diff --git a/.github/workflows/action_tools.yml b/.github/workflows/action_tools.yml index 92fe4c45227..72ea1db6bd0 100644 --- a/.github/workflows/action_tools.yml +++ b/.github/workflows/action_tools.yml @@ -8,7 +8,7 @@ on: - cron: '0 16 1 * *' push: branches: - - master + - v5.1.x paths-ignore: - documentation/** - '**/README.md' @@ -18,7 +18,7 @@ on: - '**/*.cpp' pull_request: branches: - - master + - v5.1.x paths-ignore: - documentation/** - '**/README.md' diff --git a/.github/workflows/action_utest.yml b/.github/workflows/action_utest.yml index 99690a6e488..8a5245955bd 100644 --- a/.github/workflows/action_utest.yml +++ b/.github/workflows/action_utest.yml @@ -8,14 +8,14 @@ on: - cron: '0 16 1 * *' push: branches: - - master + - v5.1.x paths-ignore: - documentation/** - '**/README.md' - '**/README_zh.md' pull_request: branches: - - master + - v5.1.x paths-ignore: - documentation/** - '**/README.md' diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml index 3bdc0c76506..7268ccf603d 100644 --- a/.github/workflows/bsp_buildings.yml +++ b/.github/workflows/bsp_buildings.yml @@ -8,14 +8,14 @@ on: - cron: '0 16 * * *' push: branches: - - master + - v5.1.x paths-ignore: - documentation/** - '**/README.md' - '**/README_zh.md' pull_request: branches: - - master + - v5.1.x paths-ignore: - documentation/** - '**/README.md' @@ -37,14 +37,17 @@ jobs: fail-fast: false matrix: legs: - - RTT_BSP: "RT-Thread Online Packages" + - RTT_BSP: "RT-Thread Online Packages (STM32F407 RT-Spark)" RTT_TOOL_CHAIN: "sourcery-arm" SUB_RTT_BSP: - "stm32/stm32f407-rt-spark" - - RTT_BSP: "RTduino/Arduino Libraries" + - RTT_BSP: "RTduino/Arduino Libraries (STM32F412 Nucleo)" RTT_TOOL_CHAIN: "sourcery-arm" SUB_RTT_BSP: - "stm32/stm32f412-st-nucleo" + - RTT_BSP: "RTduino/Arduino Libraries (Raspberry Pico)" + RTT_TOOL_CHAIN: "sourcery-arm" + SUB_RTT_BSP: - "raspberry-pico" - RTT_BSP: "others_at32_hc32" RTT_TOOL_CHAIN: "sourcery-arm" @@ -136,6 +139,7 @@ jobs: - "stm32/stm32f401-weact-blackpill" - "stm32/stm32f405-smdz-breadfruit" - "stm32/stm32f407-armfly-v5" + - "stm32/stm32f407-lckfb-skystar" - "stm32/stm32f407-atk-explorer" - "stm32/stm32f407-robomaster-c" - "stm32/stm32f407-st-discovery" @@ -176,6 +180,7 @@ jobs: - "stm32/stm32h750-artpi" - "stm32/stm32h750-weact-ministm32h7xx" - "stm32/stm32h750-fk750m1-vbt6" + - "stm32/stm32h7s7-st-disco" - "stm32/stm32mp157a-st-discovery" - "stm32/stm32mp157a-st-ev1" - "stm32/stm32u575-st-nucleo" @@ -218,6 +223,7 @@ jobs: - "renesas/ra8m1-ek" - "renesas/ra8d1-ek" - "renesas/ra8d1-vision-board" + - "renesas/rzt2m_rsk" - "frdm-k64f" - "xplorer4330/M4" - RTT_BSP: "gd32_n32_apm32" diff --git a/.github/workflows/compile_bsp_with_drivers.yml b/.github/workflows/compile_bsp_with_drivers.yml index 634eab49bb0..0062a4ac86f 100644 --- a/.github/workflows/compile_bsp_with_drivers.yml +++ b/.github/workflows/compile_bsp_with_drivers.yml @@ -15,14 +15,14 @@ name: BSP compilation with more drivers on: push: branches: - - master + - v5.1.x paths-ignore: - documentation/** - '**/README.md' - '**/README_zh.md' pull_request: branches: - - master + - v5.1.x paths-ignore: - documentation/** - '**/README.md' diff --git a/.github/workflows/doxygen.yml b/.github/workflows/doxygen.yml index 934a07eab7a..56fbd31bf73 100644 --- a/.github/workflows/doxygen.yml +++ b/.github/workflows/doxygen.yml @@ -5,14 +5,14 @@ on: - cron: '0 16 30 * *' push: branches: - - master + - v5.1.x paths-ignore: - documentation/** - '**/README.md' - '**/README_zh.md' pull_request: branches: - - master + - v5.1.x paths-ignore: - documentation/** - bsp/** diff --git a/.github/workflows/file_check.yml b/.github/workflows/file_check.yml index 2959db7e585..b4d7de3f124 100644 --- a/.github/workflows/file_check.yml +++ b/.github/workflows/file_check.yml @@ -3,7 +3,7 @@ name: Check File Format and License on: pull_request: branches: - - master + - v5.1.x paths-ignore: - documentation/** - '**/README.md' diff --git a/.github/workflows/manual_trigger_scons_except_STM32_all.yml b/.github/workflows/manual_trigger_scons_except_STM32_all.yml index 7658f948c0a..f3b4186b640 100644 --- a/.github/workflows/manual_trigger_scons_except_STM32_all.yml +++ b/.github/workflows/manual_trigger_scons_except_STM32_all.yml @@ -126,6 +126,8 @@ jobs: #- {RTT_BSP_NAME: "hk32_hk32f030c8-mini", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hk32/hk32f030c8-mini"} #scons dist有问题 - {RTT_BSP_NAME: "hpmicro_hpm6750evk", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hpmicro/hpm6750evk"} - {RTT_BSP_NAME: "hpmicro_hpm6750evkmini", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hpmicro/hpm6750evkmini"} + - {RTT_BSP_NAME: "ht32f12366", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "ht32/ht32f12366"} + - {RTT_BSP_NAME: "ht32f52352", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "ht32/ht32f52352"} #- {RTT_BSP_NAME: "imx_imx6ull-smart", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imx/imx6ull-smart"} # toolchain还没支持 - {RTT_BSP_NAME: "imx6sx_cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imx6sx/cortex-a9"} - {RTT_BSP_NAME: "imx6ul", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imx6ul"} diff --git a/.github/workflows/pkgs_test.yml b/.github/workflows/pkgs_test.yml index 87e70fb35ca..63921920139 100644 --- a/.github/workflows/pkgs_test.yml +++ b/.github/workflows/pkgs_test.yml @@ -3,14 +3,14 @@ name: pkgs_test on: push: branches: - - master + - v5.1.x paths-ignore: - documentation/** - '**/README.md' - '**/README_zh.md' pull_request: branches: - - master + - v5.1.x paths-ignore: - documentation/** - '**/README.md' diff --git a/.github/workflows/spell_check.yml b/.github/workflows/spell_check.yml index af0942c2783..c77b5f946bb 100644 --- a/.github/workflows/spell_check.yml +++ b/.github/workflows/spell_check.yml @@ -3,12 +3,12 @@ name: Check Spelling on: push: branches: - - master + - v5.1.x paths: - 'documentation/**' pull_request: branches: - - master + - v5.1.x paths: - 'documentation/**' jobs: diff --git a/.github/workflows/static_code_analysis.yml b/.github/workflows/static_code_analysis.yml index 025e458517d..8143dbd90e5 100644 --- a/.github/workflows/static_code_analysis.yml +++ b/.github/workflows/static_code_analysis.yml @@ -3,7 +3,7 @@ name: Static code analysis on: pull_request: branches: - - master + - v5.1.x paths-ignore: - documentation/** - '**/README.md' diff --git a/README.md b/README.md index 2ed689db2bb..ba3f1ab16f3 100644 --- a/README.md +++ b/README.md @@ -144,7 +144,7 @@ RT-Thread is very grateful for the support from all community developers, and if # Contribution -If you are interested in RT-Thread and want to join in the development of RT-Thread and become a code contributor,please refer to the [Code Contribution Guide](documentation/contribution_guide/contribution_guide.md). +If you are interested in RT-Thread and want to join in the development of RT-Thread and become a code contributor,please refer to the [Code Contribution Guide](.github/CONTRIBUTING.md). ## Thanks for the following contributors! diff --git a/README_de.md b/README_de.md index 5ce4b2f0105..f57408dc31e 100644 --- a/README_de.md +++ b/README_de.md @@ -144,4 +144,4 @@ RT-Thread ist sehr dankbar für die Unterstützung durch alle Entwickler der Com # Beitrag -Wenn Sie an RT-Thread interessiert sind und sich an der Entwicklung von RT-Thread beteiligen und einen Beitrag zum Code leisten wollen, lesen Sie bitte den [Code Contribution Guide](documentation/contribution_guide/contribution_guide.md). +Wenn Sie an RT-Thread interessiert sind und sich an der Entwicklung von RT-Thread beteiligen und einen Beitrag zum Code leisten wollen, lesen Sie bitte den [Code Contribution Guide](.github/CONTRIBUTING.md). diff --git a/README_es.md b/README_es.md index 82794aa034e..455dd0c30f1 100644 --- a/README_es.md +++ b/README_es.md @@ -143,4 +143,4 @@ RT-Thread está muy agradecido por el apoyo de todos los desarrolladores de la c # Contribución -Si estás interesado en RT-Thread y quieres unirte al desarrollo de RT-Thread y convertirte en un contribuidor de código, por favor consulta la [Guía de Contribución de Código.](documentation/contribution_guide/contribution_guide.md). +Si estás interesado en RT-Thread y quieres unirte al desarrollo de RT-Thread y convertirte en un contribuidor de código, por favor consulta la [Guía de Contribución de Código.](.github/CONTRIBUTING.md). diff --git a/bsp/CME_M7/project.uvproj b/bsp/CME_M7/project.uvproj index ad342552a15..af9d6f73376 100644 --- a/bsp/CME_M7/project.uvproj +++ b/bsp/CME_M7/project.uvproj @@ -543,6 +543,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1147,93 +1166,93 @@ Libraries - cmem7_efuse.c + cmem7_i2c.c 1 - StdPeriph_Driver\src\cmem7_efuse.c + StdPeriph_Driver\src\cmem7_i2c.c - cmem7_eth.c + cmem7_tim.c 1 - StdPeriph_Driver\src\cmem7_eth.c + StdPeriph_Driver\src\cmem7_tim.c - cmem7_flash.c + cmem7_wdg.c 1 - StdPeriph_Driver\src\cmem7_flash.c + StdPeriph_Driver\src\cmem7_wdg.c - cmem7_adc.c + cmem7_aes.c 1 - StdPeriph_Driver\src\cmem7_adc.c + StdPeriph_Driver\src\cmem7_aes.c - cmem7_i2c.c + cmem7_eth.c 1 - StdPeriph_Driver\src\cmem7_i2c.c + StdPeriph_Driver\src\cmem7_eth.c - cmem7_dma.c + cmem7_gpio.c 1 - StdPeriph_Driver\src\cmem7_dma.c + StdPeriph_Driver\src\cmem7_gpio.c - cmem7_gpio.c + cmem7_spi.c 1 - StdPeriph_Driver\src\cmem7_gpio.c + StdPeriph_Driver\src\cmem7_spi.c - cmem7_misc.c + cmem7_dma.c 1 - StdPeriph_Driver\src\cmem7_misc.c + StdPeriph_Driver\src\cmem7_dma.c - cmem7_wdg.c + cmem7_rtc.c 1 - StdPeriph_Driver\src\cmem7_wdg.c + StdPeriph_Driver\src\cmem7_rtc.c - cmem7_rtc.c + cmem7_uart.c 1 - StdPeriph_Driver\src\cmem7_rtc.c + StdPeriph_Driver\src\cmem7_uart.c - cmem7_can.c + cmem7_flash.c 1 - StdPeriph_Driver\src\cmem7_can.c + StdPeriph_Driver\src\cmem7_flash.c - cmem7_tim.c + cmem7_can.c 1 - StdPeriph_Driver\src\cmem7_tim.c + StdPeriph_Driver\src\cmem7_can.c - cmem7_spi.c + cmem7_usb.c 1 - StdPeriph_Driver\src\cmem7_spi.c + StdPeriph_Driver\src\cmem7_usb.c @@ -1245,23 +1264,23 @@ - cmem7_aes.c + cmem7_adc.c 1 - StdPeriph_Driver\src\cmem7_aes.c + StdPeriph_Driver\src\cmem7_adc.c - cmem7_usb.c + cmem7_efuse.c 1 - StdPeriph_Driver\src\cmem7_usb.c + StdPeriph_Driver\src\cmem7_efuse.c - cmem7_uart.c + cmem7_misc.c 1 - StdPeriph_Driver\src\cmem7_uart.c + StdPeriph_Driver\src\cmem7_misc.c diff --git a/bsp/ESP32_C3/drivers/drv_gpio.c b/bsp/ESP32_C3/drivers/drv_gpio.c index f09f45dc930..4a4aa978ff6 100644 --- a/bsp/ESP32_C3/drivers/drv_gpio.c +++ b/bsp/ESP32_C3/drivers/drv_gpio.c @@ -21,9 +21,9 @@ static void mcu_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) /*TODO:set gpio out put mode */ } -static rt_int8_t mcu_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t mcu_pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value; + rt_ssize_t value; value = gpio_get_level(pin); return value; } diff --git a/bsp/Infineon/libraries/HAL_Drivers/drv_gpio.c b/bsp/Infineon/libraries/HAL_Drivers/drv_gpio.c index 1fd09c1cd43..e1a8f0ee81e 100644 --- a/bsp/Infineon/libraries/HAL_Drivers/drv_gpio.c +++ b/bsp/Infineon/libraries/HAL_Drivers/drv_gpio.c @@ -150,7 +150,7 @@ static void ifx_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) cyhal_gpio_write(gpio_pin, value); } -static rt_int8_t ifx_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t ifx_pin_read(struct rt_device *device, rt_base_t pin) { rt_uint16_t gpio_pin; @@ -160,7 +160,7 @@ static rt_int8_t ifx_pin_read(struct rt_device *device, rt_base_t pin) } else { - return -RT_ERROR; + return -RT_EINVAL; } return cyhal_gpio_read(gpio_pin); diff --git a/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvproj b/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvproj index 51f96880420..177734ce465 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvproj +++ b/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1093,13 +1112,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_clock.c - - - psoc6_03_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c - - cy_scb_uart.c @@ -1149,6 +1161,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_sema.c + + + psoc6_03_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c + + cyhal_utils.c @@ -1191,13 +1210,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_lptimer.c - - - psoc6_01_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c - - cy_prot.c @@ -1226,13 +1238,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysint.c - - - psoc6_04_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c - - cyhal_triggers_psoc6_01.c @@ -1242,16 +1247,16 @@ - cyhal_syspm.c + psoc6_01_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c - psoc6_02_cm0p_sleep.c + cyhal_syspm.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c @@ -1282,6 +1287,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c + + + psoc6_04_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c + + cy_flash.c @@ -1289,6 +1301,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_flash.c + + + psoc6_02_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + + cy_ble_clk.c @@ -1315,58 +1334,58 @@ libs - cycfg_routing.c + cycfg_qspi_memslot.c 1 - libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_routing.c + libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_qspi_memslot.c - cycfg_clocks.c + cycfg.c 1 - libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_clocks.c + libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg.c - cycfg_qspi_memslot.c + cycfg_routing.c 1 - libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_qspi_memslot.c + libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_routing.c - cybsp.c + cycfg_capsense.c 1 - libs\TARGET_CY8CKIT-062-BLE\cybsp.c + libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_capsense.c - cycfg.c + cycfg_clocks.c 1 - libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg.c + libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_clocks.c - cycfg_capsense.c + cycfg_peripherals.c 1 - libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_capsense.c + libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_peripherals.c - startup_psoc6_01_cm4.S - 2 - libs\TARGET_CY8CKIT-062-BLE\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_01_cm4.S + cycfg_system.c + 1 + libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_system.c - cycfg_system.c - 1 - libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_system.c + startup_psoc6_01_cm4.S + 2 + libs\TARGET_CY8CKIT-062-BLE\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_01_cm4.S @@ -1385,9 +1404,9 @@ - cycfg_peripherals.c + cybsp.c 1 - libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_peripherals.c + libs\TARGET_CY8CKIT-062-BLE\cybsp.c diff --git a/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvprojx b/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvprojx index ab1c6366996..c1ec39d859f 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvprojx +++ b/bsp/Infineon/psoc6-cy8ckit-062-BLE/project.uvprojx @@ -487,6 +487,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1130,16 +1149,16 @@ - cy_ipc_drv.c + psoc6_02_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_drv.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c - psoc6_01_cm0p_sleep.c + cy_ipc_drv.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_drv.c @@ -1156,6 +1175,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syslib.c + + + psoc6_04_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c + + cy_ipc_pipe.c @@ -1193,9 +1219,9 @@ - psoc6_03_cm0p_sleep.c + psoc6_01_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c @@ -1219,13 +1245,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c - - - psoc6_02_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c - - cy_systick.c @@ -1263,9 +1282,9 @@ - psoc6_04_cm0p_sleep.c + psoc6_03_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c @@ -1292,20 +1311,6 @@ libs - - - cycfg_capsense.c - 1 - libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_capsense.c - - - - - cycfg_qspi_memslot.c - 1 - libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_qspi_memslot.c - - system_psoc6_cm4.c @@ -1322,30 +1327,30 @@ - cycfg_peripherals.c + cycfg.c 1 - libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_peripherals.c + libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg.c - cycfg.c + cycfg_clocks.c 1 - libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg.c + libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_clocks.c - cycfg_routing.c + cybsp.c 1 - libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_routing.c + libs\TARGET_CY8CKIT-062-BLE\cybsp.c - cycfg_clocks.c + cycfg_capsense.c 1 - libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_clocks.c + libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_capsense.c @@ -1357,9 +1362,9 @@ - cybsp.c + cycfg_peripherals.c 1 - libs\TARGET_CY8CKIT-062-BLE\cybsp.c + libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_peripherals.c @@ -1369,6 +1374,20 @@ libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_pins.c + + + cycfg_routing.c + 1 + libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_routing.c + + + + + cycfg_qspi_memslot.c + 1 + libs\TARGET_CY8CKIT-062-BLE\config\GeneratedSource\cycfg_qspi_memslot.c + + diff --git a/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvproj b/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvproj index db26d3f9d77..b66c62fe666 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvproj +++ b/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1086,6 +1105,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_scb_common.c + + + psoc6_02_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + + cyhal_clock.c @@ -1093,6 +1119,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_clock.c + + + psoc6_01_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c + + cy_scb_uart.c @@ -1114,13 +1147,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils_impl.c - - - psoc6_02_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c - - cyhal_gpio.c @@ -1142,6 +1168,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_sema.c + + + psoc6_04_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c + + cyhal_utils.c @@ -1184,13 +1217,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_lptimer.c - - - psoc6_03_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c - - cy_prot.c @@ -1247,13 +1273,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\source\pin_packages\cyhal_psoc6_01_124_bga.c - - - psoc6_01_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c - - cyhal_interconnect.c @@ -1284,16 +1303,16 @@ - cy_syspm.c + psoc6_03_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syspm.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c - psoc6_04_cm0p_sleep.c + cy_syspm.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syspm.c @@ -1308,86 +1327,86 @@ libs - cycfg_routing.c + cycfg_system.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_routing.c + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_system.c - cycfg_connectivity_bt.c + cybsp.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_connectivity_bt.c + libs\TARGET_CY8CKIT-062-WIFI-BT\cybsp.c - cycfg_pins.c + system_psoc6_cm4.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_pins.c + libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\system_psoc6_cm4.c - cycfg_qspi_memslot.c + cycfg_pins.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_qspi_memslot.c + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_pins.c - cycfg.c + cycfg_clocks.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg.c + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_clocks.c - startup_psoc6_01_cm4.s - 2 - libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_01_cm4.s + cycfg_qspi_memslot.c + 1 + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_qspi_memslot.c - system_psoc6_cm4.c + cycfg_connectivity_bt.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\system_psoc6_cm4.c + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_connectivity_bt.c - cybsp.c + cycfg_capsense.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\cybsp.c + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_capsense.c - cycfg_system.c + cycfg_peripherals.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_system.c + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_peripherals.c - cycfg_clocks.c + cycfg_routing.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_clocks.c + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_routing.c - cycfg_capsense.c - 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_capsense.c + startup_psoc6_01_cm4.s + 2 + libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_01_cm4.s - cycfg_peripherals.c + cycfg.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_peripherals.c + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg.c diff --git a/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvprojx b/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvprojx index 802886c109a..93441081eeb 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvprojx +++ b/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1050,13 +1069,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_gpio.c - - - psoc6_01_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c - - cyhal_irq_impl.c @@ -1078,6 +1090,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_clock.c + + + psoc6_02_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + + cy_scb_uart.c @@ -1099,13 +1118,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils_impl.c - - - psoc6_03_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c - - cyhal_gpio.c @@ -1129,30 +1141,30 @@ - psoc6_04_cm0p_sleep.c + psoc6_03_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c - psoc6_02_cm0p_sleep.c + cyhal_utils.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils.c - cyhal_utils.c + cy_ipc_drv.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils.c + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_drv.c - cy_ipc_drv.c + psoc6_04_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_drv.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c @@ -1267,6 +1279,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_flash.c + + + psoc6_01_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c + + cy_syspm.c @@ -1286,23 +1305,23 @@ libs - cybsp.c + cycfg_peripherals.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\cybsp.c + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_peripherals.c - cycfg_peripherals.c + cycfg_system.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_peripherals.c + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_system.c - cycfg_system.c + cycfg_routing.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_system.c + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_routing.c @@ -1314,9 +1333,9 @@ - cycfg_routing.c + cycfg.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_routing.c + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg.c @@ -1328,44 +1347,44 @@ - cycfg_connectivity_bt.c + cycfg_capsense.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_connectivity_bt.c + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_capsense.c - cycfg.c + system_psoc6_cm4.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg.c + libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\system_psoc6_cm4.c - cycfg_capsense.c + cybsp.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_capsense.c + libs\TARGET_CY8CKIT-062-WIFI-BT\cybsp.c - startup_psoc6_01_cm4.s - 2 - libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_01_cm4.s + cycfg_clocks.c + 1 + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_clocks.c - system_psoc6_cm4.c - 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\system_psoc6_cm4.c + startup_psoc6_01_cm4.s + 2 + libs\TARGET_CY8CKIT-062-WIFI-BT\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_01_cm4.s - cycfg_clocks.c + cycfg_connectivity_bt.c 1 - libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_clocks.c + libs\TARGET_CY8CKIT-062-WIFI-BT\config\GeneratedSource\cycfg_connectivity_bt.c diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvproj b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvproj index 2e8318d7fe7..b3024717b8a 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvproj +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1109,9 +1128,9 @@ - psoc6_02_cm0p_sleep.c + cy_scb_uart.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_scb_uart.c @@ -1123,9 +1142,9 @@ - cy_scb_uart.c + psoc6_03_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_scb_uart.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c @@ -1142,13 +1161,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils_impl.c - - - psoc6_03_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c - - cyhal_gpio.c @@ -1198,13 +1210,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syslib.c - - - psoc6_04_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c - - cy_ipc_pipe.c @@ -1261,6 +1266,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_systick.c + + + psoc6_04_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c + + cyhal_interconnect.c @@ -1282,6 +1294,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c + + + psoc6_02_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + + psoc6_01_cm0p_sleep.c @@ -1308,16 +1327,16 @@ libs - cycfg_pins.c + cycfg_capsense.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_pins.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_capsense.c - cycfg_system.c - 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_system.c + startup_psoc6_02_cm4.S + 2 + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S @@ -1329,65 +1348,65 @@ - startup_psoc6_02_cm4.S - 2 - libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S + cycfg_connectivity_bt.c + 1 + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_connectivity_bt.c - system_psoc6_cm4.c + cycfg.c 1 - libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\system_psoc6_cm4.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg.c - cycfg_capsense.c + cycfg_routing.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_capsense.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_routing.c - cycfg_routing.c + cycfg_peripherals.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_routing.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_peripherals.c - cycfg_clocks.c + cycfg_pins.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_clocks.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_pins.c - cycfg.c + cycfg_system.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_system.c - cycfg_connectivity_bt.c + cycfg_clocks.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_connectivity_bt.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_clocks.c - cycfg_qspi_memslot.c + system_psoc6_cm4.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_qspi_memslot.c + libs\TARGET_CY8CKIT-062S2-43012\COMPONENT_CM4\system_psoc6_cm4.c - cycfg_peripherals.c + cycfg_qspi_memslot.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_peripherals.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_qspi_memslot.c diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvprojx b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvprojx index a2bdc271d7f..f6c8fe33b9d 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvprojx +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1078,6 +1097,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_scb_common.c + + + psoc6_02_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + + cyhal_clock.c @@ -1169,6 +1195,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syslib.c + + + psoc6_03_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c + + cy_ipc_pipe.c @@ -1213,23 +1246,23 @@ - cyhal_syspm.c + psoc6_04_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c - cy_systick.c + cyhal_syspm.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_systick.c + ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c - psoc6_04_cm0p_sleep.c + cy_systick.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_systick.c @@ -1253,20 +1286,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c - - - psoc6_03_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c - - - - - psoc6_02_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c - - cy_syspm.c @@ -1286,23 +1305,23 @@ libs - cycfg_connectivity_bt.c + cycfg.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_connectivity_bt.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg.c - cycfg_routing.c + cycfg_peripherals.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_routing.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_peripherals.c - cycfg_qspi_memslot.c + cycfg_capsense.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_qspi_memslot.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_capsense.c @@ -1314,23 +1333,23 @@ - cycfg_peripherals.c + cycfg_clocks.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_peripherals.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_clocks.c - cycfg_system.c + cycfg_qspi_memslot.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_system.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_qspi_memslot.c - cybsp.c + cycfg_system.c 1 - libs\TARGET_CY8CKIT-062S2-43012\cybsp.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_system.c @@ -1342,9 +1361,9 @@ - cycfg.c + cycfg_connectivity_bt.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_connectivity_bt.c @@ -1356,16 +1375,16 @@ - cycfg_clocks.c + cycfg_routing.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_clocks.c + libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_routing.c - cycfg_capsense.c + cybsp.c 1 - libs\TARGET_CY8CKIT-062S2-43012\config\GeneratedSource\cycfg_capsense.c + libs\TARGET_CY8CKIT-062S2-43012\cybsp.c diff --git a/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvproj b/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvproj index d83ee73212c..6f0062e7643 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvproj +++ b/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1058,6 +1077,20 @@ Libraries + + + psoc6_01_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c + + + + + psoc6_03_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c + + cy_retarget_io.c @@ -1163,13 +1196,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils.c - - - psoc6_04_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c - - cy_ipc_drv.c @@ -1191,6 +1217,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syslib.c + + + psoc6_02_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + + cy_ipc_pipe.c @@ -1233,13 +1266,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysint.c - - - psoc6_01_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c - - cyhal_syspm.c @@ -1254,13 +1280,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_systick.c - - - psoc6_03_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c - - cyhal_interconnect.c @@ -1284,16 +1303,16 @@ - cy_flash.c + psoc6_04_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_flash.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c - psoc6_02_cm0p_sleep.c + cy_flash.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_flash.c @@ -1322,23 +1341,16 @@ libs - cycfg_pins.c - 1 - libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_pins.c - - - - - cycfg_qspi_memslot.c + cycfg.c 1 - libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_qspi_memslot.c + libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg.c - cycfg_system.c + cycfg_routing.c 1 - libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_system.c + libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_routing.c @@ -1350,16 +1362,16 @@ - system_psoc6_cm4.c + cycfg_pins.c 1 - libs\TARGET_CY8CKIT-062S4\COMPONENT_CM4\system_psoc6_cm4.c + libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_pins.c - cycfg_peripherals.c + cycfg_capsense.c 1 - libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_peripherals.c + libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_capsense.c @@ -1371,16 +1383,23 @@ - cycfg_capsense.c + cycfg_qspi_memslot.c 1 - libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_capsense.c + libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_qspi_memslot.c - cycfg_routing.c + system_psoc6_cm4.c 1 - libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_routing.c + libs\TARGET_CY8CKIT-062S4\COMPONENT_CM4\system_psoc6_cm4.c + + + + + cycfg_peripherals.c + 1 + libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_peripherals.c @@ -1392,9 +1411,9 @@ - cycfg.c + cycfg_system.c 1 - libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg.c + libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_system.c diff --git a/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvprojx b/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvprojx index 51e6d217c7b..204ec0a4307 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvprojx +++ b/bsp/Infineon/psoc6-cy8ckit-062s4/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1043,6 +1062,13 @@ ..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c + + + psoc6_04_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c + + cy_scb_i2c.c @@ -1087,23 +1113,16 @@ - psoc6_01_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c - - - - - psoc6_03_cm0p_sleep.c + cy_scb_uart.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_scb_uart.c - cy_scb_uart.c + psoc6_01_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_scb_uart.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c @@ -1127,6 +1146,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_gpio.c + + + psoc6_03_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c + + cyhal_system.c @@ -1162,13 +1188,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_drv.c - - - psoc6_04_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c - - cyhal_hwmgr.c @@ -1262,23 +1281,23 @@ - cy_flash.c + psoc6_02_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_flash.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c - cy_ble_clk.c + cy_flash.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ble_clk.c + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_flash.c - psoc6_02_cm0p_sleep.c + cy_ble_clk.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ble_clk.c @@ -1298,13 +1317,6 @@ libs - - - cycfg_clocks.c - 1 - libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_clocks.c - - cycfg_routing.c @@ -1314,23 +1326,23 @@ - cycfg_system.c + cycfg_capsense.c 1 - libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_system.c + libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_capsense.c - cybsp.c + cycfg.c 1 - libs\TARGET_CY8CKIT-062S4\cybsp.c + libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg.c - cycfg_capsense.c + cycfg_clocks.c 1 - libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_capsense.c + libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_clocks.c @@ -1340,6 +1352,20 @@ libs\TARGET_CY8CKIT-062S4\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_04_cm4.S + + + cybsp.c + 1 + libs\TARGET_CY8CKIT-062S4\cybsp.c + + + + + cycfg_pins.c + 1 + libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_pins.c + + cycfg_peripherals.c @@ -1363,16 +1389,9 @@ - cycfg_pins.c - 1 - libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_pins.c - - - - - cycfg.c + cycfg_system.c 1 - libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg.c + libs\TARGET_CY8CKIT-062S4\config\GeneratedSource\cycfg_system.c diff --git a/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvproj b/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvproj index 1745503c534..8e98bdeb5c9 100644 --- a/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvproj +++ b/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1100,6 +1119,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_scb_common.c + + + psoc6_02_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + + cyhal_clock.c @@ -1151,23 +1177,16 @@ - psoc6_04_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c - - - - - psoc6_01_cm0p_sleep.c + cyhal_utils.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils.c - cyhal_utils.c + psoc6_03_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c @@ -1191,6 +1210,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syslib.c + + + psoc6_04_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c + + cy_ipc_pipe.c @@ -1240,13 +1266,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c - - - psoc6_03_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c - - cy_systick.c @@ -1284,9 +1303,9 @@ - psoc6_02_cm0p_sleep.c + psoc6_01_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c @@ -1308,16 +1327,23 @@ libs - cycfg_qspi_memslot.c + cycfg_clocks.c 1 - libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_qspi_memslot.c + libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_clocks.c - cycfg_clocks.c + cycfg_routing.c 1 - libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_clocks.c + libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_routing.c + + + + + cycfg_qspi_memslot.c + 1 + libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_qspi_memslot.c @@ -1341,13 +1367,6 @@ libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_system.c - - - cycfg_connectivity_bt.c - 1 - libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_connectivity_bt.c - - cycfg_peripherals.c @@ -1357,37 +1376,37 @@ - cycfg_routing.c + cybsp.c 1 - libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_routing.c + libs\TARGET_CY8CPROTO-062S3-4343W\cybsp.c - system_psoc6_cm4.c + cycfg_connectivity_bt.c 1 - libs\TARGET_CY8CPROTO-062S3-4343W\COMPONENT_CM4\system_psoc6_cm4.c + libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_connectivity_bt.c - cybsp.c + cycfg_capsense.c 1 - libs\TARGET_CY8CPROTO-062S3-4343W\cybsp.c + libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_capsense.c - cycfg_pins.c + system_psoc6_cm4.c 1 - libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_pins.c + libs\TARGET_CY8CPROTO-062S3-4343W\COMPONENT_CM4\system_psoc6_cm4.c - cycfg_capsense.c + cycfg_pins.c 1 - libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_capsense.c + libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_pins.c diff --git a/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvprojx b/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvprojx index 61f319b3ba8..acdff3e7e51 100644 --- a/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvprojx +++ b/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1036,6 +1055,13 @@ Libraries + + + psoc6_03_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c + + cyhal_triggers_psoc6_03.c @@ -1045,9 +1071,16 @@ - psoc6_04_cm0p_sleep.c + psoc6_02_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + + + + + cy_retarget_io.c + 1 + ..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c @@ -1092,13 +1125,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_scb_uart.c - - - psoc6_02_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c - - cy_scb_common.c @@ -1134,13 +1160,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_sema.c - - - cy_retarget_io.c - 1 - ..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c - - cyhal_utils.c @@ -1183,6 +1202,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_lptimer.c + + + psoc6_04_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c + + cy_prot.c @@ -1206,16 +1232,16 @@ - psoc6_03_cm0p_sleep.c + cy_sysint.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysint.c - cy_sysint.c + psoc6_01_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysint.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c @@ -1260,13 +1286,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c - - - psoc6_01_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c - - cy_syspm.c @@ -1286,44 +1305,44 @@ libs - cybsp.c + cycfg_pins.c 1 - libs\TARGET_CY8CPROTO-062S3-4343W\cybsp.c + libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_pins.c - cycfg_system.c - 1 - libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_system.c + startup_psoc6_03_cm4.S + 2 + libs\TARGET_CY8CPROTO-062S3-4343W\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_03_cm4.S - cycfg.c + cybsp.c 1 - libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg.c + libs\TARGET_CY8CPROTO-062S3-4343W\cybsp.c - cycfg_clocks.c + cycfg_qspi_memslot.c 1 - libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_clocks.c + libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_qspi_memslot.c - cycfg_qspi_memslot.c + system_psoc6_cm4.c 1 - libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_qspi_memslot.c + libs\TARGET_CY8CPROTO-062S3-4343W\COMPONENT_CM4\system_psoc6_cm4.c - cycfg_peripherals.c + cycfg_routing.c 1 - libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_peripherals.c + libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_routing.c @@ -1335,16 +1354,16 @@ - startup_psoc6_03_cm4.S - 2 - libs\TARGET_CY8CPROTO-062S3-4343W\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_03_cm4.S + cycfg_system.c + 1 + libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_system.c - cycfg_pins.c + cycfg_clocks.c 1 - libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_pins.c + libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_clocks.c @@ -1356,16 +1375,16 @@ - cycfg_routing.c + cycfg.c 1 - libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_routing.c + libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg.c - system_psoc6_cm4.c + cycfg_peripherals.c 1 - libs\TARGET_CY8CPROTO-062S3-4343W\COMPONENT_CM4\system_psoc6_cm4.c + libs\TARGET_CY8CPROTO-062S3-4343W\config\GeneratedSource\cycfg_peripherals.c diff --git a/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvproj b/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvproj index 1ef03d4cb05..306b0209373 100644 --- a/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvproj +++ b/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1086,13 +1105,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_gpio.c - - - psoc6_03_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c - - cyhal_irq_impl.c @@ -1156,6 +1168,20 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_sema.c + + + psoc6_03_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c + + + + + psoc6_02_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + + psoc6_01_cm0p_sleep.c @@ -1205,6 +1231,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_lptimer.c + + + psoc6_04_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c + + cy_prot.c @@ -1233,13 +1266,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysint.c - - - psoc6_04_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c - - cyhal_syspm.c @@ -1282,13 +1308,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c - - - psoc6_02_cm0p_sleep.c - 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c - - cy_syspm.c @@ -1306,13 +1325,6 @@ libs - - - cycfg_connectivity_bt.c - 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_connectivity_bt.c - - cybsp.c @@ -1322,44 +1334,44 @@ - cycfg_qspi_memslot.c + cycfg_capsense.c 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_qspi_memslot.c + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_capsense.c - cycfg_system.c + system_psoc6_cm4.c 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_system.c + libs\TARGET_RTT-062S2\COMPONENT_CM4\system_psoc6_cm4.c - cycfg_peripherals.c - 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_peripherals.c + startup_psoc6_02_cm4.S + 2 + libs\TARGET_RTT-062S2\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S - system_psoc6_cm4.c + cycfg_connectivity_bt.c 1 - libs\TARGET_RTT-062S2\COMPONENT_CM4\system_psoc6_cm4.c + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_connectivity_bt.c - startup_psoc6_02_cm4.S - 2 - libs\TARGET_RTT-062S2\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S + cycfg_pins.c + 1 + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_pins.c - cycfg_capsense.c + cycfg_peripherals.c 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_capsense.c + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_peripherals.c @@ -1371,16 +1383,16 @@ - cycfg_pins.c + cycfg_routing.c 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_pins.c + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_routing.c - cycfg_routing.c + cycfg_qspi_memslot.c 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_routing.c + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_qspi_memslot.c @@ -1390,6 +1402,13 @@ libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg.c + + + cycfg_system.c + 1 + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_system.c + + diff --git a/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvprojx b/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvprojx index 7678f8d16b1..a3778c2b8bc 100644 --- a/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvprojx +++ b/bsp/Infineon/psoc6-evaluationkit-062S2/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1045,9 +1064,9 @@ - psoc6_03_cm0p_sleep.c + cy_retarget_io.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c @@ -1108,16 +1127,16 @@ - psoc6_04_cm0p_sleep.c + cyhal_gpio.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_gpio.c - cyhal_gpio.c + psoc6_02_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_gpio.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c @@ -1134,13 +1153,6 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_sema.c - - - cy_retarget_io.c - 1 - ..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c - - cyhal_utils.c @@ -1206,44 +1218,44 @@ - cy_sysint.c + psoc6_04_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysint.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c - cyhal_syspm.c + cy_sysint.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysint.c - cyhal_psoc6_02_68_qfn.c + psoc6_01_cm0p_sleep.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\source\pin_packages\cyhal_psoc6_02_68_qfn.c + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c - psoc6_01_cm0p_sleep.c + cyhal_syspm.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c - cy_systick.c + cyhal_psoc6_02_68_qfn.c 1 - ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_systick.c + ..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\source\pin_packages\cyhal_psoc6_02_68_qfn.c - psoc6_02_cm0p_sleep.c + cy_systick.c 1 - ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c + ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_systick.c @@ -1267,6 +1279,13 @@ ..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c + + + psoc6_03_cm0p_sleep.c + 1 + ..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c + + cy_syspm.c @@ -1293,37 +1312,37 @@ - cycfg_clocks.c + cycfg_routing.c 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_clocks.c + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_routing.c - cycfg_capsense.c + system_psoc6_cm4.c 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_capsense.c + libs\TARGET_RTT-062S2\COMPONENT_CM4\system_psoc6_cm4.c - system_psoc6_cm4.c + cycfg_capsense.c 1 - libs\TARGET_RTT-062S2\COMPONENT_CM4\system_psoc6_cm4.c + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_capsense.c - cycfg_system.c + cycfg_pins.c 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_system.c + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_pins.c - cycfg_qspi_memslot.c + cycfg_system.c 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_qspi_memslot.c + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_system.c @@ -1335,37 +1354,37 @@ - cycfg_peripherals.c + cycfg_qspi_memslot.c 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_peripherals.c + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_qspi_memslot.c - cycfg_routing.c + cycfg_peripherals.c 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_routing.c + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_peripherals.c - cycfg_pins.c + cycfg.c 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_pins.c + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg.c - cycfg_connectivity_bt.c + cycfg_clocks.c 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_connectivity_bt.c + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_clocks.c - cycfg.c + cycfg_connectivity_bt.c 1 - libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg.c + libs\TARGET_RTT-062S2\config\GeneratedSource\cycfg_connectivity_bt.c diff --git a/bsp/Vango/v85xx/drivers/drv_gpio.c b/bsp/Vango/v85xx/drivers/drv_gpio.c index 4caf5b9bccc..11d7454841a 100644 --- a/bsp/Vango/v85xx/drivers/drv_gpio.c +++ b/bsp/Vango/v85xx/drivers/drv_gpio.c @@ -140,11 +140,11 @@ static void v85xx_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t v85xx_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t v85xx_pin_read(rt_device_t dev, rt_base_t pin) { GPIO_TypeDef *gpio_port; uint16_t gpio_pin; - int value = PIN_LOW; + rt_ssize_t value = PIN_LOW; if (PIN_PORT(pin) == PIN_V85XXPORT_A) { @@ -157,6 +157,10 @@ static rt_int8_t v85xx_pin_read(rt_device_t dev, rt_base_t pin) gpio_pin = PIN_V85XXPIN(pin); value = GPIOBToF_ReadInputDataBit(gpio_port, gpio_pin); } + else + { + return -RT_EINVAL; + } return value; } diff --git a/bsp/Vango/v85xx/project.uvprojx b/bsp/Vango/v85xx/project.uvprojx index 871cd8c3546..5044c86edbe 100644 --- a/bsp/Vango/v85xx/project.uvprojx +++ b/bsp/Vango/v85xx/project.uvprojx @@ -483,6 +483,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1059,9 +1078,16 @@ Vango_Lib - lib_wdt.c + lib_misc.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_wdt.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_misc.c + + + + + lib_tmr.c + 1 + Libraries\VangoV85xx_standard_peripheral\Source\lib_tmr.c @@ -1073,79 +1099,79 @@ - lib_i2c.c + lib_LoadNVR.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_i2c.c + Libraries\CMSIS\Vango\V85xx\Source\lib_LoadNVR.c - lib_cortex.c + lib_flash.c 1 - Libraries\CMSIS\Vango\V85xx\Source\lib_cortex.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_flash.c - lib_ana.c + lib_rtc.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_ana.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_rtc.c - lib_LoadNVR.c + lib_u32k.c 1 - Libraries\CMSIS\Vango\V85xx\Source\lib_LoadNVR.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_u32k.c - lib_comp.c + lib_dma.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_comp.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_dma.c - lib_misc.c + lib_clk.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_misc.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_clk.c - lib_tmr.c + lib_gpio.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_tmr.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_gpio.c - lib_iso7816.c + lib_CodeRAM.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_iso7816.c + Libraries\CMSIS\Vango\V85xx\Source\lib_CodeRAM.c - lib_adc_tiny.c + lib_crypt.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_adc_tiny.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_crypt.c - lib_CodeRAM.c + lib_lcd.c 1 - Libraries\CMSIS\Vango\V85xx\Source\lib_CodeRAM.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_lcd.c - lib_u32k.c + lib_uart.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_u32k.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_uart.c @@ -1157,37 +1183,30 @@ - lib_rtc.c - 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_rtc.c - - - - - lib_flash.c + lib_adc_tiny.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_flash.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_adc_tiny.c - lib_lcd.c + lib_version.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_lcd.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_version.c - lib_uart.c + lib_iso7816.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_uart.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_iso7816.c - lib_crypt.c + lib_cortex.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_crypt.c + Libraries\CMSIS\Vango\V85xx\Source\lib_cortex.c @@ -1199,51 +1218,51 @@ - lib_spi.c + lib_adc.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_spi.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_adc.c - lib_pmu.c + lib_comp.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_pmu.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_comp.c - lib_clk.c + lib_spi.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_clk.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_spi.c - lib_dma.c + lib_wdt.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_dma.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_wdt.c - lib_version.c + lib_pmu.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_version.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_pmu.c - lib_adc.c + lib_i2c.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_adc.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_i2c.c - lib_gpio.c + lib_ana.c 1 - Libraries\VangoV85xx_standard_peripheral\Source\lib_gpio.c + Libraries\VangoV85xx_standard_peripheral\Source\lib_ana.c diff --git a/bsp/Vango/v85xxp/drivers/drv_gpio.c b/bsp/Vango/v85xxp/drivers/drv_gpio.c index dcb57e0dd5b..4b7f2fdfcf4 100644 --- a/bsp/Vango/v85xxp/drivers/drv_gpio.c +++ b/bsp/Vango/v85xxp/drivers/drv_gpio.c @@ -141,11 +141,11 @@ static void V85XXP_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t V85XXP_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t V85XXP_pin_read(rt_device_t dev, rt_base_t pin) { GPIO_Type *gpio_port; uint16_t gpio_pin; - int value = PIN_LOW; + rt_ssize_t value = PIN_LOW; if (PIN_PORT(pin) == PIN_V85XXPPORT_A) { diff --git a/bsp/Vango/v85xxp/project.uvprojx b/bsp/Vango/v85xxp/project.uvprojx index 1af4617310e..bd682a6c7e6 100644 --- a/bsp/Vango/v85xxp/project.uvprojx +++ b/bsp/Vango/v85xxp/project.uvprojx @@ -483,6 +483,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1052,142 +1071,142 @@ Vango_Lib - lib_adc_tiny.c + lib_version.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_adc_tiny.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_version.c - lib_uart.c + lib_cmp.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_uart.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_cmp.c - lib_wdt.c + lib_iso7816.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_wdt.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_iso7816.c - lib_lcd.c + lib_misc.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_lcd.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_misc.c - lib_adc.c + lib_uart.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_adc.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_uart.c - lib_flash.c + lib_tmr.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_flash.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_tmr.c - lib_misc.c + lib_adc.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_misc.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_adc.c - lib_spi.c + lib_flash.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_spi.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_flash.c - lib_ana.c + lib_gpio.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_ana.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_gpio.c - lib_tmr.c + lib_cortex.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_tmr.c + Libraries\CMSIS\Vango\V85xxP\Source\lib_cortex.c - lib_cortex.c + lib_crypt.c 1 - Libraries\CMSIS\Vango\V85xxP\Source\lib_cortex.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_crypt.c - lib_cmp.c + lib_clk.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_cmp.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_clk.c - lib_crypt.c + lib_pwm.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_crypt.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_pwm.c - lib_dma.c + lib_adc_tiny.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_dma.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_adc_tiny.c - lib_pwm.c + lib_pmu.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_pwm.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_pmu.c - lib_clk.c + lib_lcd.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_clk.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_lcd.c - lib_gpio.c + lib_wdt.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_gpio.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_wdt.c - lib_pmu.c + system_target.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_pmu.c + Libraries\CMSIS\Vango\V85xxP\Source\system_target.c - lib_u32k.c + lib_i2c.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_u32k.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_i2c.c - lib_i2c.c + lib_rtc.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_i2c.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_rtc.c @@ -1199,16 +1218,23 @@ - lib_rtc.c + lib_spi.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_rtc.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_spi.c - lib_iso7816.c + lib_dma.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_iso7816.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_dma.c + + + + + lib_u32k.c + 1 + Libraries\VangoV85xxP_standard_peripheral\Source\lib_u32k.c @@ -1227,16 +1253,9 @@ - system_target.c - 1 - Libraries\CMSIS\Vango\V85xxP\Source\system_target.c - - - - - lib_version.c + lib_ana.c 1 - Libraries\VangoV85xxP_standard_peripheral\Source\lib_version.c + Libraries\VangoV85xxP_standard_peripheral\Source\lib_ana.c diff --git a/bsp/acm32/acm32f0x0-nucleo/drivers/drv_gpio.c b/bsp/acm32/acm32f0x0-nucleo/drivers/drv_gpio.c index 000f60397a4..8bddf41ed02 100644 --- a/bsp/acm32/acm32f0x0-nucleo/drivers/drv_gpio.c +++ b/bsp/acm32/acm32f0x0-nucleo/drivers/drv_gpio.c @@ -188,7 +188,7 @@ static void acm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) HAL_GPIO_WritePin(index->gpio, index->pin, (enum_PinState_t)value); } -static rt_int8_t acm32_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t acm32_pin_read(rt_device_t dev, rt_base_t pin) { int value; const struct pin_index *index; @@ -198,7 +198,7 @@ static rt_int8_t acm32_pin_read(rt_device_t dev, rt_base_t pin) index = get_pin(pin); if (index == RT_NULL) { - return value; + return -RT_EINVAL; } value = HAL_GPIO_ReadPin(index->gpio, index->pin); diff --git a/bsp/acm32/acm32f0x0-nucleo/drivers/drv_pm.c b/bsp/acm32/acm32f0x0-nucleo/drivers/drv_pm.c index 63150e4063f..e431e467e1e 100644 --- a/bsp/acm32/acm32f0x0-nucleo/drivers/drv_pm.c +++ b/bsp/acm32/acm32f0x0-nucleo/drivers/drv_pm.c @@ -135,7 +135,7 @@ static rt_tick_t _pm_timer_get_tick(struct rt_pm *pm) { rt_tick_t tick; RT_ASSERT(pm != RT_NULL); - + tick = 1; return get_os_tick_from_pm_tick(tick); diff --git a/bsp/acm32/acm32f0x0-nucleo/project.ewp b/bsp/acm32/acm32f0x0-nucleo/project.ewp index b14d36e28a8..92bb6c55af5 100644 --- a/bsp/acm32/acm32f0x0-nucleo/project.ewp +++ b/bsp/acm32/acm32f0x0-nucleo/project.ewp @@ -2230,6 +2230,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c @@ -2267,34 +2270,34 @@ $PROJ_DIR$\drivers\drv_i2c.c - $PROJ_DIR$\drivers\drv_wdt.c + $PROJ_DIR$\drivers\drv_uart.c - $PROJ_DIR$\drivers\drv_rtc.c + $PROJ_DIR$\drivers\drv_wdt.c - $PROJ_DIR$\drivers\drv_spi.c + $PROJ_DIR$\drivers\drv_adc.c - $PROJ_DIR$\drivers\drv_adc.c + $PROJ_DIR$\drivers\drv_spi.c $PROJ_DIR$\drivers\drv_gpio.c - $PROJ_DIR$\drivers\drv_hwtimer.c + $PROJ_DIR$\drivers\drv_pm.c - $PROJ_DIR$\drivers\drv_pm.c + $PROJ_DIR$\drivers\drv_hwtimer.c $PROJ_DIR$\drivers\drv_soft_i2c.c - $PROJ_DIR$\drivers\board.c + $PROJ_DIR$\drivers\drv_rtc.c - $PROJ_DIR$\drivers\drv_uart.c + $PROJ_DIR$\drivers\board.c diff --git a/bsp/acm32/acm32f0x0-nucleo/project.uvprojx b/bsp/acm32/acm32f0x0-nucleo/project.uvprojx index e0f6df6bd25..da7df308e26 100644 --- a/bsp/acm32/acm32f0x0-nucleo/project.uvprojx +++ b/bsp/acm32/acm32f0x0-nucleo/project.uvprojx @@ -606,6 +606,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -801,9 +820,9 @@ Drivers - drv_soft_i2c.c + drv_pm.c 1 - drivers\drv_soft_i2c.c + drivers\drv_pm.c @@ -813,6 +832,13 @@ drivers\drv_rtc.c + + + drv_adc.c + 1 + drivers\drv_adc.c + + drv_uart.c @@ -829,16 +855,16 @@ - drv_wdt.c + drv_soft_i2c.c 1 - drivers\drv_wdt.c + drivers\drv_soft_i2c.c - drv_pm.c + drv_gpio.c 1 - drivers\drv_pm.c + drivers\drv_gpio.c @@ -850,9 +876,9 @@ - board.c + drv_wdt.c 1 - drivers\board.c + drivers\drv_wdt.c @@ -864,16 +890,9 @@ - drv_adc.c - 1 - drivers\drv_adc.c - - - - - drv_gpio.c + board.c 1 - drivers\drv_gpio.c + drivers\board.c diff --git a/bsp/acm32/acm32f4xx-nucleo/drivers/drv_gpio.c b/bsp/acm32/acm32f4xx-nucleo/drivers/drv_gpio.c index 3b5d7a32258..bb653fca6e9 100644 --- a/bsp/acm32/acm32f4xx-nucleo/drivers/drv_gpio.c +++ b/bsp/acm32/acm32f4xx-nucleo/drivers/drv_gpio.c @@ -206,7 +206,7 @@ static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) HAL_GPIO_WritePin(index->gpio, index->pin, (enum_PinState_t)value); } -static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t _pin_read(rt_device_t dev, rt_base_t pin) { int value; const struct pin_index *index; @@ -216,7 +216,7 @@ static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin) index = get_pin(pin); if (index == RT_NULL) { - return value; + return -RT_EINVAL; } value = HAL_GPIO_ReadPin(index->gpio, index->pin); diff --git a/bsp/acm32/acm32f4xx-nucleo/project.ewp b/bsp/acm32/acm32f4xx-nucleo/project.ewp index 3fb0b2981e5..48c5da0cf5f 100644 --- a/bsp/acm32/acm32f4xx-nucleo/project.ewp +++ b/bsp/acm32/acm32f4xx-nucleo/project.ewp @@ -2210,6 +2210,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c @@ -2238,10 +2241,10 @@ Drivers - $PROJ_DIR$\drivers\drv_gpio.c + $PROJ_DIR$\drivers\drv_uart.c - $PROJ_DIR$\drivers\drv_uart.c + $PROJ_DIR$\drivers\drv_gpio.c $PROJ_DIR$\drivers\board.c diff --git a/bsp/acm32/acm32f4xx-nucleo/project.uvprojx b/bsp/acm32/acm32f4xx-nucleo/project.uvprojx index f3290dcac06..02b15ed3720 100644 --- a/bsp/acm32/acm32f4xx-nucleo/project.uvprojx +++ b/bsp/acm32/acm32f4xx-nucleo/project.uvprojx @@ -538,6 +538,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -702,16 +721,16 @@ - board.c + drv_uart.c 1 - drivers\board.c + drivers\drv_uart.c - drv_uart.c + board.c 1 - drivers\drv_uart.c + drivers\board.c diff --git a/bsp/airm2m/air105/libraries/rt_drivers/drv_gpio.c b/bsp/airm2m/air105/libraries/rt_drivers/drv_gpio.c index 6c17599e89f..b726ec4e6bf 100644 --- a/bsp/airm2m/air105/libraries/rt_drivers/drv_gpio.c +++ b/bsp/airm2m/air105/libraries/rt_drivers/drv_gpio.c @@ -60,7 +60,7 @@ static void air105_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t air105_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t air105_pin_read(rt_device_t dev, rt_base_t pin) { if (pin < GPIO_MAX) { @@ -68,7 +68,7 @@ static rt_int8_t air105_pin_read(rt_device_t dev, rt_base_t pin) } else { - return -1; + return -RT_EINVAL; } } diff --git a/bsp/airm2m/air32f103/libraries/rt_drivers/drv_gpio.c b/bsp/airm2m/air32f103/libraries/rt_drivers/drv_gpio.c index a81c1790bb4..53dac60dfbd 100644 --- a/bsp/airm2m/air32f103/libraries/rt_drivers/drv_gpio.c +++ b/bsp/airm2m/air32f103/libraries/rt_drivers/drv_gpio.c @@ -157,7 +157,7 @@ static void air32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t air32_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t air32_pin_read(rt_device_t dev, rt_base_t pin) { GPIO_TypeDef *gpio_port; uint16_t gpio_pin; @@ -169,6 +169,10 @@ static rt_int8_t air32_pin_read(rt_device_t dev, rt_base_t pin) gpio_pin = PIN_AIRPIN(pin); value = GPIO_ReadInputDataBit(gpio_port, gpio_pin); } + else + { + return -RT_EINVAL; + } return value; } diff --git a/bsp/airm2m/air32f103/project.ewp b/bsp/airm2m/air32f103/project.ewp index 7bcc40bef25..8d9fbcdfc82 100644 --- a/bsp/airm2m/air32f103/project.ewp +++ b/bsp/airm2m/air32f103/project.ewp @@ -2218,6 +2218,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/airm2m/air32f103/project.uvprojx b/bsp/airm2m/air32f103/project.uvprojx index e1a8bd60158..e4656d9989a 100644 --- a/bsp/airm2m/air32f103/project.uvprojx +++ b/bsp/airm2m/air32f103/project.uvprojx @@ -487,6 +487,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/allwinner/d1/.config b/bsp/allwinner/d1/.config index 8e0b8ccb122..f38cb96783f 100644 --- a/bsp/allwinner/d1/.config +++ b/bsp/allwinner/d1/.config @@ -72,7 +72,7 @@ CONFIG_RT_USING_MEMTRACE=y # CONFIG_RT_USING_HEAP_ISR is not set CONFIG_RT_USING_HEAP=y CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set +CONFIG_RT_USING_DEVICE_OPS=y # CONFIG_RT_USING_INTERRUPT_INFO is not set # CONFIG_RT_USING_THREADSAFE_PRINTF is not set # CONFIG_RT_USING_SCHED_THREAD_CTX is not set @@ -153,6 +153,7 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DFS_ROMFS=y # CONFIG_RT_USING_DFS_ROMFS_USER_ROOT is not set +CONFIG_RT_USING_DFS_PTYFS=y # CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_TMPFS is not set # CONFIG_RT_USING_DFS_MQUEUE is not set @@ -187,8 +188,6 @@ CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 -CONFIG_RT_USING_TTY=y -# CONFIG_RT_TTY_DEBUG is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CPUTIME is not set CONFIG_RT_USING_I2C=y @@ -397,10 +396,11 @@ CONFIG_RT_CH_MSG_MAX_NR=1024 CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 CONFIG_LWP_TID_MAX_NR=64 CONFIG_RT_LWP_SHM_MAX_NR=64 -# CONFIG_LWP_UNIX98_PTY is not set CONFIG_RT_USING_LDSO=y # CONFIG_ELF_DEBUG_ENABLE is not set # CONFIG_ELF_LOAD_RANDOMIZE is not set +CONFIG_LWP_USING_TERMINAL=y +CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # Memory management diff --git a/bsp/allwinner/d1/rtconfig.h b/bsp/allwinner/d1/rtconfig.h index 8aca7375f97..fa1d2d602a9 100644 --- a/bsp/allwinner/d1/rtconfig.h +++ b/bsp/allwinner/d1/rtconfig.h @@ -47,6 +47,7 @@ #define RT_USING_MEMTRACE #define RT_USING_HEAP #define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart" @@ -105,6 +106,7 @@ #define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS #define RT_USING_DFS_ROMFS +#define RT_USING_DFS_PTYFS #define RT_USING_PAGECACHE /* page cache config */ @@ -131,7 +133,6 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_TTY #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_NULL @@ -256,6 +257,8 @@ #define LWP_TID_MAX_NR 64 #define RT_LWP_SHM_MAX_NR 64 #define RT_USING_LDSO +#define LWP_USING_TERMINAL +#define LWP_PTY_MAX_PARIS_LIMIT 64 /* Memory management */ diff --git a/bsp/allwinner/d1s/.config b/bsp/allwinner/d1s/.config index 8beb51059e8..38a1e7d9006 100644 --- a/bsp/allwinner/d1s/.config +++ b/bsp/allwinner/d1s/.config @@ -72,7 +72,7 @@ CONFIG_RT_USING_MEMTRACE=y # CONFIG_RT_USING_HEAP_ISR is not set CONFIG_RT_USING_HEAP=y CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set +CONFIG_RT_USING_DEVICE_OPS=y # CONFIG_RT_USING_INTERRUPT_INFO is not set # CONFIG_RT_USING_THREADSAFE_PRINTF is not set # CONFIG_RT_USING_SCHED_THREAD_CTX is not set @@ -152,6 +152,7 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 # CONFIG_RT_DFS_ELM_USE_EXFAT is not set CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +CONFIG_RT_USING_DFS_PTYFS=y # CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_TMPFS is not set # CONFIG_RT_USING_DFS_MQUEUE is not set @@ -185,8 +186,6 @@ CONFIG_RT_USING_SERIAL=y # CONFIG_RT_USING_SERIAL_V1 is not set CONFIG_RT_USING_SERIAL_V2=y # CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_USING_TTY=y -# CONFIG_RT_TTY_DEBUG is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set @@ -316,10 +315,11 @@ CONFIG_RT_CH_MSG_MAX_NR=1024 CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 CONFIG_LWP_TID_MAX_NR=64 CONFIG_RT_LWP_SHM_MAX_NR=64 -# CONFIG_LWP_UNIX98_PTY is not set CONFIG_RT_USING_LDSO=y # CONFIG_ELF_DEBUG_ENABLE is not set # CONFIG_ELF_LOAD_RANDOMIZE is not set +CONFIG_LWP_USING_TERMINAL=y +CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # Memory management diff --git a/bsp/allwinner/d1s/rtconfig.h b/bsp/allwinner/d1s/rtconfig.h index 032644d48f6..b52049619c4 100644 --- a/bsp/allwinner/d1s/rtconfig.h +++ b/bsp/allwinner/d1s/rtconfig.h @@ -47,6 +47,7 @@ #define RT_USING_MEMTRACE #define RT_USING_HEAP #define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart0" @@ -104,6 +105,7 @@ #define RT_DFS_ELM_REENTRANT #define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS +#define RT_USING_DFS_PTYFS #define RT_USING_PAGECACHE /* page cache config */ @@ -128,7 +130,6 @@ #define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL #define RT_USING_SERIAL_V2 -#define RT_USING_TTY #define RT_USING_NULL #define RT_USING_ZERO #define RT_USING_RANDOM @@ -194,6 +195,8 @@ #define LWP_TID_MAX_NR 64 #define RT_LWP_SHM_MAX_NR 64 #define RT_USING_LDSO +#define LWP_USING_TERMINAL +#define LWP_PTY_MAX_PARIS_LIMIT 64 /* Memory management */ diff --git a/bsp/allwinner/libraries/drivers/drv_pin.c b/bsp/allwinner/libraries/drivers/drv_pin.c index ce0a5359a9e..5d0d4e94391 100644 --- a/bsp/allwinner/libraries/drivers/drv_pin.c +++ b/bsp/allwinner/libraries/drivers/drv_pin.c @@ -32,11 +32,11 @@ static void hal_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t va hal_gpio_set_data(pin,value); } -static rt_int8_t hal_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t hal_pin_read(struct rt_device *device, rt_base_t pin) { gpio_data_t value; hal_gpio_get_data(pin,&value); - return (rt_int8_t)value; + return (rt_ssize_t)value; } static rt_err_t hal_pin_attach_irq(struct rt_device *device, rt_base_t pin, diff --git a/bsp/allwinner/libraries/drivers/touch/drv_touch.c b/bsp/allwinner/libraries/drivers/touch/drv_touch.c index 8361fb17428..d21013551cc 100644 --- a/bsp/allwinner/libraries/drivers/touch/drv_touch.c +++ b/bsp/allwinner/libraries/drivers/touch/drv_touch.c @@ -1,5 +1,5 @@ /* - * COPYRIGHT (C) 2012-2022, Shanghai Real-Thread Technology Co., Ltd + * COPYRIGHT (C) 2012-2024, Shanghai Real-Thread Technology Co., Ltd * All rights reserved. * Change Logs: * Date Author Notes diff --git a/bsp/allwinner/libraries/drivers/touch/drv_touch.h b/bsp/allwinner/libraries/drivers/touch/drv_touch.h index e7c6e7e0fbd..ad96e7c2458 100644 --- a/bsp/allwinner/libraries/drivers/touch/drv_touch.h +++ b/bsp/allwinner/libraries/drivers/touch/drv_touch.h @@ -1,5 +1,5 @@ /* - * COPYRIGHT (C) 2012-2022, Shanghai Real-Thread Technology Co., Ltd + * COPYRIGHT (C) 2012-2024, Shanghai Real-Thread Technology Co., Ltd * All rights reserved. * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/drivers/drv_gpio.c b/bsp/allwinner_tina/drivers/drv_gpio.c index d2457cd652c..25d956d35eb 100644 --- a/bsp/allwinner_tina/drivers/drv_gpio.c +++ b/bsp/allwinner_tina/drivers/drv_gpio.c @@ -453,12 +453,12 @@ static void pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t value) gpio_set_value(pin_index[pin].pin_port, pin_index[pin].pin, value); } -static rt_int8_t pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t pin_read(struct rt_device *device, rt_base_t pin) { if ((pin > PIN_NUM(pin_index)) || (pin_index[pin].magic != PIN_MAGIC)) { LOG_E("pin:%d value wrongful", pin); - return 0; + return -RT_EINVAL; } return gpio_get_value(pin_index[pin].pin_port, pin_index[pin].pin); diff --git a/bsp/amebaz/.config b/bsp/amebaz/.config index bed1c53c04e..f4b177dd90d 100644 --- a/bsp/amebaz/.config +++ b/bsp/amebaz/.config @@ -163,6 +163,7 @@ CONFIG_RT_WLAN_SCAN_WAIT_MS=10000 CONFIG_RT_WLAN_CONNECT_WAIT_MS=10000 CONFIG_RT_WLAN_SCAN_SORT=y CONFIG_RT_WLAN_MSH_CMD_ENABLE=y +CONFIG_RT_WLAN_JOIN_SCAN_BY_MGNT=y CONFIG_RT_WLAN_AUTO_CONNECT_ENABLE=y CONFIG_AUTO_CONNECTION_PERIOD_MS=2000 CONFIG_RT_WLAN_CFG_ENABLE=y diff --git a/bsp/amebaz/project.ewp b/bsp/amebaz/project.ewp index 28a4c609070..f4726be0fa5 100644 --- a/bsp/amebaz/project.ewp +++ b/bsp/amebaz/project.ewp @@ -2144,10 +2144,10 @@ Applications - $PROJ_DIR$\applications\smartconfig_app.c + $PROJ_DIR$\applications\main.c - $PROJ_DIR$\applications\main.c + $PROJ_DIR$\applications\smartconfig_app.c @@ -2206,6 +2206,9 @@ $PROJ_DIR$\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/amebaz/rtconfig.h b/bsp/amebaz/rtconfig.h index c52448d9c3c..387265ad719 100644 --- a/bsp/amebaz/rtconfig.h +++ b/bsp/amebaz/rtconfig.h @@ -92,6 +92,7 @@ #define RT_WLAN_CONNECT_WAIT_MS 10000 #define RT_WLAN_SCAN_SORT #define RT_WLAN_MSH_CMD_ENABLE +#define RT_WLAN_JOIN_SCAN_BY_MGNT #define RT_WLAN_AUTO_CONNECT_ENABLE #define AUTO_CONNECTION_PERIOD_MS 2000 #define RT_WLAN_CFG_ENABLE diff --git a/bsp/apm32/apm32e103ze-evalboard/project.ewp b/bsp/apm32/apm32e103ze-evalboard/project.ewp index a6157909c1b..f208d0a2b64 100644 --- a/bsp/apm32/apm32e103ze-evalboard/project.ewp +++ b/bsp/apm32/apm32e103ze-evalboard/project.ewp @@ -2262,6 +2262,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/apm32/apm32e103ze-evalboard/project.uvprojx b/bsp/apm32/apm32e103ze-evalboard/project.uvprojx index 7d7d60d64ff..2866f8214e2 100644 --- a/bsp/apm32/apm32e103ze-evalboard/project.uvprojx +++ b/bsp/apm32/apm32e103ze-evalboard/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/apm32/apm32e103ze-tinyboard/project.ewp b/bsp/apm32/apm32e103ze-tinyboard/project.ewp index a6157909c1b..f208d0a2b64 100644 --- a/bsp/apm32/apm32e103ze-tinyboard/project.ewp +++ b/bsp/apm32/apm32e103ze-tinyboard/project.ewp @@ -2262,6 +2262,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/apm32/apm32e103ze-tinyboard/project.uvprojx b/bsp/apm32/apm32e103ze-tinyboard/project.uvprojx index 9ede6405645..f42adf6f62c 100644 --- a/bsp/apm32/apm32e103ze-tinyboard/project.uvprojx +++ b/bsp/apm32/apm32e103ze-tinyboard/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/apm32/apm32f030r8-miniboard/project.ewp b/bsp/apm32/apm32f030r8-miniboard/project.ewp index e0d213ce2ef..9a285d4d417 100644 --- a/bsp/apm32/apm32f030r8-miniboard/project.ewp +++ b/bsp/apm32/apm32f030r8-miniboard/project.ewp @@ -2260,6 +2260,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/apm32/apm32f030r8-miniboard/project.uvprojx b/bsp/apm32/apm32f030r8-miniboard/project.uvprojx index c4dd4234e52..158420bae08 100644 --- a/bsp/apm32/apm32f030r8-miniboard/project.uvprojx +++ b/bsp/apm32/apm32f030r8-miniboard/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/apm32/apm32f051r8-evalboard/project.ewp b/bsp/apm32/apm32f051r8-evalboard/project.ewp index a84fcdf51e9..34e0559bdf0 100644 --- a/bsp/apm32/apm32f051r8-evalboard/project.ewp +++ b/bsp/apm32/apm32f051r8-evalboard/project.ewp @@ -2262,6 +2262,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/apm32/apm32f051r8-evalboard/project.uvprojx b/bsp/apm32/apm32f051r8-evalboard/project.uvprojx index 122ed969181..f910946d8ce 100644 --- a/bsp/apm32/apm32f051r8-evalboard/project.uvprojx +++ b/bsp/apm32/apm32f051r8-evalboard/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/apm32/apm32f072vb-miniboard/project.ewp b/bsp/apm32/apm32f072vb-miniboard/project.ewp index d45cf9a48ec..4739701e977 100644 --- a/bsp/apm32/apm32f072vb-miniboard/project.ewp +++ b/bsp/apm32/apm32f072vb-miniboard/project.ewp @@ -2262,6 +2262,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/apm32/apm32f072vb-miniboard/project.uvprojx b/bsp/apm32/apm32f072vb-miniboard/project.uvprojx index b244010ae1a..3a1b6f28e50 100644 --- a/bsp/apm32/apm32f072vb-miniboard/project.uvprojx +++ b/bsp/apm32/apm32f072vb-miniboard/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/apm32/apm32f091vc-miniboard/project.ewp b/bsp/apm32/apm32f091vc-miniboard/project.ewp index 8b0f72946e0..a13f8c829c5 100644 --- a/bsp/apm32/apm32f091vc-miniboard/project.ewp +++ b/bsp/apm32/apm32f091vc-miniboard/project.ewp @@ -2262,6 +2262,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/apm32/apm32f091vc-miniboard/project.uvprojx b/bsp/apm32/apm32f091vc-miniboard/project.uvprojx index 8a995d61605..839ee78bb64 100644 --- a/bsp/apm32/apm32f091vc-miniboard/project.uvprojx +++ b/bsp/apm32/apm32f091vc-miniboard/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/apm32/apm32f103vb-miniboard/project.ewp b/bsp/apm32/apm32f103vb-miniboard/project.ewp index 5cec65a487c..4c067c58a63 100644 --- a/bsp/apm32/apm32f103vb-miniboard/project.ewp +++ b/bsp/apm32/apm32f103vb-miniboard/project.ewp @@ -2264,6 +2264,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/apm32/apm32f103vb-miniboard/project.uvprojx b/bsp/apm32/apm32f103vb-miniboard/project.uvprojx index d8a76eaa29a..a82c61ae79b 100644 --- a/bsp/apm32/apm32f103vb-miniboard/project.uvprojx +++ b/bsp/apm32/apm32f103vb-miniboard/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/apm32/apm32f103xe-minibroard/project.ewp b/bsp/apm32/apm32f103xe-minibroard/project.ewp index 80f623ea5ef..a7f72c5b6b3 100644 --- a/bsp/apm32/apm32f103xe-minibroard/project.ewp +++ b/bsp/apm32/apm32f103xe-minibroard/project.ewp @@ -2234,6 +2234,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/apm32/apm32f103xe-minibroard/project.uvprojx b/bsp/apm32/apm32f103xe-minibroard/project.uvprojx index 2c27db85799..9091c43e62b 100644 --- a/bsp/apm32/apm32f103xe-minibroard/project.uvprojx +++ b/bsp/apm32/apm32f103xe-minibroard/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/apm32/apm32f107vc-evalboard/project.ewp b/bsp/apm32/apm32f107vc-evalboard/project.ewp index b6df615df8d..61791b7dafb 100644 --- a/bsp/apm32/apm32f107vc-evalboard/project.ewp +++ b/bsp/apm32/apm32f107vc-evalboard/project.ewp @@ -2264,6 +2264,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/apm32/apm32f107vc-evalboard/project.uvprojx b/bsp/apm32/apm32f107vc-evalboard/project.uvprojx index a523336e8da..b17679dc89b 100644 --- a/bsp/apm32/apm32f107vc-evalboard/project.uvprojx +++ b/bsp/apm32/apm32f107vc-evalboard/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/apm32/apm32f407ig-minibroard/project.ewp b/bsp/apm32/apm32f407ig-minibroard/project.ewp index b01f024fbbb..1452a27546c 100644 --- a/bsp/apm32/apm32f407ig-minibroard/project.ewp +++ b/bsp/apm32/apm32f407ig-minibroard/project.ewp @@ -2232,6 +2232,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/apm32/apm32f407ig-minibroard/project.uvprojx b/bsp/apm32/apm32f407ig-minibroard/project.uvprojx index 5cee83c6ecf..2b0b55fc395 100644 --- a/bsp/apm32/apm32f407ig-minibroard/project.uvprojx +++ b/bsp/apm32/apm32f407ig-minibroard/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/apm32/apm32f407zg-evalboard/project.ewp b/bsp/apm32/apm32f407zg-evalboard/project.ewp index 9aee2032cac..345bf7900ea 100644 --- a/bsp/apm32/apm32f407zg-evalboard/project.ewp +++ b/bsp/apm32/apm32f407zg-evalboard/project.ewp @@ -2264,6 +2264,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/apm32/apm32f407zg-evalboard/project.uvprojx b/bsp/apm32/apm32f407zg-evalboard/project.uvprojx index ed82a3ed309..4704a8ffc5f 100644 --- a/bsp/apm32/apm32f407zg-evalboard/project.uvprojx +++ b/bsp/apm32/apm32f407zg-evalboard/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/apm32/apm32s103vb-miniboard/project.ewp b/bsp/apm32/apm32s103vb-miniboard/project.ewp index 04d7a144cdf..9a089720d45 100644 --- a/bsp/apm32/apm32s103vb-miniboard/project.ewp +++ b/bsp/apm32/apm32s103vb-miniboard/project.ewp @@ -2262,6 +2262,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/apm32/apm32s103vb-miniboard/project.uvprojx b/bsp/apm32/apm32s103vb-miniboard/project.uvprojx index b4cd951fe27..43f24881fe2 100644 --- a/bsp/apm32/apm32s103vb-miniboard/project.uvprojx +++ b/bsp/apm32/apm32s103vb-miniboard/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/apm32/libraries/Drivers/drv_gpio.c b/bsp/apm32/libraries/Drivers/drv_gpio.c index c00ac26c54e..9555dd08055 100644 --- a/bsp/apm32/libraries/Drivers/drv_gpio.c +++ b/bsp/apm32/libraries/Drivers/drv_gpio.c @@ -173,7 +173,7 @@ static void apm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t apm32_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t apm32_pin_read(rt_device_t dev, rt_base_t pin) { GPIO_T *gpio_port; uint16_t gpio_pin; @@ -185,6 +185,10 @@ static rt_int8_t apm32_pin_read(rt_device_t dev, rt_base_t pin) gpio_pin = PIN_APMPIN(pin); value = GPIO_ReadInputBit(gpio_port, gpio_pin); } + else + { + return -RT_EINVAL; + } return value; } diff --git a/bsp/apollo2/board/gpio.c b/bsp/apollo2/board/gpio.c index 08bcdfdbfcf..ad87b6310d7 100644 --- a/bsp/apollo2/board/gpio.c +++ b/bsp/apollo2/board/gpio.c @@ -59,9 +59,9 @@ void am_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -rt_int8_t am_pin_read(rt_device_t dev, rt_base_t pin) +rt_ssize_t am_pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value = PIN_LOW; + rt_ssize_t value = PIN_LOW; if (am_hal_gpio_pin_config_read(pin) == AM_HAL_GPIO_OUTPUT) { diff --git a/bsp/apollo2/project.uvprojx b/bsp/apollo2/project.uvprojx index 88ab45403e7..80824fddc77 100644 --- a/bsp/apollo2/project.uvprojx +++ b/bsp/apollo2/project.uvprojx @@ -576,6 +576,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -790,23 +809,23 @@ Drivers - led.c + board_rtc.c 1 - board\led.c + board\rtc.c - uart.c + i2c.c 1 - board\uart.c + board\i2c.c - board.c + pdm.c 1 - board\board.c + board\pdm.c @@ -818,23 +837,23 @@ - gpio.c + pwm.c 1 - board\gpio.c + board\pwm.c - spi.c + flash.c 1 - board\spi.c + board\flash.c - pdm.c + spi.c 1 - board\pdm.c + board\spi.c @@ -846,30 +865,30 @@ - flash.c + led.c 1 - board\flash.c + board\led.c - board_rtc.c + gpio.c 1 - board\rtc.c + board\gpio.c - pwm.c + uart.c 1 - board\pwm.c + board\uart.c - i2c.c + board.c 1 - board\i2c.c + board\board.c diff --git a/bsp/asm9260t/project.ewp b/bsp/asm9260t/project.ewp index 134d3e06b81..d46508e3ab9 100644 --- a/bsp/asm9260t/project.ewp +++ b/bsp/asm9260t/project.ewp @@ -2128,6 +2128,9 @@ $PROJ_DIR$\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/asm9260t/project.uvproj b/bsp/asm9260t/project.uvproj index 0b6f2185600..4bbe4edc980 100644 --- a/bsp/asm9260t/project.uvproj +++ b/bsp/asm9260t/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f402-start/project.ewp b/bsp/at32/at32f402-start/project.ewp index 3085c43e852..bc804088b70 100644 --- a/bsp/at32/at32f402-start/project.ewp +++ b/bsp/at32/at32f402-start/project.ewp @@ -2160,6 +2160,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/at32/at32f402-start/project.uvproj b/bsp/at32/at32f402-start/project.uvproj index fd8979767ac..dae82f04254 100644 --- a/bsp/at32/at32f402-start/project.uvproj +++ b/bsp/at32/at32f402-start/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f402-start/project.uvprojx b/bsp/at32/at32f402-start/project.uvprojx index 07528c398d8..b7740dce373 100644 --- a/bsp/at32/at32f402-start/project.uvprojx +++ b/bsp/at32/at32f402-start/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f403a-start/project.ewp b/bsp/at32/at32f403a-start/project.ewp index 7c4f032a7c1..522b1d579bb 100644 --- a/bsp/at32/at32f403a-start/project.ewp +++ b/bsp/at32/at32f403a-start/project.ewp @@ -2160,6 +2160,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/at32/at32f403a-start/project.uvproj b/bsp/at32/at32f403a-start/project.uvproj index 17bbf2a1972..eeb9357d2a9 100644 --- a/bsp/at32/at32f403a-start/project.uvproj +++ b/bsp/at32/at32f403a-start/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f403a-start/project.uvprojx b/bsp/at32/at32f403a-start/project.uvprojx index ff3bb9aafb0..8c9ee790592 100644 --- a/bsp/at32/at32f403a-start/project.uvprojx +++ b/bsp/at32/at32f403a-start/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f405-start/project.ewp b/bsp/at32/at32f405-start/project.ewp index 7ed1e1f1364..2ce614d151c 100644 --- a/bsp/at32/at32f405-start/project.ewp +++ b/bsp/at32/at32f405-start/project.ewp @@ -2160,6 +2160,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/at32/at32f405-start/project.uvproj b/bsp/at32/at32f405-start/project.uvproj index aaabcf2a577..767665d18ea 100644 --- a/bsp/at32/at32f405-start/project.uvproj +++ b/bsp/at32/at32f405-start/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f405-start/project.uvprojx b/bsp/at32/at32f405-start/project.uvprojx index b9f49ae1603..852822e56ea 100644 --- a/bsp/at32/at32f405-start/project.uvprojx +++ b/bsp/at32/at32f405-start/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f407-start/project.ewp b/bsp/at32/at32f407-start/project.ewp index 746e8f4f078..7f0ae3a13ee 100644 --- a/bsp/at32/at32f407-start/project.ewp +++ b/bsp/at32/at32f407-start/project.ewp @@ -2160,6 +2160,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/at32/at32f407-start/project.uvproj b/bsp/at32/at32f407-start/project.uvproj index d1b6e448798..40f636f5098 100644 --- a/bsp/at32/at32f407-start/project.uvproj +++ b/bsp/at32/at32f407-start/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f407-start/project.uvprojx b/bsp/at32/at32f407-start/project.uvprojx index e36635088fc..3a3ed33893b 100644 --- a/bsp/at32/at32f407-start/project.uvprojx +++ b/bsp/at32/at32f407-start/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f413-start/project.ewp b/bsp/at32/at32f413-start/project.ewp index a4f9c6b0f7d..7257fa0b827 100644 --- a/bsp/at32/at32f413-start/project.ewp +++ b/bsp/at32/at32f413-start/project.ewp @@ -2160,6 +2160,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/at32/at32f413-start/project.uvproj b/bsp/at32/at32f413-start/project.uvproj index 61b9ef61214..f30c655ee82 100644 --- a/bsp/at32/at32f413-start/project.uvproj +++ b/bsp/at32/at32f413-start/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f413-start/project.uvprojx b/bsp/at32/at32f413-start/project.uvprojx index 17098e8548f..e5ad69c2fd4 100644 --- a/bsp/at32/at32f413-start/project.uvprojx +++ b/bsp/at32/at32f413-start/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f415-start/project.ewp b/bsp/at32/at32f415-start/project.ewp index 12bb1795cc3..8c144c80842 100644 --- a/bsp/at32/at32f415-start/project.ewp +++ b/bsp/at32/at32f415-start/project.ewp @@ -2160,6 +2160,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/at32/at32f415-start/project.uvproj b/bsp/at32/at32f415-start/project.uvproj index 1815ec90eba..7b92efa2993 100644 --- a/bsp/at32/at32f415-start/project.uvproj +++ b/bsp/at32/at32f415-start/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f415-start/project.uvprojx b/bsp/at32/at32f415-start/project.uvprojx index 5984ce20682..89061a0681d 100644 --- a/bsp/at32/at32f415-start/project.uvprojx +++ b/bsp/at32/at32f415-start/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f421-start/project.ewp b/bsp/at32/at32f421-start/project.ewp index 0955bdac562..a501a9389c9 100644 --- a/bsp/at32/at32f421-start/project.ewp +++ b/bsp/at32/at32f421-start/project.ewp @@ -2158,6 +2158,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/at32/at32f421-start/project.uvproj b/bsp/at32/at32f421-start/project.uvproj index 4787615fa6e..f129883d4a3 100644 --- a/bsp/at32/at32f421-start/project.uvproj +++ b/bsp/at32/at32f421-start/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f421-start/project.uvprojx b/bsp/at32/at32f421-start/project.uvprojx index 4f1f88dc2ee..f5ad54dc84b 100644 --- a/bsp/at32/at32f421-start/project.uvprojx +++ b/bsp/at32/at32f421-start/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f423-start/project.ewp b/bsp/at32/at32f423-start/project.ewp index 8b67c23136c..d7c04c4d544 100644 --- a/bsp/at32/at32f423-start/project.ewp +++ b/bsp/at32/at32f423-start/project.ewp @@ -2160,6 +2160,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/at32/at32f423-start/project.uvproj b/bsp/at32/at32f423-start/project.uvproj index 8ece1e06e38..63d0fb81fd2 100644 --- a/bsp/at32/at32f423-start/project.uvproj +++ b/bsp/at32/at32f423-start/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f423-start/project.uvprojx b/bsp/at32/at32f423-start/project.uvprojx index 81646924c1c..c40b327fddd 100644 --- a/bsp/at32/at32f423-start/project.uvprojx +++ b/bsp/at32/at32f423-start/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f425-start/project.ewp b/bsp/at32/at32f425-start/project.ewp index bcca1ab32ae..253fdb1ad05 100644 --- a/bsp/at32/at32f425-start/project.ewp +++ b/bsp/at32/at32f425-start/project.ewp @@ -2160,6 +2160,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/at32/at32f425-start/project.uvproj b/bsp/at32/at32f425-start/project.uvproj index db2c447666e..2ae2c18a965 100644 --- a/bsp/at32/at32f425-start/project.uvproj +++ b/bsp/at32/at32f425-start/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f425-start/project.uvprojx b/bsp/at32/at32f425-start/project.uvprojx index 5f263093d2f..3886ed930a8 100644 --- a/bsp/at32/at32f425-start/project.uvprojx +++ b/bsp/at32/at32f425-start/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f435-start/project.ewp b/bsp/at32/at32f435-start/project.ewp index ee879169772..ceeb4bf4cb3 100644 --- a/bsp/at32/at32f435-start/project.ewp +++ b/bsp/at32/at32f435-start/project.ewp @@ -2160,6 +2160,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/at32/at32f435-start/project.uvproj b/bsp/at32/at32f435-start/project.uvproj index 81a9c822818..27f3e9ddb2a 100644 --- a/bsp/at32/at32f435-start/project.uvproj +++ b/bsp/at32/at32f435-start/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f435-start/project.uvprojx b/bsp/at32/at32f435-start/project.uvprojx index 9009646ae49..0e328bbdff4 100644 --- a/bsp/at32/at32f435-start/project.uvprojx +++ b/bsp/at32/at32f435-start/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f437-start/project.ewp b/bsp/at32/at32f437-start/project.ewp index 40c055baf7a..48384f69d3a 100644 --- a/bsp/at32/at32f437-start/project.ewp +++ b/bsp/at32/at32f437-start/project.ewp @@ -2160,6 +2160,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/at32/at32f437-start/project.uvproj b/bsp/at32/at32f437-start/project.uvproj index 8904bbc756c..afa087d3c76 100644 --- a/bsp/at32/at32f437-start/project.uvproj +++ b/bsp/at32/at32f437-start/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/at32f437-start/project.uvprojx b/bsp/at32/at32f437-start/project.uvprojx index eb3ef0cff68..da97bf83815 100644 --- a/bsp/at32/at32f437-start/project.uvprojx +++ b/bsp/at32/at32f437-start/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/at32/libraries/rt_drivers/drv_adc.c b/bsp/at32/libraries/rt_drivers/drv_adc.c index 73a9c1184c8..1a67c490e80 100644 --- a/bsp/at32/libraries/rt_drivers/drv_adc.c +++ b/bsp/at32/libraries/rt_drivers/drv_adc.c @@ -135,8 +135,10 @@ static rt_err_t at32_get_adc_value(struct rt_adc_device *device, rt_int8_t chann /* adc_x regular channels configuration */ #if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ defined (SOC_SERIES_AT32F423) + adc_flag_clear(adc_x, ADC_OCCE_FLAG); adc_ordinary_channel_set(adc_x, (adc_channel_select_type)channel, 1, ADC_SAMPLETIME_247_5); #else + adc_flag_clear(adc_x, ADC_CCE_FLAG); adc_ordinary_channel_set(adc_x, (adc_channel_select_type)channel, 1, ADC_SAMPLETIME_239_5); #endif diff --git a/bsp/at32/libraries/rt_drivers/drv_gpio.c b/bsp/at32/libraries/rt_drivers/drv_gpio.c index ddbd4bb5523..a35569441f0 100644 --- a/bsp/at32/libraries/rt_drivers/drv_gpio.c +++ b/bsp/at32/libraries/rt_drivers/drv_gpio.c @@ -184,7 +184,7 @@ static void at32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) gpio_bits_write(gpio_port, gpio_pin, (confirm_state)value); } -static rt_int8_t at32_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t at32_pin_read(rt_device_t dev, rt_base_t pin) { gpio_type *gpio_port; uint16_t gpio_pin; @@ -198,6 +198,11 @@ static rt_int8_t at32_pin_read(rt_device_t dev, rt_base_t pin) gpio_pin = PIN_ATPIN(pin); value = gpio_input_data_bit_read(gpio_port, gpio_pin); } + else + { + return -RT_EINVAL; + } + return value; } diff --git a/bsp/at91/at91sam9g45/project.uvproj b/bsp/at91/at91sam9g45/project.uvproj index b2668f42318..3225844b71c 100644 --- a/bsp/at91/at91sam9g45/project.uvproj +++ b/bsp/at91/at91sam9g45/project.uvproj @@ -525,6 +525,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1070,23 +1089,23 @@ ktime - hrtimer.c + cputimer.c 1 - ..\..\..\components\drivers\ktime\src\hrtimer.c + ..\..\..\components\drivers\ktime\src\cputimer.c - boottime.c + hrtimer.c 1 - ..\..\..\components\drivers\ktime\src\boottime.c + ..\..\..\components\drivers\ktime\src\hrtimer.c - cputimer.c + boottime.c 1 - ..\..\..\components\drivers\ktime\src\cputimer.c + ..\..\..\components\drivers\ktime\src\boottime.c @@ -1160,30 +1179,30 @@ Platform - interrupt.c + reset.c 1 - platform\interrupt.c + platform\reset.c - rt_low_level_init.c + system_clock.c 1 - platform\rt_low_level_init.c + platform\system_clock.c - system_clock.c + interrupt.c 1 - platform\system_clock.c + platform\interrupt.c - reset.c + rt_low_level_init.c 1 - platform\reset.c + platform\rt_low_level_init.c diff --git a/bsp/avr32/drivers/drv_gpio.c b/bsp/avr32/drivers/drv_gpio.c index 4f84a48bf4f..0f9ce2ac321 100644 --- a/bsp/avr32/drivers/drv_gpio.c +++ b/bsp/avr32/drivers/drv_gpio.c @@ -59,7 +59,7 @@ static void at32uc3_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t v } } -static rt_int8_t at32uc3_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t at32uc3_pin_read(struct rt_device *device, rt_base_t pin) { RT_ASSERT((AVR32_BSP_GPIO_PMIN <= pin) && (pin <= AVR32_BSP_GPIO_PMAX)); return (gpio_get_pin_value(pin) ? PIN_HIGH : PIN_LOW); diff --git a/bsp/avr32/drivers/drv_soft_i2c.c b/bsp/avr32/drivers/drv_soft_i2c.c index 756d0db04c3..1aa9bd18566 100644 --- a/bsp/avr32/drivers/drv_soft_i2c.c +++ b/bsp/avr32/drivers/drv_soft_i2c.c @@ -34,7 +34,7 @@ static void avr32_i2c_gpio_init(struct avr32_i2c *i2c) rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); gpio_set_gpio_open_drain_pin(cfg->scl); - + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); gpio_set_gpio_open_drain_pin(cfg->sda); } @@ -50,11 +50,11 @@ static void avr32_set_sda(void *data, rt_int32_t state) struct avr32_soft_i2c_config* cfg = (struct avr32_soft_i2c_config*)data; if (state) { - gpio_set_gpio_open_drain_pin(cfg->sda); + gpio_set_gpio_open_drain_pin(cfg->sda); } else { - gpio_clr_gpio_open_drain_pin(cfg->sda); + gpio_clr_gpio_open_drain_pin(cfg->sda); } } @@ -69,11 +69,11 @@ static void avr32_set_scl(void *data, rt_int32_t state) struct avr32_soft_i2c_config* cfg = (struct avr32_soft_i2c_config*)data; if (state) { - gpio_set_gpio_open_drain_pin(cfg->scl); + gpio_set_gpio_open_drain_pin(cfg->scl); } else { - gpio_clr_gpio_open_drain_pin(cfg->scl); + gpio_clr_gpio_open_drain_pin(cfg->scl); } } @@ -126,10 +126,10 @@ static rt_err_t avr32_i2c_bus_unlock(const struct avr32_soft_i2c_config *cfg) { while (i++ < 9) { - gpio_set_gpio_open_drain_pin(cfg->scl); - rt_hw_us_delay(100); - gpio_clr_gpio_open_drain_pin(cfg->scl); - rt_hw_us_delay(100); + gpio_set_gpio_open_drain_pin(cfg->scl); + rt_hw_us_delay(100); + gpio_clr_gpio_open_drain_pin(cfg->scl); + rt_hw_us_delay(100); } } if (PIN_LOW == gpio_get_gpio_open_drain_pin_output_value(cfg->sda)) diff --git a/bsp/beaglebone/drivers/gpio.c b/bsp/beaglebone/drivers/gpio.c index 1add5015326..90c62a0cf6c 100644 --- a/bsp/beaglebone/drivers/gpio.c +++ b/bsp/beaglebone/drivers/gpio.c @@ -170,7 +170,7 @@ static void am33xx_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t } } -static rt_int8_t am33xx_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t am33xx_pin_read(struct rt_device *device, rt_base_t pin) { RT_ASSERT(pin >= 0 && pin < 128); rt_base_t gpiox = pin >> 5; diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c b/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c index c297b743718..5cf0a72aa57 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c @@ -106,7 +106,7 @@ static void ab32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) hal_gpio_write(PORT_SFR(port), gpio_pin, (rt_uint8_t)value); } -static rt_int8_t ab32_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t ab32_pin_read(rt_device_t dev, rt_base_t pin) { rt_uint8_t port = PIN_PORT(pin); rt_uint8_t gpio_pin = pin - port_table[port].total_pin; diff --git a/bsp/bouffalo_lab/bl808/d0/.config b/bsp/bouffalo_lab/bl808/d0/.config index 653919eb5db..4762aa135ea 100644 --- a/bsp/bouffalo_lab/bl808/d0/.config +++ b/bsp/bouffalo_lab/bl808/d0/.config @@ -129,6 +129,7 @@ CONFIG_RT_USING_DFS_V2=y # CONFIG_RT_USING_DFS_ELMFAT is not set CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +CONFIG_RT_USING_DFS_PTYFS=y # CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_TMPFS is not set # CONFIG_RT_USING_DFS_MQUEUE is not set @@ -159,8 +160,6 @@ CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 -CONFIG_RT_USING_TTY=y -# CONFIG_RT_TTY_DEBUG is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CPUTIME is not set CONFIG_RT_USING_I2C=y @@ -300,10 +299,11 @@ CONFIG_RT_CH_MSG_MAX_NR=1024 CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 CONFIG_LWP_TID_MAX_NR=64 CONFIG_RT_LWP_SHM_MAX_NR=64 -# CONFIG_LWP_UNIX98_PTY is not set CONFIG_RT_USING_LDSO=y # CONFIG_ELF_DEBUG_ENABLE is not set # CONFIG_ELF_LOAD_RANDOMIZE is not set +CONFIG_LWP_USING_TERMINAL=y +CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # Memory management diff --git a/bsp/bouffalo_lab/bl808/d0/rtconfig.h b/bsp/bouffalo_lab/bl808/d0/rtconfig.h index 8cd622a8b66..e6bb7edf01a 100755 --- a/bsp/bouffalo_lab/bl808/d0/rtconfig.h +++ b/bsp/bouffalo_lab/bl808/d0/rtconfig.h @@ -91,6 +91,7 @@ #define DFS_FD_MAX 16 #define RT_USING_DFS_V2 #define RT_USING_DFS_DEVFS +#define RT_USING_DFS_PTYFS #define RT_USING_PAGECACHE /* page cache config */ @@ -113,7 +114,6 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_TTY #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_NULL @@ -180,6 +180,8 @@ #define LWP_TID_MAX_NR 64 #define RT_LWP_SHM_MAX_NR 64 #define RT_USING_LDSO +#define LWP_USING_TERMINAL +#define LWP_PTY_MAX_PARIS_LIMIT 64 /* Memory management */ diff --git a/bsp/bouffalo_lab/bl808/m0/.config b/bsp/bouffalo_lab/bl808/m0/.config index 5da01fa7812..5238482c911 100755 --- a/bsp/bouffalo_lab/bl808/m0/.config +++ b/bsp/bouffalo_lab/bl808/m0/.config @@ -218,6 +218,7 @@ CONFIG_RT_WLAN_SCAN_WAIT_MS=10000 CONFIG_RT_WLAN_CONNECT_WAIT_MS=10000 CONFIG_RT_WLAN_SCAN_SORT=y CONFIG_RT_WLAN_MSH_CMD_ENABLE=y +CONFIG_RT_WLAN_JOIN_SCAN_BY_MGNT=y CONFIG_RT_WLAN_AUTO_CONNECT_ENABLE=y CONFIG_AUTO_CONNECTION_PERIOD_MS=2000 CONFIG_RT_WLAN_CFG_ENABLE=y diff --git a/bsp/bouffalo_lab/bl808/m0/rtconfig.h b/bsp/bouffalo_lab/bl808/m0/rtconfig.h index a4a0de1b800..3b81f39eaa4 100644 --- a/bsp/bouffalo_lab/bl808/m0/rtconfig.h +++ b/bsp/bouffalo_lab/bl808/m0/rtconfig.h @@ -133,6 +133,7 @@ #define RT_WLAN_CONNECT_WAIT_MS 10000 #define RT_WLAN_SCAN_SORT #define RT_WLAN_MSH_CMD_ENABLE +#define RT_WLAN_JOIN_SCAN_BY_MGNT #define RT_WLAN_AUTO_CONNECT_ENABLE #define AUTO_CONNECTION_PERIOD_MS 2000 #define RT_WLAN_CFG_ENABLE diff --git a/bsp/bouffalo_lab/libraries/rt_drivers/drv_adc.c b/bsp/bouffalo_lab/libraries/rt_drivers/drv_adc.c index 7cbe6dddfce..c9b5db6d4f6 100644 --- a/bsp/bouffalo_lab/libraries/rt_drivers/drv_adc.c +++ b/bsp/bouffalo_lab/libraries/rt_drivers/drv_adc.c @@ -49,7 +49,7 @@ static struct bl_adc bl_adc_obj; struct _adc_channel_cfg { struct bflb_adc_channel_s chan; - uint16_t chan_gpio; + uint16_t chan_gpio; }; static struct _adc_channel_cfg chan[] = { @@ -197,7 +197,7 @@ int rt_hw_adc_init(void) LOG_E("adc dma device not found"); return -RT_ERROR; } - + bl_adc_obj.sem = rt_sem_create("adc_sem", 0, RT_IPC_FLAG_PRIO); if(bl_adc_obj.sem == RT_NULL) { diff --git a/bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.c b/bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.c index 406cf3e384e..763dd1dd75c 100755 --- a/bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.c +++ b/bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.c @@ -48,7 +48,7 @@ static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) bflb_gpio_reset(gpio, pin); } -static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t _pin_read(rt_device_t dev, rt_base_t pin) { return bflb_gpio_read(gpio, pin); } diff --git a/bsp/ck802/libraries/include/drv_eth.h b/bsp/ck802/libraries/include/drv_eth.h index 12b5d182139..2c106fea733 100644 --- a/bsp/ck802/libraries/include/drv_eth.h +++ b/bsp/ck802/libraries/include/drv_eth.h @@ -33,17 +33,17 @@ typedef struct csi_driver_version { } csi_drv_version_t; /* General return codes */ -#define CSI_ETH_OK 0 ///< Operation succeeded +#define CSI_ETH_OK 0 ///< Operation succeeded #define CSI_ETH_ERROR CSI_DRV_ERRNO_ETH_BASE+1 ///< Unspecified error #define CSI_ETH_ERROR_BUSY CSI_DRV_ERRNO_ETH_BASE+2 ///< Driver is busy #define CSI_ETH_ERROR_TIMEOUT CSI_DRV_ERRNO_ETH_BASE+3 ///< Timeout occurred #define CSI_ETH_ERROR_UNSUPPORTED CSI_DRV_ERRNO_ETH_BASE+4 ///< Operation not supported #define CSI_ETH_ERROR_PARAMETER CSI_DRV_ERRNO_ETH_BASE+5 ///< Parameter error -#define CSI_ETH_ERROR_SPECIFIC CSI_DRV_ERRNO_ETH_BASE+6 ///< Start of driver specific errors +#define CSI_ETH_ERROR_SPECIFIC CSI_DRV_ERRNO_ETH_BASE+6 ///< Start of driver specific errors /** \brief General power states -*/ +*/ typedef enum eth_power_state { CSI_ETH_POWER_OFF, ///< Power off: no operation possible CSI_ETH_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events diff --git a/bsp/ck802/libraries/include/drv_eth_phy.h b/bsp/ck802/libraries/include/drv_eth_phy.h index adf4aa01714..27ef4155954 100644 --- a/bsp/ck802/libraries/include/drv_eth_phy.h +++ b/bsp/ck802/libraries/include/drv_eth_phy.h @@ -65,8 +65,8 @@ csi_drv_version_t csi_eth_phy_get_version(eth_phy_handle_t handle); /** \brief Initialize Ethernet PHY Device. - \param[in] fn_read - \param[in] fn_write + \param[in] fn_read + \param[in] fn_write \return ethernet phy handle */ eth_phy_handle_t csi_eth_phy_initialize(csi_eth_phy_read_t fn_read, csi_eth_phy_write_t fn_write); diff --git a/bsp/cvitek/.gitignore b/bsp/cvitek/.gitignore index 97d926d9575..93694d216fc 100755 --- a/bsp/cvitek/.gitignore +++ b/bsp/cvitek/.gitignore @@ -1,2 +1,6 @@ +cvitek_bootloader fip.bin -boot.sd \ No newline at end of file +boot.sd +output +c906_little/board/script +Image.lzma \ No newline at end of file diff --git a/bsp/cvitek/README.md b/bsp/cvitek/README.md index d9c7ae10777..f1bb1ee3cea 100755 --- a/bsp/cvitek/README.md +++ b/bsp/cvitek/README.md @@ -8,20 +8,43 @@ | 芯片名称 | 芯片架构 | 内存大小 | 默认日志串口 | 备注 | | ------- | ------- |------- | -------- | -------- | -| cv1800b | RISC-V C906 | 64MByte | uart0 | 默认开启 MMU，运行 RT-SMART 模式 | +| cv180x | RISC-V C906 | 64MByte | uart0 | 支持 MMU， 支持 RT-Thread 标准版 和 RT-SMART 模式，默认运行 RT-Thread 标准版本 | +| cv181x | RISC-V C906 或 Cortex A53 通过硬件 IO 二选一 | 64MByte | uart0 | 支持 MMU， 支持 RT-Thread 标准版 和 RT-SMART 版，默认运行 RT-Thread 标准版本 | - 小核 | 目录 | 内存大小 | 默认日志串口 | 备注 | | ---- | ------- | -------- | --- | -| c906-little | 与大核共享 | uart1 | 无 MMU，运行 RT-Thread 标准 | +| c906-little | 与大核共享 | uart1 | 无 MMU，运行 RT-Thread 标准版 | > 注：异构芯片需单独编译每个核的 OS +## 编译 +异构芯片需单独编译每个核的 OS，在大/小核对应的目录下，依次执行: + +1. 开发板选择 +Linux平台下，可以先执行： +```shell +$ scons --menuconfig +``` + +选择当前需要编译的目标开发板类型 +```shell +Board Type (milkv-duo) ---> + ( ) milkv-duo + ( ) milkv-duo-spinor + (X) milkv-duo256m + ( ) milkv-duo256m-spinor +``` + +2. 编译 +```shell +$ scons +``` ## 运行 -编译成功后，会在 `bsp/cvitek` 目录下自动生成 `fip.bin` 和 `boot.sd` 文件，其中大核运行文件在 `boot.sd` 中，小核的运行文件在 `fip.bin` 中。 +编译成功后，会在 `bsp/cvitek/output` 对应开发板型号目录下自动生成 `fip.bin` 和 `boot.sd` 文件，其中大核运行文件在 `boot.sd` 中，小核的运行文件在 `fip.bin` 中。 1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。 2. 将根目录下的 `fip.bin` 和 `boot.sd` 复制 SD 卡第一个分区中。 @@ -36,13 +59,28 @@ | gpio | 支持 | | | i2c | 支持 | | | adc | 支持 | | +| spi | 支持 | 默认CS引脚，每个数据之间CS会拉高，请根据时序选择GPIO作为CS。若读取数据，tx需持续dummy数据。| ## 支持开发板 - milk-v duo: [https://milkv.io/duo](https://milkv.io/duo) +- milk-v duo256m: [https://milkv.io/duo256m](https://milkv.io/docs/duo/getting-started/duo256m) ## FAQ 1. 如遇到不能正常编译，请先使用 `scons --menuconfig` 重新生成配置。 +2. 错误：./mkimage: error while loading shared libraries: libssl.so.1.1: cannot open shared object file: No such file or directory + +可在 [http://security.ubuntu.com/ubuntu/pool/main/o/openssl](http://security.ubuntu.com/ubuntu/pool/main/o/openssl) 下载 `libssl1.1_1.1.1f-1ubuntu2_amd64.deb` 文件后安装即可解决。 +或使用以下命令下载安装: +```shell +$ wget http://security.ubuntu.com/ubuntu/pool/main/o/openssl/libssl1.1_1.1.1f-1ubuntu2_amd64.deb +$ sudo dpkg -i libssl1.1_1.1.1f-1ubuntu2_amd64.deb +``` + +3. 如发现切换开发板编译正常，但无法正常打包，请切换至自动下载的 `cvi_bootloader` 目录，并手工运行 `git pull` 更新，或删除该目录后重新自动下载。 + ## 联系人信息 -维护人：[flyingcys](https://github.com/flyingcys) \ No newline at end of file +维护人：[flyingcys](https://github.com/flyingcys) + +更多信息请参考 [https://riscv-rtthread-programming-manual.readthedocs.io](https://riscv-rtthread-programming-manual.readthedocs.io) \ No newline at end of file diff --git a/bsp/cvitek/board_env.sh b/bsp/cvitek/board_env.sh new file mode 100755 index 00000000000..dcd4572702c --- /dev/null +++ b/bsp/cvitek/board_env.sh @@ -0,0 +1,45 @@ +#!/bin/bash + +function get_board_type() +{ + BOARD_CONFIG=("CONFIG_BOARD_TYPE_MILKV_DUO" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINAND" "CONFIG_BOARD_TYPE_MILKV_DUO256M" "CONFIG_BOARD_TYPE_MILKV_DUO256M_SPINOR" "CONFIG_BOARD_TYPE_MILKV_DUO256M_SPINAND") + BOARD_VALUE=("milkv-duo" "milkv-duo-spinor" "milkv-duo-spinand" "milkv-duo256m" "milkv-duo256m-spinor" "milkv-duo256m-spinand") + STORAGE_VAUE=("sd" "spinor" "spinand" "sd" "spinor" "spinand") + + for ((i=0;i<${#BOARD_CONFIG[@]};i++)) + do + config_value=$(grep -w "${BOARD_CONFIG[i]}" ${PROJECT_PATH}/.config | cut -d= -f2) + if [ "$config_value" == "y" ]; then + BOARD_TYPE=${BOARD_VALUE[i]} + STORAGE_TYPE=${STORAGE_VAUE[i]} + break + fi + done + export BOARD_TYPE=${BOARD_TYPE} + export STORAGE_TYPE=${STORAGE_TYPE} +} + +function check_bootloader() +{ + restult=$(curl -m 10 -s http://www.ip-api.com/json) + COUNTRY=$(echo $restult | sed 's/.*"country":"\([^"]*\)".*/\1/') + echo "Country: $COUNTRY" + + if [ "$COUNTRY" == "China" ]; then + BOOTLOADER_URL=https://gitee.com/flyingcys/cvitek_bootloader + else + BOOTLOADER_URL=https://github.com/flyingcys/cvitek_bootloader + fi + + if [ ! -d cvitek_bootloader ]; then + echo "cvitek_bootloader not exist, clone it from ${BOOTLOADER_URL}" + git clone ${BOOTLOADER_URL} + + if [ $? -ne 0 ]; then + echo "Failed to clone ${BOOTLOADER_URL} !" + exit 1 + fi +fi +} + + diff --git a/bsp/cvitek/c906_little/.config b/bsp/cvitek/c906_little/.config index 56756b1f7d2..0944943d7fe 100644 --- a/bsp/cvitek/c906_little/.config +++ b/bsp/cvitek/c906_little/.config @@ -1080,6 +1080,7 @@ CONFIG_RT_USING_UART1=y CONFIG_UART_IRQ_BASE=30 # CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_WDT is not set # CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_RTC is not set @@ -1087,3 +1088,7 @@ CONFIG_BSP_USING_C906_LITTLE=y CONFIG_PLIC_PHY_ADDR=0x70000000 CONFIG_IRQ_MAX_NR=128 CONFIG_TIMER_CLK_FREQ=25000000 +# CONFIG_BOARD_TYPE_MILKV_DUO is not set +# CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR is not set +CONFIG_BOARD_TYPE_MILKV_DUO256M=y +# CONFIG_BOARD_TYPE_MILKV_DUO256M_SPINOR is not set diff --git a/bsp/cvitek/c906_little/Kconfig b/bsp/cvitek/c906_little/Kconfig index 2e6980adea4..d981d97abe7 100755 --- a/bsp/cvitek/c906_little/Kconfig +++ b/bsp/cvitek/c906_little/Kconfig @@ -37,4 +37,22 @@ config IRQ_MAX_NR config TIMER_CLK_FREQ int - default 25000000 \ No newline at end of file + default 25000000 + +choice + prompt "Board Type" + default BOARD_TYPE_MILKV_DUO256M + + config BOARD_TYPE_MILKV_DUO + bool "milkv-duo" + + config BOARD_TYPE_MILKV_DUO_SPINOR + bool "milkv-duo-spinor" + + config BOARD_TYPE_MILKV_DUO256M + bool "milkv-duo256m" + + config BOARD_TYPE_MILKV_DUO256M_SPINOR + bool "milkv-duo256m-spinor" + +endchoice diff --git a/bsp/cvitek/c906_little/README.md b/bsp/cvitek/c906_little/README.md index 71a3d6135d3..14bd1a7e499 100755 --- a/bsp/cvitek/c906_little/README.md +++ b/bsp/cvitek/c906_little/README.md @@ -17,20 +17,39 @@ $ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin ``` ## 编译 -1. Linux平台下，可以先执行： +1. 依赖安装 + +```shell +$ sudo apt install -y scons libncurses5-dev wget flex bison +``` + + +2. Linux平台下，先执行： ```shell $ scons --menuconfig ``` -它会自动下载env相关脚本到~/.env目录，然后执行 +选择当前需要编译的目标开发板类型： +```shell +Board Type (milkv-duo) ---> + ( ) milkv-duo + ( ) milkv-duo-spinor + (X) milkv-duo256m + ( ) milkv-duo256m-spinor +``` + +它会自动下载 env 相关脚本到 ~/.env 目录，然后执行 ```shell $ source ~/.env/env.sh $ pkgs --update ``` -更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf文件。 +更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf 文件。 编译完成后脚本自动调用 `combine-fip.sh` 脚本进行打包，并生成 `fip.sd`, 该文件即为 SD 卡启动的 c906_little 文件。 +第一次调用 `combine-fip.sh` 脚本时会自动下载打包需要的 `opsbsbi`、`fsbl`、`uboot` 等相关文件至 `bsp/cvitek/cvitek_bootloader` 目录，请耐心等待。 + +下载完成后会自动解压、编译，后续再次编译同一类型开发板只会调用相关文件打包合成 `fip.bin`。如需手工编译相关 `cvitek_bootloader` 文件，可在 `bsp/cvitek/cvitek_bootloader` 目录下执行 `bash build.sh lunch` 选择对应的开发板编译。 ## 运行 1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。 @@ -49,4 +68,6 @@ HW_HEAP_BEGIN:83f74dc0 RT_HW_HEAP_END:84000000 size: 569920 2006 - 2022 Copyright by RT-Thread team Hello, RISC-V! msh /> -``` \ No newline at end of file +``` + +> 注：c906 小核默认日志串口为 uart1 \ No newline at end of file diff --git a/bsp/cvitek/c906_little/README_en.md b/bsp/cvitek/c906_little/README_en.md new file mode 100755 index 00000000000..df6d28fa9c8 --- /dev/null +++ b/bsp/cvitek/c906_little/README_en.md @@ -0,0 +1,72 @@ +# c906_little bsp +This BSP is a coprocessor in the cv18xx series processor, using RISCV C906 @ 700Mhz. +Features: +- No MMU +- Integrated Floating-point Unit (FPU) + +## Toolchain Download +Download the toolchain for `riscv64-unknown-elf-gcc`: [https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz](https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz) + +> Note: +Current BSP only supports Linux compilation. + +After correct decompression, add the local path of the `riscv64-unknown-elf-gcc` toolchain to `EXEC_PATH` in `rtconfig.py`, or specify the path through the `RTT_EXEC_PATH` environment variable. + +```shell +$ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin +``` + +## Compilation +1. Dependency Installation + +```shell +$ sudo apt install -y scons libncurses5-dev wget flex bison +``` + +2. On Linux platform, execute: +```shell +$ scons --menuconfig +``` + +Choose the target development board type that needs to be compiled: +```shell +Board Type (milkv-duo) ---> + ( ) milkv-duo + ( ) milkv-duo-spinor + (X) milkv-duo256m + ( ) milkv-duo256m-spinor +``` + +It will automatically download env related scripts to the ~/.env directory, then execute +```shell +$ source ~/.env/env.sh +$ pkgs --update +``` +After updating the software packages, execute `scons -j10` or `scons -j10 --verbose` to compile this BSP. Or use the `scons --exec-path="GCC toolchain path"` command to compile directly while specifying the toolchain location. If the compilation is correct, the rtthread.elf file will be generated. + +After the compilation is completed, the script automatically calls the `combine-fip.sh` script for packaging, and generates `fip.sd`, which is the c906_little file for SD card startup. + +The first time the `combine-fip.sh` script is called, it will automatically download the required `opsbsbi`, `fsbl`, `uboot`, and other related files to the `bsp/cvitek/cvitek_bootloader` directory, please be patient. + +After downloading, it will automatically decompress and compile. Subsequently, when compiling the same type of development board again, only the relevant files will be called to package and synthesize `fip.bin`. If you need to manually compile the related `cvitek_bootloader` files, you can execute `bash build.sh lunch` in the `bsp/cvitek/cvitek_bootloader` directory to choose the corresponding development board for compilation. + +## Running +1. Divide the SD card into 2 partitions, the 1st partition is used to store bin files, and the 2nd partition is used as a data storage partition, with the partition format being `FAT32`. +2. Copy the `fip.bin` and `boot.sd` from the root directory into the 1st partition of the SD card. Subsequent firmware updates only require copying the `fip.sd` file. +Where: +- fip.bin: fsbl, opensbi, uboot, c906_little packaged bin file +- boot.sd: bin file packaged by the main kernel + +After updating `fip.sd`, restarting will show the output information on the serial port: +```shell +HW_HEAP_BEGIN:83f74dc0 RT_HW_HEAP_END:84000000 size: 569920 + + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Jan 27 2024 22:45:49 + 2006 - 2022 Copyright by RT-Thread team +Hello, RISC-V! +msh /> +``` + +> Note: The default log serial port for the c906 little core is uart1 \ No newline at end of file diff --git a/bsp/cvitek/c906_little/SConstruct b/bsp/cvitek/c906_little/SConstruct index b331ef4db85..0a1878479d0 100755 --- a/bsp/cvitek/c906_little/SConstruct +++ b/bsp/cvitek/c906_little/SConstruct @@ -37,5 +37,9 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) # include libraries objs.extend(SConscript(drivers_path_prefix + '/SConscript', variant_dir='build/drivers', duplicate=0)) +if GetDepend('BOARD_TYPE_MILKV_DUO256M'): + env['LINKFLAGS'] = env['LINKFLAGS'].replace('cv180x_lscript.ld', 'cv181x_lscript.ld') + env['LINKFLAGS'] = env['LINKFLAGS'].replace('-L board/script/cv180x', '-L board/script/cv181x') + # make a building DoBuilding(TARGET, objs) diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig index 3780246c591..6a0d10c0f30 100755 --- a/bsp/cvitek/c906_little/board/Kconfig +++ b/bsp/cvitek/c906_little/board/Kconfig @@ -45,6 +45,11 @@ menu "General Drivers Configuration" select RT_USING_ADC default n + config BSP_USING_SPI + bool "Using SPI" + select RT_USING_SPI + default n + menuconfig BSP_USING_WDT bool "Enable Watchdog Timer" select RT_USING_WDT diff --git a/bsp/cvitek/c906_little/cv180x_lscript.ld b/bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld similarity index 98% rename from bsp/cvitek/c906_little/cv180x_lscript.ld rename to bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld index 180e3193119..a91067f7250 100755 --- a/bsp/cvitek/c906_little/cv180x_lscript.ld +++ b/bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld @@ -7,6 +7,8 @@ * Date Author Notes * 2024/01/11 flyingcys The first version */ +INCLUDE ./cvi_board_memmap.ld + _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x20000; /* _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000; */ /*_HEAP_SIZE = 0x20000;*/ @@ -15,9 +17,6 @@ _EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024; _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048; _EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024; -CVIMMAP_FREERTOS_ADDR = 0x83f40000; -CVIMMAP_FREERTOS_SIZE = 0xc0000; - /* Define Memories in the system */ MEMORY diff --git a/bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld b/bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld new file mode 100755 index 00000000000..9f2f1558260 --- /dev/null +++ b/bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld @@ -0,0 +1,30 @@ +CONFIG_SYS_TEXT_BASE = 0x80200000; +CVIMMAP_ATF_SIZE = 0x80000; +CVIMMAP_BOOTLOGO_ADDR = 0x82473000; +CVIMMAP_BOOTLOGO_SIZE = 0x0; +CVIMMAP_CONFIG_SYS_INIT_SP_ADDR = 0x82300000; +CVIMMAP_CVI_UPDATE_HEADER_ADDR = 0x813ffc00; +CVIMMAP_CVI_UPDATE_HEADER_SIZE = 0x400; +CVIMMAP_DRAM_BASE = 0x80000000; +CVIMMAP_DRAM_SIZE = 0x4000000; +CVIMMAP_FREERTOS_ADDR = 0x83f40000; +CVIMMAP_FREERTOS_RESERVED_ION_SIZE = 0x0; +CVIMMAP_FREERTOS_SIZE = 0xc0000; +CVIMMAP_FSBL_C906L_START_ADDR = 0x83f40000; +CVIMMAP_FSBL_UNZIP_ADDR = 0x81400000; +CVIMMAP_FSBL_UNZIP_SIZE = 0xf00000; +CVIMMAP_H26X_BITSTREAM_ADDR = 0x82473000; +CVIMMAP_H26X_BITSTREAM_SIZE = 0x0; +CVIMMAP_H26X_ENC_BUFF_ADDR = 0x82473000; +CVIMMAP_H26X_ENC_BUFF_SIZE = 0x0; +CVIMMAP_ION_ADDR = 0x82473000; +CVIMMAP_ION_SIZE = 0x1acd000; +CVIMMAP_ISP_MEM_BASE_ADDR = 0x82473000; +CVIMMAP_ISP_MEM_BASE_SIZE = 0x0; +CVIMMAP_KERNEL_MEMORY_ADDR = 0x80000000; +CVIMMAP_KERNEL_MEMORY_SIZE = 0x3f40000; +CVIMMAP_MONITOR_ADDR = 0x80000000; +CVIMMAP_OPENSBI_FDT_ADDR = 0x80080000; +CVIMMAP_OPENSBI_SIZE = 0x80000; +CVIMMAP_UIMAG_ADDR = 0x81400000; +CVIMMAP_UIMAG_SIZE = 0xf00000; \ No newline at end of file diff --git a/bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld b/bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld new file mode 100755 index 00000000000..a91067f7250 --- /dev/null +++ b/bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024/01/11 flyingcys The first version + */ +INCLUDE ./cvi_board_memmap.ld + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x20000; +/* _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000; */ +/*_HEAP_SIZE = 0x20000;*/ + +_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024; +_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048; +_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024; + +/* Define Memories in the system */ + +MEMORY +{ + psu_ddr_0_MEM_0 : ORIGIN = CVIMMAP_FREERTOS_ADDR , LENGTH = CVIMMAP_FREERTOS_SIZE +} + +/* Specify the default entry point to the program */ + +/*ENTRY(_vector_table)*/ +ENTRY(_start) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.text : { + KEEP (*(.vectors)) + *(.boot) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.plt) + *(.gnu_warning) + *(.gcc_execpt_table) + *(.glue_7) + *(.glue_7t) + *(.ARM.extab) + *(.gnu.linkonce.armextab.*) + + /* section information for finsh shell */ + . = ALIGN(8); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(8); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(8); + + /* section information for initial. */ + . = ALIGN(8); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(8); + + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; +} > psu_ddr_0_MEM_0 + +.init (ALIGN(64)) : { + KEEP (*(.init)) +} > psu_ddr_0_MEM_0 + +.fini (ALIGN(64)) : { + KEEP (*(.fini)) +} > psu_ddr_0_MEM_0 + +.interp : { + KEEP (*(.interp)) +} > psu_ddr_0_MEM_0 + +.note-ABI-tag : { + KEEP (*(.note-ABI-tag)) +} > psu_ddr_0_MEM_0 + +.rodata : { + . = ALIGN(64); + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.srodata*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > psu_ddr_0_MEM_0 + +.rodata1 : { + . = ALIGN(64); + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > psu_ddr_0_MEM_0 + +.data : { + . = ALIGN(64); + _data = .; + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.d.*) + *(.jcr) + *(.got) + *(.got.plt) + _edata = .; +} > psu_ddr_0_MEM_0 + +.data1 : { + . = ALIGN(64); + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > psu_ddr_0_MEM_0 + +.got : { + *(.got) +} > psu_ddr_0_MEM_0 + +.got1 : { + *(.got1) +} > psu_ddr_0_MEM_0 + +.got2 : { + *(.got2) +} > psu_ddr_0_MEM_0 + +.ctors : { + . = ALIGN(64); + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > psu_ddr_0_MEM_0 + +.dtors : { + . = ALIGN(64); + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > psu_ddr_0_MEM_0 + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > psu_ddr_0_MEM_0 + +.eh_frame : { + *(.eh_frame) +} > psu_ddr_0_MEM_0 + +.eh_framehdr : { + __eh_framehdr_start = .; + *(.eh_framehdr) + __eh_framehdr_end = .; +} > psu_ddr_0_MEM_0 + +.gcc_except_table : { + *(.gcc_except_table) +} > psu_ddr_0_MEM_0 + +.bss (NOLOAD) : { + . = ALIGN(64); + _bss = .; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(64); + _ebss = .; +} > psu_ddr_0_MEM_0 + +/*_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );*/ + _data_lma = LOADADDR(.data); + +/* Generate Stack and Heap definitions */ +.stack (NOLOAD) : { + . = ALIGN(64); + _stack_end_end = .; + . += _STACK_SIZE; + _stack_top = .; + __rt_rvstack = .; +} > psu_ddr_0_MEM_0 + +.heap (NOLOAD) : { + . = ALIGN(64); + _heap = .; + HeapBase = .; + _heap_start = .; + *(.heap*) + /*. += _HEAP_SIZE;*/ + /*_heap_size = _HEAP_SIZE; */ + _heap_end = .; + HeapLimit = .; +} > psu_ddr_0_MEM_0 + +HeapLimit = ORIGIN(psu_ddr_0_MEM_0) + LENGTH(psu_ddr_0_MEM_0); +_end = .; +} + diff --git a/bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld b/bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld new file mode 100755 index 00000000000..d2b87440447 --- /dev/null +++ b/bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld @@ -0,0 +1,32 @@ +CONFIG_SYS_TEXT_BASE = 0x80200000; +CVIMMAP_ATF_SIZE = 0x80000; +CVIMMAP_BOOTLOGO_ADDR = 0x8b13e000; +CVIMMAP_BOOTLOGO_SIZE = 0x1c2000; +CVIMMAP_CONFIG_SYS_INIT_SP_ADDR = 0x82800000; +CVIMMAP_CVI_UPDATE_HEADER_ADDR = 0x817ffc00; +CVIMMAP_CVI_UPDATE_HEADER_SIZE = 0x400; +CVIMMAP_DRAM_BASE = 0x80000000; +CVIMMAP_DRAM_SIZE = 0x10000000; +CVIMMAP_FRAMEBUFFER_ADDR = 0x8b13e000; +CVIMMAP_FRAMEBUFFER_SIZE = 0x1c2000; +CVIMMAP_FREERTOS_ADDR = 0x8fe00000; +CVIMMAP_FREERTOS_RESERVED_ION_SIZE = 0x1600000; +CVIMMAP_FREERTOS_SIZE = 0x200000; +CVIMMAP_FSBL_C906L_START_ADDR = 0x8fe00000; +CVIMMAP_FSBL_UNZIP_ADDR = 0x81800000; +CVIMMAP_FSBL_UNZIP_SIZE = 0x1000000; +CVIMMAP_H26X_BITSTREAM_ADDR = 0x8b300000; +CVIMMAP_H26X_BITSTREAM_SIZE = 0x200000; +CVIMMAP_H26X_ENC_BUFF_ADDR = 0x8b500000; +CVIMMAP_H26X_ENC_BUFF_SIZE = 0x0; +CVIMMAP_ION_ADDR = 0x8b300000; +CVIMMAP_ION_SIZE = 0x4b00000; +CVIMMAP_ISP_MEM_BASE_ADDR = 0x8b500000; +CVIMMAP_ISP_MEM_BASE_SIZE = 0x1400000; +CVIMMAP_KERNEL_MEMORY_ADDR = 0x80000000; +CVIMMAP_KERNEL_MEMORY_SIZE = 0xfe00000; +CVIMMAP_MONITOR_ADDR = 0x80000000; +CVIMMAP_OPENSBI_FDT_ADDR = 0x80080000; +CVIMMAP_OPENSBI_SIZE = 0x80000; +CVIMMAP_UIMAG_ADDR = 0x81800000; +CVIMMAP_UIMAG_SIZE = 0x1000000; \ No newline at end of file diff --git a/bsp/cvitek/c906_little/rtconfig.h b/bsp/cvitek/c906_little/rtconfig.h index 40db54549b1..d4fced8b338 100755 --- a/bsp/cvitek/c906_little/rtconfig.h +++ b/bsp/cvitek/c906_little/rtconfig.h @@ -268,5 +268,6 @@ #define PLIC_PHY_ADDR 0x70000000 #define IRQ_MAX_NR 128 #define TIMER_CLK_FREQ 25000000 +#define BOARD_TYPE_MILKV_DUO256M #endif diff --git a/bsp/cvitek/c906_little/rtconfig.py b/bsp/cvitek/c906_little/rtconfig.py index dd7ed95f05a..50c32d55617 100755 --- a/bsp/cvitek/c906_little/rtconfig.py +++ b/bsp/cvitek/c906_little/rtconfig.py @@ -18,7 +18,7 @@ if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.0/bin' + EXEC_PATH = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin' else: print('Please make sure your toolchains is GNU GCC!') exit(0) @@ -47,9 +47,10 @@ CFLAGS += ' -DCONFIG_64BIT' LINKER_SCRIPTS = r'cv180x_lscript.ld' + LINKER_SCRIPTS_PATH = r' -L board/script/cv180x' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' - LFLAGS = DEVICE + ' -nostartfiles -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS + LFLAGS = DEVICE + ' -nostartfiles -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS + LINKER_SCRIPTS_PATH CPATH = '' LPATH = '' @@ -63,4 +64,4 @@ DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' -POST_ACTION += 'cd .. && ./combine-fip.sh c906_little/rtthread.bin\n' \ No newline at end of file +POST_ACTION += 'cd .. && bash combine-fip.sh ' + os.getcwd() + ' rtthread.bin' + ' \n' \ No newline at end of file diff --git a/bsp/cvitek/combine-fip.sh b/bsp/cvitek/combine-fip.sh index fee521077c0..414da79eb34 100755 --- a/bsp/cvitek/combine-fip.sh +++ b/bsp/cvitek/combine-fip.sh @@ -1,23 +1,49 @@ #!/bin/bash -set -e - -LITTLE_BIN=$1 - -. ./pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env && \ -./pre-build/fsbl/plat/cv180x/fiptool.py -v genfip \ - 'fip.bin' \ - --MONITOR_RUNADDR="${MONITOR_RUNADDR}" \ - --BLCP_2ND_RUNADDR="${BLCP_2ND_RUNADDR}" \ - --CHIP_CONF='./pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin' \ - --NOR_INFO='FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' \ - --NAND_INFO='00000000'\ - --BL2='pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin' \ - --BLCP_IMG_RUNADDR=0x05200200 \ - --BLCP_PARAM_LOADADDR=0 \ - --BLCP=pre-build/fsbl/test/empty.bin \ - --DDR_PARAM='pre-build/fsbl/test/cv181x/ddr_param.bin' \ - --BLCP_2ND=$LITTLE_BIN \ - --MONITOR='pre-build/fw_dynamic.bin' \ - --LOADER_2ND='pre-build/u-boot-raw.bin' \ - --compress='lzma' \ No newline at end of file +PROJECT_PATH=$1 +IMAGE_NAME=$2 + +if [ -z "$PROJECT_PATH" ] || [ -z "$IMAGE_NAME" ]; then + echo "Usage: $0 " + exit 1 +fi + +ROOT_PATH=$(pwd) +echo $ROOT_PATH + +. board_env.sh + +get_board_type +echo "board_type: ${BOARD_TYPE}" + +check_bootloader || exit 0 + +export BLCP_2ND_PATH=${PROJECT_PATH}/${IMAGE_NAME} + +pushd cvitek_bootloader + +. env.sh + +get_build_board ${BOARD_TYPE} + +echo "board: ${MV_BOARD_LINK}" + +if [ ! -d opensbi/build/platform/generic ] || [ ! -d fsbl/build/${MV_BOARD_LINK} ] || [ ! -d u-boot-2021.10/build/${MV_BOARD_LINK} ]; then + do_build + + CHIP_ARCH_L=$(echo $CHIP_ARCH | tr '[:upper:]' '[:lower:]') + cp -rf build/output/${MV_BOARD_LINK}/cvi_board_memmap.ld ${ROOT_PATH}/c906_little/board/script/${CHIP_ARCH_L} +else + echo "Build already done, skip build" + + do_combine + + if [ $? -ne 0 ]; then + do_build + fi +fi + +popd + +mkdir -p output/${MV_BOARD} +cp -rf cvitek_bootloader/install/soc_${MV_BOARD_LINK}/fip.bin output/${MV_BOARD}/fip.bin \ No newline at end of file diff --git a/bsp/cvitek/cv1800b/.gitignore b/bsp/cvitek/cv1800b/.gitignore deleted file mode 100755 index f58350d6cff..00000000000 --- a/bsp/cvitek/cv1800b/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -cv1800b_milkv_duo_sd.dtb -Image -Image.lzma -multi.its -boot.sd \ No newline at end of file diff --git a/bsp/cvitek/cv1800b/README_en.md b/bsp/cvitek/cv1800b/README_en.md deleted file mode 100755 index 19da2982c83..00000000000 --- a/bsp/cvitek/cv1800b/README_en.md +++ /dev/null @@ -1,130 +0,0 @@ -[中文](README.md) | **English** - -## Overview -CV180ZB/CV1800B/CV1801B are high-performance, low-power chips designed for consumer surveillance IP cameras, smart home devices, and other product areas. They integrate H.264/H.265 video compression encoders and ISPs, and support various image enhancement and correction algorithms such as digital wide dynamic range, 3D noise reduction, defogging, and lens distortion correction, providing professional-grade video image quality to customers. - -1. Processor Core -- Main processor: RISCV C906 @ 1.0Ghz - - 32KB I-cache, 64KB D-Cache - - Integrated vector and floating-point units (FPU). -- Coprocessor: RISCV C906 @ 700Mhz - - Integrated floating-point unit (FPU). - -2. Memory Interface -- Built-in DRAM: DDR2 16bitx1, with a maximum speed of 1333Mbps, capacity of 512Mbit (64MB). -- Support for SPI NOR flash interface (1.8V / 3.0V) - - Support for 1, 2, 4-wire modes - - Maximum support of 256MBytes -- Support for SPI Nand flash interface (1.8V / 3.0V) - - Support for 1KB/2KB/4KB page (corresponding to a maximum capacity of 16GB/32GB/64GB) - - Use the built-in ECC module of the device itself - -3. Peripherals -- Up to 26 GPIO pins on the MilkV-Duo 40-pin header provide access to internal peripherals such as SDIO, I2C, PWM, SPI, J-TAG, and UART. -- Up to 3x I2C -- Up to 5x UART -- Up to 1x SDIO1 -- Up to 1x SPI -- Up to 2x ADC -- Up to 7x PWM -- Up to 1x RUN -- Up to 1x JTAG -- Integrated MAC PHY supporting 10/100Mbps full-duplex or half-duplex mode -- One USB Host / device interface - -## Toolchain Download -Download the `riscv64-unknown-linux-musl-gcc` toolchain from: [https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2) - -> Note: -The current BSP only supports Linux compilation. - -After correct extraction, add the local path of the `riscv64-unknown-linux-musl-gcc` toolchain to `EXEC_PATH` in `rtconfig.py`, or specify the path through the `RTT_EXEC_PATH` environment variable. - -```shell -$ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin -``` - -## Compilation -1. Installing Dependencies -```shell -$ sudo apt install -y device-tree-compiler -``` -On the Linux platform, you can execute: - -```shell -$ scons --menuconfig -``` -It will automatically download environment-related scripts to the ~/.env directory, and then execute -```shell -$ source ~/.env/env.sh -$ pkgs --update -``` - -After updating the software packages, use `scons -j10` or `scons -j10 --verbose` to compile this board support package. Alternatively, you can use the command `scons --exec-path="GCC_toolchain_path"` to specify the toolchain location for compilation. If the compilation is successful, an rtthread.elf file will be generated. - -After the compilation is completed, the script automatically calls the `./mksdimg.sh` script to package and generate the `boot.sd` file, which is the kernel file for SD card boot. - -## Running -1. Divide the SD card into 2 partitions, with the first partition used to store bin files and the second partition used as a data storage partition. The partition format is FAT32. - -2. Copy the `fip.bin` and `boot.sd` files from the root directory to the first partition of the SD card. For subsequent firmware updates, you only need to copy the `boot.sd` file. -Where: -- fip.bin: the bin file after fsbl、opensbi and U-Boot are packaged -- boot.sd: the bin file after the kernel is packaged - -After updating `boot.sd`, power on again and you will see the serial output information: - -```shell -U-Boot 2021.10 (Jun 26 2023 - 14:09:06 +0800)cvitek_cv180x - -DRAM: 63.3 MiB -gd->relocaddr=0x82435000. offset=0x2235000 -MMC: cv-sd@4310000: 0 -Loading Environment from ... OK -In: serial -Out: serial -Err: serial -Net: -Warning: ethernet@4070000 (eth0) using random MAC address - 62:80:19:6c:d4:64 -eth0: ethernet@4070000 -Hit any key to stop autoboot: 0 -Boot from SD ... -switch to partitions #0, OK -mmc0 is current device -132692 bytes read in 12 ms (10.5 MiB/s) -## Loading kernel from FIT Image at 81400000 ... - Using 'config-cv1800b_milkv_duo_sd' configuration - Trying 'kernel-1' kernel subimage - Verifying Hash Integrity ... crc32+ OK -## Loading fdt from FIT Image at 81400000 ... - Using 'config-cv1800b_milkv_duo_sd' configuration - Trying 'fdt-cv1800b_milkv_duo_sd' fdt subimage - Verifying Hash Integrity ... sha256+ OK - Booting using the fdt blob at 0x8141b590 - Uncompressing Kernel Image - Decompressing 296768 bytes used 42ms - Loading Device Tree to 0000000081be5000, end 0000000081becb60 ... OK - -Starting kernel ... - -heap: [0x802766b0 - 0x812766b0] - - \ | / -- RT - Thread Smart Operating System - / | \ 5.0.1 build Jun 28 2023 23:44:36 - 2006 - 2022 Copyright by RT-Thread team -Hello RT-Smart! -msh /> -``` -## Driver Support List - -| Driver | Support Status | Remarks | -| :----- | :------------- | :--------------------- | -| UART | Supported | Default baud rate 115200 | - -## Supported Development Boards -- milk-v duo: [https://milkv.io/duo](https://milkv.io/duo) - -## Contact information - -Maintenance person：[flyingcys](https://github.com/flyingcys) diff --git a/bsp/cvitek/cv1800b/mksdimg.sh b/bsp/cvitek/cv1800b/mksdimg.sh deleted file mode 100755 index 60dd65a076d..00000000000 --- a/bsp/cvitek/cv1800b/mksdimg.sh +++ /dev/null @@ -1,7 +0,0 @@ -#/bin/sh -set -e -echo "start compress kernel..." - -lzma -c -9 -f -k Image > Image.lzma - -./mkimage -f multi.its -r ../boot.sd \ No newline at end of file diff --git a/bsp/cvitek/cv18xx_aarch64/.config b/bsp/cvitek/cv18xx_aarch64/.config new file mode 100644 index 00000000000..969cda0784b --- /dev/null +++ b/bsp/cvitek/cv18xx_aarch64/.config @@ -0,0 +1,1156 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=8192 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +CONFIG_RT_KPRINTF_USING_LONGLONG=y +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_DEBUGING_PAGE_LEAK is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_PAGE_MAX_ORDER=11 +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_MEMTRACE=y +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +CONFIG_RT_USING_DEVICE_OPS=y +CONFIG_RT_USING_INTERRUPT_INFO=y +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_SCHED_THREAD_CTX=y +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50100 +CONFIG_RT_USING_STDC_ATOMIC=y +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 + +# +# AArch64 Architecture Configuration +# +CONFIG_ARCH_TEXT_OFFSET=0x200000 +CONFIG_ARCH_RAM_OFFSET=0x80000000 +CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096 +CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_CPU_64BIT=y +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_HW_ATOMIC is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_MM_MMU=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_MMU=y +CONFIG_ARCH_ARMV8=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=10 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=256 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FD_MAX=32 +# CONFIG_RT_USING_DFS_V1 is not set +CONFIG_RT_USING_DFS_V2=y +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +# CONFIG_RT_DFS_ELM_USE_EXFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_ROMFS_USER_ROOT is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=256 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_NULL=y +CONFIG_RT_USING_ZERO=y +CONFIG_RT_USING_RANDOM=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +CONFIG_RT_USING_PM=y +CONFIG_PM_TICKLESS_THRESHOLD_TIME=2 +# CONFIG_PM_USING_CUSTOM_CONFIG is not set +# CONFIG_PM_ENABLE_DEBUG is not set +# CONFIG_PM_ENABLE_SUSPEND_SLEEP_MODE is not set +# CONFIG_PM_ENABLE_THRESHOLD_SLEEP_MODE is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +CONFIG_RT_USING_DEV_BUS=y +# CONFIG_RT_USING_WIFI is not set +CONFIG_RT_USING_VIRTIO=y +CONFIG_RT_USING_VIRTIO10=y +CONFIG_RT_USING_VIRTIO_MMIO_ALIGN=y +CONFIG_RT_USING_VIRTIO_BLK=y +# CONFIG_RT_USING_VIRTIO_NET is not set +CONFIG_RT_USING_VIRTIO_CONSOLE=y +CONFIG_RT_USING_VIRTIO_CONSOLE_PORT_MAX_NR=4 +CONFIG_RT_USING_VIRTIO_GPU=y +CONFIG_RT_USING_VIRTIO_INPUT=y +CONFIG_RT_USING_PIN=y +CONFIG_RT_USING_KTIME=y +# CONFIG_RT_USING_HWTIMER is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +CONFIG_RT_USING_POSIX_FS=y +CONFIG_RT_USING_POSIX_DEVIO=y +CONFIG_RT_USING_POSIX_STDIO=y +CONFIG_RT_USING_POSIX_POLL=y +CONFIG_RT_USING_POSIX_SELECT=y +# CONFIG_RT_USING_POSIX_EVENTFD is not set +# CONFIG_RT_USING_POSIX_TIMERFD is not set +# CONFIG_RT_USING_POSIX_SOCKET is not set +CONFIG_RT_USING_POSIX_TERMIOS=y +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_POSIX_MMAN is not set +CONFIG_RT_USING_POSIX_DELAY=y +CONFIG_RT_USING_POSIX_CLOCK=y +CONFIG_RT_USING_POSIX_TIMER=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +CONFIG_RT_USING_POSIX_PIPE=y +CONFIG_RT_USING_POSIX_PIPE_SIZE=512 +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +CONFIG_RT_USING_RESOURCE_ID=y +CONFIG_RT_USING_ADT=y +CONFIG_RT_USING_ADT_AVL=y +CONFIG_RT_USING_ADT_BITMAP=y +CONFIG_RT_USING_ADT_HASHMAP=y +CONFIG_RT_USING_ADT_REF=y +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_NCNN is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# +CONFIG_SOC_CV18XX_AARCH64=y +CONFIG_BOARD_TYPE_MILKV_DUO256M=y +# CONFIG_BOARD_TYPE_MILKV_DUO256M_SPINOR is not set + +# +# General Drivers Configuration +# +CONFIG_BSP_SUPPORT_FPU=y +CONFIG_BSP_USING_GIC=y +CONFIG_BSP_USING_GICV2=y +# CONFIG_BSP_USING_GICV3 is not set +CONFIG_BSP_USING_UART=y +CONFIG_RT_USING_UART0=y +CONFIG_UART_IRQ_BASE=60 +# CONFIG_RT_USING_UART1 is not set +# CONFIG_RT_USING_UART2 is not set +# CONFIG_RT_USING_UART3 is not set +# CONFIG_RT_USING_UART4 is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_PWM is not set diff --git a/bsp/cvitek/cv18xx_aarch64/Kconfig b/bsp/cvitek/cv18xx_aarch64/Kconfig new file mode 100644 index 00000000000..ea607ee38a3 --- /dev/null +++ b/bsp/cvitek/cv18xx_aarch64/Kconfig @@ -0,0 +1,46 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_CV18XX_AARCH64 + bool + select ARCH_ARMV8 + select ARCH_CPU_64BIT + select ARCH_ARM_MMU + select RT_USING_CACHE + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select RT_USING_GIC + select BSP_USING_GIC + select ARCH_MM_MMU + default y + +choice + prompt "Board Type" + default BOARD_TYPE_MILKV_DUO256M + + config BOARD_TYPE_MILKV_DUO256M + bool "milkv-duo256m" + + config BOARD_TYPE_MILKV_DUO256M_SPINOR + bool "milkv-duo256m-spinor" + +endchoice + +source "$BSP_DIR/board/Kconfig" diff --git a/bsp/cvitek/cv18xx_aarch64/README.md b/bsp/cvitek/cv18xx_aarch64/README.md new file mode 100644 index 00000000000..4d85cb2d791 --- /dev/null +++ b/bsp/cvitek/cv18xx_aarch64/README.md @@ -0,0 +1,119 @@ +# Milkv-Duo256M 板级支持包说明 + +## 1. 简介 + +Milk-V Duo 256M 是 Duo 的升级版本，内存提升至 256M，满足需要更大内存容量的应用。采用 SG2002 计算系列芯片，计算能力提升至 1.0TOPS@INT8。它可以实现 RISC-V/ARM 架构之间的无缝切换，并支持双系统同时运行。此外，它还包含 SPI、UART 等一系列丰富的 GPIO 接口，适合边缘智能监控领域的各种硬件开发，包括 IP 摄像头、智能猫眼锁、可视门铃等。 + +该板级支持包主要是针对**ARM架构的大核**实现的一份移植，支持RT-Thread标准版和Smart版内核。 + +## 2. 编译说明 + +推荐使用ubuntu20的[env环境](https://github.com/RT-Thread/env)，当然也可以使用windows上的[env工具](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)进行编译。下面介绍**标准版**和**Smart版本**的编译流程。 + +### 2.1 RT-Thread编译 + +**1.menuconfig配置工程：** + +该BSP默认menuconfig支持的就是RT-Thread标准版，无需配置工程。 + +**2.配置工具链相关环境：** + +依次执行下面命令进行环境变量的相关配置： + +```shell +export RTT_CC=gcc +export RTT_EXEC_PATH="/opt/tools/gnu_gcc/arm-gnu-toolchain-13.2.Rel1-x86_64-aarch64-none-elf/bin" +export RTT_CC_PREFIX=aarch64-none-elf- +export PATH=$PATH:$RTT_EXEC_PATH +``` + +**3.编译：** + +```shell +scons -j12 +``` + +### 2.2 RT-Smart编译 + +**1.menuconfig配置工程：** + +```shell +RT-Thread Kernel ---> + [*] Enable RT-Thread Smart (microkernel on kernel/userland) +``` + +**2.配置工具链相关环境：** + +依次执行下面命令进行环境变量的相关配置： + +```shell +export RTT_CC=gcc +export RTT_EXEC_PATH="/opt/tools/gnu_gcc/aarch64-linux-musleabi_for_x86_64-pc-linux-gnu/bin" +export RTT_CC_PREFIX=aarch64-linux-musleabi- +export PATH=$PATH:$RTT_EXEC_PATH +``` + +**3.编译：** + +```shell +scons -j12 +``` + +如果编译正确无误，会产生 `rtthread.elf`, `rtthread.bin` 文件。 + +## 3. 运行 + +> 目前仅支持使用uboot对 `rtthread.bin` 文件进行加载，uboot对 `boot.sd` 的加载方式后续会实现。 + +1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。 + +2. 将bsp的boot目录下的 `fip.bin` 和编译生成的 `rtthread.bin` 复制 SD 卡第一个分区中。后续更新固件只需要复制 `rtthread.bin` 文件即可。 + +配置**串口0**参数： 115200 8N1 ，硬件和软件流控为关。 + +进入uboot命令行后依次输入以下命令。 + +```shell +fatload mmc 0:1 0x80200000 rtthread.bin +dcache flush +go 0x80200000 +``` + +> 0x80200000为rtthread.bin加载到内存的位置，可在menuconfig中自己修改，注意不能与小核固件加载位置重叠。 + +完成后可以看到串口的输出信息： + +**标准版log信息：** + +```shell +heap: [0x8028f2b0 - 0x84000000] + + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Apr 16 2024 00:05:56 + 2006 - 2024 Copyright by RT-Thread team +hello rt-thread! +msh /> +``` + +**Smart版log信息：** + +```shell +heap: [0x002f62c0 - 0x04000000] + + \ | / +- RT - Thread Smart Operating System + / | \ 5.1.0 build Apr 16 2024 00:04:47 + 2006 - 2024 Copyright by RT-Thread team +[E/lwp] lwp_startup: init program not found +Switching to legacy mode... +hello rt-thread! +msh /> +``` +## 4. 注意事项 + +目前RISC-V(Smart版本)支持外设物理地址映射到完全相同的虚拟地址，而ARM(Smart版本)目前是不支持这样搞的，所以在编写驱动的时候应该使用rt_ioremap这样的函数讲物理地址映射到可访问的虚拟地址上去。为了保证ARM的Smart版本内核能够成功运行，目前仅对uart和pinctrl的驱动进行了适配。其他驱动可能会因为未进行ioremap导致不可用。 + +## 5. 联系人信息 + +维护人：[liYony](https://github.com/liYony) diff --git a/bsp/cvitek/cv1800b/SConscript b/bsp/cvitek/cv18xx_aarch64/SConscript old mode 100755 new mode 100644 similarity index 100% rename from bsp/cvitek/cv1800b/SConscript rename to bsp/cvitek/cv18xx_aarch64/SConscript diff --git a/bsp/cvitek/cv18xx_aarch64/SConstruct b/bsp/cvitek/cv18xx_aarch64/SConstruct new file mode 100644 index 00000000000..1642f6ef13b --- /dev/null +++ b/bsp/cvitek/cv18xx_aarch64/SConstruct @@ -0,0 +1,53 @@ +import os +import sys +import rtconfig +import re + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT +TRACE_CONFIG = "" + +content = "" +with open("rtconfig.h") as f: + for line in f.readlines(): + if line.find("RT_BACKTRACE_FUNCTION_NAME") != -1: + for token in line.split(" "): + if re.match(r'RT_BACKTRACE_FUNCTION_NAME$', token, flags=0): + TRACE_CONFIG = " " + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS + TRACE_CONFIG, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS + TRACE_CONFIG, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS + TRACE_CONFIG, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] +env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group' + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/drivers'): + drivers_path_prefix = SDK_ROOT + '/drivers' +else: + drivers_path_prefix = os.path.dirname(SDK_ROOT) + '/drivers' + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# include libraries +objs.extend(SConscript(drivers_path_prefix + '/SConscript', variant_dir='build/drivers', duplicate=0)) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/cvitek/cv1800b/applications/SConscript b/bsp/cvitek/cv18xx_aarch64/applications/SConscript old mode 100755 new mode 100644 similarity index 100% rename from bsp/cvitek/cv1800b/applications/SConscript rename to bsp/cvitek/cv18xx_aarch64/applications/SConscript diff --git a/bsp/cvitek/cv18xx_aarch64/applications/main.c b/bsp/cvitek/cv18xx_aarch64/applications/main.c new file mode 100644 index 00000000000..d7414cd58a4 --- /dev/null +++ b/bsp/cvitek/cv18xx_aarch64/applications/main.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/10/7 bernard the first version + */ + +#include + +int main(void) +{ + rt_kprintf("hello rt-thread!\n"); + + return 0; +} diff --git a/bsp/cvitek/cv18xx_aarch64/board/Kconfig b/bsp/cvitek/cv18xx_aarch64/board/Kconfig new file mode 100755 index 00000000000..a7e559a1a40 --- /dev/null +++ b/bsp/cvitek/cv18xx_aarch64/board/Kconfig @@ -0,0 +1,87 @@ +menu "General Drivers Configuration" + config BSP_SUPPORT_FPU + bool "Using Float" + default y + + config BSP_USING_GIC + bool + default y + + choice + prompt "GIC Version" + default BSP_USING_GICV2 + + config BSP_USING_GICV2 + bool "GICv2" + + config BSP_USING_GICV3 + bool "GICv3" + endchoice + + menuconfig BSP_USING_UART + bool "Using UART" + select RT_USING_SERIAL + default y + + if BSP_USING_UART + config RT_USING_UART0 + bool "Enable UART 0" + default y + + config UART_IRQ_BASE + int + default 60 + + config RT_USING_UART1 + bool "Enable UART 1" + default n + + config RT_USING_UART2 + bool "Enable UART 2" + default n + + config RT_USING_UART3 + bool "Enable UART 3" + default n + + config RT_USING_UART4 + bool "Enable UART 4" + default n + + endif + + config BSP_USING_ADC + bool "Using ADC" + select RT_USING_ADC + default n + + config BSP_USING_SPI + bool "Using SPI" + select RT_USING_SPI + default n + + menuconfig BSP_USING_PWM + bool "Using PWM" + select RT_USING_PWM + default n + + if BSP_USING_PWM + config BSP_USING_PWM0 + bool "Enable PWM 0" + default n + + config BSP_USING_PWM1 + bool "Enable PWM 1" + default n + + config BSP_USING_PWM2 + bool "Enable PWM 2" + default n + + config BSP_USING_PWM3 + bool "Enable PWM 3" + default n + + endif + +endmenu diff --git a/bsp/cvitek/cv1800b/board/SConscript b/bsp/cvitek/cv18xx_aarch64/board/SConscript similarity index 100% rename from bsp/cvitek/cv1800b/board/SConscript rename to bsp/cvitek/cv18xx_aarch64/board/SConscript diff --git a/bsp/cvitek/cv18xx_aarch64/board/board.c b/bsp/cvitek/cv18xx_aarch64/board/board.c new file mode 100644 index 00000000000..ce4eb86dd38 --- /dev/null +++ b/bsp/cvitek/cv18xx_aarch64/board/board.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-15 liYony the first version + */ + +#include +#include +#include +#include +#include +#include + +extern size_t MMUTable[]; + +#ifdef RT_USING_SMART +struct mem_desc platform_mem_desc[] = { + {KERNEL_VADDR_START, KERNEL_VADDR_START + 0x0FFFFFFF, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM}, +}; +#else +struct mem_desc platform_mem_desc[] = +{ + {0x80200000, 0x90200000 - 1, 0x80200000, NORMAL_MEM}, /* memory size 256M */ + {0x01000000, 0x80000000 - 1, 0x01000000, DEVICE_MEM}, +}; +#endif + +const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]); + +void idle_wfi(void) +{ + asm volatile("wfi"); +} + +static rt_ubase_t pinmux_base = RT_NULL; + +void rt_hw_board_init(void) +{ +#ifdef RT_USING_SMART + rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET); +#else + rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xffffd0000000, 0x10000000, MMUTable, 0); +#endif + rt_region_t init_page_region; + init_page_region.start = PAGE_START; + init_page_region.end = PAGE_END; + rt_page_init(init_page_region); + + rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size); + +#ifdef RT_USING_HEAP + /* initialize system heap */ + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); + + /* initialize uart */ + rt_hw_uart_init(); + + /* initialize timer for os tick */ + rt_hw_gtimer_init(); + + rt_thread_idle_sethook(idle_wfi); +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + /* set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + rt_kprintf("heap: [0x%08x - 0x%08x]\n", HEAP_BEGIN, HEAP_END); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +rt_ubase_t pinmux_base_ioremap(void) +{ + if (pinmux_base == RT_NULL) + { + pinmux_base = (rt_size_t)rt_ioremap((void*)0x03001000, 0x1000); + } + + return pinmux_base; +} diff --git a/bsp/cvitek/cv18xx_aarch64/board/board.h b/bsp/cvitek/cv18xx_aarch64/board/board.h new file mode 100644 index 00000000000..c38920b19a0 --- /dev/null +++ b/bsp/cvitek/cv18xx_aarch64/board/board.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-15 liYony the first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +extern unsigned char __bss_end; + +#define HEAP_BEGIN ((void*)&__bss_end) + +#ifdef RT_USING_SMART +#define HEAP_END ((size_t)KERNEL_VADDR_START + 64 * 1024 * 1024) +#define PAGE_START HEAP_END +#define PAGE_END ((size_t)KERNEL_VADDR_START + 128 * 1024 * 1024) +#else +#define HEAP_END (ARCH_RAM_OFFSET + 64 * 1024 * 1024) +#define PAGE_START HEAP_END +#define PAGE_END ((size_t)PAGE_START + 64 * 1024 * 1024) +#endif + +void rt_hw_board_init(void); + +int rt_hw_uart_init(void); + +#endif /* __BOARD_H__ */ diff --git a/bsp/cvitek/cv18xx_aarch64/board/cv18xx.h b/bsp/cvitek/cv18xx_aarch64/board/cv18xx.h new file mode 100644 index 00000000000..bf7b52631ec --- /dev/null +++ b/bsp/cvitek/cv18xx_aarch64/board/cv18xx.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-15 liYony the first version + */ + +#ifndef __CV18XX_H__ +#define __CV18XX_H__ + +#include +#include + +#ifdef RT_USING_SMART +#include +#endif + +#define __REG32(x) (*((volatile unsigned int *)(x))) +#define __REG16(x) (*((volatile unsigned short *)(x))) + +/* GIC */ +#define MAX_HANDLERS 116 +#define GIC_IRQ_START 0 +#define ARM_GIC_NR_IRQS 116 +#define ARM_GIC_MAX_NR 1 + +/* GICv2 */ +#define GIC400_DISTRIBUTOR_PPTR 0x01F01000U +#define GIC400_CONTROLLER_PPTR 0x01F02000U +#define GIC400_SIZE 0x00001000U + +/* the basic constants and interfaces needed by gic */ +rt_inline rt_ubase_t platform_get_gic_dist_base(void) +{ + return GIC400_DISTRIBUTOR_PPTR; +} + +rt_inline rt_ubase_t platform_get_gic_cpu_base(void) +{ + return GIC400_CONTROLLER_PPTR; +} + +#endif /* __CV18XX_H__ */ diff --git a/bsp/cvitek/cv18xx_aarch64/boot/fip.bin b/bsp/cvitek/cv18xx_aarch64/boot/fip.bin new file mode 100644 index 00000000000..c406223010f Binary files /dev/null and b/bsp/cvitek/cv18xx_aarch64/boot/fip.bin differ diff --git a/bsp/cvitek/cv18xx_aarch64/rtconfig.h b/bsp/cvitek/cv18xx_aarch64/rtconfig.h new file mode 100644 index 00000000000..2d35ff261c7 --- /dev/null +++ b/bsp/cvitek/cv18xx_aarch64/rtconfig.h @@ -0,0 +1,342 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 16 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 8192 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 8192 + +/* kservice optimization */ + +#define RT_KSERVICE_USING_STDLIB +#define RT_KPRINTF_USING_LONGLONG +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_PAGE_MAX_ORDER 11 +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_MEMHEAP_AUTO_BINDING +#define RT_USING_MEMTRACE +#define RT_USING_HEAP +#define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS +#define RT_USING_INTERRUPT_INFO +#define RT_USING_SCHED_THREAD_CTX +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50100 +#define RT_USING_STDC_ATOMIC +#define RT_BACKTRACE_LEVEL_MAX_NR 32 + +/* AArch64 Architecture Configuration */ + +#define ARCH_TEXT_OFFSET 0x200000 +#define ARCH_RAM_OFFSET 0x80000000 +#define ARCH_SECONDARY_CPU_STACK_SIZE 4096 +#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS +#define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define RT_USING_CPU_FFS +#define ARCH_MM_MMU +#define ARCH_ARM +#define ARCH_ARM_MMU +#define ARCH_ARMV8 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 8192 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 10 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 256 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 32 +#define RT_USING_DFS_V2 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_ROMFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 256 +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_RANDOM +#define RT_USING_PM +#define PM_TICKLESS_THRESHOLD_TIME 2 +#define RT_USING_DEV_BUS +#define RT_USING_VIRTIO +#define RT_USING_VIRTIO10 +#define RT_USING_VIRTIO_MMIO_ALIGN +#define RT_USING_VIRTIO_BLK +#define RT_USING_VIRTIO_CONSOLE +#define RT_USING_VIRTIO_CONSOLE_PORT_MAX_NR 4 +#define RT_USING_VIRTIO_GPU +#define RT_USING_VIRTIO_INPUT +#define RT_USING_PIN +#define RT_USING_KTIME + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + +#define RT_USING_POSIX_FS +#define RT_USING_POSIX_DEVIO +#define RT_USING_POSIX_STDIO +#define RT_USING_POSIX_POLL +#define RT_USING_POSIX_SELECT +#define RT_USING_POSIX_TERMIOS +#define RT_USING_POSIX_DELAY +#define RT_USING_POSIX_CLOCK +#define RT_USING_POSIX_TIMER + +/* Interprocess Communication (IPC) */ + +#define RT_USING_POSIX_PIPE +#define RT_USING_POSIX_PIPE_SIZE 512 + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Memory protection */ + + +/* Utilities */ + +#define RT_USING_RESOURCE_ID +#define RT_USING_ADT +#define RT_USING_ADT_AVL +#define RT_USING_ADT_BITMAP +#define RT_USING_ADT_HASHMAP +#define RT_USING_ADT_REF + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* BL808 WiFi */ + + +/* CYW43439 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + + +/* Kendryte SDK */ + + +/* sensors drivers */ + + +/* touch drivers */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +#define SOC_CV18XX_AARCH64 +#define BOARD_TYPE_MILKV_DUO256M + +/* General Drivers Configuration */ + +#define BSP_SUPPORT_FPU +#define BSP_USING_GIC +#define BSP_USING_GICV2 +#define BSP_USING_UART +#define RT_USING_UART0 +#define UART_IRQ_BASE 60 + +#endif diff --git a/bsp/cvitek/cv18xx_aarch64/rtconfig.py b/bsp/cvitek/cv18xx_aarch64/rtconfig.py new file mode 100644 index 00000000000..c363513a185 --- /dev/null +++ b/bsp/cvitek/cv18xx_aarch64/rtconfig.py @@ -0,0 +1,47 @@ +import os + +# toolchains options +ARCH ='aarch64' +CPU ='cortex-a' +CROSS_TOOL = 'gcc' +PLATFORM = 'gcc' +EXEC_PATH = os.getenv('RTT_EXEC_PATH') or '/usr/bin' +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + CPP = PREFIX + 'cpp' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + CFPFLAGS = ' ' + AFPFLAGS = ' ' + DEVICE = ' -march=armv8-a -mtune=cortex-a53 -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing' + + CPPFLAGS= ' -E -P -x assembler-with-cpp' + CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall -fdiagnostics-color=always' + CFLAGS = DEVICE + CFPFLAGS + ' -Wall -Wno-cpp -std=gnu99 -fdiagnostics-color=always' + AFLAGS = ' -c' + AFPFLAGS + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + ' -lsupc++ -lgcc -static' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + CXXFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -Os' + CXXFLAGS += ' -Os' + CXXFLAGS += ' -Woverloaded-virtual -fno-exceptions -fno-rtti' + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/cvitek/cv1800b/.config b/bsp/cvitek/cv18xx_risc-v/.config similarity index 96% rename from bsp/cvitek/cv1800b/.config rename to bsp/cvitek/cv18xx_risc-v/.config index fd58346a239..c2da459eee4 100644 --- a/bsp/cvitek/cv1800b/.config +++ b/bsp/cvitek/cv18xx_risc-v/.config @@ -8,7 +8,7 @@ # CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set -CONFIG_RT_USING_SMART=y +# CONFIG_RT_USING_SMART is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_AMP is not set # CONFIG_RT_USING_SMP is not set @@ -25,10 +25,10 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_IDLE_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 # # kservice optimization @@ -89,7 +89,6 @@ CONFIG_RT_USING_CACHE=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # CONFIG_RT_USING_CPU_FFS is not set CONFIG_ARCH_MM_MMU=y -CONFIG_KERNEL_VADDR_START=0x80000000 CONFIG_ARCH_RISCV=y CONFIG_ARCH_RISCV64=y @@ -98,7 +97,7 @@ CONFIG_ARCH_RISCV64=y # CONFIG_RT_USING_COMPONENTS_INIT=y CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=6144 +CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192 CONFIG_RT_MAIN_THREAD_PRIORITY=10 # CONFIG_RT_USING_LEGACY is not set CONFIG_RT_USING_MSH=y @@ -125,6 +124,7 @@ CONFIG_RT_USING_DFS=y CONFIG_DFS_USING_POSIX=y CONFIG_DFS_USING_WORKDIR=y CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_V1 is not set CONFIG_RT_USING_DFS_V2=y # CONFIG_RT_USING_DFS_ELMFAT is not set CONFIG_RT_USING_DFS_DEVFS=y @@ -132,17 +132,6 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_TMPFS is not set # CONFIG_RT_USING_DFS_MQUEUE is not set -CONFIG_RT_USING_PAGECACHE=y - -# -# page cache config -# -CONFIG_RT_PAGECACHE_COUNT=4096 -CONFIG_RT_PAGECACHE_ASPACE_COUNT=1024 -CONFIG_RT_PAGECACHE_PRELOAD=4 -CONFIG_RT_PAGECACHE_HASH_NR=1024 -CONFIG_RT_PAGECACHE_GC_WORK_LEVEL=90 -CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70 # CONFIG_RT_USING_FAL is not set # @@ -152,15 +141,13 @@ CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70 CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y -CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192 CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 -CONFIG_RT_USING_TTY=y -# CONFIG_RT_TTY_DEBUG is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set @@ -224,11 +211,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 CONFIG_RT_USING_POSIX_FS=y CONFIG_RT_USING_POSIX_DEVIO=y CONFIG_RT_USING_POSIX_STDIO=y -# CONFIG_RT_USING_POSIX_POLL is not set +CONFIG_RT_USING_POSIX_POLL=y # CONFIG_RT_USING_POSIX_SELECT is not set # CONFIG_RT_USING_POSIX_EVENTFD is not set -# CONFIG_RT_USING_POSIX_EPOLL is not set -# CONFIG_RT_USING_POSIX_SIGNALFD is not set # CONFIG_RT_USING_POSIX_TIMERFD is not set # CONFIG_RT_USING_POSIX_SOCKET is not set CONFIG_RT_USING_POSIX_TERMIOS=y @@ -281,23 +266,6 @@ CONFIG_RT_USING_ADT_HASHMAP=y CONFIG_RT_USING_ADT_REF=y # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set -CONFIG_RT_USING_LWP=y -# CONFIG_LWP_DEBUG is not set -CONFIG_RT_LWP_MAX_NR=30 -CONFIG_LWP_TASK_STACK_SIZE=16384 -CONFIG_RT_CH_MSG_MAX_NR=1024 -CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 -CONFIG_LWP_TID_MAX_NR=64 -CONFIG_RT_LWP_SHM_MAX_NR=64 -# CONFIG_LWP_UNIX98_PTY is not set -CONFIG_RT_USING_LDSO=y -# CONFIG_ELF_DEBUG_ENABLE is not set -# CONFIG_ELF_LOAD_RANDOMIZE is not set - -# -# Memory management -# -# CONFIG_RT_USING_MEMBLOCK is not set # # RT-Thread Utestcases @@ -1129,9 +1097,14 @@ CONFIG_UART_IRQ_BASE=44 # CONFIG_RT_USING_UART3 is not set # CONFIG_RT_USING_UART4 is not set # CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_PWM is not set -CONFIG_BSP_USING_CV1800B=y +CONFIG_BSP_USING_CV18XX=y CONFIG_C906_PLIC_PHY_ADDR=0x70000000 CONFIG_IRQ_MAX_NR=64 CONFIG_TIMER_CLK_FREQ=25000000 -CONFIG___STACKSIZE__=4096 +CONFIG___STACKSIZE__=8192 +# CONFIG_BOARD_TYPE_MILKV_DUO is not set +# CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR is not set +CONFIG_BOARD_TYPE_MILKV_DUO256M=y +# CONFIG_BOARD_TYPE_MILKV_DUO256M_SPINOR is not set diff --git a/bsp/cvitek/cv18xx_risc-v/.gitignore b/bsp/cvitek/cv18xx_risc-v/.gitignore new file mode 100755 index 00000000000..5a70c2b55ff --- /dev/null +++ b/bsp/cvitek/cv18xx_risc-v/.gitignore @@ -0,0 +1,2 @@ +dtb/ +Image \ No newline at end of file diff --git a/bsp/cvitek/cv1800b/Kconfig b/bsp/cvitek/cv18xx_risc-v/Kconfig similarity index 67% rename from bsp/cvitek/cv1800b/Kconfig rename to bsp/cvitek/cv18xx_risc-v/Kconfig index 18394dca61a..19774422733 100755 --- a/bsp/cvitek/cv1800b/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/Kconfig @@ -19,7 +19,7 @@ source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" source "board/Kconfig" -config BSP_USING_CV1800B +config BSP_USING_CV18XX bool select ARCH_RISCV64 select RT_USING_SYSTEM_WORKQUEUE @@ -45,3 +45,21 @@ config TIMER_CLK_FREQ config __STACKSIZE__ int "stack size for interrupt" default 4096 + +choice + prompt "Board Type" + default BOARD_TYPE_MILKV_DUO256M + + config BOARD_TYPE_MILKV_DUO + bool "milkv-duo" + + config BOARD_TYPE_MILKV_DUO_SPINOR + bool "milkv-duo-spinor" + + config BOARD_TYPE_MILKV_DUO256M + bool "milkv-duo256m" + + config BOARD_TYPE_MILKV_DUO256M_SPINOR + bool "milkv-duo256m-spinor" + +endchoice diff --git a/bsp/cvitek/cv1800b/README.md b/bsp/cvitek/cv18xx_risc-v/README.md similarity index 57% rename from bsp/cvitek/cv1800b/README.md rename to bsp/cvitek/cv18xx_risc-v/README.md index 9293cf2e29f..336b6439acf 100755 --- a/bsp/cvitek/cv1800b/README.md +++ b/bsp/cvitek/cv18xx_risc-v/README.md @@ -1,7 +1,7 @@ **中文** | [English](README_en.md) ## 概述 -CV180ZB/CV1800B/CV1801B 是面向民用消费监控 IP 摄像机、居家智能等多项产品领域而推出的高性能、低功耗芯片，集成了 H.264/H.265 视频压缩编码器和 ISP；支持数字寛动态、 3D 降噪、除雾、镜头畸变校正等多种图像增强和矫正算法，为客户提供专业级的视频图像质量。 +CV18xx 系列芯片面向民用消费监控 IP 摄像机、居家智能等多项产品领域而推出的高性能、低功耗芯片，集成了 H.264/H.265 视频压缩编码器和 ISP；支持数字寛动态、 3D 降噪、除雾、镜头畸变校正等多种图像增强和矫正算法，为客户提供专业级的视频图像质量。 1. 处理器内核 @@ -34,34 +34,62 @@ CV180ZB/CV1800B/CV1801B 是面向民用消费监控 IP 摄像机、居家智能 - 一个 USB Host / device 接口 ## Toolchain 下载 -下载 `riscv64-unknown-linux-musl-gcc` 的工具链: [https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2) +1. RT-Thread 标准版工具链：`riscv64-unknown-elf-gcc` 下载地址 [https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz](https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz) + +2. RT-Smart 版工具链： `riscv64-unknown-linux-musl-gcc` 下载地址 [https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2) > 注： -当前 bsp 只支持 Linux 编译 +当前 bsp 只支持 Linux 编译，推荐 ubuntu 22.04 -正确解压后，在`rtconfig.py`中将 `riscv64-unknown-linux-musl-gcc` 工具链的本地路径加入 `EXEC_PATH` 或通过 `RTT_EXEC_PATH` 环境变量指定路径。 +正确解压后，在`rtconfig.py`中将 `riscv64-unknown-elf-gcc` 或 `riscv64-unknown-linux-musl-gcc` 工具链的本地路径加入 `EXEC_PATH` 或通过 `RTT_EXEC_PATH` 环境变量指定路径。 ```shell +# RT-Thread 标准版按照以下配置： +$ export RTT_CC_PREFIX=riscv64-unknown-elf- +$ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin + +# RT-Samrt 版按照以下配置： +$ export RTT_CC_PREFIX=riscv64-unknown-linux-musl- $ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin ``` ## 编译 -1. 依赖安装 +### 依赖安装 ```shell -$ sudo apt install -y device-tree-compiler +$ sudo apt install -y scons libncurses5-dev device-tree-compiler ``` -2. Linux平台下，可以先执行： + +## 修改当前工程配置 + +Linux平台下，执行： ```shell $ scons --menuconfig ``` +1. 默认编译为 RT-Thread 标准版，如果需要编译为 RT-Smart 版，请按照如下方式修改： +```shell +RT-Thread Kernel ---> + [*] Enable RT-Thread Smart (microkernel on kernel/userland) + + (0x80000000) The virtural address of kernel start +``` + +2. 选择当前需要编译的目标开发板类型： +```shell +Board Type (milkv-duo) ---> + ( ) milkv-duo + ( ) milkv-duo-spinor + (X) milkv-duo256m + ( ) milkv-duo256m-spinor +``` + 它会自动下载env相关脚本到~/.env目录，然后执行 ```shell $ source ~/.env/env.sh $ pkgs --update ``` -更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf文件。 +更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包，编译正确无误，会产生 rtthread.elf 文件。 编译完成后脚本自动调用 `./mksdimg.sh` 脚本进行打包，并生成 `boot.sd`, 该文件即为 SD 卡启动的 kernel 文件。 @@ -110,22 +138,9 @@ Starting kernel ... heap: [0x802766b0 - 0x812766b0] \ | / -- RT - Thread Smart Operating System - / | \ 5.0.1 build Jun 28 2023 23:44:36 - 2006 - 2022 Copyright by RT-Thread team -Hello RT-Smart! +- RT - Thread Operating System + / | \ 5.1.0 build Apr 7 2024 23:33:20 + 2006 - 2024 Copyright by RT-Thread team +Hello RISC-V! msh /> ``` -## 驱动支持列表 - -| 驱动 | 支持情况 | 备注 | -| :--- | :------- | :---------------- | -| UART | 支持 | 默认波特率115200 | - - -## 支持开发板 -- milk-v duo: [https://milkv.io/duo](https://milkv.io/duo) - -## 联系人信息 - -维护人：[flyingcys](https://github.com/flyingcys) \ No newline at end of file diff --git a/bsp/cvitek/cv18xx_risc-v/README_en.md b/bsp/cvitek/cv18xx_risc-v/README_en.md new file mode 100755 index 00000000000..3b19462de00 --- /dev/null +++ b/bsp/cvitek/cv18xx_risc-v/README_en.md @@ -0,0 +1,145 @@ +[中文](README.md) | **English** + +## Overview +The CV18xx series of chips are high-performance, low-power chips launched for various products in the field of civilian consumer surveillance IP cameras, smart homes, and more. These chips integrate H.264/H.265 video compression encoders, as well as ISP; they support various image enhancement and correction algorithms such as digital wide dynamic range, 3D noise reduction, defogging, and lens distortion correction, providing customers with professional-level video image quality. + +1. Processor Core +- Main Processor: RISC-V C906 @ 1.0Ghz + - 32KB I-cache, 64KB D-Cache + - Integrated Vector and Floating-Point Unit (FPU). +- Co-processor: RISC-V C906 @ 700Mhz + - Integrated Floating-Point Unit (FPU) + +2. Storage Interface +- Built-in DRAM: DDR2 16bitx1, with a maximum speed of 1333Mbps, and a capacity of 512Mbit (64MB) +- Support for SPI NOR flash interface (1.8V / 3.0V) + - Supports 1, 2, 4 line modes + - Maximum support of 256MByte +- Support for SPI Nand flash interface (1.8V / 3.0V) + - Supports 1KB/2KB/4KB page (corresponding to maximum capacity of 16GB/32GB/64GB) + - Utilizes the device's built-in ECC module + +3. Peripherals +- Up to 26 GPIO pins on the MilkV-Duo 40-pin header provide access to internal peripherals such as SDIO, I2C, PWM, SPI, J-TAG, and UART +- Up to 3x I2C +- Up to 5x UART +- Up to 1x SDIO1 +- Up to 1x SPI +- Up to 2x ADC +- Up to 7x PWM +- Up to 1x RUN +- Up to 1x JTAG +- Integrated MAC PHY supports 10/100Mbps full or half duplex mode +- One USB host/device interface + +## Toolchain Download +1. RT-Thread Standard Edition Toolchain: `riscv64-unknown-elf-gcc` Download Link [https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz](https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz) + +2. RT-Smart Edition Toolchain: `riscv64-unknown-linux-musl-gcc` Download Link [https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2) + +> Note: +The current bsp only supports Linux compilation, and it is recommended to use Ubuntu 22.04 + +After correctly extracting, add the local path of the `riscv64-unknown-elf-gcc` or `riscv64-unknown-linux-musl-gcc` toolchain to `EXEC_PATH` in `rtconfig.py` or specify the path through the `RTT_EXEC_PATH` environment variable. + +```shell +# For RT-Thread Standard Edition, use the following configuration: +$ export RTT_CC_PREFIX=riscv64-unknown-elf- +$ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin + +# For RT-Smart Edition, use the following configuration: +$ export RTT_CC_PREFIX=riscv64-unknown-linux-musl- +$ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin +``` + +## Compilation + +### Dependency Installation +```shell +$ sudo apt install -y scons libncurses5-dev device-tree-compiler +``` + +## Modify Current Project Configuration + +For the Linux platform, execute: +```shell +$ scons --menuconfig +``` + +1. By default, compile as RT-Thread Standard Edition. If you need to compile as RT-Smart Edition, modify as follows: +```shell +RT-Thread Kernel ---> + [*] Enable RT-Thread Smart (microkernel on kernel/userland) + + (0x80000000) The virtual address of kernel start +``` + +2. Select the current target development board type: +```shell +Board Type (milkv-duo) ---> + ( ) milkv-duo + ( ) milkv-duo-spinor + (X) milkv-duo256m + ( ) milkv-duo256m-spinor +``` + +It will automatically download relevant scripts to the ~/.env directory, then execute: +```shell +$ source ~/.env/env.sh +$ pkgs --update +``` +After updating the software package, execute `scons -j10` or `scons -j10 --verbose` to compile this board support package. If the compilation is successful, an rtthread.elf file will be generated. + +After the compilation is complete, the script automatically calls the `./mksdimg.sh` script to package and generate `boot.sd`, which is the kernel file for SD card startup. + +## Running +1. Divide the SD card into 2 partitions, with the first partition used to store bin files, and the second partition used as a data storage partition, with `FAT32` format. +2. Copy the `fip.bin` and `boot.sd` files from the root directory to the first partition of the SD card. Subsequent firmware updates only require copying the `boot.sd` file. +Where: +- fip.bin: fsbl, opensbi, and uboot packaged bin file +- boot.sd: kernel packaged bin file + +After updating `boot.sd`, restart to see the serial port output: + +```shell +U-Boot 2021.10 (Jun 26 2023 - 14:09:06 +0800)cvitek_cv180x + +DRAM: 63.3 MiB +gd->relocaddr=0x82435000. offset=0x2235000 +MMC: cv-sd@4310000: 0 +Loading Environment from ... OK +In: serial +Out: serial +Err: serial +Net: +Warning: ethernet@4070000 (eth0) using random MAC address - 62:80:19:6c:d4:64 +eth0: ethernet@4070000 +Hit any key to stop autoboot: 0 +Boot from SD ... +switch to partitions #0, OK +mmc0 is current device +132692 bytes read in 12 ms (10.5 MiB/s) +## Loading kernel from FIT Image at 81400000 ... + Using 'config-cv1800b_milkv_duo_sd' configuration + Trying 'kernel-1' kernel subimage + Verifying Hash Integrity ... crc32+ OK +## Loading fdt from FIT Image at 81400000 ... + Using 'config-cv1800b_milkv_duo_sd' configuration + Trying 'fdt-cv1800b_milkv_duo_sd' fdt subimage + Verifying Hash Integrity ... sha256+ OK + Booting using the fdt blob at 0x8141b590 + Uncompressing Kernel Image + Decompressing 296768 bytes used 42ms + Loading Device Tree to 0000000081be5000, end 0000000081becb60 ... OK + +Starting kernel ... + +heap: [0x802766b0 - 0x812766b0] + + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Apr 7 2024 23:33:20 + 2006 - 2024 Copyright by RT-Thread team +Hello RISC-V! +msh /> +``` \ No newline at end of file diff --git a/bsp/cvitek/cv18xx_risc-v/SConscript b/bsp/cvitek/cv18xx_risc-v/SConscript new file mode 100755 index 00000000000..c7ef7659ece --- /dev/null +++ b/bsp/cvitek/cv18xx_risc-v/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/cvitek/cv1800b/SConstruct b/bsp/cvitek/cv18xx_risc-v/SConstruct similarity index 100% rename from bsp/cvitek/cv1800b/SConstruct rename to bsp/cvitek/cv18xx_risc-v/SConstruct diff --git a/bsp/cvitek/cv18xx_risc-v/applications/SConscript b/bsp/cvitek/cv18xx_risc-v/applications/SConscript new file mode 100755 index 00000000000..c583d3016e0 --- /dev/null +++ b/bsp/cvitek/cv18xx_risc-v/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/cvitek/cv1800b/applications/main.c b/bsp/cvitek/cv18xx_risc-v/applications/main.c similarity index 81% rename from bsp/cvitek/cv1800b/applications/main.c rename to bsp/cvitek/cv18xx_risc-v/applications/main.c index a8afc8b0f92..16417b5d08c 100755 --- a/bsp/cvitek/cv1800b/applications/main.c +++ b/bsp/cvitek/cv18xx_risc-v/applications/main.c @@ -13,7 +13,10 @@ int main(void) { +#ifdef RT_USING_SMART rt_kprintf("Hello RT-Smart!\n"); - +#else + rt_kprintf("Hello RISC-V!\n"); +#endif return 0; } diff --git a/bsp/cvitek/cv1800b/board/Kconfig b/bsp/cvitek/cv18xx_risc-v/board/Kconfig similarity index 93% rename from bsp/cvitek/cv1800b/board/Kconfig rename to bsp/cvitek/cv18xx_risc-v/board/Kconfig index 82f7886f098..a743c804dea 100755 --- a/bsp/cvitek/cv1800b/board/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/board/Kconfig @@ -37,6 +37,11 @@ menu "General Drivers Configuration" select RT_USING_ADC default n + config BSP_USING_SPI + bool "Using SPI" + select RT_USING_SPI + default n + menuconfig BSP_USING_PWM bool "Using PWM" select RT_USING_PWM diff --git a/bsp/cvitek/cv18xx_risc-v/board/SConscript b/bsp/cvitek/cv18xx_risc-v/board/SConscript new file mode 100755 index 00000000000..4488cae0736 --- /dev/null +++ b/bsp/cvitek/cv18xx_risc-v/board/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') +CPPPATH = [cwd] + +group = DefineGroup('Driver', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/cvitek/cv1800b/board/board.c b/bsp/cvitek/cv18xx_risc-v/board/board.c similarity index 100% rename from bsp/cvitek/cv1800b/board/board.c rename to bsp/cvitek/cv18xx_risc-v/board/board.c diff --git a/bsp/cvitek/cv1800b/board/board.h b/bsp/cvitek/cv18xx_risc-v/board/board.h similarity index 100% rename from bsp/cvitek/cv1800b/board/board.h rename to bsp/cvitek/cv18xx_risc-v/board/board.h diff --git a/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo-spinor/cv1800b_milkv_duo_spinor.dtb b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo-spinor/cv1800b_milkv_duo_spinor.dtb new file mode 100755 index 00000000000..5275da07d2f Binary files /dev/null and b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo-spinor/cv1800b_milkv_duo_spinor.dtb differ diff --git a/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo-spinor/multi.its b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo-spinor/multi.its new file mode 100755 index 00000000000..5dfcc9d0aaf --- /dev/null +++ b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo-spinor/multi.its @@ -0,0 +1,56 @@ +/* + * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs + */ + +/dts-v1/; + +/ { + description = "Various kernels, ramdisks and FDT blobs"; + #address-cells = <2>; + + images { + kernel-1 { + description = "cvitek kernel"; + data = /incbin/("./Image.lzma"); + type = "kernel"; + arch = "riscv"; + os = "linux"; + compression = "lzma"; + load = <0x0 0x80200000>; + entry = <0x0 0x80200000>; + hash-2 { + algo = "crc32"; + }; + }; + + + /*FDT*/ + + fdt-cv1800b_milkv_duo_spinor { + description = "cvitek device tree - cv1800b_milkv_duo_spinor"; + data = /incbin/("./cv1800b_milkv_duo_spinor.dtb"); + type = "flat_dt"; + arch = "riscv"; + compression = "none"; + hash-1 { + algo = "sha256"; + }; + }; + + + + }; + + /*CFG*/ + configurations { + + config-cv1800b_milkv_duo_spinor { + description = "boot cvitek system with board cv1800b_milkv_duo_spinor"; + kernel = "kernel-1"; + fdt = "fdt-cv1800b_milkv_duo_spinor"; + }; + + }; + + +}; diff --git a/bsp/cvitek/cv1800b/cv1800b_milkv_duo_sd.dtb b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo/cv1800b_milkv_duo_sd.dtb similarity index 100% rename from bsp/cvitek/cv1800b/cv1800b_milkv_duo_sd.dtb rename to bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo/cv1800b_milkv_duo_sd.dtb diff --git a/bsp/cvitek/cv1800b/multi.its b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo/multi.its similarity index 100% rename from bsp/cvitek/cv1800b/multi.its rename to bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo/multi.its diff --git a/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m-spinor/cv1812cp_milkv_duo256m_spinor.dtb b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m-spinor/cv1812cp_milkv_duo256m_spinor.dtb new file mode 100755 index 00000000000..e48fe8e3115 Binary files /dev/null and b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m-spinor/cv1812cp_milkv_duo256m_spinor.dtb differ diff --git a/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m-spinor/multi.its b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m-spinor/multi.its new file mode 100755 index 00000000000..23f546482cd --- /dev/null +++ b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m-spinor/multi.its @@ -0,0 +1,56 @@ +/* + * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs + */ + +/dts-v1/; + +/ { + description = "Various kernels, ramdisks and FDT blobs"; + #address-cells = <2>; + + images { + kernel-1 { + description = "cvitek kernel"; + data = /incbin/("./Image.lzma"); + type = "kernel"; + arch = "riscv"; + os = "linux"; + compression = "lzma"; + load = <0x0 0x80200000>; + entry = <0x0 0x80200000>; + hash-2 { + algo = "crc32"; + }; + }; + + + /*FDT*/ + + fdt-cv1812cp_milkv_duo256m_spinor { + description = "cvitek device tree - cv1812cp_milkv_duo256m_spinor"; + data = /incbin/("./cv1812cp_milkv_duo256m_spinor.dtb"); + type = "flat_dt"; + arch = "riscv"; + compression = "none"; + hash-1 { + algo = "sha256"; + }; + }; + + + + }; + + /*CFG*/ + configurations { + + config-cv1812cp_milkv_duo256m_spinor { + description = "boot cvitek system with board cv1812cp_milkv_duo256m_spinor"; + kernel = "kernel-1"; + fdt = "fdt-cv1812cp_milkv_duo256m_spinor"; + }; + + }; + + +}; diff --git a/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m/cv1812cp_milkv_duo256m_sd.dtb b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m/cv1812cp_milkv_duo256m_sd.dtb new file mode 100755 index 00000000000..01af66027b5 Binary files /dev/null and b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m/cv1812cp_milkv_duo256m_sd.dtb differ diff --git a/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m/multi.its b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m/multi.its new file mode 100755 index 00000000000..5e01397d554 --- /dev/null +++ b/bsp/cvitek/cv18xx_risc-v/dtb/milkv-duo256m/multi.its @@ -0,0 +1,56 @@ +/* + * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs + */ + +/dts-v1/; + +/ { + description = "Various kernels, ramdisks and FDT blobs"; + #address-cells = <2>; + + images { + kernel-1 { + description = "cvitek kernel"; + data = /incbin/("./Image.lzma"); + type = "kernel"; + arch = "riscv"; + os = "linux"; + compression = "lzma"; + load = <0x0 0x80200000>; + entry = <0x0 0x80200000>; + hash-2 { + algo = "crc32"; + }; + }; + + + /*FDT*/ + + fdt-cv1812cp_milkv_duo256m_sd { + description = "cvitek device tree - cv1812cp_milkv_duo256m_sd"; + data = /incbin/("./cv1812cp_milkv_duo256m_sd.dtb"); + type = "flat_dt"; + arch = "riscv"; + compression = "none"; + hash-1 { + algo = "sha256"; + }; + }; + + + + }; + + /*CFG*/ + configurations { + + config-cv1812cp_milkv_duo256m_sd { + description = "boot cvitek system with board cv1812cp_milkv_duo256m_sd"; + kernel = "kernel-1"; + fdt = "fdt-cv1812cp_milkv_duo256m_sd"; + }; + + }; + + +}; diff --git a/bsp/cvitek/cv1800b/link.lds b/bsp/cvitek/cv18xx_risc-v/link.lds similarity index 100% rename from bsp/cvitek/cv1800b/link.lds rename to bsp/cvitek/cv18xx_risc-v/link.lds diff --git a/bsp/cvitek/cv1800b/link_stacksize.lds b/bsp/cvitek/cv18xx_risc-v/link_stacksize.lds similarity index 100% rename from bsp/cvitek/cv1800b/link_stacksize.lds rename to bsp/cvitek/cv18xx_risc-v/link_stacksize.lds diff --git a/bsp/cvitek/cv1800b/rtconfig.h b/bsp/cvitek/cv18xx_risc-v/rtconfig.h similarity index 85% rename from bsp/cvitek/cv1800b/rtconfig.h rename to bsp/cvitek/cv18xx_risc-v/rtconfig.h index 236544eee34..7fb6e27f8a5 100755 --- a/bsp/cvitek/cv1800b/rtconfig.h +++ b/bsp/cvitek/cv18xx_risc-v/rtconfig.h @@ -7,7 +7,6 @@ /* RT-Thread Kernel */ #define RT_NAME_MAX 8 -#define RT_USING_SMART #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -18,10 +17,10 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 1024 +#define IDLE_THREAD_STACK_SIZE 8192 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 2048 +#define RT_TIMER_THREAD_STACK_SIZE 8192 /* kservice optimization */ @@ -57,7 +56,6 @@ #define ARCH_CPU_64BIT #define RT_USING_CACHE #define ARCH_MM_MMU -#define KERNEL_VADDR_START 0x80000000 #define ARCH_RISCV #define ARCH_RISCV64 @@ -65,7 +63,7 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 6144 +#define RT_MAIN_THREAD_STACK_SIZE 8192 #define RT_MAIN_THREAD_PRIORITY 10 #define RT_USING_MSH #define RT_USING_FINSH @@ -90,29 +88,18 @@ #define DFS_FD_MAX 16 #define RT_USING_DFS_V2 #define RT_USING_DFS_DEVFS -#define RT_USING_PAGECACHE - -/* page cache config */ - -#define RT_PAGECACHE_COUNT 4096 -#define RT_PAGECACHE_ASPACE_COUNT 1024 -#define RT_PAGECACHE_PRELOAD 4 -#define RT_PAGECACHE_HASH_NR 1024 -#define RT_PAGECACHE_GC_WORK_LEVEL 90 -#define RT_PAGECACHE_GC_STOP_LEVEL 70 /* Device Drivers */ #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE -#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192 #define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_TTY #define RT_USING_NULL #define RT_USING_ZERO #define RT_USING_RANDOM @@ -139,6 +126,7 @@ #define RT_USING_POSIX_FS #define RT_USING_POSIX_DEVIO #define RT_USING_POSIX_STDIO +#define RT_USING_POSIX_POLL #define RT_USING_POSIX_TERMIOS #define RT_USING_POSIX_DELAY #define RT_USING_POSIX_CLOCK @@ -164,17 +152,6 @@ #define RT_USING_ADT_BITMAP #define RT_USING_ADT_HASHMAP #define RT_USING_ADT_REF -#define RT_USING_LWP -#define RT_LWP_MAX_NR 30 -#define LWP_TASK_STACK_SIZE 16384 -#define RT_CH_MSG_MAX_NR 1024 -#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024 -#define LWP_TID_MAX_NR 64 -#define RT_LWP_SHM_MAX_NR 64 -#define RT_USING_LDSO - -/* Memory management */ - /* RT-Thread Utestcases */ @@ -311,10 +288,11 @@ #define BSP_USING_UART #define RT_USING_UART0 #define UART_IRQ_BASE 44 -#define BSP_USING_CV1800B +#define BSP_USING_CV18XX #define C906_PLIC_PHY_ADDR 0x70000000 #define IRQ_MAX_NR 64 #define TIMER_CLK_FREQ 25000000 -#define __STACKSIZE__ 4096 +#define __STACKSIZE__ 8192 +#define BOARD_TYPE_MILKV_DUO256M #endif diff --git a/bsp/cvitek/cv1800b/rtconfig.py b/bsp/cvitek/cv18xx_risc-v/rtconfig.py similarity index 83% rename from bsp/cvitek/cv1800b/rtconfig.py rename to bsp/cvitek/cv18xx_risc-v/rtconfig.py index 0914d5c010f..91667d1bf0e 100755 --- a/bsp/cvitek/cv1800b/rtconfig.py +++ b/bsp/cvitek/cv18xx_risc-v/rtconfig.py @@ -16,7 +16,7 @@ if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = r'/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin' + EXEC_PATH = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin' else: print('Please make sure your toolchains is GNU GCC!') exit(0) @@ -25,11 +25,12 @@ EXEC_PATH = os.getenv('RTT_EXEC_PATH') BUILD = 'debug' +CHIP_TYPE = 'cv180x' if PLATFORM == 'gcc': # toolchains #PREFIX = 'riscv64-unknown-elf-' - PREFIX = os.getenv('RTT_CC_PREFIX') or 'riscv64-unknown-linux-musl-' + PREFIX = os.getenv('RTT_CC_PREFIX') or 'riscv64-unknown-elf-' CC = PREFIX + 'gcc' CXX = PREFIX + 'g++' AS = PREFIX + 'gcc' @@ -56,4 +57,5 @@ CXXFLAGS = CFLAGS DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread.asm\n' -POST_ACTION = OBJCPY + ' -O binary $TARGET Image\n' + SIZE + ' $TARGET \n' + './mksdimg.sh\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET Image \n' + SIZE + ' $TARGET \n' +POST_ACTION += 'cd .. && bash mksdimg.sh ' + os.getcwd() + ' Image \n' diff --git a/bsp/cvitek/drivers/.ignore_format.yml b/bsp/cvitek/drivers/.ignore_format.yml new file mode 100755 index 00000000000..821281b7e92 --- /dev/null +++ b/bsp/cvitek/drivers/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- libraries \ No newline at end of file diff --git a/bsp/cvitek/drivers/SConscript b/bsp/cvitek/drivers/SConscript index 83c882470cc..35979fed548 100755 --- a/bsp/cvitek/drivers/SConscript +++ b/bsp/cvitek/drivers/SConscript @@ -2,17 +2,23 @@ from building import * cwd = GetCurrentDir() src = Split(''' -drv_uart.c -drv_por.c + drv_uart.c + drv_por.c ''') CPPDEFINES = [] CPPPATH = [cwd] -if GetDepend('BSP_USING_CV1800B') or GetDepend('BSP_USING_C906_LITTLE'): - CPPPATH += [cwd + r'/cv1800b'] +CHIP_TYPE = 'cv180x' +if GetDepend('BOARD_TYPE_MILKV_DUO256M') or GetDepend('BOARD_TYPE_MILKV_DUO256M_SPINOR') or GetDepend('BOARD_TYPE_MILKV_DUO256M_SPINAND'): + CHIP_TYPE = 'cv181x' +elif GetDepend('BOARD_TYPE_MILKV_DUO') or GetDepend('BOARD_TYPE_MILKV_DUO_SPINOR') or GetDepend('BOARD_TYPE_MILKV_DUO_SPINAND'): + CHIP_TYPE = 'cv180x' -if GetDepend('BSP_USING_CV1800B'): +CPPPATH += [cwd + r'/libraries'] +CPPPATH += [cwd + r'/libraries/' + CHIP_TYPE] + +if GetDepend('BSP_USING_CV18XX'): src += ['drv_gpio.c'] if GetDepend('BSP_USING_I2C'): @@ -24,9 +30,13 @@ if GetDepend('BSP_USING_ADC'): if GetDepend('BSP_USING_WDT'): src += ['drv_wdt.c'] +if GetDepend(['BSP_USING_SPI']): + src += ['drv_spi.c'] + if GetDepend('BSP_USING_PWM'): src += ['drv_pwm.c'] - CPPPATH += [cwd + r'/cv1800b/pwm'] + CPPPATH += [cwd + r'/libraries/cv180x/pwm'] + CPPDEFINES += ['-DCONFIG_64BIT'] if GetDepend('BSP_USING_RTC'): diff --git a/bsp/cvitek/drivers/drv_gpio.c b/bsp/cvitek/drivers/drv_gpio.c index 4a1ae809c77..f6e6752e98d 100755 --- a/bsp/cvitek/drivers/drv_gpio.c +++ b/bsp/cvitek/drivers/drv_gpio.c @@ -126,7 +126,7 @@ static void dwapb_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t dwapb_write32(base_addr + GPIO_SWPORTA_DR, reg_val); } -static rt_int8_t dwapb_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t dwapb_pin_read(struct rt_device *device, rt_base_t pin) { rt_uint8_t bit, port; rt_ubase_t base_addr; diff --git a/bsp/cvitek/drivers/drv_spi.c b/bsp/cvitek/drivers/drv_spi.c new file mode 100644 index 00000000000..aa6b3dd0b9f --- /dev/null +++ b/bsp/cvitek/drivers/drv_spi.c @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-28 qiujingbao first version + */ + +#include "drv_spi.h" +#ifdef RT_USING_SPI + +#define DBG_TAG "drv.spi" +#define DBG_LVL DBG_INFO +#include + +static struct cv1800_spi cv1800_spi_obj[] = +{ +#ifdef BSP_USING_SPI + { + .spi_id = SPI2, + .device_name = "spi2", + .fifo_len = SPI_TXFTLR, + }, +#endif +}; + +static struct spi_regs *get_spi_base(uint8_t spi_id) +{ + struct spi_regs *spi_base = NULL; + + switch (spi_id) + { + case SPI0: + spi_base = (struct spi_regs *)SPI0_BASE; + break; + case SPI1: + spi_base = (struct spi_regs *)SPI1_BASE; + break; + case SPI2: + spi_base = (struct spi_regs *)SPI2_BASE; + break; + case SPI3: + spi_base = (struct spi_regs *)SPI3_BASE; + break; + } + + return spi_base; +} + +static rt_err_t drv_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) +{ + rt_err_t ret = RT_EOK; + struct cv1800_spi *spi_dev = RT_NULL; + uint32_t mode; + + spi_dev = (struct cv1800_spi *)(device->bus->parent.user_data); + + spi_dev->data_width = configuration->data_width; + + /* disable spi */ + spi_enable(spi_dev->reg, 0); + + /* clear irq */ + spi_clear_irq(spi_dev->reg, SPI_IRQ_MSAK); + + /* set clk */ + ret = spi_set_frequency(spi_dev->reg, configuration->max_hz); + if (ret) + return ret; + + /* set mode */ + ret = gen_spi_mode(configuration, &mode); + if (ret) + return ret; + + spi_set_mode(spi_dev->reg, mode); + + /* set cs */ + spi_enable_cs(spi_dev->reg, 0x1); + + spi_enable(spi_dev->reg, 0x1); + + mode = mmio_read_32((uintptr_t)&spi_dev->reg->spi_ctrl0); + LOG_D("mode: %x", mode); + mode = mmio_read_32((uintptr_t)&spi_dev->reg->spi_baudr); + LOG_D("spi_baudr: %x", mode); + + return ret; +} + +int hw_spi_recv(struct cv1800_spi *dev) { + uint32_t rever; + uint32_t tem; + int ret; + + rever = mmio_read_32((uintptr_t)&dev->reg->spi_rxflr); + ret = (int)rever; + + while (rever) + { + tem = mmio_read_32((uintptr_t)&dev->reg->spi_dr); + + if (dev->recv_buf < dev->recv_end) + { + if (dev->data_width == 8) + *(uint8_t *)(dev->recv_buf) = tem; + else + *(uint16_t *)(dev->recv_buf) = tem; + } + else + { + return 0; + } + + rever--; + dev->recv_buf += dev->data_width >> 3; + } + return ret; +} + +int hw_spi_send(struct cv1800_spi *dev) { + uint32_t txflr; + uint32_t max; + uint16_t value; + + txflr = mmio_read_32((uintptr_t)&dev->reg->spi_txflr); + max = dev->fifo_len - txflr; + + while (max) + { + if (dev->send_end - dev->send_buf) + { + if (dev->data_width == 8) + value = *(uint8_t *)(dev->send_buf); + else + value = *(uint16_t *)(dev->send_buf); + } + else + { + return 0; + } + + mmio_write_32((uintptr_t)&dev->reg->spi_dr, value); + dev->send_buf += dev->data_width >> 3; + max--; + } + + return 0; +} +static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) { + int ret = 0; + struct cv1800_spi *spi_dev; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(message != RT_NULL); + + spi_dev = (struct cv1800_spi *)(device->bus->parent.user_data); + + if (message->send_buf != RT_NULL) + { + spi_dev->send_buf = message->send_buf; + spi_dev->send_end = (void *)((uint8_t *)spi_dev->send_buf + message->length); + } + + if (message->recv_buf != RT_NULL) + { + spi_dev->recv_buf = message->recv_buf; + spi_dev->recv_end = (void *)((uint8_t *)spi_dev->recv_buf + message->length); + } + + /* if user use their cs */ + if (message->cs_take && device->cs_pin != PIN_NONE) + rt_pin_write(device->cs_pin, PIN_LOW); + + if (message->send_buf) + { + while (spi_dev->send_buf != spi_dev->send_end) + { + hw_spi_send(spi_dev); + } + + /* wait for complete */ + while (mmio_read_32((uintptr_t)&spi_dev->reg->spi_txflr)) {} + + ret = message->length; + } + + if (message->recv_buf) + { + while (spi_dev->recv_buf != spi_dev->recv_end) + { + hw_spi_recv(spi_dev); + } + + ret = message->length; + } + + if (message->cs_release && device->cs_pin != PIN_NONE) + rt_pin_write(device->cs_pin, PIN_HIGH); + + return ret; +} + +const static struct rt_spi_ops drv_spi_ops = +{ + drv_spi_configure, + spixfer, +}; + +int rt_hw_spi_init(void) +{ + rt_err_t ret = RT_EOK; + struct spi_regs *reg = NULL; + + for (rt_size_t i = 0; i < sizeof(cv1800_spi_obj) / sizeof(struct cv1800_spi); i++) { + /* set reg base addr */ + reg = get_spi_base(cv1800_spi_obj[i].spi_id); + if (!reg) + return -RT_ERROR; + + cv1800_spi_obj[i].reg = reg; + cv1800_spi_obj[i].spi_bus.parent.user_data = &cv1800_spi_obj[i]; + + /* register spix bus */ + ret = rt_spi_bus_register(&cv1800_spi_obj[i].spi_bus, cv1800_spi_obj[i].device_name, &drv_spi_ops); + } + + return ret; +} +INIT_BOARD_EXPORT(rt_hw_spi_init); + +#endif /* RT_USING_SPI */ diff --git a/bsp/cvitek/drivers/drv_spi.h b/bsp/cvitek/drivers/drv_spi.h new file mode 100644 index 00000000000..2e20b15b2eb --- /dev/null +++ b/bsp/cvitek/drivers/drv_spi.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-28 qiujingbao first version + */ +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include "rtdevice.h" +#include +#include + +#include "mmio.h" +#include "pinctrl.h" + +#define SPI0 0x0 +#define SPI1 0x1 +#define SPI2 0x2 +#define SPI3 0x3 + +#define SPI0_BASE 0x04180000 +#define SPI1_BASE 0x04190000 +#define SPI2_BASE 0x041A0000 +#define SPI3_BASE 0x041B0000 + +#define SPI_IRQ_MSAK 0x3e +#define SPI_FREQUENCY 187500000 + +/* Transmit FiFO Threshold Level */ +#define SPI_TXFTLR 0xf + +#define SPI_CTRL0_DATA_FREAM_SHIFT 0 +#define SPI_CTRL0_FREAM_FORMAT_SHIFT 4 +#define SPI_CTRL0_CPHA_SHIFT 6 +#define SPI_CTRL0_CPOL_SHIFT 7 +#define SPI_CTRL0_TRANS_MODE 8 +#define SPI_CTRL0_LOOP_SHIFT 11 +#define SPI_CTRL0_CTRL_FREAM_SHIFT 12 + +struct cv1800_spi { + uint8_t spi_id; + char *device_name; + + uint8_t fifo_len; + uint8_t data_width; + + const void *send_buf; + void *recv_buf; + + const void *send_end; + void *recv_end; + + struct rt_spi_bus spi_bus; + struct spi_regs *reg; +}; + +struct spi_regs { + uint32_t spi_ctrl0; // 0x00 + uint32_t spi_ctrl1; // 0x04 + uint32_t spi_ssienr; // 0x08 + uint32_t spi_mwcr; // 0x0c + uint32_t spi_ser; // 0x10 + uint32_t spi_baudr; // 0x14 + uint32_t spi_txftlr; // 0x18 + uint32_t spi_rxftlr; // 0x1c + uint32_t spi_txflr; // 0x20 + uint32_t spi_rxflr; // 0x24 + uint32_t spi_sr; // 0x28 + uint32_t spi_imr; // 0x2c + uint32_t spi_isr; // 0x30 + uint32_t spi_risr; // 0x34 + uint32_t spi_txoicr; // 0x38 + uint32_t spi_rxoicr; // 0x3c + uint32_t spi_rxuicr; // 0x40 + uint32_t spi_msticr; // 0x44 + uint32_t spi_icr; // 0x48 + uint32_t spi_dmacr; // 0x4c + uint32_t spi_dmatdlr; // 0x50 + uint32_t spi_dmardlr; // 0x54 + uint32_t spi_idr; // 0x58 + uint32_t spi_version; // 0x5c + uint32_t spi_dr; // 0x60 + uint32_t spi_rx_sample_dly; // 0xf0 + uint32_t spi_cs_override; // 0xf4 +}; + +uint32_t gen_spi_mode(struct rt_spi_configuration *cfg, uint32_t *mode) +{ + uint32_t value = 0; + + if (cfg->data_width != 8 && cfg->data_width != 16) + return -1; + + value |= (cfg->data_width - 1) >> SPI_CTRL0_DATA_FREAM_SHIFT; + value |= cfg->mode >> SPI_CTRL0_CPHA_SHIFT; + + *mode = value; + return 0; +} + +/* set spi mode */ +static inline void spi_set_mode(struct spi_regs *reg, uint32_t mode) +{ + mmio_write_32((uintptr_t)®->spi_ctrl0, mode); +} + +/* clear irq */ +static inline void spi_clear_irq(struct spi_regs *reg, uint32_t mode) +{ + mmio_write_32((uintptr_t)®->spi_imr, mode); +} + +static inline void spi_enable_cs(struct spi_regs *reg, uint32_t enable) +{ + if (enable) + enable = 0x1; + else + enable = 0x0; + + mmio_write_32((uintptr_t)®->spi_ser, enable); +} + +/* set spi frequency*/ +static inline rt_err_t spi_set_frequency(struct spi_regs *reg, uint32_t speed) +{ + uint16_t value; + + /* The value of the BAUDR register must be an even number between 2-65534 */ + value = SPI_FREQUENCY / speed; + if (value % 2 != 0) + value++; + + if (value < 4 || value > 65534) + value = 4; + + mmio_write_32((uintptr_t)®->spi_baudr, value); + + return RT_EOK; +} + +static inline void spi_enable(struct spi_regs *reg, uint32_t enable) +{ + if (enable) + enable = 0x1; + else + enable = 0x0; + + mmio_write_32((uintptr_t)®->spi_ssienr, enable); +} + +#endif /* __DRV_SPI_H__ */ diff --git a/bsp/cvitek/drivers/drv_uart.c b/bsp/cvitek/drivers/drv_uart.c index b629cd5a0d0..845e6708f68 100644 --- a/bsp/cvitek/drivers/drv_uart.c +++ b/bsp/cvitek/drivers/drv_uart.c @@ -252,30 +252,45 @@ int rt_hw_uart_init(void) PINMUX_CONFIG(UART0_RX, UART0_RX); PINMUX_CONFIG(UART0_TX, UART0_TX); BSP_INSTALL_UART_DEVICE(0); +#if defined(ARCH_ARM) && defined(RT_USING_SMART) + uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); +#endif /* defined(ARCH_ARM) && defined(RT_USING_SMART) */ #endif #ifdef RT_USING_UART1 PINMUX_CONFIG(IIC0_SDA, UART1_RX); PINMUX_CONFIG(IIC0_SCL, UART1_TX); BSP_INSTALL_UART_DEVICE(1); +#if defined(ARCH_ARM) && defined(RT_USING_SMART) + uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); +#endif /* defined(ARCH_ARM) && defined(RT_USING_SMART) */ #endif #ifdef RT_USING_UART2 PINMUX_CONFIG(SD1_D1, UART2_RX); PINMUX_CONFIG(SD1_D2, UART2_TX); BSP_INSTALL_UART_DEVICE(2); +#if defined(ARCH_ARM) && defined(RT_USING_SMART) + uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); +#endif /* defined(ARCH_ARM) && defined(RT_USING_SMART) */ #endif #ifdef RT_USING_UART3 PINMUX_CONFIG(SD1_D1, UART3_RX); PINMUX_CONFIG(SD1_D2, UART3_TX); BSP_INSTALL_UART_DEVICE(3); +#if defined(ARCH_ARM) && defined(RT_USING_SMART) + uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); +#endif /* defined(ARCH_ARM) && defined(RT_USING_SMART) */ #endif #ifdef RT_USING_UART4 PINMUX_CONFIG(SD1_GP0, UART4_RX); PINMUX_CONFIG(SD1_GP1, UART4_TX); BSP_INSTALL_UART_DEVICE(4); +#if defined(ARCH_ARM) && defined(RT_USING_SMART) + uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); +#endif /* defined(ARCH_ARM) && defined(RT_USING_SMART) */ #endif return 0; diff --git a/bsp/cvitek/drivers/cv1800b/cv180x_pinlist_swconfig.h b/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinlist_swconfig.h similarity index 100% rename from bsp/cvitek/drivers/cv1800b/cv180x_pinlist_swconfig.h rename to bsp/cvitek/drivers/libraries/cv180x/cv180x_pinlist_swconfig.h diff --git a/bsp/cvitek/drivers/cv1800b/cv180x_pinmux.h b/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinmux.h similarity index 100% rename from bsp/cvitek/drivers/cv1800b/cv180x_pinmux.h rename to bsp/cvitek/drivers/libraries/cv180x/cv180x_pinmux.h diff --git a/bsp/cvitek/drivers/cv1800b/cv180x_reg_fmux_gpio.h b/bsp/cvitek/drivers/libraries/cv180x/cv180x_reg_fmux_gpio.h similarity index 100% rename from bsp/cvitek/drivers/cv1800b/cv180x_reg_fmux_gpio.h rename to bsp/cvitek/drivers/libraries/cv180x/cv180x_reg_fmux_gpio.h diff --git a/bsp/cvitek/drivers/cv1800b/pinctrl.h b/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h similarity index 100% rename from bsp/cvitek/drivers/cv1800b/pinctrl.h rename to bsp/cvitek/drivers/libraries/cv180x/pinctrl.h diff --git a/bsp/cvitek/drivers/cv1800b/pwm/cvi_pwm.h b/bsp/cvitek/drivers/libraries/cv180x/pwm/cvi_pwm.h old mode 100644 new mode 100755 similarity index 100% rename from bsp/cvitek/drivers/cv1800b/pwm/cvi_pwm.h rename to bsp/cvitek/drivers/libraries/cv180x/pwm/cvi_pwm.h diff --git a/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinlist_swconfig.h b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinlist_swconfig.h new file mode 100755 index 00000000000..64d4ec9cdb2 --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinlist_swconfig.h @@ -0,0 +1,653 @@ + +#define CAM_MCLK0__CAM_MCLK0 0 +#define CAM_MCLK0__AUX1 2 +#define CAM_MCLK0__XGPIOA_0 3 +#define CAM_PD0__IIS1_MCLK 1 +#define CAM_PD0__XGPIOA_1 3 +#define CAM_PD0__CAM_HS0 4 +#define CAM_RST0__XGPIOA_2 3 +#define CAM_RST0__CAM_VS0 4 +#define CAM_RST0__IIC4_SCL 6 +#define CAM_MCLK1__CAM_MCLK1 0 +#define CAM_MCLK1__AUX2 2 +#define CAM_MCLK1__XGPIOA_3 3 +#define CAM_MCLK1__CAM_HS0 4 +#define CAM_PD1__IIS1_MCLK 1 +#define CAM_PD1__XGPIOA_4 3 +#define CAM_PD1__CAM_VS0 4 +#define CAM_PD1__IIC4_SDA 6 +#define IIC3_SCL__IIC3_SCL 0 +#define IIC3_SCL__XGPIOA_5 3 +#define IIC3_SDA__IIC3_SDA 0 +#define IIC3_SDA__XGPIOA_6 3 +#define SD0_CLK__SDIO0_CLK 0 +#define SD0_CLK__IIC1_SDA 1 +#define SD0_CLK__SPI0_SCK 2 +#define SD0_CLK__XGPIOA_7 3 +#define SD0_CLK__PWM_15 5 +#define SD0_CLK__EPHY_LNK_LED 6 +#define SD0_CLK__DBG_0 7 +#define SD0_CMD__SDIO0_CMD 0 +#define SD0_CMD__IIC1_SCL 1 +#define SD0_CMD__SPI0_SDO 2 +#define SD0_CMD__XGPIOA_8 3 +#define SD0_CMD__PWM_14 5 +#define SD0_CMD__EPHY_SPD_LED 6 +#define SD0_CMD__DBG_1 7 +#define SD0_D0__SDIO0_D_0 0 +#define SD0_D0__CAM_MCLK1 1 +#define SD0_D0__SPI0_SDI 2 +#define SD0_D0__XGPIOA_9 3 +#define SD0_D0__UART3_TX 4 +#define SD0_D0__PWM_13 5 +#define SD0_D0__WG0_D0 6 +#define SD0_D0__DBG_2 7 +#define SD0_D1__SDIO0_D_1 0 +#define SD0_D1__IIC1_SDA 1 +#define SD0_D1__AUX0 2 +#define SD0_D1__XGPIOA_10 3 +#define SD0_D1__UART1_TX 4 +#define SD0_D1__PWM_12 5 +#define SD0_D1__WG0_D1 6 +#define SD0_D1__DBG_3 7 +#define SD0_D2__SDIO0_D_2 0 +#define SD0_D2__IIC1_SCL 1 +#define SD0_D2__AUX1 2 +#define SD0_D2__XGPIOA_11 3 +#define SD0_D2__UART1_RX 4 +#define SD0_D2__PWM_11 5 +#define SD0_D2__WG1_D0 6 +#define SD0_D2__DBG_4 7 +#define SD0_D3__SDIO0_D_3 0 +#define SD0_D3__CAM_MCLK0 1 +#define SD0_D3__SPI0_CS_X 2 +#define SD0_D3__XGPIOA_12 3 +#define SD0_D3__UART3_RX 4 +#define SD0_D3__PWM_10 5 +#define SD0_D3__WG1_D1 6 +#define SD0_D3__DBG_5 7 +#define SD0_CD__SDIO0_CD 0 +#define SD0_CD__XGPIOA_13 3 +#define SD0_PWR_EN__SDIO0_PWR_EN 0 +#define SD0_PWR_EN__XGPIOA_14 3 +#define SPK_EN__XGPIOA_15 3 +#define UART0_TX__UART0_TX 0 +#define UART0_TX__CAM_MCLK1 1 +#define UART0_TX__PWM_4 2 +#define UART0_TX__XGPIOA_16 3 +#define UART0_TX__UART1_TX 4 +#define UART0_TX__AUX1 5 +#define UART0_TX__DBG_6 7 +#define UART0_RX__UART0_RX 0 +#define UART0_RX__CAM_MCLK0 1 +#define UART0_RX__PWM_5 2 +#define UART0_RX__XGPIOA_17 3 +#define UART0_RX__UART1_RX 4 +#define UART0_RX__AUX0 5 +#define UART0_RX__DBG_7 7 +#define EMMC_RSTN__EMMC_RSTN 0 +#define EMMC_RSTN__XGPIOA_21 3 +#define EMMC_RSTN__AUX2 4 +#define EMMC_DAT2__EMMC_DAT_2 0 +#define EMMC_DAT2__SPINOR_HOLD_X 1 +#define EMMC_DAT2__SPINAND_HOLD 2 +#define EMMC_DAT2__XGPIOA_26 3 +#define EMMC_CLK__EMMC_CLK 0 +#define EMMC_CLK__SPINOR_SCK 1 +#define EMMC_CLK__SPINAND_CLK 2 +#define EMMC_CLK__XGPIOA_22 3 +#define EMMC_DAT0__EMMC_DAT_0 0 +#define EMMC_DAT0__SPINOR_MOSI 1 +#define EMMC_DAT0__SPINAND_MOSI 2 +#define EMMC_DAT0__XGPIOA_25 3 +#define EMMC_DAT3__EMMC_DAT_3 0 +#define EMMC_DAT3__SPINOR_WP_X 1 +#define EMMC_DAT3__SPINAND_WP 2 +#define EMMC_DAT3__XGPIOA_27 3 +#define EMMC_CMD__EMMC_CMD 0 +#define EMMC_CMD__SPINOR_MISO 1 +#define EMMC_CMD__SPINAND_MISO 2 +#define EMMC_CMD__XGPIOA_23 3 +#define EMMC_DAT1__EMMC_DAT_1 0 +#define EMMC_DAT1__SPINOR_CS_X 1 +#define EMMC_DAT1__SPINAND_CS 2 +#define EMMC_DAT1__XGPIOA_24 3 +#define JTAG_CPU_TMS__JTAG_CPU_TMS 0 +#define JTAG_CPU_TMS__CAM_MCLK0 1 +#define JTAG_CPU_TMS__PWM_7 2 +#define JTAG_CPU_TMS__XGPIOA_19 3 +#define JTAG_CPU_TMS__UART1_RTS 4 +#define JTAG_CPU_TMS__AUX0 5 +#define JTAG_CPU_TMS__UART1_TX 6 +#define JTAG_CPU_TMS__VO_D_28 7 +#define JTAG_CPU_TCK__JTAG_CPU_TCK 0 +#define JTAG_CPU_TCK__CAM_MCLK1 1 +#define JTAG_CPU_TCK__PWM_6 2 +#define JTAG_CPU_TCK__XGPIOA_18 3 +#define JTAG_CPU_TCK__UART1_CTS 4 +#define JTAG_CPU_TCK__AUX1 5 +#define JTAG_CPU_TCK__UART1_RX 6 +#define JTAG_CPU_TCK__VO_D_29 7 +#define JTAG_CPU_TRST__JTAG_CPU_TRST 0 +#define JTAG_CPU_TRST__XGPIOA_20 3 +#define JTAG_CPU_TRST__VO_D_30 6 +#define IIC0_SCL__IIC0_SCL 0 +#define IIC0_SCL__UART1_TX 1 +#define IIC0_SCL__UART2_TX 2 +#define IIC0_SCL__XGPIOA_28 3 +#define IIC0_SCL__WG0_D0 5 +#define IIC0_SCL__DBG_10 7 +#define IIC0_SDA__IIC0_SDA 0 +#define IIC0_SDA__UART1_RX 1 +#define IIC0_SDA__UART2_RX 2 +#define IIC0_SDA__XGPIOA_29 3 +#define IIC0_SDA__WG0_D1 5 +#define IIC0_SDA__WG1_D0 6 +#define IIC0_SDA__DBG_11 7 +#define AUX0__AUX0 0 +#define AUX0__XGPIOA_30 3 +#define AUX0__IIS1_MCLK 4 +#define AUX0__VO_D_31 5 +#define AUX0__WG1_D1 6 +#define AUX0__DBG_12 7 +#define PWR_VBAT_DET__PWR_VBAT_DET 0 +#define PWR_RSTN__PWR_RSTN 0 +#define PWR_SEQ1__PWR_SEQ1 0 +#define PWR_SEQ1__PWR_GPIO_3 3 +#define PWR_SEQ2__PWR_SEQ2 0 +#define PWR_SEQ2__PWR_GPIO_4 3 +#define PWR_SEQ3__PWR_SEQ3 0 +#define PWR_SEQ3__PWR_GPIO_5 3 +#define PTEST__PWR_PTEST 0 +#define PWR_WAKEUP0__PWR_WAKEUP0 0 +#define PWR_WAKEUP0__PWR_IR0 1 +#define PWR_WAKEUP0__PWR_UART0_TX 2 +#define PWR_WAKEUP0__PWR_GPIO_6 3 +#define PWR_WAKEUP0__UART1_TX 4 +#define PWR_WAKEUP0__IIC4_SCL 5 +#define PWR_WAKEUP0__EPHY_LNK_LED 6 +#define PWR_WAKEUP0__WG2_D0 7 +#define PWR_WAKEUP1__PWR_WAKEUP1 0 +#define PWR_WAKEUP1__PWR_IR1 1 +#define PWR_WAKEUP1__PWR_GPIO_7 3 +#define PWR_WAKEUP1__UART1_TX 4 +#define PWR_WAKEUP1__IIC4_SCL 5 +#define PWR_WAKEUP1__EPHY_LNK_LED 6 +#define PWR_WAKEUP1__WG0_D0 7 +#define PWR_BUTTON1__PWR_BUTTON1 0 +#define PWR_BUTTON1__PWR_GPIO_8 3 +#define PWR_BUTTON1__UART1_RX 4 +#define PWR_BUTTON1__IIC4_SDA 5 +#define PWR_BUTTON1__EPHY_SPD_LED 6 +#define PWR_BUTTON1__WG2_D1 7 +#define PWR_ON__PWR_ON 0 +#define PWR_ON__PWR_GPIO_9 3 +#define PWR_ON__UART1_RX 4 +#define PWR_ON__IIC4_SDA 5 +#define PWR_ON__EPHY_SPD_LED 6 +#define PWR_ON__WG0_D1 7 +#define XTAL_XIN__PWR_XTAL_CLKIN 0 +#define PWR_GPIO0__PWR_GPIO_0 0 +#define PWR_GPIO0__UART2_TX 1 +#define PWR_GPIO0__PWR_UART0_RX 2 +#define PWR_GPIO0__PWM_8 4 +#define PWR_GPIO1__PWR_GPIO_1 0 +#define PWR_GPIO1__UART2_RX 1 +#define PWR_GPIO1__EPHY_LNK_LED 3 +#define PWR_GPIO1__PWM_9 4 +#define PWR_GPIO1__PWR_IIC_SCL 5 +#define PWR_GPIO1__IIC2_SCL 6 +#define PWR_GPIO1__PWR_MCU_JTAG_TMS 7 +#define PWR_GPIO2__PWR_GPIO_2 0 +#define PWR_GPIO2__PWR_SECTICK 2 +#define PWR_GPIO2__EPHY_SPD_LED 3 +#define PWR_GPIO2__PWM_10 4 +#define PWR_GPIO2__PWR_IIC_SDA 5 +#define PWR_GPIO2__IIC2_SDA 6 +#define PWR_GPIO2__PWR_MCU_JTAG_TCK 7 +#define CLK32K__CLK32K 0 +#define CLK32K__AUX0 1 +#define CLK32K__PWR_MCU_JTAG_TDI 2 +#define CLK32K__PWR_GPIO_10 3 +#define CLK32K__PWM_2 4 +#define CLK32K__KEY_COL0 5 +#define CLK32K__CAM_MCLK0 6 +#define CLK32K__DBG_0 7 +#define CLK25M__CLK25M 0 +#define CLK25M__AUX1 1 +#define CLK25M__PWR_MCU_JTAG_TDO 2 +#define CLK25M__PWR_GPIO_11 3 +#define CLK25M__PWM_3 4 +#define CLK25M__KEY_COL1 5 +#define CLK25M__CAM_MCLK1 6 +#define CLK25M__DBG_1 7 +#define IIC2_SCL__IIC2_SCL 0 +#define IIC2_SCL__PWM_14 1 +#define IIC2_SCL__PWR_GPIO_12 3 +#define IIC2_SCL__UART2_RX 4 +#define IIC2_SCL__KEY_COL2 7 +#define IIC2_SDA__IIC2_SDA 0 +#define IIC2_SDA__PWM_15 1 +#define IIC2_SDA__PWR_GPIO_13 3 +#define IIC2_SDA__UART2_TX 4 +#define IIC2_SDA__IIS1_MCLK 5 +#define IIC2_SDA__IIS2_MCLK 6 +#define IIC2_SDA__KEY_COL3 7 +#define UART2_TX__UART2_TX 0 +#define UART2_TX__PWM_11 1 +#define UART2_TX__PWR_UART1_TX 2 +#define UART2_TX__PWR_GPIO_14 3 +#define UART2_TX__KEY_ROW3 4 +#define UART2_TX__UART4_TX 5 +#define UART2_TX__IIS2_BCLK 6 +#define UART2_TX__WG2_D0 7 +#define UART2_RTS__UART2_RTS 0 +#define UART2_RTS__PWM_8 1 +#define UART2_RTS__PWR_GPIO_15 3 +#define UART2_RTS__KEY_ROW0 4 +#define UART2_RTS__UART4_RTS 5 +#define UART2_RTS__IIS2_DO 6 +#define UART2_RTS__WG1_D0 7 +#define UART2_RX__UART2_RX 0 +#define UART2_RX__PWM_10 1 +#define UART2_RX__PWR_UART1_RX 2 +#define UART2_RX__PWR_GPIO_16 3 +#define UART2_RX__KEY_COL3 4 +#define UART2_RX__UART4_RX 5 +#define UART2_RX__IIS2_DI 6 +#define UART2_RX__WG2_D1 7 +#define UART2_CTS__UART2_CTS 0 +#define UART2_CTS__PWM_9 1 +#define UART2_CTS__PWR_GPIO_17 3 +#define UART2_CTS__KEY_ROW1 4 +#define UART2_CTS__UART4_CTS 5 +#define UART2_CTS__IIS2_LRCK 6 +#define UART2_CTS__WG1_D1 7 +#define SD1_D3__PWR_SD1_D3_VO32 0 +#define SD1_D3__SPI2_CS_X 1 +#define SD1_D3__IIC1_SCL 2 +#define SD1_D3__PWR_GPIO_18 3 +#define SD1_D3__CAM_MCLK0 4 +#define SD1_D3__UART3_CTS 5 +#define SD1_D3__PWR_SPINOR1_CS_X 6 +#define SD1_D3__PWM_4 7 +#define SD1_D2__PWR_SD1_D2_VO33 0 +#define SD1_D2__IIC1_SCL 1 +#define SD1_D2__UART2_TX 2 +#define SD1_D2__PWR_GPIO_19 3 +#define SD1_D2__CAM_MCLK0 4 +#define SD1_D2__UART3_TX 5 +#define SD1_D2__PWR_SPINOR1_HOLD_X 6 +#define SD1_D2__PWM_5 7 +#define SD1_D1__PWR_SD1_D1_VO34 0 +#define SD1_D1__IIC1_SDA 1 +#define SD1_D1__UART2_RX 2 +#define SD1_D1__PWR_GPIO_20 3 +#define SD1_D1__CAM_MCLK1 4 +#define SD1_D1__UART3_RX 5 +#define SD1_D1__PWR_SPINOR1_WP_X 6 +#define SD1_D1__PWM_6 7 +#define SD1_D0__PWR_SD1_D0_VO35 0 +#define SD1_D0__SPI2_SDI 1 +#define SD1_D0__IIC1_SDA 2 +#define SD1_D0__PWR_GPIO_21 3 +#define SD1_D0__CAM_MCLK1 4 +#define SD1_D0__UART3_RTS 5 +#define SD1_D0__PWR_SPINOR1_MISO 6 +#define SD1_D0__PWM_7 7 +#define SD1_CMD__PWR_SD1_CMD_VO36 0 +#define SD1_CMD__SPI2_SDO 1 +#define SD1_CMD__IIC3_SCL 2 +#define SD1_CMD__PWR_GPIO_22 3 +#define SD1_CMD__CAM_VS0 4 +#define SD1_CMD__EPHY_LNK_LED 5 +#define SD1_CMD__PWR_SPINOR1_MOSI 6 +#define SD1_CMD__PWM_8 7 +#define SD1_CLK__PWR_SD1_CLK_VO37 0 +#define SD1_CLK__SPI2_SCK 1 +#define SD1_CLK__IIC3_SDA 2 +#define SD1_CLK__PWR_GPIO_23 3 +#define SD1_CLK__CAM_HS0 4 +#define SD1_CLK__EPHY_SPD_LED 5 +#define SD1_CLK__PWR_SPINOR1_SCK 6 +#define SD1_CLK__PWM_9 7 +#define RSTN__RSTN 0 +#define PWM0_BUCK__PWM_0 0 +#define PWM0_BUCK__XGPIOB_0 3 +#define ADC3__CAM_MCLK0 1 +#define ADC3__IIC4_SCL 2 +#define ADC3__XGPIOB_1 3 +#define ADC3__PWM_12 4 +#define ADC3__EPHY_LNK_LED 5 +#define ADC3__WG2_D0 6 +#define ADC3__UART3_TX 7 +#define ADC2__CAM_MCLK1 1 +#define ADC2__IIC4_SDA 2 +#define ADC2__XGPIOB_2 3 +#define ADC2__PWM_13 4 +#define ADC2__EPHY_SPD_LED 5 +#define ADC2__WG2_D1 6 +#define ADC2__UART3_RX 7 +#define ADC1__XGPIOB_3 3 +#define ADC1__KEY_COL2 4 +#define USB_ID__USB_ID 0 +#define USB_ID__XGPIOB_4 3 +#define USB_VBUS_EN__USB_VBUS_EN 0 +#define USB_VBUS_EN__XGPIOB_5 3 +#define PKG_TYPE0__PKG_TYPE0 0 +#define USB_VBUS_DET__USB_VBUS_DET 0 +#define USB_VBUS_DET__XGPIOB_6 3 +#define USB_VBUS_DET__CAM_MCLK0 4 +#define USB_VBUS_DET__CAM_MCLK1 5 +#define PKG_TYPE1__PKG_TYPE1 0 +#define PKG_TYPE2__PKG_TYPE2 0 +#define MUX_SPI1_MISO__UART3_RTS 1 +#define MUX_SPI1_MISO__IIC1_SDA 2 +#define MUX_SPI1_MISO__XGPIOB_8 3 +#define MUX_SPI1_MISO__PWM_9 4 +#define MUX_SPI1_MISO__KEY_COL1 5 +#define MUX_SPI1_MISO__SPI1_SDI 6 +#define MUX_SPI1_MISO__DBG_14 7 +#define MUX_SPI1_MOSI__UART3_RX 1 +#define MUX_SPI1_MOSI__IIC1_SCL 2 +#define MUX_SPI1_MOSI__XGPIOB_7 3 +#define MUX_SPI1_MOSI__PWM_8 4 +#define MUX_SPI1_MOSI__KEY_COL0 5 +#define MUX_SPI1_MOSI__SPI1_SDO 6 +#define MUX_SPI1_MOSI__DBG_13 7 +#define MUX_SPI1_CS__UART3_CTS 1 +#define MUX_SPI1_CS__CAM_MCLK0 2 +#define MUX_SPI1_CS__XGPIOB_10 3 +#define MUX_SPI1_CS__PWM_11 4 +#define MUX_SPI1_CS__KEY_ROW3 5 +#define MUX_SPI1_CS__SPI1_CS_X 6 +#define MUX_SPI1_CS__DBG_16 7 +#define MUX_SPI1_SCK__UART3_TX 1 +#define MUX_SPI1_SCK__CAM_MCLK1 2 +#define MUX_SPI1_SCK__XGPIOB_9 3 +#define MUX_SPI1_SCK__PWM_10 4 +#define MUX_SPI1_SCK__KEY_ROW2 5 +#define MUX_SPI1_SCK__SPI1_SCK 6 +#define MUX_SPI1_SCK__DBG_15 7 +#define PAD_ETH_TXM__UART3_RTS 1 +#define PAD_ETH_TXM__IIC1_SDA 2 +#define PAD_ETH_TXM__XGPIOB_24 3 +#define PAD_ETH_TXM__PWM_12 4 +#define PAD_ETH_TXM__CAM_MCLK1 5 +#define PAD_ETH_TXM__SPI1_SDI 6 +#define PAD_ETH_TXM__IIS2_BCLK 7 +#define PAD_ETH_TXP__UART3_RX 1 +#define PAD_ETH_TXP__IIC1_SCL 2 +#define PAD_ETH_TXP__XGPIOB_25 3 +#define PAD_ETH_TXP__PWM_13 4 +#define PAD_ETH_TXP__CAM_MCLK0 5 +#define PAD_ETH_TXP__SPI1_SDO 6 +#define PAD_ETH_TXP__IIS2_LRCK 7 +#define PAD_ETH_RXM__UART3_CTS 1 +#define PAD_ETH_RXM__CAM_MCLK0 2 +#define PAD_ETH_RXM__XGPIOB_26 3 +#define PAD_ETH_RXM__PWM_14 4 +#define PAD_ETH_RXM__CAM_VS0 5 +#define PAD_ETH_RXM__SPI1_CS_X 6 +#define PAD_ETH_RXM__IIS2_DI 7 +#define PAD_ETH_RXP__UART3_TX 1 +#define PAD_ETH_RXP__CAM_MCLK1 2 +#define PAD_ETH_RXP__XGPIOB_27 3 +#define PAD_ETH_RXP__PWM_15 4 +#define PAD_ETH_RXP__CAM_HS0 5 +#define PAD_ETH_RXP__SPI1_SCK 6 +#define PAD_ETH_RXP__IIS2_DO 7 +#define VIVO_D10__PWM_1 0 +#define VIVO_D10__VI1_D_10 1 +#define VIVO_D10__VO_D_23 2 +#define VIVO_D10__XGPIOB_11 3 +#define VIVO_D10__RMII0_IRQ 4 +#define VIVO_D10__CAM_MCLK0 5 +#define VIVO_D10__IIC1_SDA 6 +#define VIVO_D10__UART2_TX 7 +#define VIVO_D9__PWM_2 0 +#define VIVO_D9__VI1_D_9 1 +#define VIVO_D9__VO_D_22 2 +#define VIVO_D9__XGPIOB_12 3 +#define VIVO_D9__CAM_MCLK1 5 +#define VIVO_D9__IIC1_SCL 6 +#define VIVO_D9__UART2_RX 7 +#define VIVO_D8__PWM_3 0 +#define VIVO_D8__VI1_D_8 1 +#define VIVO_D8__VO_D_21 2 +#define VIVO_D8__XGPIOB_13 3 +#define VIVO_D8__RMII0_MDIO 4 +#define VIVO_D8__SPI3_SDO 5 +#define VIVO_D8__IIC2_SCL 6 +#define VIVO_D8__CAM_VS0 7 +#define VIVO_D7__VI2_D_7 0 +#define VIVO_D7__VI1_D_7 1 +#define VIVO_D7__VO_D_20 2 +#define VIVO_D7__XGPIOB_14 3 +#define VIVO_D7__RMII0_RXD1 4 +#define VIVO_D7__SPI3_SDI 5 +#define VIVO_D7__IIC2_SDA 6 +#define VIVO_D7__CAM_HS0 7 +#define VIVO_D6__VI2_D_6 0 +#define VIVO_D6__VI1_D_6 1 +#define VIVO_D6__VO_D_19 2 +#define VIVO_D6__XGPIOB_15 3 +#define VIVO_D6__RMII0_REFCLKI 4 +#define VIVO_D6__SPI3_SCK 5 +#define VIVO_D6__UART2_TX 6 +#define VIVO_D6__CAM_VS0 7 +#define VIVO_D5__VI2_D_5 0 +#define VIVO_D5__VI1_D_5 1 +#define VIVO_D5__VO_D_18 2 +#define VIVO_D5__XGPIOB_16 3 +#define VIVO_D5__RMII0_RXD0 4 +#define VIVO_D5__SPI3_CS_X 5 +#define VIVO_D5__UART2_RX 6 +#define VIVO_D5__CAM_HS0 7 +#define VIVO_D4__VI2_D_4 0 +#define VIVO_D4__VI1_D_4 1 +#define VIVO_D4__VO_D_17 2 +#define VIVO_D4__XGPIOB_17 3 +#define VIVO_D4__RMII0_MDC 4 +#define VIVO_D4__IIC1_SDA 5 +#define VIVO_D4__UART2_CTS 6 +#define VIVO_D4__CAM_VS0 7 +#define VIVO_D3__VI2_D_3 0 +#define VIVO_D3__VI1_D_3 1 +#define VIVO_D3__VO_D_16 2 +#define VIVO_D3__XGPIOB_18 3 +#define VIVO_D3__RMII0_TXD0 4 +#define VIVO_D3__IIC1_SCL 5 +#define VIVO_D3__UART2_RTS 6 +#define VIVO_D3__CAM_HS0 7 +#define VIVO_D2__VI2_D_2 0 +#define VIVO_D2__VI1_D_2 1 +#define VIVO_D2__VO_D_15 2 +#define VIVO_D2__XGPIOB_19 3 +#define VIVO_D2__RMII0_TXD1 4 +#define VIVO_D2__CAM_MCLK1 5 +#define VIVO_D2__PWM_2 6 +#define VIVO_D2__UART2_TX 7 +#define VIVO_D1__VI2_D_1 0 +#define VIVO_D1__VI1_D_1 1 +#define VIVO_D1__VO_D_14 2 +#define VIVO_D1__XGPIOB_20 3 +#define VIVO_D1__RMII0_RXDV 4 +#define VIVO_D1__IIC3_SDA 5 +#define VIVO_D1__PWM_3 6 +#define VIVO_D1__IIC4_SCL 7 +#define VIVO_D0__VI2_D_0 0 +#define VIVO_D0__VI1_D_0 1 +#define VIVO_D0__VO_D_13 2 +#define VIVO_D0__XGPIOB_21 3 +#define VIVO_D0__RMII0_TXCLK 4 +#define VIVO_D0__IIC3_SCL 5 +#define VIVO_D0__WG1_D0 6 +#define VIVO_D0__IIC4_SDA 7 +#define VIVO_CLK__VI2_CLK 0 +#define VIVO_CLK__VI1_CLK 1 +#define VIVO_CLK__VO_CLK1 2 +#define VIVO_CLK__XGPIOB_22 3 +#define VIVO_CLK__RMII0_TXEN 4 +#define VIVO_CLK__CAM_MCLK0 5 +#define VIVO_CLK__WG1_D1 6 +#define VIVO_CLK__UART2_RX 7 +#define PAD_MIPIRX5N__VI1_D_11 1 +#define PAD_MIPIRX5N__VO_D_12 2 +#define PAD_MIPIRX5N__XGPIOC_0 3 +#define PAD_MIPIRX5N__CAM_MCLK0 5 +#define PAD_MIPIRX5N__WG0_D0 6 +#define PAD_MIPIRX5N__DBG_0 7 +#define PAD_MIPIRX5P__VI1_D_12 1 +#define PAD_MIPIRX5P__VO_D_11 2 +#define PAD_MIPIRX5P__XGPIOC_1 3 +#define PAD_MIPIRX5P__IIS1_MCLK 4 +#define PAD_MIPIRX5P__CAM_MCLK1 5 +#define PAD_MIPIRX5P__WG0_D1 6 +#define PAD_MIPIRX5P__DBG_1 7 +#define PAD_MIPIRX4N__VI0_CLK 1 +#define PAD_MIPIRX4N__VI1_D_13 2 +#define PAD_MIPIRX4N__XGPIOC_2 3 +#define PAD_MIPIRX4N__IIC1_SDA 4 +#define PAD_MIPIRX4N__CAM_MCLK0 5 +#define PAD_MIPIRX4N__KEY_ROW0 6 +#define PAD_MIPIRX4N__MUX_SPI1_SCK 7 +#define PAD_MIPIRX4P__VI0_D_0 1 +#define PAD_MIPIRX4P__VI1_D_14 2 +#define PAD_MIPIRX4P__XGPIOC_3 3 +#define PAD_MIPIRX4P__IIC1_SCL 4 +#define PAD_MIPIRX4P__CAM_MCLK1 5 +#define PAD_MIPIRX4P__KEY_ROW1 6 +#define PAD_MIPIRX4P__MUX_SPI1_CS 7 +#define PAD_MIPIRX3N__VI0_D_1 1 +#define PAD_MIPIRX3N__VI1_D_15 2 +#define PAD_MIPIRX3N__XGPIOC_4 3 +#define PAD_MIPIRX3N__CAM_MCLK0 4 +#define PAD_MIPIRX3N__MUX_SPI1_MISO 7 +#define PAD_MIPIRX3P__VI0_D_2 1 +#define PAD_MIPIRX3P__VI1_D_16 2 +#define PAD_MIPIRX3P__XGPIOC_5 3 +#define PAD_MIPIRX3P__MUX_SPI1_MOSI 7 +#define PAD_MIPIRX2N__VI0_D_3 1 +#define PAD_MIPIRX2N__VO_D_10 2 +#define PAD_MIPIRX2N__XGPIOC_6 3 +#define PAD_MIPIRX2N__VI1_D_17 4 +#define PAD_MIPIRX2N__IIC4_SCL 5 +#define PAD_MIPIRX2N__DBG_6 7 +#define PAD_MIPIRX2P__VI0_D_4 1 +#define PAD_MIPIRX2P__VO_D_9 2 +#define PAD_MIPIRX2P__XGPIOC_7 3 +#define PAD_MIPIRX2P__VI1_D_18 4 +#define PAD_MIPIRX2P__IIC4_SDA 5 +#define PAD_MIPIRX2P__DBG_7 7 +#define PAD_MIPIRX1N__VI0_D_5 1 +#define PAD_MIPIRX1N__VO_D_8 2 +#define PAD_MIPIRX1N__XGPIOC_8 3 +#define PAD_MIPIRX1N__KEY_ROW3 6 +#define PAD_MIPIRX1N__DBG_8 7 +#define PAD_MIPIRX1P__VI0_D_6 1 +#define PAD_MIPIRX1P__VO_D_7 2 +#define PAD_MIPIRX1P__XGPIOC_9 3 +#define PAD_MIPIRX1P__IIC1_SDA 4 +#define PAD_MIPIRX1P__KEY_ROW2 6 +#define PAD_MIPIRX1P__DBG_9 7 +#define PAD_MIPIRX0N__VI0_D_7 1 +#define PAD_MIPIRX0N__VO_D_6 2 +#define PAD_MIPIRX0N__XGPIOC_10 3 +#define PAD_MIPIRX0N__IIC1_SCL 4 +#define PAD_MIPIRX0N__CAM_MCLK1 5 +#define PAD_MIPIRX0N__DBG_10 7 +#define PAD_MIPIRX0P__VI0_D_8 1 +#define PAD_MIPIRX0P__VO_D_5 2 +#define PAD_MIPIRX0P__XGPIOC_11 3 +#define PAD_MIPIRX0P__CAM_MCLK0 4 +#define PAD_MIPIRX0P__DBG_11 7 +#define PAD_MIPI_TXM4__SD1_CLK 1 +#define PAD_MIPI_TXM4__VO_D_24 2 +#define PAD_MIPI_TXM4__XGPIOC_18 3 +#define PAD_MIPI_TXM4__CAM_MCLK1 4 +#define PAD_MIPI_TXM4__PWM_12 5 +#define PAD_MIPI_TXM4__IIC1_SDA 6 +#define PAD_MIPI_TXM4__DBG_18 7 +#define PAD_MIPI_TXP4__SD1_CMD 1 +#define PAD_MIPI_TXP4__VO_D_25 2 +#define PAD_MIPI_TXP4__XGPIOC_19 3 +#define PAD_MIPI_TXP4__CAM_MCLK0 4 +#define PAD_MIPI_TXP4__PWM_13 5 +#define PAD_MIPI_TXP4__IIC1_SCL 6 +#define PAD_MIPI_TXP4__DBG_19 7 +#define PAD_MIPI_TXM3__SD1_D0 1 +#define PAD_MIPI_TXM3__VO_D_26 2 +#define PAD_MIPI_TXM3__XGPIOC_20 3 +#define PAD_MIPI_TXM3__IIC2_SDA 4 +#define PAD_MIPI_TXM3__PWM_14 5 +#define PAD_MIPI_TXM3__IIC1_SDA 6 +#define PAD_MIPI_TXM3__CAM_VS0 7 +#define PAD_MIPI_TXP3__SD1_D1 1 +#define PAD_MIPI_TXP3__VO_D_27 2 +#define PAD_MIPI_TXP3__XGPIOC_21 3 +#define PAD_MIPI_TXP3__IIC2_SCL 4 +#define PAD_MIPI_TXP3__PWM_15 5 +#define PAD_MIPI_TXP3__IIC1_SCL 6 +#define PAD_MIPI_TXP3__CAM_HS0 7 +#define PAD_MIPI_TXM2__VI0_D_13 1 +#define PAD_MIPI_TXM2__VO_D_0 2 +#define PAD_MIPI_TXM2__XGPIOC_16 3 +#define PAD_MIPI_TXM2__IIC1_SDA 4 +#define PAD_MIPI_TXM2__PWM_8 5 +#define PAD_MIPI_TXM2__SPI0_SCK 6 +#define PAD_MIPI_TXM2__SD1_D2 7 +#define PAD_MIPI_TXP2__VI0_D_14 1 +#define PAD_MIPI_TXP2__VO_CLK0 2 +#define PAD_MIPI_TXP2__XGPIOC_17 3 +#define PAD_MIPI_TXP2__IIC1_SCL 4 +#define PAD_MIPI_TXP2__PWM_9 5 +#define PAD_MIPI_TXP2__SPI0_CS_X 6 +#define PAD_MIPI_TXP2__SD1_D3 7 +#define PAD_MIPI_TXM1__VI0_D_11 1 +#define PAD_MIPI_TXM1__VO_D_2 2 +#define PAD_MIPI_TXM1__XGPIOC_14 3 +#define PAD_MIPI_TXM1__IIC2_SDA 4 +#define PAD_MIPI_TXM1__PWM_10 5 +#define PAD_MIPI_TXM1__SPI0_SDO 6 +#define PAD_MIPI_TXM1__DBG_14 7 +#define PAD_MIPI_TXP1__VI0_D_12 1 +#define PAD_MIPI_TXP1__VO_D_1 2 +#define PAD_MIPI_TXP1__XGPIOC_15 3 +#define PAD_MIPI_TXP1__IIC2_SCL 4 +#define PAD_MIPI_TXP1__PWM_11 5 +#define PAD_MIPI_TXP1__SPI0_SDI 6 +#define PAD_MIPI_TXP1__DBG_15 7 +#define PAD_MIPI_TXM0__VI0_D_9 1 +#define PAD_MIPI_TXM0__VO_D_4 2 +#define PAD_MIPI_TXM0__XGPIOC_12 3 +#define PAD_MIPI_TXM0__CAM_MCLK1 4 +#define PAD_MIPI_TXM0__PWM_14 5 +#define PAD_MIPI_TXM0__CAM_VS0 6 +#define PAD_MIPI_TXM0__DBG_12 7 +#define PAD_MIPI_TXP0__VI0_D_10 1 +#define PAD_MIPI_TXP0__VO_D_3 2 +#define PAD_MIPI_TXP0__XGPIOC_13 3 +#define PAD_MIPI_TXP0__CAM_MCLK0 4 +#define PAD_MIPI_TXP0__PWM_15 5 +#define PAD_MIPI_TXP0__CAM_HS0 6 +#define PAD_MIPI_TXP0__DBG_13 7 +#define PAD_AUD_AINL_MIC__XGPIOC_23 3 +#define PAD_AUD_AINL_MIC__IIS1_BCLK 4 +#define PAD_AUD_AINL_MIC__IIS2_BCLK 5 +#define PAD_AUD_AINR_MIC__XGPIOC_22 3 +#define PAD_AUD_AINR_MIC__IIS1_DO 4 +#define PAD_AUD_AINR_MIC__IIS2_DI 5 +#define PAD_AUD_AINR_MIC__IIS1_DI 6 +#define PAD_AUD_AOUTL__XGPIOC_25 3 +#define PAD_AUD_AOUTL__IIS1_LRCK 4 +#define PAD_AUD_AOUTL__IIS2_LRCK 5 +#define PAD_AUD_AOUTR__XGPIOC_24 3 +#define PAD_AUD_AOUTR__IIS1_DI 4 +#define PAD_AUD_AOUTR__IIS2_DO 5 +#define PAD_AUD_AOUTR__IIS1_DO 6 +#define GPIO_RTX__XGPIOB_23 3 +#define GPIO_RTX__PWM_1 4 +#define GPIO_RTX__CAM_MCLK0 5 +#define GPIO_ZQ__PWR_GPIO_24 3 +#define GPIO_ZQ__PWM_2 4 diff --git a/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h new file mode 100755 index 00000000000..9b3e81ef424 --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h @@ -0,0 +1,46 @@ +#ifndef _CV181X_PINMUX_H_ +#define _CV181X_PINMUX_H_ + +#define PINMUX_UART0 0 +#define PINMUX_UART1 1 +#define PINMUX_UART2 2 +#define PINMUX_UART3 3 +#define PINMUX_UART3_2 4 +#define PINMUX_I2C0 5 +#define PINMUX_I2C1 6 +#define PINMUX_I2C2 7 +#define PINMUX_I2C3 8 +#define PINMUX_I2C4 9 +#define PINMUX_I2C4_2 10 +#define PINMUX_SPI0 11 +#define PINMUX_SPI1 12 +#define PINMUX_SPI2 13 +#define PINMUX_SPI2_2 14 +#define PINMUX_SPI3 15 +#define PINMUX_SPI3_2 16 +#define PINMUX_I2S0 17 +#define PINMUX_I2S1 18 +#define PINMUX_I2S2 19 +#define PINMUX_I2S3 20 +#define PINMUX_USBID 21 +#define PINMUX_SDIO0 22 +#define PINMUX_SDIO1 23 +#define PINMUX_ND 24 +#define PINMUX_EMMC 25 +#define PINMUX_SPI_NOR 26 +#define PINMUX_SPI_NAND 27 +#define PINMUX_CAM0 28 +#define PINMUX_CAM1 29 +#define PINMUX_PCM0 30 +#define PINMUX_PCM1 31 +#define PINMUX_CSI0 32 +#define PINMUX_CSI1 33 +#define PINMUX_CSI2 34 +#define PINMUX_DSI 35 +#define PINMUX_VI0 36 +#define PINMUX_VO 37 +#define PINMUX_PWM1 38 +#define PINMUX_UART4 39 +#define PINMUX_SPI_NOR1 40 + +#endif // end of _CV181X_PINMUX_H_ diff --git a/bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h b/bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h new file mode 100755 index 00000000000..5dbf34be305 --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h @@ -0,0 +1,475 @@ +// $Module: fmux_gpio $ +// $RegisterBank Version: V 1.0.00 $ +// $Author: ghost $ +// $Date: Fri, 30 Jul 2021 08:58:54 PM $ +// + +//GEN REG ADDR/OFFSET/MASK +#define FMUX_GPIO_REG_IOCTRL_CAM_MCLK0 0x0 +#define FMUX_GPIO_REG_IOCTRL_CAM_PD0 0x4 +#define FMUX_GPIO_REG_IOCTRL_CAM_RST0 0x8 +#define FMUX_GPIO_REG_IOCTRL_CAM_MCLK1 0xc +#define FMUX_GPIO_REG_IOCTRL_CAM_PD1 0x10 +#define FMUX_GPIO_REG_IOCTRL_IIC3_SCL 0x14 +#define FMUX_GPIO_REG_IOCTRL_IIC3_SDA 0x18 +#define FMUX_GPIO_REG_IOCTRL_SD0_CLK 0x1c +#define FMUX_GPIO_REG_IOCTRL_SD0_CMD 0x20 +#define FMUX_GPIO_REG_IOCTRL_SD0_D0 0x24 +#define FMUX_GPIO_REG_IOCTRL_SD0_D1 0x28 +#define FMUX_GPIO_REG_IOCTRL_SD0_D2 0x2c +#define FMUX_GPIO_REG_IOCTRL_SD0_D3 0x30 +#define FMUX_GPIO_REG_IOCTRL_SD0_CD 0x34 +#define FMUX_GPIO_REG_IOCTRL_SD0_PWR_EN 0x38 +#define FMUX_GPIO_REG_IOCTRL_SPK_EN 0x3c +#define FMUX_GPIO_REG_IOCTRL_UART0_TX 0x40 +#define FMUX_GPIO_REG_IOCTRL_UART0_RX 0x44 +#define FMUX_GPIO_REG_IOCTRL_EMMC_RSTN 0x48 +#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT2 0x4c +#define FMUX_GPIO_REG_IOCTRL_EMMC_CLK 0x50 +#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT0 0x54 +#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT3 0x58 +#define FMUX_GPIO_REG_IOCTRL_EMMC_CMD 0x5c +#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT1 0x60 +#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TMS 0x64 +#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TCK 0x68 +#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TRST 0x6c +#define FMUX_GPIO_REG_IOCTRL_IIC0_SCL 0x70 +#define FMUX_GPIO_REG_IOCTRL_IIC0_SDA 0x74 +#define FMUX_GPIO_REG_IOCTRL_AUX0 0x78 +#define FMUX_GPIO_REG_IOCTRL_PWR_VBAT_DET 0x7c +#define FMUX_GPIO_REG_IOCTRL_PWR_RSTN 0x80 +#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ1 0x84 +#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ2 0x88 +#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ3 0x8c +#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP0 0x90 +#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP1 0x94 +#define FMUX_GPIO_REG_IOCTRL_PWR_BUTTON1 0x98 +#define FMUX_GPIO_REG_IOCTRL_PWR_ON 0x9c +#define FMUX_GPIO_REG_IOCTRL_XTAL_XIN 0xa0 +#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO0 0xa4 +#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO1 0xa8 +#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO2 0xac +#define FMUX_GPIO_REG_IOCTRL_CLK32K 0xb0 +#define FMUX_GPIO_REG_IOCTRL_CLK25M 0xb4 +#define FMUX_GPIO_REG_IOCTRL_IIC2_SCL 0xb8 +#define FMUX_GPIO_REG_IOCTRL_IIC2_SDA 0xbc +#define FMUX_GPIO_REG_IOCTRL_UART2_TX 0xc0 +#define FMUX_GPIO_REG_IOCTRL_UART2_RTS 0xc4 +#define FMUX_GPIO_REG_IOCTRL_UART2_RX 0xc8 +#define FMUX_GPIO_REG_IOCTRL_UART2_CTS 0xcc +#define FMUX_GPIO_REG_IOCTRL_SD1_D3 0xd0 +#define FMUX_GPIO_REG_IOCTRL_SD1_D2 0xd4 +#define FMUX_GPIO_REG_IOCTRL_SD1_D1 0xd8 +#define FMUX_GPIO_REG_IOCTRL_SD1_D0 0xdc +#define FMUX_GPIO_REG_IOCTRL_SD1_CMD 0xe0 +#define FMUX_GPIO_REG_IOCTRL_SD1_CLK 0xe4 +#define FMUX_GPIO_REG_IOCTRL_RSTN 0xe8 +#define FMUX_GPIO_REG_IOCTRL_PWM0_BUCK 0xec +#define FMUX_GPIO_REG_IOCTRL_ADC3 0xf0 +#define FMUX_GPIO_REG_IOCTRL_ADC2 0xf4 +#define FMUX_GPIO_REG_IOCTRL_ADC1 0xf8 +#define FMUX_GPIO_REG_IOCTRL_USB_ID 0xfc +#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_EN 0x100 +#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE0 0x104 +#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_DET 0x108 +#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE1 0x10c +#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE2 0x110 +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MISO 0x114 +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MOSI 0x118 +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_CS 0x11c +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_SCK 0x120 +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXM 0x124 +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXP 0x128 +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXM 0x12c +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXP 0x130 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D10 0x134 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D9 0x138 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D8 0x13c +#define FMUX_GPIO_REG_IOCTRL_VIVO_D7 0x140 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D6 0x144 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D5 0x148 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D4 0x14c +#define FMUX_GPIO_REG_IOCTRL_VIVO_D3 0x150 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D2 0x154 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D1 0x158 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D0 0x15c +#define FMUX_GPIO_REG_IOCTRL_VIVO_CLK 0x160 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5N 0x164 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5P 0x168 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4N 0x16c +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4P 0x170 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3N 0x174 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3P 0x178 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2N 0x17c +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2P 0x180 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1N 0x184 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1P 0x188 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0N 0x18c +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0P 0x190 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM4 0x194 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP4 0x198 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM3 0x19c +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP3 0x1a0 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM2 0x1a4 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP2 0x1a8 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM1 0x1ac +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP1 0x1b0 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM0 0x1b4 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP0 0x1b8 +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINL_MIC 0x1bc +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINR_MIC 0x1c0 +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTL 0x1c4 +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTR 0x1c8 +#define FMUX_GPIO_REG_IOCTRL_GPIO_RTX 0x1cc +#define FMUX_GPIO_REG_IOCTRL_GPIO_ZQ 0x1d0 +#define FMUX_GPIO_FUNCSEL_CAM_MCLK0 0x0 +#define FMUX_GPIO_FUNCSEL_CAM_MCLK0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CAM_MCLK0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CAM_PD0 0x4 +#define FMUX_GPIO_FUNCSEL_CAM_PD0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CAM_PD0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CAM_RST0 0x8 +#define FMUX_GPIO_FUNCSEL_CAM_RST0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CAM_RST0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CAM_MCLK1 0xc +#define FMUX_GPIO_FUNCSEL_CAM_MCLK1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CAM_MCLK1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CAM_PD1 0x10 +#define FMUX_GPIO_FUNCSEL_CAM_PD1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CAM_PD1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC3_SCL 0x14 +#define FMUX_GPIO_FUNCSEL_IIC3_SCL_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC3_SCL_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC3_SDA 0x18 +#define FMUX_GPIO_FUNCSEL_IIC3_SDA_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC3_SDA_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_CLK 0x1c +#define FMUX_GPIO_FUNCSEL_SD0_CLK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_CLK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_CMD 0x20 +#define FMUX_GPIO_FUNCSEL_SD0_CMD_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_CMD_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D0 0x24 +#define FMUX_GPIO_FUNCSEL_SD0_D0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D1 0x28 +#define FMUX_GPIO_FUNCSEL_SD0_D1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D2 0x2c +#define FMUX_GPIO_FUNCSEL_SD0_D2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D3 0x30 +#define FMUX_GPIO_FUNCSEL_SD0_D3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_CD 0x34 +#define FMUX_GPIO_FUNCSEL_SD0_CD_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_CD_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN 0x38 +#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SPK_EN 0x3c +#define FMUX_GPIO_FUNCSEL_SPK_EN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SPK_EN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART0_TX 0x40 +#define FMUX_GPIO_FUNCSEL_UART0_TX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART0_TX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART0_RX 0x44 +#define FMUX_GPIO_FUNCSEL_UART0_RX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART0_RX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_RSTN 0x48 +#define FMUX_GPIO_FUNCSEL_EMMC_RSTN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_RSTN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT2 0x4c +#define FMUX_GPIO_FUNCSEL_EMMC_DAT2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_CLK 0x50 +#define FMUX_GPIO_FUNCSEL_EMMC_CLK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_CLK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT0 0x54 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT3 0x58 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_CMD 0x5c +#define FMUX_GPIO_FUNCSEL_EMMC_CMD_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_CMD_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT1 0x60 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS 0x64 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK 0x68 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST 0x6c +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC0_SCL 0x70 +#define FMUX_GPIO_FUNCSEL_IIC0_SCL_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC0_SCL_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC0_SDA 0x74 +#define FMUX_GPIO_FUNCSEL_IIC0_SDA_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC0_SDA_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_AUX0 0x78 +#define FMUX_GPIO_FUNCSEL_AUX0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_AUX0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET 0x7c +#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_RSTN 0x80 +#define FMUX_GPIO_FUNCSEL_PWR_RSTN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_RSTN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ1 0x84 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ2 0x88 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ3 0x8c +#define FMUX_GPIO_FUNCSEL_PWR_SEQ3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0 0x90 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1 0x94 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1 0x98 +#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_ON 0x9c +#define FMUX_GPIO_FUNCSEL_PWR_ON_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_ON_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_XTAL_XIN 0xa0 +#define FMUX_GPIO_FUNCSEL_XTAL_XIN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_XTAL_XIN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO0 0xa4 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO1 0xa8 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO2 0xac +#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CLK32K 0xb0 +#define FMUX_GPIO_FUNCSEL_CLK32K_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CLK32K_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CLK25M 0xb4 +#define FMUX_GPIO_FUNCSEL_CLK25M_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CLK25M_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC2_SCL 0xb8 +#define FMUX_GPIO_FUNCSEL_IIC2_SCL_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC2_SCL_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC2_SDA 0xbc +#define FMUX_GPIO_FUNCSEL_IIC2_SDA_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC2_SDA_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART2_TX 0xc0 +#define FMUX_GPIO_FUNCSEL_UART2_TX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART2_TX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART2_RTS 0xc4 +#define FMUX_GPIO_FUNCSEL_UART2_RTS_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART2_RTS_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART2_RX 0xc8 +#define FMUX_GPIO_FUNCSEL_UART2_RX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART2_RX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART2_CTS 0xcc +#define FMUX_GPIO_FUNCSEL_UART2_CTS_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART2_CTS_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D3 0xd0 +#define FMUX_GPIO_FUNCSEL_SD1_D3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D2 0xd4 +#define FMUX_GPIO_FUNCSEL_SD1_D2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D1 0xd8 +#define FMUX_GPIO_FUNCSEL_SD1_D1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D0 0xdc +#define FMUX_GPIO_FUNCSEL_SD1_D0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_CMD 0xe0 +#define FMUX_GPIO_FUNCSEL_SD1_CMD_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_CMD_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_CLK 0xe4 +#define FMUX_GPIO_FUNCSEL_SD1_CLK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_CLK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_RSTN 0xe8 +#define FMUX_GPIO_FUNCSEL_RSTN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_RSTN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWM0_BUCK 0xec +#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_ADC3 0xf0 +#define FMUX_GPIO_FUNCSEL_ADC3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_ADC3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_ADC2 0xf4 +#define FMUX_GPIO_FUNCSEL_ADC2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_ADC2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_ADC1 0xf8 +#define FMUX_GPIO_FUNCSEL_ADC1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_ADC1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_USB_ID 0xfc +#define FMUX_GPIO_FUNCSEL_USB_ID_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_USB_ID_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN 0x100 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE0 0x104 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET 0x108 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE1 0x10c +#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE2 0x110 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO 0x114 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI 0x118 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS 0x11c +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK 0x120 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM 0x124 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP 0x128 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM 0x12c +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP 0x130 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D10 0x134 +#define FMUX_GPIO_FUNCSEL_VIVO_D10_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D10_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D9 0x138 +#define FMUX_GPIO_FUNCSEL_VIVO_D9_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D9_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D8 0x13c +#define FMUX_GPIO_FUNCSEL_VIVO_D8_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D8_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D7 0x140 +#define FMUX_GPIO_FUNCSEL_VIVO_D7_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D7_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D6 0x144 +#define FMUX_GPIO_FUNCSEL_VIVO_D6_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D6_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D5 0x148 +#define FMUX_GPIO_FUNCSEL_VIVO_D5_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D5_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D4 0x14c +#define FMUX_GPIO_FUNCSEL_VIVO_D4_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D4_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D3 0x150 +#define FMUX_GPIO_FUNCSEL_VIVO_D3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D2 0x154 +#define FMUX_GPIO_FUNCSEL_VIVO_D2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D1 0x158 +#define FMUX_GPIO_FUNCSEL_VIVO_D1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D0 0x15c +#define FMUX_GPIO_FUNCSEL_VIVO_D0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_CLK 0x160 +#define FMUX_GPIO_FUNCSEL_VIVO_CLK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_CLK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N 0x164 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P 0x168 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N 0x16c +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P 0x170 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N 0x174 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P 0x178 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N 0x17c +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P 0x180 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N 0x184 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P 0x188 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N 0x18c +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P 0x190 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4 0x194 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4 0x198 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3 0x19c +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3 0x1a0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2 0x1a4 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2 0x1a8 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1 0x1ac +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1 0x1b0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0 0x1b4 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0 0x1b8 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC 0x1bc +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC 0x1c0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL 0x1c4 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR 0x1c8 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_GPIO_RTX 0x1cc +#define FMUX_GPIO_FUNCSEL_GPIO_RTX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_GPIO_RTX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_GPIO_ZQ 0x1d0 +#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_MASK 0x7 diff --git a/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h b/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h new file mode 100755 index 00000000000..1f064ebd737 --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved. + * + * File Name: pinctrl.h + * Description: + */ + +#ifndef __PINCTRL_CV181X_H__ +#define __PINCTRL_CV181X_H__ + +//#include "../core.h" +#include "cv181x_pinlist_swconfig.h" +#include "cv181x_reg_fmux_gpio.h" + +#define PAD_MIPI_TXM4__MIPI_TXM4 0 +#define PAD_MIPI_TXP4__MIPI_TXP4 0 +#define PAD_MIPI_TXM3__MIPI_TXM3 0 +#define PAD_MIPI_TXP3__MIPI_TXP3 0 +#define PAD_MIPI_TXM2__MIPI_TXM2 0 +#define PAD_MIPI_TXP2__MIPI_TXP2 0 +#define PAD_MIPI_TXM1__MIPI_TXM1 0 +#define PAD_MIPI_TXP1__MIPI_TXP1 0 +#define PAD_MIPI_TXM0__MIPI_TXM0 0 +#define PAD_MIPI_TXP0__MIPI_TXP0 0 + +#if defined(ARCH_ARM) && defined(RT_USING_SMART) +extern rt_ubase_t pinmux_base_ioremap(void); +#define PINMUX_BASE pinmux_base_ioremap() +#else +#define PINMUX_BASE 0x03001000 +#endif /* defined(ARCH_ARM) && defined(RT_USING_SMART) */ +#define PINMUX_MASK(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK +#define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET +#define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME +#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \ + mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \ + PINMUX_MASK(PIN_NAME) << PINMUX_OFFSET(PIN_NAME), \ + PINMUX_VALUE(PIN_NAME, FUNC_NAME)) + +#endif /* __PINCTRL_CV181X_H__ */ diff --git a/bsp/cvitek/drivers/cv1800b/mmio.h b/bsp/cvitek/drivers/libraries/mmio.h old mode 100644 new mode 100755 similarity index 99% rename from bsp/cvitek/drivers/cv1800b/mmio.h rename to bsp/cvitek/drivers/libraries/mmio.h index bc36d5a3ca9..2ef1930a1c1 --- a/bsp/cvitek/drivers/cv1800b/mmio.h +++ b/bsp/cvitek/drivers/libraries/mmio.h @@ -9,6 +9,7 @@ #include #include "types.h" +#ifndef ARCH_ARM #define __raw_readb(a) (*(volatile unsigned char *)(a)) #define __raw_readw(a) (*(volatile unsigned short *)(a)) #define __raw_readl(a) (*(volatile unsigned int *)(a)) @@ -39,13 +40,12 @@ #define writew(v, c) ({ __io_bw(); __raw_writew((v), (c)); __io_aw(); }) #define writel(v, c) ({ __io_bw(); __raw_writel((v), (c)); __io_aw(); }) - #ifdef CONFIG_64BIT #define readq(c) ({ u64 __v; __io_br(); __v = __raw_readq(c); __io_ar(__v); __v; }) #define writeq(v, c) ({ __io_bw(); __raw_writeq((v), (c)); __io_aw(); }) #endif // CONFIG_64BIT -/* +#else #define __raw_readb(a) (*(volatile unsigned char *)(a)) #define __raw_readw(a) (*(volatile unsigned short *)(a)) #define __raw_readl(a) (*(volatile unsigned int *)(a)) @@ -69,7 +69,7 @@ #define cpu_write8(a, v) writeb(a, v) #define cpu_write16(a, v) writew(a, v) #define cpu_write32(a, v) writel(a, v) -*/ +#endif /* ARCH_ARM */ #define mmio_wr32 mmio_write_32 #define mmio_rd32 mmio_read_32 diff --git a/bsp/cvitek/drivers/cv1800b/types.h b/bsp/cvitek/drivers/libraries/types.h similarity index 100% rename from bsp/cvitek/drivers/cv1800b/types.h rename to bsp/cvitek/drivers/libraries/types.h diff --git a/bsp/cvitek/cv1800b/mkimage b/bsp/cvitek/mkimage similarity index 100% rename from bsp/cvitek/cv1800b/mkimage rename to bsp/cvitek/mkimage diff --git a/bsp/cvitek/mksdimg.sh b/bsp/cvitek/mksdimg.sh new file mode 100755 index 00000000000..26e70bba620 --- /dev/null +++ b/bsp/cvitek/mksdimg.sh @@ -0,0 +1,44 @@ +#/bin/sh +set -e + +PROJECT_PATH=$1 +IMAGE_NAME=$2 + +if [ -z "$PROJECT_PATH" ] || [ -z "$IMAGE_NAME" ]; then + echo "Usage: $0 " + exit 1 +fi + +ROOT_PATH=$(pwd) +echo ${ROOT_PATH} + +. board_env.sh + +get_board_type + +echo "start compress kernel..." + +lzma -c -9 -f -k ${PROJECT_PATH}/${IMAGE_NAME} > ${PROJECT_PATH}/dtb/${BOARD_TYPE}/Image.lzma + +mkdir -p ${ROOT_PATH}/output/${BOARD_TYPE} +./mkimage -f ${PROJECT_PATH}/dtb/${BOARD_TYPE}/multi.its -r ${ROOT_PATH}/output/${BOARD_TYPE}/boot.${STORAGE_TYPE} + +if [ "${STORAGE_TYPE}" == "spinor" ] || [ "${STORAGE_TYPE}" == "spinand" ]; then + + check_bootloader || exit 0 + + pushd cvitek_bootloader + + . env.sh + get_build_board ${BOARD_TYPE} + + CHIP_ARCH_L=$(echo $CHIP_ARCH | tr '[:upper:]' '[:lower:]') + + echo "board: ${MV_BOARD_LINK}" + + IMGTOOL_PATH=build/tools/common/image_tool + FLASH_PARTITION_XML=build/boards/"${CHIP_ARCH_L}"/"${MV_BOARD_LINK}"/partition/partition_"${STORAGE_TYPE}".xml + python3 "$IMGTOOL_PATH"/raw2cimg.py "${ROOT_PATH}"/output/"${BOARD_TYPE}"/boot."$STORAGE_TYPE" "${ROOT_PATH}/output/${BOARD_TYPE}" "$FLASH_PARTITION_XML" + + popd +fi \ No newline at end of file diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin deleted file mode 100755 index 84ea0561c04..00000000000 Binary files a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin and /dev/null differ diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin deleted file mode 100755 index c9902e4a9e5..00000000000 --- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin +++ /dev/null @@ -1 +0,0 @@ -ﾭ \ No newline at end of file diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env deleted file mode 100755 index cff9e11100b..00000000000 --- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env +++ /dev/null @@ -1,2 +0,0 @@ -MONITOR_RUNADDR=0x0000000080000000 -BLCP_2ND_RUNADDR=0x0000000083f40000 diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin deleted file mode 100755 index d2dabd68683..00000000000 Binary files a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin and /dev/null differ diff --git a/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h b/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h deleted file mode 100755 index 906c5b0ba6a..00000000000 --- a/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __BOARD_MMAP__83494f74__ -#define __BOARD_MMAP__83494f74__ - -#define CONFIG_SYS_TEXT_BASE 0x80200000 /* offset 2.0MiB */ -#define CVIMMAP_ATF_SIZE 0x80000 /* 512.0KiB */ -#define CVIMMAP_BOOTLOGO_ADDR 0x82473000 /* offset 36.44921875MiB */ -#define CVIMMAP_BOOTLOGO_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_CONFIG_SYS_INIT_SP_ADDR 0x82300000 /* offset 35.0MiB */ -#define CVIMMAP_CVI_UPDATE_HEADER_ADDR 0x813ffc00 /* offset 19.9990234375MiB */ -#define CVIMMAP_CVI_UPDATE_HEADER_SIZE 0x400 /* 1.0KiB */ -#define CVIMMAP_DRAM_BASE 0x80000000 /* offset 0.0KiB */ -#define CVIMMAP_DRAM_SIZE 0x4000000 /* 64.0MiB */ -#define CVIMMAP_FREERTOS_ADDR 0x83f40000 /* offset 63.25MiB */ -#define CVIMMAP_FREERTOS_RESERVED_ION_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_FREERTOS_SIZE 0xc0000 /* 768.0KiB */ -#define CVIMMAP_FSBL_C906L_START_ADDR 0x83f40000 /* offset 63.25MiB */ -#define CVIMMAP_FSBL_UNZIP_ADDR 0x81400000 /* offset 20.0MiB */ -#define CVIMMAP_FSBL_UNZIP_SIZE 0xf00000 /* 15.0MiB */ -#define CVIMMAP_H26X_BITSTREAM_ADDR 0x82473000 /* offset 36.44921875MiB */ -#define CVIMMAP_H26X_BITSTREAM_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_H26X_ENC_BUFF_ADDR 0x82473000 /* offset 36.44921875MiB */ -#define CVIMMAP_H26X_ENC_BUFF_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_ION_ADDR 0x82473000 /* offset 36.44921875MiB */ -#define CVIMMAP_ION_SIZE 0x1acd000 /* 26.80078125MiB */ -#define CVIMMAP_ISP_MEM_BASE_ADDR 0x82473000 /* offset 36.44921875MiB */ -#define CVIMMAP_ISP_MEM_BASE_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_KERNEL_MEMORY_ADDR 0x80000000 /* offset 0.0KiB */ -#define CVIMMAP_KERNEL_MEMORY_SIZE 0x3f40000 /* 63.25MiB */ -#define CVIMMAP_MONITOR_ADDR 0x80000000 /* offset 0.0KiB */ -#define CVIMMAP_OPENSBI_FDT_ADDR 0x80080000 /* offset 512.0KiB */ -#define CVIMMAP_OPENSBI_SIZE 0x80000 /* 512.0KiB */ -#define CVIMMAP_UIMAG_ADDR 0x81400000 /* offset 20.0MiB */ -#define CVIMMAP_UIMAG_SIZE 0xf00000 /* 15.0MiB */ - -#endif /* __BOARD_MMAP__83494f74__ */ diff --git a/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py b/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py deleted file mode 100755 index 2c487eda69a..00000000000 --- a/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env python3 - -import logging -import struct -import argparse - -CHIP_CONF_CMD_DELAY_MS = 0xFFFFFFFD -CHIP_CONF_CMD_DELAY_US = 0xFFFFFFFE - -CHIP_CONF_SCAN_START_1 = 0xFFFFFFA0 - - -def gen_chip_conf(args): - logging.info("gen_chip_conf") - regs = [ - (0x0E00000C, 0xA0000001), # ATF_DBG_REG = 0x0E00000C - (0x0E00000C, 0xA0000002), - # (CHIP_CONF_CMD_DELAY_MS, 100), - # (CHIP_CONF_CMD_DELAY_US, 100), - (CHIP_CONF_SCAN_START_1, 0xFFFFFFFF), - ] - - chip_conf = b"".join(struct.pack("= %r is required" % (PYTHON_MIN_VERSION,)) - sys.exit(-1) - - -try: - import coloredlogs -except ImportError: - coloredlogs = None - -try: - import argcomplete -except ImportError: - argcomplete = None - - -LOADER_2ND_MAGIC_ORIG = b"BL33" -LOADER_2ND_MAGIC_LZMA = b"B3MA" -LOADER_2ND_MAGIC_LZ4 = b"B3Z4" - -LOADER_2ND_MAGIC_LIST = [ - LOADER_2ND_MAGIC_ORIG, - LOADER_2ND_MAGIC_LZMA, - LOADER_2ND_MAGIC_LZ4, -] - -IMAGE_ALIGN = 512 -PARAM1_SIZE = 0x1000 -PARAM1_SIZE_WO_SIG = 0x800 -PARAM2_SIZE = 0x1000 - - -def round_up(divident, divisor): - return ((divident + divisor - 1) // divisor) * divisor - - -def lzma_compress(body): - z = lzma.LZMACompressor(lzma.FORMAT_ALONE, preset=lzma.PRESET_EXTREME) - compressed = z.compress(body) - compressed += z.flush() - - return compressed - - -def lz4_compress(body): - try: - import lz4.frame - except ImportError: - logging.error("lz4 is not installed. Run 'pip install lz4'.") - raise - - compressed = lz4.frame.compress(body) - return compressed - - -class Entry: - __slots__ = "name", "type", "addr", "_content", "entry_size" - - def __init__(self): - self.addr = None - self._content = None - - @property - def end(self): - return self.addr + self.entry_size - - @property - def content(self): - return self._content - - @content.setter - def content(self, value): - if type(value) == int: - value = value.to_bytes(self.entry_size, "little") - - if self.entry_size is not None: - if len(value) > self.entry_size: - raise ValueError("%s (%d bytes) must <= %#r" % (self.name, len(value), self.entry_size)) - value = value + b"\0" * (self.entry_size - len(value)) - - self._content = value - - @classmethod - def make(cls, name, entry_size, _type, init=None): - entry = Entry() - entry.name = name - entry.type = _type - entry.entry_size = entry_size - - if type(init) in (bytes, bytearray): - entry.content = bytes(init) - elif entry_size is not None: - entry.content = b"\0" * entry.entry_size - else: - entry.content = b"" - - return (name, entry) - - def toint(self): - if self.type != int: - raise TypeError("%s is not int type" % self.name) - - return int.from_bytes(self.content, "little") - - def tostr(self): - v = self.content - if self.type == int: - v = "%#08x" % self.toint() - elif type(self.content) in [bytes, bytearray]: - v = v.hex() - if len(v) > 32: - v = v[:32] + "..." - - return v - - def __str__(self): - v = self.tostr() - return "<%s=%s (%dbytes)>" % (self.name, v, self.entry_size) - - def __repr__(self): - v = self.tostr() - return "<%s: a=%#x s=%#x c=%s %r>" % (self.name, self.addr, self.entry_size, v, self.type) - - -class FIP: - param1 = OrderedDict( - [ - Entry.make("MAGIC1", 8, int, b"CVBL01\n\0"), - Entry.make("MAGIC2", 4, int), - Entry.make("PARAM_CKSUM", 4, int), - Entry.make("NAND_INFO", 128, int), - Entry.make("NOR_INFO", 36, int), - Entry.make("FIP_FLAGS", 8, int), - Entry.make("CHIP_CONF_SIZE", 4, int), - Entry.make("BLCP_IMG_CKSUM", 4, int), - Entry.make("BLCP_IMG_SIZE", 4, int), - Entry.make("BLCP_IMG_RUNADDR", 4, int), - Entry.make("BLCP_PARAM_LOADADDR", 4, int), - Entry.make("BLCP_PARAM_SIZE", 4, int), - Entry.make("BL2_IMG_CKSUM", 4, int), - Entry.make("BL2_IMG_SIZE", 4, int), - Entry.make("BLD_IMG_SIZE", 4, int), - Entry.make("PARAM2_LOADADDR", 4, int), - Entry.make("RESERVED1", 4, int), - Entry.make("CHIP_CONF", 760, bytes), - Entry.make("BL_EK", 32, bytes), - Entry.make("ROOT_PK", 512, bytes), - Entry.make("BL_PK", 512, bytes), - Entry.make("BL_PK_SIG", 512, bytes), - Entry.make("CHIP_CONF_SIG", 512, bytes), - Entry.make("BL2_IMG_SIG", 512, bytes), - Entry.make("BLCP_IMG_SIG", 512, bytes), - ] - ) - - body1 = OrderedDict( - [ - Entry.make("BLCP", None, bytes), - Entry.make("BL2", None, bytes), - ] - ) - - param2 = OrderedDict( - [ - Entry.make("MAGIC1", 8, int, b"CVLD02\n\0"), - Entry.make("PARAM2_CKSUM", 4, int), - Entry.make("RESERVED1", 4, bytes), - # DDR param - Entry.make("DDR_PARAM_CKSUM", 4, int), - Entry.make("DDR_PARAM_LOADADDR", 4, int), - Entry.make("DDR_PARAM_SIZE", 4, int), - Entry.make("DDR_PARAM_RESERVED", 4, int), - # BLCP_2ND - Entry.make("BLCP_2ND_CKSUM", 4, int), - Entry.make("BLCP_2ND_LOADADDR", 4, int), - Entry.make("BLCP_2ND_SIZE", 4, int), - Entry.make("BLCP_2ND_RUNADDR", 4, int), - # ATF-BL31 or OpenSBI - Entry.make("MONITOR_CKSUM", 4, int), - Entry.make("MONITOR_LOADADDR", 4, int), - Entry.make("MONITOR_SIZE", 4, int), - Entry.make("MONITOR_RUNADDR", 4, int), - # u-boot - Entry.make("LOADER_2ND_RESERVED0", 4, int), - Entry.make("LOADER_2ND_LOADADDR", 4, int), - Entry.make("LOADER_2ND_RESERVED1", 4, int), - Entry.make("LOADER_2ND_RESERVED2", 4, int), - # Reserved - Entry.make("RESERVED_LAST", 4096 - 16 * 5, bytes), - ] - ) - - body2 = OrderedDict( - [ - Entry.make("DDR_PARAM", None, bytes), - Entry.make("BLCP_2ND", None, bytes), - Entry.make("MONITOR", None, bytes), - Entry.make("LOADER_2ND", None, bytes), - ] - ) - - ldr_2nd_hdr = OrderedDict( - [ - Entry.make("JUMP0", 4, int), - Entry.make("MAGIC", 4, int), - Entry.make("CKSUM", 4, int), - Entry.make("SIZE", 4, int), - Entry.make("RUNADDR", 8, int), - Entry.make("RESERVED1", 4, int), - Entry.make("RESERVED2", 4, int), - ] - ) - - FIP_FLAGS_SCS_MASK = 0x000c - FIP_FLAGS_ENCRYPTED_MASK = 0x0030 - - def _param_size(self, param): - return max((e.end for e in param.values())) - - def _gen_param(self): - addr = 0 - for entry in self.param1.values(): - entry.addr = addr - addr += entry.entry_size - - assert PARAM1_SIZE_WO_SIG == self.param1["BL_PK_SIG"].addr - - addr = 0 - for entry in self.param2.values(): - entry.addr = addr - addr += entry.entry_size - - assert PARAM2_SIZE == self.param2["RESERVED_LAST"].addr + self.param2["RESERVED_LAST"].entry_size - - addr = 0 - for entry in self.ldr_2nd_hdr.values(): - entry.addr = addr - addr += entry.entry_size - - def __init__(self): - self.compress_algo = None - self._gen_param() - - def image_crc(self, image): - crc = binascii.crc_hqx(image, 0) - crc = pack("gpio, index->pin, value); } -rt_int8_t es32f0_pin_read(rt_device_t dev, rt_base_t pin) +rt_ssize_t es32f0_pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value; + rt_ssize_t value; const struct pin_index *index; value = PIN_LOW; index = get_pin(pin); if (index == RT_NULL) { - return value; + return -RT_EINVAL; } value = ald_gpio_read_pin(index->gpio, index->pin); return value; diff --git a/bsp/essemi/es32f0654/project.uvprojx b/bsp/essemi/es32f0654/project.uvprojx index b7d8f057d06..c470884e7b2 100644 --- a/bsp/essemi/es32f0654/project.uvprojx +++ b/bsp/essemi/es32f0654/project.uvprojx @@ -482,6 +482,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1013,79 +1032,79 @@ Libraries - ald_calc.c + ald_wdt.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_calc.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_wdt.c - ald_gpio.c + ald_spi.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_gpio.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_spi.c - utils.c + ald_bkpc.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\utils.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_bkpc.c - ald_acmp.c + ald_gpio.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_acmp.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_gpio.c - ald_crc.c + ald_rmu.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crc.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rmu.c - ald_spi.c + ald_smartcard.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_spi.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_smartcard.c - ald_tsense.c + ald_calc.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_tsense.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_calc.c - ald_can.c + ald_rtc.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_can.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rtc.c - ald_usart.c + ald_acmp.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_usart.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_acmp.c - ald_cmu.c + ald_uart.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_cmu.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_uart.c - ald_rmu.c + ald_dma.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rmu.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_dma.c @@ -1097,114 +1116,114 @@ - ald_pis.c + ald_tsense.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pis.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_tsense.c - ald_iap.c + ald_can.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_iap.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_can.c - ald_timer.c + ald_trng.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_timer.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_trng.c - ald_bkpc.c + ald_crc.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_bkpc.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crc.c - ald_flash_ext.c + ald_pis.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pis.c - ald_pmu.c + utils.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pmu.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\utils.c - ald_rtc.c + ald_iap.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_rtc.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_iap.c - ald_trng.c + ald_crypt.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_trng.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crypt.c - ald_flash.c + ald_timer.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_timer.c - ald_uart.c + ald_cmu.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_uart.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_cmu.c - ald_i2c.c + ald_flash_ext.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_i2c.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c - ald_adc.c + ald_pmu.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_adc.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_pmu.c - ald_dma.c + ald_adc.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_dma.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_adc.c - ald_smartcard.c + ald_flash.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_smartcard.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash.c - ald_wdt.c + ald_usart.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_wdt.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_usart.c - ald_crypt.c + ald_i2c.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_crypt.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_i2c.c diff --git a/bsp/essemi/es32f365x/project.ewp b/bsp/essemi/es32f365x/project.ewp index 97dcfdddee4..9d072964cde 100644 --- a/bsp/essemi/es32f365x/project.ewp +++ b/bsp/essemi/es32f365x/project.ewp @@ -2139,6 +2139,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c @@ -2263,109 +2266,109 @@ Libraries - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c - $PROJ_DIR$\..\es32f369x\libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\iar\startup_es32f36xx.s + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c + $PROJ_DIR$\..\es32f369x\libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\iar\startup_es32f36xx.s - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c - $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c + $PROJ_DIR$\..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c diff --git a/bsp/essemi/es32f365x/project.uvprojx b/bsp/essemi/es32f365x/project.uvprojx index 09222360dc0..74dada4e4eb 100644 --- a/bsp/essemi/es32f365x/project.uvprojx +++ b/bsp/essemi/es32f365x/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1042,44 +1061,37 @@ Libraries - ald_tsense.c - 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c - - - - - ald_nor_lcd.c + ald_i2s.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c - ald_usb.c + ald_ebi.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c - ald_rmu.c + ald_iap.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c - ald_calc.c + ald_dma.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c - ald_uart.c + ald_flash_ext.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c @@ -1091,23 +1103,23 @@ - ald_i2s.c + ald_cmu.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c - ald_cmu.c + ald_rtc.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c - ald_crypt.c + ald_usb.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c @@ -1119,9 +1131,9 @@ - ald_adc.c + ald_nor_lcd.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c @@ -1133,16 +1145,16 @@ - ald_qspi.c + ald_adc.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c - ald_iap.c + ald_flash.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c @@ -1154,44 +1166,51 @@ - ald_sram.c + ald_pmu.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c - ald_dac.c + ald_rmu.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c - ald_gpio.c + ald_acmp.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c - ald_nand.c + ald_crypt.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c - ald_timer.c + ald_wdt.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c - ald_wdt.c + ald_can.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c + + + + + ald_spi.c + 1 + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c @@ -1203,86 +1222,86 @@ - ald_ebi.c + ald_timer.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c - ald_flash_ext.c + utils.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c - startup_es32f36xx.s - 2 - ..\es32f369x\libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s + ald_calc.c + 1 + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c - utils.c + ald_dac.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c - ald_pmu.c - 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c + startup_es32f36xx.s + 2 + ..\es32f369x\libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s - ald_dma.c + ald_sram.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c - ald_spi.c + ald_gpio.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c - ald_acmp.c + ald_tsense.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c - ald_flash.c + ald_qspi.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c - ald_rtc.c + ald_uart.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c - ald_trng.c + ald_nand.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c - ald_can.c + ald_trng.c 1 - ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c + ..\es32f369x\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c diff --git a/bsp/essemi/es32f369x/applications/arduino_pinout/SConscript b/bsp/essemi/es32f369x/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/essemi/es32f369x/applications/arduino_pinout/SConscript +++ b/bsp/essemi/es32f369x/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/essemi/es32f369x/drivers/drv_gpio.c b/bsp/essemi/es32f369x/drivers/drv_gpio.c index ccfae8819b2..f97b89565a5 100644 --- a/bsp/essemi/es32f369x/drivers/drv_gpio.c +++ b/bsp/essemi/es32f369x/drivers/drv_gpio.c @@ -247,15 +247,15 @@ void es32f3_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) ald_gpio_write_pin(index->gpio, index->pin, value); } -rt_int8_t es32f3_pin_read(rt_device_t dev, rt_base_t pin) +rt_ssize_t es32f3_pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value; + rt_ssize_t value; const struct pin_index *index; value = PIN_LOW; index = get_pin(pin); if (index == RT_NULL) { - return value; + return -RT_EINVAL; } value = ald_gpio_read_pin(index->gpio, index->pin); return value; diff --git a/bsp/essemi/es32f369x/project.ewp b/bsp/essemi/es32f369x/project.ewp index 7ec0f7915bf..dad00bfffa8 100644 --- a/bsp/essemi/es32f369x/project.ewp +++ b/bsp/essemi/es32f369x/project.ewp @@ -2139,6 +2139,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c @@ -2263,109 +2266,109 @@ Libraries - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c - - - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c - - - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c + + + $PROJ_DIR$\libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\iar\startup_es32f36xx.s $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c - $PROJ_DIR$\libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\iar\startup_es32f36xx.s + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c - $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c + + + $PROJ_DIR$\libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c diff --git a/bsp/essemi/es32f369x/project.uvprojx b/bsp/essemi/es32f369x/project.uvprojx index 18c9a24f739..88578b36b8a 100644 --- a/bsp/essemi/es32f369x/project.uvprojx +++ b/bsp/essemi/es32f369x/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1042,23 +1061,23 @@ Libraries - ald_i2s.c + ald_cmu.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c - ald_dac.c + ald_spi.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c - ald_i2c.c + utils.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c @@ -1070,219 +1089,219 @@ - ald_usb.c + ald_acmp.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c - ald_gpio.c + ald_crc.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c - ald_uart.c + ald_nand.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c - ald_tsense.c + ald_flash.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c - ald_flash_ext.c + ald_tsense.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c - ald_rtc.c + ald_gpio.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c - ald_iap.c + ald_sram.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c - ald_rmu.c + ald_usb.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c - ald_adc.c + ald_bkpc.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c - ald_ebi.c + ald_flash_ext.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c - ald_sram.c + ald_rtchw.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c - ald_nand.c + ald_adc.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c - utils.c + ald_uart.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c - ald_can.c + ald_i2c.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c - ald_acmp.c + ald_iap.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c - ald_crypt.c + ald_wdt.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c - ald_rtchw.c + ald_can.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c - ald_crc.c + ald_rtc.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c - ald_trng.c + ald_nor_lcd.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c - ald_timer.c + ald_crypt.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c - ald_pis.c + ald_qspi.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c - ald_cmu.c + ald_i2s.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c - ald_nor_lcd.c + ald_pis.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c - ald_wdt.c - 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c + startup_es32f36xx.s + 2 + libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s - startup_es32f36xx.s - 2 - libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s + ald_timer.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c - ald_flash.c + ald_dma.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c - ald_spi.c + ald_pmu.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c - ald_dma.c + ald_dac.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c - ald_qspi.c + ald_rmu.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c - ald_pmu.c + ald_ebi.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c - ald_bkpc.c + ald_trng.c 1 - libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c diff --git a/bsp/essemi/es32vf2264/applications/arduino_pinout/SConscript b/bsp/essemi/es32vf2264/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/essemi/es32vf2264/applications/arduino_pinout/SConscript +++ b/bsp/essemi/es32vf2264/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/essemi/es32vf2264/drivers/drv_gpio.c b/bsp/essemi/es32vf2264/drivers/drv_gpio.c index dd13df8e094..1d4ca316788 100644 --- a/bsp/essemi/es32vf2264/drivers/drv_gpio.c +++ b/bsp/essemi/es32vf2264/drivers/drv_gpio.c @@ -246,7 +246,7 @@ void es32f3_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) ald_gpio_write_pin(index->gpio, index->pin, value); } -rt_int8_t es32f3_pin_read(rt_device_t dev, rt_base_t pin) +rt_ssize_t es32f3_pin_read(rt_device_t dev, rt_base_t pin) { int value; const struct pin_index *index; @@ -254,7 +254,7 @@ rt_int8_t es32f3_pin_read(rt_device_t dev, rt_base_t pin) index = get_pin(pin); if (index == RT_NULL) { - return value; + return -RT_EINVAL; } value = ald_gpio_read_pin(index->gpio, index->pin); return value; @@ -337,7 +337,7 @@ rt_err_t es32f3_pin_attach_irq(struct rt_device *device, rt_base_t pin, index = get_pin(pin); if (index == RT_NULL) { - return RT_ENOSYS; + return -RT_ENOSYS; } /* pin no. convert to dec no. */ for (irqindex = 0; irqindex < 16; irqindex++) @@ -349,7 +349,7 @@ rt_err_t es32f3_pin_attach_irq(struct rt_device *device, rt_base_t pin, } if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) { - return RT_ENOSYS; + return -RT_ENOSYS; } level = rt_hw_interrupt_disable(); if (pin_irq_hdr_tab[irqindex].pin == pin && @@ -363,7 +363,7 @@ rt_err_t es32f3_pin_attach_irq(struct rt_device *device, rt_base_t pin, if (pin_irq_hdr_tab[irqindex].pin != -1) { rt_hw_interrupt_enable(level); - return RT_EBUSY; + return -RT_EBUSY; } pin_irq_hdr_tab[irqindex].pin = pin; pin_irq_hdr_tab[irqindex].hdr = hdr; @@ -381,7 +381,7 @@ rt_err_t es32f3_pin_detach_irq(struct rt_device *device, rt_base_t pin) index = get_pin(pin); if (index == RT_NULL) { - return RT_ENOSYS; + return -RT_ENOSYS; } for (irqindex = 0; irqindex < 16; irqindex++) @@ -393,7 +393,7 @@ rt_err_t es32f3_pin_detach_irq(struct rt_device *device, rt_base_t pin) } if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) { - return RT_ENOSYS; + return -RT_ENOSYS; } level = rt_hw_interrupt_disable(); if (pin_irq_hdr_tab[irqindex].pin == -1) @@ -425,7 +425,7 @@ rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin, index = get_pin(pin); if (index == RT_NULL) { - return RT_ENOSYS; + return -RT_ENOSYS; } if (enabled == PIN_IRQ_ENABLE) { @@ -439,13 +439,13 @@ rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin, } if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) { - return RT_ENOSYS; + return -RT_ENOSYS; } level = rt_hw_interrupt_disable(); if (pin_irq_hdr_tab[irqindex].pin == -1) { rt_hw_interrupt_enable(level); - return RT_ENOSYS; + return -RT_ENOSYS; } irqmap = &pin_irq_map[irqindex]; ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct); @@ -479,14 +479,14 @@ rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin, irqmap = get_pin_irq_map(index->pin); if (irqmap == RT_NULL) { - return RT_ENOSYS; + return -RT_ENOSYS; } /*csi_vic_disable_sirq(irqmap->irqno);*/ } else { - return RT_ENOSYS; + return -RT_ENOSYS; } return RT_EOK; } diff --git a/bsp/fm33lc026/libraries/HAL_Drivers/drv_gpio.c b/bsp/fm33lc026/libraries/HAL_Drivers/drv_gpio.c index 9814fc9ff04..c605cc587cc 100644 --- a/bsp/fm33lc026/libraries/HAL_Drivers/drv_gpio.c +++ b/bsp/fm33lc026/libraries/HAL_Drivers/drv_gpio.c @@ -148,11 +148,11 @@ static void fm33_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t fm33_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t fm33_pin_read(rt_device_t dev, rt_base_t pin) { GPIO_Type *gpio_port; uint16_t gpio_pin; - rt_int8_t value = PIN_LOW; + rt_ssize_t value = PIN_LOW; if (PIN_PORT(pin) < PIN_STPORT_MAX) { @@ -160,6 +160,10 @@ static rt_int8_t fm33_pin_read(rt_device_t dev, rt_base_t pin) gpio_pin = PIN_STPIN(pin); value = FL_GPIO_GetInputPin(gpio_port, gpio_pin); } + else + { + value = -RT_EINVAL; + } return value; } @@ -404,7 +408,7 @@ static rt_err_t fm33_pin_irq_enable(struct rt_device *device, rt_base_t pin, return RT_EOK; } const static struct rt_pin_ops _fm33_pin_ops = - { +{ fm33_pin_mode, fm33_pin_write, fm33_pin_read, diff --git a/bsp/fm33lc026/project.uvprojx b/bsp/fm33lc026/project.uvprojx index b3c9ea738b1..ca1cf579c9e 100644 --- a/bsp/fm33lc026/project.uvprojx +++ b/bsp/fm33lc026/project.uvprojx @@ -540,6 +540,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/frdm-k64f/project.uvproj b/bsp/frdm-k64f/project.uvproj index 35ce81ac79f..2e308623eae 100644 --- a/bsp/frdm-k64f/project.uvproj +++ b/bsp/frdm-k64f/project.uvproj @@ -403,16 +403,16 @@ Applications - application.c + startup.c 1 - applications\application.c + applications\startup.c - startup.c + application.c 1 - applications\startup.c + applications\application.c @@ -515,6 +515,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/frdm-k64f/project.uvprojx b/bsp/frdm-k64f/project.uvprojx index 544f9e16975..0005a472890 100644 --- a/bsp/frdm-k64f/project.uvprojx +++ b/bsp/frdm-k64f/project.uvprojx @@ -376,16 +376,16 @@ Applications - startup.c + application.c 1 - applications\startup.c + applications\application.c - application.c + startup.c 1 - applications\application.c + applications\startup.c @@ -488,6 +488,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/ft2004/drivers/drv_sdctrl.c b/bsp/ft2004/drivers/drv_sdctrl.c index a1e6740046e..790a38aba06 100644 --- a/bsp/ft2004/drivers/drv_sdctrl.c +++ b/bsp/ft2004/drivers/drv_sdctrl.c @@ -598,7 +598,7 @@ int rthw_sdctrl_init(void) #endif normalIrqFlgs |= NORMAL_IRQ_CC; - /* register handler、irq enable bit and wait callback */ + /* register handler irq enable bit and wait callback */ FSdCtrl_SetHandler(ft_sdctrl_p, FTSDCTRL_CMDIRQID, rthw_sdctrl_nomarl_callback, ft_sdctrl_p); FSdCtrl_NormalIrqSet(ft_sdctrl_p, normalIrqFlgs); FSdCtrl_CmdWaitRegister(ft_sdctrl_p, rthw_sdctrl_cmd_wait); diff --git a/bsp/ft32/ft32f072xb-starter/project.uvprojx b/bsp/ft32/ft32f072xb-starter/project.uvprojx index 743a721f22d..fdac507ae9a 100644 --- a/bsp/ft32/ft32f072xb-starter/project.uvprojx +++ b/bsp/ft32/ft32f072xb-starter/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/ft32/libraries/Drivers/drv_gpio.c b/bsp/ft32/libraries/Drivers/drv_gpio.c index 313da3635ba..479294a3d03 100644 --- a/bsp/ft32/libraries/Drivers/drv_gpio.c +++ b/bsp/ft32/libraries/Drivers/drv_gpio.c @@ -135,11 +135,11 @@ static void ft32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t ft32_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t ft32_pin_read(rt_device_t dev, rt_base_t pin) { GPIO_TypeDef *gpio_port; uint16_t gpio_pin; - rt_int8_t value = PIN_LOW; + rt_ssize_t value = PIN_LOW; if (PIN_PORT(pin) < PIN_STPORT_MAX) { @@ -147,6 +147,10 @@ static rt_int8_t ft32_pin_read(rt_device_t dev, rt_base_t pin) gpio_pin = PIN_FTPIN(pin); value = GPIO_ReadInputDataBit(gpio_port, gpio_pin); } + else + { + return -RT_EINVAL; + } return value; } diff --git a/bsp/fujitsu/mb9x/mb9bf506r/project.ewp b/bsp/fujitsu/mb9x/mb9bf506r/project.ewp index 0df47a10d18..8b3f2c3e6a8 100644 --- a/bsp/fujitsu/mb9x/mb9bf506r/project.ewp +++ b/bsp/fujitsu/mb9x/mb9bf506r/project.ewp @@ -160,7 +160,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT __RTTHREAD__ __RT_IPC_SOURCE__ __RT_KERNEL_SOURCE__ @@ -1055,7 +1054,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT __RTTHREAD__ __RT_IPC_SOURCE__ __RT_KERNEL_SOURCE__ @@ -1793,10 +1791,10 @@ Applications - $PROJ_DIR$\applications\startup.c + $PROJ_DIR$\applications\application.c - $PROJ_DIR$\applications\application.c + $PROJ_DIR$\applications\startup.c @@ -1864,6 +1862,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c @@ -1892,7 +1893,7 @@ Drivers - $PROJ_DIR$\drivers\board.c + $PROJ_DIR$\drivers\fm3_uart.c $PROJ_DIR$\drivers\nand.c @@ -1901,7 +1902,7 @@ $PROJ_DIR$\drivers\led.c - $PROJ_DIR$\drivers\fm3_uart.c + $PROJ_DIR$\drivers\board.c diff --git a/bsp/fujitsu/mb9x/mb9bf506r/project.uvproj b/bsp/fujitsu/mb9x/mb9bf506r/project.uvproj index 657050fb1b2..fc122185f1f 100644 --- a/bsp/fujitsu/mb9x/mb9bf506r/project.uvproj +++ b/bsp/fujitsu/mb9x/mb9bf506r/project.uvproj @@ -384,16 +384,16 @@ Applications - application.c + startup.c 1 - applications\application.c + applications\startup.c - startup.c + application.c 1 - applications\startup.c + applications\application.c @@ -513,6 +513,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -670,16 +689,16 @@ Drivers - nand.c + fm3_uart.c 1 - drivers\nand.c + drivers\fm3_uart.c - fm3_uart.c + nand.c 1 - drivers\fm3_uart.c + drivers\nand.c diff --git a/bsp/fujitsu/mb9x/mb9bf568r/project.uvproj b/bsp/fujitsu/mb9x/mb9bf568r/project.uvproj index 04b4d710ad1..51f1eac663f 100644 --- a/bsp/fujitsu/mb9x/mb9bf568r/project.uvproj +++ b/bsp/fujitsu/mb9x/mb9bf568r/project.uvproj @@ -389,16 +389,16 @@ Applications - application.c + startup.c 1 - applications\application.c + applications\startup.c - startup.c + application.c 1 - applications\startup.c + applications\application.c @@ -518,6 +518,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -675,16 +694,16 @@ Drivers - board.c + drivers_serial.c 1 - drivers\board.c + drivers\serial.c - drivers_serial.c + board.c 1 - drivers\serial.c + drivers\board.c diff --git a/bsp/fujitsu/mb9x/mb9bf618s/project.ewp b/bsp/fujitsu/mb9x/mb9bf618s/project.ewp index 09bcbb10b64..3df37141902 100644 --- a/bsp/fujitsu/mb9x/mb9bf618s/project.ewp +++ b/bsp/fujitsu/mb9x/mb9bf618s/project.ewp @@ -169,7 +169,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT __RTTHREAD__ __RT_IPC_SOURCE__ __RT_KERNEL_SOURCE__ @@ -1114,7 +1113,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT __RTTHREAD__ __RT_IPC_SOURCE__ __RT_KERNEL_SOURCE__ @@ -1893,10 +1891,10 @@ Applications - $PROJ_DIR$\applications\application.c + $PROJ_DIR$\applications\startup.c - $PROJ_DIR$\applications\startup.c + $PROJ_DIR$\applications\application.c @@ -1964,6 +1962,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c @@ -1992,10 +1993,10 @@ Drivers - $PROJ_DIR$\drivers\board.c + $PROJ_DIR$\drivers\serial.c - $PROJ_DIR$\drivers\serial.c + $PROJ_DIR$\drivers\board.c $PROJ_DIR$\drivers\led.c diff --git a/bsp/fujitsu/mb9x/mb9bf618s/project.uvproj b/bsp/fujitsu/mb9x/mb9bf618s/project.uvproj index 33073d6d364..3b7f3b495d6 100644 --- a/bsp/fujitsu/mb9x/mb9bf618s/project.uvproj +++ b/bsp/fujitsu/mb9x/mb9bf618s/project.uvproj @@ -390,16 +390,16 @@ Applications - startup.c + application.c 1 - applications\startup.c + applications\application.c - application.c + startup.c 1 - applications\application.c + applications\startup.c @@ -519,6 +519,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -676,16 +695,16 @@ Drivers - board.c + drivers_serial.c 1 - drivers\board.c + drivers\serial.c - drivers_serial.c + board.c 1 - drivers\serial.c + drivers\board.c diff --git a/bsp/gd32/arm/gd32103c-eval/project.ewp b/bsp/gd32/arm/gd32103c-eval/project.ewp index 53e5aafe1d4..a20b8c3cb1b 100644 --- a/bsp/gd32/arm/gd32103c-eval/project.ewp +++ b/bsp/gd32/arm/gd32103c-eval/project.ewp @@ -2000,6 +2000,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/gd32/arm/gd32103c-eval/project.uvproj b/bsp/gd32/arm/gd32103c-eval/project.uvproj index e41dbda2ab0..80fdf64e8ef 100644 --- a/bsp/gd32/arm/gd32103c-eval/project.uvproj +++ b/bsp/gd32/arm/gd32103c-eval/project.uvproj @@ -522,6 +522,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32103c-eval/project.uvprojx b/bsp/gd32/arm/gd32103c-eval/project.uvprojx index b6bae9cc0f6..09bd371cda2 100644 --- a/bsp/gd32/arm/gd32103c-eval/project.uvprojx +++ b/bsp/gd32/arm/gd32103c-eval/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32105c-eval/project.ewp b/bsp/gd32/arm/gd32105c-eval/project.ewp index 36e2e83cdc1..20a64d171d0 100644 --- a/bsp/gd32/arm/gd32105c-eval/project.ewp +++ b/bsp/gd32/arm/gd32105c-eval/project.ewp @@ -2000,6 +2000,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/gd32/arm/gd32105c-eval/project.uvproj b/bsp/gd32/arm/gd32105c-eval/project.uvproj index f08109dcc9f..332c620e0a7 100644 --- a/bsp/gd32/arm/gd32105c-eval/project.uvproj +++ b/bsp/gd32/arm/gd32105c-eval/project.uvproj @@ -522,6 +522,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32105c-eval/project.uvprojx b/bsp/gd32/arm/gd32105c-eval/project.uvprojx index b0197bf684b..555014206bb 100644 --- a/bsp/gd32/arm/gd32105c-eval/project.uvprojx +++ b/bsp/gd32/arm/gd32105c-eval/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32105r-start/project.ewp b/bsp/gd32/arm/gd32105r-start/project.ewp index 36e2e83cdc1..20a64d171d0 100644 --- a/bsp/gd32/arm/gd32105r-start/project.ewp +++ b/bsp/gd32/arm/gd32105r-start/project.ewp @@ -2000,6 +2000,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/gd32/arm/gd32105r-start/project.uvproj b/bsp/gd32/arm/gd32105r-start/project.uvproj index ade82c59b93..ccd25ff36c4 100644 --- a/bsp/gd32/arm/gd32105r-start/project.uvproj +++ b/bsp/gd32/arm/gd32105r-start/project.uvproj @@ -522,6 +522,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32105r-start/project.uvprojx b/bsp/gd32/arm/gd32105r-start/project.uvprojx index 2e6e66a9fae..067b8f86cc7 100644 --- a/bsp/gd32/arm/gd32105r-start/project.uvprojx +++ b/bsp/gd32/arm/gd32105r-start/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32107c-eval/project.ewp b/bsp/gd32/arm/gd32107c-eval/project.ewp index e672e9066ea..55603b88131 100644 --- a/bsp/gd32/arm/gd32107c-eval/project.ewp +++ b/bsp/gd32/arm/gd32107c-eval/project.ewp @@ -2002,6 +2002,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/gd32/arm/gd32107c-eval/project.uvproj b/bsp/gd32/arm/gd32107c-eval/project.uvproj index 0f6f7e5778d..24e2eaa84c0 100644 --- a/bsp/gd32/arm/gd32107c-eval/project.uvproj +++ b/bsp/gd32/arm/gd32107c-eval/project.uvproj @@ -522,6 +522,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32107c-eval/project.uvprojx b/bsp/gd32/arm/gd32107c-eval/project.uvprojx index fdf48522c40..961a4b6cab8 100644 --- a/bsp/gd32/arm/gd32107c-eval/project.uvprojx +++ b/bsp/gd32/arm/gd32107c-eval/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32205r-start/project.ewp b/bsp/gd32/arm/gd32205r-start/project.ewp index 76cc47110b6..257bb46147b 100644 --- a/bsp/gd32/arm/gd32205r-start/project.ewp +++ b/bsp/gd32/arm/gd32205r-start/project.ewp @@ -2000,6 +2000,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/gd32/arm/gd32205r-start/project.uvproj b/bsp/gd32/arm/gd32205r-start/project.uvproj index e8bbe3002de..105815afea9 100644 --- a/bsp/gd32/arm/gd32205r-start/project.uvproj +++ b/bsp/gd32/arm/gd32205r-start/project.uvproj @@ -522,6 +522,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32205r-start/project.uvprojx b/bsp/gd32/arm/gd32205r-start/project.uvprojx index 9e9015ac9d5..93b7b8405e9 100644 --- a/bsp/gd32/arm/gd32205r-start/project.uvprojx +++ b/bsp/gd32/arm/gd32205r-start/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32207i-eval/project.ewp b/bsp/gd32/arm/gd32207i-eval/project.ewp index 1fbfff0e7d7..7420926346f 100644 --- a/bsp/gd32/arm/gd32207i-eval/project.ewp +++ b/bsp/gd32/arm/gd32207i-eval/project.ewp @@ -2000,6 +2000,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/gd32/arm/gd32207i-eval/project.uvproj b/bsp/gd32/arm/gd32207i-eval/project.uvproj index bede91dbe92..c42f132e72b 100644 --- a/bsp/gd32/arm/gd32207i-eval/project.uvproj +++ b/bsp/gd32/arm/gd32207i-eval/project.uvproj @@ -522,6 +522,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32207i-eval/project.uvprojx b/bsp/gd32/arm/gd32207i-eval/project.uvprojx index b4cb73b045e..e473780cddc 100644 --- a/bsp/gd32/arm/gd32207i-eval/project.uvprojx +++ b/bsp/gd32/arm/gd32207i-eval/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32303c-start/project.ewp b/bsp/gd32/arm/gd32303c-start/project.ewp index db39b2d9795..22f39057252 100644 --- a/bsp/gd32/arm/gd32303c-start/project.ewp +++ b/bsp/gd32/arm/gd32303c-start/project.ewp @@ -2000,6 +2000,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/gd32/arm/gd32303c-start/project.uvproj b/bsp/gd32/arm/gd32303c-start/project.uvproj index fef03e271f9..ccac00429e0 100644 --- a/bsp/gd32/arm/gd32303c-start/project.uvproj +++ b/bsp/gd32/arm/gd32303c-start/project.uvproj @@ -522,6 +522,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32303c-start/project.uvprojx b/bsp/gd32/arm/gd32303c-start/project.uvprojx index d7b1a1b6b34..65e9c03ae5a 100644 --- a/bsp/gd32/arm/gd32303c-start/project.uvprojx +++ b/bsp/gd32/arm/gd32303c-start/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32303e-eval/project.ewp b/bsp/gd32/arm/gd32303e-eval/project.ewp index 31412725f7e..6b5e92f4117 100644 --- a/bsp/gd32/arm/gd32303e-eval/project.ewp +++ b/bsp/gd32/arm/gd32303e-eval/project.ewp @@ -2000,6 +2000,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/gd32/arm/gd32303e-eval/project.uvproj b/bsp/gd32/arm/gd32303e-eval/project.uvproj index 3b8c5fb4299..de25cc74618 100644 --- a/bsp/gd32/arm/gd32303e-eval/project.uvproj +++ b/bsp/gd32/arm/gd32303e-eval/project.uvproj @@ -522,6 +522,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32303e-eval/project.uvprojx b/bsp/gd32/arm/gd32303e-eval/project.uvprojx index f9663a8fc48..58634d41f2b 100644 --- a/bsp/gd32/arm/gd32303e-eval/project.uvprojx +++ b/bsp/gd32/arm/gd32303e-eval/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32305r-start/project.ewp b/bsp/gd32/arm/gd32305r-start/project.ewp index 83d035a6d08..a86704604ac 100644 --- a/bsp/gd32/arm/gd32305r-start/project.ewp +++ b/bsp/gd32/arm/gd32305r-start/project.ewp @@ -2000,6 +2000,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/gd32/arm/gd32305r-start/project.uvproj b/bsp/gd32/arm/gd32305r-start/project.uvproj index 1f6eae713e8..b8d8efa6f59 100644 --- a/bsp/gd32/arm/gd32305r-start/project.uvproj +++ b/bsp/gd32/arm/gd32305r-start/project.uvproj @@ -522,6 +522,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32305r-start/project.uvprojx b/bsp/gd32/arm/gd32305r-start/project.uvprojx index 08e1a0ad786..a3c0ff864ad 100644 --- a/bsp/gd32/arm/gd32305r-start/project.uvprojx +++ b/bsp/gd32/arm/gd32305r-start/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32307e-start/project.ewp b/bsp/gd32/arm/gd32307e-start/project.ewp index f2d83dff77a..64b85d5aaeb 100644 --- a/bsp/gd32/arm/gd32307e-start/project.ewp +++ b/bsp/gd32/arm/gd32307e-start/project.ewp @@ -2000,6 +2000,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/gd32/arm/gd32307e-start/project.uvproj b/bsp/gd32/arm/gd32307e-start/project.uvproj index 1cb61c626d1..fbf506b22c5 100644 --- a/bsp/gd32/arm/gd32307e-start/project.uvproj +++ b/bsp/gd32/arm/gd32307e-start/project.uvproj @@ -522,6 +522,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32307e-start/project.uvprojx b/bsp/gd32/arm/gd32307e-start/project.uvprojx index d760043058e..8c12cf9fe8d 100644 --- a/bsp/gd32/arm/gd32307e-start/project.uvprojx +++ b/bsp/gd32/arm/gd32307e-start/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32407v-lckfb/project.ewp b/bsp/gd32/arm/gd32407v-lckfb/project.ewp index fa29f6db364..882eefbafc5 100644 --- a/bsp/gd32/arm/gd32407v-lckfb/project.ewp +++ b/bsp/gd32/arm/gd32407v-lckfb/project.ewp @@ -2011,6 +2011,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/gd32/arm/gd32407v-lckfb/project.uvproj b/bsp/gd32/arm/gd32407v-lckfb/project.uvproj index 06551351bc0..aaf64e82960 100644 --- a/bsp/gd32/arm/gd32407v-lckfb/project.uvproj +++ b/bsp/gd32/arm/gd32407v-lckfb/project.uvproj @@ -579,6 +579,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32407v-lckfb/project.uvprojx b/bsp/gd32/arm/gd32407v-lckfb/project.uvprojx index 619c202cc43..6fae9ed9b66 100644 --- a/bsp/gd32/arm/gd32407v-lckfb/project.uvprojx +++ b/bsp/gd32/arm/gd32407v-lckfb/project.uvprojx @@ -544,6 +544,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32407v-start/project.ewp b/bsp/gd32/arm/gd32407v-start/project.ewp index 55ba9a078aa..a9a281084b9 100644 --- a/bsp/gd32/arm/gd32407v-start/project.ewp +++ b/bsp/gd32/arm/gd32407v-start/project.ewp @@ -2009,6 +2009,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/gd32/arm/gd32407v-start/project.uvproj b/bsp/gd32/arm/gd32407v-start/project.uvproj index b77f3790b44..6584c25cbed 100644 --- a/bsp/gd32/arm/gd32407v-start/project.uvproj +++ b/bsp/gd32/arm/gd32407v-start/project.uvproj @@ -579,6 +579,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32407v-start/project.uvprojx b/bsp/gd32/arm/gd32407v-start/project.uvprojx index a1cdc9f04d7..68242775d1a 100644 --- a/bsp/gd32/arm/gd32407v-start/project.uvprojx +++ b/bsp/gd32/arm/gd32407v-start/project.uvprojx @@ -543,6 +543,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32450z-eval/project.ewp b/bsp/gd32/arm/gd32450z-eval/project.ewp index 7c478c22e18..f15047fea18 100644 --- a/bsp/gd32/arm/gd32450z-eval/project.ewp +++ b/bsp/gd32/arm/gd32450z-eval/project.ewp @@ -173,7 +173,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT GD32F450 __RTTHREAD__ USE_STDPERIPH_DRIVER @@ -1145,7 +1144,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT GD32F450 __RTTHREAD__ USE_STDPERIPH_DRIVER @@ -2008,6 +2006,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/gd32/arm/gd32450z-eval/project.uvproj b/bsp/gd32/arm/gd32450z-eval/project.uvproj index e79fd593ab7..58ee4991df1 100644 --- a/bsp/gd32/arm/gd32450z-eval/project.uvproj +++ b/bsp/gd32/arm/gd32450z-eval/project.uvproj @@ -522,6 +522,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32450z-eval/project.uvprojx b/bsp/gd32/arm/gd32450z-eval/project.uvprojx index 12f729f5360..7e9447d6292 100644 --- a/bsp/gd32/arm/gd32450z-eval/project.uvprojx +++ b/bsp/gd32/arm/gd32450z-eval/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32470z-lckfb/project.ewp b/bsp/gd32/arm/gd32470z-lckfb/project.ewp index 97e405f77f1..a8c8ec3bcce 100644 --- a/bsp/gd32/arm/gd32470z-lckfb/project.ewp +++ b/bsp/gd32/arm/gd32470z-lckfb/project.ewp @@ -173,7 +173,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT GD32F470 __RTTHREAD__ USE_STDPERIPH_DRIVER @@ -1145,7 +1144,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT GD32F470 __RTTHREAD__ USE_STDPERIPH_DRIVER @@ -2008,6 +2006,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/gd32/arm/gd32470z-lckfb/project.uvproj b/bsp/gd32/arm/gd32470z-lckfb/project.uvproj index 155b0e22a4e..d743b1d0ad1 100644 --- a/bsp/gd32/arm/gd32470z-lckfb/project.uvproj +++ b/bsp/gd32/arm/gd32470z-lckfb/project.uvproj @@ -522,6 +522,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/gd32470z-lckfb/project.uvprojx b/bsp/gd32/arm/gd32470z-lckfb/project.uvprojx index aa9874df061..f90e584c925 100644 --- a/bsp/gd32/arm/gd32470z-lckfb/project.uvprojx +++ b/bsp/gd32/arm/gd32470z-lckfb/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_core.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_core.h index 65c3dbf81e3..49853ad6f07 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_core.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_core.h @@ -10,27 +10,27 @@ /* Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -170,7 +170,7 @@ typedef struct _usb_class_core uint8_t (*set_intf) (usb_dev *udev, usb_req *req); /*!< device set interface callback */ uint8_t (*ctlx_in) (usb_dev *udev); /*!< device contrl in callback */ - uint8_t (*ctlx_out) (usb_dev *udev); + uint8_t (*ctlx_out) (usb_dev *udev); uint8_t (*data_in) (usb_dev *udev, uint8_t ep_num); /*!< device data in handler */ uint8_t (*data_out) (usb_dev *udev, uint8_t ep_num); /*!< device data out handler */ @@ -295,9 +295,9 @@ typedef struct _usb_core_driver __STATIC_INLINE uint32_t usb_coreintr_get(usb_core_regs *usb_regs) { uint32_t reg_data = usb_regs->gr->GINTEN; - + reg_data &= usb_regs->gr->GINTF; - + return reg_data; } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h index c187e8693f7..ef47066a494 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_dev.h @@ -10,27 +10,27 @@ /* Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -132,7 +132,7 @@ __STATIC_INLINE uint32_t usb_iepintnum_read (usb_core_driver *udev) uint32_t value = udev->regs.dr->DAEPINT; value &= udev->regs.dr->DAEPINTEN; - + return value & DAEPINT_IEPITB; } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_host.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_host.h index 53c5183eefa..b6e54f08fbd 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_host.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_host.h @@ -10,27 +10,27 @@ /* Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h index ff65e2bd9cb..cb06f0b3d44 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_hw.h @@ -10,27 +10,27 @@ /* Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h index ae93df81852..be75a1ef2fe 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usb_regs.h @@ -10,27 +10,27 @@ /* Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h index eb79e15d275..6ec3ec07f5f 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbd_int.h @@ -10,27 +10,27 @@ /* Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h index 99a606dad72..0944614771c 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Include/drv_usbh_int.h @@ -10,27 +10,27 @@ /* Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_core.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_core.c index ba9ee199b25..2d99cc78f1e 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_core.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_core.c @@ -10,27 +10,27 @@ /* Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -41,15 +41,15 @@ OF SUCH DAMAGE. static void usb_core_reset (usb_core_regs *usb_regs); /*! - \brief configure USB core basic + \brief configure USB core basic \param[in] usb_basic: pointer to USB capabilities \param[in] usb_regs: USB core registers \param[in] usb_core: USB core \param[out] none \retval operation status */ -usb_status usb_basic_init (usb_core_basic *usb_basic, - usb_core_regs *usb_regs, +usb_status usb_basic_init (usb_core_basic *usb_basic, + usb_core_regs *usb_regs, usb_core_enum usb_core) { /* configure USB default transfer mode as FIFO mode */ @@ -142,7 +142,7 @@ usb_status usb_basic_init (usb_core_basic *usb_basic, } /*! - \brief initializes the USB controller registers and + \brief initializes the USB controller registers and prepares the core device mode or host mode operation \param[in] usb_basic: pointer to USB capabilities \param[in] usb_regs: pointer to USB core registers @@ -222,9 +222,9 @@ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs) \param[out] none \retval operation status */ -usb_status usb_txfifo_write (usb_core_regs *usb_regs, - uint8_t *src_buf, - uint8_t fifo_num, +usb_status usb_txfifo_write (usb_core_regs *usb_regs, + uint8_t *src_buf, + uint8_t fifo_num, uint16_t byte_count) { uint32_t word_count = (byte_count + 3U) / 4U; diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c index 11bfab7e582..f7059516d18 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_dev.c @@ -10,27 +10,27 @@ /* Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -49,7 +49,7 @@ static const uint8_t EP0_MAXLEN[4] = { #ifdef USB_FS_CORE /* USB endpoint Tx FIFO size */ -static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = +static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = { (uint16_t)TX0_FIFO_FS_SIZE, (uint16_t)TX1_FIFO_FS_SIZE, @@ -61,7 +61,7 @@ static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = #ifdef USB_HS_CORE -uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT] = +uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT] = { (uint16_t)TX0_FIFO_HS_SIZE, (uint16_t)TX1_FIFO_HS_SIZE, @@ -215,7 +215,7 @@ usb_status usb_devint_enable (usb_core_driver *udev) usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc) { __IO uint32_t *reg_addr = NULL; - + uint8_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES; /* get the endpoint number */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_host.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_host.c index ab82a5ff035..a3e8d213070 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_host.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usb_host.c @@ -10,27 +10,27 @@ /* Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -61,7 +61,7 @@ usb_status usb_host_init (usb_core_driver *udev) /* initialize host configuration register */ if (USB_ULPI_PHY == udev->bp.phy_itf) { - usb_phyclock_config (udev, HCTL_30_60MHZ); + usb_phyclock_config (udev, HCTL_30_60MHZ); } else { usb_phyclock_config (udev, HCTL_48MHZ); } diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c index f22e79507e4..794102a67e3 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbd_int.c @@ -10,27 +10,27 @@ /* Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c index b4358ea9bcf..9a161e8f655 100644 --- a/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c +++ b/bsp/gd32/arm/libraries/GD32F4xx_Firmware_Library/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c @@ -10,27 +10,27 @@ /* Copyright (c) 2022, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -40,7 +40,7 @@ OF SUCH DAMAGE. #pragma O0 #elif defined (__GNUC__) /*!< GNU compiler */ #pragma GCC optimize ("O0") -#elif defined (__TASKING__) /*!< TASKING compiler */ +#elif defined (__TASKING__) /*!< TASKING compiler */ #pragma optimize=0 #endif /* __CC_ARM */ @@ -137,8 +137,8 @@ uint32_t usbh_isr (usb_core_driver *udev) \param[out] none \retval none */ -static inline void usb_pp_halt (usb_core_driver *udev, - uint8_t pp_num, +static inline void usb_pp_halt (usb_core_driver *udev, + uint8_t pp_num, uint32_t pp_int, usb_pipe_staus pp_status) { @@ -460,7 +460,7 @@ static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num) pp->urb_state = URB_DONE; if ((uint8_t)USB_EPTYPE_BULK == ((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U)) { - pp->data_toggle_out ^= 1U; + pp->data_toggle_out ^= 1U; } break; @@ -530,7 +530,7 @@ static uint32_t usbh_int_rxfifonoempty (usb_core_driver *udev) /* manage multiple transfer packet */ udev->host.pipe[pp_num].xfer_buf += count; udev->host.pipe[pp_num].xfer_count += count; - + xfer_count = udev->host.pipe[pp_num].xfer_count; udev->host.backup_xfercount[pp_num] = xfer_count; diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c index 5503f3c51ac..9bad48c034d 100644 --- a/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c +++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c @@ -362,15 +362,15 @@ static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) * @param dev, pin * @retval None */ -static rt_int8_t gd32_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t gd32_pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value = PIN_LOW; + rt_ssize_t value = PIN_LOW; const struct pin_index *index = RT_NULL; index = get_pin(pin); if (index == RT_NULL) { - return value; + return -RT_EINVAL; } value = gpio_input_bit_get(index->gpio_periph, index->pin); diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_pwm.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_pwm.c index 56d4f0ffe22..5daf2421cdc 100644 --- a/bsp/gd32/arm/libraries/gd32_drivers/drv_pwm.c +++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_pwm.c @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2023-06-05 zengjianwei first version + * Date Author Notes + * 2023-06-05 zengjianwei first version */ #include diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_sdio.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_sdio.c index d7d408ac1dc..813c0b6a4ad 100644 --- a/bsp/gd32/arm/libraries/gd32_drivers/drv_sdio.c +++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_sdio.c @@ -19,7 +19,7 @@ #define LOG_TAG "drv.sdio" #include "drv_log.h" -#define SDIO_DMA_USE_IPC 0//1:ʹipcͬ +#define SDIO_DMA_USE_IPC 0//1:使用ipc做同步 /* card status of R1 definitions */ #define SD_R1_OUT_OF_RANGE BIT(31) /* command's argument was out of the allowed range */ diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_spi_flash.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_spi_flash.c index b89813a926c..1fdaf3a715f 100644 --- a/bsp/gd32/arm/libraries/gd32_drivers/drv_spi_flash.c +++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_spi_flash.c @@ -34,7 +34,7 @@ static int rt_hw_spi_flash_init(void) static struct gd32_spi_cs spi_cs; spi_cs.GPIOx = GD25Q_SPI_CS_GPIOX; spi_cs.GPIO_Pin = GD25Q_SPI_CS_GPIOX_PIN_X; - + rcu_periph_clock_enable(GD25Q_SPI_CS_GPIOX_CLK); #if defined SOC_SERIES_GD32F4xx gpio_mode_set(spi_cs.GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, spi_cs.GPIO_Pin); diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c index b159661d11b..8d3df301d42 100644 --- a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c @@ -248,15 +248,15 @@ static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) * @param dev, pin * @retval None */ -static rt_int8_t gd32_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t gd32_pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value = PIN_LOW; + rt_ssize_t value = PIN_LOW; const struct pin_index *index = RT_NULL; index = get_pin(pin); if (index == RT_NULL) { - return value; + return -RT_EINVAL; } value = gpio_input_bit_get(index->gpio_periph, index->pin); diff --git a/bsp/hc32/ev_hc32f448_lqfp80/project.ewp b/bsp/hc32/ev_hc32f448_lqfp80/project.ewp index cc954d45f22..731b4c16f5a 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/project.ewp +++ b/bsp/hc32/ev_hc32f448_lqfp80/project.ewp @@ -1985,10 +1985,10 @@ Applications - $PROJ_DIR$\applications\xtal32_fcm.c + $PROJ_DIR$\applications\main.c - $PROJ_DIR$\applications\main.c + $PROJ_DIR$\applications\xtal32_fcm.c @@ -2047,6 +2047,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx b/bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx index 5c29eb30e62..468e2b9b847 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx +++ b/bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx @@ -493,6 +493,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewp b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewp index 848445c20d1..ab4e14eb479 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewp +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewp @@ -2049,6 +2049,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx index 8d7ac58443b..b16a88e6f1f 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx @@ -493,6 +493,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp b/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp index 3c24caf09d6..a7aca336fb4 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp @@ -1987,10 +1987,10 @@ Applications - $PROJ_DIR$\applications\main.c + $PROJ_DIR$\applications\xtal32_fcm.c - $PROJ_DIR$\applications\xtal32_fcm.c + $PROJ_DIR$\applications\main.c @@ -2049,6 +2049,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx b/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx index 30c1ebb4132..ecdf0a4ff0a 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx @@ -493,6 +493,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/hc32/libraries/hc32_drivers/drv_gpio.c b/bsp/hc32/libraries/hc32_drivers/drv_gpio.c index 29c2f57e479..6758436c0d3 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_gpio.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_gpio.c @@ -283,7 +283,7 @@ static void hc32_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t v } } -static rt_int8_t hc32_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t hc32_pin_read(struct rt_device *device, rt_base_t pin) { uint8_t gpio_port; uint16_t gpio_pin; @@ -302,6 +302,10 @@ static rt_int8_t hc32_pin_read(struct rt_device *device, rt_base_t pin) value = PIN_HIGH; } } + else + { + return -RT_EINVAL; + } return value; } diff --git a/bsp/hc32l136/drivers/drv_gpio.c b/bsp/hc32l136/drivers/drv_gpio.c index b76673da011..3407c0b98a1 100644 --- a/bsp/hc32l136/drivers/drv_gpio.c +++ b/bsp/hc32l136/drivers/drv_gpio.c @@ -145,11 +145,11 @@ static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t _pin_read(rt_device_t dev, rt_base_t pin) { uint8_t gpio_port; uint16_t gpio_pin; - rt_int8_t value = PIN_LOW; + rt_ssize_t value = PIN_LOW; if (pin < PIN_MAX_NUM) { @@ -164,6 +164,10 @@ static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin) value = PIN_HIGH; } } + else + { + value = -RT_EINVAL; + } return value; } diff --git a/bsp/hc32l136/drivers/drv_usart.c b/bsp/hc32l136/drivers/drv_usart.c index d5904a63d6c..0e5967dad09 100644 --- a/bsp/hc32l136/drivers/drv_usart.c +++ b/bsp/hc32l136/drivers/drv_usart.c @@ -270,7 +270,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, stcBaud.u32Baud = cfg->baud_rate; u16Scnt = Uart_CalScnt(uart->config->idx, &stcBaud); Uart_SetBaud(uart->config->idx, u16Scnt); - + Uart_ClrStatus(uart->config->idx, UartTC); Uart_ClrStatus(uart->config->idx, UartRC); Uart_DisableIrq(uart->config->idx, UartTxIrq); @@ -315,7 +315,7 @@ static int hc32_putc(struct rt_serial_device *serial, char c) RT_ASSERT(RT_NULL != serial); uart = rt_container_of(serial, struct hc32_uart, serial); - + if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX) { if (Uart_GetStatus(uart->config->idx, UartTC) == FALSE) diff --git a/bsp/hc32l136/drivers/drv_usart.h b/bsp/hc32l136/drivers/drv_usart.h index a948bde5d34..ca542de27a8 100644 --- a/bsp/hc32l136/drivers/drv_usart.h +++ b/bsp/hc32l136/drivers/drv_usart.h @@ -7,7 +7,7 @@ * Date Author Notes * 2021-08-19 pjq first version */ - + #ifndef __DRV_USART_H__ #define __DRV_USART_H__ diff --git a/bsp/hc32l136/project.ewp b/bsp/hc32l136/project.ewp index 33143a4d89d..2e9c27cbd33 100644 --- a/bsp/hc32l136/project.ewp +++ b/bsp/hc32l136/project.ewp @@ -2046,6 +2046,9 @@ $PROJ_DIR$\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/hc32l136/project.uvprojx b/bsp/hc32l136/project.uvprojx index e71f8ce8ab0..a0d61aba4d0 100644 --- a/bsp/hc32l136/project.uvprojx +++ b/bsp/hc32l136/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/hc32l196/drivers/drv_gpio.c b/bsp/hc32l196/drivers/drv_gpio.c index b35b13ebea7..ab007a5868e 100644 --- a/bsp/hc32l196/drivers/drv_gpio.c +++ b/bsp/hc32l196/drivers/drv_gpio.c @@ -103,14 +103,14 @@ static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t _pin_read(rt_device_t dev, rt_base_t pin) { en_gpio_port_t gpio_port; en_gpio_pin_t gpio_pin; if (pin >= PIN_MAX_NUM) { - return PIN_LOW; + return -RT_EINVAL; } gpio_port = GPIO_PORT(pin); diff --git a/bsp/hc32l196/project.uvprojx b/bsp/hc32l196/project.uvprojx index 12374cae697..935fd51ede5 100644 --- a/bsp/hc32l196/project.uvprojx +++ b/bsp/hc32l196/project.uvprojx @@ -478,6 +478,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/hk32/hk32f030c8-mini/project.ewp b/bsp/hk32/hk32f030c8-mini/project.ewp index 0c21e7abba0..1309324c597 100644 --- a/bsp/hk32/hk32f030c8-mini/project.ewp +++ b/bsp/hk32/hk32f030c8-mini/project.ewp @@ -2165,6 +2165,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/hk32/hk32f030c8-mini/project.uvproj b/bsp/hk32/hk32f030c8-mini/project.uvproj index e4d6eba2625..7fb1ea13a75 100644 --- a/bsp/hk32/hk32f030c8-mini/project.uvproj +++ b/bsp/hk32/hk32f030c8-mini/project.uvproj @@ -565,6 +565,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/hk32/hk32f030c8-mini/project.uvprojx b/bsp/hk32/hk32f030c8-mini/project.uvprojx index 1191fed6025..d3a508303d0 100644 --- a/bsp/hk32/hk32f030c8-mini/project.uvprojx +++ b/bsp/hk32/hk32f030c8-mini/project.uvprojx @@ -543,6 +543,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/hk32/libraries/rt_drivers/drv_gpio.c b/bsp/hk32/libraries/rt_drivers/drv_gpio.c index f5a7de8fd68..bc59b76aa4f 100644 --- a/bsp/hk32/libraries/rt_drivers/drv_gpio.c +++ b/bsp/hk32/libraries/rt_drivers/drv_gpio.c @@ -120,6 +120,11 @@ static rt_int8_t hk32_pin_read(rt_device_t dev, rt_base_t pin) gpio_pin = PIN_HKPIN(pin); value = GPIO_ReadInputDataBit(gpio_port, gpio_pin); } + else + { + return -RT_ENOSYS; + } + return value; } diff --git a/bsp/hpmicro/libraries/drivers/drv_gpio.c b/bsp/hpmicro/libraries/drivers/drv_gpio.c index 887d3a59130..6877fa607af 100644 --- a/bsp/hpmicro/libraries/drivers/drv_gpio.c +++ b/bsp/hpmicro/libraries/drivers/drv_gpio.c @@ -217,13 +217,13 @@ static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; } -static rt_int8_t hpm_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t hpm_pin_read(rt_device_t dev, rt_base_t pin) { /* TODO: Check the validity of the pin value */ uint32_t gpio_idx = pin >> 5; uint32_t pin_idx = pin & 0x1FU; - return (int) gpio_read_pin(HPM_GPIO0, gpio_idx, pin_idx); + return (rt_ssize_t) gpio_read_pin(HPM_GPIO0, gpio_idx, pin_idx); } static void hpm_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) @@ -310,13 +310,15 @@ static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_u return RT_EOK; } -const static struct rt_pin_ops hpm_pin_ops = { - .pin_mode = hpm_pin_mode, - .pin_write = hpm_pin_write, - .pin_read = hpm_pin_read, - .pin_attach_irq = hpm_pin_attach_irq, - .pin_detach_irq = hpm_pin_detach_irq, - .pin_irq_enable = hpm_pin_irq_enable}; +const static struct rt_pin_ops hpm_pin_ops = +{ + .pin_mode = hpm_pin_mode, + .pin_write = hpm_pin_write, + .pin_read = hpm_pin_read, + .pin_attach_irq = hpm_pin_attach_irq, + .pin_detach_irq = hpm_pin_detach_irq, + .pin_irq_enable = hpm_pin_irq_enable +}; int rt_hw_pin_init(void) { diff --git a/bsp/hpmicro/libraries/drivers/drv_uart.h b/bsp/hpmicro/libraries/drivers/drv_uart.h index 4c4a67db821..b316d47ea40 100644 --- a/bsp/hpmicro/libraries/drivers/drv_uart.h +++ b/bsp/hpmicro/libraries/drivers/drv_uart.h @@ -11,4 +11,4 @@ int rt_hw_uart_init(void); -#endif /* DRV_UART_H */ \ No newline at end of file +#endif /* DRV_UART_H */ diff --git a/bsp/hpmicro/libraries/drivers/drv_wdt.c b/bsp/hpmicro/libraries/drivers/drv_wdt.c index 5cf2274d0f6..63540a886d5 100644 --- a/bsp/hpmicro/libraries/drivers/drv_wdt.c +++ b/bsp/hpmicro/libraries/drivers/drv_wdt.c @@ -246,4 +246,4 @@ int rt_hw_wdt_init(void) } INIT_BOARD_EXPORT(rt_hw_wdt_init); -#endif /* RT_USING_WDT */ \ No newline at end of file +#endif /* RT_USING_WDT */ diff --git a/bsp/hpmicro/libraries/drivers/drv_wdt.h b/bsp/hpmicro/libraries/drivers/drv_wdt.h index 4c69255af0f..100ffc27dd8 100644 --- a/bsp/hpmicro/libraries/drivers/drv_wdt.h +++ b/bsp/hpmicro/libraries/drivers/drv_wdt.h @@ -11,4 +11,4 @@ int rt_hw_wdt_init(void); -#endif \ No newline at end of file +#endif diff --git a/bsp/ht32/ht32f12366/.config b/bsp/ht32/ht32f12366/.config new file mode 100644 index 00000000000..033557c8562 --- /dev/null +++ b/bsp/ht32/ht32f12366/.config @@ -0,0 +1,1093 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="usart0" +CONFIG_RT_VER_NUM=0x50100 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# CONFIG_RT_USING_CACHE is not set +CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M3=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI_BITOPS is not set +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# +CONFIG_SOC_FAMILY_HT32=y +CONFIG_SOC_SERIES_HT32F1=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HT32F12366=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_USART0=y +# CONFIG_BSP_USING_USART1 is not set +# CONFIG_BSP_USING_UART0 is not set +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C is not set + +# +# Board extended module Drivers +# diff --git a/bsp/ht32/ht32f12366/Kconfig b/bsp/ht32/ht32f12366/Kconfig new file mode 100644 index 00000000000..7a400db91f4 --- /dev/null +++ b/bsp/ht32/ht32f12366/Kconfig @@ -0,0 +1,22 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" + diff --git a/bsp/ht32/ht32f12366/README.md b/bsp/ht32/ht32f12366/README.md new file mode 100644 index 00000000000..04de7527d74 --- /dev/null +++ b/bsp/ht32/ht32f12366/README.md @@ -0,0 +1,107 @@ +# HT32F12366 BSP 说明 + +## 简介 + +ESK32-30105是合泰基于HT32F12366芯片并针对Cortex®-M3入门而设计的评估板。本文档是为ESK32-30105开发板提供的BSP(板级支持包)说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +## 开发板介绍 + +ESK32-30105使用32位ARM® Cortex®-M3高性能、低功耗单片机HT32F12366，针对Cortex®-M3入门而设计。开发板外观如下图所示： + +![board.png](figures/board.png) + +该开发板常用 **板载资源** 如下： + +- MCU：HT32F12366，主频 96MHz，256KB FLASH ，128KB SRAM +- 常用外设 + - LED：2个，（绿色，PE0、PD15） +- 常用接口：USB 转串口 、USB SLAVE +- 调试接口：板载的 e-Link32 Lite SWD 下载 + +开发板更多详细信息请参考合泰官网的相关文档 [ESK32-30105](https://www.holtek.com.cn/page/detail/dev_kit/ESK32-30105)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :--- | :---: | :--- | +| USB 转串口 | 支持 | 使用 USART0 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1...PE15 ---> PIN: 0, 1...79 | +| USART | 支持 | USART0/1 | +| UART | 支持 | UART0/1 | +| SPI | 支持 | SPI0/1 | +| I2C | 支持 | 硬件 I2C0/1 | +| ADC | 暂不支持 | | +| WDT | 暂不支持 | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多片上资源，实现更多高级功能。 + +### 快速上手 + +本 BSP 为仅为开发者提供MDK5的工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线通过板载的 e-Link32 Lite将芯片连接到 PC。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 注：工程默认配置使用CMSIS-DAP下载方式，在通过 e-Link32 Lite 连接开发板的基础上，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，LED1和LED2交替闪烁。 + +连接开发板对应串口到 PC（也可以通过e-Link32 Lite的模拟串口将开发板连接到PC）, 在终端工具里调整好串口配置（115200-8-1-N）并打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +> 注：由于RT-Thread的finsh控制台使用的是命令行的输入形式，推荐使用串口调试工具如：Tabby terminal 或者 Tera Term。 + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Apr 10 2024 14:39:43 + 2006 - 2024 Copyright by RT-Thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 USART0 的功能，如果需使用更多的片上资源，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`scons --target=mdk5` 命令重新生成工程。 + +## 注意事项 + +开发板和芯片的相关资料可以在[合泰官网](https://www.holtek.com.cn/page/index)进行查找和下载，如芯片的数据手册和开发使用手册、开发板的原理图、Keil_v5的pack安装包等。 + +## 联系人信息 + +维护人: + +- [QT-one](https://github.com/QT-one) \ No newline at end of file diff --git a/bsp/ht32/ht32f12366/SConscript b/bsp/ht32/ht32f12366/SConscript new file mode 100644 index 00000000000..682f94215ca --- /dev/null +++ b/bsp/ht32/ht32f12366/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os #包含os库 +Import('RTT_ROOT') #导入RTT_ROOT对象（RTT_ROOT代表的是RT-Thread源码包） +from building import * #把building模块的所有内容都导入到当前模块中 + +cwd = GetCurrentDir() #获取当前路径，并将该路径信息保存到变量cwd中 +objs = [] #创建一个list型变量objs +list = os.listdir(cwd) #得到当前目录下的所有子目录，并保存到变量list中 + +for d in list: #for循环用d记录循环的次数，直到寻遍所有路径 + path = os.path.join(cwd, d) #根据d获取到不同的路径 + if os.path.isfile(os.path.join(path, 'SConscript')): #如果该路径下存在名为SConscript的文件 + objs = objs + SConscript(os.path.join(d, 'SConscript')) #将路径中SConscript文件内的源码读取到objs中 + +Return('objs') #将objs返回出去 diff --git a/bsp/ht32/ht32f12366/SConstruct b/bsp/ht32/ht32f12366/SConstruct new file mode 100644 index 00000000000..5fcd0e3860a --- /dev/null +++ b/bsp/ht32/ht32f12366/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +ht32_library = 'HT32_STD_1xxxx_FWLib' +rtconfig.BSP_LIBRARY_TYPE = ht32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, ht32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ht32_drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/ht32/ht32f12366/applications/SConscript b/bsp/ht32/ht32f12366/applications/SConscript new file mode 100644 index 00000000000..9023be657ab --- /dev/null +++ b/bsp/ht32/ht32f12366/applications/SConscript @@ -0,0 +1,21 @@ +#导入其他模块的变量 +Import('RTT_ROOT') +Import('rtconfig') + +#导入使用到的模块 +from building import * + +#获取当前目录的路径 +cwd = GetCurrentDir() + +#创建一个列表，用于保存需要使用到的C文件路径 +src = Glob('*c') + +#创建一个列表，用于保存需要包含的H文件路径 +path = [cwd] + +#创建一个组别 +group = DefineGroup('Applications', src, depend = [''], CPPPATH = path) + +#返回创建好的组别 +Return('group') \ No newline at end of file diff --git a/bsp/ht32/ht32f12366/applications/main.c b/bsp/ht32/ht32f12366/applications/main.c new file mode 100644 index 00000000000..6df261c71be --- /dev/null +++ b/bsp/ht32/ht32f12366/applications/main.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include +#include +#include "board.h" + +/* defined the led2 pin: pd15 */ +#define LED1_PIN GET_PIN(D, 15) +/* defined the led3 pin: pe0 */ +#define LED2_PIN GET_PIN(E, 0) + +int main(void) +{ + rt_uint32_t speed = 200; + /* set led1 pin mode to output */ + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + /* set led2 pin mode to output */ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED1_PIN, PIN_LOW); + rt_pin_write(LED2_PIN, PIN_HIGH); + rt_thread_mdelay(speed); + rt_pin_write(LED1_PIN, PIN_HIGH); + rt_pin_write(LED2_PIN, PIN_LOW); + rt_thread_mdelay(speed); + } +} diff --git a/bsp/ht32/ht32f12366/board/Kconfig b/bsp/ht32/ht32f12366/board/Kconfig new file mode 100644 index 00000000000..3ee604b7be1 --- /dev/null +++ b/bsp/ht32/ht32f12366/board/Kconfig @@ -0,0 +1,77 @@ +menu "Hardware Drivers Config" + +config SOC_HT32F12366 + bool + select SOC_SERIES_HT32F1 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default n + +    menuconfig BSP_USING_UART + bool "Enable UART" + default n + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_USART0 + bool "Enable USART0" + default n + + config BSP_USING_USART1 + bool "Enable USART1" + default n + + config BSP_USING_UART0 + bool "Enable UART0" + default n + + config BSP_USING_UART1 + bool "Enable UART1" + default n +        endif + + menuconfig BSP_USING_SPI + bool "Enable SPI Bus" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0 Bus" + default n + + config BSP_USING_SPI1 + bool "Enable SPI1 Bus" + default n  + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C Bus" + default n + select RT_USING_I2C + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0 Bus" + default n + + config BSP_USING_I2C1 + bool "Enable I2C1 Bus" + default n + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/ht32/ht32f12366/board/SConscript b/bsp/ht32/ht32f12366/board/SConscript new file mode 100644 index 00000000000..ba173ea9682 --- /dev/null +++ b/bsp/ht32/ht32f12366/board/SConscript @@ -0,0 +1,27 @@ + +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +src = Glob('src/*.c') + +startup_path_prefix = SDK_LIB +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_01.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_01.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_01.s'] + +path = [cwd] +path = [cwd + '/inc'] + +CPPDEFINES = ['USE_HT32F12366_SK, USE_HT32F12365_66, USE_MEM_HT32F12366'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') \ No newline at end of file diff --git a/bsp/ht32/ht32f12366/board/inc/board.h b/bsp/ht32/ht32f12366/board/inc/board.h new file mode 100644 index 00000000000..91d5c2d0a53 --- /dev/null +++ b/bsp/ht32/ht32f12366/board/inc/board.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "ht32.h" +#include "ht32_msp.h" + +#ifdef BSP_USING_GPIO + #include "drv_gpio.h" +#endif + +#ifdef BSP_USING_UART + #include "drv_usart.h" +#endif + +#ifdef BSP_USING_SPI + #include "drv_spi.h" +#endif + +#ifdef BSP_USING_I2C + #include "drv_i2c.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* whether use board external SRAM memory */ +#define HT32_EXT_SRAM 0 +#define HT32_EXT_SRAM_BEGIN 0x68000000 +#define HT32_EXT_SRAM_END (HT32_EXT_SRAM_BEGIN + HT32_EXT_SRAM*1024) + +/* internal sram memory size */ +#define HT32_SRAM_END (0x20000000 + LIBCFG_RAM_SIZE) + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif +#define HEAP_END HT32_SRAM_END + +void rt_hw_board_clock_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/ht32/ht32f12366/board/inc/ht32_msp.h b/bsp/ht32/ht32f12366/board/inc/ht32_msp.h new file mode 100644 index 00000000000..8d05995146f --- /dev/null +++ b/bsp/ht32/ht32f12366/board/inc/ht32_msp.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __HT32_MSP_H__ +#define __HT32_MSP_H__ + +#include +#include "ht32.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* UART gpio */ +#ifdef BSP_USING_UART +#ifdef BSP_USING_USART0 + + #define HTCFG_USART0_IPN USART0 + + #define _HTCFG_USART0_TX_GPIOX A + #define _HTCFG_USART0_TX_GPION 8 + #define _HTCFG_USART0_RX_GPIOX A + #define _HTCFG_USART0_RX_GPION 10 + + #define HTCFG_USART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_TX_GPIOX) + #define HTCFG_USART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_TX_GPIOX) + #define HTCFG_USART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_TX_GPIOX) + #define HTCFG_USART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_TX_GPION) + + #define HTCFG_USART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_RX_GPIOX) + #define HTCFG_USART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_RX_GPIOX) + #define HTCFG_USART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_RX_GPIOX) + #define HTCFG_USART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_RX_GPION) + +#endif +#ifdef BSP_USING_USART1 + + #define HTCFG_USART1_IPN USART1 + + #define _HTCFG_USART1_TX_GPIOX A + #define _HTCFG_USART1_TX_GPION 4 + #define _HTCFG_USART1_RX_GPIOX A + #define _HTCFG_USART1_RX_GPION 5 + + #define HTCFG_USART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_TX_GPIOX) + #define HTCFG_USART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_TX_GPIOX) + #define HTCFG_USART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_TX_GPIOX) + #define HTCFG_USART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_TX_GPION) + + #define HTCFG_USART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_RX_GPIOX) + #define HTCFG_USART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_RX_GPIOX) + #define HTCFG_USART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_RX_GPIOX) + #define HTCFG_USART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_RX_GPION) + +#endif +#ifdef BSP_USING_UART0 + + #define HTCFG_UART0_IPN UART0 + + #define _HTCFG_UART0_TX_GPIOX C + #define _HTCFG_UART0_TX_GPION 9 + #define _HTCFG_UART0_RX_GPIOX C + #define _HTCFG_UART0_RX_GPION 10 + + #define HTCFG_UART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_TX_GPIOX) + #define HTCFG_UART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_TX_GPIOX) + #define HTCFG_UART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_TX_GPIOX) + #define HTCFG_UART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_TX_GPION) + + #define HTCFG_UART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_RX_GPIOX) + #define HTCFG_UART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_RX_GPIOX) + #define HTCFG_UART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_RX_GPIOX) + #define HTCFG_UART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_RX_GPION) + +#endif +#ifdef BSP_USING_UART1 + + #define HTCFG_UART1_IPN UART1 + + #define _HTCFG_UART1_TX_GPIOX C + #define _HTCFG_UART1_TX_GPION 2 + #define _HTCFG_UART1_RX_GPIOX C + #define _HTCFG_UART1_RX_GPION 3 + + #define HTCFG_UART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_TX_GPIOX) + #define HTCFG_UART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_TX_GPIOX) + #define HTCFG_UART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_TX_GPIOX) + #define HTCFG_UART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_TX_GPION) + + #define HTCFG_UART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_RX_GPIOX) + #define HTCFG_UART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_RX_GPIOX) + #define HTCFG_UART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_RX_GPIOX) + #define HTCFG_UART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_RX_GPION) + +#endif +#endif + +/* SPI gpio */ +#ifdef BSP_USING_SPI +#ifdef BSP_USING_SPI0 + + #define HTCFG_SPI0_IPN SPI0 + + #define _HTCFG_SPI0_SCK_GPIOX B + #define _HTCFG_SPI0_SCK_GPION 3 + + #define _HTCFG_SPI0_MISO_GPIOX B + #define _HTCFG_SPI0_MISO_GPION 5 + + #define _HTCFG_SPI0_MOSI_GPIOX B + #define _HTCFG_SPI0_MOSI_GPION 4 + + #define HTCFG_SPI0_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_SCK_GPIOX) + #define HTCFG_SPI0_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_SCK_GPIOX) + #define HTCFG_SPI0_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_SCK_GPION) + + #define HTCFG_SPI0_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MISO_GPIOX) + #define HTCFG_SPI0_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MISO_GPIOX) + #define HTCFG_SPI0_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MISO_GPION) + + #define HTCFG_SPI0_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MOSI_GPIOX) + #define HTCFG_SPI0_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MOSI_GPIOX) + #define HTCFG_SPI0_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MOSI_GPION) + +#endif +#ifdef BSP_USING_SPI1 + + #define HTCFG_SPI1_IPN SPI1 + + #define _HTCFG_SPI1_SCK_GPIOX B + #define _HTCFG_SPI1_SCK_GPION 7 + + #define _HTCFG_SPI1_MISO_GPIOX B + #define _HTCFG_SPI1_MISO_GPION 9 + + #define _HTCFG_SPI1_MOSI_GPIOX B + #define _HTCFG_SPI1_MOSI_GPION 8 + + #define HTCFG_SPI1_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_SCK_GPIOX) + #define HTCFG_SPI1_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_SCK_GPIOX) + #define HTCFG_SPI1_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_SCK_GPION) + + #define HTCFG_SPI1_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MISO_GPIOX) + #define HTCFG_SPI1_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MISO_GPIOX) + #define HTCFG_SPI1_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MISO_GPION) + + #define HTCFG_SPI1_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MOSI_GPIOX) + #define HTCFG_SPI1_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MOSI_GPIOX) + #define HTCFG_SPI1_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MOSI_GPION) + +#endif +#endif + +/* I2C gpio */ +#ifdef BSP_USING_I2C +#ifdef BSP_USING_I2C0 + + #define HTCFG_I2C0_IPN I2C0 + + #define _HTCFG_I2C0_SCL_GPIOX B + #define _HTCFG_I2C0_SCL_GPION 12 + + #define _HTCFG_I2C0_SDA_GPIOX B + #define _HTCFG_I2C0_SDA_GPION 13 + + #define HTCFG_I2C0_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SCL_GPIOX) + #define HTCFG_I2C0_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SCL_GPIOX) + #define HTCFG_I2C0_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SCL_GPION) + + #define HTCFG_I2C0_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SDA_GPIOX) + #define HTCFG_I2C0_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SDA_GPIOX) + #define HTCFG_I2C0_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SDA_GPION) + +#endif +#ifdef BSP_USING_I2C1 + + #define HTCFG_I2C1_IPN I2C1 + + #define _HTCFG_I2C1_SCL_GPIOX A + #define _HTCFG_I2C1_SCL_GPION 0 + + #define _HTCFG_I2C1_SDA_GPIOX A + #define _HTCFG_I2C1_SDA_GPION 1 + + #define HTCFG_I2C1_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SCL_GPIOX) + #define HTCFG_I2C1_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SCL_GPIOX) + #define HTCFG_I2C1_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SCL_GPION) + + #define HTCFG_I2C1_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SDA_GPIOX) + #define HTCFG_I2C1_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SDA_GPIOX) + #define HTCFG_I2C1_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SDA_GPION) + +#endif +#endif + +void ht32_usart_gpio_init(void *instance); +void ht32_spi_gpio_init(void *instance); +void ht32_i2c_gpio_init(void *instance); + +#ifdef __cplusplus +} +#endif + +#endif /* __HT32_MSP_H__ */ diff --git a/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_01_usbdconf.h b/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_01_usbdconf.h new file mode 100644 index 00000000000..432b323d7a4 --- /dev/null +++ b/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_01_usbdconf.h @@ -0,0 +1,453 @@ +/*********************************************************************************************************//** + * @file IP/Example/ht32f1xxxx_01_usbdconf.h + * @version $Rev:: 1090 $ + * @date $Date:: 2018-01-29 #$ + * @brief The configuration file of USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_01_USBDCONF_H +#define __HT32F1XXXX_01_USBDCONF_H + +// Enter Low Power mode when Suspended +#define USBDCORE_ENABLE_LOW_POWER (0) +// + +#if (USBDCORE_ENABLE_LOW_POWER == 1) + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#else + #define USBDCore_LowPower(...) +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Interrupt Enable */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Interrupt Setting (UIER) +// USB Global Interrupt Enable (UGIE) (Default) +// Start Of Frame Interrupt Enable (SOFIE) +// USB Reset Interrupt Enable (URSTIE) (Default) +// Resume Interrupt Enable (RSMIE) (Default) +// Suspend Interrupt Enable (SUSPIE) (Default) +// Expected Start of Frame Interrupt Enable (ESOFE) +// Control Endpoint Interrupt Enable (EP0IE) (Default) +// Endpoint1 Interrupt Enable (EP1IE) +// Endpoint2 Interrupt Enable (EP2IE) +// Endpoint3 Interrupt Enable (EP3IE) +// Endpoint4 Interrupt Enable (EP4IE) +// Endpoint5 Interrupt Enable (EP5IE) +// Endpoint6 Interrupt Enable (EP6IE) +// Endpoint7 Interrupt Enable (EP7IE) +#define _UIER (0x011D) +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Control Endpoint0 Configuration +// Endpoint Buffer Length (EPLEN) +// <8=> 8 bytes +// <16=> 16 bytes +// <32=> 32 bytes +// <64=> 64 bytes + /* Maximum: 64 Bytes */ +#define _EP0LEN (64) + + +// Control Endpoint0 Interrupt Enable Settings (EP0IER) +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) (Default) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +// SETUP Token Packet Received Interrupt Enable (STRXIE) +// SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default) +// SETUP Data Error Interrupt Enable (SDERIE) +// Zero Length Data Packet Received Interrupt Enable (ZLRXIE) +#define _EP0_IER (0x212) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint1 Configuration +#define _EP1_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP1_CFG_EPADR (1) + +// Endpoint Enable (EPEN) +#define _EP1_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP1_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP1_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP1LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP1_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint2 Configuration +#define _EP2_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP2_CFG_EPADR (2) + +// Endpoint Enable (EPEN) +#define _EP2_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP2_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP2_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP2LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP2_IER (0x002) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint3 Configuration +#define _EP3_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP3_CFG_EPADR (3) + +// Endpoint Enable (EPEN) +#define _EP3_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP3_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP3_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP3LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP3_IER (0x10) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint4 Configuration +#define _EP4_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP4_CFG_EPADR (4) + +// Endpoint Enable (EPEN) +#define _EP4_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP4_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP4_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP4LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP4_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP4_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint5 Configuration +#define _EP5_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP5_CFG_EPADR (5) + +// Endpoint Enable (EPEN) +#define _EP5_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP5_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP5_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP5LEN_TMP (8) + + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP5_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP5_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint6 Configuration +#define _EP6_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP6_CFG_EPADR (6) + +// Endpoint Enable (EPEN) +#define _EP6_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP6_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP6_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP6LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP6_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP6_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint7 Configuration +#define _EP7_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP7_CFG_EPADR (7) + +// Endpoint Enable (EPEN) +#define _EP7_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP7_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP7_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP7LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP7_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP7_IER (0x10) +// +// + +#endif diff --git a/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_conf.h b/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_conf.h new file mode 100644 index 00000000000..1128790b115 --- /dev/null +++ b/bsp/ht32/ht32f12366/board/inc/ht32f1xxxx_conf.h @@ -0,0 +1,490 @@ +/*********************************************************************************************************//** + * @file IP/Example/ht32f1xxxx_conf.h + * @version $Rev:: 2922 $ + * @date $Date:: 2023-06-07 #$ + * @brief Library configuration file. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_CONF_H +#define __HT32F1XXXX_CONF_H + +/* Exported constants --------------------------------------------------------------------------------------*/ + +#define RETARGET_ITM 0 +#define RETARGET_USB 1 +#define RETARGET_SYSLOG 2 +#define RETARGET_COM1 10 +#define RETARGET_COM2 11 +#define RETARGET_USART0 12 +#define RETARGET_USART1 13 +#define RETARGET_UART0 14 +#define RETARGET_UART1 15 + + +/* Retarget settings of the C standard I/O library functions (printf, scanf, getchar, ...etc.) */ +/* +// Enable Retarget +// Retarget Port +// <0=> ITM +// <1=> USB Virtual COM +// <2=> Syslog +// <10=> COM1 +// <11=> COM2 +// <12=> USART0 +// <13=> USART1 +// <14=> UART0 +// <15=> UART1 +// Enable Auto Return +// Auto Return function adds "\r" before "\n" automatically when print message by Retarget. +*/ +#define _RETARGET 1 +#define RETARGET_PORT 10 +#define _AUTO_RETURN 0 + +#ifndef AUTO_RETURN +#if (_AUTO_RETURN == 1) +#define AUTO_RETURN +#endif +#endif + +/* Enable Interrupt Mode for UxART Retarget +// Retarget COM/UxART Setting +// UxART Baudrate +// Enable Interrupt Mode for UxART Tx Retarget +// Define UxARTn_IRQHandler By Retarget (ht32_serial.c) +// Disable (RETARGET_DEFINE_HANDLER = 0) if application already have UxARTn_IRQHandler. +// RETARGET_UART_IRQHandler() shall be called by UxARTn_IRQHandler when disable. +// Tx Buffer Length (in byte) +// +*/ +#define RETARGET_UxART_BAUDRATE 115200 +#define RETARGET_INT_MODE 0 +#define RETARGET_DEFINE_HANDLER 1 +#define RETARGET_INT_BUFFER_SIZE 64 + +#if (_RETARGET == 1) +#if (RETARGET_PORT == RETARGET_ITM) +#elif (RETARGET_PORT == RETARGET_USB) + #define RETARGET_IS_USB +// Retarget USB Virtual COM Setting +// Communication (Interrupt IN) +// <1=> Endpoint 1 +// <2=> Endpoint 2 +// <3=> Endpoint 3 +// <4=> Endpoint 4 +// <5=> Endpoint 5 +// <6=> Endpoint 6 +// <7=> Endpoint 7 +// Data Rx (Bulk OUT) +// <1=> Endpoint 1 +// <2=> Endpoint 2 +// <3=> Endpoint 3 +// <4=> Endpoint 4 +// <5=> Endpoint 5 +// <6=> Endpoint 6 +// <7=> Endpoint 7 +// Data Tx (Bulk IN) +// <1=> Endpoint 1 +// <2=> Endpoint 2 +// <3=> Endpoint 3 +// <4=> Endpoint 4 +// <5=> Endpoint 5 +// <6=> Endpoint 6 +// <7=> Endpoint 7 +// Communication Endpoint Buffer Length (in byte) <4-64:4> +// Data Rx Endpoint Buffer Length (in byte) <4-64:4> +// Data Tx Endpoint Buffer Length (in byte) <4-64:4> +// Rx Buffer Length (in byte) <64-1024:4> +// Tx Buffer Length (in byte) <1-63:1> +// Please use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1. +// USB Tx Mode (BULK IN) +// <0=> Block Mode (Wait until both USB and terminal software are ready) +// <1=> Non-Block Mode (Drop data if USB or terminal software is not ready) +// Enable HSI Auto Trim By USB Function +// Need turn on if the USB clock source is from HSI (PLL USBPLL clock Source). + #define RETARGET_CTRL_EPT (5) + #define RETARGET_RX_EPT (6) + #define RETARGET_TX_EPT (7) + #define RETARGET_CTRL_EPTLEN (8) + #define RETARGET_RX_EPTLEN (64) + #define RETARGET_TX_EPTLEN (64) + #define RETARGET_BUFFER_SIZE (64) + #define RETARGET_TXBUFFER_SIZE (1) // Use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1. + #define RETARGET_USB_MODE (0) + #define RETARGET_HSI_ATM (1) +// +#elif (RETARGET_PORT == RETARGET_COM1) + #define RETARGET_COM_PORT COM1 + #define RETARGET_USART_PORT COM1_PORT + #define RETARGET_UART_IRQn COM1_IRQn + #define RETARGET_UART_IRQHandler COM1_IRQHandler + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_COM2) + #define RETARGET_COM_PORT COM2 + #define RETARGET_USART_PORT COM2_PORT + #define RETARGET_UART_IRQn COM2_IRQn + #define RETARGET_UART_IRQHandler COM2_IRQHandler + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_USART0) + #define RETARGET_UxART_IPN USART0 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_USART1) + #define RETARGET_UxART_IPN USART1 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART0) + #define RETARGET_UxART_IPN UART0 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART1) + #define RETARGET_UxART_IPN UART1 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#endif + extern void RETARGET_Configuration(void); +#else + #define RETARGET_Configuration(...) + #undef printf + #undef getchar + #define printf(...) + #define getchar() (0) +#endif + +#if (RETARGET_DEFINE_HANDLER == 0) +#undef RETARGET_UART_IRQHandler +#endif + +/* +// Enable HT32 Time Function +// Provide "Time_GetTick()" and "Time_Dealy()" functions. + +// Timer Selection +// <0=> BFTM0 +// <1=> BFTM1 +// <2=> SCTM0 +// <3=> SCTM1 +// <4=> SCTM2 +// <5=> SCTM3 +// <6=> PWM0 +// <7=> PWM1 +// <8=> PWM2 +// <9=> GPTM0 +// <10=> GPTM1 +// <11=> MCTM0 + +// Timer Clock Setting +// +// Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler) +// HTCFG_TIME_CLKSRC = _HTCFG_TIME_CORECLK / (2^HTCFG_TIME_PCLK_DIV) +// _HTCFG_TIME_CORECLK = LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL) + +// -- Core Clock Setting (CK_AHB) +// HTCFG_TIME_CLKSEL +// 0 = Default Maximum (LIBCFG_MAX_SPEED) +// 1 = Manual Input (HTCFG_TIME_CLK_MANUAL) +// <0=> Default Maximum (LIBCFG_MAX_SPEED) +// <1=> Manual Input (HTCFG_TIME_CLK_MANUAL) + +// -- Core Clock Manual Input (Hz) +// HTCFG_TIME_CLK_MANUAL +// Only meaningful when Core Clock Setting (HTCFG_TIME_CLKSEL) = Manual Input (1) + +// -- APB Peripheral Clock Prescaler +// HTCFG_TIME_PCLK_DIV +// <0=> /1 +// <1=> /2 +// <2=> /4 +// <3=> /8 + +// Time Tick (Hz, not applicable for BFTM) <1-1000000:100> +// Not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM. +*/ +#if (0) // Enable HT32 Time Function +#define HTCFG_TIME_IPSEL (0) +#define HTCFG_TIME_CLKSEL (0) // 0 = Default Maximum (LIBCFG_MAX_SPEED), 1 = Manual Input (HTCFG_TIME_CLKSRC) +#define HTCFG_TIME_CLK_MANUAL (20000000) // Only meaningful when HTCFG_TIME_CLKSEL = 1 (Manual Input) +#define HTCFG_TIME_PCLK_DIV (0) // 0 ~ 3. (/1, /2, /4, /8) +#define HTCFG_TIME_TICKHZ (1000) // Hz, not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM +#define HTCFG_TIME_MULTIPLE (1) // MUST be 1, 2, 4, 8. TICK = COUNT / MULTIPLE. Not applicable for BFTM. +/* + + Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler) + HTCFG_TIME_CLKSRC = (_HTCFG_TIME_CORECLK) / (2^HTCFG_TIME_PCLK_DIV) + where _HTCFG_TIME_CORECLK can be LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL) + + Tick Range: 0 ~ 2^32 / HTCFG_TIME_TICKHZ (maximum tick time) + Interrupt Time: _HTCFG_TIME_OVERFLOW_VALUE / (HTCFG_TIME_TICKHZ * HTCFG_TIME_MULTIPLE) Second + (Interrupt Time is not applicable for BFTM) + + Example: 32-bit BFTM with 48 MHz Timer Clock + HTCFG_TIME_TICKHZ = HTCFG_TIME_CLKSRC = 48000000 + Tick Range: 0 ~ 2^32 / 48000000 = 0 ~ 89.478485 Second (maximum tick time, return to 0 every 89.478485 Second) + BFTM do not use interrupt + + Example: 16-bit GPTM with 1 ms tick + HTCFG_TIME_TICKHZ = 1000 (Hz) + HTCFG_TIME_MULTIPLE = 1 (1 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 1000 = 0 ~ 4294967 Second = 0 ~ 49.7 Day (maximum tick time, return to 0 every 49.7 Day) + Interrupt Time: 65536 / (1000 * 1) = 65.536 Second (Trigger interrupt every 65.536 Second) +*/ +#endif +/* +// +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f1xxxx_conf.h" file (this file). +*/ +/* +// Enable User Define HSE Value +// Enable user define HSE value to overwrite default "HSE_VALUE" define in "ht32fxxxxx_nn.h". +// HSE Value (Hz) +*/ +#if (0) +#define HSE_VALUE 16000000 +#endif +/* +// +*/ + +/* +// Enable CKOUT Function +*/ +#define ENABLE_CKOUT 0 + + +/* The DEBUG definition to enter debug mode for library */ +/* +// Library Debug Mode +*/ +#define HT32_LIB_DEBUG 0 + + +/* Enable/disable the specific peripheral inclusion */ + +// Library Inclusion Configuration +/* ADC -----------------------------------------------------------------------------------------------------*/ +/* +// ADC Library +*/ +#define _ADC 1 + +/* AES -----------------------------------------------------------------------------------------------------*/ +/* +// AES Library +*/ +#define _AES 1 + +/* BFTM ----------------------------------------------------------------------------------------------------*/ +/* +// BFTM Library +*/ +#define _BFTM 1 + +/* Clock Control -------------------------------------------------------------------------------------------*/ +/* +// Clock Control Library +*/ +#define _CKCU 1 + +/* Comparator/OPA ------------------------------------------------------------------------------------------*/ +/* +// Comparator/OPA Library +*/ +#define _CMP_OPA 1 + +/* Comparator ----------------------------------------------------------------------------------------------*/ +/* +// Comparator Library +*/ +#define _CMP 1 + +/* CRC -----------------------------------------------------------------------------------------------------*/ +/* +// CRC Library +*/ +#define _CRC 1 + +/* CSIF ----------------------------------------------------------------------------------------------------*/ +/* +// CSIF Library +*/ +#define _CSIF 1 + +/* EBI -----------------------------------------------------------------------------------------------------*/ +/* +// EBI Library +*/ +#define _EBI 1 + +/* EXTI ----------------------------------------------------------------------------------------------------*/ +/* +// EXTI Library +*/ +#define _EXTI 1 + +/* Flash ---------------------------------------------------------------------------------------------------*/ +/* +// Flash Library +*/ +#define _FLASH 1 + +/* GPIO ----------------------------------------------------------------------------------------------------*/ +/* +// GPIO Library +*/ +#define _GPIO 1 + +/* GPTM ----------------------------------------------------------------------------------------------------*/ +/* +// GPTM Library +*/ +#define _GPTM 1 + +/* I2C -----------------------------------------------------------------------------------------------------*/ +/* +// I2C Library +*/ +#define _I2C 1 + +/* I2S -----------------------------------------------------------------------------------------------------*/ +/* +// I2S Library +*/ +#define _I2S 1 + +/* MCTM ----------------------------------------------------------------------------------------------------*/ +/* +// MCTM Library +*/ +#define _MCTM 1 + +/* PDMA ----------------------------------------------------------------------------------------------------*/ +/* +// PDMA Library +*/ +#define _PDMA 1 + +/* PWM -----------------------------------------------------------------------------------------------------*/ +/* +// PWM Library +*/ +#define _PWM 1 + +/* PWRCU ---------------------------------------------------------------------------------------------------*/ +/* +// PWRCU Library +*/ +#define _PWRCU 1 + +/* RSTCU ---------------------------------------------------------------------------------------------------*/ +/* +// RSTCU Library +*/ +#define _RSTCU 1 + +/* RTC -----------------------------------------------------------------------------------------------------*/ +/* +// RTC Library +*/ +#define _RTC 1 + +/* SCI -----------------------------------------------------------------------------------------------------*/ +/* +// SCI Library +*/ +#define _SCI 1 + +/* SCTM ----------------------------------------------------------------------------------------------------*/ +/* +// SCTM Library +*/ +#define _SCTM 1 + +/* SDIO ----------------------------------------------------------------------------------------------------*/ +/* +// SDIO Library +*/ +#define _SDIO 1 + +/* SPI -----------------------------------------------------------------------------------------------------*/ +/* +// SPI Library +*/ +#define _SPI 1 + +/* USART ---------------------------------------------------------------------------------------------------*/ +/* +// USART/UART Library +*/ +#define _USART 1 + +/* USBD ----------------------------------------------------------------------------------------------------*/ +/* +// USB Library +*/ +#define _USB 1 + +/* WDT -----------------------------------------------------------------------------------------------------*/ +/* +// WDT Library +*/ +#define _WDT 1 + +/* Misc ----------------------------------------------------------------------------------------------------*/ +/* +// Misc Library +*/ +#define _MISC 1 + +/* Serial --------------------------------------------------------------------------------------------------*/ +/* +// Serial Library +*/ +#define _SERIAL 1 + +/* Software Random Number ----------------------------------------------------------------------------------*/ +/* +// Software Random Number Library +*/ +#define _SWRAND 1 + + +// + +#endif diff --git a/bsp/ht32/ht32f12366/board/linker_scripts/link.icf b/bsp/ht32/ht32f12366/board/linker_scripts/link.icf new file mode 100644 index 00000000000..65c2bfc8b7c --- /dev/null +++ b/bsp/ht32/ht32f12366/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file diff --git a/bsp/ht32/ht32f12366/board/linker_scripts/link.lds b/bsp/ht32/ht32f12366/board/linker_scripts/link.lds new file mode 100644 index 00000000000..27269dd77ea --- /dev/null +++ b/bsp/ht32/ht32f12366/board/linker_scripts/link.lds @@ -0,0 +1,156 @@ +/* + * linker script for AT32 with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 96K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/ht32/ht32f12366/board/linker_scripts/link.sct b/bsp/ht32/ht32f12366/board/linker_scripts/link.sct new file mode 100644 index 00000000000..16cced4f77f --- /dev/null +++ b/bsp/ht32/ht32f12366/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x0003FC00 { ; load region size_region + ER_IROM1 0x00000000 0x0003FC00 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/ht32/ht32f12366/board/src/board.c b/bsp/ht32/ht32f12366/board/src/board.c new file mode 100644 index 00000000000..e0160468e94 --- /dev/null +++ b/bsp/ht32/ht32f12366/board/src/board.c @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "board.h" + +/* This feature will initialize the HT32 chip clock */ +void rt_hw_board_clock_init(void) +{ + +} diff --git a/bsp/ht32/ht32f12366/board/src/ht32_msp.c b/bsp/ht32/ht32f12366/board/src/ht32_msp.c new file mode 100644 index 00000000000..4ef7b61b543 --- /dev/null +++ b/bsp/ht32/ht32f12366/board/src/ht32_msp.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "ht32_msp.h" + +/* GPIO configuration for UART */ +#ifdef BSP_USING_UART +void ht32_usart_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_USART_TypeDef *usart_x = (HT_USART_TypeDef *)instance; +#ifdef BSP_USING_USART0 + if(HT_USART0 == usart_x) + { + CKCUClock.Bit.HTCFG_USART0_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_USART0_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_USART0_RX_GPIO_PORT,HTCFG_USART0_RX_GPIO_PIN,GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_USART0_TX_GPIO_ID,HTCFG_USART0_TX_GPIO_PIN,AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_USART0_RX_GPIO_ID,HTCFG_USART0_RX_GPIO_PIN,AFIO_FUN_USART_UART); + } +#endif +#ifdef BSP_USING_USART1 + if(HT_USART1 == usart_x) + { + CKCUClock.Bit.HTCFG_USART1_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_USART1_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_USART1_RX_GPIO_PORT,HTCFG_USART1_RX_GPIO_PIN,GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_USART1_TX_GPIO_ID,HTCFG_USART1_TX_GPIO_PIN,AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_USART1_RX_GPIO_ID,HTCFG_USART1_RX_GPIO_PIN,AFIO_FUN_USART_UART); + } +#endif +#ifdef BSP_USING_UART0 + if(HT_UART0 == usart_x) + { + CKCUClock.Bit.HTCFG_UART0_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_UART0_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_UART0_RX_GPIO_PORT,HTCFG_UART0_RX_GPIO_PIN,GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_UART0_TX_GPIO_ID,HTCFG_UART0_TX_GPIO_PIN,AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_UART0_RX_GPIO_ID,HTCFG_UART0_RX_GPIO_PIN,AFIO_FUN_USART_UART); + } +#endif +#ifdef BSP_USING_UART1 + if(HT_UART1 == usart_x) + { + CKCUClock.Bit.HTCFG_UART1_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_UART1_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_UART1_RX_GPIO_PORT,HTCFG_UART1_RX_GPIO_PIN,GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_UART1_TX_GPIO_ID,HTCFG_UART1_TX_GPIO_PIN,AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_UART1_RX_GPIO_ID,HTCFG_UART1_RX_GPIO_PIN,AFIO_FUN_USART_UART); + } +#endif +} +#endif + +/* GPIO configuration for SPI */ +#ifdef BSP_USING_SPI +void ht32_spi_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_SPI_TypeDef *spi_x = (HT_SPI_TypeDef *)instance; +#ifdef BSP_USING_SPI0 + if(HT_SPI0 == spi_x) + { + CKCUClock.Bit.HTCFG_SPI0_SCK_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI0_MISO_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI0_MOSI_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + + AFIO_GPxConfig(HTCFG_SPI0_SCK_GPIO_ID, HTCFG_SPI0_SCK_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI0_MISO_GPIO_ID, HTCFG_SPI0_MISO_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI0_MOSI_GPIO_ID, HTCFG_SPI0_MOSI_GPIO_PIN, AFIO_FUN_SPI); + } +#endif +#ifdef BSP_USING_SPI1 + if(HT_SPI1 == spi_x) + { + CKCUClock.Bit.HTCFG_SPI1_SCK_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI1_MISO_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI1_MOSI_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + + AFIO_GPxConfig(HTCFG_SPI1_SCK_GPIO_ID, HTCFG_SPI1_SCK_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI1_MISO_GPIO_ID, HTCFG_SPI1_MISO_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI1_MOSI_GPIO_ID, HTCFG_SPI1_MOSI_GPIO_PIN, AFIO_FUN_SPI); + } +#endif +} +#endif + +/* GPIO configuration for I2C */ +#ifdef BSP_USING_I2C +void ht32_i2c_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_I2C_TypeDef *i2c_x = (HT_I2C_TypeDef *)instance; +#ifdef BSP_USING_I2C0 + if(HT_I2C0 == i2c_x) + { + CKCUClock.Bit.HTCFG_I2C0_SCL_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_I2C0_SDA_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + /* Configure GPIO to I2C mode */ + AFIO_GPxConfig(HTCFG_I2C0_SCL_GPIO_ID,HTCFG_I2C0_SCL_GPIO_PIN,AFIO_FUN_I2C); + AFIO_GPxConfig(HTCFG_I2C0_SDA_GPIO_ID,HTCFG_I2C0_SDA_GPIO_PIN,AFIO_FUN_I2C); + } +#endif +#ifdef BSP_USING_I2C1 + if(HT_I2C1 == i2c_x) + { + CKCUClock.Bit.HTCFG_I2C1_SCL_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_I2C1_SDA_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock,ENABLE); + /* Configure GPIO to I2C mode */ + AFIO_GPxConfig(HTCFG_I2C1_SCL_GPIO_ID,HTCFG_I2C1_SCL_GPIO_PIN,AFIO_FUN_I2C); + AFIO_GPxConfig(HTCFG_I2C1_SDA_GPIO_ID,HTCFG_I2C1_SDA_GPIO_PIN,AFIO_FUN_I2C); + } +#endif +} +#endif diff --git a/bsp/ht32/ht32f12366/figures/board.png b/bsp/ht32/ht32f12366/figures/board.png new file mode 100644 index 00000000000..850221d1afa Binary files /dev/null and b/bsp/ht32/ht32f12366/figures/board.png differ diff --git a/bsp/ht32/ht32f12366/project.uvoptx b/bsp/ht32/ht32f12366/project.uvoptx new file mode 100644 index 00000000000..4c6655f9dd9 --- /dev/null +++ b/bsp/ht32/ht32f12366/project.uvoptx @@ -0,0 +1,179 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 2 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0HT32F.FLM -FS00 -FL0100000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FF1HT32F_OPT.FLM -FS11FF00000 -FL11000 -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM)) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/ht32/ht32f12366/project.uvprojx b/bsp/ht32/ht32f12366/project.uvprojx new file mode 100644 index 00000000000..733d03c6803 --- /dev/null +++ b/bsp/ht32/ht32f12366/project.uvprojx @@ -0,0 +1,1366 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC + + + HT32F12366 + Holtek + Holtek.HT32_DFP.1.0.19 + http://mcu.holtek.com.tw/pack + IRAM(0x20000000,0x20000) IROM(0x00000000,0x3FC00) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM)) + 0 + $$Device:HT32F12366$ARM\INC\Holtek\HT32F1xxxx\ht32f1xxxx_01.h + + + + + + + + + + $$Device:HT32F12366$SVD\HT32F12365_66.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x3fc00 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x3fc00 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, USE_HT32F12366_SK, USE_HT32F12365_66, USE_MEM_HT32F12366, __CLK_TCK=RT_TICK_PER_SECOND, USE_HT32_DRIVER, __RTTHREAD__ + + ..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\ht32_drivers;..\libraries\HT32_STD_1xxxx_FWLib\library\Device\Holtek\HT32F1xxxx\Include;applications;..\..\..\libcpu\arm\cortex-m3;..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\inc;.;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\drivers\include;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;board\inc;..\..\..\components\libc\posix\io\epoll;..\..\..\components\libc\posix\ipc;..\libraries\HT32_STD_1xxxx_FWLib\library\CMSIS\Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_HT32_CHIP=2 + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + + + cunistd.c + 1 + ..\..\..\components\libc\compilers\common\cunistd.c + + + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + + + DeviceDrivers + + + device.c + 1 + ..\..\..\components\drivers\core\device.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + i2c-bit-ops.c + 1 + ..\..\..\components\drivers\i2c\i2c-bit-ops.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + i2c_core.c + 1 + ..\..\..\components\drivers\i2c\i2c_core.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + i2c_dev.c + 1 + ..\..\..\components\drivers\i2c\i2c_dev.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + completion.c + 1 + ..\..\..\components\drivers\ipc\completion.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\ipc\dataqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + pipe.c + 1 + ..\..\..\components\drivers\ipc\pipe.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\ipc\ringblk_buf.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\ipc\ringbuffer.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + pin.c + 1 + ..\..\..\components\drivers\pin\pin.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + spi_core.c + 1 + ..\..\..\components\drivers\spi\spi_core.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + spi_dev.c + 1 + ..\..\..\components\drivers\spi\spi_dev.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + Drivers + + + board.c + 1 + board\src\board.c + + + + + ht32_msp.c + 1 + board\src\ht32_msp.c + + + + + startup_ht32f1xxxx_01.s + 2 + ..\libraries\HT32_STD_1xxxx_FWLib\library\Device\Holtek\HT32F1xxxx\Source\ARM\startup_ht32f1xxxx_01.s + + + + + drv_common.c + 1 + ..\libraries\ht32_drivers\drv_common.c + + + + + drv_gpio.c + 1 + ..\libraries\ht32_drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\ht32_drivers\drv_usart.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + memheap.c + 1 + ..\..\..\src\memheap.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_comm.c + 1 + ..\..\..\src\scheduler_comm.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_up.c + 1 + ..\..\..\src\scheduler_up.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + libcpu + + + atomic_arm.c + 1 + ..\..\..\libcpu\arm\common\atomic_arm.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m3\context_rvds.S + + + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m3\cpuport.c + + + + + Libraries + + + ht32f1xxxx_wdt.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_wdt.c + + + + + ht32f1xxxx_sci.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_sci.c + + + + + ht32f1xxxx_rstcu.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_rstcu.c + + + + + ht32f1xxxx_usbd.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_usbd.c + + + + + ht32f1xxxx_tm.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_tm.c + + + + + ht32f1xxxx_ckcu.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_ckcu.c + + + + + ht32f1xxxx_usart.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_usart.c + + + + + ht32f1xxxx_aes.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_aes.c + + + + + ht32f1xxxx_flash.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_flash.c + + + + + ht32f1xxxx_gpio.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_gpio.c + + + + + ht32_cm3_misc.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32_cm3_misc.c + + + + + ht32f1xxxx_crc.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_crc.c + + + + + ht32f1xxxx_sdio.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_sdio.c + + + + + ht32f1xxxx_ebi.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_ebi.c + + + + + ht32f1xxxx_cmp.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_cmp.c + + + + + ht32f1xxxx_i2c.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_i2c.c + + + + + ht32f1xxxx_adc.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_adc.c + + + + + ht32f1xxxx_pwrcu.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_pwrcu.c + + + + + ht32f1xxxx_pdma.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_pdma.c + + + + + system_ht32f1xxxx_02.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\Device\Holtek\HT32F1xxxx\Source\system_ht32f1xxxx_02.c + + + + + ht32f1xxxx_mctm.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_mctm.c + + + + + ht32f1xxxx_spi.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_spi.c + + + + + ht32f1xxxx_bftm.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_bftm.c + + + + + ht32f1xxxx_i2s.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_i2s.c + + + + + ht32f1xxxx_exti.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_exti.c + + + + + ht32f1xxxx_rtc.c + 1 + ..\libraries\HT32_STD_1xxxx_FWLib\library\HT32F1xxxx_Driver\src\ht32f1xxxx_rtc.c + + + + + + + + + + + + diff --git a/bsp/ht32/ht32f12366/rtconfig.h b/bsp/ht32/ht32f12366/rtconfig.h new file mode 100644 index 00000000000..42fd7c23e09 --- /dev/null +++ b/bsp/ht32/ht32f12366/rtconfig.h @@ -0,0 +1,273 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "usart0" +#define RT_VER_NUM 0x50100 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M3 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_SPI +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Memory protection */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* BL808 WiFi */ + + +/* CYW43439 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + + +/* Kendryte SDK */ + + +/* sensors drivers */ + + +/* touch drivers */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +#define SOC_FAMILY_HT32 +#define SOC_SERIES_HT32F1 + +/* Hardware Drivers Config */ + +#define SOC_HT32F12366 + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_USART0 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/ht32/ht32f12366/rtconfig.py b/bsp/ht32/ht32f12366/rtconfig.py new file mode 100644 index 00000000000..1c3077b6cf4 --- /dev/null +++ b/bsp/ht32/ht32f12366/rtconfig.py @@ -0,0 +1,152 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m3' +CROSS_TOOL='keil' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' +# EXEC_PATH = r'D:\keil5\keil_v532\UV4' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M3 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M3' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M3' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + diff --git a/bsp/ht32/ht32f12366/template.uvoptx b/bsp/ht32/ht32f12366/template.uvoptx new file mode 100644 index 00000000000..4c6655f9dd9 --- /dev/null +++ b/bsp/ht32/ht32f12366/template.uvoptx @@ -0,0 +1,179 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 2 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0HT32F.FLM -FS00 -FL0100000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FF1HT32F_OPT.FLM -FS11FF00000 -FL11000 -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM)) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/ht32/ht32f12366/template.uvprojx b/bsp/ht32/ht32f12366/template.uvprojx new file mode 100644 index 00000000000..9b24487b535 --- /dev/null +++ b/bsp/ht32/ht32f12366/template.uvprojx @@ -0,0 +1,392 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC + + + HT32F12366 + Holtek + Holtek.HT32_DFP.1.0.19 + http://mcu.holtek.com.tw/pack + IRAM(0x20000000,0x20000) IROM(0x00000000,0x3FC00) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F12366$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F12366$ARM\Flash\HT32F_OPT.FLM)) + 0 + $$Device:HT32F12366$ARM\INC\Holtek\HT32F1xxxx\ht32f1xxxx_01.h + + + + + + + + + + $$Device:HT32F12366$SVD\HT32F12365_66.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x3fc00 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x3fc00 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_HT32_CHIP=2 + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + diff --git a/bsp/ht32/ht32f52352/.config b/bsp/ht32/ht32f52352/.config new file mode 100644 index 00000000000..b89bfb8deb1 --- /dev/null +++ b/bsp/ht32/ht32f52352/.config @@ -0,0 +1,1092 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" +CONFIG_RT_VER_NUM=0x50100 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# CONFIG_RT_USING_CACHE is not set +# CONFIG_RT_USING_HW_ATOMIC is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M0=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI_BITOPS is not set +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# +CONFIG_SOC_FAMILY_HT32=y +CONFIG_SOC_SERIES_HT32F5=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HT32F52352=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_USART0 is not set +CONFIG_BSP_USING_USART1=y +# CONFIG_BSP_USING_UART0 is not set +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C is not set + +# +# Board extended module Drivers +# diff --git a/bsp/ht32/ht32f52352/Kconfig b/bsp/ht32/ht32f52352/Kconfig new file mode 100644 index 00000000000..79b160b8567 --- /dev/null +++ b/bsp/ht32/ht32f52352/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/ht32/ht32f52352/README.md b/bsp/ht32/ht32f52352/README.md new file mode 100644 index 00000000000..10644a76a4a --- /dev/null +++ b/bsp/ht32/ht32f52352/README.md @@ -0,0 +1,108 @@ +# HT32F52352 BSP 说明 + +## 简介 + +ESK32-30501是合泰基于HT32F52352芯片并针对Cortex®-M0+入门而设计的评估板。本文档是为ESK32-30501开发板提供的BSP(板级支持包)说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +## 开发板介绍 + +ESK32-30501使用32位Arm® Cortex®-M0+高性能、低功耗单片机HT32F52352，针对Cortex®-M0+入门而设计。开发板外观如下图所示： + +![board.png](figures/board.png) + +该开发板常用 **板载资源** 如下： + +- MCU：HT32F52352，主频 48MHz，128KB FLASH ，16KB SRAM +- 常用外设 + - LED：2个，（绿色，PC14、PC15） +- 常用接口：USB 转串口 、USB SLAVE +- 调试接口：板载的 e-Link32 Lite SWD 下载 + +开发板更多详细信息请参考合泰官网的相关文档[ESK32-30501](https://www.holtek.com.cn/page/detail/dev_kit/ESK32-30501)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :--- | :---: | :--- | +| USB 转串口 | 支持 | 使用 USART1 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1...PD3 ---> PIN: 0, 1...51 | +| USART | 支持 | USART0/1 | +| UART | 支持 | UART0/1 | +| SPI | 支持 | SPI0/1 | +| I2C | 支持 | 硬件 I2C0/1 | +| ADC | 暂不支持 | | +| WDT | 暂不支持 | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多片上资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为仅为开发者提供MDK5的工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线通过板载的 e-Link32 Lite将芯片连接到 PC。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 注：工程默认配置使用CMSIS-DAP下载方式，在通过 e-Link32 Lite 连接开发板的基础上，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，LED1和LED2交替闪烁。 + +连接开发板对应串口到 PC（也可以通过e-Link32 Lite的模拟串口将开发板连接到PC）, 在终端工具里调整好串口配置（115200-8-1-N）并打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +> 注：由于RT-Thread的finsh控制台使用的是命令行的输入形式，推荐使用串口调试工具如：Tabby terminal 或者 Tera Term。 + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Apr 10 2024 14:39:43 + 2006 - 2024 Copyright by RT-Thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 USART1 的功能，如果需使用更多的片上资源，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`scons --target=mdk5` 命令重新生成工程。 + +## 注意事项 + +开发板和芯片的相关资料可以在[合泰官网](https://www.holtek.com.cn/page/index)进行查找和下载，如芯片的数据手册和开发使用手册、开发板的原理图、Keil_v5的pack安装包等。 + +## 联系人信息 + +维护人: + +- [QT-one](https://github.com/QT-one) \ No newline at end of file diff --git a/bsp/ht32/ht32f52352/SConscript b/bsp/ht32/ht32f52352/SConscript new file mode 100644 index 00000000000..682f94215ca --- /dev/null +++ b/bsp/ht32/ht32f52352/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os #包含os库 +Import('RTT_ROOT') #导入RTT_ROOT对象（RTT_ROOT代表的是RT-Thread源码包） +from building import * #把building模块的所有内容都导入到当前模块中 + +cwd = GetCurrentDir() #获取当前路径，并将该路径信息保存到变量cwd中 +objs = [] #创建一个list型变量objs +list = os.listdir(cwd) #得到当前目录下的所有子目录，并保存到变量list中 + +for d in list: #for循环用d记录循环的次数，直到寻遍所有路径 + path = os.path.join(cwd, d) #根据d获取到不同的路径 + if os.path.isfile(os.path.join(path, 'SConscript')): #如果该路径下存在名为SConscript的文件 + objs = objs + SConscript(os.path.join(d, 'SConscript')) #将路径中SConscript文件内的源码读取到objs中 + +Return('objs') #将objs返回出去 diff --git a/bsp/ht32/ht32f52352/SConstruct b/bsp/ht32/ht32f52352/SConstruct new file mode 100644 index 00000000000..9f16ec63d24 --- /dev/null +++ b/bsp/ht32/ht32f52352/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +ht32_library = 'HT32_STD_5xxxx_FWLib' +rtconfig.BSP_LIBRARY_TYPE = ht32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, ht32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ht32_drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/ht32/ht32f52352/applications/SConscript b/bsp/ht32/ht32f52352/applications/SConscript new file mode 100644 index 00000000000..9023be657ab --- /dev/null +++ b/bsp/ht32/ht32f52352/applications/SConscript @@ -0,0 +1,21 @@ +#导入其他模块的变量 +Import('RTT_ROOT') +Import('rtconfig') + +#导入使用到的模块 +from building import * + +#获取当前目录的路径 +cwd = GetCurrentDir() + +#创建一个列表，用于保存需要使用到的C文件路径 +src = Glob('*c') + +#创建一个列表，用于保存需要包含的H文件路径 +path = [cwd] + +#创建一个组别 +group = DefineGroup('Applications', src, depend = [''], CPPPATH = path) + +#返回创建好的组别 +Return('group') \ No newline at end of file diff --git a/bsp/ht32/ht32f52352/applications/main.c b/bsp/ht32/ht32f52352/applications/main.c new file mode 100644 index 00000000000..3bcf7a1215c --- /dev/null +++ b/bsp/ht32/ht32f52352/applications/main.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include +#include +#include "board.h" + +/* defined the led2 pin: pc14 */ +#define LED1_PIN GET_PIN(C, 14) +/* defined the led3 pin: pc15 */ +#define LED2_PIN GET_PIN(C, 15) + +int main(void) +{ + rt_uint32_t speed = 200; + /* set led1 pin mode to output */ + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + /* set led2 pin mode to output */ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED1_PIN, PIN_LOW); + rt_pin_write(LED2_PIN, PIN_HIGH); + rt_thread_mdelay(speed); + rt_pin_write(LED1_PIN, PIN_HIGH); + rt_pin_write(LED2_PIN, PIN_LOW); + rt_thread_mdelay(speed); + } +} diff --git a/bsp/ht32/ht32f52352/board/Kconfig b/bsp/ht32/ht32f52352/board/Kconfig new file mode 100644 index 00000000000..b12d8e56263 --- /dev/null +++ b/bsp/ht32/ht32f52352/board/Kconfig @@ -0,0 +1,77 @@ +menu "Hardware Drivers Config" + +config SOC_HT32F52352 + bool + select SOC_SERIES_HT32F5 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default n + +    menuconfig BSP_USING_UART + bool "Enable UART" + default n + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_USART0 + bool "Enable USART0" + default n + + config BSP_USING_USART1 + bool "Enable USART1" + default n + + config BSP_USING_UART0 + bool "Enable UART0" + default n + + config BSP_USING_UART1 + bool "Enable UART1" + default n +        endif + + menuconfig BSP_USING_SPI + bool "Enable SPI Bus" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0 Bus" + default n + + config BSP_USING_SPI1 + bool "Enable SPI1 Bus" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C Bus" + default n + select RT_USING_I2C + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0 Bus" + default n + + config BSP_USING_I2C1 + bool "Enable I2C1 Bus" + default n + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/ht32/ht32f52352/board/SConscript b/bsp/ht32/ht32f52352/board/SConscript new file mode 100644 index 00000000000..79eab7eced6 --- /dev/null +++ b/bsp/ht32/ht32f52352/board/SConscript @@ -0,0 +1,27 @@ + +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +src = Glob('src/*.c') + +startup_path_prefix = SDK_LIB +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_01.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s'] + +path = [cwd] +path = [cwd + '/inc'] + +CPPDEFINES = ['USE_HT32F52352_SK, USE_HT32F52342_52, USE_MEM_HT32F52352'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') \ No newline at end of file diff --git a/bsp/ht32/ht32f52352/board/inc/board.h b/bsp/ht32/ht32f52352/board/inc/board.h new file mode 100644 index 00000000000..91d5c2d0a53 --- /dev/null +++ b/bsp/ht32/ht32f52352/board/inc/board.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "ht32.h" +#include "ht32_msp.h" + +#ifdef BSP_USING_GPIO + #include "drv_gpio.h" +#endif + +#ifdef BSP_USING_UART + #include "drv_usart.h" +#endif + +#ifdef BSP_USING_SPI + #include "drv_spi.h" +#endif + +#ifdef BSP_USING_I2C + #include "drv_i2c.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* whether use board external SRAM memory */ +#define HT32_EXT_SRAM 0 +#define HT32_EXT_SRAM_BEGIN 0x68000000 +#define HT32_EXT_SRAM_END (HT32_EXT_SRAM_BEGIN + HT32_EXT_SRAM*1024) + +/* internal sram memory size */ +#define HT32_SRAM_END (0x20000000 + LIBCFG_RAM_SIZE) + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif +#define HEAP_END HT32_SRAM_END + +void rt_hw_board_clock_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/ht32/ht32f52352/board/inc/ht32_msp.h b/bsp/ht32/ht32f52352/board/inc/ht32_msp.h new file mode 100644 index 00000000000..066add8d568 --- /dev/null +++ b/bsp/ht32/ht32f52352/board/inc/ht32_msp.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __HT32_MSP_H__ +#define __HT32_MSP_H__ + +#include +#include "ht32.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* UART gpio */ +#ifdef BSP_USING_UART +#ifdef BSP_USING_USART0 +#define HTCFG_USART0_IPN USART0 + +#define _HTCFG_USART0_TX_GPIOX A +#define _HTCFG_USART0_TX_GPION 2 +#define _HTCFG_USART0_RX_GPIOX A +#define _HTCFG_USART0_RX_GPION 3 + +#define HTCFG_USART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_TX_GPIOX) +#define HTCFG_USART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_TX_GPIOX) +#define HTCFG_USART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_TX_GPIOX) +#define HTCFG_USART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_TX_GPION) + +#define HTCFG_USART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART0_RX_GPIOX) +#define HTCFG_USART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART0_RX_GPIOX) +#define HTCFG_USART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART0_RX_GPIOX) +#define HTCFG_USART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART0_RX_GPION) + +#endif +#ifdef BSP_USING_USART1 + +#define HTCFG_USART1_IPN USART1 + +#define _HTCFG_USART1_TX_GPIOX A +#define _HTCFG_USART1_TX_GPION 4 +#define _HTCFG_USART1_RX_GPIOX A +#define _HTCFG_USART1_RX_GPION 5 + +#define HTCFG_USART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_TX_GPIOX) +#define HTCFG_USART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_TX_GPIOX) +#define HTCFG_USART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_TX_GPIOX) +#define HTCFG_USART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_TX_GPION) + +#define HTCFG_USART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_USART1_RX_GPIOX) +#define HTCFG_USART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_USART1_RX_GPIOX) +#define HTCFG_USART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_USART1_RX_GPIOX) +#define HTCFG_USART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_USART1_RX_GPION) + +#endif +#ifdef BSP_USING_UART0 + +#define HTCFG_UART0_IPN UART0 + +#define _HTCFG_UART0_TX_GPIOX B +#define _HTCFG_UART0_TX_GPION 2 +#define _HTCFG_UART0_RX_GPIOX B +#define _HTCFG_UART0_RX_GPION 3 + +#define HTCFG_UART0_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_TX_GPIOX) +#define HTCFG_UART0_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_TX_GPIOX) +#define HTCFG_UART0_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_TX_GPIOX) +#define HTCFG_UART0_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_TX_GPION) + +#define HTCFG_UART0_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART0_RX_GPIOX) +#define HTCFG_UART0_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART0_RX_GPIOX) +#define HTCFG_UART0_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART0_RX_GPIOX) +#define HTCFG_UART0_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART0_RX_GPION) + +#endif +#ifdef BSP_USING_UART1 + +#define HTCFG_UART1_IPN UART1 + +#define _HTCFG_UART1_TX_GPIOX B +#define _HTCFG_UART1_TX_GPION 4 +#define _HTCFG_UART1_RX_GPIOX B +#define _HTCFG_UART1_RX_GPION 5 + +#define HTCFG_UART1_TX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_TX_GPIOX) +#define HTCFG_UART1_TX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_TX_GPIOX) +#define HTCFG_UART1_TX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_TX_GPIOX) +#define HTCFG_UART1_TX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_TX_GPION) + +#define HTCFG_UART1_RX_GPIO_ID STRCAT2(GPIO_P, _HTCFG_UART1_RX_GPIOX) +#define HTCFG_UART1_RX_GPIO_CLK STRCAT2(P, _HTCFG_UART1_RX_GPIOX) +#define HTCFG_UART1_RX_GPIO_PORT STRCAT2(HT_GPIO, _HTCFG_UART1_RX_GPIOX) +#define HTCFG_UART1_RX_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_UART1_RX_GPION) + +#endif +#endif + +/* SPI gpio */ +#ifdef BSP_USING_SPI +#ifdef BSP_USING_SPI0 + +#define HTCFG_SPI0_IPN SPI0 + +#define _HTCFG_SPI0_SCK_GPIOX C +#define _HTCFG_SPI0_SCK_GPION 0 + +#define _HTCFG_SPI0_MISO_GPIOX A +#define _HTCFG_SPI0_MISO_GPION 11 + +#define _HTCFG_SPI0_MOSI_GPIOX A +#define _HTCFG_SPI0_MOSI_GPION 9 + +#define HTCFG_SPI0_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_SCK_GPIOX) +#define HTCFG_SPI0_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_SCK_GPIOX) +#define HTCFG_SPI0_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_SCK_GPION) + +#define HTCFG_SPI0_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MISO_GPIOX) +#define HTCFG_SPI0_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MISO_GPIOX) +#define HTCFG_SPI0_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MISO_GPION) + +#define HTCFG_SPI0_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI0_MOSI_GPIOX) +#define HTCFG_SPI0_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI0_MOSI_GPIOX) +#define HTCFG_SPI0_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI0_MOSI_GPION) + +#endif +#ifdef BSP_USING_SPI1 + +#define HTCFG_SPI1_IPN SPI1 + +#define _HTCFG_SPI1_SCK_GPIOX A +#define _HTCFG_SPI1_SCK_GPION 15 + +#define _HTCFG_SPI1_MISO_GPIOX B +#define _HTCFG_SPI1_MISO_GPION 1 + +#define _HTCFG_SPI1_MOSI_GPIOX B +#define _HTCFG_SPI1_MOSI_GPION 0 + +#define HTCFG_SPI1_SCK_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_SCK_GPIOX) +#define HTCFG_SPI1_SCK_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_SCK_GPIOX) +#define HTCFG_SPI1_SCK_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_SCK_GPION) + +#define HTCFG_SPI1_MISO_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MISO_GPIOX) +#define HTCFG_SPI1_MISO_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MISO_GPIOX) +#define HTCFG_SPI1_MISO_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MISO_GPION) + +#define HTCFG_SPI1_MOSI_GPIO_CLK STRCAT2(P, _HTCFG_SPI1_MOSI_GPIOX) +#define HTCFG_SPI1_MOSI_GPIO_ID STRCAT2(GPIO_P, _HTCFG_SPI1_MOSI_GPIOX) +#define HTCFG_SPI1_MOSI_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_SPI1_MOSI_GPION) + +#endif +#endif + +/* I2C gpio */ +#ifdef BSP_USING_I2C +#ifdef BSP_USING_I2C0 + +#define HTCFG_I2C0_IPN I2C0 + +#define _HTCFG_I2C0_SCL_GPIOX C +#define _HTCFG_I2C0_SCL_GPION 12 + +#define _HTCFG_I2C0_SDA_GPIOX C +#define _HTCFG_I2C0_SDA_GPION 13 + +#define HTCFG_I2C0_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SCL_GPIOX) +#define HTCFG_I2C0_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SCL_GPIOX) +#define HTCFG_I2C0_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SCL_GPION) + +#define HTCFG_I2C0_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C0_SDA_GPIOX) +#define HTCFG_I2C0_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C0_SDA_GPIOX) +#define HTCFG_I2C0_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C0_SDA_GPION) + +#endif +#ifdef BSP_USING_I2C1 + +#define HTCFG_I2C1_IPN I2C1 + +#define _HTCFG_I2C1_SCL_GPIOX A +#define _HTCFG_I2C1_SCL_GPION 0 + +#define _HTCFG_I2C1_SDA_GPIOX A +#define _HTCFG_I2C1_SDA_GPION 1 + +#define HTCFG_I2C1_SCL_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SCL_GPIOX) +#define HTCFG_I2C1_SCL_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SCL_GPIOX) +#define HTCFG_I2C1_SCL_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SCL_GPION) + +#define HTCFG_I2C1_SDA_GPIO_CLK STRCAT2(P, _HTCFG_I2C1_SDA_GPIOX) +#define HTCFG_I2C1_SDA_GPIO_ID STRCAT2(GPIO_P, _HTCFG_I2C1_SDA_GPIOX) +#define HTCFG_I2C1_SDA_GPIO_PIN STRCAT2(GPIO_PIN_, _HTCFG_I2C1_SDA_GPION) + +#endif +#endif + +void ht32_usart_gpio_init(void *instance); +void ht32_spi_gpio_init(void *instance); +void ht32_i2c_gpio_init(void *instance); + +#ifdef __cplusplus +} +#endif + +#endif /* __HT32_MSP_H__ */ diff --git a/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_01_usbdconf.h b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_01_usbdconf.h new file mode 100644 index 00000000000..a512579519a --- /dev/null +++ b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_01_usbdconf.h @@ -0,0 +1,453 @@ +/*********************************************************************************************************//** + * @file IP/Example/ht32f5xxxx_01_usbdconf.h + * @version $Rev:: 2390 $ + * @date $Date:: 2017-12-21 #$ + * @brief The configuration file of USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_01_USBDCONF_H +#define __HT32F5XXXX_01_USBDCONF_H + +// Enter Low Power mode when Suspended +#define USBDCORE_ENABLE_LOW_POWER (0) +// + +#if (USBDCORE_ENABLE_LOW_POWER == 1) + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#else + #define USBDCore_LowPower(...) +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Interrupt Enable */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Interrupt Setting (UIER) +// USB Global Interrupt Enable (UGIE) (Default) +// Start Of Frame Interrupt Enable (SOFIE) +// USB Reset Interrupt Enable (URSTIE) (Default) +// Resume Interrupt Enable (RSMIE) (Default) +// Suspend Interrupt Enable (SUSPIE) (Default) +// Expected Start of Frame Interrupt Enable (ESOFE) +// Control Endpoint Interrupt Enable (EP0IE) (Default) +// Endpoint1 Interrupt Enable (EP1IE) +// Endpoint2 Interrupt Enable (EP2IE) +// Endpoint3 Interrupt Enable (EP3IE) +// Endpoint4 Interrupt Enable (EP4IE) +// Endpoint5 Interrupt Enable (EP5IE) +// Endpoint6 Interrupt Enable (EP6IE) +// Endpoint7 Interrupt Enable (EP7IE) +#define _UIER (0x011D) +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Control Endpoint0 Configuration +// Endpoint Buffer Length (EPLEN) +// <8=> 8 bytes +// <16=> 16 bytes +// <32=> 32 bytes +// <64=> 64 bytes + /* Maximum: 64 Bytes */ +#define _EP0LEN (64) + + +// Control Endpoint0 Interrupt Enable Settings (EP0IER) +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) (Default) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +// SETUP Token Packet Received Interrupt Enable (STRXIE) +// SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default) +// SETUP Data Error Interrupt Enable (SDERIE) +// Zero Length Data Packet Received Interrupt Enable (ZLRXIE) +#define _EP0_IER (0x212) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint1 Configuration +#define _EP1_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP1_CFG_EPADR (1) + +// Endpoint Enable (EPEN) +#define _EP1_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP1_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP1_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP1LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP1_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint2 Configuration +#define _EP2_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP2_CFG_EPADR (2) + +// Endpoint Enable (EPEN) +#define _EP2_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP2_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP2_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP2LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP2_IER (0x002) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint3 Configuration +#define _EP3_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP3_CFG_EPADR (3) + +// Endpoint Enable (EPEN) +#define _EP3_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP3_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP3_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP3LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP3_IER (0x10) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint4 Configuration +#define _EP4_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP4_CFG_EPADR (4) + +// Endpoint Enable (EPEN) +#define _EP4_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP4_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP4_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP4LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP4_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP4_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint5 Configuration +#define _EP5_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP5_CFG_EPADR (5) + +// Endpoint Enable (EPEN) +#define _EP5_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP5_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP5_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP5LEN_TMP (8) + + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP5_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP5_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint6 Configuration +#define _EP6_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP6_CFG_EPADR (6) + +// Endpoint Enable (EPEN) +#define _EP6_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP6_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP6_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP6LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP6_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP6_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint7 Configuration +#define _EP7_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP7_CFG_EPADR (7) + +// Endpoint Enable (EPEN) +#define _EP7_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP7_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP7_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP7LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP7_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP7_IER (0x10) +// +// + +#endif diff --git a/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_02_usbdconf.h b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_02_usbdconf.h new file mode 100644 index 00000000000..272e8cd127b --- /dev/null +++ b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_02_usbdconf.h @@ -0,0 +1,569 @@ +/*********************************************************************************************************//** + * @file IP/Example/ht32f5xxxx_02_usbdconf.h + * @version $Rev:: 5656 $ + * @date $Date:: 2021-11-24 #$ + * @brief The configuration file of USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_02_USBDCONF_H +#define __HT32F5XXXX_02_USBDCONF_H + +// Enter Low Power mode when Suspended +#define USBDCORE_ENABLE_LOW_POWER (0) +// + +#if (USBDCORE_ENABLE_LOW_POWER == 1) + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#else + #define USBDCore_LowPower(...) +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Interrupt Enable */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Interrupt Setting (UIER) +// USB Global Interrupt Enable (UGIE) (Default) +// Start Of Frame Interrupt Enable (SOFIE) +// USB Reset Interrupt Enable (URSTIE) (Default) +// Resume Interrupt Enable (RSMIE) (Default) +// Suspend Interrupt Enable (SUSPIE) (Default) +// Expected Start of Frame Interrupt Enable (ESOFE) +// Control Endpoint Interrupt Enable (EP0IE) (Default) +// Endpoint1 Interrupt Enable (EP1IE) +// Endpoint2 Interrupt Enable (EP2IE) +// Endpoint3 Interrupt Enable (EP3IE) +// Endpoint4 Interrupt Enable (EP4IE) +// Endpoint5 Interrupt Enable (EP5IE) +// Endpoint6 Interrupt Enable (EP6IE) +// Endpoint7 Interrupt Enable (EP7IE) +// Endpoint8 Interrupt Enable (EP8IE) +// Endpoint9 Interrupt Enable (EP9IE) +#define _UIER (0x011D) +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Control Endpoint0 Configuration +// Endpoint Buffer Length (EPLEN) +// <8=> 8 bytes +// <16=> 16 bytes +// <32=> 32 bytes +// <64=> 64 bytes + /* Maximum: 64 Bytes */ +#define _EP0LEN (64) + + +// Control Endpoint0 Interrupt Enable Settings (EP0IER) +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) (Default) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +// SETUP Token Packet Received Interrupt Enable (STRXIE) +// SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default) +// SETUP Data Error Interrupt Enable (SDERIE) +// Zero Length Data Packet Received Interrupt Enable (ZLRXIE) +#define _EP0_IER (0x212) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint1 Configuration +#define _EP1_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP1_CFG_EPADR (1) + +// Endpoint Enable (EPEN) +#define _EP1_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP1_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP1_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP1LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP1_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint2 Configuration +#define _EP2_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP2_CFG_EPADR (2) + +// Endpoint Enable (EPEN) +#define _EP2_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP2_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP2_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP2LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP2_IER (0x002) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint3 Configuration +#define _EP3_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP3_CFG_EPADR (3) + +// Endpoint Enable (EPEN) +#define _EP3_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP3_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP3_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP3LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP3_IER (0x10) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint4 Configuration +#define _EP4_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP4_CFG_EPADR (4) + +// Endpoint Enable (EPEN) +#define _EP4_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP4_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP4_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP4LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP4_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP4_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint5 Configuration +#define _EP5_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP5_CFG_EPADR (5) + +// Endpoint Enable (EPEN) +#define _EP5_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP5_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP5_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP5LEN_TMP (8) + + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP5_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP5_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint6 Configuration +#define _EP6_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP6_CFG_EPADR (6) + +// Endpoint Enable (EPEN) +#define _EP6_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP6_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP6_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP6LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP6_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP6_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint7 Configuration +#define _EP7_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP7_CFG_EPADR (7) + +// Endpoint Enable (EPEN) +#define _EP7_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP7_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP7_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP7LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP7_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP7_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint8 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint8 Configuration +#define _EP8_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP8_CFG_EPADR (8) + +// Endpoint Enable (EPEN) +#define _EP8_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP8_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP8_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP8LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP8_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint9 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint9 Configuration +#define _EP9_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +#define _EP9_CFG_EPADR (9) + +// Endpoint Enable (EPEN) +#define _EP9_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP9_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP9_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP9LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP9_IER (0x10) +// +// + +#endif diff --git a/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_conf.h b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_conf.h new file mode 100644 index 00000000000..c78b9bb75d7 --- /dev/null +++ b/bsp/ht32/ht32f52352/board/inc/ht32f5xxxx_conf.h @@ -0,0 +1,556 @@ +/*********************************************************************************************************//** + * @file IP/Example/ht32f5xxxx_conf.h + * @version $Rev:: 7109 $ + * @date $Date:: 2023-08-10 #$ + * @brief Library configuration file. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_CONF_H +#define __HT32F5XXXX_CONF_H + +/* Exported constants --------------------------------------------------------------------------------------*/ + +#define RETARGET_USB 1 +#define RETARGET_SYSLOG 2 +#define RETARGET_COM1 10 +#define RETARGET_COM2 11 +#define RETARGET_USART0 12 +#define RETARGET_USART1 13 +#define RETARGET_UART0 14 +#define RETARGET_UART1 15 +#define RETARGET_UART2 16 +#define RETARGET_UART3 17 + + +/* Retarget settings of the C standard I/O library functions (printf, scanf, getchar, ...etc.) */ +/* +// Enable Retarget +// Retarget Port +// <1=> USB Virtual COM +// <2=> Syslog +// <10=> COM1 +// <11=> COM2 +// <12=> USART0 +// <13=> USART1 +// <14=> UART0 +// <15=> UART1 +// <16=> UART2 +// <17=> UART3 +// Enable Auto Return +// Auto Return function adds "\r" before "\n" automatically when print message by Retarget. +*/ +#define _RETARGET 1 +#define RETARGET_PORT 10 +#define _AUTO_RETURN 0 + +#ifndef AUTO_RETURN +#if (_AUTO_RETURN == 1) +#define AUTO_RETURN +#endif +#endif + +/* Enable Interrupt Mode for UxART Retarget +// Retarget COM/UxART Setting +// UxART Baudrate +// Enable Interrupt Mode for UxART Tx Retarget +// Define UxARTn_IRQHandler By Retarget (ht32_serial.c) +// Disable (RETARGET_DEFINE_HANDLER = 0) if application already have UxARTn_IRQHandler. +// RETARGET_UART_IRQHandler() shall be called by UxARTn_IRQHandler when disable. +// Tx Buffer Length (in byte) +// +*/ +#define RETARGET_UxART_BAUDRATE 115200 +#define RETARGET_INT_MODE 0 +#define RETARGET_DEFINE_HANDLER 1 +#define RETARGET_INT_BUFFER_SIZE 64 + +#if (_RETARGET == 1) +#if (RETARGET_PORT == RETARGET_USB) + #define RETARGET_IS_USB +// Retarget USB Virtual COM Setting +// Communication (Interrupt IN) +// <1=> Endpoint 1 +// <2=> Endpoint 2 +// <3=> Endpoint 3 +// <4=> Endpoint 4 +// <5=> Endpoint 5 +// <6=> Endpoint 6 +// <7=> Endpoint 7 +// Data Rx (Bulk OUT) +// <1=> Endpoint 1 +// <2=> Endpoint 2 +// <3=> Endpoint 3 +// <4=> Endpoint 4 +// <5=> Endpoint 5 +// <6=> Endpoint 6 +// <7=> Endpoint 7 +// Data Tx (Bulk IN) +// <1=> Endpoint 1 +// <2=> Endpoint 2 +// <3=> Endpoint 3 +// <4=> Endpoint 4 +// <5=> Endpoint 5 +// <6=> Endpoint 6 +// <7=> Endpoint 7 +// Communication Endpoint Buffer Length (in byte) <4-64:4> +// Data Rx Endpoint Buffer Length (in byte) <4-64:4> +// Data Tx Endpoint Buffer Length (in byte) <4-64:4> +// Rx Buffer Length (in byte) <64-1024:4> +// Tx Buffer Length (in byte) <1-63:1> +// Please use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1. +// USB Tx Mode (BULK IN) +// <0=> Block Mode (Wait until both USB and terminal software are ready) +// <1=> Non-Block Mode (Drop data if USB or terminal software is not ready) +// Enable HSI Auto Trim By USB Function +// Need turn on if the USB clock source is from HSI (PLL USBPLL clock Source). + #define RETARGET_CTRL_EPT (5) + #define RETARGET_RX_EPT (6) + #define RETARGET_TX_EPT (7) + #define RETARGET_CTRL_EPTLEN (8) + #define RETARGET_RX_EPTLEN (64) + #define RETARGET_TX_EPTLEN (64) + #define RETARGET_BUFFER_SIZE (64) + #define RETARGET_TXBUFFER_SIZE (1) // Use "SERIAL_Flush()" to sent out the buffer data immediately when Tx Buffer Length > 1. + #define RETARGET_USB_MODE (0) + #define RETARGET_HSI_ATM (1) +// +#elif (RETARGET_PORT == RETARGET_COM1) + #define RETARGET_COM_PORT COM1 + #define RETARGET_USART_PORT COM1_PORT + #define RETARGET_UART_IRQn COM1_IRQn + #define RETARGET_UART_IRQHandler COM1_IRQHandler + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_COM2) + #define RETARGET_COM_PORT COM2 + #define RETARGET_USART_PORT COM2_PORT + #define RETARGET_UART_IRQn COM2_IRQn + #define RETARGET_UART_IRQHandler COM2_IRQHandler + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_USART0) + #define RETARGET_UxART_IPN USART0 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_USART1) + #define RETARGET_UxART_IPN USART1 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART0) + #define RETARGET_UxART_IPN UART0 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART1) + #define RETARGET_UxART_IPN UART1 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART2) + #define RETARGET_UxART_IPN UART2 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#elif (RETARGET_PORT == RETARGET_UART3) + #define RETARGET_UxART_IPN UART3 + #define RETARGET_USART_PORT STRCAT2(HT_, RETARGET_UxART_IPN) + #define RETARGET_UART_IRQn STRCAT2(RETARGET_UxART_IPN, _IRQn) + #define RETARGET_UART_IRQHandler STRCAT2(RETARGET_UxART_IPN, _IRQHandler) + #define RETARGET_IS_UART +#endif + extern void RETARGET_Configuration(void); +#else + #define RETARGET_Configuration(...) + #undef printf + #undef getchar + #define printf(...) + #define getchar() (0) +#endif + +#if (RETARGET_DEFINE_HANDLER == 0) +#undef RETARGET_UART_IRQHandler +#endif + +/* +// Enable HT32 Time Function +// Provide "Time_GetTick()" and "Time_Dealy()" functions. + +// Timer Selection +// <0=> BFTM0 +// <1=> BFTM1 +// <2=> SCTM0 +// <3=> SCTM1 +// <4=> SCTM2 +// <5=> SCTM3 +// <6=> PWM0 +// <7=> PWM1 +// <8=> PWM2 +// <9=> GPTM0 +// <10=> GPTM1 +// <11=> MCTM0 + +// Timer Clock Setting +// +// Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler) +// HTCFG_TIME_CLKSRC = _HTCFG_TIME_CORECLK / (2^HTCFG_TIME_PCLK_DIV) +// _HTCFG_TIME_CORECLK = LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL) + +// -- Core Clock Setting (CK_AHB) +// HTCFG_TIME_CLKSEL +// 0 = Default Maximum (LIBCFG_MAX_SPEED) +// 1 = Manual Input (HTCFG_TIME_CLK_MANUAL) +// <0=> Default Maximum (LIBCFG_MAX_SPEED) +// <1=> Manual Input (HTCFG_TIME_CLK_MANUAL) + +// -- Core Clock Manual Input (Hz) +// HTCFG_TIME_CLK_MANUAL +// Only meaningful when Core Clock Setting (HTCFG_TIME_CLKSEL) = Manual Input (1) + +// -- APB Peripheral Clock Prescaler +// HTCFG_TIME_PCLK_DIV +// <0=> /1 +// <1=> /2 +// <2=> /4 +// <3=> /8 + +// Time Tick (Hz, not applicable for BFTM) <1-1000000:100> +// Not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM. +*/ +#if (0) // Enable HT32 Time Function +#define HTCFG_TIME_IPSEL (0) +#define HTCFG_TIME_CLKSEL (0) // 0 = Default Maximum (LIBCFG_MAX_SPEED), 1 = Manual Input (HTCFG_TIME_CLKSRC) +#define HTCFG_TIME_CLK_MANUAL (20000000) // Only meaningful when HTCFG_TIME_CLKSEL = 1 (Manual Input) +#define HTCFG_TIME_PCLK_DIV (0) // 0 ~ 3. (/1, /2, /4, /8) +#define HTCFG_TIME_TICKHZ (1000) // Hz, not applicable for BFTM, fixed TICKHZ to HTCFG_TIME_CLKSRC for BFTM +#define HTCFG_TIME_MULTIPLE (1) // MUST be 1, 2, 4, 8. TICK = COUNT / MULTIPLE. Not applicable for BFTM. +/* + + Timer Clock = (Core Clock) / (APB Peripheral Clock Prescaler) + HTCFG_TIME_CLKSRC = (_HTCFG_TIME_CORECLK) / (2^HTCFG_TIME_PCLK_DIV) + where _HTCFG_TIME_CORECLK can be LIBCFG_MAX_SPEED or HTCFG_TIME_CLK_MANUAL (selected by HTCFG_TIME_CLKSEL) + + Tick Range: 0 ~ 2^32 / HTCFG_TIME_TICKHZ (maximum tick time) + Interrupt Time: _HTCFG_TIME_OVERFLOW_VALUE / (HTCFG_TIME_TICKHZ * HTCFG_TIME_MULTIPLE) Second + (Interrupt Time is not applicable for BFTM) + + Example: 32-bit BFTM with 48 MHz Timer Clock + HTCFG_TIME_TICKHZ = HTCFG_TIME_CLKSRC = 48000000 + Tick Range: 0 ~ 2^32 / 48000000 = 0 ~ 89.478485 Second (maximum tick time, return to 0 every 89.478485 Second) + BFTM do not use interrupt + + Example: 16-bit GPTM with 1 ms tick + HTCFG_TIME_TICKHZ = 1000 (Hz) + HTCFG_TIME_MULTIPLE = 1 (1 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 1000 = 0 ~ 4294967 Second = 0 ~ 49.7 Day (maximum tick time, return to 0 every 49.7 Day) + Interrupt Time: 65536 / (1000 * 1) = 65.536 Second (Trigger interrupt every 65.536 Second) +*/ +#endif +/* +// +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file (this file). +*/ +/* +// Enable User Define HSE Value +// Enable user define HSE value to overwrite default "HSE_VALUE" define in "ht32fxxxxx_nn.h". +// HSE Value (Hz) +*/ +#if (0) +#define HSE_VALUE 16000000 +#endif +/* +// +*/ + +/* +// Enable CKOUT Function +*/ +#define ENABLE_CKOUT 0 + +/* +// Enable Get CK_ADC of "CKCU_GetClocksFrequency()" +// Enable ADC0_Freq and ADC1_Freq of the "CKCU_GetClocksFrequency()" function. It required the division calculation (by C Library) and increased the code size. +*/ +#define HT32_LIB_ENABLE_GET_CK_ADC 0 + +/* The DEBUG definition to enter debug mode for library */ +/* +// Library Debug Mode +*/ +#define HT32_LIB_DEBUG 0 + + +/* Enable/disable the specific peripheral inclusion */ + +// Library Inclusion Configuration +/* ADC -----------------------------------------------------------------------------------------------------*/ +/* +// ADC Library +*/ +#define _ADC 1 + +/* AES -----------------------------------------------------------------------------------------------------*/ +/* +// AES Library +*/ +#define _AES 1 + +/* BFTM ----------------------------------------------------------------------------------------------------*/ +/* +// BFTM Library +*/ +#define _BFTM 1 + +/* CAN -----------------------------------------------------------------------------------------------------*/ +/* +// CAN Library +*/ +#define _CAN 1 + +/* Clock Control -------------------------------------------------------------------------------------------*/ +/* +// Clock Control Library +*/ +#define _CKCU 1 + +/* Comparator ----------------------------------------------------------------------------------------------*/ +/* +// Comparator Library +*/ +#define _CMP 1 + +/* CRC -----------------------------------------------------------------------------------------------------*/ +/* +// CRC Library +*/ +#define _CRC 1 + +/* DAC -----------------------------------------------------------------------------------------------------*/ +/* +// DAC Library +*/ +#define _DAC 1 + +/* DAC Dual 16-bit -----------------------------------------------------------------------------------------*/ +/* +// DAC_Dual16 Library +*/ +#define _DAC_DUAL16 1 + +/* DIV -----------------------------------------------------------------------------------------------------*/ +/* +// DIV Library +*/ +#define _DIV 1 + +/* EBI -----------------------------------------------------------------------------------------------------*/ +/* +// EBI Library +*/ +#define _EBI 1 + +/* EXTI ----------------------------------------------------------------------------------------------------*/ +/* +// EXTI Library +*/ +#define _EXTI 1 + +/* Flash ---------------------------------------------------------------------------------------------------*/ +/* +// Flash Library +*/ +#define _FLASH 1 + +/* GPIO ----------------------------------------------------------------------------------------------------*/ +/* +// GPIO Library +*/ +#define _GPIO 1 + +/* GPTM ----------------------------------------------------------------------------------------------------*/ +/* +// GPTM Library +*/ +#define _GPTM 1 + +/* I2C -----------------------------------------------------------------------------------------------------*/ +/* +// I2C Library +*/ +#define _I2C 1 + +/* I2S -----------------------------------------------------------------------------------------------------*/ +/* +// I2S Library +*/ +#define _I2S 1 + +/* LCD -----------------------------------------------------------------------------------------------------*/ +/* +// LCD Library +*/ +#define _LCD 1 + +/* LEDC ----------------------------------------------------------------------------------------------------*/ +/* +// LEDC Library +*/ +#define _LEDC 1 + +/* MCTM ----------------------------------------------------------------------------------------------------*/ +/* +// MCTM Library +*/ +#define _MCTM 1 + +/* MIDI ----------------------------------------------------------------------------------------------------*/ +/* +// MIDI Library +*/ +#define _MIDI 1 + +/* OPA -----------------------------------------------------------------------------------------------------*/ +/* +// OPA +*/ +#define _OPA 1 + +/* PDMA ----------------------------------------------------------------------------------------------------*/ +/* +// PDMA Library +*/ +#define _PDMA 1 + +/* PWM -----------------------------------------------------------------------------------------------------*/ +/* +// PWM Library +*/ +#define _PWM 1 + +/* PWRCU ---------------------------------------------------------------------------------------------------*/ +/* +// PWRCU Library +*/ +#define _PWRCU 1 + +/* RSTCU ---------------------------------------------------------------------------------------------------*/ +/* +// RSTCU Library +*/ +#define _RSTCU 1 + +/* RTC -----------------------------------------------------------------------------------------------------*/ +/* +// RTC Library +*/ +#define _RTC 1 + +/* SCI -----------------------------------------------------------------------------------------------------*/ +/* +// SCI Library +*/ +#define _SCI 1 + +/* SCTM ----------------------------------------------------------------------------------------------------*/ +/* +// SCTM Library +*/ +#define _SCTM 1 + +/* SLED ----------------------------------------------------------------------------------------------------*/ +/* +// SLED Library +*/ +#define _SLED 1 + +/* SPI -----------------------------------------------------------------------------------------------------*/ +/* +// SPI Library +*/ +#define _SPI 1 + +/* TKEY ----------------------------------------------------------------------------------------------------*/ +/* +// TKEY Library +*/ +#define _TKEY 1 + +/* USART ---------------------------------------------------------------------------------------------------*/ +/* +// USART/UART Library +*/ +#define _USART 1 + +/* USBD ----------------------------------------------------------------------------------------------------*/ +/* +// USB Library +*/ +#define _USB 1 + +/* WDT -----------------------------------------------------------------------------------------------------*/ +/* +// WDT Library +*/ +#define _WDT 1 + +/* Misc ----------------------------------------------------------------------------------------------------*/ +/* +// Misc Library +*/ +#define _MISC 1 + +/* Serial --------------------------------------------------------------------------------------------------*/ +/* +// Serial Library +*/ +#define _SERIAL 1 + +/* Software DIV --------------------------------------------------------------------------------------------*/ +/* +// Software Divider Library +*/ +#define _SWDIV 1 + +/* Software Random Number ----------------------------------------------------------------------------------*/ +/* +// Software Random Number Library +*/ +#define _SWRAND 1 + + +// + +#endif diff --git a/bsp/ht32/ht32f52352/board/linker_scripts/link.icf b/bsp/ht32/ht32f52352/board/linker_scripts/link.icf new file mode 100644 index 00000000000..65c2bfc8b7c --- /dev/null +++ b/bsp/ht32/ht32f52352/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file diff --git a/bsp/ht32/ht32f52352/board/linker_scripts/link.lds b/bsp/ht32/ht32f52352/board/linker_scripts/link.lds new file mode 100644 index 00000000000..27269dd77ea --- /dev/null +++ b/bsp/ht32/ht32f52352/board/linker_scripts/link.lds @@ -0,0 +1,156 @@ +/* + * linker script for AT32 with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 96K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/ht32/ht32f52352/board/linker_scripts/link.sct b/bsp/ht32/ht32f52352/board/linker_scripts/link.sct new file mode 100644 index 00000000000..ece577cb3ea --- /dev/null +++ b/bsp/ht32/ht32f52352/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x0001FE00 { ; load region size_region + ER_IROM1 0x00000000 0x0001FE00 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/ht32/ht32f52352/board/src/board.c b/bsp/ht32/ht32f52352/board/src/board.c new file mode 100644 index 00000000000..e0160468e94 --- /dev/null +++ b/bsp/ht32/ht32f52352/board/src/board.c @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "board.h" + +/* This feature will initialize the HT32 chip clock */ +void rt_hw_board_clock_init(void) +{ + +} diff --git a/bsp/ht32/ht32f52352/board/src/ht32_msp.c b/bsp/ht32/ht32f52352/board/src/ht32_msp.c new file mode 100644 index 00000000000..1315b9723f9 --- /dev/null +++ b/bsp/ht32/ht32f52352/board/src/ht32_msp.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "ht32_msp.h" + +/* GPIO configuration for UART */ +#ifdef BSP_USING_UART +void ht32_usart_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_USART_TypeDef *usart_x = (HT_USART_TypeDef *)instance; +#ifdef BSP_USING_USART0 + if (HT_USART0 == usart_x) + { + CKCUClock.Bit.HTCFG_USART0_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_USART0_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_USART0_RX_GPIO_PORT, HTCFG_USART0_RX_GPIO_PIN, GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_USART0_TX_GPIO_ID, HTCFG_USART0_TX_GPIO_PIN, AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_USART0_RX_GPIO_ID, HTCFG_USART0_RX_GPIO_PIN, AFIO_FUN_USART_UART); + } +#endif +#ifdef BSP_USING_USART1 + if (HT_USART1 == usart_x) + { + CKCUClock.Bit.HTCFG_USART1_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_USART1_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_USART1_RX_GPIO_PORT, HTCFG_USART1_RX_GPIO_PIN, GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_USART1_TX_GPIO_ID, HTCFG_USART1_TX_GPIO_PIN, AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_USART1_RX_GPIO_ID, HTCFG_USART1_RX_GPIO_PIN, AFIO_FUN_USART_UART); + } +#endif +#ifdef BSP_USING_UART0 + if (HT_UART0 == usart_x) + { + CKCUClock.Bit.HTCFG_UART0_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_UART0_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_UART0_RX_GPIO_PORT, HTCFG_UART0_RX_GPIO_PIN, GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_UART0_TX_GPIO_ID, HTCFG_UART0_TX_GPIO_PIN, AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_UART0_RX_GPIO_ID, HTCFG_UART0_RX_GPIO_PIN, AFIO_FUN_USART_UART); + } +#endif +#ifdef BSP_USING_UART1 + if (HT_UART1 == usart_x) + { + CKCUClock.Bit.HTCFG_UART1_TX_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_UART1_RX_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Turn on UxART Rx internal pull up resistor to prevent unknow state */ + GPIO_PullResistorConfig(HTCFG_UART1_RX_GPIO_PORT, HTCFG_UART1_RX_GPIO_PIN, GPIO_PR_UP); + /* Config AFIO mode as UxART function */ + AFIO_GPxConfig(HTCFG_UART1_TX_GPIO_ID, HTCFG_UART1_TX_GPIO_PIN, AFIO_FUN_USART_UART); + AFIO_GPxConfig(HTCFG_UART1_RX_GPIO_ID, HTCFG_UART1_RX_GPIO_PIN, AFIO_FUN_USART_UART); + } +#endif +} +#endif + +/* GPIO configuration for SPI */ +#ifdef BSP_USING_SPI +void ht32_spi_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_SPI_TypeDef *spi_x = (HT_SPI_TypeDef *)instance; +#ifdef BSP_USING_SPI0 + if (HT_SPI0 == spi_x) + { + CKCUClock.Bit.HTCFG_SPI0_SCK_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI0_MISO_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI0_MOSI_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + AFIO_GPxConfig(HTCFG_SPI0_SCK_GPIO_ID, HTCFG_SPI0_SCK_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI0_MISO_GPIO_ID, HTCFG_SPI0_MISO_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI0_MOSI_GPIO_ID, HTCFG_SPI0_MOSI_GPIO_PIN, AFIO_FUN_SPI); + } +#endif +#ifdef BSP_USING_SPI1 + if (HT_SPI1 == spi_x) + { + CKCUClock.Bit.HTCFG_SPI1_SCK_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI1_MISO_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_SPI1_MOSI_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + AFIO_GPxConfig(HTCFG_SPI1_SCK_GPIO_ID, HTCFG_SPI1_SCK_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI1_MISO_GPIO_ID, HTCFG_SPI1_MISO_GPIO_PIN, AFIO_FUN_SPI); + AFIO_GPxConfig(HTCFG_SPI1_MOSI_GPIO_ID, HTCFG_SPI1_MOSI_GPIO_PIN, AFIO_FUN_SPI); + } +#endif +} +#endif + +/* GPIO configuration for I2C */ +#ifdef BSP_USING_I2C +void ht32_i2c_gpio_init(void *instance) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + HT_I2C_TypeDef *i2c_x = (HT_I2C_TypeDef *)instance; +#ifdef BSP_USING_I2C0 + if (HT_I2C0 == i2c_x) + { + CKCUClock.Bit.HTCFG_I2C0_SCL_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_I2C0_SDA_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Configure GPIO to I2C mode */ + AFIO_GPxConfig(HTCFG_I2C0_SCL_GPIO_ID, HTCFG_I2C0_SCL_GPIO_PIN, AFIO_FUN_I2C); + AFIO_GPxConfig(HTCFG_I2C0_SDA_GPIO_ID, HTCFG_I2C0_SDA_GPIO_PIN, AFIO_FUN_I2C); + } +#endif +#ifdef BSP_USING_I2C1 + if (HT_I2C1 == i2c_x) + { + CKCUClock.Bit.HTCFG_I2C1_SCL_GPIO_CLK = 1; + CKCUClock.Bit.HTCFG_I2C1_SDA_GPIO_CLK = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + /* Configure GPIO to I2C mode */ + AFIO_GPxConfig(HTCFG_I2C1_SCL_GPIO_ID, HTCFG_I2C1_SCL_GPIO_PIN, AFIO_FUN_I2C); + AFIO_GPxConfig(HTCFG_I2C1_SDA_GPIO_ID, HTCFG_I2C1_SDA_GPIO_PIN, AFIO_FUN_I2C); + } +#endif +} +#endif diff --git a/bsp/ht32/ht32f52352/figures/board.png b/bsp/ht32/ht32f52352/figures/board.png new file mode 100644 index 00000000000..2e7fb71882b Binary files /dev/null and b/bsp/ht32/ht32f52352/figures/board.png differ diff --git a/bsp/ht32/ht32f52352/project.uvoptx b/bsp/ht32/ht32f52352/project.uvoptx new file mode 100644 index 00000000000..eaed3566caf --- /dev/null +++ b/bsp/ht32/ht32f52352/project.uvoptx @@ -0,0 +1,179 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 2 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0HT32F.FLM -FS00 -FL0100000 -FP0($$Device:HT32F52352$ARM\Flash\HT32F.FLM) -FF1HT32F_OPT.FLM -FS11FF00000 -FL11000 -FP1($$Device:HT32F52352$ARM\Flash\HT32F_OPT.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F52352$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F52352$ARM\Flash\HT32F_OPT.FLM)) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/ht32/ht32f52352/project.uvprojx b/bsp/ht32/ht32f52352/project.uvprojx new file mode 100644 index 00000000000..e127766d5f7 --- /dev/null +++ b/bsp/ht32/ht32f52352/project.uvprojx @@ -0,0 +1,1345 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC + + + HT32F52352 + Holtek + Holtek.HT32_DFP.1.0.19 + http://mcu.holtek.com.tw/pack + IRAM(0x20000000,0x4000) IROM(0x00000000,0x1FE00) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F52352$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F52352$ARM\Flash\HT32F_OPT.FLM)) + 0 + $$Device:HT32F52352$ARM\INC\Holtek\HT32F5xxxx\ht32f5xxxx_01.h + + + + + + + + + + $$Device:HT32F52352$SVD\HT32F52342_52.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x0 + 0x1fe00 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x1fe00 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, USE_HT32_DRIVER, __RTTHREAD__, USE_HT32F52352_SK, USE_HT32F52342_52, USE_MEM_HT32F52352 + + ..\..\..\libcpu\arm\cortex-m0;..\libraries\ht32_drivers;applications;.;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\compilers\common\include;..\libraries\HT32_STD_5xxxx_FWLib\library\CMSIS\Include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\posix\io\epoll;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;board\inc;..\..\..\include;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\inc;..\..\..\components\drivers\include;..\libraries\HT32_STD_5xxxx_FWLib\library\Device\Holtek\HT32F5xxxx\Include;..\..\..\components\libc\posix\ipc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_HT32_CHIP=4 + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + + + cunistd.c + 1 + ..\..\..\components\libc\compilers\common\cunistd.c + + + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + + + DeviceDrivers + + + device.c + 1 + ..\..\..\components\drivers\core\device.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + i2c-bit-ops.c + 1 + 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waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + pin.c + 1 + ..\..\..\components\drivers\pin\pin.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + spi_core.c + 1 + ..\..\..\components\drivers\spi\spi_core.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + spi_dev.c + 1 + ..\..\..\components\drivers\spi\spi_dev.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + Drivers + + + board.c + 1 + board\src\board.c + + + + + ht32_msp.c + 1 + board\src\ht32_msp.c + + + + + startup_ht32f5xxxx_01.s + 2 + ..\libraries\HT32_STD_5xxxx_FWLib\library\Device\Holtek\HT32F5xxxx\Source\ARM\startup_ht32f5xxxx_01.s + + + + + drv_common.c + 1 + ..\libraries\ht32_drivers\drv_common.c + + + + + drv_gpio.c + 1 + ..\libraries\ht32_drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\ht32_drivers\drv_usart.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + + + + __RT_KERNEL_SOURCE__ + + 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+ + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + + + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + + + + + Libraries + + + ht32f5xxxx_sci.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_sci.c + + + + + ht32f5xxxx_rstcu.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_rstcu.c + + + + + ht32f5xxxx_adc.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_adc.c + + + + + ht32f5xxxx_cmp.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_cmp.c + + + + + ht32_cm0plus_misc.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32_cm0plus_misc.c + + + + + ht32f5xxxx_crc.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_crc.c + + + + + ht32f5xxxx_spi.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_spi.c + + + + + ht32f5xxxx_pwrcu.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_pwrcu.c + + + + + ht32f5xxxx_pdma.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_pdma.c + + + + + ht32f5xxxx_mctm.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_mctm.c + + + + + ht32f5xxxx_rtc.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_rtc.c + + + + + ht32f5xxxx_i2s.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_i2s.c + + + + + ht32f5xxxx_usbd.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_usbd.c + + + + + ht32f5xxxx_wdt.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_wdt.c + + + + + ht32f5xxxx_ebi.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_ebi.c + + + + + ht32f5xxxx_tm.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_tm.c + + + + + ht32f5xxxx_ckcu.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_ckcu.c + + + + + ht32f5xxxx_gpio.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_gpio.c + + + + + ht32f5xxxx_exti.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_exti.c + + + + + ht32f5xxxx_bftm.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_bftm.c + + + + + ht32f5xxxx_usart.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_usart.c + + + + + ht32f5xxxx_i2c.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_i2c.c + + + + + ht32f5xxxx_flash.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\HT32F5xxxx_Driver\src\ht32f5xxxx_flash.c + + + + + system_ht32f5xxxx_01.c + 1 + ..\libraries\HT32_STD_5xxxx_FWLib\library\Device\Holtek\HT32F5xxxx\Source\system_ht32f5xxxx_01.c + + + + + + + + + + + + diff --git a/bsp/ht32/ht32f52352/rtconfig.h b/bsp/ht32/ht32f52352/rtconfig.h new file mode 100644 index 00000000000..3caf5a5be0f --- /dev/null +++ b/bsp/ht32/ht32f52352/rtconfig.h @@ -0,0 +1,271 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "usart1" +#define RT_VER_NUM 0x50100 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M0 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_SPI +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Memory protection */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* BL808 WiFi */ + + +/* CYW43439 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + + +/* Kendryte SDK */ + + +/* sensors drivers */ + + +/* touch drivers */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +#define SOC_FAMILY_HT32 +#define SOC_SERIES_HT32F5 + +/* Hardware Drivers Config */ + +#define SOC_HT32F52352 + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_USART1 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/ht32/ht32f52352/rtconfig.py b/bsp/ht32/ht32f52352/rtconfig.py new file mode 100644 index 00000000000..964fa9313e6 --- /dev/null +++ b/bsp/ht32/ht32f52352/rtconfig.py @@ -0,0 +1,152 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='keil' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' +# EXEC_PATH = r'D:\keil5\keil_v532\UV4' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M0 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + diff --git a/bsp/ht32/ht32f52352/template.uvoptx b/bsp/ht32/ht32f52352/template.uvoptx new file mode 100644 index 00000000000..eaed3566caf --- /dev/null +++ b/bsp/ht32/ht32f52352/template.uvoptx @@ -0,0 +1,179 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 2 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0HT32F.FLM -FS00 -FL0100000 -FP0($$Device:HT32F52352$ARM\Flash\HT32F.FLM) -FF1HT32F_OPT.FLM -FS11FF00000 -FL11000 -FP1($$Device:HT32F52352$ARM\Flash\HT32F_OPT.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F52352$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F52352$ARM\Flash\HT32F_OPT.FLM)) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/ht32/ht32f52352/template.uvprojx b/bsp/ht32/ht32f52352/template.uvprojx new file mode 100644 index 00000000000..2530ad2a7e3 --- /dev/null +++ b/bsp/ht32/ht32f52352/template.uvprojx @@ -0,0 +1,392 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060422::V5.06 update 4 (build 422)::ARMCC + + + HT32F52352 + Holtek + Holtek.HT32_DFP.1.0.19 + http://mcu.holtek.com.tw/pack + IRAM(0x20000000,0x4000) IROM(0x00000000,0x1FE00) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0HT32F -FS00 -FL0100000 -FF1HT32F_OPT -FS11FF00000 -FL11000 -FP0($$Device:HT32F52352$ARM\Flash\HT32F.FLM) -FP1($$Device:HT32F52352$ARM\Flash\HT32F_OPT.FLM)) + 0 + $$Device:HT32F52352$ARM\INC\Holtek\HT32F5xxxx\ht32f5xxxx_01.h + + + + + + + + + + $$Device:HT32F52352$SVD\HT32F52342_52.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x0 + 0x1fe00 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x1fe00 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_HT32_CHIP=4 + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + diff --git a/bsp/ht32/libraries/.ignore_format.yml b/bsp/ht32/libraries/.ignore_format.yml new file mode 100644 index 00000000000..65b2f1a1564 --- /dev/null +++ b/bsp/ht32/libraries/.ignore_format.yml @@ -0,0 +1,7 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- HT32_STD_1xxxx_FWLib +- HT32_STD_5xxxx_FWLib diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/Release_Notes.txt b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/Release_Notes.txt new file mode 100644 index 00000000000..20ad57f3fc1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/Release_Notes.txt @@ -0,0 +1,876 @@ +/*********************************************************************************************************//** + * @file Release_Notes.txt + * @version V1.4.1 + * @date 2023-10-31 + * @brief The Release notes of HT32 Firmware Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +// Supported Device +// ======================================== +// HT32F1653, HT32F1654 +// HT32F1655, HT32F1656 +// HT32F12345 +// HT32F12364 +// HT32F12365, HT32F12366 +// HT32F22366 + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.4.1_2982 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-10-31 + + Main Changes + + Add new example. + - "GPIO/PinLock" + + Modify examples below, add volatile qualifiers on some variables (in the for loop usage) + to fix the Arm Compiler Version 6 optimization issue. + ("u32" to "vu32", unsigned int to volatile unsigned int). + - “PWRCU/PowerDown_WAKEUPPin” + - “PWRCU/PowerDown_RTC” + - “TM/PWM” + + Modify examples below, use separate "if" statements instead of "if-else" to avoid double-entry ISR. + - "PWRCU/DeepSleepMode1" + - "PWRCU/DeepSleepMode2" + + Modify "ht32_time.h", "ht32f1xxxx_conf.h" and "ht32_time_conf.h" for "LIBCFG_CKCU_NO_APB_PRESCALER" series. + - To ensure the correct configuration of the timer clock, the "HTCFG_TIME_PCLK_DIV" is redefined as 0. + + Add "Project or Target File Clearing" functions ("_ClearProject.bat" and "_ClearTarget.bat"). + + Modify "syscall.c" to prevent redundant initialization of the heap index. + + Modify "ht32f1xxxx_01.h" to add below definition. + - "sc64", "vs64", "vsc64", "uc64", "vu64", "vuc64" + + Modify PWRCU related define (The left side old one is still kept for backward compatible). + - PWRCU_FLAG_BAKPOR -> PWRCU_FLAG_PWRPOR + + Modify "RETARGET_Configuration()", add the operation of UxARTn peripheral clock enable. + + Update and sync "ht32f1xxxx_conf.h", modify related define of UxARTn retarget port. + + Update "ht32_op.c" and "ht32_op.s" to support new version of bootloader waiting time setting address. + (The setting address is changed from 0x1FF0002C to 0x1FF0004C) + + Add "ht32_op_V107.c" and "ht32_op_V107.s" to support the use of older versions of bootloader. + + Add "CKCU_ATCInit()" API for HSI Auto Trim initial function. + + Update "ht32f1xxxx_adc.c" and "ht32f1xxxx_adc_02.c", modify the ADC enable related flow. + + Add the below folder, For the BMduino shield/module Keil Driver. + - "BestModules" + + Others + + Update comment, format, typing error, and coding style. + + Adjust "LIBCFG_xxxxx" definition below. + - "LIBCFG_CKCU_APBCLKFIX" rename to "LIBCFG_CKCU_NO_APB_PRESCALER" + + Modify the Sourcery G++ Lite toolchain project. + - Set C99 mode to fix issues after updating CMSIS v5.9.0 ("for" loop initial declarations). + + Update e-Link32 Pro/Lite Command line tool as "V1.19" ("utilities/elink32pro/eLink32pro.exe"). + + Modify "_ProjectConfigScript.bat" to prevent the creation of project that copy unused system/startup files. + + Update "project_template/Script" for adding project C++ source files and setting the chip model mechanism. + - The updated files are as follows: + "Script/_ProjectSource.bat" + "Script/_ProjectSource.ini" + + Update "project_template/Script" for improving script mechanism. + - The updated files are as follows: + "Script/_CreateProjectConfScript.bat" + "Script/_CreateProjectScript.bat" + "Script/_ht32_ic_name.ini" + + Modify and check the example supportability of each IC. + + Add the below file, for the BMduino shield. + - "ht32_undef_IP.h" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.3.2_2858 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-02-02 + + Main Changes + + Add new examples: + - "SRAM_Overwrite/Watchpoint_Heap" + - "SRAM_Overwrite/Watchpoint_Stack" + + Update "ht32f1xxxx_conf.h" for user layer HSE_VALUE setting. + + Others + + Update comment, format, typing error, and coding style. + + Modify "system_ht32fxxxxx_nn.c", add HSE_VALUE notice and update PLL Out formula. + + Update and sync system.c files. + + Update EEPROM Emulation middleware, improve efficacy and reduce resource usage. + "utilities/middleware/eeprom_emulation.c" + "utilities/middleware/ht32_eeprom_config_templet.h" + + Update I2C Master middleware, improve setting way and fix minor errors. + "utilities/middleware/i2c_master.c/.h" + "utilities/middleware/i2c_master_config_templet.h" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.3.1_2808 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-12-01 + + Main Changes + + Update "ht32_time.h", fix a formula error of "TIME_TICK2US()" and "TIME_TICK2MS()" macro. + + Modify "ht32_retarget.c", fix retarget can't work when the MicroLIB is not used in Keil's V6 compiler. + + Modify "ht32_serial.c/.h" and "ht32_retarget.c", fix ITM setting issue. + + Update "ht32fxxxx_sk.h", add TRACESWO pin assignment for ITM. + + Update "SPI/PDMA" example, change the order of API execution (SPI_SELOutputCmd() execution before SPI_Cmd()). + + Update "CSIF/Init" example, modify the datatype form and add comments to explain the length of the Rx buffer. + + Update following I2C example. (sync. with M0+) + - I2C/7_bit_mode + - I2C/10_bit_mode + - I2C/EEPROM_Simulate + - I2C/Interrupt + - I2C/PDMA + + GPIO + - Add new define "GPIO_PIN_NUM_n" for GPIO pin number (n = 0 ~ 15). + + EXTI + - Add "gEXTIn_IRQn[]" and "EXTI_GetIRQn()" macro to map GPIO pin number (0 ~ 15) to "EXTIn_IRQn". + - Add "GPIO2EXTI()" macro to map GPIO pin to EXTI Channel. + - Change "AFIO_EXTISourceConfig()" API, remove "AFIO_EXTI_CH_Enum" and "AFIO_ESS_Enum". + Old: void AFIO_EXTISourceConfig(AFIO_EXTI_CH_Enum AFIO_EXTI_CH_n, AFIO_ESS_Enum AFIO_ESS_Px) + New: void AFIO_EXTISourceConfig(u32 GPIO_PIN_NUM_n, u32 GPIO_Px) + + Others + + Update comment, format, typing error, and coding style. + + Update "ht32_op.s/.c", allow "Bootloader Waiting Time" function for all series. + + Update "CKCU/HSI_AutoTrim_By_USB" example, add the following define to "ht32_board_config.h". + - "CKCU_PLL_CFG" + - "CKCU_SYSCLK_DIV_CFG" + + Upgrade CMSIS to v5.9.0. + + Modify API parameter check macro of Library Debug Mode, fix parameter check error. + + Modify variable declaration of "PDMACH_InitTypeDef" to reduce memory size. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.2.1_2753 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-10-11 + + Main Changes + + Add new examples: + - "I2C/7_bit_mode_master" + - "I2C/7_bit_mode_slave" + + Add the following API for PDMA. + - "PDMA_DeInit()" + - "PDMA_AddrConfig()" + - "PDMA_SrcAddrConfig()" + - "PDMA_DstAddrConfig()" + - "PDMA_GetRemainBlkCnt()" + + Add the following API for ADC. + - "ADC_ChannelDataAlign()" + - "ADC_ChannelOffsetValue()" + - "ADC_ChannelOffsetCmd()" + + Update "ht32_retarget.c", modify the retarget related functions for SEGGER Embedded Studio. + + Update "FLASH_SetWaitState()" function, disable Pre-fetch and Branch Cache function before change + wait state. + + Update following middleware. + "utilities/middleware/i2c_master.c/h" + "utilities/middleware/uart_module.c" + + Others + + Update comment, format, typing error, and coding style. + + Update "BFTM/OneShot" example, fix the register access sequence and time calculation formula. + + Update "TM/PWM/main.c" + - Add "HTCFG_PWM_TM_RELOAD" check. + - Add PWM channel initial function. + - Remove "_ht32_project_source.h" (Use "_ProjectSource.ini" to add "pwm.c" into project compiling list). + + Fix the upper/lower case error of #include file name. + + Update e-Link32 Pro/Lite Command line tool as "V1.18" ("utilities/elink32pro/eLink32pro.exe"). + + Change the project recommended minimum version of SEGGER Embedded Studio from V4.12 to V6.20. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.1.1_2647 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-06-10 + + Main Changes + + Add following middleware. + "utilities/middleware/spi_module.c" + "utilities/middleware/spi_module.h" + "utilities/middleware/spi_module_config_templet.h" + + Fixed FW library compatibility with ARM compiler version 6 of MDK-ARM V5.37. + - Add MDK-ARMv537 project template for MDK-ARM V5.37. + - Update "project_template/Script". Those MDK-ARMv537 project templates will be added for use if choose + the target IDE is "Keil MDK-ARMv5". The fixed files are as follows: + "Script/_CreateProjectScript.bat" + "Script/_ProjectConfig.bat" + "Script/_ProjectSource.bat" + - Update "core_cm3.h", fix compiler error. + - Update "FMC/FLASH_OperationNoHalt", fix the compiler issue of Arm Compiler Version V6.18 and the + compiler warning of linker script file. The fixed files are as follows: + "FLASH_OperationNoHalt/main.c" + "FLASH_OperationNoHalt/linker.lin" + - Update following middleware, remove STRCAT3 usage to fix compiler error. + "utilities/middleware/uart_module.c" + "utilities/middleware/i2c_master.c" + "utilities/middleware/spi_module.c" + + Update "ht32_retarget.c". Implement __write function to fix compiler error in IAR EWARM Version 9.20 + or later. + + Update GNU Arm makefile in the project_template, fix the compatibility issue that the makefile of GNU Arm + Version 11 cannot be compiled. + + Update EWARM in the project_template, fix the compiler error that header file path doesn't exist in + the file list of Workspace of IAR EWARM Version 7. + + Fix SPI initial PDMA parameter in the "utilities/common/spi_flash.c". + + Sync M0+ I2C/EEPROM to fix compiler warning of the GNU compiler. + + Sync M0+ library\HT32F1xxxx_Driver\inc\ht32_dependency.h. + + Others + + Update comment, format, typing error, and coding style. + + Update e-Link32 Pro/Lite Command line tool as "V1.16" ("utilities/elink32pro/eLink32pro.exe"). + + Update the following examples to remove compiler warning of the IAR EWARM. + "BFTM\TimeMeasure" + "TM\PWMInput\ht32f1xxxx_01_it.c" + "USBD\HID_Keyboard_Virtual_COM\ht32_usbd_class.c" + "USBD\Mass_Storage_SDIO\sd_disk.c" + "USBD\USB_UAC_Sound\ht32_usbd_class.c" + "USBD\Virtual_COM\ht32_usbd_class.c" + + Update and sync create project related files ("_ProjectConfig.bat"、"_ProjectConfig.ini"). + + Update content of "project_template/IP/Example/readme.txt", add MDK-ARM V5.37 related information. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.0.10_2585 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-04-14 + + Main Changes + + Update EEPROM Basic and EEPROM Emulation middleware, fix the include and define sequence. + "utilities/middleware/eeprom_basic.h" + "utilities/middleware/eeprom_emulation.h" + + Update UART Module middleware, add the "UARTM_IsTxFinished()" API. + "utilities/middleware/uart_module.c" + "utilities/middleware/uart_module.h" + + Others + + Update e-Link32 Pro/Lite Command line tool as "V1.0.15" ("utilities/elink32pro/eLink32pro.exe"). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.0.10_2585 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-04-14 + + Main Changes + + Update EEPROM Basic and EEPROM Emulation middleware, fix the include and define sequence. + "utilities/middleware/eeprom_basic.h" + "utilities/middleware/eeprom_emulation.h" + + Update UART Module middleware, add the "UARTM_IsTxFinished()" API. + "utilities/middleware/uart_module.c" + "utilities/middleware/uart_module.h" + + Others + + Update e-Link32 Pro/Lite Command line tool as "V1.0.15" ("utilities/elink32pro/eLink32pro.exe"). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_V1.0.9_2556 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-03-15 + + Main Changes + + Change to the new Holtek version format (Vm.n.r). + + Add new "FMC/FLASH_OperationNoHalt" example. + + Modify "utilities/common/ring_buffer.c", fix the thread-safe issue of "Buffer_GetLength()". + + Update "GNU_ARM/linker.ld", fix the heap/stack area overlap problem. + + Add "ADC_SamplingTimeConfig()" function for the "ht32f1xxxx_adc_02.c". + + Others + + Update comment, format, typing error, and coding style. + + Modify "bool, TRUE, FALSE" define way for C++/.cpp applications. + + Update "startup_ht32fxxxxx_nn.s", support "USE_HT32_CHIP" define exist at startup.s and project Asm + setting in the same time (project's Asm Define has the higher priority). + + Remove unuse global variable "DelayTime" of "ebi_lcd.c" and "spi_lcd.c". + + Update "spi_lcd.c/.h", fix the GPIO Chip SEL define mistake. + + Add following middleware. + "utilities/middleware/uart_module.c" + "utilities/middleware/uart_module.h" + + Update related middleware (eeprom_basic and eeprom_emulation). + + Update e-Link32 Pro/Lite Command line tool as "V1.0.14" ("utilities/elink32pro/eLink32pro.exe"). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_v008_2470 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-08-19 + + Main Changes + + Add "ht32_time.c/.h" to support following new functions for delay, time measure, and timeout. + "Time_Init()" + "Time_Delay()" + "Time_GetTick()" + + Add new examples: + - "ADC/OneShot_SWTrigger_ByTM" + - "GPIO/Input" + - "GPIO/Output" + - "Time/TimeFun" + - "Time/TimeFun_UserConf" + - "USART/RS485_NMM_Slave" + + Add new definition, "FLASH_WAITSTATE_MAX". + + Add "USART_PARITY_MARK" and "USART_PARITY_SPACE" for the UART parity mode. + + Update "ADC_RegularTrigConfig()" and "AC_TRIG_XXXX" define to support all the trigger source of ADC. + + Add "CKCU_ADCPRE_DIV1" parameter of "CKCU_SetADCnPrescaler()" for the HT32F12364. + + Modified "SDIO_ClearFlag()", disable Status Enable Register (SER) to clear SDIO_FLAG_BUF_OVERFLOW and + SDIO_FLAG_BUF_UNDERFLOW. + + Fix the result mistake of the marco below of HT32F12364 (LIBCFG_FLASH_2PAGE_PER_WPBIT is missing). + "#define FLASH_WP_PAGE_SET(OP, PAGE)" + "#define FLASH_WP_PAGE_CLEAR(OP, PAGE)" + "#define FLASH_IS_WP_PAGE(OP, PAGE)" + + Update following example, modify the default value of "gIsINEmpty" from TRUE to FALSE. The default value + TRUE may cause the F/W to not send CSW after the first Inquiry CBW Command in a specific condition. + "example/USBD/HID_Keyboard_Mass_Storage" + "example/USBD/Mass_Storage" + "example/USBD/Mass_Storage_IAP" + "example/USBD/Mass_Storage_SDIO" + + Others + + Update comment, format, typing error, and coding style. + + Fix compile error when turn on Library debug mode (HT32_LIB_DEBUG = 1). + + Update e-Link32 Pro Commander to V1.10. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_v007_2414 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-05-11 + + Main Changes + + Add new examples: + - "EXTI/GPIO_Interrupt" + - "CKCU/HSI_AutoTrim_By_LSE" + + Update the IAP example of HT32F12364 project: + - IAR EWARM v6/v7/v8: + 1. Modify "startup_ht32f1xxxx_03.s" to "startup_ht32f1xxxx_iar_03.s". + 2. Modify "ht32f1xxxx_adc.c" to "ht32f1xxxx_adc_02.c". + - Keil MDK-ARM v4/v5: Modify "ht32f1xxxx_adc.c" to "ht32f1xxxx_adc_02.c". + + Fix the system stuck in CKCU_HSIAutoTrimCmd() because of the misjudgment of CKCU_HSIAutoTrimIsReady(). + + Fix the CHIP ID error. Fixed "USE_HT32_CHIP=3" to "USE_HT32_CHIP=16". The fixed files are as follows: + - IAP/IAP_Text_RAM/EWARM/Project_12364_IAP.ewp + - IAP/IAP_UI/EWARM/Project_12364_IAP.ewp + + Fix the syntax error on the "IAP/IAP_Text_RAM/EWARM/startup_ht32f1xxxx_iar_03_iap.s". + + Others + + Update comment, format, typing error, and coding style. + + Update the version of eLink32pro.exe to 1.0.1.1. + + Update the following project setting: + - IAR EWARM v6/v7: Modify "_ht32_project_source.c" to "_ht32_project_source.h". + - SEGGER Embedded Studio: Add the new definition "arm_compiler_variant="SEGGER"". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_1xxxx_FWLib_v006_2361 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-02-26 + + Main Changes + + Add "Create Project Configuration Menu" to choose the target IDE and Device when the first time to do the + create project operation of the example. The configuration file, "_CreateProjectConfig.bat" is saved to + the root path of the HT32 Firmware Library. You can reset the create project IDE/IC configuration anytime + by deleting the configuration file. + Target IDE/Compiler: + - Keil MDK-ARM v5 + - Keil MDK-ARM v4 + - IAR EWARM v8 + - IAR EWARM v6/v7 + - SEGGER Embedded Studio + - GNU [with Keil and GNU make] + - SourceryG++Lite [with Keil] + Target Device: + - xxxxx: Single Device + - xxx*: Series + + Add new examples: + - "NVIC/Disable_Interrupt" + - "TM/InternalTrigger" + - "TM/PWM_Buzzer" + - "WDT/Auto_Enable" + + Add Flash programming function of GNU Maker (via e-Link32 Pro/Lite Commander). + "make IC=xxxxx eraseall" + "make IC=xxxxx program" + "make IC=xxxxx run" + + Update "CKCU_HSIAutoTrimCmd()" and "CKCU_HSIAutoTrimIsReady()" function to improve clock stability. + + Fix the cache address problem of "SDDISK_Read()" function. + "USBD/Mass_Storage/sd_disk.c", "USBD/Mass_Storage_SDIO/sd_disk.c" + + Update GNU project (*.uvprojx), fix the compile error when use new GNU Arm version + ("gcc-arm-none-eabi-10-2020-q2-preview-win32" or above). + + Fix Keil compiling error when disable both retarget and MicroLib. + + Update "ht32f1xxxx_01.h", fix the compatibility issue when user include "stdbool.h". + + Modify GNU compiler settings, output text file (disassembly) after building the code. + + Add "HT32_FWLIB_VER" and "HT32_FWLIB_SVN" in "ht32f1xxxx_lib.h" for the version information of + HT32 Firmware Library. + Example: + "#define HT32_FWLIB_VER (006)" + "#define HT32_FWLIB_VER (2361)" + + Add new AFIO define in "ht32f1xxxx_gpio.h". + - "AFIO_FUN_MCTM1" + - "AFIO_FUN_PWM" + - "AFIO_FUN_PWM0", "AFIO_FUN_PWM1", "AFIO_FUN_PWM2", "AFIO_FUN_PWM3" + + Add following alias of MCTM IRQ handler + "#define MCTM0_IRQn MCTM0UP_IRQn" + "#define MCTM0_IRQHandler MCTM0UP_IRQHandler" + "#define MCTM1_IRQn MCTM1UP_IRQn" + "#define MCTM1_IRQHandler MCTM1UP_IRQHandler" + + Others + + Update comment, format, typing error, and coding style. + + Update "SPI/FIFO_SEL_Hardware" example, add Rx FIFO Timeout function and fix data loss issue. + + Update "USBD/Mass_Storage" example, add "HTCFG_SD_MAXSPEED" define for different board. + + Update "utilities/common/spi_lcd.c". + - Remove duplicate SPI parameter setting of "LCD_Init()". + - Update SPI chip select define and SPI configuration by "LCD_SPI_SEL_AFIO_MODE". + - Swap the "GPIO_DirectionConfig()" and "GPIO_SetOutBits()" function to prevent transient state + of SPI_SEL pin. + + Update "_ProjectConfig*.bat" files. + + Add "Project Source File Setting" functions ("_ProjectSource.ini" and "_ProjectSource.bat"). + + Rename "_CreateProjectUSB.bat" as "_CreateProject.bat". + + Add dummy xxTM C files, to notify the user that SCTM/PWM/GPTM/MCTM timer use the "ht32f1xxxx_tm.c" driver. + "ht32f1xxxx_gptm.c", "ht32f1xxxx_pwm.c", "ht32f1xxxx_sctm.c" + + Add "IS_IPN_MCTM()" and "IS_IPN_GPTM" macro, for use to confirm the xxTMn is GPTM or MCTM. + + Update comment and board/pin configuration of "ADC/OneShot_TMTrigger_PDMA" example. + + Update and sync startup.s/system.c files. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v005_2207 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2020-08-11 + + Main Changes + + Add the following files to use e-Link32 Pro with SEGGER Embedded Studio. Refer to the + "readme e-Link32 Pro.txt" for how to use it. + "emStudiov4/readme e-Link32 Pro.txt" + "emStudiov4/Project_xxxxx.bat" + "emStudiov4/_MassErase.bat" + + Fix the "I2S_FIFOTrigLevelConfig()" error which did not clear the field of I2S FCR correctly. + + Fix "RPRE_MASK" define error for "RTC_SetPrescaler()" function. + + Add "SPI_FLASH_WaitForWriteEnd()" function in the end of the write status operation + ("SPI_FLASH_WriteStatus()"). + + Modify "SPI_FLASH_WaitForWriteEnd()" function to return value of status register. + + Add below notice of examples to inform the user to check the local structure variable without a + default value. + "Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below this function." + + Add "LIBCFG_MAX_SPEED" in the file "ht32fxxxxx_libcfg.h" which indicate the maximum core speed. + + Add the following definition for convenience. + PDMACH0_IRQn ~ PDMACH5_IRQn + AFIO_FUN_MCTM0 + AFIO_FUN_GPTM0 ~ AFIO_FUN_GPTM3 + AFIO_FUN_PWM0 + AFIO_FUN_SCTM0 ~ AFIO_FUN_SCTM2 + + Add new examples. + "TM/PWM" + "TM/UpdateEvent" + + Add "s64/u64" definition. + + Others + + Update comment, format, typing error, and coding style. + + Add below notice in the "FMC/FLASH_Security" example. + "The Option Byte will be write protected (cannot be changed again) after the + Security Protection is enabled. Refer to the user manual for details." + + Remove HSI disable setting of Configuration Wizard and add notice in the "system_xxxxx_nn.c". + + Update the following examples to remove compiler warning of the GNU compiler. + "USBD/Mass_Storage" + "USART/PDMA" + "USART/Interrupt" + + Add "-Waddress-of-packed-member" #pragma of below examples to remove compiler warning of the + GNU compiler. + "USBD/Mass_Storage" + "USBD/Mass_Storage_IAP" + "USBD/Mass_Storage_SDIO" + "USBD/HID_Keyboard" + "USBD/HID_Keyboard_Joystick" + "USBD/HID_Keyboard_Mass_Storage" + "USBD/HID_Keyboard_Virtual_COM" + "USBD/HID_Mouse" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v004_2103 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2020-04-25 + + Main Changes + + Remove the "I2C_Cmd()" in the "I2C_Init()" function since it shall be called after the I2C related + settings. User shall call the "I2C_Cmd()" by themself after the "I2C_Init()". + + Update "system_ht32f1xxxx_02.c", modify the LDO related setting. + + Add "USART_GetIntStatus()" function to get the enabled interrupt source. + + Add "RETARGET_HSI_ATM" setting to turn on/off the auto-trim function of HSI ("ht32f1xxxx_conf.h"). + + Add "USBDClass_Reset()" into the "USBD/*" example to reset related flag for the self-power application. + + Modify "ht32f5xxxx_aes.c", fix "AES_SetKeyTable()" and "_AES_CryptData()" functions who did not clear + related fields before set it. + + Rename examples as below. + IP Old Name New Name + -------- -------- -------- + ADC EXTITrigger_DiscontinuousMode Discontinuous_EXTITrigger + ADC PDMA_ADCResult OneShot_TMTrigger_PDMA + ADC Potentiometer_ContinuousMode Continuous_Potentiometer + ADC TM_Trigger OneShot_PWMTrigger + ADC TM_Trigger_with_Delay OneShot_PWMTrigger_with_Delay + USART HyperTerminal_TxRx Retarget + USART HyperTerminal_TxRx_Interrupt Interrupt + USART HyperTerminal_TxRx_Interrupt_FIFO Interrupt_FIFO + + Update the following example to improve readability. + "ADC/AnalogWatchdog" + "ADC/Continuous_Potentiometer" + "ADC/Discontinuous_EXTITrigger" + "ADC/InternalReferenceVoltage" + "ADC/OneShot_PWMTrigger" + "ADC/OneShot_PWMTrigger_with_Delay" + "ADC/OneShot_TMTrigger_PDMA" + "ADC/Two_Group_MaxCH" + "USART/Interrupt" + "USART/Interrupt_FIFO" + "USART/PDMA" + "USART/Polling" + "USART/Retarget" + "USBD/HID_Demo" + "USBD/HID_DemoVendorReport" + + Update UxART related example, turn on internal pull up to prevent unknown state. + + Add new examples. + "BFTM/OneShot" + "BFTM/TimeMeasure" + + Remove unnecessary RTC compare match restart setting of the RTC example + (which cause the time not correct after entering the low power mode). + + ADC to ADC0 related modification (to compatible with M0+ and ADC1). + Modify "HT_ADC" and "ADC_IRQn" to "HT_ADC0" and "ADC0_IRQn". + Modify "AFIO_FUN_ADC" as "AFIO_FUN_ADC0". + Modify "CKCU_SetADCPrescaler()" to "CKCU_SetADCnPrescaler()". + Add "CKCU_ADCPRE_ADCn_TypeDef". + Modify "ADC_Freq" to "ADC0_Freq" of "CKCU_ClocksTypeDef". + Modify "ADC" to "ADC0" of "RSTCU_PeripReset_TypeDef". + Add "HT_ADC", "ADC_IRQn", "AFIO_FUN_ADC" define for backward compatibility. + + Fix "HT_GPIOF" define error of HT32F12364. + + Others + + Update "SPI/FIFO_SEL_Hardware" example, change the code location of the IP enable ("SPI_Cmd()"). + + Update "system_ht32fxxxxx_nn.c" (coding style). + + Update "ht32_series.c/h" and "ht32_retarget_usbdconf.h" to improve the compatibly of the + terminal software. + + Update comment, format, typing error, and coding style. + + Fix interrupt mode of UxART retarget, remove unnecessary FIFO/interrupt configuration of the + retarget function. + + Update format of "CKCU_PeripClockConfig_TypeDef" and "RSTCU_PeripReset_TypeDef". + + Update and modify naming rule of the "HTCFG_xxxx" configuration define in the "ht32_board_config.h". + + Update settings of project files. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v004_1946 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-11-28 + + Main Changes + + Move the "common/*.h" include from the begin to the end (after the pin define) in the file + "HT32_Board/ht32fxxxx_sk/dvb.h". The original include way leads to the pin define lost when you + use the EBI_LCD->EBI_LCD_RAM outside the "ebi_lcd.c". + + Fix error of "_CreateProjectScript.bat" which cause the stack size and RW base can not be set by the + "_ProjectConfig.bat" of the emStudiov4 project. + + Add "GPIO_GetID()" function to convert HT_GPIOx to GPIO_Px. + + Update "HID_Demo_UI.exe" to support HID Report ID. + + Add "USBD/HID_DemoVendorReport" example. + + Modify "SPI_Init()" function, fix SPIx Clock Prescaler setting of HT32F12364. + + Modify "system_ht32f1xxxx_03.c", fix PLLCFGR initiation error which cause the "PLL_CLK_SRC_DIV" setting + is not work. + + Add "RETARGET_UxART_BAUDRATE" setting to change the retarget UART baudrate in "ht32f1xxxx_conf.h". + + Add "RETARGET_HSI_ATM" setting to turn on/off the auto-trim function of HSI. + + Add "RETARGET_DEFINE_HANDLER" setting to remove the UxARTn_IRQHandler() define of the retarget. + This setting is used for the model who grouping two UART Interrupt into one vector. + + Add non-block mode of USB Virtual-COM retarget function ((Drop data if USB or terminal software is + not ready). + + Modify "PWRCU_SetLDOFTRM()" function, fix the error which cause the LDO output voltage fine trim is + not work. + + Update "PWRCU_DeepSleep2()" to restore the LDO output voltage fine trim after system wakeup. + + Add SWCLK toggle of "GPIO_DisableDebugPort()" function. + + Others + + Add "utilities/common/lcd.h" to put the lcd related register together. + + Update format and coding style. + + Add PLL Output frequency comment of "system_ht32f1xxxx_nn.c". + + Update project files. + .c and .h files order. + Project format. + Include path order. + + Add "USAGE_PAGE_L" define of "USB/HID_Demo" example. + + Fix typing error of "ht32f1xxxx_conf.h". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v004_1812 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-09-11 + + Main Changes + + Add new device support. + HT32F12364 + + Update "ebi_lcd.c/h", fix LCD_SPI_BL_GPIO_XXX define error (shall be LCD_EBI_BL_GPIO_XXX). + + Update USB example, use USB PLL by default (if USB PLL exist). + + Fix function name typing error + SPI_GUADTCmd() -> SPI_GUARDTCmd() + SPI_GUADTConfig -> SPI_GUARDTConfig() + + Update "ADC_RegularGroupConfig()" and "ADC_HPGroupConfig()", prevent to enable the ADC directly after + the above function call. User shall use the "ADC_Cmd(HT_ADC, ENABLE);" to enable the ADC. + + Rename following files. + "IAR/startup_ht32f1xxxx_01.s" to "IARstartup_ht32f1xxxx_iar_01.s" + "IAR/startup_ht32f1xxxx_03.s" to "IARstartup_ht32f1xxxx_iar_03.s" + + Others + + Update comment and coding style. + + Update "USART/HyperTerminal_TxRx_Interrupt" example, remove unnecessary configuration of LED. + + Update readme file of "EBI/LCD" example. + + Add "PWRCU/PowerDown_RTC" example. + + Add "PWRCU/PWRCU_PowerDown_WAKEUPPin" example. + + Add "RTC/Time" example. + + Update and sync "ht32f1xxxx_conf.h". + + Update and sync "HT32F1xxxx_01_DebugSupport.ini". + + Update "ht32f1xxxx_tm.c", remove unnecessary variable initialization. + + Update "ht32_op.c" and "ht32_op.s", edit comment of WDT Enable function. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v003_1679 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-04-19 + + Main Changes + + Fix error of "CKCU_HSIAutoTrimClkConfig()" function which cause the HSI auto-trim not work. + + Modify following define of ADC. + ADC_CH_GNDREF -> ADC_CH_GND_VREF + ADC_CH_VREF -> ADC_CH_VDD_VREF + + Others + + None. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v003_1673 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-04-09 + + Main Changes + + Add SEGGER Embedded Studio IDE support (beta version). + + Update "ht32f1xxxx_usbd.c" and "ht32_usbd_core.c", add Force USB Reset Control function (apply to specific + model only). + + Update Create Project script, add Script folder in project_template. + + Add "TM/TriggerCounter" example. + + Add "USBD/HID_Keyboard_Mass_Storage" example. + + Others + + Update comment of example code. + + Update define of "USBD/Mass_Storage" example. + + Update "EXTI/WakeUp_DeepSleepMode1" Example, add LED3 (for some SK have only LED2 and LED3 on board). + + Update/sync startup.s/system.c files. + + Update/sync "HT32F1xxxx_01_DebugSupport.ini". + + Update/sync "ht32_op.s" and "ht32_op.c". + + Update "BootProcess" function. + + Update/sync "FlashMacro.mac". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v002_1496 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-12-17 + + Main Changes + + Modify Control IN/OUT method of USB Core, to fix USB transfer problem when CPU in the lower speed or late + USB interrupt case. + + Add workaround for PDMA CH3 issue (Interrupt Enable bit of CH3 is not work). + + Others + + Add "USBD_DisableDefaultPull()" function to disable pull resistance when the USB is not use. + + Rename RTC example as below. + "Calendar" -> "Time_BackupDomain" + + Add new example. + "RTC/Calendar_BackupDomain" + "FMC/EnableProtectionByFW" + + Update "EXTI/WakeUp_DeepSleepMode1" example. + + Update coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v002_1406 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-09-30 + + Main Changes + + Update HardFault_Handler of "ht32f1xxxx_01_it.c",add the debug instruction and system reset. + + Add "RAND/Random_Number" example and update "ht32_rand.c". + + Add "__HT_check_sp" and "__HT_check_heap" symbol into startup.s and watchpoint command into + "HT32F1xxxx_01_DebugSupport.ini" for debug stack/heap underflow, overflow, and overwrite. + + Update "USBD/HID_Keyboard_Joystick" and "USBD/HID_Mouse" example, change the set flag sequence + (before USBDCore_EPTWriteINData). + + Add GNU Make support of GNU Arm compiler. + + Others + + Add "objcooy.txt" which shows how to use obj tools of GNU Arm compiler. + + Update format and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v002_1367 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-08-02 + + Main Changes + + Add GNU Arm compiler support. + - Add project_template related files + - "startup_ht32f5xxxx_gcc_nn.s" + - "linker.ld" (link script) + + Update "ht32f5xxxx_tm.c/.h", add following functions which have TM_CH_n parameter. + void TM_ForcedOREF(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, TM_OM_Enum ForcedAction) + void TM_SetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) + void TM_SetAsymmetricCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) + u32 TM_GetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n) + + Others + + Add "USBD/HID_Keyboard_Virtual_COM" example. + + Fix compile error when turn on Library debug mode (HT32_LIB_DEBUG = 1). + + Modify "example/NVIC/Vector_Table_Offset" example code to support GUN compiler. + + Simplify "example/USART/HyperTerminal_TxRx_Interrupt" example. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_1302 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-06-11 + + Main Changes + + Add SourceryG++Lite compiler support. + - Add project_template related files + - "startup_ht32f1xxxx_cs3_nn.s" + - "linker.ld" (link script) + + Add DMA support of "utilities/common/spi_flash.c". + + Add "EXTI_GetEdgeFlag()" function. + + Add LIBCFG_AES_SWAP function to process endian issue of AES. + + Others + + Update "ht32f1xxxx_conf.h" for AUTO_RETURN (\r) option. + + Update format of IAR "startup_ht32f1xxxx_01.s". + + Fix "LIBCFC_CKCU_USB_PLL" typing error of ht32fxxxx_libcfg.h and example code (shall be LIBCFG_CKCU_USB_PLL). + + Fix IAP_PPBIT define error of "IAP/IAP_UI" example. + + Update "ht32f1xxxx_ckcu.c" to remove unnecessary register write of PLL. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_1153 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-02-28 + + Main Changes + + Add "USBD/USB_UAC_Sound_RateControl" Example. + + Add "I2C_SpeedOffset" parameter of I2C_InitTypeDef to reach real I2C speed. + Note: Related examples are also updated. + + Change EBI timing of "ebi_lcd.c" to fix LCD display problem on HT32F12345 with ESK32-A2A31. + + Add "CKCU/HSI_AutoTrim_By_USB" Example. + + Update "CKCU_HSIAutoTrimIsReady" function of "ht32f5xxxx_ckcu.c". + + Others + + Update format and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_1023 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-12-30 + + Main Changes + + Update boot related functions of "startup_ht32f1xxxx_nn.s" and "system_ht32f1xxxx_nn.c". + + Update "ht32_op.c" and "ht32_op.s" to support enable WDT function by Flash Option byte (Apply to specific + model only). + + Add "GPIO_DisableDebugPort()"" function to disable SWD function. + + Others + + Fix IAR Project setting error of IAP Example. + + Add "RTC_LSILoadTrimData()" function. + + Add "LIBCFG_RTC_LSI_LOAD_TRIM" define of HT32F165x. + + Remove useless "RTC_LSICmd()"" function. + + Update following examples, remove LSI enable code (LSI default on). + "PWRCU/DeepSleepMode1" + "PWRCU/BackupData" + "PWRCU/DeepSleepMode2" + "PWRCU/PowerDownMode" + "RTC/Calendar" + + Update I2S and USB UAC related examples (Coding style and remove unuse define). + + Update USB Example, remove invalid remote wakeup configuration by define (Only HID class support Remote + Wakeup). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_933 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-11-17 + + Main Changes + + Fix AES typing error of "ht32f1xxxx_aes.c/.h" (EBC to ECB). + + Fix TM define error of "ht32f1xxxx_tm.c/.h". + + Others + + Update "ht32_virtual_com.inf" file, add Digital Signature. + + Update typing error of example code. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_899 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-10-19 + + Main Changes + + Update "SDIO/SDCard" Example code. Fix read Card SCR problem which causes SDIO working on 1-bit mode + abnormally. + + Others + + Update project setting. + + Remove some project files. Use "CreateProject.bat" to copy project files automatically. + + Add "LIBCFG_CHIPNAME" define. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_785 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-08-31 + + Main Changes + + Fix "ht32f1xxxx_conf.h" typing error ("_ADC" to "_AES"). + + Fix AES typing error (EBC to ECB). + + Others + + Update "ht32_usbd_core.c" to support vendor function. + + Add "USE_MEM_HT32F1xxxx" define into project. + + Add "USE_MEM_HT32F1xxxx" default define into "ht32f1xxxx_xx_libcfg.h". + + Rename "system_ht32f1xxxx.h" to "system_ht32f1xxxx_01.h" for PACK requirement. + + Update IAP examples. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_671 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-07-27 + + Main Changes + + None + + Others + + Update "ht32_op.c", add CK_CODE/CK_DATA/CK_CODEOP in Option Bytes (same format with e-Writer32). + + Modify USB/Mass_Storage example for WIN10 compatibility issue. + + Add "USE_MEM_HT32F1xxxx" support for memory size define (LIBCFG_FLASH_SIZE/LIBCFG_RAM_SIZE). + + Add IAR EWARMv8 project template (create by IAR EWARM v8.11). + + Upgrade the version of IAR EWARM project template from v6.20 to v6.50. + Note: + 1. Supported CMSIS-DAP: IAR EWARM v6.50 and above. + 2. RDI/e-Link32 is not supported anymore from the v8.xx of IAR EWARM. + + Known Issue: + + IAP example is not ready, will be update in next release. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_552 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-07-17 + + Main Changes + + Add example code. + + Update TM for PDMA support. + + Fix "USART_RXTL_01/04/08/14" define error. + + Fix "HT32F_DVB_BuzzerFun()" define error of "ht32f1xxxx_board_01.c". + + Fix pin assignment error of "ht32f12366_sk.h" + + Others + + Add BUTTON_MODE_WAKE_UP support for "ht32f1xxxx_sk.c/.h". + + Update typing error and coding style. + + Remove warning on old MDK-ARM version. + + Update project setting. + + Add DEINIT_ENABLE setting of "ht32f1xxxx_system_nn.c". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F1xxxx_FWLib_v001_167 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-06-14 + + Main Changes + + Initial version. + + Others + + diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/SConscript b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/SConscript new file mode 100644 index 00000000000..bae7234da69 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/SConscript @@ -0,0 +1,48 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() + +src = Split(""" + library/HT32F1xxxx_Driver/src/ht32_cm3_misc.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_adc.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_aes.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_bftm.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_ckcu.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_cmp.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_crc.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_ebi.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_exti.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_flash.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_gpio.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2c.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2s.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_mctm.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_pdma.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_pwrcu.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_rstcu.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_rtc.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_sci.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_sdio.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_spi.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_tm.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_usart.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_usbd.c + library/HT32F1xxxx_Driver/src/ht32f1xxxx_wdt.c + + library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_02.c +""") +#HT32F1xxxx_Driver/src/ht32f1xxxx_csif.c + +path = [ + cwd + '/library/HT32F1xxxx_Driver/inc', + cwd + '/library/CMSIS/Include', + cwd + '/library/Device/Holtek/HT32F1xxxx/Include' +] + +CPPDEFINES = ['USE_HT32_DRIVER'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') + diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/ARM.CMSIS.pdsc b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/ARM.CMSIS.pdsc new file mode 100644 index 00000000000..96775d502ae --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/ARM.CMSIS.pdsc @@ -0,0 +1,3271 @@ + + + + CMSIS + CMSIS (Common Microcontroller Software Interface Standard) + ARM + + http://www.keil.com/pack/ + + + + CMSIS-Core(M): 5.6.0 + - Arm Cortex-M85 cpu support + - Arm China STAR-MC1 cpu support + - Updated system_ARMCM55.c + CMSIS-DSP: 1.10.0 (see revision history for details) + CMSIS-NN: 3.1.0 (see revision history for details) + - Support for int16 convolution and fully connected for reference implementation + - Support for DSP extension optimization for int16 convolution and fully connected + - Support dilation for int8 convolution + - Support dilation for int8 depthwise convolution + - Support for int16 depthwise conv for reference implementation including dilation + - Support for int16 average and max pooling for reference implementation + - Support for elementwise add and mul int16 scalar version + - Support for softmax int16 scalar version + - Support for SVDF with 8 bit state tensor + CMSIS-RTOS2: 2.1.3 (unchanged) + - RTX 5.5.4 (see revision history for details) + CMSIS-Pack: deprecated (moved to Open-CMSIS-Pack) + CMSIS-SVD: 1.3.9 (see revision history for details) + CMSIS-DAP: 2.1.1 (see revision history for details) + - Allow default clock frequency to use fast clock mode + Devices + - Support for Cortex-M85 + Utilities + - SVDConv 3.3.42 + - PackChk 1.3.95 + + + CMSIS-Core(M): 5.5.0 (see revision history for details) + - Updated GCC LinkerDescription, GCC Assembler startup + - Added Armv8-M Stack Sealing (to linker, startup) for toolchain ARM, GCC + - Changed C-Startup to default Startup. + - Updated Armv8-M Assembler startup to use GAS syntax + Note: Updating existing projects may need manual user interaction! + CMSIS-Core(A): 1.2.1 (see revision history for details) + - Bugfixes for Cortex-A32 + CMSIS-DAP: 2.1.0 (see revision history for details) + - Enhanced DAP_Info + - Added extra UART support + CMSIS-DSP: 1.9.0 (see revision history for details) + - Purged pre-built libs from Git + - Enhanced support for f16 datatype + - Fixed couple of GCC issues + CMSIS-NN: 3.0.0 (see revision history for details including version 2.0.0) + - Major interface change for functions compatible with TensorFlow Lite for Microcontroller + - Added optimization for SVDF kernel + - Improved MVE performance for fully Connected and max pool operator + - NULL bias support for fully connected operator in non-MVE case(Can affect performance) + - Expanded existing unit test suite along with support for FVP + - Removed Examples folder + CMSIS-RTOS2: + - RTX 5.5.3 (see revision history for details) + - CVE-2021-27431 vulnerability mitigation. + - Enhanced stack overrun checking. + - Various bug fixes and improvements. + CMSIS-Pack: 1.7.2 (see revision history for details) + - Support for Microchip XC32 compiler + - Support for Custom Datapath Extension + + + CMSIS-Build: 0.9.0 (beta) + - Draft for CMSIS Project description (CPRJ) + CMSIS-Core(M): 5.4.0 (see revision history for details) + - Cortex-M55 cpu support + - Enhanced MVE support for Armv8.1-MML + - Fixed device config define checks. + - L1 Cache functions for Armv7-M and later + CMSIS-Core(A): 1.2.0 (see revision history for details) + - Fixed GIC_SetPendingIRQ to use GICD_SGIR + - Added missing DSP intrinsics + - Reworked assembly intrinsics: volatile, barriers and clobber + CMSIS-DSP: 1.8.0 (see revision history for details) + - Added new functions and function groups + - Added MVE support + CMSIS-NN: 1.3.0 (see revision history for details) + - Added MVE support + - Further optimizations for kernels using DSP extension + CMSIS-RTOS2: + - RTX 5.5.2 (see revision history for details) + CMSIS-Driver: 2.8.0 + - Added VIO API 0.1.0 (Preview) + - removed volatile from status related typedefs in APIs + - enhanced WiFi Interface API with support for polling Socket Receive/Send + CMSIS-Pack: 1.6.3 (see revision history for details) + - deprecating all types specific to cpdsc format. Cpdsc is replaced by Cprj with dedicated schema. + Devices: + - ARMCM55 device + - ARMv81MML startup code recognizing __MVE_USED macro + - Refactored vector table references for all Cortex-M devices + - Reworked ARMCM* C-StartUp files. + - Include L1 Cache functions in ARMv8MML/ARMv81MML devices + Utilities: + Attention: Linux binaries moved to Linux64 folder! + - SVDConv 3.3.35 + - PackChk 1.3.89 + + + CMSIS-Core(M): 5.3.0 (see revision history for details) + - Added provisions for compiler-independent C startup code. + CMSIS-Core(A): 1.1.4 (see revision history for details) + - Fixed __FPU_Enable. + CMSIS-DSP: 1.7.0 (see revision history for details) + - New Neon versions of f32 functions + - Python wrapper + - Preliminary cmake build + - Compilation flags for FFTs + - Changes to arm_math.h + CMSIS-NN: 1.2.0 (see revision history for details) + - New function for depthwise convolution with asymmetric quantization. + - New support functions for requantization. + CMSIS-RTOS: + - RTX 4.82.0 (updated provisions for Arm Compiler 6 when using Cortex-M0/M0+) + CMSIS-RTOS2: + - RTX 5.5.1 (see revision history for details) + CMSIS-Driver: 2.7.1 + - WiFi Interface API 1.0.0 + Devices: + - Generalized C startup code for all Cortex-M family devices. + - Updated Cortex-A default memory regions and MMU configurations + - Moved Cortex-A memory and system config files to avoid include path issues + + + The following folders are deprecated + - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) + + CMSIS-Core(M): 5.2.1 (see revision history for details) + - Fixed compilation issue in cmsis_armclang_ltm.h + + + The following folders have been removed: + - CMSIS/Lib/ (superseded by CMSIS/DSP/Lib/) + - CMSIS/DSP_Lib/ (superseded by CMSIS/DSP/) + The following folders are deprecated + - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) + + CMSIS-Core(M): 5.2.0 (see revision history for details) + - Reworked Stack/Heap configuration for ARM startup files. + - Added Cortex-M35P device support. + - Added generic Armv8.1-M Mainline device support. + CMSIS-Core(A): 1.1.3 (see revision history for details) + CMSIS-DSP: 1.6.0 (see revision history for details) + - reworked DSP library source files + - reworked DSP library documentation + - Changed DSP folder structure + - moved DSP libraries to folder ./DSP/Lib + - ARM DSP Libraries are built with ARMCLANG + - Added DSP Libraries Source variant + CMSIS-RTOS2: + - RTX 5.5.0 (see revision history for details) + CMSIS-Driver: 2.7.0 + - Added WiFi Interface API 1.0.0-beta + - Added components for project specific driver implementations + CMSIS-Pack: 1.6.0 (see revision history for details) + Devices: + - Added Cortex-M35P and ARMv81MML device templates. + - Fixed C-Startup Code for GCC (aligned with other compilers) + Utilities: + - SVDConv 3.3.25 + - PackChk 1.3.82 + + + Aligned pack structure with repository. + The following folders are deprecated: + - CMSIS/Include/ + - CMSIS/DSP_Lib/ + + CMSIS-Core(M): 5.1.2 (see revision history for details) + - Added Cortex-M1 support (beta). + CMSIS-Core(A): 1.1.2 (see revision history for details) + CMSIS-NN: 1.1.0 + - Added new math functions. + CMSIS-RTOS2: + - API 2.1.3 (see revision history for details) + - RTX 5.4.0 (see revision history for details) + * Updated exception handling on Cortex-A + CMSIS-Driver: + - Flash Driver API V2.2.0 + Utilities: + - SVDConv 3.3.21 + - PackChk 1.3.71 + + + Updated Arm company brand. + CMSIS-Core(M): 5.1.1 (see revision history for details) + CMSIS-Core(A): 1.1.1 (see revision history for details) + CMSIS-DAP: 2.0.0 (see revision history for details) + CMSIS-NN: 1.0.0 + - Initial contribution of the bare metal Neural Network Library. + CMSIS-RTOS2: + - RTX 5.3.0 (see revision history for details) + - OS Tick API 1.0.1 + + + CMSIS-Core(M): 5.1.0 (see revision history for details) + - Added MPU Functions for ARMv8-M for Cortex-M23/M33. + - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler. + CMSIS-Core(A): 1.1.0 (see revision history for details) + - Added compiler_iccarm.h. + - Added additional access functions for physical timer. + CMSIS-DAP: 1.2.0 (see revision history for details) + CMSIS-DSP: 1.5.2 (see revision history for details) + CMSIS-Driver: 2.6.0 (see revision history for details) + - CAN Driver API V1.2.0 + - NAND Driver API V2.3.0 + CMSIS-RTOS: + - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata. + CMSIS-RTOS2: + - API 2.1.2 (see revision history for details) + - RTX 5.2.3 (see revision history for details) + Devices: + - Added GCC startup and linker script for Cortex-A9. + - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU. + - Added IAR startup code for Cortex-A9 + + + CMSIS-RTOS2: + - RTX 5.2.1 (see revision history for details) + + + CMSIS-Core(M): 5.0.2 (see revision history for details) + - Changed Version Control macros to be core agnostic. + - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7. + CMSIS-Core(A): 1.0.0 (see revision history for details) + - Initial release + - IRQ Controller API 1.0.0 + CMSIS-Driver: 2.05 (see revision history for details) + - All typedefs related to status have been made volatile. + CMSIS-RTOS2: + - API 2.1.1 (see revision history for details) + - RTX 5.2.0 (see revision history for details) + - OS Tick API 1.0.0 + CMSIS-DSP: 1.5.2 (see revision history for details) + - Fixed GNU Compiler specific diagnostics. + CMSIS-Pack: 1.5.0 (see revision history for details) + - added System Description File (*.SDF) Format + CMSIS-Zone: 0.0.1 (Preview) + - Initial specification draft + + + Package Description: + - added taxonomy for Cclass RTOS + CMSIS-RTOS2: + - API 2.1 (see revision history for details) + - RTX 5.1.0 (see revision history for details) + CMSIS-Core: 5.0.1 (see revision history for details) + - Added __PACKED_STRUCT macro + - Added uVisior support + - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__ + - Updated template for secure main function (main_s.c) + - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c) + CMSIS-DSP: 1.5.1 (see revision history for details) + - added ARMv8M DSP libraries. + CMSIS-Pack:1.4.9 (see revision history for details) + - added Pack Index File specification and schema file + + + Changed open source license to Apache 2.0 + CMSIS_Core: + - Added support for Cortex-M23 and Cortex-M33. + - Added ARMv8-M device configurations for mainline and baseline. + - Added CMSE support and thread context management for TrustZone for ARMv8-M + - Added cmsis_compiler.h to unify compiler behaviour. + - Updated function SCB_EnableICache (for Cortex-M7). + - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType + CMSIS-RTOS: + - bug fix in RTX 4.82 (see revision history for details) + CMSIS-RTOS2: + - new API including compatibility layer to CMSIS-RTOS + - reference implementation based on RTX5 + - supports all Cortex-M variants including TrustZone for ARMv8-M + CMSIS-SVD: + - reworked SVD format documentation + - removed SVD file database documentation as SVD files are distributed in packs + - updated SVDConv for Win32 and Linux + CMSIS-DSP: + - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib. + - Added DSP libraries build projects to CMSIS pack. + + + - CMSIS-Core 4.30.0 (see revision history for details) + - CMSIS-DAP 1.1.0 (unchanged) + - CMSIS-Driver 2.04.0 (see revision history for details) + - CMSIS-DSP 1.4.7 (no source code change [still labeled 1.4.5], see revision history for details) + - CMSIS-Pack 1.4.1 (see revision history for details) + - CMSIS-RTOS 4.80.0 Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details) + - CMSIS-SVD 1.3.1 (see revision history for details) + + + - CMSIS-Core 4.20 (see revision history for details) + - CMSIS-DSP 1.4.6 (no source code change [still labeled 1.4.5], see revision history for details) + - CMSIS-Pack 1.4.0 (adding memory attributes, algorithm style) + - CMSIS-Driver 2.03.0 (adding CAN [Controller Area Network] API) + - CMSIS-RTOS + -- API 1.02 (unchanged) + -- RTX 4.79 (see revision history for details) + - CMSIS-SVD 1.3.0 (see revision history for details) + - CMSIS-DAP 1.1.0 (extended with SWO support) + + + - CMSIS-Core 4.10 (Cortex-M7 extended Cache Maintenance functions) + - CMSIS-DSP 1.4.5 (see revision history for details) + - CMSIS-Driver 2.02 (adding SAI (Serial Audio Interface) API) + - CMSIS-Pack 1.3.3 (Semantic Versioning, Generator extensions) + - CMSIS-RTOS + -- API 1.02 (unchanged) + -- RTX 4.78 (see revision history for details) + - CMSIS-SVD 1.2 (unchanged) + + + Adding Cortex-M7 support + - CMSIS-Core 4.00 (Cortex-M7 support, corrected C++ include guards in core header files) + - CMSIS-DSP 1.4.4 (Cortex-M7 support and corrected out of bound issues) + - CMSIS-Pack 1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial) + - CMSIS-SVD 1.2 (Cortex-M7 extensions) + - CMSIS-RTOS RTX 4.75 (see revision history for details) + + + - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices + + + - CMSIS-Driver 2.02 (incompatible update) + - CMSIS-Pack 1.3 (see revision history for details) + - CMSIS-DSP 1.4.2 (unchanged) + - CMSIS-Core 3.30 (unchanged) + - CMSIS-RTOS RTX 4.74 (unchanged) + - CMSIS-RTOS API 1.02 (unchanged) + - CMSIS-SVD 1.10 (unchanged) + PACK: + - removed G++ specific files from PACK + - added Component Startup variant "C Startup" + - added Pack Checking Utility + - updated conditions to reflect tool-chain dependency + - added Taxonomy for Graphics + - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers" + + + + - CMSIS-RTOS 4.74 (see revision history for details) + - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1. + + + + + + + + + Software components for audio processing + Generic Interfaces for Evaluation and Development Boards + Drivers that support an external component available on an evaluation board + Compiler Software Extensions + Cortex Microcontroller Software Interface Components + Unified Device Drivers compliant to CMSIS-Driver Specifications + Startup, System Setup + Data exchange or data formatter + Drivers that support an extension board or shield + File Drive Support and File System + IoT cloud client connector + IoT specific services + IoT specific software utility + Graphical User Interface + Network Stack using Internet Protocols + Real-time Operating System + Encryption for secure communication or storage + Universal Serial Bus Stack + Generic software utility components + + + + + + + +The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + +The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + + + + + + +The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA. +The ARM Cortex-M1 processor implements the ARMv6-M architecture profile. + + + + + + + + + + + + + + + + +The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + +The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + + + + + + +The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + + + + + + + + + + + +The Arm Cortex-M23 is based on the Armv8-M baseline architecture. +It is the smallest and most energy efficient Arm processor with Arm TrustZone technology. +Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security. + + + + + + + + + + + + + + + + + + + + + + + +The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller +class processor based on the Armv8-M mainline architecture with Arm TrustZone security. + + + + + + + + + + + + no DSP Instructions, no Floating Point Unit, no TrustZone + + + + + + + + no DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, no TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller +class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications. + + + + + + + + + + + + + no DSP Instructions, no Floating Point Unit, no TrustZone + + + + + + + + no DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, no TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-M55 processor is a fully synthesizable, mid-range, microcontroller-class processor that implements the Armv8.1-M mainline architecture and includes support for the M-profile Vector Extension (MVE), also known as Arm Helium technology. +It is Arm's most AI-capable Cortex-M processor, delivering enhanced, energy-efficient digital signal processing (DSP) and machine learning (ML) performance. +The Cortex-M55 processor achieves high compute performance across scalar and vector operations, while maintaining low energy consumption. + + + + + + + + + + + + + Floating Point Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-M85 processor is a fully synthesizable high-performance microcontroller class processor that implements the Armv8.1-M Mainline architecture which includes support for the M-profile Vector Extension (MVE). +The processor also supports previous Armv8-M architectural features. +The design is focused on compute applications such as Digital Signal Processing (DSP) and machine learning. +The Arm Cortex-M85 processor is energy efficient and achieves high compute performance across scalar and vector operations while maintaining low power consumption. + + + + + + + + + + + + + Floating Point Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone, PACBTI + + + + + + + + +The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling + + + + + + + + + + + + + + + +The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling + + + + + + + + + + + + + + + + +Armv8-M Baseline based device with TrustZone + + + + + + + + + + + + + + + + + + +Armv8-M Mainline based device with TrustZone + + + + + + + + + + + + no DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + no DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + no DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + + +Armv8.1-M Mainline based device with TrustZone and MVE + + + + + + + + + + + + + Double Precision Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full +virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit +Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family. + + + + + + + + + + + + + + + + + +The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture. +The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem, +an optional integrated GIC, and an optional L2 cache controller. + + + + + + + + + + + + + + + + + +The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities. +The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions, +and 8-bit Java bytecodes in Jazelle state. + + + + + + + + + + + + + + + + + + + Device interrupt controller interface + + + + + + RTOS Kernel system tick timer interface + + + + + + + CMSIS-RTOS API for Cortex-M, SC000, and SC300 + + + + + + CMSIS-RTOS API for Cortex-M, SC000, and SC300 + + + + + + + + USART Driver API for Cortex-M + + + + + + + SPI Driver API for Cortex-M + + + + + + + SAI Driver API for Cortex-M + + + + + + + I2C Driver API for Cortex-M + + + + + + + CAN Driver API for Cortex-M + + + + + + + Flash Driver API for Cortex-M + + + + + + + MCI Driver API for Cortex-M + + + + + + + NAND Flash Driver API for Cortex-M + + + + + + + Ethernet MAC and PHY Driver API for Cortex-M + + + + + + + + Ethernet MAC Driver API for Cortex-M + + + + + + + Ethernet PHY Driver API for Cortex-M + + + + + + + USB Device Driver API for Cortex-M + + + + + + + USB Host Driver API for Cortex-M + + + + + + + WiFi driver + + + + + + + Virtual I/O + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Armv6-M architecture based device + + + + + + + Armv7-M architecture based device + + + + + + + Armv8-M base line architecture based device + + + + + Armv8-M main line architecture based device + + + + + + + Armv8.1-M main line architecture based device + + + + + + Armv8-M/Armv8.1-M architecture based device + + + + + Armv8-M architecture based device + + + + + + Armv6_7-M architecture based device + + + + + Armv6_7_8-M architecture based device + + + + + + Armv7-A architecture based device + + + + + + + TrustZone + + + + TrustZone (Secure) + + + + + TrustZone (Non-secure) + + + + + + + + Startup files for Arm Compiler 6 targeting TrustZone secure mode + + + + + Startup files for Arm Compiler 6 targeting non-TrustZone or TrustZone non-secure mode + + + + + + + Generic Arm Cortex-M0 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M0+ device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M1 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M3 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M4 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M7 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M23 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M33 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M35P device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M55 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M85 device startup and depends on CMSIS Core + + + + + + Generic Arm SC000 device startup and depends on CMSIS Core + + + + + + Generic Arm SC300 device startup and depends on CMSIS Core + + + + + + Generic Armv8-M Baseline device startup and depends on CMSIS Core + + + + + + Generic Armv8-M Mainline device startup and depends on CMSIS Core + + + + + + Generic Armv8.1-M Mainline device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-A5 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-A7 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-A9 device startup and depends on CMSIS Core + + + + + + + Components required for DSP + + + + + + + + Components required for NN + + + + + + Components required for RTOS RTX + + + + + + + Components required for RTOS RTX IFX + + + + + + + + Components required for RTOS RTX5 + + + + + + Components required for RTOS2 RTX5 + + + + + + + Components required for RTOS2 RTX5 on Armv7-A + + + + + + + + + Components required for RTOS2 RTX5 in Non-Secure Domain + + + + + + + + + Arm Compiler for Armv6-M architecture (little endian) + + + + + + Arm Compiler for Armv6-M architecture (big endian) + + + + + + Arm Compiler for Armv7-M architecture without FPU (little endian) + + + + + + + Arm Compiler for Armv7-M architecture without FPU (big endian) + + + + + + + Arm Compiler for Armv7-M architecture with FPU (little endian) + + + + + + + + Arm Compiler for Armv7-M architecture with FPU (big endian) + + + + + + + + Arm Compiler for Armv8-M base line architecture (little endian) + + + + + + Arm Compiler for Armv8-M/Armv8.1-M main line architecture without FPU/MVE (little endian) + + + + + + + + Arm Compiler for Armv8-M/Armv8.1-M main line architecture with FPU/MVE (little endian) + + + + + + + + + + + GNU Compiler for Armv6-M architecture (little endian) + + + + + + GNU Compiler for Armv6-M architecture (big endian) + + + + + + GNU Compiler for Armv7-M architecture without FPU (little endian) + + + + + + + GNU Compiler for Armv7-M architecture without FPU (big endian) + + + + + + + GNU Compiler for Armv7-M architecture with FPU (little endian) + + + + + + + + GNU Compiler for Armv7-M architecture with FPU (big endian) + + + + + + + + GNU Compiler for Armv8-M base line architecture (little endian) + + + + + + GNU Compiler for Armv8-M/Armv8.1-M main line architecture without FPU/MVE (little endian) + + + + + + + + GNU Compiler for Armv8-M/Armv8.1-M main line architecture with FPU/MVE (little endian) + + + + + + + + + + + IAR Compiler for Armv6-M architecture (little endian) + + + + + + IAR Compiler for Armv6-M architecture (big endian) + + + + + + IAR Compiler for Armv7-M architecture without FPU (little endian) + + + + + + + IAR Compiler for Armv7-M architecture without FPU (big endian) + + + + + + + IAR Compiler for Armv7-M architecture with FPU (little endian) + + + + + + + + IAR Compiler for Armv7-M architecture with FPU (big endian) + + + + + + + + IAR Compiler for Armv8-M base line architecture (little endian) + + + + + + IAR Compiler for Armv8-M main line architecture without FPU (little endian) + + + + + + + IAR Compiler for Armv8-M main line architecture with FPU (little endian) + + + + + + + + IAR Compiler for Armv8.1-M main line architecture without FPU/MVE (little endian) + + + + + + + + IAR Compiler for Armv8.1-M main line architecture with FPU/MVE (little endian) + + + + + + + + + + + Arm Assembler for Armv6-M architecture + + + + + GNU Assembler for Armv6-M architecture + + + + + + IAR Assembler for Armv6-M architecture + + + + + + Arm Assembler for Armv7-M architecture + + + + + GNU Assembler for Armv7-M architecture + + + + + + IAR Assembler for Armv7-M architecture + + + + + + GNU Assembler for Armv8-M base line architecture + + + + + GNU Assembler for Armv8-M/Armv8.1-M main line architecture + + + + + IAR Assembler for Armv8-M base line architecture + + + + + IAR Assembler for Armv8-M main line architecture + + + + + + Arm Assembler for Armv7-A architecture + + + + + GNU Assembler for Armv7-A architecture + + + + + + IAR Assembler for Armv7-A architecture + + + + + + + Components required for OS Tick Private Timer + + + + + + + Components required for OS Tick Generic Physical Timer + + + + + + + + + + CMSIS-CORE for Cortex-M, SC000, SC300, Star-MC1, ARMv8-M, ARMv8.1-M + + + + + + + + + + + + + CMSIS-CORE for Cortex-A + + + + + + + + + + + System and Startup for Generic Arm Cortex-M0 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M0 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M0+ device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M0+ device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M1 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M1 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M3 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M3 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M4 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M4 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M7 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M7 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M23 device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M23 device + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M33 device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M33 device + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M35P device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M35P device + + + + + + + + + + + + + + + + + + + System and Startup for Generic Cortex-M55 device + + + + + + + + + + + + + + + + + System and Startup for Generic Cortex-M85 device + + + + + + + + + + + + + + + + + System and Startup for Generic Arm SC000 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm SC000 device + + + + + + + + + + + + + + + System and Startup for Generic Arm SC300 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm SC300 device + + + + + + + + + + + + + + + System and Startup for Generic Armv8-M Baseline device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Armv8-M Baseline device + + + + + + + + + + + + + + + + + + System and Startup for Generic Armv8-M Mainline device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Armv8-M Mainline device + + + + + + + + + + + + + + + + + + System and Startup for Generic Armv8.1-M Mainline device + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-A5 device + + + + + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-A7 device + + + + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-A9 device + + + + + + + + + + + + + + + + + + + + + + IRQ Controller implementation using GIC + + + + + + + + OS Tick implementation using Private Timer + + + + + + + OS Tick implementation using Generic Physical Timer + + + + + + + + CMSIS-DSP Library for Cortex-M, SC000, and SC300 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-NN Neural Network Library + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300 + + + #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ + #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata + + + #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ + #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300 + + + #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ + #define RTE_CMSIS_RTOS_RTX5 /* CMSIS-RTOS Keil RTX5 */ + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Library) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Library) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Source) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Armv7-A (Source) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Source) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ + #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Access to #include Driver_USART.h file and code template for custom implementation + + + + + + + Access to #include Driver_SPI.h file and code template for custom implementation + + + + + + + Access to #include Driver_SAI.h file and code template for custom implementation + + + + + + + Access to #include Driver_I2C.h file and code template for custom implementation + + + + + + + Access to #include Driver_CAN.h file and code template for custom implementation + + + + + + + Access to #include Driver_Flash.h file and code template for custom implementation + + + + + + + Access to #include Driver_MCI.h file and code template for custom implementation + + + + + + + Access to #include Driver_NAND.h file and code template for custom implementation + + + + + + + Access to #include Driver_ETH_PHY/MAC.h files and code templates for custom implementation + + + + + + + + + Access to #include Driver_ETH_MAC.h file and code template for custom implementation + + + + + + + Access to #include Driver_ETH_PHY.h file and code template for custom implementation + + + + + + + Access to #include Driver_USBD.h file and code template for custom implementation + + + + + + + Access to #include Driver_USBH.h file and code template for custom implementation + + + + + + + Access to #include Driver_WiFi.h file + + + + + + + + + Virtual I/O custom implementation template + + + + + + Virtual I/O implementation using memory only + + + + + + + + + + uVision Simulator + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + EWARM Simulator + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DSP_Lib Bayes example + + + + + + + + + Getting Started + + + + + DSP_Lib Class Marks example + + + + + + + + + Getting Started + + + + + DSP_Lib Convolution example + + + + + + + + + Getting Started + + + + + DSP_Lib Dotproduct example + + + + + + + + + Getting Started + + + + + DSP_Lib FFT Bin example + + + + + + + + + Getting Started + + + + + DSP_Lib FIR example + + + + + + + + + Getting Started + + + + + DSP_Lib Graphic Equalizer example + + + + + + + + + Getting Started + + + + + DSP_Lib Linear Interpolation example + + + + + + + + + Getting Started + + + + + DSP_Lib Matrix example + + + + + + + + + Getting Started + + + + + DSP_Lib Signal Convergence example + + + + + + + + + Getting Started + + + + + DSP_Lib Sinus/Cosinus example + + + + + + + + + Getting Started + + + + + DSP_Lib SVM example + + + + + + + + + Getting Started + + + + + DSP_Lib Variance example + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Blinky example + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 mixed API v1 and v2 + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Message Queue Example + + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Memory Pool Example + + + + + + + + + + Getting Started + + + + + Bare-metal secure/non-secure example without RTOS + + + + + + + + + Getting Started + + + + + Secure/non-secure RTOS example with thread context management + + + + + + + + + Getting Started + + + + + Secure/non-secure RTOS example with security test cases and system recovery + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Blinky example + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Message Queue Example + + + + + + + + + Getting Started + + + + + + diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cachel1_armv7.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cachel1_armv7.h new file mode 100644 index 00000000000..abebc95f946 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armcc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 00000000000..a955d471391 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 00000000000..69114177477 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang_ltm.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 00000000000..1e255d5907f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_compiler.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 00000000000..adbf296f15a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_gcc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 00000000000..67bda4ef3c3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_iccarm.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 00000000000..65b824b009c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_version.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 00000000000..8b4765f186e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv81mml.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv81mml.h new file mode 100644 index 00000000000..94128a1a709 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv81mml.h @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mbl.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mbl.h new file mode 100644 index 00000000000..e9c9b5bf591 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mml.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mml.h new file mode 100644 index 00000000000..c119fbf2424 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mml.h @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm0.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 00000000000..0a0ba223e19 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm0plus.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 00000000000..879a384124e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm1.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm1.h new file mode 100644 index 00000000000..83b8fc6a0d1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm23.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 00000000000..f2cf49fb16c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm3.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 00000000000..74fb87e5c56 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm33.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 00000000000..18a2e6fb034 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm35p.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm35p.h new file mode 100644 index 00000000000..3843d9542c5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm35p.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm4.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 00000000000..e21cd149256 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm55.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm55.h new file mode 100644 index 00000000000..faa30ce36a9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm55.h @@ -0,0 +1,4817 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ + +/* 'SCnSCB' is deprecated and replaced by 'ICB' */ +typedef ICB_Type SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) + +#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) +#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) + +#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) +#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) + +#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) +#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) + +#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) +#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) + +#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) +#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) + +#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) +#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) + +#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) +#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) + +#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) +#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) + +#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) +#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) +#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) + +#define SCnSCB (ICB) +#define SCnSCB_NS (ICB_NS) + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm7.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 00000000000..010506e9fa4 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm85.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm85.h new file mode 100644 index 00000000000..60463111897 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_cm85.h @@ -0,0 +1,4672 @@ +/**************************************************************************//** + * @file core_cm85.h + * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File + * @version V1.0.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "pac_armv81.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_sc000.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 00000000000..e252068ce64 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_sc300.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 00000000000..d66621031e0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_starmc1.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_starmc1.h new file mode 100644 index 00000000000..ebc0f77eb73 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/core_starmc1.h @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv7.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 00000000000..9909f83990b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv8.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 00000000000..19855b9667c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/pac_armv81.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/pac_armv81.h new file mode 100644 index 00000000000..854b60a204c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/pac_armv81.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/pmu_armv8.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/pmu_armv8.h new file mode 100644 index 00000000000..aa53bb47c1f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/tz_context.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/tz_context.h new file mode 100644 index 00000000000..facc2c9a47e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/main_s.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/main_s.c new file mode 100644 index 00000000000..0e56b7cb947 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/main_s.c @@ -0,0 +1,58 @@ +/****************************************************************************** + * @file main_s.c + * @brief Code template for secure main function + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Use CMSE intrinsics */ +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +/* TZ_START_NS: Start address of non-secure application */ +#ifndef TZ_START_NS +#define TZ_START_NS (0x200000U) +#endif + +/* typedef for non-secure callback functions */ +typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); + +/* Secure main() */ +int main(void) { + funcptr_void NonSecure_ResetHandler; + + /* Add user setup code for secure part here*/ + + /* Set non-secure main stack (MSP_NS) */ + __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); + + /* Get non-secure reset handler */ + NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); + + /* Start non-secure state software application */ + NonSecure_ResetHandler(); + + /* Non-secure software does not return, this code is not executed */ + while (1) { + __NOP(); + } +} diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/tz_context.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/tz_context.c new file mode 100644 index 00000000000..e2e82942f81 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/tz_context.c @@ -0,0 +1,200 @@ +/****************************************************************************** + * @file tz_context.c + * @brief Context Management for Armv8-M TrustZone - Sample implementation + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2016-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + // Privileged Thread Mode using PSP + __set_CONTROL(0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armcc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 00000000000..a955d471391 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armclang.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 00000000000..69114177477 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 00000000000..1e255d5907f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_compiler.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 00000000000..adbf296f15a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_gcc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 00000000000..67bda4ef3c3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_iccarm.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 00000000000..65b824b009c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_version.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_version.h new file mode 100644 index 00000000000..8b4765f186e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/core_cm0plus.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/core_cm0plus.h new file mode 100644 index 00000000000..879a384124e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/core_cm3.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/core_cm3.h new file mode 100644 index 00000000000..74fb87e5c56 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/mpu_armv7.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/mpu_armv7.h new file mode 100644 index 00000000000..9909f83990b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/LICENSE.txt b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/LICENSE.txt new file mode 100644 index 00000000000..8dada3edaf5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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It gives our users and partners contiguous access to the CMSIS development. It allows you to review the work and provide feedback or create pull requests for contributions. + +A [pre-built documentation](https://arm-software.github.io/CMSIS_5/develop/General/html/index.html) is updated from time to time, but may be also generated using the instructions under [Generate CMSIS Pack for Release](https://github.com/ARM-software/CMSIS_5#generate-cmsis-pack-for-release). + +## Overview of CMSIS Components + +The following is an list of all CMSIS components that are available. + +| CMSIS-... | Target Processors | Description | +|:----------|:--------------------|:-------------| +|[Core(M)](http://arm-software.github.io/CMSIS_5/Core/html/index.html) | All Cortex-M, SecurCore | Standardized API for the Cortex-M processor core and peripherals. Includes intrinsic functions for Cortex-M4/M7/M33/M35P SIMD instructions.| +|[Core(A)](http://arm-software.github.io/CMSIS_5/Core_A/html/index.html)| Cortex-A5/A7/A9 | API and basic run-time system for the Cortex-A5/A7/A9 processor core and peripherals.| +|[Driver](http://arm-software.github.io/CMSIS_5/Driver/html/index.html) | All Cortex-M, SecurCore | Generic peripheral driver interfaces for middleware. Connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces.| +|[DSP](http://arm-software.github.io/CMSIS_5/DSP/html/index.html) | All Cortex-M | DSP library collection with over 60 Functions for various data types: fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit). Implementations optimized for the SIMD instruction set are available for Cortex-M4/M7/M33/M35P.| +|[NN](http://arm-software.github.io/CMSIS_5/NN/html/index.html) | All Cortex-M | Collection of efficient neural network kernels developed to maximize the performance and minimize the memory footprint on Cortex-M processor cores.| +|[RTOS v1](http://arm-software.github.io/CMSIS_5/RTOS/html/index.html) | Cortex-M0/M0+/M3/M4/M7 | Common API for real-time operating systems along with a reference implementation based on RTX. It enables software components that can work across multiple RTOS systems.| +|[RTOS v2](http://arm-software.github.io/CMSIS_5/RTOS2/html/index.html)| All Cortex-M, Cortex-A5/A7/A9 | Extends CMSIS-RTOS v1 with Armv8-M support, dynamic object creation, provisions for multi-core systems, binary compatible interface. | +|[Pack](http://arm-software.github.io/CMSIS_5/Pack/html/index.html) | All Cortex-M, SecurCore, Cortex-A5/A7/A9 | Describes a delivery mechanism for software components, device parameters, and evaluation board support. It simplifies software re-use and product life-cycle management (PLM).
Is part of the [Open CMSIS Pack project](https://www.open-cmsis-pack.org). | +|[Build](http://arm-software.github.io/CMSIS_5/Build/html/index.html) | All Cortex-M, SecurCore, Cortex-A5/A7/A9 | A set of tools, software frameworks, and work flows that improve productivity, for example with Continuous Integration (CI) support.
Is replaced with the [CMSIS-Toolbox](https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools). | +|[SVD](http://arm-software.github.io/CMSIS_5/SVD/html/index.html) | All Cortex-M, SecurCore | Peripheral description of a device that can be used to create peripheral awareness in debuggers or CMSIS-Core header files.| +|[DAP](http://arm-software.github.io/CMSIS_5/DAP/html/index.html) | All Cortex | Firmware for a debug unit that interfaces to the CoreSight Debug Access Port. | +|[Zone](http://arm-software.github.io/CMSIS_5/Zone/html/index.html) | All Cortex-M | Defines methods to describe system resources and to partition these resources into multiple projects and execution areas. | + +## Implemented Enhancements + - CMSIS-Pack generation with [shell script template](https://arm-software.github.io/CMSIS_5/Pack/html/bash_script.html) for Windows and Linux + - CMSIS-Pack: [Git workflow](https://arm-software.github.io/CMSIS_5/Pack/html/element_repository.html) via Eclipse menu *Window - Preferences - CMSIS Packs - Manage Local Repositories* and [MDK](http://www.keil.com/support/man/docs/uv4/uv4_ca_packinst_repo.htm) + - [CMSIS-Zone release 1.0](https://arm-software.github.io/CMSIS_5/Zone/html/index.html) with support for multi-processor, TrustZone, and MPU configuration + - Support for Armv8.1M Architecture and Cortex-M55 (release in March 2020) + - CMSIS-DSP is fully ported to SIMD for Cortex-M family (Armv8.1-M) and Cortex-A & Cortex-R with NEON, using the same APIs. + +## Further Planned Enhancements + - CMSIS-Pack: + - System Description SDF Format: describe more complex debug topologies than with a Debug Description in a tool agnostic way + - CPDSC project file format: allows project templates that are agnostic of an IDE + - Minimize need for IDE specific settings: CMSIS-Pack supports IDE specific parameters. Analyze and minimize + - CMSIS-Build: command-line driven make system for CMSIS-Pack based projects (to support CI tests) + +For further details see also the [Slides of the Embedded World CMSIS Partner Meeting](https://github.com/ARM-software/CMSIS_5/blob/develop/CMSIS_Review_Meeting_2020.pdf). + +## Other related GitHub repositories + +| Repository | Description | +|:--------------------------- |:--------------------------------------------------------- | +| [cmsis-pack-eclipse](https://github.com/ARM-software/cmsis-pack-eclipse) | CMSIS-Pack Management for Eclipse reference implementation Pack support | +| [CMSIS-FreeRTOS](https://github.com/arm-software/CMSIS-FreeRTOS) | CMSIS-RTOS adoption of FreeRTOS | +| [CMSIS-Driver](https://github.com/arm-software/CMSIS-Driver) | Generic MCU driver implementations and templates for Ethernet MAC/PHY and Flash. | +| [CMSIS-Driver_Validation](https://github.com/ARM-software/CMSIS-Driver_Validation) | CMSIS-Driver Validation can be used to verify CMSIS-Driver in a user system | +| [CMSIS-Zone](https://github.com/ARM-software/CMSIS-Zone) | CMSIS-Zone Utility along with example projects and FreeMarker templates | +| [NXP_LPC](https://github.com/ARM-software/NXP_LPC) | CMSIS Driver Implementations for the NXP LPC Microcontroller Series | +| [mdk-packs](https://github.com/mdk-packs) | IoT cloud connectors as trail implementations for MDK (help us to make it generic)| +| [trustedfirmware.org](https://www.trustedfirmware.org/) | Arm Trusted Firmware provides a reference implementation of secure world software for Armv8-A and Armv8-M.| + + +## Directory Structure + +| Directory | Content | +|:-------------------- |:--------------------------------------------------------- | +| CMSIS/Core | CMSIS-Core(M) related files (for release) | +| CMSIS/Core_A | CMSIS-Core(A) related files (for release) | +| CMSIS/CoreValidation | Validation for Core(M) and Core(A) (NOT part of release) | +| CMSIS/DAP | CMSIS-DAP related files and examples | +| CMSIS/Driver | CMSIS-Driver API headers and template files | +| CMSIS/DSP | CMSIS-DSP related files | +| CMSIS/NN | CMSIS-NN related files | +| CMSIS/RTOS | RTOS v1 related files (for Cortex-M) | +| CMSIS/RTOS2 | RTOS v2 related files (for Cortex-M & Armv8-M) | +| CMSIS/Pack | CMSIS-Pack examples and tutorials | +| CMSIS/DoxyGen | Source of the documentation | +| CMSIS/Utilities | Utility programs | + +## Generate CMSIS Pack for Release + +This GitHub development repository lacks pre-built libraries of various software components (RTOS, RTOS2). +In order to generate a full pack one needs to have the build environment available to build these libraries. +This causes some sort of inconvenience. Hence the pre-built libraries may be moved out into separate pack(s) +in the future. + +To build a complete CMSIS pack for installation the following additional tools are required: + - **doxygen.exe** Version: 1.8.6 (Documentation Generator) + - **mscgen.exe** Version: 0.20 (Message Sequence Chart Converter) + - **7z.exe (7-Zip)** Version: 16.02 (File Archiver) + +Using these tools, you can generate on a Windows PC: + - **CMSIS Documentation** using the batch file **gen_doc.sh** (located in ./CMSIS/Doxygen). + - **CMSIS Software Pack** using the batch file **gen_pack.sh** (located in ./CMSIS/Utilities). + The bash script does not generate the documentation. The pre-built libraries for RTX4 and RTX5 + are not included within this repository. + +The file ./CMSIS/DoxyGen/How2Doc.txt describes the rules for creating API documentation. + +## License + +Arm CMSIS is licensed under Apache 2.0. + +## Contributions and Pull Requests + +Contributions are accepted under Apache 2.0. Only submit contributions where you have authored all of the code. + +### Issues and Labels + +Please feel free to raise an [issue on GitHub](https://github.com/ARM-software/CMSIS_5/issues) +to report misbehavior (i.e. bugs) or start discussions about enhancements. This +is your best way to interact directly with the maintenance team and the community. +We encourage you to append implementation suggestions as this helps to decrease the +workload of the very limited maintenance team. + +We will be monitoring and responding to issues as best we can. +Please attempt to avoid filing duplicates of open or closed items when possible. +In the spirit of openness we will be tagging issues with the following: + +- **bug** – We consider this issue to be a bug that will be investigated. + +- **wontfix** - We appreciate this issue but decided not to change the current behavior. + +- **enhancement** – Denotes something that will be implemented soon. + +- **future** - Denotes something not yet schedule for implementation. + +- **out-of-scope** - We consider this issue loosely related to CMSIS. It might by implemented outside of CMSIS. Let us know about your work. + +- **question** – We have further questions to this issue. Please review and provide feedback. + +- **documentation** - This issue is a documentation flaw that will be improved in future. + +- **review** - This issue is under review. Please be patient. + +- **DONE** - We consider this issue as resolved - please review and close it. In case of no further activity this issues will be closed after a week. + +- **duplicate** - This issue is already addressed elsewhere, see comment with provided references. + +- **Important Information** - We provide essential information regarding planned or resolved major enhancements. + diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/ht32f1xxxx_01.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/ht32f1xxxx_01.h new file mode 100644 index 00000000000..f2bcf5de2ad --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/ht32f1xxxx_01.h @@ -0,0 +1,1462 @@ +/***************************************************************************//** + * @file ht32f1xxxx_01.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File + * @version $Rev:: 2914 $ + * @date $Date:: 2023-05-18 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * Holtek supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within + * development tools that are supporting such ARM-based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F1653, HT32F1654 +// HT32F1655, HT32F1656 +// HT32F12345 +// HT32F12365, HT32F12366 +// HT32F22366 +// HT32F12364 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F1xxxx HT32F1xxxx + * @{ + */ + + +#ifndef __HT32F1XXXX_01_H__ +#define __HT32F1XXXX_01_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !defined(USE_HT32F1653_54) && \ + !defined(USE_HT32F1655_56) && \ + !defined(USE_HT32F12345) && \ + !defined(USE_HT32F12365_66) && \ + !defined(USE_HT32F12364) + + //#define USE_HT32F1653_54 + //#define USE_HT32F1655_56 + //#define USE_HT32F12345 + //#define USE_HT32F12365_66 + +#endif + +#if !defined(USE_NOCHIP) && \ + !defined(USE_HT32F1653_54) && \ + !defined(USE_HT32F1655_56) && \ + !defined(USE_HT32F12345) && \ + !defined(USE_HT32F12365_66) && \ + !defined(USE_HT32F12364) + + #error Please add "USE_HT32Fxxxxx_xx" define into C Preprocessor Symbols of the Project configuration. + +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ +/** + * @brief Value of the High Speed Internal oscillator in Hz + */ +#define HSI_VALUE 8000000UL /*!< Value of the High Speed Internal oscillator in Hz */ + +/** + * @brief Value of the Low Speed Internal oscillator in Hz + */ +#define LSI_VALUE 32000UL /*!< Value of the Low Speed Internal oscillator in Hz */ + +/** + * @brief Value of the Low Speed External oscillator in Hz + */ +#define LSE_VALUE 32768UL /*!< Value of the Low Speed External oscillator in Hz */ + +/** + * @brief Adjust the High Speed External oscillator (HSE) Startup Timeout value + */ +#define HSE_READY_TIME ((uint16_t)0xFFFF) /*!< Time out for HSE start up */ +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + + +/** @addtogroup Configuration_for_Interrupt_Number + * @{ + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ****************************** */ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Int */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** HT32 Specific Interrupt Numbers ************************************ */ + CKRDY_IRQn = 0, /*!< Clock ready interrupt */ + LVD_IRQn = 1, /*!< Low voltage detection interrupt */ + BOD_IRQn = 2, /*!< Brown-Out detection interrupt */ + #if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) + WDT_IRQn = 3, /*!< WDT global interrupt */ + #endif + RTC_IRQn = 4, /*!< RTC Wake-up Interrupt */ + FLASH_IRQn = 5, /*!< FLASH global Interrupt */ + EVWUP_IRQn = 6, /*!< Event Wake-up Interrupt */ + LPWUP_IRQn = 7, /*!< WAKEUP pin Interrupt */ + EXTI0_IRQn = 8, /*!< EXTI0 Line detection Interrupt */ + EXTI1_IRQn = 9, /*!< EXTI1 Line detection Interrupt */ + EXTI2_IRQn = 10, /*!< EXTI2 Line detection Interrupt */ + EXTI3_IRQn = 11, /*!< EXTI3 Line detection Interrupt */ + EXTI4_IRQn = 12, /*!< EXTI4 Line detection Interrupt */ + EXTI5_IRQn = 13, /*!< EXTI5 Line detection Interrupt */ + EXTI6_IRQn = 14, /*!< EXTI6 Line detection Interrupt */ + EXTI7_IRQn = 15, /*!< EXTI7 Line detection Interrupt */ + EXTI8_IRQn = 16, /*!< EXTI8 Line detection Interrupt */ + EXTI9_IRQn = 17, /*!< EXTI9 Line detection Interrupt */ + EXTI10_IRQn = 18, /*!< EXTI10 Line detection Interrupt */ + EXTI11_IRQn = 19, /*!< EXTI11 Line detection Interrupt */ + EXTI12_IRQn = 20, /*!< EXTI12 Line detection Interrupt */ + EXTI13_IRQn = 21, /*!< EXTI13 Line detection Interrupt */ + EXTI14_IRQn = 22, /*!< EXTI14 Line detection Interrupt */ + EXTI15_IRQn = 23, /*!< EXTI15 Line detection Interrupt */ + #if !defined(USE_HT32F12364) + COMP_IRQn = 24, /*!< Comparator global Interrupt */ + #endif + ADC0_IRQn = 25, /*!< ADC Interrupt */ + #if !defined(USE_HT32F12364) + MCTM0BRK_IRQn = 27, /*!< MCTM0 BRK interrupt */ + MCTM0UP_IRQn = 28, /*!< MCTM0 UP interrupt */ + MCTM0TR_IRQn = 29, /*!< MCTM0 TR interrupt */ + MCTM0CC_IRQn = 30, /*!< MCTM0 CC interrupt */ + MCTM1BRK_IRQn = 31, /*!< MCTM1 BRK interrupt */ + MCTM1UP_IRQn = 32, /*!< MCTM1 UP interrupt */ + MCTM1TR_IRQn = 33, /*!< MCTM1 TR interrupt */ + MCTM1CC_IRQn = 34, /*!< MCTM1 CC interrupt */ + #endif + GPTM0_IRQn = 35, /*!< General-Purpose Timer0 Interrupt */ + #if !defined(USE_HT32F12364) + GPTM1_IRQn = 36, /*!< General-Purpose Timer1 Interrupt */ + #endif + #if defined(USE_HT32F12364) + SCTM0_IRQn = 37, /*!< Single-Channel Timer0 Interrupt */ + SCTM1_IRQn = 38, /*!< Single-Channel Timer1 Interrupt */ + PWM0_IRQn = 39, /*!< Pulse Width Modulator Timer0 Interrupt */ + #endif + BFTM0_IRQn = 41, /*!< Basic Function Timer0 interrupt */ + BFTM1_IRQn = 42, /*!< Basic Function Timer1 interrupt */ + I2C0_IRQn = 43, /*!< I2C0 global Interrupt */ + I2C1_IRQn = 44, /*!< I2C1 global Interrupt */ + SPI0_IRQn = 45, /*!< SPI0 global Interrupt */ + SPI1_IRQn = 46, /*!< SPI1 global Interrupt */ + USART0_IRQn = 47, /*!< USART0 global Interrupt */ + #if !defined(USE_HT32F12364) + USART1_IRQn = 48, /*!< USART1 global Interrupt */ + #endif + UART0_IRQn = 49, /*!< UART0 global Interrupt */ + UART1_IRQn = 50, /*!< UART1 global Interrupt */ + #if !defined(USE_HT32F12345) + SCI_IRQn = 51, /*!< Smart Card interface interrupt */ + #endif + #if !defined(USE_HT32F12364) + I2S_IRQn = 52, /*!< I2S global Interrupt */ + #endif + USB_IRQn = 53, /*!< USB interrupt */ + #if defined(USE_HT32F12365_66) || defined(USE_HT32F12345) + SDIO_IRQn = 54, /*!< SDIO interrupt */ + #endif + PDMACH0_IRQn = 55, /*!< PDMA channel 0 global interrupt */ + PDMACH1_IRQn = 56, /*!< PDMA channel 1 global interrupt */ + PDMACH2_IRQn = 57, /*!< PDMA channel 2 global interrupt */ + PDMACH3_IRQn = 58, /*!< PDMA channel 3 global interrupt */ + PDMACH4_IRQn = 59, /*!< PDMA channel 4 global interrupt */ + PDMACH5_IRQn = 60, /*!< PDMA channel 5 global interrupt */ + #if !defined(USE_HT32F12364) + PDMACH6_IRQn = 61, /*!< PDMA channel 6 global interrupt */ + PDMACH7_IRQn = 62, /*!< PDMA channel 7 global interrupt */ + #endif + #if defined(USE_HT32F12365_66) || defined(USE_HT32F12345) + PDMACH8_IRQn = 63, /*!< PDMA channel 8 global interrupt */ + PDMACH9_IRQn = 64, /*!< PDMA channel 9 global interrupt */ + PDMACH10_IRQn = 65, /*!< PDMA channel 10 global interrupt */ + PDMACH11_IRQn = 66, /*!< PDMA channel 11 global interrupt */ + #endif + #if defined(USE_HT32F12365_66) + CSIF_IRQn = 67, /*!< CMOS sensor interface interrupt */ + #endif + #if !defined(USE_HT32F12364) + EBI_IRQn = 68, /*!< External bus interface interrupt */ + #endif + #if defined(USE_HT32F12365_66) || defined(USE_HT32F12364) + AES_IRQn = 69, /*!< AES interrupt */ + #endif +} IRQn_Type; + +#define MCTM0_IRQn MCTM0UP_IRQn +#define MCTM0_IRQHandler MCTM0UP_IRQHandler +#define MCTM1_IRQn MCTM1UP_IRQn +#define MCTM1_IRQHandler MCTM1UP_IRQHandler + + +/** + * @} + */ + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_ht32f1xxxx_01.h" /* HT32 system */ + + +/** @addtogroup Exported_Types + * @{ + */ + +typedef signed long long s64; +typedef signed int s32; +typedef signed short s16; +typedef signed char s8; + +typedef const s64 sc64; /*!< Read Only */ +typedef const s32 sc32; /*!< Read Only */ +typedef const s16 sc16; /*!< Read Only */ +typedef const s8 sc8; /*!< Read Only */ + +typedef __IO s64 vs64; +typedef __IO s32 vs32; +typedef __IO s16 vs16; +typedef __IO s8 vs8; + +typedef __I s64 vsc64; /*!< Read Only */ +typedef __I s32 vsc32; /*!< Read Only */ +typedef __I s16 vsc16; /*!< Read Only */ +typedef __I s8 vsc8; /*!< Read Only */ + +typedef unsigned long long u64; +typedef unsigned int u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef const u64 uc64; /*!< Read Only */ +typedef const u32 uc32; /*!< Read Only */ +typedef const u16 uc16; /*!< Read Only */ +typedef const u8 uc8; /*!< Read Only */ + +typedef __IO u64 vu64; +typedef __IO u32 vu32; +typedef __IO u16 vu16; +typedef __IO u8 vu8; + +typedef __I u64 vuc64; /*!< Read Only */ +typedef __I u32 vuc32; /*!< Read Only */ +typedef __I u16 vuc16; /*!< Read Only */ +typedef __I u8 vuc8; /*!< Read Only */ + + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; + +#if !defined(bool) && !defined(__cplusplus) // user may already included or CPP +typedef enum {FALSE = 0, TRUE = !FALSE} bool; +#define false FALSE +#define true TRUE +#else +#define FALSE 0 +#define TRUE 1 +#endif + +typedef enum {RESET = 0, SET = !RESET} FlagStatus; + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + +/** + * @} + */ + +#if defined (__CC_ARM) + #define __ALIGN4 __align(4) +#elif defined (__ICCARM__) + #define __ALIGN4 _Pragma("data_alignment = 4") +#elif defined (__GNUC__) + #define __ALIGN4 __attribute__((aligned(4))) +#endif + +#if defined (__GNUC__) + #define __PACKED_H + #define __PACKED_F __attribute__ ((packed)) +#elif defined (__ICCARM__) || (__CC_ARM) + #define __PACKED_H __packed + #define __PACKED_F +#endif + +#if defined (__CC_ARM) +#pragma anon_unions +#endif + + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648) + + +/** + * @brief Exported constants and macro + */ +#define IS_CONTROL_STATUS(STATUS) ((STATUS == DISABLE) || (STATUS == ENABLE)) + +#define wb(addr, value) (*((u8 volatile *) (addr)) = value) +#define rb(addr) (*((u8 volatile *) (addr))) +#define whw(addr, value) (*((u16 volatile *) (addr)) = value) +#define rhw(addr) (*((u16 volatile *) (addr))) +#define ww(addr, value) (*((u32 volatile *) (addr)) = value) +#define rw(addr) (*((u32 volatile *) (addr))) + + +#define ResetBit_BB(Addr, BitNumber) (*(vu32 *) ((Addr & 0xF0000000) + 0x02000000 + \ + ((Addr & 0xFFFFF) << 5) + (BitNumber << 2)) = 0) +#define SetBit_BB(Addr, BitNumber) (*(vu32 *) ((Addr & 0xF0000000) + 0x02000000 + \ + ((Addr & 0xFFFFF) << 5) + (BitNumber << 2)) = 1) +#define GetBit_BB(Addr, BitNumber) (*(vu32 *) ((Addr & 0xF0000000) + 0x02000000 + \ + ((Addr & 0xFFFFF) << 5) + (BitNumber << 2))) +#define BitBand(Addr, BitNumber) (*(vu32 *) ((Addr & 0xF0000000) + 0x02000000 + \ + ((Addr & 0xFFFFF) << 5) + (BitNumber << 2))) + +#define STRCAT2_(a, b) a##b +#define STRCAT2(a, b) STRCAT2_(a, b) +#define STRCAT3_(a, b, c) a##b##c +#define STRCAT3(a, b, c) STRCAT3_(a, b, c) + +#define IPN_NULL (0) +#define IPN_MCTM0 (0x4002C000) +#define IPN_MCTM1 (0x4002D000) +#define IPN_GPTM0 (0x4006E000) +#define IPN_GPTM1 (0x4006F000) +#define IPN_CHECK(IP) STRCAT2(IPN_, IP) +#define IS_IPN_MCTM(IP) (IPN_CHECK(IP) == IPN_MCTM0) || (IPN_CHECK(IP) == IPN_MCTM1) +#define IS_IPN_GPTM(IP) (IPN_CHECK(IP) == IPN_GPTM0) || (IPN_CHECK(IP) == IPN_GPTM1) + + +/** @addtogroup Peripheral_Registers_Structures + * @{ + */ + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + /* USART0: 0x40000000 */ + /* USART1: 0x40040000 */ + /* UART0: 0x40001000 */ + /* UART1: 0x40041000 */ + #if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) + union { + __IO uint32_t DR; /*!< 0x000 Data Register */ + __IO uint32_t RBR; /*!< 0x000 Receive Buffer Register */ + __IO uint32_t TBR; /*!< 0x000 Transmit Holding Register */ + }; + __IO uint32_t IER; /*!< 0x004 Interrupt Enable Register */ + __IO uint32_t IIR; /*!< 0x008 Interrupt Identification Register/FIFO Control Register */ + __IO uint32_t FCR; /*!< 0x00C FIFO Control Register */ + __IO uint32_t LCR; /*!< 0x010 Line Control Register */ + __IO uint32_t MCR; /*!< 0x014 Modem Control Register */ + union { + __IO uint32_t LSR; /*!< 0x018 Line Status Register */ + __IO uint32_t SR; /*!< 0x018 Line Status Register */ + }; + __IO uint32_t MSR; /*!< 0x01C Modem Status Register */ + __IO uint32_t TPR; /*!< 0x020 Timing Parameter Register */ + __IO uint32_t MDR; /*!< 0x024 Mode Register */ + __IO uint32_t ICR; /*!< 0x028 IrDA Register */ + __IO uint32_t RCR; /*!< 0x02C RS485 Control Register */ + __IO uint32_t SCR; /*!< 0x030 Synchronous Control Register */ + __IO uint32_t FSR; /*!< 0x034 FIFO Status Register */ + __IO uint32_t DLR; /*!< 0x038 Divisor Latch Register */ + __IO uint32_t DTR; /*!< 0x040 Debug/Test Register */ + #else + __IO uint32_t DR; /*!< 0x000 Data Register */ + __IO uint32_t CR; /*!< 0x004 Control Register */ + __IO uint32_t FCR; /*!< 0x008 FIFO Control Register */ + __IO uint32_t IER; /*!< 0x00C Interrupt Enable Register */ + __IO uint32_t SR; /*!< 0x010 Status Register */ + __IO uint32_t TPR; /*!< 0x014 Timing Parameter Register */ + __IO uint32_t ICR; /*!< 0x018 IrDA COntrol Register */ + __IO uint32_t RCR; /*!< 0x01C RS485 Control Register */ + __IO uint32_t SCR; /*!< 0x020 Synchronous Control Register */ + __IO uint32_t DLR; /*!< 0x024 Divisor Latch Register */ + __IO uint32_t DTR; /*!< 0x028 Debug/Test Register */ + #endif +} HT_USART_TypeDef; + + +/** + * @brief SPI + */ +typedef struct +{ + /* SPI0: 0x40004000 */ + /* SPI1: 0x40044000 */ + __IO uint32_t CR0; /*!< 0x000 Control Register 0 */ + __IO uint32_t CR1; /*!< 0x004 Control Register 1 */ + __IO uint32_t IER; /*!< 0x008 Interrupt Enable Register */ + __IO uint32_t CPR; /*!< 0x00C Clock Prescaler Register */ + __IO uint32_t DR; /*!< 0x010 Data Register */ + __IO uint32_t SR; /*!< 0x014 Status Register */ + __IO uint32_t FCR; /*!< 0x018 FIFO Control Register */ + __IO uint32_t FSR; /*!< 0x01C FIFO Status Register */ + __IO uint32_t FTOCR; /*!< 0x020 FIFO Time Out Counter Register */ +} HT_SPI_TypeDef; + + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + /* ADC: 0x40010000 */ +#if defined(USE_HT32F12364) + __IO uint32_t CR; /*!< 0x000 ADC Conversion Control Register */ + __IO uint32_t LST[2]; /*!< 0x004 - 0x008 ADC Conversion List Register 0-1 */ + uint32_t RESERVE0[5]; /*!< 0x00C - 0x01C Reserved */ + __IO uint32_t STR; /*!< 0x020 ADC Input Sampling Time Register */ + uint32_t RESERVE1[3]; /*!< 0x024 - 0x02C Reserved */ + __IO uint32_t DR[8]; /*!< 0x030 - 0x04C ADC Conversion Data Register 0-7 */ + uint32_t RESERVE2[8]; /*!< 0x050 - 0x06C Reserved */ + __IO uint32_t TCR; /*!< 0x070 ADC Trigger Control Register */ + __IO uint32_t TSR; /*!< 0x074 ADC Trigger Source Register */ + __IO uint32_t WCR; /*!< 0x078 ADC Watchdog Control Register */ + __IO uint32_t WTR; /*!< 0x07C ADC Watchdog Threshold Register */ + __IO uint32_t IER; /*!< 0x080 ADC Interrupt Enable Register */ + __IO uint32_t IRAW; /*!< 0x084 ADC Interrupt Raw Status Register */ + __IO uint32_t ISR; /*!< 0x088 ADC Interrupt Status Register */ + __IO uint32_t ICLR; /*!< 0x08C ADC Interrupt Clear Register */ + __IO uint32_t PDMAR; /*!< 0x090 ADC PDMA Request Register */ + uint32_t RESERVE3[3]; /*!< 0x094 - 0x09C Reserved */ + __IO uint32_t VREFCR; /*!< 0x0A0 ADC Reference Voltage Control Register */ + __IO uint32_t VREFVALR; /*!< 0x0A4 ADC Reference Voltage Value Register */ +#else + uint32_t RESERVE0[1]; /*!< 0x000 Reserved */ + __IO uint32_t RST; /*!< 0x004 ADC Reset Register */ + __IO uint32_t CONV; /*!< 0x008 ADC Regular Conversion Mode Register */ + __IO uint32_t HCONV; /*!< 0x00C ADC High-priority Conversion Mode Register */ + __IO uint32_t LST[4]; /*!< 0x010 - 0x01C ADC Regular Conversion List Register 0-3 */ + __IO uint32_t HLST; /*!< 0x020 ADC High-priority Conversion List Register */ + uint32_t RESERVE1[3]; /*!< 0x024 - 0x02C Reserved */ + __IO uint32_t OFR[16]; /*!< 0x030 - 0x06C ADC Input Offset Register 0-15 */ + __IO uint32_t STR[16]; /*!< 0x070 - 0x0AC ADC Input Sampling Time Register 0-15 */ + __IO uint32_t DR[16]; /*!< 0x0B0 - 0x0EC ADC Regular Conversion Data Register 0-15 */ + __IO uint32_t HDR[4]; /*!< 0x0F0 - 0x0FC ADC High-priority Conversion Data Register 0-3 */ + __IO uint32_t TCR; /*!< 0x100 ADC Regular Trigger Control Register */ + __IO uint32_t TSR; /*!< 0x104 ADC Regular Trigger Source Register */ + uint32_t RESERVE2[2]; /*!< 0x108 - 0x10C Reserved */ + __IO uint32_t HTCR; /*!< 0x110 ADC High-priority Trigger Control Register */ + __IO uint32_t HTSR; /*!< 0x114 ADC High-priority Trigger Source Register */ + uint32_t RESERVE3[2]; /*!< 0x118 - 0x11C Reserved */ + __IO uint32_t WCR; /*!< 0x120 ADC Watchdog Control Register */ + __IO uint32_t LTR; /*!< 0x124 ADC Lower Threshold Register */ + __IO uint32_t UTR; /*!< 0x128 ADC Upper Threshold Register */ + uint32_t RESERVE4[1]; /*!< 0x12C Reserved */ + __IO uint32_t IER; /*!< 0x130 ADC Interrupt Enable Register */ + __IO uint32_t IRAW; /*!< 0x134 ADC Interrupt Raw Status Register */ + __IO uint32_t ISR; /*!< 0x138 ADC Interrupt Status Register */ + __IO uint32_t ICLR; /*!< 0x13C ADC Interrupt Clear Register */ + __IO uint32_t PDMAR; /*!< 0x140 ADC PDMA Request Register */ +#endif +} HT_ADC_TypeDef; + + +/** + * @brief Op Amp/Comparator + */ +typedef struct +{ + /* CMP_OP0: 0x40018000 */ + /* CMP_OP1: 0x40018100 */ + __IO uint32_t OPACR; /*!< 0x000 Operational Amplifier control register */ + __IO uint32_t OFVCR; /*!< 0x004 Comparator input offset voltage cancellation register */ + __IO uint32_t CMPIER; /*!< 0x008 Comparator interrupt enable register */ + __IO uint32_t CMPRSR; /*!< 0x00C Comparator raw status register */ + __IO uint32_t CMPISR; /*!< 0x010 Comparator interrupt status register */ + __IO uint32_t CMPICLR; /*!< 0x014 Comparator interrupt clear register */ +} HT_CMP_OP_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + /* CMP0: 0x40058000 */ + /* CMP1: 0x40058100 */ + __IO uint32_t CR; /*!< 0x000 Comparator Control Register */ + __IO uint32_t VALR; /*!< 0x004 Comparator Voltage Reference Value Register */ + __IO uint32_t IER; /*!< 0x008 Comparator Interrupt Enable Register */ + __IO uint32_t TFR; /*!< 0x00C Comparator Transition Flag Register */ +} HT_CMP_TypeDef; + + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + /* GPIOA: 0x400B0000 */ + /* GPIOB: 0x400B2000 */ + /* GPIOC: 0x400B4000 */ + /* GPIOD: 0x400B6000 */ + /* GPIOE: 0x400B8000 */ + /* GPIOF: 0x400BA000 */ + __IO uint32_t DIRCR; /*!< 0x000 Data Direction Control Register */ + __IO uint32_t INER; /*!< 0x004 Input function enable register */ + __IO uint32_t PUR; /*!< 0x008 Pull-Up Selection Register */ + __IO uint32_t PDR; /*!< 0x00C Pull-Down Selection Register */ + __IO uint32_t ODR; /*!< 0x010 Open Drain Selection Register */ + __IO uint32_t DRVR; /*!< 0x014 Drive Current Selection Register */ + __IO uint32_t LOCKR; /*!< 0x018 Lock Register */ + __IO uint32_t DINR; /*!< 0x01c Data Input Register */ + __IO uint32_t DOUTR; /*!< 0x020 Data Output Register */ + __IO uint32_t SRR; /*!< 0x024 Output Set and Reset Control Register */ + __IO uint32_t RR; /*!< 0x028 Output Reset Control Register */ +} HT_GPIO_TypeDef; + + +/** + * @brief AFIO + */ +typedef struct +{ + /* AFIO: 0x40022000 */ + __IO uint32_t ESSR[2]; /*!< 0x000 EXTI Source Selection Register 0 ~ 1 */ + uint32_t RESERVE0[6]; /*!< 0x008 - 0x01C Reserved */ + __IO uint32_t GPACFGR[2]; /*!< 0x020 GPIO Port A Configuration Register 0 ~ 1 */ + __IO uint32_t GPBCFGR[2]; /*!< 0x028 GPIO Port B Configuration Register 0 ~ 1 */ + __IO uint32_t GPCCFGR[2]; /*!< 0x030 GPIO Port C Configuration Register 0 ~ 1 */ + __IO uint32_t GPDCFGR[2]; /*!< 0x038 GPIO Port D Configuration Register 0 ~ 1 */ +#if defined(USE_HT32F1655_56) || defined(USE_HT32F12365_66) + __IO uint32_t GPECFGR[2]; /*!< 0x040 GPIO Port E Configuration Register 0 ~ 1 */ +#else + uint32_t RESERVE1[2]; /*!< 0x040 - 0x044 Reserved */ +#endif +#if defined(USE_HT32F12364) + __IO uint32_t GPECFGR[2]; /*!< 0x048 GPIO Port F Configuration Register 0 ~ 1 */ +#endif +} HT_AFIO_TypeDef; + + +/** + * @brief External Interrupt/Event Controller + */ +typedef struct +{ + /* EXTI: 0x40024000 */ + __IO uint32_t CFGR0; /*!< 0x000 EXTI Interrupt 0 Configuration Register */ + __IO uint32_t CFGR1; /*!< 0x004 EXTI Interrupt 1 Configuration Register */ + __IO uint32_t CFGR2; /*!< 0x008 EXTI Interrupt 2 Configuration Register */ + __IO uint32_t CFGR3; /*!< 0x00C EXTI Interrupt 3 Configuration Register */ + __IO uint32_t CFGR4; /*!< 0x010 EXTI Interrupt 4 Configuration Register */ + __IO uint32_t CFGR5; /*!< 0x014 EXTI Interrupt 5 Configuration Register */ + __IO uint32_t CFGR6; /*!< 0x018 EXTI Interrupt 6 Configuration Register */ + __IO uint32_t CFGR7; /*!< 0x01C EXTI Interrupt 7 Configuration Register */ + __IO uint32_t CFGR8; /*!< 0x020 EXTI Interrupt 8 Configuration Register */ + __IO uint32_t CFGR9; /*!< 0x024 EXTI Interrupt 9 Configuration Register */ + __IO uint32_t CFGR10; /*!< 0x028 EXTI Interrupt 10 Configuration Register */ + __IO uint32_t CFGR11; /*!< 0x02C EXTI Interrupt 11 Configuration Register */ + __IO uint32_t CFGR12; /*!< 0x030 EXTI Interrupt 12 Configuration Register */ + __IO uint32_t CFGR13; /*!< 0x034 EXTI Interrupt 13 Configuration Register */ + __IO uint32_t CFGR14; /*!< 0x038 EXTI Interrupt 14 Configuration Register */ + __IO uint32_t CFGR15; /*!< 0x03C EXTI Interrupt 15 Configuration Register */ + __IO uint32_t CR; /*!< 0x040 EXTI Interrupt Control Register */ + __IO uint32_t EDGEFLGR; /*!< 0x044 EXTI Interrupt Edge Flag Register */ + __IO uint32_t EDGESR; /*!< 0x048 EXTI Interrupt Edge Status Register */ + __IO uint32_t SSCR; /*!< 0x04C EXTI Interrupt Software Set Command Register */ + __IO uint32_t WAKUPCR; /*!< 0x050 EXTI Interrupt Wakeup Control Register */ + __IO uint32_t WAKUPPOLR; /*!< 0x054 EXTI Interrupt Wakeup Polarity Register */ + __IO uint32_t WAKUPFLG; /*!< 0x058 EXTI Interrupt Wakeup Flag Register */ +} HT_EXTI_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + /* I2C0: 0x40048000 */ + /* I2C1: 0x40049000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t IER; /*!< 0x004 Interrupt Enable Register */ + __IO uint32_t ADDR; /*!< 0x008 Address Register */ + __IO uint32_t SR; /*!< 0x00C Status Register */ + __IO uint32_t SHPGR; /*!< 0x010 SCL High Period Generation Register */ + __IO uint32_t SLPGR; /*!< 0x014 SCL Low Period Generation Register */ + __IO uint32_t DR; /*!< 0x018 Data Register */ + __IO uint32_t TAR; /*!< 0x01C Target Register */ + __IO uint32_t ADDMR; /*!< 0x020 Address Mask Register */ + __IO uint32_t ADDSR; /*!< 0x024 Address Snoop Register */ + __IO uint32_t TOUT; /*!< 0x028 Timeout Register */ +} HT_I2C_TypeDef; + + +/** + * @brief WATCHDOG + */ +typedef struct +{ + /* WDT: 0x40068000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t MR0; /*!< 0x004 Mode 0 Register */ + __IO uint32_t MR1; /*!< 0x008 Mode 1 Register */ + __IO uint32_t SR; /*!< 0x00C Status Register */ + __IO uint32_t PR; /*!< 0x010 Write Protect Register */ +#if defined(USE_HT32F1655_56) + __IO uint32_t CNTR; /*!< 0x014 Counter Register */ +#else + uint32_t RESERVED0[1]; /*!< 0x014 Reserved */ +#endif + __IO uint32_t CSR; /*!< 0x018 Clock Selection Register */ +} HT_WDT_TypeDef; + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + /* RTC: 0x4006A000 */ + __IO uint32_t CNT; /*!< 0x000 RTC Counter Register */ + __IO uint32_t CMP; /*!< 0x004 RTC Compare Register */ + __IO uint32_t CR; /*!< 0x008 RTC Control Register */ + __IO uint32_t SR; /*!< 0x00C RTC Status Register */ + __IO uint32_t IWEN; /*!< 0x010 RTC Interrupt/Wake-up Enable Register */ +} HT_RTC_TypeDef; + + +/** + * @brief Power Control Unit + */ +typedef struct +{ + /* PWRCU: 0x4006A100 */ + __IO uint32_t SR; /*!< 0x000 Status Register */ + __IO uint32_t CR; /*!< 0x004 Control Register */ + __IO uint32_t TEST; /*!< 0x008 Test Register */ + __IO uint32_t HSIRCR; /*!< 0x00C HSI Ready Counter Control Register */ + __IO uint32_t LVDCSR; /*!< 0x010 Low Voltage/Brown Out Detect Control and Status Register*/ + uint32_t RESERVE1[59]; /*!< 0x014 ~ 0x0FC Reserved */ +#if !defined(USE_HT32F12364) + __IO uint32_t BAKREG[10]; /*!< 0x100 ~ 0x124 Backup Register 0 ~ 9 */ +#endif +} HT_PWRCU_TypeDef; + + +#if 0 +/** + * @brief General-Purpose Timer + */ +typedef struct +{ + /* GPTM0: 0x4006E000 */ + /* GPTM1: 0x4006F000 */ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[3]; /*!< 0x014 - 0x01C Reserved */ + __IO uint32_t CH0ICFR; /*!< 0x020 Channel-0 Input Configuration Register */ + __IO uint32_t CH1ICFR; /*!< 0x024 Channel-1 Input Configuration Register */ + __IO uint32_t CH2ICFR; /*!< 0x028 Channel-2 Input Configuration Register */ + __IO uint32_t CH3ICFR; /*!< 0x02C Channel-3 Input Configuration Register */ + uint32_t RESERVED2[4]; /*!< 0x030 - 0x03C Reserved */ + __IO uint32_t CH0OCFR; /*!< 0x040 Channel-0 Output Configuration Register */ + __IO uint32_t CH1OCFR; /*!< 0x044 Channel-1 Output Configuration Register */ + __IO uint32_t CH2OCFR; /*!< 0x048 Channel-2 Output Configuration Register */ + __IO uint32_t CH3OCFR; /*!< 0x04C Channel-3 Output Configuration Register */ + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED3[7]; /*!< 0x058 - 0x070 Reserved */ + __IO uint32_t DICTR; /*!< 0x074 DMA / Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + uint32_t RESERVED4[1]; /*!< 0x08C Reserved */ + __IO uint32_t CH0CCR; /*!< 0x090 Channel 0 Capture/Compare Register */ + __IO uint32_t CH1CCR; /*!< 0x094 Channel 1 Capture/Compare Register */ + __IO uint32_t CH2CCR; /*!< 0x098 Channel 2 Capture/Compare Register */ + __IO uint32_t CH3CCR; /*!< 0x09C Channel 3 Capture/Compare Register */ + __IO uint32_t CH0ACR; /*!< 0x0A0 Channel 0 Asymmetric Compare Register */ + __IO uint32_t CH1ACR; /*!< 0x0A4 Channel 1 Asymmetric Compare Register */ + __IO uint32_t CH2ACR; /*!< 0x0A8 Channel 2 Asymmetric Compare Register */ + __IO uint32_t CH3ACR; /*!< 0x0AC Channel 3 Asymmetric Compare Register */ +} HT_GPTM_TypeDef; +#endif + + +/** + * @brief Flash Memory Controller + */ +typedef struct +{ + /* FLASH: 0x40080000 */ + __IO uint32_t TADR; /*!< 0x000 Flash Target Address Register */ + __IO uint32_t WRDR; /*!< 0x004 Flash Write Data Register */ + uint32_t RESERVED0[1]; /*!< 0x008 Reserved */ + __IO uint32_t OCMR; /*!< 0x00C Flash Operation Command Register */ + __IO uint32_t OPCR; /*!< 0x010 Flash Operation Control Register */ + __IO uint32_t OIER; /*!< 0x014 Flash Operation Interrupt Enable Register */ + __IO uint32_t OISR; /*!< 0x018 Flash Operation Interrupt and Status Register */ + uint32_t RESERVED1[1]; /*!< 0x01C Reserved */ + __IO uint32_t PPSR[4]; /*!< 0x020 ~ 0x02C Flash Page Erase/Program Protection Status Register */ + __IO uint32_t CPSR; /*!< 0x030 Flash Security Protection Status Register */ + uint32_t RESERVED2[51]; /*!< 0x034 ~ 0x0FC Reserved */ + __IO uint32_t VMCR; /*!< 0x100 Flash Vector Mapping Control Register */ + uint32_t RESERVED3[31]; /*!< 0x104 ~ 0x17C Reserved */ + __IO uint32_t MDID; /*!< 0x180 Manufacturer and Device ID Register */ + __IO uint32_t PNSR; /*!< 0x184 Flash Page Number Status Register */ + __IO uint32_t PSSR; /*!< 0x188 Flash Page Size Status Register */ +#if defined(USE_HT32F1653_54) | defined(USE_HT32F1655_56) + uint32_t RESERVED4[29]; /*!< 0x18C ~ 0x1FC Reserved */ +#else + __IO uint32_t DID; /*!< 0x18C Device ID Register */ + uint32_t RESERVED4[28]; /*!< 0x190 ~ 0x1FC Reserved */ +#endif + __IO uint32_t CFCR; /*!< 0x200 Flash Cache and Pre-fetch Control Register */ + uint32_t RESERVED5[63]; /*!< 0x204 ~ 0x2FC Reserved */ + __IO uint32_t SBVT[4]; /*!< 0x300 ~ 0x30C SRAM Booting Vector (4x32Bit) */ +#if defined(USE_HT32F1653_54) | defined(USE_HT32F1655_56) +#else + __IO uint32_t CID[4]; /*!< 0x310 ~ 0x31C Custom ID Register */ +#endif +} HT_FLASH_TypeDef; + + +/** + * @brief Clock Control Unit + */ +typedef struct +{ + /* CKCU: 0x40088000 */ + __IO uint32_t GCFGR; /*!< 0x000 Global Clock Configuration Register */ + __IO uint32_t GCCR; /*!< 0x004 Global Clock Control Register */ + __IO uint32_t GCSR; /*!< 0x008 Global Clock Status Register */ + __IO uint32_t GCIR; /*!< 0x00C Global Clock Interrupt Register */ + uint32_t RESERVED0[2]; /*!< 0x010 ~ 0x14 Reserved */ + __IO uint32_t PLLCFGR; /*!< 0x018 PLL Configuration Register */ + __IO uint32_t PLLCR; /*!< 0x01C PLL Control Register */ + __IO uint32_t AHBCFGR; /*!< 0x020 AHB Configuration Register */ + __IO uint32_t AHBCCR; /*!< 0x024 AHB Clock Control Register */ + __IO uint32_t APBCFGR; /*!< 0x028 APB Configuration Register */ + __IO uint32_t APBCCR0; /*!< 0x02C APB Clock Control Register 0 */ + __IO uint32_t APBCCR1; /*!< 0x030 APB Clock Control Register 1 */ + __IO uint32_t CKST; /*!< 0x034 Clock source status Register */ +#if defined(USE_HT32F1655_56) + uint32_t RESERVED1[4]; /*!< 0x038 ~ 0x44 Reserved */ +#else + __IO uint32_t APBPCSR0; /*!< 0x038 APB Peripheral Clock Selection Register 0 */ + __IO uint32_t APBPCSR1; /*!< 0x03C APB Peripheral Clock Selection Register 1 */ + __IO uint32_t HSICR; /*!< 0x040 HSI Control Register */ + __IO uint32_t HSIATCR; /*!< 0x044 HSI Auto Trimming Counter Register */ +#endif +#if defined(USE_HT32F12364) + __IO uint32_t APBPCSR2; /*!< 0x048 APB Peripheral Clock Selection Register 2 */ + uint32_t RESERVED2[173]; /*!< 0x04C ~ 0x2FC Reserved */ +#else + uint32_t RESERVED2[174]; /*!< 0x048 ~ 0x2FC Reserved */ +#endif + __IO uint32_t LPCR; /*!< 0x300 Low Power Control Register */ + __IO uint32_t MCUDBGCR; /*!< 0x304 MCU Debug Control Register */ +} HT_CKCU_TypeDef; + + +/** + * @brief Reset Control Unit + */ +typedef struct +{ + /* RSTCU: 0x40088100 */ + __IO uint32_t GRSR; /*!< 0x000 Global Reset Status Register */ + __IO uint32_t AHBPRST; /*!< 0x004 AHB Peripheral Reset Register */ + __IO uint32_t APBPRST0; /*!< 0x008 APB Peripheral Reset Register 0 */ + __IO uint32_t APBPRST1; /*!< 0x00C APB Peripheral Reset Register 1 */ +} HT_RSTCU_TypeDef; + + +/** + * @brief Smart Card Interface + */ +typedef struct +{ + /* SCI0: 0x40043000 */ + /* SCI1: 0x4003A000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t CCR; /*!< 0x008 Contact Control Register */ + __IO uint32_t ETU; /*!< 0x00C Elementary Time Unit Register */ + __IO uint32_t GT; /*!< 0x010 Guardtime Register */ + __IO uint32_t WT; /*!< 0x014 Waiting Time Register */ + __IO uint32_t IER; /*!< 0x018 Interrupt Enable Register */ + __IO uint32_t IPR; /*!< 0x01C Interrupt Pending Register */ + __IO uint32_t TXB; /*!< 0x020 Transmit Buffer Register */ + __IO uint32_t RXB; /*!< 0x024 Receive Buffer Register */ + __IO uint32_t PSC; /*!< 0x028 Prescaler Register */ +} HT_SCI_TypeDef; + + +/** + * @brief Basic Function Timer + */ +typedef struct +{ + /* BFTM0: 0x40076000 */ + /* BFTM1: 0x40077000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t CNTR; /*!< 0x008 Counter Value Register */ + __IO uint32_t CMP; /*!< 0x00C Compare Value Register */ +} HT_BFTM_TypeDef; + + +#if 0 +/** + * @brief Motor Control Timer + */ +typedef struct +{ + /* MCTM0: 0x4002C000 */ + /* MCTM1: 0x4002D000 */ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[3]; /*!< 0x014 - 0x01C Reserved */ + __IO uint32_t CH0ICFR; /*!< 0x020 Channel-0 Input Configuration Register */ + __IO uint32_t CH1ICFR; /*!< 0x024 Channel-1 Input Configuration Register */ + __IO uint32_t CH2ICFR; /*!< 0x028 Channel-2 Input Configuration Register */ + __IO uint32_t CH3ICFR; /*!< 0x02C Channel-3 Input Configuration Register */ + uint32_t RESERVED2[4]; /*!< 0x030 - 0x03C Reserved */ + __IO uint32_t CH0OCFR; /*!< 0x040 Channel-0 Output Configuration Register */ + __IO uint32_t CH1OCFR; /*!< 0x044 Channel-1 Output Configuration Register */ + __IO uint32_t CH2OCFR; /*!< 0x048 Channel-2 Output Configuration Register */ + __IO uint32_t CH3OCFR; /*!< 0x04C Channel-3 Output Configuration Register */ + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED3[5]; /*!< 0x058 - 0x068 Reserved */ + __IO uint32_t CHBRKCFR; /*!< 0x06C Channel Break Configuration Register */ + __IO uint32_t CHBRKCTR; /*!< 0x070 Channel Break Control Register */ + __IO uint32_t DICTR; /*!< 0x074 DMA / Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + __IO uint32_t REPR; /*!< 0x08C Repetition Register */ + __IO uint32_t CH0CCR; /*!< 0x090 Channel 0 Capture/Compare Register */ + __IO uint32_t CH1CCR; /*!< 0x094 Channel 1 Capture/Compare Register */ + __IO uint32_t CH2CCR; /*!< 0x098 Channel 2 Capture/Compare Register */ + __IO uint32_t CH3CCR; /*!< 0x09C Channel 3 Capture/Compare Register */ + __IO uint32_t CH0ACR; /*!< 0x0A0 Channel 0 Asymmetric Compare Register */ + __IO uint32_t CH1ACR; /*!< 0x0A4 Channel 1 Asymmetric Compare Register */ + __IO uint32_t CH2ACR; /*!< 0x0A8 Channel 2 Asymmetric Compare Register */ + __IO uint32_t CH3ACR; /*!< 0x0AC Channel 3 Asymmetric Compare Register */ +} HT_MCTM_TypeDef; +#endif + + +/** + * @brief Timer + */ +typedef struct +{ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[3]; /*!< 0x014 - 0x01C Reserved */ + __IO uint32_t CH0ICFR; /*!< 0x020 Channel-0 Input Configuration Register */ + __IO uint32_t CH1ICFR; /*!< 0x024 Channel-1 Input Configuration Register */ + __IO uint32_t CH2ICFR; /*!< 0x028 Channel-2 Input Configuration Register */ + __IO uint32_t CH3ICFR; /*!< 0x02C Channel-3 Input Configuration Register */ + uint32_t RESERVED2[4]; /*!< 0x030 - 0x03C Reserved */ + __IO uint32_t CH0OCFR; /*!< 0x040 Channel-0 Output Configuration Register */ + __IO uint32_t CH1OCFR; /*!< 0x044 Channel-1 Output Configuration Register */ + __IO uint32_t CH2OCFR; /*!< 0x048 Channel-2 Output Configuration Register */ + __IO uint32_t CH3OCFR; /*!< 0x04C Channel-3 Output Configuration Register */ + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED3[5]; /*!< 0x058 - 0x068 Reserved */ + __IO uint32_t CHBRKCFR; /*!< 0x06C Channel Break Configuration Register */ + __IO uint32_t CHBRKCTR; /*!< 0x070 Channel Break Control Register */ + __IO uint32_t DICTR; /*!< 0x074 DMA / Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + __IO uint32_t REPR; /*!< 0x08C Repetition Register */ + __IO uint32_t CH0CCR; /*!< 0x090 Channel 0 Capture/Compare Register */ + __IO uint32_t CH1CCR; /*!< 0x094 Channel 1 Capture/Compare Register */ + __IO uint32_t CH2CCR; /*!< 0x098 Channel 2 Capture/Compare Register */ + __IO uint32_t CH3CCR; /*!< 0x09C Channel 3 Capture/Compare Register */ + __IO uint32_t CH0ACR; /*!< 0x0A0 Channel 0 Asymmetric Compare Register */ + __IO uint32_t CH1ACR; /*!< 0x0A4 Channel 1 Asymmetric Compare Register */ + __IO uint32_t CH2ACR; /*!< 0x0A8 Channel 2 Asymmetric Compare Register */ + __IO uint32_t CH3ACR; /*!< 0x0AC Channel 3 Asymmetric Compare Register */ +} HT_TM_TypeDef; + + +/** + * @brief Peripheral Direct Memory Access Channel + */ +typedef struct +{ + __IO uint32_t CR; /*!< 0x000 PDMA Channel Control Register */ + __IO uint32_t SADR; /*!< 0x004 PDMA Channel Source Address Register */ + __IO uint32_t DADR; /*!< 0x008 PDMA Channel Destination Address Register */ +#if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) + __IO uint32_t CADR; /*!< 0x00C PDMA Channel Current Address Register */ +#else + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ +#endif + __IO uint32_t TSR; /*!< 0x010 PDMA Channel Transfer Size Register */ + __IO uint32_t CTSR; /*!< 0x014 PDMA Channel Current Transfer Size Register */ +} HT_PDMACH_TypeDef; + + +/** + * @brief Peripheral Direct Memory Access Global + */ +typedef struct +{ + /* PDMA: 0x40090000 */ + HT_PDMACH_TypeDef PDMACH0; /*!< 0x000 PDMA channel 0 registers */ + HT_PDMACH_TypeDef PDMACH1; /*!< 0x018 PDMA channel 1 registers */ + HT_PDMACH_TypeDef PDMACH2; /*!< 0x030 PDMA channel 2 registers */ + HT_PDMACH_TypeDef PDMACH3; /*!< 0x048 PDMA channel 3 registers */ + HT_PDMACH_TypeDef PDMACH4; /*!< 0x060 PDMA channel 4 registers */ + HT_PDMACH_TypeDef PDMACH5; /*!< 0x078 PDMA channel 5 registers */ +#if !defined(USE_HT32F12364) + HT_PDMACH_TypeDef PDMACH6; /*!< 0x090 PDMA channel 6 registers */ + HT_PDMACH_TypeDef PDMACH7; /*!< 0x0A8 PDMA channel 7 registers */ +#endif +#if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) + uint32_t RESERVED0[24];/*!< 0x0C0 - 0x011C Reserved */ +#elif defined(USE_HT32F12365_66) || defined(USE_HT32F12345) + HT_PDMACH_TypeDef PDMACH8; /*!< 0x0C0 PDMA channel 8 registers */ + HT_PDMACH_TypeDef PDMACH9; /*!< 0x0D8 PDMA channel 9 registers */ + HT_PDMACH_TypeDef PDMACH10; /*!< 0x0F0 PDMA channel 10 registers */ + HT_PDMACH_TypeDef PDMACH11; /*!< 0x108 PDMA channel 11 registers */ +#elif defined(USE_HT32F12364) + uint32_t RESERVED0[36];/*!< 0x090 - 0x11C Reserved */ +#endif + __IO uint32_t ISR0; /*!< 0x120 PDMA Interrupt Status Register 0 */ +#if !defined(USE_HT32F12364) + __IO uint32_t ISR1; /*!< 0x124 PDMA Interrupt Status Register 1 */ +#else + uint32_t RESERVED1[1]; /*!< 0x124 Reserved */ +#endif + __IO uint32_t ISCR0; /*!< 0x128 PDMA Interrupt Status Clear Register 0 */ +#if !defined(USE_HT32F12364) + __IO uint32_t ISCR1; /*!< 0x12C PDMA Interrupt Status Clear Register 1 */ +#else + uint32_t RESERVED2[1]; /*!< 0x12C Reserved */ +#endif + __IO uint32_t IER0; /*!< 0x130 PDMA Interrupt Enable Register 0 */ +#if !defined(USE_HT32F12364) + __IO uint32_t IER1; /*!< 0x134 PDMA Interrupt Enable Register 1 */ +#endif +} HT_PDMA_TypeDef; + + +/** + * @brief Universal Serial Bus Global + */ +typedef struct +{ + /* USB: 0x400A8000 */ + __IO uint32_t CSR; /*!< 0x000 USB Control and Status Register */ + __IO uint32_t IER; /*!< 0x004 USB Interrupt Enable Register */ + __IO uint32_t ISR; /*!< 0x008 USB Interrupt Status Register */ + __IO uint32_t FCR; /*!< 0x00C USB Frame Count Register */ + __IO uint32_t DEVAR; /*!< 0x010 USB Device Address Register */ + __IO uint32_t EP0CSR; /*!< 0x014 USB Endpoint 0 Control and Status Register */ + __IO uint32_t EP0IER; /*!< 0x018 USB Endpoint 0 Interrupt Enable Register */ + __IO uint32_t EP0ISR; /*!< 0x01C USB Endpoint 0 Interrupt Status Register */ + __IO uint32_t EP0TCR; /*!< 0x020 USB Endpoint 0 Transfer Count Register */ + __IO uint32_t EP0CFGR; /*!< 0x024 USB Endpoint 0 Configuration Register */ + __IO uint32_t EP1CSR; /*!< 0x028 USB Endpoint 1 Control and Status Register */ + __IO uint32_t EP1IER; /*!< 0x02C USB Endpoint 1 Interrupt Enable Register */ + __IO uint32_t EP1ISR; /*!< 0x030 USB Endpoint 1 Interrupt Status Register */ + __IO uint32_t EP1TCR; /*!< 0x034 USB Endpoint 1 Transfer Count Register */ + __IO uint32_t EP1CFGR; /*!< 0x038 USB Endpoint 1 Configuration Register */ + __IO uint32_t EP2CSR; /*!< 0x03C USB Endpoint 2 Control and Status Register */ + __IO uint32_t EP2IER; /*!< 0x040 USB Endpoint 2 Interrupt Enable Register */ + __IO uint32_t EP2ISR; /*!< 0x044 USB Endpoint 2 Interrupt Status Register */ + __IO uint32_t EP2TCR; /*!< 0x048 USB Endpoint 2 Transfer Count Register */ + __IO uint32_t EP2CFGR; /*!< 0x04C USB Endpoint 2 Configuration Register */ + __IO uint32_t EP3CSR; /*!< 0x050 USB Endpoint 3 Control and Status Register */ + __IO uint32_t EP3IER; /*!< 0x054 USB Endpoint 3 Interrupt Enable Register */ + __IO uint32_t EP3ISR; /*!< 0x058 USB Endpoint 3 Interrupt Status Register */ + __IO uint32_t EP3TCR; /*!< 0x05C USB Endpoint 3 Transfer Count Register */ + __IO uint32_t EP3CFGR; /*!< 0x060 USB Endpoint 3 Configuration Register */ + __IO uint32_t EP4CSR; /*!< 0x064 USB Endpoint 4 Control and Status Register */ + __IO uint32_t EP4IER; /*!< 0x068 USB Endpoint 4 Interrupt Enable Register */ + __IO uint32_t EP4ISR; /*!< 0x06C USB Endpoint 4 Interrupt Status Register */ + __IO uint32_t EP4TCR; /*!< 0x070 USB Endpoint 4 Transfer Count Register */ + __IO uint32_t EP4CFGR; /*!< 0x074 USB Endpoint 4 Configuration Register */ + __IO uint32_t EP5CSR; /*!< 0x078 USB Endpoint 5 Control and Status Register */ + __IO uint32_t EP5IER; /*!< 0x07C USB Endpoint 5 Interrupt Enable Register */ + __IO uint32_t EP5ISR; /*!< 0x080 USB Endpoint 5 Interrupt Status Register */ + __IO uint32_t EP5TCR; /*!< 0x084 USB Endpoint 5 Transfer Count Register */ + __IO uint32_t EP5CFGR; /*!< 0x088 USB Endpoint 5 Configuration Register */ + __IO uint32_t EP6CSR; /*!< 0x08C USB Endpoint 6 Control and Status Register */ + __IO uint32_t EP6IER; /*!< 0x090 USB Endpoint 6 Interrupt Enable Register */ + __IO uint32_t EP6ISR; /*!< 0x094 USB Endpoint 6 Interrupt Status Register */ + __IO uint32_t EP6TCR; /*!< 0x098 USB Endpoint 6 Transfer Count Register */ + __IO uint32_t EP6CFGR; /*!< 0x09C USB Endpoint 6 Configuration Register */ + __IO uint32_t EP7CSR; /*!< 0x0A0 USB Endpoint 7 Control and Status Register */ + __IO uint32_t EP7IER; /*!< 0x0A4 USB Endpoint 7 Interrupt Enable Register */ + __IO uint32_t EP7ISR; /*!< 0x0A8 USB Endpoint 7 Interrupt Status Register */ + __IO uint32_t EP7TCR; /*!< 0x0AC USB Endpoint 7 Transfer Count Register */ + __IO uint32_t EP7CFGR; /*!< 0x0B0 USB Endpoint 7 Configuration Register */ +} HT_USB_TypeDef; + + +/** + * @brief Universal Serial Bus Endpoint + */ +typedef struct +{ + /* USB Endpoint0: 0x400A8014 */ + /* USB Endpoint1: 0x400A8028 */ + /* USB Endpoint2: 0x400A803C */ + /* USB Endpoint3: 0x400A8050 */ + /* USB Endpoint4: 0x400A8064 */ + /* USB Endpoint5: 0x400A8078 */ + /* USB Endpoint6: 0x400A808C */ + /* USB Endpoint7: 0x400A80A0 */ + __IO uint32_t CSR; /*!< 0x000 USB Endpoint n Control and Status Register */ + __IO uint32_t IER; /*!< 0x004 USB Endpoint n Interrupt Enable Register */ + __IO uint32_t ISR; /*!< 0x008 USB Endpoint n Interrupt Status Register */ + __IO uint32_t TCR; /*!< 0x00C USB Endpoint n Transfer Count Register */ + __IO uint32_t CFGR; /*!< 0x010 USB Endpoint n Configuration Register */ +} HT_USBEP_TypeDef; + + +/** + * @brief External Bus Interface + */ +typedef struct +{ + /* EBI: 0x40098000 */ + __IO uint32_t CR; /*!< 0x000 EBI Control Register */ +#if !defined(USE_HT32F12364) + __IO uint32_t PCR; /*!< 0x004 EBI Page Control Register */ +#else + uint32_t RESERVED0[1]; /*!< 0x004 Reserved */ +#endif + __IO uint32_t SR; /*!< 0x008 EBI Status Register */ + uint32_t RESERVED1[1]; /*!< 0x00C Reserved */ + __IO uint32_t ATR0; /*!< 0x010 EBI Address Timing Register 0 */ + __IO uint32_t RTR0; /*!< 0x014 EBI Read Timing Register 0 */ + __IO uint32_t WTR0; /*!< 0x018 EBI Write Timing Register 0 */ + __IO uint32_t PR0; /*!< 0x01C EBI Parity Register 0 */ +#if !defined(USE_HT32F12364) + __IO uint32_t ATR1; /*!< 0x020 EBI Address Timing Register 1 */ + __IO uint32_t RTR1; /*!< 0x024 EBI Read Timing Register 1 */ + __IO uint32_t WTR1; /*!< 0x028 EBI Write Timing Register 1 */ + __IO uint32_t PR1; /*!< 0x02C EBI Parity Register 1 */ + __IO uint32_t ATR2; /*!< 0x030 EBI Address Timing Register 2 */ + __IO uint32_t RTR2; /*!< 0x034 EBI Read Timing Register 2 */ + __IO uint32_t WTR2; /*!< 0x038 EBI Write Timing Register 2 */ + __IO uint32_t PR2; /*!< 0x03C EBI Parity Register 2 */ + __IO uint32_t ATR3; /*!< 0x040 EBI Address Timing Register 3 */ + __IO uint32_t RTR3; /*!< 0x044 EBI Read Timing Register 3 */ + __IO uint32_t WTR3; /*!< 0x048 EBI Write Timing Register 3 */ + __IO uint32_t PR3; /*!< 0x04C EBI Parity Register 3 */ + __IO uint32_t IEN; /*!< 0x050 EBI Interrupt Enable Register */ + __IO uint32_t IF; /*!< 0x054 EBI Interrupt Flag Register */ + __IO uint32_t IFC; /*!< 0x058 EBI Interrupt Clear Register */ +#endif +} HT_EBI_TypeDef; + + +/** + * @brief Cyclic Redundancy Check + */ +typedef struct +{ + /* CRC: 0x4008A000 */ + __IO uint32_t CR; /*!< 0x000 CRC Control Register */ + __IO uint32_t SDR; /*!< 0x004 CRC Seed Register */ + __IO uint32_t CSR; /*!< 0x008 CRC Checksum Register */ + __IO uint32_t DR; /*!< 0x00C CRC Data Register */ +} HT_CRC_TypeDef; + + +/** + * @brief Integrated Interchip Sound + */ +typedef struct +{ + /* I2S: 0x40026000 */ + __IO uint32_t CR; /*!< 0x000 I2S Control Register */ + __IO uint32_t IER; /*!< 0x004 I2S Interrupt Enable Register */ + __IO uint32_t CDR; /*!< 0x008 I2S Clock Divider Register */ + __IO uint32_t TXDR; /*!< 0x00C I2S TX Data Register */ + __IO uint32_t RXDR; /*!< 0x010 I2S RX Data Register */ + __IO uint32_t FCR; /*!< 0x014 I2S FIFO Control Register */ + __IO uint32_t SR; /*!< 0x018 I2S Status Register */ + __IO uint32_t RCNTR; /*!< 0x01C I2S Rate Counter Register */ +} HT_I2S_TypeDef; + + +/** + * @brief Secure digital input/output + */ +typedef struct +{ + /* SDIO: 0x400A0000 */ + __IO uint32_t BLKSIZE; /*!< 0x000 Block Size Register */ + __IO uint32_t BLKCNT; /*!< 0x004 Block Count Register */ + __IO uint32_t ARG; /*!< 0x008 Argument Register */ + __IO uint32_t TMR; /*!< 0x00C Transfer Mode Register */ + __IO uint32_t CMD; /*!< 0x010 Command Register Register */ + __IO uint32_t RESP0; /*!< 0x014 Response Register 0 */ + __IO uint32_t RESP1; /*!< 0x018 Response Register 1 */ + __IO uint32_t RESP2; /*!< 0x01C Response Register 2 */ + __IO uint32_t RESP3; /*!< 0x020 Response Register 3 */ + __IO uint32_t DR; /*!< 0x024 Data Register */ + __IO uint32_t PSR; /*!< 0x028 Present Status Register */ + __IO uint32_t CR; /*!< 0x02C Control Register */ + uint32_t RESERVED0[2]; /*!< 0x030 - 0x034 Reserved */ + __IO uint32_t CLKCR; /*!< 0x038 Clock Control Register */ + __IO uint32_t TMOCR; /*!< 0x03C Timeout Control Register */ + __IO uint32_t SWRST; /*!< 0x040 Software Reset Register */ + __IO uint32_t SR; /*!< 0x044 Status Register */ + __IO uint32_t SER; /*!< 0x048 Status Enable Register */ + __IO uint32_t IER; /*!< 0x04C Interrupt Enable Register */ +} HT_SDIO_TypeDef; + + +/** + * @brief CMOS Sensor Interface + */ +typedef struct +{ + /* CSIF: 0x400CC000 */ + __IO uint32_t ENR; /*!< 0x000 Enable Register */ + __IO uint32_t CR; /*!< 0x004 Control Register */ + __IO uint32_t IMGWH; /*!< 0x008 Image Width/Height Register */ + __IO uint32_t WCR0; /*!< 0x00C Window Capture 0 Register */ + __IO uint32_t WCR1; /*!< 0x010 Window Capture 1 Register */ + __IO uint32_t SMP; /*!< 0x014 Row & Column Sub-Sample Register */ + __IO uint32_t SMPCOL; /*!< 0x018 Column Sub-Sample Register */ + __IO uint32_t SMPROW; /*!< 0x01C Row Sub-Sample Register */ + __IO uint32_t FIFO0; /*!< 0x020 FIFO Register 0 */ + __IO uint32_t FIFO1; /*!< 0x024 FIFO Register 1 */ + __IO uint32_t FIFO2; /*!< 0x028 FIFO Register 2 */ + __IO uint32_t FIFO3; /*!< 0x02C FIFO Register 3 */ + __IO uint32_t FIFO4; /*!< 0x030 FIFO Register 4 */ + __IO uint32_t FIFO5; /*!< 0x034 FIFO Register 5 */ + __IO uint32_t FIFO6; /*!< 0x038 FIFO Register 6 */ + __IO uint32_t FIFO7; /*!< 0x03C FIFO Register 7 */ + __IO uint32_t IER; /*!< 0x040 Interrupt Enable Register */ + __IO uint32_t SR; /*!< 0x044 Status Register */ +} HT_CSIF_TypeDef; + + +/** + * @brief Advanced Encryption Standard + */ +typedef struct +{ + /* AES: 0x400C8000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t PDMAR; /*!< 0x008 PDMA Register */ + __IO uint32_t ISR; /*!< 0x00C Interrupt Status Register */ + __IO uint32_t IER; /*!< 0x010 Interrupt Enable Register */ + __IO uint32_t DINR; /*!< 0x014 Data Input Register */ + __IO uint32_t DOUTR; /*!< 0x018 Data Output Register */ + __IO uint32_t KEYR[8]; /*!< 0x01C - 0x038 Key Register 0~7 */ + __IO uint32_t IVR[4]; /*!< 0x03C - 0x048 Initial Vector Register 0~3 */ +} HT_AES_TypeDef; + + +/** + * @} + */ + + +/** @addtogroup Peripheral_Memory_Map + * @{ + */ + +#define HT_SRAM_BASE (0x20000000UL) +#define HT_SRAM_BB_BASE (0x22000000UL) + +#define HT_PERIPH_BASE (0x40000000UL) +#define HT_PERIPH_BB_BASE (0x42000000UL) + +#define HT_APB0PERIPH_BASE (HT_PERIPH_BASE) /* 0x40000000 */ +#define HT_APB1PERIPH_BASE (HT_PERIPH_BASE + 0x40000) /* 0x40040000 */ +#define HT_AHBPERIPH_BASE (HT_PERIPH_BASE + 0x80000) /* 0x40080000 */ + +/* APB0 */ +#define HT_USART0_BASE (HT_APB0PERIPH_BASE + 0x0000) /* 0x40000000 */ +#define HT_UART0_BASE (HT_APB0PERIPH_BASE + 0x1000) /* 0x40001000 */ +#define HT_SPI0_BASE (HT_APB0PERIPH_BASE + 0x4000) /* 0x40004000 */ +#define HT_ADC0_BASE (HT_APB0PERIPH_BASE + 0x10000) /* 0x40010000 */ +#define HT_CMP_OP0_BASE (HT_APB0PERIPH_BASE + 0x18000) /* 0x40018000 */ +#define HT_CMP_OP1_BASE (HT_APB0PERIPH_BASE + 0x18100) /* 0x40018100 */ +#define HT_AFIO_BASE (HT_APB0PERIPH_BASE + 0x22000) /* 0x40022000 */ +#define HT_EXTI_BASE (HT_APB0PERIPH_BASE + 0x24000) /* 0x40024000 */ +#define HT_I2S_BASE (HT_APB0PERIPH_BASE + 0x26000) /* 0x40026000 */ +#define HT_MCTM0_BASE (HT_APB0PERIPH_BASE + 0x2C000) /* 0x4002C000 */ +#define HT_MCTM1_BASE (HT_APB0PERIPH_BASE + 0x2D000) /* 0x4002D000 */ +#define HT_PWM0_BASE (HT_APB0PERIPH_BASE + 0x31000) /* 0x40031000 */ +#define HT_SCTM0_BASE (HT_APB0PERIPH_BASE + 0x34000) /* 0x40034000 */ +#define HT_SCI1_BASE (HT_APB0PERIPH_BASE + 0x3A000) /* 0x4003A000 */ + +/* APB1 */ +#define HT_USART1_BASE (HT_APB1PERIPH_BASE + 0x0000) /* 0x40040000 */ +#define HT_UART1_BASE (HT_APB1PERIPH_BASE + 0x1000) /* 0x40041000 */ +#define HT_SCI0_BASE (HT_APB1PERIPH_BASE + 0x3000) /* 0x40043000 */ +#define HT_SPI1_BASE (HT_APB1PERIPH_BASE + 0x4000) /* 0x40044000 */ +#define HT_I2C0_BASE (HT_APB1PERIPH_BASE + 0x8000) /* 0x40048000 */ +#define HT_I2C1_BASE (HT_APB1PERIPH_BASE + 0x9000) /* 0x40049000 */ +#define HT_CMP0_BASE (HT_APB1PERIPH_BASE + 0x18000) /* 0x40058000 */ +#define HT_CMP1_BASE (HT_APB1PERIPH_BASE + 0x18100) /* 0x40058100 */ +#define HT_WDT_BASE (HT_APB1PERIPH_BASE + 0x28000) /* 0x40068000 */ +#define HT_RTC_BASE (HT_APB1PERIPH_BASE + 0x2A000) /* 0x4006A000 */ +#define HT_PWRCU_BASE (HT_APB1PERIPH_BASE + 0x2A100) /* 0x4006A100 */ +#define HT_GPTM0_BASE (HT_APB1PERIPH_BASE + 0x2E000) /* 0x4006E000 */ +#define HT_GPTM1_BASE (HT_APB1PERIPH_BASE + 0x2F000) /* 0x4006F000 */ +#define HT_SCTM1_BASE (HT_APB1PERIPH_BASE + 0x34000) /* 0x40074000 */ +#define HT_BFTM0_BASE (HT_APB1PERIPH_BASE + 0x36000) /* 0x40076000 */ +#define HT_BFTM1_BASE (HT_APB1PERIPH_BASE + 0x37000) /* 0x40077000 */ + +/* AHB */ +#define HT_FLASH_BASE (HT_AHBPERIPH_BASE + 0x0000) /* 0x40080000 */ +#define HT_CKCU_BASE (HT_AHBPERIPH_BASE + 0x8000) /* 0x40088000 */ +#define HT_RSTCU_BASE (HT_AHBPERIPH_BASE + 0x8100) /* 0x40088100 */ +#define HT_CRC_BASE (HT_AHBPERIPH_BASE + 0xA000) /* 0x4008A000 */ +#define HT_PDMA_BASE (HT_AHBPERIPH_BASE + 0x10000) /* 0x40090000 */ +#define HT_EBI_BASE (HT_AHBPERIPH_BASE + 0x18000) /* 0x40098000 */ +#define HT_SDIO_BASE (HT_AHBPERIPH_BASE + 0x20000) /* 0x400A0000 */ +#define HT_USB_BASE (HT_AHBPERIPH_BASE + 0x28000) /* 0x400A8000 */ +#define HT_USB_EP0_BASE (HT_USB_BASE + 0x0014) /* 0x400A8014 */ +#define HT_USB_EP1_BASE (HT_USB_BASE + 0x0028) /* 0x400A8028 */ +#define HT_USB_EP2_BASE (HT_USB_BASE + 0x003C) /* 0x400A803C */ +#define HT_USB_EP3_BASE (HT_USB_BASE + 0x0050) /* 0x400A8050 */ +#define HT_USB_EP4_BASE (HT_USB_BASE + 0x0064) /* 0x400A8064 */ +#define HT_USB_EP5_BASE (HT_USB_BASE + 0x0078) /* 0x400A8078 */ +#define HT_USB_EP6_BASE (HT_USB_BASE + 0x008C) /* 0x400A808C */ +#define HT_USB_EP7_BASE (HT_USB_BASE + 0x00A0) /* 0x400A80A0 */ +#define HT_USB_SRAM_BASE (HT_AHBPERIPH_BASE + 0x2A000) /* 0x400AA000 */ +#define HT_GPIOA_BASE (HT_AHBPERIPH_BASE + 0x30000) /* 0x400B0000 */ +#define HT_GPIOB_BASE (HT_AHBPERIPH_BASE + 0x32000) /* 0x400B2000 */ +#define HT_GPIOC_BASE (HT_AHBPERIPH_BASE + 0x34000) /* 0x400B4000 */ +#define HT_GPIOD_BASE (HT_AHBPERIPH_BASE + 0x36000) /* 0x400B6000 */ +#define HT_GPIOE_BASE (HT_AHBPERIPH_BASE + 0x38000) /* 0x400B8000 */ +#define HT_GPIOF_BASE (HT_AHBPERIPH_BASE + 0x3A000) /* 0x400BA000 */ +#define HT_AES_BASE (HT_AHBPERIPH_BASE + 0x48000) /* 0x400C8000 */ +#define HT_CSIF_BASE (HT_AHBPERIPH_BASE + 0x4C000) /* 0x400CC000 */ + +/** + * @} + */ + +/* Peripheral declaration */ +#define HT_ADC0 ((HT_ADC_TypeDef *) HT_ADC0_BASE) +#define HT_AFIO ((HT_AFIO_TypeDef *) HT_AFIO_BASE) +#define HT_BFTM0 ((HT_BFTM_TypeDef *) HT_BFTM0_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_CKCU ((HT_CKCU_TypeDef *) HT_CKCU_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_EXTI ((HT_EXTI_TypeDef *) HT_EXTI_BASE) +#define HT_FLASH ((HT_FLASH_TypeDef *) HT_FLASH_BASE) +#define HT_GPIOA ((HT_GPIO_TypeDef *) HT_GPIOA_BASE) +#define HT_GPIOB ((HT_GPIO_TypeDef *) HT_GPIOB_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_GPTM0 ((HT_TM_TypeDef *) HT_GPTM0_BASE) +#define HT_I2C0 ((HT_I2C_TypeDef *) HT_I2C0_BASE) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_PWRCU ((HT_PWRCU_TypeDef *) HT_PWRCU_BASE) +#define HT_RSTCU ((HT_RSTCU_TypeDef *) HT_RSTCU_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_SPI0 ((HT_SPI_TypeDef *) HT_SPI0_BASE) +#define HT_UART0 ((HT_USART_TypeDef *) HT_UART0_BASE) +#define HT_USART0 ((HT_USART_TypeDef *) HT_USART0_BASE) +#define HT_USB ((HT_USB_TypeDef *) HT_USB_BASE) +#define HT_USBEP0 ((HT_USBEP_TypeDef *) HT_USB_EP0_BASE) +#define HT_USBEP1 ((HT_USBEP_TypeDef *) HT_USB_EP1_BASE) +#define HT_USBEP2 ((HT_USBEP_TypeDef *) HT_USB_EP2_BASE) +#define HT_USBEP3 ((HT_USBEP_TypeDef *) HT_USB_EP3_BASE) +#define HT_USBEP4 ((HT_USBEP_TypeDef *) HT_USB_EP4_BASE) +#define HT_USBEP5 ((HT_USBEP_TypeDef *) HT_USB_EP5_BASE) +#define HT_USBEP6 ((HT_USBEP_TypeDef *) HT_USB_EP6_BASE) +#define HT_USBEP7 ((HT_USBEP_TypeDef *) HT_USB_EP7_BASE) +#define HT_WDT ((HT_WDT_TypeDef *) HT_WDT_BASE) + + +#if defined(USE_HT32F1655_56) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CMP_OP0 ((HT_CMP_OP_TypeDef *) HT_CMP_OP0_BASE) +#define HT_CMP_OP1 ((HT_CMP_OP_TypeDef *) HT_CMP_OP1_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_MCTM1 ((HT_TM_TypeDef *) HT_MCTM1_BASE) +#define HT_GPTM1 ((HT_TM_TypeDef *) HT_GPTM1_BASE) +#define HT_SCI0 ((HT_SCI_TypeDef *) HT_SCI0_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_GPIOE ((HT_GPIO_TypeDef *) HT_GPIOE_BASE) +#endif + +#if defined(USE_HT32F1653_54) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_MCTM1 ((HT_TM_TypeDef *) HT_MCTM1_BASE) +#define HT_GPTM1 ((HT_TM_TypeDef *) HT_GPTM1_BASE) +#define HT_SCI0 ((HT_SCI_TypeDef *) HT_SCI0_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#endif + +#if defined(USE_HT32F12365_66) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_MCTM1 ((HT_TM_TypeDef *) HT_MCTM1_BASE) +#define HT_GPTM1 ((HT_TM_TypeDef *) HT_GPTM1_BASE) +#define HT_SCI0 ((HT_SCI_TypeDef *) HT_SCI0_BASE) +#define HT_SCI1 ((HT_SCI_TypeDef *) HT_SCI1_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_GPIOE ((HT_GPIO_TypeDef *) HT_GPIOE_BASE) +#define HT_SDIO ((HT_SDIO_TypeDef *) HT_SDIO_BASE) +#define HT_AES ((HT_AES_TypeDef *) HT_AES_BASE) +#define HT_CSIF ((HT_CSIF_TypeDef *) HT_CSIF_BASE) +#endif + +#if defined(USE_HT32F12345) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_MCTM1 ((HT_TM_TypeDef *) HT_MCTM1_BASE) +#define HT_GPTM1 ((HT_TM_TypeDef *) HT_GPTM1_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_SDIO ((HT_SDIO_TypeDef *) HT_SDIO_BASE) +#endif + +#if defined(USE_HT32F12364) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_SCI0 ((HT_SCI_TypeDef *) HT_SCI0_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_GPIOF ((HT_GPIO_TypeDef *) HT_GPIOF_BASE) +#define HT_AES ((HT_AES_TypeDef *) HT_AES_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_SCTM0 ((HT_TM_TypeDef *) HT_SCTM0_BASE) +#define HT_SCTM1 ((HT_TM_TypeDef *) HT_SCTM1_BASE) +#endif + +#if defined USE_HT32_DRIVER + #include "ht32f1xxxx_lib.h" +#endif + +/** + * @brief Adjust the value of High Speed External oscillator (HSE) + Tip: To avoid from modifying every time for different HSE, please define + the "HSE_VALUE=n000000" ("n" represents n MHz) in your own toolchain compiler preprocessor, + or edit the "HSE_VALUE" in the "ht32f1xxxx_conf.h" file. + */ +#if !defined HSE_VALUE + /* Available HSE_VALUE: 4 MHz ~ 16 MHz */ + #define HSE_VALUE 8000000UL /*!< Value of the External oscillator in Hz */ +#endif + +/** + * @brief Define for backward compatibility + */ +#define HT_ADC HT_ADC0 +#define ADC ADC0 +#define ADC_IRQn ADC0_IRQn + + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_01.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_01.h new file mode 100644 index 00000000000..bdba227af08 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_01.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f1xxxx_01.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File + * for the Holtek HT32F1xxxx Device Series + * @version $Rev:: 735 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F1xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F1XXXX_01_H +#define __SYSTEM_HT32F1XXXX_01_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F1xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F1xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_02.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_02.h new file mode 100644 index 00000000000..ea20c74d674 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_02.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f1xxxx_02.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File + * for the Holtek HT32F1xxxx Device Series + * @version $Rev:: 735 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F1xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F1XXXX_02_H +#define __SYSTEM_HT32F1XXXX_02_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F1xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F1xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_03.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_03.h new file mode 100644 index 00000000000..214d0008f7d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/system_ht32f1xxxx_03.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f1xxxx_03.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File + * for the Holtek HT32F1xxxx Device Series + * @version $Rev:: 735 $ + * @date $Date:: 2019-06-12 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F1xxxx_system + * @{ + */ + + +#ifndef __system_ht32f1xxxx_03_H +#define __system_ht32f1xxxx_03_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F1xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F1xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12345.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12345.s new file mode 100644 index 00000000000..f3f24a1faf0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12345.s @@ -0,0 +1,469 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_01.s +; Version : $Rev:: 2524 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +USE_HT32_CHIP_SET EQU 3 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012366 + +HT32F1653_54_55_56 EQU 1 +HT32F12365_66 EQU 2 +HT32F12345 EQU 3 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-131072:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD WDT_IRQHandler ; 03, 19, 0x04C, + ELSE + DCD _RESERVED ; 03, 19, 0x04C, + ENDIF + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD COMP_IRQHandler ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MCTM0BRK_IRQHandler ; 27, 43, 0x0AC, + DCD MCTM0UP_IRQHandler ; 28, 44, 0x0B0, + DCD MCTM0TR_IRQHandler ; 29, 45, 0x0B4, + DCD MCTM0CC_IRQHandler ; 30, 46, 0x0B8, + DCD MCTM1BRK_IRQHandler ; 31, 47, 0x0BC, + DCD MCTM1UP_IRQHandler ; 32, 48, 0x0C0, + DCD MCTM1TR_IRQHandler ; 33, 49, 0x0C4, + DCD MCTM1CC_IRQHandler ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD GPTM1_IRQHandler ; 36, 52, 0x0D0, + DCD _RESERVED ; 37, 53, 0x0D4, + DCD _RESERVED ; 38, 54, 0x0D8, + DCD _RESERVED ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD USART1_IRQHandler ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + IF (USE_HT32_CHIP=HT32F12345) + DCD _RESERVED ; 51, 67, 0x10C, + ELSE + DCD SCI_IRQHandler ; 51, 67, 0x10C, + ENDIF + DCD I2S_IRQHandler ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 54, 70, 0x118, + ELSE + DCD SDIO_IRQHandler ; 54, 70, 0x118, + ENDIF + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD PDMA_CH6_IRQHandler ; 61, 77, 0x134, + DCD PDMA_CH7_IRQHandler ; 62, 78, 0x138, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + ELSE + DCD PDMA_CH8_IRQHandler ; 63, 79, 0x13C, + DCD PDMA_CH9_IRQHandler ; 64, 80, 0x140, + DCD PDMA_CH10_IRQHandler ; 65, 81, 0x144, + DCD PDMA_CH11_IRQHandler ; 66, 82, 0x148, + ENDIF + IF (USE_HT32_CHIP=HT32F12365_66) + DCD CSIF_IRQHandler ; 67, 83, 0x14C, + ELSE + DCD _RESERVED ; 67, 83, 0x14C, + ENDIF + DCD EBI_IRQHandler ; 68, 84, 0x150, + IF (USE_HT32_CHIP=HT32F12365_66) + DCD AES_IRQHandler ; 69, 85, 0x154, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE + LDR R0, =BootProcess + BLX R0 + ENDIF + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + ENDIF + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT CKRDY_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT LPWUP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0BRK_IRQHandler [WEAK] + EXPORT MCTM0UP_IRQHandler [WEAK] + EXPORT MCTM0TR_IRQHandler [WEAK] + EXPORT MCTM0CC_IRQHandler [WEAK] + EXPORT MCTM1BRK_IRQHandler [WEAK] + EXPORT MCTM1UP_IRQHandler [WEAK] + EXPORT MCTM1TR_IRQHandler [WEAK] + EXPORT MCTM1CC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT PDMA_CH0_IRQHandler [WEAK] + EXPORT PDMA_CH1_IRQHandler [WEAK] + EXPORT PDMA_CH2_IRQHandler [WEAK] + EXPORT PDMA_CH3_IRQHandler [WEAK] + EXPORT PDMA_CH4_IRQHandler [WEAK] + EXPORT PDMA_CH5_IRQHandler [WEAK] + EXPORT PDMA_CH6_IRQHandler [WEAK] + EXPORT PDMA_CH7_IRQHandler [WEAK] + EXPORT PDMA_CH8_IRQHandler [WEAK] + EXPORT PDMA_CH9_IRQHandler [WEAK] + EXPORT PDMA_CH10_IRQHandler [WEAK] + EXPORT PDMA_CH11_IRQHandler [WEAK] + EXPORT CSIF_IRQHandler [WEAK] + EXPORT EBI_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +WDT_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0BRK_IRQHandler +MCTM0UP_IRQHandler +MCTM0TR_IRQHandler +MCTM0CC_IRQHandler +MCTM1BRK_IRQHandler +MCTM1UP_IRQHandler +MCTM1TR_IRQHandler +MCTM1CC_IRQHandler +GPTM0_IRQHandler +GPTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +SDIO_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +PDMA_CH6_IRQHandler +PDMA_CH7_IRQHandler +PDMA_CH8_IRQHandler +PDMA_CH9_IRQHandler +PDMA_CH10_IRQHandler +PDMA_CH11_IRQHandler +CSIF_IRQHandler +EBI_IRQHandler +AES_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12364.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12364.s new file mode 100644 index 00000000000..a1a24ab522b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12364.s @@ -0,0 +1,393 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_03.s +; Version : $Rev:: 2524 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F12364 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <16=> HT32F12364 +USE_HT32_CHIP_SET EQU 16 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012364 + +HT32F12364 EQU 16 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-131072:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + DCD _RESERVED ; 03, 19, 0x04C, + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + DCD _RESERVED ; 32, 48, 0x0C0, + DCD _RESERVED ; 33, 49, 0x0C4, + DCD _RESERVED ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD _RESERVED ; 36, 52, 0x0D0, + DCD SCTM0_IRQHandler ; 37, 53, 0x0D4, + DCD SCTM1_IRQHandler ; 38, 54, 0x0D8, + DCD PWM0_IRQHandler ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD _RESERVED ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + DCD SCI_IRQHandler ; 51, 67, 0x10C, + DCD _RESERVED ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + DCD _RESERVED ; 54, 70, 0x118, + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD _RESERVED ; 61, 77, 0x134, + DCD _RESERVED ; 62, 78, 0x138, + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + DCD _RESERVED ; 67, 83, 0x14C, + DCD _RESERVED ; 68, 84, 0x150, + DCD AES_IRQHandler ; 69, 85, 0x154, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT CKRDY_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT LPWUP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_IRQHandler [WEAK] + EXPORT PDMA_CH1_IRQHandler [WEAK] + EXPORT PDMA_CH2_IRQHandler [WEAK] + EXPORT PDMA_CH3_IRQHandler [WEAK] + EXPORT PDMA_CH4_IRQHandler [WEAK] + EXPORT PDMA_CH5_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +USB_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +AES_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12365_66.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12365_66.s new file mode 100644 index 00000000000..3381f582403 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f12365_66.s @@ -0,0 +1,469 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_01.s +; Version : $Rev:: 2524 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +USE_HT32_CHIP_SET EQU 2 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012366 + +HT32F1653_54_55_56 EQU 1 +HT32F12365_66 EQU 2 +HT32F12345 EQU 3 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-131072:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD WDT_IRQHandler ; 03, 19, 0x04C, + ELSE + DCD _RESERVED ; 03, 19, 0x04C, + ENDIF + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD COMP_IRQHandler ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MCTM0BRK_IRQHandler ; 27, 43, 0x0AC, + DCD MCTM0UP_IRQHandler ; 28, 44, 0x0B0, + DCD MCTM0TR_IRQHandler ; 29, 45, 0x0B4, + DCD MCTM0CC_IRQHandler ; 30, 46, 0x0B8, + DCD MCTM1BRK_IRQHandler ; 31, 47, 0x0BC, + DCD MCTM1UP_IRQHandler ; 32, 48, 0x0C0, + DCD MCTM1TR_IRQHandler ; 33, 49, 0x0C4, + DCD MCTM1CC_IRQHandler ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD GPTM1_IRQHandler ; 36, 52, 0x0D0, + DCD _RESERVED ; 37, 53, 0x0D4, + DCD _RESERVED ; 38, 54, 0x0D8, + DCD _RESERVED ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD USART1_IRQHandler ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + IF (USE_HT32_CHIP=HT32F12345) + DCD _RESERVED ; 51, 67, 0x10C, + ELSE + DCD SCI_IRQHandler ; 51, 67, 0x10C, + ENDIF + DCD I2S_IRQHandler ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 54, 70, 0x118, + ELSE + DCD SDIO_IRQHandler ; 54, 70, 0x118, + ENDIF + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD PDMA_CH6_IRQHandler ; 61, 77, 0x134, + DCD PDMA_CH7_IRQHandler ; 62, 78, 0x138, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + ELSE + DCD PDMA_CH8_IRQHandler ; 63, 79, 0x13C, + DCD PDMA_CH9_IRQHandler ; 64, 80, 0x140, + DCD PDMA_CH10_IRQHandler ; 65, 81, 0x144, + DCD PDMA_CH11_IRQHandler ; 66, 82, 0x148, + ENDIF + IF (USE_HT32_CHIP=HT32F12365_66) + DCD CSIF_IRQHandler ; 67, 83, 0x14C, + ELSE + DCD _RESERVED ; 67, 83, 0x14C, + ENDIF + DCD EBI_IRQHandler ; 68, 84, 0x150, + IF (USE_HT32_CHIP=HT32F12365_66) + DCD AES_IRQHandler ; 69, 85, 0x154, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE + LDR R0, =BootProcess + BLX R0 + ENDIF + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + ENDIF + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT CKRDY_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT LPWUP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0BRK_IRQHandler [WEAK] + EXPORT MCTM0UP_IRQHandler [WEAK] + EXPORT MCTM0TR_IRQHandler [WEAK] + EXPORT MCTM0CC_IRQHandler [WEAK] + EXPORT MCTM1BRK_IRQHandler [WEAK] + EXPORT MCTM1UP_IRQHandler [WEAK] + EXPORT MCTM1TR_IRQHandler [WEAK] + EXPORT MCTM1CC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT PDMA_CH0_IRQHandler [WEAK] + EXPORT PDMA_CH1_IRQHandler [WEAK] + EXPORT PDMA_CH2_IRQHandler [WEAK] + EXPORT PDMA_CH3_IRQHandler [WEAK] + EXPORT PDMA_CH4_IRQHandler [WEAK] + EXPORT PDMA_CH5_IRQHandler [WEAK] + EXPORT PDMA_CH6_IRQHandler [WEAK] + EXPORT PDMA_CH7_IRQHandler [WEAK] + EXPORT PDMA_CH8_IRQHandler [WEAK] + EXPORT PDMA_CH9_IRQHandler [WEAK] + EXPORT PDMA_CH10_IRQHandler [WEAK] + EXPORT PDMA_CH11_IRQHandler [WEAK] + EXPORT CSIF_IRQHandler [WEAK] + EXPORT EBI_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +WDT_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0BRK_IRQHandler +MCTM0UP_IRQHandler +MCTM0TR_IRQHandler +MCTM0CC_IRQHandler +MCTM1BRK_IRQHandler +MCTM1UP_IRQHandler +MCTM1TR_IRQHandler +MCTM1CC_IRQHandler +GPTM0_IRQHandler +GPTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +SDIO_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +PDMA_CH6_IRQHandler +PDMA_CH7_IRQHandler +PDMA_CH8_IRQHandler +PDMA_CH9_IRQHandler +PDMA_CH10_IRQHandler +PDMA_CH11_IRQHandler +CSIF_IRQHandler +EBI_IRQHandler +AES_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f165x.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f165x.s new file mode 100644 index 00000000000..9a0fd83e614 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f165x.s @@ -0,0 +1,469 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_01.s +; Version : $Rev:: 2524 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012366 + +HT32F1653_54_55_56 EQU 1 +HT32F12365_66 EQU 2 +HT32F12345 EQU 3 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-131072:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD WDT_IRQHandler ; 03, 19, 0x04C, + ELSE + DCD _RESERVED ; 03, 19, 0x04C, + ENDIF + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD COMP_IRQHandler ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MCTM0BRK_IRQHandler ; 27, 43, 0x0AC, + DCD MCTM0UP_IRQHandler ; 28, 44, 0x0B0, + DCD MCTM0TR_IRQHandler ; 29, 45, 0x0B4, + DCD MCTM0CC_IRQHandler ; 30, 46, 0x0B8, + DCD MCTM1BRK_IRQHandler ; 31, 47, 0x0BC, + DCD MCTM1UP_IRQHandler ; 32, 48, 0x0C0, + DCD MCTM1TR_IRQHandler ; 33, 49, 0x0C4, + DCD MCTM1CC_IRQHandler ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD GPTM1_IRQHandler ; 36, 52, 0x0D0, + DCD _RESERVED ; 37, 53, 0x0D4, + DCD _RESERVED ; 38, 54, 0x0D8, + DCD _RESERVED ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD USART1_IRQHandler ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + IF (USE_HT32_CHIP=HT32F12345) + DCD _RESERVED ; 51, 67, 0x10C, + ELSE + DCD SCI_IRQHandler ; 51, 67, 0x10C, + ENDIF + DCD I2S_IRQHandler ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 54, 70, 0x118, + ELSE + DCD SDIO_IRQHandler ; 54, 70, 0x118, + ENDIF + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD PDMA_CH6_IRQHandler ; 61, 77, 0x134, + DCD PDMA_CH7_IRQHandler ; 62, 78, 0x138, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + ELSE + DCD PDMA_CH8_IRQHandler ; 63, 79, 0x13C, + DCD PDMA_CH9_IRQHandler ; 64, 80, 0x140, + DCD PDMA_CH10_IRQHandler ; 65, 81, 0x144, + DCD PDMA_CH11_IRQHandler ; 66, 82, 0x148, + ENDIF + IF (USE_HT32_CHIP=HT32F12365_66) + DCD CSIF_IRQHandler ; 67, 83, 0x14C, + ELSE + DCD _RESERVED ; 67, 83, 0x14C, + ENDIF + DCD EBI_IRQHandler ; 68, 84, 0x150, + IF (USE_HT32_CHIP=HT32F12365_66) + DCD AES_IRQHandler ; 69, 85, 0x154, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE + LDR R0, =BootProcess + BLX R0 + ENDIF + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + ENDIF + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT CKRDY_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT LPWUP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0BRK_IRQHandler [WEAK] + EXPORT MCTM0UP_IRQHandler [WEAK] + EXPORT MCTM0TR_IRQHandler [WEAK] + EXPORT MCTM0CC_IRQHandler [WEAK] + EXPORT MCTM1BRK_IRQHandler [WEAK] + EXPORT MCTM1UP_IRQHandler [WEAK] + EXPORT MCTM1TR_IRQHandler [WEAK] + EXPORT MCTM1CC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT PDMA_CH0_IRQHandler [WEAK] + EXPORT PDMA_CH1_IRQHandler [WEAK] + EXPORT PDMA_CH2_IRQHandler [WEAK] + EXPORT PDMA_CH3_IRQHandler [WEAK] + EXPORT PDMA_CH4_IRQHandler [WEAK] + EXPORT PDMA_CH5_IRQHandler [WEAK] + EXPORT PDMA_CH6_IRQHandler [WEAK] + EXPORT PDMA_CH7_IRQHandler [WEAK] + EXPORT PDMA_CH8_IRQHandler [WEAK] + EXPORT PDMA_CH9_IRQHandler [WEAK] + EXPORT PDMA_CH10_IRQHandler [WEAK] + EXPORT PDMA_CH11_IRQHandler [WEAK] + EXPORT CSIF_IRQHandler [WEAK] + EXPORT EBI_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +WDT_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0BRK_IRQHandler +MCTM0UP_IRQHandler +MCTM0TR_IRQHandler +MCTM0CC_IRQHandler +MCTM1BRK_IRQHandler +MCTM1UP_IRQHandler +MCTM1TR_IRQHandler +MCTM1CC_IRQHandler +GPTM0_IRQHandler +GPTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +SDIO_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +PDMA_CH6_IRQHandler +PDMA_CH7_IRQHandler +PDMA_CH8_IRQHandler +PDMA_CH9_IRQHandler +PDMA_CH10_IRQHandler +PDMA_CH11_IRQHandler +CSIF_IRQHandler +EBI_IRQHandler +AES_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_01.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_01.s new file mode 100644 index 00000000000..481edd75d07 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_01.s @@ -0,0 +1,469 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_01.s +; Version : $Rev:: 2524 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012366 + +HT32F1653_54_55_56 EQU 1 +HT32F12365_66 EQU 2 +HT32F12345 EQU 3 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-131072:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD WDT_IRQHandler ; 03, 19, 0x04C, + ELSE + DCD _RESERVED ; 03, 19, 0x04C, + ENDIF + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD COMP_IRQHandler ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MCTM0BRK_IRQHandler ; 27, 43, 0x0AC, + DCD MCTM0UP_IRQHandler ; 28, 44, 0x0B0, + DCD MCTM0TR_IRQHandler ; 29, 45, 0x0B4, + DCD MCTM0CC_IRQHandler ; 30, 46, 0x0B8, + DCD MCTM1BRK_IRQHandler ; 31, 47, 0x0BC, + DCD MCTM1UP_IRQHandler ; 32, 48, 0x0C0, + DCD MCTM1TR_IRQHandler ; 33, 49, 0x0C4, + DCD MCTM1CC_IRQHandler ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD GPTM1_IRQHandler ; 36, 52, 0x0D0, + DCD _RESERVED ; 37, 53, 0x0D4, + DCD _RESERVED ; 38, 54, 0x0D8, + DCD _RESERVED ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD USART1_IRQHandler ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + IF (USE_HT32_CHIP=HT32F12345) + DCD _RESERVED ; 51, 67, 0x10C, + ELSE + DCD SCI_IRQHandler ; 51, 67, 0x10C, + ENDIF + DCD I2S_IRQHandler ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 54, 70, 0x118, + ELSE + DCD SDIO_IRQHandler ; 54, 70, 0x118, + ENDIF + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD PDMA_CH6_IRQHandler ; 61, 77, 0x134, + DCD PDMA_CH7_IRQHandler ; 62, 78, 0x138, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + ELSE + DCD PDMA_CH8_IRQHandler ; 63, 79, 0x13C, + DCD PDMA_CH9_IRQHandler ; 64, 80, 0x140, + DCD PDMA_CH10_IRQHandler ; 65, 81, 0x144, + DCD PDMA_CH11_IRQHandler ; 66, 82, 0x148, + ENDIF + IF (USE_HT32_CHIP=HT32F12365_66) + DCD CSIF_IRQHandler ; 67, 83, 0x14C, + ELSE + DCD _RESERVED ; 67, 83, 0x14C, + ENDIF + DCD EBI_IRQHandler ; 68, 84, 0x150, + IF (USE_HT32_CHIP=HT32F12365_66) + DCD AES_IRQHandler ; 69, 85, 0x154, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE + LDR R0, =BootProcess + BLX R0 + ENDIF + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + ENDIF + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT CKRDY_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT LPWUP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0BRK_IRQHandler [WEAK] + EXPORT MCTM0UP_IRQHandler [WEAK] + EXPORT MCTM0TR_IRQHandler [WEAK] + EXPORT MCTM0CC_IRQHandler [WEAK] + EXPORT MCTM1BRK_IRQHandler [WEAK] + EXPORT MCTM1UP_IRQHandler [WEAK] + EXPORT MCTM1TR_IRQHandler [WEAK] + EXPORT MCTM1CC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT PDMA_CH0_IRQHandler [WEAK] + EXPORT PDMA_CH1_IRQHandler [WEAK] + EXPORT PDMA_CH2_IRQHandler [WEAK] + EXPORT PDMA_CH3_IRQHandler [WEAK] + EXPORT PDMA_CH4_IRQHandler [WEAK] + EXPORT PDMA_CH5_IRQHandler [WEAK] + EXPORT PDMA_CH6_IRQHandler [WEAK] + EXPORT PDMA_CH7_IRQHandler [WEAK] + EXPORT PDMA_CH8_IRQHandler [WEAK] + EXPORT PDMA_CH9_IRQHandler [WEAK] + EXPORT PDMA_CH10_IRQHandler [WEAK] + EXPORT PDMA_CH11_IRQHandler [WEAK] + EXPORT CSIF_IRQHandler [WEAK] + EXPORT EBI_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +WDT_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0BRK_IRQHandler +MCTM0UP_IRQHandler +MCTM0TR_IRQHandler +MCTM0CC_IRQHandler +MCTM1BRK_IRQHandler +MCTM1UP_IRQHandler +MCTM1TR_IRQHandler +MCTM1CC_IRQHandler +GPTM0_IRQHandler +GPTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +SDIO_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +PDMA_CH6_IRQHandler +PDMA_CH7_IRQHandler +PDMA_CH8_IRQHandler +PDMA_CH9_IRQHandler +PDMA_CH10_IRQHandler +PDMA_CH11_IRQHandler +CSIF_IRQHandler +EBI_IRQHandler +AES_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_03.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_03.s new file mode 100644 index 00000000000..323e76c6b6e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ARM/startup_ht32f1xxxx_03.s @@ -0,0 +1,393 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_03.s +; Version : $Rev:: 2524 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F12364 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <16=> HT32F12364 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012364 + +HT32F12364 EQU 16 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-131072:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-131072:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + DCD _RESERVED ; 03, 19, 0x04C, + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + DCD _RESERVED ; 32, 48, 0x0C0, + DCD _RESERVED ; 33, 49, 0x0C4, + DCD _RESERVED ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD _RESERVED ; 36, 52, 0x0D0, + DCD SCTM0_IRQHandler ; 37, 53, 0x0D4, + DCD SCTM1_IRQHandler ; 38, 54, 0x0D8, + DCD PWM0_IRQHandler ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD _RESERVED ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + DCD SCI_IRQHandler ; 51, 67, 0x10C, + DCD _RESERVED ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + DCD _RESERVED ; 54, 70, 0x118, + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD _RESERVED ; 61, 77, 0x134, + DCD _RESERVED ; 62, 78, 0x138, + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + DCD _RESERVED ; 67, 83, 0x14C, + DCD _RESERVED ; 68, 84, 0x150, + DCD AES_IRQHandler ; 69, 85, 0x154, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT CKRDY_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT LPWUP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_IRQHandler [WEAK] + EXPORT PDMA_CH1_IRQHandler [WEAK] + EXPORT PDMA_CH2_IRQHandler [WEAK] + EXPORT PDMA_CH3_IRQHandler [WEAK] + EXPORT PDMA_CH4_IRQHandler [WEAK] + EXPORT PDMA_CH5_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +USB_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +AES_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_01.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_01.s new file mode 100644 index 00000000000..0e11813688a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_01.s @@ -0,0 +1,427 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_cs3_01.s +; Version : $Rev:: 1578 $ +; Date : $Date:: 2019-03-29 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00012366 +*/ + + .equ HT32F1653_54_55_56, 1 + .equ HT32F12365_66, 2 + .equ HT32F12345, 3 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* ---, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* ---, 03, 0x00C, Hard Fault Handler */ + .long MemManage_Handler /* ---, 04, 0x010, MPU Fault Handler */ + .long BusFault_Handler /* ---, 05, 0x014, Bus Fault Handler */ + .long UsageFault_Handler /* ---, 06, 0x018, Usage Fault Handler */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* ---, 11, 0x02C, SVC Handler */ + .long DebugMon_Handler /* ---, 12, 0x030, Debug Monitor Handler */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* ---, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* ---, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long CKRDY_IRQHandler /* 00, 16, 0x040, */ + .long LVD_IRQHandler /* 01, 17, 0x044, */ + .long BOD_IRQHandler /* 02, 18, 0x048, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long WDT_IRQHandler /* 03, 19, 0x04C, */ + .else + .long _RESERVED /* 03, 19, 0x04C, */ + .endif + .long RTC_IRQHandler /* 04, 20, 0x050, */ + .long FLASH_IRQHandler /* 05, 21, 0x054, */ + .long EVWUP_IRQHandler /* 06, 22, 0x058, */ + .long LPWUP_IRQHandler /* 07, 23, 0x05C, */ + .long EXTI0_IRQHandler /* 08, 24, 0x060, */ + .long EXTI1_IRQHandler /* 09, 25, 0x064, */ + .long EXTI2_IRQHandler /* 10, 26, 0x068, */ + .long EXTI3_IRQHandler /* 11, 27, 0x06C, */ + .long EXTI4_IRQHandler /* 12, 28, 0x070, */ + .long EXTI5_IRQHandler /* 13, 29, 0x074, */ + .long EXTI6_IRQHandler /* 14, 30, 0x078, */ + .long EXTI7_IRQHandler /* 15, 31, 0x07C, */ + .long EXTI8_IRQHandler /* 16, 32, 0x080, */ + .long EXTI9_IRQHandler /* 17, 33, 0x084, */ + .long EXTI10_IRQHandler /* 18, 34, 0x088, */ + .long EXTI11_IRQHandler /* 19, 35, 0x08C, */ + .long EXTI12_IRQHandler /* 20, 36, 0x090, */ + .long EXTI13_IRQHandler /* 21, 37, 0x094, */ + .long EXTI14_IRQHandler /* 22, 38, 0x098, */ + .long EXTI15_IRQHandler /* 23, 39, 0x09C, */ + .long COMP_IRQHandler /* 24, 40, 0x0A0, */ + .long ADC_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MCTM0BRK_IRQHandler /* 27, 43, 0x0AC, */ + .long MCTM0UP_IRQHandler /* 28, 44, 0x0B0, */ + .long MCTM0TR_IRQHandler /* 29, 45, 0x0B4, */ + .long MCTM0CC_IRQHandler /* 30, 46, 0x0B8, */ + .long MCTM1BRK_IRQHandler /* 31, 47, 0x0BC, */ + .long MCTM1UP_IRQHandler /* 32, 48, 0x0C0, */ + .long MCTM1TR_IRQHandler /* 33, 49, 0x0C4, */ + .long MCTM1CC_IRQHandler /* 34, 50, 0x0C8, */ + .long GPTM0_IRQHandler /* 35, 51, 0x0CC, */ + .long GPTM1_IRQHandler /* 36, 52, 0x0D0, */ + .long _RESERVED /* 37, 53, 0x0D4, */ + .long _RESERVED /* 38, 54, 0x0D8, */ + .long _RESERVED /* 39, 55, 0x0DC, */ + .long _RESERVED /* 40, 56, 0x0E0, */ + .long BFTM0_IRQHandler /* 41, 57, 0x0E4, */ + .long BFTM1_IRQHandler /* 42, 58, 0x0E8, */ + .long I2C0_IRQHandler /* 43, 59, 0x0EC, */ + .long I2C1_IRQHandler /* 44, 60, 0x0F0, */ + .long SPI0_IRQHandler /* 45, 61, 0x0F4, */ + .long SPI1_IRQHandler /* 46, 62, 0x0F8, */ + .long USART0_IRQHandler /* 47, 63, 0x0FC, */ + .long USART1_IRQHandler /* 48, 64, 0x100, */ + .long UART0_IRQHandler /* 49, 65, 0x104, */ + .long UART1_IRQHandler /* 50, 66, 0x108, */ + .if (USE_HT32_CHIP==HT32F12345) + .long _RESERVED /* 51, 67, 0x10C, */ + .else + .long SCI_IRQHandler /* 51, 67, 0x10C, */ + .endif + .long I2S_IRQHandler /* 52, 68, 0x110, */ + .long USB_IRQHandler /* 53, 69, 0x114, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long _RESERVED /* 54, 70, 0x118, */ + .else + .long SDIO_IRQHandler /* 54, 70, 0x118, */ + .endif + .long PDMA_CH0_IRQHandler /* 55, 71, 0x11C, */ + .long PDMA_CH1_IRQHandler /* 56, 72, 0x120, */ + .long PDMA_CH2_IRQHandler /* 57, 73, 0x124, */ + .long PDMA_CH3_IRQHandler /* 58, 74, 0x128, */ + .long PDMA_CH4_IRQHandler /* 59, 75, 0x12C, */ + .long PDMA_CH5_IRQHandler /* 60, 76, 0x130, */ + .long PDMA_CH6_IRQHandler /* 61, 77, 0x134, */ + .long PDMA_CH7_IRQHandler /* 62, 78, 0x138, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long _RESERVED /* 63, 79, 0x13C, */ + .long _RESERVED /* 64, 80, 0x140, */ + .long _RESERVED /* 65, 81, 0x144, */ + .long _RESERVED /* 66, 82, 0x148, */ + .else + .long PDMA_CH8_IRQHandler /* 63, 79, 0x13C, */ + .long PDMA_CH9_IRQHandler /* 64, 80, 0x140, */ + .long PDMA_CH10_IRQHandler /* 65, 81, 0x144, */ + .long PDMA_CH11_IRQHandler /* 66, 82, 0x148, */ + .endif + .if (USE_HT32_CHIP==HT32F12365_66) + .long CSIF_IRQHandler /* 67, 83, 0x14C, */ + .else + .long _RESERVED /* 67, 83, 0x14C, */ + .endif + .long EBI_IRQHandler /* 68, 84, 0x150, */ + .if (USE_HT32_CHIP==HT32F12365_66) + .long AES_IRQHandler /* 69, 85, 0x154, */ + .endif + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .else + LDR R0, =BootProcess + BLX R0 + .endif + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .else + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .endif + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ CKRDY_IRQHandler + IRQ LVD_IRQHandler + IRQ BOD_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ LPWUP_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ EXTI5_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ EXTI10_IRQHandler + IRQ EXTI11_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ EXTI14_IRQHandler + IRQ EXTI15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0BRK_IRQHandler + IRQ MCTM0UP_IRQHandler + IRQ MCTM0TR_IRQHandler + IRQ MCTM0CC_IRQHandler + IRQ MCTM1BRK_IRQHandler + IRQ MCTM1UP_IRQHandler + IRQ MCTM1TR_IRQHandler + IRQ MCTM1CC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ GPTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ SDIO_IRQHandler + IRQ PDMA_CH0_IRQHandler + IRQ PDMA_CH1_IRQHandler + IRQ PDMA_CH2_IRQHandler + IRQ PDMA_CH3_IRQHandler + IRQ PDMA_CH4_IRQHandler + IRQ PDMA_CH5_IRQHandler + IRQ PDMA_CH6_IRQHandler + IRQ PDMA_CH7_IRQHandler + IRQ PDMA_CH8_IRQHandler + IRQ PDMA_CH9_IRQHandler + IRQ PDMA_CH10_IRQHandler + IRQ PDMA_CH11_IRQHandler + IRQ CSIF_IRQHandler + IRQ EBI_IRQHandler + IRQ AES_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_03.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_03.s new file mode 100644 index 00000000000..2d3a6034d94 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/CodeSourcery/startup_ht32f1xxxx_cs3_03.s @@ -0,0 +1,370 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_cs3_03.s +; Version : $Rev:: 1771 $ +; Date : $Date:: 2019-07-25 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F12364 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <16=> HT32F12364 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00012364 +*/ + + .equ HT32F12364, 16 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* ---, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* ---, 03, 0x00C, Hard Fault Handler */ + .long MemManage_Handler /* ---, 04, 0x010, MPU Fault Handler */ + .long BusFault_Handler /* ---, 05, 0x014, Bus Fault Handler */ + .long UsageFault_Handler /* ---, 06, 0x018, Usage Fault Handler */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* ---, 11, 0x02C, SVC Handler */ + .long DebugMon_Handler /* ---, 12, 0x030, Debug Monitor Handler */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* ---, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* ---, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long CKRDY_IRQHandler /* 00, 16, 0x040, */ + .long LVD_IRQHandler /* 01, 17, 0x044, */ + .long BOD_IRQHandler /* 02, 18, 0x048, */ + .long _RESERVED /* 03, 19, 0x04C, */ + .long RTC_IRQHandler /* 04, 20, 0x050, */ + .long FLASH_IRQHandler /* 05, 21, 0x054, */ + .long EVWUP_IRQHandler /* 06, 22, 0x058, */ + .long LPWUP_IRQHandler /* 07, 23, 0x05C, */ + .long EXTI0_IRQHandler /* 08, 24, 0x060, */ + .long EXTI1_IRQHandler /* 09, 25, 0x064, */ + .long EXTI2_IRQHandler /* 10, 26, 0x068, */ + .long EXTI3_IRQHandler /* 11, 27, 0x06C, */ + .long EXTI4_IRQHandler /* 12, 28, 0x070, */ + .long EXTI5_IRQHandler /* 13, 29, 0x074, */ + .long EXTI6_IRQHandler /* 14, 30, 0x078, */ + .long EXTI7_IRQHandler /* 15, 31, 0x07C, */ + .long EXTI8_IRQHandler /* 16, 32, 0x080, */ + .long EXTI9_IRQHandler /* 17, 33, 0x084, */ + .long EXTI10_IRQHandler /* 18, 34, 0x088, */ + .long EXTI11_IRQHandler /* 19, 35, 0x08C, */ + .long EXTI12_IRQHandler /* 20, 36, 0x090, */ + .long EXTI13_IRQHandler /* 21, 37, 0x094, */ + .long EXTI14_IRQHandler /* 22, 38, 0x098, */ + .long EXTI15_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long ADC_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long _RESERVED /* 30, 46, 0x0B8, */ + .long _RESERVED /* 31, 47, 0x0BC, */ + .long _RESERVED /* 32, 48, 0x0C0, */ + .long _RESERVED /* 33, 49, 0x0C4, */ + .long _RESERVED /* 34, 50, 0x0C8, */ + .long GPTM0_IRQHandler /* 35, 51, 0x0CC, */ + .long _RESERVED /* 36, 52, 0x0D0, */ + .long SCTM0_IRQHandler /* 37, 53, 0x0D4, */ + .long SCTM1_IRQHandler /* 38, 54, 0x0D8, */ + .long PWM0_IRQHandler /* 39, 55, 0x0DC, */ + .long _RESERVED /* 40, 56, 0x0E0, */ + .long BFTM0_IRQHandler /* 41, 57, 0x0E4, */ + .long BFTM1_IRQHandler /* 42, 58, 0x0E8, */ + .long I2C0_IRQHandler /* 43, 59, 0x0EC, */ + .long I2C1_IRQHandler /* 44, 60, 0x0F0, */ + .long SPI0_IRQHandler /* 45, 61, 0x0F4, */ + .long SPI1_IRQHandler /* 46, 62, 0x0F8, */ + .long USART0_IRQHandler /* 47, 63, 0x0FC, */ + .long _RESERVED /* 48, 64, 0x100, */ + .long UART0_IRQHandler /* 49, 65, 0x104, */ + .long UART1_IRQHandler /* 50, 66, 0x108, */ + .long SCI_IRQHandler /* 51, 67, 0x10C, */ + .long _RESERVED /* 52, 68, 0x110, */ + .long USB_IRQHandler /* 53, 69, 0x114, */ + .long _RESERVED /* 54, 70, 0x118, */ + .long PDMA_CH0_IRQHandler /* 55, 71, 0x11C, */ + .long PDMA_CH1_IRQHandler /* 56, 72, 0x120, */ + .long PDMA_CH2_IRQHandler /* 57, 73, 0x124, */ + .long PDMA_CH3_IRQHandler /* 58, 74, 0x128, */ + .long PDMA_CH4_IRQHandler /* 59, 75, 0x12C, */ + .long PDMA_CH5_IRQHandler /* 60, 76, 0x130, */ + .long _RESERVED /* 61, 77, 0x134, */ + .long _RESERVED /* 62, 78, 0x138, */ + .long _RESERVED /* 63, 79, 0x13C, */ + .long _RESERVED /* 64, 80, 0x140, */ + .long _RESERVED /* 65, 81, 0x144, */ + .long _RESERVED /* 66, 82, 0x148, */ + .long _RESERVED /* 67, 83, 0x14C, */ + .long _RESERVED /* 68, 84, 0x150, */ + .long AES_IRQHandler /* 69, 85, 0x154, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ CKRDY_IRQHandler + IRQ LVD_IRQHandler + IRQ BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ LPWUP_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ EXTI5_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ EXTI10_IRQHandler + IRQ EXTI11_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ EXTI14_IRQHandler + IRQ EXTI15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_IRQHandler + IRQ PDMA_CH1_IRQHandler + IRQ PDMA_CH2_IRQHandler + IRQ PDMA_CH3_IRQHandler + IRQ PDMA_CH4_IRQHandler + IRQ PDMA_CH5_IRQHandler + IRQ AES_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_01.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_01.s new file mode 100644 index 00000000000..623ce3b725f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_01.s @@ -0,0 +1,485 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_gcc_01.s +; Version : $Rev:: 1578 $ +; Date : $Date:: 2019-03-29 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00012366 +*/ + + .equ HT32F1653_54_55_56, 1 + .equ HT32F12365_66, 2 + .equ HT32F12345, 3 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* ---, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* ---, 03, 0x00C, Hard Fault Handler */ + .long MemManage_Handler /* ---, 04, 0x010, MPU Fault Handler */ + .long BusFault_Handler /* ---, 05, 0x014, Bus Fault Handler */ + .long UsageFault_Handler /* ---, 06, 0x018, Usage Fault Handler */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* ---, 11, 0x02C, SVC Handler */ + .long DebugMon_Handler /* ---, 12, 0x030, Debug Monitor Handler */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* ---, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* ---, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long CKRDY_IRQHandler /* 00, 16, 0x040, */ + .long LVD_IRQHandler /* 01, 17, 0x044, */ + .long BOD_IRQHandler /* 02, 18, 0x048, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long WDT_IRQHandler /* 03, 19, 0x04C, */ + .else + .long _RESERVED /* 03, 19, 0x04C, */ + .endif + .long RTC_IRQHandler /* 04, 20, 0x050, */ + .long FLASH_IRQHandler /* 05, 21, 0x054, */ + .long EVWUP_IRQHandler /* 06, 22, 0x058, */ + .long LPWUP_IRQHandler /* 07, 23, 0x05C, */ + .long EXTI0_IRQHandler /* 08, 24, 0x060, */ + .long EXTI1_IRQHandler /* 09, 25, 0x064, */ + .long EXTI2_IRQHandler /* 10, 26, 0x068, */ + .long EXTI3_IRQHandler /* 11, 27, 0x06C, */ + .long EXTI4_IRQHandler /* 12, 28, 0x070, */ + .long EXTI5_IRQHandler /* 13, 29, 0x074, */ + .long EXTI6_IRQHandler /* 14, 30, 0x078, */ + .long EXTI7_IRQHandler /* 15, 31, 0x07C, */ + .long EXTI8_IRQHandler /* 16, 32, 0x080, */ + .long EXTI9_IRQHandler /* 17, 33, 0x084, */ + .long EXTI10_IRQHandler /* 18, 34, 0x088, */ + .long EXTI11_IRQHandler /* 19, 35, 0x08C, */ + .long EXTI12_IRQHandler /* 20, 36, 0x090, */ + .long EXTI13_IRQHandler /* 21, 37, 0x094, */ + .long EXTI14_IRQHandler /* 22, 38, 0x098, */ + .long EXTI15_IRQHandler /* 23, 39, 0x09C, */ + .long COMP_IRQHandler /* 24, 40, 0x0A0, */ + .long ADC_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MCTM0BRK_IRQHandler /* 27, 43, 0x0AC, */ + .long MCTM0UP_IRQHandler /* 28, 44, 0x0B0, */ + .long MCTM0TR_IRQHandler /* 29, 45, 0x0B4, */ + .long MCTM0CC_IRQHandler /* 30, 46, 0x0B8, */ + .long MCTM1BRK_IRQHandler /* 31, 47, 0x0BC, */ + .long MCTM1UP_IRQHandler /* 32, 48, 0x0C0, */ + .long MCTM1TR_IRQHandler /* 33, 49, 0x0C4, */ + .long MCTM1CC_IRQHandler /* 34, 50, 0x0C8, */ + .long GPTM0_IRQHandler /* 35, 51, 0x0CC, */ + .long GPTM1_IRQHandler /* 36, 52, 0x0D0, */ + .long _RESERVED /* 37, 53, 0x0D4, */ + .long _RESERVED /* 38, 54, 0x0D8, */ + .long _RESERVED /* 39, 55, 0x0DC, */ + .long _RESERVED /* 40, 56, 0x0E0, */ + .long BFTM0_IRQHandler /* 41, 57, 0x0E4, */ + .long BFTM1_IRQHandler /* 42, 58, 0x0E8, */ + .long I2C0_IRQHandler /* 43, 59, 0x0EC, */ + .long I2C1_IRQHandler /* 44, 60, 0x0F0, */ + .long SPI0_IRQHandler /* 45, 61, 0x0F4, */ + .long SPI1_IRQHandler /* 46, 62, 0x0F8, */ + .long USART0_IRQHandler /* 47, 63, 0x0FC, */ + .long USART1_IRQHandler /* 48, 64, 0x100, */ + .long UART0_IRQHandler /* 49, 65, 0x104, */ + .long UART1_IRQHandler /* 50, 66, 0x108, */ + .if (USE_HT32_CHIP==HT32F12345) + .long _RESERVED /* 51, 67, 0x10C, */ + .else + .long SCI_IRQHandler /* 51, 67, 0x10C, */ + .endif + .long I2S_IRQHandler /* 52, 68, 0x110, */ + .long USB_IRQHandler /* 53, 69, 0x114, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long _RESERVED /* 54, 70, 0x118, */ + .else + .long SDIO_IRQHandler /* 54, 70, 0x118, */ + .endif + .long PDMA_CH0_IRQHandler /* 55, 71, 0x11C, */ + .long PDMA_CH1_IRQHandler /* 56, 72, 0x120, */ + .long PDMA_CH2_IRQHandler /* 57, 73, 0x124, */ + .long PDMA_CH3_IRQHandler /* 58, 74, 0x128, */ + .long PDMA_CH4_IRQHandler /* 59, 75, 0x12C, */ + .long PDMA_CH5_IRQHandler /* 60, 76, 0x130, */ + .long PDMA_CH6_IRQHandler /* 61, 77, 0x134, */ + .long PDMA_CH7_IRQHandler /* 62, 78, 0x138, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long _RESERVED /* 63, 79, 0x13C, */ + .long _RESERVED /* 64, 80, 0x140, */ + .long _RESERVED /* 65, 81, 0x144, */ + .long _RESERVED /* 66, 82, 0x148, */ + .else + .long PDMA_CH8_IRQHandler /* 63, 79, 0x13C, */ + .long PDMA_CH9_IRQHandler /* 64, 80, 0x140, */ + .long PDMA_CH10_IRQHandler /* 65, 81, 0x144, */ + .long PDMA_CH11_IRQHandler /* 66, 82, 0x148, */ + .endif + .if (USE_HT32_CHIP==HT32F12365_66) + .long CSIF_IRQHandler /* 67, 83, 0x14C, */ + .else + .long _RESERVED /* 67, 83, 0x14C, */ + .endif + .long EBI_IRQHandler /* 68, 84, 0x150, */ + .if (USE_HT32_CHIP==HT32F12365_66) + .long AES_IRQHandler /* 69, 85, 0x154, */ + .endif + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .else + LDR R0, =BootProcess + BLX R0 + .endif + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .else + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .endif + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ CKRDY_IRQHandler + IRQ LVD_IRQHandler + IRQ BOD_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ LPWUP_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ EXTI5_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ EXTI10_IRQHandler + IRQ EXTI11_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ EXTI14_IRQHandler + IRQ EXTI15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0BRK_IRQHandler + IRQ MCTM0UP_IRQHandler + IRQ MCTM0TR_IRQHandler + IRQ MCTM0CC_IRQHandler + IRQ MCTM1BRK_IRQHandler + IRQ MCTM1UP_IRQHandler + IRQ MCTM1TR_IRQHandler + IRQ MCTM1CC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ GPTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ SDIO_IRQHandler + IRQ PDMA_CH0_IRQHandler + IRQ PDMA_CH1_IRQHandler + IRQ PDMA_CH2_IRQHandler + IRQ PDMA_CH3_IRQHandler + IRQ PDMA_CH4_IRQHandler + IRQ PDMA_CH5_IRQHandler + IRQ PDMA_CH6_IRQHandler + IRQ PDMA_CH7_IRQHandler + IRQ PDMA_CH8_IRQHandler + IRQ PDMA_CH9_IRQHandler + IRQ PDMA_CH10_IRQHandler + IRQ PDMA_CH11_IRQHandler + IRQ CSIF_IRQHandler + IRQ EBI_IRQHandler + IRQ AES_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_03.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_03.s new file mode 100644 index 00000000000..652eb110610 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/GCC/startup_ht32f1xxxx_gcc_03.s @@ -0,0 +1,428 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_gcc_03.s +; Version : $Rev:: 1771 $ +; Date : $Date:: 2019-07-25 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F12364 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <16=> HT32F12364 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00012364 +*/ + + .equ HT32F12364, 16 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* ---, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* ---, 03, 0x00C, Hard Fault Handler */ + .long MemManage_Handler /* ---, 04, 0x010, MPU Fault Handler */ + .long BusFault_Handler /* ---, 05, 0x014, Bus Fault Handler */ + .long UsageFault_Handler /* ---, 06, 0x018, Usage Fault Handler */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* ---, 11, 0x02C, SVC Handler */ + .long DebugMon_Handler /* ---, 12, 0x030, Debug Monitor Handler */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* ---, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* ---, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long CKRDY_IRQHandler /* 00, 16, 0x040, */ + .long LVD_IRQHandler /* 01, 17, 0x044, */ + .long BOD_IRQHandler /* 02, 18, 0x048, */ + .long _RESERVED /* 03, 19, 0x04C, */ + .long RTC_IRQHandler /* 04, 20, 0x050, */ + .long FLASH_IRQHandler /* 05, 21, 0x054, */ + .long EVWUP_IRQHandler /* 06, 22, 0x058, */ + .long LPWUP_IRQHandler /* 07, 23, 0x05C, */ + .long EXTI0_IRQHandler /* 08, 24, 0x060, */ + .long EXTI1_IRQHandler /* 09, 25, 0x064, */ + .long EXTI2_IRQHandler /* 10, 26, 0x068, */ + .long EXTI3_IRQHandler /* 11, 27, 0x06C, */ + .long EXTI4_IRQHandler /* 12, 28, 0x070, */ + .long EXTI5_IRQHandler /* 13, 29, 0x074, */ + .long EXTI6_IRQHandler /* 14, 30, 0x078, */ + .long EXTI7_IRQHandler /* 15, 31, 0x07C, */ + .long EXTI8_IRQHandler /* 16, 32, 0x080, */ + .long EXTI9_IRQHandler /* 17, 33, 0x084, */ + .long EXTI10_IRQHandler /* 18, 34, 0x088, */ + .long EXTI11_IRQHandler /* 19, 35, 0x08C, */ + .long EXTI12_IRQHandler /* 20, 36, 0x090, */ + .long EXTI13_IRQHandler /* 21, 37, 0x094, */ + .long EXTI14_IRQHandler /* 22, 38, 0x098, */ + .long EXTI15_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long ADC_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long _RESERVED /* 30, 46, 0x0B8, */ + .long _RESERVED /* 31, 47, 0x0BC, */ + .long _RESERVED /* 32, 48, 0x0C0, */ + .long _RESERVED /* 33, 49, 0x0C4, */ + .long _RESERVED /* 34, 50, 0x0C8, */ + .long GPTM0_IRQHandler /* 35, 51, 0x0CC, */ + .long _RESERVED /* 36, 52, 0x0D0, */ + .long SCTM0_IRQHandler /* 37, 53, 0x0D4, */ + .long SCTM1_IRQHandler /* 38, 54, 0x0D8, */ + .long PWM0_IRQHandler /* 39, 55, 0x0DC, */ + .long _RESERVED /* 40, 56, 0x0E0, */ + .long BFTM0_IRQHandler /* 41, 57, 0x0E4, */ + .long BFTM1_IRQHandler /* 42, 58, 0x0E8, */ + .long I2C0_IRQHandler /* 43, 59, 0x0EC, */ + .long I2C1_IRQHandler /* 44, 60, 0x0F0, */ + .long SPI0_IRQHandler /* 45, 61, 0x0F4, */ + .long SPI1_IRQHandler /* 46, 62, 0x0F8, */ + .long USART0_IRQHandler /* 47, 63, 0x0FC, */ + .long _RESERVED /* 48, 64, 0x100, */ + .long UART0_IRQHandler /* 49, 65, 0x104, */ + .long UART1_IRQHandler /* 50, 66, 0x108, */ + .long SCI_IRQHandler /* 51, 67, 0x10C, */ + .long _RESERVED /* 52, 68, 0x110, */ + .long USB_IRQHandler /* 53, 69, 0x114, */ + .long _RESERVED /* 54, 70, 0x118, */ + .long PDMA_CH0_IRQHandler /* 55, 71, 0x11C, */ + .long PDMA_CH1_IRQHandler /* 56, 72, 0x120, */ + .long PDMA_CH2_IRQHandler /* 57, 73, 0x124, */ + .long PDMA_CH3_IRQHandler /* 58, 74, 0x128, */ + .long PDMA_CH4_IRQHandler /* 59, 75, 0x12C, */ + .long PDMA_CH5_IRQHandler /* 60, 76, 0x130, */ + .long _RESERVED /* 61, 77, 0x134, */ + .long _RESERVED /* 62, 78, 0x138, */ + .long _RESERVED /* 63, 79, 0x13C, */ + .long _RESERVED /* 64, 80, 0x140, */ + .long _RESERVED /* 65, 81, 0x144, */ + .long _RESERVED /* 66, 82, 0x148, */ + .long _RESERVED /* 67, 83, 0x14C, */ + .long _RESERVED /* 68, 84, 0x150, */ + .long AES_IRQHandler /* 69, 85, 0x154, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ CKRDY_IRQHandler + IRQ LVD_IRQHandler + IRQ BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ LPWUP_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ EXTI5_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ EXTI10_IRQHandler + IRQ EXTI11_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ EXTI14_IRQHandler + IRQ EXTI15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_IRQHandler + IRQ PDMA_CH1_IRQHandler + IRQ PDMA_CH2_IRQHandler + IRQ PDMA_CH3_IRQHandler + IRQ PDMA_CH4_IRQHandler + IRQ PDMA_CH5_IRQHandler + IRQ AES_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_01.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_01.s new file mode 100644 index 00000000000..331f561dc03 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_01.s @@ -0,0 +1,416 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_iar_01.s +; Version : $Rev:: 1774 $ +; Date : $Date:: 2019-07-25 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 + +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012366 + +HT32F1653_54_55_56 EQU 1 +HT32F12365_66 EQU 2 +HT32F12345 EQU 3 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD WDT_IRQHandler ; 03, 19, 0x04C, + ELSE + DCD _RESERVED ; 03, 19, 0x04C, + ENDIF + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD COMP_IRQHandler ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MCTM0BRK_IRQHandler ; 27, 43, 0x0AC, + DCD MCTM0UP_IRQHandler ; 28, 44, 0x0B0, + DCD MCTM0TR_IRQHandler ; 29, 45, 0x0B4, + DCD MCTM0CC_IRQHandler ; 30, 46, 0x0B8, + DCD MCTM1BRK_IRQHandler ; 31, 47, 0x0BC, + DCD MCTM1UP_IRQHandler ; 32, 48, 0x0C0, + DCD MCTM1TR_IRQHandler ; 33, 49, 0x0C4, + DCD MCTM1CC_IRQHandler ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD GPTM1_IRQHandler ; 36, 52, 0x0D0, + DCD _RESERVED ; 37, 53, 0x0D4, + DCD _RESERVED ; 38, 54, 0x0D8, + DCD _RESERVED ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD USART1_IRQHandler ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + IF (USE_HT32_CHIP=HT32F12345) + DCD _RESERVED ; 51, 67, 0x10C, + ELSE + DCD SCI_IRQHandler ; 51, 67, 0x10C, + ENDIF + DCD I2S_IRQHandler ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 54, 70, 0x118, + ELSE + DCD SDIO_IRQHandler ; 54, 70, 0x118, + ENDIF + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD PDMA_CH6_IRQHandler ; 61, 77, 0x134, + DCD PDMA_CH7_IRQHandler ; 62, 78, 0x138, + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + ELSE + DCD PDMA_CH8_IRQHandler ; 63, 79, 0x13C, + DCD PDMA_CH9_IRQHandler ; 64, 80, 0x140, + DCD PDMA_CH10_IRQHandler ; 65, 81, 0x144, + DCD PDMA_CH11_IRQHandler ; 66, 82, 0x148, + ENDIF + IF (USE_HT32_CHIP=HT32F12365_66) + DCD CSIF_IRQHandler ; 67, 83, 0x14C, + ELSE + DCD _RESERVED ; 67, 83, 0x14C, + ENDIF + DCD EBI_IRQHandler ; 68, 84, 0x150, + IF (USE_HT32_CHIP=HT32F12365_66) + DCD AES_IRQHandler ; 69, 85, 0x154, + ENDIF + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE + LDR R0, =BootProcess + BLX R0 + ENDIF + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + IF (USE_HT32_CHIP=HT32F1653_54_55_56) + ELSE +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDIF + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK CKRDY_IRQHandler + PUBWEAK LVD_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK LPWUP_IRQHandler + PUBWEAK EXTI0_IRQHandler + PUBWEAK EXTI1_IRQHandler + PUBWEAK EXTI2_IRQHandler + PUBWEAK EXTI3_IRQHandler + PUBWEAK EXTI4_IRQHandler + PUBWEAK EXTI5_IRQHandler + PUBWEAK EXTI6_IRQHandler + PUBWEAK EXTI7_IRQHandler + PUBWEAK EXTI8_IRQHandler + PUBWEAK EXTI9_IRQHandler + PUBWEAK EXTI10_IRQHandler + PUBWEAK EXTI11_IRQHandler + PUBWEAK EXTI12_IRQHandler + PUBWEAK EXTI13_IRQHandler + PUBWEAK EXTI14_IRQHandler + PUBWEAK EXTI15_IRQHandler + PUBWEAK COMP_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK MCTM0BRK_IRQHandler + PUBWEAK MCTM0UP_IRQHandler + PUBWEAK MCTM0TR_IRQHandler + PUBWEAK MCTM0CC_IRQHandler + PUBWEAK MCTM1BRK_IRQHandler + PUBWEAK MCTM1UP_IRQHandler + PUBWEAK MCTM1TR_IRQHandler + PUBWEAK MCTM1CC_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK GPTM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK USART1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK SCI_IRQHandler + PUBWEAK I2S_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK SDIO_IRQHandler + PUBWEAK PDMA_CH0_IRQHandler + PUBWEAK PDMA_CH1_IRQHandler + PUBWEAK PDMA_CH2_IRQHandler + PUBWEAK PDMA_CH3_IRQHandler + PUBWEAK PDMA_CH4_IRQHandler + PUBWEAK PDMA_CH5_IRQHandler + PUBWEAK PDMA_CH6_IRQHandler + PUBWEAK PDMA_CH7_IRQHandler + PUBWEAK PDMA_CH8_IRQHandler + PUBWEAK PDMA_CH9_IRQHandler + PUBWEAK PDMA_CH10_IRQHandler + PUBWEAK PDMA_CH11_IRQHandler + PUBWEAK CSIF_IRQHandler + PUBWEAK EBI_IRQHandler + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +WDT_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0BRK_IRQHandler +MCTM0UP_IRQHandler +MCTM0TR_IRQHandler +MCTM0CC_IRQHandler +MCTM1BRK_IRQHandler +MCTM1UP_IRQHandler +MCTM1TR_IRQHandler +MCTM1CC_IRQHandler +GPTM0_IRQHandler +GPTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +SDIO_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +PDMA_CH6_IRQHandler +PDMA_CH7_IRQHandler +PDMA_CH8_IRQHandler +PDMA_CH9_IRQHandler +PDMA_CH10_IRQHandler +PDMA_CH11_IRQHandler +CSIF_IRQHandler +EBI_IRQHandler +AES_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_03.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_03.s new file mode 100644 index 00000000000..dc390128455 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/IAR/startup_ht32f1xxxx_iar_03.s @@ -0,0 +1,339 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_iar_03.s +; Version : $Rev:: 1774 $ +; Date : $Date:: 2019-07-25 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F12364 + +;// HT32 Device +;// <0=> By Project Asm Define +;// <16=> HT32F12364 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00012364 + +HT32F12364 EQU 16 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; ---, 02, 0x008, NMI Handler + DCD HardFault_Handler ; ---, 03, 0x00C, Hard Fault Handler + DCD MemManage_Handler ; ---, 04, 0x010, Memory Management Fault Handler + DCD BusFault_Handler ; ---, 05, 0x014, Bus Fault Handler + DCD UsageFault_Handler ; ---, 06, 0x018, Usage Fault Handler + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; ---, 11, 0x02C, SVC Handler + DCD DebugMon_Handler ; ---, 12, 0x030, Debug Monitor Handler + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; ---, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; ---, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD CKRDY_IRQHandler ; 00, 16, 0x040, + DCD LVD_IRQHandler ; 01, 17, 0x044, + DCD BOD_IRQHandler ; 02, 18, 0x048, + DCD _RESERVED ; 03, 19, 0x04C, + DCD RTC_IRQHandler ; 04, 20, 0x050, + DCD FLASH_IRQHandler ; 05, 21, 0x054, + DCD EVWUP_IRQHandler ; 06, 22, 0x058, + DCD LPWUP_IRQHandler ; 07, 23, 0x05C, + DCD EXTI0_IRQHandler ; 08, 24, 0x060, + DCD EXTI1_IRQHandler ; 09, 25, 0x064, + DCD EXTI2_IRQHandler ; 10, 26, 0x068, + DCD EXTI3_IRQHandler ; 11, 27, 0x06C, + DCD EXTI4_IRQHandler ; 12, 28, 0x070, + DCD EXTI5_IRQHandler ; 13, 29, 0x074, + DCD EXTI6_IRQHandler ; 14, 30, 0x078, + DCD EXTI7_IRQHandler ; 15, 31, 0x07C, + DCD EXTI8_IRQHandler ; 16, 32, 0x080, + DCD EXTI9_IRQHandler ; 17, 33, 0x084, + DCD EXTI10_IRQHandler ; 18, 34, 0x088, + DCD EXTI11_IRQHandler ; 19, 35, 0x08C, + DCD EXTI12_IRQHandler ; 20, 36, 0x090, + DCD EXTI13_IRQHandler ; 21, 37, 0x094, + DCD EXTI14_IRQHandler ; 22, 38, 0x098, + DCD EXTI15_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD ADC_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + DCD _RESERVED ; 32, 48, 0x0C0, + DCD _RESERVED ; 33, 49, 0x0C4, + DCD _RESERVED ; 34, 50, 0x0C8, + DCD GPTM0_IRQHandler ; 35, 51, 0x0CC, + DCD _RESERVED ; 36, 52, 0x0D0, + DCD SCTM0_IRQHandler ; 37, 53, 0x0D4, + DCD SCTM1_IRQHandler ; 38, 54, 0x0D8, + DCD PWM0_IRQHandler ; 39, 55, 0x0DC, + DCD _RESERVED ; 40, 56, 0x0E0, + DCD BFTM0_IRQHandler ; 41, 57, 0x0E4, + DCD BFTM1_IRQHandler ; 42, 58, 0x0E8, + DCD I2C0_IRQHandler ; 43, 59, 0x0EC, + DCD I2C1_IRQHandler ; 44, 60, 0x0F0, + DCD SPI0_IRQHandler ; 45, 61, 0x0F4, + DCD SPI1_IRQHandler ; 46, 62, 0x0F8, + DCD USART0_IRQHandler ; 47, 63, 0x0FC, + DCD _RESERVED ; 48, 64, 0x100, + DCD UART0_IRQHandler ; 49, 65, 0x104, + DCD UART1_IRQHandler ; 50, 66, 0x108, + DCD SCI_IRQHandler ; 51, 67, 0x10C, + DCD _RESERVED ; 52, 68, 0x110, + DCD USB_IRQHandler ; 53, 69, 0x114, + DCD _RESERVED ; 54, 70, 0x118, + DCD PDMA_CH0_IRQHandler ; 55, 71, 0x11C, + DCD PDMA_CH1_IRQHandler ; 56, 72, 0x120, + DCD PDMA_CH2_IRQHandler ; 57, 73, 0x124, + DCD PDMA_CH3_IRQHandler ; 58, 74, 0x128, + DCD PDMA_CH4_IRQHandler ; 59, 75, 0x12C, + DCD PDMA_CH5_IRQHandler ; 60, 76, 0x130, + DCD _RESERVED ; 61, 77, 0x134, + DCD _RESERVED ; 62, 78, 0x138, + DCD _RESERVED ; 63, 79, 0x13C, + DCD _RESERVED ; 64, 80, 0x140, + DCD _RESERVED ; 65, 81, 0x144, + DCD _RESERVED ; 66, 82, 0x148, + DCD _RESERVED ; 67, 83, 0x14C, + DCD _RESERVED ; 68, 84, 0x150, + DCD AES_IRQHandler ; 69, 85, 0x154, + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK CKRDY_IRQHandler + PUBWEAK LVD_IRQHandler + PUBWEAK BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK LPWUP_IRQHandler + PUBWEAK EXTI0_IRQHandler + PUBWEAK EXTI1_IRQHandler + PUBWEAK EXTI2_IRQHandler + PUBWEAK EXTI3_IRQHandler + PUBWEAK EXTI4_IRQHandler + PUBWEAK EXTI5_IRQHandler + PUBWEAK EXTI6_IRQHandler + PUBWEAK EXTI7_IRQHandler + PUBWEAK EXTI8_IRQHandler + PUBWEAK EXTI9_IRQHandler + PUBWEAK EXTI10_IRQHandler + PUBWEAK EXTI11_IRQHandler + PUBWEAK EXTI12_IRQHandler + PUBWEAK EXTI13_IRQHandler + PUBWEAK EXTI14_IRQHandler + PUBWEAK EXTI15_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK SCI_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK PDMA_CH0_IRQHandler + PUBWEAK PDMA_CH1_IRQHandler + PUBWEAK PDMA_CH2_IRQHandler + PUBWEAK PDMA_CH3_IRQHandler + PUBWEAK PDMA_CH4_IRQHandler + PUBWEAK PDMA_CH5_IRQHandler + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CKRDY_IRQHandler +LVD_IRQHandler +BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +LPWUP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +USB_IRQHandler +PDMA_CH0_IRQHandler +PDMA_CH1_IRQHandler +PDMA_CH2_IRQHandler +PDMA_CH3_IRQHandler +PDMA_CH4_IRQHandler +PDMA_CH5_IRQHandler +AES_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/SEGGER_THUMB_Startup.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/SEGGER_THUMB_Startup.s new file mode 100644 index 00000000000..63a379c8042 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/SEGGER_THUMB_Startup.s @@ -0,0 +1,435 @@ +// ********************************************************************** +// * SEGGER Microcontroller GmbH * +// * The Embedded Experts * +// ********************************************************************** +// * * +// * (c) 2014 - 2018 SEGGER Microcontroller GmbH * +// * (c) 2001 - 2018 Rowley Associates Limited * +// * * +// * www.segger.com Support: support@segger.com * +// * * +// ********************************************************************** +// * * +// * All rights reserved. * +// * * +// * Redistribution and use in source and binary forms, with or * +// * without modification, are permitted provided that the following * +// * conditions are met: * +// * * +// * - Redistributions of source code must retain the above copyright * +// * notice, this list of conditions and the following disclaimer. * +// * * +// * - Neither the name of SEGGER Microcontroller GmbH * +// * nor the names of its contributors may be used to endorse or * +// * promote products derived from this software without specific * +// * prior written permission. * +// * * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +// * DISCLAIMED. * +// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +// * DAMAGE. * +// * * +// ********************************************************************** +// Preprocessor Definitions +// ------------------------ +// +// FULL_LIBRARY +// +// If defined then +// - argc, argv are setup by the debug_getargs. +// - the exit symbol is defined and executes on return from main. +// - the exit symbol calls destructors, atexit functions and then debug_exit. +// +// If not defined then +// - argc and argv are zero. +// - the exit symbol is defined, executes on return from main and loops +// + + .syntax unified + + .section .segger.init.__SEGGER_init_lzss, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_lzss +.thumb_func +__SEGGER_init_lzss: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source stream + adds r4, r4, #8 +2: + ldrb r2, [r1] + adds r1, r1, #1 + tst r2, r2 + beq 9f @ 0 -> end of table + cmp r2, #0x80 + bcc 1f @ +ve -> literal run +// +// -ve -> copy run +// +// r0 = pointer to output stream +// r1 = pointer to input stream +// r2 = run length +// r3 = copy byte +// r4 = pointer to initialization table +// +3: + subs r2, r2, #0x80 // convert to run length + beq 10f + ldrb r3, [r1] // r3 = first byte of distance + adds r1, r1, #1 + cmp r3, #0x80 + bcc 5f // r3 < 128, short run + subs r3, r3, #0x80 // Adjust to recover true run length high byte + lsls r3, r3, #8 // Prepare to fuse + ldrb r5, [r1] // extract run length low byte + adds r1, r1, #1 + adds r3, r3, r5 // construct run length +5: + subs r5, r0, r3 // source of where to copy from +4: + ldrb r3, [r5] // source byte of run + strb r3, [r0] // store to destination + adds r5, r5, #1 + adds r0, r0, #1 + subs r2, r2, #1 + bne 4b + b 2b +// +// +ve -> literal run +// +// r0 = pointer to output stream +// r1 = pointer to input stream +// r2 = run length +// r3 = copy byte +// r4 = pointer to initialization table +// +1: + ldrb r3, [r1] // source byte of run + adds r1, r1, #1 + strb r3, [r0] // store to destination + adds r0, r0, #1 + subs r2, r2, #1 + bne 1b + b 2b +9: + bx lr +10: + b 10b + + .section .segger.init.__SEGGER_init_zero, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_zero +.thumb_func +__SEGGER_init_zero: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ size + adds r4, r4, #8 + tst r1, r1 + beq 2f + movs r2, #0 +1: + strb r2, [r0] + adds r0, r0, #1 + subs r1, r1, #1 + bne 1b +2: + bx lr + + .section .segger.init.__SEGGER_init_copy, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_copy +.thumb_func +__SEGGER_init_copy: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source + ldr r2, [r4, #8] @ size + adds r4, r4, #12 + tst r2, r2 + beq 2f +1: + ldrb r3, [r1] + strb r3, [r0] + adds r0, r0, #1 + adds r1, r1, #1 + subs r2, r2, #1 + bne 1b +2: + bx lr + + .section .segger.init.__SEGGER_init_pack, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_pack +.thumb_func +__SEGGER_init_pack: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source stream + adds r4, r4, #8 +1: + ldrb r2, [r1] + adds r1, r1, #1 + cmp r2, #0x80 + beq 4f + bcc 3f + ldrb r3, [r1] @ byte to replicate + adds r1, r1, #1 + negs r2, r2 + adds r2, r2, #255 + adds r2, r2, #1 +2: + strb r3, [r0] + adds r0, r0, #1 + subs r2, r2, #1 + bpl 2b + b 1b + +3: @ 1+n literal bytes + ldrb r3, [r1] + strb r3, [r0] + adds r0, r0, #1 + adds r1, r1, #1 + subs r2, r2, #1 + bpl 3b + b 1b +4: + bx lr + + .section .segger.init.__SEGGER_init_zpak, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_zpak +.thumb_func +__SEGGER_init_zpak: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source stream + ldr r2, [r4, #8] @ size + adds r4, r4, #12 @ skip table entries +1: + ldrb r3, [r1] @ get control byte from source stream + adds r1, r1, #1 + movs r6, #8 +2: + movs r5, #0 @ prepare zero filler + lsrs r3, r3, #1 @ get byte control flag + bcs 3f @ carry set -> zero filler + ldrb r5, [r1] @ get literal byte from source stream + adds r1, r1, #1 +3: + strb r5, [r0] @ store initialization byte + adds r0, r0, #1 + subs r2, r2, #1 @ size -= 1 + beq 4f @ exit when destination filled + subs r6, r6, #1 @ decrement bit count + bne 2b @ still within this control byte + b 1b @ get next control byte +4: + bx lr + +#ifndef APP_ENTRY_POINT +#define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE +#define ARGSSPACE 128 +#endif + + .global _start + .extern APP_ENTRY_POINT + .global exit + .weak exit + +#ifdef INITIALIZE_USER_SECTIONS + .extern InitializeUserMemorySections +#endif + + .section .init, "ax" + .code 16 + .align 1 + .thumb_func + +_start: + ldr r0, = __stack_end__ + mov sp, r0 + ldr r4, =__SEGGER_init_table__ +1: + ldr r0, [r4] + adds r4, r4, #4 + tst r0, r0 + beq 2f + blx r0 + b 1b +2: + + /* Initialize the heap */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + subs r1, r1, r0 + cmp r1, #8 + blt 1f + movs r2, #0 + str r2, [r0] + adds r0, r0, #4 + str r1, [r0] +1: + +#ifdef INITIALIZE_USER_SECTIONS + ldr r2, =InitializeUserMemorySections + blx r2 +#endif + + /* Call constructors */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0] + adds r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b ctor_loop +ctor_end: + + /* Setup initial call frame */ + movs r0, #0 + mov lr, r0 + mov r12, sp + + .type start, function +start: + /* Jump to application entry point */ +#ifdef FULL_LIBRARY + movs r0, #ARGSSPACE + ldr r1, =args + ldr r2, =debug_getargs + blx r2 + ldr r1, =args +#else + movs r0, #0 + movs r1, #0 +#endif + ldr r2, =APP_ENTRY_POINT + blx r2 + + .thumb_func +exit: +#ifdef FULL_LIBRARY + mov r5, r0 // save the exit parameter/return result + + /* Call destructors */ + ldr r0, =__dtors_start__ + ldr r1, =__dtors_end__ +dtor_loop: + cmp r0, r1 + beq dtor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b dtor_loop +dtor_end: + + /* Call atexit functions */ + ldr r2, =_execute_at_exit_fns + blx r2 + + /* Call debug_exit with return result/exit parameter */ + mov r0, r5 + ldr r2, =debug_exit + blx r2 +#endif + + /* Returned from application entry point, loop forever. */ +exit_loop: + b exit_loop + + // default C/C++ library helpers + +.macro HELPER helper_name + .section .text.\helper_name, "ax", %progbits + .global \helper_name + .align 1 + .weak \helper_name +\helper_name: + .thumb_func +.endm + +.macro JUMPTO name +#if defined(__thumb__) && !defined(__thumb2__) + mov r12, r0 + ldr r0, =\name + push {r0} + mov r0, r12 + pop {pc} +#else + b \name +#endif +.endm + +HELPER __aeabi_read_tp + ldr r0, =__tbss_start__-8 + bx lr +HELPER abort + b . +HELPER __assert + b . +HELPER __aeabi_assert + b . +HELPER __sync_synchronize + bx lr +HELPER __getchar + JUMPTO debug_getchar +HELPER __putchar + JUMPTO debug_putchar +HELPER __open + JUMPTO debug_fopen +HELPER __close + JUMPTO debug_fclose +HELPER __write + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fwrite +HELPER __read + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fread +HELPER __seek + push {r4, lr} + mov r4, r0 + bl debug_fseek + cmp r0, #0 + bne 1f + mov r0, r4 + bl debug_ftell + pop {r4, pc} +1: + ldr r0, =-1 + pop {r4, pc} + // char __user_locale_name_buffer[]; + .section .bss.__user_locale_name_buffer, "aw", %nobits + .global __user_locale_name_buffer + .weak __user_locale_name_buffer + __user_locale_name_buffer: + .word 0x0 + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_01.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_01.s new file mode 100644 index 00000000000..5f60bca990d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_01.s @@ -0,0 +1,391 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_es_01.s +; Version : $Rev:: 1578 $ +; Date : $Date:: 2019-03-29 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F1653, HT32F1654 +; HT32F1655, HT32F1656 +; HT32F12365, HT32F12366 +; HT32F12345 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F1653/1654/1655/1656 +;// <2=> HT32F12365/12366 +;// <3=> HT32F12345 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00012366 +*/ + + .equ HT32F1653_54_55_56, 1 + .equ HT32F12365_66, 2 + .equ HT32F12345, 3 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* ---, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* ---, 03, 0x00C, Hard Fault Handler */ + .long MemManage_Handler /* ---, 04, 0x010, MPU Fault Handler */ + .long BusFault_Handler /* ---, 05, 0x014, Bus Fault Handler */ + .long UsageFault_Handler /* ---, 06, 0x018, Usage Fault Handler */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* ---, 11, 0x02C, SVC Handler */ + .long DebugMon_Handler /* ---, 12, 0x030, Debug Monitor Handler */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* ---, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* ---, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long CKRDY_IRQHandler /* 00, 16, 0x040, */ + .long LVD_IRQHandler /* 01, 17, 0x044, */ + .long BOD_IRQHandler /* 02, 18, 0x048, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long WDT_IRQHandler /* 03, 19, 0x04C, */ + .else + .long _RESERVED /* 03, 19, 0x04C, */ + .endif + .long RTC_IRQHandler /* 04, 20, 0x050, */ + .long FLASH_IRQHandler /* 05, 21, 0x054, */ + .long EVWUP_IRQHandler /* 06, 22, 0x058, */ + .long LPWUP_IRQHandler /* 07, 23, 0x05C, */ + .long EXTI0_IRQHandler /* 08, 24, 0x060, */ + .long EXTI1_IRQHandler /* 09, 25, 0x064, */ + .long EXTI2_IRQHandler /* 10, 26, 0x068, */ + .long EXTI3_IRQHandler /* 11, 27, 0x06C, */ + .long EXTI4_IRQHandler /* 12, 28, 0x070, */ + .long EXTI5_IRQHandler /* 13, 29, 0x074, */ + .long EXTI6_IRQHandler /* 14, 30, 0x078, */ + .long EXTI7_IRQHandler /* 15, 31, 0x07C, */ + .long EXTI8_IRQHandler /* 16, 32, 0x080, */ + .long EXTI9_IRQHandler /* 17, 33, 0x084, */ + .long EXTI10_IRQHandler /* 18, 34, 0x088, */ + .long EXTI11_IRQHandler /* 19, 35, 0x08C, */ + .long EXTI12_IRQHandler /* 20, 36, 0x090, */ + .long EXTI13_IRQHandler /* 21, 37, 0x094, */ + .long EXTI14_IRQHandler /* 22, 38, 0x098, */ + .long EXTI15_IRQHandler /* 23, 39, 0x09C, */ + .long COMP_IRQHandler /* 24, 40, 0x0A0, */ + .long ADC_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MCTM0BRK_IRQHandler /* 27, 43, 0x0AC, */ + .long MCTM0UP_IRQHandler /* 28, 44, 0x0B0, */ + .long MCTM0TR_IRQHandler /* 29, 45, 0x0B4, */ + .long MCTM0CC_IRQHandler /* 30, 46, 0x0B8, */ + .long MCTM1BRK_IRQHandler /* 31, 47, 0x0BC, */ + .long MCTM1UP_IRQHandler /* 32, 48, 0x0C0, */ + .long MCTM1TR_IRQHandler /* 33, 49, 0x0C4, */ + .long MCTM1CC_IRQHandler /* 34, 50, 0x0C8, */ + .long GPTM0_IRQHandler /* 35, 51, 0x0CC, */ + .long GPTM1_IRQHandler /* 36, 52, 0x0D0, */ + .long _RESERVED /* 37, 53, 0x0D4, */ + .long _RESERVED /* 38, 54, 0x0D8, */ + .long _RESERVED /* 39, 55, 0x0DC, */ + .long _RESERVED /* 40, 56, 0x0E0, */ + .long BFTM0_IRQHandler /* 41, 57, 0x0E4, */ + .long BFTM1_IRQHandler /* 42, 58, 0x0E8, */ + .long I2C0_IRQHandler /* 43, 59, 0x0EC, */ + .long I2C1_IRQHandler /* 44, 60, 0x0F0, */ + .long SPI0_IRQHandler /* 45, 61, 0x0F4, */ + .long SPI1_IRQHandler /* 46, 62, 0x0F8, */ + .long USART0_IRQHandler /* 47, 63, 0x0FC, */ + .long USART1_IRQHandler /* 48, 64, 0x100, */ + .long UART0_IRQHandler /* 49, 65, 0x104, */ + .long UART1_IRQHandler /* 50, 66, 0x108, */ + .if (USE_HT32_CHIP==HT32F12345) + .long _RESERVED /* 51, 67, 0x10C, */ + .else + .long SCI_IRQHandler /* 51, 67, 0x10C, */ + .endif + .long I2S_IRQHandler /* 52, 68, 0x110, */ + .long USB_IRQHandler /* 53, 69, 0x114, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long _RESERVED /* 54, 70, 0x118, */ + .else + .long SDIO_IRQHandler /* 54, 70, 0x118, */ + .endif + .long PDMA_CH0_IRQHandler /* 55, 71, 0x11C, */ + .long PDMA_CH1_IRQHandler /* 56, 72, 0x120, */ + .long PDMA_CH2_IRQHandler /* 57, 73, 0x124, */ + .long PDMA_CH3_IRQHandler /* 58, 74, 0x128, */ + .long PDMA_CH4_IRQHandler /* 59, 75, 0x12C, */ + .long PDMA_CH5_IRQHandler /* 60, 76, 0x130, */ + .long PDMA_CH6_IRQHandler /* 61, 77, 0x134, */ + .long PDMA_CH7_IRQHandler /* 62, 78, 0x138, */ + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .long _RESERVED /* 63, 79, 0x13C, */ + .long _RESERVED /* 64, 80, 0x140, */ + .long _RESERVED /* 65, 81, 0x144, */ + .long _RESERVED /* 66, 82, 0x148, */ + .else + .long PDMA_CH8_IRQHandler /* 63, 79, 0x13C, */ + .long PDMA_CH9_IRQHandler /* 64, 80, 0x140, */ + .long PDMA_CH10_IRQHandler /* 65, 81, 0x144, */ + .long PDMA_CH11_IRQHandler /* 66, 82, 0x148, */ + .endif + .if (USE_HT32_CHIP==HT32F12365_66) + .long CSIF_IRQHandler /* 67, 83, 0x14C, */ + .else + .long _RESERVED /* 67, 83, 0x14C, */ + .endif + .long EBI_IRQHandler /* 68, 84, 0x150, */ + .if (USE_HT32_CHIP==HT32F12365_66) + .long AES_IRQHandler /* 69, 85, 0x154, */ + .endif + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .else + LDR R0, =BootProcess + BLX R0 + .endif + LDR R0, =SystemInit + BLX R0 + BL _start + .if (USE_HT32_CHIP==HT32F1653_54_55_56) + .else + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .endif + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ CKRDY_IRQHandler + IRQ LVD_IRQHandler + IRQ BOD_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ LPWUP_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ EXTI5_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ EXTI10_IRQHandler + IRQ EXTI11_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ EXTI14_IRQHandler + IRQ EXTI15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0BRK_IRQHandler + IRQ MCTM0UP_IRQHandler + IRQ MCTM0TR_IRQHandler + IRQ MCTM0CC_IRQHandler + IRQ MCTM1BRK_IRQHandler + IRQ MCTM1UP_IRQHandler + IRQ MCTM1TR_IRQHandler + IRQ MCTM1CC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ GPTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ SDIO_IRQHandler + IRQ PDMA_CH0_IRQHandler + IRQ PDMA_CH1_IRQHandler + IRQ PDMA_CH2_IRQHandler + IRQ PDMA_CH3_IRQHandler + IRQ PDMA_CH4_IRQHandler + IRQ PDMA_CH5_IRQHandler + IRQ PDMA_CH6_IRQHandler + IRQ PDMA_CH7_IRQHandler + IRQ PDMA_CH8_IRQHandler + IRQ PDMA_CH9_IRQHandler + IRQ PDMA_CH10_IRQHandler + IRQ PDMA_CH11_IRQHandler + IRQ CSIF_IRQHandler + IRQ EBI_IRQHandler + IRQ AES_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_03.s b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_03.s new file mode 100644 index 00000000000..4360057e332 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/emStudio/startup_ht32f1xxxx_es_03.s @@ -0,0 +1,335 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f1xxxx_es_03.s +; Version : $Rev:: 1771 $ +; Date : $Date:: 2019-07-25 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F12364 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <16=> HT32F12364 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00012364 +*/ + + .equ HT32F12364, 16 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* ---, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* ---, 03, 0x00C, Hard Fault Handler */ + .long MemManage_Handler /* ---, 04, 0x010, MPU Fault Handler */ + .long BusFault_Handler /* ---, 05, 0x014, Bus Fault Handler */ + .long UsageFault_Handler /* ---, 06, 0x018, Usage Fault Handler */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* ---, 11, 0x02C, SVC Handler */ + .long DebugMon_Handler /* ---, 12, 0x030, Debug Monitor Handler */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* ---, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* ---, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long CKRDY_IRQHandler /* 00, 16, 0x040, */ + .long LVD_IRQHandler /* 01, 17, 0x044, */ + .long BOD_IRQHandler /* 02, 18, 0x048, */ + .long _RESERVED /* 03, 19, 0x04C, */ + .long RTC_IRQHandler /* 04, 20, 0x050, */ + .long FLASH_IRQHandler /* 05, 21, 0x054, */ + .long EVWUP_IRQHandler /* 06, 22, 0x058, */ + .long LPWUP_IRQHandler /* 07, 23, 0x05C, */ + .long EXTI0_IRQHandler /* 08, 24, 0x060, */ + .long EXTI1_IRQHandler /* 09, 25, 0x064, */ + .long EXTI2_IRQHandler /* 10, 26, 0x068, */ + .long EXTI3_IRQHandler /* 11, 27, 0x06C, */ + .long EXTI4_IRQHandler /* 12, 28, 0x070, */ + .long EXTI5_IRQHandler /* 13, 29, 0x074, */ + .long EXTI6_IRQHandler /* 14, 30, 0x078, */ + .long EXTI7_IRQHandler /* 15, 31, 0x07C, */ + .long EXTI8_IRQHandler /* 16, 32, 0x080, */ + .long EXTI9_IRQHandler /* 17, 33, 0x084, */ + .long EXTI10_IRQHandler /* 18, 34, 0x088, */ + .long EXTI11_IRQHandler /* 19, 35, 0x08C, */ + .long EXTI12_IRQHandler /* 20, 36, 0x090, */ + .long EXTI13_IRQHandler /* 21, 37, 0x094, */ + .long EXTI14_IRQHandler /* 22, 38, 0x098, */ + .long EXTI15_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long ADC_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long _RESERVED /* 30, 46, 0x0B8, */ + .long _RESERVED /* 31, 47, 0x0BC, */ + .long _RESERVED /* 32, 48, 0x0C0, */ + .long _RESERVED /* 33, 49, 0x0C4, */ + .long _RESERVED /* 34, 50, 0x0C8, */ + .long GPTM0_IRQHandler /* 35, 51, 0x0CC, */ + .long _RESERVED /* 36, 52, 0x0D0, */ + .long SCTM0_IRQHandler /* 37, 53, 0x0D4, */ + .long SCTM1_IRQHandler /* 38, 54, 0x0D8, */ + .long PWM0_IRQHandler /* 39, 55, 0x0DC, */ + .long _RESERVED /* 40, 56, 0x0E0, */ + .long BFTM0_IRQHandler /* 41, 57, 0x0E4, */ + .long BFTM1_IRQHandler /* 42, 58, 0x0E8, */ + .long I2C0_IRQHandler /* 43, 59, 0x0EC, */ + .long I2C1_IRQHandler /* 44, 60, 0x0F0, */ + .long SPI0_IRQHandler /* 45, 61, 0x0F4, */ + .long SPI1_IRQHandler /* 46, 62, 0x0F8, */ + .long USART0_IRQHandler /* 47, 63, 0x0FC, */ + .long _RESERVED /* 48, 64, 0x100, */ + .long UART0_IRQHandler /* 49, 65, 0x104, */ + .long UART1_IRQHandler /* 50, 66, 0x108, */ + .long SCI_IRQHandler /* 51, 67, 0x10C, */ + .long _RESERVED /* 52, 68, 0x110, */ + .long USB_IRQHandler /* 53, 69, 0x114, */ + .long _RESERVED /* 54, 70, 0x118, */ + .long PDMA_CH0_IRQHandler /* 55, 71, 0x11C, */ + .long PDMA_CH1_IRQHandler /* 56, 72, 0x120, */ + .long PDMA_CH2_IRQHandler /* 57, 73, 0x124, */ + .long PDMA_CH3_IRQHandler /* 58, 74, 0x128, */ + .long PDMA_CH4_IRQHandler /* 59, 75, 0x12C, */ + .long PDMA_CH5_IRQHandler /* 60, 76, 0x130, */ + .long _RESERVED /* 61, 77, 0x134, */ + .long _RESERVED /* 62, 78, 0x138, */ + .long _RESERVED /* 63, 79, 0x13C, */ + .long _RESERVED /* 64, 80, 0x140, */ + .long _RESERVED /* 65, 81, 0x144, */ + .long _RESERVED /* 66, 82, 0x148, */ + .long _RESERVED /* 67, 83, 0x14C, */ + .long _RESERVED /* 68, 84, 0x150, */ + .long AES_IRQHandler /* 69, 85, 0x154, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #1 + BEQ BP3 + CMP R1, #2 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ CKRDY_IRQHandler + IRQ LVD_IRQHandler + IRQ BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ LPWUP_IRQHandler + IRQ EXTI0_IRQHandler + IRQ EXTI1_IRQHandler + IRQ EXTI2_IRQHandler + IRQ EXTI3_IRQHandler + IRQ EXTI4_IRQHandler + IRQ EXTI5_IRQHandler + IRQ EXTI6_IRQHandler + IRQ EXTI7_IRQHandler + IRQ EXTI8_IRQHandler + IRQ EXTI9_IRQHandler + IRQ EXTI10_IRQHandler + IRQ EXTI11_IRQHandler + IRQ EXTI12_IRQHandler + IRQ EXTI13_IRQHandler + IRQ EXTI14_IRQHandler + IRQ EXTI15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_IRQHandler + IRQ PDMA_CH1_IRQHandler + IRQ PDMA_CH2_IRQHandler + IRQ PDMA_CH3_IRQHandler + IRQ PDMA_CH4_IRQHandler + IRQ PDMA_CH5_IRQHandler + IRQ AES_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_01.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_01.c new file mode 100644 index 00000000000..37cb60ba18a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_01.c @@ -0,0 +1,462 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_01.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File + * for the Holtek HT32F165x Device Series + * @version $Rev:: 2817 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F1653, HT32F1654 +// HT32F1655, HT32F1656 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F1xxxx_system HT32F1xxxx System + * @{ + */ + + +#include "ht32f1xxxx_01.h" + +/** @addtogroup HT32F1xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = ((HSE or HSI) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Feedback Clock Divider (NF2): 1 ~ 64 +// <1-64:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 64 MHz to 144 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 8 MHz to 144 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 MHz <= CK_AHB <= 24 MHz +// 1 WS: 24 MHz < CK_AHB <= 48 MHz +// 2 WS: 48 MHz < CK_AHB <= 72 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable +// Default branch cache = ENABLE +// Dcode cache-able +// <0=> YES +// <1=> NO +// Default Dcode cache-able = NO +// +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f1xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_NF2_DIV (18) /*!< 1~64: DIV1~DIV64 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI */ +#define HCLK_DIV (1) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DCODE_CACHE_ABLE (1) /*!< 0: YES, 1: NO */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = ((HSE or HSI) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 64000000UL + #define VCO_MAX 144000000UL + #define PLL_MIN 8000000UL + #define PLL_MAX 144000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000000UL +#define CKAHB_MAX 72000000UL +#define WS0_CLK 24000000UL +#define WS1_CLK 48000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F1xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F1xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + HT_CKCU->LPCR = 1; /* configure Backup domain isolation */ + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + +#if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while (((HT_CKCU->CKST >> 30) & 3UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ +#endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x3F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~3UL) | HCLK_SRC); /* select CK_SYS source */ + while (((HT_CKCU->CKST >> 30) & 3UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ + #if (DCODE_CACHE_ABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 7); /* 0: DCODE cache-able, 1: DCODE non cache-able */ + #else + SetBit_BB((u32)(&HT_FLASH->CFCR), 7); /* 0: DCODE cache-able, 1: DCODE non cache-able */ + #endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 3UL; + u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (64) : (HT_CKCU->PLLCFGR >> 23); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = (HT_CKCU->CKST >> 30) & 3UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = ((HSI_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((HSE_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_02.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_02.c new file mode 100644 index 00000000000..c0d6be90383 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_02.c @@ -0,0 +1,525 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_02.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File + * for the Holtek HT32F1xxxx Device Series + * @version $Rev:: 2817 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F12345 +// HT32F12365, HT32F12366 +// HT32F22366 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F1xxxx_system HT32F1xxxx System + * @{ + */ + + +#include "ht32f1xxxx_01.h" + +/** @addtogroup HT32F1xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = ((HSE or HSI) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Feedback Clock Divider (NF2): 1 ~ 32 +// <1-32:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 64 MHz to 96 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 8 MHz to 96 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <3=> 3 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 24 MHz +// 1 WS: 24 MHz < CK_AHB <= 48 MHz +// 2 WS: 48 MHz < CK_AHB <= 72 MHz +// 3 WS: 72 MHz < CK_AHB <= 96 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable +// Default branch cache = ENABLE +// Dcode cache-able +// <0=> YES +// <1=> NO +// Default Dcode cache-able = NO +// +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f1xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_NF2_DIV (12) /*!< 1~32: DIV1~DIV32 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 3: WS = 3, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DCODE_CACHE_ABLE (1) /*!< 0: YES, 1: NO */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = ((HSE or HSI) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 64000000UL + #define VCO_MAX 96000000UL + #define PLL_MIN 8000000UL + #define PLL_MAX 96000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 96000000UL +#define WS0_CLK 24000000UL +#define WS1_CLK 48000000UL +#define WS2_CLK 72000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS2_CLK) && (WAIT_STATE < 3) || \ + (__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif + +/** + * @brief LDO_MODE definition + */ +#if (__CK_AHB > 90000000UL) + #define __LDO_MODE (3) +#elif (__CK_AHB > 80000000UL) + #define __LDO_MODE (2) +#endif +/** + * @} + */ + +/** @addtogroup HT32F1xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F1xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + +#if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 3); /* disable USB PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 9); /* select USB PLL source as HSI */ +#endif + + /* LDO initiation */ +#if (__CK_AHB > 80000000UL) + do { + HT_PWRCU->CR = (HT_PWRCU->CR & ~(3UL << 4)) | (__LDO_MODE << 4); + } while (((HT_PWRCU->CR >> 4) & 3UL) != __LDO_MODE); +#endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x1F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS2_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 4UL); /* auto-select wait state */ + #elif (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* LDO initiation */ +#if (__CK_AHB > 80000000UL) +#else + do { + HT_PWRCU->CR = (HT_PWRCU->CR & ~(3UL << 4)); + } while (((HT_PWRCU->CR >> 4) & 3UL) != 0x0); +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ + #if (DCODE_CACHE_ABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 7); /* 0: DCODE cache-able, 1: DCODE non cache-able */ + #else + SetBit_BB((u32)(&HT_FLASH->CFCR), 7); /* 0: DCODE cache-able, 1: DCODE non cache-able */ + #endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (32) : (HT_CKCU->PLLCFGR >> 23); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = ((HSI_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((HSE_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_03.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_03.c new file mode 100644 index 00000000000..64d7a6b6f70 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_03.c @@ -0,0 +1,526 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F1xxxx/Source/system_ht32f1xxxx_03.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File + * for the Holtek HT32F1xxxx Device Series + * @version $Rev:: 2817 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F12364 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F1xxxx_system HT32F1xxxx System + * @{ + */ + + +#include "ht32f1xxxx_01.h" + +/** @addtogroup HT32F1xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 32 +// <1-32:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 64 MHz to 76 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 8 MHz to 76 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <3=> 3 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// 3 WS: 60 MHz < CK_AHB <= 76 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable +// Default branch cache = ENABLE +// Dcode cache-able +// <0=> YES +// <1=> NO +// Default Dcode cache-able = NO +// +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f1xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (0) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (9) /*!< 1~32: DIV1~DIV32 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 3: WS = 3, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DCODE_CACHE_ABLE (1) /*!< 0: YES, 1: NO */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 64000000UL + #define VCO_MAX 76000000UL + #define PLL_MIN 8000000UL + #define PLL_MAX 76000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 76000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL +#define WS2_CLK 60000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS2_CLK) && (WAIT_STATE < 3) || \ + (__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F1xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F1xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + +#if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 3); /* disable USB PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 9); /* select USB PLL source as HSI */ +#endif + + /* LDO initiation */ +#if (__CK_AHB > 72000000UL) + do { + HT_PWRCU->CR = (HT_PWRCU->CR & ~(3UL << 4)) | (3UL << 4); + } while (((HT_PWRCU->CR >> 4) & 3UL) != 3UL); +#endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x1F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS2_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 4UL); /* auto-select wait state */ + #elif (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* LDO initiation */ +#if (__CK_AHB > 72000000UL) +#else + do { + HT_PWRCU->CR = (HT_PWRCU->CR & ~(3UL << 4)); + } while (((HT_PWRCU->CR >> 4) & 3UL) != 0x0); +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ + #if (DCODE_CACHE_ABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 7); /* 0: DCODE cache-able, 1: DCODE non cache-able */ + #else + SetBit_BB((u32)(&HT_FLASH->CFCR), 7); /* 0: DCODE cache-able, 1: DCODE non cache-able */ + #endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 31UL) == 0) ? (32) : ((HT_CKCU->PLLCFGR >> 23) & 31UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32.h new file mode 100644 index 00000000000..bbfcf8bd2c6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32.h @@ -0,0 +1,35 @@ +/*********************************************************************************************************//** + * @file ht32.h + * @version $Rev:: 80 $ + * @date $Date:: 2017-05-25 #$ + * @brief The API between application and HT32FXXXX Firmware Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_H +#define __HT32_H + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_01.h" + +#endif /* __HT32_H -----------------------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_cm3_misc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_cm3_misc.h new file mode 100644 index 00000000000..2acc00f77ac --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_cm3_misc.h @@ -0,0 +1,132 @@ +/*********************************************************************************************************//** + * @file ht32_cm3_misc.h + * @version $Rev:: 5 $ + * @date $Date:: 2017-05-11 #$ + * @brief All the function prototypes for the miscellaneous firmware library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_CM3_MISC_H +#define __HT32_CM3_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32_Peripheral_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Exported_Constants MISC exported constants + * @{ + */ + +/* Vector Table Base */ +#define NVIC_VECTTABLE_RAM ((u32)0x20000000) +#define NVIC_VECTTABLE_FLASH ((u32)0x00000000) + +#define IS_NVIC_VECTTABLE(VECTTABLE) ((VECTTABLE == NVIC_VECTTABLE_RAM) || \ + (VECTTABLE == NVIC_VECTTABLE_FLASH)) + +#define IS_NVIC_OFFSET(OFFSET) (OFFSET < 0x0001FFFF) + +/* System Low Power */ +#define NVIC_LOWPOWER_SEVONPEND ((u8)0x10) +#define NVIC_LOWPOWER_SLEEPDEEP ((u8)0x04) +#define NVIC_LOWPOWER_SLEEPONEXIT ((u8)0x02) + +#define IS_NVIC_LOWPOWER(LOWPOWER) ((LOWPOWER == NVIC_LOWPOWER_SEVONPEND) || \ + (LOWPOWER == NVIC_LOWPOWER_SLEEPDEEP) || \ + (LOWPOWER == NVIC_LOWPOWER_SLEEPONEXIT)) + +/* System Handler */ +#define SYSTEMHANDLER_NMI ((u32)0x80000000) +#define SYSTEMHANDLER_PSV ((u32)0x10000000) +#define SYSTEMHANDLER_SYSTICK ((u32)0x04000000) +#define SYSTEMHANDLER_ALL ((u32)0x94000000) + +#define IS_NVIC_SYSTEMHANDLER(HANDLER) ((HANDLER == SYSTEMHANDLER_NMI) || \ + (HANDLER == SYSTEMHANDLER_PSV) || \ + (HANDLER == SYSTEMHANDLER_SYSTICK) ||\ + (HANDLER == SYSTEMHANDLER_ALL)) + +/* SysTick clock source */ +#define SYSTICK_SRC_STCLK ((u32)0xFFFFFFFB) +#define SYSTICK_SRC_FCLK ((u32)0x00000004) + +#define IS_SYSTICK_CLOCK_SOURCE(SOURCE) ((SOURCE == SYSTICK_SRC_STCLK) || \ + (SOURCE == SYSTICK_SRC_FCLK) ) + +/* SysTick counter state */ +#define SYSTICK_COUNTER_DISABLE ((u32)0xFFFFFFFE) +#define SYSTICK_COUNTER_ENABLE ((u32)0x00000001) +#define SYSTICK_COUNTER_CLEAR ((u32)0x00000000) + +#define IS_SYSTICK_COUNTER(COUNTER) ((COUNTER == SYSTICK_COUNTER_DISABLE) || \ + (COUNTER == SYSTICK_COUNTER_ENABLE) || \ + (COUNTER == SYSTICK_COUNTER_CLEAR)) + +#define IS_SYSTICK_RELOAD(RELOAD) ((RELOAD > 0) && (RELOAD <= 0xFFFFFF)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Exported_Functions MISC exported functions + * @{ + */ +void NVIC_SetVectorTable(u32 NVIC_VectTable, u32 NVIC_Offset); +void NVIC_LowPowerConfig(u8 NVIC_LowPowerMode, ControlStatus NewState); +void NVIC_CoreReset(void); +void NVIC_SetPendingSystemHandler(u32 SystemHandler); +void SYSTICK_ClockSourceConfig(u32 SysTick_ClockSource); +void SYSTICK_CounterCmd(u32 SysTick_Counter); +void SYSTICK_IntConfig(ControlStatus NewState); +void SYSTICK_SetReloadValue(u32 SysTick_Reload); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_dependency.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_dependency.h new file mode 100644 index 00000000000..46eef808e91 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_dependency.h @@ -0,0 +1,86 @@ +/*********************************************************************************************************//** + * @file ht32_dependency.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of dependency check. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +#ifdef __cplusplus + extern "C" { +#endif + + +#if 0 // Version setting example for module + +/* Dependency check ----------------------------------------------------------------------------------------*/ +#define MIN_HT32_FWLIB_VER (0x01000005) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x2200) +#include "ht32_dependency.h" // Not exist means the version of HT32 Firmware Library is older than the module required. + +#endif + +#if 0 // Version setting example for module + +/* Dependency check ----------------------------------------------------------------------------------------*/ +#if (__CORTEX_M == 0) +#define MIN_HT32_FWLIB_VER (0x01000024) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x5762) +#endif +#if (__CORTEX_M == 3) +#define MIN_HT32_FWLIB_VER (0x01000009) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x2556) +#endif +#include "ht32_dependency.h" // Not exist means the version of HT32 Firmware Library is older than the module required. + +#endif + + +#if 0 // Enable for test +#undef HT32_FWLIB_VER +#undef HT32_FWLIB_SVN +#define HT32_FWLIB_VER (0x00000004) +#define HT32_FWLIB_SVN (0x1074) +#endif + + +// Check "ht32fxxxxx_lib.h" for the version of HT32 Firmwar Library +#if (HT32_FWLIB_VER != 999999) +#if HT32_FWLIB_VER < MIN_HT32_FWLIB_VER + #error !!! The version of HT32 Firmware Library is older than the module required. Please update HT32 Firmware Library. +#endif + +#if HT32_FWLIB_SVN < MIN_HT32_FWLIB_SVN + #error !!! The version of HT32 Firmware Library is older than the module required. Please update HT32 Firmware Library. +#endif +#endif + + +// Un-defined for next module of the .C include .C case +#undef MIN_HT32_FWLIB_VER +#undef MIN_HT32_FWLIB_SVN + + +#ifdef __cplusplus +} +#endif + +//#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_rand.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_rand.h new file mode 100644 index 00000000000..c3ffdc9ec6f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_rand.h @@ -0,0 +1,43 @@ +/*********************************************************************************************************//** + * @file ht32_rand.h + * @version $Rev:: 133 $ + * @date $Date:: 2017-06-14 #$ + * @brief The header file of random number. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_RAND_H +#define __HT32_RAND_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported functions --------------------------------------------------------------------------------------*/ +void Rand_Init(u32 *uSeed, u32 uCount, u32 a, u32 b); +extern u32 (*Rand_Get)(u32 *, u32); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_retarget_desc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_retarget_desc.h new file mode 100644 index 00000000000..8cc88050862 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_retarget_desc.h @@ -0,0 +1,182 @@ +/*********************************************************************************************************//** + * @file ht32_retarget_desc.h + * @version $Rev:: 5 $ + * @date $Date:: 2017-05-11 #$ + * @brief The USB VCP descriptor file of retarget. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_RETARGET_DESC_H +#define __HT32_RETARGET_DESC_H + +/* Exported constants --------------------------------------------------------------------------------------*/ + + /*--------------------------------------------------------------------------------------------------------*/ + /* IAD to associate the two CDC interfaces */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + 8, // bLength 1 Size of this descriptor in bytes + 11, // bDescriptorType 1 Descriptor Type + 11, // bFirstInterface 1 + 2, // bInterfaceCount 1 + 2, // bFunctionClass 1 + 2, // bFunctionSubClass 1 + 0, // bFunctionProtocol 1 + 0x00, // iFunction 1 Index of string descriptor describing this function. + + /*--------------------------------------------------------------------------------------------------------*/ + /* Interface descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_INF, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_04_INF, // bDescriptorType 1 INTERFACE Descriptor Type + 11, // bInterfaceNumber 1 Number of this interface (Zero-based 0) + 0x00, // bAlternateSetting 1 Value used to select alternate setting + 1, // bNumEndpoints 1 Number of endpoints used by this interface + DESC_CLASS_02_CDC_CTRL, // bInterfaceClass 1 Class code (assigned by USB-IF) + 2, // bInterfaceSubClass 1 Subclass code (assigned by USB-IF) + 0, // bInterfaceProtocol 1 Protocol code (assigned by USB) + 0x00, // iInterface 1 Index of string descriptor describing this interface + + /*--------------------------------------------------------------------------------------------------------*/ + /* Header Functional descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 5, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 0, // bDescriptorSubtype 1 header functional descriptor + DESC_H2B(0x0110), // bcdCDC 2 spec release number + + /*--------------------------------------------------------------------------------------------------------*/ + /* Abstract control management Functional */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 4, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 2, // bDescriptorSubtype 1 Abstract Control Management Functional descriptor + 0x02, // bmCapabilities 1 + + /*--------------------------------------------------------------------------------------------------------*/ + /* Union Functional */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 5, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 5, // bDescriptorSubtype 1 Union Functional descriptor + 0x00, // bMasterInterface 1 Communication class interface + 0x01, // bSlaveInterface0 1 Data Class Interface + + /*--------------------------------------------------------------------------------------------------------*/ + /* Call Management Functional */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 5, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 1, // bDescriptorSubtype 1 Call Management Functional descriptor + 0x00, // bmCapabilities 1 + 0x01, // bDataInterface 1 Interface number of Data + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLengthE 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + (0x80 | RETARGET_CTRL_EPT), // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x03, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(RETARGET_CTRL_LEN),// wMaxPacketSize 2 Maximum packet size + 0x00, // bInterval 1 Interval for polling endpoint + + /*--------------------------------------------------------------------------------------------------------*/ + /* Data class interface descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_INF, // bLength 1 Endpoint Descriptor size + DESC_TYPE_04_INF, // bDescriptorType 1 + 12, // bInterfaceNumber 1 Number of Interface + 0x00, // bAlternateSetting 1 Alternate setting + 2, // bNumEndpoints 1 Two endpoints used + DESC_CLASS_0A_CDC_DATA, // bInterfaceClass 1 + 0, // bInterfaceSubClass 1 + 0, // bInterfaceProtocol 1 + 0x00, // iInterface 1 + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint n Out descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + (0x00 | RETARGET_RX_EPT), // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x02, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(RETARGET_RX_LEN), // wMaxPacketSize 2 Maximum packet size + 0x00, // bInterval 1 Interval for polling endpoint + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint n In Descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + (0x80 | RETARGET_TX_EPT), // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x02, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(RETARGET_TX_LEN), // wMaxPacketSize 2 Maximum packet size + 0x00, // bInterval 1 Interval for polling endpoint + +#endif /* __HT32_RETARGET_DESC_H ---------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_retarget_usbdconf.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_retarget_usbdconf.h new file mode 100644 index 00000000000..e333957f6b2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_retarget_usbdconf.h @@ -0,0 +1,321 @@ +/*********************************************************************************************************//** + * @file ht32_retarget_usbdconf.h + * @version $Rev:: 1958 $ + * @date $Date:: 2019-12-27 #$ + * @brief The USB Device configuration of retarget + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_RETARGET_USBDCONF_H +#define __HT32_RETARGET_USBDCONF_H + +/* Settings ------------------------------------------------------------------------------------------------*/ +#define RETARGET_INF (0) +#define RETARGET_DLEN (0) + +#if (_RETARGET == 1) + + #ifdef RETARGET_IS_USB + + #undef RETARGET_INF + #undef RETARGET_DLEN + #define RETARGET_INF (2) + #define RETARGET_DLEN (8 + DESC_LEN_INF * 2 + 5 + 4 + 5 + 5 + DESC_LEN_EPT * 3) + + #if (_EP1_ENABLE == 0 && _EP2_ENABLE == 0 && _EP3_ENABLE == 0 && _EP4_ENABLE == 0 && \ + _EP5_ENABLE == 0 && _EP6_ENABLE == 0 && _EP7_ENABLE == 0) + #define NON_USB_IN_APP + #undef _UIER + #undef _EP0LEN + #undef _EP0_IER + #define _EP0LEN (64) + #define _EP0_IER (0x212) + #define _UIER (0x011D) + #endif + + #define _UIER_ALL (_UIER | (EP0IE << RETARGET_RX_EPT) | (EP0IE << RETARGET_TX_EPT)) + + #if (RETARGET_RX_EPT == 1 || RETARGET_TX_EPT == 1 || RETARGET_CTRL_EPT == 1) + #if (_EP1_ENABLE == 1) + #define _RERATGET1_ERR + #else + #undef _EP1_ENABLE + #undef _EP1_CFG_EPADR + #undef _EP1_CFG_EPEN_TMP + #undef _EP1_TYPR + #undef _EP1_CFG_EPDIR + #undef _EP1LEN_TMP + #undef _EP1_IER + + #define _EP1_ENABLE (1) + #define _EP1_CFG_EPADR (1) + #define _EP1_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 1) + #define _EP1_TYPR (2) + #define _EP1_CFG_EPDIR (0) + #define _EP1LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP1_IER (0x02) + #define RETARGET_RX_LEN (_EP1LEN) + #elif (RETARGET_TX_EPT == 1) + #define _EP1_TYPR (2) + #define _EP1_CFG_EPDIR (1) + #define _EP1LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP1_IER (0x10) + #define RETARGET_TX_LEN (_EP1LEN) + #elif (RETARGET_CTRL_EPT == 1) + #define _EP1_TYPR (3) + #define _EP1_CFG_EPDIR (1) + #define _EP1LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP1_IER (0x10) + #define RETARGET_CTRL_LEN (_EP1LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 2 || RETARGET_TX_EPT == 2 || RETARGET_CTRL_EPT == 2) + #if (_EP2_ENABLE == 1) + #define _RERATGET2_ERR + #else + #undef _EP2_ENABLE + #undef _EP2_CFG_EPADR + #undef _EP2_CFG_EPEN_TMP + #undef _EP2_TYPR + #undef _EP2_CFG_EPDIR + #undef _EP2LEN_TMP + #undef _EP2_IER + + #define _EP2_ENABLE (1) + #define _EP2_CFG_EPADR (2) + #define _EP2_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 2) + #define _EP2_TYPR (2) + #define _EP2_CFG_EPDIR (0) + #define _EP2LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP2_IER (0x02) + #define RETARGET_RX_LEN (_EP2LEN) + #elif (RETARGET_TX_EPT == 2) + #define _EP2_TYPR (2) + #define _EP2_CFG_EPDIR (1) + #define _EP2LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP2_IER (0x10) + #define RETARGET_TX_LEN (_EP2LEN) + #elif (RETARGET_CTRL_EPT == 2) + #define _EP2_TYPR (3) + #define _EP2_CFG_EPDIR (1) + #define _EP2LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP2_IER (0x10) + #define RETARGET_CTRL_LEN (_EP2LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 3 || RETARGET_TX_EPT == 3 || RETARGET_CTRL_EPT == 3) + #if (_EP3_ENABLE == 1) + #define _RERATGET3_ERR + #else + #undef _EP3_ENABLE + #undef _EP3_CFG_EPADR + #undef _EP3_CFG_EPEN_TMP + #undef _EP3_TYPR + #undef _EP3_CFG_EPDIR + #undef _EP3LEN_TMP + #undef _EP3_IER + + #define _EP3_ENABLE (1) + #define _EP3_CFG_EPADR (3) + #define _EP3_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 3) + #define _EP3_TYPR (2) + #define _EP3_CFG_EPDIR (0) + #define _EP3LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP3_IER (0x02) + #define RETARGET_RX_LEN (_EP3LEN) + #elif (RETARGET_TX_EPT == 3) + #define _EP3_TYPR (2) + #define _EP3_CFG_EPDIR (1) + #define _EP3LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP3_IER (0x10) + #define RETARGET_TX_LEN (_EP3LEN) + #elif (RETARGET_CTRL_EPT == 3) + #define _EP3_TYPR (3) + #define _EP3_CFG_EPDIR (1) + #define _EP3LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP3_IER (0x10) + #define RETARGET_CTRL_LEN (_EP3LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 4 || RETARGET_TX_EPT == 4 || RETARGET_CTRL_EPT == 4) + #if (_EP4_ENABLE == 1) + #define _RERATGET4_ERR + #else + #undef _EP4_ENABLE + #undef _EP4_CFG_EPADR + #undef _EP4_CFG_EPEN_TMP + #undef _EP4_TYPR + #undef _EP4_CFG_EPDIR + #undef _EP4LEN_TMP + #undef _EP4_IER + + #define _EP4_ENABLE (1) + #define _EP4_CFG_EPADR (4) + #define _EP4_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 4) + #define _EP4_TYPR (2) + #define _EP4_CFG_EPDIR (0) + #define _EP4LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP4_IER (0x02) + #define RETARGET_RX_LEN (_EP4LEN) + #elif (RETARGET_TX_EPT == 4) + #define _EP4_TYPR (2) + #define _EP4_CFG_EPDIR (1) + #define _EP4LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP4_IER (0x10) + #define RETARGET_TX_LEN (_EP4LEN) + #elif (RETARGET_CTRL_EPT == 4) + #define _EP4_TYPR (3) + #define _EP4_CFG_EPDIR (1) + #define _EP4LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP4_IER (0x10) + #define RETARGET_CTRL_LEN (_EP4LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 5 || RETARGET_TX_EPT == 5 || RETARGET_CTRL_EPT == 5) + #if (_EP5_ENABLE == 1) + #define _RERATGET5_ERR + #else + #undef _EP5_ENABLE + #undef _EP5_CFG_EPADR + #undef _EP5_CFG_EPEN_TMP + #undef _EP5_TYPR + #undef _EP5_CFG_EPDIR + #undef _EP5LEN_TMP + #undef _EP5_IER + + #define _EP5_ENABLE (1) + #define _EP5_CFG_EPADR (5) + #define _EP5_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 5) + #define _EP5_TYPR (2) + #define _EP5_CFG_EPDIR (0) + #define _EP5LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP5_IER (0x02) + #define RETARGET_RX_LEN (_EP5LEN) + #elif (RETARGET_TX_EPT == 5) + #define _EP5_TYPR (2) + #define _EP5_CFG_EPDIR (1) + #define _EP5LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP5_IER (0x10) + #define RETARGET_TX_LEN (_EP5LEN) + #elif (RETARGET_CTRL_EPT == 5) + #define _EP5_TYPR (3) + #define _EP5_CFG_EPDIR (1) + #define _EP5LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP5_IER (0x10) + #define RETARGET_CTRL_LEN (_EP5LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 6 || RETARGET_TX_EPT == 6 || RETARGET_CTRL_EPT == 6) + #if (_EP6_ENABLE == 1) + #define _RERATGET6_ERR + #else + #undef _EP6_ENABLE + #undef _EP6_CFG_EPADR + #undef _EP6_CFG_EPEN_TMP + #undef _EP6_TYPR + #undef _EP6_CFG_EPDIR + #undef _EP6LEN_TMP + #undef _EP6_IER + + #define _EP6_ENABLE (1) + #define _EP6_CFG_EPADR (6) + #define _EP6_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 6) + #define _EP6_TYPR (2) + #define _EP6_CFG_EPDIR (0) + #define _EP6LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP6_IER (0x02) + #define RETARGET_RX_LEN (_EP6LEN) + #elif (RETARGET_TX_EPT == 6) + #define _EP6_TYPR (2) + #define _EP6_CFG_EPDIR (1) + #define _EP6LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP6_IER (0x10) + #define RETARGET_TX_LEN (_EP6LEN) + #elif (RETARGET_CTRL_EPT == 6) + #define _EP6_TYPR (3) + #define _EP6_CFG_EPDIR (1) + #define _EP6LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP6_IER (0x10) + #define RETARGET_CTRL_LEN (_EP6LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 7 || RETARGET_TX_EPT == 7 || RETARGET_CTRL_EPT == 7) + #if (_EP7_ENABLE == 1) + #define _RERATGET7_ERR + #else + #undef _EP7_ENABLE + #undef _EP7_CFG_EPADR + #undef _EP7_CFG_EPEN_TMP + #undef _EP7_TYPR + #undef _EP7_CFG_EPDIR + #undef _EP7LEN_TMP + #undef _EP7_IER + + #define _EP7_ENABLE (1) + #define _EP7_CFG_EPADR (7) + #define _EP7_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 7) + #define _EP7_TYPR (2) + #define _EP7_CFG_EPDIR (0) + #define _EP7LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP7_IER (0x02) + #define RETARGET_RX_LEN (_EP7LEN) + #elif (RETARGET_TX_EPT == 7) + #define _EP7_TYPR (2) + #define _EP7_CFG_EPDIR (1) + #define _EP7LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP7_IER (0x10) + #define RETARGET_TX_LEN (_EP7LEN) + #elif (RETARGET_CTRL_EPT == 7) + #define _EP7_TYPR (3) + #define _EP7_CFG_EPDIR (1) + #define _EP7LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP7_IER (0x10) + #define RETARGET_CTRL_LEN (_EP7LEN) + #endif + #endif + #endif + + #endif /* #ifdef RETARGET_IS_USB */ + +#endif /* #if (_RETARGET == 1) */ + +#endif /* __HT32_RETARGET_USBDCONF_H -----------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_serial.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_serial.h new file mode 100644 index 00000000000..641fb91d51f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_serial.h @@ -0,0 +1,84 @@ +/*********************************************************************************************************//** + * @file ht32_serial.h + * @version $Rev:: 2765 $ + * @date $Date:: 2022-11-11 #$ + * @brief The header file of the Serial library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_SERIAL_H +#define __HT32_SERIAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#ifdef RETARGET_IS_USB +#include "ht32_usbd_core.h" +#endif + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @addtogroup SERIAL + * @brief Serial related functions + * @{ + */ + + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Exported_Functions Serial exported functions + * @{ + */ +void RETARGET_UART_IRQHandler(void); +u32 SERIAL_GetChar(void); +u32 SERIAL_PutChar(u32 ch); +#ifdef RETARGET_IS_USB +void SERIAL_USBDClass_Request(USBDCore_Device_TypeDef *pDev); +void SERIAL_USBDClass_RXHandler(USBD_EPTn_Enum EPTn); +void SERIAL_USBDClass_TXHandler(USBD_EPTn_Enum EPTn); +void SERIAL_USBDInit(void); +void SERIAL_Flush(void); +#else +#define SERIAL_Flush(...) +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_time.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_time.h new file mode 100644 index 00000000000..1fc44cdc7c4 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_time.h @@ -0,0 +1,170 @@ +/*********************************************************************************************************//** + * @file ht32_time.h + * @version $Rev:: 2896 $ + * @date $Date:: 2023-03-04 #$ + * @brief The header file of time function. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_TIME_H +#define __HT32_TIME_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#ifndef HTCFG_TIME_IPSEL +#include "ht32_time_conf.h" +#endif + +/* Settings ------------------------------------------------------------------------------------------------*/ +#ifdef HTCFG_TIME_IPSEL +#if (HTCFG_TIME_IPSEL == 0) +#define HTCFG_TIME_IPN BFTM0 +#endif +#if (HTCFG_TIME_IPSEL == 1) +#define HTCFG_TIME_IPN BFTM1 +#endif +#if (HTCFG_TIME_IPSEL == 2) +#define HTCFG_TIME_IPN SCTM0 +#endif +#if (HTCFG_TIME_IPSEL == 3) +#define HTCFG_TIME_IPN SCTM1 +#endif +#if (HTCFG_TIME_IPSEL == 4) +#define HTCFG_TIME_IPN SCTM2 +#endif +#if (HTCFG_TIME_IPSEL == 5) +#define HTCFG_TIME_IPN SCTM3 +#endif +#if (HTCFG_TIME_IPSEL == 6) +#define HTCFG_TIME_IPN PWM0 +#endif +#if (HTCFG_TIME_IPSEL == 7) +#define HTCFG_TIME_IPN PWM1 +#endif +#if (HTCFG_TIME_IPSEL == 8) +#define HTCFG_TIME_IPN PWM2 +#endif +#if (HTCFG_TIME_IPSEL == 9) +#define HTCFG_TIME_IPN GPTM0 +#endif +#if (HTCFG_TIME_IPSEL == 10) +#define HTCFG_TIME_IPN GPTM1 +#endif +#if (HTCFG_TIME_IPSEL == 11) +#define HTCFG_TIME_IPN MCTM0 +#endif +#endif + +/* Exported constants --------------------------------------------------------------------------------------*/ +#ifndef IS_IPN_BFTM +#undef IPN_MCTM0 +#undef IPN_MCTM1 +#undef IPN_GPTM0 +#undef IPN_GPTM1 + +#define IPN_NULL (0) +#define IPN_MCTM0 (0x4002C000) +#define IPN_MCTM1 (0x4002D000) +#define IPN_GPTM0 (0x4006E000) +#define IPN_GPTM1 (0x4006F000) +#define IPN_SCTM0 (0x40034000) +#define IPN_SCTM1 (0x40074000) +#define IPN_SCTM2 (0x40035000) +#define IPN_SCTM3 (0x40075000) +#define IPN_PWM0 (0x40031000) +#define IPN_PWM1 (0x40071000) +#define IPN_PWM2 (0x40031000) +#define IPN_BFTM0 (0x40076000) +#define IPN_BFTM1 (0x40077000) +#define IPN_CHECK(IP) STRCAT2(IPN_, IP) +#define IS_IPN_BFTM(IP) (IPN_CHECK(IP) == IPN_BFTM0) || (IPN_CHECK(IP) == IPN_BFTM1) +#define IS_IPN_MCTM(IP) (IPN_CHECK(IP) == IPN_MCTM0) || (IPN_CHECK(IP) == IPN_MCTM1) +#define IS_IPN_GPTM(IP) (IPN_CHECK(IP) == IPN_GPTM0) || (IPN_CHECK(IP) == IPN_GPTM1) +#define IS_IPN_SCTM(IP) (IPN_CHECK(IP) == IPN_SCTM0) || (IPN_CHECK(IP) == IPN_SCTM1) || (IPN_CHECK(IP) == IPN_SCTM2) || (IPN_CHECK(IP) == IPN_SCTM3) +#define IS_IPN_PWM(IP) (IPN_CHECK(IP) == IPN_PWM0) || (IPN_CHECK(IP) == IPN_PWM1) || (IPN_CHECK(IP) == IPN_PWM2) +#define IS_IPN_TM(IP) (IS_IPN_MCTM(IP) || IS_IPN_GPTM(IP) || IS_IPN_SCTM(IP) || IS_IPN_PWM(IP)) +#endif + +#define _HTCFG_TIME_PORT STRCAT2(HT_, HTCFG_TIME_IPN) + +#if (HTCFG_TIME_CLKSEL == 0) +#define _HTCFG_TIME_CORECLK (LIBCFG_MAX_SPEED) +#else +#define _HTCFG_TIME_CORECLK (HTCFG_TIME_CLK_MANUAL) +#endif + +#if (LIBCFG_CKCU_NO_APB_PRESCALER == 1) +#undef HTCFG_TIME_PCLK_DIV +#define HTCFG_TIME_PCLK_DIV (0) +#endif + +#define HTCFG_TIME_CLKSRC (_HTCFG_TIME_CORECLK >> HTCFG_TIME_PCLK_DIV) + +#if (IS_IPN_BFTM(HTCFG_TIME_IPN)) +#undef HTCFG_TIME_TICKHZ +#define HTCFG_TIME_TICKHZ HTCFG_TIME_CLKSRC +#endif + +/* Exported macro ------------------------------------------------------------------------------------------*/ +#define TIME_TICKDIFF(start, current) ((current >= start) ? (u32)(current - start) : (u32)(0xFFFFFFFF - start + 1 + current)) + +#if (HTCFG_TIME_TICKHZ < 1000000) +#define TIME_US2TICK(us) (us / (1000000UL / HTCFG_TIME_TICKHZ)) +#define TIME_TICK2US(t) (t * (1000000UL / HTCFG_TIME_TICKHZ)) +#else +#define TIME_US2TICK(us) (us * (HTCFG_TIME_TICKHZ / 1000000UL)) +#define TIME_TICK2US(t) (t / (HTCFG_TIME_TICKHZ / 1000000UL)) +#endif + +#if (HTCFG_TIME_TICKHZ < 1000) +#define TIME_MS2TICK(ms) (ms / (1000UL / HTCFG_TIME_TICKHZ)) +#define TIME_TICK2MS(t) (t * (1000UL / HTCFG_TIME_TICKHZ)) +#else +#define TIME_MS2TICK(ms) (ms * (HTCFG_TIME_TICKHZ / 1000UL)) +#define TIME_TICK2MS(t) (t / (HTCFG_TIME_TICKHZ / 1000UL)) +#endif + +#define TIME_S2TICK(s) (s * (u32)(HTCFG_TIME_TICKHZ)) +#define TIME_TICK2S(t) (t / (HTCFG_TIME_TICKHZ)) + + +#define GET_CNT() (_HTCFG_TIME_PORT->CNTR) + +/* Exported functions --------------------------------------------------------------------------------------*/ +void Time_Init(void); +void Time_Delay(u32 delay); +u32 Time_GetTick(void); + +#if (IS_IPN_BFTM(HTCFG_TIME_IPN)) +// BFTM +#define Time_GetTick GET_CNT +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_undef_IP.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_undef_IP.h new file mode 100644 index 00000000000..4339a8135dc --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32_undef_IP.h @@ -0,0 +1,200 @@ +/*********************************************************************************************************//** + * @file ht32_undef_IP.h + * @version $Rev:: 2962 $ + * @date $Date:: 2023-10-18 #$ + * @brief Header file for undefined IP. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ + +#ifndef __HT32_UNDEF_IP_H +#define __HT32_UNDEF_IP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if _AES +#undef _AES +#endif + +#ifdef _ADC +#undef _ADC +#endif + +#ifdef _BFTM +#undef _BFTM +#endif + +#ifdef _CAN +#undef _CAN +#endif + +#ifdef _CKCU +#undef _CKCU +#endif + +#ifdef _CMP +#undef _CMP +#endif + +#ifdef _CRC +#undef _CRC +#endif + +#ifdef _CSIF +#undef _CSIF +#endif + +#ifdef _DAC +#undef _DAC +#endif + +#ifdef _DIV +#undef _DIV +#endif + +#ifdef _EBI +#undef _EBI +#endif + +#ifdef _EXTI +#undef _EXTI +#endif + +#ifdef _FLASH +#undef _FLASH +#endif + +#ifdef _GPIO +#undef _GPIO +#endif + +#ifdef _GPTM +#undef _GPTM +#endif + +#ifdef _I2C +#undef _I2C +#endif + +#ifdef _I2S +#undef _I2S +#endif + +#ifdef _LCD +#undef _LCD +#endif + +#ifdef _LEDC +#undef _LEDC +#endif + +#ifdef _MCTM +#undef _MCTM +#endif + +#ifdef _MIDI +#undef _MIDI +#endif + +#ifdef _OPA +#undef _OPA +#endif + +#ifdef _PDMA +#undef _PDMA +#endif + +#ifdef _PWRCU +#undef _PWRCU +#endif + +#ifdef _PWM +#undef _PWM +#endif + +#ifdef _RSTCU +#undef _RSTCU +#endif + +#ifdef _RTC +#undef _RTC +#endif + +#ifdef _SCI +#undef _SCI +#endif + +#ifdef _SCTM +#undef _SCTM +#endif + +#ifdef _SDIO +#undef _SDIO +#endif + +#ifdef _SLED +#undef _SLED +#endif + +#ifdef _SPI +#undef _SPI +#endif + +#ifdef _TKEY +#undef _TKEY +#endif + +#ifdef _USART +#undef _USART +#endif + +#ifdef _USB +#undef _USB +#endif + +#ifdef _WDT +#undef _WDT +#endif + +#ifdef _MISC +#undef _MISC +#endif + +#ifdef _SERIAL +#undef _SERIAL +#endif + +#ifdef _SWDIV +#undef _SWDIV +#endif + +#ifdef _SWRAND +#undef _SWRAND +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12345_libcfg.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12345_libcfg.h new file mode 100644 index 00000000000..3e435d4b167 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12345_libcfg.h @@ -0,0 +1,57 @@ +/*********************************************************************************************************//** + * @file ht32f12345_libcfg.h + * @version $Rev:: 2805 $ + * @date $Date:: 2022-12-01 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F12345_LIBCFG_H +#define __HT32F12345_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F12345) +#define USE_MEM_HT32F12345 +#endif + +#define LIBCFG_MAX_SPEED (96000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F12345 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x12345) +#endif + +#define LIBCFG_SDIO (1) + +#define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_FMC_WAIT_STATE_3 (1) +#define LIBCFG_PDMA_CH8_11 (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_RTC_LSI_LOAD_TRIM (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12364_libcfg.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12364_libcfg.h new file mode 100644 index 00000000000..5093b688478 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12364_libcfg.h @@ -0,0 +1,77 @@ +/*********************************************************************************************************//** + * @file ht32f12364_libcfg.h + * @version $Rev:: 2805 $ + * @date $Date:: 2022-12-01 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F12364_LIBCFG_H +#define __HT32F12364_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F12364) +#define USE_MEM_HT32F12364 +#endif + +#define LIBCFG_MAX_SPEED (72000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F12364 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 128) + #define LIBCFG_CHIPNAME (0x12364) +#endif + +#define LIBCFG_ADC_V01 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_AES (1) +#define LIBCFG_CKCU_APBPCSR2 (1) +#define LIBCFG_CKCU_ADCPRE_DIV5 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_EBI_V01 (1) +#define LIBCFG_FLASH_2PAGE_PER_WPBIT (1) +#define LIBCFG_FMC_WAIT_STATE_3 (1) +#define LIBCFG_GPIOF (1) +#define LIBCFG_NO_ADC_CH8_15 (1) +#define LIBCFG_NO_BACK_DOMAIN (1) +#define LIBCFG_NO_CKCU_USBPRE (1) +#define LIBCFG_NO_CMP_TRIG_ADC (1) +#define LIBCFG_NO_CMP_HPTRIG_ADC (1) +#define LIBCFG_NO_GPTM1 (1) +#define LIBCFG_NO_I2S (1) +#define LIBCFG_NO_MCTM0 (1) +#define LIBCFG_NO_MCTM1 (1) +#define LIBCFG_NO_PDMA_CH6_11 (1) +#define LIBCFG_NO_USART1 (1) +#define LIBCFG_PDMA_V01 (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWRCU_LVDS_17_31 (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SPI_CLK_PRE_V01 (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12365_66_libcfg.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12365_66_libcfg.h new file mode 100644 index 00000000000..ee16bf2fa1a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f12365_66_libcfg.h @@ -0,0 +1,78 @@ +/*********************************************************************************************************//** + * @file ht32f12365_66_libcfg.h + * @version $Rev:: 2805 $ + * @date $Date:: 2022-12-01 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F12365_66_LIBCFG_H +#define __HT32F12365_66_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F12365) && !defined(USE_MEM_HT32F12366) && !defined(USE_MEM_HT32F22366) +#define USE_MEM_HT32F12366 +#endif + +#define LIBCFG_MAX_SPEED (96000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F12365 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 64) + #define LIBCFG_CHIPNAME (0x12365) +#endif + +#ifdef USE_MEM_HT32F12366 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 128) + #define LIBCFG_CHIPNAME (0x12366) +#endif + +#ifdef USE_MEM_HT32F22366 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 128) + #define LIBCFG_CHIPNAME (0x22366) +#endif + +#define LIBCFG_AES (1) +#define LIBCFG_CSIF (1) +#define LIBCFG_GPIOE (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SCI1 (1) +#define LIBCFG_SDIO (1) + +#define LIBCFG_ADC_CH12_15 (1) +#define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_EBI_BYTELAND_ASYNCREADY (1) +#define LIBCFG_FLASH_2PAGE_PER_WPBIT (1) +#define LIBCFG_FMC_WAIT_STATE_3 (1) +#define LIBCFG_PDMA_CH8_11 (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_RTC_LSI_LOAD_TRIM (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_AES_SWAP (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1653_54_libcfg.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1653_54_libcfg.h new file mode 100644 index 00000000000..cebe74e6370 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1653_54_libcfg.h @@ -0,0 +1,77 @@ +/*********************************************************************************************************//** + * @file ht32f1653_54_libcfg.h + * @version $Rev:: 2805 $ + * @date $Date:: 2022-12-01 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1653_54_LIBCFG_H +#define __HT32F1653_54_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F1653) && !defined(USE_MEM_HT32F1654) +#define USE_MEM_HT32F1654 +#endif + +#define LIBCFG_MAX_SPEED (72000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F1653 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x1653) +#endif + +#ifdef USE_MEM_HT32F1654 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x1654) +#endif + +#define LIBCFG_SCI0 (1) + +#define LIBCFG_ADC_NOENBIT (1) +#define LIBCFG_CKCU_AUTOTRIM_NOCKIN (1) +#define LIBCFG_CKCU_CKSWST_LEGACY (1) +#define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_NO_HCLK_LOW_SPEED (1) +#define LIBCDG_CKCU_PLL_144M (1) +#define LIBCDG_CKCU_SYSCLK_DIV8_ONLY (1) +#define LIBCFG_CKCU_USB_DIV3 (1) +#define LIBCFG_FLASH_HALFCYCYLE (1) +#define LIBCFG_FLASH_ZWPWESAVING (1) +#define LIBCFG_NO_CMP_HPTRIG_ADC (1) +#define LIBCFG_GPIO_DV_4_8MA_ONLY (1) +#define LIBCFG_PDMA_BLKLEN65536 (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_PWRCU_HSI_READY_COUNTER (1) +#define LIBCFG_PWRCU_LDO_LEGACY (1) +#define LIBCFG_PWRCU_LVDS_27_35 (1) +#define LIBCFG_RTC_LSI_LOAD_TRIM (1) +#define LIBCFG_USART_V01 (1) +#define LIBCFG_WDT_INT (1) +#define LIBCFC_WEAK_AF1 (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1655_56_libcfg.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1655_56_libcfg.h new file mode 100644 index 00000000000..30ac2b27927 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1655_56_libcfg.h @@ -0,0 +1,86 @@ +/*********************************************************************************************************//** + * @file ht32f1655_56_libcfg.h + * @version $Rev:: 2887 $ + * @date $Date:: 2023-03-02 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1655_56_LIBCFG_H +#define __HT32F1655_56_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F1655) && !defined(USE_MEM_HT32F1656) +#define USE_MEM_HT32F1656 +#endif + +#define LIBCFG_MAX_SPEED (72000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F1655 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 128) + #define LIBCFG_RAM_SIZE (1024 * 32) + #define LIBCFG_CHIPNAME (0x1655) +#endif + +#ifdef USE_MEM_HT32F1656 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 32) + #define LIBCFG_CHIPNAME (0x1656) +#endif + +#define LIBCFG_CMP_OPA (1) +#define LIBCFG_GPIOE (1) +#define LIBCFG_SCI0 (1) + +#define LIBCFG_ADC_CH12_15 (1) +#define LIBCFG_ADC_NOENBIT (1) +#define LIBCFG_CKCU_NO_APB_PRESCALER (1) +#define LIBCFG_CKCU_CKSWST_LEGACY (1) +#define LIBCFG_CKCU_HSI_NO_AUTOTRIM (1) +#define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_NO_HCLK_LOW_SPEED (1) +#define LIBCDG_CKCU_PLL_144M (1) +#define LIBCDG_CKCU_SYSCLK_DIV8_ONLY (1) +#define LIBCFG_CKCU_USART_PRESCALER (1) +#define LIBCFG_CKCU_USB_DIV3 (1) +#define LIBCFG_EBI_BYTELAND_ASYNCREADY (1) +#define LIBCFG_EXTI_8BIT_DEBOUNCE_COUNTER (1) +#define LIBCFG_GPIO_DV_4_8MA_ONLY (1) +#define LIBCFG_FLASH_2PAGE_PER_WPBIT (1) +#define LIBCFG_FLASH_HALFCYCYLE (1) +#define LIBCFG_FLASH_ZWPWESAVING (1) +#define LIBCFG_NO_CMP_TRIG_ADC (1) +#define LIBCFG_NO_CMP_HPTRIG_ADC (1) +#define LIBCFG_PDMA_BLKLEN65536 (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_PWRCU_HSI_READY_COUNTER (1) +#define LIBCFG_PWRCU_LDO_LEGACY (1) +#define LIBCFG_PWRCU_LVDS_27_35 (1) +#define LIBCFG_RTC_LSI_LOAD_TRIM (1) +#define LIBCFG_USART_V01 (1) +#define LIBCFG_WDT_INT (1) +#define LIBCFC_WEAK_AF1 (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_adc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_adc.h new file mode 100644 index 00000000000..92e286f14b3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_adc.h @@ -0,0 +1,498 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_adc.h + * @version $Rev:: 2791 $ + * @date $Date:: 2022-11-24 #$ + * @brief The header file of the ADC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_ADC_H +#define __HT32F1XXXX_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Constants ADC exported constants + * @{ + */ +#define IS_ADC(x) (x == HT_ADC) + +#define ONE_SHOT_MODE (0x00000000) +#define CONTINUOUS_MODE (0x00000002) +#define DISCONTINUOUS_MODE (0x00000003) + +#define IS_ADC_CONVERSION_MODE(REGULAR_MODE) (((REGULAR_MODE) == ONE_SHOT_MODE) || \ + ((REGULAR_MODE) == CONTINUOUS_MODE) || \ + ((REGULAR_MODE) == DISCONTINUOUS_MODE)) + +#define IS_ADC_HP_CONVERSION_MODE(HP_MODE) (((HP_MODE) == ONE_SHOT_MODE) || \ + ((HP_MODE) == CONTINUOUS_MODE) || \ + ((HP_MODE) == DISCONTINUOUS_MODE)) + + +#define ADC_CH_0 (0) +#define ADC_CH_1 (1) +#define ADC_CH_2 (2) +#define ADC_CH_3 (3) +#define ADC_CH_4 (4) +#define ADC_CH_5 (5) +#define ADC_CH_6 (6) +#define ADC_CH_7 (7) +#if !(LIBCFG_NO_ADC_CH8_15) +#define ADC_CH_8 (8) +#define ADC_CH_9 (9) +#define ADC_CH_10 (10) +#define ADC_CH_11 (11) +#if (LIBCFG_ADC_CH12_15) +#define ADC_CH_12 (12) +#define ADC_CH_13 (13) +#define ADC_CH_14 (14) +#define ADC_CH_15 (15) +#define IS_ADC_CHANNEL12_15(CHANNEL) (((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || \ + ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15)) +#else +#define IS_ADC_CHANNEL12_15(CHANNEL) (0) +#endif +#else +#define IS_ADC_CHANNEL8_14(CHANNEL) (0) +#define ADC_CH_IVREF (15) +#endif +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) + +#define ADC_CH_GNDREF ADC_CH_GND_VREF +#define ADC_CH_VREF ADC_CH_VDD_VREF + + +#if (LIBCFG_NO_ADC_CH8_15) +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + (IS_ADC_CHANNEL8_14(CHANNEL)) || \ + ((CHANNEL) == ADC_CH_IVREF) || ((CHANNEL) == ADC_CH_GND_VREF) || \ + ((CHANNEL) == ADC_CH_VDD_VREF)) +#else +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || \ + ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) || \ + (IS_ADC_CHANNEL12_15(CHANNEL)) || \ + ((CHANNEL) == ADC_CH_GND_VREF) || ((CHANNEL) == ADC_CH_VDD_VREF)) +#endif + +#if (LIBCFG_NO_ADC_CH8_15) +#define IS_ADC_INPUT_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7)) +#else +#define IS_ADC_INPUT_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || \ + ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) || \ + (IS_ADC_CHANNEL12_15(CHANNEL))) +#endif + +#define ADC_TRIG_SOFTWARE (1UL << 0) + +/* ((ADCTCR[4] << 4) | (ADCTSR[20] << 20)) */ +#if (!LIBCFG_NO_CMP_TRIG_ADC) +#define ADC_TRIG_CMP0 ((1UL << 4) | (0UL << 20)) +#define ADC_TRIG_CMP1 ((1UL << 4) | (1UL << 20)) +#endif + +#if (!LIBCFG_NO_CMP_HPTRIG_ADC) +#define ADC_HPTRIG_CMP0 ADC_TRIG_CMP0 +#define ADC_HPTRIG_CMP1 ADC_TRIG_CMP1 +#endif + +/* ((ADCTCR[3] << 3) | (ADCTSR[23:22] << 22) | (ADCTSR[19] << 19)) */ +#define ADC_TRIG_BFTM0 ((1UL << 3) | (0UL << 22) | (0UL << 19)) +#define ADC_TRIG_BFTM1 ((1UL << 3) | (0UL << 22) | (1UL << 19)) + +/* ((ADCTCR[3] << 3) | (ADCTSR[29:27]) << 27) | (ADCTSR[23:22] << 22) | (ADCTSR[19] << 19)) */ +#if (LIBCFG_PWM0) +#define ADC_TRIG_PWM0_MTO ((1UL << 3) | (0UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH0O ((1UL << 3) | (1UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH1O ((1UL << 3) | (2UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH2O ((1UL << 3) | (3UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH3O ((1UL << 3) | (4UL << 27) | (1UL << 22) | (0UL << 19)) +#endif +#if (LIBCFG_PWM1) +#define ADC_TRIG_PWM1_MTO ((1UL << 3) | (0UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH0O ((1UL << 3) | (1UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH1O ((1UL << 3) | (2UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH2O ((1UL << 3) | (3UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH3O ((1UL << 3) | (4UL << 27) | (1UL << 22) | (1UL << 19)) +#endif + +/* ((ADCTCR[2] << 2) | (ADCTSR[26:24] << 24) | (ADCTSR[18:16] << 16)) */ +#if (!LIBCFG_NO_MCTM0) +#define ADC_TRIG_MCTM0_MTO ((1UL << 2) | (0UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH0O ((1UL << 2) | (1UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH1O ((1UL << 2) | (2UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH2O ((1UL << 2) | (3UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH3O ((1UL << 2) | (4UL << 24) | (0UL << 16)) +#endif + +#if (!LIBCFG_NO_MCTM1) +#define ADC_TRIG_MCTM1_MTO ((1UL << 2) | (0UL << 24) | (1UL << 16)) +#define ADC_TRIG_MCTM1_CH0O ((1UL << 2) | (1UL << 24) | (1UL << 16)) +#define ADC_TRIG_MCTM1_CH1O ((1UL << 2) | (2UL << 24) | (1UL << 16)) +#define ADC_TRIG_MCTM1_CH2O ((1UL << 2) | (3UL << 24) | (1UL << 16)) +#define ADC_TRIG_MCTM1_CH3O ((1UL << 2) | (4UL << 24) | (1UL << 16)) +#endif + +#define ADC_TRIG_GPTM0_MTO ((1UL << 2) | (0UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH0O ((1UL << 2) | (1UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH1O ((1UL << 2) | (2UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH2O ((1UL << 2) | (3UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH3O ((1UL << 2) | (4UL << 24) | (2UL << 16)) + +#if (!LIBCFG_NO_GPTM1) +#define ADC_TRIG_GPTM1_MTO ((1UL << 2) | (0UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH0O ((1UL << 2) | (1UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH1O ((1UL << 2) | (2UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH2O ((1UL << 2) | (3UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH3O ((1UL << 2) | (4UL << 24) | (3UL << 16)) +#endif + +/* (ADCTCR[1] << 1) | (ADCTSR[11:8] << 8) */ +#define ADC_TRIG_EXTI_0 ((1UL << 1) | ( 0UL << 8)) +#define ADC_TRIG_EXTI_1 ((1UL << 1) | ( 1UL << 8)) +#define ADC_TRIG_EXTI_2 ((1UL << 1) | ( 2UL << 8)) +#define ADC_TRIG_EXTI_3 ((1UL << 1) | ( 3UL << 8)) +#define ADC_TRIG_EXTI_4 ((1UL << 1) | ( 4UL << 8)) +#define ADC_TRIG_EXTI_5 ((1UL << 1) | ( 5UL << 8)) +#define ADC_TRIG_EXTI_6 ((1UL << 1) | ( 6UL << 8)) +#define ADC_TRIG_EXTI_7 ((1UL << 1) | ( 7UL << 8)) +#define ADC_TRIG_EXTI_8 ((1UL << 1) | ( 8UL << 8)) +#define ADC_TRIG_EXTI_9 ((1UL << 1) | ( 9UL << 8)) +#define ADC_TRIG_EXTI_10 ((1UL << 1) | (10UL << 8)) +#define ADC_TRIG_EXTI_11 ((1UL << 1) | (11UL << 8)) +#define ADC_TRIG_EXTI_12 ((1UL << 1) | (12UL << 8)) +#define ADC_TRIG_EXTI_13 ((1UL << 1) | (13UL << 8)) +#define ADC_TRIG_EXTI_14 ((1UL << 1) | (14UL << 8)) +#define ADC_TRIG_EXTI_15 ((1UL << 1) | (15UL << 8)) + + +#define IS_ADC_TRIG(REGTRIG) (IS_ADC_TRIG1(REGTRIG) || \ + IS_ADC_TRIG2(REGTRIG) || \ + IS_ADC_TRIG3(REGTRIG) || \ + IS_ADC_TRIG4(REGTRIG) || \ + IS_ADC_TRIG5(REGTRIG) || \ + IS_ADC_TRIG6(REGTRIG) || \ + IS_ADC_TRIG7(REGTRIG)) + +#define IS_ADC_HPTRIG(REGTRIG) (IS_ADC_TRIG1(REGTRIG) || \ + IS_ADC_TRIG2(REGTRIG) || \ + IS_ADC_TRIG3(REGTRIG) || \ + IS_ADC_TRIG4(REGTRIG) || \ + IS_ADC_TRIG5(REGTRIG) || \ + IS_ADC_TRIG6(REGTRIG) || \ + IS_ADC_HPTRIG7(REGTRIG)) + +#define IS_ADC_TRIG1(REGTRIG) (((REGTRIG) == ADC_TRIG_GPTM0_MTO) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH0O) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH1O) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH2O) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH3O) || \ + ((REGTRIG) == ADC_TRIG_BFTM0) || \ + ((REGTRIG) == ADC_TRIG_EXTI_0) || \ + ((REGTRIG) == ADC_TRIG_EXTI_1) || \ + ((REGTRIG) == ADC_TRIG_EXTI_2) || \ + ((REGTRIG) == ADC_TRIG_EXTI_3) || \ + ((REGTRIG) == ADC_TRIG_EXTI_4) || \ + ((REGTRIG) == ADC_TRIG_EXTI_5) || \ + ((REGTRIG) == ADC_TRIG_EXTI_6) || \ + ((REGTRIG) == ADC_TRIG_EXTI_7) || \ + ((REGTRIG) == ADC_TRIG_EXTI_8) || \ + ((REGTRIG) == ADC_TRIG_EXTI_9) || \ + ((REGTRIG) == ADC_TRIG_EXTI_10) || \ + ((REGTRIG) == ADC_TRIG_EXTI_11) || \ + ((REGTRIG) == ADC_TRIG_EXTI_12) || \ + ((REGTRIG) == ADC_TRIG_EXTI_13) || \ + ((REGTRIG) == ADC_TRIG_EXTI_14) || \ + ((REGTRIG) == ADC_TRIG_EXTI_15) || \ + ((REGTRIG) == ADC_TRIG_SOFTWARE)) + +#define IS_ADC_TRIG2(REGTRIG) ((REGTRIG) == ADC_TRIG_BFTM1) + +#if (!LIBCFG_NO_MCTM0) +#define IS_ADC_TRIG3(REGTRIG) (((REGTRIG) == ADC_TRIG_MCTM0_MTO) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH0O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH1O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH2O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH3O) || \ + ((REGTRIG) == ADC_TRIG_BFTM1)) +#else +#define IS_ADC_TRIG3(REGTRIG) (0) +#endif + +#if (!LIBCFG_NO_MCTM1) +#define IS_ADC_TRIG4(REGTRIG) (((REGTRIG) == ADC_TRIG_GPTM1_MTO) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH0O) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH1O) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH2O) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH3O)) +#else +#define IS_ADC_TRIG4(REGTRIG) (0) +#endif + +#if (LIBCFG_PWM0) +#define IS_ADC_TRIG5(REGTRIG) (((REGTRIG) == ADC_TRIG_PWM0_MTO) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH0O) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH1O) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH2O) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH3O)) +#else +#define IS_ADC_TRIG5(REGTRIG) (0) +#endif + +#if (LIBCFG_PWM1) +#define IS_ADC_TRIG6(REGTRIG) (((REGTRIG) == ADC_TRIG_PWM1_MTO) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH0O) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH1O) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH2O) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH3O)) +#else +#define IS_ADC_TRIG6(REGTRIG) (0) +#endif + +#if (!LIBCFG_NO_CMP_TRIG_ADC) +#define IS_ADC_TRIG7(REGTRIG) (((REGTRIG) == ADC_TRIG_CMP0) || \ + ((REGTRIG) == ADC_TRIG_CMP1)) +#else +#define IS_ADC_TRIG7(REGTRIG) (0) +#endif + +#if (!LIBCFG_NO_CMP_HPTRIG_ADC) +#define IS_ADC_HPTRIG7(REGTRIG) (((REGTRIG) == ADC_HPTRIG_CMP0) || \ + ((REGTRIG) == ADC_HPTRIG_CMP1)) +#else +#define IS_ADC_HPTRIG7(REGTRIG) (0) +#endif + + +#define ADC_INT_SINGLE_EOC (0x00000001) +#define ADC_INT_SUB_GROUP_EOC (0x00000002) +#define ADC_INT_CYCLE_EOC (0x00000004) +#define ADC_INT_HP_SINGLE_EOC (0x00000100) +#define ADC_INT_HP_SUB_GROUP_EOC (0x00000200) +#define ADC_INT_HP_CYCLE_EOC (0x00000400) +#define ADC_INT_AWD_LOWER (0x00010000) +#define ADC_INT_AWD_UPPER (0x00020000) +#define ADC_INT_DATA_OVERWRITE (0x01000000) +#define ADC_INT_HP_DATA_OVERWRITE (0x02000000) + +#define IS_ADC_INT(INT) ((((INT) & 0xFCFCF8F8) == 0) && ((INT) != 0)) + + +#define ADC_FLAG_SINGLE_EOC (0x00000001) +#define ADC_FLAG_SUB_GROUP_EOC (0x00000002) +#define ADC_FLAG_CYCLE_EOC (0x00000004) +#define ADC_FLAG_HP_SINGLE_EOC (0x00000100) +#define ADC_FLAG_HP_SUB_GROUP_EOC (0x00000200) +#define ADC_FLAG_HP_CYCLE_EOC (0x00000400) +#define ADC_FLAG_AWD_LOWER (0x00010000) +#define ADC_FLAG_AWD_UPPER (0x00020000) +#define ADC_FLAG_DATA_OVERWRITE (0x01000000) +#define ADC_FLAG_HP_DATA_OVERWRITE (0x02000000) + +#define IS_ADC_FLAG(FLAG) ((((FLAG) & 0xFCFCF8F8) == 0) && ((FLAG) != 0)) + + +#define ADC_REGULAR_DATA0 (0) +#define ADC_REGULAR_DATA1 (1) +#define ADC_REGULAR_DATA2 (2) +#define ADC_REGULAR_DATA3 (3) +#define ADC_REGULAR_DATA4 (4) +#define ADC_REGULAR_DATA5 (5) +#define ADC_REGULAR_DATA6 (6) +#define ADC_REGULAR_DATA7 (7) +#define ADC_REGULAR_DATA8 (8) +#define ADC_REGULAR_DATA9 (9) +#define ADC_REGULAR_DATA10 (10) +#define ADC_REGULAR_DATA11 (11) +#define ADC_REGULAR_DATA12 (12) +#define ADC_REGULAR_DATA13 (13) +#define ADC_REGULAR_DATA14 (14) +#define ADC_REGULAR_DATA15 (15) + +#define IS_ADC_REGULAR_DATA(DATA) ((DATA) < 16) + + +#define ADC_HP_DATA0 (0) +#define ADC_HP_DATA1 (1) +#define ADC_HP_DATA2 (2) +#define ADC_HP_DATA3 (3) + +#define IS_ADC_HP_DATA(DATA) ((DATA) < 4) + + +#define ADC_AWD_DISABLE (u8)0x00 +#define ADC_AWD_ALL_LOWER (u8)0x05 +#define ADC_AWD_ALL_UPPER (u8)0x06 +#define ADC_AWD_ALL_LOWER_UPPER (u8)0x07 +#define ADC_AWD_SINGLE_LOWER (u8)0x01 +#define ADC_AWD_SINGLE_UPPER (u8)0x02 +#define ADC_AWD_SINGLE_LOWER_UPPER (u8)0x03 + +#define IS_ADC_AWD(AWD) (((AWD) == ADC_AWD_DISABLE) || \ + ((AWD) == ADC_AWD_ALL_LOWER) || \ + ((AWD) == ADC_AWD_ALL_UPPER) || \ + ((AWD) == ADC_AWD_ALL_LOWER_UPPER) || \ + ((AWD) == ADC_AWD_SINGLE_LOWER) || \ + ((AWD) == ADC_AWD_SINGLE_UPPER) || \ + ((AWD) == ADC_AWD_SINGLE_LOWER_UPPER)) + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) < 4096) + +#define ADC_PDMA_REGULAR_SINGLE (0x00000001) +#define ADC_PDMA_REGULAR_SUBGROUP (0x00000002) +#define ADC_PDMA_REGULAR_CYCLE (0x00000004) + +#define ADC_PDMA_HP_SINGLE (0x00000100) +#define ADC_PDMA_HP_SUBGROUP (0x00000200) +#define ADC_PDMA_HP_CYCLE (0x00000400) + +#define IS_ADC_PDMA(PDMA) (((PDMA) == ADC_PDMA_REGULAR_SINGLE) || \ + ((PDMA) == ADC_PDMA_REGULAR_SUBGROUP) || \ + ((PDMA) == ADC_PDMA_REGULAR_CYCLE) || \ + ((PDMA) == ADC_PDMA_HP_SINGLE) || \ + ((PDMA) == ADC_PDMA_HP_SUBGROUP) || \ + ((PDMA) == ADC_PDMA_HP_CYCLE)) + + +#define IS_ADC_INPUT_SAMPLING_TIME(TIME) ((TIME) <= 255) + +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) < 4096) + +#define IS_ADC_REGULAR_RANK(RANK) ((RANK) < 16) + +#define IS_ADC_HP_RANK(RANK) ((RANK) < 4) + +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 16)) +#define IS_ADC_REGULAR_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 16)) + +#define IS_ADC_HP_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 4)) +#define IS_ADC_HP_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 4)) + +#define ADC_VREF_1V215 (0ul << 4) +#define ADC_VREF_2V0 (1ul << 4) +#define ADC_VREF_2V5 (2ul << 4) +#define ADC_VREF_2V7 (3ul << 4) + +#define IS_ADC_VREF_SEL(SEL) ((SEL == ADC_VREF_1V215) || \ + (SEL == ADC_VREF_2V0) || \ + (SEL == ADC_VREF_2V5) || \ + (SEL == ADC_VREF_2V7)) + +typedef enum +{ + ADC_ALIGN_RIGHT = (0 << 14), + ADC_ALIGN_LEFT = (1 << 14), +} ADC_ALIGN_Enum; + +#define IS_ADC_ALIGN(ALIGN) (((ALIGN) == ADC_ALIGN_RIGHT) || ((ALIGN) == ADC_ALIGN_LEFT)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Functions ADC exported functions + * @{ + */ +void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn); +void ADC_Reset(HT_ADC_TypeDef* HT_ADCn); +void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); + +void ADC_SamplingTimeConfig(HT_ADC_TypeDef* HT_ADCn, u8 SampleClock); // Apply for the specific model only +void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock); +void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength); +void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x); + +void ADC_HPChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock); +void ADC_HPGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength); +void ADC_HPTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x); + +void ADC_ChannelDataAlign(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ADC_ALIGN_Enum ADC_ALIGN_x); +void ADC_ChannelOffsetValue(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u16 OffsetValue); +void ADC_ChannelOffsetCmd(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ControlStatus NewState); + +void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +void ADC_HPSoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); + +u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn); +u16 ADC_GetHPConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_HP_DATAn); + +void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState); +FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); +void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); +FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x); + +void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x); +void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n); +void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER); + +void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState); + +void ADC_VREFCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +void ADC_VREFConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_VREF_x); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_aes.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_aes.h new file mode 100644 index 00000000000..176bf19e728 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_aes.h @@ -0,0 +1,202 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_aes.h + * @version $Rev:: 2022 $ + * @date $Date:: 2020-02-03 #$ + * @brief The header file of the ADC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_AES_H +#define __HT32F1XXXX_AES_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup AES + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Types AES exported types + * @{ + */ + +/** + * @brief Definition of AES Init Structure + */ +typedef struct +{ + u16 AES_KeySize; + u16 AES_Dir; + u16 AES_Mode; + u16 AES_Swap; +} AES_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Constants AES exported constants + * @{ + */ + +#define IS_AES(AES) (AES == HT_AES) + +/* Definitions of AES key size */ +#define AES_KEYSIZE_128B ((u32)0x00000000) +#define AES_KEYSIZE_192B ((u32)0x00000020) +#define AES_KEYSIZE_256B ((u32)0x00000040) + +#define IS_AES_KEY_SIZE(SIZE) ((SIZE == AES_KEYSIZE_128B) || (SIZE == AES_KEYSIZE_192B) || (SIZE == AES_KEYSIZE_256B)) + +/* Definitions of AES direction */ +typedef enum +{ + AES_DIR_ENCRYPT =0, + AES_DIR_DECRYPT =2 +} AES_DIR_Enum; + +#define IS_AES_DIR(DIR) ((DIR == AES_DIR_ENCRYPT) || (DIR == AES_DIR_DECRYPT)) + +/* Definitions of AES mode */ +#define AES_MODE_ECB ((u32)0x00000000) +#define AES_MODE_CBC ((u32)0x00000004) +#define AES_MODE_CTR ((u32)0x00000008) + +#define IS_AES_MODE(MODE) ((MODE == AES_MODE_ECB) || (MODE == AES_MODE_CBC) || (MODE == AES_MODE_CTR)) + +/* Definitions of AES key start */ +#define AES_KEYSTART_DISABLE ((u32)0x00000000) +#define AES_KEYSTART_ENABLE ((u32)0x00000010) + +#define IS_AES_KEYSTART(KEYSTART) ((KEYSTART == AES_KEYSTART_DISABLE) || (KEYSTART == AES_KEYSTART_ENABLE)) + +/* Definitions of AES swap */ +#define AES_SWAP_DISABLE ((u32)0x00000000) +#define AES_SWAP_ENABLE ((u32)0x00000100) + +#define IS_AES_SWAP(SWAP) ((SWAP == AES_SWAP_DISABLE) || (SWAP == AES_SWAP_ENABLE)) + +/* Definitions of AES flush */ +#define AES_FLUSH_DISABLE ((u32)0x00000000) +#define AES_FLUSH_ENABLE ((u32)0x00000400) + +#define IS_AES_FLUSH(FLUSH) ((FLUSH == AES_FLUSH_DISABLE) || (FLUSH == AES_FLUSH_ENABLE)) + +/* Definitions of AES Enable */ +#define AES_DISABLE ((u32)0x00000000) +#define AES_ENABLE ((u32)0x00000001) + +#define IS_AES_CMD(CMD) ((CMD == AES_DISABLE) || (CMD == AES_ENABLE)) + +/* Definitions of AES status */ +#define AES_SR_IFEMPTY ((u32)0x00000001) +#define AES_SR_IFNFULL ((u32)0x00000002) +#define AES_SR_OFNEMPTY ((u32)0x00000004) +#define AES_SR_OFFULL ((u32)0x00000008) +#define AES_SR_BUSY ((u32)0x00000010) + +#define IS_AES_STATUS(STATUS) ((STATUS == AES_SR_IFEMPTY) || \ + (STATUS == AES_SR_IFNFULL) || \ + (STATUS == AES_SR_OFNEMPTY) || \ + (STATUS == AES_SR_OFFULL) || \ + (STATUS == AES_SR_BUSY)) + +/* Definitions of AES PDMA */ +#define AES_PDMA_IFDMAEN ((u32)0x00000001) +#define AES_PDMA_OFDMAEN ((u32)0x00000002) + +#define IS_AES_PDMA(AES_PDMA) ((AES_PDMA == AES_PDMA_IFDMAEN) || (AES_PDMA == AES_PDMA_OFDMAEN)) + +/* Definitions of AES Interrupt Status */ +#define AES_INTSR_IFINT ((u32)0x00000001) +#define AES_INTSR_OFINT ((u32)0x00000002) + +#define IS_AES_INTSR(AES_INSR) ((AES_INSR == AES_INTSR_IFINT) || (AES_INSR == AES_INTSR_OFINT)) + +/* Definitions of AES interrupt enable */ +#define AES_IER_IFINTEN ((u32)0x00000001) +#define AES_IER_OFINTEN ((u32)0x00000002) + +#define IS_AES_IER(ARS_IER) ((ARS_IER == AES_IER_IFINTEN) || (ARS_IER == AES_IER_OFINTEN)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Functions AES exported functions + * @{ + */ +void AES_ECB_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); +void AES_CBC_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); +void AES_CTR_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); +void AES_SetKeyTable(HT_AES_TypeDef* HT_AESn, uc8* Key, u32 keySize); +ErrStatus _AES_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum dir, uc8 *iv, u32 length, uc8 *inputData, u8 *outputData); +#define AES_ECB_CryptData(a, b, c, d, e) _AES_CryptData(a, b, NULL, c, d, e) +#define AES_CBC_CryptData _AES_CryptData +#define AES_CTR_CryptData(a, b, c, d, e) _AES_CryptData(a, AES_DIR_ENCRYPT, b, c, d, e) +#if 0 +ErrStatus AES_ECB_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum mode, u32 length, uc8 *inputData, u8 *outputData); +ErrStatus AES_CBC_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum mode, uc8 *iv, u32 length, uc8 *inputData, u8 *outputData); +ErrStatus AES_CTR_CryptData(HT_AES_TypeDef* HT_AESn, uc8 *iv, u32 length, uc8 *inputData, u8 *outputData); +#endif + +void AES_StartKey(HT_AES_TypeDef* HT_AESn); +void AES_DeInit(HT_AES_TypeDef* HT_AESn); +void AES_FIFOFlush(HT_AES_TypeDef* HT_AESn); +void AES_Cmd(HT_AES_TypeDef* HT_AESn, ControlStatus NewState); +FlagStatus AES_GetStatus(HT_AES_TypeDef* HT_AESn, u32 AES_Status); +void AES_PDMACmd(HT_AES_TypeDef* HT_AESn, u32 AES_PDMA_xFDMAEN, ControlStatus NewState); +FlagStatus AES_GetIntStatus(HT_AES_TypeDef* HT_AESn, u32 AES_INTSR_x); +void AES_IntConfig(HT_AES_TypeDef* HT_AESn, u32 AES_IER_x, ControlStatus NewState); +void AES_SetInputData(HT_AES_TypeDef* HT_AESn, uc32 AES_Data); +u32 AES_GetOutputData(HT_AES_TypeDef* HT_AESn); +void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, uc8* Vector); +void AESCore_IRQHandler(HT_AES_TypeDef* HT_AESn); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_bftm.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_bftm.h new file mode 100644 index 00000000000..091cc6dd77c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_bftm.h @@ -0,0 +1,99 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_bftm.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the BFTM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_BFTM_H +#define __HT32F1XXXX_BFTM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup BFTM + * @{ + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Types BFTM exported types + * @{ + */ +typedef u32 BFTM_DataTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Constants BFTM exported constants + * @{ + */ +#define IS_BFTM(x) ((x == HT_BFTM0) || (x == HT_BFTM1)) + +#define BFTM_FLAG_MATCH (1UL << 0) +#define BFTM_INT_MATCH (1UL << 0) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Functions BFTM exported functions + * @{ + */ +void BFTM_DeInit(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_EnaCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState); +void BFTM_SetCompare(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCompare); +u32 BFTM_GetCompare(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_SetCounter(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCounter); +u32 BFTM_GetCounter(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_OneShotModeCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState); +void BFTM_IntConfig(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState); +FlagStatus BFTM_GetFlagStatus(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_ClearFlag(HT_BFTM_TypeDef* HT_BFTMn); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_ckcu.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_ckcu.h new file mode 100644 index 00000000000..11369ee4d0d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_ckcu.h @@ -0,0 +1,734 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_ckcu.h + * @version $Rev:: 2974 $ + * @date $Date:: 2023-10-30 #$ + * @brief The header file of the Clock Control Unit library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_CKCU_H +#define __HT32F1XXXX_CKCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CKCU + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Exported_Types CKCU exported types + * @{ + */ + +/** + * @brief Enumeration of APB peripheral prescaler. + */ +typedef enum +{ + CKCU_APBCLKPRE_DIV1 = 0, + CKCU_APBCLKPRE_DIV2, + CKCU_APBCLKPRE_DIV4, + CKCU_APBCLKPRE_DIV8, + CKCU_APBCLKPRE_DIV16, + CKCU_APBCLKPRE_DIV32 +} CKCU_APBCLKPRE_TypeDef; + +/** + * @brief Enumeration of CK_REF prescaler. + */ +typedef enum +{ + CKCU_CKREFPRE_DIV2 = 0, + CKCU_CKREFPRE_DIV4, + CKCU_CKREFPRE_DIV6, + CKCU_CKREFPRE_DIV8, + CKCU_CKREFPRE_DIV10, + CKCU_CKREFPRE_DIV12, + CKCU_CKREFPRE_DIV14, + CKCU_CKREFPRE_DIV16, + CKCU_CKREFPRE_DIV18, + CKCU_CKREFPRE_DIV20, + CKCU_CKREFPRE_DIV22, + CKCU_CKREFPRE_DIV24, + CKCU_CKREFPRE_DIV26, + CKCU_CKREFPRE_DIV28, + CKCU_CKREFPRE_DIV30, + CKCU_CKREFPRE_DIV32, + CKCU_CKREFPRE_DIV34, + CKCU_CKREFPRE_DIV36, + CKCU_CKREFPRE_DIV38, + CKCU_CKREFPRE_DIV40, + CKCU_CKREFPRE_DIV42, + CKCU_CKREFPRE_DIV44, + CKCU_CKREFPRE_DIV46, + CKCU_CKREFPRE_DIV48, + CKCU_CKREFPRE_DIV50, + CKCU_CKREFPRE_DIV52, + CKCU_CKREFPRE_DIV54, + CKCU_CKREFPRE_DIV56, + CKCU_CKREFPRE_DIV58, + CKCU_CKREFPRE_DIV60, + CKCU_CKREFPRE_DIV62, + CKCU_CKREFPRE_DIV64 +} CKCU_CKREFPRE_TypeDef; + +/** + * @brief Enumeration of PLL clock source. + */ +typedef enum +{ + CKCU_PLLSRC_HSE = 0, + CKCU_PLLSRC_HSI +} CKCU_PLLSRC_TypeDef; + +#if (LIBCFG_CKCU_USART_PRESCALER) +/** + * @brief Enumeration of CK_USART prescaler. + */ +typedef enum +{ + CKCU_URPRE_DIV1 = 0, + CKCU_URPRE_DIV2 +} CKCU_URPRE_TypeDef; +#endif + +#if (!LIBCFG_NO_CKCU_USBPRE) +/** + * @brief Enumeration of CK_USB prescaler. + */ +typedef enum +{ + CKCU_USBPRE_DIV1 = 0, + CKCU_USBPRE_DIV2, +#if (LIBCFG_CKCU_USB_DIV3) + CKCU_USBPRE_DIV3 +#endif +} CKCU_USBPRE_TypeDef; +#endif + +#if (LIBCFG_CKCU_USB_PLL) +/** + * @brief Enumeration of CK_USB clock source. + */ +typedef enum +{ + CKCU_CKPLL = 0, + CKCU_CKUSBPLL +} CKCU_USBSRC_TypeDef; +#endif + +/** + * @brief Enumeration of WDT clock source. + */ +typedef enum +{ + CKCU_WDTSRC_LSI = 0, + CKCU_WDTSRC_LSE +} CKCU_WDTSRC_TypeDef; + + + +#if (!LIBCFG_CKCU_HSI_NO_AUTOTRIM) +/** + * @brief Enumeration of HSI auto-trim clock source. + */ +typedef enum +{ + CKCU_ATC_LSE = 0, + CKCU_ATC_USB = 1, +#if (LIBCFG_CKCU_AUTOTRIM_NOCKIN) +#else + CKCU_ATC_CKIN = 2, +#endif +} CKCU_ATC_TypeDef; + +#endif + +#if (LIBCFG_CKCU_ATM_V01) +/** + * @brief Enumeration of ATC search algorithm. + */ +typedef enum +{ + CKCU_ATC_BINARY_SEARCH = 0, + CKCU_ATC_LINEAR_SEARCH = 8 +} CKCU_ATCSearchAlgorithm_TypeDef; + +/** + * @brief Enumeration of ATC frequency tolerance. + */ +typedef enum +{ + CKCU_ATC_DOUBLE_PRECISION = 0, + CKCU_ATC_SINGLE_PRECISION = 4 +} CKCU_ATCFrqTolerance_TypeDef; +#endif + +/** + * @brief Enumeration of CK_AHB prescaler. + */ +typedef enum +{ + CKCU_SYSCLK_DIV1 = 0, + CKCU_SYSCLK_DIV2, + CKCU_SYSCLK_DIV4, + CKCU_SYSCLK_DIV8, +#if (LIBCFG_CKCU_SYSCLK_DIV8_ONLY) +#else + CKCU_SYSCLK_DIV16, + CKCU_SYSCLK_DIV32 +#endif +} CKCU_SYSCLKDIV_TypeDef; + +/** + * @brief Enumeration of CK_ADC prescaler. + */ +typedef enum +{ + #if (LIBCFG_CKCU_NO_ADCPRE_DIV1) + #else + CKCU_ADCPRE_DIV1 = 0, + #endif + CKCU_ADCPRE_DIV2 = 1, + CKCU_ADCPRE_DIV4, + CKCU_ADCPRE_DIV8, + CKCU_ADCPRE_DIV16, + CKCU_ADCPRE_DIV32, + CKCU_ADCPRE_DIV64, +#if (LIBCFG_CKCU_ADCPRE_DIV5) + CKCU_ADCPRE_DIV5 +#else + CKCU_ADCPRE_DIV6 +#endif +} CKCU_ADCPRE_TypeDef; + +/** + * @brief Enumeration of CK_ADCn. + */ +typedef enum +{ + CKCU_ADCPRE_ADC0 = 16, +} CKCU_ADCPRE_ADCn_TypeDef; + +/** + * @brief Enumeration of System clock source. + */ +typedef enum +{ + CKCU_SW_PLL = 1, + CKCU_SW_HSE = 2, + CKCU_SW_HSI = 3, +#if (LIBCFG_CKCU_NO_HCLK_LOW_SPEED) +#else + CKCU_SW_LSE = 6, + CKCU_SW_LSI = 7 +#endif +} CKCU_SW_TypeDef; + +/** + * @brief Enumeration of CKOUT clock source. + */ +typedef enum +{ + CKCU_CKOUTSRC_REFCK = 0, + CKCU_CKOUTSRC_HCLK_DIV16 = 1, + CKCU_CKOUTSRC_SYSCK_DIV16 = 2, + CKCU_CKOUTSRC_HSECK_DIV16 = 3, + CKCU_CKOUTSRC_HSICK_DIV16 = 4, + CKCU_CKOUTSRC_LSECK = 5, + CKCU_CKOUTSRC_LSICK = 6 +} CKCU_CKOUTSRC_TypeDef; + +/** + * @brief Enumeration of PLL clock source status. + */ +typedef enum +{ + CKCU_PLLST_SYSCK = 1, + CKCU_PLLST_USB = 4, + CKCU_PLLST_REFCK = 8 +} CKCU_PLLST_TypeDef; + +/** + * @brief Enumeration of HSI clock source status. + */ +typedef enum +{ + CKCU_HSIST_SYSCK = 1, + CKCU_HSIST_PLL = 2, + CKCU_HSIST_CKM = 4 +} CKCU_HSIST_TypeDef; + +/** + * @brief Enumeration of HSE clock source status. + */ +typedef enum +{ + CKCU_HSEST_SYSCK = 1, + CKCU_HSEST_PLL +} CKCU_HSEST_TypeDef; + +/** + * @brief Definition of CKOUT Init Structure. + */ +typedef struct +{ + CKCU_CKOUTSRC_TypeDef CKOUTSRC; +} CKCU_CKOUTInitTypeDef; + +/** + * @brief Definition of PLL Init Structure. + */ +typedef struct +{ + u32 CFG; + CKCU_PLLSRC_TypeDef ClockSource; + ControlStatus BYPASSCmd; +} CKCU_PLLInitTypeDef; + +/** + * @brief Definition of structure for clock frequency. + */ +typedef struct +{ + u32 PLL_Freq; + u32 SYSCK_Freq; + u32 HCLK_Freq; +#if (LIBCFG_CKCU_USART_PRESCALER) + u32 USART_Freq; +#endif + u32 ADC0_Freq; +} CKCU_ClocksTypeDef; + +#if (LIBCFG_CKCU_ATM_V01) +/** + * @brief Definition of ATC Init Structure. + */ +typedef struct +{ + CKCU_ATCSearchAlgorithm_TypeDef SearchAlgorithm; + CKCU_ATCFrqTolerance_TypeDef FrqTolerance; +} CKCU_ATCInitTypeDef; +#endif + +/** + * @brief Definition of initial structure of peripheral clock control. + */ +typedef union +{ + struct + { + /* Definitions of AHB clock control */ + unsigned long FMC :1; // Bit 0 + unsigned long :1; // Bit 1 + unsigned long SRAM :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long PDMA :1; // Bit 4 + unsigned long BM :1; // Bit 5 + unsigned long APB0 :1; // Bit 6 + unsigned long APB1 :1; // Bit 7 + + unsigned long CSIF :1; // Bit 8 + unsigned long CSIFMCLK :1; // Bit 9 + unsigned long USBD :1; // Bit 10 + unsigned long CKREF :1; // Bit 11 + unsigned long EBI :1; // Bit 12 + unsigned long CRC :1; // Bit 13 + unsigned long SDIO :1; // Bit 14 + unsigned long AES :1; // Bit 15 + + unsigned long PA :1; // Bit 16 + unsigned long PB :1; // Bit 17 + unsigned long PC :1; // Bit 18 + unsigned long PD :1; // Bit 19 + unsigned long PE :1; // Bit 20 + unsigned long PF :1; // Bit 21 + unsigned long :1; // Bit 22 + unsigned long :1; // Bit 23 + + unsigned long :1; // Bit 24 + unsigned long :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long :1; // Bit 28 + unsigned long :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB0 clock control */ + unsigned long I2C0 :1; // Bit 0 + unsigned long I2C1 :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long SPI0 :1; // Bit 4 + unsigned long SPI1 :1; // Bit 5 + unsigned long :1; // Bit 6 + unsigned long :1; // Bit 7 + + unsigned long USART0 :1; // Bit 8 + unsigned long USART1 :1; // Bit 9 + unsigned long UART0 :1; // Bit 10 + unsigned long UART1 :1; // Bit 11 + unsigned long :1; // Bit 12 + unsigned long :1; // Bit 13 + unsigned long AFIO :1; // Bit 14 + unsigned long EXTI :1; // Bit 15 + + unsigned long :1; // Bit 16 + unsigned long :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 + unsigned long :1; // Bit 22 + unsigned long :1; // Bit 23 + + unsigned long SCI0 :1; // Bit 24 + unsigned long I2S :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long SCI1 :1; // Bit 27 + unsigned long :1; // Bit 28 + unsigned long :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB1 clock control */ + unsigned long MCTM0 :1; // Bit 0 + unsigned long MCTM1 :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long WDT :1; // Bit 4 + unsigned long :1; // Bit 5 + unsigned long BKP :1; // Bit 6 + unsigned long :1; // Bit 7 + + unsigned long GPTM0 :1; // Bit 8 + unsigned long GPTM1 :1; // Bit 9 + unsigned long :1; // Bit 10 + unsigned long :1; // Bit 11 + unsigned long PWM0 :1; // Bit 12 + unsigned long :1; // Bit 13 + unsigned long :1; // Bit 14 + unsigned long :1; // Bit 15 + + unsigned long BFTM0 :1; // Bit 16 + unsigned long BFTM1 :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 +#if (LIBCFG_CMP_OPA) + unsigned long OPA0 :1; // Bit 22 +#else + unsigned long CMP :1; // Bit 22 +#endif + unsigned long OPA1 :1; // Bit 23 + + unsigned long ADC0 :1; // Bit 24 + unsigned long :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long SCTM0 :1; // Bit 28 + unsigned long SCTM1 :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + } Bit; + u32 Reg[3]; +} CKCU_PeripClockConfig_TypeDef; + +#define CKCU_APBPCSR_OFFSET (5) +#define CKCU_APBPCSR0 (0 << CKCU_APBPCSR_OFFSET) +#define CKCU_APBPCSR1 (1 << CKCU_APBPCSR_OFFSET) +#define CKCU_APBPCSR2 (4 << CKCU_APBPCSR_OFFSET) +typedef enum +{ + CKCU_PCLK_I2C0 = (CKCU_APBPCSR0 | 0), + CKCU_PCLK_I2C1 = (CKCU_APBPCSR0 | 2), + CKCU_PCLK_SPI0 = (CKCU_APBPCSR0 | 4), + CKCU_PCLK_SPI1 = (CKCU_APBPCSR0 | 6), + CKCU_PCLK_BFTM0 = (CKCU_APBPCSR0 | 12), + CKCU_PCLK_BFTM1 = (CKCU_APBPCSR0 | 14), + CKCU_PCLK_MCTM0 = (CKCU_APBPCSR0 | 16), + CKCU_PCLK_MCTM1 = (CKCU_APBPCSR0 | 18), + CKCU_PCLK_GPTM0 = (CKCU_APBPCSR0 | 20), + CKCU_PCLK_GPTM1 = (CKCU_APBPCSR0 | 22), + CKCU_PCLK_USART0 = (CKCU_APBPCSR0 | 24), + CKCU_PCLK_USART1 = (CKCU_APBPCSR0 | 26), + CKCU_PCLK_UART0 = (CKCU_APBPCSR0 | 28), + CKCU_PCLK_UART1 = (CKCU_APBPCSR0 | 30), + CKCU_PCLK_AFIO = (CKCU_APBPCSR1 | 0), + CKCU_PCLK_EXTI = (CKCU_APBPCSR1 | 2), + CKCU_PCLK_ADC = (CKCU_APBPCSR1 | 4), + CKCU_PCLK_CMP = (CKCU_APBPCSR1 | 8), + CKCU_PCLK_WDTR = (CKCU_APBPCSR1 | 12), + CKCU_PCLK_BKPR = (CKCU_APBPCSR1 | 14), +#if (LIBCFG_SCI0) + CKCU_PCLK_SCI0 = (CKCU_APBPCSR1 | 16), +#endif +#if (LIBCFG_SCI1) + CKCU_PCLK_SCI1 = (CKCU_APBPCSR1 | 18), +#endif + CKCU_PCLK_I2S = (CKCU_APBPCSR1 | 20), + CKCU_PCLK_SCTM0 = (CKCU_APBPCSR1 | 24), + CKCU_PCLK_SCTM1 = (CKCU_APBPCSR1 | 26), + CKCU_PCLK_PWM0 = (CKCU_APBPCSR2 | 16), +} CKCU_PeripPrescaler_TypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Exported_Constants CKCU exported constants + * @{ + */ + +/* Definitions of clock ready flag */ +#define CKCU_FLAG_PLLRDY (1UL << 1) +#define CKCU_FLAG_HSERDY (1UL << 2) +#define CKCU_FLAG_HSIRDY (1UL << 3) +#define CKCU_FLAG_LSERDY (1UL << 4) +#define CKCU_FLAG_LSIRDY (1UL << 5) +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_FLAG_USBPLLRDY (1UL) +#define IS_CKCU_FLAG(FLAG) (((FLAG & 0xFFFFFFC0) == 0) && (FLAG != 0)) +#else +#define IS_CKCU_FLAG(FLAG) (((FLAG & 0xFFFFFFC1) == 0) && (FLAG != 0)) +#endif +/* Definitions of clock interrupt & flag */ +#define CKCU_INT_CKS (1UL) +#define CKCU_INT_PLLRDY (1UL << 2) +#define CKCU_INT_HSERDY (1UL << 3) +#define CKCU_INT_HSIRDY (1UL << 4) +#define CKCU_INT_LSERDY (1UL << 5) +#define CKCU_INT_LSIRDY (1UL << 6) + +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_INT_USBPLLRDY (1UL << 1) +#define IS_CKCU_INT_FLAG(FLAG) (((FLAG & 0xFFFFFF80) == 0) && (FLAG != 0)) +#else +#define IS_CKCU_INT_FLAG(FLAG) (((FLAG & 0xFFFFFF82) == 0) && (FLAG != 0)) +#endif + +#define CKCU_INT_CKSIE (1UL << 16) +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_INT_USBPLLRDYIE (1UL << 17) +#endif +#define CKCU_INT_PLLRDYIE (1UL << 18) +#define CKCU_INT_HSERDYIE (1UL << 19) +#define CKCU_INT_HSIRDYIE (1UL << 20) +#define CKCU_INT_LSERDYIE (1UL << 21) +#define CKCU_INT_LSIRDYIE (1UL << 22) + +#if (LIBCFG_CKCU_USB_PLL) +#define IS_CKCU_INT(IT) (((IT & 0xFF80FFFF) == 0) && (IT != 0)) +#else +#define IS_CKCU_INT(IT) (((IT & 0xFF82FFFF) == 0) && (IT != 0)) +#endif + +#define IS_PLL_CLKSRC(SRC) ((SRC == CKCU_PLLSRC_HSE) || \ + (SRC == CKCU_PLLSRC_HSI)) + +/* Definitions of PLL frequency */ +#if (LIBCDG_CKCU_PLL_144M) +#define CKCU_PLL_4M_144M ((36UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_144M ((18UL << 23) | (0UL << 21)) +#define CKCU_PLL_12M_144M ((12UL << 23) | (0UL << 21)) +#define CKCU_PLL_16M_144M (( 9UL << 23) | (0UL << 21)) +#endif + +#define CKCU_PLL_4M_48M ((12UL << 23) | (0UL << 21)) +#define CKCU_PLL_4M_72M ((18UL << 23) | (0UL << 21)) +#define CKCU_PLL_4M_96M ((24UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_48M (( 6UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_64M (( 8UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_72M (( 9UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_80M ((10UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_96M ((12UL << 23) | (0UL << 21)) +#define CKCU_PLL_12M_48M (( 4UL << 23) | (0UL << 21)) +#define CKCU_PLL_12M_72M (( 6UL << 23) | (0UL << 21)) +#define CKCU_PLL_12M_96M (( 8UL << 23) | (0UL << 21)) +#define CKCU_PLL_16M_80M (( 5UL << 23) | (0UL << 21)) +#define CKCU_PLL_16M_96M (( 6UL << 23) | (0UL << 21)) + +#if (LIBCDG_CKCU_PLL_144M) +#define IS_PLL_CFG(CFG) (((CFG & 0xE01FFFFF) == 0x0)) +#else +#define IS_PLL_CFG(CFG) (((CFG & 0xF01FFFFF) == 0x0)) +#endif + +#if (LIBCFG_CKCU_USB_PLL) +/* Definitions of USBPLL frequency */ +#define CKCU_USBPLL_4M_48M ((12UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_8M_48M (( 6UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_12M_48M (( 4UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_16M_48M (( 3UL << 7) | (0UL << 5)) + +#define IS_USBPLL_CFG(CFG) (((CFG & 0xFFFFF81F) == 0x0)) +#endif + +/* Definitions of MCU debug control */ +#define CKCU_DBG_SLEEP (1UL) +#define CKCU_DBG_DEEPSLEEP1 (1UL << 1) +#define CKCU_DBG_POWERDOWN (1UL << 2) +#define CKCU_DBG_WDT_HALT (1UL << 3) +#define CKCU_DBG_MCTM0_HALT (1UL << 4) +#define CKCU_DBG_MCTM1_HALT (1UL << 5) +#define CKCU_DBG_GPTM0_HALT (1UL << 6) +#define CKCU_DBG_GPTM1_HALT (1UL << 7) +#define CKCU_DBG_USART0_HALT (1UL << 8) +#define CKCU_DBG_USART1_HALT (1UL << 9) +#define CKCU_DBG_SPI0_HALT (1UL << 10) +#define CKCU_DBG_SPI1_HALT (1UL << 11) +#define CKCU_DBG_I2C0_HALT (1UL << 12) +#define CKCU_DBG_I2C1_HALT (1UL << 13) +#define CKCU_DBG_DEEPSLEEP2 (1UL << 14) +#define CKCU_DBG_SCI_HALT (1UL << 15) +#define CKCU_DBG_BFTM0_HALT (1UL << 16) +#define CKCU_DBG_BFTM1_HALT (1UL << 17) +#define CKCU_DBG_UART0_HALT (1UL << 18) +#define CKCU_DBG_UART1_HALT (1UL << 19) +#define CKCU_DBG_TRACE_ON (1UL << 20) + +#if (LIBCFG_SCI0) +#define CKCU_DBG_SCI0_HALT (1UL << 15) +#endif +#if (LIBCFG_SCI1) +#define CKCU_DBG_SCI1_HALT (1UL << 21) +#endif + +#define IS_CKCU_DBG(MODE) (((MODE & 0xBF200000) == 0) && (MODE != 0)) + +/* Definitions of AHB clock control */ +#define CKCU_AHBEN_SLEEP_FMC (1UL) +#define CKCU_AHBEN_SLEEP_SRAM (1UL << 2) +#define CKCU_AHBEN_SLEEP_BM (1UL << 5) +#define CKCU_AHBEN_SLEEP_APB0 (1UL << 6) +#define CKCU_AHBEN_SLEEP_APB1 (1UL << 7) + +#define IS_CKCU_SLEEP_AHB(PERIPH) (((PERIPH & 0xFFFFFF1A) == 0) && (PERIPH != 0)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Exported_Functions CKCU exported functions + * @{ + */ +void CKCU_DeInit(void); + +void CKCU_HSICmd(ControlStatus Cmd); +void CKCU_HSECmd(ControlStatus Cmd); +bool CKCU_IS_HSI_USED(CKCU_HSIST_TypeDef Target); +bool CKCU_IS_HSE_USED(CKCU_HSEST_TypeDef Target); +FlagStatus CKCU_GetClockReadyStatus(u32 CKCU_FLAG); +ErrStatus CKCU_WaitHSEReady(void); + +ErrStatus CKCU_SysClockConfig(CKCU_SW_TypeDef CLKSRC); +u32 CKCU_GetSysClockSource(void); + +void CKCU_PeripClockConfig(CKCU_PeripClockConfig_TypeDef Clock, ControlStatus Cmd); + +void CKCU_PLLInit(CKCU_PLLInitTypeDef *PLL_InitStruct); +void CKCU_PLLCmd(ControlStatus Cmd); +bool CKCU_IS_PLL_USED(CKCU_PLLST_TypeDef Target); + +#if (LIBCFG_CKCU_USB_PLL) +void CKCU_USBPLLInit(CKCU_PLLInitTypeDef *USBPLL_InitStruct); +void CKCU_USBPLLCmd(ControlStatus Cmd); +void CKCU_USBClockConfig(CKCU_USBSRC_TypeDef USBSRC); +#endif + +void CKCU_SleepClockConfig(u32 CKCU_CLK, ControlStatus Cmd); + +void CKCU_SetHCLKPrescaler(CKCU_SYSCLKDIV_TypeDef HCLKPRE); +void CKCU_SetCKREFPrescaler(CKCU_CKREFPRE_TypeDef CKREFPRE); +void CKCU_SetADCnPrescaler(CKCU_ADCPRE_ADCn_TypeDef CKCU_ADCPRE_ADCn, CKCU_ADCPRE_TypeDef CKCU_ADCPRE_DIVn); +#define CKCU_SetADCPrescaler(DIV) CKCU_SetADCnPrescaler(CKCU_ADCPRE_ADC0, DIV) + +#if (LIBCFG_CKCU_USART_PRESCALER) +void CKCU_SetUSARTPrescaler(CKCU_URPRE_TypeDef URPRE); +#endif + +#if (!LIBCFG_NO_CKCU_USBPRE) +void CKCU_SetUSBPrescaler(CKCU_USBPRE_TypeDef USBPRE); +#endif + +#if (LIBCFG_CKCU_NO_APB_PRESCALER) +#else +void CKCU_SetPeripPrescaler(CKCU_PeripPrescaler_TypeDef Perip, CKCU_APBCLKPRE_TypeDef PCLKPRE); +#endif + +void CKCU_GetClocksFrequency(CKCU_ClocksTypeDef* CKCU_Clk); +u32 CKCU_GetPLLFrequency(void); +u32 CKCU_GetPeripFrequency(CKCU_PeripPrescaler_TypeDef Perip); + +void CKCU_CKMCmd(ControlStatus Cmd); +void CKCU_PSRCWKUPCmd(ControlStatus Cmd); +void CKCU_BKISOCmd(ControlStatus Cmd); +void CKCU_CKOUTConfig(CKCU_CKOUTInitTypeDef *CKOUTInit); +void CKCU_MCUDBGConfig(u32 CKCU_DBGx, ControlStatus Cmd); + +void CKCU_IntConfig(u32 CKCU_INT, ControlStatus Cmd); +FlagStatus CKCU_GetIntStatus(u32 CKCU_INT); +void CKCU_ClearIntFlag(u32 CKCU_INT); + +#if (!LIBCFG_CKCU_HSI_NO_AUTOTRIM) +#if (LIBCFG_CKCU_ATM_V01) +void CKCU_ATCInit(CKCU_ATCInitTypeDef* ATC_InitStruct); +void CKCU_HSIAutoTrimAlgorithm(u32 Algo); +void CKCU_HSIAutoTrimFreqTolerance(u32 Tolerance); +#endif +void CKCU_HSIAutoTrimClkConfig(CKCU_ATC_TypeDef CLKSRC); +void CKCU_HSIAutoTrimCmd(ControlStatus Cmd); +bool CKCU_HSIAutoTrimIsReady(void); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_cmp.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_cmp.h new file mode 100644 index 00000000000..7650247fb4e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_cmp.h @@ -0,0 +1,230 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_cmp.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the CMP library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_CMP_H +#define __HT32F1XXXX_CMP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CMP + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Types CMP exported types + * @{ + */ + +typedef struct +{ + u32 CMP_Wakeup; + u32 CMP_OutputSelection; + u32 CMP_ScalerSource; + u32 CMP_ScalerOutputBuf; + u32 CMP_ScalerEnable; + u32 CMP_CoutSync; + u32 CMP_OutputPol; + u32 CMP_InvInputSelection; + u32 CMP_Hysteresis; + u32 CMP_Speed; +} CMP_InitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Constants CMP exported constants + * @{ + */ + +/* Definitions of CMP Protection Key */ +#define CMP_PROTECT_KEY ((u32)0x9C3A0000) + + +/* Definitions of CMP Output Status */ +#define CMP_OUTPUT_HIGH ((u32)0x00008000) +#define CMP_OUTPUT_LOW ((u32)0x00000000) + + +/* Definitions of CMP Wakeup Control Bit */ +#define CMP_WUP_ENABLE ((u32)0x00004000) +#define CMP_WUP_DISABLE ((u32)0x00000000) + +#define IS_CMP_Wakeup_Set(x) ((x == CMP_WUP_ENABLE) || (x == CMP_WUP_DISABLE)) + + +/* Definitions of CMP Output Selection for IP Trigger Source */ +#define CMP_TRIG_NONE ((u32)0x00000000) +#define CMP_TRIG_GPTM_CH3 ((u32)0x00000800) +#define CMP_TRIG_MCTM_CH3 ((u32)0x00001000) +#define CMP_TRIG_MCTM_BK1 ((u32)0x00001800) +#define CMP_TRIG_ADC ((u32)0x00002000) + +#define IS_CMP_OutputSelection(x) ((x == CMP_TRIG_NONE) || (x == CMP_TRIG_GPTM_CH3) || (x == CMP_TRIG_MCTM_CH3) || \ + (x == CMP_TRIG_MCTM_BK1) || (x == CMP_TRIG_ADC)) + +/* Definitions of CMP Scaler Source Selection */ +#define CMP_SCALER_SRC_VDDA ((u32)0x00000000) +#define CMP_SCALER_SRC_VREF ((u32)0x00000400) + +#define IS_CMP_ScalerSource(x) ((x == CMP_SCALER_SRC_VDDA) || (x == CMP_SCALER_SRC_VREF)) + + +/* Definitions of CMP Scaler Output Enable Bit */ +#define CMP_SCALER_OBUF_DISABLE ((u32)0x00000000) +#define CMP_SCALER_OBUF_ENABLE ((u32)0x00000200) + +#define IS_CMP_ScalerOutputBuf(x) ((x == CMP_SCALER_OBUF_DISABLE) || (x == CMP_SCALER_OBUF_ENABLE)) + + +/* Definitions of CMP Scaler Enable Bit */ +#define CMP_SCALER_DISABLE ((u32)0x00000000) +#define CMP_SCALER_ENABLE ((u32)0x00000100) + +#define IS_CMP_ScalerEnable(x) ((x == CMP_SCALER_DISABLE) || (x == CMP_SCALER_ENABLE)) + + +/* Definitions of CMP Sync Output Enable bit */ +#define CMP_ASYNC_OUTPUT ((u32)0x00000000) +#define CMP_SYNC_OUTPUT ((u32)0x00000080) + +#define IS_CMP_CoutSynchronized(x) ((x == CMP_ASYNC_OUTPUT) || (x == CMP_SYNC_OUTPUT)) + + +/* Definitions of CMP Output Polarity Selection */ +#define CMP_NONINV_OUTPUT ((u32)0x00000000) +#define CMP_INV_OUTPUT ((u32)0x00000040) + +#define IS_CMP_OutputPol_Set(x) ((x == CMP_NONINV_OUTPUT) || (x == CMP_INV_OUTPUT)) + + +/* Definitions of CMP Inverted Input Source Selection */ +#define CMP_EXTERNAL_CN_IN ((u32)0x00000000) +#define CMP_SCALER_CN_IN ((u32)0x00000010) + +#define IS_CMP_InvInputSelection(x) ((x == CMP_EXTERNAL_CN_IN) || (x == CMP_SCALER_CN_IN)) + + +/* Definitions of CMP Hysteresis Level Selection */ +#define CMP_NO_HYSTERESIS ((u32)0x00000000) +#define CMP_LOW_HYSTERESIS ((u32)0x00000004) +#define CMP_MID_HYSTERESIS ((u32)0x00000008) +#define CMP_HIGH_HYSTERESIS ((u32)0x0000000C) + +#define IS_CMP_Hysteresis_Set(x) ((x == CMP_NO_HYSTERESIS) || (x == CMP_LOW_HYSTERESIS) || (x == CMP_MID_HYSTERESIS) || \ + (x == CMP_HIGH_HYSTERESIS)) + +/* Definitions of CMP Speed Mode Selection */ +#define CMP_HIGH_SPEED ((u32)0x00000002) +#define CMP_LOW_SPEED ((u32)0x00000000) + +#define IS_CMP_Speed_Set(x) ((x == CMP_HIGH_SPEED) || (x == CMP_LOW_SPEED)) + + +/* Definitions of CMP Enable bit */ +#define CMP_ENABLE ((u32)0x00000001) + + +/* Definitions of CMP Output Edge Interrupt Enable bit */ +#define CMP_INT_RE ((u32)0x00000002) +#define CMP_INT_FE ((u32)0x00000001) + +/* Check the CMP Interrupt Parameter */ +#define IS_CMP_INT(x) ((x & 0xFFFFFF00) != 0x0) + + +/* Definitions of CMP Output Edge Detection Enable bit */ +#define CMP_RE_Detect ((u32)0x00000200) +#define CMP_FE_Detect ((u32)0x00000100) + +#define IS_CMP_EdgeDetect(x) ((x == CMP_RE_Detect) || (x == CMP_FE_Detect)) + + +/* Definitions of CMP Output Edge Flag */ +#define CMP_FLAG_RE ((u32)0x00000002) +#define CMP_FLAG_FE ((u32)0x00000001) + +/* Check the CMP flag Parameter */ +#define IS_CMP_FLAG(x) ((x & 0xFFFFFF00) != 0x0) + + +/* Check the CMPx Parameter */ +#define IS_CMP(x) ((x == HT_CMP0) || (x == HT_CMP1)) + + +/* Check the Scaler Value */ +#define IS_SCALER_VALUE(x) (x <= 0x3F) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Functions CMP exported functions + * @{ + */ +void CMP_DeInit(HT_CMP_TypeDef* HT_CMPn); +void CMP_UnprotectConfig(HT_CMP_TypeDef* HT_CMPn); +void CMP_Init(HT_CMP_TypeDef* HT_CMPn, CMP_InitTypeDef* CMP_InitStruct); +void CMP_StructInit(CMP_InitTypeDef* CMP_InitStruct); +void CMP_Cmd(HT_CMP_TypeDef* HT_CMPn, ControlStatus NewState); +void CMP_IntConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_INT_x, ControlStatus NewState); +void CMP_EdgeDetectConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_xE_Detect, ControlStatus NewState); +FlagStatus CMP_GetFlagStatus(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x); +void CMP_ClearFlag(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x); +FlagStatus CMP_GetOutputStatus(HT_CMP_TypeDef* HT_CMPn); +void CMP_SetScalerValue(HT_CMP_TypeDef* HT_CMPn, u8 Scaler_Value); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_cmp_op.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_cmp_op.h new file mode 100644 index 00000000000..bcfb5d82ff7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_cmp_op.h @@ -0,0 +1,124 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_cmp_op.h + * @version $Rev:: 122 $ + * @date $Date:: 2017-06-13 #$ + * @brief The header file of the CMP_OP library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_CMP_OP_H +#define __HT32F1XXXX_CMP_OP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CMP_OP + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CMP_OP_Exported_Constants CMP_OP exported constants + * @{ + */ + +/* Definitions of CMP_OP modes */ +#define OP_MODE (0x00000000ul) +#define CMP_MODE (0x00000002ul) + +#define IS_CMP_OP_MODE(MODE) ((MODE == OP_MODE) || (MODE == CMP_MODE)) + +/* Definitions the cancelation reference input of CMP_OP */ +#define CMP_OP_NEGATIVE_INPUT (0x00000000ul) +#define CMP_OP_POSITIVE_INPUT (0x00000008ul) + +#define IS_CMP_OP_REF(REF) ((REF == CMP_OP_NEGATIVE_INPUT ) || (REF == CMP_OP_POSITIVE_INPUT)) + +/* Definitions of CMP_OP input offset */ +#define CMP_OP_IOVC_MIN (0x00000000ul) +#define CMP_OP_IOVC_CENTER (0x00000020ul) +#define CMP_OP_IOVC_MAX (0x0000003Ful) + +#define IS_CMP_OP_IOVC(IOVC) (IOVC <= 63 ) + +/* Definitions of CMP_OP interrupts */ +#define CMP_OP_INT_FALLING (0x00000001ul) +#define CMP_OP_INT_RISING (0x00000002ul) + +#define IS_CMP_OP_INT(CMP_OP_INT) (((CMP_OP_INT & 0xFFFFFFFC) == 0x0) && \ + (CMP_OP_INT != 0x0)) + +/* Definitions of CMP_OP interrupt flags */ +#define CMP_OP_FLAG_FALLING (0x00000001ul) +#define CMP_OP_FLAG_RISING (0x00000002ul) + +#define IS_CMP_OP_FLAG(FLAG) (((FLAG & 0xFFFFFFFC) == 0x0) && \ + (FLAG != 0x0)) + +/* check parameter of the CMP_OPx */ +#define IS_CMP_OP_ALL_PERIPH(PERIPH) ((PERIPH == HT_CMP_OP0) || (PERIPH == HT_CMP_OP1)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CMP_OP_Exported_Functions CMP_OP exported functions + * @{ + */ +void CMP_OP_DeInit(HT_CMP_OP_TypeDef* CMP_OPx); +void CMP_OP_Config(HT_CMP_OP_TypeDef* CMP_OPx, u32 mode, u32 cancellation); +void CMP_OP_Cmd(HT_CMP_OP_TypeDef* CMP_OPx, ControlStatus NewState); +void CMP_OP_CancellationModeConfig(HT_CMP_OP_TypeDef* CMP_OPx, u16 CMP_OP_REF_INPUT); +void CMP_OP_SetCancellationVaule(HT_CMP_OP_TypeDef* CMP_OPx, u32 cancellation); +u32 CMP_OP_GetCancellationVaule(HT_CMP_OP_TypeDef* CMP_OPx); +void CMP_OP_IntConfig(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_INT, ControlStatus NewState); +FlagStatus CMP_OP_GetIntStatus(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_INT); +FlagStatus CMP_OP_GetFlagStatus(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_FLAG); +void CMP_OP_ClearIntPendingBit(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_INT); +FlagStatus CMP_OP_GetOutputStatus(HT_CMP_OP_TypeDef* CMP_OPx); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_crc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_crc.h new file mode 100644 index 00000000000..0247ced9ca6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_crc.h @@ -0,0 +1,124 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_crc.h + * @version $Rev:: 2787 $ + * @date $Date:: 2022-11-23 #$ + * @brief The header file of the CRC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_CRC_H +#define __HT32F1XXXX_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Types CRC exported types + * @{ + */ + +/* Definition of CRC Init Structure */ +typedef enum +{ + CRC_CCITT_POLY = 0, + CRC_16_POLY = 1, + CRC_32_POLY = 2, + CRC_USER_DEFINE = 0xF +} CRC_Mode; + +typedef struct +{ + CRC_Mode Mode; + u32 uSeed; + u32 uCR; +} CRC_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Constants CRC exported constants + * @{ + */ +#define IS_CRC_POLY(POLY) ((POLY == CRC_CCITT_POLY) || \ + (POLY == CRC_16_POLY) || \ + (POLY == CRC_32_POLY) || \ + (POLY == CRC_USER_DEFINE)) + +#define CRC_NORMAL_WR (0) +#define CRC_BIT_RVS_WR (1UL << 2) +#define CRC_BYTE_RVS_WR (1UL << 3) +#define CRC_CMPL_WR (1UL << 4) + +#define CRC_NORMAL_SUM (0) +#define CRC_BIT_RVS_SUM (1UL << 5) +#define CRC_BYTE_RVS_SUM (1UL << 6) +#define CRC_CMPL_SUM (1UL << 7) + +#define IS_CRC_MOD(MOD) ((MOD & 0xFFFFFF00) == 0) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC exported functions + * @{ + */ +void CRC_DeInit(HT_CRC_TypeDef* HT_CRCn); +void CRC_Init(HT_CRC_TypeDef* HT_CRCn, CRC_InitTypeDef* CRC_InitStruct); +u32 CRC_Process(HT_CRC_TypeDef* HT_CRCn, u8 *buffer, u32 length); + +u16 CRC_CCITT(u16 seed, u8 *buffer, u32 length); +u16 CRC_16(u16 seed, u8 *buffer, u32 length); +u32 CRC_32(u32 seed, u8 *buffer, u32 length); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_ebi.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_ebi.h new file mode 100644 index 00000000000..b09ba30b777 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_ebi.h @@ -0,0 +1,289 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_ebi.h + * @version $Rev:: 2788 $ + * @date $Date:: 2022-11-24 #$ + * @brief The header file of the EBI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_EBI_H +#define __HT32F1XXXX_EBI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup EBI + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Types EBI exported types + * @{ + */ +typedef struct +{ + u32 EBI_Bank; + u32 EBI_Mode; + #if (LIBCFG_EBI_BYTELAND_ASYNCREADY) + u32 EBI_ByteLane; + u32 EBI_AsynchronousReady; + u32 EBI_ARDYTimeOut; + u32 EBI_ByteLanePolarity; + u32 EBI_ReadySignalPolarity; + #endif + u32 EBI_IdleCycle; + u32 EBI_ChipSelectPolarity; + u32 EBI_AddressLatchPolarity; + u32 EBI_WriteEnablePolarity; + u32 EBI_ReadEnablePolarity; + u32 EBI_IdleCycleTime; + u32 EBI_AddressSetupTime; + u32 EBI_AddressHoldTime; + u32 EBI_WriteSetupTime; + u32 EBI_WriteStrobeTime; + u32 EBI_WriteHoldTime; + u32 EBI_ReadSetupTime; + u32 EBI_ReadStrobeTime; + u32 EBI_ReadHoldTime; + #if !(LIBCFG_EBI_V01) + u32 EBI_PageMode; + u32 EBI_PageLength; + u32 EBI_PageHitMode; + u32 EBI_PageAccessTime; + u32 EBI_PageOpenTime; + #endif +} EBI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Constants EBI exported constants + * @{ + */ +#define EBI_BANK_0 ((u32)0x00000000) +#define EBI_BANK_1 ((u32)0x00000001) +#define EBI_BANK_2 ((u32)0x00000002) +#define EBI_BANK_3 ((u32)0x00000003) + +#define IS_EBI_BANK(BANK) ((BANK == EBI_BANK_0) || \ + (BANK == EBI_BANK_1) || \ + (BANK == EBI_BANK_2) || \ + (BANK == EBI_BANK_3)) + + +#define EBI_MODE_D8A8 ((u32)0x00000000) +#define EBI_MODE_D16A16ALE ((u32)0x00000001) +#define EBI_MODE_D8A24ALE ((u32)0x00000002) +#define EBI_MODE_D16 ((u32)0x00000003) + +#define IS_EBI_MODE(MODE) ((MODE == EBI_MODE_D8A8) || \ + (MODE == EBI_MODE_D16A16ALE) || \ + (MODE == EBI_MODE_D8A24ALE) || \ + (MODE == EBI_MODE_D16)) + + +#if (LIBCFG_EBI_BYTELAND_ASYNCREADY) +#define EBI_BYTELANE_ENABLE ((u32)0x01000000) +#define EBI_BYTELANE_DISABLE ((u32)0x00000000) + +#define IS_EBI_BYTELANE(BYTELANE) ((BYTELANE == EBI_BYTELANE_ENABLE) || \ + (BYTELANE == EBI_BYTELANE_DISABLE)) +#endif + + +#define EBI_IDLECYCLE_ENABLE ((u32)0x00000000) +#define EBI_IDLECYCLE_DISABLE ((u32)0x00001000) + +#define IS_EBI_IDLECYCLE(IDLECYCLE) ((IDLECYCLE == EBI_IDLECYCLE_ENABLE) || \ + (IDLECYCLE == EBI_IDLECYCLE_DISABLE)) + + +#if (LIBCFG_EBI_BYTELAND_ASYNCREADY) +#define EBI_ASYNCHRONOUSREADY_ENABLE ((u32)0x00010000) +#define EBI_ASYNCHRONOUSREADY_DISABLE ((u32)0x00000000) + +#define IS_EBI_ARDY(ARDY) ((ARDY == EBI_ASYNCHRONOUSREADY_ENABLE) || \ + (ARDY == EBI_ASYNCHRONOUSREADY_DISABLE)) + + +#define EBI_ARDYTIMEOUT_ENABLE ((u32)0x00000000) +#define EBI_ARDYTIMEOUT_DISABLE ((u32)0x00020000) + +#define IS_EBI_ARDY_TIMEOUT(TIMEOUT) ((TIMEOUT == EBI_ARDYTIMEOUT_ENABLE) || \ + (TIMEOUT == EBI_ARDYTIMEOUT_DISABLE)) +#endif + + +#define EBI_CHIPSELECTPOLARITY_LOW ((u32)0x00000000) +#define EBI_CHIPSELECTPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_CS_POLARITY(POLARITY) ((POLARITY == EBI_CHIPSELECTPOLARITY_LOW) || \ + (POLARITY == EBI_CHIPSELECTPOLARITY_HIGH)) + + +#define EBI_ADDRESSLATCHPOLARITY_LOW ((u32)0x00000000) +#define EBI_ADDRESSLATCHPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_ALE_POLARITY(POLARITY) ((POLARITY == EBI_ADDRESSLATCHPOLARITY_LOW) || \ + (POLARITY == EBI_ADDRESSLATCHPOLARITY_HIGH)) + + +#define EBI_WRITEENABLEPOLARITY_LOW ((u32)0x00000000) +#define EBI_WRITEENABLEPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_WE_POLARITY(POLARITY) ((POLARITY == EBI_WRITEENABLEPOLARITY_LOW) || \ + (POLARITY == EBI_WRITEENABLEPOLARITY_HIGH)) + + +#define EBI_READENABLEPOLARITY_LOW ((u32)0x00000000) +#define EBI_READENABLEPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_RE_POLARITY(POLARITY) ((POLARITY == EBI_READENABLEPOLARITY_LOW) || \ + (POLARITY == EBI_READENABLEPOLARITY_HIGH)) + + +#if (LIBCFG_EBI_BYTELAND_ASYNCREADY) +#define EBI_BYTELANEPOLARITY_LOW ((u32)0x00000000) +#define EBI_BYTELANEPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_BL_POLARITY(POLARITY) ((POLARITY == EBI_BYTELANEPOLARITY_LOW) || \ + (POLARITY == EBI_BYTELANEPOLARITY_HIGH)) + + +#define EBI_READYSIGNALPOLARITY_LOW ((u32)0x00000000) +#define EBI_READYSIGNALPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_ARDY_POLARITY(POLARITY) ((POLARITY == EBI_READYSIGNALPOLARITY_LOW) || \ + (POLARITY == EBI_READYSIGNALPOLARITY_HIGH)) +#endif + +#if !(LIBCFG_EBI_V01) +#define EBI_PAGEMODE_ENABLE ((u32)0x01000000) +#define EBI_PAGEMODE_DISABLE ((u32)0x00000000) + +#define IS_EBI_PAGE_MODE(MODE) ((MODE == EBI_PAGEMODE_ENABLE) || \ + (MODE == EBI_PAGEMODE_DISABLE)) + + +#define EBI_PAGELENGTH_4 ((u32)0x00000000) +#define EBI_PAGELENGTH_8 ((u32)0x00000001) +#define EBI_PAGELENGTH_16 ((u32)0x00000002) +#define EBI_PAGELENGTH_32 ((u32)0x00000003) + +#define IS_EBI_PAGE_LENGTH(LENGTH) ((LENGTH == EBI_PAGELENGTH_4) || \ + (LENGTH == EBI_PAGELENGTH_8) || \ + (LENGTH == EBI_PAGELENGTH_16) || \ + (LENGTH == EBI_PAGELENGTH_32)) + + +#define EBI_PAGEHITMODE_ADDINC ((u32)0x00000010) +#define EBI_PAGEHITMODE_INTRPAGE ((u32)0x00000000) + +#define IS_EBI_PAGE_HIT_MODE(MODE) ((MODE == EBI_PAGEHITMODE_ADDINC) || \ + (MODE == EBI_PAGEHITMODE_INTRPAGE)) +#endif + + +#if !(LIBCFG_EBI_V01) +#if (LIBCFG_EBI_BYTELAND_ASYNCREADY) +#define EBI_INT_TOUT ((u32)0x00000001) +#endif +#define EBI_INT_ACCDIS ((u32)0x00000002) +#define EBI_INT_ACCERR ((u32)0x00000002) +#define EBI_INT_ACCRES ((u32)0x00000004) +#define EBI_INT_ALL ((u32)0x00000007) + +#define IS_EBI_INT(INT) (((INT & 0xFFFFFFF8) == 0x0) && (INT != 0x0)) + +#define IS_EBI_INT_FLAG(FLAG) (((FLAG & 0xFFFFFFFC) == 0x0) && (FLAG != 0x0)) +#endif + + +#define IS_EBI_IDLE_CYCLE_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_ADDRESS_SETUP_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_ADDRESS_HOLD_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_WRITE_SETUP_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_WRITE_STROBE_TIME(TIME) (TIME < 0x40) + +#define IS_EBI_WRITE_HOLD_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_READ_SETUP_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_READ_STROBE_TIME(TIME) (TIME < 0x40) + +#define IS_EBI_READ_HOLD_TIME(TIME) (TIME < 0x10) + +#if !(LIBCFG_EBI_V01) +#define IS_EBI_PAGE_ACCESS_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_PAGE_OPEN_TIME(TIME) (TIME < 0x100) +#endif +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Functions EBI exported functions + * @{ + */ +void EBI_DeInit(void); +void EBI_Init(EBI_InitTypeDef* EBI_InitStruct); +void EBI_StructInit(EBI_InitTypeDef* EBI_InitStruct); +void EBI_Cmd(u32 EBI_Bank, ControlStatus NewState); +void EBI_IntConfig(u32 EBI_Int, ControlStatus NewState); +FlagStatus EBI_GetIntStatus(u32 EBI_Int); +void EBI_ClearIntFlag(u32 EBI_Int); +FlagStatus EBI_GetBusyStatus(void); +FlagStatus EBI_GetARDYStatus(void); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_exti.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_exti.h new file mode 100644 index 00000000000..ad34ac56bc0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_exti.h @@ -0,0 +1,208 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_exti.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the EXTI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_EXTI_H +#define __HT32F1XXXX_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macro EXTI exported macros + * @{ + */ +/*********************************************************************************************************//** + * @brief Convert the pin number of GPIO to the channel of EXTI. + * @param n: can be 0, 1 to 15 to select the pin number of GPIO. + ************************************************************************************************************/ +#define GPIO2EXTI(n) (n) +#define EXTI_GetIRQn(ch) gEXTIn_IRQn[ch] +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Types EXTI exported types + * @{ + */ + +/* Definitions of EXTI interrupt line */ +typedef enum +{ + EXTI_CHANNEL_0 = 0, + EXTI_CHANNEL_1, + EXTI_CHANNEL_2, + EXTI_CHANNEL_3, + EXTI_CHANNEL_4, + EXTI_CHANNEL_5, + EXTI_CHANNEL_6, + EXTI_CHANNEL_7, + EXTI_CHANNEL_8, + EXTI_CHANNEL_9, + EXTI_CHANNEL_10, + EXTI_CHANNEL_11, + EXTI_CHANNEL_12, + EXTI_CHANNEL_13, + EXTI_CHANNEL_14, + EXTI_CHANNEL_15, +} EXTI_Channel_TypeDef; + +#define IS_EXTI_CHANNEL(CHANNEL) ((CHANNEL == EXTI_CHANNEL_0) || \ + (CHANNEL == EXTI_CHANNEL_1) || \ + (CHANNEL == EXTI_CHANNEL_2) || \ + (CHANNEL == EXTI_CHANNEL_3) || \ + (CHANNEL == EXTI_CHANNEL_4) || \ + (CHANNEL == EXTI_CHANNEL_5) || \ + (CHANNEL == EXTI_CHANNEL_6) || \ + (CHANNEL == EXTI_CHANNEL_7) || \ + (CHANNEL == EXTI_CHANNEL_8) || \ + (CHANNEL == EXTI_CHANNEL_9) || \ + (CHANNEL == EXTI_CHANNEL_10) || \ + (CHANNEL == EXTI_CHANNEL_11) || \ + (CHANNEL == EXTI_CHANNEL_12) || \ + (CHANNEL == EXTI_CHANNEL_13) || \ + (CHANNEL == EXTI_CHANNEL_14) || \ + (CHANNEL == EXTI_CHANNEL_15)) + +/* Definitions of EXTI init structure */ +typedef enum +{ + EXTI_LOW_LEVEL = 0x0, + EXTI_HIGH_LEVEL = 0x1, + EXTI_NEGATIVE_EDGE = 0x2, + EXTI_POSITIVE_EDGE = 0x3, + EXTI_BOTH_EDGE = 0x4 +} EXTI_Interrupt_TypeDef; + +#define IS_EXTI_INT_TYPE(TYPE) ((TYPE == EXTI_LOW_LEVEL) || \ + (TYPE == EXTI_HIGH_LEVEL) || \ + (TYPE == EXTI_NEGATIVE_EDGE) || \ + (TYPE == EXTI_POSITIVE_EDGE) || \ + (TYPE == EXTI_BOTH_EDGE)) + +typedef enum +{ + EXTI_DEBOUNCE_DISABLE = 0x0, + EXTI_DEBOUNCE_ENABLE = 0x1 +} EXTI_Deb_TypeDef; + +#define IS_EXTI_DEBOUNCE_TYPE(TYPE) ((TYPE == EXTI_DEBOUNCE_DISABLE) || \ + (TYPE == EXTI_DEBOUNCE_ENABLE)) + +typedef struct +{ + u32 EXTI_Channel; + EXTI_Deb_TypeDef EXTI_Debounce; + #if (LIBCFG_EXTI_8BIT_DEBOUNCE_COUNTER) + u8 EXTI_DebounceCnt; + #else + u16 EXTI_DebounceCnt; + #endif + EXTI_Interrupt_TypeDef EXTI_IntType; +} EXTI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI exported constants + * @{ + */ + +/* Definitions of EXTI wake up polarity */ +#define EXTI_WAKEUP_HIGH_LEVEL ((u8)0x0) +#define EXTI_WAKEUP_LOW_LEVEL ((u8)0x1) + +#define IS_EXTI_WAKEUP_TYPE(TYPE) ((TYPE == EXTI_WAKEUP_HIGH_LEVEL) || \ + (TYPE == EXTI_WAKEUP_LOW_LEVEL)) + + +#define EXTI_EDGE_POSITIVE ((u8)0x0) +#define EXTI_EDGE_NEGATIVE ((u8)0x1) + +#define IS_EXTI_EDGE(EDGE) ((EDGE == EXTI_EDGE_POSITIVE) || \ + (EDGE == EXTI_EDGE_NEGATIVE)) + +#if (LIBCFG_EXTI_8BIT_DEBOUNCE_COUNTER) +#define IS_EXTI_DEBOUNCE_SIZE(SIZE) (SIZE <= 0xFF) +#else +#define IS_EXTI_DEBOUNCE_SIZE(SIZE) (SIZE <= 0xFFFF) +#endif + +extern const IRQn_Type gEXTIn_IRQn[16]; + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI exported functions + * @{ + */ +void EXTI_DeInit(u32 EXTI_Channel); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_IntConfig(u32 EXTI_Channel, ControlStatus NewState); +void EXTI_WakeupEventConfig(u32 EXTI_Channel, u8 EXTI_WakeUpType, ControlStatus NewState); +void EXTI_WakeupEventIntConfig(ControlStatus NewState); +void EXTI_ClearEdgeFlag(u32 EXTI_Channel); +void EXTI_ClearWakeupFlag(u32 EXTI_Channel); +FlagStatus EXTI_GetEdgeFlag(u32 EXTI_Channel); +FlagStatus EXTI_GetEdgeStatus(u32 EXTI_Channel, u32 EXTI_Edge); +FlagStatus EXTI_GetWakeupFlagStatus(u32 EXTI_Channel); +void EXTI_SWIntCmd(u32 EXTI_Channel, ControlStatus NewState); +FlagStatus EXTI_GetSWCmdStatus(u32 EXTI_Channel); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_flash.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_flash.h new file mode 100644 index 00000000000..cb194268c00 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_flash.h @@ -0,0 +1,191 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_flash.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the FLASH library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_FLASH_H +#define __HT32F1XXXX_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH exported types + * @{ + */ + +/** + * @brief Enumeration of FLASH return status. + */ +typedef enum +{ + FLASH_COMPLETE = 0, + FLASH_ERR_ADDR_OUT_OF_RANGE, + FLASH_ERR_WRITE_PROTECTED, + FLASH_TIME_OUT +} FLASH_State; + +/** + * @brief Enumeration of FLASH boot mode. + */ +typedef enum +{ + FLASH_BOOT_SRAM = 0, + FLASH_BOOT_LOADER = 1, + FLASH_BOOT_MAIN = 2 +} FLASH_Vector; + +typedef struct +{ + u32 WriteProtect[4]; + u32 MainSecurity; + u32 OptionProtect; +} FLASH_OptionByte; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH exported constants + * @{ + */ + +/* Flash Information */ +#define FLASH_PAGE_SIZE (LIBCFG_FLASH_PAGESIZE) /* Flash page size */ + +/* Flash Wait State */ +#define FLASH_WAITSTATE_0 (0x00000001) /* FLASH zero wait state */ +#define FLASH_WAITSTATE_1 (0x00000002) /* FLASH one wait state */ +#define FLASH_WAITSTATE_2 (0x00000003) /* FLASH two wait state */ +#if (LIBCFG_FMC_WAIT_STATE_3) +#define FLASH_WAITSTATE_3 (0x00000004) /* FLASH three wait state */ +#endif + +#if (LIBCFG_FMC_WAIT_STATE_3) +#define FLASH_WAITSTATE_MAX (FLASH_WAITSTATE_3) +#else +#define FLASH_WAITSTATE_MAX (FLASH_WAITSTATE_2) +#endif + +/* FLASH OISR Flags */ +#define FLASH_FLAG_ORFF (0x00000001) /* Operation Finished Flag */ +#define FLASH_FLAG_ITADF (0x00000002) /* Invalid Target Address Flag */ +#define FLASH_FLAG_OBEF (0x00000004) /* Option Byte Check Sum Error Flag */ +#define FLASH_FLAG_IOCMF (0x00000008) /* Invalid Operation Command Flag */ +#define FLASH_FLAG_OREF (0x00000010) /* Operation Error Flag */ +#define FLASH_FLAG_RORFF (0x00010000) /* Raw Operation Finished Flag */ +#define FLASH_FLAG_PPEF (0x00020000) /* Page Erase/Program Protected Error Flag */ + +/* FLASH OIER */ +#define FLASH_INT_ORFIEN (0x00000001) /* Flash Operation Finished Interrupt Enable */ +#define FLASH_INT_ITADIEN (0x00000002) /* Invalid Target Address Interrupt Enable */ +#define FLASH_INT_OBEIEN (0x00000004) /* Option Byte Checksum Error Interrupt Enable */ +#define FLASH_INT_IOCMIEN (0x00000008) /* Invalid Operation Command Interrupt Enable */ +#define FLASH_INT_OREIEN (0x00000010) /* Operation Error Interrupt Enable */ +#define FLASH_INT_ALL (0x0000001F) /* Flash all Interrupt Enable */ + +/* Option Bytes Address */ +#define OPTION_BYTE_BASE (0x1FF00000) /* Option Byte Base Address */ +#define OB_PP0 (0x1FF00000) /* Option Byte: Write Protection 0 */ +#define OB_PP1 (0x1FF00004) /* Option Byte: Write Protection 1 */ +#define OB_PP2 (0x1FF00008) /* Option Byte: Write Protection 2 */ +#define OB_PP3 (0x1FF0000C) /* Option Byte: Write Protection 3 */ +#define OB_CP (0x1FF00010) /* Option Byte: Security Protection */ +#define OB_CHECKSUM (0x1FF00020) /* Option Byte: Checksum */ + +/* Flash Write Protection Page Mask */ +#if (LIBCFG_FLASH_2PAGE_PER_WPBIT) + #define FLASH_WP_PAGE_SET(OP, PAGE) (OP.WriteProtect[PAGE / 64] |= 1 << ((PAGE % 64) / 2)) + #define FLASH_WP_PAGE_CLEAR(OP, PAGE) (OP.WriteProtect[PAGE / 64] &= ~(1 << ((PAGE % 64) / 2))) + #define FLASH_IS_WP_PAGE(OP, PAGE) (OP.WriteProtect[PAGE / 64] & (1 << ((PAGE % 64) / 2))) +#else + #define FLASH_WP_PAGE_SET(OP, PAGE) (OP.WriteProtect[PAGE / 32] |= 1 << (PAGE % 32)) + #define FLASH_WP_PAGE_CLEAR(OP, PAGE) (OP.WriteProtect[PAGE / 32] &= ~(1 << (PAGE % 32))) + #define FLASH_IS_WP_PAGE(OP, PAGE) (OP.WriteProtect[PAGE / 32] & (1 << (PAGE % 32))) +#endif +#define FLASH_WP_ALLPAGE_SET(OP) {u32 i; for (i = 0; i < 4; i++) { OP.WriteProtect[i] = 0xFFFFFFFF; } } + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH exported functions + * @{ + */ +void FLASH_SetWaitState(u32 FLASH_WAITSTATE_n); +void FLASH_PrefetchBufferCmd(ControlStatus NewState); +void FLASH_DcodeCacheCmd(ControlStatus NewState); +void FLASH_BranchCacheCmd(ControlStatus NewState); +#if (LIBCFG_FLASH_HALFCYCYLE) +ErrStatus FLASH_FlashHalfCycleCmd(ControlStatus NewState); +#endif +#if (LIBCFG_FLASH_ZWPWESAVING) +ErrStatus FLASH_FlashZwPwrSavingCmd(ControlStatus NewState); +#endif +void FLASH_SetRemappingMode(FLASH_Vector RemapMode); +FLASH_State FLASH_ErasePage(u32 PageAddress); +FLASH_State FLASH_EraseOptionByte(void); +FLASH_State FLASH_MassErase(void); +FLASH_State FLASH_ProgramWordData(u32 Address, u32 Data); +FLASH_State FLASH_ProgramOptionByte(FLASH_OptionByte *Option); +void FLASH_GetOptionByteStatus(FLASH_OptionByte *Option); +void FLASH_IntConfig(u32 FLASH_INT, ControlStatus Cmd); +FlagStatus FLASH_GetIntStatus(u32 FLASH_FLAG_x); +void FLASH_ClearIntFlag(u32 FLASH_FLAG_x); +FLASH_State FLASH_WaitForOperationEnd(void); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_gpio.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_gpio.h new file mode 100644 index 00000000000..30e360baf52 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_gpio.h @@ -0,0 +1,426 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_gpio.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the GPIO and AFIO library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_GPIO_H +#define __HT32F1XXXX_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Settings GPIO settings + * @{ + */ +#ifndef AUTO_CK_CONTROL +#define AUTO_CK_CONTROL (0) +#endif +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO exported types + * @{ + */ + +/** + * @brief Enumeration of GPIO pull resistor. + */ +typedef enum +{ + GPIO_PR_UP = 0, /*!< weak pull-up resistor */ + GPIO_PR_DOWN, /*!< weak pull-down resistor */ + GPIO_PR_DISABLE /*!< Tri-state */ +} GPIO_PR_Enum; +/** + * @brief Enumeration of GPIO output drive current. + */ +typedef enum +{ + GPIO_DV_4MA = 0, /*!< 4mA source/sink current */ + GPIO_DV_8MA, /*!< 8mA source/sink current */ + #if (LIBCFG_GPIO_DV_4_8MA_ONLY) + #else + GPIO_DV_12MA, /*!< 12mA source/sink current */ + GPIO_DV_16MA /*!< 16mA source/sink current */ + #endif +} GPIO_DV_Enum; +/** + * @brief Enumeration of GPIO direction. + */ +typedef enum +{ + GPIO_DIR_IN = 0, /*!< input mode */ + GPIO_DIR_OUT /*!< output mode */ +} GPIO_DIR_Enum; +/** + * @brief Enumeration of GPIO port source for EXTI channel. + */ +typedef enum +{ + AFIO_ESS_PA = 0, /*!< EXTI channel x source come from GPIO Port A */ + AFIO_ESS_PB = 1, /*!< EXTI channel x source come from GPIO Port B */ + AFIO_ESS_PC = 2, /*!< EXTI channel x source come from GPIO Port C */ + AFIO_ESS_PD = 3, /*!< EXTI channel x source come from GPIO Port D */ +#if (LIBCFG_GPIOE) + AFIO_ESS_PE = 4, /*!< EXTI channel x source come from GPIO Port E */ +#endif +#if (LIBCFG_GPIOF) + AFIO_ESS_PF = 5 /*!< EXTI channel x source come from GPIO Port F */ +#endif +} AFIO_ESS_Enum; +/** + * @brief Enumeration of AFIO for EXTI channel. + */ +typedef enum +{ + AFIO_EXTI_CH_0 = 0, /*!< GPIO pin 0 */ + AFIO_EXTI_CH_1, /*!< GPIO pin 1 */ + AFIO_EXTI_CH_2, /*!< GPIO pin 2 */ + AFIO_EXTI_CH_3, /*!< GPIO pin 3 */ + AFIO_EXTI_CH_4, /*!< GPIO pin 4 */ + AFIO_EXTI_CH_5, /*!< GPIO pin 5 */ + AFIO_EXTI_CH_6, /*!< GPIO pin 6 */ + AFIO_EXTI_CH_7, /*!< GPIO pin 7 */ + AFIO_EXTI_CH_8, /*!< GPIO pin 8 */ + AFIO_EXTI_CH_9, /*!< GPIO pin 9 */ + AFIO_EXTI_CH_10, /*!< GPIO pin 10 */ + AFIO_EXTI_CH_11, /*!< GPIO pin 11 */ + AFIO_EXTI_CH_12, /*!< GPIO pin 12 */ + AFIO_EXTI_CH_13, /*!< GPIO pin 13 */ + AFIO_EXTI_CH_14, /*!< GPIO pin 14 */ + AFIO_EXTI_CH_15 /*!< GPIO pin 15 */ +} AFIO_EXTI_CH_Enum; +/** + * @brief Enumeration of AFIO_MODE. + */ +typedef enum +{ + AFIO_MODE_DEFAULT = 0, /*!< Default AFIO mode */ + AFIO_MODE_1, /*!< AFIO mode 1 */ + AFIO_MODE_2, /*!< AFIO mode 2 */ + AFIO_MODE_3, /*!< AFIO mode 3 */ + AFIO_MODE_4, /*!< AFIO mode 4 */ + AFIO_MODE_5, /*!< AFIO mode 5 */ + AFIO_MODE_6, /*!< AFIO mode 6 */ + AFIO_MODE_7, /*!< AFIO mode 7 */ + AFIO_MODE_8, /*!< AFIO mode 8 */ + AFIO_MODE_9, /*!< AFIO mode 9 */ + AFIO_MODE_10, /*!< AFIO mode 10 */ + AFIO_MODE_11, /*!< AFIO mode 11 */ + AFIO_MODE_12, /*!< AFIO mode 12 */ + AFIO_MODE_13, /*!< AFIO mode 13 */ + AFIO_MODE_14, /*!< AFIO mode 14 */ + AFIO_MODE_15 /*!< AFIO mode 15 */ +} AFIO_MODE_Enum; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO exported constants + * @{ + */ + +/* Definitions of AFIO_FUN */ +#define AFIO_FUN_DEFAULT AFIO_MODE_DEFAULT /*!< Default AFIO mode */ +#define AFIO_FUN_GPIO AFIO_MODE_1 /*!< AFIO mode GPIO */ +#define AFIO_FUN_ADC0 AFIO_MODE_2 /*!< AFIO mode ADC0 */ +#define AFIO_FUN_CMP AFIO_MODE_3 /*!< AFIO mode CMP */ +#define AFIO_FUN_MCTM_GPTM AFIO_MODE_4 /*!< AFIO mode MCTM/GPTM */ +#define AFIO_FUN_SPI AFIO_MODE_5 /*!< AFIO mode SPI */ +#define AFIO_FUN_USART_UART AFIO_MODE_6 /*!< AFIO mode USART/UART */ +#define AFIO_FUN_I2C AFIO_MODE_7 /*!< AFIO mode I2C */ +#define AFIO_FUN_SCI AFIO_MODE_8 /*!< AFIO mode SCI */ +#define AFIO_FUN_EBI AFIO_MODE_9 /*!< AFIO mode EBI */ +#define AFIO_FUN_I2S AFIO_MODE_10 /*!< AFIO mode I2S */ +#define AFIO_FUN_SDIO AFIO_MODE_11 /*!< AFIO mode SDIO */ +#define AFIO_FUN_CSIF AFIO_MODE_12 /*!< AFIO mode CSIF */ +#define AFIO_FUN_SCTM AFIO_MODE_13 /*!< AFIO mode SCTM */ +#define AFIO_FUN_PWM AFIO_MODE_13 /*!< AFIO mode PWM */ +#define AFIO_FUN_SYSTEM AFIO_MODE_15 /*!< AFIO mode System */ + +/* Definitions of AFIO_FUN alias */ +#define AFIO_FUN_MCTM0 AFIO_FUN_MCTM_GPTM +#define AFIO_FUN_MCTM1 AFIO_FUN_MCTM_GPTM + +#define AFIO_FUN_GPTM0 AFIO_FUN_MCTM_GPTM +#define AFIO_FUN_GPTM1 AFIO_FUN_MCTM_GPTM +#define AFIO_FUN_GPTM2 AFIO_FUN_MCTM_GPTM +#define AFIO_FUN_GPTM3 AFIO_FUN_MCTM_GPTM + +#define AFIO_FUN_PWM0 AFIO_FUN_PWM +#define AFIO_FUN_PWM1 AFIO_FUN_PWM +#define AFIO_FUN_PWM2 AFIO_FUN_PWM +#define AFIO_FUN_PWM3 AFIO_FUN_PWM + +#define AFIO_FUN_SCTM0 AFIO_FUN_SCTM +#define AFIO_FUN_SCTM1 AFIO_FUN_SCTM + +#define AFIO_FUN_ADC AFIO_FUN_ADC0 +#define AFIO_FUN_PWM_SCTM AFIO_MODE_13 + +/* Definitions of GPIO_Px */ +#define GPIO_PORT_NUM (6) +#define GPIO_PIN_NUM (16) +#define GPIO_PA (0) +#define GPIO_PB (1) +#define GPIO_PC (2) +#define GPIO_PD (3) +#if (LIBCFG_GPIOE) +#define GPIO_PE (4) +#endif +#if (LIBCFG_GPIOF) +#define GPIO_PF (5) +#endif + +/* Definitions of GPIO port source for EXTI channel */ +#define AFIO_ESS_PA GPIO_PA /*!< EXTI channel x source come from GPIO Port A */ +#define AFIO_ESS_PB GPIO_PB /*!< EXTI channel x source come from GPIO Port B */ +#define AFIO_ESS_PC GPIO_PC /*!< EXTI channel x source come from GPIO Port C */ +#define AFIO_ESS_PD GPIO_PD /*!< EXTI channel x source come from GPIO Port D */ +#if (LIBCFG_GPIOE) +#define AFIO_ESS_PE GPIO_PE /*!< EXTI channel x source come from GPIO Port E */ +#endif +#if (LIBCFG_GPIOF) +#define AFIO_ESS_PF GPIO_PF /*!< EXTI channel x source come from GPIO Port F */ +#endif + +/* Definitions of GPIO_PIN */ +#define GPIO_PIN_0 0x0001 /*!< GPIO pin 0 selected */ +#define GPIO_PIN_1 0x0002 /*!< GPIO pin 1 selected */ +#define GPIO_PIN_2 0x0004 /*!< GPIO pin 2 selected */ +#define GPIO_PIN_3 0x0008 /*!< GPIO pin 3 selected */ +#define GPIO_PIN_4 0x0010 /*!< GPIO pin 4 selected */ +#define GPIO_PIN_5 0x0020 /*!< GPIO pin 5 selected */ +#define GPIO_PIN_6 0x0040 /*!< GPIO pin 6 selected */ +#define GPIO_PIN_7 0x0080 /*!< GPIO pin 7 selected */ +#define GPIO_PIN_8 0x0100 /*!< GPIO pin 8 selected */ +#define GPIO_PIN_9 0x0200 /*!< GPIO pin 9 selected */ +#define GPIO_PIN_10 0x0400 /*!< GPIO pin 10 selected */ +#define GPIO_PIN_11 0x0800 /*!< GPIO pin 11 selected */ +#define GPIO_PIN_12 0x1000 /*!< GPIO pin 12 selected */ +#define GPIO_PIN_13 0x2000 /*!< GPIO pin 13 selected */ +#define GPIO_PIN_14 0x4000 /*!< GPIO pin 14 selected */ +#define GPIO_PIN_15 0x8000 /*!< GPIO pin 15 selected */ +#define GPIO_PIN_ALL 0xFFFF /*!< GPIO all pins selected */ + +/* Definitions of AFIO_PIN */ +#define AFIO_PIN_0 0x0001 /*!< AFIO pin 0 selected */ +#define AFIO_PIN_1 0x0002 /*!< AFIO pin 1 selected */ +#define AFIO_PIN_2 0x0004 /*!< AFIO pin 2 selected */ +#define AFIO_PIN_3 0x0008 /*!< AFIO pin 3 selected */ +#define AFIO_PIN_4 0x0010 /*!< AFIO pin 4 selected */ +#define AFIO_PIN_5 0x0020 /*!< AFIO pin 5 selected */ +#define AFIO_PIN_6 0x0040 /*!< AFIO pin 6 selected */ +#define AFIO_PIN_7 0x0080 /*!< AFIO pin 7 selected */ +#define AFIO_PIN_8 0x0100 /*!< AFIO pin 8 selected */ +#define AFIO_PIN_9 0x0200 /*!< AFIO pin 9 selected */ +#define AFIO_PIN_10 0x0400 /*!< AFIO pin 10 selected */ +#define AFIO_PIN_11 0x0800 /*!< AFIO pin 11 selected */ +#define AFIO_PIN_12 0x1000 /*!< AFIO pin 12 selected */ +#define AFIO_PIN_13 0x2000 /*!< AFIO pin 13 selected */ +#define AFIO_PIN_14 0x4000 /*!< AFIO pin 14 selected */ +#define AFIO_PIN_15 0x8000 /*!< AFIO pin 15 selected */ +#define AFIO_PIN_ALL 0xFFFF /*!< All AFIO pins selected */ + +/* Definitions of GPIO_PIN_NUM */ +#define GPIO_PIN_NUM_0 0x00 /*!< GPIO pin number 0 selected */ +#define GPIO_PIN_NUM_1 0x01 /*!< GPIO pin number 1 selected */ +#define GPIO_PIN_NUM_2 0x02 /*!< GPIO pin number 2 selected */ +#define GPIO_PIN_NUM_3 0x03 /*!< GPIO pin number 3 selected */ +#define GPIO_PIN_NUM_4 0x04 /*!< GPIO pin number 4 selected */ +#define GPIO_PIN_NUM_5 0x05 /*!< GPIO pin number 5 selected */ +#define GPIO_PIN_NUM_6 0x06 /*!< GPIO pin number 6 selected */ +#define GPIO_PIN_NUM_7 0x07 /*!< GPIO pin number 7 selected */ +#define GPIO_PIN_NUM_8 0x08 /*!< GPIO pin number 8 selected */ +#define GPIO_PIN_NUM_9 0x09 /*!< GPIO pin number 9 selected */ +#define GPIO_PIN_NUM_10 0x0A /*!< GPIO pin number 10 selected */ +#define GPIO_PIN_NUM_11 0x0B /*!< GPIO pin number 11 selected */ +#define GPIO_PIN_NUM_12 0x0C /*!< GPIO pin number 12 selected */ +#define GPIO_PIN_NUM_13 0x0D /*!< GPIO pin number 13 selected */ +#define GPIO_PIN_NUM_14 0x0E /*!< GPIO pin number 14 selected */ +#define GPIO_PIN_NUM_15 0x0F /*!< GPIO pin number 15 selected */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macro GPIO exported macro + * @{ + */ +/* check parameter of the GPIOx */ +#define IS_GPIO(x) (IS_GPIOABCD(x) || IS_GPIOE(x) || IS_GPIOF(x)) +#define IS_GPIOABCD(x) ((x==HT_GPIOA) || (x==HT_GPIOB) || (x==HT_GPIOC) || (x==HT_GPIOD)) +#if (LIBCFG_GPIOE) +#define IS_GPIOE(x) (x == HT_GPIOE) +#else +#define IS_GPIOE(x) (0) +#endif +#if (LIBCFG_GPIOF) +#define IS_GPIOF(x) (x == HT_GPIOF) +#else +#define IS_GPIOF(x) (0) +#endif + +/* check parameter of the GPIO_Px */ +#define IS_GPIO_PORT(x) (IS_GPIO_PORT1(x) || IS_GPIO_PORT2(x) || IS_GPIO_PORT3(x) || IS_GPIO_PORT4(x) || IS_GPIO_PORT5(x)) + +#define IS_GPIO_PORT1(x) ((x == GPIO_PA) || (x == GPIO_PB) ) + +#define IS_GPIO_PORT2(x) (x == GPIO_PC) + +#define IS_GPIO_PORT3(x) (x == GPIO_PD) + +#if (LIBCFG_GPIOE) +#define IS_GPIO_PORT4(x) (x == GPIO_PE) +#else +#define IS_GPIO_PORT4(x) (0) +#endif +#if (LIBCFG_GPIOF) +#define IS_GPIO_PORT5(x) (x == GPIO_PF) +#else +#define IS_GPIO_PORT5(x) (0) +#endif + +/* check parameter of the GPIO_PIN_NUM */ +#define IS_GPIO_PIN_NUM(x) (x < 16) + +/* check parameter of the GPIOx pull resistor */ +#define IS_GPIO_PR(x) (((x) == GPIO_PR_UP) || ((x) == GPIO_PR_DOWN) || ((x) == GPIO_PR_DISABLE)) + +/* check parameter of the GPIOx driving current */ +#if (LIBCFG_GPIO_DV_4_8MA_ONLY) +#define IS_GPIO_DV_12_16MA(x) (0) +#else +#define IS_GPIO_DV_12_16MA(x) (((x) == GPIO_DV_12MA) || ((x) == GPIO_DV_16MA)) +#endif +#define IS_GPIO_DV(x) (((x) == GPIO_DV_4MA) || ((x) == GPIO_DV_8MA) || IS_GPIO_DV_12_16MA(x)) + +/* check parameter of the GPIOx input/output direction */ +#define IS_GPIO_DIR(x) (((x) == GPIO_DIR_IN) || ((x) == GPIO_DIR_OUT) ) + +/* check parameter of the EXTI source port */ +#if (LIBCFG_GPIOE) +#define IS_ESSE(x) (x == AFIO_ESS_PE) +#else +#define IS_ESSE(x) (0) +#endif +#if (LIBCFG_GPIOF) +#define IS_ESSF(x) (x == AFIO_ESS_PF) +#else +#define IS_ESSF(x) (0) +#endif + +#define IS_AFIO_ESS(x) ((x == AFIO_ESS_PA) || (x == AFIO_ESS_PB) || (x == AFIO_ESS_PC) || (x == AFIO_ESS_PD) || IS_ESSE(x) || IS_ESSF(x)) + +/* check parameter of the EXTI channel */ +#define IS_AFIO_EXTI_CH(x) ((x == AFIO_EXTI_CH_0) || (x == AFIO_EXTI_CH_1) || \ + (x == AFIO_EXTI_CH_2) || (x == AFIO_EXTI_CH_3) || \ + (x == AFIO_EXTI_CH_4) || (x == AFIO_EXTI_CH_5) || \ + (x == AFIO_EXTI_CH_6) || (x == AFIO_EXTI_CH_7) || \ + (x == AFIO_EXTI_CH_8) || (x == AFIO_EXTI_CH_9) || \ + (x == AFIO_EXTI_CH_10) || (x == AFIO_EXTI_CH_11) || \ + (x == AFIO_EXTI_CH_12) || (x == AFIO_EXTI_CH_13) || \ + (x == AFIO_EXTI_CH_14) || (x == AFIO_EXTI_CH_15)) + +/* check parameter of the AFIO mode */ +#define IS_AFIO_MODE(x) ((x == AFIO_MODE_DEFAULT) || (x == AFIO_MODE_1) || \ + (x == AFIO_MODE_2) || (x == AFIO_MODE_3) || \ + (x == AFIO_MODE_4) || (x == AFIO_MODE_5) || \ + (x == AFIO_MODE_6) || (x == AFIO_MODE_7) || \ + (x == AFIO_MODE_8) || (x == AFIO_MODE_9) || \ + (x == AFIO_MODE_10) || (x == AFIO_MODE_11) || \ + (x == AFIO_MODE_12) || (x == AFIO_MODE_13) || \ + (x == AFIO_MODE_14) || (x == AFIO_MODE_15)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO exported functions + * @{ + */ + +/* Prototype of related GPIO function */ +void GPIO_DeInit(HT_GPIO_TypeDef* HT_GPIOx); +void GPIO_DirectionConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DIR_Enum GPIO_DIR_INorOUT); +void GPIO_PullResistorConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_PR_Enum GPIO_PR_x); +void GPIO_InputConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd); +void GPIO_DriveConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DV_Enum GPIO_DV_nMA); +void GPIO_OpenDrainConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd); +FlagStatus GPIO_ReadInBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n); +FlagStatus GPIO_ReadOutBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n); +u16 GPIO_ReadInData(HT_GPIO_TypeDef* HT_GPIOx); +u16 GPIO_ReadOutData(HT_GPIO_TypeDef* HT_GPIOx); +void GPIO_SetOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP); +void GPIO_ClearOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP); +void GPIO_WriteOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, FlagStatus Status); +void GPIO_WriteOutData(HT_GPIO_TypeDef* HT_GPIOx, u16 Data); +void GPIO_PinLock(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP); +bool GPIO_IsPortLocked(HT_GPIO_TypeDef* HT_GPIOx); +bool GPIO_IsPinLocked(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n); +void GPIO_DisableDebugPort(void); +u32 GPIO_GetID(HT_GPIO_TypeDef* HT_GPIOx); + +/* Prototype of related AFIO function */ +void AFIO_DeInit(void); +void AFIO_GPxConfig(u32 GPIO_Px, u32 AFIO_PIN_n, AFIO_MODE_Enum AFIO_MODE_n); +void AFIO_EXTISourceConfig(u32 GPIO_PIN_NUM_n, u32 GPIO_Px); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_i2c.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_i2c.h new file mode 100644 index 00000000000..7d1c3144900 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_i2c.h @@ -0,0 +1,325 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_i2c.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the I2C library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_I2C_H +#define __HT32F1XXXX_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C exported types + * @{ + */ + +typedef u16 I2C_AddressTypeDef; + +typedef struct +{ + u8 I2C_GeneralCall; + u8 I2C_AddressingMode; + u8 I2C_Acknowledge; + u8 I2C_SpeedOffset; /* Offset value to reach real speed, recommended I2C_SpeedOffset = I2C PCLK/8000000 */ + /* which based on 4.7K Pull up */ + u32 I2C_Speed; + u16 I2C_OwnAddress; +} I2C_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Constants I2C exported constants + * @{ + */ +#define I2C_GENERALCALL_ENABLE ((u32)0x00000004) +#define I2C_GENERALCALL_DISABLE ((u32)0x00000000) + +#define IS_I2C_GENERAL_CALL(CALL) ((CALL == I2C_GENERALCALL_ENABLE) || \ + (CALL == I2C_GENERALCALL_DISABLE)) + +#define I2C_ADDRESSING_7BIT ((u32)0x00000000) +#define I2C_ADDRESSING_10BIT ((u32)0x00000080) + +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) ((ADDRESS == I2C_ADDRESSING_7BIT) || \ + (ADDRESS == I2C_ADDRESSING_10BIT)) + +#define I2C_ACK_ENABLE ((u32)0x00000001) +#define I2C_ACK_DISABLE ((u32)0x00000000) + +#define IS_I2C_ACKNOWLEDGE(ACKNOWLEDGE) ((ACKNOWLEDGE == I2C_ACK_ENABLE) || \ + (ACKNOWLEDGE == I2C_ACK_DISABLE)) + + +#define I2C_INT_STA ((u32)0x00000001) +#define I2C_INT_STO ((u32)0x00000002) +#define I2C_INT_ADRS ((u32)0x00000004) +#define I2C_INT_GCS ((u32)0x00000008) +#define I2C_INT_ARBLOS ((u32)0x00000100) +#define I2C_INT_RXNACK ((u32)0x00000200) +#define I2C_INT_BUSERR ((u32)0x00000400) +#define I2C_INT_TOUT ((u32)0x00000800) +#define I2C_INT_RXDNE ((u32)0x00010000) +#define I2C_INT_TXDE ((u32)0x00020000) +#define I2C_INT_RXBF ((u32)0x00040000) +#define I2C_INT_ALL ((u32)0x00070F0F) + +#define IS_I2C_INT(int) (((int & 0xFFF8F0F0) == 0x0) && (int != 0x0)) + +#define I2C_MASTER_READ ((u32)0x00000400) +#define I2C_MASTER_WRITE ((u32)0x00000000) + +#define IS_I2C_DIRECTION(DIRECTION) ((DIRECTION == I2C_MASTER_READ) || \ + (DIRECTION == I2C_MASTER_WRITE)) + + +#define I2C_REGISTER_CR ((u8)0x00) +#define I2C_REGISTER_IER ((u8)0x04) +#define I2C_REGISTER_ADDR ((u8)0x08) +#define I2C_REGISTER_SR ((u8)0x0C) +#define I2C_REGISTER_SHPGR ((u8)0x10) +#define I2C_REGISTER_SLPGR ((u8)0x14) +#define I2C_REGISTER_DR ((u8)0x18) +#define I2C_REGISTER_BFCLR ((u8)0x1C) +#define I2C_REGISTER_TAR ((u8)0x20) + +#define IS_I2C_REGISTER(REGISTER) ((REGISTER == I2C_REGISTER_CR) || \ + (REGISTER == I2C_REGISTER_IER) || \ + (REGISTER == I2C_REGISTER_ADDR) || \ + (REGISTER == I2C_REGISTER_SR) || \ + (REGISTER == I2C_REGISTER_SHPGR) || \ + (REGISTER == I2C_REGISTER_SLPGR) || \ + (REGISTER == I2C_REGISTER_DR) || \ + (REGISTER == I2C_REGISTER_BFCLR) || \ + (REGISTER == I2C_REGISTER_TAR)) + + +#define I2C_FLAG_STA ((u32)0x00000001) +#define I2C_FLAG_STO ((u32)0x00000002) +#define I2C_FLAG_ADRS ((u32)0x00000004) +#define I2C_FLAG_GCS ((u32)0x00000008) +#define I2C_FLAG_ARBLOS ((u32)0x00000100) +#define I2C_FLAG_RXNACK ((u32)0x00000200) +#define I2C_FLAG_BUSERR ((u32)0x00000400) +#define I2C_FLAG_TOUTF ((u32)0x00000800) +#define I2C_FLAG_RXDNE ((u32)0x00010000) +#define I2C_FLAG_TXDE ((u32)0x00020000) +#define I2C_FLAG_RXBF ((u32)0x00040000) +#define I2C_FLAG_BUSBUSY ((u32)0x00080000) +#define I2C_FLAG_MASTER ((u32)0x00100000) +#define I2C_FLAG_TXNRX ((u32)0x00200000) + +#define IS_I2C_FLAG(FLAG) ((FLAG == I2C_FLAG_STA) || \ + (FLAG == I2C_FLAG_STO) || \ + (FLAG == I2C_FLAG_ADRS) || \ + (FLAG == I2C_FLAG_GCS) || \ + (FLAG == I2C_FLAG_ARBLOS) || \ + (FLAG == I2C_FLAG_RXNACK) || \ + (FLAG == I2C_FLAG_BUSERR) || \ + (FLAG == I2C_FLAG_TOUTF) || \ + (FLAG == I2C_FLAG_RXDNE) || \ + (FLAG == I2C_FLAG_TXDE) || \ + (FLAG == I2C_FLAG_RXBF) || \ + (FLAG == I2C_FLAG_BUSBUSY)|| \ + (FLAG == I2C_FLAG_MASTER) || \ + (FLAG == I2C_FLAG_TXNRX)) + +#define IS_I2C_CLEAR_FLAG(FLAG) ((FLAG == I2C_FLAG_ARBLOS) || \ + (FLAG == I2C_FLAG_RXNACK) || \ + (FLAG == I2C_FLAG_BUSERR) || \ + (FLAG == I2C_FLAG_TOUTF)) + +#define I2C_MASTER_SEND_START ((u32)0x00180001) +#define I2C_MASTER_RECEIVER_MODE ((u32)0x00180004) +#define I2C_MASTER_TRANSMITTER_MODE ((u32)0x003A0004) +#define I2C_MASTER_RX_NOT_EMPTY ((u32)0x00190000) +#define I2C_MASTER_RX_NOT_EMPTY_NOBUSY ((u32)0x00010000) +#define I2C_MASTER_TX_EMPTY ((u32)0x003A0000) +#define I2C_MASTER_RX_BUFFER_FULL ((u32)0x001D0000) +#define I2C_SLAVE_ACK_TRANSMITTER_ADDRESS ((u32)0x002A0004) +#define I2C_SLAVE_ACK_RECEIVER_ADDRESS ((u32)0x00080004) +#define I2C_SLAVE_ACK_GCALL_ADDRESS ((u32)0x00080008) +#define I2C_SLAVE_RX_NOT_EMPTY ((u32)0x00090000) +#define I2C_SLAVE_RX_NOT_EMPTY_STOP ((u32)0x00010002) +#define I2C_SLAVE_TX_EMPTY ((u32)0x002A0000) +#define I2C_SLAVE_RX_BUFFER_FULL ((u32)0x000D0000) +#define I2C_SLAVE_RECEIVED_NACK ((u32)0x00080200) +#define I2C_SLAVE_RECEIVED_NACK_STOP ((u32)0x00000202) +#define I2C_SLAVE_STOP_DETECTED ((u32)0x00000002) + + +#define IS_I2C_STATUS(STATUS) ((STATUS == I2C_MASTER_SEND_START) || \ + (STATUS == I2C_MASTER_RECEIVER_MODE) || \ + (STATUS == I2C_MASTER_TRANSMITTER_MODE) || \ + (STATUS == I2C_MASTER_RX_NOT_EMPTY) || \ + (STATUS == I2C_MASTER_RX_NOT_EMPTY_NOBUSY) || \ + (STATUS == I2C_MASTER_TX_EMPTY) || \ + (STATUS == I2C_MASTER_RX_BUFFER_FULL) || \ + (STATUS == I2C_SLAVE_ACK_TRANSMITTER_ADDRESS) || \ + (STATUS == I2C_SLAVE_ACK_RECEIVER_ADDRESS) || \ + (STATUS == I2C_SLAVE_ACK_GCALL_ADDRESS) || \ + (STATUS == I2C_SLAVE_RX_NOT_EMPTY) || \ + (STATUS == I2C_SLAVE_RX_NOT_EMPTY_STOP) || \ + (STATUS == I2C_SLAVE_TX_EMPTY) || \ + (STATUS == I2C_SLAVE_RX_BUFFER_FULL) || \ + (STATUS == I2C_SLAVE_RECEIVED_NACK) || \ + (STATUS == I2C_SLAVE_RECEIVED_NACK_STOP) || \ + (STATUS == I2C_SLAVE_STOP_DETECTED)) + +#define I2C_PDMAREQ_TX ((u32)0x00000100) +#define I2C_PDMAREQ_RX ((u32)0x00000200) + +#define IS_I2C_PDMA_REQ(REQ) (((REQ & 0xFFFFFCFF) == 0x0) && (REQ != 0x0)) + +#define I2C_PRESCALER_1 ((u32)0x00000000) +#define I2C_PRESCALER_2 ((u32)0x00010000) +#define I2C_PRESCALER_4 ((u32)0x00020000) +#define I2C_PRESCALER_8 ((u32)0x00030000) +#define I2C_PRESCALER_16 ((u32)0x00040000) +#define I2C_PRESCALER_32 ((u32)0x00050000) +#define I2C_PRESCALER_64 ((u32)0x00060000) +#define I2C_PRESCALER_128 ((u32)0x00070000) + +#define IS_I2C_PRESCALER(PRESCALER) ((PRESCALER == I2C_PRESCALER_1) || \ + (PRESCALER == I2C_PRESCALER_2) || \ + (PRESCALER == I2C_PRESCALER_4) || \ + (PRESCALER == I2C_PRESCALER_8) || \ + (PRESCALER == I2C_PRESCALER_16) || \ + (PRESCALER == I2C_PRESCALER_32) || \ + (PRESCALER == I2C_PRESCALER_64) || \ + (PRESCALER == I2C_PRESCALER_128)) + +#define I2C_MASKBIT_0 ((u32)0x00000001) +#define I2C_MASKBIT_1 ((u32)0x00000002) +#define I2C_MASKBIT_2 ((u32)0x00000004) +#define I2C_MASKBIT_3 ((u32)0x00000008) +#define I2C_MASKBIT_4 ((u32)0x00000010) +#define I2C_MASKBIT_5 ((u32)0x00000020) +#define I2C_MASKBIT_6 ((u32)0x00000040) +#define I2C_MASKBIT_7 ((u32)0x00000080) +#define I2C_MASKBIT_8 ((u32)0x00000100) +#define I2C_MASKBIT_9 ((u32)0x00000200) + + +#define IS_I2C_ADDRESS_MASK(MASK) ((MASK == I2C_MASKBIT_0) || \ + (MASK == I2C_MASKBIT_1) || \ + (MASK == I2C_MASKBIT_2) || \ + (MASK == I2C_MASKBIT_3) || \ + (MASK == I2C_MASKBIT_4) || \ + (MASK == I2C_MASKBIT_5) || \ + (MASK == I2C_MASKBIT_6) || \ + (MASK == I2C_MASKBIT_7) || \ + (MASK == I2C_MASKBIT_8) || \ + (MASK == I2C_MASKBIT_9)) + + +#define IS_I2C(I2C) ((I2C == HT_I2C0) || (I2C == HT_I2C1)) + +#define IS_I2C_ADDRESS(ADDRESS) (ADDRESS <= 0x3FF) + +#define IS_I2C_SPEED(SPEED) ((SPEED >= 1) && (SPEED <= 1000000)) + +#define IS_I2C_SCL_HIGH(HIGH) (HIGH <= 0xFFFF) + +#define IS_I2C_SCL_LOW(LOW) (LOW <= 0xFFFF) + +#define IS_I2C_TIMEOUT(TIMEOUT) (TIMEOUT <= 0xFFFF) + +#define SEQ_FILTER_DISABLE ((u32)0x00000000) +#define SEQ_FILTER_1_PCLK ((u32)0x00004000) +#define SEQ_FILTER_2_PCLK ((u32)0x00008000) + +#define IS_I2C_SEQ_FILTER_MASK(CONFIG) ((CONFIG == SEQ_FILTER_DISABLE) || \ + (CONFIG == SEQ_FILTER_1_PCLK) || \ + (CONFIG == SEQ_FILTER_2_PCLK)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Functions I2C exported functions + * @{ + */ +void I2C_DeInit(HT_I2C_TypeDef* I2Cx); +void I2C_Init(HT_I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStructure); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStructure); +void I2C_Cmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_GenerateSTOP(HT_I2C_TypeDef* I2Cx); +void I2C_IntConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Int, ControlStatus NewState); +void I2C_GeneralCallCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_AckCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_SetOwnAddress(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address); +void I2C_TargetAddressConfig(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address, u32 I2C_Direction); +void I2C_SendData(HT_I2C_TypeDef* I2Cx, u8 I2C_Data); +u8 I2C_ReceiveData(HT_I2C_TypeDef* I2Cx); +u32 I2C_ReadRegister(HT_I2C_TypeDef* I2Cx, u8 I2C_Register); +FlagStatus I2C_GetFlagStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag); +ErrStatus I2C_CheckStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Status); +void I2C_ClearFlag(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag); +void I2C_SetSCLHighPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_HighPeriod); +void I2C_SetSCLLowPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_LowPeriod); +void I2C_PDMACmd(HT_I2C_TypeDef* I2Cx, u32 I2C_PDMAREQ, ControlStatus NewState); +void I2C_PDMANACKCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_TimeOutCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_SetTimeOutValue(HT_I2C_TypeDef* I2Cx, u32 I2C_Timeout); +void I2C_SetTimeOutPrescaler(HT_I2C_TypeDef* I2Cx, u32 I2C_Prescaler); +void I2C_AddressMaskConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Mask); +u16 I2C_GetAddressBuffer(HT_I2C_TypeDef* I2Cx); +void I2C_CombFilterCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_SequentialFilterConfig(HT_I2C_TypeDef* I2Cx, u32 Seq_Filter_Select); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_i2s.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_i2s.h new file mode 100644 index 00000000000..4a63e994586 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_i2s.h @@ -0,0 +1,240 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_i2s.h + * @version $Rev:: 1364 $ + * @date $Date:: 2018-08-02 #$ + * @brief The header file of the I2S library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_I2S_H +#define __HT32F1XXXX_I2S_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Types I2S exported types + * @{ + */ +typedef struct +{ + u32 I2S_Mode; + u32 I2S_Format; + u32 I2S_WordWidth; + u32 I2S_MclkOut; + u32 I2S_MclkInv; + u32 I2S_BclkInv; + u32 I2S_X_Div; + u32 I2S_Y_Div; + u32 I2S_N_Div; +} I2S_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Constants I2S exported constants + * @{ + */ +/* mode */ +#define I2S_MASTER_TX (1UL << 1) +#define I2S_MASTER_RX (1UL << 2) +#define I2S_MASTER_TX_RX ((1UL << 1) | (1UL << 2)) + +#define I2S_SLAVE_TX ((1UL << 3) | (1UL << 1)) +#define I2S_SLAVE_RX ((1UL << 3) | (1UL << 2)) +#define I2S_SLAVE_TX_RX ((1UL << 3) | (1UL << 1) | (1UL << 2)) + +#define IS_I2S_MODE(MOD) ((MOD == I2S_MASTER_TX) || \ + (MOD == I2S_MASTER_RX) || \ + (MOD == I2S_MASTER_TX_RX) || \ + (MOD == I2S_SLAVE_TX) || \ + (MOD == I2S_SLAVE_RX) || \ + (MOD == I2S_SLAVE_TX_RX)) + + +/* format */ +#define I2S_JUSTIFIED_STEREO (0) +#define LEFT_JUSTIFIED_STEREO (1UL << 6) +#define RIGHT_JUSTIFIED_STEREO (2UL << 6) +#define I2S_JUSTIFIED_REPEAT (1UL << 10) + +#define I2S_JUSTIFIED_STEREO_EXT (1UL << 8) +#define LEFT_JUSTIFIED_STEREO_EXT ((1UL << 8) | (1UL << 6)) +#define RIGHT_JUSTIFIED_STEREO_EXT ((1UL << 8) | (2UL << 6)) +#define I2S_JUSTIFIED_REPEAT_EXT ((1UL << 8) | (1UL << 10)) + +#define I2S_JUSTIFIED_MONO (1UL << 11) +#define LEFT_JUSTIFIED_MONO ((1UL << 11) | (1UL << 6)) +#define RIGHT_JUSTIFIED_MONO ((1UL << 11) | (2UL << 6)) + +#define I2S_JUSTIFIED_MONO_EXT ((1UL << 8) | (1UL << 11)) +#define LEFT_JUSTIFIED_MONO_EXT ((1UL << 8) | (1UL << 11) | (1UL << 6)) +#define RIGHT_JUSTIFIED_MONO_EXT ((1UL << 8) | (1UL << 11) | (2UL << 6)) + +#define IS_I2S_FORMAT(FMT) ((FMT == I2S_JUSTIFIED_STEREO) || \ + (FMT == LEFT_JUSTIFIED_STEREO) || \ + (FMT == RIGHT_JUSTIFIED_STEREO) || \ + (FMT == I2S_JUSTIFIED_REPEAT) || \ + (FMT == I2S_JUSTIFIED_STEREO_EXT) || \ + (FMT == LEFT_JUSTIFIED_STEREO_EXT) || \ + (FMT == RIGHT_JUSTIFIED_STEREO_EXT) || \ + (FMT == I2S_JUSTIFIED_REPEAT_EXT) || \ + (FMT == I2S_JUSTIFIED_MONO) || \ + (FMT == LEFT_JUSTIFIED_MONO) || \ + (FMT == RIGHT_JUSTIFIED_MONO) || \ + (FMT == I2S_JUSTIFIED_MONO_EXT) || \ + (FMT == LEFT_JUSTIFIED_MONO_EXT) || \ + (FMT == RIGHT_JUSTIFIED_MONO_EXT)) + + +/* word width */ +#define I2S_WORDWIDTH_8 (0) +#define I2S_WORDWIDTH_16 (1UL << 4) +#define I2S_WORDWIDTH_24 (2UL << 4) +#define I2S_WORDWIDTH_32 (3UL << 4) + +#define IS_I2S_WORD_WIDTH(WIDTH) ((WIDTH == I2S_WORDWIDTH_8) || \ + (WIDTH == I2S_WORDWIDTH_16) || \ + (WIDTH == I2S_WORDWIDTH_24) || \ + (WIDTH == I2S_WORDWIDTH_32)) + + +/* clock divider */ +#define IS_I2S_MCLK_DIV(X, Y) ((X > 0) && (X < 256) && (Y > 0) && (Y < 256) && (X <= Y)) + +#define IS_I2S_BCLK_DIV(N) (N < 256) + + +/* FIFO */ +#define I2S_TX_FIFO (1UL << 8) +#define I2S_RX_FIFO (2UL << 8) + +#define IS_I2S_ONE_FIFO(FIFO) ((FIFO == I2S_TX_FIFO) || (FIFO == I2S_RX_FIFO)) + +#define IS_I2S_TWO_FIFO(FIFO) (((FIFO & 0xFFFFFCFF) == 0) && (FIFO != 0)) + +#define IS_I2S_FIFO_LEVEL(LEVEL) ((LEVEL & 0x0000000F) < 9) + + +/* interrupt */ +#define I2S_INT_TXFIFO_TRI (1UL) +#define I2S_INT_TXFIFO_UDF (1UL << 1) +#define I2S_INT_TXFIFO_OVF (1UL << 2) + +#define I2S_INT_RXFIFO_TRI (1UL << 4) +#define I2S_INT_RXFIFO_UDF (1UL << 5) +#define I2S_INT_RXFIFO_OVF (1UL << 6) + +#define IS_I2S_INT(INT) (((INT & 0xFFFFFF88) == 0) && (INT != 0)) + + +/* flag */ +#define I2S_FLAG_TXFIFO_TRI (1UL) +#define I2S_FLAG_TXFIFO_UDF (1UL << 1) +#define I2S_FLAG_TXFIFO_OVF (1UL << 2) +#define I2S_FLAG_RXFIFO_TRI (1UL << 8) +#define I2S_FLAG_RXFIFO_UDF (1UL << 9) +#define I2S_FLAG_RXFIFO_OVF (1UL << 10) + +#define I2S_FLAG_TXFIFO_EMP (1UL << 3) +#define I2S_FLAG_TXFIFO_FUL (1UL << 4) +#define I2S_FLAG_RXFIFO_EMP (1UL << 11) +#define I2S_FLAG_RXFIFO_FUL (1UL << 12) +#define I2S_FLAG_RIGHT_CH (1UL << 16) +#define I2S_FLAG_TX_BUSY (1UL << 17) +#define I2S_FLAG_CLK_RDY (1UL << 18) + +#define IS_I2S_FLAG_CLEAR(FLAG) (((FLAG & 0xFFFFF8F8) == 0) && (FLAG != 0)) + +#define IS_I2S_FLAG(FLAG) ((FLAG == I2S_FLAG_TXFIFO_TRI) || \ + (FLAG == I2S_FLAG_TXFIFO_UDF) || \ + (FLAG == I2S_FLAG_TXFIFO_OVF) || \ + (FLAG == I2S_FLAG_TXFIFO_EMP) || \ + (FLAG == I2S_FLAG_TXFIFO_FUL) || \ + (FLAG == I2S_FLAG_RXFIFO_TRI) || \ + (FLAG == I2S_FLAG_RXFIFO_UDF) || \ + (FLAG == I2S_FLAG_RXFIFO_OVF) || \ + (FLAG == I2S_FLAG_RXFIFO_EMP) || \ + (FLAG == I2S_FLAG_RXFIFO_FUL) || \ + (FLAG == I2S_FLAG_RIGHT_CH) || \ + (FLAG == I2S_FLAG_TX_BUSY) || \ + (FLAG == I2S_FLAG_CLK_RDY)) + + +/* PDMA request */ +#define I2S_PDMAREQ_TX (1UL << 13) +#define I2S_PDMAREQ_RX (1UL << 14) + +#define IS_I2S_PDMA_REQ(REQ) (((REQ & 0xFFFF9FFF) == 0) && (REQ != 0)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Functions I2S exported functions + * @{ + */ +void I2S_DeInit(void); +void I2S_Init(I2S_InitTypeDef* I2S_InitStruct); +void I2S_Cmd(ControlStatus NewState); +void I2S_MclkOutputCmd(ControlStatus NewState); +void I2S_TxMuteCmd(ControlStatus NewState); +void I2S_PDMACmd(u32 I2S_PDMAREQ, ControlStatus NewState); +void I2S_FIFOReset(u32 I2S_FIFO); +void I2S_FIFOTrigLevelConfig(u32 I2S_FIFO, u32 I2S_FIFOLevel); +u8 I2S_GetFIFOStatus(u32 I2S_FIFO); +void I2S_IntConfig(u32 I2S_Int, ControlStatus NewState); +FlagStatus I2S_GetFlagStatus(u32 I2S_Flag); +void I2S_ClearFlag(u32 I2S_Flag); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_lib.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_lib.h new file mode 100644 index 00000000000..f3c09ec6c04 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_lib.h @@ -0,0 +1,223 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_lib.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file includes all the header files of the libraries. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_LIB_H +#define __HT32F1XXXX_LIB_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Settings ------------------------------------------------------------------------------------------------*/ +#define HT32_FWLIB_VER (0x01004001) +#define HT32_FWLIB_SVN (0x2982) + +#if defined(USE_HT32F1653_54) + #include "ht32f1653_54_libcfg.h" +#endif +#if defined(USE_HT32F1655_56) + #include "ht32f1655_56_libcfg.h" +#endif +#if defined(USE_HT32F12365_66) + #include "ht32f12365_66_libcfg.h" +#endif +#if defined(USE_HT32F12345) + #include "ht32f12345_libcfg.h" +#endif +#if defined(USE_HT32F12364) + #include "ht32f12364_libcfg.h" +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include +#include "ht32f1xxxx_conf.h" + +#if (HT32_LIB_DEBUG == 1) +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define Assert_Param(expr) ((expr) ? (void)0 : assert_error((u8 *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- ------------------------------*/ +void assert_error(u8* file, u32 line); +#else + +#define Assert_Param(expr) ((void)0) + +#endif /* DEBUG --------------------------------------------------------------------------------------------*/ + + +#if _ADC + #include "ht32f1xxxx_adc.h" +#endif + +#if _AES && LIBCFG_AES + #include "ht32f1xxxx_aes.h" +#endif + +#if _BFTM + #include "ht32f1xxxx_bftm.h" +#endif + +#if _CKCU + #include "ht32f1xxxx_ckcu.h" +#endif + +#if _CMP_OPA && LIBCFG_CMP_OPA + #include "ht32f1xxxx_cmp_op.h" +#endif + +#if _CMP && (!LIBCFG_CMP_OPA) + #include "ht32f1xxxx_cmp.h" +#endif + +#if _CRC + #include "ht32f1xxxx_crc.h" +#endif + +#if _CSIF && LIBCFG_CSIF + #include "ht32f2xxxx_csif.h" +#endif + +#if _EBI + #include "ht32f1xxxx_ebi.h" +#endif + +#if _EXTI + #include "ht32f1xxxx_exti.h" +#endif + +#if _FLASH + #include "ht32f1xxxx_flash.h" +#endif + +#if _GPIO + #include "ht32f1xxxx_gpio.h" +#endif + +#if _GPTM + #include "ht32f1xxxx_tm_type.h" + #include "ht32f1xxxx_tm.h" +#endif + +#if _I2C + #include "ht32f1xxxx_i2c.h" +#endif + +#if _I2S + #include "ht32f1xxxx_i2s.h" +#endif + +#if _MCTM && (!LIBCFG_NO_MCTM0) + #include "ht32f1xxxx_tm_type.h" + #include "ht32f1xxxx_tm.h" + #include "ht32f1xxxx_mctm.h" +#endif + +#if _PDMA + #include "ht32f1xxxx_pdma.h" +#endif + +#if _PWRCU + #include "ht32f1xxxx_pwrcu.h" +#endif + +#if _PWM + #include "ht32f1xxxx_tm_type.h" + #include "ht32f1xxxx_tm.h" +#endif + +#if _RSTCU + #include "ht32f1xxxx_rstcu.h" +#endif + +#if _RTC + #include "ht32f1xxxx_rtc.h" +#endif + +#if _SCI && LIBCFG_SCI0 + #include "ht32f1xxxx_sci.h" +#endif + +#if _SDIO && LIBCFG_SDIO + #include "ht32f1xxxx_sdio.h" +#endif + +#if _SPI + #include "ht32f1xxxx_spi.h" +#endif + +#if _SCTM + #include "ht32f1xxxx_tm_type.h" + #include "ht32f1xxxx_tm.h" +#endif + +#if _USART + #include "ht32f1xxxx_usart.h" +#endif + +#if _USB + #include "ht32f1xxxx_usbd.h" +#endif + +#if _WDT + #include "ht32f1xxxx_wdt.h" +#endif + +#if _MISC + #include "ht32_cm3_misc.h" +#endif + +#if _SERIAL + #include "ht32_serial.h" +#endif + +#if _SWRAND + #include "ht32_rand.h" +#endif + +#if (_RETARGET) + #if defined (__GNUC__) + #undef getchar + #define getchar SERIAL_GetChar + #endif +#endif + +#ifdef HTCFG_TIME_IPSEL +#include "ht32_time.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_mctm.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_mctm.h new file mode 100644 index 00000000000..e99cfa0f301 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_mctm.h @@ -0,0 +1,237 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_mctm.h + * @version $Rev:: 122 $ + * @date $Date:: 2017-06-13 #$ + * @brief The header file of the MCTM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_MCTM_H +#define __HT32F1XXXX_MCTM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_tm.h" +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup MCTM + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Types MCTM exported types + * @{ + */ +/** + * @brief Enumeration of MCTM channel output idle state. + */ +/** + * @brief Definition of Break & DeadTime init structure. + */ +typedef struct +{ + u32 OSSRState; + u32 OSSIState; + u32 LockLevel; + u32 Break0; + u32 Break0Polarity; + u32 Break1; + u32 Break1Polarity; + u32 AutomaticOutput; + u8 DeadTime; + u8 BreakFilter; +} MCTM_CHBRKCTRInitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Constants MCTM exported constants + * @{ + */ + +/** @defgroup MCTM_BKE Definitions of MCTM break control + * @{ + */ +#define MCTM_BREAK_ENABLE 0x00000001 /*!< Break enable */ +#define MCTM_BREAK_DISABLE 0x00000000 /*!< Break disable */ +/** + * @} + */ + +/** @defgroup MCTM_BKP Definitions of MCTM break polarity + * @{ + */ +#define MCTM_BREAK_POLARITY_LOW 0x00000000 /*!< Break input pin active low level */ +#define MCTM_BREAK_POLARITY_HIGH 0x00000002 /*!< Break input pin active high level */ +/** + * @} + */ + +/** @defgroup MCTM_CHMOE Definitions of MCTM main output enable function state + * @{ + */ +#define MCTM_CHMOE_DISABLE 0x00000000 /*!< main output disable */ +#define MCTM_CHMOE_ENABLE 0x00000010 /*!< Main output enable */ +/** + * @} + */ + +/** @defgroup MCTM_CHAOE Definitions of MCTM automatic output enable function state + * @{ + */ +#define MCTM_CHAOE_DISABLE 0x00000000 /*!< Automatic output enable function disable */ +#define MCTM_CHAOE_ENABLE 0x00000020 /*!< Automatic output enable function enable */ +/** + * @} + */ + +/** @defgroup MCTM_LOCK_LEVEL Definitions of MCTM lock level selection + * @{ + */ +#define MCTM_LOCK_LEVEL_OFF 0x00000000 /*!< Lock Off */ +#define MCTM_LOCK_LEVEL_1 0x00010000 /*!< Lock level 1 */ +#define MCTM_LOCK_LEVEL_2 0x00020000 /*!< Lock level 2 */ +#define MCTM_LOCK_LEVEL_3 0x00030000 /*!< Lock level 3 */ +/** + * @} + */ + +/** @defgroup MCTM_OSSI Definitions of Off-State Selection for Idle mode states + * @{ + */ +#define MCTM_OSSI_STATE_ENABLE 0x00100000 +#define MCTM_OSSI_STATE_DISABLE 0x00000000 +/** + * @} + */ + +/** @defgroup MCTM_OSSR Definitions of Off-State Selection for Run mode states + * @{ + */ +#define MCTM_OSSR_STATE_ENABLE 0x00200000 +#define MCTM_OSSR_STATE_DISABLE 0x00000000 +/** + * @} + */ + +/** @defgroup MCTM_Check_Parameter Check parameter + * @{ + */ + +/** + * @brief Used to check parameter of the MCTMx. + */ +#define IS_MCTM(x) ((x == HT_MCTM0) || (x == HT_MCTM1)) +/** + * @brief Used to check parameter of the complementary output channel. + */ +#define IS_MCTM_COMPLEMENTARY_CH(x) (((x) == TM_CH_0) || ((x) == TM_CH_1) || \ + ((x) == TM_CH_2)) +/** + * @brief Used to check parameter of the COMUS. + */ +#define IS_MCTM_COMUS(x) ((x == MCTM_COMUS_STIOFF) || (x == MCTM_COMUS_STION)) +/** + * @brief Used to check parameter of the channel output idle state. + */ +#define IS_MCTM_OIS(x) ((x == MCTM_OIS_LOW) || (x == MCTM_OIS_HIGH)) +/** + * @brief Used to check value of MCTM break control state. + */ +#define IS_MCTM_BREAK_STATE(STATE) (((STATE) == MCTM_BREAK_ENABLE) || \ + ((STATE) == MCTM_BREAK_DISABLE)) +/** + * @brief Used to check value of MCTM break polarity. + */ +#define IS_MCTM_BREAK_POLARITY(POLARITY) (((POLARITY) == MCTM_BREAK_POLARITY_LOW) || \ + ((POLARITY) == MCTM_BREAK_POLARITY_HIGH)) +/** + * @brief Used to check value of MCTM automatic output enable control state. + */ +#define IS_MCTM_CHAOE_STATE(STATE) (((STATE) == MCTM_CHAOE_ENABLE) || \ + ((STATE) == MCTM_CHAOE_DISABLE)) +/** + * @brief Used to check value of MCTM lock level. + */ +#define IS_MCTM_LOCK_LEVEL(LEVEL) (((LEVEL) == MCTM_LOCK_LEVEL_OFF) || \ + ((LEVEL) == MCTM_LOCK_LEVEL_1) || \ + ((LEVEL) == MCTM_LOCK_LEVEL_2) || \ + ((LEVEL) == MCTM_LOCK_LEVEL_3)) +/** + * @brief Used to check value of MCTM OSSI state. + */ +#define IS_MCTM_OSSI_STATE(STATE) (((STATE) == MCTM_OSSI_STATE_ENABLE) || \ + ((STATE) == MCTM_OSSI_STATE_DISABLE)) +/** + * @brief Used to check value of MCTM OSSR state. + */ +#define IS_MCTM_OSSR_STATE(STATE) (((STATE) == MCTM_OSSR_STATE_ENABLE) || \ + ((STATE) == MCTM_OSSR_STATE_DISABLE)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Functions MCTM exported functions + * @{ + */ +void MCTM_ChNPolarityConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHP_Enum Pol); +void MCTM_ChannelNConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control); + +void MCTM_CHMOECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState); +void MCTM_CHBRKCTRConfig(HT_TM_TypeDef* MCTMx, MCTM_CHBRKCTRInitTypeDef *CHBRKCTRInit); +void MCTM_CHBRKCTRStructInit(MCTM_CHBRKCTRInitTypeDef* CHBRKCTRInit); +void MCTM_COMPRECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState); +void MCTM_COMUSConfig(HT_TM_TypeDef* MCTMx, MCTM_COMUS_Enum Sel); + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_pdma.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_pdma.h new file mode 100644 index 00000000000..fbb2259615e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_pdma.h @@ -0,0 +1,344 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_pdma.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the PDMA library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_PDMA_H +#define __HT32F1XXXX_PDMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup PDMA + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Types PDMA exported types + * @{ + */ + +/** + * @brief Definition of PDMA channel Init Structure + */ +typedef struct +{ + u32 PDMACH_SrcAddr; /*!< source address */ + u32 PDMACH_DstAddr; /*!< destination address */ + u16 PDMACH_BlkCnt; /*!< number of blocks for a PDMA transfer (1 ~ 65,535) */ + u16 PDMACH_BlkLen; /*!< number of data for a block (1 ~ 65,535) */ + u8 PDMACH_DataSize; /*!< number of bits for a data (8-bit/16-bit/32-bit) */ + u16 PDMACH_Priority; /*!< software priority for a PDMA transfer (L/M/H/VH) */ + u16 PDMACH_AdrMod; /*!< address mode (LIN_INC/LIN_DEC/CIR_INC/CIR_DEC/FIX/AUTO_RELOAD) */ +} PDMACH_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Constants PDMA exported constants + * @{ + */ +/* priority */ +#define L_PRIO (0) /*!< low priority */ +#define M_PRIO (1UL << 8) /*!< medium priority */ +#define H_PRIO (2UL << 8) /*!< high priority */ +#define VH_PRIO (3UL << 8) /*!< very high priority */ + +#define IS_PDMA_PRIO(PRIO) ((PRIO >> 8) < 4) /*!< check channel priority parameter */ + +/* address mode */ +#define AUTO_RELOAD (1UL << 11) /*!< enable auto reload */ +#define ADR_FIX (1UL << 10) /*!< enable address fix */ + +#define SRC_ADR_LIN_INC (0) /*!< source address linear increment */ +#define SRC_ADR_LIN_DEC (1UL << 6) /*!< source address linear decrement */ +#define SRC_ADR_CIR_INC (2UL << 6) /*!< source address circular increment */ +#define SRC_ADR_CIR_DEC (3UL << 6) /*!< source address circular decrement */ +#define SRC_ADR_FIX (ADR_FIX | SRC_ADR_CIR_INC) /*!< source address fix */ + +#define DST_ADR_LIN_INC (0) /*!< destination address linear increment */ +#define DST_ADR_LIN_DEC (1UL << 4) /*!< destination address linear decrement */ +#define DST_ADR_CIR_INC (2UL << 4) /*!< destination address circular increment */ +#define DST_ADR_CIR_DEC (3UL << 4) /*!< destination address circular decrement */ +#define DST_ADR_FIX (ADR_FIX | DST_ADR_CIR_INC) /*!< destination address fix */ + +#define IS_PDMA_ADR_MOD(MOD) ((MOD & 0xFFFFF30F) == 0) /*!< check address mode parameters */ + +/* transfer size */ +#if (LIBCFG_PDMA_BLKLEN65536) +#define _PDMA_BLK_LEN (65535) +#else +#define _PDMA_BLK_LEN (255) +#endif +#define IS_PDMA_BLK_CNT(CNT) ((CNT > 0) && (CNT <= 65535)) /*!< block count per transfer */ +#define IS_PDMA_BLK_LEN(LEN) ((LEN > 0) && (LEN <= _PDMA_BLK_LEN)) /*!< block size per block count */ + +/* transfer width */ +#define WIDTH_8BIT (0) /*!< 8-bit transfer width */ +#define WIDTH_16BIT (1UL << 2) /*!< 16-bit transfer width */ +#define WIDTH_32BIT (2UL << 2) /*!< 32-bit transfer width */ + +#define IS_PDMA_WIDTH(WIDTH) ((WIDTH >> 2) < 3) /*!< check transfer width parameter */ + +/* channel number */ +#define PDMA_CH0 (0) /*!< channel 0 number */ +#define PDMA_CH1 (1UL) /*!< channel 1 number */ +#define PDMA_CH2 (2UL) /*!< channel 2 number */ +#define PDMA_CH3 (3UL) /*!< channel 3 number */ +#define PDMA_CH4 (4UL) /*!< channel 4 number */ +#define PDMA_CH5 (5UL) /*!< channel 5 number */ +#if !(LIBCFG_NO_PDMA_CH6_11) +#define PDMA_CH6 (6UL) /*!< channel 6 number */ +#define PDMA_CH7 (7UL) /*!< channel 7 number */ +#if (LIBCFG_PDMA_CH8_11) +#define PDMA_CH8 (8UL) /*!< channel 8 number */ +#define PDMA_CH9 (9UL) /*!< channel 9 number */ +#define PDMA_CH10 (10UL) /*!< channel 10 number */ +#define PDMA_CH11 (11UL) /*!< channel 11 number */ +#endif +#endif + +#if (LIBCFG_NO_PDMA_CH6_11) +#define _PDMA_CH_NUM (6) +#elif (LIBCFG_PDMA_CH8_11) +#define _PDMA_CH_NUM (12) +#else +#define _PDMA_CH_NUM (8) +#endif + +#define IS_PDMA_CH(CH) (CH < _PDMA_CH_NUM) /*!< check channel number parameter */ + +#define PDMA_ADC0 PDMA_CH0 /*!< ADC PDMA channel number */ +#define PDMA_ADC PDMA_ADC0 + +#define PDMA_SPI0_RX PDMA_CH0 /*!< SPI0_RX PDMA channel number */ +#define PDMA_SPI0_TX PDMA_CH1 /*!< SPI0_TX PDMA channel number */ +#define PDMA_SPI1_RX PDMA_CH4 /*!< SPI1_RX PDMA channel number */ +#define PDMA_SPI1_TX PDMA_CH5 /*!< SPI1_TX PDMA channel number */ + +#if defined(USE_HT32F12364) +#define PDMA_USART0_RX PDMA_CH0 /*!< USART_RX PDMA channel number */ +#define PDMA_USART0_TX PDMA_CH1 /*!< USART_TX PDMA channel number */ +#else +#define PDMA_USART0_RX PDMA_CH2 /*!< USART0_RX PDMA channel number */ +#define PDMA_USART0_TX PDMA_CH3 /*!< USART0_TX PDMA channel number */ +#endif +#if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) +#define PDMA_USART1_TX PDMA_CH6 /*!< USART1_TX PDMA channel number */ +#define PDMA_USART1_RX PDMA_CH7 /*!< USART1_RX PDMA channel number */ +#endif +#if defined(USE_HT32F12365_66) || defined(USE_HT32F12345) +#define PDMA_USART1_RX PDMA_CH8 /*!< USART1_RX PDMA channel number */ +#define PDMA_USART1_TX PDMA_CH9 /*!< USART1_TX PDMA channel number */ +#endif +#if defined(USE_HT32F12364) +#define PDMA_UART0_RX PDMA_CH2 /*!< UART0_RX PDMA channel number */ +#define PDMA_UART0_TX PDMA_CH3 /*!< UART0_TX PDMA channel number */ +#else +#define PDMA_UART0_RX PDMA_CH0 /*!< UART0_RX PDMA channel number */ +#define PDMA_UART0_TX PDMA_CH1 /*!< UART0_TX PDMA channel number */ +#endif +#define PDMA_UART1_RX PDMA_CH4 /*!< UART1_RX PDMA channel number */ +#define PDMA_UART1_TX PDMA_CH5 /*!< UART1_TX PDMA channel number */ + +#if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) +#define PDMA_SCI0_RX PDMA_CH6 /*!< SCI_RX PDMA channel number */ +#define PDMA_SCI0_TX PDMA_CH7 /*!< SCI_TX PDMA channel number */ +#endif +#if defined(USE_HT32F12364) +#define PDMA_SCI0_RX PDMA_CH4 /*!< SCI_RX PDMA channel number */ +#define PDMA_SCI0_TX PDMA_CH5 /*!< SCI_TX PDMA channel number */ +#endif +#if defined(USE_HT32F12365_66) +#define PDMA_SCI0_RX PDMA_CH8 /*!< SCI0_RX PDMA channel number */ +#define PDMA_SCI0_TX PDMA_CH9 /*!< SCI0_TX PDMA channel number */ +#define PDMA_SCI1_RX PDMA_CH10 /*!< SCI1_RX PDMA channel number */ +#define PDMA_SCI1_TX PDMA_CH11 /*!< SCI1_TX PDMA channel number */ +#endif + +#if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) || defined(USE_HT32F12364) +#define PDMA_I2C0_RX PDMA_CH2 /*!< I2C0_RX PDMA channel number */ +#define PDMA_I2C0_TX PDMA_CH4 /*!< I2C0_TX PDMA channel number */ +#elif defined(USE_HT32F12365_66) || defined(USE_HT32F12345) +#define PDMA_I2C0_RX PDMA_CH10 /*!< I2C0_RX PDMA channel number */ +#define PDMA_I2C0_TX PDMA_CH11 /*!< I2C0_TX PDMA channel number */ +#endif +#if defined(USE_HT32F12364) +#define PDMA_I2C1_RX PDMA_CH3 /*!< I2C1_RX PDMA channel number */ +#define PDMA_I2C1_TX PDMA_CH5 /*!< I2C1_TX PDMA channel number */ +#else +#define PDMA_I2C1_RX PDMA_CH6 /*!< I2C1_RX PDMA channel number */ +#define PDMA_I2C1_TX PDMA_CH7 /*!< I2C1_TX PDMA channel number */ +#endif + +#if !(LIBCFG_NO_MCTM0) +#define PDMA_MCTM0_CH0 PDMA_CH0 /*!< MCTM0_CH0 PDMA channel number */ +#define PDMA_MCTM0_TRIG PDMA_CH1 /*!< MCTM0_TRIG PDMA channel number */ +#define PDMA_MCTM0_CH1 PDMA_CH2 /*!< MCTM0_CH1 PDMA channel number */ +#define PDMA_MCTM0_CH3 PDMA_CH3 /*!< MCTM0_CH3 PDMA channel number */ +#define PDMA_MCTM0_CH2 PDMA_CH4 /*!< MCTM0_CH2 PDMA channel number */ +#define PDMA_MCTM0_UEV1 PDMA_CH5 /*!< MCTM0_UEV1 PDMA channel number */ +#define PDMA_MCTM0_UEV2 PDMA_CH7 /*!< MCTM0_UEV2 PDMA channel number */ + +#define PDMA_MCTM1_CH0 PDMA_CH1 /*!< MCTM1_CH0 PDMA channel number */ +#define PDMA_MCTM1_CH2 PDMA_CH2 /*!< MCTM1_CH2 PDMA channel number */ +#define PDMA_MCTM1_UEV1 PDMA_CH3 /*!< MCTM1_UEV1 PDMA channel number */ +#define PDMA_MCTM1_CH1 PDMA_CH4 /*!< MCTM1_CH1 PDMA channel number */ +#define PDMA_MCTM1_CH3 PDMA_CH5 /*!< MCTM1_CH3 PDMA channel number */ +#define PDMA_MCTM1_UEV2 PDMA_CH6 /*!< MCTM1_UEV2 PDMA channel number */ +#define PDMA_MCTM1_TRIG PDMA_CH7 /*!< MCTM1_TRIG PDMA channel number */ +#endif + +#if defined(USE_HT32F12364) +#define PDMA_GPTM0_CH0 PDMA_CH2 /*!< GPTM0_CH0 PDMA channel number */ +#define PDMA_GPTM0_CH1 PDMA_CH0 /*!< GPTM0_CH1 PDMA channel number */ +#define PDMA_GPTM0_CH2 PDMA_CH1 /*!< GPTM0_CH2 PDMA channel number */ +#define PDMA_GPTM0_CH3 PDMA_CH0 /*!< GPTM0_CH3 PDMA channel number */ +#define PDMA_GPTM0_TRIG PDMA_CH2 /*!< GPTM0_TRIG PDMA channel number */ +#define PDMA_GPTM0_UEV PDMA_CH1 /*!< GPTM0_UEV PDMA channel number */ +#else +#define PDMA_GPTM0_CH1 PDMA_CH0 /*!< GPTM0_CH1 PDMA channel number */ +#define PDMA_GPTM0_CH3 PDMA_CH0 /*!< GPTM0_CH3 PDMA channel number */ +#define PDMA_GPTM0_UEV PDMA_CH1 /*!< GPTM0_UEV PDMA channel number */ +#define PDMA_GPTM0_CH2 PDMA_CH2 /*!< GPTM0_CH2 PDMA channel number */ +#define PDMA_GPTM0_CH0 PDMA_CH3 /*!< GPTM0_CH0 PDMA channel number */ +#define PDMA_GPTM0_TRIG PDMA_CH3 /*!< GPTM0_TRIG PDMA channel number */ +#endif + +#if defined(USE_HT32F1653_54) || defined(USE_HT32F1655_56) +#define PDMA_GPTM1_CH0 PDMA_CH4 /*!< GPTM1_CH0 PDMA channel number */ +#define PDMA_GPTM1_CH1 PDMA_CH5 /*!< GPTM1_CH1 PDMA channel number */ +#define PDMA_GPTM1_UEV PDMA_CH5 /*!< GPTM1_UEV PDMA channel number */ +#define PDMA_GPTM1_CH2 PDMA_CH6 /*!< GPTM1_CH2 PDMA channel number */ +#define PDMA_GPTM1_TRIG PDMA_CH6 /*!< GPTM1_TRIG PDMA channel number */ +#define PDMA_GPTM1_CH3 PDMA_CH7 /*!< GPTM1_CH3 PDMA channel number */ +#endif +#if defined(USE_HT32F12365_66) || defined(USE_HT32F12345) +#define PDMA_GPTM1_CH0 PDMA_CH8 /*!< GPTM1_CH0 PDMA channel number */ +#define PDMA_GPTM1_CH1 PDMA_CH9 /*!< GPTM1_CH1 PDMA channel number */ +#define PDMA_GPTM1_UEV PDMA_CH9 /*!< GPTM1_UEV PDMA channel number */ +#define PDMA_GPTM1_CH2 PDMA_CH10 /*!< GPTM1_CH2 PDMA channel number */ +#define PDMA_GPTM1_TRIG PDMA_CH10 /*!< GPTM1_TRIG PDMA channel number */ +#define PDMA_GPTM1_CH3 PDMA_CH11 /*!< GPTM1_CH3 PDMA channel number */ +#endif + +#if (LIBCFG_PWM0) +#define PDMA_PWM0_CH0 PDMA_CH5 /*!< PWM0_CH0 PDMA channel number */ +#define PDMA_PWM0_CH1 PDMA_CH3 /*!< PWM0_CH1 PDMA channel number */ +#define PDMA_PWM0_CH2 PDMA_CH4 /*!< PWM0_CH2 PDMA channel number */ +#define PDMA_PWM0_CH3 PDMA_CH3 /*!< PWM0_CH3 PDMA channel number */ +#define PDMA_PWM0_TRIG PDMA_CH5 /*!< PWM0_TRIG PDMA channel number */ +#define PDMA_PWM0_UEV PDMA_CH4 /*!< PWM0_UEV PDMA channel number */ +#endif + + +#define PDMA_I2S_RX PDMA_CH2 /*!< I2S_RX PDMA channel number */ +#define PDMA_I2S_TX PDMA_CH3 /*!< I2S_TX PDMA channel number */ + +#if defined(USE_HT32F12365_66) +#define PDMA_CSIF PDMA_CH0 /*!< CSIF PDMA channel number */ +#endif + +#if defined(USE_HT32F12365_66) || defined(USE_HT32F12345) +#define PDMA_SDIO_RX PDMA_CH6 /*!< SDIO_RX PDMA channel number */ +#define PDMA_SDIO_TX PDMA_CH7 /*!< SDIO_TX PDMA channel number */ +#endif + +#if defined(USE_HT32F12364) +#define PDMA_AES_OUT PDMA_CH4 /*!< AES_OUT PDMA channel number */ +#define PDMA_AES_IN PDMA_CH5 /*!< AES_IN PDMA channel number */ +#elif defined(USE_HT32F12365_66) +#define PDMA_AES_OUT PDMA_CH10 /*!< AES_OUT PDMA channel number */ +#define PDMA_AES_IN PDMA_CH11 /*!< AES_IN PDMA channel number */ +#endif + +/* flag */ +#define PDMA_FLAG_GE (1UL << 0) /*!< PDMA channel global event flag */ +#define PDMA_FLAG_BE (1UL << 1) /*!< PDMA channel block end flag */ +#define PDMA_FLAG_HT (1UL << 2) /*!< PDMA channel half transfer flag */ +#define PDMA_FLAG_TC (1UL << 3) /*!< PDMA channel transfer complete flag */ +#define PDMA_FLAG_TE (1UL << 4) /*!< PDMA channel transfer error flag */ + +#define IS_PDMA_FLAG(FLAG) (((FLAG & 0xFFFFFFE0) == 0) && (FLAG != 0)) +#define IS_PDMA_CLEAR_FLAG(FLAG) (((FLAG & 0xFFFFFFE0) == 0) && (FLAG != 0)) + +/* interrupt */ +#define PDMA_INT_GE (1UL << 0) /*!< PDMA channel global event interrupt */ +#define PDMA_INT_BE (1UL << 1) /*!< PDMA channel block end interrupt */ +#define PDMA_INT_HT (1UL << 2) /*!< PDMA channel half transfer interrupt */ +#define PDMA_INT_TC (1UL << 3) /*!< PDMA channel transfer complete interrupt */ +#define PDMA_INT_TE (1UL << 4) /*!< PDMA channel transfer error interrupt */ + +#define IS_PDMA_INT(INT) (((INT & 0xFFFFFFE0) == 0) && (INT != 0)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Functions PDMA exported functions + * @{ + */ +void PDMA_DeInit(void); +void PDMA_Config(u32 PDMA_CHn, PDMACH_InitTypeDef *PDMACH_InitStruct); +void PDMA_AddrConfig(u32 PDMA_CHn, u32 SrcAddr, u32 DstAddr); +void PDMA_SrcAddrConfig(u32 PDMA_CHn, u32 SrcAddr); +void PDMA_DstAddrConfig(u32 PDMA_CHn, u32 DstAddr); +void PDMA_TranSizeConfig(u32 PDMA_CHn, u16 BlkCnt, u16 BlkLen); +void PDMA_EnaCmd(u32 PDMA_CHn, ControlStatus NewState); +void PDMA_SwTrigCmd(u32 PDMA_CHn, ControlStatus NewState); + +void PDMA_IntConfig(u32 PDMA_CHn, u32 PDMA_INT_x, ControlStatus NewState); +FlagStatus PDMA_GetFlagStatus(u32 PDMA_CHn, u32 PDMA_FLAG_x); +void PDMA_ClearFlag(u32 PDMA_CHn, u32 PDMA_FLAG_x); +u16 PDMA_GetRemainBlkCnt(u32 PDMA_CHn); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_pwrcu.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_pwrcu.h new file mode 100644 index 00000000000..267e7be4484 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_pwrcu.h @@ -0,0 +1,285 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_pwrcu.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the Power Control Unit library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_PWRCU_H +#define __HT32F1XXXX_PWRCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup PWRCU + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Types PWRCU exported types + * @{ + */ + +/** + * @brief Status of Power control unit + */ +typedef enum +{ + PWRCU_OK = 0, /*!< Ready for access or backup domain power-on reset is released */ + PWRCU_TIMEOUT, /*!< Time out */ + PWRCU_ERROR /*!< Error */ +} PWRCU_Status; +/** + * @brief DMOS status + */ +typedef enum +{ + PWRCU_DMOS_STS_ON = 0, /*!< DMOS on */ + PWRCU_DMOS_STS_OFF, /*!< DMOS off */ + PWRCU_DMOS_STS_OFF_BY_BODRESET /*!< DMOS off caused by brow out reset */ +} PWRCU_DMOSStatus; +/** + * @brief LVD level selection + */ +typedef enum +{ + PWRCU_LVDS_LV1 = 0x00000000, /*!< LVD level 1 */ + PWRCU_LVDS_LV2 = 0x00020000, /*!< LVD level 2 */ + PWRCU_LVDS_LV3 = 0x00040000, /*!< LVD level 3 */ + PWRCU_LVDS_LV4 = 0x00060000, /*!< LVD level 4 */ + PWRCU_LVDS_LV5 = 0x00400000, /*!< LVD level 5 */ + PWRCU_LVDS_LV6 = 0x00420000, /*!< LVD level 6 */ + PWRCU_LVDS_LV7 = 0x00440000, /*!< LVD level 7 */ + PWRCU_LVDS_LV8 = 0x00460000 /*!< LVD level 8 */ +} PWRCU_LVDS_Enum; +#if (LIBCFG_PWRCU_LVDS_27_35) + #define PWRCU_LVDS_2V7 PWRCU_LVDS_LV1 + #define PWRCU_LVDS_2V8 PWRCU_LVDS_LV2 + #define PWRCU_LVDS_2V9 PWRCU_LVDS_LV3 + #define PWRCU_LVDS_3V PWRCU_LVDS_LV4 + #define PWRCU_LVDS_3V1 PWRCU_LVDS_LV5 + #define PWRCU_LVDS_3V2 PWRCU_LVDS_LV6 + #define PWRCU_LVDS_3V4 PWRCU_LVDS_LV7 + #define PWRCU_LVDS_3V5 PWRCU_LVDS_LV8 +#elif (LIBCFG_PWRCU_LVDS_17_31) + #define PWRCU_LVDS_1V75 PWRCU_LVDS_LV1 + #define PWRCU_LVDS_1V95 PWRCU_LVDS_LV2 + #define PWRCU_LVDS_2V15 PWRCU_LVDS_LV3 + #define PWRCU_LVDS_2V35 PWRCU_LVDS_LV4 + #define PWRCU_LVDS_2V55 PWRCU_LVDS_LV5 + #define PWRCU_LVDS_2V75 PWRCU_LVDS_LV6 + #define PWRCU_LVDS_2V95 PWRCU_LVDS_LV7 + #define PWRCU_LVDS_3V15 PWRCU_LVDS_LV8 +#else + #define PWRCU_LVDS_2V25 PWRCU_LVDS_LV1 + #define PWRCU_LVDS_2V4 PWRCU_LVDS_LV2 + #define PWRCU_LVDS_2V55 PWRCU_LVDS_LV3 + #define PWRCU_LVDS_2V7 PWRCU_LVDS_LV4 + #define PWRCU_LVDS_2V85 PWRCU_LVDS_LV5 + #define PWRCU_LVDS_3V PWRCU_LVDS_LV6 + #define PWRCU_LVDS_3V15 PWRCU_LVDS_LV7 + #define PWRCU_LVDS_3V3 PWRCU_LVDS_LV8 +#endif +/** + * @brief BOD reset or interrupt selection + */ +typedef enum +{ + PWRCU_BODRIS_RESET = 0, /*!< Reset the whole chip */ + PWRCU_BODRIS_INT = 1, /*!< Assert interrupt */ +} PWRCU_BODRIS_Enum; +/** + * @brief Sleep entry instruction selection + */ +typedef enum +{ + PWRCU_SLEEP_ENTRY_WFE = 0, /*!< Sleep then wait for event */ + PWRCU_SLEEP_ENTRY_WFI /*!< Sleep then wait for interrupt */ +} PWRCU_SLEEP_ENTRY_Enum; +#if (!LIBCFG_NO_BACK_DOMAIN) +/** + * @brief Backup register selection + */ +typedef enum +{ + PWRCU_BAKREG_0 = 0, + PWRCU_BAKREG_1, + PWRCU_BAKREG_2, + PWRCU_BAKREG_3, + PWRCU_BAKREG_4, + PWRCU_BAKREG_5, + PWRCU_BAKREG_6, + PWRCU_BAKREG_7, + PWRCU_BAKREG_8, + PWRCU_BAKREG_9 +} PWRCU_BAKREG_Enum; +#endif +/** + * @brief Vdd18/Vdd15 power good source selection + */ +typedef enum +{ + PWRCU_VRDYSC_BKISO = 0, /*!< Vdd18/Vdd15 power good source come from BK_ISO bit in CKCU unit */ + PWRCU_VRDYSC_VPOR /*!< Vdd18/Vdd15 power good source come from Vdd18 power on reset */ +} PWRCU_VRDYSC_Enum; +#if (!LIBCFG_PWRCU_LDO_LEGACY) +/** + * @brief LDO operation mode selection + */ +typedef enum +{ + PWRCU_LDO_NORMAL = 0, /*!< The LDO is operated in normal current mode */ + PWRCU_LDO_LOWCURRENT /*!< The LDO is operated in low current mode */ +} PWRCU_LDOMODE_Enum; +/** + * @brief LDO output offset selection + */ +typedef enum +{ + PWRCU_LDO_DEFAULT = 0x00000000, /*!< The LDO default output voltage */ + PWRCU_LDO_OFFSET_DEC5P = 0x00000010, /*!< The LDO default output voltage offset -5% */ + PWRCU_LDO_OFFSET_ADD3P = 0x00000020, /*!< The LDO default output voltage offset +3% */ + PWRCU_LDO_OFFSET_ADD7P = 0x00000030, /*!< The LDO default output voltage offset +7% */ +} PWRCU_LDOFTRM_Enum; +#endif +/** + * @brief HSI ready counter bit length selection + */ +typedef enum +{ + PWRCU_HSIRCBL_4 = 0, /*!< 4 bits */ + PWRCU_HSIRCBL_5, /*!< 5 bits */ + PWRCU_HSIRCBL_6, /*!< 5 bits */ + PWRCU_HSIRCBL_7 /*!< 7 bits (Default) */ +} PWRCU_HSIRCBL_Enum; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Constants PWRCU exported constants + * @{ + */ + +/* Definitions of PWRCU_FLAG */ +#define PWRCU_FLAG_PWRPOR 0x0001 /*!< Backup domain power-on reset flag */ +#define PWRCU_FLAG_PD 0x0002 /*!< Power-Down flag */ +#define PWRCU_FLAG_WUP 0x0100 /*!< External WAKEUP pin flag */ + +#define PWRCU_FLAG_BAKPOR PWRCU_FLAG_PWRPOR + +/* check PWRCU_LVDS parameter */ +#define IS_PWRCU_LVDS(x) ((x == PWRCU_LVDS_LV1) || (x == PWRCU_LVDS_LV2) || \ + (x == PWRCU_LVDS_LV3) || (x == PWRCU_LVDS_LV4) || \ + (x == PWRCU_LVDS_LV5) || (x == PWRCU_LVDS_LV6) || \ + (x == PWRCU_LVDS_LV7) || (x == PWRCU_LVDS_LV8)) + +/* check PWRCU_BODRIS parameter */ +#define IS_PWRCU_BODRIS(x) ((x == PWRCU_BODRIS_RESET) || (x == PWRCU_BODRIS_INT)) + +/* check PWRCU_HSIRCBL parameter */ +#define IS_PWRCU_HSIRCBL(x) (x <= 3) + +/* check PWRCU_SLEEP_ENTRY parameter */ +#define IS_PWRCU_SLEEP_ENTRY(x) ((x == PWRCU_SLEEP_ENTRY_WFI) || (x == PWRCU_SLEEP_ENTRY_WFE)) + +/* check PWRCU_BAKREG parameter */ +#define IS_PWRCU_BAKREG(x) (x < 10) + +/* check PWRCU_VRDY_SRC parameter */ +#define IS_PWRCU_VRDYSC(x) ((x == PWRCU_VRDYSC_BKISO) || (x == PWRCU_VRDYSC_VPOR)) + +#if (!LIBCFG_PWRCU_LDO_LEGACY) +/* check PWRCU_LDOMODE parameter */ +#define IS_PWRCU_LDOMODE(x) ((x == PWRCU_LDO_NORMAL) || (x == PWRCU_LDO_LOWCURRENT)) +#if (!LIBCFG_NO_PWRCU_LDO_CFG_VOLTAGE) +/* check PWRCU_LDOFTRM parameter */ +#define IS_PWRCU_LDOFTRM(x) ((x == PWRCU_LDO_DEFAULT) || (x == PWRCU_LDO_OFFSET_DEC5P) || \ + (x == PWRCU_LDO_OFFSET_ADD3P) || (x == PWRCU_LDO_OFFSET_ADD7P)) +#endif +#endif +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Functions PWRCU exported functions + * @{ + */ +void PWRCU_DeInit(void); +PWRCU_Status PWRCU_CheckReadyAccessed(void); +u16 PWRCU_GetFlagStatus(void); +#if (!LIBCFG_NO_BACK_DOMAIN) +u32 PWRCU_ReadBackupRegister(PWRCU_BAKREG_Enum BAKREGx); +void PWRCU_WriteBackupRegister(PWRCU_BAKREG_Enum BAKREGx, u32 DATA); +#endif +void PWRCU_Sleep(PWRCU_SLEEP_ENTRY_Enum SleepEntry); +void PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_Enum SleepEntry); +void PWRCU_DeepSleep2(PWRCU_SLEEP_ENTRY_Enum SleepEntry); +void PWRCU_PowerDown(void); +void PWRCU_SetLVDS(PWRCU_LVDS_Enum Level); +#if (!LIBCFG_PWRCU_LDO_LEGACY) +void PWRCU_SetLDOFTRM(PWRCU_LDOFTRM_Enum VolOffset); +void PWRCU_LDOConfig(PWRCU_LDOMODE_Enum Sel); +#endif +void PWRCU_LVDCmd(ControlStatus NewState); +void PWRCU_BODCmd(ControlStatus NewState); +void PWRCU_BODRISConfig(PWRCU_BODRIS_Enum Selection); +FlagStatus PWRCU_GetLVDFlagStatus(void); +FlagStatus PWRCU_GetBODFlagStatus(void); +PWRCU_DMOSStatus PWRCU_GetDMOSStatus(void); +void PWRCU_DMOSCmd(ControlStatus NewState); +void PWRCU_VRDYSourceConfig(PWRCU_VRDYSC_Enum Sel); +void PWRCU_LVDIntWakeupConfig(ControlStatus NewState); +void PWRCU_LVDEventWakeupConfig(ControlStatus NewState); +void PWRCU_WakeupPinCmd(ControlStatus NewState); +void PWRCU_WakeupPinIntConfig(ControlStatus NewState); +void PWRCU_HSIReadyCounterBitLengthConfig(PWRCU_HSIRCBL_Enum BitLength); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rstcu.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rstcu.h new file mode 100644 index 00000000000..c6870ab8bf1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rstcu.h @@ -0,0 +1,266 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_rstcu.h + * @version $Rev:: 2973 $ + * @date $Date:: 2023-10-30 #$ + * @brief The header file of the Reset Control Unit library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_RSTCU_H +#define __HT32F1XXXX_RSTCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup RSTCU + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Types RSTCU exported types + * @{ + */ + +/** + * @brief Enumeration of Global reset status. + */ +typedef enum +{ + RSTCU_FLAG_SYSRST = 0, + RSTCU_FLAG_EXTRST, + RSTCU_FLAG_WDTRST, + RSTCU_FLAG_PORST +} RSTCU_RSTF_TypeDef; + +/** + * @brief Definition of initial structure of peripheral reset. + */ +typedef union +{ + struct + { + /* Definitions of AHB peripheral reset */ + unsigned long PDMA :1; // Bit 0 + unsigned long :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 +#if (LIBCFG_CSIF) + unsigned long CSIF :1; // Bit 4 +#else + unsigned long :1; // Bit 4 +#endif + unsigned long USBD :1; // Bit 5 + unsigned long EBI :1; // Bit 6 + unsigned long CRC :1; // Bit 7 + + unsigned long PA :1; // Bit 8 + unsigned long PB :1; // Bit 9 + unsigned long PC :1; // Bit 10 + unsigned long PD :1; // Bit 11 +#if (LIBCFG_GPIOE) + unsigned long PE :1; // Bit 12 +#else + unsigned long :1; // Bit 12 +#endif +#if (LIBCFG_GPIOF) + unsigned long PF :1; // Bit 13 +#else + unsigned long :1; // Bit 13 +#endif +#if (LIBCFG_SDIO) + unsigned long SDIO :1; // Bit 14 +#else + unsigned long :1; // Bit 14 +#endif +#if (LIBCFG_AES) + unsigned long AES :1; // Bit 15 +#else + unsigned long :1; // Bit 15 +#endif + + unsigned long :1; // Bit 16 + unsigned long :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 + unsigned long :1; // Bit 22 + unsigned long :1; // Bit 23 + + unsigned long :1; // Bit 24 + unsigned long :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long :1; // Bit 28 + unsigned long :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB peripheral 0 reset */ + unsigned long I2C0 :1; // Bit 0 + unsigned long I2C1 :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long SPI0 :1; // Bit 4 + unsigned long SPI1 :1; // Bit 5 + unsigned long :1; // Bit 6 + unsigned long :1; // Bit 7 + + unsigned long USART0 :1; // Bit 8 + unsigned long USART1 :1; // Bit 9 + unsigned long UART0 :1; // Bit 10 + unsigned long UART1 :1; // Bit 11 + unsigned long :1; // Bit 12 + unsigned long :1; // Bit 13 + unsigned long AFIO :1; // Bit 14 + unsigned long EXTI :1; // Bit 15 + + unsigned long :1; // Bit 16 + unsigned long :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 + unsigned long :1; // Bit 22 + unsigned long :1; // Bit 23 + +#if (LIBCFG_SCI0) + unsigned long SCI0 :1; // Bit 24 +#else + unsigned long :1; // Bit 24 +#endif + unsigned long I2S :1; // Bit 25 + unsigned long :1; // Bit 26 +#if (LIBCFG_SCI1) + unsigned long SCI1 :1; // Bit 27 +#else + unsigned long :1; // Bit 27 +#endif + unsigned long :1; // Bit 28 + unsigned long :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB peripheral 1 reset */ + unsigned long MCTM0 :1; // Bit 0 + unsigned long MCTM1 :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long WDT :1; // Bit 4 + unsigned long :1; // Bit 5 + unsigned long :1; // Bit 6 + unsigned long :1; // Bit 7 + + unsigned long GPTM0 :1; // Bit 8 + unsigned long GPTM1 :1; // Bit 9 + unsigned long :1; // Bit 10 + unsigned long :1; // Bit 11 + unsigned long PWM0 :1; // Bit 12 + unsigned long :1; // Bit 13 + unsigned long :1; // Bit 14 + unsigned long :1; // Bit 15 + + unsigned long BFTM0 :1; // Bit 16 + unsigned long BFTM1 :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 +#if (LIBCFG_CMP_OPA) + unsigned long OPA0 :1; // Bit 22 +#else + unsigned long CMP :1; // Bit 22 +#endif +#if (LIBCFG_CMP_OPA) + unsigned long OPA1 :1; // Bit 23 +#else + unsigned long :1; // Bit 23 +#endif + + unsigned long ADC0 :1; // Bit 24 + unsigned long :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long SCTM0 :1; // Bit 28 + unsigned long SCTM1 :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + } Bit; + u32 Reg[3]; +} RSTCU_PeripReset_TypeDef; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Constants RSTCU exported constants + * @{ + */ + +/* Other definitions */ +#define IS_RSTCU_FLAG(FLAG) ((FLAG == RSTCU_FLAG_SYSRST) || \ + (FLAG == RSTCU_FLAG_EXTRST) || \ + (FLAG == RSTCU_FLAG_WDTRST) || \ + (FLAG == RSTCU_FLAG_PORST)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Functions RSTCU exported functions + * @{ + */ +FlagStatus RSTCU_GetResetFlagStatus(RSTCU_RSTF_TypeDef RSTCU_RSTF); +void RSTCU_ClearResetFlag(RSTCU_RSTF_TypeDef RSTCU_RSTF); +void RSTCU_ClearAllResetFlag(void); +void RSTCU_PeripReset(RSTCU_PeripReset_TypeDef Reset, ControlStatus Cmd); + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rtc.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rtc.h new file mode 100644 index 00000000000..f2e50b49f9b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_rtc.h @@ -0,0 +1,245 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_rtc.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the RTC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_RTC_H +#define __HT32F1XXXX_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Types RTC exported types + * @{ + */ + +/** + * @brief Selection of RTC clock source + */ +typedef enum +{ + RTC_SRC_LSI = 0, /*!< Low speed internal clock, about 32 kHz */ + RTC_SRC_LSE /*!< Low speed external 32768 Hz clock */ +} RTC_SRC_Enum; +/** + * @brief Selection of RTC LSE startup mode + */ +typedef enum +{ + RTC_LSESM_NORMAL = 0, /*!< Little power consumption but longer startup time. */ + RTC_LSESM_FAST /*!< Shortly startup time but higher power consumption. */ +} RTC_LSESM_Enum; +/** + * @brief Selection of RTC prescaler + */ +typedef enum +{ + RTC_RPRE_1 = 0x0000, /*!< CK_SECOND = CK_RTC */ + RTC_RPRE_2 = 0x0100, /*!< CK_SECOND = CK_RTC / 2 */ + RTC_RPRE_4 = 0x0200, /*!< CK_SECOND = CK_RTC / 4 */ + RTC_RPRE_8 = 0x0300, /*!< CK_SECOND = CK_RTC / 8 */ + RTC_RPRE_16 = 0x0400, /*!< CK_SECOND = CK_RTC / 16 */ + RTC_RPRE_32 = 0x0500, /*!< CK_SECOND = CK_RTC / 32 */ + RTC_RPRE_64 = 0x0600, /*!< CK_SECOND = CK_RTC / 64 */ + RTC_RPRE_128 = 0x0700, /*!< CK_SECOND = CK_RTC / 128 */ + RTC_RPRE_256 = 0x0800, /*!< CK_SECOND = CK_RTC / 256 */ + RTC_RPRE_512 = 0x0900, /*!< CK_SECOND = CK_RTC / 512 */ + RTC_RPRE_1024 = 0x0A00, /*!< CK_SECOND = CK_RTC / 1024 */ + RTC_RPRE_2048 = 0x0B00, /*!< CK_SECOND = CK_RTC / 2048 */ + RTC_RPRE_4096 = 0x0C00, /*!< CK_SECOND = CK_RTC / 4096 */ + RTC_RPRE_8192 = 0x0D00, /*!< CK_SECOND = CK_RTC / 8192 */ + RTC_RPRE_16384 = 0x0E00, /*!< CK_SECOND = CK_RTC / 16384 */ + RTC_RPRE_32768 = 0x0F00 /*!< CK_SECOND = CK_RTC / 32768 */ +} RTC_RPRE_Enum; +/** + * @brief Active polarity of RTC output + */ +typedef enum +{ + RTC_ROAP_HIGH = 0, /*!< Active level is high */ + RTC_ROAP_LOW /*!< Active level is low */ +} RTC_ROAP_Enum; +/** + * @brief Waveform mode of RTC output + */ +typedef enum +{ + RTC_ROWM_PULSE = 0, /*!< Pulse mode. */ + RTC_ROWM_LEVEL /*!< Level mode. */ +} RTC_ROWM_Enum; +/** + * @brief Waveform mode of RTC output + */ +typedef enum +{ + RTC_ROES_MATCH = 0, /*!< Selected RTC compare match. */ + RTC_ROES_SECOND /*!< Selected RTC second clock. */ +} RTC_ROES_Enum; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Constants RTC exported constants + * @{ + */ + +/** @defgroup RTC_WAKEUP Selection of RTC wakeup source + * @{ + */ +#define RTC_WAKEUP_CSEC 0x00000100 +#define RTC_WAKEUP_CM 0x00000200 +#define RTC_WAKEUP_OV 0x00000400 +/** + * @} + */ + +/** @defgroup RTC_IT RTC Selection of interrupt source + * @{ + */ +#define RTC_INT_CSEC 0x00000001 +#define RTC_INT_CM 0x00000002 +#define RTC_INT_OV 0x00000004 +/** + * @} + */ + +/** @defgroup RTC_FLAG RTC Definitions of flags + * @{ + */ +#define RTC_FLAG_CSEC 0x00000001 +#define RTC_FLAG_CM 0x00000002 +#define RTC_FLAG_OV 0x00000004 +/** + * @} + */ + +/** @defgroup RTC_Check_Parameter Selection of Vdd18 power good + * @{ + */ + +/** + * @brief Used to check RTC_SRC_Enum parameter + */ +#define IS_RTC_SRC(x) ((x == RTC_SRC_LSI) || (x == RTC_SRC_LSE)) +/** + * @brief Used to check RTC_LSESM_Enum parameter + */ +#define IS_RTC_LSESM(x) ((x == RTC_LSESM_NORMAL) || (x == RTC_LSESM_FAST)) +/** + * @brief Used to check RTC_RPRE_Enum parameter + */ +#define IS_RTC_PSC(x) ((x == RTC_RPRE_1) || (x == RTC_RPRE_2) || (x == RTC_RPRE_4) ||\ + (x == RTC_RPRE_8) || (x == RTC_RPRE_16) || (x == RTC_RPRE_32) ||\ + (x == RTC_RPRE_64) || (x == RTC_RPRE_128) || (x == RTC_RPRE_256) ||\ + (x == RTC_RPRE_512) || (x == RTC_RPRE_1024) || (x == RTC_RPRE_2048) ||\ + (x == RTC_RPRE_4096) || (x == RTC_RPRE_8192) || (x == RTC_RPRE_16384) ||\ + (x == RTC_RPRE_32768)) +/** + * @brief Used to check RTC_ROAP_Enum parameter + */ +#define IS_RTC_ROAP(x) ((x == RTC_ROAP_HIGH) || (x == RTC_ROAP_LOW)) +/** + * @brief Used to check RTC_ROWM_Enum parameter + */ +#define IS_RTC_ROWM(x) ((x == RTC_ROWM_PULSE) || (x == RTC_ROWM_LEVEL)) +/** + * @brief Used to check RTC_ROES_Enum parameter + */ +#define IS_RTC_ROES(x) ((x == RTC_ROES_MATCH) || (x == RTC_ROES_SECOND)) +/** + * @brief Used to check RTC_WAKEUP parameter + */ +#define IS_RTC_WAKEUP(x) ((((x) & (u32)0xFFFFF8FF) == 0x00) && ((x) != 0x00)) +/** + * @brief Used to check RTC_INT parameter + */ +#define IS_RTC_INT(x) ((((x) & (u32)0xFFFFFFF8) == 0x00) && ((x) != 0x00)) +/** + * @brief Used to check RTC_FLAG parameter + */ +#define IS_RTC_FLAG(x) ((((x) & (u32)0xFFFFFFF8) == 0x00) && ((x) != 0x00)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC exported functions + * @{ + */ +void RTC_DeInit(void); +void RTC_ClockSourceConfig(RTC_SRC_Enum Source); +void RTC_LSESMConfig(RTC_LSESM_Enum Mode); +void RTC_LSECmd(ControlStatus NewState); +void RTC_CMPCLRCmd(ControlStatus NewState); +void RTC_SetPrescaler(RTC_RPRE_Enum Psc); +u16 RTC_GetPrescaler(void); +void RTC_Cmd(ControlStatus NewState); +u32 RTC_GetCounter(void); +void RTC_SetCompare(u32 Compare); +u32 RTC_GetCompare(void); +void RTC_WakeupConfig(u32 RTC_WAKEUP, ControlStatus NewState); +void RTC_IntConfig(u32 RTC_INT, ControlStatus NewState); +u8 RTC_GetFlagStatus(void); +void RTC_OutConfig(RTC_ROWM_Enum WMode, RTC_ROES_Enum EventSel, RTC_ROAP_Enum Pol); +void RTC_OutCmd(ControlStatus NewState); +FlagStatus RTC_GetOutStatus(void); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_sci.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_sci.h new file mode 100644 index 00000000000..7118c1c42cc --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_sci.h @@ -0,0 +1,278 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_sci.h + * @version $Rev:: 122 $ + * @date $Date:: 2017-06-13 #$ + * @brief The header file of the SCI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_SCI_H +#define __HT32F1XXXX_SCI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup SCI + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Types SCI exported types + * @{ + */ +typedef struct +{ + u32 SCI_Mode; + u32 SCI_Retry; + u32 SCI_Convention; + u32 SCI_CardPolarity; + u32 SCI_ClockPrescale; +} SCI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Constants SCI exported constants + * @{ + */ +#define SCI_MODE_MANUAL ((u32)0x00000000) +#define SCI_MODE_SCI ((u32)0x00000008) + +#define IS_SCI_MODE(MODE) ((MODE == SCI_MODE_MANUAL) || \ + (MODE == SCI_MODE_SCI)) + + +#define SCI_RETRY_NO ((u32)0x00000000) +#define SCI_RETRY_4 ((u32)0x00000012) +#define SCI_RETRY_5 ((u32)0x00000002) + +#define IS_SCI_RETRY(RETRY) ((RETRY == SCI_RETRY_NO) || \ + (RETRY == SCI_RETRY_4) || \ + (RETRY == SCI_RETRY_5)) + + +#define SCI_CONVENTION_DIRECT ((u32)0x00000000) +#define SCI_CONVENTION_INVERSE ((u32)0x00000001) + +#define IS_SCI_CONVENTION(CONVENTION) ((CONVENTION == SCI_CONVENTION_DIRECT) || \ + (CONVENTION == SCI_CONVENTION_INVERSE)) + + +#define SCI_CARDPOLARITY_LOW ((u32)0x00000000) +#define SCI_CARDPOLARITY_HIGH ((u32)0x00000040) + +#define IS_SCI_CARD_POLARITY(POLARITY) ((POLARITY == SCI_CARDPOLARITY_LOW) || \ + (POLARITY == SCI_CARDPOLARITY_HIGH)) + + +#define SCI_CLKPRESCALER_1 ((u32)0x00000000) +#define SCI_CLKPRESCALER_2 ((u32)0x00000001) +#define SCI_CLKPRESCALER_4 ((u32)0x00000002) +#define SCI_CLKPRESCALER_6 ((u32)0x00000003) +#define SCI_CLKPRESCALER_8 ((u32)0x00000004) +#define SCI_CLKPRESCALER_10 ((u32)0x00000005) +#define SCI_CLKPRESCALER_12 ((u32)0x00000006) +#define SCI_CLKPRESCALER_14 ((u32)0x00000007) +#define SCI_CLKPRESCALER_16 ((u32)0x00000008) +#define SCI_CLKPRESCALER_18 ((u32)0x00000009) +#define SCI_CLKPRESCALER_20 ((u32)0x0000000A) +#define SCI_CLKPRESCALER_22 ((u32)0x0000000B) +#define SCI_CLKPRESCALER_24 ((u32)0x0000000C) +#define SCI_CLKPRESCALER_26 ((u32)0x0000000D) +#define SCI_CLKPRESCALER_28 ((u32)0x0000000E) +#define SCI_CLKPRESCALER_30 ((u32)0x0000000F) +#define SCI_CLKPRESCALER_32 ((u32)0x00000010) +#define SCI_CLKPRESCALER_34 ((u32)0x00000011) +#define SCI_CLKPRESCALER_36 ((u32)0x00000012) +#define SCI_CLKPRESCALER_38 ((u32)0x00000013) +#define SCI_CLKPRESCALER_40 ((u32)0x00000014) +#define SCI_CLKPRESCALER_42 ((u32)0x00000015) +#define SCI_CLKPRESCALER_44 ((u32)0x00000016) +#define SCI_CLKPRESCALER_46 ((u32)0x00000017) +#define SCI_CLKPRESCALER_48 ((u32)0x00000018) +#define SCI_CLKPRESCALER_50 ((u32)0x00000019) +#define SCI_CLKPRESCALER_52 ((u32)0x0000001A) +#define SCI_CLKPRESCALER_54 ((u32)0x0000001B) +#define SCI_CLKPRESCALER_56 ((u32)0x0000001C) +#define SCI_CLKPRESCALER_58 ((u32)0x0000001D) +#define SCI_CLKPRESCALER_60 ((u32)0x0000001E) +#define SCI_CLKPRESCALER_62 ((u32)0x0000001F) +#define SCI_CLKPRESCALER_64 ((u32)0x00000020) +#define SCI_CLKPRESCALER_66 ((u32)0x00000021) +#define SCI_CLKPRESCALER_68 ((u32)0x00000022) +#define SCI_CLKPRESCALER_70 ((u32)0x00000023) +#define SCI_CLKPRESCALER_72 ((u32)0x00000024) +#define SCI_CLKPRESCALER_74 ((u32)0x00000025) +#define SCI_CLKPRESCALER_76 ((u32)0x00000026) +#define SCI_CLKPRESCALER_78 ((u32)0x00000027) +#define SCI_CLKPRESCALER_80 ((u32)0x00000028) +#define SCI_CLKPRESCALER_82 ((u32)0x00000029) +#define SCI_CLKPRESCALER_84 ((u32)0x0000002A) +#define SCI_CLKPRESCALER_86 ((u32)0x0000002B) +#define SCI_CLKPRESCALER_88 ((u32)0x0000002C) +#define SCI_CLKPRESCALER_90 ((u32)0x0000002D) +#define SCI_CLKPRESCALER_92 ((u32)0x0000002E) +#define SCI_CLKPRESCALER_94 ((u32)0x0000002F) +#define SCI_CLKPRESCALER_96 ((u32)0x00000030) +#define SCI_CLKPRESCALER_98 ((u32)0x00000031) +#define SCI_CLKPRESCALER_100 ((u32)0x00000032) +#define SCI_CLKPRESCALER_102 ((u32)0x00000033) +#define SCI_CLKPRESCALER_104 ((u32)0x00000034) +#define SCI_CLKPRESCALER_106 ((u32)0x00000035) +#define SCI_CLKPRESCALER_108 ((u32)0x00000036) +#define SCI_CLKPRESCALER_110 ((u32)0x00000037) +#define SCI_CLKPRESCALER_112 ((u32)0x00000038) +#define SCI_CLKPRESCALER_114 ((u32)0x00000039) +#define SCI_CLKPRESCALER_116 ((u32)0x0000003A) +#define SCI_CLKPRESCALER_118 ((u32)0x0000003B) +#define SCI_CLKPRESCALER_120 ((u32)0x0000003C) +#define SCI_CLKPRESCALER_122 ((u32)0x0000003D) +#define SCI_CLKPRESCALER_124 ((u32)0x0000003E) +#define SCI_CLKPRESCALER_126 ((u32)0x0000003F) + +#define IS_SCI_CLOCK_PRESCALER(PRESCALER) (PRESCALER <= 0x3F) + + +#define SCI_COMPENSATION_ENABLE ((u32)0x00008000) +#define SCI_COMPENSATION_DISABLE ((u32)0x00000000) + +#define IS_SCI_ETU_COMPENSATION(COMPENSATION) ((COMPENSATION == SCI_COMPENSATION_ENABLE) || \ + (COMPENSATION == SCI_COMPENSATION_DISABLE)) + + +#define SCI_CLK_HARDWARE ((u32)0x00000080) +#define SCI_CLK_SOFTWARE ((u32)0xFFFFFF7F) + +#define IS_SCI_CLK_MODE(MODE) ((MODE == SCI_CLK_HARDWARE) || \ + (MODE == SCI_CLK_SOFTWARE)) + + +#define SCI_CLK_HIGH ((u32)0x00000004) +#define SCI_CLK_LOW ((u32)0xFFFFFFFB) + +#define IS_SCI_CLK(CLK) ((CLK == SCI_CLK_HIGH) || \ + (CLK == SCI_CLK_LOW)) + + +#define SCI_DIO_HIGH ((u32)0x00000008) +#define SCI_DIO_LOW ((u32)0xFFFFFFF7) + +#define IS_SCI_DIO(DIO) ((DIO == SCI_DIO_HIGH) || \ + (DIO == SCI_DIO_LOW)) + + +#define SCI_INT_PAR ((u32)0x00000001) +#define SCI_INT_RXC ((u32)0x00000002) +#define SCI_INT_TXC ((u32)0x00000004) +#define SCI_INT_WT ((u32)0x00000008) +#define SCI_INT_CARD ((u32)0x00000040) +#define SCI_INT_TXBE ((u32)0x00000080) +#define SCI_INT_ALL ((u32)0x000000CF) + +#define IS_SCI_INT(INT) (((INT & 0xFFFFFF30) == 0x0) && (INT != 0)) + + + +#define SCI_FLAG_PAR ((u32)0x00000001) +#define SCI_FLAG_RXC ((u32)0x00000002) +#define SCI_FLAG_TXC ((u32)0x00000004) +#define SCI_FLAG_WT ((u32)0x00000008) +#define SCI_FLAG_CARD ((u32)0x00000040) +#define SCI_FLAG_TXBE ((u32)0x00000080) + +#define IS_SCI_FLAG(FLAG) ((FLAG == SCI_FLAG_PAR) || \ + (FLAG == SCI_FLAG_RXC) || \ + (FLAG == SCI_FLAG_TXC) || \ + (FLAG == SCI_FLAG_WT) || \ + (FLAG == SCI_FLAG_CARD) || \ + (FLAG == SCI_FLAG_TXBE)) + +#define IS_SCI_CLEAR_FLAG(FLAG) ((FLAG == SCI_FLAG_PAR) || \ + (FLAG == SCI_FLAG_TXC) || \ + (FLAG == SCI_FLAG_WT)) + + +#define SCI_PDMAREQ_TX ((u32)0x00000100) +#define SCI_PDMAREQ_RX ((u32)0x00000200) + +#define IS_SCI_PDMA_REQ(REQ) (((REQ & 0xFFFFFCFF) == 0x0) && (REQ != 0)) + + +#define IS_SCI_ETU(ETU) ((ETU >= 12) & (ETU <= 2047)) + +#define IS_SCI_GUARDTIME(GUARDTIME) ((GUARDTIME >= 11) & (GUARDTIME <= 511)) + +#define IS_SCI_WAITING_TIME(TIME) ((TIME >= 372) & (TIME <= 16777215)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Functions SCI exported functions + * @{ + */ +void SCI_DeInit(HT_SCI_TypeDef* SCIx); +void SCI_Init(HT_SCI_TypeDef* SCIx, SCI_InitTypeDef* SCI_InitStruct); +void SCI_StructInit(SCI_InitTypeDef* SCI_InitStruct); +void SCI_Cmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState); +void SCI_ETUConfig(HT_SCI_TypeDef* SCIx, u32 SCI_ETU, u32 SCI_Compensation); +void SCI_SetGuardTimeValue(HT_SCI_TypeDef* SCIx, u16 SCI_GuardTime); +void SCI_SetWaitingTimeValue(HT_SCI_TypeDef* SCIx, u32 SCI_WaitingTime); +void SCI_WaitingTimeCounterCmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState); +void SCI_SendData(HT_SCI_TypeDef* SCIx, u8 SCI_Data); +u8 SCI_ReceiveData(HT_SCI_TypeDef* SCIx); +void SCI_ClockModeConfig(HT_SCI_TypeDef* SCIx, u32 SCI_CLKMode); +void SCI_SoftwareClockCmd(HT_SCI_TypeDef* SCIx, u32 SCI_CLK); +void SCI_OutputDIO(HT_SCI_TypeDef* SCIx, u32 SCI_DIO); +void SCI_IntConfig(HT_SCI_TypeDef* SCIx, u32 SCI_Int, ControlStatus NewState); +FlagStatus SCI_GetFlagStatus(HT_SCI_TypeDef* SCIx, u32 SCI_Flag); +void SCI_ClearFlag(HT_SCI_TypeDef* SCIx, u32 SCI_Flag); +void SCI_PDMACmd(HT_SCI_TypeDef* SCIx, u32 SCI_PDMAREQ, ControlStatus NewState); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_sdio.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_sdio.h new file mode 100644 index 00000000000..4a62ce7db4c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_sdio.h @@ -0,0 +1,413 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_sdio.h + * @version $Rev:: 2458 $ + * @date $Date:: 2021-08-05 #$ + * @brief The header file of the SDIO library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_SDIO_H +#define __HT32F1XXXX_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Types SDIO exported types + * @{ + */ +typedef struct +{ + u32 SDIO_ClockDiv; /*!< Specify the SDIO clock divider value. + This parameter can be a value between 1 and 256. */ + + u32 SDIO_ClockPeriod; /*!< Specify whether SDIO clock has longer or shorter low period + when the SDIO clock divider value is odd. + This parameter can be a value of @ref SDIO_Clock_Period */ + + u32 SDIO_ClockPowerSave; /*!< Specify whether SDIO clock output is enabled or disabled + when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + u32 SDIO_BusWide; /*!< Specify the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + u32 SDIO_BusMode; /*!< Specify the SDIO bus Mode. + This parameter can be a value of @ref SDIO_Bus_Mode */ +} SDIO_InitTypeDef; + + +typedef struct +{ + u32 SDIO_Argument; /*!< Specify the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + u32 SDIO_CmdIndex; /*!< Specify the SDIO command index. It must be lower than 0x40. */ + + u32 SDIO_Response; /*!< Specify the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + u32 SDIO_DatPresent; /*!< Specify whether data is present on the SDIO data line + after SDIO command or not. + This parameter can be a value of @ref SDIO_Data_Present */ + + u32 SDIO_CmdIdxChk; /*!< Specify whether SDIO command index check function is enabled or not. + This parameter can be a value of @ref SDIO_CmdIdx_Check */ + + u32 SDIO_CmdCrcChk; /*!< Specify whether SDIO command CRC check function is enabled or not. + This parameter can be a value of @ref SDIO_CmdCrc_Check */ +} SDIO_CmdInitTypeDef; + + +typedef struct +{ + u32 SDIO_DataBlockCount; /*!< Specify the number of data block count to be transferred. + This parameter can be a value between 1 and 65535. */ + + u32 SDIO_DataBlockSize; /*!< Specify the data block size for block transfer. + This parameter can be a value between 1 and 2048. */ + + u32 SDIO_TransferDir; /*!< Specify the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + u32 SDIO_TransferMode; /*!< Specify whether data transfer is in single block or multi-block mode. + This parameter can be a value of @ref SDIO_Transfer_Mode */ + + u32 SDIO_DataTimeOut; /*!< Specify the data timeout period in card bus clock periods. + This parameter can be a value between 0x1 and 0x00ffffff. */ + +} SDIO_DataInitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Constants SDIO exported constants + * @{ + */ + +/** @defgroup SDIO_Clock_Div SDIO Clock Div + * @{ + */ +#define IS_SDIO_CLOC_DIV(DIV) ((DIV > 0) && (DIV < 256)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Period SDIO Clock Period + * @{ + */ +#define SDIO_Clock_LowPeriod_Shorter (0x00000000) +#define SDIO_Clock_LowPeriod_Longer (0x00000008) + +#define IS_SDIO_CLOCK_PERIOD(PERIOD) (((PERIOD) == SDIO_Clock_LowPeriod_Shorter) || \ + ((PERIOD) == SDIO_Clock_LowPeriod_Longer)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Power_Save SDIO Clock Power Save + * @{ + */ +#define SDIO_Clock_PowerSave_Disable (0x00000000) +#define SDIO_Clock_PowerSave_StopLow (0x00000002) +#define SDIO_Clock_PowerSave_StopHigh (0x00000003) + +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_Clock_PowerSave_Disable) || \ + ((SAVE) == SDIO_Clock_PowerSave_StopLow) || \ + ((SAVE) == SDIO_Clock_PowerSave_StopHigh)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Wide SDIO Bus Wide + * @{ + */ +#define SDIO_BusWide_1b (0x00000000) +#define SDIO_BusWide_4b (0x00000002) + +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || \ + ((WIDE) == SDIO_BusWide_4b)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Mode SDIO Bus Mode + * @{ + */ +#define SDIO_BusMode_NormalSpeed (0x00000000) +#define SDIO_BusMode_HighSpeed (0x00000004) + +#define IS_SDIO_BUS_MODE(MODE) (((MODE) == SDIO_BusMode_NormalSpeed) || \ + ((MODE) == SDIO_BusMode_HighSpeed)) +/** + * @} + */ + +/** @defgroup SDIO_Command_Index SDIO Command Index + * @{ + */ +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @defgroup SDIO_Response_Type SDIO Response Type + * @{ + */ +#define SDIO_Response_No (0x00000000) +#define SDIO_Response_Long (0x00000001) +#define SDIO_Response_Short (0x00000002) + +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Present SDIO Data Present + * @{ + */ +#define SDIO_Data_Present_No (0x00000000) +#define SDIO_Data_Present_Yes (0x00000020) + +#define IS_SDIO_DATA_PRESENT(PRESENT) (((PRESENT) == SDIO_Data_Present_No) || \ + ((PRESENT) == SDIO_Data_Present_Yes)) +/** + * @} + */ + +/** @defgroup SDIO_CmdIdx_Check SDIO CmdIdx Check + * @{ + */ +#define SDIO_CmdIdxChk_No (0x00000000) +#define SDIO_CmdIdxChk_Yes (0x00000010) + +#define IS_SDIO_CMD_IDX_CHK(CHK) (((CHK) == SDIO_CmdIdxChk_No) || \ + ((CHK) == SDIO_CmdIdxChk_Yes)) +/** + * @} + */ + +/** @defgroup SDIO_CmdCrc_Check SDIO CmdCrc Check + * @{ + */ +#define SDIO_CmdCrcChk_No (0x00000000) +#define SDIO_CmdCrcChk_Yes (0x00000008) + +#define IS_SDIO_CMD_CRC_CHK(CHK) (((CHK) == SDIO_CmdCrcChk_No) || \ + ((CHK) == SDIO_CmdCrcChk_Yes)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Count SDIO Data Block Count + * @{ + */ +#define IS_SDIO_DATA_BLOCK_COUNT(COUNT) ((COUNT > 0) && (COUNT <= 65535)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Size SDIO Data Block Size + * @{ + */ +#define IS_SDIO_DATA_BLOCK_SIZE(SIZE) ((SIZE > 0) && (SIZE <= 2048)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Mode SDIO Transfer Mode + * @{ + */ +#define SDIO_SingleBlock_Transfer (0x00000000) +#define SDIO_MultiBlock_Transfer (0x00000022) +#define SDIO_SingleBlock_DMA_Transfer (0x00000100) +#define SDIO_MultiBlock_DMA_Transfer (0x00000122) + +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_SingleBlock_Transfer) || \ + ((MODE) == SDIO_MultiBlock_Transfer) || \ + ((MODE) == SDIO_SingleBlock_DMA_Transfer) || \ + ((MODE) == SDIO_MultiBlock_DMA_Transfer)) +/** + * @} + */ +/** @defgroup SDIO_Transfer_Direction SDIO Transfer Direction + * @{ + */ +#define SDIO_TransferDir_ToCard (0x00000000) +#define SDIO_TransferDir_ToSDIO (0x00000010) + +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) +/** + * @} + */ + + +/** @defgroup SDIO_Data_TimeOut SDIO Data TimeOut + * @{ + */ +#define IS_SDIO_DATA_TIMEOUT(TIME) ((TIME > 0) && (TIME <= 0x00ffffff)) +/** + * @} + */ + +/** @defgroup SDIO_Flags SDIO Flags + * @{ + */ +#define SDIO_FLAG_CMD_SEND (0x00000001) +#define SDIO_FLAG_TRANS_END (0x00000002) +#define SDIO_FLAG_BUF_OVERFLOW (0x00000008) +#define SDIO_FLAG_BUF_UNDERFLOW (0x00000010) +#define SDIO_FLAG_BUF_HALF (0x00000020) +#define SDIO_FLAG_BUF_FULL (0x00000040) +#define SDIO_FLAG_BUF_EMPTY (0x00000080) +#define SDIO_FLAG_ERR (0x00008000) +#define SDIO_FLAG_CMD_TIMEOUT (0x00010000) +#define SDIO_FLAG_CMD_CRCERR (0x00020000) +#define SDIO_FLAG_CMD_ENDERR (0x00040000) +#define SDIO_FLAG_CMD_IDXERR (0x00080000) +#define SDIO_FLAG_DATA_TIMEOUT (0x00100000) +#define SDIO_FLAG_DATA_CRCERR (0x00200000) +#define SDIO_FLAG_DATA_ENDERR (0x00400000) +#define SDIO_FLAG_CARD_INT (0x01000000) +#define SDIO_FLAG_DAT_ERR (0x02000000) +#define SDIO_FLAG_CMD_ERR (0x04000000) + +#define IS_SDIO_FLAG(FLAG) (((FLAG) != 0) && (((FLAG) & 0x077F80FB) != 0)) +/** + * @} + */ + +/** @defgroup SDIO_Response_Registers SDIO Response Registers + * @{ + */ +#define SDIO_RESP1 (0x00000000) +#define SDIO_RESP2 (0x00000004) +#define SDIO_RESP3 (0x00000008) +#define SDIO_RESP4 (0x0000000C) + +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ + ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || \ + ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_Interrupt_sources SDIO Interrupt sources + * @{ + */ +#define SDIO_INT_CMD_SEND (0x00000001) +#define SDIO_INT_TRANS_END (0x00000002) +#define SDIO_INT_BUF_OVERFLOW (0x00000008) +#define SDIO_INT_BUF_UNDERFLOW (0x00000010) +#define SDIO_INT_BUF_HALF (0x00000020) +#define SDIO_INT_BUF_FULL (0x00000040) +#define SDIO_INT_BUF_EMPTY (0x00000080) +#define SDIO_INT_CMD_TIMEOUT (0x00010000) +#define SDIO_INT_CMD_CRCERR (0x00020000) +#define SDIO_INT_CMD_IDXERR (0x00080000) +#define SDIO_INT_DATA_TIMEOUT (0x00100000) +#define SDIO_INT_DATA_CRCERR (0x00200000) +#define SDIO_INT_CARD_INT (0x01000000) + +#define IS_SDIO_INT(INT) (((INT) != 0) && (((INT) & 0x013B00FB) != 0)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Macro SDIO exported macro + * @{ + */ +#define RESET_CPSM() {\ + HT_SDIO->SWRST |= (1UL << 1);\ + while (HT_SDIO->SWRST & (1UL << 1));\ + } + +#define RESET_DPSM() {\ + HT_SDIO->SWRST |= (1UL << 2);\ + while (HT_SDIO->SWRST & (1UL << 2));\ + } +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Functions SDIO exported functions + * @{ + */ +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(ControlStatus Cmd); +u32 SDIO_ReadData(void); +void SDIO_WriteData(u32 Data); +u32 SDIO_GetFIFOCount(void); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +u32 SDIO_GetResponse(u32 SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_FlagConfig(u32 SDIO_FLAG, ControlStatus NewState); +FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG); +void SDIO_ClearFlag(u32 SDIO_FLAG); +void SDIO_IntConfig(u32 SDIO_INT, ControlStatus NewState); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_spi.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_spi.h new file mode 100644 index 00000000000..d69c32afbfa --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_spi.h @@ -0,0 +1,297 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_spi.h + * @version $Rev:: 2797 $ + * @date $Date:: 2022-11-28 #$ + * @brief The header file of the SPI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_SPI_H +#define __HT32F1XXXX_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI exported types + * @{ + */ +typedef u16 SPI_DataTypeDef; +typedef u16 SPI_TimeoutTypeDef; + +typedef struct +{ + u32 SPI_Mode; + u32 SPI_FIFO; + u32 SPI_DataLength; + u32 SPI_SELMode; + u32 SPI_SELPolarity; + u32 SPI_CPOL; + u32 SPI_CPHA; + u32 SPI_FirstBit; + u32 SPI_RxFIFOTriggerLevel; + u32 SPI_TxFIFOTriggerLevel; + u32 SPI_ClockPrescaler; +} SPI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Constants SPI exported constants + * @{ + */ +#define SPI_FIFO_ENABLE ((u32)0x00000400) +#define SPI_FIFO_DISABLE ((u32)0x00000000) + +#define IS_SPI_FIFO_SET(FIFO) ((FIFO == SPI_FIFO_ENABLE) || \ + (FIFO == SPI_FIFO_DISABLE)) + +#define SPI_DATALENGTH_1 ((u32)0x00000001) +#define SPI_DATALENGTH_2 ((u32)0x00000002) +#define SPI_DATALENGTH_3 ((u32)0x00000003) +#define SPI_DATALENGTH_4 ((u32)0x00000004) +#define SPI_DATALENGTH_5 ((u32)0x00000005) +#define SPI_DATALENGTH_6 ((u32)0x00000006) +#define SPI_DATALENGTH_7 ((u32)0x00000007) +#define SPI_DATALENGTH_8 ((u32)0x00000008) +#define SPI_DATALENGTH_9 ((u32)0x00000009) +#define SPI_DATALENGTH_10 ((u32)0x0000000A) +#define SPI_DATALENGTH_11 ((u32)0x0000000B) +#define SPI_DATALENGTH_12 ((u32)0x0000000C) +#define SPI_DATALENGTH_13 ((u32)0x0000000D) +#define SPI_DATALENGTH_14 ((u32)0x0000000E) +#define SPI_DATALENGTH_15 ((u32)0x0000000F) +#define SPI_DATALENGTH_16 ((u32)0x00000000) + +#define IS_SPI_DATALENGTH(DATALENGTH) ((DATALENGTH <= 0xF)) + + +#define SPI_MASTER ((u32)0x00004000) +#define SPI_SLAVE ((u32)0x00000000) + +#define IS_SPI_MODE(MODE) ((MODE == SPI_MASTER) || \ + (MODE == SPI_SLAVE)) + + +#define SPI_SEL_HARDWARE ((u32)0x00002000) +#define SPI_SEL_SOFTWARE ((u32)0x00000000) + +#define IS_SPI_SEL_MODE(SELMODE) ((SELMODE == SPI_SEL_HARDWARE) || \ + (SELMODE == SPI_SEL_SOFTWARE)) + + +#define SPI_SEL_ACTIVE ((u32)0x00000010) +#define SPI_SEL_INACTIVE ((u32)0xFFFFFFEF) + +#define IS_SPI_SOFTWARE_SEL(SEL) ((SEL == SPI_SEL_ACTIVE) || \ + (SEL == SPI_SEL_INACTIVE)) + + +#define SPI_SELPOLARITY_HIGH ((u32)0x00000800) +#define SPI_SELPOLARITY_LOW ((u32)0x00000000) + +#define IS_SPI_SEL_POLARITY(POLARITY) ((POLARITY == SPI_SELPOLARITY_HIGH) || \ + (POLARITY == SPI_SELPOLARITY_LOW)) + + +#define SPI_CPOL_HIGH ((u32)0x00000400) +#define SPI_CPOL_LOW ((u32)0x00000000) + +#define IS_SPI_CPOL(CPOL) ((CPOL == SPI_CPOL_HIGH) || \ + (CPOL == SPI_CPOL_LOW)) + + +#define SPI_CPHA_FIRST ((u32)0x00000000) +#define SPI_CPHA_SECOND ((u32)0x00000001) + +#define IS_SPI_CPHA(CPHA) ((CPHA == SPI_CPHA_FIRST) || \ + (CPHA == SPI_CPHA_SECOND)) + + +#define SPI_FIRSTBIT_LSB ((u32)0x00001000) +#define SPI_FIRSTBIT_MSB ((u32)0x00000000) + +#define IS_SPI_FIRST_BIT(BIT) ((BIT == SPI_FIRSTBIT_LSB) || \ + (BIT == SPI_FIRSTBIT_MSB)) + + +#define SPI_FLAG_TXBE ((u32)0x00000001) +#define SPI_FLAG_TXE ((u32)0x00000002) +#define SPI_FLAG_RXBNE ((u32)0x00000004) +#define SPI_FLAG_WC ((u32)0x00000008) +#define SPI_FLAG_RO ((u32)0x00000010) +#define SPI_FLAG_MF ((u32)0x00000020) +#define SPI_FLAG_SA ((u32)0x00000040) +#define SPI_FLAG_TOUT ((u32)0x00000080) +#define SPI_FLAG_BUSY ((u32)0x00000100) + +#define IS_SPI_FLAG(FLAG) ((FLAG == SPI_FLAG_TXBE) || \ + (FLAG == SPI_FLAG_TXE) || \ + (FLAG == SPI_FLAG_RXBNE) || \ + (FLAG == SPI_FLAG_WC) || \ + (FLAG == SPI_FLAG_RO) || \ + (FLAG == SPI_FLAG_MF) || \ + (FLAG == SPI_FLAG_SA) || \ + (FLAG == SPI_FLAG_TOUT) || \ + (FLAG == SPI_FLAG_BUSY)) + +#define IS_SPI_FLAG_CLEAR(CLEAR) ((CLEAR == SPI_FLAG_WC) || \ + (CLEAR == SPI_FLAG_RO) || \ + (CLEAR == SPI_FLAG_MF) || \ + (CLEAR == SPI_FLAG_SA) || \ + (CLEAR == SPI_FLAG_TOUT)) + + +#define SPI_INT_TXBE ((u32)0x00000001) +#define SPI_INT_TXE ((u32)0x00000002) +#define SPI_INT_RXBNE ((u32)0x00000004) +#define SPI_INT_WC ((u32)0x00000008) +#define SPI_INT_RO ((u32)0x00000010) +#define SPI_INT_MF ((u32)0x00000020) +#define SPI_INT_SA ((u32)0x00000040) +#define SPI_INT_TOUT ((u32)0x00000080) +#define SPI_INT_ALL ((u32)0x000000FF) + +#define IS_SPI_INT(SPI_INT) (((SPI_INT & 0xFFFFFF00) == 0x0) && (SPI_INT != 0x0)) + + +#define SPI_FIFO_TX ((u32)0x00000100) +#define SPI_FIFO_RX ((u32)0x00000200) + +#define IS_SPI_FIFO_DIRECTION(DIRECTION) (((DIRECTION & 0xFFFFFCFF) == 0) && (DIRECTION != 0)) + + +#define SPI_PDMAREQ_TX ((u32)0x00000002) +#define SPI_PDMAREQ_RX ((u32)0x00000004) + +#define IS_SPI_PDMA_REQ(REQ) (((REQ & 0xFFFFFFF9) == 0x0) && (REQ != 0x0)) + + +#define IS_SPI(SPI) ((SPI == HT_SPI0) || (SPI == HT_SPI1)) + +#define IS_SPI_DATA(DATA) (DATA <= 0xffff) + +#define IS_SPI_FIFO_LEVEL(LEVEL) (LEVEL <= 8) + +#define IS_SPI_CLOCK_PRESCALER(PRESCALER) (PRESCALER >= 2) + +#define SPI_GUADTIME_1_SCK ((u16)0x0000) +#define SPI_GUADTIME_2_SCK ((u16)0x0001) +#define SPI_GUADTIME_3_SCK ((u16)0x0002) +#define SPI_GUADTIME_4_SCK ((u16)0x0003) +#define SPI_GUADTIME_5_SCK ((u16)0x0004) +#define SPI_GUADTIME_6_SCK ((u16)0x0005) +#define SPI_GUADTIME_7_SCK ((u16)0x0006) +#define SPI_GUADTIME_8_SCK ((u16)0x0007) +#define SPI_GUADTIME_9_SCK ((u16)0x0008) +#define SPI_GUADTIME_10_SCK ((u16)0x0009) +#define SPI_GUADTIME_11_SCK ((u16)0x000A) +#define SPI_GUADTIME_12_SCK ((u16)0x000B) +#define SPI_GUADTIME_13_SCK ((u16)0x000C) +#define SPI_GUADTIME_14_SCK ((u16)0x000D) +#define SPI_GUADTIME_15_SCK ((u16)0x000E) +#define SPI_GUADTIME_16_SCK ((u16)0x000F) + +#define IS_SPI_GUADTIME(GUADTIMEPERIOD) ((GUADTIMEPERIOD <= 0x000F)) + + +#define SPI_SELHOLDTIME_HALF_SCK ((u16)0x0000) +#define SPI_SELHOLDTIME_1_SCK ((u16)0x0001) +#define SPI_SELHOLDTIME_1_HALF_SCK ((u16)0x0002) +#define SPI_SELHOLDTIME_2_SCK ((u16)0x0003) +#define SPI_SELHOLDTIME_2_HALF_SCK ((u16)0x0004) +#define SPI_SELHOLDTIME_3_SCK ((u16)0x0005) +#define SPI_SELHOLDTIME_3_HALF_SCK ((u16)0x0006) +#define SPI_SELHOLDTIME_4_SCK ((u16)0x0007) +#define SPI_SELHOLDTIME_4_HALF_SCK ((u16)0x0008) +#define SPI_SELHOLDTIME_5_SCK ((u16)0x0009) +#define SPI_SELHOLDTIME_5_HALF_SCK ((u16)0x000A) +#define SPI_SELHOLDTIME_6_SCK ((u16)0x000B) +#define SPI_SELHOLDTIME_6_HALF_SCK ((u16)0x000C) +#define SPI_SELHOLDTIME_7_SCK ((u16)0x000D) +#define SPI_SELHOLDTIME_7_HALF_SCK ((u16)0x000E) +#define SPI_SELHOLDTIME_8_SCK ((u16)0x000F) + +#define IS_SPI_SELHOLDTIME(SELHOLDTIME) ((SELHOLDTIME <= 0x000F)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI exported functions + * @{ + */ +void SPI_DeInit(HT_SPI_TypeDef* SPIx); +void SPI_Init(HT_SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void SPI_Cmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void SPI_SELOutputCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void SPI_FIFOCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void SPI_SetDataLength(HT_SPI_TypeDef* SPIx, u16 SPI_DataLength); +void SPI_SELModeConfig(HT_SPI_TypeDef* SPIx, u32 SPI_SELMode); +void SPI_SoftwareSELCmd(HT_SPI_TypeDef* SPIx, u32 SPI_SoftwareSEL); +void SPI_SendData(HT_SPI_TypeDef* SPIx, SPI_DataTypeDef SPI_Data); +SPI_DataTypeDef SPI_ReceiveData(HT_SPI_TypeDef* SPIx); +void SPI_SetTimeOutValue(HT_SPI_TypeDef* SPIx, SPI_TimeoutTypeDef SPI_Timeout); +void SPI_IntConfig(HT_SPI_TypeDef* SPIx, u32 SPI_Int, ControlStatus NewState); +FlagStatus SPI_GetFlagStatus(HT_SPI_TypeDef* SPIx, u32 SPI_Flag); +u8 SPI_GetFIFOStatus(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection); +void SPI_ClearFlag(HT_SPI_TypeDef* SPIx, u32 SPI_FlagClear); +void SPI_FIFOTriggerLevelConfig(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection, u8 SPI_FIFOLevel); +void SPI_PDMACmd(HT_SPI_TypeDef* SPIx, u32 SPI_PDMAREQ, ControlStatus NewState); +void SPI_DUALCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void SPI_GUARDTCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void SPI_GUARDTConfig(HT_SPI_TypeDef* SPIx, u32 Guard_Time); +void SPI_SELHTConfig(HT_SPI_TypeDef* SPIx, u32 CS_Hold_Time); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm.h new file mode 100644 index 00000000000..b15bbbdbd09 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm.h @@ -0,0 +1,623 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_tm.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the TM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_TM_H +#define __HT32F1XXXX_TM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup TM + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Types TM exported types + * @{ + */ +/** + * @brief Enumeration of TM counter mode. + */ +typedef enum +{ + TM_CNT_MODE_UP = 0x00000000, /*!< Edge up-counting mode */ + TM_CNT_MODE_CA1 = 0x00010000, /*!< Center-align mode 1 */ + TM_CNT_MODE_CA2 = 0x00020000, /*!< Center-align mode 2 */ + TM_CNT_MODE_CA3 = 0x00030000, /*!< Center-align mode 3 */ + TM_CNT_MODE_DOWN = 0x01000000 /*!< Edge down-counting mode */ +} TM_CNT_MODE_Enum; +/** + * @brief Enumeration of TM prescaler reload time. + */ +typedef enum +{ + TM_PSC_RLD_UPDATE = 0x0000, /*!< Reload prescaler at next update event */ + TM_PSC_RLD_IMMEDIATE = 0x0100 /*!< Reload prescaler immediately */ +} TM_PSC_RLD_Enum; +/** + * @brief Enumeration of TM channel output mode. + */ +typedef enum +{ + TM_OM_MATCH_NOCHANGE = 0x0000, /*!< TM channel output no change on match */ + TM_OM_MATCH_INACTIVE = 0x0001, /*!< TM channel output inactive level on match */ + TM_OM_MATCH_ACTIVE = 0x0002, /*!< TM channel output active level on match */ + TM_OM_MATCH_TOGGLE = 0x0003, /*!< TM channel output toggle on match */ + TM_OM_FORCED_INACTIVE = 0x0004, /*!< TM channel output forced inactive level */ + TM_OM_FORCED_ACTIVE = 0x0005, /*!< TM channel output forced active level */ + TM_OM_PWM1 = 0x0006, /*!< TM channel pwm1 output mode */ + TM_OM_PWM2 = 0x0007, /*!< TM channel pwm2 output mode */ + TM_OM_ASYMMETRIC_PWM1 = 0x0106, /*!< TM channel asymmetric pwm1 output mode */ + TM_OM_ASYMMETRIC_PWM2 = 0x0107 /*!< TM channel asymmetric pwm2 output mode */ +} TM_OM_Enum; +/** + * @brief Enumeration of TM channel capture source selection. + */ +typedef enum +{ + TM_CHCCS_DIRECT = 0x00010000, /*!< TM channel capture selection direct input */ + TM_CHCCS_INDIRECT = 0x00020000, /*!< TM channel capture selection indirect input */ + TM_CHCCS_TRCED = 0x00030000 /*!< TM channel capture selection TRCED of trigger control block */ +} TM_CHCCS_Enum; +/** + * @brief Enumeration of TM channel capture prescaler. + */ +typedef enum +{ + TM_CHPSC_OFF = 0x00000000, /*!< TM channel capture no prescaler, capture is done each event */ + TM_CHPSC_2 = 0x00040000, /*!< TM channel capture is done once every 2 event */ + TM_CHPSC_4 = 0x00080000, /*!< TM channel capture is done once every 4 event */ + TM_CHPSC_8 = 0x000C0000 /*!< TM channel capture is done once every 8 event */ +} TM_CHPSC_Enum; +/** + * @brief Enumeration of TM fDTS clock divider. + */ +typedef enum +{ + TM_CKDIV_OFF = 0x0000, /*!< fDTS = fCLKIN */ + TM_CKDIV_2 = 0x0100, /*!< fDTS = fCLKIN / 2 */ + TM_CKDIV_4 = 0x0200 /*!< fDTS = fCLKIN / 4 */ +} TM_CKDIV_Enum; +/** + * @brief Enumeration of TM ETI input prescaler. + */ +typedef enum +{ + TM_ETIPSC_OFF = 0x00000000, /*!< ETI prescaler off */ + TM_ETIPSC_2 = 0x00001000, /*!< ETIP frequency divided by 2 */ + TM_ETIPSC_4 = 0x00002000, /*!< ETIP frequency divided by 4 */ + TM_ETIPSC_8 = 0x00003000 /*!< ETIP frequency divided by 8 */ +} TM_ETIPSC_Enum; +/** + * @brief Enumeration of TM ETI input polarity. + */ +typedef enum +{ + TM_ETIPOL_NONINVERTED = 0x00000000, /*!< TM ETI polarity is active high or rising edge */ + TM_ETIPOL_INVERTED = 0x00010000 /*!< TM ETI polarity is active low or falling edge */ +} TM_ETIPOL_Enum; +/** + * @brief Enumeration of TM slave trigger input selection. + */ +typedef enum +{ + TM_TRSEL_UEVG = 0x0, /*!< Software trigger by setting UEVG bit */ + TM_TRSEL_TI0S0 = 0x1, /*!< Filtered channel 0 input */ + TM_TRSEL_TI1S1 = 0x2, /*!< Filtered channel 1 input */ + TM_TRSEL_ETIF = 0x3, /*!< External Trigger input */ + TM_TRSEL_TI0BED = 0x8, /*!< Trigger input 0 both edge detector */ + TM_TRSEL_ITI0 = 0x9, /*!< Internal trigger input 0 */ + TM_TRSEL_ITI1 = 0xA, /*!< Internal trigger input 1 */ + TM_TRSEL_ITI2 = 0xB /*!< Internal trigger input 2 */ +} TM_TRSEL_Enum; +/** + * @brief Enumeration of TM slave mode selection. + */ +typedef enum +{ + TM_SMSEL_DISABLE = 0x0000, /*!< The prescaler is clocked directly by the internal clock */ + TM_SMSEL_DECODER1 = 0x0100, /*!< Counter counts up/down on CH0 edge depending on CH1 level */ + TM_SMSEL_DECODER2 = 0x0200, /*!< Counter counts up/down on CH1 edge depending on CH0 level */ + TM_SMSEL_DECODER3 = 0x0300, /*!< Counter counts up/down on both CH0 & CH1 edges depending on the + level of the other input */ + TM_SMSEL_RESTART = 0x0400, /*!< Slave restart mode */ + TM_SMSEL_PAUSE = 0x0500, /*!< Slave pause mode */ + TM_SMSEL_TRIGGER = 0x0600, /*!< Slave trigger mode */ + TM_SMSEL_STIED = 0x0700 /*!< Rising edge of the selected trigger(STI) clock the counter */ +} TM_SMSEL_Enum; +/** + * @brief Enumeration of TM master mode selection. + */ +typedef enum +{ + TM_MMSEL_RESET = 0x00000000, /*!< Send trigger signal when S/W setting UEVG or slave restart */ + TM_MMSEL_ENABLE = 0x00010000, /*!< The counter enable signal is used as trigger output. */ + TM_MMSEL_UPDATE = 0x00020000, /*!< The update event is used as trigger output. */ + TM_MMSEL_CH0CC = 0x00030000, /*!< Channel 0 capture or compare match occurred as trigger output. */ + TM_MMSEL_CH0OREF = 0x00040000, /*!< The CH0OREF signal is used as trigger output. */ + TM_MMSEL_CH1OREF = 0x00050000, /*!< The CH1OREF signal is used as trigger output. */ + TM_MMSEL_CH2OREF = 0x00060000, /*!< The CH2OREF signal is used as trigger output. */ + TM_MMSEL_CH3OREF = 0x00070000 /*!< The CH3OREF signal is used as trigger output. */ +} TM_MMSEL_Enum; +/** + * @brief Enumeration of TM channel Capture / Compare PDMA selection. + */ +typedef enum +{ + TM_CHCCDS_CHCCEV = 0, /*!< Send CHx PDMA request when channel capture/compare event occurs */ + TM_CHCCDS_UEV /*!< Send CHx PDMA request when update event occurs */ +} TM_CHCCDS_Enum; +/** + * @brief Definition of TM timebase init structure. + */ +typedef struct +{ + u16 CounterReload; /*!< Period (Value for CRR register) */ + u16 Prescaler; /*!< Prescaler (Value for PSCR register) */ + u8 RepetitionCounter; /*!< Repetition counter */ + TM_CNT_MODE_Enum CounterMode; /*!< Counter mode refer to \ref TM_CNT_MODE_Enum */ + TM_PSC_RLD_Enum PSCReloadTime; /*!< Prescaler reload mode refer to \ref TM_PSC_RLD_Enum */ +} TM_TimeBaseInitTypeDef; +/** + * @brief Definition of TM channel output init structure. + */ +typedef struct +{ + TM_CH_Enum Channel; /*!< Channel selection refer to \ref TM_CH_Enum */ + TM_OM_Enum OutputMode; /*!< Channel output mode selection refer to \ref TM_OM_Enum */ + TM_CHCTL_Enum Control; /*!< CHxO output state refer to \ref TM_CHCTL_Enum */ + TM_CHCTL_Enum ControlN; /*!< CHxO output state refer to \ref TM_CHCTL_Enum */ + TM_CHP_Enum Polarity; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + TM_CHP_Enum PolarityN; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + MCTM_OIS_Enum IdleState; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + MCTM_OIS_Enum IdleStateN; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + u16 Compare; /*!< Value for CHxCCR register */ + u16 AsymmetricCompare; /*!< Value for CHxACR register */ +} TM_OutputInitTypeDef; +/** + * @brief Definition of TM channel input init structure. + */ +typedef struct +{ + TM_CH_Enum Channel; /*!< Channel selection refer to \ref TM_CH_Enum */ + TM_CHP_Enum Polarity; /*!< Channel input polarity refer to \ref TM_CHP_Enum */ + TM_CHCCS_Enum Selection; /*!< Channel capture source selection refer to \ref TM_CHCCS_Enum */ + TM_CHPSC_Enum Prescaler; /*!< Channel Capture prescaler refer to \ref TM_CHPSC_Enum */ + u8 Filter; /*!< Digital filter Configuration, it must between 0x0 ~ 0xF. */ +} TM_CaptureInitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Constants TM exported constants + * @{ + */ + +/** @defgroup TM_INT Definitions of TM_INT + * @{ + */ +#define TM_INT_CH0CC 0x0001 /*!< Channel 0 capture/compare interrupt */ +#define TM_INT_CH1CC 0x0002 /*!< Channel 1 capture/compare interrupt */ +#define TM_INT_CH2CC 0x0004 /*!< Channel 2 capture/compare interrupt */ +#define TM_INT_CH3CC 0x0008 /*!< Channel 3 capture/compare interrupt */ +#define TM_INT_UEV 0x0100 /*!< Update interrupt */ +#define TM_INT_UEV2 0x0200 /*!< Update interrupt 2 */ +#define TM_INT_TEV 0x0400 /*!< Trigger interrupt */ +#define TM_INT_BRKEV 0x0800 /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TM_PDMA Definitions of TM_PDMA + * @{ + */ +#define TM_PDMA_CH0CC 0x00010000 /*!< Channel 0 capture/compare PDMA request */ +#define TM_PDMA_CH1CC 0x00020000 /*!< Channel 1 capture/compare PDMA request */ +#define TM_PDMA_CH2CC 0x00040000 /*!< Channel 2 capture/compare PDMA request */ +#define TM_PDMA_CH3CC 0x00080000 /*!< Channel 3 capture/compare PDMA request */ +#define TM_PDMA_UEV 0x01000000 /*!< Update PDMA request */ +#define TM_PDMA_UEV2 0x02000000 /*!< Update 2 PDMA request */ +#define TM_PDMA_TEV 0x04000000 /*!< Trigger PDMA request */ +/** + * @} + */ + +/** @defgroup TM_EVENT Definitions of TM_EVENT + * @{ + */ +#define TM_EVENT_CH0CC 0x0001 /*!< Channel 0 capture/compare event */ +#define TM_EVENT_CH1CC 0x0002 /*!< Channel 1 capture/compare event */ +#define TM_EVENT_CH2CC 0x0004 /*!< Channel 2 capture/compare event */ +#define TM_EVENT_CH3CC 0x0008 /*!< Channel 3 capture/compare event */ +#define TM_EVENT_UEV 0x0100 /*!< Update event */ +#define TM_EVENT_UEV2 0x0200 /*!< Update event 2 */ +#define TM_EVENT_TEV 0x0400 /*!< Trigger event */ +#define TM_EVENT_BRKEV 0x0800 /*!< Break event */ +/** + * @} + */ + +/** @defgroup TM_FLAG Definitions of TM_FLAG + * @{ + */ +#define TM_FLAG_CH0CC 0x0001 /*!< Channel 0 capture/compare flag */ +#define TM_FLAG_CH1CC 0x0002 /*!< Channel 1 capture/compare flag */ +#define TM_FLAG_CH2CC 0x0004 /*!< Channel 2 capture/compare flag */ +#define TM_FLAG_CH3CC 0x0008 /*!< Channel 3 capture/compare flag */ +#define TM_FLAG_CH0OC 0x0010 /*!< Channel 0 over capture flag */ +#define TM_FLAG_CH1OC 0x0020 /*!< Channel 1 over capture flag */ +#define TM_FLAG_CH2OC 0x0040 /*!< Channel 2 over capture flag */ +#define TM_FLAG_CH3OC 0x0080 /*!< Channel 3 over capture flag */ +#define TM_FLAG_UEV 0x0100 /*!< Update flag */ +#define TM_FLAG_UEV2 0x0200 /*!< Update 2 flag */ +#define TM_FLAG_TEV 0x0400 /*!< Trigger flag */ +#define TM_FLAG_BRK0 0x0800 /*!< Break 0 flag */ +#define TM_FLAG_BRK1 0x1000 /*!< Break 1 flag */ +/** + * @} + */ + +/** @defgroup TM_Check_Parameter Check parameter + * @{ + */ + +/** + * @brief Used to check parameter of the TMx. + */ +#define IS_TM(x) (IS_GPTM0(x) || IS_GPTM1(x) || IS_MCTM0(x) || IS_MCTM1(x) || IS_SCTM(x)) +#define IS_GPTM0(x) (x == HT_GPTM0) + +#define IS_GPTM1(x) (0) +#define IS_MCTM0(x) (0) +#define IS_MCTM1(x) (0) + +#if !(LIBCFG_NO_GPTM1) +#undef IS_GPTM1 +#define IS_GPTM1(x) (x == HT_GPTM1) +#endif + +#if !(LIBCFG_NO_MCTM0) +#undef IS_MCTM0 +#define IS_MCTM0(x) (x == HT_MCTM0) +#endif + +#if !(LIBCFG_NO_MCTM1) +#undef IS_MCTM1 +#define IS_MCTM1(x) (x == HT_MCTM1) +#endif + +#define IS_SCTM(x) (IS_SCTM0(x) || IS_SCTM1(x)) + +#define IS_SCTM0(x) (0) +#define IS_SCTM1(x) (0) + +#if (LIBCFG_SCTM0) +#undef IS_SCTM0 +#define IS_SCTM0(x) (x == HT_SCTM0) +#endif + +#if (LIBCFG_SCTM1) +#undef IS_SCTM1 +#define IS_SCTM1(x) (x == HT_SCTM1) +#endif + + +/** + * @brief Used to check parameter of the output compare mode. + */ +#define IS_TM_OM_CMP(x) (((x) == TM_OM_MATCH_NOCHANGE) || \ + ((x) == TM_OM_MATCH_INACTIVE) || \ + ((x) == TM_OM_MATCH_ACTIVE) || \ + ((x) == TM_OM_MATCH_TOGGLE) || \ + ((x) == TM_OM_PWM1) || \ + ((x) == TM_OM_PWM2)) +/** + * @brief Used to check parameter of the output mode. + */ +#define IS_TM_OM(x) (((x) == TM_OM_MATCH_NOCHANGE) || \ + ((x) == TM_OM_MATCH_INACTIVE) || \ + ((x) == TM_OM_MATCH_ACTIVE) || \ + ((x) == TM_OM_MATCH_TOGGLE) || \ + ((x) == TM_OM_PWM1) || \ + ((x) == TM_OM_PWM2) || \ + ((x) == TM_OM_FORCED_INACTIVE) || \ + ((x) == TM_OM_FORCED_ACTIVE) || \ + ((x) == TM_OM_ASYMMETRIC_PWM1) || \ + ((x) == TM_OM_ASYMMETRIC_PWM2)) +/** + * @brief Used to check parameter of the channel. + */ +#define IS_TM_CH(x) (((x) == TM_CH_0) || ((x) == TM_CH_1) || \ + ((x) == TM_CH_2) || ((x) == TM_CH_3)) +/** + * @brief Used to check parameter of the channel for PWM input function. + */ +#define IS_TM_CH_PWMI(x) (((x) == TM_CH_0) || ((x) == TM_CH_1)) +/** + * @brief Used to check parameter of the clock divider. + */ +#define IS_TM_CKDIV(x) ((x == TM_CKDIV_OFF) || \ + (x == TM_CKDIV_2) || \ + (x == TM_CKDIV_4)) +/** + * @brief Used to check parameter of the counter mode. + */ +#define IS_TM_CNT_MODE(x) ((x == TM_CNT_MODE_UP) || \ + (x == TM_CNT_MODE_CA1) || \ + (x == TM_CNT_MODE_CA2) || \ + (x == TM_CNT_MODE_CA3) || \ + (x == TM_CNT_MODE_DOWN)) +/** + * @brief Used to check parameter of the channel polarity. + */ +#define IS_TM_CHP(x) ((x == TM_CHP_NONINVERTED) || (x == TM_CHP_INVERTED)) +/** + * @brief Used to check parameter of the channel control. + */ +#define IS_TM_CHCTL(x) ((x == TM_CHCTL_DISABLE) || (x == TM_CHCTL_ENABLE)) +/** + * @brief Used to check parameter of the channel capture / compare PDMA selection. + */ +#define IS_TM_CHCCDS(x) ((x == TM_CHCCDS_CHCCEV) || (x == TM_CHCCDS_UEV)) +/** + * @brief Used to check parameter of the channel input selection. + */ +#define IS_TM_CHCCS(x) ((x == TM_CHCCS_DIRECT) || \ + (x == TM_CHCCS_INDIRECT) || \ + (x == TM_CHCCS_TRCED)) +/** + * @brief Used to check parameter of the channel capture prescaler. + */ +#define IS_TM_CHPSC(x) ((x == TM_CHPSC_OFF) || \ + (x == TM_CHPSC_2) || \ + (x == TM_CHPSC_4) || \ + (x == TM_CHPSC_8)) +/** + * @brief Used to check parameter of the ETI prescaler. + */ +#define IS_TM_ETIPSC(x) ((x == TM_ETIPSC_OFF) || \ + (x == TM_ETIPSC_2) || \ + (x == TM_ETIPSC_4) || \ + (x == TM_ETIPSC_8)) +/** + * @brief Used to check parameter of the TM interrupt. + */ +#define IS_TM_INT(x) (((x & 0xFFFFF0F0) == 0x0) && (x != 0)) +/** + * @brief Used to check parameter of the TM PDMA request. + */ +#define IS_TM_PDMA(x) (((x & 0xF8F0FFFF) == 0x0) && (x != 0)) +/** + * @brief Used to check parameter of the TM interrupt for \ref TM_GetIntStatus function. + */ +#define IS_TM_GET_INT(x) ((x == TM_INT_CH0CC) || \ + (x == TM_INT_CH1CC) || \ + (x == TM_INT_CH2CC) || \ + (x == TM_INT_CH3CC) || \ + (x == TM_INT_UEV) || \ + (x == TM_INT_UEV2) || \ + (x == TM_INT_TEV) || \ + (x == TM_INT_BRKEV)) +/** + * @brief Used to check parameter of the TM STI selection. + */ +#define IS_TM_TRSEL(x) ((x == TM_TRSEL_UEVG) || \ + (x == TM_TRSEL_TI0S0) || \ + (x == TM_TRSEL_TI1S1) || \ + (x == TM_TRSEL_ETIF) || \ + (x == TM_TRSEL_TI0BED) || \ + (x == TM_TRSEL_ITI0) || \ + (x == TM_TRSEL_ITI1) || \ + (x == TM_TRSEL_ITI2)) +/** + * @brief Used to check parameter of the ITI. + */ +#define IS_TM_ITI(x) ((x == TM_TRSEL_ITI0) || (x == TM_TRSEL_ITI1) || (x == TM_TRSEL_ITI2)) +/** + * @brief Used to check parameter of the TM_TRSEL for \ref TM_ChExternalClockConfig function. + */ +#define IS_TM_TRSEL_CH(x) ((x == TM_TRSEL_TI0S0) || (x == TM_TRSEL_TI1S1) || \ + (x == TM_TRSEL_TI0BED)) +/** + * @brief Used to check parameter of the TM ETI polarity. + */ +#define IS_TM_ETIPOL(x) ((x == TM_ETIPOL_NONINVERTED) || (x == TM_ETIPOL_INVERTED)) +/** + * @brief Used to check parameter of the TM prescaler reload time. + */ +#define IS_TM_PSC_RLD(x) ((x == TM_PSC_RLD_UPDATE) || (x == TM_PSC_RLD_IMMEDIATE)) +/** + * @brief Used to check parameter of the forced action. + */ +#define IS_TM_OM_FORCED(x) ((x == TM_OM_FORCED_ACTIVE) || (x == TM_OM_FORCED_INACTIVE)) +/** + * @brief Used to check parameter of the decoder mode. + */ +#define IS_TM_SMSEL_DECODER(x) ((x == TM_SMSEL_DECODER1) || (x == TM_SMSEL_DECODER2) || \ + (x == TM_SMSEL_DECODER3)) +/** + * @brief Used to check parameter of the event. + */ +#define IS_TM_EVENT(x) (((x & 0xFFFFF0F0) == 0x0000) && (x != 0x0000)) +/** + * @brief Used to check parameter of the TM master mode selection. + */ +#define IS_TM_MMSEL(x) (((x) == TM_MMSEL_RESET) || \ + ((x) == TM_MMSEL_ENABLE) || \ + ((x) == TM_MMSEL_UPDATE) || \ + ((x) == TM_MMSEL_CH0CC) || \ + ((x) == TM_MMSEL_CH0OREF) || \ + ((x) == TM_MMSEL_CH1OREF) || \ + ((x) == TM_MMSEL_CH2OREF) || \ + ((x) == TM_MMSEL_CH3OREF)) +/** + * @brief Used to check parameter of the TM slave mode. + */ +#define IS_TM_SLAVE_MODE(x) ((x == TM_SMSEL_RESTART) || (x == TM_SMSEL_PAUSE) || \ + (x == TM_SMSEL_TRIGGER) || (x == TM_SMSEL_STIED)) +/** + * @brief Used to check parameter of the TM flag. + */ +#define IS_TM_FLAG(x) ((x == TM_FLAG_CH0CC) || \ + (x == TM_FLAG_CH1CC) || \ + (x == TM_FLAG_CH2CC) || \ + (x == TM_FLAG_CH3CC) || \ + (x == TM_FLAG_CH0OC) || \ + (x == TM_FLAG_CH1OC) || \ + (x == TM_FLAG_CH2OC) || \ + (x == TM_FLAG_CH3OC) || \ + (x == TM_FLAG_UEV) || \ + (x == TM_FLAG_UEV2) || \ + (x == TM_FLAG_TEV) || \ + (x == TM_FLAG_BRK0) || \ + (x == TM_FLAG_BRK1)) + +/** + * @brief Used to check parameter of the TM flag for \ref TM_ClearFlag function. + */ +#define IS_TM_FLAG_CLR(x) (((x & 0xFFFFE000) == 0) && (x != 0)) +/** + * @brief Used to check value of TM digital filter. + */ +#define IS_TM_FILTER(x) (x <= 0xF) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Functions TM exported functions + * @{ + */ +#define TM_SetCaptureCompare0(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_0, Cmp) +#define TM_SetCaptureCompare1(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_1, Cmp) +#define TM_SetCaptureCompare2(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_2, Cmp) +#define TM_SetCaptureCompare3(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_3, Cmp) + +#define TM_ForcedOREF0(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_0, ForcedAction) +#define TM_ForcedOREF1(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_1, ForcedAction) +#define TM_ForcedOREF2(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_2, ForcedAction) +#define TM_ForcedOREF3(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_3, ForcedAction) + +#define TM_SetAsymmetricCompare0(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_0, Cmp) +#define TM_SetAsymmetricCompare1(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_1, Cmp) +#define TM_SetAsymmetricCompare2(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_2, Cmp) +#define TM_SetAsymmetricCompare3(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_3, Cmp) + +#define TM_GetCaptureCompare0(TMx) TM_GetCaptureCompare(TMx,TM_CH_0) +#define TM_GetCaptureCompare1(TMx) TM_GetCaptureCompare(TMx,TM_CH_1) +#define TM_GetCaptureCompare2(TMx) TM_GetCaptureCompare(TMx,TM_CH_2) +#define TM_GetCaptureCompare3(TMx) TM_GetCaptureCompare(TMx,TM_CH_3) + +void TM_DeInit(HT_TM_TypeDef* TMx); +void TM_TimeBaseInit(HT_TM_TypeDef* TMx, TM_TimeBaseInitTypeDef* TimeBaseInit); +void TM_OutputInit(HT_TM_TypeDef* TMx, TM_OutputInitTypeDef* OutInit); +void TM_CaptureInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit); +void TM_PwmInputInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit); +void TM_TimeBaseStructInit(TM_TimeBaseInitTypeDef* TimeBaseInit); +void TM_OutputStructInit(TM_OutputInitTypeDef* OutInit); +void TM_CaptureStructInit(TM_CaptureInitTypeDef* CapInit); +void TM_Cmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_ItiExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Iti); +void TM_ChExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel, TM_CHP_Enum Pol, u8 Filter); +void TM_EtiExternalClockConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter); +void TM_EtiConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter); +void TM_PrescalerConfig(HT_TM_TypeDef* TMx, u16 Psc, TM_PSC_RLD_Enum PscReloadTime); +void TM_CounterModeConfig(HT_TM_TypeDef* TMx, TM_CNT_MODE_Enum Mod); +void TM_StiConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel); +void TM_DecoderConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum DecoderMod, TM_CHP_Enum CH0P, TM_CHP_Enum CH1P); + +void TM_ForcedOREF(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, TM_OM_Enum ForcedAction); +void TM_CRRPreloadCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_CHCCRPreloadConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState); +void TM_ClearOREFConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState); +void TM_ChPolarityConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHP_Enum Pol); + +void TM_ImmActiveConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState); +void TM_ChannelConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control); + +void TM_OutputModeConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_OM_Enum Mod); +void TM_UpdateCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_UEVG_IntConfig(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_HallInterfaceCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_SinglePulseModeCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_MMSELConfig(HT_TM_TypeDef* TMx, TM_MMSEL_Enum Sel); +void TM_SlaveModeConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum Sel); +void TM_TimSyncCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_SetCounter(HT_TM_TypeDef* TMx, u16 Counter); +void TM_SetCounterReload(HT_TM_TypeDef* TMx, u16 Reload); +void TM_SetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp); +void TM_SetAsymmetricCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp); + +void TM_CHPSCConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHPSC_Enum Psc); +void TM_CKDIVConfig(HT_TM_TypeDef* TMx, TM_CKDIV_Enum Div); +u32 TM_GetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n); +u32 TM_GetCounter(HT_TM_TypeDef* TMx); +u32 TM_GetPrescaler(HT_TM_TypeDef* TMx); +void TM_GenerateEvent(HT_TM_TypeDef* TMx, u32 TM_EVENT); +FlagStatus TM_GetFlagStatus(HT_TM_TypeDef* TMx, u32 TM_FLAG); +void TM_ClearFlag(HT_TM_TypeDef* TMx, u32 TM_FLAG); +void TM_IntConfig(HT_TM_TypeDef* TMx, u32 TM_INT, ControlStatus NewState); +FlagStatus TM_GetIntStatus(HT_TM_TypeDef* TMx, u32 TM_INT); +void TM_ClearIntPendingBit(HT_TM_TypeDef* TMx, u32 TM_INT); +void TM_InternalClockConfig(HT_TM_TypeDef* TMx); + +void TM_CHCCDSConfig(HT_TM_TypeDef* TMx, TM_CHCCDS_Enum Selection); +void TM_PDMAConfig(HT_TM_TypeDef* TMx, u32 TM_PDMA, ControlStatus NewState); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm_type.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm_type.h new file mode 100644 index 00000000000..19cac328c58 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_tm_type.h @@ -0,0 +1,113 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_tm_type.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the TM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_TM_TYPE_H +#define __HT32F1XXXX_TM_TYPE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup TM + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Types TM exported types + * @{ + */ +/** + * @brief Enumeration of TM channel. + */ +typedef enum +{ + TM_CH_0 = 0, /*!< TM channel 0 */ + TM_CH_1, /*!< TM channel 1 */ + TM_CH_2, /*!< TM channel 2 */ + TM_CH_3 /*!< TM channel 3 */ +} TM_CH_Enum; +/** + * @brief Enumeration of TM channel control. + */ +typedef enum +{ + TM_CHCTL_DISABLE = 0, /*!< TM channel disable */ + TM_CHCTL_ENABLE /*!< TM channel enable */ +} TM_CHCTL_Enum; +/** + * @brief Enumeration of TM channel polarity. + */ +typedef enum +{ + TM_CHP_NONINVERTED = 0, /*!< TM channel polarity is active high or rising edge */ + TM_CHP_INVERTED /*!< TM channel polarity is active low or falling edge */ +} TM_CHP_Enum; +/** + * @brief Enumeration of MCTM channel output idle state. + */ +typedef enum +{ + MCTM_OIS_LOW = 0, /*!< MCTM channel output low when CHMOE equal to 0 */ + MCTM_OIS_HIGH /*!< MCTM channel output high when CHMOE equal to 0 */ +} MCTM_OIS_Enum; +/** + * @brief Enumeration of MCTM COMUS. + */ +typedef enum +{ + MCTM_COMUS_STIOFF = 0, /*!< MCTM capture/compare control bits are updated by + setting the UEV2G bit only */ + MCTM_COMUS_STION /*!< MCTM capture/compare control bits are updated by both + setting the UEV2G bit or when a rising edge occurs on STI */ +} MCTM_COMUS_Enum; +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usart.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usart.h new file mode 100644 index 00000000000..6e0c5332b20 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usart.h @@ -0,0 +1,585 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_usart.h + * @version $Rev:: 2797 $ + * @date $Date:: 2022-11-28 #$ + * @brief The header file of the USART library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_USART_H +#define __HT32F1XXXX_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + + +#define LIBCFG_USART_V01_LEGACY (0) + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Types USART exported types + * @{ + */ +/* Definition of USART Init Structure ---------------------------------------------------------------------*/ +typedef struct +{ + u32 USART_BaudRate; + u16 USART_WordLength; + u16 USART_StopBits; + u16 USART_Parity; + u16 USART_Mode; +} USART_InitTypeDef; + +typedef struct +{ + u16 USART_ClockEnable; + u16 USART_ClockPhase; + u16 USART_ClockPolarity; + u16 USART_TransferSelectMode; +} USART_SynClock_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Constants USART exported constants + * @{ + */ + +#define USART_CMD_TX (0) +#define USART_CMD_RX (1) + +#define USART_CMD_OUT (0) +#define USART_CMD_IN (1) + +/* USART Word Length ---------------------------------------------------------------------------------------*/ +/** @defgroup USART_Word_Length Definitions of USART word length + * @{ + */ +#if (LIBCFG_USART_V01) +#define USART_WORDLENGTH_7B ((u32)0x00000000) +#define USART_WORDLENGTH_8B ((u32)0x00000001) +#define USART_WORDLENGTH_9B ((u32)0x00000002) +#else +#define USART_WORDLENGTH_7B ((u32)0x00000000) +#define USART_WORDLENGTH_8B ((u32)0x00000100) +#define USART_WORDLENGTH_9B ((u32)0x00000200) +#endif + +#define IS_USART_WORD_LENGTH(LENGTH) ((LENGTH == USART_WORDLENGTH_9B) || \ + (LENGTH == USART_WORDLENGTH_8B) || \ + (LENGTH == USART_WORDLENGTH_7B)) +/** + * @} + */ + +/* USART Stop Bits -----------------------------------------------------------------------------------------*/ +/** @defgroup USART_Stop_Bit Definitions of USART stop bit + * @{ + */ +#if (LIBCFG_USART_V01) +#define USART_STOPBITS_1 ((u32)0x00000000) +#define USART_STOPBITS_2 ((u32)0x00000004) +#else +#define USART_STOPBITS_1 ((u32)0x00000000) +#define USART_STOPBITS_2 ((u32)0x00000400) +#endif + + +#define IS_USART_STOPBITS(STOPBITS) ((STOPBITS == USART_STOPBITS_1) || \ + (STOPBITS == USART_STOPBITS_2)) +/** + * @} + */ + +/* USART Parity --------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Parity Definitions of USART parity + * @{ + */ +#if (LIBCFG_USART_V01) +#define USART_PARITY_NO ((u32)0x00000000) +#define USART_PARITY_EVEN ((u32)0x00000018) +#define USART_PARITY_ODD ((u32)0x00000008) +#else +#define USART_PARITY_NO ((u32)0x00000000) +#define USART_PARITY_EVEN ((u32)0x00001800) +#define USART_PARITY_ODD ((u32)0x00000800) +#define USART_PARITY_MARK ((u32)0x00002800) +#define USART_PARITY_SPACE ((u32)0x00003800) +#endif + +#define IS_USART_PARITY(PARITY) ((PARITY == USART_PARITY_NO) || \ + (PARITY == USART_PARITY_EVEN) || \ + (PARITY == USART_PARITY_ODD)) +/** + * @} + */ + +/* USART Mode ----------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Mode Definitions of USART mode + * @{ + */ +#define USART_MODE_NORMAL ((u32)0x00000000) +#define USART_MODE_IRDA ((u32)0x00000001) +#define USART_MODE_RS485 ((u32)0x00000002) +#define USART_MODE_SYNCHRONOUS ((u32)0x00000003) + +#define IS_USART_MODE(MODE) ((MODE == USART_MODE_NORMAL) || \ + (MODE == USART_MODE_IRDA) || \ + (MODE == USART_MODE_RS485) || \ + (MODE == USART_MODE_SYNCHRONOUS)) +/** + * @} + */ + +/* USART Transfer Select Mode ------------------------------------------------------------------------------*/ +/** @defgroup USART_LSB Definitions of USART LSB + * @{ + */ +#define USART_LSB_FIRST ((u32)0x00000000) +#define USART_MSB_FIRST ((u32)0x00000004) + +#define IS_USART_TRANSFER_MODE(TMODE) ((TMODE == USART_LSB_FIRST) || \ + (TMODE == USART_MSB_FIRST)) +/** + * @} + */ + + +/* USART Synchronous Clock ---------------------------------------------------------------------------------*/ +/** @defgroup USART_Synchronous_Clock Definitions of USART synchronous clock + * @{ + */ +#define USART_SYN_CLOCK_DISABLE ((u32)0x00000000) +#define USART_SYN_CLOCK_ENABLE ((u32)0x00000001) + +#define IS_USART_SYNCHRONOUS_CLOCK(SYNCLOCK) ((SYNCLOCK == USART_SYN_CLOCK_DISABLE) || \ + (SYNCLOCK == USART_SYN_CLOCK_ENABLE)) +/** + * @} + */ + +/* USART Synchronous Clock Phase ---------------------------------------------------------------------------*/ +/** @defgroup USART_Synchronous_Clock_Phase Definitions of USART Synchronous clock phase + * @{ + */ +#define USART_SYN_CLOCK_PHASE_FIRST ((u32)0x00000000) +#define USART_SYN_CLOCK_PHASE_SECOND ((u32)0x00000004) + +#define IS_USART_SYNCHRONOUS_PHASE(PHASE) ((PHASE == USART_SYN_CLOCK_PHASE_FIRST) || \ + (PHASE == USART_SYN_CLOCK_PHASE_SECOND)) +/** + * @} + */ + +/* USART Clock Polarity ------------------------------------------------------------------------------------*/ +/** @defgroup USART_Clock_Polarity Definitions of USART clock polarity + * @{ + */ +#define USART_SYN_CLOCK_POLARITY_LOW ((u32)0x00000000) +#define USART_SYN_CLOCK_POLARITY_HIGH ((u32)0x00000008) + +#define IS_USART_SYNCHRONOUS_POLARITY(POLARITY) ((POLARITY == USART_SYN_CLOCK_POLARITY_LOW) || \ + (POLARITY == USART_SYN_CLOCK_POLARITY_HIGH)) +/** + * @} + */ + +/* USART IrDA ---------------------------------------------------------------------------------------------*/ +/** @defgroup USART_IrDA Definitions of USART IrDA + * @{ + */ +#define USART_IRDA_LOWPOWER ((u32)0x00000002) +#define USART_IRDA_NORMAL ((u32)0xFFFFFFFD) + +#define IS_USART_IRDA_MODE(MODE) ((MODE == USART_IRDA_LOWPOWER) || \ + (MODE == USART_IRDA_NORMAL)) + +#define USART_IRDA_TX ((u32)0x00000004) +#define USART_IRDA_RX ((u32)0xFFFFFFFB) + +#define IS_USART_IRDA_DIRECTION(DIRECTION) ((DIRECTION == USART_IRDA_TX) || \ + (DIRECTION == USART_IRDA_RX)) +/** + * @} + */ + +#define IS_USART_TL(x) (IS_USART_RXTL(x) || IS_USART_TXTL(x)) + +/* USART Rx FIFO Interrupt Trigger Level -------------------------------------------------------------------*/ +/** @defgroup USART_RX_FIFO_Trigger_Level Definitions of USART Rx FIFO interrupts + * @{ + */ +#if (LIBCFG_USART_V01) +#define USART_RXTL_01 ((u32)0x00000000) +#define USART_RXTL_04 ((u32)0x00000010) +#define USART_RXTL_08 ((u32)0x00000020) +#define USART_RXTL_14 ((u32)0x00000030) + +#define IS_USART_RXTL(RXTL) ((RXTL == USART_RXTL_01) || \ + (RXTL == USART_RXTL_04) || \ + (RXTL == USART_RXTL_08) || \ + (RXTL == USART_RXTL_14)) +#else +#define USART_RXTL_01 ((u32)0x00000000) +#define USART_RXTL_02 ((u32)0x00000010) +#define USART_RXTL_04 ((u32)0x00000020) +#define USART_RXTL_06 ((u32)0x00000030) + +#define IS_USART_RXTL(RXTL) ((RXTL == USART_RXTL_01) || \ + (RXTL == USART_RXTL_02) || \ + (RXTL == USART_RXTL_04) || \ + (RXTL == USART_RXTL_06)) +#endif +/** + * @} + */ + +/* USART Tx FIFO Interrupt Trigger Level -------------------------------------------------------------------*/ +/** @defgroup USART_TX_FIFO_Trigger_Level Definitions of USART Tx FIFO interrupts + * @{ + */ +#if (LIBCFG_USART_V01) +#define USART_TXTL_00 ((u32)0x00000000) +#define USART_TXTL_02 ((u32)0x00000010) +#define USART_TXTL_04 ((u32)0x00000020) +#define USART_TXTL_08 ((u32)0x00000030) + +#define IS_USART_TXTL(TXTL) ((TXTL == USART_TXTL_00) || \ + (TXTL == USART_TXTL_02) || \ + (TXTL == USART_TXTL_04) || \ + (TXTL == USART_TXTL_08)) +#else +#define USART_TXTL_00 ((u32)0x00000000) +#define USART_TXTL_02 ((u32)0x00000010) +#define USART_TXTL_04 ((u32)0x00000020) +#define USART_TXTL_06 ((u32)0x00000030) + +#define IS_USART_TXTL(TXTL) ((TXTL == USART_TXTL_00) || \ + (TXTL == USART_TXTL_02) || \ + (TXTL == USART_TXTL_04) || \ + (TXTL == USART_TXTL_06)) +#endif +/** + * @} + */ + +/* USART Interrupt definition ------------------------------------------------------------------------------*/ +/** @defgroup USART_Interrupt_Enable Definitions of USART interrupt Enable bits + * @{ + */ +#if (LIBCFG_USART_V01) +#define USART_INT_RXDR ((u32)0x00000001) +#define USART_INT_TXDE ((u32)0x00000002) +#define USART_INT_RLSIE ((u32)0x00000004) +#define USART_INT_MSIE ((u32)0x00000008) +#define USART_INT_TOUT ((u32)0x00000100) + +#if (LIBCFG_USART_V01_LEGACY) +#define USART_IER_RDAIE (USART_INT_RXDR) +#define USART_IER_THREIE (USART_INT_TXDE) +#define USART_IER_RLSIE (USART_INT_RLSIE) +#define USART_IER_MSIE (USART_INT_MSIE) +#endif + +#define IS_USART_INT(INT) ((((INT) & 0xFFFFFFF0) == 0) && ((INT) != 0)) + +#define USART_IID_RLS ((u8)0x06) +#define USART_IID_RDA ((u8)0x04) +#define USART_IID_CTI ((u8)0x0C) +#define USART_IID_THRE ((u8)0x02) +#define USART_IID_MS ((u8)0x00) +#define USART_IID_NON ((u8)0x01) + +#define IS_USART_IID(IID) ((IID == USART_IID_RLS) || \ + (IID == USART_IID_RDA) || \ + (IID == USART_IID_CTI) || \ + (IID == USART_IID_THRE) || \ + (IID == USART_IID_MS) || \ + (IID == USART_IID_NON)) + +#else +#define USART_INT_RXDR ((u32)0x00000001) +#define USART_INT_TXDE ((u32)0x00000002) +#define USART_INT_TXC ((u32)0x00000004) +#define USART_INT_OE ((u32)0x00000008) +#define USART_INT_PE ((u32)0x00000010) +#define USART_INT_FE ((u32)0x00000020) +#define USART_INT_BI ((u32)0x00000040) +#define USART_INT_RSADD ((u32)0x00000080) +#define USART_INT_TOUT ((u32)0x00000100) +#define USART_INT_CTS ((u32)0x00000200) + +#define IS_USART_INT(INT) ((((INT) & 0xFFFFFC00) == 0) && ((INT) != 0)) +#endif +/** + * @} + */ + +/* USART Flags ---------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Flag Definitions of USART flags + * @{ + */ +#if (LIBCFG_USART_V01) +#define USART_FLAG_RXDNE ((u32)0x00000001) +#define USART_FLAG_THRE ((u32)0x00000020) +#define USART_FLAG_TXC ((u32)0x00000040) +#define USART_FLAG_ERR ((u32)0x00000080) + +#define USART_FLAG_FROM_IIR ((u32)0x00000800) +#define USART_FLAG_MODIS ((u32)0x00000800) +#define USART_FLAG_TXDE ((u32)0x00000802) +#define USART_FLAG_RXDR ((u32)0x00000804) +#define USART_FLAG_RLSI ((u32)0x00000806) +#define USART_FLAG_TOUT ((u32)0x0000080C) + +#if (LIBCFG_USART_V01_LEGACY) +#define USART_LSR_RFDR (USART_FLAG_RXDNE) +#define USART_LSR_THRE (USART_FLAG_THRE) +#define USART_LSR_TE (USART_FLAG_TXC) +#define USART_LSR_ERR (USART_FLAG_ERR) +#endif + +#define IS_USART_FLAG(FLAG) ((FLAG == USART_FLAG_RXDNE) || \ + (FLAG == USART_FLAG_THRE) || \ + (FLAG == USART_FLAG_TXC) || \ + (FLAG == USART_FLAG_ERR) || \ + (FLAG == USART_FLAG_TXDE) || \ + (FLAG == USART_FLAG_RXDR) || \ + (FLAG == USART_FLAG_TOUT)) + +#define USART_LSR_OE ((u32)0x00000002) +#define USART_LSR_PE ((u32)0x00000004) +#define USART_LSR_FE ((u32)0x00000008) +#define USART_LSR_BI ((u32)0x00000010) +#define USART_LSR_RSADD ((u32)0x00000100) + +#else +#define USART_FLAG_RXDNE ((u32)0x00000001) +#define USART_FLAG_OE ((u32)0x00000002) +#define USART_FLAG_PE ((u32)0x00000004) +#define USART_FLAG_FE ((u32)0x00000008) +#define USART_FLAG_BI ((u32)0x00000010) +#define USART_FLAG_RXDR ((u32)0x00000020) +#define USART_FLAG_TOUT ((u32)0x00000040) +#define USART_FLAG_TXDE ((u32)0x00000080) +#define USART_FLAG_TXC ((u32)0x00000100) +#define USART_FLAG_RSADD ((u32)0x00000200) +#define USART_FLAG_CTSC ((u32)0x00000400) +#define USART_FLAG_CTSS ((u32)0x00000800) + +#define IS_USART_FLAG(FLAG) ((FLAG == USART_FLAG_RXDNE) || (FLAG == USART_FLAG_OE) || \ + (FLAG == USART_FLAG_PE) || (FLAG == USART_FLAG_FE) || \ + (FLAG == USART_FLAG_BI) || (FLAG == USART_FLAG_RXDR) || \ + (FLAG == USART_FLAG_TOUT) || (FLAG == USART_FLAG_TXDE) || \ + (FLAG == USART_FLAG_TXC) || (FLAG == USART_FLAG_RSADD) || \ + (FLAG == USART_FLAG_CTSC) || (FLAG == USART_FLAG_CTSS)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((FLAG == USART_FLAG_OE) || (FLAG == USART_FLAG_PE) || \ + (FLAG == USART_FLAG_FE) || (FLAG == USART_FLAG_BI) || \ + (FLAG == USART_FLAG_TOUT) || (FLAG == USART_FLAG_RSADD) || \ + (FLAG == USART_FLAG_CTSC)) +#endif +/** + * @} + */ + +/* USART RS485 definition ----------------------------------------------------------------------------------*/ +/** @defgroup USART_RS485 Definitions of USART RS485 + * @{ + */ +#define USART_RS485POLARITY_LOW ((u32)0x00000001) +#define USART_RS485POLARITY_HIGH ((u32)0xFFFFFFFE) + +#define IS_USART_RS485_POLARITY(POLARITY) ((POLARITY == USART_RS485POLARITY_LOW) || \ + (POLARITY == USART_RS485POLARITY_HIGH)) +/** + * @} + */ +#if (LIBCFG_USART_V01) +#define USART_FIFO_TX ((u32)0x00000004) +#define USART_FIFO_RX ((u32)0x00000002) +#else +#define USART_FIFO_TX ((u32)0x00000001) +#define USART_FIFO_RX ((u32)0x00000002) +#endif + +#define IS_USART_FIFO_DIRECTION(DIRECTION) ((DIRECTION == USART_FIFO_TX) || \ + (DIRECTION == USART_FIFO_RX)) + +#if (LIBCFG_USART_V01) +#define USART_STICK_LOW ((u32)0x00000010) +#define USART_STICK_HIGH ((u32)0xFFFFFFEF) +#else +#define USART_STICK_LOW ((u32)0x00001000) +#define USART_STICK_HIGH ((u32)0xFFFFEFFF) +#endif + +#define IS_USART_STICK_PARITY(PARITY) ((PARITY == USART_STICK_LOW) || (PARITY == USART_STICK_HIGH)) + +#if (LIBCFG_USART_V01) +#define USART_PDMAREQ_TX ((u32)0x00000010) +#define USART_PDMAREQ_RX ((u32)0x00000020) +#else +#define USART_PDMAREQ_TX ((u32)0x00000040) +#define USART_PDMAREQ_RX ((u32)0x00000080) +#endif + +#define IS_USART_PDMA_REQ(REQ) ((REQ == USART_PDMAREQ_TX) || (REQ == USART_PDMAREQ_RX)) + +#define IS_USART(USART) ((USART == HT_USART0) || \ + (IS_USART1(USART)) || \ + (USART == HT_UART0) || \ + (USART == HT_UART1)) + +#if (LIBCFG_NO_USART1) +#define IS_USART1(x) (0) +#else +#define IS_USART1(x) (x == HT_USART1) +#endif + +#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE > 0) && (BAUDRATE < 0x0044AA21)) +#define IS_USART_DATA(DATA) (DATA <= 0x1FF) +#define IS_USART_GUARD_TIME(TIME) (TIME <= 0xFF) +#define IS_USART_IRDA_PRESCALER(PRESCALER) (PRESCALER <= 0xFF) +#define IS_USART_TIMEOUT(TIMEOUT) (TIMEOUT <= 0x7F) +#define IS_USART_ADDRESS_MATCH_VALUE(VALUE) (VALUE <= 0xFF) +/** + * @} + */ + +#if (LIBCFG_USART_V01) +/* USART Modem definition ----------------------------------------------------------------------------------*/ +/** @defgroup USART_MODEM Definitions of USART Modem + * @{ + */ +#define USART_MODEM_DTR ((u32)0x00000000) +#define USART_MODEM_RTS ((u32)0x00000001) + +#define IS_USART_MODEM_PIN(PIN) ((PIN == USART_MODEM_DTR) || (PIN == USART_MODEM_RTS)) + +#define USART_MODEMSTATE_HIGH ((u32)0x00000000) +#define USART_MODEMSTATE_LOW ((u32)0x00000001) + +#define IS_USART_MODEM_STATE(STATE) ((STATE == USART_MODEMSTATE_HIGH) || (STATE == USART_MODEMSTATE_LOW)) +/** + * @} + */ +#endif + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Functions USART exported functions + * @{ + */ +#define USART_TxCmd(USARTx, NewState) USART_TxRxCmd(USARTx, USART_CMD_TX, NewState) +#define USART_RxCmd(USARTx, NewState) USART_TxRxCmd(USARTx, USART_CMD_RX, NewState) + +#define USART_TxPDMACmd(USARTx, NewState) USART_PDMACmd(USARTx, USART_PDMAREQ_TX, NewState) +#define USART_RxPDMACmd(USARTx, NewState) USART_PDMACmd(USARTx, USART_PDMAREQ_RX, NewState) + +#define USART_RXTLConfig(USARTx, USART_tl) USART_TXRXTLConfig(USARTx, USART_CMD_RX, USART_tl) +#define USART_TXTLConfig(USARTx, USART_tl) USART_TXRXTLConfig(USARTx, USART_CMD_TX, USART_tl) + +#define USART_IrDAInvtOutputCmd(USARTx, NewState) USART_IrDAInvtCmd(USARTx, USART_CMD_OUT, NewState) +#define USART_IrDAInvtInputCmd(USARTx, NewState) USART_IrDAInvtCmd(USARTx, USART_CMD_IN, NewState) + +void USART_DeInit(HT_USART_TypeDef* USARTx); +void USART_Init(HT_USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStructure); +void USART_StructInit(USART_InitTypeDef* USART_InitStructure); +void USART_SendData(HT_USART_TypeDef* USARTx, u16 Data); +u16 USART_ReceiveData(HT_USART_TypeDef* USARTx); +FlagStatus USART_GetFlagStatus(HT_USART_TypeDef* USARTx, u32 USART_FLAG_x); +#if (LIBCFG_USART_V01) +#else +FlagStatus USART_GetIntStatus(HT_USART_TypeDef* USARTx, u32 USART_FLAG_x); +void USART_ClearFlag(HT_USART_TypeDef* USARTx, u32 USART_Flag); +#endif +void USART_IntConfig(HT_USART_TypeDef* USARTx, u32 USART_INT_x, ControlStatus NewState); +void USART_TxRxCmd(HT_USART_TypeDef* USARTx,u32 TxRx, ControlStatus NewState); +void USART_PDMACmd(HT_USART_TypeDef* USARTx, u32 USART_PDMAREQ, ControlStatus NewState); +void USART_ForceBreakCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_StickParityCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_StickParityConfig(HT_USART_TypeDef* USARTx, u32 USART_StickParity); + +void USART_SetGuardTime(HT_USART_TypeDef* USARTx, u32 USART_GuardTime); +void USART_TXRXTLConfig(HT_USART_TypeDef* USARTx, u32 TxRx, u32 USART_tl); +void USART_SetTimeOutValue(HT_USART_TypeDef* USARTx, u32 USART_TimeOut); +void USART_FIFOReset(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection); +u8 USART_GetFIFOStatus(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection); +void USART_HardwareFlowControlCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); + +void USART_IrDACmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_IrDAConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDAMode); +void USART_SetIrDAPrescaler(HT_USART_TypeDef* USARTx, u32 USART_IrDAPrescaler); +void USART_IrDADirectionConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDADirection); +void USART_IrDAInvtCmd(HT_USART_TypeDef* USARTx, u32 inout, ControlStatus NewState); + +void USART_RS485TxEnablePolarityConfig(HT_USART_TypeDef* USARTx, u32 USART_RS485Polarity); +void USART_RS485NMMCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_RS485AADCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_SetAddressMatchValue(HT_USART_TypeDef* USARTx, u32 USART_AddressMatchValue); + +void USART_SynClockInit(HT_USART_TypeDef* USARTx, USART_SynClock_InitTypeDef* USART_SynClock_InitStruct); +void USART_SynClockStructInit(USART_SynClock_InitTypeDef* USART_SynClock_InitStruct); + +#if (LIBCFG_USART_V01) +#if (LIBCFG_USART_V01_LEGACY) +#define USART_GetLineStatus USART_GetFlagStatus +#endif + +void USART_ForceModemPinState(HT_USART_TypeDef* USARTx, u32 USART_ModemPin, u32 USART_ModemState); +u8 USART_GetModemStatus(HT_USART_TypeDef* USARTx); +#define USART_TimeOutIntConfig(USARTx, NewState) USART_IntConfig(USARTx, USART_INT_TOUT, NewState) +//void USART_TimeOutIntConfig(HT_USART_TypeDef* USARTx, ControlStatus NewState); +u8 USART_GetIntID(HT_USART_TypeDef* USARTx); +u32 USART_GetLineStatusValue(HT_USART_TypeDef* USARTx); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbd.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbd.h new file mode 100644 index 00000000000..8f616a245bf --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbd.h @@ -0,0 +1,325 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_usbd.h + * @version $Rev:: 1670 $ + * @date $Date:: 2019-04-09 #$ + * @brief The header file of the USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_USBD_H +#define __HT32F1XXXX_USBD_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_01_usbdconf.h" +#include "ht32f1xxxx_usbdinit.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup USBDevice USB Device + * @brief USB Device driver modules + * @{ + */ + + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Settings USB Device settings + * @{ + */ +#define MAX_EP_NUM (8) +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Types USB Device exported types + * @{ + */ +/* USB Endpoint number */ +typedef enum +{ + USBD_EPT0 = 0, + USBD_EPT1 = 1, + USBD_EPT2 = 2, + USBD_EPT3 = 3, + USBD_EPT4 = 4, + USBD_EPT5 = 5, + USBD_EPT6 = 6, + USBD_EPT7 = 7, + USBD_NOEPT = -1, +} USBD_EPTn_Enum; + +typedef enum +{ + USBD_TCR_0 = 0, + USBD_TCR_1 = 16, +} USBD_TCR_Enum; + +typedef enum +{ + USBD_NAK = 0, + USBD_ACK = 1 +} USBD_Handshake_Enum; + +/* Endpoint CFGR Register */ +typedef struct _EPTCFGR_BIT +{ + vu32 EPBUFA: 10; + vu32 EPLEN : 10; + vu32 _RES0 : 3; + vu32 SDBS : 1; + vu32 EPADR : 4; + vu32 EPDIR : 1; + vu32 EPTYPE: 1; + vu32 _RES1 : 1; + vu32 EPEN : 1; +} USBD_EPTCFGR_Bit; + +typedef union _EPTCFGR_TYPEDEF +{ + USBD_EPTCFGR_Bit bits; + u32 word; +} USBD_EPTCFGR_TypeDef; + +/* Endpoint CFGR and IER Register */ +typedef struct +{ + USBD_EPTCFGR_TypeDef CFGR; + u32 IER; +} USBD_EPTInit_TypeDef; + +/* Endpoint 0 ~ MAX_EP_NUM */ +typedef struct +{ + u32 uInterruptMask; + USBD_EPTInit_TypeDef ept[MAX_EP_NUM]; +} USBD_Driver_TypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Constants USB Device exported constants + * @{ + */ + +/* USB Interrupt Enable Register (USBIER) */ +#define UGIE ((u32)0x00000001) /*!< USB global Interrupt Enable */ +#define SOFIE ((u32)0x00000002) /*!< Start Of Frame Interrupt Enable */ +#define URSTIE ((u32)0x00000004) /*!< USB Reset Interrupt Enable */ +#define RSMIE ((u32)0x00000008) /*!< Resume Interrupt Enable */ +#define SUSPIE ((u32)0x00000010) /*!< Suspend Interrupt Enable */ +#define ESOFIE ((u32)0x00000020) /*!< Expected Start Of Frame Interrupt Enable */ +#define FRESIE ((u32)0x00000040) /*!< Force USB Reset Control Interrupt Enable */ +#define EP0IE ((u32)0x00000100) /*!< Endpoint 0 Interrupt Enable */ +#define EP1IE ((u32)0x00000200) /*!< Endpoint 1 Interrupt Enable */ +#define EP2IE ((u32)0x00000400) /*!< Endpoint 2 Interrupt Enable */ +#define EP3IE ((u32)0x00000800) /*!< Endpoint 3 Interrupt Enable */ +#define EP4IE ((u32)0x00001000) /*!< Endpoint 4 Interrupt Enable */ +#define EP5IE ((u32)0x00002000) /*!< Endpoint 5 Interrupt Enable */ +#define EP6IE ((u32)0x00004000) /*!< Endpoint 6 Interrupt Enable */ +#define EP7IE ((u32)0x00008000) /*!< Endpoint 7 Interrupt Enable */ + +/* USB Interrupt Status Register (USBISR) */ +#define SOFIF ((u32)0x00000002) /*!< Start Of Frame Interrupt Flag */ +#define URSTIF ((u32)0x00000004) /*!< USB Reset Interrupt Flag */ +#define RSMIF ((u32)0x00000008) /*!< Resume Interrupt Flag */ +#define SUSPIF ((u32)0x00000010) /*!< Suspend Interrupt Flag */ +#define ESOFIF ((u32)0x00000020) /*!< Expected Start Of Frame Interrupt Flag */ +#define FRESIF ((u32)0x00000040) /*!< Force USB Reset Control Interrupt Flag */ +#define EP0IF ((u32)0x00000100) /*!< Endpoint 0 Interrupt flag */ +#define EP1IF ((u32)0x00000200) /*!< Endpoint 1 Interrupt flag */ +#define EP2IF ((u32)0x00000400) /*!< Endpoint 2 Interrupt flag */ +#define EP3IF ((u32)0x00000800) /*!< Endpoint 3 Interrupt flag */ +#define EP4IF ((u32)0x00001000) /*!< Endpoint 4 Interrupt flag */ +#define EP5IF ((u32)0x00002000) /*!< Endpoint 5 Interrupt flag */ +#define EP6IF ((u32)0x00004000) /*!< Endpoint 6 Interrupt flag */ +#define EP7IF ((u32)0x00008000) /*!< Endpoint 7 Interrupt flag */ +#define EPnIF ((u32)0x0000FF00) /*!< Endpoint n Interrupt flag */ + +/* USB Endpoint n Interrupt Enable Register (USBEPnIER) */ +#define OTRXIE ((u32)0x00000001) /*!< OUT Token Received Interrupt Enable */ +#define ODRXIE ((u32)0x00000002) /*!< OUT Data Received Interrupt Enable */ +#define ODOVIE ((u32)0x00000004) /*!< OUT Data Buffer Overrun Interrupt Enable */ +#define ITRXIE ((u32)0x00000008) /*!< IN Token Received Interrupt Enable */ +#define IDTXIE ((u32)0x00000010) /*!< IN Data Transmitted Interrupt Enable */ +#define NAKIE ((u32)0x00000020) /*!< NAK Transmitted Interrupt Enable */ +#define STLIE ((u32)0x00000040) /*!< STALL Transmitted Interrupt Enable */ +#define UERIE ((u32)0x00000080) /*!< USB Error Interrupt Enable */ +#define STRXIE ((u32)0x00000100) /*!< SETUP Token Received Interrupt Enable */ +#define SDRXIE ((u32)0x00000200) /*!< SETUP Data Received Interrupt Enable */ +#define SDERIE ((u32)0x00000400) /*!< SETUP Data Error Interrupt Enable */ +#define ZLRXIE ((u32)0x00000800) /*!< Zero Length Data Received Interrupt Enable */ + +/* USB Endpoint n Interrupt Status Register (USBEPnISR) */ +#define OTRXIF ((u32)0x00000001) /*!< OUT Token Received Interrupt Flag */ +#define ODRXIF ((u32)0x00000002) /*!< OUT Data Received Interrupt Flag */ +#define ODOVIF ((u32)0x00000004) /*!< OUT Data Buffer Overrun Interrupt Flag */ +#define ITRXIF ((u32)0x00000008) /*!< IN Token Received Interrupt Flag */ +#define IDTXIF ((u32)0x00000010) /*!< IN Data Transmitted Interrupt Flag */ +#define NAKIF ((u32)0x00000020) /*!< NAK Transmitted Interrupt Flag */ +#define STLIF ((u32)0x00000040) /*!< STALL Transmitted Interrupt Flag */ +#define UERIF ((u32)0x00000080) /*!< USB Error Interrupt Flag */ +#define STRXIF ((u32)0x00000100) /*!< SETUP Token Received Interrupt Flag */ +#define SDRXIF ((u32)0x00000200) /*!< SETUP Data Received Interrupt Flag */ +#define SDERIF ((u32)0x00000400) /*!< SETUP Data Error Interrupt Flag */ +#define ZLRXIF ((u32)0x00000800) /*!< Zero Length Data Received Interrupt Flag */ + +/* USB Endpoint n Control and Status Register (USBEPnCSR) */ +#define DTGTX ((u32)0x00000001) /*!< Data Toggle Status, for IN transfer */ +#define NAKTX ((u32)0x00000002) /*!< NAK Status, for IN transfer */ +#define STLTX ((u32)0x00000004) /*!< STALL Status, for IN transfer */ +#define DTGRX ((u32)0x00000008) /*!< Data Toggle Status, for OUT transfer */ +#define NAKRX ((u32)0x00000010) /*!< NAK Status, for OUT transfer */ +#define STLRX ((u32)0x00000020) /*!< STALL Status, for OUT transfer */ + +/* For USBD_EPTGetTranssferCount function */ +#define USBD_CNTB0 (USBD_TCR_0) +#define USBD_CNTB1 (USBD_TCR_1) +#define USBD_CNTIN (USBD_TCR_0) +#define USBD_CNTOUT (USBD_TCR_1) +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Macro USB Device exported macro + * @{ + */ +/* API macro for USB Core - Global event and operation */ +#define API_USB_INIT(driver) (USBD_Init(driver)) +#define API_USB_DEINIT() (USBD_DeInit()) +#define API_USB_POWER_UP(driver, power) (USBD_PowerUp(driver, power)) +#define API_USB_POWER_OFF() (USBD_PowerOff()) +#define API_USB_POWER_ON() (USBD_PowerOn()) +#define API_USB_REMOTE_WAKEUP() (USBD_RemoteWakeup()) +#define API_USB_READ_SETUP(buffer) (USBD_ReadSETUPData((u32 *)(buffer))) +#define API_USB_SET_ADDR(addr) (USBD_SetAddress(addr)) +#define API_USB_GET_CTRL_IN_LEN() (USBD_EPTGetBufferLen(USBD_EPT0)) +#define API_USB_ENABLE_INT(flag) (USBD_EnableINT(flag)) +#define API_USB_GET_INT() (USBD_GetINT()) +#define API_USB_GET_EPT_NUM(flag) (USBD_GetEPTnINTNumber(flag)) +#define API_USB_IS_SETUP_INT(flag) (flag & SDRXIF) +#define API_USB_CLR_SETUP_INT() (USBD_EPTClearINT(USBD_EPT0, SDRXIF)) +#define API_USB_IS_RESET_INT(flag) (flag & URSTIF) +#define API_USB_CLR_RESET_INT() (USBD_ClearINT(URSTIF)) +#define API_USB_IS_SOF_INT(flag) (flag & SOFIF) +#define API_USB_CLR_SOF_INT() (USBD_ClearINT(SOFIF)) +#define API_USB_IS_FRES_INT(flag) (flag & FRESIF) +#define API_USB_CLR_FRES_INT() (USBD_ClearINT(FRESIF)) +#define API_USB_IS_RESUME_INT(flag) (flag & RSMIF) +#define API_USB_CLR_RESUME_INT() (USBD_ClearINT(RSMIF)) +#define API_USB_IS_SUSPEND_INT(flag) (flag & SUSPIF) +#define API_USB_CLR_SUSPEND_INT() (USBD_ClearINT(SUSPIF)) +#define API_USB_IS_EPTn_INT(flag, EPTn) (flag & (EP0IF << EPTn)) +#define API_USB_CLR_EPTn_INT(EPTn) (USBD_ClearINT(EP0IF << EPTn)) + +/* API macro for USB Core - Endpoint event and operation */ +#define API_USB_EPTn_INIT(EPTn, driver) (USBD_EPTInit(EPTn, driver)) +#define API_USB_EPTn_RESET(EPTn) (USBD_EPTReset(EPTn)) +#define API_USB_EPTn_SEND_STALL(EPTn) (USBD_EPTSendSTALL(EPTn)) +#define API_USB_EPTn_GET_INT(EPTn) (USBD_EPTGetINT(EPTn)) +#define API_USB_EPTn_IS_IN_INT(flag) (flag & IDTXIF) +#define API_USB_EPTn_CLR_IN_INT(EPTn) (USBD_EPTClearINT(EPTn, IDTXIF)) +#define API_USB_EPTn_IS_OUT_INT(flag) (flag & ODRXIF) +#define API_USB_EPTn_CLR_OUT_INT(EPTn) (USBD_EPTClearINT(EPTn, ODRXIF)) +#define API_USB_EPTn_IS_INT(flag) (flag & (ODRXIF | IDTXIF)) +#define API_USB_EPTn_CLR_INT(EPTn) (USBD_EPTClearINT(EPTn, (ODRXIF | IDTXIF))) +#define API_USB_EPTn_GET_HALT(EPTn) (USBD_EPTGetHalt(EPTn)) +#define API_USB_EPTn_SET_HALT(EPTn) (USBD_EPTSetHalt(EPTn)) +#define API_USB_EPTn_CLR_HALT(EPTn) (USBD_EPTClearHalt(EPTn)) +#define API_USB_EPTn_WAIT_STALL_SENT(EPTn) (USBD_EPTWaitSTALLSent(EPTn)) +#define API_USB_EPTn_CLR_DTG(EPTn) (USBD_EPTClearDTG(EPTn)) +#define API_USB_EPTn_GET_BUFFLEN(EPTn) (USBD_EPTGetBufferLen(EPTn)) +#define API_USB_EPTn_GET_CNT(EPTn, type) (USBD_EPTGetTransferCount(EPTn, type)) +#define API_USB_EPTn_WRITE_IN(EPTn, from, len) (USBD_EPTWriteINData(EPTn, from, len)) +#define API_USB_EPTn_READ_OUT(EPTn, to, len) (USBD_EPTReadOUTData(EPTn, to, len)) +#define API_USB_EPTn_READ_MEM(EPTn, to, len) (USBD_EPTReadMemory(EPTn, to, len)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Functions USB Device exported functions + * @{ + */ +void USBD_Init(u32 *pDriver); +void USBD_PreInit(USBD_Driver_TypeDef *pDriver); +void USBD_DPpullupCmd(ControlStatus NewState); +void USBD_DPWakeUpCmd(ControlStatus NewState); +void USBD_DeInit(void); +void USBD_PowerUp(u32 *pDriver, u32 uIsSelfPowered); +void USBD_PowerOff(void); +void USBD_PowerOn(void); +void USBD_SRAMResetConditionCmd(ControlStatus NewState); +void USBD_DisableDefaultPull(void); +void USBD_RemoteWakeup(void); +void USBD_ReadSETUPData(u32 *pBuffer); +void USBD_SetAddress(u32 address); +void USBD_EnableINT(u32 INTFlag); +void USBD_DisableINT(u32 INTFlag); +u32 USBD_GetINT(void); +void USBD_ClearINT(u32 INTFlag); +USBD_EPTn_Enum USBD_GetEPTnINTNumber(u32 INTFlag); + +void USBD_EPTInit(USBD_EPTn_Enum USBD_EPTn, u32 *pDriver); +void USBD_EPTReset(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTEnableINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag); +u32 USBD_EPTGetINT(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTClearINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag); +void USBD_EPTSendSTALL(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetHalt(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTSetHalt(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTClearHalt(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTWaitSTALLSent(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTClearDTG(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetBuffer0Addr(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetBuffer1Addr(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetBufferLen(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetTransferCount(USBD_EPTn_Enum USBD_EPTn, USBD_TCR_Enum USBD_TCR_0or1); +u32 USBD_EPTWriteINData(USBD_EPTn_Enum USBD_EPTn, u32 *pFrom, u32 len); +u32 USBD_EPTReadOUTData(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +u32 USBD_EPTReadMemory(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbdchk.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbdchk.h new file mode 100644 index 00000000000..0109747eb3c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbdchk.h @@ -0,0 +1,504 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_usbdchk.h + * @version $Rev:: 122 $ + * @date $Date:: 2017-06-13 #$ + * @brief The header file of the USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_USBDCHK_H +#define __HT32F1XXXX_USBDCHK_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup USBDevice + * @{ + */ + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint 0 ~ 7 and checking */ +/* !!! DO NOT MODIFY !!! */ +/*----------------------------------------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP0LEN != 8 && _EP0LEN != 16 && _EP0LEN != 32 && _EP0LEN != 64) + #error "USB Buffer Length (EPLEN) of Control Endpoint0 must be 8, 16, 32, or 64 bytes." +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration and checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP1_ENABLE == 1) + #if (_EP1_TYPR == EP_TYPE_BULK) + #if (_EP1LEN != 8 && _EP1LEN != 16 && _EP1LEN != 32 && _EP1LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint1 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP1LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint1 must be less than 64 bytes." + #endif + #if (_EP1LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint1 cannot be 0 byte." + #endif + #if ((_EP1LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint1 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP2_ENABLE == 1) + #if (_EP2_TYPR == EP_TYPE_BULK) + #if (_EP2LEN != 8 && _EP2LEN != 16 && _EP2LEN != 32 && _EP2LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint2 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP2LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint2 must be less than 64 bytes." + #endif + #if (_EP2LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint2 cannot be 0 byte." + #endif + #if ((_EP2LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint2 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP3_ENABLE == 1) + #if (_EP3_TYPR == EP_TYPE_BULK) + #if (_EP3LEN != 8 && _EP3LEN != 16 && _EP3LEN != 32 && _EP3LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint3 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP3LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint3 must be less than 64 bytes." + #endif + #if (_EP3LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint3 cannot be 0 byte." + #endif + #if ((_EP3LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint3 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP4_ENABLE == 1) + #if (_EP4_TYPR == EP_TYPE_BULK) + #if (_EP4LEN != 8 && _EP4LEN != 16 && _EP4LEN != 32 && _EP4LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP4_TYPR == EP_TYPE_INT) + #if (_EP4LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP4_TYPR == EP_TYPE_ISO) + #if (_EP4LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP4LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint4 cannot be 0 byte." + #endif + #if ((_EP4LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP5_ENABLE == 1) + #if (_EP5_TYPR == EP_TYPE_BULK) + #if (_EP5LEN != 8 && _EP5LEN != 16 && _EP5LEN != 32 && _EP5LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP5_TYPR == EP_TYPE_INT) + #if (_EP5LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP5_TYPR == EP_TYPE_ISO) + #if (_EP5LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP5LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint5 cannot be 0 byte." + #endif + #if ((_EP5LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP6_ENABLE == 1) + #if (_EP6_TYPR == EP_TYPE_BULK) + #if (_EP6LEN != 8 && _EP6LEN != 16 && _EP6LEN != 32 && _EP6LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP6_TYPR == EP_TYPE_INT) + #if (_EP6LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP6_TYPR == EP_TYPE_ISO) + #if (_EP6LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP6LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint6 cannot be 0 byte." + #endif + #if ((_EP6LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP7_ENABLE == 1) + #if (_EP7_TYPR == EP_TYPE_BULK) + #if (_EP7LEN != 8 && _EP7LEN != 16 && _EP7LEN != 32 && _EP7LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP7_TYPR == EP_TYPE_INT) + #if (_EP7LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP7_TYPR == EP_TYPE_ISO) + #if (_EP7LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP7LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint7 cannot be 0 byte." + #endif + #if ((_EP7LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be a multiple of 4 (word-aligned)." + #endif +#endif + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Check the endpoint address */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP1_ENABLE == 1) + #if (_EP1_CFG_EPADR == 0) + #error "The address of Endpoint1 (EPADR) cannot be 0." + #endif + #if (_EP2_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint7." + #endif + #endif +#endif + +#if (_EP2_ENABLE == 1) + #if (_EP2_CFG_EPADR == 0) + #error "The address of Endpoint2 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint7." + #endif + #endif +#endif + +#if (_EP3_ENABLE == 1) + #if (_EP3_CFG_EPADR == 0) + #error "The address of Endpoint3 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint7." + #endif + #endif +#endif + +#if (_EP4_ENABLE == 1) + #if (_EP4_CFG_EPADR == 0) + #error "The address of Endpoint4 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint7." + #endif + #endif +#endif + +#if (_EP5_ENABLE == 1) + #if (_EP5_CFG_EPADR == 0) + #error "The address of Endpoint5 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint7." + #endif + #endif +#endif + +#if (_EP6_ENABLE == 1) + #if (_EP6_CFG_EPADR == 0) + #error "The address of Endpoint6 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint7." + #endif + #endif +#endif + +#if (_EP7_ENABLE == 1) + #if (_EP7_CFG_EPADR == 0) + #error "The address of Endpoint1 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint6." + #endif + #endif +#endif + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Check Buffer size */ +/*----------------------------------------------------------------------------------------------------------*/ +#if ((_EP0LEN_T + _EP1LEN + _EP2LEN + _EP3LEN + _EP4LEN_T + _EP5LEN_T + _EP6LEN_T + _EP7LEN_T) > 1024) + #error "Total buffer size of Endpoint 0 ~ 7 must be less than 1024 bytes." +#endif + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbdinit.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbdinit.h new file mode 100644 index 00000000000..b0cd17e96f6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_usbdinit.h @@ -0,0 +1,283 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_usbdinit.h + * @version $Rev:: 2971 $ + * @date $Date:: 2023-10-25 #$ + * @brief The header file of the USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_USBDINIT_H +#define __HT32F1XXXX_USBDINIT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32_retarget_usbdconf.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup USBDevice + * @{ + */ + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint 0 ~ 7 Configuration */ +/* !!! DO NOT MODIFY !!! */ +/*----------------------------------------------------------------------------------------------------------*/ + +#define EP_TYPE_ISO (1) +#define EP_TYPE_BULK (2) +#define EP_TYPE_INT (3) + +#ifndef _UIER_ALL + #define _UIER_ALL _UIER +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP0_CFG_EPEN (1UL) +#define _EP0STADR (HT_USB_SRAM_BASE + 0x8) +#define _EP0INTADR (_EP0STADR) +#define _EP0OUTTADR (_EP0STADR + _EP0LEN) +#define _EP0_CFG ((_EP0_CFG_EPEN << 31) | \ + (_EP0LEN << 10) | \ + (_EP0STADR & EPBUFA_MASK)) +#define _EP0LEN_T (_EP0LEN * 2) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP1STADR (_EP0STADR + (_EP0LEN * 2)) + +#if (_EP1_ENABLE == 1) + #define _EP1LEN (_EP1LEN_TMP) +#else + #define _EP1LEN (0) +#endif + +#if (_EP1_CFG_EPEN_TMP == 1) + #define _EP1_CFG_EPEN (1UL) +#else + #define _EP1_CFG_EPEN (0UL) +#endif + +#define _EP1_CFG ((_EP1_CFG_EPEN << 31) | \ + (_EP1_CFG_EPDIR << 28) | \ + (_EP1_CFG_EPADR << 24) | \ + (_EP1LEN << 10) | \ + (_EP1STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP2STADR (_EP1STADR + _EP1LEN) + +#if (_EP2_ENABLE == 1) + #define _EP2LEN (_EP2LEN_TMP) +#else + #define _EP2LEN (0) +#endif + +#if (_EP2_CFG_EPEN_TMP == 1) + #define _EP2_CFG_EPEN (1UL) +#else + #define _EP2_CFG_EPEN (0UL) +#endif + +#define _EP2_CFG ((_EP2_CFG_EPEN << 31) | \ + (_EP2_CFG_EPDIR << 28) | \ + (_EP2_CFG_EPADR << 24) | \ + (_EP2LEN << 10) | \ + (_EP2STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP3STADR (_EP2STADR + _EP2LEN) + +#if (_EP3_ENABLE == 1) + #define _EP3LEN (_EP3LEN_TMP) +#else + #define _EP3LEN (0) +#endif + +#if (_EP3_CFG_EPEN_TMP == 1) + #define _EP3_CFG_EPEN (1UL) +#else + #define _EP3_CFG_EPEN (0UL) +#endif + +#define _EP3_CFG ((_EP3_CFG_EPEN << 31) | \ + (_EP3_CFG_EPDIR << 28) | \ + (_EP3_CFG_EPADR << 24) | \ + (_EP3LEN << 10) | \ + (_EP3STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP4STADR (_EP3STADR + _EP3LEN) + +#if (_EP4_ENABLE == 1) + #define _EP4LEN (_EP4LEN_TMP) + #define _EP4LEN_T (_EP4LEN_TMP * (_EP4_CFG_SDBS + 1)) +#else + #define _EP4LEN (0) + #define _EP4LEN_T (0) +#endif +#if (_EP4_TYPR == EP_TYPE_ISO) + #define _EP4_CFG_EPTYPE (1) +#else + #define _EP4_CFG_EPTYPE (0) +#endif + +#if (_EP4_CFG_EPEN_TMP == 1) + #define _EP4_CFG_EPEN (1UL) +#else + #define _EP4_CFG_EPEN (0UL) +#endif + +#define _EP4_CFG ((_EP4_CFG_EPEN << 31) | \ + (_EP4_CFG_EPTYPE << 29) | \ + (_EP4_CFG_EPDIR << 28) | \ + (_EP4_CFG_EPADR << 24) | \ + (_EP4_CFG_SDBS << 23) | \ + (_EP4LEN << 10) | \ + (_EP4STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP5STADR (_EP4STADR + _EP4LEN_T) + +#if (_EP5_ENABLE == 1) + #define _EP5LEN (_EP5LEN_TMP) + #define _EP5LEN_T (_EP5LEN_TMP * (_EP5_CFG_SDBS + 1)) +#else + #define _EP5LEN (0) + #define _EP5LEN_T (0) +#endif +#if (_EP5_TYPR == EP_TYPE_ISO) + #define _EP5_CFG_EPTYPE (1) +#else + #define _EP5_CFG_EPTYPE (0) +#endif + +#if (_EP5_CFG_EPEN_TMP == 1) + #define _EP5_CFG_EPEN (1UL) +#else + #define _EP5_CFG_EPEN (0UL) +#endif + +#define _EP5_CFG ((_EP5_CFG_EPEN << 31) | \ + (_EP5_CFG_EPTYPE << 29) | \ + (_EP5_CFG_EPDIR << 28) | \ + (_EP5_CFG_EPADR << 24) | \ + (_EP5_CFG_SDBS << 23) | \ + (_EP5LEN << 10) | \ + (_EP5STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP6STADR (_EP5STADR + _EP5LEN_T) + +#if (_EP6_ENABLE == 1) + #define _EP6LEN (_EP6LEN_TMP) + #define _EP6LEN_T (_EP6LEN_TMP * (_EP6_CFG_SDBS + 1)) +#else + #define _EP6LEN (0) + #define _EP6LEN_T (0) +#endif +#if (_EP6_TYPR == EP_TYPE_ISO) + #define _EP6_CFG_EPTYPE (1) +#else + #define _EP6_CFG_EPTYPE (0) +#endif + +#if (_EP6_CFG_EPEN_TMP == 1) + #define _EP6_CFG_EPEN (1UL) +#else + #define _EP6_CFG_EPEN (0UL) +#endif + +#define _EP6_CFG ((_EP6_CFG_EPEN << 31) | \ + (_EP6_CFG_EPTYPE << 29) | \ + (_EP6_CFG_EPDIR << 28) | \ + (_EP6_CFG_EPADR << 24) | \ + (_EP6_CFG_SDBS << 23) | \ + (_EP6LEN << 10) | \ + (_EP6STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP7STADR (_EP6STADR + _EP6LEN_T) + +#if (_EP7_ENABLE == 1) + #define _EP7LEN (_EP7LEN_TMP) + #define _EP7LEN_T (_EP7LEN_TMP * (_EP7_CFG_SDBS + 1)) +#else + #define _EP7LEN (0) + #define _EP7LEN_T (0) +#endif +#if (_EP7_TYPR == EP_TYPE_ISO) + #define _EP7_CFG_EPTYPE (1) +#else + #define _EP7_CFG_EPTYPE (0) +#endif + +#if (_EP7_CFG_EPEN_TMP == 1) + #define _EP7_CFG_EPEN (1UL) +#else + #define _EP7_CFG_EPEN (0UL) +#endif + +#define _EP7_CFG ((_EP7_CFG_EPEN << 31) | \ + (_EP7_CFG_EPTYPE << 29) | \ + (_EP7_CFG_EPDIR << 28) | \ + (_EP7_CFG_EPADR << 24) | \ + (_EP7_CFG_SDBS << 23) | \ + (_EP7LEN << 10) | \ + (_EP7STADR & EPBUFA_MASK)) + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_wdt.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_wdt.h new file mode 100644 index 00000000000..c0a9c03951f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f1xxxx_wdt.h @@ -0,0 +1,148 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_wdt.h + * @version $Rev:: 122 $ + * @date $Date:: 2017-06-13 #$ + * @brief The header file of the WDT library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F1XXXX_WDT_H +#define __HT32F1XXXX_WDT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup WDT + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Exported_Constants WDT exported constants + * @{ + */ + +/* WDT prescaler */ +#define WDT_PRESCALER_1 ((u16)0x0000) +#define WDT_PRESCALER_2 ((u16)0x1000) +#define WDT_PRESCALER_4 ((u16)0x2000) +#define WDT_PRESCALER_8 ((u16)0x3000) +#define WDT_PRESCALER_16 ((u16)0x4000) +#define WDT_PRESCALER_32 ((u16)0x5000) +#define WDT_PRESCALER_64 ((u16)0x6000) +#define WDT_PRESCALER_128 ((u16)0x7000) + +#define IS_WDT_PRESCALER(PRESCALER) ((PRESCALER == WDT_PRESCALER_1) || \ + (PRESCALER == WDT_PRESCALER_2) || \ + (PRESCALER == WDT_PRESCALER_4) || \ + (PRESCALER == WDT_PRESCALER_8) || \ + (PRESCALER == WDT_PRESCALER_16) || \ + (PRESCALER == WDT_PRESCALER_32) || \ + (PRESCALER == WDT_PRESCALER_64) || \ + (PRESCALER == WDT_PRESCALER_128)) + + +/* WDT runs or halts in sleep and deep sleep1 mode */ +/* WDT WDTSHLT mask */ +#define MODE0_WDTSHLT_BOTH ((u32)0x00000000) +#define MODE0_WDTSHLT_SLEEP ((u32)0x00004000) +#define MODE0_WDTSHLT_HALT ((u32)0x00008000) + +#define IS_WDT_WDTSHLT_MODE(WDT_Mode) ((WDT_Mode == MODE0_WDTSHLT_BOTH) || \ + (WDT_Mode == MODE0_WDTSHLT_SLEEP) || \ + (WDT_Mode == MODE0_WDTSHLT_HALT)) + + + +/* WDT Flag */ +#define WDT_FLAG_UNDERFLOW ((u32)0x00000001) +#define WDT_FLAG_ERROR ((u32)0x00000002) + + +#define IS_WDT_FLAG(WDT_FLAG) ((WDT_FLAG == WDT_FLAG_UNDERFLOW) || \ + (WDT_FLAG == WDT_FLAG_ERROR)) + + +#define IS_WDT_RELOAD(WDTV) ((WDTV <= 0xFFF)) + +#define IS_WDT_DELTA(WDTD) ((WDTD <= 0xFFF)) + +/* WDT Source Select */ +#define WDT_SOURCE_LSI ((u32)0x00000000) +#define WDT_SOURCE_LSE ((u32)0x00000001) + + +#define IS_WDT_SOURCE_SELECT(WDT_SOURCE) ((WDT_SOURCE == WDT_SOURCE_LSI) || \ + (WDT_SOURCE == WDT_SOURCE_LSE)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Exported_Functions WDT exported functions + * @{ + */ +void WDT_DeInit(void); +void WDT_Cmd(ControlStatus NewState); +#if (LIBCFG_WDT_INT) +void WDT_IntConfig(ControlStatus NewState); +#endif +void WDT_HaltConfig(u32 WDT_Mode); +void WDT_ResetCmd(ControlStatus NewState); +void WDT_ProtectCmd(ControlStatus NewState); +void WDT_SetReloadValue(u16 WDTV); +u16 WDT_GetReloadValue(void); +void WDT_SetDeltaValue(u16 WDTD); +u16 WDT_GetDeltaValue(void); +void WDT_SetPrescaler(u16 WDT_PRESCALER); +u8 WDT_GetPrescaler(void); +void WDT_Restart(void); +FlagStatus WDT_GetFlagStatus (u32 WDT_FLAG); +void WDT_LockCmd(ControlStatus NewState); +void WDT_SourceConfig(u32 WDT_SOURCE); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f2xxxx_csif.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f2xxxx_csif.h new file mode 100644 index 00000000000..2460b561bae --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ht32f2xxxx_csif.h @@ -0,0 +1,302 @@ +/*********************************************************************************************************//** + * @file ht32f2xxxx_csif.h + * @version $Rev:: 122 $ + * @date $Date:: 2017-06-13 #$ + * @brief The header file of the CSIF library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F2XXXX_CSIF_H +#define __HT32F2XXXX_CSIF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CSIF + * @{ + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ + +/** @defgroup CSIF_Exported_Types CSIF exported types + * @{ + */ + +typedef struct +{ + u32 CSIF_Format; + u32 CSIF_VSYNCType; + u32 CSIF_HSYNCType; + u32 CSIF_SampleEdge; + u32 CSIF_VSYNCPolarity; + u32 CSIF_HSYNCPolarity; + u32 CSIF_LineDelay; + u32 CSIF_FrameDelay; + u32 CSIF_ImageWidth; + u32 CSIF_ImageHeight; +}CSIF_BasicInitTypeDef; + + +typedef struct +{ + u32 CSIF_Window; + u32 CSIF_HorizontalStartPoint; + u32 CSIF_VerticalStartPoint; + u32 CSIF_WindowWidth; + u32 CSIF_WindowHeight; +}CSIF_WindowInitTypeDef; + + +typedef struct +{ + u32 CSIF_SubSample; + u32 CSIF_ColumnSkipMaskLength; + u32 CSIF_RowSkipMaskLength; + u32 CSIF_ColumnSkipMask; + u32 CSIF_RowSkipMask; +}CSIF_SubSampleInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CSIF_Exported_Constants CSIF exported constants + * @{ + */ + +#define CSIF_FORMAT_RAWRGB ((u32)0x00000000) +#define CSIF_FORMAT_YUV422 ((u32)0x00000010) + +#define IS_CSIF_FORMAT(FORMAT) ((FORMAT == CSIF_FORMAT_RAWRGB) || \ + (FORMAT == CSIF_FORMAT_YUV422)) + + +#define CSIF_VSYNCTYPE_PULSE ((u32)0x00000000) +#define CSIF_VSYNCTYPE_OVERLAP ((u32)0x00000002) + +#define IS_CSIF_VSYNC_TYPE(TYPE) ((TYPE == CSIF_VSYNCTYPE_PULSE) || \ + (TYPE == CSIF_VSYNCTYPE_OVERLAP)) + + +#define CSIF_HSYNCTYPE_CONTINUOUS ((u32)0x00000000) +#define CSIF_HSYNCTYPE_DISCONTINUOUS ((u32)0x00000004) + +#define IS_CSIF_HSYNC_TYPE(TYPE) ((TYPE == CSIF_HSYNCTYPE_CONTINUOUS) || \ + (TYPE == CSIF_HSYNCTYPE_DISCONTINUOUS)) + + +#define CSIF_SAMPLEEDGE_FALLING ((u32)0x00000000) +#define CSIF_SAMPLEEDGE_RISING ((u32)0x00000008) + +#define IS_CSIF_SAMPLE_EDGE(EDGE) ((EDGE == CSIF_SAMPLEEDGE_FALLING) || \ + (EDGE == CSIF_SAMPLEEDGE_RISING)) + + +#define CSIF_VSYNCPOLARITY_HIGH ((u32)0x00000000) +#define CSIF_VSYNCPOLARITY_LOW ((u32)0x00000040) + +#define IS_CSIF_VSYNC_POLARITY(POLARITY) ((POLARITY == CSIF_VSYNCPOLARITY_HIGH) || \ + (POLARITY == CSIF_VSYNCPOLARITY_LOW)) + + +#define CSIF_HSYNCPOLARITY_HIGH ((u32)0x00000000) +#define CSIF_HSYNCPOLARITY_LOW ((u32)0x00000080) + +#define IS_CSIF_HSYNC_POLARITY(POLARITY) ((POLARITY == CSIF_HSYNCPOLARITY_HIGH) || \ + (POLARITY == CSIF_HSYNCPOLARITY_LOW)) + + +#define CSIF_WINDOW_ENABLE ((u32)0x80000000) +#define CSIF_WINDOW_DISABLE ((u32)0x00000000) + +#define IS_CSIF_WINDOW(WINDOW) ((WINDOW == CSIF_WINDOW_ENABLE) || \ + (WINDOW == CSIF_WINDOW_DISABLE)) + + +#define CSIF_SUBSAMPLE_ENABLE ((u32)0x80000000) +#define CSIF_SUBSAMPLE_DISABLE ((u32)0x00000000) + +#define IS_CSIF_SUB_SAMPLE(SAMPLE) ((SAMPLE == CSIF_SUBSAMPLE_ENABLE) || \ + (SAMPLE == CSIF_SUBSAMPLE_DISABLE)) + + +#define CSIF_MASKLENGTH_1B ((u32)0x00000000) +#define CSIF_MASKLENGTH_2B ((u32)0x00000001) +#define CSIF_MASKLENGTH_3B ((u32)0x00000002) +#define CSIF_MASKLENGTH_4B ((u32)0x00000003) +#define CSIF_MASKLENGTH_5B ((u32)0x00000004) +#define CSIF_MASKLENGTH_6B ((u32)0x00000005) +#define CSIF_MASKLENGTH_7B ((u32)0x00000006) +#define CSIF_MASKLENGTH_8B ((u32)0x00000007) +#define CSIF_MASKLENGTH_9B ((u32)0x00000008) +#define CSIF_MASKLENGTH_10B ((u32)0x00000009) +#define CSIF_MASKLENGTH_11B ((u32)0x0000000A) +#define CSIF_MASKLENGTH_12B ((u32)0x0000000B) +#define CSIF_MASKLENGTH_13B ((u32)0x0000000C) +#define CSIF_MASKLENGTH_14B ((u32)0x0000000D) +#define CSIF_MASKLENGTH_15B ((u32)0x0000000E) +#define CSIF_MASKLENGTH_16B ((u32)0x0000000F) +#define CSIF_MASKLENGTH_17B ((u32)0x00000010) +#define CSIF_MASKLENGTH_18B ((u32)0x00000011) +#define CSIF_MASKLENGTH_19B ((u32)0x00000012) +#define CSIF_MASKLENGTH_20B ((u32)0x00000013) +#define CSIF_MASKLENGTH_21B ((u32)0x00000014) +#define CSIF_MASKLENGTH_22B ((u32)0x00000015) +#define CSIF_MASKLENGTH_23B ((u32)0x00000016) +#define CSIF_MASKLENGTH_24B ((u32)0x00000017) +#define CSIF_MASKLENGTH_25B ((u32)0x00000018) +#define CSIF_MASKLENGTH_26B ((u32)0x00000019) +#define CSIF_MASKLENGTH_27B ((u32)0x0000001A) +#define CSIF_MASKLENGTH_28B ((u32)0x0000001B) +#define CSIF_MASKLENGTH_29B ((u32)0x0000001C) +#define CSIF_MASKLENGTH_30B ((u32)0x0000001D) +#define CSIF_MASKLENGTH_31B ((u32)0x0000001E) +#define CSIF_MASKLENGTH_32B ((u32)0x0000001F) + +#define IS_CSIF_MASK_LENGTH(LENGTH) (LENGTH <= 0x1F) + + +#define CSIF_FIFO_0 ((u8)0x20) +#define CSIF_FIFO_1 ((u8)0x24) +#define CSIF_FIFO_2 ((u8)0x28) +#define CSIF_FIFO_3 ((u8)0x2C) +#define CSIF_FIFO_4 ((u8)0x30) +#define CSIF_FIFO_5 ((u8)0x34) +#define CSIF_FIFO_6 ((u8)0x38) +#define CSIF_FIFO_7 ((u8)0x3C) + +#define IS_CSIF_FIFO(FIFO) ((FIFO == CSIF_FIFO_0) || \ + (FIFO == CSIF_FIFO_1) || \ + (FIFO == CSIF_FIFO_2) || \ + (FIFO == CSIF_FIFO_3) || \ + (FIFO == CSIF_FIFO_4) || \ + (FIFO == CSIF_FIFO_5) || \ + (FIFO == CSIF_FIFO_6) || \ + (FIFO == CSIF_FIFO_7)) + +#define CSIF_INT_SOFFLG ((u32)0x00000001) +#define CSIF_INT_EOFFLG ((u32)0x00000002) +#define CSIF_INT_CAPSTA ((u32)0x00000004) +#define CSIF_INT_CAPSTS ((u32)0x00000008) +#define CSIF_INT_BADFRAME ((u32)0x00000010) +#define CSIF_INT_FIFOOVR ((u32)0x00000100) +#define CSIF_INT_FIFOEMP ((u32)0x00000200) +#define CSIF_INT_FIFOFUL ((u32)0x00000400) +#define CSIF_INT_ALL ((u32)0x0000071F) + +#define IS_CSIF_INT(INT) (((INT & 0xFFFFF8E0) == 0x0) && (INT != 0x0)) + + + +#define CSIF_FLAG_SOFFLG ((u32)0x00000001) +#define CSIF_FLAG_EOFFLG ((u32)0x00000002) +#define CSIF_FLAG_CAPSTA ((u32)0x00000004) +#define CSIF_FLAG_CAPSTS ((u32)0x00000008) +#define CSIF_FLAG_BADFRAME ((u32)0x00000010) +#define CSIF_FLAG_FIFOOVR ((u32)0x00000100) +#define CSIF_FLAG_FIFOEMP ((u32)0x00000200) +#define CSIF_FLAG_FIFOFUL ((u32)0x00000400) + +#define IS_CSIF_FLAG(FLAG) ((FLAG == CSIF_FLAG_SOFFLG) || \ + (FLAG == CSIF_FLAG_EOFFLG) || \ + (FLAG == CSIF_FLAG_CAPSTA) || \ + (FLAG == CSIF_FLAG_CAPSTS) || \ + (FLAG == CSIF_FLAG_BADFRAME) || \ + (FLAG == CSIF_FLAG_FIFOOVR) || \ + (FLAG == CSIF_FLAG_FIFOEMP) || \ + (FLAG == CSIF_FLAG_FIFOFUL)) + +#define IS_CSIF_CLEAR_FLAG(FLAG) ((FLAG == CSIF_FLAG_SOFFLG) || \ + (FLAG == CSIF_FLAG_EOFFLG) || \ + (FLAG == CSIF_FLAG_CAPSTA) || \ + (FLAG == CSIF_FLAG_CAPSTS) || \ + (FLAG == CSIF_FLAG_BADFRAME)) + + +#define IS_CSIF_LINE_DELAY(DELAY) (DELAY <= 0xFF) + +#define IS_CSIF_FRAME_DELAY(DELAY) (DELAY <= 0xFF) + +#define IS_CSIF_IMAGE_WIDTH(WIDTH) (WIDTH <= 0x800) + +#define IS_CSIF_IMAGE_HEIGHT(HEIGHT) (HEIGHT <= 0x800) + +#define IS_CSIF_HORSTART_POINT(POINT) (POINT <= 0x7FF) + +#define IS_CSIF_VERSTART_POINT(POINT) (POINT <= 0x7FF) + +#define IS_CSIF_WINDOW_WIDTH(WIDTH) (WIDTH <= 0x800) + +#define IS_CSIF_WINDOW_HEIGHT(HEIGHT) (HEIGHT <= 0x800) + +#define IS_CSIF_PRESCALER(PRESCALER) ((PRESCALER%2 == 0) && (PRESCALER != 0)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CSIF_Exported_Functions CSIF exported functions + * @{ + */ +void CSIF_DeInit(void); +void CSIF_BasicInit(CSIF_BasicInitTypeDef* CSIF_BasicInitStruct); +void CSIF_BasicStructInit(CSIF_BasicInitTypeDef* CSIF_BasicInitStruct); +void CSIF_WindowInit(CSIF_WindowInitTypeDef* CSIF_WindowInitStruct); +void CSIF_WindowStructInit(CSIF_WindowInitTypeDef* CSIF_WindowInitStruct); +void CSIF_SubSampleInit(CSIF_SubSampleInitTypeDef* CSIF_SubSampleInitStruct); +void CSIF_SunSampleStructInit(CSIF_SubSampleInitTypeDef* CSIF_SubSampleInitStruct); +void CSIF_Cmd(ControlStatus NewState); +void CSIF_IntConfig(u32 CSIF_Int, ControlStatus NewState); +FlagStatus CSIF_GetFlagStatus(u32 CSIF_Flag); +void CSIF_ClearFlag(u32 CSIF_Flag); +u32 CSIF_ReceiveData(u8 CSIF_FIFO); +void CSIF_MasterClockCmd(ControlStatus NewState); +void CSIF_SetMasterClockPrescaler(u8 CSIF_Prescaler); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_cm3_misc.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_cm3_misc.c new file mode 100644 index 00000000000..c9632a267d1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_cm3_misc.c @@ -0,0 +1,232 @@ +/*********************************************************************************************************//** + * @file ht32_cm3_misc.c + * @version $Rev:: 2437 $ + * @date $Date:: 2021-06-01 #$ + * @brief This file provides all the miscellaneous firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32_cm3_misc.h" +#include "ht32_rand.c" +#ifdef HTCFG_TIME_IPSEL +#include "ht32_time.c" +#endif + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup MISC MISC + * @brief MISC driver modules + * @{ + */ + + +/* Private definitions -------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Private_Define MISC private definitions + * @{ + */ +#define AIRCR_VECTKEY_MASK ((u32)0x05FA0000) +#define CTRL_TICKINT_SET ((u32)0x00000002) +#define CTRL_TICKINT_RESET ((u32)0xFFFFFFFD) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Exported_Functions MISC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Set the vector table location and Offset. + * @param NVIC_VectTable: Specify if the vector table is in FLASH or RAM. + * This parameter can be one of the following values: + * @arg NVIC_VECTTABLE_RAM + * @arg NVIC_VECTTABLE_FLASH + * @param NVIC_Offset: Vector Table base offset field. + * This value must be a multiple of 0x100. + * @retval None + ***********************************************************************************************************/ +void NVIC_SetVectorTable(u32 NVIC_VectTable, u32 NVIC_Offset) +{ + /* Check the parameters */ + Assert_Param(IS_NVIC_VECTTABLE(NVIC_VectTable)); + Assert_Param(IS_NVIC_OFFSET(NVIC_Offset)); + + SCB->VTOR = NVIC_VectTable | (NVIC_Offset & (u32)0x1FFFFF80); +} + +/*********************************************************************************************************//** + * @brief Select which low power mode to execute to the system. + * @param NVIC_LowPowerMode: Specify the new low power mode to execute to the system. + * This parameter can be one of the following values: + * @arg NVIC_LOWPOWER_SEVONPEND + * @arg NVIC_LOWPOWER_SLEEPDEEP + * @arg NVIC_LOWPOWER_SLEEPONEXIT + * @param NewState: new state of low power condition. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void NVIC_LowPowerConfig(u8 NVIC_LowPowerMode, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_NVIC_LOWPOWER(NVIC_LowPowerMode)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= NVIC_LowPowerMode; + } + else + { + SCB->SCR &= (u32)(~(u32)NVIC_LowPowerMode); + } +} + +/*********************************************************************************************************//** + * @brief Generate a Core (Core + NVIC) reset. + * @retval None + ***********************************************************************************************************/ +void NVIC_CoreReset(void) +{ + SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x01; +} + +/*********************************************************************************************************//** + * @brief Set the pending bit for a system handler. + * @param SystemHandler: Specify the system handler pending bit to be set. + * This parameter can be one of the following values: + * @arg SYSTEMHANDLER_NMI + * @arg SYSTEMHANDLER_PSV + * @arg SYSTEMHANDLER_SYSTICK + * @retval None + ***********************************************************************************************************/ +void NVIC_SetPendingSystemHandler(u32 SystemHandler) +{ + /* Check the parameters */ + Assert_Param(IS_NVIC_SYSTEMHANDLER(SystemHandler)); + + /* Set the corresponding System Handler pending bit */ + SCB->ICSR |= SystemHandler; +} + +/*********************************************************************************************************//** + * @brief Configure the SysTick clock source. + * @param SysTick_ClockSource: Specify the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_SRC_STCLK : External reference clock is selected as SysTick clock source. + * @arg SYSTICK_SRC_FCLK : AHB clock is selected as SysTick clock source. + * @retval None + ***********************************************************************************************************/ +void SYSTICK_ClockSourceConfig(u32 SysTick_ClockSource) +{ + /* Check the parameters */ + Assert_Param(IS_SYSTICK_CLOCK_SOURCE(SysTick_ClockSource)); + + if (SysTick_ClockSource == SYSTICK_SRC_FCLK) + { + SysTick->CTRL |= SYSTICK_SRC_FCLK; + } + else + { + SysTick->CTRL &= SYSTICK_SRC_STCLK; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SysTick counter. + * @param SysTick_Counter: new state of the SysTick counter. + * This parameter can be one of the following values: + * @arg SYSTICK_COUNTER_DISABLE : Disable counter + * @arg SYSTICK_COUNTER_ENABLE : Enable counter + * @arg SYSTICK_COUNTER_CLEAR : Clear counter value to 0 + * @retval None + ***********************************************************************************************************/ +void SYSTICK_CounterCmd(u32 SysTick_Counter) +{ + /* Check the parameters */ + Assert_Param(IS_SYSTICK_COUNTER(SysTick_Counter)); + + if (SysTick_Counter == SYSTICK_COUNTER_CLEAR) + { + SysTick->VAL = SYSTICK_COUNTER_CLEAR; + } + else + { + if (SysTick_Counter == SYSTICK_COUNTER_ENABLE) + { + SysTick->CTRL |= SYSTICK_COUNTER_ENABLE; + } + else + { + SysTick->CTRL &= SYSTICK_COUNTER_DISABLE; + } + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SysTick Interrupt. + * @param NewState: new state of the SysTick Interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void SYSTICK_IntConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SysTick->CTRL |= CTRL_TICKINT_SET; + } + else + { + SysTick->CTRL &= CTRL_TICKINT_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Set SysTick counter reload value. + * @param SysTick_Reload: SysTick reload new value. + * This parameter must be a number between 1 and 0xFFFFFF. + * @retval None + ***********************************************************************************************************/ +void SYSTICK_SetReloadValue(u32 SysTick_Reload) +{ + /* Check the parameters */ + Assert_Param(IS_SYSTICK_RELOAD(SysTick_Reload)); + + SysTick->LOAD = SysTick_Reload; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_rand.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_rand.c new file mode 100644 index 00000000000..5b47d8884f6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_rand.c @@ -0,0 +1,106 @@ +/*********************************************************************************************************//** + * @file ht32_rand.c + * @version $Rev:: 1736 $ + * @date $Date:: 2019-06-25 #$ + * @brief The rundom number function. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include + +/* Global variables ----------------------------------------------------------------------------------------*/ +#if !(LIBCFG_ADC_V01) +__ALIGN4 static uc32 RandData[] = +{ + 0x4fffe92d, 0xb0844948, 0x94016a4c, 0x94006b0c, + 0xf4446a4c, 0x624c3440, 0x4d446b0c, 0x630c432c, + 0x2135ea4f, 0xf004688c, 0xf5a40480, 0x608c4479, + 0x2403ea42, 0x4402ea44, 0x6403ea44, 0xea42610c, + 0xea442402, 0xea444403, 0x614c6403, 0x0282eb01, + 0x67142417, 0x0283eb01, 0x22016714, 0x2100f8c1, + 0xf042688a, 0x608a0280, 0x90c4f8df, 0x2004f8d9, + 0x4a309202, 0x93036853, 0x73fff64f, 0x3004f8c9, + 0xf8d96053, 0x69d7601c, 0x2104f8d1, 0x0201f042, + 0x2104f8c1, 0x2134f8d1, 0xd5fb0752, 0x2fb0f851, + 0x0b0ff002, 0xf002684a, 0x688a0e0f, 0x0a0ff002, + 0xf00268ca, 0x690a050f, 0x040ff002, 0xf002694a, + 0x698a030f, 0xf00269c9, 0xf8d0020f, 0xf8d9c000, + 0x44c4801c, 0xeb064466, 0x4f164607, 0xf8d76006, + 0xea4bc01c, 0xeb06180e, 0xea4f460c, 0xea4c2c0a, + 0xea483505, 0xea480805, 0xea444404, 0xea435303, + 0xea426202, 0x9a057101, 0x44114431, 0x98026001, + 0x0004f8c9, 0x60789803, 0x99014803, 0x99006241, + 0xb0086301, 0x8ff0e8bd, 0x40088000, 0x01000040, + 0x400b0000, 0x400b2000 +}; +#else +__ALIGN4 static uc32 RandData[] = +{ + 0x4946b5ff, 0x6a4cb087, 0x6b0c9404, 0x6a4c9403, + 0x042d2503, 0x624c432c, 0x4d416b0c, 0x630c432c, + 0x68394f40, 0x2580463c, 0x402926f9, 0x1b890236, + 0x021e6039, 0x04114316, 0x0619430e, 0x607e430e, + 0x43160216, 0x4316041a, 0x60a6430e, 0x62212117, + 0x22014934, 0x630a3140, 0x432b6823, 0x4e326023, + 0x93056873, 0x685c4b31, 0x4c319406, 0x605c6074, + 0x69dd69f4, 0x43136b4b, 0x4a2a634b, 0x68533280, + 0xd5fc075b, 0x463a6b3b, 0x0f1b071b, 0x6b7b9302, + 0x071b6bbf, 0x073f0f1b, 0x97010f3f, 0x07176bd2, + 0x680a0f3f, 0x071746bc, 0x97000f3f, 0x0717684a, + 0x688a0f3f, 0x071246be, 0x0f1268c9, 0x68074e1a, + 0x042d69f6, 0x193419be, 0x4d181964, 0x69ed6004, + 0x011b9e02, 0x431e9f01, 0x023b042d, 0x46671964, + 0x432b033d, 0x431e9f00, 0x431e043b, 0x053b4677, + 0x0612431e, 0x07094316, 0x9a08430e, 0x18891931, + 0x48096001, 0x60419905, 0x99064808, 0x48036041, + 0x62419904, 0x63019903, 0xbdf0b00b, 0x40088000, + 0x01000040, 0x40010000, 0x400b0000, 0x400b2000, + 0x0000ffff +}; +#endif +__ALIGN4 static uc32 RandData2[] = +{ + 0x4604b510, 0x18406800, 0x46216020, 0x68084a03, + 0x4a034350, 0x60081880, 0xbd100840, 0x41c64e6d, + 0x00003039 +}; + +typedef void (*Randinit_TypeDef) (u32 *, u32, u32, u32); +u32 (*Rand_Get)(u32 *, u32); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/*********************************************************************************************************//** + * @brief Rand init. + * @param uSeed + * @param uCount + * @param a + * @param b + * @retval none + ***********************************************************************************************************/ +void Rand_Init(u32 *uSeed, u32 uCount, u32 a, u32 b) +{ + Randinit_TypeDef Randinit = (Randinit_TypeDef)((u32)RandData | 0x1); + Rand_Get = (u32 (*)(u32 *, u32))((u32)RandData2 | 0x1); + Randinit(uSeed, uCount, a, b); +} diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_retarget.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_retarget.c new file mode 100644 index 00000000000..27ea3a0dfd7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_retarget.c @@ -0,0 +1,413 @@ +/*********************************************************************************************************//** + * @file ht32_retarget.c + * @version $Rev:: 2922 $ + * @date $Date:: 2023-06-07 #$ + * @brief Retarget layer for target-dependent low level functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_board.h" + +#if defined (__CC_ARM) + #pragma import(__use_no_semihosting_swi) +#endif + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #ifndef __MICROLIB + __asm(".global __use_no_semihosting"); + #endif +#endif + +#if (_RETARGET == 1) +#include + +#if defined (__CC_ARM) + #include +#endif + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup RETARGET Retarget + * @brief Retarget related functions + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup RETARGET_Private_Define Retarget private definitions + * @{ + */ + +#if (RETARGET_PORT == RETARGET_ITM) +#define ITM_PORT8(n) (*((vu8 *)(0xE0000000 + 4 * n))) +#define ITM_PORT16(n) (*((vu16 *)(0xE0000000 + 4 * n))) +#define ITM_PORT32(n) (*((vu32 *)(0xE0000000 + 4 * n))) + +#define DEMCR (*((vu32 *)(0xE000EDFC))) +#define TRCENA (0x01000000) +volatile int32_t ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* For Keil MDK-ARM only */ +#endif +/** + * @} + */ + +/* Global variables ----------------------------------------------------------------------------------------*/ +/** @defgroup RETARGET_Global_Variable Retarget global variables + * @{ + */ +#if defined (__CC_ARM) +struct __FILE { int handle; /* Add whatever you need here */ }; +FILE __stdout; +FILE __stdin; +#endif + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #ifndef __MICROLIB + FILE __stdout; + FILE __stdin; + FILE __stderr; + #endif +#endif + +#if defined (__SES_ARM) && defined(__SEGGER_RTL_VERSION) +struct __SEGGER_RTL_FILE_impl { // NOTE: Provides implementation for FILE + int stub; // only needed so impl has size != 0. +}; +static FILE __SEGGER_RTL_stdin_file = { 0 }; // stdin reads from UART +static FILE __SEGGER_RTL_stdout_file = { 0 }; // stdout writes to UART +static FILE __SEGGER_RTL_stderr_file = { 0 }; // stderr writes to UART + +FILE *stdin = &__SEGGER_RTL_stdin_file; // NOTE: Provide implementation of stdin for RTL. +FILE *stdout = &__SEGGER_RTL_stdout_file; // NOTE: Provide implementation of stdout for RTL. +FILE *stderr = &__SEGGER_RTL_stderr_file; // NOTE: Provide implementation of stderr for RTL. + +static int _stdin_ungot = EOF; +#endif +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup RETARGET_Exported_Functions Retarget exported functions + * @{ + */ + +void RETARGET_Configuration(void) +{ +#ifdef RETARGET_IS_UART + /* !!! NOTICE !!! + Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below in this function. + */ + USART_InitTypeDef USART_InitStructure; + #ifdef RETARGET_UxART_BAUDRATE + USART_InitStructure.USART_BaudRate = RETARGET_UxART_BAUDRATE; + #else + USART_InitStructure.USART_BaudRate = 115200; + #endif + USART_InitStructure.USART_WordLength = USART_WORDLENGTH_8B; + USART_InitStructure.USART_StopBits = USART_STOPBITS_1; + USART_InitStructure.USART_Parity = USART_PARITY_NO; + USART_InitStructure.USART_Mode = USART_MODE_NORMAL; + + #ifdef RETARGET_COM_PORT + HT32F_DVB_COMInit(RETARGET_COM_PORT, &USART_InitStructure); + #else + { /* Enable peripheral clock of UxART */ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + CKCUClock.Bit.RETARGET_UxART_IPN = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + } + + USART_Init(RETARGET_USART_PORT, &USART_InitStructure); + USART_TxCmd(RETARGET_USART_PORT, ENABLE); + USART_RxCmd(RETARGET_USART_PORT, ENABLE); + #if (RETARGET_INT_MODE == 1) + NVIC_EnableIRQ(RETARGET_UART_IRQn); + #endif + #endif +#endif + +#if (RETARGET_PORT == RETARGET_ITM) + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.AFIO = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + CKCU_MCUDBGConfig(CKCU_DBG_TRACE_ON, ENABLE); + AFIO_GPxConfig(TRACESWO_GPIO_ID, TRACESWO_AFIO_PIN, TRACESWO_AFIO_MODE); +#endif + +#ifdef NON_USB_IN_APP + SERIAL_USBDInit(); +#endif +} + +int __backspace(FILE *stream) +{ + if (stream == 0) // Remove the compiler warning + { + } + return 0; +} + +/* + Keil and IAR before 9.20 share fputc() to implement printf +*/ +int fputc (int ch, FILE *f) +{ + #if 0 + if (f == 0) // Remove the compiler warning + { + } + #endif + #if (RETARGET_PORT == RETARGET_ITM) + if (DEMCR & TRCENA) + { + while (ITM_PORT32(0) == 0); + ITM_PORT8(0) = ch; + } + return (ch); + #else + #ifdef AUTO_RETURN + if (ch == '\n') + { + SERIAL_PutChar('\r'); + } + #endif + return (SERIAL_PutChar(ch)); + #endif +} + +#if defined (__ICCARM__) +#if (__VER__ > 9010000) +/* + IAR's version after 9.20 use write to implement printf +*/ +int __write(int Handle, + const unsigned char * Buf, + int Bufsize) +{ + size_t nChars = 0; + if (Handle == -1) + { + return 0; + } + /* Check for stdout and stderr + (only necessary if FILE descriptors are enabled.) */ + if (Handle != 1 && Handle != 2) + { + return -1; + } + for (/*Empty */; Bufsize > 0; --Bufsize) + { + SERIAL_PutChar(*Buf++); + ++nChars; + } + return nChars; +} +#endif +int __read(int Handle, unsigned char *Buf, size_t BufSize) +{ + #if (RETARGET_PORT != RETARGET_ITM) + int nChars = 0; + + if (Handle != 0) + { + return -1; + } + + for (/* Empty */; BufSize > 0; --BufSize) + { + unsigned char c = NULL; + c = SERIAL_GetChar(); + if (c == 0) + break; + *Buf++ = c; + ++nChars; + } + #endif + return nChars; +} + +#elif defined(__SES_ARM) +#if defined(__SEGGER_RTL_VERSION) +/* + SES's version after 6.20 use RTL to implement printf. +*/ +/*********************************************************************************************************//** + * @brief Get character from standard input.. + * @retval Character received. + ************************************************************************************************************/ +static char _stdin_getc(void) { + unsigned char c; + + if (_stdin_ungot != EOF) { + c = _stdin_ungot; + _stdin_ungot = EOF; + } else { + c = SERIAL_GetChar(); + } + return c; +} + +/*********************************************************************************************************//** + * @brief Get file status. + * @param Pointer to file. + * @retval -1: Failure, stream is not a valid file. 0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_stat(FILE *stream) { + if (stream == stdin || stream == stdout || stream == stderr) { + return 0; // NOTE: stdin, stdout, and stderr are assumed to be valid. + } else { + return EOF; + } +} + +/*********************************************************************************************************//** + * @brief Get stream buffer size. + * @param stream: Pointer to file. + * @retval Nonzero number of characters to use for buffered I/O; for unbuffered I/O, return 1. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_bufsize(FILE *stream) { + (void)stream; + return 1; +} + +/*********************************************************************************************************//** + * @brief Read data from file. + * @param stream: Pointer to file to read from. + * @param s: Pointer to object that receives the input. + * @param len: Number of characters to read from file. + * @retval -1: Failure, stream is not a valid file. >0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_read(FILE *stream, char *s, unsigned len) { + int c; + + if (stream == stdin) { + c = 0; + while (len > 0) { + *s = _stdin_getc(); + ++s; + ++c; + --len; + } + } else { + c = EOF; + } + return c; +} + +/*********************************************************************************************************//** + * @brief Write data to file. + * @param stream: Pointer to file to write to. + * @param s:Pointer to object to write to file. + * @param len:Number of characters to write to the file. + * @retval -1: Failure, stream is not a valid file. >0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_write(FILE *stream, const char *s, unsigned len) { + if ((stream == stdout) || (stream == stderr)) { + //BSP_UART_WriteBlocking(_UART_Port, (const unsigned char*) s, len); + for (/*Empty */; len > 0; --len) + { + SERIAL_PutChar(*s++); + } + return len; + } else { + return EOF; + } +} + +/*********************************************************************************************************//** + * @brief ush character back to stream. + * @param stream: Pointer to file to push back to. + * @param c: Character to push back. + * @retval -1: Failure, stream is not a valid file. >0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_unget(FILE *stream, int c) { + if (stream == stdin) { + if (c != EOF && _stdin_ungot == EOF) { + _stdin_ungot = c; + } else { + c = EOF; + } + } else { + c = EOF; + } + return c; +} +#endif +#else +int fgetc (FILE *f) +{ + #if 0 + if (f == 0) // Remove the compiler warning + { + } + #endif + #if (RETARGET_PORT == RETARGET_ITM) + /* For Keil MDK-ARM only */ + while (ITM_CheckChar() == 0); + return (ITM_ReceiveChar()); + #else + return (SERIAL_GetChar()); + #endif +} +#endif + +void _ttywrch(int ch) +{ + #if (RETARGET_PORT == RETARGET_ITM) + if (DEMCR & TRCENA) + { + while (ITM_PORT32(0) == 0); + ITM_PORT8(0) = ch; + } + #else + SERIAL_PutChar(ch); + #endif +} +#endif + +void _sys_exit(int return_code) +{ + if (return_code == 0) // Remove the compiler warning + { + } + +label: goto label; /* endless loop */ +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_retarget_desc.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_retarget_desc.c new file mode 100644 index 00000000000..2b955b173de --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_retarget_desc.c @@ -0,0 +1,272 @@ +/*********************************************************************************************************//** + * @file ht32_retarget_desc.c + * @version $Rev:: 41 $ + * @date $Date:: 2017-05-23 #$ + * @brief The The USB Descriptor of retarget. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Includes ------------------------------------------------------------------------------------------------*/ + +#define DESC_LEN_CONFN_T (u16)(DESC_LEN_CONFN) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Device descriptor setting +// USB Specification Release number (bcdUSB) +// <0x0200=> USB 2.0 +// <0x0110=> USB 1.1 +// <0x0100=> USB 1.0 +// USB Class code (assigned by the USB-IF) +// <0x00=> Use class information in the Interface Descriptors (0x00) +// <0x02=> Communications and CDC Control (CDC, 0x02) +// <0xDC=> Diagnostic Device (0xDC) +// <0xEF=> Miscellaneous (0xEF) +// <0xFF=> Vendor Specific (0xFF) +// USB Subclass code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Protocol code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Vendor ID <0x0-0xFFFF:1> +// USB Product ID <0x0-0xFFFF:1> +// USB Device Version <0x0-0xFFFF:1> +// USB String descriptor - Manufacturer +// USB String descriptor - Product +// USB String descriptor - Device serial number +// USB Number of possible configurations <0-255:1> +#define DESC_BCDUSB (0x0110) +#define DESC_BDEVCLASS (0x00) +#define DESC_BDEVSUBCLASS (0x00) +#define DESC_BDEVPROTOCOL (0x00) +#define DESC_IDVENDOR (0x04D9) +#define DESC_IDPRODUCT (0x8008) +#define DESC_BCDDEVICE (0x0100) +#define DESC_IMANUFACTURE (1) +#define DESC_IPRODUCT (1) +#define DESC_ISERIALNUM (1) +#define DESC_INUMCONFN (1) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (DESC_BDEVCLASS == 0x0 & DESC_BDEVSUBCLASS != 0x0) +#error "DESC_BDEVSUBCLASS must be reset to zero when the DESC_BDEVCLASS is equal to zero." +#endif +#define DESC_WMAXPACKETSIZE0 (_EP0LEN) +#define DESC_STR_MAN (1 * DESC_IMANUFACTURE) +#define DESC_STR_PRD (2 * DESC_IPRODUCT) +#define DESC_STR_SER (3 * DESC_ISERIALNUM) +#define DESC_NUM_STRING (1 + 3) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_DeviceDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Device descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_DEV, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_01_DEV, // bDescriptorType 1 DEVICE Descriptor Type + DESC_H2B(DESC_BCDUSB), // bcdUSB 2 USB Specification Release Number + DESC_BDEVCLASS, // bDeviceClass 1 Class code (assigned by the USB-IF) + DESC_BDEVSUBCLASS, // bDeviceSubClass 1 Subclass code (assigned by the USB-IF) + DESC_BDEVPROTOCOL, // bDeviceProtocol 1 Protocol code (assigned by the USB-IF) + DESC_WMAXPACKETSIZE0, // wMaxPacketSize0 1 Maximum packet size for endpoint zero + DESC_H2B(DESC_IDVENDOR), // idVendor 2 Vendor ID (assigned by USB-IF) + DESC_H2B(DESC_IDPRODUCT), // idProduct 2 Product ID (assigned by manufacturer) + DESC_H2B(DESC_BCDDEVICE), // bcdDevice 2 Device release number + DESC_STR_MAN, // iManufacturer 1 Index of string descriptor (Manufacturer) + DESC_STR_PRD, // iProduct 1 Index of string descriptor (Product) + DESC_STR_SER, // iSerialNumber 1 Index of string descriptor (Serial Number) + DESC_INUMCONFN, // iNumConfigurations 1 Number of possible configuration +}; + + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Configuration descriptor setting +// Self-powered +// Bit 6 of bmAttributes +// Remote Wakeup +// Bit 5 of bmAttributes +// USB Device maximum power (mA) < 2-512:2> +#define DESC_BMATTR_SELF_POWER (0) +#define DESC_BMATTR_REMOTE_WAKEUP (0) +#define DESC_BMAXPOWER (100) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#define DESC_BMATTRIBUTES (0x80 | (DESC_BMATTR_SELF_POWER << 6) | (DESC_BMATTR_REMOTE_WAKEUP << 5)) +#define DESC_TOTAL_LEN DESC_H2B((DESC_LEN_CONFN_T + RETARGET_DLEN)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_ConfnDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Configuration descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_CONFN, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_02_CONFN, // bDescriptorType 1 CONFIGURATION Descriptor Type + DESC_TOTAL_LEN, // wTotalLength 2 Total length of data returned for this configuration + RETARGET_INF, // bNumberInterface 1 Number of interfaces supported by this configuration + 0x01, // bConfigurationValue 1 Value to use as an argument to the SetConfiguration() + 0x00, // iConfiguration 1 Index of string descriptor describing this configuration + DESC_BMATTRIBUTES, // bmAttributes 1 Configuration characteristics + // D6: Self-powered, D5: RemoteWakeup + DESC_POWER(DESC_BMAXPOWER), // bMaxPower 1 Maximum power consumption of the USB device (2 mA units) + + #ifdef RETARGET_IS_USB + #include "ht32_retarget_desc.h" + #endif + +}; + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB String Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_StringDescLANGID[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* LANGID (Index = 0) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(1), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_H2B(0x0409), // wLANGID[0] 2 LANGID code zero +}; + +#if (DESC_IMANUFACTURE == 1) +__ALIGN4 static uc8 guUSB_StringDescManufacture[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Manufacture (Index = 1) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(6), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('H'), // bString N UNICODE encoded string + DESC_CHAR('O'), + DESC_CHAR('L'), + DESC_CHAR('T'), + DESC_CHAR('E'), + DESC_CHAR('K'), +}; +#endif + +#if (DESC_IPRODUCT == 1) +__ALIGN4 static uc8 guUSB_StringDescProduct[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Product (Index = 2) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(7), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('U'), // bString N UNICODE encoded string + DESC_CHAR('S'), + DESC_CHAR('B'), + DESC_CHAR('-'), + DESC_CHAR('V'), + DESC_CHAR('C'), + DESC_CHAR('P'), +}; +#endif + + +#if (DESC_ISERIALNUM == 1) +__ALIGN4 static uc8 guUSB_StringDescSerialNum[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Serial Number (Index = 3) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(12), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('S'), // bString N UNICODE encoded string + DESC_CHAR('N'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('1'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), +}; +#endif + +uc8 *gpStringDesc[DESC_NUM_STRING] = +{ + + guUSB_StringDescLANGID, + + #if (DESC_IMANUFACTURE == 1) + guUSB_StringDescManufacture, + #else + NULL, + #endif + + #if (DESC_IPRODUCT == 1) + guUSB_StringDescProduct, + #else + NULL, + #endif + + #if (DESC_ISERIALNUM == 1) + guUSB_StringDescSerialNum + #else + NULL, + #endif + +}; + +/*********************************************************************************************************//** + * @brief USB Descriptor pointer initialization. + * @param pDesc: pointer of USBDCore_Desc_TypeDef + * @retval None + ***********************************************************************************************************/ +void USBDDesc_Init(USBDCore_Desc_TypeDef *pDesc) +{ + pDesc->pDeviceDesc = guUSB_DeviceDesc; + pDesc->pConfnDesc = guUSB_ConfnDesc; + pDesc->ppStringDesc = gpStringDesc; + pDesc->uStringDescNumber = DESC_NUM_STRING; + + return; +} diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_serial.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_serial.c new file mode 100644 index 00000000000..7eded142f3b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_serial.c @@ -0,0 +1,549 @@ +/*********************************************************************************************************//** + * @file ht32_serial.c + * @version $Rev:: 2794 $ + * @date $Date:: 2022-11-25 #$ + * @brief This file provides all the Low level serial routines for HT32. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_board.h" + +#if (_RETARGET == 1) + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup SERIAL SERIAL + * @brief Serial related functions + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Exported_Functions Serial exported functions + * @{ + */ + +#ifdef RETARGET_IS_UART + +#if (RETARGET_INT_MODE == 1) +__ALIGN4 static u8 uSerialBuffer[RETARGET_INT_BUFFER_SIZE]; +static vu32 uReadIndex; +static vu32 uWriteIndex; + +#define IS_BUFFER_FULL(LEN) (((uWriteIndex + LEN) >= RETARGET_INT_BUFFER_SIZE) ? ((uWriteIndex + LEN - RETARGET_INT_BUFFER_SIZE) == uReadIndex) : ((uWriteIndex + LEN) == uReadIndex)) +#define IS_BUFFER_EMPTY() (uReadIndex == uWriteIndex) +#define BUFFER_FREE_LEN() ((uWriteIndex >= uReadIndex) ? (RETARGET_INT_BUFFER_SIZE - uWriteIndex + uReadIndex - 1) : (uReadIndex - uWriteIndex - 1)) + +/*********************************************************************************************************//** + * @brief UART IRQ handler. + * @retval None + ************************************************************************************************************/ +void RETARGET_UART_IRQHandler(void) +{ + if (((RETARGET_USART_PORT->SR) & USART_FLAG_TXDE)) + { + if (IS_BUFFER_EMPTY()) + { + RETARGET_USART_PORT->IER &= ~USART_INT_TXDE; + } + else + { + RETARGET_USART_PORT->DR = uSerialBuffer[uReadIndex++]; + if (uReadIndex == RETARGET_INT_BUFFER_SIZE) + { + uReadIndex = 0; + } + } + } + +} +#endif + +/*********************************************************************************************************//** + * @brief Put char to USART. + * @param ch: The char put to USART. + * @retval The char put to USART. + ************************************************************************************************************/ +u32 SERIAL_PutChar(u32 ch) +{ +#if (RETARGET_INT_MODE == 1) + + while (IS_BUFFER_FULL(1)); + + uSerialBuffer[uWriteIndex++] = ch; + if (uWriteIndex == RETARGET_INT_BUFFER_SIZE) + { + uWriteIndex = 0; + } + RETARGET_USART_PORT->IER |= USART_INT_TXDE; + +#else + + USART_SendData(RETARGET_USART_PORT, (u8)ch); + while (USART_GetFlagStatus(RETARGET_USART_PORT, USART_FLAG_TXC) == RESET) + { + } + +#endif + + return ch; +} + +/*********************************************************************************************************//** + * @brief Get char from USART. + * @retval The char got from USART. + ************************************************************************************************************/ +u32 SERIAL_GetChar(void) +{ + #if (LIBCFG_USART_V01) + while (USART_GetFlagStatus(RETARGET_USART_PORT, USART_FLAG_RXDNE) == RESET) + { + } + #else + while (USART_GetFlagStatus(RETARGET_USART_PORT, USART_FLAG_RXDR) == RESET) + { + } + #endif + return USART_ReceiveData(RETARGET_USART_PORT); +} +#endif + + +#ifdef RETARGET_IS_USB +/* Private types -------------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_TypesDefinitions Serial private types definitions + * @{ + */ +typedef struct _VCP_LINE_CODING +{ + u32 dwDTERate; //Bit rate; + u8 bCharFormat; //Stop bits: + //0 = 1 Stop bit + //1 = 1.5 Stop bit + //2 = 2 Stop bit + u8 bParityType; //parity: + //0 = None + //1 = Odd + //2 = Even + //3 = Mark + //4 = Space + u8 bDataBits; //Number of data bits (7, 8, 9) +} USBDClass_VCP_LINE_CODING; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_Define Serial private definitions + * @{ + */ +#define CLASS_REQ_20_SET_LINE_CODING (0x20) +#define CLASS_REQ_21_GET_LINE_CODING (0x21) +#define CLASS_REQ_22_SET_CONTROL_LINE_STATE (0x22) + +#ifndef RETARGET_TXBUFFER_SIZE + #define RETARGET_TXBUFFER_SIZE (1) +#endif + +#define RETARGET_USB_MODE_BLOCK (0) +#define RETARGET_USB_MODE_NONBLOCK (1) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_Macro Serial private macros + * @{ + */ +#define IS_BUFFER_FULL(LEN) (((uWriteIndex + LEN) >= RETARGET_BUFFER_SIZE) ? ((uWriteIndex + LEN - RETARGET_BUFFER_SIZE) == uReadIndex) : ((uWriteIndex + LEN) == uReadIndex)) +#define IS_BUFFER_EMPTY() (uReadIndex == uWriteIndex) +#define BUFFER_FREE_LEN() ((uWriteIndex >= uReadIndex) ? (RETARGET_BUFFER_SIZE - uWriteIndex + uReadIndex - 1) : (uReadIndex - uWriteIndex - 1)) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_Variable Serial private variables + * @{ + */ +static USBDClass_VCP_LINE_CODING USBDClassVCPLineCoding; +__ALIGN4 static u8 uSerialBuffer[RETARGET_BUFFER_SIZE]; +static vu32 uReadIndex; +static vu32 uWriteIndex; +static vu32 uDTRState = 0; +static vu32 gIsINEmpty = TRUE; + +static u32 TxCount = 0; +__ALIGN4 static u8 TxBuffer[RETARGET_TXBUFFER_SIZE]; +/** + * @} + */ + +#if (RETARGET_RX_EPT == RETARGET_TX_EPT) + #error USB Endpoint of retarget Rx and Tx must different. Please check RETARGET_RX_EPT/RETARGET_TX_EPT "ht32_retarget_usbdconf.h". +#endif + +#if (RETARGET_CTRL_EPT == RETARGET_TX_EPT) + #error USB Endpoint of retarget Control and Tx must different. Please check RETARGET_CTRL_EPT/RETARGET_TX_EPT "ht32_retarget_usbdconf.h". +#endif + +#if (RETARGET_CTRL_EPT == RETARGET_RX_EPT) + #error USB Endpoint of retarget Control and Rx must different. Please check RETARGET_CTRL_EPT/RETARGET_RX_EPT "ht32_retarget_usbdconf.h". +#endif + +#ifdef _RERATGET1_ERR + #error Endpoint 1 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET2_ERR + #error Endpoint 2 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET3_ERR + #error Endpoint 3 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET4_ERR + #error Endpoint 4 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET5_ERR + #error Endpoint 5 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET6_ERR + #error Endpoint 6 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET7_ERR + #error Endpoint 7 already used by other USB class. Retarget can not overwrite it. +#endif + +/*********************************************************************************************************//** + * @brief Put char to USB. + * @param ch: The char put to USB. + * @retval The char put to USB. + ************************************************************************************************************/ +u32 SERIAL_PutChar(u32 ch) +{ + #if (RETARGET_TXBUFFER_SIZE > 63) + #error RETARGET_TXBUFFER_SIZE shall less than 63 (define in ht32fxxxxx_conf.h). + #endif + + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_BLOCK) + while (uDTRState == 0); /* Wait until user open the virtual COM port by PC UI such as Hyper Terminal */ + #elif (RETARGET_USB_MODE == RETARGET_USB_MODE_NONBLOCK) + if (uDTRState == 0) /* Drop data if USB or terminal software is not ready */ + { + return ch; + } + #endif + + TxBuffer[TxCount++] = ch; + + if (TxCount == RETARGET_TXBUFFER_SIZE) + { + TxCount = 0; + + while (gIsINEmpty == FALSE) + { + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_NONBLOCK) + if (uDTRState == 0) + { + return ch; + } + #endif + } + + gIsINEmpty = FALSE; + USBDCore_EPTWriteINData((USBD_EPTn_Enum)RETARGET_TX_EPT, (u32 *)&TxBuffer, RETARGET_TXBUFFER_SIZE); + } + + return ch; +} + +/*********************************************************************************************************//** + * @brief Get char from USB. + * @retval The char got from USB. + ************************************************************************************************************/ +u32 SERIAL_GetChar(void) +{ + u32 value = 0; + + while (IS_BUFFER_EMPTY()); + value = uSerialBuffer[uReadIndex++]; + if (uReadIndex == RETARGET_BUFFER_SIZE) + { + uReadIndex = 0; + } + + return value; +} + +/*********************************************************************************************************//** + * @brief Flush the Tx Buffer + * @retval None + ************************************************************************************************************/ +void SERIAL_Flush(void) +{ + do + { + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_NONBLOCK) + if (uDTRState == 0) + { + return; + } + #endif + } while (USBDCore_EPTGetTransferCount((USBD_EPTn_Enum)RETARGET_TX_EPT, USBD_TCR_0)); + + gIsINEmpty = FALSE; + USBDCore_EPTWriteINData((USBD_EPTn_Enum)RETARGET_TX_EPT, (u32 *)&TxBuffer, TxCount); + TxCount = 0; +} + +#ifdef NON_USB_IN_APP +#include "ht32_retarget_desc.c" +__ALIGN4 USBDCore_TypeDef gUSBCore; +USBD_Driver_TypeDef gUSBDriver; + +/*********************************************************************************************************//** + * @brief This function handles USB interrupt. + * @retval None + ************************************************************************************************************/ +void USB_IRQHandler(void) +{ + USBDCore_IRQHandler(&gUSBCore); +} + +/*********************************************************************************************************//** + * @brief USB Class initialization. + * @param pClass: pointer of USBDCore_Class_TypeDef + * @retval None + ************************************************************************************************************/ +void USBDClass_Init(USBDCore_Class_TypeDef *pClass) +{ + pClass->CallBack_ClassRequest = SERIAL_USBDClass_Request; + pClass->CallBack_EPTn[RETARGET_RX_EPT] = SERIAL_USBDClass_RXHandler; + pClass->CallBack_EPTn[RETARGET_TX_EPT] = SERIAL_USBDClass_TXHandler; + return; +} + +#if (LIBCFG_CKCU_USB_PLL) +/*********************************************************************************************************//** + * @brief Configure USB PLL + * @retval None + ************************************************************************************************************/ +void USBPLL_Configuration(void) +{ + if ((HT_CKCU->GCCR & (1 << 11)) == 0) + { + CKCU_HSICmd(ENABLE); + } + + { /* USB PLL configuration */ + + /* !!! NOTICE !!! + Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below in this function. + */ + CKCU_PLLInitTypeDef PLLInit; + + PLLInit.ClockSource = CKCU_PLLSRC_HSI; + #if (LIBCFG_CKCU_USB_PLL_96M) + PLLInit.CFG = CKCU_USBPLL_8M_96M; + #else + PLLInit.CFG = CKCU_USBPLL_8M_48M; + #endif + PLLInit.BYPASSCmd = DISABLE; + CKCU_USBPLLInit(&PLLInit); + } + + CKCU_USBPLLCmd(ENABLE); + + while (CKCU_GetClockReadyStatus(CKCU_FLAG_USBPLLRDY) == RESET); + CKCU_USBClockConfig(CKCU_CKUSBPLL); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure USB for retarget. + * @retval None + ************************************************************************************************************/ +void SERIAL_USBDInit(void) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + CKCUClock.Bit.USBD = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + #if (LIBCFG_CKCU_USB_PLL) + USBPLL_Configuration(); + #else + { + u32 uPLL; + uPLL = CKCU_GetPLLFrequency(); + // uPLL=48000000, CKCU_USBPRE_DIV1 + // uPLL=96000000, CKCU_USBPRE_DIV2 + // uPLL=144000000, CKCU_USBPRE_DIV3 + CKCU_SetUSBPrescaler((CKCU_USBPRE_TypeDef)((uPLL / 48000000) - 1)); + #endif + +#if (LIBCFG_CKCU_HSI_NO_AUTOTRIM) +#else + /* !!! NOTICE !!! + Must turn on if the USB clock source is from HSI (PLL clock Source) + */ + #if (RETARGET_HSI_ATM) + CKCU_HSIAutoTrimClkConfig(CKCU_ATC_USB); + CKCU_HSIAutoTrimCmd(ENABLE); + #endif +#endif + + gUSBCore.pDriver = (u32 *)&gUSBDriver; /* Initiate memory pointer of USB driver */ + USBDDesc_Init(&gUSBCore.Device.Desc); /* Initiate memory pointer of descriptor */ + USBDClass_Init(&gUSBCore.Class); /* Initiate USB Class layer */ + USBDCore_Init(&gUSBCore); /* Initiate USB Core layer */ + NVIC_EnableIRQ(USB_IRQn); /* Enable USB device interrupt */ + USBD_DPpullupCmd(ENABLE); + + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_BLOCK) + USBDCore_MainRoutine(&gUSBCore); /* USB core main routine */ + while (USBDCore_GetStatus() != USB_STATE_CONFIGURED); + #else + gUSBCore.Info.CurrentFeature.Bits.bSelfPowered = TRUE; + USBDCore_MainRoutine(&gUSBCore); /* USB core main routine */ + #endif +} +#endif + +/*********************************************************************************************************//** + * @brief USB Device Class Request for USB retarget + * @param pDev: pointer of USB Device + * @retval None + ************************************************************************************************************/ +void SERIAL_USBDClass_Request(USBDCore_Device_TypeDef *pDev) +{ + u8 USBCmd = *((u8 *)(&(pDev->Request.bRequest))); + u16 len = *((u16 *)(&(pDev->Request.wLength))); + u32 inf = pDev->Request.wIndex; + u32 uIsCmdOK = 0; + + if (inf != 11) + { + return; + } + + if (USBCmd == CLASS_REQ_22_SET_CONTROL_LINE_STATE) + { + if (len == 0) + { + uDTRState = pDev->Request.wValueL & 0x1; + pDev->Transfer.pData = 0; + pDev->Transfer.sByteLength = 0; + pDev->Transfer.Action = USB_ACTION_DATAOUT; + } + } + else + { + if (USBCmd == CLASS_REQ_20_SET_LINE_CODING) + { + pDev->Transfer.Action = USB_ACTION_DATAOUT; + uIsCmdOK = 1; + } + else if (USBCmd == CLASS_REQ_21_GET_LINE_CODING) + { + pDev->Transfer.Action = USB_ACTION_DATAIN; + uIsCmdOK = 1; + } + + if (uIsCmdOK == 1) + { + pDev->Transfer.pData = (uc8*)&USBDClassVCPLineCoding; + pDev->Transfer.sByteLength = (sizeof(USBDClassVCPLineCoding) > pDev->Request.wLength) ? (pDev->Request.wLength) : (sizeof(USBDClassVCPLineCoding)); + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Received handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None +************************************************************************************************************/ +void SERIAL_USBDClass_RXHandler(USBD_EPTn_Enum EPTn) +{ + u32 uLen; + u32 uFreeLen = BUFFER_FREE_LEN(); + u8 uTempBuffer[64]; + u32 i; + + /* Read Receive data */ + uLen = USBDCore_EPTReadOUTData(EPTn, (u32*)uTempBuffer, 64); + + if (uLen > uFreeLen) + { + uLen = uFreeLen; + } + + for (i = 0; i < uLen; i++) + { + uSerialBuffer[uWriteIndex++] = uTempBuffer[i]; + if (uWriteIndex == RETARGET_BUFFER_SIZE) + { + uWriteIndex = 0; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Tx handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None +************************************************************************************************************/ +void SERIAL_USBDClass_TXHandler(USBD_EPTn_Enum EPTn) +{ + gIsINEmpty = TRUE; + return; +} + +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_time.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_time.c new file mode 100644 index 00000000000..ff501874845 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32_time.c @@ -0,0 +1,185 @@ +/*********************************************************************************************************//** + * @file ht32_time.c + * @version $Rev:: 2888 $ + * @date $Date:: 2023-03-03 #$ + * @brief The time functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_time.h" + +/* + Tick Range: 0 ~ 2^32 / HTCFG_TIME_TICKHZ (maximum tick time) + Interrupt Time: _HTCFG_TIME_OVERFLOW_VALUE / (HTCFG_TIME_TICKHZ * HTCFG_TIME_MULTIPLE) Second (not apply for BFTM) + + Example: 32-bit BFTM with 48 MHz Timer Clock + HTCFG_TIME_TICKHZ = HTCFG_TIME_CLKSRC = 48000000 + Tick Range: 0 ~ 2^32 / 48000000 = 0 ~ 89.478485 Second (maximum tick time, return to 0 every 89.478485 Second) + BFTM do not use interrupt + + Example: 16-bit SCTM with 1 us tick + HTCFG_TIME_TICKHZ = 1000000 (Hz) + HTCFG_TIME_MULTIPLE = 1 (1 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 1000000 = 0 ~ 4294 Second = 0 ~ 71.58 Minute (maximum tick time, return to 0 every 71.58 Minute) + Interrupt Time: 65536 / (1000000 * 1) = 65.536 ms (Trigger interrupt every 65.536 ms) + + Example: 16-bit SCTM with 10 us tick + HTCFG_TIME_TICKHZ = 100000 (Hz) + HTCFG_TIME_MULTIPLE = 4 (4 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 100000 = 0 ~ 42949 Second = 0 ~ 715.82 Minute = 11.93 Hour (maximum tick time, return to 0 every 11.93 Hour) + Interrupt Time: 65536 / (100000 * 4) = 163.84 ms (Trigger interrupt every 163.84 ms) + + Example: 16-bit GPTM with 1 ms tick + HTCFG_TIME_TICKHZ = 1000 (Hz) + HTCFG_TIME_MULTIPLE = 4 (4 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 1000 = 0 ~ 4294967 Second = 0 ~ 49.7 Day (maximum tick time, return to 0 every 49.7 Day) + Interrupt Time: 65536 / (1000 * 4) = 16.384 Second (Trigger interrupt every 16.384 Second) +*/ + +/* Private constants ---------------------------------------------------------------------------------------*/ +#define _HTCFG_TIME_CKCU_PCLK STRCAT2(CKCU_PCLK_, HTCFG_TIME_IPN) + +#if (IS_IPN_TM(HTCFG_TIME_IPN)) +// SCTM/PWM/GPTM/MCTM +#define _HTCFG_TIME_IRQn STRCAT2(HTCFG_TIME_IPN, _IRQn) +#define _HTCFG_TIME_IRQHandler STRCAT2(HTCFG_TIME_IPN, _IRQHandler) +#define _HTCFG_TIME_CLKDIV (HTCFG_TIME_CLKSRC / HTCFG_TIME_TICKHZ / HTCFG_TIME_MULTIPLE) +#define _HTCFG_TIME_OVERFLOW_VALUE (65536) // 16-bit = 2^16 + +#if (_HTCFG_TIME_CLKDIV <= 0) + #error "_HTCFG_TIME_CLKDIV is not correct (must >= 1)!" +#endif + +#if (_HTCFG_TIME_CLKDIV > 65536) + #error "_HTCFG_TIME_CLKDIV is not correct (must <= 65536)!" +#endif + +#if ((_HTCFG_TIME_CLKDIV * HTCFG_TIME_MULTIPLE) != (HTCFG_TIME_CLKSRC / HTCFG_TIME_TICKHZ)) + #error "_HTCFG_TIME_CLKDIV is not correct (must be integer)!" +#endif +#endif + +/* Private variables ---------------------------------------------------------------------------------------*/ +#if (IS_IPN_TM(HTCFG_TIME_IPN)) +u32 gTotalTick = 0x00000000; +u8 gIsTimeInt = FALSE; +#endif + +/* Global functions ----------------------------------------------------------------------------------------*/ +/*********************************************************************************************************//** + * @brief Time Init function. + * @retval None + ***********************************************************************************************************/ +void Time_Init(void) +{ + { /* Enable peripheral clock */ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.HTCFG_TIME_IPN = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + } + + #if (LIBCFG_CKCU_NO_APB_PRESCALER == 0) + CKCU_SetPeripPrescaler(_HTCFG_TIME_CKCU_PCLK, (CKCU_APBCLKPRE_TypeDef)HTCFG_TIME_PCLK_DIV); + #endif + + #if (IS_IPN_TM(HTCFG_TIME_IPN)) + + { /* Time base configuration */ + /* !!! NOTICE !!! + Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below in this function. + */ + TM_TimeBaseInitTypeDef TimeBaseInit; + + TimeBaseInit.Prescaler = _HTCFG_TIME_CLKDIV - 1; + TimeBaseInit.CounterReload = _HTCFG_TIME_OVERFLOW_VALUE -1; + TimeBaseInit.RepetitionCounter = 0; + TimeBaseInit.CounterMode = TM_CNT_MODE_UP; + TimeBaseInit.PSCReloadTime = TM_PSC_RLD_IMMEDIATE; + TM_TimeBaseInit(_HTCFG_TIME_PORT, &TimeBaseInit); + + /* Clear Update Event Interrupt flag since the "TM_TimeBaseInit()" writes the UEV1G bit */ + TM_ClearFlag(_HTCFG_TIME_PORT, TM_FLAG_UEV); + } + + /* Enable Update Event interrupt */ + TM_IntConfig(_HTCFG_TIME_PORT, TM_INT_UEV, ENABLE); + NVIC_EnableIRQ(_HTCFG_TIME_IRQn); + + TM_SetCounter(_HTCFG_TIME_PORT, 0x0000); + TM_Cmd(_HTCFG_TIME_PORT, ENABLE); + + #else + + BFTM_SetCounter(_HTCFG_TIME_PORT, 0x00000000); + BFTM_EnaCmd(_HTCFG_TIME_PORT, ENABLE); + #endif +} + +/*********************************************************************************************************//** + * @brief Time delay function. + * @param uDelayTick: Delay count based on tick. + * @retval None + ***********************************************************************************************************/ +void Time_Delay(u32 uDelayTick) +{ + u32 uCurrent; + u32 uStart = Time_GetTick(); + + do + { + uCurrent = Time_GetTick(); + } while (TIME_TICKDIFF(uStart, uCurrent) < uDelayTick); +} + +#if (IS_IPN_TM(HTCFG_TIME_IPN)) +/*********************************************************************************************************//** + * @brief Gets the current time tick. + * @retval Time Tick + ***********************************************************************************************************/ +u32 Time_GetTick(void) +{ + u32 uCount = GET_CNT(); + + if (gIsTimeInt == TRUE) + { + gIsTimeInt = FALSE; + uCount = GET_CNT(); + gTotalTick += (_HTCFG_TIME_OVERFLOW_VALUE / HTCFG_TIME_MULTIPLE); + } + + return (gTotalTick + (uCount / HTCFG_TIME_MULTIPLE)); +} + +/*********************************************************************************************************//** + * @brief This function handles Timer interrupt. + * @retval None + ************************************************************************************************************/ +void _HTCFG_TIME_IRQHandler(void) +{ + TM_ClearFlag(_HTCFG_TIME_PORT, TM_INT_UEV); + + gIsTimeInt = TRUE; +} +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_adc.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_adc.c new file mode 100644 index 00000000000..501d3947563 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_adc.c @@ -0,0 +1,724 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_adc.c + * @version $Rev:: 2972 $ + * @date $Date:: 2023-10-28 #$ + * @brief This file provides all the ADC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_adc.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Private_Define ADC private definitions + * @{ + */ +#define ADC_ENABLE_BIT (0x00000080) +#define ADC_SOFTWARE_RESET (0x00000001) +#define LST_SEQ_SET (0x0000001F) +#define TCR_SC_SET (0x00000001) + +#define HLST_SEQ_SET (0x0000001F) +#define HTCR_SC_SET (0x00000001) + +#define OFR_ADOF_MASK (0x00000FFF) +#define OFR_ADAL (1 << 14) +#define OFR_ADOFE (1 << 15) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions ADC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the HT_ADCn peripheral registers to their default reset values. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + if (HT_ADCn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.ADC0 = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Reset ADC. + * @param HT_ADCn: is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_Reset(HT_ADC_TypeDef* HT_ADCn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + HT_ADCn->RST |= ADC_SOFTWARE_RESET; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + #if (LIBCFG_ADC_NOENBIT) + #else + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->CONV |= ADC_ENABLE_BIT; + ADC_Reset(HT_ADCn); + } + else + { + HT_ADCn->CONV &= ~(ADC_ENABLE_BIT); + } + #endif +} + +/*********************************************************************************************************//** + * @brief Configure conversion mode and length of list queue for regular group. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_MODE: ADC Cyclic Conversion Mode. + * This parameter can be one of the following values: + * @arg ONE_SHOT_MODE : + * @arg CONTINUOUS_MODE : + * @arg DISCONTINUOUS_MODE : + * @param Length: must between 1 ~ 16 + * @param SubLength: must between 1 ~ 16, only valid for DISCONTINUOUS_MODE. + * @retval None + ************************************************************************************************************/ +void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CONVERSION_MODE(ADC_MODE)); + Assert_Param(IS_ADC_REGULAR_LENGTH(Length)); + if (ADC_MODE == DISCONTINUOUS_MODE) + { + Assert_Param(IS_ADC_REGULAR_SUB_LENGTH(SubLength)); + } + + /* Config cyclic conversion mode and length of list queue and sub length for regular group */ + #if (LIBCFG_ADC_NOENBIT) + HT_ADCn->CONV = ((u32)(SubLength - 1) << 16) | ((u32)(Length - 1) << 8) | ADC_MODE; + #else + HT_ADCn->CONV = ((u32)(SubLength - 1) << 16) | ((u32)(Length - 1) << 8) | ADC_MODE | (HT_ADCn->CONV & ADC_ENABLE_BIT); + #endif +} + +/*********************************************************************************************************//** + * @brief Configure conversion mode and length of list queue for high priority group. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_MODE: ADC Cyclic Conversion Mode. + * This parameter can be one of the following values: + * @arg ONE_SHOT_MODE : + * @arg CONTINUOUS_MODE : + * @arg DISCONTINUOUS_MODE : + * @param Length: must between 1 ~ 4 + * @param SubLength: must between 1 ~ 4 + * @retval None + ************************************************************************************************************/ +void ADC_HPGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CONVERSION_MODE(ADC_MODE)); + Assert_Param(IS_ADC_HP_LENGTH(Length)); + Assert_Param(IS_ADC_HP_SUB_LENGTH(SubLength)); + + /* Config cyclic conversion mode and length of list queue and sub length for regular group */ + HT_ADCn->HCONV = ((u32)(SubLength - 1) << 16) | ((u32)(Length - 1) << 8) | ADC_MODE; +} + +/*********************************************************************************************************//** + * @brief Configure the corresponding rank in the sequencer and the sampling time for the regular channel + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected, x must between 0 ~ 11 + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param Rank: The rank in the regular group sequencer. + * This parameter must be between 0 to 15. + * @param SampleClock: Number of sampling clocks. + * This parameter must be between 0x00 to 0xFF. + * @retval None + ************************************************************************************************************/ +void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock) +{ + u32 tmpreg1, tmpreg2; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_REGULAR_RANK(Rank)); + Assert_Param(IS_ADC_INPUT_SAMPLING_TIME(SampleClock)); + + /* config sampling clock of correspond ADC input channel */ + HT_ADCn->STR[ADC_CH_n] = SampleClock; + + /* Get the old register value */ + tmpreg1 = HT_ADCn->LST[Rank >> 2]; + /* Calculate the mask to clear */ + tmpreg2 = LST_SEQ_SET << (8 * (Rank & 0x3)); + /* Clear the old SEQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_CH_n << (8 * (Rank & 0x3)); + /* Set the SEQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + HT_ADCn->LST[Rank >> 2] = tmpreg1; +} + +/*********************************************************************************************************//** + * @brief Configure the corresponding rank in the sequencer and the sample time for the High Priority channel + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected, x must between 0 ~ 11 + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param Rank: The rank in the high priority group sequencer. + * This parameter must be between 0 to 3. + * @param SampleClock: Number of sampling clocks. + * This parameter must be between 0x00 to 0xFF. + * @retval None + ************************************************************************************************************/ +void ADC_HPChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock) +{ + u32 tmpreg1, tmpreg2; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_HP_RANK(Rank)); + Assert_Param(IS_ADC_INPUT_SAMPLING_TIME(SampleClock)); + + /* config sampling clock of correspond ADC input channel */ + HT_ADCn->STR[ADC_CH_n] = SampleClock; + + /* Get the old register value */ + tmpreg1 = HT_ADCn->HLST; + /* Calculate the mask to clear */ + tmpreg2 = HLST_SEQ_SET << (8 * (Rank & 0x3)); + /* Clear the old SEQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_CH_n << (8 * (Rank & 0x3)); + /* Set the SEQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + HT_ADCn->HLST = tmpreg1; +} + +/*********************************************************************************************************//** + * @brief Configure the ADC trigger source for regular channels conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_TRIG_x: + * This parameter can be one of the following values: + * @arg ADC_TRIG_SOFTWARE : S/W trigger + * @arg ADC_TRIG_EXTI_n : where n can be 0 ~ 15 + * @arg ADC_TRIG_MCTMn_MTO : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_GPTMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_TRIG_BFTMn : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_TRIG_CMPn : where n can be 0 ~ 1 + * @retval None + ************************************************************************************************************/ +void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_TRIG(ADC_TRIG_x)); + + /* Config external trigger conversion source of regular group */ + HT_ADCn->TCR = ADC_TRIG_x & 0x0000001F; + HT_ADCn->TSR = ADC_TRIG_x & (~0x0000001F); +} + +/*********************************************************************************************************//** + * @brief Configure the ADC trigger source for high priority channels conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_TRIG_x: + * This parameter can be one of the following values: + * @arg ADC_TRIG_EXTI_n : where n can be 0 ~ 15 + * @arg ADC_TRIG_MCTMn_MTO : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_GPTMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_TRIG_BFTMn : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_HPTRIG_CMPn : where n can be 0 ~ 1 + * @retval None + ************************************************************************************************************/ +void ADC_HPTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_HPTRIG(ADC_TRIG_x)); + + HT_ADCn->HTCR = ADC_TRIG_x & 0x0000001F; + HT_ADCn->HTSR = ADC_TRIG_x & (~0x0000001F); +} + +/*********************************************************************************************************//** + * @brief Configure the channel data alignment format. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected + * @arg ADC_CH_OPAn : ADC channel for OPAn + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param ADC_ALIGN_x: ADC_ALIGN_RIGHT or ADC_ALIGN_LEFT + * @retval None + ************************************************************************************************************/ +void ADC_ChannelDataAlign(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ADC_ALIGN_Enum ADC_ALIGN_x) +{ + u32 OFRValue; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_ALIGN(ADC_ALIGN_x)); + + OFRValue = HT_ADCn->OFR[ADC_CH_n] & (~(OFR_ADAL)); + OFRValue |= ADC_ALIGN_x; + + HT_ADCn->OFR[ADC_CH_n] = OFRValue; +} + +/*********************************************************************************************************//** + * @brief Configure the offset value for channel offset cancellation. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected + * @arg ADC_CH_OPAn : ADC channel for OPAn + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param OffsetValue: The offset value + * @retval None + ************************************************************************************************************/ +void ADC_ChannelOffsetValue(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u16 OffsetValue) +{ + u32 OFRValue; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_OFFSET(OffsetValue)); + + OFRValue = HT_ADCn->OFR[ADC_CH_n] & (~OFR_ADOF_MASK); + OFRValue |= (OffsetValue & 0xFFF); + HT_ADCn->OFR[ADC_CH_n] = OFRValue; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the channel offset cancellation function. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected + * @arg ADC_CH_OPAn : ADC channel for OPAn + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param NewState: ENABLE DISABLE + * @retval None + ************************************************************************************************************/ +void ADC_ChannelOffsetCmd(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ControlStatus NewState) +{ + u32 OFRValue; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + OFRValue = HT_ADCn->OFR[ADC_CH_n] & (~(OFR_ADOFE)); + + if (NewState == ENABLE) + { + OFRValue |= OFR_ADOFE; + } + + HT_ADCn->OFR[ADC_CH_n] = OFRValue; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable software start of the regular channel conversion of the selected ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Start Conversion */ + if (NewState != DISABLE) + { + HT_ADCn->TSR |= TCR_SC_SET; + } + else + { + HT_ADCn->TSR &= ~TCR_SC_SET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable software start of the high priority channel conversion of the selected ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_HPSoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Start Conversion */ + if (NewState != DISABLE) + { + HT_ADCn->HTSR |= HTCR_SC_SET; + } + else + { + HT_ADCn->HTSR &= ~HTCR_SC_SET; + } +} + +/*********************************************************************************************************//** + * @brief Return the result of ADC regular channel conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_REGULAR_DATAn: where n can be 0 ~ 15 + * @retval The Value of data conversion. + ************************************************************************************************************/ +u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_REGULAR_DATA(ADC_REGULAR_DATAn)); + + return ((u16)HT_ADCn->DR[ADC_REGULAR_DATAn]); +} + +/*********************************************************************************************************//** + * @brief Return the result of ADC high priority channel conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_HP_DATAn: where x can be 0 ~ 3 + * @retval The Value of data conversion. + ************************************************************************************************************/ +u16 ADC_GetHPConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_HP_DATAn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_HP_DATA(ADC_HP_DATAn)); + + return ((u16)HT_ADCn->HDR[ADC_HP_DATAn]); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC interrupts. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the ADC interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_HP_SINGLE_EOC : + * @arg ADC_INT_HP_SUB_GROUP_EOC : + * @arg ADC_INT_HP_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_HP_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->IER |= ADC_INT_x; + } + else + { + HT_ADCn->IER &= ~ADC_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC interrupt has occurred. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_HP_SINGLE_EOC : + * @arg ADC_INT_HP_SUB_GROUP_EOC : + * @arg ADC_INT_HP_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_HP_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + if ((HT_ADCn->ISR & ADC_INT_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Clear the ADC interrupt pending bits. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt pending bits to be cleared. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_HP_SINGLE_EOC : + * @arg ADC_INT_HP_SUB_GROUP_EOC : + * @arg ADC_INT_HP_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_HP_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + HT_ADCn->ICLR = ADC_INT_x; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC flag has been set. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_FLAG_x: Specify the flag to check. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_SINGLE_EOC : + * @arg ADC_FLAG_SUB_GROUP_EOC : + * @arg ADC_FLAG_CYCLE_EOC : + * @arg ADC_FLAG_HP_SINGLE_EOC : + * @arg ADC_FLAG_HP_SUB_GROUP_EOC : + * @arg ADC_FLAG_HP_CYCLE_EOC : + * @arg ADC_FLAG_DATA_OVERWRITE : + * @arg ADC_FLAG_HP_DATA_OVERWRITE : + * @arg ADC_FLAG_AWD_LOWER : + * @arg ADC_FLAG_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_FLAG(ADC_FLAG_x)); + + if ((HT_ADCn->IRAW & ADC_FLAG_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable Lower/Upper threshold warning of the analog watchdog on single/all channels. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_AWD_x: + * This parameter can be any combination of the following values: + * @arg ADC_AWD_DISABLE : + * @arg ADC_AWD_ALL_LOWER : + * @arg ADC_AWD_ALL_UPPER : + * @arg ADC_AWD_ALL_LOWER_UPPER : + * @arg ADC_AWD_SINGLE_LOWER : + * @arg ADC_AWD_SINGLE_UPPER : + * @arg ADC_AWD_SINGLE_LOWER_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_AWD(ADC_AWD_x)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFFFF8) | ADC_AWD_x; +} + +/*********************************************************************************************************//** + * @brief Configure the analog watchdog that guards single channel. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: where n must between 0 ~ 11 + * @retval None + ************************************************************************************************************/ +void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INPUT_CHANNEL(ADC_CH_n)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFF0FF) | ((u32)ADC_CH_n << 8); +} + +/*********************************************************************************************************//** + * @brief Configure the high and low thresholds of the analog watchdog. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param UPPER: must between 0x0000 ~ 0x0FFF + * @param LOWER: must between 0x0000 ~ 0x0FFF + * @retval None + ************************************************************************************************************/ +void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_THRESHOLD(UPPER)); + Assert_Param(IS_ADC_THRESHOLD(LOWER)); + + HT_ADCn->LTR = LOWER; + HT_ADCn->UTR = UPPER; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified PDMA request. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_PDMA_x: Specify the ADC PDMA request that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_PDMA_REGULAR_SINGLE : + * @arg ADC_PDMA_REGULAR_SUBGROUP : + * @arg ADC_PDMA_REGULAR_CYCLE : + * @arg ADC_PDMA_HP_SINGLE : + * @arg ADC_PDMA_HP_SUBGROUP : + * @arg ADC_PDMA_HP_CYCLE : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_PDMA(ADC_PDMA_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->PDMAR |= ADC_PDMA_x; + } + else + { + HT_ADCn->PDMAR &= ~ADC_PDMA_x; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_adc_02.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_adc_02.c new file mode 100644 index 00000000000..8d22863d7bb --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_adc_02.c @@ -0,0 +1,559 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_adc_02.c + * @version $Rev:: 2972 $ + * @date $Date:: 2023-10-28 #$ + * @brief This file provides all the ADC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_adc.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Private_Define ADC private definitions + * @{ + */ +#define ADC_ENABLE_BIT (0x00000080) +#define ADC_SOFTWARE_RESET (0x00000040) +#define LST_SEQ_SET (0x0000001F) +#define TCR_SC_SET (0x00000001) + +#define HLST_SEQ_SET (0x0000001F) +#define HTCR_SC_SET (0x00000001) + +#if (LIBCFG_ADC_IVREF) +#define ADC_VREF_MVDDAEN (0x00000100) +#endif +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions ADC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the HT_ADCn peripheral registers to their default reset values. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + if (HT_ADCn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.ADC0 = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Reset ADC. + * @param HT_ADCn: is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_Reset(HT_ADC_TypeDef* HT_ADCn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + HT_ADCn->CR |= ADC_SOFTWARE_RESET; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->CR |= ADC_ENABLE_BIT; + ADC_Reset(HT_ADCn); + } + else + { + HT_ADCn->CR &= ~(ADC_ENABLE_BIT); + } +} + +/*********************************************************************************************************//** + * @brief Configure conversion mode and length of list queue for regular group. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_MODE: ADC Cyclic Conversion Mode. + * This parameter can be one of the following values: + * @arg ONE_SHOT_MODE : + * @arg CONTINUOUS_MODE : + * @arg DISCONTINUOUS_MODE : + * @param Length: must between 1 ~ 8 + * @param SubLength: must between 1 ~ 8, only valid for DISCONTINUOUS_MODE. + * @retval None + ************************************************************************************************************/ +void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CONVERSION_MODE(ADC_MODE)); + Assert_Param(IS_ADC_REGULAR_LENGTH(Length)); + if (ADC_MODE == DISCONTINUOUS_MODE) + { + Assert_Param(IS_ADC_REGULAR_SUB_LENGTH(SubLength)); + } + + /* Config cyclic conversion mode and length of list queue and sub length for regular group */ + HT_ADCn->CR = ((u32)(SubLength - 1) << 16) | ((u32)(Length - 1) << 8) | ADC_MODE | (HT_ADCn->CR & ADC_ENABLE_BIT); +} + +/*********************************************************************************************************//** + * @brief Configure the corresponding rank in the sequencer and the sampling time for the regular channel + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel n selected, n must between 0 ~ m (m represent the maximum external ADC input channel). + * @arg ADC_CH_DAC1 : ADC DAC1 selected + * @arg ADC_CH_DAC0 : ADC DAC0 selected + * @arg ADC_CH_IVREF : ADC Internal VREF selected + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @arg ADC_CH_MVDDA : ADC MVDDA selected + * @param Rank: The rank in the regular group sequencer. + * This parameter must be between 0 to 7. + * @param SampleClock: must between 0 ~ 255. + * @retval None + ************************************************************************************************************/ +void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock) +{ + u32 tmpreg1, tmpreg2; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_REGULAR_RANK(Rank)); + Assert_Param(IS_ADC_INPUT_SAMPLING_TIME(SampleClock)); + + /* config sampling clock of ADC input channel */ + HT_ADCn->STR = SampleClock; + /* Get the old register value */ + tmpreg1 = HT_ADCn->LST[Rank >> 2]; + /* Calculate the mask to clear */ + tmpreg2 = LST_SEQ_SET << (8 * (Rank & 0x3)); + /* Clear the old SEQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_CH_n << (8 * (Rank & 0x3)); + /* Set the SEQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + HT_ADCn->LST[Rank >> 2] = tmpreg1; +} + +/*********************************************************************************************************//** + * @brief Configure the ADC trigger source for regular channels conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_TRIG_x: + * This parameter can be one of the following values: + * @arg ADC_TRIG_SOFTWARE : S/W trigger + * @arg ADC_TRIG_EXTI_n : where n can be 0 ~ 15 + * @arg ADC_TRIG_MCTMn_MTO : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_GPTMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_TRIG_BFTMn : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_TRIG_CMPn : where n can be 0 ~ 1 + * @retval None + ************************************************************************************************************/ +void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_TRIG(ADC_TRIG_x)); + + /* Config external trigger conversion source of regular group */ + HT_ADCn->TCR = ADC_TRIG_x & 0x0000001F; + HT_ADCn->TSR = ADC_TRIG_x & (~0x0000001F); +} + +/*********************************************************************************************************//** + * @brief Configure the sampling time for the ADC input channel. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param SampleClock: must between 0 ~ 255. + * @retval None + ************************************************************************************************************/ +void ADC_SamplingTimeConfig(HT_ADC_TypeDef* HT_ADCn, u8 SampleClock) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + /* config sampling clock of ADC input channel */ + HT_ADCn->STR = SampleClock; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable software start of the regular channel conversion of the selected ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Start Conversion */ + if (NewState != DISABLE) + { + HT_ADCn->TSR |= TCR_SC_SET; + } + else + { + HT_ADCn->TSR &= ~TCR_SC_SET; + } +} + +/*********************************************************************************************************//** + * @brief Return the result of ADC regular channel conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_REGULAR_DATAn: where n can be 0 ~ 7 + * @retval The Value of data conversion. + ************************************************************************************************************/ +u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_REGULAR_DATA(ADC_REGULAR_DATAn)); + + return ((u16)HT_ADCn->DR[ADC_REGULAR_DATAn]); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC interrupts. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the ADC interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->IER |= ADC_INT_x; + } + else + { + HT_ADCn->IER &= ~ADC_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC interrupt has occurred. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + if ((HT_ADCn->ISR & ADC_INT_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Clear the ADC interrupt pending bits. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt pending bits to be cleared. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + HT_ADCn->ICLR = ADC_INT_x; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC flag has been set. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_FLAG_x: Specify the flag to check. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_SINGLE_EOC : + * @arg ADC_FLAG_SUB_GROUP_EOC : + * @arg ADC_FLAG_CYCLE_EOC : + * @arg ADC_FLAG_DATA_OVERWRITE : + * @arg ADC_FLAG_AWD_LOWER : + * @arg ADC_FLAG_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_FLAG(ADC_FLAG_x)); + + if ((HT_ADCn->IRAW & ADC_FLAG_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable Lower/Upper threshold warning of the analog watchdog on single/all channels. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_AWD_x: + * This parameter can be any combination of the following values: + * @arg ADC_AWD_DISABLE : + * @arg ADC_AWD_ALL_LOWER : + * @arg ADC_AWD_ALL_UPPER : + * @arg ADC_AWD_ALL_LOWER_UPPER : + * @arg ADC_AWD_SINGLE_LOWER : + * @arg ADC_AWD_SINGLE_UPPER : + * @arg ADC_AWD_SINGLE_LOWER_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_AWD(ADC_AWD_x)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFFFF8) | ADC_AWD_x; +} + +/*********************************************************************************************************//** + * @brief Configure the analog watchdog that guards single channel. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: where n must between 0 ~ m (m represent the maximum external ADC input channel). + * @retval None + ************************************************************************************************************/ +void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INPUT_CHANNEL(ADC_CH_n)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFF0FF) | ((u32)ADC_CH_n << 8); +} + +/*********************************************************************************************************//** + * @brief Configure the high and low thresholds of the analog watchdog. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param UPPER: must between 0x0000 ~ 0x0FFF + * @param LOWER: must between 0x0000 ~ 0x0FFF + * @retval None + ************************************************************************************************************/ +void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_THRESHOLD(UPPER)); + Assert_Param(IS_ADC_THRESHOLD(LOWER)); + + HT_ADCn->WTR = (UPPER << 16) | LOWER; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified PDMA request. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_PDMA_x: Specify the ADC PDMA request that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_PDMA_REGULAR_SINGLE : + * @arg ADC_PDMA_REGULAR_SUBGROUP : + * @arg ADC_PDMA_REGULAR_CYCLE : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_PDMA(ADC_PDMA_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->PDMAR |= ADC_PDMA_x; + } + else + { + HT_ADCn->PDMAR &= ~ADC_PDMA_x; + } +} + +#if (LIBCFG_ADC_IVREF) +/*********************************************************************************************************//** + * @brief Enable or Disable the VREF. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_VREFCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->VREFCR |= 0x00000001; + } + else + { + HT_ADCn->VREFCR &= ~(0x00000001); + } +} + +/*********************************************************************************************************//** + * @brief Configure the VREF output voltage. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_VREF_x: + * This parameter can be one of the following value: + * @arg ADC_VREF_1V215 : + * @arg ADC_VREF_2V0 : + * @arg ADC_VREF_2V5 : + * @arg ADC_VREF_2V7 : + * @retval None + ************************************************************************************************************/ +void ADC_VREFConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_VREF_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_VREF_SEL(ADC_VREF_x)); + + HT_ADCn->VREFCR = (HT_ADCn->VREFCR & ~(3ul << 4)) | (ADC_VREF_x); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the power of MVDDA (VDDA/2) + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_MVDDACmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->VREFCR |= ADC_VREF_MVDDAEN; + } + else + { + HT_ADCn->VREFCR &= ~(ADC_VREF_MVDDAEN); + } +} + +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_aes.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_aes.c new file mode 100644 index 00000000000..c6e8ea2a5b8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_aes.c @@ -0,0 +1,550 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_aes.c + * @version $Rev:: 2788 $ + * @date $Date:: 2022-11-24 #$ + * @brief This file provides all the AES firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_aes.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup AES AES + * @brief AES driver modules + * @{ + */ + + +/* Global variables ----------------------------------------------------------------------------------------*/ +u32 *gpu32OutputBuff; +u32 gu32OutputIndex = 0; + +u32 *gpu32InputBuff; +u32 gu32InputSize = 0; +u32 gu32InputIndex = 0; + +/* Private functions ---------------------------------------------------------------------------------------*/ +static void _AES_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Functions AES exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the AES peripheral registers to their default reset values. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AES_DeInit(HT_AES_TypeDef* HT_AESn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + if (HT_AESn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.AES = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Flush the FIFO. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AES_FIFOFlush(HT_AES_TypeDef* HT_AESn) +{ + AES_Cmd(HT_AESn, DISABLE); + HT_AESn->CR |= AES_FLUSH_ENABLE; + AES_Cmd(HT_AESn, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified AES. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void AES_Cmd(HT_AES_TypeDef* HT_AESn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_AESn->CR |= AES_ENABLE; + } + else + { + HT_AESn->CR &= ~AES_ENABLE; + } +} + +/*********************************************************************************************************//** + * @brief Start the AES key. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AES_StartKey(HT_AES_TypeDef* HT_AESn) +{ + HT_AESn->CR |= (1 << 4); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where AES is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void _AES_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_KEY_SIZE(AES_InitStruct->AES_KeySize)); + Assert_Param(IS_AES_DIR(AES_InitStruct->AES_Dir)); + Assert_Param(IS_AES_MODE(AES_InitStruct->AES_Mode)); + Assert_Param(IS_AES_SWAP(AES_InitStruct->AES_Swap)); + + HT_AESn->CR = (HT_AESn->CR & 0xFFFFFE81) | AES_InitStruct->AES_KeySize | + AES_InitStruct->AES_Dir | AES_InitStruct->AES_Mode | + AES_InitStruct->AES_Swap; + + AES_Cmd(HT_AESn, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral on ECB mode according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where AES is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void AES_ECB_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + AES_InitStruct->AES_Mode = AES_MODE_ECB; + _AES_Init(HT_AESn, AES_InitStruct); + + AES_IntConfig(HT_AESn, AES_IER_OFINTEN, ENABLE); + NVIC_EnableIRQ(AES_IRQn); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral on CBC mode according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where AES is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void AES_CBC_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + AES_InitStruct->AES_Mode = AES_MODE_CBC; + _AES_Init(HT_AESn, AES_InitStruct); + + AES_IntConfig(HT_AESn, AES_IER_OFINTEN, ENABLE); + NVIC_EnableIRQ(AES_IRQn); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral on CTR mode according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where HT_AESn is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void AES_CTR_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + AES_InitStruct->AES_Mode = AES_MODE_CTR; + _AES_Init(HT_AESn, AES_InitStruct); + + AES_IntConfig(HT_AESn, AES_IER_OFINTEN, ENABLE); + NVIC_EnableIRQ(AES_IRQn); +} + +/*********************************************************************************************************//** + * @brief Check whether the specified AES status has been set. + * @param HT_AESn: where HT_AESn is the selected AES peripheral. + * @param AES_SR_x: specify the flag to be check. + * This parameter can be one of the following values: + * @arg AES_SR_IFEMPTY : AES Input FIFO is Empty + * @arg AES_SR_IFNFULL : AES Input FIFO is not Full + * @arg AES_SR_OFNEMPTY : AES Output FIFO is not Empty + * @arg AES_SR_OFFULL : AES Output FIFO is Full + * @arg AES_SR_BUSY : AES is busy when AES is in encrypt/decrypt action and key expansion + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus AES_GetStatus(HT_AES_TypeDef* HT_AESn, u32 AES_SR_x) +{ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_STATUS(AES_SR_x)); + + if ((HT_AESn->SR & AES_SR_x) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the AES PDMA interface. + * @param HT_AESn: where HT_AESn is the selected HT_AESn peripheral. + * @param AES_PDMA_xFDMAEN: specify the AES FIFO DMA to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg AES_PDMA_IFDMAEN : input FIFO PDMA + * @arg AES_PDMA_OFDMAEN : Output FIFO PDMA + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void AES_PDMACmd(HT_AES_TypeDef* HT_AESn, u32 AES_PDMA_xFDMAEN, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_AESn->PDMAR |= AES_PDMA_xFDMAEN; + } + else + { + HT_AESn->PDMAR &= ~AES_PDMA_xFDMAEN; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified AES interrupt has occurred. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param AES_INTSR_x: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * @arg AES_INTSR_IFINT : + * @arg AES_INTSR_OFINT : + * @return SET or RESET + ************************************************************************************************************/ +FlagStatus AES_GetIntStatus(HT_AES_TypeDef* HT_AESn, u32 AES_INTSR_x) +{ + FlagStatus Status; + u32 aes_isr = HT_AESn->ISR; + u32 aes_ier = HT_AESn->IER; + + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_INTSR(AES_INTSR_x)); + + Status = (FlagStatus)(aes_isr & aes_ier); + if ((Status & AES_INTSR_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified AES interrupts. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param AES_IER_x: Specify the AES interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg AES_IER_IFINTEN : + * @arg AES_IER_OFINTEN : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void AES_IntConfig(HT_AES_TypeDef* HT_AESn, u32 AES_IER_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_IER(AES_IER_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_AESn->IER |= AES_IER_x; + } + else + { + HT_AESn->IER &= ~AES_IER_x; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified AES Input data. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param AES_Data: Data input + * @retval None + ************************************************************************************************************/ +void AES_SetInputData(HT_AES_TypeDef* HT_AESn, uc32 AES_Data) +{ + Assert_Param(IS_AES(HT_AESn)); + #if (LIBCFG_AES_SWAP) + HT_AESn->DINR = __REV(AES_Data); + #else + HT_AESn->DINR = AES_Data; + #endif +} + +/*********************************************************************************************************//** + * @brief Get the specified AES output data. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @retval Output Data + ************************************************************************************************************/ +u32 AES_GetOutputData(HT_AES_TypeDef* HT_AESn) +{ + Assert_Param(IS_AES(HT_AESn)); + #if (LIBCFG_AES_SWAP) + return __REV(HT_AESn->DOUTR); + #else + return HT_AESn->DOUTR; + #endif +} + +/*********************************************************************************************************//** + * @brief Set the specified AES key table. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param Key: Key table + * @param keySize: Key table's size + * @retval None + ************************************************************************************************************/ +void AES_SetKeyTable(HT_AES_TypeDef* HT_AESn, uc8* Key, u32 keySize) +{ + u32 i; + u32 uCRTemp = HT_AESn->CR & (~(0x00000060UL)); + if (keySize == 128/8) + { + uCRTemp |= AES_KEYSIZE_128B; + } + else if (keySize == 192/8) + { + uCRTemp |= AES_KEYSIZE_192B; + } + else if (keySize == 256/8) + { + uCRTemp |= AES_KEYSIZE_256B; + } + else + { + return; + } + HT_AESn->CR = uCRTemp; + + for (i = 0; i < keySize; i += 4) + { + #if (LIBCFG_AES_SWAP) + HT_AESn->KEYR[i >> 2] = __REV(*(u32*)&Key[i]); + #else + HT_AESn->KEYR[i >> 2] = *(u32*)&Key[i]; + #endif + } + + AES_StartKey(HT_AES); +} + +/*********************************************************************************************************//** + * @brief Set the specified AES Vector table. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param Vector: + * @retval None + ************************************************************************************************************/ +void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, uc8* Vector) +{ + int i; + Assert_Param(IS_AES(HT_AESn)); + + for (i = 0; i < 16; i += 4) + { + #if (LIBCFG_AES_SWAP) + HT_AESn->IVR[i >> 2] = __REV(*(u32*)&Vector[i]); + #else + HT_AESn->IVR[i >> 2] = *(u32*)&Vector[i]; + #endif + } +} + +/*********************************************************************************************************//** + * @brief AES Crypt Data + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param dir: Crypt Data's direction + * @param iv: initial vector table + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus _AES_CryptData(HT_AES_TypeDef* HT_AESn, + AES_DIR_Enum dir, + uc8 *iv, + u32 length, + uc8 *inputData, + u8 *outputData) +{ + /*AES Data blocks 16 byte */ + if ((length % 16) != 0) + { + /* Data size can not be divisible by 16. */ + return ERROR; + } + + /*Set inital Vector */ + if (iv != NULL) + { + AES_SetVectorTable(HT_AESn, iv); + } + + /*FIFO Flush */ + AES_FIFOFlush(HT_AES); + + /*Set direction */ + HT_AESn->CR = (HT_AESn->CR & 0xFFFFFFFD) | dir; + + /*Create input/output data */ + gpu32InputBuff = (u32*)inputData; + gpu32OutputBuff = (u32*)outputData; + + /*Init Index */ + gu32OutputIndex = 0; + gu32InputSize = length/4; + + /*Set input data */ + AES_IntConfig(HT_AES, AES_IER_IFINTEN, ENABLE); + + /*Waitting for conversion */ + while (AES_GetStatus(HT_AES, AES_SR_OFNEMPTY)); + return SUCCESS; +} + +#if 0 +/*********************************************************************************************************//** + * @brief AES Crypt Data on ECB mode + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param dir: Crypt Data's direction + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus AES_ECB_CryptData(HT_AES_TypeDef* HT_AESn, + AES_DIR_Enum dir, + u32 length, + uc8 *inputData, + u8 *outputData) +{ + return _AES_CryptData(HT_AESn, + dir, + NULL, + length, + inputData, + outputData); +} + +/*********************************************************************************************************//** + * @brief AES Crypt Data on CBC mode + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param dir: Crypt Data's direction + * @param iv: initial vector table + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus AES_CBC_CryptData(HT_AES_TypeDef* HT_AESn, + AES_DIR_Enum dir, + uc8 *iv, + u32 length, + uc8 *inputData, + u8 *outputData) +{ + return _AES_CryptData(HT_AESn, + dir, + iv, + length, + inputData, + outputData); +} + +/*********************************************************************************************************//** + * @brief AES Crypt Data on CTR mode + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param iv: initial vector table + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus AES_CTR_CryptData(HT_AES_TypeDef* HT_AESn, + uc8 *iv, + u32 length, + uc8 *inputData, + u8 *outputData) +{ + return _AES_CryptData(HT_AESn, + AES_DIR_ENCRYPT, + iv, + length, + inputData, + outputData); +} +#endif + +/*********************************************************************************************************//** + * @brief This function handles AES Core interrupt. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AESCore_IRQHandler(HT_AES_TypeDef* HT_AESn) +{ + if (AES_GetIntStatus(HT_AES, AES_INTSR_OFINT)) + { + gpu32OutputBuff[gu32OutputIndex++] = AES_GetOutputData(HT_AES); + } + if (AES_GetIntStatus(HT_AES, AES_INTSR_IFINT)) + { + if (gu32InputIndex < gu32InputSize) + { + AES_SetInputData(HT_AES, gpu32InputBuff[gu32InputIndex]); + gu32InputIndex++; + } + else + { + AES_IntConfig(HT_AES, AES_IER_IFINTEN, DISABLE); + gu32InputIndex = 0; + } + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_bftm.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_bftm.c new file mode 100644 index 00000000000..c38bebac7ee --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_bftm.c @@ -0,0 +1,240 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_bftm.c + * @version $Rev:: 2789 $ + * @date $Date:: 2022-11-24 #$ + * @brief This file provides all the BFTM firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_bftm.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup BFTM BFTM + * @brief BFTM driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Functions BFTM exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the specified BFTM registers to their default values. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval None + ************************************************************************************************************/ +void BFTM_DeInit(HT_BFTM_TypeDef* HT_BFTMn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + if (HT_BFTMn == HT_BFTM0) + { + RSTCUReset.Bit.BFTM0 = 1; + } + else if (HT_BFTMn == HT_BFTM1) + { + RSTCUReset.Bit.BFTM1 = 1; + } + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void BFTM_EnaCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_BFTMn->CR |= (1UL << 2); + } + else + { + HT_BFTMn->CR &= ~(1UL << 2); + } +} + +/*********************************************************************************************************//** + * @brief Configure the CMP register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param uCompare: Specify a value to the CMP register. + * @retval None + ************************************************************************************************************/ +void BFTM_SetCompare(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCompare) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + HT_BFTMn->CMP = uCompare; +} + +/*********************************************************************************************************//** + * @brief Get the CMP register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval The value of the CMP register + ************************************************************************************************************/ +u32 BFTM_GetCompare(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + return HT_BFTMn->CMP; +} + +/*********************************************************************************************************//** + * @brief Set the CNTR register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param uCounter: Specify a new value to the CNTR register. + * @retval None + ************************************************************************************************************/ +void BFTM_SetCounter(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCounter) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + HT_BFTMn->CNTR = uCounter; +} + +/*********************************************************************************************************//** + * @brief Get the CNTR register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval The value of the CNTR register + ************************************************************************************************************/ +u32 BFTM_GetCounter(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + return HT_BFTMn->CNTR; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the one shot mode of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void BFTM_OneShotModeCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_BFTMn->CR |= (1UL << 1); + } + else + { + HT_BFTMn->CR &= ~(1UL << 1); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified BFTM interrupt. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void BFTM_IntConfig(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_BFTMn->CR |= BFTM_INT_MATCH; + } + else + { + HT_BFTMn->CR &= ~BFTM_INT_MATCH; + } +} + +/*********************************************************************************************************//** + * @brief Get the flag status of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus BFTM_GetFlagStatus(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + if (HT_BFTMn->SR & BFTM_FLAG_MATCH) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the interrupt flag of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval None + ************************************************************************************************************/ +void BFTM_ClearFlag(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + HT_BFTMn->SR &= ~BFTM_FLAG_MATCH; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ckcu.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ckcu.c new file mode 100644 index 00000000000..81e7f8f143d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ckcu.c @@ -0,0 +1,1076 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_ckcu.c + * @version $Rev:: 2972 $ + * @date $Date:: 2023-10-28 #$ + * @brief This file provides all the Clock Control Unit firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_ckcu.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CKCU CKCU + * @brief CKCU driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Private_Define CKCU private definitions + * @{ + */ + +/* GCFGR bit field definition */ +#define CKCU_POS_CKOUTSRC 0 +#define CKCU_MASK_CKOUTSRC ((u32)0x7 << CKCU_POS_CKOUTSRC) + +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_POS_USBSRC 10 +#define CKCU_MASK_USBSRC ((u32)0x1 << CKCU_POS_USBSRC) +#endif + +#define CKCU_POS_CKREFPRE 11 +#define CKCU_MASK_CKREFPRE ((u32)0x1F << CKCU_POS_CKREFPRE) + +#if (LIBCFG_CKCU_USART_PRESCALER) +#define CKCU_POS_URPRE 20 +#define CKCU_MASK_URPRE ((u32)0x3 << CKCU_POS_URPRE) +#endif + +#if (!LIBCFG_NO_CKCU_USBPRE) +#define CKCU_POS_USBPRE 22 +#define CKCU_MASK_USBPRE ((u32)0x3 << CKCU_POS_USBPRE) +#endif + +/* GCCR bit field definition */ +#define CKCU_POS_SW 0 +#if (LIBCFG_CKCU_NO_HCLK_LOW_SPEED) +#define CKCU_MASK_SW ((u32)0x3 << CKCU_POS_SW) +#else +#define CKCU_MASK_SW ((u32)0x7 << CKCU_POS_SW) +#endif + +/* PLLCFGR bit field definition */ +#define CKCU_POS_POTD 21 +#define CKCU_MASK_POTD ((u32)0x3 << CKCU_POS_POTD) + +#define CKCU_POS_PFBD 23 +#if (LIBCDG_CKCU_PLL_144M) +#define CKCU_MASK_PFBD ((u32)0x3F << CKCU_POS_PFBD) +#else +#define CKCU_MASK_PFBD ((u32)0x1F << CKCU_POS_PFBD) +#endif + +/* APBCFGR bit field definition */ +#define CKCU_POS_ADCDIV 16 +#define CKCU_MASK_ADCDIV ((u32)0x7 << CKCU_POS_ADCDIV) + +/* CKST bit field definition */ +#define CKCU_POS_PLLST 8 +#define CKCU_MASK_PLLST ((u32)0xF << CKCU_POS_PLLST) + +#define CKCU_POS_HSEST 16 +#define CKCU_MASK_HSEST ((u32)0x3 << CKCU_POS_HSEST) + +#define CKCU_POS_HSIST 24 +#define CKCU_MASK_HSIST ((u32)0x7 << CKCU_POS_HSIST) + +#if (LIBCFG_CKCU_CKSWST_LEGACY) +#define CKCU_POS_CKSWST 30 +#define CKCU_MASK_CKSWST ((u32)0x3 << CKCU_POS_CKSWST) +#else +#define CKCU_POS_CKSWST 0 +#define CKCU_MASK_CKSWST ((u32)0x7 << CKCU_POS_CKSWST) +#endif + +/* GCFGR Bit Band Alias */ +#define CKCU_BB_PLLSRC BitBand((u32)&HT_CKCU->GCFGR, 8) +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_BB_USBPLLSRC BitBand((u32)&HT_CKCU->GCFGR, 9) +#endif + +/* GCCR Bit Band Alias */ +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_BB_USBPLLEN BitBand((u32)&HT_CKCU->GCCR, 3) +#endif +#define CKCU_BB_PLLEN BitBand((u32)&HT_CKCU->GCCR, 9) +#define CKCU_BB_HSEEN BitBand((u32)&HT_CKCU->GCCR, 10) +#define CKCU_BB_HSIEN BitBand((u32)&HT_CKCU->GCCR, 11) +#define CKCU_BB_CKMEN BitBand((u32)&HT_CKCU->GCCR, 16) +#define CKCU_BB_PSRCEN BitBand((u32)&HT_CKCU->GCCR, 17) + +/* GCIR Bit Band Alias */ +#define CKCU_BB_CKSF BitBand((u32)&HT_CKCU->GCIR, 0) +#define CKCU_BB_CKSIE BitBand((u32)&HT_CKCU->GCIR, 16) + +/* PLLCR Bit Band Alias */ +#define CKCU_BB_PLLBYPASS BitBand((u32)&HT_CKCU->PLLCR, 31) + +#if (!LIBCFG_NO_BACK_DOMAIN) +/* LPCR Bit Band Alias */ +#define CKCU_BB_BKISO BitBand((u32)&HT_CKCU->LPCR, 0) +#endif + +#if (!LIBCFG_CKCU_HSI_NO_AUTOTRIM) +/* HSICR Bit Band Alias */ +#define CKCU_BB_TRIMEN BitBand((u32)&HT_CKCU->HSICR, 0) +#define CKCU_BB_ATCEN BitBand((u32)&HT_CKCU->HSICR, 1) +#define CKCU_BB_REFCLKSEL0 BitBand((u32)&HT_CKCU->HSICR, 5) +#define CKCU_BB_REFCLKSEL1 BitBand((u32)&HT_CKCU->HSICR, 6) +#endif + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Private_Macro CKCU private macros + * @{ + */ +#define CKCU_BF_WRITE(Reg, Mask, Pos, WriteValue) (Reg = ((Reg & ~((u32)Mask)) | ((u32)WriteValue << Pos))) +#define CKCU_BF_READ(Reg, Mask, Pos) ((Reg & (u32)Mask) >> Pos) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup CKCU_Exported_Functions CKCU exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CKCU registers to the reset values. + * @retval None + ************************************************************************************************************/ +void CKCU_DeInit(void) +{ + /* Reset system clock */ + CKCU_HSICmd(ENABLE); + while (CKCU_GetClockReadyStatus(CKCU_FLAG_HSIRDY) == RESET); + CKCU_SysClockConfig(CKCU_SW_HSI); + +#if (LIBCFG_CKCU_USB_PLL) + HT_CKCU->GCFGR = 0x00000302; /* Reset value of GCFGR */ +#else + HT_CKCU->GCFGR = 0x00000102; /* Reset value of GCFGR */ +#endif + HT_CKCU->GCCR = 0x00000803; /* Reset value of GCCR */ +#if (LIBCFG_CKCU_USB_PLL) + HT_CKCU->GCIR = 0x0000007F; /* Clear all interrupt flags */ +#else + HT_CKCU->GCIR = 0x0000007D; /* Clear all interrupt flags */ +#endif + + HT_CKCU->PLLCR = 0; /* Reset value of PLLCR */ + HT_CKCU->AHBCFGR = 0; /* Reset value of AHBCFGR */ + HT_CKCU->AHBCCR = 0x000000E5; /* Reset value of AHBCCR */ + HT_CKCU->APBCFGR = 0x00010000; /* Reset value of APBCFGR */ + HT_CKCU->APBCCR0 = 0; /* Reset value of APBCCR0 */ + HT_CKCU->APBCCR1 = 0; /* Reset value of APBCCR1 */ +#if (LIBCFG_CKCU_NO_APB_PRESCALER) +#else + HT_CKCU->APBPCSR0 = 0; /* Reset value of APBPCSR0 */ + HT_CKCU->APBPCSR1 = 0; /* Reset value of APBPCSR1 */ +#endif +#if (LIBCFG_CKCU_APBPCSR2) + HT_CKCU->APBPCSR2 = 0; /* Reset value of APBPCSR2 */ +#endif +#if (LIBCFG_CKCU_HSI_NO_AUTOTRIM) +#else + HT_CKCU->HSICR = 0; /* Reset value of HSICR */ + HT_CKCU->HSIATCR = 0; /* Reset value of HSIATCR */ +#endif + HT_CKCU->LPCR = 0; /* Reset value of LPCR */ + HT_CKCU->MCUDBGCR = 0; /* Reset value of MCUDBGCR */ +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the external high speed oscillator (HSE). + * @note HSE can not be stopped if it is used by system clock or PLL. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_HSECmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BB_HSEEN = Cmd; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the internal high speed oscillator (HSI). + * @note HSI can not be stopped if it is used by system clock or PLL. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_HSICmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BB_HSIEN = Cmd; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the PLL clock. + * @note PLL can not be stopped if it is used by system clock or CK_REF. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_PLLCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BB_PLLEN = Cmd; +} + +#if (LIBCFG_CKCU_USB_PLL) +/*********************************************************************************************************//** + * @brief Enable or Disable the USBPLL clock. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_USBPLLCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BB_USBPLLEN = Cmd; +} +#endif + +/*********************************************************************************************************//** + * @brief Wait for HSE is ready to be used. + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus CKCU_WaitHSEReady(void) +{ + u32 ReadyCnt = 0; + + /* Wait until HSE is ready or time-out occurred */ + while (CKCU_GetClockReadyStatus(CKCU_FLAG_HSERDY) != SET) + { + if (++ReadyCnt >= HSE_READY_TIME) + { + return ERROR; + } + } + + return SUCCESS; +} + +/*********************************************************************************************************//** + * @brief Check whether the specific clock ready flag is set or not. + * @param CKCU_FLAG: specify the clock ready flag. + * This parameter can be one of the following values: + * @arg CKCU_FLAG_USBPLLRDY : USB PLL ready flag + * @arg CKCU_FLAG_PLLRDY : PLL ready flag + * @arg CKCU_FLAG_HSERDY : HSE ready flag + * @arg CKCU_FLAG_HSIRDY : HSI ready flag + * @arg CKCU_FLAG_LSERDY : LSE ready flag + * @arg CKCU_FLAG_LSIRDY : LSI ready flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CKCU_GetClockReadyStatus(u32 CKCU_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_FLAG(CKCU_FLAG)); + + if (HT_CKCU->GCSR & CKCU_FLAG) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief This function is used to configure PLL. + * @param PLL_InitStruct: pointer to CKCU_PLLInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_PLLInit(CKCU_PLLInitTypeDef *PLL_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_PLL_CLKSRC(PLL_InitStruct->ClockSource)); + Assert_Param(IS_CONTROL_STATUS(PLL_InitStruct->BYPASSCmd)); + Assert_Param(IS_PLL_CFG(PLL_InitStruct->CFG)); + + CKCU_BB_PLLSRC = PLL_InitStruct->ClockSource; + CKCU_BB_PLLBYPASS = PLL_InitStruct->BYPASSCmd; + HT_CKCU->PLLCFGR = (HT_CKCU->PLLCFGR & 0x0000FFFF) | PLL_InitStruct->CFG; +} + +#if (LIBCFG_CKCU_USB_PLL) +/*********************************************************************************************************//** + * @brief This function is used to configure USBPLL. + * @param USBPLL_InitStruct: pointer to CKCU_PLLInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_USBPLLInit(CKCU_PLLInitTypeDef *USBPLL_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_PLL_CLKSRC(USBPLL_InitStruct->ClockSource)); + Assert_Param(IS_USBPLL_CFG(USBPLL_InitStruct->CFG)); + + CKCU_BB_USBPLLSRC = USBPLL_InitStruct->ClockSource; + HT_CKCU->PLLCFGR = (HT_CKCU->PLLCFGR & 0xFFFF0000) | USBPLL_InitStruct->CFG; +} + +/*********************************************************************************************************//** + * @brief Configure the CK_USB clock source. + * @param USBSRC: specify the USB clock source. + * This parameter can be one of the following values: + * @arg CKCU_CKPLL : CK_USB = CK_PLL + * @arg CKCU_CKUSBPLL : CK_USB = CK_USBPLL + * @retval None + ************************************************************************************************************/ +void CKCU_USBClockConfig(CKCU_USBSRC_TypeDef USBSRC) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_USBSRC, CKCU_POS_USBSRC, USBSRC); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure the CK_SYS source. + * @param CLKSRC: specify the system clock source. + * This parameter can be one of the following values: + * @arg CKCU_SW_PLL : PLL is selected as CK_SYS + * @arg CKCU_SW_HSE : HSE is selected as CK_SYS + * @arg CKCU_SW_HSI : HSI is selected as CK_SYS + * @arg CKCU_SW_LSE : LSE is selected as CK_SYS + * @arg CKCU_SW_LSI : LSI is selected as CK_SYS + * @retval None + ************************************************************************************************************/ +ErrStatus CKCU_SysClockConfig(CKCU_SW_TypeDef CLKSRC) +{ + u32 cnt = 0xFF; + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_SW, CKCU_POS_SW, CLKSRC); + + /* Wait until new system clock source is applied or time-out */ + while (--cnt) + { + if (CKCU_GetSysClockSource() == (u32)CLKSRC) + { + return SUCCESS; + } + } + + return ERROR; +} + +/*********************************************************************************************************//** + * @brief Return the source clock which is used as system clock. + * @retval The source clock used as system clock. + * 0x01: PLL is selected as system clock + * 0x02: HSE is selected as system clock + * 0x03: HSI is selected as system clock + * 0x06: LSE is selected as system clock + * 0x07: LSI is selected as system clock + ************************************************************************************************************/ +u32 CKCU_GetSysClockSource(void) +{ + return ((u32)CKCU_BF_READ(HT_CKCU->CKST, CKCU_MASK_CKSWST, CKCU_POS_CKSWST)); +} + +/*********************************************************************************************************//** + * @brief Configure the CK_AHB prescaler. + * @param HCLKPRE: specify the value of divider. + * This parameter can be one of the following values: + * @arg CKCU_SYSCLK_DIV1 : HCLK = CK_SYS + * @arg CKCU_SYSCLK_DIV2 : HCLK = CK_SYS / 2 + * @arg CKCU_SYSCLK_DIV4 : HCLK = CK_SYS / 4 + * @arg CKCU_SYSCLK_DIV8 : HCLK = CK_SYS / 8 + * @arg CKCU_SYSCLK_DIV16 : HCLK = CK_SYS / 16 + * @arg CKCU_SYSCLK_DIV32 : HCLK = CK_SYS / 32 + * @retval None + ************************************************************************************************************/ +void CKCU_SetHCLKPrescaler(CKCU_SYSCLKDIV_TypeDef HCLKPRE) +{ + HT_CKCU->AHBCFGR = HCLKPRE; +} + +/*********************************************************************************************************//** + * @brief Configure the CK_REF prescaler. + * @param CKREFPRE: specify the value of divider. + * This parameter can be: CKCU_CKREFPRE_DIV2 to CKCU_CKREFPRE_DIV64 (CK_REF = CK_PLL / (2 * (N + 1)), N = 0 ~ 31) + * @retval None + ************************************************************************************************************/ +void CKCU_SetCKREFPrescaler(CKCU_CKREFPRE_TypeDef CKREFPRE) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_CKREFPRE, CKCU_POS_CKREFPRE, CKREFPRE); +} + +#if (LIBCFG_CKCU_USART_PRESCALER) +/********************************************************************************************************//** + * @brief Configure the CK_USART prescaler. + * @param URPRE: specify the prescaler value. + * This parameter can be: + * @arg CKCU_URPRE_DIV1: USART clock divided by 1 + * @arg CKCU_URPRE_DIV2: USART clock divided by 2 + * @retval None + ************************************************************************************************************/ +void CKCU_SetUSARTPrescaler(CKCU_URPRE_TypeDef URPRE) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_URPRE, CKCU_POS_URPRE, URPRE); +} +#endif + +#if (!LIBCFG_NO_CKCU_USBPRE) +/*********************************************************************************************************//** + * @brief Configure the CK_USB prescaler. + * @param USBPRE: specify the value of divider. + * This parameter can be one of the following values: + * @arg CKCU_USBPRE_DIV1 : CK_USB = CK_PLL / 1 + * @arg CKCU_USBPRE_DIV2 : CK_USB = CK_PLL / 2 + * @arg CKCU_USBPRE_DIV3 : CK_USB = CK_PLL / 3 (For HT32F165x only) + * @retval None + ************************************************************************************************************/ +void CKCU_SetUSBPrescaler(CKCU_USBPRE_TypeDef USBPRE) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_USBPRE, CKCU_POS_USBPRE, USBPRE); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure the CK_ADC prescaler. + * @param CKCU_ADCPRE_ADCn: specify the ADCn. + * @param CKCU_ADCPRE_DIVn: specify the prescaler value. + * This parameter can be one of the following values: + * @arg CKCU_ADCPRE_DIV1 : CK_ADC = HCLK / 1 (HT32F12364 Only) + * @arg CKCU_ADCPRE_DIV2 : CK_ADC = HCLK / 2 + * @arg CKCU_ADCPRE_DIV4 : CK_ADC = HCLK / 4 + * @arg CKCU_ADCPRE_DIV5 : CK_ADC = HCLK / 5 (HT32F12364 Only) + * @arg CKCU_ADCPRE_DIV6 : CK_ADC = HCLK / 6 + * @arg CKCU_ADCPRE_DIV8 : CK_ADC = HCLK / 8 + * @arg CKCU_ADCPRE_DIV16 : CK_ADC = HCLK / 16 + * @arg CKCU_ADCPRE_DIV32 : CK_ADC = HCLK / 32 + * @arg CKCU_ADCPRE_DIV64 : CK_ADC = HCLK / 64 + * @retval None + ************************************************************************************************************/ +void CKCU_SetADCnPrescaler(CKCU_ADCPRE_ADCn_TypeDef CKCU_ADCPRE_ADCn, CKCU_ADCPRE_TypeDef CKCU_ADCPRE_DIVn) +{ + HT_CKCU->APBCFGR = (HT_CKCU->APBCFGR & (~(0x07 << CKCU_ADCPRE_ADCn))) | (CKCU_ADCPRE_DIVn << CKCU_ADCPRE_ADCn); +} + +/*********************************************************************************************************//** + * @brief Return the frequency of the different clocks. + * @param CKCU_Clk: pointer to CKCU_ClocksTypeDef structure to get the clocks frequency. + * @retval None + ************************************************************************************************************/ +void CKCU_GetClocksFrequency(CKCU_ClocksTypeDef* CKCU_Clk) +{ + u32 div; + #if (LIBCFG_CKCU_CKSWST_LEGACY) + u32 SystemCoreClockSrc = (HT_CKCU->CKST >> 30) & 3UL; + #else + u32 SystemCoreClockSrc = (HT_CKCU->CKST >> 0) & 7UL; + #endif + + CKCU_Clk->PLL_Freq = CKCU_GetPLLFrequency(); + + /* Get system frequency */ + switch (SystemCoreClockSrc) + { + case CKCU_SW_PLL: + CKCU_Clk->SYSCK_Freq = CKCU_Clk->PLL_Freq; + break; + case CKCU_SW_HSE: + CKCU_Clk->SYSCK_Freq = HSE_VALUE; + break; + case CKCU_SW_HSI: + CKCU_Clk->SYSCK_Freq = HSI_VALUE; + break; + #if (LIBCFG_CKCU_NO_HCLK_LOW_SPEED) + #else + case CKCU_SW_LSE: + CKCU_Clk->SYSCK_Freq = LSE_VALUE; + break; + case CKCU_SW_LSI: + CKCU_Clk->SYSCK_Freq = LSI_VALUE; + break; + #endif + default: + CKCU_Clk->SYSCK_Freq = 0; + break; + } + + /* Get HCLK frequency */ + CKCU_Clk->HCLK_Freq = (CKCU_Clk->SYSCK_Freq) >> (HT_CKCU->AHBCFGR); + + #if (LIBCFG_CKCU_USART_PRESCALER) + /* Get USART frequency */ + { + u32 urpre; + urpre = CKCU_BF_READ(HT_CKCU->GCFGR, CKCU_MASK_URPRE, CKCU_POS_URPRE); + CKCU_Clk->USART_Freq = (CKCU_Clk->HCLK_Freq) >> urpre; + } + #endif + + /* Get ADC frequency */ + div = CKCU_BF_READ(HT_CKCU->APBCFGR, CKCU_MASK_ADCDIV, CKCU_POS_ADCDIV); + CKCU_Clk->ADC0_Freq = (div == 7) ? ((CKCU_Clk->HCLK_Freq) / 6) : ((CKCU_Clk->HCLK_Freq) >> div); +} + +/*********************************************************************************************************//** + * @brief Return the frequency of the PLL. + * @retval PLL Frequency + ************************************************************************************************************/ +u32 CKCU_GetPLLFrequency(void) +{ + u32 pllNO, pllNF, ClockSrc; + + /* Get PLL frequency */ + if (CKCU_BB_PLLEN == DISABLE) + { + return 0; + } + + ClockSrc = (CKCU_BB_PLLSRC == CKCU_PLLSRC_HSE) ? HSE_VALUE : HSI_VALUE; + + if (CKCU_BB_PLLBYPASS == ENABLE) + { + return ClockSrc; + } + + pllNF = CKCU_BF_READ(HT_CKCU->PLLCFGR, CKCU_MASK_PFBD, CKCU_POS_PFBD); + if (pllNF == 0) + pllNF = 64; + + pllNO = CKCU_BF_READ(HT_CKCU->PLLCFGR, CKCU_MASK_POTD, CKCU_POS_POTD); + pllNO = (u8)0x1 << pllNO; + + return ((ClockSrc / pllNO) * pllNF); +} + +#if (LIBCFG_CKCU_NO_APB_PRESCALER == 0) +/*********************************************************************************************************//** + * @brief Configure the APB peripheral prescaler. + * @param Perip: specify the APB peripheral. + * This parameter can be: + * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, + * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, + * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, + * CKCU_PCLK_MCTM0, CKCU_PCLK_MCTM1, + * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, + * CKCU_PCLK_USART0, CKCU_PCLK_USART1, + * CKCU_PCLK_UART0, CKCU_PCLK_UART1, + * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC, CKCU_PCLK_CMP, + * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, + * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, + * CKCU_PCLK_I2S, + * CKCU_PCLK_SCTM0, CKCU_PCLK_SCTM1, + * CKCU_PCLK_PWM0 + * @param PCLKPrescaler: specify the value of prescaler. + * This parameter can be: + * @arg CKCU_APBCLKPRE_DIV1: specific peripheral clock = PCLK / 1 (inapplicable to BKPRCLK) + * @arg CKCU_APBCLKPRE_DIV2: specific peripheral clock = PCLK / 2 (inapplicable to BKPRCLK) + * @arg CKCU_APBCLKPRE_DIV4: specific peripheral clock = PCLK / 4 + * @arg CKCU_APBCLKPRE_DIV8: specific peripheral clock = PCLK / 8 + * @arg CKCU_APBCLKPRE_DIV16: specific peripheral clock = PCLK / 16 (BKPRCLK only) + * @arg CKCU_APBCLKPRE_DIV32: specific peripheral clock = PCLK / 32 (BKPRCLK only) + * @retval None + ************************************************************************************************************/ +void CKCU_SetPeripPrescaler(CKCU_PeripPrescaler_TypeDef Perip, CKCU_APBCLKPRE_TypeDef PCLKPrescaler) +{ + u32 *PCSR = (u32 *)((&HT_CKCU->APBPCSR0) + (Perip >> CKCU_APBPCSR_OFFSET)); + u32 Prescaler = PCLKPrescaler; + if (Perip == CKCU_PCLK_BKPR) + { + Prescaler -= 2; + } + Perip &= 0x0000001F; + CKCU_BF_WRITE(*PCSR, (3UL << Perip), Perip, Prescaler); +} +#endif + +/*********************************************************************************************************//** + * @brief Return the operating frequency of the specific APB peripheral. + * @param Perip: specify the APB peripheral. + * This parameter can be: + * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, + * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, + * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, + * CKCU_PCLK_MCTM0, CKCU_PCLK_MCTM1, + * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, + * CKCU_PCLK_USART0, CKCU_PCLK_USART1, + * CKCU_PCLK_UART0, CKCU_PCLK_UART1, + * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC, CKCU_PCLK_CMP, + * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, + * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, + * CKCU_PCLK_I2S, + * CKCU_PCLK_I2S, + * CKCU_PCLK_SCTM0, CKCU_PCLK_SCTM1, + * CKCU_PCLK_PWM0 + * @retval Frequency in Hz + ************************************************************************************************************/ +u32 CKCU_GetPeripFrequency(CKCU_PeripPrescaler_TypeDef Perip) +{ + CKCU_ClocksTypeDef Clock; + + #if (LIBCFG_CKCU_NO_APB_PRESCALER) + CKCU_GetClocksFrequency(&Clock); + return Clock.HCLK_Freq; + #else + u32 *PCSR = (u32 *)(&HT_CKCU->APBPCSR0 + (Perip >> CKCU_APBPCSR_OFFSET)); + u32 PCLKPrescaler = 0; + + if (Perip == CKCU_PCLK_BKPR) + { + PCLKPrescaler = 2; + } + + Perip &= 0x0000001F; + PCLKPrescaler += CKCU_BF_READ(*PCSR, (3UL << Perip), Perip); + + CKCU_GetClocksFrequency(&Clock); + return (Clock.HCLK_Freq >> (PCLKPrescaler)); + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the HSE Clock Monitor function. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_CKMCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BB_CKMEN = Cmd; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the power saving wakeup RC clock. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_PSRCWKUPCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BB_PSRCEN = Cmd; +} + +/*********************************************************************************************************//** + * @brief Select the output clock source through the CKOUT pin. + * @param CKOUTInit: pointer to CKCU_CKOUTInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_CKOUTConfig(CKCU_CKOUTInitTypeDef *CKOUTInit) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_CKOUTSRC, CKCU_POS_CKOUTSRC, CKOUTInit->CKOUTSRC); +} + +/*********************************************************************************************************//** + * @brief Check whether the specific CKCU interrupt has occurred or not. + * @param CKCU_INT: specify the CKCU interrupt source. + * This parameter can be any combination of the following values: + * @arg CKCU_INT_CKS, CKCU_INT_PLLRDY, CKCU_INT_HSERDY, CKCU_INT_HSIRDY, CKCU_INT_LSERDY, CKCU_INT_LSIRDY + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CKCU_GetIntStatus(u32 CKCU_INT) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_INT_FLAG(CKCU_INT)); + + if (HT_CKCU->GCIR & CKCU_INT) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the CKCU interrupt flag. + * @param CKCU_INT: specify the CKCU interrupt flag to clear. + * This parameter can be any combination of the following values: + * @arg CKCU_INT_CKS : HSE clock failure interrupt flag (NMI) + * @arg CKCU_INT_USBPLLRDY : USB PLL ready interrupt flag + * @arg CKCU_INT_PLLRDY : PLL ready interrupt flag + * @arg CKCU_INT_HSERDY : HSE ready interrupt flag + * @arg CKCU_INT_HSIRDY : HSI ready interrupt flag + * @arg CKCU_INT_LSERDY : LSE ready interrupt flag + * @arg CKCU_INT_LSIRDY : LSI ready interrupt flag + * @retval None + ************************************************************************************************************/ +void CKCU_ClearIntFlag(u32 CKCU_INT) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_INT_FLAG(CKCU_INT)); + + HT_CKCU->GCIR |= CKCU_INT; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specific CKCU interrupts. + * @param CKCU_INT: specify the CKCU interrupt source which is enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CKCU_INT_CKSIE : HSE clock failure interrupt (NMI) + * @arg CKCU_INT_USBPLLRDYIE : USB PLL ready interrupt + * @arg CKCU_INT_PLLRDYIE : PLL ready interrupt + * @arg CKCU_INT_HSERDYIE : HSE ready interrupt + * @arg CKCU_INT_HSIRDYIE : HSI ready interrupt + * @arg CKCU_INT_LSERDYIE : LSE ready interrupt + * @arg CKCU_INT_LSIRDYIE : LSI ready interrupt + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_IntConfig(u32 CKCU_INT, ControlStatus Cmd) +{ + u32 tmp1 = HT_CKCU->GCIR; + + /* Check the parameters */ + Assert_Param(IS_CKCU_INT(CKCU_INT)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + tmp1 |= CKCU_INT; + } + else + { + tmp1 &= ~CKCU_INT; + } + + /* Note: CKCU interrupt flags will be cleared by writing "1" */ +#if (LIBCFG_CKCU_USB_PLL) + tmp1 &= ~0x0000007F; +#else + tmp1 &= ~0x0000007D; +#endif + HT_CKCU->GCIR = tmp1; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the AHB peripheral clock during SLEEP mode. + * @param CKCU_CLK: specify the clock which is enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CKCU_AHBEN_SLEEP_FMC, CKCU_AHBEN_SLEEP_SRAM, CKCU_AHBEN_SLEEP_BM, CKCU_AHBEN_SLEEP_APB0, + * CKCU_AHBEN_SLEEP_APB1 + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_SleepClockConfig(u32 CKCU_CLK, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_SLEEP_AHB(CKCU_CLK)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + HT_CKCU->AHBCCR |= CKCU_CLK; + } + else + { + HT_CKCU->AHBCCR &= ~CKCU_CLK; + } +} + +/*********************************************************************************************************//** + * @brief Check if PLL clock used by the specific target source or not. + * @param Target: specify the target clock. + * This parameter can be one of the following values: + * @arg CKCU_PLLST_SYSCK : Is PLL used by system clock + * @arg CKCU_PLLST_USB : Is PLL used by USB + * @arg CKCU_PLLST_REFCK : Is PLL used by CK_REF + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_IS_PLL_USED(CKCU_PLLST_TypeDef Target) +{ + if ((HT_CKCU->CKST >> CKCU_POS_PLLST) & (u32)Target) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/*********************************************************************************************************//** + * @brief Check HSI clock used by the specific target source or not. + * @param Target: specify the target clock. + * This parameter can be one of the following values: + * @arg CKCU_HSIST_SYSCK : Is HSI used by system clock + * @arg CKCU_HSIST_PLL : Is HSI used by PLL + * @arg CKCU_HSIST_CKM : Is HSI used by clock monitor + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_IS_HSI_USED(CKCU_HSIST_TypeDef Target) +{ + if ((HT_CKCU->CKST >> CKCU_POS_HSIST) & (u32)Target) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/*********************************************************************************************************//** + * @brief Check HSE clock used by the specific target source or not. + * @param Target: specify the target clock. + * This parameter can be one of the following values: + * @arg CKCU_HSEST_SYSCK : Is HSE used by system clock + * @arg CKCU_HSEST_PLL : Is HSE used by PLL + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_IS_HSE_USED(CKCU_HSEST_TypeDef Target) +{ + if ((HT_CKCU->CKST >> CKCU_POS_HSEST) & (u32)Target) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specific debug function. + * @param CKCU_DBGx: specify the debug functions to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CKCU_DBG_SLEEP, CKCU_DBG_DEEPSLEEP1, CKCU_DBG_DEEPSLEEP2, CKCU_DBG_POWERDOWN, + * CKCU_DBG_MCTM0_HALT, CKCU_DBG_MCTM1_HALT, + * CKCU_DBG_GPTM0_HALT, CKCU_DBG_GPTM1_HALT, + * CKCU_DBG_PWM_HALT, CKCU_DBG_SCTM0_HALT, CKCU_DBG_SCTM1_HALT, + * CKCU_DBG_BFTM0_HALT, CKCU_DBG_BFTM1_HALT, + * CKCU_DBG_USART0_HALT, CKCU_DBG_USART1_HALT, + * CKCU_DBG_UART0_HALT, CKCU_DBG_UART1_HALT, + * CKCU_DBG_SPI0_HALT, CKCU_DBG_SPI1_HALT, + * CKCU_DBG_I2C0_HALT, CKCU_DBG_I2C1_HALT, + * CKCU_DBG_SCI0_HALT, CKCU_DBG_SCI1_HALT, + * CKCU_DBG_WDT_HALT, CKCU_DBG_TRACE_ON + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_MCUDBGConfig(u32 CKCU_DBGx, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_DBG(CKCU_DBGx)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + HT_CKCU->MCUDBGCR |= CKCU_DBGx; + } + else + { + HT_CKCU->MCUDBGCR &= ~CKCU_DBGx; + } +} + +#if (!LIBCFG_NO_BACK_DOMAIN) +/*********************************************************************************************************//** + * @brief Enable or Disable the Backup domain isolation control. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_BKISOCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + CKCU_BB_BKISO = 0; /* Backup domain is isolated */ + } + else + { + CKCU_BB_BKISO = 1; /* Backup domain is accessible */ + } +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the peripheral clock. + * @param Clock: specify the peripheral clock enable bits. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_PeripClockConfig(CKCU_PeripClockConfig_TypeDef Clock, ControlStatus Cmd) +{ + u32 uAHBCCR; + u32 uAPBCCR0; + u32 uAPBCCR1; + + uAHBCCR = HT_CKCU->AHBCCR; + uAPBCCR0 = HT_CKCU->APBCCR0; + uAPBCCR1 = HT_CKCU->APBCCR1; + + uAHBCCR &= ~(Clock.Reg[0]); + uAPBCCR0 &= ~(Clock.Reg[1]); + uAPBCCR1 &= ~(Clock.Reg[2]); + + if (Cmd != DISABLE) + { + uAHBCCR |= Clock.Reg[0]; + uAPBCCR0 |= Clock.Reg[1]; + uAPBCCR1 |= Clock.Reg[2]; + } + + HT_CKCU->AHBCCR = uAHBCCR; + HT_CKCU->APBCCR0 = uAPBCCR0; + HT_CKCU->APBCCR1 = uAPBCCR1; +} + +#if (!LIBCFG_CKCU_HSI_NO_AUTOTRIM) +/*********************************************************************************************************//** + * @brief Configure the reference clock of HSI auto-trim function. + * @param CLKSRC: specify the clock source. + * This parameter can be: + * @arg CKCU_ATC_LSE: LSE is selected as reference clock + * @arg CKCU_ATC_USB: USB is selected as reference clock + * @arg CKCU_ATC_CKIN: External pin (CKIN) is selected as reference clock + * @retval None + ************************************************************************************************************/ +void CKCU_HSIAutoTrimClkConfig(CKCU_ATC_TypeDef CLKSRC) +{ + #if (LIBCFG_CKCU_AUTOTRIM_NOCKIN==1) + HT_CKCU->HSICR = (HT_CKCU->HSICR & (~(0x1 << 5))) | (CLKSRC << 5); + #else + HT_CKCU->HSICR = (HT_CKCU->HSICR & (~(0x3 << 5))) | (CLKSRC << 5); + #endif +} + +#if (LIBCFG_CKCU_ATM_V01) +/*********************************************************************************************************//** + * @brief Initialize the ATC according to the specified parameters in the ATC_InitStruct. + * @param ATC_InitStruct: pointer to a CKCU_ATCInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_ATCInit(CKCU_ATCInitTypeDef* ATC_InitStruct) +{ + HT_CKCU->HSICR &= 0xFFFFFFF3; + HT_CKCU->HSICR |= (u32)ATC_InitStruct->SearchAlgorithm | (u32)ATC_InitStruct->FrqTolerance; +} + +/*********************************************************************************************************//** + * @brief Automatic Trimming Algorithm Mode Selection. + * @param Algo: Search Algorithm. + * This parameter can be: + * @arg CKCU_ATC_BINARY_SEARCH: Auto Trimming Controller is used binary search to approach the target range + * @arg CKCU_ATC_LINEAR_SEARCH: Auto Trimming Controller is used linear search to approach the target range + * @retval None + ***********************************************************************************************************/ +void CKCU_HSIAutoTrimAlgorithm(u32 Algo) +{ + HT_CKCU->HSICR = (HT_CKCU->HSICR & (~(0x1 << 3))) | Algo; +} + +/*********************************************************************************************************//** + * @brief Lock Target Range Selection. + * @param Tolerance: Variation Tolerance. + * This parameter can be: + * @arg CKCU_ATC_DOUBLE_PRECISION: 0.2 % variation + * @arg CKCU_ATC_SINGLE_PRECISION: 0.1 % variation + * @retval None + ***********************************************************************************************************/ +void CKCU_HSIAutoTrimFreqTolerance(u32 Tolerance) +{ + HT_CKCU->HSICR = (HT_CKCU->HSICR & (~(0x1 << 2))) | Tolerance; +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the HSI auto-trim function. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_HSIAutoTrimCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BB_TRIMEN = Cmd; + CKCU_BB_ATCEN = Cmd; +} + +/*********************************************************************************************************//** + * @brief Check Auto Trim is ready or not. + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_HSIAutoTrimIsReady(void) +{ +#if (LIBCFG_CKCU_AUTO_TRIM_LEGACY) + u32 lower_bound, upper_bound, i; + static u32 ATCR = 0; + + if ((HT_CKCU->HSICR & (3ul << 5)) == 0) + { + lower_bound = 7812 - 19; + upper_bound = 7812 + 19; + } + else + { + lower_bound = 8000 - 20; + upper_bound = 8000 + 20; + } + + SystemCoreClockUpdate(); + for (i = SystemCoreClock / 8000; i > 0; i--){}; + ATCR += HT_CKCU->HSIATCR; + ATCR /= 2; + + if ((ATCR >= lower_bound) && (ATCR <= upper_bound)) + { + ATCR = 0; + return TRUE; + } + else + { + return FALSE; + } + +#else + return (HT_CKCU->HSICR & 0x80) ? TRUE : FALSE; +#endif +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_cmp.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_cmp.c new file mode 100644 index 00000000000..ec0688153b8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_cmp.c @@ -0,0 +1,298 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_cmp.c + * @version $Rev:: 2794 $ + * @date $Date:: 2022-11-25 #$ + * @brief This file provides all the CMP firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_cmp.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CMP CMP + * @brief CMP driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Functions CMP exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CMP0 and CMP1 peripheral registers to their default reset values. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @retval None + ************************************************************************************************************/ +void CMP_DeInit(HT_CMP_TypeDef* HT_CMPn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + if (HT_CMPn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.CMP = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Unprotect the selected comparator configuration before setting the Comparator Control Register. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @retval None + ************************************************************************************************************/ +void CMP_UnprotectConfig(HT_CMP_TypeDef* HT_CMPn) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + + /* Set the unlock code corresponding to selected comparator */ + HT_CMPn->CR = CMP_PROTECT_KEY; +} + +/*********************************************************************************************************//** + * @brief Initialize the CMP peripheral according to the specified parameters in the CMP_InitStruct. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_InitStruct: pointer to a CMP_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CMP_Init(HT_CMP_TypeDef* HT_CMPn, CMP_InitTypeDef* CMP_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_Wakeup_Set(CMP_InitStruct->CMP_Wakeup)); + Assert_Param(IS_CMP_OutputSelection(CMP_InitStruct->CMP_OutputSelection)); + Assert_Param(IS_CMP_ScalerSource(CMP_InitStruct->CMP_ScalerSource)); + Assert_Param(IS_CMP_ScalerOutputBuf(CMP_InitStruct->CMP_ScalerOutputBuf)); + Assert_Param(IS_CMP_ScalerEnable(CMP_InitStruct->CMP_ScalerEnable)); + Assert_Param(IS_CMP_CoutSynchronized(CMP_InitStruct->CMP_CoutSync)); + Assert_Param(IS_CMP_OutputPol_Set(CMP_InitStruct->CMP_OutputPol)); + Assert_Param(IS_CMP_InvInputSelection(CMP_InitStruct->CMP_InvInputSelection)); + Assert_Param(IS_CMP_Hysteresis_Set(CMP_InitStruct->CMP_Hysteresis)); + Assert_Param(IS_CMP_Speed_Set(CMP_InitStruct->CMP_Speed)); + + HT_CMPn->CR |= CMP_InitStruct->CMP_Wakeup | CMP_InitStruct->CMP_OutputSelection | CMP_InitStruct->CMP_ScalerSource | \ + CMP_InitStruct->CMP_ScalerOutputBuf | CMP_InitStruct->CMP_ScalerEnable | CMP_InitStruct->CMP_CoutSync | \ + CMP_InitStruct->CMP_OutputPol | CMP_InitStruct->CMP_InvInputSelection | CMP_InitStruct->CMP_Hysteresis | \ + CMP_InitStruct->CMP_Speed; +} + +/*********************************************************************************************************//** + * @brief Fill each CMP_InitStruct member with its default value. + * @param CMP_InitStruct: pointer to an CMP_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CMP_StructInit(CMP_InitTypeDef* CMP_InitStruct) +{ + /* CMP_InitStruct members default value */ + CMP_InitStruct->CMP_Wakeup = CMP_WUP_DISABLE; + CMP_InitStruct->CMP_OutputSelection = CMP_TRIG_NONE; + CMP_InitStruct->CMP_ScalerSource = CMP_SCALER_SRC_VDDA; + CMP_InitStruct->CMP_ScalerOutputBuf = CMP_SCALER_OBUF_DISABLE; + CMP_InitStruct->CMP_ScalerEnable = CMP_SCALER_DISABLE; + CMP_InitStruct->CMP_CoutSync = CMP_ASYNC_OUTPUT; + CMP_InitStruct->CMP_OutputPol = CMP_NONINV_OUTPUT; + CMP_InitStruct->CMP_InvInputSelection = CMP_EXTERNAL_CN_IN; + CMP_InitStruct->CMP_Hysteresis = CMP_NO_HYSTERESIS; + CMP_InitStruct->CMP_Speed = CMP_LOW_SPEED; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP peripheral. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CMP_Cmd(HT_CMP_TypeDef* HT_CMPn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CMPn->CR |= CMP_ENABLE; + } + else + { + HT_CMPn->CR &= ~(u32)CMP_ENABLE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP interrupts. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_INT_x: specify the CMP interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CMP_INT_RE : CMP rising edge interrupt + * @arg CMP_INT_FE : CMP falling edge interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CMP_IntConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_INT(CMP_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CMPn->IER |= CMP_INT_x; + } + else + { + HT_CMPn->IER &= ~CMP_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP edge detection. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_xE_Detect: specify the CMP edge detection that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CMP_RE_Detect : CMP rising edge detection + * @arg CMP_FE_Detect : CMP falling edge detection + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CMP_EdgeDetectConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_xE_Detect, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_EdgeDetect(CMP_xE_Detect)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CMPn->TFR = (HT_CMPn->TFR | CMP_xE_Detect) & 0xfffffffc; + } + else + { + HT_CMPn->TFR = (HT_CMPn->TFR & (~CMP_xE_Detect)) & 0xfffffffc; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified CM flag has been set. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_FLAG_x: specify the flag to be checked. + * This parameter can be any combination of the following values: + * @arg CMP_FLAG_RE : CMP rising edge flag + * @arg CMP_FLAG_FE : CMP falling edge flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CMP_GetFlagStatus(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_FLAG(CMP_FLAG_x)); + + if ((HT_CMPn->TFR & CMP_FLAG_x) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear flags of the specified CMP. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_FLAG_x: specify the flag to be checked. + * This parameter can be any combination of the following values: + * @arg CMP_FLAG_RE : CMP rising edge flag + * @arg CMP_FLAG_FE : CMP falling edge flag + * @retval None + ************************************************************************************************************/ +void CMP_ClearFlag(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_FLAG(CMP_FLAG_x)); + + /* Clear the flags */ + HT_CMPn->TFR = (HT_CMPn->TFR & 0xfffffffc) | CMP_FLAG_x; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Get the output status of the specified CMP. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CMP_GetOutputStatus(HT_CMP_TypeDef* HT_CMPn) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + + if ((HT_CMPn-> CR & CMP_OUTPUT_HIGH) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified reference value in the data register of the scaler. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param Scaler_Value: value to be loaded in the selected data register + * @retval None + ************************************************************************************************************/ +void CMP_SetScalerValue(HT_CMP_TypeDef* HT_CMPn, u8 Scaler_Value) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_SCALER_VALUE(Scaler_Value)); + + /* Set the scaler reference value register */ + HT_CMPn->VALR = (u32)Scaler_Value; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_cmp_op.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_cmp_op.c new file mode 100644 index 00000000000..cd26f7a5d88 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_cmp_op.c @@ -0,0 +1,307 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_cmp_op.c + * @version $Rev:: 129 $ + * @date $Date:: 2017-06-14 #$ + * @brief This file provides all the CMP_OP firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_cmp_op.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CMP_OP CMP_OP + * @brief CMP_OP driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup CMP_OP_Private_Define CMP_OP private definitions + * @{ + */ +#define CMP_OP_ENABLE (0x00000001ul) +#define CMP_OP_CANCELLATION_MODE (0x00000004ul) +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CMP_OP_Exported_Functions CMP_OP exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CMP_OP peripheral registers to their default reset values. + * @param CMP_OPx: where x can be 0 or 1 to select the CMP_OP peripheral. + * @retval None + ************************************************************************************************************/ +void CMP_OP_DeInit(HT_CMP_OP_TypeDef* CMP_OPx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + + if (CMP_OPx == HT_CMP_OP0) + { + RSTCUReset.Bit.OPA0 = 1; + } + else + { + RSTCUReset.Bit.OPA1 = 1; + } + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure the CMP_OP peripheral as OPA or CMP mode and fill the cancellation value. + * @param CMP_OPx: where CMP_OP is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param mode: Specify the CMP_OPx peripheral mode + * This parameter can be any combination of the following values: + * @arg OP_MODE : Operational Amplifier mode + * @arg CMP_MODE : Comparator Mode Selection + * @param cancellation: Specify the input offset voltage cancellation value. + * @retval None +************************************************************************************************************/ +void CMP_OP_Config(HT_CMP_OP_TypeDef* CMP_OPx, u32 mode, u32 cancellation) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CMP_OP_MODE(mode)); + Assert_Param(IS_CMP_OP_IOVC(cancellation)); + + CMP_OPx->OPACR = (CMP_OPx->OPACR & CMP_OP_ENABLE) | mode; + CMP_OPx->OFVCR = cancellation; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP_OP peripheral. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param NewState: new state of the CMP_OPx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None +************************************************************************************************************/ +void CMP_OP_Cmd(HT_CMP_OP_TypeDef* CMP_OPx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CMP_OPx peripheral */ + CMP_OPx->OPACR |= CMP_OP_ENABLE; + } + else + { + /* Disable the selected CMP_OPx peripheral */ + CMP_OPx->OPACR &= ~(u32)CMP_OP_ENABLE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the CMP_OP peripheral as cancellation mode and select the source of reference input. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param CMP_OP_REF_INPUT: Specify the the source of reference input. + * This parameter can be any combination of the following values: + * @arg CMP_OP_NEGATIVE_INPUT + * @arg CMP_OP_POSITIVE_INPUT + * @retval None +************************************************************************************************************/ +void CMP_OP_CancellationModeConfig(HT_CMP_OP_TypeDef* CMP_OPx, u16 CMP_OP_REF_INPUT) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CMP_OP_REF(CMP_OP_REF_INPUT)); + + CMP_OPx->OPACR = (CMP_OPx->OPACR & CMP_OP_ENABLE) | CMP_OP_CANCELLATION_MODE | CMP_OP_REF_INPUT; +} + +/*********************************************************************************************************//** + * @brief Set input offset voltage cancellation value. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param cancellation: Specify the input offset voltage cancellation value. + * @retval None +************************************************************************************************************/ +void CMP_OP_SetCancellationVaule(HT_CMP_OP_TypeDef* CMP_OPx, u32 cancellation) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CMP_OP_IOVC(cancellation)); + + CMP_OPx->OFVCR = cancellation; +} + +/*********************************************************************************************************//** + * @brief Get input offset voltage cancellation value. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @retval The input offset voltage cancellation value. +************************************************************************************************************/ +u32 CMP_OP_GetCancellationVaule(HT_CMP_OP_TypeDef* CMP_OPx) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + + return CMP_OPx->OFVCR; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP_OP interrupts. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param CMP_OP_INT: Specify the CMP_OP interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * - CMP_OP_INT_FALLING: + * - CMP_OP_INT_RISING: + * @param NewState new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None +************************************************************************************************************/ +void CMP_OP_IntConfig(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_INT, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CMP_OP_INT(CMP_OP_INT)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + CMP_OPx->CMPIER |= CMP_OP_INT; + } + else + { + CMP_OPx->CMPIER &= ~CMP_OP_INT; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC interrupt has occurred. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param CMP_OP_INT: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * - CMP_OP_INT_FALLING: + * - CMP_OP_INT_RISING: + * @retval SET or RESET +************************************************************************************************************/ +FlagStatus CMP_OP_GetIntStatus(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_INT) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CMP_OP_INT(CMP_OP_INT)); + + if ((CMP_OPx->CMPISR & CMP_OP_INT) != 0x0) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified CMP_OP flag has been set. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param CMP_OP_FLAG: Specify the flag to check. + * This parameter can be any combination of the following values: + * - CMP_OP_FLAG_FALLING: + * - CMP_OP_FLAG_RISING: + * @retval SET or RESET +************************************************************************************************************/ +FlagStatus CMP_OP_GetFlagStatus(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_FLAG) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CMP_OP_FLAG(CMP_OP_FLAG)); + + if ((CMP_OPx->CMPRSR & CMP_OP_FLAG) != 0x0) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + + +/*********************************************************************************************************//** + * @brief Clear the CMP_OPx interrupt pending bits. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @param CMP_OP_INT: specifies the interrupt pending bits to be cleared. + * This parameter can be any combination of the following values: + * - CMP_OP_INT_FALLING: + * - CMP_OP_INT_RISING: + * @retval None +************************************************************************************************************/ +void CMP_OP_ClearIntPendingBit(HT_CMP_OP_TypeDef* CMP_OPx, u32 CMP_OP_INT) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + Assert_Param(IS_CMP_OP_INT(CMP_OP_INT)); + + CMP_OPx->CMPICLR = CMP_OP_INT; +} + +/*********************************************************************************************************//** + * @brief Get the output status of CMP_OPx. + * @param CMP_OPx: where CMP_OPx is the selected CMP_OP from the CMP_OP peripherals, x can be 0 or 1. + * @retval SET or RESET +************************************************************************************************************/ +FlagStatus CMP_OP_GetOutputStatus(HT_CMP_OP_TypeDef* CMP_OPx) +{ + /* Check the parameters */ + Assert_Param(IS_CMP_OP_ALL_PERIPH(CMP_OPx)); + + if ((CMP_OPx->OPACR & 0x00000100) != 0x0) + { + return SET; + } + else + { + return RESET; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_crc.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_crc.c new file mode 100644 index 00000000000..6630ae3023a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_crc.c @@ -0,0 +1,190 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_crc.c + * @version $Rev:: 2787 $ + * @date $Date:: 2022-11-23 #$ + * @brief This file provides all the CRC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_crc.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CRC peripheral registers to their default reset values. + * @param HT_CRCn: where CRC is the selected CRC peripheral. + * @retval None + ************************************************************************************************************/ +void CRC_DeInit(HT_CRC_TypeDef* HT_CRCn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + if (HT_CRCn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.CRC = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the CRC peripheral according to the specified parameters in the CRC_InitStruct. + * @param HT_CRCn: Selected CRC peripheral. + * @param CRC_InitStruct: pointer to a CRC_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CRC_Init(HT_CRC_TypeDef* HT_CRCn, CRC_InitTypeDef* CRC_InitStruct) +{ + u32 uCRValue; + HT_CRCn->SDR = CRC_InitStruct->uSeed; + switch (CRC_InitStruct->Mode) + { + case CRC_CCITT_POLY: + { + uCRValue = CRC_CCITT_POLY | CRC_NORMAL_WR | CRC_NORMAL_SUM; + break; + } + case CRC_16_POLY: + { + uCRValue = CRC_16_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM; + break; + } + case CRC_32_POLY: + { + uCRValue = CRC_32_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM | CRC_CMPL_SUM; + break; + } + case CRC_USER_DEFINE: + default: + { + uCRValue = CRC_InitStruct->uCR; + break; + } + } + + HT_CRCn->CR = uCRValue; +} + +/*********************************************************************************************************//** + * @brief Get the CRC checksum from the given data + * @param HT_CRCn: Selected CRC peripheral. + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ***********************************************************************************************************/ +u32 CRC_Process(HT_CRC_TypeDef* HT_CRCn, u8 *buffer, u32 length) +{ + while (length--) + { + wb(&HT_CRCn->DR, *buffer++); // byte write + } + + return (HT_CRCn->CSR); +} + +/*********************************************************************************************************//** + * @brief Get the CRC-CCITT checksum from the given data + * @param seed: CRC initial data + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ************************************************************************************************************/ +u16 CRC_CCITT(u16 seed, u8 *buffer, u32 length) +{ + /* CRC-CCITT poly: 0x1021 */ + HT_CRC->SDR = seed; + HT_CRC->CR = CRC_CCITT_POLY | CRC_NORMAL_WR | CRC_NORMAL_SUM; + + while (length--) + { + wb(&HT_CRC->DR, *buffer++); // byte write + } + + return (u16)(HT_CRC->CSR); +} + +/*********************************************************************************************************//** + * @brief Get the CRC-16 checksum from the given data + * @param seed: CRC initial data + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ************************************************************************************************************/ +u16 CRC_16(u16 seed, u8 *buffer, u32 length) +{ + /* CRC-16 poly: 0x8005 */ + HT_CRC->SDR = seed; + HT_CRC->CR = CRC_16_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM; + + while (length--) + { + wb(&HT_CRC->DR, *buffer++); // byte write + } + + return (u16)(HT_CRC->CSR); +} + +/*********************************************************************************************************//** + * @brief Get the CRC-32 checksum from the given data + * @param seed: CRC initial data + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ************************************************************************************************************/ +u32 CRC_32(u32 seed, u8 *buffer, u32 length) +{ + /* CRC-32 poly: 0x04C11DB7 */ + HT_CRC->SDR = seed; + HT_CRC->CR = CRC_32_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM | CRC_CMPL_SUM; + + while (length--) + { + wb(&HT_CRC->DR, *buffer++); // byte write + } + + return (HT_CRC->CSR); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ebi.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ebi.c new file mode 100644 index 00000000000..55be3bc8dd0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_ebi.c @@ -0,0 +1,339 @@ +/********************************************************************************************************//** + * @file ht32f1xxxx_ebi.c + * @version $Rev:: 2788 $ + * @date $Date:: 2022-11-24 #$ + * @brief This file provides all the EBI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_ebi.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup EBI EBI + * @brief EBI driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Functions EBI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitializes the EBI peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void EBI_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.EBI = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initializes the EBI peripheral according to the specified parameters in the EBI_InitStruct. + * @param EBI_InitStruct: pointer to a EBI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void EBI_Init(EBI_InitTypeDef* EBI_InitStruct) +{ + u32 tmp; + u32 bank = EBI_InitStruct->EBI_Bank; + u32 offset = EBI_InitStruct->EBI_Bank * 0x10; + + /* Check the parameters */ + Assert_Param(IS_EBI_BANK(EBI_InitStruct->EBI_Bank)); + Assert_Param(IS_EBI_MODE(EBI_InitStruct->EBI_Mode)); + #if (LIBCFG_EBI_BYTELAND_ASYNCREADY) + Assert_Param(IS_EBI_BYTELANE(EBI_InitStruct->EBI_ByteLane)); + Assert_Param(IS_EBI_ARDY(EBI_InitStruct->EBI_AsynchronousReady)); + Assert_Param(IS_EBI_ARDY_TIMEOUT(EBI_InitStruct->EBI_ARDYTimeOut)); + Assert_Param(IS_EBI_BL_POLARITY(EBI_InitStruct->EBI_ByteLanePolarity)); + Assert_Param(IS_EBI_ARDY_POLARITY(EBI_InitStruct->EBI_ReadySignalPolarity)); + #endif + Assert_Param(IS_EBI_IDLECYCLE(EBI_InitStruct->EBI_IdleCycle)); + Assert_Param(IS_EBI_CS_POLARITY(EBI_InitStruct->EBI_ChipSelectPolarity)); + Assert_Param(IS_EBI_ALE_POLARITY(EBI_InitStruct->EBI_AddressLatchPolarity)); + Assert_Param(IS_EBI_WE_POLARITY(EBI_InitStruct->EBI_WriteEnablePolarity)); + Assert_Param(IS_EBI_RE_POLARITY(EBI_InitStruct->EBI_ReadEnablePolarity)); + Assert_Param(IS_EBI_IDLE_CYCLE_TIME(EBI_InitStruct->EBI_IdleCycleTime)); + Assert_Param(IS_EBI_ADDRESS_SETUP_TIME(EBI_InitStruct->EBI_AddressSetupTime)); + Assert_Param(IS_EBI_ADDRESS_HOLD_TIME(EBI_InitStruct->EBI_AddressHoldTime)); + Assert_Param(IS_EBI_WRITE_SETUP_TIME(EBI_InitStruct->EBI_WriteSetupTime)); + Assert_Param(IS_EBI_WRITE_STROBE_TIME(EBI_InitStruct->EBI_WriteStrobeTime)); + Assert_Param(IS_EBI_WRITE_HOLD_TIME(EBI_InitStruct->EBI_WriteHoldTime)); + Assert_Param(IS_EBI_READ_SETUP_TIME(EBI_InitStruct->EBI_ReadSetupTime)); + Assert_Param(IS_EBI_READ_STROBE_TIME(EBI_InitStruct->EBI_ReadStrobeTime)); + #if !(LIBCFG_EBI_V01) + Assert_Param(IS_EBI_PAGE_MODE(EBI_InitStruct->EBI_PageMode)); + Assert_Param(IS_EBI_PAGE_LENGTH(EBI_InitStruct->EBI_PageLength)); + Assert_Param(IS_EBI_PAGE_HIT_MODE(EBI_InitStruct->EBI_PageHitMode)); + Assert_Param(IS_EBI_PAGE_ACCESS_TIME(EBI_InitStruct->EBI_PageAccessTime)); + Assert_Param(IS_EBI_PAGE_OPEN_TIME(EBI_InitStruct->EBI_PageOpenTime)); + #endif + + + *((u32 *)((u32)&HT_EBI->ATR0 + offset)) = EBI_InitStruct->EBI_AddressSetupTime | + (EBI_InitStruct->EBI_AddressHoldTime << 8); +#if (LIBCFG_EBI_V01) +*((u32 *)((u32)&HT_EBI->RTR0 + offset)) = EBI_InitStruct->EBI_ReadSetupTime | + (EBI_InitStruct->EBI_ReadStrobeTime << 8) | + (EBI_InitStruct->EBI_ReadHoldTime << 16); +#else +*((u32 *)((u32)&HT_EBI->RTR0 + offset)) = EBI_InitStruct->EBI_ReadSetupTime | + (EBI_InitStruct->EBI_ReadStrobeTime << 8) | + (EBI_InitStruct->EBI_ReadHoldTime << 16) | + EBI_InitStruct->EBI_PageMode; +#endif + *((u32 *)((u32)&HT_EBI->WTR0 + offset)) = EBI_InitStruct->EBI_WriteSetupTime | + (EBI_InitStruct->EBI_WriteStrobeTime << 8) | + (EBI_InitStruct->EBI_WriteHoldTime << 16); + *((u32 *)((u32)&HT_EBI->PR0 + offset)) = EBI_InitStruct->EBI_ChipSelectPolarity | + (EBI_InitStruct->EBI_ReadEnablePolarity << 1) | + (EBI_InitStruct->EBI_AddressLatchPolarity << 3) | + #if (LIBCFG_EBI_BYTELAND_ASYNCREADY) + (EBI_InitStruct->EBI_ReadySignalPolarity << 4) | + (EBI_InitStruct->EBI_ByteLanePolarity << 5) | + #endif + (EBI_InitStruct->EBI_WriteEnablePolarity << 2); + + + /*------------------------- EBI Control Register Configuration -------------------------------------------*/ + tmp = (3 << (bank * 2)) | (0x00001000 << bank) | + (0x00010000 << (bank * 2)) | (0x00020000 << (bank * 2)) | + (0x01000000 << bank); + tmp = HT_EBI->CR & (~tmp); + HT_EBI->CR = (EBI_InitStruct->EBI_Mode << (bank * 2)) | + (EBI_InitStruct->EBI_IdleCycle << bank) | + #if (LIBCFG_EBI_BYTELAND_ASYNCREADY) + (EBI_InitStruct->EBI_AsynchronousReady << (bank * 2)) | + (EBI_InitStruct->EBI_ARDYTimeOut << (bank * 2)) | + (EBI_InitStruct->EBI_ByteLane << bank) | + #endif + (EBI_InitStruct->EBI_IdleCycleTime << 28) | tmp; + + #if !(LIBCFG_EBI_V01) + if (EBI_InitStruct->EBI_PageMode) + { + Assert_Param(IS_EBI_PAGE_LENGTH(EBI_InitStruct->EBI_PageLength)); + Assert_Param(IS_EBI_PAGE_HIT_MODE(EBI_InitStruct->EBI_PageHitMode)); + Assert_Param(IS_EBI_PAGE_ACCESS_TIME(EBI_InitStruct->EBI_PageAccessTime)); + Assert_Param(IS_EBI_PAGE_OPEN_TIME(EBI_InitStruct->EBI_PageOpenTime)); + + HT_EBI->PCR = EBI_InitStruct->EBI_PageLength | EBI_InitStruct->EBI_PageHitMode | + (EBI_InitStruct->EBI_PageAccessTime << 8) | (EBI_InitStruct->EBI_PageOpenTime << 16); + } + #endif +} + +/*********************************************************************************************************//** + * @brief Fills each EBI_InitStruct member with its default value. + * @param EBI_InitStruct: pointer to an EBI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void EBI_StructInit(EBI_InitTypeDef* EBI_InitStruct) +{ + /* Initialize the EBI structure parameters values */ + EBI_InitStruct->EBI_Bank = EBI_BANK_0; + EBI_InitStruct->EBI_Mode = EBI_MODE_D8A8; + #if (LIBCFG_EBI_BYTELAND_ASYNCREADY) + EBI_InitStruct->EBI_ByteLane = EBI_BYTELANE_DISABLE; + EBI_InitStruct->EBI_AsynchronousReady = EBI_ASYNCHRONOUSREADY_DISABLE; + EBI_InitStruct->EBI_ARDYTimeOut = EBI_ARDYTIMEOUT_DISABLE; + EBI_InitStruct->EBI_ByteLanePolarity = EBI_BYTELANEPOLARITY_LOW; + EBI_InitStruct->EBI_ReadySignalPolarity = EBI_READYSIGNALPOLARITY_LOW; + #endif + EBI_InitStruct->EBI_IdleCycle = EBI_IDLECYCLE_DISABLE; + EBI_InitStruct->EBI_ChipSelectPolarity = EBI_CHIPSELECTPOLARITY_LOW; + EBI_InitStruct->EBI_AddressLatchPolarity = EBI_ADDRESSLATCHPOLARITY_LOW; + EBI_InitStruct->EBI_WriteEnablePolarity = EBI_WRITEENABLEPOLARITY_LOW; + EBI_InitStruct->EBI_ReadEnablePolarity = EBI_READENABLEPOLARITY_LOW; + EBI_InitStruct->EBI_IdleCycleTime = 0xF; + EBI_InitStruct->EBI_AddressSetupTime = 0xF; + EBI_InitStruct->EBI_AddressHoldTime = 0xF; + EBI_InitStruct->EBI_WriteSetupTime = 0xF; + EBI_InitStruct->EBI_WriteStrobeTime = 0x3F; + EBI_InitStruct->EBI_WriteHoldTime = 0xF; + EBI_InitStruct->EBI_ReadSetupTime = 0xF; + EBI_InitStruct->EBI_ReadStrobeTime = 0x3F; + EBI_InitStruct->EBI_ReadHoldTime = 0xF; + #if !(LIBCFG_EBI_V01) + EBI_InitStruct->EBI_PageMode = EBI_PAGEMODE_DISABLE; + EBI_InitStruct->EBI_PageLength = EBI_PAGELENGTH_4; + EBI_InitStruct->EBI_PageHitMode = EBI_PAGEHITMODE_ADDINC; + EBI_InitStruct->EBI_PageAccessTime = 0xF; + EBI_InitStruct->EBI_PageOpenTime = 0xFF; + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the EBI peripheral. + * @param EBI_Bank: EBI Bank. + * This parameter can be one of the following values: + * @arg EBI_BANK_0 : EBI Bank 0 + * @arg EBI_BANK_1 : EBI Bank 1 + * @arg EBI_BANK_2 : EBI Bank 2 + * @arg EBI_BANK_3 : EBI Bank 3 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EBI_Cmd(u32 EBI_Bank, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EBI_BANK(EBI_Bank)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_EBI->CR |= (0x100 << EBI_Bank); + } + else + { + HT_EBI->CR &= ~(0x100 << EBI_Bank); + } +} + +#if !(LIBCFG_EBI_V01) +/*********************************************************************************************************//** + * @brief Enable or Disable the specified EBI interrupt. + * @param EBI_Int: specify the EBI interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg EBI_INT_TOUT : ARDY time out interrupt + * @arg EBI_INT_ACCDIS : Access disabled bank interrupt + * @arg EBI_INT_ACCRES : Access under software reset interrupt + * @arg EBI_INT_ALL : All EBI interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void EBI_IntConfig(u32 EBI_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EBI_INT(EBI_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_EBI->IEN |= EBI_Int; + } + else + { + HT_EBI->IEN &= (u32)~EBI_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified EBI interrupt has been occurred. + * @param EBI_IntFlag: specify the EBI interrupt to be check. + * This parameter can be one of the following values: + * @arg EBI_INT_TOUT : ARDY time out interrupt + * @arg EBI_INT_ACCERR : Access disabled bank or under software reset interrupt + * @retval SET or RESET + ***********************************************************************************************************/ +FlagStatus EBI_GetIntStatus(u32 EBI_IntFlag) +{ + u32 status = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + Assert_Param(IS_EBI_INT_FLAG(EBI_IntFlag)); + + status = HT_EBI->IF; + + if ((status & EBI_IntFlag) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Clear the specified EBI interrupt flag. + * @param EBI_IntFlag: specify the interrupt flag that is to be cleared. + * This parameter can be any combination of the following values: + * @arg EBI_INT_TOUT : ARDY time out interrupt flag + * @arg EBI_INT_ACCERR : Access disabled bank or under software reset interrupt flag + * @retval None + ***********************************************************************************************************/ +void EBI_ClearIntFlag(u32 EBI_IntFlag) +{ + /* Check the parameters */ + Assert_Param(IS_EBI_INT_FLAG(EBI_IntFlag)); + + HT_EBI->IFC = EBI_IntFlag; +} +#endif + +/*********************************************************************************************************//** + * @brief Check whether the specified EBI busy flag has been set. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EBI_GetBusyStatus(void) +{ + if (HT_EBI->SR & 0x1) + { + return SET; + } + else + { + return RESET; + } +} + +#if (LIBCFG_EBI_BYTELAND_ASYNCREADY) +/*********************************************************************************************************//** + * @brief Check whether the specified EBI ARDY flag has been set. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EBI_GetARDYStatus(void) +{ + if (HT_EBI->SR & 0x10) + { + return SET; + } + else + { + return RESET; + } +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_exti.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_exti.c new file mode 100644 index 00000000000..de263a613a6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_exti.c @@ -0,0 +1,516 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_exti.c + * @version $Rev:: 2873 $ + * @date $Date:: 2023-02-23 #$ + * @brief This file provides all the EXTI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_exti.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Define EXTI private definitions + * @{ + */ +/* EXTI EVWUPIEN mask */ +#define WAKUPCR_EVWUPIEN_SET ((u32)0x80000000) +#define WAKUPCR_EVWUPIEN_RESET ((u32)0x7FFFFFFF) + +const IRQn_Type gEXTIn_IRQn[16] = { + EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, + EXTI4_IRQn, EXTI5_IRQn, EXTI6_IRQn, EXTI7_IRQn, + EXTI8_IRQn, EXTI9_IRQn, EXTI10_IRQn, EXTI11_IRQn, + EXTI12_IRQn, EXTI13_IRQn, EXTI14_IRQn, EXTI15_IRQn, +}; + +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the EXTI peripheral registers. + * @param EXTI_Channel: can be 0, 1 to 15 to select the EXTI Channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval None + ************************************************************************************************************/ +void EXTI_DeInit(u32 EXTI_Channel) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + tmp = 1 << EXTI_Channel; + + *((u32 *) HT_EXTI + EXTI_Channel) = 0x0; + HT_EXTI->CR &= (~tmp); + HT_EXTI->EDGEFLGR = tmp; + HT_EXTI->EDGESR = tmp; + HT_EXTI->SSCR &= (~tmp); + HT_EXTI->WAKUPCR &= (~tmp); + HT_EXTI->WAKUPPOLR &= (~tmp); + HT_EXTI->WAKUPFLG = tmp; +} + +/*********************************************************************************************************//** + * @brief Initialize the EXTI peripheral. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + u32 regval; + + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_InitStruct->EXTI_Channel)); + Assert_Param(IS_EXTI_DEBOUNCE_TYPE(EXTI_InitStruct->EXTI_Debounce)); + Assert_Param(IS_EXTI_DEBOUNCE_SIZE(EXTI_InitStruct->EXTI_DebounceCnt)); + Assert_Param(IS_EXTI_INT_TYPE(EXTI_InitStruct->EXTI_IntType)); + + /* Set EXTI interrupt configuration */ + regval = (EXTI_InitStruct->EXTI_Debounce << 31) | (EXTI_InitStruct->EXTI_IntType << 28) | (EXTI_InitStruct->EXTI_DebounceCnt); + *((u32 *) HT_EXTI + EXTI_InitStruct->EXTI_Channel) = regval; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified EXTI channelx interrupts. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_IntConfig(u32 EXTI_Channel, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Configure EXTI interrupt */ + if (NewState == ENABLE) + { + HT_EXTI->CR |= (1 << EXTI_Channel); + } + else + { + HT_EXTI->CR &= ~(1 << EXTI_Channel); + } +} + +/*********************************************************************************************************//** + * @brief Configure the EXTI channelx event wakeup function. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param EXTI_WakeUpType: determines the type of signal to trigger EXTI interrupt. + * This parameter can be one of the following values: + * @arg EXTI_WAKEUP_HIGH_LEVEL + * @arg EXTI_WAKEUP_LOW_LEVEL + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_WakeupEventConfig(u32 EXTI_Channel, u8 EXTI_WakeUpType, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_EXTI_WAKEUP_TYPE(EXTI_WakeUpType)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == ENABLE) + { + if (EXTI_WakeUpType == EXTI_WAKEUP_HIGH_LEVEL) + { + HT_EXTI->WAKUPPOLR &= ~(1 << EXTI_Channel); + } + else + { + HT_EXTI->WAKUPPOLR |= (1 << EXTI_Channel); + } + + HT_EXTI->WAKUPCR |= (1 << EXTI_Channel); + } + else + { + HT_EXTI->WAKUPCR &= ~(1 << EXTI_Channel); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the EXTI channelx event wakeup interrupt. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_WakeupEventIntConfig(ControlStatus NewState) +{ + if (NewState == ENABLE) + { + /* Set EVWUPIEN bit */ + HT_EXTI->WAKUPCR |= WAKUPCR_EVWUPIEN_SET; + } + else + { + /* Clear EVWUPIEN bit */ + HT_EXTI->WAKUPCR &= WAKUPCR_EVWUPIEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified EXTI channelx edge flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval None + ************************************************************************************************************/ +void EXTI_ClearEdgeFlag(u32 EXTI_Channel) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + tmp = 1 << EXTI_Channel; + + /* Write 1 to clear both edge detection flag */ + HT_EXTI->EDGEFLGR = tmp; + /* Write 1 to clear positive edge detection flag */ + HT_EXTI->EDGESR = tmp; +} + +/*********************************************************************************************************//** + * @brief Clear the specified EXTI channelx wakeup flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval None + ************************************************************************************************************/ +void EXTI_ClearWakeupFlag(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + /* Write 1 to clear wake up flag */ + HT_EXTI->WAKUPFLG = 1 << EXTI_Channel; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx edge flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetEdgeFlag(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + return ((HT_EXTI->EDGEFLGR & (1UL << EXTI_Channel)) ? SET : RESET); +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx edge status. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param EXTI_Edge: can be status of edge that user want to monitor. + * This parameter can be one of the following values: + * @arg EXTI_EDGE_POSITIVE + * @arg EXTI_EDGE_NEGATIVE + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetEdgeStatus(u32 EXTI_Channel, u32 EXTI_Edge) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_EXTI_EDGE(EXTI_Edge)); + + if (HT_EXTI->EDGEFLGR & (1UL << EXTI_Channel)) + { + if (((HT_EXTI->EDGESR >> EXTI_Channel) & 1UL) ^ EXTI_Edge) + { + return SET; + } + else + { + return RESET; + } + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx wakeup flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetWakeupFlagStatus(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + if (HT_EXTI->WAKUPFLG & (1 << EXTI_Channel)) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Activate or Deactivate an EXTI channelx interrupt by software. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_SWIntCmd(u32 EXTI_Channel, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == ENABLE) + { + HT_EXTI->SSCR = 1 << EXTI_Channel; + } + else + { + HT_EXTI->SSCR &= ~(1 << EXTI_Channel); + } +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx software command register bit. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetSWCmdStatus(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + if (HT_EXTI->SSCR & (1 << EXTI_Channel)) + { + return SET; + } + else + { + return RESET; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_flash.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_flash.c new file mode 100644 index 00000000000..301920da1d2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_flash.c @@ -0,0 +1,603 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_flash.c + * @version $Rev:: 2972 $ + * @date $Date:: 2023-10-28 #$ + * @brief This file provides all the FLASH firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_flash.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Define FLASH private definitions + * @{ + */ + +/* Delay definition */ +#define FLASH_TIMEOUT (0x000FFFFF) + +/* FLASH OCMR */ +#define FLASH_CMD_STADNBY (0x00000000) +#define FLASH_CMD_PROGRAM (0x00000004) +#define FLASH_CMD_PAGEERASE (0x00000008) +#define FLASH_CMD_MASSERASE (0x0000000A) + +/* FLASH OPCR */ +#define FLASH_READY (0x6UL << 1) +#define FLASH_SEND_MAIN (0x00000014) + +/* FLASH CFCR */ +#define CFCR_WAIT_MASK (0xFFFFFFF8) + +#define FLASH_PREFETCHBUF_ON (0x00000010) +#define FLASH_PREFETCHBUF_OFF (0xFFFFFFEF) + +#define FLASH_BRANCHCACHE_ON (0x00001000) +#define FLASH_BRANCHCACHE_OFF (0xFFFFEFFF) + +#define FLASH_DCODECACHE_ON (0xFFFFFF7F) +#define FLASH_DCODECACHE_OFF (0x00000080) + +#define FLASH_CFCR_MASK (0xFFFFEFE8) +#define FLASH_PREFETCHBUF_AND_BRANCHCACHE_ON (0x00001010) +#define FLASH_PREFETCHBUF_AND_BRANCHCACHE_OFF (0xFFFFEFEF) + +#if (LIBCFG_FLASH_HALFCYCYLE) +#define FLASH_HALFCYCLE_ON (0x00008000) +#define FLASH_HALFCYCLE_OFF (0xFFFF7FFF) +#endif +#if (LIBCFG_FLASH_ZWPWESAVING) +#define FLASH_ZWPWRSAVING_ON (0x00010000) +#define FLASH_ZWPWRSAVING_OFF (0xFFFEFFFF) +#endif +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macro FLASH private macros + * @{ + */ + +/** + * @brief Check parameter of the FLASH wait state. + */ + +#if (LIBCFG_FMC_WAIT_STATE_3) +#define IS_WAIT_STATE3(x) (x == FLASH_WAITSTATE_3) +#else +#define IS_WAIT_STATE3(x) (0) +#endif + +#define IS_FLASH_WAITSTATE(WAIT) ((WAIT == FLASH_WAITSTATE_0) || \ + (WAIT == FLASH_WAITSTATE_1) || \ + (WAIT == FLASH_WAITSTATE_2) || \ + (IS_WAIT_STATE3(WAIT))) + +/** + * @brief Check parameter of the FLASH vector mapping. + */ +#define IS_FLASH_VECTOR_MODE(MODE) ((MODE == FLASH_BOOT_LOADER) || \ + (MODE == FLASH_BOOT_SRAM) || \ + (MODE == FLASH_BOOT_MAIN)) +/** + * @brief Check parameter of the FLASH address. + */ +#define IS_FLASH_ADDRESS(ADDRESS) (ADDRESS < 0x20000000) /* Code 0.5GB Area */ + +/** + * @brief Check parameter of the FLASH interrupt status. + */ +#define IS_FLASH_WC_FLAG(FLAG) ((FLAG & 0x0000001F) != 0) + +/** + * @brief Check parameter of the FLASH interrupt flag. + */ +#define IS_FLASH_FLAG(FLAG) ((FLAG & 0x0003001F) != 0) + +/** + * @brief Check parameter of the FLASH interrupt. + */ +#define IS_FLASH_INT(IT) ((IT & 0x0000001F) != 0) + +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Configure the FLASH wait state. + * @param FLASH_WAITSTATE_n: Setting of FLASH wait state. + * This parameter can be one of the following values: + * @arg \ref FLASH_WAITSTATE_0 : zero wait state + * @arg \ref FLASH_WAITSTATE_1 : one wait state + * @arg \ref FLASH_WAITSTATE_2 : two wait state + * @arg \ref FLASH_WAITSTATE_3 : three wait state (For HT32F1xxxx only) + * @retval None + ************************************************************************************************************/ +void FLASH_SetWaitState(u32 FLASH_WAITSTATE_n) +{ + u32 uCFCR; + /* Check the parameters */ + Assert_Param(IS_FLASH_WAITSTATE(FLASH_WAITSTATE_n)); + + /* !!! NOTICE !!! + Before changing wait state, both Pre-fetch function and Branch Cache function must be disabled. + */ + uCFCR = HT_FLASH->CFCR; /* Backup previous settings. */ + + /* Disable Pre-fetch function and Branch Cache. */ + HT_FLASH->CFCR = uCFCR & FLASH_PREFETCHBUF_AND_BRANCHCACHE_OFF; + /* Change wait state. */ + HT_FLASH->CFCR = (uCFCR & FLASH_CFCR_MASK) | FLASH_WAITSTATE_n; + /* Restore previous settings. */ + HT_FLASH->CFCR |= uCFCR & (FLASH_PREFETCHBUF_AND_BRANCHCACHE_ON); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable FLASH pre-fetch buffer. + * @param NewState: This parameter can be ENABLE or DISABLE + * @retval None + ************************************************************************************************************/ +void FLASH_PrefetchBufferCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_FLASH->CFCR |= FLASH_PREFETCHBUF_ON; + } + else + { + HT_FLASH->CFCR &= FLASH_PREFETCHBUF_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable FLASH DCODE cache mode. + * @param NewState: This parameter can be ENABLE or DISABLE + * @retval None + ************************************************************************************************************/ +void FLASH_DcodeCacheCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_FLASH->CFCR &= FLASH_DCODECACHE_ON; + } + else + { + HT_FLASH->CFCR |= FLASH_DCODECACHE_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable FLASH branch cache. + * @param NewState: This parameter can be ENABLE or DISABLE + * @retval None + ************************************************************************************************************/ +void FLASH_BranchCacheCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_FLASH->CFCR |= FLASH_BRANCHCACHE_ON; + } + else + { + HT_FLASH->CFCR &= FLASH_BRANCHCACHE_OFF; + } +} + +#if (LIBCFG_FLASH_HALFCYCYLE) +/*********************************************************************************************************//** + * @brief Enable or Disable FLASH half cycle access. + * @param NewState: new state of the FLASH half cycle access. + * This parameter can be: ENABLE or DISABLE + * @retval ERROR or SUCCESS + ************************************************************************************************************/ +ErrStatus FLASH_FlashHalfCycleCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if ((HT_FLASH->CFCR & ~CFCR_WAIT_MASK) == FLASH_WAITSTATE_0) + { + if (NewState != DISABLE) + { + HT_FLASH->CFCR |= FLASH_HALFCYCLE_ON; + } + else + { + HT_FLASH->CFCR &= FLASH_HALFCYCLE_OFF; + } + + return SUCCESS; + } + + return ERROR; +} +#endif + +#if (LIBCFG_FLASH_ZWPWESAVING) +/*********************************************************************************************************//** + * @brief Enable or Disable FLASH zero wait state power saving. + * @param NewState: new state of the FLASH zero wait state power saving. + * This parameter can be: ENABLE or DISABLE + * @retval ERROR or SUCCESS + ************************************************************************************************************/ +ErrStatus FLASH_FlashZwPwrSavingCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if ((HT_FLASH->CFCR & ~CFCR_WAIT_MASK) == FLASH_WAITSTATE_0) + { + if (NewState != DISABLE) + { + HT_FLASH->CFCR |= FLASH_ZWPWRSAVING_ON; + } + else + { + HT_FLASH->CFCR &= FLASH_ZWPWRSAVING_OFF; + } + + return SUCCESS; + } + + return ERROR; +} +#endif + +/*********************************************************************************************************//** + * @brief Set vector remapping mode. + * @param FLASH_BOOT_x: Booting mode. + * This parameter can be one of the following values: + * @arg \ref FLASH_BOOT_LOADER : Boot loader mode + * @arg \ref FLASH_BOOT_SRAM : SRAM booting mode + * @arg \ref FLASH_BOOT_MAIN : Main FLASH mode + * @retval None + ************************************************************************************************************/ +void FLASH_SetRemappingMode(FLASH_Vector FLASH_BOOT_x) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_VECTOR_MODE(FLASH_BOOT_x)); + + HT_FLASH->VMCR = FLASH_BOOT_x; +} + +/*********************************************************************************************************//** + * @brief Erase a specific FLASH page. + * @param PageAddress: Address of the erased page. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * - \ref FLASH_ERR_ADDR_OUT_OF_RANGE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_ErasePage(u32 PageAddress) +{ + FLASH_State status; + #if (AUTO_CMDVERIFY == 1) + u32 uData; + u32 uAddress; + PageAddress &= (~(FLASH_PAGE_SIZE - 1)); + uAddress = PageAddress; + #endif + + /* Check the parameters */ + Assert_Param(IS_FLASH_ADDRESS(PageAddress)); + + #if (AUTO_CMDVERIFY == 1) + do + { + if (uAddress - PageAddress == FLASH_PAGE_SIZE) + { + return FLASH_COMPLETE; + } + + uData = rw(uAddress); + uAddress += 4; + } while (uData == 0xFFFFFFFF); + #endif + + HT_FLASH->TADR = PageAddress; + HT_FLASH->OCMR = FLASH_CMD_PAGEERASE; + + #if (AUTO_CMDVERIFY == 1) + do { + #endif + status = FLASH_WaitForOperationEnd(); + #if (AUTO_CMDVERIFY == 1) + if (status != FLASH_COMPLETE) + break; + } while (rw(uAddress - 4) != 0xFFFFFFFF); + #endif + + return status; +} + +/*********************************************************************************************************//** + * @brief Erase FLASH Option Byte page. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_EraseOptionByte(void) +{ + return FLASH_ErasePage(OPTION_BYTE_BASE); +} + +/*********************************************************************************************************//** + * @brief Erase the entire FLASH. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_MassErase(void) +{ + HT_FLASH->OCMR = FLASH_CMD_MASSERASE; + + return FLASH_WaitForOperationEnd(); +} + +/*********************************************************************************************************//** + * @brief Program one word data. + * @param Address: The specific FLASH address to be programmed. + * @param Data: The specific FLASH data to be programmed. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * - \ref FLASH_ERR_ADDR_OUT_OF_RANGE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_ProgramWordData(u32 Address, u32 Data) +{ + FLASH_State status; + + /* Check the parameters */ + Assert_Param(IS_FLASH_ADDRESS(Address)); + + HT_FLASH->TADR = Address; + HT_FLASH->WRDR = Data; + HT_FLASH->OCMR = FLASH_CMD_PROGRAM; + + if (Data == 0xFFFFFFFF) + { + return FLASH_COMPLETE; + } + + #if (AUTO_CMDVERIFY == 1) + do { + #endif + status = FLASH_WaitForOperationEnd(); + #if (AUTO_CMDVERIFY == 1) + if (status != FLASH_COMPLETE) + break; + } while (rw(Address) == 0xFFFFFFFF); + #endif + + return status; +} + +/*********************************************************************************************************//** + * @brief Program FLASH Option Byte page. + * @param Option: Struct pointer of Option Bytes. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_ProgramOptionByte(FLASH_OptionByte *Option) +{ + s32 i; + u32 CP = ~(Option->MainSecurity | Option->OptionProtect << 1); + u32 checksum = 0; + + for (i = 3; i >= 0; i--) + { + FLASH_ProgramWordData(OB_PP0 + i * 4, ~(Option->WriteProtect[i])); + checksum += ~(Option->WriteProtect[i]); + } + + FLASH_ProgramWordData(OB_CP, CP); + checksum += CP; + + FLASH_ProgramWordData(OB_CHECKSUM, checksum); + + return FLASH_COMPLETE; +} + +/*********************************************************************************************************//** + * @brief Return security status of the FLASH. + * @param Option: Struct pointer of Option Bytes. + * @retval None + ************************************************************************************************************/ +void FLASH_GetOptionByteStatus(FLASH_OptionByte *Option) +{ + s32 i; + + for (i = 3; i >= 0; i--) + { + Option->WriteProtect[i] = ~HT_FLASH->PPSR[i]; + } + + Option->MainSecurity = !(HT_FLASH->CPSR & 1); + Option->OptionProtect = !((HT_FLASH->CPSR >> 1) & 1); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specific FLASH interrupts. + * @param FLASH_INT_x: The specific FLASH interrupt. + * This parameter can be any combination (|) of the following values: + * @arg \ref FLASH_INT_ORFIEN + * @arg \ref FLASH_INT_ITADIEN + * @arg \ref FLASH_INT_OBEIEN + * @arg \ref FLASH_INT_IOCMIEN + * @arg \ref FLASH_INT_OREIEN + * @arg \ref FLASH_INT_ALL + * @param Cmd: This parameter can be ENABLE or DISABLE + * @retval None + ************************************************************************************************************/ +void FLASH_IntConfig(u32 FLASH_INT_x, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_INT(FLASH_INT_x)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + HT_FLASH->OIER |= FLASH_INT_x; + } + else + { + HT_FLASH->OIER &= ~FLASH_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Return flag status of the FLASH interrupt. + * @param FLASH_FLAG_x: Flag of the FLASH interrupt. + * This parameter can be any combination (|) of the following values: + * @arg \ref FLASH_FLAG_OREF + * @arg \ref FLASH_FLAG_IOCMF + * @arg \ref FLASH_FLAG_OBEF + * @arg \ref FLASH_FLAG_ITADF + * @arg \ref FLASH_FLAG_ORFF + * @arg \ref FLASH_FLAG_PPEF + * @arg \ref FLASH_FLAG_RORFF + * @retval FlagStatus + * - \ref SET + * - \ref RESET + ************************************************************************************************************/ +FlagStatus FLASH_GetIntStatus(u32 FLASH_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_FLAG(FLASH_FLAG_x)); + + if ((HT_FLASH->OISR & FLASH_FLAG_x) != (u32)RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear specific interrupt flags of FLASH. + * @param FLASH_FLAG_x: interrupt flag of FLASH. + * This parameter can be any combination (|) of the following values: + * @arg \ref FLASH_FLAG_OREF + * @arg \ref FLASH_FLAG_IOCMF + * @arg \ref FLASH_FLAG_OBEF + * @arg \ref FLASH_FLAG_ITADF + * @arg \ref FLASH_FLAG_ORFF + * @retval None + ************************************************************************************************************/ +void FLASH_ClearIntFlag(u32 FLASH_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_WC_FLAG(FLASH_FLAG_x)); + + HT_FLASH->OISR = FLASH_FLAG_x; +} + +/*********************************************************************************************************//** + * @brief Wait untill the FLASH operation has finished or time-out has occurred. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * - \ref FLASH_ERR_ADDR_OUT_OF_RANGE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_WaitForOperationEnd(void) +{ + u32 Timeout = FLASH_TIMEOUT; + u32 Status; + + HT_FLASH->OIER |= (FLASH_INT_ITADIEN); + HT_FLASH->OPCR = FLASH_SEND_MAIN; + + /* Waits till the FLASH operation has finished or time-out has occurred */ + while (Timeout--) + { + if ((HT_FLASH->OPCR & FLASH_READY) == FLASH_READY) + { + break; + } + } + Status = HT_FLASH->OISR; + HT_FLASH->OISR &= ~(FLASH_INT_ITADIEN); + + if (Status & FLASH_FLAG_PPEF) + { + return FLASH_ERR_WRITE_PROTECTED; + } + if (Status & FLASH_FLAG_ITADF) + { + return FLASH_ERR_ADDR_OUT_OF_RANGE; + } + if (Timeout == 0) + { + return FLASH_TIME_OUT; + } + + return FLASH_COMPLETE; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_gpio.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_gpio.c new file mode 100644 index 00000000000..572d61055c7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_gpio.c @@ -0,0 +1,730 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_gpio.c + * @version $Rev:: 2797 $ + * @date $Date:: 2022-11-28 #$ + * @brief This file provides all the GPIO and AFIO firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_gpio.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO driver modules + * @{ + */ + + +/* Private function prototypes -----------------------------------------------------------------------------*/ +u32 _GPIO_ClockControl(HT_GPIO_TypeDef* HT_GPIOx, ControlStatus Cmd); +u32 _AFIO_ClockControl(ControlStatus Cmd); + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macro GPIO private macros + * @{ + */ +#if (AUTO_CK_CONTROL == 1) + #define GPIO_CK_ST u32 isAlreadyOn + #define GPIO_CK_ON() (isAlreadyOn = _GPIO_ClockControl(HT_GPIOx, ENABLE)) + #define GPIO_CK_OFF() if (isAlreadyOn == FALSE) _GPIO_ClockControl(HT_GPIOx, DISABLE) + #define AFIO_CK_ST u32 isAlreadyOn + #define AFIO_CK_ON() (isAlreadyOn = _AFIO_ClockControl(ENABLE)) + #define AFIO_CK_OFF() if (isAlreadyOn == FALSE) _AFIO_ClockControl(DISABLE) +#else + #define GPIO_CK_ST + #define GPIO_CK_ON(...) + #define GPIO_CK_OFF(...) + #define AFIO_CK_ST + #define AFIO_CK_ON(...) + #define AFIO_CK_OFF(...) +#endif +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions GPIO exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitializes the GPIO peripheral registers to their default reset values. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval None + ************************************************************************************************************/ +void GPIO_DeInit(HT_GPIO_TypeDef* HT_GPIOx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + if (HT_GPIOx == HT_GPIOA) + { + RSTCUReset.Bit.PA = 1; + } + else if (HT_GPIOx == HT_GPIOB) + { + RSTCUReset.Bit.PB = 1; + } + else if (HT_GPIOx == HT_GPIOC) + { + RSTCUReset.Bit.PC = 1; + } + else if (HT_GPIOx == HT_GPIOD) + { + RSTCUReset.Bit.PD = 1; + } + #if (LIBCFG_GPIOE) + else if (HT_GPIOx == HT_GPIOE) + { + RSTCUReset.Bit.PE = 1; + } + #endif + #if (LIBCFG_GPIOF) + else if (HT_GPIOx == HT_GPIOF) + { + RSTCUReset.Bit.PF = 1; + } + #endif + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure the direction of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param GPIO_DIR_INorOUT: + * This parameter can be one of below: + * @arg GPIO_DIR_IN : The pins are input mode + * @arg GPIO_DIR_OUT : The pins are output mode + * @retval None + ************************************************************************************************************/ +void GPIO_DirectionConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DIR_Enum GPIO_DIR_INorOUT) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_GPIO_DIR(GPIO_DIR_INorOUT)); + + GPIO_CK_ON(); + + if (GPIO_DIR_INorOUT != GPIO_DIR_IN) + HT_GPIOx->DIRCR |= GPIO_PIN_nBITMAP; + else + HT_GPIOx->DIRCR &= ~GPIO_PIN_nBITMAP; + + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Configure the pull resistor of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param GPIO_PR_x: Selection of Pull resistor. + * This parameter can be one of below: + * @arg GPIO_PR_UP : The pins with internal pull-up resistor + * @arg GPIO_PR_DOWN : The pins with internal pull-down resistor + * @arg GPIO_PR_DISABLE : The pins without pull resistor + * @retval None + ************************************************************************************************************/ +void GPIO_PullResistorConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_PR_Enum GPIO_PR_x) +{ + u32 temp_up, temp_down; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_GPIO_PR(GPIO_PR_x)); + + GPIO_CK_ON(); + temp_up = HT_GPIOx->PUR; + temp_down = HT_GPIOx->PDR; + + temp_up &= ~GPIO_PIN_nBITMAP; + temp_down &= ~GPIO_PIN_nBITMAP; + + switch (GPIO_PR_x) + { + case GPIO_PR_UP: + temp_up |= GPIO_PIN_nBITMAP; + break; + case GPIO_PR_DOWN: + temp_down |= GPIO_PIN_nBITMAP; + break; + case GPIO_PR_DISABLE: + break; + default: + break; + } + + HT_GPIOx->PUR = temp_up; + HT_GPIOx->PDR = temp_down; + + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the input control of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void GPIO_InputConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + GPIO_CK_ON(); + if (Cmd != DISABLE) + HT_GPIOx->INER |= GPIO_PIN_nBITMAP; + else + HT_GPIOx->INER &= ~GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Select the driving current of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param GPIO_DV_nMA: + * This parameter can be one of below: + * @arg GPIO_DV_4MA : Select output driving current as 4 mA + * @arg GPIO_DV_8MA : Select output driving current as 8 mA + * @arg GPIO_DV_12MA : Select output driving current as 12 mA (For HT32F1xxxx only) + * @arg GPIO_DV_16MA : Select output driving current as 16 mA (For HT32F1xxxx only) + * @retval None + ************************************************************************************************************/ +void GPIO_DriveConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DV_Enum GPIO_DV_nMA) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_GPIO_DV(GPIO_DV_nMA)); + + GPIO_CK_ON(); +#if (LIBCFG_GPIO_DV_4_8MA_ONLY) + if (GPIO_DV_nMA != GPIO_DV_4MA) + HT_GPIOx->DRVR |= GPIO_PIN_nBITMAP; + else + HT_GPIOx->DRVR &= ~GPIO_PIN_nBITMAP; +#else +{ + u8 index = 0, temp = 0; + u32 CurrentMode = 0, PinPosition = 0; + for (index = 0; index < 16; index++) + { + if ((GPIO_PIN_nBITMAP & 0x0001) == 1) + { + temp = index << 1; + CurrentMode |= ((u32) GPIO_DV_nMA << temp); + PinPosition |= ((u32) 0x03 << temp); + } + GPIO_PIN_nBITMAP >>= 1; + } + + HT_GPIOx->DRVR &= ~PinPosition; + HT_GPIOx->DRVR |= CurrentMode; +} +#endif + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the open drain function of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void GPIO_OpenDrainConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + GPIO_CK_ON(); + if (Cmd != DISABLE) + HT_GPIOx->ODR |= GPIO_PIN_nBITMAP; + else + HT_GPIOx->ODR &= ~GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Get the input data of specified port pin. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_n: This parameter can be GPIO_PIN_x. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus GPIO_ReadInBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n) +{ + FlagStatus result; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->DINR & GPIO_PIN_n) != RESET) + result = SET; + else + result = RESET; + + GPIO_CK_OFF(); + return result; +} + +/*********************************************************************************************************//** + * @brief Get the input data of specified GPIO port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval The value of input data register. + ************************************************************************************************************/ +u16 GPIO_ReadInData(HT_GPIO_TypeDef* HT_GPIOx) +{ + u16 uValue; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + uValue = (u16)HT_GPIOx->DINR; + GPIO_CK_OFF(); + return (uValue); +} + +/*********************************************************************************************************//** + * @brief Get the output data of specified port pin. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_n: This parameter can be GPIO_PIN_x. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus GPIO_ReadOutBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n) +{ + FlagStatus result; + GPIO_CK_ST; + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->DOUTR & GPIO_PIN_n) != RESET) + result = SET; + else + result = RESET; + + GPIO_CK_OFF(); + return result; +} + +/*********************************************************************************************************//** + * @brief Get the output data of specified GPIO port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval The value of output data register. + ************************************************************************************************************/ +u16 GPIO_ReadOutData(HT_GPIO_TypeDef* HT_GPIOx) +{ + u32 uValue; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + uValue = (u16)HT_GPIOx->DOUTR; + GPIO_CK_OFF(); + return uValue; +} + +/*********************************************************************************************************//** + * @brief Set the selected port bits of output data. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bit to be set. + * This parameter can be any combination of GPIO_PIN_x. + * @retval None + ************************************************************************************************************/ +void GPIO_SetOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->SRR = GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Clear the selected port bits of output data. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bit to be clear. + * This parameter can be any combination of GPIO_PIN_x. + * @retval None + ************************************************************************************************************/ +void GPIO_ClearOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->RR = GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Set or Clear the selected port bits of data. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bits. + * This parameter can be any combination of GPIO_PIN_x. + * @param Status: This parameter can be SET or RESET. + * @retval None + ************************************************************************************************************/ +void GPIO_WriteOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, FlagStatus Status) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if (Status != RESET) + HT_GPIOx->SRR = GPIO_PIN_nBITMAP; + else + HT_GPIOx->RR = GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Put data to the specified GPIO data port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param Data: Specify the data to be written to the port data register. + * @retval None + ************************************************************************************************************/ +void GPIO_WriteOutData(HT_GPIO_TypeDef* HT_GPIOx, u16 Data) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->DOUTR = Data; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Lock configuration of GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bits. + * This parameter can be any combination of GPIO_PIN_x. + * @retval None + ************************************************************************************************************/ +void GPIO_PinLock(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->LOCKR = (u32)0x5FA00000 | GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Get the lock state of specified GPIO port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool GPIO_IsPortLocked(HT_GPIO_TypeDef* HT_GPIOx) +{ + bool result; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->LOCKR >> 16) == 0) + result = FALSE; + else + result = TRUE; + GPIO_CK_OFF(); + return result; +} + +/*********************************************************************************************************//** + * @brief Get the lock state of specified GPIO port pin. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_n: This parameter can be GPIO_PIN_x. + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool GPIO_IsPinLocked(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n) +{ + bool result; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->LOCKR & GPIO_PIN_n) == 0) + result = FALSE; + else + result = TRUE; + GPIO_CK_OFF(); + return result; +} + +/*********************************************************************************************************//** + * @brief Disable DEBUG port to prevent unexpected security lock. + * @retval None + ************************************************************************************************************/ +void GPIO_DisableDebugPort(void) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.PA = 1; + CKCUClock.Bit.AFIO = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + AFIO_GPxConfig(GPIO_PA, GPIO_PIN_13, AFIO_FUN_GPIO); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_13, GPIO_PR_DOWN); + GPIO_InputConfig(HT_GPIOA, GPIO_PIN_13, DISABLE); + + #if 0 + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + AFIO_GPxConfig(GPIO_PA, GPIO_PIN_12, AFIO_FUN_GPIO); + #endif +} + +/*********************************************************************************************************//** + * @brief Convert HT_GPIOx to GPIO_Px + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval GPIO_Px: GPIO ID + ************************************************************************************************************/ +u32 GPIO_GetID(HT_GPIO_TypeDef* HT_GPIOx) +{ + // Convert 0x400B0000 ~ 0x400C6000 to 0 ~ 11 + u32 GPIO_Px = (((u32)HT_GPIOx) >> (12 + 1)) & 0x7F; + GPIO_Px -= 0x58; // 0xB0000 >> 13 = 0x58 + + return GPIO_Px; +} + +/*********************************************************************************************************//** + * @brief Deinitialize the AFIO peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void AFIO_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.AFIO = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure alternated mode of GPIO with specified pins. + * @param GPIO_Px: GPIO_PA ~ GPIO_PE. + * @param AFIO_PIN_n: This parameter can be any combination of AFIO_PIN_x. + * @param AFIO_MODE_n: This parameter can be one of the following values: + * @arg AFIO_MODE_DEFAULT : The default I/O function + * @arg AFIO_MODE_1 : Alternated mode 1 + * @arg AFIO_MODE_2 : Alternated mode 2 + * @arg AFIO_MODE_3 : Alternated mode 3 + * @arg AFIO_MODE_4 : Alternated mode 4 + * @arg AFIO_MODE_5 : Alternated mode 5 + * @arg AFIO_MODE_6 : Alternated mode 6 + * @arg AFIO_MODE_7 : Alternated mode 7 + * @arg AFIO_MODE_8 : Alternated mode 8 + * @arg AFIO_MODE_9 : Alternated mode 9 + * @arg AFIO_MODE_10 : Alternated mode 10 + * @arg AFIO_MODE_11 : Alternated mode 11 + * @arg AFIO_MODE_12 : Alternated mode 12 + * @arg AFIO_MODE_13 : Alternated mode 13 + * @arg AFIO_MODE_14 : Alternated mode 14 + * @arg AFIO_MODE_15 : Alternated mode 15 + * @retval None + ************************************************************************************************************/ +void AFIO_GPxConfig(u32 GPIO_Px, u32 AFIO_PIN_n, AFIO_MODE_Enum AFIO_MODE_n) +{ + vu32* pGPxCFGR = ((vu32*)&HT_AFIO->GPACFGR[0]) + GPIO_Px * 2; + u32 index = 0; + u32 Mask = 0, PinMode = 0; + s32 i; + AFIO_CK_ST; + + Assert_Param(IS_AFIO_MODE(AFIO_MODE_n)); + AFIO_CK_ON(); + + for (i = 0; i <= 8; i += 8) + { + Mask = 0; + PinMode = 0; + if (AFIO_PIN_n & (0x00FF << i)) + { + for (index = 0; index < 8; index++) + { + if ((AFIO_PIN_n >> index) & (0x0001 << i)) + { + Mask |= (0xF << (index * 4)); + PinMode |= (AFIO_MODE_n << (index * 4)); + } + } + *pGPxCFGR = (*pGPxCFGR & (~Mask)) | PinMode; + } + pGPxCFGR++; + } + + AFIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Select the GPIO pin to be used as EXTI channel. + * @param GPIO_PIN_NUM_n: Specify the GPIO pin number to be configured. + * @param GPIO_Px: GPIO_PA ~ GPIO_PF. + * @retval None + ************************************************************************************************************/ +void AFIO_EXTISourceConfig(u32 GPIO_PIN_NUM_n, u32 GPIO_Px) +{ + u8 index = 0; + u32 tmp = 0; + AFIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO_PORT(GPIO_Px)); + Assert_Param(IS_GPIO_PIN_NUM(GPIO_PIN_NUM_n)); + + AFIO_CK_ON(); + + if (GPIO_PIN_NUM_n > 7) + { + index = 1; + GPIO_PIN_NUM_n -= 8; + } + + tmp = HT_AFIO->ESSR[index]; + tmp &= ~((u32)0x0F << (GPIO_PIN_NUM_n * 4)); + tmp |= (u32)GPIO_Px << (GPIO_PIN_NUM_n * 4); + HT_AFIO->ESSR[index] = tmp; + AFIO_CK_OFF(); +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Turn on/Turn off specify GPIO clock. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval TRUE or FALSE (TRUE: already turn on, FALSE, Turn on by this call) + ***********************************************************************************************************/ +u32 _GPIO_ClockControl(HT_GPIO_TypeDef* HT_GPIOx, ControlStatus Cmd) +{ + u32 PxENStatus; + /*--------------------------------------------------------------------------------------------------------*/ + /* ((0x400Bx000 & 0x0000F000) >> 12 ) / 2 + 16 = */ + /* (0x0 ~ 0x4) + 16 = 16 ~ 20 for AHBCCR PAEN ~ PEEN bit offset */ + /*--------------------------------------------------------------------------------------------------------*/ + u32 offset = ((((u32)HT_GPIOx) & 0x0000F000) >> 12) / 2 + 16; + + PxENStatus = HT_CKCU->AHBCCR & (1 << offset); + + if (PxENStatus != 0) + { + if (Cmd == DISABLE) + { + HT_CKCU->AHBCCR &= (~(1 << offset)); + } + return TRUE; + } + + HT_CKCU->AHBCCR |= (1 << offset); + return FALSE; +} + +/*********************************************************************************************************//** + * @brief Turn on/Turn off AFIO clock. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval TRUE or FALSE (TRUE: already turn on, FALSE, Turn on by this call) + ***********************************************************************************************************/ +u32 _AFIO_ClockControl(ControlStatus Cmd) +{ + u32 AFIOENStatus; + + AFIOENStatus = HT_CKCU->APBCCR0 & (1 << 14); + + if (AFIOENStatus != 0) + { + if (Cmd == DISABLE) + { + HT_CKCU->APBCCR0 &= (~(1 << 14)); + } + return TRUE; + } + + HT_CKCU->APBCCR0 |= (1 << 14); + return FALSE; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_gptm.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_gptm.c new file mode 100644 index 00000000000..b824c72b168 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_gptm.c @@ -0,0 +1,2 @@ +The SCTM, PWM, GPTM, and MCTM timer have similar architecture. They use the same driver, +"ht32fxxxxx_tm.c/.h" to save the code size. For those timers, please refet to the TM driver/example. diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2c.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2c.c new file mode 100644 index 00000000000..81ea72bc65f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2c.c @@ -0,0 +1,773 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_i2c.c + * @version $Rev:: 2787 $ + * @date $Date:: 2022-11-23 #$ + * @brief This file provides all the I2C firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_i2c.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Private_Define I2C private definitions + * @{ + */ +/* I2C ENI2C mask */ +#define CR_ENI2C_SET ((u32)0x00000008) +#define CR_ENI2C_RESET ((u32)0xFFFFFFF7) + +/* I2C ENGC mask */ +#define CR_ENGC_SET ((u32)0x00000004) +#define CR_ENGC_RESET ((u32)0xFFFFFFFB) + +/* I2C AA mask */ +#define CR_ACK_SET ((u32)0x00000001) +#define CR_ACK_RESET ((u32)0xFFFFFFFE) + +/* I2C PDMANACK mask */ +#define CR_PDMANACK_SET ((u32)0x00000400) +#define CR_PDMANACK_RESET ((u32)0xFFFFFBFF) + +/* I2C ENTOUT mask */ +#define CR_ENTOUT_SET ((u32)0x00001000) +#define CR_ENTOUT_RESET ((u32)0xFFFFEFFF) + +/* I2C COMBFILT mask */ +#define CR_COMBFILTER_SET ((u32)0x00002000) +#define CR_COMBFILTER_RESET ((u32)0xFFFFDFFF) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Functions I2C exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the I2C peripheral registers to their default reset values. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval None + ************************************************************************************************************/ +void I2C_DeInit(HT_I2C_TypeDef* I2Cx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + if (I2Cx == HT_I2C0) + { + RSTCUReset.Bit.I2C0 = 1; + } + else if (I2Cx == HT_I2C1) + { + RSTCUReset.Bit.I2C1 = 1; + } + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the I2Cx peripheral according to the specified parameters in the I2C_InitStruct. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void I2C_Init(HT_I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + u32 PCLK_Freq = 0; + s32 sTmp = 0; + s32 SHPGR = 0; + s32 SLPGR = 0; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_GENERAL_CALL(I2C_InitStruct->I2C_GeneralCall)); + Assert_Param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AddressingMode)); + Assert_Param(IS_I2C_ACKNOWLEDGE(I2C_InitStruct->I2C_Acknowledge)); + Assert_Param(IS_I2C_ADDRESS(I2C_InitStruct->I2C_OwnAddress)); + Assert_Param(IS_I2C_SPEED(I2C_InitStruct->I2C_Speed)); + + I2Cx->CR = (I2Cx->CR & 0xFFFFFF7A) | I2C_InitStruct->I2C_GeneralCall | + I2C_InitStruct->I2C_AddressingMode | I2C_InitStruct->I2C_Acknowledge; + + I2Cx->ADDR = I2C_InitStruct->I2C_OwnAddress; + + if (I2Cx == HT_I2C0) + PCLK_Freq = CKCU_GetPeripFrequency(CKCU_PCLK_I2C0); + else if (I2Cx == HT_I2C1) + PCLK_Freq = CKCU_GetPeripFrequency(CKCU_PCLK_I2C1); + + switch (I2Cx->CR & 0xC000) + { + case 0: + { + sTmp = 6; + break; + } + case 0x4000: + { + sTmp = 8; + break; + } + case 0x8000: + { + sTmp = 9; + break; + } + } + + SHPGR = (PCLK_Freq * 9)/(I2C_InitStruct->I2C_Speed * 20) - sTmp - I2C_InitStruct->I2C_SpeedOffset; + SLPGR = (PCLK_Freq * 11)/(I2C_InitStruct->I2C_Speed * 20) - sTmp - I2C_InitStruct->I2C_SpeedOffset; + + SHPGR = (SHPGR < 0) ? 0 : SHPGR; + SLPGR = (SLPGR < 0) ? 0 : SLPGR; + + I2Cx->SHPGR = SHPGR; + I2Cx->SLPGR = SLPGR; +} + +/*********************************************************************************************************//** + * @brief Fill each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ + I2C_InitStruct->I2C_GeneralCall = I2C_GENERALCALL_DISABLE; + I2C_InitStruct->I2C_AddressingMode = I2C_ADDRESSING_7BIT; + I2C_InitStruct->I2C_Acknowledge = I2C_ACK_DISABLE; + I2C_InitStruct->I2C_OwnAddress = 0; + I2C_InitStruct->I2C_Speed = 1000000; + I2C_InitStruct->I2C_SpeedOffset = 0; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified I2C peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_Cmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ENI2C_SET; + } + else + { + I2Cx->CR &= CR_ENI2C_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Generate STOP condition of I2C communication. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval None + ************************************************************************************************************/ +void I2C_GenerateSTOP(HT_I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + I2Cx->CR |= 0x2; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable I2C interrupts. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Int: specify if the I2C interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_INT_STA + * @arg I2C_INT_STO + * @arg I2C_INT_ADRS + * @arg I2C_INT_GCS + * @arg I2C_INT_ARBLOS + * @arg I2C_INT_RXNACK + * @arg I2C_INT_BUSERR + * @arg I2C_INT_TOUT + * @arg I2C_INT_RXDNE + * @arg I2C_INT_TXDE + * @arg I2C_INT_RXBF + * @arg I2C_INT_ALL + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_IntConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_INT(I2C_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->IER |= I2C_Int; + } + else + { + I2Cx->IER &= (u32)~I2C_Int; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable I2C General Call. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_GeneralCallCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ENGC_SET; + } + else + { + I2Cx->CR &= CR_ENGC_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable I2C sending acknowledgement. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_AckCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ACK_SET; + } + else + { + I2Cx->CR &= CR_ACK_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Configure own address of the specified I2C. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Address: specify own address of I2C. + * @retval None + ************************************************************************************************************/ +void I2C_SetOwnAddress(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDRESS(I2C_Address)); + + I2Cx->ADDR = I2C_Address; +} + +/*********************************************************************************************************//** + * @brief Start transmitting to target slave address. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Address: specify the slave address which will be transmitted. + * @param I2C_Direction: This parameter can be I2C_MASTER_READ or I2C_MASTER_WRITE. + * @retval None + ************************************************************************************************************/ +void I2C_TargetAddressConfig(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address, u32 I2C_Direction) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDRESS(I2C_Address)); + Assert_Param(IS_I2C_DIRECTION(I2C_Direction)); + + /* Make sure the prior stop command has been finished */ + while (I2Cx->CR & 0x2); + + if (I2C_Direction != I2C_MASTER_WRITE) + { + I2Cx->TAR = I2C_Address | I2C_MASTER_READ; + } + else + { + I2Cx->TAR = I2C_Address | I2C_MASTER_WRITE; + } +} + +/*********************************************************************************************************//** + * @brief Send a data word through the I2Cx peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Data: Byte to be transmitted. + * @retval None + ************************************************************************************************************/ +void I2C_SendData(HT_I2C_TypeDef* I2Cx, u8 I2C_Data) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + I2Cx->DR = I2C_Data; +} + +/*********************************************************************************************************//** + * @brief Return the received data by the I2Cx peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval The value of the received data. + ************************************************************************************************************/ +u8 I2C_ReceiveData(HT_I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + return (u8)I2Cx->DR; +} + +/*********************************************************************************************************//** + * @brief Read the specified I2C register and returns its value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Register: specify the register to read. + * This parameter can be one of the following values: + * @arg I2C_REGISTER_CR : Control Register + * @arg I2C_REGISTER_IER : Interrupt Enable Register + * @arg I2C_REGISTER_ADDR : Address Register + * @arg I2C_REGISTER_SR : Status Register + * @arg I2C_REGISTER_SHPGR : SCL High Period Generation Register + * @arg I2C_REGISTER_SLPGR : SCL Low Period Generation Register + * @arg I2C_REGISTER_DR : Data Register + * @arg I2C_REGISTER_TAR : Target Register + * @retval None + ************************************************************************************************************/ +u32 I2C_ReadRegister(HT_I2C_TypeDef* I2Cx, u8 I2C_Register) +{ + vu32 tmp = 0; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (u32)I2Cx; + tmp += I2C_Register; + return (*(u32 *)tmp); +} + +/*********************************************************************************************************//** + * @brief Check whether the specified I2C flag has been set. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Flag: specify the flag to be check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_STA : I2C start condition transmitted flag (Master mode) + * @arg I2C_FLAG_STO : I2C stop condition detected flag (Slave flag) + * @arg I2C_FLAG_ADRS : I2C address flag + * @arg I2C_FLAG_GCS : I2C general call flag (Slave mode) + * @arg I2C_FLAG_ARBLOS : I2C arbitration loss flag (Master mode) + * @arg I2C_FLAG_RXNACK : I2C received not acknowledge flag + * @arg I2C_FLAG_BUSERR : I2C bus error flag + * @arg I2C_FLAG_RXDNE : I2C Rx data not empty flag + * @arg I2C_FLAG_TXDE : I2C Tx data empty flag + * @arg I2C_FLAG_RXBF : I2C RX buffer full flag + * @arg I2C_FLAG_BUSBUSY : I2C bus busy flag + * @arg I2C_FLAG_MASTER : I2C master mode flag (Master flag) + * @arg I2C_FLAG_TXNRX : I2C transmitter mode flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus I2C_GetFlagStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_FLAG(I2C_Flag)); + + if ((I2Cx->SR & I2C_Flag) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified I2C status has been active. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Status: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg I2C_MASTER_SEND_START + * @arg I2C_MASTER_RECEIVER_MODE + * @arg I2C_MASTER_TRANSMITTER_MODE + * @arg I2C_MASTER_RX_NOT_EMPTY + * @arg I2C_MASTER_RX_NOT_EMPTY_NOBUSY + * @arg I2C_MASTER_TX_EMPTY + * @arg I2C_MASTER_RX_BUFFER_FULL + * @arg I2C_SLAVE_ACK_TRANSMITTER_ADDRESS + * @arg I2C_SLAVE_ACK_RECEIVER_ADDRESS + * @arg I2C_SLAVE_ACK_GCALL_ADDRESS + * @arg I2C_SLAVE_RX_NOT_EMPTY + * @arg I2C_SLAVE_RX_NOT_EMPTY_STOP + * @arg I2C_SLAVE_TX_EMPTY + * @arg I2C_SLAVE_RX_BUFFER_FULL + * @arg I2C_SLAVE_RECEIVED_NACK + * @arg I2C_SLAVE_RECEIVED_NACK_STOP + * @arg I2C_SLAVE_STOP_DETECTED + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus I2C_CheckStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Status) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_STATUS(I2C_Status)); + + if (I2Cx->SR == I2C_Status) + { + return (SUCCESS); + } + else + { + return (ERROR); + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified I2C flag. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Flag: specify the flag that is to be cleared. + * This parameter can be one of the following values: + * @arg I2C_FLAG_ARBLOS : I2C arbitration flag + * @arg I2C_FLAG_RXNACK : I2C receive not acknowledge flag + * @arg I2C_FLAG_BUSERR : I2C Bus error flag + * @retval None + ************************************************************************************************************/ +void I2C_ClearFlag(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_CLEAR_FLAG(I2C_Flag)); + + I2Cx->SR = I2C_Flag; +} + +/*********************************************************************************************************//** + * @brief Set the interval timing of the high period of the I2C clock. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_HighPeriod: specify the high period that is to be set. + * This parameter must be a number between 0 and 0xFFFF. + * @retval None + ************************************************************************************************************/ +void I2C_SetSCLHighPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_HighPeriod) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_SCL_HIGH(I2C_HighPeriod)); + + I2Cx->SHPGR = I2C_HighPeriod; +} + +/*********************************************************************************************************//** + * @brief Set the interval timing of low period of the I2C clock. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_LowPeriod: specify the low period that is to be set. + * This parameter must be a number between 0 and 0xFFFF. + * @retval None + ************************************************************************************************************/ +void I2C_SetSCLLowPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_LowPeriod) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_SCL_LOW(I2C_LowPeriod)); + + I2Cx->SLPGR = I2C_LowPeriod; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the I2Cx PDMA interface. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_PDMAREQ: specify the I2C PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_PDMAREQ_TX: Tx PDMA transfer request + * @arg I2C_PDMAREQ_RX: Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_PDMACmd(HT_I2C_TypeDef* I2Cx, u32 I2C_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_PDMA_REQ(I2C_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= I2C_PDMAREQ; + } + else + { + I2Cx->CR &= ~I2C_PDMAREQ; + } +} + +/*********************************************************************************************************//** + * @brief Specify that the next PDMA transfer is the last one. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_PDMANACKCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_PDMANACK_SET; + } + else + { + I2Cx->CR &= CR_PDMANACK_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified I2C time out function. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_TimeOutCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ENTOUT_SET; + } + else + { + I2Cx->CR &= CR_ENTOUT_RESET; + } +} + +/*********************************************************************************************************//** + * @brief This function is used to set the I2C timeout value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Timeout: specify the timeout value. + * @retval None + ************************************************************************************************************/ +void I2C_SetTimeOutValue(HT_I2C_TypeDef* I2Cx, u32 I2C_Timeout) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_TIMEOUT(I2C_Timeout)); + + I2Cx->TOUT = (I2C_Timeout | (I2Cx->TOUT & 0xFFFF0000)); +} + +/*********************************************************************************************************//** + * @brief This function is used to set the prescaler of I2C timeout value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Prescaler: specify the I2C time out prescaler value. + * This parameter can be one of the following values: + * @arg I2C_PRESCALER_1 : I2C prescaler set to 1 + * @arg I2C_PRESCALER_2 : I2C prescaler set to 2 + * @arg I2C_PRESCALER_4 : I2C prescaler set to 4 + * @arg I2C_PRESCALER_16 : I2C prescaler set to 16 + * @arg I2C_PRESCALER_32 : I2C prescaler set to 32 + * @arg I2C_PRESCALER_64 : I2C prescaler set to 64 + * @arg I2C_PRESCALER_128 : I2C prescaler set to 128 + * @retval None + ************************************************************************************************************/ +void I2C_SetTimeOutPrescaler(HT_I2C_TypeDef* I2Cx, u32 I2C_Prescaler) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_PRESCALER(I2C_Prescaler)); + + I2Cx->TOUT = (I2C_Prescaler | (I2Cx->TOUT & 0x0000FFFF)); +} + +/*********************************************************************************************************//** + * @brief This function is used to determine the prescaler of I2C timeout value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Mask: specify the bit position of I2C slave address to be masked. + * This parameter can be any combination of the following values: + * @arg I2C_MASKBIT_0 : Bit 0 of I2C slave address is masked + * @arg I2C_MASKBIT_1 : Bit 1 of I2C slave address is masked + * @arg I2C_MASKBIT_2 : Bit 2 of I2C slave address is masked + * @arg I2C_MASKBIT_3 : Bit 3 of I2C slave address is masked + * @arg I2C_MASKBIT_4 : Bit 4 of I2C slave address is masked + * @arg I2C_MASKBIT_5 : Bit 5 of I2C slave address is masked + * @arg I2C_MASKBIT_6 : Bit 6 of I2C slave address is masked + * @arg I2C_MASKBIT_7 : Bit 7 of I2C slave address is masked + * @arg I2C_MASKBIT_8 : Bit 8 of I2C slave address is masked + * @arg I2C_MASKBIT_9 : Bit 9 of I2C slave address is masked + * @retval None + ************************************************************************************************************/ +void I2C_AddressMaskConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Mask) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDRESS_MASK(I2C_Mask)); + + I2Cx->ADDMR = I2C_Mask; +} + +/*********************************************************************************************************//** + * @brief Return the received address by the I2Cx peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval The value of the received address. + ************************************************************************************************************/ +u16 I2C_GetAddressBuffer(HT_I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + return ((u16)I2Cx->ADDSR); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the combinational filter. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_CombFilterCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_COMBFILTER_SET; + } + else + { + I2Cx->CR &= CR_COMBFILTER_RESET; + } +} + +/*********************************************************************************************************//** + * @brief This function is used to determine the filter glitch width of 0~2 PCLK. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param Seq_Filter_Select: specify the glitch width of 0~2 PCLK. + * This parameter can be any combination of the following values: + * @arg SEQ_FILTER_DISABLE : sequential filter is disabled + * @arg SEQ_FILTER_1_PCLK : filter glitch width of 1 PCLK + * @arg SEQ_FILTER_2_PCLK : filter glitch width of 2 PCLK + * @retval None + ************************************************************************************************************/ +void I2C_SequentialFilterConfig(HT_I2C_TypeDef* I2Cx, u32 Seq_Filter_Select) +{ + u32 SHPGR = I2Cx->SHPGR; + u32 SLPGR = I2Cx->SLPGR; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_SEQ_FILTER_MASK(Seq_Filter_Select)); + + switch (I2Cx->CR & 0xC000) + { + case 0: + if (Seq_Filter_Select == SEQ_FILTER_1_PCLK) + { + if (SHPGR >= 2) + { + SHPGR -= 2; + SLPGR -= 2; + } + } + else if (Seq_Filter_Select == SEQ_FILTER_2_PCLK) + { + if (SHPGR >= 2) + { + SHPGR -= 3; + SLPGR -= 3; + } + } + break; + + case 0x4000: + if (Seq_Filter_Select == SEQ_FILTER_DISABLE) + { + SHPGR += 2; + SLPGR += 2; + } + else if (Seq_Filter_Select == SEQ_FILTER_2_PCLK) + { + if (SHPGR >= 1) + { + SHPGR -= 1; + SLPGR -= 1; + } + } + break; + + case 0x8000: + if (Seq_Filter_Select == SEQ_FILTER_DISABLE) + { + SHPGR += 3; + SLPGR += 3; + } + else if (Seq_Filter_Select == SEQ_FILTER_1_PCLK) + { + SHPGR += 1; + SLPGR += 1; + } + break; + + default: + break; + } + + I2Cx->SHPGR = SHPGR; + I2Cx->SLPGR = SLPGR; + I2Cx->CR = (I2Cx->CR & 0x3FFF) | Seq_Filter_Select; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2s.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2s.c new file mode 100644 index 00000000000..b2698441276 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_i2s.c @@ -0,0 +1,336 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_i2s.c + * @version $Rev:: 2140 $ + * @date $Date:: 2020-07-23 #$ + * @brief This file provides all the I2S firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_i2s.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup I2S I2S + * @brief I2S driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Private_Define I2S private definitions + * @{ + */ +#define I2S_EN (1UL) +#define MCLK_OP_EN (1UL << 9) +#define TX_MUTE_EN (1UL << 12) +#define CLK_DIV_EN (1UL << 15) +#define BCLK_INV_EN (1UL << 18) +#define MCLK_INV_EN (1UL << 19) + +#define I2S_SLAVE (1UL << 3) +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Functions I2S exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the I2S peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void I2S_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.I2S = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the I2S peripheral according to the specified parameters in the I2S_InitStruct. + * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void I2S_Init(I2S_InitTypeDef* I2S_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + Assert_Param(IS_I2S_FORMAT(I2S_InitStruct->I2S_Format)); + Assert_Param(IS_I2S_WORD_WIDTH(I2S_InitStruct->I2S_WordWidth)); + Assert_Param(IS_I2S_MCLK_DIV(I2S_InitStruct->I2S_X_Div, I2S_InitStruct->I2S_Y_Div)); + Assert_Param(IS_I2S_BCLK_DIV(I2S_InitStruct->I2S_N_Div)); + + HT_I2S->CR = I2S_InitStruct->I2S_Mode | I2S_InitStruct->I2S_Format | I2S_InitStruct->I2S_WordWidth; + + if (I2S_InitStruct->I2S_BclkInv == ENABLE) + { + HT_I2S->CR |= BCLK_INV_EN; + } + + if (I2S_InitStruct->I2S_MclkInv == ENABLE) + { + HT_I2S->CR |= MCLK_INV_EN; + } + + if ((I2S_InitStruct->I2S_Mode & I2S_SLAVE) == RESET) + { + HT_I2S->CDR = (I2S_InitStruct->I2S_N_Div << 16) | (I2S_InitStruct->I2S_X_Div << 8) | + (I2S_InitStruct->I2S_Y_Div); + HT_I2S->CR |= CLK_DIV_EN; + while (I2S_GetFlagStatus(I2S_FLAG_CLK_RDY) == RESET); + + if (I2S_InitStruct->I2S_MclkOut == ENABLE) + { + HT_I2S->CR |= MCLK_OP_EN; + } + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the I2S peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_Cmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->CR |= I2S_EN; + } + else + { + HT_I2S->CR &= ~I2S_EN; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the Tx mute for the I2S peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_TxMuteCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->CR |= TX_MUTE_EN; + } + else + { + HT_I2S->CR &= ~TX_MUTE_EN; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the I2S PDMA interface. + * @param I2S_PDMAREQ: specify the I2S PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2S_PDMAREQ_TX : Tx PDMA transfer request + * @arg I2S_PDMAREQ_RX : Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_PDMACmd(u32 I2S_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_PDMA_REQ(I2S_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->CR |= I2S_PDMAREQ; + } + else + { + HT_I2S->CR &= I2S_PDMAREQ; + } +} + +/*********************************************************************************************************//** + * @brief Reset the specified I2S FIFO. + * @param I2S_FIFO: specify the FIFO that is to be reset. + * This parameter can be any combination of the following values: + * @arg I2S_TX_FIFO : I2S Tx FIFO + * @arg I2S_RX_FIFO : I2S Rx FIFO + * @retval None + ************************************************************************************************************/ +void I2S_FIFOReset(u32 I2S_FIFO) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_TWO_FIFO(I2S_FIFO)); + + HT_I2S->FCR |= I2S_FIFO; +} + +/*********************************************************************************************************//** + * @brief Set the trigger level of specified I2S FIFO. + * @param I2S_FIFO: specify the FIFO that is to be set. + * This parameter can be any combination of the following values: + * @arg I2S_TX_FIFO : I2S Tx FIFO + * @arg I2S_RX_FIFO : I2S Rx FIFO + * @param I2S_FIFOLevel: Specify the FIFO trigger level. + * @retval None + ************************************************************************************************************/ +void I2S_FIFOTrigLevelConfig(u32 I2S_FIFO, u32 I2S_FIFOLevel) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_TWO_FIFO(I2S_FIFO)); + Assert_Param(IS_I2S_FIFO_LEVEL(I2S_FIFOLevel)); + + if (I2S_FIFO == I2S_TX_FIFO) + { + HT_I2S->FCR = ((HT_I2S->FCR & (~0x0000000F)) | I2S_FIFOLevel); + } + else + { + HT_I2S->FCR = ((HT_I2S->FCR & (~0x000000F0)) | (I2S_FIFOLevel << 4)); + } +} + +/*********************************************************************************************************//** + * @brief Return the status of specified I2S FIFO. + * @param I2S_FIFO: specify the FIFO that is to be checked. + * This parameter can be one of the following values: + * @arg I2S_TX_FIFO : I2S Tx FIFO + * @arg I2S_RX_FIFO : I2S Rx FIFO + * @retval The number of data in specified I2S FIFO. + ************************************************************************************************************/ +u8 I2S_GetFIFOStatus(u32 I2S_FIFO) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_ONE_FIFO(I2S_FIFO)); + + if (I2S_FIFO == I2S_TX_FIFO) + { + return (u8)((HT_I2S->SR >> 24) & 0x0F); + } + else + { + return (u8)(HT_I2S->SR >> 28); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the I2S interrupt. + * @param I2S_Int: specify if the I2S interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2S_INT_TXFIFO_TRI : I2S Tx FIFO trigger level interrupt + * @arg I2S_INT_TXFIFO_UF : I2S Rx FIFO underflow interrupt + * @arg I2S_INT_TXFIFO_OV : I2S Tx FIFO overflow interrupt + * @arg I2S_INT_RXFIFO_TRI : I2S Rx FIFO trigger level interrupt + * @arg I2S_INT_RXFIFO_UV : I2S Rx FIFO underflow interrupt + * @arg I2S_INT_RXFIFO_OV : I2S Rx FIFO overflow interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_IntConfig(u32 I2S_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_INT(I2S_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->IER |= I2S_Int; + } + else + { + HT_I2S->IER &= ~I2S_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified I2S flag has been set or not. + * @param I2S_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_TXFIFO_TRI : I2S Tx FIFO trigger level flag + * @arg I2S_FLAG_TXFIFO_UDF : I2S Tx FIFO underflow flag + * @arg I2S_FLAG_TXFIFO_OVF : I2S Tx FIFO overflow flag + * @arg I2S_FLAG_TXFIFO_EMP : I2S Tx FIFO empty flag + * @arg I2S_FLAG_TXFIFO_FUL : I2S Tx FIFO full flag + * @arg I2S_FLAG_RXFIFO_TRI : I2S Rx FIFO trigger level flag + * @arg I2S_FLAG_RXFIFO_UDF : I2S Rx FIFO underflow flag + * @arg I2S_FLAG_RXFIFO_OVF : I2S Rx FIFO overflow flag + * @arg I2S_FLAG_RXFIFO_EMP : I2S Rx FIFO empty flag + * @arg I2S_FLAG_RXFIFO_FUL : I2S Rx FIFO full flag + * @arg I2S_FLAG_RIGHT_CH : I2S right channel flag + * @arg I2S_FLAG_TX_BUSY : I2S Tx busy flag + * @arg I2S_FLAG_CLK_RDY : I2S clock ready flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus I2S_GetFlagStatus(u32 I2S_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_FLAG(I2S_Flag)); + + if (HT_I2S->SR & I2S_Flag) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified I2S flag. + * @param I2S_Flag: specify the flag that is to be cleared. + * This parameter can be any combination of the following values: + * @arg I2S_FLAG_TXFIFO_TRI : I2S Tx FIFO trigger level flag + * @arg I2S_FLAG_TXFIFO_UV : I2S Tx FIFO underflow flag + * @arg I2S_FLAG_TXFIFO_OV : I2S Tx FIFO overflow flag + * @arg I2S_FLAG_RXFIFO_TRI : I2S Rx FIFO trigger level flag + * @arg I2S_FLAG_RXFIFO_UV : I2S Rx FIFO underflow flag + * @arg I2S_FLAG_RXFIFO_OV : I2S Rx FIFO overflow flag + * @retval None + ************************************************************************************************************/ +void I2S_ClearFlag(u32 I2S_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_FLAG_CLEAR(I2S_Flag)); + + HT_I2S->SR = I2S_Flag; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_mctm.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_mctm.c new file mode 100644 index 00000000000..a77c3858b27 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_mctm.c @@ -0,0 +1,253 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_mctm.c + * @version $Rev:: 2797 $ + * @date $Date:: 2022-11-28 #$ + * @brief This file provides all the MCTM firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_mctm.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup MCTM MCTM + * @brief MCTM driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Private_Define MCTM private definitions + * @{ + */ +#define CTR_COMPRE 0x00000100ul +#define CTR_COMUS 0x00000200ul + +#define CHBRKCTR_CHMOE 0x00000010ul +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Functions MCTM exported functions + * @{ + */ + +/*********************************************************************************************************//** + * @brief Configure polarity of the MCTMx channel N. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripheral. + * @param Channel: Specify the MCTM channel. + * This parameter can be one of the following values: + * @arg MCTM_CH_0 : MCTM channel 0 + * @arg MCTM_CH_1 : MCTM channel 1 + * @arg MCTM_CH_2 : MCTM channel 2 + * @arg MCTM_CH_3 : MCTM channel 3 + * @param Pol: Specify the polarity of channel N. + * This parameter can be one of the following values: + * @arg MCTM_CHP_NONINVERTED : active high + * @arg MCTM_CHP_INVERTED : active low + * @retval None + ************************************************************************************************************/ +void MCTM_ChNPolarityConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHP_Enum Pol) +{ + u32 wChpolr; + + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_COMPLEMENTARY_CH(Channel)); + Assert_Param(IS_TM_CHP(Pol)); + + /* Set or reset the CHxN polarity */ + wChpolr = MCTMx->CHPOLR & (~(u32)(0x2 << (Channel << 1))); + MCTMx->CHPOLR = wChpolr | ((Pol << 1) << (Channel << 1)); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the MCTMx channel N. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripheral. + * @param Channel: Specify the MCTM channel. + * This parameter can be one of the following values: + * @arg MCTM_CH_0 : MCTM channel 0 + * @arg MCTM_CH_1 : MCTM channel 1 + * @arg MCTM_CH_2 : MCTM channel 2 + * @arg MCTM_CH_3 : MCTM channel 3 + * @param Control: This parameter can be TM_CHCTL_ENABLE or TM_CHCTL_DISABLE. + * @retval None + ************************************************************************************************************/ +void MCTM_ChannelNConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_COMPLEMENTARY_CH(Channel)); + Assert_Param(IS_TM_CHCTL(Control)); + + /* Reset the CHxNE Bit */ + MCTMx->CHCTR &= ~(u32)(0x2 << (Channel << 1)); + + /* Set or reset the CHxNE Bit */ + MCTMx->CHCTR |= (u32)(Control << 1) << (Channel << 1); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the channels main output of the MCTMx. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void MCTM_CHMOECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MCTM Main Output */ + MCTMx->CHBRKCTR |= CHBRKCTR_CHMOE; + } + else + { + /* Disable the MCTM Main Output */ + MCTMx->CHBRKCTR &= ~CHBRKCTR_CHMOE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the break feature, dead time, Lock level, the OSSI, the OSSR State + * and the CHAOE(automatic output enable). + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param CHBRKCTRInit: Point to a MCTM_CHBRKCTRInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void MCTM_CHBRKCTRConfig(HT_TM_TypeDef* MCTMx, MCTM_CHBRKCTRInitTypeDef *CHBRKCTRInit) +{ + u32 wTmpReg; + + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_OSSR_STATE(CHBRKCTRInit->OSSRState)); + Assert_Param(IS_MCTM_OSSI_STATE(CHBRKCTRInit->OSSIState)); + Assert_Param(IS_MCTM_LOCK_LEVEL(CHBRKCTRInit->LockLevel)); + Assert_Param(IS_MCTM_BREAK_STATE(CHBRKCTRInit->Break0)); + Assert_Param(IS_MCTM_BREAK_POLARITY(CHBRKCTRInit->Break0Polarity)); + Assert_Param(IS_MCTM_BREAK_STATE(CHBRKCTRInit->Break1)); + Assert_Param(IS_MCTM_BREAK_POLARITY(CHBRKCTRInit->Break1Polarity)); + Assert_Param(IS_MCTM_CHAOE_STATE(CHBRKCTRInit->AutomaticOutput)); + Assert_Param(IS_TM_FILTER(CHBRKCTRInit->BreakFilter)); + + wTmpReg = MCTMx->CHBRKCTR & 0x00000010; // Keep CHMOE + wTmpReg |= (u32)CHBRKCTRInit->BreakFilter << 8; + wTmpReg |= (u32)CHBRKCTRInit->DeadTime << 24; + wTmpReg |= CHBRKCTRInit->LockLevel | CHBRKCTRInit->OSSRState | CHBRKCTRInit->OSSIState; + wTmpReg |= CHBRKCTRInit->Break0 | CHBRKCTRInit->Break0Polarity | CHBRKCTRInit->AutomaticOutput; + wTmpReg |= (CHBRKCTRInit->Break1 << 2) | (CHBRKCTRInit->Break1Polarity << 2); + + MCTMx->CHBRKCTR = wTmpReg; +} + +/*********************************************************************************************************//** + * @brief Fill each CHBRKCTRInitStruct member with its default value. + * @param CHBRKCTRInitStruct: Point to a MCTM_CHBRKCTRInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void MCTM_CHBRKCTRStructInit(MCTM_CHBRKCTRInitTypeDef* CHBRKCTRInitStruct) +{ + /* Set the default configuration */ + CHBRKCTRInitStruct->OSSRState = MCTM_OSSR_STATE_DISABLE; + CHBRKCTRInitStruct->OSSIState = MCTM_OSSI_STATE_DISABLE; + CHBRKCTRInitStruct->LockLevel = MCTM_LOCK_LEVEL_OFF; + CHBRKCTRInitStruct->DeadTime = 0x00; + CHBRKCTRInitStruct->Break0 = MCTM_BREAK_DISABLE; + CHBRKCTRInitStruct->Break0Polarity = MCTM_BREAK_POLARITY_LOW; + CHBRKCTRInitStruct->Break1 = MCTM_BREAK_DISABLE; + CHBRKCTRInitStruct->Break1Polarity = MCTM_BREAK_POLARITY_LOW; + CHBRKCTRInitStruct->BreakFilter = 0; + CHBRKCTRInitStruct->AutomaticOutput = MCTM_CHAOE_DISABLE; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable MCTMx COMPRE function. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void MCTM_COMPRECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MCTM COMPRE */ + MCTMx->CTR |= CTR_COMPRE; + } + else + { + /* Disable the MCTM COMPRE */ + MCTMx->CTR &= ~CTR_COMPRE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the MCTMx COMUS function. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param Sel: Specify the COMUS value. + * This parameter can be one of the following values: + * @arg MCTM_COMUS_STIOFF : MCTM capture/compare control bits are updated by setting the UEV2G bit only + * @arg MCTM_COMUS_STION : MCTM capture/compare control bits are updated by both setting the UEV2G bit + * or when a rising edge occurs on STI + * @retval None + ************************************************************************************************************/ +void MCTM_COMUSConfig(HT_TM_TypeDef* MCTMx, MCTM_COMUS_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_COMUS(Sel)); + + if (Sel != MCTM_COMUS_STIOFF) + { + /* Set the MCTM COMUS bit */ + MCTMx->CTR |= CTR_COMUS; + } + else + { + /* Clear the MCTM COMUS bit */ + MCTMx->CTR &= ~CTR_COMUS; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pdma.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pdma.c new file mode 100644 index 00000000000..8a816d946fa --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pdma.c @@ -0,0 +1,341 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_pdma.c + * @version $Rev:: 2717 $ + * @date $Date:: 2022-08-20 #$ + * @brief This file provides all the PDMA firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_pdma.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup PDMA PDMA + * @brief PDMA driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Functions PDMA exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the PDMA peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void PDMA_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.PDMA = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure specific PDMA channel + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * PDMA_CH0 ~ PDMA_CH7 + * PDMA_CH8 ~ PDMA_CH11 (For specific models only) + * @param PDMACH_InitStruct: pointer to a PDMACH_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void PDMA_Config(u32 PDMA_CHn, PDMACH_InitTypeDef *PDMACH_InitStruct) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_WIDTH(PDMACH_InitStruct->PDMACH_DataSize)); + Assert_Param(IS_PDMA_PRIO(PDMACH_InitStruct->PDMACH_Priority)); + Assert_Param(IS_PDMA_ADR_MOD(PDMACH_InitStruct->PDMACH_AdrMod)); + Assert_Param(IS_PDMA_BLK_CNT(PDMACH_InitStruct->PDMACH_BlkCnt)); + Assert_Param(IS_PDMA_BLK_LEN(PDMACH_InitStruct->PDMACH_BlkLen)); + + /* PDMA channel x configuration */ + PDMACHx->CR = (PDMACH_InitStruct->PDMACH_DataSize | PDMACH_InitStruct->PDMACH_Priority | PDMACH_InitStruct->PDMACH_AdrMod); + + PDMACHx->SADR = PDMACH_InitStruct->PDMACH_SrcAddr; + + PDMACHx->DADR = PDMACH_InitStruct->PDMACH_DstAddr; + + PDMACHx->TSR = (PDMACH_InitStruct->PDMACH_BlkCnt << 16) | PDMACH_InitStruct->PDMACH_BlkLen; +} + +/*********************************************************************************************************//** + * @brief PDMA_AddrConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param SrcAddr: Source address + * @param DstAddr: Destination address + * @retval None + ************************************************************************************************************/ +void PDMA_AddrConfig(u32 PDMA_CHn, u32 SrcAddr, u32 DstAddr) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + /* transfer address configuration */ + PDMACHx->SADR = SrcAddr; + PDMACHx->DADR = DstAddr; +} + +/*********************************************************************************************************//** + * @brief PDMA_SrcAddrConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param SrcAddr: Source address + * @retval None + ************************************************************************************************************/ +void PDMA_SrcAddrConfig(u32 PDMA_CHn, u32 SrcAddr) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + /* transfer address configuration */ + PDMACHx->SADR = SrcAddr; +} + +/*********************************************************************************************************//** + * @brief PDMA_DstAddrConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param DstAddr: Destination address + * @retval None + ************************************************************************************************************/ +void PDMA_DstAddrConfig(u32 PDMA_CHn, u32 DstAddr) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + /* transfer address configuration */ + PDMACHx->DADR = DstAddr; +} + +/*********************************************************************************************************//** + * @brief PDMA_TranSizeConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * PDMA_CH0 ~ PDMA_CH7 + * PDMA_CH8 ~ PDMA_CH11 (For specific models only) + * @param BlkCnt: Number of blocks for a transfer + * @param BlkLen: Number of data for a block + * @retval None + ************************************************************************************************************/ +void PDMA_TranSizeConfig(u32 PDMA_CHn, u16 BlkCnt, u16 BlkLen) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_BLK_CNT(BlkCnt)); + Assert_Param(IS_PDMA_BLK_LEN(BlkLen)); + + /* transfer size configuration */ + PDMACHx->TSR = ((BlkCnt << 16) | BlkLen); +} + +/*********************************************************************************************************//** + * @brief Enable the specific PDMA channel interrupts + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * PDMA_CH0 ~ PDMA_CH7 + * PDMA_CH8 ~ PDMA_CH11 (For specific models only) + * @param PDMA_INT_x: PDMA_INT_GE, PDMA_INT_BE, PDMA_INT_HT, PDMA_INT_TC, PDMA_INT_TE + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PDMA_IntConfig(u32 PDMA_CHn, u32 PDMA_INT_x, ControlStatus NewState) +{ + #if (LIBCFG_PDMA_V01) + u32 *PdmaIntEnReg = ((u32 *)(&HT_PDMA->IER0)); + #else + u32 *PdmaIntEnReg = (PDMA_CHn < 6) ? ((u32 *)(&HT_PDMA->IER0)) : ((u32 *)(&HT_PDMA->IER1)); + #endif + u32 BitShift = (PDMA_CHn < 6) ? (PDMA_CHn * 5) : ((PDMA_CHn - 6) * 5); + u32 uRegTmp = 0; + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_INT(PDMA_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_PDMA_CH3FIX) + if (PDMA_CHn == PDMA_CH3) + { + if (PDMA_INT_x & PDMA_INT_BE) + { + uRegTmp |= (PDMA_INT_BE << (PDMA_CH2 * 5)); + } + if (PDMA_INT_x & PDMA_INT_HT) + { + uRegTmp |= (PDMA_INT_HT << (PDMA_CH2 * 5)); + } + } + #endif + + if (NewState != DISABLE) + { + *PdmaIntEnReg |= ((PDMA_INT_x << BitShift) | uRegTmp); + } + else + { + *PdmaIntEnReg &= ~(PDMA_INT_x << BitShift); + } +} + +/*********************************************************************************************************//** + * @brief Enable a specific PDMA channel + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * PDMA_CH0 ~ PDMA_CH7 + * PDMA_CH8 ~ PDMA_CH11 (For specific models only) + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PDMA_EnaCmd(u32 PDMA_CHn, ControlStatus NewState) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SetBit_BB((u32)(&PDMACHx->CR), 0); + } + else + { + ResetBit_BB((u32)(&PDMACHx->CR), 0); + } +} + +/*********************************************************************************************************//** + * @brief Software trigger a specific PDMA channel + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * PDMA_CH0 ~ PDMA_CH7 + * PDMA_CH8 ~ PDMA_CH11 (For specific models only) + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PDMA_SwTrigCmd(u32 PDMA_CHn, ControlStatus NewState) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SetBit_BB((u32)(&PDMACHx->CR), 1); + } + else + { + ResetBit_BB((u32)(&PDMACHx->CR), 1); + } +} + +/*********************************************************************************************************//** + * @brief Get the specific PDMA channel interrupt flag + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * PDMA_CH0 ~ PDMA_CH7 + * PDMA_CH8 ~ PDMA_CH11 (For specific models only) + * @param PDMA_FLAG_x: PDMA_FLAG_GE, PDMA_FLAG_BE, PDMA_FLAG_HT, PDMA_FLAG_TC, PDMA_FLAG_TE + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus PDMA_GetFlagStatus(u32 PDMA_CHn, u32 PDMA_FLAG_x) +{ + #if (LIBCFG_PDMA_V01) + u32 *PdmaIntStatReg = ((u32 *)(&HT_PDMA->ISR0)); + #else + u32 *PdmaIntStatReg = (PDMA_CHn < 6) ? ((u32 *)(&HT_PDMA->ISR0)) : ((u32 *)(&HT_PDMA->ISR1)); + #endif + u32 BitShift = (PDMA_CHn < 6) ? (PDMA_CHn * 5) : ((PDMA_CHn - 6) * 5); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_FLAG(PDMA_FLAG_x)); + + if ((*PdmaIntStatReg & (PDMA_FLAG_x << BitShift)) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specific PDMA channel interrupt flags + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * PDMA_CH0 ~ PDMA_CH7 + * PDMA_CH8 ~ PDMA_CH11 (For specific models only) + * @param PDMA_FLAG_x: PDMA_FLAG_GE, PDMA_FLAG_BE, PDMA_FLAG_HT, PDMA_FLAG_TC, PDMA_FLAG_TE + * @retval None + ************************************************************************************************************/ +void PDMA_ClearFlag(u32 PDMA_CHn, u32 PDMA_FLAG_x) +{ + #if (LIBCFG_PDMA_V01) + u32 *PdmaIntStatClrReg = ((u32 *)(&HT_PDMA->ISCR0)); + #else + u32 *PdmaIntStatClrReg = (PDMA_CHn < 6) ? ((u32 *)(&HT_PDMA->ISCR0)) : ((u32 *)(&HT_PDMA->ISCR1)); + #endif + u32 BitShift = (PDMA_CHn < 6) ? (PDMA_CHn * 5) : ((PDMA_CHn - 6) * 5); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_CLEAR_FLAG(PDMA_FLAG_x)); + + *PdmaIntStatClrReg |= (PDMA_FLAG_x << BitShift); +} + +/*********************************************************************************************************//** + * @brief Get remain block count of the specific PDMA channel + * @retval CBLKCNT + ************************************************************************************************************/ +u16 PDMA_GetRemainBlkCnt(u32 PDMA_CHn) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + return ((PDMACHx->CTSR) >> 16); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pwm.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pwm.c new file mode 100644 index 00000000000..b824c72b168 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pwm.c @@ -0,0 +1,2 @@ +The SCTM, PWM, GPTM, and MCTM timer have similar architecture. They use the same driver, +"ht32fxxxxx_tm.c/.h" to save the code size. For those timers, please refet to the TM driver/example. diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pwrcu.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pwrcu.c new file mode 100644 index 00000000000..82f0fdb62a8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_pwrcu.c @@ -0,0 +1,665 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_pwrcu.c + * @version $Rev:: 2970 $ + * @date $Date:: 2023-10-25 #$ + * @brief This file provides all the Power Control Unit firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_pwrcu.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup PWRCU PWRCU + * @brief PWRCU driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Private_Define PWRCU private definitions + * @{ + */ +#define APBCCR1_ADDR (HT_CKCU_BASE + 0x30) +#define BAKCR_ADDR (HT_PWRCU_BASE + 0x04) +#define LVDCSR_ADDR (HT_PWRCU_BASE + 0x10) + +#define BB_ADCEN BitBand(APBCCR1_ADDR, 24) +#define BB_RTCEN BitBand(APBCCR1_ADDR, 6) + +#define BB_LDOLCM BitBand(BAKCR_ADDR, 2) +#define BB_LDOOFF BitBand(BAKCR_ADDR, 3) +#define BB_DMOSON BitBand(BAKCR_ADDR, 7) +#define BB_WUPEN BitBand(BAKCR_ADDR, 8) +#define BB_WUPIEN BitBand(BAKCR_ADDR, 9) +#define BB_VRDYSC BitBand(BAKCR_ADDR, 12) +#define BB_DMOSSTS BitBand(BAKCR_ADDR, 15) + +#define BB_BODEN BitBand(LVDCSR_ADDR, 0) +#define BB_BODRIS BitBand(LVDCSR_ADDR, 1) +#define BB_BODF BitBand(LVDCSR_ADDR, 3) +#define BB_LVDEN BitBand(LVDCSR_ADDR, 16) +#define BB_LVDF BitBand(LVDCSR_ADDR, 19) +#define BB_LVDIWEN BitBand(LVDCSR_ADDR, 20) +#define BB_LVDEWEN BitBand(LVDCSR_ADDR, 21) + +#define LDOFTRM_MASK 0xFFFFFFCF +#define LVDS_MASK 0xFFB9FFFF +#define BAKRST_SET 0x1 +#define BAKTEST_READY 0x27 +#define TIME_OUT 48000000 + +#define SLEEPDEEP_SET 0x04 /*!< Cortex SLEEPDEEP bit */ +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Functions PWRCU exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize Backup domain which contains PWRCU and RTC units. + * @retval None + ************************************************************************************************************/ +void PWRCU_DeInit(void) +{ + HT_PWRCU->CR = BAKRST_SET; + while(HT_PWRCU->CR & 0xFFFFEFFF); /* Skip Bit 12 when wait RESET finish. */ + while (HT_PWRCU->SR); /* Waits until the BAKPORF be cleared by read */ +} + +/*********************************************************************************************************//** + * @brief Waits, until the PWRCU can be accessed. + * @retval PWRCU_TIMEOUT or PWRCU_OK + ************************************************************************************************************/ +PWRCU_Status PWRCU_CheckReadyAccessed(void) +{ + u32 wTimeOutCnt = TIME_OUT; + +#if (!LIBCFG_NO_BACK_DOMAIN) + /* Set the ISO control bit */ + HT_CKCU->LPCR = 0x1; +#endif + + while (--wTimeOutCnt) + { + if (HT_PWRCU->TEST == BAKTEST_READY) + { + #if (!LIBCFG_NO_BACK_DOMAIN) + u32 write = ~HT_PWRCU->BAKREG[9]; + u32 backup = HT_PWRCU->BAKREG[9]; + while (1) + { + HT_PWRCU->BAKREG[9] = write; + if (HT_PWRCU->BAKREG[9] == write) break; + } + HT_PWRCU->BAKREG[9] = backup; + #endif + return PWRCU_OK; + } + } + return PWRCU_TIMEOUT; +} + +/*********************************************************************************************************//** + * @brief Return the flags of PWRCU. + * @retval This function will return one of the following: + * - 0x0000 : There is no flag is set. + * - 0x0001 (PWRCU_FLAG_PWRPOR) : Backup domain power-on reset flag has been set. + * - 0x0002 (PWRCU_FLAG_PD) : Power-Down flag has been set. + * - 0x0100 (PWRCU_FLAG_WUP) : External WAKEUP pin flag has been set. + * - 0x0102 (PWRCU_FLAG_PD | PWRCU_FLAG_WUP) : Both PDF and WUPF flags have been set. + ************************************************************************************************************/ +u16 PWRCU_GetFlagStatus(void) +{ + u32 uRTCStatus = 0; + u32 uStatus; + uRTCStatus = BB_RTCEN; + + BB_RTCEN = 1; + + uStatus = HT_PWRCU->SR; + BB_RTCEN = uRTCStatus; + + return uStatus; +} + +#if (!LIBCFG_NO_BACK_DOMAIN) +/*********************************************************************************************************//** + * @brief Return the value of specified backup register. + * @param BAKREGx: Number of backup register. Where x can be 0 ~ 9. + * @return Between 0x0 ~ 0xFFFFFFFF. + ************************************************************************************************************/ +u32 PWRCU_ReadBackupRegister(PWRCU_BAKREG_Enum BAKREGx) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_BAKREG(BAKREGx)); + + return HT_PWRCU->BAKREG[BAKREGx]; +} + +/*********************************************************************************************************//** + * @brief Write the DATA to specified backup register. + * @param BAKREGx : Number of backup registers. Where x can be 0 ~ 9. + * @param DATA : Must between 0x0 ~ 0xFFFFFFFF. + * @retval None + ************************************************************************************************************/ +void PWRCU_WriteBackupRegister(PWRCU_BAKREG_Enum BAKREGx, u32 DATA) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_BAKREG(BAKREGx)); + + HT_PWRCU->BAKREG[BAKREGx] = DATA; +} +#endif + +/*********************************************************************************************************//** + * @brief Enter SLEEP mode. + * @param SleepEntry : Enters sleep mode instruction that is used to WFI or WFE. + * This parameter can be one of the following values: + * @arg PWRCU_SLEEP_ENTRY_WFE : Enters SLEEP mode via WFE instruction + * @arg PWRCU_SLEEP_ENTRY_WFI : Enters SLEEP mode via WFI instruction + * @retval None + ************************************************************************************************************/ +void PWRCU_Sleep(PWRCU_SLEEP_ENTRY_Enum SleepEntry) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_SLEEP_ENTRY(SleepEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= ~(u32)SLEEPDEEP_SET; + + if (SleepEntry == PWRCU_SLEEP_ENTRY_WFE) + { + /* Wait for event */ + __WFE(); + } + else + { + /* Wait for interrupt */ + __WFI(); + } +} + +/*********************************************************************************************************//** + * @brief Enter DEEP-SLEEP Mode 1. + * @param SleepEntry : Enters sleep mode instruction that is used to WFI or WFE. + * This parameter can be one of the following values: + * @arg PWRCU_SLEEP_ENTRY_WFE : Enters SLEEP mode via WFE instruction + * @arg PWRCU_SLEEP_ENTRY_WFI : Enters SLEEP mode via WFI instruction + * @retval None + ************************************************************************************************************/ +void PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_Enum SleepEntry) +{ + u32 uRTCStatus = 0; + u32 uADCStatus = 0; + + /* Check the parameters */ + Assert_Param(IS_PWRCU_SLEEP_ENTRY(SleepEntry)); + + uRTCStatus = BB_RTCEN; + uADCStatus = BB_ADCEN; + + BB_RTCEN = 1; + BB_ADCEN = 0; + + BB_DMOSON = 0; + BB_LDOOFF = 0; + + BB_RTCEN = uRTCStatus; + /* Sets SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SLEEPDEEP_SET; + + if (SleepEntry == PWRCU_SLEEP_ENTRY_WFE) + { + /* Wait for event */ + __WFE(); + } + else + { + /* Wait for interrupt */ + __WFI(); + } + BB_ADCEN = uADCStatus; +} + +/*********************************************************************************************************//** + * @brief Enter DEEP-SLEEP Mode 2. + * @param SleepEntry : Enters sleep mode instruction that is used to WFI or WFE. + * This parameter can be one of the following values: + * @arg PWRCU_SLEEP_ENTRY_WFE : Enters SLEEP mode via WFE instruction + * @arg PWRCU_SLEEP_ENTRY_WFI : Enters SLEEP mode via WFI instruction + * @retval None + ************************************************************************************************************/ +void PWRCU_DeepSleep2(PWRCU_SLEEP_ENTRY_Enum SleepEntry) +{ + u32 uRTCStatus = 0; + u32 uADCStatus = 0; + #if (!LIBCFG_PWRCU_LDO_LEGACY) + u32 uLDOStatus = 0; + #endif + + /* Check the parameters */ + Assert_Param(IS_PWRCU_SLEEP_ENTRY(SleepEntry)); + + uRTCStatus = BB_RTCEN; + uADCStatus = BB_ADCEN; + + BB_RTCEN = 1; + BB_ADCEN = 0; + + if (BB_DMOSSTS == 0) + { + BB_DMOSON = 0; + BB_DMOSON = 1; + } + BB_LDOOFF = 0; + + BB_RTCEN = uRTCStatus; + + #if (!LIBCFG_PWRCU_LDO_LEGACY) + uLDOStatus = HT_PWRCU->CR & ~LDOFTRM_MASK; + if (uLDOStatus >= PWRCU_LDO_OFFSET_ADD3P) + { + CKCU_PSRCWKUPCmd(ENABLE); + } + #endif + + /* Sets SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SLEEPDEEP_SET; + + if (SleepEntry == PWRCU_SLEEP_ENTRY_WFE) + { + /* Wait for event */ + __WFE(); + } + else + { + /* Wait for interrupt */ + __WFI(); + } + + #if (!LIBCFG_PWRCU_LDO_LEGACY) + if (uLDOStatus >= PWRCU_LDO_OFFSET_ADD3P) + { + PWRCU_SetLDOFTRM((PWRCU_LDOFTRM_Enum)uLDOStatus); + CKCU_PSRCWKUPCmd(DISABLE); + + if ((HT_CKCU->GCCR >> 9) & 1) + { + while (CKCU_GetClockReadyStatus(CKCU_FLAG_PLLRDY) != SET); + } + } + #endif + + BB_ADCEN = uADCStatus; +} + +/*********************************************************************************************************//** + * @brief Enter POWER-DOWN Mode. + * @retval None + ************************************************************************************************************/ +void PWRCU_PowerDown(void) +{ + u32 uRTCStatus = 0; + u32 uADCStatus = 0; + + uRTCStatus = BB_RTCEN; + uADCStatus = BB_ADCEN; + + BB_RTCEN = 1; + BB_ADCEN = 0; + + #if (LIBCFG_RTC_LSI_LOAD_TRIM) + { + static u8 isLSITrimLoaded = FALSE; + if (isLSITrimLoaded == FALSE) + { + u32 i = 9600; + isLSITrimLoaded = TRUE; + HT_RTC->CR &= ~(1UL << 2); + /* Insert a delay must > 1 CK_RTC */ + while (i--); + HT_RTC->CR |= (1UL << 2); + while ((HT_CKCU->GCSR & 0x20) == 0); + } + } + #endif + + BB_DMOSON = 0; + BB_LDOOFF = 1; + + BB_RTCEN = uRTCStatus; + + /* Sets SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SLEEPDEEP_SET; + + /* Enters power-down mode */ + __WFE(); + + BB_ADCEN = uADCStatus; +} + +#if (LIBCFG_PWRCU_LDO_LEGACY) +#else +/*********************************************************************************************************//** + * @brief Configure LDO output voltage fine trim. + * @param VolOffset: LDO default output voltage offset. + * This parameter can be one of following: + * @arg PWRCU_LDO_DEFAULT : default output voltage + * @arg PWRCU_LDO_OFFSET_DEC5P : default output voltage offset -5% + * @arg PWRCU_LDO_OFFSET_ADD3P : default output voltage offset +3% + * @arg PWRCU_LDO_OFFSET_ADD7P : default output voltage offset +7% + * @retval None + ************************************************************************************************************/ +void PWRCU_SetLDOFTRM(PWRCU_LDOFTRM_Enum VolOffset) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_LDOFTRM(VolOffset)); + + do { + HT_PWRCU->CR = (HT_PWRCU->CR & LDOFTRM_MASK) | VolOffset; + } while ((HT_PWRCU->CR & ~LDOFTRM_MASK) != VolOffset); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure LVD voltage level. + * @param Level: Low voltage detect level. + * This parameter can be one of the following: + * HT32F165x: + * @arg PWRCU_LVDS_2V7 : 2.7 V + * @arg PWRCU_LVDS_2V8 : 2.9 V + * @arg PWRCU_LVDS_2V9 : 2.9 V + * @arg PWRCU_LVDS_3V : 3.0 V + * @arg PWRCU_LVDS_3V1 : 3.1 V + * @arg PWRCU_LVDS_3V2 : 3.2 V + * @arg PWRCU_LVDS_3V4 : 3.4 V + * @arg PWRCU_LVDS_3V5 : 3.5 V + * HT32F123xx: + * @arg PWRCU_LVDS_2V25 : 2.25 V + * @arg PWRCU_LVDS_2V4 : 2.40 V + * @arg PWRCU_LVDS_2V55 : 2.55 V + * @arg PWRCU_LVDS_2V7 : 2.70 V + * @arg PWRCU_LVDS_2V85 : 2.85 V + * @arg PWRCU_LVDS_3V : 3.00 V + * @arg PWRCU_LVDS_3V15 : 3.15 V + * @arg PWRCU_LVDS_3V3 : 3.30 V + * HT32F12364: + * @arg PWRCU_LVDS_1V75 : 1.75 V + * @arg PWRCU_LVDS_1V95 : 1.95 V + * @arg PWRCU_LVDS_2V15 : 2.15 V + * @arg PWRCU_LVDS_2V35 : 2.35 V + * @arg PWRCU_LVDS_2V55 : 2.55 V + * @arg PWRCU_LVDS_2V75 : 2.75 V + * @arg PWRCU_LVDS_2V95 : 2.95 V + * @arg PWRCU_LVDS_3V15 : 3.15 V + * @retval None + ************************************************************************************************************/ +void PWRCU_SetLVDS(PWRCU_LVDS_Enum Level) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_LVDS(Level)); + + HT_PWRCU->LVDCSR = (HT_PWRCU->LVDCSR & LVDS_MASK) | Level; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable LVD function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_LVDCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + BB_LVDEN = NewState; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable BOD reset function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_BODCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + BB_BODEN = NewState; +} + +/*********************************************************************************************************//** + * @brief Select when the BOD occurs, the action for the cause Reset or Interrupt. + * @param Selection: BOD reset or interrupt selection. + * This parameter can be one of the following values: + * @arg PWRCU_BODRIS_RESET : Reset the whole chip + * @arg PWRCU_BODRIS_INT : Assert interrupt + * @retval None + ************************************************************************************************************/ +void PWRCU_BODRISConfig(PWRCU_BODRIS_Enum Selection) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_BODRIS(Selection)); + + BB_BODRIS = Selection; +} + +/*********************************************************************************************************//** + * @brief Return the flag status of LVD. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus PWRCU_GetLVDFlagStatus(void) +{ + return (FlagStatus)BB_LVDF; +} + +/*********************************************************************************************************//** + * @brief Return the flag status of BOD. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus PWRCU_GetBODFlagStatus(void) +{ + return (FlagStatus)BB_BODF; +} + +/*********************************************************************************************************//** + * @brief Return the DMOS status. + * @retval This function will return one of the following values: + * - PWRCU_DMOS_STS_ON : DMOS on + * - PWRCU_DMOS_STS_OFF : DMOS off + * - PWRCU_DMOS_STS_OFF_BY_BODRESET : DMOS off caused by brow out reset + ************************************************************************************************************/ +PWRCU_DMOSStatus PWRCU_GetDMOSStatus(void) +{ + u32 wDmosStatus = HT_PWRCU->CR & 0x8080; + + if (wDmosStatus == 0x0) + { + return PWRCU_DMOS_STS_OFF; + } + else if (wDmosStatus == 0x8080) + { + return PWRCU_DMOS_STS_ON; + } + else + { + return PWRCU_DMOS_STS_OFF_BY_BODRESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable DMOS function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_DMOSCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (BB_DMOSSTS == 0) + { + BB_DMOSON = 0; + } + + BB_DMOSON = NewState; +} + +#if (LIBCFG_PWRCU_LDO_LEGACY) +#else +/*********************************************************************************************************//** + * @brief Configure the LDO operation mode. + * @param Sel: Specify the LDO mode. + * This parameter can be one of the following values: + * @arg PWRCU_LDO_NORMAL : The LDO is operated in normal current mode + * @arg PWRCU_LDO_LOWCURRENT : The LDO is operated in low current mode + * @retval None + ************************************************************************************************************/ +void PWRCU_LDOConfig(PWRCU_LDOMODE_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_LDOMODE(Sel)); + + if (Sel == PWRCU_LDO_NORMAL) + { + BB_LDOLCM = 0; + } + else + { + BB_LDOLCM = 1; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Configure VDD18/VDD15 power good source. + * @param Sel: Specify VDD18/VDD15 power good source. + * This parameter can be one of the following values: + * @arg PWRCU_VRDYSC_BKISO : Vdd18/Vdd15 power good source come from BK_ISO bit in CKCU unit + * @arg PWRCU_VRDYSC_VPOR : Vdd18/Vdd15 power good source come from Vdd18/Vdd15 power on reset + * @retval None + ************************************************************************************************************/ +void PWRCU_VRDYSourceConfig(PWRCU_VRDYSC_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_VRDYSC(Sel)); + + BB_VRDYSC = Sel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the LVD interrupt wakeup function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_LVDIntWakeupConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + BB_LVDIWEN = NewState; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the LVD event wakeup function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_LVDEventWakeupConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + BB_LVDEWEN = NewState; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the external WAKEUP pin function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_WakeupPinCmd(ControlStatus NewState) +{ + u32 uRTCStatus = 0; + + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + uRTCStatus = BB_RTCEN; + + BB_RTCEN = 1; + + BB_WUPEN = NewState; + + BB_RTCEN = uRTCStatus; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the external WAKEUP pin interrupt function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_WakeupPinIntConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + BB_WUPIEN = NewState; +} + +#if (LIBCFG_PWRCU_HSI_READY_COUNTER) +/*********************************************************************************************************//** + * @brief Configure HSI ready counter bit length. + * @param BitLength: HSI ready counter bit length. + * This parameter can be one of following: + * @arg PWRCU_HSIRCBL_4 : 4 bits + * @arg PWRCU_HSIRCBL_5 : 5 bits + * @arg PWRCU_HSIRCBL_6 : 6 bits + * @arg PWRCU_HSIRCBL_7 : 7 bits (Default) + * @retval None + ************************************************************************************************************/ +void PWRCU_HSIReadyCounterBitLengthConfig(PWRCU_HSIRCBL_Enum BitLength) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_HSIRCBL(BitLength)); + + HT_PWRCU->HSIRCR = BitLength; +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rstcu.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rstcu.c new file mode 100644 index 00000000000..e4ac9f5b9d7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rstcu.c @@ -0,0 +1,142 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_rstcu.c + * @version $Rev:: 2787 $ + * @date $Date:: 2022-11-23 #$ + * @brief This file provides all the Reset Control Unit firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_rstcu.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup RSTCU RSTCU + * @brief RSTCU driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Functions RSTCU exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Check whether the specific global reset flag is set or not. + * @param RSTCU_RSTF: specify the reset flag. + * This parameter can be one of the following values: + * @arg RSTCU_FLAG_SYSRST : Get system reset flag + * @arg RSTCU_FLAG_EXTRST : Get external pin reset flag + * @arg RSTCU_FLAG_WDTRST : Get WDT reset flag + * @arg RSTCU_FLAG_PORST : Get power on reset flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus RSTCU_GetResetFlagStatus(RSTCU_RSTF_TypeDef RSTCU_RSTF) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_RSTCU_FLAG(RSTCU_RSTF)); + + tmp = (HT_RSTCU->GRSR & ((u32)0x1 << RSTCU_RSTF)); + if (tmp != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specific global reset flag. + * @param RSTCU_RSTF: specify the reset flag. + * This parameter can be one of the following values: + * @arg RSTCU_FLAG_SYSRST : Clear system reset flag + * @arg RSTCU_FLAG_EXTRST : Clear external pin reset flag + * @arg RSTCU_FLAG_WDTRST : Clear WDT reset flag + * @arg RSTCU_FLAG_PORST : Clear power on reset flag + * @retval None + ************************************************************************************************************/ +void RSTCU_ClearResetFlag(RSTCU_RSTF_TypeDef RSTCU_RSTF) +{ + /* Check the parameters */ + Assert_Param(IS_RSTCU_FLAG(RSTCU_RSTF)); + + HT_RSTCU->GRSR = (u32)0x1 << RSTCU_RSTF; /* Write 1 to clear */ +} + +/*********************************************************************************************************//** + * @brief Clear all of the global reset flag. + * @retval None + ************************************************************************************************************/ +void RSTCU_ClearAllResetFlag(void) +{ + HT_RSTCU->GRSR = (u32)0xF; /* Write 1 to clear */ +} + +/*********************************************************************************************************//** + * @brief Peripheral reset function. + * @param Reset: specify the peripheral clock enable bits. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RSTCU_PeripReset(RSTCU_PeripReset_TypeDef Reset, ControlStatus Cmd) +{ + u32 uAHBPRST; + u32 uAPBPRST0; + u32 uAPBPRST1; + + uAHBPRST = HT_RSTCU->AHBPRST; + uAPBPRST0 = HT_RSTCU->APBPRST0; + uAPBPRST1 = HT_RSTCU->APBPRST1; + + uAHBPRST &= ~(Reset.Reg[0]); + uAPBPRST0 &= ~(Reset.Reg[1]); + uAPBPRST1 &= ~(Reset.Reg[2]); + + if (Cmd != DISABLE) + { + uAHBPRST |= Reset.Reg[0]; + uAPBPRST0 |= Reset.Reg[1]; + uAPBPRST1 |= Reset.Reg[2]; + } + + HT_RSTCU->AHBPRST = uAHBPRST; + HT_RSTCU->APBPRST0 = uAPBPRST0; + HT_RSTCU->APBPRST1 = uAPBPRST1; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rtc.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rtc.c new file mode 100644 index 00000000000..6c8a2638a73 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_rtc.c @@ -0,0 +1,372 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_rtc.c + * @version $Rev:: 2233 $ + * @date $Date:: 2020-10-13 #$ + * @brief This file provides all the RTC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_rtc.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup RTC RTC + * @brief RTC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Private_Define RTC private definitions + * @{ + */ +#define RTC_CR_ADDR (HT_RTC_BASE + 0x008) +#define BB_RTCEN BitBand(RTC_CR_ADDR, 0) +#define BB_RTCSRC BitBand(RTC_CR_ADDR, 1) +#define BB_LSI_EN BitBand(RTC_CR_ADDR, 2) +#define BB_LSE_EN BitBand(RTC_CR_ADDR, 3) +#define BB_CMPCLR BitBand(RTC_CR_ADDR, 4) +#define BB_SOP BitBand(RTC_CR_ADDR, 5) +#define BB_ROEN BitBand(RTC_CR_ADDR, 16) +#define BB_ROES BitBand(RTC_CR_ADDR, 17) +#define BB_ROWM BitBand(RTC_CR_ADDR, 18) +#define BB_ROAP BitBand(RTC_CR_ADDR, 19) +#define BB_ROLF BitBand(RTC_CR_ADDR, 20) +#define RPRE_MASK (0xFFFFF0FF) + +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the RTC peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void RTC_DeInit(void) +{ + HT_RTC->CR = 0x00000004; + HT_RTC->CMP = 0x0; + HT_RTC->IWEN = 0x0; + HT_RTC->CR |= 0x00000005; + while (HT_RTC->CNT); + HT_RTC->CR = 0x00000F04; + /* Read the RTC_SR register to clear it */ + HT_RTC->SR; +} + +/*********************************************************************************************************//** + * @brief Select the RTC timer clock source. + * @param Source: specify the clock source of RTC and backup domain. + * @arg RTC_SRC_LSI : Low speed internal clock. + * @arg RTC_SRC_LSE : Low speed external clock. + * @retval None + ************************************************************************************************************/ +void RTC_ClockSourceConfig(RTC_SRC_Enum Source) +{ + Assert_Param(IS_RTC_SRC(Source)); + + BB_RTCSRC = Source; +} + +#if (LIBCFG_RTC_LSI_LOAD_TRIM) +/*********************************************************************************************************//** + * @brief Loads the LSI trim data. + * @retval None + ************************************************************************************************************/ +void RTC_LSILoadTrimData(void) +{ + u32 i = 9600; + + HT_RTC->CR &= ~(1UL << 2); + /* Insert a delay must > 1 CK_RTC */ + while (i--); + HT_RTC->CR |= (1UL << 2); + while ((HT_CKCU->GCSR & 0x20) == 0); +} +#endif + +/*********************************************************************************************************//** + * @brief Select the LSE startup mode. + * @param Mode: specify the LSE startup mode. + * This parameter can be one of the following values: + * @arg RTC_LSESM_NORMAL : Little power consumption but longer startup time. + * @arg RTC_LSESM_FAST : Shortly startup time but higher power consumption. + * @retval None + ************************************************************************************************************/ +void RTC_LSESMConfig(RTC_LSESM_Enum Mode) +{ + Assert_Param(IS_RTC_LSESM(Mode)); + + BB_SOP = Mode; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the LSE clock. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_LSECmd(ControlStatus NewState) +{ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == DISABLE) + { + BB_LSE_EN = 0; + while (HT_CKCU->GCSR & 0x10); + } + else + { + BB_LSE_EN = 1; + while ((HT_CKCU->GCSR & 0x10) == 0); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the compare match function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_CMPCLRCmd(ControlStatus NewState) +{ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + BB_CMPCLR = NewState; +} + +/*********************************************************************************************************//** + * @brief Configure the RTC prescaler. + * @param Psc: Value of RTC prescaler. + * This parameter can be one of following values: + * @arg RTC_RPRE_1 + * @arg RTC_RPRE_2 + * @arg RTC_RPRE_4 + * @arg RTC_RPRE_8 + * @arg RTC_RPRE_16 + * @arg RTC_RPRE_32 + * @arg RTC_RPRE_64 + * @arg RTC_RPRE_128 + * @arg RTC_RPRE_256 + * @arg RTC_RPRE_512 + * @arg RTC_RPRE_1024 + * @arg RTC_RPRE_2048 + * @arg RTC_RPRE_4096 + * @arg RTC_RPRE_8192 + * @arg RTC_RPRE_16384 + * @arg RTC_RPRE_32768 + * @retval None + ************************************************************************************************************/ +void RTC_SetPrescaler(RTC_RPRE_Enum Psc) +{ + Assert_Param(IS_RTC_PSC(Psc)); + + HT_RTC->CR = (HT_RTC->CR & RPRE_MASK) | Psc; +} + +/*********************************************************************************************************//** + * @brief Return the RTC prescaler setting. + * @retval The prescaler value. It is powered by 2 and max.is 32768. + ************************************************************************************************************/ +u16 RTC_GetPrescaler(void) +{ + u32 prescaler; + + prescaler = HT_RTC->CR >> 8; + + return ((u16)0x1 << prescaler); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the RTC timer. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_Cmd(ControlStatus NewState) +{ + BB_RTCEN = NewState; +} + +/*********************************************************************************************************//** + * @brief Return the counter value. + * @retval Between 0x0 ~ 0xFFFFFFFF. + ************************************************************************************************************/ +u32 RTC_GetCounter(void) +{ + /* !!! NOTICE !!! + A 1/CK_RTC delay time is required if you read the RTC CNT count immediately when the RTC compare match + occurred (in the RTC ISR or the system is wakeup from the DeepSleep1/2). + The CK_RTC can be configured from the LSI or LSE. + */ + return (HT_RTC->CNT); +} + +/*********************************************************************************************************//** + * @brief Configure the compare match value. + * @param Compare: Between 0x0 ~ 0xFFFFFFFF + * @retval None + ************************************************************************************************************/ +void RTC_SetCompare(u32 Compare) +{ + HT_RTC->CMP = Compare; +} + +/*********************************************************************************************************//** + * @brief Return the compare match value. + * @retval Between 0x0 ~ 0xFFFFFFFF. + ************************************************************************************************************/ +u32 RTC_GetCompare(void) +{ + return (HT_RTC->CMP); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified wakeup source. + * @param RTC_WAKEUP Selection of Wakeup source. + * This parameter can be any combination of the following values: + * @arg RTC_WAKEUP_CSEC : Waken up by counter counting. + * @arg RTC_WAKEUP_CM : Waken up by counter compare match with CMP register. + * @arg RTC_WAKEUP_OV : Waken up by counter overflow. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_WakeupConfig(u32 RTC_WAKEUP, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_RTC_WAKEUP(RTC_WAKEUP)); + + if (NewState != DISABLE) + { + HT_RTC->IWEN |= RTC_WAKEUP; + } + else + { + HT_RTC->IWEN &= ~RTC_WAKEUP; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified interrupt source. + * @param RTC_INT: Selection of Wakeup source. + * This parameter can be any combination of the following values: + * @arg RTC_INT_CSEC : Assert interrupt at counter counting + * @arg RTC_INT_CM : Assert interrupt at counter compare match with CMP register + * @arg RTC_INT_OV : Assert interrupt at counter overflow + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_IntConfig(u32 RTC_INT, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_RTC_INT(RTC_INT)); + + if (NewState != DISABLE) + { + HT_RTC->IWEN |= RTC_INT; + } + else + { + HT_RTC->IWEN &= ~RTC_INT; + } +} + +/*********************************************************************************************************//** + * @brief Return the RTC flags. + * @retval RTC_STS register value. + * This parameter can be any combination of following: + * - 0x0 : No flag set + * - 0x1 : Count flag + * - 0x2 : Match flag + * - 0x4 : Overflow flag + * @note RTC_SR is read clear. + ************************************************************************************************************/ +u8 RTC_GetFlagStatus(void) +{ + return ((u8)HT_RTC->SR); +} + +/*********************************************************************************************************//** + * @brief Configure the RTC output function. + * @param WMode: specify the RTC output waveform mode + * This parameter can be one of the following values: + * @arg RTC_ROWM_PULSE : Pulse mode + * @arg RTC_ROWM_LEVEL : Level mode + * @param EventSel: specify the RTC output event selection + * This parameter can be one of the following values: + * @arg RTC_ROES_MATCH : Compare match selected + * @arg RTC_ROES_SECOND : Second clock selected + * @param Pol: specify the RTC output active polarity + * This parameter can be one of the following values: + * @arg RTC_ROAP_HIGH : Active level is high + * @arg RTC_ROAP_LOW : Active level is low + * @note This function will disable RTC output first. + ************************************************************************************************************/ +void RTC_OutConfig(RTC_ROWM_Enum WMode, RTC_ROES_Enum EventSel, RTC_ROAP_Enum Pol) +{ + Assert_Param(IS_RTC_ROWM(WMode)); + Assert_Param(IS_RTC_ROES(EventSel)); + Assert_Param(IS_RTC_ROAP(Pol)); + + BB_ROEN = 0; + BB_ROWM = WMode; + BB_ROES = EventSel; + BB_ROAP = Pol; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the RTC output. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_OutCmd(ControlStatus NewState) +{ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + BB_ROEN = NewState; +} + +/*********************************************************************************************************//** + * @brief Return the RTCOUT level mode flag. + * @retval SET or RESET + * @note Reads RTC_CR action will clear ROLF flag. + ************************************************************************************************************/ +FlagStatus RTC_GetOutStatus(void) +{ + return (FlagStatus)BB_ROLF; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sci.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sci.c new file mode 100644 index 00000000000..f3c826ae156 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sci.c @@ -0,0 +1,444 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_sci.c + * @version $Rev:: 2797 $ + * @date $Date:: 2022-11-28 #$ + * @brief This file provides all the SCI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_sci.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup SCI SCI + * @brief SCI driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Private_Define SCI private definitions + * @{ + */ +/* SCI ENSCI mask */ +#define CR_ENSCI_SET ((u32)0x00000020) +#define CR_ENSCI_RESET ((u32)0xFFFFFFDF) + +/* SCI WTEN mask */ +#define CR_WTEN_SET ((u32)0x00000004) +#define CR_WTEN_RESET ((u32)0xFFFFFFFB) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Functions SCI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the SCI peripheral registers to their default reset values. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @retval None + ************************************************************************************************************/ +void SCI_DeInit(HT_SCI_TypeDef* SCIx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + if (SCIx == HT_SCI0) + { + RSTCUReset.Bit.SCI0 = 1; + } + #if (LIBCFG_SCI1) + else + { + RSTCUReset.Bit.SCI1 = 1; + } + #endif + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the SCI peripheral according to the specified parameters in the SCI_InitStruct. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_InitStruct: pointer to a SCI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SCI_Init(HT_SCI_TypeDef* SCIx, SCI_InitTypeDef* SCI_InitStruct) +{ + u32 tmpreg; + + /* Check the parameters */ + Assert_Param(IS_SCI_MODE(SCI_InitStruct->SCI_Mode)); + Assert_Param(IS_SCI_RETRY(SCI_InitStruct->SCI_Retry)); + Assert_Param(IS_SCI_CONVENTION(SCI_InitStruct->SCI_Convention)); + Assert_Param(IS_SCI_CARD_POLARITY(SCI_InitStruct->SCI_CardPolarity)); + Assert_Param(IS_SCI_CLOCK_PRESCALER(SCI_InitStruct->SCI_ClockPrescale)); + + + /*------------------------- SCI Control Register Configuration -------------------------------------------*/ + tmpreg = SCIx->CR; + tmpreg &= 0xFFFFFFA4; + + tmpreg |= SCI_InitStruct->SCI_Mode | SCI_InitStruct->SCI_Retry | SCI_InitStruct->SCI_Convention | + SCI_InitStruct->SCI_CardPolarity; + + SCIx->CR = tmpreg; + + /*------------------------- SCI Prescaler Register Configuration -----------------------------------------*/ + SCIx->PSC = SCI_InitStruct->SCI_ClockPrescale; +} + +/*********************************************************************************************************//** + * @brief Initialize the SCI peripheral according to the specified parameters in the SCI_InitStruct. + * @param SCI_InitStruct: pointer to a SCI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SCI_StructInit(SCI_InitTypeDef* SCI_InitStruct) +{ + /* Initialize the SCI_Mode member */ + SCI_InitStruct->SCI_Mode = SCI_MODE_MANUAL; + + /* Initialize the SCI_Retry member */ + SCI_InitStruct->SCI_Retry = SCI_RETRY_NO; + + /* Initialize the SCI_Convention member */ + SCI_InitStruct->SCI_Convention = SCI_CONVENTION_DIRECT; + + /* Initialize the SCI_CardPolarity member */ + SCI_InitStruct->SCI_CardPolarity = SCI_CARDPOLARITY_LOW; + + /* Initialize the SCI_ClockPrescale member */ + SCI_InitStruct->SCI_ClockPrescale = SCI_CLKPRESCALER_1; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SCI peripheral. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_Cmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->CR |= CR_ENSCI_SET; + } + else + { + SCIx->CR &= CR_ENSCI_RESET; + } +} + +/*********************************************************************************************************//** + * @brief This function is used to configure the Elementary Time Unit. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_ETU: specify the SCI Elementary Time Unit. + * @param SCI_Compensation: Enable or Disable the Compensation mode. + * This parameter can be one of the following values: + * @arg SCI_COMPENSATION_ENABLE : Compensation mode enabled + * @arg SCI_COMPENSATION_DISABLE : Compensation mode disabled + * @retval None + ************************************************************************************************************/ +void SCI_ETUConfig(HT_SCI_TypeDef* SCIx, u32 SCI_ETU, u32 SCI_Compensation) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_ETU(SCI_ETU)); + Assert_Param(IS_SCI_ETU_COMPENSATION(SCI_Compensation)); + + SCIx->ETU = SCI_ETU | SCI_Compensation; +} + +/*********************************************************************************************************//** + * @brief This function is used to set the value of SCI GuardTime. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_GuardTime: specify the value of SCI GuardTime value. + * @retval None + ************************************************************************************************************/ +void SCI_SetGuardTimeValue(HT_SCI_TypeDef* SCIx, u16 SCI_GuardTime) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_GUARDTIME(SCI_GuardTime)); + + SCIx->GT = SCI_GuardTime; +} + +/*********************************************************************************************************//** + * @brief This function is used to set the value of SCI Waiting Time. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_WaitingTime: specify the value of SCI Waiting Time value. + * @retval None + ************************************************************************************************************/ +void SCI_SetWaitingTimeValue(HT_SCI_TypeDef* SCIx, u32 SCI_WaitingTime) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_WAITING_TIME(SCI_WaitingTime)); + + SCIx->WT = SCI_WaitingTime; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the Waiting Time Counter. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_WaitingTimeCounterCmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->CR |= CR_WTEN_SET; + } + else + { + SCIx->CR &= CR_WTEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Sends a data byte through the SCI peripheral. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Data: byte to be transmitted. + * @retval None + ************************************************************************************************************/ +void SCI_SendData(HT_SCI_TypeDef* SCIx, u8 SCI_Data) +{ + SCIx->TXB = SCI_Data; +} + +/*********************************************************************************************************//** + * @brief Returns the received data through the SCI peripheral. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @retval The value of the received data. + ************************************************************************************************************/ +u8 SCI_ReceiveData(HT_SCI_TypeDef* SCIx) +{ + return ((u8)SCIx->RXB); +} + +/*********************************************************************************************************//** + * @brief Determines the SCI output clock signal is driven by hardware or software. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_CLKMode: specify the SCI clock pin mode. + * This parameter can be one of the following values: + * @arg SCI_CLK_SOFTWARE : SCI output clock is controlled by software + * @arg SCI_CLK_HARDWARE : SCI output clock is controlled by hardware + * @retval None + ************************************************************************************************************/ +void SCI_ClockModeConfig(HT_SCI_TypeDef* SCIx, u32 SCI_CLKMode) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_CLK_MODE(SCI_CLKMode)); + + if (SCI_CLKMode != SCI_CLK_SOFTWARE) + { + SCIx->CCR |= SCI_CLK_HARDWARE; + } + else + { + SCIx->CCR &= SCI_CLK_SOFTWARE; + } +} + +/*********************************************************************************************************//** + * @brief Output the SCI clock pin low or high by software. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_CLK: specify if the SCI clock pin to be high or low. + * This parameter can be one of the following values: + * @arg SCI_CLK_HIGH : Software drive SCI output clock high + * @arg SCI_CLK_LOW : Software drive SCI output clock low + * @retval None + ************************************************************************************************************/ +void SCI_SoftwareClockCmd(HT_SCI_TypeDef* SCIx, u32 SCI_CLK) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_CLK(SCI_CLK)); + + if (SCI_CLK != SCI_CLK_LOW) + { + SCIx->CCR |= SCI_CLK_HIGH; + } + else + { + SCIx->CCR &= SCI_CLK_LOW; + } +} + +/*********************************************************************************************************//** + * @brief Output the SCI DIO pin low or high by software. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_DIO: specify if the SCI DIO pin to be high or low. + * This parameter can be one of the following values: + * @arg SCI_DIO_HIGH : Drive SCI DIO signal high + * @arg SCI_DIO_LOW : Drive SCI DIO signal low + * @retval None + ************************************************************************************************************/ +void SCI_OutputDIO(HT_SCI_TypeDef* SCIx, u32 SCI_DIO) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_DIO(SCI_DIO)); + + if (SCI_DIO != SCI_DIO_LOW) + { + SCIx->CCR |= SCI_DIO_HIGH; + } + else + { + SCIx->CCR &= SCI_DIO_LOW; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SCI interrupt. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Int: specify the SCI interrupt source to be enabled or disable. + * This parameter can be any combination of the following values: + * @arg SCI_INT_PAR : SCI parity error interrupt + * @arg SCI_INT_RXC : SCI received character interrupt + * @arg SCI_INT_TXC : SCI transmitted character interrupt + * @arg SCI_INT_WT : SCI waiting timer interrupt + * @arg SCI_INT_CARD : SCI card insert/remove interrupt + * @arg SCI_INT_TXBE : SCI transmit buffer empty interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_IntConfig(HT_SCI_TypeDef* SCIx, u32 SCI_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_INT(SCI_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->IER |= SCI_Int; + } + else + { + SCIx->IER &= ~SCI_Int; + } +} + +/*********************************************************************************************************//** + * @brief Get the status of specified SCI flag. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg SCI_FLAG_PAR : SCI parity error flag + * @arg SCI_FLAG_RXC : SCI received character flag + * @arg SCI_FLAG_TXC : SCI transmitted character flag + * @arg SCI_FLAG_WT : SCI waiting timer flag + * @arg SCI_FLAG_CARD : SCI card insert/remove flag + * @arg SCI_FLAG_TXBE : SCI transmit buffer empty flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus SCI_GetFlagStatus(HT_SCI_TypeDef* SCIx, u32 SCI_Flag) +{ + u32 statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + Assert_Param(IS_SCI_FLAG(SCI_Flag)); + + statusreg = SCIx->SR; + + if ((statusreg & SCI_Flag) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Clears the flag status of specified SCI flag. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Flag: specify the flag to be cleared. + * This parameter can be one of the following values: + * @arg SCI_FLAG_PAR : SCI parity error flag + * @arg SCI_FLAG_TXC : SCI transmitted character flag + * @arg SCI_FLAG_WT : SCI waiting timer flag + * @retval None + ************************************************************************************************************/ +void SCI_ClearFlag(HT_SCI_TypeDef* SCIx, u32 SCI_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_CLEAR_FLAG(SCI_Flag)); + + if (SCI_Flag != SCI_FLAG_WT) + { + SCIx->SR &= ~SCI_Flag; + } + else + { + SCIx->CR &= CR_WTEN_RESET; + SCIx->CR |= CR_WTEN_SET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or disables the SCI PDMA interface. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_PDMAREQ: specify the SCI PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SCI_PDMAREQ_TX : Tx PDMA transfer request + * @arg SCI_PDMAREQ_RX : Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_PDMACmd(HT_SCI_TypeDef* SCIx, u32 SCI_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_PDMA_REQ(SCI_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->CR |= SCI_PDMAREQ; + } + else + { + SCIx->CR &= ~SCI_PDMAREQ; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sctm.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sctm.c new file mode 100644 index 00000000000..b824c72b168 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sctm.c @@ -0,0 +1,2 @@ +The SCTM, PWM, GPTM, and MCTM timer have similar architecture. They use the same driver, +"ht32fxxxxx_tm.c/.h" to save the code size. For those timers, please refet to the TM driver/example. diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sdio.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sdio.c new file mode 100644 index 00000000000..f596560451a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_sdio.c @@ -0,0 +1,355 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_sdio.c + * @version $Rev:: 2459 $ + * @date $Date:: 2021-08-13 #$ + * @brief This file provides all the SDIO firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_sdio.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup SDIO SDIO + * @brief SDIO driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Functions SDIO exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the SDIO peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void SDIO_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.SDIO = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the SDIO peripheral according to the specified parameters in the SDIO_InitStruct. + * @param SDIO_InitStruct: pointer to a SDIO_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) +{ + u32 t; + + /* Check the parameters */ + Assert_Param(IS_SDIO_CLOC_DIV(SDIO_InitStruct->SDIO_ClockDiv)); + Assert_Param(IS_SDIO_CLOCK_PERIOD(SDIO_InitStruct->SDIO_ClockPeriod)); + Assert_Param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); + Assert_Param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); + Assert_Param(IS_SDIO_BUS_MODE(SDIO_InitStruct->SDIO_BusMode)); + + /* Disable the SDIO clock and wait for a while */ + SDIO_ClockCmd(DISABLE); + for (t = 500; t > 0; t--); + + /* Configure SDIO bus and clock */ + HT_SDIO->CR = SDIO_InitStruct->SDIO_BusWide | SDIO_InitStruct->SDIO_BusMode; + + HT_SDIO->CLKCR = SDIO_InitStruct->SDIO_ClockPeriod | SDIO_InitStruct->SDIO_ClockPowerSave | + ((SDIO_InitStruct->SDIO_ClockDiv - 1) << 8); + + /* Enable SDIO bus clock */ + SDIO_ClockCmd(ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or disable the SDIO Clock. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SDIO_ClockCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + BitBand((u32)&HT_SDIO->CLKCR, 2) = Cmd; + } + else + { + BitBand((u32)&HT_SDIO->CLKCR, 2) = Cmd; + } +} + +/*********************************************************************************************************//** + * @brief Initialize the SDIO command according to the specified parameters in the SDIO_CmdInitStruct. + * @param SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); + Assert_Param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); + Assert_Param(IS_SDIO_DATA_PRESENT(SDIO_CmdInitStruct->SDIO_DatPresent)); + Assert_Param(IS_SDIO_CMD_IDX_CHK(SDIO_CmdInitStruct->SDIO_CmdIdxChk)); + Assert_Param(IS_SDIO_CMD_CRC_CHK(SDIO_CmdInitStruct->SDIO_CmdCrcChk)); + + HT_SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + + HT_SDIO->CMD = SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response | + SDIO_CmdInitStruct->SDIO_DatPresent | SDIO_CmdInitStruct->SDIO_CmdIdxChk | + SDIO_CmdInitStruct->SDIO_CmdCrcChk; +} + +/*********************************************************************************************************//** + * @brief Return response received from the card for the last command. + * @param SDIO_RESP: Specify the SDIO response register. + * This parameter can be one of the following values: + * @arg SDIO_RESP1 : Response Register 1 + * @arg SDIO_RESP2 : Response Register 2 + * @arg SDIO_RESP3 : Response Register 3 + * @arg SDIO_RESP4 : Response Register 4 + * @retval The Corresponding response register value. + ************************************************************************************************************/ +u32 SDIO_GetResponse(u32 SDIO_RESP) +{ + /* Check the parameters */ + Assert_Param(IS_SDIO_RESP(SDIO_RESP)); + + return(rw((u32)&HT_SDIO->RESP0 + SDIO_RESP)); +} + +/*********************************************************************************************************//** + * @brief Initialize the SDIO data path according to the specified parameters in the SDIO_DataInitStruct. + * @param SDIO_DataInitStruct: pointer to a SDIO_DataInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_SDIO_DATA_BLOCK_COUNT(SDIO_DataInitStruct->SDIO_DataBlockCount)); + Assert_Param(IS_SDIO_DATA_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); + Assert_Param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); + Assert_Param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); + Assert_Param(IS_SDIO_DATA_TIMEOUT(SDIO_DataInitStruct->SDIO_DataTimeOut)); + + /* configure DPSM */ + RESET_DPSM(); + HT_SDIO->BLKCNT = SDIO_DataInitStruct->SDIO_DataBlockCount; + HT_SDIO->BLKSIZE = SDIO_DataInitStruct->SDIO_DataBlockSize; + HT_SDIO->TMR = SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_TransferDir; + HT_SDIO->TMOCR = SDIO_DataInitStruct->SDIO_DataTimeOut; +} + +/*********************************************************************************************************//** + * @brief Read one data word from FIFO. + * @return Data received + ************************************************************************************************************/ +u32 SDIO_ReadData(void) +{ + return HT_SDIO->DR; +} + +/*********************************************************************************************************//** + * @brief Write one data word to FIFO. + * @param Data: 32-bit data word to write. + * @retval None + ************************************************************************************************************/ +void SDIO_WriteData(u32 Data) +{ + HT_SDIO->DR = Data; +} + +/*********************************************************************************************************//** + * @brief Return the number of words left to be written to or read from FIFO. + * @return Remaining number of words. + ************************************************************************************************************/ +u32 SDIO_GetFIFOCount(void) +{ + return (HT_SDIO->PSR >> 20); +} + +/*********************************************************************************************************//** + * @brief Enable the SDIO's flag. + * @param SDIO_FLAG: specify the flag to enable. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CMD_SEND : + * @arg SDIO_FLAG_TRANS_END : + * @arg SDIO_FLAG_BUF_OVERFLOW : + * @arg SDIO_FLAG_BUF_UNDERFLOW : + * @arg SDIO_FLAG_BUF_HALF : + * @arg SDIO_FLAG_BUF_FULL : + * @arg SDIO_FLAG_BUF_EMPTY : + * @arg SDIO_FLAG_CMD_TIMEOUT : + * @arg SDIO_FLAG_CMD_CRCERR : + * @arg SDIO_FLAG_CMD_IDXERR : + * @arg SDIO_FLAG_DATA_TIMEOUT : + * @arg SDIO_FLAG_DATA_CRCERR : + * @arg SDIO_FLAG_CARD_INT : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SDIO_FlagConfig(u32 SDIO_FLAG, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SDIO_FLAG(SDIO_FLAG)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_SDIO->SER |= (SDIO_FLAG); + } + else + { + HT_SDIO->SER &= ~(SDIO_FLAG); + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified SDIO flag is set or not. + * @param SDIO_FLAG: specify the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CMD_SEND : + * @arg SDIO_FLAG_TRANS_END : + * @arg SDIO_FLAG_BUF_OVERFLOW : + * @arg SDIO_FLAG_BUF_UNDERFLOW : + * @arg SDIO_FLAG_BUF_HALF : + * @arg SDIO_FLAG_BUF_FULL : + * @arg SDIO_FLAG_BUF_EMPTY : + * @arg SDIO_FLAG_CMD_TIMEOUT : + * @arg SDIO_FLAG_CMD_CRCERR : + * @arg SDIO_FLAG_CMD_IDXERR : + * @arg SDIO_FLAG_DATA_TIMEOUT : + * @arg SDIO_FLAG_DATA_CRCERR : + * @arg SDIO_FLAG_CARD_INT : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_SDIO_FLAG(SDIO_FLAG)); + + if (HT_SDIO->SR & (SDIO_FLAG)) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the SDIO's pending flags. + * @param SDIO_FLAG: specify the flag to clear. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CMD_SEND : + * @arg SDIO_FLAG_TRANS_END : + * @arg SDIO_FLAG_BUF_OVERFLOW : + * @arg SDIO_FLAG_BUF_UNDERFLOW : + * @arg SDIO_FLAG_BUF_HALF : + * @arg SDIO_FLAG_BUF_FULL : + * @arg SDIO_FLAG_BUF_EMPTY : + * @arg SDIO_FLAG_ERR : + * @arg SDIO_FLAG_CMD_TIMEOUT : + * @arg SDIO_FLAG_CMD_CRCERR : + * @arg SDIO_FLAG_CMD_ENDERR : + * @arg SDIO_FLAG_CMD_IDXERR : + * @arg SDIO_FLAG_DATA_TIMEOUT : + * @arg SDIO_FLAG_DATA_CRCERR : + * @arg SDIO_FLAG_DATA_ENDERR : + * @arg SDIO_FLAG_CARD_INT : + * @arg SDIO_FLAG_DAT_ERR : + * @arg SDIO_FLAG_CMD_ERR : + * @retval SET or RESET + ************************************************************************************************************/ +void SDIO_ClearFlag(u32 SDIO_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_SDIO_FLAG(SDIO_FLAG)); + + HT_SDIO->SR = (SDIO_FLAG); + + if (SDIO_FLAG & SDIO_FLAG_BUF_OVERFLOW) + { + HT_SDIO->SER &= ~(SDIO_FLAG_BUF_OVERFLOW); + HT_SDIO->SER |= (SDIO_FLAG_BUF_OVERFLOW); + } + if (SDIO_FLAG & SDIO_FLAG_BUF_UNDERFLOW) + { + HT_SDIO->SER &= ~(SDIO_FLAG_BUF_UNDERFLOW); + HT_SDIO->SER |= (SDIO_FLAG_BUF_UNDERFLOW); + } +} + +/*********************************************************************************************************//** + * @brief Clear the SDIO's pending flags. + * @param SDIO_INT: specify the flag to clear. + * This parameter can be one of the following values: + * @arg SDIO_INT_CMD_SEND : + * @arg SDIO_INT_TRANS_END : + * @arg SDIO_INT_BUF_OVERFLOW : + * @arg SDIO_INT_BUF_UNDERFLOW : + * @arg SDIO_INT_BUF_HALF : + * @arg SDIO_INT_BUF_FULL : + * @arg SDIO_INT_BUF_EMPTY : + * @arg SDIO_INT_CMD_TIMEOUT : + * @arg SDIO_INT_CMD_CRCERR : + * @arg SDIO_INT_CMD_IDXERR : + * @arg SDIO_INT_DATA_TIMEOUT : + * @arg SDIO_INT_DATA_CRCERR : + * @arg SDIO_INT_CARD_INT : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval SET or RESET + ************************************************************************************************************/ +void SDIO_IntConfig(u32 SDIO_INT, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SDIO_INT(SDIO_INT)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_SDIO->IER |= (SDIO_INT); + } + else + { + HT_SDIO->IER &= ~(SDIO_INT); + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_spi.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_spi.c new file mode 100644 index 00000000000..c0e8face8c5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_spi.c @@ -0,0 +1,623 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_spi.c + * @version $Rev:: 2797 $ + * @date $Date:: 2022-11-28 #$ + * @brief This file provides all the SPI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_spi.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Private_Define SPI private definitions + * @{ + */ +/* SPI SPIEN Mask */ +#define CR0_SPIEN_SET (u32)0x00000001 +#define CR0_SPIEN_RESET (u32)0xFFFFFFFE + +/* SPI SELOEN Mask */ +#define CR0_SELOEN_SET (u32)0x00000008 +#define CR0_SELOEN_RESET (u32)0xFFFFFFF7 + +/* SPI SPI DUALEN Mask */ +#define CR0_DUALEN_SET (u32)0x00000040 +#define CR0_DUALEN_RESET (u32)0xFFFFFFBF + +/* SPI SPI GUADTEN Mask */ +#define CR0_GUADTEN_SET (u32)0x00000080 +#define CR0_GUADTEN_RESET (u32)0xFFFFFF7F + +/* SPI FIFOEN Mask */ +#define FCR_FIFOEN_SET (u32)0x00000400 +#define FCR_FIFOEN_RESET (u32)0xFFFFFBFF + +/* SPI DFL Mask */ +#define CR1_DFL_MASK (u32)0x0000000F + +/* SPI FIFO Mask */ +#define FCR_FIFO_MASK (u32)0x0000000F +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the SPI peripheral registers to their default reset values. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @retval None + ************************************************************************************************************/ +void SPI_DeInit(HT_SPI_TypeDef* SPIx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + + if (SPIx == HT_SPI0) + { + RSTCUReset.Bit.SPI0 = 1; + } + else if (SPIx == HT_SPI1) + { + RSTCUReset.Bit.SPI1 = 1; + } + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the SPIx peripheral according to the specified parameters in the SPI_InitStruct. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SPI_Init(HT_SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + Assert_Param(IS_SPI_FIFO_SET(SPI_InitStruct->SPI_FIFO)); + Assert_Param(IS_SPI_DATALENGTH(SPI_InitStruct->SPI_DataLength)); + Assert_Param(IS_SPI_SEL_MODE(SPI_InitStruct->SPI_SELMode)); + Assert_Param(IS_SPI_SEL_POLARITY(SPI_InitStruct->SPI_SELPolarity)); + Assert_Param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + Assert_Param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + Assert_Param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + Assert_Param(IS_SPI_FIFO_LEVEL(SPI_InitStruct->SPI_RxFIFOTriggerLevel)); + Assert_Param(IS_SPI_FIFO_LEVEL(SPI_InitStruct->SPI_TxFIFOTriggerLevel)); + Assert_Param(IS_SPI_CLOCK_PRESCALER(SPI_InitStruct->SPI_ClockPrescaler)); + + /*---------------------------- SPIx Control Register 2 Configuration -------------------------------------*/ + tmp = SPI_InitStruct->SPI_CPOL; + if (tmp == SPI_CPOL_LOW) + { + tmp |= (0x100 << SPI_InitStruct->SPI_CPHA); + } + else + { + tmp |= (0x200 >> SPI_InitStruct->SPI_CPHA); + } + + SPIx->CR1 = SPI_InitStruct->SPI_Mode | SPI_InitStruct->SPI_DataLength | + SPI_InitStruct->SPI_SELMode | SPI_InitStruct->SPI_SELPolarity | + SPI_InitStruct->SPI_FirstBit | tmp; + + /*---------------------------- SPIx FIFO Control Register Configuration ----------------------------------*/ + SPIx->FCR = SPI_InitStruct->SPI_FIFO | SPI_InitStruct->SPI_TxFIFOTriggerLevel | + (SPI_InitStruct->SPI_RxFIFOTriggerLevel << 4); + + /*---------------------------- SPIx Clock Prescaler Register Configuration -------------------------------*/ + #if (LIBCFG_SPI_CLK_PRE_V01) + SPIx->CPR = (SPI_InitStruct->SPI_ClockPrescaler - 1); + #else + SPIx->CPR = (SPI_InitStruct->SPI_ClockPrescaler / 2) - 1; + #endif +} + +/*********************************************************************************************************//** + * @brief Fill each SPI_InitStruct member with its default value. + * @param SPI_InitStruct: pointer to an SPI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ + /* Initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_SLAVE; + + /* Initialize the SPI_FIFO member */ + SPI_InitStruct->SPI_FIFO = SPI_FIFO_DISABLE; + + /* Initialize the SPI_DataLength member */ + SPI_InitStruct->SPI_DataLength = SPI_DATALENGTH_16; + + /* Initialize the SPI_SELMode member */ + SPI_InitStruct->SPI_SELMode = SPI_SEL_SOFTWARE; + + /* Initialize the SPI_SELPolarity member */ + SPI_InitStruct->SPI_SELPolarity = SPI_SELPOLARITY_LOW; + + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_LOW; + + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_FIRST; + + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FIRSTBIT_MSB; + + /* Initialize the SPI_RxFIFOTriggerLevel member */ + SPI_InitStruct->SPI_RxFIFOTriggerLevel = 0; + + /* Initialize the SPI_TxFIFOTriggerLevel member */ + SPI_InitStruct->SPI_TxFIFOTriggerLevel = 0; + + /* Initialize the SPI_ClockPrescaler member */ + SPI_InitStruct->SPI_ClockPrescaler = 2; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SPI peripheral. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_Cmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR0 |= CR0_SPIEN_SET; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR0 &= CR0_SPIEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SEL output for the specified SPI peripheral. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_SELOutputCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->CR0 |= CR0_SELOEN_SET; + } + else + { + SPIx->CR0 &= CR0_SELOEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable SPI FIFO. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_FIFOCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->FCR |= FCR_FIFOEN_SET; + } + else + { + SPIx->FCR &= FCR_FIFOEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Configure the data length for the selected SPI. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_DataLength: specify data length of the SPI. + * @retval None + ************************************************************************************************************/ +void SPI_SetDataLength(HT_SPI_TypeDef* SPIx, u16 SPI_DataLength) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_DATALENGTH(SPI_DataLength)); + + /* Clear DFL[3:0] in CR1 */ + SPIx->CR1 &= (u32)~CR1_DFL_MASK; + + /* Set new DFL[3:0] in CR1 */ + SPIx->CR1 |= SPI_DataLength; +} + +/*********************************************************************************************************//** + * @brief SEL pin is configured to be driven by hardware or software. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_SEL: specify the SPI SEL pin mode. + * This parameter can be one of the following values: + * @arg SPI_SEL_HARDWARE : SEL is driven by hardware + * @arg SPI_SEL_SOFTWARE : SEL is driven by software + * @retval None + ************************************************************************************************************/ +void SPI_SELModeConfig(HT_SPI_TypeDef* SPIx, u32 SPI_SEL) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_SEL_MODE(SPI_SEL)); + + if (SPI_SEL != SPI_SEL_SOFTWARE) + { + SPIx->CR1 |= SPI_SEL_HARDWARE; + } + else + { + SPIx->CR1 &= ~SPI_SEL_HARDWARE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the SEL state by software. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_SoftwareSEL: specify if the SPI SEL to be active or inactive. + * This parameter can be one of the following values: + * @arg SPI_SEL_ACTIVE : activate SEL signal + * @arg SPI_SEL_INACTIVE : deactivate SEL signal + * @retval None + ************************************************************************************************************/ +void SPI_SoftwareSELCmd(HT_SPI_TypeDef* SPIx, u32 SPI_SoftwareSEL) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_SOFTWARE_SEL(SPI_SoftwareSEL)); + + if (SPI_SoftwareSEL != SPI_SEL_INACTIVE) + { + SPIx->CR0 |= SPI_SEL_ACTIVE; + } + else + { + SPIx->CR0 &= SPI_SEL_INACTIVE; + } +} + +/*********************************************************************************************************//** + * @brief Send a data through the SPIx peripheral. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Data: the data to be transmitted. + * @retval None + ************************************************************************************************************/ +void SPI_SendData(HT_SPI_TypeDef* SPIx, SPI_DataTypeDef SPI_Data) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_DATA(SPI_Data)); + + SPIx->DR = SPI_Data; +} + +/*********************************************************************************************************//** + * @brief Return the received data through the SPIx peripheral + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @retval The value of the received data. + ************************************************************************************************************/ +SPI_DataTypeDef SPI_ReceiveData(HT_SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + + return (SPI_DataTypeDef)SPIx->DR; +} + +/*********************************************************************************************************//** + * @brief Set the value of SPI FIFO Time Out. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Timeout: specify the value of Time Out. + * @retval None + ************************************************************************************************************/ +void SPI_SetTimeOutValue(HT_SPI_TypeDef* SPIx, SPI_TimeoutTypeDef SPI_Timeout) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + + SPIx->FTOCR = SPI_Timeout; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SPI interrupt. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Int: specify if the SPI interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_INT_TXBE : SPI Tx buffer empty interrupt + * @arg SPI_INT_TXE : SPI Tx empty interrupt + * @arg SPI_INT_RXBNE : SPI Rx buffer not empty interrupt + * @arg SPI_INT_WC : SPI write collision interrupt + * @arg SPI_INT_RO : SPI read overrun interrupt + * @arg SPI_INT_MF : SPI mode fault interrupt + * @arg SPI_INT_SA : SPI slave abort interrupt + * @arg SPI_INT_TO : SPI time out interrupt + * @arg SPI_INT_ALL : All SPI interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_IntConfig(HT_SPI_TypeDef* SPIx, u32 SPI_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_INT(SPI_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->IER |= SPI_Int; + } + else + { + SPIx->IER &= (u32)~SPI_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified SPI flag has been set or not. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_TXBE : SPI Tx buffer empty flag + * @arg SPI_FLAG_TXE : SPI Tx empty flag + * @arg SPI_FLAG_RXBNE : SPI Rx buffer not empty flag + * @arg SPI_FLAG_WC : SPI write collision flag + * @arg SPI_FLAG_RO : SPI read overrun flag + * @arg SPI_FLAG_MF : SPI mode fault flag + * @arg SPI_FLAG_SA : SPI slave abort flag + * @arg SPI_FLAG_TOUT : SPI time out flag + * @arg SPI_FLAG_BUSY : SPI busy flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus SPI_GetFlagStatus(HT_SPI_TypeDef* SPIx, u32 SPI_Flag) +{ + FlagStatus bitstatus = RESET; + u32 statusreg = 0; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FLAG(SPI_Flag)); + + statusreg = SPIx->SR; + + if ((statusreg & SPI_Flag) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Return the status of specified SPI FIFO. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_FIFODirection: specify the FIFO that is to be checked. + * This parameter can be one of the following values: + * @arg SPI_FIFO_TX : + * @arg SPI_FIFO_RX : + * @retval The number of data in Tx FIFO or Rx FIFO. + ************************************************************************************************************/ +u8 SPI_GetFIFOStatus(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection) +{ + u32 tmpreg; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FIFO_DIRECTION(SPI_FIFODirection)); + + if (SPI_FIFODirection == SPI_FIFO_TX) + { + tmpreg = SPIx->FSR & FCR_FIFO_MASK; + } + else + { + tmpreg = (SPIx->FSR & (FCR_FIFO_MASK << 4)) >> 4; + } + + return (u8)tmpreg; +} + +/*********************************************************************************************************//** + * @brief Clear the specified SPI flag. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Flag: specify the flag that is to be cleared. + * This parameter can be one of the following values: + * @arg SPI_FLAG_WC : SPI write collision flag + * @arg SPI_FLAG_RO : SPI read overrun flag + * @arg SPI_FLAG_MF : SPI mode fault flag + * @arg SPI_FLAG_SA : SPI slave abort flag + * @arg SPI_FLAG_TOUT : SPI time out flag + * @retval None + ************************************************************************************************************/ +void SPI_ClearFlag(HT_SPI_TypeDef* SPIx, u32 SPI_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FLAG_CLEAR(SPI_Flag)); + + SPIx->SR = SPI_Flag; +} + +/*********************************************************************************************************//** + * @brief Set the trigger level of SPI FIFO. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_FIFODirection: specify the FIFO that is to be set. + * This parameter can be one of the following values: + * @arg SPI_FIFO_TX : + * @arg SPI_FIFO_RX : + * @param SPI_FIFOLevel: Specify the FIFO trigger level. + * @retval None + ************************************************************************************************************/ +void SPI_FIFOTriggerLevelConfig(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection, u8 SPI_FIFOLevel) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FIFO_DIRECTION(SPI_FIFODirection)); + Assert_Param(IS_SPI_FIFO_LEVEL(SPI_FIFOLevel)); + + if (SPI_FIFODirection == SPI_FIFO_TX) + { + SPIx->FCR = ((SPIx->FCR & (0x00000400 | (FCR_FIFO_MASK << 4))) | SPI_FIFOLevel); + } + else + { + SPIx->FCR = ((SPIx->FCR & (0x00000400 | FCR_FIFO_MASK)) | (SPI_FIFOLevel << 4)); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SPIx PDMA interface. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_PDMAREQ: specify the SPI PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_PDMAREQ_TX : Tx PDMA transfer request + * @arg SPI_PDMAREQ_RX : Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_PDMACmd(HT_SPI_TypeDef* SPIx, u32 SPI_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_PDMA_REQ(SPI_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->CR0 |= SPI_PDMAREQ; + } + else + { + SPIx->CR0 &= ~SPI_PDMAREQ; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SPIx dual port read interface. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_DUALCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + (NewState == ENABLE)?(SPIx->CR0 |= CR0_DUALEN_SET):(SPIx->CR0 &= CR0_DUALEN_RESET); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SPIx guard time selection function. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_GUARDTCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + (NewState == ENABLE) ? (SPIx->CR0 |= CR0_GUADTEN_SET) : (SPIx->CR0 &= CR0_GUADTEN_RESET); +} + +/*********************************************************************************************************//** + * @brief Set the SPIx guard time length. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param Guard_Time: number of SCK to be the guard time length. + * This parameter can be: SPI_GUADTIME_1_SCK to SPI_GUADTIME_16_SCK. + * @retval None + ************************************************************************************************************/ +void SPI_GUARDTConfig(HT_SPI_TypeDef* SPIx, u32 Guard_Time) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_GUADTIME(Guard_Time)); + + SPIx->CR0 = (SPIx->CR0 & 0xF0FF) | (Guard_Time << 8); +} + +/*********************************************************************************************************//** + * @brief Set the SPIx chip select hold time. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param CS_Hold_Time: number of SCK to be the hold time length. + * This parameter can be: 0 ~ 15 + * @retval None + ************************************************************************************************************/ +void SPI_SELHTConfig(HT_SPI_TypeDef* SPIx, u32 CS_Hold_Time) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_SELHOLDTIME(CS_Hold_Time)); + + SPIx->CR0 = (SPIx->CR0 & 0x0FFF) | (CS_Hold_Time << 12); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_tm.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_tm.c new file mode 100644 index 00000000000..df486b5523e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_tm.c @@ -0,0 +1,1656 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_tm.c + * @version $Rev:: 2973 $ + * @date $Date:: 2023-10-30 #$ + * @brief This file provides all the TM firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_tm.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup TM TM + * @brief TM driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup TM_Private_Define TM private definitions + * @{ + */ +#define CNTCFR_UEVDIS 0x00000001ul +#define CNTCFR_UGDIS 0x00000002ul +#define CNTCFR_DIR 0x01000000ul +#define CNTCFR_CMSEL_MASK ~0x00030000ul +#define CNTCFR_CKDIV_MASK ~0x00000300ul + +#define MDCFR_SPMSET 0x01000000ul +#define MDCFR_TSE 0x00000001ul +#define MDCFR_SMSEL_MASK ~0x00000700ul +#define MDCFR_MMSEL_MASK ~0x00070000ul + +#define TRCFR_ECME 0x01000000ul +#define TRCFR_ETI_POL 0x00010000ul +#define TRCFR_ETI_PSC_MASK ~0x00003000ul +#define TRCFR_ETIF_MASK ~0x00000F00ul +#define TRCFR_TRSEL_MASK ~0x0000000Ful +#define TRCFR_ETI_CONF_MASK ~0x00013F00ul + +#define CTR_TME 0x00000001ul +#define CTR_CRBE 0x00000002ul +#define CTR_CHCCDS 0x00010000ul + +#define CH0ICFR_CH0SRC 0x80000000ul +#define CHICFR_CHF_MASK ~0x0000000Ful +#define CHICFR_CHCCS_MASK ~0x00030000ul +#define CHICFR_CHPSC_MASK ~0x000C0000ul + +#define CHOCFR_REFCE 0x00000008ul +#define CHOCFR_CHPRE 0x00000010ul +#define CHOCFR_IMAE 0x00000020ul +#define CHOCFR_CHOM_MASK ~0x00000107ul + +#define CHPOLR_CH0P 0x00000001ul +#define CHPOLR_CH1P 0x00000004ul +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void _TM_CHx_Config(HT_TM_TypeDef* TMx, TM_CH_Enum Ch, TM_CHP_Enum Pol, TM_CHCCS_Enum Sel, u8 Filter); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Functions TM exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the TMx peripheral registers to their default reset values. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval None + ************************************************************************************************************/ +void TM_DeInit(HT_TM_TypeDef* TMx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + if (TMx == HT_GPTM0) + { + RSTCUReset.Bit.GPTM0 = 1; + } + #if (!LIBCFG_NO_GPTM1) + else if (TMx == HT_GPTM1) + { + RSTCUReset.Bit.GPTM1 = 1; + } + #endif + #if (!LIBCFG_NO_MCTM0) + else if (TMx == HT_MCTM0) + { + RSTCUReset.Bit.MCTM0 = 1; + } + #endif + #if (!LIBCFG_NO_MCTM1) + else if (TMx == HT_MCTM1) + { + RSTCUReset.Bit.MCTM1 = 1; + } + #endif + #if (LIBCFG_PWM0) + else if (TMx == HT_PWM0) + { + RSTCUReset.Bit.PWM0 = 1; + } + #endif + #if (LIBCFG_SCTM0) + else if (TMx == HT_SCTM0) + { + RSTCUReset.Bit.SCTM0 = 1; + } + #endif + #if (LIBCFG_SCTM1) + else if (TMx == HT_SCTM1) + { + RSTCUReset.Bit.SCTM1 = 1; + } + #endif + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the TMx counter to reload, prescaler, counter mode and repetition counter. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param TimeBaseInit: Point to a \ref TM_TimeBaseInitTypeDef that contains the configuration information. + * @retval None + ************************************************************************************************************/ +void TM_TimeBaseInit(HT_TM_TypeDef* TMx, TM_TimeBaseInitTypeDef* TimeBaseInit) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CNT_MODE(TimeBaseInit->CounterMode)); + Assert_Param(IS_TM_PSC_RLD(TimeBaseInit->PSCReloadTime)); + + /* Set the counter reload value */ + TMx->CRR = TimeBaseInit->CounterReload; + + /* Set the Prescaler value */ + TMx->PSCR = TimeBaseInit->Prescaler; + + /* Select the Counter Mode */ + TMx->CNTCFR &= CNTCFR_CMSEL_MASK; /* CNTCFR_DIR is read only when the timer configured as */ + TMx->CNTCFR &= ~(u32)CNTCFR_DIR; /* Center-aligned mode. Reset mode first and then reset the */ + /* CNTCFR_DIR bit (separate as two steps). */ + + TMx->CNTCFR |= TimeBaseInit->CounterMode; + + #if (!LIBCFG_NO_MCTM0) + if ((TMx == HT_MCTM0) || (TMx == HT_MCTM1)) + { + /* Set the Repetition value */ + TMx->REPR = TimeBaseInit->RepetitionCounter; + } + #endif + + /* To reload the Prescaler value immediatly or next update event */ + TMx->EVGR = TimeBaseInit->PSCReloadTime; +} + +/*********************************************************************************************************//** + * @brief Initialize the TMx channel N output. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param OutInit: Point to a \ref TM_OutputInitTypeDef structure that contains + the configuration information. + * @retval None + ************************************************************************************************************/ +void TM_OutputInit(HT_TM_TypeDef* TMx, TM_OutputInitTypeDef* OutInit) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + OutInit->Channel; + vu32 *pCcr = (vu32*)&TMx->CH0CCR + OutInit->Channel; + vu32 *pAcr = (vu32*)&TMx->CH0ACR + OutInit->Channel; + u8 bChPos = OutInit->Channel << 1; + u32 wTmpMask; + u32 wTmpReg; + u32 uIsMCTM = 0; + + #if (!LIBCFG_NO_MCTM0) + if ((TMx == HT_MCTM0) || (TMx == HT_MCTM1)) + { + uIsMCTM = 1; + } + #endif + if (uIsMCTM) + { + wTmpMask = ~(0x3ul << bChPos); + } + else + { + wTmpMask = ~(0x1ul << bChPos); + } + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(OutInit->Channel)); + Assert_Param(IS_TM_OM(OutInit->OutputMode)); + Assert_Param(IS_TM_CHCTL(OutInit->Control)); + Assert_Param(IS_TM_CHP(OutInit->Polarity)); + + #if (!LIBCFG_NO_MCTM0) + if (uIsMCTM) + { + Assert_Param(IS_TM_CHCTL(OutInit->ControlN)); + Assert_Param(IS_TM_CHP(OutInit->PolarityN)); + Assert_Param(IS_MCTM_OIS(OutInit->IdleState)); + Assert_Param(IS_MCTM_OIS(OutInit->IdleStateN)); + } + #endif + + + /* Disable the Channel */ + TMx->CHCTR &= wTmpMask; + + /* Set the Output Compare Polarity */ + wTmpReg = TMx->CHPOLR & wTmpMask; + + if (uIsMCTM) + { + wTmpReg |= (u32)(OutInit->Polarity | (OutInit->PolarityN << 1)) << bChPos; + } + else + { + wTmpReg |= (u32)(OutInit->Polarity) << bChPos; + } + + TMx->CHPOLR = wTmpReg; + + /* Set the Output Idle State */ + if (uIsMCTM) + { + wTmpReg = TMx->CHBRKCFR & wTmpMask; + wTmpReg |= (u32)(OutInit->IdleState | (OutInit->IdleStateN << 1)) << bChPos; + TMx->CHBRKCFR = wTmpReg; + } + + /* Select the Output Compare Mode */ + *pOcfr &= CHOCFR_CHOM_MASK; + *pOcfr |= OutInit->OutputMode; + + /* Set the Capture Compare Register value */ + *pCcr = OutInit->Compare; + + /* Set the Asymmetric Compare Register value */ + *pAcr = OutInit->AsymmetricCompare; + + /* Set the channel state */ + if (uIsMCTM) + { + TMx->CHCTR |= (u32)(OutInit->Control | (OutInit->ControlN << 1)) << bChPos; + } + else + { + TMx->CHCTR |= (u32)(OutInit->Control) << bChPos; + } +} + +/*********************************************************************************************************//** + * @brief Initialize input capture of the TMx channel. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param CapInit: Point to a \ref TM_CaptureInitTypeDef structure that contains the configuration + * information. + * @retval None + ************************************************************************************************************/ +void TM_CaptureInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(CapInit->Channel)); + Assert_Param(IS_TM_CHP(CapInit->Polarity)); + Assert_Param(IS_TM_CHCCS(CapInit->Selection)); + Assert_Param(IS_TM_CHPSC(CapInit->Prescaler)); + Assert_Param(IS_TM_FILTER(CapInit->Filter)); + + _TM_CHx_Config(TMx, CapInit->Channel, CapInit->Polarity, CapInit->Selection, CapInit->Filter); + + /* Set the Input Capture Prescaler value */ + TM_CHPSCConfig(TMx, CapInit->Channel, CapInit->Prescaler); +} + +/*********************************************************************************************************//** + * @brief Configure the TMx to measure an external PWM signal. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param CapInit: Point to a \ref TM_CaptureInitTypeDef structure that contains the configuration + * information. + * @retval None + ************************************************************************************************************/ +void TM_PwmInputInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit) +{ + TM_CHP_Enum OppositePol; + TM_CHCCS_Enum OppositeSel; + TM_CH_Enum OppositeChannel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH_PWMI(CapInit->Channel)); + Assert_Param(IS_TM_CHP(CapInit->Polarity)); + Assert_Param(IS_TM_CHCCS(CapInit->Selection)); + Assert_Param(IS_TM_CHPSC(CapInit->Prescaler)); + Assert_Param(IS_TM_FILTER(CapInit->Filter)); + + /* Select the Opposite Input Polarity */ + if (CapInit->Polarity == TM_CHP_NONINVERTED) + { + OppositePol = TM_CHP_INVERTED; + } + else + { + OppositePol = TM_CHP_NONINVERTED; + } + + /* Select the Opposite Input */ + if (CapInit->Selection == TM_CHCCS_DIRECT) + { + OppositeSel = TM_CHCCS_INDIRECT; + } + else + { + OppositeSel = TM_CHCCS_DIRECT; + } + + if (CapInit->Channel == TM_CH_0) + { + OppositeChannel = TM_CH_1; + } + else + { + OppositeChannel = TM_CH_0; + } + + /* Capture Channel Configuration */ + _TM_CHx_Config(TMx, CapInit->Channel, CapInit->Polarity, CapInit->Selection, CapInit->Filter); + + /* Set the Input Capture Prescaler value */ + TM_CHPSCConfig(TMx, CapInit->Channel, CapInit->Prescaler); + + /* Opposite Channel Configuration */ + _TM_CHx_Config(TMx, OppositeChannel, OppositePol, OppositeSel, CapInit->Filter); + + /* Set the Input Capture Prescaler value */ + TM_CHPSCConfig(TMx, OppositeChannel, CapInit->Prescaler); +} + +/*********************************************************************************************************//** + * @brief Fill each TimeBaseInit member with its default value. + * @param TimeBaseInit: Point to a \ref TM_TimeBaseInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void TM_TimeBaseStructInit(TM_TimeBaseInitTypeDef* TimeBaseInit) +{ + /* Set the default configuration */ + TimeBaseInit->CounterMode = TM_CNT_MODE_UP; + TimeBaseInit->CounterReload = 0xFFFF; + TimeBaseInit->Prescaler = 0x0000; + TimeBaseInit->PSCReloadTime = TM_PSC_RLD_IMMEDIATE; + TimeBaseInit->RepetitionCounter = 0; +} + +/*********************************************************************************************************//** + * @brief Fill each OutInit member with its default value. + * @param OutInit: Point to a \ref TM_OutputInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void TM_OutputStructInit(TM_OutputInitTypeDef* OutInit) +{ + /* Set the default configuration */ + OutInit->Channel = TM_CH_0; + OutInit->OutputMode = TM_OM_MATCH_NOCHANGE; + OutInit->Control = TM_CHCTL_DISABLE; + OutInit->ControlN = TM_CHCTL_DISABLE; + OutInit->Polarity = TM_CHP_NONINVERTED; + OutInit->PolarityN = TM_CHP_NONINVERTED; + OutInit->IdleState = MCTM_OIS_LOW; + OutInit->IdleStateN = MCTM_OIS_LOW; + OutInit->Compare = 0x0000; + OutInit->AsymmetricCompare = 0x0000; +} + +/*********************************************************************************************************//** + * @brief Fill each CapInit member with its default value. + * @param CapInit: Point to a \ref TM_CaptureInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void TM_CaptureStructInit(TM_CaptureInitTypeDef* CapInit) +{ + /* Set the default configuration */ + CapInit->Channel = TM_CH_0; + CapInit->Polarity = TM_CHP_NONINVERTED; + CapInit->Selection = TM_CHCCS_DIRECT; + CapInit->Prescaler = TM_CHPSC_OFF; + CapInit->Filter = 0x00; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable TMx counter. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_Cmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TM Counter */ + TMx->CTR |= CTR_TME; + } + else + { + /* Disable the TM Counter */ + TMx->CTR &= ~CTR_TME; + } +} + +/*********************************************************************************************************//** + * @brief Configure external clock mode of the TMx. Used ITIx as the clock source. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Iti: Trigger source. + * This parameter can be one of the following values: + * @arg TM_TRSEL_ITI0: Internal trigger 0 + * @arg TM_TRSEL_ITI1: Internal trigger 1 + * @arg TM_TRSEL_ITI2: Internal trigger 2 + * @retval None + ************************************************************************************************************/ +void TM_ItiExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Iti) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_ITI(Iti)); + + /* Select the Internal Trigger. Slave mode will be disable in this function */ + TM_StiConfig(TMx, Iti); + + /* Select the STIED as external clock source */ + TMx->MDCFR |= TM_SMSEL_STIED; +} + +/*********************************************************************************************************//** + * @brief Configure external clock mode of the TMx. Used CHx as the clock source. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the channel source. + * This parameter can be one of the following values: + * @arg TM_TRSEL_TI0BED : TI0 both edge detector + * @arg TM_TRSEL_TI0S0 : Filtered timer input 0 + * @arg TM_TRSEL_TI1S1 : Filtered timer input 1 + * @param Pol: Specify the CHx Polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : active high. + * @arg TM_CHP_INVERTED : active low. + * @param Filter: Specify the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + ************************************************************************************************************/ +void TM_ChExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel, TM_CHP_Enum Pol, u8 Filter) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_TRSEL_CH(Sel)); + Assert_Param(IS_TM_CHP(Pol)); + Assert_Param(IS_TM_FILTER(Filter)); + + /* Configure the Timer Input Clock Source */ + if (Sel == TM_TRSEL_TI1S1) + { + _TM_CHx_Config(TMx, TM_CH_1, Pol, TM_CHCCS_DIRECT, Filter); + } + else + { + _TM_CHx_Config(TMx, TM_CH_0, Pol, TM_CHCCS_DIRECT, Filter); + } + + /* Select the external clock source. Slave mode will be disable in this function */ + TM_StiConfig(TMx, Sel); + + /* Select the STIED as external clock source */ + TMx->MDCFR |= TM_SMSEL_STIED; +} + +/*********************************************************************************************************//** + * @brief Configure external clock mode of the TMx. Used ETI as the clock source. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param Psc: The external Trigger Prescaler. + * It can be one of the following values: + * @arg TM_ETIPSC_OFF : ETI prescaler off + * @arg TM_ETIPSC_2 : ETIP frequency divided by 2 + * @arg TM_ETIPSC_4 : ETIP frequency divided by 4 + * @arg TM_ETIPSC_8 : ETIP frequency divided by 8 + * @param Pol: The external trigger input polarity. + * It can be one of the following values: + * @arg TM_ETIPOL_NONINVERTED : Active high level or rising edge + * @arg TM_ETIPOL_INVERTED : Active low level or falling edge + * @param Filter: Filter for ETI input. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + ************************************************************************************************************/ +void TM_EtiExternalClockConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_ETIPSC(Psc)); + Assert_Param(IS_TM_ETIPOL(Pol)); + Assert_Param(IS_TM_FILTER(Filter)); + + /* Configure the ETI Clock source */ + TM_EtiConfig(TMx, Psc, Pol, Filter); + + /* Enable the external clock mode */ + TMx->TRCFR |= TRCFR_ECME; +} + +/*********************************************************************************************************//** + * @brief Configure external trigger input (ETI) of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param Psc: The external Trigger Prescaler. + * It can be one of the following values: + * @arg TM_ETIPSC_OFF : ETI prescaler off + * @arg TM_ETIPSC_2 : ETIP frequency divided by 2 + * @arg TM_ETIPSC_4 : ETIP frequency divided by 4 + * @arg TM_ETIPSC_8 : ETIP frequency divided by 8 + * @param Pol: The external trigger input polarity. + * It can be one of the following values: + * @arg TM_ETIPOL_NONINVERTED : Active high level or rising edge + * @arg TM_ETIPOL_INVERTED : Active low level or falling edge + * @param Filter: Filter for ETI input. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + ************************************************************************************************************/ +void TM_EtiConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter) +{ + u32 wTrcfr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_ETIPSC(Psc)); + Assert_Param(IS_TM_ETIPOL(Pol)); + Assert_Param(IS_TM_FILTER(Filter)); + + /* Get TRCFR value with cleared ETI configuration bits */ + wTrcfr = TMx->TRCFR & TRCFR_ETI_CONF_MASK; + + /* Set the prescaler, filter and polarity for ETI input */ + wTrcfr |= (u32)Psc | Pol | ((u32)Filter << 8); + + /* Write to TMx TRCFR */ + TMx->TRCFR = wTrcfr; +} + +/*********************************************************************************************************//** + * @brief Configure prescaler of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Psc: Specify the prescaler value. + * @param PscReloadTime: Specify the TM prescaler reload time. + * This parameter can be one of the following values: + * @arg TM_PSC_RLD_UPDATE : The prescaler is loaded at the next update event. + * @arg TM_PSC_RLD_IMMEDIATE : The prescaler is loaded immediatly. + * @retval None + ************************************************************************************************************/ +void TM_PrescalerConfig(HT_TM_TypeDef* TMx, u16 Psc, TM_PSC_RLD_Enum PscReloadTime) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_PSC_RLD(PscReloadTime)); + + /* Set the prescaler value */ + TMx->PSCR = Psc; + + /* Set the UEVG bit or not */ + TMx->EVGR = PscReloadTime; +} + +/*********************************************************************************************************//** + * @brief Configure counter mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Mod: Specify the counter mode to be used. + * This parameter can be one of the following values: + * @arg TM_CNT_MODE_UP : TM up counting mode. + * @arg TM_CNT_MODE_DOWN : TM down counting mode. + * @arg TM_CNT_MODE_CA1 : TM center aligned mode 1. + * @arg TM_CNT_MODE_CA2 : TM center aligned mode 2. + * @arg TM_CNT_MODE_CA3 : TM center aligned mode 3. + * @retval None + ************************************************************************************************************/ +void TM_CounterModeConfig(HT_TM_TypeDef* TMx, TM_CNT_MODE_Enum Mod) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CNT_MODE(Mod)); + + /* Reset the CMSEL and DIR Bits */ + TMx->CNTCFR &= CNTCFR_CMSEL_MASK; /* CNTCFR_DIR is read only when the timer configured as */ + TMx->CNTCFR &= ~(u32)CNTCFR_DIR; /* Center-aligned mode. Reset mode first and then reset the */ + /* CNTCFR_DIR bit (separate as two steps). */ + + /* Set the Counter Mode */ + TMx->CNTCFR |= Mod; +} + +/*********************************************************************************************************//** + * @brief Select the STI source. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the STI source. + * This parameter can be one of the following: + * @arg TM_TRSEL_ITI0 : Internal trigger 0. + * @arg TM_TRSEL_ITI1 : Internal trigger 1. + * @arg TM_TRSEL_ITI2 : Internal trigger 2. + * @arg TM_TRSEL_TI0BED : TI0 both edge detector. + * @arg TM_TRSEL_TI0S0 : Filtered channel 0 input. + * @arg TM_TRSEL_TI1S1 : Filtered channel 1 input. + * @arg TM_TRSEL_ETIF : External trigger input. + * @arg TM_TRSEL_UEVG : Trigger by setting UEVG bit. + * @retval None + ************************************************************************************************************/ +void TM_StiConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel) +{ + u32 wTrcfr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_TRSEL(Sel)); + + /* Disable slave mode */ + TMx->MDCFR &= MDCFR_SMSEL_MASK; + + /* Get the TRCFR value with cleared TRSEL */ + wTrcfr = TMx->TRCFR & TRCFR_TRSEL_MASK; + + /* Set the STI source */ + TMx->TRCFR |= wTrcfr | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure encoder interface of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param DecoderMod: Specify the TMx decoder mode. + * This parameter can be one of the following values: + * @arg TM_SMSEL_DECODER1 : Counter counts on CH0 edge depending on CH1 level. + * @arg TM_SMSEL_DECODER2 : Counter counts on CH1 edge depending on CH0 level. + * @arg TM_SMSEL_DECODER3 : Counter counts on both CH0 and CH1 edges depending on + * the level of the other input. + * @param CH0P: Specify the CH0 polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : Active high level or rising edge + * @arg TM_CHP_INVERTED : Active low level or falling edge + * @param CH1P: Specify the CH1 polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : Active high level or rising edge + * @arg TM_CHP_INVERTED : Active low level or falling edge + * @retval None + ************************************************************************************************************/ +void TM_DecoderConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum DecoderMod, TM_CHP_Enum CH0P, TM_CHP_Enum CH1P) +{ + u32 wMdcfr, wCh0Icfr, wCh1Icfr, wChpolr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_SMSEL_DECODER(DecoderMod)); + Assert_Param(IS_TM_CHP(CH0P)); + Assert_Param(IS_TM_CHP(CH1P)); + + /* Get the TMx MDCFR register value */ + wMdcfr = TMx->MDCFR; + + /* Get the TMx CH0ICFR & CH1ICFR register value */ + wCh0Icfr = TMx->CH0ICFR; + wCh1Icfr = TMx->CH1ICFR; + + /* Get the TMx CHPOLR register value */ + wChpolr = TMx->CHPOLR; + + /* Set the decoder mode */ + wMdcfr &= MDCFR_SMSEL_MASK; + wMdcfr |= DecoderMod; + + /* Select the channel 0 and the channel 1 as input and clear CH0SRC */ + wCh0Icfr &= CHICFR_CHCCS_MASK & (~CH0ICFR_CH0SRC); + wCh1Icfr &= CHICFR_CHCCS_MASK; + wCh0Icfr |= TM_CHCCS_DIRECT; + wCh1Icfr |= TM_CHCCS_DIRECT; + + /* Set the CH0 and the CH1 polarities */ + wChpolr &= ~(CHPOLR_CH0P | CHPOLR_CH1P); + wChpolr |= (CH0P | (CH1P << 2)); + + /* Write to TMx MDCFR */ + TMx->MDCFR = wMdcfr; + + /* Write to TMx CH0ICFR & CH1ICFR */ + TMx->CH0ICFR = wCh0Icfr; + TMx->CH1ICFR = wCh1Icfr; + + /* Write to TMx CHPOLR */ + TMx->CHPOLR = wChpolr; +} + +/*********************************************************************************************************//** + * @brief Force the TMx CHnOREF waveform to active or inactive level. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param ForcedAction: Specify the forced action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TM_OM_FORCED_ACTIVE : Forced active level on CH0OREF + * @arg TM_OM_FORCED_INACTIVE : Forced inactive level on CH0OREF. + * @retval None + ************************************************************************************************************/ +void TM_ForcedOREF(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, TM_OM_Enum ForcedAction) +{ + vu32* pCHnOCFR = ((vu32*)&TMx->CH0OCFR) + (TM_CH_n * 1); + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + Assert_Param(IS_TM_OM_FORCED(ForcedAction)); + + /* Configure The forced output mode */ + *pCHnOCFR = (*pCHnOCFR & CHOCFR_CHOM_MASK) | ForcedAction; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the TMx CRR preload function. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_CRRPreloadCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Set the CRR preload control bit */ + TMx->CTR |= CTR_CRBE; + } + else + { + /* Reset the CRR preload control bit */ + TMx->CTR &= ~CTR_CRBE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the TMx CHxCCR preload function. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param NewState This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_CHCCRPreloadConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Enable or disable the channel N CCR preload feature */ + if (NewState != DISABLE) + { + *pOcfr |= CHOCFR_CHPRE; + } + else + { + *pOcfr &= ~CHOCFR_CHPRE; + } +} + +/*********************************************************************************************************//** + * @brief Clear or Safeguard the CHxOREF signal when ETI is active. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param NewState This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_ClearOREFConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Enable or Disable the channel N clear Oref at ETI active function */ + if (NewState != DISABLE) + { + *pOcfr |= CHOCFR_REFCE; + } + else + { + *pOcfr &= ~CHOCFR_REFCE; + } +} + +/*********************************************************************************************************//** + * @brief Configure polarity of the TMx channel N. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Pol: Specify the polarity of channel N. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : active high + * @arg TM_CHP_INVERTED : active low + * @retval None + ************************************************************************************************************/ +void TM_ChPolarityConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHP_Enum Pol) +{ + u32 wChpolr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_CHP(Pol)); + + /* Set or reset the CHx polarity */ + wChpolr = TMx->CHPOLR & (~(u32)(0x1 << (Channel << 1))); + TMx->CHPOLR = wChpolr | (Pol << (Channel << 1)); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the single pulse immediate active function. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + * @note Must configure output mode to PWM1 or PWM2 before invoke this function. + ************************************************************************************************************/ +void TM_ImmActiveConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Enable or disable the channel N clear CHxOREF at ETI active function */ + if (NewState != DISABLE) + { + *pOcfr |= CHOCFR_IMAE; + } + else + { + *pOcfr &= ~CHOCFR_IMAE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the TMx channel N. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Control: This parameter can be TM_CHCTL_ENABLE or TM_CHCTL_DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_ChannelConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_CHCTL(Control)); + + /* Reset the CHxE Bit */ + TMx->CHCTR &= ~(u32)(0x1 << (Channel << 1)); + + /* Set or reset the CHxE Bit */ + TMx->CHCTR |= (u32)Control << (Channel << 1); +} + +/*********************************************************************************************************//** + * @brief Configure output mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Mod: Specify the TM output mode. + * This parameter can be one of the following values: + * @arg TM_OM_MATCH_NOCHANGE : Output dont change on match + * @arg TM_OM_MATCH_INACTIVE : Output inactive on compare match + * @arg TM_OM_MATCH_ACTIVE : Output active on compare match + * @arg TM_OM_MATCH_TOGGLE : Output toggle on compare match + * @arg TM_OM_FORCED_INACTIVE : Output forced inactive + * @arg TM_OM_FORCED_ACTIVE : Output forced active + * @arg TM_OM_PWM1 : PWM1 mode + * @arg TM_OM_PWM2 : PWM2 mode + * @arg TM_OM_ASYMMETRIC_PWM1 : Asymmetric PWM1 mode + * @arg TM_OM_ASYMMETRIC_PWM2 : Asymmetric PWM2 mode + * @retval None + * @note This function disables the selected channel before changing the output mode. + ************************************************************************************************************/ +void TM_OutputModeConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_OM_Enum Mod) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_OM(Mod)); + + /* Disable the channel: Reset the CHxE Bit */ + TMx->CHCTR &= ~(u32)(0x1 << (Channel << 1)); + + /* Selects the TM output mode */ + *pOcfr = (*pOcfr & CHOCFR_CHOM_MASK) | Mod; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable update event of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE (default) or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_UpdateCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == DISABLE) + { + /* Set the update disable bit */ + TMx->CNTCFR |= CNTCFR_UEVDIS; + } + else + { + /* Reset the update disable bit */ + TMx->CNTCFR &= ~CNTCFR_UEVDIS; + } +} + +/*********************************************************************************************************//** + * @brief Configure UEVG interrupt function of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be one of the following value: + * @arg ENABLE : Default value. Any of the following events will generate an update event interrupt: + * - Counter overflow/underflow + * - Setting the UEVG bit + * - Update generation through the slave restart mode + * @arg DISABLE : Only counter overflow/underflow generations an update event interrupt. + * @retval None + ************************************************************************************************************/ +void TM_UEVG_IntConfig(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == DISABLE) + { + /* Set the UEVG interrupt disable bit */ + TMx->CNTCFR |= CNTCFR_UGDIS; + } + else + { + /* Reset the UEVG interrupt disable bit */ + TMx->CNTCFR &= ~CNTCFR_UGDIS; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable hall sensor interface of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_HallInterfaceCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Set the CH0SRC Bit */ + TMx->CH0ICFR |= CH0ICFR_CH0SRC; + } + else + { + /* Reset the CH0SRC Bit */ + TMx->CH0ICFR &= ~CH0ICFR_CH0SRC; + } +} + +/*********************************************************************************************************//** + * @brief Select single pulse mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_SinglePulseModeCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + TMx->MDCFR |= MDCFR_SPMSET; + } + else + { + TMx->MDCFR &= ~MDCFR_SPMSET; + } +} + +/*********************************************************************************************************//** + * @brief Select master trigger output source of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the master trigger output source. + * This parameter can be as follow: + * @arg TM_MMSEL_RESET : Send trigger signal when S/W setting UEVG or slave restart + * @arg TM_MMSEL_ENABLE : The counter enable signal is used as trigger output. + * @arg TM_MMSEL_UPDATE : The update event is used as trigger output. + * @arg TM_MMSEL_CH0CC : Channel 0 capture or compare match occurred as trigger output. + * @arg TM_MMSEL_CH0OREF : The CH0OREF signal is used as trigger output. + * @arg TM_MMSEL_CH1OREF : The CH1OREF signal is used as trigger output. + * @arg TM_MMSEL_CH2OREF : The CH2OREF signal is used as trigger output. + * @arg TM_MMSEL_CH3OREF : The CH3OREF signal is used as trigger output. + * @retval None + ************************************************************************************************************/ +void TM_MMSELConfig(HT_TM_TypeDef* TMx, TM_MMSEL_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_MMSEL(Sel)); + + /* Select the MTO source */ + TMx->MDCFR = (TMx->MDCFR & MDCFR_MMSEL_MASK) | Sel; +} + +/*********************************************************************************************************//** + * @brief Select slave mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the timer slave mode. + * This parameter can be one of the following values: + * @arg TM_SMSEL_RESTART : Slave restart counter mode. + * @arg TM_SMSEL_PAUSE : Slave pause counter mode. + * @arg TM_SMSEL_TRIGGER : Slave trigger counter start mode. + * @arg TM_SMSEL_STIED : Used rising edge of STI as prescaler clock source. + * @retval None + ************************************************************************************************************/ +void TM_SlaveModeConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_SLAVE_MODE(Sel)); + + /* Select the slave mode */ + TMx->MDCFR = (TMx->MDCFR & MDCFR_SMSEL_MASK) | Sel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the master & slave TMx synchronous function. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_TimSyncCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Set the TSE Bit */ + TMx->MDCFR |= MDCFR_TSE; + } + else + { + /* Reset the TSE Bit */ + TMx->MDCFR &= ~MDCFR_TSE; + } +} + +/*********************************************************************************************************//** + * @brief Set counter register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Counter: Specify the counter register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetCounter(HT_TM_TypeDef* TMx, u16 Counter) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Set the Counter Register value */ + TMx->CNTR = Counter; +} + +/*********************************************************************************************************//** + * @brief Set counter reload register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Reload: Specify the counter reload register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetCounterReload(HT_TM_TypeDef* TMx, u16 Reload) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Set the counter reload register value */ + TMx->CRR = Reload; +} + +/*********************************************************************************************************//** + * @brief Set channel n capture/compare register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Cmp: Specify the CH0CCR register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) +{ + vu32* pCHnCCR = ((vu32*)&TMx->CH0CCR) + (TM_CH_n * 1); + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + + /* Set the CHnCCR register new value */ + *pCHnCCR = Cmp; +} + +/*********************************************************************************************************//** + * @brief Set channel n asymmetric compare register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Cmp: Specify the CH0ACR register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetAsymmetricCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) +{ + vu32* pCHnACR = ((vu32*)&TMx->CH0ACR) + (TM_CH_n * 1); + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + + /* Set the CHnACR register new value */ + *pCHnACR = Cmp; +} + +/*********************************************************************************************************//** + * @brief Configure input capture prescaler. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Psc: Specify the input capture prescaler new value. + * This parameter can be one of the following values: + * @arg TM_CHPSC_OFF : No prescaler + * @arg TM_CHPSC_2 : Capture is done once every 2 events + * @arg TM_CHPSC_4 : Capture is done once every 4 events + * @arg TM_CHPSC_8 : Capture is done once every 8 events + * @retval None + ************************************************************************************************************/ +void TM_CHPSCConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHPSC_Enum Psc) +{ + vu32 *pIcfr = (vu32*)&TMx->CH0ICFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_CHPSC(Psc)); + + /* Reset the CHxPSC bits */ + *pIcfr &= CHICFR_CHPSC_MASK; + + /* Set the capture input prescaler value */ + *pIcfr |= Psc; +} + +/*********************************************************************************************************//** + * @brief Set clock division value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Div: Specify the clock division value. + * This parameter can be one of the following value: + * @arg TM_CKDIV_OFF : fDTS = fCLKIN + * @arg TM_CKDIV_2 : fDTS = fCLKIN / 2 + * @arg TM_CKDIV_4 : fDTS = fCLKIN / 4 + * @retval None + ************************************************************************************************************/ +void TM_CKDIVConfig(HT_TM_TypeDef* TMx, TM_CKDIV_Enum Div) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CKDIV(Div)); + + /* Reset the CKDIV Bits */ + TMx->CNTCFR &= CNTCFR_CKDIV_MASK; + + /* Set the CKDIV value */ + TMx->CNTCFR |= Div; +} + +/*********************************************************************************************************//** + * @brief Get channel n capture/compare register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @retval Value of CH0CCR register + ************************************************************************************************************/ +u32 TM_GetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n) +{ + vu32* pCHnCCR = ((vu32*)&TMx->CH0CCR) + (TM_CH_n * 1); + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + + /* Get the CHnCCR register value */ + return (*pCHnCCR); +} + +/*********************************************************************************************************//** + * @brief Get counter value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval Value of Counter register + ************************************************************************************************************/ +u32 TM_GetCounter(HT_TM_TypeDef* TMx) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Get the Counter Register value */ + return TMx->CNTR; +} + +/*********************************************************************************************************//** + * @brief Get prescaler value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval Value of Prescaler register + ************************************************************************************************************/ +u32 TM_GetPrescaler(HT_TM_TypeDef* TMx) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Get the Prescaler Register value */ + return TMx->PSCR; +} + +/*********************************************************************************************************//** + * @brief Generate TMx events. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_EVENT: Stores the event source. + * This parameter can be any combination of following: + * @arg TM_EVENT_CH0CC : Timer Capture/compare 0 event + * @arg TM_EVENT_CH1CC : Timer Capture/compare 1 event + * @arg TM_EVENT_CH2CC : Timer Capture/compare 2 event + * @arg TM_EVENT_CH3CC : Timer Capture/compare 3 event + * @arg TM_EVENT_UEV : Timer update event + * @arg TM_EVENT_UEV2 : Timer update event 2 + * @arg TM_EVENT_TEV : Timer trigger event + * @arg TM_EVENT_BRKEV : Timer break event + * @retval None + ************************************************************************************************************/ +void TM_GenerateEvent(HT_TM_TypeDef* TMx, u32 TM_EVENT) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_EVENT(TM_EVENT)); + + /* Set the event sources */ + TMx->EVGR = TM_EVENT; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified TMx flag has been set. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_FLAG: Specify the flag to be checked. + * This parameter can be one of the following values: + * @arg TM_FLAG_CH0CC : TM Capture/compare 0 flag + * @arg TM_FLAG_CH1CC : TM Capture/compare 1 flag + * @arg TM_FLAG_CH2CC : TM Capture/compare 2 flag + * @arg TM_FLAG_CH3CC : TM Capture/compare 3 flag + * @arg TM_FLAG_CH0OC : TM channel 0 overcapture flag + * @arg TM_FLAG_CH1OC : TM channel 1 overcapture flag + * @arg TM_FLAG_CH2OC : TM channel 2 overcapture flag + * @arg TM_FLAG_CH3OC : TM channel 3 overcapture flag + * @arg TM_FLAG_UEV : TM update flag + * @arg TM_FLAG_UEV2 : TM update 2 flag + * @arg TM_FLAG_TEV : TM trigger flag + * @arg TM_FLAG_BRK0 : TM break 0 flag + * @arg TM_FLAG_BRK1 : TM break 1 flag + * @retval The new state of TM_FLAG (SET or RESET). + ************************************************************************************************************/ +FlagStatus TM_GetFlagStatus(HT_TM_TypeDef* TMx, u32 TM_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_FLAG(TM_FLAG)); + + if ((TMx->INTSR & TM_FLAG) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear flags of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_FLAG: Specify the flag to be cleared. + * This parameter can be any combination of the following values: + * @arg TM_FLAG_CH0CC : TM Capture/compare 0 flag + * @arg TM_FLAG_CH1CC : TM Capture/compare 1 flag + * @arg TM_FLAG_CH2CC : TM Capture/compare 2 flag + * @arg TM_FLAG_CH3CC : TM Capture/compare 3 flag + * @arg TM_FLAG_CH0OC : TM channel 0 overcapture flag + * @arg TM_FLAG_CH1OC : TM channel 1 overcapture flag + * @arg TM_FLAG_CH2OC : TM channel 2 overcapture flag + * @arg TM_FLAG_CH3OC : TM channel 3 overcapture flag + * @arg TM_FLAG_UEV : TM update flag + * @arg TM_FLAG_UEV2 : TM update 2 flag + * @arg TM_FLAG_TEV : TM trigger flag + * @arg TM_FLAG_BRK0 : TM break 0 flag + * @arg TM_FLAG_BRK1 : TM break 1 flag + * @retval None + ************************************************************************************************************/ +void TM_ClearFlag(HT_TM_TypeDef* TMx, u32 TM_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_FLAG_CLR(TM_FLAG)); + + /* Clear the flags */ + TMx->INTSR = ~TM_FLAG; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified interrupts of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_INT: Specify the TM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TM_INT_CH0CC : TM Capture/compare 0 interrupt + * @arg TM_INT_CH1CC : TM Capture/compare 1 interrupt + * @arg TM_INT_CH2CC : TM Capture/compare 2 interrupt + * @arg TM_INT_CH3CC : TM Capture/compare 3 interrupt + * @arg TM_INT_UEV : TM update interrupt + * @arg TM_INT_UEV2 : TM update 2 interrupt + * @arg TM_INT_TEV : TM trigger interrupt + * @arg TM_INT_BRKEV : TM break interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_IntConfig(HT_TM_TypeDef* TMx, u32 TM_INT, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_INT(TM_INT)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the interrupt sources */ + TMx->DICTR |= TM_INT; + } + else + { + /* Disable the interrupt sources */ + TMx->DICTR &= ~TM_INT; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the TMx interrupt has occurred. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_INT: Specify the TM interrupt source to be checked. + * This parameter can be one of the following values: + * @arg TM_INT_CH0CC : TM Capture/compare 0 interrupt + * @arg TM_INT_CH1CC : TM Capture/compare 1 interrupt + * @arg TM_INT_CH2CC : TM Capture/compare 2 interrupt + * @arg TM_INT_CH3CC : TM Capture/compare 3 interrupt + * @arg TM_INT_UEV : TM update interrupt + * @arg TM_INT_UEV2 : TM update 2 interrupt + * @arg TM_INT_TEV : TM trigger interrupt + * @arg TM_INT_BRKEV : TM break interrupt + * @retval The new state of the TM_INT(SET or RESET) + ************************************************************************************************************/ +FlagStatus TM_GetIntStatus(HT_TM_TypeDef* TMx, u32 TM_INT) +{ + u32 itstatus, itenable; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_GET_INT(TM_INT)); + + itstatus = TMx->INTSR & TM_INT; + itenable = TMx->DICTR & TM_INT; + + if ((itstatus != 0) && (itenable != 0)) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear interrupt pending bits of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_INT: Specify the TM interrupt to be cleared. + * This parameter can be any combination of the following values: + * @arg TM_INT_CH0CC : TM Capture/compare 0 interrupt + * @arg TM_INT_CH1CC : TM Capture/compare 1 interrupt + * @arg TM_INT_CH2CC : TM Capture/compare 2 interrupt + * @arg TM_INT_CH3CC : TM Capture/compare 3 interrupt + * @arg TM_INT_UEV : TM update interrupt + * @arg TM_INT_UEV2 : TM update 2 interrupt + * @arg TM_INT_TEV : TM trigger interrupt + * @arg TM_INT_BRKEV : TM break interrupt + * @retval None + ************************************************************************************************************/ +void TM_ClearIntPendingBit(HT_TM_TypeDef* TMx, u32 TM_INT) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_INT(TM_INT)); + + /* Clear the interrupt pending Bit */ + TMx->INTSR = ~TM_INT; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Disable slave mode to clock the prescaler directly with the internal clock. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval None + ************************************************************************************************************/ +void TM_InternalClockConfig(HT_TM_TypeDef* TMx) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TMx->MDCFR &= MDCFR_SMSEL_MASK; +} + +/*********************************************************************************************************//** + * @brief Select Channel Capture/Compare PDMA event of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Selection: This parameter can be TM_CHCCDS_CHCCEV or TM_CHCCDS_UEV. + * @retval None + ************************************************************************************************************/ +void TM_CHCCDSConfig(HT_TM_TypeDef* TMx, TM_CHCCDS_Enum Selection) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CHCCDS(Selection)); + + if (Selection != TM_CHCCDS_CHCCEV) + { + TMx->CTR |= CTR_CHCCDS; + } + else + { + TMx->CTR &= ~CTR_CHCCDS; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified PDMA requests of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_PDMA: Specify the TM PDMA requests to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TM_PDMA_CH0CC : TM Capture/compare 0 PDMA request + * @arg TM_PDMA_CH1CC : TM Capture/compare 1 PDMA request + * @arg TM_PDMA_CH2CC : TM Capture/compare 2 PDMA request + * @arg TM_PDMA_CH3CC : TM Capture/compare 3 PDMA request + * @arg TM_PDMA_UEV : TM update PDMA request + * @arg TM_PDMA_UEV2 : TM update 2 PDMA request + * @arg TM_PDMA_TEV : TM trigger PDMA request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_PDMAConfig(HT_TM_TypeDef* TMx, u32 TM_PDMA, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_PDMA(TM_PDMA)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PDMA request */ + TMx->DICTR |= TM_PDMA; + } + else + { + /* Disable the PDMA request */ + TMx->DICTR &= ~TM_PDMA; + } +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup TM_Private_Functions TM private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Configure the CHx as input. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Ch: Specify the TM Channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Pol: The input polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : Active high level or rising edge + * @arg TM_CHP_INVERTED : Active low level or falling edge + * @param Sel: Specify the input to be used. + * This parameter can be one of the following values: + * @arg TM_CHCCS_DIRECT : TM CHxI is mapped on CHx. + * @arg TM_CHCCS_INDIRECT : TM CH1I is mapped on CH0 (or CH0I->CH1 or CH2I->CH3 or CH3I->CH2). + * @arg TM_CHCCS_TRCED : TM CHx is mapped on TRC. + * @param Filter: Specify the input capture filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + ************************************************************************************************************/ +static void _TM_CHx_Config(HT_TM_TypeDef* TMx, TM_CH_Enum Ch, TM_CHP_Enum Pol, TM_CHCCS_Enum Sel, u8 Filter) +{ + vu32* pIcfr = (vu32*)&TMx->CH0ICFR + Ch; + u32 wIcfr, wChpolr; + + /* Disable the channel N: reset the CHxE bit */ + TMx->CHCTR &= ~((u32)0x1 << (Ch << 1)); + + wIcfr = *pIcfr; + wChpolr = TMx->CHPOLR; + + /* Select the input and set the filter */ + wIcfr &= CHICFR_CHCCS_MASK & CHICFR_CHF_MASK; + wIcfr |= Sel | Filter; + *pIcfr = wIcfr; + + /* Select the polarity bit */ + wChpolr &= ~((u32)0x1 << (Ch << 1)); + wChpolr |= (u32)Pol << (Ch << 1); + TMx->CHPOLR = wChpolr; + + /* Set the CHxE Bit */ + TMx->CHCTR |= (u32)0x1 << (Ch << 1); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_usart.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_usart.c new file mode 100644 index 00000000000..93ccffa0bfa --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_usart.c @@ -0,0 +1,1105 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_usart.c + * @version $Rev:: 2972 $ + * @date $Date:: 2023-10-28 #$ + * @brief This file provides all the USART firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_usart.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup USART USART + * @brief USART driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup USART_Private_Define USART private definitions + * @{ + */ +#if (LIBCFG_USART_V01) +#define MDR_CLEAR_Mask ((u32)0xFFFFFFFC) +#define LCR_CLEAR_Mask ((u32)0xFFFFFFE0) + +#define USART_TIMEOUT_ON ((u32)0x00000080) +#define USART_TIMEOUT_OFF ((u32)0xFFFFFF7F) + +#define USART_BREAK_ON ((u32)0x00000040) +#define USART_BREAK_OFF ((u32)0xFFFFFFBF) + +#define USART_SPE_ON ((u32)0x00000020) +#define USART_SPE_OFF ((u32)0xFFFFFFDF) + +#define USART_EN_ON ((u32)0x00000100) + +#define USART_HFCEN_ON ((u32)0x00000004) +#define USART_HFCEN_OFF ((u32)0xFFFFFFFB) +#else +#define CR_CLEAR_Mask ((u32)0xFFFFE0FC) + +#define USART_BREAK_ON ((u32)0x00004000) +#define USART_BREAK_OFF ((u32)0xFFFFBFFF) + +#define USART_PBE_ON ((u32)0x00000800) +#define USART_SPE_ON ((u32)0x00002000) +#define USART_SPE_OFF ((u32)0xFFFFDFFF) + +#define USART_EN_ON ((u32)0x00000010) + +#define USART_HFCEN_ON ((u32)0x00000008) +#define USART_HFCEN_OFF ((u32)0xFFFFFFF7) + +#define USART_RXTOEN_ON ((u32)0x00000080) +#endif + +#define FCR_TL_Mask ((u32)0x00000030) + +#define TRSM_CLEAR_Mask ((u32)0xFFFFFFFB) +#define TPR_TG_Mask ((u32)0xFFFF00FF) +#define ICR_IRDAPSC_Mask ((u32)0xFFFF00FF) +#define TPR_RXTOIC_Mask ((u32)0xFFFFFF80) +#define RS485CR_ADDM_Mask ((u32)0xFFFF00FF) + +#define USART_IRDA_ON ((u32)0x00000001) +#define USART_IRDA_OFF ((u32)0xFFFFFFFE) + +#define USART_INV_ON ((u32)0x00000010) + +#define USART_RS485NMM_ON ((u32)0x00000002) +#define USART_RS485NMM_OFF ((u32)0xFFFFFFFD) + +#define USART_RS485AAD_ON ((u32)0x00000004) +#define USART_RS485AAD_OFF ((u32)0xFFFFFFFB) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Functions USART exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the USART/UART peripheral registers to their default reset values. + * @param USARTx: Parameter to select the UxART peripheral. + * @retval None + ************************************************************************************************************/ +void USART_DeInit(HT_USART_TypeDef* USARTx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + u32 uIPAddr = (u32)USARTx; + + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + switch (uIPAddr) + { + case HT_USART0_BASE: + { + RSTCUReset.Bit.USART0 = 1; + break; + } + #if !(LIBCFG_NO_USART1) + case HT_USART1_BASE: + { + RSTCUReset.Bit.USART1 = 1; + break; + } + #endif + case HT_UART0_BASE: + { + RSTCUReset.Bit.UART0 = 1; + break; + } + case HT_UART1_BASE: + { + RSTCUReset.Bit.UART1 = 1; + break; + } + } + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the USART/UART peripheral according to the specified parameters in the USART_InitStruct. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_Init(HT_USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + u32 uIPClock = 0; + u32 uIPAddr = (u32)USARTx; + + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + Assert_Param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + Assert_Param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + Assert_Param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + Assert_Param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + + #if (LIBCFG_USART_V01) + USARTx->LCR = (USARTx->LCR & LCR_CLEAR_Mask) | USART_InitStruct->USART_StopBits | + USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity; + + USARTx->MDR = (USARTx->MDR & MDR_CLEAR_Mask) | USART_InitStruct->USART_Mode; + #else + USARTx->CR = (USARTx->CR & CR_CLEAR_Mask) | USART_InitStruct->USART_StopBits | + USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + #endif + + switch (uIPAddr) + { + case HT_USART0_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_USART0); + break; + } + #if !(LIBCFG_NO_USART1) + case HT_USART1_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_USART1); + break; + } + #endif + case HT_UART0_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_UART0); + break; + } + case HT_UART1_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_UART1); + break; + } + } + + USARTx->DLR = uIPClock / (u32)USART_InitStruct->USART_BaudRate; +} + +/*********************************************************************************************************//** + * @brief Fill each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WORDLENGTH_8B; + USART_InitStruct->USART_StopBits = USART_STOPBITS_1; + USART_InitStruct->USART_Parity = USART_PARITY_NO; + USART_InitStruct->USART_Mode = USART_MODE_NORMAL; +} + +/*********************************************************************************************************//** + * @brief USART/UART send data to Tx. + * @param USARTx: Parameter to select the UxART peripheral. + * @param Data: the data to be transmitted. + * @retval None + ************************************************************************************************************/ +void USART_SendData(HT_USART_TypeDef* USARTx, u16 Data) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_DATA(Data)); + + USARTx->DR = Data; +} + +/*********************************************************************************************************//** + * @brief USART/UART receive data from Rx. + * @param USARTx: Parameter to select the UxART peripheral. + * @retval The received data. + ************************************************************************************************************/ +u16 USART_ReceiveData(HT_USART_TypeDef* USARTx) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + return (u16)(USARTx->DR); +} + +/*********************************************************************************************************//** + * @brief Get the specified USART/UART status flags. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_FLAG_x: Specify the flag to be check. + * This parameter can be one of the following values: + * LIBCFG_USART_V01 / LIBCFG_USART_V01_LEGACY: + * @arg USART_FLAG_RXDNE / USART_LSR_RFDR + * @arg USART_FLAG_THRE / USART_LSR_THRE + * @arg USART_FLAG_TXC / USART_LSR_TE + * @arg USART_FLAG_ERR / USART_LSR_ERR + * @arg USART_FLAG_MODIS + * @arg USART_FLAG_TXDE + * @arg USART_FLAG_RXDR + * @arg USART_FLAG_RLSI + * @arg USART_FLAG_TOUT + * HT32F1xxxx: + * @arg USART_FLAG_RXDNE : + * @arg USART_FLAG_OE : + * @arg USART_FLAG_PE : + * @arg USART_FLAG_FE : + * @arg USART_FLAG_BI : + * @arg USART_FLAG_RXDR : + * @arg USART_FLAG_TOUT : + * @arg USART_FLAG_TXDE : + * @arg USART_FLAG_TXC : + * @arg USART_FLAG_RSADD : + * @arg USART_FLAG_CTSC : + * @arg USART_FLAG_CTSS : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus USART_GetFlagStatus(HT_USART_TypeDef* USARTx, u32 USART_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_FLAG(USART_FLAG_x)); + + #if (LIBCFG_USART_V01) + if (USART_FLAG_x & USART_FLAG_FROM_IIR) + { + if (USARTx->IIR == (USART_FLAG_x & (~(USART_FLAG_FROM_IIR)))) + { + return (SET); + } + else + { + return (RESET); + } + } + else + { + #endif + + if ((USARTx->SR & USART_FLAG_x) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } + + #if (LIBCFG_USART_V01) + } + #endif +} + +#if (LIBCFG_USART_V01) +#else +/*********************************************************************************************************//** + * @brief Get the specified USART/UART INT status. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_INT_x: Specify if the USART/UART interrupt source. + * This parameter can be one of the following values: + * @arg USART_INT_RXDR : + * @arg USART_INT_TXDE : + * @arg USART_INT_TXC : + * @arg USART_INT_OE : + * @arg USART_INT_PE : + * @arg USART_INT_FE : + * @arg USART_INT_BI : + * @arg USART_INT_RSADD : + * @arg USART_INT_TOUT : + * @arg USART_INT_CTS : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus USART_GetIntStatus(HT_USART_TypeDef* USARTx, u32 USART_INT_x) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_INT(USART_INT_x)); + + if ((USARTx->IER & USART_INT_x) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified USART/UART flags. + * @param USARTx: where USARTx is the selected USART/UART from the USART/UART peripherals. + * @param USART_Flag: Specify the flag to check. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_OE : + * @arg USART_FLAG_PE : + * @arg USART_FLAG_FE : + * @arg USART_FLAG_BI : + * @arg USART_FLAG_TOUT : + * @arg USART_FLAG_RSADD : + * @arg USART_FLAG_CTSC : + * @retval SET or RESET + ************************************************************************************************************/ +void USART_ClearFlag(HT_USART_TypeDef* USARTx, u32 USART_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_CLEAR_FLAG(USART_Flag)); + + USARTx->SR &= USART_Flag; +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART interrupts. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_INT_x: Specify if the USART/UART interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * LIBCFG_USART_V01 / LIBCFG_USART_V01_LEGACY + * @arg USART_INT_RXDR / USART_IER_RDAIE : + * @arg USART_INT_TXDE / USART_IER_THREIE : + * @arg USART_INT_RLSIE / USART_IER_RLSIE : TXC, OE, PE, FE, BI, RSADD + * @arg USART_INT_MSIE / USART_IER_MSIE : + * HT32F1xxxx: + * @arg USART_INT_RXDR : + * @arg USART_INT_TXDE : + * @arg USART_INT_TXC : + * @arg USART_INT_OE : + * @arg USART_INT_PE : + * @arg USART_INT_FE : + * @arg USART_INT_BI : + * @arg USART_INT_RSADD : + * @arg USART_INT_TOUT : + * @arg USART_INT_CTS : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_IntConfig(HT_USART_TypeDef* USARTx, u32 USART_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_INT(USART_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_USART_V01) + if (USART_INT_x & USART_INT_TOUT) + { + if (NewState != DISABLE) + { + USARTx->TPR |= USART_TIMEOUT_ON; + } + else + { + USARTx->TPR &= USART_TIMEOUT_OFF; + } + } + #endif + + if (NewState != DISABLE) + { + USARTx->IER |= USART_INT_x; + } + else + { + USARTx->IER &= ~USART_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART Tx/Rx. + * @param USARTx: Parameter to select the USART peripheral. + * @param TxRx: This parameter can be USART_CMD_TX or USART_CMD_RX. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_TxRxCmd(HT_USART_TypeDef* USARTx, u32 TxRx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_USART_V01) + if (NewState != DISABLE) + { + USARTx->FCR |= (USART_EN_ON << TxRx); + } + else + { + USARTx->FCR &= ~(USART_EN_ON << TxRx); + } + #else + if (NewState != DISABLE) + { + USARTx->CR |= (USART_EN_ON << TxRx); + } + else + { + USARTx->CR &= ~(USART_EN_ON << TxRx); + } + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART PDMA interface. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_PDMAREQ: specify the USART/UART PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg USART_PDMAREQ_TX + * @arg USART_PDMAREQ_RX + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_PDMACmd(HT_USART_TypeDef* USARTx, u32 USART_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_PDMA_REQ(USART_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_USART_V01) + if (NewState != DISABLE) + { + USARTx->MDR |= USART_PDMAREQ; + } + else + { + USARTx->MDR &= ~USART_PDMAREQ; + } + #else + if (NewState != DISABLE) + { + USARTx->CR |= USART_PDMAREQ; + } + else + { + USARTx->CR &= ~USART_PDMAREQ; + } + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART break control function. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_ForceBreakCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_USART_V01) + if (NewState != DISABLE) + { + USARTx->LCR |= USART_BREAK_ON; + } + else + { + USARTx->LCR &= USART_BREAK_OFF; + } + #else + if (NewState != DISABLE) + { + USARTx->CR |= USART_BREAK_ON; + } + else + { + USARTx->CR &= USART_BREAK_OFF; + } + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART stick parity function. + * @param USARTx: Parameter to select the UxART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_StickParityCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_USART_V01) + if (NewState != DISABLE) + { + USARTx->LCR |= USART_SPE_ON; + } + else + { + USARTx->LCR &= USART_SPE_OFF; + } + #else + if (NewState != DISABLE) + { + USARTx->CR |= USART_SPE_ON | USART_PBE_ON; + } + else + { + USARTx->CR &= USART_SPE_OFF; + } + #endif +} + +/*********************************************************************************************************//** + * @brief Configure the stick parity value of the USART/UART. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_StickParity: Specify the stick parity of the USART/UART. + * This parameter can be one of the following values: + * @arg USART_STICK_LOW + * @arg USART_STICK_HIGH + * @retval None + ************************************************************************************************************/ +void USART_StickParityConfig(HT_USART_TypeDef * USARTx, u32 USART_StickParity) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_STICK_PARITY(USART_StickParity)); + + #if (LIBCFG_USART_V01) + if (USART_StickParity != USART_STICK_HIGH) + { + USARTx->LCR |= USART_STICK_LOW; + } + else + { + USARTx->LCR &= USART_STICK_HIGH; + } + #else + if (USART_StickParity != USART_STICK_HIGH) + { + USARTx->CR |= USART_STICK_LOW; + } + else + { + USARTx->CR &= USART_STICK_HIGH; + } + #endif +} + +/*********************************************************************************************************//** + * @brief Set the specified USART guard time. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_GuardTime: Specify the guard time. + * @retval None + ************************************************************************************************************/ +void USART_SetGuardTime(HT_USART_TypeDef* USARTx, u32 USART_GuardTime) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_GUARD_TIME(USART_GuardTime)); + + USARTx->TPR = (USARTx->TPR & TPR_TG_Mask) | (USART_GuardTime << 0x08); +} + +/*********************************************************************************************************//** + * @brief Configure the Tx/Rx FIFO Interrupt Trigger Level. + * @param USARTx: Parameter to select the USART peripheral. + * @param TxRx: This parameter can be USART_CMD_TX or USART_CMD_RX. + * @param USART_tl: Specify the USART Tx/Rx FIFO interrupt trigger level. + * This parameter can be one of the following values: + * For LIBCFG_USART_V01: + * @arg USART_RXTL_01 + * @arg USART_RXTL_04 + * @arg USART_RXTL_08 + * @arg USART_RXTL_14 + * @arg USART_TXTL_00 + * @arg USART_TXTL_02 + * @arg USART_TXTL_04 + * @arg USART_TXTL_08 + * For HT32F1xxxx: + * @arg USART_RXTL_01 + * @arg USART_RXTL_02 + * @arg USART_RXTL_04 + * @arg USART_RXTL_06 + * @arg USART_TXTL_00 + * @arg USART_TXTL_02 + * @arg USART_TXTL_04 + * @arg USART_TXTL_06 + * @retval None + ************************************************************************************************************/ +void USART_TXRXTLConfig(HT_USART_TypeDef* USARTx, u32 TxRx, u32 USART_tl) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_TL(USART_tl)); + + USARTx->FCR = (USARTx->FCR & ~(FCR_TL_Mask << (TxRx * 2))) | (USART_tl << (TxRx * 2)); +} + +/*********************************************************************************************************//** + * @brief Set the USART FIFO time-out value. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_TimeOut: Specify the time-out value. + * @retval None + ************************************************************************************************************/ +void USART_SetTimeOutValue(HT_USART_TypeDef* USARTx, u32 USART_TimeOut) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_TIMEOUT(USART_TimeOut)); + + #if (LIBCFG_USART_V01) + USARTx->TPR = (USARTx->TPR & TPR_RXTOIC_Mask) | USART_TimeOut; + #else + USARTx->TPR = (USARTx->TPR & TPR_RXTOIC_Mask) | USART_TimeOut | USART_RXTOEN_ON; + #endif +} + +/*********************************************************************************************************//** + * @brief Clear both the write and read point in USART Tx FIFO or Rx FIFO. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_FIFODirection: Determine TX FIFO or Rx FIFO that is to be reset. + * This parameter can be any combination of the following values: + * @arg USART_FIFO_TX + * @arg USART_FIFO_RX + * @retval None + ************************************************************************************************************/ +void USART_FIFOReset(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_FIFO_DIRECTION(USART_FIFODirection)); + + USARTx->FCR |= USART_FIFODirection; +} + +/*********************************************************************************************************//** + * @brief Return the status of specified USART FIFO. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_FIFODirection: specify the FIFO that is to be check. + * This parameter can be one of the following values: + * @arg USART_FIFO_TX + * @arg USART_FIFO_RX + * @retval The number of data in Tx FIFO or Rx FIFO. + ************************************************************************************************************/ +u8 USART_GetFIFOStatus(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_FIFO_DIRECTION(USART_FIFODirection)); + + #if (LIBCFG_USART_V01) + if (USART_FIFODirection == USART_FIFO_TX) + { + return (u8)(USARTx->FSR & 0x1F); + } + else + { + return (u8)((USARTx->FSR & 0x1F00) >> 8); + } + #else + if (USART_FIFODirection == USART_FIFO_TX) + { + return (u8)((USARTx->FCR & 0xF0000) >> 16); + } + else + { + return (u8)((USARTx->FCR & 0xF000000) >> 24); + } + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART hardware flow control. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_HardwareFlowControlCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_USART_V01) + if (NewState != DISABLE) + { + USARTx->MCR |= USART_HFCEN_ON; + } + else + { + USARTx->MCR &= USART_HFCEN_OFF; + } + #else + if (NewState != DISABLE) + { + USARTx->CR |= USART_HFCEN_ON; + } + else + { + USARTx->CR &= USART_HFCEN_OFF; + } + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART IrDA interface. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_IrDACmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->ICR |= USART_IRDA_ON; + } + else + { + USARTx->ICR &= USART_IRDA_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Configure the USART IrDA interface. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_IrDAMode: Specify the USART IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IRDA_LOWPOWER + * @arg USART_IRDA_NORMAL + * @retval None + ************************************************************************************************************/ +void USART_IrDAConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDAMode) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + if (USART_IrDAMode != USART_IRDA_NORMAL) + { + USARTx->ICR |= USART_IRDA_LOWPOWER; + } + else + { + USARTx->ICR &= USART_IRDA_NORMAL; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified USART IrDA prescaler. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_IrDAPrescaler: Specify the USART IrDA prescaler. + * @retval None + ************************************************************************************************************/ +void USART_SetIrDAPrescaler(HT_USART_TypeDef* USARTx, u32 USART_IrDAPrescaler) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_IRDA_PRESCALER(USART_IrDAPrescaler)); + + USARTx->ICR = (USARTx->ICR & ICR_IRDAPSC_Mask) | (USART_IrDAPrescaler << 0x08); +} + +/*********************************************************************************************************//** + * @brief Enable the IrDA transmitter or receiver. + * @param USARTx: Parameter to select the USART peripheral, x can be 0 or 1. + * @param USART_IrDADirection: Specify the USART IrDA direction select. + * This parameter can be one of the following values: + * @arg USART_IRDA_TX + * @arg USART_IRDA_RX + * @retval None + ************************************************************************************************************/ +void USART_IrDADirectionConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDADirection) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_IRDA_DIRECTION(USART_IrDADirection)); + + if (USART_IrDADirection != USART_IRDA_RX) + { + USARTx->ICR |= USART_IRDA_TX; + } + else + { + USARTx->ICR &= USART_IRDA_RX; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable inverting serial output/input function of IrDA on the specified USART. + * @param USARTx: Parameter to select the USART peripheral. + * @param inout: This parameter can be USART_CMD_OUT or USART_CMD_IN. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_IrDAInvtCmd(HT_USART_TypeDef* USARTx, u32 inout, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->ICR |= (USART_INV_ON << inout); + } + else + { + USARTx->ICR &= ~(USART_INV_ON << inout); + } +} + +/*********************************************************************************************************//** + * @brief Configure the polarity of USART RS485 transmitter enable signal. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_RS485Polarity: Specify the polarity of USART RS485 Tx enable signal. + * This parameter can be one of the following values: + * @arg USART_RS485POL_LOW + * @arg USART_RS485POL_HIGH + * @retval None + ************************************************************************************************************/ +void USART_RS485TxEnablePolarityConfig(HT_USART_TypeDef* USARTx, u32 USART_RS485Polarity) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_RS485_POLARITY(USART_RS485Polarity)); + + if (USART_RS485Polarity != USART_RS485POLARITY_HIGH) + { + USARTx->RCR |= USART_RS485POLARITY_LOW; + } + else + { + USARTx->RCR &= USART_RS485POLARITY_HIGH; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART RS485 normal multi-drop operation mode. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_RS485NMMCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->RCR |= USART_RS485NMM_ON; + } + else + { + USARTx->RCR &= USART_RS485NMM_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART RS485 normal multi-drop operation mode. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_RS485AADCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->RCR |= USART_RS485AAD_ON; + } + else + { + USARTx->RCR &= USART_RS485AAD_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified USART RS485 address match value. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_AddressMatchValue: specify the USART RS485 address match value. + * @retval None + ************************************************************************************************************/ +void USART_SetAddressMatchValue(HT_USART_TypeDef* USARTx, u32 USART_AddressMatchValue) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_ADDRESS_MATCH_VALUE(USART_AddressMatchValue)); + + USARTx->RCR = (USARTx->RCR & RS485CR_ADDM_Mask) | (u32)(USART_AddressMatchValue << 0x08); +} + +/*********************************************************************************************************//** + * @brief Initialize the clock of the USART peripheral according to the specified parameters + * in the USART_ClockInitStruct. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_SynClock_InitStruct: pointer to a USART_SynClock_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_SynClockInit(HT_USART_TypeDef* USARTx, USART_SynClock_InitTypeDef* USART_SynClock_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_SYNCHRONOUS_CLOCK(USART_SynClock_InitStruct->USART_ClockEnable)); + Assert_Param(IS_USART_SYNCHRONOUS_PHASE(USART_SynClock_InitStruct->USART_ClockPhase)); + Assert_Param(IS_USART_SYNCHRONOUS_POLARITY(USART_SynClock_InitStruct->USART_ClockPolarity)); + Assert_Param(IS_USART_TRANSFER_MODE(USART_SynClock_InitStruct->USART_TransferSelectMode)); + + USARTx->SCR = USART_SynClock_InitStruct->USART_ClockEnable | USART_SynClock_InitStruct->USART_ClockPhase | + USART_SynClock_InitStruct->USART_ClockPolarity; + + #if (LIBCFG_USART_V01) + USARTx->MDR = (USARTx->MDR & TRSM_CLEAR_Mask) | USART_SynClock_InitStruct->USART_TransferSelectMode; + #else + USARTx->CR = (USARTx->CR & TRSM_CLEAR_Mask) | USART_SynClock_InitStruct->USART_TransferSelectMode; + #endif +} + +/*********************************************************************************************************//** + * @brief Fill each USART_SynClockInitStruct member with its default value. + * @param USART_SynClock_InitStruct: pointer to a USART_SynClock_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_SynClockStructInit(USART_SynClock_InitTypeDef* USART_SynClock_InitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_SynClock_InitStruct->USART_ClockEnable = USART_SYN_CLOCK_DISABLE; + USART_SynClock_InitStruct->USART_ClockPhase = USART_SYN_CLOCK_PHASE_FIRST; + USART_SynClock_InitStruct->USART_ClockPolarity = USART_SYN_CLOCK_POLARITY_LOW; + USART_SynClock_InitStruct->USART_TransferSelectMode = USART_LSB_FIRST; +} + +#if (LIBCFG_USART_V01) +/*********************************************************************************************************//** + * @brief Force pin DTR/RTS to low or high state. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_ModemPin: Specify the USART modem pin to be forced. + * This parameter can be one of the following values: + * @arg USART_MODEM_DTR + * @arg USART_MODEM_RTS + * @param USART_ModemState: the USART modem pin state. + * This parameter can be one of the following values: + * @arg USART_MODEMSTATE_HIGH + * @arg USART_MODEMSTATE_LOW + * @retval None + ************************************************************************************************************/ +void USART_ForceModemPinState(HT_USART_TypeDef* USARTx, u32 USART_ModemPin, u32 USART_ModemState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_MODEM_PIN(USART_ModemPin)); + Assert_Param(IS_USART_MODEM_STATE(USART_ModemState)); + + if (USART_ModemState != USART_MODEMSTATE_HIGH) + { + USARTx->MCR |= USART_MODEMSTATE_LOW << USART_ModemPin; + } + else + { + USARTx->MCR &= ~(USART_MODEMSTATE_HIGH << USART_ModemPin); + } +} + +/*********************************************************************************************************//** + * @brief Get Modem status. + * @param USARTx: Parameter to select the USART peripheral. + * @retval The current status of Modem Status Register. + ************************************************************************************************************/ +u8 USART_GetModemStatus(HT_USART_TypeDef* USARTx) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + return (u8)(USARTx->MSR); +} + +#if 0 +/*********************************************************************************************************//** + * @brief Enable or Disable time out interrupt of the USART. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_TimeOutIntConfig(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->TPR |= USART_TIMEOUT_ON; + } + else + { + USARTx->TPR &= USART_TIMEOUT_OFF; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Get Interrupt ID value. + * @param USARTx: Parameter to select the USART peripheral. + * @retval The interrupt ID of USART. + * @arg USART_IID_RLS + * @arg USART_IID_RDA + * @arg USART_IID_CTI + * @arg USART_IID_THRE + * @arg USART_IID_MS + * @arg USART_IID_NON + ************************************************************************************************************/ +u8 USART_GetIntID(HT_USART_TypeDef* USARTx) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + return (u8)(USARTx->IIR); +} + +/*********************************************************************************************************//** + * @brief Get Line Status Value. + * @param USARTx: Parameter to select the USART peripheral. + * @retval The vlaue of LSR. + ************************************************************************************************************/ +u32 USART_GetLineStatusValue(HT_USART_TypeDef* USARTx) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + return (u8)(USARTx->LSR); +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_usbd.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_usbd.c new file mode 100644 index 00000000000..307c5f3d2c2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_usbd.c @@ -0,0 +1,796 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_usbd.c + * @version $Rev:: 1670 $ + * @date $Date:: 2019-04-09 #$ + * @brief The USB Device Peripheral Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32f1xxxx_usbdchk.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup USBDevice USB Device + * @brief USB Device driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Constant USB Device private constants + * @{ + */ +#define TCR_MASK (0x1FF) +#define EPLEN_MASK ((u32)0x000FFC00) +#define EPBUFA_MASK ((u32)0x000003FF) +#define ISR_EPn_OFFSET (8) + +/* USB Control and Status Register (USBCSR) */ +#define FRES ((u32)0x00000002) /* Force USB Reset */ +#define PDWN ((u32)0x00000004) /* Power Down */ +#define LPMODE ((u32)0x00000008) /* Low-power Mode */ +#define GENRSM ((u32)0x00000020) /* Generate Resume */ +#define ADRSET ((u32)0x00000100) /* Device Address Setting */ +#define SRAMRSTC ((u32)0x00000200) /* USB SRAM reset condition */ +#define DPPUEN ((u32)0x00000400) /* DP Pull Up Enable */ +#define DPWKEN ((u32)0x00000800) /* DP Wake Up Enable */ + +#define EPDIR_IN (1) +#define EPDIR_OUT (0) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Variable USB Device private variables + * @{ + */ +static u32 gIsFirstPowered = TRUE; +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Macro USB Device private macros + * @{ + */ +#ifndef USBDCore_LowPower + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#endif +/** + * @brief Convert Byte length to Word length + */ +#define ByteLen2WordLen(n) ((n + 3) >> 2) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void _USBD_CopyMemory(u32 *pFrom, u32 *pTo, u32 len); +static HT_USBEP_TypeDef * _USBD_GetEPTnAddr(USBD_EPTn_Enum USBD_EPTn); +static void _delay(u32 nCount); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Functions USB Device exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Pre initialization for USBD_Init function. + * @param pDriver: USB initialization structure + * @retval None + ***********************************************************************************************************/ +void USBD_PreInit(USBD_Driver_TypeDef *pDriver) +{ + pDriver->uInterruptMask = _UIER_ALL; + + pDriver->ept[USBD_EPT0].CFGR.word = _EP0_CFG; + pDriver->ept[USBD_EPT0].IER = _EP0_IER; + + #if (_EP1_ENABLE == 1) + pDriver->ept[USBD_EPT1].CFGR.word = _EP1_CFG; + pDriver->ept[USBD_EPT1].IER = _EP1_IER; + #endif + + #if (_EP2_ENABLE == 1) + pDriver->ept[USBD_EPT2].CFGR.word = _EP2_CFG; + pDriver->ept[USBD_EPT2].IER = _EP2_IER; + #endif + + #if (_EP3_ENABLE == 1) + pDriver->ept[USBD_EPT3].CFGR.word = _EP3_CFG; + pDriver->ept[USBD_EPT3].IER = _EP3_IER; + #endif + + #if (_EP4_ENABLE == 1) + pDriver->ept[USBD_EPT4].CFGR.word = _EP4_CFG; + pDriver->ept[USBD_EPT4].IER = _EP4_IER; + #endif + + #if (_EP5_ENABLE == 1) + pDriver->ept[USBD_EPT5].CFGR.word = _EP5_CFG; + pDriver->ept[USBD_EPT5].IER = _EP5_IER; + #endif + + #if (_EP6_ENABLE == 1) + pDriver->ept[USBD_EPT6].CFGR.word = _EP6_CFG; + pDriver->ept[USBD_EPT6].IER = _EP6_IER; + #endif + + #if (_EP7_ENABLE == 1) + pDriver->ept[USBD_EPT7].CFGR.word = _EP7_CFG; + pDriver->ept[USBD_EPT7].IER = _EP7_IER; + #endif + + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Peripheral initialization. + * @param pDriver: USB initialization structure + * @retval None + ***********************************************************************************************************/ +void USBD_Init(u32 *pDriver) +{ + USBD_Driver_TypeDef *pDrv = (USBD_Driver_TypeDef *)pDriver; + + /* Init USB Device Driver struct */ + USBD_PreInit(pDrv); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Internal DP pull up. + * @param NewState: ENABLE or DISABLE + * @retval None + ***********************************************************************************************************/ +void USBD_DPpullupCmd(ControlStatus NewState) +{ + (NewState == ENABLE)?(HT_USB->CSR |= DPPUEN):(HT_USB->CSR &= ~DPPUEN); +} + +/*********************************************************************************************************//** + * @brief USB Device Wake Up when DP is high level. + * @param NewState: ENABLE or DISABLE + * @retval None + ***********************************************************************************************************/ +void USBD_DPWakeUpCmd(ControlStatus NewState) +{ + (NewState == ENABLE)?(HT_USB->CSR |= DPWKEN):(HT_USB->CSR &= ~DPWKEN); +} + +/*********************************************************************************************************//** + * @brief USB Device Peripheral deinitialization. + * @retval None + ***********************************************************************************************************/ +void USBD_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.USBD = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); + + return; +} + +/*********************************************************************************************************//** + * @brief USB power up procedure. + * @retval None + ***********************************************************************************************************/ +void USBD_PowerUp(u32 *pDriver, u32 uIsSelfPowered) +{ + USBD_Driver_TypeDef *pDrv = (USBD_Driver_TypeDef *)pDriver; + + if (gIsFirstPowered == TRUE) + { + gIsFirstPowered = FALSE; + + if (HT_USB->CSR & 0x40) + { + HT_USB->CSR = (DPPUEN | LPMODE | PDWN); + while((HT_USB->ISR & URSTIE) == 0); + HT_USB->ISR = 0xFFFFFFFF; + if (uIsSelfPowered == FALSE) + { + USBDCore_LowPower(); + } + USBD_EnableINT(pDrv->uInterruptMask); + } + else + { + HT_USB->CSR = (DPWKEN | DPPUEN | LPMODE | PDWN); + while((HT_USB->ISR & URSTIE) == 0); + HT_USB->ISR = 0xFFFFFFFF; + if (uIsSelfPowered == FALSE) + { + USBDCore_LowPower(); + } + USBD_DPWakeUpCmd(DISABLE); + USBD_EnableINT(pDrv->uInterruptMask); + USBD_DPpullupCmd(DISABLE); + _delay(200); + USBD_DPpullupCmd(ENABLE); + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief Enter USB Device Power Down mode. + * @retval None + ***********************************************************************************************************/ +void USBD_PowerOff(void) +{ + HT_USB->CSR |= (LPMODE | PDWN); + return; +} + +/*********************************************************************************************************//** + * @brief Exit USB Device Power Down mode. + * @retval None + ***********************************************************************************************************/ +void USBD_PowerOn(void) +{ + HT_USB->CSR |= 0x00001000; + HT_USB->CSR &= 0x00001400; + return; +} + +/*********************************************************************************************************//** + * @brief USB SRAM reset condition. + * @param NewState: ENABLE or DISABLE + * @retval None + ***********************************************************************************************************/ +void USBD_SRAMResetConditionCmd(ControlStatus NewState) +{ + (NewState == ENABLE)?(HT_USB->CSR |= SRAMRSTC):(HT_USB->CSR &= ~SRAMRSTC); +} + +/*********************************************************************************************************//** + * @brief Disable Default pull resistance of D+ and D-. + * @retval None + ***********************************************************************************************************/ +void USBD_DisableDefaultPull(void) +{ + HT_USB->CSR = FRES; // Clear PDWN and keep FRES = 1 +} + +/*********************************************************************************************************//** + * @brief Generate a resume request to USB Host for Remote Wakeup function. + * @retval None + ***********************************************************************************************************/ +void USBD_RemoteWakeup(void) +{ + HT_USB->CSR |= GENRSM; + return; +} + +/*********************************************************************************************************//** + * @brief Read Endpoint0 SETUP data from USB Buffer. + * @param pBuffer: Buffer for save SETUP data + * @retval None + ***********************************************************************************************************/ +void USBD_ReadSETUPData(u32 *pBuffer) +{ + u32 *pSrc = (u32 *)HT_USB_SRAM_BASE; + + *pBuffer = *pSrc; + *(pBuffer + 1) = *(pSrc + 1); + return; +} + +/*********************************************************************************************************//** + * @brief Set USB Device address. + * @param address: USB address which specified by Host + * @retval None + ***********************************************************************************************************/ +void USBD_SetAddress(u32 address) +{ + HT_USB->CSR |= ADRSET; + HT_USB->DEVAR = address; + return; +} + +/*********************************************************************************************************//** + * @brief Enable USB Device interrupt. + * @param INTFlag: USB Device global interrupt flag + * @arg UGIE | SOFIE | URSTIE | RSMIE | SUSPIE | ESOFIE + * EP0IE | EP1IE | EP2IE | EP3IE | EP4IE | EP5IE | EP6IE | EP7IE + * @retval None + ***********************************************************************************************************/ +void USBD_EnableINT(u32 INTFlag) +{ + HT_USB->IER |= INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Disable USB Device interrupt. + * @param INTFlag: USB Device global interrupt flag + * @arg UGIE | SOFIE | URSTIE | RSMIE | SUSPIE | ESOFIE + * EP0IE | EP1IE | EP2IE | EP3IE | EP4IE | EP5IE | EP6IE | EP7IE + * @retval None + ***********************************************************************************************************/ +void USBD_DisableINT(u32 INTFlag) +{ + HT_USB->IER &= (~INTFlag); + return; +} + +/*********************************************************************************************************//** + * @brief Get active USB Device interrupt flag. + * @retval USB ISR Flag + ***********************************************************************************************************/ +u32 USBD_GetINT(void) +{ + u32 IER = HT_USB->IER | FRESIE; + return (HT_USB->ISR & IER); +} + +/*********************************************************************************************************//** + * @brief Clear USB Device interrupt flag. + * @param INTFlag: USB Device global interrupt flag + * @arg SOFIF | URSTIF | RSMIF | SUSPIF | ESOFIF + * EP0IF | EP1IF | EP2IF | EP3IF | EP4IF | EP5IF | EP6IF | EP7IF + * @retval None + ***********************************************************************************************************/ +void USBD_ClearINT(u32 INTFlag) +{ + HT_USB->ISR = INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Get USB Endpoint number by interrupt flag. + * @param INTFlag: USB Device global interrupt flag + * @arg SOFIF | URSTIF | RSMIF | SUSPIF | ESOFIF + * EP0IF | EP1IF | EP2IF | EP3IF | EP4IF | EP5IF | EP6IF | EP7IF + * @retval USB Endpoint number from USBD_EPT1 ~ USBD_EPT7 + ***********************************************************************************************************/ +USBD_EPTn_Enum USBD_GetEPTnINTNumber(u32 INTFlag) +{ + s32 i; + for (i = MAX_EP_NUM - 1; i > 0; i--) + { + if ((INTFlag >> (i + ISR_EPn_OFFSET)) & SET) + { + return (USBD_EPTn_Enum)i; + } + } + + return USBD_NOEPT; +} + +/*********************************************************************************************************//** + * @brief USB Device Peripheral initialization for Endpoint. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @param pDriver: USB initialization structure + * @retval None + ***********************************************************************************************************/ +void USBD_EPTInit(USBD_EPTn_Enum USBD_EPTn, u32 *pDriver) +{ + USBD_Driver_TypeDef *pDrv = (USBD_Driver_TypeDef *)pDriver; + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + + USBEPn->CFGR = pDrv->ept[USBD_EPTn].CFGR.word; + USBEPn->IER = pDrv->ept[USBD_EPTn].IER; + + USBEPn->ISR = 0xFFFFFFFF; + + USBD_EPTReset(USBD_EPTn); + + return; +} + +/*********************************************************************************************************//** + * @brief Reset Endpoint Status. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTReset(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + USBEPn->CSR = (USBEPn->CSR) & (DTGTX | DTGRX | NAKRX); + return; +} + +/*********************************************************************************************************//** + * @brief Enable Interrupt for Endpoint. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @param INTFlag: Interrupt flag + * @arg OTRXIE | ODRXIE | ODOVIE | ITRXIE | IDTXIE | NAKIE | STLIE | UERIE | + * STRXIE | SDRXIE | SDERIE | ZLRXIE + * @retval None + ***********************************************************************************************************/ +void USBD_EPTEnableINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag) +{ + _USBD_GetEPTnAddr(USBD_EPTn)->IER = INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Get active USB Device Endpoint interrupt. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval USB Endpoint ISR Flag + ***********************************************************************************************************/ +u32 USBD_EPTGetINT(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + u32 IER = USBEPn->IER; + return (USBEPn->ISR & IER); +} + +/*********************************************************************************************************//** + * @brief Clear Interrupt for Endpoint. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @param INTFlag: Interrupt flag + * @arg OTRXIF | ODRXIF | ODOVIF | ITRXIF | IDTXIF | NAKIF | STLIF | UERIF | + * STRXIF | SDRXIF | SDERIF | ZLRXIF + * @retval None + ***********************************************************************************************************/ +void USBD_EPTClearINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag) +{ + _USBD_GetEPTnAddr(USBD_EPTn)->ISR = INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n Halt status (STLTX or STLRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval Endpoint Halt Status (1: Endpoint is Halt, 0: Endpoint is not Halt) + ***********************************************************************************************************/ +u32 USBD_EPTGetHalt(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + return (((USBEPn->CSR) & STLTX) ? 1 : 0); + } + else + { + return (((USBEPn->CSR) & STLRX) ? 1 : 0); + } +} + +/*********************************************************************************************************//** + * @brief Send STALL on Endpoint n. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTSendSTALL(USBD_EPTn_Enum USBD_EPTn) +{ + _USBD_GetEPTnAddr(USBD_EPTn)->CSR = STLTX; + return; +} + +/*********************************************************************************************************//** + * @brief Set Endpoint n Halt status (STLTX or STLRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTSetHalt(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + +#if 1 + /* Clean STLIF flag, for USBD_EPTWaitSTALLSent function */ + USBEPn->ISR = STLIF; + USBEPn->CSR = (~(USBEPn->CSR)) & (STLTX | STLRX); +#else + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + /* Clean STLIF flag, for USBD_EPTWaitSTALLSent function */ + USBEPn->ISR = STLIF; + /* Set only when STLTX = 0 */ + USBEPn->CSR = (~(USBEPn->CSR)) & STLTX; + } + else + { + /* Set only when STLRX = 0 */ + USBEPn->CSR = (~(USBEPn->CSR)) & STLRX; + } +#endif + + return; +} + +/*********************************************************************************************************//** + * @brief Clear Endpoint n Halt status (STLTX or STLRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTClearHalt(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + +#if 1 + USBEPn->CSR = (USBEPn->CSR) & (STLTX | STLRX); +#else + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + /* Clear only when STLTX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & STLTX; + } + else + { + /* Clear only when STLRX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & STLRX; + } +#endif + + return; +} + +/*********************************************************************************************************//** + * @brief Wait until STALL transmission is finished + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTWaitSTALLSent(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + u32 uSTALLState = (CFGR->EPDIR == EPDIR_IN) ? ((USBEPn->CSR) & STLTX) : ((USBEPn->CSR) & STLRX); + + if (uSTALLState) + { + while ((USBEPn->ISR & STLIF) == 0); + } + + return; +} + +/*********************************************************************************************************//** + * @brief Clear Endpoint n Data toggle bit (DTGTX or DTGRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTClearDTG(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + +#if 1 + USBEPn->CSR = (USBEPn->CSR) & (DTGTX | DTGRX); +#else + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + /* Clear only when DTGTX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & DTGTX; + } + else + { + /* Clear only when DTGRX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & DTGRX; + } +#endif + return; +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n buffer 0 address. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval USB Endpoint buffer 0 address + ***********************************************************************************************************/ +u32 USBD_EPTGetBuffer0Addr(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + return (HT_USB_SRAM_BASE + (USBEPn->CFGR & EPBUFA_MASK)); +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n buffer 1 address. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval USB Endpoint buffer 1 address + ***********************************************************************************************************/ +u32 USBD_EPTGetBuffer1Addr(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + return (HT_USB_SRAM_BASE + (USBEPn->CFGR & EPBUFA_MASK) + USBD_EPTGetBufferLen(USBD_EPTn)); +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n buffer length. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval USB Endpoint buffer length + ***********************************************************************************************************/ +u32 USBD_EPTGetBufferLen(USBD_EPTn_Enum USBD_EPTn) +{ + return ((_USBD_GetEPTnAddr(USBD_EPTn)->CFGR & EPLEN_MASK) >> 10); +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n Transfer Count. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @param USBD_TCR_n: USBD_TCR_0 or USBD_TCR_1 + * @retval Endpoint Transfer Count + ***********************************************************************************************************/ +u32 USBD_EPTGetTransferCount(USBD_EPTn_Enum USBD_EPTn, USBD_TCR_Enum USBD_TCR_n) +{ + return (((_USBD_GetEPTnAddr(USBD_EPTn)->TCR) >> USBD_TCR_n) & TCR_MASK); +} + +/*********************************************************************************************************//** + * @brief Write IN Data from User buffer to USB buffer. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @param pFrom: Source buffer + * @param len: Length for write IN data + * @retval Total length written by this function + ***********************************************************************************************************/ +u32 USBD_EPTWriteINData(USBD_EPTn_Enum USBD_EPTn, u32 *pFrom, u32 len) +{ + u32 bufferlen = USBD_EPTGetBufferLen(USBD_EPTn); + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + u32 EPTnLen; + u32 *pTo; + + EPTnLen = (USBD_EPTn == USBD_EPT0) ? USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTIN):USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTB0); + + if (len <= bufferlen && EPTnLen == 0) + { + pTo = (u32 *)USBD_EPTGetBuffer0Addr(USBD_EPTn); + _USBD_CopyMemory(pFrom, pTo, ByteLen2WordLen(len)); + USBEPn->TCR = len; + USBEPn->CSR = NAKTX; + return len; + } + else + { + return 0; + } +} + +/*********************************************************************************************************//** + * @brief Read OUT Data from USB buffer to User buffer. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @param pTo: Destination memory + * @param len: Length for read OUT data, set as 0 for discard current OUT data in the USB buffer + * @retval Total length read by this function + ***********************************************************************************************************/ +u32 USBD_EPTReadOUTData(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + u32 EPTnLen = 0; + + if (len != 0) + { + EPTnLen = USBD_EPTReadMemory(USBD_EPTn, pTo, len); + } + + if (EPTnLen != 0 || len == 0) + { + USBEPn->CSR = (USBEPn->CSR & NAKRX); + } + + return EPTnLen; +} + +/*********************************************************************************************************//** + * @brief Read memory from endpoint buffer. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @param pTo: Destination buffer + * @param len: Length for read OUT data + * @retval Total length read by this function + ***********************************************************************************************************/ +u32 USBD_EPTReadMemory(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len) +{ + u32 EPTnLen = 0; + u32 *pFrom; + + EPTnLen = (USBD_EPTn == USBD_EPT0) ? USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTOUT):USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTB0); + + if (EPTnLen <= len) + { + pFrom = (USBD_EPTn == USBD_EPT0) ? (u32 *)USBD_EPTGetBuffer1Addr(USBD_EPTn):(u32 *)USBD_EPTGetBuffer0Addr(USBD_EPTn); + _USBD_CopyMemory(pFrom, pTo, ByteLen2WordLen(EPTnLen)); + } + + return EPTnLen; +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Function USB Device private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Copy 32 bits memory from pFrom to pTo. + * @param pFrom: Source buffer + * @param pTo: Destination buffer + * @param len: Copy length + * @retval None + ***********************************************************************************************************/ +static void _USBD_CopyMemory(u32 *pFrom, u32 *pTo, u32 len) +{ + s32 i; + for (i = len - 1; i >= 0; i--) + { + pTo[i] = pFrom[i]; + } + + return; +} + +/*********************************************************************************************************//** + * @brief Convent USBD_EPTn_Enum to USBEP_TypeDef. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval USBEP0 ~ USBEP7 + ***********************************************************************************************************/ +static HT_USBEP_TypeDef * _USBD_GetEPTnAddr(USBD_EPTn_Enum USBD_EPTn) +{ + return ((HT_USBEP_TypeDef *)(HT_USBEP0 + USBD_EPTn)); +} + +/*********************************************************************************************************//** + * @brief Inserts a delay time. + * @param nCount: specifies the delay time length. + * @retval None + ***********************************************************************************************************/ +static void _delay(u32 nCount) +{ + u32 i; + + for (i = 0; i < nCount; i++) + { + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_wdt.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_wdt.c new file mode 100644 index 00000000000..5bd9a98e770 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f1xxxx_wdt.c @@ -0,0 +1,363 @@ +/*********************************************************************************************************//** + * @file ht32f1xxxx_wdt.c + * @version $Rev:: 2797 $ + * @date $Date:: 2022-11-28 #$ + * @brief This file provides all the WDT firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f1xxxx_wdt.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup WDT WDT + * @brief WDT driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Private_Define WDT private definitions + * @{ + */ + +/* WDT Restart Key */ +#define RESTART_KEY ((u32)0x5FA00000) + +/* WDT Protect mask */ +#define PRCT_SET ((u32)0x0000CA35) +#define PRCT_RESET ((u32)0x000035CA) + +/* WDT WDTFIEN mask */ +#define MODE0_WDTFIEN_SET ((u32)0x00001000) +#define MODE0_WDTFIEN_RESET ((u32)0xFFFFEFFF) + +/* WDT WDTRSTEN mask */ +#define MODE0_WDTRETEN_SET ((u32)0x00002000) +#define MODE0_WDTRETEN_RESET ((u32)0xFFFFDFFF) + +/* WDT WDTEN mask */ +#define MODE0_WDTEN_SET ((u32)0x00010000) +#define MODE0_WDTEN_RESET ((u32)0xFFFEFFFF) + +/* WDT WDTLOCK mask */ +#define MODE0_WDTLOCK_SET ((u32)0x00000010) +#define MODE0_WDTLOCK_RESET ((u32)0x00000000) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Exported_Functions WDT exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the WDT peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void WDT_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.WDT = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the WDT. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_Cmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_WDT->MR0 |= MODE0_WDTEN_SET; + } + else + { + HT_WDT->MR0 &= MODE0_WDTEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Configure the WDT to run or halt in sleep and deep sleep1 mode. + * @param WDT_Mode: + * This parameter can be one of the following values: + * @arg MODE0_WDTSHLT_BOTH : WDT runs in sleep and deep sleep1 mode + * @arg MODE0_WDTSHLT_SLEEP : WDT runs in sleep mode + * @arg MODE0_WDTSHLT_HALT : WDT halts in sleep and deep sleep1 mode + * @retval None + ************************************************************************************************************/ +void WDT_HaltConfig(u32 WDT_Mode) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_WDTSHLT_MODE(WDT_Mode)); + + HT_WDT->MR0 = ((WDT_Mode) | (HT_WDT->MR0 & 0x00013FFF)); +} + +#if (LIBCFG_WDT_INT) +/*********************************************************************************************************//** + * @brief Enable or Disable the WDT interrupt when WDT meets underflow or error. + * @param NewState: This parameter can be: ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_IntConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_WDT->MR0 |= MODE0_WDTFIEN_SET; + } + else + { + HT_WDT->MR0 &= MODE0_WDTFIEN_RESET; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the WDT Reset when WDT meets underflow or error. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_ResetCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_WDT->MR0 |= MODE0_WDTRETEN_SET; + } + else + { + HT_WDT->MR0 &= MODE0_WDTRETEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable protection mechanism of the WDT. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_ProtectCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_WDT->PR = PRCT_SET; + } + else + { + HT_WDT->PR = PRCT_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Set reload value of the WDT. + * @param WDT_WDTV : specify the WDT Reload value. + * This parameter must be a number between 0 and 0x0FFF + * @retval None + ************************************************************************************************************/ +void WDT_SetReloadValue(u16 WDT_WDTV) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_RELOAD(WDT_WDTV)); + + HT_WDT->MR0 = WDT_WDTV | (HT_WDT->MR0 & 0x0000F000); +} + +/*********************************************************************************************************//** + * @brief Get the current reload value of the WDT. + * @retval WDT reload value between 0 and 0x0FFF + ************************************************************************************************************/ +u16 WDT_GetReloadValue(void) +{ + return ((u16)(HT_WDT->MR0 & 0xFFF)); +} + +/*********************************************************************************************************//** + * @brief Set delta value of the WDT. + * @param WDT_WDTD : specify the WDT Delta value. + * This parameter must be a number between 0 and 0x0FFF + * @retval None + ************************************************************************************************************/ +void WDT_SetDeltaValue(u16 WDT_WDTD) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_DELTA(WDT_WDTD)); + + HT_WDT->MR1 = (WDT_WDTD | (HT_WDT->MR1 & 0x00007000)); +} + +/*********************************************************************************************************//** + * @brief Get current delta value of the WDT. + * @retval WDT delta value between 0 and 0x0FFF + ************************************************************************************************************/ +u16 WDT_GetDeltaValue(void) +{ + return ((u16)(HT_WDT->MR1 & 0xFFF)); +} + +/*********************************************************************************************************//** + * @brief Set prescaler value of the WDT. + * @param WDT_PRESCALER: specify the WDT Prescaler value. + * This parameter can be one of the following values: + * @arg WDT_PRESCALER_1 : WDT prescaler set to 1 + * @arg WDT_PRESCALER_2 : WDT prescaler set to 2 + * @arg WDT_PRESCALER_4 : WDT prescaler set to 4 + * @arg WDT_PRESCALER_8 : WDT prescaler set to 8 + * @arg WDT_PRESCALER_16 : WDT prescaler set to 16 + * @arg WDT_PRESCALER_32 : WDT prescaler set to 32 + * @arg WDT_PRESCALER_64 : WDT prescaler set to 64 + * @arg WDT_PRESCALER_128 : WDT prescaler set to 128 + * @retval None + ************************************************************************************************************/ +void WDT_SetPrescaler(u16 WDT_PRESCALER) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_PRESCALER(WDT_PRESCALER)); + + HT_WDT->MR1 = (WDT_PRESCALER | (HT_WDT->MR1 & 0x00000FFF)); +} + +/*********************************************************************************************************//** + * @brief Get the current prescaler value of the WDT. + * @retval WDT prescaler value + ************************************************************************************************************/ +u8 WDT_GetPrescaler(void) +{ + u32 tmp; + + tmp = HT_WDT->MR1 & 0x7000; + tmp >>= 12; + return ((u8)0x1 << tmp); +} + +/*********************************************************************************************************//** + * @brief WDT Restart (Reload WDT Counter) + * @retval None + ************************************************************************************************************/ +void WDT_Restart(void) +{ + HT_WDT->CR = RESTART_KEY | 0x1; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified WDT flag has been set. + * @param WDT_FLAG: specify the flag to be check. + * This parameter can be one of the following values: + * @arg WDT_FLAG_UNDERFLOW : WDT underflow active + * @arg WDT_FLAG_ERROR : WDT error active + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus WDT_GetFlagStatus(u32 WDT_FLAG) +{ + u32 statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + Assert_Param(IS_WDT_FLAG(WDT_FLAG)); + + statusreg = HT_WDT->SR; + + if (statusreg != WDT_FLAG) + { + bitstatus = RESET; + } + else + { + bitstatus = SET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the WDTLOCK. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_LockCmd(ControlStatus NewState) +{ + u32 uRegVale; + + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + uRegVale = HT_WDT->CSR; + if (NewState != DISABLE) + { + HT_WDT->CSR |= (MODE0_WDTLOCK_SET | (uRegVale & 0x00000001)); + } + else + { + HT_WDT->CSR &= (MODE0_WDTLOCK_RESET | (uRegVale & 0x00000001)); + } +} + +/*********************************************************************************************************//** + * @brief WDT source select. + * @param WDT_SOURCE: LSI or LSE of the WDT source. + * This parameter can be one of the following values: + * @arg WDT_SOURCE_LSI : + * @arg WDT_SOURCE_LSE : + * @retval None + ************************************************************************************************************/ +void WDT_SourceConfig(u32 WDT_SOURCE) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_SOURCE_SELECT(WDT_SOURCE)); + + if (WDT_SOURCE != WDT_SOURCE_LSE) + { + HT_WDT->CSR = WDT_SOURCE_LSI; + } + else + { + HT_WDT->CSR = WDT_SOURCE_LSE; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f2xxxx_csif.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f2xxxx_csif.c new file mode 100644 index 00000000000..fed68afd333 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ht32f2xxxx_csif.c @@ -0,0 +1,386 @@ +/*********************************************************************************************************//** + * @file ht32f2xxxx_csif.c + * @version $Rev:: 118 $ + * @date $Date:: 2017-06-02 #$ + * @brief This file provides all the CSIF firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f2xxxx_csif.h" + +/** @addtogroup HT32F1xxxx_Peripheral_Driver HT32F1xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CSIF CSIF + * @brief CSIF driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup CSIF_Private_Define CSIF private definitions + * @{ + */ +/* CSIF CSIFEN mask */ +#define ENR_CSIFEN_SET ((u32)0x80000000) +#define ENR_CSIFEN_RESET ((u32)0x00000000) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CSIF_Exported_Functions CSIF exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CSIF peripheral registers to their default reset values. + * @retval None + ***********************************************************************************************************/ +void CSIF_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.CSIF = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initializes the CSIF peripheral according to the specified parameters in the CSIF_BasicInitStruct. + * @param CSIF_BasicInitStruct: pointer to a CSIF_BasicInitTypeDef structure that contains the configuration + * information for the specified CSIF peripheral. + * @retval None + ***********************************************************************************************************/ +void CSIF_BasicInit(CSIF_BasicInitTypeDef* CSIF_BasicInitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_CSIF_FORMAT(CSIF_BasicInitStruct->CSIF_Format)); + Assert_Param(IS_CSIF_VSYNC_TYPE(CSIF_BasicInitStruct->CSIF_VSYNCType)); + Assert_Param(IS_CSIF_HSYNC_TYPE(CSIF_BasicInitStruct->CSIF_HSYNCType)); + Assert_Param(IS_CSIF_SAMPLE_EDGE(CSIF_BasicInitStruct->CSIF_SampleEdge)); + Assert_Param(IS_CSIF_VSYNC_POLARITY(CSIF_BasicInitStruct->CSIF_VSYNCPolarity)); + Assert_Param(IS_CSIF_HSYNC_POLARITY(CSIF_BasicInitStruct->CSIF_HSYNCPolarity)); + Assert_Param(IS_CSIF_LINE_DELAY(CSIF_BasicInitStruct->CSIF_LineDelay)); + Assert_Param(IS_CSIF_FRAME_DELAY(CSIF_BasicInitStruct->CSIF_FrameDelay)); + Assert_Param(IS_CSIF_IMAGE_WIDTH(CSIF_BasicInitStruct->CSIF_ImageWidth)); + Assert_Param(IS_CSIF_IMAGE_HEIGHT(CSIF_BasicInitStruct->CSIF_ImageHeight)); + + /*------------------------ CSIF Control Register Configuration -------------------------------------------*/ + HT_CSIF->CR = CSIF_BasicInitStruct->CSIF_Format | CSIF_BasicInitStruct->CSIF_VSYNCType | CSIF_BasicInitStruct->CSIF_HSYNCType | + CSIF_BasicInitStruct->CSIF_SampleEdge | CSIF_BasicInitStruct->CSIF_VSYNCPolarity | + CSIF_BasicInitStruct->CSIF_HSYNCPolarity | (CSIF_BasicInitStruct->CSIF_LineDelay << 8) | + (CSIF_BasicInitStruct->CSIF_FrameDelay << 16); + + /*------------------------ CSIF Image Width/Height Register Configuration --------------------------------*/ + HT_CSIF->IMGWH = (CSIF_BasicInitStruct->CSIF_ImageWidth-1) | ((CSIF_BasicInitStruct->CSIF_ImageHeight-1) << 16); +} + +/*********************************************************************************************************//** + * @brief Fills each CSIF_BasicInitStruct member with its default value. + * @param CSIF_BasicInitStruct: pointer to an CSIF_BasicInitTypeDef structure which will be initialized. + * @retval None + ***********************************************************************************************************/ +void CSIF_BasicStructInit(CSIF_BasicInitTypeDef* CSIF_BasicInitStruct) +{ + /* Initialize the CSIF_Format member */ + CSIF_BasicInitStruct->CSIF_Format = CSIF_FORMAT_RAWRGB; + + /* Initialize the CSIF_VSYNCType member */ + CSIF_BasicInitStruct->CSIF_VSYNCType = CSIF_VSYNCTYPE_PULSE; + + /* Initialize the CSIF_HSYNCType member */ + CSIF_BasicInitStruct->CSIF_HSYNCType = CSIF_HSYNCTYPE_CONTINUOUS; + + /* Initialize the CSIF_SampleEdge member */ + CSIF_BasicInitStruct->CSIF_SampleEdge = CSIF_SAMPLEEDGE_FALLING; + + /* Initialize the CSIF_VSYNCPolarity member */ + CSIF_BasicInitStruct->CSIF_VSYNCPolarity = CSIF_VSYNCPOLARITY_HIGH; + + /* Initialize the CSIF_HSYNCPolarity member */ + CSIF_BasicInitStruct->CSIF_HSYNCPolarity = CSIF_HSYNCPOLARITY_HIGH; + + /* Initialize the CSIF_LineDelay member */ + CSIF_BasicInitStruct->CSIF_LineDelay = 0; + + /* Initialize the CSIF_FrameDelay member */ + CSIF_BasicInitStruct->CSIF_FrameDelay = 0; + + /* Initialize the CSIF_ImageWidth member */ + CSIF_BasicInitStruct->CSIF_ImageWidth = 0; + + /* Initialize the CSIF_ImageHeight member */ + CSIF_BasicInitStruct->CSIF_ImageHeight = 0; + +} + +/*********************************************************************************************************//** + * @brief Initializes the CSIF peripheral according to the specified parameters in the CSIF_WindowInitStruct. + * @param CSIF_WindowInitStruct: pointer to a CSIF_WindowInitTypeDef structure that contains the configuration + * information for the specified CSIF peripheral. + * @retval None + ***********************************************************************************************************/ +void CSIF_WindowInit(CSIF_WindowInitTypeDef* CSIF_WindowInitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_CSIF_WINDOW(CSIF_WindowInitStruct->CSIF_Window)); + Assert_Param(IS_CSIF_HORSTART_POINT(CSIF_WindowInitStruct->CSIF_HorizontalStartPoint)); + Assert_Param(IS_CSIF_VERSTART_POINT(CSIF_WindowInitStruct->CSIF_VerticalStartPoint)); + Assert_Param(IS_CSIF_WINDOW_WIDTH(CSIF_WindowInitStruct->CSIF_WindowWidth)); + Assert_Param(IS_CSIF_WINDOW_HEIGHT(CSIF_WindowInitStruct->CSIF_WindowHeight)); + + /*------------------------ CSIF Window Capture Register 0 Configuration ----------------------------------*/ + HT_CSIF->WCR0 = CSIF_WindowInitStruct->CSIF_Window | CSIF_WindowInitStruct->CSIF_HorizontalStartPoint | + (CSIF_WindowInitStruct->CSIF_VerticalStartPoint << 16); + + /*------------------------ CSIF Window Capture Register 1 Configuration ----------------------------------*/ + HT_CSIF->WCR1 = (CSIF_WindowInitStruct->CSIF_WindowWidth-1) | ((CSIF_WindowInitStruct->CSIF_WindowHeight-1) << 16); +} + +/*********************************************************************************************************//** + * @brief Fills each CSIF_WindowStructInit member with its default value. + * @param CSIF_WindowInitStruct: pointer to an CSIF_WindowInitTypeDef structure which will be initialized. + * @retval None + ***********************************************************************************************************/ +void CSIF_WindowStructInit(CSIF_WindowInitTypeDef* CSIF_WindowInitStruct) +{ + /* Initialize the CSIF_Window member */ + CSIF_WindowInitStruct->CSIF_Window = CSIF_WINDOW_DISABLE; + + /* Initialize the CSIF_HorizontalStartPoint member */ + CSIF_WindowInitStruct->CSIF_HorizontalStartPoint = 0; + + /* Initialize the CSIF_VerticalStartPoint member */ + CSIF_WindowInitStruct->CSIF_VerticalStartPoint = 0; + + /* Initialize the CSIF_WindowWidth member */ + CSIF_WindowInitStruct->CSIF_WindowWidth = 0; + + /* Initialize the CSIF_WindowHeight member */ + CSIF_WindowInitStruct->CSIF_WindowHeight = 0; +} + +/*********************************************************************************************************//** + * @brief Initializes the CSIF peripheral according to the specified parameters in the CSIF_SubSampleInitStruct. + * @param CSIF_SubSampleInitStruct: pointer to a CSIF_SubSampleInitTypeDef structure that contains the configuration + * information for the specified CSIF peripheral. + * @retval None + ***********************************************************************************************************/ +void CSIF_SubSampleInit(CSIF_SubSampleInitTypeDef* CSIF_SubSampleInitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_CSIF_SUB_SAMPLE(CSIF_SubSampleInitStruct->CSIF_SubSample)); + Assert_Param(IS_CSIF_MASK_LENGTH(CSIF_SubSampleInitStruct->CSIF_ColumnSkipMaskLength)); + Assert_Param(IS_CSIF_MASK_LENGTH(CSIF_SubSampleInitStruct->CSIF_RowSkipMaskLength)); + + /*------------------------ CSIF Row & Column Sub-Sample RegisterConfiguration ----------------------------*/ + HT_CSIF->SMP = CSIF_SubSampleInitStruct->CSIF_SubSample | (CSIF_SubSampleInitStruct->CSIF_ColumnSkipMaskLength << 8) | + (CSIF_SubSampleInitStruct->CSIF_RowSkipMaskLength << 16); + + /*------------------------ CSIF Column Sub-Sample Register Configuration ---------------------------------*/ + HT_CSIF->SMPCOL = CSIF_SubSampleInitStruct->CSIF_ColumnSkipMask; + + /*------------------------ CSIF Row Sub-Sample Register Configuration ------------------------------------*/ + HT_CSIF->SMPROW = CSIF_SubSampleInitStruct->CSIF_RowSkipMask; +} + +/*********************************************************************************************************//** + * @brief Fills each CSIF_SubSampleInitStruct member with its default value + * @param CSIF_SubSampleInitStruct: pointer to an CSIF_SubSampleInitTypeDef structurewhich will be initialized. + * @retval None + ***********************************************************************************************************/ +void CSIF_SunSampleStructInit(CSIF_SubSampleInitTypeDef* CSIF_SubSampleInitStruct) +{ + /* Initialize the CSIF_SubSample member */ + CSIF_SubSampleInitStruct->CSIF_SubSample = CSIF_SUBSAMPLE_DISABLE; + + /* Initialize the CSIF_ColumnSkipMaskLength member */ + CSIF_SubSampleInitStruct->CSIF_ColumnSkipMaskLength = CSIF_MASKLENGTH_32B; + + /* Initialize the CSIF_RowSkipMaskLength member */ + CSIF_SubSampleInitStruct->CSIF_RowSkipMaskLength = CSIF_MASKLENGTH_32B; + + /* Initialize the CSIF_ColumnSkipMask member */ + CSIF_SubSampleInitStruct->CSIF_ColumnSkipMask = 0; + + /* Initialize the CSIF_RowSkipMask member */ + CSIF_SubSampleInitStruct->CSIF_RowSkipMask = 0; +} + +/*********************************************************************************************************//** + * @brief Enables or Disables the CSIF peripheral. + * @param NewState: new state of the CSIF peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void CSIF_Cmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable CSIF peripheral */ + HT_CSIF->ENR = ENR_CSIFEN_SET; + } + else + { + /* Disable CSIF peripheral */ + HT_CSIF->ENR = ENR_CSIFEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enables or Disables the specified CSIF interrupt. + * @param CSIF_Int: specifies if the CSIF interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CSIF_INT_SOFFLG : CSIF start of frame interrupt + * @arg CSIF_INT_EOFFLG : CSIF end of frame interrupt + * @arg CSIF_INT_CAPSTA : CSIF cpature start interrupt + * @arg CSIF_INT_CAPSTS : CSIF capture status interrupt + * @arg CSIF_INT_BADFRAME : CSIF bad frame interrupt + * @arg CSIF_INT_FIFOOVR : CSIF FIFO overrun interrupt + * @arg CSIF_INT_FIFOEMP : CSIF FIFO empty interrupt + * @arg CSIF_INT_FIFOFUL : CSIF FIFO full interrupt + * @arg CSIF_INT_ALL : All CSIF interrupt + * @param NewState: new state of the CSIF interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void CSIF_IntConfig(u32 CSIF_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CSIF_INT(CSIF_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CSIF->IER |= CSIF_Int; + } + else + { + HT_CSIF->IER &= (u32)~CSIF_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified CSIF flag has been set. + * @param CSIF_Flag: specifies the flag that is to be check. + * This parameter can be one of the following values: + * @arg CSIF_FLAG_SOFFLG : CSIF start of frame flag + * @arg CSIF_FLAG_EOFFLG : CSIF end of frame flag + * @arg CSIF_FLAG_CAPSTA : CSIF cpature start flag + * @arg CSIF_FLAG_CAPSTS : CSIF capture status flag + * @arg CSIF_FLAG_BADFRAME : CSIF bad frame fla + * @arg CSIF_FLAG_FIFOOVR : CSIF FIFO overrun flag + * @arg CSIF_FLAG_FIFOEMP : CSIF FIFO empty flag + * @arg CSIF_FLAG_FIFOFUL : CSIF FIFO full flag + * @retval The new state of CSIF_Flag (SET or RESET). + ***********************************************************************************************************/ +FlagStatus CSIF_GetFlagStatus(u32 CSIF_Flag) +{ + u32 statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + Assert_Param(IS_CSIF_FLAG(CSIF_Flag)); + + statusreg = HT_CSIF->SR; + + if ((statusreg & CSIF_Flag) != (u32)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Clear the specified CSIF flag. + * @param CSIF_Flag: specifies the flag to be cleared. + * This parameter can be one of the following values: + * @arg CSIF_FLAG_SOFFLG : CSIF start of frame flag + * @arg CSIF_FLAG_EOFFLG : CSIF end of frame flag + * @arg CSIF_FLAGT_CAPSTA : CSIF cpature start flag + * @arg CSIF_FLAG_CAPSTS : CSIF capture status flag + * @arg CSIF_FLAG_BADFRAME : CSIF bad frame flag + * @retval None + ***********************************************************************************************************/ +void CSIF_ClearFlag(u32 CSIF_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_CSIF_CLEAR_FLAG(CSIF_Flag)); + + HT_CSIF->SR = CSIF_Flag; +} + +/*********************************************************************************************************//** + * @brief Enables or Disables the CSIF Master Clock. + * @param NewState: new state of the CSIF Master Clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void CSIF_MasterClockCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CKCU->AHBCCR |= 0x00000200; + } + else + { + HT_CKCU->AHBCCR &= 0xFFFFFDFF; + } +} + +/*********************************************************************************************************//** + * @brief Sets the CSIF Master Clock Prescaler. + * @param CSIF_Prescaler: specifies the CSIF Master Clock Prescaler value. + * This parameter must be even. + * @retval None + ***********************************************************************************************************/ +void CSIF_SetMasterClockPrescaler(u8 CSIF_Prescaler) +{ + /* Check the parameters */ + Assert_Param(IS_CSIF_PRESCALER(CSIF_Prescaler)); + + HT_CKCU->GCFGR |= (CSIF_Prescaler/2-1) << 24; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/printf.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/printf.c new file mode 100644 index 00000000000..7b4f905013e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/printf.c @@ -0,0 +1,390 @@ +/*********************************************************************************************************//** + * @file printf.c + * @version $Rev:: 5 $ + * @date $Date:: 2017-05-11 #$ + * @brief Print functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup PRINTF printf re-implementation + * @brief printf related functions + * @{ + */ + + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup PRINTF_Private_Macro printf private macros + * @{ + */ +#define vaStart(list, param) list = (char*)((int)¶m + sizeof(param)) +#define vaArg(list, type) ((type *)(list += sizeof(type)))[-1] +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static const char *FormatItem(const char *f, int a); +static void PutRepChar(const char c, int count); +static int PutString(const char *pString); +static int PutStringReverse(const char *pString, int index); +static void PutNumber(int value, int radix, int width, char fill); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup PRINTF_Exported_Functions printf exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Print function. + * @param f: Format string. + * @retval String length. + ************************************************************************************************************/ +signed int printf(const char *f, ...) +{ + char *argP; + int i = 0; + + vaStart(argP, f); + while (*f) + { + if (*f == '%') + { + f = FormatItem(f + 1, vaArg(argP, int)); + } + else + { + fputc(*f++, (FILE *)1); + } + i++; + } + return i; +} + +/*********************************************************************************************************//** + * @brief Put string. + * @param pString: String. + * @retval String length. + ************************************************************************************************************/ +signed int puts(const char *pString) +{ + int i; + i = PutString(pString); + fputc('\n', (FILE *)1); + return i; +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup PRINTF_Private_Function printf private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Format item for print function. + * @param f: Format string. + * @param a: Length of format string. + * @retval Point of string. + ************************************************************************************************************/ +static const char *FormatItem(const char *f, int a) +{ + char c; + int fieldwidth = 0; + int leftjust = FALSE; + int radix = 0; + char fill = ' '; + int i; + + if (*f == '0') + { + fill = '0'; + } + + while ((c = *f++) != 0) + { + if (c >= '0' && c <= '9') + { + fieldwidth = (fieldwidth * 10) + (c - '0'); + } + else + { + switch (c) + { + case '\000': + { + return (--f); + } + case '%': + { + fputc('%', (FILE *)1); + return (f); + } + case '-': + { + leftjust = TRUE; + break; + } + case 'c': + { + if (leftjust) + { + fputc(a & 0x7f, (FILE *)f); + } + if (fieldwidth > 0) + { + PutRepChar(fill, fieldwidth - 1); + } + if (!leftjust) + { + fputc(a & 0x7f, (FILE *)f); + return (f); + } + } + case 's': + { + i = 0; + while (*((char *)(a + i)) !='\0' ) + { + i++; + } + + if (leftjust) + { + PutString((char *)a); + } + + if (fieldwidth > i ) + { + PutRepChar(fill, fieldwidth - i); + } + + if (!leftjust) + { + PutString((char *)a); + } + return (f); + } + case 'l': + { + radix = -10; + f++; + break; + } + case 'd': + case 'i': + { + radix = -10; + break; + } + case 'u': + { + radix = 10; + break; + } + case 'x': + case 'X': + { + radix = 16; + break; + } + case 'o': + { + radix = 8; + break; + } + default: + { + radix = 3; + break; + } + } + } + if (radix) + { + break; + } + } + + if (leftjust) + { + fieldwidth = -fieldwidth; + } + + PutNumber(a, radix, fieldwidth, fill); + + return (f); +} + +/*********************************************************************************************************//** + * @brief Put repeat character. + * @param c: Character. + * @param count: Repeat count + ************************************************************************************************************/ +static void PutRepChar(const char c, int count) +{ + while (count--) + { + fputc(c, (FILE *)1); + } +} + +/*********************************************************************************************************//** + * @brief Put string. + * @param pString: String. + * @retval String length. + ************************************************************************************************************/ +static int PutString(const char *pString) +{ + int i = 0; + while (*pString != '\0') + { + fputc(*pString, (FILE *)1); + pString++; + i++; + } + + return i; +} + +/*********************************************************************************************************//** + * @brief Put string in reversed order. + * @param pString: String. + * @param index: String length + * @retval String length. + ************************************************************************************************************/ +static int PutStringReverse(const char *pString, int index) +{ + int i = 0; + while ((index--) > 0) + { + fputc(pString[index], (FILE *)1); + i++; + } + return i; +} + +/*********************************************************************************************************//** + * @brief Put number. + * @param value: Value of number. + * @param radix: Radix of number. + * @param width: Width of number. + * @param fill: fill character. + ************************************************************************************************************/ +static void PutNumber(int value, int radix, int width, char fill) +{ + char buffer[8]; + int bi = 0; + unsigned int uvalue; + unsigned short digit; + unsigned short left = FALSE; + unsigned short negative = FALSE; + + if (fill == 0) + { + fill = ' '; + } + + if (width < 0) + { + width = -width; + left = TRUE; + } + + if (width < 0 || width > 80) + { + width = 0; + } + + if (radix < 0) + { + radix = -radix; + if (value < 0) + { + negative = TRUE; + value = -value; + } + } + + uvalue = value; + + do + { + if (radix != 16) + { + digit = uvalue % radix; + uvalue = uvalue / radix; + } + else + { + digit = uvalue & 0xf; + uvalue = uvalue >> 4; + } + buffer[bi] = digit + ((digit <= 9) ? '0' : ('A' - 10)); + bi++; + } + while (uvalue != 0); + + if (negative) + { + buffer[bi] = '-'; + bi += 1; + } + + if (width <= bi) + { + PutStringReverse(buffer, bi); + } + else + { + width -= bi; + if (!left) + { + PutRepChar(fill, width); + } + + PutStringReverse(buffer, bi); + + if (left) + { + PutRepChar(fill, width); + } + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/syscalls.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/syscalls.c new file mode 100644 index 00000000000..b78500264e0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/syscalls.c @@ -0,0 +1,127 @@ +/*********************************************************************************************************//** + * @file syscalls.c + * @version $Rev:: 2904 $ + * @date $Date:: 2023-03-27 #$ + * @brief Implementation of system call related functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include +#include +#include +#include + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup SYSCALLS System call functions + * @brief System call functions for GNU toolchain + * @{ + */ + + +/* Global variables ----------------------------------------------------------------------------------------*/ +/** @defgroup SYSCALLS_Global_Variable System call global variables + * @{ + */ +#undef errno +extern int errno; +extern int _end; +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SYSCALLS_Exported_Functions System call exported functions + * @{ + */ +caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char *prev_heap; + + if (heap == NULL) + { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t) prev_heap; +} + +int link(char *old, char *new) { +return -1; +} + +int _close(int fd) +{ + return -1; +} + +int _fstat(int fd, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int fd) +{ + return 1; +} + +int _lseek(int fd, int ptr, int dir) +{ + return 0; +} + +int _read(int fd, char *ptr, int len) +{ + return 0; +} + +int _write(int fd, char *ptr, int len) +{ + return len; +} + +void abort(void) +{ + /* Abort called */ + while (1); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.c new file mode 100644 index 00000000000..a90caeb9861 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.c @@ -0,0 +1,426 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_class.c + * @version $Rev:: 11 $ + * @date $Date:: 2017-05-15 #$ + * @brief The USB Device Class. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_usbd_core.h" +#include "ht32_usbd_class.h" + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDClass USB Device Class + * @brief USB Device Class + * @{ + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Private_Define USB Device Class private definitions + * @{ + */ +#define CLASS_REQ_01_CMD1 (u16)(0x1 << 8) +#define CLASS_REQ_02_CMD2 (u16)(0x2 << 8) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void USBDClass_MainRoutine(u32 uPara); +static void USBDClass_ClassProcess(void); +static void USBDClass_EPT1Process(void); +static void USBDClass_EPT2Process(void); + +static void USBDClass_Reset(u32 uPara); +static void USBDClass_StartOfFrame(u32 uPara); + +static void USBDClass_Standard_GetDescriptor(USBDCore_Device_TypeDef *pDev); +static void USBDClass_Standard_SetInterface(USBDCore_Device_TypeDef *pDev); +static void USBDClass_Standard_GetInterface(USBDCore_Device_TypeDef *pDev); + +static void USBDClass_Request(USBDCore_Device_TypeDef *pDev); + +static void USBDClass_CMD1(USBDCore_Device_TypeDef *pDev); +static void USBDClass_CMD2(USBDCore_Device_TypeDef *pDev); + +static void USBDClass_Endpoint1(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint2(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint3(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint4(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint5(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint6(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint7(USBD_EPTn_Enum EPTn); + +/* Global Function -----------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Exported_Functions USB Device Class exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Class initialization. + * @param pClass: pointer of USBDCore_Class_TypeDef + * @retval None + ***********************************************************************************************************/ +void USBDClass_Init(USBDCore_Class_TypeDef *pClass) +{ + pClass->CallBack_MainRoutine.func = USBDClass_MainRoutine; + //pClass->CallBack_MainRoutine.uPara = (u32)NULL; + + pClass->CallBack_Reset.func = USBDClass_Reset; + pClass->CallBack_Reset.uPara = (u32)NULL; + + pClass->CallBack_StartOfFrame.func = USBDClass_StartOfFrame; + pClass->CallBack_StartOfFrame.uPara = (u32)NULL; + + pClass->CallBack_ClassGetDescriptor = USBDClass_Standard_GetDescriptor; + pClass->CallBack_ClassSetInterface = USBDClass_Standard_SetInterface; + pClass->CallBack_ClassGetInterface = USBDClass_Standard_GetInterface; + + pClass->CallBack_ClassRequest = USBDClass_Request; + pClass->CallBack_EPTn[1] = USBDClass_Endpoint1; + pClass->CallBack_EPTn[2] = USBDClass_Endpoint2; + pClass->CallBack_EPTn[3] = USBDClass_Endpoint3; + pClass->CallBack_EPTn[4] = USBDClass_Endpoint4; + pClass->CallBack_EPTn[5] = USBDClass_Endpoint5; + pClass->CallBack_EPTn[6] = USBDClass_Endpoint6; + pClass->CallBack_EPTn[7] = USBDClass_Endpoint7; + + #ifdef RETARGET_IS_USB + pClass->CallBack_EPTn[RETARGET_RX_EPT] = SERIAL_USBDClass_RXHandler; + #endif + + return; +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Private_Functions USB Device Class private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Class main routine. + * @param uPara: Parameter for Class main routine + * @retval None + ***********************************************************************************************************/ +static void USBDClass_MainRoutine(u32 uPara) +{ + USBDClass_ClassProcess(); + USBDClass_EPT1INProcess(); + USBDClass_EPT2OUTProcess(); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Process for application. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_ClassProcess(void) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint 1 Process for application. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_EPT1Process(void) +{ + if (gIsEP1 == TRUE) + { + gIsEP1 = FALSE; + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint 2 Process for application. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_EPT2Process(void) +{ + if (gIsEP2 == TRUE) + { + gIsEP2 = FALSE; + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Reset. + * @param uPara: Parameter for Class Reset. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Reset(u32 uPara) +{ + +} + +/*********************************************************************************************************//** + * @brief USB Class Start of Frame. + * @param uPara: Parameter for Class Start of Frame. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_StartOfFrame(u32 uPara) +{ + +} + +/*********************************************************************************************************//** + * @brief USB Device Class Request + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Request(USBDCore_Device_TypeDef *pDev) +{ + u16 uUSBCmd = *((u16 *)(&(pDev->Request))); + +#ifdef RETARGET_IS_USB + SERIAL_USBDClass_Request(pDev); +#endif + + switch (uUSBCmd) + { + /*------------------------------------------------------------------------------------------------------*/ + /* | bRequest | Data transfer direction | Type | Recipient | Data */ + /*------------------------------------------------------------------------------------------------------*/ + + /*------------------------------------------------------------------------------------------------------*/ + /* | 01_CMD1 | 80_Device-to-Host | 20_Class Request | 1_Interface | 01A1h */ + /*------------------------------------------------------------------------------------------------------*/ + case (CLASS_REQ_01_CMDID0 | REQ_DIR_01_D2H | REQ_TYPE_01_CLS | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld CMD0\t[%02d][%02d]\r\n", __DBG_USBCount, pDev->Request.wValueH, pDev->Request.wLength ); + USBDClass_RequestCMD1(pDev); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 02_CMD2 | 00_Host-to-Device | 20_Class Request | 1_Interface | 0221h */ + /*------------------------------------------------------------------------------------------------------*/ + case (CLASS_REQ_02_GET_IDLE | REQ_DIR_00_H2D | REQ_TYPE_01_CLS | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld CMD1\t[%02d][%02d]\r\n", __DBG_USBCount, pDev->Request.wValueH, pDev->Request.wLength ); + USBDClass_RequestCMD2(pDev); + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Class Standard Request - GET_DESCRIPTOR + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Standard_GetDescriptor(USBDCore_Device_TypeDef *pDev) +{ + u32 type = pDev->Request.wValueH; + + switch (type) + { + case DESC_TYPE_01_XXX + { + pDev->Transfer.pData = (uc8 *)(__BUFFER_POINTER__); + pDev->Transfer.sByteLength = DESC_LEN_XXX; + pDev->Transfer.Action = USB_ACTION_DATAIN; + break; + } + case DESC_TYPE_02_XXX: + { + pDev->Transfer.pData = (uc8 *)(__BUFFER_POINTER__); + pDev->Transfer.sByteLength = DESC_LEN_XXX; + pDev->Transfer.Action = USB_ACTION_DATAIN; + break; + } + } /* switch (type) */ + + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Class Standard Request - SET_INTERFACE + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Standard_SetInterface(USBDCore_Device_TypeDef *pDev) +{ + +} + +/*********************************************************************************************************//** + * @brief USB Device Class Standard Request - GET_INTERFACE + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Standard_GetInterface(USBDCore_Device_TypeDef *pDev) +{ + +} + + + +/*********************************************************************************************************//** + * @brief USB Device Class Request - CMD1 + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_CMD1(USBDCore_Device_TypeDef *pDev) +{ + /* Add your own Class request function here.... + For example.... + + u32 uReportID = pDev->Request.wValueL; + u32 uInterface = pDev->Request.wIndex; + + pDev->Transfer.pData = (uc8 *)&(__IDLE_DURATION_BUFFER[uReportID]); + pDev->Transfer.sByteLength = 1; + pDev->Transfer.Action= USB_ACTION_DATAIN; + + */ + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Class Request - CMD2 + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_CMD2(USBDCore_Device_TypeDef *pDev) +{ + /* Add your own Class request function here.... + For example.... + + u32 uReportID = pDev->Request.wValueL; + u32 uInterface = pDev->Request.wIndex; + + pDev->Transfer.pData = (uc8 *)&(__IDLE_DURATION_BUFFER[uReportID]); + pDev->Transfer.sByteLength = 1; + pDev->Transfer.Action= USB_ACTION_DATAIN; + + */ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint1(USBD_EPTn_Enum EPTn) +{ + gIsEP1 = TRUE; + + __DBG_USBPrintf("%06ld EP1\t[%02d]", ++__DBG_USBCount, (int)USBDCore_EPTGetBufferLen(EPTn)); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint2(USBD_EPTn_Enum EPTn) +{ + gIsEP2 = TRUE; + __DBG_USBPrintf("%06ld EP2\t[%02d]", ++__DBG_USBCount, (int)USBDCore_EPTGetBufferLen(EPTn)); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint3(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint4(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint5(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint6(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint7(USBD_EPTn_Enum EPTn) +{ + return; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.h new file mode 100644 index 00000000000..c674de9ce6c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.h @@ -0,0 +1,87 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_class.h + * @version $Rev:: 5 $ + * @date $Date:: 2017-05-11 #$ + * @brief The header file of USB Device Class. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_USBD_CLASS_H +#define __HT32_USBD_CLASS_H + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDClass USB Device Class + * @brief USB Device Class + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Private_Define USB Device Class private definitions + * @{ + */ +/* For ht32_usbd_descriptor.c */ +#define CLASS_INF_CLASS (DESC_CLASS_03_XXX) +#define CLASS_INF_SUBCLASS (HID_SUBCLASS_00_NONE) +#define CLASS_INF_PTCO (HID_PROTOCOL_00_NONE) + +/* HID related definition */ +#define DESC_LEN_XXX ((u32)(9)) +#define DESC_LEN_XXX ((u16)(47)) + +#define DESC_TYPE_01_XXX (0x01) +#define DESC_TYPE_02_XXX (0x02) + +#define HID_SUBCLASS_00_NONE (0x00) +#define HID_SUBCLASS_01_BOOT (0x01) + +#define HID_PROTOCOL_00_NONE (0x00) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Exported_Functions USB Device Class exported functions + * @{ + */ +void USBDClass_Init(USBDCore_Class_TypeDef *pClass); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __HT32_USBD_CLASS_H ------------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.c new file mode 100644 index 00000000000..a4432bf192f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.c @@ -0,0 +1,368 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_descriptor.c + * @version $Rev:: 5 $ + * @date $Date:: 2017-05-11 #$ + * @brief The USB Descriptor. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_usbd_core.h" +#include "ht32_usbd_class.h" +#include "ht32_usbd_descriptor.h" + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDDescriptor USB Descriptor + * @brief USB descriptor + * @{ + */ + + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Device descriptor setting +// USB Specification Release number (bcdUSB) +// <0x0200=> USB 2.0 +// <0x0110=> USB 1.1 +// <0x0100=> USB 1.0 +// USB Class code (assigned by the USB-IF) +// <0x00=> Use class information in the Interface Descriptors (0x00) +// <0x02=> Communications and CDC Control (CDC, 0x02) +// <0xDC=> Diagnostic Device (0xDC) +// <0xEF=> Miscellaneous (0xEF) +// <0xFF=> Vendor Specific (0xFF) +// USB Subclass code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Protocol code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Vendor ID <0x0-0xFFFF:1> +// USB Product ID <0x0-0xFFFF:1> +// USB Device Version <0x0-0xFFFF:1> +// USB String descriptor - Manufacturer +// USB String descriptor - Product +// USB String descriptor - Device serial number +// USB Number of possible configurations <0-255:1> +#define DESC_BCDUSB (0x0110) +#define DESC_BDEVCLASS (0x00) +#define DESC_BDEVSUBCLASS (0x00) +#define DESC_BDEVPROTOCOL (0x00) +#define DESC_IDVENDOR (0x04D9) +#define DESC_IDPRODUCT (0x8008) +#define DESC_BCDDEVICE (0x0100) +#define DESC_IMANUFACTURE (1) +#define DESC_IPRODUCT (1) +#define DESC_ISERIALNUM (1) +#define DESC_INUMCONFN (1) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (DESC_BDEVCLASS == 0x0 & DESC_BDEVSUBCLASS != 0x0) +#error "DESC_BDEVSUBCLASS must be reset to zero when the DESC_BDEVCLASS is equal to zero." +#endif +#define DESC_WMAXPACKETSIZE0 (_EP0LEN) +#define DESC_STR_MAN (1 * DESC_IMANUFACTURE) +#define DESC_STR_PRD (2 * DESC_IPRODUCT) +#define DESC_STR_SER (3 * DESC_ISERIALNUM) +#define DESC_NUM_STRING (1 + 3) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_DeviceDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Device descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_DEV, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_01_DEV, // bDescriptorType 1 DEVICE Descriptor Type + DESC_H2B(DESC_BCDUSB), // bcdUSB 2 USB Specification Release Number + DESC_BDEVCLASS, // bDeviceClass 1 Class code (assigned by the USB-IF) + DESC_BDEVSUBCLASS, // bDeviceSubClass 1 Subclass code (assigned by the USB-IF) + DESC_BDEVPROTOCOL, // bDeviceProtocol 1 Protocol code (assigned by the USB-IF) + DESC_WMAXPACKETSIZE0, // wMaxPacketSize0 1 Maximum packet size for endpoint zero + DESC_H2B(DESC_IDVENDOR), // idVendor 2 Vendor ID (assigned by USB-IF) + DESC_H2B(DESC_IDPRODUCT), // idProduct 2 Product ID (assigned by manufacturer) + DESC_H2B(DESC_BCDDEVICE), // bcdDevice 2 Device release number + DESC_STR_MAN, // iManufacturer 1 Index of string descriptor (Manufacturer) + DESC_STR_PRD, // iProduct 1 Index of string descriptor (Product) + DESC_STR_SER, // iSerialNumber 1 Index of string descriptor (Serial Number) + DESC_INUMCONFN, // iNumConfigurations 1 Number of possible configuration +}; + + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Configuration descriptor setting +// Self-powered +// Bit 6 of bmAttributes +// Remote Wakeup +// Bit 5 of bmAttributes +// USB Device maximum power (mA) < 2-512:2> +#define DESC_BMATTR_SELF_POWER (0) +#define DESC_BMATTR_REMOTE_WAKEUP (1) +#define DESC_BMAXPOWER (100) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#define DESC_BMATTRIBUTES (0x80 | (DESC_BMATTR_SELF_POWER << 6) | (DESC_BMATTR_REMOTE_WAKEUP << 5)) +#define DESC_TOTAL_LEN DESC_H2B((DESC_LEN_CONFN_T + RETARGET_DLEN)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_ConfnDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Configuration descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_CONFN, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_02_CONFN, // bDescriptorType 1 CONFIGURATION Descriptor Type + DESC_TOTAL_LEN, // wTotalLength 2 Total length of data returned for this configuration + 0x01 + RETARGET_INF, // bNumberInterface 1 Number of interfaces supported by this configuration + 0x01, // bConfigurationValue 1 Value to use as an argument to the SetConfiguration() + 0x00, // iConfiguration 1 Index of string descriptor describing this configuration + DESC_BMATTRIBUTES, // bmAttributes 1 Configuration characteristics + // D6: Self-powered, D5: RemoteWakeup + DESC_POWER(DESC_BMAXPOWER), // bMaxPower 1 Maximum power consumption of the USB device (2 mA units) + + /*--------------------------------------------------------------------------------------------------------*/ + /* Interface descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_INF, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_04_INF, // bDescriptorType 1 INTERFACE Descriptor Type + 0x00, // bInterfaceNumber 1 Number of this interface (Zero-based 0) + 0x00, // bAlternateSetting 1 Value used to select this alternate setting + 2, // bNumEndpoints 1 Number of endpoints used by this interface + CLASS_INF_CLASS, // bInterfaceClass 1 Class code (assigned by USB-IF) + CLASS_INF_SUBCLASS, // bInterfaceSubClass 1 Subclass code (assigned by USB-IF) + CLASS_INF_PTCO, // bInterfaceProtocol 1 Protocol code (assigned by USB) + 0x00, // iInterface 1 Index of string descriptor describing this interface + + /*--------------------------------------------------------------------------------------------------------*/ + /* XXX descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_XXX, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_01_XXX, // bDescriptorType 1 XXX Descriptor type + DESC_H2B(0x0110), // bcdXXX 2 XXX Specification Release Number + 0x21, // bCountryCode 1 Country code of the localized hardware + 0x01, // bNumDescriptors 1 Number of class descriptors (at least 1) + DESC_TYPE_02_XXX, // bDescriptorType 1 REPORT Descriptor Type + DESC_H2B(DESC_LEN_XXXX), // bDescriptorLength 2 Total size of the Report descriptor + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + 0x81, // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x03, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(_EP1LEN), // wMaxPacketSize 2 Maximum packet size + 0x01, // bInterval 1 Interval for polling endpoint + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + 0x02, // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x03, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(_EP2LEN), // wMaxPacketSize 2 Maximum packet size + 0x01, // bInterval 1 Interval for polling endpoint + + #ifdef RETARGET_IS_USB + #include "ht32_retarget_desc.h" + #endif + +}; + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB String Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_StringDescLANGID[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* LANGID (Index = 0) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(1), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_H2B(0x0409), // wLANGID[0] 2 LANGID code zero +}; + +#if (DESC_IMANUFACTURE == 1) +__ALIGN4 static uc8 guUSB_StringDescManufacture[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Manufacture (Index = 1) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(6), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('H'), // bString N UNICODE encoded string + DESC_CHAR('O'), + DESC_CHAR('L'), + DESC_CHAR('T'), + DESC_CHAR('E'), + DESC_CHAR('K'), +}; +#endif + +#if (DESC_IPRODUCT == 1) +__ALIGN4 static uc8 guUSB_StringDescProduct[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Product (Index = 2) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(12), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('U'), // bString N UNICODE encoded string + DESC_CHAR('S'), + DESC_CHAR('B'), + DESC_CHAR('-'), + DESC_CHAR('X'), + DESC_CHAR('X'), + DESC_CHAR('X'), + DESC_CHAR(' '), + DESC_CHAR('D'), + DESC_CHAR('E'), + DESC_CHAR('M'), + DESC_CHAR('O'), +}; +#endif + + +#if (DESC_ISERIALNUM == 1) +__ALIGN4 static u8 guUSB_StringDescSerialNum[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Serial Number (Index = 3) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(12), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('S'), // bString N UNICODE encoded string + DESC_CHAR('N'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), +}; +#endif + +uc8 *gpStringDesc[DESC_NUM_STRING] = +{ + + guUSB_StringDescLANGID, + + #if (DESC_IMANUFACTURE == 1) + guUSB_StringDescManufacture, + #else + NULL, + #endif + + #if (DESC_IPRODUCT == 1) + guUSB_StringDescProduct, + #else + NULL, + #endif + + #if (DESC_ISERIALNUM == 1) + guUSB_StringDescSerialNum + #else + NULL, + #endif + +}; + +/*********************************************************************************************************//** + * @brief USB Descriptor pointer initialization. + * @param pDesc: pointer of USBDCore_Desc_TypeDef + * @retval None + ***********************************************************************************************************/ +void USBDDesc_Init(USBDCore_Desc_TypeDef *pDesc) +{ + pDesc->pDeviceDesc = guUSB_DeviceDesc; + pDesc->pConfnDesc = guUSB_ConfnDesc; + pDesc->ppStringDesc = gpStringDesc; + pDesc->uStringDescNumber = DESC_NUM_STRING; + + return; +} + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.h new file mode 100644 index 00000000000..1f0dee2e819 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.h @@ -0,0 +1,59 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_descriptor.h + * @version $Rev:: 5 $ + * @date $Date:: 2017-05-11 #$ + * @brief The USB descriptor. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_USBD_DESCRIPTOR_H +#define __HT32_USBD_DESCRIPTOR_H + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDDescriptor USB Descriptor + * @brief USB descriptor + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +#define DESC_LEN_CONFN_T (u16)(DESC_LEN_CONFN + DESC_LEN_INF + DESC_LEN_XXX + DESC_LEN_EPT * 2) + +/* Exported functions --------------------------------------------------------------------------------------*/ +void USBDDesc_Init(USBDCore_Desc_TypeDef *pDesc); + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __HT32_USBD_DESCRIPTOR_H -------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32fxxxxx_usbdconf.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32fxxxxx_usbdconf.h new file mode 100644 index 00000000000..73cdd54b0a0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/example/ht32fxxxxx_usbdconf.h @@ -0,0 +1,453 @@ +/*********************************************************************************************************//** + * @file example/ht32fxxxxx_usbdconf.h + * @version $Rev:: 5 $ + * @date $Date:: 2017-05-11 #$ + * @brief The configuration file of USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32FXXXX_USBDCONF_H +#define __HT32FXXXX_USBDCONF_H + +// Enter Low Power mode when Suspended +#define USBDCORE_ENABLE_LOW_POWER (0) +// + +#if (USBDCORE_ENABLE_LOW_POWER == 1) + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#else + #define USBDCore_LowPower(...) +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Interrupt Enable */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Interrupt Setting (UIER) +// USB Global Interrupt Enable (UGIE) (Default) +// Start Of Frame Interrupt Enable (SOFIE) +// USB Reset Interrupt Enable (URSTIE) (Default) +// Resume Interrupt Enable (RSMIE) (Default) +// Suspend Interrupt Enable (SUSPIE) (Default) +// Expected Start of Frame Interrupt Enable (ESOFE) +// Control Endpoint Interrupt Enable (EP0IE) (Default) +// Endpoint1 Interrupt Enable (EP1IE) +// Endpoint2 Interrupt Enable (EP2IE) +// Endpoint3 Interrupt Enable (EP3IE) +// Endpoint4 Interrupt Enable (EP4IE) +// Endpoint5 Interrupt Enable (EP5IE) +// Endpoint6 Interrupt Enable (EP6IE) +// Endpoint7 Interrupt Enable (EP7IE) +#define _UIER (0x071D) +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Control Endpoint0 Configuration +// Endpoint Buffer Length (EPLEN) +// <8=> 8 bytes +// <16=> 16 bytes +// <32=> 32 bytes +// <64=> 64 bytes + /* Maximum: 64 Bytes */ +#define _EP0LEN (64) + + +// Control Endpoint0 Interrupt Enable Settings (EP0IER) +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) (Default) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +// SETUP Token Packet Received Interrupt Enable (STRXIE) +// SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default) +// SETUP Data Error Interrupt Enable (SDERIE) +// Zero Length Data Packet Received Interrupt Enable (ZLRXIE) +#define _EP0_IER (0x212) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint1 Configuration +#define _EP1_ENABLE (1) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP1_CFG_EPADR (1) + +// Endpoint Enable (EPEN) +#define _EP1_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP1_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP1_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP1LEN_TMP (64) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP1_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint2 Configuration +#define _EP2_ENABLE (1) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP2_CFG_EPADR (2) + +// Endpoint Enable (EPEN) +#define _EP2_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP2_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP2_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP2LEN_TMP (64) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP2_IER (0x002) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint3 Configuration +#define _EP3_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP3_CFG_EPADR (3) + +// Endpoint Enable (EPEN) +#define _EP3_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP3_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP3_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP3LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP3_IER (0x10) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint4 Configuration +#define _EP4_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP4_CFG_EPADR (4) + +// Endpoint Enable (EPEN) +#define _EP4_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP4_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP4_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP4LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP4_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP4_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint5 Configuration +#define _EP5_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP5_CFG_EPADR (5) + +// Endpoint Enable (EPEN) +#define _EP5_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP5_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP5_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP5LEN_TMP (8) + + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP5_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP5_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint6 Configuration +#define _EP6_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP6_CFG_EPADR (6) + +// Endpoint Enable (EPEN) +#define _EP6_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP6_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP6_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP6LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP6_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP6_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint7 Configuration +#define _EP7_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP7_CFG_EPADR (7) + +// Endpoint Enable (EPEN) +#define _EP7_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP7_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP7_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP7LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP7_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP7_IER (0x10) +// +// + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/inc/ht32_usbd_core.h b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/inc/ht32_usbd_core.h new file mode 100644 index 00000000000..a30f749d105 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/inc/ht32_usbd_core.h @@ -0,0 +1,435 @@ +/*********************************************************************************************************//** + * @file ht32_usbd_core.h + * @version $Rev:: 2555 $ + * @date $Date:: 2022-03-15 #$ + * @brief The header file of standard protocol related function for HT32 USB Device Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_USBD_CORE_H +#define __HT32_USBD_CORE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32_USBD_Library + * @{ + */ + +/** @addtogroup USBDCore + * @{ + */ + + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Settings USB Device Core settings + * @{ + */ +/* USBD Debug mode */ +// Enable USB Debug mode +// Dump USB Debug data +#ifndef USBDCORE_DEBUG + #define USBDCORE_DEBUG (0) /*!< Enable USB Debug mode */ + #define USBDCORE_DEBUG_DATA (0) /*!< Dump USB Debug data */ +#endif +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Type USB Device Core exported types + * @{ + */ +/** + * @brief USB Device Request. + */ +typedef __PACKED_H struct +{ + uc8 bmRequestType; + uc8 bRequest; + uc8 wValueL; + uc8 wValueH; + uc16 wIndex; + uc16 wLength; +} __PACKED_F USBDCore_Request_TypeDef; + +/** + * @brief USB Descriptor. + */ +typedef struct +{ + uc8 *pDeviceDesc; /*!< Device Descriptor */ + uc8 *pConfnDesc; /*!< Configuration Descriptor */ + uc8 **ppStringDesc; /*!< String Descriptor */ + u32 uStringDescNumber; /*!< Count of String Descriptor */ +} USBDCore_Desc_TypeDef; + +/** + * @brief STALL, control IN or control OUT. + */ +typedef enum +{ + USB_ACTION_STALL = 0, + USB_ACTION_DATAIN = 1, + USB_ACTION_DATAOUT = 2, +} USBDCore_Action_Enum; + +/** + * @brief Call back function. + */ +typedef struct +{ + void (*func) (u32 uPara); /*!< Call back function pointer */ + u32 uPara; /*!< Parameter of call back function */ +} USBDCore_CallBack_TypeDef; + +/** + * @brief Parameter for control IN/OUT Transfer. + */ +typedef struct +{ + u8 uBuffer[2]; /*!< Temporary buffer */ + uc8 *pData; /*!< Pointer of control IN/OUT Data */ + s32 sByteLength; /*!< Total length for control IN/OUT Transfer */ + USBDCore_Action_Enum Action; /*!< STALL, control IN or control OUT */ + USBDCore_CallBack_TypeDef CallBack_OUT; /*!< Call back function pointer for Control OUT */ +} USBDCore_Transfer_TypeDef; + +/** + * @brief USB Device. + */ +typedef struct +{ + USBDCore_Request_TypeDef Request; /*!< USB Device Request */ + USBDCore_Desc_TypeDef Desc; /*!< USB Descriptor */ + USBDCore_Transfer_TypeDef Transfer; /*!< Parameter for control IN/OUT Transfer */ +} USBDCore_Device_TypeDef; + +/** + * @brief Bit access for CurrentFeature. + */ +typedef __PACKED_H struct _FEATURE_TYPEBIT +{ + unsigned bSelfPowered :1; /*!< Remote Wakeup feature */ + unsigned bRemoteWakeup :1; /*!< Self Powered */ +} __PACKED_F USBDCore_Feature_TypeBit; + +/** + * @brief For Set/ClearFeature and GetStatus request. + */ +typedef __PACKED_H union _FEATURE_TYPEDEF +{ + u8 uByte; /*!< Byte access for CurrentFeature */ + USBDCore_Feature_TypeBit Bits; /*!< Bit access for CurrentFeature */ +} __PACKED_F USBDCore_Feature_TypeDef; + +/** + * @brief Device State. + */ +typedef enum +{ + USB_STATE_UNCONNECTED = 0, + USB_STATE_ATTACHED = 1, + USB_STATE_POWERED = 2, + USB_STATE_SUSPENDED = 3, + USB_STATE_DEFAULT = 4, + USB_STATE_ADDRESS = 5, + USB_STATE_CONFIGURED = 6, +} USBDCore_Status_Enum; + +/** + * @brief USB Device information. + */ +typedef struct +{ + u8 uCurrentConfiguration; /*!< For Set/GetConfiguration request */ + u8 uCurrentInterface; /*!< For Set/GetInterface request */ + volatile USBDCore_Status_Enum CurrentStatus; /*!< Device State */ + USBDCore_Status_Enum LastStatus; /*!< Device State before SUSPEND */ + USBDCore_Feature_TypeDef CurrentFeature; /*!< For Set/ClearFeature and GetStatus request */ + u32 uIsDiscardClearFeature; /*!< Discard ClearFeature flag for Mass Storage */ +} USBDCore_Info_TypeDef; + +typedef void (*USBDCore_CallBackClass_Typedef) (USBDCore_Device_TypeDef *pDev); +typedef void (*USBDCore_CallBackVendor_Typedef) (USBDCore_Device_TypeDef *pDev); +typedef void (*USBDCore_CallBackEPTn_Typedef) (USBD_EPTn_Enum EPTn); + +/** + * @brief USB Class call back function. + */ +typedef struct +{ + USBDCore_CallBack_TypeDef CallBack_MainRoutine; /*!< Class main routine call back function */ + USBDCore_CallBack_TypeDef CallBack_Reset; /*!< Class RESET call back function */ + USBDCore_CallBack_TypeDef CallBack_StartOfFrame; /*!< Class SOF call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassGetDescriptor; /*!< Class Get Descriptor call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassSetInterface; /*!< Set Interface call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassGetInterface; /*!< Get Interface call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassRequest; /*!< Class Request call back function */ + USBDCore_CallBackVendor_Typedef CallBack_VendorRequest; /*!< Vendor Request call back function */ + USBDCore_CallBackEPTn_Typedef CallBack_EPTn[MAX_EP_NUM]; /*!< Endpoint n call back function */ +} USBDCore_Class_TypeDef; + +/** + * @brief USB Device Power related call back function. + */ +typedef struct +{ + USBDCore_CallBack_TypeDef CallBack_Suspend; +} USBDCore_Power_TypeDef; + +/** + * @brief Major structure of USB Library. + */ +typedef struct +{ + USBDCore_Device_TypeDef Device; /*!< USB Device */ + USBDCore_Info_TypeDef Info; /*!< USB Device information */ + USBDCore_Class_TypeDef Class; /*!< USB Class call back function */ + u32 *pDriver; /*!< USB Device Driver initialization structure */ + USBDCore_Power_TypeDef Power; /*!< USB Device Power related call back function */ +} USBDCore_TypeDef; + +/*----------------------------------------------------------------------------------------------------------*/ +/* Variable architecture of USB Library */ +/*----------------------------------------------------------------------------------------------------------*/ +/* USBCore - USBDCore_TypeDef Major structure of USB Library */ +/* USBCore.Device - USBDCore_Device_TypeDef USB Device */ +/* USBCore.Device.Request - USBDCore_Request_TypeDef USB Device Request */ +/* USBCore.Device.Request.bmRequestType */ +/* USBCore.Device.Request.bRequest */ +/* USBCore.Device.Request.wValueL */ +/* USBCore.Device.Request.wValueH */ +/* USBCore.Device.Request.wIndex */ +/* USBCore.Device.Request.wLength */ +/* USBCore.Device.Desc - USBDCore_Desc_TypeDef USB Descriptor */ +/* USBCore.Device.Desc.pDeviceDesc Device Descriptor */ +/* USBCore.Device.Desc.pConfnDesc Configuration Descriptor */ +/* USBCore.Device.Desc.pStringDesc[DESC_NUM_STRING] String Descriptor */ +/* USBCore.Device.Desc.uStringDescNumber Count of String Descriptor */ +/* USBCore.Device.Transfer - USBDCore_Transfer_TypeDef Parameter for control IN/OUT Transfer */ +/* USBCore.Device.Transfer.uBuffer[2] Temporary buffer */ +/* USBCore.Device.Transfer.pData Pointer of control IN/OUT Data */ +/* USBCore.Device.Transfer.sByteLength Total length for control IN/OUT Transfer */ +/* USBCore.Device.Transfer.Action - USBDCore_Action_Enum STALL, control IN or control OUT */ +/* USBCore.Device.Transfer.CallBack_OUT.func(uPara) Call back function pointer for Control OUT */ +/* USBCore.Device.Transfer.CallBack_OUT.uPara Parameter of Control OUT call back function */ +/* */ +/* USBCore.Info - USBDCore_Info_TypeDef USB Device information */ +/* USBCore.Info.uCurrentConfiguration For Set/GetConfiguration request */ +/* USBCore.Info.uCurrentInterface For Set/GetInterface request */ +/* USBCore.Info.CurrentStatus - USBDCore_Status_Enum Device State */ +/* USBCore.Info.LastStatus - USBDCore_Status_Enum Device State before SUSPEND */ +/* USBCore.Info.CurrentFeature - USBDCore_Feature_TypeDef For Set/ClearFeature and GetStatus request */ +/* USBCore.Info.CurrentFeature.uByte Byte access for CurrentFeature */ +/* USBCore.Info.CurrentFeature.Bits.bRemoteWakeup Remote Wakeup feature */ +/* USBCore.Info.CurrentFeature.Bits.bSelfPowered Self Powered */ +/* USBCore.Info.uIsDiscardClearFeature Discard ClearFeature flag for Mass Storage */ +/* */ +/* USBCore.Class - USBDCore_Class_TypeDef USB Class call back function */ +/* USBCore.Class.CallBack_MainRoutine.func(uPara) Class main routine call back function */ +/* USBCore.Class.CallBack_MainRoutine.uPara Parameter of class main routine */ +/* USBCore.Class.CallBack_Reset.func(uPara) Class RESET call back function */ +/* USBCore.Class.CallBack_Reset.uPara Parameter of RESET call back function */ +/* USBCore.Class.CallBack_StartOfFrame.func(uPara) Class SOF call back function */ +/* USBCore.Class.CallBack_StartOfFrame.uPara Parameter of SOF call back function */ +/* USBCore.Class.CallBack_ClassGetDescriptor(pDev) Class Get Descriptor call back function */ +/* USBCore.Class.CallBack_ClassSetInterface(pDev) Set Interface call back function */ +/* USBCore.Class.CallBack_ClassGetInterface(pDev) Get Interface call back function */ +/* USBCore.Class.CallBack_ClassRequest(pDev) Class Request call back function */ +/* USBCore.Class.CallBack_EPTn[MAX_EP_NUM](EPTn) Endpoint n call back function */ +/* */ +/* USBCore.pDriver USB Device Driver initialization structure */ +/* */ +/* USBCore.Power - USBDCore_Power_TypeDef USB Device Power related call back function */ +/* USBCore.Power.CallBack_Suspend.func(uPara) System low power function for SUSPEND */ +/* USBCore.Power.CallBack_Suspend.uPara Parameter of system low power function */ +/*----------------------------------------------------------------------------------------------------------*/ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Constant USB Device Core exported constants + * @{ + */ + +/** @defgroup USBDCore_Descriptor Definitions for USB descriptor + * @{ + */ +#define DESC_TYPE_01_DEV (0x1) +#define DESC_TYPE_02_CONFN (0x2) +#define DESC_TYPE_03_STR (0x3) +#define DESC_TYPE_04_INF (0x4) +#define DESC_TYPE_05_EPT (0x5) +#define DESC_TYPE_06_DEV_QLF (0x6) +#define DESC_TYPE_08_INF_PWR (0x8) + +#define DESC_CLASS_00_BY_INF (0x00) +#define DESC_CLASS_01_AUDIO (0x01) +#define DESC_CLASS_02_CDC_CTRL (0x02) +#define DESC_CLASS_03_HID (0x03) +#define DESC_CLASS_05_PHY (0x05) +#define DESC_CLASS_06_STILL_IMG (0x06) +#define DESC_CLASS_07_PRINTER (0x07) +#define DESC_CLASS_08_MASS_STORAGE (0x08) +#define DESC_CLASS_09_HUB (0x09) +#define DESC_CLASS_0A_CDC_DATA (0x0A) +#define DESC_CLASS_0B_SMART_CARD (0x0B) +#define DESC_CLASS_0E_VIDEO (0x0E) +#define DESC_CLASS_0F_PHD (0x0F) +#define DESC_CLASS_FF_VENDOR (0xFF) + +#define DESC_LEN_DEV ((u32)(18)) +#define DESC_LEN_CONFN ((u32)(9)) +#define DESC_LEN_INF ((u32)(9)) +#define DESC_LEN_EPT ((u32)(7)) +/** + * @} + */ + +/** @defgroup USBDCore_Request Definitions for USB Request + * @{ + */ +#define REQ_DIR_00_H2D (0 << 7) +#define REQ_DIR_01_D2H (1 << 7) + +#define REQ_TYPE_00_STD (0 << 5) +#define REQ_TYPE_01_CLS (1 << 5) +#define REQ_TYPE_02_VND (2 << 5) + +#define REQ_REC_00_DEV (0) +#define REQ_REC_01_INF (1) +#define REQ_REC_02_EPT (2) +/** + * @} + */ + +/** + * @brief For USBDCore_EPTReadOUTData function. + */ +#define USB_DISCARD_OUT_DATA (0) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Macro USB Device Core exported macros + * @{ + */ +#define __DBG_USBPrintf(...) +#define __DBG_USBDump(a, b) + +#if (USBDCORE_DEBUG == 1) + #ifndef RETARGET_IS_USB + extern u32 __DBG_USBCount; + #undef __DBG_USBPrintf + #define __DBG_USBPrintf printf + #if (USBDCORE_DEBUG_DATA == 1) + #undef __DBG_USBDump + void __DBG_USBDump(uc8 *memory, u32 len); + #endif + #endif +#endif + +/** + * @brief Convert Half-Word to Byte for descriptor. + */ +#define DESC_H2B(Val) ((u8)(Val & 0x00FF)), ((u8)((Val & 0xFF00) >> 8)) + +/** + * @brief Padding 0 automatically for String descriptor. + */ +#define DESC_CHAR(c) (c), (0) + +/** + * @brief Calculate String length for String descriptor. + */ +#define DESC_STRLEN(n) (n * 2 + 2) + +/** + * @brief Calculate power for Configuration descriptor. + */ +#define DESC_POWER(mA) (mA / 2) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Functions USB Device Core exported functions + * @{ + */ +#define USBDCore_DeInit API_USB_DEINIT +#define USBDCore_EPTReset API_USB_EPTn_RESET +#define USBDCore_EPTGetBufferLen API_USB_EPTn_GET_BUFFLEN +#define USBDCore_EPTGetTransferCount API_USB_EPTn_GET_CNT +#define USBDCore_EPTSetSTALL API_USB_EPTn_SET_HALT +#define USBDCore_EPTWaitSTALLSent API_USB_EPTn_WAIT_STALL_SENT +#define USBDCore_EPTClearDataToggle API_USB_EPTn_CLR_DTG + +#define USBDCore_EPTWriteINData API_USB_EPTn_WRITE_IN +#define USBDCore_EPTReadOUTData API_USB_EPTn_READ_OUT +#define USBDCore_EPTReadMemory API_USB_EPTn_READ_MEM + +void USBDCore_Init(USBDCore_TypeDef *pCore); +void USBDCore_IRQHandler(USBDCore_TypeDef *pCore); +void USBDCore_MainRoutine(USBDCore_TypeDef *pCore); +u32 USBDCore_IsSuspend(USBDCore_TypeDef *pCore); +u32 USBDCore_GetRemoteWakeUpFeature(USBDCore_TypeDef *pCore); +void USBDCore_TriggerRemoteWakeup(void); +USBDCore_Status_Enum USBDCore_GetStatus(void); + +void USBDCore_EPTReset(USBD_EPTn_Enum USBD_EPTn); +u32 USBDCore_EPTGetBufferLen(USBD_EPTn_Enum USBD_EPTn); +u32 USBDCore_EPTGetTransferCount(USBD_EPTn_Enum USBD_EPTn, USBD_TCR_Enum type); +void USBDCore_EPTSetSTALL(USBD_EPTn_Enum USBD_EPTn); +void USBDCore_EPTWaitSTALLSent(USBD_EPTn_Enum USBD_EPTn); +void USBDCore_EPTClearDataToggle(USBD_EPTn_Enum USBD_EPTn); + +u32 USBDCore_EPTWriteINData(USBD_EPTn_Enum USBD_EPTn, u32 *pFrom, u32 len); +u32 USBDCore_EPTReadOUTData(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +u32 USBDCore_EPTReadMemory(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HT32_USBD_CORE_H -------------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/src/ht32_usbd_core.c b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/src/ht32_usbd_core.c new file mode 100644 index 00000000000..0a7bc4c20c6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32_USBD_Library/src/ht32_usbd_core.c @@ -0,0 +1,1037 @@ +/*********************************************************************************************************//** + * @file ht32_usbd_core.c + * @version $Rev:: 1684 $ + * @date $Date:: 2019-05-07 #$ + * @brief The standard protocol related function of HT32 USB Device Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_usbd_core.h" + +#ifdef USBD_VENDOR_SUPPORT +#include "ht32_usbd_vendor.c" +#endif + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDCore USB Device Core + * @brief USB Device Core standard protocol related function + * @{ + */ + + +/* Private types -------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_TypesDefinitions USB Device Core private types definitions + * @{ + */ +typedef enum +{ + Device = 0, + Interface = 1, + Endpoint = 2, + Other = 3, +} USBDCore_Recipient_Enum; + +typedef enum +{ + ClearFeature = 0, + SetFeature = 1, +} USBDCore_SetClearFeature_Enum; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Define USB Device Core private definitions + * @{ + */ +/* USBD Debug mode */ +#if (USBDCORE_DEBUG == 1) + #ifdef RETARGET_IS_USB + #warning "USB debug mode can not work when retaget to USB Virtual COM. Turn off automatically." + #undef USBDCORE_DEBUG + #define USBDCORE_DEBUG 0 + #else + u32 __DBG_USBCount; + #warning "USB debug mode has been enabled which degrade the performance." + #warning "After the debug operation, please remember to turn off USB debug mode." + #endif +#endif + +/** @defgroup USBDCore_STD Definition for standard request + * @{ + */ +#define REQ_00_GET_STAT ((u16)(0 << 8)) +#define REQ_01_CLR_FETU ((u16)(1 << 8)) +#define REQ_03_SET_FETU ((u16)(3 << 8)) +#define REQ_05_SET_ADDR ((u16)(5 << 8)) +#define REQ_06_GET_DESC ((u16)(6 << 8)) +#define REQ_07_SET_DESC ((u16)(7 << 8)) +#define REQ_08_GET_CONF ((u16)(8 << 8)) +#define REQ_09_SET_CONF ((u16)(9 << 8)) +#define REQ_10_GET_INF ((u16)(10 << 8)) +#define REQ_11_SET_INF ((u16)(11 << 8)) +#define REQ_12_SYN_FRME ((u16)(12 << 8)) +/** + * @} + */ + +#define DESC_TYPE_01_DEV (0x1) +#define DESC_TYPE_02_CONFN (0x2) +#define DESC_TYPE_03_STR (0x3) +#define USB_NO_DATA (-1) /*!< For Device.Transfer.sByteLength */ +#define BMREQUEST_TYPE_MASK (0x6 << 4) /*!< bmRequestType[6:5] */ +#define USB_FEATURE_REMOTE_WAKEUP (1) + +#define MAX_CONTROL_OUT_SIZE (64) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void _USBDCore_PowerHandler(USBDCore_TypeDef *pCore); +static void _USBDCore_Reset(USBDCore_TypeDef *pCore); +static void _USBDCore_Resume(USBDCore_TypeDef *pCore); +static void _USBDCore_Suspend(USBDCore_TypeDef *pCore); +static void _USBDCore_Setup(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_Request(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_GetStatus(USBDCore_TypeDef *pCore, USBDCore_Recipient_Enum recipient); +static void _USBDCore_Standard_SetClearFeature(USBDCore_TypeDef *pCore, USBDCore_Recipient_Enum recipient, USBDCore_SetClearFeature_Enum type); +static void _USBDCore_Standard_SetAddress(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_GetDescriptor(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_GetConfiguration(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_SetConfiguration(USBDCore_TypeDef *pCore); +static void _USBDCore_ControlIN(USBDCore_TypeDef *pCore); +static void _USBDCore_ControlOUT(USBDCore_TypeDef *pCore); + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Macro USB Device Core private macros + * @{ + */ +/** + * @brief Get self powered bit from Device descriptor + */ +#define _GET_SELFPOWERED_FROM_DESC() (((pCore->Device.Desc.pConfnDesc[7]) >> 6) & 0x01) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Variable USB Device Core private variables + * @{ + */ +USBDCore_TypeDef *pUSBCore; +/** + * @} + */ + + +/* Global Function -----------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Functions USB Device Core exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Core initialization. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_Init(USBDCore_TypeDef *pCore) +{ + pUSBCore = pCore; + pCore->Info.CurrentStatus = USB_STATE_POWERED; + API_USB_INIT(pCore->pDriver); + __DBG_USBPrintf("\r\n%06ld \r\n", ++__DBG_USBCount); + return; +} + +/*********************************************************************************************************//** + * @brief USB Interrupt Service Routine. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_IRQHandler(USBDCore_TypeDef *pCore) +{ + u32 USBISRFlag = API_USB_GET_INT(); + u32 USBEPTISRFlag; + USBD_EPTn_Enum EPTn; + + #if (USBDCORE_DEBUG == 1) + u32 USBAddr = HT_USB->DEVAR; + #endif + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB SOF Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SOF_INT(USBISRFlag)) + { + __DBG_USBPrintf("%06ld SOF[%02d][%02lX]\r\n", ++__DBG_USBCount, pCore->Info.CurrentStatus, USBAddr); + if (pCore->Class.CallBack_StartOfFrame.func != NULL) + { + pCore->Class.CallBack_StartOfFrame.func(pCore->Class.CallBack_StartOfFrame.uPara); + } + API_USB_CLR_SOF_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB SUSPEND Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SUSPEND_INT(USBISRFlag)) + { + __DBG_USBPrintf("%06ld SUSPEND[%02d]\r\n", ++__DBG_USBCount, pCore->Info.CurrentStatus); + API_USB_CLR_SUSPEND_INT(); + _USBDCore_Suspend(pCore); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB RESET Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_RESET_INT(USBISRFlag)) + { + if (API_USB_IS_FRES_INT(USBISRFlag)) + { + API_USB_CLR_FRES_INT(); + } + else + { + __DBG_USBPrintf("%06ld RESET[%02d][%02lX]\r\n", ++__DBG_USBCount, pCore->Info.CurrentStatus, USBAddr); + _USBDCore_Reset(pCore); + if (pCore->Class.CallBack_Reset.func != NULL) + { + pCore->Class.CallBack_Reset.func(pCore->Class.CallBack_Reset.uPara); + } + } + API_USB_CLR_RESET_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB RESUME Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_RESUME_INT(USBISRFlag)) + { + __DBG_USBPrintf("%06ld RESUME\r\n", ++__DBG_USBCount); + _USBDCore_Resume(pCore); + API_USB_CLR_RESUME_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB Endpoint 0 interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_EPTn_INT(USBISRFlag, USBD_EPT0)) + { + USBEPTISRFlag = API_USB_EPTn_GET_INT(USBD_EPT0); + + /*------------------------------------------------------------------------------------------------------*/ + /* Control SETUP Stage */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SETUP_INT(USBEPTISRFlag)) + { + API_USB_READ_SETUP(&(pCore->Device.Request)); /* Read SETUP Command data from USB Buffer*/ + + __DBG_USBPrintf("%06ld SETUP\t[08]\r\n", ++__DBG_USBCount); + __DBG_USBDump((uc8 *)&(pCore->Device.Request), 8); + + _USBDCore_Setup(pCore); + API_USB_CLR_SETUP_INT(); /* Clear SETUP Interrupt */ + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Control Endpoint 0 IN */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_EPTn_IS_IN_INT(USBEPTISRFlag)) + { + __DBG_USBPrintf("%06ld EP0IN\t[%02ld]", ++__DBG_USBCount, pCore->Device.Transfer.sByteLength); + + _USBDCore_ControlIN(pCore); + API_USB_EPTn_CLR_IN_INT(USBD_EPT0); + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Control Endpoint 0 OUT */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_EPTn_IS_OUT_INT(USBEPTISRFlag)) + { + __DBG_USBPrintf("%06ld EP0OUT\t[%02ld]", ++__DBG_USBCount, pCore->Device.Transfer.sByteLength); + + /*----------------------------------------------------------------------------------------------------*/ + /* Clear interrupt flag before USBDCore_ControlOUT is meaning since USBDCore_ControlOUT clear NAKRX */ + /* bit which will cause another interrupt occur. */ + /*----------------------------------------------------------------------------------------------------*/ + API_USB_EPTn_CLR_OUT_INT(USBD_EPT0); + _USBDCore_ControlOUT(pCore); + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Clear Control Endpoint 0 global interrupt */ + /*------------------------------------------------------------------------------------------------------*/ + API_USB_CLR_EPTn_INT(USBD_EPT0); + + } /* if (API_USB_IS_EP_INT(USBISRFlag, USBD_EPT0)) */ + + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB Endpoint n call back function */ + /*--------------------------------------------------------------------------------------------------------*/ + while ((EPTn = API_USB_GET_EPT_NUM(API_USB_GET_INT())) != USBD_NOEPT) + { + USBEPTISRFlag = API_USB_EPTn_GET_INT((USBD_EPTn_Enum)EPTn); + + if (API_USB_EPTn_IS_INT(USBEPTISRFlag)) + { + API_USB_EPTn_CLR_INT(EPTn); + API_USB_CLR_EPTn_INT(EPTn); + + if (pCore->Class.CallBack_EPTn[EPTn] != NULL) + { + pCore->Class.CallBack_EPTn[EPTn](EPTn); + } + } + } /* while ((EPTn = API_USB_GET_EPTn_NUM(API_USB_GET_INT())) != USBD_NOEPT) */ + + return; +} + +/*********************************************************************************************************//** + * @brief USB Core Main Routine for application. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_MainRoutine(USBDCore_TypeDef *pCore) +{ + _USBDCore_PowerHandler(pCore); + + /*--------------------------------------------------------------------------------------------------------*/ + /* Class main routine call back function */ + /*--------------------------------------------------------------------------------------------------------*/ + if ((pCore->Class.CallBack_MainRoutine.func != NULL) && (pCore->Info.CurrentStatus == USB_STATE_CONFIGURED)) + { + pCore->Class.CallBack_MainRoutine.func(pCore->Class.CallBack_MainRoutine.uPara); + } + + return; +} + +/*********************************************************************************************************//** + * @brief Return Suspend status + * @param pCore: pointer of USB Device + * @retval TRUE or FALSE + ***********************************************************************************************************/ +u32 USBDCore_IsSuspend(USBDCore_TypeDef *pCore) +{ + return ((pCore->Info.CurrentStatus == USB_STATE_SUSPENDED) ? TRUE : FALSE); +} + +/*********************************************************************************************************//** + * @brief Return remote wake status which set by SET FEATURE standard command + * @param pCore: pointer of USB Device + * @retval TRUE or FALSE + ***********************************************************************************************************/ +u32 USBDCore_GetRemoteWakeUpFeature(USBDCore_TypeDef *pCore) +{ + return (pCore->Info.CurrentFeature.Bits.bRemoteWakeup); +} + +/*********************************************************************************************************//** + * @brief Turn on USB power and remote wakeup the Host + * @retval None + ***********************************************************************************************************/ +void USBDCore_TriggerRemoteWakeup(void) +{ + API_USB_POWER_ON(); /* Turn on USB Power */ + API_USB_REMOTE_WAKEUP(); /* Generate Remote Wakeup request to Host (RESUME) */ + return; +} + +/*********************************************************************************************************//** + * @brief Get USB Device status + * @retval USBDCore_Status_Enum + ***********************************************************************************************************/ +USBDCore_Status_Enum USBDCore_GetStatus(void) +{ + return pUSBCore->Info.CurrentStatus; +} + +/*********************************************************************************************************//** + * @brief Dump memory data for debug purpose. + * @param memory: buffer pointer to dump + * @param len: dump length + * @retval None + ***********************************************************************************************************/ +#if (USBDCORE_DEBUG == 1 && USBDCORE_DEBUG_DATA == 1) +void __DBG_USBDump(uc8 *memory, u32 len) +{ + u32 i; + for (i = 0; i < len; i++) + { + if (i % 8 == 0) + { + if (i != 0) + { + __DBG_USBPrintf("\r\n"); + } + __DBG_USBPrintf("\t\t"); + } + __DBG_USBPrintf("%02X ", *((u8 *)(memory + i))); + } + __DBG_USBPrintf("\r\n"); + + return; +} +#endif +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Function USB Device Core private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Core Power handler for application. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_PowerHandler(USBDCore_TypeDef *pCore) +{ + API_USB_POWER_UP(pCore->pDriver, pCore->Info.CurrentFeature.Bits.bSelfPowered); + + if (pCore->Info.CurrentStatus == USB_STATE_SUSPENDED) + { + /*------------------------------------------------------------------------------------------------------*/ + /* System Low Power call back function */ + /*------------------------------------------------------------------------------------------------------*/ + if (pCore->Power.CallBack_Suspend.func != NULL) + { + __DBG_USBPrintf("%06ld >LOWPOWER\r\n", ++__DBG_USBCount); + + pCore->Power.CallBack_Suspend.func(pCore->Power.CallBack_Suspend.uPara); + + __DBG_USBPrintf("%06ld pDriver; + + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + pCore->Info.uCurrentConfiguration = 0; + pCore->Info.uCurrentInterface = 0; + pCore->Info.CurrentFeature.Bits.bRemoteWakeup = 0; + pCore->Info.CurrentStatus = USB_STATE_DEFAULT; + pCore->Info.uIsDiscardClearFeature = FALSE; + + API_USB_DEINIT(); + + API_USB_POWER_ON(); + + /* Endpoint 0 initialization */ + API_USB_EPTn_INIT(USBD_EPT0, pCore->pDriver); // To be modify, init from desc + + /* Enable USB interrupt */ + API_USB_ENABLE_INT(pDrv->uInterruptMask); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Resume + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Resume(USBDCore_TypeDef *pCore) +{ + API_USB_POWER_ON(); + pCore->Info.CurrentStatus = pCore->Info.LastStatus; + return; +} + +/*********************************************************************************************************//** + * @brief USB Suspend + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Suspend(USBDCore_TypeDef *pCore) +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* When Device has been suspended, Change CurrentStatus as SUSPEND and then USBDCore_PowerHandler will */ + /* turn off chip power. */ + /*--------------------------------------------------------------------------------------------------------*/ + if (pCore->Info.CurrentStatus >= USB_STATE_POWERED) + { + API_USB_POWER_OFF(); + pCore->Info.LastStatus = pCore->Info.CurrentStatus; + pCore->Info.CurrentStatus = USB_STATE_SUSPENDED; + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Setup Stage + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Setup(USBDCore_TypeDef *pCore) +{ + pCore->Device.Transfer.Action = USB_ACTION_STALL; + pCore->Device.Transfer.sByteLength = 0; + + switch (pCore->Device.Request.bmRequestType & BMREQUEST_TYPE_MASK) + { + /*------------------------------------------------------------------------------------------------------*/ + /* Standard requests */ + /*------------------------------------------------------------------------------------------------------*/ + case REQ_TYPE_00_STD: + { + _USBDCore_Standard_Request(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* Class requests */ + /*------------------------------------------------------------------------------------------------------*/ + case REQ_TYPE_01_CLS: + { + if (pCore->Class.CallBack_ClassRequest != NULL) + { + pCore->Class.CallBack_ClassRequest(&(pCore->Device)); + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* Vendor requests */ + /*------------------------------------------------------------------------------------------------------*/ + case REQ_TYPE_02_VND: + { + if (pCore->Class.CallBack_VendorRequest != NULL) + { + pCore->Class.CallBack_VendorRequest(&(pCore->Device)); + } + /* Add Vendor requests handler here.... */ + #ifdef USBD_VENDOR_SUPPORT + USBDVendor_Request(pCore); + #endif + break; + } + } /* switch (gUSBReq.bmRequestType.byte) */ + + switch (pCore->Device.Transfer.Action) + { + /*------------------------------------------------------------------------------------------------------*/ + /* Control IN */ + /*------------------------------------------------------------------------------------------------------*/ + case USB_ACTION_DATAIN: + { + /*----------------------------------------------------------------------------------------------------*/ + /* When the Control IN length is large than the Host required, transfer the length which specified */ + /* by SETUP Data Packet. */ + /*----------------------------------------------------------------------------------------------------*/ + if (pCore->Device.Transfer.sByteLength > pCore->Device.Request.wLength) + { + pCore->Device.Transfer.sByteLength = pCore->Device.Request.wLength; + } + __DBG_USBPrintf("%06ld EP0IN\t[%02ld]", __DBG_USBCount, pCore->Device.Transfer.sByteLength); + + _USBDCore_ControlIN(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* Control OUT */ + /*------------------------------------------------------------------------------------------------------*/ + case USB_ACTION_DATAOUT: + { + if (pCore->Device.Transfer.sByteLength == 0) + { + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32 *)0, 0); /* Prepare ZLP ack for Control OUT */ + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* STALL */ + /*------------------------------------------------------------------------------------------------------*/ + default: + { + __DBG_USBPrintf("%06ld EP0 STALL\r\n", __DBG_USBCount); + + API_USB_EPTn_SEND_STALL(USBD_EPT0); + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Stand Request. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_Request(USBDCore_TypeDef *pCore) +{ + u16 USBCmd = *((u16 *)(&(pCore->Device.Request))); + + switch (USBCmd) + { + /*------------------------------------------------------------------------------------------------------*/ + /* | bRequest | Data transfer direction | Type | Recipient | Data */ + /*------------------------------------------------------------------------------------------------------*/ + + /*------------------------------------------------------------------------------------------------------*/ + /* | 00_Get Status | 80_Device-to-Host | 00_Standard Request | 0_Device | 0080h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_00_GET_STAT | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld GET DST\t[%02d]\r\n", __DBG_USBCount, pCore->Info.CurrentFeature.uByte); + _USBDCore_Standard_GetStatus(pCore, Device); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 00_Get Status | 80_Device-to-Host | 00_Standard Request | 1_Interface | 0081h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_00_GET_STAT | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld GET IST\t[%02d]\r\n", __DBG_USBCount, 0); + _USBDCore_Standard_GetStatus(pCore, Interface); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 00_Get Status | 80_Device-to-Host | 00_Standard Request | 2_Endpoint | 0082h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_00_GET_STAT | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_02_EPT): + { + __DBG_USBPrintf("%06ld GET EST\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wIndex); + _USBDCore_Standard_GetStatus(pCore, Endpoint); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 01_Clear Feature | 00_Host-to-Device | 00_Standard Request | 0_Device | 0100h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_01_CLR_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld CLR DFEA\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetClearFeature(pCore, Device, ClearFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 01_Clear Feature | 00_Host-to-Device | 00_Standard Request | 2_Endpoint | 0102h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_01_CLR_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_02_EPT): + { + __DBG_USBPrintf("%06ld CLR EFEA\t[0x%02x]\r\n", __DBG_USBCount, pCore->Device.Request.wIndex); + _USBDCore_Standard_SetClearFeature(pCore, Endpoint, ClearFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 03_Set Feature | 00_Host-to-Device | 00_Standard Request | 0_Device | 0300h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_03_SET_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld SET DFEA\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetClearFeature(pCore, Device, SetFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 03_Set Feature | 00_Host-to-Device | 00_Standard Request | 2_Endpoint | 0302h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_03_SET_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_02_EPT): + { + __DBG_USBPrintf("%06ld SET EFEA\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wIndex); + _USBDCore_Standard_SetClearFeature(pCore, Endpoint, SetFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 05_Set Address | 00_Host-to-Device | 00_Standard Request | 0_Device | 0500h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_05_SET_ADDR | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld SET ADDR\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetAddress(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 06_Get Descriptor | 80_Device-to-Host | 00_Standard Request | 0_Device | 0680h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_06_GET_DESC | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld GET DDESC\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueH); + _USBDCore_Standard_GetDescriptor(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 06_Get Descriptor | 80_Device-to-Host | 00_Standard Request | 1_Interface | 0681h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_06_GET_DESC | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld GET IDESC\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueH); + if (pCore->Class.CallBack_ClassGetDescriptor != NULL) + { + pCore->Class.CallBack_ClassGetDescriptor((USBDCore_Device_TypeDef *)&(pCore->Device)); + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 08_Get Configuration | 80_Host-to-Device | 00_Standard Request | 0_Device | 0880h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_08_GET_CONF | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld GET CONF\t[%02X]\r\n", __DBG_USBCount, pCore->Info.uCurrentConfiguration); + _USBDCore_Standard_GetConfiguration(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 09_Set Configuration | 00_Host-to-Device | 00_Standard Request | 0_Device | 0900h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_09_SET_CONF | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld SET CONF\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetConfiguration(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 11_Set Interface | 00_Host-to-Device | 00_Standard Request | 1_Interface | 0B01h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_11_SET_INF | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld SET INF\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + if (pCore->Class.CallBack_ClassSetInterface != NULL) + { + pCore->Class.CallBack_ClassSetInterface((USBDCore_Device_TypeDef *)&(pCore->Device)); + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 10_Get Interface | 80_Device-to-Host | 00_Standard Request | 1_Interface | 0A81h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_10_GET_INF | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld GET INF\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + if (pCore->Class.CallBack_ClassGetInterface != NULL) + { + pCore->Class.CallBack_ClassGetInterface((USBDCore_Device_TypeDef *)&(pCore->Device)); + } + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - GET_STATUS. + * @param pCore: pointer of USB Device + * @param recipient: Recipient + * @arg Device: 0 + * @arg Interface: 1 + * @arg Endpoint: 2 + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_GetStatus(USBDCore_TypeDef *pCore, USBDCore_Recipient_Enum recipient) +{ + pCore->Device.Transfer.uBuffer[1] = 0; + switch (recipient) + { + case Device: + { + pCore->Device.Transfer.uBuffer[0] = pCore->Info.CurrentFeature.uByte; + break; + } + case Interface: + { + pCore->Device.Transfer.uBuffer[0] = 0; + break; + } + case Endpoint: + { + pCore->Device.Transfer.uBuffer[0] = API_USB_EPTn_GET_HALT((USBD_EPTn_Enum)(pCore->Device.Request.wIndex & 0xF)); + break; + } + default: + { + return; + } + } + + pCore->Device.Transfer.pData = (uc8 *)&(pCore->Device.Transfer.uBuffer); + pCore->Device.Transfer.sByteLength = 2; + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - SET_FEATURE / CLEAR_FEATURE. + * @param pCore: pointer of USB Device + * @param recipient: Recipient + * @arg Device: 0 + * @arg Interface: 1 + * @arg Endpoint: 2 + * @param type: + * @arg ClearFeature: 0 + @arg SerFeature: 1 + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_SetClearFeature(USBDCore_TypeDef *pCore, + USBDCore_Recipient_Enum recipient, + USBDCore_SetClearFeature_Enum type) +{ + u32 i; + switch (recipient) + { + case Device: + { + if (pCore->Device.Request.wValueL == USB_FEATURE_REMOTE_WAKEUP) + { + pCore->Info.CurrentFeature.Bits.bRemoteWakeup = type; + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + } + break; + } + case Endpoint: + { + i = pCore->Device.Request.wIndex & 0xF; + if (i != 0) + { + if (type == ClearFeature) + { + if (pCore->Info.uIsDiscardClearFeature == FALSE) + { + API_USB_EPTn_CLR_HALT((USBD_EPTn_Enum)i); + API_USB_EPTn_CLR_DTG((USBD_EPTn_Enum)i); + } + } + else + { + API_USB_EPTn_SET_HALT((USBD_EPTn_Enum)i); + } + } + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + break; + } + default: + { + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - SET_ADDRESS. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_SetAddress(USBDCore_TypeDef *pCore) +{ + API_USB_SET_ADDR(pCore->Device.Request.wValueL); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + pCore->Info.CurrentStatus = USB_STATE_ADDRESS; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - GET_DESCRIPTOR. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_GetDescriptor(USBDCore_TypeDef *pCore) +{ + u32 value = pCore->Device.Request.wValueH; + uc8 *pTemp; + + switch (value) + { + case DESC_TYPE_01_DEV: + { + pCore->Device.Transfer.pData = pCore->Device.Desc.pDeviceDesc; + pCore->Device.Transfer.sByteLength = *(pCore->Device.Desc.pDeviceDesc); + pCore->Device.Transfer.Action= USB_ACTION_DATAIN; + break; + } + case DESC_TYPE_02_CONFN: + { + pCore->Device.Transfer.pData = pCore->Device.Desc.pConfnDesc; + pCore->Device.Transfer.sByteLength = *(u16 *)((pCore->Device.Desc.pConfnDesc) + 2); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + break; + } + case DESC_TYPE_03_STR: + { + value = pCore->Device.Request.wValueL; + if (value < pCore->Device.Desc.uStringDescNumber) + { + if (*(pCore->Device.Desc.ppStringDesc + value) != NULL) + { + pTemp = *(pCore->Device.Desc.ppStringDesc + value); + pCore->Device.Transfer.pData = (uc8 *)(pTemp); + pCore->Device.Transfer.sByteLength = *(pTemp); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + } + } + break; + } + } + + #ifdef USBD_VENDOR_SUPPORT + USBDVendor_StandardGetDescriptor(pCore); + #endif + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - GET_CONFIGURATION. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_GetConfiguration(USBDCore_TypeDef *pCore) +{ + pCore->Device.Transfer.pData = &(pCore->Info.uCurrentConfiguration); + pCore->Device.Transfer.sByteLength = 1; + pCore->Device.Transfer.Action= USB_ACTION_DATAIN; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - SET_CONFIGURATION. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_SetConfiguration(USBDCore_TypeDef *pCore) +{ + u32 i; + + pCore->Info.uCurrentConfiguration = pCore->Device.Request.wValueL; + pCore->Device.Transfer.Action= USB_ACTION_DATAIN; + + /* Endpoint n settings */ + for (i = 1; i < MAX_EP_NUM; i++) + { + API_USB_EPTn_INIT((USBD_EPTn_Enum)i, pCore->pDriver); // To be modify, init from desc + } + + pCore->Info.CurrentStatus = USB_STATE_CONFIGURED; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Control IN transfer. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_ControlIN(USBDCore_TypeDef *pCore) +{ + s32 EP0INLen = API_USB_GET_CTRL_IN_LEN(); + u32 len; + + if (pCore->Device.Transfer.sByteLength != USB_NO_DATA && pCore->Device.Transfer.Action == USB_ACTION_DATAIN) + { + if (pCore->Device.Transfer.sByteLength >= EP0INLen) + { + len = EP0INLen; + pCore->Device.Transfer.sByteLength -= len; + } + else + { + len = pCore->Device.Transfer.sByteLength; + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + pCore->Device.Transfer.Action = USB_ACTION_DATAOUT; + } + + __DBG_USBPrintf("[%02ld]\r\n", len); + __DBG_USBDump((uc8 *)pCore->Device.Transfer.pData, len); + + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32 *)pCore->Device.Transfer.pData, len); + pCore->Device.Transfer.pData = pCore->Device.Transfer.pData + len; + } + else + { + __DBG_USBPrintf("[-1]\r\n"); + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Control OUT transfer. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_ControlOUT(USBDCore_TypeDef *pCore) +{ + u32 len; + + if (pCore->Device.Transfer.sByteLength != USB_NO_DATA && pCore->Device.Transfer.Action == USB_ACTION_DATAOUT) + { + len = API_USB_EPTn_READ_OUT(USBD_EPT0, (u32 *)pCore->Device.Transfer.pData, MAX_CONTROL_OUT_SIZE); + + __DBG_USBPrintf("[%02ld]\r\n", len); + __DBG_USBDump((uc8 *)pCore->Device.Transfer.pData, len); + + pCore->Device.Transfer.pData = pCore->Device.Transfer.pData + len; + pCore->Device.Transfer.sByteLength -= len; + + if (pCore->Device.Transfer.sByteLength == 0) + { + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + if (pCore->Device.Transfer.CallBack_OUT.func != NULL) + { + pCore->Device.Transfer.CallBack_OUT.func(pCore->Device.Transfer.CallBack_OUT.uPara); + pCore->Device.Transfer.CallBack_OUT.func = NULL; + } + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32 *)0, 0); + } + } + else + { + __DBG_USBPrintf("[-1]\r\n"); + } + + return; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/Release_Notes.txt b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/Release_Notes.txt new file mode 100644 index 00000000000..948233eafca --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/Release_Notes.txt @@ -0,0 +1,1674 @@ +/*********************************************************************************************************//** + * @file Release_Notes.txt + * @version V1.9.1 + * @date 2023-12-22 + * @brief The Release notes of HT32 Firmware Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +// Supported Device +// ======================================== +// HT32F50020, HT32F50030 +// HT32F50220, HT32F50230 +// HT32F50231, HT32F50241 +// HT32F50343 +// HT32F50431, HT32F50441 +// HT32F50442, HT32F50452 +// HT32F52220, HT32F52230 +// HT32F52231, HT32F52241 +// HT32F52234, HT32F52244 +// HT32F52243, HT32F52253 +// HT32F52331, HT32F52341 +// HT32F52342, HT32F52352 +// HT32F52344, HT32F52354 +// HT32F52357, HT32F52367 +// HT32F53231, HT32F53241 +// HT32F53242, HT32F53252 +// HT32F54231, HT32F54241 +// HT32F54243, HT32F54253 +// HT32F57331, HT32F57341 +// HT32F57342, HT32F57352 +// HT32F59041, HT32F59741 +// HT32F59046, HT32F59746 +// HT32F5826, HT32F5828 +// HT32F0006 +// HT32F0008 +// HT32F52142 +// HT32F61030, HT32F61041 +// HT32F61141 +// HT32F61244, HT32F61245 +// HT32F61352 +// HT32F61355, HT32F61356, HT32F61357 +// HT32F61630, HT32F61641 +// HT32F62030, HT32F62040, HT32F62050 +// HT32F65230, HT32F65240 +// HT32F65232 +// HT32F67041, HT32F67051 +// HT32F67232 +// HT32F67233 +// HT32F67741 +// HT32F67742 +// HT50F32002, HT50F32003 +// HT50F3200S, HT50F3200T +// HF5032 +// MXTX6306 + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.9.1_7446 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-12-22 + Main Changes + + Add example support of BM18B367A DVB. + + Add "system_ht32f5xxxx_18.c" for BM18B367A DVB. + + Update "ht32f5xxxx_aes.c/h", changed API parameter 4 bytes to remove type conversion at driver layer. + + Update example, add "__ALIGN4" to variables and enforced type conversion for 4 bytes read/write API calls. + - "AES/CBC" + - "AES/CTR" + - "AES/ECB" + + Update USB example, add the process of detecting USB bus status before USBDCore_LowPower(). + - "CKCU/HSI_AutoTrim_By_USB" + - "USBD/*" + + Update USART example for BM18B367A DVB, add the HSI auto trim by LSE related flow. + - "USART/Interrupt" + - "USART/Interrupt_FIFO" + - "USART/PDMA" + - "USART/Polling" + - "USART/Retarget" + - "USART/RS485_NMM_Slave" + + Others + + Update comment, format, typing error, and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.8.1_7371 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-12-06 + Main Changes + + Update "ht32f5xxxx_usbd.c", fix the USB buffer unaligned handling mechanism. + + Update "ht32f5xxxx_rtc.c", modify the RTC_LSECmd() related flow. + + Fix example IO define error of BM53A367A DVB. + - "I2C/PDMA" + + Update example IO define for the latest version of BM53A367A DVB. + - "TM/MatchOutputToggle" + - "TM/PWM" + + Update "ht32f5xxxx_adc.c" and "ht32f65xxx_66xxx_adc.c" to modify the ADC enable related flow. + + Others + + Update comment, format, typing error, and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.7.1_7327 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-11-01 + Main Changes + + Fix example IO define conflict with LED1 of HT32F57352 Starter Kit. + - "CMP/ComparatorInterrupt" + + Fix example IO define error of HT32F50441. + - "MCTM/ComplementaryOutput" + + Update "ht32f5xxxx_ckcu.c", modify the HSI Auto Trim initial function related flow. + + Update "ht32f5xxxx_adc.c" and "ht32f65xxx_66xxx_adc.c", modify the ADC enable related flow. + + Update "ht32_op.c" and "ht32_op.s" to support new version of bootloader waiting time setting address. + (The setting address is changed from 0x1FF0002C to 0x1FF0004C) + + Add "ht32_op_V107.c" and "ht32_op_V107.s" to support the use of older versions of bootloader. + + Others + + Update comment, format, typing error, and coding style. + + Modify and check the example supportability of each IC. + + Add the below file, for the BMduino shield. + - "ht32_undef_IP.h" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.6.2_7271 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-10-03 + Main Changes + + Add example support. + - HT32F53231/41, HT32F53242/52 + - HT32F50431/41, HT32F50442/52 + - HT32F52234/44 + + Fix example IO define error of HT32F52367. + - "USBD/Mass_Storage" + + Modify the example below, add volatile qualifier on some variables (in the for loop usage) + to fix the Arm Compiler Version 6 optimization issue. + ("u32" to "vu32", unsigned int to volatile unsigned int). + - "FMC/FLASH_Security" + + Modify the example below, change the timer used from GPTM to BFTM to increase support. + - "PDMA/SoftwareTrigger" + + Add the below folder, For the BMduino shield/module Keil Driver. + - "BestModules" + + Others + + Update comment, format, typing error, and coding style. + + Adjust "LIBCFG_xxxxx" definition below. + New: + "LIBCFG_ADC_IVREF_DEFAULT_08V" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.6.1_7190 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-08-31 + Main Changes + + Add new device support. + - HT32F61030, HT32F61041 + - HT32F50431, HT32F50441, HT32F50442, HT32F50452 + - HT32F53231, HT32F53241, HT32F53242, HT32F53252 + + Add Controller Area Network driver, "ht32f5xxxx_can.c/h". + + Add new "CAN/FIFO" example. + + Others + + Update comment, format, typing error, and coding style. + + Update "project_template/Script" for adding project C++ source files and setting the chip model mechanism. + - The updated files are as follows: + "Script/_ProjectSource.bat" + "Script/_ProjectSource.ini" + + Update "project_template/Script" for improving script mechanism. + - The updated files are as follows: + "Script/_CreateProjectConfScript.bat" + "Script/_CreateProjectScript.bat" + "Script/_ht32_ic_name.ini" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.5.1_7084 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-08-01 + Main Changes + + Add new device support. + - HT32F52234, HT32F52244 + + Modify DAC related define (The left side old one is still kept for backward compatible). + - HT_DAC -> HT_DAC0 + - AFIO_FUN_DAC -> AFIO_FUN_DAC0 + - CKCU_PCLK_DAC -> CKCU_PCLK_DAC0 + + Modify API as below, add parameter "HT_DAC_TypeDef* HT_DACn" to select DAC engine from the DAC peripherals. + Old API + - DAC_DeInit(void) + - DAC_ModeConfig(u8 ModeSel) + - DAC_ReferenceConfig(u8 DAC_Ch, u32 RefSel) + - DAC_ResolutionConfig(u8 DAC_Ch, u32 ResoSel) + - DAC_OutBufCmd(u8 DAC_Ch, ControlStatus NewState) + - DAC_Cmd(u8 DAC_Ch, ControlStatus NewState) + - DAC_SetData(u8 DAC_Ch, u32 Data) + - DAC_GetOutData(u8 DAC_Ch) + New API + - DAC_DeInit(HT_DAC_TypeDef* HT_DACn) + - DAC_ModeConfig(HT_DAC_TypeDef* HT_DACn, u8 ModeSel) + - DAC_ReferenceConfig(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 RefSel) + - DAC_ResolutionConfig(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 ResoSel) + - DAC_OutBufCmd(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, ControlStatus NewState) + - DAC_Cmd(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, ControlStatus NewState) + - DAC_SetData(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 Data) + - DAC_GetOutData(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch) + + Add API as below. + - "USART_LIN_SendBreak()" API for the USART/UART LIN mode send break to Tx. + - "USART_LIN_LengthSelect()" API for the USART/UART LIN mode configure the break detection length. + - "CKCU_Set_HSIReadyCounter" API for set HSI ready counter value. + + Others + + Update comment, format, typing error, and coding style. + + Rename "LIBCFG_xxxxx" definition below. + - "LIBCFG_DAC" to "LIBCFG_DAC0" + + Add HT32F61630/HT32F61641 related files for Create Project. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.4.3_7026 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-07-17 + + Main Changes + + Add new device support. + - HT32F59046, HT32F59746 + + Others + + Update comment, format, typing error, and coding style. + + Update and sync startup.s/system.c files. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.4.2_6992 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-06-20 + + Main Changes + + Add new device support. + - HT32F61630, HT32F61641 + - HT32F62030, HT32F62040, HT32F62050 + - HT32F67742 + + Modify "RETARGET_Configuration()", add the operation of UxARTn peripheral clock enable. + + Update and sync "ht32f5xxxx_conf.h", modify related define of UxARTn retarget port. + + Others + + Update comment, format, typing error, and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.4.1_6948 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-05-19 + + Main Changes + + Add new device support. + - HT50F3200S, HT50F3200T + + Add example support of HT32F67233. + + Add new "GPIO/PinLock" example. + + Add "Project or Target File Clearing" functions ("_ClearProject.bat" and "_ClearTarget.bat"). + + Rename "ht32f652xx_opa.c/h" to "ht32f65xxx_66xxx_opa.c/h". + + Rename "ht32f652xx_adc.c/h" to "ht32f65xxx_66xxx_adc.c/h". + + Add "ht32f652xx_opa.c/h" and "ht32f652xx_adc.c/h" for backward compatible. + + Modify "ht32_time.h", "ht32f5xxxx_conf.h" and "ht32_time_conf.h" for "LIBCFG_CKCU_NO_APB_PRESCALER" series. + - To ensure the correct configuration of the timer clock, the "HTCFG_TIME_PCLK_DIV" is redefined as 0. + + Modify "syscall.c" to prevent redundant initialization of the heap index. + + Modify the examples below, use separate "if" statements instead of "if-else" to avoid double-entry ISR. + - "PWRCU/DeepSleepMode1" + - "PWRCU/DeepSleepMode2" + + Modify "ht32f5xxxx_01.h" below, ensure the defined register naming to be consistent with the document. + Old New + ----- ----- + - HT_OPA_TypeDef + "OFR" to "VOS" + "VALR" to "DAC" + - HT_CMP_TypeDef + "ICR" to "CI" + "OCR" to "CO" + + Others + + Update comment, format, typing error, and coding style. + + Update e-Link32 Pro/Lite Command line tool as "V1.19" ("utilities/elink32pro/eLink32pro.exe"). + + Update the LVDS setting method of "example\PWRCU\BOD_LVD" example ht32_board_config.h file. + + Update "system_ht32f5xxxx_nn.c" and "startup_ht32f5xxxx_nn.s" files. + + Modify "_ProjectConfigScript.bat" to prevent the creation of project that copy unused system/startup files. + + Modify the Sourcery G++ Lite toolchain project. + - Set C99 mode to fix issues after updating CMSIS v5.9.0 ("for" loop initial declarations). + + Modify and check the startup_ht32fxxxxx_nn files, fix _HT32FWID more than one digit problem. + + Adjust "LIBCFG_xxxxx" definition below. + New: + "LIBCFG_ADC_NO_OFFSET_REG" + Rename: + "LIBCFG_CMP_OCR" to "LIBCFG_CMP_CO" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.3.4_6737 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-02-17 + + Main Changes + + Add example support of HT32F61244, HT32F61245. + + Modify the example below, add volatile qualifier on some variables (in the for loop usage) + to fix the Arm Compiler Version 6 optimization issue. + ("u32" to "vu32", unsigned int to volatile unsigned int). + - "PWRCU/PowerDown_WAKEUPPin" + - "PWRCU/PowerDown_RTC" + - "TM/PWM" + + Others + + Update comment, format, typing error, and coding style. + + Change the default RTC clock as LSI for the "PWRCU/PowerDownMode" example. + + Add the pin group of QSPI in "ht32f61245_sk.h". + + Add "ht32_board_config.h" for the "SYSTICK/DelayMicrosecond" example. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.3.3_6685 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2023-01-18 + + Main Changes + + Add new device support. + - HT32F61244, HT32F61245, HT32F67233 + + Add new examples: + - "SRAM_Overwrite/Watchpoint_Heap" + - "SRAM_Overwrite/Watchpoint_Stack" + + Update "ht32f5xxxx_conf.h" for user layer HSE_VALUE setting. + + Update "ht32f5xxxx_midi.c/.h" for HT32F0006/61355/61356/61357/61244/61245. + + Add "PDMA_MIDI_IN", "PDMA_MIDI_OUT" define. + + Fix "MAX_EP_NUM" define error of HT32F61141. + + Update "SPI/PDMA" example, fix the function call order as below. The "SPI_SELOutputCmd()" shall be called + before the "SPI_Cmd()", to prevent SPI Master Mode Fault (MF) error if Chip Select pin did not have + an external pull-up. + "SPI_SELOutputCmd(HTCFG_SPIS_PORT, ENABLE);" + "SPI_Cmd(HTCFG_SPIS_PORT, ENABLE);" + + Others + + Update comment, format, typing error, and coding style. + + Update and sync startup.s/system.c files. + + Modify "system_ht32fxxxxx_nn.c", add HSE_VALUE notice and update PLL Out formula. + + Update EEPROM Emulation middleware, improve efficacy and reduce resource usage. + "utilities/middleware/eeprom_emulation.c" + "utilities/middleware/ht32_eeprom_config_templet.h" + + Update I2C Master middleware, improve setting way and fix minor errors. + "utilities/middleware/i2c_master.c/.h" + "utilities/middleware/i2c_master_config_templet.h" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.3.2_6448 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-11-15 + + Main Changes + + Add new examples: + - "ADC/ADC_InternalReferenceVoltage_SWTriggerr" + + Add "LIBCFG_ADC_TRIG_DELAY" define to support "ADC_TrigDelayConfig" function for HT32F65230/65240. + + Update "ADC_24bit/Convert_Interrupt" example, fix "I2CMaster_Typedef" structure variable error (correct + "uTimeout_ms" to "uTimeout_us") of "ADC24_WriteRegNonBlock()" and "ADC24_ReadRegNonBlock()". + + Update "ht32_time.h", fix a formula error of "TIME_TICK2US()" and "TIME_TICK2MS()" macro. + + Modify "ht32_retarget.c", fix retarget can't work when the MicroLIB is not used in Keil's V6 compiler. + + Others + + Upgrade CMSIS to v5.9.0. + + Update "ht32_op.s/c", allow "Bootloader Waiting Time" function for all series. + + Modify "HT32F5xxxx_01_DebugSupport.ini" content. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.3.1_6405 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-10-28 + + Main Changes + + Add new device support. + - HT32F50020, HT32F50030 + + GPIO + - Add new define "GPIO_PIN_NUM_n" for GPIO pin number (n = 0 ~ 15). + + EXTI + - Add "gEXTIn_IRQn[]" and "EXTI_GetIRQn()"" macro to map GPIO pin number (0 ~ 15) to "EXTIn_IRQn". + - Add "GPIO2EXTI()"" macro to map GPIO pin to EXTI Channel. + - Change "AFIO_EXTISourceConfig()"" API, remove "AFIO_EXTI_CH_Enum" and "AFIO_ESS_Enum". + Old: "void AFIO_EXTISourceConfig(AFIO_EXTI_CH_Enum AFIO_EXTI_CH_n, AFIO_ESS_Enum AFIO_ESS_Px);" + New: "void AFIO_EXTISourceConfig(u32 GPIO_PIN_NUM_n, u32 GPIO_Px);" + + LEDC + - Fix typing error of the following define. + Old New + ------------- ---------------- + LEDC_FLAG_FEAME LEDC_FLAG_FRAME + LEDC_INT_FEAME LEDC_INT_FRAME + + Fix the error that "TM_DeInit(HT_PWM2)" not works. + + Add new examples: + - "ADC/OneShot_SWTrigger" + + Rename examples as below. + IP Old Name New Name + -------- -------- -------- + ADC InternalReferenceVoltage InternalReferenceVoltage_PWMTrigger + + Modify "EXTI/WakeUp_SleepMode" example, fix "EXTIn_IRQHandler()" ISR naming error of "ht32f5xxxx_01_it.c" + (HT32F652xx). + + Others + + Update comment, format, typing error, and coding style. + + Update and sync startup.s/system.c files. + + Modify API parameter check macro of Library Debug Mode, fix parameter check error. + + Modify variable declaration of "PDMACH_InitTypeDef" to reduce memory size. + + Add a setting, "HT32_LIB_ENABLE_GET_CK_ADC" to control "ADC0_Freq/ADC1_Freq" calculation of the + "CKCU_GetClocksFrequency()" function (default off for code size consideration). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.2.1_6192 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-09-30 + + Main Changes + + Add new device support. + - HT32F67232 + - HT32F67041, HT32F67051 + + Add the following API for PDMA. + - "PDMA_DeInit()" + - "PDMA_AddrConfig()" + - "PDMA_SrcAddrConfig()" + - "PDMA_DstAddrConfig()" + - "PDMA_GetRemainBlkCnt()" + + Add the following API for ADC (HT32F652xx only). + - "ADC_ChannelDataAlign()" + - "ADC_ChannelOffsetValue()" + - "ADC_ChannelOffsetCmd()" + + Add the following API for OPA (HT32F652xx only). + - "OPA_SetUnProtectKey()" + - "OPA_ProtectConfig()" + + Update "OPA/OPA_Enable" example, add the un-protect key related functions. + + Update "FLASH_SetWaitState()" function, disable Pre-fetch and Branch Cache function before change + wait state. + + Fix "HT_ADC->OFR" define error of HT32F65232. + + Update "ht32_retarget.c", modify the retarget related functions for SEGGER Embedded Studio. + + Update following middleware. + "utilities/middleware/i2c_master.c/h" + "utilities/middleware/uart_module.c" + + Others + + Update comment, format, typing error, and coding style. + + Update and sync startup.s/system.c files. + + Change "HT_PWRCU->BAKPSR" to "HT_PWRCU->LDOSR" of HT32F57352. + + Fix "HT_AES->KEYR" define error (from KEYR[8] to KEYR[4] for AES128). + + Update "BFTM/OneShot" example, fix the register access sequence and time calculation formula. + + Update "TM/PWM/main.c", add "HTCFG_PWM_TM_RELOAD" check. + + Update "SLED/*" example, for fix error and coding style. + + Update "HT32F_DVB_PBInit()" of "ht32f5xxxx_board_01.c", add "LIBCFG_EXTI_4_7_GROUP" support. + + Update e-Link32 Pro/Lite Command line tool as "V1.18" ("utilities/elink32pro/eLink32pro.exe"). + + Change the project recommended minimum version of SEGGER Embedded Studio from V4.12 to V6.20. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.1.1_5938 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-06-08 + + Main Changes + + Add new "TM/TriggerCounter_FrequencyMeasure" example. + + Add following middleware. + "utilities/middleware/spi_module.c" + "utilities/middleware/spi_module.h" + "utilities/middleware/spi_module_config_templet.h" + + Fixed FW library compatibility with ARM compiler version 6 of MDK-ARM V5.37. + - Add MDK-ARMv537 project template for MDK-ARM V5.37. + - Update "project_template/Script". Those MDK-ARMv537 project templates will be added for use if choose + the target IDE is "Keil MDK-ARMv5". The fixed files are as follows: + "Script/_CreateProjectScript.bat" + "Script/_ProjectConfig.bat" + "Script/_ProjectSource.bat" + - Update "core_cm0plus.h", fix compiler error. + - Update "SLED/ARGB_GetLEDNum", fix compiler warning. + - Update "FMC/FLASH_OperationNoHalt", fix the compiler issue of Arm Compiler Version V6.18 and the + compiler warning of linker script file. The fixed files are as follows: + "FLASH_OperationNoHalt/main.c" + "FLASH_OperationNoHalt/linker.lin" + - Update following middleware, remove STRCAT3 usage to fix compiler error. + "utilities/middleware/uart_module.c" + "utilities/middleware/i2c_master.c" + "utilities/middleware/spi_module.c" + + Update "ht32_retarget.c". Implement __write function to fix compiler error in IAR EWARM Version 9.20 + or later. + + Update GNU Arm makefile in the project_template, fix the compatibility issue that the makefile of GNU Arm + Version 11 cannot be compiled. + + Update EWARM in the project_template, fix the compiler error that header file path doesn't exist in + the file list of Workspace of IAR EWARM Version 7. + + Fix SPI initial PDMA parameter in the "utilities/common/spi_flash.c". + + Others + + Update comment, format, typing error, and coding style. + + Update e-Link32 Pro/Lite Command line tool as "V1.16" ("utilities/elink32pro/eLink32pro.exe"). + + Update the following examples to remove compiler warning of the IAR EWARM. + "BFTM/TimeMeasure" + "TM/PWMOut_PDMA_4CH" + "USBD/HID_Keyboard_Virtual_COM" + "USBD/USB_UAC_Sound" + "USBD/USB_Video" + "USBD/Virtual_COM" + + Update "TM/PWM" example, add the PWM channel initial function to "pwm.c". + + Update "WDT/Period_Reload" example, add WDT_ResetCmd function. + + Update and sync create project related files ("_ProjectConfig.bat", "_ProjectConfig.ini"). + + Update content of "project_template/IP/Example/readme.txt", add MDK-ARM V5.37 related information. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.0.25_5831 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-04-19 + + Main Changes + + Add example support of BM53A367A. + + Add "LIBCFG_ADC_MVDDA" define, fix the issue that "ADC_MVDDACmd()" function is missing of HT32F50343. + + Update EEPROM Basic and EEPROM Emulation middleware, fix the include and define sequence. + "utilities/middleware/eeprom_basic.h" + "utilities/middleware/eeprom_emulation.h" + + Update UART Module middleware, add the "UARTM_IsTxFinished()" API. + "utilities/middleware/uart_module.c" + "utilities/middleware/uart_module.h" + + Others + + Update comment, format, typing error, and coding style. + + Update e-Link32 Pro/Lite Command line tool as "V1.0.15" ("utilities/elink32pro/eLink32pro.exe"). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_V1.0.24_5762 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-03-08 + + Main Changes + + Change to the new Holtek version format (Vm.n.r). + + Add following middleware. + "utilities/middleware/uart_module.c" + "utilities/middleware/uart_module.h" + + Add new "FMC/FLASH_OperationNoHalt" example. + + Modify "utilities/common/ring_buffer.c", fix the thread-safe issue of "Buffer_GetLength()". + + Others + + Update comment, format, typing error, and coding style. + + Update "startup_ht32fxxxxx_nn.s", support "USE_HT32_CHIP" define exist at startup.s and project Asm + setting in the same time (project's Asm Define has the higher priority). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v023_5734 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2022-02-10 + + Main Changes + + Add new device support. + - MXTX6306 + + Rename previously "EXTI/GPIO_Interrupt" example to "EXTI/EXTI_Key_LED". + + Add new "EXTI/GPIO_Interrupt" example. + + Update the internal VREF level driver, add the missing voltage level setting/define for the HT32F542xx + series. + ADC_VREF_2V5 + ADC_VREF_3V0 + ADC_VREF_4V0 + ADC_VREF_4V5 + + Others + + Update comment, format, typing error, and coding style. + + Modify "bool, TRUE, FALSE" define way for C++/.cpp applications. + + Add warning message for the HT32F54241 SK ("ht32f54241_sk.h" and "ht32_board_config.h" of the related + examples). + + Simplify the following examples to use less IO/LED/KEY. + - "GPIO/InputOutput" + - "EXTI/EXTI_Key_LED" + + Update "utilities/common/spi_flash.c and spi_lcd.c", change the SPI Clock prescaler from 2 to 4 when the + Core clock is large than 48 MHz. + + Update "eLink32pro.exe" from v1.1.2 to v1.1.3. + + Update related middleware (eeprom_basic and eeprom_emulation). + + Update "ADC/InternalReferenceVoltage" example, add the voltage level setting of the internal VREF for + the 5V MCU. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v022_5673 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-12-09 + + Main Changes + + Add new device support. + HT32F61141 + + Add new board support. + HT32F54241 DVB + HT32F54253 DVB + + Add new examples: + - "SYSTICK/DelayMicrosecond" + + Update "ht32fxxxxx_sk.h", "spi_lcd.c/.h", fix the GPIO Chip SEL define mistake which cause the H/W SPI SEL + not work of the following SK model. + HT32F50230, HT32F50241, HT32F52241, HT32F52253, HT32F52341, HT32F54241, HT32F65232, HT32F65240 + + Update "ht32f54241_sk.h" and "ht32f54253_sh.h", fix the COM port UART/Pin and SPI LCD BL typing error. + + Update "GNU_ARM/linker.ld", fix the heap/stack area overlap problem. + + Fix the following library configuration error of HT32F54241/54253. + Add: "LIBCFG_CKCU_PLLSRCDIV", "LIBCFG_PWRCU_PORF". + Remove: "LIBCFG_CMP" (HT32F54241 only, not support). + + Update "example/I2C/TouchKey/ht32_board_config.h", fix the typing error of I2C Port. + + Others + + Rename "LIBCFG_NO_PWRCU_PORF" to "LIBCFG_NO_PWRCU_VDDPORF". + + Update comment, format, typing error, and coding style. + + Update "example/LEDC/7-SegmentDigitalDisplay/main.c", change the frame rate from 40 Hz to 50 Hz. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v021_5582 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-08-19 + + Main Changes + + Add example support of HT32F54241/54253. + + Update "SPI/Slave" example of HT32F52253, modify the SPI port and pin assignment from SPI1 to SPI0. + + Update "SPI/SEL_Software" example of HT32F52253, fix the typing error of SEL GPIO clock. + + Update "SPI/Master" example of HT32F52253. + - Fix the configuration typing error of "ht32_board_config.h". + - Modify the SPI port and pin assignment from SPI1 to SPI0. + + Others + + Update comment, format, typing error, and coding style. + + Update "_ProjectConfig*.bat" files. + + Update "RSTCU/Peripheral_Reset_Function" example, modify "HTCFG_LED0_RST" to "HTCFG_LED1_RST". + + Update "SPI/Slave" example, move the IRQHandler define from "ht32f5xxxx_01_it.c" to "ht32_board_config.h" + to reduce maintenance time. + + Add "LCD_SPI_RST_UNUSE" define for "ht32fxxxxx_sk.h" and "spi_lcd.c", to decide the "spi_lcd.c" controls + the LCD_RST pin or not. + + Update e-Link32 Pro Commander to V1.10. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v020_5545 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-07-23 + + Main Changes + + Add new device support. + HT32F54231, HT32F54241 + HT32F54243, HT32F54253 + HT32F67741 + + Add "ht32_time.c/.h" to support following new functions for delay, time measure, and timeout. + "Time_Init()" + "Time_Delay()" + "Time_GetTick()" + + Add new examples: + - "GPIO/Input" + - "GPIO/Output" + - "Time/TimeFun" + - "Time/TimeFun_UserConf" + - "TM/PWMOut_PDMA_4CH" + - "USART/RS485_NMM_Slave" + + Add new definition, "FLASH_WAITSTATE_MAX". + + Fix the problem that "FLASH_BranchCacheCmd()" is not exist of HT32F0006, HT32F61352, and HT32F6135x. + + Fix the problem that "PWRCU_WakeupMultiPinCmd()", "PWRCU_WAKEUP_PIN_1" are not exist of HT32F50343. + + Fix typing error which cause the "I2C2_IRQn" missing (from "USE_HT32F2243_53" to "USE_HT32F52243_53"). + + Modify the following definition (CH4 to CH7 usually have the compare function only but the "TM_FLAG_CHnC" + definition is not compatible with the "TM_FLAG_CHnCC"). + "TM_FLAG_CH4C" to "TM_FLAG_CH4CC" + "TM_FLAG_CH5C" to "TM_FLAG_CH5CC" + "TM_FLAG_CH6C" to "TM_FLAG_CH6CC" + "TM_FLAG_CH7C" to "TM_FLAG_CH7CC" + + Modify "TM_GetCaptureCompare()" to support TM_CH4 ~ TM_CH7 for 8 channel PWM timer. + + Add "TM_GetCaptureCompare4()" ~ "TM_GetCaptureCompare7()" functions. + + Add "USART_PARITY_MARK" and "USART_PARITY_SPACE" for the UART parity mode. + + Update "example/I2C/Interrupt/main.c", fix the configuration error of I2C slave. + + Update following example, modify the default value of "gIsINEmpty" from TRUE to FALSE. The default value + TRUE may cause the F/W to not send CSW after the first Inquiry CBW Command in a specific condition. + "example/USBD/HID_Keyboard_Mass_Storage" + "example/USBD/Mass_Storage" + "example/USBD/Mass_Storage_IAP" + + Others + + Update comment, format, typing error, and coding style. + + Adjust and fix error of "LIBCFG_xxxxx" definition. + New: + "LIBCFG_FMC_PREFETCH", + Rename: + "LIBCFG_SINK_CURRENT_ENHANCED" to "LIBCFG_GPIO_SINK_CURRENT_ENHANCED" + "LIBCFG_WAKEUP_V01" to "LIBCFG_PWRCU_WAKEUP_V01" + "LIBCFG_CACHE" to "LIBCFG_FMC_BRANCHCACHE" + Remove: + "LIBCFG_ADC_INTERNAL_CH_V02", "LIBCFG_NO_FMC_PRE_FETCH", "LIBCFG_NO_FMC_WAIT_STATUS", + "LIBCFG_ADC_INTERNAL_CH_V03", "LIBCFG_ADC_INTERNAL_CH_DAC" + + Remove unnecessary functions, "PWRCU_WakeupPinIntConfig()" and "PWRCU_WakeupMultiPinIntConfig()". + + Remove unuse global variable "DelayTime" of "ebi_lcd.c" and "spi_lcd.c". + + Change the member order of the "I2C_InitTypeDef". + + Modify the "USART_StickParityCmd()" function to set the PBE bit by default when the command is ENABLE. + + Remove compiler warning of GNU by adding the dummy "if" usage of the unused parameter. + + Fix the case error of "HT32_Board" include path. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v019_5358 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-05-11 + + Main Changes + + Add new examples: + - "ADC/OneShot_SWTrigger_ByTM" + - "CKCU/HSI_AutoTrim_By_LSE" + + Update startup/system files supported of specific MCU projects. + Old New + ------------------------- ------------------------- + - HT32F0006/HT32F61352 + system_ht32f0006.c to system_ht32f5xxxx_07.c + startup_ht32f5xxxx_xxx_01.s to startup_ht32f5xxxx_xxx_07.s + - HT32F52344/HT32F52354 + startup_ht32f5xxxx_01.s to startup_ht32f5xxxx_03.s + + Fix the problem of Flash API of HT32F50343 that the AHB clock of the GPIO port was not enable ,but the + drive current of SPI_MOSI is adjusted. The fixed item is as follows: + - The function "SPI_FLASH_Init()", It is in the "utilities/common/spi_flash.c". + - Add new define "#define FLASH_SPI_MOSI_CLK(CK) (CK.Bit.PB)", It is in the + "utilities/HT32_Board/ht32f50343_sk.h". + + Fixed the system was stuck in CKCU_HSIAutoTrimCmd() because of the misjudgment of CKCU_HSIAutoTrimIsReady(). + + Fixed the problem that the example CKCU/HSI_AUTO_Trim_BY_USB uses HSE(CKCU_PLLSRC_HSE) as the USB PLL + clock source. Change the USB PLL Clock source to HSI(CKCU_PLLSRC_HSI). + + Fix the CHIP ID error in all HT32F6135x projects. Fixed "USE_HT32_CHIP=10" to "USE_HT32_CHIP=17". + + Remove the interrupt capability of the DAC. Modify the file as follows: + - "example/DAC/Async_2CH/ht32f5xxxx_01_it.c"" + - "example/DAC/Async_2CH/main.c" + - "example/DAC/Sync_12bit_2CH/ht32f5xxxx_01_it.c" + - "example/DAC/Sync_12bit_2CH/main.c" + - "trunk/library/Device/Holtek/HT32F5xxxx/Include/ht32f5xxxx_01.h" + - "library/HT32F5xxxx_Driver/inc/ht32f5xxxx_dac.h" + - "library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac.c" + + Others + + Update comment, format, typing error, and coding style. + + Update LIBCFG of SCTM. + - Add the new definition of LIBCFG for a specific MCU: + "#define LIBCFG_SCTM0 (1)" + "#define LIBCFG_SCTM1 (1)" + - Remove the definition of LIBCFG for a specific MCU: + "#define LIBCFG_NO_SCTM (1)" + - Update ht325xxxx_tm.c to depend on the new definitions LIBCFG_SCTM0 and LIBCFG_SCTM1. + + Update the version of eLink32pro.exe to 1.0.1.1. + + Update the following project setting: + - IAR EWARM v6/v7: Modify "_ht32_project_source.c" to "_ht32_project_source.h". + - SEGGER Embedded Studio: Add the new definition "arm_compiler_variant="SEGGER"". + + Remove redundant SCTM definition of 57331/57341. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v018_5303 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2021-02-26 + + Main Changes + + Add "Create Project Configuration Menu" to choose the target IDE and Device when the first time to do the + create project operation of the example. The configuration file, "_CreateProjectConfig.bat" is saved to + the root path of the HT32 Firmware Library. You can reset the create project IDE/IC configuration anytime + by deleting the configuration file. + Target IDE/Compiler: + - Keil MDK-ARM v5 + - Keil MDK-ARM v4 + - IAR EWARM v8 + - IAR EWARM v6/v7 + - SEGGER Embedded Studio + - GNU [with Keil and GNU make] + - SourceryG++Lite [with Keil] + Target Device: + - xxxxx: Single Device + - xxx*: Series + + Add new examples: + - "ADC_24bit/Convert_Interrupt" + - "NVIC/Disable_Interrupt" + - "TM/InternalTrigger" + - "WDT/Auto_Enable" + + Add Flash programming function of GNU Maker (via e-Link32 Pro/Lite Commander). + "make IC=xxxxx eraseall" + "make IC=xxxxx program" + "make IC=xxxxx run" + + Update "CKCU_HSIAutoTrimCmd()" and "CKCU_HSIAutoTrimIsReady()" function to improve clock stability. + + Fix the cache address problem of "SDDISK_Read()" function. + "USBD/Mass_Storage/sd_disk.c" + + Update GNU project (*.uvprojx), fix the compile error when use new GNU Arm version + ("gcc-arm-none-eabi-10-2020-q2-preview-win32" or above). + + Fix Keil compiling error when disable both retarget and MicroLib. + + Update "ht32f1xxxx_01.h", fix the compatibility issue when user include "stdbool.h". + + Modify GNU compiler settings, output text file (disassembly) after building the code. + + Change the startup/system supporting files of specify MCU device. + Old New + ------------------------- ------------------------- + - HT32F0006/HT32F61352 + system_ht32f0006.c to system_ht32f5xxxx_07.c + startup_ht32f5xxxx_xxx_01.s to startup_ht32f5xxxx_xxx_07.s + - HT32F52344/HT32F52354 + startup_ht32f5xxxx_01.s to startup_ht32f5xxxx_03.s + + Add "HT32_FWLIB_VER" and "HT32_FWLIB_SVN" in "ht32f1xxxx_lib.h" for the version information of + HT32 Firmware Library. + Example: + "#define HT32_FWLIB_VER (018)" + "#define HT32_FWLIB_VER (5303)" + + Add new AFIO define in "ht32f1xxxx_gpio.h". + - "AFIO_FUN_MCTM0", "AFIO_FUN_MCTM1" + - "AFIO_FUN_GPTM0", "AFIO_FUN_GPTM1", "AFIO_FUN_GPTM2", "AFIO_FUN_GPTM3" + - "AFIO_FUN_PWM0", "AFIO_FUN_PWM1", "AFIO_FUN_PWM2", "AFIO_FUN_PWM3" + + Add following alias of MCTM IRQ handler + "#define MCTM0_IRQn MCTM0UP_IRQn" + "#define MCTM0_IRQHandler MCTM0UP_IRQHandler" + "#define MCTM1_IRQn MCTM1UP_IRQn" + "#define MCTM1_IRQHandler MCTM1UP_IRQHandler" + + Others + + Update comment, format, typing error, and coding style. + + Update "TM/PWM_Buzzer" example, move the buzzer function to "buzzer_pwm.c/.h". + + Update "_ProjectConfig*.bat" files. + + Add "Project Source File Setting" functions ("_ProjectSource.ini" and "_ProjectSource.bat"). + + Rename "_CreateProjectUSB.bat" as "_CreateProject.bat". + + Add dummy xxTM C files, to notify the user that SCTM/PWM/GPTM/MCTM timer use the "ht32f5xxxx_tm.c" driver. + "ht32f5xxxx_gptm.c", "ht32f5xxxx_pwm.c", "ht32f5xxxx_sctm.c" + + Add "IS_IPN_MCTM()" and "IS_IPN_GPTM" macro, for use to confirm the xxTMn is GPTM or MCTM. + + Update comment and board/pin configuration of "ADC/OneShot_TMTrigger_PDMA" example. + + Update and sync startup.s/system.c files. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v017_5137 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2020-12-31 + + Main Changes + + Update IAR linker.icf, modify the ROM/RAM size. + + Add "LCDENS" related notice of "ht32f5xxxx_lcd.c/.h". + + Fix Keil compiling error when disable both retarget and MicroLib. + + Update "ht32f5xxxx_flash.c", fix the flash erase/program related flow. + + Others + + Update comment, format, typing error, and coding style. + + Update SPI chip select define and SPI configuration of "utilities/common/spi_lcd.c & spi_lcd.h". + + Add "BOARD_DISABLE_EEPROM" define of "utilities/common/i2c_eeprom.c". + + Add notice of VREF stable time and output function. + + Update create project script. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v017_5074 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2020-11-08 + + Main Changes + + Add new device and example support. + HT32F65232, HT32F5828 + + Add "ADC_DualModeConfig()" API for the dual ADC mode of HT32F65230/65240. + + Add "ADC/OneShot_PWMTrigger_Dual_ADC" example. + + Update "startup_ht32f5xxxx_*_05.s" to support HT32F5828. + + Add "system_ht32f5xxxx_08.c" and "startup_ht32f5xxxx_*_08.s" for HT32F652xx series. + + Fix the FIFF/TIFN(Fsampling/Event) setting error of the following function and typedef of the + HT32F65230/65240. + "TM_CaptureInit()" + "TM_PwmInputInit()" + "TM_CHFDIV_Enum" + + Modify the function "MCTM_UpdateDisable()" to "MCTM_UpdateEventDisable" and add "MCTM_UEV1UD/MCTM_UEV1OD" + enum for HT32F65230/65240. + + Add OCR support and update CMP_INPUT_x define for HT32F65232. + + Rename "startup_ht32f65230_40.s" to "startup_ht32fxxxx_08.s" for HT32F652xx series. + + Rename "ht32f65230_40_opa.c/h" to "ht32f652xx_opa.c/h". + + Rename "ht32f65230_40_adc.c/h" to "ht32f652xx_adc.c/h". + + Add missing define of ADC_TRIG_XXXX and modify "ht32f652xx_adc.c/h" for support HT32F652xx series. + + Modify "ht32f5xxxx_rtc.c/h", use LIBCFG_LSE to disable "RTC_SRC_LSE", "RTC_LSECmd()", and + "RTC_LSESMConfig()". + + Remove un-support functions of HT32F5xxxx series. + "TM_EtiExternalClockConfig()" + "TM_EtiConfig()" + + Add missing enum, "TM_CKDIV_8" for HT32F652xx series. + + Add "MCTM_CHBRKCTRConfig2()" MCTM to support Break2 of HT32F652xx series. + + Add missing MCTM interrupt define of HT32F652xx series. + "MCTM_INT_CH0CD" + "MCTM_INT_CH1CD" + "MCTM_INT_CH2CD" + "MCTM_INT_CH3CD" + "MCTM_INT_OVER" + "MCTM_INT_UNDER" + + Others + + Update "system_ht32f5xxxx_04.c", remove unnecessary define. + + Update comment, format, typing error, and coding style. + + Add below notice of examples to inform the user to check the local structure variable without a + default value. + "Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below this function." + + Add "LIBCFG_EXTI_4_9_GROUP" define for the chip who supported extra EXTI interrupt channel. + + Update "MCTM_CHBRKCTRConfig()" function to keep "CHMOE" value. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v016_4983 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2020-10-16 + + Main Changes + + Add new device and example support. + HT32F61355, HT32F61356, HT32F61357 + + Add new board support. + HT32F65240 Starter Kit + + Add more example support for HT32F65240 DVB. + + Add a new example. + "OPA/OPA_Enable" + + Change the default USB LDO setting from the enable mode to bypass mode. + + Update "SPI/FIFO_SEL_Hardware" example. Use timeout interrupt and RX_FIFO length to read the + corresponding data (Previously, it was fixed to read 4 bytes which may cause the data loss problem in + specific conditions). + + Update "CKCU/Clock_Configuration_LSI" example. Add wait for LSI clock ready before the system clock + source switches to LSI (Otherwise, the switching may fail). + + Update "SPI/Slave" example to fix missing EXTI interrupt service routine of HT32F52354. + + Modify "TM/PWM" example to output the complete PWM signal before stopping it. + + Update CMP driver, "ht32f5xxxx_cmp.c/h" and "ht32f65230_40_libcfg.h". Support new CMP function of + HT32F65230/65240. + + Update CMP example "CMP/ComparatorInterrupt" to support HT32F65230/65240 and improve readability. + + Remove "OFVCR" parameter of "HT_OPA_TypeDef" struct in the "ht32f5xxx_01.h". This register is not + supported by the HT32F65230/65240. + + Remove the following unnecessary API in the "ht32f65230_40_opa.c" and "ht32f65230_40_opa.h". + "void OPA_Config(HT_OPA_TypeDef* HT_OPAn, u32 mode, u32 cancellation)" + "void OPA_CancellationModeConfig(HT_OPA_TypeDef* HT_OPAn, u16 OPA_REF_INPUT)" + "void OPA_SetCancellationVaule(HT_OPA_TypeDef* HT_OPAn, u32 cancellation)" + "u32 OPA_GetCancellationVaule(HT_OPA_TypeDef* HT_OPAn)" + + Others + + Update comment, format, typing error, and coding style. + + Update "I2C/Interrupt/main.c" to improve readability. + + Add below notice into USB examples to inform the user turn on the HSI Auto Trim function when the PLL + clock source is HSI (PLL for USB 48 MHz clock). + "Msut turn on if the USB clock source is from HSI (PLL clock Source)" + + Remove the following unnecessary files. + "WDT/Period_Reload/ht32_board_config.h" + "FMC/FLASH_Write_Protection/ht32_board_config.h" + + Remove the remote wake-up function in the "USB_Video/main.c". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v015_4909 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2020-08-11 + + Main Changes + + Add the following files to use e-Link32 Pro with SEGGER Embedded Studio. Refer to the + "readme e-Link32 Pro.txt" for how to use it. + "emStudiov4/readme e-Link32 Pro.txt" + "emStudiov4/Project_xxxxx.bat" + "emStudiov4/_MassErase.bat" + + Add QSPI support. + "ht32f5xxxx_spi.c". + "QSPI_QuadCmd()" + "QSPI_DirectionConfig()" + "utilities/common/spi_flash.c" + "SPI_FLASH_WriteStatus2()" + "QSPI_FLASH_BufferQuadRead()" + "QSPI_FLASH_BufferQuadReadByDMA()" + "QSPI_FLASH_BufferWrite()" + "QSPI_FLASH_BufferWriteByDMA()" + "utilities/HT32_Board" + "ht32f52367_sk.h" + "ht32f0006_dvb.h" + + Add new examples. + "TM/PWM" + "TM/UpdateEvent" + "QSPI/Flash_Quad_Mode_PDMA" + + Change the USB LDO default state from ON (PWRCU_VREG_ENABLE) to OFF (PWRCU_VREG_BYPASS) and + add below notice description. + "USB LDO Should be enabled (PWRCU_VREG_ENABLE) if the MCU VDD > 3.6 V." + + Change the driving current as 8 mA of LCD/SPI Flash utilities driver SPI pins for HT32F50343 (since the + default operation voltage of Starter Kit is 3.3 V). + + Add "SPI_FLASH_WaitForWriteEnd()" function in the end of the write status operation + ("SPI_FLASH_WriteStatus()"). + + Fix typing error of the define, "LIBCFG_MAX_SPEED" for HT32F52220/52230/52231/52241/52243/52253. + There are a few examples that refer to this value to set the IP-related frequency. + + Fix the I2S clock setting error of the following example. + "I2S/CodecLoopback_PDMA" + "USBD/USB_UAC_Sound" + "USBD/USB_UAC_Sound_RateControl" + + Add below notice of examples to inform the user to check the local structure variable without a + default value. + "Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below this function." + + Fix defined problem of "utilities/common/ebi_lcd.c". Change "EBI_FUN_BYTELAND" / "EBI_FUN_ASYNCREADY" to + "LIBCFG_EBI_BYTELAND_ASYNCREADY". + + Fix the "I2S_FIFOTrigLevelConfig()" error which did not clear the field of I2S FCR correctly. + + Fix "RPRE_MASK" define error for "RTC_SetPrescaler()" function. + + Add utilities drivers into HT32F0006/HT32F61352 project. + "i2c_eeprom.c" + "spi_flash.c" + "spi_lcd.c" + + Others + + Update comment, format, typing error, and coding style. + + Add below notice in the "FMC/FLASH_Security" example. + "The Option Byte will be write protected (cannot be changed again) after the + Security Protection is enabled. Refer to the user manual for details." + + Update and modify naming rule of the "HTCFG_xxxx" configuration define in the "ht32_board_config.h". + "I2S/CodecLoopback_PDMA" + + Update the following examples to remove compiler warning of the GNU compiler. + "SLED/ARGB_GetLEDNum" + "USART/PDMA" + + Add "-Waddress-of-packed-member" #pragma of below examples to remove compiler warning of the + GNU compiler. + "USBD/Mass_Storage" + "USBD/HID_Keyboard_Mass_Storage" + + Add the following notice in the Program/Erase related function. + "HSI must keep turn on when doing the Flash operation (Erase/Program)." + + Remove HSI disable setting of Configuration Wizard and add notice in the "system_xxxxx_nn.c". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v014_4736 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2020-04-08 + + Main Changes - Modification & Improvement + + Add "USBDClass_Reset()" into the "USBD/*" example to reset related flag for the self-power application. + + Modify "ht32f5xxxx_aes.c", fix "AES_SetKeyTable()" and "_AES_CryptData()" functions who did not clear + related fields before set it. + + Update UxART related example, turn on internal pull up to prevent unknown state. + + Remove unnecessary RTC compare match restart setting of the "RTC/Calendar_BackupDomain" example. + (which cause the time not correct after entering the low power mode). + + Make up the init structure member when the XXXXX_InitTypeDef is a local variable (which without the + default value). For example, add the following code. + "MCTM_OutputInitStructure.AsymmetricCompare = 0;" + "OutInit.ControlN = TM_CHCTL_DISABLE;" + + Update "TM/InputCapture" example, fix the Pulse Width Count formula (shall be plus with 1). + + Fix RAM size from 8K to 16K of HT32F0006 (LIBCFG_RAM_SIZE). + + Update the following example to improve readability. + "ADC/AnalogWatchdog" + "ADC/Continuous_Potentiometer" + "ADC/Discontinuous_EXTITrigger" + "ADC/InternalReferenceVoltage" + "ADC/OneShot_PWMTrigger" + "ADC/OneShot_PWMTrigger_with_Delay" + "ADC/OneShot_TMTrigger_PDMA" + "ADC/Two_Group_MaxCH" + "EXTI/GPIO_Interrupt" + "HWDIV/DIV32" + "TM/InputCapture" + "TM/MatchOutputActive" + "TM/MatchOutputToggle" + "TM/PWM_Buzzer" + "TM/PWMInput" + "TM/PWMOut_PDMA" + "TM/SinglePulseMode" + "TM/TriggerCounter" + "USART/Interrupt" + "USART/Interrupt_FIFO" + "USART/PDMA" + "USART/Polling" + "USART/Retarget" + "USBD/HID_Demo" + "USBD/HID_DemoVendorReport" + + Main Changes - API Function & Compatibility + + Add "USART_GetIntStatus()" function to get the both enabled and occurred interrupt source. + + Remove the "I2C_Cmd()" in the "I2C_Init()" function since it shall be called after the I2C related + settings. User shall call the "I2C_Cmd()" by themself after the "I2C_Init()". + + Add "DR_8BIT", "DR_16BIT", and "DR_32BIT" define for the "HT_SLEDn" structure. + + Modify "ADC_RegularChannelConfig()", add the last variable-length argument for the code compatibility + between the general HT32 model and the specific model (with the independent sample & hold function of each + ADC channel). + "ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, ...)" + + Modify the following MCTM IRQ define for compatibility. + Old New + ------------- ---------------- + MCTM_BRK_IRQn MCTM0_BRK_IRQn + MCTM_UP_IRQn MCTM0_UP_IRQn + MCTM_TR_UP2_IRQn MCTM0_TR_UP2_IRQn + MCTM_CC_IRQn MCTM0_CC_IRQn + GPTM_G_IRQn GPTM0_G_IRQn + GPTM_VCLK_IRQn GPTM0_VCLK_IRQn + + Modify "AFIO_FUN_ADC" as AFIO_FUN_ADC0. + + Add the following functions of "ht32f5xxxx_div.c". + "DIV_IsDivByZero()": Return the division by zero flag. + "DIV_uDiv32()": Do the 32-bit unsigned division. + "DIV_uGetLastRemainder()": Get remainder of last 32-bit unsigned division. + + Add "u64" definition. + + Add the following definition for convenience. + PDMACH0_IRQn ~ PDMACH5_IRQn + AFIO_FUN_MCTM0 + AFIO_FUN_GPTM0 ~ AFIO_FUN_GPTM3 + AFIO_FUN_PWM0 ~ AFIO_FUN_PWM3 + AFIO_FUN_SCTM0 ~ AFIO_FUN_SCTM3 + + Add "LIBCFG_MAX_SPEED" in the file "ht32fxxxxx_libcfg.h" which indicate the maximum core speed. + + Main Changes - New Example & Supporting + + Add new examples. + "BFTM/OneShot" + "BFTM/TimeMeasure" + "Mono_LCD/LCD_module" (for ESK32-A3A31 mono LCD module) + "SLED/ARGB_GetLEDNum" + "USBD/HID_DemoVendorReport" + + Add example support of HT32F65230/65240 + ADC, BFTM, CRC, EXTI, FMC, GPIO, HWDIV, NVIC, PDMA, PWRCU, RSTCU, RTC, SWDIV, SYSTICK, TM, WDT + + Rename examples as below. + IP Old Name New Name + -------- -------- -------- + ADC EXTITrigger_DiscontinuousMode Discontinuous_EXTITrigger + ADC PDMA_ADCResult OneShot_TMTrigger_PDMA + ADC Potentiometer_ContinuousMode Continuous_Potentiometer + ADC TM_Trigger OneShot_PWMTrigger + ADC TM_Trigger_with_Delay OneShot_PWMTrigger_with_Delay + QSPI Flash Flash_Quad_Mode + TM PWMOutput PWM_Buzzer + USART HyperTerminal_TxRx Retarget + USART HyperTerminal_TxRx_Interrupt Interrupt + USART HyperTerminal_TxRx_Interrupt_FIFO Interrupt_FIFO + Mono_LCD 8CHAR_14SEG_Demo Demo + + Others + + Update comment, format, typing error, and coding style. + + Update and modify naming rule of the "HTCFG_xxxx" configuration define in the "ht32_board_config.h". + + Update "ht32_series.c/h" and "ht32_retarget_usbdconf.h" to improve the compatibly of the + terminal software. + + Add ring buffer support of the "Virtual_COM" and "HID_Keyboard_Virtual_COM" examples. + + Fix interrupt mode of UxART retarget, remove unnecessary FIFO/interrupt configuration of the + retarget function. + + Update "system_ht32fxxxxx_nn.c" (coding style only). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v013_4429 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-12-05 + + Main Changes + + Update "USBD/Virtual_COM" example, add ZLP process for BULK transfer. + + Fix memory size error of HT32F65230. + + Modify "ht32f65230_40_libcfg.h", fix the "USE_MEM_HT32F65230" define problem of HT32F65230. + + Others + + Fix typing error of ""USBD/HID_Keyboard_Virtual_COM" example. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v013_4425 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-11-29 + + Main Changes + + Add new device support. + HT32F65230 + + Changes for HT32F65230 and HT32F65240 + Change USE_HT32F65240 to USE_HT32F65230_40. + Rename "startup_ht3265240_xxx.s" to "startup_ht3265230_40_xxx.s". + + Update "HID_Demo_UI.exe" to support HID Report ID. + + Add "USBD/HID_DemoVendorReport" example. + + Add UART0_IRQn ~ UART3_IRQn define for HT32F52357/52367 (map to UART0_UART2_IRQn and UART1_UART3_IRQn). + + Add "RETARGET_UxART_BAUDRATE" setting to change the retarget UART baudrate in "ht32f5xxxx_conf.h". + + Add "RETARGET_HSI_ATM" setting to turn on/off the auto-trim function of HSI. + + Add "RETARGET_DEFINE_HANDLER" setting to remove the UxARTn_IRQHandler() define of the retarget. + This setting is used for the model who grouping two UART Interrupt into one vector. + + Add non-block mode of USB Virtual-COM retarget function ((Drop data if USB or terminal software is + not ready). + + Fix EXTI4_IRQn ~ EXTI15_IRQn define error of HT32F65230/65240. + + Add SWCLK toggle of "GPIO_DisableDebugPort()" function. + + Others + + Add "USAGE_PAGE_L" define of "USB/HID_Demo" example. + + Add "UART0_UART2_IRQHandler()" and "UART1_UART3_IRQHandler" example in the file "ht32f5xxxx_01_it.c" for + HT32F52357/52367. + + Update format and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v012_4285 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-10-18 + + Main Changes + + Add new device support. + HT32F50343, HT32F59041, HT32F59741, HF5032 + + Fix HT32F65240 IRQ number error of "USART0_IRQn" and "UART0_IRQn". + + Fix "ADC_CH_GND_VREF" and "ADC_CH_VDD_VREF" define error of HT32F65240. + + Add "GPIO_GetID()" function to convert the HT_GPIOx to GPIO_Px. + + Add "LIBCFG_PWRCU_NO_PORF" define of HT32F65240 to fix the "PWRCU_DeInit()" function not work. + + Update "system_ht32fxxxxx.c" and "startup_ht32fxxxxx_xx_nn.s". + + Rename "startup_ht32f5xxxx_01/02.s" of IAR as "startup_ht32f5xxxx_iar_01/02.s". + + Move the "common/*.h" include from the begin to the end (after the pin define) in the file + "HT32_Board/ht32fxxxx_sk/dvb.h". The original include way leads to the pin define lost when you + use the EBI_LCD->EBI_LCD_RAM outside the "ebi_lcd.c". + + Update "ebi_lcd.c", fix LCD_SPI_BL_GPIO_XXX define error (shall be LCD_EBI_BL_GPIO_XXX). + + Fix error of "_CreateProjectScript.bat" which cause the stack size and RW base can not be set by the + "_ProjectConfig.bat" of the emStudiov4 project. + + Others + + Remove the wrong define, "LIBCFG_CKCU_USB_PLL_96M" of HT32F52367. + + Add calculation method of PLL clock in the file, "system_ht32f5xxxx_nn.c". + + Add "utilities/common/lcd.h" to put the lcd related register together. + + Update example to improve readability. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v011_4188 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-08-05 + + Main Changes + + Add new device support. + HT32F57331, HT32F57341, HT32F57342, HT32F57352, HT32F52357, HT32F52367, HT32F52142, + HT32F65240, HT32F61352, HT50F32002, HT50F32003 + + Fix define error of "ht32fxxxxx_libcfg.h". + + Update "system_ht32fxxxxx.c" and "startup_ht32fxxxxx_xx_nn.s". + + Rename "startup_ht32f5xxxx_nn.s" of IAR as "startup_ht32f5xxxx_iar_nn.s". + + Modify ADC related define (The left side old one is still kept for backward compatible). + HT_ADC -> HT_ADC0 + ADC -> ADC0 + ADC_IRQn -> ADC0_IRQn + + Fix typing error of the function name below. + SPI_GUARDTCmd(), SPI_GUARDTConfig() + + Others + + Update content of "readme.txt". + + Add s64 ("typedef signed long long s64;"). + + Update comment and coding style. + + Update and sync "ht32f5xxxx_conf.h". + + Update and sync create project related files ("_ProjectConfig.bat", "_CreateProjectScript.bat"). + + Update "HT32F5xxxx_01_DebugSupport.ini". + + Update "ht32_op.s" and "ht32_op.c". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v010_3748 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-04-09 + + Main Changes + + Update functions of "ht32f5xxxx_dac_dual16.c". + + Update Create Project script, add Script folder in project_template. + + Fix VREFCR/VREFVALR register address error of HT_ADC_TypeDef. + + Fix "ADC_VREFConfig()" error (ADC_VREF_x shift error). + + Add "ADC_MVDDACmd()" function. + + Add "PWRCU_DeepSleep2Ex()" function for the case which wakeup by EXTI in the short time or the wakeup + source keeps active. + Notice: PWRCU_DeepSleep2Ex() function will affect the accuracy of RTC for the date/time application. + + Add "TM/TriggerCounter" example. + + Add "ADC/InternalReferenceVoltage" example. + + Update "ADC/Potentiometer_ContinuousMode" example, remove division in the ISR of ADC. + + Others + + Update "ht32f5xxxx_usbd.c" and "ht32_usbd_core.c", add Force USB Reset Control function (apply to specific + model only). + + Update/sync startup.s/system.c files, fix PLL range and content errors. + + Update "BootProcess" function. + + Update/sync "ht32_op.s" and "ht32_op.c". + + Update "PWRCU/DeepSleepMode1" examples, fix compile error when set "DISABLE_DEBUG_PIN" = 1. + + Update "PWRCU/PowerDownMode" examples + - Update EXTI ISR to reduce maintenance time. + - Add "DISABLE_DEBUG_PIN" function. + + Update/sync "FlashMacro.mac". + + Update Keil after build setting + - Add double quotes (") in the command. + - Change filename keyword from "#L" to "!L" (relative path specification to the current folder). + - Update "fromelf.txt" and "objcopy.txt" + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v009_3383 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2019-02-12 + + Main Changes + + Add SEGGER Embedded Studio IDE support (beta version). + + Update "EXTI/WakeUp_DeepSleepMode1" Example, fix channel error of EXTI clear wakeup flag and add LED3 + (for some SK have only LED2 and LED3 on board). + + Others + + Update comment and coding style. + + Add "USBD/USB_UAC_Sound_RateControl" Example. + + Add "USBD/HID_Keyboard_Mass_Storage" Example. + + Update utilities/common/spi_flash.c/h", change the way of HT_PDMA define. + + Update HT32F0006 MDK-ARM project related files (uvproj*). fix SRAM size. + + Update "LIBCFG_DAC" as "LIBCFG_DACDUAL16" for HT32F0006. + + Add "LIBCFG_DACDUAL16" define for "ht32f5xxxx_dac_dual16.h" of "ht32f5xxxx_lib.h". + + Fix missed "I2C2_IRQHandler" and "AES_IRQHandler" in "startup_ht32f5xxxx_01.s" files (both MDK-ARM and + EWARM). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v008_3322 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-12-17 + + Main Changes + + Fix filename error of IAR EWARM and GNU make file ("ht32f5xxxx_dac_dual16.c"). + + Others + + Update "startup_ht32f5xxxx_xxxx.s". + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v008_3314 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-12-12 + + Main Changes + + Add new device support. + HT32F0006 + + Modify Control IN/OUT method of USB Core, to fix USB transfer problem when CPU in the lower speed or late + USB interrupt case. + + Add workaround for PDMA CH3 issue (Interrupt Enable bit of CH3 is not work). + + Modify "CKCU_ATC_EXT_PIN" as "CKCU_ATC_CKIN". + + Others + + Fix typing error of MCTM. + + Add "LIBCFG_ipname" define to the IP channel of "ht32f5xxxx_pdma.h". + + Add "USBD_DisableDefaultPull()" function to disable pull resistance when the USB is not use. + + Update comment and coding style. + + Rename RTC example as below. + "Calendar" -> "Time" + "Calendar_backup_Domain" -> "Time_BackupDomain" + + Add new example, "RTC/Calendar_BackupDomain". + + Update "EXTI/WakeUp_DeepSleepMode1" example. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v007_3076 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-09-30 + + Main Changes + + Update HardFault_Handler of "ht32f5xxxx_01_it.c",add the debug instruction and system reset. + + Update AES examples, add zero init of local Struct (AES_InitTypeDef AES_InitStruct). + + Add "__HT_check_sp" and "__HT_check_heap" symbol into startup.s and watchpoint command into + "HT32F5xxxx_01_DebugSupport.ini" for debug stack/heap underflow, overflow, and overwrite. + + Add GNU Make support of GNU Arm compiler. + + Add 52354 IAR project files into "project_template/IP/Template_USB". + + Add "LIBCFG_ADC_INTERNAL_CH_V02" define to fix the "ADC_CH_GNDREF/ADC_CH_VREF" mismatch of HT32F502xx + Series (The ADC input channel number of analog ground/power is different between HT32F502xx and other + series). + + Update "USBD/HID_Keyboard_Joystick" and "USBD/HID_Mouse" example, change the set flag sequence + (before USBDCore_EPTWriteINData). + + Others + + Add "objcooy.txt" which shows how to use obj tools of GNU Arm compiler. + + Update format and coding style. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v007_2962 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-08-02 + + Main Changes + + Add GNU Arm compiler support. + - Add project_template related files + - "startup_ht32f5xxxx_gcc_nn.s" + - "linker.ld" (link script) + + Fix typing error of "ht32f52230_sk.h" file. + "COM1_IRQHandler" shall be "UART0_IRQHandler". + + Fix startup.s error of IAP example which cause UART not work. + + Rename "CreatProject.bat" to "_CreateProject.bat" and update its content. + + Update "ht32f5xxxx_tm.c/.h", add following functions which have TM_CH_n parameter. + void TM_ForcedOREF(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, TM_OM_Enum ForcedAction) + void TM_SetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) + void TM_SetAsymmetricCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) + u32 TM_GetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n) + + Others + + Fix compile error when turn on Library debug mode (HT32_LIB_DEBUG = 1). + + Fix compile warning/error of GNU Arm compiler. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v006_2891 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-07-14 + + Main Changes + + None + + Others + + Add "USBD/HID_Keyboard_Virtual_COM" example. + + Add "ADC/Two_Group_MaxCH" example. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v006_2863 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-06-11 + + Main Changes + + Add new device support. + HT32F52344, HT32F52354 + + Add DMA support of "utilities/common/spi_flash.c". + + Add missed function prototype declaration of "GPIO_SinkConfig()" in "ht32f5xxxx_gpio.h". + + Add "EXTI_GetEdgeFlag()" function. + + Add LIBCFG_AES_SWAP function to process endian issue of AES. + + Others + + Update project and "ht32f5826_libcfg.h" typing error of HT32F5826. + + Fix "LIBCFC_CKCU_USB_PLL" typing error of ht32fxxxx_libcfg.h and example code (shall be LIBCFG_CKCU_USB_PLL). + + Add LED3 toggle of "//project_template/IP/Example" since HT32F52253 Starter Kit using LED2 and LED3. + + Fix compiler error of "USBD/USB_UAC_Sound" Example. + + Remove unnecessary define "LIBCFG_CKCU_INTERRUPT_FLAG_V01". + + Update ht32_op.s and ht32_op.c (improve readability). + + FIx memory size typing error of HT32F0008 project. + + Add LIBCFG_FMC_CMD_READY_WAIT define to insert NOP after ISP command for specific model. + + Update USB's example, driver, an setting related to the LIBCFG_CKCU_USB_PLL_96M. + + Update comment and coding style. + + Add MDK_ARMv5 project of IAP example. + + Fix HT32F52352 IAP_PPBIT define error of "IAP/IAP_UI" example. + + Change buffer size of "IAP/IAP_UI" example for the MCU runs on the slower speed. + + Update "USBD/Mass_Storage" example. + + Update "ht32f5xxxx_ckcu.c" to remove unnecessary register write of PLL. + + Update "EXTI/GPIO_Interrupt" example to reduce maintenance effort. + + Update "ht32f52352_sk.h", "ht32f52354_sk.h", and "ebi_lcd.h" to support EBI 8-bit mode with SPI dual output. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v006_2687 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-04-12 + + Main Changes + + Add SourceryG++Lite compiler support. + - Add project_template related files + - "startup_ht32f5xxxx_cs3_nn.s" + - "linker.ld" (link script) + + Fix typing error of "Project_50241.uvproj" files. + + Others + + Update "ht32f5xxxx_conf.h" for AUTO_RETURN (\r) option. + + Update "ht32f5xxxx_div.h" to remove compiler error of SourceryG++Lite compiler. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v005_2639 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2018-02-28 + + Main Changes + + Add "I2C_SpeedOffset" parameter of "I2C_InitTypeDef" struct to reach real I2C speed. + + Add "CKCU/HSI_AutoTrim_By_USB" Example. + + Add "USBD/HID_Keyboard_Joystick" Example. + + Update "CKCU_HSIAutoTrimIsReady" function of "ht32f5xxxx_ckcu.c". + + Others + + Update SPI/PDMA example to support HT32F52243/52253. + + Add "I2C_SpeedOffset" parameter of I2C related examples. + + Update "i2c_eeprom.c" to remove warning on specify compiler. + + Modify EXTI related code of "USBD/HID_Keyboard" Example to reduce maintenance effort. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v005_2481 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-12-30 + + Main Changes + + None + + Others + + Update I2S and USB UAC related examples (Coding style and remove unuse define). + + Fix I2S setting of "USB_UAC_Sound" example. + + Fix define error of "PWRCU/DeepSleepMode1" example. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v005_2470 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-12-29 + + Main Changes + + Add new device support. + HT32F50231, HT32F50241 + Note: The examples of HT32F50220, HT32F50230, HT32F50231, HT32F50241 are under test. Please contact us if + any question. Thanks. + + Update boot related functions of "startup_ht32f5xxxx_nn.s" and "system_ht32f5xxxx_nn.c". + + Fix USB example code which forget to turn on USB PLL of HT32F0008. + + Update IAP example to support HT32F0008. + + Add "GPIO_DisableDebugPort()"" function to disable SWD function. + + Add "GPIO_SinkConfig()" function for sink current configuration (Apply to specific model only). + + Update "ht32_op.c" and "ht32_op.s" to support enable WDT function by Flash Option byte (Apply to specific + model only). + + Add "Clock_Configuration_LSI" example to show how to configure the system clock between High Speed + (PLL, HSI, or HSE) and LSI. + + Others + + Fix errors of following examples (related to the MCU we added recently). + "EXTI/GPIO_Interrupt" + "PWRCU/BOD_LVD" + "PWRCU/PowerDownMode" + "RAND/Random_Number" + "SPI/Slave" + "TM/MatchOutputToggle" + "TM/PWMOut_PDMA" + "TM/PWMOutput" + "TM/SinglePulseMode" + "USART/HyperTerminal_TxRx_Interrupt_FIFO" + "USART/PDMA" + + Fix "LIBCFG_CHIPNAME" typing error of HT32F50220/50230. + + Remove useless "RTC_LSICmd()"" function. + + Update "RTC_LSILoadTrimData()" to prevent hardfault if RTC clock is not enabled when calling this function. + + Update typing error and coding style of "ht32f5xxxx_ckcu.h". + + Change pin assignment of HT32F0008's example. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v005_2267 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-11-30 + + Main Changes + + Add new device support. + HT32F0008 + HT32F50220, HT32F50230 + + Others + + Update "ht32_virtual_com.inf" file, add Digital Signature. + + Update "ht32_usbd_core.c/.h", add vendor request call back capability. + + Fix compiler warning when turn on library debug mode. + + Fix IAR project setting of IAP related examples (Output format). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v004_1996 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-10-19 + + Main Changes + + Update "system_ht32F5xxxx_03.c", modify PLL related setting. + + Change "LIBCFG_WP_2PAGE_PER_BIT" to "LIBCFG_FLASH_2PAGE_PER_WPBIT". + + Others + + Update "PWRCU/DeepSleepMode2" example, fix compiler error when DISABLE_DEBUG_PIN = 1. + + Update "WDT/Period_Reload" example, fix comment typing error. + + Add "LIBCFG_CHIPNAME" define. + + Update project setting. + + Update "NVIC/External_Interrupt" example, remove unuse define. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v004_1790 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-09-05 + + Main Changes + + Fix vector table error ("startup_ht32f5xxxx_01.s"). + + Others + + Update "system_ht32f5xxxx_xx.c". + + Update Keil project setting, enable "User->After Build Run #1" as default value to output Binary file. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32_STD_5xxxx_FWLib_v004_1753 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-08-31 + + Main Changes + + Rename "HT32F520xx_FWLib" to "HT32_STD_5xxxx_FWLib" and "520xx" to "5xxxx". + The following files are also renamed. + Old New + ====================================== ====================================== + startup_ht32f520xx_01.s startup_ht32f5xxxx_01.s + system_ht32f520xx_01.c system_ht32f5xxxx_01.c + system_ht32f5xxxx_02.c system_ht32f5xxxx_02.c + ht32f520xx_01_it.c ht32f5xxxx_01_it.c + ht32f523xx_01_usbdconf.h ht32f5xxxx_01_usbdconf.h + ht32f520xx_01_conf.h ht32f5xxxx_conf.h + HT32F520xx_01_DebugSupport.ini HT32F5xxxx_01_DebugSupport.ini + ht32f520xx_sk.c ht32f5xxxx_board_01.c + ht32f520xx_01.h ht32f5xxxx_01.h + + Others + + Update "ht32_usbd_core.c" to support vendor function. + + Add "USE_MEM_HT32F5xxxx" define into project. + + Add "USE_MEM_HT32F5xxxx" default define into "ht32f5xxxx_xx_libcfg.h". + + Update the IAP Example. Change IAP loader size from 3 KBytes to 4 KBytes (Since the code size of IAP + example for IAR EWARM is large than 3 KB). + + Add new device support + HT32F5826 + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F520xx_FWLib_v003_1661 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-07-27 + + Main Changes + + Add hardware divider driver, "ht32f520xx_div.c/h" + + Update following example to support HT32F52243 and HT32F52253. + DIV, IAP, SPI, TM + Note: The code size of IAP example for IAR EWARM is large than 3 KB. It over Reserved size of the IAP + area. We will update it in the next version. + + Others + + Update project related file and setting. + + Modify USB/Mass_Storage example for WIN10 compatibility issue. + + Update "ht32_op.c" and "ht32_op.s", add CK_CODE/CK_DATA/CK_CODEOP in Option Bytes (same format with e-Writer32). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F520xx_FWLib_v003_1566 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-07-17 + + Main Changes + + Fix COM1 & BUZZER setting error of "ht32f52253_sk.h". + + Update following example to support HT32F52243 and HT32F52253. + ADC, I2C + + Others + + Update ht32_op.s and ht32_op.c + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F520xx_FWLib_v003_1534 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-07-03 + + Main Changes + + Add new device support + HT32F52243, HT32F52253 + Note: The following example is not supported yet for the HT32F52243 and HT32F52253. + ADC, DIV, I2C, IAP, SPI, TM + + Add IAR EWARMv8 project template (create by IAR EWARM v8.11). + + Update "system_ht32f520xx_01.c" and "system_ht32f520xx_02.c" to support different setting between + IAP and AP. + + Fix "ht32_retarget.c" error (UxART Rx interrupt is no need to turn on). + + Update UxART driver to sync with HT32_STD_1xxxx FW Library. + + Modify following variable name of "MCTM_CHBRKCTRInitTypeDef". + Break -> Break0 + BreakPolarity -> Break0Polarity + + Others + + Update project related file and setting. + + Upgrade the version of IAR EWARM project template from v6.20 to v6.50. + Note: + 1. Supported CMSIS-DAP: IAR EWARM v6.50 and above. + 2. RDI/e-Link32 is not supported anymore from the v8.xx of IAR EWARM. + 3. For the Cortex-M0+, you must use IAR EWARM v6.40 and above. + + Update file format and coding style. + + Modify "EXTI_DebounceCnt" of "EXTI_InitTypeDef" from u32 to u16, to prevent count setting over range. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F520xx_FWLib_v002_1320 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2017-05-04 + + Main Changes + + Fix IAR compiler failed issue of "ht32_cm0plus_misc.c" (Tool Internal Error with Access violation error). + + Others + + Fix config error of ADC example, "PWMTrigger_OneShotMode". + + Rename ADC example "PWMTrigger_OneShotMode" as "TM_Trigger". + + Add ADC example, "TM_Trigger_with_Delay". + + Fix I2C register naming (ADDBR to ADDSR). + + Fix build error when Library Debug mode enable. + + Fix IAP example, add "USART_ClearFlag(HTCFG_UART_PORT, USART_FLAG_TOUT)" in the UART ISR. + + Fix SPI Flash dual read, enable dual read function (SPI_DUALCmd()) before send dummy bytes. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F520xx_FWLib_v002_1143 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2016-10-11 + + Main Changes + + Fix FLASH_WP_ALLPAGE_SET macro error. + + Add memory footprint information (ht32fxxxxx_xx_libcfg.h). + + Others + + Update typing error and naming rule. + + Update "ht32f520xx_02.h" variable data type define to prevent data type confusion (such as const s32 not + equal to sc32). + + Modify Re-target to USB Tx buffer size from 63 to 1. Add notice message for SERIAL_Flush() when Tx buffer + size is lager than 1. + + Update MDK_ARMv5 project setting. + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F520xx_FWLib_v002_966 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2016-08-17 + + Main Changes + + Add "CKCU_HSIAutoTrimIsReady()" functions. + + Fix Re-target USB virtual bug (Bulk out 64 Bytes without zero length OUT is not allow). + + Add example code. + + Update IAR EWARM project of example codes. + + Add random number function/example. + + Others + + Rename and update "HT32_Virtual_COM.inf". Add VID/PID for e-Link32Pro USB to UART function. + + Update pin assignment of HT32F52341 SPI/Master example. + + Fix "CKCU_GetClocksFrequency()" and "CKCU_GetPLLFrequency()" error. + + Update typing error and naming rule. + + Fix USB descriptor error of "ht32_retarget_desc.h". + + Fix CKCU/Clock_Configuration example error (CKOUT pin). + +/*----------------------------------------------------------------------------------------------------------*/ +/* HT32F520xx_FWLib_v002_820 */ +/*----------------------------------------------------------------------------------------------------------*/ + Release Date: 2016-06-20 + + Main Changes + + Fix IAP_Text_RAM example setting error. + + Fix "_USBD_CopyMemory()" error. + + Fix EXTI init sequence of HT32F_DVB_PBInit() which may cause unexpect EXTI interrupt. + + Fix LIBCFG_WP_2PAGE_PER_BIT define error of HT32F52331/41. + + Add project files of MDK_ARMv5 (*.uvprojx), select CMSIS-DAP debug adapter as default setting. + + Others + + Fix IAR scanf not work issue + + Add UART interrupt mode for Re-target. + + Improve efficiency of USB re-target (USB IN). + + Modify uIsTerminalOpened check method. + + Fix Re-target to USB bug (OUT data overrun the Rx buffer). + + Remove unnecessary divide/mod operation ("ring_buffer.c", "ht32_serial.c"). + + Remove unnecessary code of "ht32f520xx_tm.c". + + Fix Buffer_GetLength error of "ring_buffer.c". + + Modify __RBIT as RBIT of "ht32_cm0plus_misc.c" (__RBIT is keyword of IAR). diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/SConscript b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/SConscript new file mode 100644 index 00000000000..b673b24b8f6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/SConscript @@ -0,0 +1,49 @@ +import rtconfig +from building import * +Import('rtconfig') + +cwd = GetCurrentDir() +src = [] + +if GetDepend(['SOC_HT32F52352']): + src = Split(""" + library/HT32F5xxxx_Driver/src/ht32_cm0plus_misc.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_adc.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_bftm.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_ckcu.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_cmp.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_crc.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_ebi.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_exti.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_flash.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_gpio.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2c.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2s.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_mctm.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_pdma.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwrcu.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_rstcu.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_rtc.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_sci.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_tm.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_usart.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_usbd.c + library/HT32F5xxxx_Driver/src/ht32f5xxxx_wdt.c + library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_01.c + """) + + + +path = [ + cwd + '/library/HT32F5xxxx_Driver/inc', + cwd + '/library/CMSIS/Include', + cwd + '/library/Device/Holtek/HT32F5xxxx/Include' +] + +CPPDEFINES = ['USE_HT32_DRIVER'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') + diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/ARM.CMSIS.pdsc b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/ARM.CMSIS.pdsc new file mode 100644 index 00000000000..96775d502ae --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/ARM.CMSIS.pdsc @@ -0,0 +1,3271 @@ + + + + CMSIS + CMSIS (Common Microcontroller Software Interface Standard) + ARM + + http://www.keil.com/pack/ + + + + CMSIS-Core(M): 5.6.0 + - Arm Cortex-M85 cpu support + - Arm China STAR-MC1 cpu support + - Updated system_ARMCM55.c + CMSIS-DSP: 1.10.0 (see revision history for details) + CMSIS-NN: 3.1.0 (see revision history for details) + - Support for int16 convolution and fully connected for reference implementation + - Support for DSP extension optimization for int16 convolution and fully connected + - Support dilation for int8 convolution + - Support dilation for int8 depthwise convolution + - Support for int16 depthwise conv for reference implementation including dilation + - Support for int16 average and max pooling for reference implementation + - Support for elementwise add and mul int16 scalar version + - Support for softmax int16 scalar version + - Support for SVDF with 8 bit state tensor + CMSIS-RTOS2: 2.1.3 (unchanged) + - RTX 5.5.4 (see revision history for details) + CMSIS-Pack: deprecated (moved to Open-CMSIS-Pack) + CMSIS-SVD: 1.3.9 (see revision history for details) + CMSIS-DAP: 2.1.1 (see revision history for details) + - Allow default clock frequency to use fast clock mode + Devices + - Support for Cortex-M85 + Utilities + - SVDConv 3.3.42 + - PackChk 1.3.95 + + + CMSIS-Core(M): 5.5.0 (see revision history for details) + - Updated GCC LinkerDescription, GCC Assembler startup + - Added Armv8-M Stack Sealing (to linker, startup) for toolchain ARM, GCC + - Changed C-Startup to default Startup. + - Updated Armv8-M Assembler startup to use GAS syntax + Note: Updating existing projects may need manual user interaction! + CMSIS-Core(A): 1.2.1 (see revision history for details) + - Bugfixes for Cortex-A32 + CMSIS-DAP: 2.1.0 (see revision history for details) + - Enhanced DAP_Info + - Added extra UART support + CMSIS-DSP: 1.9.0 (see revision history for details) + - Purged pre-built libs from Git + - Enhanced support for f16 datatype + - Fixed couple of GCC issues + CMSIS-NN: 3.0.0 (see revision history for details including version 2.0.0) + - Major interface change for functions compatible with TensorFlow Lite for Microcontroller + - Added optimization for SVDF kernel + - Improved MVE performance for fully Connected and max pool operator + - NULL bias support for fully connected operator in non-MVE case(Can affect performance) + - Expanded existing unit test suite along with support for FVP + - Removed Examples folder + CMSIS-RTOS2: + - RTX 5.5.3 (see revision history for details) + - CVE-2021-27431 vulnerability mitigation. + - Enhanced stack overrun checking. + - Various bug fixes and improvements. + CMSIS-Pack: 1.7.2 (see revision history for details) + - Support for Microchip XC32 compiler + - Support for Custom Datapath Extension + + + CMSIS-Build: 0.9.0 (beta) + - Draft for CMSIS Project description (CPRJ) + CMSIS-Core(M): 5.4.0 (see revision history for details) + - Cortex-M55 cpu support + - Enhanced MVE support for Armv8.1-MML + - Fixed device config define checks. + - L1 Cache functions for Armv7-M and later + CMSIS-Core(A): 1.2.0 (see revision history for details) + - Fixed GIC_SetPendingIRQ to use GICD_SGIR + - Added missing DSP intrinsics + - Reworked assembly intrinsics: volatile, barriers and clobber + CMSIS-DSP: 1.8.0 (see revision history for details) + - Added new functions and function groups + - Added MVE support + CMSIS-NN: 1.3.0 (see revision history for details) + - Added MVE support + - Further optimizations for kernels using DSP extension + CMSIS-RTOS2: + - RTX 5.5.2 (see revision history for details) + CMSIS-Driver: 2.8.0 + - Added VIO API 0.1.0 (Preview) + - removed volatile from status related typedefs in APIs + - enhanced WiFi Interface API with support for polling Socket Receive/Send + CMSIS-Pack: 1.6.3 (see revision history for details) + - deprecating all types specific to cpdsc format. Cpdsc is replaced by Cprj with dedicated schema. + Devices: + - ARMCM55 device + - ARMv81MML startup code recognizing __MVE_USED macro + - Refactored vector table references for all Cortex-M devices + - Reworked ARMCM* C-StartUp files. + - Include L1 Cache functions in ARMv8MML/ARMv81MML devices + Utilities: + Attention: Linux binaries moved to Linux64 folder! + - SVDConv 3.3.35 + - PackChk 1.3.89 + + + CMSIS-Core(M): 5.3.0 (see revision history for details) + - Added provisions for compiler-independent C startup code. + CMSIS-Core(A): 1.1.4 (see revision history for details) + - Fixed __FPU_Enable. + CMSIS-DSP: 1.7.0 (see revision history for details) + - New Neon versions of f32 functions + - Python wrapper + - Preliminary cmake build + - Compilation flags for FFTs + - Changes to arm_math.h + CMSIS-NN: 1.2.0 (see revision history for details) + - New function for depthwise convolution with asymmetric quantization. + - New support functions for requantization. + CMSIS-RTOS: + - RTX 4.82.0 (updated provisions for Arm Compiler 6 when using Cortex-M0/M0+) + CMSIS-RTOS2: + - RTX 5.5.1 (see revision history for details) + CMSIS-Driver: 2.7.1 + - WiFi Interface API 1.0.0 + Devices: + - Generalized C startup code for all Cortex-M family devices. + - Updated Cortex-A default memory regions and MMU configurations + - Moved Cortex-A memory and system config files to avoid include path issues + + + The following folders are deprecated + - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) + + CMSIS-Core(M): 5.2.1 (see revision history for details) + - Fixed compilation issue in cmsis_armclang_ltm.h + + + The following folders have been removed: + - CMSIS/Lib/ (superseded by CMSIS/DSP/Lib/) + - CMSIS/DSP_Lib/ (superseded by CMSIS/DSP/) + The following folders are deprecated + - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) + + CMSIS-Core(M): 5.2.0 (see revision history for details) + - Reworked Stack/Heap configuration for ARM startup files. + - Added Cortex-M35P device support. + - Added generic Armv8.1-M Mainline device support. + CMSIS-Core(A): 1.1.3 (see revision history for details) + CMSIS-DSP: 1.6.0 (see revision history for details) + - reworked DSP library source files + - reworked DSP library documentation + - Changed DSP folder structure + - moved DSP libraries to folder ./DSP/Lib + - ARM DSP Libraries are built with ARMCLANG + - Added DSP Libraries Source variant + CMSIS-RTOS2: + - RTX 5.5.0 (see revision history for details) + CMSIS-Driver: 2.7.0 + - Added WiFi Interface API 1.0.0-beta + - Added components for project specific driver implementations + CMSIS-Pack: 1.6.0 (see revision history for details) + Devices: + - Added Cortex-M35P and ARMv81MML device templates. + - Fixed C-Startup Code for GCC (aligned with other compilers) + Utilities: + - SVDConv 3.3.25 + - PackChk 1.3.82 + + + Aligned pack structure with repository. + The following folders are deprecated: + - CMSIS/Include/ + - CMSIS/DSP_Lib/ + + CMSIS-Core(M): 5.1.2 (see revision history for details) + - Added Cortex-M1 support (beta). + CMSIS-Core(A): 1.1.2 (see revision history for details) + CMSIS-NN: 1.1.0 + - Added new math functions. + CMSIS-RTOS2: + - API 2.1.3 (see revision history for details) + - RTX 5.4.0 (see revision history for details) + * Updated exception handling on Cortex-A + CMSIS-Driver: + - Flash Driver API V2.2.0 + Utilities: + - SVDConv 3.3.21 + - PackChk 1.3.71 + + + Updated Arm company brand. + CMSIS-Core(M): 5.1.1 (see revision history for details) + CMSIS-Core(A): 1.1.1 (see revision history for details) + CMSIS-DAP: 2.0.0 (see revision history for details) + CMSIS-NN: 1.0.0 + - Initial contribution of the bare metal Neural Network Library. + CMSIS-RTOS2: + - RTX 5.3.0 (see revision history for details) + - OS Tick API 1.0.1 + + + CMSIS-Core(M): 5.1.0 (see revision history for details) + - Added MPU Functions for ARMv8-M for Cortex-M23/M33. + - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler. + CMSIS-Core(A): 1.1.0 (see revision history for details) + - Added compiler_iccarm.h. + - Added additional access functions for physical timer. + CMSIS-DAP: 1.2.0 (see revision history for details) + CMSIS-DSP: 1.5.2 (see revision history for details) + CMSIS-Driver: 2.6.0 (see revision history for details) + - CAN Driver API V1.2.0 + - NAND Driver API V2.3.0 + CMSIS-RTOS: + - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata. + CMSIS-RTOS2: + - API 2.1.2 (see revision history for details) + - RTX 5.2.3 (see revision history for details) + Devices: + - Added GCC startup and linker script for Cortex-A9. + - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU. + - Added IAR startup code for Cortex-A9 + + + CMSIS-RTOS2: + - RTX 5.2.1 (see revision history for details) + + + CMSIS-Core(M): 5.0.2 (see revision history for details) + - Changed Version Control macros to be core agnostic. + - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7. + CMSIS-Core(A): 1.0.0 (see revision history for details) + - Initial release + - IRQ Controller API 1.0.0 + CMSIS-Driver: 2.05 (see revision history for details) + - All typedefs related to status have been made volatile. + CMSIS-RTOS2: + - API 2.1.1 (see revision history for details) + - RTX 5.2.0 (see revision history for details) + - OS Tick API 1.0.0 + CMSIS-DSP: 1.5.2 (see revision history for details) + - Fixed GNU Compiler specific diagnostics. + CMSIS-Pack: 1.5.0 (see revision history for details) + - added System Description File (*.SDF) Format + CMSIS-Zone: 0.0.1 (Preview) + - Initial specification draft + + + Package Description: + - added taxonomy for Cclass RTOS + CMSIS-RTOS2: + - API 2.1 (see revision history for details) + - RTX 5.1.0 (see revision history for details) + CMSIS-Core: 5.0.1 (see revision history for details) + - Added __PACKED_STRUCT macro + - Added uVisior support + - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__ + - Updated template for secure main function (main_s.c) + - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c) + CMSIS-DSP: 1.5.1 (see revision history for details) + - added ARMv8M DSP libraries. + CMSIS-Pack:1.4.9 (see revision history for details) + - added Pack Index File specification and schema file + + + Changed open source license to Apache 2.0 + CMSIS_Core: + - Added support for Cortex-M23 and Cortex-M33. + - Added ARMv8-M device configurations for mainline and baseline. + - Added CMSE support and thread context management for TrustZone for ARMv8-M + - Added cmsis_compiler.h to unify compiler behaviour. + - Updated function SCB_EnableICache (for Cortex-M7). + - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType + CMSIS-RTOS: + - bug fix in RTX 4.82 (see revision history for details) + CMSIS-RTOS2: + - new API including compatibility layer to CMSIS-RTOS + - reference implementation based on RTX5 + - supports all Cortex-M variants including TrustZone for ARMv8-M + CMSIS-SVD: + - reworked SVD format documentation + - removed SVD file database documentation as SVD files are distributed in packs + - updated SVDConv for Win32 and Linux + CMSIS-DSP: + - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib. + - Added DSP libraries build projects to CMSIS pack. + + + - CMSIS-Core 4.30.0 (see revision history for details) + - CMSIS-DAP 1.1.0 (unchanged) + - CMSIS-Driver 2.04.0 (see revision history for details) + - CMSIS-DSP 1.4.7 (no source code change [still labeled 1.4.5], see revision history for details) + - CMSIS-Pack 1.4.1 (see revision history for details) + - CMSIS-RTOS 4.80.0 Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details) + - CMSIS-SVD 1.3.1 (see revision history for details) + + + - CMSIS-Core 4.20 (see revision history for details) + - CMSIS-DSP 1.4.6 (no source code change [still labeled 1.4.5], see revision history for details) + - CMSIS-Pack 1.4.0 (adding memory attributes, algorithm style) + - CMSIS-Driver 2.03.0 (adding CAN [Controller Area Network] API) + - CMSIS-RTOS + -- API 1.02 (unchanged) + -- RTX 4.79 (see revision history for details) + - CMSIS-SVD 1.3.0 (see revision history for details) + - CMSIS-DAP 1.1.0 (extended with SWO support) + + + - CMSIS-Core 4.10 (Cortex-M7 extended Cache Maintenance functions) + - CMSIS-DSP 1.4.5 (see revision history for details) + - CMSIS-Driver 2.02 (adding SAI (Serial Audio Interface) API) + - CMSIS-Pack 1.3.3 (Semantic Versioning, Generator extensions) + - CMSIS-RTOS + -- API 1.02 (unchanged) + -- RTX 4.78 (see revision history for details) + - CMSIS-SVD 1.2 (unchanged) + + + Adding Cortex-M7 support + - CMSIS-Core 4.00 (Cortex-M7 support, corrected C++ include guards in core header files) + - CMSIS-DSP 1.4.4 (Cortex-M7 support and corrected out of bound issues) + - CMSIS-Pack 1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial) + - CMSIS-SVD 1.2 (Cortex-M7 extensions) + - CMSIS-RTOS RTX 4.75 (see revision history for details) + + + - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices + + + - CMSIS-Driver 2.02 (incompatible update) + - CMSIS-Pack 1.3 (see revision history for details) + - CMSIS-DSP 1.4.2 (unchanged) + - CMSIS-Core 3.30 (unchanged) + - CMSIS-RTOS RTX 4.74 (unchanged) + - CMSIS-RTOS API 1.02 (unchanged) + - CMSIS-SVD 1.10 (unchanged) + PACK: + - removed G++ specific files from PACK + - added Component Startup variant "C Startup" + - added Pack Checking Utility + - updated conditions to reflect tool-chain dependency + - added Taxonomy for Graphics + - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers" + + + + - CMSIS-RTOS 4.74 (see revision history for details) + - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1. + + + + + + + + + Software components for audio processing + Generic Interfaces for Evaluation and Development Boards + Drivers that support an external component available on an evaluation board + Compiler Software Extensions + Cortex Microcontroller Software Interface Components + Unified Device Drivers compliant to CMSIS-Driver Specifications + Startup, System Setup + Data exchange or data formatter + Drivers that support an extension board or shield + File Drive Support and File System + IoT cloud client connector + IoT specific services + IoT specific software utility + Graphical User Interface + Network Stack using Internet Protocols + Real-time Operating System + Encryption for secure communication or storage + Universal Serial Bus Stack + Generic software utility components + + + + + + + +The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + +The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + + + + + + +The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA. +The ARM Cortex-M1 processor implements the ARMv6-M architecture profile. + + + + + + + + + + + + + + + + +The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + +The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + + + + + + +The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling +- upward compatibility with the rest of the Cortex-M processor family. + + + + + + + + + + + + + + + + + + + + + + + + + + +The Arm Cortex-M23 is based on the Armv8-M baseline architecture. +It is the smallest and most energy efficient Arm processor with Arm TrustZone technology. +Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security. + + + + + + + + + + + + + + + + + + + + + + + +The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller +class processor based on the Armv8-M mainline architecture with Arm TrustZone security. + + + + + + + + + + + + no DSP Instructions, no Floating Point Unit, no TrustZone + + + + + + + + no DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, no TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller +class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications. + + + + + + + + + + + + + no DSP Instructions, no Floating Point Unit, no TrustZone + + + + + + + + no DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, no TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-M55 processor is a fully synthesizable, mid-range, microcontroller-class processor that implements the Armv8.1-M mainline architecture and includes support for the M-profile Vector Extension (MVE), also known as Arm Helium technology. +It is Arm's most AI-capable Cortex-M processor, delivering enhanced, energy-efficient digital signal processing (DSP) and machine learning (ML) performance. +The Cortex-M55 processor achieves high compute performance across scalar and vector operations, while maintaining low energy consumption. + + + + + + + + + + + + + Floating Point Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-M85 processor is a fully synthesizable high-performance microcontroller class processor that implements the Armv8.1-M Mainline architecture which includes support for the M-profile Vector Extension (MVE). +The processor also supports previous Armv8-M architectural features. +The design is focused on compute applications such as Digital Signal Processing (DSP) and machine learning. +The Arm Cortex-M85 processor is energy efficient and achieves high compute performance across scalar and vector operations while maintaining low power consumption. + + + + + + + + + + + + + Floating Point Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone, PACBTI + + + + + + + + +The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling + + + + + + + + + + + + + + + +The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: +- simple, easy-to-use programmers model +- highly efficient ultra-low power operation +- excellent code density +- deterministic, high-performance interrupt handling + + + + + + + + + + + + + + + + +Armv8-M Baseline based device with TrustZone + + + + + + + + + + + + + + + + + + +Armv8-M Mainline based device with TrustZone + + + + + + + + + + + + no DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + no DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + + + + no DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + + +Armv8.1-M Mainline based device with TrustZone and MVE + + + + + + + + + + + + + Double Precision Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + + + + + + +The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full +virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit +Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family. + + + + + + + + + + + + + + + + + +The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture. +The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem, +an optional integrated GIC, and an optional L2 cache controller. + + + + + + + + + + + + + + + + + +The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities. +The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions, +and 8-bit Java bytecodes in Jazelle state. + + + + + + + + + + + + + + + + + + + Device interrupt controller interface + + + + + + RTOS Kernel system tick timer interface + + + + + + + CMSIS-RTOS API for Cortex-M, SC000, and SC300 + + + + + + CMSIS-RTOS API for Cortex-M, SC000, and SC300 + + + + + + + + USART Driver API for Cortex-M + + + + + + + SPI Driver API for Cortex-M + + + + + + + SAI Driver API for Cortex-M + + + + + + + I2C Driver API for Cortex-M + + + + + + + CAN Driver API for Cortex-M + + + + + + + Flash Driver API for Cortex-M + + + + + + + MCI Driver API for Cortex-M + + + + + + + NAND Flash Driver API for Cortex-M + + + + + + + Ethernet MAC and PHY Driver API for Cortex-M + + + + + + + + Ethernet MAC Driver API for Cortex-M + + + + + + + Ethernet PHY Driver API for Cortex-M + + + + + + + USB Device Driver API for Cortex-M + + + + + + + USB Host Driver API for Cortex-M + + + + + + + WiFi driver + + + + + + + Virtual I/O + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Armv6-M architecture based device + + + + + + + Armv7-M architecture based device + + + + + + + Armv8-M base line architecture based device + + + + + Armv8-M main line architecture based device + + + + + + + Armv8.1-M main line architecture based device + + + + + + Armv8-M/Armv8.1-M architecture based device + + + + + Armv8-M architecture based device + + + + + + Armv6_7-M architecture based device + + + + + Armv6_7_8-M architecture based device + + + + + + Armv7-A architecture based device + + + + + + + TrustZone + + + + TrustZone (Secure) + + + + + TrustZone (Non-secure) + + + + + + + + Startup files for Arm Compiler 6 targeting TrustZone secure mode + + + + + Startup files for Arm Compiler 6 targeting non-TrustZone or TrustZone non-secure mode + + + + + + + Generic Arm Cortex-M0 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M0+ device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M1 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M3 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M4 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M7 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M23 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M33 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M35P device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M55 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-M85 device startup and depends on CMSIS Core + + + + + + Generic Arm SC000 device startup and depends on CMSIS Core + + + + + + Generic Arm SC300 device startup and depends on CMSIS Core + + + + + + Generic Armv8-M Baseline device startup and depends on CMSIS Core + + + + + + Generic Armv8-M Mainline device startup and depends on CMSIS Core + + + + + + Generic Armv8.1-M Mainline device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-A5 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-A7 device startup and depends on CMSIS Core + + + + + + Generic Arm Cortex-A9 device startup and depends on CMSIS Core + + + + + + + Components required for DSP + + + + + + + + Components required for NN + + + + + + Components required for RTOS RTX + + + + + + + Components required for RTOS RTX IFX + + + + + + + + Components required for RTOS RTX5 + + + + + + Components required for RTOS2 RTX5 + + + + + + + Components required for RTOS2 RTX5 on Armv7-A + + + + + + + + + Components required for RTOS2 RTX5 in Non-Secure Domain + + + + + + + + + Arm Compiler for Armv6-M architecture (little endian) + + + + + + Arm Compiler for Armv6-M architecture (big endian) + + + + + + Arm Compiler for Armv7-M architecture without FPU (little endian) + + + + + + + Arm Compiler for Armv7-M architecture without FPU (big endian) + + + + + + + Arm Compiler for Armv7-M architecture with FPU (little endian) + + + + + + + + Arm Compiler for Armv7-M architecture with FPU (big endian) + + + + + + + + Arm Compiler for Armv8-M base line architecture (little endian) + + + + + + Arm Compiler for Armv8-M/Armv8.1-M main line architecture without FPU/MVE (little endian) + + + + + + + + Arm Compiler for Armv8-M/Armv8.1-M main line architecture with FPU/MVE (little endian) + + + + + + + + + + + GNU Compiler for Armv6-M architecture (little endian) + + + + + + GNU Compiler for Armv6-M architecture (big endian) + + + + + + GNU Compiler for Armv7-M architecture without FPU (little endian) + + + + + + + GNU Compiler for Armv7-M architecture without FPU (big endian) + + + + + + + GNU Compiler for Armv7-M architecture with FPU (little endian) + + + + + + + + GNU Compiler for Armv7-M architecture with FPU (big endian) + + + + + + + + GNU Compiler for Armv8-M base line architecture (little endian) + + + + + + GNU Compiler for Armv8-M/Armv8.1-M main line architecture without FPU/MVE (little endian) + + + + + + + + GNU Compiler for Armv8-M/Armv8.1-M main line architecture with FPU/MVE (little endian) + + + + + + + + + + + IAR Compiler for Armv6-M architecture (little endian) + + + + + + IAR Compiler for Armv6-M architecture (big endian) + + + + + + IAR Compiler for Armv7-M architecture without FPU (little endian) + + + + + + + IAR Compiler for Armv7-M architecture without FPU (big endian) + + + + + + + IAR Compiler for Armv7-M architecture with FPU (little endian) + + + + + + + + IAR Compiler for Armv7-M architecture with FPU (big endian) + + + + + + + + IAR Compiler for Armv8-M base line architecture (little endian) + + + + + + IAR Compiler for Armv8-M main line architecture without FPU (little endian) + + + + + + + IAR Compiler for Armv8-M main line architecture with FPU (little endian) + + + + + + + + IAR Compiler for Armv8.1-M main line architecture without FPU/MVE (little endian) + + + + + + + + IAR Compiler for Armv8.1-M main line architecture with FPU/MVE (little endian) + + + + + + + + + + + Arm Assembler for Armv6-M architecture + + + + + GNU Assembler for Armv6-M architecture + + + + + + IAR Assembler for Armv6-M architecture + + + + + + Arm Assembler for Armv7-M architecture + + + + + GNU Assembler for Armv7-M architecture + + + + + + IAR Assembler for Armv7-M architecture + + + + + + GNU Assembler for Armv8-M base line architecture + + + + + GNU Assembler for Armv8-M/Armv8.1-M main line architecture + + + + + IAR Assembler for Armv8-M base line architecture + + + + + IAR Assembler for Armv8-M main line architecture + + + + + + Arm Assembler for Armv7-A architecture + + + + + GNU Assembler for Armv7-A architecture + + + + + + IAR Assembler for Armv7-A architecture + + + + + + + Components required for OS Tick Private Timer + + + + + + + Components required for OS Tick Generic Physical Timer + + + + + + + + + + CMSIS-CORE for Cortex-M, SC000, SC300, Star-MC1, ARMv8-M, ARMv8.1-M + + + + + + + + + + + + + CMSIS-CORE for Cortex-A + + + + + + + + + + + System and Startup for Generic Arm Cortex-M0 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M0 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M0+ device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M0+ device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M1 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M1 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M3 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M3 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M4 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M4 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M7 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M7 device + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M23 device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M23 device + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M33 device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M33 device + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-M35P device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M35P device + + + + + + + + + + + + + + + + + + + System and Startup for Generic Cortex-M55 device + + + + + + + + + + + + + + + + + System and Startup for Generic Cortex-M85 device + + + + + + + + + + + + + + + + + System and Startup for Generic Arm SC000 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm SC000 device + + + + + + + + + + + + + + + System and Startup for Generic Arm SC300 device + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm SC300 device + + + + + + + + + + + + + + + System and Startup for Generic Armv8-M Baseline device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Armv8-M Baseline device + + + + + + + + + + + + + + + + + + System and Startup for Generic Armv8-M Mainline device + + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Armv8-M Mainline device + + + + + + + + + + + + + + + + + + System and Startup for Generic Armv8.1-M Mainline device + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-A5 device + + + + + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-A7 device + + + + + + + + + + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-A9 device + + + + + + + + + + + + + + + + + + + + + + IRQ Controller implementation using GIC + + + + + + + + OS Tick implementation using Private Timer + + + + + + + OS Tick implementation using Generic Physical Timer + + + + + + + + CMSIS-DSP Library for Cortex-M, SC000, and SC300 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-NN Neural Network Library + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300 + + + #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ + #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata + + + #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ + #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300 + + + #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ + #define RTE_CMSIS_RTOS_RTX5 /* CMSIS-RTOS Keil RTX5 */ + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Library) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Library) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Source) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Armv7-A (Source) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Source) + + + #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ + #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Access to #include Driver_USART.h file and code template for custom implementation + + + + + + + Access to #include Driver_SPI.h file and code template for custom implementation + + + + + + + Access to #include Driver_SAI.h file and code template for custom implementation + + + + + + + Access to #include Driver_I2C.h file and code template for custom implementation + + + + + + + Access to #include Driver_CAN.h file and code template for custom implementation + + + + + + + Access to #include Driver_Flash.h file and code template for custom implementation + + + + + + + Access to #include Driver_MCI.h file and code template for custom implementation + + + + + + + Access to #include Driver_NAND.h file and code template for custom implementation + + + + + + + Access to #include Driver_ETH_PHY/MAC.h files and code templates for custom implementation + + + + + + + + + Access to #include Driver_ETH_MAC.h file and code template for custom implementation + + + + + + + Access to #include Driver_ETH_PHY.h file and code template for custom implementation + + + + + + + Access to #include Driver_USBD.h file and code template for custom implementation + + + + + + + Access to #include Driver_USBH.h file and code template for custom implementation + + + + + + + Access to #include Driver_WiFi.h file + + + + + + + + + Virtual I/O custom implementation template + + + + + + Virtual I/O implementation using memory only + + + + + + + + + + uVision Simulator + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + EWARM Simulator + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DSP_Lib Bayes example + + + + + + + + + Getting Started + + + + + DSP_Lib Class Marks example + + + + + + + + + Getting Started + + + + + DSP_Lib Convolution example + + + + + + + + + Getting Started + + + + + DSP_Lib Dotproduct example + + + + + + + + + Getting Started + + + + + DSP_Lib FFT Bin example + + + + + + + + + Getting Started + + + + + DSP_Lib FIR example + + + + + + + + + Getting Started + + + + + DSP_Lib Graphic Equalizer example + + + + + + + + + Getting Started + + + + + DSP_Lib Linear Interpolation example + + + + + + + + + Getting Started + + + + + DSP_Lib Matrix example + + + + + + + + + Getting Started + + + + + DSP_Lib Signal Convergence example + + + + + + + + + Getting Started + + + + + DSP_Lib Sinus/Cosinus example + + + + + + + + + Getting Started + + + + + DSP_Lib SVM example + + + + + + + + + Getting Started + + + + + DSP_Lib Variance example + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Blinky example + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 mixed API v1 and v2 + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Message Queue Example + + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Memory Pool Example + + + + + + + + + + Getting Started + + + + + Bare-metal secure/non-secure example without RTOS + + + + + + + + + Getting Started + + + + + Secure/non-secure RTOS example with thread context management + + + + + + + + + Getting Started + + + + + Secure/non-secure RTOS example with security test cases and system recovery + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Blinky example + + + + + + + + + Getting Started + + + + + CMSIS-RTOS2 Message Queue Example + + + + + + + + + Getting Started + + + + + + diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cachel1_armv7.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cachel1_armv7.h new file mode 100644 index 00000000000..abebc95f946 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armcc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 00000000000..a955d471391 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 00000000000..69114177477 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang_ltm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 00000000000..1e255d5907f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_compiler.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 00000000000..adbf296f15a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_gcc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 00000000000..67bda4ef3c3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_iccarm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 00000000000..65b824b009c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_version.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 00000000000..8b4765f186e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv81mml.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv81mml.h new file mode 100644 index 00000000000..94128a1a709 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv81mml.h @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mbl.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mbl.h new file mode 100644 index 00000000000..e9c9b5bf591 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mml.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mml.h new file mode 100644 index 00000000000..c119fbf2424 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_armv8mml.h @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm0.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 00000000000..0a0ba223e19 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm0plus.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 00000000000..879a384124e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm1.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm1.h new file mode 100644 index 00000000000..83b8fc6a0d1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm23.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 00000000000..f2cf49fb16c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm3.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 00000000000..74fb87e5c56 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm33.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 00000000000..18a2e6fb034 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm35p.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm35p.h new file mode 100644 index 00000000000..3843d9542c5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm35p.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm4.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 00000000000..e21cd149256 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm55.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm55.h new file mode 100644 index 00000000000..faa30ce36a9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm55.h @@ -0,0 +1,4817 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ + +/* 'SCnSCB' is deprecated and replaced by 'ICB' */ +typedef ICB_Type SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) + +#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) +#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) + +#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) +#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) + +#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) +#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) + +#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) +#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) + +#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) +#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) + +#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) +#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) + +#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) +#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) + +#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) +#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) + +#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) +#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) +#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) + +#define SCnSCB (ICB) +#define SCnSCB_NS (ICB_NS) + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm7.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 00000000000..010506e9fa4 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm85.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm85.h new file mode 100644 index 00000000000..60463111897 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_cm85.h @@ -0,0 +1,4672 @@ +/**************************************************************************//** + * @file core_cm85.h + * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File + * @version V1.0.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "pac_armv81.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_sc000.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 00000000000..e252068ce64 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_sc300.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 00000000000..d66621031e0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_starmc1.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_starmc1.h new file mode 100644 index 00000000000..ebc0f77eb73 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/core_starmc1.h @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv7.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 00000000000..9909f83990b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv8.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 00000000000..19855b9667c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/pac_armv81.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/pac_armv81.h new file mode 100644 index 00000000000..854b60a204c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/pac_armv81.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/pmu_armv8.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/pmu_armv8.h new file mode 100644 index 00000000000..aa53bb47c1f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/tz_context.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/tz_context.h new file mode 100644 index 00000000000..facc2c9a47e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/main_s.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/main_s.c new file mode 100644 index 00000000000..0e56b7cb947 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/main_s.c @@ -0,0 +1,58 @@ +/****************************************************************************** + * @file main_s.c + * @brief Code template for secure main function + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Use CMSE intrinsics */ +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +/* TZ_START_NS: Start address of non-secure application */ +#ifndef TZ_START_NS +#define TZ_START_NS (0x200000U) +#endif + +/* typedef for non-secure callback functions */ +typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); + +/* Secure main() */ +int main(void) { + funcptr_void NonSecure_ResetHandler; + + /* Add user setup code for secure part here*/ + + /* Set non-secure main stack (MSP_NS) */ + __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); + + /* Get non-secure reset handler */ + NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); + + /* Start non-secure state software application */ + NonSecure_ResetHandler(); + + /* Non-secure software does not return, this code is not executed */ + while (1) { + __NOP(); + } +} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/tz_context.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/tz_context.c new file mode 100644 index 00000000000..e2e82942f81 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Template/ARMv8-M/tz_context.c @@ -0,0 +1,200 @@ +/****************************************************************************** + * @file tz_context.c + * @brief Context Management for Armv8-M TrustZone - Sample implementation + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2016-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + // Privileged Thread Mode using PSP + __set_CONTROL(0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armcc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 00000000000..a955d471391 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armclang.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 00000000000..69114177477 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 00000000000..1e255d5907f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_compiler.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 00000000000..adbf296f15a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_gcc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 00000000000..67bda4ef3c3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_iccarm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 00000000000..65b824b009c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_version.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_version.h new file mode 100644 index 00000000000..8b4765f186e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/core_cm0plus.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/core_cm0plus.h new file mode 100644 index 00000000000..879a384124e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/core_cm3.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/core_cm3.h new file mode 100644 index 00000000000..74fb87e5c56 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/mpu_armv7.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/mpu_armv7.h new file mode 100644 index 00000000000..9909f83990b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/LICENSE.txt b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/LICENSE.txt new file mode 100644 index 00000000000..8dada3edaf5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/README.md b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/README.md new file mode 100644 index 00000000000..0630bf8cd4f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/README.md @@ -0,0 +1,141 @@ +# CMSIS Version 5 + +[![Version](https://img.shields.io/github/v/release/arm-software/CMSIS_5)](https://github.com/ARM-software/CMSIS_5/releases/latest) [![License](https://img.shields.io/github/license/arm-software/CMSIS_5)](https://arm-software.github.io/CMSIS_5/General/html/LICENSE.txt) + +The branch *master* of this GitHub repository contains ![Version](https://img.shields.io/github/v/release/arm-software/CMSIS_5?display_name=release&label=%20&sort=semver). +The [documentation](http://arm-software.github.io/CMSIS_5/General/html/index.html) is available under http://arm-software.github.io/CMSIS_5/General/html/index.html + +Use [Issues](https://github.com/ARM-software/CMSIS_5#issues-and-labels) to provide feedback and report problems for CMSIS Version 5. + +**Note:** The branch *develop* of this GitHub repository reflects our current state of development and is constantly updated. It gives our users and partners contiguous access to the CMSIS development. It allows you to review the work and provide feedback or create pull requests for contributions. + +A [pre-built documentation](https://arm-software.github.io/CMSIS_5/develop/General/html/index.html) is updated from time to time, but may be also generated using the instructions under [Generate CMSIS Pack for Release](https://github.com/ARM-software/CMSIS_5#generate-cmsis-pack-for-release). + +## Overview of CMSIS Components + +The following is an list of all CMSIS components that are available. + +| CMSIS-... | Target Processors | Description | +|:----------|:--------------------|:-------------| +|[Core(M)](http://arm-software.github.io/CMSIS_5/Core/html/index.html) | All Cortex-M, SecurCore | Standardized API for the Cortex-M processor core and peripherals. Includes intrinsic functions for Cortex-M4/M7/M33/M35P SIMD instructions.| +|[Core(A)](http://arm-software.github.io/CMSIS_5/Core_A/html/index.html)| Cortex-A5/A7/A9 | API and basic run-time system for the Cortex-A5/A7/A9 processor core and peripherals.| +|[Driver](http://arm-software.github.io/CMSIS_5/Driver/html/index.html) | All Cortex-M, SecurCore | Generic peripheral driver interfaces for middleware. Connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces.| +|[DSP](http://arm-software.github.io/CMSIS_5/DSP/html/index.html) | All Cortex-M | DSP library collection with over 60 Functions for various data types: fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit). Implementations optimized for the SIMD instruction set are available for Cortex-M4/M7/M33/M35P.| +|[NN](http://arm-software.github.io/CMSIS_5/NN/html/index.html) | All Cortex-M | Collection of efficient neural network kernels developed to maximize the performance and minimize the memory footprint on Cortex-M processor cores.| +|[RTOS v1](http://arm-software.github.io/CMSIS_5/RTOS/html/index.html) | Cortex-M0/M0+/M3/M4/M7 | Common API for real-time operating systems along with a reference implementation based on RTX. It enables software components that can work across multiple RTOS systems.| +|[RTOS v2](http://arm-software.github.io/CMSIS_5/RTOS2/html/index.html)| All Cortex-M, Cortex-A5/A7/A9 | Extends CMSIS-RTOS v1 with Armv8-M support, dynamic object creation, provisions for multi-core systems, binary compatible interface. | +|[Pack](http://arm-software.github.io/CMSIS_5/Pack/html/index.html) | All Cortex-M, SecurCore, Cortex-A5/A7/A9 | Describes a delivery mechanism for software components, device parameters, and evaluation board support. It simplifies software re-use and product life-cycle management (PLM).
Is part of the [Open CMSIS Pack project](https://www.open-cmsis-pack.org). | +|[Build](http://arm-software.github.io/CMSIS_5/Build/html/index.html) | All Cortex-M, SecurCore, Cortex-A5/A7/A9 | A set of tools, software frameworks, and work flows that improve productivity, for example with Continuous Integration (CI) support.
Is replaced with the [CMSIS-Toolbox](https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools). | +|[SVD](http://arm-software.github.io/CMSIS_5/SVD/html/index.html) | All Cortex-M, SecurCore | Peripheral description of a device that can be used to create peripheral awareness in debuggers or CMSIS-Core header files.| +|[DAP](http://arm-software.github.io/CMSIS_5/DAP/html/index.html) | All Cortex | Firmware for a debug unit that interfaces to the CoreSight Debug Access Port. | +|[Zone](http://arm-software.github.io/CMSIS_5/Zone/html/index.html) | All Cortex-M | Defines methods to describe system resources and to partition these resources into multiple projects and execution areas. | + +## Implemented Enhancements + - CMSIS-Pack generation with [shell script template](https://arm-software.github.io/CMSIS_5/Pack/html/bash_script.html) for Windows and Linux + - CMSIS-Pack: [Git workflow](https://arm-software.github.io/CMSIS_5/Pack/html/element_repository.html) via Eclipse menu *Window - Preferences - CMSIS Packs - Manage Local Repositories* and [MDK](http://www.keil.com/support/man/docs/uv4/uv4_ca_packinst_repo.htm) + - [CMSIS-Zone release 1.0](https://arm-software.github.io/CMSIS_5/Zone/html/index.html) with support for multi-processor, TrustZone, and MPU configuration + - Support for Armv8.1M Architecture and Cortex-M55 (release in March 2020) + - CMSIS-DSP is fully ported to SIMD for Cortex-M family (Armv8.1-M) and Cortex-A & Cortex-R with NEON, using the same APIs. + +## Further Planned Enhancements + - CMSIS-Pack: + - System Description SDF Format: describe more complex debug topologies than with a Debug Description in a tool agnostic way + - CPDSC project file format: allows project templates that are agnostic of an IDE + - Minimize need for IDE specific settings: CMSIS-Pack supports IDE specific parameters. Analyze and minimize + - CMSIS-Build: command-line driven make system for CMSIS-Pack based projects (to support CI tests) + +For further details see also the [Slides of the Embedded World CMSIS Partner Meeting](https://github.com/ARM-software/CMSIS_5/blob/develop/CMSIS_Review_Meeting_2020.pdf). + +## Other related GitHub repositories + +| Repository | Description | +|:--------------------------- |:--------------------------------------------------------- | +| [cmsis-pack-eclipse](https://github.com/ARM-software/cmsis-pack-eclipse) | CMSIS-Pack Management for Eclipse reference implementation Pack support | +| [CMSIS-FreeRTOS](https://github.com/arm-software/CMSIS-FreeRTOS) | CMSIS-RTOS adoption of FreeRTOS | +| [CMSIS-Driver](https://github.com/arm-software/CMSIS-Driver) | Generic MCU driver implementations and templates for Ethernet MAC/PHY and Flash. | +| [CMSIS-Driver_Validation](https://github.com/ARM-software/CMSIS-Driver_Validation) | CMSIS-Driver Validation can be used to verify CMSIS-Driver in a user system | +| [CMSIS-Zone](https://github.com/ARM-software/CMSIS-Zone) | CMSIS-Zone Utility along with example projects and FreeMarker templates | +| [NXP_LPC](https://github.com/ARM-software/NXP_LPC) | CMSIS Driver Implementations for the NXP LPC Microcontroller Series | +| [mdk-packs](https://github.com/mdk-packs) | IoT cloud connectors as trail implementations for MDK (help us to make it generic)| +| [trustedfirmware.org](https://www.trustedfirmware.org/) | Arm Trusted Firmware provides a reference implementation of secure world software for Armv8-A and Armv8-M.| + + +## Directory Structure + +| Directory | Content | +|:-------------------- |:--------------------------------------------------------- | +| CMSIS/Core | CMSIS-Core(M) related files (for release) | +| CMSIS/Core_A | CMSIS-Core(A) related files (for release) | +| CMSIS/CoreValidation | Validation for Core(M) and Core(A) (NOT part of release) | +| CMSIS/DAP | CMSIS-DAP related files and examples | +| CMSIS/Driver | CMSIS-Driver API headers and template files | +| CMSIS/DSP | CMSIS-DSP related files | +| CMSIS/NN | CMSIS-NN related files | +| CMSIS/RTOS | RTOS v1 related files (for Cortex-M) | +| CMSIS/RTOS2 | RTOS v2 related files (for Cortex-M & Armv8-M) | +| CMSIS/Pack | CMSIS-Pack examples and tutorials | +| CMSIS/DoxyGen | Source of the documentation | +| CMSIS/Utilities | Utility programs | + +## Generate CMSIS Pack for Release + +This GitHub development repository lacks pre-built libraries of various software components (RTOS, RTOS2). +In order to generate a full pack one needs to have the build environment available to build these libraries. +This causes some sort of inconvenience. Hence the pre-built libraries may be moved out into separate pack(s) +in the future. + +To build a complete CMSIS pack for installation the following additional tools are required: + - **doxygen.exe** Version: 1.8.6 (Documentation Generator) + - **mscgen.exe** Version: 0.20 (Message Sequence Chart Converter) + - **7z.exe (7-Zip)** Version: 16.02 (File Archiver) + +Using these tools, you can generate on a Windows PC: + - **CMSIS Documentation** using the batch file **gen_doc.sh** (located in ./CMSIS/Doxygen). + - **CMSIS Software Pack** using the batch file **gen_pack.sh** (located in ./CMSIS/Utilities). + The bash script does not generate the documentation. The pre-built libraries for RTX4 and RTX5 + are not included within this repository. + +The file ./CMSIS/DoxyGen/How2Doc.txt describes the rules for creating API documentation. + +## License + +Arm CMSIS is licensed under Apache 2.0. + +## Contributions and Pull Requests + +Contributions are accepted under Apache 2.0. Only submit contributions where you have authored all of the code. + +### Issues and Labels + +Please feel free to raise an [issue on GitHub](https://github.com/ARM-software/CMSIS_5/issues) +to report misbehavior (i.e. bugs) or start discussions about enhancements. This +is your best way to interact directly with the maintenance team and the community. +We encourage you to append implementation suggestions as this helps to decrease the +workload of the very limited maintenance team. + +We will be monitoring and responding to issues as best we can. +Please attempt to avoid filing duplicates of open or closed items when possible. +In the spirit of openness we will be tagging issues with the following: + +- **bug** – We consider this issue to be a bug that will be investigated. + +- **wontfix** - We appreciate this issue but decided not to change the current behavior. + +- **enhancement** – Denotes something that will be implemented soon. + +- **future** - Denotes something not yet schedule for implementation. + +- **out-of-scope** - We consider this issue loosely related to CMSIS. It might by implemented outside of CMSIS. Let us know about your work. + +- **question** – We have further questions to this issue. Please review and provide feedback. + +- **documentation** - This issue is a documentation flaw that will be improved in future. + +- **review** - This issue is under review. Please be patient. + +- **DONE** - We consider this issue as resolved - please review and close it. In case of no further activity this issues will be closed after a week. + +- **duplicate** - This issue is already addressed elsewhere, see comment with provided references. + +- **Important Information** - We provide essential information regarding planned or resolved major enhancements. + diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/ht32f5xxxx_01.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/ht32f5xxxx_01.h new file mode 100644 index 00000000000..f72fd72a6f8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/ht32f5xxxx_01.h @@ -0,0 +1,2749 @@ +/***************************************************************************//** + * @file ht32f5xxxx_01.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File + * @version $Rev:: 7319 $ + * @date $Date:: 2023-10-28 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * Holtek supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within + * development tools that are supporting such ARM-based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F50020, HT32F50030 +// HT32F50220, HT32F50230 +// HT32F50231, HT32F50241 +// HT32F50343 +// HT32F50431, HT32F50441 +// HT32F50442, HT32F50452 +// HT32F52220, HT32F52230 +// HT32F52231, HT32F52241 +// HT32F52243, HT32F52253 +// HT32F52331, HT32F52341 +// HT32F52342, HT32F52352 +// HT32F52344, HT32F52354 +// HT32F52357, HT32F52367 +// HT32F53231, HT32F53241 +// HT32F53242, HT32F53252 +// HT32F54231, HT32F54241 +// HT32F54243, HT32F54253 +// HT32F57331, HT32F57341 +// HT32F57342, HT32F57352 +// HT32F5826, HT32F5828 +// HT32F0006 +// HT32F0008 +// HT32F61141 +// HT32F61244, HT32F61245 +// HT32F65230, HT32F65240 +// HT32F65232 +// HT32F66242, HT32F66246 +// HT32F67041, HT32F67051 +// HT32F52234, HT32F52244 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx HT32F5xxxx + * @{ + */ + + +#ifndef __HT32F5XXXX_01_H__ +#define __HT32F5XXXX_01_H__ + +#include "ht32_config.h" + +#ifdef __cplusplus + extern "C" { +#endif + +#if !defined(USE_HT32F52220_30) && \ + !defined(USE_HT32F52231_41) && \ + !defined(USE_HT32F52331_41) && \ + !defined(USE_HT32F52342_52) && \ + !defined(USE_HT32F52243_53) && \ + !defined(USE_HT32F5826) && \ + !defined(USE_HT32F0008) && \ + !defined(USE_HT32F50220_30) && \ + !defined(USE_HT32F50231_41) && \ + !defined(USE_HT32F52344_54) && \ + !defined(USE_HT32F0006) && \ + !defined(USE_HT32F52357_67) && \ + !defined(USE_HT32F65230_40) && \ + !defined(USE_HT32F54231_41) && \ + !defined(USE_HT32F54243_53) && \ + !defined(USE_HT32F57331_41) && \ + !defined(USE_HT32F57342_52) && \ + !defined(USE_HT32F50343) && \ + !defined(USE_HT32F65232) && \ + !defined(USE_HT32F61141) && \ + !defined(USE_HT32F61244_45) && \ + !defined(USE_HT32F50020_30) && \ + !defined(USE_HT32F67041_51) && \ + !defined(USE_HT32F50431_41) && \ + !defined(USE_HT32F50442_52) && \ + !defined(USE_HT32F53231_41) && \ + !defined(USE_HT32F53242_52) && \ + !defined(USE_HT32F66242) && \ + !defined(USE_HT32F66246) && \ + !defined(USE_HT32F52234_44) + + //#define USE_HT32F52220_30 + //#define USE_HT32F52231_41 + //#define USE_HT32F52331_41 + //#define USE_HT32F52342_52 + //#define USE_HT32F52243_53 + //#define USE_HT32F5826 + //#define USE_HT32F0008 + //#define USE_HT32F50220_30 + //#define USE_HT32F50231_41 + //#define USE_HT32F52344_54 + //#define USE_HT32F0006 + //#define USE_HT32F52357_67 + //#define USE_HT32F65230_40 + //#define USE_HT32F54231_41 + //#define USE_HT32F54243_53 + //#define USE_HT32F57331_41 + //#define USE_HT32F57342_52 + //#define USE_HT32F50343 + //#define USE_HT32F65232 + //#define USE_HT32F61141 + //#define USE_HT32F61244_45 + //#define USE_HT32F50020_30 + //#define USE_HT32F67041_51 + //#define USE_HT32F50431_41 + //#define USE_HT32F50442_52 + //#define USE_HT32F53231_41 + //#define USE_HT32F53242_52 + //#define USE_HT32F66242 + //#define USE_HT32F66246 + //#define USE_HT32F52234_44 + +#endif + +#if !defined(USE_NOCHIP) && \ + !defined(USE_HT32F52220_30) && \ + !defined(USE_HT32F52231_41) && \ + !defined(USE_HT32F52331_41) && \ + !defined(USE_HT32F52342_52) && \ + !defined(USE_HT32F52243_53) && \ + !defined(USE_HT32F5826) && \ + !defined(USE_HT32F0008) && \ + !defined(USE_HT32F50220_30) && \ + !defined(USE_HT32F50231_41) && \ + !defined(USE_HT32F52344_54) && \ + !defined(USE_HT32F0006) && \ + !defined(USE_HT32F52357_67) && \ + !defined(USE_HT32F65230_40) && \ + !defined(USE_HT32F54231_41) && \ + !defined(USE_HT32F54243_53) && \ + !defined(USE_HT32F57331_41) && \ + !defined(USE_HT32F57342_52) && \ + !defined(USE_HT32F50343) && \ + !defined(USE_HT32F65232) && \ + !defined(USE_HT32F61141) && \ + !defined(USE_HT32F61244_45) && \ + !defined(USE_HT32F50020_30) && \ + !defined(USE_HT32F67041_51) && \ + !defined(USE_HT32F50431_41) && \ + !defined(USE_HT32F50442_52) && \ + !defined(USE_HT32F53231_41) && \ + !defined(USE_HT32F53242_52) && \ + !defined(USE_HT32F66242) && \ + !defined(USE_HT32F66246) && \ + !defined(USE_HT32F52234_44) + + #error Please add "USE_HT32Fxxxxx_xx" define into C Preprocessor Symbols of the Project configuration. + +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ +/** + * @brief Value of the High Speed Internal oscillator in Hz + */ +#if defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) + #define HSI_VALUE 20000000UL /*!< Value of the Internal High Speed oscillator in Hz */ +#elif defined(USE_HT32F50020_30) + #define HSI_VALUE 16000000UL /*!< Value of the Internal High Speed oscillator in Hz */ +#else + #define HSI_VALUE 8000000UL /*!< Value of the High Speed Internal oscillator in Hz */ +#endif + +/** + * @brief Value of the Low Speed Internal oscillator in Hz + */ +#define LSI_VALUE 32000UL /*!< Value of the Low Speed Internal oscillator in Hz */ + +#if !defined(USE_HT32F52220_30) && !defined(USE_HT32F66242) && !defined(USE_HT32F66246) +/** + * @brief Value of the Low Speed External oscillator in Hz + */ +#define LSE_VALUE 32768UL /*!< Value of the Low Speed External oscillator in Hz */ +#endif + +/** + * @brief Adjust the High Speed External oscillator (HSE) Startup Timeout value + */ +#define HSE_READY_TIME ((uint16_t)0xFFFF) /*!< Time out for HSE start up */ +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + + +/** @addtogroup Configuration_for_Interrupt_Number + * @{ + */ +typedef enum IRQn +{ +/****** Cortex-M0+ Processor Exceptions Numbers ******************************** */ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ + +/****** HT32 Specific Interrupt Numbers *************************************** */ + LVD_BOD_IRQn = 0, /*!< Low voltage & Brown-out detection interrupt */ + #if !defined(USE_HT32F52220_30) + RTC_IRQn = 1, /*!< RTC Wake-up Interrupt */ + #endif + FLASH_IRQn = 2, /*!< FLASH global Interrupt */ + EVWUP_IRQn = 3, /*!< EXTI Event Wake-up & WAKEUP pin Interrupt */ + EXTI0_1_IRQn = 4, /*!< EXTI0-1 Line detection Interrupt */ + EXTI2_3_IRQn = 5, /*!< EXTI2-3 Line detection Interrupt */ + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) + EXTI4_9_IRQn = 6, /*!< EXTI4-9 Line detection Interrupt */ + #elif defined(USE_HT32F50020_30) + EXTI4_7_IRQn = 6, /*!< EXTI4-7 Line detection Interrupt */ + #else + EXTI4_15_IRQn = 6, /*!< EXTI4-15 Line detection Interrupt */ + #endif + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined(USE_HT32F66246) + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) + EXTI10_15_IRQn = 7, /*!< EXTI10-15 Line detection Interrupt */ + #elif defined(USE_HT32F66246) + CAN0_IRQn = 7, /*!< CAN0 global Interrupt */ + #endif + ADC0_IRQn = 8, /*!< ADC0 Interrupt */ + #if defined(USE_HT32F65230_40) + ADC1_IRQn = 9, /*!< ADC1 Interrupt */ + #elif defined(USE_HT32F66242) + CORDIC_IRQn = 9, /*!< CORDIC global Interrupt */ + #elif defined(USE_HT32F66246) + CORDIC_IRQn = 9, /*!< CORDIC global Interrupt */ + #endif + MCTM0_BRK_IRQn = 10, /*!< MCTM BRK Interrupt */ + MCTM0_UP_IRQn = 11, /*!< MCTM UP Interrupt */ + MCTM0_TR_UP2_IRQn = 12, /*!< MCTM TR & UP2 Interrupt */ + MCTM0_CC_IRQn = 13, /*!< MCTM CC Interrupt */ + GPTM0_G_IRQn = 14, /*!< GPTM G Interrupt */ + GPTM0_VCLK_IRQn = 15, /*!< GPTM VCLK Interrupt */ + BFTM0_IRQn = 16, /*!< Basic Function Timer0 Interrupt */ + BFTM1_IRQn = 17, /*!< Basic Function Timer1 Interrupt */ + CMP0_IRQn = 18, /*!< Comparator0 Interrupt */ + CMP1_IRQn = 19, /*!< Comparator1 Interrupt */ + #if defined(USE_HT32F65230_40) + CMP2_IRQn = 20, /*!< Comparator2 Interrupt */ + #elif defined(USE_HT32F66242) + PID_IRQn = 20, /*!< PID global Interrupt */ + #elif defined(USE_HT32F66246) + PID_IRQn = 20, /*!< PID global Interrupt */ + #endif + I2C0_IRQn = 21, /*!< I2C global Interrupt */ + SPI0_IRQn = 22, /*!< SPI global Interrupt */ + USART0_IRQn = 23, /*!< USART global Interrupt */ + UART0_IRQn = 24, /*!< UART global Interrupt */ + PDMACH0_1_IRQn = 25, /*!< PDMA channel 0-1 Interrupt */ + PDMACH2_3_IRQn = 26, /*!< PDMA channel 2-3 Interrupt */ + PDMACH4_5_IRQn = 27, /*!< PDMA channel 4-5 Interrupt */ + SCTM0_IRQn = 28, /*!< Single Channel Timer0 Interrupt */ + SCTM1_IRQn = 29, /*!< Single Channel Timer1 Interrupt */ + SCTM2_IRQn = 30, /*!< Single Channel Timer2 Interrupt */ + SCTM3_IRQn = 31, /*!< Single Channel Timer3 Interrupt */ + #else + #if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F52344_54) || defined(USE_HT32F54243_53) || defined(USE_HT32F53242_52) || defined(USE_HT32F50442_52) + COMP_IRQn = 7, /*!< Comparator global Interrupt */ + #endif + #if defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) + COMP_DAC_IRQn = 7, /*!< Comparator & DAC global Interrupt */ + #endif + #if defined(USE_HT32F52234_44) + DAC0_1_IRQn = 7, /*!< DAC0 & DAC1 global Interrupt */ + #endif + #if !defined(USE_HT32F0008) + ADC0_IRQn = 8, /*!< ADC Interrupt */ + #endif + #if defined(USE_HT32F52243_53) || defined(USE_HT32F54243_53) || defined(USE_HT32F52234_44) + I2C2_IRQn = 9, /*!< I2C2 global Interrupt */ + #endif + #if defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F67041_51) + AES_IRQn = 9, /*!< AES global Interrupt */ + #endif + #if !defined(USE_HT32F52220_30) && !defined(USE_HT32F0008) && !defined(USE_HT32F50220_30) && !defined(USE_HT32F0006) && !defined(USE_HT32F57342_52) && !defined(USE_HT32F57331_41) && !defined(USE_HT32F50343) && !defined(USE_HT32F61244_45) && !defined(USE_HT32F50020_30) && !defined(USE_HT32F67041_51) && !defined(USE_HT32F52234_44) + MCTM0_IRQn = 10, /*!< Motor Control Timer0 interrupt */ + #endif + #if defined(USE_HT32F50343) + PWM2_IRQn = 10, /*!< PWM Timer2 interrupt */ + #endif + #if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) + GPTM1_IRQn = 11, /*!< General-Purpose Timer1 Interrupt */ + #endif + #if defined(USE_HT32F52357_67) + QSPI_IRQn = 11, /*!< QSPI global Interrupt */ + #endif + #if defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) + LCD_IRQn = 11, /*!< LCD global Interrupt */ + #endif + #if defined(USE_HT32F54231_41) || defined(USE_HT32F54243_53) + TKEY_IRQn = 11, /*!< Touch-Key global Interrupt */ + #endif + #if defined(USE_HT32F67041_51) + RF_IRQn = 11, /*!< 2.4G RF global Interrupt */ + #endif + #if !defined(USE_HT32F50020_30) && !defined(USE_HT32F52234_44) + GPTM0_IRQn = 12, /*!< General-Purpose Timer0 Interrupt */ + #endif + #if !defined(USE_HT32F0008) && !defined(USE_HT32F50220_30) && !defined(USE_HT32F50231_41) && !defined(USE_HT32F57331_41) && !defined(USE_HT32F53231_41) && !defined(USE_HT32F53242_52) && !defined(USE_HT32F50431_41) && !defined(USE_HT32F50442_52) + SCTM0_IRQn = 13, /*!< Single Channel Timer0 Interrupt */ + SCTM1_IRQn = 14, /*!< Single Channel Timer1 Interrupt */ + #endif + #if defined(USE_HT32F52231_41) || defined(USE_HT32F52331_41) || defined(USE_HT32F52243_53) || defined(USE_HT32F0006) || defined(USE_HT32F54243_53) || defined(USE_HT32F50020_30) || defined(USE_HT32F67041_51) + SCTM2_IRQn = 15, /*!< Single Channel Timer2 Interrupt */ + #endif + #if defined(USE_HT32F52231_41) || defined(USE_HT32F52331_41) || defined(USE_HT32F52243_53) || defined(USE_HT32F0006) || defined(USE_HT32F54243_53) || defined(USE_HT32F67041_51) + SCTM3_IRQn = 16, /*!< Single Channel Timer3 Interrupt */ + #endif + #if defined(USE_HT32F0008) || defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F50343) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) || defined(USE_HT32F52234_44) + PWM0_IRQn = 15, /*!< PWM Timer0 Interrupt */ + #endif + #if defined(USE_HT32F0008) || defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F50343) || defined(USE_HT32F53242_52) || defined(USE_HT32F50442_52) + PWM1_IRQn = 16, /*!< PWM Timer1 Interrupt */ + #endif + BFTM0_IRQn = 17, /*!< Basic Function Timer0 Interrupt */ + #if !defined(USE_HT32F52220_30) && !defined(USE_HT32F50220_30) && !defined(USE_HT32F50020_30) + BFTM1_IRQn = 18, /*!< Basic Function Timer1 Interrupt */ + #endif + I2C0_IRQn = 19, /*!< I2C0 global Interrupt */ + #if !defined(USE_HT32F52220_30) && !defined(USE_HT32F0008) && !defined(USE_HT32F50220_30) && !defined(USE_HT32F52344_54) && !defined(USE_HT32F0006) && !defined(USE_HT32F61244_45) && !defined(USE_HT32F50020_30) + I2C1_IRQn = 20, /*!< I2C1 global Interrupt */ + #endif + SPI0_IRQn = 21, /*!< SPI0 global Interrupt */ + #if !defined(USE_HT32F52220_30) && !defined(USE_HT32F0008) && !defined(USE_HT32F0006) && !defined(USE_HT32F50020_30) && !defined(USE_HT32F61244_45) && !defined(USE_HT32F52234_44) + SPI1_IRQn = 22, /*!< SPI1 global Interrupt */ + #endif + #if defined(USE_HT32F0006) || defined(USE_HT32F61244_45) + QSPI_IRQn = 22, /*!< QSPI global Interrupt */ + #endif + #if !defined(USE_HT32F50220_30) && !defined(USE_HT32F52344_54) && !defined(USE_HT32F50343) && !defined(USE_HT32F61244_45) && !defined(USE_HT32F50020_30) && !defined(USE_HT32F67041_51) + USART0_IRQn = 23, /*!< USART0 global Interrupt */ + #endif + #if defined(USE_HT32F52342_52) || defined(USE_HT32F52243_53) || defined(USE_HT32F5826) || defined(USE_HT32F52357_67) || defined(USE_HT32F54243_53) || defined(USE_HT32F53242_52) || defined(USE_HT32F50442_52) + USART1_IRQn = 24, /*!< USART1 global Interrupt */ + #endif + UART0_IRQn = 25, /*!< UART0 global Interrupt */ + #if !defined(USE_HT32F52220_30) && !defined(USE_HT32F0008) && !defined(USE_HT32F0006) && !defined(USE_HT32F61244_45) && !defined(USE_HT32F52234_44) + UART1_IRQn = 26, /*!< UART1 global Interrupt */ + #endif + #if defined(USE_HT32F52357_67) + UART0_UART2_IRQn = 25, /*!< UART0 & UART2 global Interrupt */ + UART1_UART3_IRQn = 26, /*!< UART1 & UART3 global Interrupt */ + #endif + #if defined(USE_HT32F52331_41) || defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F61141) + SCI_IRQn = 27, /*!< Smart Card Interface Interrupt */ + #endif + #if defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) + CAN0_IRQn = 27, /*!< CAN0 global Interrupt */ + #endif + #if defined(USE_HT32F0006) || defined(USE_HT32F61244_45) + MIDI_IRQn = 27, /*!< MIDI global Interrupt */ + #endif + #if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) + I2S_IRQn = 28, /*!< I2S global Interrupt */ + #endif + #if defined(USE_HT32F52243_53) || defined(USE_HT32F54243_53) + UART2_IRQn = 27, /*!< UART2 global Interrupt */ + UART3_IRQn = 28, /*!< UART3 global Interrupt */ + #endif + #if defined(USE_HT32F0008) + AES_IRQn = 28, /*!< AES global Interrupt */ + #endif + #if defined(USE_HT32F50343) + SLED0_IRQn = 27, /*!< SLED0 global Interrupt */ + SLED1_IRQn = 28, /*!< SLED1 global Interrupt */ + #endif + #if defined(USE_HT32F52331_41) || defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F0008) || defined(USE_HT32F52344_54) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F50343) || defined(USE_HT32F61141) + USB_IRQn = 29, /*!< USB interrupt */ + #endif + #if defined(USE_HT32F54231_41) || defined(USE_HT32F54243_53) || defined(USE_HT32F50020_30) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) + LEDC_IRQn = 29, /*!< LEDC global Interrupt */ + #endif + #if defined(USE_HT32F52342_52) || defined(USE_HT32F52243_53) || defined(USE_HT32F5826) || defined(USE_HT32F0008) || defined(USE_HT32F52344_54) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F50343) || defined(USE_HT32F54243_53) || defined(USE_HT32F61244_45) || defined(USE_HT32F67041_51) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) || defined(USE_HT32F52234_44) + PDMACH0_1_IRQn = 30, /*!< PDMA channel 0-1 interrupt */ + PDMACH2_5_IRQn = 31, /*!< PDMA channel 2-5 interrupt */ + #endif + #endif +} IRQn_Type; + +#define EXTI0_IRQn EXTI0_1_IRQn +#define EXTI1_IRQn EXTI0_1_IRQn +#define EXTI2_IRQn EXTI2_3_IRQn +#define EXTI3_IRQn EXTI2_3_IRQn +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) +#define EXTI4_IRQn EXTI4_9_IRQn +#define EXTI5_IRQn EXTI4_9_IRQn +#define EXTI6_IRQn EXTI4_9_IRQn +#define EXTI7_IRQn EXTI4_9_IRQn +#define EXTI8_IRQn EXTI4_9_IRQn +#define EXTI9_IRQn EXTI4_9_IRQn +#define EXTI10_IRQn EXTI10_15_IRQn +#define EXTI11_IRQn EXTI10_15_IRQn +#define EXTI12_IRQn EXTI10_15_IRQn +#define EXTI13_IRQn EXTI10_15_IRQn +#define EXTI14_IRQn EXTI10_15_IRQn +#define EXTI15_IRQn EXTI10_15_IRQn +#elif defined(USE_HT32F50020_30) +#define EXTI4_IRQn EXTI4_7_IRQn +#define EXTI5_IRQn EXTI4_7_IRQn +#define EXTI6_IRQn EXTI4_7_IRQn +#define EXTI7_IRQn EXTI4_7_IRQn +#else +#define EXTI4_IRQn EXTI4_15_IRQn +#define EXTI5_IRQn EXTI4_15_IRQn +#define EXTI6_IRQn EXTI4_15_IRQn +#define EXTI7_IRQn EXTI4_15_IRQn +#define EXTI8_IRQn EXTI4_15_IRQn +#define EXTI9_IRQn EXTI4_15_IRQn +#define EXTI10_IRQn EXTI4_15_IRQn +#define EXTI11_IRQn EXTI4_15_IRQn +#define EXTI12_IRQn EXTI4_15_IRQn +#define EXTI13_IRQn EXTI4_15_IRQn +#define EXTI14_IRQn EXTI4_15_IRQn +#define EXTI15_IRQn EXTI4_15_IRQn +#endif + +#define PDMACH0_IRQn PDMACH0_1_IRQn +#define PDMACH1_IRQn PDMACH0_1_IRQn +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined(USE_HT32F66246) +#define PDMACH2_IRQn PDMACH2_3_IRQn +#define PDMACH3_IRQn PDMACH2_3_IRQn +#define PDMACH4_IRQn PDMACH4_5_IRQn +#define PDMACH5_IRQn PDMACH4_5_IRQn +#else +#define PDMACH2_IRQn PDMACH2_5_IRQn +#define PDMACH3_IRQn PDMACH2_5_IRQn +#define PDMACH4_IRQn PDMACH2_5_IRQn +#define PDMACH5_IRQn PDMACH2_5_IRQn +#endif + + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_ht32f5xxxx_01.h" /* HT32 system */ + + +/** @addtogroup Exported_Types + * @{ + */ + +typedef signed long long s64; +typedef signed int s32; +typedef signed short s16; +typedef signed char s8; + +typedef const s64 sc64; /*!< Read Only */ +typedef const s32 sc32; /*!< Read Only */ +typedef const s16 sc16; /*!< Read Only */ +typedef const s8 sc8; /*!< Read Only */ + +typedef __IO s64 vs64; +typedef __IO s32 vs32; +typedef __IO s16 vs16; +typedef __IO s8 vs8; + +typedef __I s64 vsc64; /*!< Read Only */ +typedef __I s32 vsc32; /*!< Read Only */ +typedef __I s16 vsc16; /*!< Read Only */ +typedef __I s8 vsc8; /*!< Read Only */ + +typedef unsigned long long u64; +typedef unsigned int u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef const u64 uc64; /*!< Read Only */ +typedef const u32 uc32; /*!< Read Only */ +typedef const u16 uc16; /*!< Read Only */ +typedef const u8 uc8; /*!< Read Only */ + +typedef __IO u64 vu64; +typedef __IO u32 vu32; +typedef __IO u16 vu16; +typedef __IO u8 vu8; + +typedef __I u64 vuc64; /*!< Read Only */ +typedef __I u32 vuc32; /*!< Read Only */ +typedef __I u16 vuc16; /*!< Read Only */ +typedef __I u8 vuc8; /*!< Read Only */ + + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; + +#if !defined(bool) && !defined(__cplusplus) // user may already included or CPP +typedef enum {FALSE = 0, TRUE = !FALSE} bool; +#define false FALSE +#define true TRUE +#else +#define FALSE 0 +#define TRUE 1 +#endif + +typedef enum {RESET = 0, SET = !RESET} FlagStatus; + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + +/** + * @} + */ + +#if defined (__CC_ARM) + #define __ALIGN4 __align(4) +#elif defined (__ICCARM__) + #define __ALIGN4 _Pragma("data_alignment = 4") +#elif defined (__GNUC__) + #define __ALIGN4 __attribute__((aligned(4))) +#endif + +#if defined (__GNUC__) + #define __PACKED_H + #define __PACKED_F __attribute__ ((packed)) +#elif defined (__ICCARM__) || (__CC_ARM) + #define __PACKED_H __packed + #define __PACKED_F +#endif + +#if defined (__CC_ARM) +#pragma anon_unions +#endif + + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648) + + +/** + * @brief Exported constants and macro + */ +#define IS_CONTROL_STATUS(STATUS) ((STATUS == DISABLE) || (STATUS == ENABLE)) + +#define wb(addr, value) (*((u8 volatile *) (addr)) = value) +#define rb(addr) (*((u8 volatile *) (addr))) +#define whw(addr, value) (*((u16 volatile *) (addr)) = value) +#define rhw(addr) (*((u16 volatile *) (addr))) +#define ww(addr, value) (*((u32 volatile *) (addr)) = value) +#define rw(addr) (*((u32 volatile *) (addr))) + + +#define ResetBit_BB(Addr, BitNumber) (rw(Addr) &= ~(1UL << BitNumber)) +#define SetBit_BB(Addr, BitNumber) (rw(Addr) |= (1UL << BitNumber)) +#define GetBit_BB(Addr, BitNumber) ((rw(Addr) >> BitNumber) & 1UL) +#define WriteBit_BB(Addr, BitNumber, Value) (Addr = ((Addr & ~((u32)1 << BitNumber)) | ((u32)Value << BitNumber))) + +#define STRCAT2_(a, b) a##b +#define STRCAT2(a, b) STRCAT2_(a, b) +#define STRCAT3_(a, b, c) a##b##c +#define STRCAT3(a, b, c) STRCAT3_(a, b, c) + +#define IPN_NULL (0) +#define IPN_MCTM0 (0x4002C000) +#define IPN_MCTM1 (0x4002D000) +#define IPN_GPTM0 (0x4006E000) +#define IPN_GPTM1 (0x4006F000) +#define IPN_SCTM0 (0x40034000) +#define IPN_SCTM1 (0x40074000) +#define IPN_SCTM2 (0x40035000) +#define IPN_SCTM3 (0x40075000) +#define IPN_PWM0 (0x40031000) +#define IPN_PWM1 (0x40071000) +#define IPN_PWM2 (0x40031000) +#define IPN_BFTM0 (0x40076000) +#define IPN_BFTM1 (0x40077000) +#define IPN_CHECK(IP) STRCAT2(IPN_, IP) +#define IS_IPN_BFTM(IP) (IPN_CHECK(IP) == IPN_BFTM0) || (IPN_CHECK(IP) == IPN_BFTM1) +#define IS_IPN_MCTM(IP) (IPN_CHECK(IP) == IPN_MCTM0) || (IPN_CHECK(IP) == IPN_MCTM1) +#define IS_IPN_GPTM(IP) (IPN_CHECK(IP) == IPN_GPTM0) || (IPN_CHECK(IP) == IPN_GPTM1) +#define IS_IPN_SCTM(IP) (IPN_CHECK(IP) == IPN_SCTM0) || (IPN_CHECK(IP) == IPN_SCTM1) || (IPN_CHECK(IP) == IPN_SCTM2) || (IPN_CHECK(IP) == IPN_SCTM3) +#define IS_IPN_PWM(IP) (IPN_CHECK(IP) == IPN_PWM0) || (IPN_CHECK(IP) == IPN_PWM1) || (IPN_CHECK(IP) == IPN_PWM2) +#define IS_IPN_TM(IP) (IS_IPN_MCTM(IP) || IS_IPN_GPTM(IP) || IS_IPN_SCTM(IP) || IS_IPN_PWM(IP)) + + +/** @addtogroup Peripheral_Registers_Structures + * @{ + */ + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + /* USART0: 0x40000000 */ + /* USART1: 0x40040000 */ + /* UART0: 0x40001000 */ + /* UART2: 0x40002000 */ + /* UART1: 0x40041000 */ + /* UART3: 0x40042000 */ + __IO uint32_t DR; /*!< 0x000 Data Register */ + __IO uint32_t CR; /*!< 0x004 Control Register */ + __IO uint32_t FCR; /*!< 0x008 FIFO Control Register */ + __IO uint32_t IER; /*!< 0x00C Interrupt Enable Register */ + __IO uint32_t SR; /*!< 0x010 Status Register */ + __IO uint32_t TPR; /*!< 0x014 Timing Parameter Register */ + __IO uint32_t ICR; /*!< 0x018 IrDA COntrol Register */ + __IO uint32_t RCR; /*!< 0x01C RS485 Control Register */ + __IO uint32_t SCR; /*!< 0x020 Synchronous Control Register */ + __IO uint32_t DLR; /*!< 0x024 Divisor Latch Register */ + __IO uint32_t DTR; /*!< 0x028 Debug/Test Register */ +} HT_USART_TypeDef; + + +/** + * @brief SPI + */ +typedef struct +{ + /* SPI0: 0x40004000 */ + /* SPI1: 0x40044000 */ + __IO uint32_t CR0; /*!< 0x000 Control Register 0 */ + __IO uint32_t CR1; /*!< 0x004 Control Register 1 */ + __IO uint32_t IER; /*!< 0x008 Interrupt Enable Register */ + __IO uint32_t CPR; /*!< 0x00C Clock Prescaler Register */ + __IO uint32_t DR; /*!< 0x010 Data Register */ + __IO uint32_t SR; /*!< 0x014 Status Register */ + __IO uint32_t FCR; /*!< 0x018 FIFO Control Register */ + __IO uint32_t FSR; /*!< 0x01C FIFO Status Register */ + __IO uint32_t FTOCR; /*!< 0x020 FIFO Time Out Counter Register */ +#if defined(USE_HT32F0006) || defined(USE_HT32F61244_45) + __IO uint32_t MIDICR0; /*!< 0x040 MIDI Control Register 0 */ + __IO uint32_t MIDICR1; /*!< 0x044 MIDI Control Register 1 */ +#endif +} HT_SPI_TypeDef; + + +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined(USE_HT32F66246) +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + /* ADC0: 0x40010000 */ + /* ADC1: 0x40050000 */ + __IO uint32_t CFGR; /*!< 0x000 ADC Configuration Register (ADC1 only) */ + __IO uint32_t RST; /*!< 0x004 ADC Reset Register */ + __IO uint32_t CONV; /*!< 0x008 ADC Regular Conversion Mode Register */ + __IO uint32_t HCONV; /*!< 0x00C ADC High-priority Conversion Mode Register */ + __IO uint32_t LST[2]; /*!< 0x010 - 0x014 ADC Conversion List Register */ + uint32_t RESERVE0[2]; /*!< 0x018 - 0x01C Reserved */ + __IO uint32_t HLST; /*!< 0x020 ADC High-priority Conversion List Register */ + uint32_t RESERVE1[3]; /*!< 0x024 - 0x02C Reserved */ + #if defined(USE_HT32F65230_40) + __IO uint32_t OFR[12]; /*!< 0x030 - 0x05C ADC Input Offset Register 0-11 */ + uint32_t RESERVE2[4]; /*!< 0x060 - 0x06C Reserved */ + __IO uint32_t STR[12]; /*!< 0x070 - 0x08C ADC Input Sampling Time Register 0-11 */ + uint32_t RESERVE3[4]; /*!< 0x090 - 0x0AC Reserved */ + #endif + #if defined(USE_HT32F65232) + __IO uint32_t OFR[15]; /*!< 0x030 - 0x068 ADC Input Offset Register 0-14 */ + uint32_t RESERVE2[1]; /*!< 0x06C Reserved */ + __IO uint32_t STR[15]; /*!< 0x070 - 0x0A8 ADC Input Sampling Time Register 0-14 */ + uint32_t RESERVE3[1]; /*!< 0x0AC Reserved */ + #endif + #if defined(USE_HT32F66242) + uint32_t RESERVE2[16]; /*!< 0x030 - 0x06C Reserved */ + __IO uint32_t STR[16]; /*!< 0x070 - 0x0AC ADC Input Sampling Time Register 0-15 */ + #endif + #if defined(USE_HT32F66246) + uint32_t RESERVE2[16]; /*!< 0x030 - 0x06C Reserved */ + __IO uint32_t STR[16]; /*!< 0x070 - 0x0AC ADC Input Sampling Time Register 0-15 */ + #endif + __IO uint32_t DR[8]; /*!< 0x0B0 - 0x0CC ADC Regular Conversion Data Register 0-7 */ + uint32_t RESERVE4[8]; /*!< 0x0D0 - 0x0EC Reserved */ + __IO uint32_t HDR[4]; /*!< 0x0F0 - 0x0FC ADC High-priority Conversion Data Register 0-3 */ + __IO uint32_t TCR; /*!< 0x100 ADC Trigger Control Register */ + __IO uint32_t TSR; /*!< 0x104 ADC Trigger Source Register */ + uint32_t RESERVE5[2]; /*!< 0x108 - 0x10C Reserved */ + __IO uint32_t HTCR; /*!< 0x110 ADC High-priority Trigger Control Register */ + __IO uint32_t HTSR; /*!< 0x114 ADC High-priority Trigger Source Register */ + uint32_t RESERVE6[2]; /*!< 0x118 - 0x11C Reserved */ + __IO uint32_t WCR; /*!< 0x120 ADC Watchdog Control Register */ + __IO uint32_t LTR; /*!< 0x124 ADC Watchdog Threshold Register */ + __IO uint32_t UTR; /*!< 0x128 ADC Watchdog Threshold Register */ + uint32_t RESERVE7[1]; /*!< 0x12C Reserved */ + __IO uint32_t IER; /*!< 0x130 ADC Interrupt Enable Register */ + __IO uint32_t IRAW; /*!< 0x134 ADC Interrupt Raw Status Register */ + __IO uint32_t ISR; /*!< 0x138 ADC Interrupt Status Register */ + __IO uint32_t ICLR; /*!< 0x13C ADC Interrupt Clear Register */ + __IO uint32_t PDMAR; /*!< 0x140 ADC PDMA Request Register */ + #if defined(USE_HT32F65230_40) + uint32_t RESERVE8[3]; /*!< 0x144 - 0x14C Reserved */ + __IO uint32_t DIESR; /*!< 0x150 Dual ADC Interrupt Enable/Status Register (ADC1 only) */ + __IO uint32_t DPDMAR; /*!< 0x154 Dual ADC PDMA Request Register (ADC1 only) */ + #endif + #if defined(USE_HT32F66242) + uint32_t RESERVE8[3]; /*!< 0x144 - 0x14C Reserved */ + __IO uint32_t VREFCR; /*!< 0x150 ADC Reference Voltage Control Register */ + uint32_t RESERVE9[3]; /*!< 0x154 - 0x15C Reserved */ + __IO uint32_t HDR4[8]; /*!< 0x160 - 0x17C ADC High-priority Conversion Data Register 4-11 */ + uint32_t RESERVE10[4]; /*!< 0x180 - 0x18C Reserved */ + __IO uint32_t STR16[2]; /*!< 0x190 - 0x194 ADC Input Sampling Time Register 16-17 */ + #endif + #if defined(USE_HT32F66246) + uint32_t RESERVE8[3]; /*!< 0x144 - 0x14C Reserved */ + __IO uint32_t VREFCR; /*!< 0x150 ADC Reference Voltage Control Register */ + uint32_t RESERVE9[3]; /*!< 0x154 - 0x15C Reserved */ + __IO uint32_t HDR4[8]; /*!< 0x160 - 0x17C ADC High-priority Conversion Data Register 4-11 */ + uint32_t RESERVE10[4]; /*!< 0x180 - 0x18C Reserved */ + __IO uint32_t STR16[2]; /*!< 0x190 - 0x194 ADC Input Sampling Time Register 16-17 */ + #endif +} HT_ADC_TypeDef; +#else +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + /* ADC: 0x40010000 */ + __IO uint32_t CR; /*!< 0x000 ADC Conversion Control Register */ + #if defined(USE_HT32F50020_30) + __IO uint32_t LST[1]; /*!< 0x004 ADC Conversion List Register 0 */ + uint32_t RESERVE0[6]; /*!< 0x008 - 0x01C Reserved */ + #else + __IO uint32_t LST[2]; /*!< 0x004 - 0x008 ADC Conversion List Register 0-1 */ + uint32_t RESERVE0[5]; /*!< 0x00C - 0x01C Reserved */ + #endif + __IO uint32_t STR; /*!< 0x020 ADC Input Sampling Time Register */ + uint32_t RESERVE1[3]; /*!< 0x024 - 0x02C Reserved */ + #if defined(USE_HT32F50020_30) + __IO uint32_t DR[4]; /*!< 0x030 - 0x03C ADC Conversion Data Register 0-3 */ + uint32_t RESERVE2[13]; /*!< 0x040 - 0x070 Reserved */ + #else + __IO uint32_t DR[8]; /*!< 0x030 - 0x04C ADC Conversion Data Register 0-7 */ + uint32_t RESERVE2[8]; /*!< 0x050 - 0x06C Reserved */ + __IO uint32_t TCR; /*!< 0x070 ADC Trigger Control Register */ + #endif + __IO uint32_t TSR; /*!< 0x074 ADC Trigger Source Register */ + #if defined(USE_HT32F50020_30) + __IO uint32_t RESERVE3[2]; /*!< 0x078 - 0x07C Reserved */ + #else + __IO uint32_t WCR; /*!< 0x078 ADC Watchdog Control Register */ + __IO uint32_t WTR; /*!< 0x07C ADC Watchdog Threshold Register */ + #endif + __IO uint32_t IER; /*!< 0x080 ADC Interrupt Enable Register */ + __IO uint32_t IRAW; /*!< 0x084 ADC Interrupt Raw Status Register */ + __IO uint32_t ISR; /*!< 0x088 ADC Interrupt Status Register */ + __IO uint32_t ICLR; /*!< 0x08C ADC Interrupt Clear Register */ + #if defined(USE_HT32F52342_52) || defined(USE_HT32F52243_53) || defined(USE_HT32F5826) || defined(USE_HT32F52344_54) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F50343) || defined(USE_HT32F54243_53) || defined(USE_HT32F61244_45) || defined(USE_HT32F67041_51) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) || defined(USE_HT32F52234_44) + __IO uint32_t PDMAR; /*!< 0x090 ADC PDMA Request Register */ + #else + uint32_t RESERVE4; /*!< 0x090 Reserved */ + #endif + #if defined(USE_HT32F52344_54) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F50343) || defined(USE_HT32F54231_41) || defined(USE_HT32F54243_53) || defined(USE_HT32F67041_51) || defined(USE_HT32F50020_30) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) || defined(USE_HT32F52234_44) + uint32_t RESERVE5[3]; /*!< 0x094 - 0x09C Reserved */ + __IO uint32_t VREFCR; /*!< 0x0A0 ADC Reference Voltage Control Register */ + __IO uint32_t VREFVALR; /*!< 0x0A4 ADC Reference Voltage Value Register */ + #endif +} HT_ADC_TypeDef; +#endif + + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + /* DACDUAL16: 0x40054000 */ + __IO uint32_t CR; /*!< 0x000 D/A Converter Control Register */ + __IO uint32_t RH; /*!< 0x004 D/A R-channel data register */ + __IO uint32_t LH; /*!< 0x008 D/A L-channel data register */ + __IO uint32_t TG; /*!< 0x00c D/A data trigger Register */ +} HT_DAC_DUAL16_TypeDef; + +/** + * @brief Digital to Analog Converter Channel + */ +typedef struct +{ + __IO uint32_t CR; /*!< 0x000 DAC Channel Control Register */ + uint32_t RESERVE0[2]; /*!< 0x004 - 0x008 Reserved */ + __IO uint32_t DHR; /*!< 0x00C DAC Channel Data Holding Register */ + __IO uint32_t DOR; /*!< 0x010 DAC Channel Data Output Register */ + uint32_t RESERVE1[3]; /*!< 0x014 - 0x01C Reserved */ +} HT_DACCH_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + /* DAC1: 0x40014000 */ + /* DAC0: 0x40054000 */ + __IO uint32_t CFGR; /*!< 0x000 DAC Configuration Register */ + uint32_t RESERVE0[3]; /*!< 0x004 - 0x00C Reserved */ + HT_DACCH_TypeDef DACCH0; /*!< 0x010 DAC channel 0 registers */ + HT_DACCH_TypeDef DACCH1; /*!< 0x030 DAC channel 1 registers */ +} HT_DAC_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + /* CMP0: 0x40058000 */ + /* CMP1: 0x40058100 */ + /* CMP2: 0x40058200 */ + __IO uint32_t CR; /*!< 0x000 Comparator Control Register */ + __IO uint32_t VALR; /*!< 0x004 Comparator Voltage Reference Value Register */ + __IO uint32_t IER; /*!< 0x008 Comparator Interrupt Enable Register */ + __IO uint32_t TFR; /*!< 0x00C Comparator Transition Flag Register */ + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined(USE_HT32F66246) + __IO uint32_t CI; /*!< 0x010 Comparator Input Control Register */ + #endif + #if defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined(USE_HT32F66246) + __IO uint32_t CO; /*!< 0x014 Comparator Output Control Register */ + #endif +} HT_CMP_TypeDef; + + +/** + * @brief Operational Amplifier + */ +typedef struct +{ + /* OPA0: 0x40018000 */ + /* OPA1: 0x40018100 */ + __IO uint32_t CR; /*!< 0x000 Operational Amplifier Control Register */ + #if defined(USE_HT32F65232) + __IO uint32_t VOS; /*!< 0x004 Operational Amplifier Input Offset Register */ + __IO uint32_t DAC; /*!< 0x008 Operational Amplifier Voltage Reference Value Register */ + #endif +} HT_OPA_TypeDef; + +/** + * @brief Programmable Gain Amplifier 0~X + */ +typedef struct +{ + /* PGA0: 0x40018000 */ + /* PGA1: 0x40018008 */ + /* PGA2: 0x40018010 */ + /* PGA3: 0x40018018 */ + __IO uint32_t CR; /*!< 0x000 Programmable Gain Amplifier Control Register */ + __IO uint32_t VOS; /*!< 0x004 Programmable Gain Amplifier Offset Control Register */ +} HT_PGA0_X_TypeDef; + +/** + * @brief Programmable Gain Amplifier + */ +typedef struct +{ + /* PGA: 0x40018000 */ + __IO uint32_t VR; /*!< 0x020 PGA Voltage Follower Control Register */ +} HT_PGA_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + /* GPIOA: 0x400B0000 */ + /* GPIOB: 0x400B2000 */ + /* GPIOC: 0x400B4000 */ + /* GPIOD: 0x400B6000 */ + /* GPIOE: 0x400B8000 */ + /* GPIOF: 0x400BA000 */ + __IO uint32_t DIRCR; /*!< 0x000 Data Direction Control Register */ + __IO uint32_t INER; /*!< 0x004 Input function enable register */ + __IO uint32_t PUR; /*!< 0x008 Pull-Up Selection Register */ + __IO uint32_t PDR; /*!< 0x00C Pull-Down Selection Register */ + __IO uint32_t ODR; /*!< 0x010 Open Drain Selection Register */ + __IO uint32_t DRVR; /*!< 0x014 Drive Current Selection Register */ + __IO uint32_t LOCKR; /*!< 0x018 Lock Register */ + __IO uint32_t DINR; /*!< 0x01c Data Input Register */ + __IO uint32_t DOUTR; /*!< 0x020 Data Output Register */ + __IO uint32_t SRR; /*!< 0x024 Output Set and Reset Control Register */ + __IO uint32_t RR; /*!< 0x028 Output Reset Control Register */ + #if defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) || defined(USE_HT32F54231_41) || defined(USE_HT32F54243_53) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) + __IO uint32_t SCER; /*!< 0x02C Sink Current Enhanced Selection Register */ + #endif +} HT_GPIO_TypeDef; + + +/** + * @brief AFIO + */ +typedef struct +{ + /* AFIO: 0x40022000 */ + #if defined(USE_HT32F50020_30) + __IO uint32_t ESSR[1]; /*!< 0x000 EXTI Source Selection Register 0 */ + uint32_t RESERVE0[7]; /*!< 0x004 - 0x01C Reserved */ + #else + __IO uint32_t ESSR[2]; /*!< 0x000 EXTI Source Selection Register 0 ~ 1 */ + uint32_t RESERVE0[6]; /*!< 0x008 - 0x01C Reserved */ + #endif + __IO uint32_t GPACFGR[2]; /*!< 0x020 GPIO Port A Configuration Register 0 ~ 1 */ + __IO uint32_t GPBCFGR[2]; /*!< 0x028 GPIO Port B Configuration Register 0 ~ 1 */ + #if !defined(USE_HT32F52220_30) + __IO uint32_t GPCCFGR[2]; /*!< 0x030 GPIO Port C Configuration Register 0 ~ 1 */ + #endif + #if defined(USE_HT32F52342_52) || defined(USE_HT32F52243_53) || defined(USE_HT32F5826) || defined(USE_HT32F52344_54) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F54243_53) || defined(USE_HT32F61244_45) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) + __IO uint32_t GPDCFGR[2]; /*!< 0x038 GPIO Port D Configuration Register 0 ~ 1 */ + #endif + #if defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) + __IO uint32_t GPECFGR[2]; /*!< 0x040 GPIO Port E Configuration Register 0 ~ 1 */ + #endif + #if defined(USE_HT32F0008) || defined(USE_HT32F50020_30) + uint32_t RESERVE1[4]; /*!< 0x038 - 0x044 Reserved */ + __IO uint32_t GPFCFGR[2]; /*!< 0x048 GPIO Port F Configuration Register 0 ~ 1 */ + #endif +} HT_AFIO_TypeDef; + + +/** + * @brief External Interrupt/Event Controller + */ +typedef struct +{ + /* EXTI: 0x40024000 */ + __IO uint32_t CFGR0; /*!< 0x000 EXTI Interrupt 0 Configuration Register */ + __IO uint32_t CFGR1; /*!< 0x004 EXTI Interrupt 1 Configuration Register */ + __IO uint32_t CFGR2; /*!< 0x008 EXTI Interrupt 2 Configuration Register */ + __IO uint32_t CFGR3; /*!< 0x00C EXTI Interrupt 3 Configuration Register */ + __IO uint32_t CFGR4; /*!< 0x010 EXTI Interrupt 4 Configuration Register */ + __IO uint32_t CFGR5; /*!< 0x014 EXTI Interrupt 5 Configuration Register */ + __IO uint32_t CFGR6; /*!< 0x018 EXTI Interrupt 6 Configuration Register */ + __IO uint32_t CFGR7; /*!< 0x01C EXTI Interrupt 7 Configuration Register */ + #if defined(USE_HT32F50020_30) + __IO uint32_t RESERVE0[8]; /*!< 0x020 - 0x3C Reserved */ + #else + __IO uint32_t CFGR8; /*!< 0x020 EXTI Interrupt 8 Configuration Register */ + __IO uint32_t CFGR9; /*!< 0x024 EXTI Interrupt 9 Configuration Register */ + __IO uint32_t CFGR10; /*!< 0x028 EXTI Interrupt 10 Configuration Register */ + __IO uint32_t CFGR11; /*!< 0x02C EXTI Interrupt 11 Configuration Register */ + __IO uint32_t CFGR12; /*!< 0x030 EXTI Interrupt 12 Configuration Register */ + __IO uint32_t CFGR13; /*!< 0x034 EXTI Interrupt 13 Configuration Register */ + __IO uint32_t CFGR14; /*!< 0x038 EXTI Interrupt 14 Configuration Register */ + __IO uint32_t CFGR15; /*!< 0x03C EXTI Interrupt 15 Configuration Register */ + #endif + __IO uint32_t CR; /*!< 0x040 EXTI Interrupt Control Register */ + __IO uint32_t EDGEFLGR; /*!< 0x044 EXTI Interrupt Edge Flag Register */ + __IO uint32_t EDGESR; /*!< 0x048 EXTI Interrupt Edge Status Register */ + __IO uint32_t SSCR; /*!< 0x04C EXTI Interrupt Software Set Command Register */ + __IO uint32_t WAKUPCR; /*!< 0x050 EXTI Interrupt Wakeup Control Register */ + __IO uint32_t WAKUPPOLR; /*!< 0x054 EXTI Interrupt Wakeup Polarity Register */ + __IO uint32_t WAKUPFLG; /*!< 0x058 EXTI Interrupt Wakeup Flag Register */ +} HT_EXTI_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + /* I2C2: 0x40008000 */ + /* I2C0: 0x40048000 */ + /* I2C1: 0x40049000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t IER; /*!< 0x004 Interrupt Enable Register */ + __IO uint32_t ADDR; /*!< 0x008 Address Register */ + __IO uint32_t SR; /*!< 0x00C Status Register */ + __IO uint32_t SHPGR; /*!< 0x010 SCL High Period Generation Register */ + __IO uint32_t SLPGR; /*!< 0x014 SCL Low Period Generation Register */ + __IO uint32_t DR; /*!< 0x018 Data Register */ + __IO uint32_t TAR; /*!< 0x01C Target Register */ + __IO uint32_t ADDMR; /*!< 0x020 Address Mask Register */ + __IO uint32_t ADDSR; /*!< 0x024 Address Snoop Register */ + __IO uint32_t TOUT; /*!< 0x028 Timeout Register */ +} HT_I2C_TypeDef; + + +/** + * @brief WATCHDOG + */ +typedef struct +{ + /* WDT: 0x40068000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t MR0; /*!< 0x004 Mode 0 Register */ + __IO uint32_t MR1; /*!< 0x008 Mode 1 Register */ + __IO uint32_t SR; /*!< 0x00C Status Register */ + __IO uint32_t PR; /*!< 0x010 Write Protect Register */ + uint32_t RESERVED0[1]; /*!< 0x014 Reserved */ + __IO uint32_t CSR; /*!< 0x018 Clock Selection Register */ +} HT_WDT_TypeDef; + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + /* RTC: 0x4006A000 */ + __IO uint32_t CNT; /*!< 0x000 RTC Counter Register */ + __IO uint32_t CMP; /*!< 0x004 RTC Compare Register */ + __IO uint32_t CR; /*!< 0x008 RTC Control Register */ + __IO uint32_t SR; /*!< 0x00C RTC Status Register */ + __IO uint32_t IWEN; /*!< 0x010 RTC Interrupt/Wake-up Enable Register */ +} HT_RTC_TypeDef; + + +/** + * @brief Power Control Unit + */ +typedef struct +{ + /* PWRCU: 0x4006A100 */ + __IO uint32_t SR; /*!< 0x000 Status Register */ + __IO uint32_t CR; /*!< 0x004 Control Register */ + #if !defined(USE_HT32F50220_30) && !defined(USE_HT32F50231_41) && !defined(USE_HT32F65230_40) && !defined(USE_HT32F50343) && !defined(USE_HT32F54231_41) && !defined(USE_HT32F54243_53) && !defined(USE_HT32F50020_30) && !defined(USE_HT32F53231_41) && !defined(USE_HT32F53242_52) && !defined(USE_HT32F50431_41) && !defined(USE_HT32F50442_52) && !defined(USE_HT32F66242) && !defined(USE_HT32F66246) + __IO uint32_t TEST; /*!< 0x008 Test Register */ + #else + uint32_t RESERVE0[1]; /*!< 0x008 Reserved */ + #endif + #if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F52357_67) + __IO uint32_t HSIRCR; /*!< 0x00C HSI Ready Counter Control Register */ + #else + uint32_t RESERVE1[1]; /*!< 0x00C Reserved */ + #endif + __IO uint32_t LVDCSR; /*!< 0x010 Low Voltage/Brown Out Detect Control and Status Register*/ + #if defined(USE_HT32F57342_52) + uint32_t RESERVE2[2]; /*!< 0x014 ~ 0x18 Reserved */ + __IO uint32_t LDOSR ; /*!< 0x01C Power Control LDO Status Register */ + #endif + #if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F52357_67) + uint32_t RESERVE3[59]; /*!< 0x014 ~ 0x0FC Reserved */ + __IO uint32_t BAKREG[10]; /*!< 0x100 ~ 0x124 Backup Register 0 ~ 9 */ + #endif +} HT_PWRCU_TypeDef; + + +/** + * @brief General-Purpose Timer + */ +typedef struct +{ + /* GPTM0: 0x4006E000 */ + /* GPTM1: 0x4006F000 */ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[3]; /*!< 0x014 - 0x01C Reserved */ + __IO uint32_t CH0ICFR; /*!< 0x020 Channel-0 Input Configuration Register */ + __IO uint32_t CH1ICFR; /*!< 0x024 Channel-1 Input Configuration Register */ + __IO uint32_t CH2ICFR; /*!< 0x028 Channel-2 Input Configuration Register */ + __IO uint32_t CH3ICFR; /*!< 0x02C Channel-3 Input Configuration Register */ + uint32_t RESERVED2[4]; /*!< 0x030 - 0x03C Reserved */ + __IO uint32_t CH0OCFR; /*!< 0x040 Channel-0 Output Configuration Register */ + __IO uint32_t CH1OCFR; /*!< 0x044 Channel-1 Output Configuration Register */ + __IO uint32_t CH2OCFR; /*!< 0x048 Channel-2 Output Configuration Register */ + __IO uint32_t CH3OCFR; /*!< 0x04C Channel-3 Output Configuration Register */ + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED3[7]; /*!< 0x058 - 0x070 Reserved */ + __IO uint32_t DICTR; /*!< 0x074 DMA / Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + uint32_t RESERVED4[1]; /*!< 0x08C Reserved */ + __IO uint32_t CH0CCR; /*!< 0x090 Channel 0 Capture/Compare Register */ + __IO uint32_t CH1CCR; /*!< 0x094 Channel 1 Capture/Compare Register */ + __IO uint32_t CH2CCR; /*!< 0x098 Channel 2 Capture/Compare Register */ + __IO uint32_t CH3CCR; /*!< 0x09C Channel 3 Capture/Compare Register */ + __IO uint32_t CH0ACR; /*!< 0x0A0 Channel 0 Asymmetric Compare Register */ + __IO uint32_t CH1ACR; /*!< 0x0A4 Channel 1 Asymmetric Compare Register */ + __IO uint32_t CH2ACR; /*!< 0x0A8 Channel 2 Asymmetric Compare Register */ + __IO uint32_t CH3ACR; /*!< 0x0AC Channel 3 Asymmetric Compare Register */ +} HT_GPTM_TypeDef; + + +/** + * @brief Flash Memory Controller + */ +typedef struct +{ + /* FLASH: 0x40080000 */ + __IO uint32_t TADR; /*!< 0x000 Flash Target Address Register */ + __IO uint32_t WRDR; /*!< 0x004 Flash Write Data Register */ + uint32_t RESERVED0[1]; /*!< 0x008 Reserved */ + __IO uint32_t OCMR; /*!< 0x00C Flash Operation Command Register */ + __IO uint32_t OPCR; /*!< 0x010 Flash Operation Control Register */ + __IO uint32_t OIER; /*!< 0x014 Flash Operation Interrupt Enable Register */ + __IO uint32_t OISR; /*!< 0x018 Flash Operation Interrupt and Status Register */ + uint32_t RESERVED1[1]; /*!< 0x01C Reserved */ + __IO uint32_t PPSR[4]; /*!< 0x020 ~ 0x02C Flash Page Erase/Program Protection Status Register */ + __IO uint32_t CPSR; /*!< 0x030 Flash Security Protection Status Register */ + uint32_t RESERVED2[51]; /*!< 0x034 ~ 0x0FC Reserved */ + __IO uint32_t VMCR; /*!< 0x100 Flash Vector Mapping Control Register */ + uint32_t RESERVED3[31]; /*!< 0x104 ~ 0x17C Reserved */ + __IO uint32_t MDID; /*!< 0x180 Manufacturer and Device ID Register */ + __IO uint32_t PNSR; /*!< 0x184 Flash Page Number Status Register */ + __IO uint32_t PSSR; /*!< 0x188 Flash Page Size Status Register */ + __IO uint32_t DID; /*!< 0x18C Device ID Register */ + uint32_t RESERVED4[28]; /*!< 0x190 ~ 0x1FC Reserved */ + #if defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) + uint32_t RESERVED5[1]; /*!< 0x200 Reserved */ + #else + __IO uint32_t CFCR; /*!< 0x200 Flash Cache and Pre-fetch Control Register */ + #endif + uint32_t RESERVED6[67]; /*!< 0x204 ~ 0x30C Reserved */ + __IO uint32_t CID[4]; /*!< 0x310 ~ 0x31C Custom ID Register */ +} HT_FLASH_TypeDef; + + +/** + * @brief Clock Control Unit + */ +typedef struct +{ + /* CKCU: 0x40088000 */ + __IO uint32_t GCFGR; /*!< 0x000 Global Clock Configuration Register */ + __IO uint32_t GCCR; /*!< 0x004 Global Clock Control Register */ + __IO uint32_t GCSR; /*!< 0x008 Global Clock Status Register */ + __IO uint32_t GCIR; /*!< 0x00C Global Clock Interrupt Register */ + uint32_t RESERVED0[2]; /*!< 0x010 ~ 0x14 Reserved */ + #if !defined(USE_HT32F50220_30) && !defined(USE_HT32F50231_41) + __IO uint32_t PLLCFGR; /*!< 0x018 PLL Configuration Register */ + __IO uint32_t PLLCR; /*!< 0x01C PLL Control Register */ + #else + uint32_t RESERVED1[2]; /*!< 0x018 ~ 0x1C Reserved */ + #endif + __IO uint32_t AHBCFGR; /*!< 0x020 AHB Configuration Register */ + __IO uint32_t AHBCCR; /*!< 0x024 AHB Clock Control Register */ + #if defined(USE_HT32F0008) + uint32_t RESERVED1[1]; /*!< 0x028 Reserved */ + #else + __IO uint32_t APBCFGR; /*!< 0x028 APB Configuration Register */ + #endif + __IO uint32_t APBCCR0; /*!< 0x02C APB Clock Control Register 0 */ + __IO uint32_t APBCCR1; /*!< 0x030 APB Clock Control Register 1 */ + __IO uint32_t CKST; /*!< 0x034 Clock source status Register */ + #if !defined(USE_HT32F50020_30) + __IO uint32_t APBPCSR0; /*!< 0x038 APB Peripheral Clock Selection Register 0 */ + __IO uint32_t APBPCSR1; /*!< 0x03C APB Peripheral Clock Selection Register 1 */ + #else + uint32_t RESERVED2[2]; /*!< 0x038 ~ 0x3C Reserved */ + #endif + #if !defined(USE_HT32F50020_30) + __IO uint32_t HSICR; /*!< 0x040 HSI Control Register */ + __IO uint32_t HSIATCR; /*!< 0x044 HSI Auto Trimming Counter Register */ + #else + uint32_t RESERVED3[2]; /*!< 0x040 ~ 0x44 Reserved */ + #endif + #if defined(USE_HT32F0008) || defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F50343) || defined(USE_HT32F54231_41) || defined(USE_HT32F54243_53) || defined(USE_HT32F61244_45) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) + __IO uint32_t APBPCSR2; /*!< 0x048 APB Peripheral Clock Selection Register 2 */ + uint32_t RESERVED4[173]; /*!< 0x04C ~ 0x2FC Reserved */ + #elif defined(USE_HT32F52234_44) + __IO uint32_t APBPCSR2; /*!< 0x048 APB Peripheral Clock Selection Register 2 */ + __IO uint32_t HSIRDYCR; /*!< 0x04C HSI Ready Counter Register */ + uint32_t RESERVED4[172]; /*!< 0x050 ~ 0x2FC Reserved */ + #else + uint32_t RESERVED4[174]; /*!< 0x048 ~ 0x2FC Reserved */ + #endif + #if !defined(USE_HT32F50020_30) + __IO uint32_t LPCR; /*!< 0x300 Low Power Control Register */ + #else + uint32_t RESERVED5; /*!< 0x300 Reserved */ + #endif + __IO uint32_t MCUDBGCR; /*!< 0x304 MCU Debug Control Register */ +} HT_CKCU_TypeDef; + + +/** + * @brief Reset Control Unit + */ +typedef struct +{ + /* RSTCU: 0x40088100 */ + __IO uint32_t GRSR; /*!< 0x000 Global Reset Status Register */ + __IO uint32_t AHBPRST; /*!< 0x004 AHB Peripheral Reset Register */ + __IO uint32_t APBPRST0; /*!< 0x008 APB Peripheral Reset Register 0 */ + __IO uint32_t APBPRST1; /*!< 0x00C APB Peripheral Reset Register 1 */ +} HT_RSTCU_TypeDef; + + +/** + * @brief Smart Card Interface + */ +typedef struct +{ + /* SCI0: 0x40043000 */ + /* SCI1: 0x4003A000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t CCR; /*!< 0x008 Contact Control Register */ + __IO uint32_t ETU; /*!< 0x00C Elementary Time Unit Register */ + __IO uint32_t GT; /*!< 0x010 Guardtime Register */ + __IO uint32_t WT; /*!< 0x014 Waiting Time Register */ + __IO uint32_t IER; /*!< 0x018 Interrupt Enable Register */ + __IO uint32_t IPR; /*!< 0x01C Interrupt Pending Register */ + __IO uint32_t TXB; /*!< 0x020 Transmit Buffer Register */ + __IO uint32_t RXB; /*!< 0x024 Receive Buffer Register */ + __IO uint32_t PSC; /*!< 0x028 Prescaler Register */ +} HT_SCI_TypeDef; + + +/** + * @brief Basic Function Timer + */ +typedef struct +{ + /* BFTM0: 0x40076000 */ + /* BFTM1: 0x40077000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t CNTR; /*!< 0x008 Counter Value Register */ + __IO uint32_t CMP; /*!< 0x00C Compare Value Register */ +} HT_BFTM_TypeDef; + + +#if 0 +/** + * @brief Motor Control Timer + */ +typedef struct +{ + /* MCTM0: 0x4002C000 */ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[3]; /*!< 0x014 - 0x01C Reserved */ + __IO uint32_t CH0ICFR; /*!< 0x020 Channel-0 Input Configuration Register */ + __IO uint32_t CH1ICFR; /*!< 0x024 Channel-1 Input Configuration Register */ + __IO uint32_t CH2ICFR; /*!< 0x028 Channel-2 Input Configuration Register */ + __IO uint32_t CH3ICFR; /*!< 0x02C Channel-3 Input Configuration Register */ + uint32_t RESERVED2[4]; /*!< 0x030 - 0x03C Reserved */ + __IO uint32_t CH0OCFR; /*!< 0x040 Channel-0 Output Configuration Register */ + __IO uint32_t CH1OCFR; /*!< 0x044 Channel-1 Output Configuration Register */ + __IO uint32_t CH2OCFR; /*!< 0x048 Channel-2 Output Configuration Register */ + __IO uint32_t CH3OCFR; /*!< 0x04C Channel-3 Output Configuration Register */ + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED3[5]; /*!< 0x058 - 0x068 Reserved */ + __IO uint32_t CHBRKCFR; /*!< 0x06C Channel Break Configuration Register */ + __IO uint32_t CHBRKCTR; /*!< 0x070 Channel Break Control Register */ + __IO uint32_t DICTR; /*!< 0x074 DMA / Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + __IO uint32_t REPR; /*!< 0x08C Repetition Register */ + __IO uint32_t CH0CCR; /*!< 0x090 Channel 0 Capture/Compare Register */ + __IO uint32_t CH1CCR; /*!< 0x094 Channel 1 Capture/Compare Register */ + __IO uint32_t CH2CCR; /*!< 0x098 Channel 2 Capture/Compare Register */ + __IO uint32_t CH3CCR; /*!< 0x09C Channel 3 Capture/Compare Register */ + __IO uint32_t CH0ACR; /*!< 0x0A0 Channel 0 Asymmetric Compare Register */ + __IO uint32_t CH1ACR; /*!< 0x0A4 Channel 1 Asymmetric Compare Register */ + __IO uint32_t CH2ACR; /*!< 0x0A8 Channel 2 Asymmetric Compare Register */ + __IO uint32_t CH3ACR; /*!< 0x0AC Channel 3 Asymmetric Compare Register */ +} HT_MCTM_TypeDef; +#endif + + +/** + * @brief Timer + */ +typedef struct +{ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[3]; /*!< 0x014 - 0x01C Reserved */ + __IO uint32_t CH0ICFR; /*!< 0x020 Channel-0 Input Configuration Register */ + __IO uint32_t CH1ICFR; /*!< 0x024 Channel-1 Input Configuration Register */ + __IO uint32_t CH2ICFR; /*!< 0x028 Channel-2 Input Configuration Register */ + __IO uint32_t CH3ICFR; /*!< 0x02C Channel-3 Input Configuration Register */ + uint32_t RESERVED2[4]; /*!< 0x030 - 0x03C Reserved */ + __IO uint32_t CH0OCFR; /*!< 0x040 Channel-0 Output Configuration Register */ + __IO uint32_t CH1OCFR; /*!< 0x044 Channel-1 Output Configuration Register */ + __IO uint32_t CH2OCFR; /*!< 0x048 Channel-2 Output Configuration Register */ + __IO uint32_t CH3OCFR; /*!< 0x04C Channel-3 Output Configuration Register */ + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED3[5]; /*!< 0x058 - 0x068 Reserved */ + __IO uint32_t CHBRKCFR; /*!< 0x06C Channel Break Configuration Register */ + __IO uint32_t CHBRKCTR; /*!< 0x070 Channel Break Control Register */ + __IO uint32_t DICTR; /*!< 0x074 DMA / Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + __IO uint32_t REPR; /*!< 0x08C Repetition Register */ + __IO uint32_t CH0CCR; /*!< 0x090 Channel 0 Capture/Compare Register */ + __IO uint32_t CH1CCR; /*!< 0x094 Channel 1 Capture/Compare Register */ + __IO uint32_t CH2CCR; /*!< 0x098 Channel 2 Capture/Compare Register */ + __IO uint32_t CH3CCR; /*!< 0x09C Channel 3 Capture/Compare Register */ + __IO uint32_t CH0ACR; /*!< 0x0A0 Channel 0 Asymmetric Compare Register */ + __IO uint32_t CH1ACR; /*!< 0x0A4 Channel 1 Asymmetric Compare Register */ + __IO uint32_t CH2ACR; /*!< 0x0A8 Channel 2 Asymmetric Compare Register */ + __IO uint32_t CH3ACR; /*!< 0x0AC Channel 3 Asymmetric Compare Register */ + #if defined(USE_HT32F50343) + uint32_t RESERVED4[20]; /*!< 0x0B0 - 0x0FC Reserved */ + __IO uint32_t CH4OCFR; /*!< 0x100 Channel-4 Output Configuration Register */ + __IO uint32_t CH5OCFR; /*!< 0x104 Channel-5 Output Configuration Register */ + __IO uint32_t CH6OCFR; /*!< 0x108 Channel-6 Output Configuration Register */ + __IO uint32_t CH7OCFR; /*!< 0x10C Channel-7 Output Configuration Register */ + __IO uint32_t CH4CR; /*!< 0x110 Channel 4 Compare Register */ + __IO uint32_t CH5CR; /*!< 0x114 Channel 5 Compare Register */ + __IO uint32_t CH6CR; /*!< 0x118 Channel 6 Compare Register */ + __IO uint32_t CH7CR; /*!< 0x11C Channel 7 Compare Register */ + #endif +} HT_TM_TypeDef; + + +/** + * @brief Peripheral Direct Memory Access Channel + */ +typedef struct +{ + __IO uint32_t CR; /*!< 0x000 PDMA Channel Control Register */ + __IO uint32_t SADR; /*!< 0x004 PDMA Channel Source Address Register */ + __IO uint32_t DADR; /*!< 0x008 PDMA Channel Destination Address Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t TSR; /*!< 0x010 PDMA Channel Transfer Size Register */ + __IO uint32_t CTSR; /*!< 0x014 PDMA Channel Current Transfer Size Register */ +} HT_PDMACH_TypeDef; + + +/** + * @brief Peripheral Direct Memory Access Global + */ +typedef struct +{ + /* PDMA: 0x40090000 */ + HT_PDMACH_TypeDef PDMACH0; /*!< 0x000 PDMA channel 0 registers */ + HT_PDMACH_TypeDef PDMACH1; /*!< 0x018 PDMA channel 1 registers */ + HT_PDMACH_TypeDef PDMACH2; /*!< 0x030 PDMA channel 2 registers */ + HT_PDMACH_TypeDef PDMACH3; /*!< 0x048 PDMA channel 3 registers */ + HT_PDMACH_TypeDef PDMACH4; /*!< 0x060 PDMA channel 4 registers */ + HT_PDMACH_TypeDef PDMACH5; /*!< 0x078 PDMA channel 5 registers */ + uint32_t RESERVED0[36];/*!< 0x090 - 0x11C Reserved */ + __IO uint32_t ISR; /*!< 0x120 PDMA Interrupt Status Register */ + uint32_t RESERVED1[1]; /*!< 0x124 Reserved */ + __IO uint32_t ISCR; /*!< 0x128 PDMA Interrupt Status Clear Register */ + uint32_t RESERVED2[1]; /*!< 0x12C Reserved */ + __IO uint32_t IER; /*!< 0x130 PDMA Interrupt Enable Register */ +} HT_PDMA_TypeDef; + + +/** + * @brief Universal Serial Bus Global + */ +typedef struct +{ + /* USB: 0x400A8000 */ + __IO uint32_t CSR; /*!< 0x000 USB Control and Status Register */ + __IO uint32_t IER; /*!< 0x004 USB Interrupt Enable Register */ + __IO uint32_t ISR; /*!< 0x008 USB Interrupt Status Register */ + __IO uint32_t FCR; /*!< 0x00C USB Frame Count Register */ + __IO uint32_t DEVAR; /*!< 0x010 USB Device Address Register */ + __IO uint32_t EP0CSR; /*!< 0x014 USB Endpoint 0 Control and Status Register */ + __IO uint32_t EP0IER; /*!< 0x018 USB Endpoint 0 Interrupt Enable Register */ + __IO uint32_t EP0ISR; /*!< 0x01C USB Endpoint 0 Interrupt Status Register */ + __IO uint32_t EP0TCR; /*!< 0x020 USB Endpoint 0 Transfer Count Register */ + __IO uint32_t EP0CFGR; /*!< 0x024 USB Endpoint 0 Configuration Register */ + __IO uint32_t EP1CSR; /*!< 0x028 USB Endpoint 1 Control and Status Register */ + __IO uint32_t EP1IER; /*!< 0x02C USB Endpoint 1 Interrupt Enable Register */ + __IO uint32_t EP1ISR; /*!< 0x030 USB Endpoint 1 Interrupt Status Register */ + __IO uint32_t EP1TCR; /*!< 0x034 USB Endpoint 1 Transfer Count Register */ + __IO uint32_t EP1CFGR; /*!< 0x038 USB Endpoint 1 Configuration Register */ + __IO uint32_t EP2CSR; /*!< 0x03C USB Endpoint 2 Control and Status Register */ + __IO uint32_t EP2IER; /*!< 0x040 USB Endpoint 2 Interrupt Enable Register */ + __IO uint32_t EP2ISR; /*!< 0x044 USB Endpoint 2 Interrupt Status Register */ + __IO uint32_t EP2TCR; /*!< 0x048 USB Endpoint 2 Transfer Count Register */ + __IO uint32_t EP2CFGR; /*!< 0x04C USB Endpoint 2 Configuration Register */ + __IO uint32_t EP3CSR; /*!< 0x050 USB Endpoint 3 Control and Status Register */ + __IO uint32_t EP3IER; /*!< 0x054 USB Endpoint 3 Interrupt Enable Register */ + __IO uint32_t EP3ISR; /*!< 0x058 USB Endpoint 3 Interrupt Status Register */ + __IO uint32_t EP3TCR; /*!< 0x05C USB Endpoint 3 Transfer Count Register */ + __IO uint32_t EP3CFGR; /*!< 0x060 USB Endpoint 3 Configuration Register */ + __IO uint32_t EP4CSR; /*!< 0x064 USB Endpoint 4 Control and Status Register */ + __IO uint32_t EP4IER; /*!< 0x068 USB Endpoint 4 Interrupt Enable Register */ + __IO uint32_t EP4ISR; /*!< 0x06C USB Endpoint 4 Interrupt Status Register */ + __IO uint32_t EP4TCR; /*!< 0x070 USB Endpoint 4 Transfer Count Register */ + __IO uint32_t EP4CFGR; /*!< 0x074 USB Endpoint 4 Configuration Register */ + __IO uint32_t EP5CSR; /*!< 0x078 USB Endpoint 5 Control and Status Register */ + __IO uint32_t EP5IER; /*!< 0x07C USB Endpoint 5 Interrupt Enable Register */ + __IO uint32_t EP5ISR; /*!< 0x080 USB Endpoint 5 Interrupt Status Register */ + __IO uint32_t EP5TCR; /*!< 0x084 USB Endpoint 5 Transfer Count Register */ + __IO uint32_t EP5CFGR; /*!< 0x088 USB Endpoint 5 Configuration Register */ + __IO uint32_t EP6CSR; /*!< 0x08C USB Endpoint 6 Control and Status Register */ + __IO uint32_t EP6IER; /*!< 0x090 USB Endpoint 6 Interrupt Enable Register */ + __IO uint32_t EP6ISR; /*!< 0x094 USB Endpoint 6 Interrupt Status Register */ + __IO uint32_t EP6TCR; /*!< 0x098 USB Endpoint 6 Transfer Count Register */ + __IO uint32_t EP6CFGR; /*!< 0x09C USB Endpoint 6 Configuration Register */ + __IO uint32_t EP7CSR; /*!< 0x0A0 USB Endpoint 7 Control and Status Register */ + __IO uint32_t EP7IER; /*!< 0x0A4 USB Endpoint 7 Interrupt Enable Register */ + __IO uint32_t EP7ISR; /*!< 0x0A8 USB Endpoint 7 Interrupt Status Register */ + __IO uint32_t EP7TCR; /*!< 0x0AC USB Endpoint 7 Transfer Count Register */ + __IO uint32_t EP7CFGR; /*!< 0x0B0 USB Endpoint 7 Configuration Register */ + #if defined(USE_HT32F61141) + __IO uint32_t EP8CSR; /*!< 0x0B4 USB Endpoint 8 Control and Status Register */ + __IO uint32_t EP8IER; /*!< 0x0B8 USB Endpoint 8 Interrupt Enable Register */ + __IO uint32_t EP8ISR; /*!< 0x0BC USB Endpoint 8 Interrupt Status Register */ + __IO uint32_t EP8TCR; /*!< 0x0C0 USB Endpoint 8 Transfer Count Register */ + __IO uint32_t EP8CFGR; /*!< 0x0C4 USB Endpoint 8 Configuration Register */ + __IO uint32_t EP9CSR; /*!< 0x0C8 USB Endpoint 9 Control and Status Register */ + __IO uint32_t EP9IER; /*!< 0x0CC USB Endpoint 9 Interrupt Enable Register */ + __IO uint32_t EP9ISR; /*!< 0x0D0 USB Endpoint 9 Interrupt Status Register */ + __IO uint32_t EP9TCR; /*!< 0x0D4 USB Endpoint 9 Transfer Count Register */ + __IO uint32_t EP9CFGR; /*!< 0x0D8 USB Endpoint 9 Configuration Register */ + #endif +} HT_USB_TypeDef; + + +/** + * @brief Universal Serial Bus Endpoint + */ +typedef struct +{ + /* USB Endpoint0: 0x400A8014 */ + /* USB Endpoint1: 0x400A8028 */ + /* USB Endpoint2: 0x400A803C */ + /* USB Endpoint3: 0x400A8050 */ + /* USB Endpoint4: 0x400A8064 */ + /* USB Endpoint5: 0x400A8078 */ + /* USB Endpoint6: 0x400A808C */ + /* USB Endpoint7: 0x400A80A0 */ + /* USB Endpoint8: 0x400A80B4 */ + /* USB Endpoint9: 0x400A80C8 */ + __IO uint32_t CSR; /*!< 0x000 USB Endpoint n Control and Status Register */ + __IO uint32_t IER; /*!< 0x004 USB Endpoint n Interrupt Enable Register */ + __IO uint32_t ISR; /*!< 0x008 USB Endpoint n Interrupt Status Register */ + __IO uint32_t TCR; /*!< 0x00C USB Endpoint n Transfer Count Register */ + __IO uint32_t CFGR; /*!< 0x010 USB Endpoint n Configuration Register */ +} HT_USBEP_TypeDef; + + +/** + * @brief External Bus Interface + */ +typedef struct +{ + /* EBI: 0x40098000 */ + __IO uint32_t CR; /*!< 0x000 EBI Control Register */ + uint32_t RESERVED0[1]; /*!< 0x004 Reserved */ + __IO uint32_t SR; /*!< 0x008 EBI Status Register */ + uint32_t RESERVED1[1]; /*!< 0x00C Reserved */ + __IO uint32_t ATR; /*!< 0x010 EBI Address Timing Register */ + __IO uint32_t RTR; /*!< 0x014 EBI Read Timing Register */ + __IO uint32_t WTR; /*!< 0x018 EBI Write Timing Register */ + __IO uint32_t PR; /*!< 0x01C EBI Parity Register */ +} HT_EBI_TypeDef; + + +/** + * @brief Cyclic Redundancy Check + */ +typedef struct +{ + /* CRC: 0x4008A000 */ + __IO uint32_t CR; /*!< 0x000 CRC Control Register */ + __IO uint32_t SDR; /*!< 0x004 CRC Seed Register */ + __IO uint32_t CSR; /*!< 0x008 CRC Checksum Register */ + __IO uint32_t DR; /*!< 0x00C CRC Data Register */ +} HT_CRC_TypeDef; + + +/** + * @brief Integrated Interchip Sound + */ +typedef struct +{ + /* I2S: 0x40026000 */ + __IO uint32_t CR; /*!< 0x000 I2S Control Register */ + __IO uint32_t IER; /*!< 0x004 I2S Interrupt Enable Register */ + __IO uint32_t CDR; /*!< 0x008 I2S Clock Divider Register */ + __IO uint32_t TXDR; /*!< 0x00C I2S TX Data Register */ + __IO uint32_t RXDR; /*!< 0x010 I2S RX Data Register */ + __IO uint32_t FCR; /*!< 0x014 I2S FIFO Control Register */ + __IO uint32_t SR; /*!< 0x018 I2S Status Register */ + __IO uint32_t RCNTR; /*!< 0x01C I2S Rate Counter Register */ +} HT_I2S_TypeDef; + + +/** + * @brief PWM Timer + */ +typedef struct +{ + /* PWM0: 0x40031000 */ + /* PWM2: 0x40032000 */ + /* PWM1: 0x40071000 */ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[11]; /*!< 0x014 - 0x03C Reserved */ + __IO uint32_t CH0OCFR; /*!< 0x040 Channel-0 Output Configuration Register */ + __IO uint32_t CH1OCFR; /*!< 0x044 Channel-1 Output Configuration Register */ + __IO uint32_t CH2OCFR; /*!< 0x048 Channel-2 Output Configuration Register */ + __IO uint32_t CH3OCFR; /*!< 0x04C Channel-3 Output Configuration Register */ + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED2[7]; /*!< 0x058 - 0x070 Reserved */ + __IO uint32_t DICTR; /*!< 0x074 DMA / Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + uint32_t RESERVED3[1]; /*!< 0x08C Reserved */ + __IO uint32_t CH0CR; /*!< 0x090 Channel 0 Compare Register */ + __IO uint32_t CH1CR; /*!< 0x094 Channel 1 Compare Register */ + __IO uint32_t CH2CR; /*!< 0x098 Channel 2 Compare Register */ + __IO uint32_t CH3CR; /*!< 0x09C Channel 3 Compare Register */ + __IO uint32_t CH0ACR; /*!< 0x0A0 Channel 0 Asymmetric Compare Register */ + __IO uint32_t CH1ACR; /*!< 0x0A4 Channel 1 Asymmetric Compare Register */ + __IO uint32_t CH2ACR; /*!< 0x0A8 Channel 2 Asymmetric Compare Register */ + __IO uint32_t CH3ACR; /*!< 0x0AC Channel 3 Asymmetric Compare Register */ + #if defined(USE_HT32F50343) + uint32_t RESERVED4[20]; /*!< 0x0B0 - 0x0FC Reserved */ + __IO uint32_t CH4OCFR; /*!< 0x100 Channel-4 Output Configuration Register */ + __IO uint32_t CH5OCFR; /*!< 0x104 Channel-5 Output Configuration Register */ + __IO uint32_t CH6OCFR; /*!< 0x108 Channel-6 Output Configuration Register */ + __IO uint32_t CH7OCFR; /*!< 0x10C Channel-7 Output Configuration Register */ + __IO uint32_t CH4CR; /*!< 0x110 Channel 4 Compare Register */ + __IO uint32_t CH5CR; /*!< 0x114 Channel 5 Compare Register */ + __IO uint32_t CH6CR; /*!< 0x118 Channel 6 Compare Register */ + __IO uint32_t CH7CR; /*!< 0x11C Channel 7 Compare Register */ + #endif +} HT_PWM_TypeDef; + + +/** + * @brief Single Channel Timer + */ +typedef struct +{ + /* SCTM0: 0x40034000 */ + /* SCTM1: 0x40074000 */ + /* SCTM2: 0x40035000 */ + /* SCTM3: 0x40075000 */ + __IO uint32_t CNTCFR; /*!< 0x000 Counter Configuration Register */ + __IO uint32_t MDCFR; /*!< 0x004 Mode Configuration Register */ + __IO uint32_t TRCFR; /*!< 0x008 Trigger Configuration Register */ + uint32_t RESERVED0[1]; /*!< 0x00C Reserved */ + __IO uint32_t CTR; /*!< 0x010 Control Register */ + uint32_t RESERVED1[3]; /*!< 0x014 - 0x01C Reserved */ + __IO uint32_t CH0ICFR; /*!< 0x020 Channel 0 Input Configuration Register */ + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined(USE_HT32F66246) + __IO uint32_t CH1ICFR; /*!< 0x024 Channel 1 Input Configuration Register */ + uint32_t RESERVED2[6]; /*!< 0x028 - 0x03C Reserved */ + #else + uint32_t RESERVED2[7]; /*!< 0x024 - 0x03C Reserved */ + #endif + __IO uint32_t CHOCFR; /*!< 0x040 Channel Output Configuration Register */ + #if defined(USE_HT32F50020_30) + __IO uint32_t CH1OCFR; /*!< 0x044 Channel 1 Output Configuration Register */ + uint32_t RESERVED3[2]; /*!< 0x048 - 0x04C Reserved */ + #else + uint32_t RESERVED3[3]; /*!< 0x044 - 0x04C Reserved */ + #endif + __IO uint32_t CHCTR; /*!< 0x050 Channel Control Register */ + __IO uint32_t CHPOLR; /*!< 0x054 Channel Polarity Configuration Register */ + uint32_t RESERVED4[7]; /*!< 0x058 - 0x070 Reserved */ + __IO uint32_t DICTR; /*!< 0x074 Interrupt Control Register */ + __IO uint32_t EVGR; /*!< 0x078 Event Generator Register */ + __IO uint32_t INTSR; /*!< 0x07C Interrupt Status Register */ + __IO uint32_t CNTR; /*!< 0x080 Counter Register */ + __IO uint32_t PSCR; /*!< 0x084 Prescaler Register */ + __IO uint32_t CRR; /*!< 0x088 Counter Reload Register */ + uint32_t RESERVED5[1]; /*!< 0x08C Reserved */ + __IO uint32_t CH0CCR; /*!< 0x090 Channel 0 Capture/Compare Register */ + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F50020_30) || defined(USE_HT32F66242) || defined(USE_HT32F66246) + __IO uint32_t CH1CCR; /*!< 0x094 Channel 1 Capture Register */ + #endif +} HT_SCTM_TypeDef; + + +/** + * @brief Divider + */ +typedef struct +{ + /* DIV: 0x400CA000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t DDR; /*!< 0x004 Dividend register */ + __IO uint32_t DSR; /*!< 0x008 Divisor Register */ + __IO uint32_t QTR; /*!< 0x00C Quotient Register */ + __IO uint32_t RMR; /*!< 0x010 Remainder Register */ +} HT_DIV_TypeDef; + + +/** + * @brief Advanced Encryption Standard + */ +typedef struct +{ + /* AES: 0x400C8000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t PDMAR; /*!< 0x008 PDMA Register */ + __IO uint32_t ISR; /*!< 0x00C Interrupt Status Register */ + __IO uint32_t IER; /*!< 0x010 Interrupt Enable Register */ + __IO uint32_t DINR; /*!< 0x014 Data Input Register */ + __IO uint32_t DOUTR; /*!< 0x018 Data Output Register */ + #if defined(USE_HT32F52357_67) + __IO uint32_t KEYR[8]; /*!< 0x01C - 0x038 Key Register 0~7 */ + #else + __IO uint32_t KEYR[4]; /*!< 0x01C - 0x028 Key Register 0~3 */ + uint32_t RESERVED0[4]; /*!< 0x02C - 0x038 Reserved */ + #endif + __IO uint32_t IVR[4]; /*!< 0x03C - 0x048 Initial Vector Register 0~3 */ +} HT_AES_TypeDef; + + +/** + * @brief MIDI + */ +typedef struct +{ + /* MIDI: 0x40060000 */ + __IO uint32_t CHAN; /*!< 0x000 MIDI Channel Number Select */ + __IO uint32_t FREQ; /*!< 0x004 MIDI Frequency Number */ + __IO uint32_t VOL; /*!< 0x008 MIDI Volume Control */ + __IO uint32_t ST_ADDR; /*!< 0x00C MIDI Start Address */ + __IO uint32_t RE_NUM; /*!< 0x010 MIDI Repeat Number */ + __IO uint32_t END_ADDR; /*!< 0x014 MIDI End Address */ + __IO uint32_t IER; /*!< 0x018 MIDI Interrupt/DMA Enable Register */ + __IO uint32_t SR; /*!< 0x01C MIDI Status Register */ + __IO uint32_t MCU_CH0; /*!< 0x020 MIDI MCU Channel 0 data */ + __IO uint32_t MCU_CH1; /*!< 0x024 MIDI MCU Channel 1 data */ + __IO uint32_t MCU_CH2; /*!< 0x028 MIDI MCU Channel 2 data */ + __IO uint32_t MCU_CH3; /*!< 0x02C MIDI MCU Channel 3 data */ + __IO uint32_t MIDIL; /*!< 0x030 MIDI Engine Waveform of Left Channel */ + __IO uint32_t MIDIR; /*!< 0x034 MIDI Engine Waveform of Right Channel */ + __IO uint32_t SPI_DATA; /*!< 0x038 MIDI SPI Flash data read */ + __IO uint32_t SPI_ADDR; /*!< 0x03C MIDI SPI Flash address read */ + __IO uint32_t CTRL; /*!< 0x040 MIDI Control Register */ +} HT_MIDI_TypeDef; + + +/** + * @brief LCD + */ +typedef struct +{ + /* LCD: 0x4001A000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t FCR; /*!< 0x004 Frame Control Register */ + __IO uint32_t IER; /*!< 0x008 Interrupt Enable Register */ + __IO uint32_t SR; /*!< 0x00C Status Register */ + __IO uint32_t CLR; /*!< 0x010 Clear Register */ + uint32_t RESERVED[3]; /*!< 0x014 - 0x020 Reserved */ + __IO uint32_t RAM[16]; /*!< 0x020 - 0x05C Display Memory */ +} HT_LCD_TypeDef; + + +/** + * @brief Serial SLED Interface + */ +typedef struct +{ + /* SLED0: 0x4000E000 */ + /* SLED1: 0x4004E000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t CDR; /*!< 0x008 Clock Divider Register */ + __IO uint32_t TCR; /*!< 0x00C Timne Code Register */ + union { + __IO uint8_t DR_8BIT; /*!< 0x010 Data Register, 8-bit access, duplicate 4 times into 32-bit */ + __IO uint16_t DR_16BIT; /*!< 0x010 Data Register, 16-bit access, duplicate 2 times into 32-bit */ + __IO uint32_t DR_32BIT; /*!< 0x010 Data Register */ + }; + __IO uint32_t FCR; /*!< 0x014 FIFO Control Register */ +} HT_SLED_TypeDef; + + +/** + * @brief Touch Key Module + */ +typedef struct +{ + __IO uint32_t CR; /*!< 0x000 Touch Key Module Control Register */ + __IO uint32_t KCFGR; /*!< 0x004 Touch Key Module Key Configuration Register */ + __IO uint32_t SR; /*!< 0x008 Touch Key Module Status Register */ + __IO uint32_t ROCPR; /*!< 0x00C Touch Key Module Reference OSC Capacitor Register */ + __IO uint32_t K3CPR; /*!< 0x010 Touch Key Module Key 3 Capacitor Register */ + __IO uint32_t K2CPR; /*!< 0x014 Touch Key Module Key 2 Capacitor Register */ + __IO uint32_t K1CPR; /*!< 0x018 Touch Key Module Key 1 Capacitor Register */ + __IO uint32_t K0CPR; /*!< 0x01C Touch Key Module Key 0 Capacitor Register */ + __IO uint32_t CFCNTR; /*!< 0x020 Touch Key Module C/F Counter Register */ + __IO uint32_t K3CNTR; /*!< 0x024 Touch Key Module Key 3 Counter Register */ + __IO uint32_t K2CNTR; /*!< 0x028 Touch Key Module Key 2 Counter Register */ + __IO uint32_t K1CNTR; /*!< 0x02C Touch Key Module Key 1 Counter Register */ + __IO uint32_t K0CNTR; /*!< 0x030 Touch Key Module Key 0 Counter Register */ + __IO uint32_t K3THR; /*!< 0x034 Touch Key Module Key 3 Threshold Register */ + __IO uint32_t K2THR; /*!< 0x038 Touch Key Module Key 2 Threshold Register */ + __IO uint32_t K1THR; /*!< 0x03C Touch Key Module Key 1 Threshold Register */ + __IO uint32_t K0THR; /*!< 0x040 Touch Key Module Key 0 Threshold Register */ + uint32_t RESERVED0[47]; /*!< 0x044 - 0x0FC Reserved */ +} HT_TKM_TypeDef; + + +/** + * @brief Touch Key + */ +typedef struct +{ + /* TKEY: 0x4001A000 */ + __IO uint32_t TKCR; /*!< 0x000 Touch Key Control Register */ + __IO uint32_t TKCNTR; /*!< 0x004 Touch Key Counter Register */ + __IO uint32_t TKTSCRR; /*!< 0x008 Touch Key Time Slot Counter Reload Register */ + __IO uint32_t TKIER; /*!< 0x00C Touch Key Interrupt Enable Register */ + __IO uint32_t TKSR; /*!< 0x010 Touch Key Status Register */ + uint32_t RESERVED0[59]; /*!< 0x014 - 0x0FC Reserved */ + HT_TKM_TypeDef TKM0; /*!< 0x100 Touch Key Module 0 registers */ + HT_TKM_TypeDef TKM1; /*!< 0x200 Touch Key Module 1 registers */ + HT_TKM_TypeDef TKM2; /*!< 0x300 Touch Key Module 2 registers */ + HT_TKM_TypeDef TKM3; /*!< 0x400 Touch Key Module 3 registers */ + HT_TKM_TypeDef TKM4; /*!< 0x500 Touch Key Module 4 registers */ + HT_TKM_TypeDef TKM5; /*!< 0x600 Touch Key Module 5 registers */ +} HT_TKEY_TypeDef; + + +/** + * @brief LED Controller + */ +typedef struct +{ + /* LEDC: 0x4005A000 */ + __IO uint32_t CR; /*!< 0x000 LED Control Register */ + __IO uint32_t CER; /*!< 0x004 LED COM Enable Register */ + __IO uint32_t PCR; /*!< 0x008 LED Polarity Control Register */ + __IO uint32_t IER; /*!< 0x00C LED Interrupt Enable Register */ + __IO uint32_t SR; /*!< 0x010 LED Status Register */ + __IO uint32_t DTCR; /*!< 0x014 LED Dead Time Control Register */ + #if defined(USE_HT32F54231_41) || defined(USE_HT32F50020_30) || defined(USE_HT32F53231_41) || defined(USE_HT32F53242_52) || defined(USE_HT32F50431_41) || defined(USE_HT32F50442_52) + __IO uint32_t DR[8]; /*!< 0x018 - 0x034 LED Data Register */ + #endif + #if defined(USE_HT32F54243_53) + __IO uint32_t DR[12]; /*!< 0x018 - 0x044 LED Data Register */ + #endif +} HT_LEDC_TypeDef; + + +/** + * @brief Controller Area Network Interface + */ +typedef struct +{ + __IO uint32_t CREQ; /*!< 0x000 CAN Interface Command Request Register */ + __IO uint32_t CMASK; /*!< 0x004 CAN Interface Command Mask Register */ + __IO uint32_t MASK0; /*!< 0x008 CAN Interface Mask Register 0 */ + __IO uint32_t MASK1; /*!< 0x00C CAN Interface Mask Register 1 */ + __IO uint32_t ARB0; /*!< 0x010 CAN Interface Arbitration Register 0 */ + __IO uint32_t ARB1; /*!< 0x014 CAN Interface Arbitration Register 1 */ + __IO uint32_t MCR; /*!< 0x018 CAN Interface Message Control Register */ + __IO uint32_t DA0R; /*!< 0x01C CAN Interface Data A 0 Register */ + __IO uint32_t DA1R; /*!< 0x020 CAN Interface Data A 1 Register */ + __IO uint32_t DB0R; /*!< 0x024 CAN Interface Data B 0 Register */ + __IO uint32_t DB1R; /*!< 0x028 CAN Interface Data B 1 Register */ +} HT_CANIF_TypeDef; + +/** + * @brief Controller Area Network Global + */ +typedef struct +{ + /* CAN: 0x4000C000 */ + __IO uint32_t CR; /*!< 0x000 Control Register */ + __IO uint32_t SR; /*!< 0x004 Status Register */ + __IO uint32_t ECR; /*!< 0x008 Error Counter Register */ + __IO uint32_t BTR; /*!< 0x00C Bit Timing Register */ + __IO uint32_t IR; /*!< 0x010 Interrupt Register */ + __IO uint32_t TR; /*!< 0x014 Test Register */ + __IO uint32_t BRPER; /*!< 0x018 BRP Extension Register */ + uint32_t RESERVED0[1]; /*!< 0x01C Reserved */ + HT_CANIF_TypeDef IF0; /*!< 0x020 - 0x048 CAN Interface 0 registers */ + uint32_t RESERVED1[13];/*!< 0x04C - 0x07C Reserved */ + HT_CANIF_TypeDef IF1; /*!< 0x080 - 0x0A8 CAN Interface 1 registers */ + uint32_t RESERVED2[21];/*!< 0x0AC - 0x0FC Reserved */ + __IO uint32_t TRR0; /*!< 0x100 Transmission Request Register 0 */ + __IO uint32_t TRR1; /*!< 0x104 Transmission Request Register 1 */ + uint32_t RESERVED3[6]; /*!< 0x108 - 0x11C Reserved */ + __IO uint32_t NDR0; /*!< 0x120 New Data Register 0 */ + __IO uint32_t NDR1; /*!< 0x124 New Data Register 1 */ + uint32_t RESERVED4[6]; /*!< 0x128 - 0x13C Reserved */ + __IO uint32_t IPR0; /*!< 0x140 Interrupt Pending Register 0 */ + __IO uint32_t IPR1; /*!< 0x144 Interrupt Pending Register 1 */ + uint32_t RESERVED5[6]; /*!< 0x148 - 0x15C Reserved */ + __IO uint32_t MVR0; /*!< 0x160 Message Valid Register 0 */ + __IO uint32_t MVR1; /*!< 0x164 Message Valid Register 1 */ +} HT_CAN_TypeDef; + +/** + * @brief Coordinate Rotation Digital Computer + */ +typedef struct +{ + /* CORDIC: 0x400DC000 */ + __IO uint32_t CSR; /*!< 0x000 Control/Satus Register */ + __IO uint32_t WDATA; /*!< 0x004 Argument Register */ + __IO uint32_t RDATA; /*!< 0x008 Result Register */ +} HT_CORDIC_TypeDef; + +/** + * @brief Proportional Integral Derivative controller + */ +typedef struct +{ + /* PID: 0x400EC000 */ + __IO uint32_t CR0; /*!< 0x000 Control Register 0 */ + __IO uint32_t UI_INPUT; /*!< 0x004 */ + __IO uint32_t ERR_n; /*!< 0x008 */ + __IO uint32_t PID_OUT; /*!< 0x00C */ + __IO uint32_t SPD1ERR1; /*!< 0x010 */ + __IO uint32_t SPD1KP; /*!< 0x014 */ + __IO uint32_t SPD1KI; /*!< 0x018 */ + __IO uint32_t SPD1KD; /*!< 0x01C */ + __IO uint32_t SPD1UI1; /*!< 0x020 */ + __IO uint32_t SPD1UI_MAX; /*!< 0x024 */ + __IO uint32_t SPD1UI_MIN; /*!< 0x028 */ + __IO uint32_t SPD1_PIDOUT_LIM; /*!< 0x02C */ + __IO uint32_t IQ1ERR1; /*!< 0x030 */ + __IO uint32_t IQ1KP; /*!< 0x034 */ + __IO uint32_t IQ1KI; /*!< 0x038 */ + __IO uint32_t IQ1KD; /*!< 0x03C */ + __IO uint32_t IQ1UI1; /*!< 0x040 */ + __IO uint32_t IQ1UI_MAX; /*!< 0x044 */ + __IO uint32_t IQ1UI_MIN; /*!< 0x048 */ + __IO uint32_t IQ1_PIDOUT_LIM; /*!< 0x04C */ + __IO uint32_t ID1ERR1; /*!< 0x050 */ + __IO uint32_t ID1KP; /*!< 0x054 */ + __IO uint32_t ID1KI; /*!< 0x058 */ + __IO uint32_t ID1KD; /*!< 0x05C */ + __IO uint32_t ID1UI1; /*!< 0x060 */ + __IO uint32_t ID1UI_MAX; /*!< 0x064 */ + __IO uint32_t ID1UI_MIN; /*!< 0x068 */ + __IO uint32_t ID1_PIDOUT_LIM; /*!< 0x06C */ + __IO uint32_t FWNK1ERR1; /*!< 0x070 */ + __IO uint32_t FWNK1KP; /*!< 0x074 */ + __IO uint32_t FWNK1KI; /*!< 0x078 */ + __IO uint32_t FWNK1KD; /*!< 0x07C */ + __IO uint32_t FWNK1UI1; /*!< 0x080 */ + __IO uint32_t FWNK1UI_MAX; /*!< 0x084 */ + __IO uint32_t FWNK1UI_MIN; /*!< 0x088 */ + __IO uint32_t FWNK1_PIDOUT_LIM;/*!< 0x08C */ + __IO uint32_t PLL1ERR1; /*!< 0x090 */ + __IO uint32_t PLL1KP; /*!< 0x094 */ + __IO uint32_t PLL1KI; /*!< 0x098 */ + __IO uint32_t PLL1KD; /*!< 0x09C */ + __IO uint32_t PLL1UI1; /*!< 0x0A0 */ + __IO uint32_t PLL1UI_MAX; /*!< 0x0A4 */ + __IO uint32_t PLL1UI_MIN; /*!< 0x0A8 */ + __IO uint32_t PLL1_PIDOUT_LIM; /*!< 0x0AC */ + __IO uint32_t USR1ERR1; /*!< 0x0B0 */ + __IO uint32_t USR1KP; /*!< 0x0B4 */ + __IO uint32_t USR1KI; /*!< 0x0B8 */ + __IO uint32_t USR1KD; /*!< 0x0BC */ + __IO uint32_t USR1UI1; /*!< 0x0C0 */ + __IO uint32_t USR1UI_MAX; /*!< 0x0C4 */ + __IO uint32_t USR1UI_MIN; /*!< 0x0C8 */ + __IO uint32_t USR1_PIDOUT_LIM; /*!< 0x0CC */ +} HT_PID_TypeDef; +/** + * @} + */ + +/** + * @brief RF + */ +typedef struct +{ + /* RF: 0x400D0000 */ + __IO uint8_t TRXADR0; /*!< 0x000 TX/RX ADDRESS 5BYTES(LSB) */ + __IO uint8_t TRXADR1; /*!< 0x001 TX/RX ADDRESS 5BYTES */ + __IO uint8_t TRXADR2; /*!< 0x002 TX/RX ADDRESS 5BYTES */ + __IO uint8_t TRXADR3; /*!< 0x003 TX/RX ADDRESS 5BYTES */ + __IO uint8_t TRXADR4; /*!< 0x004 TX/RX ADDRESS 5BYTES(MSB) */ + __IO uint8_t RXP1ADR0; /*!< 0x005 RX PIPE1 ADDRESS 5BYTES(LSB) */ + __IO uint8_t RXP1ADR1; /*!< 0x006 RX PIPE1 ADDRESS 5BYTES */ + __IO uint8_t RXP1ADR2; /*!< 0x007 RX PIPE1 ADDRESS 5BYTES */ + __IO uint8_t RXP1ADR3; /*!< 0x008 RX PIPE1 ADDRESS 5BYTES */ + __IO uint8_t RXP1ADR4; /*!< 0x009 RX PIPE1 ADDRESS 5BYTES(MSB) */ + __IO uint8_t RXP2ADR0; /*!< 0x00A RX PIPE2 ADDRESS 5BYTES(LSB) */ + __IO uint8_t RXP3ADR0; /*!< 0x00B RX PIPE3 ADDRESS 5BYTES(LSB) */ + __IO uint8_t RXP4ADR0; /*!< 0x00C RX PIPE4 ADDRESS 5BYTES(LSB) */ + __IO uint8_t RXP5ADR0; /*!< 0x00D RX PIPE5 ADDRESS 5BYTES(LSB) */ + uint8_t RESERVED0[2]; /*!< 0x00E - 0x00F Reserved */ + __IO uint8_t TXFIFO; /*!< 0x010 TX FIFO WRITE ONLY */ + uint8_t RESERVED1[3]; /*!< 0x011 - 0x013 Reserved */ + __IO uint8_t RXFIFO; /*!< 0x014 RX FIFO READ ONLY */ + uint8_t RESERVED2[3]; /*!< 0x015 - 0x017 Reserved */ + __IO uint8_t FWREND; /*!< 0x018 FIFO Read/Write End */ + __IO uint8_t FLUSHFF; /*!< 0x019 FLUSH TX/RX FIFO */ + __IO uint8_t TXFFSEL; /*!< 0x01A Write TX FIFO Select ACK Payload or NACK Payload */ + __IO uint8_t PIPESEL; /*!< 0x01B Write TX FIFO for PIPE ACK Payload */ + __IO uint8_t RFC1; /*!< 0x01C RF Control Register 1 */ + __IO uint8_t RFC2; /*!< 0x01D RF Control Register 2 */ + __IO uint8_t RFC3; /*!< 0x01E RF Control Register 3 */ + uint8_t RESERVED3[1]; /*!< 0x01F Reserved */ + __IO uint8_t CFG1; /*!< 0x020 Configuration Control Register 1 */ + __IO uint8_t RC1; /*!< 0x021 Reset/Clock Control Register 1 */ + __IO uint8_t RC2; /*!< 0x022 Reset/Clock Control Register 2 */ + __IO uint8_t MASK; /*!< 0x023 Mask Control Register */ + __IO uint8_t IRQ1; /*!< 0x024 Interrupt Control Register 1 */ + __IO uint8_t STATUS; /*!< 0x025 FIFO Status Control Register */ + __IO uint8_t IO1; /*!< 0x026 IO Control Register 1 */ + __IO uint8_t IO2; /*!< 0x027 IO Control Register 2 */ + __IO uint8_t IO3; /*!< 0x028 IO Control Register 3 */ + __IO uint8_t PKT1; /*!< 0x029 Packet Control Register 1 */ + __IO uint8_t PKT2; /*!< 0x02A Packet Control Register 2 */ + __IO uint8_t PKT3; /*!< 0x02B Packet Control Register 3 */ + __IO uint8_t PKT4; /*!< 0x02C Packet Control Register 4 */ + __IO uint8_t PKT5; /*!< 0x02D Packet Control Register 5 */ + __IO uint8_t MOD1; /*!< 0x02E Modulator Control Register 1 */ + __IO uint8_t MOD2; /*!< 0x02F Modulator Control Register 2 */ + __IO uint8_t DM1; /*!< 0x030 De-modulator Control Register 1 */ + __IO uint8_t DM2; /*!< 0x031 De-modulator Control Register 2 */ + __IO uint8_t RT1; /*!< 0x032 PTX Retransmission Control Register 1 */ + __IO uint8_t RT2; /*!< 0x033 PTX Retransmission Control Register 2 */ + __IO uint8_t CE; /*!< 0x034 Chip Enable Control Register */ + __IO uint8_t CP21; /*!< 0x035 CP Control Register 21 */ + __IO uint8_t CP22; /*!< 0x036 CP Control Register 22 */ + __IO uint8_t CP31; /*!< 0x037 CP Control Register 31 */ + __IO uint8_t CP2R; /*!< 0x038 CP Control Register 2 for Read */ + __IO uint8_t CP3R; /*!< 0x039 CP Control Register 3 for Read */ + __IO uint8_t CP2RX; /*!< 0x03A CP Control Register 2 for RX */ + __IO uint8_t CP3RX; /*!< 0x03B CP Control Register 3 for RX */ + __IO uint8_t PDB; /*!< 0x03C RF Power Down Bar Enable Control Register */ + __IO uint8_t RF1; /*!< 0x03D RF RX control Register 1 */ + uint8_t RESERVED4[2]; /*!< 0x03E - 0x03F Reserved */ + __IO uint8_t OM; /*!< 0x040 Operation Mode Control Register */ + __IO uint8_t CFO1; /*!< 0x041 Carrier Frequency Offset Control Register 1 */ + __IO uint8_t SX1; /*!< 0x042 Fractional-N Synthesizer Control Register 1 */ + __IO uint8_t SX2; /*!< 0x043 Fractional-N Synthesizer Control Register 2 */ + __IO uint8_t SX3; /*!< 0x044 Fractional-N Synthesizer Control Register 3 */ + __IO uint8_t SX4; /*!< 0x045 Fractional-N Synthesizer Control Register 4 */ + __IO uint8_t STA1; /*!< 0x046 Status Control Register 1 */ + __IO uint8_t RSSI1; /*!< 0x047 RSSI Control Register 1 */ + __IO uint8_t RSSI2; /*!< 0x048 RSSI Control Register 2 */ + __IO uint8_t RSSI3; /*!< 0x049 RSSI Control Register 3 */ + __IO uint8_t DPL1; /*!< 0x04A Dynamic Payload Length Control Register 1 */ + __IO uint8_t DPL2; /*!< 0x04B Dynamic Payload Length Control Register 2 */ + __IO uint8_t RXPW0; /*!< 0x04C RX Payload Length Control Register 0 */ + __IO uint8_t RXPW1; /*!< 0x04D RX Payload Length Control Register 1 */ + __IO uint8_t RXPW2; /*!< 0x04E RX Payload Length Control Register 2 */ + __IO uint8_t RXPW3; /*!< 0x04F RX Payload Length Control Register 3 */ + __IO uint8_t RXPW4; /*!< 0x050 RX Payload Length Control Register 4 */ + __IO uint8_t RXPW5; /*!< 0x051 RX Payload Length Control Register 5 */ + __IO uint8_t ENAA; /*!< 0x052 Enable Auto-ACK Control Register */ + __IO uint8_t PEN; /*!< 0x053 Pipe Enable Control Register */ + __IO uint8_t XO1; /*!< 0x054 XO Control Register 1 */ + __IO uint8_t XO2; /*!< 0x055 XO Control Register 2 */ + __IO uint8_t TXP1; /*!< 0x056 TX Power Control Register 1 */ + __IO uint8_t DM3; /*!< 0x057 De-modulator Control Register 3 */ + __IO uint8_t AGC1; /*!< 0x058 AGC Control Register 1 */ + __IO uint8_t AGC2; /*!< 0x059 AGC Control Register 2 */ + __IO uint8_t AGC3; /*!< 0x05A AGC Control Register 3 */ + __IO uint8_t AGC4; /*!< 0x05B AGC Control Register 4 */ + __IO uint8_t FCF1; /*!< 0x05C Filter Coefficient Control Register 1 */ + __IO uint8_t FCF2; /*!< 0x05D Filter Coefficient Control Register 2 */ + __IO uint8_t FCF3; /*!< 0x05E Filter Coefficient Control Register 3 */ + __IO uint8_t FCF4; /*!< 0x05F Filter Coefficient Control Register 4 */ + __IO uint8_t RXG; /*!< 0x060 RX Gain Control Register */ + __IO uint8_t CP1; /*!< 0x061 CP Control Register 1 */ + __IO uint8_t CP2; /*!< 0x062 CP Control Register 2 */ + __IO uint8_t CP3; /*!< 0x063 CP Control Register 3 */ + __IO uint8_t OD1; /*!< 0x064 MMD and OD Control Register 1 */ + __IO uint8_t OD2; /*!< 0x065 MMD and OD Control Register 2 */ + __IO uint8_t VC1; /*!< 0x066 VCO Control Register 1 */ + __IO uint8_t VC2; /*!< 0x067 VCO Control Register 2 */ + __IO uint8_t VC3; /*!< 0x068 VCO Control Register 3 */ + __IO uint8_t RX1; /*!< 0x069 RX Control Register 1 */ + __IO uint8_t RX2; /*!< 0x06A RX Control Register 2 */ + __IO uint8_t RX3; /*!< 0x06B RX Control Register 3 */ + __IO uint8_t RX4; /*!< 0x06C RX Control Register 4 */ + __IO uint8_t RX5; /*!< 0x06D RX Control Register 5 */ + __IO uint8_t TX1; /*!< 0x06E TX Control Register 1 */ + __IO uint8_t TX2; /*!< 0x06F TX Control Register 2 */ + __IO uint8_t TX3; /*!< 0x070 TX Control Register 3 */ + __IO uint8_t CA1; /*!< 0x071 VCO DFC Calibration Control Register 1 */ + __IO uint8_t CA2; /*!< 0x072 VCO DFC Calibration Control Register 2 */ + __IO uint8_t CA3; /*!< 0x073 VCO DFC Calibration Control Register 3 */ + __IO uint8_t LD1; /*!< 0x074 LDO Control Register 1 */ + __IO uint8_t LD2; /*!< 0x075 LDO Control Register 2 */ + __IO uint8_t LD3; /*!< 0x076 LDO Control Register 3 */ + __IO uint8_t RTM1; /*!< 0x077 RF Test Mode Control Register 1 */ + uint8_t RESERVED5[8]; /*!< 0x078 - 0x07F Reserved */ + __IO uint8_t TEST1; /*!< 0x080 Test Control Register 1 */ + __IO uint8_t TEST2; /*!< 0x081 Test Control Register 2 */ + __IO uint8_t TEST3; /*!< 0x082 Test Control Register 3 */ + __IO uint8_t TEST4; /*!< 0x083 Test Control Register 4 */ + __IO uint8_t TEST5; /*!< 0x084 Test Control Register 5 */ + __IO uint8_t TEST6; /*!< 0x085 Test Control Register 6 */ + __IO uint8_t TEST7; /*!< 0x086 Test Control Register 7 */ +} HT_RF_TypeDef; +/** + * @} + */ + +/** @addtogroup Peripheral_Memory_Map + * @{ + */ + +#define HT_SRAM_BASE (0x20000000UL) + +#define HT_PERIPH_BASE (0x40000000UL) + +#define HT_APBPERIPH_BASE (HT_PERIPH_BASE) /* 0x40000000 */ +#define HT_AHBPERIPH_BASE (HT_PERIPH_BASE + 0x80000) /* 0x40080000 */ + +/* APB */ +#define HT_USART0_BASE (HT_APBPERIPH_BASE + 0x0000) /* 0x40000000 */ +#define HT_UART0_BASE (HT_APBPERIPH_BASE + 0x1000) /* 0x40001000 */ +#define HT_UART2_BASE (HT_APBPERIPH_BASE + 0x2000) /* 0x40002000 */ +#define HT_SPI0_BASE (HT_APBPERIPH_BASE + 0x4000) /* 0x40004000 */ +#define HT_I2C2_BASE (HT_APBPERIPH_BASE + 0x8000) /* 0x40008000 */ +#define HT_CAN0_BASE (HT_APBPERIPH_BASE + 0xC000) /* 0x4000C000 */ +#define HT_SLED0_BASE (HT_APBPERIPH_BASE + 0xE000) /* 0x4000E000 */ +#define HT_ADC0_BASE (HT_APBPERIPH_BASE + 0x10000) /* 0x40010000 */ +#define HT_DAC1_BASE (HT_APBPERIPH_BASE + 0x14000) /* 0x40014000 */ +#define HT_OPA0_BASE (HT_APBPERIPH_BASE + 0x18000) /* 0x40018000 */ +#define HT_PGA0_BASE (HT_APBPERIPH_BASE + 0x18000) /* 0x40018000 */ +#define HT_PGA1_BASE (HT_APBPERIPH_BASE + 0x18008) /* 0x40018008 */ +#define HT_PGA2_BASE (HT_APBPERIPH_BASE + 0x18010) /* 0x40018010 */ +#define HT_PGA3_BASE (HT_APBPERIPH_BASE + 0x18018) /* 0x40018018 */ +#define HT_PGA_BASE (HT_APBPERIPH_BASE + 0x18020) /* 0x40018020 */ +#define HT_OPA1_BASE (HT_APBPERIPH_BASE + 0x18100) /* 0x40018100 */ +#define HT_LCD_BASE (HT_APBPERIPH_BASE + 0x1A000) /* 0x4001A000 */ +#define HT_TKEY_BASE (HT_APBPERIPH_BASE + 0x1A000) /* 0x4001A000 */ +#define HT_AFIO_BASE (HT_APBPERIPH_BASE + 0x22000) /* 0x40022000 */ +#define HT_EXTI_BASE (HT_APBPERIPH_BASE + 0x24000) /* 0x40024000 */ +#define HT_I2S_BASE (HT_APBPERIPH_BASE + 0x26000) /* 0x40026000 */ +#define HT_MCTM0_BASE (HT_APBPERIPH_BASE + 0x2C000) /* 0x4002C000 */ +#define HT_PWM0_BASE (HT_APBPERIPH_BASE + 0x31000) /* 0x40031000 */ +#define HT_SCTM0_BASE (HT_APBPERIPH_BASE + 0x34000) /* 0x40034000 */ +#define HT_PWM2_BASE (HT_APBPERIPH_BASE + 0x32000) /* 0x40031000 */ +#define HT_SCTM2_BASE (HT_APBPERIPH_BASE + 0x35000) /* 0x40035000 */ +#define HT_SCI1_BASE (HT_APBPERIPH_BASE + 0x3A000) /* 0x4003A000 */ +#define HT_USART1_BASE (HT_APBPERIPH_BASE + 0x40000) /* 0x40040000 */ +#define HT_UART1_BASE (HT_APBPERIPH_BASE + 0x41000) /* 0x40041000 */ +#define HT_UART3_BASE (HT_APBPERIPH_BASE + 0x42000) /* 0x40042000 */ +#define HT_SCI0_BASE (HT_APBPERIPH_BASE + 0x43000) /* 0x40043000 */ +#define HT_SPI1_BASE (HT_APBPERIPH_BASE + 0x44000) /* 0x40044000 */ +#define HT_I2C0_BASE (HT_APBPERIPH_BASE + 0x48000) /* 0x40048000 */ +#define HT_I2C1_BASE (HT_APBPERIPH_BASE + 0x49000) /* 0x40049000 */ +#define HT_SLED1_BASE (HT_APBPERIPH_BASE + 0x4E000) /* 0x4004E000 */ +#define HT_ADC1_BASE (HT_APBPERIPH_BASE + 0x50000) /* 0x40050000 */ +#define HT_DACDUAL16_BASE (HT_APBPERIPH_BASE + 0x54000) /* 0x40054000 */ +#define HT_DAC0_BASE (HT_APBPERIPH_BASE + 0x54000) /* 0x40054000 */ +#define HT_CMP0_BASE (HT_APBPERIPH_BASE + 0x58000) /* 0x40058000 */ +#define HT_CMP1_BASE (HT_APBPERIPH_BASE + 0x58100) /* 0x40058100 */ +#define HT_CMP2_BASE (HT_APBPERIPH_BASE + 0x58200) /* 0x40058200 */ +#define HT_LEDC_BASE (HT_APBPERIPH_BASE + 0x5A000) /* 0x4005A000 */ +#define HT_MIDI_BASE (HT_APBPERIPH_BASE + 0x60000) /* 0x40060000 */ +#define HT_WDT_BASE (HT_APBPERIPH_BASE + 0x68000) /* 0x40068000 */ +#define HT_RTC_BASE (HT_APBPERIPH_BASE + 0x6A000) /* 0x4006A000 */ +#define HT_PWRCU_BASE (HT_APBPERIPH_BASE + 0x6A100) /* 0x4006A100 */ +#define HT_GPTM0_BASE (HT_APBPERIPH_BASE + 0x6E000) /* 0x4006E000 */ +#define HT_GPTM1_BASE (HT_APBPERIPH_BASE + 0x6F000) /* 0x4006F000 */ +#define HT_PWM1_BASE (HT_APBPERIPH_BASE + 0x71000) /* 0x40071000 */ +#define HT_SCTM1_BASE (HT_APBPERIPH_BASE + 0x74000) /* 0x40074000 */ +#define HT_SCTM3_BASE (HT_APBPERIPH_BASE + 0x75000) /* 0x40075000 */ +#define HT_BFTM0_BASE (HT_APBPERIPH_BASE + 0x76000) /* 0x40076000 */ +#define HT_BFTM1_BASE (HT_APBPERIPH_BASE + 0x77000) /* 0x40077000 */ + +/* AHB */ +#define HT_FLASH_BASE (HT_AHBPERIPH_BASE + 0x0000) /* 0x40080000 */ +#define HT_CKCU_BASE (HT_AHBPERIPH_BASE + 0x8000) /* 0x40088000 */ +#define HT_RSTCU_BASE (HT_AHBPERIPH_BASE + 0x8100) /* 0x40088100 */ +#define HT_CRC_BASE (HT_AHBPERIPH_BASE + 0xA000) /* 0x4008A000 */ +#define HT_PDMA_BASE (HT_AHBPERIPH_BASE + 0x10000) /* 0x40090000 */ +#define HT_EBI_BASE (HT_AHBPERIPH_BASE + 0x18000) /* 0x40098000 */ +#define HT_USB_BASE (HT_AHBPERIPH_BASE + 0x28000) /* 0x400A8000 */ +#define HT_USB_EP0_BASE (HT_USB_BASE + 0x0014) /* 0x400A8014 */ +#define HT_USB_EP1_BASE (HT_USB_BASE + 0x0028) /* 0x400A8028 */ +#define HT_USB_EP2_BASE (HT_USB_BASE + 0x003C) /* 0x400A803C */ +#define HT_USB_EP3_BASE (HT_USB_BASE + 0x0050) /* 0x400A8050 */ +#define HT_USB_EP4_BASE (HT_USB_BASE + 0x0064) /* 0x400A8064 */ +#define HT_USB_EP5_BASE (HT_USB_BASE + 0x0078) /* 0x400A8078 */ +#define HT_USB_EP6_BASE (HT_USB_BASE + 0x008C) /* 0x400A808C */ +#define HT_USB_EP7_BASE (HT_USB_BASE + 0x00A0) /* 0x400A80A0 */ +#define HT_USB_EP8_BASE (HT_USB_BASE + 0x00B4) /* 0x400A80B4 */ +#define HT_USB_EP9_BASE (HT_USB_BASE + 0x00C8) /* 0x400A80C8 */ +#define HT_USB_SRAM_BASE (HT_AHBPERIPH_BASE + 0x2A000) /* 0x400AA000 */ +#define HT_GPIOA_BASE (HT_AHBPERIPH_BASE + 0x30000) /* 0x400B0000 */ +#define HT_GPIOB_BASE (HT_AHBPERIPH_BASE + 0x32000) /* 0x400B2000 */ +#define HT_GPIOC_BASE (HT_AHBPERIPH_BASE + 0x34000) /* 0x400B4000 */ +#define HT_GPIOD_BASE (HT_AHBPERIPH_BASE + 0x36000) /* 0x400B6000 */ +#define HT_GPIOE_BASE (HT_AHBPERIPH_BASE + 0x38000) /* 0x400B8000 */ +#define HT_GPIOF_BASE (HT_AHBPERIPH_BASE + 0x3A000) /* 0x400BA000 */ +#define HT_AES_BASE (HT_AHBPERIPH_BASE + 0x48000) /* 0x400C8000 */ +#define HT_DIV_BASE (HT_AHBPERIPH_BASE + 0x4A000) /* 0x400CA000 */ +#define HT_RF_BASE (HT_AHBPERIPH_BASE + 0x50000) /* 0x400D0000 */ +#define HT_CORDIC_BASE (HT_AHBPERIPH_BASE + 0x5C000) /* 0x400DC000 */ +#define HT_PID_BASE (HT_AHBPERIPH_BASE + 0x5E000) /* 0x400DE000 */ +#define HT_QSPI_BASE (HT_AHBPERIPH_BASE + 0x60000) /* 0x400E0000 */ + +/** + * @} + */ + +/* Peripheral declaration */ +#define HT_FLASH ((HT_FLASH_TypeDef *) HT_FLASH_BASE) +#define HT_CKCU ((HT_CKCU_TypeDef *) HT_CKCU_BASE) +#define HT_PWRCU ((HT_PWRCU_TypeDef *) HT_PWRCU_BASE) +#define HT_RSTCU ((HT_RSTCU_TypeDef *) HT_RSTCU_BASE) +#define HT_AFIO ((HT_AFIO_TypeDef *) HT_AFIO_BASE) +#define HT_EXTI ((HT_EXTI_TypeDef *) HT_EXTI_BASE) +#define HT_GPIOA ((HT_GPIO_TypeDef *) HT_GPIOA_BASE) +#define HT_GPIOB ((HT_GPIO_TypeDef *) HT_GPIOB_BASE) +#define HT_BFTM0 ((HT_BFTM_TypeDef *) HT_BFTM0_BASE) +#define HT_WDT ((HT_WDT_TypeDef *) HT_WDT_BASE) +#define HT_UART0 ((HT_USART_TypeDef *) HT_UART0_BASE) +#define HT_SPI0 ((HT_SPI_TypeDef *) HT_SPI0_BASE) +#define HT_I2C0 ((HT_I2C_TypeDef *) HT_I2C0_BASE) + +#if !defined(USE_HT32F50020_30) && !defined(USE_HT32F52234_44) +#define HT_GPTM0 ((HT_TM_TypeDef *) HT_GPTM0_BASE) +#endif + +#if !defined(USE_HT32F0008) && !defined(USE_HT32F61141) +#define HT_ADC0 ((HT_ADC_TypeDef *) HT_ADC0_BASE) +#endif + +#if !defined(USE_HT32F0008) && !defined(USE_HT32F50220_30) && !defined(USE_HT32F50231_41) && !defined(USE_HT32F57331_41) && !defined(USE_HT32F53231_41) && !defined(USE_HT32F53242_52) && !defined(USE_HT32F50431_41) && !defined(USE_HT32F50442_52) +#define HT_SCTM0 ((HT_TM_TypeDef *) HT_SCTM0_BASE) +#define HT_SCTM1 ((HT_TM_TypeDef *) HT_SCTM1_BASE) +#endif + +#if defined(USE_HT32F52231_41) || defined(USE_HT32F52331_41) || defined(USE_HT32F52243_53) || defined(USE_HT32F0006) || defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F54243_53) || defined(USE_HT32F50020_30) || defined(USE_HT32F67041_51) || defined(USE_HT32F66242) || defined(USE_HT32F66246) +#define HT_SCTM2 ((HT_TM_TypeDef *) HT_SCTM2_BASE) +#endif + +#if defined(USE_HT32F52231_41) || defined(USE_HT32F52331_41) || defined(USE_HT32F52243_53) || defined(USE_HT32F0006) || defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F54243_53) || defined(USE_HT32F67041_51) || defined(USE_HT32F66242) || defined(USE_HT32F66246) +#define HT_SCTM3 ((HT_TM_TypeDef *) HT_SCTM3_BASE) +#endif + +#if !defined(USE_HT32F50220_30) && !defined(USE_HT32F52344_54) && !defined(USE_HT32F50343) && !defined(USE_HT32F61141) && !defined(USE_HT32F61244_45) && !defined(USE_HT32F50020_30) && !defined(USE_HT32F67041_51) +#define HT_USART0 ((HT_USART_TypeDef *) HT_USART0_BASE) +#endif + +#if defined(USE_HT32F52331_41) || defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F61141) +#define HT_SCI0 ((HT_SCI_TypeDef *) HT_SCI0_BASE) +#endif + +#if defined(USE_HT32F52331_41) || defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F0008) || defined(USE_HT32F52344_54) || defined(USE_HT32F0006) || defined(USE_HT32F52357_67) || defined(USE_HT32F57342_52) || defined(USE_HT32F57331_41) || defined(USE_HT32F50343) || defined(USE_HT32F61141) +#define HT_USB ((HT_USB_TypeDef *) HT_USB_BASE) +#define HT_USBEP0 ((HT_USBEP_TypeDef *) HT_USB_EP0_BASE) +#define HT_USBEP1 ((HT_USBEP_TypeDef *) HT_USB_EP1_BASE) +#define HT_USBEP2 ((HT_USBEP_TypeDef *) HT_USB_EP2_BASE) +#define HT_USBEP3 ((HT_USBEP_TypeDef *) HT_USB_EP3_BASE) +#define HT_USBEP4 ((HT_USBEP_TypeDef *) HT_USB_EP4_BASE) +#define HT_USBEP5 ((HT_USBEP_TypeDef *) HT_USB_EP5_BASE) +#define HT_USBEP6 ((HT_USBEP_TypeDef *) HT_USB_EP6_BASE) +#define HT_USBEP7 ((HT_USBEP_TypeDef *) HT_USB_EP7_BASE) +#endif + +#if defined(USE_HT32F52231_41) || defined(USE_HT32F52331_41) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#endif + +#if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_GPTM1 ((HT_TM_TypeDef *) HT_GPTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_SCI1 ((HT_SCI_TypeDef *) HT_SCI1_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#endif + +#if defined(USE_HT32F52243_53) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_UART2 ((HT_USART_TypeDef *) HT_UART2_BASE) +#define HT_UART3 ((HT_USART_TypeDef *) HT_UART3_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_I2C2 ((HT_I2C_TypeDef *) HT_I2C2_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#endif + +#if defined(USE_HT32F0008) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_AES ((HT_AES_TypeDef *) HT_AES_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOF ((HT_GPIO_TypeDef *) HT_GPIOF_BASE) +#endif + +#if defined(USE_HT32F50220_30) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#endif + +#if defined(USE_HT32F50231_41) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#endif + +#if defined(USE_HT32F52344_54) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#endif + +#if defined(USE_HT32F0006) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_QSPI ((HT_SPI_TypeDef *) HT_QSPI_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_DACDUAL16 ((HT_DAC_DUAL16_TypeDef *) HT_DACDUAL16_BASE) +#define HT_MIDI ((HT_MIDI_TypeDef *) HT_MIDI_BASE) +#endif + +#if defined(USE_HT32F52357_67) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_DAC0 ((HT_DAC_TypeDef *) HT_DAC0_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_SCI1 ((HT_SCI_TypeDef *) HT_SCI1_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_UART2 ((HT_USART_TypeDef *) HT_UART2_BASE) +#define HT_UART3 ((HT_USART_TypeDef *) HT_UART3_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_QSPI ((HT_SPI_TypeDef *) HT_QSPI_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_AES ((HT_AES_TypeDef *) HT_AES_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_GPIOE ((HT_GPIO_TypeDef *) HT_GPIOE_BASE) +#endif + +#if defined(USE_HT32F57342_52) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_DAC0 ((HT_DAC_TypeDef *) HT_DAC0_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_SCI1 ((HT_SCI_TypeDef *) HT_SCI1_BASE) +#define HT_I2S ((HT_I2S_TypeDef *) HT_I2S_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_AES ((HT_AES_TypeDef *) HT_AES_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_GPIOE ((HT_GPIO_TypeDef *) HT_GPIOE_BASE) +#define HT_LCD ((HT_LCD_TypeDef *) HT_LCD_BASE) +#endif + +#if defined(USE_HT32F57331_41) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_LCD ((HT_LCD_TypeDef *) HT_LCD_BASE) +#endif + +#if defined(USE_HT32F65230_40) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_ADC1 ((HT_ADC_TypeDef *) HT_ADC1_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_CMP2 ((HT_CMP_TypeDef *) HT_CMP2_BASE) +#define HT_OPA0 ((HT_OPA_TypeDef *) HT_OPA0_BASE) +#define HT_OPA1 ((HT_OPA_TypeDef *) HT_OPA1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#endif + +#if defined(USE_HT32F65232) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_OPA0 ((HT_OPA_TypeDef *) HT_OPA0_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#endif + +#if defined(USE_HT32F50343) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_PWM2 ((HT_TM_TypeDef *) HT_PWM2_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_SLED0 ((HT_SLED_TypeDef *) HT_SLED0_BASE) +#define HT_SLED1 ((HT_SLED_TypeDef *) HT_SLED1_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#endif + +#if defined(USE_HT32F54231_41) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_TKEY ((HT_TKEY_TypeDef *) HT_TKEY_BASE) +#define HT_LEDC ((HT_LEDC_TypeDef *) HT_LEDC_BASE) +#endif + +#if defined(USE_HT32F54243_53) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_UART2 ((HT_USART_TypeDef *) HT_UART2_BASE) +#define HT_UART3 ((HT_USART_TypeDef *) HT_UART3_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_I2C2 ((HT_I2C_TypeDef *) HT_I2C2_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_TKEY ((HT_TKEY_TypeDef *) HT_TKEY_BASE) +#define HT_LEDC ((HT_LEDC_TypeDef *) HT_LEDC_BASE) +#endif + +#if defined(USE_HT32F61141) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SCI1 ((HT_SCI_TypeDef *) HT_SCI1_BASE) +#define HT_USBEP8 ((HT_USBEP_TypeDef *) HT_USB_EP8_BASE) +#define HT_USBEP9 ((HT_USBEP_TypeDef *) HT_USB_EP9_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#endif + +#if defined(USE_HT32F61244_45) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_LSTM0 ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#define HT_QSPI ((HT_SPI_TypeDef *) HT_QSPI_BASE) +#define HT_DACDUAL16 ((HT_DAC_DUAL16_TypeDef *) HT_DACDUAL16_BASE) +#define HT_MIDI ((HT_MIDI_TypeDef *) HT_MIDI_BASE) + +#define HT_RTC HT_LSTM0 +#endif + +#if defined(USE_HT32F50020_30) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOF ((HT_GPIO_TypeDef *) HT_GPIOF_BASE) +#define HT_LEDC ((HT_LEDC_TypeDef *) HT_LEDC_BASE) +#endif + +#if defined(USE_HT32F67041_51) +#define HT_AES ((HT_AES_TypeDef *) HT_AES_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_RF ((HT_RF_TypeDef *) HT_RF_BASE) +#endif + +#if defined(USE_HT32F50442_52) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_LEDC ((HT_LEDC_TypeDef *) HT_LEDC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#endif + +#if defined(USE_HT32F50431_41) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_LEDC ((HT_LEDC_TypeDef *) HT_LEDC_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#endif + +#if defined(USE_HT32F53242_52) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_PWM1 ((HT_TM_TypeDef *) HT_PWM1_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_EBI ((HT_EBI_TypeDef *) HT_EBI_BASE) +#define HT_USART1 ((HT_USART_TypeDef *) HT_USART1_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_LEDC ((HT_LEDC_TypeDef *) HT_LEDC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_CAN0 ((HT_CAN_TypeDef *) HT_CAN0_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#endif + +#if defined(USE_HT32F53231_41) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_UART1 ((HT_USART_TypeDef *) HT_UART1_BASE) +#define HT_SPI1 ((HT_SPI_TypeDef *) HT_SPI1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_LEDC ((HT_LEDC_TypeDef *) HT_LEDC_BASE) +#define HT_CAN0 ((HT_CAN_TypeDef *) HT_CAN0_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_GPIOD ((HT_GPIO_TypeDef *) HT_GPIOD_BASE) +#endif + +#if defined(USE_HT32F66242) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_PGA0 ((HT_PGA0_X_TypeDef *) HT_PGA0_BASE) +#define HT_PGA1 ((HT_PGA0_X_TypeDef *) HT_PGA1_BASE) +#define HT_PGA2 ((HT_PGA0_X_TypeDef *) HT_PGA2_BASE) +#define HT_PGA3 ((HT_PGA0_X_TypeDef *) HT_PGA3_BASE) +#define HT_PGA ((HT_PGA_TypeDef *) HT_PGA_BASE) +#define HT_PID ((HT_LCD_TypeDef *) HT_LCD_BASE) +#define HT_CORDIC ((HT_CORDIC_TypeDef *) HT_CORDIC_BASE) +#define HT_LSTM0 ((HT_RTC_TypeDef *) HT_RTC_BASE) + +#define HT_RTC HT_LSTM0 +#endif + +#if defined(USE_HT32F66246) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_CMP0 ((HT_CMP_TypeDef *) HT_CMP0_BASE) +#define HT_CMP1 ((HT_CMP_TypeDef *) HT_CMP1_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_MCTM0 ((HT_TM_TypeDef *) HT_MCTM0_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#define HT_CAN0 ((HT_CAN_TypeDef *) HT_CAN0_BASE) +#define HT_PGA0 ((HT_PGA0_X_TypeDef *) HT_PGA0_BASE) +#define HT_PGA1 ((HT_PGA0_X_TypeDef *) HT_PGA1_BASE) +#define HT_PGA2 ((HT_PGA0_X_TypeDef *) HT_PGA2_BASE) +#define HT_PGA3 ((HT_PGA0_X_TypeDef *) HT_PGA3_BASE) +#define HT_PGA ((HT_PGA_TypeDef *) HT_PGA_BASE) +#define HT_PID ((HT_LCD_TypeDef *) HT_LCD_BASE) +#define HT_CORDIC ((HT_CORDIC_TypeDef *) HT_CORDIC_BASE) +#define HT_LSTM0 ((HT_RTC_TypeDef *) HT_RTC_BASE) + +#define HT_RTC HT_LSTM0 +#endif + +#if defined(USE_HT32F52234_44) +#define HT_PDMA ((HT_PDMA_TypeDef *) HT_PDMA_BASE) +#define HT_BFTM1 ((HT_BFTM_TypeDef *) HT_BFTM1_BASE) +#define HT_PWM0 ((HT_TM_TypeDef *) HT_PWM0_BASE) +#define HT_DAC0 ((HT_DAC_TypeDef *) HT_DAC0_BASE) +#define HT_DAC1 ((HT_DAC_TypeDef *) HT_DAC1_BASE) +#define HT_I2C1 ((HT_I2C_TypeDef *) HT_I2C1_BASE) +#define HT_I2C2 ((HT_I2C_TypeDef *) HT_I2C2_BASE) +#define HT_RTC ((HT_RTC_TypeDef *) HT_RTC_BASE) +#define HT_CRC ((HT_CRC_TypeDef *) HT_CRC_BASE) +#define HT_DIV ((HT_DIV_TypeDef *) HT_DIV_BASE) +#define HT_GPIOC ((HT_GPIO_TypeDef *) HT_GPIOC_BASE) +#endif + +#if defined USE_HT32_DRIVER + #include "ht32f5xxxx_lib.h" +#endif + +/** + * @brief Adjust the value of High Speed External oscillator (HSE) + Tip: To avoid from modifying every time for different HSE, please define + the "HSE_VALUE=n000000" ("n" represents n MHz) in your own toolchain compiler preprocessor, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + */ +#if !defined HSE_VALUE + #if defined(USE_HT32F50220_30) || defined(USE_HT32F50231_41) + /* Available HSE_VALUE: 4 MHz ~ 20 MHz */ + #define HSE_VALUE 20000000UL /*!< Value of the External oscillator in Hz */ + #elif defined(USE_HT32F50020_30) + /* Available HSE_VALUE: 4 MHz ~ 16 MHz */ + #define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */ + #elif defined(USE_HT32F0006) + /* Available HSE_VALUE: 4 MHz ~ 16 MHz */ + #define HSE_VALUE 12000000UL /*!< Value of the External oscillator in Hz */ + #elif defined(USE_HT32F61244_45) + /* Available HSE_VALUE: 4 MHz ~ 16 MHz */ + #define HSE_VALUE 12000000UL /*!< Value of the External oscillator in Hz */ + #elif defined(USE_HT32F67041_51) + /* Available HSE_VALUE: 16 MHz */ + #define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */ + #else + /* Available HSE_VALUE: 4 MHz ~ 16 MHz */ + #define HSE_VALUE 8000000UL /*!< Value of the External oscillator in Hz */ + #endif +#endif + +/** + * @brief Define for backward compatibility + */ +#define HT_ADC HT_ADC0 +#define ADC ADC0 +#define ADC_IRQn ADC0_IRQn + +#define HT_DAC HT_DAC0 +#define AFIO_FUN_DAC AFIO_FUN_DAC0 +#define CKCU_PCLK_DAC CKCU_PCLK_DAC0 + +#if defined(USE_HT32F52357_67) + #define UART0_IRQn UART0_UART2_IRQn + #define UART2_IRQn UART0_UART2_IRQn + #define UART1_IRQn UART1_UART3_IRQn + #define UART3_IRQn UART1_UART3_IRQn +#endif + +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) + // Alias + #define GPTM0_IRQn GPTM0_G_IRQn + #define GPTM0_IRQHandler GPTM0_G_IRQHandler + #define MCTM0_IRQn MCTM0_UP_IRQn + #define MCTM0_IRQHandler MCTM0_G_IRQHandler + #define MCTM1_IRQn MCTM1_UP_IRQn + #define MCTM1_IRQHandler MCTM1_G_IRQHandler +#endif + +#define AFIO_ESS_Enum u32 + +#if 0 // Set as 1 for backward compatibility +#if defined(USE_HT32F50020_30) +#define EXTI8_IRQn EXTI0_1_IRQn +#define EXTI9_IRQn EXTI0_1_IRQn +#define EXTI10_IRQn EXTI2_3_IRQn +#define EXTI11_IRQn EXTI2_3_IRQn +#define EXTI12_IRQn EXTI4_7_IRQn +#define EXTI13_IRQn EXTI4_7_IRQn +#define EXTI14_IRQn EXTI4_7_IRQn +#define EXTI15_IRQn EXTI4_7_IRQn + +#define EXTI_CHANNEL_8 EXTI_CHANNEL_0 +#define EXTI_CHANNEL_9 EXTI_CHANNEL_1 +#define EXTI_CHANNEL_10 EXTI_CHANNEL_2 +#define EXTI_CHANNEL_11 EXTI_CHANNEL_3 +#define EXTI_CHANNEL_12 EXTI_CHANNEL_4 +#define EXTI_CHANNEL_13 EXTI_CHANNEL_5 +#define EXTI_CHANNEL_14 EXTI_CHANNEL_6 +#define EXTI_CHANNEL_15 EXTI_CHANNEL_7 +#endif +#endif + +#if (LIBCFG_SPI_NO_MULTI_MASTER) +#define SPI_SELOutputCmd(...) +#endif + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f0006.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f0006.h new file mode 100644 index 00000000000..388963ffe1f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f0006.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f0006.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F0006 Device + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F0006_H +#define __SYSTEM_HT32F0006_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F0006_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F0006_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5826.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5826.h new file mode 100644 index 00000000000..a1f54a57cae --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5826.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5826.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5826_H +#define __SYSTEM_HT32F5826_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_01.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_01.h new file mode 100644 index 00000000000..bf83db51625 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_01.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_01.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_01_H +#define __SYSTEM_HT32F5XXXX_01_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_02.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_02.h new file mode 100644 index 00000000000..cffecbeac6d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_02.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_02.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_02_H +#define __SYSTEM_HT32F5XXXX_02_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_03.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_03.h new file mode 100644 index 00000000000..35c215726d8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_03.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_03.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_03_H +#define __SYSTEM_HT32F5XXXX_03_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_04.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_04.h new file mode 100644 index 00000000000..7ddd2dc9d98 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_04.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_04.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_04_H +#define __SYSTEM_HT32F5XXXX_04_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_05.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_05.h new file mode 100644 index 00000000000..c0ead9e7d52 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_05.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_05.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_05_H +#define __SYSTEM_HT32F5XXXX_05_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_06.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_06.h new file mode 100644 index 00000000000..e8600c85bbe --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_06.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_06.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_06_H +#define __SYSTEM_HT32F5XXXX_06_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_07.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_07.h new file mode 100644 index 00000000000..30a451c6c1d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_07.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_07.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_07_H +#define __SYSTEM_HT32F5XXXX_07_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_08.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_08.h new file mode 100644 index 00000000000..5f982d45b9f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_08.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_08.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_08_H +#define __SYSTEM_HT32F5XXXX_08_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_09.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_09.h new file mode 100644 index 00000000000..85528c095c3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_09.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_09.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_09_H +#define __SYSTEM_HT32F5XXXX_09_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_10.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_10.h new file mode 100644 index 00000000000..8ae7e67c9e9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_10.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_10.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_10_H +#define __SYSTEM_HT32F5XXXX_10_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_11.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_11.h new file mode 100644 index 00000000000..c9a7e04c33a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_11.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_11.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_11_H +#define __SYSTEM_HT32F5XXXX_11_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_12.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_12.h new file mode 100644 index 00000000000..0f4983569ea --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_12.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_12.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_12_H +#define __SYSTEM_HT32F5XXXX_12_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_13.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_13.h new file mode 100644 index 00000000000..8176285eea8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_13.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_13.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_13_H +#define __SYSTEM_HT32F5XXXX_13_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_14.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_14.h new file mode 100644 index 00000000000..042adba38de --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_14.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_14.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_14_H +#define __SYSTEM_HT32F5XXXX_14_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_15.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_15.h new file mode 100644 index 00000000000..f6d6fc17874 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_15.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_15.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_15_H +#define __SYSTEM_HT32F5XXXX_15_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_16.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_16.h new file mode 100644 index 00000000000..ca845b0ea3a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_16.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_16.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_16_H +#define __SYSTEM_HT32F5XXXX_16_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_17.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_17.h new file mode 100644 index 00000000000..ecf72bd705a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_17.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_17.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 1725 $ + * @date $Date:: 2017-08-24 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_17_H +#define __SYSTEM_HT32F5XXXX_17_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_18.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_18.h new file mode 100644 index 00000000000..73ba94f18a7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Include/system_ht32f5xxxx_18.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file system_ht32f5xxxx_18.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 7408 $ + * @date $Date:: 2023-12-14 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for use with Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system + * @{ + */ + + +#ifndef __SYSTEM_HT32F5XXXX_18_H +#define __SYSTEM_HT32F5XXXX_18_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_System_Exported_types + * @{ + */ +extern __IO uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + * @} + */ + + +/** @addtogroup HT32F5xxxx_System_Exported_Functions + * @{ + */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_hf5032.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_hf5032.s new file mode 100644 index 00000000000..a86606d9663 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_hf5032.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 7 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0006.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0006.s new file mode 100644 index 00000000000..e0b5ba76e21 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0006.s @@ -0,0 +1,304 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_07.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +USE_HT32_CHIP_SET EQU 10 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00061355 +;_HT32FWID EQU 0x00061356 +;_HT32FWID EQU 0x00061357 + +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT32F61355_56_57 EQU 17 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0008.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0008.s new file mode 100644 index 00000000000..db72cb363fa --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f0008.s @@ -0,0 +1,403 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_03.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +USE_HT32_CHIP_SET EQU 6 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052142 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00052357 +;_HT32FWID EQU 0x00052367 +;_HT32FWID EQU 0x0003200F + +HT32F0008 EQU 6 +HT32F52142 EQU 6 +HT32F52344_54 EQU 9 +HT32F52357_67 EQU 11 +HT50F3200T EQU 11 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD AES_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD QSPI_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52357_67) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_UART2_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_UART3_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD SCI_IRQHandler ; 27, 43, 0xAC, + ELSE + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART0_UART2_IRQHandler [WEAK] + EXPORT UART1_UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART0_UART2_IRQHandler +UART1_UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50020_30.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50020_30.s new file mode 100644 index 00000000000..45853e20f1f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50020_30.s @@ -0,0 +1,235 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +USE_HT32_CHIP_SET EQU 25 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050020 +;_HT32FWID EQU 0x00050030 +;_HT32FWID EQU 0x00061630 +;_HT32FWID EQU 0x00061030 + +HT32F50020_30 EQU 25 +HT32F61630 EQU 25 +HT32F61030 EQU 25 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-2048:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-2048:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_7_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD _RESERVED ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_7_IRQHandler +ADC_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +BFTM0_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50220_30.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50220_30.s new file mode 100644 index 00000000000..a86606d9663 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50220_30.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 7 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50231_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50231_41.s new file mode 100644 index 00000000000..8e689529096 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50231_41.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 8 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50343.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50343.s new file mode 100644 index 00000000000..1a58d66e73b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50343.s @@ -0,0 +1,298 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_06.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50343 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <15=> HT32F50343 +USE_HT32_CHIP_SET EQU 15 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050343 + +HT32F50343 EQU 15 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-12288:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-12288:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD PWM2_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SLED0_IRQHandler ; 27, 43, 0x0AC, + DCD SLED1_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SLED0_IRQHandler [WEAK] + EXPORT SLED1_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +PWM2_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SLED0_IRQHandler +SLED1_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50431_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50431_41.s new file mode 100644 index 00000000000..be3f3ca0f7f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50431_41.s @@ -0,0 +1,264 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_14.s +; Version : $Rev:: 6793 $ +; Date : $Date:: 2023-03-14 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50442, HT32F50452 +; HT32F50431, HT32F50441 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <26=> HT32F50442/52 +;// <30=> HT32F50431/41 +USE_HT32_CHIP_SET EQU 30 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050442 +;_HT32FWID EQU 0x00050452 +;_HT32FWID EQU 0x00050431 +;_HT32FWID EQU 0x00050441 + +HT32F50442_52 EQU 26 +HT32F50431_41 EQU 30 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50442_52.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50442_52.s new file mode 100644 index 00000000000..214cdf9e323 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f50442_52.s @@ -0,0 +1,264 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_14.s +; Version : $Rev:: 6793 $ +; Date : $Date:: 2023-03-14 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50442, HT32F50452 +; HT32F50431, HT32F50441 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <26=> HT32F50442/52 +;// <30=> HT32F50431/41 +USE_HT32_CHIP_SET EQU 26 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050442 +;_HT32FWID EQU 0x00050452 +;_HT32FWID EQU 0x00050431 +;_HT32FWID EQU 0x00050441 + +HT32F50442_52 EQU 26 +HT32F50431_41 EQU 30 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52142.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52142.s new file mode 100644 index 00000000000..db72cb363fa --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52142.s @@ -0,0 +1,403 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_03.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +USE_HT32_CHIP_SET EQU 6 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052142 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00052357 +;_HT32FWID EQU 0x00052367 +;_HT32FWID EQU 0x0003200F + +HT32F0008 EQU 6 +HT32F52142 EQU 6 +HT32F52344_54 EQU 9 +HT32F52357_67 EQU 11 +HT50F3200T EQU 11 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD AES_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD QSPI_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52357_67) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_UART2_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_UART3_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD SCI_IRQHandler ; 27, 43, 0xAC, + ELSE + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART0_UART2_IRQHandler [WEAK] + EXPORT UART1_UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART0_UART2_IRQHandler +UART1_UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52220_30.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52220_30.s new file mode 100644 index 00000000000..ae562b2a89a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52220_30.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52231_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52231_41.s new file mode 100644 index 00000000000..c653285b1f2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52231_41.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 2 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52234_44.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52234_44.s new file mode 100644 index 00000000000..9f80e3bd0eb --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52234_44.s @@ -0,0 +1,239 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_17.s +; Version : $Rev:: 7027 $ +; Date : $Date:: 2023-07-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52234, HT32F52244 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <33=> HT32F52234/44 +USE_HT32_CHIP_SET EQU 33 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052234 +;_HT32FWID EQU 0x00052244 + +HT32F52234_44 EQU 33 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD DAC0_1_IRQHandler ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD I2C2_IRQHandler ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DAC0_1_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DAC0_1_IRQHandler +ADC_IRQHandler +I2C2_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52243_53.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52243_53.s new file mode 100644 index 00000000000..e9b3a2c1946 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52243_53.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 5 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52331_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52331_41.s new file mode 100644 index 00000000000..8cd61fd13a8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52331_41.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 3 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52342_52.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52342_52.s new file mode 100644 index 00000000000..2285fed9c8b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52342_52.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 4 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52344_54.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52344_54.s new file mode 100644 index 00000000000..e745eaa8033 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52344_54.s @@ -0,0 +1,403 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_03.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +USE_HT32_CHIP_SET EQU 9 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052142 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00052357 +;_HT32FWID EQU 0x00052367 +;_HT32FWID EQU 0x0003200F + +HT32F0008 EQU 6 +HT32F52142 EQU 6 +HT32F52344_54 EQU 9 +HT32F52357_67 EQU 11 +HT50F3200T EQU 11 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD AES_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD QSPI_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52357_67) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_UART2_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_UART3_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD SCI_IRQHandler ; 27, 43, 0xAC, + ELSE + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART0_UART2_IRQHandler [WEAK] + EXPORT UART1_UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART0_UART2_IRQHandler +UART1_UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52357_67.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52357_67.s new file mode 100644 index 00000000000..4533138d126 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f52357_67.s @@ -0,0 +1,403 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_03.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +USE_HT32_CHIP_SET EQU 11 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052142 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00052357 +;_HT32FWID EQU 0x00052367 +;_HT32FWID EQU 0x0003200F + +HT32F0008 EQU 6 +HT32F52142 EQU 6 +HT32F52344_54 EQU 9 +HT32F52357_67 EQU 11 +HT50F3200T EQU 11 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD AES_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD QSPI_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52357_67) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_UART2_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_UART3_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD SCI_IRQHandler ; 27, 43, 0xAC, + ELSE + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART0_UART2_IRQHandler [WEAK] + EXPORT UART1_UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART0_UART2_IRQHandler +UART1_UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53231_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53231_41.s new file mode 100644 index 00000000000..e1bc80febe4 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53231_41.s @@ -0,0 +1,266 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_15.s +; Version : $Rev:: 6874 $ +; Date : $Date:: 2023-05-03 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F53242, HT32F53252 +; HT32F53231, HT32F53241 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <28=> HT32F53242/52 +;// <29=> HT32F53231/41 +USE_HT32_CHIP_SET EQU 29 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00053242 +;_HT32FWID EQU 0x00053252 +;_HT32FWID EQU 0x00053231 +;_HT32FWID EQU 0x00053241 + +HT32F53242_52 EQU 28 +HT32F53231_41 EQU 29 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD CAN0_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +CAN0_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53242_52.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53242_52.s new file mode 100644 index 00000000000..f4dbd9cf62f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f53242_52.s @@ -0,0 +1,266 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_15.s +; Version : $Rev:: 6874 $ +; Date : $Date:: 2023-05-03 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F53242, HT32F53252 +; HT32F53231, HT32F53241 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <28=> HT32F53242/52 +;// <29=> HT32F53231/41 +USE_HT32_CHIP_SET EQU 28 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00053242 +;_HT32FWID EQU 0x00053252 +;_HT32FWID EQU 0x00053231 +;_HT32FWID EQU 0x00053241 + +HT32F53242_52 EQU 28 +HT32F53231_41 EQU 29 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD CAN0_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +CAN0_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54231_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54231_41.s new file mode 100644 index 00000000000..5db17956e76 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54231_41.s @@ -0,0 +1,343 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_09.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F54231, HT32F54241 +; HT32F54243, HT32F54253 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <19=> HT32F54231/41 +;// <20=> HT32F54243/53 +USE_HT32_CHIP_SET EQU 19 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00054231 +;_HT32FWID EQU 0x00054241 +;_HT32FWID EQU 0x00054243 +;_HT32FWID EQU 0x00054253 + +HT32F54231_41 EQU 19 +HT32F54243_53 EQU 20 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD TKEY_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F54243_53) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT TKEY_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +I2C2_IRQHandler +MCTM0_IRQHandler +TKEY_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54243_53.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54243_53.s new file mode 100644 index 00000000000..657d0d65230 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f54243_53.s @@ -0,0 +1,343 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_09.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F54231, HT32F54241 +; HT32F54243, HT32F54253 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <19=> HT32F54231/41 +;// <20=> HT32F54243/53 +USE_HT32_CHIP_SET EQU 20 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00054231 +;_HT32FWID EQU 0x00054241 +;_HT32FWID EQU 0x00054243 +;_HT32FWID EQU 0x00054253 + +HT32F54231_41 EQU 19 +HT32F54243_53 EQU 20 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD TKEY_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F54243_53) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT TKEY_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +I2C2_IRQHandler +MCTM0_IRQHandler +TKEY_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57331_41.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57331_41.s new file mode 100644 index 00000000000..cbaf7f3ee16 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57331_41.s @@ -0,0 +1,350 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 13 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57342_52.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57342_52.s new file mode 100644 index 00000000000..b1d916864c8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f57342_52.s @@ -0,0 +1,350 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 14 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5826.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5826.s new file mode 100644 index 00000000000..eba919c13e5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5826.s @@ -0,0 +1,311 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5826.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F5826 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F5826 +USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00005826 + +HT32F5826 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD COMP_IRQHandler ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5828.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5828.s new file mode 100644 index 00000000000..b1d916864c8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5828.s @@ -0,0 +1,350 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 14 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59041.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59041.s new file mode 100644 index 00000000000..8e689529096 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59041.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 8 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59046.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59046.s new file mode 100644 index 00000000000..8e689529096 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59046.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 8 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59741.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59741.s new file mode 100644 index 00000000000..cbaf7f3ee16 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59741.s @@ -0,0 +1,350 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 13 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59746.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59746.s new file mode 100644 index 00000000000..cbaf7f3ee16 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f59746.s @@ -0,0 +1,350 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 13 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_01.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_01.s new file mode 100644 index 00000000000..b11048b5e03 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_01.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_02.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_02.s new file mode 100644 index 00000000000..de2009c868d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_02.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_03.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_03.s new file mode 100644 index 00000000000..1ff2f77f4b7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_03.s @@ -0,0 +1,403 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_03.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052142 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00052357 +;_HT32FWID EQU 0x00052367 +;_HT32FWID EQU 0x0003200F + +HT32F0008 EQU 6 +HT32F52142 EQU 6 +HT32F52344_54 EQU 9 +HT32F52357_67 EQU 11 +HT50F3200T EQU 11 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD AES_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD QSPI_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52357_67) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_UART2_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_UART3_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD SCI_IRQHandler ; 27, 43, 0xAC, + ELSE + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART0_UART2_IRQHandler [WEAK] + EXPORT UART1_UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART0_UART2_IRQHandler +UART1_UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_05.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_05.s new file mode 100644 index 00000000000..842644ceee5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_05.s @@ -0,0 +1,350 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_06.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_06.s new file mode 100644 index 00000000000..bf17a58ce71 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_06.s @@ -0,0 +1,298 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_06.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50343 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <15=> HT32F50343 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050343 + +HT32F50343 EQU 15 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-12288:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-12288:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD PWM2_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SLED0_IRQHandler ; 27, 43, 0x0AC, + DCD SLED1_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT PWM2_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SLED0_IRQHandler [WEAK] + EXPORT SLED1_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +PWM2_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SLED0_IRQHandler +SLED1_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_07.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_07.s new file mode 100644 index 00000000000..10f210c5a27 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_07.s @@ -0,0 +1,304 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_07.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00061355 +;_HT32FWID EQU 0x00061356 +;_HT32FWID EQU 0x00061357 + +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT32F61355_56_57 EQU 17 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_08.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_08.s new file mode 100644 index 00000000000..24cf68758d8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_08.s @@ -0,0 +1,278 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_08.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; MXTX6306 +; HT50F3200S + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> MXTX6306 +;// <12=> HT50F3200S +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00065230 +;_HT32FWID EQU 0x00065240 +;_HT32FWID EQU 0x00065232 +;_HT32FWID EQU 0x00006306 +;_HT32FWID EQU 0x0003200F + +HT32F65230_40 EQU 12 +HT32F65232 EQU 18 +MXTX6306 EQU 12 +HT50F3200S EQU 12 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_9_IRQHandler ; 06, 22, 0x058, + DCD EXTI10_15_IRQHandler ; 07, 23, 0x05C, + DCD ADC0_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD ADC1_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD CMP2_IRQHandler ; 20, 36, 0x090, + ELSE + DCD _RESERVED ; 20, 36, 0x090, + ENDIF + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_9_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_9_IRQHandler +EXTI10_15_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_09.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_09.s new file mode 100644 index 00000000000..089c851eb17 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_09.s @@ -0,0 +1,343 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_09.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F54231, HT32F54241 +; HT32F54243, HT32F54253 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <19=> HT32F54231/41 +;// <20=> HT32F54243/53 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00054231 +;_HT32FWID EQU 0x00054241 +;_HT32FWID EQU 0x00054243 +;_HT32FWID EQU 0x00054253 + +HT32F54231_41 EQU 19 +HT32F54243_53 EQU 20 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD TKEY_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F54243_53) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT TKEY_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +I2C2_IRQHandler +MCTM0_IRQHandler +TKEY_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_10.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_10.s new file mode 100644 index 00000000000..57fb44e3145 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_10.s @@ -0,0 +1,235 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_10.s +; Version : $Rev:: 5783 $ +; Date : $Date:: 2022-03-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F61244, HT32F61245 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <24=> HT32F61244/45 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00061244 +;_HT32FWID EQU 0x00061245 + +HT32F61244_45 EQU 24 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_11.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_11.s new file mode 100644 index 00000000000..784096cf664 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_11.s @@ -0,0 +1,245 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_11.s +; Version : $Rev:: 5991 $ +; Date : $Date:: 2022-06-23 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F67041, HT32F67051 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <22=> HT32F67041/51 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00067041 +;_HT32FWID EQU 0x00067051 + +HT32F67041_51 EQU 22 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD AES_IRQHandler ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD RF_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT RF_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +AES_IRQHandler +RF_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_12.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_12.s new file mode 100644 index 00000000000..45e5c701091 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_12.s @@ -0,0 +1,278 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_12.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F61141 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <23=> HT32F61141 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00061141 + +HT32F61141 EQU 23 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD _RESERVED ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +USB_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_13.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_13.s new file mode 100644 index 00000000000..f03c345a43d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_13.s @@ -0,0 +1,235 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050020 +;_HT32FWID EQU 0x00050030 +;_HT32FWID EQU 0x00061630 +;_HT32FWID EQU 0x00061030 + +HT32F50020_30 EQU 25 +HT32F61630 EQU 25 +HT32F61030 EQU 25 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-2048:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-2048:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_7_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD _RESERVED ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_7_IRQHandler +ADC_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +BFTM0_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_14.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_14.s new file mode 100644 index 00000000000..a76b5da417b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_14.s @@ -0,0 +1,264 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_14.s +; Version : $Rev:: 6793 $ +; Date : $Date:: 2023-03-14 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50442, HT32F50452 +; HT32F50431, HT32F50441 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <26=> HT32F50442/52 +;// <30=> HT32F50431/41 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050442 +;_HT32FWID EQU 0x00050452 +;_HT32FWID EQU 0x00050431 +;_HT32FWID EQU 0x00050441 + +HT32F50442_52 EQU 26 +HT32F50431_41 EQU 30 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_15.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_15.s new file mode 100644 index 00000000000..e261fa60210 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_15.s @@ -0,0 +1,266 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_15.s +; Version : $Rev:: 6874 $ +; Date : $Date:: 2023-05-03 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F53242, HT32F53252 +; HT32F53231, HT32F53241 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <28=> HT32F53242/52 +;// <29=> HT32F53231/41 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00053242 +;_HT32FWID EQU 0x00053252 +;_HT32FWID EQU 0x00053231 +;_HT32FWID EQU 0x00053241 + +HT32F53242_52 EQU 28 +HT32F53231_41 EQU 29 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD CAN0_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +CAN0_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_16.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_16.s new file mode 100644 index 00000000000..23328ec7c45 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_16.s @@ -0,0 +1,275 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_16.s +; Version : $Rev:: 7092 $ +; Date : $Date:: 2023-08-02 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F66242 +; HT32F66246 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + + + + + + + +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +;_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00066246 + +HT32F66246 EQU 31 +HT32F66242 EQU 33 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + + IF (USE_HT32_CHIP=0) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66246) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66242) +_HT32FWID EQU 0x00066242 + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F66246) + DCD CAN0_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD CORDIC_IRQHandler ; 09, 25, 0x064, + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + DCD PID_IRQHandler ; 20, 36, 0x090, + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT PID_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +CAN0_IRQHandler +ADC_IRQHandler +CORDIC_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +PID_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_17.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_17.s new file mode 100644 index 00000000000..0829021a82f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f5xxxx_17.s @@ -0,0 +1,239 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_17.s +; Version : $Rev:: 7027 $ +; Date : $Date:: 2023-07-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52234, HT32F52244 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <33=> HT32F52234/44 +USE_HT32_CHIP_SET EQU 0 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052234 +;_HT32FWID EQU 0x00052244 + +HT32F52234_44 EQU 33 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD DAC0_1_IRQHandler ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD I2C2_IRQHandler ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DAC0_1_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DAC0_1_IRQHandler +ADC_IRQHandler +I2C2_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61030.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61030.s new file mode 100644 index 00000000000..45853e20f1f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61030.s @@ -0,0 +1,235 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +USE_HT32_CHIP_SET EQU 25 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050020 +;_HT32FWID EQU 0x00050030 +;_HT32FWID EQU 0x00061630 +;_HT32FWID EQU 0x00061030 + +HT32F50020_30 EQU 25 +HT32F61630 EQU 25 +HT32F61030 EQU 25 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-2048:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-2048:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_7_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD _RESERVED ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_7_IRQHandler +ADC_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +BFTM0_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61041.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61041.s new file mode 100644 index 00000000000..8e689529096 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61041.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 8 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61141.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61141.s new file mode 100644 index 00000000000..e01651cc145 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61141.s @@ -0,0 +1,278 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_12.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F61141 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <23=> HT32F61141 +USE_HT32_CHIP_SET EQU 23 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00061141 + +HT32F61141 EQU 23 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD _RESERVED ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +USB_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61244_45.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61244_45.s new file mode 100644 index 00000000000..5477d2e2554 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61244_45.s @@ -0,0 +1,235 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_10.s +; Version : $Rev:: 5783 $ +; Date : $Date:: 2022-03-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F61244, HT32F61245 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <24=> HT32F61244/45 +USE_HT32_CHIP_SET EQU 24 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00061244 +;_HT32FWID EQU 0x00061245 + +HT32F61244_45 EQU 24 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61352.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61352.s new file mode 100644 index 00000000000..e0b5ba76e21 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61352.s @@ -0,0 +1,304 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_07.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +USE_HT32_CHIP_SET EQU 10 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00061355 +;_HT32FWID EQU 0x00061356 +;_HT32FWID EQU 0x00061357 + +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT32F61355_56_57 EQU 17 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61355_56_57.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61355_56_57.s new file mode 100644 index 00000000000..418bcfd86f8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61355_56_57.s @@ -0,0 +1,304 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_07.s +; Version : $Rev:: 5740 $ +; Date : $Date:: 2022-02-17 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +USE_HT32_CHIP_SET EQU 17 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00061355 +;_HT32FWID EQU 0x00061356 +;_HT32FWID EQU 0x00061357 + +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT32F61355_56_57 EQU 17 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61630.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61630.s new file mode 100644 index 00000000000..45853e20f1f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61630.s @@ -0,0 +1,235 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +USE_HT32_CHIP_SET EQU 25 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050020 +;_HT32FWID EQU 0x00050030 +;_HT32FWID EQU 0x00061630 +;_HT32FWID EQU 0x00061030 + +HT32F50020_30 EQU 25 +HT32F61630 EQU 25 +HT32F61030 EQU 25 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-2048:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-2048:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_7_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD _RESERVED ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT LEDC_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_7_IRQHandler +ADC_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +BFTM0_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61641.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61641.s new file mode 100644 index 00000000000..8e689529096 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f61641.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 8 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62030.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62030.s new file mode 100644 index 00000000000..ae562b2a89a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62030.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62040.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62040.s new file mode 100644 index 00000000000..c653285b1f2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62040.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 2 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62050.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62050.s new file mode 100644 index 00000000000..e9b3a2c1946 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f62050.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 5 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65230_40.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65230_40.s new file mode 100644 index 00000000000..b9865368094 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65230_40.s @@ -0,0 +1,278 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_08.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; MXTX6306 +; HT50F3200S + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> MXTX6306 +;// <12=> HT50F3200S +USE_HT32_CHIP_SET EQU 12 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00065230 +;_HT32FWID EQU 0x00065240 +;_HT32FWID EQU 0x00065232 +;_HT32FWID EQU 0x00006306 +;_HT32FWID EQU 0x0003200F + +HT32F65230_40 EQU 12 +HT32F65232 EQU 18 +MXTX6306 EQU 12 +HT50F3200S EQU 12 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_9_IRQHandler ; 06, 22, 0x058, + DCD EXTI10_15_IRQHandler ; 07, 23, 0x05C, + DCD ADC0_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD ADC1_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD CMP2_IRQHandler ; 20, 36, 0x090, + ELSE + DCD _RESERVED ; 20, 36, 0x090, + ENDIF + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_9_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_9_IRQHandler +EXTI10_15_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65232.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65232.s new file mode 100644 index 00000000000..0ec4ece850d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f65232.s @@ -0,0 +1,278 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_08.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; MXTX6306 +; HT50F3200S + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> MXTX6306 +;// <12=> HT50F3200S +USE_HT32_CHIP_SET EQU 18 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00065230 +;_HT32FWID EQU 0x00065240 +;_HT32FWID EQU 0x00065232 +;_HT32FWID EQU 0x00006306 +;_HT32FWID EQU 0x0003200F + +HT32F65230_40 EQU 12 +HT32F65232 EQU 18 +MXTX6306 EQU 12 +HT50F3200S EQU 12 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_9_IRQHandler ; 06, 22, 0x058, + DCD EXTI10_15_IRQHandler ; 07, 23, 0x05C, + DCD ADC0_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD ADC1_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD CMP2_IRQHandler ; 20, 36, 0x090, + ELSE + DCD _RESERVED ; 20, 36, 0x090, + ENDIF + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_9_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_9_IRQHandler +EXTI10_15_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66242.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66242.s new file mode 100644 index 00000000000..d2f753c1156 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66242.s @@ -0,0 +1,275 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_16.s +; Version : $Rev:: 7092 $ +; Date : $Date:: 2023-08-02 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F66242 +; HT32F66246 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + + + + + + + +USE_HT32_CHIP_SET EQU 33 ; Notice that the project's Asm Define has the higher priority. + +;_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00066246 + +HT32F66246 EQU 31 +HT32F66242 EQU 33 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + + IF (USE_HT32_CHIP=0) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66246) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66242) +_HT32FWID EQU 0x00066242 + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F66246) + DCD CAN0_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD CORDIC_IRQHandler ; 09, 25, 0x064, + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + DCD PID_IRQHandler ; 20, 36, 0x090, + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT PID_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +CAN0_IRQHandler +ADC_IRQHandler +CORDIC_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +PID_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66246.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66246.s new file mode 100644 index 00000000000..9a02335cc69 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f66246.s @@ -0,0 +1,275 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_16.s +; Version : $Rev:: 7092 $ +; Date : $Date:: 2023-08-02 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F66242 +; HT32F66246 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + + + + + + + +USE_HT32_CHIP_SET EQU 31 ; Notice that the project's Asm Define has the higher priority. + +;_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00066246 + +HT32F66246 EQU 31 +HT32F66242 EQU 33 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + + IF (USE_HT32_CHIP=0) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66246) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66242) +_HT32FWID EQU 0x00066242 + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F66246) + DCD CAN0_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD CORDIC_IRQHandler ; 09, 25, 0x064, + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + DCD PID_IRQHandler ; 20, 36, 0x090, + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT PID_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +CAN0_IRQHandler +ADC_IRQHandler +CORDIC_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +PID_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67041_51.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67041_51.s new file mode 100644 index 00000000000..13c68a18eca --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67041_51.s @@ -0,0 +1,245 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_11.s +; Version : $Rev:: 5991 $ +; Date : $Date:: 2022-06-23 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F67041, HT32F67051 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <22=> HT32F67041/51 +USE_HT32_CHIP_SET EQU 22 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00067041 +;_HT32FWID EQU 0x00067051 + +HT32F67041_51 EQU 22 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD AES_IRQHandler ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD RF_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT RF_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +AES_IRQHandler +RF_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67232.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67232.s new file mode 100644 index 00000000000..ae562b2a89a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67232.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67233.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67233.s new file mode 100644 index 00000000000..ae562b2a89a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67233.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 1 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67741.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67741.s new file mode 100644 index 00000000000..c653285b1f2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67741.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 2 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67742.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67742.s new file mode 100644 index 00000000000..cbaf7f3ee16 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht32f67742.s @@ -0,0 +1,350 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 13 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32002.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32002.s new file mode 100644 index 00000000000..a86606d9663 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32002.s @@ -0,0 +1,327 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 7 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-4096:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-4096:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32003.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32003.s new file mode 100644 index 00000000000..2285fed9c8b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f32003.s @@ -0,0 +1,482 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 4 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM1_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT MIDI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200s.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200s.s new file mode 100644 index 00000000000..b9865368094 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200s.s @@ -0,0 +1,278 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_08.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; MXTX6306 +; HT50F3200S + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> MXTX6306 +;// <12=> HT50F3200S +USE_HT32_CHIP_SET EQU 12 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00065230 +;_HT32FWID EQU 0x00065240 +;_HT32FWID EQU 0x00065232 +;_HT32FWID EQU 0x00006306 +;_HT32FWID EQU 0x0003200F + +HT32F65230_40 EQU 12 +HT32F65232 EQU 18 +MXTX6306 EQU 12 +HT50F3200S EQU 12 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_9_IRQHandler ; 06, 22, 0x058, + DCD EXTI10_15_IRQHandler ; 07, 23, 0x05C, + DCD ADC0_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD ADC1_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD CMP2_IRQHandler ; 20, 36, 0x090, + ELSE + DCD _RESERVED ; 20, 36, 0x090, + ENDIF + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_9_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_9_IRQHandler +EXTI10_15_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200t.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200t.s new file mode 100644 index 00000000000..4533138d126 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_ht50f3200t.s @@ -0,0 +1,403 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_03.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +USE_HT32_CHIP_SET EQU 11 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052142 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00052357 +;_HT32FWID EQU 0x00052367 +;_HT32FWID EQU 0x0003200F + +HT32F0008 EQU 6 +HT32F52142 EQU 6 +HT32F52344_54 EQU 9 +HT32F52357_67 EQU 11 +HT50F3200T EQU 11 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-16384:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-16384:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD AES_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD QSPI_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52357_67) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_UART2_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_UART3_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD SCI_IRQHandler ; 27, 43, 0xAC, + ELSE + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +BootProcess PROC + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT COMP_DAC_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT MCTM0_IRQHandler [WEAK] + EXPORT GPTM0_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART0_UART2_IRQHandler [WEAK] + EXPORT UART1_UART3_IRQHandler [WEAK] + EXPORT SCI_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_5_IRQHandler [WEAK] + +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART0_UART2_IRQHandler +UART1_UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx6306.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx6306.s new file mode 100644 index 00000000000..b9865368094 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ARM/startup_mxtx6306.s @@ -0,0 +1,278 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_08.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; MXTX6306 +; HT50F3200S + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// Select HT32 Device for the assembly setting. +;// Notice that the project's Asm Define has the higher priority. +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> MXTX6306 +;// <12=> HT50F3200S +USE_HT32_CHIP_SET EQU 12 ; Notice that the project's Asm Define has the higher priority. + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00065230 +;_HT32FWID EQU 0x00065240 +;_HT32FWID EQU 0x00065232 +;_HT32FWID EQU 0x00006306 +;_HT32FWID EQU 0x0003200F + +HT32F65230_40 EQU 12 +HT32F65232 EQU 18 +MXTX6306 EQU 12 +HT50F3200S EQU 12 + + IF USE_HT32_CHIP_SET=0 + ; Use project's Asm Define setting (default) + ELSE + IF :DEF:USE_HT32_CHIP + ; Use project's Asm Define setting (higher priority than the "USE_HT32_CHIP_SET") + ELSE + ; Use "USE_HT32_CHIP_SET" in the "startup_ht32xxxxx_xx.s" file +USE_HT32_CHIP EQU USE_HT32_CHIP_SET + ENDIF + ENDIF + +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <0-8192:8> +Stack_Size EQU 512 + + AREA STACK, NOINIT, READWRITE, ALIGN = 3 +__HT_check_sp +Stack_Mem SPACE Stack_Size +__initial_sp + +;// Heap Size (in Bytes) <0-8192:8> +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN = 3 +__HT_check_heap +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + AREA RESET, CODE, READONLY + EXPORT __Vectors +_RESERVED EQU 0xFFFFFFFF +__Vectors + DCD __initial_sp ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_9_IRQHandler ; 06, 22, 0x058, + DCD EXTI10_15_IRQHandler ; 07, 23, 0x05C, + DCD ADC0_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD ADC1_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD CMP2_IRQHandler ; 20, 36, 0x090, + ELSE + DCD _RESERVED ; 20, 36, 0x090, + ENDIF + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT LVD_BOD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EVWUP_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_9_IRQHandler [WEAK] + EXPORT EXTI10_15_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT MCTM0_BRK_IRQHandler [WEAK] + EXPORT MCTM0_UP_IRQHandler [WEAK] + EXPORT MCTM0_TR_UP2_IRQHandler [WEAK] + EXPORT MCTM0_CC_IRQHandler [WEAK] + EXPORT GPTM0_G_IRQHandler [WEAK] + EXPORT GPTM0_VCLK_IRQHandler [WEAK] + EXPORT BFTM0_IRQHandler [WEAK] + EXPORT BFTM1_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT PDMA_CH0_1_IRQHandler [WEAK] + EXPORT PDMA_CH2_3_IRQHandler [WEAK] + EXPORT PDMA_CH4_5_IRQHandler [WEAK] + EXPORT SCTM0_IRQHandler [WEAK] + EXPORT SCTM1_IRQHandler [WEAK] + EXPORT SCTM2_IRQHandler [WEAK] + EXPORT SCTM3_IRQHandler [WEAK] +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_9_IRQHandler +EXTI10_15_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __HT_check_heap + EXPORT __HT_check_sp + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_01.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_01.s new file mode 100644 index 00000000000..13adc8cdcc3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_01.s @@ -0,0 +1,461 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00052220 + .equ _HT32FWID, 0x00052230 + .equ _HT32FWID, 0x00052231 + .equ _HT32FWID, 0x00052241 + .equ _HT32FWID, 0x00052331 + .equ _HT32FWID, 0x00052341 + .equ _HT32FWID, 0x00052342 + .equ _HT32FWID, 0x00052352 + .equ _HT32FWID, 0x00052243 + .equ _HT32FWID, 0x00052253 + .equ _HT32FWID, 0x00000008 + .equ _HT32FWID, 0x00052344 + .equ _HT32FWID, 0x00052354 + .equ _HT32FWID, 0x00000006 + .equ _HT32FWID, 0x00061352 + .equ _HT32FWID, 0x00032003 + .equ _HT32FWID, 0x00062030 + .equ _HT32FWID, 0x00062040 + .equ _HT32FWID, 0x00062050 + .equ _HT32FWID, 0x00067741 + .equ _HT32FWID, 0x00067232 + .equ _HT32FWID, 0x00067233 +*/ + + .equ HT32F52220_30, 1 + .equ HT32F52231_41, 2 + .equ HT32F52331_41, 3 + .equ HT32F52342_52, 4 + .equ HT32F52243_53, 5 + .equ HT32F0008, 6 + .equ HT32F52344_54, 9 + .equ HT32F0006, 10 + .equ HT32F61352, 10 + .equ HT50F32003, 4 + .equ HT32F62030, 1 + .equ HT32F62040, 2 + .equ HT32F62050, 5 + .equ HT32F67741, 2 + .equ HT32F67232, 1 + .equ HT32F67233, 1 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .if (USE_HT32_CHIP==HT32F52220_30) + .long _RESERVED /* 01, 17, 0x044, */ + .else + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .endif + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52344_54) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 08, 24, 0x060, */ + .else + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) + .long GPTM1_IRQHandler /* 11, 27, 0x06C, */ + .else + .long _RESERVED /* 11, 27, 0x06C, */ + .endif + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .else + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F52231_41) || (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52243_53) || (USE_HT32_CHIP==HT32F0006) + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .if (USE_HT32_CHIP==HT32F52220_30) + .long _RESERVED /* 18, 34, 0x088, */ + .else + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .endif + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 22, 38, 0x098, */ + .else + .if (USE_HT32_CHIP==HT32F0006) + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .else + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .endif + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52243_53) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 26, 42, 0x0A8, */ + .else + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52342_52) + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long UART2_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0006) + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 27, 43, 0xAC, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F0006) + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long UART3_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long AES_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long _RESERVED /* 29, 45, 0x0B4, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52243_53) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM1_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ SCI_IRQHandler + IRQ MIDI_IRQHandler + IRQ I2S_IRQHandler + IRQ AES_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_02.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_02.s new file mode 100644 index 00000000000..1521f84226f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_02.s @@ -0,0 +1,324 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050220 + .equ _HT32FWID, 0x00050230 + .equ _HT32FWID, 0x00050231 + .equ _HT32FWID, 0x00050241 + .equ _HT32FWID, 0x00032002 + .equ _HT32FWID, 0x00059041 + .equ _HT32FWID, 0x000F5032 + .equ _HT32FWID, 0x00061641 + .equ _HT32FWID, 0x00059046 + .equ _HT32FWID, 0x00061041 +*/ + + .equ HT32F50220_30, 7 + .equ HT32F50231_41, 8 + .equ HT50F32002, 7 + .equ HT32F59041, 8 + .equ HF5032, 7 + .equ HT32F61641, 8 + .equ HT32F59046, 8 + .equ HT32F61041, 8 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 18, 34, 0x088, */ + .else + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .endif + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_03.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_03.s new file mode 100644 index 00000000000..1f2906d7606 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_03.s @@ -0,0 +1,386 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_03.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00000008 + .equ _HT32FWID, 0x00052142 + .equ _HT32FWID, 0x00052344 + .equ _HT32FWID, 0x00052354 + .equ _HT32FWID, 0x00052357 + .equ _HT32FWID, 0x00052367 + .equ _HT32FWID, 0x0003200F +*/ + + .equ HT32F0008, 6 + .equ HT32F52142, 6 + .equ HT32F52344_54, 9 + .equ HT32F52357_67, 11 + .equ HT50F3200T, 11 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long COMP_DAC_IRQHandler /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 08, 24, 0x060, */ + .else + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long AES_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long QSPI_IRQHandler /* 11, 27, 0x06C, */ + .else + .long _RESERVED /* 11, 27, 0x06C, */ + .endif + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .else + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52357_67) + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 22, 38, 0x098, */ + .else + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .long UART0_UART2_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_UART3_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .else + .long _RESERVED /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long AES_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ COMP_DAC_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART0_UART2_IRQHandler + IRQ UART1_UART3_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ AES_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_05.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_05.s new file mode 100644 index 00000000000..1618d4b1c0c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_05.s @@ -0,0 +1,338 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00057331 + .equ _HT32FWID, 0x00057341 + .equ _HT32FWID, 0x00057342 + .equ _HT32FWID, 0x00057352 + .equ _HT32FWID, 0x00059741 + .equ _HT32FWID, 0x00005828 + .equ _HT32FWID, 0x00067742 + .equ _HT32FWID, 0x00059746 +*/ + + .equ HT32F57331_41, 13 + .equ HT32F57342_52, 14 + .equ HT32F59741, 13 + .equ HT32F5828, 14 + .equ HT32F67742, 13 + .equ HT32F59746, 13 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long COMP_DAC_IRQHandler /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long AES_IRQHandler /* 09, 25, 0x064, */ + .endif + .long _RESERVED /* 10, 26, 0x068, */ + .long LCD_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 30, 46, 0x0B8, */ + .long _RESERVED /* 31, 47, 0x0BC, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ COMP_DAC_IRQHandler + IRQ ADC_IRQHandler + IRQ AES_IRQHandler + IRQ LCD_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_06.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_06.s new file mode 100644 index 00000000000..f7788dc2174 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_06.s @@ -0,0 +1,289 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_06.s +; Version : $Rev:: 4141 $ +; Date : $Date:: 2019-07-24 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50343 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <15=> HT32F50343 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050343 +*/ + + .equ HT32F50343, 15 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long PWM2_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SLED0_IRQHandler /* 27, 43, 0x0AC, */ + .long SLED1_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ PWM2_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SLED0_IRQHandler + IRQ SLED1_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_07.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_07.s new file mode 100644 index 00000000000..2ecf7587575 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_07.s @@ -0,0 +1,296 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_07.s +; Version : $Rev:: 5157 $ +; Date : $Date:: 2021-01-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00000006 + .equ _HT32FWID, 0x00061352 + .equ _HT32FWID, 0x00061355 + .equ _HT32FWID, 0x00061356 + .equ _HT32FWID, 0x00061357 +*/ + + .equ HT32F0006, 10 + .equ HT32F61352, 10 + .equ HT32F61355_56_57, 17 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ MIDI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_08.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_08.s new file mode 100644 index 00000000000..3c0ee31039e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_08.s @@ -0,0 +1,258 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_08.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; HT50F3200S +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> HT50F3200S +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00065230 + .equ _HT32FWID, 0x00065240 + .equ _HT32FWID, 0x00065232 + .equ _HT32FWID, 0x0003200F +*/ + + .equ HT32F65230_40, 12 + .equ HT32F65232, 18 + .equ HT50F3200S, 12 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_9_IRQHandler /* 06, 22, 0x058, */ + .long EXTI10_15_IRQHandler /* 07, 23, 0x05C, */ + .long ADC0_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F65230_40) + .long ADC1_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .long MCTM0_BRK_IRQHandler /* 10, 26, 0x068, */ + .long MCTM0_UP_IRQHandler /* 11, 27, 0x06C, */ + .long MCTM0_TR_UP2_IRQHandler /* 12, 28, 0x070, */ + .long MCTM0_CC_IRQHandler /* 13, 29, 0x074, */ + .long GPTM0_G_IRQHandler /* 14, 30, 0x078, */ + .long GPTM0_VCLK_IRQHandler /* 15, 31, 0x07C, */ + .long BFTM0_IRQHandler /* 16, 32, 0x080, */ + .long BFTM1_IRQHandler /* 17, 33, 0x084, */ + .long CMP0_IRQHandler /* 18, 34, 0x088, */ + .long CMP1_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F65230_40) + .long CMP2_IRQHandler /* 20, 36, 0x090, */ + .else + .long _RESERVED /* 20, 36, 0x090, */ + .endif + .long I2C0_IRQHandler /* 21, 37, 0x094, */ + .long SPI0_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long UART0_IRQHandler /* 24, 40, 0x0A0, */ + .long PDMA_CH0_1_IRQHandler /* 25, 41, 0x0A4, */ + .long PDMA_CH2_3_IRQHandler /* 26, 42, 0x0A8, */ + .long PDMA_CH4_5_IRQHandler /* 27, 43, 0x0AC, */ + .long SCTM0_IRQHandler /* 28, 44, 0x0B0, */ + .long SCTM1_IRQHandler /* 29, 45, 0x0B4, */ + .long SCTM2_IRQHandler /* 30, 46, 0x0B8, */ + .long SCTM3_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_9_IRQHandler + IRQ EXTI10_15_IRQHandler + IRQ ADC0_IRQHandler + IRQ ADC1_IRQHandler + IRQ MCTM0_BRK_IRQHandler + IRQ MCTM0_UP_IRQHandler + IRQ MCTM0_TR_UP2_IRQHandler + IRQ MCTM0_CC_IRQHandler + IRQ GPTM0_G_IRQHandler + IRQ GPTM0_VCLK_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ CMP2_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_3_IRQHandler + IRQ PDMA_CH4_5_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_09.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_09.s new file mode 100644 index 00000000000..f30b6881fb2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_09.s @@ -0,0 +1,329 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_09.s +; Version : $Rev:: 6206 $ +; Date : $Date:: 2022-10-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F54231, HT32F54241 +; HT32F54243, HT32F54253 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <19=> HT32F54231/41 +;// <20=> HT32F54243/53 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00054231 + .equ _HT32FWID, 0x00054241 + .equ _HT32FWID, 0x00054243 + .equ _HT32FWID, 0x00054253 +*/ + + .equ HT32F54231_41, 19 + .equ HT32F54243_53, 20 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .endif + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long TKEY_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long UART2_IRQHandler /* 27, 43, 0x0AC, */ + .long UART3_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .if (USE_HT32_CHIP==HT32F54243_53) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ I2C2_IRQHandler + IRQ MCTM0_IRQHandler + IRQ TKEY_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_10.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_10.s new file mode 100644 index 00000000000..c2fb7bd0281 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_10.s @@ -0,0 +1,230 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_10.s +; Version : $Rev:: 6601 $ +; Date : $Date:: 2022-12-27 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F61244, HT32F61245 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <24=> HT32F61244/45 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00061244 + .equ _HT32FWID, 0x00061245 +*/ + + .equ HT32F61244_45, 24 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART0_IRQHandler + IRQ MIDI_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_11.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_11.s new file mode 100644 index 00000000000..465d0db99d3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_11.s @@ -0,0 +1,235 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_11.s +; Version : $Rev:: 6206 $ +; Date : $Date:: 2022-10-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F67041, HT32F67051 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <22=> HT32F67041/51 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00067041 + .equ _HT32FWID, 0x00067051 +*/ + + .equ HT32F67041_51, 22 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long AES_IRQHandler /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long RF_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ AES_IRQHandler + IRQ RF_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_12.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_12.s new file mode 100644 index 00000000000..0e1001014c9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_12.s @@ -0,0 +1,278 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_12.s +; Version : $Rev:: 6206 $ +; Date : $Date:: 2022-10-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F61141 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <23=> HT32F61141 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00061141 +*/ + + .equ HT32F61141, 23 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long _RESERVED /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSL R1, R1, #4 + LSR R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ USB_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_13.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_13.s new file mode 100644 index 00000000000..649b402684f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_13.s @@ -0,0 +1,234 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050020 + .equ _HT32FWID, 0x00050030 + .equ _HT32FWID, 0x00061630 + .equ _HT32FWID, 0x00061030 +*/ + + .equ HT32F50020_30, 25 + .equ HT32F61630, 25 + .equ HT32F61030, 25 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_7_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long _RESERVED /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long _RESERVED /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_7_IRQHandler + IRQ ADC_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ BFTM0_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ LEDC_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_14.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_14.s new file mode 100644 index 00000000000..335d485622b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_14.s @@ -0,0 +1,254 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_14.s +; Version : $Rev:: 6793 $ +; Date : $Date:: 2023-03-14 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50442, HT32F50452 +; HT32F50431, HT32F50441 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <26=> HT32F50442/52 +;// <30=> HT32F50431/41 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050442 + .equ _HT32FWID, 0x00050452 + .equ _HT32FWID, 0x00050431 + .equ _HT32FWID, 0x00050441 +*/ + + .equ HT32F50442_52, 26 + .equ HT32F50431_41, 30 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .else + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_15.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_15.s new file mode 100644 index 00000000000..304bfbd8035 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_15.s @@ -0,0 +1,255 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_15.s +; Version : $Rev:: 6902 $ +; Date : $Date:: 2023-05-08 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F53242, HT32F53252 +; HT32F53231, HT32F53241 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <28=> HT32F53242/52 +;// <29=> HT32F53231/41 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00053242 + .equ _HT32FWID, 0x00053252 + .equ _HT32FWID, 0x00053231 + .equ _HT32FWID, 0x00053241 +*/ + + .equ HT32F53242_52, 28 + .equ HT32F53231_41, 29 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .else + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long CAN0_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ CAN0_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_16.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_16.s new file mode 100644 index 00000000000..01f644a0a3b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_16.s @@ -0,0 +1,259 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_16.s +; Version : $Rev:: 7094 $ +; Date : $Date:: 2023-08-02 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F66242 +; HT32F66246 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* + + + + +*/ + .equ USE_HT32_CHIP_SET, 0 + +/* + .equ _HT32FWID, 0xFFFFFFFF + .equ _HT32FWID, 0x00066246 +*/ + + .equ HT32F66246, 31 + .equ HT32F66242, 33 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .if USE_HT32_CHIP == 0 + .equ _HT32FWID, 0x00066246 + .endif + .if USE_HT32_CHIP == HT32F66246 + .equ _HT32FWID, 0x00066246 + .endif + .if USE_HT32_CHIP == HT32F66242 + .equ _HT32FWID, 0x00066242 + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F66246) + .long CAN0_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long CORDIC_IRQHandler /* 09, 25, 0x064, */ + .long MCTM0_BRK_IRQHandler /* 10, 26, 0x068, */ + .long MCTM0_UP_IRQHandler /* 11, 27, 0x06C, */ + .long MCTM0_TR_UP2_IRQHandler /* 12, 28, 0x070, */ + .long MCTM0_CC_IRQHandler /* 13, 29, 0x074, */ + .long GPTM0_G_IRQHandler /* 14, 30, 0x078, */ + .long GPTM0_VCLK_IRQHandler /* 15, 31, 0x07C, */ + .long BFTM0_IRQHandler /* 16, 32, 0x080, */ + .long BFTM1_IRQHandler /* 17, 33, 0x084, */ + .long CMP0_IRQHandler /* 18, 34, 0x088, */ + .long CMP1_IRQHandler /* 19, 35, 0x08C, */ + .long PID_IRQHandler /* 20, 36, 0x090, */ + .long I2C0_IRQHandler /* 21, 37, 0x094, */ + .long SPI0_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long UART0_IRQHandler /* 24, 40, 0x0A0, */ + .long PDMA_CH0_1_IRQHandler /* 25, 41, 0x0A4, */ + .long PDMA_CH2_3_IRQHandler /* 26, 42, 0x0A8, */ + .long PDMA_CH4_5_IRQHandler /* 27, 43, 0x0AC, */ + .long SCTM0_IRQHandler /* 28, 44, 0x0B0, */ + .long SCTM1_IRQHandler /* 29, 45, 0x0B4, */ + .long SCTM2_IRQHandler /* 30, 46, 0x0B8, */ + .long SCTM3_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ CAN0_IRQHandler + IRQ ADC_IRQHandler + IRQ CORDIC_IRQHandler + IRQ MCTM0_BRK_IRQHandler + IRQ MCTM0_UP_IRQHandler + IRQ MCTM0_TR_UP2_IRQHandler + IRQ MCTM0_CC_IRQHandler + IRQ GPTM0_G_IRQHandler + IRQ GPTM0_VCLK_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ PID_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_3_IRQHandler + IRQ PDMA_CH4_5_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_17.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_17.s new file mode 100644 index 00000000000..47dac68db7d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/CodeSourcery/startup_ht32f5xxxx_cs3_17.s @@ -0,0 +1,233 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_cs3_17.s +; Version : $Rev:: 7030 $ +; Date : $Date:: 2023-07-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F52234, HT32F52244 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <33=> HT32F52234/44 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00052234 + .equ _HT32FWID, 0x00052244 +*/ + + .equ HT32F52234_44, 33 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack + .globl __cs3_stack_size + .globl __HT_check_sp +__HT_check_sp: +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif +__cs3_stack: + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end + .globl __HT_check_heap +__HT_check_heap: +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* ---, 00, 0x000, Top address of Stack */ + .long __cs3_reset /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long DAC0_1_IRQHandler /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long _RESERVED /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0, =_start + BX R0 + .thumb_func + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ DAC0_1_IRQHandler + IRQ ADC_IRQHandler + IRQ I2C2_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s new file mode 100644 index 00000000000..6ef935fb93a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_01.s @@ -0,0 +1,519 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00052220 + .equ _HT32FWID, 0x00052230 + .equ _HT32FWID, 0x00052231 + .equ _HT32FWID, 0x00052241 + .equ _HT32FWID, 0x00052331 + .equ _HT32FWID, 0x00052341 + .equ _HT32FWID, 0x00052342 + .equ _HT32FWID, 0x00052352 + .equ _HT32FWID, 0x00052243 + .equ _HT32FWID, 0x00052253 + .equ _HT32FWID, 0x00000008 + .equ _HT32FWID, 0x00052344 + .equ _HT32FWID, 0x00052354 + .equ _HT32FWID, 0x00000006 + .equ _HT32FWID, 0x00061352 + .equ _HT32FWID, 0x00032003 + .equ _HT32FWID, 0x00062030 + .equ _HT32FWID, 0x00062040 + .equ _HT32FWID, 0x00062050 + .equ _HT32FWID, 0x00067741 + .equ _HT32FWID, 0x00067232 + .equ _HT32FWID, 0x00067233 +*/ + + .equ HT32F52220_30, 1 + .equ HT32F52231_41, 2 + .equ HT32F52331_41, 3 + .equ HT32F52342_52, 4 + .equ HT32F52243_53, 5 + .equ HT32F0008, 6 + .equ HT32F52344_54, 9 + .equ HT32F0006, 10 + .equ HT32F61352, 10 + .equ HT50F32003, 4 + .equ HT32F62030, 1 + .equ HT32F62040, 2 + .equ HT32F62050, 5 + .equ HT32F67741, 2 + .equ HT32F67232, 1 + .equ HT32F67233, 1 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .if (USE_HT32_CHIP==HT32F52220_30) + .long _RESERVED /* 01, 17, 0x044, */ + .else + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .endif + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52344_54) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 08, 24, 0x060, */ + .else + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) + .long GPTM1_IRQHandler /* 11, 27, 0x06C, */ + .else + .long _RESERVED /* 11, 27, 0x06C, */ + .endif + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .else + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F52231_41) || (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52243_53) || (USE_HT32_CHIP==HT32F0006) + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .if (USE_HT32_CHIP==HT32F52220_30) + .long _RESERVED /* 18, 34, 0x088, */ + .else + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .endif + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 22, 38, 0x098, */ + .else + .if (USE_HT32_CHIP==HT32F0006) + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .else + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .endif + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52243_53) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 26, 42, 0x0A8, */ + .else + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52342_52) + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long UART2_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0006) + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 27, 43, 0xAC, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F0006) + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long UART3_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long AES_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long _RESERVED /* 29, 45, 0x0B4, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52243_53) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM1_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ SCI_IRQHandler + IRQ MIDI_IRQHandler + IRQ I2S_IRQHandler + IRQ AES_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_02.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_02.s new file mode 100644 index 00000000000..784c9cef994 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_02.s @@ -0,0 +1,382 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050220 + .equ _HT32FWID, 0x00050230 + .equ _HT32FWID, 0x00050231 + .equ _HT32FWID, 0x00050241 + .equ _HT32FWID, 0x00032002 + .equ _HT32FWID, 0x00059041 + .equ _HT32FWID, 0x000F5032 + .equ _HT32FWID, 0x00061641 + .equ _HT32FWID, 0x00059046 + .equ _HT32FWID, 0x00061041 +*/ + + .equ HT32F50220_30, 7 + .equ HT32F50231_41, 8 + .equ HT50F32002, 7 + .equ HT32F59041, 8 + .equ HF5032, 7 + .equ HT32F61641, 8 + .equ HT32F59046, 8 + .equ HT32F61041, 8 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 18, 34, 0x088, */ + .else + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .endif + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_03.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_03.s new file mode 100644 index 00000000000..e00f3d2618b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_03.s @@ -0,0 +1,444 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_03.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00000008 + .equ _HT32FWID, 0x00052142 + .equ _HT32FWID, 0x00052344 + .equ _HT32FWID, 0x00052354 + .equ _HT32FWID, 0x00052357 + .equ _HT32FWID, 0x00052367 + .equ _HT32FWID, 0x0003200F +*/ + + .equ HT32F0008, 6 + .equ HT32F52142, 6 + .equ HT32F52344_54, 9 + .equ HT32F52357_67, 11 + .equ HT50F3200T, 11 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long COMP_DAC_IRQHandler /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 08, 24, 0x060, */ + .else + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long AES_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long QSPI_IRQHandler /* 11, 27, 0x06C, */ + .else + .long _RESERVED /* 11, 27, 0x06C, */ + .endif + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .else + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52357_67) + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 22, 38, 0x098, */ + .else + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .long UART0_UART2_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_UART3_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .else + .long _RESERVED /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long AES_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ COMP_DAC_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART0_UART2_IRQHandler + IRQ UART1_UART3_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ AES_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_05.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_05.s new file mode 100644 index 00000000000..5aba9e9f485 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_05.s @@ -0,0 +1,396 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00057331 + .equ _HT32FWID, 0x00057341 + .equ _HT32FWID, 0x00057342 + .equ _HT32FWID, 0x00057352 + .equ _HT32FWID, 0x00059741 + .equ _HT32FWID, 0x00005828 + .equ _HT32FWID, 0x00067742 + .equ _HT32FWID, 0x00059746 +*/ + + .equ HT32F57331_41, 13 + .equ HT32F57342_52, 14 + .equ HT32F59741, 13 + .equ HT32F5828, 14 + .equ HT32F67742, 13 + .equ HT32F59746, 13 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long COMP_DAC_IRQHandler /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long AES_IRQHandler /* 09, 25, 0x064, */ + .endif + .long _RESERVED /* 10, 26, 0x068, */ + .long LCD_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 30, 46, 0x0B8, */ + .long _RESERVED /* 31, 47, 0x0BC, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ COMP_DAC_IRQHandler + IRQ ADC_IRQHandler + IRQ AES_IRQHandler + IRQ LCD_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_06.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_06.s new file mode 100644 index 00000000000..8d21e6d9003 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_06.s @@ -0,0 +1,347 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_06.s +; Version : $Rev:: 4143 $ +; Date : $Date:: 2019-07-24 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50343 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <15=> HT32F50343 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050343 +*/ + + .equ HT32F50343, 15 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long PWM2_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SLED0_IRQHandler /* 27, 43, 0x0AC, */ + .long SLED1_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ PWM2_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SLED0_IRQHandler + IRQ SLED1_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_07.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_07.s new file mode 100644 index 00000000000..f6702bded77 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_07.s @@ -0,0 +1,355 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_07.s +; Version : $Rev:: 5157 $ +; Date : $Date:: 2021-01-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00000006 + .equ _HT32FWID, 0x00061352 + .equ _HT32FWID, 0x00061355 + .equ _HT32FWID, 0x00061356 + .equ _HT32FWID, 0x00061357 +*/ + + .equ HT32F0006, 10 + .equ HT32F61352, 10 + .equ HT32F61355_56_57, 17 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ MIDI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_08.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_08.s new file mode 100644 index 00000000000..eef814945f9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_08.s @@ -0,0 +1,315 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_08.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; HT50F3200S +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> HT50F3200S +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00065230 + .equ _HT32FWID, 0x00065240 + .equ _HT32FWID, 0x00065232 + .equ _HT32FWID, 0x0003200F +*/ + + .equ HT32F65230_40, 12 + .equ HT32F65232, 18 + .equ HT50F3200S, 12 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_9_IRQHandler /* 06, 22, 0x058, */ + .long EXTI10_15_IRQHandler /* 07, 23, 0x05C, */ + .long ADC0_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F65230_40) + .long ADC1_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .long MCTM0_BRK_IRQHandler /* 10, 26, 0x068, */ + .long MCTM0_UP_IRQHandler /* 11, 27, 0x06C, */ + .long MCTM0_TR_UP2_IRQHandler /* 12, 28, 0x070, */ + .long MCTM0_CC_IRQHandler /* 13, 29, 0x074, */ + .long GPTM0_G_IRQHandler /* 14, 30, 0x078, */ + .long GPTM0_VCLK_IRQHandler /* 15, 31, 0x07C, */ + .long BFTM0_IRQHandler /* 16, 32, 0x080, */ + .long BFTM1_IRQHandler /* 17, 33, 0x084, */ + .long CMP0_IRQHandler /* 18, 34, 0x088, */ + .long CMP1_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F65230_40) + .long CMP2_IRQHandler /* 20, 36, 0x090, */ + .else + .long _RESERVED /* 20, 36, 0x090, */ + .endif + .long I2C0_IRQHandler /* 21, 37, 0x094, */ + .long SPI0_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long UART0_IRQHandler /* 24, 40, 0x0A0, */ + .long PDMA_CH0_1_IRQHandler /* 25, 41, 0x0A4, */ + .long PDMA_CH2_3_IRQHandler /* 26, 42, 0x0A8, */ + .long PDMA_CH4_5_IRQHandler /* 27, 43, 0x0AC, */ + .long SCTM0_IRQHandler /* 28, 44, 0x0B0, */ + .long SCTM1_IRQHandler /* 29, 45, 0x0B4, */ + .long SCTM2_IRQHandler /* 30, 46, 0x0B8, */ + .long SCTM3_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_9_IRQHandler + IRQ EXTI10_15_IRQHandler + IRQ ADC0_IRQHandler + IRQ ADC1_IRQHandler + IRQ MCTM0_BRK_IRQHandler + IRQ MCTM0_UP_IRQHandler + IRQ MCTM0_TR_UP2_IRQHandler + IRQ MCTM0_CC_IRQHandler + IRQ GPTM0_G_IRQHandler + IRQ GPTM0_VCLK_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ CMP2_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_3_IRQHandler + IRQ PDMA_CH4_5_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_09.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_09.s new file mode 100644 index 00000000000..1a2be14682b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_09.s @@ -0,0 +1,387 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_09.s +; Version : $Rev:: 5410 $ +; Date : $Date:: 2021-06-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F54231, HT32F54241 +; HT32F54243, HT32F54253 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <19=> HT32F54231/41 +;// <20=> HT32F54243/53 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00054231 + .equ _HT32FWID, 0x00054241 + .equ _HT32FWID, 0x00054243 + .equ _HT32FWID, 0x00054253 +*/ + + .equ HT32F54231_41, 19 + .equ HT32F54243_53, 20 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .endif + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long TKEY_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long UART2_IRQHandler /* 27, 43, 0x0AC, */ + .long UART3_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .if (USE_HT32_CHIP==HT32F54243_53) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ I2C2_IRQHandler + IRQ MCTM0_IRQHandler + IRQ TKEY_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_10.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_10.s new file mode 100644 index 00000000000..d6688b44417 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_10.s @@ -0,0 +1,289 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_10.s +; Version : $Rev:: 6601 $ +; Date : $Date:: 2022-12-27 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F61244, HT32F61245 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <24=> HT32F61244/45 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00061244 + .equ _HT32FWID, 0x00061245 +*/ + + .equ HT32F61244_45, 24 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART0_IRQHandler + IRQ MIDI_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_11.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_11.s new file mode 100644 index 00000000000..f5b5d9585e7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_11.s @@ -0,0 +1,294 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_11.s +; Version : $Rev:: 6206 $ +; Date : $Date:: 2022-10-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F67041, HT32F67051 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <22=> HT32F67041/51 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00067041 + .equ _HT32FWID, 0x00067051 +*/ + + .equ HT32F67041_51, 22 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long AES_IRQHandler /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long RF_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ AES_IRQHandler + IRQ RF_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_12.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_12.s new file mode 100644 index 00000000000..91be324717e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_12.s @@ -0,0 +1,336 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_12.s +; Version : $Rev:: 5572 $ +; Date : $Date:: 2021-08-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F61141 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <23=> HT32F61141 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00061141 +*/ + + .equ HT32F61141, 23 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long _RESERVED /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ USB_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_13.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_13.s new file mode 100644 index 00000000000..1d5b8a33b1e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_13.s @@ -0,0 +1,292 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050020 + .equ _HT32FWID, 0x00050030 + .equ _HT32FWID, 0x00061630 + .equ _HT32FWID, 0x00061030 +*/ + + .equ HT32F50020_30, 25 + .equ HT32F61630, 25 + .equ HT32F61030, 25 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_7_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long _RESERVED /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long _RESERVED /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_7_IRQHandler + IRQ ADC_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ BFTM0_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ LEDC_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_14.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_14.s new file mode 100644 index 00000000000..9a02b727d93 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_14.s @@ -0,0 +1,312 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_14.s +; Version : $Rev:: 6838 $ +; Date : $Date:: 2023-04-06 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50442, HT32F50452 +; HT32F50431, HT32F50441 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <26=> HT32F50442/52 +;// <30=> HT32F50431/41 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050442 + .equ _HT32FWID, 0x00050452 + .equ _HT32FWID, 0x00050431 + .equ _HT32FWID, 0x00050441 +*/ + + .equ HT32F50442_52, 26 + .equ HT32F50431_41, 30 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .else + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_15.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_15.s new file mode 100644 index 00000000000..685f83659e6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_15.s @@ -0,0 +1,313 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_15.s +; Version : $Rev:: 6902 $ +; Date : $Date:: 2023-05-08 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F53242, HT32F53252 +; HT32F53231, HT32F53241 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <28=> HT32F53242/52 +;// <29=> HT32F53231/41 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00053242 + .equ _HT32FWID, 0x00053252 + .equ _HT32FWID, 0x00053231 + .equ _HT32FWID, 0x00053241 +*/ + + .equ HT32F53242_52, 28 + .equ HT32F53231_41, 29 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .else + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long CAN0_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ CAN0_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_16.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_16.s new file mode 100644 index 00000000000..8cb1f85b48b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_16.s @@ -0,0 +1,317 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_16.s +; Version : $Rev:: 7094 $ +; Date : $Date:: 2023-08-02 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F66242 +; HT32F66246 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* + + + + +*/ + .equ USE_HT32_CHIP_SET, 0 + +/* + .equ _HT32FWID, 0xFFFFFFFF + .equ _HT32FWID, 0x00066246 +*/ + + .equ HT32F66246, 31 + .equ HT32F66242, 33 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .if USE_HT32_CHIP == 0 + .equ _HT32FWID, 0x00066246 + .endif + .if USE_HT32_CHIP == HT32F66246 + .equ _HT32FWID, 0x00066246 + .endif + .if USE_HT32_CHIP == HT32F66242 + .equ _HT32FWID, 0x00066242 + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F66246) + .long CAN0_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long CORDIC_IRQHandler /* 09, 25, 0x064, */ + .long MCTM0_BRK_IRQHandler /* 10, 26, 0x068, */ + .long MCTM0_UP_IRQHandler /* 11, 27, 0x06C, */ + .long MCTM0_TR_UP2_IRQHandler /* 12, 28, 0x070, */ + .long MCTM0_CC_IRQHandler /* 13, 29, 0x074, */ + .long GPTM0_G_IRQHandler /* 14, 30, 0x078, */ + .long GPTM0_VCLK_IRQHandler /* 15, 31, 0x07C, */ + .long BFTM0_IRQHandler /* 16, 32, 0x080, */ + .long BFTM1_IRQHandler /* 17, 33, 0x084, */ + .long CMP0_IRQHandler /* 18, 34, 0x088, */ + .long CMP1_IRQHandler /* 19, 35, 0x08C, */ + .long PID_IRQHandler /* 20, 36, 0x090, */ + .long I2C0_IRQHandler /* 21, 37, 0x094, */ + .long SPI0_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long UART0_IRQHandler /* 24, 40, 0x0A0, */ + .long PDMA_CH0_1_IRQHandler /* 25, 41, 0x0A4, */ + .long PDMA_CH2_3_IRQHandler /* 26, 42, 0x0A8, */ + .long PDMA_CH4_5_IRQHandler /* 27, 43, 0x0AC, */ + .long SCTM0_IRQHandler /* 28, 44, 0x0B0, */ + .long SCTM1_IRQHandler /* 29, 45, 0x0B4, */ + .long SCTM2_IRQHandler /* 30, 46, 0x0B8, */ + .long SCTM3_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ CAN0_IRQHandler + IRQ ADC_IRQHandler + IRQ CORDIC_IRQHandler + IRQ MCTM0_BRK_IRQHandler + IRQ MCTM0_UP_IRQHandler + IRQ MCTM0_TR_UP2_IRQHandler + IRQ MCTM0_CC_IRQHandler + IRQ GPTM0_G_IRQHandler + IRQ GPTM0_VCLK_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ PID_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_3_IRQHandler + IRQ PDMA_CH4_5_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_17.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_17.s new file mode 100644 index 00000000000..f19b45b36f8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/GCC/startup_ht32f5xxxx_gcc_17.s @@ -0,0 +1,291 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_gcc_17.s +; Version : $Rev:: 7030 $ +; Date : $Date:: 2023-07-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F52234, HT32F52244 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <33=> HT32F52234/44 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00052234 + .equ _HT32FWID, 0x00052244 +*/ + + .equ HT32F52234_44, 33 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +/* start address for the initialization values of the .data section. defined in linker script */ +.word _sidata + +/* start address for the .data section. defined in linker script */ +.word _sdata + +/* end address for the .data section. defined in linker script */ +.word _edata + +/* start address for the .bss section. defined in linker script */ +.word _sbss + +/* end address for the .bss section. defined in linker script */ +.word _ebss + + +/* +; Amount of memory (in bytes) allocated for Stack and Heap +; Tailor those values to your application needs +;// Stack Size (in Bytes, must 8 byte aligned) <:8> +*/ + .equ Stack_Size, 512 + .section ".stack", "w" + .align 3 + .globl __StackTop + .globl __StackLimit + .globl __HT_check_sp +__HT_check_sp: +__StackLimit: + .if Stack_Size + .space Stack_Size + .endif + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + +/* +;// Heap Size (in Bytes) <:8> +*/ + .equ Heap_Size, 0 + .section ".heap", "w" + .align 3 + .globl __HeapBase + .globl _end + .globl __HeapLimit + .globl __HT_check_heap +__HT_check_heap: +__HeapBase: +_end: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .section .isr_vector,"a",%progbits + .global __interrupt_vector_cortex_m + .type __interrupt_vector_cortex_m, %object +__interrupt_vector_cortex_m: + .long __StackTop /* ---, 00, 0x000, Top address of Stack */ + .long Reset_Handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long DAC0_1_IRQHandler /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long _RESERVED /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + .size __interrupt_vector_cortex_m, . - __interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + LDR R0, =__StackTop /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + + /* Copy the data segment initializers from flash to SRAM */ + MOVS R1, #0 + B LoopCopyDataInit + +CopyDataInit: + LDR R3, =_sidata + LDR R3, [R3, R1] + STR R3, [R0, R1] + ADDS R1, R1, #4 + +LoopCopyDataInit: + LDR R0, =_sdata + LDR R3, =_edata + ADDS R2, R0, R1 + CMP R2, R3 + BCC CopyDataInit + LDR R2, =_sbss + B LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + MOVS R3, #0 + STR R3, [R2] + ADDS R2, R2, #4 + +LoopFillZerobss: + LDR R3, =_ebss + CMP R2, R3 + BCC FillZerobss + + /* Call static constructors */ + BL __libc_init_array + + /* Call the application's entry point.*/ + BL main + +LoopForever: + B LoopForever + + .thumb_func + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ DAC0_1_IRQHandler + IRQ ADC_IRQHandler + IRQ I2C2_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s new file mode 100644 index 00000000000..1fc4bed7a63 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_01.s @@ -0,0 +1,430 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052220 +;_HT32FWID EQU 0x00052230 +;_HT32FWID EQU 0x00052231 +;_HT32FWID EQU 0x00052241 +;_HT32FWID EQU 0x00052331 +;_HT32FWID EQU 0x00052341 +;_HT32FWID EQU 0x00052342 +;_HT32FWID EQU 0x00052352 +;_HT32FWID EQU 0x00052243 +;_HT32FWID EQU 0x00052253 +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00032003 +;_HT32FWID EQU 0x00062030 +;_HT32FWID EQU 0x00062040 +;_HT32FWID EQU 0x00062050 +;_HT32FWID EQU 0x00067741 +;_HT32FWID EQU 0x00067232 +;_HT32FWID EQU 0x00067233 + +HT32F52220_30 EQU 1 +HT32F52231_41 EQU 2 +HT32F52331_41 EQU 3 +HT32F52342_52 EQU 4 +HT32F52243_53 EQU 5 +HT32F0008 EQU 6 +HT32F52344_54 EQU 9 +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT50F32003 EQU 4 +HT32F62030 EQU 1 +HT32F62040 EQU 2 +HT32F62050 EQU 5 +HT32F67741 EQU 2 +HT32F67232 EQU 1 +HT32F67233 EQU 1 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 01, 17, 0x044, + ELSE + DCD RTC_IRQHandler ; 01, 17, 0x044, + ENDIF + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) + DCD GPTM1_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F52231_41) || (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0006) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F52220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + IF (USE_HT32_CHIP=HT32F0006) + DCD QSPI_IRQHandler ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + IF (USE_HT32_CHIP=HT32F52220_30) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F0006) + DCD _RESERVED ; 26, 42, 0x0A8, + ELSE + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0006) + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0006) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52331_41) || (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD USB_IRQHandler ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52243_53) + DCD _RESERVED ; 29, 45, 0x0B4, + ENDIF + IF (USE_HT32_CHIP=HT32F52342_52) || (USE_HT32_CHIP=HT32F52243_53) || (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) || (USE_HT32_CHIP=HT32F0006) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK COMP_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK MCTM0_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK GPTM1_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK SCTM3_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK PWM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK I2C2_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK QSPI_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK USART1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK UART3_IRQHandler + PUBWEAK SCI_IRQHandler + PUBWEAK MIDI_IRQHandler + PUBWEAK I2S_IRQHandler + PUBWEAK AES_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM1_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SCI_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_02.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_02.s new file mode 100644 index 00000000000..90e00906880 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_02.s @@ -0,0 +1,275 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050220 +;_HT32FWID EQU 0x00050230 +;_HT32FWID EQU 0x00050231 +;_HT32FWID EQU 0x00050241 +;_HT32FWID EQU 0x00032002 +;_HT32FWID EQU 0x00059041 +;_HT32FWID EQU 0x000F5032 +;_HT32FWID EQU 0x00061641 +;_HT32FWID EQU 0x00059046 +;_HT32FWID EQU 0x00061041 + +HT32F50220_30 EQU 7 +HT32F50231_41 EQU 8 +HT50F32002 EQU 7 +HT32F59041 EQU 8 +HF5032 EQU 7 +HT32F61641 EQU 8 +HT32F59046 EQU 8 +HT32F61041 EQU 8 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 18, 34, 0x088, + ELSE + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + ENDIF + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + IF (USE_HT32_CHIP=HT32F50220_30) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK MCTM0_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK PWM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_03.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_03.s new file mode 100644 index 00000000000..d33333bd3a4 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_03.s @@ -0,0 +1,351 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_03.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000008 +;_HT32FWID EQU 0x00052142 +;_HT32FWID EQU 0x00052344 +;_HT32FWID EQU 0x00052354 +;_HT32FWID EQU 0x00052357 +;_HT32FWID EQU 0x00052367 +;_HT32FWID EQU 0x0003200F + +HT32F0008 EQU 6 +HT32F52142 EQU 6 +HT32F52344_54 EQU 9 +HT32F52357_67 EQU 11 +HT50F3200T EQU 11 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 08, 24, 0x060, + ELSE + DCD ADC_IRQHandler ; 08, 24, 0x060, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD AES_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 10, 26, 0x068, + ELSE + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD QSPI_IRQHandler ; 11, 27, 0x06C, + ELSE + DCD _RESERVED ; 11, 27, 0x06C, + ENDIF + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ELSE + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52357_67) + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F0008) || (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 20, 36, 0x090, + ELSE + DCD I2C1_IRQHandler ; 20, 36, 0x090, + ENDIF + DCD SPI0_IRQHandler ; 21, 37, 0x094, + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 22, 38, 0x098, + ELSE + DCD SPI1_IRQHandler ; 22, 38, 0x098, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 23, 39, 0x09C, + ELSE + DCD USART0_IRQHandler ; 23, 39, 0x09C, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + DCD UART0_UART2_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_UART3_IRQHandler ; 26, 42, 0x0A8, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD SCI_IRQHandler ; 27, 43, 0xAC, + ELSE + DCD _RESERVED ; 27, 43, 0xAC, + ENDIF + IF (USE_HT32_CHIP=HT32F0008) + DCD AES_IRQHandler ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52344_54) + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F52357_67) + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK COMP_IRQHandler + PUBWEAK COMP_DAC_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK MCTM0_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK PWM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK QSPI_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK USART1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK UART0_UART2_IRQHandler + PUBWEAK UART1_UART3_IRQHandler + PUBWEAK SCI_IRQHandler + PUBWEAK I2S_IRQHandler + PUBWEAK AES_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART0_UART2_IRQHandler +UART1_UART3_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +AES_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_05.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_05.s new file mode 100644 index 00000000000..2d5a99264b3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_05.s @@ -0,0 +1,298 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00057331 +;_HT32FWID EQU 0x00057341 +;_HT32FWID EQU 0x00057342 +;_HT32FWID EQU 0x00057352 +;_HT32FWID EQU 0x00059741 +;_HT32FWID EQU 0x00005828 +;_HT32FWID EQU 0x00067742 +;_HT32FWID EQU 0x00059746 + +HT32F57331_41 EQU 13 +HT32F57342_52 EQU 14 +HT32F59741 EQU 13 +HT32F5828 EQU 14 +HT32F67742 EQU 13 +HT32F59746 EQU 13 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD COMP_DAC_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD AES_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD _RESERVED ; 10, 26, 0x068, + DCD LCD_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + ENDIF + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F57331_41) + DCD _RESERVED ; 30, 46, 0x0B8, + DCD _RESERVED ; 31, 47, 0x0BC, + ENDIF + IF (USE_HT32_CHIP=HT32F57342_52) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK COMP_DAC_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK AES_IRQHandler + PUBWEAK LCD_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK PWM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK USART1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK SCI_IRQHandler + PUBWEAK I2S_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_DAC_IRQHandler +ADC_IRQHandler +AES_IRQHandler +LCD_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_06.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_06.s new file mode 100644 index 00000000000..fc26530cff5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_06.s @@ -0,0 +1,245 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_06.s +; Version : $Rev:: 4123 $ +; Date : $Date:: 2019-07-23 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50343 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <15=> HT32F50343 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050343 + +HT32F50343 EQU 15 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD PWM2_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD PWM1_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SLED0_IRQHandler ; 27, 43, 0x0AC, + DCD SLED1_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK PWM2_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK PWM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK SLED0_IRQHandler + PUBWEAK SLED1_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +PWM2_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SLED0_IRQHandler +SLED1_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_07.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_07.s new file mode 100644 index 00000000000..dd22e9e2ed3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_07.s @@ -0,0 +1,252 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_07.s +; Version : $Rev:: 5157 $ +; Date : $Date:: 2021-01-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00000006 +;_HT32FWID EQU 0x00061352 +;_HT32FWID EQU 0x00061355 +;_HT32FWID EQU 0x00061356 +;_HT32FWID EQU 0x00061357 + +HT32F0006 EQU 10 +HT32F61352 EQU 10 +HT32F61355_56_57 EQU 17 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD I2S_IRQHandler ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK SCTM3_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK QSPI_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK MIDI_IRQHandler + PUBWEAK I2S_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +I2S_IRQHandler +USB_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_08.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_08.s new file mode 100644 index 00000000000..c1c8add3fb3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_08.s @@ -0,0 +1,224 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_08.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; HT50F3200S + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> HT50F3200S +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00065230 +;_HT32FWID EQU 0x00065240 +;_HT32FWID EQU 0x00065232 +;_HT32FWID EQU 0x0003200F + +HT32F65230_40 EQU 12 +HT32F65232 EQU 18 +HT50F3200S EQU 12 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_9_IRQHandler ; 06, 22, 0x058, + DCD EXTI10_15_IRQHandler ; 07, 23, 0x05C, + DCD ADC0_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD ADC1_IRQHandler ; 09, 25, 0x064, + ELSE + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + IF (USE_HT32_CHIP=HT32F65230_40) + DCD CMP2_IRQHandler ; 20, 36, 0x090, + ELSE + DCD _RESERVED ; 20, 36, 0x090, + ENDIF + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_9_IRQHandler + PUBWEAK EXTI10_15_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK ADC1_IRQHandler + PUBWEAK MCTM0_BRK_IRQHandler + PUBWEAK MCTM0_UP_IRQHandler + PUBWEAK MCTM0_TR_UP2_IRQHandler + PUBWEAK MCTM0_CC_IRQHandler + PUBWEAK GPTM0_G_IRQHandler + PUBWEAK GPTM0_VCLK_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK CMP1_IRQHandler + PUBWEAK CMP2_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_3_IRQHandler + PUBWEAK PDMA_CH4_5_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK SCTM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_9_IRQHandler +EXTI10_15_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_09.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_09.s new file mode 100644 index 00000000000..508fb39eaa8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_09.s @@ -0,0 +1,291 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_09.s +; Version : $Rev:: 5410 $ +; Date : $Date:: 2021-06-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F54231, HT32F54241 +; HT32F54243, HT32F54253 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <19=> HT32F54231/41 +;// <20=> HT32F54243/53 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00054231 +;_HT32FWID EQU 0x00054241 +;_HT32FWID EQU 0x00054243 +;_HT32FWID EQU 0x00054253 + +HT32F54231_41 EQU 19 +HT32F54243_53 EQU 20 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 09, 25, 0x064, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD I2C2_IRQHandler ; 09, 25, 0x064, + ENDIF + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD TKEY_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + IF (USE_HT32_CHIP=HT32F54231_41) + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + ENDIF + IF (USE_HT32_CHIP=HT32F54243_53) + DCD UART2_IRQHandler ; 27, 43, 0x0AC, + DCD UART3_IRQHandler ; 28, 44, 0x0B0, + ENDIF + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + IF (USE_HT32_CHIP=HT32F54243_53) + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + ENDIF + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK COMP_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK I2C2_IRQHandler + PUBWEAK MCTM0_IRQHandler + PUBWEAK TKEY_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK SCTM3_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK USART1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK UART3_IRQHandler + PUBWEAK LEDC_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +I2C2_IRQHandler +MCTM0_IRQHandler +TKEY_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_10.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_10.s new file mode 100644 index 00000000000..a8289bc68eb --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_10.s @@ -0,0 +1,184 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_10.s +; Version : $Rev:: 5780 $ +; Date : $Date:: 2022-03-28 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F61244, HT32F61245 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <24=> HT32F61244/45 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00061244 +;_HT32FWID EQU 0x00061245 + +HT32F61244_45 EQU 24 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD QSPI_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD MIDI_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK QSPI_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK MIDI_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +QSPI_IRQHandler +UART0_IRQHandler +MIDI_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_11.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_11.s new file mode 100644 index 00000000000..e49a6d56433 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_11.s @@ -0,0 +1,194 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_11.s +; Version : $Rev:: 5991 $ +; Date : $Date:: 2022-06-23 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F67041, HT32F67051 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <22=> HT32F67041/51 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00067041 +;_HT32FWID EQU 0x00067051 + +HT32F67041_51 EQU 22 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD AES_IRQHandler ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD RF_IRQHandler ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD SCTM3_IRQHandler ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK AES_IRQHandler + PUBWEAK RF_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK SCTM3_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +AES_IRQHandler +RF_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_12.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_12.s new file mode 100644 index 00000000000..90ff940648b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_12.s @@ -0,0 +1,226 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_12.s +; Version : $Rev:: 5572 $ +; Date : $Date:: 2021-08-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F61141 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <23=> HT32F61141 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00061141 + +HT32F61141 EQU 23 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD _RESERVED ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD _RESERVED ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD SCI_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD USB_IRQHandler ; 29, 45, 0x0B4, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + +BootProcess + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1 LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2 DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3 LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4 LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK SCI_IRQHandler + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +GPTM0_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SCI_IRQHandler +USB_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_13.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_13.s new file mode 100644 index 00000000000..b573c7b115f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_13.s @@ -0,0 +1,184 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050020 +;_HT32FWID EQU 0x00050030 +;_HT32FWID EQU 0x00061630 +;_HT32FWID EQU 0x00061030 + +HT32F50020_30 EQU 25 +HT32F61630 EQU 25 +HT32F61030 EQU 25 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_7_IRQHandler ; 06, 22, 0x058, + DCD _RESERVED ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD SCTM2_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD _RESERVED ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD _RESERVED ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD _RESERVED ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_7_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK LEDC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_7_IRQHandler +ADC_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +BFTM0_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_14.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_14.s new file mode 100644 index 00000000000..ffd489d97ab --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_14.s @@ -0,0 +1,213 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_14.s +; Version : $Rev:: 6834 $ +; Date : $Date:: 2023-03-31 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F50442, HT32F50452 +; HT32F50431, HT32F50441 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <26=> HT32F50442/52 +;// <30=> HT32F50431/41 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00050442 +;_HT32FWID EQU 0x00050452 +;_HT32FWID EQU 0x00050431 +;_HT32FWID EQU 0x00050441 + +HT32F50442_52 EQU 26 +HT32F50431_41 EQU 30 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F50442_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK COMP_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK MCTM0_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK PWM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK USART1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK LEDC_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_15.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_15.s new file mode 100644 index 00000000000..cf8b05ac9b1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_15.s @@ -0,0 +1,215 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_15.s +; Version : $Rev:: 6902 $ +; Date : $Date:: 2023-05-08 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F53242, HT32F53252 +; HT32F53231, HT32F53241 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <28=> HT32F53242_52 +;// <29=> HT32F53231_41 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00053242 +;_HT32FWID EQU 0x00053252 +;_HT32FWID EQU 0x00053231 +;_HT32FWID EQU 0x00053241 + +HT32F53242_52 EQU 28 +HT32F53231_41 EQU 29 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD COMP_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD _RESERVED ; 09, 25, 0x064, + DCD MCTM0_IRQHandler ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD GPTM0_IRQHandler ; 12, 28, 0x070, + DCD _RESERVED ; 13, 29, 0x074, + DCD _RESERVED ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD PWM1_IRQHandler ; 16, 32, 0x080, + ELSE + DCD _RESERVED ; 16, 32, 0x080, + ENDIF + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD SPI1_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + IF (USE_HT32_CHIP=HT32F53242_52) + DCD USART1_IRQHandler ; 24, 40, 0x0A0, + ELSE + DCD _RESERVED ; 24, 40, 0x0A0, + ENDIF + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD UART1_IRQHandler ; 26, 42, 0x0A8, + DCD CAN0_IRQHandler ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD LEDC_IRQHandler ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK COMP_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK MCTM0_IRQHandler + PUBWEAK GPTM0_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK PWM1_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK USART1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK CAN0_IRQHandler + PUBWEAK LEDC_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +COMP_IRQHandler +ADC_IRQHandler +MCTM0_IRQHandler +GPTM0_IRQHandler +PWM0_IRQHandler +PWM1_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +CAN0_IRQHandler +LEDC_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_16.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_16.s new file mode 100644 index 00000000000..753e6eb1659 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_16.s @@ -0,0 +1,224 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_16.s +; Version : $Rev:: 7212 $ +; Date : $Date:: 2023-09-11 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F66242 +; HT32F66246 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + + + + + +USE_HT32_CHIP_SET EQU 0 + +;_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00066246 + +HT32F66246 EQU 31 +HT32F66242 EQU 33 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + IF (USE_HT32_CHIP=0) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66246) +_HT32FWID EQU 0x00066246 + ENDIF + IF (USE_HT32_CHIP=HT32F66242) +_HT32FWID EQU 0x00066242 + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + IF (USE_HT32_CHIP=HT32F66246) + DCD CAN0_IRQHandler ; 07, 23, 0x05C, + ELSE + DCD _RESERVED ; 07, 23, 0x05C, + ENDIF + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD CORDIC_IRQHandler ; 09, 25, 0x064, + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + DCD PID_IRQHandler ; 20, 36, 0x090, + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK CAN0_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK CORDIC_IRQHandler + PUBWEAK MCTM0_BRK_IRQHandler + PUBWEAK MCTM0_UP_IRQHandler + PUBWEAK MCTM0_TR_UP2_IRQHandler + PUBWEAK MCTM0_CC_IRQHandler + PUBWEAK GPTM0_G_IRQHandler + PUBWEAK GPTM0_VCLK_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK CMP1_IRQHandler + PUBWEAK PID_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_3_IRQHandler + PUBWEAK PDMA_CH4_5_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK SCTM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +CAN0_IRQHandler +ADC_IRQHandler +CORDIC_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +PID_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_17.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_17.s new file mode 100644 index 00000000000..bfabd93ba90 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f5xxxx_iar_17.s @@ -0,0 +1,188 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_iar_17.s +; Version : $Rev:: 7212 $ +; Date : $Date:: 2023-09-11 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F52234, HT32F52244 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <33=> HT32F52234/44 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00052234 +;_HT32FWID EQU 0x00052244 + +HT32F52234_44 EQU 33 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_15_IRQHandler ; 06, 22, 0x058, + DCD DAC0_1_IRQHandler ; 07, 23, 0x05C, + DCD ADC_IRQHandler ; 08, 24, 0x060, + DCD I2C2_IRQHandler ; 09, 25, 0x064, + DCD _RESERVED ; 10, 26, 0x068, + DCD _RESERVED ; 11, 27, 0x06C, + DCD _RESERVED ; 12, 28, 0x070, + DCD SCTM0_IRQHandler ; 13, 29, 0x074, + DCD SCTM1_IRQHandler ; 14, 30, 0x078, + DCD PWM0_IRQHandler ; 15, 31, 0x07C, + DCD _RESERVED ; 16, 32, 0x080, + DCD BFTM0_IRQHandler ; 17, 33, 0x084, + DCD BFTM1_IRQHandler ; 18, 34, 0x088, + DCD I2C0_IRQHandler ; 19, 35, 0x08C, + DCD I2C1_IRQHandler ; 20, 36, 0x090, + DCD SPI0_IRQHandler ; 21, 37, 0x094, + DCD _RESERVED ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD _RESERVED ; 24, 40, 0x0A0, + DCD UART0_IRQHandler ; 25, 41, 0x0A4, + DCD _RESERVED ; 26, 42, 0x0A8, + DCD _RESERVED ; 27, 43, 0x0AC, + DCD _RESERVED ; 28, 44, 0x0B0, + DCD _RESERVED ; 29, 45, 0x0B4, + DCD PDMA_CH0_1_IRQHandler ; 30, 46, 0x0B8, + DCD PDMA_CH2_5_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_15_IRQHandler + PUBWEAK DAC0_1_IRQHandler + PUBWEAK ADC_IRQHandler + PUBWEAK I2C2_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK PWM0_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DAC0_1_IRQHandler +ADC_IRQHandler +I2C2_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +PWM0_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_5_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f65230_40_iar.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f65230_40_iar.s new file mode 100644 index 00000000000..695ea54ce58 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/IAR/startup_ht32f65230_40_iar.s @@ -0,0 +1,209 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* Holtek Semiconductor Inc. */ +;/* */ +;/* Copyright (C) Holtek Semiconductor Inc. */ +;/* All rights reserved. */ +;/* */ +;/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f65230_40_iar.s +; Version : $Rev:: 6877 $ +; Date : $Date:: 2023-05-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +; Supported Device +; ======================================== +; HT32F65230 +; HT32F65240 + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// HT32 Device +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +USE_HT32_CHIP_SET EQU 0 + +_HT32FWID EQU 0xFFFFFFFF +;_HT32FWID EQU 0x00065230 +;_HT32FWID EQU 0x00065240 + +HT32F65230_40 EQU 12 + + IF USE_HT32_CHIP_SET=0 + ELSE + #undef USE_HT32_CHIP + #define USE_HT32_CHIP USE_HT32_CHIP_SET + ENDIF + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;******************************************************************************* + DATA +_RESERVED EQU 0xFFFFFFFF +__vector_table + DCD sfe(CSTACK) ; ---, 00, 0x000, Top address of Stack + DCD Reset_Handler ; ---, 01, 0x004, Reset Handler + DCD NMI_Handler ; -14, 02, 0x008, NMI Handler + DCD HardFault_Handler ; -13, 03, 0x00C, Hard Fault Handler + DCD _RESERVED ; ---, 04, 0x010, Reserved + DCD _RESERVED ; ---, 05, 0x014, Reserved + DCD _RESERVED ; ---, 06, 0x018, Reserved + DCD _RESERVED ; ---, 07, 0x01C, Reserved + DCD _HT32FWID ; ---, 08, 0x020, Reserved + DCD _RESERVED ; ---, 09, 0x024, Reserved + DCD _RESERVED ; ---, 10, 0x028, Reserved + DCD SVC_Handler ; -05, 11, 0x02C, SVC Handler + DCD _RESERVED ; ---, 12, 0x030, Reserved + DCD _RESERVED ; ---, 13, 0x034, Reserved + DCD PendSV_Handler ; -02, 14, 0x038, PendSV Handler + DCD SysTick_Handler ; -01, 15, 0x03C, SysTick Handler + + ; External Interrupt Handler + DCD LVD_BOD_IRQHandler ; 00, 16, 0x040, + DCD RTC_IRQHandler ; 01, 17, 0x044, + DCD FLASH_IRQHandler ; 02, 18, 0x048, + DCD EVWUP_IRQHandler ; 03, 19, 0x04C, + DCD EXTI0_1_IRQHandler ; 04, 20, 0x050, + DCD EXTI2_3_IRQHandler ; 05, 21, 0x054, + DCD EXTI4_9_IRQHandler ; 06, 22, 0x058, + DCD EXTI10_15_IRQHandler ; 07, 23, 0x05C, + DCD ADC0_IRQHandler ; 08, 24, 0x060, + DCD ADC1_IRQHandler ; 09, 25, 0x064, + DCD MCTM0_BRK_IRQHandler ; 10, 26, 0x068, + DCD MCTM0_UP_IRQHandler ; 11, 27, 0x06C, + DCD MCTM0_TR_UP2_IRQHandler ; 12, 28, 0x070, + DCD MCTM0_CC_IRQHandler ; 13, 29, 0x074, + DCD GPTM0_G_IRQHandler ; 14, 30, 0x078, + DCD GPTM0_VCLK_IRQHandler ; 15, 31, 0x07C, + DCD BFTM0_IRQHandler ; 16, 32, 0x080, + DCD BFTM1_IRQHandler ; 17, 33, 0x084, + DCD CMP0_IRQHandler ; 18, 34, 0x088, + DCD CMP1_IRQHandler ; 19, 35, 0x08C, + DCD CMP2_IRQHandler ; 20, 36, 0x090, + DCD I2C0_IRQHandler ; 21, 37, 0x094, + DCD SPI0_IRQHandler ; 22, 38, 0x098, + DCD USART0_IRQHandler ; 23, 39, 0x09C, + DCD UART0_IRQHandler ; 24, 40, 0x0A0, + DCD PDMA_CH0_1_IRQHandler ; 25, 41, 0x0A4, + DCD PDMA_CH2_3_IRQHandler ; 26, 42, 0x0A8, + DCD PDMA_CH4_5_IRQHandler ; 27, 43, 0x0AC, + DCD SCTM0_IRQHandler ; 28, 44, 0x0B0, + DCD SCTM1_IRQHandler ; 29, 45, 0x0B4, + DCD SCTM2_IRQHandler ; 30, 46, 0x0B8, + DCD SCTM3_IRQHandler ; 31, 47, 0x0BC, + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + PUBWEAK LVD_BOD_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK FLASH_IRQHandler + PUBWEAK EVWUP_IRQHandler + PUBWEAK EXTI0_1_IRQHandler + PUBWEAK EXTI2_3_IRQHandler + PUBWEAK EXTI4_9_IRQHandler + PUBWEAK EXTI10_15_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK ADC1_IRQHandler + PUBWEAK MCTM0_BRK_IRQHandler + PUBWEAK MCTM0_UP_IRQHandler + PUBWEAK MCTM0_TR_UP2_IRQHandler + PUBWEAK MCTM0_CC_IRQHandler + PUBWEAK GPTM0_G_IRQHandler + PUBWEAK GPTM0_VCLK_IRQHandler + PUBWEAK BFTM0_IRQHandler + PUBWEAK BFTM1_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK CMP1_IRQHandler + PUBWEAK CMP2_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK USART0_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK PDMA_CH0_1_IRQHandler + PUBWEAK PDMA_CH2_3_IRQHandler + PUBWEAK PDMA_CH4_5_IRQHandler + PUBWEAK SCTM0_IRQHandler + PUBWEAK SCTM1_IRQHandler + PUBWEAK SCTM2_IRQHandler + PUBWEAK SCTM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LVD_BOD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +EVWUP_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_9_IRQHandler +EXTI10_15_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +MCTM0_BRK_IRQHandler +MCTM0_UP_IRQHandler +MCTM0_TR_UP2_IRQHandler +MCTM0_CC_IRQHandler +GPTM0_G_IRQHandler +GPTM0_VCLK_IRQHandler +BFTM0_IRQHandler +BFTM1_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +CMP2_IRQHandler +I2C0_IRQHandler +SPI0_IRQHandler +USART0_IRQHandler +UART0_IRQHandler +PDMA_CH0_1_IRQHandler +PDMA_CH2_3_IRQHandler +PDMA_CH4_5_IRQHandler +SCTM0_IRQHandler +SCTM1_IRQHandler +SCTM2_IRQHandler +SCTM3_IRQHandler + B . + + END diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/SEGGER_THUMB_Startup.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/SEGGER_THUMB_Startup.s new file mode 100644 index 00000000000..63a379c8042 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/SEGGER_THUMB_Startup.s @@ -0,0 +1,435 @@ +// ********************************************************************** +// * SEGGER Microcontroller GmbH * +// * The Embedded Experts * +// ********************************************************************** +// * * +// * (c) 2014 - 2018 SEGGER Microcontroller GmbH * +// * (c) 2001 - 2018 Rowley Associates Limited * +// * * +// * www.segger.com Support: support@segger.com * +// * * +// ********************************************************************** +// * * +// * All rights reserved. * +// * * +// * Redistribution and use in source and binary forms, with or * +// * without modification, are permitted provided that the following * +// * conditions are met: * +// * * +// * - Redistributions of source code must retain the above copyright * +// * notice, this list of conditions and the following disclaimer. * +// * * +// * - Neither the name of SEGGER Microcontroller GmbH * +// * nor the names of its contributors may be used to endorse or * +// * promote products derived from this software without specific * +// * prior written permission. * +// * * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +// * DISCLAIMED. * +// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +// * DAMAGE. * +// * * +// ********************************************************************** +// Preprocessor Definitions +// ------------------------ +// +// FULL_LIBRARY +// +// If defined then +// - argc, argv are setup by the debug_getargs. +// - the exit symbol is defined and executes on return from main. +// - the exit symbol calls destructors, atexit functions and then debug_exit. +// +// If not defined then +// - argc and argv are zero. +// - the exit symbol is defined, executes on return from main and loops +// + + .syntax unified + + .section .segger.init.__SEGGER_init_lzss, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_lzss +.thumb_func +__SEGGER_init_lzss: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source stream + adds r4, r4, #8 +2: + ldrb r2, [r1] + adds r1, r1, #1 + tst r2, r2 + beq 9f @ 0 -> end of table + cmp r2, #0x80 + bcc 1f @ +ve -> literal run +// +// -ve -> copy run +// +// r0 = pointer to output stream +// r1 = pointer to input stream +// r2 = run length +// r3 = copy byte +// r4 = pointer to initialization table +// +3: + subs r2, r2, #0x80 // convert to run length + beq 10f + ldrb r3, [r1] // r3 = first byte of distance + adds r1, r1, #1 + cmp r3, #0x80 + bcc 5f // r3 < 128, short run + subs r3, r3, #0x80 // Adjust to recover true run length high byte + lsls r3, r3, #8 // Prepare to fuse + ldrb r5, [r1] // extract run length low byte + adds r1, r1, #1 + adds r3, r3, r5 // construct run length +5: + subs r5, r0, r3 // source of where to copy from +4: + ldrb r3, [r5] // source byte of run + strb r3, [r0] // store to destination + adds r5, r5, #1 + adds r0, r0, #1 + subs r2, r2, #1 + bne 4b + b 2b +// +// +ve -> literal run +// +// r0 = pointer to output stream +// r1 = pointer to input stream +// r2 = run length +// r3 = copy byte +// r4 = pointer to initialization table +// +1: + ldrb r3, [r1] // source byte of run + adds r1, r1, #1 + strb r3, [r0] // store to destination + adds r0, r0, #1 + subs r2, r2, #1 + bne 1b + b 2b +9: + bx lr +10: + b 10b + + .section .segger.init.__SEGGER_init_zero, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_zero +.thumb_func +__SEGGER_init_zero: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ size + adds r4, r4, #8 + tst r1, r1 + beq 2f + movs r2, #0 +1: + strb r2, [r0] + adds r0, r0, #1 + subs r1, r1, #1 + bne 1b +2: + bx lr + + .section .segger.init.__SEGGER_init_copy, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_copy +.thumb_func +__SEGGER_init_copy: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source + ldr r2, [r4, #8] @ size + adds r4, r4, #12 + tst r2, r2 + beq 2f +1: + ldrb r3, [r1] + strb r3, [r0] + adds r0, r0, #1 + adds r1, r1, #1 + subs r2, r2, #1 + bne 1b +2: + bx lr + + .section .segger.init.__SEGGER_init_pack, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_pack +.thumb_func +__SEGGER_init_pack: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source stream + adds r4, r4, #8 +1: + ldrb r2, [r1] + adds r1, r1, #1 + cmp r2, #0x80 + beq 4f + bcc 3f + ldrb r3, [r1] @ byte to replicate + adds r1, r1, #1 + negs r2, r2 + adds r2, r2, #255 + adds r2, r2, #1 +2: + strb r3, [r0] + adds r0, r0, #1 + subs r2, r2, #1 + bpl 2b + b 1b + +3: @ 1+n literal bytes + ldrb r3, [r1] + strb r3, [r0] + adds r0, r0, #1 + adds r1, r1, #1 + subs r2, r2, #1 + bpl 3b + b 1b +4: + bx lr + + .section .segger.init.__SEGGER_init_zpak, "ax" + .code 16 + .balign 2 + .global __SEGGER_init_zpak +.thumb_func +__SEGGER_init_zpak: + ldr r0, [r4] @ destination + ldr r1, [r4, #4] @ source stream + ldr r2, [r4, #8] @ size + adds r4, r4, #12 @ skip table entries +1: + ldrb r3, [r1] @ get control byte from source stream + adds r1, r1, #1 + movs r6, #8 +2: + movs r5, #0 @ prepare zero filler + lsrs r3, r3, #1 @ get byte control flag + bcs 3f @ carry set -> zero filler + ldrb r5, [r1] @ get literal byte from source stream + adds r1, r1, #1 +3: + strb r5, [r0] @ store initialization byte + adds r0, r0, #1 + subs r2, r2, #1 @ size -= 1 + beq 4f @ exit when destination filled + subs r6, r6, #1 @ decrement bit count + bne 2b @ still within this control byte + b 1b @ get next control byte +4: + bx lr + +#ifndef APP_ENTRY_POINT +#define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE +#define ARGSSPACE 128 +#endif + + .global _start + .extern APP_ENTRY_POINT + .global exit + .weak exit + +#ifdef INITIALIZE_USER_SECTIONS + .extern InitializeUserMemorySections +#endif + + .section .init, "ax" + .code 16 + .align 1 + .thumb_func + +_start: + ldr r0, = __stack_end__ + mov sp, r0 + ldr r4, =__SEGGER_init_table__ +1: + ldr r0, [r4] + adds r4, r4, #4 + tst r0, r0 + beq 2f + blx r0 + b 1b +2: + + /* Initialize the heap */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + subs r1, r1, r0 + cmp r1, #8 + blt 1f + movs r2, #0 + str r2, [r0] + adds r0, r0, #4 + str r1, [r0] +1: + +#ifdef INITIALIZE_USER_SECTIONS + ldr r2, =InitializeUserMemorySections + blx r2 +#endif + + /* Call constructors */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0] + adds r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b ctor_loop +ctor_end: + + /* Setup initial call frame */ + movs r0, #0 + mov lr, r0 + mov r12, sp + + .type start, function +start: + /* Jump to application entry point */ +#ifdef FULL_LIBRARY + movs r0, #ARGSSPACE + ldr r1, =args + ldr r2, =debug_getargs + blx r2 + ldr r1, =args +#else + movs r0, #0 + movs r1, #0 +#endif + ldr r2, =APP_ENTRY_POINT + blx r2 + + .thumb_func +exit: +#ifdef FULL_LIBRARY + mov r5, r0 // save the exit parameter/return result + + /* Call destructors */ + ldr r0, =__dtors_start__ + ldr r1, =__dtors_end__ +dtor_loop: + cmp r0, r1 + beq dtor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b dtor_loop +dtor_end: + + /* Call atexit functions */ + ldr r2, =_execute_at_exit_fns + blx r2 + + /* Call debug_exit with return result/exit parameter */ + mov r0, r5 + ldr r2, =debug_exit + blx r2 +#endif + + /* Returned from application entry point, loop forever. */ +exit_loop: + b exit_loop + + // default C/C++ library helpers + +.macro HELPER helper_name + .section .text.\helper_name, "ax", %progbits + .global \helper_name + .align 1 + .weak \helper_name +\helper_name: + .thumb_func +.endm + +.macro JUMPTO name +#if defined(__thumb__) && !defined(__thumb2__) + mov r12, r0 + ldr r0, =\name + push {r0} + mov r0, r12 + pop {pc} +#else + b \name +#endif +.endm + +HELPER __aeabi_read_tp + ldr r0, =__tbss_start__-8 + bx lr +HELPER abort + b . +HELPER __assert + b . +HELPER __aeabi_assert + b . +HELPER __sync_synchronize + bx lr +HELPER __getchar + JUMPTO debug_getchar +HELPER __putchar + JUMPTO debug_putchar +HELPER __open + JUMPTO debug_fopen +HELPER __close + JUMPTO debug_fclose +HELPER __write + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fwrite +HELPER __read + mov r3, r0 + mov r0, r1 + movs r1, #1 + JUMPTO debug_fread +HELPER __seek + push {r4, lr} + mov r4, r0 + bl debug_fseek + cmp r0, #0 + bne 1f + mov r0, r4 + bl debug_ftell + pop {r4, pc} +1: + ldr r0, =-1 + pop {r4, pc} + // char __user_locale_name_buffer[]; + .section .bss.__user_locale_name_buffer, "aw", %nobits + .global __user_locale_name_buffer + .weak __user_locale_name_buffer + __user_locale_name_buffer: + .word 0x0 + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_01.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_01.s new file mode 100644 index 00000000000..a667619b58b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_01.s @@ -0,0 +1,426 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_01.s +; Version : $Rev:: 6953 $ +; Date : $Date:: 2023-05-30 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F52220, HT32F52230 +; HT32F52231, HT32F52241 +; HT32F52331, HT32F52341 +; HT32F52342, HT32F52352 +; HT32F52243, HT32F52253 +; HT32F0008 +; HT32F52344, HT32F52354 +; HT32F0006 +; HT32F61352 +; HT50F32003 +; HT32F62030, HT32F62040, HT32F62050 +; HT32F67741 +; HT32F67232 +; HT32F67233 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <1=> HT32F52220/30 +;// <2=> HT32F52231/41 +;// <3=> HT32F52331/41 +;// <4=> HT32F52342/52 +;// <5=> HT32F52243/53 +;// <6=> HT32F0008 +;// <9=> HT32F52344/54 +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <4=> HT50F32003 +;// <2=> HT32F67741 +;// <1=> HT32F67232 +;// <1=> HT32F67233 +;// <1=> HT32F62030 +;// <2=> HT32F62040 +;// <5=> HT32F62050 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00052220 + .equ _HT32FWID, 0x00052230 + .equ _HT32FWID, 0x00052231 + .equ _HT32FWID, 0x00052241 + .equ _HT32FWID, 0x00052331 + .equ _HT32FWID, 0x00052341 + .equ _HT32FWID, 0x00052342 + .equ _HT32FWID, 0x00052352 + .equ _HT32FWID, 0x00052243 + .equ _HT32FWID, 0x00052253 + .equ _HT32FWID, 0x00000008 + .equ _HT32FWID, 0x00052344 + .equ _HT32FWID, 0x00052354 + .equ _HT32FWID, 0x00000006 + .equ _HT32FWID, 0x00061352 + .equ _HT32FWID, 0x00032003 + .equ _HT32FWID, 0x00062030 + .equ _HT32FWID, 0x00062040 + .equ _HT32FWID, 0x00062050 + .equ _HT32FWID, 0x00067741 + .equ _HT32FWID, 0x00067232 + .equ _HT32FWID, 0x00067233 +*/ + + .equ HT32F52220_30, 1 + .equ HT32F52231_41, 2 + .equ HT32F52331_41, 3 + .equ HT32F52342_52, 4 + .equ HT32F52243_53, 5 + .equ HT32F0008, 6 + .equ HT32F52344_54, 9 + .equ HT32F0006, 10 + .equ HT32F61352, 10 + .equ HT50F32003, 4 + .equ HT32F62030, 1 + .equ HT32F62040, 2 + .equ HT32F62050, 5 + .equ HT32F67741, 2 + .equ HT32F67232, 1 + .equ HT32F67233, 1 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .if (USE_HT32_CHIP==HT32F52220_30) + .long _RESERVED /* 01, 17, 0x044, */ + .else + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .endif + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52344_54) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 08, 24, 0x060, */ + .else + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) + .long GPTM1_IRQHandler /* 11, 27, 0x06C, */ + .else + .long _RESERVED /* 11, 27, 0x06C, */ + .endif + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .else + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F52231_41) || (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52243_53) || (USE_HT32_CHIP==HT32F0006) + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .if (USE_HT32_CHIP==HT32F52220_30) + .long _RESERVED /* 18, 34, 0x088, */ + .else + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .endif + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 22, 38, 0x098, */ + .else + .if (USE_HT32_CHIP==HT32F0006) + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .else + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .endif + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52243_53) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .if (USE_HT32_CHIP==HT32F52220_30) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F0006) + .long _RESERVED /* 26, 42, 0x0A8, */ + .else + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52342_52) + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long UART2_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0006) + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 27, 43, 0xAC, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F0006) + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long UART3_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long AES_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52331_41) || (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .endif + .if (USE_HT32_CHIP==HT32F52243_53) + .long _RESERVED /* 29, 45, 0x0B4, */ + .endif + .if (USE_HT32_CHIP==HT32F52342_52) || (USE_HT32_CHIP==HT32F52243_53) || (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) || (USE_HT32_CHIP==HT32F0006) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM1_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ SCI_IRQHandler + IRQ MIDI_IRQHandler + IRQ I2S_IRQHandler + IRQ AES_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_02.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_02.s new file mode 100644 index 00000000000..5b5110f922e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_02.s @@ -0,0 +1,289 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_02.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50220, HT32F50230 +; HT32F50231, HT32F50241 +; HT50F32002 +; HT32F59041 +; HF5032 +; HT32F61641 +; HT32F59046 +; HT32F61041 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <7=> HT32F50220/30 +;// <8=> HT32F50231/41 +;// <7=> HT50F32002 +;// <8=> HT32F59041 +;// <7=> HF5032 +;// <8=> HT32F61641 +;// <8=> HT32F59046 +;// <8=> HT32F61041 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050220 + .equ _HT32FWID, 0x00050230 + .equ _HT32FWID, 0x00050231 + .equ _HT32FWID, 0x00050241 + .equ _HT32FWID, 0x00032002 + .equ _HT32FWID, 0x00059041 + .equ _HT32FWID, 0x000F5032 + .equ _HT32FWID, 0x00061641 + .equ _HT32FWID, 0x00059046 + .equ _HT32FWID, 0x00061041 +*/ + + .equ HT32F50220_30, 7 + .equ HT32F50231_41, 8 + .equ HT50F32002, 7 + .equ HT32F59041, 8 + .equ HF5032, 7 + .equ HT32F61641, 8 + .equ HT32F59046, 8 + .equ HT32F61041, 8 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 18, 34, 0x088, */ + .else + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .endif + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .if (USE_HT32_CHIP==HT32F50220_30) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_03.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_03.s new file mode 100644 index 00000000000..e004b723458 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_03.s @@ -0,0 +1,351 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_03.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F0008 +; HT32F52142 +; HT32F52344, HT32F52354 +; HT32F52357, HT32F52367 +; HT50F3200T +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <6=> HT32F0008 +;// <6=> HT32F52142 +;// <9=> HT32F52344/54 +;// <11=> HT32F52357/67 +;// <11=> HT50F3200T +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00000008 + .equ _HT32FWID, 0x00052142 + .equ _HT32FWID, 0x00052344 + .equ _HT32FWID, 0x00052354 + .equ _HT32FWID, 0x00052357 + .equ _HT32FWID, 0x00052367 + .equ _HT32FWID, 0x0003200F +*/ + + .equ HT32F0008, 6 + .equ HT32F52142, 6 + .equ HT32F52344_54, 9 + .equ HT32F52357_67, 11 + .equ HT50F3200T, 11 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long COMP_DAC_IRQHandler /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 08, 24, 0x060, */ + .else + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long AES_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 10, 26, 0x068, */ + .else + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long QSPI_IRQHandler /* 11, 27, 0x06C, */ + .else + .long _RESERVED /* 11, 27, 0x06C, */ + .endif + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .else + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52357_67) + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F0008) || (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 20, 36, 0x090, */ + .else + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .endif + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 22, 38, 0x098, */ + .else + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 23, 39, 0x09C, */ + .else + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .long UART0_UART2_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_UART3_IRQHandler /* 26, 42, 0x0A8, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .else + .long _RESERVED /* 27, 43, 0x0AC, */ + .endif + .if (USE_HT32_CHIP==HT32F0008) + .long AES_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52344_54) + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F52357_67) + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ COMP_DAC_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART0_UART2_IRQHandler + IRQ UART1_UART3_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ AES_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_05.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_05.s new file mode 100644 index 00000000000..25447b9b1f8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_05.s @@ -0,0 +1,303 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_05.s +; Version : $Rev:: 6993 $ +; Date : $Date:: 2023-06-26 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F57331, HT32F57341 +; HT32F57342, HT32F57352 +; HT32F59741 +; HT32F5828 +; HT32F67742 +; HT32F59746 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <13=> HT32F57331/41 +;// <14=> HT32F57342/52 +;// <13=> HT32F59741 +;// <14=> HT32F5828 +;// <13=> HT32F67742 +;// <13=> HT32F59746 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00057331 + .equ _HT32FWID, 0x00057341 + .equ _HT32FWID, 0x00057342 + .equ _HT32FWID, 0x00057352 + .equ _HT32FWID, 0x00059741 + .equ _HT32FWID, 0x00005828 + .equ _HT32FWID, 0x00067742 + .equ _HT32FWID, 0x00059746 +*/ + + .equ HT32F57331_41, 13 + .equ HT32F57342_52, 14 + .equ HT32F59741, 13 + .equ HT32F5828, 14 + .equ HT32F67742, 13 + .equ HT32F59746, 13 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long COMP_DAC_IRQHandler /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long AES_IRQHandler /* 09, 25, 0x064, */ + .endif + .long _RESERVED /* 10, 26, 0x068, */ + .long LCD_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .endif + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .if (USE_HT32_CHIP==HT32F57331_41) + .long _RESERVED /* 30, 46, 0x0B8, */ + .long _RESERVED /* 31, 47, 0x0BC, */ + .endif + .if (USE_HT32_CHIP==HT32F57342_52) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ COMP_DAC_IRQHandler + IRQ ADC_IRQHandler + IRQ AES_IRQHandler + IRQ LCD_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_06.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_06.s new file mode 100644 index 00000000000..00dc85d2332 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_06.s @@ -0,0 +1,254 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_06.s +; Version : $Rev:: 4142 $ +; Date : $Date:: 2019-07-24 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50343 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <15=> HT32F50343 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050343 +*/ + + .equ HT32F50343, 15 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long PWM2_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SLED0_IRQHandler /* 27, 43, 0x0AC, */ + .long SLED1_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ PWM2_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SLED0_IRQHandler + IRQ SLED1_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_07.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_07.s new file mode 100644 index 00000000000..4f71e6a0293 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_07.s @@ -0,0 +1,262 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_07.s +; Version : $Rev:: 5157 $ +; Date : $Date:: 2021-01-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F0006 +; HT32F61352 +; HT32F61355, HT32F61356, HT32F61357 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <10=> HT32F0006 +;// <10=> HT32F61352 +;// <17=> HT32F61355/56/57 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00000006 + .equ _HT32FWID, 0x00061352 + .equ _HT32FWID, 0x00061355 + .equ _HT32FWID, 0x00061356 + .equ _HT32FWID, 0x00061357 +*/ + + .equ HT32F0006, 10 + .equ HT32F61352, 10 + .equ HT32F61355_56_57, 17 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .long I2S_IRQHandler /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ QSPI_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ MIDI_IRQHandler + IRQ I2S_IRQHandler + IRQ USB_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_08.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_08.s new file mode 100644 index 00000000000..afbbdcd1158 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_08.s @@ -0,0 +1,222 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_08.s +; Version : $Rev:: 6887 $ +; Date : $Date:: 2023-05-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F65230, HT32F65240 +; HT32F65232 +; HT50F3200S +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <12=> HT32F65230_40 +;// <18=> HT32F65232 +;// <12=> HT50F3200S +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00065230 + .equ _HT32FWID, 0x00065240 + .equ _HT32FWID, 0x00065232 + .equ _HT32FWID, 0x0003200F +*/ + + .equ HT32F65230_40, 12 + .equ HT32F65232, 18 + .equ HT50F3200S, 12 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_9_IRQHandler /* 06, 22, 0x058, */ + .long EXTI10_15_IRQHandler /* 07, 23, 0x05C, */ + .long ADC0_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F65230_40) + .long ADC1_IRQHandler /* 09, 25, 0x064, */ + .else + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .long MCTM0_BRK_IRQHandler /* 10, 26, 0x068, */ + .long MCTM0_UP_IRQHandler /* 11, 27, 0x06C, */ + .long MCTM0_TR_UP2_IRQHandler /* 12, 28, 0x070, */ + .long MCTM0_CC_IRQHandler /* 13, 29, 0x074, */ + .long GPTM0_G_IRQHandler /* 14, 30, 0x078, */ + .long GPTM0_VCLK_IRQHandler /* 15, 31, 0x07C, */ + .long BFTM0_IRQHandler /* 16, 32, 0x080, */ + .long BFTM1_IRQHandler /* 17, 33, 0x084, */ + .long CMP0_IRQHandler /* 18, 34, 0x088, */ + .long CMP1_IRQHandler /* 19, 35, 0x08C, */ + .if (USE_HT32_CHIP==HT32F65230_40) + .long CMP2_IRQHandler /* 20, 36, 0x090, */ + .else + .long _RESERVED /* 20, 36, 0x090, */ + .endif + .long I2C0_IRQHandler /* 21, 37, 0x094, */ + .long SPI0_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long UART0_IRQHandler /* 24, 40, 0x0A0, */ + .long PDMA_CH0_1_IRQHandler /* 25, 41, 0x0A4, */ + .long PDMA_CH2_3_IRQHandler /* 26, 42, 0x0A8, */ + .long PDMA_CH4_5_IRQHandler /* 27, 43, 0x0AC, */ + .long SCTM0_IRQHandler /* 28, 44, 0x0B0, */ + .long SCTM1_IRQHandler /* 29, 45, 0x0B4, */ + .long SCTM2_IRQHandler /* 30, 46, 0x0B8, */ + .long SCTM3_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_9_IRQHandler + IRQ EXTI10_15_IRQHandler + IRQ ADC0_IRQHandler + IRQ ADC1_IRQHandler + IRQ MCTM0_BRK_IRQHandler + IRQ MCTM0_UP_IRQHandler + IRQ MCTM0_TR_UP2_IRQHandler + IRQ MCTM0_CC_IRQHandler + IRQ GPTM0_G_IRQHandler + IRQ GPTM0_VCLK_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ CMP2_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_3_IRQHandler + IRQ PDMA_CH4_5_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_09.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_09.s new file mode 100644 index 00000000000..cd8e491fce0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_09.s @@ -0,0 +1,294 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_09.s +; Version : $Rev:: 5410 $ +; Date : $Date:: 2021-06-04 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F54231, HT32F54241 +; HT32F54243, HT32F54253 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <19=> HT32F54231/41 +;// <20=> HT32F54243/53 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00054231 + .equ _HT32FWID, 0x00054241 + .equ _HT32FWID, 0x00054243 + .equ _HT32FWID, 0x00054253 +*/ + + .equ HT32F54231_41, 19 + .equ HT32F54243_53, 20 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 09, 25, 0x064, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .endif + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long TKEY_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .if (USE_HT32_CHIP==HT32F54231_41) + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .endif + .if (USE_HT32_CHIP==HT32F54243_53) + .long UART2_IRQHandler /* 27, 43, 0x0AC, */ + .long UART3_IRQHandler /* 28, 44, 0x0B0, */ + .endif + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .if (USE_HT32_CHIP==HT32F54243_53) + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + .endif + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ I2C2_IRQHandler + IRQ MCTM0_IRQHandler + IRQ TKEY_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_10.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_10.s new file mode 100644 index 00000000000..d9253dcbca5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_10.s @@ -0,0 +1,194 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_10.s +; Version : $Rev:: 6601 $ +; Date : $Date:: 2022-12-27 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F61244, HT32F61245 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <24=> HT32F61244/45 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00061244 + .equ _HT32FWID, 0x00061245 +*/ + + .equ HT32F61244_45, 24 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long QSPI_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long MIDI_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ QSPI_IRQHandler + IRQ UART0_IRQHandler + IRQ MIDI_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_11.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_11.s new file mode 100644 index 00000000000..176c685784c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_11.s @@ -0,0 +1,199 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_11.s +; Version : $Rev:: 6206 $ +; Date : $Date:: 2022-10-05 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F67041, HT32F67051 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <22=> HT32F67041/51 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00067041 + .equ _HT32FWID, 0x00067051 +*/ + + .equ HT32F67041_51, 22 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long AES_IRQHandler /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long RF_IRQHandler /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long SCTM3_IRQHandler /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ ADC_IRQHandler + IRQ AES_IRQHandler + IRQ RF_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_12.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_12.s new file mode 100644 index 00000000000..b1dc8ca860d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_12.s @@ -0,0 +1,243 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_12.s +; Version : $Rev:: 5572 $ +; Date : $Date:: 2021-08-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F61141 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <23=> HT32F61141 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00061141 +*/ + + .equ HT32F61141, 23 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long _RESERVED /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long _RESERVED /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long SCI_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long USB_IRQHandler /* 29, 45, 0x0B4, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =BootProcess + BLX R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .thumb_func +BootProcess: + LDR R0, =0x40080300 + LDR R1,[R0, #0x10] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x14] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x18] + CMP R1, #0 + BNE BP1 + LDR R1,[R0, #0x1C] + CMP R1, #0 + BEQ BP2 +BP1: + LDR R0, =0x40080180 + LDR R1,[R0, #0xC] + LSLS R1, R1, #4 + LSRS R1, R1, #20 + CMP R1, #0 + BEQ BP3 + CMP R1, #5 + BEQ BP3 + CMP R1, #6 + BEQ BP3 +BP2: + DSB + LDR R0, =0x20000000 + LDR R1, =0x05fa0004 + STR R1, [R0] + LDR R1, =0xe000ed00 + LDR R0, =0x05fa0004 + STR R0, [R1, #0xC] + DSB + B . +BP3: + LDR R0, =0x20000000 + LDR R1, [R0] + LDR R0, =0x05fa0004 + CMP R0, R1 + BEQ BP4 + BX LR +BP4: + LDR R0, =0x40088100 + LDR R1, =0x00000001 + STR R1, [R0] + LDR R0, =0x20000000 + LDR R1, =0x0 + STR R1, [R0] + BX LR + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ GPTM0_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ SCI_IRQHandler + IRQ USB_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_13.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_13.s new file mode 100644 index 00000000000..8c3a524ef12 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_13.s @@ -0,0 +1,197 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_13.s +; Version : $Rev:: 7119 $ +; Date : $Date:: 2023-08-15 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50020, HT32F50030 +; HT32F61630 +; HT32F61030 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <25=> HT32F50020/30 +;// <25=> HT32F61630 +;// <25=> HT32F61030 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050020 + .equ _HT32FWID, 0x00050030 + .equ _HT32FWID, 0x00061630 + .equ _HT32FWID, 0x00061030 +*/ + + .equ HT32F50020_30, 25 + .equ HT32F61630, 25 + .equ HT32F61030, 25 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_7_IRQHandler /* 06, 22, 0x058, */ + .long _RESERVED /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long _RESERVED /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long SCTM2_IRQHandler /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long _RESERVED /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long _RESERVED /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long _RESERVED /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_7_IRQHandler + IRQ ADC_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ BFTM0_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ LEDC_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_14.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_14.s new file mode 100644 index 00000000000..530eb0949ff --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_14.s @@ -0,0 +1,216 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_14.s +; Version : $Rev:: 6793 $ +; Date : $Date:: 2023-03-14 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F50442, HT32F50452 +; HT32F50431, HT32F50441 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <26=> HT32F50442/52 +;// <30=> HT32F50431/41 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00050442 + .equ _HT32FWID, 0x00050452 + .equ _HT32FWID, 0x00050431 + .equ _HT32FWID, 0x00050441 +*/ + + .equ HT32F50442_52, 26 + .equ HT32F50431_41, 30 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .else + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F50442_52) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_15.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_15.s new file mode 100644 index 00000000000..732e674b455 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_15.s @@ -0,0 +1,217 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_15.s +; Version : $Rev:: 6902 $ +; Date : $Date:: 2023-05-08 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F53242, HT32F53252 +; HT32F53231, HT32F53241 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <28=> HT32F53242/52 +;// <29=> HT32F53231/41 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00053242 + .equ _HT32FWID, 0x00053252 + .equ _HT32FWID, 0x00053231 + .equ _HT32FWID, 0x00053241 +*/ + + .equ HT32F53242_52, 28 + .equ HT32F53231_41, 29 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long COMP_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long _RESERVED /* 09, 25, 0x064, */ + .long MCTM0_IRQHandler /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long GPTM0_IRQHandler /* 12, 28, 0x070, */ + .long _RESERVED /* 13, 29, 0x074, */ + .long _RESERVED /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long PWM1_IRQHandler /* 16, 32, 0x080, */ + .else + .long _RESERVED /* 16, 32, 0x080, */ + .endif + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long SPI1_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .if (USE_HT32_CHIP==HT32F53242_52) + .long USART1_IRQHandler /* 24, 40, 0x0A0, */ + .else + .long _RESERVED /* 24, 40, 0x0A0, */ + .endif + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long UART1_IRQHandler /* 26, 42, 0x0A8, */ + .long CAN0_IRQHandler /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long LEDC_IRQHandler /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ COMP_IRQHandler + IRQ ADC_IRQHandler + IRQ MCTM0_IRQHandler + IRQ GPTM0_IRQHandler + IRQ PWM0_IRQHandler + IRQ PWM1_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ CAN0_IRQHandler + IRQ LEDC_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_16.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_16.s new file mode 100644 index 00000000000..81260f6c782 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_16.s @@ -0,0 +1,221 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_16.s +; Version : $Rev:: 7094 $ +; Date : $Date:: 2023-08-02 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F66242 +; HT32F66246 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* + + + + +*/ + .equ USE_HT32_CHIP_SET, 0 + +/* + .equ _HT32FWID, 0xFFFFFFFF + .equ _HT32FWID, 0x00066246 +*/ + + .equ HT32F66246, 31 + .equ HT32F66242, 33 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .if USE_HT32_CHIP == 0 + .equ _HT32FWID, 0x00066246 + .endif + .if USE_HT32_CHIP == HT32F66246 + .equ _HT32FWID, 0x00066246 + .endif + .if USE_HT32_CHIP == HT32F66242 + .equ _HT32FWID, 0x00066242 + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .if (USE_HT32_CHIP==HT32F66246) + .long CAN0_IRQHandler /* 07, 23, 0x05C, */ + .else + .long _RESERVED /* 07, 23, 0x05C, */ + .endif + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long CORDIC_IRQHandler /* 09, 25, 0x064, */ + .long MCTM0_BRK_IRQHandler /* 10, 26, 0x068, */ + .long MCTM0_UP_IRQHandler /* 11, 27, 0x06C, */ + .long MCTM0_TR_UP2_IRQHandler /* 12, 28, 0x070, */ + .long MCTM0_CC_IRQHandler /* 13, 29, 0x074, */ + .long GPTM0_G_IRQHandler /* 14, 30, 0x078, */ + .long GPTM0_VCLK_IRQHandler /* 15, 31, 0x07C, */ + .long BFTM0_IRQHandler /* 16, 32, 0x080, */ + .long BFTM1_IRQHandler /* 17, 33, 0x084, */ + .long CMP0_IRQHandler /* 18, 34, 0x088, */ + .long CMP1_IRQHandler /* 19, 35, 0x08C, */ + .long PID_IRQHandler /* 20, 36, 0x090, */ + .long I2C0_IRQHandler /* 21, 37, 0x094, */ + .long SPI0_IRQHandler /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long UART0_IRQHandler /* 24, 40, 0x0A0, */ + .long PDMA_CH0_1_IRQHandler /* 25, 41, 0x0A4, */ + .long PDMA_CH2_3_IRQHandler /* 26, 42, 0x0A8, */ + .long PDMA_CH4_5_IRQHandler /* 27, 43, 0x0AC, */ + .long SCTM0_IRQHandler /* 28, 44, 0x0B0, */ + .long SCTM1_IRQHandler /* 29, 45, 0x0B4, */ + .long SCTM2_IRQHandler /* 30, 46, 0x0B8, */ + .long SCTM3_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ CAN0_IRQHandler + IRQ ADC_IRQHandler + IRQ CORDIC_IRQHandler + IRQ MCTM0_BRK_IRQHandler + IRQ MCTM0_UP_IRQHandler + IRQ MCTM0_TR_UP2_IRQHandler + IRQ MCTM0_CC_IRQHandler + IRQ GPTM0_G_IRQHandler + IRQ GPTM0_VCLK_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ CMP0_IRQHandler + IRQ CMP1_IRQHandler + IRQ PID_IRQHandler + IRQ I2C0_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_3_IRQHandler + IRQ PDMA_CH4_5_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ SCTM2_IRQHandler + IRQ SCTM3_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_17.s b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_17.s new file mode 100644 index 00000000000..d5be1f4cd53 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/emStudio/startup_ht32f5xxxx_es_17.s @@ -0,0 +1,195 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* Holtek Semiconductor Inc. */ +/* */ +/* Copyright (C) Holtek Semiconductor Inc. */ +/* All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------------------------------------- +; File Name : startup_ht32f5xxxx_es_17.s +; Version : $Rev:: 7030 $ +; Date : $Date:: 2023-07-18 #$ +; Description : Startup code. +;-----------------------------------------------------------------------------------------------------------*/ + +/* +; Supported Device +; ======================================== +; HT32F52234, HT32F52244 +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ +/* +;// HT32 Device +;// <0=> By Project Asm Define +;// <33=> HT32F52234/44 +*/ + .equ USE_HT32_CHIP_SET, 0 + + .equ _HT32FWID, 0xFFFFFFFF +/* + .equ _HT32FWID, 0x00052234 + .equ _HT32FWID, 0x00052244 +*/ + + .equ HT32F52234_44, 33 + + .if USE_HT32_CHIP_SET == 0 + .else + .equ USE_HT32_CHIP, USE_HT32_CHIP_SET + .endif + + .equ _RESERVED, 0xFFFFFFFF +/* +;******************************************************************************* +; Fill-up the Vector Table entries with the exceptions ISR address +;********************************************************************************/ + .syntax unified + .global reset_handler + .global Reset_Handler + .equ Reset_Handler, reset_handler + + .section .vectors, "ax" + .section .vectors, "ax" + .code 16 + .balign 2 + .global _vectors +_vectors: + .long __stack_end__ /* ---, 00, 0x000, Top address of Stack */ + .long reset_handler /* ---, 01, 0x004, Reset Handler */ + .long NMI_Handler /* -14, 02, 0x008, NMI Handler */ + .long HardFault_Handler /* -13, 03, 0x00C, Hard Fault Handler */ + .long _RESERVED /* ---, 04, 0x010, Reserved */ + .long _RESERVED /* ---, 05, 0x014, Reserved */ + .long _RESERVED /* ---, 06, 0x018, Reserved */ + .long _RESERVED /* ---, 07, 0x01C, Reserved */ + .long _HT32FWID /* ---, 08, 0x020, Reserved */ + .long _RESERVED /* ---, 09, 0x024, Reserved */ + .long _RESERVED /* ---, 10, 0x028, Reserved */ + .long SVC_Handler /* -05, 11, 0x02C, SVC Handler */ + .long _RESERVED /* ---, 12, 0x030, Reserved */ + .long _RESERVED /* ---, 13, 0x034, Reserved */ + .long PendSV_Handler /* -02, 14, 0x038, PendSV Handler */ + .long SysTick_Handler /* -01, 15, 0x03C, SysTick Handler */ + + /* External Interrupt Handler */ + .long LVD_BOD_IRQHandler /* 00, 16, 0x040, */ + .long RTC_IRQHandler /* 01, 17, 0x044, */ + .long FLASH_IRQHandler /* 02, 18, 0x048, */ + .long EVWUP_IRQHandler /* 03, 19, 0x04C, */ + .long EXTI0_1_IRQHandler /* 04, 20, 0x050, */ + .long EXTI2_3_IRQHandler /* 05, 21, 0x054, */ + .long EXTI4_15_IRQHandler /* 06, 22, 0x058, */ + .long DAC0_1_IRQHandler /* 07, 23, 0x05C, */ + .long ADC_IRQHandler /* 08, 24, 0x060, */ + .long I2C2_IRQHandler /* 09, 25, 0x064, */ + .long _RESERVED /* 10, 26, 0x068, */ + .long _RESERVED /* 11, 27, 0x06C, */ + .long _RESERVED /* 12, 28, 0x070, */ + .long SCTM0_IRQHandler /* 13, 29, 0x074, */ + .long SCTM1_IRQHandler /* 14, 30, 0x078, */ + .long PWM0_IRQHandler /* 15, 31, 0x07C, */ + .long _RESERVED /* 16, 32, 0x080, */ + .long BFTM0_IRQHandler /* 17, 33, 0x084, */ + .long BFTM1_IRQHandler /* 18, 34, 0x088, */ + .long I2C0_IRQHandler /* 19, 35, 0x08C, */ + .long I2C1_IRQHandler /* 20, 36, 0x090, */ + .long SPI0_IRQHandler /* 21, 37, 0x094, */ + .long _RESERVED /* 22, 38, 0x098, */ + .long USART0_IRQHandler /* 23, 39, 0x09C, */ + .long _RESERVED /* 24, 40, 0x0A0, */ + .long UART0_IRQHandler /* 25, 41, 0x0A4, */ + .long _RESERVED /* 26, 42, 0x0A8, */ + .long _RESERVED /* 27, 43, 0x0AC, */ + .long _RESERVED /* 28, 44, 0x0B0, */ + .long _RESERVED /* 29, 45, 0x0B4, */ + .long PDMA_CH0_1_IRQHandler /* 30, 46, 0x0B8, */ + .long PDMA_CH2_5_IRQHandler /* 31, 47, 0x0BC, */ + + + + .thumb + + +/* Reset Handler */ + + .section .text.reset_handler + .weak reset_handler + .type reset_handler, %function +reset_handler: + LDR R0, =__stack_end__ /* set stack pointer */ + MOV SP, R0 + LDR R0, =SystemInit + BLX R0 + BL _start + .size Reset_Handler, .-Reset_Handler + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ LVD_BOD_IRQHandler + IRQ RTC_IRQHandler + IRQ FLASH_IRQHandler + IRQ EVWUP_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ DAC0_1_IRQHandler + IRQ ADC_IRQHandler + IRQ I2C2_IRQHandler + IRQ SCTM0_IRQHandler + IRQ SCTM1_IRQHandler + IRQ PWM0_IRQHandler + IRQ BFTM0_IRQHandler + IRQ BFTM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ SPI0_IRQHandler + IRQ USART0_IRQHandler + IRQ UART0_IRQHandler + IRQ PDMA_CH0_1_IRQHandler + IRQ PDMA_CH2_5_IRQHandler + + .end diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f0006.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f0006.c new file mode 100644 index 00000000000..aa9578190f2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f0006.c @@ -0,0 +1,478 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f0006.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F0006 +// HT32F61352 + +//#define USE_HT32F0006 +//#define USE_HT32F61352 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 24 MHz to 48 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 48 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 24 MHz +// 1 WS: 24 MHz < CK_AHB <= 48 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_NF2_DIV (4) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = ((HSE or HSI) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 48000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 48000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 48000000UL +#define WS0_CLK 24000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + HT_CKCU->LPCR = 1; /* configure Backup domain isolation */ + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = ((HSI_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((HSE_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5826.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5826.c new file mode 100644 index 00000000000..9e59781925b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5826.c @@ -0,0 +1,508 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5826.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F5826 + +//#define USE_HT32F5826 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// Not apply to HT32F52220/30 +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = ((HSE or HSI) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 24 MHz to 48 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 48 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE (Not apply to HT32F52220/30) +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <9=> AUTO +// HT32F52331/41/42/52, HT32F5826 +// 0 WS: 1 kHz <= CK_AHB <= 24 MHz +// 1 WS: 24 MHz < CK_AHB <= 48 MHz +// HT32F52220/30/31/41/43/53 +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable (HT3F52342/52, HT32F5826 Only) +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_NF2_DIV (6) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = ((HSE or HSI) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if !defined(USE_HT32F52220_30) +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 48000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 48000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #ifdef USE_HT32F52220_30 + #error "CK_LSE can not be the source of SystemCoreClock for HT32F52220/30" + #else + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#if defined(USE_HT32F52331_41) || defined(USE_HT32F52342_52) || defined(USE_HT32F5826) + #define CKAHB_MIN 1000UL + #define CKAHB_MAX 48000000UL + #define WS0_CLK 24000000UL +#endif + +#if defined(USE_HT32F52220_30) || defined(USE_HT32F52231_41) || defined(USE_HT32F52243_53) + #define CKAHB_MIN 1000UL + #define CKAHB_MAX 40000000UL + #define WS0_CLK 20000000UL +#endif + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + HT_CKCU->LPCR = 1; /* configure Backup domain isolation */ + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + + while ((HT_PWRCU->CR & 0x00000200) != 0x00000200) /* Backup domain register access test */ + HT_PWRCU->CR = 0x00000200; + while ((HT_PWRCU->CR & 0x00000200) != 0x00000000) + HT_PWRCU->CR = 0x00000000; + HT_CKCU->LPCR = 0; + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if !defined(USE_HT32F52220_30) +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = ((HSI_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((HSE_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + #ifndef USE_HT32F52220_30 + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + #endif + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_01.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_01.c new file mode 100644 index 00000000000..e6f4c361e5d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_01.c @@ -0,0 +1,518 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_01.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F52220, HT32F52230 +// HT32F52231, HT32F52241 +// HT32F52331, HT32F52341 +// HT32F52342, HT32F52352 +// HT32F52243, HT32F52253 +// HT50F32003 + +//#define USE_HT32F52220_30 +//#define USE_HT32F52231_41 +//#define USE_HT32F52331_41 +//#define USE_HT32F52342_52 +//#define USE_HT32F52243_53 +//#define USE_HT50F32003 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// Not apply to HT32F52220/30 +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = ((HSE or HSI) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 24 MHz to 48 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 48 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE (Not apply to HT32F52220/30) +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <9=> AUTO +// HT32F52331/41/42/52 +// 0 WS: 1 kHz <= CK_AHB <= 24 MHz +// 1 WS: 24 MHz < CK_AHB <= 48 MHz +// HT32F52220/30/31/41/43/53 +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable (HT3F52342/52 Only) +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_NF2_DIV (6) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = ((HSE or HSI) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if !defined(USE_HT32F52220_30) +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 48000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 48000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #ifdef USE_HT32F52220_30 + #error "CK_LSE can not be the source of SystemCoreClock for HT32F52220/30" + #else + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#if defined(USE_HT32F52331_41) || defined(USE_HT32F52342_52) + #define CKAHB_MIN 1000UL + #define CKAHB_MAX 48000000UL + #define WS0_CLK 24000000UL +#endif + +#if defined(USE_HT32F52220_30) || defined(USE_HT32F52231_41) || defined(USE_HT32F52243_53) + #define CKAHB_MIN 1000UL + #define CKAHB_MAX 40000000UL + #define WS0_CLK 20000000UL +#endif + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + HT_CKCU->LPCR = 1; /* configure Backup domain isolation */ + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + + while ((HT_PWRCU->CR & 0x00000200) != 0x00000200) /* Backup domain register access test */ + HT_PWRCU->CR = 0x00000200; + while ((HT_PWRCU->CR & 0x00000200) != 0x00000000) + HT_PWRCU->CR = 0x00000000; + HT_CKCU->LPCR = 0; + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if !defined(USE_HT32F52220_30) +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#ifdef USE_HT32F52342_52 +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = ((HSI_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((HSE_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + #ifndef USE_HT32F52220_30 + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + #endif + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_02.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_02.c new file mode 100644 index 00000000000..f8647355441 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_02.c @@ -0,0 +1,525 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_02.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6953 $ + * @date $Date:: 2023-05-30 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F52220, HT32F52230 +// HT32F52231, HT32F52241 +// HT32F52331, HT32F52341 +// HT32F52342, HT32F52352 +// HT32F52243, HT32F52253 +// HT32F62030, HT32F62040, HT32F62050 +// HT32F67232, HT32F67233 +// HT32F67741, + +//#define USE_HT32F52220_30 +//#define USE_HT32F52231_41 +//#define USE_HT32F52331_41 +//#define USE_HT32F52342_52 +//#define USE_HT32F52243_53 +//#define USE_HT32F62030 +//#define USE_HT32F62040 +//#define USE_HT32F62050 +//#define USE_HT32F67232 +//#define USE_HT32F67233 +//#define USE_HT32F67741 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// Not apply to HT32F52220/30 +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = ((HSE or HSI) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 24 MHz to 48 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 48 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE (Not apply to HT32F52220/30) +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <9=> AUTO +// HT32F52331/41/42/52 +// 0 WS: 1 kHz <= CK_AHB <= 24 MHz +// 1 WS: 24 MHz < CK_AHB <= 48 MHz +// HT32F52220/30/31/41/43/53 +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable (HT3F52342/52 Only) +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_NF2_DIV (5) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = ((HSE or HSI) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if !defined(USE_HT32F52220_30) +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 48000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 48000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #ifdef USE_HT32F52220_30 + #error "CK_LSE can not be the source of SystemCoreClock for HT32F52220/30" + #else + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#if defined(USE_HT32F52331_41) || defined(USE_HT32F52342_52) + #define CKAHB_MIN 1000UL + #define CKAHB_MAX 48000000UL + #define WS0_CLK 24000000UL +#endif + +#if defined(USE_HT32F52220_30) || defined(USE_HT32F52231_41) || defined(USE_HT32F52243_53) + #define CKAHB_MIN 1000UL + #define CKAHB_MAX 40000000UL + #define WS0_CLK 20000000UL +#endif + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + HT_CKCU->LPCR = 1; /* configure Backup domain isolation */ + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + + while ((HT_PWRCU->CR & 0x00000200) != 0x00000200) /* Backup domain register access test */ + HT_PWRCU->CR = 0x00000200; + while ((HT_PWRCU->CR & 0x00000200) != 0x00000000) + HT_PWRCU->CR = 0x00000000; + HT_CKCU->LPCR = 0; + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if !defined(USE_HT32F52220_30) +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#ifdef USE_HT32F52342_52 +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = ((HSI_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((HSE_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + #ifndef USE_HT32F52220_30 + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + #endif + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_03.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_03.c new file mode 100644 index 00000000000..4da04c838a3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_03.c @@ -0,0 +1,518 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_03.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 7370 $ + * @date $Date:: 2023-12-06 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F0008 +// HT32F52142 +// HT32F52344, HT32F52354 +// HT32F52357, HT32F52367 +// HT32F65230, HT32F65240 +// HT50F3200T + +//#define USE_HT32F0008 +//#define USE_HT32F52142 +//#define USE_HT32F52344_54 +//#define USE_HT32F52357_67 +//#define USE_HT32F65230_40 +//#define USE_HT50F3200T + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// Enable Waiting LSE Clock Ready +// Default Waiting LSE Clock Ready = ENABLE +// +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable (HT32F52357/67, HT32F65230/40, HT50F3200T Only) +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_WAIT_READY (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #ifndef USE_HT32F65230_40 + ResetBit_BB((u32)(&HT_CKCU->GCCR), 3); /* disable USB PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 9); /* select USB PLL source as HSI */ + #endif + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + #if (LSE_WAIT_READY == 1) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ + #endif +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if defined(USE_HT32F52357_67) || defined(USE_HT32F65230_40) +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_04.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_04.c new file mode 100644 index 00000000000..b709d27c6f7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_04.c @@ -0,0 +1,335 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_04.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 7119 $ + * @date $Date:: 2023-08-15 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F50220, HT32F50230 +// HT32F50231, HT32F50241 +// HT50F32002 +// HT32F59041 +// HF5032 +// HT32F61641 +// HT32F59046 +// HT32F61041 + +//#define USE_HT32F50220_30 +//#define USE_HT32F50231_41 +//#define USE_HT50F32002 +//#define USE_HT32F59041 +//#define USE_HF5032 +//#define USE_HT32F61641 +//#define USE_HT32F59046 +//#define USE_HT32F61041 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 2 +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define HCLK_SRC (2) /*!< 0: N/A 1: N/A 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 20000000UL) + #error "CK_HSI clock issue: must be 20 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 20000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 20 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 20000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_CKCU->AHBCFGR = 1; /* set CK_AHB prescaler */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2)) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3)) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_05.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_05.c new file mode 100644 index 00000000000..e0460f199e0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_05.c @@ -0,0 +1,497 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_05.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6993 $ + * @date $Date:: 2023-06-26 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F57331, HT32F57341 +// HT32F57342, HT32F57352 +// HT32F59741 +// HT32F5828 +// HT32F67742 +// HT32F59746 + +//#define USE_HT32F57331_41 +//#define USE_HT32F57342_52 +//#define USE_HT32F59741 +//#define USE_HT32F5828 +//#define USE_HT32F67742 +//#define USE_HT32F59746 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 3); /* disable USB PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 9); /* select USB PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_06.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_06.c new file mode 100644 index 00000000000..3be16d53197 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_06.c @@ -0,0 +1,488 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_06.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F50343 + + +//#define USE_HT32F50343 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 3); /* disable USB PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 9); /* select USB PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_07.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_07.c new file mode 100644 index 00000000000..3eb3d41a9c6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_07.c @@ -0,0 +1,482 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_07.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F0006 +// HT32F61352 +// HT32F61355 +// HT32F61356 +// HT32F61357 + +//#define USE_HT32F0006 +//#define USE_HT32F61352 +//#define USE_HT32F61355_56_57 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL clock source x NF2 +// PLL feedback clock must be in the range of 24 MHz to 48 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 48 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 24 MHz +// 1 WS: 24 MHz < CK_AHB <= 48 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_NF2_DIV (4) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 9: WS = AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = ((HSE or HSI) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO (HSI_VALUE * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO (HSE_VALUE * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 48000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 48000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 48000000UL +#define WS0_CLK 24000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + HT_CKCU->LPCR = 1; /* configure Backup domain isolation */ + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllFeedbackClockDiv = ((HT_CKCU->PLLCFGR >> 23) == 0) ? (16) : (HT_CKCU->PLLCFGR >> 23); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = ((HSI_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((HSE_VALUE * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_08.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_08.c new file mode 100644 index 00000000000..e20480f1ed1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_08.c @@ -0,0 +1,518 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_08.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6877 $ + * @date $Date:: 2023-05-04 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F65230, HT32F65240 +// HT32F65232 +// MXTX6306 +// HT50F3200S + +//#define USE_HT32F65230_40 +//#define USE_HT32F65232 +//#define USE_MXTX6306 +//#define USE_HT50F3200S + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// HT32F65230/65240, MXTX6306, HT50F3200S Only +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE (HT32F65230/65240, MXTX6306, HT50F3200S Only) +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable (HT32F52357/67, HT32F65230/40, MXTX6306, HT50F3200S Only) +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if defined(USE_HT32F65230_40) +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif +#endif +#if defined(USE_HT32F65232) + #if (LSE_ENABLE == 1) + #error "Dose not support LSE!" + #endif +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if defined(USE_HT32F65230_40) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif + #if defined(USE_HT32F65232) + #error "Dose not support LSE!" + #endif + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if defined(USE_HT32F65230_40) +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable VDD power domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + #if defined(USE_HT32F65230_40) + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + #endif + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_09.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_09.c new file mode 100644 index 00000000000..a7b5f240910 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_09.c @@ -0,0 +1,489 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_09.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F54231, HT32F54241 +// HT32F54243, HT32F54253 + +//#define USE_HT32F54231_41 +//#define USE_HT32F54243_53 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x1 << 11); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 3); /* disable USB PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 9); /* select USB PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_10.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_10.c new file mode 100644 index 00000000000..704ebb5730f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_10.c @@ -0,0 +1,455 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_10.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F61244, HT32F61245 + +//#define USE_HT32F61244_45 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 48 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 48 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 48 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (0) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (4) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 48000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 48000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 48000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + ResetBit_BB((u32)(&HT_CKCU->AHBCCR), 11); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable VDD power domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_11.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_11.c new file mode 100644 index 00000000000..d1b2c20be4f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_11.c @@ -0,0 +1,511 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_11.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F67041, HT32F67051 + +//#define USE_HT32F67041_51 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// HSE Output Clock Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// Default HSE output clock divider = 1 +// +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_CLK_DIV (1) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if (HSE_VALUE != 16000000UL) + #error "CK_HSE clock issue: must be 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_HSE definition + */ +#define __CK_HSE (HSE_VALUE >> HSE_CLK_DIV) /*!< Get CK_HSE frequency */ + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_PLL_IN frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_PLL_SRC (HSI_VALUE >> PLL_CLK_SRC_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_PLL_SRC (__CK_HSE >> PLL_CLK_SRC_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define PLL_SRC_MIN 4000000UL + #define PLL_SRC_MAX 16000000UL + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_PLL_IN frequency */ + #if ((__CK_PLL_SRC < PLL_SRC_MIN) || (__CK_PLL_SRC > PLL_SRC_MAX)) + #error "CK_PLL_SRC clock issue: must be in the range!" + #endif + + /* Get CK_VCO frequency */ + #define __CK_VCO (__CK_PLL_SRC * PLL_NF2_DIV) /*!< Get CK_VCO frequency */ + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS __CK_HSE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + ResetBit_BB((u32)(&HT_CKCU->AHBCCR), 11); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + HT_CKCU->GCFGR = (HT_CKCU->GCFGR & ~(3UL << 16)) | (HSE_CLK_DIV << 16); /* set HSE divider */ + + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + u32 HseClockDiv = (HT_CKCU->GCFGR >> 16) & 3UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = ((((HSE_VALUE >> HseClockDiv) >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = (HSE_VALUE >> HseClockDiv) >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_12.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_12.c new file mode 100644 index 00000000000..feca9dca25b --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_12.c @@ -0,0 +1,485 @@ +/***************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_12.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6597 $ + * @date $Date:: 2022-12-27 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F61141 + +//#define USE_HT32F61141 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 48 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 48 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 48 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (0) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (6) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 48000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 48000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 48000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable VDD power domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_13.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_13.c new file mode 100644 index 00000000000..c906eb16400 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_13.c @@ -0,0 +1,325 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_13.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 7119 $ + * @date $Date:: 2023-08-15 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F50020, HT32F50030 +// HT32F61630 +// HT32F61030 + +//#define USE_HT32F50020_30 +//#define USE_HT32F61630 +//#define USE_HT32F61030 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 2 +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define HCLK_SRC (2) /*!< 0: N/A 1: N/A 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 16000000UL) + #error "CK_HSI clock issue: must be 16 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 16000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_CKCU->AHBCFGR = 1; /* set CK_AHB prescaler */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2)) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3)) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_14.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_14.c new file mode 100644 index 00000000000..2dc4216f4b5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_14.c @@ -0,0 +1,487 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_14.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6790 $ + * @date $Date:: 2023-03-13 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F50442, HT32F50452 +// HT32F50431, HT32F50441 + +//#define USE_HT32F50442_52 +//#define USE_HT32F50431_41 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x1 << 11); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable VDD power domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_15.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_15.c new file mode 100644 index 00000000000..ad84d9825cd --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_15.c @@ -0,0 +1,487 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_15.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 6777 $ + * @date $Date:: 2023-03-06 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F53242, HT32F53252 +// HT32F53231, HT32F53241 + +//#define USE_HT32F53242_52 +//#define USE_HT32F53231_41 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x1 << 11); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable VDD power domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_16.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_16.c new file mode 100644 index 00000000000..5eb90ab190d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_16.c @@ -0,0 +1,472 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_16.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 7090 $ + * @date $Date:: 2023-08-02 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F66242 +// HT32F66246 + +//#define USE_HT32F66246 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 32 +// <1-32:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 64 MHz to 96 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 8 MHz to 96 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <3=> 3 WS +// <9=> AUTO +// 0 WS: 1 KHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// 3 WS: 60 MHz < CK_AHB <= 80 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (20) /*!< 1~32: DIV1~DIV32 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 3: WS = 3, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 64000000UL + #define VCO_MAX 96000000UL + #define PLL_MIN 8000000UL + #define PLL_MAX 96000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 80000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL +#define WS2_CLK 60000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS2_CLK) && (WAIT_STATE < 3) || \ + (__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x1 << 11); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x1F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS2_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 4UL); /* auto-select wait state */ + #elif (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 31UL) == 0) ? (32) : ((HT_CKCU->PLLCFGR >> 23) & 31UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_17.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_17.c new file mode 100644 index 00000000000..9eb200c4004 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_17.c @@ -0,0 +1,488 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_17.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 7027 $ + * @date $Date:: 2023-07-18 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F52234, HT32F52244 + +//#define USE_HT32F52234_44 + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed Internal RC Oscillator (HSI) +// Default HSI = ENABLE +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (0) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable VDD power domain register clock */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x1 << 11); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable VDD power domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_18.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_18.c new file mode 100644 index 00000000000..ba5073e76f2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_18.c @@ -0,0 +1,518 @@ +/**************************************************************************//** + * @file library/Device/Holtek/HT32F5xxxx/Source/system_ht32f5xxxx_18.c + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the Holtek HT32F5xxxx Device Series + * @version $Rev:: 7413 $ + * @date $Date:: 2023-12-15 #$ + * + * @note + * Copyright (C) Holtek Semiconductor Inc. All rights reserved. + * + * @par + * ARM Limited (ARM) supplies this software for Cortex-M processor-based + * microcontrollers. This file can be freely distributed within development + * tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Supported Device +// ======================================== +// HT32F0008 +// HT32F52142 +// HT32F52344, HT32F52354 +// HT32F52357, HT32F52367 +// HT32F65230, HT32F65240 +// HT50F3200T + +//#define USE_HT32F0008 +//#define USE_HT32F52142 +//#define USE_HT32F52344_54 +//#define USE_HT32F52357_67 +//#define USE_HT32F65230_40 +//#define USE_HT50F3200T + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup HT32F5xxxx_system HT32F5xxxx System + * @{ + */ + + +#include "ht32f5xxxx_01.h" + +/** @addtogroup HT32F5xxxx_System_Private_Defines + * @{ + */ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// Enable High Speed External Crystal Oscillator (HSE) +// Default HSE = DISABLE +// +// Enable Low Speed External Crystal Oscillator (LSE) +// Default LSE = DISABLE +// Enable Waiting LSE Clock Ready +// Default Waiting LSE Clock Ready = ENABLE +// +// +// Enable PLL +// Default PLL = DISABLE +// PLL Out = (((HSE or HSI) / SRC_DIV) x NF2 ) / NO2 +// PLL Clock Source +// <0=> CK_HSE +// <1=> CK_HSI +// Default PLL clock source = CK_HSI +// PLL source clock must be in the range of 4 MHz to 16 MHz +// PLL Clock Source Divider (SRC_DIV) +// <0=> 1 +// <1=> 2 +// PLL input clock = PLL Clock Source / (SRC_DIV) +// PLL Feedback Clock Divider (NF2): 1 ~ 16 +// <1-16:1> +// PLL feedback clock = PLL input clock x NF2 +// PLL feedback clock must be in the range of 24 MHz to 60 MHz +// PLL Output Clock Divider (NO2) +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// PLL output clock = PLL feedback clock / NO2 +// PLL output clock must be in the range of 4 MHz to 60 MHz +// +// +// SystemCoreClock Configuration (CK_AHB) +// SystemCoreClock Source +// <1=> CK_PLL +// <2=> CK_HSE +// <3=> CK_HSI +// <6=> CK_LSE +// <7=> CK_LSI +// Default SystemCoreClock source = CK_HSI +// SystemCoreClock Source Divider +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// Default SystemCoreClock source divider = 1 +// +// +// FLASH Configuration +// Wait state +// <0=> 0 WS +// <1=> 1 WS +// <2=> 2 WS +// <9=> AUTO +// 0 WS: 1 kHz <= CK_AHB <= 20 MHz +// 1 WS: 20 MHz < CK_AHB <= 40 MHz +// 2 WS: 40 MHz < CK_AHB <= 60 MHz +// Pre-fetch Buffer Enable +// Default pre-fetch buffer = ENABLE +// Branch cache Enable (HT32F52357/67, HT32F65230/40, HT50F3200T Only) +// Default branch cache = ENABLE +// +*/ + +/* !!! NOTICE !!! + HSI must keep turn on when doing the Flash operation (Erase/Program). +*/ + +/* !!! NOTICE !!! + * How to adjust the value of High Speed External oscillator (HSE)? + The default value of HSE is define by "HSE_VALUE" in "ht32fxxxxx_nn.h". + If your board uses a different HSE speed, please add a new compiler preprocessor + C define, "HSE_VALUE=n000000" ("n" represents n MHz) in the toolchain/IDE, + or edit the "HSE_VALUE" in the "ht32f5xxxx_conf.h" file. + Take Keil MDK-ARM for instance, to set HSE as 16 MHz: + "Option of Taret -> C/C++ > Preprocessor Symbols" + Define: USE_HT32_DRIVER, USE_HT32Fxxxxx_SK, USE_HT32Fxxxxx_xx, USE_MEM_HT32Fxxxxx, HSE_VALUE=16000000 + ^^ Add "HSE_VALUE" + define as above. +*/ +#define HSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define HSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define LSI_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define LSE_WAIT_READY (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define PLL_CLK_SRC (1) /*!< 0: HSE, 1: HSI */ +#define PLL_CLK_SRC_DIV (1) /*!< 0: DIV1, 1: DIV2 */ +#define PLL_NF2_DIV (15) /*!< 1~16: DIV1~DIV16 */ +#define PLL_NO2_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8 */ +#define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: LSI */ +#define HCLK_DIV (0) /*!< 0: DIV1, 1: DIV2, 2: DIV4, 3: DIV8, 4: DIV16, 5: DIV32 */ +#define WAIT_STATE (9) /*!< 0: WS = 0, 1: WS = 1, 2: WS = 2, 9: AUTO */ +#define PRE_FETCH_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define BCACHE_ENABLE (1) /*!< 0: DISABLE, 1: ENABLE */ +#define DEINIT_ENABLE (1) /* Set 0 for reduce code size */ + +/*----------------------------------------------------------------------------------------------------------*/ +/* PLL Out = (((HSE or HSI) / (PLL_CLK_SRC_DIV + 1)) x PLL_NF2) / PLL_NO2 */ +/*----------------------------------------------------------------------------------------------------------*/ + + +/*--------------------- WDT Configuration ---------------------------------- +// +// Enable WDT Configuration +// WDT Prescaler Selection +// <0=> CK_WDT / 1 +// <1=> CK_WDT / 2 +// <2=> CK_WDT / 4 +// <3=> CK_WDT / 8 +// <4=> CK_WDT / 16 +// <5=> CK_WDT / 32 +// <6=> CK_WDT / 64 +// <7=> CK_WDT / 128 +// WDT Reload Value <1-4095:1> +// Enable WDT Reset function +// WDT Sleep Halt mode +// <0=> No halt +// <1=> Halt in DeepSleep1 +// <2=> Halt in Sleep & DeepSleep1 +// +*/ +#define WDT_ENABLE (0) /*!< 0: DISABLE, 1: ENABLE */ +#define WDT_PRESCALER (5) /*!< 0: 1/1, 1: 1/2, 2: 1/4, 3: 1/8, 4: 1/16, 5: 1/32, 6: 1/64, 7: 1/128 */ +#define WDT_RELOAD (2000) /*!< 0 ~ 4095, 12 bit */ +#define WDT_RESET_ENABLE (1) /*!< 0: No Reset, 1: Reset when WDT over flow */ +#define WDT_SLEEP_HALT (2) /*!< 0: No halt, 1: Halt in DeepSleep1, 2: Halt in Sleep & DeepSleep1 */ + +/** + * @brief Check HSI frequency + */ +#if (HSI_VALUE != 8000000UL) + #error "CK_HSI clock issue: must be 8 MHz!" +#endif + +/** + * @brief Check HSE frequency + */ +#if ((HSE_VALUE < 4000000UL) || (HSE_VALUE > 16000000UL)) + #error "CK_HSE clock issue: must be in the range of 4 MHz to 16 MHz!" +#endif + +/** + * @brief Check LSI frequency + */ +#if (LSI_VALUE != 32000UL) + #error "CK_LSI clock issue: must be 32 kHz!" +#endif + +/** + * @brief Check LSE frequency + */ +#if (LSE_VALUE != 32768UL) + #error "CK_LSE clock issue: must be 32.768 kHz!" +#endif + +/** + * @brief CK_PLL definition + */ +#if (PLL_ENABLE == 1) + /* Get CK_VCO frequency */ + #if (PLL_CLK_SRC == 1) + #if (HSI_ENABLE == 0) + #error "CK_PLL clock source issue: HSI has not been enabled" + #else + #define __CK_VCO ((HSI_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSI as PLL source */ + #endif + #else + #if (HSE_ENABLE == 0) + #error "CK_PLL clock source issue: HSE has not been enabled!" + #else + #define __CK_VCO ((HSE_VALUE >> PLL_CLK_SRC_DIV) * PLL_NF2_DIV) /*!< Select HSE as PLL source */ + #endif + #endif + + #define VCO_MIN 24000000UL + #define VCO_MAX 60000000UL + #define PLL_MIN 4000000UL + #define PLL_MAX 60000000UL + + /* Check CK_VCO frequency */ + #if ((__CK_VCO < VCO_MIN) || (__CK_VCO > VCO_MAX)) + #error "CK_VCO clock issue: must be in the range!" + #endif + + #define __CK_PLL (__CK_VCO >> PLL_NO2_DIV) /*!< Get CK_PLL frequency */ + + /* Check CK_PLL frequency */ + #if ((__CK_PLL < PLL_MIN) || (__CK_PLL > PLL_MAX)) + #error "CK_PLL clock issue: must be in the range!" + #endif +#endif + +/** + * @brief CK_SYS definition + */ +#if (HCLK_SRC == 1) + #if (PLL_ENABLE == 1) + #define __CK_SYS __CK_PLL /*!< Select PLL as CK_SYS source */ + #else + #error "CK_SYS clock source issue: PLL is not enable!" + #endif +#elif (HCLK_SRC == 2) + #if (HSE_ENABLE == 1) + #define __CK_SYS HSE_VALUE /*!< Select HSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSE is not enable!" + #endif +#elif (HCLK_SRC == 3) + #if (HSI_ENABLE == 1) + #define __CK_SYS HSI_VALUE /*!< Select HSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: HSI is not enable!" + #endif +#elif (HCLK_SRC == 6) + #if (LSE_ENABLE == 1) + #define __CK_SYS LSE_VALUE /*!< Select LSE as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSE is not enable!" + #endif +#elif (HCLK_SRC == 7) + #if (LSI_ENABLE == 1) + #define __CK_SYS LSI_VALUE /*!< Select LSI as CK_SYS source */ + #else + #error "CK_SYS clock source issue: LSI is not enable!" + #endif +#else + #error "CK_SYS clock source issue: No clock source is selected!" +#endif + +/** + * @brief CK_AHB definition + */ +#define __CK_AHB (__CK_SYS >> HCLK_DIV) /*!< Get CK_AHB frequency */ + +#define CKAHB_MIN 1000UL +#define CKAHB_MAX 60000000UL +#define WS0_CLK 20000000UL +#define WS1_CLK 40000000UL + +/* Check CK_AHB frequency */ +#if ((__CK_AHB < CKAHB_MIN) || (__CK_AHB > CKAHB_MAX)) + #error "CK_AHB clock issue: must be in the range!" +#endif + +/* Check FLASH wait-state setting */ +#if ((__CK_AHB > WS1_CLK) && (WAIT_STATE < 2) || \ + (__CK_AHB > WS0_CLK) && (WAIT_STATE < 1)) + #error "FLASH wait state configuration issue!" +#endif +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Variables + * @{ + */ +__IO uint32_t SystemCoreClock = __CK_AHB; /*!< SystemCoreClock = CK_AHB */ +/** + * @} + */ + +/** @addtogroup HT32F5xxxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initializes the system clocks and the embedded Flash. + * @note This function should be used after reset. + * @retval None + */ +void SystemInit(void) +{ +#if (WDT_ENABLE == 1) + HT_CKCU->APBCCR1 |= (0x1 << 4); + HT_WDT->PR = 0x35CA; + HT_WDT->MR0 = 0; + HT_WDT->MR1 = ((HT_WDT->MR1 & 0xFFF) | (WDT_PRESCALER << 12)); + HT_WDT->MR0 = WDT_RELOAD | (WDT_RESET_ENABLE << 13) | (WDT_SLEEP_HALT << 14) | (0x1 << 16); + HT_WDT->CR = 0x5FA00001; +#else + #if (DEINIT_ENABLE == 1) + HT_RSTCU->APBPRST1 = (1 << 4); + #endif +#endif + + SetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* enable Backup domain register clock */ + while (HT_PWRCU->TEST != 0x27); /* wait for Backup domain register ready */ + + #if (DEINIT_ENABLE == 1) + /* De-init the setting */ + HT_CKCU->AHBCCR &= ~(0x3 << 10); /* disable IP who may use PLL as source */ + SetBit_BB((u32)(&HT_CKCU->GCCR), 11); /* enable HSI */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 3)); /* wait for HSI ready */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | 3UL); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != 3UL); /* wait for clock switch complete */ + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 1UL); /* set Wait State as 0 WS */ + HT_CKCU->AHBCFGR = 0; /* set CK_AHB prescaler */ + ResetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* disable PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #ifndef USE_HT32F65230_40 + ResetBit_BB((u32)(&HT_CKCU->GCCR), 3); /* disable USB PLL */ + SetBit_BB((u32)(&HT_CKCU->GCFGR), 9); /* select USB PLL source as HSI */ + #endif + #endif + + /* HSE initiation */ +#if (HSE_ENABLE == 1) + SetBit_BB((u32)(&HT_CKCU->GCCR), 10); /* enable HSE */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 2)){}; /* wait for HSE ready */ +#endif + + /* LSE initiation */ +#if (LSE_ENABLE == 1) + do { + SetBit_BB((u32)(&HT_RTC->CR), 3); /* enable LSE */ + } while (!GetBit_BB((u32)(&HT_RTC->CR), 3)); + #if (LSE_WAIT_READY == 1) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 4)); /* wait for LSE ready */ + #endif +#endif + + ResetBit_BB((u32)(&HT_CKCU->APBCCR1), 6); /* disable Backup domain register clock */ + + /* LSI initiation */ +#if (HCLK_SRC == 7) + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 5)){}; /* wait for LSI ready */ +#endif + + /* PLL initiation */ +#if (PLL_ENABLE == 1) + HT_CKCU->PLLCFGR = ((PLL_NF2_DIV & 0x0F) << 23) | (PLL_NO2_DIV << 21); /* set PLL divider */ + + #if (PLL_CLK_SRC_DIV == 1) + SetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* set PLL clock source divider */ + #else + ResetBit_BB((u32)(&HT_CKCU->PLLCFGR), 28); /* reset PLL clock source divider */ + #endif + + #if (PLL_CLK_SRC == 0) + ResetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSE */ + #else + SetBit_BB((u32)(&HT_CKCU->GCFGR), 8); /* select PLL source as HSI */ + #endif + + SetBit_BB((u32)(&HT_CKCU->GCCR), 9); /* enable PLL */ + while (!GetBit_BB((u32)(&HT_CKCU->GCSR), 1)){}; /* wait for PLL ready */ +#endif + + /* CK_AHB initiation */ +#if (WAIT_STATE == 9) + #if (__CK_AHB > WS1_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 3UL); /* auto-select wait state */ + #elif (__CK_AHB > WS0_CLK) + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | 2UL); /* auto-select wait state */ + #endif +#else + HT_FLASH->CFCR = (((HT_FLASH->CFCR) & ~7UL) | (WAIT_STATE + 1)); /* manual wait state */ +#endif + + HT_CKCU->AHBCFGR = HCLK_DIV; /* set CK_AHB prescaler */ + HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source */ + while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete */ + + /* Pre-fetch buffer configuration */ +#if (PRE_FETCH_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 4); /* 0: pre-fetch disable, 1: pre-fetch enable */ +#endif + + /* Branch cache configuration */ +#if defined(USE_HT32F52357_67) || defined(USE_HT32F65230_40) +#if (BCACHE_ENABLE == 0) + ResetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#else + SetBit_BB((u32)(&HT_FLASH->CFCR), 12); /* 0: branch cache disable, 1: branch cache enable */ +#endif +#endif + + /* HSE power down */ +#if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 10); +#endif + + /* HSI power down */ +#if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) + ResetBit_BB((u32)(&HT_CKCU->GCCR), 11); +#endif +} + +/** + * @brief Update SystemCoreClock + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + u32 SystemCoreClockDiv = HT_CKCU->AHBCFGR & 7UL; + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + u32 PllFeedbackClockDiv = (((HT_CKCU->PLLCFGR >> 23) & 15UL) == 0) ? (16) : ((HT_CKCU->PLLCFGR >> 23) & 15UL); + u32 PllOutputClockDiv = (HT_CKCU->PLLCFGR >> 21) & 3UL; + u32 SystemCoreClockSrc = HT_CKCU->CKST & 7UL; + + /* Get system core clock according to global clock control & configuration registers */ + if (SystemCoreClockSrc == 1) + { + if (GetBit_BB((u32)(&HT_CKCU->PLLCR), 31)) + { + PllFeedbackClockDiv = 1; + PllOutputClockDiv = 0; + } + + if (GetBit_BB((u32)(&HT_CKCU->GCFGR), 8)) + { + SystemCoreClock = (((HSI_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + else + { + SystemCoreClock = (((HSE_VALUE >> PllSourceClockDiv) * PllFeedbackClockDiv) >> PllOutputClockDiv) >> SystemCoreClockDiv; + } + } + else if (SystemCoreClockSrc == 2) + { + SystemCoreClock = HSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 3) + { + SystemCoreClock = HSI_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 6) + { + SystemCoreClock = LSE_VALUE >> SystemCoreClockDiv; + } + else if (SystemCoreClockSrc == 7) + { + SystemCoreClock = LSI_VALUE >> SystemCoreClockDiv; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT Holtek Semiconductor Inc. *****END OF FILE*** */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32.h new file mode 100644 index 00000000000..ccedbb647f8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32.h @@ -0,0 +1,35 @@ +/*********************************************************************************************************//** + * @file ht32.h + * @version $Rev:: 1704 $ + * @date $Date:: 2017-08-17 #$ + * @brief The API between application and HT32FXXXX Firmware Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_H +#define __HT32_H + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_01.h" + +#endif /* __HT32_H -----------------------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_cm0plus_misc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_cm0plus_misc.h new file mode 100644 index 00000000000..8919d357bc9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_cm0plus_misc.h @@ -0,0 +1,132 @@ +/*********************************************************************************************************//** + * @file ht32_cm0plus_misc.h + * @version $Rev:: 750 $ + * @date $Date:: 2016-05-31 #$ + * @brief All the function prototypes for the miscellaneous firmware library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_CM0PLUS_MISC_H +#define __HT32_CM0PLUS_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32_Peripheral_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Exported_Constants MISC exported constants + * @{ + */ + +/* Vector Table Base */ +#define NVIC_VECTTABLE_RAM ((u32)0x20000000) +#define NVIC_VECTTABLE_FLASH ((u32)0x00000000) + +#define IS_NVIC_VECTTABLE(VECTTABLE) ((VECTTABLE == NVIC_VECTTABLE_RAM) || \ + (VECTTABLE == NVIC_VECTTABLE_FLASH)) + +#define IS_NVIC_OFFSET(OFFSET) (OFFSET < 0x0001FFFF) + +/* System Low Power */ +#define NVIC_LOWPOWER_SEVONPEND ((u8)0x10) +#define NVIC_LOWPOWER_SLEEPDEEP ((u8)0x04) +#define NVIC_LOWPOWER_SLEEPONEXIT ((u8)0x02) + +#define IS_NVIC_LOWPOWER(LOWPOWER) ((LOWPOWER == NVIC_LOWPOWER_SEVONPEND) || \ + (LOWPOWER == NVIC_LOWPOWER_SLEEPDEEP) || \ + (LOWPOWER == NVIC_LOWPOWER_SLEEPONEXIT)) + +/* System Handler */ +#define SYSTEMHANDLER_NMI ((u32)0x80000000) +#define SYSTEMHANDLER_PSV ((u32)0x10000000) +#define SYSTEMHANDLER_SYSTICK ((u32)0x04000000) +#define SYSTEMHANDLER_ALL ((u32)0x94000000) + +#define IS_NVIC_SYSTEMHANDLER(HANDLER) ((HANDLER == SYSTEMHANDLER_NMI) || \ + (HANDLER == SYSTEMHANDLER_PSV) || \ + (HANDLER == SYSTEMHANDLER_SYSTICK) ||\ + (HANDLER == SYSTEMHANDLER_ALL)) + +/* SysTick clock source */ +#define SYSTICK_SRC_STCLK ((u32)0xFFFFFFFB) +#define SYSTICK_SRC_FCLK ((u32)0x00000004) + +#define IS_SYSTICK_CLOCK_SOURCE(SOURCE) ((SOURCE == SYSTICK_SRC_STCLK) || \ + (SOURCE == SYSTICK_SRC_FCLK) ) + +/* SysTick counter state */ +#define SYSTICK_COUNTER_DISABLE ((u32)0xFFFFFFFE) +#define SYSTICK_COUNTER_ENABLE ((u32)0x00000001) +#define SYSTICK_COUNTER_CLEAR ((u32)0x00000000) + +#define IS_SYSTICK_COUNTER(COUNTER) ((COUNTER == SYSTICK_COUNTER_DISABLE) || \ + (COUNTER == SYSTICK_COUNTER_ENABLE) || \ + (COUNTER == SYSTICK_COUNTER_CLEAR)) + +#define IS_SYSTICK_RELOAD(RELOAD) ((RELOAD > 0) && (RELOAD <= 0xFFFFFF)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Exported_Functions MISC exported functions + * @{ + */ +void NVIC_SetVectorTable(u32 NVIC_VectTable, u32 NVIC_Offset); +void NVIC_LowPowerConfig(u8 NVIC_LowPowerMode, ControlStatus NewState); +void NVIC_SetPendingSystemHandler(u32 SystemHandler); +void SYSTICK_ClockSourceConfig(u32 SysTick_ClockSource); +void SYSTICK_CounterCmd(u32 SysTick_Counter); +void SYSTICK_IntConfig(ControlStatus NewState); +void SYSTICK_SetReloadValue(u32 SysTick_Reload); +u32 RBIT(u32 in); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_config.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_config.h new file mode 100644 index 00000000000..bd4e5612472 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_config.h @@ -0,0 +1,307 @@ +/*********************************************************************************************************//** + * @file ht32_config.h + * @version $Rev:: 7125 $ + * @date $Date:: 2023-08-16 #$ + * @brief Configuration file of HT32. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_CONFIG_H +#define __HT32_CONFIG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Settings ------------------------------------------------------------------------------------------------*/ +#ifdef USE_HT32F59999_SK + #define USE_HT32F52352_SK +#endif +#ifdef USE_HT32F59999 + #define USE_HT32F52342_52 +#endif +#ifdef USE_MEM_HT32F59999 + #define USE_MEM_HT32F52352 +#endif + +#ifdef USE_HT32F52142_SK + #define USE_HT32F0008_SK +#endif +#ifdef USE_HT32F52142 + #define USE_HT32F0008 +#endif +#ifdef USE_MEM_HT32F52142 + #define USE_MEM_HT32F0008 +#endif + +#ifdef USE_HT32F61352_DVB + #define USE_HT32F0006_DVB +#endif +#ifdef USE_HT32F61352 + #define USE_HT32F0006 +#endif +#ifdef USE_MEM_HT32F61352 + #define USE_MEM_HT32F0006 +#endif +#ifdef USE_HT32F61355_56_57 + #define USE_HT32F0006 +#endif +#ifdef USE_MEM_HT32F61355 + #define USE_MEM_HT32F0006 +#endif +#ifdef USE_MEM_HT32F61356 + #define USE_MEM_HT32F0006 +#endif +#ifdef USE_MEM_HT32F61357 + #define USE_MEM_HT32F0006 +#endif + +#ifdef USE_HT50F32002_SK + #define USE_HT32F50230_SK +#endif +#ifdef USE_HT50F32002 + #define USE_HT32F50220_30 +#endif +#ifdef USE_MEM_HT50F32002 + #define USE_MEM_HT32F50230 +#endif + +#ifdef USE_HT50F32003_SK + #define USE_HT32F52352_SK +#endif +#ifdef USE_HT50F32003 + #define USE_HT32F52342_52 +#endif +#ifdef USE_MEM_HT50F32003 + #define USE_MEM_HT32F52352 +#endif + +#ifdef USE_HT32F59041_SK + #define USE_HT32F50241_SK +#endif +#ifdef USE_HT32F59041 + #define USE_HT32F50231_41 +#endif +#ifdef USE_MEM_HT32F59041 + #define USE_MEM_HT32F50241 +#endif + +#ifdef USE_HT32F59741_SK + #define USE_HT32F57341_SK +#endif +#ifdef USE_HT32F59741 + #define USE_HT32F57331_41 +#endif +#ifdef USE_MEM_HT32F59741 + #define USE_MEM_HT32F57341 +#endif + +#ifdef USE_HT32F67741_SK + #define USE_HT32F52241_SK +#endif +#ifdef USE_HT32F67741 + #define USE_HT32F52231_41 +#endif +#ifdef USE_MEM_HT32F67741 + #define USE_MEM_HT32F52241 +#endif + +#ifdef USE_HF5032_SK + #define USE_HT32F50230_SK +#endif +#ifdef USE_HF5032 + #define USE_HT32F50220_30 +#endif +#ifdef USE_MEM_HF5032 + #define USE_MEM_HT32F50230 +#endif + +#ifdef USE_HT32F65240 + #undef USE_HT32F65230_40 + #define USE_HT32F65230_40 +#elif defined USE_HT32F65230_40 + #undef USE_HT32F65240 + #define USE_HT32F65240 +#endif + +#ifdef USE_HT32F5828_SK + #define USE_HT32F57352_SK +#endif +#ifdef USE_HT32F5828 + #define USE_HT32F57342_52 +#endif +#ifdef USE_MEM_HT32F5828 + #define USE_MEM_HT32F57352 +#endif + +#ifdef USE_MXTX6306_SK + #define USE_HT32F65240_SK +#endif +#ifdef USE_MXTX6306 + #define USE_HT32F65230_40 +#endif +#ifdef USE_MEM_MXTX6306 + #define USE_MEM_HT32F65230 +#endif + +#ifdef USE_HT32F67232_SK + #define USE_HT32F52230_SK +#endif +#ifdef USE_HT32F67232 + #define USE_HT32F52220_30 +#endif +#ifdef USE_MEM_HT32F67232 + #define USE_MEM_HT32F52230 +#endif + +#ifdef USE_HT32F67233 + #define USE_HT32F52220_30 +#endif +#ifdef USE_MEM_HT32F67233 + #define USE_MEM_HT32F52230 +#endif + +#ifdef USE_HT50F3200S_SK + #define USE_HT32F65240_SK +#endif +#ifdef USE_HT50F3200S + #define USE_HT32F65230_40 +#endif +#ifdef USE_MEM_HT50F3200S + #define USE_MEM_HT32F65240 +#endif + +#ifdef USE_HT50F3200T_SK + #define USE_HT32F52367_SK +#endif +#ifdef USE_HT50F3200T + #define USE_HT32F52357_67 +#endif +#ifdef USE_MEM_HT50F3200T + #define USE_MEM_HT32F52367 +#endif + +#ifdef USE_HT32F62030_SK + #define USE_HT32F52230_SK +#endif +#ifdef USE_HT32F62030 + #define USE_HT32F52220_30 +#endif +#ifdef USE_MEM_HT32F62030 + #define USE_MEM_HT32F52230 +#endif + +#ifdef USE_HT32F62040_SK + #define USE_HT32F52241_SK +#endif +#ifdef USE_HT32F62040 + #define USE_HT32F52231_41 +#endif +#ifdef USE_MEM_HT32F62040 + #define USE_MEM_HT32F52241 +#endif + +#ifdef USE_HT32F62050_SK + #define USE_HT32F52253_SK +#endif +#ifdef USE_HT32F62050 + #define USE_HT32F52243_53 +#endif +#ifdef USE_MEM_HT32F62050 + #define USE_MEM_HT32F52253 +#endif + +#ifdef USE_HT32F61630_SK + #define USE_HT32F50030_SK +#endif +#ifdef USE_HT32F61630 + #define USE_HT32F50020_30 +#endif +#ifdef USE_MEM_HT32F61630 + #define USE_MEM_HT32F50030 +#endif + +#ifdef USE_HT32F61641_SK + #define USE_HT32F50241_SK +#endif +#ifdef USE_HT32F61641 + #define USE_HT32F50231_41 +#endif +#ifdef USE_MEM_HT32F61641 + #define USE_MEM_HT32F50241 +#endif + +#ifdef USE_HT32F67742_SK + #define USE_HT32F57341_SK +#endif +#ifdef USE_HT32F67742 + #define USE_HT32F57331_41 +#endif +#ifdef USE_MEM_HT32F67742 + #define USE_MEM_HT32F57341 +#endif + +#ifdef USE_HT32F59046_SK + #define USE_HT32F50241_SK +#endif +#ifdef USE_HT32F59046 + #define USE_HT32F50231_41 +#endif +#ifdef USE_MEM_HT32F59046 + #define USE_MEM_HT32F50241 +#endif + +#ifdef USE_HT32F59746_SK + #define USE_HT32F57341_SK +#endif +#ifdef USE_HT32F59746 + #define USE_HT32F57331_41 +#endif +#ifdef USE_MEM_HT32F59746 + #define USE_MEM_HT32F57341 +#endif + +#ifdef USE_HT32F61030_SK + #define USE_HT32F50030_SK +#endif +#ifdef USE_HT32F61030 + #define USE_HT32F50020_30 +#endif +#ifdef USE_MEM_HT32F61030 + #define USE_MEM_HT32F50030 +#endif + +#ifdef USE_HT32F61041_SK + #define USE_HT32F50241_SK +#endif +#ifdef USE_HT32F61041 + #define USE_HT32F50231_41 +#endif +#ifdef USE_MEM_HT32F61041 + #define USE_MEM_HT32F50241 +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_dependency.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_dependency.h new file mode 100644 index 00000000000..d96ecb9c3c4 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_dependency.h @@ -0,0 +1,86 @@ +/*********************************************************************************************************//** + * @file ht32_dependency.h + * @version $Rev:: 5863 $ + * @date $Date:: 2022-05-12 #$ + * @brief The header file of dependency check. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +#ifdef __cplusplus + extern "C" { +#endif + + +#if 0 // Version setting example for module + +/* Dependency check ----------------------------------------------------------------------------------------*/ +#define MIN_HT32_FWLIB_VER (0x01000005) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x2200) +#include "ht32_dependency.h" // Not exist means the version of HT32 Firmware Library is older than the module required. + +#endif + +#if 0 // Version setting example for module + +/* Dependency check ----------------------------------------------------------------------------------------*/ +#if (__CORTEX_M == 0) +#define MIN_HT32_FWLIB_VER (0x01000024) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x5762) +#endif +#if (__CORTEX_M == 3) +#define MIN_HT32_FWLIB_VER (0x01000009) //0xmmnnnrrr -> Vm.n.r +#define MIN_HT32_FWLIB_SVN (0x2556) +#endif +#include "ht32_dependency.h" // Not exist means the version of HT32 Firmware Library is older than the module required. + +#endif + + +#if 0 // Enable for test +#undef HT32_FWLIB_VER +#undef HT32_FWLIB_SVN +#define HT32_FWLIB_VER (0x00000004) +#define HT32_FWLIB_SVN (0x1074) +#endif + + +// Check "ht32fxxxxx_lib.h" for the version of HT32 Firmwar Library +#if (HT32_FWLIB_VER != 999999) +#if HT32_FWLIB_VER < MIN_HT32_FWLIB_VER + #error !!! The version of HT32 Firmware Library is older than the module required. Please update HT32 Firmware Library. +#endif + +#if HT32_FWLIB_SVN < MIN_HT32_FWLIB_SVN + #error !!! The version of HT32 Firmware Library is older than the module required. Please update HT32 Firmware Library. +#endif +#endif + + +// Un-defined for next module of the .C include .C case +#undef MIN_HT32_FWLIB_VER +#undef MIN_HT32_FWLIB_SVN + + +#ifdef __cplusplus +} +#endif + +//#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_div.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_div.h new file mode 100644 index 00000000000..7fa7c168c11 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_div.h @@ -0,0 +1,37 @@ +/*********************************************************************************************************//** + * @file ht32_div.h + * @version $Rev:: 220 $ + * @date $Date:: 2016-02-16 #$ + * @brief The header file of division assembly. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_DIV_H +#define __HT32_DIV_H + +/* Exported functions --------------------------------------------------------------------------------------*/ +void DIV32_Init(void); +extern u32 (*UDIV32)(u32, u32); +extern s32 (*SDIV32)(s32, s32); + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_rand.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_rand.h new file mode 100644 index 00000000000..46827ba4147 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_rand.h @@ -0,0 +1,43 @@ +/*********************************************************************************************************//** + * @file ht32_rand.h + * @version $Rev:: 957 $ + * @date $Date:: 2016-08-15 #$ + * @brief The header file of random number. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_RAND_H +#define __HT32_RAND_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported functions --------------------------------------------------------------------------------------*/ +void Rand_Init(u32 *uSeed, u32 uCount, u32 a, u32 b); +extern u32 (*Rand_Get)(u32 *, u32); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_retarget_desc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_retarget_desc.h new file mode 100644 index 00000000000..9605a275976 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_retarget_desc.h @@ -0,0 +1,182 @@ +/*********************************************************************************************************//** + * @file ht32_retarget_desc.h + * @version $Rev:: 891 $ + * @date $Date:: 2016-07-14 #$ + * @brief The USB VCP descriptor file of retarget. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_RETARGET_DESC_H +#define __HT32_RETARGET_DESC_H + +/* Exported constants --------------------------------------------------------------------------------------*/ + + /*--------------------------------------------------------------------------------------------------------*/ + /* IAD to associate the two CDC interfaces */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + 8, // bLength 1 Size of this descriptor in bytes + 11, // bDescriptorType 1 Descriptor Type + 11, // bFirstInterface 1 + 2, // bInterfaceCount 1 + 2, // bFunctionClass 1 + 2, // bFunctionSubClass 1 + 0, // bFunctionProtocol 1 + 0x00, // iFunction 1 Index of string descriptor describing this function. + + /*--------------------------------------------------------------------------------------------------------*/ + /* Interface descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_INF, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_04_INF, // bDescriptorType 1 INTERFACE Descriptor Type + 11, // bInterfaceNumber 1 Number of this interface (Zero-based 0) + 0x00, // bAlternateSetting 1 Value used to select alternate setting + 1, // bNumEndpoints 1 Number of endpoints used by this interface + DESC_CLASS_02_CDC_CTRL, // bInterfaceClass 1 Class code (assigned by USB-IF) + 2, // bInterfaceSubClass 1 Subclass code (assigned by USB-IF) + 0, // bInterfaceProtocol 1 Protocol code (assigned by USB) + 0x00, // iInterface 1 Index of string descriptor describing this interface + + /*--------------------------------------------------------------------------------------------------------*/ + /* Header Functional descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 5, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 0, // bDescriptorSubtype 1 header functional descriptor + DESC_H2B(0x0110), // bcdCDC 2 spec release number + + /*--------------------------------------------------------------------------------------------------------*/ + /* Abstract control management Functional */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 4, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 2, // bDescriptorSubtype 1 Abstract Control Management Functional descriptor + 0x02, // bmCapabilities 1 + + /*--------------------------------------------------------------------------------------------------------*/ + /* Union Functional */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 5, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 5, // bDescriptorSubtype 1 Union Functional descriptor + 0x00, // bMasterInterface 1 Communication class interface + 0x01, // bSlaveInterface0 1 Data Class Interface + + /*--------------------------------------------------------------------------------------------------------*/ + /* Call Management Functional */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + 5, // bFunctionLength 1 Size of this descriptor in bytes + 0x24, // bDescriptorType 1 CS_INTERFACE descriptor type + 1, // bDescriptorSubtype 1 Call Management Functional descriptor + 0x00, // bmCapabilities 1 + 0x01, // bDataInterface 1 Interface number of Data + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLengthE 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + (0x80 | RETARGET_CTRL_EPT), // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x03, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(RETARGET_CTRL_LEN),// wMaxPacketSize 2 Maximum packet size + 0x00, // bInterval 1 Interval for polling endpoint + + /*--------------------------------------------------------------------------------------------------------*/ + /* Data class interface descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_INF, // bLength 1 Endpoint Descriptor size + DESC_TYPE_04_INF, // bDescriptorType 1 + 12, // bInterfaceNumber 1 Number of Interface + 0x00, // bAlternateSetting 1 Alternate setting + 2, // bNumEndpoints 1 Two endpoints used + DESC_CLASS_0A_CDC_DATA, // bInterfaceClass 1 + 0, // bInterfaceSubClass 1 + 0, // bInterfaceProtocol 1 + 0x00, // iInterface 1 + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint n Out descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + (0x00 | RETARGET_RX_EPT), // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x02, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(RETARGET_RX_LEN), // wMaxPacketSize 2 Maximum packet size + 0x00, // bInterval 1 Interval for polling endpoint + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint n In Descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + (0x80 | RETARGET_TX_EPT), // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x02, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(RETARGET_TX_LEN), // wMaxPacketSize 2 Maximum packet size + 0x00, // bInterval 1 Interval for polling endpoint + +#endif /* __HT32_RETARGET_DESC_H ---------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_retarget_usbdconf.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_retarget_usbdconf.h new file mode 100644 index 00000000000..f06a3346040 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_retarget_usbdconf.h @@ -0,0 +1,321 @@ +/*********************************************************************************************************//** + * @file ht32_retarget_usbdconf.h + * @version $Rev:: 4447 $ + * @date $Date:: 2019-12-27 #$ + * @brief The USB Device configuration of retarget + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_RETARGET_USBDCONF_H +#define __HT32_RETARGET_USBDCONF_H + +/* Settings ------------------------------------------------------------------------------------------------*/ +#define RETARGET_INF (0) +#define RETARGET_DLEN (0) + +#if (_RETARGET == 1) + + #ifdef RETARGET_IS_USB + + #undef RETARGET_INF + #undef RETARGET_DLEN + #define RETARGET_INF (2) + #define RETARGET_DLEN (8 + DESC_LEN_INF * 2 + 5 + 4 + 5 + 5 + DESC_LEN_EPT * 3) + + #if (_EP1_ENABLE == 0 && _EP2_ENABLE == 0 && _EP3_ENABLE == 0 && _EP4_ENABLE == 0 && \ + _EP5_ENABLE == 0 && _EP6_ENABLE == 0 && _EP7_ENABLE == 0) + #define NON_USB_IN_APP + #undef _UIER + #undef _EP0LEN + #undef _EP0_IER + #define _EP0LEN (64) + #define _EP0_IER (0x212) + #define _UIER (0x011D) + #endif + + #define _UIER_ALL (_UIER | (EP0IE << RETARGET_RX_EPT) | (EP0IE << RETARGET_TX_EPT)) + + #if (RETARGET_RX_EPT == 1 || RETARGET_TX_EPT == 1 || RETARGET_CTRL_EPT == 1) + #if (_EP1_ENABLE == 1) + #define _RERATGET1_ERR + #else + #undef _EP1_ENABLE + #undef _EP1_CFG_EPADR + #undef _EP1_CFG_EPEN_TMP + #undef _EP1_TYPR + #undef _EP1_CFG_EPDIR + #undef _EP1LEN_TMP + #undef _EP1_IER + + #define _EP1_ENABLE (1) + #define _EP1_CFG_EPADR (1) + #define _EP1_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 1) + #define _EP1_TYPR (2) + #define _EP1_CFG_EPDIR (0) + #define _EP1LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP1_IER (0x02) + #define RETARGET_RX_LEN (_EP1LEN) + #elif (RETARGET_TX_EPT == 1) + #define _EP1_TYPR (2) + #define _EP1_CFG_EPDIR (1) + #define _EP1LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP1_IER (0x10) + #define RETARGET_TX_LEN (_EP1LEN) + #elif (RETARGET_CTRL_EPT == 1) + #define _EP1_TYPR (3) + #define _EP1_CFG_EPDIR (1) + #define _EP1LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP1_IER (0x10) + #define RETARGET_CTRL_LEN (_EP1LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 2 || RETARGET_TX_EPT == 2 || RETARGET_CTRL_EPT == 2) + #if (_EP2_ENABLE == 1) + #define _RERATGET2_ERR + #else + #undef _EP2_ENABLE + #undef _EP2_CFG_EPADR + #undef _EP2_CFG_EPEN_TMP + #undef _EP2_TYPR + #undef _EP2_CFG_EPDIR + #undef _EP2LEN_TMP + #undef _EP2_IER + + #define _EP2_ENABLE (1) + #define _EP2_CFG_EPADR (2) + #define _EP2_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 2) + #define _EP2_TYPR (2) + #define _EP2_CFG_EPDIR (0) + #define _EP2LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP2_IER (0x02) + #define RETARGET_RX_LEN (_EP2LEN) + #elif (RETARGET_TX_EPT == 2) + #define _EP2_TYPR (2) + #define _EP2_CFG_EPDIR (1) + #define _EP2LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP2_IER (0x10) + #define RETARGET_TX_LEN (_EP2LEN) + #elif (RETARGET_CTRL_EPT == 2) + #define _EP2_TYPR (3) + #define _EP2_CFG_EPDIR (1) + #define _EP2LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP2_IER (0x10) + #define RETARGET_CTRL_LEN (_EP2LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 3 || RETARGET_TX_EPT == 3 || RETARGET_CTRL_EPT == 3) + #if (_EP3_ENABLE == 1) + #define _RERATGET3_ERR + #else + #undef _EP3_ENABLE + #undef _EP3_CFG_EPADR + #undef _EP3_CFG_EPEN_TMP + #undef _EP3_TYPR + #undef _EP3_CFG_EPDIR + #undef _EP3LEN_TMP + #undef _EP3_IER + + #define _EP3_ENABLE (1) + #define _EP3_CFG_EPADR (3) + #define _EP3_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 3) + #define _EP3_TYPR (2) + #define _EP3_CFG_EPDIR (0) + #define _EP3LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP3_IER (0x02) + #define RETARGET_RX_LEN (_EP3LEN) + #elif (RETARGET_TX_EPT == 3) + #define _EP3_TYPR (2) + #define _EP3_CFG_EPDIR (1) + #define _EP3LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP3_IER (0x10) + #define RETARGET_TX_LEN (_EP3LEN) + #elif (RETARGET_CTRL_EPT == 3) + #define _EP3_TYPR (3) + #define _EP3_CFG_EPDIR (1) + #define _EP3LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP3_IER (0x10) + #define RETARGET_CTRL_LEN (_EP3LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 4 || RETARGET_TX_EPT == 4 || RETARGET_CTRL_EPT == 4) + #if (_EP4_ENABLE == 1) + #define _RERATGET4_ERR + #else + #undef _EP4_ENABLE + #undef _EP4_CFG_EPADR + #undef _EP4_CFG_EPEN_TMP + #undef _EP4_TYPR + #undef _EP4_CFG_EPDIR + #undef _EP4LEN_TMP + #undef _EP4_IER + + #define _EP4_ENABLE (1) + #define _EP4_CFG_EPADR (4) + #define _EP4_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 4) + #define _EP4_TYPR (2) + #define _EP4_CFG_EPDIR (0) + #define _EP4LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP4_IER (0x02) + #define RETARGET_RX_LEN (_EP4LEN) + #elif (RETARGET_TX_EPT == 4) + #define _EP4_TYPR (2) + #define _EP4_CFG_EPDIR (1) + #define _EP4LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP4_IER (0x10) + #define RETARGET_TX_LEN (_EP4LEN) + #elif (RETARGET_CTRL_EPT == 4) + #define _EP4_TYPR (3) + #define _EP4_CFG_EPDIR (1) + #define _EP4LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP4_IER (0x10) + #define RETARGET_CTRL_LEN (_EP4LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 5 || RETARGET_TX_EPT == 5 || RETARGET_CTRL_EPT == 5) + #if (_EP5_ENABLE == 1) + #define _RERATGET5_ERR + #else + #undef _EP5_ENABLE + #undef _EP5_CFG_EPADR + #undef _EP5_CFG_EPEN_TMP + #undef _EP5_TYPR + #undef _EP5_CFG_EPDIR + #undef _EP5LEN_TMP + #undef _EP5_IER + + #define _EP5_ENABLE (1) + #define _EP5_CFG_EPADR (5) + #define _EP5_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 5) + #define _EP5_TYPR (2) + #define _EP5_CFG_EPDIR (0) + #define _EP5LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP5_IER (0x02) + #define RETARGET_RX_LEN (_EP5LEN) + #elif (RETARGET_TX_EPT == 5) + #define _EP5_TYPR (2) + #define _EP5_CFG_EPDIR (1) + #define _EP5LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP5_IER (0x10) + #define RETARGET_TX_LEN (_EP5LEN) + #elif (RETARGET_CTRL_EPT == 5) + #define _EP5_TYPR (3) + #define _EP5_CFG_EPDIR (1) + #define _EP5LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP5_IER (0x10) + #define RETARGET_CTRL_LEN (_EP5LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 6 || RETARGET_TX_EPT == 6 || RETARGET_CTRL_EPT == 6) + #if (_EP6_ENABLE == 1) + #define _RERATGET6_ERR + #else + #undef _EP6_ENABLE + #undef _EP6_CFG_EPADR + #undef _EP6_CFG_EPEN_TMP + #undef _EP6_TYPR + #undef _EP6_CFG_EPDIR + #undef _EP6LEN_TMP + #undef _EP6_IER + + #define _EP6_ENABLE (1) + #define _EP6_CFG_EPADR (6) + #define _EP6_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 6) + #define _EP6_TYPR (2) + #define _EP6_CFG_EPDIR (0) + #define _EP6LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP6_IER (0x02) + #define RETARGET_RX_LEN (_EP6LEN) + #elif (RETARGET_TX_EPT == 6) + #define _EP6_TYPR (2) + #define _EP6_CFG_EPDIR (1) + #define _EP6LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP6_IER (0x10) + #define RETARGET_TX_LEN (_EP6LEN) + #elif (RETARGET_CTRL_EPT == 6) + #define _EP6_TYPR (3) + #define _EP6_CFG_EPDIR (1) + #define _EP6LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP6_IER (0x10) + #define RETARGET_CTRL_LEN (_EP6LEN) + #endif + #endif + #endif + + #if (RETARGET_RX_EPT == 7 || RETARGET_TX_EPT == 7 || RETARGET_CTRL_EPT == 7) + #if (_EP7_ENABLE == 1) + #define _RERATGET7_ERR + #else + #undef _EP7_ENABLE + #undef _EP7_CFG_EPADR + #undef _EP7_CFG_EPEN_TMP + #undef _EP7_TYPR + #undef _EP7_CFG_EPDIR + #undef _EP7LEN_TMP + #undef _EP7_IER + + #define _EP7_ENABLE (1) + #define _EP7_CFG_EPADR (7) + #define _EP7_CFG_EPEN_TMP (1) + #if (RETARGET_RX_EPT == 7) + #define _EP7_TYPR (2) + #define _EP7_CFG_EPDIR (0) + #define _EP7LEN_TMP (RETARGET_RX_EPTLEN) + #define _EP7_IER (0x02) + #define RETARGET_RX_LEN (_EP7LEN) + #elif (RETARGET_TX_EPT == 7) + #define _EP7_TYPR (2) + #define _EP7_CFG_EPDIR (1) + #define _EP7LEN_TMP (RETARGET_TX_EPTLEN) + #define _EP7_IER (0x10) + #define RETARGET_TX_LEN (_EP7LEN) + #elif (RETARGET_CTRL_EPT == 7) + #define _EP7_TYPR (3) + #define _EP7_CFG_EPDIR (1) + #define _EP7LEN_TMP (RETARGET_CTRL_EPTLEN) + #define _EP7_IER (0x10) + #define RETARGET_CTRL_LEN (_EP7LEN) + #endif + #endif + #endif + + #endif /* #ifdef RETARGET_IS_USB */ + +#endif /* #if (_RETARGET == 1) */ + +#endif /* __HT32_RETARGET_USBDCONF_H -----------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_serial.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_serial.h new file mode 100644 index 00000000000..bea9f04ae34 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_serial.h @@ -0,0 +1,84 @@ +/*********************************************************************************************************//** + * @file ht32_serial.h + * @version $Rev:: 6444 $ + * @date $Date:: 2022-11-11 #$ + * @brief The header file of the Serial library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_SERIAL_H +#define __HT32_SERIAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#ifdef RETARGET_IS_USB +#include "ht32_usbd_core.h" +#endif + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @addtogroup SERIAL + * @brief Serial related functions + * @{ + */ + + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Exported_Functions Serial exported functions + * @{ + */ +void RETARGET_UART_IRQHandler(void); +u32 SERIAL_GetChar(void); +u32 SERIAL_PutChar(u32 ch); +#ifdef RETARGET_IS_USB +void SERIAL_USBDClass_Request(USBDCore_Device_TypeDef *pDev); +void SERIAL_USBDClass_RXHandler(USBD_EPTn_Enum EPTn); +void SERIAL_USBDClass_TXHandler(USBD_EPTn_Enum EPTn); +void SERIAL_USBDInit(void); +void SERIAL_Flush(void); +#else +#define SERIAL_Flush(...) +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_time.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_time.h new file mode 100644 index 00000000000..51aeba2c3ee --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_time.h @@ -0,0 +1,170 @@ +/*********************************************************************************************************//** + * @file ht32_time.h + * @version $Rev:: 6751 $ + * @date $Date:: 2023-03-02 #$ + * @brief The header file of time function. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_TIME_H +#define __HT32_TIME_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#ifndef HTCFG_TIME_IPSEL +#include "ht32_time_conf.h" +#endif + +/* Settings ------------------------------------------------------------------------------------------------*/ +#ifdef HTCFG_TIME_IPSEL +#if (HTCFG_TIME_IPSEL == 0) +#define HTCFG_TIME_IPN BFTM0 +#endif +#if (HTCFG_TIME_IPSEL == 1) +#define HTCFG_TIME_IPN BFTM1 +#endif +#if (HTCFG_TIME_IPSEL == 2) +#define HTCFG_TIME_IPN SCTM0 +#endif +#if (HTCFG_TIME_IPSEL == 3) +#define HTCFG_TIME_IPN SCTM1 +#endif +#if (HTCFG_TIME_IPSEL == 4) +#define HTCFG_TIME_IPN SCTM2 +#endif +#if (HTCFG_TIME_IPSEL == 5) +#define HTCFG_TIME_IPN SCTM3 +#endif +#if (HTCFG_TIME_IPSEL == 6) +#define HTCFG_TIME_IPN PWM0 +#endif +#if (HTCFG_TIME_IPSEL == 7) +#define HTCFG_TIME_IPN PWM1 +#endif +#if (HTCFG_TIME_IPSEL == 8) +#define HTCFG_TIME_IPN PWM2 +#endif +#if (HTCFG_TIME_IPSEL == 9) +#define HTCFG_TIME_IPN GPTM0 +#endif +#if (HTCFG_TIME_IPSEL == 10) +#define HTCFG_TIME_IPN GPTM1 +#endif +#if (HTCFG_TIME_IPSEL == 11) +#define HTCFG_TIME_IPN MCTM0 +#endif +#endif + +/* Exported constants --------------------------------------------------------------------------------------*/ +#ifndef IS_IPN_BFTM +#undef IPN_MCTM0 +#undef IPN_MCTM1 +#undef IPN_GPTM0 +#undef IPN_GPTM1 + +#define IPN_NULL (0) +#define IPN_MCTM0 (0x4002C000) +#define IPN_MCTM1 (0x4002D000) +#define IPN_GPTM0 (0x4006E000) +#define IPN_GPTM1 (0x4006F000) +#define IPN_SCTM0 (0x40034000) +#define IPN_SCTM1 (0x40074000) +#define IPN_SCTM2 (0x40035000) +#define IPN_SCTM3 (0x40075000) +#define IPN_PWM0 (0x40031000) +#define IPN_PWM1 (0x40071000) +#define IPN_PWM2 (0x40031000) +#define IPN_BFTM0 (0x40076000) +#define IPN_BFTM1 (0x40077000) +#define IPN_CHECK(IP) STRCAT2(IPN_, IP) +#define IS_IPN_BFTM(IP) (IPN_CHECK(IP) == IPN_BFTM0) || (IPN_CHECK(IP) == IPN_BFTM1) +#define IS_IPN_MCTM(IP) (IPN_CHECK(IP) == IPN_MCTM0) || (IPN_CHECK(IP) == IPN_MCTM1) +#define IS_IPN_GPTM(IP) (IPN_CHECK(IP) == IPN_GPTM0) || (IPN_CHECK(IP) == IPN_GPTM1) +#define IS_IPN_SCTM(IP) (IPN_CHECK(IP) == IPN_SCTM0) || (IPN_CHECK(IP) == IPN_SCTM1) || (IPN_CHECK(IP) == IPN_SCTM2) || (IPN_CHECK(IP) == IPN_SCTM3) +#define IS_IPN_PWM(IP) (IPN_CHECK(IP) == IPN_PWM0) || (IPN_CHECK(IP) == IPN_PWM1) || (IPN_CHECK(IP) == IPN_PWM2) +#define IS_IPN_TM(IP) (IS_IPN_MCTM(IP) || IS_IPN_GPTM(IP) || IS_IPN_SCTM(IP) || IS_IPN_PWM(IP)) +#endif + +#define _HTCFG_TIME_PORT STRCAT2(HT_, HTCFG_TIME_IPN) + +#if (HTCFG_TIME_CLKSEL == 0) +#define _HTCFG_TIME_CORECLK (LIBCFG_MAX_SPEED) +#else +#define _HTCFG_TIME_CORECLK (HTCFG_TIME_CLK_MANUAL) +#endif + +#if (LIBCFG_CKCU_NO_APB_PRESCALER == 1) +#undef HTCFG_TIME_PCLK_DIV +#define HTCFG_TIME_PCLK_DIV (0) +#endif + +#define HTCFG_TIME_CLKSRC (_HTCFG_TIME_CORECLK >> HTCFG_TIME_PCLK_DIV) + +#if (IS_IPN_BFTM(HTCFG_TIME_IPN)) +#undef HTCFG_TIME_TICKHZ +#define HTCFG_TIME_TICKHZ HTCFG_TIME_CLKSRC +#endif + +/* Exported macro ------------------------------------------------------------------------------------------*/ +#define TIME_TICKDIFF(start, current) ((current >= start) ? (u32)(current - start) : (u32)(0xFFFFFFFF - start + 1 + current)) + +#if (HTCFG_TIME_TICKHZ < 1000000) +#define TIME_US2TICK(us) (us / (1000000UL / HTCFG_TIME_TICKHZ)) +#define TIME_TICK2US(t) (t * (1000000UL / HTCFG_TIME_TICKHZ)) +#else +#define TIME_US2TICK(us) (us * (HTCFG_TIME_TICKHZ / 1000000UL)) +#define TIME_TICK2US(t) (t / (HTCFG_TIME_TICKHZ / 1000000UL)) +#endif + +#if (HTCFG_TIME_TICKHZ < 1000) +#define TIME_MS2TICK(ms) (ms / (1000UL / HTCFG_TIME_TICKHZ)) +#define TIME_TICK2MS(t) (t * (1000UL / HTCFG_TIME_TICKHZ)) +#else +#define TIME_MS2TICK(ms) (ms * (HTCFG_TIME_TICKHZ / 1000UL)) +#define TIME_TICK2MS(t) (t / (HTCFG_TIME_TICKHZ / 1000UL)) +#endif + +#define TIME_S2TICK(s) (s * (u32)(HTCFG_TIME_TICKHZ)) +#define TIME_TICK2S(t) (t / (HTCFG_TIME_TICKHZ)) + + +#define GET_CNT() (_HTCFG_TIME_PORT->CNTR) + +/* Exported functions --------------------------------------------------------------------------------------*/ +void Time_Init(void); +void Time_Delay(u32 delay); +u32 Time_GetTick(void); + +#if (IS_IPN_BFTM(HTCFG_TIME_IPN)) +// BFTM +#define Time_GetTick GET_CNT +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_undef_IP.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_undef_IP.h new file mode 100644 index 00000000000..fb67ddcd1ff --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32_undef_IP.h @@ -0,0 +1,200 @@ +/*********************************************************************************************************//** + * @file ht32_undef_IP.h + * @version $Rev:: 7309 $ + * @date $Date:: 2023-10-18 #$ + * @brief Header file for undefined IP. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ + +#ifndef __HT32_UNDEF_IP_H +#define __HT32_UNDEF_IP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if _AES +#undef _AES +#endif + +#ifdef _ADC +#undef _ADC +#endif + +#ifdef _BFTM +#undef _BFTM +#endif + +#ifdef _CAN +#undef _CAN +#endif + +#ifdef _CKCU +#undef _CKCU +#endif + +#ifdef _CMP +#undef _CMP +#endif + +#ifdef _CRC +#undef _CRC +#endif + +#ifdef _CSIF +#undef _CSIF +#endif + +#ifdef _DAC +#undef _DAC +#endif + +#ifdef _DIV +#undef _DIV +#endif + +#ifdef _EBI +#undef _EBI +#endif + +#ifdef _EXTI +#undef _EXTI +#endif + +#ifdef _FLASH +#undef _FLASH +#endif + +#ifdef _GPIO +#undef _GPIO +#endif + +#ifdef _GPTM +#undef _GPTM +#endif + +#ifdef _I2C +#undef _I2C +#endif + +#ifdef _I2S +#undef _I2S +#endif + +#ifdef _LCD +#undef _LCD +#endif + +#ifdef _LEDC +#undef _LEDC +#endif + +#ifdef _MCTM +#undef _MCTM +#endif + +#ifdef _MIDI +#undef _MIDI +#endif + +#ifdef _OPA +#undef _OPA +#endif + +#ifdef _PDMA +#undef _PDMA +#endif + +#ifdef _PWRCU +#undef _PWRCU +#endif + +#ifdef _PWM +#undef _PWM +#endif + +#ifdef _RSTCU +#undef _RSTCU +#endif + +#ifdef _RTC +#undef _RTC +#endif + +#ifdef _SCI +#undef _SCI +#endif + +#ifdef _SCTM +#undef _SCTM +#endif + +#ifdef _SDIO +#undef _SDIO +#endif + +#ifdef _SLED +#undef _SLED +#endif + +#ifdef _SPI +#undef _SPI +#endif + +#ifdef _TKEY +#undef _TKEY +#endif + +#ifdef _USART +#undef _USART +#endif + +#ifdef _USB +#undef _USB +#endif + +#ifdef _WDT +#undef _WDT +#endif + +#ifdef _MISC +#undef _MISC +#endif + +#ifdef _SERIAL +#undef _SERIAL +#endif + +#ifdef _SWDIV +#undef _SWDIV +#endif + +#ifdef _SWRAND +#undef _SWRAND +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f0006_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f0006_libcfg.h new file mode 100644 index 00000000000..ca5464f9776 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f0006_libcfg.h @@ -0,0 +1,73 @@ +/*********************************************************************************************************//** + * @file ht32f0006_libcfg.h + * @version $Rev:: 6657 $ + * @date $Date:: 2023-01-16 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F0006_LIBCFG_H +#define __HT32F0006_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F0006) +#define USE_MEM_HT32F0006 +#endif + +#define LIBCFG_MAX_SPEED (48000000) + +#define LIBCFG_FLASH_PAGESIZE (512) + +#ifdef USE_MEM_HT32F0006 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x0006) +#endif + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DACDUAL16 (1) +#define LIBCFG_DIV (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_I2S (1) +#define LIBCFG_LSE (1) +#define LIBCFG_MIDI (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_QSPI (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_USBD (1) + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_ADC_CH12_15 (1) +#define LIBCFG_AFE0006 (1) +#define LIBCFG_FMC_BRANCHCACHE (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FLASH_2PAGE_PER_WPBIT (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f0008_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f0008_libcfg.h new file mode 100644 index 00000000000..a53d939bbf6 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f0008_libcfg.h @@ -0,0 +1,74 @@ +/*********************************************************************************************************//** + * @file ht32f0008_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F0008_LIBCFG_H +#define __HT32F0008_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F0008) +#define USE_MEM_HT32F0008 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F0008 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x0008) +#endif + +#define LIBCFG_PDMA (1) + +#define LIBCFG_BFTM1 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_USBD (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_AES (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOF (1) + +#define LIBCFG_NO_ADC (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) +#define LIBCFG_AFIO_PWM_MODE4 (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_GPIO_DISABLE_DEBUG_PORT (1) +#define LIBCFG_AES_SWAP (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50020_30_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50020_30_libcfg.h new file mode 100644 index 00000000000..44d05bdcc92 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50020_30_libcfg.h @@ -0,0 +1,111 @@ +/*********************************************************************************************************//** + * @file ht32f50020_30_libcfg.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __ht32f50020_30_LIBCFG_H +#define __ht32f50020_30_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F50020) && !defined(USE_MEM_HT32F50030) +#define USE_MEM_HT32F50030 +#endif + +#define LIBCFG_MAX_SPEED (16000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F50020 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 16) + #define LIBCFG_RAM_SIZE (1024 * 2) + #define LIBCFG_CHIPNAME (0x50020) +#endif + +#ifdef USE_MEM_HT32F50030 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 31) + #define LIBCFG_RAM_SIZE (1024 * 2) + #define LIBCFG_CHIPNAME (0x50030) +#endif + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOF (1) +#define LIBCFG_LEDC (1) +#define LIBCFG_LSE (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_NO_GPTM0 (1) +#define LIBCFG_NO_USART0 (1) + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_LEVEL_TYPE2 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_ADC_VREFBUF (1) +#define LIBCFG_ADC_NO_DISCON_MODE (1) +#define LIBCFG_ADC_NO_SEQ_4_7 (1) +#define LIBCFG_ADC_NO_WDT (1) +#define LIBCFG_ADC_SW_TRIGGER_ONLY (1) +#define LIBCFG_AFIO_LEDC_MODE3 (1) +#define LIBCFG_AFIO_MODE_0_7 (1) +#define LIBCFG_AFIO_SCTM_MODE4 (1) +#define LIBCFG_AFIO_SYSTEM_MODE1 (1) +#define LIBCFG_BFTM_16BIT_COUNTER (1) +#define LIBCFG_CKCU_NO_APB_PRESCALER (1) +#define LIBCFG_CKCU_NO_AUTO_TRIM (1) +#define LIBCFG_CKCU_NO_LPCR (1) +#define LIBCFG_EXTI_8BIT_DEBOUNCE_COUNTER (1) +#define LIBCFG_EXTI_8CH (1) +#define LIBCFG_EXTI_DEBCNTPRE (1) +#define LIBCFG_GPIO_PR_STRONG_UP (1) +#define LIBCFG_I2C_PRESCALER_2BIT (1) +#define LIBCFG_I2C_TOUT_COUNT_8BIT (1) +#define LIBCFG_I2C_TWO_DEV_ADDR (1) +#define LIBCFG_I2C_NO_10BIT_MODE (1) +#define LIBCFG_I2C_NO_ADDR_MASK (1) +#define LIBCFG_I2C_NO_ARBLOS (1) +#define LIBCFG_LEDC_NO_COM_8_11 (1) +#define LIBCFG_NO_PLL (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_SPI_CLK_PRE_V01 (1) +#define LIBCFG_SPI_DATA_LENGTH_V01 (1) +#define LIBCFG_SPI_FIFO_DEPTH_V01 (1) +#define LIBCFG_SPI_NO_DUAL (1) +#define LIBCFG_SPI_NO_MULTI_MASTER (1) +#define LIBCFG_SPI_TIMEOUT_LENGTH_V01 (1) +#define LIBCFG_TM_CKDIV_8 (1) +#define LIBCFG_TM_PRESCALER_8BIT (1) +#define LIBCFG_TM_SCTM_2CHANNEL (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50220_30_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50220_30_libcfg.h new file mode 100644 index 00000000000..3624e76b7b2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50220_30_libcfg.h @@ -0,0 +1,75 @@ +/*********************************************************************************************************//** + * @file ht32f50220_30_libcfg.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F50220_30_LIBCFG_H +#define __HT32F50220_30_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F50220) && !defined(USE_MEM_HT32F50230) +#define USE_MEM_HT32F50230 +#endif + +#define LIBCFG_MAX_SPEED (20000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F50220 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 16) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x50220) +#endif + +#ifdef USE_MEM_HT32F50230 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 31) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x50230) +#endif + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_LSE (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) +#define LIBCFG_DIV (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIO_SINK_CURRENT_ENHANCED (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_NO_PLL (1) +#define LIBCFG_NO_USART0 (1) +#define LIBCFG_FMC_CMD_READY_WAIT (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50231_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50231_41_libcfg.h new file mode 100644 index 00000000000..b7e24634f75 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50231_41_libcfg.h @@ -0,0 +1,79 @@ +/*********************************************************************************************************//** + * @file ht32f50231_41_libcfg.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F50231_41_LIBCFG_H +#define __HT32F50231_41_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F50231) && !defined(USE_MEM_HT32F50241) +#define USE_MEM_HT32F50241 +#endif + +#define LIBCFG_MAX_SPEED (20000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F50231 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x50231) +#endif + +#ifdef USE_MEM_HT32F50241 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x50241) +#endif + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_LSE (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) +#define LIBCFG_DIV (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIO_SINK_CURRENT_ENHANCED (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CRC (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_NO_PLL (1) +#define LIBCFG_FMC_CMD_READY_WAIT (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50343_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50343_libcfg.h new file mode 100644 index 00000000000..2e13c2bea0a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50343_libcfg.h @@ -0,0 +1,87 @@ +/*********************************************************************************************************//** + * @file ht32f50343_libcfg.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F50343_LIBCFG_H +#define __HT32F50343_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F50343) +#define USE_MEM_HT32F50343 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F50343 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 12) + #define LIBCFG_CHIPNAME (0x50343) +#endif + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_LSE (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_NO_USART0 (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_VREG (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) +#define LIBCFG_PWM2 (1) +#define LIBCFG_PWM_8_CHANNEL (1) +#define LIBCFG_SLED0 (1) +#define LIBCFG_SLED1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_USBD (1) + + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50431_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50431_41_libcfg.h new file mode 100644 index 00000000000..9c3bb3bb397 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50431_41_libcfg.h @@ -0,0 +1,95 @@ +/*********************************************************************************************************//** + * @file ht32f50431_41_libcfg.h + * @version $Rev:: 7265 $ + * @date $Date:: 2023-10-02 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F50431_41_LIBCFG_H +#define __HT32F50431_41_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F50431) && !defined(USE_MEM_HT32F50441) +#define USE_MEM_HT32F50441 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F50431 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x50431) +#endif + +#ifdef USE_MEM_HT32F50441 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x50441) +#endif + +#define LIBCFG_PDMA (1) +#define LIBCFG_ADC_CH8_11 (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PWM0 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_LEDC (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) + +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) + +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_LEDC_NO_COM_8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_LEVEL_TYPE2 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_USART_LIN (1) +#define LIBCFG_USART_SINGLE_WIRE (1) +#define LIBCFG_GPIO_SINK_CURREMT_ENHANCED (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50442_52_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50442_52_libcfg.h new file mode 100644 index 00000000000..6a3cff8ab63 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f50442_52_libcfg.h @@ -0,0 +1,99 @@ +/*********************************************************************************************************//** + * @file ht32f50442_52_libcfg.h + * @version $Rev:: 7265 $ + * @date $Date:: 2023-10-02 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F50442_52_LIBCFG_H +#define __HT32F50442_52_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F50442) && !defined(USE_MEM_HT32F50452) +#define USE_MEM_HT32F50452 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F50442 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x50442) +#endif + +#ifdef USE_MEM_HT32F50452 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x50452) +#endif + +#define LIBCFG_PDMA (1) +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_CMP (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_EBI (1) +#define LIBCFG_LEDC (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) + +#define LIBCFG_USART1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) + +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_LEDC_NO_COM_8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_LEVEL_TYPE2 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_USART_LIN (1) +#define LIBCFG_USART_SINGLE_WIRE (1) +#define LIBCFG_GPIO_SINK_CURREMT_ENHANCED (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52220_30_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52220_30_libcfg.h new file mode 100644 index 00000000000..1804c38460e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52220_30_libcfg.h @@ -0,0 +1,61 @@ +/*********************************************************************************************************//** + * @file ht32f52220_30_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52220_30_LIBCFG_H +#define __HT32F52220_30_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52220) && !defined(USE_MEM_HT32F52230) +#define USE_MEM_HT32F52230 +#endif + +#define LIBCFG_MAX_SPEED (40000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F52220 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 16) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x52220) +#endif + +#ifdef USE_MEM_HT32F52230 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 31) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x52230) +#endif + +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) + +#define LIBCFG_GPIO_DISABLE_DEBUG_PORT (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52231_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52231_41_libcfg.h new file mode 100644 index 00000000000..071c8ab1dc0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52231_41_libcfg.h @@ -0,0 +1,76 @@ +/*********************************************************************************************************//** + * @file ht32f52231_41_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52231_41_LIBCFG_H +#define __HT32F52231_41_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52231) && !defined(USE_MEM_HT32F52241) +#define USE_MEM_HT32F52241 +#endif + +#define LIBCFG_MAX_SPEED (40000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F52231 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x52231) +#endif + +#ifdef USE_MEM_HT32F52241 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x52241) +#endif + +#define LIBCFG_ADC_CH8_11 (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_MCTM0 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_CRC (1) + +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIO_DISABLE_DEBUG_PORT (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52234_44_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52234_44_libcfg.h new file mode 100644 index 00000000000..1ac83f1323d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52234_44_libcfg.h @@ -0,0 +1,83 @@ +/*********************************************************************************************************//** + * @file ht32f52234_44_libcfg.h + * @version $Rev:: 7265 $ + * @date $Date:: 2023-10-02 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52234_44_LIBCFG_H +#define __HT32F52234_44_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52234) && !defined(USE_MEM_HT32F52244) +#define USE_MEM_HT32F52244 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F52234 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x52234) +#endif + +#ifdef USE_MEM_HT32F52244 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x52244) +#endif + +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_DEFAULT_08V (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_LSE (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_I2C2 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_NO_GPTM0 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_HSIRDYCR (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_DAC0 (1) +#define LIBCFG_DAC1 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_USART_LIN (1) +#define LIBCFG_USART_SINGLE_WIRE (1) +#define LIBCFG_AFIO_DAC_MODE3 (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52243_53_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52243_53_libcfg.h new file mode 100644 index 00000000000..38f4675048f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52243_53_libcfg.h @@ -0,0 +1,84 @@ +/*********************************************************************************************************//** + * @file ht32f52243_53_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52243_53_LIBCFG_H +#define __HT32F52243_53_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52243) && !defined(USE_MEM_HT32F52253) +#define USE_MEM_HT32F52253 +#endif + +#define LIBCFG_MAX_SPEED (40000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F52243 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x52243) +#endif + +#ifdef USE_MEM_HT32F52253 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x52253) +#endif + +#define LIBCFG_PDMA (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_ADC_CH8_11 (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_MCTM0 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) + +#define LIBCFG_USART1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_UART2 (1) +#define LIBCFG_UART3 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_I2C2 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_GPIO_DISABLE_DEBUG_PORT (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52331_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52331_41_libcfg.h new file mode 100644 index 00000000000..63db24b8f42 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52331_41_libcfg.h @@ -0,0 +1,78 @@ +/*********************************************************************************************************//** + * @file ht32f52331_41_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52331_41_LIBCFG_H +#define __HT32F52331_41_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52331) && !defined(USE_MEM_HT32F52341) +#define USE_MEM_HT32F52341 +#endif + +#define LIBCFG_MAX_SPEED (48000000) + +#define LIBCFG_FLASH_PAGESIZE (512) + +#ifdef USE_MEM_HT32F52331 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x52331) +#endif + +#ifdef USE_MEM_HT32F52341 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x52341) +#endif + +#define LIBCFG_ADC_CH8_11 (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_MCTM0 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_USBD (1) +#define LIBCFG_CRC (1) + +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIO_DISABLE_DEBUG_PORT (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52342_52_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52342_52_libcfg.h new file mode 100644 index 00000000000..54a148b5893 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52342_52_libcfg.h @@ -0,0 +1,91 @@ +/*********************************************************************************************************//** + * @file ht32f52342_52_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52342_52_LIBCFG_H +#define __HT32F52342_52_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52342) && !defined(USE_MEM_HT32F52352) +#define USE_MEM_HT32F52352 +#endif + +#define LIBCFG_MAX_SPEED (48000000) + +#define LIBCFG_FLASH_PAGESIZE (512) + +#ifdef USE_MEM_HT32F52342 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 128) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x52342) +#endif + +#ifdef USE_MEM_HT32F52352 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x52352) +#endif + +#define LIBCFG_PDMA (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_CMP (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_GPTM1 (1) +#define LIBCFG_MCTM0 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SCI1 (1) +#define LIBCFG_USBD (1) +#define LIBCFG_EBI (1) +#define LIBCFG_I2S (1) +#define LIBCFG_CRC (1) + +#define LIBCFG_USART1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) + +#define LIBCFG_BAKREG (1) + +#define LIBCFG_FMC_BRANCHCACHE (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FLASH_2PAGE_PER_WPBIT (1) +#define LIBCFG_GPIO_DISABLE_DEBUG_PORT (1) +#define LIBCFG_RTC_LSI_LOAD_TRIM (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52344_54_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52344_54_libcfg.h new file mode 100644 index 00000000000..452a832483a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52344_54_libcfg.h @@ -0,0 +1,84 @@ +/*********************************************************************************************************//** + * @file ht32f52344_54_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52344_54_LIBCFG_H +#define __HT32F52344_54_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52344) && !defined(USE_MEM_HT32F52354) +#define USE_MEM_HT32F52354 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F52344 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x52344) +#endif + +#ifdef USE_MEM_HT32F52354 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x52354) +#endif + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_CKCU_USB_PLL_96M (1) +#define LIBCFG_CKCU_MCTM_SRC (1) +#define LIBCFG_CMP (1) +#define LIBCFG_CMP_IVREF_CN_IN (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_EBI (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_LSE (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_NO_USART0 (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_USBD (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52357_67_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52357_67_libcfg.h new file mode 100644 index 00000000000..1804f46079f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f52357_67_libcfg.h @@ -0,0 +1,102 @@ +/*********************************************************************************************************//** + * @file ht32f52357_67_libcfg.h + * @version $Rev:: 7167 $ + * @date $Date:: 2023-08-25 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F52357_67_LIBCFG_H +#define __HT32F52357_67_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F52357) && !defined(USE_MEM_HT32F52367) +#define USE_MEM_HT32F52367 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F52357 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 128) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x52357) +#endif + +#ifdef USE_MEM_HT32F52367 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 32) + #define LIBCFG_CHIPNAME (0x52367) +#endif + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_AES (1) +#define LIBCFG_AES_KEYSIZE_256B (1) +#define LIBCFG_BAKREG (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_CMP (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DAC0 (1) +#define LIBCFG_DIV (1) +#define LIBCFG_EBI (1) +#define LIBCFG_FLASH_2PAGE_PER_WPBIT (1) +#define LIBCFG_FMC_BRANCHCACHE (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_GPIOE (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_I2S (1) +#define LIBCFG_LSE (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) +#define LIBCFG_QSPI (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SCI1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_UART2 (1) +#define LIBCFG_UART3 (1) +#define LIBCFG_USART1 (1) +#define LIBCFG_USBD (1) + +#define UART0_IRQHandler UART0_UART2_IRQHandler +#define UART2_IRQHandler UART0_UART2_IRQHandler +#define UART1_IRQHandler UART1_UART3_IRQHandler +#define UART3_IRQHandler UART1_UART3_IRQHandler + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53231_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53231_41_libcfg.h new file mode 100644 index 00000000000..43068a9c12f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53231_41_libcfg.h @@ -0,0 +1,96 @@ +/*********************************************************************************************************//** + * @file ht32f53231_41_libcfg.h + * @version $Rev:: 7265 $ + * @date $Date:: 2023-10-02 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F53231_41_LIBCFG_H +#define __HT32F53231_41_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F53231) && !defined(USE_MEM_HT32F53241) +#define USE_MEM_HT32F53241 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F53231 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x53231) +#endif + +#ifdef USE_MEM_HT32F53241 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x53241) +#endif + +#define LIBCFG_PDMA (1) +#define LIBCFG_ADC_CH8_11 (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PWM0 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_LEDC (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_CAN0 (1) + +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) + +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_LEDC_NO_COM_8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_LEVEL_TYPE2 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_USART_LIN (1) +#define LIBCFG_USART_SINGLE_WIRE (1) +#define LIBCFG_GPIO_SINK_CURREMT_ENHANCED (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53242_52_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53242_52_libcfg.h new file mode 100644 index 00000000000..c2493ba610c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f53242_52_libcfg.h @@ -0,0 +1,100 @@ +/*********************************************************************************************************//** + * @file ht32f53242_52_libcfg.h + * @version $Rev:: 7265 $ + * @date $Date:: 2023-10-02 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F53242_52_LIBCFG_H +#define __HT32F53242_52_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F53242) && !defined(USE_MEM_HT32F53252) +#define USE_MEM_HT32F53252 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F53242 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x53242) +#endif + +#ifdef USE_MEM_HT32F53252 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x53252) +#endif + +#define LIBCFG_PDMA (1) +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_CMP (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_EBI (1) +#define LIBCFG_LEDC (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_CAN0 (1) + +#define LIBCFG_USART1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) + +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_LEDC_NO_COM_8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_LEVEL_TYPE2 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_USART_LIN (1) +#define LIBCFG_USART_SINGLE_WIRE (1) +#define LIBCFG_GPIO_SINK_CURREMT_ENHANCED (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54231_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54231_41_libcfg.h new file mode 100644 index 00000000000..671765ef1ba --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54231_41_libcfg.h @@ -0,0 +1,87 @@ +/*********************************************************************************************************//** + * @file ht32f54231_41_libcfg.h + * @version $Rev:: 7184 $ + * @date $Date:: 2023-08-31 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F54231_41_LIBCFG_H +#define __HT32F54231_41_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F54231) && !defined(USE_MEM_HT32F54241) +#define USE_MEM_HT32F52352 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F54231 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x54231) +#endif + +#ifdef USE_MEM_HT32F54241 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x54241) +#endif + +#define LIBCFG_ADC_CH8_9 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_LEVEL_TYPE2 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIO_SINK_CURRENT_ENHANCED (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_LEDC (1) +#define LIBCFG_LEDC_NO_COM_8_11 (1) +#define LIBCFG_LSE (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_TKEY (1) +#define LIBCFG_UART1 (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54243_53_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54243_53_libcfg.h new file mode 100644 index 00000000000..750e4fb3773 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f54243_53_libcfg.h @@ -0,0 +1,95 @@ +/*********************************************************************************************************//** + * @file ht32f54243_53_libcfg.h + * @version $Rev:: 6896 $ + * @date $Date:: 2023-05-08 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F54243_53_LIBCFG_H +#define __HT32F54243_53_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F54243) && !defined(USE_MEM_HT32F54253) +#define USE_MEM_HT32F52352 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F54243 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x54243) +#endif + +#ifdef USE_MEM_HT32F54253 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x54253) +#endif + +#define LIBCFG_ADC_CH8_9 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_IVREF_LEVEL_TYPE2 (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CRC (1) +#define LIBCFG_CMP (1) +#define LIBCFG_DIV (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_GPIO_SINK_CURRENT_ENHANCED (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_I2C2 (1) +#define LIBCFG_LEDC (1) +#define LIBCFG_LSE (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_TKEY (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_UART2 (1) +#define LIBCFG_UART3 (1) +#define LIBCFG_USART1 (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f57331_41_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f57331_41_libcfg.h new file mode 100644 index 00000000000..147fdcc041d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f57331_41_libcfg.h @@ -0,0 +1,79 @@ +/*********************************************************************************************************//** + * @file ht32f57331_41_libcfg.h + * @version $Rev:: 6189 $ + * @date $Date:: 2022-09-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F57331_41_LIBCFG_H +#define __HT32F57331_41_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F57331) && !defined(USE_MEM_HT32F57341) +#define USE_MEM_HT32F57341 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F57331 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x57331) +#endif + +#ifdef USE_MEM_HT32F57341 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x57341) +#endif + +#define LIBCFG_ADC_CH8_9 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_LCD_SRC (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_LCD (1) +#define LIBCFG_LSE (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_USBD (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f57342_52_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f57342_52_libcfg.h new file mode 100644 index 00000000000..c8740e5f8d9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f57342_52_libcfg.h @@ -0,0 +1,89 @@ +/*********************************************************************************************************//** + * @file ht32f57342_52_libcfg.h + * @version $Rev:: 7167 $ + * @date $Date:: 2023-08-25 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F57342_52_LIBCFG_H +#define __HT32F57342_52_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F57342) && !defined(USE_MEM_HT32F57352) +#define USE_MEM_HT32F57352 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F57342 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x57342) +#endif + +#ifdef USE_MEM_HT32F57352 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x57352) +#endif + +#define LIBCFG_ADC_CH8_9 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_AES (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_LCD_SRC (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CKCU_USB_PLL (1) +#define LIBCFG_CRC (1) +#define LIBCFG_CMP (1) +#define LIBCFG_DAC0 (1) +#define LIBCFG_DIV (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_GPIOE (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_I2S (1) +#define LIBCFG_LCD (1) +#define LIBCFG_LSE (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_PWM0 (1) +#define LIBCFG_PWM1 (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SCI1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_USBD (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5826_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5826_libcfg.h new file mode 100644 index 00000000000..f2378a22fdd --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5826_libcfg.h @@ -0,0 +1,85 @@ +/*********************************************************************************************************//** + * @file ht32f5826_libcfg.h + * @version $Rev:: 7184 $ + * @date $Date:: 2023-08-31 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5826_LIBCFG_H +#define __HT32F5826_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F5826) +#define USE_MEM_HT32F5826 +#endif + +#define LIBCFG_MAX_SPEED (48000000) + +#define LIBCFG_FLASH_PAGESIZE (512) + +#ifdef USE_MEM_HT32F5826 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 255) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x5826) +#endif + +#define LIBCFG_PDMA (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_CMP (1) + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_GPTM1 (1) +#define LIBCFG_MCTM0 (1) + +#define LIBCFG_LSE (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SCI1 (1) +#define LIBCFG_USBD (1) +#define LIBCFG_EBI (1) +#define LIBCFG_I2S (1) +#define LIBCFG_CRC (1) + +#define LIBCFG_USART1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_I2C1 (1) + +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) + +#define LIBCFG_BAKREG (1) + +#define LIBCFG_FMC_BRANCHCACHE (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FLASH_2PAGE_PER_WPBIT (1) +#define LIBCFG_GPIO_DISABLE_DEBUG_PORT (1) +#define LIBCFG_RTC_LSI_LOAD_TRIM (1) +#define LIBCFG_CKCU_AUTO_TRIM_LEGACY (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_adc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_adc.h new file mode 100644 index 00000000000..c50babaa1aa --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_adc.h @@ -0,0 +1,660 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_adc.h + * @version $Rev:: 7265 $ + * @date $Date:: 2023-10-02 #$ + * @brief The header file of the ADC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __ht32f5XXXX_ADC_H +#define __ht32f5XXXX_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Constants ADC exported constants + * @{ + */ +#define IS_ADC(x) (x == HT_ADC0) + +#define ONE_SHOT_MODE (0x00000000) +#define CONTINUOUS_MODE (0x00000002) +#if (LIBCFG_ADC_NO_DISCON_MODE) +#define IS_DISCONTINUOUS_MODE(x) (0) +#else +#define DISCONTINUOUS_MODE (0x00000003) +#define IS_DISCONTINUOUS_MODE(x) (x == DISCONTINUOUS_MODE) +#endif + +#define IS_ADC_CONVERSION_MODE(REGULAR_MODE) ((REGULAR_MODE == ONE_SHOT_MODE) || \ + (REGULAR_MODE == CONTINUOUS_MODE) || \ + (IS_DISCONTINUOUS_MODE(REGULAR_MODE))) + +#define ADC_CH_0 (0) +#define ADC_CH_1 (1) +#define ADC_CH_2 (2) +#define ADC_CH_3 (3) +#define ADC_CH_4 (4) +#define ADC_CH_5 (5) +#define ADC_CH_6 (6) +#define ADC_CH_7 (7) + +#define IS_ADC_CHANNEL1(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7)) + +#if (LIBCFG_ADC_CH8_9) +#define ADC_CH_8 (8) +#define ADC_CH_9 (9) +#define IS_ADC_CHANNEL2(CHANNEL) (((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9)) +#elif (LIBCFG_ADC_CH8_11) +#define ADC_CH_8 (8) +#define ADC_CH_9 (9) +#define ADC_CH_10 (10) +#define ADC_CH_11 (11) +#define IS_ADC_CHANNEL2(CHANNEL) (((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || \ + ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11)) +#else +#define IS_ADC_CHANNEL2(CHANNEL) (0) +#endif + +#if (LIBCFG_ADC_CH12_15) +#define ADC_CH_12 (12) +#define ADC_CH_13 (13) +#define ADC_CH_14 (14) +#define ADC_CH_15 (15) +#define IS_ADC_CHANNEL3(CHANNEL) (((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || \ + ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15)) +#else +#define IS_ADC_CHANNEL3(CHANNEL) (0) +#endif + +#if defined(USE_HT32F50020_30) +#define ADC_CH_BANDGAP (12) +#define ADC_CH_MVDDA (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_BANDGAP) || ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F50220_30) +#define ADC_CH_GND_VREF (12) +#define ADC_CH_VDD_VREF (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F50231_41) +#define ADC_CH_GND_VREF (12) +#define ADC_CH_VDD_VREF (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F52220_30) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F52231_41) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F52243_53) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F52331_41) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F52342_52) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F52344_54) +#define ADC_CH_IVREF (15) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_MVDDA (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_GND_VREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F52357_67) +#define ADC_CH_VDD_VREF (12) +#define ADC_CH_DAC0_CH1 (13) +#define ADC_CH_DAC0_CH0 (14) +#define ADC_CH_IVREF (15) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_MVDDA (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_VDD_VREF) || \ + ((CH) == ADC_CH_DAC0_CH1) || \ + ((CH) == ADC_CH_DAC0_CH0) || \ + ((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_GND_VREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F57331_41) +#define ADC_CH_VDD_VREF (12) +#define ADC_CH_IVREF (15) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_MVDDA (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_VDD_VREF) || \ + ((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_GND_VREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F57342_52) +#define ADC_CH_VDD_VREF (12) +#define ADC_CH_DAC0_CH1 (13) +#define ADC_CH_DAC0_CH0 (14) +#define ADC_CH_IVREF (15) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_MVDDA (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_VDD_VREF) || \ + ((CH) == ADC_CH_DAC0_CH1) || \ + ((CH) == ADC_CH_DAC0_CH0) || \ + ((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_GND_VREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F0006) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F61244_45) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F50343) +#define ADC_CH_MVDDA (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F5826) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_VDD_VREF (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) +#endif + +#if defined(USE_HT32F54231_41) +#define ADC_CH_GND_VREF (10) +#define ADC_CH_VDD_VREF (11) +#define ADC_CH_IVREF (12) +#define ADC_CH_MVDDA (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || \ + ((CH) == ADC_CH_VDD_VREF) || \ + ((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F54243_53) +#define ADC_CH_GND_VREF (10) +#define ADC_CH_VDD_VREF (11) +#define ADC_CH_IVREF (12) +#define ADC_CH_MVDDA (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || \ + ((CH) == ADC_CH_VDD_VREF) || \ + ((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F67041_51) +#define ADC_CH_IVREF (15) +#define ADC_CH_GND_VREF (16) +#define ADC_CH_MVDDA (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_GND_VREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F52234_44) +#define ADC_CH_DAC0_CH0 (12) +#define ADC_CH_DAC0_CH1 (13) +#define ADC_CH_DAC1_CH0 (14) +#define ADC_CH_DAC1_CH1 (15) +#define ADC_CH_IVREF (16) +#define ADC_CH_MVDDA (17) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_DAC0_CH0) || \ + ((CH) == ADC_CH_DAC0_CH1) || \ + ((CH) == ADC_CH_DAC1_CH0) || \ + ((CH) == ADC_CH_DAC1_CH1) || \ + ((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F53231_41) +#define ADC_CH_IVREF (12) +#define ADC_CH_MVDDA (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F53242_52) +#define ADC_CH_IVREF (12) +#define ADC_CH_MVDDA (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F50431_41) +#define ADC_CH_IVREF (12) +#define ADC_CH_MVDDA (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#if defined(USE_HT32F50442_52) +#define ADC_CH_IVREF (12) +#define ADC_CH_MVDDA (13) +#define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ + ((CH) == ADC_CH_MVDDA)) +#endif + +#define IS_ADC_CHANNEL(CHANNEL) (IS_ADC_CHANNEL1(CHANNEL) || \ + IS_ADC_CHANNEL2(CHANNEL) || \ + IS_ADC_CHANNEL3(CHANNEL) || \ + IS_ADC_CH_INTERNAL1(CHANNEL)) + +#define IS_ADC_INPUT_CHANNEL(CHANNEL) (IS_ADC_CHANNEL1(CHANNEL) || IS_ADC_CHANNEL2(CHANNEL) || IS_ADC_CHANNEL3(CHANNEL)) + + +#define ADC_TRIG_SOFTWARE (1UL << 0) + +#if (LIBCFG_ADC_SW_TRIGGER_ONLY) +#define IS_ADC_TRIG(REGTRIG) ((REGTRIG) == ADC_TRIG_SOFTWARE) +#else +/* ((ADCTCR[4] << 4) | (ADCTSR[20] << 20)) */ +#if (LIBCFG_CMP) +#define ADC_TRIG_CMP0 ((1UL << 4) | (0UL << 20)) +#define ADC_TRIG_CMP1 ((1UL << 4) | (1UL << 20)) +#endif + +/* ((ADCTCR[3] << 3) | (ADCTSR[23:22] << 22) | (ADCTSR[19] << 19)) */ +#define ADC_TRIG_BFTM0 ((1UL << 3) | (0UL << 22) | (0UL << 19)) +#if (LIBCFG_BFTM1) +#define ADC_TRIG_BFTM1 ((1UL << 3) | (0UL << 22) | (1UL << 19)) +#endif + +/* ((ADCTCR[3] << 3) | (ADCTSR[29:27]) << 27) | (ADCTSR[23:22] << 22) | (ADCTSR[19] << 19)) */ +#if (LIBCFG_PWM0) +#define ADC_TRIG_PWM0_MTO ((1UL << 3) | (0UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH0O ((1UL << 3) | (1UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH1O ((1UL << 3) | (2UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH2O ((1UL << 3) | (3UL << 27) | (1UL << 22) | (0UL << 19)) +#define ADC_TRIG_PWM0_CH3O ((1UL << 3) | (4UL << 27) | (1UL << 22) | (0UL << 19)) +#endif +#if (LIBCFG_PWM1) +#define ADC_TRIG_PWM1_MTO ((1UL << 3) | (0UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH0O ((1UL << 3) | (1UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH1O ((1UL << 3) | (2UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH2O ((1UL << 3) | (3UL << 27) | (1UL << 22) | (1UL << 19)) +#define ADC_TRIG_PWM1_CH3O ((1UL << 3) | (4UL << 27) | (1UL << 22) | (1UL << 19)) +#endif + +/* ((ADCTCR[2] << 2) | (ADCTSR[26:24] << 24) | (ADCTSR[18:16] << 16)) */ +#if (LIBCFG_MCTM0) +#define ADC_TRIG_MCTM0_MTO ((1UL << 2) | (0UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH0O ((1UL << 2) | (1UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH1O ((1UL << 2) | (2UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH2O ((1UL << 2) | (3UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH3O ((1UL << 2) | (4UL << 24) | (0UL << 16)) +#endif + +#if (LIBCFG_NO_GPTM0) +#define IS_ADC_TRIG_GPTM0(x) (0) +#else +#define ADC_TRIG_GPTM0_MTO ((1UL << 2) | (0UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH0O ((1UL << 2) | (1UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH1O ((1UL << 2) | (2UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH2O ((1UL << 2) | (3UL << 24) | (2UL << 16)) +#define ADC_TRIG_GPTM0_CH3O ((1UL << 2) | (4UL << 24) | (2UL << 16)) + +#define IS_ADC_TRIG_GPTM0(x) (((x) == ADC_TRIG_GPTM0_MTO) || \ + ((x) == ADC_TRIG_GPTM0_CH0O) || \ + ((x) == ADC_TRIG_GPTM0_CH1O) || \ + ((x) == ADC_TRIG_GPTM0_CH2O) || \ + ((x) == ADC_TRIG_GPTM0_CH3O)) +#endif + +#if (LIBCFG_GPTM1) +#define ADC_TRIG_GPTM1_MTO ((1UL << 2) | (0UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH0O ((1UL << 2) | (1UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH1O ((1UL << 2) | (2UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH2O ((1UL << 2) | (3UL << 24) | (3UL << 16)) +#define ADC_TRIG_GPTM1_CH3O ((1UL << 2) | (4UL << 24) | (3UL << 16)) +#endif + +/* (ADCTCR[1] << 1) | (ADCTSR[11:8] << 8) */ +#define ADC_TRIG_EXTI_0 ((1UL << 1) | ( 0UL << 8)) +#define ADC_TRIG_EXTI_1 ((1UL << 1) | ( 1UL << 8)) +#define ADC_TRIG_EXTI_2 ((1UL << 1) | ( 2UL << 8)) +#define ADC_TRIG_EXTI_3 ((1UL << 1) | ( 3UL << 8)) +#define ADC_TRIG_EXTI_4 ((1UL << 1) | ( 4UL << 8)) +#define ADC_TRIG_EXTI_5 ((1UL << 1) | ( 5UL << 8)) +#define ADC_TRIG_EXTI_6 ((1UL << 1) | ( 6UL << 8)) +#define ADC_TRIG_EXTI_7 ((1UL << 1) | ( 7UL << 8)) +#define ADC_TRIG_EXTI_8 ((1UL << 1) | ( 8UL << 8)) +#define ADC_TRIG_EXTI_9 ((1UL << 1) | ( 9UL << 8)) +#define ADC_TRIG_EXTI_10 ((1UL << 1) | (10UL << 8)) +#define ADC_TRIG_EXTI_11 ((1UL << 1) | (11UL << 8)) +#define ADC_TRIG_EXTI_12 ((1UL << 1) | (12UL << 8)) +#define ADC_TRIG_EXTI_13 ((1UL << 1) | (13UL << 8)) +#define ADC_TRIG_EXTI_14 ((1UL << 1) | (14UL << 8)) +#define ADC_TRIG_EXTI_15 ((1UL << 1) | (15UL << 8)) + +#define IS_ADC_TRIG(REGTRIG) (IS_ADC_TRIG1(REGTRIG) || \ + IS_ADC_TRIG2(REGTRIG) || \ + IS_ADC_TRIG3(REGTRIG) || \ + IS_ADC_TRIG4(REGTRIG) || \ + IS_ADC_TRIG5(REGTRIG) || \ + IS_ADC_TRIG6(REGTRIG) || \ + IS_ADC_TRIG7(REGTRIG)) + +#define IS_ADC_TRIG1(REGTRIG) (IS_ADC_TRIG_GPTM0(REGTRIG) || \ + ((REGTRIG) == ADC_TRIG_BFTM0) || \ + ((REGTRIG) == ADC_TRIG_EXTI_0) || \ + ((REGTRIG) == ADC_TRIG_EXTI_1) || \ + ((REGTRIG) == ADC_TRIG_EXTI_2) || \ + ((REGTRIG) == ADC_TRIG_EXTI_3) || \ + ((REGTRIG) == ADC_TRIG_EXTI_4) || \ + ((REGTRIG) == ADC_TRIG_EXTI_5) || \ + ((REGTRIG) == ADC_TRIG_EXTI_6) || \ + ((REGTRIG) == ADC_TRIG_EXTI_7) || \ + ((REGTRIG) == ADC_TRIG_EXTI_8) || \ + ((REGTRIG) == ADC_TRIG_EXTI_9) || \ + ((REGTRIG) == ADC_TRIG_EXTI_10) || \ + ((REGTRIG) == ADC_TRIG_EXTI_11) || \ + ((REGTRIG) == ADC_TRIG_EXTI_12) || \ + ((REGTRIG) == ADC_TRIG_EXTI_13) || \ + ((REGTRIG) == ADC_TRIG_EXTI_14) || \ + ((REGTRIG) == ADC_TRIG_EXTI_15) || \ + ((REGTRIG) == ADC_TRIG_SOFTWARE)) + +#if (LIBCFG_BFTM1) +#define IS_ADC_TRIG2(REGTRIG) ((REGTRIG) == ADC_TRIG_BFTM1) +#else +#define IS_ADC_TRIG2(REGTRIG) (0) +#endif + +#if (LIBCFG_MCTM0) +#define IS_ADC_TRIG3(REGTRIG) (((REGTRIG) == ADC_TRIG_MCTM0_MTO) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH0O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH1O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH2O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH3O) || \ + ((REGTRIG) == ADC_TRIG_BFTM1)) +#else +#define IS_ADC_TRIG3(REGTRIG) (0) +#endif + +#if (LIBCFG_GPTM1) +#define IS_ADC_TRIG4(REGTRIG) (((REGTRIG) == ADC_TRIG_GPTM1_MTO) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH0O) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH1O) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH2O) || \ + ((REGTRIG) == ADC_TRIG_GPTM1_CH3O)) +#else +#define IS_ADC_TRIG4(REGTRIG) (0) +#endif + +#if (LIBCFG_PWM0) +#define IS_ADC_TRIG5(REGTRIG) (((REGTRIG) == ADC_TRIG_PWM0_MTO) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH0O) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH1O) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH2O) || \ + ((REGTRIG) == ADC_TRIG_PWM0_CH3O)) +#else +#define IS_ADC_TRIG5(REGTRIG) (0) +#endif + +#if (LIBCFG_PWM1) +#define IS_ADC_TRIG6(REGTRIG) (((REGTRIG) == ADC_TRIG_PWM1_MTO) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH0O) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH1O) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH2O) || \ + ((REGTRIG) == ADC_TRIG_PWM1_CH3O)) +#else +#define IS_ADC_TRIG6(REGTRIG) (0) +#endif + +#if (LIBCFG_CMP) +#define IS_ADC_TRIG7(REGTRIG) (((REGTRIG) == ADC_TRIG_CMP0) || \ + ((REGTRIG) == ADC_TRIG_CMP1)) +#else +#define IS_ADC_TRIG7(REGTRIG) (0) +#endif +#endif + +#define ADC_INT_SINGLE_EOC (0x00000001) +#if (LIBCFG_ADC_NO_DISCON_MODE == 0) +#define ADC_INT_SUB_GROUP_EOC (0x00000002) +#endif +#define ADC_INT_CYCLE_EOC (0x00000004) +#if (LIBCFG_ADC_NO_WDT == 0) +#define ADC_INT_AWD_LOWER (0x00010000) +#define ADC_INT_AWD_UPPER (0x00020000) +#endif +#define ADC_INT_DATA_OVERWRITE (0x01000000) + +#define IS_ADC_INT(INT) ((((INT) & 0xFEFCFFF8) == 0) && ((INT) != 0)) + + +#define ADC_FLAG_SINGLE_EOC (0x00000001) +#if (LIBCFG_ADC_NO_DISCON_MODE == 0) +#define ADC_FLAG_SUB_GROUP_EOC (0x00000002) +#endif +#define ADC_FLAG_CYCLE_EOC (0x00000004) +#if (LIBCFG_ADC_NO_WDT == 0) +#define ADC_FLAG_AWD_LOWER (0x00010000) +#define ADC_FLAG_AWD_UPPER (0x00020000) +#endif +#define ADC_FLAG_DATA_OVERWRITE (0x01000000) + +#define IS_ADC_FLAG(FLAG) ((((FLAG) & 0xFEFCFFF8) == 0) && ((FLAG) != 0)) + + +#define ADC_REGULAR_DATA0 (0) +#define ADC_REGULAR_DATA1 (1) +#define ADC_REGULAR_DATA2 (2) +#define ADC_REGULAR_DATA3 (3) +#if (LIBCFG_ADC_NO_SEQ_4_7 == 0) +#define ADC_REGULAR_DATA4 (4) +#define ADC_REGULAR_DATA5 (5) +#define ADC_REGULAR_DATA6 (6) +#define ADC_REGULAR_DATA7 (7) +#endif + +#if (LIBCFG_ADC_NO_SEQ_4_7) +#define IS_ADC_REGULAR_DATA(DATA) ((DATA) < 4) +#else +#define IS_ADC_REGULAR_DATA(DATA) ((DATA) < 8) +#endif + +#define ADC_AWD_DISABLE (u8)0x00 +#define ADC_AWD_ALL_LOWER (u8)0x05 +#define ADC_AWD_ALL_UPPER (u8)0x06 +#define ADC_AWD_ALL_LOWER_UPPER (u8)0x07 +#define ADC_AWD_SINGLE_LOWER (u8)0x01 +#define ADC_AWD_SINGLE_UPPER (u8)0x02 +#define ADC_AWD_SINGLE_LOWER_UPPER (u8)0x03 + +#define IS_ADC_AWD(AWD) (((AWD) == ADC_AWD_DISABLE) || \ + ((AWD) == ADC_AWD_ALL_LOWER) || \ + ((AWD) == ADC_AWD_ALL_UPPER) || \ + ((AWD) == ADC_AWD_ALL_LOWER_UPPER) || \ + ((AWD) == ADC_AWD_SINGLE_LOWER) || \ + ((AWD) == ADC_AWD_SINGLE_UPPER) || \ + ((AWD) == ADC_AWD_SINGLE_LOWER_UPPER)) + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) < 4096) + +#if (LIBCFG_PDMA) +#define ADC_PDMA_REGULAR_SINGLE (0x00000001) +#define ADC_PDMA_REGULAR_SUBGROUP (0x00000002) +#define ADC_PDMA_REGULAR_CYCLE (0x00000004) + +#define IS_ADC_PDMA(PDMA) (((PDMA) == ADC_PDMA_REGULAR_SINGLE) || \ + ((PDMA) == ADC_PDMA_REGULAR_SUBGROUP) || \ + ((PDMA) == ADC_PDMA_REGULAR_CYCLE)) +#endif + +#define IS_ADC_INPUT_SAMPLING_TIME(TIME) ((TIME) <= 255) + +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) < 4096) + + +#if (LIBCFG_ADC_NO_SEQ_4_7) +#define IS_ADC_REGULAR_RANK(RANK) ((RANK) < 4) +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 4)) +#else +#define IS_ADC_REGULAR_RANK(RANK) ((RANK) < 8) +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 8)) +#endif +#define IS_ADC_REGULAR_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 8)) + +#if (LIBCFG_ADC_IVREF) +#if (LIBCFG_ADC_IVREF_LEVEL_TYPE2) +#define ADC_VREF_2V5 (0ul << 4) +#define ADC_VREF_3V0 (1ul << 4) +#define ADC_VREF_4V0 (2ul << 4) +#define ADC_VREF_4V5 (3ul << 4) + +#define IS_ADC_VREF_SEL(SEL) ((SEL == ADC_VREF_2V5) || \ + (SEL == ADC_VREF_3V0) || \ + (SEL == ADC_VREF_4V0) || \ + (SEL == ADC_VREF_4V5)) +#else + #if LIBCFG_ADC_IVREF_DEFAULT_08V + #define ADC_VREF_0V8 (0ul << 4) + #define ADC_VREF_DEFAULT ADC_VREF_0V8 + #else + #define ADC_VREF_1V215 (0ul << 4) + #define ADC_VREF_DEFAULT ADC_VREF_1V215 + #endif +#define ADC_VREF_2V0 (1ul << 4) +#define ADC_VREF_2V5 (2ul << 4) +#define ADC_VREF_2V7 (3ul << 4) + +#define IS_ADC_VREF_SEL(SEL) ((SEL == ADC_VREF_DEFAULT) || \ + (SEL == ADC_VREF_2V0) || \ + (SEL == ADC_VREF_2V5) || \ + (SEL == ADC_VREF_2V7)) +#endif +#endif + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Functions ADC exported functions + * @{ + */ +void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn); +void ADC_Reset(HT_ADC_TypeDef* HT_ADCn); +void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); + +void ADC_SamplingTimeConfig(HT_ADC_TypeDef* HT_ADCn, u8 SampleClock); +void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, ...); +void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength); +void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x); + +void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); + +u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn); + +void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState); +FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); +void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); +FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x); + +#if (LIBCFG_ADC_NO_WDT) +#else +void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x); +void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n); +void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER); +#endif + +#if (LIBCFG_PDMA) +void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState); +#endif + +#if (LIBCFG_ADC_IVREF) +void ADC_VREFCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +void ADC_VREFConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_VREF_x); +#endif + +#if (LIBCFG_ADC_VREFBUF) +void ADC_VREFOutputCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +#endif + +#if (LIBCFG_ADC_MVDDA) +void ADC_MVDDACmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_aes.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_aes.h new file mode 100644 index 00000000000..ec7db174436 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_aes.h @@ -0,0 +1,209 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_aes.h + * @version $Rev:: 7390 $ + * @date $Date:: 2023-12-12 #$ + * @brief The header file of the ADC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_AES_H +#define __HT32F5XXXX_AES_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup AES + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Types AES exported types + * @{ + */ + +/** + * @brief Definition of AES Init Structure + */ +typedef struct +{ + u16 AES_KeySize; + u16 AES_Dir; + u16 AES_Mode; + u16 AES_Swap; +} AES_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Constants AES exported constants + * @{ + */ + +#define IS_AES(AES) (AES == HT_AES) + +/* Definitions of AES key size */ +#define AES_KEYSIZE_128B ((u32)0x00000000) +#define IS_AES_KEY_SIZE1(SIZE) (SIZE == AES_KEYSIZE_128B) + +#if (LIBCFG_AES_KEYSIZE_256B) +#define AES_KEYSIZE_192B ((u32)0x00000020) +#define AES_KEYSIZE_256B ((u32)0x00000040) +#define IS_AES_KEY_SIZE2(SIZE) ((SIZE == AES_KEYSIZE_192B) || (SIZE == AES_KEYSIZE_256B)) +#else +#define IS_AES_KEY_SIZE2(SIZE) (0) +#endif + +#define IS_AES_KEY_SIZE(SIZE) (IS_AES_KEY_SIZE1(SIZE) || IS_AES_KEY_SIZE2(SIZE)) + +/* Definitions of AES direction */ +typedef enum +{ + AES_DIR_ENCRYPT =0, + AES_DIR_DECRYPT =2 +} AES_DIR_Enum; + +#define IS_AES_DIR(DIR) ((DIR == AES_DIR_ENCRYPT) || (DIR == AES_DIR_DECRYPT)) + +/* Definitions of AES mode */ +#define AES_MODE_ECB ((u32)0x00000000) +#define AES_MODE_CBC ((u32)0x00000004) +#define AES_MODE_CTR ((u32)0x00000008) + +#define IS_AES_MODE(MODE) ((MODE == AES_MODE_ECB) || (MODE == AES_MODE_CBC) || (MODE == AES_MODE_CTR)) + +/* Definitions of AES key start */ +#define AES_KEYSTART_DISABLE ((u32)0x00000000) +#define AES_KEYSTART_ENABLE ((u32)0x00000010) + +#define IS_AES_KEYSTART(KEYSTART) ((KEYSTART == AES_KEYSTART_DISABLE) || (KEYSTART == AES_KEYSTART_ENABLE)) + +/* Definitions of AES swap */ +#define AES_SWAP_DISABLE ((u32)0x00000000) +#define AES_SWAP_ENABLE ((u32)0x00000100) + +#define IS_AES_SWAP(SWAP) ((SWAP == AES_SWAP_DISABLE) || (SWAP == AES_SWAP_ENABLE)) + +/* Definitions of AES flush */ +#define AES_FLUSH_DISABLE ((u32)0x00000000) +#define AES_FLUSH_ENABLE ((u32)0x00000400) + +#define IS_AES_FLUSH(FLUSH) ((FLUSH == AES_FLUSH_DISABLE) || (FLUSH == AES_FLUSH_ENABLE)) + +/* Definitions of AES Enable */ +#define AES_DISABLE ((u32)0x00000000) +#define AES_ENABLE ((u32)0x00000001) + +#define IS_AES_CMD(CMD) ((CMD == AES_DISABLE) || (CMD == AES_ENABLE)) + +/* Definitions of AES status */ +#define AES_SR_IFEMPTY ((u32)0x00000001) +#define AES_SR_IFNFULL ((u32)0x00000002) +#define AES_SR_OFNEMPTY ((u32)0x00000004) +#define AES_SR_OFFULL ((u32)0x00000008) +#define AES_SR_BUSY ((u32)0x00000010) + +#define IS_AES_STATUS(STATUS) ((STATUS == AES_SR_IFEMPTY) || \ + (STATUS == AES_SR_IFNFULL) || \ + (STATUS == AES_SR_OFNEMPTY) || \ + (STATUS == AES_SR_OFFULL) || \ + (STATUS == AES_SR_BUSY)) + +/* Definitions of AES PDMA */ +#define AES_PDMA_IFDMAEN ((u32)0x00000001) +#define AES_PDMA_OFDMAEN ((u32)0x00000002) + +#define IS_AES_PDMA(AES_PDMA) ((AES_PDMA == AES_PDMA_IFDMAEN) || (AES_PDMA == AES_PDMA_OFDMAEN)) + +/* Definitions of AES Interrupt Status */ +#define AES_INTSR_IFINT ((u32)0x00000001) +#define AES_INTSR_OFINT ((u32)0x00000002) + +#define IS_AES_INTSR(AES_INSR) ((AES_INSR == AES_INTSR_IFINT) || (AES_INSR == AES_INTSR_OFINT)) + +/* Definitions of AES interrupt enable */ +#define AES_IER_IFINTEN ((u32)0x00000001) +#define AES_IER_OFINTEN ((u32)0x00000002) + +#define IS_AES_IER(ARS_IER) ((ARS_IER == AES_IER_IFINTEN) || (ARS_IER == AES_IER_OFINTEN)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Functions AES exported functions + * @{ + */ +void AES_ECB_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); +void AES_CBC_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); +void AES_CTR_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); +void AES_SetKeyTable(HT_AES_TypeDef* HT_AESn, u32 *Key, u32 keySize); +ErrStatus _AES_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum dir, u32 *iv, u32 length, u32 *inputData, u32 *outputData); +#define AES_ECB_CryptData(a, b, c, d, e) _AES_CryptData(a, b, NULL, c, d, e) +#define AES_CBC_CryptData _AES_CryptData +#define AES_CTR_CryptData(a, b, c, d, e) _AES_CryptData(a, AES_DIR_ENCRYPT, b, c, d, e) +#if 0 +ErrStatus AES_ECB_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum mode, u32 length, u32 *inputData, u32 *outputData); +ErrStatus AES_CBC_CryptData(HT_AES_TypeDef* HT_AESn, AES_DIR_Enum mode, u32 *iv, u32 length, u32 *inputData, u32 *outputData); +ErrStatus AES_CTR_CryptData(HT_AES_TypeDef* HT_AESn, u32 *iv, u32 length, u32 *inputData, u32 *outputData); +#endif + +void AES_StartKey(HT_AES_TypeDef* HT_AESn); +void AES_DeInit(HT_AES_TypeDef* HT_AESn); +void AES_FIFOFlush(HT_AES_TypeDef* HT_AESn); +void AES_Cmd(HT_AES_TypeDef* HT_AESn, ControlStatus NewState); +FlagStatus AES_GetStatus(HT_AES_TypeDef* HT_AESn, u32 AES_Status); +void AES_PDMACmd(HT_AES_TypeDef* HT_AESn, u32 AES_PDMA_xFDMAEN, ControlStatus NewState); +FlagStatus AES_GetIntStatus(HT_AES_TypeDef* HT_AESn, u32 AES_INTSR_x); +void AES_IntConfig(HT_AES_TypeDef* HT_AESn, u32 AES_IER_x, ControlStatus NewState); +void AES_SetInputData(HT_AES_TypeDef* HT_AESn, uc32 AES_Data); +u32 AES_GetOutputData(HT_AES_TypeDef* HT_AESn); +void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, u32 *Vector); +void AESCore_IRQHandler(HT_AES_TypeDef* HT_AESn); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_bftm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_bftm.h new file mode 100644 index 00000000000..5b6e6c904c0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_bftm.h @@ -0,0 +1,111 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_bftm.h + * @version $Rev:: 6393 $ + * @date $Date:: 2022-10-27 #$ + * @brief The header file of the BFTM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_BFTM_H +#define __HT32F5XXXX_BFTM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup BFTM + * @{ + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Types BFTM exported types + * @{ + */ +#if (LIBCFG_BFTM_16BIT_COUNTER) +typedef u16 BFTM_DataTypeDef; +#else +typedef u32 BFTM_DataTypeDef; +#endif +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Constants BFTM exported constants + * @{ + */ +#define IS_BFTM(x) (IS_BFTM0(x) || IS_BFTM1(x)) + +#define IS_BFTM0(x) (x == HT_BFTM0) + +#if (LIBCFG_BFTM1) +#define IS_BFTM1(x) (x == HT_BFTM1) +#else +#define IS_BFTM1(x) (0) +#endif + +#define BFTM_FLAG_MATCH (1UL << 0) +#define BFTM_INT_MATCH (1UL << 0) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Functions BFTM exported functions + * @{ + */ +void BFTM_DeInit(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_EnaCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState); +void BFTM_SetCompare(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCompare); +u32 BFTM_GetCompare(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_SetCounter(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCounter); +u32 BFTM_GetCounter(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_OneShotModeCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState); +void BFTM_IntConfig(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState); +FlagStatus BFTM_GetFlagStatus(HT_BFTM_TypeDef* HT_BFTMn); +void BFTM_ClearFlag(HT_BFTM_TypeDef* HT_BFTMn); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_can.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_can.h new file mode 100644 index 00000000000..a66d141dd79 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_can.h @@ -0,0 +1,498 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_can.h + * @version $Rev:: 7188 $ + * @date $Date:: 2023-08-31 #$ + * @brief The header file of the CAN library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_CAN_H +#define __HT32F5XXXX_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Types CAN exported types + * @{ + */ + +/** + * @brief CAN message structure + */ +typedef struct +{ + u32 IdType; + u32 FrameType; + u32 Id; + u32 DLC; +} STR_CANMSG_TypeDef; + +/** + * @brief CAN TX message structure + */ +typedef struct +{ + u32 IdType; + u32 FrameType; + u32 Id; + u32 MCR; + u32 DLC; + u32 EOB; + u32 RMTEN; + u32 UMASK; + u32 Data[8]; +} STR_CANMSG_T_TypeDef; + +/** + * @brief CAN RX message structure + */ +typedef struct +{ + u32 IdType; + u32 Id; + u32 u8Xtd; + u32 u8Dir; + u32 MCR; + u32 MASK0; + u32 MASK1; + u32 EOB; + u32 UMASK; + u32 RMTEN; + u32 DIR; /* For receive remote frame. */ + } STR_CANMSG_R_TypeDef; + +/** + * @brief CAN mask message structure + */ +typedef struct +{ + u32 u8Xtd; + u32 u8Dir; + u32 u32Id; + u32 u8IdType; +} STR_CANMASK_TyprDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Constants CAN exported constants + * @{ + */ +#define IS_CAN(x) IS_CAN0(x) +#define IS_CAN0(x) (x == HT_CAN0) + +/** + * @brief CAN Test Mode Constant Definitions + */ +#define CAN_NORMAL_MODE 0 +#define CAN_BASIC_MODE 0x04 +#define CAN_SILENT_MODE 0x08 +#define CAN_LBACK_MODE 0x10 +#define CAN_LBS_MODE 0x18 + +/** + * @brief DMessage ID Type Constant Definitions + */ +#define CAN_STD_ID 0 +#define CAN_EXT_ID 1 + +/** + * @brief Message Frame Type Constant Definitions + */ +#define CAN_REMOTE_FRAME 0 +#define CAN_DATA_FRAME 1 + +#define CAN_NBR 1 +#define CAN_VECTOR_NBR 1 +#define DATA_NBR 4 + +/** + * @brief CAN CR Bit Field Definitions + */ +#define CAN_CR_TEST_Pos 7 /*!< CAN_T::CR: TEST Position */ +#define CAN_CR_TEST_Msk (1ul << CAN_CR_TEST_Pos) /*!< CAN_T::CR: TEST Mask */ + +#define CAN_CR_CCE_Pos 6 /*!< CAN_T::CR: CCE Position */ +#define CAN_CR_CCE_Msk (1ul << CAN_CR_CCE_Pos) /*!< CAN_T::CR: CCE Mask */ + +#define CAN_CR_DAR_Pos 5 /*!< CAN_T::CR: DAR Position */ +#define CAN_CR_DAR_Msk (1ul << CAN_CR_DAR_Pos) /*!< CAN_T::CR: DAR Mask */ + +#define CAN_CR_EIE_Pos 3 /*!< CAN_T::CR: EIE Position */ +#define CAN_CR_EIE_Msk (1ul << CAN_CR_EIE_Pos) /*!< CAN_T::CR: EIE Mask */ + +#define CAN_CR_SIE_Pos 2 /*!< CAN_T::CR: SIE Position */ +#define CAN_CR_SIE_Msk (1ul << CAN_CR_SIE_Pos) /*!< CAN_T::CR SIE Mask */ + +#define CAN_CR_IE_Pos 1 /*!< CAN_T::CR: IE Position */ +#define CAN_CR_IE_Msk (1ul << CAN_CR_IE_Pos) /*!< CAN_T::CR: IE Mask */ + +#define CAN_CR_INIT_Pos 0 /*!< CAN_T::CR: INIT Position */ +#define CAN_CR_INIT_Msk (1ul << CAN_CR_INIT_Pos) /*!< CAN_T::CR: INIT Mask */ + +/** + * @brief CAN STATUS Bit Field Definitions + */ +#define CAN_SR_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */ +#define CAN_SR_BOFF_Msk (1ul << CAN_SR_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Mask */ + +#define CAN_SR_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */ +#define CAN_SR_EWARN_Msk (1ul << CAN_SR_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Mask */ + +#define CAN_SR_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */ +#define CAN_SR_EPASS_Msk (1ul << CAN_SR_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Mask */ + +#define CAN_SR_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */ +#define CAN_SR_RXOK_Msk (1ul << CAN_SR_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Mask */ + +#define CAN_SR_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */ +#define CAN_SR_TXOK_Msk (1ul << CAN_SR_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Mask */ + +#define CAN_SR_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */ +#define CAN_SR_LEC_Msk (0x3ul << CAN_SR_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */ + +/** + * @brief CAN ECR Bit Field Definitions + */ +#define CAN_ECR_RP_Pos 15 /*!< CAN_T::ECR: RP Position */ +#define CAN_ECR_RP_Msk (1ul << CAN_ECR_RP_Pos) /*!< CAN_T::ECR: RP Mask */ + +#define CAN_ECR_REC_Pos 8 /*!< CAN_T::ECR: REC Position */ +#define CAN_ECR_REC_Msk (0x7Ful << CAN_ECR_REC_Pos) /*!< CAN_T::ECR: REC Mask */ + +#define CAN_ECR_TEC_Pos 0 /*!< CAN_T::ECR: TEC Position */ +#define CAN_ECR_TEC_Msk (0xFFul << CAN_ECR_TEC_Pos) /*!< CAN_T::ECR: TEC Mask */ + +/** + * @brief CAN BTR Bit Field Definitions + */ +#define CAN_BTR_TSEG1_Pos 12 /*!< CAN_T::BTR: TSEG1 Position */ +#define CAN_BTR_TSEG1_Msk (0x7ul << CAN_BTR_TSEG1_Pos) /*!< CAN_T::BTR: TSEG1 Mask */ + +#define CAN_BTR_TSEG0_Pos 8 /*!< CAN_T::BTR: TSEG0 Position */ +#define CAN_BTR_TSEG0_Msk (0xFul << CAN_BTR_TSEG0_Pos) /*!< CAN_T::BTR: TSEG0 Mask */ + +#define CAN_BTR_SJW_Pos 6 /*!< CAN_T::BTR: SJW Position */ +#define CAN_BTR_SJW_Msk (0x3ul << CAN_BTR_SJW_Pos) /*!< CAN_T::BTR: SJW Mask */ + +#define CAN_BTR_BRP_Pos 0 /*!< CAN_T::BTR: BRP Position */ +#define CAN_BTR_BRP_Msk (0x3Ful << CAN_BTR_BRP_Pos) /*!< CAN_T::BTR: BRP Mask */ + +/** + * @brief CAN IR Bit Field Definitions + */ +#define CAN_IR_INTID_Pos 0 /*!< CAN_T::IR: INTID Position */ +#define CAN_IR_INTID_Msk (0xFFFFul << CAN_IR_INTID_Pos) /*!< CAN_T::R: INTID Mask */ + +/** + * @brief CAN TEST Bit Field Definitions + */ +#define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */ +#define CAN_TEST_RX_Msk (1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX Mask */ + +#define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */ +#define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX Mask */ + +#define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */ +#define CAN_TEST_LBACK_Msk (1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK Mask */ + +#define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */ +#define CAN_TEST_SILENT_Msk (1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */ + +#define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */ +#define CAN_TEST_BASIC_Msk (1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */ + +/** + * @brief CAN BPRE Bit Field Definitions + */ +#define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */ +#define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */ + +/** + * @brief CAN IFn_CREQ Bit Field Definitions + */ +#define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_T::IFnCREQ: BUSY Position */ +#define CAN_IF_CREQ_BUSY_Msk (1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_T::IFnCREQ: BUSY Mask */ + +#define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_T::IFnCREQ: MSGNUM Position */ +#define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_T::IFnCREQ: MSGNUM Mask */ + +/** + * @brief CAN IFn_CMASK Bit Field Definitions + */ +#define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_T::IFnCMASK: WRRD Position */ +#define CAN_IF_CMASK_WRRD_Msk (1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_T::IFnCMASK: WRRD Mask */ + +#define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_T::IFnCMASK: MASK Position */ +#define CAN_IF_CMASK_MASK_Msk (1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_T::IFnCMASK: MASK Mask */ + +#define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_T::IFnCMASK: ARB Position */ +#define CAN_IF_CMASK_ARB_Msk (1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_T::IFnCMASK: ARB Mask */ + +#define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_T::IFnCMASK: CONTROL Position */ +#define CAN_IF_CMASK_CONTROL_Msk (1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_T::IFnCMASK: CONTROL Mask */ + +#define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_T::IFnCMASK: CLRINTPND Position */ +#define CAN_IF_CMASK_CLRINTPND_Msk (1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_T::IFnCMASK: CLRINTPND Mask */ + +#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_T::IFnCMASK: TXRQSTNEWDAT Position */ +#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_T::IFnCMASK: TXRQSTNEWDAT Mask */ + +#define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_T::IFnCMASK: DATAA Position */ +#define CAN_IF_CMASK_DATAA_Msk (1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_T::IFnCMASK: DATAA Mask */ + +#define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_T::IFnCMASK: DATAB Position */ +#define CAN_IF_CMASK_DATAB_Msk (1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_T::IFnCMASK: DATAB Mask */ + +/** + * @brief CAN IFn_MASK0 Bit Field Definitions + */ +#define CAN_IF_MASK0_MSK_Pos 0 /*!< CAN_T::IFnMASK0: MSK Position */ +#define CAN_IF_MASK0_MSK_Msk (0xFFul << CAN_IF_MASK0_MSK_Pos) /*!< CAN_T::IFnMASK0: MSK Mask */ + +/** + * @brief CAN IFn_MASK1 Bit Field Definitions + */ +#define CAN_IF_MASK1_MXTD_Pos 15 /*!< CAN_T::IFnMASK1: MXTD Position */ +#define CAN_IF_MASK1_MXTD_Msk (1ul << CAN_IF_MASK1_MXTD_Pos) /*!< CAN_T::IFnMASK1: MXTD Mask */ + +#define CAN_IF_MASK1_MDIR_Pos 14 /*!< CAN_T::IFnMASK1: MDIR Position */ +#define CAN_IF_MASK1_MDIR_Msk (1ul << CAN_IF_MASK1_MDIR_Pos) /*!< CAN_T::IFnMASK1: MDIR Mask */ + +#define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_T::IFnMASK1: MSK Position */ +#define CAN_IF_MASK1_MSK_Msk (0x1FFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_T::IFnMASK1: MSK Mask */ + +/** + * @brief CAN IFn_ARB0 Bit Field Definitions + */ +#define CAN_IF_ARB0_ID_Pos 0 /*!< CAN_T::IFnARB0: ID Position */ +#define CAN_IF_ARB0_ID_Msk (0xFFFFul << CAN_IF_ARB0_ID_Pos) /*!< CAN_T::IFnARB0: ID Mask */ + +/** + * @brief CAN IFn_ARB1 Bit Field Definitions + */ +#define CAN_IF_ARB1_MSGVAL_Pos 15 /*!< CAN_T::IFnARB1: MSGVAL Position */ +#define CAN_IF_ARB1_MSGVAL_Msk (1ul << CAN_IF_ARB1_MSGVAL_Pos) /*!< CAN_T::IFnARB1: MSGVAL Mask */ + +#define CAN_IF_ARB1_XTD_Pos 14 /*!< CAN_T::IFnARB1: XTD Position */ +#define CAN_IF_ARB1_XTD_Msk (1ul << CAN_IF_ARB1_XTD_Pos) /*!< CAN_T::IFnARB1: XTD Mask */ + +#define CAN_IF_ARB1_DIR_Pos 13 /*!< CAN_T::IFnARB1: DIR Position */ +#define CAN_IF_ARB1_DIR_Msk (1ul << CAN_IF_ARB1_DIR_Pos) /*!< CAN_T::IFnARB1: DIR Mask */ + +#define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_T::IFnARB1: ID Position */ +#define CAN_IF_ARB1_ID_Msk (0x1FFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_T::IFnARB1: ID Mask */ + +/** + * @brief CAN IFn_MCR Bit Field Definitions + */ +#define CAN_IF_MCR_NEWDAT_Pos 15 /*!< CAN_T::IFnMCON: NEWDAT Position */ +#define CAN_IF_MCR_NEWDAT_Msk (1ul << CAN_IF_MCR_NEWDAT_Pos) /*!< CAN_T::IFnMCON: NEWDAT Mask */ + +#define CAN_IF_MCR_MSGLST_Pos 14 /*!< CAN_T::IFnMCON: MSGLST Position */ +#define CAN_IF_MCR_MSGLST_Msk (1ul << CAN_IF_MCR_MSGLST_Pos) /*!< CAN_T::IFnMCON: MSGLST Mask */ + +#define CAN_IF_MCR_INTPND_Pos 13 /*!< CAN_T::IFnMCON: INTPND Position */ +#define CAN_IF_MCR_INTPND_Msk (1ul << CAN_IF_MCR_INTPND_Pos) /*!< CAN_T::IFnMCON: INTPND Mask */ + +#define CAN_IF_MCR_UMASK_Pos 12 /*!< CAN_T::IFnMCON: UMASK Position */ +#define CAN_IF_MCR_UMASK_Msk (1ul << CAN_IF_MCR_UMASK_Pos) /*!< CAN_T::IFnMCON: UMASK Mask */ + +#define CAN_IF_MCR_TXIE_Pos 11 /*!< CAN_T::IFnMCON: TXIE Position */ +#define CAN_IF_MCR_TXIE_Msk (1ul << CAN_IF_MCR_TXIE_Pos) /*!< CAN_T::IFnMCON: TXIE Mask */ + +#define CAN_IF_MCR_RXIE_Pos 10 /*!< CAN_T::IFnMCON: RXIE Position */ +#define CAN_IF_MCR_RXIE_Msk (1ul << CAN_IF_MCR_RXIE_Pos) /*!< CAN_T::IFnMCON: RXIE Mask */ + +#define CAN_IF_MCR_RMTEN_Pos 9 /*!< CAN_T::IFnMCON: RMTEN Position */ +#define CAN_IF_MCR_RMTEN_Msk (1ul << CAN_IF_MCR_RMTEN_Pos) /*!< CAN_T::IFnMCON: RMTEN Mask */ + +#define CAN_IF_MCR_TXRQST_Pos 8 /*!< CAN_T::IFnMCON: TXRQST Position */ +#define CAN_IF_MCR_TXRQST_Msk (1ul << CAN_IF_MCR_TXRQST_Pos) /*!< CAN_T::IFnMCON: TXRQST Mask */ + +#define CAN_IF_MCR_EOB_Pos 7 /*!< CAN_T::IFnMCON: EOB Position */ +#define CAN_IF_MCR_EOB_Msk (1ul << CAN_IF_MCR_EOB_Pos) /*!< CAN_T::IFnMCON: EOB Mask */ + +#define CAN_IF_MCR_DLC_Pos 0 /*!< CAN_T::IFnMCON: DLC Position */ +#define CAN_IF_MCR_DLC_Msk (0xFul << CAN_IF_MCR_DLC_Pos) /*!< CAN_T::IFnMCON: DLC Mask */ + +/** + * @brief CAN IFn_DATA_A0 Bit Field Definitions + */ +#define CAN_IF_DAT_A0_DATA1_Pos 8 /*!< CAN_T::IFnDATAA0: DATA1 Position */ +#define CAN_IF_DAT_A0_DATA1_Msk (0xFFul << CAN_IF_DAT_A0_DATA1_Pos) /*!< CAN_T::IFnDATAA0: DATA1 Mask */ + +#define CAN_IF_DAT_A0_DATA0_Pos 0 /*!< CAN_T::IFnDATAA0: DATA0 Position */ +#define CAN_IF_DAT_A0_DATA0_Msk (0xFFul << CAN_IF_DAT_A0_DATA0_Pos) /*!< CAN_T::IFnDATAA0: DATA0 Mask */ + +/** + * @brief CAN IFn_DATA_A1 Bit Field Definitions + */ +#define CAN_IF_DAT_A1_DATA3_Pos 8 /*!< CAN_T::IFnDATAA1: DATA3 Position */ +#define CAN_IF_DAT_A1_DATA3_Msk (0xFFul << CAN_IF_DAT_A1_DATA3_Pos) /*!< CAN_T::IFnDATAA1: DATA3 Mask */ + +#define CAN_IF_DAT_A1_DATA2_Pos 0 /*!< CAN_T::IFnDATAA1: DATA2 Position */ +#define CAN_IF_DAT_A1_DATA2_Msk (0xFFul << CAN_IF_DAT_A1_DATA2_Pos) /*!< CAN_T::IFnDATAA1: DATA2 Mask */ + +/** + * @brief CAN IFn_DATA_B0 Bit Field Definitions + */ +#define CAN_IF_DAT_B0_DATA5_Pos 8 /*!< CAN_T::IFnDATAB0: DATA5 Position */ +#define CAN_IF_DAT_B0_DATA5_Msk (0xFFul << CAN_IF_DAT_B0_DATA5_Pos) /*!< CAN_T::IFnDATAB0: DATA5 Mask */ + +#define CAN_IF_DAT_B0_DATA4_Pos 0 /*!< CAN_T::IFnDATAB0: DATA4 Position */ +#define CAN_IF_DAT_B0_DATA4_Msk (0xFFul << CAN_IF_DAT_B0_DATA4_Pos) /*!< CAN_T::IFnDATAB0: DATA4 Mask */ + +/** + * @brief CAN IFn_DATA_B1 Bit Field Definitions + */ +#define CAN_IF_DAT_B1_DATA7_Pos 8 /*!< CAN_T::IFnDATAB1: DATA7 Position */ +#define CAN_IF_DAT_B1_DATA7_Msk (0xFFul << CAN_IF_DAT_B1_DATA7_Pos) /*!< CAN_T::IFnDATAB1: DATA7 Mask */ + +#define CAN_IF_DAT_B1_DATA6_Pos 0 /*!< CAN_T::IFnDATAB1: DATA6 Position */ +#define CAN_IF_DAT_B1_DATA6_Msk (0xFFul << CAN_IF_DAT_B1_DATA6_Pos) /*!< CAN_T::IFnDATAB1: DATA6 Mask */ + +/** + * @brief CAN IFn_TXRQST0 Bit Field Definitions + */ +#define CAN_IF_TXRQST0_TXRQST_Pos 0 /*!< CAN_T::IFnTXRQST0: TXRQST Position */ +#define CAN_IF_TXRQST0_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST0_TXRQST_Pos) /*!< CAN_T::IFnTXRQST0: TXRQST Mask */ + +/** + * @brief CAN IFn_TXRQST1 Bit Field Definitions + */ +#define CAN_IF_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::IFnTXRQST1: TXRQST Position */ +#define CAN_IF_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST1_TXRQST_Pos) /*!< CAN_T::IFnTXRQST1: TXRQST Mask */ + +/** + * @brief CAN IFn_NDAT0 Bit Field Definitions + */ +#define CAN_IF_NDAT0_NEWDATA_Pos 0 /*!< CAN_T::IFnNDAT0: NEWDATA Position */ +#define CAN_IF_NDAT0_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT0_NEWDATA_Pos) /*!< CAN_T::IFnNDAT0: NEWDATA Mask */ + +/** + * @brief CAN IFn_NDAT1 Bit Field Definitions + */ +#define CAN_IF_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::IFnNDAT1: NEWDATA Position */ +#define CAN_IF_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT1_NEWDATA_Pos) /*!< CAN_T::IFnNDAT1: NEWDATA Mask */ + +/** + * @brief CAN IFn_IPND0 Bit Field Definitions + */ +#define CAN_IF_IPND0_INTPND_Pos 0 /*!< CAN_T::IFnIPND0: INTPND Position */ +#define CAN_IF_IPND0_INTPND_Msk (0xFFFFul << CAN_IF_IPND0_INTPND_Pos) /*!< CAN_T::IFnIPND0: INTPND Mask */ + +/** + * @brief CAN IFn_IPND1 Bit Field Definitions + */ +#define CAN_IF_IPND1_INTPND_Pos 0 /*!< CAN_T::IFnIPND1: INTPND Position */ +#define CAN_IF_IPND1_INTPND_Msk (0xFFFFul << CAN_IF_IPND1_INTPND_Pos) /*!< CAN_T::IFnIPND1: INTPND Mask */ + +/** + * @brief CAN IFn_MVLD0 Bit Field Definitions + */ +#define CAN_IF_MVLD0_MSGVAL_Pos 0 /*!< CAN_T::IFnMVLD0: MSGVAL Position */ +#define CAN_IF_MVLD0_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD0_MSGVAL_Pos) /*!< CAN_T::IFnMVLD0: MSGVAL Mask */ + +/** + * @brief CAN IFn_MVLD1 Bit Field Definitions + */ +#define CAN_IF_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::IFnMVLD1: MSGVAL Position */ +#define CAN_IF_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD1_MSGVAL_Pos) /*!< CAN_T::IFnMVLD1: MSGVAL Mask */ + +/** + * @brief CAN WUEN Bit Field Definitions + */ +#define CAN_WUEN_WAKUP_EN_Pos 0 /*!< CAN_T::WUEN: WAKUP_EN Position */ +#define CAN_WUEN_WAKUP_EN_Msk (1ul << CAN_WUEN_WAKUP_EN_Pos) /*!< CAN_T::WUEN: WAKUP_EN Mask */ + +/** + * @brief CAN WUSTATUS Bit Field Definitions + */ +#define CAN_WUSTATUS_WAKUP_STS_Pos 0 /*!< CAN_T::WUSTATUS: WAKUP_STS Position */ +#define CAN_WUSTATUS_WAKUP_STS_Msk (1ul << CAN_WUSTATUS_WAKUP_STS_Pos) /*!< CAN_T::WUSTATUS: WAKUP_STS Mask */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Functions CAN exported functions + * @{ + */ +void CAN_DeInit(HT_CAN_TypeDef* CANx); +u32 CAN_SetBaudRate(HT_CAN_TypeDef *CANx, u32 u32BaudRate); +void CAN_Close(HT_CAN_TypeDef *CANx); +u32 CAN_Open(HT_CAN_TypeDef *CANx, u32 u32BaudRate, u32 u32Mode); +void CAN_CLR_INT_PENDING_BIT(HT_CAN_TypeDef *CANx, u32 u32MsgNum); +void CAN_EnableInt(HT_CAN_TypeDef *CANx, u32 u32Mask); +void CAN_DisableInt(HT_CAN_TypeDef *CANx, u32 u32Mask); +s32 CAN_Transmit(HT_CAN_TypeDef *CANx, u32 u32MsgNum , STR_CANMSG_T_TypeDef* pCanMsg); +s32 CAN_Receive(HT_CAN_TypeDef *CANx, u32 u32MsgNum , STR_CANMSG_T_TypeDef* pCanMsg); +s32 CAN_SetRxMsg(HT_CAN_TypeDef *CANx, u32 u32MsgNum , STR_CANMSG_R_TypeDef* pCanMsg); +s32 CAN_SetTxMsg(HT_CAN_TypeDef *CANx, u32 u32MsgNum , STR_CANMSG_T_TypeDef* pCanMsg); +s32 CAN_TriggerTxMsg(HT_CAN_TypeDef *CANx, u32 u32MsgNum); +void CAN_EnterInitMode(HT_CAN_TypeDef *CANx); +void CAN_LeaveInitMode(HT_CAN_TypeDef *CANx); +void CAN_WaitMsg(HT_CAN_TypeDef *CANx); +u32 CAN_GetCANBitRate(HT_CAN_TypeDef *CANx); +void CAN_EnterTestMode(HT_CAN_TypeDef *CANx, u32 u8TestMask); +void CAN_LeaveTestMode(HT_CAN_TypeDef *CANx); +u32 CAN_IsNewDataReceived(HT_CAN_TypeDef *CANx, u32 u8MsgObj); +s32 CAN_BasicSendMsg(HT_CAN_TypeDef *CANx, STR_CANMSG_T_TypeDef* pCanMsg); +s32 CAN_BasicReceiveMsg(HT_CAN_TypeDef *CANx, STR_CANMSG_T_TypeDef* pCanMsg); +s32 CAN_SetRxMsgObj(HT_CAN_TypeDef *CANx, u32 MsgObj, STR_CANMSG_R_TypeDef* pCanMsg); +s32 CAN_ReadMsgObj(HT_CAN_TypeDef *CANx, u32 u8MsgObj, u32 u8Release, STR_CANMSG_T_TypeDef* pCanMsg); +s32 CAN_MsgObjMaskConfig(HT_CAN_TypeDef *tCAN, u32 u8MsgObj, STR_CANMSG_R_TypeDef* MaskMsg); +s32 CAN_SetMultiRxMsg(HT_CAN_TypeDef *CANx, u32 u32MsgNum , u32 u32MsgCount, STR_CANMSG_R_TypeDef* pCanMsg); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ckcu.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ckcu.h new file mode 100644 index 00000000000..531078537b5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ckcu.h @@ -0,0 +1,936 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_ckcu.h + * @version $Rev:: 7108 $ + * @date $Date:: 2023-08-09 #$ + * @brief The header file of the Clock Control Unit library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_CKCU_H +#define __HT32F5XXXX_CKCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CKCU + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Exported_Types CKCU exported types + * @{ + */ + +#if (!LIBCFG_CKCU_NO_APB_PRESCALER) +/** + * @brief Enumeration of APB peripheral prescaler. + */ +typedef enum +{ + CKCU_APBCLKPRE_DIV1 = 0, + CKCU_APBCLKPRE_DIV2, + CKCU_APBCLKPRE_DIV4, + CKCU_APBCLKPRE_DIV8, + CKCU_APBCLKPRE_DIV16, + CKCU_APBCLKPRE_DIV32 +} CKCU_APBCLKPRE_TypeDef; +#endif + +/** + * @brief Enumeration of CK_REF prescaler. + */ +typedef enum +{ + CKCU_CKREFPRE_DIV2 = 0, + CKCU_CKREFPRE_DIV4, + CKCU_CKREFPRE_DIV6, + CKCU_CKREFPRE_DIV8, + CKCU_CKREFPRE_DIV10, + CKCU_CKREFPRE_DIV12, + CKCU_CKREFPRE_DIV14, + CKCU_CKREFPRE_DIV16, + CKCU_CKREFPRE_DIV18, + CKCU_CKREFPRE_DIV20, + CKCU_CKREFPRE_DIV22, + CKCU_CKREFPRE_DIV24, + CKCU_CKREFPRE_DIV26, + CKCU_CKREFPRE_DIV28, + CKCU_CKREFPRE_DIV30, + CKCU_CKREFPRE_DIV32, + CKCU_CKREFPRE_DIV34, + CKCU_CKREFPRE_DIV36, + CKCU_CKREFPRE_DIV38, + CKCU_CKREFPRE_DIV40, + CKCU_CKREFPRE_DIV42, + CKCU_CKREFPRE_DIV44, + CKCU_CKREFPRE_DIV46, + CKCU_CKREFPRE_DIV48, + CKCU_CKREFPRE_DIV50, + CKCU_CKREFPRE_DIV52, + CKCU_CKREFPRE_DIV54, + CKCU_CKREFPRE_DIV56, + CKCU_CKREFPRE_DIV58, + CKCU_CKREFPRE_DIV60, + CKCU_CKREFPRE_DIV62, + CKCU_CKREFPRE_DIV64 +} CKCU_CKREFPRE_TypeDef; + +#if (!LIBCFG_NO_PLL) +/** + * @brief Enumeration of PLL clock source. + */ +typedef enum +{ + CKCU_PLLSRC_HSE = 0, + CKCU_PLLSRC_HSI +} CKCU_PLLSRC_TypeDef; + +#define IS_PLL_CLKSRC(SRC) ((SRC == CKCU_PLLSRC_HSE) || \ + (SRC == CKCU_PLLSRC_HSI)) +#endif + +#if (LIBCFG_CKCU_USB_PLL) +/** + * @brief Enumeration of CK_USB clock source. + */ +typedef enum +{ + CKCU_CKPLL = 0, + CKCU_CKUSBPLL +} CKCU_USBSRC_TypeDef; +#endif + +#if (LIBCFG_CKCU_LCD_SRC) +/** + * @brief Enumeration of CK_LCD clock source. + */ +typedef enum +{ + CKCU_LCDSRC_LSI = 0, + #if (LIBCFG_LSE) + CKCU_LCDSRC_LSE, + #endif + CKCU_LCDSRC_HSI, + CKCU_LCDSRC_HSE +} CKCU_LCDSRC_TypeDef; +#endif + +#if (LIBCFG_CKCU_MCTM_SRC) +/** + * @brief Enumeration of MCTM clock source. + */ +typedef enum +{ + CKCU_MCTMSRC_AHB = 0, + CKCU_MCTMSRC_USBPLL +} CKCU_MCTMSRC_TypeDef; + +#define IS_MCTM_SRC(SRC) ((SRC == CKCU_MCTMSRC_AHB) || \ + (SRC == CKCU_MCTMSRC_USBPLL)) +#endif + + +#if (((LIBCFG_LSE) || (LIBCFG_USBD) || (LIBCFG_CKCU_REFCLK_EXT_PIN)) && (!LIBCFG_CKCU_NO_AUTO_TRIM)) +/** + * @brief Enumeration of HSI auto-trim clock source. + */ +typedef enum +{ + #if (LIBCFG_LSE) + CKCU_ATC_LSE = 0, + #endif + #if (LIBCFG_USBD) + CKCU_ATC_USB = 1, + #endif + #if (LIBCFG_CKCU_REFCLK_EXT_PIN) + CKCU_ATC_CKIN = 2, + #endif +} CKCU_ATC_TypeDef; +#endif + +#if (LIBCFG_CKCU_ATM_V01) +/** + * @brief Enumeration of ATC search algorithm. + */ +typedef enum +{ + CKCU_ATC_BINARY_SEARCH = 0, + CKCU_ATC_LINEAR_SEARCH = 8 +} CKCU_ATCSearchAlgorithm_TypeDef; + +/** + * @brief Enumeration of ATC frequency tolerance. + */ +typedef enum +{ + CKCU_ATC_DOUBLE_PRECISION = 0, + CKCU_ATC_SINGLE_PRECISION = 4 +} CKCU_ATCFrqTolerance_TypeDef; +#endif + +/** + * @brief Enumeration of CK_AHB prescaler. + */ +typedef enum +{ + CKCU_SYSCLK_DIV1 = 0, + CKCU_SYSCLK_DIV2, + CKCU_SYSCLK_DIV4, + CKCU_SYSCLK_DIV8, + CKCU_SYSCLK_DIV16, + CKCU_SYSCLK_DIV32 +} CKCU_SYSCLKDIV_TypeDef; + +/** + * @brief Enumeration of CK_ADC prescaler. + */ +typedef enum +{ + #if (LIBCFG_CKCU_NO_ADCPRE_DIV1) + #else + CKCU_ADCPRE_DIV1 = 0, + #endif + CKCU_ADCPRE_DIV2 = 1, + CKCU_ADCPRE_DIV4, + CKCU_ADCPRE_DIV8, + CKCU_ADCPRE_DIV16, + CKCU_ADCPRE_DIV32, + CKCU_ADCPRE_DIV64, + CKCU_ADCPRE_DIV3 +} CKCU_ADCPRE_TypeDef; + +/** + * @brief Enumeration of CK_ADCn. + */ +typedef enum +{ + CKCU_ADCPRE_ADC0 = 16, + #if (LIBCFG_ADC1) + CKCU_ADCPRE_ADC1 = 20, + #endif +} CKCU_ADCPRE_ADCn_TypeDef; + +#if (LIBCFG_LCD) +/** + * @brief Enumeration of CK_LCD prescaler. + */ +typedef enum +{ + CKCU_LCDPRE_DIV1 = 0, + CKCU_LCDPRE_DIV2, + CKCU_LCDPRE_DIV4, + CKCU_LCDPRE_DIV8, + CKCU_LCDPRE_DIV16, +} CKCU_LCDPRE_TypeDef; +#endif + +#if (LIBCFG_MIDI) +/** + * @brief Enumeration of CK_MIDI prescaler. + */ +typedef enum +{ + CKCU_MIDIPRE_DIV16 = 0, + CKCU_MIDIPRE_DIV13, + CKCU_MIDIPRE_DIV11, + CKCU_MIDIPRE_DIV9, + CKCU_MIDIPRE_DIV8, +} CKCU_MIDIPRE_TypeDef; +#endif + +/** + * @brief Enumeration of System clock source. + */ +typedef enum +{ +#if (!LIBCFG_NO_PLL) + CKCU_SW_PLL = 1, +#endif + CKCU_SW_HSE = 2, + CKCU_SW_HSI = 3, + #if (LIBCFG_LSE) + CKCU_SW_LSE = 6, + #endif + CKCU_SW_LSI = 7 +} CKCU_SW_TypeDef; + +/** + * @brief Enumeration of CKOUT clock source. + */ +typedef enum +{ + CKCU_CKOUTSRC_REFCK = 0, + CKCU_CKOUTSRC_HCLK_DIV16 = 1, + CKCU_CKOUTSRC_SYSCK_DIV16 = 2, + CKCU_CKOUTSRC_HSECK_DIV16 = 3, + CKCU_CKOUTSRC_HSICK_DIV16 = 4, + #if (LIBCFG_LSE) + CKCU_CKOUTSRC_LSECK = 5, + #endif + CKCU_CKOUTSRC_LSICK = 6 +} CKCU_CKOUTSRC_TypeDef; + +#if (!LIBCFG_NO_PLL) +/** + * @brief Enumeration of PLL clock source status. + */ +typedef enum +{ + CKCU_PLLST_SYSCK = 1, + #if (LIBCFG_USBD) + CKCU_PLLST_USB = 4, + #endif + CKCU_PLLST_REFCK = 8 +} CKCU_PLLST_TypeDef; +#endif + +/** + * @brief Enumeration of HSI clock source status. + */ +typedef enum +{ + CKCU_HSIST_SYSCK = 1, +#if (!LIBCFG_NO_PLL) + CKCU_HSIST_PLL = 2, +#endif + CKCU_HSIST_CKM = 4 +} CKCU_HSIST_TypeDef; + +/** + * @brief Enumeration of HSE clock source status. + */ +typedef enum +{ + CKCU_HSEST_SYSCK = 1, +#if (!LIBCFG_NO_PLL) + CKCU_HSEST_PLL +#endif +} CKCU_HSEST_TypeDef; + +/** + * @brief Definition of CKOUT Init Structure. + */ +typedef struct +{ + CKCU_CKOUTSRC_TypeDef CKOUTSRC; +} CKCU_CKOUTInitTypeDef; + +#if (!LIBCFG_NO_PLL) +/** + * @brief Definition of PLL Init Structure. + */ +typedef struct +{ + u32 CFG; + CKCU_PLLSRC_TypeDef ClockSource; + ControlStatus BYPASSCmd; +} CKCU_PLLInitTypeDef; +#endif + +/** + * @brief Definition of structure for clock frequency. + */ +typedef struct +{ +#if (!LIBCFG_NO_PLL) + u32 PLL_Freq; +#endif + u32 SYSCK_Freq; + u32 HCLK_Freq; +#if (HT32_LIB_ENABLE_GET_CK_ADC) +#if (!LIBCFG_NO_ADC) + u32 ADC0_Freq; +#endif +#if (LIBCFG_ADC1) + u32 ADC1_Freq; +#endif +#endif +} CKCU_ClocksTypeDef; + +#if (LIBCFG_CKCU_ATM_V01) +/** + * @brief Definition of ATC Init Structure. + */ +typedef struct +{ + CKCU_ATCSearchAlgorithm_TypeDef SearchAlgorithm; + CKCU_ATCFrqTolerance_TypeDef FrqTolerance; +} CKCU_ATCInitTypeDef; +#endif + +/** + * @brief Definition of initial structure of peripheral clock control. + */ +typedef union +{ + struct + { + /* Definitions of AHB clock control */ + unsigned long FMC :1; // Bit 0 + unsigned long :1; // Bit 1 + unsigned long SRAM :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long PDMA :1; // Bit 4 + unsigned long BM :1; // Bit 5 + unsigned long APB :1; // Bit 6 + unsigned long :1; // Bit 7 + + unsigned long :1; // Bit 8 + unsigned long :1; // Bit 9 + unsigned long USBD :1; // Bit 10 + unsigned long CKREF :1; // Bit 11 + unsigned long EBI :1; // Bit 12 + unsigned long CRC :1; // Bit 13 + unsigned long :1; // Bit 14 + unsigned long AES :1; // Bit 15 + + unsigned long PA :1; // Bit 16 + unsigned long PB :1; // Bit 17 + unsigned long PC :1; // Bit 18 + unsigned long PD :1; // Bit 19 + unsigned long PE :1; // Bit 20 + unsigned long PF :1; // Bit 21 + unsigned long :1; // Bit 22 + unsigned long :1; // Bit 23 + + unsigned long DIV :1; // Bit 24 + unsigned long QSPI :1; // Bit 25 + unsigned long RF :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long :1; // Bit 28 + unsigned long :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB0 clock control */ + unsigned long I2C0 :1; // Bit 0 + unsigned long I2C1 :1; // Bit 1 + unsigned long I2C2 :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long SPI0 :1; // Bit 4 + unsigned long SPI1 :1; // Bit 5 + unsigned long :1; // Bit 6 + unsigned long :1; // Bit 7 + + unsigned long USART0 :1; // Bit 8 + unsigned long USART1 :1; // Bit 9 + unsigned long UART0 :1; // Bit 10 + unsigned long UART1 :1; // Bit 11 + unsigned long UART2 :1; // Bit 12 + unsigned long UART3 :1; // Bit 13 + unsigned long AFIO :1; // Bit 14 + unsigned long EXTI :1; // Bit 15 + + unsigned long :1; // Bit 16 + unsigned long :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 + unsigned long SLED0 :1; // Bit 22 + unsigned long SLED1 :1; // Bit 23 + + unsigned long SCI0 :1; // Bit 24 + unsigned long I2S :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long SCI1 :1; // Bit 27 + unsigned long MIDI :1; // Bit 28 + unsigned long LEDC :1; // Bit 29 + unsigned long CAN0 :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB1 clock control */ + unsigned long MCTM0 :1; // Bit 0 + unsigned long :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long WDT :1; // Bit 4 + unsigned long :1; // Bit 5 + unsigned long BKP :1; // Bit 6 + unsigned long DAC1 :1; // Bit 7 + + unsigned long GPTM0 :1; // Bit 8 + unsigned long GPTM1 :1; // Bit 9 + unsigned long :1; // Bit 10 + unsigned long :1; // Bit 11 + unsigned long PWM0 :1; // Bit 12 + unsigned long PWM1 :1; // Bit 13 + unsigned long PWM2 :1; // Bit 14 + unsigned long :1; // Bit 15 + + unsigned long BFTM0 :1; // Bit 16 + unsigned long BFTM1 :1; // Bit 17 + unsigned long TKEY :1; // Bit 18 + unsigned long LCDR :1; // Bit 19 + unsigned long LCDC :1; // Bit 20 + unsigned long DAC0 :1; // Bit 21 + unsigned long CMP :1; // Bit 22 + unsigned long OPA :1; // Bit 23 + + unsigned long ADC0 :1; // Bit 24 + unsigned long ADC1 :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long SCTM0 :1; // Bit 28 + unsigned long SCTM1 :1; // Bit 29 + unsigned long SCTM2 :1; // Bit 30 + unsigned long SCTM3 :1; // Bit 31 + } Bit; + u32 Reg[3]; +} CKCU_PeripClockConfig_TypeDef; + +#define CKCU_APBPCSR_OFFSET (5) +#define CKCU_APBPCSR0 (0 << CKCU_APBPCSR_OFFSET) +#define CKCU_APBPCSR1 (1 << CKCU_APBPCSR_OFFSET) +#define CKCU_APBPCSR2 (4 << CKCU_APBPCSR_OFFSET) +typedef enum +{ + CKCU_PCLK_I2C0 = (CKCU_APBPCSR0 | 0), + #if (LIBCFG_I2C1) + CKCU_PCLK_I2C1 = (CKCU_APBPCSR0 | 2), + #endif + CKCU_PCLK_SPI0 = (CKCU_APBPCSR0 | 4), + #if (LIBCFG_SPI1) + CKCU_PCLK_SPI1 = (CKCU_APBPCSR0 | 6), + #endif + #if (LIBCFG_UART2) + CKCU_PCLK_UART2 = (CKCU_APBPCSR0 | 8), + #endif + #if (LIBCFG_UART3) + CKCU_PCLK_UART3 = (CKCU_APBPCSR0 | 10), + #endif + CKCU_PCLK_BFTM0 = (CKCU_APBPCSR0 | 12), + #if (LIBCFG_BFTM1) + CKCU_PCLK_BFTM1 = (CKCU_APBPCSR0 | 14), + #endif + #if (LIBCFG_MCTM0) + CKCU_PCLK_MCTM0 = (CKCU_APBPCSR0 | 16), + #endif + #if (!LIBCFG_NO_GPTM0) + CKCU_PCLK_GPTM0 = (CKCU_APBPCSR0 | 20), + #endif + #if (LIBCFG_GPTM1) + CKCU_PCLK_GPTM1 = (CKCU_APBPCSR0 | 22), + #endif + #if (!LIBCFG_NO_USART0) + CKCU_PCLK_USART0 = (CKCU_APBPCSR0 | 24), + #endif + #if (LIBCFG_USART1) + CKCU_PCLK_USART1 = (CKCU_APBPCSR0 | 26), + #endif + CKCU_PCLK_UART0 = (CKCU_APBPCSR0 | 28), + #if (LIBCFG_UART1) + CKCU_PCLK_UART1 = (CKCU_APBPCSR0 | 30), + #endif + CKCU_PCLK_AFIO = (CKCU_APBPCSR1 | 0), + CKCU_PCLK_EXTI = (CKCU_APBPCSR1 | 2), + #if (!LIBCFG_NO_ADC) + CKCU_PCLK_ADC0 = (CKCU_APBPCSR1 | 4), + #endif + #if (LIBCFG_ADC1) + CKCU_PCLK_ADC1 = (CKCU_APBPCSR1 | 6), + #endif + #if (LIBCFG_CMP) + CKCU_PCLK_CMP = (CKCU_APBPCSR1 | 8), + #endif + #if (LIBCFG_OPA) + CKCU_PCLK_OPA = (CKCU_APBPCSR1 | 10), + #endif + CKCU_PCLK_WDTR = (CKCU_APBPCSR1 | 12), + CKCU_PCLK_BKPR = (CKCU_APBPCSR1 | 14), + #if (LIBCFG_SCI0) + CKCU_PCLK_SCI0 = (CKCU_APBPCSR1 | 16), + #endif + #if (LIBCFG_SCI1) + CKCU_PCLK_SCI1 = (CKCU_APBPCSR1 | 18), + #endif + #if (LIBCFG_I2S) + CKCU_PCLK_I2S = (CKCU_APBPCSR1 | 20), + #endif + #if (LIBCFG_I2C2) + CKCU_PCLK_I2C2 = (CKCU_APBPCSR1 | 22), + #endif + #if (LIBCFG_SCTM0) + CKCU_PCLK_SCTM0 = (CKCU_APBPCSR1 | 24), + #endif + #if (LIBCFG_SCTM1) + CKCU_PCLK_SCTM1 = (CKCU_APBPCSR1 | 26), + #endif + #if (LIBCFG_SCTM2) + CKCU_PCLK_SCTM2 = (CKCU_APBPCSR1 | 28), + #endif + #if (LIBCFG_SCTM3) + CKCU_PCLK_SCTM3 = (CKCU_APBPCSR1 | 30), + #endif + #if (LIBCFG_AFE0006) + CKCU_PCLK_AFE = (CKCU_APBPCSR2 | 0), + #endif + #if (LIBCFG_DACDUAL16) || (LIBCFG_DAC0) + CKCU_PCLK_DAC0 = (CKCU_APBPCSR2 | 2), + #endif + #if (LIBCFG_LEDC) + CKCU_PCLK_LEDC = (CKCU_APBPCSR2 | 6), + #endif + #if (LIBCFG_MIDI) + CKCU_PCLK_MIDI = (CKCU_APBPCSR2 | 8), + #endif + #if (LIBCFG_TKEY) + CKCU_PCLK_TKEY = (CKCU_APBPCSR2 | 10), + #endif + #if (LIBCFG_SLED0) + CKCU_PCLK_SLED0 = (CKCU_APBPCSR2 | 12), + #endif + #if (LIBCFG_SLED1) + CKCU_PCLK_SLED1 = (CKCU_APBPCSR2 | 14), + #endif + #if (LIBCFG_PWM0) + CKCU_PCLK_PWM0 = (CKCU_APBPCSR2 | 16), + #endif + #if (LIBCFG_PWM1) + CKCU_PCLK_PWM1 = (CKCU_APBPCSR2 | 18), + #endif + #if (LIBCFG_PWM2) + CKCU_PCLK_PWM2 = (CKCU_APBPCSR2 | 20), + #endif + #if (LIBCFG_CAN0) + CKCU_PCLK_CAN0 = (CKCU_APBPCSR2 | 20), + #endif + #if (LIBCFG_DAC1) + CKCU_PCLK_DAC1 = (CKCU_APBPCSR2 | 24), + #endif +} CKCU_PeripPrescaler_TypeDef; + +#define CKCU_PCLK_ADC CKCU_PCLK_ADC0 +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Exported_Constants CKCU exported constants + * @{ + */ + +/* Definitions of clock ready flag */ +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_FLAG_USBPLLRDY (1UL) +#endif +#if (!LIBCFG_NO_PLL) +#define CKCU_FLAG_PLLRDY (1UL << 1) +#endif +#define CKCU_FLAG_HSERDY (1UL << 2) +#define CKCU_FLAG_HSIRDY (1UL << 3) +#if (LIBCFG_LSE) +#define CKCU_FLAG_LSERDY (1UL << 4) +#endif +#define CKCU_FLAG_LSIRDY (1UL << 5) + +#define IS_CKCU_FLAG(FLAG) (((FLAG & 0xFFFFFFC0) == 0) && (FLAG != 0)) + +/* Definitions of clock interrupt & flag */ +#define CKCU_INT_CKS (1UL) +#define IS_CKCU_INT_FLAG(FLAG) (FLAG == CKCU_INT_CKS) + +#define CKCU_INT_CKSIE (1UL << 16) +#define IS_CKCU_INT(INT) (((INT & 0xFFFEFFFF) == 0) && (INT != 0)) + +#if (!LIBCFG_NO_PLL) +/* Definitions of PLL frequency */ +#define CKCU_PLL_4M_48M ((12UL << 23) | (0UL << 21)) +#define CKCU_PLL_4M_40M ((10UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_48M (( 6UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_40M (( 5UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_32M (( 4UL << 23) | (0UL << 21)) +#define CKCU_PLL_12M_48M (( 4UL << 23) | (0UL << 21)) +#define CKCU_PLL_16M_48M (( 3UL << 23) | (0UL << 21)) + +#if (LIBCFG_CKCU_SYS_CK_60M) +#define CKCU_PLL_4M_60M ((0UL << 28) | (15UL << 23) | (0UL << 21)) +#define CKCU_PLL_8M_60M ((1UL << 28) | (15UL << 23) | (0UL << 21)) +#define CKCU_PLL_12M_60M ((0UL << 28) | ( 5UL << 23) | (0UL << 21)) +#define CKCU_PLL_16M_56M ((1UL << 28) | ( 7UL << 23) | (0UL << 21)) +#endif + +#define IS_PLL_CFG(CFG) (((CFG & 0xE81FFFFF) == 0x0) && (CFG != 0)) +#endif + +#if (LIBCFG_CKCU_USB_PLL) +/* Definitions of USBPLL frequency */ +#if (LIBCFG_CKCU_USB_PLL_96M) +#define CKCU_USBPLL_4M_96M ((24UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_8M_96M ((12UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_12M_96M (( 8UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_16M_96M (( 6UL << 7) | (0UL << 5)) +#else +#define CKCU_USBPLL_4M_48M ((12UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_8M_48M (( 6UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_12M_48M (( 4UL << 7) | (0UL << 5)) +#define CKCU_USBPLL_16M_48M (( 3UL << 7) | (0UL << 5)) +#endif + +#define IS_USBPLL_CFG(CFG) (((CFG & 0xFFFFF81F) == 0x0) && (CFG != 0)) +#endif + + + + +/* Definitions of MCU debug control */ +#define CKCU_DBG_SLEEP (1UL) +#define CKCU_DBG_DEEPSLEEP1 (1UL << 1) +#define CKCU_DBG_POWERDOWN (1UL << 2) +#define CKCU_DBG_WDT_HALT (1UL << 3) + +#if (LIBCFG_MCTM0) +#define CKCU_DBG_MCTM0_HALT (1UL << 4) +#endif + +#if (!LIBCFG_NO_GPTM0) +#define CKCU_DBG_GPTM0_HALT (1UL << 6) +#endif + +#if (LIBCFG_GPTM1) +#define CKCU_DBG_GPTM1_HALT (1UL << 7) +#endif + +#if (!LIBCFG_NO_USART0) +#define CKCU_DBG_USART0_HALT (1UL << 8) +#endif + +#if (LIBCFG_USART1) +#define CKCU_DBG_USART1_HALT (1UL << 9) +#endif + +#define CKCU_DBG_SPI0_HALT (1UL << 10) + +#if (LIBCFG_SPI1) +#define CKCU_DBG_SPI1_HALT (1UL << 11) +#endif + +#if defined(USE_HT32F0006) || defined(USE_HT32F61244_45) +#define CKCU_DBG_QSPI_HALT (1UL << 11) +#endif + +#define CKCU_DBG_I2C0_HALT (1UL << 12) + +#if (LIBCFG_I2C1) +#define CKCU_DBG_I2C1_HALT (1UL << 13) +#endif + +#define CKCU_DBG_DEEPSLEEP2 (1UL << 14) + +#if (LIBCFG_SCI0) +#define CKCU_DBG_SCI0_HALT (1UL << 15) +#endif + +#define CKCU_DBG_BFTM0_HALT (1UL << 16) + +#if (LIBCFG_BFTM1) +#define CKCU_DBG_BFTM1_HALT (1UL << 17) +#endif + +#define CKCU_DBG_UART0_HALT (1UL << 18) + +#if (LIBCFG_UART1) +#define CKCU_DBG_UART1_HALT (1UL << 19) +#endif + +#if (LIBCFG_SCI1) +#define CKCU_DBG_SCI1_HALT (1UL << 21) +#endif + +#if (LIBCFG_SCTM0) +#define CKCU_DBG_SCTM0_HALT (1UL << 22) +#endif + +#if (LIBCFG_SCTM1) +#define CKCU_DBG_SCTM1_HALT (1UL << 23) +#endif + +#if (LIBCFG_SCTM2) +#define CKCU_DBG_SCTM2_HALT (1UL << 24) +#endif + +#if (LIBCFG_SCTM3) +#define CKCU_DBG_SCTM3_HALT (1UL << 25) +#endif + +#if (LIBCFG_CAN0) +#define CKCU_DBG_CAN0_HALT (1UL << 26) +#endif + +#if (LIBCFG_UART2) +#define CKCU_DBG_UART2_HALT (1UL << 26) +#endif + +#if (LIBCFG_UART3) +#define CKCU_DBG_UART3_HALT (1UL << 27) +#endif + +#if (LIBCFG_I2C2) +#define CKCU_DBG_I2C2_HALT (1UL << 28) +#endif + +#if (LIBCFG_PWM2) +#define CKCU_DBG_PWM2_HALT (1UL << 29) +#endif + +#if defined(USE_HT32F52357_67) +#define CKCU_DBG_QSPI_HALT (1UL << 29) +#endif + +#if (LIBCFG_PWM0) +#define CKCU_DBG_PWM0_HALT (1UL << 30) +#endif + +#if (LIBCFG_PWM1) +#define CKCU_DBG_PWM1_HALT (1UL << 31) +#endif + +#define IS_CKCU_DBG(MODE) (((MODE & ~(0xFFEFFFDF)) == 0) && (MODE != 0)) + +/* Definitions of AHB clock control */ +#define CKCU_AHBEN_SLEEP_FMC (1UL) +#define CKCU_AHBEN_SLEEP_SRAM (1UL << 2) +#define CKCU_AHBEN_SLEEP_BM (1UL << 5) +#define CKCU_AHBEN_SLEEP_APB0 (1UL << 6) + +#define IS_CKCU_SLEEP_AHB(PERIPH) (((PERIPH & 0xFFFFFF9A) == 0) && (PERIPH != 0)) + +/* Definitions of HSI Ready Counter Value */ +#if (LIBCFG_CKCU_HSIRDYCR) +#define IS_COUNTER_VALUE(VALUE) ((VALUE) < 0x20) +#endif +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Exported_Functions CKCU exported functions + * @{ + */ +void CKCU_DeInit(void); + +void CKCU_HSICmd(ControlStatus Cmd); +void CKCU_HSECmd(ControlStatus Cmd); +bool CKCU_IS_HSI_USED(CKCU_HSIST_TypeDef Target); +bool CKCU_IS_HSE_USED(CKCU_HSEST_TypeDef Target); +FlagStatus CKCU_GetClockReadyStatus(u32 CKCU_FLAG); +ErrStatus CKCU_WaitHSEReady(void); + +ErrStatus CKCU_SysClockConfig(CKCU_SW_TypeDef CLKSRC); +u32 CKCU_GetSysClockSource(void); + +void CKCU_PeripClockConfig(CKCU_PeripClockConfig_TypeDef Clock, ControlStatus Cmd); + +#if (LIBCFG_NO_PLL) +#else +void CKCU_PLLInit(CKCU_PLLInitTypeDef *PLL_InitStruct); +void CKCU_PLLCmd(ControlStatus Cmd); +bool CKCU_IS_PLL_USED(CKCU_PLLST_TypeDef Target); +#endif + +#if (LIBCFG_CKCU_USB_PLL) +void CKCU_USBPLLInit(CKCU_PLLInitTypeDef *USBPLL_InitStruct); +void CKCU_USBPLLCmd(ControlStatus Cmd); +void CKCU_USBClockConfig(CKCU_USBSRC_TypeDef USBSRC); +#endif + +#if (LIBCFG_CKCU_LCD_SRC) +void CKCU_LCDClockConfig(CKCU_LCDSRC_TypeDef LCDSRC); +#endif + +#if (LIBCFG_CKCU_MCTM_SRC) +void CKCU_MCTMClockConfig(CKCU_MCTMSRC_TypeDef CKCU_MCTMSRC_x); +#endif + +void CKCU_SleepClockConfig(u32 CKCU_CLK, ControlStatus Cmd); + +void CKCU_SetHCLKPrescaler(CKCU_SYSCLKDIV_TypeDef HCLKPRE); +void CKCU_SetCKREFPrescaler(CKCU_CKREFPRE_TypeDef CKREFPRE); +void CKCU_SetADCnPrescaler(CKCU_ADCPRE_ADCn_TypeDef CKCU_ADCPRE_ADCn, CKCU_ADCPRE_TypeDef CKCU_ADCPRE_DIVn); +#define CKCU_SetADCPrescaler(DIV) CKCU_SetADCnPrescaler(CKCU_ADCPRE_ADC0, DIV) + +#if (LIBCFG_MIDI) +void CKCU_SetMIDIPrescaler(CKCU_MIDIPRE_TypeDef MIDIPRE); +#endif + +#if (!LIBCFG_CKCU_NO_APB_PRESCALER) +void CKCU_SetPeripPrescaler(CKCU_PeripPrescaler_TypeDef Perip, CKCU_APBCLKPRE_TypeDef PCLKPRE); +#endif + +void CKCU_GetClocksFrequency(CKCU_ClocksTypeDef* CKCU_Clk); +u32 CKCU_GetPLLFrequency(void); +u32 CKCU_GetPeripFrequency(CKCU_PeripPrescaler_TypeDef Perip); + +void CKCU_CKMCmd(ControlStatus Cmd); +void CKCU_PSRCWKUPCmd(ControlStatus Cmd); + +#if (!LIBCFG_CKCU_NO_LPCR) +void CKCU_BKISOCmd(ControlStatus Cmd); +#endif + +void CKCU_CKOUTConfig(CKCU_CKOUTInitTypeDef *CKOUTInit); +void CKCU_MCUDBGConfig(u32 CKCU_DBGx, ControlStatus Cmd); + +void CKCU_IntConfig(u32 CKCU_INT, ControlStatus Cmd); +FlagStatus CKCU_GetIntStatus(u32 CKCU_INT); +void CKCU_ClearIntFlag(u32 CKCU_INT); + +#if (((LIBCFG_LSE) || (LIBCFG_USBD)) && (!LIBCFG_CKCU_NO_AUTO_TRIM)) +#if (LIBCFG_CKCU_ATM_V01) +void CKCU_ATCInit(CKCU_ATCInitTypeDef* ATC_InitStruct); +#endif +void CKCU_HSIAutoTrimClkConfig(CKCU_ATC_TypeDef CLKSRC); +void CKCU_HSIAutoTrimCmd(ControlStatus Cmd); +bool CKCU_HSIAutoTrimIsReady(void); +#endif + +#if (LIBCFG_CKCU_HSIRDYCR) +void CKCU_Set_HSIReadyCounter(u8 value); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_cmp.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_cmp.h new file mode 100644 index 00000000000..5869bcd21c2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_cmp.h @@ -0,0 +1,362 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_cmp.h + * @version $Rev:: 7319 $ + * @date $Date:: 2023-10-28 #$ + * @brief The header file of the CMP library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_CMP_H +#define __HT32F5XXXX_CMP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CMP + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Types CMP exported types + * @{ + */ + +typedef struct +{ + u32 CMP_Wakeup; + u32 CMP_OutputSelection; + u32 CMP_ScalerSource; + u32 CMP_ScalerOutputBuf; + u32 CMP_ScalerEnable; + u32 CMP_CoutSync; + u32 CMP_OutputPol; + #if (LIBCFG_CMP_65x_VER) + u32 CMP_InputSelection; + #endif + u32 CMP_InvInputSelection; + u32 CMP_Hysteresis; + u32 CMP_Speed; +} CMP_InitTypeDef; + +#if (LIBCFG_CMP_CO) +typedef enum +{ + CMP_SYNCOUT_CMPnO = 0, + CMP_SYNCOUT_MCTM_CH0O = 1, + CMP_SYNCOUT_MCTM_CH0NO = 2, + CMP_SYNCOUT_MCTM_CH1O = 3, + CMP_SYNCOUT_MCTM_CH1NO = 4, + CMP_SYNCOUT_MCTM_CH2O = 5, + CMP_SYNCOUT_MCTM_CH2NO = 6, + CMP_SYNCOUT_MCTM_CH3O = 7, + CMP_SYNCOUT_MCTM_CH3OB = 8, // Inverted of MCTM_CH3O +} CMP_SYNCOUT_Enum; +#endif + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Constants CMP exported constants + * @{ + */ + +/* Definitions of CMP Protection Key */ +#define CMP_PROTECT_KEY ((u32)0x9C3A0000) + + +/* Definitions of CMP Output Status */ +#define CMP_OUTPUT_HIGH ((u32)0x00008000) +#define CMP_OUTPUT_LOW ((u32)0x00000000) + + +/* Definitions of CMP Wakeup Control Bit */ +#define CMP_WUP_ENABLE ((u32)0x00004000) +#define CMP_WUP_DISABLE ((u32)0x00000000) + +#define IS_CMP_Wakeup_Set(x) ((x == CMP_WUP_ENABLE) || (x == CMP_WUP_DISABLE)) + + +/* Definitions of CMP Output Selection for IP Trigger Source */ +#if (LIBCFG_CMP_65x_VER) +#define CMP_TRIG_NONE ((u32)0x0 << 11) +#define CMP_TRIG_GPTM_CH0 ((u32)0x1 << 11) // CMP0 +#define CMP_TRIG_GPTM_CH1 ((u32)0x1 << 11) // CMP1 + +#define IS_CMP_OutputSelection2(x) (0) +#if (LIBCFG_CMP2) +#define CMP_TRIG_GPTM_CH2 ((u32)0x1 << 11) // CMP2 +#undef IS_CMP_OutputSelection2 +#define IS_CMP_OutputSelection2(x) (x == CMP_TRIG_GPTM_CH2) +#endif + +#define CMP_TRIG_GPTM_CH3 ((u32)0x2 << 11) +#define CMP_TRIG_SCTM ((u32)0x3 << 11) +#define CMP_TRIG_MCTM_CH3 ((u32)0x4 << 11) +#define CMP_TRIG_MCTM_BK0 ((u32)0x5 << 11) +#define CMP_TRIG_MCTM_BK1 ((u32)0x6 << 11) +#define CMP_TRIG_ADC ((u32)0x7 << 11) + +#define IS_CMP_OutputSelection(x) ((x == CMP_TRIG_NONE) || \ + (x == CMP_TRIG_GPTM_CH0) || \ + (x == CMP_TRIG_GPTM_CH1) || \ + IS_CMP_OutputSelection2(x) || \ + (x == CMP_TRIG_GPTM_CH3) || \ + (x == CMP_TRIG_SCTM) || \ + (x == CMP_TRIG_MCTM_CH3) || \ + (x == CMP_TRIG_MCTM_BK0) || \ + (x == CMP_TRIG_MCTM_BK1) || \ + (x == CMP_TRIG_ADC)) +#else +#define CMP_TRIG_NONE ((u32)0x0 << 11) +#define CMP_TRIG_GPTM_CH3 ((u32)0x1 << 11) +#if (LIBCFG_MCTM0) +#define CMP_TRIG_MCTM_CH3 ((u32)0x2 << 11) +#define CMP_TRIG_MCTM_BK1 ((u32)0x3 << 11) +#endif +#define CMP_TRIG_ADC ((u32)0x4 << 11) + +#if (LIBCFG_MCTM0) +#define IS_CMP_OutSelMCTM(x) ((x == CMP_TRIG_MCTM_CH3) || (x == CMP_TRIG_MCTM_BK1)) +#else +#define IS_CMP_OutSelMCTM(x) (0) +#endif + +#define IS_CMP_OutputSelection(x) ((x == CMP_TRIG_NONE) || \ + (x == CMP_TRIG_GPTM_CH3) || \ + IS_CMP_OutSelMCTM(x) || \ + (x == CMP_TRIG_ADC)) +#endif + +/* Definitions of CMP Scaler Source Selection */ +#define CMP_SCALER_SRC_VDDA ((u32)0x00000000) + +#if (LIBCFG_CMP_NOSCALER_SRC) +#define IS_CMP_ScalerSource(x) ((x == CMP_SCALER_SRC_VDDA)) +#else +#define CMP_SCALER_SRC_VREF ((u32)0x00000400) +#define IS_CMP_ScalerSource(x) ((x == CMP_SCALER_SRC_VDDA) || (x == CMP_SCALER_SRC_VREF)) +#endif + + +/* Definitions of CMP Scaler Output Enable Bit */ +#define CMP_SCALER_OBUF_DISABLE ((u32)0x00000000) +#define CMP_SCALER_OBUF_ENABLE ((u32)0x00000200) + +#define IS_CMP_ScalerOutputBuf(x) ((x == CMP_SCALER_OBUF_DISABLE) || (x == CMP_SCALER_OBUF_ENABLE)) + + +/* Definitions of CMP Scaler Enable Bit */ +#define CMP_SCALER_DISABLE ((u32)0x00000000) +#define CMP_SCALER_ENABLE ((u32)0x00000100) + +#define IS_CMP_ScalerEnable(x) ((x == CMP_SCALER_DISABLE) || (x == CMP_SCALER_ENABLE)) + + +/* Definitions of CMP Sync Output Enable bit */ +#define CMP_ASYNC_OUTPUT ((u32)0x00000000) +#define CMP_SYNC_OUTPUT ((u32)0x00000080) + +#define IS_CMP_CoutSynchronized(x) ((x == CMP_ASYNC_OUTPUT) || (x == CMP_SYNC_OUTPUT)) + + +/* Definitions of CMP Output Polarity Selection */ +#define CMP_NONINV_OUTPUT ((u32)0x00000000) +#define CMP_INV_OUTPUT ((u32)0x00000040) + +#define IS_CMP_OutputPol_Set(x) ((x == CMP_NONINV_OUTPUT) || (x == CMP_INV_OUTPUT)) + + +/* Definitions of CMP Inverted Input Source Selection */ +#if (LIBCFG_CMP_65x_VER) +#if (LIBCFG_CMP_POS_INPUT_SEL_V2) +#define CMP_INPUT_CMPnP ((u32)0x00000000) +#define CMP_INPUT_CMPnP0 ((u32)0x00000000) +#define CMP_INPUT_CMPnP1 ((u32)0x00000001) +#define CMP_INPUT_CMPnP2 ((u32)0x00000002) +#define CMP_INPUT_OPA0O ((u32)0x00000003) + +#define IS_CMP_InputSelection(x) ((x == CMP_INPUT_CMPnP) || \ + (x == CMP_INPUT_CMPnP0) || \ + (x == CMP_INPUT_CMPnP1) || \ + (x == CMP_INPUT_CMPnP2) || \ + (x == CMP_INPUT_OPA0O)) +#else +#define CMP_INPUT_CMPnP ((u32)0x00000000) +#define CMP_INPUT_OPA0O ((u32)0x00000001) +#define CMP_INPUT_OPA1O ((u32)0x00000002) + +#define IS_CMP_InputSelection(x) ((x == CMP_INPUT_CMPnP) || (x == CMP_INPUT_OPA0O) || (x == CMP_INPUT_OPA1O)) +#endif +#endif + + +/* Definitions of CMP Inverted Input Source Selection */ +#define CMP_EXTERNAL_CN_IN ((u32)0x00000000) +#define CMP_SCALER_CN_IN ((u32)0x00000010) + +#define IS_CMP_InvInSel2(x) (0) + +#if (LIBCFG_CMP_IVREF_CN_IN) +#define CMP_IVREF_CN_IN ((u32)0x00000020) +#undef IS_CMP_InvInSel2 +#define IS_CMP_InvInSel2(x) ((x == CMP_IVREF_CN_IN)) +#endif + +#if defined(USE_HT32F65230_40) +#define CMP_CMP0N_CN_IN ((u32)0x00000020) +#undef IS_CMP_InvInSel2 +#define IS_CMP_InvInSel2(x) ((x == CMP_CMP0N_CN_IN)) +#endif + +#if defined(USE_HT32F65232) +#define CMP0_CMP1N_CN_IN ((u32)0x00000020) +#define CMP1_CMP0N_CN_IN ((u32)0x00000020) +#undef IS_CMP_InvInSel2 +#define IS_CMP_InvInSel2(x) ((x == CMP0_CMP1N_CN_IN)) +#endif + +#define IS_CMP_InvInputSelection(x) ((x == CMP_EXTERNAL_CN_IN) || (x == CMP_SCALER_CN_IN) || IS_CMP_InvInSel2(x)) + + +/* Definitions of CMP Hysteresis Level Selection */ +#define CMP_NO_HYSTERESIS ((u32)0x00000000) +#define CMP_LOW_HYSTERESIS ((u32)0x00000004) +#define CMP_MID_HYSTERESIS ((u32)0x00000008) +#define CMP_HIGH_HYSTERESIS ((u32)0x0000000C) + +#define IS_CMP_Hysteresis_Set(x) ((x == CMP_NO_HYSTERESIS) || (x == CMP_LOW_HYSTERESIS) || (x == CMP_MID_HYSTERESIS) || \ + (x == CMP_HIGH_HYSTERESIS)) + +/* Definitions of CMP Speed Mode Selection */ +#define CMP_HIGH_SPEED ((u32)0x00000002) +#define CMP_LOW_SPEED ((u32)0x00000000) + +#define IS_CMP_Speed_Set(x) ((x == CMP_HIGH_SPEED) || (x == CMP_LOW_SPEED)) + + +/* Definitions of CMP Enable bit */ +#define CMP_ENABLE ((u32)0x00000001) + + +/* Definitions of CMP Output Edge Interrupt Enable bit */ +#define CMP_INT_RE ((u32)0x00000002) +#define CMP_INT_FE ((u32)0x00000001) + +/* Check the CMP Interrupt Parameter */ +#define IS_CMP_INT(x) ((x & 0xFFFFFF00) != 0x0) + + +/* Definitions of CMP Output Edge Detection Enable bit */ +#define CMP_RE_Detect ((u32)0x00000200) +#define CMP_FE_Detect ((u32)0x00000100) + +#define IS_CMP_EdgeDetect(x) ((x == CMP_RE_Detect) || (x == CMP_FE_Detect)) + + +/* Definitions of CMP Output Edge Flag */ +#define CMP_FLAG_RE ((u32)0x00000002) +#define CMP_FLAG_FE ((u32)0x00000001) + +/* Check the CMP flag Parameter */ +#define IS_CMP_FLAG(x) ((x & 0xFFFFFF00) != 0x0) + + +/* Check the CMPx Parameter */ +#if (LIBCFG_CMP2) +#define IS_CMP2(x) (x == HT_CMP2) +#else +#define IS_CMP2(x) (0) +#endif +#define IS_CMP(x) ((x == HT_CMP0) || (x == HT_CMP1) || IS_CMP2(x)) + + +/* Check the Scaler Value */ +#if (LIBCFG_CMP_SCALER_8BIT) +#define IS_SCALER_VALUE(x) (x <= 0xFF) +#else +#define IS_SCALER_VALUE(x) (x <= 0x3F) +#endif + +#if (LIBCFG_CMP_CO) +#define IS_CMP_SYNC_SOURCE(x) ((x == CMP_SYNCOUT_CMPnO) || \ + (x == CMP_SYNCOUT_MCTM_CH0O) || \ + (x == CMP_SYNCOUT_MCTM_CH0NO) || \ + (x == CMP_SYNCOUT_MCTM_CH1O) || \ + (x == CMP_SYNCOUT_MCTM_CH1NO) || \ + (x == CMP_SYNCOUT_MCTM_CH2O) || \ + (x == CMP_SYNCOUT_MCTM_CH2NO) || \ + (x == CMP_SYNCOUT_MCTM_CH3O) || \ + (x == CMP_SYNCOUT_MCTM_CH3OB)) +#endif + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Functions CMP exported functions + * @{ + */ +void CMP_DeInit(HT_CMP_TypeDef* HT_CMPn); +void CMP_UnprotectConfig(HT_CMP_TypeDef* HT_CMPn); +void CMP_Init(HT_CMP_TypeDef* HT_CMPn, CMP_InitTypeDef* CMP_InitStruct); +void CMP_StructInit(CMP_InitTypeDef* CMP_InitStruct); +void CMP_Cmd(HT_CMP_TypeDef* HT_CMPn, ControlStatus NewState); +void CMP_IntConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_INT_x, ControlStatus NewState); +void CMP_EdgeDetectConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_xE_Detect, ControlStatus NewState); +FlagStatus CMP_GetFlagStatus(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x); +void CMP_ClearFlag(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x); +FlagStatus CMP_GetOutputStatus(HT_CMP_TypeDef* HT_CMPn); +void CMP_SetScalerValue(HT_CMP_TypeDef* HT_CMPn, u8 Scaler_Value); +#if (LIBCFG_CMP_CO) +void CMP_Output_SyncSource_Select(HT_CMP_TypeDef* HT_CMPn, CMP_SYNCOUT_Enum CMP_SYNCOUT_x); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_crc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_crc.h new file mode 100644 index 00000000000..d6d763777ca --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_crc.h @@ -0,0 +1,124 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_crc.h + * @version $Rev:: 5031 $ + * @date $Date:: 2020-11-03 #$ + * @brief The header file of the CRC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_CRC_H +#define __HT32F5XXXX_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Types CRC exported types + * @{ + */ + +/* Definition of CRC Init Structure */ +typedef enum +{ + CRC_CCITT_POLY = 0, + CRC_16_POLY = 1, + CRC_32_POLY = 2, + CRC_USER_DEFINE = 0xF +} CRC_Mode; + +typedef struct +{ + CRC_Mode Mode; + u32 uSeed; + u32 uCR; +} CRC_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Constants CRC exported constants + * @{ + */ +#define IS_CRC_POLY(POLY) ((POLY == CRC_CCITT_POLY) || \ + (POLY == CRC_16_POLY) || \ + (POLY == CRC_32_POLY) || \ + (POLY == CRC_USER_DEFINE)) + +#define CRC_NORMAL_WR (0) +#define CRC_BIT_RVS_WR (1UL << 2) +#define CRC_BYTE_RVS_WR (1UL << 3) +#define CRC_CMPL_WR (1UL << 4) + +#define CRC_NORMAL_SUM (0) +#define CRC_BIT_RVS_SUM (1UL << 5) +#define CRC_BYTE_RVS_SUM (1UL << 6) +#define CRC_CMPL_SUM (1UL << 7) + +#define IS_CRC_MOD(MOD) ((MOD & 0xFFFFFF00) == 0) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC exported functions + * @{ + */ +void CRC_DeInit(HT_CRC_TypeDef* HT_CRCn); +void CRC_Init(HT_CRC_TypeDef* HT_CRCn, CRC_InitTypeDef* CRC_InitStruct); +u32 CRC_Process(HT_CRC_TypeDef* HT_CRCn, u8 *buffer, u32 length); + +u16 CRC_CCITT(u16 seed, u8 *buffer, u32 length); +u16 CRC_16(u16 seed, u8 *buffer, u32 length); +u32 CRC_32(u32 seed, u8 *buffer, u32 length); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_dac.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_dac.h new file mode 100644 index 00000000000..50b56ac79c7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_dac.h @@ -0,0 +1,130 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_dac.h + * @version $Rev:: 7081 $ + * @date $Date:: 2023-08-01 #$ + * @brief The header file of the DAC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_DAC_H +#define __HT32F5XXXX_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup DAC_Exported_Types DAC exported types + * @{ + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup DAC_Exported_Constants DAC exported constants + * @{ + */ +#define ASYNC_MODE (0x00000000) +#define SYNC_MODE (0x00000001) + +#if (LIBCFG_DAC1) +#define IS_DAC(DAC) (((DAC) == HT_DAC0) || ((DAC) == HT_DAC1)) +#else +#define IS_DAC(DAC) ((DAC) == HT_DAC0) +#endif + + +#define IS_DAC_CONVERSION_MODE(MODE) (((MODE) == ASYNC_MODE) || ((MODE) == SYNC_MODE)) + + +#define DAC_CH0 (0) +#define DAC_CH1 (1) + +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CH0) || ((CHANNEL) == DAC_CH1)) + + + +#define DAC_REFERENCE_VDDA (0) +#define DAC_REFERENCE_VREF (1UL << 14) + +#define IS_DAC_REFERENCE(REF) (((REF) == DAC_REFERENCE_VDDA) || ((REF) == DAC_REFERENCE_VREF)) + + +#define DAC_RESOLUTION_12BIT (0) +#define DAC_RESOLUTION_8BIT (1UL << 2) + +#define IS_DAC_RESOLUTION(RES) (((RES) == DAC_RESOLUTION_8BIT) || ((RES) == DAC_RESOLUTION_12BIT)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup DAC_Exported_Functions DAC exported functions + * @{ + */ +void DAC_DeInit(HT_DAC_TypeDef* HT_DACn); + +void DAC_ModeConfig(HT_DAC_TypeDef* HT_DACn, u8 ModeSel); + +void DAC_ReferenceConfig(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 RefSel); +void DAC_ResolutionConfig(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 ResoSel); + +void DAC_OutBufCmd(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, ControlStatus NewState); +void DAC_Cmd(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, ControlStatus NewState); + +void DAC_SetData(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 Data); +u16 DAC_GetOutData(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch); + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_dac_dual16.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_dac_dual16.h new file mode 100644 index 00000000000..306cbb125f7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_dac_dual16.h @@ -0,0 +1,92 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_dac_dual16.h + * @version $Rev:: 4282 $ + * @date $Date:: 2019-10-18 #$ + * @brief The header file of the DAC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_DAC_DUAL16_DAC_H +#define __HT32F5XXXX_DAC_DUAL16_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup DAC_DUAL16 + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup DAC_Exported_Types DAC exported types + * @{ + */ +typedef enum +{ + DAC_CH_R = 0, + DAC_CH_L = 1, +} DAC_Dual16_Ch; + +typedef enum +{ + DATA_FROM_UC = 0, + DATA_FROM_MIDI = 1, +} DAC_Dual16_Source; +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup DAC_DUAL16_Exported_Functions DAC exported functions + * @{ + */ +void DACD16_DeInit(void); +void DACD16_DataSourceConfig(HT_DAC_DUAL16_TypeDef* DACx, DAC_Dual16_Ch DAC_CH_x, DAC_Dual16_Source DATA_FROM_x); +void DACD16_SetChannelData(HT_DAC_DUAL16_TypeDef* DACx, DAC_Dual16_Ch DAC_CH_x, u16 Data); +void DACD16_SoftwareStartConvCmd(HT_DAC_DUAL16_TypeDef* DACx, DAC_Dual16_Ch DAC_CH_x); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_div.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_div.h new file mode 100644 index 00000000000..9cf23f9c315 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_div.h @@ -0,0 +1,113 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_div.h + * @version $Rev:: 4617 $ + * @date $Date:: 2020-02-26 #$ + * @brief The header file of the DIV library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_DIV_H +#define __HT32F5XXXX_DIV_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup DIV + * @{ + */ + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup DIV_Settings DIV settings + * @{ + */ +#define DIV_ENABLE_DIVIDE_BY_ZERO_CHECK (0) +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup DIV_Exported_Types DIV exported types + * @{ + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup DIV_Exported_Constants DIV exported constants + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup DIV_Exported_Functions DIV exported functions + * @{ + */ +void DIV_DeInit(void); +s32 DIV_Div32(s32 dividend, s32 divisor); +s32 DIV_Mod(s32 dividend, s32 divisor); +bool DIV_IsDivByZero(void); + +u32 DIV_uDiv32(u32 dividend, u32 divisor); +u32 DIV_uGetLastRemainder(void); + +/*********************************************************************************************************//** + * @brief Retuen the remainder of last dividend/divisor calculatation. + * @retval The remainder of dividend/divisor + ************************************************************************************************************/ +__STATIC_INLINE s32 DIV_GetLastRemainder(void) +{ + return (HT_DIV->RMR); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ebi.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ebi.h new file mode 100644 index 00000000000..98e6153146a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ebi.h @@ -0,0 +1,183 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_ebi.h + * @version $Rev:: 2772 $ + * @date $Date:: 2018-05-15 #$ + * @brief The header file of the EBI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_EBI_H +#define __HT32F5XXXX_EBI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup EBI + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Types EBI exported types + * @{ + */ +typedef struct +{ + u32 EBI_Bank; + u32 EBI_Mode; + u32 EBI_IdleCycle; + u32 EBI_ChipSelectPolarity; + u32 EBI_AddressLatchPolarity; + u32 EBI_WriteEnablePolarity; + u32 EBI_ReadEnablePolarity; + u32 EBI_IdleCycleTime; + u32 EBI_AddressSetupTime; + u32 EBI_AddressHoldTime; + u32 EBI_WriteSetupTime; + u32 EBI_WriteStrobeTime; + u32 EBI_WriteHoldTime; + u32 EBI_ReadSetupTime; + u32 EBI_ReadStrobeTime; + u32 EBI_ReadHoldTime; +} EBI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Constants EBI exported constants + * @{ + */ +#define EBI_BANK_0 ((u32)0x00000000) +#define EBI_BANK_1 ((u32)0x00000001) +#define EBI_BANK_2 ((u32)0x00000002) +#define EBI_BANK_3 ((u32)0x00000003) + +#define IS_EBI_BANK(BANK) ((BANK == EBI_BANK_0) || \ + (BANK == EBI_BANK_1) || \ + (BANK == EBI_BANK_2) || \ + (BANK == EBI_BANK_3)) + + +#define EBI_MODE_D8A8 ((u32)0x00000000) +#define EBI_MODE_D16A16ALE ((u32)0x00000001) +#define EBI_MODE_D8A24ALE ((u32)0x00000002) +#define EBI_MODE_D16 ((u32)0x00000003) + +#define IS_EBI_MODE(MODE) ((MODE == EBI_MODE_D8A8) || \ + (MODE == EBI_MODE_D16A16ALE) || \ + (MODE == EBI_MODE_D8A24ALE) || \ + (MODE == EBI_MODE_D16)) + + +#define EBI_IDLECYCLE_ENABLE ((u32)0x00000000) +#define EBI_IDLECYCLE_DISABLE ((u32)0x00001000) + +#define IS_EBI_IDLECYCLE(IDLECYCLE) ((IDLECYCLE == EBI_IDLECYCLE_ENABLE) || \ + (IDLECYCLE == EBI_IDLECYCLE_DISABLE)) + + +#define EBI_CHIPSELECTPOLARITY_LOW ((u32)0x00000000) +#define EBI_CHIPSELECTPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_CS_POLARITY(POLARITY) ((POLARITY == EBI_CHIPSELECTPOLARITY_LOW) || \ + (POLARITY == EBI_CHIPSELECTPOLARITY_HIGH)) + + +#define EBI_ADDRESSLATCHPOLARITY_LOW ((u32)0x00000000) +#define EBI_ADDRESSLATCHPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_ALE_POLARITY(POLARITY) ((POLARITY == EBI_ADDRESSLATCHPOLARITY_LOW) || \ + (POLARITY == EBI_ADDRESSLATCHPOLARITY_HIGH)) + + +#define EBI_WRITEENABLEPOLARITY_LOW ((u32)0x00000000) +#define EBI_WRITEENABLEPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_WE_POLARITY(POLARITY) ((POLARITY == EBI_WRITEENABLEPOLARITY_LOW) || \ + (POLARITY == EBI_WRITEENABLEPOLARITY_HIGH)) + + +#define EBI_READENABLEPOLARITY_LOW ((u32)0x00000000) +#define EBI_READENABLEPOLARITY_HIGH ((u32)0x00000001) + +#define IS_EBI_RE_POLARITY(POLARITY) ((POLARITY == EBI_READENABLEPOLARITY_LOW) || \ + (POLARITY == EBI_READENABLEPOLARITY_HIGH)) + + +#define IS_EBI_IDLE_CYCLE_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_ADDRESS_SETUP_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_ADDRESS_HOLD_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_WRITE_SETUP_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_WRITE_STROBE_TIME(TIME) (TIME < 0x40) + +#define IS_EBI_WRITE_HOLD_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_READ_SETUP_TIME(TIME) (TIME < 0x10) + +#define IS_EBI_READ_STROBE_TIME(TIME) (TIME < 0x40) + +#define IS_EBI_READ_HOLD_TIME(TIME) (TIME < 0x10) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Functions EBI exported functions + * @{ + */ +void EBI_DeInit(void); +void EBI_Init(EBI_InitTypeDef* EBI_InitStruct); +void EBI_StructInit(EBI_InitTypeDef* EBI_InitStruct); +void EBI_Cmd(u32 EBI_Bank, ControlStatus NewState); +FlagStatus EBI_GetBusyStatus(void); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_exti.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_exti.h new file mode 100644 index 00000000000..bdda2d24427 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_exti.h @@ -0,0 +1,263 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_exti.h + * @version $Rev:: 6496 $ + * @date $Date:: 2022-11-28 #$ + * @brief The header file of the EXTI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_EXTI_H +#define __HT32F5XXXX_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macro EXTI exported macros + * @{ + */ +/*********************************************************************************************************//** + * @brief Convert the pin number of GPIO to the channel of EXTI. + * @param n: can be 0, 1 to 15 to select the pin number of GPIO. + ************************************************************************************************************/ +#if (LIBCFG_EXTI_8CH) + #define GPIO2EXTI(n) ((n >= 8) ? (n - 8) : n) +#else + #define GPIO2EXTI(n) (n) +#endif + +#define EXTI_GetIRQn(ch) gEXTIn_IRQn[ch] +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Types EXTI exported types + * @{ + */ + +/* Definitions of EXTI interrupt line */ +typedef enum +{ + EXTI_CHANNEL_0 = 0, + EXTI_CHANNEL_1, + EXTI_CHANNEL_2, + EXTI_CHANNEL_3, + EXTI_CHANNEL_4, + EXTI_CHANNEL_5, + EXTI_CHANNEL_6, + EXTI_CHANNEL_7, +#if (!LIBCFG_EXTI_8CH) + EXTI_CHANNEL_8, + EXTI_CHANNEL_9, + EXTI_CHANNEL_10, + EXTI_CHANNEL_11, + EXTI_CHANNEL_12, + EXTI_CHANNEL_13, + EXTI_CHANNEL_14, + EXTI_CHANNEL_15, +#endif +} EXTI_Channel_TypeDef; + +#if (LIBCFG_EXTI_8CH) +#define IS_CHANNEL_8(x) (0) +#define IS_CHANNEL_9(x) (0) +#define IS_CHANNEL_10(x) (0) +#define IS_CHANNEL_11(x) (0) +#define IS_CHANNEL_12(x) (0) +#define IS_CHANNEL_13(x) (0) +#define IS_CHANNEL_14(x) (0) +#define IS_CHANNEL_15(x) (0) +#else +#define IS_CHANNEL_8(x) (x == EXTI_CHANNEL_8) +#define IS_CHANNEL_9(x) (x == EXTI_CHANNEL_9) +#define IS_CHANNEL_10(x) (x == EXTI_CHANNEL_10) +#define IS_CHANNEL_11(x) (x == EXTI_CHANNEL_11) +#define IS_CHANNEL_12(x) (x == EXTI_CHANNEL_12) +#define IS_CHANNEL_13(x) (x == EXTI_CHANNEL_13) +#define IS_CHANNEL_14(x) (x == EXTI_CHANNEL_14) +#define IS_CHANNEL_15(x) (x == EXTI_CHANNEL_15) +#endif + + +#define IS_EXTI_CHANNEL(CHANNEL) ((CHANNEL == EXTI_CHANNEL_0) || \ + (CHANNEL == EXTI_CHANNEL_1) || \ + (CHANNEL == EXTI_CHANNEL_2) || \ + (CHANNEL == EXTI_CHANNEL_3) || \ + (CHANNEL == EXTI_CHANNEL_4) || \ + (CHANNEL == EXTI_CHANNEL_5) || \ + (CHANNEL == EXTI_CHANNEL_6) || \ + (CHANNEL == EXTI_CHANNEL_7) || \ + IS_CHANNEL_8(CHANNEL) || \ + IS_CHANNEL_9(CHANNEL) || \ + IS_CHANNEL_10(CHANNEL) || \ + IS_CHANNEL_11(CHANNEL) || \ + IS_CHANNEL_12(CHANNEL) || \ + IS_CHANNEL_13(CHANNEL) || \ + IS_CHANNEL_14(CHANNEL) || \ + IS_CHANNEL_15(CHANNEL)) + + +/* Definitions of EXTI init structure */ +typedef enum +{ + EXTI_LOW_LEVEL = 0x0, + EXTI_HIGH_LEVEL = 0x1, + EXTI_NEGATIVE_EDGE = 0x2, + EXTI_POSITIVE_EDGE = 0x3, + EXTI_BOTH_EDGE = 0x4 +} EXTI_Interrupt_TypeDef; + +#define IS_EXTI_INT_TYPE(TYPE) ((TYPE == EXTI_LOW_LEVEL) || \ + (TYPE == EXTI_HIGH_LEVEL) || \ + (TYPE == EXTI_NEGATIVE_EDGE) || \ + (TYPE == EXTI_POSITIVE_EDGE) || \ + (TYPE == EXTI_BOTH_EDGE)) + +typedef enum +{ + EXTI_DEBOUNCE_DISABLE = 0x0, + EXTI_DEBOUNCE_ENABLE = 0x1 +} EXTI_Deb_TypeDef; + +#define IS_EXTI_DEBOUNCE_TYPE(TYPE) ((TYPE == EXTI_DEBOUNCE_DISABLE) || \ + (TYPE == EXTI_DEBOUNCE_ENABLE)) + +#if (LIBCFG_EXTI_DEBCNTPRE) +typedef enum +{ + EXTI_DBCNTPRE_DIV1 = 0, + EXTI_DBCNTPRE_DIV2, + EXTI_DBCNTPRE_DIV4, + EXTI_DBCNTPRE_DIV8, + EXTI_DBCNTPRE_DIV16, + EXTI_DBCNTPRE_DIV32, + EXTI_DBCNTPRE_DIV64, + EXTI_DBCNTPRE_DIV128, +} EXTI_DebCntPre_TypeDef; + +#define IS_EXTI_DEBOUNCE_COUNTER_PRESCALER(TYPE) ((TYPE == EXTI_DBCNTPRE_DIV1) || \ + (TYPE == EXTI_DBCNTPRE_DIV2) || \ + (TYPE == EXTI_DBCNTPRE_DIV4) || \ + (TYPE == EXTI_DBCNTPRE_DIV8) || \ + (TYPE == EXTI_DBCNTPRE_DIV16) || \ + (TYPE == EXTI_DBCNTPRE_DIV32) || \ + (TYPE == EXTI_DBCNTPRE_DIV64) || \ + (TYPE == EXTI_DBCNTPRE_DIV128)) +#endif + +typedef struct +{ + u32 EXTI_Channel; + EXTI_Deb_TypeDef EXTI_Debounce; + #if (LIBCFG_EXTI_8BIT_DEBOUNCE_COUNTER) + u8 EXTI_DebounceCnt; + #else + u16 EXTI_DebounceCnt; + #endif + EXTI_Interrupt_TypeDef EXTI_IntType; +} EXTI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI exported constants + * @{ + */ + +/* Definitions of EXTI wake up polarity */ +#define EXTI_WAKEUP_HIGH_LEVEL ((u8)0x0) +#define EXTI_WAKEUP_LOW_LEVEL ((u8)0x1) + +#define IS_EXTI_WAKEUP_TYPE(TYPE) ((TYPE == EXTI_WAKEUP_HIGH_LEVEL) || \ + (TYPE == EXTI_WAKEUP_LOW_LEVEL)) + + +#define EXTI_EDGE_POSITIVE ((u8)0x0) +#define EXTI_EDGE_NEGATIVE ((u8)0x1) + +#define IS_EXTI_EDGE(EDGE) ((EDGE == EXTI_EDGE_POSITIVE) || \ + (EDGE == EXTI_EDGE_NEGATIVE)) + +#if (LIBCFG_EXTI_8BIT_DEBOUNCE_COUNTER) +#define IS_EXTI_DEBOUNCE_SIZE(SIZE) (SIZE <= 0xFF) +#else +#define IS_EXTI_DEBOUNCE_SIZE(SIZE) (SIZE <= 0xFFFF) +#endif + +extern const IRQn_Type gEXTIn_IRQn[16]; + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI exported functions + * @{ + */ +void EXTI_DeInit(u32 EXTI_Channel); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_IntConfig(u32 EXTI_Channel, ControlStatus NewState); +#if (LIBCFG_EXTI_DEBCNTPRE) +void EXTI_SetDebounceCounterPrescaler(EXTI_DebCntPre_TypeDef EXTI_DBCNTPRE_DIVn); +#endif +void EXTI_WakeupEventConfig(u32 EXTI_Channel, u8 EXTI_WakeUpType, ControlStatus NewState); +void EXTI_WakeupEventIntConfig(ControlStatus NewState); +void EXTI_ClearEdgeFlag(u32 EXTI_Channel); +void EXTI_ClearWakeupFlag(u32 EXTI_Channel); +FlagStatus EXTI_GetEdgeFlag(u32 EXTI_Channel); +FlagStatus EXTI_GetEdgeStatus(u32 EXTI_Channel, u32 EXTI_Edge); +FlagStatus EXTI_GetWakeupFlagStatus(u32 EXTI_Channel); +void EXTI_SWIntCmd(u32 EXTI_Channel, ControlStatus NewState); +FlagStatus EXTI_GetSWCmdStatus(u32 EXTI_Channel); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_flash.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_flash.h new file mode 100644 index 00000000000..0ee8ba77d71 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_flash.h @@ -0,0 +1,190 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_flash.h + * @version $Rev:: 5496 $ + * @date $Date:: 2021-07-19 #$ + * @brief The header file of the FLASH library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_FLASH_H +#define __HT32F5XXXX_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH exported types + * @{ + */ + +/** + * @brief Enumeration of FLASH return status. + */ +typedef enum +{ + FLASH_COMPLETE = 0, + FLASH_ERR_ADDR_OUT_OF_RANGE, + FLASH_ERR_WRITE_PROTECTED, + FLASH_TIME_OUT +} FLASH_State; + +/** + * @brief Enumeration of FLASH boot mode. + */ +typedef enum +{ + FLASH_BOOT_LOADER = 1, + FLASH_BOOT_MAIN = 2 +} FLASH_Vector; + +typedef struct +{ + u32 WriteProtect[4]; + u32 MainSecurity; + u32 OptionProtect; +} FLASH_OptionByte; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH exported constants + * @{ + */ + +/* Flash Information */ +#define FLASH_PAGE_SIZE (LIBCFG_FLASH_PAGESIZE) /* Flash page size */ + +#if (LIBCFG_FMC_PREFETCH) + +/* Flash Wait State */ +#define FLASH_WAITSTATE_0 (0x00000001) /* FLASH zero wait state */ +#define FLASH_WAITSTATE_1 (0x00000002) /* FLASH one wait state */ +#if (LIBCFG_FMC_WAIT_STATE_2) +#define FLASH_WAITSTATE_2 (0x00000003) /* FLASH two wait state */ +#endif + +#if (LIBCFG_FMC_WAIT_STATE_2) +#define FLASH_WAITSTATE_MAX (FLASH_WAITSTATE_2) +#else +#define FLASH_WAITSTATE_MAX (FLASH_WAITSTATE_1) +#endif + +#endif + +/* FLASH OISR Flags */ +#define FLASH_FLAG_ORFF (0x00000001) /* Operation Finished Flag */ +#define FLASH_FLAG_ITADF (0x00000002) /* Invalid Target Address Flag */ +#define FLASH_FLAG_OBEF (0x00000004) /* Option Byte Check Sum Error Flag */ +#define FLASH_FLAG_IOCMF (0x00000008) /* Invalid Operation Command Flag */ +#define FLASH_FLAG_OREF (0x00000010) /* Operation Error Flag */ +#define FLASH_FLAG_RORFF (0x00010000) /* Raw Operation Finished Flag */ +#define FLASH_FLAG_PPEF (0x00020000) /* Page Erase/Program Protected Error Flag */ + +/* FLASH OIER */ +#define FLASH_INT_ORFIEN (0x00000001) /* Flash Operation Finished Interrupt Enable */ +#define FLASH_INT_ITADIEN (0x00000002) /* Invalid Target Address Interrupt Enable */ +#define FLASH_INT_OBEIEN (0x00000004) /* Option Byte Checksum Error Interrupt Enable */ +#define FLASH_INT_IOCMIEN (0x00000008) /* Invalid Operation Command Interrupt Enable */ +#define FLASH_INT_OREIEN (0x00000010) /* Operation Error Interrupt Enable */ +#define FLASH_INT_ALL (0x0000001F) /* Flash all Interrupt Enable */ + +/* Option Bytes Address */ +#define OPTION_BYTE_BASE (0x1FF00000) /* Option Byte Base Address */ +#define OB_PP0 (0x1FF00000) /* Option Byte: Write Protection 0 */ +#define OB_PP1 (0x1FF00004) /* Option Byte: Write Protection 1 */ +#define OB_PP2 (0x1FF00008) /* Option Byte: Write Protection 2 */ +#define OB_PP3 (0x1FF0000C) /* Option Byte: Write Protection 3 */ +#define OB_CP (0x1FF00010) /* Option Byte: Security Protection */ +#define OB_CHECKSUM (0x1FF00020) /* Option Byte: Checksum */ + +/* Flash Write Protection Page Mask */ +#if (LIBCFG_FLASH_2PAGE_PER_WPBIT) + #define FLASH_WP_PAGE_SET(OP, PAGE) (OP.WriteProtect[PAGE / 64] |= 1 << ((PAGE % 64) / 2)) + #define FLASH_WP_PAGE_CLEAR(OP, PAGE) (OP.WriteProtect[PAGE / 64] &= ~(1 << ((PAGE % 64) / 2))) + #define FLASH_IS_WP_PAGE(OP, PAGE) (OP.WriteProtect[PAGE / 64] & (1 << ((PAGE % 64) / 2))) +#else + #define FLASH_WP_PAGE_SET(OP, PAGE) (OP.WriteProtect[PAGE / 32] |= 1 << (PAGE % 32)) + #define FLASH_WP_PAGE_CLEAR(OP, PAGE) (OP.WriteProtect[PAGE / 32] &= ~(1 << (PAGE % 32))) + #define FLASH_IS_WP_PAGE(OP, PAGE) (OP.WriteProtect[PAGE / 32] & (1 << (PAGE % 32))) +#endif +#define FLASH_WP_ALLPAGE_SET(OP) {u32 i; for (i = 0; i < 4; i++) { OP.WriteProtect[i] = 0xFFFFFFFF; } } + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH exported functions + * @{ + */ +#if (LIBCFG_FMC_PREFETCH) +void FLASH_SetWaitState(u32 FLASH_WAITSTATE_n); +void FLASH_PrefetchBufferCmd(ControlStatus NewState); +#endif +#if (LIBCFG_FMC_BRANCHCACHE) +void FLASH_BranchCacheCmd(ControlStatus NewState); +#endif +void FLASH_SetRemappingMode(FLASH_Vector RemapMode); +FLASH_State FLASH_ErasePage(u32 PageAddress); +FLASH_State FLASH_EraseOptionByte(void); +FLASH_State FLASH_MassErase(void); +FLASH_State FLASH_ProgramWordData(u32 Address, u32 Data); +FLASH_State FLASH_ProgramOptionByte(FLASH_OptionByte *Option); +void FLASH_GetOptionByteStatus(FLASH_OptionByte *Option); +void FLASH_IntConfig(u32 FLASH_INT, ControlStatus Cmd); +FlagStatus FLASH_GetIntStatus(u32 FLASH_FLAG_x); +void FLASH_ClearIntFlag(u32 FLASH_FLAG_x); +FLASH_State FLASH_WaitForOperationEnd(void); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_gpio.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_gpio.h new file mode 100644 index 00000000000..42f274c4e7c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_gpio.h @@ -0,0 +1,508 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_gpio.h + * @version $Rev:: 7115 $ + * @date $Date:: 2023-08-11 #$ + * @brief The header file of the GPIO and AFIO library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_GPIO_H +#define __HT32F5XXXX_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Settings GPIO settings + * @{ + */ +#ifndef AUTO_CK_CONTROL +#define AUTO_CK_CONTROL (0) +#endif +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO exported types + * @{ + */ + +/** + * @brief Enumeration of GPIO pull resistor. + */ +typedef enum +{ + GPIO_PR_UP = 0, /*!< weak pull-up resistor */ + GPIO_PR_DOWN, /*!< weak pull-down resistor */ + GPIO_PR_DISABLE, /*!< Tri-state */ + #if (LIBCFG_GPIO_PR_STRONG_UP) + GPIO_PR_STRONG_UP, /*!< strong pull-up resistor */ + GPIO_PR_STRONGEST_UP /*!< strongest pull-up resistor */ + #endif +} GPIO_PR_Enum; +/** + * @brief Enumeration of GPIO output drive current. + */ +typedef enum +{ + GPIO_DV_4MA = 0, /*!< 4mA source/sink current */ + GPIO_DV_8MA, /*!< 8mA source/sink current */ + GPIO_DV_12MA, /*!< 12mA source/sink current */ + GPIO_DV_16MA /*!< 16mA source/sink current */ +} GPIO_DV_Enum; +/** + * @brief Enumeration of GPIO direction. + */ +typedef enum +{ + GPIO_DIR_IN = 0, /*!< input mode */ + GPIO_DIR_OUT /*!< output mode */ +} GPIO_DIR_Enum; +/** + * @brief Enumeration of AFIO for EXTI channel. + */ +typedef enum +{ + AFIO_EXTI_CH_0 = 0, /*!< GPIO pin 0 */ + AFIO_EXTI_CH_1, /*!< GPIO pin 1 */ + AFIO_EXTI_CH_2, /*!< GPIO pin 2 */ + AFIO_EXTI_CH_3, /*!< GPIO pin 3 */ + AFIO_EXTI_CH_4, /*!< GPIO pin 4 */ + AFIO_EXTI_CH_5, /*!< GPIO pin 5 */ + AFIO_EXTI_CH_6, /*!< GPIO pin 6 */ + AFIO_EXTI_CH_7, /*!< GPIO pin 7 */ + AFIO_EXTI_CH_8, /*!< GPIO pin 8 */ + AFIO_EXTI_CH_9, /*!< GPIO pin 9 */ + AFIO_EXTI_CH_10, /*!< GPIO pin 10 */ + AFIO_EXTI_CH_11, /*!< GPIO pin 11 */ + AFIO_EXTI_CH_12, /*!< GPIO pin 12 */ + AFIO_EXTI_CH_13, /*!< GPIO pin 13 */ + AFIO_EXTI_CH_14, /*!< GPIO pin 14 */ + AFIO_EXTI_CH_15 /*!< GPIO pin 15 */ +} AFIO_EXTI_CH_Enum; +/** + * @brief Enumeration of AFIO_MODE. + */ +typedef enum +{ + AFIO_MODE_DEFAULT = 0, /*!< Default AFIO mode */ + AFIO_MODE_1, /*!< AFIO mode 1 */ + AFIO_MODE_2, /*!< AFIO mode 2 */ + AFIO_MODE_3, /*!< AFIO mode 3 */ + AFIO_MODE_4, /*!< AFIO mode 4 */ + AFIO_MODE_5, /*!< AFIO mode 5 */ + AFIO_MODE_6, /*!< AFIO mode 6 */ + AFIO_MODE_7, /*!< AFIO mode 7 */ + AFIO_MODE_8, /*!< AFIO mode 8 */ + AFIO_MODE_9, /*!< AFIO mode 9 */ + AFIO_MODE_10, /*!< AFIO mode 10 */ + AFIO_MODE_11, /*!< AFIO mode 11 */ + AFIO_MODE_12, /*!< AFIO mode 12 */ + AFIO_MODE_13, /*!< AFIO mode 13 */ + AFIO_MODE_14, /*!< AFIO mode 14 */ + AFIO_MODE_15 /*!< AFIO mode 15 */ +} AFIO_MODE_Enum; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO exported constants + * @{ + */ + +/* Definitions of AFIO_FUN */ +#define AFIO_FUN_DEFAULT AFIO_MODE_DEFAULT /*!< Default AFIO mode */ +#define AFIO_FUN_GPIO AFIO_MODE_1 /*!< AFIO mode GPIO */ +#if (LIBCFG_AFIO_SYSTEM_MODE1) +#define AFIO_FUN_SYSTEM AFIO_MODE_1 /*!< AFIO mode System */ +#else +#define AFIO_FUN_SYSTEM AFIO_MODE_15 /*!< AFIO mode System */ +#endif +#if (LIBCFG_AFIO_DAC_MODE3) +#define AFIO_FUN_DAC0 AFIO_MODE_3 /*!< AFIO mode DAC0 */ +#define AFIO_FUN_DAC1 AFIO_MODE_3 /*!< AFIO mode DAC1 */ +#else +#define AFIO_FUN_DAC0 AFIO_MODE_2 /*!< AFIO mode DAC0 */ +#endif +#define AFIO_FUN_ADC0 AFIO_MODE_2 /*!< AFIO mode ADC0 */ +#define AFIO_FUN_ADC1 AFIO_MODE_3 /*!< AFIO mode ADC1 */ +#if (LIBCFG_AFIO_LEDC_MODE3) +#define AFIO_FUN_LEDC AFIO_MODE_3 /*!< AFIO mode LEDC */ +#else +#define AFIO_FUN_LEDC AFIO_MODE_14 /*!< AFIO mode LEDC */ +#endif +#define AFIO_FUN_CMP AFIO_MODE_3 /*!< AFIO mode CMP */ +#define AFIO_FUN_MCTM_GPTM AFIO_MODE_4 /*!< AFIO mode MCTM/GPTM */ +#if (LIBCFG_AFIO_SCTM_MODE4) +#define AFIO_FUN_SCTM AFIO_MODE_4 /*!< AFIO mode SCTM */ +#elif (LIBCFG_AFIO_SCTM_MODE9) +#define AFIO_FUN_SCTM AFIO_MODE_9 /*!< AFIO mode SCTM */ +#else +#define AFIO_FUN_SCTM AFIO_MODE_13 /*!< AFIO mode SCTM */ +#endif +#if (LIBCFG_AFIO_PWM_MODE4) +#define AFIO_FUN_PWM AFIO_MODE_4 /*!< AFIO mode PWM */ +#else +#define AFIO_FUN_PWM AFIO_MODE_13 /*!< AFIO mode PWM */ +#endif +#define AFIO_FUN_SPI AFIO_MODE_5 /*!< AFIO mode SPI */ +#define AFIO_FUN_USART_UART AFIO_MODE_6 /*!< AFIO mode USART/UART */ +#define AFIO_FUN_I2C AFIO_MODE_7 /*!< AFIO mode I2C */ +#define AFIO_FUN_SCI AFIO_MODE_8 /*!< AFIO mode SCI */ +#define AFIO_FUN_CMP_OPA AFIO_MODE_8 /*!< AFIO mode CMP/OPA */ +#define AFIO_FUN_EBI AFIO_MODE_9 /*!< AFIO mode EBI */ +#define AFIO_FUN_I2S AFIO_MODE_10 /*!< AFIO mode I2S */ +#define AFIO_FUN_CAN AFIO_MODE_12 /*!< AFIO mode CAN */ +#define AFIO_FUN_TEKY AFIO_MODE_12 /*!< AFIO mode TKEY */ +#define AFIO_FUN_LCD AFIO_MODE_14 /*!< AFIO mode LCD */ +#define AFIO_FUN_SLED AFIO_MODE_14 /*!< AFIO mode SLED */ + +/* Definitions of AFIO_FUN alias */ +#define AFIO_FUN_MCTM0 AFIO_FUN_MCTM_GPTM + +#define AFIO_FUN_GPTM0 AFIO_FUN_MCTM_GPTM +#define AFIO_FUN_GPTM1 AFIO_FUN_MCTM_GPTM +#define AFIO_FUN_GPTM2 AFIO_FUN_MCTM_GPTM +#define AFIO_FUN_GPTM3 AFIO_FUN_MCTM_GPTM + +#define AFIO_FUN_PWM0 AFIO_FUN_PWM +#define AFIO_FUN_PWM1 AFIO_FUN_PWM +#define AFIO_FUN_PWM2 AFIO_FUN_PWM +#define AFIO_FUN_PWM3 AFIO_FUN_PWM + +#define AFIO_FUN_SCTM0 AFIO_FUN_SCTM +#define AFIO_FUN_SCTM1 AFIO_FUN_SCTM +#define AFIO_FUN_SCTM2 AFIO_FUN_SCTM +#define AFIO_FUN_SCTM3 AFIO_FUN_SCTM + +#define AFIO_FUN_ADC AFIO_FUN_ADC0 + +/* Definitions of GPIO_Px */ +#define GPIO_PORT_NUM (6) +#define GPIO_PIN_NUM (16) +#define GPIO_PA (0) +#define GPIO_PB (1) +#if (LIBCFG_GPIOC) +#define GPIO_PC (2) +#endif +#if (LIBCFG_GPIOD) +#define GPIO_PD (3) +#endif +#if (LIBCFG_GPIOE) +#define GPIO_PE (4) +#endif +#if (LIBCFG_GPIOF) +#define GPIO_PF (5) +#endif + +/* Definitions of GPIO port source for EXTI channel */ +#define AFIO_ESS_PA GPIO_PA /*!< EXTI channel x source come from GPIO Port A */ +#define AFIO_ESS_PB GPIO_PB /*!< EXTI channel x source come from GPIO Port B */ +#if (LIBCFG_GPIOC) +#define AFIO_ESS_PC GPIO_PC /*!< EXTI channel x source come from GPIO Port C */ +#endif +#if (LIBCFG_GPIOD) +#define AFIO_ESS_PD GPIO_PD /*!< EXTI channel x source come from GPIO Port D */ +#endif +#if (LIBCFG_GPIOE) +#define AFIO_ESS_PE GPIO_PE /*!< EXTI channel x source come from GPIO Port E */ +#endif +#if (LIBCFG_GPIOF) +#define AFIO_ESS_PF GPIO_PF /*!< EXTI channel x source come from GPIO Port F */ +#endif + +/* Definitions of GPIO_PIN */ +#define GPIO_PIN_0 0x0001 /*!< GPIO pin 0 selected */ +#define GPIO_PIN_1 0x0002 /*!< GPIO pin 1 selected */ +#define GPIO_PIN_2 0x0004 /*!< GPIO pin 2 selected */ +#define GPIO_PIN_3 0x0008 /*!< GPIO pin 3 selected */ +#define GPIO_PIN_4 0x0010 /*!< GPIO pin 4 selected */ +#define GPIO_PIN_5 0x0020 /*!< GPIO pin 5 selected */ +#define GPIO_PIN_6 0x0040 /*!< GPIO pin 6 selected */ +#define GPIO_PIN_7 0x0080 /*!< GPIO pin 7 selected */ +#define GPIO_PIN_8 0x0100 /*!< GPIO pin 8 selected */ +#define GPIO_PIN_9 0x0200 /*!< GPIO pin 9 selected */ +#define GPIO_PIN_10 0x0400 /*!< GPIO pin 10 selected */ +#define GPIO_PIN_11 0x0800 /*!< GPIO pin 11 selected */ +#define GPIO_PIN_12 0x1000 /*!< GPIO pin 12 selected */ +#define GPIO_PIN_13 0x2000 /*!< GPIO pin 13 selected */ +#define GPIO_PIN_14 0x4000 /*!< GPIO pin 14 selected */ +#define GPIO_PIN_15 0x8000 /*!< GPIO pin 15 selected */ +#define GPIO_PIN_ALL 0xFFFF /*!< GPIO all pins selected */ + +/* Definitions of AFIO_PIN */ +#define AFIO_PIN_0 0x0001 /*!< AFIO pin 0 selected */ +#define AFIO_PIN_1 0x0002 /*!< AFIO pin 1 selected */ +#define AFIO_PIN_2 0x0004 /*!< AFIO pin 2 selected */ +#define AFIO_PIN_3 0x0008 /*!< AFIO pin 3 selected */ +#define AFIO_PIN_4 0x0010 /*!< AFIO pin 4 selected */ +#define AFIO_PIN_5 0x0020 /*!< AFIO pin 5 selected */ +#define AFIO_PIN_6 0x0040 /*!< AFIO pin 6 selected */ +#define AFIO_PIN_7 0x0080 /*!< AFIO pin 7 selected */ +#define AFIO_PIN_8 0x0100 /*!< AFIO pin 8 selected */ +#define AFIO_PIN_9 0x0200 /*!< AFIO pin 9 selected */ +#define AFIO_PIN_10 0x0400 /*!< AFIO pin 10 selected */ +#define AFIO_PIN_11 0x0800 /*!< AFIO pin 11 selected */ +#define AFIO_PIN_12 0x1000 /*!< AFIO pin 12 selected */ +#define AFIO_PIN_13 0x2000 /*!< AFIO pin 13 selected */ +#define AFIO_PIN_14 0x4000 /*!< AFIO pin 14 selected */ +#define AFIO_PIN_15 0x8000 /*!< AFIO pin 15 selected */ +#define AFIO_PIN_ALL 0xFFFF /*!< All AFIO pins selected */ + +/* Definitions of GPIO_PIN_NUM */ +#define GPIO_PIN_NUM_0 0x00 /*!< GPIO pin number 0 selected */ +#define GPIO_PIN_NUM_1 0x01 /*!< GPIO pin number 1 selected */ +#define GPIO_PIN_NUM_2 0x02 /*!< GPIO pin number 2 selected */ +#define GPIO_PIN_NUM_3 0x03 /*!< GPIO pin number 3 selected */ +#define GPIO_PIN_NUM_4 0x04 /*!< GPIO pin number 4 selected */ +#define GPIO_PIN_NUM_5 0x05 /*!< GPIO pin number 5 selected */ +#define GPIO_PIN_NUM_6 0x06 /*!< GPIO pin number 6 selected */ +#define GPIO_PIN_NUM_7 0x07 /*!< GPIO pin number 7 selected */ +#define GPIO_PIN_NUM_8 0x08 /*!< GPIO pin number 8 selected */ +#define GPIO_PIN_NUM_9 0x09 /*!< GPIO pin number 9 selected */ +#define GPIO_PIN_NUM_10 0x0A /*!< GPIO pin number 10 selected */ +#define GPIO_PIN_NUM_11 0x0B /*!< GPIO pin number 11 selected */ +#define GPIO_PIN_NUM_12 0x0C /*!< GPIO pin number 12 selected */ +#define GPIO_PIN_NUM_13 0x0D /*!< GPIO pin number 13 selected */ +#define GPIO_PIN_NUM_14 0x0E /*!< GPIO pin number 14 selected */ +#define GPIO_PIN_NUM_15 0x0F /*!< GPIO pin number 15 selected */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macro GPIO exported macro + * @{ + */ +/* check parameter of the GPIOx */ +#define IS_GPIO(x) (IS_GPIO1(x) || IS_GPIO2(x) || IS_GPIO3(x) || IS_GPIO4(x) || IS_GPIO5(x)) + +#define IS_GPIO1(x) ((x == HT_GPIOA) || (x == HT_GPIOB) ) + +#if (LIBCFG_GPIOC) +#define IS_GPIO2(x) (x == HT_GPIOC) +#else +#define IS_GPIO2(x) (0) +#endif +#if (LIBCFG_GPIOD) +#define IS_GPIO3(x) (x == HT_GPIOD) +#else +#define IS_GPIO3(x) (0) +#endif +#if (LIBCFG_GPIOE) +#define IS_GPIO4(x) (x == HT_GPIOE) +#else +#define IS_GPIO4(x) (0) + #endif +#if (LIBCFG_GPIOF) +#define IS_GPIO5(x) (x == HT_GPIOF) +#else +#define IS_GPIO5(x) (0) +#endif + +/* check parameter of the GPIO_Px */ +#define IS_GPIO_PORT(x) (IS_GPIO_PORT1(x) || IS_GPIO_PORT2(x) || IS_GPIO_PORT3(x) || IS_GPIO_PORT4(x) || IS_GPIO_PORT5(x)) + +#define IS_GPIO_PORT1(x) ((x == GPIO_PA) || (x == GPIO_PB)) + +#if (LIBCFG_GPIOC) +#define IS_GPIO_PORT2(x) (x == GPIO_PC) +#else +#define IS_GPIO_PORT2(x) (0) +#endif +#if (LIBCFG_GPIOD) +#define IS_GPIO_PORT3(x) (x == GPIO_PD) +#else +#define IS_GPIO_PORT3(x) (0) +#endif +#if (LIBCFG_GPIOE) +#define IS_GPIO_PORT4(x) (x == GPIO_PE) +#else +#define IS_GPIO_PORT4(x) (0) +#endif +#if (LIBCFG_GPIOF) +#define IS_GPIO_PORT5(x) (x == GPIO_PF) +#else +#define IS_GPIO_PORT5(x) (0) +#endif + +/* check parameter of the GPIO_PIN_NUM */ +#define IS_GPIO_PIN_NUM(x) (x < 16) + + +#define IS_GPIO_PR_UP(x) (x == GPIO_PR_UP) +#define IS_GPIO_PR_DOWN(x) (x == GPIO_PR_DOWN) +#define IS_GPIO_PR_DISABLE(x) (x == GPIO_PR_DISABLE) + +#if (LIBCFG_GPIO_PR_STRONG_UP) +#define IS_GPIO_PR_STRONG_UP(x) (x == GPIO_PR_STRONG_UP) +#define IS_GPIO_PR_STRONGEST_UP(x) (x == GPIO_PR_STRONGEST_UP) +#else +#define IS_GPIO_PR_STRONG_UP(x) (0) +#define IS_GPIO_PR_STRONGEST_UP(x) (0) +#endif + +/* check parameter of the GPIOx pull resistor */ +#define IS_GPIO_PR(x) (IS_GPIO_PR_UP(x) || \ + IS_GPIO_PR_DOWN(x) || \ + IS_GPIO_PR_DISABLE(x) || \ + IS_GPIO_PR_STRONG_UP(x) || \ + IS_GPIO_PR_STRONGEST_UP(x)) + +/* check parameter of the GPIOx driving current */ +#define IS_GPIO_DV(x) (((x) == GPIO_DV_4MA) || ((x) == GPIO_DV_8MA) || ((x) == GPIO_DV_12MA) || ((x) == GPIO_DV_16MA) ) + +/* check parameter of the GPIOx input/output direction */ +#define IS_GPIO_DIR(x) (((x) == GPIO_DIR_IN) || ((x) == GPIO_DIR_OUT)) + +/* check parameter of the EXTI source port */ +#define IS_AFIO_ESS(x) (IS_AFIO_ESS1(x) || IS_AFIO_ESS2(x) || IS_AFIO_ESS3(x) || IS_AFIO_ESS4(x) || IS_AFIO_ESS5(x)) + +#define IS_AFIO_ESS1(x) ((x == AFIO_ESS_PA) || (x == AFIO_ESS_PB)) +#if (LIBCFG_GPIOC) +#define IS_AFIO_ESS2(x) (x == AFIO_ESS_PC) +#else +#define IS_AFIO_ESS2(x) (0) +#endif +#if (LIBCFG_GPIOD) +#define IS_AFIO_ESS3(x) (x == AFIO_ESS_PD) +#else +#define IS_AFIO_ESS3(x) (0) +#endif +#if (LIBCFG_GPIOE) +#define IS_AFIO_ESS4(x) (x == AFIO_ESS_PE) +#else +#define IS_AFIO_ESS4(x) (0) +#endif +#if (LIBCFG_GPIOF) +#define IS_AFIO_ESS5(x) (x == AFIO_ESS_PF) +#else +#define IS_AFIO_ESS5(x) (0) +#endif + +/* check parameter of the EXTI channel */ +#if (LIBCFG_EXTI_8CH) +#define IS_AFIO_EXTI_CH(x) ((x == AFIO_EXTI_CH_0) || (x == AFIO_EXTI_CH_1) || \ + (x == AFIO_EXTI_CH_2) || (x == AFIO_EXTI_CH_3) || \ + (x == AFIO_EXTI_CH_4) || (x == AFIO_EXTI_CH_5) || \ + (x == AFIO_EXTI_CH_6) || (x == AFIO_EXTI_CH_7)) +#else +#define IS_AFIO_EXTI_CH(x) ((x == AFIO_EXTI_CH_0) || (x == AFIO_EXTI_CH_1) || \ + (x == AFIO_EXTI_CH_2) || (x == AFIO_EXTI_CH_3) || \ + (x == AFIO_EXTI_CH_4) || (x == AFIO_EXTI_CH_5) || \ + (x == AFIO_EXTI_CH_6) || (x == AFIO_EXTI_CH_7) || \ + (x == AFIO_EXTI_CH_8) || (x == AFIO_EXTI_CH_9) || \ + (x == AFIO_EXTI_CH_10) || (x == AFIO_EXTI_CH_11) || \ + (x == AFIO_EXTI_CH_12) || (x == AFIO_EXTI_CH_13) || \ + (x == AFIO_EXTI_CH_14) || (x == AFIO_EXTI_CH_15)) +#endif + +/* check parameter of the AFIO mode */ +#if (LIBCFG_AFIO_MODE_0_7) +#define IS_AFIO_MODE(x) ((x == AFIO_MODE_DEFAULT) || (x == AFIO_MODE_1) || \ + (x == AFIO_MODE_2) || (x == AFIO_MODE_3) || \ + (x == AFIO_MODE_4) || (x == AFIO_MODE_5) || \ + (x == AFIO_MODE_6) || (x == AFIO_MODE_7)) +#else +#define IS_AFIO_MODE(x) ((x == AFIO_MODE_DEFAULT) || (x == AFIO_MODE_1) || \ + (x == AFIO_MODE_2) || (x == AFIO_MODE_3) || \ + (x == AFIO_MODE_4) || (x == AFIO_MODE_5) || \ + (x == AFIO_MODE_6) || (x == AFIO_MODE_7) || \ + (x == AFIO_MODE_8) || (x == AFIO_MODE_9) || \ + (x == AFIO_MODE_10) || (x == AFIO_MODE_11) || \ + (x == AFIO_MODE_12) || (x == AFIO_MODE_13) || \ + (x == AFIO_MODE_14) || (x == AFIO_MODE_15)) +#endif +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO exported functions + * @{ + */ + +/* Prototype of related GPIO function */ +void GPIO_DeInit(HT_GPIO_TypeDef* HT_GPIOx); +void GPIO_DirectionConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DIR_Enum GPIO_DIR_INorOUT); +void GPIO_PullResistorConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_PR_Enum GPIO_PR_x); +void GPIO_InputConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd); +void GPIO_DriveConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DV_Enum GPIO_DV_nMA); +void GPIO_OpenDrainConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd); +#if LIBCFG_GPIO_SINK_CURRENT_ENHANCED +void GPIO_SinkConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n, ControlStatus Cmd); +#endif +FlagStatus GPIO_ReadInBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n); +FlagStatus GPIO_ReadOutBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n); +u16 GPIO_ReadInData(HT_GPIO_TypeDef* HT_GPIOx); +u16 GPIO_ReadOutData(HT_GPIO_TypeDef* HT_GPIOx); +void GPIO_SetOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP); +void GPIO_ClearOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP); +void GPIO_WriteOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, FlagStatus Status); +void GPIO_WriteOutData(HT_GPIO_TypeDef* HT_GPIOx, u16 Data); +void GPIO_PinLock(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP); +bool GPIO_IsPortLocked(HT_GPIO_TypeDef* HT_GPIOx); +bool GPIO_IsPinLocked(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n); +#if (LIBCFG_GPIO_DISABLE_DEBUG_PORT) +void GPIO_DisableDebugPort(void); +#endif +u32 GPIO_GetID(HT_GPIO_TypeDef* HT_GPIOx); + +/* Prototype of related AFIO function */ +void AFIO_DeInit(void); +void AFIO_GPxConfig(u32 GPIO_Px, u32 AFIO_PIN_n, AFIO_MODE_Enum AFIO_MODE_n); +void AFIO_EXTISourceConfig(u32 GPIO_PIN_NUM_n, u32 GPIO_Px); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2c.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2c.h new file mode 100644 index 00000000000..1f822f93d64 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2c.h @@ -0,0 +1,412 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_i2c.h + * @version $Rev:: 7104 $ + * @date $Date:: 2023-08-08 #$ + * @brief The header file of the I2C library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_I2C_H +#define __HT32F5XXXX_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C exported types + * @{ + */ + +#if (LIBCFG_I2C_TWO_DEV_ADDR) +typedef u8 I2C_AddressTypeDef; +#else +typedef u16 I2C_AddressTypeDef; +#endif + +typedef struct +{ + u8 I2C_GeneralCall; + u8 I2C_AddressingMode; + u8 I2C_Acknowledge; + u8 I2C_SpeedOffset; /* Offset value to reach real speed, recommended I2C_SpeedOffset = I2C PCLK/8000000 */ + /* which based on 4.7K Pull up */ + u32 I2C_Speed; + u16 I2C_OwnAddress; +} I2C_InitTypeDef; + +#if (LIBCFG_I2C_TWO_DEV_ADDR) +typedef enum +{ + I2C_DEV_ADDR_0 = 0, + I2C_DEV_ADDR_1 +} I2C_ADDR_Enum; + +#define IS_I2C_ADDR(x) ((x == I2C_DEV_ADDR_0) || (x == I2C_DEV_ADDR_1)) +#endif +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Constants I2C exported constants + * @{ + */ +#define I2C_GENERALCALL_ENABLE ((u32)0x00000004) +#define I2C_GENERALCALL_DISABLE ((u32)0x00000000) + +#define IS_I2C_GENERAL_CALL(CALL) ((CALL == I2C_GENERALCALL_ENABLE) || \ + (CALL == I2C_GENERALCALL_DISABLE)) + +#define I2C_ADDRESSING_7BIT ((u32)0x00000000) +#if (LIBCFG_I2C_NO_10BIT_MODE) +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) ((ADDRESS == I2C_ADDRESSING_7BIT)) +#else +#define I2C_ADDRESSING_10BIT ((u32)0x00000080) + +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) ((ADDRESS == I2C_ADDRESSING_7BIT) || \ + (ADDRESS == I2C_ADDRESSING_10BIT)) +#endif + +#define I2C_ACK_ENABLE ((u32)0x00000001) +#define I2C_ACK_DISABLE ((u32)0x00000000) + +#define IS_I2C_ACKNOWLEDGE(ACKNOWLEDGE) ((ACKNOWLEDGE == I2C_ACK_ENABLE) || \ + (ACKNOWLEDGE == I2C_ACK_DISABLE)) + +#if (LIBCFG_I2C_TWO_DEV_ADDR) +#define I2C_DEV_ADDR0_ENABLE ((u32)0x00008000) +#define I2C_DEV_ADDR0_DISABLE ((u32)0x00000000) + +#define IS_I2C_ADDR0_ENABLE(ADDR) ((ADDR == I2C_ADDR0_ENABLE) || \ + (ADDR == I2C_ADDR0_DISABLE)) + +#define I2C_DEV_ADDR1_ENABLE ((u32)0x80000000) +#define I2C_DEV_ADDR1_DISABLE ((u32)0x00000000) + +#define IS_I2C_ADDR1(ADDR) ((ADDR == I2C_ADDR1_ENABLE) || \ + (ADDR == I2C_ADDR1_DISABLE)) +#endif + +#define I2C_INT_STA ((u32)0x00000001) +#define I2C_INT_STO ((u32)0x00000002) +#define I2C_INT_ADRS ((u32)0x00000004) +#define I2C_INT_GCS ((u32)0x00000008) +#if (LIBCFG_I2C_NO_ARBLOS == 0) +#define I2C_INT_ARBLOS ((u32)0x00000100) +#endif +#define I2C_INT_RXNACK ((u32)0x00000200) +#define I2C_INT_BUSERR ((u32)0x00000400) +#define I2C_INT_TOUT ((u32)0x00000800) +#define I2C_INT_RXDNE ((u32)0x00010000) +#define I2C_INT_TXDE ((u32)0x00020000) +#define I2C_INT_RXBF ((u32)0x00040000) +#if (LIBCFG_I2C_NO_ARBLOS) +#define I2C_INT_ALL ((u32)0x00070E0F) +#else +#define I2C_INT_ALL ((u32)0x00070F0F) +#endif + +#if (LIBCFG_I2C_NO_ARBLOS) +#define IS_I2C_INT(int) (((int & 0xFFF8F1F0) == 0x0) && (int != 0x0)) +#else +#define IS_I2C_INT(int) (((int & 0xFFF8F0F0) == 0x0) && (int != 0x0)) +#endif + +#define I2C_MASTER_READ ((u32)0x00000400) +#define I2C_MASTER_WRITE ((u32)0x00000000) + +#define IS_I2C_DIRECTION(DIRECTION) ((DIRECTION == I2C_MASTER_READ) || \ + (DIRECTION == I2C_MASTER_WRITE)) + + +#define I2C_REGISTER_CR ((u8)0x00) +#define I2C_REGISTER_IER ((u8)0x04) +#define I2C_REGISTER_ADDR ((u8)0x08) +#define I2C_REGISTER_SR ((u8)0x0C) +#define I2C_REGISTER_SHPGR ((u8)0x10) +#define I2C_REGISTER_SLPGR ((u8)0x14) +#define I2C_REGISTER_DR ((u8)0x18) +#define I2C_REGISTER_BFCLR ((u8)0x1C) +#define I2C_REGISTER_TAR ((u8)0x20) + +#define IS_I2C_REGISTER(REGISTER) ((REGISTER == I2C_REGISTER_CR) || \ + (REGISTER == I2C_REGISTER_IER) || \ + (REGISTER == I2C_REGISTER_ADDR) || \ + (REGISTER == I2C_REGISTER_SR) || \ + (REGISTER == I2C_REGISTER_SHPGR) || \ + (REGISTER == I2C_REGISTER_SLPGR) || \ + (REGISTER == I2C_REGISTER_DR) || \ + (REGISTER == I2C_REGISTER_BFCLR) || \ + (REGISTER == I2C_REGISTER_TAR)) + + +#define I2C_FLAG_STA ((u32)0x00000001) +#define I2C_FLAG_STO ((u32)0x00000002) +#define I2C_FLAG_ADRS ((u32)0x00000004) +#define I2C_FLAG_GCS ((u32)0x00000008) +#if (LIBCFG_I2C_NO_ARBLOS) +#define IS_FLAG_ARBLOS(x) (0) +#else +#define I2C_FLAG_ARBLOS ((u32)0x00000100) +#define IS_FLAG_ARBLOS(x) (x == I2C_FLAG_ARBLOS) +#endif +#define I2C_FLAG_RXNACK ((u32)0x00000200) +#define I2C_FLAG_BUSERR ((u32)0x00000400) +#define I2C_FLAG_TOUTF ((u32)0x00000800) +#define I2C_FLAG_RXDNE ((u32)0x00010000) +#define I2C_FLAG_TXDE ((u32)0x00020000) +#define I2C_FLAG_RXBF ((u32)0x00040000) +#define I2C_FLAG_BUSBUSY ((u32)0x00080000) +#define I2C_FLAG_MASTER ((u32)0x00100000) +#define I2C_FLAG_TXNRX ((u32)0x00200000) + +#define IS_I2C_FLAG(FLAG) ((FLAG == I2C_FLAG_STA) || \ + (FLAG == I2C_FLAG_STO) || \ + (FLAG == I2C_FLAG_ADRS) || \ + (FLAG == I2C_FLAG_GCS) || \ + IS_FLAG_ARBLOS(FLAG) || \ + (FLAG == I2C_FLAG_RXNACK) || \ + (FLAG == I2C_FLAG_BUSERR) || \ + (FLAG == I2C_FLAG_TOUTF) || \ + (FLAG == I2C_FLAG_RXDNE) || \ + (FLAG == I2C_FLAG_TXDE) || \ + (FLAG == I2C_FLAG_RXBF) || \ + (FLAG == I2C_FLAG_BUSBUSY)|| \ + (FLAG == I2C_FLAG_MASTER) || \ + (FLAG == I2C_FLAG_TXNRX)) + +#define IS_I2C_CLEAR_FLAG(FLAG) (IS_FLAG_ARBLOS(FLAG) || \ + (FLAG == I2C_FLAG_RXNACK) || \ + (FLAG == I2C_FLAG_BUSERR) || \ + (FLAG == I2C_FLAG_TOUTF)) + +#define I2C_MASTER_SEND_START ((u32)0x00180001) +#define I2C_MASTER_RECEIVER_MODE ((u32)0x00180004) +#define I2C_MASTER_TRANSMITTER_MODE ((u32)0x003A0004) +#define I2C_MASTER_RX_NOT_EMPTY ((u32)0x00190000) +#define I2C_MASTER_RX_NOT_EMPTY_NOBUSY ((u32)0x00010000) +#define I2C_MASTER_TX_EMPTY ((u32)0x003A0000) +#define I2C_MASTER_RX_BUFFER_FULL ((u32)0x001D0000) +#define I2C_SLAVE_ACK_TRANSMITTER_ADDRESS ((u32)0x002A0004) +#define I2C_SLAVE_ACK_RECEIVER_ADDRESS ((u32)0x00080004) +#define I2C_SLAVE_ACK_GCALL_ADDRESS ((u32)0x00080008) +#define I2C_SLAVE_RX_NOT_EMPTY ((u32)0x00090000) +#define I2C_SLAVE_RX_NOT_EMPTY_STOP ((u32)0x00010002) +#define I2C_SLAVE_TX_EMPTY ((u32)0x002A0000) +#define I2C_SLAVE_RX_BUFFER_FULL ((u32)0x000D0000) +#define I2C_SLAVE_RECEIVED_NACK ((u32)0x00080200) +#define I2C_SLAVE_RECEIVED_NACK_STOP ((u32)0x00000202) +#define I2C_SLAVE_STOP_DETECTED ((u32)0x00000002) + + +#define IS_I2C_STATUS(STATUS) ((STATUS == I2C_MASTER_SEND_START) || \ + (STATUS == I2C_MASTER_RECEIVER_MODE) || \ + (STATUS == I2C_MASTER_TRANSMITTER_MODE) || \ + (STATUS == I2C_MASTER_RX_NOT_EMPTY) || \ + (STATUS == I2C_MASTER_RX_NOT_EMPTY_NOBUSY) || \ + (STATUS == I2C_MASTER_TX_EMPTY) || \ + (STATUS == I2C_MASTER_RX_BUFFER_FULL) || \ + (STATUS == I2C_SLAVE_ACK_TRANSMITTER_ADDRESS) || \ + (STATUS == I2C_SLAVE_ACK_RECEIVER_ADDRESS) || \ + (STATUS == I2C_SLAVE_ACK_GCALL_ADDRESS) || \ + (STATUS == I2C_SLAVE_RX_NOT_EMPTY) || \ + (STATUS == I2C_SLAVE_RX_NOT_EMPTY_STOP) || \ + (STATUS == I2C_SLAVE_TX_EMPTY) || \ + (STATUS == I2C_SLAVE_RX_BUFFER_FULL) || \ + (STATUS == I2C_SLAVE_RECEIVED_NACK) || \ + (STATUS == I2C_SLAVE_RECEIVED_NACK_STOP) || \ + (STATUS == I2C_SLAVE_STOP_DETECTED)) + +#if (LIBCFG_PDMA) +#define I2C_PDMAREQ_TX ((u32)0x00000100) +#define I2C_PDMAREQ_RX ((u32)0x00000200) + +#define IS_I2C_PDMA_REQ(REQ) (((REQ & 0xFFFFFCFF) == 0x0) && (REQ != 0x0)) +#endif + +#define I2C_PRESCALER_1 ((u32)0x00000000) +#define I2C_PRESCALER_2 ((u32)0x00010000) +#define I2C_PRESCALER_4 ((u32)0x00020000) +#define I2C_PRESCALER_8 ((u32)0x00030000) +#if (LIBCFG_I2C_PRESCALER_2BIT == 0) +#define I2C_PRESCALER_16 ((u32)0x00040000) +#define I2C_PRESCALER_32 ((u32)0x00050000) +#define I2C_PRESCALER_64 ((u32)0x00060000) +#define I2C_PRESCALER_128 ((u32)0x00070000) +#endif + +#if (LIBCFG_I2C_PRESCALER_2BIT) +#define IS_I2C_PRESCALER(PRESCALER) ((PRESCALER == I2C_PRESCALER_1) || \ + (PRESCALER == I2C_PRESCALER_2) || \ + (PRESCALER == I2C_PRESCALER_4) || \ + (PRESCALER == I2C_PRESCALER_8)) +#else +#define IS_I2C_PRESCALER(PRESCALER) ((PRESCALER == I2C_PRESCALER_1) || \ + (PRESCALER == I2C_PRESCALER_2) || \ + (PRESCALER == I2C_PRESCALER_4) || \ + (PRESCALER == I2C_PRESCALER_8) || \ + (PRESCALER == I2C_PRESCALER_16) || \ + (PRESCALER == I2C_PRESCALER_32) || \ + (PRESCALER == I2C_PRESCALER_64) || \ + (PRESCALER == I2C_PRESCALER_128)) +#endif + +#if (LIBCFG_I2C_NO_ADDR_MASK == 0) +#define I2C_MASKBIT_0 ((u32)0x00000001) +#define I2C_MASKBIT_1 ((u32)0x00000002) +#define I2C_MASKBIT_2 ((u32)0x00000004) +#define I2C_MASKBIT_3 ((u32)0x00000008) +#define I2C_MASKBIT_4 ((u32)0x00000010) +#define I2C_MASKBIT_5 ((u32)0x00000020) +#define I2C_MASKBIT_6 ((u32)0x00000040) +#define I2C_MASKBIT_7 ((u32)0x00000080) +#define I2C_MASKBIT_8 ((u32)0x00000100) +#define I2C_MASKBIT_9 ((u32)0x00000200) + + +#define IS_I2C_ADDRESS_MASK(MASK) ((MASK == I2C_MASKBIT_0) || \ + (MASK == I2C_MASKBIT_1) || \ + (MASK == I2C_MASKBIT_2) || \ + (MASK == I2C_MASKBIT_3) || \ + (MASK == I2C_MASKBIT_4) || \ + (MASK == I2C_MASKBIT_5) || \ + (MASK == I2C_MASKBIT_6) || \ + (MASK == I2C_MASKBIT_7) || \ + (MASK == I2C_MASKBIT_8) || \ + (MASK == I2C_MASKBIT_9)) +#endif + +#define IS_I2C(x) (IS_I2C0(x) || IS_I2C1(x) || IS_I2C2(x)) +#define IS_I2C0(x) (x == HT_I2C0) + +#if (LIBCFG_I2C1) +#define IS_I2C1(x) (x == HT_I2C1) +#else +#define IS_I2C1(x) (0) +#endif + +#if (LIBCFG_I2C2) +#define IS_I2C2(x) (x == HT_I2C2) +#else +#define IS_I2C2(x) (0) +#endif + +#if (LIBCFG_I2C_NO_10BIT_MODE) +#define IS_I2C_ADDRESS(ADDRESS) (ADDRESS <= 0x7F) +#else +#define IS_I2C_ADDRESS(ADDRESS) (ADDRESS <= 0x3FF) +#endif + +#define IS_I2C_SPEED(SPEED) ((SPEED >= 1) && (SPEED <= 1000000)) + +#define IS_I2C_SCL_HIGH(HIGH) (HIGH <= 0xFFFF) + +#define IS_I2C_SCL_LOW(LOW) (LOW <= 0xFFFF) + +#if (LIBCFG_I2C_TOUT_COUNT_8BIT) +#define IS_I2C_TIMEOUT(TIMEOUT) (TIMEOUT <= 0xFF) +#else +#define IS_I2C_TIMEOUT(TIMEOUT) (TIMEOUT <= 0xFFFF) +#endif + +#define SEQ_FILTER_DISABLE ((u32)0x00000000) +#define SEQ_FILTER_1_PCLK ((u32)0x00004000) +#define SEQ_FILTER_2_PCLK ((u32)0x00008000) + +#define IS_I2C_SEQ_FILTER_MASK(CONFIG) ((CONFIG == SEQ_FILTER_DISABLE) || \ + (CONFIG == SEQ_FILTER_1_PCLK) || \ + (CONFIG == SEQ_FILTER_2_PCLK)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Functions I2C exported functions + * @{ + */ +void I2C_DeInit(HT_I2C_TypeDef* I2Cx); +void I2C_Init(HT_I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStructure); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStructure); +void I2C_Cmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_GenerateSTOP(HT_I2C_TypeDef* I2Cx); +void I2C_IntConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Int, ControlStatus NewState); +void I2C_GeneralCallCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_AckCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_SetOwnAddress(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address); +#if (LIBCFG_I2C_TWO_DEV_ADDR) +void I2C_SetOwnAddress1(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address); +void I2C_OwnAddressCmd(HT_I2C_TypeDef* I2Cx, I2C_ADDR_Enum Address, ControlStatus NewState); +#endif +void I2C_TargetAddressConfig(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address, u32 I2C_Direction); +void I2C_SendData(HT_I2C_TypeDef* I2Cx, u8 I2C_Data); +u8 I2C_ReceiveData(HT_I2C_TypeDef* I2Cx); +u32 I2C_ReadRegister(HT_I2C_TypeDef* I2Cx, u8 I2C_Register); +FlagStatus I2C_GetFlagStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag); +ErrStatus I2C_CheckStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Status); +void I2C_ClearFlag(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag); +void I2C_SetSCLHighPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_HighPeriod); +void I2C_SetSCLLowPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_LowPeriod); +#if (LIBCFG_PDMA) +void I2C_PDMACmd(HT_I2C_TypeDef* I2Cx, u32 I2C_PDMAREQ, ControlStatus NewState); +void I2C_PDMANACKCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +#endif +void I2C_TimeOutCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_SetTimeOutValue(HT_I2C_TypeDef* I2Cx, u32 I2C_Timeout); +void I2C_SetTimeOutPrescaler(HT_I2C_TypeDef* I2Cx, u32 I2C_Prescaler); +#if (LIBCFG_I2C_NO_ADDR_MASK == 0) +void I2C_AddressMaskConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Mask); +#endif +u16 I2C_GetAddressBuffer(HT_I2C_TypeDef* I2Cx); +void I2C_CombFilterCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState); +void I2C_SequentialFilterConfig(HT_I2C_TypeDef* I2Cx, u32 Seq_Filter_Select); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2s.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2s.h new file mode 100644 index 00000000000..2d4646c4d11 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_i2s.h @@ -0,0 +1,240 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_i2s.h + * @version $Rev:: 2960 $ + * @date $Date:: 2018-08-02 #$ + * @brief The header file of the I2S library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_I2S_H +#define __HT32F5XXXX_I2S_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Types I2S exported types + * @{ + */ +typedef struct +{ + u32 I2S_Mode; + u32 I2S_Format; + u32 I2S_WordWidth; + u32 I2S_MclkOut; + u32 I2S_MclkInv; + u32 I2S_BclkInv; + u32 I2S_X_Div; + u32 I2S_Y_Div; + u32 I2S_N_Div; +} I2S_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Constants I2S exported constants + * @{ + */ +/* mode */ +#define I2S_MASTER_TX (1UL << 1) +#define I2S_MASTER_RX (1UL << 2) +#define I2S_MASTER_TX_RX ((1UL << 1) | (1UL << 2)) + +#define I2S_SLAVE_TX ((1UL << 3) | (1UL << 1)) +#define I2S_SLAVE_RX ((1UL << 3) | (1UL << 2)) +#define I2S_SLAVE_TX_RX ((1UL << 3) | (1UL << 1) | (1UL << 2)) + +#define IS_I2S_MODE(MOD) ((MOD == I2S_MASTER_TX) || \ + (MOD == I2S_MASTER_RX) || \ + (MOD == I2S_MASTER_TX_RX) || \ + (MOD == I2S_SLAVE_TX) || \ + (MOD == I2S_SLAVE_RX) || \ + (MOD == I2S_SLAVE_TX_RX)) + + +/* format */ +#define I2S_JUSTIFIED_STEREO (0) +#define LEFT_JUSTIFIED_STEREO (1UL << 6) +#define RIGHT_JUSTIFIED_STEREO (2UL << 6) +#define I2S_JUSTIFIED_REPEAT (1UL << 10) + +#define I2S_JUSTIFIED_STEREO_EXT (1UL << 8) +#define LEFT_JUSTIFIED_STEREO_EXT ((1UL << 8) | (1UL << 6)) +#define RIGHT_JUSTIFIED_STEREO_EXT ((1UL << 8) | (2UL << 6)) +#define I2S_JUSTIFIED_REPEAT_EXT ((1UL << 8) | (1UL << 10)) + +#define I2S_JUSTIFIED_MONO (1UL << 11) +#define LEFT_JUSTIFIED_MONO ((1UL << 11) | (1UL << 6)) +#define RIGHT_JUSTIFIED_MONO ((1UL << 11) | (2UL << 6)) + +#define I2S_JUSTIFIED_MONO_EXT ((1UL << 8) | (1UL << 11)) +#define LEFT_JUSTIFIED_MONO_EXT ((1UL << 8) | (1UL << 11) | (1UL << 6)) +#define RIGHT_JUSTIFIED_MONO_EXT ((1UL << 8) | (1UL << 11) | (2UL << 6)) + +#define IS_I2S_FORMAT(FMT) ((FMT == I2S_JUSTIFIED_STEREO) || \ + (FMT == LEFT_JUSTIFIED_STEREO) || \ + (FMT == RIGHT_JUSTIFIED_STEREO) || \ + (FMT == I2S_JUSTIFIED_REPEAT) || \ + (FMT == I2S_JUSTIFIED_STEREO_EXT) || \ + (FMT == LEFT_JUSTIFIED_STEREO_EXT) || \ + (FMT == RIGHT_JUSTIFIED_STEREO_EXT) || \ + (FMT == I2S_JUSTIFIED_REPEAT_EXT) || \ + (FMT == I2S_JUSTIFIED_MONO) || \ + (FMT == LEFT_JUSTIFIED_MONO) || \ + (FMT == RIGHT_JUSTIFIED_MONO) || \ + (FMT == I2S_JUSTIFIED_MONO_EXT) || \ + (FMT == LEFT_JUSTIFIED_MONO_EXT) || \ + (FMT == RIGHT_JUSTIFIED_MONO_EXT)) + + +/* word width */ +#define I2S_WORDWIDTH_8 (0) +#define I2S_WORDWIDTH_16 (1UL << 4) +#define I2S_WORDWIDTH_24 (2UL << 4) +#define I2S_WORDWIDTH_32 (3UL << 4) + +#define IS_I2S_WORD_WIDTH(WIDTH) ((WIDTH == I2S_WORDWIDTH_8) || \ + (WIDTH == I2S_WORDWIDTH_16) || \ + (WIDTH == I2S_WORDWIDTH_24) || \ + (WIDTH == I2S_WORDWIDTH_32)) + + +/* clock divider */ +#define IS_I2S_MCLK_DIV(X, Y) ((X > 0) && (X < 256) && (Y > 0) && (Y < 256) && (X <= Y)) + +#define IS_I2S_BCLK_DIV(N) (N < 256) + + +/* FIFO */ +#define I2S_TX_FIFO (1UL << 8) +#define I2S_RX_FIFO (2UL << 8) + +#define IS_I2S_ONE_FIFO(FIFO) ((FIFO == I2S_TX_FIFO) || (FIFO == I2S_RX_FIFO)) + +#define IS_I2S_TWO_FIFO(FIFO) (((FIFO & 0xFFFFFCFF) == 0) && (FIFO != 0)) + +#define IS_I2S_FIFO_LEVEL(LEVEL) ((LEVEL & 0x0000000F) < 9) + + +/* interrupt */ +#define I2S_INT_TXFIFO_TRI (1UL) +#define I2S_INT_TXFIFO_UDF (1UL << 1) +#define I2S_INT_TXFIFO_OVF (1UL << 2) + +#define I2S_INT_RXFIFO_TRI (1UL << 4) +#define I2S_INT_RXFIFO_UDF (1UL << 5) +#define I2S_INT_RXFIFO_OVF (1UL << 6) + +#define IS_I2S_INT(INT) (((INT & 0xFFFFFF88) == 0) && (INT != 0)) + + +/* flag */ +#define I2S_FLAG_TXFIFO_TRI (1UL) +#define I2S_FLAG_TXFIFO_UDF (1UL << 1) +#define I2S_FLAG_TXFIFO_OVF (1UL << 2) +#define I2S_FLAG_RXFIFO_TRI (1UL << 8) +#define I2S_FLAG_RXFIFO_UDF (1UL << 9) +#define I2S_FLAG_RXFIFO_OVF (1UL << 10) + +#define I2S_FLAG_TXFIFO_EMP (1UL << 3) +#define I2S_FLAG_TXFIFO_FUL (1UL << 4) +#define I2S_FLAG_RXFIFO_EMP (1UL << 11) +#define I2S_FLAG_RXFIFO_FUL (1UL << 12) +#define I2S_FLAG_RIGHT_CH (1UL << 16) +#define I2S_FLAG_TX_BUSY (1UL << 17) +#define I2S_FLAG_CLK_RDY (1UL << 18) + +#define IS_I2S_FLAG_CLEAR(FLAG) (((FLAG & 0xFFFFF8F8) == 0) && (FLAG != 0)) + +#define IS_I2S_FLAG(FLAG) ((FLAG == I2S_FLAG_TXFIFO_TRI) || \ + (FLAG == I2S_FLAG_TXFIFO_UDF) || \ + (FLAG == I2S_FLAG_TXFIFO_OVF) || \ + (FLAG == I2S_FLAG_TXFIFO_EMP) || \ + (FLAG == I2S_FLAG_TXFIFO_FUL) || \ + (FLAG == I2S_FLAG_RXFIFO_TRI) || \ + (FLAG == I2S_FLAG_RXFIFO_UDF) || \ + (FLAG == I2S_FLAG_RXFIFO_OVF) || \ + (FLAG == I2S_FLAG_RXFIFO_EMP) || \ + (FLAG == I2S_FLAG_RXFIFO_FUL) || \ + (FLAG == I2S_FLAG_RIGHT_CH) || \ + (FLAG == I2S_FLAG_TX_BUSY) || \ + (FLAG == I2S_FLAG_CLK_RDY)) + + +/* PDMA request */ +#define I2S_PDMAREQ_TX (1UL << 13) +#define I2S_PDMAREQ_RX (1UL << 14) + +#define IS_I2S_PDMA_REQ(REQ) (((REQ & 0xFFFF9FFF) == 0) && (REQ != 0)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Functions I2S exported functions + * @{ + */ +void I2S_DeInit(void); +void I2S_Init(I2S_InitTypeDef* I2S_InitStruct); +void I2S_Cmd(ControlStatus NewState); +void I2S_MclkOutputCmd(ControlStatus NewState); +void I2S_TxMuteCmd(ControlStatus NewState); +void I2S_PDMACmd(u32 I2S_PDMAREQ, ControlStatus NewState); +void I2S_FIFOReset(u32 I2S_FIFO); +void I2S_FIFOTrigLevelConfig(u32 I2S_FIFO, u32 I2S_FIFOLevel); +u8 I2S_GetFIFOStatus(u32 I2S_FIFO); +void I2S_IntConfig(u32 I2S_Int, ControlStatus NewState); +FlagStatus I2S_GetFlagStatus(u32 I2S_Flag); +void I2S_ClearFlag(u32 I2S_Flag); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lcd.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lcd.h new file mode 100644 index 00000000000..61070c721e3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lcd.h @@ -0,0 +1,382 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_lcd.h + * @version V1.00 + * @date 11/15/2017 + * @brief The header file of the LCD library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_LCD_H +#define __HT32F5XXXX_LCD_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup LCD + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup LCD_Exported_Types LCD exported types + * @{ + */ +/** + * @brief Enumeration of LCD mask time. + */ +typedef enum { + LCD_MaskTime_25ns = (0x00 << 24), /*!< MCONT mask time = 25 ns */ + LCD_MaskTime_40ns = (0x01 << 24), /*!< MCONT mask time = 40 ns */ +} LCD_MaskTime_Enum; + +/** + * @brief Enumeration of LCD STATIC switch. + */ +typedef enum { + LCD_StaticSwitch_Close = (0x00 << 14), /*!< STATIC switch is closed during dead time */ + LCD_StaticSwitch_Open = (0x01 << 14), /*!< STATIC switch is open during dead time */ +} LCD_StaticSwitch_Enum; + +/** + * @brief Enumeration of LCD MUXCOM7. + */ +typedef enum +{ + /*!< 57341: SEG28/COM7 */ + /*!< 57352: SEG36/COM7 */ + LCD_MUXCOM7_IS_COM7 = (0x00 << 11), + LCD_MUXCOM7_IS_SEGx = (0x01 << 11), +} LCD_MUXCOM7_Enum; + +/** + * @brief Enumeration of LCD MUXCOM6. + */ +typedef enum +{ + /*!< 57341: SEG27/COM6 */ + /*!< 57352: SEG35/COM6 */ + LCD_MUXCOM6_IS_COM6 = (0x00 << 10), + LCD_MUXCOM6_IS_SEGx = (0x01 << 10), +} LCD_MUXCOM6_Enum; + +/** + * @brief Enumeration of LCD MUXCOM5. + */ +typedef enum +{ + /*!< 57341: SEG26/COM5 */ + /*!< 57352: SEG34/COM5 */ + LCD_MUXCOM5_IS_COM5 = (0x00 << 9), + LCD_MUXCOM5_IS_SEGx = (0x01 << 9), +} LCD_MUXCOM5_Enum; + +/** + * @brief Enumeration of LCD MUXCOM4. + */ +typedef enum +{ + /*!< 57341: SEG25/COM4 */ + /*!< 57352: SEG33/COM4 */ + LCD_MUXCOM4_IS_COM4 = (0x00 << 8), + LCD_MUXCOM4_IS_SEGx = (0x01 << 8), +} LCD_MUXCOM4_Enum; + +/** + * @brief Enumeration of LCD waveform. + */ +typedef enum +{ + LCD_Type_A_Waveform = (0x00 << 7), /*!< Type A waveform */ + LCD_Type_B_Waveform = (0x01 << 7), /*!< Type B waveform */ +} LCD_Waveform_Enum; + +/** + * @brief Enumeration of LCD bias. + */ +typedef enum { + LCD_Bias_1_4 = (0x00 << 5), /*!< 1/4 bias */ + LCD_Bias_1_2 = (0x01 << 5), /*!< 1/2 bias */ + LCD_Bias_1_3 = (0x02 << 5), /*!< 1/3 bias */ + LCD_Bias_Static = (0x03 << 5), /*!< Static bias */ +} LCD_Bias_Enum; + +/** + * @brief Enumeration of LCD duty. + */ +typedef enum { + LCD_Duty_Static = (0x00 << 2), /*!< Static duty */ + LCD_Duty_1_2 = (0x01 << 2), /*!< 1/2 duty */ + LCD_Duty_1_3 = (0x02 << 2), /*!< 1/3 duty */ + LCD_Duty_1_4 = (0x03 << 2), /*!< 1/4 duty */ + LCD_Duty_1_6 = (0x04 << 2), /*!< 1/6 duty */ + LCD_Duty_1_8 = (0x05 << 2), /*!< 1/8 duty */ +} LCD_Duty_Enum; + +/** + * @brief Enumeration of LCD voltage source. + */ +typedef enum { + LCD_VoltageSource_External = (0x00 << 1), /*!< External voltage source */ + LCD_VoltageSource_Internal = (0x01 << 1), /*!< Internal voltage source */ +} LCD_VoltageSource_Enum; + +/** + * @brief Enumeration of LCD clock prescaler. + */ +typedef enum { + LCD_Prescaler_1 = (0x00 << 22), /*!< CK_PS = CK_LCD / 1 */ + LCD_Prescaler_2 = (0x01 << 22), /*!< CK_PS = CK_LCD / 2 */ + LCD_Prescaler_4 = (0x02 << 22), /*!< CK_PS = CK_LCD / 4 */ + LCD_Prescaler_8 = (0x03 << 22), /*!< CK_PS = CK_LCD / 8 */ + LCD_Prescaler_16 = (0x04 << 22), /*!< CK_PS = CK_LCD / 16 */ + LCD_Prescaler_32 = (0x05 << 22), /*!< CK_PS = CK_LCD / 32 */ + LCD_Prescaler_64 = (0x06 << 22), /*!< CK_PS = CK_LCD / 64 */ + LCD_Prescaler_128 = (0x07 << 22), /*!< CK_PS = CK_LCD / 128 */ + LCD_Prescaler_256 = (0x08 << 22), /*!< CK_PS = CK_LCD / 256 */ + LCD_Prescaler_512 = (0x09 << 22), /*!< CK_PS = CK_LCD / 512 */ + LCD_Prescaler_1024 = (0x0A << 22), /*!< CK_PS = CK_LCD / 1024 */ + LCD_Prescaler_2048 = (0x0B << 22), /*!< CK_PS = CK_LCD / 2048 */ + LCD_Prescaler_4096 = (0x0C << 22), /*!< CK_PS = CK_LCD / 4096 */ + LCD_Prescaler_8192 = (0x0D << 22), /*!< CK_PS = CK_LCD / 8192 */ + LCD_Prescaler_16384 = (0x0E << 22), /*!< CK_PS = CK_LCD / 16384 */ + LCD_Prescaler_32768 = (0x0F << 22) /*!< CK_PS = CK_LCD / 32768 */ +} LCD_Prescaler_Enum; + +/** + * @brief Enumeration of LCD clock divider. + */ +typedef enum { + LCD_Divider_16 = (0x00 << 18), /*!< CK_DIV = CK_PS / 16 */ + LCD_Divider_17 = (0x01 << 18), /*!< CK_DIV = CK_PS / 17 */ + LCD_Divider_18 = (0x02 << 18), /*!< CK_DIV = CK_PS / 18 */ + LCD_Divider_19 = (0x03 << 18), /*!< CK_DIV = CK_PS / 19 */ + LCD_Divider_20 = (0x04 << 18), /*!< CK_DIV = CK_PS / 20 */ + LCD_Divider_21 = (0x05 << 18), /*!< CK_DIV = CK_PS / 21 */ + LCD_Divider_22 = (0x06 << 18), /*!< CK_DIV = CK_PS / 22 */ + LCD_Divider_23 = (0x07 << 18), /*!< CK_DIV = CK_PS / 23 */ + LCD_Divider_24 = (0x08 << 18), /*!< CK_DIV = CK_PS / 24 */ + LCD_Divider_25 = (0x09 << 18), /*!< CK_DIV = CK_PS / 25 */ + LCD_Divider_26 = (0x0A << 18), /*!< CK_DIV = CK_PS / 26 */ + LCD_Divider_27 = (0x0B << 18), /*!< CK_DIV = CK_PS / 27 */ + LCD_Divider_28 = (0x0C << 18), /*!< CK_DIV = CK_PS / 28 */ + LCD_Divider_29 = (0x0D << 18), /*!< CK_DIV = CK_PS / 29 */ + LCD_Divider_30 = (0x0E << 18), /*!< CK_DIV = CK_PS / 30 */ + LCD_Divider_31 = (0x0F << 18), /*!< CK_DIV = CK_PS / 31 */ +} LCD_Divider_Enum; + +/** + * @brief Enumeration of LCD blink mode. + */ +typedef enum { + LCD_BlinkMode_Off = (0x00 << 16), /*!< Blink inactive */ + LCD_BlinkMode_SEG0_COM0 = (0x01 << 16), /*!< SEG0 on COM0 blink */ + LCD_BlinkMode_SEG0_AllCOM = (0x02 << 16), /*!< SEG0 on All COM blink */ + LCD_BlinkMode_AllSEG_AllCOM = (0x03 << 16), /*!< All SEG on All COM blink */ +} LCD_BlinkMode_Enum; + +/** + * @brief Enumeration of LCD blink frequency. + */ +typedef enum +{ + LCD_BlinkFrequency_Div8 = (0x00 << 13), /*!< Blink frequency = frame rate / 8 */ + LCD_BlinkFrequency_Div16 = (0x01 << 13), /*!< Blink frequency = frame rate / 16 */ + LCD_BlinkFrequency_Div32 = (0x02 << 13), /*!< Blink frequency = frame rate / 32 */ + LCD_BlinkFrequency_Div64 = (0x03 << 13), /*!< Blink frequency = frame rate / 64 */ + LCD_BlinkFrequency_Div128 = (0x04 << 13), /*!< Blink frequency = frame rate / 128 */ + LCD_BlinkFrequency_Div256 = (0x05 << 13), /*!< Blink frequency = frame rate / 256 */ + LCD_BlinkFrequency_Div512 = (0x06 << 13), /*!< Blink frequency = frame rate / 512 */ + LCD_BlinkFrequency_Div1024 = (0x07 << 13), /*!< Blink frequency = frame rate / 1024 */ +} LCD_BlinkFrequency_Enum; + +/** + * @brief Enumeration of LCD charge pump. + */ +typedef enum +{ + LCD_ChargePump_2V65 = (0x00 << 10), /*!< Charge pump voltage = 2.65 V */ + LCD_ChargePump_2V75 = (0x01 << 10), /*!< Charge pump voltage = 2.75 V */ + LCD_ChargePump_2V85 = (0x02 << 10), /*!< Charge pump voltage = 2.85 V */ + LCD_ChargePump_2V95 = (0x03 << 10), /*!< Charge pump voltage = 2.95 V */ + LCD_ChargePump_3V10 = (0x04 << 10), /*!< Charge pump voltage = 3.10 V */ + LCD_ChargePump_3V25 = (0x05 << 10), /*!< Charge pump voltage = 3.25 V */ + LCD_ChargePump_3V40 = (0x06 << 10), /*!< Charge pump voltage = 3.40 V */ + LCD_ChargePump_3V55 = (0x07 << 10), /*!< Charge pump voltage = 3.55 V */ +} LCD_ChargePump_Enum; + +/** + * @brief Enumeration of LCD dead time. + */ +typedef enum +{ + LCD_Deadtime_0 = (0x00 << 7), /*!< No dead time */ + LCD_Deadtime_1 = (0x01 << 7), /*!< Type A: 1/2 phase period; Type B: 1 phase period */ + LCD_Deadtime_2 = (0x02 << 7), /*!< Type A: 2/2 phase period; Type B: 2 phase period */ + LCD_Deadtime_3 = (0x03 << 7), /*!< Type A: 3/2 phase period; Type B: 3 phase period */ + LCD_Deadtime_4 = (0x04 << 7), /*!< Type A: 4/2 phase period; Type B: 4 phase period */ + LCD_Deadtime_5 = (0x05 << 7), /*!< Type A: 5/2 phase period; Type B: 5 phase period */ + LCD_Deadtime_6 = (0x06 << 7), /*!< Type A: 6/2 phase period; Type B: 6 phase period */ + LCD_Deadtime_7 = (0x07 << 7), /*!< Type A: 7/2 phase period; Type B: 7 phase period */ +} LCD_DeadTime_Enum; + +/** + * @brief Enumeration of LCD high drive. + */ +typedef enum +{ + LCD_HighDrive_0 = (0x00 << 4), /*!< No high drive */ + LCD_HighDrive_1 = (0x01 << 4), /*!< High drive duration = 1 CK_PS pulses */ + LCD_HighDrive_2 = (0x02 << 4), /*!< High drive duration = 2 CK_PS pulses */ + LCD_HighDrive_3 = (0x03 << 4), /*!< High drive duration = 3 CK_PS pulses */ + LCD_HighDrive_4 = (0x04 << 4), /*!< High drive duration = 4 CK_PS pulses */ + LCD_HighDrive_5 = (0x05 << 4), /*!< High drive duration = 5 CK_PS pulses */ + LCD_HighDrive_6 = (0x06 << 4), /*!< High drive duration = 6 CK_PS pulses */ + LCD_HighDrive_7 = (0x07 << 4), /*!< High drive duration = 7 CK_PS pulses */ + LCD_HighDrive_Static = (0xff), /*!< Static high drive */ +} LCD_HighDrive_Enum; + +/** + * @brief Definition of LCD Init Structure. + */ +typedef struct +{ + LCD_Prescaler_Enum LCD_Prescaler; + LCD_Divider_Enum LCD_Divider; + LCD_Duty_Enum LCD_Duty; + LCD_Bias_Enum LCD_Bias; + LCD_Waveform_Enum LCD_Waveform; + LCD_VoltageSource_Enum LCD_VoltageSource; +} LCD_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup LCD_Exported_Constants LCD exported constants + * @{ + */ +#define LCD_INT_UDD ((u32)0x00000002) +#define LCD_INT_SOF ((u32)0x00000001) + +#define IS_LCD_INT(INT) ((((INT) & 0xFFFFFFFC) == 0) && ((INT) != 0)) + + +#define LCD_FLAG_FCRSF ((u32)0x00000020) +#define LCD_FLAG_RDY ((u32)0x00000010) +#define LCD_FLAG_UDD ((u32)0x00000008) +#define LCD_FLAG_UDR ((u32)0x00000004) +#define LCD_FLAG_SOF ((u32)0x00000002) +#define LCD_FLAG_ENS ((u32)0x00000001) + +#define IS_LCD_FLAG(FLAG) (((FLAG) == LCD_FLAG_FCRSF) || \ + ((FLAG) == LCD_FLAG_RDY) || \ + ((FLAG) == LCD_FLAG_UDD) || \ + ((FLAG) == LCD_FLAG_UDR) || \ + ((FLAG) == LCD_FLAG_SOF) || \ + ((FLAG) == LCD_FLAG_ENS)) + + +#define LCD_CLR_UDD ((u32)0x00000002) +#define LCD_CLR_SOF ((u32)0x00000001) + +#define IS_LCD_CLEAR(CLR) ((((CLR) & 0xFFFFFFFC) == 0) && ((CLR) != 0)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup LCD_Exported_Functions LCD exported functions + * @{ + */ + +/* !!! NOTICE !!! + Before using the following functions, be sure to confirm LCDENS = 0 by "LCD_GetFlagStatus(LCD_FLAG_ENS);", + otherwise the LCD may display abnormally. + LCD_DriverInit() + LCD_MaskTimeConfig() + LCD_StaticSwitchConfig() + LCD_MuxCOM7Config() + LCD_MuxCOM6Config() + LCD_MuxCOM5Config() + LCD_MuxCOM4Config() + LCD_WaveformConfig() + LCD_BiasConfig() + LCD_DutyConfig() + LCD_VoltageSourceConfig() + LCD_ChargePumpConfig() +*/ + +void LCD_DriverDeInit(void); +void LCD_DriverInit(LCD_InitTypeDef* LCD_InitStruct); + +void LCD_MaskTimeConfig(LCD_MaskTime_Enum Sel); +void LCD_HalfRLCmd(ControlStatus NewState); +void LCD_StaticSwitchConfig(LCD_StaticSwitch_Enum Sel); +void LCD_MuxCOM7Config(LCD_MUXCOM7_Enum Sel); +void LCD_MuxCOM6Config(LCD_MUXCOM6_Enum Sel); +void LCD_MuxCOM5Config(LCD_MUXCOM5_Enum Sel); +void LCD_MuxCOM4Config(LCD_MUXCOM4_Enum Sel); +void LCD_WaveformConfig(LCD_Waveform_Enum Sel); +void LCD_BiasConfig(LCD_Bias_Enum Sel); +void LCD_DutyConfig(LCD_Duty_Enum Sel); +void LCD_VoltageSourceConfig(LCD_VoltageSource_Enum Sel); +void LCD_Cmd(ControlStatus NewState); + +void LCD_PrescalerConfig(LCD_Prescaler_Enum Sel); +void LCD_DividerConfig(LCD_Divider_Enum Sel); +void LCD_BlinkModeConfig(LCD_BlinkMode_Enum Sel); +void LCD_BlinkFreqConfig(LCD_BlinkFrequency_Enum Sel); +void LCD_ChargePumpConfig(LCD_ChargePump_Enum Sel); +void LCD_DeadTimeConfig(LCD_DeadTime_Enum Sel); +void LCD_HighDriveConfig(LCD_HighDrive_Enum Sel); + +void LCD_IntConfig(u32 LCD_Int, ControlStatus NewState); +FlagStatus LCD_GetFlagStatus(u32 LCD_Flag); +void LCD_SetUpdateDisplayRequest(void); +void LCD_ClearFlag(u32 LCD_Flag); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ledc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ledc.h new file mode 100644 index 00000000000..c12c2a0b04d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_ledc.h @@ -0,0 +1,209 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_ledc.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The header file of the LED Controller library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_LEDC_H +#define __HT32F5XXXX_LEDC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup LEDC + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup LEDC_Exported_Types LEDC exported types + * @{ + */ + +/** + * @brief Selection of LEDC clock source + */ +typedef enum +{ + LEDC_SRC_PCLK = 0, + LEDC_SRC_LSI, /*!< Low speed internal clock, about 32KHz */ + LEDC_SRC_LSE /*!< Low speed external 32768 Hz clock */ +} LEDC_SRC_Enum; + +/** + * @brief Selection of LEDC duty clock numbers + */ +typedef enum +{ + LEDC_DTYNUM_8 = 0, + LEDC_DTYNUM_16, + LEDC_DTYNUM_32, + LEDC_DTYNUM_64 +} LEDC_DTYNUM_Enum; + +/** + * @brief Definition of LEDC Init Structure + */ +typedef struct +{ + LEDC_SRC_Enum LEDC_ClockSource; + LEDC_DTYNUM_Enum LEDC_DutyClockNumber; + u32 LEDC_ClockPrescaler; + u32 LEDC_COMxEN; + u32 LEDC_DeadTime; +} LEDC_InitTypeDef; + +/** + * @brief Enumeration of LED layout mode. + */ +typedef enum +{ + COMMON_CATHODE, /*!< LEDC SEG output polarity is non-inverted. */ + /*!< LEDC COM output polarity is non-inverted.*/ + COMMON_CATHODE_WITH_NPN, /*!< LEDC SEG output polarity is non-inverted. */ + /*!< LEDC COM output polarity is inverted.*/ + COMMON_ANODE_WITH_PNP, /*!< LEDC SEG output polarity is inverted. */ + /*!< LEDC COM output polarity is non-inverted.*/ + COMMON_ANODE_WITH_NPN, /*!< LEDC SEG output polarity is inverted. */ + /*!< LEDC COM output polarity is inverted.*/ +} LEDC_Mode; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup LEDC_Exported_Constants LEDC exported constants + * @{ + */ + +/* Definitions of LEDCER */ +#define LEDC_COM0EN 0x0001 /*!< LEDC COM0 enable */ +#define LEDC_COM1EN 0x0002 /*!< LEDC COM1 enable */ +#define LEDC_COM2EN 0x0004 /*!< LEDC COM2 enable */ +#define LEDC_COM3EN 0x0008 /*!< LEDC COM3 enable */ +#define LEDC_COM4EN 0x0010 /*!< LEDC COM4 enable */ +#define LEDC_COM5EN 0x0020 /*!< LEDC COM5 enable */ +#define LEDC_COM6EN 0x0040 /*!< LEDC COM6 enable */ +#define LEDC_COM7EN 0x0080 /*!< LEDC COM7 enable */ +#if (LIBCFG_LEDC_NO_COM_8_11 == 0) +#define LEDC_COM8EN 0x0100 /*!< LEDC COM8 enable */ +#define LEDC_COM9EN 0x0200 /*!< LEDC COM9 enable */ +#define LEDC_COM10EN 0x0400 /*!< LEDC COM10 enable */ +#define LEDC_COM11EN 0x0800 /*!< LEDC COM11 enable */ +#endif + +/* Definitions of COMxPOL */ +#define LEDC_COM0POL 0x00000001 /*!< LEDC COM0 polarity */ +#define LEDC_COM1POL 0x00000002 /*!< LEDC COM1 polarity */ +#define LEDC_COM2POL 0x00000004 /*!< LEDC COM2 polarity */ +#define LEDC_COM3POL 0x00000008 /*!< LEDC COM3 polarity */ +#define LEDC_COM4POL 0x00000010 /*!< LEDC COM4 polarity */ +#define LEDC_COM5POL 0x00000020 /*!< LEDC COM5 polarity */ +#define LEDC_COM6POL 0x00000040 /*!< LEDC COM6 polarity */ +#define LEDC_COM7POL 0x00000080 /*!< LEDC COM7 polarity */ +#if (LIBCFG_LEDC_NO_COM_8_11 == 0) +#define LEDC_COM8POL 0x00000100 /*!< LEDC COM8 polarity */ +#define LEDC_COM9POL 0x00000200 /*!< LEDC COM9 polarity */ +#define LEDC_COM10POL 0x00000400 /*!< LEDC COM10 polarity */ +#define LEDC_COM11POL 0x00000800 /*!< LEDC COM11 polarity */ +#endif + +/* Definitions of SEGxPOL */ +#define LEDC_SEG0POL 0x00010000 /*!< LEDC SEG0 polarity */ +#define LEDC_SEG1POL 0x00020000 /*!< LEDC SEG1 polarity */ +#define LEDC_SEG2POL 0x00040000 /*!< LEDC SEG2 polarity */ +#define LEDC_SEG3POL 0x00080000 /*!< LEDC SEG3 polarity */ +#define LEDC_SEG4POL 0x00100000 /*!< LEDC SEG4 polarity */ +#define LEDC_SEG5POL 0x00200000 /*!< LEDC SEG5 polarity */ +#define LEDC_SEG6POL 0x00400000 /*!< LEDC SEG6 polarity */ +#define LEDC_SEG7POL 0x00800000 /*!< LEDC SEG7 polarity */ + +#define LEDC_FLAG_FRAME (1UL << 0) +#define LEDC_INT_FRAME (1UL << 0) + + +/* check parameter of the LEDC mode */ +#define IS_LEDC_MODE(x) ((x == COMMON_CATHODE) || (x == COMMON_CATHODE_WITH_NPN) || \ + (x == COMMON_ANODE_WITH_PNP) || (x == COMMON_ANODE_WITH_NPN)) + +/** + * @brief Used to check LEDC_SRC_Enum parameter + */ +#define IS_LEDC_SRC(x) ((x == LEDC_SRC_PCLK) || (x == LEDC_SRC_LSI) || (x == LEDC_SRC_LSE)) +#define IS_LEDC_DTYNUM(x) ((x == LEDC_DTYNUM_8) || (x == LEDC_DTYNUM_16) || (x == LEDC_DTYNUM_32) ||\ + (x == LEDC_DTYNUM_64)) +#define IS_LEDC_PSC(x) (x < 4096) +#define IS_LEDC_DTCR(x) (x < 64) +#define IS_LEDC_COMEN(x) (((x & 0xF000) == 0x0) && (x != 0x0)) +#define IS_LEDC_COMPOL(x) (((x & 0xFFFFF000) == 0x0) && (x != 0x0)) +#define IS_LEDC_SEGPOL(x) (((x & 0xFF00FFFF) == 0x0) && (x != 0x0)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup LEDC_Exported_Functions LEDC exported functions + * @{ + */ +void LEDC_DeInit(void); +void LEDC_Init(LEDC_InitTypeDef* LEDC_InitStruct); +void LEDC_ClockSourceConfig(LEDC_SRC_Enum Source); +void LEDC_Cmd(ControlStatus NewState); +void LEDC_IntConfig(ControlStatus NewState); +FlagStatus LEDC_GetFlagStatus(void); +void LEDC_ClearFlagStatus(void); +void LEDC_COMxConfig(u32 LEDC_COMxEN, ControlStatus Cmd); +void LEDC_SetDeadTimeDuty(u32 LEDC_DeadTimeDuty); +void LEDC_SetPolarityMode(u32 LEDC_COMxPOL, u32 LEDC_SEGxPOL , LEDC_Mode mode); +#define LEDC_SetData(COMx, data) HT_LEDC->DR[COMx] = data +#define LEDC_GetData(COMx) HT_LEDC->DR[COMx] +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lib.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lib.h new file mode 100644 index 00000000000..b04cdb33a48 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_lib.h @@ -0,0 +1,332 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_lib.h + * @version $Rev:: 7319 $ + * @date $Date:: 2023-10-28 #$ + * @brief The header file includes all the header files of the libraries. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_LIB_H +#define __HT32F5XXXX_LIB_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Settings ------------------------------------------------------------------------------------------------*/ +#define HT32_FWLIB_VER (0x01009001) +#define HT32_FWLIB_SVN (0x7446) + +#if defined(USE_HT32F52220_30) + #include "ht32f52220_30_libcfg.h" +#endif +#if defined(USE_HT32F52231_41) + #include "ht32f52231_41_libcfg.h" +#endif +#if defined(USE_HT32F52331_41) + #include "ht32f52331_41_libcfg.h" +#endif +#if defined(USE_HT32F52342_52) + #include "ht32f52342_52_libcfg.h" +#endif +#if defined(USE_HT32F52243_53) + #include "ht32f52243_53_libcfg.h" +#endif +#if defined(USE_HT32F5826) + #include "ht32f5826_libcfg.h" +#endif +#if defined(USE_HT32F0008) + #include "ht32f0008_libcfg.h" +#endif +#if defined(USE_HT32F50220_30) + #include "ht32f50220_30_libcfg.h" +#endif +#if defined(USE_HT32F50231_41) + #include "ht32f50231_41_libcfg.h" +#endif +#if defined(USE_HT32F52344_54) + #include "ht32f52344_54_libcfg.h" +#endif +#if defined(USE_HT32F0006) + #include "ht32f0006_libcfg.h" +#endif +#if defined(USE_HT32F52357_67) + #include "ht32f52357_67_libcfg.h" +#endif +#if defined(USE_HT32F54231_41) + #include "ht32f54231_41_libcfg.h" +#endif +#if defined(USE_HT32F54243_53) + #include "ht32f54243_53_libcfg.h" +#endif +#if defined(USE_HT32F57342_52) + #include "ht32f57342_52_libcfg.h" +#endif +#if defined(USE_HT32F57331_41) + #include "ht32f57331_41_libcfg.h" +#endif +#if defined(USE_HT32F50343) + #include "ht32f50343_libcfg.h" +#endif +#if defined(USE_HT32F65230_40) + #include "ht32f65230_40_libcfg.h" +#endif +#if defined(USE_HT32F65232) + #include "ht32f65232_libcfg.h" +#endif +#if defined(USE_HT32F61141) + #include "ht32f61141_libcfg.h" +#endif +#if defined(USE_HT32F61244_45) + #include "ht32f61244_45_libcfg.h" +#endif +#if defined(USE_HT32F50020_30) + #include "ht32f50020_30_libcfg.h" +#endif +#if defined(USE_HT32F67041_51) + #include "ht32f67041_51_libcfg.h" +#endif +#if defined(USE_HT32F50442_52) + #include "ht32f50442_52_libcfg.h" +#endif +#if defined(USE_HT32F50431_41) + #include "ht32f50431_41_libcfg.h" +#endif +#if defined(USE_HT32F53242_52) + #include "ht32f53242_52_libcfg.h" +#endif +#if defined(USE_HT32F53231_41) + #include "ht32f53231_41_libcfg.h" +#endif +#if defined(USE_HT32F66242) + #include "ht32f66242_libcfg.h" +#endif +#if defined(USE_HT32F66246) + #include "ht32f66246_libcfg.h" +#endif +#if defined(USE_HT32F52234_44) + #include "ht32f52234_44_libcfg.h" +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include +#include "ht32f5xxxx_conf.h" + +#if (HT32_LIB_DEBUG == 1) +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define Assert_Param(expr) ((expr) ? (void)0 : assert_error((u8 *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- ------------------------------*/ +void assert_error(u8* file, u32 line); +#else + +#define Assert_Param(expr) ((void)0) + +#endif /* DEBUG --------------------------------------------------------------------------------------------*/ + + +#if _ADC + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F66242) || defined(USE_HT32F66246) + #include "ht32f65xxx_66xxx_adc.h" + #else + #include "ht32f5xxxx_adc.h" + #endif +#endif + +#if _AES && LIBCFG_AES + #include "ht32f5xxxx_aes.h" +#endif + +#if _BFTM + #include "ht32f5xxxx_bftm.h" +#endif + +#if _CAN && LIBCFG_CAN0 + #include "ht32f5xxxx_can.h" +#endif + +#if _CKCU + #include "ht32f5xxxx_ckcu.h" +#endif + +#if _CMP && LIBCFG_CMP + #include "ht32f5xxxx_cmp.h" +#endif + +#if _CRC && LIBCFG_CRC + #include "ht32f5xxxx_crc.h" +#endif + +#if _DAC && (LIBCFG_DAC0 || LIBCFG_DAC1) + #include "ht32f5xxxx_dac.h" +#endif + +#if _DAC && LIBCFG_DACDUAL16 + #include "ht32f5xxxx_dac_dual16.h" +#endif + +#if _DIV && LIBCFG_DIV + #include "ht32f5xxxx_div.h" +#endif + +#if _EBI && LIBCFG_EBI + #include "ht32f5xxxx_ebi.h" +#endif + +#if _EXTI + #include "ht32f5xxxx_exti.h" +#endif + +#if _FLASH + #include "ht32f5xxxx_flash.h" +#endif + +#if _GPIO + #include "ht32f5xxxx_gpio.h" +#endif + +#if _GPTM + #include "ht32f5xxxx_tm_type.h" + #include "ht32f5xxxx_tm.h" +#endif + +#if _I2C + #include "ht32f5xxxx_i2c.h" +#endif + +#if _I2S && LIBCFG_I2S + #include "ht32f5xxxx_i2s.h" +#endif + +#if _LCD && LIBCFG_LCD + #include "ht32f5xxxx_lcd.h" +#endif + +#if _LEDC && LIBCFG_LEDC + #include "ht32f5xxxx_ledc.h" +#endif + +#if _MCTM && LIBCFG_MCTM0 + #include "ht32f5xxxx_tm_type.h" + #include "ht32f5xxxx_tm.h" + #include "ht32f5xxxx_mctm.h" +#endif + +#if _MIDI && LIBCFG_MIDI + #include "ht32f5xxxx_midi.h" +#endif + +#if _OPA && LIBCFG_OPA + #if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) + #include "ht32f65xxx_66xxx_opa.h" + #else + #endif +#endif + +#if _PDMA && LIBCFG_PDMA + #include "ht32f5xxxx_pdma.h" +#endif + +#if _PWRCU + #include "ht32f5xxxx_pwrcu.h" +#endif + +#if _RSTCU + #include "ht32f5xxxx_rstcu.h" +#endif + +#if _RTC + #include "ht32f5xxxx_rtc.h" +#endif + +#if _SCI && LIBCFG_SCI0 + #include "ht32f5xxxx_sci.h" +#endif + +#if _SCTM + #include "ht32f5xxxx_tm_type.h" + #include "ht32f5xxxx_tm.h" +#endif + +#if _SLED && LIBCFG_SLED0 + #include "ht32f5xxxx_sled.h" +#endif + +#if _SPI + #include "ht32f5xxxx_spi.h" +#endif + +#if _TKEY && LIBCFG_TKEY + #include "ht32f5xxxx_tkey.h" +#endif + +#if _USART + #include "ht32f5xxxx_usart.h" +#endif + +#if _USB && LIBCFG_USBD + #include "ht32f5xxxx_usbd.h" +#endif + +#if _WDT + #include "ht32f5xxxx_wdt.h" +#endif + +#if _MISC + #include "ht32_cm0plus_misc.h" +#endif + +#if _SERIAL + #include "ht32_serial.h" +#endif + +#if _SWDIV + #include "ht32_div.h" +#endif + +#if _SWRAND + #include "ht32_rand.h" +#endif + +#if (_RETARGET) + #if defined (__GNUC__) + #undef getchar + #define getchar SERIAL_GetChar + #endif +#endif + +#ifdef HTCFG_TIME_IPSEL +#include "ht32_time.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_mctm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_mctm.h new file mode 100644 index 00000000000..cbea7b628ba --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_mctm.h @@ -0,0 +1,298 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_mctm.h + * @version $Rev:: 5258 $ + * @date $Date:: 2021-02-04 #$ + * @brief The header file of the MCTM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_MCTM_H +#define __HT32F5XXXX_MCTM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_tm.h" +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup MCTM + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Types MCTM exported types + * @{ + */ +/** + * @brief Enumeration of MCTM channel output idle state. + */ +/** + * @brief Definition of Break & DeadTime init structure. + */ +typedef struct +{ + u32 OSSRState; + u32 OSSIState; + u32 LockLevel; + u32 Break0; + u32 Break0Polarity; + u32 AutomaticOutput; + u8 DeadTime; + u8 BreakFilter; +} MCTM_CHBRKCTRInitTypeDef; + +typedef union +{ + struct + { + /* Definitions of CHBRKCTR */ + unsigned long Break0 :1; // BK0E + unsigned long Break0Polarity :1; // BK0P + #if (LIBCFG_TM_652XX_V1) + unsigned long Break1 :1; // BK1E + unsigned long Break1Polarity :1; // BK1E + #else + unsigned long :1; + unsigned long :1; + #endif + unsigned long :1; // CHMOE + unsigned long AutomaticOutput :1; // CHAOE + #if (LIBCFG_TM_65232) + unsigned long Break0FromCMP0 :1; // BK0CMP0 + unsigned long Break0FromCMP1 :1; // BK0CMP1 + #else + unsigned long :1; + unsigned long :1; + #endif + + #if (LIBCFG_TM_652XX_V1) + unsigned long Break0EventCount :2; // BK0FN + unsigned long Break0FDiv :2; // BK0FF + unsigned long Break1EventCount :2; // BK1FN + unsigned long Break1FDiv :2; // BK1FF + #else + unsigned long Break0Filter :4; // BK0F + unsigned long :4; + #endif + + unsigned long LockLevel :2; // LOCKLV + unsigned long DeglitchFilte :1; // GFSEL + unsigned long :1; + unsigned long OSSIState :1; // CHOSSI + unsigned long OSSRState :1; // CHOSSR + #if (LIBCFG_TM_65232) + unsigned long Break1FromCMP0 :1; // BK1CMP0 + unsigned long Break1FromCMP1 :1; // BK1CMP1 + #else + unsigned long :1; + unsigned long :1; + #endif + + unsigned long DeadTime :8; // CHDTG + } Bit; + u32 Reg; +} MCTM_CHBRKCTRTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Constants MCTM exported constants + * @{ + */ + +/** @defgroup MCTM_BKE Definitions of MCTM break control + * @{ + */ +#define MCTM_BREAK_ENABLE 0x00000001 /*!< Break enable */ +#define MCTM_BREAK_DISABLE 0x00000000 /*!< Break disable */ +/** + * @} + */ + +/** @defgroup MCTM_BKP Definitions of MCTM break polarity + * @{ + */ +#define MCTM_BREAK_POLARITY_LOW 0x00000000 /*!< Break input pin active low level */ +#define MCTM_BREAK_POLARITY_HIGH 0x00000002 /*!< Break input pin active high level */ +/** + * @} + */ + +/** @defgroup MCTM_CHMOE Definitions of MCTM main output enable function state + * @{ + */ +#define MCTM_CHMOE_DISABLE 0x00000000 /*!< main output disable */ +#define MCTM_CHMOE_ENABLE 0x00000010 /*!< Main output enable */ +/** + * @} + */ + +/** @defgroup MCTM_CHAOE Definitions of MCTM automatic output enable function state + * @{ + */ +#define MCTM_CHAOE_DISABLE 0x00000000 /*!< Automatic output enable function disable */ +#define MCTM_CHAOE_ENABLE 0x00000020 /*!< Automatic output enable function enable */ +/** + * @} + */ + +/** @defgroup MCTM_LOCK_LEVEL Definitions of MCTM lock level selection + * @{ + */ +#define MCTM_LOCK_LEVEL_OFF 0x00000000 /*!< Lock Off */ +#define MCTM_LOCK_LEVEL_1 0x00010000 /*!< Lock level 1 */ +#define MCTM_LOCK_LEVEL_2 0x00020000 /*!< Lock level 2 */ +#define MCTM_LOCK_LEVEL_3 0x00030000 /*!< Lock level 3 */ +/** + * @} + */ + +/** @defgroup MCTM_OSSI Definitions of Off-State Selection for Idle mode states + * @{ + */ +#define MCTM_OSSI_STATE_ENABLE 0x00100000 +#define MCTM_OSSI_STATE_DISABLE 0x00000000 +/** + * @} + */ + +/** @defgroup MCTM_OSSR Definitions of Off-State Selection for Run mode states + * @{ + */ +#define MCTM_OSSR_STATE_ENABLE 0x00200000 +#define MCTM_OSSR_STATE_DISABLE 0x00000000 +/** + * @} + */ + +/** @defgroup MCTM_Check_Parameter Check parameter + * @{ + */ + +/** + * @brief Used to check parameter of the MCTMx. + */ +#define IS_MCTM(x) (IS_MCTM0(x)) + +#if (LIBCFG_MCTM0) +#define IS_MCTM0(x) (x == HT_MCTM0) +#else +#define IS_MCTM0(x) (0) +#endif + +/** + * @brief Used to check parameter of the complementary output channel. + */ +#define IS_MCTM_COMPLEMENTARY_CH(x) (((x) == TM_CH_0) || ((x) == TM_CH_1) || \ + ((x) == TM_CH_2)) +/** + * @brief Used to check parameter of the COMUS. + */ +#define IS_MCTM_COMUS(x) ((x == MCTM_COMUS_STIOFF) || (x == MCTM_COMUS_STION)) +/** + * @brief Used to check parameter of the channel output idle state. + */ +#define IS_MCTM_OIS(x) ((x == MCTM_OIS_LOW) || (x == MCTM_OIS_HIGH)) +/** + * @brief Used to check value of MCTM break control state. + */ +#define IS_MCTM_BREAK_STATE(STATE) (((STATE) == MCTM_BREAK_ENABLE) || \ + ((STATE) == MCTM_BREAK_DISABLE)) +/** + * @brief Used to check value of MCTM break polarity. + */ +#define IS_MCTM_BREAK_POLARITY(POLARITY) (((POLARITY) == MCTM_BREAK_POLARITY_LOW) || \ + ((POLARITY) == MCTM_BREAK_POLARITY_HIGH)) +/** + * @brief Used to check value of MCTM automatic output enable control state. + */ +#define IS_MCTM_CHAOE_STATE(STATE) (((STATE) == MCTM_CHAOE_ENABLE) || \ + ((STATE) == MCTM_CHAOE_DISABLE)) +/** + * @brief Used to check value of MCTM lock level. + */ +#define IS_MCTM_LOCK_LEVEL(LEVEL) (((LEVEL) == MCTM_LOCK_LEVEL_OFF) || \ + ((LEVEL) == MCTM_LOCK_LEVEL_1) || \ + ((LEVEL) == MCTM_LOCK_LEVEL_2) || \ + ((LEVEL) == MCTM_LOCK_LEVEL_3)) +/** + * @brief Used to check value of MCTM OSSI state. + */ +#define IS_MCTM_OSSI_STATE(STATE) (((STATE) == MCTM_OSSI_STATE_ENABLE) || \ + ((STATE) == MCTM_OSSI_STATE_DISABLE)) +/** + * @brief Used to check value of MCTM OSSR state. + */ +#define IS_MCTM_OSSR_STATE(STATE) (((STATE) == MCTM_OSSR_STATE_ENABLE) || \ + ((STATE) == MCTM_OSSR_STATE_DISABLE)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Functions MCTM exported functions + * @{ + */ +void MCTM_ChNPolarityConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHP_Enum Pol); +void MCTM_ChannelNConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control); + +void MCTM_CHMOECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState); +void MCTM_CHBRKCTRConfig(HT_TM_TypeDef* MCTMx, MCTM_CHBRKCTRInitTypeDef *CHBRKCTRInit); +void MCTM_CHBRKCTRConfig2(HT_TM_TypeDef* MCTMx, MCTM_CHBRKCTRTypeDef *CHBRKCTRInit); +void MCTM_CHBRKCTRStructInit(MCTM_CHBRKCTRInitTypeDef* CHBRKCTRInit); +void MCTM_COMPRECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState); +void MCTM_COMUSConfig(HT_TM_TypeDef* MCTMx, MCTM_COMUS_Enum Sel); + +#if (LIBCFG_MCTM_UEV1DIS) +void MCTM_UpdateEventDisable(HT_TM_TypeDef* MCTMx, MCTM_UEV1DIS_Enum MCTM_UEV1x, FlagStatus NewState); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_midi.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_midi.h new file mode 100644 index 00000000000..08da134013e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_midi.h @@ -0,0 +1,404 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_midi.h + * @version $Rev:: 6684 $ + * @date $Date:: 2023-01-18 #$ + * @brief The header file of the MIDI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_MIDI_H +#define __HT32F5XXXX_MIDI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup MIDI + * @{ + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup MIDI_Exported_Types MIDI exported types + * @{ + */ + +/** + * @brief Enumeration of MIDI CTRL MCUCHEN3. + */ +typedef enum +{ + MCUCHEN3_OFF = DISABLE, + MCUCHEN3_ON = ENABLE, +} MIDI_CTRL_MCUCHEN3_Enum; +/** + * @brief Enumeration of MIDI CTRL MCUCHEN2. + */ +typedef enum +{ + MCUCHEN2_OFF = DISABLE, + MCUCHEN2_ON = ENABLE, +} MIDI_CTRL_MCUCHEN2_Enum; +/** + * @brief Enumeration of MIDI CTRL MCUCHEN1. + */ +typedef enum +{ + MCUCHEN1_OFF = DISABLE, + MCUCHEN1_ON = ENABLE, +} MIDI_CTRL_MCUCHEN1_Enum; +/** + * @brief Enumeration of MIDI CTRL MCUCHEN0. + */ +typedef enum +{ + MCUCHEN0_OFF = DISABLE, + MCUCHEN0_ON = ENABLE, +} MIDI_CTRL_MCUCHEN0_Enum; +/** + * @brief Enumeration of MIDI CTRL MUSIC. + */ +typedef enum +{ + MUSICEN_OFF = DISABLE, + MUSICEN_ON = ENABLE, +} MIDI_CTRL_MUSICEN_Enum; +/** + * @brief Enumeration of MIDI SPI RDEN. + */ +typedef enum +{ + SPIRDEN_OFF = DISABLE, + SPIRDEN_ON = ENABLE, +} MIDI_CTRL_SPIRDEN_Enum; +/** + * @brief Enumeration of MIDI SPI DISLOOP. + */ +typedef enum +{ + SPIDISLOOP_OFF = DISABLE, + SPIDISLOOP_ON = ENABLE, +} MIDI_CTRL_SPIDISLOOP_Enum; +/** + * @brief Enumeration of MIDI CTRL CHS. + */ +typedef enum +{ + CHS16 = 0, /*!< Select 16-Channel */ + CHS20, /*!< Select 20-Channel */ + CHS24, /*!< Select 24-Channel */ + CHS28, /*!< Select 28-Channel */ + CHS32, /*!< Select 32-Channel */ +} MIDI_CTRL_CHS_Enum; + +/** + * @brief Enumeration of MIDI Note. + */ +typedef enum +{ + BL0 = 0, + BL1, + BL2, + BL3, + BL4, + BL5, + BL6, + BL7, + BL8, + BL9, + BL10, + BL11, +} MIDI_FREQ_BL_Enum; + +/** + * @brief Enumeration of MIDI VOL AR. + */ +typedef enum +{ + ENV_RELEASE = RESET, + ENV_ATTACK = SET, +} MIDI_VOL_AR_Enum; +/** + * @brief Enumeration of MIDI VOL ENV. + */ +typedef enum +{ + ENV_TYPE0 = 0, + ENV_TYPE1, + ENV_TYPE2, + ENV_NO, +} MIDI_VOL_ENV_Enum; + +/** + * @brief Enumeration of MIDI RE_NUM WBS. + */ +typedef enum +{ + WBS8 = 0, /*!< WBS 8-bit */ + WBS12, /*!< WBS 12-bit */ + WBS16, /*!< WBS 16-bit */ +} MIDI_RENUM_WBS_Enum; + +/** + * @brief Enumeration of MIDI CHAN ST. + */ +typedef enum +{ + ST_OFF = DISABLE, + ST_ON = ENABLE, +} MIDI_CHAN_ST_Enum; +/** + * @brief Enumeration of MIDI CHAN VM. + */ +typedef enum +{ + VM_OFF = DISABLE, + VM_ON = ENABLE, +} MIDI_CHAN_VM_Enum; +/** + * @brief Enumeration of MIDI CHAN FR. + */ +typedef enum +{ + FR_OFF = DISABLE, + FR_ON = ENABLE, +} MIDI_CHAN_FR_Enum; +/** + * @brief Enumeration of MIDI CHAN CHx. + */ +typedef enum +{ + MIDI_CHx0 = 0, + MIDI_CHx1, + MIDI_CHx2, + MIDI_CHx3, + MIDI_CHx4, + MIDI_CHx5, + MIDI_CHx6, + MIDI_CHx7, + MIDI_CHx8, + MIDI_CHx9, + MIDI_CHx10, + MIDI_CHx11, + MIDI_CHx12, + MIDI_CHx13, + MIDI_CHx14, + MIDI_CHx15, + MIDI_CHx16, + MIDI_CHx17, + MIDI_CHx18, + MIDI_CHx19, + MIDI_CHx20, + MIDI_CHx21, + MIDI_CHx22, + MIDI_CHx23, + MIDI_CHx24, + MIDI_CHx25, + MIDI_CHx26, + MIDI_CHx27, + MIDI_CHx28, + MIDI_CHx29, + MIDI_CHx30, + MIDI_CHx31, +} MIDI_CHAN_CHx_Enum; + +typedef struct +{ + u8 MIDI_CTRL_DACDS; + ControlStatus MIDI_CTRL_MUSICEN; + ControlStatus MIDI_CTRL_SPIDISLOOP; + u8 MIDI_CTRL_CHS; + MIDI_FREQ_BL_Enum MIDI_FREQ_BL; + u16 MIDI_FREQ_FR; + MIDI_VOL_AR_Enum MIDI_VOL_AR; + MIDI_VOL_ENV_Enum MIDI_VOL_ENV; + u16 MIDI_VOL_VL; + u16 MIDI_VOL_VR; + u32 MIDI_STADDR; + MIDI_RENUM_WBS_Enum MIDI_RENUM_WBS; + u16 MIDI_RENUM_RE; + u32 MIDI_ENDADDR; + ControlStatus MIDI_CHAN_ST; + ControlStatus MIDI_CHAN_VM; + ControlStatus MIDI_CHAN_FR; + u8 MIDI_CHAN_CHx; +} MIDI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup MIDI_Exported_Constants MIDI exported constants + * @{ + */ +/* Definitions of MIDI_FLAG */ +#define MIDI_FLAG_INTF 0x0001 + +/* Definitions of MIDI_INT */ +#define MIDI_INT_INTEN 0x0001 +#define MIDI_INT_MIDII_DMAEN 0x0002 +#define MIDI_INT_MIDIO_DMAEN 0x0004 + +/* Definitions of MIDI_VOL */ +#define VOL_MAX 0 +#define VOL_MID 0x1FF +#define VOL_380 0x380 +#define VOL_MIN 0x3FF +#define VOL_MUTE VOL_MIN + +//#define IS_MIDI(x) ((MIDI == HT_MIDI)) +#define IS_MIDI(x) ((x == HT_MIDI)) + +#define IS_MIDI_INT(x) (((x & 0xFFFFFFF8) == 0x0) && (x != 0)) +#define IS_MIDI_FLAG(x) (x == MIDI_FLAG_INTF) +#define IS_MIDI_FLAG_CLEAR(x) (((x & 0xFFFFFFFE) == 0) && (x != 0)) + +#define IS_MIDI_CTRL_MCUCHEN3(x) ((x == MCUCHEN3_OFF) || (x == MCUCHEN3_ON)) +#define IS_MIDI_CTRL_MCUCHEN2(x) ((x == MCUCHEN2_OFF) || (x == MCUCHEN2_ON)) +#define IS_MIDI_CTRL_MCUCHEN1(x) ((x == MCUCHEN1_OFF) || (x == MCUCHEN1_ON)) +#define IS_MIDI_CTRL_MCUCHEN0(x) ((x == MCUCHEN0_OFF) || (x == MCUCHEN0_ON)) +#define IS_MIDI_CTRL_DACDS(x) (x < 8) +#define IS_MIDI_CTRL_MUSICEN(x) ((x == MUSICEN_OFF) || (x == MUSICEN_ON)) +#define IS_MIDI_CTRL_SPIRDEN(x) ((x == SPIRDEN_OFF) || (x == SPIRDEN_ON)) +#define IS_MIDI_CTRL_SPIDISLOOP(x) ((x == SPIDISLOOP_OFF) || (x == SPIDISLOOP_ON)) +#define IS_MIDI_CTRL_CHS(x) (x < 8) + +#define IS_MIDI_FREQ_BL(x) (x < 12) +#define IS_MIDI_FREQ_FR(x) (x < 0xFFF) + +#define IS_MIDI_VOL_AR(x) (ENV_ATTACK || ENV_RELEASE) +#define IS_MIDI_VOL_ENV(x) (ENV_TYPE0 || ENV_TYPE1 || ENV_TYPE2 || ENV_NO) +#define IS_MIDI_VOL_VL(x) (x < 0x3FF) +#define IS_MIDI_VOL_VR(x) (x < 0x3FF) + +#define IS_MIDI_STADDR(x) (x < 0x7FFFF) + +#define IS_MIDI_RENUM_WBS(x) ((x == WBS8) || (x == WBS12) || (x == WBS16)) +#define IS_MIDI_RENUM_RE(x) (x < 0x7FFF) + +#define IS_MIDI_ENDADDR(x) (x < 0xFFFFFF) + +#define IS_MIDI_CHAN_ST(x) ((x == ST_OFF) || (x == ST_ON)) +#define IS_MIDI_CHAN_VM(x) ((x == VM_OFF) || (x == VM_ON)) +#define IS_MIDI_CHAN_FR(x) ((x == FR_OFF) || (x == FR_ON)) +#define IS_MIDI_CHAN_CHx(x) (x < 32) + +#define IS_MIDI_MCUCHx11_BH(x) (x < 0xFFFF) +#define IS_MIDI_MCUCHx11_BL(x) (x < 0xFFFF) + +#define IS_MIDI_MCUCHx12_CH(x) (x < 0xFFFF) +#define IS_MIDI_MCUCHx12_CL(x) (x < 0xFFFF) + +#define IS_MIDI_MCUCHx13_DH(x) (x < 0xFFFF) +#define IS_MIDI_MCUCHx13_DL(x) (x < 0xFFFF) + +#define IS_MIDI_MCUCHx14_EH(x) (x < 0xFFFF) +#define IS_MIDI_MCUCHx14_EL(x) (x < 0xFFFF) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup MIDI_Exported_Functions MIDI exported functions + * @{ + */ +void MIDI_DeInit(void); +void MIDI_Init(HT_MIDI_TypeDef* MIDIx, MIDI_InitTypeDef* MIDI_InitStruct); +void MIDI_StructInit(MIDI_InitTypeDef* MIDI_InitStruct); +void MIDI_IntConfig(HT_MIDI_TypeDef* MIDIx, u32 MIDI_Int, ControlStatus NewState); +FlagStatus MIDI_GetFlagStatus(HT_MIDI_TypeDef* MIDIx, u32 MIDI_Flag); +void MIDI_ClearFlag(HT_MIDI_TypeDef* MIDIx, u32 MIDI_Flag); + +void MIDI_CTRL(HT_MIDI_TypeDef* MIDIx, + MIDI_CTRL_MCUCHEN3_Enum MCUCHEN3, MIDI_CTRL_MCUCHEN2_Enum MCUCHEN2, + MIDI_CTRL_MCUCHEN1_Enum MCUCHEN1, MIDI_CTRL_MCUCHEN0_Enum MCUCHEN0, + u8 DACDS, + MIDI_CTRL_MUSICEN_Enum MUSICEN, + MIDI_CTRL_SPIRDEN_Enum SPIRDEN, MIDI_CTRL_SPIDISLOOP_Enum SPIDISLOOP, + MIDI_CTRL_CHS_Enum CHS); +void MIDI_FREQ(HT_MIDI_TypeDef* MIDIx, MIDI_FREQ_BL_Enum BL, u16 FR); +void MIDI_VOL(HT_MIDI_TypeDef* MIDIx, MIDI_VOL_AR_Enum A_R, MIDI_VOL_ENV_Enum ENV, u16 VL, u16 VR); +void MIDI_STADDR(HT_MIDI_TypeDef* MIDIx, u32 ST_ADDR); +void MIDI_RENUM(HT_MIDI_TypeDef* MIDIx, MIDI_RENUM_WBS_Enum WBS, u16 RE); +void MIDI_ENDADDR(HT_MIDI_TypeDef* MIDIx, u32 END_ADDR); +void MIDI_CHAN(HT_MIDI_TypeDef* MIDIx, MIDI_CHAN_ST_Enum ST, MIDI_CHAN_VM_Enum VM, MIDI_CHAN_FR_Enum FR, u8 CHx); + +void MIDI_MCUCH0(HT_MIDI_TypeDef* MIDIx, u16 CH0B, u16 CH0A); +void MIDI_MCUCH1(HT_MIDI_TypeDef* MIDIx, u16 CH1B, u16 CH1A); +void MIDI_MCUCH2(HT_MIDI_TypeDef* MIDIx, u16 CH2B, u16 CH2A); +void MIDI_MCUCH3(HT_MIDI_TypeDef* MIDIx, u16 CH3B, u16 CH3A); + +void MIDI_FREQ_BL(HT_MIDI_TypeDef* MIDIx, MIDI_FREQ_BL_Enum BL); +void MIDI_FREQ_FR(HT_MIDI_TypeDef* MIDIx, u16 FR); +void MIDI_VOL_AR(HT_MIDI_TypeDef* MIDIx, MIDI_VOL_AR_Enum A_R); +void MIDI_VOL_ENV(HT_MIDI_TypeDef* MIDIx, MIDI_VOL_ENV_Enum ENV); +void MIDI_VOL_VL(HT_MIDI_TypeDef* MIDIx, u16 VL); +void MIDI_VOL_VR(HT_MIDI_TypeDef* MIDIx, u16 VR); +void MIDI_RENUM_WBS(HT_MIDI_TypeDef* MIDIx, MIDI_RENUM_WBS_Enum WBS); +void MIDI_RENUM_RE(HT_MIDI_TypeDef* MIDIx, u16 RE); +void MIDI_CHAN_STCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CHAN_VMCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CHAN_FRCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CHAN_CHx(HT_MIDI_TypeDef* MIDIx, u8 CHx); +void MIDI_MCUCH0_CH0B(HT_MIDI_TypeDef* MIDIx, u16 CH0B); +void MIDI_MCUCH0_CH0A(HT_MIDI_TypeDef* MIDIx, u16 CH0A); +void MIDI_MCUCH1_CH1B(HT_MIDI_TypeDef* MIDIx, u16 CH1B); +void MIDI_MCUCH1_CH1A(HT_MIDI_TypeDef* MIDIx, u16 CH1A); +void MIDI_MCUCH2_CH2B(HT_MIDI_TypeDef* MIDIx, u16 CH2B); +void MIDI_MCUCH2_CH2A(HT_MIDI_TypeDef* MIDIx, u16 CH2A); +void MIDI_MCUCH3_CH3B(HT_MIDI_TypeDef* MIDIx, u16 CH3B); +void MIDI_MCUCH3_CH3A(HT_MIDI_TypeDef* MIDIx, u16 CH3A); +void MIDI_CTRL_MCUCHEN3(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CTRL_MCUCHEN2(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CTRL_MCUCHEN1(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CTRL_MCUCHEN0(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CTRL_DACDS(HT_MIDI_TypeDef* MIDIx, u8 DACDS); +void MIDI_CTRL_MUSICENCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CTRL_SPIRDENCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CTRL_SPIDISLOOPCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState); +void MIDI_CTRL_CHS(HT_MIDI_TypeDef* MIDIx, u8 CHS); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pdma.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pdma.h new file mode 100644 index 00000000000..1dbea97ba3f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pdma.h @@ -0,0 +1,377 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_pdma.h + * @version $Rev:: 7319 $ + * @date $Date:: 2023-10-28 #$ + * @brief The header file of the PDMA library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_PDMA_H +#define __HT32F5XXXX_PDMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup PDMA + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Types PDMA exported types + * @{ + */ + +/** + * @brief Definition of PDMA channel Init Structure + */ +typedef struct +{ + u32 PDMACH_SrcAddr; /*!< source address */ + u32 PDMACH_DstAddr; /*!< destination address */ + u16 PDMACH_BlkCnt; /*!< number of blocks for a PDMA transfer (1 ~ 65,535) */ + u8 PDMACH_BlkLen; /*!< number of data for a block (1 ~ 255) */ + u8 PDMACH_DataSize; /*!< number of bits for a data (8-bit/16-bit/32-bit) */ + u16 PDMACH_Priority; /*!< software priority for a PDMA transfer (L/M/H/VH) */ + u16 PDMACH_AdrMod; /*!< address mode (LIN_INC/LIN_DEC/CIR_INC/CIR_DEC/FIX/AUTO_RELOAD) */ +} PDMACH_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Constants PDMA exported constants + * @{ + */ +/* priority */ +#define L_PRIO (0) /*!< low priority */ +#define M_PRIO (1UL << 8) /*!< medium priority */ +#define H_PRIO (2UL << 8) /*!< high priority */ +#define VH_PRIO (3UL << 8) /*!< very high priority */ + +#define IS_PDMA_PRIO(PRIO) ((PRIO >> 8) < 4) /*!< check channel priority parameter */ + +/* address mode */ +#define AUTO_RELOAD (1UL << 11) /*!< enable auto reload */ +#define ADR_FIX (1UL << 10) /*!< enable address fix */ + +#define SRC_ADR_LIN_INC (0) /*!< source address linear increment */ +#define SRC_ADR_LIN_DEC (1UL << 6) /*!< source address linear decrement */ +#define SRC_ADR_CIR_INC (2UL << 6) /*!< source address circular increment */ +#define SRC_ADR_CIR_DEC (3UL << 6) /*!< source address circular decrement */ +#define SRC_ADR_FIX (ADR_FIX | SRC_ADR_CIR_INC) /*!< source address fix */ + +#define DST_ADR_LIN_INC (0) /*!< destination address linear increment */ +#define DST_ADR_LIN_DEC (1UL << 4) /*!< destination address linear decrement */ +#define DST_ADR_CIR_INC (2UL << 4) /*!< destination address circular increment */ +#define DST_ADR_CIR_DEC (3UL << 4) /*!< destination address circular decrement */ +#define DST_ADR_FIX (ADR_FIX | DST_ADR_CIR_INC) /*!< destination address fix */ + +#define IS_PDMA_ADR_MOD(MOD) ((MOD & 0xFFFFF30F) == 0) /*!< check address mode parameters */ + +/* transfer size */ +#define IS_PDMA_BLK_CNT(CNT) ((CNT > 0) && (CNT <= 65535)) /*!< block count per transfer */ +#define IS_PDMA_BLK_LEN(LEN) ((LEN > 0) && (LEN <= 255)) /*!< block size per block count */ + +/* transfer width */ +#define WIDTH_8BIT (0) /*!< 8-bit transfer width */ +#define WIDTH_16BIT (1UL << 2) /*!< 16-bit transfer width */ +#define WIDTH_32BIT (2UL << 2) /*!< 32-bit transfer width */ + +#define IS_PDMA_WIDTH(WIDTH) ((WIDTH >> 2) < 3) /*!< check transfer width parameter */ + +/* channel number */ +#define PDMA_CH0 (0) /*!< channel 0 number */ +#define PDMA_CH1 (1UL) /*!< channel 1 number */ +#define PDMA_CH2 (2UL) /*!< channel 2 number */ +#define PDMA_CH3 (3UL) /*!< channel 3 number */ +#define PDMA_CH4 (4UL) /*!< channel 4 number */ +#define PDMA_CH5 (5UL) /*!< channel 5 number */ + +#define IS_PDMA_CH(CH) (CH < 6) /*!< check channel number parameter */ + +#define PDMA_ADC0 PDMA_CH0 /*!< ADC PDMA channel number */ +#if (LIBCFG_ADC1) +#define PDMA_ADC1 PDMA_CH1 /*!< ADC PDMA channel number */ +#endif +#define PDMA_ADC PDMA_ADC0 + +#if(LIBCFG_DAC0) +#define PDMA_DAC0_CH0 PDMA_CH1 /*!< DAC0 CH0 PDMA channel number */ +#define PDMA_DAC0_CH1 PDMA_CH3 /*!< DAC0 CH1 PDMA channel number */ +#endif + +#if(LIBCFG_DAC1) +#define PDMA_DAC1_CH0 PDMA_CH4 /*!< DAC1 CH0 PDMA channel number */ +#define PDMA_DAC1_CH1 PDMA_CH5 /*!< DAC1 CH1 PDMA channel number */ +#endif + +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) || defined(USE_HT32F0006) || defined(USE_HT32F61244_45) +#define PDMA_SPI0_RX PDMA_CH4 /*!< SPI0_RX PDMA channel number */ +#define PDMA_SPI0_TX PDMA_CH5 /*!< SPI0_TX PDMA channel number */ +#elif defined(USE_HT32F57342_52) || defined(USE_HT32F52357_67) || defined(USE_HT32F67041_51) || defined(USE_HT32F52234_44) +#define PDMA_SPI0_RX PDMA_CH2 /*!< SPI0_RX PDMA channel number */ +#define PDMA_SPI0_TX PDMA_CH3 /*!< SPI0_TX PDMA channel number */ +#else +#define PDMA_SPI0_RX PDMA_CH0 /*!< SPI0_RX PDMA channel number */ +#define PDMA_SPI0_TX PDMA_CH1 /*!< SPI0_TX PDMA channel number */ +#endif + +#if (LIBCFG_SPI1) +#define PDMA_SPI1_RX PDMA_CH4 /*!< SPI1_RX PDMA channel number */ +#define PDMA_SPI1_TX PDMA_CH5 /*!< SPI1_TX PDMA channel number */ +#endif + +#if (LIBCFG_QSPI) +#define PDMA_QSPI_TX PDMA_CH1 /*!< QSPI_TX PDMA channel number */ +#define PDMA_QSPI_RX PDMA_CH0 /*!< QSPI_RX PDMA channel number */ +#endif + +#define PDMA_USART0_RX PDMA_CH0 /*!< USART0_RX PDMA channel number */ +#define PDMA_USART0_TX PDMA_CH1 /*!< USART0_TX PDMA channel number */ +#if (LIBCFG_USART1) +#define PDMA_USART1_RX PDMA_CH2 /*!< USART1_RX PDMA channel number */ +#define PDMA_USART1_TX PDMA_CH3 /*!< USART1_TX PDMA channel number */ +#endif + +#if defined(USE_HT32F52243_53) || defined(USE_HT32F52357_67) || defined(USE_HT32F54243_53) +#define PDMA_UART2_RX PDMA_CH0 /*!< UART2_RX PDMA channel number */ +#define PDMA_UART2_TX PDMA_CH1 /*!< UART2_TX PDMA channel number */ +#define PDMA_UART3_RX PDMA_CH4 /*!< UART3_RX PDMA channel number */ +#define PDMA_UART3_TX PDMA_CH5 /*!< UART3_TX PDMA channel number */ +#endif + +#define PDMA_UART0_RX PDMA_CH2 /*!< UART0_RX PDMA channel number */ +#define PDMA_UART0_TX PDMA_CH3 /*!< UART0_TX PDMA channel number */ +#if (LIBCFG_UART1) +#define PDMA_UART1_RX PDMA_CH4 /*!< UART1_RX PDMA channel number */ +#define PDMA_UART1_TX PDMA_CH5 /*!< UART1_TX PDMA channel number */ +#endif + +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) +#define PDMA_I2C0_RX PDMA_CH2 /*!< I2C0_RX PDMA channel number */ +#define PDMA_I2C0_TX PDMA_CH3 /*!< I2C0_TX PDMA channel number */ +#elif defined(USE_HT32F52234_44) +#define PDMA_I2C0_RX PDMA_CH2 /*!< I2C0_RX PDMA channel number */ +#define PDMA_I2C0_TX PDMA_CH0 /*!< I2C0_TX PDMA channel number */ +#else +#define PDMA_I2C0_RX PDMA_CH2 /*!< I2C0_RX PDMA channel number */ +#define PDMA_I2C0_TX PDMA_CH4 /*!< I2C0_TX PDMA channel number */ +#endif +#if (LIBCFG_I2C1) +#if defined(USE_HT32F52234_44) +#define PDMA_I2C1_RX PDMA_CH3 /*!< I2C1_RX PDMA channel number */ +#define PDMA_I2C1_TX PDMA_CH1 /*!< I2C1_TX PDMA channel number */ +#else +#define PDMA_I2C1_RX PDMA_CH3 /*!< I2C1_RX PDMA channel number */ +#define PDMA_I2C1_TX PDMA_CH5 /*!< I2C1_TX PDMA channel number */ +#endif +#endif + +#if defined(USE_HT32F52243_53) || defined(USE_HT32F54243_53) +#define PDMA_I2C2_RX PDMA_CH0 /*!< I2C2_RX PDMA channel number */ +#define PDMA_I2C2_TX PDMA_CH1 /*!< I2C2_TX PDMA channel number */ +#elif defined(USE_HT32F52234_44) +#define PDMA_I2C2_RX PDMA_CH4 /*!< I2C2_RX PDMA channel number */ +#define PDMA_I2C2_TX PDMA_CH5 /*!< I2C2_TX PDMA channel number */ +#endif + +#if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) || defined(USE_HT32F57342_52) || defined(USE_HT32F52357_67) +#define PDMA_SCI0_TX PDMA_CH5 /*!< SCI0_TX PDMA channel number */ +#define PDMA_SCI0_RX PDMA_CH4 /*!< SCI0_RX PDMA channel number */ +#define PDMA_SCI1_TX PDMA_CH3 /*!< SCI1_TX PDMA channel number */ +#define PDMA_SCI1_RX PDMA_CH2 /*!< SCI1_RX PDMA channel number */ +#endif + +#if (LIBCFG_I2S) +#define PDMA_I2S_TX PDMA_CH2 /*!< I2S_TX PDMA channel number */ +#define PDMA_I2S_RX PDMA_CH1 /*!< I2S_RX PDMA channel number */ +#endif + +#if (LIBCFG_MCTM0) +#define PDMA_MCTM0_CH0 PDMA_CH0 /*!< MCTM0_CH0 PDMA channel number */ +#define PDMA_MCTM0_TRIG PDMA_CH1 /*!< MCTM0_TRIG PDMA channel number */ +#define PDMA_MCTM0_CH1 PDMA_CH2 /*!< MCTM0_CH1 PDMA channel number */ +#define PDMA_MCTM0_CH2 PDMA_CH3 /*!< MCTM0_CH2 PDMA channel number */ +#define PDMA_MCTM0_CH3 PDMA_CH4 /*!< MCTM0_CH3 PDMA channel number */ +#define PDMA_MCTM0_UEV2 PDMA_CH4 /*!< MCTM0_UEV2 PDMA channel number */ +#define PDMA_MCTM0_UEV1 PDMA_CH5 /*!< MCTM0_UEV1 PDMA channel number */ +#endif + +#if (LIBCFG_NO_GPTM0) +#else +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) +#define PDMA_GPTM0_CH1 PDMA_CH0 /*!< GPTM0_CH1 PDMA channel number */ +#define PDMA_GPTM0_CH2 PDMA_CH1 /*!< GPTM0_CH2 PDMA channel number */ +#define PDMA_GPTM0_CH0 PDMA_CH2 /*!< GPTM0_CH0 PDMA channel number */ +#define PDMA_GPTM0_CH3 PDMA_CH3 /*!< GPTM0_CH3 PDMA channel number */ +#define PDMA_GPTM0_UEV PDMA_CH4 /*!< GPTM0_UEV PDMA channel number */ +#define PDMA_GPTM0_TRIG PDMA_CH5 /*!< GPTM0_TRIG PDMA channel number */ +#else +#define PDMA_GPTM0_CH1 PDMA_CH0 /*!< GPTM0_CH1 PDMA channel number */ +#define PDMA_GPTM0_CH3 PDMA_CH0 /*!< GPTM0_CH3 PDMA channel number */ +#define PDMA_GPTM0_CH2 PDMA_CH1 /*!< GPTM0_CH2 PDMA channel number */ +#define PDMA_GPTM0_UEV PDMA_CH1 /*!< GPTM0_UEV PDMA channel number */ +#define PDMA_GPTM0_CH0 PDMA_CH2 /*!< GPTM0_CH0 PDMA channel number */ +#define PDMA_GPTM0_TRIG PDMA_CH2 /*!< GPTM0_TRIG PDMA channel number */ +#endif +#endif + +#if (LIBCFG_GPTM1) +#define PDMA_GPTM1_CH0 PDMA_CH3 /*!< GPTM1_CH0 PDMA channel number */ +#define PDMA_GPTM1_CH3 PDMA_CH3 /*!< GPTM1_CH3 PDMA channel number */ +#define PDMA_GPTM1_CH1 PDMA_CH4 /*!< GPTM1_CH1 PDMA channel number */ +#define PDMA_GPTM1_UEV PDMA_CH4 /*!< GPTM1_UEV PDMA channel number */ +#define PDMA_GPTM1_CH2 PDMA_CH5 /*!< GPTM1_CH2 PDMA channel number */ +#define PDMA_GPTM1_TRIG PDMA_CH5 /*!< GPTM1_TRIG PDMA channel number */ +#endif + +#if defined(USE_HT32F65230_40) || defined(USE_HT32F65232) +#define PDMA_SCTM0_CH0 PDMA_CH0 /*!< SCTM0_CH0 PDMA channel number */ +#define PDMA_SCTM0_CH1 PDMA_CH1 /*!< SCTM0_CH1 PDMA channel number */ +#define PDMA_SCTM1_CH0 PDMA_CH2 /*!< SCTM1_CH0 PDMA channel number */ +#define PDMA_SCTM1_CH1 PDMA_CH3 /*!< SCTM1_CH1 PDMA channel number */ +#define PDMA_SCTM2_CH0 PDMA_CH4 /*!< SCTM2_CH0 PDMA channel number */ +#define PDMA_SCTM2_CH1 PDMA_CH5 /*!< SCTM2_CH1 PDMA channel number */ +#define PDMA_SCTM3_CH0 PDMA_CH4 /*!< SCTM3_CH0 PDMA channel number */ +#define PDMA_SCTM3_CH1 PDMA_CH5 /*!< SCTM3_CH1 PDMA channel number */ +#endif + +#if (LIBCFG_PWM0) +#if defined(USE_HT32F52234_44) +#define PDMA_PWM0_CH0 PDMA_CH5 /*!< PWM0_CH0 PDMA channel number */ +#define PDMA_PWM0_CH1 PDMA_CH3 /*!< PWM0_CH1 PDMA channel number */ +#define PDMA_PWM0_CH2 PDMA_CH4 /*!< PWM0_CH2 PDMA channel number */ +#define PDMA_PWM0_CH3 PDMA_CH3 /*!< PWM0_CH3 PDMA channel number */ +#define PDMA_PWM0_TRIG PDMA_CH5 /*!< PWM0_TRIG PDMA channel number */ +#define PDMA_PWM0_UEV PDMA_CH4 /*!< PWM0_UEV PDMA channel number */ +#else +#define PDMA_PWM0_CH0 PDMA_CH2 /*!< PWM0_CH0 PDMA channel number */ +#define PDMA_PWM0_CH1 PDMA_CH0 /*!< PWM0_CH1 PDMA channel number */ +#define PDMA_PWM0_CH2 PDMA_CH1 /*!< PWM0_CH2 PDMA channel number */ +#define PDMA_PWM0_CH3 PDMA_CH0 /*!< PWM0_CH3 PDMA channel number */ +#define PDMA_PWM0_TRIG PDMA_CH2 /*!< PWM0_TRIG PDMA channel number */ +#define PDMA_PWM0_UEV PDMA_CH1 /*!< PWM0_UEV PDMA channel number */ +#endif +#endif + +#if (LIBCFG_PWM1) +#define PDMA_PWM1_CH0 PDMA_CH5 /*!< PWM1_CH0 PDMA channel number */ +#define PDMA_PWM1_CH1 PDMA_CH3 /*!< PWM1_CH1 PDMA channel number */ +#define PDMA_PWM1_CH2 PDMA_CH4 /*!< PWM1_CH2 PDMA channel number */ +#define PDMA_PWM1_CH3 PDMA_CH3 /*!< PWM1_CH3 PDMA channel number */ +#define PDMA_PWM1_TRIG PDMA_CH5 /*!< PWM1_TRIG PDMA channel number */ +#define PDMA_PWM1_UEV PDMA_CH4 /*!< PWM1_UEV PDMA channel number */ +#endif + +#if (LIBCFG_PWM2) +#define PDMA_PWM2_CH0 PDMA_CH5 /*!< PWM2_CH0 PDMA channel number */ +#define PDMA_PWM2_CH1 PDMA_CH3 /*!< PWM2_CH1 PDMA channel number */ +#define PDMA_PWM2_CH2 PDMA_CH4 /*!< PWM2_CH2 PDMA channel number */ +#define PDMA_PWM2_CH3 PDMA_CH3 /*!< PWM2_CH3 PDMA channel number */ +#define PDMA_PWM2_TRIG PDMA_CH5 /*!< PWM2_TRIG PDMA channel number */ +#define PDMA_PWM2_UEV PDMA_CH4 /*!< PWM2_UEV PDMA channel number */ +#endif + +#if (LIBCFG_SLED0) +#define PDMA_SLED0 PDMA_CH0 /*!< SLED0 PDMA channel number */ +#endif +#if (LIBCFG_SLED1) +#define PDMA_SLED1 PDMA_CH1 /*!< SLED1 PDMA channel number */ +#endif + +#if (LIBCFG_AES) +#define PDMA_AES_OUT PDMA_CH4 /*!< AES_OUT PDMA channel number */ +#define PDMA_AES_IN PDMA_CH5 /*!< AES_IN PDMA channel number */ +#endif + +#if (LIBCFG_MIDI) +#define PDMA_MIDI_IN PDMA_CH3 /*!< MIDI_IN PDMA channel number */ +#define PDMA_MIDI_OUT PDMA_CH4 /*!< MIDI_OUT PDMA channel number */ +#endif + +/* flag */ +#define PDMA_FLAG_GE (1UL << 0) /*!< PDMA channel global event flag */ +#define PDMA_FLAG_BE (1UL << 1) /*!< PDMA channel block end flag */ +#define PDMA_FLAG_HT (1UL << 2) /*!< PDMA channel half transfer flag */ +#define PDMA_FLAG_TC (1UL << 3) /*!< PDMA channel transfer complete flag */ +#define PDMA_FLAG_TE (1UL << 4) /*!< PDMA channel transfer error flag */ + +#define IS_PDMA_FLAG(FLAG) (((FLAG & 0xFFFFFFE0) == 0) && (FLAG != 0)) +#define IS_PDMA_CLEAR_FLAG(FLAG) (((FLAG & 0xFFFFFFE0) == 0) && (FLAG != 0)) + +/* interrupt */ +#define PDMA_INT_GE (1UL << 0) /*!< PDMA channel global event interrupt */ +#define PDMA_INT_BE (1UL << 1) /*!< PDMA channel block end interrupt */ +#define PDMA_INT_HT (1UL << 2) /*!< PDMA channel half transfer interrupt */ +#define PDMA_INT_TC (1UL << 3) /*!< PDMA channel transfer complete interrupt */ +#define PDMA_INT_TE (1UL << 4) /*!< PDMA channel transfer error interrupt */ + +#define IS_PDMA_INT(INT) (((INT & 0xFFFFFFE0) == 0) && (INT != 0)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Functions PDMA exported functions + * @{ + */ +void PDMA_DeInit(void); +void PDMA_Config(u32 PDMA_CHn, PDMACH_InitTypeDef *PDMACH_InitStruct); +void PDMA_AddrConfig(u32 PDMA_CHn, u32 SrcAddr, u32 DstAddr); +void PDMA_SrcAddrConfig(u32 PDMA_CHn, u32 SrcAddr); +void PDMA_DstAddrConfig(u32 PDMA_CHn, u32 DstAddr); +void PDMA_TranSizeConfig(u32 PDMA_CHn, u16 BlkCnt, u16 BlkLen); +void PDMA_EnaCmd(u32 PDMA_CHn, ControlStatus NewState); +void PDMA_SwTrigCmd(u32 PDMA_CHn, ControlStatus NewState); + +void PDMA_IntConfig(u32 PDMA_CHn, u32 PDMA_INT_x, ControlStatus NewState); +FlagStatus PDMA_GetFlagStatus(u32 PDMA_CHn, u32 PDMA_FLAG_x); +void PDMA_ClearFlag(u32 PDMA_CHn, u32 PDMA_FLAG_x); +u16 PDMA_GetRemainBlkCnt(u32 PDMA_CHn); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pwrcu.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pwrcu.h new file mode 100644 index 00000000000..a98fb162890 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_pwrcu.h @@ -0,0 +1,376 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_pwrcu.h + * @version $Rev:: 7054 $ + * @date $Date:: 2023-07-24 #$ + * @brief The header file of the Power Control Unit library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_PWRCU_H +#define __HT32F5XXXX_PWRCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup PWRCU + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Types PWRCU exported types + * @{ + */ + +/** + * @brief Status of Power control unit + */ + +/** + * @brief Wakeup pin selection + */ +typedef enum +{ + PWRCU_WAKEUP_PIN_0 = 0, + #if (LIBCFG_PWRCU_WAKEUP1) + PWRCU_WAKEUP_PIN_1 + #endif +} PWRCU_WUP_Enum; +/** + * @brief Wakeup pin trigger type selection + */ +#if (LIBCFG_PWRCU_WAKEUP_V01) +typedef enum +{ + PWRCU_WUP_POSITIVE_EDGE = 0, /*!< Wakeup pin positive_edge triggered */ + PWRCU_WUP_NEGATIVE_EDGE, /*!< Wakeup pin negative_edge triggered */ + PWRCU_WUP_HIGH_LEVEL, /*!< Wakeup pin high-level sensitive */ + PWRCU_WUP_LOW_LEVEL, /*!< Wakeup pin low-level sensitive */ +} PWRCU_WUPTYPE_Enum; +#endif +typedef enum +{ + PWRCU_OK = 0, /*!< Ready for access or VDD power domain power-on reset is released */ + PWRCU_TIMEOUT, /*!< Time out */ + PWRCU_ERROR /*!< Error */ +} PWRCU_Status; +/** + * @brief DMOS status + */ +typedef enum +{ + PWRCU_DMOS_STS_ON = 0, /*!< DMOS on */ + PWRCU_DMOS_STS_OFF, /*!< DMOS off */ + PWRCU_DMOS_STS_OFF_BY_BODRESET /*!< DMOS off caused by brow out reset */ +} PWRCU_DMOSStatus; +/** + * @brief LVD level selection + */ +typedef enum +{ + PWRCU_LVDS_LV1 = 0x00000000, /*!< LVD level 1 */ + PWRCU_LVDS_LV2 = 0x00020000, /*!< LVD level 2 */ + PWRCU_LVDS_LV3 = 0x00040000, /*!< LVD level 3 */ + PWRCU_LVDS_LV4 = 0x00060000, /*!< LVD level 4 */ + PWRCU_LVDS_LV5 = 0x00400000, /*!< LVD level 5 */ + PWRCU_LVDS_LV6 = 0x00420000, /*!< LVD level 6 */ + PWRCU_LVDS_LV7 = 0x00440000, /*!< LVD level 7 */ + PWRCU_LVDS_LV8 = 0x00460000 /*!< LVD level 8 */ +} PWRCU_LVDS_Enum; +#if (LIBCFG_PWRCU_VDD_5V) + #define PWRCU_LVDS_2V65 PWRCU_LVDS_LV1 + #define PWRCU_LVDS_2V85 PWRCU_LVDS_LV2 + #define PWRCU_LVDS_3V05 PWRCU_LVDS_LV3 + #define PWRCU_LVDS_3V25 PWRCU_LVDS_LV4 + #define PWRCU_LVDS_3V45 PWRCU_LVDS_LV5 + #define PWRCU_LVDS_4V25 PWRCU_LVDS_LV6 + #define PWRCU_LVDS_4V45 PWRCU_LVDS_LV7 + #define PWRCU_LVDS_4V65 PWRCU_LVDS_LV8 +#elif (LIBCFG_PWRCU_VDD_2V0_3V6) + #define PWRCU_LVDS_2V25 PWRCU_LVDS_LV1 + #define PWRCU_LVDS_2V4 PWRCU_LVDS_LV2 + #define PWRCU_LVDS_2V55 PWRCU_LVDS_LV3 + #define PWRCU_LVDS_2V7 PWRCU_LVDS_LV4 + #define PWRCU_LVDS_2V85 PWRCU_LVDS_LV5 + #define PWRCU_LVDS_3V PWRCU_LVDS_LV6 + #define PWRCU_LVDS_3V15 PWRCU_LVDS_LV7 + #define PWRCU_LVDS_3V3 PWRCU_LVDS_LV8 +#else + #define PWRCU_LVDS_1V75 PWRCU_LVDS_LV1 + #define PWRCU_LVDS_1V95 PWRCU_LVDS_LV2 + #define PWRCU_LVDS_2V15 PWRCU_LVDS_LV3 + #define PWRCU_LVDS_2V35 PWRCU_LVDS_LV4 + #define PWRCU_LVDS_2V55 PWRCU_LVDS_LV5 + #define PWRCU_LVDS_2V75 PWRCU_LVDS_LV6 + #define PWRCU_LVDS_2V95 PWRCU_LVDS_LV7 + #define PWRCU_LVDS_3V15 PWRCU_LVDS_LV8 +#endif +/** + * @brief BOD reset or interrupt selection + */ +typedef enum +{ + PWRCU_BODRIS_RESET = 0, /*!< Reset the whole chip */ + PWRCU_BODRIS_INT = 1, /*!< Assert interrupt */ +} PWRCU_BODRIS_Enum; +/** + * @brief Sleep entry instruction selection + */ +typedef enum +{ + PWRCU_SLEEP_ENTRY_WFE = 0, /*!< Sleep then wait for event */ + PWRCU_SLEEP_ENTRY_WFI /*!< Sleep then wait for interrupt */ +} PWRCU_SLEEP_ENTRY_Enum; +#if (LIBCFG_BAKREG) +/** + * @brief Backup register selection + */ +typedef enum +{ + PWRCU_BAKREG_0 = 0, + PWRCU_BAKREG_1, + PWRCU_BAKREG_2, + PWRCU_BAKREG_3, + PWRCU_BAKREG_4, + PWRCU_BAKREG_5, + PWRCU_BAKREG_6, + PWRCU_BAKREG_7, + PWRCU_BAKREG_8, + PWRCU_BAKREG_9 +} PWRCU_BAKREG_Enum; +#endif +/** + * @brief Vdd15 power good source selection + */ +typedef enum +{ + PWRCU_V15RDYSC_V33ISO = 0, /*!< Vdd15 power good source come from BK_ISO bit in CKCU unit */ + PWRCU_V15RDYSC_V15POR /*!< Vdd15 power good source come from Vdd15 power on reset */ +} PWRCU_V15RDYSC_Enum; +/** + * @brief LDO operation mode selection + */ +typedef enum +{ + PWRCU_LDO_NORMAL = 0, /*!< The LDO is operated in normal current mode */ + PWRCU_LDO_LOWCURRENT /*!< The LDO is operated in low current mode */ +} PWRCU_LDOMODE_Enum; +#if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) +/** + * @brief HSI ready counter bit length selection + */ +typedef enum +{ + PWRCU_HSIRCBL_4 = 0, /*!< 4 bits */ + PWRCU_HSIRCBL_5, /*!< 5 bits */ + PWRCU_HSIRCBL_6, /*!< 5 bits */ + PWRCU_HSIRCBL_7 /*!< 7 bits (Default) */ +} PWRCU_HSIRCBL_Enum; +#endif +#if (LIBCFG_PWRCU_VREG) +/** + * @brief VREG output voltage selection + */ +typedef enum +{ + #if (LIBCFG_PWRCU_VREG_2V5) + PWRCU_VREG_2V5 = 0x08000000, /*!< VREG output voltage is 2.5 V */ + #else + PWRCU_VREG_4V0 = 0x08000000, /*!< VREG output voltage is 4.0 V */ + #endif + PWRCU_VREG_3V3 = 0x00000000, /*!< VREG output voltage is 3.3 V */ + PWRCU_VREG_3V0 = 0x04000000, /*!< VREG output voltage is 3.0 V */ + PWRCU_VREG_1V8 = 0x0C000000, /*!< VREG output voltage is 1.8 V */ +} PWRCU_VREG_VOLT_Enum; +/** + * @brief VREG operation mode + */ +typedef enum +{ + PWRCU_VREG_DISABLE = 0x00000000, /*!< VREG is disabled */ + PWRCU_VREG_ENABLE = 0x01000000, /*!< VREG is enabled */ + PWRCU_VREG_BYPASS = 0x02000000, /*!< VREG is bypassed */ +} PWRCU_VREG_MODE_Enum; +#endif +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Constants PWRCU exported constants + * @{ + */ + +/* Definitions of PWRCU_FLAG */ +#if (!LIBCFG_PWRCU_NO_VDDPORF) +#define PWRCU_FLAG_PWRPOR 0x0001 /*!< VDD power domain power-on reset flag */ +#endif +#if (!LIBCFG_PWRCU_NO_PDF) +#define PWRCU_FLAG_PD 0x0002 /*!< Power-Down flag */ +#endif +#if (LIBCFG_PWRCU_PORF) +#define PWRCU_FLAG_POR 0x0010 /*!< Power-on reset flag */ +#endif +#define PWRCU_FLAG_WUP 0x0100 /*!< External WAKEUP pin flag */ +#define PWRCU_FLAG_WUP0 0x0100 /*!< External WAKEUP0 pin flag */ +#if (LIBCFG_PWRCU_WAKEUP1) +#define PWRCU_FLAG_WUP1 0x0200 /*!< External WAKEUP1 pin flag */ +#endif + +/* check PWRCU_LVDS parameter */ +#define IS_PWRCU_LVDS(x) ((x == PWRCU_LVDS_LV1) || (x == PWRCU_LVDS_LV2) || \ + (x == PWRCU_LVDS_LV3) || (x == PWRCU_LVDS_LV4) || \ + (x == PWRCU_LVDS_LV5) || (x == PWRCU_LVDS_LV6) || \ + (x == PWRCU_LVDS_LV7) || (x == PWRCU_LVDS_LV8)) + +/* check PWRCU_BODRIS parameter */ +#define IS_PWRCU_BODRIS(x) ((x == PWRCU_BODRIS_RESET) || (x == PWRCU_BODRIS_INT)) + +/* check PWRCU_HSIRCBL parameter */ +#define IS_PWRCU_HSIRCBL(x) (x <= 3) + +/* check PWRCU_SLEEP_ENTRY parameter */ +#define IS_PWRCU_SLEEP_ENTRY(x) ((x == PWRCU_SLEEP_ENTRY_WFI) || (x == PWRCU_SLEEP_ENTRY_WFE)) + +/* check PWRCU_BAKREG parameter */ +#define IS_PWRCU_BAKREG(x) (x < 10) + +/* check PWRCU_V15RDY_SRC parameter */ +#define IS_PWRCU_V15RDYSC(x) ((x == PWRCU_V15RDYSC_V33ISO) || (x == PWRCU_V15RDYSC_V15POR)) + +/* check PWRCU_LDOMODE parameter */ +#define IS_PWRCU_LDOMODE(x) ((x == PWRCU_LDO_NORMAL) || (x == PWRCU_LDO_LOWCURRENT)) + +/* check PWRCU_WUP parameter */ +#define IS_PWRCU_WAKEUPPIN(x) (IS_PWRCU_WAKE0(x) || IS_PWRCU_WAKE1(x)) + +#define IS_PWRCU_WAKE0(x) (x == PWRCU_WAKEUP_PIN_0) + +#if (LIBCFG_PWRCU_WAKEUP1) +#define IS_PWRCU_WAKE1(x) (x == PWRCU_WAKEUP_PIN_1) +#else +#define IS_PWRCU_WAKE1(x) (0) +#endif + +/* check PWRCU_WUPTYPE parameter */ +#define IS_PWRCU_TRIGGERTYPE(x) ((x == PWRCU_WUP_POSITIVE_EDGE) || \ + (x == PWRCU_WUP_NEGATIVE_EDGE) || \ + (x == PWRCU_WUP_HIGH_LEVEL) || \ + (x == PWRCU_WUP_LOW_LEVEL)) + +#if (LIBCFG_PWRCU_VREG) +#define IS_PWRCU_VREG_VOLT(x) ((IS_PWRCU_VREG_VOLT_L2(x)) || \ + (x == PWRCU_VREG_3V3) || \ + (x == PWRCU_VREG_3V0) || \ + (x == PWRCU_VREG_1V8)) + +#if (LIBCFG_PWRCU_VREG_2V5) +#define IS_PWRCU_VREG_VOLT_L2(x) (x == PWRCU_VREG_2V5) +#else +#define IS_PWRCU_VREG_VOLT_L2(x) (x == PWRCU_VREG_4V0) +#endif + +#define IS_PWRCU_VREG_MODE(x) ((x == PWRCU_VREG_DISABLE) || \ + (x == PWRCU_VREG_ENABLE) || \ + (x == PWRCU_VREG_BYPASS)) + + +#endif + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Functions PWRCU exported functions + * @{ + */ +void PWRCU_DeInit(void); +#if (!LIBCFG_NO_PWRCU_TEST_REG) +PWRCU_Status PWRCU_CheckReadyAccessed(void); +#endif +u16 PWRCU_GetFlagStatus(void); +#if (LIBCFG_BAKREG) +u32 PWRCU_ReadBackupRegister(PWRCU_BAKREG_Enum BAKREGx); +void PWRCU_WriteBackupRegister(PWRCU_BAKREG_Enum BAKREGx, u32 DATA); +#endif +void PWRCU_Sleep(PWRCU_SLEEP_ENTRY_Enum SleepEntry); +void PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_Enum SleepEntry); +void PWRCU_DeepSleep2(PWRCU_SLEEP_ENTRY_Enum SleepEntry); +#if !defined(USE_HT32F52220_30) +void PWRCU_DeepSleep2Ex(PWRCU_SLEEP_ENTRY_Enum SleepEntry); +#endif +#if (!LIBCFG_PWRCU_NO_PD_MODE) +void PWRCU_PowerDown(void); +#endif +void PWRCU_SetLVDS(PWRCU_LVDS_Enum Level); +void PWRCU_LDOConfig(PWRCU_LDOMODE_Enum Sel); +void PWRCU_LVDCmd(ControlStatus NewState); +void PWRCU_BODCmd(ControlStatus NewState); +void PWRCU_BODRISConfig(PWRCU_BODRIS_Enum Selection); +FlagStatus PWRCU_GetLVDFlagStatus(void); +FlagStatus PWRCU_GetBODFlagStatus(void); +PWRCU_DMOSStatus PWRCU_GetDMOSStatus(void); +void PWRCU_DMOSCmd(ControlStatus NewState); +#if (LIBCFG_PWRCU_V15_READY_SOURCE) +void PWRCU_V15RDYSourceConfig(PWRCU_V15RDYSC_Enum Sel); +#endif +void PWRCU_LVDIntWakeupConfig(ControlStatus NewState); +void PWRCU_LVDEventWakeupConfig(ControlStatus NewState); +#if (LIBCFG_PWRCU_VREG) +void PWRCU_SetVREG(PWRCU_VREG_VOLT_Enum Volt); +void PWRCU_VREGConfig(PWRCU_VREG_MODE_Enum Mode); +#endif +void PWRCU_WakeupPinCmd(ControlStatus NewState); +#if (LIBCFG_PWRCU_WAKEUP_V01) +void PWRCU_WakeupMultiPinCmd(PWRCU_WUP_Enum Pin, PWRCU_WUPTYPE_Enum Type, ControlStatus NewState); +#endif +#if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) +void PWRCU_HSIReadyCounterBitLengthConfig(PWRCU_HSIRCBL_Enum BitLength); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rstcu.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rstcu.h new file mode 100644 index 00000000000..60eabde7800 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rstcu.h @@ -0,0 +1,238 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_rstcu.h + * @version $Rev:: 7115 $ + * @date $Date:: 2023-08-11 #$ + * @brief The header file of the Reset Control Unit library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_RSTCU_H +#define __HT32F5XXXX_RSTCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup RSTCU + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Types RSTCU exported types + * @{ + */ + +/** + * @brief Enumeration of Global reset status. + */ +typedef enum +{ + RSTCU_FLAG_SYSRST = 0, + RSTCU_FLAG_EXTRST, + RSTCU_FLAG_WDTRST, + RSTCU_FLAG_PORST +} RSTCU_RSTF_TypeDef; + +/** + * @brief Definition of initial structure of peripheral reset. + */ +typedef union +{ + struct + { + /* Definitions of AHB peripheral reset */ + unsigned long PDMA :1; // Bit 0 + unsigned long :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long :1; // Bit 4 + unsigned long USBD :1; // Bit 5 + unsigned long EBI :1; // Bit 6 + unsigned long CRC :1; // Bit 7 + + unsigned long PA :1; // Bit 8 + unsigned long PB :1; // Bit 9 + unsigned long PC :1; // Bit 10 + unsigned long PD :1; // Bit 11 + unsigned long PE :1; // Bit 12 + unsigned long PF :1; // Bit 13 + unsigned long :1; // Bit 14 + unsigned long AES :1; // Bit 15 + + #ifdef USE_HT32F65230_40 + unsigned long DIV :1; // Bit 16 + #else + unsigned long :1; // Bit 16 + #endif + unsigned long :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 + unsigned long :1; // Bit 22 + unsigned long :1; // Bit 23 + + #ifndef USE_HT32F65230_40 + unsigned long DIV :1; // Bit 24 + #else + unsigned long :1; // Bit 24 + #endif + unsigned long QSPI :1; // Bit 25 + unsigned long RF :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long :1; // Bit 28 + unsigned long :1; // Bit 29 + unsigned long :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB peripheral 0 reset */ + unsigned long I2C0 :1; // Bit 0 + unsigned long I2C1 :1; // Bit 1 + unsigned long I2C2 :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long SPI0 :1; // Bit 4 + unsigned long SPI1 :1; // Bit 5 + unsigned long :1; // Bit 6 + unsigned long :1; // Bit 7 + + unsigned long USART0 :1; // Bit 8 + unsigned long USART1 :1; // Bit 9 + unsigned long UART0 :1; // Bit 10 + unsigned long UART1 :1; // Bit 11 + unsigned long UART2 :1; // Bit 12 + unsigned long UART3 :1; // Bit 13 + unsigned long AFIO :1; // Bit 14 + unsigned long EXTI :1; // Bit 15 + + unsigned long :1; // Bit 16 + unsigned long :1; // Bit 17 + unsigned long :1; // Bit 18 + unsigned long :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long :1; // Bit 21 + unsigned long SLED0 :1; // Bit 22 + unsigned long SLED1 :1; // Bit 23 + + unsigned long SCI0 :1; // Bit 24 + unsigned long I2S :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long SCI1 :1; // Bit 27 + unsigned long MIDI :1; // Bit 28 + unsigned long LEDC :1; // Bit 29 + unsigned long CAN0 :1; // Bit 30 + unsigned long :1; // Bit 31 + + /* Definitions of APB peripheral 1 reset */ + unsigned long MCTM0 :1; // Bit 0 + unsigned long :1; // Bit 1 + unsigned long :1; // Bit 2 + unsigned long :1; // Bit 3 + unsigned long WDT :1; // Bit 4 + unsigned long :1; // Bit 5 + unsigned long :1; // Bit 6 + unsigned long DAC1 :1; // Bit 7 + + unsigned long GPTM0 :1; // Bit 8 + unsigned long GPTM1 :1; // Bit 9 + unsigned long :1; // Bit 10 + unsigned long :1; // Bit 11 + unsigned long PWM0 :1; // Bit 12 + unsigned long PWM1 :1; // Bit 13 + unsigned long PWM2 :1; // Bit 14 + unsigned long :1; // Bit 15 + + unsigned long BFTM0 :1; // Bit 16 + unsigned long BFTM1 :1; // Bit 17 + unsigned long TKEY :1; // Bit 18 + unsigned long LCD :1; // Bit 19 + unsigned long :1; // Bit 20 + unsigned long DAC0 :1; // Bit 21 + unsigned long CMP :1; // Bit 22 + unsigned long OPA :1; // Bit 23 + + unsigned long ADC0 :1; // Bit 24 + unsigned long ADC1 :1; // Bit 25 + unsigned long :1; // Bit 26 + unsigned long :1; // Bit 27 + unsigned long SCTM0 :1; // Bit 28 + unsigned long SCTM1 :1; // Bit 29 + unsigned long SCTM2 :1; // Bit 30 + unsigned long SCTM3 :1; // Bit 31 + } Bit; + u32 Reg[3]; +} RSTCU_PeripReset_TypeDef; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Constants RSTCU exported constants + * @{ + */ + +/* Other definitions */ +#define IS_RSTCU_FLAG(FLAG) ((FLAG == RSTCU_FLAG_SYSRST) || \ + (FLAG == RSTCU_FLAG_EXTRST) || \ + (FLAG == RSTCU_FLAG_WDTRST) || \ + (FLAG == RSTCU_FLAG_PORST)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Functions RSTCU exported functions + * @{ + */ +FlagStatus RSTCU_GetResetFlagStatus(RSTCU_RSTF_TypeDef RSTCU_RSTF); +void RSTCU_ClearResetFlag(RSTCU_RSTF_TypeDef RSTCU_RSTF); +void RSTCU_ClearAllResetFlag(void); +void RSTCU_PeripReset(RSTCU_PeripReset_TypeDef Reset, ControlStatus Cmd); + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rtc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rtc.h new file mode 100644 index 00000000000..0677ae67176 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_rtc.h @@ -0,0 +1,255 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_rtc.h + * @version $Rev:: 7278 $ + * @date $Date:: 2023-10-04 #$ + * @brief The header file of the RTC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_RTC_H +#define __HT32F5XXXX_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Types RTC exported types + * @{ + */ + +/** + * @brief Selection of RTC clock source + */ +typedef enum +{ + RTC_SRC_LSI = 0, /*!< Low speed internal clock, about 32 kHz */ + #if (LIBCFG_LSE) + RTC_SRC_LSE /*!< Low speed external 32768 Hz clock */ + #endif +} RTC_SRC_Enum; +/** + * @brief Selection of RTC LSE startup mode + */ +typedef enum +{ + RTC_LSESM_NORMAL = 0, /*!< Little power consumption but longer startup time. */ + RTC_LSESM_FAST /*!< Shortly startup time but higher power consumption. */ +} RTC_LSESM_Enum; +/** + * @brief Selection of RTC prescaler + */ +typedef enum +{ + RTC_RPRE_1 = 0x0000, /*!< CK_SECOND = CK_RTC */ + RTC_RPRE_2 = 0x0100, /*!< CK_SECOND = CK_RTC / 2 */ + RTC_RPRE_4 = 0x0200, /*!< CK_SECOND = CK_RTC / 4 */ + RTC_RPRE_8 = 0x0300, /*!< CK_SECOND = CK_RTC / 8 */ + RTC_RPRE_16 = 0x0400, /*!< CK_SECOND = CK_RTC / 16 */ + RTC_RPRE_32 = 0x0500, /*!< CK_SECOND = CK_RTC / 32 */ + RTC_RPRE_64 = 0x0600, /*!< CK_SECOND = CK_RTC / 64 */ + RTC_RPRE_128 = 0x0700, /*!< CK_SECOND = CK_RTC / 128 */ + RTC_RPRE_256 = 0x0800, /*!< CK_SECOND = CK_RTC / 256 */ + RTC_RPRE_512 = 0x0900, /*!< CK_SECOND = CK_RTC / 512 */ + RTC_RPRE_1024 = 0x0A00, /*!< CK_SECOND = CK_RTC / 1024 */ + RTC_RPRE_2048 = 0x0B00, /*!< CK_SECOND = CK_RTC / 2048 */ + RTC_RPRE_4096 = 0x0C00, /*!< CK_SECOND = CK_RTC / 4096 */ + RTC_RPRE_8192 = 0x0D00, /*!< CK_SECOND = CK_RTC / 8192 */ + RTC_RPRE_16384 = 0x0E00, /*!< CK_SECOND = CK_RTC / 16384 */ + RTC_RPRE_32768 = 0x0F00 /*!< CK_SECOND = CK_RTC / 32768 */ +} RTC_RPRE_Enum; +/** + * @brief Active polarity of RTC output + */ +typedef enum +{ + RTC_ROAP_HIGH = 0, /*!< Active level is high */ + RTC_ROAP_LOW /*!< Active level is low */ +} RTC_ROAP_Enum; +/** + * @brief Waveform mode of RTC output + */ +typedef enum +{ + RTC_ROWM_PULSE = 0, /*!< Pulse mode. */ + RTC_ROWM_LEVEL /*!< Level mode. */ +} RTC_ROWM_Enum; +/** + * @brief Waveform mode of RTC output + */ +typedef enum +{ + RTC_ROES_MATCH = 0, /*!< Selected RTC compare match. */ + RTC_ROES_SECOND /*!< Selected RTC second clock. */ +} RTC_ROES_Enum; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Constants RTC exported constants + * @{ + */ + +/** @defgroup RTC_WAKEUP Selection of RTC wakeup source + * @{ + */ +#define RTC_WAKEUP_CSEC 0x00000100 +#define RTC_WAKEUP_CM 0x00000200 +#define RTC_WAKEUP_OV 0x00000400 +/** + * @} + */ + +/** @defgroup RTC_IT RTC Selection of interrupt source + * @{ + */ +#define RTC_INT_CSEC 0x00000001 +#define RTC_INT_CM 0x00000002 +#define RTC_INT_OV 0x00000004 +/** + * @} + */ + +/** @defgroup RTC_FLAG RTC Definitions of flags + * @{ + */ +#define RTC_FLAG_CSEC 0x00000001 +#define RTC_FLAG_CM 0x00000002 +#define RTC_FLAG_OV 0x00000004 +/** + * @} + */ + +/** @defgroup RTC_Check_Parameter Selection of Vdd18 power good + * @{ + */ + +/** + * @brief Used to check RTC_SRC_Enum parameter + */ +#if (LIBCFG_LSE) +#define IS_RTC_SRC_LSE(x) (x == RTC_SRC_LSE) +#else +#define IS_RTC_SRC_LSE(x) (0) +#endif +#define IS_RTC_SRC(x) ((x == RTC_SRC_LSI) || IS_RTC_SRC_LSE(x)) +/** + * @brief Used to check RTC_LSESM_Enum parameter + */ +#define IS_RTC_LSESM(x) ((x == RTC_LSESM_NORMAL) || (x == RTC_LSESM_FAST)) +/** + * @brief Used to check RTC_RPRE_Enum parameter + */ +#define IS_RTC_PSC(x) ((x == RTC_RPRE_1) || (x == RTC_RPRE_2) || (x == RTC_RPRE_4) ||\ + (x == RTC_RPRE_8) || (x == RTC_RPRE_16) || (x == RTC_RPRE_32) ||\ + (x == RTC_RPRE_64) || (x == RTC_RPRE_128) || (x == RTC_RPRE_256) ||\ + (x == RTC_RPRE_512) || (x == RTC_RPRE_1024) || (x == RTC_RPRE_2048) ||\ + (x == RTC_RPRE_4096) || (x == RTC_RPRE_8192) || (x == RTC_RPRE_16384) ||\ + (x == RTC_RPRE_32768)) +/** + * @brief Used to check RTC_ROAP_Enum parameter + */ +#define IS_RTC_ROAP(x) ((x == RTC_ROAP_HIGH) || (x == RTC_ROAP_LOW)) +/** + * @brief Used to check RTC_ROWM_Enum parameter + */ +#define IS_RTC_ROWM(x) ((x == RTC_ROWM_PULSE) || (x == RTC_ROWM_LEVEL)) +/** + * @brief Used to check RTC_ROES_Enum parameter + */ +#define IS_RTC_ROES(x) ((x == RTC_ROES_MATCH) || (x == RTC_ROES_SECOND)) +/** + * @brief Used to check RTC_WAKEUP parameter + */ +#define IS_RTC_WAKEUP(x) ((((x) & (u32)0xFFFFF8FF) == 0x00) && ((x) != 0x00)) +/** + * @brief Used to check RTC_INT parameter + */ +#define IS_RTC_INT(x) ((((x) & (u32)0xFFFFFFF8) == 0x00) && ((x) != 0x00)) +/** + * @brief Used to check RTC_FLAG parameter + */ +#define IS_RTC_FLAG(x) ((((x) & (u32)0xFFFFFFF8) == 0x00) && ((x) != 0x00)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC exported functions + * @{ + */ +void RTC_DeInit(void); +void RTC_ClockSourceConfig(RTC_SRC_Enum Source); +#if (LIBCFG_RTC_LSI_LOAD_TRIM) +void RTC_LSILoadTrimData(void); +#endif +void RTC_LSESMConfig(RTC_LSESM_Enum Mode); +void RTC_LSECmd(ControlStatus NewState); +void RTC_CMPCLRCmd(ControlStatus NewState); +void RTC_SetPrescaler(RTC_RPRE_Enum Psc); +u16 RTC_GetPrescaler(void); +void RTC_Cmd(ControlStatus NewState); +u32 RTC_GetCounter(void); +void RTC_SetCompare(u32 Compare); +u32 RTC_GetCompare(void); +void RTC_WakeupConfig(u32 RTC_WAKEUP, ControlStatus NewState); +void RTC_IntConfig(u32 RTC_INT, ControlStatus NewState); +u8 RTC_GetFlagStatus(void); +void RTC_OutConfig(RTC_ROWM_Enum WMode, RTC_ROES_Enum EventSel, RTC_ROAP_Enum Pol); +void RTC_OutCmd(ControlStatus NewState); +FlagStatus RTC_GetOutStatus(void); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_sci.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_sci.h new file mode 100644 index 00000000000..b95ff723436 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_sci.h @@ -0,0 +1,280 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_sci.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The header file of the SCI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_SCI_H +#define __HT32F5XXXX_SCI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup SCI + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Types SCI exported types + * @{ + */ +typedef struct +{ + u32 SCI_Mode; + u32 SCI_Retry; + u32 SCI_Convention; + u32 SCI_CardPolarity; + u32 SCI_ClockPrescale; +} SCI_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Constants SCI exported constants + * @{ + */ +#define SCI_MODE_MANUAL ((u32)0x00000000) +#define SCI_MODE_SCI ((u32)0x00000008) + +#define IS_SCI_MODE(MODE) ((MODE == SCI_MODE_MANUAL) || \ + (MODE == SCI_MODE_SCI)) + + +#define SCI_RETRY_NO ((u32)0x00000000) +#define SCI_RETRY_4 ((u32)0x00000012) +#define SCI_RETRY_5 ((u32)0x00000002) + +#define IS_SCI_RETRY(RETRY) ((RETRY == SCI_RETRY_NO) || \ + (RETRY == SCI_RETRY_4) || \ + (RETRY == SCI_RETRY_5)) + + +#define SCI_CONVENTION_DIRECT ((u32)0x00000000) +#define SCI_CONVENTION_INVERSE ((u32)0x00000001) + +#define IS_SCI_CONVENTION(CONVENTION) ((CONVENTION == SCI_CONVENTION_DIRECT) || \ + (CONVENTION == SCI_CONVENTION_INVERSE)) + + +#define SCI_CARDPOLARITY_LOW ((u32)0x00000000) +#define SCI_CARDPOLARITY_HIGH ((u32)0x00000040) + +#define IS_SCI_CARD_POLARITY(POLARITY) ((POLARITY == SCI_CARDPOLARITY_LOW) || \ + (POLARITY == SCI_CARDPOLARITY_HIGH)) + + +#define SCI_CLKPRESCALER_1 ((u32)0x00000000) +#define SCI_CLKPRESCALER_2 ((u32)0x00000001) +#define SCI_CLKPRESCALER_4 ((u32)0x00000002) +#define SCI_CLKPRESCALER_6 ((u32)0x00000003) +#define SCI_CLKPRESCALER_8 ((u32)0x00000004) +#define SCI_CLKPRESCALER_10 ((u32)0x00000005) +#define SCI_CLKPRESCALER_12 ((u32)0x00000006) +#define SCI_CLKPRESCALER_14 ((u32)0x00000007) +#define SCI_CLKPRESCALER_16 ((u32)0x00000008) +#define SCI_CLKPRESCALER_18 ((u32)0x00000009) +#define SCI_CLKPRESCALER_20 ((u32)0x0000000A) +#define SCI_CLKPRESCALER_22 ((u32)0x0000000B) +#define SCI_CLKPRESCALER_24 ((u32)0x0000000C) +#define SCI_CLKPRESCALER_26 ((u32)0x0000000D) +#define SCI_CLKPRESCALER_28 ((u32)0x0000000E) +#define SCI_CLKPRESCALER_30 ((u32)0x0000000F) +#define SCI_CLKPRESCALER_32 ((u32)0x00000010) +#define SCI_CLKPRESCALER_34 ((u32)0x00000011) +#define SCI_CLKPRESCALER_36 ((u32)0x00000012) +#define SCI_CLKPRESCALER_38 ((u32)0x00000013) +#define SCI_CLKPRESCALER_40 ((u32)0x00000014) +#define SCI_CLKPRESCALER_42 ((u32)0x00000015) +#define SCI_CLKPRESCALER_44 ((u32)0x00000016) +#define SCI_CLKPRESCALER_46 ((u32)0x00000017) +#define SCI_CLKPRESCALER_48 ((u32)0x00000018) +#define SCI_CLKPRESCALER_50 ((u32)0x00000019) +#define SCI_CLKPRESCALER_52 ((u32)0x0000001A) +#define SCI_CLKPRESCALER_54 ((u32)0x0000001B) +#define SCI_CLKPRESCALER_56 ((u32)0x0000001C) +#define SCI_CLKPRESCALER_58 ((u32)0x0000001D) +#define SCI_CLKPRESCALER_60 ((u32)0x0000001E) +#define SCI_CLKPRESCALER_62 ((u32)0x0000001F) +#define SCI_CLKPRESCALER_64 ((u32)0x00000020) +#define SCI_CLKPRESCALER_66 ((u32)0x00000021) +#define SCI_CLKPRESCALER_68 ((u32)0x00000022) +#define SCI_CLKPRESCALER_70 ((u32)0x00000023) +#define SCI_CLKPRESCALER_72 ((u32)0x00000024) +#define SCI_CLKPRESCALER_74 ((u32)0x00000025) +#define SCI_CLKPRESCALER_76 ((u32)0x00000026) +#define SCI_CLKPRESCALER_78 ((u32)0x00000027) +#define SCI_CLKPRESCALER_80 ((u32)0x00000028) +#define SCI_CLKPRESCALER_82 ((u32)0x00000029) +#define SCI_CLKPRESCALER_84 ((u32)0x0000002A) +#define SCI_CLKPRESCALER_86 ((u32)0x0000002B) +#define SCI_CLKPRESCALER_88 ((u32)0x0000002C) +#define SCI_CLKPRESCALER_90 ((u32)0x0000002D) +#define SCI_CLKPRESCALER_92 ((u32)0x0000002E) +#define SCI_CLKPRESCALER_94 ((u32)0x0000002F) +#define SCI_CLKPRESCALER_96 ((u32)0x00000030) +#define SCI_CLKPRESCALER_98 ((u32)0x00000031) +#define SCI_CLKPRESCALER_100 ((u32)0x00000032) +#define SCI_CLKPRESCALER_102 ((u32)0x00000033) +#define SCI_CLKPRESCALER_104 ((u32)0x00000034) +#define SCI_CLKPRESCALER_106 ((u32)0x00000035) +#define SCI_CLKPRESCALER_108 ((u32)0x00000036) +#define SCI_CLKPRESCALER_110 ((u32)0x00000037) +#define SCI_CLKPRESCALER_112 ((u32)0x00000038) +#define SCI_CLKPRESCALER_114 ((u32)0x00000039) +#define SCI_CLKPRESCALER_116 ((u32)0x0000003A) +#define SCI_CLKPRESCALER_118 ((u32)0x0000003B) +#define SCI_CLKPRESCALER_120 ((u32)0x0000003C) +#define SCI_CLKPRESCALER_122 ((u32)0x0000003D) +#define SCI_CLKPRESCALER_124 ((u32)0x0000003E) +#define SCI_CLKPRESCALER_126 ((u32)0x0000003F) + +#define IS_SCI_CLOCK_PRESCALER(PRESCALER) (PRESCALER <= 0x3F) + + +#define SCI_COMPENSATION_ENABLE ((u32)0x00008000) +#define SCI_COMPENSATION_DISABLE ((u32)0x00000000) + +#define IS_SCI_ETU_COMPENSATION(COMPENSATION) ((COMPENSATION == SCI_COMPENSATION_ENABLE) || \ + (COMPENSATION == SCI_COMPENSATION_DISABLE)) + + +#define SCI_CLK_HARDWARE ((u32)0x00000080) +#define SCI_CLK_SOFTWARE ((u32)0xFFFFFF7F) + +#define IS_SCI_CLK_MODE(MODE) ((MODE == SCI_CLK_HARDWARE) || \ + (MODE == SCI_CLK_SOFTWARE)) + + +#define SCI_CLK_HIGH ((u32)0x00000004) +#define SCI_CLK_LOW ((u32)0xFFFFFFFB) + +#define IS_SCI_CLK(CLK) ((CLK == SCI_CLK_HIGH) || \ + (CLK == SCI_CLK_LOW)) + + +#define SCI_DIO_HIGH ((u32)0x00000008) +#define SCI_DIO_LOW ((u32)0xFFFFFFF7) + +#define IS_SCI_DIO(DIO) ((DIO == SCI_DIO_HIGH) || \ + (DIO == SCI_DIO_LOW)) + + +#define SCI_INT_PAR ((u32)0x00000001) +#define SCI_INT_RXC ((u32)0x00000002) +#define SCI_INT_TXC ((u32)0x00000004) +#define SCI_INT_WT ((u32)0x00000008) +#define SCI_INT_CARD ((u32)0x00000040) +#define SCI_INT_TXBE ((u32)0x00000080) +#define SCI_INT_ALL ((u32)0x000000CF) + +#define IS_SCI_INT(INT) (((INT & 0xFFFFFF30) == 0x0) && (INT != 0)) + + + +#define SCI_FLAG_PAR ((u32)0x00000001) +#define SCI_FLAG_RXC ((u32)0x00000002) +#define SCI_FLAG_TXC ((u32)0x00000004) +#define SCI_FLAG_WT ((u32)0x00000008) +#define SCI_FLAG_CARD ((u32)0x00000040) +#define SCI_FLAG_TXBE ((u32)0x00000080) + +#define IS_SCI_FLAG(FLAG) ((FLAG == SCI_FLAG_PAR) || \ + (FLAG == SCI_FLAG_RXC) || \ + (FLAG == SCI_FLAG_TXC) || \ + (FLAG == SCI_FLAG_WT) || \ + (FLAG == SCI_FLAG_CARD) || \ + (FLAG == SCI_FLAG_TXBE)) + +#define IS_SCI_CLEAR_FLAG(FLAG) ((FLAG == SCI_FLAG_PAR) || \ + (FLAG == SCI_FLAG_TXC) || \ + (FLAG == SCI_FLAG_WT)) + + +#define SCI_PDMAREQ_TX ((u32)0x00000100) +#define SCI_PDMAREQ_RX ((u32)0x00000200) + +#define IS_SCI_PDMA_REQ(REQ) (((REQ & 0xFFFFFCFF) == 0x0) && (REQ != 0)) + + +#define IS_SCI_ETU(ETU) ((ETU >= 12) & (ETU <= 2047)) + +#define IS_SCI_GUARDTIME(GUARDTIME) ((GUARDTIME >= 11) & (GUARDTIME <= 511)) + +#define IS_SCI_WAITING_TIME(TIME) ((TIME >= 372) & (TIME <= 16777215)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Functions SCI exported functions + * @{ + */ +void SCI_DeInit(HT_SCI_TypeDef* SCIx); +void SCI_Init(HT_SCI_TypeDef* SCIx, SCI_InitTypeDef* SCI_InitStruct); +void SCI_StructInit(SCI_InitTypeDef* SCI_InitStruct); +void SCI_Cmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState); +void SCI_ETUConfig(HT_SCI_TypeDef* SCIx, u32 SCI_ETU, u32 SCI_Compensation); +void SCI_SetGuardTimeValue(HT_SCI_TypeDef* SCIx, u16 SCI_GuardTime); +void SCI_SetWaitingTimeValue(HT_SCI_TypeDef* SCIx, u32 SCI_WaitingTime); +void SCI_WaitingTimeCounterCmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState); +void SCI_SendData(HT_SCI_TypeDef* SCIx, u8 SCI_Data); +u8 SCI_ReceiveData(HT_SCI_TypeDef* SCIx); +void SCI_ClockModeConfig(HT_SCI_TypeDef* SCIx, u32 SCI_CLKMode); +void SCI_SoftwareClockCmd(HT_SCI_TypeDef* SCIx, u32 SCI_CLK); +void SCI_OutputDIO(HT_SCI_TypeDef* SCIx, u32 SCI_DIO); +void SCI_IntConfig(HT_SCI_TypeDef* SCIx, u32 SCI_Int, ControlStatus NewState); +FlagStatus SCI_GetFlagStatus(HT_SCI_TypeDef* SCIx, u32 SCI_Flag); +void SCI_ClearFlag(HT_SCI_TypeDef* SCIx, u32 SCI_Flag); +#if (LIBCFG_PDMA) +void SCI_PDMACmd(HT_SCI_TypeDef* SCIx, u32 SCI_PDMAREQ, ControlStatus NewState); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_sled.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_sled.h new file mode 100644 index 00000000000..15a57294caf --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_sled.h @@ -0,0 +1,157 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_sled.h + * @version $Rev:: 3875 $ + * @date $Date:: 2019-05-10 #$ + * @brief The header file of the SLED library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_SLED_H +#define __HT32F5XXXX_SLED_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup SLED + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup SLED_Exported_Types SLED exported types + * @{ + */ + +/** + * @brief Enumeration of CK_SLED prescaler. + */ +typedef enum +{ + SLED_CLKPRE_DIV1 = 0, + SLED_CLKPRE_DIV2, + SLED_CLKPRE_DIV4, + SLED_CLKPRE_DIV3 +} SLED_CLKPRE_TypeDef; + +/** + * @brief Definition of SLED Init Structure. + */ +typedef struct +{ + u8 ClockPrescaler; + u8 BaudRate; + u8 T0H; + u8 T1H; + u8 TRST; + u8 SyncState; + u8 IdleState; + u8 ResetState; + u8 SyncMode; + u8 OutputPolarity; +} SLED_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup SLED_Exported_Constants SLED exported constants + * @{ + */ +#define SLED_SYNC_STATE_T0 (0) +#define SLED_SYNC_STATE_T1 (1) + +#define SLED_IDLE_STATE_LOW (0) +#define SLED_IDLE_STATE_HIGH (1) + +#define SLED_RESET_STATE_LOW (0) +#define SLED_RESET_STATE_HIGH (1) + +#define SLED_SYNC_MODE_DISABLE (0) +#define SLED_SYNC_MODE_ENABLE (1) + +#define SLED_OUTPUT_NONINVERTING (0) +#define SLED_OUTPUT_INVERTING (1) + +#define SLED_FIFO_LEVEL_0 (0 << 6) +#define SLED_FIFO_LEVEL_1 (1 << 6) +#define SLED_FIFO_LEVEL_2 (2 << 6) +#define SLED_FIFO_LEVEL_3 (3 << 6) + +#define IS_SLED_FIFO_LEVEL(LEVEL) ((LEVEL == SLED_FIFO_LEVEL_0) || \ + (LEVEL == SLED_FIFO_LEVEL_1) || \ + (LEVEL == SLED_FIFO_LEVEL_2) || \ + (LEVEL == SLED_FIFO_LEVEL_3)) + +#define IS_SLED(SLED) ((SLED == HT_SLED0) || (SLED == HT_SLED1)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SLED_Exported_Functions SLED exported functions + * @{ + */ +void SLED_DeInit(HT_SLED_TypeDef* SLEDx); +void SLED_Init(HT_SLED_TypeDef* SLEDx, SLED_InitTypeDef* SLED_InitStruct); + +void SLED_Cmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState); +void SLED_OutputCmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState); +void SLED_PDMACmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState); + +void SLED_IntCmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState); +void SLED_ClearIntFlag(HT_SLED_TypeDef* SLEDx); + +void SLED_InsertResetCode(HT_SLED_TypeDef* SLEDx); +FlagStatus SLED_GetResetCodeStatus(HT_SLED_TypeDef* SLEDx); + +FlagStatus SLED_GetBusyStatus(HT_SLED_TypeDef* SLEDx); + +void SLED_FIFOTrigLevelConfig(HT_SLED_TypeDef* SLEDx, u8 FifoLevel); +u8 SLED_GetFIFOStatus(HT_SLED_TypeDef* SLEDx); +void SLED_FIFOReset(HT_SLED_TypeDef* SLEDx); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_spi.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_spi.h new file mode 100644 index 00000000000..b92fb0d0067 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_spi.h @@ -0,0 +1,375 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_spi.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The header file of the SPI library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_SPI_H +#define __HT32F5XXXX_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + + +#if (LIBCFG_MIDI) +#include "ht32f5xxxx_spi_midi.h" +#endif + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI exported types + * @{ + */ + +#if (LIBCFG_SPI_DATA_LENGTH_V01) +typedef u8 SPI_DataTypeDef; +#else +typedef u16 SPI_DataTypeDef; +#endif + +#if (LIBCFG_SPI_TIMEOUT_LENGTH_V01) +typedef u8 SPI_TimeoutTypeDef; +#else +typedef u16 SPI_TimeoutTypeDef; +#endif + +typedef struct +{ + u32 SPI_Mode; + u32 SPI_FIFO; + u32 SPI_DataLength; + u32 SPI_SELMode; + u32 SPI_SELPolarity; + u32 SPI_CPOL; + u32 SPI_CPHA; + u32 SPI_FirstBit; + u32 SPI_RxFIFOTriggerLevel; + u32 SPI_TxFIFOTriggerLevel; + u32 SPI_ClockPrescaler; +} SPI_InitTypeDef; + +/** + * @brief Enumeration of SIO direction. + */ +#if (LIBCFG_QSPI) +typedef enum +{ + SIO_DIR_IN = 0, /*!< input mode */ + SIO_DIR_OUT /*!< output mode */ +} SIO_DIR_Enum; +#endif +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Constants SPI exported constants + * @{ + */ +#define SPI_FIFO_ENABLE ((u32)0x00000400) +#define SPI_FIFO_DISABLE ((u32)0x00000000) + +#define IS_SPI_FIFO_SET(FIFO) ((FIFO == SPI_FIFO_ENABLE) || \ + (FIFO == SPI_FIFO_DISABLE)) + +#define SPI_DATALENGTH_1 ((u32)0x00000001) +#define SPI_DATALENGTH_2 ((u32)0x00000002) +#define SPI_DATALENGTH_3 ((u32)0x00000003) +#define SPI_DATALENGTH_4 ((u32)0x00000004) +#define SPI_DATALENGTH_5 ((u32)0x00000005) +#define SPI_DATALENGTH_6 ((u32)0x00000006) +#define SPI_DATALENGTH_7 ((u32)0x00000007) + +#if (LIBCFG_SPI_DATA_LENGTH_V01) +#define SPI_DATALENGTH_8 ((u32)0x00000000) + +#define IS_SPI_DATALENGTH(DATALENGTH) ((DATALENGTH <= 0x07)) +#else +#define SPI_DATALENGTH_8 ((u32)0x00000008) +#define SPI_DATALENGTH_9 ((u32)0x00000009) +#define SPI_DATALENGTH_10 ((u32)0x0000000A) +#define SPI_DATALENGTH_11 ((u32)0x0000000B) +#define SPI_DATALENGTH_12 ((u32)0x0000000C) +#define SPI_DATALENGTH_13 ((u32)0x0000000D) +#define SPI_DATALENGTH_14 ((u32)0x0000000E) +#define SPI_DATALENGTH_15 ((u32)0x0000000F) +#define SPI_DATALENGTH_16 ((u32)0x00000000) + +#define IS_SPI_DATALENGTH(DATALENGTH) ((DATALENGTH <= 0xF)) +#endif + +#define SPI_MASTER ((u32)0x00004000) +#define SPI_SLAVE ((u32)0x00000000) + +#define IS_SPI_MODE(MODE) ((MODE == SPI_MASTER) || \ + (MODE == SPI_SLAVE)) + + +#define SPI_SEL_HARDWARE ((u32)0x00002000) +#define SPI_SEL_SOFTWARE ((u32)0x00000000) + +#define IS_SPI_SEL_MODE(SELMODE) ((SELMODE == SPI_SEL_HARDWARE) || \ + (SELMODE == SPI_SEL_SOFTWARE)) + + +#define SPI_SEL_ACTIVE ((u32)0x00000010) +#define SPI_SEL_INACTIVE ((u32)0xFFFFFFEF) + +#define IS_SPI_SOFTWARE_SEL(SEL) ((SEL == SPI_SEL_ACTIVE) || \ + (SEL == SPI_SEL_INACTIVE)) + + +#define SPI_SELPOLARITY_HIGH ((u32)0x00000800) +#define SPI_SELPOLARITY_LOW ((u32)0x00000000) + +#define IS_SPI_SEL_POLARITY(POLARITY) ((POLARITY == SPI_SELPOLARITY_HIGH) || \ + (POLARITY == SPI_SELPOLARITY_LOW)) + + +#define SPI_CPOL_HIGH ((u32)0x00000400) +#define SPI_CPOL_LOW ((u32)0x00000000) + +#define IS_SPI_CPOL(CPOL) ((CPOL == SPI_CPOL_HIGH) || \ + (CPOL == SPI_CPOL_LOW)) + + +#define SPI_CPHA_FIRST ((u32)0x00000000) +#define SPI_CPHA_SECOND ((u32)0x00000001) + +#define IS_SPI_CPHA(CPHA) ((CPHA == SPI_CPHA_FIRST) || \ + (CPHA == SPI_CPHA_SECOND)) + + +#define SPI_FIRSTBIT_LSB ((u32)0x00001000) +#define SPI_FIRSTBIT_MSB ((u32)0x00000000) + +#define IS_SPI_FIRST_BIT(BIT) ((BIT == SPI_FIRSTBIT_LSB) || \ + (BIT == SPI_FIRSTBIT_MSB)) + + +#define SPI_FLAG_TXBE ((u32)0x00000001) +#define SPI_FLAG_TXE ((u32)0x00000002) +#define SPI_FLAG_RXBNE ((u32)0x00000004) +#define SPI_FLAG_WC ((u32)0x00000008) +#define SPI_FLAG_RO ((u32)0x00000010) +#if (LIBCFG_SPI_NO_MULTI_MASTER) +#define IS_FLAG_MF(x) (0) +#else +#define SPI_FLAG_MF ((u32)0x00000020) +#define IS_FLAG_MF(x) (x == SPI_FLAG_MF) +#endif +#define SPI_FLAG_SA ((u32)0x00000040) +#define SPI_FLAG_TOUT ((u32)0x00000080) +#define SPI_FLAG_BUSY ((u32)0x00000100) + +#define IS_SPI_FLAG(FLAG) ((FLAG == SPI_FLAG_TXBE) || \ + (FLAG == SPI_FLAG_TXE) || \ + (FLAG == SPI_FLAG_RXBNE) || \ + (FLAG == SPI_FLAG_WC) || \ + (FLAG == SPI_FLAG_RO) || \ + IS_FLAG_MF(FLAG) || \ + (FLAG == SPI_FLAG_SA) || \ + (FLAG == SPI_FLAG_TOUT) || \ + (FLAG == SPI_FLAG_BUSY)) + +#define IS_SPI_FLAG_CLEAR(CLEAR) ((CLEAR == SPI_FLAG_WC) || \ + (CLEAR == SPI_FLAG_RO) || \ + IS_FLAG_MF(CLEAR) || \ + (CLEAR == SPI_FLAG_SA) || \ + (CLEAR == SPI_FLAG_TOUT)) + + +#define SPI_INT_TXBE ((u32)0x00000001) +#define SPI_INT_TXE ((u32)0x00000002) +#define SPI_INT_RXBNE ((u32)0x00000004) +#define SPI_INT_WC ((u32)0x00000008) +#define SPI_INT_RO ((u32)0x00000010) +#if (!LIBCFG_SPI_NO_MULTI_MASTER) +#define SPI_INT_MF ((u32)0x00000020) +#endif +#define SPI_INT_SA ((u32)0x00000040) +#define SPI_INT_TOUT ((u32)0x00000080) +#if (LIBCFG_SPI_NO_MULTI_MASTER) +#define SPI_INT_ALL ((u32)0x000000DF) +#else +#define SPI_INT_ALL ((u32)0x000000FF) +#endif + +#define IS_SPI_INT(SPI_INT) (((SPI_INT & 0xFFFFFF00) == 0x0) && (SPI_INT != 0x0)) + + + +#define SPI_FIFO_TX ((u32)0x00000100) +#define SPI_FIFO_RX ((u32)0x00000200) + +#define IS_SPI_FIFO_DIRECTION(DIRECTION) (((DIRECTION & 0xFFFFFCFF) == 0) && (DIRECTION != 0)) + + +#if (LIBCFG_PDMA) +#define SPI_PDMAREQ_TX ((u32)0x00000002) +#define SPI_PDMAREQ_RX ((u32)0x00000004) + +#define IS_SPI_PDMA_REQ(REQ) (((REQ & 0xFFFFFFF9) == 0x0) && (REQ != 0x0)) +#endif + +/* Check parameter of the SIOx input/output direction */ +#if (LIBCFG_QSPI) +#define IS_SIO_DIR(x) (((x) == SIO_DIR_IN) || ((x) == SIO_DIR_OUT)) +#endif + +#define IS_SPI(x) (IS_SPI0(x) || IS_SPI1(x)) +#define IS_SPI0(x) (x == HT_SPI0) +#if (LIBCFG_SPI1) +#define IS_SPI1(x) (x == HT_SPI1) +#else +#define IS_SPI1(x) (0) +#endif +#if (LIBCFG_QSPI) +#define IS_QSPI(x) (x == HT_QSPI) +#else +#define IS_QSPI(x) (0) +#endif + +#if (LIBCFG_SPI_DATA_LENGTH_V01) +#define IS_SPI_DATA(DATA) (DATA <= 0xff) +#else +#define IS_SPI_DATA(DATA) (DATA <= 0xffff) +#endif + +#if (LIBCFG_SPI_FIFO_DEPTH_V01) +#define IS_SPI_FIFO_LEVEL(LEVEL) (LEVEL <= 4) +#else +#define IS_SPI_FIFO_LEVEL(LEVEL) (LEVEL <= 8) +#endif + +#define IS_SPI_CLOCK_PRESCALER(PRESCALER) (PRESCALER >= 2) + +#define SPI_GUADTIME_1_SCK ((u16)0x0000) +#define SPI_GUADTIME_2_SCK ((u16)0x0001) +#define SPI_GUADTIME_3_SCK ((u16)0x0002) +#define SPI_GUADTIME_4_SCK ((u16)0x0003) +#define SPI_GUADTIME_5_SCK ((u16)0x0004) +#define SPI_GUADTIME_6_SCK ((u16)0x0005) +#define SPI_GUADTIME_7_SCK ((u16)0x0006) +#define SPI_GUADTIME_8_SCK ((u16)0x0007) +#define SPI_GUADTIME_9_SCK ((u16)0x0008) +#define SPI_GUADTIME_10_SCK ((u16)0x0009) +#define SPI_GUADTIME_11_SCK ((u16)0x000A) +#define SPI_GUADTIME_12_SCK ((u16)0x000B) +#define SPI_GUADTIME_13_SCK ((u16)0x000C) +#define SPI_GUADTIME_14_SCK ((u16)0x000D) +#define SPI_GUADTIME_15_SCK ((u16)0x000E) +#define SPI_GUADTIME_16_SCK ((u16)0x000F) + +#define IS_SPI_GUADTIME(GUADTIMEPERIOD) ((GUADTIMEPERIOD <= 0x000F)) + + +#define SPI_SELHOLDTIME_HALF_SCK ((u16)0x0000) +#define SPI_SELHOLDTIME_1_SCK ((u16)0x0001) +#define SPI_SELHOLDTIME_1_HALF_SCK ((u16)0x0002) +#define SPI_SELHOLDTIME_2_SCK ((u16)0x0003) +#define SPI_SELHOLDTIME_2_HALF_SCK ((u16)0x0004) +#define SPI_SELHOLDTIME_3_SCK ((u16)0x0005) +#define SPI_SELHOLDTIME_3_HALF_SCK ((u16)0x0006) +#define SPI_SELHOLDTIME_4_SCK ((u16)0x0007) +#define SPI_SELHOLDTIME_4_HALF_SCK ((u16)0x0008) +#define SPI_SELHOLDTIME_5_SCK ((u16)0x0009) +#define SPI_SELHOLDTIME_5_HALF_SCK ((u16)0x000A) +#define SPI_SELHOLDTIME_6_SCK ((u16)0x000B) +#define SPI_SELHOLDTIME_6_HALF_SCK ((u16)0x000C) +#define SPI_SELHOLDTIME_7_SCK ((u16)0x000D) +#define SPI_SELHOLDTIME_7_HALF_SCK ((u16)0x000E) +#define SPI_SELHOLDTIME_8_SCK ((u16)0x000F) + +#define IS_SPI_SELHOLDTIME(SELHOLDTIME) ((SELHOLDTIME <= 0x000F)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI exported functions + * @{ + */ +void SPI_DeInit(HT_SPI_TypeDef* SPIx); +void SPI_Init(HT_SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void SPI_Cmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +#if (!LIBCFG_SPI_NO_MULTI_MASTER) +void SPI_SELOutputCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +#endif +void SPI_FIFOCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void SPI_SetDataLength(HT_SPI_TypeDef* SPIx, u16 SPI_DataLength); +void SPI_SELModeConfig(HT_SPI_TypeDef* SPIx, u32 SPI_SELMode); +void SPI_SoftwareSELCmd(HT_SPI_TypeDef* SPIx, u32 SPI_SoftwareSEL); +void SPI_SendData(HT_SPI_TypeDef* SPIx, SPI_DataTypeDef SPI_Data); +SPI_DataTypeDef SPI_ReceiveData(HT_SPI_TypeDef* SPIx); +void SPI_SetTimeOutValue(HT_SPI_TypeDef* SPIx, SPI_TimeoutTypeDef SPI_Timeout); +void SPI_IntConfig(HT_SPI_TypeDef* SPIx, u32 SPI_Int, ControlStatus NewState); +FlagStatus SPI_GetFlagStatus(HT_SPI_TypeDef* SPIx, u32 SPI_Flag); +u8 SPI_GetFIFOStatus(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection); +void SPI_ClearFlag(HT_SPI_TypeDef* SPIx, u32 SPI_FlagClear); +void SPI_FIFOTriggerLevelConfig(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection, u8 SPI_FIFOLevel); +#if (LIBCFG_PDMA) +void SPI_PDMACmd(HT_SPI_TypeDef* SPIx, u32 SPI_PDMAREQ, ControlStatus NewState); +#endif +#if (!LIBCFG_SPI_NO_DUAL) +void SPI_DUALCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +#endif +void SPI_GUARDTCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void SPI_GUARDTConfig(HT_SPI_TypeDef* SPIx, u32 Guard_Time); +void SPI_SELHTConfig(HT_SPI_TypeDef* SPIx, u32 CS_Hold_Time); +#if (LIBCFG_QSPI) +void QSPI_QuadCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState); +void QSPI_DirectionConfig(HT_SPI_TypeDef* SPIx, SIO_DIR_Enum SIO_DIR_INorOUT); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_spi_midi.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_spi_midi.h new file mode 100644 index 00000000000..9494a08e46a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_spi_midi.h @@ -0,0 +1,204 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_spi_midi.h + * @version $Rev:: 7075 $ + * @date $Date:: 2023-07-31 #$ + * @brief The header file of SPI library (MIDI Control). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_SPI_MIDI_H +#define __HT32F5XXXX_SPI_MIDI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + + +/* Exported typedef ----------------------------------------------------------------------------------------*/ +/** @defgroup SPI_MIDI_Exported_Types QSPI MIDI exported types + * @{ + */ +typedef struct +{ + u32 MIDICTRL_MODE; + u32 MIDICTRL_CommandLength; + u32 MIDICTRL_AddressLength; + u32 MIDICTRL_ModeLength; + u32 MIDICTRL_DummyLength; + u32 MIDICTRL_DataLength; + u32 MIDICTRL_CommandValue; + u32 MIDICTRL_ModeValue; +} MIDICTRL_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Constants SPI exported constants + * @{ + */ +#define QDIOEN_POS (22) +#define SMDEL_POS (6) + +#define DOR_MODE (0UL << QDIOEN_POS | 1UL << SMDEL_POS ) +#define DIOR_MODE (1UL << QDIOEN_POS | 1UL << SMDEL_POS ) +#define QOR_MODE (0UL << QDIOEN_POS | 2UL << SMDEL_POS ) +#define QIOR_MODE (1UL << QDIOEN_POS | 2UL << SMDEL_POS ) +#define QPI_MODE (3UL << SMDEL_POS ) +#define SERIAL_MODE (0UL << SMDEL_POS ) + +/* QSPI Flash Command Field Length -------------------------------------------------------------------------*/ +#define MIDICTRL_CMDLENGTH_0 ((u32)0x00000000) +#define MIDICTRL_CMDLENGTH_1 ((u32)0x01000000) +#define MIDICTRL_CMDLENGTH_2 ((u32)0x02000000) +#define MIDICTRL_CMDLENGTH_3 ((u32)0x03000000) +#define MIDICTRL_CMDLENGTH_4 ((u32)0x04000000) +#define MIDICTRL_CMDLENGTH_5 ((u32)0x05000000) +#define MIDICTRL_CMDLENGTH_6 ((u32)0x06000000) +#define MIDICTRL_CMDLENGTH_7 ((u32)0x07000000) +#define MIDICTRL_CMDLENGTH_8 ((u32)0x08000000) + +/* QSPI FlashAddress Field Length --------------------------------------------------------------------------*/ +#define MIDICTRL_ADLENGTH_0 ((u32)0x00000000) +#define MIDICTRL_ADLENGTH_1 ((u32)0x00010000) +#define MIDICTRL_ADLENGTH_2 ((u32)0x00020000) +#define MIDICTRL_ADLENGTH_3 ((u32)0x00030000) +#define MIDICTRL_ADLENGTH_4 ((u32)0x00040000) +#define MIDICTRL_ADLENGTH_5 ((u32)0x00050000) +#define MIDICTRL_ADLENGTH_6 ((u32)0x00060000) +#define MIDICTRL_ADLENGTH_7 ((u32)0x00070000) +#define MIDICTRL_ADLENGTH_8 ((u32)0x00080000) +#define MIDICTRL_ADLENGTH_9 ((u32)0x00090000) +#define MIDICTRL_ADLENGTH_10 ((u32)0x000A0000) +#define MIDICTRL_ADLENGTH_11 ((u32)0x000B0000) +#define MIDICTRL_ADLENGTH_12 ((u32)0x000C0000) +#define MIDICTRL_ADLENGTH_13 ((u32)0x000D0000) +#define MIDICTRL_ADLENGTH_14 ((u32)0x000E0000) +#define MIDICTRL_ADLENGTH_15 ((u32)0x000F0000) +#define MIDICTRL_ADLENGTH_16 ((u32)0x00100000) +#define MIDICTRL_ADLENGTH_17 ((u32)0x00110000) +#define MIDICTRL_ADLENGTH_18 ((u32)0x00120000) +#define MIDICTRL_ADLENGTH_19 ((u32)0x00130000) +#define MIDICTRL_ADLENGTH_20 ((u32)0x00140000) +#define MIDICTRL_ADLENGTH_21 ((u32)0x00150000) +#define MIDICTRL_ADLENGTH_22 ((u32)0x00160000) +#define MIDICTRL_ADLENGTH_23 ((u32)0x00170000) +#define MIDICTRL_ADLENGTH_24 ((u32)0x00180000) + +/* QSPI Flash Command Field Length -------------------------------------------------------------------------*/ +#define MIDICTRL_MODELENGTH_0 ((u32)0x00000000) +#define MIDICTRL_MODELENGTH_1 ((u32)0x00001000) +#define MIDICTRL_MODELENGTH_2 ((u32)0x00002000) +#define MIDICTRL_MODELENGTH_3 ((u32)0x00003000) +#define MIDICTRL_MODELENGTH_4 ((u32)0x00004000) +#define MIDICTRL_MODELENGTH_5 ((u32)0x00005000) +#define MIDICTRL_MODELENGTH_6 ((u32)0x00006000) +#define MIDICTRL_MODELENGTH_7 ((u32)0x00007000) +#define MIDICTRL_MODELENGTH_8 ((u32)0x00008000) + +/* QSPI Flash Dummy Field Length ---------------------------------------------------------------------------*/ +#define MIDICTRL_DUMMYLENGTH_0 ((u32)0x00000000) +#define MIDICTRL_DUMMYLENGTH_1 ((u32)0x00000100) +#define MIDICTRL_DUMMYLENGTH_2 ((u32)0x00000200) +#define MIDICTRL_DUMMYLENGTH_3 ((u32)0x00000300) +#define MIDICTRL_DUMMYLENGTH_4 ((u32)0x00000400) +#define MIDICTRL_DUMMYLENGTH_5 ((u32)0x00000500) +#define MIDICTRL_DUMMYLENGTH_6 ((u32)0x00000600) +#define MIDICTRL_DUMMYLENGTH_7 ((u32)0x00000700) +#define MIDICTRL_DUMMYLENGTH_8 ((u32)0x00000800) + +/* QSPI Flash Data Field Length ----------------------------------------------------------------------------*/ +#define MIDICTRL_DATALENGTH_0 ((u32)0x00000000) +#define MIDICTRL_DATALENGTH_1 ((u32)0x00000001) +#define MIDICTRL_DATALENGTH_2 ((u32)0x00000002) +#define MIDICTRL_DATALENGTH_3 ((u32)0x00000003) +#define MIDICTRL_DATALENGTH_4 ((u32)0x00000004) +#define MIDICTRL_DATALENGTH_5 ((u32)0x00000005) +#define MIDICTRL_DATALENGTH_6 ((u32)0x00000006) +#define MIDICTRL_DATALENGTH_7 ((u32)0x00000007) +#define MIDICTRL_DATALENGTH_8 ((u32)0x00000008) +#define MIDICTRL_DATALENGTH_9 ((u32)0x00000009) +#define MIDICTRL_DATALENGTH_10 ((u32)0x0000000A) +#define MIDICTRL_DATALENGTH_11 ((u32)0x0000000B) +#define MIDICTRL_DATALENGTH_12 ((u32)0x0000000C) +#define MIDICTRL_DATALENGTH_13 ((u32)0x0000000D) +#define MIDICTRL_DATALENGTH_14 ((u32)0x0000000E) +#define MIDICTRL_DATALENGTH_15 ((u32)0x0000000F) +#define MIDICTRL_DATALENGTH_16 ((u32)0x00000010) +#define MIDICTRL_DATALENGTH_17 ((u32)0x00000011) +#define MIDICTRL_DATALENGTH_18 ((u32)0x00000012) +#define MIDICTRL_DATALENGTH_19 ((u32)0x00000013) +#define MIDICTRL_DATALENGTH_20 ((u32)0x00000014) +#define MIDICTRL_DATALENGTH_21 ((u32)0x00000015) +#define MIDICTRL_DATALENGTH_22 ((u32)0x00000016) +#define MIDICTRL_DATALENGTH_23 ((u32)0x00000017) +#define MIDICTRL_DATALENGTH_24 ((u32)0x00000018) +#define MIDICTRL_DATALENGTH_25 ((u32)0x00000019) +#define MIDICTRL_DATALENGTH_26 ((u32)0x0000001A) +#define MIDICTRL_DATALENGTH_27 ((u32)0x0000001B) +#define MIDICTRL_DATALENGTH_28 ((u32)0x0000001C) +#define MIDICTRL_DATALENGTH_29 ((u32)0x0000001D) +#define MIDICTRL_DATALENGTH_30 ((u32)0x0000001E) +#define MIDICTRL_DATALENGTH_31 ((u32)0x0000001F) +#define MIDICTRL_DATALENGTH_32 ((u32)0x00000020) + +#define MIDICTRL_ON ((u32)0x00800000) +#define MIDICTRL_OFF ((u32)0xFF7FFFFF) + +#define CMDVALUE_POS (8) +#define MDVALUE_POS (0) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI exported functions + * @{ + */ +void MIDICTRL_Cmd(HT_SPI_TypeDef* QSPIx ,ControlStatus NewState); +void MIDICTRL_Init(HT_SPI_TypeDef* QSPIx, MIDICTRL_InitTypeDef* MIDICTRL_InitStruct); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tkey.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tkey.h new file mode 100644 index 00000000000..e51f1292b56 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tkey.h @@ -0,0 +1,311 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_tkey.h + * @version $Rev:: 5483 $ + * @date $Date:: 2021-07-19 #$ + * @brief The header file of the TKEY library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_TKEY_H +#define __HT32F5XXXX_TKEY_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup TKEY + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup TKEY_Exported_Types TKEY exported types + * @{ + */ + +typedef enum +{ /*!< Touch key IP clock source */ + TKEY_PCLK = 0 , /*!< PCLK */ + TKEY_LSI /*!< LSI */ +} TKEY_IP_CLK_Enum; + +typedef enum +{ /*!< Periodic auto scan mode time-out selection */ + TKEY_RefOSC_DelayTime_0 = (0 << 13), /*!< 4 RefOSC clock */ + TKEY_RefOSC_DelayTime_1 = (1 << 13), /*!< 2 RefOSC clock */ + TKEY_RefOSC_DelayTime_2 = (2 << 13), /*!< 4 RefOSC clock */ + TKEY_RefOSC_DelayTime_3 = (3 << 13), /*!< 8 RefOSC clock */ + TKEY_RefOSC_DelayTime_4 = (4 << 13), /*!< 16 RefOSC clock */ + TKEY_RefOSC_DelayTime_5 = (5 << 13), /*!< 32 RefOSC clock */ + TKEY_RefOSC_DelayTime_6 = (6 << 13), /*!< 64 RefOSC clock */ + TKEY_RefOSC_DelayTime_7 = (7 << 13), /*!< 4 RefOSC clock */ +} TKEY_RefOSC_DelayTime_Enum; + + +typedef enum +{ /*!< Periodic auto scan mode time-out selection */ + TKEY_PASM_TIMEOUT_0 = (0 << 10), /*!< 2^13/FLIRC */ + TKEY_PASM_TIMEOUT_1 = (1 << 10), /*!< 2^14/FLIRC */ + TKEY_PASM_TIMEOUT_2 = (2 << 10), /*!< 2^15/FLIRC */ + TKEY_PASM_TIMEOUT_3 = (3 << 10), /*!< 2^16/FLIRC */ + TKEY_PASM_TIMEOUT_4 = (4 << 10), /*!< 2^17/FLIRC */ + TKEY_PASM_TIMEOUT_5 = (5 << 10), /*!< 2^18/FLIRC */ +} TKEY_PASM_TIMEOUT_Enum; + +typedef enum +{ /*!< Periodic auto scan mode period selection */ + TKEY_PASM_PERIOD_0 = (0 << 8), /*!< 2^14/FLIRC */ + TKEY_PASM_PERIOD_1 = (1 << 8), /*!< 2^13/FLIRC */ + TKEY_PASM_PERIOD_2 = (2 << 8), /*!< 2^12/FLIRC */ + TKEY_PASM_PERIOD_3 = (3 << 8), /*!< 2^11/FLIRC */ +} TKEY_PASM_PERIOD_Enum; + +typedef enum +{ /*!< 16-bit counter clock source selection */ + TKEY_TK16S_CLK_0 = (0 << 5), /*!< TKCLK/16 */ + TKEY_TK16S_CLK_1 = (1 << 5), /*!< TKCLK/32 */ + TKEY_TK16S_CLK_2 = (2 << 5), /*!< TKCLK/64 */ + TKEY_TK16S_CLK_3 = (3 << 5), /*!< TKCLK/128 */ +} TKEY_TK16S_CLK_Enum; + +typedef enum +{ /*!< OSC frequency selection */ + TKEY_TKFS_FREQ_0 = (0 << 3), /*!< 1MHz */ + TKEY_TKFS_FREQ_1 = (1 << 3), /*!< 3MHz */ + TKEY_TKFS_FREQ_2 = (2 << 3), /*!< 7MHz */ + TKEY_TKFS_FREQ_3 = (3 << 3), /*!< 11MHz */ +} TKEY_TKFS_FREQ_Enum; + +typedef enum +{ /*!< Mode selection */ + TKEY_MODE_AUTOSCAN = (0 << 1), /*!< Auto scan mode */ + TKEY_MODE_MANUAL = (1 << 1), /*!< Manual mode */ + TKEY_MODE_PASM = (2 << 1), /*!< Periodic auto scan mode */ +} TKEY_MODE_Enum; + +typedef enum +{ /*!< TKEY module selection */ + TKM_0 = 0, /*!< TKEY module 0 */ + TKM_1, /*!< TKEY module 1 */ + TKM_2, /*!< TKEY module 2 */ + TKM_3, /*!< TKEY module 3 */ + TKM_4, /*!< TKEY module 4 */ + TKM_5, /*!< TKEY module 5 */ +} TKM_Enum; + +typedef enum +{ /*!< 8-bit time slot counter clock source */ + TKM_TSS_CLK_0 = (0 << 8), /*!< Ref. OSC */ + TKM_TSS_CLK_1 = (1 << 8), /*!< TKCLK/32 */ + TKM_TSS_CLK_2 = (2 << 8), /*!< TKCLK/64 */ + TKM_TSS_CLK_3 = (3 << 8), /*!< TKCLK/128 */ +} TKM_TSS_CLK_Enum; + +typedef enum +{ /*!< C/F OSC frequency hopping selection */ + TKM_SOF_CTRL_SW = (0 << 3), /*!< S/W controlled frequency hopping */ + TKM_SOF_CTRL_HW = (1 << 3), /*!< H/W controlled frequency hopping */ +} TKM_SOF_CTRL_Enum; + +typedef enum +{ /*!< Key OSC and Ref OSC frequency selection */ + TKM_SOF_FREQ_0 = (0 << 0), /*!< 1.020MHz. */ + TKM_SOF_FREQ_1 = (1 << 0), /*!< 1.040MHz. */ + TKM_SOF_FREQ_2 = (2 << 0), /*!< 1.059MHz. */ + TKM_SOF_FREQ_3 = (3 << 0), /*!< 1.074MHz. */ + TKM_SOF_FREQ_4 = (4 << 0), /*!< 1.085MHz. */ + TKM_SOF_FREQ_5 = (5 << 0), /*!< 1.099MHz. */ + TKM_SOF_FREQ_6 = (6 << 0), /*!< 1.111MHz. */ + TKM_SOF_FREQ_7 = (7 << 0) /*!< 1.125MHz. */ +} TKM_SOF_FREQ_Enum; + +typedef enum +{ /*!< Key selection */ + TKM_KEY_0 = 0, /*!< Key 0 */ + TKM_KEY_1, /*!< Key 1 */ + TKM_KEY_2, /*!< Key 2 */ + TKM_KEY_3, /*!< Key 3 */ +} TKM_KEY_Enum; + +typedef enum +{ /*!< Time slot selection */ + TKM_TIME_SLOT_0 = 0, /*!< Time slot 0 */ + TKM_TIME_SLOT_1, /*!< Time slot 1 */ + TKM_TIME_SLOT_2, /*!< Time slot 2 */ + TKM_TIME_SLOT_3, /*!< Time slot 3 */ +} TKM_TIME_SLOT_Enum; + +typedef enum +{ /*!< Key threshold selection */ + TKM_KEY_THR_LOWER = 0, /*!< Lower threshold */ + TKM_KEY_THR_UPPER, /*!< Upper threshold */ +} TKM_KEY_THR_Enum; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup TKEY_Exported_Constants TKEY exported constants + * @{ + */ +#define IS_TKEY_IP_CLK(x) (((x) == TKEY_PCLK) || ((x) == TKEY_LSI) ) + +#define IS_TKEY_RefOSC_DelayTime(x) (((x) == TKEY_RefOSC_DelayTime_0) || ((x) == TKEY_RefOSC_DelayTime_1) || \ + ((x) == TKEY_RefOSC_DelayTime_2) || ((x) == TKEY_RefOSC_DelayTime_3) || \ + ((x) == TKEY_RefOSC_DelayTime_4) || ((x) == TKEY_RefOSC_DelayTime_5)|| \ + ((x) == TKEY_RefOSC_DelayTime_6) || ((x) == TKEY_RefOSC_DelayTime_7)) + +#define IS_TKEY_PASM_TIMEOUT(x) (((x) == TKEY_PASM_TIMEOUT_0) || ((x) == TKEY_PASM_TIMEOUT_1) || \ + ((x) == TKEY_PASM_TIMEOUT_2) || ((x) == TKEY_PASM_TIMEOUT_3) || \ + ((x) == TKEY_PASM_TIMEOUT_4) || ((x) == TKEY_PASM_TIMEOUT_5)) + +#define IS_TKEY_PASM_PERIOD(x) (((x) == TKEY_PASM_PERIOD_0) || ((x) == TKEY_PASM_PERIOD_1) || \ + ((x) == TKEY_PASM_PERIOD_2) || ((x) == TKEY_PASM_PERIOD_3)) + +#define IS_TKEY_TK16S_CLK(x) (((x) == TKEY_TK16S_CLK_0) || ((x) == TKEY_TK16S_CLK_1) || \ + ((x) == TKEY_TK16S_CLK_2) || ((x) == TKEY_TK16S_CLK_3)) + + +#define IS_TKEY_TKFS_FREQ(x) (((x) == TKEY_TKFS_FREQ_0) || ((x) == TKEY_TKFS_FREQ_1) || \ + ((x) == TKEY_TKFS_FREQ_2) || ((x) == TKEY_TKFS_FREQ_3)) + +#define IS_TKEY_MODE(x) (((x) == TKEY_MODE_AUTOSCAN) || ((x) == TKEY_MODE_MANUAL) || \ + ((x) == TKEY_MODE_PASM)) + +#define TKEY_INT_TKTHE ((u32)0x00000001) +#define TKEY_INT_TKRCOVE ((u32)0x00000002) +#define TKEY_INT_TKTHWUEN ((u32)0x00000004) +#define TKEY_INT_TKRCOVWUEN ((u32)0x00000008) + +#define IS_TKEY_INT(TKEY_INT) (((TKEY_INT & 0xFFFFFFFC) == 0) && (TKEY_INT != 0)) + +#define TKEY_FLAG_TKTHF ((u32)0x00000001) +#define TKEY_FLAG_TKRCOVF ((u32)0x00000002) +#define TKEY_FLAG_TK16OV ((u32)0x00000004) +#define TKEY_FLAG_TKCFOV ((u32)0x00000008) +#define TKEY_FLAG_TKBUSY ((u32)0x00000010) + +#define IS_TKEY_FLAG(FLAG) ((FLAG == TKEY_FLAG_TKTHF) || \ + (FLAG == TKEY_FLAG_TKRCOVF) || \ + (FLAG == TKEY_FLAG_TK16OV) || \ + (FLAG == TKEY_FLAG_TKCFOV) || \ + (FLAG == TKEY_FLAG_TKBUSY)) + + +#define IS_TKEY_FLAG_CLEAR(CLEAR) ((CLEAR == TKEY_FLAG_TKTHF) || \ + (CLEAR == TKEY_FLAG_TKRCOVF) || \ + (CLEAR == TKEY_FLAG_TK16OV) || \ + (CLEAR == TKEY_FLAG_TKCFOV)) + +#define IS_TKM(x) (((x) == TKM_0) || ((x) == TKM_1) || \ + ((x) == TKM_2) || ((x) == TKM_3) || \ + ((x) == TKM_4) || ((x) == TKM_5)) + +#define IS_TKM_TSS_CLK(x) (((x) == TKM_TSS_CLK_0) || ((x) == TKM_TSS_CLK_1) || \ + ((x) == TKM_TSS_CLK_2) || ((x) == TKM_TSS_CLK_3)) + + +#define IS_TKM_SOFC_CTRL(x) (((x) == TKM_SOFC_SW) || ((x) == TKM_SOFC_HW)) + +#define IS_TKM_SOF_FREQ(x) (((x) == TKM_SOF_FREQ_0) || ((x) == TKM_SOF_FREQ_1) || \ + ((x) == TKM_SOF_FREQ_2) || ((x) == TKM_SOF_FREQ_3) || \ + ((x) == TKM_SOF_FREQ_4) || ((x) == TKM_SOF_FREQ_5) || \ + ((x) == TKM_SOF_FREQ_6) || ((x) == TKM_SOF_FREQ_7)) + +#define IS_TKM_KEY(x) (((x) == TKM_KEY_3) || ((x) == TKM_KEY_2) || \ + ((x) == TKM_KEY_1) || ((x) == TKM_KEY_0)) + +#define IS_TKM_SOF_CTRL(x) (((x) == TKM_SOF_CTRL_SW) || ((x) == TKM_SOF_CTRL_HW)) + +#define IS_TKM_TIME_SLOT(x) (((x) == TKM_TIME_SLOT_0) || ((x) == TKM_TIME_SLOT_1) || \ + ((x) == TKM_TIME_SLOT_2) || ((x) == TKM_TIME_SLOT_3)) + +#define IS_TKM_KEY_THR(x) (((x) == TKM_KEY_THR_LOWER) || ((x) == TKM_KEY_THR_UPPER)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup TKEY_Exported_Functions TKEY exported functions + * @{ + */ +void TKEY_DeInit(void); +void TKEY_IPClockConfig(TKEY_IP_CLK_Enum Sel); +void TKEY_RefOSCDelayTimeConfig(TKEY_RefOSC_DelayTime_Enum Sel); +void TKEY_PASMTimeoutConfig(TKEY_PASM_TIMEOUT_Enum Sel); +void TKEY_PASMPeriodConfig(TKEY_PASM_PERIOD_Enum Sel); +void TKEY_16BitCounterClockConfig(TKEY_TK16S_CLK_Enum Sel); +void TKEY_OSCFreqConfig(TKEY_TKFS_FREQ_Enum Sel); +void TKEY_ModeConfig(TKEY_MODE_Enum Sel); +void TKEY_StartCmd(ControlStatus NewState); +void TKEY_IntConfig(u32 TKEY_Int, ControlStatus NewState); +FlagStatus TKEY_GetFlagStatus(u32 TKEY_Flag); +void TKEY_ClearFlag(u32 TKEY_Flag); +u32 TKEY_Get16BitCounterValue(void); +void TKEY_Set8BitCounterReload(u32 Reload); +u32 TKEY_Get8BitCounterReload(void); + +void TKM_TimeSlotCounterClockConfig(TKM_Enum TKMn, TKM_TSS_CLK_Enum Sel); +void TKM_RefOSCCmd(TKM_Enum TKMn, ControlStatus NewState); +void TKM_KeyOSCCmd(TKM_Enum TKMn, ControlStatus NewState); +void TKM_MultiFreqCmd(TKM_Enum TKMn, ControlStatus NewState); +void TKM_SOFCtrlConfig(TKM_Enum TKMn, TKM_SOF_CTRL_Enum Sel); +void TKM_SOFFreqConfig(TKM_Enum TKMn, TKM_SOF_FREQ_Enum Sel); +void TKM_KeyCmd(TKM_Enum TKMn, TKM_KEY_Enum Key, ControlStatus NewState); +void TKM_TimeSlotKeyConfig(TKM_Enum TKMn, TKM_TIME_SLOT_Enum Slot, TKM_KEY_Enum Key); +void TKM_KeyThresholdConfig(TKM_Enum TKMn, TKM_KEY_Enum Key, TKM_KEY_THR_Enum Sel); +FlagStatus TKM_GetMatchFlagStatus(TKM_Enum TKMn, TKM_KEY_Enum Key); +void TKM_ClearMatchFlag(TKM_Enum TKMn, TKM_KEY_Enum Key); +void TKM_SetRefOSCCapacitor(TKM_Enum TKMn, u32 Value); +u32 TKM_GetRefOSCCapacitor(TKM_Enum TKMn); +void TKM_SetKeyCapacitor(TKM_Enum TKMn, TKM_KEY_Enum Key, u32 Value); +u32 TKM_GetKeyCapacitor(TKM_Enum TKMn, TKM_KEY_Enum Key); +u32 TKM_Get16BitCFCounterValue(TKM_Enum TKMn); +u32 TKM_GetKeyCounterValue(TKM_Enum TKMn, TKM_KEY_Enum Key); +void TKM_SetKeyThreshold(TKM_Enum TKMn, TKM_KEY_Enum Key, u32 Value); +u32 TKM_GetKeyThreshold(TKM_Enum TKMn, TKM_KEY_Enum Key); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm.h new file mode 100644 index 00000000000..eb0d814f23f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm.h @@ -0,0 +1,942 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_tm.h + * @version $Rev:: 7319 $ + * @date $Date:: 2023-10-28 #$ + * @brief The header file of the TM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_TM_H +#define __HT32F5XXXX_TM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup TM + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Types TM exported types + * @{ + */ +/** + * @brief Enumeration of TM counter mode. + */ +typedef enum +{ + TM_CNT_MODE_UP = 0x00000000, /*!< Edge up-counting mode */ + TM_CNT_MODE_CA1 = 0x00010000, /*!< Center-align mode 1 */ + TM_CNT_MODE_CA2 = 0x00020000, /*!< Center-align mode 2 */ + TM_CNT_MODE_CA3 = 0x00030000, /*!< Center-align mode 3 */ + TM_CNT_MODE_DOWN = 0x01000000 /*!< Edge down-counting mode */ +} TM_CNT_MODE_Enum; +/** + * @brief Enumeration of TM prescaler reload time. + */ +typedef enum +{ + TM_PSC_RLD_UPDATE = 0x0000, /*!< Reload prescaler at next update event */ + TM_PSC_RLD_IMMEDIATE = 0x0100 /*!< Reload prescaler immediately */ +} TM_PSC_RLD_Enum; +/** + * @brief Enumeration of TM channel output mode. + */ +typedef enum +{ + TM_OM_MATCH_NOCHANGE = 0x0000, /*!< TM channel output no change on match */ + TM_OM_MATCH_INACTIVE = 0x0001, /*!< TM channel output inactive level on match */ + TM_OM_MATCH_ACTIVE = 0x0002, /*!< TM channel output active level on match */ + TM_OM_MATCH_TOGGLE = 0x0003, /*!< TM channel output toggle on match */ + TM_OM_FORCED_INACTIVE = 0x0004, /*!< TM channel output forced inactive level */ + TM_OM_FORCED_ACTIVE = 0x0005, /*!< TM channel output forced active level */ + TM_OM_PWM1 = 0x0006, /*!< TM channel pwm1 output mode */ + TM_OM_PWM2 = 0x0007, /*!< TM channel pwm2 output mode */ + TM_OM_ASYMMETRIC_PWM1 = 0x0106, /*!< TM channel asymmetric pwm1 output mode */ + TM_OM_ASYMMETRIC_PWM2 = 0x0107 /*!< TM channel asymmetric pwm2 output mode */ +} TM_OM_Enum; +/** + * @brief Enumeration of TM channel capture source selection. + */ +typedef enum +{ + TM_CHCCS_DIRECT = 0x00010000, /*!< TM channel capture selection direct input */ + TM_CHCCS_INDIRECT = 0x00020000, /*!< TM channel capture selection indirect input */ + TM_CHCCS_TRCED = 0x00030000 /*!< TM channel capture selection TRCED of trigger control block */ +} TM_CHCCS_Enum; +/** + * @brief Enumeration of TM channel capture prescaler. + */ +typedef enum +{ + TM_CHPSC_OFF = 0x00000000, /*!< TM channel capture no prescaler, capture is done each event */ + TM_CHPSC_2 = 0x00040000, /*!< TM channel capture is done once every 2 event */ + TM_CHPSC_4 = 0x00080000, /*!< TM channel capture is done once every 4 event */ + TM_CHPSC_8 = 0x000C0000 /*!< TM channel capture is done once every 8 event */ +} TM_CHPSC_Enum; +#if (LIBCFG_TM_652XX_V1) +/** + * @brief Enumeration of TM channel Filter (Fsampling) Clock Divider. + */ +typedef enum +{ + TM_CHFDIV_1 = 0x00000000, /*!< TM channel Filter Fsampling = Fdts */ + TM_CHFDIV_2 = 0x00000001, /*!< TM channel Filter Fsampling = Fdts/2 */ + TM_CHFDIV_4 = 0x00000002, /*!< TM channel Filter Fsampling = Fdts/4 */ + TM_CHFDIV_8 = 0x00000003, /*!< TM channel Filter Fsampling = Fdts/8 */ + TM_CHFDIV_16 = 0x00000004, /*!< TM channel Filter Fsampling = Fdts/16 */ + TM_CHFDIV_32 = 0x00000005, /*!< TM channel Filter Fsampling = Fdts/32 */ + TM_CHFDIV_64 = 0x00000006 /*!< TM channel Filter Fsampling = Fdts/64 */ +} TM_CHFDIV_Enum; +/** + * @brief Enumeration of TM channel Filter N-event counter + */ +#if (LIBCFG_TM_TIFN_5BIT) +typedef enum +{ + TM_CHFEV_OFF = 0, /*!< TM channel Filter off */ + TM_CHFEV_1, /*!< TM channel Filter n event counter Setting */ + TM_CHFEV_2, + TM_CHFEV_3, + TM_CHFEV_4, + TM_CHFEV_5, + TM_CHFEV_6, + TM_CHFEV_7, + TM_CHFEV_8, + TM_CHFEV_9, + TM_CHFEV_10, + TM_CHFEV_11, + TM_CHFEV_12, + TM_CHFEV_13, + TM_CHFEV_14, + TM_CHFEV_15, + TM_CHFEV_16, + TM_CHFEV_17, + TM_CHFEV_18, + TM_CHFEV_19, + TM_CHFEV_20, + TM_CHFEV_21, + TM_CHFEV_22, + TM_CHFEV_23, + TM_CHFEV_24, + TM_CHFEV_25, + TM_CHFEV_26, + TM_CHFEV_27, + TM_CHFEV_28, + TM_CHFEV_29, + TM_CHFEV_30, + TM_CHFEV_31, +} TM_CHFEV_Enum; +#else +typedef enum +{ + TM_CHFEV_OFF = 0x00000000, /*!< TM channel Filter off */ + TM_CHFEV_2 = 0x00000001, /*!< TM channel Filter 2 event counter Setting */ + TM_CHFEV_4 = 0x00000002, /*!< TM channel Filter 4 event counter Setting */ + TM_CHFEV_8 = 0x00000003, /*!< TM channel Filter 8 event counter Setting */ + TM_CHFEV_12 = 0x00000004, /*!< TM channel Filter 12 event counter Setting */ + TM_CHFEV_16 = 0x00000005 /*!< TM channel Filter 16 event counter Setting */ +} TM_CHFEV_Enum; +#endif +#endif +/** + * @brief Enumeration of TM fDTS clock divider. + */ +typedef enum +{ + TM_CKDIV_OFF = 0x0000, /*!< fDTS = fCLKIN */ + TM_CKDIV_2 = 0x0100, /*!< fDTS = fCLKIN / 2 */ + TM_CKDIV_4 = 0x0200, /*!< fDTS = fCLKIN / 4 */ + #if (LIBCFG_TM_652XX_V1 || LIBCFG_TM_CKDIV_8) + TM_CKDIV_8 = 0x0300, /*!< fDTS = fCLKIN / 8 */ + #endif +} TM_CKDIV_Enum; +#if 0 +/** + * @brief Enumeration of TM ETI input prescaler. + */ +typedef enum +{ + TM_ETIPSC_OFF = 0x00000000, /*!< ETI prescaler off */ + TM_ETIPSC_2 = 0x00001000, /*!< ETIP frequency divided by 2 */ + TM_ETIPSC_4 = 0x00002000, /*!< ETIP frequency divided by 4 */ + TM_ETIPSC_8 = 0x00003000 /*!< ETIP frequency divided by 8 */ +} TM_ETIPSC_Enum; +/** + * @brief Enumeration of TM ETI input polarity. + */ +typedef enum +{ + TM_ETIPOL_NONINVERTED = 0x00000000, /*!< TM ETI polarity is active high or rising edge */ + TM_ETIPOL_INVERTED = 0x00010000 /*!< TM ETI polarity is active low or falling edge */ +} TM_ETIPOL_Enum; +#endif +/** + * @brief Enumeration of TM slave trigger input selection. + */ +typedef enum +{ + TM_TRSEL_UEVG = 0x0, /*!< Software trigger by setting UEVG bit */ + TM_TRSEL_TI0S0 = 0x1, /*!< Filtered channel 0 input */ + TM_TRSEL_TI1S1 = 0x2, /*!< Filtered channel 1 input */ + TM_TRSEL_ETIF = 0x3, /*!< External Trigger input */ + TM_TRSEL_TI0BED = 0x8, /*!< Trigger input 0 both edge detector */ +#if (LIBCFG_TM_NO_ITI == 1) + #define IS_TRSEL_ITI0(x) (0) + #define IS_TRSEL_ITI1(x) (0) + #define IS_TRSEL_ITI2(x) (0) +#else + TM_TRSEL_ITI0 = 0x9, /*!< Internal trigger input 0 */ + TM_TRSEL_ITI1 = 0xA, /*!< Internal trigger input 1 */ + TM_TRSEL_ITI2 = 0xB /*!< Internal trigger input 2 */ + #define IS_TRSEL_ITI0(x) (x == TM_TRSEL_ITI0) + #define IS_TRSEL_ITI1(x) (x == TM_TRSEL_ITI1) + #define IS_TRSEL_ITI2(x) (x == TM_TRSEL_ITI2) +#endif +} TM_TRSEL_Enum; +/** + * @brief Enumeration of TM slave mode selection. + */ +typedef enum +{ + TM_SMSEL_DISABLE = 0x0000, /*!< The prescaler is clocked directly by the internal clock */ + TM_SMSEL_DECODER1 = 0x0100, /*!< Counter counts up/down on CH0 edge depending on CH1 level */ + TM_SMSEL_DECODER2 = 0x0200, /*!< Counter counts up/down on CH1 edge depending on CH0 level */ + TM_SMSEL_DECODER3 = 0x0300, /*!< Counter counts up/down on both CH0 & CH1 edges depending on the + level of the other input */ + TM_SMSEL_RESTART = 0x0400, /*!< Slave restart mode */ + TM_SMSEL_PAUSE = 0x0500, /*!< Slave pause mode */ + TM_SMSEL_TRIGGER = 0x0600, /*!< Slave trigger mode */ + TM_SMSEL_STIED = 0x0700, /*!< Rising edge of the selected trigger(STI) clock the counter */ + #if (LIBCFG_TM_652XX_V1) + TM_SMSEL_DECODER4 = 0x0800, /*!< Pluse/Direction mode(Counter counts on Ch0, Count up/down on Ch1 */ + #endif +} TM_SMSEL_Enum; +/** + * @brief Enumeration of TM master mode selection. + */ +typedef enum +{ + TM_MMSEL_RESET = 0x00000000, /*!< Send trigger signal when S/W setting UEVG or slave restart */ + TM_MMSEL_ENABLE = 0x00010000, /*!< The counter enable signal is used as trigger output. */ + TM_MMSEL_UPDATE = 0x00020000, /*!< The update event is used as trigger output. */ + TM_MMSEL_CH0CC = 0x00030000, /*!< Channel 0 capture or compare match occurred as trigger output. */ + TM_MMSEL_CH0OREF = 0x00040000, /*!< The CH0OREF signal is used as trigger output. */ + TM_MMSEL_CH1OREF = 0x00050000, /*!< The CH1OREF signal is used as trigger output. */ + TM_MMSEL_CH2OREF = 0x00060000, /*!< The CH2OREF signal is used as trigger output. */ + TM_MMSEL_CH3OREF = 0x00070000, /*!< The CH3OREF signal is used as trigger output. */ + #if (LIBCFG_TM_652XX_V1) + TM_MMSEL_VCLK = 0x000C0000 /*!< The VCLK signal is used as trigger output. */ + #endif + #if (LIBCFG_PWM_8_CHANNEL) + TM_MMSEL_CH4OREF = 0x00080000, /*!< The CH4OREF signal is used as trigger output. */ + TM_MMSEL_CH5OREF = 0x00090000, /*!< The CH5OREF signal is used as trigger output. */ + TM_MMSEL_CH6OREF = 0x000A0000, /*!< The CH6OREF signal is used as trigger output. */ + TM_MMSEL_CH7OREF = 0x000B0000 /*!< The CH7OREF signal is used as trigger output. */ + #endif +} TM_MMSEL_Enum; +#if (LIBCFG_PDMA) +/** + * @brief Enumeration of TM channel Capture / Compare PDMA selection. + */ +typedef enum +{ + TM_CHCCDS_CHCCEV = 0, /*!< Send CHx PDMA request when channel capture/compare event occurs */ + TM_CHCCDS_UEV /*!< Send CHx PDMA request when update event occurs */ +} TM_CHCCDS_Enum; +#endif +/** + * @brief Definition of TM timebase init structure. + */ +typedef struct +{ + u16 CounterReload; /*!< Period (Value for CRR register) */ +#if(LIBCFG_TM_PRESCALER_8BIT) + u8 Prescaler; /*!< Prescaler (Value for PSCR register) */ +#else + u16 Prescaler; /*!< Prescaler (Value for PSCR register) */ +#endif + u8 RepetitionCounter; /*!< Repetition counter */ + TM_CNT_MODE_Enum CounterMode; /*!< Counter mode refer to \ref TM_CNT_MODE_Enum */ + TM_PSC_RLD_Enum PSCReloadTime; /*!< Prescaler reload mode refer to \ref TM_PSC_RLD_Enum */ +} TM_TimeBaseInitTypeDef; +/** + * @brief Definition of TM channel output init structure. + */ +typedef struct +{ + TM_CH_Enum Channel; /*!< Channel selection refer to \ref TM_CH_Enum */ + TM_OM_Enum OutputMode; /*!< Channel output mode selection refer to \ref TM_OM_Enum */ + TM_CHCTL_Enum Control; /*!< CHxO output state refer to \ref TM_CHCTL_Enum */ + TM_CHCTL_Enum ControlN; /*!< CHxO output state refer to \ref TM_CHCTL_Enum */ + TM_CHP_Enum Polarity; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + TM_CHP_Enum PolarityN; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + MCTM_OIS_Enum IdleState; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + MCTM_OIS_Enum IdleStateN; /*!< CHxO polarity refer to \ref TM_CHP_Enum */ + u16 Compare; /*!< Value for CHxCCR register */ + u16 AsymmetricCompare; /*!< Value for CHxACR register */ +} TM_OutputInitTypeDef; +/** + * @brief Definition of TM channel input init structure. + */ +typedef struct +{ + TM_CH_Enum Channel; /*!< Channel selection refer to \ref TM_CH_Enum */ + TM_CHP_Enum Polarity; /*!< Channel input polarity refer to \ref TM_CHP_Enum */ + TM_CHCCS_Enum Selection; /*!< Channel capture source selection refer to \ref TM_CHCCS_Enum */ + TM_CHPSC_Enum Prescaler; /*!< Channel Capture prescaler refer to \ref TM_CHPSC_Enum */ + #if (LIBCFG_TM_652XX_V1) + TM_CHFDIV_Enum Fsampling; /*!< Digital filter Fsampling Frequency, it must fDTS/1 ~ fDTS/64 */ + #if (LIBCFG_TM_TIFN_5BIT) + u8 Event; /*!< Digital filter N-event counter Setting, it must be 0 ~ 31 */ + #else + TM_CHFEV_Enum Event; /*!< Digital filter N-event counter Setting, it must be 0, 2, 4, 8, 12, 16 */ + #endif + #else + u8 Filter; /*!< Digital filter Configuration, it must between 0x0 ~ 0xF. */ + #endif +} TM_CaptureInitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Constants TM exported constants + * @{ + */ + +/** @defgroup TM_INT Definitions of TM_INT + * @{ + */ +#define TM_INT_CH0CC 0x0001 /*!< Channel 0 capture/compare interrupt */ +#define TM_INT_CH1CC 0x0002 /*!< Channel 1 capture/compare interrupt */ +#define TM_INT_CH2CC 0x0004 /*!< Channel 2 capture/compare interrupt */ +#define TM_INT_CH3CC 0x0008 /*!< Channel 3 capture/compare interrupt */ +#if (LIBCFG_PWM_8_CHANNEL) +#define TM_INT_CH4CC 0x10000000ul /*!< Channel 4 compare interrupt */ +#define TM_INT_CH5CC 0x20000000ul /*!< Channel 5 compare interrupt */ +#define TM_INT_CH6CC 0x40000000ul /*!< Channel 6 compare interrupt */ +#define TM_INT_CH7CC 0x80000000ul /*!< Channel 7 compare interrupt */ +#endif +#define TM_INT_UEV 0x0100 /*!< Update interrupt */ +#define TM_INT_UEV2 0x0200 /*!< Update interrupt 2 */ +#define TM_INT_TEV 0x0400 /*!< Trigger interrupt */ +#define TM_INT_BRKEV 0x0800 /*!< Break interrupt */ + +#if (LIBCFG_TM_652XX_V1) +#define MCTM_INT_CH0CD 0x100000 /*!< Channel 0 Count-Down compare interrupt */ +#define MCTM_INT_CH1CD 0x200000 /*!< Channel 1 Count-Down compare interrupt */ +#define MCTM_INT_CH2CD 0x400000 /*!< Channel 2 Count-Down compare interrupt */ +#define MCTM_INT_CH3CD 0x800000 /*!< Channel 3 Count-Down compare interrupt */ + +#define TM_INT_VC 0x1000 /*!< Quadrature Decoder VCLK interrupt */ +#define TM_INT_QC 0x2000 /*!< Quadrature Decoder CLKPULSE interrupt */ +#define TM_INT_PE 0x4000 /*!< Quadrature Decoder Phase Error interrupt */ +#define TM_INT_DC 0x8000 /*!< Quadrature Decoder Direction Change interrupt */ + +#define MCTM_INT_OVER 0x2000 /*!< Counter overflow interrupt */ +#define MCTM_INT_UNDER 0x4000 /*!< Counter underflow Interrupt */ +#if (LIBCFG_TM_65232) +#define MCTM_INT_RECCDIF 0x8000 /*!< CCIF or CDIF Interrupt flag control by REPR */ +#endif + +#endif +/** + * @} + */ + +#if (LIBCFG_PDMA) +/** @defgroup TM_PDMA Definitions of TM_PDMA + * @{ + */ +#define TM_PDMA_CH0CC 0x00010000 /*!< Channel 0 capture/compare PDMA request */ +#define TM_PDMA_CH1CC 0x00020000 /*!< Channel 1 capture/compare PDMA request */ +#define TM_PDMA_CH2CC 0x00040000 /*!< Channel 2 capture/compare PDMA request */ +#define TM_PDMA_CH3CC 0x00080000 /*!< Channel 3 capture/compare PDMA request */ +#define TM_PDMA_UEV 0x01000000 /*!< Update PDMA request */ +#define TM_PDMA_UEV2 0x02000000 /*!< Update 2 PDMA request */ +#define TM_PDMA_TEV 0x04000000 /*!< Trigger PDMA request */ +/** + * @} + */ +#endif + +/** @defgroup TM_EVENT Definitions of TM_EVENT + * @{ + */ +#define TM_EVENT_CH0CC 0x0001 /*!< Channel 0 capture/compare event */ +#define TM_EVENT_CH1CC 0x0002 /*!< Channel 1 capture/compare event */ +#define TM_EVENT_CH2CC 0x0004 /*!< Channel 2 capture/compare event */ +#define TM_EVENT_CH3CC 0x0008 /*!< Channel 3 capture/compare event */ +#if (LIBCFG_PWM_8_CHANNEL) +#define TM_EVENT_CH4CC 0x10000000ul /*!< Channel 4 compare event */ +#define TM_EVENT_CH5CC 0x20000000ul /*!< Channel 5 compare event */ +#define TM_EVENT_CH6CC 0x40000000ul /*!< Channel 6 compare event */ +#define TM_EVENT_CH7CC 0x80000000ul /*!< Channel 7 compare event */ +#endif +#define TM_EVENT_UEV 0x0100 /*!< Update event */ +#define TM_EVENT_UEV2 0x0200 /*!< Update event 2 */ +#define TM_EVENT_TEV 0x0400 /*!< Trigger event */ +#define TM_EVENT_BRKEV 0x0800 /*!< Break event */ +/** + * @} + */ + +/** @defgroup TM_FLAG Definitions of TM_FLAG + * @{ + */ +#define TM_FLAG_CH0CC 0x0001 /*!< Channel 0 capture/compare flag */ +#define TM_FLAG_CH1CC 0x0002 /*!< Channel 1 capture/compare flag */ +#define TM_FLAG_CH2CC 0x0004 /*!< Channel 2 capture/compare flag */ +#define TM_FLAG_CH3CC 0x0008 /*!< Channel 3 capture/compare flag */ +#if (LIBCFG_PWM_8_CHANNEL) +#define TM_FLAG_CH4CC 0x10000000ul /*!< Channel 4 compare flag */ +#define TM_FLAG_CH5CC 0x20000000ul /*!< Channel 5 compare flag */ +#define TM_FLAG_CH6CC 0x40000000ul /*!< Channel 6 compare flag */ +#define TM_FLAG_CH7CC 0x80000000ul /*!< Channel 7 compare flag */ +#endif +#define TM_FLAG_CH0OC 0x0010 /*!< Channel 0 over capture flag */ +#define TM_FLAG_CH1OC 0x0020 /*!< Channel 1 over capture flag */ +#define TM_FLAG_CH2OC 0x0040 /*!< Channel 2 over capture flag */ +#define TM_FLAG_CH3OC 0x0080 /*!< Channel 3 over capture flag */ +#define TM_FLAG_UEV 0x0100 /*!< Update flag */ +#define TM_FLAG_UEV2 0x0200 /*!< Update 2 flag */ +#define TM_FLAG_TEV 0x0400 /*!< Trigger flag */ +#define TM_FLAG_BRK0 0x0800 /*!< Break 0 flag */ +#define TM_FLAG_BRK1 0x1000 /*!< Break 1 flag */ +/** + * @} + */ + +/** @defgroup TM_Check_Parameter Check parameter + * @{ + */ + +/** + * @brief Used to check parameter of the TMx. + */ +#define IS_TM(x) (IS_GPTM0(x) || IS_GPTM1(x) || IS_MCTM0(x) || IS_PWM0(x) || IS_PWM1(x) || IS_PWM2(x) || IS_SCTM(x)) +#if (!LIBCFG_NO_GPTM0) +#define IS_GPTM0(x) (x == HT_GPTM0) +#else +#define IS_GPTM0(x) (0) +#endif + +#if (LIBCFG_GPTM1) +#define IS_GPTM1(x) (x == HT_GPTM1) +#else +#define IS_GPTM1(x) (0) +#endif + +#if (LIBCFG_MCTM0) +#define IS_MCTM0(x) (x == HT_MCTM0) +#else +#define IS_MCTM0(x) (0) +#endif + +#if (LIBCFG_PWM0) +#define IS_PWM0(x) (x == HT_PWM0) +#else +#define IS_PWM0(x) (0) +#endif + +#if (LIBCFG_PWM1) +#define IS_PWM1(x) (x == HT_PWM1) +#else +#define IS_PWM1(x) (0) +#endif + +#if (LIBCFG_PWM2) +#define IS_PWM2(x) (x == HT_PWM2) +#else +#define IS_PWM2(x) (0) +#endif + +#define IS_SCTM(x) (IS_SCTM0(x) || IS_SCTM1(x) || IS_SCTM2(x) || IS_SCTM3(x)) + +#define IS_SCTM0(x) (0) +#define IS_SCTM1(x) (0) +#define IS_SCTM2(x) (0) +#define IS_SCTM3(x) (0) + +#if (LIBCFG_SCTM0) +#undef IS_SCTM0 +#define IS_SCTM0(x) (x == HT_SCTM0) +#endif + +#if (LIBCFG_SCTM1) +#undef IS_SCTM1 +#define IS_SCTM1(x) (x == HT_SCTM1) +#endif + +#if (LIBCFG_SCTM2) +#undef IS_SCTM2 +#define IS_SCTM2(x) (x == HT_SCTM2) +#endif + +#if (LIBCFG_SCTM3) +#undef IS_SCTM3 +#define IS_SCTM3(x) (x == HT_SCTM3) +#endif + +/** + * @brief Used to check parameter of the output compare mode. + */ +#define IS_TM_OM_CMP(x) (((x) == TM_OM_MATCH_NOCHANGE) || \ + ((x) == TM_OM_MATCH_INACTIVE) || \ + ((x) == TM_OM_MATCH_ACTIVE) || \ + ((x) == TM_OM_MATCH_TOGGLE) || \ + ((x) == TM_OM_PWM1) || \ + ((x) == TM_OM_PWM2)) +/** + * @brief Used to check parameter of the output mode. + */ +#define IS_TM_OM(x) (((x) == TM_OM_MATCH_NOCHANGE) || \ + ((x) == TM_OM_MATCH_INACTIVE) || \ + ((x) == TM_OM_MATCH_ACTIVE) || \ + ((x) == TM_OM_MATCH_TOGGLE) || \ + ((x) == TM_OM_PWM1) || \ + ((x) == TM_OM_PWM2) || \ + ((x) == TM_OM_FORCED_INACTIVE) || \ + ((x) == TM_OM_FORCED_ACTIVE) || \ + ((x) == TM_OM_ASYMMETRIC_PWM1) || \ + ((x) == TM_OM_ASYMMETRIC_PWM2)) + +#define IS_TM_OM_NOASYM(x) (((x) == TM_OM_MATCH_NOCHANGE) || \ + ((x) == TM_OM_MATCH_INACTIVE) || \ + ((x) == TM_OM_MATCH_ACTIVE) || \ + ((x) == TM_OM_MATCH_TOGGLE) || \ + ((x) == TM_OM_PWM1) || \ + ((x) == TM_OM_PWM2) || \ + ((x) == TM_OM_FORCED_INACTIVE) || \ + ((x) == TM_OM_FORCED_ACTIVE)) +/** + * @brief Used to check parameter of the channel. + */ +#define IS_TM_CH_0(x) (x == TM_CH_0) +#define IS_TM_CH_1(x) (x == TM_CH_1) +#define IS_TM_CH_2(x) (x == TM_CH_2) +#define IS_TM_CH_3(x) (x == TM_CH_3) +#if (LIBCFG_PWM_8_CHANNEL) +#define IS_TM_CH_4(x) (x == TM_CH_4) +#define IS_TM_CH_5(x) (x == TM_CH_5) +#define IS_TM_CH_6(x) (x == TM_CH_6) +#define IS_TM_CH_7(x) (x == TM_CH_7) +#else +#define IS_TM_CH_4(x) (0) +#define IS_TM_CH_5(x) (0) +#define IS_TM_CH_6(x) (0) +#define IS_TM_CH_7(x) (0) +#endif +#define IS_TM_CH(x) (IS_TM_CH_0(x) || IS_TM_CH_1(x) || \ + IS_TM_CH_2(x) || IS_TM_CH_3(x) || \ + IS_TM_CH_4(x) || IS_TM_CH_5(x) || \ + IS_TM_CH_6(x) || IS_TM_CH_7(x) ) + +/** + * @brief Used to check parameter of the channel for PWM input function. + */ +#define IS_TM_CH_PWMI(x) (((x) == TM_CH_0) || ((x) == TM_CH_1)) +/** + * @brief Used to check parameter of the clock divider. + */ +#define IS_TM_CKDIV_OFF(x) (x == TM_CKDIV_OFF) +#define IS_TM_CKDIV_2(x) (x == TM_CKDIV_2) +#define IS_TM_CKDIV_4(x) (x == TM_CKDIV_4) + +#if (LIBCFG_TM_CKDIV_8) +#define IS_TM_CKDIV_8(x) (x == TM_CKDIV_8) +#else +#define IS_TM_CKDIV_8(x) (0) +#endif + +#define IS_TM_CKDIV(x) (IS_TM_CKDIV_OFF(x) || \ + IS_TM_CKDIV_2(x) || \ + IS_TM_CKDIV_4(x) || \ + IS_TM_CKDIV_8(x)) +/** + * @brief Used to check parameter of the counter mode. + */ +#define IS_TM_CNT_MODE(x) ((x == TM_CNT_MODE_UP) || \ + (x == TM_CNT_MODE_CA1) || \ + (x == TM_CNT_MODE_CA2) || \ + (x == TM_CNT_MODE_CA3) || \ + (x == TM_CNT_MODE_DOWN)) +/** + * @brief Used to check parameter of the channel polarity. + */ +#define IS_TM_CHP(x) ((x == TM_CHP_NONINVERTED) || (x == TM_CHP_INVERTED)) +/** + * @brief Used to check parameter of the channel control. + */ +#define IS_TM_CHCTL(x) ((x == TM_CHCTL_DISABLE) || (x == TM_CHCTL_ENABLE)) +/** + * @brief Used to check parameter of the channel capture / compare PDMA selection. + */ +#define IS_TM_CHCCDS(x) ((x == TM_CHCCDS_CHCCEV) || (x == TM_CHCCDS_UEV)) +/** + * @brief Used to check parameter of the channel input selection. + */ +#define IS_TM_CHCCS(x) ((x == TM_CHCCS_DIRECT) || \ + (x == TM_CHCCS_INDIRECT) || \ + (x == TM_CHCCS_TRCED)) +/** + * @brief Used to check parameter of the channel capture prescaler. + */ +#define IS_TM_CHPSC(x) ((x == TM_CHPSC_OFF) || \ + (x == TM_CHPSC_2) || \ + (x == TM_CHPSC_4) || \ + (x == TM_CHPSC_8)) +#if 0 +/** + * @brief Used to check parameter of the ETI prescaler. + */ +#define IS_TM_ETIPSC(x) ((x == TM_ETIPSC_OFF) || \ + (x == TM_ETIPSC_2) || \ + (x == TM_ETIPSC_4) || \ + (x == TM_ETIPSC_8)) +#endif +/** + * @brief Used to check parameter of the TM interrupt. + */ +#define IS_TM_INT(x) (((x & 0xFF0F10F0) == 0x0) && (x != 0)) +/** + * @brief Used to check parameter of the TM PDMA request. + */ +#define IS_TM_PDMA(x) (((x & 0xFAF0FFFF) == 0x0) && (x != 0)) +/** + * @brief Used to check parameter of the TM interrupt for \ref TM_GetIntStatus function. + */ +#define IS_TM_INT_CH0CC(x) (x == TM_INT_CH0CC) +#define IS_TM_INT_CH1CC(x) (x == TM_INT_CH1CC) +#define IS_TM_INT_CH2CC(x) (x == TM_INT_CH2CC) +#define IS_TM_INT_CH3CC(x) (x == TM_INT_CH3CC) +#if (LIBCFG_PWM_8_CHANNEL) +#define IS_TM_INT_CH4CC(x) (x == TM_INT_CH4CC) +#define IS_TM_INT_CH5CC(x) (x == TM_INT_CH5CC) +#define IS_TM_INT_CH6CC(x) (x == TM_INT_CH6CC) +#define IS_TM_INT_CH7CC(x) (x == TM_INT_CH7CC) +#else +#define IS_TM_INT_CH4CC(x) (0) +#define IS_TM_INT_CH5CC(x) (0) +#define IS_TM_INT_CH6CC(x) (0) +#define IS_TM_INT_CH7CC(x) (0) +#endif +#define IS_TM_INT_UEV(x) (x == TM_INT_UEV) +#define IS_TM_INT_UEV2(x) (x == TM_INT_UEV2) +#define IS_TM_INT_TEV(x) (x == TM_INT_TEV) +#define IS_TM_INT_BRKEV(x) (x == TM_INT_BRKEV) +#define IS_TM_GET_INT(x) (IS_TM_INT_CH0CC(x) || \ + IS_TM_INT_CH1CC(x) || \ + IS_TM_INT_CH2CC(x) || \ + IS_TM_INT_CH3CC(x) || \ + IS_TM_INT_CH4CC(x) || \ + IS_TM_INT_CH5CC(x) || \ + IS_TM_INT_CH6CC(x) || \ + IS_TM_INT_CH7CC(x) || \ + IS_TM_INT_UEV(x) || \ + IS_TM_INT_UEV2(x) || \ + IS_TM_INT_TEV(x) || \ + IS_TM_INT_BRKEV(x)) + +/** + * @brief Used to check parameter of the TM STI selection. + */ +#define IS_TM_TRSEL(x) ((x == TM_TRSEL_UEVG) || \ + (x == TM_TRSEL_TI0S0) || \ + (x == TM_TRSEL_TI1S1) || \ + (x == TM_TRSEL_ETIF) || \ + (x == TM_TRSEL_TI0BED) || \ + IS_TRSEL_ITI0(x) || \ + IS_TRSEL_ITI1(x) || \ + IS_TRSEL_ITI2(x)) +/** + * @brief Used to check parameter of the ITI. + */ +#if (LIBCFG_TM_NO_ITI == 1) +#else +#define IS_TM_ITI(x) ((x == TM_TRSEL_ITI0) || (x == TM_TRSEL_ITI1) || (x == TM_TRSEL_ITI2)) +#endif +/** + * @brief Used to check parameter of the TM_TRSEL for \ref TM_ChExternalClockConfig function. + */ +#define IS_TM_TRSEL_CH(x) ((x == TM_TRSEL_TI0S0) || (x == TM_TRSEL_TI1S1) || \ + (x == TM_TRSEL_TI0BED)) +/** + * @brief Used to check parameter of the TM ETI polarity. + */ +#define IS_TM_ETIPOL(x) ((x == TM_ETIPOL_NONINVERTED) || (x == TM_ETIPOL_INVERTED)) +/** + * @brief Used to check parameter of the TM prescaler reload time. + */ +#define IS_TM_PSC_RLD(x) ((x == TM_PSC_RLD_UPDATE) || (x == TM_PSC_RLD_IMMEDIATE)) +/** + * @brief Used to check parameter of the forced action. + */ +#define IS_TM_OM_FORCED(x) ((x == TM_OM_FORCED_ACTIVE) || (x == TM_OM_FORCED_INACTIVE)) +/** + * @brief Used to check parameter of the decoder mode. + */ +#define IS_TM_SMSEL_DECODER(x) ((x == TM_SMSEL_DECODER1) || (x == TM_SMSEL_DECODER2) || \ + (x == TM_SMSEL_DECODER3)) +/** + * @brief Used to check parameter of the event. + */ +#define IS_TM_EVENT(x) (((x & 0xFFFFFAF0) == 0x0000) && (x != 0x0000)) +/** + * @brief Used to check parameter of the TM master mode selection. + */ +#define IS_TM_MMSEL_RESET(x) (x == TM_MMSEL_RESET) +#define IS_TM_MMSEL_ENABLE(x) (x == TM_MMSEL_ENABLE) +#define IS_TM_MMSEL_UPDATE(x) (x == TM_MMSEL_UPDATE) +#define IS_TM_MMSEL_CH0CC(x) (x == TM_MMSEL_CH0CC) +#define IS_TM_MMSEL_CH0OREF(x) (x == TM_MMSEL_CH0OREF) +#define IS_TM_MMSEL_CH1OREF(x) (x == TM_MMSEL_CH1OREF) +#define IS_TM_MMSEL_CH2OREF(x) (x == TM_MMSEL_CH2OREF) +#define IS_TM_MMSEL_CH3OREF(x) (x == TM_MMSEL_CH3OREF) +#if (LIBCFG_PWM_8_CHANNEL) +#define IS_TM_MMSEL_CH4OREF(x) (x == TM_MMSEL_CH4OREF) +#define IS_TM_MMSEL_CH5OREF(x) (x == TM_MMSEL_CH5OREF) +#define IS_TM_MMSEL_CH6OREF(x) (x == TM_MMSEL_CH6OREF) +#define IS_TM_MMSEL_CH7OREF(x) (x == TM_MMSEL_CH7OREF) +#else +#define IS_TM_MMSEL_CH4OREF(x) (0) +#define IS_TM_MMSEL_CH5OREF(x) (0) +#define IS_TM_MMSEL_CH6OREF(x) (0) +#define IS_TM_MMSEL_CH7OREF(x) (0) +#endif +#define IS_TM_MMSEL(x) (IS_TM_MMSEL_RESET(x) || \ + IS_TM_MMSEL_ENABLE(x) || \ + IS_TM_MMSEL_UPDATE(x) || \ + IS_TM_MMSEL_CH0CC(x) || \ + IS_TM_MMSEL_CH0OREF(x) || \ + IS_TM_MMSEL_CH1OREF(x) || \ + IS_TM_MMSEL_CH2OREF(x) || \ + IS_TM_MMSEL_CH3OREF(x) || \ + IS_TM_MMSEL_CH4OREF(x) || \ + IS_TM_MMSEL_CH5OREF(x) || \ + IS_TM_MMSEL_CH6OREF(x) || \ + IS_TM_MMSEL_CH7OREF(x)) + +/** + * @brief Used to check parameter of the TM slave mode. + */ +#define IS_TM_SLAVE_MODE(x) ((x == TM_SMSEL_RESTART) || (x == TM_SMSEL_PAUSE) || \ + (x == TM_SMSEL_TRIGGER) || (x == TM_SMSEL_STIED)) +/** + * @brief Used to check parameter of the TM flag. + */ +#define IS_TM_FLAG_CH0CC(x) (x == TM_FLAG_CH0CC) +#define IS_TM_FLAG_CH1CC(x) (x == TM_FLAG_CH1CC) +#define IS_TM_FLAG_CH2CC(x) (x == TM_FLAG_CH2CC) +#define IS_TM_FLAG_CH3CC(x) (x == TM_FLAG_CH3CC) +#if (LIBCFG_PWM_8_CHANNEL) +#define IS_TM_FLAG_CH4CC(x) (x == TM_FLAG_CH4CC) +#define IS_TM_FLAG_CH5CC(x) (x == TM_FLAG_CH5CC) +#define IS_TM_FLAG_CH6CC(x) (x == TM_FLAG_CH6CC) +#define IS_TM_FLAG_CH7CC(x) (x == TM_FLAG_CH7CC) +#else +#define IS_TM_FLAG_CH4CC(x) (0) +#define IS_TM_FLAG_CH5CC(x) (0) +#define IS_TM_FLAG_CH6CC(x) (0) +#define IS_TM_FLAG_CH7CC(x) (0) +#endif +#define IS_TM_FLAG_CH0OC(x) (x == TM_FLAG_CH0OC) +#define IS_TM_FLAG_CH1OC(x) (x == TM_FLAG_CH1OC) +#define IS_TM_FLAG_CH2OC(x) (x == TM_FLAG_CH2OC) +#define IS_TM_FLAG_CH3OC(x) (x == TM_FLAG_CH3OC) +#define IS_TM_FLAG_UEV(x) (x == TM_FLAG_UEV) +#define IS_TM_FLAG_UEV2(x) (x == TM_FLAG_UEV2) +#define IS_TM_FLAG_TEV(x) (x == TM_FLAG_TEV) +#define IS_TM_FLAG_BRK0(x) (x == TM_FLAG_BRK0) +#define IS_TM_FLAG_BRK1(x) (x == TM_FLAG_BRK1) +#define IS_TM_FLAG(x) (IS_TM_FLAG_CH0CC(x) || \ + IS_TM_FLAG_CH1CC(x) || \ + IS_TM_FLAG_CH2CC(x) || \ + IS_TM_FLAG_CH3CC(x) || \ + IS_TM_FLAG_CH4CC(x) || \ + IS_TM_FLAG_CH5CC(x) || \ + IS_TM_FLAG_CH6CC(x) || \ + IS_TM_FLAG_CH7CC(x) || \ + IS_TM_FLAG_CH0OC(x) || \ + IS_TM_FLAG_CH1OC(x) || \ + IS_TM_FLAG_CH2OC(x) || \ + IS_TM_FLAG_CH3OC(x) || \ + IS_TM_FLAG_UEV(x) || \ + IS_TM_FLAG_UEV2(x) || \ + IS_TM_FLAG_TEV(x) || \ + IS_TM_FLAG_BRK0(x) || \ + IS_TM_FLAG_BRK1(x)) + +/** + * @brief Used to check parameter of the TM flag for \ref TM_ClearFlag function. + */ +#define IS_TM_FLAG_CLR(x) (((x & 0xFFFFFA00) == 0) && (x != 0)) +/** + * @brief Used to check value of TM digital filter. + */ +#if (LIBCFG_TM_652XX_V1) +#define IS_TM_FILTER(x) (x <= 0xFF) +#else +#define IS_TM_FILTER(x) (x <= 0xF) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Functions TM exported functions + * @{ + */ +#define TM_SetCaptureCompare0(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_0, Cmp) +#define TM_SetCaptureCompare1(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_1, Cmp) +#define TM_SetCaptureCompare2(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_2, Cmp) +#define TM_SetCaptureCompare3(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_3, Cmp) +#if (LIBCFG_PWM_8_CHANNEL) +#define TM_SetCaptureCompare4(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_4, Cmp) +#define TM_SetCaptureCompare5(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_5, Cmp) +#define TM_SetCaptureCompare6(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_6, Cmp) +#define TM_SetCaptureCompare7(TMx, Cmp) TM_SetCaptureCompare(TMx, TM_CH_7, Cmp) +#endif + +#define TM_ForcedOREF0(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_0, ForcedAction) +#define TM_ForcedOREF1(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_1, ForcedAction) +#define TM_ForcedOREF2(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_2, ForcedAction) +#define TM_ForcedOREF3(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_3, ForcedAction) +#if (LIBCFG_PWM_8_CHANNEL) +#define TM_ForcedOREF4(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_4, ForcedAction) +#define TM_ForcedOREF5(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_5, ForcedAction) +#define TM_ForcedOREF6(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_6, ForcedAction) +#define TM_ForcedOREF7(TMx, ForcedAction) TM_ForcedOREF(TMx, TM_CH_7, ForcedAction) +#endif + +#define TM_SetAsymmetricCompare0(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_0, Cmp) +#define TM_SetAsymmetricCompare1(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_1, Cmp) +#define TM_SetAsymmetricCompare2(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_2, Cmp) +#define TM_SetAsymmetricCompare3(TMx, Cmp) TM_SetAsymmetricCompare(TMx, TM_CH_3, Cmp) + +#define TM_GetCaptureCompare0(TMx) TM_GetCaptureCompare(TMx, TM_CH_0) +#define TM_GetCaptureCompare1(TMx) TM_GetCaptureCompare(TMx, TM_CH_1) +#define TM_GetCaptureCompare2(TMx) TM_GetCaptureCompare(TMx, TM_CH_2) +#define TM_GetCaptureCompare3(TMx) TM_GetCaptureCompare(TMx, TM_CH_3) +#if (LIBCFG_PWM_8_CHANNEL) +#define TM_GetCaptureCompare4(TMx) TM_GetCaptureCompare(TMx, TM_CH_4) +#define TM_GetCaptureCompare5(TMx) TM_GetCaptureCompare(TMx, TM_CH_5) +#define TM_GetCaptureCompare6(TMx) TM_GetCaptureCompare(TMx, TM_CH_6) +#define TM_GetCaptureCompare7(TMx) TM_GetCaptureCompare(TMx, TM_CH_7) +#endif + +void TM_DeInit(HT_TM_TypeDef* TMx); +void TM_TimeBaseInit(HT_TM_TypeDef* TMx, TM_TimeBaseInitTypeDef* TimeBaseInit); +void TM_OutputInit(HT_TM_TypeDef* TMx, TM_OutputInitTypeDef* OutInit); +void TM_CaptureInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit); +void TM_PwmInputInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit); +void TM_TimeBaseStructInit(TM_TimeBaseInitTypeDef* TimeBaseInit); +void TM_OutputStructInit(TM_OutputInitTypeDef* OutInit); +void TM_CaptureStructInit(TM_CaptureInitTypeDef* CapInit); +void TM_Cmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +#if (LIBCFG_TM_NO_ITI == 1) +#else +void TM_ItiExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Iti); +#endif +void TM_ChExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel, TM_CHP_Enum Pol, u8 Filter); +#if 0 // M0+ not supported +void TM_EtiExternalClockConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter); +void TM_EtiConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter); +#endif +void TM_PrescalerConfig(HT_TM_TypeDef* TMx, u16 Psc, TM_PSC_RLD_Enum PscReloadTime); +void TM_CounterModeConfig(HT_TM_TypeDef* TMx, TM_CNT_MODE_Enum Mod); +void TM_StiConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel); +void TM_DecoderConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum DecoderMod, TM_CHP_Enum CH0P, TM_CHP_Enum CH1P); + +void TM_ForcedOREF(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, TM_OM_Enum ForcedAction); +void TM_CRRPreloadCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_CHCCRPreloadConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState); +void TM_ClearOREFConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState); +void TM_ChPolarityConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHP_Enum Pol); + +void TM_ImmActiveConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState); +void TM_ChannelConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control); + +void TM_OutputModeConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_OM_Enum Mod); +void TM_UpdateCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_UEVG_IntConfig(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_HallInterfaceCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_SinglePulseModeCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_MMSELConfig(HT_TM_TypeDef* TMx, TM_MMSEL_Enum Sel); +void TM_SlaveModeConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum Sel); +void TM_TimSyncCmd(HT_TM_TypeDef* TMx, ControlStatus NewState); +void TM_SetCounter(HT_TM_TypeDef* TMx, u16 Counter); +void TM_SetCounterReload(HT_TM_TypeDef* TMx, u16 Reload); +void TM_SetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp); +void TM_SetAsymmetricCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp); + +void TM_CHPSCConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHPSC_Enum Psc); +void TM_CKDIVConfig(HT_TM_TypeDef* TMx, TM_CKDIV_Enum Div); +u32 TM_GetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n); +u32 TM_GetCounter(HT_TM_TypeDef* TMx); +u32 TM_GetPrescaler(HT_TM_TypeDef* TMx); +void TM_GenerateEvent(HT_TM_TypeDef* TMx, u32 TM_EVENT); +FlagStatus TM_GetFlagStatus(HT_TM_TypeDef* TMx, u32 TM_FLAG); +void TM_ClearFlag(HT_TM_TypeDef* TMx, u32 TM_FLAG); +void TM_IntConfig(HT_TM_TypeDef* TMx, u32 TM_INT, ControlStatus NewState); +FlagStatus TM_GetIntStatus(HT_TM_TypeDef* TMx, u32 TM_INT); +void TM_ClearIntPendingBit(HT_TM_TypeDef* TMx, u32 TM_INT); +void TM_InternalClockConfig(HT_TM_TypeDef* TMx); + +#if (LIBCFG_PDMA) +void TM_CHCCDSConfig(HT_TM_TypeDef* TMx, TM_CHCCDS_Enum Selection); +void TM_PDMAConfig(HT_TM_TypeDef* TMx, u32 TM_PDMA, ControlStatus NewState); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm_type.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm_type.h new file mode 100644 index 00000000000..a6ef678b373 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_tm_type.h @@ -0,0 +1,129 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_tm_type.h + * @version $Rev:: 7319 $ + * @date $Date:: 2023-10-28 #$ + * @brief The header file of the TM library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_TM_TYPE_H +#define __HT32F5XXXX_TM_TYPE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup TM + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Types TM exported types + * @{ + */ +/** + * @brief Enumeration of TM channel. + */ +typedef enum +{ + TM_CH_0 = 0, /*!< TM channel 0 */ + TM_CH_1, /*!< TM channel 1 */ + TM_CH_2, /*!< TM channel 2 */ + TM_CH_3, /*!< TM channel 3 */ +#if (LIBCFG_PWM_8_CHANNEL) + TM_CH_4, /*!< TM channel 4 */ + TM_CH_5, /*!< TM channel 5 */ + TM_CH_6, /*!< TM channel 6 */ + TM_CH_7, /*!< TM channel 7 */ +#endif +} TM_CH_Enum; +/** + * @brief Enumeration of TM channel control. + */ +typedef enum +{ + TM_CHCTL_DISABLE = 0, /*!< TM channel disable */ + TM_CHCTL_ENABLE /*!< TM channel enable */ +} TM_CHCTL_Enum; +/** + * @brief Enumeration of TM channel polarity. + */ +typedef enum +{ + TM_CHP_NONINVERTED = 0, /*!< TM channel polarity is active high or rising edge */ + TM_CHP_INVERTED /*!< TM channel polarity is active low or falling edge */ +} TM_CHP_Enum; +/** + * @brief Enumeration of MCTM channel output idle state. + */ +typedef enum +{ + MCTM_OIS_LOW = 0, /*!< MCTM channel output low when CHMOE equal to 0 */ + MCTM_OIS_HIGH /*!< MCTM channel output high when CHMOE equal to 0 */ +} MCTM_OIS_Enum; +/** + * @brief Enumeration of MCTM COMUS. + */ +typedef enum +{ + MCTM_COMUS_STIOFF = 0, /*!< MCTM capture/compare control bits are updated by + setting the UEV2G bit only */ + MCTM_COMUS_STION /*!< MCTM capture/compare control bits are updated by both + setting the UEV2G bit or when a rising edge occurs on STI */ +} MCTM_COMUS_Enum; +#if (LIBCFG_MCTM_UEV1DIS) +/** + * @brief Enumeration of MCTM update event1 disasble. + */ +typedef enum +{ + MCTM_UEV1UD = 0x00000004, /*!< MCTM update event 1 rquest by overflow disable control */ + MCTM_UEV1OD = 0x00000008, /*!< MCTM update event 1 rquest by underflow disable control */ +} MCTM_UEV1DIS_Enum; +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usart.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usart.h new file mode 100644 index 00000000000..bb0d75fe156 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usart.h @@ -0,0 +1,499 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_usart.h + * @version $Rev:: 7107 $ + * @date $Date:: 2023-08-08 #$ + * @brief The header file of the USART library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_USART_H +#define __HT32F5XXXX_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Types USART exported types + * @{ + */ +/* Definition of USART Init Structure ---------------------------------------------------------------------*/ +typedef struct +{ + u32 USART_BaudRate; + u16 USART_WordLength; + u16 USART_StopBits; + u16 USART_Parity; + u32 USART_Mode; +} USART_InitTypeDef; + +typedef struct +{ + u16 USART_ClockEnable; + u16 USART_ClockPhase; + u16 USART_ClockPolarity; + u16 USART_TransferSelectMode; +} USART_SynClock_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Constants USART exported constants + * @{ + */ + +#define USART_CMD_TX (0) +#define USART_CMD_RX (1) + +#define USART_CMD_OUT (0) +#define USART_CMD_IN (1) + +/* USART Word Length ---------------------------------------------------------------------------------------*/ +/** @defgroup USART_Word_Length Definitions of USART word length + * @{ + */ +#define USART_WORDLENGTH_7B ((u32)0x00000000) +#define USART_WORDLENGTH_8B ((u32)0x00000100) +#define USART_WORDLENGTH_9B ((u32)0x00000200) + +#define IS_USART_WORD_LENGTH(LENGTH) ((LENGTH == USART_WORDLENGTH_9B) || \ + (LENGTH == USART_WORDLENGTH_8B) || \ + (LENGTH == USART_WORDLENGTH_7B)) +/** + * @} + */ + +/* USART Stop Bits -----------------------------------------------------------------------------------------*/ +/** @defgroup USART_Stop_Bit Definitions of USART stop bit + * @{ + */ +#define USART_STOPBITS_1 ((u32)0x00000000) +#define USART_STOPBITS_2 ((u32)0x00000400) + + +#define IS_USART_STOPBITS(STOPBITS) ((STOPBITS == USART_STOPBITS_1) || \ + (STOPBITS == USART_STOPBITS_2)) +/** + * @} + */ + +/* USART Parity --------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Parity Definitions of USART parity + * @{ + */ +#define USART_PARITY_NO ((u32)0x00000000) +#define USART_PARITY_EVEN ((u32)0x00001800) +#define USART_PARITY_ODD ((u32)0x00000800) +#define USART_PARITY_MARK ((u32)0x00002800) +#define USART_PARITY_SPACE ((u32)0x00003800) + +#define IS_USART_PARITY(PARITY) ((PARITY == USART_PARITY_NO) || \ + (PARITY == USART_PARITY_EVEN) || \ + (PARITY == USART_PARITY_ODD)) +/** + * @} + */ + +/* USART Mode ----------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Mode Definitions of USART mode + * @{ + */ +#define USART_MODE_NORMAL ((u32)0x00000000) +#define USART_MODE_IRDA ((u32)0x00000001) +#define USART_MODE_RS485 ((u32)0x00000002) +#define USART_MODE_SYNCHRONOUS ((u32)0x00000003) +#if (LIBCFG_USART_LIN) +#define USART_MODE_LIN ((u32)0x00010000) +#define IS_MODE_LIN(x) (x == USART_MODE_LIN) +#else +#define IS_MODE_LIN(x) (0) +#endif +#if (LIBCFG_USART_SINGLE_WIRE) +#define USART_MODE_SINGLE_WIRE ((u32)0x00010001) +#define IS_MODE_SINGLE_WIRE(x) (x == USART_MODE_SINGLE_WIRE) +#else +#define IS_MODE_SINGLE_WIRE(x) (0) +#endif +#define IS_USART_MODE(MODE) ((MODE == USART_MODE_NORMAL) || \ + (MODE == USART_MODE_IRDA) || \ + (MODE == USART_MODE_RS485) || \ + (MODE == USART_MODE_SYNCHRONOUS) || \ + IS_MODE_LIN(MODE) || \ + IS_MODE_SINGLE_WIRE(MODE)) +/** + * @} + */ + +/* USART Transfer Select Mode ------------------------------------------------------------------------------*/ +/** @defgroup USART_LSB Definitions of USART LSB + * @{ + */ +#define USART_LSB_FIRST ((u32)0x00000000) +#define USART_MSB_FIRST ((u32)0x00000004) + +#define IS_USART_TRANSFER_MODE(TMODE) ((TMODE == USART_LSB_FIRST) || \ + (TMODE == USART_MSB_FIRST)) +/** + * @} + */ + + +/* USART Synchronous Clock ---------------------------------------------------------------------------------*/ +/** @defgroup USART_Synchronous_Clock Definitions of USART synchronous clock + * @{ + */ +#define USART_SYN_CLOCK_DISABLE ((u32)0x00000000) +#define USART_SYN_CLOCK_ENABLE ((u32)0x00000001) + +#define IS_USART_SYNCHRONOUS_CLOCK(SYNCLOCK) ((SYNCLOCK == USART_SYN_CLOCK_DISABLE) || \ + (SYNCLOCK == USART_SYN_CLOCK_ENABLE)) +/** + * @} + */ + +/* USART Synchronous Clock Phase ---------------------------------------------------------------------------*/ +/** @defgroup USART_Synchronous_Clock_Phase Definitions of USART Synchronous clock phase + * @{ + */ +#define USART_SYN_CLOCK_PHASE_FIRST ((u32)0x00000000) +#define USART_SYN_CLOCK_PHASE_SECOND ((u32)0x00000004) + +#define IS_USART_SYNCHRONOUS_PHASE(PHASE) ((PHASE == USART_SYN_CLOCK_PHASE_FIRST) || \ + (PHASE == USART_SYN_CLOCK_PHASE_SECOND)) +/** + * @} + */ + +/* USART Clock Polarity ------------------------------------------------------------------------------------*/ +/** @defgroup USART_Clock_Polarity Definitions of USART clock polarity + * @{ + */ +#define USART_SYN_CLOCK_POLARITY_LOW ((u32)0x00000000) +#define USART_SYN_CLOCK_POLARITY_HIGH ((u32)0x00000008) + +#define IS_USART_SYNCHRONOUS_POLARITY(POLARITY) ((POLARITY == USART_SYN_CLOCK_POLARITY_LOW) || \ + (POLARITY == USART_SYN_CLOCK_POLARITY_HIGH)) +/** + * @} + */ + +/* USART IrDA ---------------------------------------------------------------------------------------------*/ +/** @defgroup USART_IrDA Definitions of USART IrDA + * @{ + */ +#define USART_IRDA_LOWPOWER ((u32)0x00000002) +#define USART_IRDA_NORMAL ((u32)0xFFFFFFFD) + +#define IS_USART_IRDA_MODE(MODE) ((MODE == USART_IRDA_LOWPOWER) || \ + (MODE == USART_IRDA_NORMAL)) + +#define USART_IRDA_TX ((u32)0x00000004) +#define USART_IRDA_RX ((u32)0xFFFFFFFB) + +#define IS_USART_IRDA_DIRECTION(DIRECTION) ((DIRECTION == USART_IRDA_TX) || \ + (DIRECTION == USART_IRDA_RX)) +/** + * @} + */ + +#define IS_USART_TL(x) (IS_USART_RXTL(x) || IS_USART_TXTL(x)) + +/* USART Rx FIFO Interrupt Trigger Level -------------------------------------------------------------------*/ +/** @defgroup USART_RX_FIFO_Trigger_Level Definitions of USART Rx FIFO interrupts + * @{ + */ +#define USART_RXTL_01 ((u32)0x00000000) +#define USART_RXTL_02 ((u32)0x00000010) +#define USART_RXTL_04 ((u32)0x00000020) +#define USART_RXTL_06 ((u32)0x00000030) + +#define IS_USART_RXTL(RXTL) ((RXTL == USART_RXTL_01) || \ + (RXTL == USART_RXTL_02) || \ + (RXTL == USART_RXTL_04) || \ + (RXTL == USART_RXTL_06)) +/** + * @} + */ + +/* USART Tx FIFO Interrupt Trigger Level -------------------------------------------------------------------*/ +/** @defgroup USART_TX_FIFO_Trigger_Level Definitions of USART Tx FIFO interrupts + * @{ + */ +#define USART_TXTL_00 ((u32)0x00000000) +#define USART_TXTL_02 ((u32)0x00000010) +#define USART_TXTL_04 ((u32)0x00000020) +#define USART_TXTL_06 ((u32)0x00000030) + +#define IS_USART_TXTL(TXTL) ((TXTL == USART_TXTL_00) || \ + (TXTL == USART_TXTL_02) || \ + (TXTL == USART_TXTL_04) || \ + (TXTL == USART_TXTL_06)) +/** + * @} + */ + +/* USART Interrupt definition ------------------------------------------------------------------------------*/ +/** @defgroup USART_Interrupt_Enable Definitions of USART interrupt Enable bits + * @{ + */ +#define USART_INT_RXDR ((u32)0x00000001) +#define USART_INT_TXDE ((u32)0x00000002) +#define USART_INT_TXC ((u32)0x00000004) +#define USART_INT_OE ((u32)0x00000008) +#define USART_INT_PE ((u32)0x00000010) +#define USART_INT_FE ((u32)0x00000020) +#define USART_INT_BI ((u32)0x00000040) +#define USART_INT_RSADD ((u32)0x00000080) +#define USART_INT_TOUT ((u32)0x00000100) +#define USART_INT_CTS ((u32)0x00000200) +#if (LIBCFG_USART_LIN) +#define USART_INT_LBD ((u32)0x00000400) +#endif + +#if (LIBCFG_USART_LIN) +#define IS_USART_INT(INT) ((((INT) & 0xFFFFF800) == 0) && ((INT) != 0)) +#else +#define IS_USART_INT(INT) ((((INT) & 0xFFFFFC00) == 0) && ((INT) != 0)) +#endif +/** + * @} + */ + +/* USART Flags ---------------------------------------------------------------------------------------------*/ +/** @defgroup USART_Flag Definitions of USART flags + * @{ + */ +#define USART_FLAG_RXDNE ((u32)0x00000001) +#define USART_FLAG_OE ((u32)0x00000002) +#define USART_FLAG_PE ((u32)0x00000004) +#define USART_FLAG_FE ((u32)0x00000008) +#define USART_FLAG_BI ((u32)0x00000010) +#define USART_FLAG_RXDR ((u32)0x00000020) +#define USART_FLAG_TOUT ((u32)0x00000040) +#define USART_FLAG_TXDE ((u32)0x00000080) +#define USART_FLAG_TXC ((u32)0x00000100) +#define USART_FLAG_RSADD ((u32)0x00000200) +#define USART_FLAG_CTSC ((u32)0x00000400) +#define USART_FLAG_CTSS ((u32)0x00000800) +#if (LIBCFG_USART_LIN) +#define USART_FLAG_LBD ((u32)0x00001000) +#define IS_FLAG_LBD(x) (x == USART_FLAG_LBD) +#else +#define IS_FLAG_LBD(x) (0) +#endif + +#define IS_USART_FLAG(FLAG) ((FLAG == USART_FLAG_RXDNE) || (FLAG == USART_FLAG_OE) || \ + (FLAG == USART_FLAG_PE) || (FLAG == USART_FLAG_FE) || \ + (FLAG == USART_FLAG_BI) || (FLAG == USART_FLAG_RXDR) || \ + (FLAG == USART_FLAG_TOUT) || (FLAG == USART_FLAG_TXDE) || \ + (FLAG == USART_FLAG_TXC) || (FLAG == USART_FLAG_RSADD) || \ + (FLAG == USART_FLAG_CTSC) || (FLAG == USART_FLAG_CTSS) || \ + IS_FLAG_LBD(FLAG)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((FLAG == USART_FLAG_OE) || (FLAG == USART_FLAG_PE) || \ + (FLAG == USART_FLAG_FE) || (FLAG == USART_FLAG_BI) || \ + (FLAG == USART_FLAG_TOUT) || (FLAG == USART_FLAG_RSADD) || \ + (FLAG == USART_FLAG_CTSC) || IS_FLAG_LBD(FLAG)) +/** + * @} + */ + +/* USART RS485 definition ----------------------------------------------------------------------------------*/ +/** @defgroup USART_RS485 Definitions of USART RS485 + * @{ + */ +#define USART_RS485POLARITY_LOW ((u32)0x00000001) +#define USART_RS485POLARITY_HIGH ((u32)0xFFFFFFFE) + +#define IS_USART_RS485_POLARITY(POLARITY) ((POLARITY == USART_RS485POLARITY_LOW) || \ + (POLARITY == USART_RS485POLARITY_HIGH)) +/** + * @} + */ + +/* USART LIN definition -----------------------------------------------------------------------------------*/ +/** @defgroup USART_LIN Definitions of USART LIN + * @{ + */ +#if (LIBCFG_USART_LIN) +#define USART_LINSENDBREAK ((u32)0x00020000) + +#define USART_LINLENGTH_10BIT ((u32)0xFFFBFFFF) +#define USART_LINLENGTH_11BIT ((u32)0x00040000) + +#define IS_USART_LINLENGTH(LENGTH) ((LENGTH == USART_LINLENGTH_10BIT) || \ + (LENGTH == USART_LINLENGTH_11BIT)) +#endif +/** + * @} + */ + +#define USART_FIFO_TX ((u32)0x00000001) +#define USART_FIFO_RX ((u32)0x00000002) + +#define IS_USART_FIFO_DIRECTION(DIRECTION) ((DIRECTION == USART_FIFO_TX) || \ + (DIRECTION == USART_FIFO_RX)) + +#define USART_STICK_LOW ((u32)0x00001000) +#define USART_STICK_HIGH ((u32)0xFFFFEFFF) + +#define IS_USART_STICK_PARITY(PARITY) ((PARITY == USART_STICK_LOW) || (PARITY == USART_STICK_HIGH)) + +#if (LIBCFG_PDMA) +#define USART_PDMAREQ_TX ((u32)0x00000040) +#define USART_PDMAREQ_RX ((u32)0x00000080) + +#define IS_USART_PDMA_REQ(REQ) (((REQ & 0xFFFFFF3F) == 0x0) && (REQ != 0x0)) +#endif + +#define IS_USART(x) (IS_USART0(x) || \ + IS_USART1(x) || \ + IS_UART0(x) || \ + IS_UART1(x) || \ + IS_UART2(x) || \ + IS_UART3(x)) +#if (LIBCFG_NO_USART0) +#define IS_USART0(x) (0) +#else +#define IS_USART0(x) (x == HT_USART0) +#endif +#define IS_UART0(x) (x == HT_UART0) +#if (LIBCFG_USART1) +#define IS_USART1(x) (x == HT_USART1) +#else +#define IS_USART1(x) (0) +#endif +#if (LIBCFG_UART1) +#define IS_UART1(x) (x == HT_UART1) +#else +#define IS_UART1(x) (0) +#endif +#if (LIBCFG_UART2) +#define IS_UART2(x) (x == HT_UART2) +#else +#define IS_UART2(x) (0) +#endif +#if (LIBCFG_UART3) +#define IS_UART3(x) (x == HT_UART3) +#else +#define IS_UART3(x) (0) +#endif +#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE > 0) && (BAUDRATE < 0x0044AA21)) +#define IS_USART_DATA(DATA) (DATA <= 0x1FF) +#define IS_USART_GUARD_TIME(TIME) (TIME <= 0xFF) +#define IS_USART_IRDA_PRESCALER(PRESCALER) (PRESCALER <= 0xFF) +#define IS_USART_TIMEOUT(TIMEOUT) (TIMEOUT <= 0x7F) +#define IS_USART_ADDRESS_MATCH_VALUE(VALUE) (VALUE <= 0xFF) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Functions USART exported functions + * @{ + */ +#define USART_TxCmd(USARTx, NewState) USART_TxRxCmd(USARTx, USART_CMD_TX, NewState) +#define USART_RxCmd(USARTx, NewState) USART_TxRxCmd(USARTx, USART_CMD_RX, NewState) + +#define USART_TxPDMACmd(USARTx, NewState) USART_PDMACmd(USARTx, USART_PDMAREQ_TX, NewState) +#define USART_RxPDMACmd(USARTx, NewState) USART_PDMACmd(USARTx, USART_PDMAREQ_RX, NewState) + +#define USART_RXTLConfig(USARTx, USART_tl) USART_TXRXTLConfig(USARTx, USART_CMD_RX, USART_tl) +#define USART_TXTLConfig(USARTx, USART_tl) USART_TXRXTLConfig(USARTx, USART_CMD_TX, USART_tl) + +#define USART_IrDAInvtOutputCmd(USARTx, NewState) USART_IrDAInvtCmd(USARTx, USART_CMD_OUT, NewState) +#define USART_IrDAInvtInputCmd(USARTx, NewState) USART_IrDAInvtCmd(USARTx, USART_CMD_IN, NewState) + +void USART_DeInit(HT_USART_TypeDef* USARTx); +void USART_Init(HT_USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStructure); +void USART_StructInit(USART_InitTypeDef* USART_InitStructure); +void USART_SendData(HT_USART_TypeDef* USARTx, u16 Data); +u16 USART_ReceiveData(HT_USART_TypeDef* USARTx); +FlagStatus USART_GetFlagStatus(HT_USART_TypeDef* USARTx, u32 USART_FLAG_x); +FlagStatus USART_GetIntStatus(HT_USART_TypeDef* USARTx, u32 USART_FLAG_x); +void USART_ClearFlag(HT_USART_TypeDef* USARTx, u32 USART_Flag); +void USART_IntConfig(HT_USART_TypeDef* USARTx, u32 USART_INT_x, ControlStatus NewState); +void USART_TxRxCmd(HT_USART_TypeDef* USARTx,u32 TxRx, ControlStatus NewState); +#if (LIBCFG_PDMA) +void USART_PDMACmd(HT_USART_TypeDef* USARTx, u32 USART_PDMAREQ, ControlStatus NewState); +#endif +void USART_ForceBreakCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_StickParityCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_StickParityConfig(HT_USART_TypeDef* USARTx, u32 USART_StickParity); + +void USART_SetGuardTime(HT_USART_TypeDef* USARTx, u32 USART_GuardTime); +void USART_TXRXTLConfig(HT_USART_TypeDef* USARTx, u32 TxRx, u32 USART_tl); +void USART_SetTimeOutValue(HT_USART_TypeDef* USARTx, u32 USART_TimeOut); +void USART_FIFOReset(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection); +u8 USART_GetFIFOStatus(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection); +void USART_HardwareFlowControlCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); + +void USART_IrDACmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_IrDAConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDAMode); +void USART_SetIrDAPrescaler(HT_USART_TypeDef* USARTx, u32 USART_IrDAPrescaler); +void USART_IrDADirectionConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDADirection); +void USART_IrDAInvtCmd(HT_USART_TypeDef* USARTx, u32 inout, ControlStatus NewState); + +void USART_RS485TxEnablePolarityConfig(HT_USART_TypeDef* USARTx, u32 USART_RS485Polarity); +void USART_RS485NMMCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_RS485AADCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState); +void USART_SetAddressMatchValue(HT_USART_TypeDef* USARTx, u32 USART_AddressMatchValue); + +void USART_SynClockInit(HT_USART_TypeDef* USARTx, USART_SynClock_InitTypeDef* USART_SynClock_InitStruct); +void USART_SynClockStructInit(USART_SynClock_InitTypeDef* USART_SynClock_InitStruct); + +#if (LIBCFG_USART_LIN) +void USART_LIN_SendBreak(HT_USART_TypeDef* USARTx); +void USART_LIN_LengthSelect(HT_USART_TypeDef* USARTx, u32 USART_LIN_Length); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbd.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbd.h new file mode 100644 index 00000000000..c9ebd0e4082 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbd.h @@ -0,0 +1,346 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_usbd.h + * @version $Rev:: 6559 $ + * @date $Date:: 2022-12-18 #$ + * @brief The header file of the USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_USBD_H +#define __HT32F5XXXX_USBD_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +#if (LIBCFG_USBD_V2) +#include "ht32f5xxxx_02_usbdconf.h" +#else +#include "ht32f5xxxx_01_usbdconf.h" +#endif +#include "ht32f5xxxx_usbdinit.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup USBDevice USB Device + * @brief USB Device driver modules + * @{ + */ + + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Settings USB Device settings + * @{ + */ +#if (LIBCFG_USBD_V2) +#define MAX_EP_NUM (10) +#else +#define MAX_EP_NUM (8) +#endif +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Types USB Device exported types + * @{ + */ +/* USB Endpoint number */ +typedef enum +{ + USBD_EPT0 = 0, + USBD_EPT1 = 1, + USBD_EPT2 = 2, + USBD_EPT3 = 3, + USBD_EPT4 = 4, + USBD_EPT5 = 5, + USBD_EPT6 = 6, + USBD_EPT7 = 7, + #if (LIBCFG_USBD_V2) + USBD_EPT8 = 8, + USBD_EPT9 = 9, + #endif + USBD_NOEPT = -1, +} USBD_EPTn_Enum; + +typedef enum +{ + USBD_TCR_0 = 0, + USBD_TCR_1 = 16, +} USBD_TCR_Enum; + +typedef enum +{ + USBD_NAK = 0, + USBD_ACK = 1 +} USBD_Handshake_Enum; + +/* Endpoint CFGR Register */ +typedef struct _EPTCFGR_BIT +{ + vu32 EPBUFA: 10; + vu32 EPLEN : 10; + vu32 _RES0 : 3; + vu32 SDBS : 1; + vu32 EPADR : 4; + vu32 EPDIR : 1; + vu32 EPTYPE: 1; + vu32 _RES1 : 1; + vu32 EPEN : 1; +} USBD_EPTCFGR_Bit; + +typedef union _EPTCFGR_TYPEDEF +{ + USBD_EPTCFGR_Bit bits; + u32 word; +} USBD_EPTCFGR_TypeDef; + +/* Endpoint CFGR and IER Register */ +typedef struct +{ + USBD_EPTCFGR_TypeDef CFGR; + u32 IER; +} USBD_EPTInit_TypeDef; + +/* Endpoint 0 ~ MAX_EP_NUM */ +typedef struct +{ + u32 uInterruptMask; + USBD_EPTInit_TypeDef ept[MAX_EP_NUM]; +} USBD_Driver_TypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Constants USB Device exported constants + * @{ + */ + +/* USB Interrupt Enable Register (USBIER) */ +#define UGIE ((u32)0x00000001) /*!< USB global Interrupt Enable */ +#define SOFIE ((u32)0x00000002) /*!< Start Of Frame Interrupt Enable */ +#define URSTIE ((u32)0x00000004) /*!< USB Reset Interrupt Enable */ +#define RSMIE ((u32)0x00000008) /*!< Resume Interrupt Enable */ +#define SUSPIE ((u32)0x00000010) /*!< Suspend Interrupt Enable */ +#define ESOFIE ((u32)0x00000020) /*!< Expected Start Of Frame Interrupt Enable */ +#define FRESIE ((u32)0x00000040) /*!< Force USB Reset Control Interrupt Enable */ +#define EP0IE ((u32)0x00000100) /*!< Endpoint 0 Interrupt Enable */ +#define EP1IE ((u32)0x00000200) /*!< Endpoint 1 Interrupt Enable */ +#define EP2IE ((u32)0x00000400) /*!< Endpoint 2 Interrupt Enable */ +#define EP3IE ((u32)0x00000800) /*!< Endpoint 3 Interrupt Enable */ +#define EP4IE ((u32)0x00001000) /*!< Endpoint 4 Interrupt Enable */ +#define EP5IE ((u32)0x00002000) /*!< Endpoint 5 Interrupt Enable */ +#define EP6IE ((u32)0x00004000) /*!< Endpoint 6 Interrupt Enable */ +#define EP7IE ((u32)0x00008000) /*!< Endpoint 7 Interrupt Enable */ + +/* USB Interrupt Status Register (USBISR) */ +#define SOFIF ((u32)0x00000002) /*!< Start Of Frame Interrupt Flag */ +#define URSTIF ((u32)0x00000004) /*!< USB Reset Interrupt Flag */ +#define RSMIF ((u32)0x00000008) /*!< Resume Interrupt Flag */ +#define SUSPIF ((u32)0x00000010) /*!< Suspend Interrupt Flag */ +#define ESOFIF ((u32)0x00000020) /*!< Expected Start Of Frame Interrupt Flag */ +#define FRESIF ((u32)0x00000040) /*!< Force USB Reset Control Interrupt Flag */ +#define EP0IF ((u32)0x00000100) /*!< Endpoint 0 Interrupt flag */ +#define EP1IF ((u32)0x00000200) /*!< Endpoint 1 Interrupt flag */ +#define EP2IF ((u32)0x00000400) /*!< Endpoint 2 Interrupt flag */ +#define EP3IF ((u32)0x00000800) /*!< Endpoint 3 Interrupt flag */ +#define EP4IF ((u32)0x00001000) /*!< Endpoint 4 Interrupt flag */ +#define EP5IF ((u32)0x00002000) /*!< Endpoint 5 Interrupt flag */ +#define EP6IF ((u32)0x00004000) /*!< Endpoint 6 Interrupt flag */ +#define EP7IF ((u32)0x00008000) /*!< Endpoint 7 Interrupt flag */ +#if (LIBCFG_USBD_V2) +#define EP8IF ((u32)0x00010000) /*!< Endpoint 8 Interrupt flag */ +#define EP9IF ((u32)0x00020000) /*!< Endpoint 9 Interrupt flag */ +#define EPnIF ((u32)0x0003FF00) /*!< Endpoint n Interrupt flag */ +#else +#define EPnIF ((u32)0x0000FF00) /*!< Endpoint n Interrupt flag */ +#endif + + +/* USB Endpoint n Interrupt Enable Register (USBEPnIER) */ +#define OTRXIE ((u32)0x00000001) /*!< OUT Token Received Interrupt Enable */ +#define ODRXIE ((u32)0x00000002) /*!< OUT Data Received Interrupt Enable */ +#define ODOVIE ((u32)0x00000004) /*!< OUT Data Buffer Overrun Interrupt Enable */ +#define ITRXIE ((u32)0x00000008) /*!< IN Token Received Interrupt Enable */ +#define IDTXIE ((u32)0x00000010) /*!< IN Data Transmitted Interrupt Enable */ +#define NAKIE ((u32)0x00000020) /*!< NAK Transmitted Interrupt Enable */ +#define STLIE ((u32)0x00000040) /*!< STALL Transmitted Interrupt Enable */ +#define UERIE ((u32)0x00000080) /*!< USB Error Interrupt Enable */ +#define STRXIE ((u32)0x00000100) /*!< SETUP Token Received Interrupt Enable */ +#define SDRXIE ((u32)0x00000200) /*!< SETUP Data Received Interrupt Enable */ +#define SDERIE ((u32)0x00000400) /*!< SETUP Data Error Interrupt Enable */ +#define ZLRXIE ((u32)0x00000800) /*!< Zero Length Data Received Interrupt Enable */ + +/* USB Endpoint n Interrupt Status Register (USBEPnISR) */ +#define OTRXIF ((u32)0x00000001) /*!< OUT Token Received Interrupt Flag */ +#define ODRXIF ((u32)0x00000002) /*!< OUT Data Received Interrupt Flag */ +#define ODOVIF ((u32)0x00000004) /*!< OUT Data Buffer Overrun Interrupt Flag */ +#define ITRXIF ((u32)0x00000008) /*!< IN Token Received Interrupt Flag */ +#define IDTXIF ((u32)0x00000010) /*!< IN Data Transmitted Interrupt Flag */ +#define NAKIF ((u32)0x00000020) /*!< NAK Transmitted Interrupt Flag */ +#define STLIF ((u32)0x00000040) /*!< STALL Transmitted Interrupt Flag */ +#define UERIF ((u32)0x00000080) /*!< USB Error Interrupt Flag */ +#define STRXIF ((u32)0x00000100) /*!< SETUP Token Received Interrupt Flag */ +#define SDRXIF ((u32)0x00000200) /*!< SETUP Data Received Interrupt Flag */ +#define SDERIF ((u32)0x00000400) /*!< SETUP Data Error Interrupt Flag */ +#define ZLRXIF ((u32)0x00000800) /*!< Zero Length Data Received Interrupt Flag */ + +/* USB Endpoint n Control and Status Register (USBEPnCSR) */ +#define DTGTX ((u32)0x00000001) /*!< Data Toggle Status, for IN transfer */ +#define NAKTX ((u32)0x00000002) /*!< NAK Status, for IN transfer */ +#define STLTX ((u32)0x00000004) /*!< STALL Status, for IN transfer */ +#define DTGRX ((u32)0x00000008) /*!< Data Toggle Status, for OUT transfer */ +#define NAKRX ((u32)0x00000010) /*!< NAK Status, for OUT transfer */ +#define STLRX ((u32)0x00000020) /*!< STALL Status, for OUT transfer */ + +/* For USBD_EPTGetTranssferCount function */ +#define USBD_CNTB0 (USBD_TCR_0) +#define USBD_CNTB1 (USBD_TCR_1) +#define USBD_CNTIN (USBD_TCR_0) +#define USBD_CNTOUT (USBD_TCR_1) +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Macro USB Device exported macro + * @{ + */ +/* API macro for USB Core - Global event and operation */ +#define API_USB_INIT(driver) (USBD_Init(driver)) +#define API_USB_DEINIT() (USBD_DeInit()) +#define API_USB_POWER_UP(driver, power) (USBD_PowerUp(driver, power)) +#define API_USB_POWER_OFF() (USBD_PowerOff()) +#define API_USB_POWER_ON() (USBD_PowerOn()) +#define API_USB_REMOTE_WAKEUP() (USBD_RemoteWakeup()) +#define API_USB_READ_SETUP(buffer) (USBD_ReadSETUPData((u32 *)(buffer))) +#define API_USB_SET_ADDR(addr) (USBD_SetAddress(addr)) +#define API_USB_GET_CTRL_IN_LEN() (USBD_EPTGetBufferLen(USBD_EPT0)) +#define API_USB_ENABLE_INT(flag) (USBD_EnableINT(flag)) +#define API_USB_GET_INT() (USBD_GetINT()) +#define API_USB_GET_EPT_NUM(flag) (USBD_GetEPTnINTNumber(flag)) +#define API_USB_IS_SETUP_INT(flag) (flag & SDRXIF) +#define API_USB_CLR_SETUP_INT() (USBD_EPTClearINT(USBD_EPT0, SDRXIF)) +#define API_USB_IS_RESET_INT(flag) (flag & URSTIF) +#define API_USB_CLR_RESET_INT() (USBD_ClearINT(URSTIF)) +#define API_USB_IS_SOF_INT(flag) (flag & SOFIF) +#define API_USB_CLR_SOF_INT() (USBD_ClearINT(SOFIF)) +#define API_USB_IS_FRES_INT(flag) (flag & FRESIF) +#define API_USB_CLR_FRES_INT() (USBD_ClearINT(FRESIF)) +#define API_USB_IS_RESUME_INT(flag) (flag & RSMIF) +#define API_USB_CLR_RESUME_INT() (USBD_ClearINT(RSMIF)) +#define API_USB_IS_SUSPEND_INT(flag) (flag & SUSPIF) +#define API_USB_CLR_SUSPEND_INT() (USBD_ClearINT(SUSPIF)) +#define API_USB_IS_EPTn_INT(flag, EPTn) (flag & (EP0IF << EPTn)) +#define API_USB_CLR_EPTn_INT(EPTn) (USBD_ClearINT(EP0IF << EPTn)) + +/* API macro for USB Core - Endpoint event and operation */ +#define API_USB_EPTn_INIT(EPTn, driver) (USBD_EPTInit(EPTn, driver)) +#define API_USB_EPTn_RESET(EPTn) (USBD_EPTReset(EPTn)) +#define API_USB_EPTn_SEND_STALL(EPTn) (USBD_EPTSendSTALL(EPTn)) +#define API_USB_EPTn_GET_INT(EPTn) (USBD_EPTGetINT(EPTn)) +#define API_USB_EPTn_IS_IN_INT(flag) (flag & IDTXIF) +#define API_USB_EPTn_CLR_IN_INT(EPTn) (USBD_EPTClearINT(EPTn, IDTXIF)) +#define API_USB_EPTn_IS_OUT_INT(flag) (flag & ODRXIF) +#define API_USB_EPTn_CLR_OUT_INT(EPTn) (USBD_EPTClearINT(EPTn, ODRXIF)) +#define API_USB_EPTn_IS_INT(flag) (flag & (ODRXIF | IDTXIF)) +#define API_USB_EPTn_CLR_INT(EPTn) (USBD_EPTClearINT(EPTn, (ODRXIF | IDTXIF))) +#define API_USB_EPTn_GET_HALT(EPTn) (USBD_EPTGetHalt(EPTn)) +#define API_USB_EPTn_SET_HALT(EPTn) (USBD_EPTSetHalt(EPTn)) +#define API_USB_EPTn_CLR_HALT(EPTn) (USBD_EPTClearHalt(EPTn)) +#define API_USB_EPTn_WAIT_STALL_SENT(EPTn) (USBD_EPTWaitSTALLSent(EPTn)) +#define API_USB_EPTn_CLR_DTG(EPTn) (USBD_EPTClearDTG(EPTn)) +#define API_USB_EPTn_GET_BUFFLEN(EPTn) (USBD_EPTGetBufferLen(EPTn)) +#define API_USB_EPTn_GET_CNT(EPTn, type) (USBD_EPTGetTransferCount(EPTn, type)) +#define API_USB_EPTn_WRITE_IN(EPTn, from, len) (USBD_EPTWriteINData(EPTn, from, len)) +#define API_USB_EPTn_READ_OUT(EPTn, to, len) (USBD_EPTReadOUTData(EPTn, to, len)) +#define API_USB_EPTn_READ_MEM(EPTn, to, len) (USBD_EPTReadMemory(EPTn, to, len)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Functions USB Device exported functions + * @{ + */ +void USBD_Init(u32 *pDriver); +void USBD_PreInit(USBD_Driver_TypeDef *pDriver); +void USBD_DPpullupCmd(ControlStatus NewState); +void USBD_DPWakeUpCmd(ControlStatus NewState); +void USBD_DeInit(void); +void USBD_PowerUp(u32 *pDriver, u32 uIsSelfPowered); +void USBD_PowerOff(void); +void USBD_PowerOn(void); +void USBD_SRAMResetConditionCmd(ControlStatus NewState); +void USBD_DisableDefaultPull(void); +void USBD_RemoteWakeup(void); +void USBD_ReadSETUPData(u32 *pBuffer); +void USBD_SetAddress(u32 address); +void USBD_EnableINT(u32 INTFlag); +void USBD_DisableINT(u32 INTFlag); +u32 USBD_GetINT(void); +void USBD_ClearINT(u32 INTFlag); +USBD_EPTn_Enum USBD_GetEPTnINTNumber(u32 INTFlag); + +void USBD_EPTInit(USBD_EPTn_Enum USBD_EPTn, u32 *pDriver); +void USBD_EPTReset(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTEnableINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag); +u32 USBD_EPTGetINT(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTClearINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag); +void USBD_EPTSendSTALL(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetHalt(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTSetHalt(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTClearHalt(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTWaitSTALLSent(USBD_EPTn_Enum USBD_EPTn); +void USBD_EPTClearDTG(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetBuffer0Addr(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetBuffer1Addr(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetBufferLen(USBD_EPTn_Enum USBD_EPTn); +u32 USBD_EPTGetTransferCount(USBD_EPTn_Enum USBD_EPTn, USBD_TCR_Enum USBD_TCR_0or1); +u32 USBD_EPTWriteINData(USBD_EPTn_Enum USBD_EPTn, u32 *pFrom, u32 len); +u32 USBD_EPTReadOUTData(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +u32 USBD_EPTReadMemory(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbdchk.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbdchk.h new file mode 100644 index 00000000000..d4d1625cef8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbdchk.h @@ -0,0 +1,706 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_usbdchk.h + * @version $Rev:: 5656 $ + * @date $Date:: 2021-11-24 #$ + * @brief The header file of the USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_USBDCHK_H +#define __HT32F5XXXX_USBDCHK_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup USBDevice + * @{ + */ + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint 0 ~ 7 and checking */ +/* !!! DO NOT MODIFY !!! */ +/*----------------------------------------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP0LEN != 8 && _EP0LEN != 16 && _EP0LEN != 32 && _EP0LEN != 64) + #error "USB Buffer Length (EPLEN) of Control Endpoint0 must be 8, 16, 32, or 64 bytes." +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration and checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP1_ENABLE == 1) + #if (_EP1_TYPR == EP_TYPE_BULK) + #if (_EP1LEN != 8 && _EP1LEN != 16 && _EP1LEN != 32 && _EP1LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint1 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP1LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint1 must be less than 64 bytes." + #endif + #if (_EP1LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint1 cannot be 0 byte." + #endif + #if ((_EP1LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint1 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP2_ENABLE == 1) + #if (_EP2_TYPR == EP_TYPE_BULK) + #if (_EP2LEN != 8 && _EP2LEN != 16 && _EP2LEN != 32 && _EP2LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint2 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP2LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint2 must be less than 64 bytes." + #endif + #if (_EP2LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint2 cannot be 0 byte." + #endif + #if ((_EP2LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint2 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP3_ENABLE == 1) + #if (_EP3_TYPR == EP_TYPE_BULK) + #if (_EP3LEN != 8 && _EP3LEN != 16 && _EP3LEN != 32 && _EP3LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint3 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP3LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint3 must be less than 64 bytes." + #endif + #if (_EP3LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint3 cannot be 0 byte." + #endif + #if ((_EP3LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint3 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint8 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP8_ENABLE == 1) + #if (_EP8_TYPR == EP_TYPE_BULK) + #if (_EP8LEN != 8 && _EP8LEN != 16 && _EP8LEN != 32 && _EP8LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint8 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP8LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint8 must be less than 64 bytes." + #endif + #if (_EP8LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint8 cannot be 0 byte." + #endif + #if ((_EP8LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint8 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint9 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP9_ENABLE == 1) + #if (_EP9_TYPR == EP_TYPE_BULK) + #if (_EP9LEN != 8 && _EP9LEN != 16 && _EP9LEN != 32 && _EP9LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint9 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP9LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint9 must be less than 64 bytes." + #endif + #if (_EP9LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint9 cannot be 0 byte." + #endif + #if ((_EP9LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint9 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP4_ENABLE == 1) + #if (_EP4_TYPR == EP_TYPE_BULK) + #if (_EP4LEN != 8 && _EP4LEN != 16 && _EP4LEN != 32 && _EP4LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP4_TYPR == EP_TYPE_INT) + #if (_EP4LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP4_TYPR == EP_TYPE_ISO) + #if (_EP4LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP4LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint4 cannot be 0 byte." + #endif + #if ((_EP4LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint4 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP5_ENABLE == 1) + #if (_EP5_TYPR == EP_TYPE_BULK) + #if (_EP5LEN != 8 && _EP5LEN != 16 && _EP5LEN != 32 && _EP5LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP5_TYPR == EP_TYPE_INT) + #if (_EP5LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP5_TYPR == EP_TYPE_ISO) + #if (_EP5LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP5LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint5 cannot be 0 byte." + #endif + #if ((_EP5LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint5 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP6_ENABLE == 1) + #if (_EP6_TYPR == EP_TYPE_BULK) + #if (_EP6LEN != 8 && _EP6LEN != 16 && _EP6LEN != 32 && _EP6LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP6_TYPR == EP_TYPE_INT) + #if (_EP6LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP6_TYPR == EP_TYPE_ISO) + #if (_EP6LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP6LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint6 cannot be 0 byte." + #endif + #if ((_EP6LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint6 must be a multiple of 4 (word-aligned)." + #endif +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 checking */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP7_ENABLE == 1) + #if (_EP7_TYPR == EP_TYPE_BULK) + #if (_EP7LEN != 8 && _EP7LEN != 16 && _EP7LEN != 32 && _EP7LEN != 64) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be 8, 16, 32, or 64 bytes under Bulk transfer." + #endif + #endif + #if (_EP7_TYPR == EP_TYPE_INT) + #if (_EP7LEN > 64) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be less than 64 bytes under Interrupt transfer." + #endif + #endif + #if (_EP7_TYPR == EP_TYPE_ISO) + #if (_EP7LEN > 1023) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be less than 1023 bytes under Isochronous transfer." + #endif + #endif + #if (_EP7LEN == 0) + #error "USB Buffer Length (EPLEN) of Endpoint7 cannot be 0 byte." + #endif + #if ((_EP7LEN & 0x3) != 0x0) + #error "USB Buffer Length (EPLEN) of Endpoint7 must be a multiple of 4 (word-aligned)." + #endif +#endif + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Check the endpoint address */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (_EP1_ENABLE == 1) + #if (_EP1_CFG_EPADR == 0) + #error "The address of Endpoint1 (EPADR) cannot be 0." + #endif + #if (_EP2_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint8." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP1_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint1 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP2_ENABLE == 1) + #if (_EP2_CFG_EPADR == 0) + #error "The address of Endpoint2 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint8." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP2_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint2 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP3_ENABLE == 1) + #if (_EP3_CFG_EPADR == 0) + #error "The address of Endpoint3 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint8." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP3_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint3 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP4_ENABLE == 1) + #if (_EP4_CFG_EPADR == 0) + #error "The address of Endpoint4 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint8." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP4_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint4 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP5_ENABLE == 1) + #if (_EP5_CFG_EPADR == 0) + #error "The address of Endpoint5 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint8." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP5_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint5 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP6_ENABLE == 1) + #if (_EP6_CFG_EPADR == 0) + #error "The address of Endpoint6 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint8." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP6_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint6 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP7_ENABLE == 1) + #if (_EP7_CFG_EPADR == 0) + #error "The address of Endpoint1 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint8." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP7_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint7 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP8_ENABLE == 1) + #if (_EP8_CFG_EPADR == 0) + #error "The address of Endpoint8 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP9_ENABLE == 1) + #if (_EP8_CFG_EPADR == _EP9_CFG_EPADR) + #error "The address of Endpoint8 (EPADR) conflicts with Endpoint9." + #endif + #endif +#endif + +#if (_EP9_ENABLE == 1) + #if (_EP9_CFG_EPADR == 0) + #error "The address of Endpoint9 (EPADR) cannot be 0." + #endif + #if (_EP1_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP1_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint1." + #endif + #endif + #if (_EP2_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP2_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint2." + #endif + #endif + #if (_EP3_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP3_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint3." + #endif + #endif + #if (_EP4_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP4_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint4." + #endif + #endif + #if (_EP5_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP5_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint5." + #endif + #endif + #if (_EP6_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP6_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint6." + #endif + #endif + #if (_EP7_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP7_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint7." + #endif + #endif + #if (_EP8_ENABLE == 1) + #if (_EP9_CFG_EPADR == _EP8_CFG_EPADR) + #error "The address of Endpoint9 (EPADR) conflicts with Endpoint8." + #endif + #endif +#endif + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Check Buffer size */ +/*----------------------------------------------------------------------------------------------------------*/ +#if ((_EP0LEN_T + _EP1LEN + _EP2LEN + _EP3LEN + _EP4LEN_T + _EP5LEN_T + _EP6LEN_T + _EP7LEN_T + _EP8LEN + _EP9LEN) > 1024) + #error "Total buffer size of Endpoint 0 ~ 7 (or 0 ~ 9) must be less than 1024 bytes." +#endif + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbdinit.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbdinit.h new file mode 100644 index 00000000000..97184ef903c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_usbdinit.h @@ -0,0 +1,330 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_usbdinit.h + * @version $Rev:: 5656 $ + * @date $Date:: 2021-11-24 #$ + * @brief The header file of the USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_USBDINIT_H +#define __HT32F5XXXX_USBDINIT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32_retarget_usbdconf.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup USBDevice + * @{ + */ + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint 0 ~ 7 Configuration */ +/* !!! DO NOT MODIFY !!! */ +/*----------------------------------------------------------------------------------------------------------*/ + +#define EP_TYPE_ISO (1) +#define EP_TYPE_BULK (2) +#define EP_TYPE_INT (3) + +#ifndef _UIER_ALL + #define _UIER_ALL _UIER +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP0_CFG_EPEN (1UL) +#define _EP0STADR (HT_USB_SRAM_BASE + 0x8) +#define _EP0INTADR (_EP0STADR) +#define _EP0OUTTADR (_EP0STADR + _EP0LEN) +#define _EP0_CFG ((_EP0_CFG_EPEN << 31) | \ + (_EP0LEN << 10) | \ + (_EP0STADR & EPBUFA_MASK)) +#define _EP0LEN_T (_EP0LEN * 2) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP1STADR (_EP0STADR + (_EP0LEN * 2)) + +#if (_EP1_ENABLE == 1) + #define _EP1LEN (_EP1LEN_TMP) +#else + #define _EP1LEN (0) +#endif + +#if (_EP1_CFG_EPEN_TMP == 1) + #define _EP1_CFG_EPEN (1UL) +#else + #define _EP1_CFG_EPEN (0UL) +#endif + +#define _EP1_CFG ((_EP1_CFG_EPEN << 31) | \ + (_EP1_CFG_EPDIR << 28) | \ + (_EP1_CFG_EPADR << 24) | \ + (_EP1LEN << 10) | \ + (_EP1STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP2STADR (_EP1STADR + _EP1LEN) + +#if (_EP2_ENABLE == 1) + #define _EP2LEN (_EP2LEN_TMP) +#else + #define _EP2LEN (0) +#endif + +#if (_EP2_CFG_EPEN_TMP == 1) + #define _EP2_CFG_EPEN (1UL) +#else + #define _EP2_CFG_EPEN (0UL) +#endif + +#define _EP2_CFG ((_EP2_CFG_EPEN << 31) | \ + (_EP2_CFG_EPDIR << 28) | \ + (_EP2_CFG_EPADR << 24) | \ + (_EP2LEN << 10) | \ + (_EP2STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP3STADR (_EP2STADR + _EP2LEN) + +#if (_EP3_ENABLE == 1) + #define _EP3LEN (_EP3LEN_TMP) +#else + #define _EP3LEN (0) +#endif + +#if (_EP3_CFG_EPEN_TMP == 1) + #define _EP3_CFG_EPEN (1UL) +#else + #define _EP3_CFG_EPEN (0UL) +#endif + +#define _EP3_CFG ((_EP3_CFG_EPEN << 31) | \ + (_EP3_CFG_EPDIR << 28) | \ + (_EP3_CFG_EPADR << 24) | \ + (_EP3LEN << 10) | \ + (_EP3STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP4STADR (_EP3STADR + _EP3LEN) + +#if (_EP4_ENABLE == 1) + #define _EP4LEN (_EP4LEN_TMP) + #define _EP4LEN_T (_EP4LEN_TMP * (_EP4_CFG_SDBS + 1)) +#else + #define _EP4LEN (0) + #define _EP4LEN_T (0) +#endif +#if (_EP4_TYPR == EP_TYPE_ISO) + #define _EP4_CFG_EPTYPE (1) +#else + #define _EP4_CFG_EPTYPE (0) +#endif + +#if (_EP4_CFG_EPEN_TMP == 1) + #define _EP4_CFG_EPEN (1UL) +#else + #define _EP4_CFG_EPEN (0UL) +#endif + +#define _EP4_CFG ((_EP4_CFG_EPEN << 31) | \ + (_EP4_CFG_EPTYPE << 29) | \ + (_EP4_CFG_EPDIR << 28) | \ + (_EP4_CFG_EPADR << 24) | \ + (_EP4_CFG_SDBS << 23) | \ + (_EP4LEN << 10) | \ + (_EP4STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP5STADR (_EP4STADR + _EP4LEN_T) + +#if (_EP5_ENABLE == 1) + #define _EP5LEN (_EP5LEN_TMP) + #define _EP5LEN_T (_EP5LEN_TMP * (_EP5_CFG_SDBS + 1)) +#else + #define _EP5LEN (0) + #define _EP5LEN_T (0) +#endif +#if (_EP5_TYPR == EP_TYPE_ISO) + #define _EP5_CFG_EPTYPE (1) +#else + #define _EP5_CFG_EPTYPE (0) +#endif + +#if (_EP5_CFG_EPEN_TMP == 1) + #define _EP5_CFG_EPEN (1UL) +#else + #define _EP5_CFG_EPEN (0UL) +#endif + +#define _EP5_CFG ((_EP5_CFG_EPEN << 31) | \ + (_EP5_CFG_EPTYPE << 29) | \ + (_EP5_CFG_EPDIR << 28) | \ + (_EP5_CFG_EPADR << 24) | \ + (_EP5_CFG_SDBS << 23) | \ + (_EP5LEN << 10) | \ + (_EP5STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP6STADR (_EP5STADR + _EP5LEN_T) + +#if (_EP6_ENABLE == 1) + #define _EP6LEN (_EP6LEN_TMP) + #define _EP6LEN_T (_EP6LEN_TMP * (_EP6_CFG_SDBS + 1)) +#else + #define _EP6LEN (0) + #define _EP6LEN_T (0) +#endif +#if (_EP6_TYPR == EP_TYPE_ISO) + #define _EP6_CFG_EPTYPE (1) +#else + #define _EP6_CFG_EPTYPE (0) +#endif + +#if (_EP6_CFG_EPEN_TMP == 1) + #define _EP6_CFG_EPEN (1UL) +#else + #define _EP6_CFG_EPEN (0UL) +#endif + +#define _EP6_CFG ((_EP6_CFG_EPEN << 31) | \ + (_EP6_CFG_EPTYPE << 29) | \ + (_EP6_CFG_EPDIR << 28) | \ + (_EP6_CFG_EPADR << 24) | \ + (_EP6_CFG_SDBS << 23) | \ + (_EP6LEN << 10) | \ + (_EP6STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP7STADR (_EP6STADR + _EP6LEN_T) + +#if (_EP7_ENABLE == 1) + #define _EP7LEN (_EP7LEN_TMP) + #define _EP7LEN_T (_EP7LEN_TMP * (_EP7_CFG_SDBS + 1)) +#else + #define _EP7LEN (0) + #define _EP7LEN_T (0) +#endif +#if (_EP7_TYPR == EP_TYPE_ISO) + #define _EP7_CFG_EPTYPE (1) +#else + #define _EP7_CFG_EPTYPE (0) +#endif + +#if (_EP7_CFG_EPEN_TMP == 1) + #define _EP7_CFG_EPEN (1UL) +#else + #define _EP7_CFG_EPEN (0UL) +#endif + +#define _EP7_CFG ((_EP7_CFG_EPEN << 31) | \ + (_EP7_CFG_EPTYPE << 29) | \ + (_EP7_CFG_EPDIR << 28) | \ + (_EP7_CFG_EPADR << 24) | \ + (_EP7_CFG_SDBS << 23) | \ + (_EP7LEN << 10) | \ + (_EP7STADR & EPBUFA_MASK)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint8 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP8STADR (_EP7STADR + _EP7LEN_T) + +#if (_EP8_ENABLE == 1) + #define _EP8LEN (_EP8LEN_TMP) +#else + #define _EP8LEN (0) +#endif + +#if (_EP8_CFG_EPEN_TMP == 1) + #define _EP8_CFG_EPEN (1UL) +#else + #define _EP8_CFG_EPEN (0UL) +#endif + +#define _EP8_CFG ((_EP8_CFG_EPEN << 31) | \ + (_EP8_CFG_EPDIR << 28) | \ + (_EP8_CFG_EPADR << 24) | \ + (_EP8LEN << 10) | \ + (_EP8STADR & EPBUFA_MASK)) + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint9 Configuration */ +/*----------------------------------------------------------------------------------------------------------*/ +#define _EP9STADR (_EP8STADR + _EP8LEN) + +#if (_EP9_ENABLE == 1) + #define _EP9LEN (_EP9LEN_TMP) +#else + #define _EP9LEN (0) +#endif + +#if (_EP9_CFG_EPEN_TMP == 1) + #define _EP9_CFG_EPEN (1UL) +#else + #define _EP9_CFG_EPEN (0UL) +#endif + +#define _EP9_CFG ((_EP9_CFG_EPEN << 31) | \ + (_EP9_CFG_EPDIR << 28) | \ + (_EP9_CFG_EPADR << 24) | \ + (_EP9LEN << 10) | \ + (_EP9STADR & EPBUFA_MASK)) + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_wdt.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_wdt.h new file mode 100644 index 00000000000..ae5fdd1c5e9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f5xxxx_wdt.h @@ -0,0 +1,149 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_wdt.h + * @version $Rev:: 1704 $ + * @date $Date:: 2017-08-17 #$ + * @brief The header file of the WDT library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F5XXXX_WDT_H +#define __HT32F5XXXX_WDT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup WDT + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Exported_Constants WDT exported constants + * @{ + */ + +/* WDT prescaler */ +#define WDT_PRESCALER_1 ((u16)0x0000) +#define WDT_PRESCALER_2 ((u16)0x1000) +#define WDT_PRESCALER_4 ((u16)0x2000) +#define WDT_PRESCALER_8 ((u16)0x3000) +#define WDT_PRESCALER_16 ((u16)0x4000) +#define WDT_PRESCALER_32 ((u16)0x5000) +#define WDT_PRESCALER_64 ((u16)0x6000) +#define WDT_PRESCALER_128 ((u16)0x7000) + +#define IS_WDT_PRESCALER(PRESCALER) ((PRESCALER == WDT_PRESCALER_1) || \ + (PRESCALER == WDT_PRESCALER_2) || \ + (PRESCALER == WDT_PRESCALER_4) || \ + (PRESCALER == WDT_PRESCALER_8) || \ + (PRESCALER == WDT_PRESCALER_16) || \ + (PRESCALER == WDT_PRESCALER_32) || \ + (PRESCALER == WDT_PRESCALER_64) || \ + (PRESCALER == WDT_PRESCALER_128)) + + +/* WDT runs or halts in sleep and deep sleep1 mode */ +/* WDT WDTSHLT mask */ +#define MODE0_WDTSHLT_BOTH ((u32)0x00000000) +#define MODE0_WDTSHLT_SLEEP ((u32)0x00004000) +#define MODE0_WDTSHLT_HALT ((u32)0x00008000) + +#define IS_WDT_WDTSHLT_MODE(WDT_Mode) ((WDT_Mode == MODE0_WDTSHLT_BOTH) || \ + (WDT_Mode == MODE0_WDTSHLT_SLEEP) || \ + (WDT_Mode == MODE0_WDTSHLT_HALT)) + + + +/* WDT Flag */ +#define WDT_FLAG_UNDERFLOW ((u32)0x00000001) +#define WDT_FLAG_ERROR ((u32)0x00000002) + + +#define IS_WDT_FLAG(WDT_FLAG) ((WDT_FLAG == WDT_FLAG_UNDERFLOW) || \ + (WDT_FLAG == WDT_FLAG_ERROR)) + + +#define IS_WDT_RELOAD(WDTV) ((WDTV <= 0xFFF)) + +#define IS_WDT_DELTA(WDTD) ((WDTD <= 0xFFF)) + +#if (LIBCFG_LSE) +/* WDT Source Select */ +#define WDT_SOURCE_LSI ((u32)0x00000000) +#define WDT_SOURCE_LSE ((u32)0x00000001) + + +#define IS_WDT_SOURCE_SELECT(WDT_SOURCE) ((WDT_SOURCE == WDT_SOURCE_LSI) || \ + (WDT_SOURCE == WDT_SOURCE_LSE)) +#endif +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Exported_Functions WDT exported functions + * @{ + */ +void WDT_DeInit(void); +void WDT_Cmd(ControlStatus NewState); +void WDT_HaltConfig(u32 WDT_Mode); +void WDT_ResetCmd(ControlStatus NewState); +void WDT_ProtectCmd(ControlStatus NewState); +void WDT_SetReloadValue(u16 WDTV); +u16 WDT_GetReloadValue(void); +void WDT_SetDeltaValue(u16 WDTD); +u16 WDT_GetDeltaValue(void); +void WDT_SetPrescaler(u16 WDT_PRESCALER); +u8 WDT_GetPrescaler(void); +void WDT_Restart(void); +FlagStatus WDT_GetFlagStatus (u32 WDT_FLAG); +void WDT_LockCmd(ControlStatus NewState); +#if (LIBCFG_LSE) +void WDT_SourceConfig(u32 WDT_SOURCE); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f61141_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f61141_libcfg.h new file mode 100644 index 00000000000..030674e28b2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f61141_libcfg.h @@ -0,0 +1,76 @@ +/*********************************************************************************************************//** + * @file ht32f61141_libcfg.h + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F61141_LIBCFG_H +#define __HT32F61141_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F61141) +#define USE_MEM_HT32F61141 +#endif + +#define LIBCFG_MAX_SPEED (48000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F61141 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 16) + #define LIBCFG_CHIPNAME (0x61141) +#endif + +#define LIBCFG_NO_ADC (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CRC (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_LSE (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_NO_USART0 (1) +#define LIBCFG_PWRCU_WAKEUP_V01 (1) +#define LIBCFG_PWRCU_WAKEUP1 (1) +#define LIBCFG_PWRCU_PORF (1) +#define LIBCFG_PWRCU_VREG (1) +#define LIBCFG_PWRCU_VREG_2V5 (1) +#define LIBCFG_SCI0 (1) +#define LIBCFG_SCI1 (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_USBD (1) +#define LIBCFG_USBD_V2 (1) + + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f61244_45_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f61244_45_libcfg.h new file mode 100644 index 00000000000..b7ed32e2963 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f61244_45_libcfg.h @@ -0,0 +1,73 @@ +/*********************************************************************************************************//** + * @file ht32f61244_45_libcfg.h + * @version $Rev:: 6719 $ + * @date $Date:: 2023-02-08 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F61244_45_LIBCFG_H +#define __HT32F61244_45_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F61244) && !defined(USE_MEM_HT32F61245) +#define USE_MEM_HT32F61245 +#endif + +#define LIBCFG_MAX_SPEED (48000000) + +#define LIBCFG_FLASH_PAGESIZE (512) + +#ifdef USE_MEM_HT32F61244 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x61244) +#endif + +#ifdef USE_MEM_HT32F61245 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x61245) +#endif + +#define LIBCFG_BFTM1 (1) +#define LIBCFG_DACDUAL16 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPIOD (1) +#define LIBCFG_MIDI (1) +#define LIBCFG_NO_USART0 (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_QSPI (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_ADC_CH12_15 (1) +#define LIBCFG_CKCU_NO_AUTO_TRIM (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) +#define LIBCFG_PWRCU_V15_READY_SOURCE (1) +#define LIBCFG_TM_NO_ITI (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65230_40_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65230_40_libcfg.h new file mode 100644 index 00000000000..bbf4192d74d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65230_40_libcfg.h @@ -0,0 +1,92 @@ +/*********************************************************************************************************//** + * @file ht32f65230_40_libcfg.h + * @version $Rev:: 7184 $ + * @date $Date:: 2023-08-31 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F65230_40_LIBCFG_H +#define __HT32F65230_40_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F65240) && !defined(USE_MEM_HT32F65230) +#define USE_MEM_HT32F65240 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F65230 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 32) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x65230) +#endif + +#ifdef USE_MEM_HT32F65240 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x65240) +#endif + +#define LIBCFG_ADC1 (1) +#define LIBCFG_ADC_SAMPLE_TIME_BY_CH (1) +#define LIBCFG_ADC_TRIG_DELAY (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CMP (1) +#define LIBCFG_CMP2 (1) +#define LIBCFG_CMP_NOSCALER_SRC (1) +#define LIBCFG_CMP_65x_VER (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_EXTI_4_9_GROUP (1) +#define LIBCFG_FMC_BRANCHCACHE (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPTM_GIRQ (1) +#define LIBCFG_LSE (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_MCTM_UEV1DIS (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_OPA (1) +#define LIBCFG_OPA1 (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_PDMA_CH3FIX (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_TM_652XX_V1 (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_NO_PORF (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65232_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65232_libcfg.h new file mode 100644 index 00000000000..8787c994132 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65232_libcfg.h @@ -0,0 +1,90 @@ +/*********************************************************************************************************//** + * @file ht32f65232_libcfg.h + * @version $Rev:: 6932 $ + * @date $Date:: 2023-05-11 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F65232_LIBCFG_H +#define __HT32F65232_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F65232) +#define USE_MEM_HT32F65232 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F65232 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 31) + #define LIBCFG_RAM_SIZE (1024 * 4) + #define LIBCFG_CHIPNAME (0x65232) +#endif + +#define LIBCFG_ADC_SAMPLE_TIME_BY_CH (1) +#define LIBCFG_ADC_TRIG_SRC_V2 (1) +#define LIBCFG_ADC_TRIG_DELAY (1) +#define LIBCFG_ADC_CH_65232 (1) +#define LIBCFG_AFIO_SCTM_MODE9 (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_NO_ADCPRE_DIV1 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CMP (1) +#define LIBCFG_CMP_NOSCALER_SRC (1) +#define LIBCFG_CMP_65x_VER (1) +#define LIBCFG_CMP_POS_INPUT_SEL_V2 (1) +#define LIBCFG_CMP_CO (1) +#define LIBCFG_CMP_SCALER_8BIT (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_EXTI_4_9_GROUP (1) +#define LIBCFG_FMC_BRANCHCACHE (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_GPTM_GIRQ (1) +#define LIBCFG_MCTM0 (1) +#define LIBCFG_MCTM_UEV1DIS (1) +#define LIBCFG_PWRCU_NO_PD_MODE (1) +#define LIBCFG_PWRCU_NO_PDF (1) +#define LIBCFG_PWRCU_NO_VDDPORF (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_OPA (1) +#define LIBCFG_OPA_V2 (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_TM_652XX_V1 (1) +#define LIBCFG_TM_65232 (1) +#define LIBCFG_TM_TIFN_5BIT (1) +#define LIBCFG_PWRCU_VDD_5V (1) +#define LIBCFG_PWRCU_NO_PORF (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_adc.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_adc.h new file mode 100644 index 00000000000..0b0313fc40c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_adc.h @@ -0,0 +1,417 @@ +/*********************************************************************************************************//** + * @file ht32f65xxx_66xxx_adc.h + * @version $Rev:: 7058 $ + * @date $Date:: 2023-07-27 #$ + * @brief The header file of the ADC library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F65XXX_66XXX_ADC_H +#define __HT32F65XXX_66XXX_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Constants ADC exported constants + * @{ + */ +#if (LIBCFG_ADC1) +#define IS_ADC(x) ((x == HT_ADC0) || (x == HT_ADC1)) +#else +#define IS_ADC(x) (x == HT_ADC0) +#endif + +#define ONE_SHOT_MODE (0x00000000) +#define CONTINUOUS_MODE (0x00000002) +#define DISCONTINUOUS_MODE (0x00000003) + +#define IS_ADC_CONVERSION_MODE(REGULAR_MODE) (((REGULAR_MODE) == ONE_SHOT_MODE) || \ + ((REGULAR_MODE) == CONTINUOUS_MODE) || \ + ((REGULAR_MODE) == DISCONTINUOUS_MODE)) + +#define IS_ADC_HP_CONVERSION_MODE(HP_MODE) (((HP_MODE) == ONE_SHOT_MODE) || \ + ((HP_MODE) == CONTINUOUS_MODE) || \ + ((HP_MODE) == DISCONTINUOUS_MODE)) + +#define DUAL_INDEPENDENT (0x00000000) +#define DUAL_CASCADE_REGULAR (0x00000001) +#define DUAL_CASCADE_REGULAR_H_PRIORITY (0x00000003) + +#define IS_ADC_DUAL_MODE(DUAL_MODE) (((DUAL_MODE) == DUAL_INDEPENDENT) || \ + ((DUAL_MODE) == DUAL_CASCADE_REGULAR) || \ + ((DUAL_MODE) == DUAL_CASCADE_REGULAR_H_PRIORITY)) + +#if (LIBCFG_ADC_CH_65232) +#define ADC_CH_0 (0) +#define ADC_CH_1 (1) +#define ADC_CH_2 (2) +#define ADC_CH_3 (3) +#define ADC_CH_4 (4) +#define ADC_CH_5 (5) +#define ADC_CH_6 (6) +#define ADC_CH_7 (7) +#define ADC_CH_8 (8) +#define ADC_CH_9 (9) +#define ADC_CH_10 (10) +#define ADC_CH_11 (11) +#define ADC_CH_OPA0 (12) +#define ADC_CH_GND_VREF (13) +#define ADC_CH_VDD_VREF (14) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || \ + ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) || \ + ((CHANNEL) == ADC_CH_OPA0) || \ + ((CHANNEL) == ADC_CH_GND_VREF) || ((CHANNEL) == ADC_CH_VDD_VREF)) + +#define IS_ADC_INPUT_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + ((CHANNEL) == ADC_CH_OPA0)) +#else +#define ADC_CH_0 (0) +#define ADC_CH_1 (1) +#define ADC_CH_2 (2) +#define ADC_CH_3 (3) +#define ADC_CH_4 (4) +#define ADC_CH_5 (5) +#define ADC_CH_6 (6) +#define ADC_CH_7 (7) +#define ADC_CH_OPA0 (8) +#define ADC_CH_OPA1 (9) +#define ADC_CH_GND_VREF (12) +#define ADC_CH_VDD_VREF (13) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + ((CHANNEL) == ADC_CH_OPA0) || ((CHANNEL) == ADC_CH_OPA1) || \ + ((CHANNEL) == ADC_CH_GND_VREF) || ((CHANNEL) == ADC_CH_VDD_VREF)) + +#define IS_ADC_INPUT_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ + ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ + ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ + ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) || \ + ((CHANNEL) == ADC_CH_OPA0) || ((CHANNEL) == ADC_CH_OPA1)) +#endif + + +#define ADC_TRIG_SOFTWARE (1UL << 0) + +#define ADC_TRIG_MCTM0_MTO ((1UL << 2) | (0UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH0O ((1UL << 2) | (1UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH1O ((1UL << 2) | (2UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH2O ((1UL << 2) | (3UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH3O ((1UL << 2) | (4UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH0MEV ((1UL << 2) | (0x18UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH0DEV ((1UL << 2) | (0x28UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH0MDEV ((1UL << 2) | (0x38UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH1MEV ((1UL << 2) | (0x19UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH1DEV ((1UL << 2) | (0x29UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH1MDEV ((1UL << 2) | (0x39UL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH2MEV ((1UL << 2) | (0x1AUL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH2DEV ((1UL << 2) | (0x2AUL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH2MDEV ((1UL << 2) | (0x3AUL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH3MEV ((1UL << 2) | (0x1BUL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH3DEV ((1UL << 2) | (0x2BUL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CH3MDEV ((1UL << 2) | (0x3BUL << 24) | (0UL << 16)) + +#define IS_ADC_TRIG_MCTM0_CHALL(REGTRIG) (0) + +#if (LIBCFG_ADC_TRIG_SRC_V2) +#define ADC_TRIG_MCTM0_CHALLMEV ((1UL << 2) | (0x1CUL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CHALLDEV ((1UL << 2) | (0x2CUL << 24) | (0UL << 16)) +#define ADC_TRIG_MCTM0_CHALLMDEV ((1UL << 2) | (0x3CUL << 24) | (0UL << 16)) + +#undef IS_ADC_TRIG_MCTM0_CHALL +#define IS_ADC_TRIG_MCTM0_CHALL(REGTRIG) ((REGTRIG == ADC_TRIG_MCTM0_CHALLMEV) || \ + (REGTRIG == ADC_TRIG_MCTM0_CHALLDEV) || \ + (REGTRIG == ADC_TRIG_MCTM0_CHALLMDEV)) +#endif + +#define ADC_TRIG_CMP0 ((1UL << 4) | (0UL << 20)) +#define ADC_TRIG_CMP1 ((1UL << 4) | (1UL << 20)) +#define ADC_TRIG_CMP2 ((1UL << 4) | (2UL << 20)) + +#define ADC_TRIG_BFTM0 ((1UL << 3) | (0UL << 22) | (0UL << 19)) +#define ADC_TRIG_BFTM1 ((1UL << 3) | (0UL << 22) | (1UL << 19)) + +#define ADC_TRIG_GPTM0_MTO ((1UL << 2) | (0UL << 24) | (1UL << 16)) +#define ADC_TRIG_GPTM0_CH0O ((1UL << 2) | (1UL << 24) | (1UL << 16)) +#define ADC_TRIG_GPTM0_CH1O ((1UL << 2) | (2UL << 24) | (1UL << 16)) +#define ADC_TRIG_GPTM0_CH2O ((1UL << 2) | (3UL << 24) | (1UL << 16)) +#define ADC_TRIG_GPTM0_CH3O ((1UL << 2) | (4UL << 24) | (1UL << 16)) + +#define ADC_TRIG_EXTI_0 ((1UL << 1) | ( 0UL << 8)) +#define ADC_TRIG_EXTI_1 ((1UL << 1) | ( 1UL << 8)) +#define ADC_TRIG_EXTI_2 ((1UL << 1) | ( 2UL << 8)) +#define ADC_TRIG_EXTI_3 ((1UL << 1) | ( 3UL << 8)) +#define ADC_TRIG_EXTI_4 ((1UL << 1) | ( 4UL << 8)) +#define ADC_TRIG_EXTI_5 ((1UL << 1) | ( 5UL << 8)) +#define ADC_TRIG_EXTI_6 ((1UL << 1) | ( 6UL << 8)) +#define ADC_TRIG_EXTI_7 ((1UL << 1) | ( 7UL << 8)) +#define ADC_TRIG_EXTI_8 ((1UL << 1) | ( 8UL << 8)) +#define ADC_TRIG_EXTI_9 ((1UL << 1) | ( 9UL << 8)) +#define ADC_TRIG_EXTI_10 ((1UL << 1) | (10UL << 8)) +#define ADC_TRIG_EXTI_11 ((1UL << 1) | (11UL << 8)) +#define ADC_TRIG_EXTI_12 ((1UL << 1) | (12UL << 8)) +#define ADC_TRIG_EXTI_13 ((1UL << 1) | (13UL << 8)) +#define ADC_TRIG_EXTI_14 ((1UL << 1) | (14UL << 8)) +#define ADC_TRIG_EXTI_15 ((1UL << 1) | (15UL << 8)) + +#define IS_ADC_TRIG(REGTRIG) (((REGTRIG) == ADC_TRIG_GPTM0_MTO) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH0O) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH1O) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH2O) || \ + ((REGTRIG) == ADC_TRIG_GPTM0_CH3O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_MTO) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH0O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH1O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH2O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH3O) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH0MEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH0DEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH0MDEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH1MEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH1DEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH1MDEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH2MEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH2DEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH2MDEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH3MEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH3DEV) || \ + ((REGTRIG) == ADC_TRIG_MCTM0_CH3MDEV) || \ + (IS_ADC_TRIG_MCTM0_CHALL(REGTRIG)) || \ + ((REGTRIG) == ADC_TRIG_BFTM0) || \ + ((REGTRIG) == ADC_TRIG_BFTM1) || \ + ((REGTRIG) == ADC_TRIG_CMP0) || \ + ((REGTRIG) == ADC_TRIG_CMP1) || \ + ((REGTRIG) == ADC_TRIG_CMP2) || \ + ((REGTRIG) == ADC_TRIG_EXTI_0) || \ + ((REGTRIG) == ADC_TRIG_EXTI_1) || \ + ((REGTRIG) == ADC_TRIG_EXTI_2) || \ + ((REGTRIG) == ADC_TRIG_EXTI_3) || \ + ((REGTRIG) == ADC_TRIG_EXTI_4) || \ + ((REGTRIG) == ADC_TRIG_EXTI_5) || \ + ((REGTRIG) == ADC_TRIG_EXTI_6) || \ + ((REGTRIG) == ADC_TRIG_EXTI_7) || \ + ((REGTRIG) == ADC_TRIG_EXTI_8) || \ + ((REGTRIG) == ADC_TRIG_EXTI_9) || \ + ((REGTRIG) == ADC_TRIG_EXTI_10) || \ + ((REGTRIG) == ADC_TRIG_EXTI_11) || \ + ((REGTRIG) == ADC_TRIG_EXTI_12) || \ + ((REGTRIG) == ADC_TRIG_EXTI_13) || \ + ((REGTRIG) == ADC_TRIG_EXTI_14) || \ + ((REGTRIG) == ADC_TRIG_EXTI_15) || \ + ((REGTRIG) == ADC_TRIG_SOFTWARE)) + + +#define ADC_INT_SINGLE_EOC (0x00000001) +#define ADC_INT_SUB_GROUP_EOC (0x00000002) +#define ADC_INT_CYCLE_EOC (0x00000004) +#define ADC_INT_HP_SINGLE_EOC (0x00000100) +#define ADC_INT_HP_SUB_GROUP_EOC (0x00000200) +#define ADC_INT_HP_CYCLE_EOC (0x00000400) +#define ADC_INT_AWD_LOWER (0x00010000) +#define ADC_INT_AWD_UPPER (0x00020000) +#define ADC_INT_DATA_OVERWRITE (0x01000000) +#define ADC_INT_HP_DATA_OVERWRITE (0x02000000) + +#define IS_ADC_INT(INT) ((((INT) & 0xFCFCFF88) == 0) && ((INT) != 0)) + + +#define ADC_FLAG_SINGLE_EOC (0x00000001) +#define ADC_FLAG_SUB_GROUP_EOC (0x00000002) +#define ADC_FLAG_CYCLE_EOC (0x00000004) +#define ADC_FLAG_HP_SINGLE_EOC (0x00000100) +#define ADC_FLAG_HP_SUB_GROUP_EOC (0x00000200) +#define ADC_FLAG_HP_CYCLE_EOC (0x00000400) +#define ADC_FLAG_AWD_LOWER (0x00010000) +#define ADC_FLAG_AWD_UPPER (0x00020000) +#define ADC_FLAG_DATA_OVERWRITE (0x01000000) +#define ADC_FLAG_HP_DATA_OVERWRITE (0x02000000) + +#define IS_ADC_FLAG(FLAG) ((((FLAG) & 0xFCFCFF88) == 0) && ((FLAG) != 0)) + + +#define ADC_REGULAR_DATA0 (0) +#define ADC_REGULAR_DATA1 (1) +#define ADC_REGULAR_DATA2 (2) +#define ADC_REGULAR_DATA3 (3) +#define ADC_REGULAR_DATA4 (4) +#define ADC_REGULAR_DATA5 (5) +#define ADC_REGULAR_DATA6 (6) +#define ADC_REGULAR_DATA7 (7) + +#define IS_ADC_REGULAR_DATA(DATA) ((DATA) < 8) + + +#define ADC_HP_DATA0 (0) +#define ADC_HP_DATA1 (1) +#define ADC_HP_DATA2 (2) +#define ADC_HP_DATA3 (3) + +#define IS_ADC_HP_DATA(DATA) ((DATA) < 4) + + +#define ADC_AWD_DISABLE (u8)0x00 +#define ADC_AWD_ALL_LOWER (u8)0x05 +#define ADC_AWD_ALL_UPPER (u8)0x06 +#define ADC_AWD_ALL_LOWER_UPPER (u8)0x07 +#define ADC_AWD_SINGLE_LOWER (u8)0x01 +#define ADC_AWD_SINGLE_UPPER (u8)0x02 +#define ADC_AWD_SINGLE_LOWER_UPPER (u8)0x03 + +#define IS_ADC_AWD(AWD) (((AWD) == ADC_AWD_DISABLE) || \ + ((AWD) == ADC_AWD_ALL_LOWER) || \ + ((AWD) == ADC_AWD_ALL_UPPER) || \ + ((AWD) == ADC_AWD_ALL_LOWER_UPPER) || \ + ((AWD) == ADC_AWD_SINGLE_LOWER) || \ + ((AWD) == ADC_AWD_SINGLE_UPPER) || \ + ((AWD) == ADC_AWD_SINGLE_LOWER_UPPER)) + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) < 4096) + +#define ADC_PDMA_REGULAR_SINGLE (0x00000001) +#define ADC_PDMA_REGULAR_SUBGROUP (0x00000002) +#define ADC_PDMA_REGULAR_CYCLE (0x00000004) + +#define ADC_PDMA_HP_SINGLE (0x00000100) +#define ADC_PDMA_HP_SUBGROUP (0x00000200) +#define ADC_PDMA_HP_CYCLE (0x00000400) + +#define IS_ADC_PDMA(PDMA) (((PDMA) == ADC_PDMA_REGULAR_SINGLE) || \ + ((PDMA) == ADC_PDMA_REGULAR_SUBGROUP) || \ + ((PDMA) == ADC_PDMA_REGULAR_CYCLE) || \ + ((PDMA) == ADC_PDMA_HP_SINGLE) || \ + ((PDMA) == ADC_PDMA_HP_SUBGROUP) || \ + ((PDMA) == ADC_PDMA_HP_CYCLE)) + + +#define IS_ADC_INPUT_SAMPLING_TIME(TIME) ((TIME) <= 255) + +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) < 4096) + +#define IS_ADC_REGULAR_RANK(RANK) ((RANK) < 8) + +#define IS_ADC_HP_RANK(RANK) ((RANK) < 4) + +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 8)) +#define IS_ADC_REGULAR_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 8)) + +#define IS_ADC_HP_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 4)) +#define IS_ADC_HP_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 4)) + +#define IS_ADC_TRIG_DELAY(DELAY) ((DELAY) < 256) + +typedef enum +{ + ADC_ALIGN_RIGHT = (0 << 14), + ADC_ALIGN_LEFT = (1 << 14), +} ADC_ALIGN_Enum; + +#define IS_ADC_ALIGN(ALIGN) (((ALIGN) == ADC_ALIGN_RIGHT) || ((ALIGN) == ADC_ALIGN_LEFT)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Functions ADC exported functions + * @{ + */ +void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn); +void ADC_Reset(HT_ADC_TypeDef* HT_ADCn); +void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +#if (LIBCFG_ADC1) +void ADC_DualModeConfig(HT_ADC_TypeDef* HT_ADCn, u32 DUAL_X, u8 HDelayTime, u8 DelayTime); +#endif + +void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock); +void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength); +void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x); + +void ADC_HPChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock); +void ADC_HPGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength); +void ADC_HPTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x); + +void ADC_ChannelDataAlign(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ADC_ALIGN_Enum ADC_ALIGN_x); +void ADC_ChannelOffsetValue(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u16 OffsetValue); +void ADC_ChannelOffsetCmd(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ControlStatus NewState); + +#if (LIBCFG_ADC_TRIG_DELAY) +void ADC_TrigDelayConfig(HT_ADC_TypeDef* HT_ADCn, u8 HDelayTime, u8 DelayTime); +#endif + +void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); +void ADC_HPSoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); + +u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn); +u16 ADC_GetHPConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_HP_DATAn); + +void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState); +FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); +void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); +FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x); + +void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x); +void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n); +void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER); + +void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_opa.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_opa.h new file mode 100644 index 00000000000..f8cfc6cca8c --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_opa.h @@ -0,0 +1,215 @@ +/*********************************************************************************************************//** + * @file ht32f65xxx_66xxx_opa.h + * @version $Rev:: 6911 $ + * @date $Date:: 2023-05-10 #$ + * @brief The header file of the OPA library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F65XXX_66XXX_OPA_H +#define __HT32F65XXX_66XXX_OPA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup OPA + * @{ + */ + + +/* Exported types ------------------------------------------------------------------------------------------*/ +#if (LIBCFG_OPA_V2) +/** @defgroup OPA_Exported_Types OPA exported types + * @{ + */ +/** + * @brief Definition of CMP init structure. + */ +typedef struct +{ + u32 OPA_ScalerEnable; + u32 OPA_ExternalPinEnable; + #if (LIBCFG_OPA_PGA) + u32 OPA_PGAEnable; + u32 OPA_UnitGainEnable; + u32 OPA_PGAGain; + #endif +} OPA_InitTypeDef; +/** + * @brief Enumeration of OPA PGA Gain. + */ +typedef enum +{ + /* OPnPGA = 1, OPnDACEN = 0 */ + PGA_GAIN_6 = 0x0, + PGA_GAIN_8 = 0x1, + PGA_GAIN_12 = 0x2, + PGA_GAIN_16 = 0x3, + PGA_GAIN_24 = 0x4, + PGA_GAIN_32 = 0x5, + PGA_GAIN_48 = 0x6, + PGA_GAIN_64 = 0x7, + + /* OPnPGA = 1, OPnDACEN = 1 */ + PGA_GAIN_5 = 0x0, + PGA_GAIN_7 = 0x1, + PGA_GAIN_11 = 0x2, + PGA_GAIN_15 = 0x3, + PGA_GAIN_23 = 0x4, + PGA_GAIN_31 = 0x5, + PGA_GAIN_47 = 0x6, + PGA_GAIN_63 = 0x7, +} OPA_PGA_Enum; +/** + * @} + */ +#endif + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup OPA_Exported_Constants OPA exported constants + * @{ + */ +#define OPA_UNPROTECT_KEY (0x9C3A) + +#if (LIBCFG_OPA1) +#define IS_OPA1(PERIPH) (PERIPH == HT_OPA1) +#else +#define IS_OPA1(PERIPH) (0) +#endif +#define IS_OPA(PERIPH) ((PERIPH == HT_OPA0) || IS_OPA1(PERIPH)) + +#if (LIBCFG_OPA_V2) +/* Definitions of OPA DAC Enable Bit */ +#define OPA_SCALER_ENABLE ((u32)0x00000100) +#define OPA_SCALER_DISABLE ((u32)0x00000000) + +/* Definitions of OPA External Pin Enable Bit */ +#define OPA_ExternalPin_ENABLE ((u32)0x00000008) +#define OPA_ExternalPin_DISABLE ((u32)0x00000000) + +/* Definitions of OPA PGA Enable Bit */ +#define OPA_PGA_ENABLE ((u32)0x00000004) +#define OPA_PGA_DISABLE ((u32)0x00000000) + +/* Definitions of OPA UnitGain Enable Bit */ +#define OPA_UNITGAIN_ENABLE ((u32)0x00000002) +#define OPA_UNITGAIN_DISABLE ((u32)0x00000000) + +/* Definitions of OPA Output Status */ +#define OPA_OUTPUT_HIGH ((u32)0x00000080) +#define OPA_OUTPUT_LOW ((u32)0x00000000) + +#define OPA_NORMAL_MODE (0) +#define OPA_OFFSET_CALIBRATION_MODE (1) + +#define OPA_INPUT_OFFSET_INN (0) +#define OPA_INPUT_OFFSET_INP (1) + +/** + * @brief Used to check parameter of the OPAx. + */ +#define IS_OPA_ScalerEnable(x) ((x == OPA_SCALER_ENABLE) || (x == OPA_SCALER_DISABLE)) + +#define IS_OPA_ExtPinEnable(x) ((x == OPA_ExternalPin_ENABLE) || (x == OPA_ExternalPin_DISABLE)) + +#define IS_OPA_PGAEnable(x) ((x == OPA_PGA_ENABLE) || (x == OPA_PGA_DISABLE)) + +#define IS_OPA_UnitGainEnable(x) ((x == OPA_UNITGAIN_ENABLE) || (x == OPA_UNITGAIN_DISABLE)) + +#define IS_OPA_PGA_SEL(SEL) ((SEL == PGA_GAIN_5) || (SEL == PGA_GAIN_6) || \ + (SEL == PGA_GAIN_7) || (SEL == PGA_GAIN_8) || \ + (SEL == PGA_GAIN_11) || (SEL == PGA_GAIN_12) || \ + (SEL == PGA_GAIN_15) || (SEL == PGA_GAIN_16) || \ + (SEL == PGA_GAIN_23) || (SEL == PGA_GAIN_24) || \ + (SEL == PGA_GAIN_31) || (SEL == PGA_GAIN_32) || \ + (SEL == PGA_GAIN_47) || (SEL == PGA_GAIN_48) || \ + (SEL == PGA_GAIN_63) || (SEL == PGA_GAIN_64)) + +#define IS_OPA_OFMMODE(MODE) ((MODE == OPA_OFFSET_CALIBRATION_MODE) || \ + (MODE == OPA_NORMAL_MODE)) + +#define IS_OPA_INPUTOFFSET_SEL(SEL) ((SEL == OPA_INPUT_OFFSET_INN) || \ + (SEL == OPA_INPUT_OFFSET_INP)) + +/* Check the OPA Scaler Value */ +#define IS_OPA_SCALER_VALUE(x) (x <= 0x3FF) + +/* Check the OPA Input Offset Value */ +#define IS_OPA_INPUTOFFSET_VALUE(x) (x <= 0x1F) +#endif +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup OPA_Exported_Functions OPA exported functions + * @{ + */ +void OPA_DeInit(void); +void OPA_Cmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState); +void OPA_SetUnProtectKey(u32 uUnProtectKey); +void OPA_ProtectConfig(HT_OPA_TypeDef* HT_OPAn); +void OPA_UnprotectConfig(HT_OPA_TypeDef* HT_OPAn); + +#if (LIBCFG_OPA_V2) +void OPA_Init(HT_OPA_TypeDef* HT_OPAn, OPA_InitTypeDef* OPA_InitStruct); +void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct); +void OPA_ExternalInputCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState); +#if (LIBCFG_OPA_PGA) +void OPA_UnitGainCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState); +void OPA_PGACmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState); +void OPA_PGAGain(HT_OPA_TypeDef* HT_OPAn, u8 bGAIN_SEL); +#endif +void OPA_ScalerCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState); +void OPA_SetScalerValue(HT_OPA_TypeDef* HT_OPAn, u32 Scaler_Value); +FlagStatus OPA_GetOutputStatus(HT_OPA_TypeDef* HT_OPAn); +void OPA_OFMMode(HT_OPA_TypeDef* HT_OPAn, u8 bMODE); +void OPA_OFM_InputOffsetReferenceSelect(HT_OPA_TypeDef* HT_OPAn, u8 bSEL); +void OPA_SetInputOffsetVoltage(HT_OPA_TypeDef* HT_OPAn, u8 bData); +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_pga.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_pga.h new file mode 100644 index 00000000000..c72336c2fad --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f65xxx_66xxx_pga.h @@ -0,0 +1,62 @@ +/*********************************************************************************************************//** + * @file ht32f65xxx_66xxx_pga.h + * @version $Rev:: 6915 $ + * @date $Date:: 2023-05-10 #$ + * @brief The header file of the PGA library (temporary file, not finish/support yet). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F65XXX_66XXX_PGA_H +#define __HT32F65XXX_66XXX_PGA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup PGA + * @{ + */ + + + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66242_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66242_libcfg.h new file mode 100644 index 00000000000..953106da19d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66242_libcfg.h @@ -0,0 +1,52 @@ +/*********************************************************************************************************//** + * @file ht32f66242_libcfg.h + * @version $Rev:: 7184 $ + * @date $Date:: 2023-08-31 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F66242_LIBCFG_H +#define __HT32F66242_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F66242) +#define USE_MEM_HT32F66242 +#endif + +#define LIBCFG_MAX_SPEED (80000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F66242 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x66242) +#endif + +#define LIBCFG_ADC_NO_OFFSET_REG (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_PDMA (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66246_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66246_libcfg.h new file mode 100644 index 00000000000..90a37a17030 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66246_libcfg.h @@ -0,0 +1,52 @@ +/*********************************************************************************************************//** + * @file ht32f66246_libcfg.h + * @version $Rev:: 7184 $ + * @date $Date:: 2023-08-31 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F66246_LIBCFG_H +#define __HT32F66246_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F66246) +#define USE_MEM_HT32F66246 +#endif + +#define LIBCFG_MAX_SPEED (80000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F66246 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 63) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x66246) +#endif + +#define LIBCFG_ADC_NO_OFFSET_REG (1) +#define LIBCFG_GPIOC (1) +#define LIBCFG_NO_PWRCU_TEST_REG (1) +#define LIBCFG_PDMA (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_cordic.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_cordic.h new file mode 100644 index 00000000000..1c25b4c0367 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_cordic.h @@ -0,0 +1,62 @@ +/*********************************************************************************************************//** + * @file ht32f66xxx_cordic.h + * @version $Rev:: 6915 $ + * @date $Date:: 2023-05-10 #$ + * @brief The header file of the CORDIC library (temporary file, not finish/support yet). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F66XXX_CORDIC_H +#define __HT32F66XXX_CORDIC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup CORDIC + * @{ + */ + + + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_pid.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_pid.h new file mode 100644 index 00000000000..c47671643ce --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f66xxx_pid.h @@ -0,0 +1,62 @@ +/*********************************************************************************************************//** + * @file ht32f66xxx_pid.h + * @version $Rev:: 6915 $ + * @date $Date:: 2023-05-10 #$ + * @brief The header file of the PID library (temporary file, not finish/support yet). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F66XXX_PID_H +#define __HT32F66XXX_PID_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @addtogroup PID + * @{ + */ + + + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f67041_51_libcfg.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f67041_51_libcfg.h new file mode 100644 index 00000000000..b72fe2659b3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ht32f67041_51_libcfg.h @@ -0,0 +1,78 @@ +/*********************************************************************************************************//** + * @file ht32f67041_51_libcfg.h + * @version $Rev:: 6923 $ + * @date $Date:: 2023-05-10 #$ + * @brief The library configuration file. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32F67041_51_LIBCFG_H +#define __HT32F67041_51_LIBCFG_H + +/* Settings ------------------------------------------------------------------------------------------------*/ + +#if !defined(USE_MEM_HT32F67041) && !defined(USE_MEM_HT32F67051) +#define USE_MEM_HT32F67051 +#endif + +#define LIBCFG_MAX_SPEED (60000000) + +#define LIBCFG_FLASH_PAGESIZE (1024) + +#ifdef USE_MEM_HT32F67041 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 64) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x67041) +#endif + +#ifdef USE_MEM_HT32F67051 + #define LIBCFG_FLASH_SIZE (LIBCFG_FLASH_PAGESIZE * 127) + #define LIBCFG_RAM_SIZE (1024 * 8) + #define LIBCFG_CHIPNAME (0x67051) +#endif + +#define LIBCFG_ADC_CH8_11 (1) +#define LIBCFG_ADC_IVREF (1) +#define LIBCFG_ADC_MVDDA (1) +#define LIBCFG_AES (1) +#define LIBCFG_BFTM1 (1) +#define LIBCFG_CKCU_ATM_V01 (1) +#define LIBCFG_CKCU_PLLSRCDIV (1) +#define LIBCFG_CKCU_REFCLK_EXT_PIN (1) +#define LIBCFG_CKCU_SYS_CK_60M (1) +#define LIBCFG_CRC (1) +#define LIBCFG_DIV (1) +#define LIBCFG_FMC_PREFETCH (1) +#define LIBCFG_FMC_WAIT_STATE_2 (1) +#define LIBCFG_I2C1 (1) +#define LIBCFG_LSE (1) +#define LIBCFG_PDMA (1) +#define LIBCFG_SCTM0 (1) +#define LIBCFG_SCTM1 (1) +#define LIBCFG_SCTM2 (1) +#define LIBCFG_SCTM3 (1) +#define LIBCFG_NO_USART0 (1) +#define LIBCFG_SPI1 (1) +#define LIBCFG_UART1 (1) +#define LIBCFG_PWRCU_VDD_2V0_3V6 (1) + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_cm0plus_misc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_cm0plus_misc.c new file mode 100644 index 00000000000..91fc97ab995 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_cm0plus_misc.c @@ -0,0 +1,243 @@ +/*********************************************************************************************************//** + * @file ht32_cm0plus_misc.c + * @version $Rev:: 5377 $ + * @date $Date:: 2021-05-26 #$ + * @brief This file provides all the miscellaneous firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32_cm0plus_misc.h" +#include "ht32_div.c" +#include "ht32_rand.c" +#ifdef HTCFG_TIME_IPSEL +#include "ht32_time.c" +#endif + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup MISC MISC + * @brief MISC driver modules + * @{ + */ + + +/* Private definitions -------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Private_Define MISC private definitions + * @{ + */ +#define AIRCR_VECTKEY_MASK ((u32)0x05FA0000) +#define CTRL_TICKINT_SET ((u32)0x00000002) +#define CTRL_TICKINT_RESET ((u32)0xFFFFFFFD) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup MISC_Exported_Functions MISC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Set the vector table location and Offset. + * @param NVIC_VectTable: Specify if the vector table is in FLASH or RAM. + * This parameter can be one of the following values: + * @arg NVIC_VECTTABLE_RAM + * @arg NVIC_VECTTABLE_FLASH + * @param NVIC_Offset: Vector Table base offset field. + * This value must be a multiple of 0x100. + * @retval None + ***********************************************************************************************************/ +void NVIC_SetVectorTable(u32 NVIC_VectTable, u32 NVIC_Offset) +{ + /* Check the parameters */ + Assert_Param(IS_NVIC_VECTTABLE(NVIC_VectTable)); + Assert_Param(IS_NVIC_OFFSET(NVIC_Offset)); + + SCB->VTOR = NVIC_VectTable | (NVIC_Offset & (u32)0x1FFFFF80); +} + +/*********************************************************************************************************//** + * @brief Select which low power mode to execute to the system. + * @param NVIC_LowPowerMode: Specify the new low power mode to execute to the system. + * This parameter can be one of the following values: + * @arg NVIC_LOWPOWER_SEVONPEND + * @arg NVIC_LOWPOWER_SLEEPDEEP + * @arg NVIC_LOWPOWER_SLEEPONEXIT + * @param NewState: new state of low power condition. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void NVIC_LowPowerConfig(u8 NVIC_LowPowerMode, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_NVIC_LOWPOWER(NVIC_LowPowerMode)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= NVIC_LowPowerMode; + } + else + { + SCB->SCR &= (u32)(~(u32)NVIC_LowPowerMode); + } +} + +/*********************************************************************************************************//** + * @brief Set the pending bit for a system handler. + * @param SystemHandler: Specify the system handler pending bit to be set. + * This parameter can be one of the following values: + * @arg SYSTEMHANDLER_NMI + * @arg SYSTEMHANDLER_PSV + * @arg SYSTEMHANDLER_SYSTICK + * @retval None + ***********************************************************************************************************/ +void NVIC_SetPendingSystemHandler(u32 SystemHandler) +{ + /* Check the parameters */ + Assert_Param(IS_NVIC_SYSTEMHANDLER(SystemHandler)); + + /* Set the corresponding System Handler pending bit */ + SCB->ICSR |= SystemHandler; +} + +/*********************************************************************************************************//** + * @brief Configure the SysTick clock source. + * @param SysTick_ClockSource: Specify the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_SRC_STCLK : External reference clock is selected as SysTick clock source. + * @arg SYSTICK_SRC_FCLK : AHB clock is selected as SysTick clock source. + * @retval None + ***********************************************************************************************************/ +void SYSTICK_ClockSourceConfig(u32 SysTick_ClockSource) +{ + /* Check the parameters */ + Assert_Param(IS_SYSTICK_CLOCK_SOURCE(SysTick_ClockSource)); + + if (SysTick_ClockSource == SYSTICK_SRC_FCLK) + { + SysTick->CTRL |= SYSTICK_SRC_FCLK; + } + else + { + SysTick->CTRL &= SYSTICK_SRC_STCLK; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SysTick counter. + * @param SysTick_Counter: new state of the SysTick counter. + * This parameter can be one of the following values: + * @arg SYSTICK_COUNTER_DISABLE : Disable counter + * @arg SYSTICK_COUNTER_ENABLE : Enable counter + * @arg SYSTICK_COUNTER_CLEAR : Clear counter value to 0 + * @retval None + ***********************************************************************************************************/ +void SYSTICK_CounterCmd(u32 SysTick_Counter) +{ + /* Check the parameters */ + Assert_Param(IS_SYSTICK_COUNTER(SysTick_Counter)); + + if (SysTick_Counter == SYSTICK_COUNTER_CLEAR) + { + SysTick->VAL = SYSTICK_COUNTER_CLEAR; + } + else + { + if (SysTick_Counter == SYSTICK_COUNTER_ENABLE) + { + SysTick->CTRL |= SYSTICK_COUNTER_ENABLE; + } + else + { + SysTick->CTRL &= SYSTICK_COUNTER_DISABLE; + } + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the SysTick Interrupt. + * @param NewState: new state of the SysTick Interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void SYSTICK_IntConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SysTick->CTRL |= CTRL_TICKINT_SET; + } + else + { + SysTick->CTRL &= CTRL_TICKINT_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Set SysTick counter reload value. + * @param SysTick_Reload: SysTick reload new value. + * This parameter must be a number between 1 and 0xFFFFFF. + * @retval None + ***********************************************************************************************************/ +void SYSTICK_SetReloadValue(u32 SysTick_Reload) +{ + /* Check the parameters */ + Assert_Param(IS_SYSTICK_RELOAD(SysTick_Reload)); + + SysTick->LOAD = SysTick_Reload; +} + +/*********************************************************************************************************//** + * @brief Reverse bits. + * @param in: Input data + * @retval uRBIT + ***********************************************************************************************************/ +u32 RBIT(u32 in) +{ + u32 uRBIT = 0; + s32 i; + + for(i = 31; i >=0; i--) + { + uRBIT |= ((in & 0x1) << i); + in = in >> 1; + } + + return uRBIT; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_div.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_div.c new file mode 100644 index 00000000000..37403e1d5ed --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_div.c @@ -0,0 +1,55 @@ +/*********************************************************************************************************//** + * @file ht32_div.c + * @version $Rev:: 220 $ + * @date $Date:: 2016-02-16 #$ + * @brief The division assembly. + ************************************************************************************************************* +* @attention +* +* Firmware Disclaimer Information +* +* 1. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the +* proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and +* other intellectual property laws. +* +* 2. The customer hereby acknowledges and agrees that the program technical documentation, including the +* code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties +* other than HOLTEK and the customer. +* +* 3. The program technical documentation, including the code, is provided "as is" and for customer reference +* only. After delivery by HOLTEK, the customer shall use the program technical documentation, including +* the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including +* the warranties of merchantability, satisfactory quality and fitness for a particular purpose. +* +*

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +#include "ht32.h" + +/* Global variables ----------------------------------------------------------------------------------------*/ +//__ALIGN4 static uc32 Data[] = +__ALIGN4 static u32 Data[] = +{ +0x09032200, 0xD32C428B, 0x428B0A03, 0x2300D311, 0xE04E469C, 0x430B4603, 0x2200D43C, 0x428B0843, +0x0903D331, 0xD31C428B, 0x428B0A03, 0x4694D301, 0x09C3E03F, 0xD301428B, 0x1AC001CB, 0x09834152, +0xD301428B, 0x1AC0018B, 0x09434152, 0xD301428B, 0x1AC0014B, 0x09034152, 0xD301428B, 0x1AC0010B, +0x08C34152, 0xD301428B, 0x1AC000CB, 0x08834152, 0xD301428B, 0x1AC0008B, 0x08434152, 0xD301428B, +0x1AC0004B, 0x1A414152, 0x4601D200, 0x46104152, 0xE05D4770, 0xD0000FCA, 0x10034249, 0x4240D300, +0x22004053, 0x0903469C, 0xD32D428B, 0x428B0A03, 0x22FCD312, 0xBA120189, 0x428B0A03, 0x0189D30C, +0x428B1192, 0x0189D308, 0x428B1192, 0x0189D304, 0x1192D03A, 0x0989E000, 0x428B09C3, 0x01CBD301, +0x41521AC0, 0x428B0983, 0x018BD301, 0x41521AC0, 0x428B0943, 0x014BD301, 0x41521AC0, 0x428B0903, +0x010BD301, 0x41521AC0, 0x428B08C3, 0x00CBD301, 0x41521AC0, 0x428B0883, 0x008BD301, 0x41521AC0, +0x0843D2D9, 0xD301428B, 0x1AC0004B, 0x1A414152, 0x4601D200, 0x41524663, 0x4610105B, 0x4240D301, +0xD5002B00, 0x47704249, 0x105B4663, 0x4240D300, 0x2000B501, 0x46C046C0, 0x0000BD02 +}; + +u32 (*UDIV32)(u32, u32); +s32 (*SDIV32)(s32, s32); + +void DIV32_Init(void) +{ + u32 fptr = (u32)Data; + UDIV32 = (u32 (*)(u32, u32))(fptr + 0x1); + SDIV32 = (s32 (*)(s32, s32))(fptr + 0x15); +} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_rand.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_rand.c new file mode 100644 index 00000000000..435766bb0ed --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_rand.c @@ -0,0 +1,81 @@ +/*********************************************************************************************************//** + * @file ht32_rand.c + * @version $Rev:: 2069 $ + * @date $Date:: 2017-11-07 #$ + * @brief The rundom number function. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include + +/* Global variables ----------------------------------------------------------------------------------------*/ +__ALIGN4 static uc32 RandData[] = +{ + 0x4946b5ff, 0x6a4cb087, 0x6b0c9404, 0x6a4c9403, + 0x042d2503, 0x624c432c, 0x4d416b0c, 0x630c432c, + 0x68394f40, 0x2580463c, 0x402926f9, 0x1b890236, + 0x021e6039, 0x04114316, 0x0619430e, 0x607e430e, + 0x43160216, 0x4316041a, 0x60a6430e, 0x62212117, + 0x22014934, 0x630a3140, 0x432b6823, 0x4e326023, + 0x93056873, 0x685c4b31, 0x4c319406, 0x605c6074, + 0x69dd69f4, 0x43136b4b, 0x4a2a634b, 0x68533280, + 0xd5fc075b, 0x463a6b3b, 0x0f1b071b, 0x6b7b9302, + 0x071b6bbf, 0x073f0f1b, 0x97010f3f, 0x07176bd2, + 0x680a0f3f, 0x071746bc, 0x97000f3f, 0x0717684a, + 0x688a0f3f, 0x071246be, 0x0f1268c9, 0x68074e1a, + 0x042d69f6, 0x193419be, 0x4d181964, 0x69ed6004, + 0x011b9e02, 0x431e9f01, 0x023b042d, 0x46671964, + 0x432b033d, 0x431e9f00, 0x431e043b, 0x053b4677, + 0x0612431e, 0x07094316, 0x9a08430e, 0x18891931, + 0x48096001, 0x60419905, 0x99064808, 0x48036041, + 0x62419904, 0x63019903, 0xbdf0b00b, 0x40088000, + 0x01000040, 0x40010000, 0x400b0000, 0x400b2000, + 0x0000ffff +}; + +__ALIGN4 static uc32 RandData2[] = +{ + 0x4604b510, 0x18406800, 0x46216020, 0x68084a03, + 0x4a034350, 0x60081880, 0xbd100840, 0x41c64e6d, + 0x00003039 +}; + +typedef void (*Randinit_TypeDef) (u32 *, u32, u32, u32); +u32 (*Rand_Get)(u32 *, u32); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/*********************************************************************************************************//** + * @brief Rand init. + * @param uSeed + * @param uCount + * @param a + * @param b + * @retval none + ***********************************************************************************************************/ +void Rand_Init(u32 *uSeed, u32 uCount, u32 a, u32 b) +{ + Randinit_TypeDef Randinit = (Randinit_TypeDef)((u32)RandData | 0x1); + Rand_Get = (u32 (*)(u32 *, u32))((u32)RandData2 | 0x1); + Randinit(uSeed, uCount, a, b); +} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_retarget.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_retarget.c new file mode 100644 index 00000000000..5ffe762c9de --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_retarget.c @@ -0,0 +1,413 @@ +/*********************************************************************************************************//** + * @file ht32_retarget.c + * @version $Rev:: 6977 $ + * @date $Date:: 2023-06-07 #$ + * @brief Retarget layer for target-dependent low level functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_board.h" + +#if defined (__CC_ARM) + #pragma import(__use_no_semihosting_swi) +#endif + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #ifndef __MICROLIB + __asm(".global __use_no_semihosting"); + #endif +#endif + +#if (_RETARGET == 1) +#include + +#if defined (__CC_ARM) + #include +#endif + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup RETARGET Retarget + * @brief Retarget related functions + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup RETARGET_Private_Define Retarget private definitions + * @{ + */ + +#if (RETARGET_PORT == RETARGET_ITM) +#define ITM_PORT8(n) (*((vu8 *)(0xE0000000 + 4 * n))) +#define ITM_PORT16(n) (*((vu16 *)(0xE0000000 + 4 * n))) +#define ITM_PORT32(n) (*((vu32 *)(0xE0000000 + 4 * n))) + +#define DEMCR (*((vu32 *)(0xE000EDFC))) +#define TRCENA (0x01000000) +volatile int32_t ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* For Keil MDK-ARM only */ +#endif +/** + * @} + */ + +/* Global variables ----------------------------------------------------------------------------------------*/ +/** @defgroup RETARGET_Global_Variable Retarget global variables + * @{ + */ +#if defined (__CC_ARM) +struct __FILE { int handle; /* Add whatever you need here */ }; +FILE __stdout; +FILE __stdin; +#endif + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #ifndef __MICROLIB + FILE __stdout; + FILE __stdin; + FILE __stderr; + #endif +#endif + +#if defined (__SES_ARM) && defined(__SEGGER_RTL_VERSION) +struct __SEGGER_RTL_FILE_impl { // NOTE: Provides implementation for FILE + int stub; // only needed so impl has size != 0. +}; +static FILE __SEGGER_RTL_stdin_file = { 0 }; // stdin reads from UART +static FILE __SEGGER_RTL_stdout_file = { 0 }; // stdout writes to UART +static FILE __SEGGER_RTL_stderr_file = { 0 }; // stderr writes to UART + +FILE *stdin = &__SEGGER_RTL_stdin_file; // NOTE: Provide implementation of stdin for RTL. +FILE *stdout = &__SEGGER_RTL_stdout_file; // NOTE: Provide implementation of stdout for RTL. +FILE *stderr = &__SEGGER_RTL_stderr_file; // NOTE: Provide implementation of stderr for RTL. + +static int _stdin_ungot = EOF; +#endif +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup RETARGET_Exported_Functions Retarget exported functions + * @{ + */ + +void RETARGET_Configuration(void) +{ +#ifdef RETARGET_IS_UART + /* !!! NOTICE !!! + Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below in this function. + */ + USART_InitTypeDef USART_InitStructure; + #ifdef RETARGET_UxART_BAUDRATE + USART_InitStructure.USART_BaudRate = RETARGET_UxART_BAUDRATE; + #else + USART_InitStructure.USART_BaudRate = 115200; + #endif + USART_InitStructure.USART_WordLength = USART_WORDLENGTH_8B; + USART_InitStructure.USART_StopBits = USART_STOPBITS_1; + USART_InitStructure.USART_Parity = USART_PARITY_NO; + USART_InitStructure.USART_Mode = USART_MODE_NORMAL; + + #ifdef RETARGET_COM_PORT + HT32F_DVB_COMInit(RETARGET_COM_PORT, &USART_InitStructure); + #else + { /* Enable peripheral clock of UxART */ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + CKCUClock.Bit.RETARGET_UxART_IPN = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + } + + USART_Init(RETARGET_USART_PORT, &USART_InitStructure); + USART_TxCmd(RETARGET_USART_PORT, ENABLE); + USART_RxCmd(RETARGET_USART_PORT, ENABLE); + #if (RETARGET_INT_MODE == 1) + NVIC_EnableIRQ(RETARGET_UART_IRQn); + #endif + #endif +#endif + +#if (RETARGET_PORT == RETARGET_ITM) + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.AFIO = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + CKCU_MCUDBGConfig(CKCU_DBG_TRACE_ON, ENABLE); + AFIO_GPxConfig(TRACESWO_GPIO_ID, TRACESWO_AFIO_PIN, TRACESWO_AFIO_MODE); +#endif + +#ifdef NON_USB_IN_APP + SERIAL_USBDInit(); +#endif +} + +int __backspace(FILE *stream) +{ + if (stream == 0) // Remove the compiler warning + { + } + return 0; +} + +/* + Keil and IAR before 9.20 share fputc() to implement printf +*/ +int fputc (int ch, FILE *f) +{ + #if 0 + if (f == 0) // Remove the compiler warning + { + } + #endif + #if (RETARGET_PORT == RETARGET_ITM) + if (DEMCR & TRCENA) + { + while (ITM_PORT32(0) == 0); + ITM_PORT8(0) = ch; + } + return (ch); + #else + #ifdef AUTO_RETURN + if (ch == '\n') + { + SERIAL_PutChar('\r'); + } + #endif + return (SERIAL_PutChar(ch)); + #endif +} + +#if defined (__ICCARM__) +#if (__VER__ > 9010000) +/* + IAR's version after 9.20 use write to implement printf +*/ +int __write(int Handle, + const unsigned char * Buf, + int Bufsize) +{ + size_t nChars = 0; + if (Handle == -1) + { + return 0; + } + /* Check for stdout and stderr + (only necessary if FILE descriptors are enabled.) */ + if (Handle != 1 && Handle != 2) + { + return -1; + } + for (/*Empty */; Bufsize > 0; --Bufsize) + { + SERIAL_PutChar(*Buf++); + ++nChars; + } + return nChars; +} +#endif +int __read(int Handle, unsigned char *Buf, size_t BufSize) +{ + #if (RETARGET_PORT != RETARGET_ITM) + int nChars = 0; + + if (Handle != 0) + { + return -1; + } + + for (/* Empty */; BufSize > 0; --BufSize) + { + unsigned char c = NULL; + c = SERIAL_GetChar(); + if (c == 0) + break; + *Buf++ = c; + ++nChars; + } + #endif + return nChars; +} + +#elif defined(__SES_ARM) +#if defined(__SEGGER_RTL_VERSION) +/* + SES's version after 6.20 use RTL to implement printf. +*/ +/*********************************************************************************************************//** + * @brief Get character from standard input.. + * @retval Character received. + ************************************************************************************************************/ +static char _stdin_getc(void) { + unsigned char c; + + if (_stdin_ungot != EOF) { + c = _stdin_ungot; + _stdin_ungot = EOF; + } else { + c = SERIAL_GetChar(); + } + return c; +} + +/*********************************************************************************************************//** + * @brief Get file status. + * @param Pointer to file. + * @retval -1: Failure, stream is not a valid file. 0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_stat(FILE *stream) { + if (stream == stdin || stream == stdout || stream == stderr) { + return 0; // NOTE: stdin, stdout, and stderr are assumed to be valid. + } else { + return EOF; + } +} + +/*********************************************************************************************************//** + * @brief Get stream buffer size. + * @param stream: Pointer to file. + * @retval Nonzero number of characters to use for buffered I/O; for unbuffered I/O, return 1. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_bufsize(FILE *stream) { + (void)stream; + return 1; +} + +/*********************************************************************************************************//** + * @brief Read data from file. + * @param stream: Pointer to file to read from. + * @param s: Pointer to object that receives the input. + * @param len: Number of characters to read from file. + * @retval -1: Failure, stream is not a valid file. >0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_read(FILE *stream, char *s, unsigned len) { + int c; + + if (stream == stdin) { + c = 0; + while (len > 0) { + *s = _stdin_getc(); + ++s; + ++c; + --len; + } + } else { + c = EOF; + } + return c; +} + +/*********************************************************************************************************//** + * @brief Write data to file. + * @param stream: Pointer to file to write to. + * @param s:Pointer to object to write to file. + * @param len:Number of characters to write to the file. + * @retval -1: Failure, stream is not a valid file. >0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_write(FILE *stream, const char *s, unsigned len) { + if ((stream == stdout) || (stream == stderr)) { + //BSP_UART_WriteBlocking(_UART_Port, (const unsigned char*) s, len); + for (/*Empty */; len > 0; --len) + { + SERIAL_PutChar(*s++); + } + return len; + } else { + return EOF; + } +} + +/*********************************************************************************************************//** + * @brief ush character back to stream. + * @param stream: Pointer to file to push back to. + * @param c: Character to push back. + * @retval -1: Failure, stream is not a valid file. >0: Success, stream is a valid file. + ***********************************************************************************************************/ +int __SEGGER_RTL_X_file_unget(FILE *stream, int c) { + if (stream == stdin) { + if (c != EOF && _stdin_ungot == EOF) { + _stdin_ungot = c; + } else { + c = EOF; + } + } else { + c = EOF; + } + return c; +} +#endif +#else +int fgetc (FILE *f) +{ + #if 0 + if (f == 0) // Remove the compiler warning + { + } + #endif + #if (RETARGET_PORT == RETARGET_ITM) + /* For Keil MDK-ARM only */ + while (ITM_CheckChar() == 0); + return (ITM_ReceiveChar()); + #else + return (SERIAL_GetChar()); + #endif +} +#endif + +void _ttywrch(int ch) +{ + #if (RETARGET_PORT == RETARGET_ITM) + if (DEMCR & TRCENA) + { + while (ITM_PORT32(0) == 0); + ITM_PORT8(0) = ch; + } + #else + SERIAL_PutChar(ch); + #endif +} +#endif + +void _sys_exit(int return_code) +{ + if (return_code == 0) // Remove the compiler warning + { + } + +label: goto label; /* endless loop */ +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_retarget_desc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_retarget_desc.c new file mode 100644 index 00000000000..b8fec7bee6e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_retarget_desc.c @@ -0,0 +1,272 @@ +/*********************************************************************************************************//** + * @file ht32_retarget_desc.c + * @version $Rev:: 783 $ + * @date $Date:: 2016-06-10 #$ + * @brief The The USB Descriptor of retarget. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Includes ------------------------------------------------------------------------------------------------*/ + +#define DESC_LEN_CONFN_T (u16)(DESC_LEN_CONFN) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Device descriptor setting +// USB Specification Release number (bcdUSB) +// <0x0200=> USB 2.0 +// <0x0110=> USB 1.1 +// <0x0100=> USB 1.0 +// USB Class code (assigned by the USB-IF) +// <0x00=> Use class information in the Interface Descriptors (0x00) +// <0x02=> Communications and CDC Control (CDC, 0x02) +// <0xDC=> Diagnostic Device (0xDC) +// <0xEF=> Miscellaneous (0xEF) +// <0xFF=> Vendor Specific (0xFF) +// USB Subclass code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Protocol code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Vendor ID <0x0-0xFFFF:1> +// USB Product ID <0x0-0xFFFF:1> +// USB Device Version <0x0-0xFFFF:1> +// USB String descriptor - Manufacturer +// USB String descriptor - Product +// USB String descriptor - Device serial number +// USB Number of possible configurations <0-255:1> +#define DESC_BCDUSB (0x0110) +#define DESC_BDEVCLASS (0x00) +#define DESC_BDEVSUBCLASS (0x00) +#define DESC_BDEVPROTOCOL (0x00) +#define DESC_IDVENDOR (0x04D9) +#define DESC_IDPRODUCT (0x8008) +#define DESC_BCDDEVICE (0x0100) +#define DESC_IMANUFACTURE (1) +#define DESC_IPRODUCT (1) +#define DESC_ISERIALNUM (1) +#define DESC_INUMCONFN (1) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (DESC_BDEVCLASS == 0x0 & DESC_BDEVSUBCLASS != 0x0) +#error "DESC_BDEVSUBCLASS must be reset to zero when the DESC_BDEVCLASS is equal to zero." +#endif +#define DESC_WMAXPACKETSIZE0 (_EP0LEN) +#define DESC_STR_MAN (1 * DESC_IMANUFACTURE) +#define DESC_STR_PRD (2 * DESC_IPRODUCT) +#define DESC_STR_SER (3 * DESC_ISERIALNUM) +#define DESC_NUM_STRING (1 + 3) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_DeviceDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Device descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_DEV, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_01_DEV, // bDescriptorType 1 DEVICE Descriptor Type + DESC_H2B(DESC_BCDUSB), // bcdUSB 2 USB Specification Release Number + DESC_BDEVCLASS, // bDeviceClass 1 Class code (assigned by the USB-IF) + DESC_BDEVSUBCLASS, // bDeviceSubClass 1 Subclass code (assigned by the USB-IF) + DESC_BDEVPROTOCOL, // bDeviceProtocol 1 Protocol code (assigned by the USB-IF) + DESC_WMAXPACKETSIZE0, // wMaxPacketSize0 1 Maximum packet size for endpoint zero + DESC_H2B(DESC_IDVENDOR), // idVendor 2 Vendor ID (assigned by USB-IF) + DESC_H2B(DESC_IDPRODUCT), // idProduct 2 Product ID (assigned by manufacturer) + DESC_H2B(DESC_BCDDEVICE), // bcdDevice 2 Device release number + DESC_STR_MAN, // iManufacturer 1 Index of string descriptor (Manufacturer) + DESC_STR_PRD, // iProduct 1 Index of string descriptor (Product) + DESC_STR_SER, // iSerialNumber 1 Index of string descriptor (Serial Number) + DESC_INUMCONFN, // iNumConfigurations 1 Number of possible configuration +}; + + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Configuration descriptor setting +// Self-powered +// Bit 6 of bmAttributes +// Remote Wakeup +// Bit 5 of bmAttributes +// USB Device maximum power (mA) < 2-512:2> +#define DESC_BMATTR_SELF_POWER (0) +#define DESC_BMATTR_REMOTE_WAKEUP (0) +#define DESC_BMAXPOWER (100) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#define DESC_BMATTRIBUTES (0x80 | (DESC_BMATTR_SELF_POWER << 6) | (DESC_BMATTR_REMOTE_WAKEUP << 5)) +#define DESC_TOTAL_LEN DESC_H2B((DESC_LEN_CONFN_T + RETARGET_DLEN)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_ConfnDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Configuration descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_CONFN, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_02_CONFN, // bDescriptorType 1 CONFIGURATION Descriptor Type + DESC_TOTAL_LEN, // wTotalLength 2 Total length of data returned for this configuration + RETARGET_INF, // bNumberInterface 1 Number of interfaces supported by this configuration + 0x01, // bConfigurationValue 1 Value to use as an argument to the SetConfiguration() + 0x00, // iConfiguration 1 Index of string descriptor describing this configuration + DESC_BMATTRIBUTES, // bmAttributes 1 Configuration characteristics + // D6: Self-powered, D5: RemoteWakeup + DESC_POWER(DESC_BMAXPOWER), // bMaxPower 1 Maximum power consumption of the USB device (2 mA units) + + #ifdef RETARGET_IS_USB + #include "ht32_retarget_desc.h" + #endif + +}; + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB String Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_StringDescLANGID[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* LANGID (Index = 0) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(1), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_H2B(0x0409), // wLANGID[0] 2 LANGID code zero +}; + +#if (DESC_IMANUFACTURE == 1) +__ALIGN4 static uc8 guUSB_StringDescManufacture[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Manufacture (Index = 1) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(6), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('H'), // bString N UNICODE encoded string + DESC_CHAR('O'), + DESC_CHAR('L'), + DESC_CHAR('T'), + DESC_CHAR('E'), + DESC_CHAR('K'), +}; +#endif + +#if (DESC_IPRODUCT == 1) +__ALIGN4 static uc8 guUSB_StringDescProduct[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Product (Index = 2) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(7), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('U'), // bString N UNICODE encoded string + DESC_CHAR('S'), + DESC_CHAR('B'), + DESC_CHAR('-'), + DESC_CHAR('V'), + DESC_CHAR('C'), + DESC_CHAR('P'), +}; +#endif + + +#if (DESC_ISERIALNUM == 1) +__ALIGN4 static uc8 guUSB_StringDescSerialNum[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Serial Number (Index = 3) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(12), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('S'), // bString N UNICODE encoded string + DESC_CHAR('N'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('1'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), +}; +#endif + +uc8 *gpStringDesc[DESC_NUM_STRING] = +{ + + guUSB_StringDescLANGID, + + #if (DESC_IMANUFACTURE == 1) + guUSB_StringDescManufacture, + #else + NULL, + #endif + + #if (DESC_IPRODUCT == 1) + guUSB_StringDescProduct, + #else + NULL, + #endif + + #if (DESC_ISERIALNUM == 1) + guUSB_StringDescSerialNum + #else + NULL, + #endif + +}; + +/*********************************************************************************************************//** + * @brief USB Descriptor pointer initialization. + * @param pDesc: pointer of USBDCore_Desc_TypeDef + * @retval None + ***********************************************************************************************************/ +void USBDDesc_Init(USBDCore_Desc_TypeDef *pDesc) +{ + pDesc->pDeviceDesc = guUSB_DeviceDesc; + pDesc->pConfnDesc = guUSB_ConfnDesc; + pDesc->ppStringDesc = gpStringDesc; + pDesc->uStringDescNumber = DESC_NUM_STRING; + + return; +} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_serial.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_serial.c new file mode 100644 index 00000000000..a1f642f3937 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_serial.c @@ -0,0 +1,555 @@ +/*********************************************************************************************************//** + * @file ht32_serial.c + * @version $Rev:: 6490 $ + * @date $Date:: 2022-11-25 #$ + * @brief This file provides all the Low level serial routines for HT32. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_board.h" + +#if (_RETARGET == 1) + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup SERIAL SERIAL + * @brief Serial related functions + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Exported_Functions Serial exported functions + * @{ + */ + +#ifdef RETARGET_IS_UART + +#if (RETARGET_INT_MODE == 1) +__ALIGN4 static u8 uSerialBuffer[RETARGET_INT_BUFFER_SIZE]; +static vu32 uReadIndex; +static vu32 uWriteIndex; + +#define IS_BUFFER_FULL(LEN) (((uWriteIndex + LEN) >= RETARGET_INT_BUFFER_SIZE) ? ((uWriteIndex + LEN - RETARGET_INT_BUFFER_SIZE) == uReadIndex) : ((uWriteIndex + LEN) == uReadIndex)) +#define IS_BUFFER_EMPTY() (uReadIndex == uWriteIndex) +#define BUFFER_FREE_LEN() ((uWriteIndex >= uReadIndex) ? (RETARGET_INT_BUFFER_SIZE - uWriteIndex + uReadIndex - 1) : (uReadIndex - uWriteIndex - 1)) + +/*********************************************************************************************************//** + * @brief UART IRQ handler. + * @retval None + ************************************************************************************************************/ +void RETARGET_UART_IRQHandler(void) +{ + if (((RETARGET_USART_PORT->SR) & USART_FLAG_TXDE)) + { + if (IS_BUFFER_EMPTY()) + { + RETARGET_USART_PORT->IER &= ~USART_INT_TXDE; + } + else + { + RETARGET_USART_PORT->DR = uSerialBuffer[uReadIndex++]; + if (uReadIndex == RETARGET_INT_BUFFER_SIZE) + { + uReadIndex = 0; + } + } + } + +} +#endif + +/*********************************************************************************************************//** + * @brief Put char to USART. + * @param ch: The char put to USART. + * @retval The char put to USART. + ************************************************************************************************************/ +u32 SERIAL_PutChar(u32 ch) +{ +#if (RETARGET_INT_MODE == 1) + + while (IS_BUFFER_FULL(1)); + + uSerialBuffer[uWriteIndex++] = ch; + if (uWriteIndex == RETARGET_INT_BUFFER_SIZE) + { + uWriteIndex = 0; + } + RETARGET_USART_PORT->IER |= USART_INT_TXDE; + +#else + + RETARGET_USART_PORT->DR = (u8)ch; + while ((RETARGET_USART_PORT->SR & USART_FLAG_TXC) == RESET) + { + } + +#endif + + return ch; +} + +/*********************************************************************************************************//** + * @brief Get char from USART. + * @retval The char got from USART. + ************************************************************************************************************/ +u32 SERIAL_GetChar(void) +{ + while (USART_GetFlagStatus(RETARGET_USART_PORT, USART_FLAG_RXDR) == RESET) + { + } + return USART_ReceiveData(RETARGET_USART_PORT); +} + +#endif + + +#ifdef RETARGET_IS_USB +/* Private types -------------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_TypesDefinitions Serial private types definitions + * @{ + */ +typedef struct _VCP_LINE_CODING +{ + u32 dwDTERate; //Bit rate; + u8 bCharFormat; //Stop bits: + //0 = 1 Stop bit + //1 = 1.5 Stop bit + //2 = 2 Stop bit + u8 bParityType; //parity: + //0 = None + //1 = Odd + //2 = Even + //3 = Mark + //4 = Space + u8 bDataBits; //Number of data bits (7, 8, 9) +} USBDClass_VCP_LINE_CODING; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_Define Serial private definitions + * @{ + */ +#define CLASS_REQ_20_SET_LINE_CODING (0x20) +#define CLASS_REQ_21_GET_LINE_CODING (0x21) +#define CLASS_REQ_22_SET_CONTROL_LINE_STATE (0x22) + +#ifndef RETARGET_TXBUFFER_SIZE + #define RETARGET_TXBUFFER_SIZE (1) +#endif + +#define RETARGET_USB_MODE_BLOCK (0) +#define RETARGET_USB_MODE_NONBLOCK (1) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_Macro Serial private macros + * @{ + */ +#define IS_BUFFER_FULL(LEN) (((uWriteIndex + LEN) >= RETARGET_BUFFER_SIZE) ? ((uWriteIndex + LEN - RETARGET_BUFFER_SIZE) == uReadIndex) : ((uWriteIndex + LEN) == uReadIndex)) +#define IS_BUFFER_EMPTY() (uReadIndex == uWriteIndex) +#define BUFFER_FREE_LEN() ((uWriteIndex >= uReadIndex) ? (RETARGET_BUFFER_SIZE - uWriteIndex + uReadIndex - 1) : (uReadIndex - uWriteIndex - 1)) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +/** @defgroup SERIAL_Private_Variable Serial private variables + * @{ + */ +static USBDClass_VCP_LINE_CODING USBDClassVCPLineCoding; +__ALIGN4 static u8 uSerialBuffer[RETARGET_BUFFER_SIZE]; +static vu32 uReadIndex; +static vu32 uWriteIndex; +static vu32 uDTRState = 0; +static vu32 gIsINEmpty = TRUE; + +static u32 TxCount = 0; +__ALIGN4 static u8 TxBuffer[RETARGET_TXBUFFER_SIZE]; +/** + * @} + */ + +#if (RETARGET_RX_EPT == RETARGET_TX_EPT) + #error USB Endpoint of retarget Rx and Tx must different. Please check RETARGET_RX_EPT/RETARGET_TX_EPT "ht32_retarget_usbdconf.h". +#endif + +#if (RETARGET_CTRL_EPT == RETARGET_TX_EPT) + #error USB Endpoint of retarget Control and Tx must different. Please check RETARGET_CTRL_EPT/RETARGET_TX_EPT "ht32_retarget_usbdconf.h". +#endif + +#if (RETARGET_CTRL_EPT == RETARGET_RX_EPT) + #error USB Endpoint of retarget Control and Rx must different. Please check RETARGET_CTRL_EPT/RETARGET_RX_EPT "ht32_retarget_usbdconf.h". +#endif + +#ifdef _RERATGET1_ERR + #error Endpoint 1 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET2_ERR + #error Endpoint 2 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET3_ERR + #error Endpoint 3 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET4_ERR + #error Endpoint 4 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET5_ERR + #error Endpoint 5 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET6_ERR + #error Endpoint 6 already used by other USB class. Retarget can not overwrite it. +#endif + +#ifdef _RERATGET7_ERR + #error Endpoint 7 already used by other USB class. Retarget can not overwrite it. +#endif + +/*********************************************************************************************************//** + * @brief Put char to USB. + * @param ch: The char put to USB. + * @retval The char put to USB. + ************************************************************************************************************/ +u32 SERIAL_PutChar(u32 ch) +{ + #if (RETARGET_TXBUFFER_SIZE > 63) + #error RETARGET_TXBUFFER_SIZE shall less than 63 (define in ht32fxxxxx_conf.h). + #endif + + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_BLOCK) + while (uDTRState == 0); /* Wait until user open the virtual COM port by PC UI such as Hyper Terminal */ + #elif (RETARGET_USB_MODE == RETARGET_USB_MODE_NONBLOCK) + if (uDTRState == 0) /* Drop data if USB or terminal software is not ready */ + { + return ch; + } + #endif + + TxBuffer[TxCount++] = ch; + + if (TxCount == RETARGET_TXBUFFER_SIZE) + { + TxCount = 0; + + while (gIsINEmpty == FALSE) + { + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_NONBLOCK) + if (uDTRState == 0) + { + return ch; + } + #endif + } + + gIsINEmpty = FALSE; + USBDCore_EPTWriteINData((USBD_EPTn_Enum)RETARGET_TX_EPT, (u32 *)&TxBuffer, RETARGET_TXBUFFER_SIZE); + } + + return ch; +} + +/*********************************************************************************************************//** + * @brief Get char from USB. + * @retval The char got from USB. + ************************************************************************************************************/ +u32 SERIAL_GetChar(void) +{ + u32 value = 0; + + while (IS_BUFFER_EMPTY()); + value = uSerialBuffer[uReadIndex++]; + if (uReadIndex == RETARGET_BUFFER_SIZE) + { + uReadIndex = 0; + } + + return value; +} + +/*********************************************************************************************************//** + * @brief Flush the Tx Buffer + * @retval None + ************************************************************************************************************/ +void SERIAL_Flush(void) +{ + do + { + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_NONBLOCK) + if (uDTRState == 0) + { + return; + } + #endif + } while (USBDCore_EPTGetTransferCount((USBD_EPTn_Enum)RETARGET_TX_EPT, USBD_TCR_0)); + + gIsINEmpty = FALSE; + USBDCore_EPTWriteINData((USBD_EPTn_Enum)RETARGET_TX_EPT, (u32 *)&TxBuffer, TxCount); + TxCount = 0; +} + +#ifdef NON_USB_IN_APP +#include "ht32_retarget_desc.c" +__ALIGN4 USBDCore_TypeDef gUSBCore; +USBD_Driver_TypeDef gUSBDriver; + +/*********************************************************************************************************//** + * @brief This function handles USB interrupt. + * @retval None + ************************************************************************************************************/ +void USB_IRQHandler(void) +{ + USBDCore_IRQHandler(&gUSBCore); +} + +/*********************************************************************************************************//** + * @brief USB Class initialization. + * @param pClass: pointer of USBDCore_Class_TypeDef + * @retval None + ************************************************************************************************************/ +void USBDClass_Init(USBDCore_Class_TypeDef *pClass) +{ + pClass->CallBack_ClassRequest = SERIAL_USBDClass_Request; + pClass->CallBack_EPTn[RETARGET_RX_EPT] = SERIAL_USBDClass_RXHandler; + pClass->CallBack_EPTn[RETARGET_TX_EPT] = SERIAL_USBDClass_TXHandler; + return; +} + +#if (LIBCFG_CKCU_USB_PLL) +/*********************************************************************************************************//** + * @brief Configure USB PLL + * @retval None + ************************************************************************************************************/ +void USBPLL_Configuration(void) +{ + if ((HT_CKCU->GCCR & (1 << 11)) == 0) + { + CKCU_HSICmd(ENABLE); + } + + { /* USB PLL configuration */ + + /* !!! NOTICE !!! + Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below in this function. + */ + CKCU_PLLInitTypeDef PLLInit; + + PLLInit.ClockSource = CKCU_PLLSRC_HSI; + #if (LIBCFG_CKCU_USB_PLL_96M) + PLLInit.CFG = CKCU_USBPLL_8M_96M; + #else + PLLInit.CFG = CKCU_USBPLL_8M_48M; + #endif + PLLInit.BYPASSCmd = DISABLE; + CKCU_USBPLLInit(&PLLInit); + } + + CKCU_USBPLLCmd(ENABLE); + + while (CKCU_GetClockReadyStatus(CKCU_FLAG_USBPLLRDY) == RESET); + CKCU_USBClockConfig(CKCU_CKUSBPLL); +} +#endif + +#if (LIBCFG_PWRCU_VREG) +/*********************************************************************************************************//** + * @brief Configure USB Voltage + * @retval None + ************************************************************************************************************/ +void USBVRG_Configuration(void) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.BKP = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + /* !!! NOTICE !!! + USB LDO should be enabled (PWRCU_VREG_ENABLE) if the MCU VDD > 3.6 V. + */ + PWRCU_VREGConfig(PWRCU_VREG_BYPASS); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure USB for retarget. + * @retval None + ************************************************************************************************************/ +void SERIAL_USBDInit(void) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + CKCUClock.Bit.USBD = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + #if (LIBCFG_CKCU_USB_PLL) + USBPLL_Configuration(); + #endif + + #if (LIBCFG_PWRCU_VREG) + USBVRG_Configuration(); /* Voltage of USB setting */ + #endif + + /* !!! NOTICE !!! + Must turn on if the USB clock source is from HSI (PLL clock Source) + */ + #if (RETARGET_HSI_ATM) + CKCU_HSIAutoTrimClkConfig(CKCU_ATC_USB); + CKCU_HSIAutoTrimCmd(ENABLE); + #endif + + gUSBCore.pDriver = (u32 *)&gUSBDriver; /* Initiate memory pointer of USB driver */ + USBDDesc_Init(&gUSBCore.Device.Desc); /* Initiate memory pointer of descriptor */ + USBDClass_Init(&gUSBCore.Class); /* Initiate USB Class layer */ + USBDCore_Init(&gUSBCore); /* Initiate USB Core layer */ + NVIC_EnableIRQ(USB_IRQn); /* Enable USB device interrupt */ + USBD_DPpullupCmd(ENABLE); + + #if (RETARGET_USB_MODE == RETARGET_USB_MODE_BLOCK) + USBDCore_MainRoutine(&gUSBCore); /* USB core main routine */ + while (USBDCore_GetStatus() != USB_STATE_CONFIGURED); + #else + gUSBCore.Info.CurrentFeature.Bits.bSelfPowered = TRUE; + USBDCore_MainRoutine(&gUSBCore); /* USB core main routine */ + #endif +} +#endif + +/*********************************************************************************************************//** + * @brief USB Device Class Request for USB retarget + * @param pDev: pointer of USB Device + * @retval None + ************************************************************************************************************/ +void SERIAL_USBDClass_Request(USBDCore_Device_TypeDef *pDev) +{ + u8 USBCmd = *((u8 *)(&(pDev->Request.bRequest))); + u16 len = *((u16 *)(&(pDev->Request.wLength))); + u32 inf = pDev->Request.wIndex; + u32 uIsCmdOK = 0; + + if (inf != 11) + { + return; + } + + if (USBCmd == CLASS_REQ_22_SET_CONTROL_LINE_STATE) + { + if (len == 0) + { + uDTRState = pDev->Request.wValueL & 0x1; + pDev->Transfer.pData = 0; + pDev->Transfer.sByteLength = 0; + pDev->Transfer.Action = USB_ACTION_DATAOUT; + } + } + else + { + if (USBCmd == CLASS_REQ_20_SET_LINE_CODING) + { + pDev->Transfer.Action = USB_ACTION_DATAOUT; + uIsCmdOK = 1; + } + else if (USBCmd == CLASS_REQ_21_GET_LINE_CODING) + { + pDev->Transfer.Action = USB_ACTION_DATAIN; + uIsCmdOK = 1; + } + + if (uIsCmdOK == 1) + { + pDev->Transfer.pData = (uc8*)&USBDClassVCPLineCoding; + pDev->Transfer.sByteLength = (sizeof(USBDClassVCPLineCoding) > pDev->Request.wLength) ? (pDev->Request.wLength) : (sizeof(USBDClassVCPLineCoding)); + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Received handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None +************************************************************************************************************/ +void SERIAL_USBDClass_RXHandler(USBD_EPTn_Enum EPTn) +{ + u32 uLen; + u32 uFreeLen = BUFFER_FREE_LEN(); + u8 uTempBuffer[64]; + u32 i; + + /* Read Receive data */ + uLen = USBDCore_EPTReadOUTData(EPTn, (u32*)uTempBuffer, 64); + + if (uLen > uFreeLen) + { + uLen = uFreeLen; + } + + for (i = 0; i < uLen; i++) + { + uSerialBuffer[uWriteIndex++] = uTempBuffer[i]; + if (uWriteIndex == RETARGET_BUFFER_SIZE) + { + uWriteIndex = 0; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Tx handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None +************************************************************************************************************/ +void SERIAL_USBDClass_TXHandler(USBD_EPTn_Enum EPTn) +{ + gIsINEmpty = TRUE; + return; +} + +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_time.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_time.c new file mode 100644 index 00000000000..a84bbb61ac9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32_time.c @@ -0,0 +1,185 @@ +/*********************************************************************************************************//** + * @file ht32_time.c + * @version $Rev:: 6461 $ + * @date $Date:: 2022-11-18 #$ + * @brief The time functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_time.h" + +/* + Tick Range: 0 ~ 2^32 / HTCFG_TIME_TICKHZ (maximum tick time) + Interrupt Time: _HTCFG_TIME_OVERFLOW_VALUE / (HTCFG_TIME_TICKHZ * HTCFG_TIME_MULTIPLE) Second (not apply for BFTM) + + Example: 32-bit BFTM with 48 MHz Timer Clock + HTCFG_TIME_TICKHZ = HTCFG_TIME_CLKSRC = 48000000 + Tick Range: 0 ~ 2^32 / 48000000 = 0 ~ 89.478485 Second (maximum tick time, return to 0 every 89.478485 Second) + BFTM do not use interrupt + + Example: 16-bit SCTM with 1 us tick + HTCFG_TIME_TICKHZ = 1000000 (Hz) + HTCFG_TIME_MULTIPLE = 1 (1 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 1000000 = 0 ~ 4294 Second = 0 ~ 71.58 Minute (maximum tick time, return to 0 every 71.58 Minute) + Interrupt Time: 65536 / (1000000 * 1) = 65.536 ms (Trigger interrupt every 65.536 ms) + + Example: 16-bit SCTM with 10 us tick + HTCFG_TIME_TICKHZ = 100000 (Hz) + HTCFG_TIME_MULTIPLE = 4 (4 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 100000 = 0 ~ 42949 Second = 0 ~ 715.82 Minute = 11.93 Hour (maximum tick time, return to 0 every 11.93 Hour) + Interrupt Time: 65536 / (100000 * 4) = 163.84 ms (Trigger interrupt every 163.84 ms) + + Example: 16-bit GPTM with 1 ms tick + HTCFG_TIME_TICKHZ = 1000 (Hz) + HTCFG_TIME_MULTIPLE = 4 (4 Timer Count = 1 Tick) + Tick Range: 0 ~ 2^32 / 1000 = 0 ~ 4294967 Second = 0 ~ 49.7 Day (maximum tick time, return to 0 every 49.7 Day) + Interrupt Time: 65536 / (1000 * 4) = 16.384 Second (Trigger interrupt every 16.384 Second) +*/ + +/* Private constants ---------------------------------------------------------------------------------------*/ +#define _HTCFG_TIME_CKCU_PCLK STRCAT2(CKCU_PCLK_, HTCFG_TIME_IPN) + +#if (IS_IPN_TM(HTCFG_TIME_IPN)) +// SCTM/PWM/GPTM/MCTM +#define _HTCFG_TIME_IRQn STRCAT2(HTCFG_TIME_IPN, _IRQn) +#define _HTCFG_TIME_IRQHandler STRCAT2(HTCFG_TIME_IPN, _IRQHandler) +#define _HTCFG_TIME_CLKDIV (HTCFG_TIME_CLKSRC / HTCFG_TIME_TICKHZ / HTCFG_TIME_MULTIPLE) +#define _HTCFG_TIME_OVERFLOW_VALUE (65536) // 16-bit = 2^16 + +#if (_HTCFG_TIME_CLKDIV <= 0) + #error "_HTCFG_TIME_CLKDIV is not correct (must >= 1)!" +#endif + +#if (_HTCFG_TIME_CLKDIV > 65536) + #error "_HTCFG_TIME_CLKDIV is not correct (must <= 65536)!" +#endif + +#if ((_HTCFG_TIME_CLKDIV * HTCFG_TIME_MULTIPLE) != (HTCFG_TIME_CLKSRC / HTCFG_TIME_TICKHZ)) + #error "_HTCFG_TIME_CLKDIV is not correct (must be integer)!" +#endif +#endif + +/* Private variables ---------------------------------------------------------------------------------------*/ +#if (IS_IPN_TM(HTCFG_TIME_IPN)) +u32 gTotalTick = 0x00000000; +u8 gIsTimeInt = FALSE; +#endif + +/* Global functions ----------------------------------------------------------------------------------------*/ +/*********************************************************************************************************//** + * @brief Time Init function. + * @retval None + ***********************************************************************************************************/ +void Time_Init(void) +{ + { /* Enable peripheral clock */ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.HTCFG_TIME_IPN = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + } + + #if (LIBCFG_CKCU_NO_APB_PRESCALER == 0) + CKCU_SetPeripPrescaler(_HTCFG_TIME_CKCU_PCLK, (CKCU_APBCLKPRE_TypeDef)HTCFG_TIME_PCLK_DIV); + #endif + + #if (IS_IPN_TM(HTCFG_TIME_IPN)) + + { /* Time base configuration */ + /* !!! NOTICE !!! + Notice that the local variable (structure) did not have an initial value. + Please confirm that there are no missing members in the parameter settings below in this function. + */ + TM_TimeBaseInitTypeDef TimeBaseInit; + + TimeBaseInit.Prescaler = _HTCFG_TIME_CLKDIV - 1; + TimeBaseInit.CounterReload = _HTCFG_TIME_OVERFLOW_VALUE -1; + TimeBaseInit.RepetitionCounter = 0; + TimeBaseInit.CounterMode = TM_CNT_MODE_UP; + TimeBaseInit.PSCReloadTime = TM_PSC_RLD_IMMEDIATE; + TM_TimeBaseInit(_HTCFG_TIME_PORT, &TimeBaseInit); + + /* Clear Update Event Interrupt flag since the "TM_TimeBaseInit()" writes the UEV1G bit */ + TM_ClearFlag(_HTCFG_TIME_PORT, TM_FLAG_UEV); + } + + /* Enable Update Event interrupt */ + TM_IntConfig(_HTCFG_TIME_PORT, TM_INT_UEV, ENABLE); + NVIC_EnableIRQ(_HTCFG_TIME_IRQn); + + TM_SetCounter(_HTCFG_TIME_PORT, 0x0000); + TM_Cmd(_HTCFG_TIME_PORT, ENABLE); + + #else + + BFTM_SetCounter(_HTCFG_TIME_PORT, 0x00000000); + BFTM_EnaCmd(_HTCFG_TIME_PORT, ENABLE); + #endif +} + +/*********************************************************************************************************//** + * @brief Time delay function. + * @param uDelayTick: Delay count based on tick. + * @retval None + ***********************************************************************************************************/ +void Time_Delay(u32 uDelayTick) +{ + u32 uCurrent; + u32 uStart = Time_GetTick(); + + do + { + uCurrent = Time_GetTick(); + } while (TIME_TICKDIFF(uStart, uCurrent) < uDelayTick); +} + +#if (IS_IPN_TM(HTCFG_TIME_IPN)) +/*********************************************************************************************************//** + * @brief Gets the current time tick. + * @retval Time Tick + ***********************************************************************************************************/ +u32 Time_GetTick(void) +{ + u32 uCount = GET_CNT(); + + if (gIsTimeInt == TRUE) + { + gIsTimeInt = FALSE; + uCount = GET_CNT(); + gTotalTick += (_HTCFG_TIME_OVERFLOW_VALUE / HTCFG_TIME_MULTIPLE); + } + + return (gTotalTick + (uCount / HTCFG_TIME_MULTIPLE)); +} + +/*********************************************************************************************************//** + * @brief This function handles Timer interrupt. + * @retval None + ************************************************************************************************************/ +void _HTCFG_TIME_IRQHandler(void) +{ + TM_ClearFlag(_HTCFG_TIME_PORT, TM_INT_UEV); + + gIsTimeInt = TRUE; +} +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_adc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_adc.c new file mode 100644 index 00000000000..d244507c110 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_adc.c @@ -0,0 +1,603 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_adc.c + * @version $Rev:: 7366 $ + * @date $Date:: 2023-12-06 #$ + * @brief This file provides all the ADC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_adc.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Private_Define ADC private definitions + * @{ + */ +#define ADC_ENABLE_BIT (0x00000080) +#define ADC_SOFTWARE_RESET (0x00000040) +#define LST_SEQ_SET (0x0000001F) +#define TCR_SC_SET (0x00000001) + +#define HLST_SEQ_SET (0x0000001F) +#define HTCR_SC_SET (0x00000001) + +#define ADC_VREF_MVDDAEN (0x00000100) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions ADC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the HT_ADCn peripheral registers to their default reset values. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + if (HT_ADCn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.ADC0 = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Reset ADC. + * @param HT_ADCn: is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_Reset(HT_ADC_TypeDef* HT_ADCn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + HT_ADCn->CR |= ADC_SOFTWARE_RESET; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->CR |= ADC_ENABLE_BIT; + } + else + { + HT_ADCn->CR &= ~(ADC_ENABLE_BIT); + } +} + +/*********************************************************************************************************//** + * @brief Configure conversion mode and length of list queue for regular group. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_MODE: ADC Cyclic Conversion Mode. + * This parameter can be one of the following values: + * @arg ONE_SHOT_MODE : + * @arg CONTINUOUS_MODE : + * @arg DISCONTINUOUS_MODE : + * @param Length: must between 1 ~ 8 + * @param SubLength: must between 1 ~ 8, only valid for DISCONTINUOUS_MODE. + * @retval None + ************************************************************************************************************/ +void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CONVERSION_MODE(ADC_MODE)); + Assert_Param(IS_ADC_REGULAR_LENGTH(Length)); + #if (LIBCFG_ADC_NO_DISCON_MODE == 0) + if (ADC_MODE == DISCONTINUOUS_MODE) + { + Assert_Param(IS_ADC_REGULAR_SUB_LENGTH(SubLength)); + } + #endif + + #if (LIBCFG_ADC_NO_DISCON_MODE) + /* Config cyclic conversion mode and length of list queue for regular group */ + HT_ADCn->CR = ((u32)(Length - 1) << 8) | ADC_MODE | (HT_ADCn->CR & ADC_ENABLE_BIT); + #else + /* Config cyclic conversion mode and length of list queue and sub length for regular group */ + HT_ADCn->CR = ((u32)(SubLength - 1) << 16) | ((u32)(Length - 1) << 8) | ADC_MODE | (HT_ADCn->CR & ADC_ENABLE_BIT); + #endif +} + +/*********************************************************************************************************//** + * @brief Configure the corresponding rank in the sequencer for the regular channel + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel n selected, n must between 0 ~ m (m represent the maximum external ADC input channel). + * @arg ADC_CH_DAC0_CH0 : ADC DAC0_CH0 selected + * @arg ADC_CH_DAC0_CH1 : ADC DAC0_CH1 selected + * @arg ADC_CH_DAC1_CH0 : ADC DAC1_CH0 selected + * @arg ADC_CH_DAC1_CH1 : ADC DAC1_CH1 selected + * @arg ADC_CH_IVREF : ADC Internal VREF selected + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @arg ADC_CH_MVDDA : ADC MVDDA selected + * @param Rank: The rank in the regular group sequencer. + * This parameter must be between 0 to 7. + * @param ...: Null parameter for API compatibility. + * @retval None + ************************************************************************************************************/ +void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, ...) +{ + u32 tmpreg1, tmpreg2; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_REGULAR_RANK(Rank)); + + /* Get the old register value */ + tmpreg1 = HT_ADCn->LST[Rank >> 2]; + /* Calculate the mask to clear */ + tmpreg2 = LST_SEQ_SET << (8 * (Rank & 0x3)); + /* Clear the old SEQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_CH_n << (8 * (Rank & 0x3)); + /* Set the SEQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + HT_ADCn->LST[Rank >> 2] = tmpreg1; +} + +/*********************************************************************************************************//** + * @brief Configure the ADC trigger source for regular channels conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_TRIG_x: + * This parameter can be one of the following values: + * @arg ADC_TRIG_SOFTWARE : S/W trigger + * @arg ADC_TRIG_EXTI_n : where n can be 0 ~ 15 + * @arg ADC_TRIG_MCTMn_MTO : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_GPTMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_TRIG_BFTMn : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_MTO : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH0O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH1O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH2O : where n can be 0 ~ 1 + * @arg ADC_TRIG_PWMn_CH3O : where n can be 0 ~ 1 + * @arg ADC_TRIG_CMPn : where n can be 0 ~ 1 + * @retval None + ************************************************************************************************************/ +void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_TRIG(ADC_TRIG_x)); + + /* Config external trigger conversion source of regular group */ + #if (LIBCFG_ADC_SW_TRIGGER_ONLY == 0) + HT_ADCn->TCR = ADC_TRIG_x & 0x0000001F; + #endif + HT_ADCn->TSR = ADC_TRIG_x & (~0x0000001F); +} + +/*********************************************************************************************************//** + * @brief Configure the sampling time for the ADC input channel. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param SampleClock: must between 0 ~ 255. + * @retval None + ************************************************************************************************************/ +void ADC_SamplingTimeConfig(HT_ADC_TypeDef* HT_ADCn, u8 SampleClock) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + /* config sampling clock of ADC input channel */ + HT_ADCn->STR = SampleClock; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable software start of the regular channel conversion of the selected ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Start Conversion */ + if (NewState != DISABLE) + { + HT_ADCn->TSR |= TCR_SC_SET; + } + else + { + HT_ADCn->TSR &= ~TCR_SC_SET; + } +} + +/*********************************************************************************************************//** + * @brief Return the result of ADC regular channel conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_REGULAR_DATAn: where n can be 0 ~ 7 + * @retval The Value of data conversion. + ************************************************************************************************************/ +u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_REGULAR_DATA(ADC_REGULAR_DATAn)); + + return ((u16)HT_ADCn->DR[ADC_REGULAR_DATAn]); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC interrupts. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the ADC interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->IER |= ADC_INT_x; + } + else + { + HT_ADCn->IER &= ~ADC_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC interrupt has occurred. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + if ((HT_ADCn->ISR & ADC_INT_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Clear the ADC interrupt pending bits. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt pending bits to be cleared. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + HT_ADCn->ICLR = ADC_INT_x; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC flag has been set. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_FLAG_x: Specify the flag to check. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_SINGLE_EOC : + * @arg ADC_FLAG_SUB_GROUP_EOC : + * @arg ADC_FLAG_CYCLE_EOC : + * @arg ADC_FLAG_DATA_OVERWRITE : + * @arg ADC_FLAG_AWD_LOWER : + * @arg ADC_FLAG_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_FLAG(ADC_FLAG_x)); + + if ((HT_ADCn->IRAW & ADC_FLAG_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +#if (LIBCFG_ADC_NO_WDT == 0) +/*********************************************************************************************************//** + * @brief Enable or Disable Lower/Upper threshold warning of the analog watchdog on single/all channels. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_AWD_x: + * This parameter can be any combination of the following values: + * @arg ADC_AWD_DISABLE : + * @arg ADC_AWD_ALL_LOWER : + * @arg ADC_AWD_ALL_UPPER : + * @arg ADC_AWD_ALL_LOWER_UPPER : + * @arg ADC_AWD_SINGLE_LOWER : + * @arg ADC_AWD_SINGLE_UPPER : + * @arg ADC_AWD_SINGLE_LOWER_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_AWD(ADC_AWD_x)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFFFF8) | ADC_AWD_x; +} + +/*********************************************************************************************************//** + * @brief Configure the analog watchdog that guards single channel. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: where n must between 0 ~ m (m represent the maximum external ADC input channel). + * @retval None + ************************************************************************************************************/ +void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INPUT_CHANNEL(ADC_CH_n)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFF0FF) | ((u32)ADC_CH_n << 8); +} + +/*********************************************************************************************************//** + * @brief Configure the high and low thresholds of the analog watchdog. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param UPPER: must between 0x0000 ~ 0x0FFF + * @param LOWER: must between 0x0000 ~ 0x0FFF + * @retval None + ************************************************************************************************************/ +void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_THRESHOLD(UPPER)); + Assert_Param(IS_ADC_THRESHOLD(LOWER)); + + HT_ADCn->WTR = (UPPER << 16) | LOWER; +} +#endif + +#if (LIBCFG_PDMA) +/*********************************************************************************************************//** + * @brief Enable or Disable the specified PDMA request. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_PDMA_x: Specify the ADC PDMA request that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_PDMA_REGULAR_SINGLE : + * @arg ADC_PDMA_REGULAR_SUBGROUP : + * @arg ADC_PDMA_REGULAR_CYCLE : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_PDMA(ADC_PDMA_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->PDMAR |= ADC_PDMA_x; + } + else + { + HT_ADCn->PDMAR &= ~ADC_PDMA_x; + } +} +#endif + +#if (LIBCFG_ADC_IVREF) +/*********************************************************************************************************//** + * @brief Enable or Disable the VREF. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_VREFCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->VREFCR |= 0x00000001; + } + else + { + HT_ADCn->VREFCR &= ~(0x00000001); + } +} + +/*********************************************************************************************************//** + * @brief Configure the VREF output voltage. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_VREF_x: + * This parameter can be one of the following value: + * @arg ADC_VREF_1V215 : + * @arg ADC_VREF_2V0 : + * @arg ADC_VREF_2V5 : + * @arg ADC_VREF_2V7 : + * For the 5 V version (LIBCFG_ADC_IVREF_LEVEL_TYPE2): + * @arg ADC_VREF_2V5 : + * @arg ADC_VREF_3V0 : + * @arg ADC_VREF_4V0 : + * @arg ADC_VREF_4V5 : + * @retval None + ************************************************************************************************************/ +void ADC_VREFConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_VREF_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_VREF_SEL(ADC_VREF_x)); + + HT_ADCn->VREFCR = (HT_ADCn->VREFCR & ~(3ul << 4)) | (ADC_VREF_x); +} +#endif + +#if (LIBCFG_ADC_VREFBUF) +/*********************************************************************************************************//** + * @brief Enable or Disable the VREF output. When enable, the VREF provides a stable voltage output to the ADVREFP pin (ADC reference positive voltage). + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_VREFOutputCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* !!! NOTICE !!! + The ADCREFP pin should not be connected to an external voltage when the VREF output is enabled. + */ + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->VREFCR |= 0x00000002; + } + else + { + HT_ADCn->VREFCR &= ~(0x00000002); + } +} +#endif + +#if (LIBCFG_ADC_MVDDA) +/*********************************************************************************************************//** + * @brief Enable or Disable the power of MVDDA (VDDA/2) + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_MVDDACmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->VREFCR |= ADC_VREF_MVDDAEN; + } + else + { + HT_ADCn->VREFCR &= ~(ADC_VREF_MVDDAEN); + } +} + +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_aes.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_aes.c new file mode 100644 index 00000000000..133889a2583 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_aes.c @@ -0,0 +1,552 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_aes.c + * @version $Rev:: 7390 $ + * @date $Date:: 2023-12-12 #$ + * @brief This file provides all the ADC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_aes.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup AES AES + * @brief AES driver modules + * @{ + */ + + +/* Global variables ----------------------------------------------------------------------------------------*/ +u32 *gpu32OutputBuff; +u32 gu32OutputIndex = 0; + +u32 *gpu32InputBuff; +u32 gu32InputSize = 0; +u32 gu32InputIndex = 0; + +/* Private functions ---------------------------------------------------------------------------------------*/ +static void _AES_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup AES_Exported_Functions AES exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the AES peripheral registers to their default reset values. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AES_DeInit(HT_AES_TypeDef* HT_AESn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + if (HT_AESn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.AES = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Flush the FIFO. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AES_FIFOFlush(HT_AES_TypeDef* HT_AESn) +{ + AES_Cmd(HT_AESn, DISABLE); + HT_AESn->CR |= AES_FLUSH_ENABLE; + AES_Cmd(HT_AESn, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified AES. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void AES_Cmd(HT_AES_TypeDef* HT_AESn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_AESn->CR |= AES_ENABLE; + } + else + { + HT_AESn->CR &= ~AES_ENABLE; + } +} + +/*********************************************************************************************************//** + * @brief Start the AES key. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AES_StartKey(HT_AES_TypeDef* HT_AESn) +{ + HT_AESn->CR |= (1 << 4); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where AES is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void _AES_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_KEY_SIZE(AES_InitStruct->AES_KeySize)); + Assert_Param(IS_AES_DIR(AES_InitStruct->AES_Dir)); + Assert_Param(IS_AES_MODE(AES_InitStruct->AES_Mode)); + Assert_Param(IS_AES_SWAP(AES_InitStruct->AES_Swap)); + + HT_AESn->CR = (HT_AESn->CR & 0xFFFFFE81) | AES_InitStruct->AES_KeySize | + AES_InitStruct->AES_Dir | AES_InitStruct->AES_Mode | + AES_InitStruct->AES_Swap; + + AES_Cmd(HT_AESn, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral on ECB mode according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where AES is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void AES_ECB_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + AES_InitStruct->AES_Mode = AES_MODE_ECB; + _AES_Init(HT_AESn, AES_InitStruct); + + AES_IntConfig(HT_AESn, AES_IER_OFINTEN, ENABLE); + NVIC_EnableIRQ(AES_IRQn); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral on CBC mode according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where AES is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void AES_CBC_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + AES_InitStruct->AES_Mode = AES_MODE_CBC; + _AES_Init(HT_AESn, AES_InitStruct); + + AES_IntConfig(HT_AESn, AES_IER_OFINTEN, ENABLE); + NVIC_EnableIRQ(AES_IRQn); +} + +/*********************************************************************************************************//** + * @brief Initialize the AES peripheral on CTR mode according to the specified parameters in the AES_InitStruct. + * @param HT_AESn: where HT_AESn is the selected AES peripheral. + * @param AES_InitStruct: pointer to a AES_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void AES_CTR_Init(HT_AES_TypeDef* HT_AESn, AES_InitTypeDef* AES_InitStruct) +{ + AES_InitStruct->AES_Mode = AES_MODE_CTR; + _AES_Init(HT_AESn, AES_InitStruct); + + AES_IntConfig(HT_AESn, AES_IER_OFINTEN, ENABLE); + NVIC_EnableIRQ(AES_IRQn); +} + +/*********************************************************************************************************//** + * @brief Check whether the specified AES status has been set. + * @param HT_AESn: where HT_AESn is the selected AES peripheral. + * @param AES_SR_x: specify the flag to be check. + * This parameter can be one of the following values: + * @arg AES_SR_IFEMPTY : AES Input FIFO is Empty + * @arg AES_SR_IFNFULL : AES Input FIFO is not Full + * @arg AES_SR_OFNEMPTY : AES Output FIFO is not Empty + * @arg AES_SR_OFFULL : AES Output FIFO is Full + * @arg AES_SR_BUSY : AES is busy when AES is in encrypt/decrypt action and key expansion + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus AES_GetStatus(HT_AES_TypeDef* HT_AESn, u32 AES_SR_x) +{ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_STATUS(AES_SR_x)); + + if ((HT_AESn->SR & AES_SR_x) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the AES PDMA interface. + * @param HT_AESn: where HT_AESn is the selected HT_AESn peripheral. + * @param AES_PDMA_xFDMAEN: specify the AES FIFO DMA to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg AES_PDMA_IFDMAEN : input FIFO PDMA + * @arg AES_PDMA_OFDMAEN : Output FIFO PDMA + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void AES_PDMACmd(HT_AES_TypeDef* HT_AESn, u32 AES_PDMA_xFDMAEN, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_AESn->PDMAR |= AES_PDMA_xFDMAEN; + } + else + { + HT_AESn->PDMAR &= ~AES_PDMA_xFDMAEN; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified AES interrupt has occurred. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param AES_INTSR_x: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * @arg AES_INTSR_IFINT : + * @arg AES_INTSR_OFINT : + * @return SET or RESET + ************************************************************************************************************/ +FlagStatus AES_GetIntStatus(HT_AES_TypeDef* HT_AESn, u32 AES_INTSR_x) +{ + FlagStatus Status; + u32 aes_isr = HT_AESn->ISR; + u32 aes_ier = HT_AESn->IER; + + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_INTSR(AES_INTSR_x)); + + Status = (FlagStatus)(aes_isr & aes_ier); + if ((Status & AES_INTSR_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified AES interrupts. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param AES_IER_x: Specify the AES interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg AES_IER_IFINTEN : + * @arg AES_IER_OFINTEN : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void AES_IntConfig(HT_AES_TypeDef* HT_AESn, u32 AES_IER_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_AES(HT_AESn)); + Assert_Param(IS_AES_IER(AES_IER_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_AESn->IER |= AES_IER_x; + } + else + { + HT_AESn->IER &= ~AES_IER_x; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified AES Input data. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param AES_Data: Data input + * @retval None + ************************************************************************************************************/ +void AES_SetInputData(HT_AES_TypeDef* HT_AESn, uc32 AES_Data) +{ + Assert_Param(IS_AES(HT_AESn)); + #if (LIBCFG_AES_SWAP) + HT_AESn->DINR = __REV(AES_Data); + #else + HT_AESn->DINR = AES_Data; + #endif +} + +/*********************************************************************************************************//** + * @brief Get the specified AES output data. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @retval Output Data + ************************************************************************************************************/ +u32 AES_GetOutputData(HT_AES_TypeDef* HT_AESn) +{ + Assert_Param(IS_AES(HT_AESn)); + #if (LIBCFG_AES_SWAP) + return __REV(HT_AESn->DOUTR); + #else + return HT_AESn->DOUTR; + #endif +} + +/*********************************************************************************************************//** + * @brief Set the specified AES key table. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param Key: Key table + * @param keySize: Key table's size + * @retval None + ************************************************************************************************************/ +void AES_SetKeyTable(HT_AES_TypeDef* HT_AESn, u32 *Key, u32 keySize) +{ + u32 i; + u32 uCRTemp = HT_AESn->CR & (~(0x00000060UL)); + if (keySize == 128/8) + { + uCRTemp |= AES_KEYSIZE_128B; + } + #if (LIBCFG_AES_KEYSIZE_256B) + else if (keySize == 192/8) + { + uCRTemp |= AES_KEYSIZE_192B; + } + else if (keySize == 256/8) + { + uCRTemp |= AES_KEYSIZE_256B; + } + #endif + else + { + return; + } + HT_AESn->CR = uCRTemp; + + for (i = 0; i < keySize; i += 4) + { + #if (LIBCFG_AES_SWAP) + HT_AESn->KEYR[i >> 2] = __REV(*&Key[i]); + #else + HT_AESn->KEYR[i >> 2] = *&Key[i]; + #endif + } + + AES_StartKey(HT_AES); +} + +/*********************************************************************************************************//** + * @brief Set the specified AES Vector table. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @param Vector: + * @retval None + ************************************************************************************************************/ +void AES_SetVectorTable(HT_AES_TypeDef* HT_AESn, u32 *Vector) +{ + int i; + Assert_Param(IS_AES(HT_AESn)); + + for (i = 0; i < 16; i += 4) + { + #if (LIBCFG_AES_SWAP) + HT_AESn->IVR[i >> 2] = __REV(*&Vector[i]); + #else + HT_AESn->IVR[i >> 2] = *&Vector[i]; + #endif + } +} + +/*********************************************************************************************************//** + * @brief AES Crypt Data + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param dir: Crypt Data's direction + * @param iv: initial vector table + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus _AES_CryptData(HT_AES_TypeDef* HT_AESn, + AES_DIR_Enum dir, + u32 *iv, + u32 length, + u32 *inputData, + u32 *outputData) +{ + /*AES Data blocks 16 byte */ + if ((length % 16) != 0) + { + /* Data size can not be divisible by 16. */ + return ERROR; + } + + /*Set inital Vector */ + if (iv != NULL) + { + AES_SetVectorTable(HT_AESn, iv); + } + + /*FIFO Flush */ + AES_FIFOFlush(HT_AES); + + /*Set direction */ + HT_AESn->CR = (HT_AESn->CR & 0xFFFFFFFD) | dir; + + /*Create input/output data */ + gpu32InputBuff = inputData; + gpu32OutputBuff = outputData; + + /*Init Index */ + gu32OutputIndex = 0; + gu32InputSize = length/4; + + /*Set input data */ + AES_IntConfig(HT_AES, AES_IER_IFINTEN, ENABLE); + + /*Waitting for conversion */ + while (AES_GetStatus(HT_AES, AES_SR_OFNEMPTY)); + return SUCCESS; +} + +#if 0 +/*********************************************************************************************************//** + * @brief AES Crypt Data on ECB mode + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param dir: Crypt Data's direction + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus AES_ECB_CryptData(HT_AES_TypeDef* HT_AESn, + AES_DIR_Enum dir, + u32 length, + u32 *inputData, + u32 *outputData) +{ + return _AES_CryptData(HT_AESn, + dir, + NULL, + length, + inputData, + outputData); +} + +/*********************************************************************************************************//** + * @brief AES Crypt Data on CBC mode + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param dir: Crypt Data's direction + * @param iv: initial vector table + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus AES_CBC_CryptData(HT_AES_TypeDef* HT_AESn, + AES_DIR_Enum dir, + u32 *iv, + u32 length, + u32 *inputData, + u32 *outputData) +{ + return _AES_CryptData(HT_AESn, + dir, + iv, + length, + inputData, + outputData); +} + +/*********************************************************************************************************//** + * @brief AES Crypt Data on CTR mode + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals + * @param iv: initial vector table + * @param length: data size + * @param inputData: InputData + * @param outputData: Output Data + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus AES_CTR_CryptData(HT_AES_TypeDef* HT_AESn, + u32 *iv, + u32 length, + u32 *inputData, + u32 *outputData) +{ + return _AES_CryptData(HT_AESn, + AES_DIR_ENCRYPT, + iv, + length, + inputData, + outputData); +} +#endif + +/*********************************************************************************************************//** + * @brief This function handles AES Core interrupt. + * @param HT_AESn: where HT_AESn is the selected AES from the AES peripherals. + * @retval None + ************************************************************************************************************/ +void AESCore_IRQHandler(HT_AES_TypeDef* HT_AESn) +{ + if (AES_GetIntStatus(HT_AES, AES_INTSR_OFINT)) + { + gpu32OutputBuff[gu32OutputIndex++] = AES_GetOutputData(HT_AES); + } + if (AES_GetIntStatus(HT_AES, AES_INTSR_IFINT)) + { + if (gu32InputIndex < gu32InputSize) + { + AES_SetInputData(HT_AES, gpu32InputBuff[gu32InputIndex]); + gu32InputIndex++; + } + else + { + AES_IntConfig(HT_AES, AES_IER_IFINTEN, DISABLE); + gu32InputIndex = 0; + } + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_bftm.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_bftm.c new file mode 100644 index 00000000000..db0ad91c0f2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_bftm.c @@ -0,0 +1,242 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_bftm.c + * @version $Rev:: 6393 $ + * @date $Date:: 2022-10-27 #$ + * @brief This file provides all the BFTM firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_bftm.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup BFTM BFTM + * @brief BFTM driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup BFTM_Exported_Functions BFTM exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the specified BFTM registers to their default values. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval None + ************************************************************************************************************/ +void BFTM_DeInit(HT_BFTM_TypeDef* HT_BFTMn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + if (HT_BFTMn == HT_BFTM0) + { + RSTCUReset.Bit.BFTM0 = 1; + } + #if (LIBCFG_BFTM1) + else if (HT_BFTMn == HT_BFTM1) + { + RSTCUReset.Bit.BFTM1 = 1; + } + #endif + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void BFTM_EnaCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_BFTMn->CR |= (1UL << 2); + } + else + { + HT_BFTMn->CR &= ~(1UL << 2); + } +} + +/*********************************************************************************************************//** + * @brief Configure the CMP register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param uCompare: Specify a value to the CMP register. + * @retval None + ************************************************************************************************************/ +void BFTM_SetCompare(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCompare) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + HT_BFTMn->CMP = uCompare; +} + +/*********************************************************************************************************//** + * @brief Get the CMP register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval The value of the CMP register + ************************************************************************************************************/ +u32 BFTM_GetCompare(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + return HT_BFTMn->CMP; +} + +/*********************************************************************************************************//** + * @brief Set the CNTR register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param uCounter: Specify a new value to the CNTR register. + * @retval None + ************************************************************************************************************/ +void BFTM_SetCounter(HT_BFTM_TypeDef* HT_BFTMn, BFTM_DataTypeDef uCounter) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + HT_BFTMn->CNTR = uCounter; +} + +/*********************************************************************************************************//** + * @brief Get the CNTR register value of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval The value of the CNTR register + ************************************************************************************************************/ +u32 BFTM_GetCounter(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + return HT_BFTMn->CNTR; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the one shot mode of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void BFTM_OneShotModeCmd(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_BFTMn->CR |= (1UL << 1); + } + else + { + HT_BFTMn->CR &= ~(1UL << 1); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified BFTM interrupt. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void BFTM_IntConfig(HT_BFTM_TypeDef* HT_BFTMn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_BFTMn->CR |= BFTM_INT_MATCH; + } + else + { + HT_BFTMn->CR &= ~BFTM_INT_MATCH; + } +} + +/*********************************************************************************************************//** + * @brief Get the flag status of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus BFTM_GetFlagStatus(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + if (HT_BFTMn->SR & BFTM_FLAG_MATCH) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the interrupt flag of the specified BFTM. + * @param HT_BFTMn: where the HT_BFTMn is the selected BFTM from the BFTM peripherals. + * @retval None + ************************************************************************************************************/ +void BFTM_ClearFlag(HT_BFTM_TypeDef* HT_BFTMn) +{ + /* Check the parameters */ + Assert_Param(IS_BFTM(HT_BFTMn)); + + HT_BFTMn->SR &= ~BFTM_FLAG_MATCH; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_can.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_can.c new file mode 100644 index 00000000000..22fca5ab022 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_can.c @@ -0,0 +1,1029 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_can.c + * @version $Rev:: 7187 $ + * @date $Date:: 2023-08-31 #$ + * @brief This file provides all the CAN firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_can.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CAN CAN + * @brief CAN driver modules + * @{ + */ + +/* Private types -------------------------------------------------------------------------------------------*/ +typedef enum +{ + IF0_NUM = 0, + IF1_NUM, + IF_TOTAL_NUM +} CANIF_NUMBER_Enum; + + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static CANIF_NUMBER_Enum GetFreeIF(HT_CAN_TypeDef *CANx); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Functions CAN exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the specified CAN registers to their default values. + * @param CANx: where the CANx is the selected CAN from the CAN peripherals. + * @retval None + ************************************************************************************************************/ +void CAN_DeInit(HT_CAN_TypeDef* CANx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + /* Check the parameters */ + Assert_Param(IS_CAN(CANx)); + + if (CANx == HT_CAN0) + { + RSTCUReset.Bit.CAN0 = 1; + } + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief This function is used to set CAN to enter initialization mode and enable access bit timing + * register.After bit timing configuration ready, user must call CAN_LeaveInitMode() + * to leave initialization mode and lock bit timing register to let new configuration + * take effect. + * @param CANx: The pointer to CAN module base address. + * @retval None + ***********************************************************************************************************/ +void CAN_EnterInitMode(HT_CAN_TypeDef *CANx) +{ + CANx->CR |= CAN_CR_INIT_Msk; + CANx->CR |= CAN_CR_CCE_Msk; +} + +/*********************************************************************************************************//** + * @brief Leave initialization mode + * @param CANx: The pointer to CAN module base address. + * @retval None + ***********************************************************************************************************/ +void CAN_LeaveInitMode(HT_CAN_TypeDef *CANx) +{ + CANx->CR &= (~(CAN_CR_INIT_Msk | CAN_CR_CCE_Msk)); + + while(CANx->CR & CAN_CR_INIT_Msk); /* Check INIT bit is released */ +} + +/*********************************************************************************************************//** + * @brief This function is used to Wait message into message buffer in basic mode. Please notice the + * function is polling NEWDAT bit of MCR register by while loop and it is used in basic mode. + * @param CANx: The pointer to CAN module base address. + * @retval None + ***********************************************************************************************************/ +void CAN_WaitMsg(HT_CAN_TypeDef *CANx) +{ + CANx->SR = 0x0; /* clr status */ + + while(1) + { + if(CANx->IF1.MCR & CAN_IF_MCR_NEWDAT_Msk) /* check new data */ + { + /*DEBUG_PRINTF("New Data IN\n");*/ + break; + } + if(CANx->SR & CAN_SR_RXOK_Msk) + { + /*DEBUG_PRINTF("Rx OK\n");*/ + } + if(CANx->SR & CAN_SR_LEC_Msk) + { + /*DEBUG_PRINTF("Error\n");*/ + } + } +} + +/*********************************************************************************************************//** + * @brief Get current bit rate + * @param CANx: The pointer to CAN module base address. + * @retval Current Bit-Rate (kilo bit per second) + ***********************************************************************************************************/ +u32 CAN_GetCANBitRate(HT_CAN_TypeDef *CANx) +{ + u32 wTseg1, wTseg2; + u32 wBpr; + + wTseg1 = (CANx->BTR & CAN_BTR_TSEG0_Msk) >> CAN_BTR_TSEG0_Pos; + wTseg2 = (CANx->BTR & CAN_BTR_TSEG1_Msk) >> CAN_BTR_TSEG1_Pos; + wBpr = CANx->BTR & CAN_BTR_BRP_Msk; + wBpr |= CANx->BRPER << 6; + + return (SystemCoreClock / (wBpr + 1) / (wTseg1 + wTseg2 + 3)); +} + +/**********************************************************************************************************//** + * @brief Switch the CAN into test mode. + * @param CANx: The pointer to CAN module base address. + * @param u8TestMask Specifies the configuration in test modes + * @arg CAN_TEST_BASIC_Msk : Enable basic mode of test mode + * @arg CAN_TEST_SILENT_Msk : Enable silent mode of test mode + * @arg CAN_TEST_LBACK_Msk : Enable Loop Back Mode of test mode + * @arg CAN_TEST_TX0_Msk/CAN_TEST_TX1_Msk: Control CAN_TX pin bit field + * @retval None + ***********************************************************************************************************/ +void CAN_EnterTestMode(HT_CAN_TypeDef *CANx, u32 u8TestMask) +{ + CANx->CR |= CAN_CR_TEST_Msk; + CANx->TR = u8TestMask; +} + +/*********************************************************************************************************//** + * @brief Leave the test mode + * @param CANx: The pointer to CAN module base address. + * @retval None + ***********************************************************************************************************/ +void CAN_LeaveTestMode(HT_CAN_TypeDef *CANx) +{ + CANx->CR |= CAN_CR_TEST_Msk; + CANx->TR &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk); + CANx->CR &= (~CAN_CR_TEST_Msk); +} + +/*********************************************************************************************************//** + * @brief Get the waiting status of a received message. + * @param CANx: The pointer to CAN module base address. + * @param MsgObj: Specifies the Message object number, from 0 to 31. 0 No message object has new data. + ***********************************************************************************************************/ +u32 CAN_IsNewDataReceived(HT_CAN_TypeDef *CANx, u32 MsgObj) +{ + MsgObj--; + return (MsgObj < 16 ? CANx->NDR0 & (1 << MsgObj) : CANx->NDR1 & (1 << (MsgObj - 16))); +} + +/*********************************************************************************************************//** + * @brief The function is used to Send CAN message in BASIC mode of test mode. Before call the API, + * the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter + * basic mode of test mode. Please notice IF0 Registers used as Tx Buffer in basic mode. + * @param CANx: The pointer to CAN module base address. + * @param pCanMsg: Pointer to the message structure containing data to transmit. + * @retval TRUE: Transmission OK, FALSE: Check busy flag of interface 0 is timeout + ***********************************************************************************************************/ +s32 CAN_BasicSendMsg(HT_CAN_TypeDef *CANx, STR_CANMSG_T_TypeDef* pCanMsg) +{ + u32 i = 0; + while(CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk); + + CANx->SR &= (~CAN_SR_TXOK_Msk); + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + CANx->IF0.ARB0 = 0; + CANx->IF0.ARB1 = (((pCanMsg->Id) & 0x7FF) << 2) ; + } + else + { + /* extended ID*/ + CANx->IF0.ARB0 = (pCanMsg->Id) & 0xFFFF; + CANx->IF0.ARB1 = ((pCanMsg->Id) & 0x1FFF0000) >> 16 | CAN_IF_ARB1_XTD_Msk; + } + + if(pCanMsg->FrameType) + CANx->IF0.ARB1 |= CAN_IF_ARB1_DIR_Msk; + else + CANx->IF0.ARB1 &= (~CAN_IF_ARB1_DIR_Msk); + + CANx->IF0.MCR = (CANx->IF0.MCR & (~CAN_IF_MCR_DLC_Msk)) | pCanMsg->DLC; + CANx->IF0.DA0R = ((u16)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]; + CANx->IF0.DA1R = ((u16)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]; + CANx->IF0.DB0R = ((u16)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]; + CANx->IF0.DB1R = ((u16)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]; + + /* request transmission*/ + CANx->IF0.CREQ &= (~CAN_IF_CREQ_BUSY_Msk); + if(CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk) + { + return FALSE; + } + + CANx->IF0.CREQ |= CAN_IF_CREQ_BUSY_Msk; /* Sending */ + + for(i = 0; i < 0xFFFFF; i++) + { + if((CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) + break; + } + + if(i >= 0xFFFFFFF) + { + return FALSE; + } + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Get a message information in BASIC mode. + * @param CANx: The pointer to CAN module base address. + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @retval FALSE: No any message received, TRUE: Receive a message success. + ***********************************************************************************************************/ +s32 CAN_BasicReceiveMsg(HT_CAN_TypeDef *CANx, STR_CANMSG_T_TypeDef* pCanMsg) +{ + if((CANx->IF1.MCR & CAN_IF_MCR_NEWDAT_Msk) == 0) /* In basic mode, receive data always save in IF1 */ + { + return FALSE; + } + + CANx->SR &= (~CAN_SR_RXOK_Msk); + + CANx->IF1.CMASK = CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + if((CANx->IF1.MASK1 & CAN_IF_ARB1_XTD_Msk) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CANx->IF1.MASK1 >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = (CANx->IF1.ARB1 & 0x1FFF) << 16; + pCanMsg->Id |= (u32)CANx->IF1.ARB0; + } + + pCanMsg->FrameType = !((CANx->IF1.ARB1 & CAN_IF_ARB1_DIR_Msk) >> CAN_IF_ARB1_DIR_Pos); + + pCanMsg->DLC = CANx->IF1.MCR & CAN_IF_MCR_DLC_Msk; + pCanMsg->Data[0] = CANx->IF1.DA0R & CAN_IF_DAT_A0_DATA0_Msk; + pCanMsg->Data[1] = (CANx->IF1.DA0R & CAN_IF_DAT_A0_DATA1_Msk) >> CAN_IF_DAT_A0_DATA1_Pos; + pCanMsg->Data[2] = CANx->IF1.DA1R & CAN_IF_DAT_A1_DATA2_Msk; + pCanMsg->Data[3] = (CANx->IF1.DA1R & CAN_IF_DAT_A1_DATA3_Msk) >> CAN_IF_DAT_A1_DATA3_Pos; + pCanMsg->Data[4] = CANx->IF1.DB0R & CAN_IF_DAT_B0_DATA4_Msk; + pCanMsg->Data[5] = (CANx->IF1.DB0R & CAN_IF_DAT_B0_DATA5_Msk) >> CAN_IF_DAT_B0_DATA5_Pos; + pCanMsg->Data[6] = CANx->IF1.DB1R & CAN_IF_DAT_B1_DATA6_Msk; + pCanMsg->Data[7] = (CANx->IF1.DB1R & CAN_IF_DAT_B1_DATA7_Msk) >> CAN_IF_DAT_B1_DATA7_Pos; + + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Set Rx message object + * @param CANx: The pointer to CAN module base address. + * @param MsgObj: Specifies the Message object number, from 0 to 31. + * @arg CAN_STD_ID (standard ID, 11-bit) + * @arg CAN_EXT_ID (extended ID, 29-bit) + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @retval TRUE: SUCCESS, FALSE: No useful interface. + ***********************************************************************************************************/ +s32 CAN_SetRxMsgObj(HT_CAN_TypeDef *CANx, u32 MsgObj, STR_CANMSG_R_TypeDef* pCanMsg) +{ + u32 u8MsgIfNum = 0; + + if((u8MsgIfNum = GetFreeIF(CANx)) == 2) /* Check Free Interface for configure */ + { + return FALSE; + } + + if (u8MsgIfNum == 1) + { + /* Command Setting */ + CANx->IF1.CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(pCanMsg->IdType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ + { + CANx->IF1.ARB0 = 0; + CANx->IF1.ARB1 = CAN_IF_ARB1_MSGVAL_Msk | (pCanMsg->Id & 0x7FF) << 2; + CANx->IF1.MASK0 = pCanMsg->MASK0; + CANx->IF1.MASK1 = pCanMsg->MASK1; + } + else + { + CANx->IF1.ARB0 = pCanMsg->Id & 0xFFFF; + CANx->IF1.ARB1 = CAN_IF_ARB1_MSGVAL_Msk | CAN_IF_ARB1_XTD_Msk | (pCanMsg->Id & 0x1FFF0000) >> 16; + } + + CANx->IF1.MCR |= CAN_IF_MCR_RXIE_Msk | pCanMsg->MCR ; + + if(pCanMsg->UMASK) + { + CANx->IF1.MCR |= CAN_IF_MCR_UMASK_Msk; + CANx->IF1.MASK0 = pCanMsg->MASK0; + CANx->IF1.MASK1 = pCanMsg->MASK1; + } + + if(pCanMsg->RMTEN) + CANx->IF1.MCR |= CAN_IF_MCR_RMTEN_Msk; + else + CANx->IF1.MCR &= (~CAN_IF_MCR_RMTEN_Msk); + + if(pCanMsg->EOB) + CANx->IF1.MCR |= CAN_IF_MCR_EOB_Msk; + else + CANx->IF1.MCR &= (~CAN_IF_MCR_EOB_Msk); + + CANx->IF1.MCR &= (~CAN_IF_MCR_INTPND_Msk); + CANx->IF1.MCR &= (~CAN_IF_MCR_NEWDAT_Msk); + CANx->IF1.DA0R = 0; + CANx->IF1.DA1R = 0; + CANx->IF1.DB0R = 0; + CANx->IF1.DB1R = 0; + CANx->IF1.CREQ = MsgObj+1; + } + else + { + /* Command Setting */ + CANx->IF0.CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(pCanMsg->IdType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ + { + CANx->IF0.ARB0 = 0; + CANx->IF0.ARB1 = CAN_IF_ARB1_MSGVAL_Msk | (pCanMsg->Id & 0x7FF) << 2; + CANx->IF0.MASK0 = pCanMsg->MASK0; + CANx->IF0.MASK1 = pCanMsg->MASK1; + } + else + { + CANx->IF0.ARB0 = pCanMsg->Id & 0xFFFF; + CANx->IF0.ARB1 = CAN_IF_ARB1_MSGVAL_Msk | CAN_IF_ARB1_XTD_Msk | (pCanMsg->Id & 0x1FFF0000) >> 16; + } + + CANx->IF0.MCR |= CAN_IF_MCR_RXIE_Msk | pCanMsg->MCR ; + + if(pCanMsg->UMASK) + { + CANx->IF0.MCR |= CAN_IF_MCR_UMASK_Msk; + CANx->IF0.MASK0 = pCanMsg->MASK0; + CANx->IF0.MASK1 = pCanMsg->MASK1; + } + + if(pCanMsg->RMTEN) + CANx->IF0.MCR |= CAN_IF_MCR_RMTEN_Msk; + else + CANx->IF0.MCR &= (~CAN_IF_MCR_RMTEN_Msk); + + if(pCanMsg->EOB) + CANx->IF0.MCR |= CAN_IF_MCR_EOB_Msk; + else + CANx->IF0.MCR &= (~CAN_IF_MCR_EOB_Msk); + + CANx->IF0.MCR &= (~CAN_IF_MCR_INTPND_Msk); + CANx->IF0.MCR &= (~CAN_IF_MCR_NEWDAT_Msk); + CANx->IF0.DA0R = 0; + CANx->IF0.DA1R = 0; + CANx->IF0.DB0R = 0; + CANx->IF0.DB1R = 0; + CANx->IF0.CREQ = MsgObj+1; + } + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Gets the message + * @param CANx: The pointer to CAN module base address. + * @param MsgObj: Specifies the Message object number, from 0 to 31. + * @param Release: Specifies the message release indicator. + * @arg TRUE : the message object is released when getting the data. + * @arg FALSE: the message object is not released. + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @retval TRUE Success, FALSE No any message received + ***********************************************************************************************************/ +s32 CAN_ReadMsgObj(HT_CAN_TypeDef *CANx, u32 MsgObj, u32 Release, STR_CANMSG_T_TypeDef* pCanMsg) +{ + u32 u8MsgIfNum = 0; + + if(!CAN_IsNewDataReceived(CANx, MsgObj)) + { + return FALSE; + } + + if((u8MsgIfNum = GetFreeIF(CANx)) == 2) /* Check Free Interface for configure */ + { + return FALSE; + } + + CANx->SR &= (~CAN_SR_RXOK_Msk); + + if (u8MsgIfNum == 1) + { + /* read the message contents*/ + CANx->IF1.CMASK = CAN_IF_CMASK_MASK_Msk + | CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_CLRINTPND_Msk + | (Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0) + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + CANx->IF1.CREQ = MsgObj; + + while(CANx->IF1.CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + + if((CANx->IF1.ARB1 & CAN_IF_ARB1_XTD_Msk) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CANx->IF1.ARB1 & CAN_IF_ARB1_ID_Msk) >> 2; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = (CANx->IF1.ARB1 & 0x1FFF) << 16 ; + pCanMsg->Id |= CANx->IF1.ARB0; + } + pCanMsg->MCR = CANx->IF1.MCR; + pCanMsg->DLC = CANx->IF1.MCR & CAN_IF_MCR_DLC_Msk; + pCanMsg->EOB = CANx->IF1.MCR & CAN_IF_MCR_EOB_Msk; + pCanMsg->Data[0] = CANx->IF1.DA0R & CAN_IF_DAT_A0_DATA0_Msk; + pCanMsg->Data[1] = (CANx->IF1.DA0R & CAN_IF_DAT_A0_DATA1_Msk) >> CAN_IF_DAT_A0_DATA1_Pos; + pCanMsg->Data[2] = CANx->IF1.DA1R & CAN_IF_DAT_A1_DATA2_Msk; + pCanMsg->Data[3] = (CANx->IF1.DA1R & CAN_IF_DAT_A1_DATA3_Msk) >> CAN_IF_DAT_A1_DATA3_Pos; + pCanMsg->Data[4] = CANx->IF1.DB0R & CAN_IF_DAT_B0_DATA4_Msk; + pCanMsg->Data[5] = (CANx->IF1.DB0R & CAN_IF_DAT_B0_DATA5_Msk) >> CAN_IF_DAT_B0_DATA5_Pos; + pCanMsg->Data[6] = CANx->IF1.DB1R & CAN_IF_DAT_B1_DATA6_Msk; + pCanMsg->Data[7] = (CANx->IF1.DB1R & CAN_IF_DAT_B1_DATA7_Msk) >> CAN_IF_DAT_B1_DATA7_Pos; + } + else + { + /* read the message contents*/ + CANx->IF0.CMASK = CAN_IF_CMASK_MASK_Msk + | CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_CLRINTPND_Msk + | (Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0) + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + CANx->IF0.CREQ = MsgObj; + + while(CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + + if((CANx->IF0.ARB1 & CAN_IF_ARB1_XTD_Msk) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CANx->IF0.ARB1 & CAN_IF_ARB1_ID_Msk) >> 2; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = (CANx->IF0.ARB1 & 0x1FFF) << 16; + pCanMsg->Id |= CANx->IF0.ARB0; + } + + pCanMsg->MCR = CANx->IF0.MCR; + pCanMsg->DLC = CANx->IF0.MCR & CAN_IF_MCR_DLC_Msk; + pCanMsg->EOB = CANx->IF0.MCR & CAN_IF_MCR_EOB_Msk; + pCanMsg->Data[0] = CANx->IF0.DA0R & CAN_IF_DAT_A0_DATA0_Msk; + pCanMsg->Data[1] = (CANx->IF0.DA0R & CAN_IF_DAT_A0_DATA1_Msk) >> CAN_IF_DAT_A0_DATA1_Pos; + pCanMsg->Data[2] = CANx->IF0.DA1R & CAN_IF_DAT_A1_DATA2_Msk; + pCanMsg->Data[3] = (CANx->IF0.DA1R & CAN_IF_DAT_A1_DATA3_Msk) >> CAN_IF_DAT_A1_DATA3_Pos; + pCanMsg->Data[4] = CANx->IF0.DB0R & CAN_IF_DAT_B0_DATA4_Msk; + pCanMsg->Data[5] = (CANx->IF0.DB0R & CAN_IF_DAT_B0_DATA5_Msk) >> CAN_IF_DAT_B0_DATA5_Pos; + pCanMsg->Data[6] = CANx->IF0.DB1R & CAN_IF_DAT_B1_DATA6_Msk; + pCanMsg->Data[7] = (CANx->IF0.DB1R & CAN_IF_DAT_B1_DATA7_Msk) >> CAN_IF_DAT_B1_DATA7_Pos; + } + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Set bus baud-rate. + * @param CANx: The pointer to CAN module base address. + * @param wBaudRate: The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. + * @retval CurrentBitRate: Real baud-rate value. + ***********************************************************************************************************/ +u32 CAN_SetBaudRate(HT_CAN_TypeDef *CANx, u32 wBaudRate) +{ + u32 wTseg0, wTseg1; + u32 wBrp; + u32 wValue; + + CAN_EnterInitMode(CANx); + + SystemCoreClockUpdate(); + + wTseg0 = 2; + wTseg1 = 1; + + wValue = SystemCoreClock / wBaudRate; + + while(1) + { + if(((wValue % (wTseg0 + wTseg1 + 3)) == 0)) + break; + if(wTseg1 < 7) + wTseg1++; + + if((wValue % (wTseg0 + wTseg1 + 3)) == 0) + break; + if(wTseg0 < 15) + wTseg0++; + else + { + wTseg0 = 2; + wTseg1 = 1; + break; + } + } + + wBrp = SystemCoreClock / (wBaudRate) / (wTseg0 + wTseg1 + 3) - 1; + + wValue = ((u32)wTseg1 << CAN_BTR_TSEG1_Pos) | ((u32)wTseg0 << CAN_BTR_TSEG0_Pos) | + (wBrp & CAN_BTR_BRP_Msk) | (CANx->BTR & CAN_BTR_SJW_Msk); + CANx->BTR = wValue; + CANx->BRPER = (wBrp >> 6) & 0x0F; + + CAN_LeaveInitMode(CANx); + + return (CAN_GetCANBitRate(CANx)); +} + +/*********************************************************************************************************//** + * @brief The function is used to disable all CAN interrupt. + * @param CANx: The pointer to CAN module base address. + * @retval None + ***********************************************************************************************************/ +void CAN_Close(HT_CAN_TypeDef *CANx) +{ + CAN_DisableInt(CANx, (CAN_CR_IE_Msk | CAN_CR_SIE_Msk | CAN_CR_EIE_Msk)); +} + +/*********************************************************************************************************//** + * @brief Set CAN operation mode and target baud-rate. + * @param CANx: The pointer to CAN module base address. + * @param wBaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. + * @param wMode The CAN operation mode. + * @arg CAN_NORMAL_MODE : Normal operation. + * @arg CAN_BASIC_MODE : Basic operation. + * @arg CAN_SILENT_MODE : Silent operation. + * @arg CAN_LBACK_MODE : Loop Back operation. + * @arg CAN_LBS_MODE : Loop Back combined with Silent operation. + * @retval u32CurrentBitRate Real baud-rate value. + ***********************************************************************************************************/ +u32 CAN_Open(HT_CAN_TypeDef *CANx, u32 wBaudRate, u32 wMode) +{ + u32 CurrentBitRate; + + CurrentBitRate = CAN_SetBaudRate(CANx, wBaudRate); + + if(wMode) + CAN_EnterTestMode(CANx, wMode); + + return CurrentBitRate; +} + +/*********************************************************************************************************//** + * @brief The function is used to configure a transmit object. + * @param CANx: The pointer to CAN module base address. + * @param MsgNum: Specifies the Message object number, from 0 to 31. + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @retval FALSE No useful interface, TRUE Config message object success. + ***********************************************************************************************************/ +s32 CAN_SetTxMsg(HT_CAN_TypeDef *CANx, u32 MsgNum , STR_CANMSG_T_TypeDef* pCanMsg) +{ + u32 MsgIfNum = 0; + u32 i = 0; + + while((MsgIfNum = GetFreeIF(CANx)) == 2) + { + i++; + if(i > 0x10000000) + return FALSE; + } + + /* update the contents needed for transmission*/ + if(MsgIfNum ==0) + { + CANx->IF0.CMASK = 0xF3; /* CAN_CMASK_WRRD_Msk | CAN_CMASK_MASK_Msk | CAN_CMASK_ARB_Msk + | CAN_CMASK_CONTROL_Msk | CAN_CMASK_DATAA_Msk | CAN_CMASK_DATAB_Msk ; */ + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + CANx->IF0.ARB0 = 0; + CANx->IF0.ARB1 = (((pCanMsg->Id) & 0x7FF) << 2) | CAN_IF_ARB1_DIR_Msk | CAN_IF_ARB1_MSGVAL_Msk; + } + else + { + /* extended ID*/ + CANx->IF0.ARB0 = (pCanMsg->Id) & 0xFFFF; + CANx->IF0.ARB1 = ((pCanMsg->Id) & 0x1FFF0000) >> 16 | CAN_IF_ARB1_DIR_Msk + | CAN_IF_ARB1_XTD_Msk | CAN_IF_ARB1_MSGVAL_Msk; + } + + if(pCanMsg->FrameType) + CANx->IF0.ARB1 |= CAN_IF_ARB1_DIR_Msk; + else + CANx->IF0.ARB1 &= (~CAN_IF_ARB1_DIR_Msk); + + CANx->IF0.DA0R = ((u16)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]; + CANx->IF0.DA1R = ((u16)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]; + CANx->IF0.DB0R = ((u16)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]; + CANx->IF0.DB1R = ((u16)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]; + CANx->IF0.MCR = 0; + if(pCanMsg->RMTEN) + CANx->IF0.MCR |= CAN_IF_MCR_RMTEN_Msk; + else + CANx->IF0.MCR &= (~CAN_IF_MCR_RMTEN_Msk); + if(pCanMsg->EOB) + CANx->IF0.MCR |= CAN_IF_MCR_EOB_Msk; + else + CANx->IF0.MCR &= (~CAN_IF_MCR_EOB_Msk); + + CANx->IF0.MCR |= CAN_IF_MCR_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCR_TXIE_Msk ; + CANx->IF0.CREQ = MsgNum +1; + } + else + { + CANx->IF1.CMASK = 0xF3; /* CAN_CMASK_WRRD_Msk | CAN_CMASK_MASK_Msk | CAN_CMASK_ARB_Msk + | CAN_CMASK_CONTROL_Msk | CAN_CMASK_DATAA_Msk | CAN_CMASK_DATAB_Msk ; */ + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + CANx->IF1.ARB0 = 0; + CANx->IF1.ARB1 = (((pCanMsg->Id) & 0x7FF) << 2) | CAN_IF_ARB1_DIR_Msk | CAN_IF_ARB1_MSGVAL_Msk; + } + else + { + /* extended ID*/ + CANx->IF1.ARB0 = (pCanMsg->Id) & 0xFFFF; + CANx->IF1.ARB1 = ((pCanMsg->Id) & 0x1FFF0000) >> 16 | CAN_IF_ARB1_DIR_Msk + | CAN_IF_ARB1_XTD_Msk | CAN_IF_ARB1_MSGVAL_Msk; + } + + if(pCanMsg->FrameType) + CANx->IF1.ARB1 |= CAN_IF_ARB1_DIR_Msk; + else + CANx->IF1.ARB1 &= (~CAN_IF_ARB1_DIR_Msk); + + CANx->IF1.DA0R = ((u16)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]; + CANx->IF1.DA1R = ((u16)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]; + CANx->IF1.DB0R = ((u16)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]; + CANx->IF1.DB1R = ((u16)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]; + + CANx->IF1.MCR = 0; + + if(pCanMsg->RMTEN) + CANx->IF1.MCR |= CAN_IF_MCR_RMTEN_Msk; + else + CANx->IF1.MCR &= (~CAN_IF_MCR_RMTEN_Msk); + + if(pCanMsg->EOB) + CANx->IF1.MCR |= CAN_IF_MCR_EOB_Msk; + else + CANx->IF1.MCR &= (~CAN_IF_MCR_EOB_Msk); + + CANx->IF1.MCR |= CAN_IF_MCR_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCR_TXIE_Msk ; + CANx->IF1.CREQ = MsgNum +1; + } + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Set transmit request bit. + * If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst + * (IFn_MCON[8]) will be ignored. + * @param CANx: The pointer to CAN module base address. + * @param u32MsgNum: Specifies the Message object number, from 0 to 31. + * @retval TRUE: Start transmit message. + ***********************************************************************************************************/ +s32 CAN_TriggerTxMsg(HT_CAN_TypeDef *CANx, u32 u32MsgNum) +{ + CANx->SR &= (~CAN_SR_TXOK_Msk); + + /* read the message contents*/ + CANx->IF1.CMASK = CAN_IF_CMASK_CLRINTPND_Msk + | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + + CANx->IF1.CREQ = u32MsgNum+1; + + while(CANx->IF1.CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + CANx->IF0.CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + CANx->IF0.CREQ = u32MsgNum+1; + + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Enable CAN interrupt. + * The application software has two possibilities to follow the source of a message interrupt. + * First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register. + * @param CANx: The pointer to CAN module base address. + * @param u32Mask: Interrupt Mask. + * @arg CAN_CR_IE_Msk : Module interrupt enable. + * @arg CAN_CR_SIE_Msk: Status change interrupt enable. + * @arg CAN_CR_EIE_Msk: Error interrupt enable. + * @retval None + ***********************************************************************************************************/ +void CAN_EnableInt(HT_CAN_TypeDef *CANx, u32 u32Mask) +{ + CAN_EnterInitMode(CANx); + + CANx->CR = (CANx->CR & 0xF1) | ((u32Mask & CAN_CR_IE_Msk) ? CAN_CR_IE_Msk : 0) + | ((u32Mask & CAN_CR_SIE_Msk) ? CAN_CR_SIE_Msk : 0) + | ((u32Mask & CAN_CR_EIE_Msk) ? CAN_CR_EIE_Msk : 0); + + + CAN_LeaveInitMode(CANx); +} + +/*********************************************************************************************************//** + * @brief Disable CAN interrupt. + * @param CANx: The pointer to CAN module base address. + * @param Mask: Interrupt Mask. (CAN_CR_IE_Msk / CAN_CR_SIE_Msk / CAN_CR_EIE_Msk). + * @retval None + ***********************************************************************************************************/ +void CAN_DisableInt(HT_CAN_TypeDef *CANx, u32 Mask) +{ + CAN_EnterInitMode(CANx); + + CANx->CR = CANx->CR & ~(CAN_CR_IE_Msk | ((Mask & CAN_CR_SIE_Msk) ? CAN_CR_SIE_Msk : 0) + | ((Mask & CAN_CR_EIE_Msk) ? CAN_CR_EIE_Msk : 0)); + + CAN_LeaveInitMode(CANx); +} + + +/*********************************************************************************************************//** + * @brief The function is used to configure a receive message object. + * @param CANx: The pointer to CAN module base address. + * @param MsgNum: Specifies the Message object number, from 0 to 31. + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @arg CAN_STD_ID: The 11-bit identifier. + * @arg CAN_EXT_ID: The 29-bit identifier. + * @retval FALSE No useful interface, TRUE Configure a receive message object success. + ***********************************************************************************************************/ +s32 CAN_SetRxMsg(HT_CAN_TypeDef *CANx, u32 MsgNum , STR_CANMSG_R_TypeDef* pCanMsg) +{ + u32 TimeOutCount = 0; + + while(CAN_SetRxMsgObj(CANx, MsgNum, pCanMsg) == FALSE) + { + TimeOutCount++; + + if(TimeOutCount >= 0x10000000) return FALSE; + } + + return TRUE; +} + +/*********************************************************************************************************//** + * @brief The function is used to configure several receive message objects. + * The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message + * reception and transmission by buffering the data to be transferred. + * @param CANx: The pointer to CAN module base address. + * @param MsgNum: The starting MSG RAM number(0 ~ 31). + * @param MsgCount: the number of MSG RAM of the FIFO. + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @arg CAN_STD_ID: The 11-bit identifier. + * @arg CAN_EXT_ID: The 29-bit identifier. + * @retval FALSE No useful interface, TRUE Configure receive message objects success. + ***********************************************************************************************************/ +s32 CAN_SetMultiRxMsg(HT_CAN_TypeDef *CANx, u32 MsgNum , u32 MsgCount, STR_CANMSG_R_TypeDef* pCanMsg) +{ + u32 i = 0; + u32 TimeOutCount; + + for(i = 1; i < MsgCount+1; i++) + { + TimeOutCount = 0; + pCanMsg->EOB = 0; + + if(i == MsgCount) + pCanMsg->EOB=1; + + while(CAN_SetRxMsgObj(CANx, MsgNum, pCanMsg) == FALSE) + { + TimeOutCount++; + + if(TimeOutCount >= 0x10000000) + return FALSE; + } + MsgNum ++; + } + + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Send CAN message. + * @param CANx: The pointer to CAN module base address. + * @param MsgNum: Specifies the Message object number, from 0 to 31. + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @retval FALSE: 1. When operation in basic mode: Transmit message time out. + * 2. When operation in normal mode: No useful interface. + * TRUE: Transmit Message success. + ***********************************************************************************************************/ +s32 CAN_Transmit(HT_CAN_TypeDef *CANx, u32 MsgNum , STR_CANMSG_T_TypeDef* pCanMsg) +{ + if((CANx->CR & CAN_CR_TEST_Msk) && (CANx->TR & CAN_TEST_BASIC_Msk)) + { + return (CAN_BasicSendMsg(CANx, pCanMsg)); + } + else + { + if(CAN_SetTxMsg(CANx, MsgNum, pCanMsg) == FALSE) + return FALSE; + + CANx->SR &= (~CAN_SR_TXOK_Msk); + + /* read the message contents*/ + CANx->IF1.CMASK = CAN_IF_CMASK_CLRINTPND_Msk + | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + + CANx->IF1.CREQ = MsgNum+1; + + while(CANx->IF1.CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + CANx->IF0.CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + CANx->IF0.CREQ = MsgNum+1; + } + + return TRUE; +} + +/*********************************************************************************************************//** + * @brief Gets the message, if received. + * The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message + * reception and transmission by buffering the data to be transferred. + * @param CANx: The pointer to CAN module base address. + * @param MsgNum: Specifies the Message object number, from 0 to 31. + * @param pCanMsg: Pointer to the message structure where received data is copied. + * @retval FALSE: No any message received, TRUE: Receive Message success. + ***********************************************************************************************************/ +s32 CAN_Receive(HT_CAN_TypeDef *CANx, u32 MsgNum , STR_CANMSG_T_TypeDef* pCanMsg) +{ + if((CANx->CR & CAN_CR_TEST_Msk) && (CANx->TR & CAN_TEST_BASIC_Msk)) + { + return (CAN_BasicReceiveMsg(CANx, pCanMsg)); + } + else + { + return CAN_ReadMsgObj(CANx, MsgNum, TRUE, pCanMsg); + } +} + +/*********************************************************************************************************//** + * @brief Clear interrupt pending bit. + * @param CANx: The pointer to CAN module base address. + * @param MsgNum: Specifies the Message object number, from 0 to 31. + * @retval None + ***********************************************************************************************************/ +void CAN_CLR_INT_PENDING_BIT(HT_CAN_TypeDef *CANx, u32 MsgNum) +{ + u32 u32IFBusyCount = 0; + + while(u32IFBusyCount < 0x10000000) + { + if((CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) + { + CANx->IF0.CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + CANx->IF0.CREQ = MsgNum+1; + break; + } + else if((CANx->IF1.CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) + { + CANx->IF1.CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + CANx->IF1.CREQ = MsgNum+1; + break; + } + + u32IFBusyCount++; + } +} + +/*********************************************************************************************************//** + * @brief The function is used to configure Mask as the message object. + * @param CANx: The pointer to CAN module base address. + * @param MsgObj: Specifies the Message object number, from 0 to 31. + * @param MaskMsg: Pointer to the message structure where received data is copied. + * @arg CAN_STD_ID: The 11-bit identifier. + * @arg CAN_EXT_ID: The 29-bit identifier. + * @retval FALSE No useful interface, TRUE Configure a receive message object success. + ***********************************************************************************************************/ +s32 CAN_MsgObjMaskConfig(HT_CAN_TypeDef *CANx, u32 MsgObj, STR_CANMSG_R_TypeDef* MaskMsg) +{ + if(MaskMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + CANx->IF0.ARB0 = 0; + CANx->IF0.ARB1 = (((MaskMsg->Id) & 0x7FF) << 2) | CAN_IF_ARB1_MSGVAL_Msk ; + + /* Set the Mask Standard ID(11-bit) for IFn Mask Register is used for acceptance filtering*/ + CANx->IF0.MASK0 = 0; + CANx->IF0.MASK1 = ((MaskMsg->Id & 0x7FF) << 2) ; + } + else + { + /* extended ID*/ + CANx->IF0.ARB0 = (MaskMsg->Id) & 0xFFFF; + CANx->IF0.ARB1 = ((MaskMsg->Id) & 0x1FFF0000) >> 16 | CAN_IF_ARB1_DIR_Msk + | CAN_IF_ARB1_XTD_Msk | CAN_IF_ARB1_MSGVAL_Msk; + /* Set the Mask Extended ID(29-bit) for IFn Mask Register is used for acceptance filtering*/ + CANx->IF0.MASK0 = (MaskMsg->Id) & 0xFFFF; + CANx->IF0.MASK1 = ((MaskMsg->Id) & 0x1FFF0000) >> 16 ; + } + + if(MaskMsg->u8Xtd) + CANx->IF0.MASK1 |= CAN_IF_MASK1_MXTD_Msk; /* The extended identifier bit (IDE) is used for acceptance filtering */ + else + CANx->IF0.MASK1 &= (~CAN_IF_MASK1_MXTD_Msk); /* The extended identifier bit (IDE) has no effect on the acceptance filtering */ + + if(MaskMsg->u8Dir) + CANx->IF0.MASK1 |= CAN_IF_MASK1_MDIR_Msk; /* The message direction bit (Dir) is used for acceptance filtering */ + else + CANx->IF0.MASK1 &= (~CAN_IF_MASK1_MDIR_Msk); /* The message direction bit (Dir) has no effect on the acceptance filtering */ + + CANx->IF0.MCR |= CAN_IF_MCR_UMASK_Msk; /* Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering */ + + /* Update the contents needed for transmission*/ + CANx->IF0.CMASK = CAN_IF_CMASK_WRRD_Msk /* Transfer data from the selected Message Buffer Registers to the Message Object addressed */ + | CAN_IF_CMASK_MASK_Msk; /* Transfer Identifier Mask + MDir + MXtd to Message Object */ + + CANx->IF0.DA0R = 0; + CANx->IF0.DA1R = 0; + CANx->IF0.DB0R = 0; + CANx->IF0.DB1R = 0; + + /* Set the Message Object in the Message RAM is selected for data transfer */ + CANx->IF0.CREQ = 1 + MsgObj; + + return TRUE; +} + +/* Private functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CAN_Private_Functions CAN private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Check if SmartCard slot is presented. + * @param CANx: The pointer to CAN module base address. +* @retval Free IF number. IF0_NUM or IF1_NUM or IF_TOTAL_NUM (No IF is free) + ***********************************************************************************************************/ +static CANIF_NUMBER_Enum GetFreeIF(HT_CAN_TypeDef *CANx) +{ + if((CANx->IF0.CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) + return IF0_NUM; + else if((CANx->IF1.CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) + return IF1_NUM; + else + return IF_TOTAL_NUM; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ckcu.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ckcu.c new file mode 100644 index 00000000000..9238830a049 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ckcu.c @@ -0,0 +1,1105 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_ckcu.c + * @version $Rev:: 7322 $ + * @date $Date:: 2023-10-28 #$ + * @brief This file provides all the Clock Control Unit firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_ckcu.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CKCU CKCU + * @brief CKCU driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Private_Define CKCU private definitions + * @{ + */ + +/* GCFGR bit field definition */ +#define CKCU_POS_CKOUTSRC 0 +#define CKCU_MASK_CKOUTSRC ((u32)0x7 << CKCU_POS_CKOUTSRC) + +#define CKCU_POS_PLLSRC 8 +#define CKCU_MASK_PLLSRC ((u32)0x1 << CKCU_POS_PLLSRC) + +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_POS_USBPLLSRC 9 +#define CKCU_MASK_USBPLLSRC ((u32)0x1 << CKCU_POS_USBPLLSRC) + +#define CKCU_POS_USBSRC 10 +#define CKCU_MASK_USBSRC ((u32)0x1 << CKCU_POS_USBSRC) +#endif + +#define CKCU_POS_CKREFPRE 11 +#define CKCU_MASK_CKREFPRE ((u32)0x1F << CKCU_POS_CKREFPRE) + +/* GCCR bit field definition */ +#define CKCU_POS_SW 0 +#define CKCU_MASK_SW ((u32)0x7 << CKCU_POS_SW) + +#if (LIBCFG_CKCU_USB_PLL) +#define CKCU_POS_USBPLLEN 3 +#define CKCU_MASK_USBPLLEN ((u32)0x1 << CKCU_POS_USBPLLEN) +#endif + +#define CKCU_POS_PLLEN 9 +#define CKCU_MASK_PLLEN ((u32)0x1 << CKCU_POS_PLLEN) + +#define CKCU_POS_HSEEN 10 +#define CKCU_MASK_HSEEN ((u32)0x1 << CKCU_POS_HSEEN) + +#define CKCU_POS_HSIEN 11 +#define CKCU_MASK_HSIEN ((u32)0x1 << CKCU_POS_HSIEN) + +#define CKCU_POS_CKMEN 16 +#define CKCU_MASK_CKMEN ((u32)0x1 << CKCU_POS_CKMEN) + +#define CKCU_POS_PSRCEN 17 +#define CKCU_MASK_PSRCEN ((u32)0x1 << CKCU_POS_PSRCEN) + +/* PLLCFGR bit field definition */ +#define CKCU_POS_POTD 21 +#define CKCU_MASK_POTD ((u32)0x3 << CKCU_POS_POTD) + +#define CKCU_POS_PFBD 23 +#define CKCU_MASK_PFBD ((u32)0x0F << CKCU_POS_PFBD) + +/* PLLCR bit field definition */ +#define CKCU_POS_PLLBYPASS 31 +#define CKCU_MASK_PLLBYPASS ((u32)0x1 << CKCU_POS_PLLBYPASS) + +/* APBCFGR bit field definition */ +#define CKCU_POS_ADC0DIV 16 +#define CKCU_MASK_ADC0DIV ((u32)0x7 << CKCU_POS_ADC0DIV) + +#if (LIBCFG_ADC1) +#define CKCU_POS_ADC1DIV 20 +#define CKCU_MASK_ADC1DIV ((u32)0x7 << CKCU_POS_ADC1DIV) +#endif + +#if (LIBCFG_CKCU_LCD_SRC) +#define CKCU_POS_LCDSRC 4 +#define CKCU_MASK_LCDSRC ((u32)0x3 << CKCU_POS_LCDSRC) +#endif + +#if (LIBCFG_LCD) +#define CKCU_POS_LCDDIV 8 +#define CKCU_MASK_LCDDIV ((u32)0x7 << CKCU_POS_LCDDIV) +#endif + +#if (LIBCFG_CKCU_MCTM_SRC) +#define CKCU_POS_MCTMCSEL 8 +#define CKCU_MASK_MCTMCSEL ((u32)0x1 << CKCU_POS_MCTMCSEL) +#endif + +#if (LIBCFG_MIDI) +#define CKCU_POS_MIDIDIV 24 +#define CKCU_MASK_MIDIDIV ((u32)0x7 << CKCU_POS_MIDIDIV) +#endif + +/* CKST bit field definition */ +#define CKCU_POS_PLLST 8 +#define CKCU_MASK_PLLST ((u32)0xF << CKCU_POS_PLLST) + +#define CKCU_POS_HSEST 16 +#define CKCU_MASK_HSEST ((u32)0x3 << CKCU_POS_HSEST) + +#define CKCU_POS_HSIST 24 +#define CKCU_MASK_HSIST ((u32)0x7 << CKCU_POS_HSIST) + +#define CKCU_POS_CKSWST 0 +#define CKCU_MASK_CKSWST ((u32)0x7 << CKCU_POS_CKSWST) + +/* LPCR bit field definition */ +#define CKCU_POS_BKISO 0 +#define CKCU_MASK_BKISO ((u32)0x1 << CKCU_POS_BKISO) + +/* HSICR bit field definition */ +#define CKCU_POS_TRIMEN (0) +#define CKCU_MASK_TRIMEN ((u32)0x1 << CKCU_POS_TRIMEN) + +#define CKCU_POS_ATCEN (1) +#define CKCU_MASK_ATCEN ((u32)0x1 << CKCU_POS_ATCEN) + +#define CKCU_POS_REFCLKSEL (5) +#define CKCU_MASK_REFCLKSEL ((u32)0x3 << CKCU_POS_REFCLKSEL) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup CKCU_Private_Macro CKCU private macros + * @{ + */ +#define CKCU_BF_WRITE(Reg, Mask, Pos, WriteValue) (Reg = ((Reg & ~((u32)Mask)) | ((u32)WriteValue << Pos))) +#define CKCU_BF_READ(Reg, Mask, Pos) ((Reg & (u32)Mask) >> Pos) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup CKCU_Exported_Functions CKCU exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CKCU registers to the reset values. + * @retval None + ************************************************************************************************************/ +void CKCU_DeInit(void) +{ + /* Reset system clock */ + CKCU_HSICmd(ENABLE); + while (CKCU_GetClockReadyStatus(CKCU_FLAG_HSIRDY) == RESET); + CKCU_SysClockConfig(CKCU_SW_HSI); + + #if (LIBCFG_CKCU_USB_PLL) + HT_CKCU->GCFGR = 0x00000302; /* Reset value of GCFGR */ + #else + HT_CKCU->GCFGR = 0x00000102; /* Reset value of GCFGR */ + #endif + HT_CKCU->GCCR = 0x00000803; /* Reset value of GCCR */ + HT_CKCU->GCIR = 0x000000FF; /* Clear all interrupt flags */ + + #if (!LIBCFG_NO_PLL) + HT_CKCU->PLLCR = 0; /* Reset value of PLLCR */ + #endif + HT_CKCU->AHBCFGR = 0; /* Reset value of AHBCFGR */ + HT_CKCU->AHBCCR = 0x00000065; /* Reset value of AHBCCR */ + #if (!LIBCFG_NO_ADC) + HT_CKCU->APBCFGR = 0x00010000; /* Reset value of APBCFGR */ + #endif + HT_CKCU->APBCCR0 = 0; /* Reset value of APBCCR0 */ + HT_CKCU->APBCCR1 = 0; /* Reset value of APBCCR1 */ + #if (!LIBCFG_CKCU_NO_APB_PRESCALER) + HT_CKCU->APBPCSR0 = 0; /* Reset value of APBPCSR0 */ + HT_CKCU->APBPCSR1 = 0; /* Reset value of APBPCSR1 */ + #endif + #if (!LIBCFG_CKCU_NO_AUTO_TRIM) + HT_CKCU->HSICR = 0; /* Reset value of HSICR */ + #endif + #if ((!LIBCFG_CKCU_NO_APB_PRESCALER) && (LIBCFG_PWM0 || LIBCFG_PWM1 || LIBCFG_MIDI || LIBCFG_DAC0 || LIBCFG_DAC1 || LIBCFG_DACDUAL16 || LIBCFG_LCD || LIBCFG_LEDC || LIBCFG_TKEY)) + HT_CKCU->APBPCSR2 = 0; /* Reset value of APBPCSR2 */ + #endif + #if (LIBCFG_CKCU_HSIRDYCR) + HT_CKCU->HSIRDYCR = 0; /* Reset value of HSIRDYCR */ + #endif + #if (!LIBCFG_CKCU_NO_LPCR) + HT_CKCU->LPCR = 0; /* Reset value of LPCR */ + #endif + HT_CKCU->MCUDBGCR = 0; /* Reset value of MCUDBGCR */ +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the external high speed oscillator (HSE). + * @note HSE can not be stopped if it is used by system clock or PLL. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_HSECmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_HSEEN, CKCU_POS_HSEEN, Cmd); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the internal high speed oscillator (HSI). + * @note HSI can not be stopped if it is used by system clock or PLL. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_HSICmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_HSIEN, CKCU_POS_HSIEN, Cmd); +} + +#if (!LIBCFG_NO_PLL) +/*********************************************************************************************************//** + * @brief Enable or Disable the PLL clock. + * @note PLL can not be stopped if it is used by system clock or CK_REF. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_PLLCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_PLLEN, CKCU_POS_PLLEN, Cmd); +} +#endif + +#if (LIBCFG_CKCU_USB_PLL) +/*********************************************************************************************************//** + * @brief Enable or Disable the USBPLL clock. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_USBPLLCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_USBPLLEN, CKCU_POS_USBPLLEN, Cmd); +} +#endif + +/*********************************************************************************************************//** + * @brief Wait for HSE is ready to be used. + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus CKCU_WaitHSEReady(void) +{ + u32 ReadyCnt = 0; + + /* Wait until HSE is ready or time-out occurred */ + while (CKCU_GetClockReadyStatus(CKCU_FLAG_HSERDY) != SET) + { + if (++ReadyCnt >= HSE_READY_TIME) + { + return ERROR; + } + } + + return SUCCESS; +} + +/*********************************************************************************************************//** + * @brief Check whether the specific clock ready flag is set or not. + * @param CKCU_FLAG: specify the clock ready flag. + * This parameter can be one of the following values: + * @arg CKCU_FLAG_USBPLLRDY : USB PLL ready flag + * @arg CKCU_FLAG_PLLRDY : PLL ready flag + * @arg CKCU_FLAG_HSERDY : HSE ready flag + * @arg CKCU_FLAG_HSIRDY : HSI ready flag + * @arg CKCU_FLAG_LSERDY : LSE ready flag + * @arg CKCU_FLAG_LSIRDY : LSI ready flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CKCU_GetClockReadyStatus(u32 CKCU_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_FLAG(CKCU_FLAG)); + + if (HT_CKCU->GCSR & CKCU_FLAG) + { + return SET; + } + else + { + return RESET; + } +} + +#if (!LIBCFG_NO_PLL) +/*********************************************************************************************************//** + * @brief This function is used to configure PLL. + * @param PLL_InitStruct: pointer to CKCU_PLLInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_PLLInit(CKCU_PLLInitTypeDef *PLL_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_PLL_CLKSRC(PLL_InitStruct->ClockSource)); + Assert_Param(IS_CONTROL_STATUS(PLL_InitStruct->BYPASSCmd)); + Assert_Param(IS_PLL_CFG(PLL_InitStruct->CFG)); + + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_PLLSRC, CKCU_POS_PLLSRC, PLL_InitStruct->ClockSource); + CKCU_BF_WRITE(HT_CKCU->PLLCR, CKCU_MASK_PLLBYPASS, CKCU_POS_PLLBYPASS, PLL_InitStruct->BYPASSCmd); + HT_CKCU->PLLCFGR = (HT_CKCU->PLLCFGR & 0x0000FFFF) | PLL_InitStruct->CFG; +} +#endif + +#if (LIBCFG_CKCU_USB_PLL) +/*********************************************************************************************************//** + * @brief This function is used to configure USBPLL. + * @param USBPLL_InitStruct: pointer to CKCU_PLLInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_USBPLLInit(CKCU_PLLInitTypeDef *USBPLL_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_PLL_CLKSRC(USBPLL_InitStruct->ClockSource)); + Assert_Param(IS_USBPLL_CFG(USBPLL_InitStruct->CFG)); + + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_USBPLLSRC, CKCU_POS_USBPLLSRC, USBPLL_InitStruct->ClockSource); + HT_CKCU->PLLCFGR = (HT_CKCU->PLLCFGR & 0xFFFF0000) | USBPLL_InitStruct->CFG; +} + +/*********************************************************************************************************//** + * @brief Configure the CK_USB clock source. + * @param USBSRC: specify the USB clock source. + * This parameter can be one of the following values: + * @arg CKCU_CKPLL : CK_USB = CK_PLL + * @arg CKCU_CKUSBPLL : CK_USB = CK_USBPLL + * @retval None + ************************************************************************************************************/ +void CKCU_USBClockConfig(CKCU_USBSRC_TypeDef USBSRC) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_USBSRC, CKCU_POS_USBSRC, USBSRC); +} +#endif + +#if (LIBCFG_CKCU_LCD_SRC) +/*********************************************************************************************************//** + * @brief Configure LCD clock source. + * @param LCDSRC: Specify LCD clock source. + * This parameter can be one of the following values: + * @arg CKCU_LCDSRC_LSI : + * @arg CKCU_LCDSRC_LSE : + * @arg CKCU_LCDSRC_HSI : + * @arg CKCU_LCDSRC_HSE : + * @retval None + ************************************************************************************************************/ +void CKCU_LCDClockConfig(CKCU_LCDSRC_TypeDef LCDSRC) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_LCDSRC, CKCU_POS_LCDSRC, LCDSRC); +} +#endif + +#if (LIBCFG_CKCU_MCTM_SRC) +/*********************************************************************************************************//** + * @brief Configure the MCTM clock source. + * @param CKCU_MCTMSRC_x: specify the MCTM clock source. + * This parameter can be one of the following values: + * @arg CKCU_MCTMSRC_AHB : CK_MCTM = CK_AHB + * @arg CKCU_MCTMSRC_USBPLL : CK_MCTM = CK_USBPLL + * @retval None + ************************************************************************************************************/ +void CKCU_MCTMClockConfig(CKCU_MCTMSRC_TypeDef CKCU_MCTMSRC_x) +{ + Assert_Param(IS_MCTM_SRC(CKCU_MCTMSRC_x)); + CKCU_BF_WRITE(HT_CKCU->APBCFGR, CKCU_MASK_MCTMCSEL, CKCU_POS_MCTMCSEL, CKCU_MCTMSRC_x); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure the CK_SYS source. + * @param CLKSRC: specify the system clock source. + * This parameter can be one of the following values: + * @arg CKCU_SW_PLL : PLL is selected as CK_SYS + * @arg CKCU_SW_HSE : HSE is selected as CK_SYS + * @arg CKCU_SW_HSI : HSI is selected as CK_SYS + * @arg CKCU_SW_LSE : LSE is selected as CK_SYS + * @arg CKCU_SW_LSI : LSI is selected as CK_SYS + * @retval None + ************************************************************************************************************/ +ErrStatus CKCU_SysClockConfig(CKCU_SW_TypeDef CLKSRC) +{ + u32 cnt = 0xFF; + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_SW, CKCU_POS_SW, CLKSRC); + + /* Wait until new system clock source is applied or time-out */ + while (--cnt) + { + if (CKCU_GetSysClockSource() == (u32)CLKSRC) + { + return SUCCESS; + } + } + + return ERROR; +} + +/*********************************************************************************************************//** + * @brief Return the source clock which is used as system clock. + * @retval The source clock used as system clock. + * 0x01: PLL is selected as system clock + * 0x02: HSE is selected as system clock + * 0x03: HSI is selected as system clock + * 0x06: LSE is selected as system clock + * 0x07: LSI is selected as system clock + ************************************************************************************************************/ +u32 CKCU_GetSysClockSource(void) +{ + return ((u32)CKCU_BF_READ(HT_CKCU->CKST, CKCU_MASK_CKSWST, CKCU_POS_CKSWST)); +} + +/*********************************************************************************************************//** + * @brief Configure the CK_AHB prescaler. + * @param HCLKPRE: specify the value of divider. + * This parameter can be one of the following values: + * @arg CKCU_SYSCLK_DIV1 : HCLK = CK_SYS + * @arg CKCU_SYSCLK_DIV2 : HCLK = CK_SYS / 2 + * @arg CKCU_SYSCLK_DIV4 : HCLK = CK_SYS / 4 + * @arg CKCU_SYSCLK_DIV8 : HCLK = CK_SYS / 8 + * @arg CKCU_SYSCLK_DIV16 : HCLK = CK_SYS / 16 + * @arg CKCU_SYSCLK_DIV32 : HCLK = CK_SYS / 32 + * @retval None + ************************************************************************************************************/ +void CKCU_SetHCLKPrescaler(CKCU_SYSCLKDIV_TypeDef HCLKPRE) +{ + HT_CKCU->AHBCFGR = HCLKPRE; +} + +/*********************************************************************************************************//** + * @brief Configure the CK_REF prescaler. + * @param CKREFPRE: specify the value of divider. + * This parameter can be: CKCU_CKREFPRE_DIV2 to CKCU_CKREFPRE_DIV64 (CK_REF = CK_PLL / (2 * (N + 1)), N = 0 ~ 31) + * @retval None + ************************************************************************************************************/ +void CKCU_SetCKREFPrescaler(CKCU_CKREFPRE_TypeDef CKREFPRE) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_CKREFPRE, CKCU_POS_CKREFPRE, CKREFPRE); +} + +#if (!LIBCFG_NO_ADC) +/*********************************************************************************************************//** + * @brief Configure the CK_ADCn prescaler. + * @param CKCU_ADCPRE_ADCn: specify the ADCn. + * @param CKCU_ADCPRE_DIVn: specify the prescaler value. + * This parameter can be one of the following values: + * @arg CKCU_ADCPRE_DIV1 : CK_ADC = HCLK / 1 + * @arg CKCU_ADCPRE_DIV2 : CK_ADC = HCLK / 2 + * @arg CKCU_ADCPRE_DIV3 : CK_ADC = HCLK / 3 + * @arg CKCU_ADCPRE_DIV4 : CK_ADC = HCLK / 4 + * @arg CKCU_ADCPRE_DIV8 : CK_ADC = HCLK / 8 + * @arg CKCU_ADCPRE_DIV16 : CK_ADC = HCLK / 16 + * @arg CKCU_ADCPRE_DIV32 : CK_ADC = HCLK / 32 + * @arg CKCU_ADCPRE_DIV64 : CK_ADC = HCLK / 64 + * @retval None + ************************************************************************************************************/ +void CKCU_SetADCnPrescaler(CKCU_ADCPRE_ADCn_TypeDef CKCU_ADCPRE_ADCn, CKCU_ADCPRE_TypeDef CKCU_ADCPRE_DIVn) +{ + HT_CKCU->APBCFGR = (HT_CKCU->APBCFGR & (~(0x07 << CKCU_ADCPRE_ADCn))) | (CKCU_ADCPRE_DIVn << CKCU_ADCPRE_ADCn); +} +#endif + +#if (LIBCFG_LCD) +/*********************************************************************************************************//** + * @brief Configure LCD clock prescaler. + * @param LCDCPS: Specify LCD clock prescaler. + * This parameter can be one of the following values: + * @arg CKCU_LCDPRE_DIV1 : + * @arg CKCU_LCDPRE_DIV2 : + * @arg CKCU_LCDPRE_DIV4 : + * @arg CKCU_LCDPRE_DIV8 : + * @arg CKCU_LCDPRE_DIV16 : + * @retval None + ************************************************************************************************************/ +void CKCU_SetLCDPrescaler(CKCU_LCDPRE_TypeDef LCDPRE) +{ + CKCU_BF_WRITE(HT_CKCU->APBCFGR, CKCU_MASK_LCDDIV, CKCU_POS_LCDDIV, LCDPRE); +} +#endif + +#if (LIBCFG_MIDI) +/*********************************************************************************************************//** + * @brief Configure the CK_MIDI prescaler. + * @param MIDIPRE: specify the value of divider. + * This parameter can be: + * @arg CKCU_MIDIPRE_DIV8 : CK_MIDI = HCLK / 8 + * @arg CKCU_MIDIPRE_DIV9 : CK_MIDI = HCLK / 9 + * @arg CKCU_MIDIPRE_DIV11 : CK_MIDI = HCLK / 11 + * @arg CKCU_MIDIPRE_DIV13 : CK_MIDI = HCLK / 13 + * @arg CKCU_MIDIPRE_DIV16 : CK_MIDI = HCLK / 16 + * @retval None + ************************************************************************************************************/ +void CKCU_SetMIDIPrescaler(CKCU_MIDIPRE_TypeDef MIDIPRE) +{ + CKCU_BF_WRITE(HT_CKCU->APBCFGR, CKCU_MASK_MIDIDIV, CKCU_POS_MIDIDIV, MIDIPRE); +} +#endif + +/*********************************************************************************************************//** + * @brief Return the frequency of the different clocks. + * @param CKCU_Clk: pointer to CKCU_ClocksTypeDef structure to get the clocks frequency. + * @retval None + ************************************************************************************************************/ +void CKCU_GetClocksFrequency(CKCU_ClocksTypeDef* CKCU_Clk) +{ + u32 div; + u32 SystemCoreClockSrc = (HT_CKCU->CKST) & 7UL; +#if (!LIBCFG_NO_PLL) + CKCU_Clk->PLL_Freq = CKCU_GetPLLFrequency(); +#endif + /* Get system frequency */ + switch (SystemCoreClockSrc) + { +#if (!LIBCFG_NO_PLL) + case CKCU_SW_PLL: + CKCU_Clk->SYSCK_Freq = CKCU_Clk->PLL_Freq; + break; +#endif + case CKCU_SW_HSE: + CKCU_Clk->SYSCK_Freq = HSE_VALUE; + break; + case CKCU_SW_HSI: + CKCU_Clk->SYSCK_Freq = HSI_VALUE; + break; + #if (LIBCFG_LSE) + case CKCU_SW_LSE: + CKCU_Clk->SYSCK_Freq = LSE_VALUE; + break; + #endif + case CKCU_SW_LSI: + CKCU_Clk->SYSCK_Freq = LSI_VALUE; + break; + default: + CKCU_Clk->SYSCK_Freq = 0; + break; + } + + /* Get HCLK frequency */ + div = HT_CKCU->AHBCFGR; + CKCU_Clk->HCLK_Freq = (div >= 5) ? ((CKCU_Clk->SYSCK_Freq) >> 5) : ((CKCU_Clk->SYSCK_Freq) >> div); + + /* Get ADC frequency */ + #if (LIBCFG_NO_ADC) + #else + #if (HT32_LIB_ENABLE_GET_CK_ADC) + div = CKCU_BF_READ(HT_CKCU->APBCFGR, CKCU_MASK_ADC0DIV, CKCU_POS_ADC0DIV); + CKCU_Clk->ADC0_Freq = (div == 7) ? ((CKCU_Clk->HCLK_Freq) / 3) : ((CKCU_Clk->HCLK_Freq) >> div); + #if (LIBCFG_ADC1) + div = CKCU_BF_READ(HT_CKCU->APBCFGR, CKCU_MASK_ADC1DIV, CKCU_POS_ADC1DIV); + CKCU_Clk->ADC1_Freq = (div == 7) ? ((CKCU_Clk->HCLK_Freq) / 3) : ((CKCU_Clk->HCLK_Freq) >> div); + #endif + #endif + #endif +} + +#if (!LIBCFG_NO_PLL) +/*********************************************************************************************************//** + * @brief Return the frequency of the PLL. + * @retval PLL Frequency + ************************************************************************************************************/ +u32 CKCU_GetPLLFrequency(void) +{ + u32 pllNO, pllNF, ClockSrc; + u32 CKCU_BB_PLLSRC = CKCU_BF_READ(HT_CKCU->GCFGR, CKCU_MASK_PLLSRC, CKCU_POS_PLLSRC); + u32 CKCU_BB_PLLBYPASS = CKCU_BF_READ(HT_CKCU->PLLCR, CKCU_MASK_PLLBYPASS, CKCU_POS_PLLBYPASS); + u32 CKCU_BB_PLLEN = CKCU_BF_READ(HT_CKCU->GCCR, CKCU_MASK_PLLEN, CKCU_POS_PLLEN); + /* Get PLL frequency */ + if (CKCU_BB_PLLEN == DISABLE) + { + return 0; + } + + ClockSrc = (CKCU_BB_PLLSRC == CKCU_PLLSRC_HSE) ? HSE_VALUE : HSI_VALUE; + + #if (LIBCFG_CKCU_PLLSRCDIV) + { + u32 PllSourceClockDiv = (HT_CKCU->PLLCFGR >> 28) & 1UL; + ClockSrc = ClockSrc >> PllSourceClockDiv; + } + #endif + + if (CKCU_BB_PLLBYPASS == ENABLE) + { + return ClockSrc; + } + + pllNF = CKCU_BF_READ(HT_CKCU->PLLCFGR, CKCU_MASK_PFBD, CKCU_POS_PFBD); + if (pllNF == 0) + pllNF = 16; + + pllNO = CKCU_BF_READ(HT_CKCU->PLLCFGR, CKCU_MASK_POTD, CKCU_POS_POTD); + + return ((ClockSrc * pllNF) >> pllNO); +} +#endif + +#if (!LIBCFG_CKCU_NO_APB_PRESCALER) +/*********************************************************************************************************//** + * @brief Configure the APB peripheral prescaler. + * @param Perip: specify the APB peripheral. + * This parameter can be: + * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, CKCU_PCLK_I2C2, + * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, + * CKCU_PCLK_CAN0, + * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, + * CKCU_PCLK_MCTM0, + * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, + * CKCU_PCLK_USART0, CKCU_PCLK_USART1, + * CKCU_PCLK_UART0, CKCU_PCLK_UART1, CKCU_PCLK_UART2, CKCU_PCLK_UART3 + * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC, CKCU_PCLK_CMP, CKCU_PCLK_OPA + * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, + * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, + * CKCU_PCLK_I2S, + * CKCU_PCLK_SCTM0, CKCU_PCLK_SCTM1, CKCU_PCLK_SCTM2, CKCU_PCLK_SCTM3 + * CKCU_PCLK_PWM0, CKCU_PCLK_PWM1 + * CKCU_PCLK_AFE, CKCU_PCLK_DAC0, CKCU_PCLK_DAC1, CKCU_PCLK_MIDI + * CKCU_PCLK_LEDC, CKCU_PCLK_TKEY + * @param PCLKPrescaler: specify the value of prescaler. + * This parameter can be: + * @arg CKCU_APBCLKPRE_DIV1: specific peripheral clock = PCLK / 1 (inapplicable to BKPRCLK) + * @arg CKCU_APBCLKPRE_DIV2: specific peripheral clock = PCLK / 2 (inapplicable to BKPRCLK) + * @arg CKCU_APBCLKPRE_DIV4: specific peripheral clock = PCLK / 4 + * @arg CKCU_APBCLKPRE_DIV8: specific peripheral clock = PCLK / 8 + * @arg CKCU_APBCLKPRE_DIV16: specific peripheral clock = PCLK / 16 (BKPRCLK only) + * @arg CKCU_APBCLKPRE_DIV32: specific peripheral clock = PCLK / 32 (BKPRCLK only) + * @retval None + ************************************************************************************************************/ +void CKCU_SetPeripPrescaler(CKCU_PeripPrescaler_TypeDef Perip, CKCU_APBCLKPRE_TypeDef PCLKPrescaler) +{ + u32 *PCSR = (u32 *)((&HT_CKCU->APBPCSR0) + (Perip >> CKCU_APBPCSR_OFFSET)); + u32 Prescaler = PCLKPrescaler; + if (Perip == CKCU_PCLK_BKPR) + { + Prescaler -= 2; + } + Perip &= 0x0000001F; + CKCU_BF_WRITE(*PCSR, (3UL << Perip), Perip, Prescaler); +} +#endif + +/*********************************************************************************************************//** + * @brief Return the operating frequency of the specific APB peripheral. + * @param Perip: specify the APB peripheral. + * This parameter can be: + * @arg CKCU_PCLK_I2C0, CKCU_PCLK_I2C1, CKCU_PCLK_I2C2, + * CKCU_PCLK_SPI0, CKCU_PCLK_SPI1, + * CKCU_PCLK_CAN0, + * CKCU_PCLK_BFTM0, CKCU_PCLK_BFTM1, + * CKCU_PCLK_MCTM0, + * CKCU_PCLK_GPTM0, CKCU_PCLK_GPTM1, + * CKCU_PCLK_USART0, CKCU_PCLK_USART1, + * CKCU_PCLK_UART0, CKCU_PCLK_UART1, CKCU_PCLK_UART2, CKCU_PCLK_UART3 + * CKCU_PCLK_AFIO, CKCU_PCLK_EXTI, CKCU_PCLK_ADC0, CKCU_PCLK_ADC1, CKCU_PCLK_CMP, CKCU_PCLK_OPA + * CKCU_PCLK_WDTR, CKCU_PCLK_BKPR, + * CKCU_PCLK_SCI0, CKCU_PCLK_SCI1, + * CKCU_PCLK_I2S, + * CKCU_PCLK_PWM0, CKCU_PCLK_PWM1 + * CKCU_PCLK_AFE, CKCU_PCLK_DAC0, CKCU_PCLK_DAC1, CKCU_PCLK_MIDI + * CKCU_PCLK_LEDC, CKCU_PCLK_TKEY + * @retval Frequency in Hz + ************************************************************************************************************/ +u32 CKCU_GetPeripFrequency(CKCU_PeripPrescaler_TypeDef Perip) +{ + CKCU_ClocksTypeDef Clock; + u32 PCLKPrescaler = 0; + #if (!LIBCFG_CKCU_NO_APB_PRESCALER) + u32 *PCSR = (u32 *)(&HT_CKCU->APBPCSR0 + (Perip >> CKCU_APBPCSR_OFFSET)); + + if (Perip == CKCU_PCLK_BKPR) + { + PCLKPrescaler = 2; + } + + Perip &= 0x0000001F; + PCLKPrescaler += CKCU_BF_READ(*PCSR, (3UL << Perip), Perip); + + #endif + CKCU_GetClocksFrequency(&Clock); + return (Clock.HCLK_Freq >> (PCLKPrescaler)); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the HSE Clock Monitor function. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_CKMCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_CKMEN, CKCU_POS_CKMEN, Cmd); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the power saving wakeup RC clock. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_PSRCWKUPCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BF_WRITE(HT_CKCU->GCCR, CKCU_MASK_PSRCEN, CKCU_POS_PSRCEN, Cmd); +} + +/*********************************************************************************************************//** + * @brief Select the output clock source through the CKOUT pin. + * @param CKOUTInit: pointer to CKCU_CKOUTInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_CKOUTConfig(CKCU_CKOUTInitTypeDef *CKOUTInit) +{ + CKCU_BF_WRITE(HT_CKCU->GCFGR, CKCU_MASK_CKOUTSRC, CKCU_POS_CKOUTSRC, CKOUTInit->CKOUTSRC); +} + +/*********************************************************************************************************//** + * @brief Check whether the specific CKCU interrupt has occurred or not. + * @param CKCU_INT: specify the CKCU interrupt source. + * This parameter can be any combination of the following values: + * @arg CKCU_INT_CKS: HSE clock failure interrupt flag (NMI) + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CKCU_GetIntStatus(u32 CKCU_INT) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_INT_FLAG(CKCU_INT)); + + if (HT_CKCU->GCIR & CKCU_INT) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the CKCU interrupt flag. + * @param CKCU_INT: specify the CKCU interrupt flag to clear. + * This parameter can be any combination of the following values: + * @arg CKCU_INT_CKS : HSE clock failure interrupt flag (NMI) + * @retval None + ************************************************************************************************************/ +void CKCU_ClearIntFlag(u32 CKCU_INT) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_INT_FLAG(CKCU_INT)); + + HT_CKCU->GCIR |= CKCU_INT; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specific CKCU interrupts. + * @param CKCU_INT: specify the CKCU interrupt source which is enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CKCU_INT_CKSIE : HSE clock failure interrupt (NMI) + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_IntConfig(u32 CKCU_INT, ControlStatus Cmd) +{ + u32 tmp1 = HT_CKCU->GCIR; + + /* Check the parameters */ + Assert_Param(IS_CKCU_INT(CKCU_INT)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + tmp1 |= CKCU_INT; + } + else + { + tmp1 &= ~CKCU_INT; + } + + /* Note: CKCU interrupt flags will be cleared by writing "1" */ + tmp1 &= ~0x00000001; + HT_CKCU->GCIR = tmp1; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the AHB peripheral clock during SLEEP mode. + * @param CKCU_CLK: specify the clock which is enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CKCU_AHBEN_SLEEP_FMC, CKCU_AHBEN_SLEEP_SRAM, CKCU_AHBEN_SLEEP_BM, CKCU_AHBEN_SLEEP_APB0, + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_SleepClockConfig(u32 CKCU_CLK, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_SLEEP_AHB(CKCU_CLK)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + HT_CKCU->AHBCCR |= CKCU_CLK; + } + else + { + HT_CKCU->AHBCCR &= ~CKCU_CLK; + } +} + +#if (!LIBCFG_NO_PLL) +/*********************************************************************************************************//** + * @brief Check if PLL clock used by the specific target source or not. + * @param Target: specify the target clock. + * This parameter can be one of the following values: + * @arg CKCU_PLLST_SYSCK : Is PLL used by system clock + * @arg CKCU_PLLST_USB : Is PLL used by USB + * @arg CKCU_PLLST_REFCK : Is PLL used by CK_REF + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_IS_PLL_USED(CKCU_PLLST_TypeDef Target) +{ + if ((HT_CKCU->CKST >> CKCU_POS_PLLST) & (u32)Target) + { + return TRUE; + } + else + { + return FALSE; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Check HSI clock used by the specific target source or not. + * @param Target: specify the target clock. + * This parameter can be one of the following values: + * @arg CKCU_HSIST_SYSCK : Is HSI used by system clock + * @arg CKCU_HSIST_PLL : Is HSI used by PLL + * @arg CKCU_HSIST_CKM : Is HSI used by clock monitor + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_IS_HSI_USED(CKCU_HSIST_TypeDef Target) +{ + if ((HT_CKCU->CKST >> CKCU_POS_HSIST) & (u32)Target) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/*********************************************************************************************************//** + * @brief Check HSE clock used by the specific target source or not. + * @param Target: specify the target clock. + * This parameter can be one of the following values: + * @arg CKCU_HSEST_SYSCK : Is HSE used by system clock + * @arg CKCU_HSEST_PLL : Is HSE used by PLL + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_IS_HSE_USED(CKCU_HSEST_TypeDef Target) +{ + if ((HT_CKCU->CKST >> CKCU_POS_HSEST) & (u32)Target) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specific debug function. + * @param CKCU_DBGx: specify the debug functions to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CKCU_DBG_SLEEP, CKCU_DBG_DEEPSLEEP1, CKCU_DBG_DEEPSLEEP2, CKCU_DBG_POWERDOWN, + * CKCU_DBG_MCTM0_HALT, + * CKCU_DBG_GPTM0_HALT, CKCU_DBG_GPTM1_HALT, + * CKCU_DBG_SCTM0_HALT, CKCU_DBG_SCTM1_HALT, CKCU_DBG_SCTM2_HALT, CKCU_DBG_SCTM3_HALT, + * CKCU_DBG_BFTM0_HALT, CKCU_DBG_BFTM1_HALT, + * CKCU_DBG_USART0_HALT, CKCU_DBG_USART1_HALT, + * CKCU_DBG_UART0_HALT, CKCU_DBG_UART1_HALT, CKCU_DBG_UART2_HALT, CKCU_DBG_UART3_HALT, + * CKCU_DBG_SPI0_HALT, CKCU_DBG_SPI1_HALT, CKCU_DBG_QSPI_HALT, + * CKCU_DBG_I2C0_HALT, CKCU_DBG_I2C1_HALT, CKCU_DBG_I2C2_HALT, + * CKCU_DBG_CAN0_HALT + * CKCU_DBG_SCI0_HALT, CKCU_DBG_SCI1_HALT, + * CKCU_DBG_WDT_HALT, + * CKCU_DBG_PWM0_HALT, CKCU_DBG_PWM1_HALT, CKCU_DBG_PWM2_HALT, + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_MCUDBGConfig(u32 CKCU_DBGx, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CKCU_DBG(CKCU_DBGx)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + HT_CKCU->MCUDBGCR |= CKCU_DBGx; + } + else + { + HT_CKCU->MCUDBGCR &= ~CKCU_DBGx; + } +} + +#if (!LIBCFG_CKCU_NO_LPCR) +/*********************************************************************************************************//** + * @brief Enable or Disable the Backup domain isolation control. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_BKISOCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + /* DISABLE: Backup domain is isolated */ + CKCU_BF_WRITE(HT_CKCU->LPCR, CKCU_MASK_BKISO, CKCU_POS_BKISO, !Cmd); +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the peripheral clock. + * @param Clock: specify the peripheral clock enable bits. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_PeripClockConfig(CKCU_PeripClockConfig_TypeDef Clock, ControlStatus Cmd) +{ + u32 uAHBCCR; + u32 uAPBCCR0; + u32 uAPBCCR1; + + uAHBCCR = HT_CKCU->AHBCCR; + uAPBCCR0 = HT_CKCU->APBCCR0; + uAPBCCR1 = HT_CKCU->APBCCR1; + + uAHBCCR &= ~(Clock.Reg[0]); + uAPBCCR0 &= ~(Clock.Reg[1]); + uAPBCCR1 &= ~(Clock.Reg[2]); + + if (Cmd != DISABLE) + { + uAHBCCR |= Clock.Reg[0]; + uAPBCCR0 |= Clock.Reg[1]; + uAPBCCR1 |= Clock.Reg[2]; + } + + HT_CKCU->AHBCCR = uAHBCCR; + HT_CKCU->APBCCR0 = uAPBCCR0; + HT_CKCU->APBCCR1 = uAPBCCR1; +} + +#if (((LIBCFG_LSE) || (LIBCFG_USBD)) && (!LIBCFG_CKCU_NO_AUTO_TRIM)) +/*********************************************************************************************************//** + * @brief Configure the reference clock of HSI auto-trim function. + * @param CLKSRC: specify the clock source. + * This parameter can be: + * @arg CKCU_ATC_LSE: LSE is selected as reference clock + * @arg CKCU_ATC_USB: USB is selected as reference clock + * @arg CKCU_ATC_CKIN: External pin (CKIN) is selected as reference clock + * @retval None + ************************************************************************************************************/ +void CKCU_HSIAutoTrimClkConfig(CKCU_ATC_TypeDef CLKSRC) +{ + CKCU_BF_WRITE(HT_CKCU->HSICR, CKCU_MASK_REFCLKSEL, CKCU_POS_REFCLKSEL, CLKSRC); +} + +#if (LIBCFG_CKCU_ATM_V01) +/*********************************************************************************************************//** + * @brief Initialize the ATC according to the specified parameters in the ATC_InitStruct. + * @param ATC_InitStruct: pointer to a CKCU_ATCInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CKCU_ATCInit(CKCU_ATCInitTypeDef* ATC_InitStruct) +{ + HT_CKCU->HSICR &= 0xFFFFFFF3; + HT_CKCU->HSICR |= (u32)ATC_InitStruct->SearchAlgorithm | (u32)ATC_InitStruct->FrqTolerance; +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the HSI auto-trim function. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CKCU_HSIAutoTrimCmd(ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + CKCU_BF_WRITE(HT_CKCU->HSICR, CKCU_MASK_TRIMEN, CKCU_POS_TRIMEN, Cmd); + CKCU_BF_WRITE(HT_CKCU->HSICR, CKCU_MASK_ATCEN, CKCU_POS_ATCEN, Cmd); +} + +/*********************************************************************************************************//** + * @brief Check Auto Trim is ready or not. + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool CKCU_HSIAutoTrimIsReady(void) +{ +#if (LIBCFG_CKCU_AUTO_TRIM_LEGACY) + u32 lower_bound, upper_bound, i; + static u32 ATCR = 0; + + if ((HT_CKCU->HSICR & (3ul << 5)) == 0) + { + lower_bound = 7812 - 19; + upper_bound = 7812 + 19; + } + else + { + lower_bound = 8000 - 20; + upper_bound = 8000 + 20; + } + + SystemCoreClockUpdate(); + for (i = SystemCoreClock / 8000; i > 0; i--){}; + ATCR += HT_CKCU->HSIATCR; + ATCR /= 2; + + if ((ATCR >= lower_bound) && (ATCR <= upper_bound)) + { + ATCR = 0; + return TRUE; + } + else + { + return FALSE; + } + +#else + return (HT_CKCU->HSICR & 0x80) ? TRUE : FALSE; +#endif +} +#endif + +#if (LIBCFG_CKCU_HSIRDYCR) +/*********************************************************************************************************//** + * @brief Set HSI Ready Counter Value. + * @param Value: 0x0~0x1F. + * @retval None + ************************************************************************************************************/ +void CKCU_Set_HSIReadyCounter(u8 Value) +{ + /* Check the parameters */ + Assert_Param(IS_COUNTER_VALUE(Value)); + + HT_CKCU->HSIRDYCR = ((HT_CKCU->HSIRDYCR) & (~(0x1F))) | Value; +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_cmp.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_cmp.c new file mode 100644 index 00000000000..10f4b9dded7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_cmp.c @@ -0,0 +1,336 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_cmp.c + * @version $Rev:: 6932 $ + * @date $Date:: 2023-05-11 #$ + * @brief This file provides all the CMP firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_cmp.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CMP CMP + * @brief CMP driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CMP_Exported_Functions CMP exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CMP0 and CMP1 peripheral registers to their default reset values. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @retval None + ************************************************************************************************************/ +void CMP_DeInit(HT_CMP_TypeDef* HT_CMPn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + if (HT_CMPn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.CMP = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Unprotect the selected comparator configuration before setting the Comparator Control Register. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @retval None + ************************************************************************************************************/ +void CMP_UnprotectConfig(HT_CMP_TypeDef* HT_CMPn) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + + /* Set the unlock code corresponding to selected comparator */ + HT_CMPn->CR = CMP_PROTECT_KEY; +} + +/*********************************************************************************************************//** + * @brief Initialize the CMP peripheral according to the specified parameters in the CMP_InitStruct. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_InitStruct: pointer to a CMP_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CMP_Init(HT_CMP_TypeDef* HT_CMPn, CMP_InitTypeDef* CMP_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_Wakeup_Set(CMP_InitStruct->CMP_Wakeup)); + Assert_Param(IS_CMP_OutputSelection(CMP_InitStruct->CMP_OutputSelection)); + Assert_Param(IS_CMP_ScalerSource(CMP_InitStruct->CMP_ScalerSource)); + Assert_Param(IS_CMP_ScalerOutputBuf(CMP_InitStruct->CMP_ScalerOutputBuf)); + Assert_Param(IS_CMP_ScalerEnable(CMP_InitStruct->CMP_ScalerEnable)); + Assert_Param(IS_CMP_CoutSynchronized(CMP_InitStruct->CMP_CoutSync)); + Assert_Param(IS_CMP_OutputPol_Set(CMP_InitStruct->CMP_OutputPol)); + #if (LIBCFG_CMP_65x_VER) + Assert_Param(IS_CMP_InputSelection(CMP_InitStruct->CMP_InputSelection)); + #endif + Assert_Param(IS_CMP_InvInputSelection(CMP_InitStruct->CMP_InvInputSelection)); + Assert_Param(IS_CMP_Hysteresis_Set(CMP_InitStruct->CMP_Hysteresis)); + Assert_Param(IS_CMP_Speed_Set(CMP_InitStruct->CMP_Speed)); + + HT_CMPn->CR |= CMP_InitStruct->CMP_Wakeup | CMP_InitStruct->CMP_OutputSelection | CMP_InitStruct->CMP_ScalerSource | \ + CMP_InitStruct->CMP_ScalerOutputBuf | CMP_InitStruct->CMP_ScalerEnable | CMP_InitStruct->CMP_CoutSync | \ + CMP_InitStruct->CMP_OutputPol | CMP_InitStruct->CMP_InvInputSelection | CMP_InitStruct->CMP_Hysteresis | \ + CMP_InitStruct->CMP_Speed; + + #if (LIBCFG_CMP_65x_VER) + HT_CMPn->CI = CMP_InitStruct->CMP_InputSelection; + #endif +} + +/*********************************************************************************************************//** + * @brief Fill each CMP_InitStruct member with its default value. + * @param CMP_InitStruct: pointer to an CMP_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CMP_StructInit(CMP_InitTypeDef* CMP_InitStruct) +{ + /* CMP_InitStruct members default value */ + CMP_InitStruct->CMP_Wakeup = CMP_WUP_DISABLE; + CMP_InitStruct->CMP_OutputSelection = CMP_TRIG_NONE; + #if (LIBCFG_CMP_NOSCALER_SRC) + CMP_InitStruct->CMP_ScalerSource = 0; + #else + CMP_InitStruct->CMP_ScalerSource = CMP_SCALER_SRC_VDDA; + #endif + CMP_InitStruct->CMP_ScalerOutputBuf = CMP_SCALER_OBUF_DISABLE; + CMP_InitStruct->CMP_ScalerEnable = CMP_SCALER_DISABLE; + CMP_InitStruct->CMP_CoutSync = CMP_ASYNC_OUTPUT; + CMP_InitStruct->CMP_OutputPol = CMP_NONINV_OUTPUT; + CMP_InitStruct->CMP_InvInputSelection = CMP_EXTERNAL_CN_IN; + CMP_InitStruct->CMP_Hysteresis = CMP_NO_HYSTERESIS; + CMP_InitStruct->CMP_Speed = CMP_LOW_SPEED; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP peripheral. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CMP_Cmd(HT_CMP_TypeDef* HT_CMPn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CMPn->CR |= CMP_ENABLE; + } + else + { + HT_CMPn->CR &= ~(u32)CMP_ENABLE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP interrupts. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_INT_x: specify the CMP interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CMP_INT_RE : CMP rising edge interrupt + * @arg CMP_INT_FE : CMP falling edge interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CMP_IntConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_INT(CMP_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CMPn->IER |= CMP_INT_x; + } + else + { + HT_CMPn->IER &= ~CMP_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified CMP edge detection. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_xE_Detect: specify the CMP edge detection that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CMP_RE_Detect : CMP rising edge detection + * @arg CMP_FE_Detect : CMP falling edge detection + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void CMP_EdgeDetectConfig(HT_CMP_TypeDef* HT_CMPn, u32 CMP_xE_Detect, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_EdgeDetect(CMP_xE_Detect)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_CMPn->TFR = (HT_CMPn->TFR | CMP_xE_Detect) & 0xfffffffc; + } + else + { + HT_CMPn->TFR = (HT_CMPn->TFR & (~CMP_xE_Detect)) & 0xfffffffc; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified CM flag has been set. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_FLAG_x: specify the flag to be checked. + * This parameter can be any combination of the following values: + * @arg CMP_FLAG_RE : CMP rising edge flag + * @arg CMP_FLAG_FE : CMP falling edge flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CMP_GetFlagStatus(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_FLAG(CMP_FLAG_x)); + + if ((HT_CMPn->TFR & CMP_FLAG_x) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear flags of the specified CMP. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param CMP_FLAG_x: specify the flag to be checked. + * This parameter can be any combination of the following values: + * @arg CMP_FLAG_RE : CMP rising edge flag + * @arg CMP_FLAG_FE : CMP falling edge flag + * @retval None + ************************************************************************************************************/ +void CMP_ClearFlag(HT_CMP_TypeDef* HT_CMPn, u32 CMP_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_FLAG(CMP_FLAG_x)); + + /* Clear the flags */ + HT_CMPn->TFR = (HT_CMPn->TFR & 0xfffffffc) | CMP_FLAG_x; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Get the output status of the specified CMP. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus CMP_GetOutputStatus(HT_CMP_TypeDef* HT_CMPn) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + + if ((HT_CMPn-> CR & CMP_OUTPUT_HIGH) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified reference value in the data register of the scaler. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param Scaler_Value: value to be loaded in the selected data register + * @retval None + ************************************************************************************************************/ +void CMP_SetScalerValue(HT_CMP_TypeDef* HT_CMPn, u8 Scaler_Value) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_SCALER_VALUE(Scaler_Value)); + + /* Set the scaler reference value register */ + HT_CMPn->VALR = (u32)Scaler_Value; +} + +#if (LIBCFG_CMP_CO) +/*********************************************************************************************************//** + * @brief Select the synchronous source with the CMPnO signal. + * @param HT_CMPn: where HT_CMPn is the selected CMP from the CMP peripherals. + * @param uCOUTSEL: Comparator Sync Output Select. + * This parameter can be one of the following value: + * @arg CMP_SYNCOUT_CMPnO : + * @arg CMP_SYNCOUT_MCTM_CH0O : + * @arg CMP_SYNCOUT_MCTM_CH0NO : + * @arg CMP_SYNCOUT_MCTM_CH1O : + * @arg CMP_SYNCOUT_MCTM_CH1NO : + * @arg CMP_SYNCOUT_MCTM_CH2O : + * @arg CMP_SYNCOUT_MCTM_CH2NO : + * @arg CMP_SYNCOUT_MCTM_CH3O : + * @arg CMP_SYNCOUT_MCTM_CH3OB : + * @retval None + ************************************************************************************************************/ +void CMP_Output_SyncSource_Select(HT_CMP_TypeDef* HT_CMPn, CMP_SYNCOUT_Enum CMP_SYNCOUT_x) +{ + /* Check the parameters */ + Assert_Param(IS_CMP(HT_CMPn)); + Assert_Param(IS_CMP_SYNC_SOURCE(CMP_SYNCOUT_x)); + + HT_CMPn->CO = (HT_CMPn->CO & 0xFFFFFFF0) | CMP_SYNCOUT_x; +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_crc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_crc.c new file mode 100644 index 00000000000..04da8291949 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_crc.c @@ -0,0 +1,190 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_crc.c + * @version $Rev:: 5483 $ + * @date $Date:: 2021-07-19 #$ + * @brief This file provides all the CRC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_crc.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the CRC peripheral registers to their default reset values. + * @param HT_CRCn: where CRC is the selected CRC peripheral. + * @retval None + ************************************************************************************************************/ +void CRC_DeInit(HT_CRC_TypeDef* HT_CRCn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + if (HT_CRCn == NULL) // Remove the compiler warning + { + } + + RSTCUReset.Bit.CRC = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the CRC peripheral according to the specified parameters in the CRC_InitStruct. + * @param HT_CRCn: Selected CRC peripheral. + * @param CRC_InitStruct: pointer to a CRC_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void CRC_Init(HT_CRC_TypeDef* HT_CRCn, CRC_InitTypeDef* CRC_InitStruct) +{ + u32 uCRValue; + HT_CRCn->SDR = CRC_InitStruct->uSeed; + switch (CRC_InitStruct->Mode) + { + case CRC_CCITT_POLY: + { + uCRValue = CRC_CCITT_POLY | CRC_NORMAL_WR | CRC_NORMAL_SUM; + break; + } + case CRC_16_POLY: + { + uCRValue = CRC_16_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM; + break; + } + case CRC_32_POLY: + { + uCRValue = CRC_32_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM | CRC_CMPL_SUM; + break; + } + case CRC_USER_DEFINE: + default: + { + uCRValue = CRC_InitStruct->uCR; + break; + } + } + + HT_CRCn->CR = uCRValue; +} + +/*********************************************************************************************************//** + * @brief Get the CRC checksum from the given data + * @param HT_CRCn: Selected CRC peripheral. + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ***********************************************************************************************************/ +u32 CRC_Process(HT_CRC_TypeDef* HT_CRCn, u8 *buffer, u32 length) +{ + while (length--) + { + wb(&HT_CRCn->DR, *buffer++); // byte write + } + + return (HT_CRCn->CSR); +} + +/*********************************************************************************************************//** + * @brief Get the CRC-CCITT checksum from the given data + * @param seed: CRC initial data + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ************************************************************************************************************/ +u16 CRC_CCITT(u16 seed, u8 *buffer, u32 length) +{ + /* CRC-CCITT poly: 0x1021 */ + HT_CRC->SDR = seed; + HT_CRC->CR = CRC_CCITT_POLY | CRC_NORMAL_WR | CRC_NORMAL_SUM; + + while (length--) + { + wb(&HT_CRC->DR, *buffer++); // byte write + } + + return (u16)(HT_CRC->CSR); +} + +/*********************************************************************************************************//** + * @brief Get the CRC-16 checksum from the given data + * @param seed: CRC initial data + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ************************************************************************************************************/ +u16 CRC_16(u16 seed, u8 *buffer, u32 length) +{ + /* CRC-16 poly: 0x8005 */ + HT_CRC->SDR = seed; + HT_CRC->CR = CRC_16_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM; + + while (length--) + { + wb(&HT_CRC->DR, *buffer++); // byte write + } + + return (u16)(HT_CRC->CSR); +} + +/*********************************************************************************************************//** + * @brief Get the CRC-32 checksum from the given data + * @param seed: CRC initial data + * @param buffer: pointer to the given data to be calculated + * @param length: data length in byte + * @retval The checksum value + ************************************************************************************************************/ +u32 CRC_32(u32 seed, u8 *buffer, u32 length) +{ + /* CRC-32 poly: 0x04C11DB7 */ + HT_CRC->SDR = seed; + HT_CRC->CR = CRC_32_POLY | CRC_BIT_RVS_WR | CRC_BIT_RVS_SUM | CRC_BYTE_RVS_SUM | CRC_CMPL_SUM; + + while (length--) + { + wb(&HT_CRC->DR, *buffer++); // byte write + } + + return (HT_CRC->CSR); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac.c new file mode 100644 index 00000000000..e209d4c1a04 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac.c @@ -0,0 +1,249 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_dac.c + * @version $Rev:: 7081 $ + * @date $Date:: 2023-08-01 #$ + * @brief This file provides all the DAC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_dac.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup DAC DAC + * @brief DAC driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup DAC_Exported_Functions DAC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the HT_DACn peripheral registers to their default reset values. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @retval None + ************************************************************************************************************/ +void DAC_DeInit(HT_DAC_TypeDef* HT_DACn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + + if (HT_DACn == HT_DAC0) + { + RSTCUReset.Bit.DAC0 = 1; + } + #if (LIBCFG_DAC1) + else if (HT_DACn == HT_DAC1) + { + RSTCUReset.Bit.DAC1 = 1; + } + #endif + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure the DAC conversion mode. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @param ModeSel: specify the conversion mode + * This parameter can be one of the following values: + * @arg ASYNC_MODE : asynchronous conversion mode + * @arg SYNC_MODE : synchronous conversion mode + * @retval None + ************************************************************************************************************/ +void DAC_ModeConfig(HT_DAC_TypeDef* HT_DACn, u8 ModeSel) +{ + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + Assert_Param(IS_DAC_CONVERSION_MODE(ModeSel)); + + HT_DACn->CFGR = ModeSel; +} + +/*********************************************************************************************************//** + * @brief Configure the specified DAC channel reference voltage. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @param DAC_Ch: the DAC channel to configure +* This parameter can be one of the following values: +* @arg DAC_CH0 : DAC channel 0 +* @arg DAC_CH1 : DAC channel 1 + * @param RefSel: DAC reference voltage source + * This parameter can be one of the following values: + * @arg DAC_REFERENCE_VDDA : VDDA + * @arg DAC_REFERENCE_VREF : VREF + * @retval None + ************************************************************************************************************/ +void DAC_ReferenceConfig(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 RefSel) +{ + HT_DACCH_TypeDef *DACnCH = (HT_DACCH_TypeDef *)((u32)&HT_DACn->DACCH0 + DAC_Ch * 8 * 4); + + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + Assert_Param(IS_DAC_CHANNEL(DAC_Ch)); + Assert_Param(IS_DAC_REFERENCE(RefSel)); + + DACnCH->CR = (DACnCH->CR & ~(3UL << 14)) | RefSel; +} + +/*********************************************************************************************************//** + * @brief Configure the specified DAC channel resolution. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @param DAC_Ch: the DAC channel to configure +* This parameter can be one of the following values: +* @arg DAC_CH0 : DAC channel 0 +* @arg DAC_CH1 : DAC channel 1 + * @param ResoSel: DAC Channel Resolution + * This parameter can be one of the following values: + * @arg DAC_RESOLUTION_8BIT : 8-bit resolution + * @arg DAC_RESOLUTION_12BIT : 12-bit resolution + * @retval None + ************************************************************************************************************/ +void DAC_ResolutionConfig(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 ResoSel) +{ + HT_DACCH_TypeDef *DACnCH = (HT_DACCH_TypeDef *)((u32)&HT_DACn->DACCH0 + DAC_Ch * 8 * 4); + + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + Assert_Param(IS_DAC_CHANNEL(DAC_Ch)); + Assert_Param(IS_DAC_RESOLUTION(ResoSel)); + + DACnCH->CR = (DACnCH->CR & ~(1UL << 2)) | ResoSel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified DAC Channel output buffer. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @param DAC_Ch: the DAC channel to configure +* This parameter can be one of the following values: +* @arg DAC_CH0 : DAC channel 0 +* @arg DAC_CH1 : DAC channel 1 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void DAC_OutBufCmd(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, ControlStatus NewState) +{ + HT_DACCH_TypeDef *DACnCH = (HT_DACCH_TypeDef *)((u32)&HT_DACn->DACCH0 + DAC_Ch * 8 * 4); + + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + Assert_Param(IS_DAC_CHANNEL(DAC_Ch)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + DACnCH->CR = (DACnCH->CR & ~(3UL << 6)) | (2UL << 6); + } + else + { + DACnCH->CR = (DACnCH->CR & ~(3UL << 6)) | (1UL << 6); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified DAC channel. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @param DAC_Ch: the DAC channel to configure +* This parameter can be one of the following values: +* @arg DAC_CH0 : DAC channel 0 +* @arg DAC_CH1 : DAC channel 1 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void DAC_Cmd(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, ControlStatus NewState) +{ + HT_DACCH_TypeDef *DACnCH = (HT_DACCH_TypeDef *)((u32)&HT_DACn->DACCH0 + DAC_Ch * 8 * 4); + + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + Assert_Param(IS_DAC_CHANNEL(DAC_Ch)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SetBit_BB((u32)&DACnCH->CR, 0); + } + else + { + ResetBit_BB((u32)&DACnCH->CR, 0); + } +} + +/*********************************************************************************************************//** + * @brief Set the data holding register value for the specified DAC channel. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @param DAC_Ch: the DAC channel to configure +* This parameter can be one of the following values: +* @arg DAC_CH0 : DAC channel 0 +* @arg DAC_CH1 : DAC channel 1 + * @param Data: next conversion data. + * @retval None + ************************************************************************************************************/ +void DAC_SetData(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch, u32 Data) +{ + HT_DACCH_TypeDef *DACnCH = (HT_DACCH_TypeDef *)((u32)&HT_DACn->DACCH0 + DAC_Ch * 8 * 4); + + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + Assert_Param(IS_DAC_CHANNEL(DAC_Ch)); + + DACnCH->DHR = Data; +} + +/*********************************************************************************************************//** + * @brief Return the data output register value of the specified DAC channel. + * @param HT_DACn: where HT_DACn is the selected DAC from the DAC peripherals. + * @param DAC_Ch: the DAC channel to configure +* This parameter can be one of the following values: +* @arg DAC_CH0 : DAC channel 0 +* @arg DAC_CH1 : DAC channel 1 + * @return The selected DAC channel data output value. + ************************************************************************************************************/ +u16 DAC_GetOutData(HT_DAC_TypeDef* HT_DACn, u8 DAC_Ch) +{ + HT_DACCH_TypeDef *DACnCH = (HT_DACCH_TypeDef *)((u32)&HT_DACn->DACCH0 + DAC_Ch * 8 * 4); + + /* Check the parameters */ + Assert_Param(IS_DAC(HT_DACn)); + Assert_Param(IS_DAC_CHANNEL(DAC_Ch)); + + return ((u16)DACnCH->DOR); +} + + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac_dual16.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac_dual16.c new file mode 100644 index 00000000000..d08f0e0e78f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_dac_dual16.c @@ -0,0 +1,191 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_dac_dual16.c + * @version $Rev:: 7071 $ + * @date $Date:: 2023-07-28 #$ + * @brief This file provides all the DAC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_dac_dual16.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup DAC_DUAL16 DAC_DUAL16 + * @brief DAC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup DAC_DUAL16_Private_Define DAC private definitions + * @{ + */ +#define DAC_POS_RCH 0 +#define DAC_POS_LCH 8 + +#define DAC_TRIG_SOFTWARE_RESET (0x00000000) +#define DAC_TRIG_SOFTWARE_SET (0x00000001) + +#define DAC_RCH_RESET (0xFFFFFFFE) +#define DAC_LCH_RESET (0xFFFFFEFF) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup DAC_DUAL16_Private_Macro DAC private macros + * @{ + */ +#define IS_DAC(x) (x == HT_DACDUAL16) + +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CH_R) || \ + ((CHANNEL) == DAC_CH_L)) + +#define IS_DAC_DATA_SOURCE(SOURCE) (((SOURCE) == DATA_FROM_UC) || \ + ((SOURCE) == DATA_FROM_MIDI)) + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFFF) +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup DAC_DUAL16_Exported_Functions DAC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the DAC peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void DACD16_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.DAC0 = 1; + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure the data source for the DAC channel. + * @param DACx: where DACx is the selected DAC from the DAC peripherals. + * @param DAC_CH_x: the DAC channel to configure + * This parameter can be one of the following values: + * @arg DAC_CH_R : DAC Right Channel selected + * @arg DAC_CH_L : DAC Left Channel selected + * @param DATA_FROM_x: Configure the data source. + * This parameter can be one of the following values: + * @arg DATA_FROM_UC : data and control signal from uC + * @arg DATA_FROM_MIDI : data and control signal from MIDI + * @retval None + ************************************************************************************************************/ +void DACD16_DataSourceConfig(HT_DAC_DUAL16_TypeDef* DACx, DAC_Dual16_Ch DAC_CH_x, DAC_Dual16_Source DATA_FROM_x) +{ + /* Check the parameters */ + Assert_Param(IS_DAC(DACx)); + Assert_Param(IS_DAC_CHANNEL(DAC_CH_x)); + Assert_Param(IS_DAC_DATA_SOURCE(DATA_FROM_x)); + + /* Set the select channel data source */ + if (DAC_CH_x == DAC_CH_R) + { + DACx->CR &= DAC_RCH_RESET; + DACx->CR |= DATA_FROM_x << DAC_POS_RCH; + } + else + { + DACx->CR &= DAC_LCH_RESET; + DACx->CR |= DATA_FROM_x << DAC_POS_LCH; + } +} + +/*********************************************************************************************************//** + * @brief Configure the data source for the DAC channel. + * @param DACx: where DACx is the selected DAC from the DAC peripherals. + * @param DAC_CH_x: the DAC channel to configure + * This parameter can be one of the following values: + * @arg DAC_CH_R : DAC Right Channel selected + * @arg DAC_CH_L : DAC Left Channel selected + * @param Data : Data to be loaded in the selected channel data register. + * @retval None + ************************************************************************************************************/ +void DACD16_SetChannelData(HT_DAC_DUAL16_TypeDef* DACx, DAC_Dual16_Ch DAC_CH_x, u16 Data) +{ + /* Check the parameters */ + Assert_Param(IS_DAC(DACx)); + Assert_Param(IS_DAC_CHANNEL(DAC_CH_x)); + Assert_Param(IS_DAC_DATA(Data)); + + /* Set the select channel data */ + if (DAC_CH_x == DAC_CH_R) + { + DACx->RH = Data; + } + else + { + DACx->LH = Data; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable software start of the channel conversion of the selected DAC . + * @param DACx: where DACx is the selected DAC from the DAC peripherals. + * @param DAC_CH_x: the DAC channel to configure + * This parameter can be one of the following values: + * @arg DAC_CH_R : DAC Right Channel selected + * @arg DAC_CH_L : DAC Left Channel selected + * @retval None + ************************************************************************************************************/ +void DACD16_SoftwareStartConvCmd(HT_DAC_DUAL16_TypeDef* DACx, DAC_Dual16_Ch DAC_CH_x) +{ + /* Check the parameters */ + Assert_Param(IS_DAC(DACx)); + Assert_Param(IS_DAC_CHANNEL(DAC_CH_x)); + + /* Start Conversion */ + if (DAC_CH_x == DAC_CH_R) + { + DACx->TG &= DAC_RCH_RESET ; + DACx->TG |= DAC_TRIG_SOFTWARE_SET << DAC_POS_RCH; + } + else + { + DACx->TG &= DAC_LCH_RESET; + DACx->TG |= DAC_TRIG_SOFTWARE_SET << DAC_POS_LCH; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_div.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_div.c new file mode 100644 index 00000000000..6e596480d34 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_div.c @@ -0,0 +1,211 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_div.c + * @version $Rev:: 6656 $ + * @date $Date:: 2023-01-16 #$ + * @brief This file provides all the DIV firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_div.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup DIV DIV + * @brief DIV driver modules + * @{ + */ + +/* Private constants ---------------------------------------------------------------------------------------*/ +#define DIVCR_START (0x00000001) +#define DIVCR_ZEF (0x00000004) +#define DIVCR_COM (0x00000008) + +/* Global variables ----------------------------------------------------------------------------------------*/ +u32 guRemainder; + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup DIV_Exported_Functions DIV exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the DIV peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void DIV_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.DIV = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Calculate the Quotient of dividend/divisor. + * @param dividend + * @param divisor + * @retval The quotient of dividend/divisor + ************************************************************************************************************/ +s32 DIV_Div32(s32 dividend, s32 divisor) +{ + HT_DIV->DDR = dividend; + HT_DIV->DSR = divisor; + HT_DIV->CR = DIVCR_START; + + while ((HT_DIV->CR & DIVCR_COM) != DIVCR_COM); + + #if (DIV_ENABLE_DIVIDE_BY_ZERO_CHECK == 1) + { + if (DIV_IsDivByZero() == TRUE) + { + while (1); + } + } + #endif + + return (HT_DIV->QTR); +} + +/*********************************************************************************************************//** + * @brief Calculate the 32-bit unsigned of dividend/divisor. + * @param dividend + * @param divisor + * @retval The quotient of dividend/divisor + ************************************************************************************************************/ +u32 DIV_uDiv32(u32 dividend, u32 divisor) +{ + u32 uResult = 0; + guRemainder = 0; + if (dividend < divisor) + { + guRemainder = dividend; + return 0; + } + + if (dividend == divisor) + { + return 1; + } + + if (divisor & 0x80000000) + { + guRemainder = dividend - divisor; + return 1; + } + + if (dividend & 0x80000000) + { + HT_DIV->DDR = 0x7FFFFFFF; + HT_DIV->DSR = divisor; + HT_DIV->CR = DIVCR_START; + + while ((HT_DIV->CR & DIVCR_COM) != DIVCR_COM); + #if (DIV_ENABLE_DIVIDE_BY_ZERO_CHECK == 1) + { + if (DIV_IsDivByZero() == TRUE) + { + while (1); + } + } + #endif + + uResult = HT_DIV->QTR; + guRemainder = HT_DIV->RMR; + dividend -= 0x7FFFFFFF; + } + + HT_DIV->DDR = dividend; + HT_DIV->DSR = divisor; + HT_DIV->CR = DIVCR_START; + + while ((HT_DIV->CR & DIVCR_COM) != DIVCR_COM); + #if (DIV_ENABLE_DIVIDE_BY_ZERO_CHECK == 1) + { + if (DIV_IsDivByZero() == TRUE) + { + while (1); + } + } + #endif + + uResult += HT_DIV->QTR; + guRemainder += HT_DIV->RMR; + + if (guRemainder >= divisor) + { + guRemainder -= divisor; + uResult++; + } + + return uResult; +} + +/*********************************************************************************************************//** + * @brief Retuen the remainder of last unsigned dividend/divisor calculatation. + * @retval guRemainder: The remainder of dividend/divisor + ************************************************************************************************************/ +u32 DIV_uGetLastRemainder(void) +{ + return guRemainder; +} + +/*********************************************************************************************************//** + * @brief Calculate the remainder of dividend/divisor. + * @param dividend + * @param divisor + * @retval The remainder of dividend/divisor + ************************************************************************************************************/ +s32 DIV_Mod(s32 dividend, s32 divisor) +{ + DIV_Div32(dividend, divisor); + + return (HT_DIV->RMR); +} + +/*********************************************************************************************************//** + * @brief Get Divide by Zero Case. + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool DIV_IsDivByZero(void) +{ + if ((HT_DIV->CR & DIVCR_ZEF) == DIVCR_ZEF) + { + return TRUE; + } + + return FALSE; +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ebi.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ebi.c new file mode 100644 index 00000000000..2ea64162cdd --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ebi.c @@ -0,0 +1,189 @@ +/********************************************************************************************************//** + * @file ht32f5xxxx_ebi.c + * @version $Rev:: 2772 $ + * @date $Date:: 2018-05-15 #$ + * @brief This file provides all the EBI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_ebi.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup EBI EBI + * @brief EBI driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup EBI_Exported_Functions EBI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitializes the EBI peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void EBI_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.EBI = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initializes the EBI peripheral according to the specified parameters in the EBI_InitStruct. + * @param EBI_InitStruct: pointer to a EBI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void EBI_Init(EBI_InitTypeDef* EBI_InitStruct) +{ + u32 tmp; + u32 bank = EBI_InitStruct->EBI_Bank; + + /* Check the parameters */ + Assert_Param(IS_EBI_BANK(EBI_InitStruct->EBI_Bank)); + Assert_Param(IS_EBI_MODE(EBI_InitStruct->EBI_Mode)); + Assert_Param(IS_EBI_IDLECYCLE(EBI_InitStruct->EBI_IdleCycle)); + Assert_Param(IS_EBI_CS_POLARITY(EBI_InitStruct->EBI_ChipSelectPolarity)); + Assert_Param(IS_EBI_ALE_POLARITY(EBI_InitStruct->EBI_AddressLatchPolarity)); + Assert_Param(IS_EBI_WE_POLARITY(EBI_InitStruct->EBI_WriteEnablePolarity)); + Assert_Param(IS_EBI_RE_POLARITY(EBI_InitStruct->EBI_ReadEnablePolarity)); + Assert_Param(IS_EBI_IDLE_CYCLE_TIME(EBI_InitStruct->EBI_IdleCycleTime)); + Assert_Param(IS_EBI_ADDRESS_SETUP_TIME(EBI_InitStruct->EBI_AddressSetupTime)); + Assert_Param(IS_EBI_ADDRESS_HOLD_TIME(EBI_InitStruct->EBI_AddressHoldTime)); + Assert_Param(IS_EBI_WRITE_SETUP_TIME(EBI_InitStruct->EBI_WriteSetupTime)); + Assert_Param(IS_EBI_WRITE_STROBE_TIME(EBI_InitStruct->EBI_WriteStrobeTime)); + Assert_Param(IS_EBI_WRITE_HOLD_TIME(EBI_InitStruct->EBI_WriteHoldTime)); + Assert_Param(IS_EBI_READ_SETUP_TIME(EBI_InitStruct->EBI_ReadSetupTime)); + Assert_Param(IS_EBI_READ_STROBE_TIME(EBI_InitStruct->EBI_ReadStrobeTime)); + + HT_EBI->ATR = EBI_InitStruct->EBI_AddressSetupTime | + (EBI_InitStruct->EBI_AddressHoldTime << 8); + HT_EBI->RTR = EBI_InitStruct->EBI_ReadSetupTime | + (EBI_InitStruct->EBI_ReadStrobeTime << 8) | + (EBI_InitStruct->EBI_ReadHoldTime << 16); + + HT_EBI->WTR = EBI_InitStruct->EBI_WriteSetupTime | + (EBI_InitStruct->EBI_WriteStrobeTime << 8) | + (EBI_InitStruct->EBI_WriteHoldTime << 16); + HT_EBI->PR = EBI_InitStruct->EBI_ChipSelectPolarity | + (EBI_InitStruct->EBI_ReadEnablePolarity << 1) | + (EBI_InitStruct->EBI_WriteEnablePolarity << 2) | + (EBI_InitStruct->EBI_AddressLatchPolarity << 3); + + + /*------------------------- EBI Control Register Configuration -------------------------------------------*/ + tmp = (3 << (bank * 2)) | (0x00001000 << bank) | + (0x00010000 << (bank * 2)) | (0x00020000 << (bank * 2)) | + (0x01000000 << bank); + tmp = HT_EBI->CR & (~tmp); + HT_EBI->CR = (EBI_InitStruct->EBI_Mode << (bank * 2)) | + (EBI_InitStruct->EBI_IdleCycle << bank) | + (EBI_InitStruct->EBI_IdleCycleTime << 28) | tmp; +} + +/*********************************************************************************************************//** + * @brief Fills each EBI_InitStruct member with its default value. + * @param EBI_InitStruct: pointer to an EBI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void EBI_StructInit(EBI_InitTypeDef* EBI_InitStruct) +{ + /* Initialize the EBI structure parameters values */ + EBI_InitStruct->EBI_Bank = EBI_BANK_0; + EBI_InitStruct->EBI_Mode = EBI_MODE_D8A8; + EBI_InitStruct->EBI_IdleCycle = EBI_IDLECYCLE_DISABLE; + EBI_InitStruct->EBI_ChipSelectPolarity = EBI_CHIPSELECTPOLARITY_LOW; + EBI_InitStruct->EBI_AddressLatchPolarity = EBI_ADDRESSLATCHPOLARITY_LOW; + EBI_InitStruct->EBI_WriteEnablePolarity = EBI_WRITEENABLEPOLARITY_LOW; + EBI_InitStruct->EBI_ReadEnablePolarity = EBI_READENABLEPOLARITY_LOW; + EBI_InitStruct->EBI_IdleCycleTime = 0xF; + EBI_InitStruct->EBI_AddressSetupTime = 0xF; + EBI_InitStruct->EBI_AddressHoldTime = 0xF; + EBI_InitStruct->EBI_WriteSetupTime = 0xF; + EBI_InitStruct->EBI_WriteStrobeTime = 0x3F; + EBI_InitStruct->EBI_WriteHoldTime = 0xF; + EBI_InitStruct->EBI_ReadSetupTime = 0xF; + EBI_InitStruct->EBI_ReadStrobeTime = 0x3F; + EBI_InitStruct->EBI_ReadHoldTime = 0xF; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the EBI peripheral. + * @param EBI_Bank: EBI Bank. + * This parameter can be one of the following values: + * @arg EBI_BANK_0 : EBI Bank 0 + * @arg EBI_BANK_1 : EBI Bank 1 + * @arg EBI_BANK_2 : EBI Bank 2 + * @arg EBI_BANK_3 : EBI Bank 3 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EBI_Cmd(u32 EBI_Bank, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EBI_BANK(EBI_Bank)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_EBI->CR |= (0x100 << EBI_Bank); + } + else + { + HT_EBI->CR &= ~(0x100 << EBI_Bank); + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified EBI busy flag has been set. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EBI_GetBusyStatus(void) +{ + if (HT_EBI->SR & 0x1) + { + return SET; + } + else + { + return RESET; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_exti.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_exti.c new file mode 100644 index 00000000000..5ecc7ef97f3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_exti.c @@ -0,0 +1,548 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_exti.c + * @version $Rev:: 6745 $ + * @date $Date:: 2023-02-23 #$ + * @brief This file provides all the EXTI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_exti.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Define EXTI private definitions + * @{ + */ +/* EXTI EVWUPIEN mask */ +#define WAKUPCR_EVWUPIEN_SET ((u32)0x80000000) +#define WAKUPCR_EVWUPIEN_RESET ((u32)0x7FFFFFFF) + +#if (LIBCFG_EXTI_8CH) + const IRQn_Type gEXTIn_IRQn[16] = { + EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, + EXTI4_IRQn, EXTI5_IRQn, EXTI6_IRQn, EXTI7_IRQn, + EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, + EXTI4_IRQn, EXTI5_IRQn, EXTI6_IRQn, EXTI7_IRQn, + }; +#else + const IRQn_Type gEXTIn_IRQn[16] = { + EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, + EXTI4_IRQn, EXTI5_IRQn, EXTI6_IRQn, EXTI7_IRQn, + EXTI8_IRQn, EXTI9_IRQn, EXTI10_IRQn, EXTI11_IRQn, + EXTI12_IRQn, EXTI13_IRQn, EXTI14_IRQn, EXTI15_IRQn, + }; +#endif +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the EXTI peripheral registers. + * @param EXTI_Channel: can be 0, 1 to 15 to select the EXTI Channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval None + ************************************************************************************************************/ +void EXTI_DeInit(u32 EXTI_Channel) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + tmp = 1 << EXTI_Channel; + + *((u32 *) HT_EXTI + EXTI_Channel) = 0x0; + HT_EXTI->CR &= (~tmp); + HT_EXTI->EDGEFLGR = tmp; + HT_EXTI->EDGESR = tmp; + HT_EXTI->SSCR &= (~tmp); + HT_EXTI->WAKUPCR &= (~tmp); + HT_EXTI->WAKUPPOLR &= (~tmp); + HT_EXTI->WAKUPFLG = tmp; +} + +/*********************************************************************************************************//** + * @brief Initialize the EXTI peripheral. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + u32 regval; + + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_InitStruct->EXTI_Channel)); + Assert_Param(IS_EXTI_DEBOUNCE_TYPE(EXTI_InitStruct->EXTI_Debounce)); + Assert_Param(IS_EXTI_DEBOUNCE_SIZE(EXTI_InitStruct->EXTI_DebounceCnt)); + Assert_Param(IS_EXTI_INT_TYPE(EXTI_InitStruct->EXTI_IntType)); + + /* Set EXTI interrupt configuration */ + regval = (EXTI_InitStruct->EXTI_Debounce << 31) | (EXTI_InitStruct->EXTI_IntType << 28) | (EXTI_InitStruct->EXTI_DebounceCnt); + *((u32 *) HT_EXTI + EXTI_InitStruct->EXTI_Channel) = regval; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified EXTI channelx interrupts. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_IntConfig(u32 EXTI_Channel, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Configure EXTI interrupt */ + if (NewState == ENABLE) + { + HT_EXTI->CR |= (1 << EXTI_Channel); + } + else + { + HT_EXTI->CR &= ~(1 << EXTI_Channel); + } +} + +#if (LIBCFG_EXTI_DEBCNTPRE) +/*********************************************************************************************************//** + * @brief Configure the Debounce Counter prescaler. + * @param EXTI_DebCntPre_DIVn: specify the prescaler value. + * This parameter can be one of the following values: + * @arg EXTI_DBCNTPRE_DIV1 : CK_DBCNT = EXTI_PCLK / 1 + * @arg EXTI_DBCNTPRE_DIV2 : CK_DBCNT = EXTI_PCLK / 2 + * @arg EXTI_DBCNTPRE_DIV4 : CK_DBCNT = EXTI_PCLK / 4 + * @arg EXTI_DBCNTPRE_DIV8 : CK_DBCNT = EXTI_PCLK / 8 + * @arg EXTI_DBCNTPRE_DIV16 : CK_DBCNT = EXTI_PCLK / 16 + * @arg EXTI_DBCNTPRE_DIV32 : CK_DBCNT = EXTI_PCLK / 32 + * @arg EXTI_DBCNTPRE_DIV64 : CK_DBCNT = EXTI_PCLK / 64 + * @arg EXTI_DBCNTPRE_DIV128 : CK_DBCNT = EXTI_PCLK / 128 + * @retval None + ************************************************************************************************************/ +void EXTI_SetDebounceCounterPrescaler(EXTI_DebCntPre_TypeDef EXTI_DBCNTPRE_DIVn) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_DEBOUNCE_COUNTER_PRESCALER(EXTI_DBCNTPRE_DIVn)); + + HT_EXTI->CFGR0 = ((HT_EXTI->CFGR0 & 0xF8FFFFFF) | (EXTI_DBCNTPRE_DIVn << 24)); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure the EXTI channelx event wakeup function. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param EXTI_WakeUpType: determines the type of signal to trigger EXTI interrupt. + * This parameter can be one of the following values: + * @arg EXTI_WAKEUP_HIGH_LEVEL + * @arg EXTI_WAKEUP_LOW_LEVEL + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_WakeupEventConfig(u32 EXTI_Channel, u8 EXTI_WakeUpType, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_EXTI_WAKEUP_TYPE(EXTI_WakeUpType)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == ENABLE) + { + if (EXTI_WakeUpType == EXTI_WAKEUP_HIGH_LEVEL) + { + HT_EXTI->WAKUPPOLR &= ~(1 << EXTI_Channel); + } + else + { + HT_EXTI->WAKUPPOLR |= (1 << EXTI_Channel); + } + + HT_EXTI->WAKUPCR |= (1 << EXTI_Channel); + } + else + { + HT_EXTI->WAKUPCR &= ~(1 << EXTI_Channel); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the EXTI channelx event wakeup interrupt. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_WakeupEventIntConfig(ControlStatus NewState) +{ + if (NewState == ENABLE) + { + /* Set EVWUPIEN bit */ + HT_EXTI->WAKUPCR |= WAKUPCR_EVWUPIEN_SET; + } + else + { + /* Clear EVWUPIEN bit */ + HT_EXTI->WAKUPCR &= WAKUPCR_EVWUPIEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified EXTI channelx edge flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval None + ************************************************************************************************************/ +void EXTI_ClearEdgeFlag(u32 EXTI_Channel) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + tmp = 1 << EXTI_Channel; + + /* Write 1 to clear both edge detection flag */ + HT_EXTI->EDGEFLGR = tmp; + /* Write 1 to clear positive edge detection flag */ + HT_EXTI->EDGESR = tmp; +} + +/*********************************************************************************************************//** + * @brief Clear the specified EXTI channelx wakeup flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval None + ************************************************************************************************************/ +void EXTI_ClearWakeupFlag(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + /* Write 1 to clear wake up flag */ + HT_EXTI->WAKUPFLG = 1 << EXTI_Channel; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx edge flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetEdgeFlag(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + return ((HT_EXTI->EDGEFLGR & (1UL << EXTI_Channel)) ? SET : RESET); +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx edge status. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param EXTI_Edge: can be status of edge that user want to monitor. + * This parameter can be one of the following values: + * @arg EXTI_EDGE_POSITIVE + * @arg EXTI_EDGE_NEGATIVE + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetEdgeStatus(u32 EXTI_Channel, u32 EXTI_Edge) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_EXTI_EDGE(EXTI_Edge)); + + if (HT_EXTI->EDGEFLGR & (1UL << EXTI_Channel)) + { + if (GetBit_BB((u32)&HT_EXTI->EDGESR, EXTI_Channel) ^ EXTI_Edge) + { + return SET; + } + else + { + return RESET; + } + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx wakeup flag. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetWakeupFlagStatus(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + if (HT_EXTI->WAKUPFLG & (1 << EXTI_Channel)) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Activate or Deactivate an EXTI channelx interrupt by software. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void EXTI_SWIntCmd(u32 EXTI_Channel, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == ENABLE) + { + HT_EXTI->SSCR = 1 << EXTI_Channel; + } + else + { + HT_EXTI->SSCR &= ~(1 << EXTI_Channel); + } +} + +/*********************************************************************************************************//** + * @brief Get the specified EXTI channelx software command register bit. + * @param EXTI_Channel: specify the EXTI channel. + * This parameter can be one of the following values: + * @arg EXTI_CHANNEL_0 + * @arg EXTI_CHANNEL_1 + * @arg EXTI_CHANNEL_2 + * @arg EXTI_CHANNEL_3 + * @arg EXTI_CHANNEL_4 + * @arg EXTI_CHANNEL_5 + * @arg EXTI_CHANNEL_6 + * @arg EXTI_CHANNEL_7 + * @arg EXTI_CHANNEL_8 + * @arg EXTI_CHANNEL_9 + * @arg EXTI_CHANNEL_10 + * @arg EXTI_CHANNEL_11 + * @arg EXTI_CHANNEL_12 + * @arg EXTI_CHANNEL_13 + * @arg EXTI_CHANNEL_14 + * @arg EXTI_CHANNEL_15 + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus EXTI_GetSWCmdStatus(u32 EXTI_Channel) +{ + /* Check the parameters */ + Assert_Param(IS_EXTI_CHANNEL(EXTI_Channel)); + + if (HT_EXTI->SSCR & (1 << EXTI_Channel)) + { + return SET; + } + else + { + return RESET; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_flash.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_flash.c new file mode 100644 index 00000000000..18e04c04fa7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_flash.c @@ -0,0 +1,471 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_flash.c + * @version $Rev:: 6657 $ + * @date $Date:: 2023-01-16 #$ + * @brief This file provides all the FLASH firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_flash.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Define FLASH private definitions + * @{ + */ + +/* Delay definition */ +#define FLASH_TIMEOUT (0x000FFFFF) + +/* FLASH OCMR */ +#define FLASH_CMD_STADNBY (0x00000000) +#define FLASH_CMD_PROGRAM (0x00000004) +#define FLASH_CMD_PAGEERASE (0x00000008) +#define FLASH_CMD_MASSERASE (0x0000000A) + +/* FLASH OPCR */ +#define FLASH_READY (0x6UL << 1) +#define FLASH_SEND_MAIN (0x00000014) + +/* FLASH CFCR */ +#define CFCR_WAIT_MASK (0xFFFFFFF8) + +#if (LIBCFG_FMC_PREFETCH) +#define FLASH_PREFETCHBUF_ON (0x00000010) +#define FLASH_PREFETCHBUF_OFF (0xFFFFFFEF) +#endif + +#if (LIBCFG_FMC_BRANCHCACHE) +#define FLASH_BRANCHCACHE_ON (0x00001000) +#define FLASH_BRANCHCACHE_OFF (0xFFFFEFFF) +#endif + +#define FLASH_CFCR_MASK (0xFFFFEFE8) +#define FLASH_PREFETCHBUF_AND_BRANCHCACHE_ON (0x00001010) +#define FLASH_PREFETCHBUF_AND_BRANCHCACHE_OFF (0xFFFFEFEF) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macro FLASH private macros + * @{ + */ + +#if (LIBCFG_FMC_PREFETCH) +/** + * @brief Check parameter of the FLASH wait state. + */ +#if (LIBCFG_FMC_WAIT_STATE_2) +#define IS_WAIT_STATE2(x) (x == FLASH_WAITSTATE_2) +#else +#define IS_WAIT_STATE2(x) (0) +#endif + +#define IS_FLASH_WAITSTATE(WAIT) ((WAIT == FLASH_WAITSTATE_0) || \ + (WAIT == FLASH_WAITSTATE_1) || \ + (IS_WAIT_STATE2(WAIT))) +#endif +/** + * @brief Check parameter of the FLASH vector mapping. + */ +#define IS_FLASH_VECTOR_MODE(MODE) ((MODE == FLASH_BOOT_LOADER) || \ + (MODE == FLASH_BOOT_MAIN)) +/** + * @brief Check parameter of the FLASH address. + */ +#define IS_FLASH_ADDRESS(ADDRESS) (ADDRESS < 0x20000000) /* Code 0.5GB Area */ + +/** + * @brief Check parameter of the FLASH interrupt status. + */ +#define IS_FLASH_WC_FLAG(FLAG) ((FLAG & 0x0000001F) != 0) + +/** + * @brief Check parameter of the FLASH interrupt flag. + */ +#define IS_FLASH_FLAG(FLAG) ((FLAG & 0x0003001F) != 0) + +/** + * @brief Check parameter of the FLASH interrupt. + */ +#define IS_FLASH_INT(IT) ((IT & 0x0000001F) != 0) + +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH exported functions + * @{ + */ +#if (LIBCFG_FMC_PREFETCH) +/*********************************************************************************************************//** + * @brief Configure the FLASH wait state. + * @param FLASH_WAITSTATE_n: Setting of FLASH wait state. + * This parameter can be one of the following values: + * @arg \ref FLASH_WAITSTATE_0 : zero wait state + * @arg \ref FLASH_WAITSTATE_1 : one wait state + * @arg \ref FLASH_WAITSTATE_2 : two wait state + * @retval None + ************************************************************************************************************/ +void FLASH_SetWaitState(u32 FLASH_WAITSTATE_n) +{ + u32 uCFCR; + /* Check the parameters */ + Assert_Param(IS_FLASH_WAITSTATE(FLASH_WAITSTATE_n)); + + /* !!! NOTICE !!! + Before changing wait state, both Pre-fetch function and Branch Cache function must be disabled. + */ + uCFCR = HT_FLASH->CFCR; /* Backup previous settings. */ + + /* Disable Pre-fetch function and Branch Cache. */ + HT_FLASH->CFCR = uCFCR & FLASH_PREFETCHBUF_AND_BRANCHCACHE_OFF; + /* Change wait state. */ + HT_FLASH->CFCR = (uCFCR & FLASH_CFCR_MASK) | FLASH_WAITSTATE_n; + /* Restore previous settings. */ + HT_FLASH->CFCR |= uCFCR & (FLASH_PREFETCHBUF_AND_BRANCHCACHE_ON); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable FLASH pre-fetch buffer. + * @param NewState: This parameter can be ENABLE or DISABLE + * @retval None + ************************************************************************************************************/ +void FLASH_PrefetchBufferCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_FLASH->CFCR |= FLASH_PREFETCHBUF_ON; + } + else + { + HT_FLASH->CFCR &= FLASH_PREFETCHBUF_OFF; + } +} +#endif + +#if (LIBCFG_FMC_BRANCHCACHE) +/*********************************************************************************************************//** + * @brief Enable or Disable FLASH branch cache. + * @param NewState: This parameter can be ENABLE or DISABLE + * @retval None + ************************************************************************************************************/ +void FLASH_BranchCacheCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_FLASH->CFCR |= FLASH_BRANCHCACHE_ON; + } + else + { + HT_FLASH->CFCR &= FLASH_BRANCHCACHE_OFF; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Set vector remapping mode. + * @param FLASH_BOOT_x: Booting mode. + * This parameter can be one of the following values: + * @arg \ref FLASH_BOOT_LOADER : Boot loader mode + * @arg \ref FLASH_BOOT_MAIN : Main FLASH mode + * @retval None + ************************************************************************************************************/ +void FLASH_SetRemappingMode(FLASH_Vector FLASH_BOOT_x) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_VECTOR_MODE(FLASH_BOOT_x)); + + HT_FLASH->VMCR = FLASH_BOOT_x; +} + +/*********************************************************************************************************//** + * @brief Erase a specific FLASH page. + * @param PageAddress: Address of the erased page. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * - \ref FLASH_ERR_ADDR_OUT_OF_RANGE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_ErasePage(u32 PageAddress) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_ADDRESS(PageAddress)); + + HT_FLASH->TADR = PageAddress; + HT_FLASH->OCMR = FLASH_CMD_PAGEERASE; + + return FLASH_WaitForOperationEnd(); +} + +/*********************************************************************************************************//** + * @brief Erase FLASH Option Byte page. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_EraseOptionByte(void) +{ + return FLASH_ErasePage(OPTION_BYTE_BASE); +} + +/*********************************************************************************************************//** + * @brief Erase the entire FLASH. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_MassErase(void) +{ + HT_FLASH->OCMR = FLASH_CMD_MASSERASE; + + return FLASH_WaitForOperationEnd(); +} + +/*********************************************************************************************************//** + * @brief Program one word data. + * @param Address: The specific FLASH address to be programmed. + * @param Data: The specific FLASH data to be programmed. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * - \ref FLASH_ERR_ADDR_OUT_OF_RANGE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_ProgramWordData(u32 Address, u32 Data) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_ADDRESS(Address)); + + HT_FLASH->TADR = Address; + HT_FLASH->WRDR = Data; + HT_FLASH->OCMR = FLASH_CMD_PROGRAM; + + return FLASH_WaitForOperationEnd(); +} + +/*********************************************************************************************************//** + * @brief Program FLASH Option Byte page. + * @param Option: Struct pointer of Option Bytes. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_ProgramOptionByte(FLASH_OptionByte *Option) +{ + s32 i; + u32 CP = ~(Option->MainSecurity | Option->OptionProtect << 1); + u32 checksum = 0; + + for (i = 3; i >= 0; i--) + { + FLASH_ProgramWordData(OB_PP0 + i * 4, ~(Option->WriteProtect[i])); + checksum += ~(Option->WriteProtect[i]); + } + + FLASH_ProgramWordData(OB_CP, CP); + checksum += CP; + + FLASH_ProgramWordData(OB_CHECKSUM, checksum); + + return FLASH_COMPLETE; +} + +/*********************************************************************************************************//** + * @brief Return security status of the FLASH. + * @param Option: Struct pointer of Option Bytes. + * @retval None + ************************************************************************************************************/ +void FLASH_GetOptionByteStatus(FLASH_OptionByte *Option) +{ + s32 i; + + for (i = 3; i >= 0; i--) + { + Option->WriteProtect[i] = ~HT_FLASH->PPSR[i]; + } + + Option->MainSecurity = !(HT_FLASH->CPSR & 1); + Option->OptionProtect = !((HT_FLASH->CPSR >> 1) & 1); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specific FLASH interrupts. + * @param FLASH_INT_x: The specific FLASH interrupt. + * This parameter can be any combination (|) of the following values: + * @arg \ref FLASH_INT_ORFIEN + * @arg \ref FLASH_INT_ITADIEN + * @arg \ref FLASH_INT_OBEIEN + * @arg \ref FLASH_INT_IOCMIEN + * @arg \ref FLASH_INT_OREIEN + * @arg \ref FLASH_INT_ALL + * @param Cmd: This parameter can be ENABLE or DISABLE + * @retval None + ************************************************************************************************************/ +void FLASH_IntConfig(u32 FLASH_INT_x, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_INT(FLASH_INT_x)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + { + HT_FLASH->OIER |= FLASH_INT_x; + } + else + { + HT_FLASH->OIER &= ~FLASH_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Return flag status of the FLASH interrupt. + * @param FLASH_FLAG_x: Flag of the FLASH interrupt. + * This parameter can be any combination (|) of the following values: + * @arg \ref FLASH_FLAG_OREF + * @arg \ref FLASH_FLAG_IOCMF + * @arg \ref FLASH_FLAG_OBEF + * @arg \ref FLASH_FLAG_ITADF + * @arg \ref FLASH_FLAG_ORFF + * @arg \ref FLASH_FLAG_PPEF + * @arg \ref FLASH_FLAG_RORFF + * @retval FlagStatus + * - \ref SET + * - \ref RESET + ************************************************************************************************************/ +FlagStatus FLASH_GetIntStatus(u32 FLASH_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_FLAG(FLASH_FLAG_x)); + + if ((HT_FLASH->OISR & FLASH_FLAG_x) != (u32)RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear specific interrupt flags of FLASH. + * @param FLASH_FLAG_x: interrupt flag of FLASH. + * This parameter can be any combination (|) of the following values: + * @arg \ref FLASH_FLAG_OREF + * @arg \ref FLASH_FLAG_IOCMF + * @arg \ref FLASH_FLAG_OBEF + * @arg \ref FLASH_FLAG_ITADF + * @arg \ref FLASH_FLAG_ORFF + * @retval None + ************************************************************************************************************/ +void FLASH_ClearIntFlag(u32 FLASH_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_FLASH_WC_FLAG(FLASH_FLAG_x)); + + HT_FLASH->OISR = FLASH_FLAG_x; +} + +/*********************************************************************************************************//** + * @brief Wait untill the FLASH operation has finished or time-out has occurred. + * @retval FLASH_State + * - \ref FLASH_COMPLETE + * - \ref FLASH_TIME_OUT + * - \ref FLASH_ERR_WRITE_PROTECTED + * - \ref FLASH_ERR_ADDR_OUT_OF_RANGE + * @note HSI must keep turn on when doing the Flash operation (Erase/Program). + ************************************************************************************************************/ +FLASH_State FLASH_WaitForOperationEnd(void) +{ + u32 Timeout = FLASH_TIMEOUT; + u32 Status; + + HT_FLASH->OIER |= (FLASH_INT_ITADIEN); + HT_FLASH->OPCR = FLASH_SEND_MAIN; + #if (LIBCFG_FMC_CMD_READY_WAIT) + __NOP();__NOP();__NOP();__NOP(); + #endif + + /* Waits till the FLASH operation has finished or time-out has occurred */ + while (Timeout--) + { + if ((HT_FLASH->OPCR & FLASH_READY) == FLASH_READY) + { + break; + } + } + Status = HT_FLASH->OISR; + HT_FLASH->OISR &= ~(FLASH_INT_ITADIEN); + + if (Status & FLASH_FLAG_PPEF) + { + return FLASH_ERR_WRITE_PROTECTED; + } + if (Status & FLASH_FLAG_ITADF) + { + return FLASH_ERR_ADDR_OUT_OF_RANGE; + } + if (Timeout == 0) + { + return FLASH_TIME_OUT; + } + + return FLASH_COMPLETE; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gpio.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gpio.c new file mode 100644 index 00000000000..4f778467dee --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gpio.c @@ -0,0 +1,767 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_gpio.c + * @version $Rev:: 6398 $ + * @date $Date:: 2022-10-27 #$ + * @brief This file provides all the GPIO and AFIO firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_gpio.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO driver modules + * @{ + */ + + +/* Private function prototypes -----------------------------------------------------------------------------*/ +u32 _GPIO_ClockControl(HT_GPIO_TypeDef* HT_GPIOx, ControlStatus Cmd); +u32 _AFIO_ClockControl(ControlStatus Cmd); + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macro GPIO private macros + * @{ + */ +#if (AUTO_CK_CONTROL == 1) + #define GPIO_CK_ST u32 isAlreadyOn + #define GPIO_CK_ON() (isAlreadyOn = _GPIO_ClockControl(HT_GPIOx, ENABLE)) + #define GPIO_CK_OFF() if (isAlreadyOn == FALSE) _GPIO_ClockControl(HT_GPIOx, DISABLE) + #define AFIO_CK_ST u32 isAlreadyOn + #define AFIO_CK_ON() (isAlreadyOn = _AFIO_ClockControl(ENABLE)) + #define AFIO_CK_OFF() if (isAlreadyOn == FALSE) _AFIO_ClockControl(DISABLE) +#else + #define GPIO_CK_ST + #define GPIO_CK_ON(...) + #define GPIO_CK_OFF(...) + #define AFIO_CK_ST + #define AFIO_CK_ON(...) + #define AFIO_CK_OFF(...) +#endif +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions GPIO exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitializes the GPIO peripheral registers to their default reset values. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval None + ************************************************************************************************************/ +void GPIO_DeInit(HT_GPIO_TypeDef* HT_GPIOx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + if (HT_GPIOx == HT_GPIOA) + { + RSTCUReset.Bit.PA = 1; + } + else if (HT_GPIOx == HT_GPIOB) + { + RSTCUReset.Bit.PB = 1; + } + #if (LIBCFG_GPIOC) + else if (HT_GPIOx == HT_GPIOC) + { + RSTCUReset.Bit.PC = 1; + } + #endif + #if (LIBCFG_GPIOD) + else if (HT_GPIOx == HT_GPIOD) + { + RSTCUReset.Bit.PD = 1; + } + #endif + #if (LIBCFG_GPIOE) + else if (HT_GPIOx == HT_GPIOE) + { + RSTCUReset.Bit.PE = 1; + } + #endif + #if (LIBCFG_GPIOF) + else if (HT_GPIOx == HT_GPIOF) + { + RSTCUReset.Bit.PF = 1; + } + #endif + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure the direction of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param GPIO_DIR_INorOUT: + * This parameter can be one of below: + * @arg GPIO_DIR_IN : The pins are input mode + * @arg GPIO_DIR_OUT : The pins are output mode + * @retval None + ************************************************************************************************************/ +void GPIO_DirectionConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DIR_Enum GPIO_DIR_INorOUT) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_GPIO_DIR(GPIO_DIR_INorOUT)); + + GPIO_CK_ON(); + + if (GPIO_DIR_INorOUT != GPIO_DIR_IN) + HT_GPIOx->DIRCR |= GPIO_PIN_nBITMAP; + else + HT_GPIOx->DIRCR &= ~GPIO_PIN_nBITMAP; + + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Configure the pull resistor of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param GPIO_PR_x: Selection of Pull resistor. + * This parameter can be one of below: + * @arg GPIO_PR_UP : The pins with internal pull-up resistor + * @arg GPIO_PR_DOWN : The pins with internal pull-down resistor + * @arg GPIO_PR_DISABLE : The pins without pull resistor + * @retval None + ************************************************************************************************************/ +void GPIO_PullResistorConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_PR_Enum GPIO_PR_x) +{ + u32 temp_up, temp_down; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_GPIO_PR(GPIO_PR_x)); + + GPIO_CK_ON(); + temp_up = HT_GPIOx->PUR; + temp_down = HT_GPIOx->PDR; + + #if (LIBCFG_GPIO_PR_STRONG_UP) + temp_up &= ~(GPIO_PIN_nBITMAP << 16); + #endif + temp_up &= ~GPIO_PIN_nBITMAP; + temp_down &= ~GPIO_PIN_nBITMAP; + + switch (GPIO_PR_x) + { + case GPIO_PR_UP: + temp_up |= GPIO_PIN_nBITMAP; + break; + case GPIO_PR_DOWN: + temp_down |= GPIO_PIN_nBITMAP; + break; + case GPIO_PR_DISABLE: + break; + #if (LIBCFG_GPIO_PR_STRONG_UP) + case GPIO_PR_STRONG_UP: + temp_up |= (GPIO_PIN_nBITMAP << 16); + break; + case GPIO_PR_STRONGEST_UP: + temp_up |= (GPIO_PIN_nBITMAP << 16); + temp_up |= GPIO_PIN_nBITMAP; + break; + #endif + default: + break; + } + + HT_GPIOx->PUR = temp_up; + HT_GPIOx->PDR = temp_down; + + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the input control of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void GPIO_InputConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + GPIO_CK_ON(); + if (Cmd != DISABLE) + HT_GPIOx->INER |= GPIO_PIN_nBITMAP; + else + HT_GPIOx->INER &= ~GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Select the driving current of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param GPIO_DV_nMA: + * This parameter can be one of below: + * @arg GPIO_DV_4MA : Select output driving current as 4 mA + * @arg GPIO_DV_8MA : Select output driving current as 8 mA + * @arg GPIO_DV_12MA : Select output driving current as 12 mA + * @arg GPIO_DV_16MA : Select output driving current as 16 mA + * @retval None + ************************************************************************************************************/ +void GPIO_DriveConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, GPIO_DV_Enum GPIO_DV_nMA) +{ + u32 index, temp, CurrentMode = 0, PinPosition = 0; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_GPIO_DV(GPIO_DV_nMA)); + + for (index = 0; index < 16; index++) + { + if ((GPIO_PIN_nBITMAP & 0x0001) == 1) + { + temp = index << 1; + CurrentMode |= ((u32) GPIO_DV_nMA << temp); + PinPosition |= ((u32) 0x03 << temp); + } + GPIO_PIN_nBITMAP >>= 1; + } + + GPIO_CK_ON(); + HT_GPIOx->DRVR &= ~PinPosition; + HT_GPIOx->DRVR |= CurrentMode; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the open drain function of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void GPIO_OpenDrainConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, ControlStatus Cmd) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + GPIO_CK_ON(); + if (Cmd != DISABLE) + HT_GPIOx->ODR |= GPIO_PIN_nBITMAP; + else + HT_GPIOx->ODR &= ~GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +#if LIBCFG_GPIO_SINK_CURRENT_ENHANCED +/*********************************************************************************************************//** + * @brief Select the sink current of specified GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_n: The port pins. + * This parameter can be any combination of GPIO_PIN_x. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void GPIO_SinkConfig(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + Assert_Param(IS_CONTROL_STATUS(Cmd)); + + if (Cmd != DISABLE) + HT_GPIOx->SCER |= GPIO_PIN_n; + else + HT_GPIOx->SCER &= ~GPIO_PIN_n; +} +#endif + +/*********************************************************************************************************//** + * @brief Get the input data of specified port pin. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_n: This parameter can be GPIO_PIN_x. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus GPIO_ReadInBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n) +{ + FlagStatus result; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->DINR & GPIO_PIN_n) != RESET) + result = SET; + else + result = RESET; + + GPIO_CK_OFF(); + return result; +} + +/*********************************************************************************************************//** + * @brief Get the input data of specified GPIO port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval The value of input data register. + ************************************************************************************************************/ +u16 GPIO_ReadInData(HT_GPIO_TypeDef* HT_GPIOx) +{ + u16 uValue; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + uValue = (u16)HT_GPIOx->DINR; + GPIO_CK_OFF(); + return (uValue); +} + +/*********************************************************************************************************//** + * @brief Get the output data of specified port pin. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_n: This parameter can be GPIO_PIN_x. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus GPIO_ReadOutBit(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n) +{ + FlagStatus result; + GPIO_CK_ST; + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->DOUTR & GPIO_PIN_n) != RESET) + result = SET; + else + result = RESET; + + GPIO_CK_OFF(); + return result; +} + +/*********************************************************************************************************//** + * @brief Get the output data of specified GPIO port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval The value of output data register. + ************************************************************************************************************/ +u16 GPIO_ReadOutData(HT_GPIO_TypeDef* HT_GPIOx) +{ + u32 uValue; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + uValue = (u16)HT_GPIOx->DOUTR; + GPIO_CK_OFF(); + return uValue; +} + +/*********************************************************************************************************//** + * @brief Set the selected port bits of output data. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bit to be set. + * This parameter can be any combination of GPIO_PIN_x. + * @retval None + ************************************************************************************************************/ +void GPIO_SetOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->SRR = GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Clear the selected port bits of output data. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bit to be clear. + * This parameter can be any combination of GPIO_PIN_x. + * @retval None + ************************************************************************************************************/ +void GPIO_ClearOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->RR = GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Set or Clear the selected port bits of data. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bits. + * This parameter can be any combination of GPIO_PIN_x. + * @param Status: This parameter can be SET or RESET. + * @retval None + ************************************************************************************************************/ +void GPIO_WriteOutBits(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP, FlagStatus Status) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if (Status != RESET) + HT_GPIOx->SRR = GPIO_PIN_nBITMAP; + else + HT_GPIOx->RR = GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Put data to the specified GPIO data port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param Data: Specify the data to be written to the port data register. + * @retval None + ************************************************************************************************************/ +void GPIO_WriteOutData(HT_GPIO_TypeDef* HT_GPIOx, u16 Data) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->DOUTR = Data; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Lock configuration of GPIO pins. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_nBITMAP: Specify the port bits. + * This parameter can be any combination of GPIO_PIN_x. + * @retval None + ************************************************************************************************************/ +void GPIO_PinLock(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_nBITMAP) +{ + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + HT_GPIOx->LOCKR = (u32)0x5FA00000 | GPIO_PIN_nBITMAP; + GPIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Get the lock state of specified GPIO port. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool GPIO_IsPortLocked(HT_GPIO_TypeDef* HT_GPIOx) +{ + bool result; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->LOCKR >> 16) == 0) + result = FALSE; + else + result = TRUE; + GPIO_CK_OFF(); + return result; +} + +/*********************************************************************************************************//** + * @brief Get the lock state of specified GPIO port pin. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param GPIO_PIN_n: This parameter can be GPIO_PIN_x. + * @retval TRUE or FALSE + ************************************************************************************************************/ +bool GPIO_IsPinLocked(HT_GPIO_TypeDef* HT_GPIOx, u16 GPIO_PIN_n) +{ + bool result; + GPIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO(HT_GPIOx)); + + GPIO_CK_ON(); + if ((HT_GPIOx->LOCKR & GPIO_PIN_n) == 0) + result = FALSE; + else + result = TRUE; + GPIO_CK_OFF(); + return result; +} + +#if (LIBCFG_GPIO_DISABLE_DEBUG_PORT) +/*********************************************************************************************************//** + * @brief Disable DEBUG port to prevent unexpected security lock. + * @retval None + ************************************************************************************************************/ +void GPIO_DisableDebugPort(void) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{ 0 }}; + CKCUClock.Bit.PA = 1; + CKCUClock.Bit.AFIO = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + AFIO_GPxConfig(GPIO_PA, GPIO_PIN_13, AFIO_FUN_GPIO); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_13, GPIO_PR_DOWN); + + #if defined(USE_HT32F52342_52) + GPIO_InputConfig(HT_GPIOA, GPIO_PIN_13, DISABLE); + #endif + + #if 0 + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_DOWN); + GPIO_PullResistorConfig(HT_GPIOA, GPIO_PIN_12, GPIO_PR_UP); + AFIO_GPxConfig(GPIO_PA, GPIO_PIN_12, AFIO_FUN_GPIO); + #endif +} +#endif + +/*********************************************************************************************************//** + * @brief Convert HT_GPIOx to GPIO_Px + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @retval GPIO_Px: GPIO ID + ************************************************************************************************************/ +u32 GPIO_GetID(HT_GPIO_TypeDef* HT_GPIOx) +{ + // Convert 0x400B0000 ~ 0x400C6000 to 0 ~ 11 + u32 GPIO_Px = (((u32)HT_GPIOx) >> (12 + 1)) & 0x7F; + GPIO_Px -= 0x58; // 0xB0000 >> 13 = 0x58 + + return GPIO_Px; +} + +/*********************************************************************************************************//** + * @brief Deinitialize the AFIO peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void AFIO_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.AFIO = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure alternated mode of GPIO with specified pins. + * @param GPIO_Px: GPIO_PA ~ GPIO_PD. + * @param AFIO_PIN_n: This parameter can be any combination of AFIO_PIN_x. + * @param AFIO_MODE_n: This parameter can be one of the following values: + * @arg AFIO_MODE_DEFAULT : The default I/O function + * @arg AFIO_MODE_1 : Alternated mode 1 + * @arg AFIO_MODE_2 : Alternated mode 2 + * @arg AFIO_MODE_3 : Alternated mode 3 + * @arg AFIO_MODE_4 : Alternated mode 4 + * @arg AFIO_MODE_5 : Alternated mode 5 + * @arg AFIO_MODE_6 : Alternated mode 6 + * @arg AFIO_MODE_7 : Alternated mode 7 + * @arg AFIO_MODE_8 : Alternated mode 8 + * @arg AFIO_MODE_9 : Alternated mode 9 + * @arg AFIO_MODE_10 : Alternated mode 10 + * @arg AFIO_MODE_11 : Alternated mode 11 + * @arg AFIO_MODE_12 : Alternated mode 12 + * @arg AFIO_MODE_13 : Alternated mode 13 + * @arg AFIO_MODE_14 : Alternated mode 14 + * @arg AFIO_MODE_15 : Alternated mode 15 + * @retval None + ************************************************************************************************************/ +void AFIO_GPxConfig(u32 GPIO_Px, u32 AFIO_PIN_n, AFIO_MODE_Enum AFIO_MODE_n) +{ + vu32* pGPxCFGR = ((vu32*)&HT_AFIO->GPACFGR[0]) + GPIO_Px * 2; + u32 index = 0; + u32 Mask = 0, PinMode = 0; + s32 i; + AFIO_CK_ST; + + Assert_Param(IS_AFIO_MODE(AFIO_MODE_n)); + AFIO_CK_ON(); + + for (i = 0; i <= 8; i += 8) + { + Mask = 0; + PinMode = 0; + if (AFIO_PIN_n & (0x00FF << i)) + { + for (index = 0; index < 8; index++) + { + if ((AFIO_PIN_n >> index) & (0x0001 << i)) + { + Mask |= (0xF << (index * 4)); + PinMode |= (AFIO_MODE_n << (index * 4)); + } + } + *pGPxCFGR = (*pGPxCFGR & (~Mask)) | PinMode; + } + pGPxCFGR++; + } + + AFIO_CK_OFF(); +} + +/*********************************************************************************************************//** + * @brief Select the GPIO pin to be used as EXTI channel. + * @param GPIO_PIN_NUM_n: Specify the GPIO pin number to be configured. + * @param GPIO_Px: GPIO_PA ~ GPIO_PF. + * @retval None + ************************************************************************************************************/ +void AFIO_EXTISourceConfig(u32 GPIO_PIN_NUM_n, u32 GPIO_Px) +{ + u8 index = 0; + u32 tmp = 0; + AFIO_CK_ST; + + /* Check the parameters */ + Assert_Param(IS_GPIO_PORT(GPIO_Px)); + Assert_Param(IS_GPIO_PIN_NUM(GPIO_PIN_NUM_n)); + + AFIO_CK_ON(); + + if (GPIO_PIN_NUM_n > 7) + { + #if (LIBCFG_EXTI_8CH) + GPIO_Px += 8; + #else + index = 1; + #endif + GPIO_PIN_NUM_n -= 8; + } + + tmp = HT_AFIO->ESSR[index]; + tmp &= ~((u32)0x0F << (GPIO_PIN_NUM_n * 4)); + tmp |= (u32)GPIO_Px << (GPIO_PIN_NUM_n * 4); + HT_AFIO->ESSR[index] = tmp; + AFIO_CK_OFF(); +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Turn on/Turn off specify GPIO clock. + * @param HT_GPIOx: where HT_GPIOx is the selected GPIO from the GPIO peripherals. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval TRUE or FALSE (TRUE: already turn on, FALSE, Turn on by this call) + ***********************************************************************************************************/ +u32 _GPIO_ClockControl(HT_GPIO_TypeDef* HT_GPIOx, ControlStatus Cmd) +{ + u32 PxENStatus; + /*--------------------------------------------------------------------------------------------------------*/ + /* ((0x400Bx000 & 0x0000F000) >> 12 ) / 2 + 16 = */ + /* (0x0 ~ 0x4) + 16 = 16 ~ 20 for AHBCCR PAEN ~ PEEN bit offset */ + /*--------------------------------------------------------------------------------------------------------*/ + u32 offset = ((((u32)HT_GPIOx) & 0x0000F000) >> 12) / 2 + 16; + + PxENStatus = HT_CKCU->AHBCCR & (1 << offset); + + if (PxENStatus != 0) + { + if (Cmd == DISABLE) + { + HT_CKCU->AHBCCR &= (~(1 << offset)); + } + return TRUE; + } + + HT_CKCU->AHBCCR |= (1 << offset); + return FALSE; +} + +/*********************************************************************************************************//** + * @brief Turn on/Turn off AFIO clock. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval TRUE or FALSE (TRUE: already turn on, FALSE, Turn on by this call) + ***********************************************************************************************************/ +u32 _AFIO_ClockControl(ControlStatus Cmd) +{ + u32 AFIOENStatus; + + AFIOENStatus = HT_CKCU->APBCCR0 & (1 << 14); + + if (AFIOENStatus != 0) + { + if (Cmd == DISABLE) + { + HT_CKCU->APBCCR0 &= (~(1 << 14)); + } + return TRUE; + } + + HT_CKCU->APBCCR0 |= (1 << 14); + return FALSE; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gptm.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gptm.c new file mode 100644 index 00000000000..b824c72b168 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_gptm.c @@ -0,0 +1,2 @@ +The SCTM, PWM, GPTM, and MCTM timer have similar architecture. They use the same driver, +"ht32fxxxxx_tm.c/.h" to save the code size. For those timers, please refet to the TM driver/example. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2c.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2c.c new file mode 100644 index 00000000000..1394eb027d7 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2c.c @@ -0,0 +1,861 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_i2c.c + * @version $Rev:: 6398 $ + * @date $Date:: 2022-10-27 #$ + * @brief This file provides all the I2C firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_i2c.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Private_Define I2C private definitions + * @{ + */ +/* I2C ENI2C mask */ +#define CR_ENI2C_SET ((u32)0x00000008) +#define CR_ENI2C_RESET ((u32)0xFFFFFFF7) + +/* I2C ENGC mask */ +#define CR_ENGC_SET ((u32)0x00000004) +#define CR_ENGC_RESET ((u32)0xFFFFFFFB) + +/* I2C AA mask */ +#define CR_ACK_SET ((u32)0x00000001) +#define CR_ACK_RESET ((u32)0xFFFFFFFE) + +/* I2C PDMANACK mask */ +#define CR_PDMANACK_SET ((u32)0x00000400) +#define CR_PDMANACK_RESET ((u32)0xFFFFFBFF) + +/* I2C ENTOUT mask */ +#define CR_ENTOUT_SET ((u32)0x00001000) +#define CR_ENTOUT_RESET ((u32)0xFFFFEFFF) + +/* I2C COMBFILT mask */ +#define CR_COMBFILTER_SET ((u32)0x00002000) +#define CR_COMBFILTER_RESET ((u32)0xFFFFDFFF) + +/* I2C Device Address 0 and Device Address 1 mask */ +#define ADDR_DEVADDR0_SET ((u32)0x00008000) +#define ADDR_DEVADDR0_RESET ((u32)0xFFFF7FFF) +#define ADDR_DEVADDR1_SET ((u32)0x80000000) +#define ADDR_DEVADDR1_RESET ((u32)0x7FFFFFFF) + +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Functions I2C exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the I2C peripheral registers to their default reset values. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval None + ************************************************************************************************************/ +void I2C_DeInit(HT_I2C_TypeDef* I2Cx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + if (I2Cx == HT_I2C0) + { + RSTCUReset.Bit.I2C0 = 1; + } + #if (LIBCFG_I2C1) + else if (I2Cx == HT_I2C1) + { + RSTCUReset.Bit.I2C1 = 1; + } + #endif + #if (LIBCFG_I2C2) + else if (I2Cx == HT_I2C2) + { + RSTCUReset.Bit.I2C2 = 1; + } + #endif + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the I2Cx peripheral according to the specified parameters in the I2C_InitStruct. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void I2C_Init(HT_I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + u32 PCLK_Freq = 0; + s32 sTmp = 0; + s32 SHPGR = 0; + s32 SLPGR = 0; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_GENERAL_CALL(I2C_InitStruct->I2C_GeneralCall)); + Assert_Param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AddressingMode)); + Assert_Param(IS_I2C_ACKNOWLEDGE(I2C_InitStruct->I2C_Acknowledge)); + Assert_Param(IS_I2C_ADDRESS(I2C_InitStruct->I2C_OwnAddress)); + Assert_Param(IS_I2C_SPEED(I2C_InitStruct->I2C_Speed)); + + #if (LIBCFG_I2C_NO_10BIT_MODE) + I2Cx->CR = (I2Cx->CR & 0xFFFFFFFA) | I2C_InitStruct->I2C_GeneralCall | I2C_InitStruct->I2C_Acknowledge; + #else + I2Cx->CR = (I2Cx->CR & 0xFFFFFF7A) | I2C_InitStruct->I2C_GeneralCall | + I2C_InitStruct->I2C_AddressingMode | I2C_InitStruct->I2C_Acknowledge; + #endif + + #if (LIBCFG_I2C_TWO_DEV_ADDR) + I2Cx->ADDR = (I2Cx->ADDR & 0xFFFF0000) | (ADDR_DEVADDR0_SET | (I2C_InitStruct->I2C_OwnAddress)); + #else + I2Cx->ADDR = I2C_InitStruct->I2C_OwnAddress; + #endif + + if (I2Cx == HT_I2C0) + PCLK_Freq = CKCU_GetPeripFrequency(CKCU_PCLK_I2C0); + #if (LIBCFG_I2C1) + else if (I2Cx == HT_I2C1) + PCLK_Freq = CKCU_GetPeripFrequency(CKCU_PCLK_I2C1); + #endif + #if (LIBCFG_I2C2) + else if (I2Cx == HT_I2C2) + PCLK_Freq = CKCU_GetPeripFrequency(CKCU_PCLK_I2C2); + #endif + + switch (I2Cx->CR & 0xC000) + { + case 0: + { + sTmp = 6; + break; + } + case 0x4000: + { + sTmp = 8; + break; + } + case 0x8000: + { + sTmp = 9; + break; + } + } + + SHPGR = (PCLK_Freq * 9)/(I2C_InitStruct->I2C_Speed * 20) - sTmp - I2C_InitStruct->I2C_SpeedOffset; + SLPGR = (PCLK_Freq * 11)/(I2C_InitStruct->I2C_Speed * 20) - sTmp - I2C_InitStruct->I2C_SpeedOffset; + + SHPGR = (SHPGR < 0) ? 0 : SHPGR; + SLPGR = (SLPGR < 0) ? 0 : SLPGR; + + I2Cx->SHPGR = SHPGR; + I2Cx->SLPGR = SLPGR; +} + +/*********************************************************************************************************//** + * @brief Fill each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ + I2C_InitStruct->I2C_GeneralCall = I2C_GENERALCALL_DISABLE; + I2C_InitStruct->I2C_AddressingMode = I2C_ADDRESSING_7BIT; + I2C_InitStruct->I2C_Acknowledge = I2C_ACK_DISABLE; + I2C_InitStruct->I2C_OwnAddress = 0; + I2C_InitStruct->I2C_Speed = 1000000; + I2C_InitStruct->I2C_SpeedOffset = 0; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified I2C peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_Cmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ENI2C_SET; + } + else + { + I2Cx->CR &= CR_ENI2C_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Generate STOP condition of I2C communication. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval None + ************************************************************************************************************/ +void I2C_GenerateSTOP(HT_I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + I2Cx->CR |= 0x2; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable I2C interrupts. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Int: specify if the I2C interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_INT_STA + * @arg I2C_INT_STO + * @arg I2C_INT_ADRS + * @arg I2C_INT_GCS + * @arg I2C_INT_ARBLOS + * @arg I2C_INT_RXNACK + * @arg I2C_INT_BUSERR + * @arg I2C_INT_TOUT + * @arg I2C_INT_RXDNE + * @arg I2C_INT_TXDE + * @arg I2C_INT_RXBF + * @arg I2C_INT_ALL + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_IntConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_INT(I2C_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->IER |= I2C_Int; + } + else + { + I2Cx->IER &= (u32)~I2C_Int; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable I2C General Call. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_GeneralCallCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ENGC_SET; + } + else + { + I2Cx->CR &= CR_ENGC_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable I2C sending acknowledgement. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_AckCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ACK_SET; + } + else + { + I2Cx->CR &= CR_ACK_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Configure own address of the specified I2C. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Address: specify own address of I2C. + * @retval None + ************************************************************************************************************/ +void I2C_SetOwnAddress(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDRESS(I2C_Address)); + + #if (LIBCFG_I2C_TWO_DEV_ADDR) + I2Cx->ADDR = (I2Cx->ADDR & 0xFFFFFF80) | (ADDR_DEVADDR0_SET | I2C_Address); + #else + I2Cx->ADDR = I2C_Address; + #endif +} + +#if (LIBCFG_I2C_TWO_DEV_ADDR) +/*********************************************************************************************************//** + * @brief Configure own address 1 of the specified I2C. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Address: specify own address 1 of I2C. + * @retval None + ************************************************************************************************************/ +void I2C_SetOwnAddress1(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDRESS(I2C_Address)); + + I2Cx->ADDR = (I2Cx->ADDR & 0xFF80FFFF) | (ADDR_DEVADDR1_SET | (I2C_Address << 16)); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable I2C own address. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param Address: specify the ADDR number. + * This parameter can be one of the following values: + * @arg I2C_DEV_ADDR_0 : + * @arg I2C_DEV_ADDR_1 : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_OwnAddressCmd(HT_I2C_TypeDef* I2Cx, I2C_ADDR_Enum Address, ControlStatus NewState) +{ + u32 value = ADDR_DEVADDR0_SET; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDR(Address)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (Address == I2C_DEV_ADDR_1) + { + value = value << 16; + } + + if (NewState != DISABLE) + { + I2Cx->ADDR |= value; + } + else + { + I2Cx->ADDR &= (~value); + } +} +#endif + +/*********************************************************************************************************//** + * @brief Start transmitting to target slave address. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Address: specify the slave address which will be transmitted. + * @param I2C_Direction: This parameter can be I2C_MASTER_READ or I2C_MASTER_WRITE. + * @retval None + ************************************************************************************************************/ +void I2C_TargetAddressConfig(HT_I2C_TypeDef* I2Cx, I2C_AddressTypeDef I2C_Address, u32 I2C_Direction) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDRESS(I2C_Address)); + Assert_Param(IS_I2C_DIRECTION(I2C_Direction)); + + /* Make sure the prior stop command has been finished */ + while (I2Cx->CR & 0x2); + + if (I2C_Direction != I2C_MASTER_WRITE) + { + I2Cx->TAR = I2C_Address | I2C_MASTER_READ; + } + else + { + I2Cx->TAR = I2C_Address | I2C_MASTER_WRITE; + } +} + +/*********************************************************************************************************//** + * @brief Send a data word through the I2Cx peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Data: Byte to be transmitted. + * @retval None + ************************************************************************************************************/ +void I2C_SendData(HT_I2C_TypeDef* I2Cx, u8 I2C_Data) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + I2Cx->DR = I2C_Data; +} + +/*********************************************************************************************************//** + * @brief Return the received data by the I2Cx peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval The value of the received data. + ************************************************************************************************************/ +u8 I2C_ReceiveData(HT_I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + return (u8)I2Cx->DR; +} + +/*********************************************************************************************************//** + * @brief Read the specified I2C register and returns its value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Register: specify the register to read. + * This parameter can be one of the following values: + * @arg I2C_REGISTER_CR : Control Register + * @arg I2C_REGISTER_IER : Interrupt Enable Register + * @arg I2C_REGISTER_ADDR : Address Register + * @arg I2C_REGISTER_SR : Status Register + * @arg I2C_REGISTER_SHPGR : SCL High Period Generation Register + * @arg I2C_REGISTER_SLPGR : SCL Low Period Generation Register + * @arg I2C_REGISTER_DR : Data Register + * @arg I2C_REGISTER_TAR : Target Register + * @retval None + ************************************************************************************************************/ +u32 I2C_ReadRegister(HT_I2C_TypeDef* I2Cx, u8 I2C_Register) +{ + vu32 tmp = 0; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (u32)I2Cx; + tmp += I2C_Register; + return (*(u32 *)tmp); +} + +/*********************************************************************************************************//** + * @brief Check whether the specified I2C flag has been set. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Flag: specify the flag to be check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_STA : I2C start condition transmitted flag (Master mode) + * @arg I2C_FLAG_STO : I2C stop condition detected flag (Slave flag) + * @arg I2C_FLAG_ADRS : I2C address flag + * @arg I2C_FLAG_GCS : I2C general call flag (Slave mode) + * @arg I2C_FLAG_ARBLOS : I2C arbitration loss flag (Master mode) + * @arg I2C_FLAG_RXNACK : I2C received not acknowledge flag + * @arg I2C_FLAG_BUSERR : I2C bus error flag + * @arg I2C_FLAG_RXDNE : I2C Rx data not empty flag + * @arg I2C_FLAG_TXDE : I2C Tx data empty flag + * @arg I2C_FLAG_RXBF : I2C RX buffer full flag + * @arg I2C_FLAG_BUSBUSY : I2C bus busy flag + * @arg I2C_FLAG_MASTER : I2C master mode flag (Master flag) + * @arg I2C_FLAG_TXNRX : I2C transmitter mode flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus I2C_GetFlagStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_FLAG(I2C_Flag)); + + if ((I2Cx->SR & I2C_Flag) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified I2C status has been active. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Status: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg I2C_MASTER_SEND_START + * @arg I2C_MASTER_RECEIVER_MODE + * @arg I2C_MASTER_TRANSMITTER_MODE + * @arg I2C_MASTER_RX_NOT_EMPTY + * @arg I2C_MASTER_RX_NOT_EMPTY_NOBUSY + * @arg I2C_MASTER_TX_EMPTY + * @arg I2C_MASTER_RX_BUFFER_FULL + * @arg I2C_SLAVE_ACK_TRANSMITTER_ADDRESS + * @arg I2C_SLAVE_ACK_RECEIVER_ADDRESS + * @arg I2C_SLAVE_ACK_GCALL_ADDRESS + * @arg I2C_SLAVE_RX_NOT_EMPTY + * @arg I2C_SLAVE_RX_NOT_EMPTY_STOP + * @arg I2C_SLAVE_TX_EMPTY + * @arg I2C_SLAVE_RX_BUFFER_FULL + * @arg I2C_SLAVE_RECEIVED_NACK + * @arg I2C_SLAVE_RECEIVED_NACK_STOP + * @arg I2C_SLAVE_STOP_DETECTED + * @retval SUCCESS or ERROR + ************************************************************************************************************/ +ErrStatus I2C_CheckStatus(HT_I2C_TypeDef* I2Cx, u32 I2C_Status) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_STATUS(I2C_Status)); + + if (I2Cx->SR == I2C_Status) + { + return (SUCCESS); + } + else + { + return (ERROR); + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified I2C flag. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Flag: specify the flag that is to be cleared. + * This parameter can be one of the following values: + * @arg I2C_FLAG_ARBLOS : I2C arbitration flag + * @arg I2C_FLAG_RXNACK : I2C receive not acknowledge flag + * @arg I2C_FLAG_BUSERR : I2C Bus error flag + * @retval None + ************************************************************************************************************/ +void I2C_ClearFlag(HT_I2C_TypeDef* I2Cx, u32 I2C_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_CLEAR_FLAG(I2C_Flag)); + + I2Cx->SR = I2C_Flag; +} + +/*********************************************************************************************************//** + * @brief Set the interval timing of the high period of the I2C clock. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_HighPeriod: specify the high period that is to be set. + * This parameter must be a number between 0 and 0xFFFF. + * @retval None + ************************************************************************************************************/ +void I2C_SetSCLHighPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_HighPeriod) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_SCL_HIGH(I2C_HighPeriod)); + + I2Cx->SHPGR = I2C_HighPeriod; +} + +/*********************************************************************************************************//** + * @brief Set the interval timing of low period of the I2C clock. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_LowPeriod: specify the low period that is to be set. + * This parameter must be a number between 0 and 0xFFFF. + * @retval None + ************************************************************************************************************/ +void I2C_SetSCLLowPeriod(HT_I2C_TypeDef* I2Cx, u32 I2C_LowPeriod) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_SCL_LOW(I2C_LowPeriod)); + + I2Cx->SLPGR = I2C_LowPeriod; +} + +#if (LIBCFG_PDMA) +/*********************************************************************************************************//** + * @brief Enable or Disable the I2Cx PDMA interface. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_PDMAREQ: specify the I2C PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_PDMAREQ_TX: Tx PDMA transfer request + * @arg I2C_PDMAREQ_RX: Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_PDMACmd(HT_I2C_TypeDef* I2Cx, u32 I2C_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_PDMA_REQ(I2C_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= I2C_PDMAREQ; + } + else + { + I2Cx->CR &= ~I2C_PDMAREQ; + } +} + +/*********************************************************************************************************//** + * @brief Specify that the next PDMA transfer is the last one. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_PDMANACKCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_PDMANACK_SET; + } + else + { + I2Cx->CR &= CR_PDMANACK_RESET; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified I2C time out function. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_TimeOutCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_ENTOUT_SET; + } + else + { + I2Cx->CR &= CR_ENTOUT_RESET; + } +} + +/*********************************************************************************************************//** + * @brief This function is used to set the I2C timeout value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Timeout: specify the timeout value. + * @retval None + ************************************************************************************************************/ +void I2C_SetTimeOutValue(HT_I2C_TypeDef* I2Cx, u32 I2C_Timeout) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_TIMEOUT(I2C_Timeout)); + + I2Cx->TOUT = (I2C_Timeout | (I2Cx->TOUT & 0xFFFF0000)); +} + +/*********************************************************************************************************//** + * @brief This function is used to set the prescaler of I2C timeout value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Prescaler: specify the I2C time out prescaler value. + * This parameter can be one of the following values: + * @arg I2C_PRESCALER_1 : I2C prescaler set to 1 + * @arg I2C_PRESCALER_2 : I2C prescaler set to 2 + * @arg I2C_PRESCALER_4 : I2C prescaler set to 4 + * @arg I2C_PRESCALER_16 : I2C prescaler set to 16 + * @arg I2C_PRESCALER_32 : I2C prescaler set to 32 + * @arg I2C_PRESCALER_64 : I2C prescaler set to 64 + * @arg I2C_PRESCALER_128 : I2C prescaler set to 128 + * @retval None + ************************************************************************************************************/ +void I2C_SetTimeOutPrescaler(HT_I2C_TypeDef* I2Cx, u32 I2C_Prescaler) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_PRESCALER(I2C_Prescaler)); + + I2Cx->TOUT = (I2C_Prescaler | (I2Cx->TOUT & 0x0000FFFF)); +} + +#if (LIBCFG_I2C_NO_ADDR_MASK == 0) +/*********************************************************************************************************//** + * @brief This function is used to determine the prescaler of I2C timeout value. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param I2C_Mask: specify the bit position of I2C slave address to be masked. + * This parameter can be any combination of the following values: + * @arg I2C_MASKBIT_0 : Bit 0 of I2C slave address is masked + * @arg I2C_MASKBIT_1 : Bit 1 of I2C slave address is masked + * @arg I2C_MASKBIT_2 : Bit 2 of I2C slave address is masked + * @arg I2C_MASKBIT_3 : Bit 3 of I2C slave address is masked + * @arg I2C_MASKBIT_4 : Bit 4 of I2C slave address is masked + * @arg I2C_MASKBIT_5 : Bit 5 of I2C slave address is masked + * @arg I2C_MASKBIT_6 : Bit 6 of I2C slave address is masked + * @arg I2C_MASKBIT_7 : Bit 7 of I2C slave address is masked + * @arg I2C_MASKBIT_8 : Bit 8 of I2C slave address is masked + * @arg I2C_MASKBIT_9 : Bit 9 of I2C slave address is masked + * @retval None + ************************************************************************************************************/ +void I2C_AddressMaskConfig(HT_I2C_TypeDef* I2Cx, u32 I2C_Mask) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_ADDRESS_MASK(I2C_Mask)); + + I2Cx->ADDMR = I2C_Mask; +} +#endif + +/*********************************************************************************************************//** + * @brief Return the received address by the I2Cx peripheral. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @retval The value of the received address. + ************************************************************************************************************/ +u16 I2C_GetAddressBuffer(HT_I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + + return ((u16)I2Cx->ADDSR); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the combinational filter. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2C_CombFilterCmd(HT_I2C_TypeDef* I2Cx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + I2Cx->CR |= CR_COMBFILTER_SET; + } + else + { + I2Cx->CR &= CR_COMBFILTER_RESET; + } +} + +/*********************************************************************************************************//** + * @brief This function is used to determine the filter glitch width of 0~2 PCLK. + * @param I2Cx: where I2Cx is the selected I2C from the I2C peripherals. + * @param Seq_Filter_Select: specify the glitch width of 0~2 PCLK. + * This parameter can be any combination of the following values: + * @arg SEQ_FILTER_DISABLE : sequential filter is disabled + * @arg SEQ_FILTER_1_PCLK : filter glitch width of 1 PCLK + * @arg SEQ_FILTER_2_PCLK : filter glitch width of 2 PCLK + * @retval None + ************************************************************************************************************/ +void I2C_SequentialFilterConfig(HT_I2C_TypeDef* I2Cx, u32 Seq_Filter_Select) +{ + u32 SHPGR = I2Cx->SHPGR; + u32 SLPGR = I2Cx->SLPGR; + + /* Check the parameters */ + Assert_Param(IS_I2C(I2Cx)); + Assert_Param(IS_I2C_SEQ_FILTER_MASK(Seq_Filter_Select)); + + switch (I2Cx->CR & 0xC000) + { + case 0: + if (Seq_Filter_Select == SEQ_FILTER_1_PCLK) + { + if (SHPGR >= 2) + { + SHPGR -= 2; + SLPGR -= 2; + } + } + else if (Seq_Filter_Select == SEQ_FILTER_2_PCLK) + { + if (SHPGR >= 2) + { + SHPGR -= 3; + SLPGR -= 3; + } + } + break; + + case 0x4000: + if (Seq_Filter_Select == SEQ_FILTER_DISABLE) + { + SHPGR += 2; + SLPGR += 2; + } + else if (Seq_Filter_Select == SEQ_FILTER_2_PCLK) + { + if (SHPGR >= 1) + { + SHPGR -= 1; + SLPGR -= 1; + } + } + break; + + case 0x8000: + if (Seq_Filter_Select == SEQ_FILTER_DISABLE) + { + SHPGR += 3; + SLPGR += 3; + } + else if (Seq_Filter_Select == SEQ_FILTER_1_PCLK) + { + SHPGR += 1; + SLPGR += 1; + } + break; + + default: + break; + } + + I2Cx->SHPGR = SHPGR; + I2Cx->SLPGR = SLPGR; + I2Cx->CR = (I2Cx->CR & 0x3FFF) | Seq_Filter_Select; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2s.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2s.c new file mode 100644 index 00000000000..4ca971eed1f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_i2s.c @@ -0,0 +1,336 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_i2s.c + * @version $Rev:: 4829 $ + * @date $Date:: 2020-07-23 #$ + * @brief This file provides all the I2S firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_i2s.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup I2S I2S + * @brief I2S driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Private_Define I2S private definitions + * @{ + */ +#define I2S_EN (1UL) +#define MCLK_OP_EN (1UL << 9) +#define TX_MUTE_EN (1UL << 12) +#define CLK_DIV_EN (1UL << 15) +#define BCLK_INV_EN (1UL << 18) +#define MCLK_INV_EN (1UL << 19) + +#define I2S_SLAVE (1UL << 3) +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Functions I2S exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the I2S peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void I2S_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.I2S = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the I2S peripheral according to the specified parameters in the I2S_InitStruct. + * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void I2S_Init(I2S_InitTypeDef* I2S_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + Assert_Param(IS_I2S_FORMAT(I2S_InitStruct->I2S_Format)); + Assert_Param(IS_I2S_WORD_WIDTH(I2S_InitStruct->I2S_WordWidth)); + Assert_Param(IS_I2S_MCLK_DIV(I2S_InitStruct->I2S_X_Div, I2S_InitStruct->I2S_Y_Div)); + Assert_Param(IS_I2S_BCLK_DIV(I2S_InitStruct->I2S_N_Div)); + + HT_I2S->CR = I2S_InitStruct->I2S_Mode | I2S_InitStruct->I2S_Format | I2S_InitStruct->I2S_WordWidth; + + if (I2S_InitStruct->I2S_BclkInv == ENABLE) + { + HT_I2S->CR |= BCLK_INV_EN; + } + + if (I2S_InitStruct->I2S_MclkInv == ENABLE) + { + HT_I2S->CR |= MCLK_INV_EN; + } + + if ((I2S_InitStruct->I2S_Mode & I2S_SLAVE) == RESET) + { + HT_I2S->CDR = (I2S_InitStruct->I2S_N_Div << 16) | (I2S_InitStruct->I2S_X_Div << 8) | + (I2S_InitStruct->I2S_Y_Div); + HT_I2S->CR |= CLK_DIV_EN; + while (I2S_GetFlagStatus(I2S_FLAG_CLK_RDY) == RESET); + + if (I2S_InitStruct->I2S_MclkOut == ENABLE) + { + HT_I2S->CR |= MCLK_OP_EN; + } + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the I2S peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_Cmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->CR |= I2S_EN; + } + else + { + HT_I2S->CR &= ~I2S_EN; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the Tx mute for the I2S peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_TxMuteCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->CR |= TX_MUTE_EN; + } + else + { + HT_I2S->CR &= ~TX_MUTE_EN; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the I2S PDMA interface. + * @param I2S_PDMAREQ: specify the I2S PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2S_PDMAREQ_TX : Tx PDMA transfer request + * @arg I2S_PDMAREQ_RX : Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_PDMACmd(u32 I2S_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_PDMA_REQ(I2S_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->CR |= I2S_PDMAREQ; + } + else + { + HT_I2S->CR &= I2S_PDMAREQ; + } +} + +/*********************************************************************************************************//** + * @brief Reset the specified I2S FIFO. + * @param I2S_FIFO: specify the FIFO that is to be reset. + * This parameter can be any combination of the following values: + * @arg I2S_TX_FIFO : I2S Tx FIFO + * @arg I2S_RX_FIFO : I2S Rx FIFO + * @retval None + ************************************************************************************************************/ +void I2S_FIFOReset(u32 I2S_FIFO) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_TWO_FIFO(I2S_FIFO)); + + HT_I2S->FCR |= I2S_FIFO; +} + +/*********************************************************************************************************//** + * @brief Set the trigger level of specified I2S FIFO. + * @param I2S_FIFO: specify the FIFO that is to be set. + * This parameter can be any combination of the following values: + * @arg I2S_TX_FIFO : I2S Tx FIFO + * @arg I2S_RX_FIFO : I2S Rx FIFO + * @param I2S_FIFOLevel: Specify the FIFO trigger level. + * @retval None + ************************************************************************************************************/ +void I2S_FIFOTrigLevelConfig(u32 I2S_FIFO, u32 I2S_FIFOLevel) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_TWO_FIFO(I2S_FIFO)); + Assert_Param(IS_I2S_FIFO_LEVEL(I2S_FIFOLevel)); + + if (I2S_FIFO == I2S_TX_FIFO) + { + HT_I2S->FCR = ((HT_I2S->FCR & (~0x0000000F)) | I2S_FIFOLevel); + } + else + { + HT_I2S->FCR = ((HT_I2S->FCR & (~0x000000F0)) | (I2S_FIFOLevel << 4)); + } +} + +/*********************************************************************************************************//** + * @brief Return the status of specified I2S FIFO. + * @param I2S_FIFO: specify the FIFO that is to be checked. + * This parameter can be one of the following values: + * @arg I2S_TX_FIFO : I2S Tx FIFO + * @arg I2S_RX_FIFO : I2S Rx FIFO + * @retval The number of data in specified I2S FIFO. + ************************************************************************************************************/ +u8 I2S_GetFIFOStatus(u32 I2S_FIFO) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_ONE_FIFO(I2S_FIFO)); + + if (I2S_FIFO == I2S_TX_FIFO) + { + return (u8)((HT_I2S->SR >> 24) & 0x0F); + } + else + { + return (u8)(HT_I2S->SR >> 28); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the I2S interrupt. + * @param I2S_Int: specify if the I2S interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2S_INT_TXFIFO_TRI : I2S Tx FIFO trigger level interrupt + * @arg I2S_INT_TXFIFO_UF : I2S Rx FIFO underflow interrupt + * @arg I2S_INT_TXFIFO_OV : I2S Tx FIFO overflow interrupt + * @arg I2S_INT_RXFIFO_TRI : I2S Rx FIFO trigger level interrupt + * @arg I2S_INT_RXFIFO_UV : I2S Rx FIFO underflow interrupt + * @arg I2S_INT_RXFIFO_OV : I2S Rx FIFO overflow interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void I2S_IntConfig(u32 I2S_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_INT(I2S_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_I2S->IER |= I2S_Int; + } + else + { + HT_I2S->IER &= ~I2S_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified I2S flag has been set or not. + * @param I2S_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_TXFIFO_TRI : I2S Tx FIFO trigger level flag + * @arg I2S_FLAG_TXFIFO_UDF : I2S Tx FIFO underflow flag + * @arg I2S_FLAG_TXFIFO_OVF : I2S Tx FIFO overflow flag + * @arg I2S_FLAG_TXFIFO_EMP : I2S Tx FIFO empty flag + * @arg I2S_FLAG_TXFIFO_FUL : I2S Tx FIFO full flag + * @arg I2S_FLAG_RXFIFO_TRI : I2S Rx FIFO trigger level flag + * @arg I2S_FLAG_RXFIFO_UDF : I2S Rx FIFO underflow flag + * @arg I2S_FLAG_RXFIFO_OVF : I2S Rx FIFO overflow flag + * @arg I2S_FLAG_RXFIFO_EMP : I2S Rx FIFO empty flag + * @arg I2S_FLAG_RXFIFO_FUL : I2S Rx FIFO full flag + * @arg I2S_FLAG_RIGHT_CH : I2S right channel flag + * @arg I2S_FLAG_TX_BUSY : I2S Tx busy flag + * @arg I2S_FLAG_CLK_RDY : I2S clock ready flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus I2S_GetFlagStatus(u32 I2S_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_FLAG(I2S_Flag)); + + if (HT_I2S->SR & I2S_Flag) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified I2S flag. + * @param I2S_Flag: specify the flag that is to be cleared. + * This parameter can be any combination of the following values: + * @arg I2S_FLAG_TXFIFO_TRI : I2S Tx FIFO trigger level flag + * @arg I2S_FLAG_TXFIFO_UV : I2S Tx FIFO underflow flag + * @arg I2S_FLAG_TXFIFO_OV : I2S Tx FIFO overflow flag + * @arg I2S_FLAG_RXFIFO_TRI : I2S Rx FIFO trigger level flag + * @arg I2S_FLAG_RXFIFO_UV : I2S Rx FIFO underflow flag + * @arg I2S_FLAG_RXFIFO_OV : I2S Rx FIFO overflow flag + * @retval None + ************************************************************************************************************/ +void I2S_ClearFlag(u32 I2S_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_I2S_FLAG_CLEAR(I2S_Flag)); + + HT_I2S->SR = I2S_Flag; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_lcd.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_lcd.c new file mode 100644 index 00000000000..eb61db93596 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_lcd.c @@ -0,0 +1,577 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_lcd.c + * @version $Rev:: 1704 $ + * @date $Date:: 2017-08-17 #$ + * @brief This file provides all the LCD firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_lcd.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup LCD LCD + * @brief LCD driver modules + * @{ + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup LCD_Exported_Functions LCD exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the LCD peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void LCD_DriverDeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + RSTCUReset.Bit.LCD = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initializes the LCD peripheral according to the specified parameters in the LCD_InitStruct. + * @param LCD_InitStruct: pointer to a LCD_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void LCD_DriverInit(LCD_InitTypeDef* LCD_InitStruct) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD control register. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->FCR = (u32)(LCD_InitStruct->LCD_Prescaler) | + (u32)(LCD_InitStruct->LCD_Divider); + + HT_LCD->CR = (u32)(LCD_InitStruct->LCD_Waveform) | + (u32)(LCD_InitStruct->LCD_Bias) | + (u32)(LCD_InitStruct->LCD_Duty) | + (u32)(LCD_InitStruct->LCD_VoltageSource); +} + +/*********************************************************************************************************//** + * @brief Configure the MCONT mask time. + * @param Sel: specify the mask time. + * This parameter can be: + * @arg LCD_MaskTime_25ns : MCONT mask time is 25 ns + * @arg LCD_MaskTime_40ns : MCONT mask time is 40 ns + * @retval None + ************************************************************************************************************/ +void LCD_MaskTimeConfig(LCD_MaskTime_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD control register. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 24)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable half of the low value resistor (HRLEN). + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void LCD_HalfRLCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_LCD->CR |= (1ul << 15); + } + else + { + HT_LCD->CR &= ~(1ul << 15); + } +} + +/*********************************************************************************************************//** + * @brief Configure the STATIC switch. + * @param Sel: specify the STATIC switch status. + * This parameter can be: + * @arg LCD_Static_Switch_Open : STATIC switch is open during dead time. + * @arg LCD_Static_Switch_close : STATIC switch is closed during dead time. + * @retval None + ************************************************************************************************************/ +void LCD_StaticSwitchConfig(LCD_StaticSwitch_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD control register. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 14)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure MuxCOM7 to be COM7 or SEGx. + * @param Sel: Specify the MuxSEG. + * This parameter can be one of the following values: + * @arg LCD_MUXCOM7_IS_COM7 : + * @arg LCD_MUXCOM7_IS_SEGx :(52341: SEG28, 57352: SEG36) + * @retval None + ************************************************************************************************************/ +void LCD_MuxCOM7Config(LCD_MUXCOM7_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD control register. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 11)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure MuxCOM6 to be COM6 or SEGx. + * @param Sel: Specify the MuxSEG. + * This parameter can be one of the following values: + * @arg LCD_MUXCOM7_IS_COM6 : + * @arg LCD_MUXCOM7_IS_SEGx :(52341: SEG27, 57352: SEG35) + * @retval None + ************************************************************************************************************/ +void LCD_MuxCOM6Config(LCD_MUXCOM6_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 10)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure MuxCOM5 to be COM5 or SEGx. + * @param Sel: Specify the MuxSEG. + * This parameter can be one of the following values: + * @arg LCD_MUXCOM7_IS_COM5 : + * @arg LCD_MUXCOM7_IS_SEGx :(52341: SEG26, 57352: SEG34) + * @retval None + ************************************************************************************************************/ +void LCD_MuxCOM5Config(LCD_MUXCOM5_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 9)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure MuxCOM4 to be COM4 or SEGx. + * @param Sel: Specify the MuxSEG. + * This parameter can be one of the following values: + * @arg LCD_MUXCOM7_IS_COM4 : + * @arg LCD_MUXCOM7_IS_SEGx :(52341: SEG25, 57352: SEG33) + * @retval None + ************************************************************************************************************/ +void LCD_MuxCOM4Config(LCD_MUXCOM4_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 8)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD waveform type. + * @param Sel: specify the LCD waveform type. + * This parameter can be one of the following values: + * @arg LCD_Type_A_Waveform : Type A waveform + * @arg LCD_Type_B_Waveform : Type B waveform + * @retval None + ************************************************************************************************************/ +void LCD_WaveformConfig(LCD_Waveform_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 7)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure LCD Bias Selector. + * @param Sel: Specify LCD Bias Selector. + * This parameter can be one of the following values: + * @arg LCD_Bias_1_4 : Bias 1/4 + * @arg LCD_Bias_1_2 : Bias 1/2 + * @arg LCD_Bias_1_3 : Bias 1/3 + * @arg LCD_Bias_Static : STATIC + * @retval None + ************************************************************************************************************/ +void LCD_BiasConfig(LCD_Bias_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(3ul << 5)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD Duty Selection. + * @param Sel: Specify LCD Duty select. + * This parameter can be one of the following values: + * @arg LCD_Duty_Static : Static duty + * @arg LCD_Duty_1_2 : 1/2 duty + * @arg LCD_Duty_1_3 : 1/3 duty + * @arg LCD_Duty_1_4 : 1/4 duty + * @arg LCD_Duty_1_6 : 1/6 duty + * @arg LCD_Duty_1_8 : 1/8 duty + ************************************************************************************************************/ +void LCD_DutyConfig(LCD_Duty_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(7ul << 2)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD Power Selection. + * @param Sel: Specify LCD Power select. + * This parameter can be one of the following values: + * @arg LCD_VoltageSource_External : External VLCD + * @arg LCD_VoltageSource_Internal : Internal charge pump + * @retval None + ************************************************************************************************************/ +void LCD_VoltageSourceConfig(LCD_VoltageSource_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + HT_LCD->CR = (HT_LCD->CR & ~(1ul << 1)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the LCD peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void LCD_Cmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_LCD->CR |= (1ul << 0); + } + else + { + HT_LCD->CR &= ~(1ul << 0); + } +} + +/*********************************************************************************************************//** + * @brief Configure the LCD 16-bit prescaler. + * @param Sel: specify the LCD 16-bit prescaler setting. + * This parameter can be one of the following values: + * @arg LCD_Prescaler_1 : CK_PS = CK_LCD / 1 + * @arg LCD_Prescaler_2 : CK_PS = CK_LCD / 2 + * @arg LCD_Prescaler_4 : CK_PS = CK_LCD / 4 + * @arg LCD_Prescaler_8 : CK_PS = CK_LCD / 8 + * @arg LCD_Prescaler_16 : CK_PS = CK_LCD / 16 + * @arg LCD_Prescaler_32 : CK_PS = CK_LCD / 32 + * @arg LCD_Prescaler_64 : CK_PS = CK_LCD / 64 + * @arg LCD_Prescaler_128 : CK_PS = CK_LCD / 128 + * @arg LCD_Prescaler_256 : CK_PS = CK_LCD / 256 + * @arg LCD_Prescaler_512 : CK_PS = CK_LCD / 512 + * @arg LCD_Prescaler_1024 : CK_PS = CK_LCD / 1024 + * @arg LCD_Prescaler_2048 : CK_PS = CK_LCD / 2048 + * @arg LCD_Prescaler_4096 : CK_PS = CK_LCD / 4096 + * @arg LCD_Prescaler_8192 : CK_PS = CK_LCD / 8192 + * @arg LCD_Prescaler_16384 : CK_PS = CK_LCD / 16384 + * @arg LCD_Prescaler_32768 : CK_PS = CK_LCD / 32768 + * @retval None + ************************************************************************************************************/ +void LCD_PrescalerConfig(LCD_Prescaler_Enum Sel) +{ + while (LCD_GetFlagStatus(LCD_FLAG_FCRSF) == SET); + HT_LCD->FCR = (HT_LCD->FCR & ~(15ul << 22)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD clock divider. + * @param Sel: specify the LCD clock divider setting. + * This parameter can be one of the following values: + * @arg LCD_Divider_16 : CK_DIV = CK_PS / 16 + * @arg LCD_Divider_17 : CK_DIV = CK_PS / 17 + * @arg LCD_Divider_18 : CK_DIV = CK_PS / 18 + * @arg LCD_Divider_19 : CK_DIV = CK_PS / 19 + * @arg LCD_Divider_20 : CK_DIV = CK_PS / 20 + * @arg LCD_Divider_21 : CK_DIV = CK_PS / 21 + * @arg LCD_Divider_22 : CK_DIV = CK_PS / 22 + * @arg LCD_Divider_23 : CK_DIV = CK_PS / 23 + * @arg LCD_Divider_24 : CK_DIV = CK_PS / 24 + * @arg LCD_Divider_25 : CK_DIV = CK_PS / 25 + * @arg LCD_Divider_26 : CK_DIV = CK_PS / 26 + * @arg LCD_Divider_27 : CK_DIV = CK_PS / 27 + * @arg LCD_Divider_28 : CK_DIV = CK_PS / 28 + * @arg LCD_Divider_29 : CK_DIV = CK_PS / 29 + * @arg LCD_Divider_30 : CK_DIV = CK_PS / 30 + * @arg LCD_Divider_31 : CK_DIV = CK_PS / 31 + * @retval None + ************************************************************************************************************/ +void LCD_DividerConfig(LCD_Divider_Enum Sel) +{ + while (LCD_GetFlagStatus(LCD_FLAG_FCRSF) == SET); + HT_LCD->FCR = (HT_LCD->FCR & ~(15ul << 18)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD Blink Mode Selection. + * @param Sel: Specify LCD Blink Mode Selection. + * This parameter can be one of the following values: + * @arg LCD_BlinkMode_Off : Blink inactive + * @arg LCD_BlinkMode_SEG0_COM0 : SEG0 on COM0 blink + * @arg LCD_BlinkMode_SEG0_AllCOM : SEG0 on All COM blink + * @arg LCD_BlinkMode_AllSEG_AllCOM : All SEG on All COM blink + ************************************************************************************************************/ +void LCD_BlinkModeConfig(LCD_BlinkMode_Enum Sel) +{ + while (LCD_GetFlagStatus(LCD_FLAG_FCRSF) == SET); + HT_LCD->FCR = (HT_LCD->FCR & ~(3ul << 16)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD Blink Frequency Selection. + * @param Sel: Specify LCD Blink Frequency Selection. + * This parameter can be one of the following values: + * @arg LCD_BlinkFrequency_Div8 : Blink frequency = frame rate / 8 + * @arg LCD_BlinkFrequency_Div16 : Blink frequency = frame rate / 16 + * @arg LCD_BlinkFrequency_Div32 : Blink frequency = frame rate / 32 + * @arg LCD_BlinkFrequency_Div64 : Blink frequency = frame rate / 64 + * @arg LCD_BlinkFrequency_Div128 : Blink frequency = frame rate / 128 + * @arg LCD_BlinkFrequency_Div256 : Blink frequency = frame rate / 256 + * @arg LCD_BlinkFrequency_Div512 : Blink frequency = frame rate / 512 + * @arg LCD_BlinkFrequency_Div1024 : Blink frequency = frame rate / 1024 + ************************************************************************************************************/ +void LCD_BlinkFrequencyConfig(LCD_BlinkFrequency_Enum Sel) +{ + while (LCD_GetFlagStatus(LCD_FLAG_FCRSF) == SET); + HT_LCD->FCR = (HT_LCD->FCR & ~(7ul << 13)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD Charge Pump Voltage Selection. + * @param Sel: Specify LCD Charge Pump Voltage Selection. + * This parameter can be one of the following values: + * @arg LCD_ChargePump_2V65 : Charge pump voltage = 2.65 V + * @arg LCD_ChargePump_2V75 : Charge pump voltage = 2.75 V + * @arg LCD_ChargePump_2V85 : Charge pump voltage = 2.85 V + * @arg LCD_ChargePump_2V95 : Charge pump voltage = 2.95 V + * @arg LCD_ChargePump_3V10 : Charge pump voltage = 3.10 V + * @arg LCD_ChargePump_3V25 : Charge pump voltage = 3.25 V + * @arg LCD_ChargePump_3V40 : Charge pump voltage = 3.40 V + * @arg LCD_ChargePump_3V55 : Charge pump voltage = 3.55 V + ************************************************************************************************************/ +void LCD_ChargePumpConfig(LCD_ChargePump_Enum Sel) +{ + /* !!! NOTICE !!! + Must wait until the LCDENS = 0 before change the LCD settings. + */ + #if 0 + while (LCD_GetFlagStatus(LCD_FLAG_ENS) == 1); + #endif + + while (LCD_GetFlagStatus(LCD_FLAG_FCRSF)); + HT_LCD->FCR = (HT_LCD->FCR & ~(7ul << 10)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD Dead Time Duration Selection. + * @param Sel: Specify LCD Dead Time Duration Selection. + This parameter can be one of the following values: + * @arg LCD_Deadtime_0 : No dead time + * @arg LCD_Deadtime_1 : Type A: 1/2 phase period; Type B: 1 phase period + * @arg LCD_Deadtime_2 : Type A: 2/2 phase period; Type B: 2 phase period + * @arg LCD_Deadtime_3 : Type A: 3/2 phase period; Type B: 3 phase period + * @arg LCD_Deadtime_4 : Type A: 4/2 phase period; Type B: 4 phase period + * @arg LCD_Deadtime_5 : Type A: 5/2 phase period; Type B: 5 phase period + * @arg LCD_Deadtime_6 : Type A: 6/2 phase period; Type B: 6 phase period + * @arg LCD_Deadtime_7 : Type A: 7/2 phase period; Type B: 7 phase period + ************************************************************************************************************/ +void LCD_DeadTimeConfig(LCD_DeadTime_Enum Sel) +{ + while (LCD_GetFlagStatus(LCD_FLAG_FCRSF) == SET); + HT_LCD->FCR = (HT_LCD->FCR & ~(7ul << 7)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the LCD High Drive Duration Selection. + * @param Sel: Specify LCD High Drive Duration Selection. + * This parameter LCD_DEAD_Enum can be one of the following values: + * @arg LCD_HighDrive_0 : No high drive + * @arg LCD_HighDrive_1 : High drive duration = 1 CK_PS pulses + * @arg LCD_HighDrive_2 : High drive duration = 2 CK_PS pulses + * @arg LCD_HighDrive_3 : High drive duration = 3 CK_PS pulses + * @arg LCD_HighDrive_4 : High drive duration = 4 CK_PS pulses + * @arg LCD_HighDrive_5 : High drive duration = 5 CK_PS pulses + * @arg LCD_HighDrive_6 : High drive duration = 6 CK_PS pulses + * @arg LCD_HighDrive_7 : High drive duration = 7 CK_PS pulses + * @arg LCD_HighDrive_Static : Static high drive + ************************************************************************************************************/ +void LCD_HighDriveConfig(LCD_HighDrive_Enum Sel) +{ + u32 FCR = HT_LCD->FCR; + + if (Sel == LCD_HighDrive_Static) + { + FCR |= (1ul << 0); + } + else + { + FCR &= ~(1ul << 0); + FCR = (FCR & ~(7ul << 4)) | Sel; + } + + while (LCD_GetFlagStatus(LCD_FLAG_FCRSF)); + HT_LCD->FCR = FCR; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified LCD interrupts. + * @param LCD_INT: Specify the LCD interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg LCD_INT_UDDIE : Update Display Done Interrupt Enable + * @arg LCD_INT_SOFIE : Start of Frame Interrupt Enable + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void LCD_IntConfig(u32 LCD_INT, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_LCD_INT(LCD_INT)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_LCD->IER |= LCD_INT; + } + else + { + HT_LCD->IER &= ~LCD_INT; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified LCD flag has been set. + * @param LCD_FLAG: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * @arg LCD_FLAG_FCRSF : LCD Frame Control Register Synchronization Flag + * @arg LCD_FLAG_RDY : Ready Flag + * @arg LCD_FLAG_UDD : Update Display Done + * @arg LCD_FLAG_UDR : Update Display Request + * @arg LCD_FLAG_SOF : Start of Frame Flag + * @arg LCD_FLAG_ENS : LCD Enabled Status + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus LCD_GetFlagStatus(u32 LCD_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_LCD_FLAG(LCD_FLAG)); + + if ((HT_LCD->SR & LCD_FLAG) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief SET LCD Update Display Request. + * @retval None + ************************************************************************************************************/ +void LCD_SetUpdateDisplayRequest(void) +{ + HT_LCD->SR |= LCD_FLAG_UDR; +} + +/*********************************************************************************************************//** + * @brief Clear the specified LCD flag. + * @param LCD_Flag: specify the flag that is to be cleared. + * This parameter can be one of the following values: + * @arg LCD_CLR_UDDC : Update display done clear + * @arg LCD_CLR_SOFC : Start of frame flag clear + * @retval None + ************************************************************************************************************/ +void LCD_ClearFlag(u32 LCD_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_LCD_CLEAR(LCD_Flag)); + + HT_LCD->CLR = LCD_Flag; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ledc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ledc.c new file mode 100644 index 00000000000..37a340dd7f3 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_ledc.c @@ -0,0 +1,309 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_ledc.c + * @version $Rev:: 6374 $ + * @date $Date:: 2022-10-25 #$ + * @brief This file provides all the LEDC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_ledc.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup LEDC LEDC + * @brief LEDC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup LEDC_Private_Define LEDC private definitions + * @{ + */ +#define RPRE_MASK 0xF000FFFF + +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup LEDC_Exported_Functions LEDC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the LEDC peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void LEDC_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + RSTCUReset.Bit.LEDC = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the LEDC peripheral according to the specified parameters in the LEDC_InitStruct. + * @param LEDC_InitStruct: Pointer to a LEDC_InitTypeDef structure. Please note the following. + 1. When LEDC is started, the LEDC_ClockSource, LEDC_ClockPrescaler and LEDC_DeadTime can't + be changed, so LEDC_Init() will turn off the LED first.You need to restart LEDC by + LEDC_Cmd(ENABEL). + 2. The LEDC_DeadTime number must be less than the LEDC_Prescaler. + Example: + If LEDC_DutyClockNumber selects LEDC_DTYNUM_8, the valid LEDC_DeadTime ranges from 0 to 7. + If LEDC_DutyClockNumber selects LEDC_DTYNUM_16, the valid LEDC_DeadTime ranges from 0 to 15. + If LEDC_DutyClockNumber selects LEDC_DTYNUM_32, the valid LEDC_DeadTime ranges from 0 to 31. + If LEDC_DutyClockNumber selects LEDC_DTYNUM_64, the valid LEDC_DeadTime ranges from 0 to 63. + * @retval None + ************************************************************************************************************/ +void LEDC_Init(LEDC_InitTypeDef* LEDC_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_LEDC_SRC(LEDC_InitStruct->LEDC_ClockSource)); + Assert_Param(IS_LEDC_DTYNUM(LEDC_InitStruct->LEDC_DutyClockNumber)); + Assert_Param(IS_LEDC_PSC(LEDC_InitStruct->LEDC_ClockPrescaler)); + Assert_Param(IS_LEDC_COMEN(LEDC_InitStruct->LEDC_COMxEN)); + Assert_Param(IS_LEDC_DTCR(LEDC_InitStruct->LEDC_DeadTime)); + + /* Disable LEDC */ + HT_LEDC->CR = 0; + + /* LEDC Control Register Configuration */ + HT_LEDC->CR = LEDC_InitStruct->LEDC_ClockSource << 8 |\ + LEDC_InitStruct->LEDC_DutyClockNumber << 12 |\ + LEDC_InitStruct->LEDC_ClockPrescaler << 16; + + /* LEDC COM Enable Register Configuration */ + HT_LEDC->CER = LEDC_InitStruct->LEDC_COMxEN; + + /* LEDC Dead Time Control Register Configuration */ + HT_LEDC->DTCR = LEDC_InitStruct->LEDC_DeadTime; +} + +/*********************************************************************************************************//** + * @brief Select the LEDC timer clock source. + * @param Source: specify the clock source of LEDC. + * @arg LEDC_SRC_PCLK + * @arg LEDC_SRC_LSI : Low speed internal clock. + * @arg LEDC_SRC_LSE : Low speed external clock. + * @retval None + ************************************************************************************************************/ +void LEDC_ClockSourceConfig(LEDC_SRC_Enum Source) +{ + Assert_Param(IS_LEDC_SRC(Source)); + + HT_LEDC->CR = (HT_LEDC->CR & ~(3UL << 8)) | ((u32)Source << 8); +} + +/*********************************************************************************************************//** + * @brief Configure the LEDC prescaler. + * @param Psc: Value of LEDC prescaler: 0~4095 + * This parameter can be one of following values: + * @retval None + ************************************************************************************************************/ +void LEDC_SetPrescaler(u32 Psc) +{ + Assert_Param(IS_LEDC_PSC(Psc)); + + HT_LEDC->CR = (HT_LEDC->CR & RPRE_MASK) | (Psc << 16); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the LEDC. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void LEDC_Cmd(ControlStatus NewState) +{ + if (NewState != DISABLE) + { + HT_LEDC->CR |= (1UL); + } + else + { + HT_LEDC->CR &= ~(1UL); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable Frame interrupt. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void LEDC_IntConfig(ControlStatus NewState) +{ + if (NewState != DISABLE) + { + HT_LEDC->IER |= LEDC_INT_FRAME; + } + else + { + HT_LEDC->IER &= ~LEDC_INT_FRAME; + } +} + +/*********************************************************************************************************//** + * @brief Get the LEDC flag. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus LEDC_GetFlagStatus(void) +{ + if (HT_LEDC->SR & LEDC_FLAG_FRAME) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the LEDC graflag. + * @retval None + ************************************************************************************************************/ +void LEDC_ClearFlagStatus(void) +{ + HT_LEDC->SR |= LEDC_FLAG_FRAME; +} + +/*********************************************************************************************************//** + * @brief Configure COMx's state of LEDC with specified pins. + * @param LEDC_COMxEN: This parameter can be any combination of the following values: + * @arg LEDC_COM0EN : Set LEDC COM0 + * @arg LEDC_COM1EN : Set LEDC COM1 + * @arg LEDC_COM2EN : Set LEDC COM2 + * @arg LEDC_COM3EN : Set LEDC COM3 + * @arg LEDC_COM4EN : Set LEDC COM4 + * @arg LEDC_COM5EN : Set LEDC COM5 + * @arg LEDC_COM6EN : Set LEDC COM6 + * @arg LEDC_COM7EN : Set LEDC COM7 + * @arg LEDC_COM8EN : Set LEDC COM8(Only support 54253 ) + * @arg LEDC_COM9EN : Set LEDC COM9(Only support 54253 ) + * @arg LEDC_COM10EN : Set LEDC COM10(Only support 54253 ) + * @arg LEDC_COM11EN : Set LEDC COM11(Only support 54253 ) + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void LEDC_COMxConfig(u32 LEDC_COMxEN, ControlStatus Cmd) +{ + /* Check the parameters */ + Assert_Param(IS_LEDC_COMEN(LEDC_COMxEN)); + + if (Cmd != DISABLE) + HT_LEDC->CER |= LEDC_COMxEN; + else + HT_LEDC->CER &= ~LEDC_COMxEN; +} + +/*********************************************************************************************************//** + * @brief Configure the dead time duty. The LED brightness can be adjusted by adjusting the dead duty. + * @param LEDC_DeadTimeDuty: Deadtime Clock Numbers. The LEDC_DeadTimeDuty number must be less than the + LEDC_DutyClockNumber(DTYNUM). + Example: + If LEDC_DutyClockNumber selects LEDC_DTYNUM_8, the valid LEDC_DeadTime ranges from 0 to 7. + If LEDC_DutyClockNumber selects LEDC_DTYNUM_16, the valid LEDC_DeadTime ranges from 0 to 15. + If LEDC_DutyClockNumber selects LEDC_DTYNUM_32, the valid LEDC_DeadTime ranges from 0 to 31. + If LEDC_DutyClockNumber selects LEDC_DTYNUM_64, the valid LEDC_DeadTime ranges from 0 to 63. + * @retval None + ************************************************************************************************************/ +void LEDC_SetDeadTimeDuty(u32 LEDC_DeadTimeDuty) +{ + /* Check the parameters */ + Assert_Param(IS_LEDC_DTCR(LEDC_DeadTimeDuty)); + + HT_LEDC->DTCR = LEDC_DeadTimeDuty; +} + +/*********************************************************************************************************//** + * @brief Set the output polarity of COM and SEG. + * @param LEDC_COMxPOL: This parameter can be any combination of the following values: + * @arg LEDC_COM0POL : Set COM0 polarity + * @arg LEDC_COM1POL : Set COM1 polarity + * @arg LEDC_COM2POL : Set COM2 polarity + * @arg LEDC_COM3POL : Set COM3 polarity + * @arg LEDC_COM4POL : Set COM4 polarity + * @arg LEDC_COM5POL : Set COM5 polarity + * @arg LEDC_COM6POL : Set COM6 polarity + * @arg LEDC_COM7POL : Set COM7 polarity + * @arg LEDC_COM8POL : Set COM8 polarity(Only support 54253 ) + * @arg LEDC_COM9POL : Set COM9 polarity(Only support 54253 ) + * @arg LEDC_COM10POL : Set COM10 polarity(Only support 54253 ) + * @arg LEDC_COM11POL : Set COM11 polarity(Only support 54253 ) + * @param LEDC_SEGxPOL: This parameter can be any combination of the following values: + * @arg LEDC_SEG0POL : Set SEG0 polarity + * @arg LEDC_SEG1POL : Set SEG1 polarity + * @arg LEDC_SEG2POL : Set SEG2 polarity + * @arg LEDC_SEG3POL : Set SEG3 polarity + * @arg LEDC_SEG4POL : Set SEG4 polarity + * @arg LEDC_SEG5POL : Set SEG5 polarity + * @arg LEDC_SEG6POL : Set SEG6 polarity + * @arg LEDC_SEG7POL : Set SEG7 polarity + * @param mode: LED layout mode. + * SEG polarity COM polarity + * ------------------------------------------------------- + * @arg COMMON_CATHODE : non-inverted non-inverted + * @arg COMMON_CATHODE_WITH_NPN : non-inverted inverted + * @arg COMMON_ANODE_WITH_PNP : inverted non-inverted + * @arg COMMON_ANODE_WITH_NPN : inverted inverted + * @arg @retval None + ************************************************************************************************************/ +void LEDC_SetPolarityMode(u32 LEDC_COMxPOL, u32 LEDC_SEGxPOL , LEDC_Mode mode) +{ + /* Check the parameters */ + Assert_Param(IS_LEDC_DTCR(mode)); + Assert_Param(IS_LEDC_COMPOL(LEDC_COMxPOL)); + Assert_Param(IS_LEDC_SEGPOL(LEDC_SEGxPOL)); + + switch(mode) + { + case COMMON_CATHODE: + HT_LEDC->PCR &= ~(LEDC_COMxPOL|LEDC_SEGxPOL); + break; + case COMMON_CATHODE_WITH_NPN: + HT_LEDC->PCR |= LEDC_COMxPOL; + HT_LEDC->PCR &= ~(LEDC_SEGxPOL); + break; + case COMMON_ANODE_WITH_PNP: + HT_LEDC->PCR &= ~(LEDC_COMxPOL); + HT_LEDC->PCR |= LEDC_SEGxPOL; + break; + case COMMON_ANODE_WITH_NPN: + HT_LEDC->PCR |= LEDC_COMxPOL|LEDC_SEGxPOL; + break; + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_lstm.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_lstm.c new file mode 100644 index 00000000000..02180b23089 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_lstm.c @@ -0,0 +1,32 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_lstm.c + * @version $Rev:: 6594 $ + * @date $Date:: 2022-12-27 #$ + * @brief This file provides all the LSTM firmware functions (alias file of RTC). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_rtc.c" + +// This is an alias file to map LSTM to RTC, since the LSTM is almost the same as RTC +// It reduces the maintenance effort. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_mctm.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_mctm.c new file mode 100644 index 00000000000..d30ac8ecedd --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_mctm.c @@ -0,0 +1,293 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_mctm.c + * @version $Rev:: 6421 $ + * @date $Date:: 2022-11-03 #$ + * @brief This file provides all the MCTM firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_mctm.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup MCTM MCTM + * @brief MCTM driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Private_Define MCTM private definitions + * @{ + */ +#define CTR_COMPRE 0x00000100ul +#define CTR_COMUS 0x00000200ul + +#define CHBRKCTR_CHMOE 0x00000010ul +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup MCTM_Exported_Functions MCTM exported functions + * @{ + */ + +/*********************************************************************************************************//** + * @brief Configure polarity of the MCTMx channel N. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripheral. + * @param Channel: Specify the MCTM channel. + * This parameter can be one of the following values: + * @arg MCTM_CH_0 : MCTM channel 0 + * @arg MCTM_CH_1 : MCTM channel 1 + * @arg MCTM_CH_2 : MCTM channel 2 + * @arg MCTM_CH_3 : MCTM channel 3 + * @param Pol: Specify the polarity of channel N. + * This parameter can be one of the following values: + * @arg MCTM_CHP_NONINVERTED : active high + * @arg MCTM_CHP_INVERTED : active low + * @retval None + ************************************************************************************************************/ +void MCTM_ChNPolarityConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHP_Enum Pol) +{ + u32 wChpolr; + + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_COMPLEMENTARY_CH(Channel)); + Assert_Param(IS_TM_CHP(Pol)); + + /* Set or reset the CHxN polarity */ + wChpolr = MCTMx->CHPOLR & (~(u32)(0x2 << (Channel << 1))); + MCTMx->CHPOLR = wChpolr | ((Pol << 1) << (Channel << 1)); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the MCTMx channel N. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripheral. + * @param Channel: Specify the MCTM channel. + * This parameter can be one of the following values: + * @arg MCTM_CH_0 : MCTM channel 0 + * @arg MCTM_CH_1 : MCTM channel 1 + * @arg MCTM_CH_2 : MCTM channel 2 + * @arg MCTM_CH_3 : MCTM channel 3 + * @param Control: This parameter can be TM_CHCTL_ENABLE or TM_CHCTL_DISABLE. + * @retval None + ************************************************************************************************************/ +void MCTM_ChannelNConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_COMPLEMENTARY_CH(Channel)); + Assert_Param(IS_TM_CHCTL(Control)); + + /* Reset the CHxNE Bit */ + MCTMx->CHCTR &= ~(u32)(0x2 << (Channel << 1)); + + /* Set or reset the CHxNE Bit */ + MCTMx->CHCTR |= (u32)(Control << 1) << (Channel << 1); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the channels main output of the MCTMx. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void MCTM_CHMOECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MCTM Main Output */ + MCTMx->CHBRKCTR |= CHBRKCTR_CHMOE; + } + else + { + /* Disable the MCTM Main Output */ + MCTMx->CHBRKCTR &= ~CHBRKCTR_CHMOE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the break feature, dead time, Lock level, the OSSI, the OSSR State + * and the CHAOE(automatic output enable). + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param CHBRKCTRInit: Point to a MCTM_CHBRKCTRInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void MCTM_CHBRKCTRConfig(HT_TM_TypeDef* MCTMx, MCTM_CHBRKCTRInitTypeDef *CHBRKCTRInit) +{ + u32 wTmpReg; + + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_OSSR_STATE(CHBRKCTRInit->OSSRState)); + Assert_Param(IS_MCTM_OSSI_STATE(CHBRKCTRInit->OSSIState)); + Assert_Param(IS_MCTM_LOCK_LEVEL(CHBRKCTRInit->LockLevel)); + Assert_Param(IS_MCTM_BREAK_STATE(CHBRKCTRInit->Break0)); + Assert_Param(IS_MCTM_BREAK_POLARITY(CHBRKCTRInit->Break0Polarity)); + Assert_Param(IS_MCTM_CHAOE_STATE(CHBRKCTRInit->AutomaticOutput)); + Assert_Param(IS_TM_FILTER(CHBRKCTRInit->BreakFilter)); + + wTmpReg = MCTMx->CHBRKCTR & 0x00000010; // Keep CHMOE + wTmpReg |= (u32)CHBRKCTRInit->BreakFilter << 8; + wTmpReg |= (u32)CHBRKCTRInit->DeadTime << 24; + wTmpReg |= CHBRKCTRInit->LockLevel | CHBRKCTRInit->OSSRState | CHBRKCTRInit->OSSIState; + wTmpReg |= CHBRKCTRInit->Break0 | CHBRKCTRInit->Break0Polarity | CHBRKCTRInit->AutomaticOutput; + + MCTMx->CHBRKCTR = wTmpReg; +} + +/*********************************************************************************************************//** + * @brief Configure the break feature, dead time, Lock level, the OSSI, the OSSR State + * and the CHAOE(automatic output enable). + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param CHBRKCTRInit: Point to a MCTM_CHBRKCTRTypeDef structure. + * @retval None + ************************************************************************************************************/ +void MCTM_CHBRKCTRConfig2(HT_TM_TypeDef* MCTMx, MCTM_CHBRKCTRTypeDef *CHBRKCTRInit) +{ + u32 wTmpReg; + + wTmpReg = MCTMx->CHBRKCTR & 0x00000010; // Keep CHMOE + + wTmpReg |= CHBRKCTRInit->Reg; + + MCTMx->CHBRKCTR = wTmpReg; +} + +/*********************************************************************************************************//** + * @brief Fill each CHBRKCTRInitStruct member with its default value. + * @param CHBRKCTRInitStruct: Point to a MCTM_CHBRKCTRInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void MCTM_CHBRKCTRStructInit(MCTM_CHBRKCTRInitTypeDef* CHBRKCTRInitStruct) +{ + /* Set the default configuration */ + CHBRKCTRInitStruct->OSSRState = MCTM_OSSR_STATE_DISABLE; + CHBRKCTRInitStruct->OSSIState = MCTM_OSSI_STATE_DISABLE; + CHBRKCTRInitStruct->LockLevel = MCTM_LOCK_LEVEL_OFF; + CHBRKCTRInitStruct->DeadTime = 0x00; + CHBRKCTRInitStruct->Break0 = MCTM_BREAK_DISABLE; + CHBRKCTRInitStruct->Break0Polarity = MCTM_BREAK_POLARITY_LOW; + CHBRKCTRInitStruct->BreakFilter = 0; + CHBRKCTRInitStruct->AutomaticOutput = MCTM_CHAOE_DISABLE; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable MCTMx COMPRE function. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void MCTM_COMPRECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MCTM COMPRE */ + MCTMx->CTR |= CTR_COMPRE; + } + else + { + /* Disable the MCTM COMPRE */ + MCTMx->CTR &= ~CTR_COMPRE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the MCTMx COMUS function. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param Sel: Specify the COMUS value. + * This parameter can be one of the following values: + * @arg MCTM_COMUS_STIOFF : MCTM capture/compare control bits are updated by setting the UEV2G bit only + * @arg MCTM_COMUS_STION : MCTM capture/compare control bits are updated by both setting the UEV2G bit + * or when a rising edge occurs on STI + * @retval None + ************************************************************************************************************/ +void MCTM_COMUSConfig(HT_TM_TypeDef* MCTMx, MCTM_COMUS_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_MCTM_COMUS(Sel)); + + if (Sel != MCTM_COMUS_STIOFF) + { + /* Set the MCTM COMUS bit */ + MCTMx->CTR |= CTR_COMUS; + } + else + { + /* Clear the MCTM COMUS bit */ + MCTMx->CTR &= ~CTR_COMUS; + } +} + +#if (LIBCFG_MCTM_UEV1DIS) +/*********************************************************************************************************//** + * @brief Enable or Disable Overflow/Underflow update event(does not contain interrupt) of the MCTMx. + * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals. + * @param MCTM_UEV1x: MCTM_UEV1UD or MCTM_UEV1OD. Overflow/underflow request disable control. + * @param NewState: This parameter can be SET or RESET. + * @retval None + ************************************************************************************************************/ +void MCTM_UpdateEventDisable(HT_TM_TypeDef* MCTMx, MCTM_UEV1DIS_Enum MCTM_UEV1x, FlagStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MCTM(MCTMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != RESET) + { + /* Set the update disable bit */ + MCTMx->CNTCFR |= MCTM_UEV1x; + } + else + { + /* Reset the update disable bit */ + MCTMx->CNTCFR &= ~MCTM_UEV1x; + } +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_midi.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_midi.c new file mode 100644 index 00000000000..15369686b31 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_midi.c @@ -0,0 +1,1176 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_midi.c + * @version $Rev:: 6684 $ + * @date $Date:: 2023-01-18 #$ + * @brief This file provides all the MIDI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_midi.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup MIDI MIDI + * @brief MIDI driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup MIDI_Private_Define MIDI private definitions + * @{ + */ +/* MIDI TRIG ST Mask */ +#define TRIG_ST_ENABLE (u32)0x00000400 +#define TRIG_ST_DISABLE (u32)0xFFFFFBFF + +/* MIDI TRIG VM Mask */ +#define TRIG_VM_ENABLE (u32)0x00000200 +#define TRIG_VM_DISABLE (u32)0xFFFFFDFF + +/* MIDI TRIG FR Mask */ +#define TRIG_FR_ENABLE (u32)0x00000100 +#define TRIG_FR_DISABLE (u32)0xFFFFFEFF + +/* MIDI CHAN CHx Mask */ +#define MIDI_CHAN_CHx_MASK (u32)0x0000001F + +/* MIDI FREQ BL Mask */ +#define MIDI_FREQ_BL_MASK (u32)0x0000F000 + +/* MIDI FREQ FR Mask */ +#define MIDI_FREQ_FR_MASK (u32)0x00000FFF + +/* MIDI VOL AR Mask */ +#define MIDI_VOL_AR_MASK (u32)0x80000000 + +/* MIDI VOL ENV Mask */ +#define MIDI_VOL_ENV_MASK (u32)0x60000000 + +/* MIDI VOL VL Mask */ +#define MIDI_VOL_VL_MASK (u32)0x03FF0000 + +/* MIDI VOL VR Mask */ +#define MIDI_VOL_VR_MASK (u32)0x000003FF + +/* MIDI RENUM WBS Mask */ +#define MIDI_RENUM_WBS_MASK (u32)0x00030000 + +/* MIDI RENUM RE Mask */ +#define MIDI_RENUM_RE_MASK (u32)0x00007FFF + +/* MIDI MCUCH0 CH0B Mask */ +#define MIDI_MCUCH0_CH0B_MASK (u32)0xFFFF0000 + +/* MIDI MCUCH0 CH0A Mask */ +#define MIDI_MCUCH0_CH0A_MASK (u32)0x0000FFFF + +/* MIDI MCUCH1 CH1B Mask */ +#define MIDI_MCUCH1_CH1B_MASK (u32)0xFFFF0000 + +/* MIDI MCUCH1 CH1A Mask */ +#define MIDI_MCUCH1_CH1A_MASK (u32)0x0000FFFF + +/* MIDI MCUCH2 CH2B Mask */ +#define MIDI_MCUCH2_CH2B_MASK (u32)0xFFFF0000 + +/* MIDI MCUCH2 CH2A Mask */ +#define MIDI_MCUCH2_CH2A_MASK (u32)0x0000FFFF + +/* MIDI MCUCH3 CH3B Mask */ +#define MIDI_MCUCH3_CH3B_MASK (u32)0xFFFF0000 + +/* MIDI MCUCH3 CH3A Mask */ +#define MIDI_MCUCH3_CH3A_MASK (u32)0x0000FFFF + +/* MIDI CTRL MCUCHEN3 Mask */ +#define MCUCHEN3_ENABLE (u32)0x00008000 +#define MCUCHEN3_DISABLE (u32)0xFFFF7FFF + +/* MIDI CTRL MCUCHEN2 Mask */ +#define MCUCHEN2_ENABLE (u32)0x00004000 +#define MCUCHEN2_DISABLE (u32)0xFFFFBFFF + +/* MIDI CTRL MCUCHEN1 Mask */ +#define MCUCHEN1_ENABLE (u32)0x00002000 +#define MCUCHEN1_DISABLE (u32)0xFFFFDFFF + +/* MIDI CTRL MCUCHEN0 Mask */ +#define MCUCHEN0_ENABLE (u32)0x00001000 +#define MCUCHEN0_DISABLE (u32)0xFFFFEFFF + +/* MIDI CTRL DACDS Mask */ +#define MIDI_CTRL_DACDS_MASK (u32)0x00000700 + +/* MIDI CTRL MUSICEN Mask */ +#define MUSICEN_ENABLE (u32)0x00000080 +#define MUSICEN_DISABLE (u32)0xFFFFFF7F + +/* MIDI CTRL SPIRDEN Mask */ +#define SPIRDEN_ENABLE (u32)0x00000040 +#define SPIRDEN_DISABLE (u32)0xFFFFFFBF + +/* MIDI CTRL SPIDISLOOP Mask */ +#define SPIDISLOOP_ENABLE (u32)0x00000020 +#define SPIDISLOOP_DISABLE (u32)0xFFFFFFDF + +/* MIDI CTRL CHS Mask */ +#define MIDI_CTRL_CHS_MASK (u32)0x00000007 +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup MIDI_Exported_Functions MIDI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the MIDI peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void MIDI_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.MIDI = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the MIDIx peripheral according to the specified parameters in the MIDI_InitStruct. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param MIDI_InitStruct: pointer to a MIDI_InitTypeDef structure that contains the configuration + * information for the specified MIDI peripheral. + * @retval None + ***********************************************************************************************************/ +void MIDI_Init(HT_MIDI_TypeDef* MIDIx, MIDI_InitTypeDef* MIDI_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_CTRL_DACDS(MIDI_InitStruct->MIDI_CTRL_DACDS)); + Assert_Param(IS_MIDI_CTRL_MUSICEN(MIDI_InitStruct->MIDI_CTRL_MUSICEN)); + Assert_Param(IS_MIDI_CTRL_SPIDISLOOP(MIDI_InitStruct->MIDI_CTRL_SPIDISLOOP)); + Assert_Param(IS_MIDI_CTRL_CHS(MIDI_InitStruct->MIDI_CTRL_CHS)); + Assert_Param(IS_MIDI_FREQ_BL(MIDI_InitStruct->MIDI_FREQ_BL)); + Assert_Param(IS_MIDI_FREQ_FR(MIDI_InitStruct->MIDI_FREQ_FR)); + Assert_Param(IS_MIDI_VOL_AR(MIDI_InitStruct->MIDI_VOL_AR)); + Assert_Param(IS_MIDI_VOL_ENV(MIDI_InitStruct->MIDI_VOL_ENV)); + Assert_Param(IS_MIDI_VOL_VL(MIDI_InitStruct->MIDI_VOL_VL)); + Assert_Param(IS_MIDI_VOL_VR(MIDI_InitStruct->MIDI_VOL_VR)); + Assert_Param(IS_MIDI_STADDR(MIDI_InitStruct->MIDI_STADDR)); + Assert_Param(IS_MIDI_RENUM_WBS(MIDI_InitStruct->MIDI_RENUM_WBS)); + Assert_Param(IS_MIDI_RENUM_RE(MIDI_InitStruct->MIDI_RENUM_RE)); + Assert_Param(IS_MIDI_ENDADDR(MIDI_InitStruct->MIDI_ENDADDR)); + Assert_Param(IS_MIDI_CHAN_ST(MIDI_InitStruct->MIDI_CHAN_ST)); + Assert_Param(IS_MIDI_CHAN_VM(MIDI_InitStruct->MIDI_CHAN_VM)); + Assert_Param(IS_MIDI_CHAN_FR(MIDI_InitStruct->MIDI_CHAN_FR)); + Assert_Param(IS_MIDI_CHAN_CHx(MIDI_InitStruct->MIDI_CHAN_CHx)); + + MIDIx->CTRL = ((MIDI_InitStruct->MIDI_CTRL_DACDS) << 8) | + ((MIDI_InitStruct->MIDI_CTRL_MUSICEN) << 7) | + ((MIDI_InitStruct->MIDI_CTRL_SPIDISLOOP) << 6) | + (MIDI_InitStruct->MIDI_CTRL_CHS); + + MIDIx->FREQ = ((MIDI_InitStruct->MIDI_FREQ_BL) << 12) | + (MIDI_InitStruct->MIDI_FREQ_FR); + + MIDIx->VOL = ((MIDI_InitStruct->MIDI_VOL_AR) << 31) | + ((MIDI_InitStruct->MIDI_VOL_ENV) << 29) | + ((MIDI_InitStruct->MIDI_VOL_VL) << 16) | + (MIDI_InitStruct->MIDI_VOL_VR); + + MIDIx->ST_ADDR = MIDI_InitStruct->MIDI_STADDR; + + MIDIx->RE_NUM = ((MIDI_InitStruct->MIDI_RENUM_WBS) << 16) | + (MIDI_InitStruct->MIDI_RENUM_RE); + + MIDIx->END_ADDR = MIDI_InitStruct->MIDI_ENDADDR; + + MIDIx->CHAN = ((MIDI_InitStruct->MIDI_CHAN_ST) << 10) | + ((MIDI_InitStruct->MIDI_CHAN_VM) << 9) | + ((MIDI_InitStruct->MIDI_CHAN_FR) << 8) | + (MIDI_InitStruct->MIDI_CHAN_CHx); +} + +/*********************************************************************************************************//** + * @brief Fill each MIDI_InitStruct member with its default value. + * @param MIDI_InitStruct: pointer to an MIDI_InitTypeDef structure which will be initialized. + * @retval None + ***********************************************************************************************************/ +void MIDI_StructInit(MIDI_InitTypeDef* MIDI_InitStruct) +{ + /* Initialize the MIDI_CTRL_DACDS member */ + MIDI_InitStruct->MIDI_CTRL_DACDS = 0x0; + + /* Initialize the MIDI_CTRL_MUSICEN member */ + MIDI_InitStruct->MIDI_CTRL_MUSICEN = DISABLE; + + /* Initialize the MIDI_CTRL_SPIDISLOOP member */ + MIDI_InitStruct->MIDI_CTRL_SPIDISLOOP = DISABLE; + + /* Initialize the MIDI_CTRL_CHS member */ + MIDI_InitStruct->MIDI_CTRL_CHS = CHS16; + + /* Initialize the MIDI_FREQ_BL member */ + MIDI_InitStruct->MIDI_FREQ_BL = BL0; + + /* Initialize the MIDI_FREQ_FR member */ + MIDI_InitStruct->MIDI_FREQ_FR = 0x0; + + /* Initialize the MIDI_VOL_AR member */ + MIDI_InitStruct->MIDI_VOL_AR = ENV_RELEASE; + + /* Initialize the MIDI_VOL_ENV member */ + MIDI_InitStruct->MIDI_VOL_ENV = ENV_NO; + + /* Initialize the MIDI_VOL_VL member */ + MIDI_InitStruct->MIDI_VOL_VL = 0x3FF; + + /* Initialize the MIDI_VOL_VR member */ + MIDI_InitStruct->MIDI_VOL_VR = 0x3FF; + + /* Initialize the MIDI_STADDR member */ + MIDI_InitStruct->MIDI_STADDR = 0x0; + + /* Initialize the MIDI_RENUM_WBS member */ + MIDI_InitStruct->MIDI_RENUM_WBS = WBS8; + + /* Initialize the MIDI_RENUM_RE member */ + MIDI_InitStruct->MIDI_RENUM_RE = 0x0; + + /* Initialize the MIDI_ENDADDR member */ + MIDI_InitStruct->MIDI_ENDADDR = 0x0; + + /* Initialize the MIDI_CHAN_ST member */ + MIDI_InitStruct->MIDI_CHAN_ST = DISABLE; + + /* Initialize the MIDI_CHAN_VM member */ + MIDI_InitStruct->MIDI_CHAN_VM = DISABLE; + + /* Initialize the MIDI_CHAN_FR member */ + MIDI_InitStruct->MIDI_CHAN_FR = DISABLE; + + /* Initialize the MIDI_CHAN_CHx member */ + MIDI_InitStruct->MIDI_CHAN_CHx = MIDI_CHx0; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified MIDI interrupt. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param MIDI_Int: specify if the MIDI interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg MIDIO_DMAEN : MIDIO DMAEN + * @arg MIDII_DMAEN : MIDII DMAEN + * @arg MIDI_INTEN : MIDI INTEN + * @param NewState: new state of the MIDI interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_IntConfig(HT_MIDI_TypeDef* MIDIx, u32 MIDI_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_INT(MIDI_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->IER |= MIDI_Int; + } + else + { + MIDIx->IER &= (u32)~MIDI_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified MIDI flag has been set or not. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param MIDI_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg MIDI_INTF : MIDI int flag + * @retval The new state of MIDI_Flag (SET or RESET). + ***********************************************************************************************************/ +FlagStatus MIDI_GetFlagStatus(HT_MIDI_TypeDef* MIDIx, u32 MIDI_Flag) +{ + FlagStatus bitstatus = RESET; + u32 statusreg = 0; + + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_FLAG(MIDI_Flag)); + + statusreg = MIDIx->SR; + + if ((statusreg & MIDI_Flag) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Clear the specified MIDI flag. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param MIDI_Flag: specify the flag that is to be cleared. + * This parameter can be one of the following values: + * @arg MIDI_INTF : MIDI INTF + * @retval None + ***********************************************************************************************************/ +void MIDI_ClearFlag(HT_MIDI_TypeDef* MIDIx, u32 MIDI_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_FLAG_CLEAR(MIDI_Flag)); + + MIDIx->SR = MIDI_Flag; +} + +/*********************************************************************************************************//** + * @brief Configure the Channel for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param MCUCHEN3: this parameter can be ENABLE or DISABLE. + * @param MCUCHEN2: this parameter can be ENABLE or DISABLE. + * @param MCUCHEN1: this parameter can be ENABLE or DISABLE. + * @param MCUCHEN0: this parameter can be ENABLE or DISABLE. + * @param DACDS: specify the clipping and distorting volume of the MIDI. + * @param MUSICEN: this parameter can be ENABLE or DISABLE. + * @param SPIRDEN: this parameter can be ENABLE or DISABLE. + * @param SPIDISLOOP: this parameter can be ENABLE or DISABLE. + * @param CHS: specify channel selection of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL(HT_MIDI_TypeDef* MIDIx, + MIDI_CTRL_MCUCHEN3_Enum MCUCHEN3, MIDI_CTRL_MCUCHEN2_Enum MCUCHEN2, + MIDI_CTRL_MCUCHEN1_Enum MCUCHEN1, MIDI_CTRL_MCUCHEN0_Enum MCUCHEN0, + u8 DACDS, + MIDI_CTRL_MUSICEN_Enum MUSICEN, + MIDI_CTRL_SPIRDEN_Enum SPIRDEN, MIDI_CTRL_SPIDISLOOP_Enum SPIDISLOOP, + MIDI_CTRL_CHS_Enum CHS) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_CTRL_MCUCHEN3(MCUCHEN3)); + Assert_Param(IS_MIDI_CTRL_MCUCHEN2(MCUCHEN2)); + Assert_Param(IS_MIDI_CTRL_MCUCHEN1(MCUCHEN1)); + Assert_Param(IS_MIDI_CTRL_MCUCHEN0(MCUCHEN0)); + Assert_Param(IS_MIDI_CTRL_DACDS(DACDS)); + Assert_Param(IS_MIDI_CTRL_MUSICEN(MUSICEN)); + Assert_Param(IS_MIDI_CTRL_SPIRDEN(SPIRDEN)); + Assert_Param(IS_MIDI_CTRL_SPIDISLOOP(SPIDISLOOP)); + Assert_Param(IS_MIDI_CTRL_CHS(CHS)); + + MIDIx->CTRL = (MCUCHEN3 << 15) | (MCUCHEN2 << 14) | (MCUCHEN1 << 13) | (MCUCHEN0 << 12) | + (DACDS << 8) | + (MUSICEN << 7) | + (SPIRDEN << 6) | (SPIDISLOOP << 5) | + CHS; +} + +/*********************************************************************************************************//** + * @brief Configure the FREQ for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param BL: specify octave of the MIDI. + * @param FR: specify pitch of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_FREQ(HT_MIDI_TypeDef* MIDIx, MIDI_FREQ_BL_Enum BL, u16 FR) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_FREQ_BL(BL)); + Assert_Param(IS_MIDI_FREQ_FR(FR)); + + MIDIx->FREQ = (BL << 12) | FR; +} + +/*********************************************************************************************************//** + * @brief Configure the VOL for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param A_R: specify attack or release of the MIDI. + * @param ENV: specify envelope of the MIDI. + * @param VL: specify left channel of the MIDI. + * @param VR: specify right channel of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_VOL(HT_MIDI_TypeDef* MIDIx, MIDI_VOL_AR_Enum A_R, MIDI_VOL_ENV_Enum ENV, u16 VL, u16 VR) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_VOL_AR(A_R)); + Assert_Param(IS_MIDI_VOL_ENV(ENV)); + Assert_Param(IS_MIDI_VOL_VL(VL)); + Assert_Param(IS_MIDI_VOL_VR(VR)); + + MIDIx->VOL = (A_R << 31) | (ENV << 29) | (VL << 16) | VR; +} + +/*********************************************************************************************************//** + * @brief Configure the Start Address for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param ST_ADDR: specify start address of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_STADDR(HT_MIDI_TypeDef* MIDIx, u32 ST_ADDR) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_STADDR(ST_ADDR)); + + MIDIx->ST_ADDR = ST_ADDR; +} + +/*********************************************************************************************************//** + * @brief Configure the RENUM for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param WBS: specify waveform of the MIDI. + * @param RE: specify repeated code of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_RENUM(HT_MIDI_TypeDef* MIDIx, MIDI_RENUM_WBS_Enum WBS, u16 RE) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_RENUM_WBS(WBS)); + Assert_Param(IS_MIDI_RENUM_RE(RE)); + + MIDIx->RE_NUM = (WBS << 16) | RE; +} + +/*********************************************************************************************************//** + * @brief Configure the End Address for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param END_ADDR: specify end address of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_ENDADDR(HT_MIDI_TypeDef* MIDIx, u32 END_ADDR) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_ENDADDR(END_ADDR)); + + MIDIx->END_ADDR = END_ADDR; +} + +/*********************************************************************************************************//** + * @brief Configure the Channel for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param TRIG_ST: this parameter can be ENABLE or DISABLE. + * @param TRIG_VM: this parameter can be ENABLE or DISABLE. + * @param TRIG_FR: this parameter can be ENABLE or DISABLE. + * @param CHx: specify selected channel of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_CHAN(HT_MIDI_TypeDef* MIDIx, + MIDI_CHAN_ST_Enum TRIG_ST, MIDI_CHAN_VM_Enum TRIG_VM, MIDI_CHAN_FR_Enum TRIG_FR, + u8 CHx) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_CHAN_ST(TRIG_ST)); + Assert_Param(IS_MIDI_CHAN_VM(TRIG_VM)); + Assert_Param(IS_MIDI_CHAN_FR(TRIG_FR)); + Assert_Param(IS_MIDI_CHAN_CHx(CHx)); + + MIDIx->CHAN = (TRIG_ST << 10) | (TRIG_VM << 9) | (TRIG_FR << 8) | CHx; +} + +/*********************************************************************************************************//** + * @brief Configure the MCU CH0 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH0B: specify DATA[31:16] of MCU CH0 of the MIDI. + * @param CH0A: specify DATA[15:0] of MCU CH0 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH0(HT_MIDI_TypeDef* MIDIx, u16 CH0B, u16 CH0A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx11_BH(CH0B)); + Assert_Param(IS_MIDI_MCUCHx11_BL(CH0A)); + + MIDIx->MCU_CH0 = (CH0B << 16) | CH0A; +} + +/*********************************************************************************************************//** + * @brief Configure the MCU CH1 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH1B: specify DATA[31:16] of MCU CH1 of the MIDI. + * @param CH1A: specify DATA[15:0] of MCU CH1 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH1(HT_MIDI_TypeDef* MIDIx, u16 CH1B, u16 CH1A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx12_CH(CH1B)); + Assert_Param(IS_MIDI_MCUCHx12_CL(CH1A)); + + MIDIx->MCU_CH1 = (CH1B << 16) | CH1A; +} + +/*********************************************************************************************************//** + * @brief Configure the MCU CH2 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH2B: specify DATA[31:16] of MCU CH2 of the MIDI. + * @param CH2A: specify DATA[15:0] of MCU CH2 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH2(HT_MIDI_TypeDef* MIDIx, u16 CH2B, u16 CH2A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx13_DH(CH2B)); + Assert_Param(IS_MIDI_MCUCHx13_DL(CH2A)); + + MIDIx->MCU_CH2 = (CH2B << 16) | CH2A; +} + +/*********************************************************************************************************//** + * @brief Configure the MCU CH3 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH3B: specify DATA[31:16] of MCU CH3 of the MIDI. + * @param CH3A: specify DATA[15:0] of MCU CH3 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH3(HT_MIDI_TypeDef* MIDIx, u16 CH3B, u16 CH3A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx14_EH(CH3B)); + Assert_Param(IS_MIDI_MCUCHx14_EL(CH3A)); + + MIDIx->MCU_CH3 = (CH3B << 16) | CH3A; +} + +/*********************************************************************************************************//** + * @brief Configure the FREQ BL for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param BL: specify octave of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_FREQ_BL(HT_MIDI_TypeDef* MIDIx, MIDI_FREQ_BL_Enum BL) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_FREQ_BL(BL)); + + /* Clear BL[3:0] in FREQ */ + MIDIx->FREQ &= (u32)~MIDI_FREQ_BL_MASK; + + /* Set new BL[3:0] in FREQ */ + MIDIx->FREQ |= (BL << 12); +} + +/*********************************************************************************************************//** + * @brief Configure the FREQ FR for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param FR: specify pitch of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_FREQ_FR(HT_MIDI_TypeDef* MIDIx, u16 FR) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_FREQ_FR(FR)); + + /* Clear FR[11:0] in FREQ */ + MIDIx->FREQ &= (u32)~MIDI_FREQ_FR_MASK; + + /* Set new FR[11:0] in FREQ */ + MIDIx->FREQ |= FR; +} + +/*********************************************************************************************************//** + * @brief Configure the VOL AR for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param A_R: specify attack or release of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_VOL_AR(HT_MIDI_TypeDef* MIDIx, MIDI_VOL_AR_Enum A_R) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_VOL_AR(A_R)); + + /* Clear A_R in VOL */ + MIDIx->VOL &= (u32)~MIDI_VOL_AR_MASK; + + /* Set new A_R in VOL */ + MIDIx->VOL |= (A_R << 31); +} + +/*********************************************************************************************************//** + * @brief Configure the VOL ENV for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param ENV: specify envelope of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_VOL_ENV(HT_MIDI_TypeDef* MIDIx, MIDI_VOL_ENV_Enum ENV) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_VOL_ENV(ENV)); + + /* Clear ENV[1:0] in VOL */ + MIDIx->VOL &= (u32)~MIDI_VOL_ENV_MASK; + + /* Set new ENV[1:0] in VOL */ + MIDIx->VOL |= (ENV << 29); +} + +/*********************************************************************************************************//** + * @brief Configure the VOL VL for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param VL: specify left channel of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_VOL_VL(HT_MIDI_TypeDef* MIDIx, u16 VL) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_VOL_VL(VL)); + + /* Clear VL[9:0] in VOL */ + MIDIx->VOL &= (u32)~MIDI_VOL_VL_MASK; + + /* Set new VL[9:0] in VOL */ + MIDIx->VOL |= (VL << 16); +} + +/*********************************************************************************************************//** + * @brief Configure the VOL VR for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param VR: specify right channel of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_VOL_VR(HT_MIDI_TypeDef* MIDIx, u16 VR) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_VOL_VR(VR)); + + /* Clear VR[9:0] in VOL */ + MIDIx->VOL &= (u32)~MIDI_VOL_VR_MASK; + + /* Set new VR[9:0] in VOL */ + MIDIx->VOL |= VR; +} + +/*********************************************************************************************************//** + * @brief Configure the RENUM WBS for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param WBS: specify waveform of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_RENUM_WBS(HT_MIDI_TypeDef* MIDIx, MIDI_RENUM_WBS_Enum WBS) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_RENUM_WBS(WBS)); + + /* Clear WBS[1:0] in RENUM */ + MIDIx->RE_NUM &= (u32)~MIDI_RENUM_WBS_MASK; + + /* Set new WBS[1:0] in RENUM */ + MIDIx->RE_NUM |= (WBS << 16); +} + +/*********************************************************************************************************//** + * @brief Configure the RENUM RE for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param RE: specify repeated code of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_RENUM_RE(HT_MIDI_TypeDef* MIDIx, u16 RE) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_RENUM_RE(RE)); + + /* Clear RE[14:0] in RENUM */ + MIDIx->RE_NUM &= (u32)~MIDI_RENUM_RE_MASK; + + /* Set new RE[14:0] in RENUM */ + MIDIx->RE_NUM |= RE; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable ST ADDR for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CHAN_STCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CHAN |= TRIG_ST_ENABLE; + } + else + { + MIDIx->CHAN &= (TRIG_ST_DISABLE); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable VM for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CHAN_VMCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CHAN |= TRIG_VM_ENABLE; + } + else + { + MIDIx->CHAN &= (TRIG_VM_DISABLE); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable FR for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CHAN_FRCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CHAN |= TRIG_FR_ENABLE; + } + else + { + MIDIx->CHAN &= (TRIG_FR_DISABLE); + } +} + +/*********************************************************************************************************//** + * @brief Configure the Selected Channel for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CHx: specify selected channel of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_CHAN_CHx(HT_MIDI_TypeDef* MIDIx, u8 CHx) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_CHAN_CHx(CHx)); + + /* Clear CHx[4:0] in CHAN */ + MIDIx->CHAN &= (u32)~MIDI_CHAN_CHx_MASK; + + /* Set new CHx[4:0] in CHAN */ + MIDIx->CHAN |= CHx; +} + +/*********************************************************************************************************//** + * @brief Configure the CH0B of MCU CH0 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH0B: specify DATA[31:16] of MCU CH0 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH0_CH0B(HT_MIDI_TypeDef* MIDIx, u16 CH0B) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx11_BH(CH0B)); + + /* Clear CH0B[16:0] in MCUCH0 */ + MIDIx->MCU_CH0 &= (u32)~MIDI_MCUCH0_CH0B_MASK; + + /* Set new CH0B[16:0] in MCUCH0 */ + MIDIx->MCU_CH0 |= (CH0B << 16); +} + +/*********************************************************************************************************//** + * @brief Configure the CH0A of MCU CH0 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH0A: specify DATA[15:0] of MCU CH0 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH0_CH0A(HT_MIDI_TypeDef* MIDIx, u16 CH0A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx11_BL(CH0A)); + + /* Clear CH0B[16:0] in MCUCH0 */ + MIDIx->MCU_CH0 &= (u32)~MIDI_MCUCH0_CH0A_MASK; + + /* Set new CH0B[16:0] in MCUCH0 */ + MIDIx->MCU_CH0 |= CH0A; +} + +/*********************************************************************************************************//** + * @brief Configure the CH1B of MCU CH1 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH1B: specify DATA[31:16] of MCU CH1 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH1_CH1B(HT_MIDI_TypeDef* MIDIx, u16 CH1B) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx12_CH(CH1B)); + + /* Clear CH0B[16:0] in MCUCH0 */ + MIDIx->MCU_CH1 &= (u32)~MIDI_MCUCH1_CH1B_MASK; + + /* Set new CH1B[16:0] in MCUCH1 */ + MIDIx->MCU_CH1 |= (CH1B << 16); +} + +/*********************************************************************************************************//** + * @brief Configure the CH1A of MCU CH1 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH1A: specify DATA[15:0] of MCU CH1 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH1_CH1A(HT_MIDI_TypeDef* MIDIx, u16 CH1A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx12_CL(CH1A)); + + /* Clear CH1A[16:0] in MCUCH1 */ + MIDIx->MCU_CH1 &= (u32)~MIDI_MCUCH1_CH1A_MASK; + + /* Set new CH1A[16:0] in MCUCH1 */ + MIDIx->MCU_CH1 |= CH1A; +} + +/*********************************************************************************************************//** + * @brief Configure the CH2B of MCU CH2 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH2B: specify DATA[31:16] of MCU CH2 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH2_CH2B(HT_MIDI_TypeDef* MIDIx, u16 CH2B) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx13_DH(CH2B)); + + /* Clear CH2B[16:0] in MCUCH2 */ + MIDIx->MCU_CH2 &= (u32)~MIDI_MCUCH2_CH2B_MASK; + + /* Set new CH2B[16:0] in MCUCH2 */ + MIDIx->MCU_CH2 |= (CH2B << 16); +} + +/*********************************************************************************************************//** + * @brief Configure the CH2A of MCU CH2 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH2A: specify DATA[15:0] of MCU CH2 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH2_CH2A(HT_MIDI_TypeDef* MIDIx, u16 CH2A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx13_DL(CH2A)); + + /* Clear CH2A[16:0] in MCUCH2 */ + MIDIx->MCU_CH2 &= (u32)~MIDI_MCUCH2_CH2A_MASK; + + /* Set new CH2A[16:0] in MCUCH2 */ + MIDIx->MCU_CH2 |= CH2A; +} + +/*********************************************************************************************************//** + * @brief Configure the CH3B of MCU CH3 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH3B: specify DATA[31:16] of MCU CH3 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH3_CH3B(HT_MIDI_TypeDef* MIDIx, u16 CH3B) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx14_EH(CH3B)); + + /* Clear CH3B[16:0] in MCUCH3 */ + MIDIx->MCU_CH3 &= (u32)~MIDI_MCUCH3_CH3B_MASK; + + /* Set new CH3B[16:0] in MCUCH3 */ + MIDIx->MCU_CH3 |= (CH3B << 16); +} + +/*********************************************************************************************************//** + * @brief Configure the CH3A of MCU CH3 DATA for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CH3A: specify DATA[15:0] of MCU CH3 of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_MCUCH3_CH3A(HT_MIDI_TypeDef* MIDIx, u16 CH3A) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_MCUCHx14_EL(CH3A)); + + /* Clear CH3A[16:0] in MCUCH3 */ + MIDIx->MCU_CH3 &= (u32)~MIDI_MCUCH3_CH3A_MASK; + + /* Set new CH3A[16:0] in MCUCH3 */ + MIDIx->MCU_CH3 |= CH3A; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable MCU CHEN3 for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_MCUCHEN3(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CTRL |= MCUCHEN3_ENABLE; + } + else + { + MIDIx->CTRL &= MCUCHEN3_DISABLE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable MCU CHEN2 for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_MCUCHEN2(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CTRL |= MCUCHEN2_ENABLE; + } + else + { + MIDIx->CTRL &= MCUCHEN2_DISABLE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable MCU CHEN1 for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_MCUCHEN1(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CTRL |= MCUCHEN1_ENABLE; + } + else + { + MIDIx->CTRL &= MCUCHEN1_DISABLE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable MCU CHEN0 for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_MCUCHEN0(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CTRL |= MCUCHEN0_ENABLE; + } + else + { + MIDIx->CTRL &= MCUCHEN0_DISABLE; + } +} + + +/*********************************************************************************************************//** + * @brief Configure the DACDS for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param DACDS: specify the clipping and distorting volume of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_DACDS(HT_MIDI_TypeDef* MIDIx, u8 DACDS) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_CTRL_DACDS(DACDS)); + + /* Clear DACDS[2:0] in CTRL */ + MIDIx->CTRL &= (u32)~MIDI_CTRL_DACDS_MASK; + + /* Set new DACDS[2:0] in CTRL */ + MIDIx->CTRL |= (DACDS << 8); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable MUSIC Engine for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_MUSICENCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CTRL |= MUSICEN_ENABLE; + } + else + { + MIDIx->CTRL &= MUSICEN_DISABLE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable SPI RDEN for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_SPIRDENCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CTRL |= SPIRDEN_ENABLE; + } + else + { + MIDIx->CTRL &= SPIRDEN_DISABLE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable SPI DISLOOP for the specified MIDI peripheral. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param NewState: new state of the MIDIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_SPIDISLOOPCmd(HT_MIDI_TypeDef* MIDIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + MIDIx->CTRL |= SPIDISLOOP_ENABLE; + } + else + { + MIDIx->CTRL &= SPIDISLOOP_DISABLE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the Channel Selection for the selected MIDI. + * @param MIDIx: where MIDIx is the selected MIDI from the MIDI peripherals. + * @param CHS: specify channel selection of the MIDI. + * @retval None + ***********************************************************************************************************/ +void MIDI_CTRL_CHS(HT_MIDI_TypeDef* MIDIx, u8 CHS) +{ + /* Check the parameters */ + Assert_Param(IS_MIDI(MIDIx)); + Assert_Param(IS_MIDI_CTRL_CHS(CHS)); + + /* Clear CHS[2:0] in CTRL */ + MIDIx->CTRL &= (u32)~MIDI_CTRL_CHS_MASK; + + /* Set new CHS[2:0] in CTRL */ + MIDIx->CTRL |= CHS; +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pdma.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pdma.c new file mode 100644 index 00000000000..4d7929e5ad5 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pdma.c @@ -0,0 +1,312 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_pdma.c + * @version $Rev:: 6479 $ + * @date $Date:: 2022-11-23 #$ + * @brief This file provides all the PDMA firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_pdma.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup PDMA PDMA + * @brief PDMA driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup PDMA_Exported_Functions PDMA exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the PDMA peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void PDMA_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.PDMA = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure specific PDMA channel + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param PDMACH_InitStruct: pointer to a PDMACH_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void PDMA_Config(u32 PDMA_CHn, PDMACH_InitTypeDef *PDMACH_InitStruct) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_WIDTH(PDMACH_InitStruct->PDMACH_DataSize)); + Assert_Param(IS_PDMA_PRIO(PDMACH_InitStruct->PDMACH_Priority)); + Assert_Param(IS_PDMA_ADR_MOD(PDMACH_InitStruct->PDMACH_AdrMod)); + Assert_Param(IS_PDMA_BLK_CNT(PDMACH_InitStruct->PDMACH_BlkCnt)); + Assert_Param(IS_PDMA_BLK_LEN(PDMACH_InitStruct->PDMACH_BlkLen)); + + /* PDMA channel x configuration */ + PDMACHx->CR = (PDMACH_InitStruct->PDMACH_DataSize | PDMACH_InitStruct->PDMACH_Priority | PDMACH_InitStruct->PDMACH_AdrMod); + + PDMACHx->SADR = PDMACH_InitStruct->PDMACH_SrcAddr; + + PDMACHx->DADR = PDMACH_InitStruct->PDMACH_DstAddr; + + PDMACHx->TSR = (PDMACH_InitStruct->PDMACH_BlkCnt << 16) | PDMACH_InitStruct->PDMACH_BlkLen; +} + +/*********************************************************************************************************//** + * @brief PDMA_AddrConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param SrcAddr: Source address + * @param DstAddr: Destination address + * @retval None + ************************************************************************************************************/ +void PDMA_AddrConfig(u32 PDMA_CHn, u32 SrcAddr, u32 DstAddr) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + /* transfer address configuration */ + PDMACHx->SADR = SrcAddr; + PDMACHx->DADR = DstAddr; +} + +/*********************************************************************************************************//** + * @brief PDMA_SrcAddrConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param SrcAddr: Source address + * @retval None + ************************************************************************************************************/ +void PDMA_SrcAddrConfig(u32 PDMA_CHn, u32 SrcAddr) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + /* transfer address configuration */ + PDMACHx->SADR = SrcAddr; +} + +/*********************************************************************************************************//** + * @brief PDMA_DstAddrConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param DstAddr: Destination address + * @retval None + ************************************************************************************************************/ +void PDMA_DstAddrConfig(u32 PDMA_CHn, u32 DstAddr) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + /* transfer address configuration */ + PDMACHx->DADR = DstAddr; +} + +/*********************************************************************************************************//** + * @brief PDMA_TranSizeConfig + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param BlkCnt: Number of blocks for a transfer + * @param BlkLen: Number of data for a block + * @retval None + ************************************************************************************************************/ +void PDMA_TranSizeConfig(u32 PDMA_CHn, u16 BlkCnt, u16 BlkLen) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_BLK_CNT(BlkCnt)); + Assert_Param(IS_PDMA_BLK_LEN(BlkLen)); + + /* transfer size configuration */ + PDMACHx->TSR = ((BlkCnt << 16) | BlkLen); +} + +/*********************************************************************************************************//** + * @brief Enable the specific PDMA channel interrupts + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param PDMA_INT_x: PDMA_INT_GE, PDMA_INT_BE, PDMA_INT_HT, PDMA_INT_TC, PDMA_INT_TE + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PDMA_IntConfig(u32 PDMA_CHn, u32 PDMA_INT_x, ControlStatus NewState) +{ + u32 uRegTmp = 0; + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_INT(PDMA_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + #if (LIBCFG_PDMA_CH3FIX) + if (PDMA_CHn == PDMA_CH3) + { + if (PDMA_INT_x & PDMA_INT_BE) + { + uRegTmp |= (PDMA_INT_BE << (PDMA_CH2 * 5)); + } + if (PDMA_INT_x & PDMA_INT_HT) + { + uRegTmp |= (PDMA_INT_HT << (PDMA_CH2 * 5)); + } + } + #endif + + if (NewState != DISABLE) + { + HT_PDMA->IER |= ((PDMA_INT_x << (PDMA_CHn * 5)) | uRegTmp); + } + else + { + HT_PDMA->IER &= ~(PDMA_INT_x << (PDMA_CHn * 5)); + } +} + +/*********************************************************************************************************//** + * @brief Enable a specific PDMA channel + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PDMA_EnaCmd(u32 PDMA_CHn, ControlStatus NewState) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + PDMACHx->CR |= (1UL); + } + else + { + PDMACHx->CR &= ~(1UL); + } +} + +/*********************************************************************************************************//** + * @brief Software trigger a specific PDMA channel + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PDMA_SwTrigCmd(u32 PDMA_CHn, ControlStatus NewState) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + PDMACHx->CR |= (1UL << 1); + } + else + { + PDMACHx->CR &= ~(1UL << 1); + } +} + +/*********************************************************************************************************//** + * @brief Get the specific PDMA channel interrupt flag + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param PDMA_FLAG_x: PDMA_FLAG_GE, PDMA_FLAG_BE, PDMA_FLAG_HT, PDMA_FLAG_TC, PDMA_FLAG_TE + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus PDMA_GetFlagStatus(u32 PDMA_CHn, u32 PDMA_FLAG_x) +{ + /* !!! NOTICE !!! + Must turn on the PDMA IER to get the ISR flag. + For example: PDMA_GetFlagStatus(PDMA_CH0, PDMA_INT_TC, ENABLE); + */ + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_FLAG(PDMA_FLAG_x)); + + if (HT_PDMA->ISR & (PDMA_FLAG_x << PDMA_CHn * 5)) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specific PDMA channel interrupt flags + * @param PDMA_CHn: PDMA_CH0 ~ PDMA_CH5 + * @param PDMA_FLAG_x: PDMA_FLAG_GE, PDMA_FLAG_BE, PDMA_FLAG_HT, PDMA_FLAG_TC, PDMA_FLAG_TE + * @retval None + ************************************************************************************************************/ +void PDMA_ClearFlag(u32 PDMA_CHn, u32 PDMA_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + Assert_Param(IS_PDMA_CLEAR_FLAG(PDMA_FLAG_x)); + + HT_PDMA->ISCR |= (PDMA_FLAG_x << PDMA_CHn * 5); +} + +/*********************************************************************************************************//** + * @brief Get remain block count of the specific PDMA channel + * @retval CBLKCNT + ************************************************************************************************************/ +u16 PDMA_GetRemainBlkCnt(u32 PDMA_CHn) +{ + HT_PDMACH_TypeDef *PDMACHx = (HT_PDMACH_TypeDef *)(HT_PDMA_BASE + PDMA_CHn * 6 * 4); + + /* Check the parameters */ + Assert_Param(IS_PDMA_CH(PDMA_CHn)); + + return ((PDMACHx->CTSR) >> 16); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwm.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwm.c new file mode 100644 index 00000000000..b824c72b168 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwm.c @@ -0,0 +1,2 @@ +The SCTM, PWM, GPTM, and MCTM timer have similar architecture. They use the same driver, +"ht32fxxxxx_tm.c/.h" to save the code size. For those timers, please refet to the TM driver/example. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwrcu.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwrcu.c new file mode 100644 index 00000000000..0ab83cf9195 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_pwrcu.c @@ -0,0 +1,846 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_pwrcu.c + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief This file provides all the Power Control Unit firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_pwrcu.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup PWRCU PWRCU + * @brief PWRCU driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Private_Define PWRCU private definitions + * @{ + */ +#define Set_RTCEN SetBit_BB((u32)&HT_CKCU->APBCCR1, 6); +#define Reset_RTCEN ResetBit_BB((u32)&HT_CKCU->APBCCR1, 6); +#define Get_RTCEN GetBit_BB((u32)&HT_CKCU->APBCCR1, 6) + +#define Set_LDOMODE SetBit_BB((u32)&HT_PWRCU->CR, 2) +#define Reset_LDOMODE ResetBit_BB((u32)&HT_PWRCU->CR, 2) + +#define Set_LDOOFF SetBit_BB((u32)&HT_PWRCU->CR, 3) +#define Reset_LDOOFF ResetBit_BB((u32)&HT_PWRCU->CR, 3) + +#define Set_DMOSON SetBit_BB((u32)&HT_PWRCU->CR, 7) +#define Reset_DMOSON ResetBit_BB((u32)&HT_PWRCU->CR, 7) + +#define Set_WUP0EN SetBit_BB((u32)&HT_PWRCU->CR, 8) +#define Reset_WUP0EN ResetBit_BB((u32)&HT_PWRCU->CR, 8) + +#if (LIBCFG_PWRCU_WAKEUP1) +#define Set_WUP1EN SetBit_BB((u32)&HT_PWRCU->CR, 10) +#define Reset_WUP1EN ResetBit_BB((u32)&HT_PWRCU->CR, 10) +#endif + +#if (LIBCFG_PWRCU_V15_READY_SOURCE) +#define Set_V15RDYSC SetBit_BB((u32)&HT_PWRCU->CR, 12) +#define Reset_V15RDYSC ResetBit_BB((u32)&HT_PWRCU->CR, 12) +#endif + +#define Set_DMOSSTS SetBit_BB((u32)&HT_PWRCU->CR, 15) +#define Reset_DMOSSTS ResetBit_BB((u32)&HT_PWRCU->CR, 15) +#define Get_DMOSSTS GetBit_BB((u32)&HT_PWRCU->CR, 15) + +#define Set_BODEN SetBit_BB((u32)&HT_PWRCU->LVDCSR, 0) +#define Reset_BODEN ResetBit_BB((u32)&HT_PWRCU->LVDCSR, 0) + +#define Set_BODRIS SetBit_BB((u32)&HT_PWRCU->LVDCSR, 1) +#define Reset_BODRIS ResetBit_BB((u32)&HT_PWRCU->LVDCSR, 1) + +#define Set_BODF SetBit_BB((u32)&HT_PWRCU->LVDCSR, 3) +#define Reset_BODF ResetBit_BB((u32)&HT_PWRCU->LVDCSR, 3) +#define Get_BODF GetBit_BB((u32)&HT_PWRCU->LVDCSR, 3) + +#define Set_LVDEN SetBit_BB((u32)&HT_PWRCU->LVDCSR, 16) +#define Reset_LVDEN ResetBit_BB((u32)&HT_PWRCU->LVDCSR, 16) + +#define Set_LVDF SetBit_BB((u32)&HT_PWRCU->LVDCSR, 19) +#define Reset_LVDF ResetBit_BB((u32)&HT_PWRCU->LVDCSR, 19) +#define Get_LVDF GetBit_BB((u32)&HT_PWRCU->LVDCSR, 19) + +#define Set_LVDIWEN SetBit_BB((u32)&HT_PWRCU->LVDCSR, 20) +#define Reset_LVDIWEN ResetBit_BB((u32)&HT_PWRCU->LVDCSR, 20) + +#define Set_LVDEWEN SetBit_BB((u32)&HT_PWRCU->LVDCSR, 21) +#define Reset_LVDEWEN ResetBit_BB((u32)&HT_PWRCU->LVDCSR, 21) + +#define SLEEPDEEP_SET 0x04 /*!< Cortex SLEEPDEEP bit */ + +#define PWRRST_SET 0x1 +#define PWRTEST_READY 0x27 +#define TIME_OUT 24000000 +#define WUP0TYPE_MASK 0xFFFCFFFF +#define WUP1TYPE_MASK 0xFFF3FFFF +#define LVDS_MASK 0xFFB9FFFF +#define VREG_V_MASK 0xF3FFFFFF +#define VREG_M_MASK 0xFCFFFFFF +#define PWRRST_SET 0x1 +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup PWRCU_Exported_Functions PWRCU exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize backup domain which contains PWRCU and RTC units. + * @retval None + ************************************************************************************************************/ +void PWRCU_DeInit(void) +{ + HT_PWRCU->CR = PWRRST_SET; + while(HT_PWRCU->CR & 0xFFFFEFFF); /* Skip Bit 12 because it isn't of valuable reference. */ + #if (LIBCFG_PWRCU_NO_PORF) + #else + while (HT_PWRCU->SR); /* Waits until the PWRPORF be cleared by read */ + #endif +} + +#if (!LIBCFG_NO_PWRCU_TEST_REG) +/*********************************************************************************************************//** + * @brief Waits, until the PWRCU can be accessed. + * @retval PWRCU_TIMEOUT or PWRCU_OK + ************************************************************************************************************/ +PWRCU_Status PWRCU_CheckReadyAccessed(void) +{ + u32 wTimeOutCnt = TIME_OUT; + + while (--wTimeOutCnt) + { + if (HT_PWRCU->TEST == PWRTEST_READY) + { + return PWRCU_OK; + } + } + return PWRCU_TIMEOUT; +} +#endif + +/*********************************************************************************************************//** + * @brief Return the flags of PWRCU. + * @retval This function will return one of the following: + * - 0x0000 : There is no flag is set. + * - 0x0001 (PWRCU_FLAG_PWRPOR) : VDD power domain power-on reset flag has been set. + * - 0x0002 (PWRCU_FLAG_PD) : Power-Down flag has been set. + * - 0x0010 (PWRCU_FLAG_POR) : Power-on reset flag has been set. + * - 0x0100 (PWRCU_FLAG_WUP0) : External WAKEUP0 pin flag has been set. + * - 0x0200 (PWRCU_FLAG_WUP1) : External WAKEUP1 pin flag has been set. + ************************************************************************************************************/ +u16 PWRCU_GetFlagStatus(void) +{ + return HT_PWRCU->SR; +} + +#if (LIBCFG_BAKREG) +/*********************************************************************************************************//** + * @brief Return the value of specified backup register. + * @param BAKREGx: Number of backup register. Where x can be 0 ~ 9. + * @return Between 0x0 ~ 0xFFFFFFFF. + ************************************************************************************************************/ +u32 PWRCU_ReadBackupRegister(PWRCU_BAKREG_Enum BAKREGx) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_BAKREG(BAKREGx)); + + return HT_PWRCU->BAKREG[BAKREGx]; +} + +/*********************************************************************************************************//** + * @brief Write the DATA to specified backup register. + * @param BAKREGx : Number of backup registers. Where x can be 0 ~ 9. + * @param DATA : Must between 0x0 ~ 0xFFFFFFFF. + * @retval None + ************************************************************************************************************/ +void PWRCU_WriteBackupRegister(PWRCU_BAKREG_Enum BAKREGx, u32 DATA) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_BAKREG(BAKREGx)); + + HT_PWRCU->BAKREG[BAKREGx] = DATA; +} +#endif + +/*********************************************************************************************************//** + * @brief Enter SLEEP mode. + * @param SleepEntry : Enters sleep mode instruction that is used to WFI or WFE. + * This parameter can be one of the following values: + * @arg PWRCU_SLEEP_ENTRY_WFE : Enters SLEEP mode via WFE instruction + * @arg PWRCU_SLEEP_ENTRY_WFI : Enters SLEEP mode via WFI instruction + * @retval None + ************************************************************************************************************/ +void PWRCU_Sleep(PWRCU_SLEEP_ENTRY_Enum SleepEntry) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_SLEEP_ENTRY(SleepEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= ~(u32)SLEEPDEEP_SET; + + if (SleepEntry == PWRCU_SLEEP_ENTRY_WFE) + { + /* Wait for event */ + __SEV(); + __WFE(); + __WFE(); + } + else + { + /* Wait for interrupt */ + __WFI(); + } +} + +/*********************************************************************************************************//** + * @brief Enter DEEP-SLEEP Mode 1. + * @param SleepEntry : Enters sleep mode instruction that is used to WFI or WFE. + * This parameter can be one of the following values: + * @arg PWRCU_SLEEP_ENTRY_WFE : Enters SLEEP mode via WFE instruction + * @arg PWRCU_SLEEP_ENTRY_WFI : Enters SLEEP mode via WFI instruction + * @retval None + ************************************************************************************************************/ +void PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_Enum SleepEntry) +{ + u32 uRTCStatus = 0; + /* Check the parameters */ + Assert_Param(IS_PWRCU_SLEEP_ENTRY(SleepEntry)); + + uRTCStatus = Get_RTCEN; + Set_RTCEN; + + Reset_DMOSON; + Reset_LDOOFF; + + /* Sets SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SLEEPDEEP_SET; + + if (uRTCStatus == 0) + { + Reset_RTCEN; + } + + if (SleepEntry == PWRCU_SLEEP_ENTRY_WFE) + { + /* Wait for event */ + __SEV(); + __WFE(); + __WFE(); + } + else + { + /* Wait for interrupt */ + __WFI(); + } + + SCB->SCR &= ~(u32)SLEEPDEEP_SET; +} + +/*********************************************************************************************************//** + * @brief Enter DEEP-SLEEP Mode 2. + * @param SleepEntry : Enters sleep mode instruction that is used to WFI or WFE. + * This parameter can be one of the following values: + * @arg PWRCU_SLEEP_ENTRY_WFE : Enters SLEEP mode via WFE instruction + * @arg PWRCU_SLEEP_ENTRY_WFI : Enters SLEEP mode via WFI instruction + * @retval None + ************************************************************************************************************/ +void PWRCU_DeepSleep2(PWRCU_SLEEP_ENTRY_Enum SleepEntry) +{ + u32 uRTCStatus = 0; + /* Check the parameters */ + Assert_Param(IS_PWRCU_SLEEP_ENTRY(SleepEntry)); + + uRTCStatus = Get_RTCEN; + Set_RTCEN; + + if (Get_DMOSSTS == 0) + { + Reset_DMOSON; + Set_DMOSON; + } + Reset_LDOOFF; + + if (uRTCStatus == 0) + { + Reset_RTCEN; + } + + /* Sets SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SLEEPDEEP_SET; + + if (SleepEntry == PWRCU_SLEEP_ENTRY_WFE) + { + /* Wait for event */ + __SEV(); + __WFE(); + __WFE(); + } + else + { + /* Wait for interrupt */ + __WFI(); + } + + SCB->SCR &= ~(u32)SLEEPDEEP_SET; +} + +#if !defined(USE_HT32F52220_30) +/*********************************************************************************************************//** + * @brief Enter DEEP-SLEEP Mode 2. + * @param SleepEntry : Enters sleep mode instruction that is used to WFI or WFE. + * This parameter can be one of the following values: + * @arg PWRCU_SLEEP_ENTRY_WFE : Enters SLEEP mode via WFE instruction + * @arg PWRCU_SLEEP_ENTRY_WFI : Enters SLEEP mode via WFI instruction + * @retval None + ************************************************************************************************************/ +void PWRCU_DeepSleep2Ex(PWRCU_SLEEP_ENTRY_Enum SleepEntry) +{ + u32 uRTCStatus = 0; + u32 uBackUp[4]; + + /* Check the parameters */ + Assert_Param(IS_PWRCU_SLEEP_ENTRY(SleepEntry)); + + uRTCStatus = Get_RTCEN; + Set_RTCEN; + uBackUp[0] = HT_RTC->CMP; + uBackUp[1] = HT_RTC->IWEN; + uBackUp[2] = HT_RTC->CR; + uBackUp[3] = HT_EXTI->WAKUPCR; + + Set_DMOSON; + Reset_LDOOFF; + + /* Sets SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SLEEPDEEP_SET; + + if (SleepEntry == PWRCU_SLEEP_ENTRY_WFE) + { + /* Wait for event */ + __SEV(); + __WFE(); + __WFE(); + } + else + { + /* Wait for interrupt */ + __WFI(); + } + + if (HT_EXTI->WAKUPFLG) + { + HT_EXTI->WAKUPCR &= ~(0xFFFF); + HT_EXTI->WAKUPFLG = 0xFFFF; + HT_RTC->CR &= (~1UL); + HT_RTC->CMP = 1; + HT_RTC->IWEN = (1 << 9); + HT_RTC->CR = (1 << 4) | (1 << 2) | (1 << 0); + __SEV(); + __WFE(); + __WFE(); + HT_RTC->CR &= (~1UL); + rw((u32)&HT_RTC->SR); + + HT_RTC->CMP = uBackUp[0]; + HT_RTC->IWEN = uBackUp[1]; + HT_RTC->CR = uBackUp[2]; + HT_EXTI->WAKUPCR = uBackUp[3]; + } + + SCB->SCR &= ~(u32)SLEEPDEEP_SET; + + if (uRTCStatus == 0) + { + Reset_RTCEN; + } +} +#endif + +#if (!LIBCFG_PWRCU_NO_PD_MODE) +/*********************************************************************************************************//** + * @brief Enter POWER-DOWN Mode. + * @retval None + ************************************************************************************************************/ +void PWRCU_PowerDown(void) +{ + u32 uRTCStatus = 0; + + uRTCStatus = Get_RTCEN; + Set_RTCEN; + + #if (LIBCFG_RTC_LSI_LOAD_TRIM) + { + static u8 isLSITrimLoaded = FALSE; + if (isLSITrimLoaded == FALSE) + { + u32 i = 4800; + isLSITrimLoaded = TRUE; + HT_RTC->CR &= ~(1UL << 2); + /* Insert a delay must > 1 CK_RTC */ + while (i--); + HT_RTC->CR |= (1UL << 2); + while ((HT_CKCU->GCSR & 0x20) == 0); + } + } + #endif + + Reset_DMOSON; + Set_LDOOFF; + + if (uRTCStatus == 0) + { + Reset_RTCEN; + } + + /* Sets SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SLEEPDEEP_SET; + + /* Enters power-down mode */ + __SEV(); + __WFE(); + __WFE(); + + { + u32 X = (16 * 250); + while (X--); + } + + NVIC_SystemReset(); +} +#endif + +/*********************************************************************************************************//** + * @brief Configure LVD voltage level. + * @param Level: Low voltage detect level. + * This parameter can be one of the following: + * VDD 2.0 ~ 3.6V version: + * @arg PWRCU_LVDS_2V25 : 2.25 V + * @arg PWRCU_LVDS_2V4 : 2.40 V + * @arg PWRCU_LVDS_2V55 : 2.55 V + * @arg PWRCU_LVDS_2V7 : 2.70 V + * @arg PWRCU_LVDS_2V85 : 2.85 V + * @arg PWRCU_LVDS_3V : 3.00 V + * @arg PWRCU_LVDS_3V15 : 3.15 V + * @arg PWRCU_LVDS_3V3 : 3.30 V + * VDD 1.65 ~ 3.6V version: + * @arg PWRCU_LVDS_1V75 : 1.75 V + * @arg PWRCU_LVDS_1V95 : 1.95 V + * @arg PWRCU_LVDS_2V15 : 2.15 V + * @arg PWRCU_LVDS_2V35 : 2.35 V + * @arg PWRCU_LVDS_2V55 : 2.55 V + * @arg PWRCU_LVDS_2V75 : 2.75 V + * @arg PWRCU_LVDS_2V95 : 2.95 V + * @arg PWRCU_LVDS_3V15 : 3.15 V + * VDD 5.0V version: + * @arg PWRCU_LVDS_2V65 : 2.65 V + * @arg PWRCU_LVDS_2V85 : 2.85 V + * @arg PWRCU_LVDS_3V05 : 3.05 V + * @arg PWRCU_LVDS_3V25 : 3.25 V + * @arg PWRCU_LVDS_3V45 : 3.45 V + * @arg PWRCU_LVDS_4V25 : 4.25 V + * @arg PWRCU_LVDS_4V45 : 4.45 V + * @arg PWRCU_LVDS_4V65 : 4.65 V + * @retval None + ************************************************************************************************************/ +void PWRCU_SetLVDS(PWRCU_LVDS_Enum Level) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_LVDS(Level)); + + HT_PWRCU->LVDCSR = (HT_PWRCU->LVDCSR & LVDS_MASK) | Level; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable LVD function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_LVDCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + Set_LVDEN; + } + else + { + Reset_LVDEN; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable BOD reset function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_BODCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + Set_BODEN; + } + else + { + Reset_BODEN; + } +} + +/*********************************************************************************************************//** + * @brief Select when the BOD occurs, the action for the cause Reset or Interrupt. + * @param Selection: BOD reset or interrupt selection. + * This parameter can be one of the following values: + * @arg PWRCU_BODRIS_RESET : Reset the whole chip + * @arg PWRCU_BODRIS_INT : Assert interrupt + * @retval None + ************************************************************************************************************/ +void PWRCU_BODRISConfig(PWRCU_BODRIS_Enum Selection) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_BODRIS(Selection)); + + if (Selection != PWRCU_BODRIS_RESET) + { + Set_BODRIS; + } + else + { + Reset_BODRIS; + } +} + +/*********************************************************************************************************//** + * @brief Return the flag status of LVD. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus PWRCU_GetLVDFlagStatus(void) +{ + return (FlagStatus)Get_LVDF; +} + +/*********************************************************************************************************//** + * @brief Return the flag status of BOD. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus PWRCU_GetBODFlagStatus(void) +{ + return (FlagStatus)Get_BODF; +} + +/*********************************************************************************************************//** + * @brief Return the DMOS status. + * @retval This function will return one of the following values: + * - PWRCU_DMOS_STS_ON : DMOS on + * - PWRCU_DMOS_STS_OFF : DMOS off + * - PWRCU_DMOS_STS_OFF_BY_BODRESET : DMOS off caused by brow out reset + ************************************************************************************************************/ +PWRCU_DMOSStatus PWRCU_GetDMOSStatus(void) +{ + u32 wDmosStatus = HT_PWRCU->CR & 0x8080; + + if (wDmosStatus == 0x0) + { + return PWRCU_DMOS_STS_OFF; + } + else if (wDmosStatus == 0x8080) + { + return PWRCU_DMOS_STS_ON; + } + else + { + return PWRCU_DMOS_STS_OFF_BY_BODRESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable DMOS function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_DMOSCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (Get_DMOSSTS == 0) + { + Reset_DMOSON; + } + + if (NewState != DISABLE) + { + Set_DMOSON; + } + else + { + Reset_DMOSON; + } +} + +/*********************************************************************************************************//** + * @brief Configure the LDO operation mode. + * @param Sel: Specify the LDO mode. + * This parameter can be one of the following values: + * @arg PWRCU_LDO_NORMAL : The LDO is operated in normal current mode + * @arg PWRCU_LDO_LOWCURRENT : The LDO is operated in low current mode + * @retval None + ************************************************************************************************************/ +void PWRCU_LDOConfig(PWRCU_LDOMODE_Enum Sel) +{ + u32 uRTCStatus = 0; + + /* Check the parameters */ + Assert_Param(IS_PWRCU_LDOMODE(Sel)); + + uRTCStatus = Get_RTCEN; + Set_RTCEN; + + if (Sel == PWRCU_LDO_NORMAL) + { + Reset_LDOMODE; + } + else + { + Set_LDOMODE; + } + + if (uRTCStatus == 0) + { + Reset_RTCEN; + } +} + +#if (LIBCFG_PWRCU_V15_READY_SOURCE) +/*********************************************************************************************************//** + * @brief Configure VDD15 power good source. + * @param Sel: specifies VDD15 power good source. + * This parameter can be one of the following values: + * @arg PWRCU_V15RDYSC_V33ISO : Vdd15 power good source come from V33_ISO bit in CKCU unit + * @arg PWRCU_V15RDYSC_V15POR : Vdd15 power good source come from Vdd15 power-on reset + * @retval None + ************************************************************************************************************/ +void PWRCU_V15RDYSourceConfig(PWRCU_V15RDYSC_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_V15RDYSC(Sel)); + + if (Sel == PWRCU_V15RDYSC_V33ISO) + { + Reset_V15RDYSC; + } + else + { + Set_V15RDYSC; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the LVD interrupt wakeup function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_LVDIntWakeupConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + Set_LVDIWEN; + } + else + { + Reset_LVDIWEN; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the LVD event wakeup function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_LVDEventWakeupConfig(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + Set_LVDEWEN; + } + else + { + Reset_LVDEWEN; + } +} + +#if (LIBCFG_PWRCU_VREG) +/*********************************************************************************************************//** + * @brief Configure the VREG output voltage. + * @param Volt: VREG output voltage. + * This parameter can be one of the following: + * @arg PWRCU_VREG_4V0 : 4.0 V + * @arg PWRCU_VREG_3V3 : 3.3 V + * @arg PWRCU_VREG_3V0 : 3.0 V + * @arg PWRCU_VREG_2V5 : 2.5 V + * @arg PWRCU_VREG_1V8 : 1.8 V + * @retval None + ************************************************************************************************************/ +void PWRCU_SetVREG(PWRCU_VREG_VOLT_Enum Volt) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_VREG_VOLT(Volt)); + + HT_PWRCU->CR = (HT_PWRCU->CR & VREG_V_MASK) | Volt; +} + +/*********************************************************************************************************//** + * @brief Configure the VREG operation mode. + * @param Mode: VREG operation mode. + * This parameter can be one of the following values: + * @arg PWRCU_VREG_DISABLE : The VREG is disabled + * @arg PWRCU_VREG_ENABLE : The VREG is enabled + * @arg PWRCU_VREG_BYPASS : The VREG is bypassed + * @retval None + ************************************************************************************************************/ +void PWRCU_VREGConfig(PWRCU_VREG_MODE_Enum Mode) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_VREG_MODE(Mode)); + + HT_PWRCU->CR = (HT_PWRCU->CR & VREG_M_MASK) | Mode; +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the external WAKEUP pin function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_WakeupPinCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + Set_WUP0EN; + } + else + { + Reset_WUP0EN; + } +} + +#if (LIBCFG_PWRCU_WAKEUP_V01) +/*********************************************************************************************************//** + * @brief Enable or Disable the external WAKEUP pin function. + * @param Pin: specify the WAKEUP pin number. + * This parameter can be one of the following values: + * @arg PWRCU_WAKEUP_PIN_0 : + * @arg PWRCU_WAKEUP_PIN_1 : + * @param Type: specify the WAKEUP pin type. + * This parameter can be one of the following values: + * @arg PWRCU_WUP_POSITIVE_EDGE : + * @arg PWRCU_WUP_NEGATIVE_EDGE : + * @arg PWRCU_WUP_HIGH_LEVEL : + * @arg PWRCU_WUP_LOW_LEVEL : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void PWRCU_WakeupMultiPinCmd(PWRCU_WUP_Enum Pin, PWRCU_WUPTYPE_Enum Type, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_WAKEUPPIN(Pin)); + Assert_Param(IS_PWRCU_TRIGGERTYPE(Type)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + if (Pin == PWRCU_WAKEUP_PIN_0) + { + HT_PWRCU->CR = (HT_PWRCU->CR & WUP0TYPE_MASK) | (Type << 16); + Set_WUP0EN; + } + else + { + HT_PWRCU->CR = (HT_PWRCU->CR & WUP1TYPE_MASK) | (Type << 18); + Set_WUP1EN; + } + } + else + { + if (Pin == PWRCU_WAKEUP_PIN_0) + Reset_WUP0EN; + else + Reset_WUP1EN; + } +} +#endif + +#if defined(USE_HT32F52342_52) || defined(USE_HT32F5826) +/*********************************************************************************************************//** + * @brief Configure HSI ready counter bit length. + * @param BitLength: HSI ready counter bit length. + * This parameter can be one of following: + * @arg PWRCU_HSIRCBL_4 : 4 bits + * @arg PWRCU_HSIRCBL_5 : 5 bits + * @arg PWRCU_HSIRCBL_6 : 6 bits + * @arg PWRCU_HSIRCBL_7 : 7 bits (Default) + * @retval None + ************************************************************************************************************/ +void PWRCU_HSIReadyCounterBitLengthConfig(PWRCU_HSIRCBL_Enum BitLength) +{ + /* Check the parameters */ + Assert_Param(IS_PWRCU_HSIRCBL(BitLength)); + + HT_PWRCU->HSIRCR = BitLength; +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_rstcu.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_rstcu.c new file mode 100644 index 00000000000..8c5ced5882f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_rstcu.c @@ -0,0 +1,142 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_rstcu.c + * @version $Rev:: 6479 $ + * @date $Date:: 2022-11-23 #$ + * @brief This file provides all the Reset Control Unit firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_rstcu.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup RSTCU RSTCU + * @brief RSTCU driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup RSTCU_Exported_Functions RSTCU exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Check whether the specific global reset flag is set or not. + * @param RSTCU_RSTF: specify the reset flag. + * This parameter can be one of the following values: + * @arg RSTCU_FLAG_SYSRST : Get system reset flag + * @arg RSTCU_FLAG_EXTRST : Get external pin reset flag + * @arg RSTCU_FLAG_WDTRST : Get WDT reset flag + * @arg RSTCU_FLAG_PORST : Get power on reset flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus RSTCU_GetResetFlagStatus(RSTCU_RSTF_TypeDef RSTCU_RSTF) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_RSTCU_FLAG(RSTCU_RSTF)); + + tmp = (HT_RSTCU->GRSR & ((u32)0x1 << RSTCU_RSTF)); + if (tmp != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specific global reset flag. + * @param RSTCU_RSTF: specify the reset flag. + * This parameter can be one of the following values: + * @arg RSTCU_FLAG_SYSRST : Clear system reset flag + * @arg RSTCU_FLAG_EXTRST : Clear external pin reset flag + * @arg RSTCU_FLAG_WDTRST : Clear WDT reset flag + * @arg RSTCU_FLAG_PORST : Clear power on reset flag + * @retval None + ************************************************************************************************************/ +void RSTCU_ClearResetFlag(RSTCU_RSTF_TypeDef RSTCU_RSTF) +{ + /* Check the parameters */ + Assert_Param(IS_RSTCU_FLAG(RSTCU_RSTF)); + + HT_RSTCU->GRSR = (u32)0x1 << RSTCU_RSTF; /* Write 1 to clear */ +} + +/*********************************************************************************************************//** + * @brief Clear all of the global reset flag. + * @retval None + ************************************************************************************************************/ +void RSTCU_ClearAllResetFlag(void) +{ + HT_RSTCU->GRSR = (u32)0xF; /* Write 1 to clear */ +} + +/*********************************************************************************************************//** + * @brief Peripheral reset function. + * @param Reset: specify the peripheral clock enable bits. + * @param Cmd: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RSTCU_PeripReset(RSTCU_PeripReset_TypeDef Reset, ControlStatus Cmd) +{ + u32 uAHBPRST; + u32 uAPBPRST0; + u32 uAPBPRST1; + + uAHBPRST = HT_RSTCU->AHBPRST; + uAPBPRST0 = HT_RSTCU->APBPRST0; + uAPBPRST1 = HT_RSTCU->APBPRST1; + + uAHBPRST &= ~(Reset.Reg[0]); + uAPBPRST0 &= ~(Reset.Reg[1]); + uAPBPRST1 &= ~(Reset.Reg[2]); + + if (Cmd != DISABLE) + { + uAHBPRST |= Reset.Reg[0]; + uAPBPRST0 |= Reset.Reg[1]; + uAPBPRST1 |= Reset.Reg[2]; + } + + HT_RSTCU->AHBPRST = uAHBPRST; + HT_RSTCU->APBPRST0 = uAPBPRST0; + HT_RSTCU->APBPRST1 = uAPBPRST1; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_rtc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_rtc.c new file mode 100644 index 00000000000..b4ae9564331 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_rtc.c @@ -0,0 +1,393 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_rtc.c + * @version $Rev:: 7336 $ + * @date $Date:: 2023-11-23 #$ + * @brief This file provides all the RTC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_rtc.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup RTC RTC + * @brief RTC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Private_Define RTC private definitions + * @{ + */ +#define RPRE_MASK (0xFFFFF0FF) + +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the RTC peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void RTC_DeInit(void) +{ + HT_RTC->CR = 0x00000004; + HT_RTC->CMP = 0x0; + HT_RTC->IWEN = 0x0; + HT_RTC->CR |= 0x00000005; + while (HT_RTC->CNT); + HT_RTC->CR = 0x00000F04; + /* Read the RTC_SR register to clear it */ + HT_RTC->SR; +} + +/*********************************************************************************************************//** + * @brief Select the RTC timer clock source. + * @param Source: specify the clock source of RTC and backup domain. + * @arg RTC_SRC_LSI : Low speed internal clock. + * @arg RTC_SRC_LSE : Low speed external clock. + * @retval None + ************************************************************************************************************/ +void RTC_ClockSourceConfig(RTC_SRC_Enum Source) +{ + Assert_Param(IS_RTC_SRC(Source)); + + HT_RTC->CR = (HT_RTC->CR & ~(1UL << 1)) | ((u32)Source << 1); +} + +#if (LIBCFG_RTC_LSI_LOAD_TRIM) +/*********************************************************************************************************//** + * @brief Loads the LSI trim data. + * @retval None + ************************************************************************************************************/ +void RTC_LSILoadTrimData(void) +{ + u32 i = 4800; + u32 isRTCEnable = HT_CKCU->APBCCR1 & (1 << 6); + + HT_CKCU->APBCCR1 |= 1 << 6; + HT_RTC->CR &= ~(1UL << 2); + /* Insert a delay must > 1 CK_RTC */ + while (i--); + HT_RTC->CR |= (1UL << 2); + while ((HT_CKCU->GCSR & 0x20) == 0); + + if (isRTCEnable == 0) + HT_CKCU->APBCCR1 &= ~(1 << 6); +} +#endif + +#if (LIBCFG_LSE) +/*********************************************************************************************************//** + * @brief Select the LSE startup mode. + * @param Mode: specify the LSE startup mode. + * This parameter can be one of the following values: + * @arg RTC_LSESM_NORMAL : Little power consumption but longer startup time. + * @arg RTC_LSESM_FAST : Shortly startup time but higher power consumption. + * @retval None + ************************************************************************************************************/ +void RTC_LSESMConfig(RTC_LSESM_Enum Mode) +{ + Assert_Param(IS_RTC_LSESM(Mode)); + + HT_RTC->CR = (HT_RTC->CR & ~(1UL << 5)) | ((u32)Mode << 5); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the LSE clock. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_LSECmd(ControlStatus NewState) +{ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == DISABLE) + { + HT_RTC->CR &= ~(1UL << 3); + } + else + { + HT_RTC->CR |= (1UL << 3); + } +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the compare match function. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_CMPCLRCmd(ControlStatus NewState) +{ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_RTC->CR |= (1UL << 4); + } + else + { + HT_RTC->CR &= ~(1UL << 4); + } +} + +/*********************************************************************************************************//** + * @brief Configure the RTC prescaler. + * @param Psc: Value of RTC prescaler. + * This parameter can be one of following values: + * @arg RTC_RPRE_1 + * @arg RTC_RPRE_2 + * @arg RTC_RPRE_4 + * @arg RTC_RPRE_8 + * @arg RTC_RPRE_16 + * @arg RTC_RPRE_32 + * @arg RTC_RPRE_64 + * @arg RTC_RPRE_128 + * @arg RTC_RPRE_256 + * @arg RTC_RPRE_512 + * @arg RTC_RPRE_1024 + * @arg RTC_RPRE_2048 + * @arg RTC_RPRE_4096 + * @arg RTC_RPRE_8192 + * @arg RTC_RPRE_16384 + * @arg RTC_RPRE_32768 + * @retval None + ************************************************************************************************************/ +void RTC_SetPrescaler(RTC_RPRE_Enum Psc) +{ + Assert_Param(IS_RTC_PSC(Psc)); + + HT_RTC->CR = (HT_RTC->CR & RPRE_MASK) | Psc; +} + +/*********************************************************************************************************//** + * @brief Return the RTC prescaler setting. + * @retval The prescaler value. It is powered by 2 and max.is 32768. + ************************************************************************************************************/ +u16 RTC_GetPrescaler(void) +{ + u32 prescaler; + + prescaler = HT_RTC->CR >> 8; + + return ((u16)0x1 << prescaler); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the RTC timer. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_Cmd(ControlStatus NewState) +{ + if (NewState != DISABLE) + { + HT_RTC->CR |= (1UL); + } + else + { + HT_RTC->CR &= ~(1UL); + } +} + +/*********************************************************************************************************//** + * @brief Return the counter value. + * @retval Between 0x0 ~ 0xFFFFFFFF. + ************************************************************************************************************/ +u32 RTC_GetCounter(void) +{ + /* !!! NOTICE !!! + A 1/CK_RTC delay time is required if you read the RTC CNT count immediately when the RTC compare match + occurred (in the RTC ISR or the system is wakeup from the DeepSleep1/2). + The CK_RTC can be configured from the LSI or LSE. + */ + return (HT_RTC->CNT); +} + +/*********************************************************************************************************//** + * @brief Configure the compare match value. + * @param Compare: Between 0x0 ~ 0xFFFFFFFF + * @retval None + ************************************************************************************************************/ +void RTC_SetCompare(u32 Compare) +{ + HT_RTC->CMP = Compare; +} + +/*********************************************************************************************************//** + * @brief Return the compare match value. + * @retval Between 0x0 ~ 0xFFFFFFFF. + ************************************************************************************************************/ +u32 RTC_GetCompare(void) +{ + return (HT_RTC->CMP); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified wakeup source. + * @param RTC_WAKEUP Selection of Wakeup source. + * This parameter can be any combination of the following values: + * @arg RTC_WAKEUP_CSEC : Waken up by counter counting. + * @arg RTC_WAKEUP_CM : Waken up by counter compare match with CMP register. + * @arg RTC_WAKEUP_OV : Waken up by counter overflow. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_WakeupConfig(u32 RTC_WAKEUP, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_RTC_WAKEUP(RTC_WAKEUP)); + + if (NewState != DISABLE) + { + HT_RTC->IWEN |= RTC_WAKEUP; + } + else + { + HT_RTC->IWEN &= ~RTC_WAKEUP; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified interrupt source. + * @param RTC_INT: Selection of Wakeup source. + * This parameter can be any combination of the following values: + * @arg RTC_INT_CSEC : Assert interrupt at counter counting + * @arg RTC_INT_CM : Assert interrupt at counter compare match with CMP register + * @arg RTC_INT_OV : Assert interrupt at counter overflow + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_IntConfig(u32 RTC_INT, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_RTC_INT(RTC_INT)); + + if (NewState != DISABLE) + { + HT_RTC->IWEN |= RTC_INT; + } + else + { + HT_RTC->IWEN &= ~RTC_INT; + } +} + +/*********************************************************************************************************//** + * @brief Return the RTC flags. + * @retval RTC_STS register value. + * This parameter can be any combination of following: + * - 0x0 : No flag set + * - 0x1 : Count flag + * - 0x2 : Match flag + * - 0x4 : Overflow flag + * @note RTC_SR is read clear. + ************************************************************************************************************/ +u8 RTC_GetFlagStatus(void) +{ + return ((u8)HT_RTC->SR); +} + +/*********************************************************************************************************//** + * @brief Configure the RTC output function. + * @param WMode: specify the RTC output waveform mode + * This parameter can be one of the following values: + * @arg RTC_ROWM_PULSE : Pulse mode + * @arg RTC_ROWM_LEVEL : Level mode + * @param EventSel: specify the RTC output event selection + * This parameter can be one of the following values: + * @arg RTC_ROES_MATCH : Compare match selected + * @arg RTC_ROES_SECOND : Second clock selected + * @param Pol: specify the RTC output active polarity + * This parameter can be one of the following values: + * @arg RTC_ROAP_HIGH : Active level is high + * @arg RTC_ROAP_LOW : Active level is low + * @note This function will disable RTC output first. + ************************************************************************************************************/ +void RTC_OutConfig(RTC_ROWM_Enum WMode, RTC_ROES_Enum EventSel, RTC_ROAP_Enum Pol) +{ + Assert_Param(IS_RTC_ROWM(WMode)); + Assert_Param(IS_RTC_ROES(EventSel)); + Assert_Param(IS_RTC_ROAP(Pol)); + + HT_RTC->CR &= ~(1UL << 16); + HT_RTC->CR = (HT_RTC->CR & ~(1UL << 18)) | ((u32)WMode << 18); + HT_RTC->CR = (HT_RTC->CR & ~(1UL << 17)) | ((u32)EventSel << 17); + HT_RTC->CR = (HT_RTC->CR & ~(1UL << 19)) | ((u32)Pol << 19); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the RTC output. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void RTC_OutCmd(ControlStatus NewState) +{ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_RTC->CR |= (1UL << 16); + } + else + { + HT_RTC->CR &= ~(1UL << 16); + } +} + +/*********************************************************************************************************//** + * @brief Return the RTCOUT level mode flag. + * @retval SET or RESET + * @note Reads RTC_CR action will clear ROLF flag. + ************************************************************************************************************/ +FlagStatus RTC_GetOutStatus(void) +{ + if (HT_RTC->CR & (1UL << 20)) + { + return SET; + } + else + { + return RESET; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sci.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sci.c new file mode 100644 index 00000000000..72a4c060673 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sci.c @@ -0,0 +1,446 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_sci.c + * @version $Rev:: 6386 $ + * @date $Date:: 2022-10-27 #$ + * @brief This file provides all the SCI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_sci.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup SCI SCI + * @brief SCI driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Private_Define SCI private definitions + * @{ + */ +/* SCI ENSCI mask */ +#define CR_ENSCI_SET ((u32)0x00000020) +#define CR_ENSCI_RESET ((u32)0xFFFFFFDF) + +/* SCI WTEN mask */ +#define CR_WTEN_SET ((u32)0x00000004) +#define CR_WTEN_RESET ((u32)0xFFFFFFFB) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SCI_Exported_Functions SCI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the SCI peripheral registers to their default reset values. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @retval None + ************************************************************************************************************/ +void SCI_DeInit(HT_SCI_TypeDef* SCIx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + if (SCIx == HT_SCI0) + { + RSTCUReset.Bit.SCI0 = 1; + } + #if (LIBCFG_SCI1) + else + { + RSTCUReset.Bit.SCI1 = 1; + } + #endif + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the SCI peripheral according to the specified parameters in the SCI_InitStruct. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_InitStruct: pointer to a SCI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SCI_Init(HT_SCI_TypeDef* SCIx, SCI_InitTypeDef* SCI_InitStruct) +{ + u32 tmpreg; + + /* Check the parameters */ + Assert_Param(IS_SCI_MODE(SCI_InitStruct->SCI_Mode)); + Assert_Param(IS_SCI_RETRY(SCI_InitStruct->SCI_Retry)); + Assert_Param(IS_SCI_CONVENTION(SCI_InitStruct->SCI_Convention)); + Assert_Param(IS_SCI_CARD_POLARITY(SCI_InitStruct->SCI_CardPolarity)); + Assert_Param(IS_SCI_CLOCK_PRESCALER(SCI_InitStruct->SCI_ClockPrescale)); + + + /*------------------------- SCI Control Register Configuration -------------------------------------------*/ + tmpreg = SCIx->CR; + tmpreg &= 0xFFFFFFA4; + + tmpreg |= SCI_InitStruct->SCI_Mode | SCI_InitStruct->SCI_Retry | SCI_InitStruct->SCI_Convention | + SCI_InitStruct->SCI_CardPolarity; + + SCIx->CR = tmpreg; + + /*------------------------- SCI Prescaler Register Configuration -----------------------------------------*/ + SCIx->PSC = SCI_InitStruct->SCI_ClockPrescale; +} + +/*********************************************************************************************************//** + * @brief Initialize the SCI peripheral according to the specified parameters in the SCI_InitStruct. + * @param SCI_InitStruct: pointer to a SCI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SCI_StructInit(SCI_InitTypeDef* SCI_InitStruct) +{ + /* Initialize the SCI_Mode member */ + SCI_InitStruct->SCI_Mode = SCI_MODE_MANUAL; + + /* Initialize the SCI_Retry member */ + SCI_InitStruct->SCI_Retry = SCI_RETRY_NO; + + /* Initialize the SCI_Convention member */ + SCI_InitStruct->SCI_Convention = SCI_CONVENTION_DIRECT; + + /* Initialize the SCI_CardPolarity member */ + SCI_InitStruct->SCI_CardPolarity = SCI_CARDPOLARITY_LOW; + + /* Initialize the SCI_ClockPrescale member */ + SCI_InitStruct->SCI_ClockPrescale = SCI_CLKPRESCALER_1; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SCI peripheral. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_Cmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->CR |= CR_ENSCI_SET; + } + else + { + SCIx->CR &= CR_ENSCI_RESET; + } +} + +/*********************************************************************************************************//** + * @brief This function is used to configure the Elementary Time Unit. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_ETU: specify the SCI Elementary Time Unit. + * @param SCI_Compensation: Enable or Disable the Compensation mode. + * This parameter can be one of the following values: + * @arg SCI_COMPENSATION_ENABLE : Compensation mode enabled + * @arg SCI_COMPENSATION_DISABLE : Compensation mode disabled + * @retval None + ************************************************************************************************************/ +void SCI_ETUConfig(HT_SCI_TypeDef* SCIx, u32 SCI_ETU, u32 SCI_Compensation) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_ETU(SCI_ETU)); + Assert_Param(IS_SCI_ETU_COMPENSATION(SCI_Compensation)); + + SCIx->ETU = SCI_ETU | SCI_Compensation; +} + +/*********************************************************************************************************//** + * @brief This function is used to set the value of SCI GuardTime. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_GuardTime: specify the value of SCI GuardTime value. + * @retval None + ************************************************************************************************************/ +void SCI_SetGuardTimeValue(HT_SCI_TypeDef* SCIx, u16 SCI_GuardTime) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_GUARDTIME(SCI_GuardTime)); + + SCIx->GT = SCI_GuardTime; +} + +/*********************************************************************************************************//** + * @brief This function is used to set the value of SCI Waiting Time. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_WaitingTime: specify the value of SCI Waiting Time value. + * @retval None + ************************************************************************************************************/ +void SCI_SetWaitingTimeValue(HT_SCI_TypeDef* SCIx, u32 SCI_WaitingTime) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_WAITING_TIME(SCI_WaitingTime)); + + SCIx->WT = SCI_WaitingTime; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the Waiting Time Counter. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_WaitingTimeCounterCmd(HT_SCI_TypeDef* SCIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->CR |= CR_WTEN_SET; + } + else + { + SCIx->CR &= CR_WTEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Sends a data byte through the SCI peripheral. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Data: byte to be transmitted. + * @retval None + ************************************************************************************************************/ +void SCI_SendData(HT_SCI_TypeDef* SCIx, u8 SCI_Data) +{ + SCIx->TXB = SCI_Data; +} + +/*********************************************************************************************************//** + * @brief Returns the received data through the SCI peripheral. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @retval The value of the received data. + ************************************************************************************************************/ +u8 SCI_ReceiveData(HT_SCI_TypeDef* SCIx) +{ + return ((u8)SCIx->RXB); +} + +/*********************************************************************************************************//** + * @brief Determines the SCI output clock signal is driven by hardware or software. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_CLKMode: specify the SCI clock pin mode. + * This parameter can be one of the following values: + * @arg SCI_CLK_SOFTWARE : SCI output clock is controlled by software + * @arg SCI_CLK_HARDWARE : SCI output clock is controlled by hardware + * @retval None + ************************************************************************************************************/ +void SCI_ClockModeConfig(HT_SCI_TypeDef* SCIx, u32 SCI_CLKMode) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_CLK_MODE(SCI_CLKMode)); + + if (SCI_CLKMode != SCI_CLK_SOFTWARE) + { + SCIx->CCR |= SCI_CLK_HARDWARE; + } + else + { + SCIx->CCR &= SCI_CLK_SOFTWARE; + } +} + +/*********************************************************************************************************//** + * @brief Output the SCI clock pin low or high by software. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_CLK: specify if the SCI clock pin to be high or low. + * This parameter can be one of the following values: + * @arg SCI_CLK_HIGH : Software drive SCI output clock high + * @arg SCI_CLK_LOW : Software drive SCI output clock low + * @retval None + ************************************************************************************************************/ +void SCI_SoftwareClockCmd(HT_SCI_TypeDef* SCIx, u32 SCI_CLK) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_CLK(SCI_CLK)); + + if (SCI_CLK != SCI_CLK_LOW) + { + SCIx->CCR |= SCI_CLK_HIGH; + } + else + { + SCIx->CCR &= SCI_CLK_LOW; + } +} + +/*********************************************************************************************************//** + * @brief Output the SCI DIO pin low or high by software. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_DIO: specify if the SCI DIO pin to be high or low. + * This parameter can be one of the following values: + * @arg SCI_DIO_HIGH : Drive SCI DIO signal high + * @arg SCI_DIO_LOW : Drive SCI DIO signal low + * @retval None + ************************************************************************************************************/ +void SCI_OutputDIO(HT_SCI_TypeDef* SCIx, u32 SCI_DIO) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_DIO(SCI_DIO)); + + if (SCI_DIO != SCI_DIO_LOW) + { + SCIx->CCR |= SCI_DIO_HIGH; + } + else + { + SCIx->CCR &= SCI_DIO_LOW; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SCI interrupt. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Int: specify the SCI interrupt source to be enabled or disable. + * This parameter can be any combination of the following values: + * @arg SCI_INT_PAR : SCI parity error interrupt + * @arg SCI_INT_RXC : SCI received character interrupt + * @arg SCI_INT_TXC : SCI transmitted character interrupt + * @arg SCI_INT_WT : SCI waiting timer interrupt + * @arg SCI_INT_CARD : SCI card insert/remove interrupt + * @arg SCI_INT_TXBE : SCI transmit buffer empty interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_IntConfig(HT_SCI_TypeDef* SCIx, u32 SCI_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_INT(SCI_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->IER |= SCI_Int; + } + else + { + SCIx->IER &= ~SCI_Int; + } +} + +/*********************************************************************************************************//** + * @brief Get the status of specified SCI flag. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg SCI_FLAG_PAR : SCI parity error flag + * @arg SCI_FLAG_RXC : SCI received character flag + * @arg SCI_FLAG_TXC : SCI transmitted character flag + * @arg SCI_FLAG_WT : SCI waiting timer flag + * @arg SCI_FLAG_CARD : SCI card insert/remove flag + * @arg SCI_FLAG_TXBE : SCI transmit buffer empty flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus SCI_GetFlagStatus(HT_SCI_TypeDef* SCIx, u32 SCI_Flag) +{ + u32 statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + Assert_Param(IS_SCI_FLAG(SCI_Flag)); + + statusreg = SCIx->SR; + + if ((statusreg & SCI_Flag) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Clears the flag status of specified SCI flag. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_Flag: specify the flag to be cleared. + * This parameter can be one of the following values: + * @arg SCI_FLAG_PAR : SCI parity error flag + * @arg SCI_FLAG_TXC : SCI transmitted character flag + * @arg SCI_FLAG_WT : SCI waiting timer flag + * @retval None + ************************************************************************************************************/ +void SCI_ClearFlag(HT_SCI_TypeDef* SCIx, u32 SCI_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_CLEAR_FLAG(SCI_Flag)); + + if (SCI_Flag != SCI_FLAG_WT) + { + SCIx->SR &= ~SCI_Flag; + } + else + { + SCIx->CR &= CR_WTEN_RESET; + SCIx->CR |= CR_WTEN_SET; + } +} + +#if (LIBCFG_PDMA) +/*********************************************************************************************************//** + * @brief Enable or disables the SCI PDMA interface. + * @param SCIx: where SCIx is the selected SCI from the SCI peripherals. + * @param SCI_PDMAREQ: specify the SCI PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SCI_PDMAREQ_TX : Tx PDMA transfer request + * @arg SCI_PDMAREQ_RX : Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SCI_PDMACmd(HT_SCI_TypeDef* SCIx, u32 SCI_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SCI_PDMA_REQ(SCI_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SCIx->CR |= SCI_PDMAREQ; + } + else + { + SCIx->CR &= ~SCI_PDMAREQ; + } +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sctm.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sctm.c new file mode 100644 index 00000000000..b824c72b168 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sctm.c @@ -0,0 +1,2 @@ +The SCTM, PWM, GPTM, and MCTM timer have similar architecture. They use the same driver, +"ht32fxxxxx_tm.c/.h" to save the code size. For those timers, please refet to the TM driver/example. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sled.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sled.c new file mode 100644 index 00000000000..132db84be45 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_sled.c @@ -0,0 +1,289 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_sled.c + * @version $Rev:: 3309 $ + * @date $Date:: 2018-12-12 #$ + * @brief This file provides all the SLED firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_sled.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup SLED SLED + * @brief SLED driver modules + * @{ + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SLED_Exported_Functions SLED exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the specified SLED peripheral registers to their default reset values. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @retval None + ************************************************************************************************************/ +void SLED_DeInit(HT_SLED_TypeDef* SLEDx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + + if (SLEDx == HT_SLED0) + { + RSTCUReset.Bit.SLED0 = 1; + } + #if(LIBCFG_SLED1) + else if (SLEDx == HT_SLED1) + { + RSTCUReset.Bit.SLED1 = 1; + } + #endif + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the specified SLED peripheral according to the specified parameters in the SLED_InitStruct. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @param SLED_InitStruct: pointer to a SLED_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SLED_Init(HT_SLED_TypeDef* SLEDx, SLED_InitTypeDef* SLED_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + + SLEDx->CDR = (SLED_InitStruct->BaudRate << 8) + | (SLED_InitStruct->ClockPrescaler << 0); + + SLEDx->TCR = (SLED_InitStruct->TRST << 16) + | (SLED_InitStruct->T1H << 8) + | (SLED_InitStruct->T0H << 0); + + SLEDx->CR = (SLED_InitStruct->SyncState << 10) + | (SLED_InitStruct->IdleState << 9) + | (SLED_InitStruct->ResetState << 8) + | (SLED_InitStruct->SyncMode << 3) + | (SLED_InitStruct->OutputPolarity << 2); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SLED peripheral. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SLED_Cmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SLEDx->CR |= (1 << 0); + } + else + { + SLEDx->CR &= ~(1 << 0); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SLED output. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SLED_OutputCmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SLEDx->CR |= (1 << 1); + } + else + { + SLEDx->CR &= ~(1 << 1); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SLED PDMA request. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SLED_PDMACmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SLEDx->CR |= (1 << 4); + } + else + { + SLEDx->CR &= ~(1 << 4); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SLED interrupt. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SLED_IntCmd(HT_SLED_TypeDef* SLEDx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SLEDx->CR |= (1 << 5); + } + else + { + SLEDx->CR &= ~(1 << 5); + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified SLED interrupt flag. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @retval None + ************************************************************************************************************/ +void SLED_ClearIntFlag(HT_SLED_TypeDef* SLEDx) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + + SLEDx->SR |= (1 << 5); +} + +/*********************************************************************************************************//** + * @brief Insert a Reset Code on the specified SLED. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @retval None + ************************************************************************************************************/ +void SLED_InsertResetCode(HT_SLED_TypeDef* SLEDx) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + + SLEDx->CR |= (1 << 15); +} + +/*********************************************************************************************************//** + * @brief Return the FIFO status of the specified SLED. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus SLED_GetResetCodeStatus(HT_SLED_TypeDef* SLEDx) +{ + if ((SLEDx->CR & (1 << 15)) != RESET) + return SET; + else + return RESET; +} + +/*********************************************************************************************************//** + * @brief Return the BUSY status of the specified SLED. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus SLED_GetBusyStatus(HT_SLED_TypeDef* SLEDx) +{ + if (SLEDx->SR & 1) + return SET; + else + return RESET; +} + +/*********************************************************************************************************//** + * @brief Set the specified SLED FIFO trigger level. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @param FifoLevel: specify the FIFO trigger level. + * This parameter can be one of the following values: + * @arg SLED_FIFO_LEVEL_0 : data request will be inserted when FIFO data count is equal to 0 + * @arg SLED_FIFO_LEVEL_1 : data request will be inserted when FIFO data count is less than or equal to 1 + * @arg SLED_FIFO_LEVEL_2 : data request will be inserted when FIFO data count is less than or equal to 2 + * @arg SLED_FIFO_LEVEL_3 : data request will be inserted when FIFO data count is less than or equal to 3 + * @retval None + ************************************************************************************************************/ +void SLED_FIFOTrigLevelConfig(HT_SLED_TypeDef* SLEDx, u8 FifoLevel) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + Assert_Param(IS_SLED_FIFO_LEVEL(FifoLevel)); + + SLEDx->FCR = FifoLevel; +} + +/*********************************************************************************************************//** + * @brief Return the FIFO status of the specified SLED. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @retval The number of data in FIFO. + ************************************************************************************************************/ +u8 SLED_GetFIFOStatus(HT_SLED_TypeDef* SLEDx) +{ + return (SLEDx->FCR >> 24); +} + +/*********************************************************************************************************//** + * @brief Reset the specified SLED FIFO. + * @param SLEDx: where SLEDx is the selected SLED from the SLED peripherals. + * @retval None + ************************************************************************************************************/ +void SLED_FIFOReset(HT_SLED_TypeDef* SLEDx) +{ + /* Check the parameters */ + Assert_Param(IS_SLED(SLEDx)); + + SLEDx->FCR |= (1 << 0); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi.c new file mode 100644 index 00000000000..55158596419 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi.c @@ -0,0 +1,712 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_spi.c + * @version $Rev:: 7322 $ + * @date $Date:: 2023-10-28 #$ + * @brief This file provides all the SPI firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_spi.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI driver modules + * @{ + */ + + +#if (LIBCFG_MIDI) +#include "ht32f5xxxx_spi_midi.c" +#endif + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Private_Define SPI private definitions + * @{ + */ +/* SPI SPIEN Mask */ +#define CR0_SPIEN_SET (u32)0x00000001 +#define CR0_SPIEN_RESET (u32)0xFFFFFFFE + +/* SPI SELOEN Mask */ +#define CR0_SELOEN_SET (u32)0x00000008 +#define CR0_SELOEN_RESET (u32)0xFFFFFFF7 + +/* SPI SPI DUALEN Mask */ +#define CR0_DUALEN_SET (u32)0x00000040 +#define CR0_DUALEN_RESET (u32)0xFFFFFFBF + +#if (LIBCFG_QSPI) +/* QSPI QUADEN Mask */ +#define CR0_QUADEN_SET (u32)0x00020000 +#define CR0_QUADEN_RESET (u32)0xFFFDFFFF +/* QSPI QDIODIR Mask */ +#define CR0_QDIODIR_OUT (u32)0x00010000 +#define CR0_QDIODIR_IN (u32)0xFFFEFFFF +#endif + +/* SPI SPI GUADTEN Mask */ +#define CR0_GUADTEN_SET (u32)0x00000080 +#define CR0_GUADTEN_RESET (u32)0xFFFFFF7F + +/* SPI FIFOEN Mask */ +#define FCR_FIFOEN_SET (u32)0x00000400 +#define FCR_FIFOEN_RESET (u32)0xFFFFFBFF + +/* SPI DFL Mask */ +#if (LIBCFG_SPI_DATA_LENGTH_V01) +#define CR1_DFL_MASK (u32)0x00000007 +#else +#define CR1_DFL_MASK (u32)0x0000000F +#endif + +/* SPI FIFO Mask */ +#if (LIBCFG_SPI_FIFO_DEPTH_V01) +#define FCR_FIFO_MASK (u32)0x00000007 +#else +#define FCR_FIFO_MASK (u32)0x0000000F +#endif + +/** + * @} + */ + + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the SPI peripheral registers to their default reset values. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @retval None + ************************************************************************************************************/ +void SPI_DeInit(HT_SPI_TypeDef* SPIx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + + if (SPIx == HT_SPI0) + { + RSTCUReset.Bit.SPI0 = 1; + } + #if (LIBCFG_SPI1) + else if (SPIx == HT_SPI1) + { + RSTCUReset.Bit.SPI1 = 1; + } + #endif + #if (LIBCFG_QSPI) + else if (SPIx == HT_QSPI) + { + RSTCUReset.Bit.QSPI = 1; + } + #endif + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the SPIx peripheral according to the specified parameters in the SPI_InitStruct. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SPI_Init(HT_SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + u32 tmp; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + Assert_Param(IS_SPI_FIFO_SET(SPI_InitStruct->SPI_FIFO)); + Assert_Param(IS_SPI_DATALENGTH(SPI_InitStruct->SPI_DataLength)); + Assert_Param(IS_SPI_SEL_MODE(SPI_InitStruct->SPI_SELMode)); + Assert_Param(IS_SPI_SEL_POLARITY(SPI_InitStruct->SPI_SELPolarity)); + Assert_Param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + Assert_Param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + Assert_Param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + Assert_Param(IS_SPI_FIFO_LEVEL(SPI_InitStruct->SPI_RxFIFOTriggerLevel)); + Assert_Param(IS_SPI_FIFO_LEVEL(SPI_InitStruct->SPI_TxFIFOTriggerLevel)); + Assert_Param(IS_SPI_CLOCK_PRESCALER(SPI_InitStruct->SPI_ClockPrescaler)); + + /*---------------------------- SPIx Control Register 2 Configuration -------------------------------------*/ + tmp = SPI_InitStruct->SPI_CPOL; + if (tmp == SPI_CPOL_LOW) + { + tmp |= (0x100 << SPI_InitStruct->SPI_CPHA); + } + else + { + tmp |= (0x200 >> SPI_InitStruct->SPI_CPHA); + } + + SPIx->CR1 = SPI_InitStruct->SPI_Mode | SPI_InitStruct->SPI_DataLength | + SPI_InitStruct->SPI_SELMode | SPI_InitStruct->SPI_SELPolarity | + SPI_InitStruct->SPI_FirstBit | tmp; + + /*---------------------------- SPIx FIFO Control Register Configuration ----------------------------------*/ + SPIx->FCR = SPI_InitStruct->SPI_FIFO | SPI_InitStruct->SPI_TxFIFOTriggerLevel | + (SPI_InitStruct->SPI_RxFIFOTriggerLevel << 4); + + /*---------------------------- SPIx Clock Prescaler Register Configuration -------------------------------*/ + #if (LIBCFG_SPI_CLK_PRE_V01) + SPIx->CPR = (SPI_InitStruct->SPI_ClockPrescaler - 1); + #else + SPIx->CPR = (SPI_InitStruct->SPI_ClockPrescaler / 2) - 1; + #endif +} + +/*********************************************************************************************************//** + * @brief Fill each SPI_InitStruct member with its default value. + * @param SPI_InitStruct: pointer to an SPI_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ + /* Initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_SLAVE; + + /* Initialize the SPI_FIFO member */ + SPI_InitStruct->SPI_FIFO = SPI_FIFO_DISABLE; + + /* Initialize the SPI_DataLength member */ + #if (LIBCFG_SPI_DATA_LENGTH_V01) + SPI_InitStruct->SPI_DataLength = SPI_DATALENGTH_8; + #else + SPI_InitStruct->SPI_DataLength = SPI_DATALENGTH_16; + #endif + + /* Initialize the SPI_SELMode member */ + SPI_InitStruct->SPI_SELMode = SPI_SEL_SOFTWARE; + + /* Initialize the SPI_SELPolarity member */ + SPI_InitStruct->SPI_SELPolarity = SPI_SELPOLARITY_LOW; + + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_LOW; + + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_FIRST; + + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FIRSTBIT_MSB; + + /* Initialize the SPI_RxFIFOTriggerLevel member */ + SPI_InitStruct->SPI_RxFIFOTriggerLevel = 0; + + /* Initialize the SPI_TxFIFOTriggerLevel member */ + SPI_InitStruct->SPI_TxFIFOTriggerLevel = 0; + + /* Initialize the SPI_ClockPrescaler member */ + SPI_InitStruct->SPI_ClockPrescaler = 2; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SPI peripheral. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_Cmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR0 |= CR0_SPIEN_SET; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR0 &= CR0_SPIEN_RESET; + } +} + +#if (!LIBCFG_SPI_NO_MULTI_MASTER) +/*********************************************************************************************************//** + * @brief Enable or Disable the SEL output for the specified SPI peripheral. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_SELOutputCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->CR0 |= CR0_SELOEN_SET; + } + else + { + SPIx->CR0 &= CR0_SELOEN_RESET; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable SPI FIFO. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_FIFOCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->FCR |= FCR_FIFOEN_SET; + } + else + { + SPIx->FCR &= FCR_FIFOEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Configure the data length for the selected SPI. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_DataLength: specify data length of the SPI. + * @retval None + ************************************************************************************************************/ +void SPI_SetDataLength(HT_SPI_TypeDef* SPIx, u16 SPI_DataLength) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_DATALENGTH(SPI_DataLength)); + + /* Clear DFL[x:0] in CR1. + if Datalength is 16-bit mode, then x = 3 + if Datalength is 8-bit mode, then x = 2 */ + SPIx->CR1 &= (u32)~CR1_DFL_MASK; + + /* Set new DFL[x:0] in CR1. + if Datalength is 16-bit mode, then x = 3 + if Datalength is 8-bit mode, then x = 2 */ + SPIx->CR1 |= SPI_DataLength; +} + +/*********************************************************************************************************//** + * @brief SEL pin is configured to be driven by hardware or software. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_SEL: specify the SPI SEL pin mode. + * This parameter can be one of the following values: + * @arg SPI_SEL_HARDWARE : SEL is driven by hardware + * @arg SPI_SEL_SOFTWARE : SEL is driven by software + * @retval None + ************************************************************************************************************/ +void SPI_SELModeConfig(HT_SPI_TypeDef* SPIx, u32 SPI_SEL) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_SEL_MODE(SPI_SEL)); + + if (SPI_SEL != SPI_SEL_SOFTWARE) + { + SPIx->CR1 |= SPI_SEL_HARDWARE; + } + else + { + SPIx->CR1 &= ~SPI_SEL_HARDWARE; + } +} + +/*********************************************************************************************************//** + * @brief Configure the SEL state by software. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_SoftwareSEL: specify if the SPI SEL to be active or inactive. + * This parameter can be one of the following values: + * @arg SPI_SEL_ACTIVE : activate SEL signal + * @arg SPI_SEL_INACTIVE : deactivate SEL signal + * @retval None + ************************************************************************************************************/ +void SPI_SoftwareSELCmd(HT_SPI_TypeDef* SPIx, u32 SPI_SoftwareSEL) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_SOFTWARE_SEL(SPI_SoftwareSEL)); + + if (SPI_SoftwareSEL != SPI_SEL_INACTIVE) + { + SPIx->CR0 |= SPI_SEL_ACTIVE; + } + else + { + SPIx->CR0 &= SPI_SEL_INACTIVE; + } +} + +/*********************************************************************************************************//** + * @brief Send a data through the SPIx peripheral. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Data: the data to be transmitted. + * @retval None + ************************************************************************************************************/ +void SPI_SendData(HT_SPI_TypeDef* SPIx, SPI_DataTypeDef SPI_Data) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_DATA(SPI_Data)); + + SPIx->DR = SPI_Data; +} + +/*********************************************************************************************************//** + * @brief Return the received data through the SPIx peripheral + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @retval The value of the received data. + ************************************************************************************************************/ +SPI_DataTypeDef SPI_ReceiveData(HT_SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + + return (SPI_DataTypeDef)SPIx->DR; +} + +/*********************************************************************************************************//** + * @brief Set the value of SPI FIFO Time Out. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Timeout: specify the value of Time Out. + * @retval None + ************************************************************************************************************/ +void SPI_SetTimeOutValue(HT_SPI_TypeDef* SPIx, SPI_TimeoutTypeDef SPI_Timeout) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + + SPIx->FTOCR = SPI_Timeout; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified SPI interrupt. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Int: specify if the SPI interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_INT_TXBE : SPI Tx buffer empty interrupt + * @arg SPI_INT_TXE : SPI Tx empty interrupt + * @arg SPI_INT_RXBNE : SPI Rx buffer not empty interrupt + * @arg SPI_INT_WC : SPI write collision interrupt + * @arg SPI_INT_RO : SPI read overrun interrupt + * @arg SPI_INT_MF : SPI mode fault interrupt + * @arg SPI_INT_SA : SPI slave abort interrupt + * @arg SPI_INT_TO : SPI time out interrupt + * @arg SPI_INT_ALL : All SPI interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_IntConfig(HT_SPI_TypeDef* SPIx, u32 SPI_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_INT(SPI_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->IER |= SPI_Int; + } + else + { + SPIx->IER &= (u32)~SPI_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified SPI flag has been set or not. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_TXBE : SPI Tx buffer empty flag + * @arg SPI_FLAG_TXE : SPI Tx empty flag + * @arg SPI_FLAG_RXBNE : SPI Rx buffer not empty flag + * @arg SPI_FLAG_WC : SPI write collision flag + * @arg SPI_FLAG_RO : SPI read overrun flag + * @arg SPI_FLAG_MF : SPI mode fault flag + * @arg SPI_FLAG_SA : SPI slave abort flag + * @arg SPI_FLAG_TOUT : SPI time out flag + * @arg SPI_FLAG_BUSY : SPI busy flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus SPI_GetFlagStatus(HT_SPI_TypeDef* SPIx, u32 SPI_Flag) +{ + FlagStatus bitstatus = RESET; + u32 statusreg = 0; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FLAG(SPI_Flag)); + + statusreg = SPIx->SR; + + if ((statusreg & SPI_Flag) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Return the status of specified SPI FIFO. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_FIFODirection: specify the FIFO that is to be checked. + * This parameter can be one of the following values: + * @arg SPI_FIFO_TX : + * @arg SPI_FIFO_RX : + * @retval The number of data in Tx FIFO or Rx FIFO. + ************************************************************************************************************/ +u8 SPI_GetFIFOStatus(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection) +{ + u32 tmpreg; + + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FIFO_DIRECTION(SPI_FIFODirection)); + + if (SPI_FIFODirection == SPI_FIFO_TX) + { + tmpreg = SPIx->FSR & FCR_FIFO_MASK; + } + else + { + tmpreg = (SPIx->FSR & (FCR_FIFO_MASK << 4)) >> 4; + } + + return (u8)tmpreg; +} + +/*********************************************************************************************************//** + * @brief Clear the specified SPI flag. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_Flag: specify the flag that is to be cleared. + * This parameter can be one of the following values: + * @arg SPI_FLAG_WC : SPI write collision flag + * @arg SPI_FLAG_RO : SPI read overrun flag + * @arg SPI_FLAG_MF : SPI mode fault flag + * @arg SPI_FLAG_SA : SPI slave abort flag + * @arg SPI_FLAG_TOUT : SPI time out flag + * @retval None + ************************************************************************************************************/ +void SPI_ClearFlag(HT_SPI_TypeDef* SPIx, u32 SPI_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FLAG_CLEAR(SPI_Flag)); + + SPIx->SR = SPI_Flag; +} + +/*********************************************************************************************************//** + * @brief Set the trigger level of SPI FIFO. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_FIFODirection: specify the FIFO that is to be set. + * This parameter can be one of the following values: + * @arg SPI_FIFO_TX : + * @arg SPI_FIFO_RX : + * @param SPI_FIFOLevel: Specify the FIFO trigger level. + * @retval None + ************************************************************************************************************/ +void SPI_FIFOTriggerLevelConfig(HT_SPI_TypeDef* SPIx, u32 SPI_FIFODirection, u8 SPI_FIFOLevel) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_FIFO_DIRECTION(SPI_FIFODirection)); + Assert_Param(IS_SPI_FIFO_LEVEL(SPI_FIFOLevel)); + + if (SPI_FIFODirection == SPI_FIFO_TX) + { + SPIx->FCR = ((SPIx->FCR & (0x00000400 | (FCR_FIFO_MASK << 4))) | SPI_FIFOLevel); + } + else + { + SPIx->FCR = ((SPIx->FCR & (0x00000400 | FCR_FIFO_MASK)) | (SPI_FIFOLevel << 4)); + } +} + +#if (LIBCFG_PDMA) +/*********************************************************************************************************//** + * @brief Enable or Disable the SPIx PDMA interface. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param SPI_PDMAREQ: specify the SPI PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_PDMAREQ_TX : Tx PDMA transfer request + * @arg SPI_PDMAREQ_RX : Rx PDMA transfer request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_PDMACmd(HT_SPI_TypeDef* SPIx, u32 SPI_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_PDMA_REQ(SPI_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + SPIx->CR0 |= SPI_PDMAREQ; + } + else + { + SPIx->CR0 &= ~SPI_PDMAREQ; + } +} +#endif + +#if (!LIBCFG_SPI_NO_DUAL) +/*********************************************************************************************************//** + * @brief Enable or Disable the SPIx dual port read interface. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_DUALCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + (NewState == ENABLE)?(SPIx->CR0 |= CR0_DUALEN_SET):(SPIx->CR0 &= CR0_DUALEN_RESET); +} +#endif + +#if (LIBCFG_QSPI) +/*********************************************************************************************************//** + * @brief Enable or Disable the QSPI quad port interface. + * @param SPIx: where SPIx is the selected QSPI from the QSPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void QSPI_QuadCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_QSPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == DISABLE) + { + QSPI_DirectionConfig(SPIx, SIO_DIR_IN); + SPIx->CR0 &= CR0_QUADEN_RESET; + } + else + { + SPIx->CR0 |= CR0_QUADEN_SET; + } +} + +/*********************************************************************************************************//** + * @brief Configure the direction of SIO pins in dual or quad mode. + * @param SPIx: where SPIx is the selected QSPI from the QSPI peripherals. + * @param SIO_DIR_INorOUT: + * This parameter can be one of below: + * @arg SIO_DIR_IN : The SIO pins are input mode + * @arg SIO_DIR_OUT : The SIO pins are output mode + * @retval None + ************************************************************************************************************/ +void QSPI_DirectionConfig(HT_SPI_TypeDef* SPIx, SIO_DIR_Enum SIO_DIR_INorOUT) +{ + /* Check the parameters */ + Assert_Param(IS_QSPI(SPIx)); + Assert_Param(IS_SIO_DIR(SIO_DIR_INorOUT)); + + if (SIO_DIR_INorOUT != SIO_DIR_IN) + SPIx->CR0 |= CR0_QDIODIR_OUT; + else + SPIx->CR0 &= CR0_QDIODIR_IN; +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the SPIx guard time selection function. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void SPI_GUARDTCmd(HT_SPI_TypeDef* SPIx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + (NewState == ENABLE) ? (SPIx->CR0 |= CR0_GUADTEN_SET) : (SPIx->CR0 &= CR0_GUADTEN_RESET); +} + +/*********************************************************************************************************//** + * @brief Set the SPIx guard time length. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param Guard_Time: number of SCK to be the guard time length. + * This parameter can be: SPI_GUADTIME_1_SCK to SPI_GUADTIME_16_SCK. + * @retval None + ************************************************************************************************************/ +void SPI_GUARDTConfig(HT_SPI_TypeDef* SPIx, u32 Guard_Time) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_GUADTIME(Guard_Time)); + + SPIx->CR0 = (SPIx->CR0 & 0xF0FF) | (Guard_Time << 8); +} + +/*********************************************************************************************************//** + * @brief Set the SPIx chip select hold time. + * @param SPIx: where SPIx is the selected SPI from the SPI peripherals. + * @param CS_Hold_Time: number of SCK to be the hold time length. + * This parameter can be: 0 ~ 15 + * @retval None + ************************************************************************************************************/ +void SPI_SELHTConfig(HT_SPI_TypeDef* SPIx, u32 CS_Hold_Time) +{ + /* Check the parameters */ + Assert_Param(IS_SPI(SPIx)); + Assert_Param(IS_SPI_SELHOLDTIME(CS_Hold_Time)); + + SPIx->CR0 = (SPIx->CR0 & 0x0FFF) | (CS_Hold_Time << 12); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi_midi.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi_midi.c new file mode 100644 index 00000000000..69a78217ee0 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_spi_midi.c @@ -0,0 +1,182 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_spi_midi.c + * @version $Rev:: 7073 $ + * @date $Date:: 2023-07-28 #$ + * @brief This file provides all the SPI firmware functions (MIDI Control). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_spi_midi.h" + + +/* Private macro -------------------------------------------------------------------------------------------*/ +#define IS_MIDICTRL_MODE(MODE) ((MODE == DOR_MODE) || \ + (MODE == DIOR_MODE) || \ + (MODE == QOR_MODE) || \ + (MODE == QIOR_MODE) || \ + (MODE == QPI_MODE) || \ + (MODE == SERIAL_MODE)) + +#define IS_MIDICTRL_CMD_LENGTH(LENGTH) ((LENGTH == MIDICTRL_CMDLENGTH_0) || \ + (LENGTH == MIDICTRL_CMDLENGTH_1) || \ + (LENGTH == MIDICTRL_CMDLENGTH_2) || \ + (LENGTH == MIDICTRL_CMDLENGTH_3) || \ + (LENGTH == MIDICTRL_CMDLENGTH_4) || \ + (LENGTH == MIDICTRL_CMDLENGTH_5) || \ + (LENGTH == MIDICTRL_CMDLENGTH_6) || \ + (LENGTH == MIDICTRL_CMDLENGTH_7) || \ + (LENGTH == MIDICTRL_CMDLENGTH_8)) + +#define IS_MIDICTRL_AD_LENGTH(LENGTH) ((LENGTH == MIDICTRL_ADLENGTH_0) || \ + (LENGTH == MIDICTRL_ADLENGTH_1) || \ + (LENGTH == MIDICTRL_ADLENGTH_2) || \ + (LENGTH == MIDICTRL_ADLENGTH_3) || \ + (LENGTH == MIDICTRL_ADLENGTH_4) || \ + (LENGTH == MIDICTRL_ADLENGTH_5) || \ + (LENGTH == MIDICTRL_ADLENGTH_6) || \ + (LENGTH == MIDICTRL_ADLENGTH_7) || \ + (LENGTH == MIDICTRL_ADLENGTH_8) || \ + (LENGTH == MIDICTRL_ADLENGTH_9) || \ + (LENGTH == MIDICTRL_ADLENGTH_10) || \ + (LENGTH == MIDICTRL_ADLENGTH_11) || \ + (LENGTH == MIDICTRL_ADLENGTH_12) || \ + (LENGTH == MIDICTRL_ADLENGTH_13) || \ + (LENGTH == MIDICTRL_ADLENGTH_14) || \ + (LENGTH == MIDICTRL_ADLENGTH_15) || \ + (LENGTH == MIDICTRL_ADLENGTH_16) || \ + (LENGTH == MIDICTRL_ADLENGTH_17) || \ + (LENGTH == MIDICTRL_ADLENGTH_18) || \ + (LENGTH == MIDICTRL_ADLENGTH_19) || \ + (LENGTH == MIDICTRL_ADLENGTH_20) || \ + (LENGTH == MIDICTRL_ADLENGTH_21) || \ + (LENGTH == MIDICTRL_ADLENGTH_22) || \ + (LENGTH == MIDICTRL_ADLENGTH_23) || \ + (LENGTH == MIDICTRL_ADLENGTH_24)) + +#define IS_MIDICTRL_MODE_LENGTH(LENGTH) ((LENGTH == MIDICTRL_MODELENGTH_0) || \ + (LENGTH == MIDICTRL_MODELENGTH_1) || \ + (LENGTH == MIDICTRL_MODELENGTH_2) || \ + (LENGTH == MIDICTRL_MODELENGTH_3) || \ + (LENGTH == MIDICTRL_MODELENGTH_4) || \ + (LENGTH == MIDICTRL_MODELENGTH_5) || \ + (LENGTH == MIDICTRL_MODELENGTH_6) || \ + (LENGTH == MIDICTRL_MODELENGTH_7) || \ + (LENGTH == MIDICTRL_MODELENGTH_8)) + +#define IS_MIDICTRL_DUMMY_LENGTH(LENGTH) ((LENGTH == MIDICTRL_DUMMYLENGTH_0) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_1) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_2) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_3) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_4) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_5) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_6) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_7) || \ + (LENGTH == MIDICTRL_DUMMYLENGTH_8)) + +#define IS_MIDICTRL_DATA_LENGTH(LENGTH) ((LENGTH == MIDICTRL_DATALENGTH_0) || \ + (LENGTH == MIDICTRL_DATALENGTH_1) || \ + (LENGTH == MIDICTRL_DATALENGTH_2) || \ + (LENGTH == MIDICTRL_DATALENGTH_3) || \ + (LENGTH == MIDICTRL_DATALENGTH_4) || \ + (LENGTH == MIDICTRL_DATALENGTH_5) || \ + (LENGTH == MIDICTRL_DATALENGTH_6) || \ + (LENGTH == MIDICTRL_DATALENGTH_7) || \ + (LENGTH == MIDICTRL_DATALENGTH_8) || \ + (LENGTH == MIDICTRL_DATALENGTH_9) || \ + (LENGTH == MIDICTRL_DATALENGTH_10) || \ + (LENGTH == MIDICTRL_DATALENGTH_11) || \ + (LENGTH == MIDICTRL_DATALENGTH_12) || \ + (LENGTH == MIDICTRL_DATALENGTH_13) || \ + (LENGTH == MIDICTRL_DATALENGTH_14) || \ + (LENGTH == MIDICTRL_DATALENGTH_15) || \ + (LENGTH == MIDICTRL_DATALENGTH_16) || \ + (LENGTH == MIDICTRL_DATALENGTH_17) || \ + (LENGTH == MIDICTRL_DATALENGTH_18) || \ + (LENGTH == MIDICTRL_DATALENGTH_19) || \ + (LENGTH == MIDICTRL_DATALENGTH_20) || \ + (LENGTH == MIDICTRL_DATALENGTH_21) || \ + (LENGTH == MIDICTRL_DATALENGTH_22) || \ + (LENGTH == MIDICTRL_DATALENGTH_23) || \ + (LENGTH == MIDICTRL_DATALENGTH_24) || \ + (LENGTH == MIDICTRL_DATALENGTH_25) || \ + (LENGTH == MIDICTRL_DATALENGTH_26) || \ + (LENGTH == MIDICTRL_DATALENGTH_27) || \ + (LENGTH == MIDICTRL_DATALENGTH_28) || \ + (LENGTH == MIDICTRL_DATALENGTH_29) || \ + (LENGTH == MIDICTRL_DATALENGTH_30) || \ + (LENGTH == MIDICTRL_DATALENGTH_31) || \ + (LENGTH == MIDICTRL_DATALENGTH_32)) + +#define IS_MIDICTRL_CMD_VALUE(VALUE) (VALUE <= 0xFF) +#define IS_MIDICTRL_MODE_VALUE(VALUE) (VALUE <= 0xFF) + +/* Global functions ----------------------------------------------------------------------------------------*/ +/*********************************************************************************************************//** + * @brief Enable or Disable QSPI MIDICTRL. + * @param QSPIx: where QSPIx is the selected QSPI from the QSPI peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void MIDICTRL_Cmd(HT_SPI_TypeDef* QSPIx ,ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + QSPIx->MIDICR0 |= MIDICTRL_ON; + } + else + { + QSPIx->MIDICR0 &= MIDICTRL_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Initialize the QSPIx peripheral MIDICTRL according to the specified parameters in the MIDICTRL_InitStruct. + * @param QSPIx: This parameter can be HT_QSPI. + * @param MIDICTRL_InitStruct: pointer to a MIDICTRL_InitTypeDef structure that contains the configuration + * information for the specified USART peripheral. + * @retval None + ************************************************************************************************************/ +void MIDICTRL_Init(HT_SPI_TypeDef* QSPIx, MIDICTRL_InitTypeDef* MIDICTRL_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_QSPI(QSPIx)); + Assert_Param(IS_MIDICTRL_MODE(MIDICTRL_InitStruct->MIDICTRL_MODE)); + Assert_Param(IS_MIDICTRL_CMD_LENGTH(MIDICTRL_InitStruct->MIDICTRL_CommandLength)); + Assert_Param(IS_MIDICTRL_AD_LENGTH(MIDICTRL_InitStruct->MIDICTRL_AddressLength)); + Assert_Param(IS_MIDICTRL_MODE_LENGTH(MIDICTRL_InitStruct->MIDICTRL_ModeLength)); + Assert_Param(IS_MIDICTRL_DUMMY_LENGTH(MIDICTRL_InitStruct->MIDICTRL_DummyLength)); + Assert_Param(IS_MIDICTRL_DATA_LENGTH(MIDICTRL_InitStruct->MIDICTRL_DataLength)); + Assert_Param(IS_MIDICTRL_CMD_VALUE(MIDICTRL_InitStruct->MIDICTRL_CommandValue)); + Assert_Param(IS_MIDICTRL_MODE_VALUE(MIDICTRL_InitStruct->MIDICTRL_ModeValue)); + + QSPIx->MIDICR0 = (QSPIx->MIDICR0 & 0xF0800000) | MIDICTRL_InitStruct->MIDICTRL_MODE | + MIDICTRL_InitStruct->MIDICTRL_CommandLength | MIDICTRL_InitStruct->MIDICTRL_AddressLength | + MIDICTRL_InitStruct->MIDICTRL_ModeLength | MIDICTRL_InitStruct->MIDICTRL_DummyLength | + MIDICTRL_InitStruct->MIDICTRL_DataLength ; + + QSPIx->MIDICR1 = (QSPIx->MIDICR1 & 0xFFFF0000) | ((MIDICTRL_InitStruct->MIDICTRL_ModeValue) << MDVALUE_POS )| + ((MIDICTRL_InitStruct->MIDICTRL_CommandValue) << CMDVALUE_POS ); +} diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tkey.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tkey.c new file mode 100644 index 00000000000..a6e482d6a08 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tkey.c @@ -0,0 +1,703 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_tkey.c + * @version $Rev:: 5500 $ + * @date $Date:: 2021-07-20 #$ + * @brief This file provides all the TKEY firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_tkey.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup TKEY TKEY + * @brief TKEY driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup TKEY_Private_Define TKEY private definitions + * @{ + */ +#define TKCLKSEL_MASK (0x80000000) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup TKEY_Exported_Functions TKEY exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the TKEY peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void TKEY_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.TKEY = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Configure Touch key IP clock source. + * @param Sel: Specify the Touch key IP clock source.. + * This parameter can be one of the following values: + * @arg TKEY_PCLK : PCLK. + * @arg TKEY_LSI : LSI. + * @retval None + ************************************************************************************************************/ +void TKEY_IPClockConfig(TKEY_IP_CLK_Enum Sel) +{ + Assert_Param(IS_TKEY_IP_CLK(Sel)); + + HT_TKEY->TKCR = (HT_TKEY->TKCR & TKCLKSEL_MASK) | (Sel << 31); +} + +/*********************************************************************************************************//** + * @brief Configure the RefOSC Delay time. + * @param Sel: Specify the periodic auto scan mode time out. + * This parameter can be one of the following values: + * @arg TKEY_RefOSC_DelayTime_0 : 4 RefOSC clock. + * @arg TKEY_RefOSC_DelayTime_1 : 2 RefOSC clock. + * @arg TKEY_RefOSC_DelayTime_2 : 4 RefOSC clock. + * @arg TKEY_RefOSC_DelayTime_3 : 8 RefOSC clock. + * @arg TKEY_RefOSC_DelayTime_4 : 16 RefOSC clock. + * @arg TKEY_RefOSC_DelayTime_5 : 32 RefOSC clock. + * @arg TKEY_RefOSC_DelayTime_6 : 64 RefOSC clock. + * @arg TKEY_RefOSC_DelayTime_7 : 4 RefOSC clock. + * @retval None + ************************************************************************************************************/ +void TKEY_RefOSCDelayTimeConfig(TKEY_RefOSC_DelayTime_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_RefOSC_DelayTime(Sel)); + + HT_TKEY->TKCR = (HT_TKEY->TKCR & ~(7 << 13)) | Sel; +} +/*********************************************************************************************************//** + * @brief Configure the periodic auto scan mode time out. + * @param Sel: Specify the periodic auto scan mode time out. + * This parameter can be one of the following values: + * @arg TKEY_PASM_TIMEOUT_0 : 2^13/FLIRC. + * @arg TKEY_PASM_TIMEOUT_1 : 2^14/FLIRC. + * @arg TKEY_PASM_TIMEOUT_2 : 2^15/FLIRC. + * @arg TKEY_PASM_TIMEOUT_3 : 2^16/FLIRC. + * @arg TKEY_PASM_TIMEOUT_4 : 2^17/FLIRC. + * @arg TKEY_PASM_TIMEOUT_5 : 2^18/FLIRC. + * @retval None + ************************************************************************************************************/ +void TKEY_PASMTimeoutConfig(TKEY_PASM_TIMEOUT_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_PASM_TIMEOUT(Sel)); + + HT_TKEY->TKCR = (HT_TKEY->TKCR & ~(7 << 10)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the periodic auto scan mode period. + * @param Sel: Specify the periodic auto scan mode period. + * This parameter can be one of the following values: + * @arg TKEY_PASM_PERIOD_0 : 2^14/FLIRC. + * @arg TKEY_PASM_PERIOD_1 : 2^13/FLIRC. + * @arg TKEY_PASM_PERIOD_2 : 2^12/FLIRC. + * @arg TKEY_PASM_PERIOD_3 : 2^11/FLIRC. + * @retval None + ************************************************************************************************************/ +void TKEY_PASMPeriodConfig(TKEY_PASM_PERIOD_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_PASM_PERIOD(Sel)); + + HT_TKEY->TKCR = (HT_TKEY->TKCR & ~(3 << 8)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the touch key 16-bit counter clock source. + * @param Sel: Specify the 16-bit counter clock source. + * This parameter can be one of the following values: + * @arg TKEY_TK16S_CLK_0 : TKCLK/16. + * @arg TKEY_TK16S_CLK_1 : TKCLK/32. + * @arg TKEY_TK16S_CLK_2 : TKCLK/64. + * @arg TKEY_TK16S_CLK_3 : TKCLK/128. + * @retval None + ************************************************************************************************************/ +void TKEY_16BitCounterClockConfig(TKEY_TK16S_CLK_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_TK16S_CLK(Sel)); + + HT_TKEY->TKCR = (HT_TKEY->TKCR & ~(3 << 5)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the touch key OSC frequency. + * @param Sel: Specify the Touch Key frequency. + * This parameter can be one of the following values: + * @arg TKEY_TKFS_FREQ_0 : 1MHz. + * @arg TKEY_TKFS_FREQ_1 : 3MHz. + * @arg TKEY_TKFS_FREQ_2 : 7MHz. + * @arg TKEY_TKFS_FREQ_3 : 11MHz. + * @retval None + ************************************************************************************************************/ +void TKEY_OSCFreqConfig(TKEY_TKFS_FREQ_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_TKFS_FREQ(Sel)); + + HT_TKEY->TKCR = (HT_TKEY->TKCR & ~(3 << 3)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the touch key operation mode. + * @param Sel: Specify the Touch Key mode. + * This parameter can be one of the following values: + * @arg TKEY_MODE_AUTOSCAN : Auto scan mode. + * @arg TKEY_MODE_MANUAL : Manual mode. + * @arg TKEY_MODE_PASM : Periodic auto scan mode. + * @retval None + ************************************************************************************************************/ +void TKEY_ModeConfig(TKEY_MODE_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_MODE(Sel)); + + HT_TKEY->TKCR = (HT_TKEY->TKCR & ~(3 << 1)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Touch Key detection control. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TKEY_StartCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_TKEY->TKCR |= (1 << 0); + } + else + { + HT_TKEY->TKCR &= ~(1 << 0); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified TKEY interrupt. + * @param TKEY_Int: specify if the TKEY interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TKEY_INT_TKRCOVE : 8-bit time slot counter overflow interrupt + * @arg TKEY_INT_TKTHE : Touch Key threshold match interrupt + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TKEY_IntConfig(u32 TKEY_Int, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_INT(TKEY_Int)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_TKEY->TKIER |= TKEY_Int; + } + else + { + HT_TKEY->TKIER &= ~TKEY_Int; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified TKEY flag has been set or not. + * @param TKEY_Flag: specify the flag that is to be check. + * This parameter can be one of the following values: + * @arg TKEY_FLAG_TKBUSY : Touch Key busy flag + * @arg TKEY_FLAG_TKCFOV : Touch Key 16-bit C/F counter overflow flag + * @arg TKEY_FLAG_TK16OV : Touch Key 16-bit counter overflow flag + * @arg TKEY_FLAG_TKRCOVF : 8-bit time slot counter overflow flag + * @arg TKEY_FLAG_TKTHF : Touch Key threshold match flag + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus TKEY_GetFlagStatus(u32 TKEY_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_FLAG(TKEY_Flag)); + + if ((HT_TKEY->TKSR & TKEY_Flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified TKEY flag. + * @param TKEY_Flag: specify the flag that is to be cleared. + * This parameter can be one of the following values: + * @arg TKEY_FLAG_TKCFOV : Touch Key 16-bit C/F counter overflow flag + * @arg TKEY_FLAG_TK16OV : Touch Key 16-bit counter overflow flag + * @arg TKEY_FLAG_TKRCOVF : 8-bit time slot counter overflow flag + * @arg TKEY_FLAG_TKTHF : Touch Key threshold match flag + * @retval None + ************************************************************************************************************/ +void TKEY_ClearFlag(u32 TKEY_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_TKEY_FLAG_CLEAR(TKEY_Flag)); + + HT_TKEY->TKSR = TKEY_Flag; +} + +/*********************************************************************************************************//** + * @brief Get the touch key 16-bit counter value. + * @retval The counter value + ************************************************************************************************************/ +u32 TKEY_Get16BitCounterValue(void) +{ + return HT_TKEY->TKCNTR; +} + +/*********************************************************************************************************//** + * @brief Set the 8-bit time slot counter reload value. + * @param Reload: Specify the counter reload value. + * @retval None + ************************************************************************************************************/ +void TKEY_Set8BitCounterReload(u32 Reload) +{ + HT_TKEY->TKTSCRR = Reload; +} + +/*********************************************************************************************************//** + * @brief Get the 8-bit time slot counter reload value. + * @retval The counter reload value + ************************************************************************************************************/ +u32 TKEY_Get8BitCounterReload(void) +{ + return HT_TKEY->TKTSCRR; +} + +/*********************************************************************************************************//** + * @brief Configure the 8-bit time slot counter clock source. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Sel: Specify the 8-bit time slot counter clock source. + * This parameter can be one of the following values: + * @arg TKM_TSS_CLK_0 : Ref OSC. + * @arg TKM_TSS_CLK_1 : TKCLK/32. + * @arg TKM_TSS_CLK_2 : TKCLK/64. + * @arg TKM_TSS_CLK_3 : TKCLK/128. + * @retval None + ************************************************************************************************************/ +void TKM_TimeSlotCounterClockConfig(TKM_Enum TKMn, TKM_TSS_CLK_Enum Sel) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_TSS_CLK(Sel)); + + TKMx->CR = (TKMx->CR & ~(3 << 8)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the Reference OSC. + * @param TKMn: TKM_0 ~ TKM_5 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TKM_RefOSCCmd(TKM_Enum TKMn, ControlStatus NewState) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + TKMx->CR |= (1 << 7); + } + else + { + TKMx->CR &= ~(1 << 7); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the Key OSC. + * @param TKMn: TKM_0 ~ TKM_5 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TKM_KeyOSCCmd(TKM_Enum TKMn, ControlStatus NewState) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + TKMx->CR |= (1 << 6); + } + else + { + TKMx->CR &= ~(1 << 6); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the Multi-frequency. + * @param TKMn: TKM_0 ~ TKM_5 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TKM_MultiFreqCmd(TKM_Enum TKMn, ControlStatus NewState) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + TKMx->CR |= (1 << 5); + } + else + { + TKMx->CR &= ~(1 << 5); + } +} + +/*********************************************************************************************************//** + * @brief Configure the C/F OSC frequency-hopping. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Sel: Specify the C/F OSC frequency-hopping method. + * This paramter can be one of the following values: + * @arg TKM_SOF_CTRL_SW : + * @arg TKM_SOF_CTRL_HW : + * @retval None + ************************************************************************************************************/ +void TKM_SOFCtrlConfig(TKM_Enum TKMn, TKM_SOF_CTRL_Enum Sel) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_SOF_CTRL(Sel)); + + TKMx->CR = (TKMx->CR & ~(1 << 3)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure the Key OSC and the Reference OSC frequency. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Sel: Specify the OSC frequency. + * This paramter can be one of the following values: + * @arg TKM_SOF_FREQ_0 : 1.020MHz. + * @arg TKM_SOF_FREQ_1 : 1.040MHz. + * @arg TKM_SOF_FREQ_2 : 1.059MHz. + * @arg TKM_SOF_FREQ_3 : 1.074MHz. + * @arg TKM_SOF_FREQ_4 : 1.085MHz. + * @arg TKM_SOF_FREQ_5 : 1.099MHz. + * @arg TKM_SOF_FREQ_6 : 1.111MHz. + * @arg TKM_SOF_FREQ_7 : 1.125MHz. + * @retval None + ************************************************************************************************************/ +void TKM_SOFFreqConfig(TKM_Enum TKMn, TKM_SOF_FREQ_Enum Sel) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_SOF_FREQ(Sel)); + + TKMx->CR = (TKMx->CR & ~(7 << 0)) | Sel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified Touch Key. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TKM_KeyCmd(TKM_Enum TKMn, TKM_KEY_Enum Key, ControlStatus NewState) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + TKMx->KCFGR |= (1 << Key); + } + else + { + TKMx->KCFGR &= ~(1 << Key); + } +} + +/*********************************************************************************************************//** + * @brief Configure the Time Slot X key selection (for auto scan mode & Periodic auto scan mode). + * @param TKMn: TKM_0 ~ TKM_5 + * @param Slot: TKM_TIME_SLOT_0 ~ TKM_TIME_SLOT_3 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @retval None + ************************************************************************************************************/ +void TKM_TimeSlotKeyConfig(TKM_Enum TKMn, TKM_TIME_SLOT_Enum Slot, TKM_KEY_Enum Key) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + u32 offset = (16 + (Slot * 2)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_TIME_SLOT(Slot)); + Assert_Param(IS_TKM_KEY(Key)); + + TKMx->KCFGR = (TKMx->KCFGR & ~(3 << offset)) | (Key << offset); +} + +/*********************************************************************************************************//** + * @brief Configure the Key threshold. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @param Sel: Specify the Key threshold. + * This parameter can be one of the following values: + * @arg TKM_KEY_THR_LOWER : + * @arg TKM_KEY_THR_UPPER : + * @retval None + ************************************************************************************************************/ +void TKM_KeyThresholdConfig(TKM_Enum TKMn, TKM_KEY_Enum Key, TKM_KEY_THR_Enum Sel) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + u32 offset = (8 + Key); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + Assert_Param(IS_TKM_KEY_THR(Sel)); + + TKMx->KCFGR = (TKMx->KCFGR & ~(1 << offset)) | (Sel << offset); +} + +/*********************************************************************************************************//** + * @brief Check whether the specified key threshold match flag has been set or not. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus TKM_GetMatchFlagStatus(TKM_Enum TKMn, TKM_KEY_Enum Key) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + + if ((TKMx->SR & (1 << Key)) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified key threshold match flag. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @retval None + ************************************************************************************************************/ +void TKM_ClearMatchFlag(TKM_Enum TKMn, TKM_KEY_Enum Key) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + + TKMx->SR = (1 << Key); +} + +/*********************************************************************************************************//** + * @brief Set the reference OSC capacitor value. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Value: Specify the capacitor value between 0x000 ~ 0x3FF. + * @retval None + ************************************************************************************************************/ +void TKM_SetRefOSCCapacitor(TKM_Enum TKMn, u32 Value) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + + TKMx->ROCPR = Value; +} + +/*********************************************************************************************************//** + * @brief Get the reference OSC capacitor value. + * @param TKMn: TKM_0 ~ TKM_5 + * @retval The capacitor value + ************************************************************************************************************/ +u32 TKM_GetRefOSCCapacitor(TKM_Enum TKMn) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + + return TKMx->ROCPR; +} + +/*********************************************************************************************************//** + * @brief Set the key capacitor value. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @param Value: Specify the capacitor value between 0x000 ~ 0x3FF. + * @retval None + ************************************************************************************************************/ +void TKM_SetKeyCapacitor(TKM_Enum TKMn, TKM_KEY_Enum Key, u32 Value) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + + *(vu32*)((u32)&TKMx->K3CPR + ((3 - Key) * 4)) = Value; +} + +/*********************************************************************************************************//** + * @brief Get the key capacitor value. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @retval The capacitor value + ************************************************************************************************************/ +u32 TKM_GetKeyCapacitor(TKM_Enum TKMn, TKM_KEY_Enum Key) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + + return *(vu32*)((u32)&TKMx->K3CPR + ((3 - Key) * 4)); +} + +/*********************************************************************************************************//** + * @brief Get the 16-bit C/F counter value. + * @param TKMn: TKM_0 ~ TKM_5 + * @retval The counter value + ************************************************************************************************************/ +u32 TKM_Get16BitCFCounterValue(TKM_Enum TKMn) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + + return TKMx->CFCNTR; +} + +/*********************************************************************************************************//** + * @brief Get the key counter value. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @retval None + ************************************************************************************************************/ +u32 TKM_GetKeyCounterValue(TKM_Enum TKMn, TKM_KEY_Enum Key) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + + return *(vu32*)((u32)&TKMx->K3CNTR + ((3 - Key) * 4)); +} + +/*********************************************************************************************************//** + * @brief Set the key threshold value. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @param Value: Specify the key threshold value between 0x0000 ~ 0xFFFF. + * @retval None + ************************************************************************************************************/ +void TKM_SetKeyThreshold(TKM_Enum TKMn, TKM_KEY_Enum Key, u32 Value) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + + *(vu32*)((u32)&TKMx->K3THR + ((3 - Key) * 4)) = Value; +} + +/*********************************************************************************************************//** + * @brief Get the key threshold value. + * @param TKMn: TKM_0 ~ TKM_5 + * @param Key: TKM_KEY_0 ~ TKM_KEY_3 + * @retval The threshold value + ************************************************************************************************************/ +u32 TKEY_GetKeyThreshold(TKM_Enum TKMn, TKM_KEY_Enum Key) +{ + HT_TKM_TypeDef *TKMx = (HT_TKM_TypeDef *)((u32)&HT_TKEY->TKM0 + (TKMn * 0x100)); + + /* Check the parameters */ + Assert_Param(IS_TKM(TKMn)); + Assert_Param(IS_TKM_KEY(Key)); + + return *(vu32*)((u32)&TKMx->K3THR + ((3 - Key) * 4)); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tm.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tm.c new file mode 100644 index 00000000000..1e4a2fe15d8 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_tm.c @@ -0,0 +1,1853 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_tm.c + * @version $Rev:: 7059 $ + * @date $Date:: 2023-07-27 #$ + * @brief This file provides all the TM firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_tm.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup TM TM + * @brief TM driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup TM_Private_Define TM private definitions + * @{ + */ +#define CNTCFR_UEVDIS 0x00000001ul +#define CNTCFR_UGDIS 0x00000002ul +#define CNTCFR_DIR 0x01000000ul +#define CNTCFR_CMSEL_MASK ~0x00030000ul +#define CNTCFR_CKDIV_MASK ~0x00000300ul + +#define MDCFR_SPMSET 0x01000000ul +#define MDCFR_TSE 0x00000001ul +#define MDCFR_SMSEL_MASK ~0x00000700ul +#define MDCFR_MMSEL_MASK ~0x00070000ul + +#if 0 +#define TRCFR_ECME 0x01000000ul +#define TRCFR_ETI_POL 0x00010000ul +#define TRCFR_ETI_PSC_MASK ~0x00003000ul +#define TRCFR_ETIF_MASK ~0x00000F00ul +#define TRCFR_ETI_CONF_MASK ~0x00013F00ul +#endif +#define TRCFR_TRSEL_MASK ~0x0000000Ful + +#define CTR_TME 0x00000001ul +#define CTR_CRBE 0x00000002ul +#define CTR_CHCCDS 0x00010000ul + +#define CH0ICFR_CH0SRC 0x80000000ul +#define CHICFR_CHF_MASK ~0x000000FFul +#define CHICFR_CHCCS_MASK ~0x00030000ul +#define CHICFR_CHPSC_MASK ~0x000C0000ul + +#define CHOCFR_REFCE 0x00000008ul +#define CHOCFR_CHPRE 0x00000010ul +#define CHOCFR_IMAE 0x00000020ul +#define CHOCFR_CHOM_MASK ~0x00000107ul + +#define CHPOLR_CH0P 0x00000001ul +#define CHPOLR_CH1P 0x00000004ul +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void _TM_CHx_Config(HT_TM_TypeDef* TMx, TM_CH_Enum Ch, TM_CHP_Enum Pol, TM_CHCCS_Enum Sel, u8 Filter); + +/* Private macro -------------------------------------------------------------------------------------------*/ +#if (LIBCFG_TM_TIFN_5BIT) +#define FILTER_PROCESS(cap) ((cap->Fsampling << 5) + cap->Event) +#else +#define FILTER_PROCESS(cap) ((cap->Fsampling << 4) + cap->Event) +#endif + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup TM_Exported_Functions TM exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the TMx peripheral registers to their default reset values. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval None + ************************************************************************************************************/ +void TM_DeInit(HT_TM_TypeDef* TMx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + #if (!LIBCFG_NO_GPTM0) + if (TMx == HT_GPTM0) + { + RSTCUReset.Bit.GPTM0 = 1; + } + #endif + #if (LIBCFG_GPTM1) + else if (TMx == HT_GPTM1) + { + RSTCUReset.Bit.GPTM1 = 1; + } + #endif + #if (LIBCFG_MCTM0) + else if (TMx == HT_MCTM0) + { + RSTCUReset.Bit.MCTM0 = 1; + } + #endif + #if (LIBCFG_SCTM0) + if (TMx == HT_SCTM0) + { + RSTCUReset.Bit.SCTM0 = 1; + } + #endif + #if (LIBCFG_SCTM1) + else if (TMx == HT_SCTM1) + { + RSTCUReset.Bit.SCTM1 = 1; + } + #endif + #if (LIBCFG_SCTM2) + else if (TMx == HT_SCTM2) + { + RSTCUReset.Bit.SCTM2 = 1; + } + #endif + #if (LIBCFG_SCTM3) + else if (TMx == HT_SCTM3) + { + RSTCUReset.Bit.SCTM3 = 1; + } + #endif + #if (LIBCFG_PWM0) + if (TMx == HT_PWM0) + { + RSTCUReset.Bit.PWM0 = 1; + } + #endif + #if (LIBCFG_PWM1) + else if (TMx == HT_PWM1) + { + RSTCUReset.Bit.PWM1 = 1; + } + #endif + #if (LIBCFG_PWM2) + else if (TMx == HT_PWM2) + { + RSTCUReset.Bit.PWM1 = 1; + } + #endif + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the TMx counter to reload, prescaler, counter mode and repetition counter. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param TimeBaseInit: Point to a \ref TM_TimeBaseInitTypeDef that contains the configuration information. + * @retval None + ************************************************************************************************************/ +void TM_TimeBaseInit(HT_TM_TypeDef* TMx, TM_TimeBaseInitTypeDef* TimeBaseInit) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CNT_MODE(TimeBaseInit->CounterMode)); + Assert_Param(IS_TM_PSC_RLD(TimeBaseInit->PSCReloadTime)); + + /* Set the counter reload value */ + TMx->CRR = TimeBaseInit->CounterReload; + + /* Set the Prescaler value */ + TMx->PSCR = TimeBaseInit->Prescaler; + + /* Select the Counter Mode */ + TMx->CNTCFR &= CNTCFR_CMSEL_MASK; /* CNTCFR_DIR is read only when the timer configured as */ + TMx->CNTCFR &= ~(u32)CNTCFR_DIR; /* Center-aligned mode. Reset mode first and then reset the */ + /* CNTCFR_DIR bit (separate as two steps). */ + + TMx->CNTCFR |= TimeBaseInit->CounterMode; + + #if (LIBCFG_MCTM0) + if (TMx == HT_MCTM0) + { + /* Set the Repetition value */ + TMx->REPR = TimeBaseInit->RepetitionCounter; + } + #endif + + /* To reload the Prescaler value immediatly or next update event */ + TMx->EVGR = TimeBaseInit->PSCReloadTime; +} + +/*********************************************************************************************************//** + * @brief Initialize the TMx channel N output. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param OutInit: Point to a \ref TM_OutputInitTypeDef structure that contains + the configuration information. + * @retval None + ************************************************************************************************************/ +void TM_OutputInit(HT_TM_TypeDef* TMx, TM_OutputInitTypeDef* OutInit) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + OutInit->Channel; + vu32 *pCcr = (vu32*)&TMx->CH0CCR + OutInit->Channel; + vu32 *pAcr = (vu32*)&TMx->CH0ACR + OutInit->Channel; + u8 bChPos = OutInit->Channel << 1; + u32 wTmpMask; + u32 wTmpReg; + + #if (LIBCFG_MCTM0) + if (TMx == HT_MCTM0) + { + wTmpMask = ~(0x3ul << bChPos); + } + else + #endif + { + wTmpMask = ~(0x1ul << bChPos); + } + +#if (LIBCFG_PWM_8_CHANNEL) + if ((OutInit->Channel > TM_CH_3) && (OutInit->Channel <= TM_CH_7) ) + { + u8 bOffset = OutInit->Channel - 4; + pOcfr = (vu32*)&TMx->CH4OCFR + bOffset; + pCcr = (vu32*)&TMx->CH4CR + bOffset; + } +#endif + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(OutInit->Channel)); + Assert_Param(IS_TM_OM(OutInit->OutputMode)); +#if (LIBCFG_PWM_8_CHANNEL) + if ((OutInit->Channel > TM_CH_3) && (OutInit->Channel <= TM_CH_7) ) + { + Assert_Param(IS_TM_OM_NOASYM(OutInit->OutputMode)); + } +#endif + Assert_Param(IS_TM_CHCTL(OutInit->Control)); + Assert_Param(IS_TM_CHP(OutInit->Polarity)); + #if (LIBCFG_MCTM0) + if (TMx == HT_MCTM0) + { + Assert_Param(IS_TM_CHCTL(OutInit->ControlN)); + Assert_Param(IS_TM_CHP(OutInit->PolarityN)); + Assert_Param(IS_MCTM_OIS(OutInit->IdleState)); + Assert_Param(IS_MCTM_OIS(OutInit->IdleStateN)); + } + #endif + + /* Disable the Channel */ + TMx->CHCTR &= wTmpMask; + + /* Set the Output Compare Polarity */ + wTmpReg = TMx->CHPOLR & wTmpMask; + #if (LIBCFG_MCTM0) + if (TMx == HT_MCTM0) + { + wTmpReg |= (u32)(OutInit->Polarity | (OutInit->PolarityN << 1)) << bChPos; + } + else + #endif + { + wTmpReg |= (u32)(OutInit->Polarity) << bChPos; + } + + TMx->CHPOLR = wTmpReg; + + /* Set the Output Idle State */ + #if (LIBCFG_MCTM0) + if (TMx == HT_MCTM0) + { + wTmpReg = TMx->CHBRKCFR & wTmpMask; + wTmpReg |= (u32)(OutInit->IdleState | (OutInit->IdleStateN << 1)) << bChPos; + TMx->CHBRKCFR = wTmpReg; + } + #endif + + /* Select the Output Compare Mode */ + *pOcfr &= CHOCFR_CHOM_MASK; + *pOcfr |= OutInit->OutputMode; + + /* Set the Capture Compare Register value */ + *pCcr = OutInit->Compare; + + /* Set the Asymmetric Compare Register value */ + *pAcr = OutInit->AsymmetricCompare; + + /* Set the channel state */ + #if (LIBCFG_MCTM0) + if (TMx == HT_MCTM0) + { + TMx->CHCTR |= (u32)(OutInit->Control | (OutInit->ControlN << 1)) << bChPos; + } + else + #endif + { + TMx->CHCTR |= (u32)(OutInit->Control) << bChPos; + } +} + +/*********************************************************************************************************//** + * @brief Initialize input capture of the TMx channel. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param CapInit: Point to a \ref TM_CaptureInitTypeDef structure that contains the configuration + * information. + * @retval None + ************************************************************************************************************/ +void TM_CaptureInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit) +{ + u8 Filter; + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(CapInit->Channel)); + Assert_Param(IS_TM_CHP(CapInit->Polarity)); + Assert_Param(IS_TM_CHCCS(CapInit->Selection)); + Assert_Param(IS_TM_CHPSC(CapInit->Prescaler)); + #if (LIBCFG_TM_652XX_V1) + #else + Assert_Param(IS_TM_FILTER(CapInit->Filter)); + #endif + + #if (LIBCFG_TM_652XX_V1) + Filter = FILTER_PROCESS(CapInit); + #else + Filter = CapInit->Filter; + #endif + _TM_CHx_Config(TMx, CapInit->Channel, CapInit->Polarity, CapInit->Selection, Filter); + + /* Set the Input Capture Prescaler value */ + TM_CHPSCConfig(TMx, CapInit->Channel, CapInit->Prescaler); +} + +/*********************************************************************************************************//** + * @brief Configure the TMx to measure an external PWM signal. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param CapInit: Point to a \ref TM_CaptureInitTypeDef structure that contains the configuration + * information. + * @retval None + * @note The CapInit->Channel can only be TM_CH_0 or TM_CH_1. CH2/CH3 are not supported since it cannot be + * the STI source to reset the counter. + ************************************************************************************************************/ +void TM_PwmInputInit(HT_TM_TypeDef* TMx, TM_CaptureInitTypeDef* CapInit) +{ + u8 Filter; + TM_CHP_Enum OppositePol; + TM_CHCCS_Enum OppositeSel; + TM_CH_Enum OppositeChannel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH_PWMI(CapInit->Channel)); + Assert_Param(IS_TM_CHP(CapInit->Polarity)); + Assert_Param(IS_TM_CHCCS(CapInit->Selection)); + Assert_Param(IS_TM_CHPSC(CapInit->Prescaler)); + #if (LIBCFG_TM_652XX_V1) + #else + Assert_Param(IS_TM_FILTER(CapInit->Filter)); + #endif + + /* Select the Opposite Input Polarity */ + if (CapInit->Polarity == TM_CHP_NONINVERTED) + { + OppositePol = TM_CHP_INVERTED; + } + else + { + OppositePol = TM_CHP_NONINVERTED; + } + + /* Select the Opposite Input */ + if (CapInit->Selection == TM_CHCCS_DIRECT) + { + OppositeSel = TM_CHCCS_INDIRECT; + } + else + { + OppositeSel = TM_CHCCS_DIRECT; + } + + /* Can only be TM_CH_0 or TM_CH_1. CH2/CH3 are not supported since it cannot be the STI source to */ + /* reset the counter */ + if (CapInit->Channel == TM_CH_0) + { + OppositeChannel = TM_CH_1; + } + else + { + OppositeChannel = TM_CH_0; + } + + #if (LIBCFG_TM_652XX_V1) + Filter = FILTER_PROCESS(CapInit); + #else + Filter = CapInit->Filter; + #endif + + /* Capture Channel Configuration */ + _TM_CHx_Config(TMx, CapInit->Channel, CapInit->Polarity, CapInit->Selection, Filter); + + /* Set the Input Capture Prescaler value */ + TM_CHPSCConfig(TMx, CapInit->Channel, CapInit->Prescaler); + + /* Opposite Channel Configuration */ + _TM_CHx_Config(TMx, OppositeChannel, OppositePol, OppositeSel, Filter); + + /* Set the Input Capture Prescaler value */ + TM_CHPSCConfig(TMx, OppositeChannel, CapInit->Prescaler); +} + +/*********************************************************************************************************//** + * @brief Fill each TimeBaseInit member with its default value. + * @param TimeBaseInit: Point to a \ref TM_TimeBaseInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void TM_TimeBaseStructInit(TM_TimeBaseInitTypeDef* TimeBaseInit) +{ + /* Set the default configuration */ + TimeBaseInit->CounterMode = TM_CNT_MODE_UP; + TimeBaseInit->CounterReload = 0xFFFF; + TimeBaseInit->Prescaler = 0x0000; + TimeBaseInit->PSCReloadTime = TM_PSC_RLD_IMMEDIATE; + #if (LIBCFG_MCTM0) + TimeBaseInit->RepetitionCounter = 0; + #endif +} + +/*********************************************************************************************************//** + * @brief Fill each OutInit member with its default value. + * @param OutInit: Point to a \ref TM_OutputInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void TM_OutputStructInit(TM_OutputInitTypeDef* OutInit) +{ + /* Set the default configuration */ + OutInit->Channel = TM_CH_0; + OutInit->OutputMode = TM_OM_MATCH_NOCHANGE; + OutInit->Control = TM_CHCTL_DISABLE; + OutInit->Polarity = TM_CHP_NONINVERTED; + #if (LIBCFG_MCTM0) + OutInit->ControlN = TM_CHCTL_DISABLE; + OutInit->PolarityN = TM_CHP_NONINVERTED; + OutInit->IdleState = MCTM_OIS_LOW; + OutInit->IdleStateN = MCTM_OIS_LOW; + #endif + OutInit->Compare = 0x0000; + OutInit->AsymmetricCompare = 0x0000; +} + +/*********************************************************************************************************//** + * @brief Fill each CapInit member with its default value. + * @param CapInit: Point to a \ref TM_CaptureInitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void TM_CaptureStructInit(TM_CaptureInitTypeDef* CapInit) +{ + /* Set the default configuration */ + CapInit->Channel = TM_CH_0; + CapInit->Polarity = TM_CHP_NONINVERTED; + CapInit->Selection = TM_CHCCS_DIRECT; + CapInit->Prescaler = TM_CHPSC_OFF; + #if (LIBCFG_TM_652XX_V1) + CapInit->Fsampling = TM_CHFDIV_1; + CapInit->Event = TM_CHFEV_OFF; + #else + CapInit->Filter = 0x00; + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable TMx counter. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_Cmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TM Counter */ + TMx->CTR |= CTR_TME; + } + else + { + /* Disable the TM Counter */ + TMx->CTR &= ~CTR_TME; + } +} + +#if (LIBCFG_TM_NO_ITI == 1) +#else +/*********************************************************************************************************//** + * @brief Configure external clock mode of the TMx. Used ITIx as the clock source. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Iti: Trigger source. + * This parameter can be one of the following values: + * @arg TM_TRSEL_ITI0: Internal trigger 0 + * @arg TM_TRSEL_ITI1: Internal trigger 1 + * @arg TM_TRSEL_ITI2: Internal trigger 2 + * @retval None + ************************************************************************************************************/ +void TM_ItiExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Iti) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_ITI(Iti)); + + /* Select the Internal Trigger. Slave mode will be disable in this function */ + TM_StiConfig(TMx, Iti); + + /* Select the STIED as external clock source */ + TMx->MDCFR |= TM_SMSEL_STIED; +} +#endif + +/*********************************************************************************************************//** + * @brief Configure external clock mode of the TMx. Used CHx as the clock source. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the channel source. + * This parameter can be one of the following values: + * @arg TM_TRSEL_TI0BED : TI0 both edge detector + * @arg TM_TRSEL_TI0S0 : Filtered timer input 0 + * @arg TM_TRSEL_TI1S1 : Filtered timer input 1 + * @param Pol: Specify the CHx Polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : active high. + * @arg TM_CHP_INVERTED : active low. + * @param Filter: Specify the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + ************************************************************************************************************/ +void TM_ChExternalClockConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel, TM_CHP_Enum Pol, u8 Filter) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_TRSEL_CH(Sel)); + Assert_Param(IS_TM_CHP(Pol)); + #if (LIBCFG_TM_652XX_V1) + #else + Assert_Param(IS_TM_FILTER(Filter)); + #endif + + /* Configure the Timer Input Clock Source */ + if (Sel == TM_TRSEL_TI1S1) + { + _TM_CHx_Config(TMx, TM_CH_1, Pol, TM_CHCCS_DIRECT, Filter); + } + else + { + _TM_CHx_Config(TMx, TM_CH_0, Pol, TM_CHCCS_DIRECT, Filter); + } + + /* Select the external clock source. Slave mode will be disable in this function */ + TM_StiConfig(TMx, Sel); + + /* Select the STIED as external clock source */ + TMx->MDCFR |= TM_SMSEL_STIED; +} + +#if 0 +/*********************************************************************************************************//** + * @brief Configure external clock mode of the TMx. Used ETI as the clock source. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param Psc: The external Trigger Prescaler. + * It can be one of the following values: + * @arg TM_ETIPSC_OFF : ETI prescaler off + * @arg TM_ETIPSC_2 : ETIP frequency divided by 2 + * @arg TM_ETIPSC_4 : ETIP frequency divided by 4 + * @arg TM_ETIPSC_8 : ETIP frequency divided by 8 + * @param Pol: The external trigger input polarity. + * It can be one of the following values: + * @arg TM_ETIPOL_NONINVERTED : Active high level or rising edge + * @arg TM_ETIPOL_INVERTED : Active low level or falling edge + * @param Filter: Filter for ETI input. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + ************************************************************************************************************/ +void TM_EtiExternalClockConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_ETIPSC(Psc)); + Assert_Param(IS_TM_ETIPOL(Pol)); + Assert_Param(IS_TM_FILTER(Filter)); + + /* Configure the ETI Clock source */ + TM_EtiConfig(TMx, Psc, Pol, Filter); + + /* Enable the external clock mode */ + TMx->TRCFR |= TRCFR_ECME; +} + +/*********************************************************************************************************//** + * @brief Configure external trigger input (ETI) of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param Psc: The external Trigger Prescaler. + * It can be one of the following values: + * @arg TM_ETIPSC_OFF : ETI prescaler off + * @arg TM_ETIPSC_2 : ETIP frequency divided by 2 + * @arg TM_ETIPSC_4 : ETIP frequency divided by 4 + * @arg TM_ETIPSC_8 : ETIP frequency divided by 8 + * @param Pol: The external trigger input polarity. + * It can be one of the following values: + * @arg TM_ETIPOL_NONINVERTED : Active high level or rising edge + * @arg TM_ETIPOL_INVERTED : Active low level or falling edge + * @param Filter: Filter for ETI input. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + ************************************************************************************************************/ +void TM_EtiConfig(HT_TM_TypeDef* TMx, TM_ETIPSC_Enum Psc, TM_ETIPOL_Enum Pol, u8 Filter) +{ + u32 wTrcfr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_ETIPSC(Psc)); + Assert_Param(IS_TM_ETIPOL(Pol)); + Assert_Param(IS_TM_FILTER(Filter)); + + /* Get TRCFR value with cleared ETI configuration bits */ + wTrcfr = TMx->TRCFR & TRCFR_ETI_CONF_MASK; + + /* Set the prescaler, filter and polarity for ETI input */ + wTrcfr |= (u32)Psc | Pol | ((u32)Filter << 8); + + /* Write to TMx TRCFR */ + TMx->TRCFR = wTrcfr; +} +#endif + +/*********************************************************************************************************//** + * @brief Configure prescaler of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Psc: Specify the prescaler value. + * @param PscReloadTime: Specify the TM prescaler reload time. + * This parameter can be one of the following values: + * @arg TM_PSC_RLD_UPDATE : The prescaler is loaded at the next update event. + * @arg TM_PSC_RLD_IMMEDIATE : The prescaler is loaded immediatly. + * @retval None + ************************************************************************************************************/ +void TM_PrescalerConfig(HT_TM_TypeDef* TMx, u16 Psc, TM_PSC_RLD_Enum PscReloadTime) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_PSC_RLD(PscReloadTime)); + + /* Set the prescaler value */ + TMx->PSCR = Psc; + + /* Set the UEVG bit or not */ + TMx->EVGR = PscReloadTime; +} + +/*********************************************************************************************************//** + * @brief Configure counter mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Mod: Specify the counter mode to be used. + * This parameter can be one of the following values: + * @arg TM_CNT_MODE_UP : TM up counting mode. + * @arg TM_CNT_MODE_DOWN : TM down counting mode. + * @arg TM_CNT_MODE_CA1 : TM center aligned mode 1. + * @arg TM_CNT_MODE_CA2 : TM center aligned mode 2. + * @arg TM_CNT_MODE_CA3 : TM center aligned mode 3. + * @retval None + ************************************************************************************************************/ +void TM_CounterModeConfig(HT_TM_TypeDef* TMx, TM_CNT_MODE_Enum Mod) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CNT_MODE(Mod)); + + /* Reset the CMSEL and DIR Bits */ + TMx->CNTCFR &= CNTCFR_CMSEL_MASK; /* CNTCFR_DIR is read only when the timer configured as */ + TMx->CNTCFR &= ~(u32)CNTCFR_DIR; /* Center-aligned mode. Reset mode first and then reset the */ + /* CNTCFR_DIR bit (separate as two steps). */ + + /* Set the Counter Mode */ + TMx->CNTCFR |= Mod; +} + +/*********************************************************************************************************//** + * @brief Select the STI source. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the STI source. + * This parameter can be one of the following: + * @arg TM_TRSEL_ITI0 : Internal trigger 0. + * @arg TM_TRSEL_ITI1 : Internal trigger 1. + * @arg TM_TRSEL_ITI2 : Internal trigger 2. + * @arg TM_TRSEL_TI0BED : TI0 both edge detector. + * @arg TM_TRSEL_TI0S0 : Filtered channel 0 input. + * @arg TM_TRSEL_TI1S1 : Filtered channel 1 input. + * @arg TM_TRSEL_ETIF : External trigger input. + * @arg TM_TRSEL_UEVG : Trigger by setting UEVG bit. + * @retval None + ************************************************************************************************************/ +void TM_StiConfig(HT_TM_TypeDef* TMx, TM_TRSEL_Enum Sel) +{ + u32 wTrcfr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_TRSEL(Sel)); + + /* Disable slave mode */ + TMx->MDCFR &= MDCFR_SMSEL_MASK; + + /* Get the TRCFR value with cleared TRSEL */ + wTrcfr = TMx->TRCFR & TRCFR_TRSEL_MASK; + + /* Set the STI source */ + TMx->TRCFR |= wTrcfr | Sel; +} + +/*********************************************************************************************************//** + * @brief Configure encoder interface of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param DecoderMod: Specify the TMx decoder mode. + * This parameter can be one of the following values: + * @arg TM_SMSEL_DECODER1 : Counter counts on CH0 edge depending on CH1 level. + * @arg TM_SMSEL_DECODER2 : Counter counts on CH1 edge depending on CH0 level. + * @arg TM_SMSEL_DECODER3 : Counter counts on both CH0 and CH1 edges depending on + * the level of the other input. + * @param CH0P: Specify the CH0 polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : Active high level or rising edge + * @arg TM_CHP_INVERTED : Active low level or falling edge + * @param CH1P: Specify the CH1 polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : Active high level or rising edge + * @arg TM_CHP_INVERTED : Active low level or falling edge + * @retval None + ************************************************************************************************************/ +void TM_DecoderConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum DecoderMod, TM_CHP_Enum CH0P, TM_CHP_Enum CH1P) +{ + u32 wMdcfr, wCh0Icfr, wCh1Icfr, wChpolr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_SMSEL_DECODER(DecoderMod)); + Assert_Param(IS_TM_CHP(CH0P)); + Assert_Param(IS_TM_CHP(CH1P)); + + /* Get the TMx MDCFR register value */ + wMdcfr = TMx->MDCFR; + + /* Get the TMx CH0ICFR & CH1ICFR register value */ + wCh0Icfr = TMx->CH0ICFR; + wCh1Icfr = TMx->CH1ICFR; + + /* Get the TMx CHPOLR register value */ + wChpolr = TMx->CHPOLR; + + /* Set the decoder mode */ + wMdcfr &= MDCFR_SMSEL_MASK; + wMdcfr |= DecoderMod; + + /* Select the channel 0 and the channel 1 as input and clear CH0SRC */ + wCh0Icfr &= CHICFR_CHCCS_MASK & (~CH0ICFR_CH0SRC); + wCh1Icfr &= CHICFR_CHCCS_MASK; + wCh0Icfr |= TM_CHCCS_DIRECT; + wCh1Icfr |= TM_CHCCS_DIRECT; + + /* Set the CH0 and the CH1 polarities */ + wChpolr &= ~(CHPOLR_CH0P | CHPOLR_CH1P); + wChpolr |= (CH0P | (CH1P << 2)); + + /* Write to TMx MDCFR */ + TMx->MDCFR = wMdcfr; + + /* Write to TMx CH0ICFR & CH1ICFR */ + TMx->CH0ICFR = wCh0Icfr; + TMx->CH1ICFR = wCh1Icfr; + + /* Write to TMx CHPOLR */ + TMx->CHPOLR = wChpolr; +} + +/*********************************************************************************************************//** + * @brief Force the TMx CHnOREF waveform to active or inactive level. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @arg TM_CH_4 : TM channel 4 + * @arg TM_CH_5 : TM channel 5 + * @arg TM_CH_6 : TM channel 6 + * @arg TM_CH_7 : TM channel 7 + * @param ForcedAction: Specify the forced action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TM_OM_FORCED_ACTIVE : Forced active level on CH0OREF + * @arg TM_OM_FORCED_INACTIVE : Forced inactive level on CH0OREF. + * @retval None + ************************************************************************************************************/ +void TM_ForcedOREF(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, TM_OM_Enum ForcedAction) +{ + vu32* pCHnOCFR = ((vu32*)&TMx->CH0OCFR) + (TM_CH_n * 1); +#if (LIBCFG_PWM_8_CHANNEL) + if ((TM_CH_n > TM_CH_3) && (TM_CH_n <= TM_CH_7) ) + { + pCHnOCFR = ((vu32*)&TMx->CH4OCFR) + ((TM_CH_n -4) * 1); + } +#endif + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + Assert_Param(IS_TM_OM_FORCED(ForcedAction)); + + /* Configure The forced output mode */ + *pCHnOCFR = (*pCHnOCFR & CHOCFR_CHOM_MASK) | ForcedAction; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the TMx CRR preload function. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_CRRPreloadCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Set the CRR preload control bit */ + TMx->CTR |= CTR_CRBE; + } + else + { + /* Reset the CRR preload control bit */ + TMx->CTR &= ~CTR_CRBE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the TMx CHxCCR preload function. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @arg TM_CH_4 : TM channel 4 + * @arg TM_CH_5 : TM channel 5 + * @arg TM_CH_6 : TM channel 6 + * @arg TM_CH_7 : TM channel 7 + * @param NewState This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_CHCCRPreloadConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); +#if (LIBCFG_PWM_8_CHANNEL) + if ((Channel > TM_CH_3) && (Channel <= TM_CH_7)) + { + u8 bOffset = Channel - 4; + pOcfr = (vu32*)&TMx->CH4OCFR + bOffset; + } +#endif + /* Enable or disable the channel N CCR preload feature */ + if (NewState != DISABLE) + { + *pOcfr |= CHOCFR_CHPRE; + } + else + { + *pOcfr &= ~CHOCFR_CHPRE; + } +} + +/*********************************************************************************************************//** + * @brief Clear or Safeguard the CHxOREF signal when ETI is active. + * @param TMx: where TMx is the selected TM from the TM peripheral. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param NewState This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_ClearOREFConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Enable or Disable the channel N clear Oref at ETI active function */ + if (NewState != DISABLE) + { + *pOcfr |= CHOCFR_REFCE; + } + else + { + *pOcfr &= ~CHOCFR_REFCE; + } +} + +/*********************************************************************************************************//** + * @brief Configure polarity of the TMx channel N. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @arg TM_CH_4 : TM channel 4 + * @arg TM_CH_5 : TM channel 5 + * @arg TM_CH_6 : TM channel 6 + * @arg TM_CH_7 : TM channel 7 + * @param Pol: Specify the polarity of channel N. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : active high + * @arg TM_CHP_INVERTED : active low + * @retval None + ************************************************************************************************************/ +void TM_ChPolarityConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHP_Enum Pol) +{ + u32 wChpolr; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_CHP(Pol)); + + /* Set or reset the CHx polarity */ + wChpolr = TMx->CHPOLR & (~(u32)(0x1 << (Channel << 1))); + TMx->CHPOLR = wChpolr | (Pol << (Channel << 1)); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the single pulse immediate active function. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @arg TM_CH_4 : TM channel 4 + * @arg TM_CH_5 : TM channel 5 + * @arg TM_CH_6 : TM channel 6 + * @arg TM_CH_7 : TM channel 7 + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + * @note Must configure output mode to PWM1 or PWM2 before invoke this function. + ************************************************************************************************************/ +void TM_ImmActiveConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, ControlStatus NewState) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + +#if (LIBCFG_PWM_8_CHANNEL) + if ((Channel > TM_CH_3) && (Channel <= TM_CH_7) ) + { + u8 bOffset = Channel - 4; + pOcfr = (vu32*)&TMx->CH4OCFR + bOffset; + } +#endif + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Enable or disable the channel N clear CHxOREF at ETI active function */ + if (NewState != DISABLE) + { + *pOcfr |= CHOCFR_IMAE; + } + else + { + *pOcfr &= ~CHOCFR_IMAE; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the TMx channel N. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @arg TM_CH_4 : TM channel 4 + * @arg TM_CH_5 : TM channel 5 + * @arg TM_CH_6 : TM channel 6 + * @arg TM_CH_7 : TM channel 7 + * @param Control: This parameter can be TM_CHCTL_ENABLE or TM_CHCTL_DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_ChannelConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_CHCTL(Control)); + + /* Reset the CHxE Bit */ + TMx->CHCTR &= ~(u32)(0x1 << (Channel << 1)); + + /* Set or reset the CHxE Bit */ + TMx->CHCTR |= (u32)Control << (Channel << 1); +} + +/*********************************************************************************************************//** + * @brief Configure output mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @arg TM_CH_4 : TM channel 4 + * @arg TM_CH_5 : TM channel 5 + * @arg TM_CH_6 : TM channel 6 + * @arg TM_CH_7 : TM channel 7 + * @param Mod: Specify the TM output mode. + * This parameter can be one of the following values: + * @arg TM_OM_MATCH_NOCHANGE : Output dont change on match + * @arg TM_OM_MATCH_INACTIVE : Output inactive on compare match + * @arg TM_OM_MATCH_ACTIVE : Output active on compare match + * @arg TM_OM_MATCH_TOGGLE : Output toggle on compare match + * @arg TM_OM_FORCED_INACTIVE : Output forced inactive + * @arg TM_OM_FORCED_ACTIVE : Output forced active + * @arg TM_OM_PWM1 : PWM1 mode + * @arg TM_OM_PWM2 : PWM2 mode + * @arg TM_OM_ASYMMETRIC_PWM1 : Asymmetric PWM1 mode + * @arg TM_OM_ASYMMETRIC_PWM2 : Asymmetric PWM2 mode + * @retval None + * @note This function disables the selected channel before changing the output mode. + ************************************************************************************************************/ +void TM_OutputModeConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_OM_Enum Mod) +{ + vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; + +#if (LIBCFG_PWM_8_CHANNEL) + if ((Channel > TM_CH_3) && (Channel <= TM_CH_7) ) + { + u8 bOffset = Channel - 4; + pOcfr = (vu32*)&TMx->CH4OCFR + bOffset; + } +#endif + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_OM(Mod)); +#if (LIBCFG_PWM_8_CHANNEL) + if ((Channel > TM_CH_3) && (Channel <= TM_CH_7) ) + { + Assert_Param(IS_TM_OM_NOASYM(Mod)); + } +#endif + + /* Disable the channel: Reset the CHxE Bit */ + TMx->CHCTR &= ~(u32)(0x1 << (Channel << 1)); + + /* Selects the TM output mode */ + *pOcfr = (*pOcfr & CHOCFR_CHOM_MASK) | Mod; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable update event of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE (default) or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_UpdateCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == DISABLE) + { + /* Set the update disable bit */ + TMx->CNTCFR |= CNTCFR_UEVDIS; + } + else + { + /* Reset the update disable bit */ + TMx->CNTCFR &= ~CNTCFR_UEVDIS; + } +} + +/*********************************************************************************************************//** + * @brief Configure UEVG interrupt function of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be one of the following value: + * @arg ENABLE : Default value. Any of the following events will generate an update event interrupt: + * - Counter overflow/underflow + * - Setting the UEVG bit + * - Update generation through the slave restart mode + * @arg DISABLE : Only counter overflow/underflow generations an update event interrupt. + * @retval None + ************************************************************************************************************/ +void TM_UEVG_IntConfig(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState == DISABLE) + { + /* Set the UEVG interrupt disable bit */ + TMx->CNTCFR |= CNTCFR_UGDIS; + } + else + { + /* Reset the UEVG interrupt disable bit */ + TMx->CNTCFR &= ~CNTCFR_UGDIS; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable hall sensor interface of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_HallInterfaceCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Set the CH0SRC Bit */ + TMx->CH0ICFR |= CH0ICFR_CH0SRC; + } + else + { + /* Reset the CH0SRC Bit */ + TMx->CH0ICFR &= ~CH0ICFR_CH0SRC; + } +} + +/*********************************************************************************************************//** + * @brief Select single pulse mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_SinglePulseModeCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + TMx->MDCFR |= MDCFR_SPMSET; + } + else + { + TMx->MDCFR &= ~MDCFR_SPMSET; + } +} + +/*********************************************************************************************************//** + * @brief Select master trigger output source of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the master trigger output source. + * This parameter can be as follow: + * @arg TM_MMSEL_RESET : Send trigger signal when S/W setting UEVG or slave restart + * @arg TM_MMSEL_ENABLE : The counter enable signal is used as trigger output. + * @arg TM_MMSEL_UPDATE : The update event is used as trigger output. + * @arg TM_MMSEL_CH0CC : Channel 0 capture or compare match occurred as trigger output. + * @arg TM_MMSEL_CH0OREF : The CH0OREF signal is used as trigger output. + * @arg TM_MMSEL_CH1OREF : The CH1OREF signal is used as trigger output. + * @arg TM_MMSEL_CH2OREF : The CH2OREF signal is used as trigger output. + * @arg TM_MMSEL_CH3OREF : The CH3OREF signal is used as trigger output. + * @arg TM_MMSEL_CH4OREF : The CH4OREF signal is used as trigger output. + * @arg TM_MMSEL_CH5OREF : The CH5OREF signal is used as trigger output. + * @arg TM_MMSEL_CH6OREF : The CH6OREF signal is used as trigger output. + * @arg TM_MMSEL_CH7OREF : The CH7OREF signal is used as trigger output. + * @retval None + ************************************************************************************************************/ +void TM_MMSELConfig(HT_TM_TypeDef* TMx, TM_MMSEL_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_MMSEL(Sel)); + + /* Select the MTO source */ + TMx->MDCFR = (TMx->MDCFR & MDCFR_MMSEL_MASK) | Sel; +} + +/*********************************************************************************************************//** + * @brief Select slave mode of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Sel: Specify the timer slave mode. + * This parameter can be one of the following values: + * @arg TM_SMSEL_RESTART : Slave restart counter mode. + * @arg TM_SMSEL_PAUSE : Slave pause counter mode. + * @arg TM_SMSEL_TRIGGER : Slave trigger counter start mode. + * @arg TM_SMSEL_STIED : Used rising edge of STI as prescaler clock source. + * @retval None + ************************************************************************************************************/ +void TM_SlaveModeConfig(HT_TM_TypeDef* TMx, TM_SMSEL_Enum Sel) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_SLAVE_MODE(Sel)); + + /* Select the slave mode */ + TMx->MDCFR = (TMx->MDCFR & MDCFR_SMSEL_MASK) | Sel; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the master & slave TMx synchronous function. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_TimSyncCmd(HT_TM_TypeDef* TMx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Set the TSE Bit */ + TMx->MDCFR |= MDCFR_TSE; + } + else + { + /* Reset the TSE Bit */ + TMx->MDCFR &= ~MDCFR_TSE; + } +} + +/*********************************************************************************************************//** + * @brief Set counter register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Counter: Specify the counter register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetCounter(HT_TM_TypeDef* TMx, u16 Counter) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Set the Counter Register value */ + TMx->CNTR = Counter; +} + +/*********************************************************************************************************//** + * @brief Set counter reload register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Reload: Specify the counter reload register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetCounterReload(HT_TM_TypeDef* TMx, u16 Reload) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Set the counter reload register value */ + TMx->CRR = Reload; +} + +/*********************************************************************************************************//** + * @brief Set channel n capture/compare register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @arg TM_CH_4 : TM channel 4 + * @arg TM_CH_5 : TM channel 5 + * @arg TM_CH_6 : TM channel 6 + * @arg TM_CH_7 : TM channel 7 + * @param Cmp: Specify the CH0CCR register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) +{ + vu32* pCHnCCR = ((vu32*)&TMx->CH0CCR) + (TM_CH_n * 1); + #if (LIBCFG_PWM_8_CHANNEL) + if ((TM_CH_n > TM_CH_3) && (TM_CH_n <= TM_CH_7) ) + { + pCHnCCR = ((vu32*)&TMx->CH4CR) + ((TM_CH_n - 4) * 1); + } + #endif + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + + /* Set the CHnCCR register new value */ + *pCHnCCR = Cmp; +} + +/*********************************************************************************************************//** + * @brief Set channel n asymmetric compare register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Cmp: Specify the CH0ACR register new value. + * @retval None + ************************************************************************************************************/ +void TM_SetAsymmetricCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n, u16 Cmp) +{ + vu32* pCHnACR = ((vu32*)&TMx->CH0ACR) + (TM_CH_n * 1); + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + + /* Set the CHnACR register new value */ + *pCHnACR = Cmp; +} + +/*********************************************************************************************************//** + * @brief Configure input capture prescaler. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Channel: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Psc: Specify the input capture prescaler new value. + * This parameter can be one of the following values: + * @arg TM_CHPSC_OFF : No prescaler + * @arg TM_CHPSC_2 : Capture is done once every 2 events + * @arg TM_CHPSC_4 : Capture is done once every 4 events + * @arg TM_CHPSC_8 : Capture is done once every 8 events + * @retval None + ************************************************************************************************************/ +void TM_CHPSCConfig(HT_TM_TypeDef* TMx, TM_CH_Enum Channel, TM_CHPSC_Enum Psc) +{ + vu32 *pIcfr = (vu32*)&TMx->CH0ICFR + Channel; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(Channel)); + Assert_Param(IS_TM_CHPSC(Psc)); + + /* Reset the CHxPSC bits */ + *pIcfr &= CHICFR_CHPSC_MASK; + + /* Set the capture input prescaler value */ + *pIcfr |= Psc; +} + +/*********************************************************************************************************//** + * @brief Set clock division value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Div: Specify the clock division value. + * This parameter can be one of the following value: + * @arg TM_CKDIV_OFF : fDTS = fCLKIN + * @arg TM_CKDIV_2 : fDTS = fCLKIN / 2 + * @arg TM_CKDIV_4 : fDTS = fCLKIN / 4 + * @arg TM_CKDIV_8 : fDTS = fCLKIN / 8 + * @retval None + ************************************************************************************************************/ +void TM_CKDIVConfig(HT_TM_TypeDef* TMx, TM_CKDIV_Enum Div) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CKDIV(Div)); + + /* Reset the CKDIV Bits */ + TMx->CNTCFR &= CNTCFR_CKDIV_MASK; + + /* Set the CKDIV value */ + TMx->CNTCFR |= Div; +} + +/*********************************************************************************************************//** + * @brief Get channel n capture/compare register value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_CH_n: Specify the TM channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @retval Value of CH0CCR register + ************************************************************************************************************/ +u32 TM_GetCaptureCompare(HT_TM_TypeDef* TMx, TM_CH_Enum TM_CH_n) +{ + vu32* pCHnCCR = ((vu32*)&TMx->CH0CCR) + (TM_CH_n * 1); + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CH(TM_CH_n)); + + #if (LIBCFG_PWM_8_CHANNEL) + if ((TM_CH_n > TM_CH_3) && (TM_CH_n <= TM_CH_7)) + { + pCHnCCR = ((vu32*)&TMx->CH4CR) + ((TM_CH_n - 4) * 1); + } + #endif + + /* Get the CHnCCR register value */ + return (*pCHnCCR); +} + +/*********************************************************************************************************//** + * @brief Get counter value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval Value of Counter register + ************************************************************************************************************/ +u32 TM_GetCounter(HT_TM_TypeDef* TMx) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Get the Counter Register value */ + return TMx->CNTR; +} + +/*********************************************************************************************************//** + * @brief Get prescaler value of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval Value of Prescaler register + ************************************************************************************************************/ +u32 TM_GetPrescaler(HT_TM_TypeDef* TMx) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Get the Prescaler Register value */ + return TMx->PSCR; +} + +/*********************************************************************************************************//** + * @brief Generate TMx events. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_EVENT: Stores the event source. + * This parameter can be any combination of following: + * @arg TM_EVENT_CH0CC : Timer Capture/compare 0 event + * @arg TM_EVENT_CH1CC : Timer Capture/compare 1 event + * @arg TM_EVENT_CH2CC : Timer Capture/compare 2 event + * @arg TM_EVENT_CH3CC : Timer Capture/compare 3 event + * @arg TM_EVENT_CH4CC : Timer Compare 4 event + * @arg TM_EVENT_CH5CC : Timer Compare 5 event + * @arg TM_EVENT_CH6CC : Timer Compare 6 event + * @arg TM_EVENT_CH7CC : Timer Compare 7 event + * @arg TM_EVENT_UEV : Timer update event + * @arg TM_EVENT_UEV2 : Timer update event 2 + * @arg TM_EVENT_TEV : Timer trigger event + * @arg TM_EVENT_BRKEV : Timer break event + * @retval None + ************************************************************************************************************/ +void TM_GenerateEvent(HT_TM_TypeDef* TMx, u32 TM_EVENT) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_EVENT(TM_EVENT)); + + /* Set the event sources */ + TMx->EVGR = TM_EVENT; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified TMx flag has been set. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_FLAG: Specify the flag to be checked. + * This parameter can be one of the following values: + * @arg TM_FLAG_CH0CC : TM Capture/compare 0 flag + * @arg TM_FLAG_CH1CC : TM Capture/compare 1 flag + * @arg TM_FLAG_CH2CC : TM Capture/compare 2 flag + * @arg TM_FLAG_CH3CC : TM Capture/compare 3 flag + * @arg TM_FLAG_CH4CC : TM Compare 4 flag + * @arg TM_FLAG_CH5CC : TM Compare 5 flag + * @arg TM_FLAG_CH6CC : TM Compare 6 flag + * @arg TM_FLAG_CH7CC : TM Compare 7 flag + * @arg TM_FLAG_CH0OC : TM channel 0 overcapture flag + * @arg TM_FLAG_CH1OC : TM channel 1 overcapture flag + * @arg TM_FLAG_CH2OC : TM channel 2 overcapture flag + * @arg TM_FLAG_CH3OC : TM channel 3 overcapture flag + * @arg TM_FLAG_UEV : TM update flag + * @arg TM_FLAG_UEV2 : TM update 2 flag + * @arg TM_FLAG_TEV : TM trigger flag + * @arg TM_FLAG_BRK0 : TM break 0 flag + * @arg TM_FLAG_BRK1 : TM break 1 flag + * @retval The new state of TM_FLAG (SET or RESET). + ************************************************************************************************************/ +FlagStatus TM_GetFlagStatus(HT_TM_TypeDef* TMx, u32 TM_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_FLAG(TM_FLAG)); + + if ((TMx->INTSR & TM_FLAG) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear flags of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_FLAG: Specify the flag to be cleared. + * This parameter can be any combination of the following values: + * @arg TM_FLAG_CH0CC : TM Capture/compare 0 flag + * @arg TM_FLAG_CH1CC : TM Capture/compare 1 flag + * @arg TM_FLAG_CH2CC : TM Capture/compare 2 flag + * @arg TM_FLAG_CH3CC : TM Capture/compare 3 flag + * @arg TM_FLAG_CH4CC : TM Compare 4 flag + * @arg TM_FLAG_CH5CC : TM Compare 5 flag + * @arg TM_FLAG_CH6CC : TM Compare 6 flag + * @arg TM_FLAG_CH7CC : TM Compare 7 flag + * @arg TM_FLAG_CH0OC : TM channel 0 overcapture flag + * @arg TM_FLAG_CH1OC : TM channel 1 overcapture flag + * @arg TM_FLAG_CH2OC : TM channel 2 overcapture flag + * @arg TM_FLAG_CH3OC : TM channel 3 overcapture flag + * @arg TM_FLAG_UEV : TM update flag + * @arg TM_FLAG_UEV2 : TM update 2 flag + * @arg TM_FLAG_TEV : TM trigger flag + * @arg TM_FLAG_BRK0 : TM break 0 flag + * @arg TM_FLAG_BRK1 : TM break 1 flag + * @retval None + ************************************************************************************************************/ +void TM_ClearFlag(HT_TM_TypeDef* TMx, u32 TM_FLAG) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_FLAG_CLR(TM_FLAG)); + + /* Clear the flags */ + TMx->INTSR = ~TM_FLAG; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified interrupts of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_INT: Specify the TM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TM_INT_CH0CC : TM Capture/compare 0 interrupt + * @arg TM_INT_CH1CC : TM Capture/compare 1 interrupt + * @arg TM_INT_CH2CC : TM Capture/compare 2 interrupt + * @arg TM_INT_CH3CC : TM Capture/compare 3 interrupt + * @arg TM_INT_CH4CC : TM Compare 4 interrupt + * @arg TM_INT_CH5CC : TM Compare 5 interrupt + * @arg TM_INT_CH6CC : TM Compare 6 interrupt + * @arg TM_INT_CH7CC : TM Compare 7 interrupt + * @arg TM_INT_UEV : TM update interrupt + * @arg TM_INT_UEV2 : TM update 2 interrupt + * @arg TM_INT_TEV : TM trigger interrupt + * @arg TM_INT_BRKEV : TM break interrupt + * @arg MCTM_INT_CH0CD : MCTM Channel 0 Count-Down compare interrupt + * @arg MCTM_INT_CH1CD : MCTM Channel 1 Count-Down compare interrupt + * @arg MCTM_INT_CH2CD : MCTM Channel 2 Count-Down compare interrupt + * @arg MCTM_INT_CH3CD : MCTM Channel 3 Count-Down compare interrupt + * @arg TM_INT_VC : TM Velocity clock trigger interrupt + * @arg TM_INT_QC : TM Quadrature decoder CLKPULSE interrupt + * @arg TM_INT_PE : TM Phase error interrupt + * @arg TM_INT_DC : TM Counter direction change interrupt + * @arg MCTM_INT_OVER : MCTM CNTR Overflow interrupt + * @arg MCTM_INT_UNDER : MCTM CNTR Underflow interrupt + * @arg MCTM_INT_RECCDIF : MCTM CCIF or CIDF interrupt flag control by REPR + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_IntConfig(HT_TM_TypeDef* TMx, u32 TM_INT, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_INT(TM_INT)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the interrupt sources */ + TMx->DICTR |= TM_INT; + } + else + { + /* Disable the interrupt sources */ + TMx->DICTR &= ~TM_INT; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the TMx interrupt has occurred. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_INT: Specify the TM interrupt source to be checked. + * This parameter can be one of the following values: + * @arg TM_INT_CH0CC : TM Capture/compare 0 interrupt + * @arg TM_INT_CH1CC : TM Capture/compare 1 interrupt + * @arg TM_INT_CH2CC : TM Capture/compare 2 interrupt + * @arg TM_INT_CH3CC : TM Capture/compare 3 interrupt + * @arg TM_INT_CH4CC : TM Compare 4 interrupt + * @arg TM_INT_CH5CC : TM Compare 5 interrupt + * @arg TM_INT_CH6CC : TM Compare 6 interrupt + * @arg TM_INT_CH7CC : TM Compare 7 interrupt + * @arg TM_INT_UEV : TM update interrupt + * @arg TM_INT_UEV2 : TM update 2 interrupt + * @arg TM_INT_TEV : TM trigger interrupt + * @arg TM_INT_BRKEV : TM break interrupt + * @retval The new state of the TM_INT(SET or RESET) + ************************************************************************************************************/ +FlagStatus TM_GetIntStatus(HT_TM_TypeDef* TMx, u32 TM_INT) +{ + u32 itstatus, itenable; + + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_GET_INT(TM_INT)); + + itstatus = TMx->INTSR & TM_INT; + itenable = TMx->DICTR & TM_INT; + + if ((itstatus != 0) && (itenable != 0)) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Clear interrupt pending bits of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_INT: Specify the TM interrupt to be cleared. + * This parameter can be any combination of the following values: + * @arg TM_INT_CH0CC : TM Capture/compare 0 interrupt + * @arg TM_INT_CH1CC : TM Capture/compare 1 interrupt + * @arg TM_INT_CH2CC : TM Capture/compare 2 interrupt + * @arg TM_INT_CH3CC : TM Capture/compare 3 interrupt + * @arg TM_INT_CH4CC : TM Compare 4 interrupt + * @arg TM_INT_CH5CC : TM Compare 5 interrupt + * @arg TM_INT_CH6CC : TM Compare 6 interrupt + * @arg TM_INT_CH7CC : TM Compare 7 interrupt + * @arg TM_INT_UEV : TM update interrupt + * @arg TM_INT_UEV2 : TM update 2 interrupt + * @arg TM_INT_TEV : TM trigger interrupt + * @arg TM_INT_BRKEV : TM break interrupt + * @retval None + ************************************************************************************************************/ +void TM_ClearIntPendingBit(HT_TM_TypeDef* TMx, u32 TM_INT) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_INT(TM_INT)); + + /* Clear the interrupt pending Bit */ + TMx->INTSR = ~TM_INT; + + /*--------------------------------------------------------------------------------------------------------*/ + /* DSB instruction is added in this function to ensure the write operation which is for clearing interrupt*/ + /* flag is actually completed before exiting ISR. It prevents the NVIC from detecting the interrupt again */ + /* since the write register operation may be pended in the internal write buffer of Cortex-Mx when program*/ + /* has exited interrupt routine. This DSB instruction may be masked if this function is called in the */ + /* beginning of ISR and there are still some instructions before exiting ISR. */ + /*--------------------------------------------------------------------------------------------------------*/ + __DSB(); +} + +/*********************************************************************************************************//** + * @brief Disable slave mode to clock the prescaler directly with the internal clock. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @retval None + ************************************************************************************************************/ +void TM_InternalClockConfig(HT_TM_TypeDef* TMx) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TMx->MDCFR &= MDCFR_SMSEL_MASK; +} + +#if (LIBCFG_PDMA) +/*********************************************************************************************************//** + * @brief Select Channel Capture/Compare PDMA event of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Selection: This parameter can be TM_CHCCDS_CHCCEV or TM_CHCCDS_UEV. + * @retval None + ************************************************************************************************************/ +void TM_CHCCDSConfig(HT_TM_TypeDef* TMx, TM_CHCCDS_Enum Selection) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_CHCCDS(Selection)); + + if (Selection != TM_CHCCDS_CHCCEV) + { + TMx->CTR |= CTR_CHCCDS; + } + else + { + TMx->CTR &= ~CTR_CHCCDS; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified PDMA requests of the TMx. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param TM_PDMA: Specify the TM PDMA requests to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TM_PDMA_CH0CC : TM Capture/compare 0 PDMA request + * @arg TM_PDMA_CH1CC : TM Capture/compare 1 PDMA request + * @arg TM_PDMA_CH2CC : TM Capture/compare 2 PDMA request + * @arg TM_PDMA_CH3CC : TM Capture/compare 3 PDMA request + * @arg TM_PDMA_UEV : TM update PDMA request + * @arg TM_PDMA_UEV2 : TM update 2 PDMA request + * @arg TM_PDMA_TEV : TM trigger PDMA request + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void TM_PDMAConfig(HT_TM_TypeDef* TMx, u32 TM_PDMA, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_TM(TMx)); + Assert_Param(IS_TM_PDMA(TM_PDMA)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PDMA request */ + TMx->DICTR |= TM_PDMA; + } + else + { + /* Disable the PDMA request */ + TMx->DICTR &= ~TM_PDMA; + } +} +#endif +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup TM_Private_Functions TM private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Configure the CHx as input. + * @param TMx: where TMx is the selected TM from the TM peripherals. + * @param Ch: Specify the TM Channel. + * This parameter can be one of the following values: + * @arg TM_CH_0 : TM channel 0 + * @arg TM_CH_1 : TM channel 1 + * @arg TM_CH_2 : TM channel 2 + * @arg TM_CH_3 : TM channel 3 + * @param Pol: The input polarity. + * This parameter can be one of the following values: + * @arg TM_CHP_NONINVERTED : Active high level or rising edge + * @arg TM_CHP_INVERTED : Active low level or falling edge + * @param Sel: Specify the input to be used. + * This parameter can be one of the following values: + * @arg TM_CHCCS_DIRECT : TM CHxI is mapped on CHx. + * @arg TM_CHCCS_INDIRECT : TM CH1I is mapped on CH0 (or CH0I->CH1 or CH2I->CH3 or CH3I->CH2). + * @arg TM_CHCCS_TRCED : TM CHx is mapped on TRC. + * @param Filter: Specify the input capture filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + ************************************************************************************************************/ +static void _TM_CHx_Config(HT_TM_TypeDef* TMx, TM_CH_Enum Ch, TM_CHP_Enum Pol, TM_CHCCS_Enum Sel, u8 Filter) +{ + vu32* pIcfr = (vu32*)&TMx->CH0ICFR + Ch; + u32 wIcfr, wChpolr; + + /* Disable the channel N: reset the CHxE bit */ + TMx->CHCTR &= ~((u32)0x1 << (Ch << 1)); + + wIcfr = *pIcfr; + wChpolr = TMx->CHPOLR; + + /* Select the input and set the filter */ + wIcfr &= CHICFR_CHCCS_MASK & CHICFR_CHF_MASK; + wIcfr |= Sel | Filter; + *pIcfr = wIcfr; + + /* Select the polarity bit */ + wChpolr &= ~((u32)0x1 << (Ch << 1)); + wChpolr |= (u32)Pol << (Ch << 1); + TMx->CHPOLR = wChpolr; + + /* Set the CHxE Bit */ + TMx->CHCTR |= (u32)0x1 << (Ch << 1); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usart.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usart.c new file mode 100644 index 00000000000..c0dd366f364 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usart.c @@ -0,0 +1,911 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_usart.c + * @version $Rev:: 7054 $ + * @date $Date:: 2023-07-24 #$ + * @brief This file provides all the USART firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_usart.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup USART USART + * @brief USART driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup USART_Private_Define USART private definitions + * @{ + */ +#define CR_CLEAR_Mask ((u32)0xFFFFE0FC) + +#define USART_BREAK_ON ((u32)0x00004000) +#define USART_BREAK_OFF ((u32)0xFFFFBFFF) + +#define USART_PBE_ON ((u32)0x00000800) +#define USART_SPE_ON ((u32)0x00002000) +#define USART_SPE_OFF ((u32)0xFFFFDFFF) + +#define USART_EN_ON ((u32)0x00000010) + +#define USART_HFCEN_ON ((u32)0x00000008) +#define USART_HFCEN_OFF ((u32)0xFFFFFFF7) + +#define USART_RXTOEN_ON ((u32)0x00000080) + +#define FCR_TL_Mask ((u32)0x00000030) + +#define TRSM_CLEAR_Mask ((u32)0xFFFFFFFB) +#define TPR_TG_Mask ((u32)0xFFFF00FF) +#define ICR_IRDAPSC_Mask ((u32)0xFFFF00FF) +#define TPR_RXTOIC_Mask ((u32)0xFFFFFF80) +#define RS485CR_ADDM_Mask ((u32)0xFFFF00FF) + +#define USART_IRDA_ON ((u32)0x00000001) +#define USART_IRDA_OFF ((u32)0xFFFFFFFE) + +#define USART_INV_ON ((u32)0x00000010) + +#define USART_RS485NMM_ON ((u32)0x00000002) +#define USART_RS485NMM_OFF ((u32)0xFFFFFFFD) + +#define USART_RS485AAD_ON ((u32)0x00000004) +#define USART_RS485AAD_OFF ((u32)0xFFFFFFFB) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup USART_Exported_Functions USART exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the USART/UART peripheral registers to their default reset values. + * @param USARTx: Parameter to select the UxART peripheral. + * @retval None + ************************************************************************************************************/ +void USART_DeInit(HT_USART_TypeDef* USARTx) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + u32 uIPAddr = (u32)USARTx; + + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + switch (uIPAddr) + { + #if (!LIBCFG_NO_USART0) + case HT_USART0_BASE: + { + RSTCUReset.Bit.USART0 = 1; + break; + } + #endif + #if (LIBCFG_USART1) + case HT_USART1_BASE: + { + RSTCUReset.Bit.USART1 = 1; + break; + } + #endif + case HT_UART0_BASE: + { + RSTCUReset.Bit.UART0 = 1; + break; + } + #if (LIBCFG_UART1) + case HT_UART1_BASE: + { + RSTCUReset.Bit.UART1 = 1; + break; + } + #endif + #if (LIBCFG_UART2) + case HT_UART2_BASE: + { + RSTCUReset.Bit.UART2 = 1; + break; + } + #endif + #if (LIBCFG_UART3) + case HT_UART3_BASE: + { + RSTCUReset.Bit.UART3 = 1; + break; + } + #endif + } + + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Initialize the USART/UART peripheral according to the specified parameters in the USART_InitStruct. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_Init(HT_USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + u32 uIPClock = 0; + u32 uIPAddr = (u32)USARTx; + + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + Assert_Param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + Assert_Param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + Assert_Param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + Assert_Param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + + USARTx->CR = (USARTx->CR & CR_CLEAR_Mask) | USART_InitStruct->USART_StopBits | + USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + + switch (uIPAddr) + { + #if (!LIBCFG_NO_USART0) + case HT_USART0_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_USART0); + break; + } + #endif + #if (LIBCFG_USART1) + case HT_USART1_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_USART1); + break; + } + #endif + case HT_UART0_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_UART0); + break; + } + #if (LIBCFG_UART1) + case HT_UART1_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_UART1); + break; + } + #endif + #if (LIBCFG_UART2) + case HT_UART2_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_UART2); + break; + } + #endif + #if (LIBCFG_UART3) + case HT_UART3_BASE: + { + uIPClock = CKCU_GetPeripFrequency(CKCU_PCLK_UART3); + break; + } + #endif + } + + USARTx->DLR = uIPClock / (u32)USART_InitStruct->USART_BaudRate; +} + +/*********************************************************************************************************//** + * @brief Fill each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WORDLENGTH_8B; + USART_InitStruct->USART_StopBits = USART_STOPBITS_1; + USART_InitStruct->USART_Parity = USART_PARITY_NO; + USART_InitStruct->USART_Mode = USART_MODE_NORMAL; +} + +/*********************************************************************************************************//** + * @brief USART/UART send data to Tx. + * @param USARTx: Parameter to select the UxART peripheral. + * @param Data: the data to be transmitted. + * @retval None + ************************************************************************************************************/ +void USART_SendData(HT_USART_TypeDef* USARTx, u16 Data) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_DATA(Data)); + + USARTx->DR = Data; +} + +/*********************************************************************************************************//** + * @brief USART/UART receive data from Rx. + * @param USARTx: Parameter to select the UxART peripheral. + * @retval The received data. + ************************************************************************************************************/ +u16 USART_ReceiveData(HT_USART_TypeDef* USARTx) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + return (u16)(USARTx->DR); +} + +/*********************************************************************************************************//** + * @brief Get the specified USART/UART status flags. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_FLAG_x: Specify the flag to be check. + * This parameter can be one of the following values: + * @arg USART_FLAG_RXDNE : + * @arg USART_FLAG_OE : + * @arg USART_FLAG_PE : + * @arg USART_FLAG_FE : + * @arg USART_FLAG_BI : + * @arg USART_FLAG_RXDR : + * @arg USART_FLAG_TOUT : + * @arg USART_FLAG_TXDE : + * @arg USART_FLAG_TXC : + * @arg USART_FLAG_RSADD : + * @arg USART_FLAG_CTSC : + * @arg USART_FLAG_CTSS : + * @arg USART_FLAG_LBD : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus USART_GetFlagStatus(HT_USART_TypeDef* USARTx, u32 USART_FLAG_x) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_FLAG(USART_FLAG_x)); + + if ((USARTx->SR & USART_FLAG_x) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } +} + +/*********************************************************************************************************//** + * @brief Get the specified USART/UART INT status. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_INT_x: Specify if the USART/UART interrupt source. + * This parameter can be one of the following values: + * @arg USART_INT_RXDR : + * @arg USART_INT_TXDE : + * @arg USART_INT_TXC : + * @arg USART_INT_OE : + * @arg USART_INT_PE : + * @arg USART_INT_FE : + * @arg USART_INT_BI : + * @arg USART_INT_RSADD : + * @arg USART_INT_TOUT : + * @arg USART_INT_CTS : + * @arg USART_INT_LBD : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus USART_GetIntStatus(HT_USART_TypeDef* USARTx, u32 USART_INT_x) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_INT(USART_INT_x)); + + if ((USARTx->IER & USART_INT_x) != (u32)RESET) + { + return (SET); + } + else + { + return (RESET); + } +} + +/*********************************************************************************************************//** + * @brief Clear the specified USART/UART flags. + * @param USARTx: where USARTx is the selected USART/UART from the USART/UART peripherals. + * @param USART_Flag: Specify the flag to check. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_OE : + * @arg USART_FLAG_PE : + * @arg USART_FLAG_FE : + * @arg USART_FLAG_BI : + * @arg USART_FLAG_TOUT : + * @arg USART_FLAG_RSADD : + * @arg USART_FLAG_CTSC : + * @arg USART_FLAG_LBD : + * @retval SET or RESET + ************************************************************************************************************/ +void USART_ClearFlag(HT_USART_TypeDef* USARTx, u32 USART_Flag) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_CLEAR_FLAG(USART_Flag)); + + USARTx->SR &= USART_Flag; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART interrupts. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_INT_x: Specify if the USART/UART interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_INT_RXDR : + * @arg USART_INT_TXDE : + * @arg USART_INT_TXC : + * @arg USART_INT_OE : + * @arg USART_INT_PE : + * @arg USART_INT_FE : + * @arg USART_INT_BI : + * @arg USART_INT_RSADD : + * @arg USART_INT_TOUT : + * @arg USART_INT_CTS : +* @arg USART_INT_LBD : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_IntConfig(HT_USART_TypeDef* USARTx, u32 USART_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_INT(USART_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->IER |= USART_INT_x; + } + else + { + USARTx->IER &= ~USART_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART Tx/Rx. + * @param USARTx: Parameter to select the USART peripheral. + * @param TxRx: This parameter can be USART_CMD_TX or USART_CMD_RX. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_TxRxCmd(HT_USART_TypeDef* USARTx, u32 TxRx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + if (NewState != DISABLE) + { + USARTx->CR |= (USART_EN_ON << TxRx); + } + else + { + USARTx->CR &= ~(USART_EN_ON << TxRx); + } +} + +#if (LIBCFG_PDMA) +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART PDMA interface. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_PDMAREQ: specify the USART/UART PDMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg USART_PDMAREQ_TX + * @arg USART_PDMAREQ_RX + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_PDMACmd(HT_USART_TypeDef* USARTx, u32 USART_PDMAREQ, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_PDMA_REQ(USART_PDMAREQ)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->CR |= USART_PDMAREQ; + } + else + { + USARTx->CR &= ~USART_PDMAREQ; + } +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART break control function. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_ForceBreakCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->CR |= USART_BREAK_ON; + } + else + { + USARTx->CR &= USART_BREAK_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART/UART stick parity function. + * @param USARTx: Parameter to select the UxART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_StickParityCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->CR |= USART_SPE_ON | USART_PBE_ON; + } + else + { + USARTx->CR &= USART_SPE_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Configure the stick parity value of the USART/UART. + * @param USARTx: Parameter to select the UxART peripheral. + * @param USART_StickParity: Specify the stick parity of the USART/UART. + * This parameter can be one of the following values: + * @arg USART_STICK_LOW + * @arg USART_STICK_HIGH + * @retval None + ************************************************************************************************************/ +void USART_StickParityConfig(HT_USART_TypeDef * USARTx, u32 USART_StickParity) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_STICK_PARITY(USART_StickParity)); + + if (USART_StickParity != USART_STICK_HIGH) + { + USARTx->CR |= USART_STICK_LOW; + } + else + { + USARTx->CR &= USART_STICK_HIGH; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified USART guard time. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_GuardTime: Specify the guard time. + * @retval None + ************************************************************************************************************/ +void USART_SetGuardTime(HT_USART_TypeDef* USARTx, u32 USART_GuardTime) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_GUARD_TIME(USART_GuardTime)); + + USARTx->TPR = (USARTx->TPR & TPR_TG_Mask) | (USART_GuardTime << 0x08); +} + +/*********************************************************************************************************//** + * @brief Configure the Tx/Rx FIFO Interrupt Trigger Level. + * @param USARTx: Parameter to select the USART peripheral. + * @param TxRx: This parameter can be USART_CMD_TX or USART_CMD_RX. + * @param USART_tl: Specify the USART Tx/Rx FIFO interrupt trigger level. + * This parameter can be one of the following values: + * @arg USART_RXTL_01 + * @arg USART_RXTL_02 + * @arg USART_RXTL_04 + * @arg USART_RXTL_06 + * @arg USART_TXTL_00 + * @arg USART_TXTL_02 + * @arg USART_TXTL_04 + * @arg USART_TXTL_06 + * @retval None + ************************************************************************************************************/ +void USART_TXRXTLConfig(HT_USART_TypeDef* USARTx, u32 TxRx, u32 USART_tl) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_TL(USART_tl)); + + USARTx->FCR = (USARTx->FCR & ~(FCR_TL_Mask << (TxRx * 2))) | (USART_tl << (TxRx * 2)); +} + +/*********************************************************************************************************//** + * @brief Set the USART FIFO time-out value. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_TimeOut: Specify the time-out value. + * @retval None + ************************************************************************************************************/ +void USART_SetTimeOutValue(HT_USART_TypeDef* USARTx, u32 USART_TimeOut) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_TIMEOUT(USART_TimeOut)); + + USARTx->TPR = (USARTx->TPR & TPR_RXTOIC_Mask) | USART_TimeOut | USART_RXTOEN_ON; +} + +/*********************************************************************************************************//** + * @brief Clear both the write and read point in USART Tx FIFO or Rx FIFO. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_FIFODirection: Determine TX FIFO or Rx FIFO that is to be reset. + * This parameter can be any combination of the following values: + * @arg USART_FIFO_TX + * @arg USART_FIFO_RX + * @retval None + ************************************************************************************************************/ +void USART_FIFOReset(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_FIFO_DIRECTION(USART_FIFODirection)); + + USARTx->FCR |= USART_FIFODirection; +} + +/*********************************************************************************************************//** + * @brief Return the status of specified USART FIFO. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_FIFODirection: specify the FIFO that is to be check. + * This parameter can be one of the following values: + * @arg USART_FIFO_TX + * @arg USART_FIFO_RX + * @retval The number of data in Tx FIFO or Rx FIFO. + ************************************************************************************************************/ +u8 USART_GetFIFOStatus(HT_USART_TypeDef* USARTx, u32 USART_FIFODirection) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_FIFO_DIRECTION(USART_FIFODirection)); + + if (USART_FIFODirection == USART_FIFO_TX) + { + return (u8)((USARTx->FCR & 0xF0000) >> 16); + } + else + { + return (u8)((USARTx->FCR & 0xF000000) >> 24); + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART hardware flow control. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_HardwareFlowControlCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->CR |= USART_HFCEN_ON; + } + else + { + USARTx->CR &= USART_HFCEN_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART IrDA interface. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_IrDACmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->ICR |= USART_IRDA_ON; + } + else + { + USARTx->ICR &= USART_IRDA_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Configure the USART IrDA interface. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_IrDAMode: Specify the USART IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IRDA_LOWPOWER + * @arg USART_IRDA_NORMAL + * @retval None + ************************************************************************************************************/ +void USART_IrDAConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDAMode) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + if (USART_IrDAMode != USART_IRDA_NORMAL) + { + USARTx->ICR |= USART_IRDA_LOWPOWER; + } + else + { + USARTx->ICR &= USART_IRDA_NORMAL; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified USART IrDA prescaler. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_IrDAPrescaler: Specify the USART IrDA prescaler. + * @retval None + ************************************************************************************************************/ +void USART_SetIrDAPrescaler(HT_USART_TypeDef* USARTx, u32 USART_IrDAPrescaler) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_IRDA_PRESCALER(USART_IrDAPrescaler)); + + USARTx->ICR = (USARTx->ICR & ICR_IRDAPSC_Mask) | (USART_IrDAPrescaler << 0x08); +} + +/*********************************************************************************************************//** + * @brief Enable the IrDA transmitter or receiver. + * @param USARTx: Parameter to select the USART peripheral, x can be 0 or 1. + * @param USART_IrDADirection: Specify the USART IrDA direction select. + * This parameter can be one of the following values: + * @arg USART_IRDA_TX + * @arg USART_IRDA_RX + * @retval None + ************************************************************************************************************/ +void USART_IrDADirectionConfig(HT_USART_TypeDef* USARTx, u32 USART_IrDADirection) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_IRDA_DIRECTION(USART_IrDADirection)); + + if (USART_IrDADirection != USART_IRDA_RX) + { + USARTx->ICR |= USART_IRDA_TX; + } + else + { + USARTx->ICR &= USART_IRDA_RX; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable inverting serial output/input function of IrDA on the specified USART. + * @param USARTx: Parameter to select the USART peripheral. + * @param inout: This parameter can be USART_CMD_OUT or USART_CMD_IN. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_IrDAInvtCmd(HT_USART_TypeDef* USARTx, u32 inout, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->ICR |= (USART_INV_ON << inout); + } + else + { + USARTx->ICR &= ~(USART_INV_ON << inout); + } +} + +/*********************************************************************************************************//** + * @brief Configure the polarity of USART RS485 transmitter enable signal. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_RS485Polarity: Specify the polarity of USART RS485 Tx enable signal. + * This parameter can be one of the following values: + * @arg USART_RS485POL_LOW + * @arg USART_RS485POL_HIGH + * @retval None + ************************************************************************************************************/ +void USART_RS485TxEnablePolarityConfig(HT_USART_TypeDef* USARTx, u32 USART_RS485Polarity) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_RS485_POLARITY(USART_RS485Polarity)); + + if (USART_RS485Polarity != USART_RS485POLARITY_HIGH) + { + USARTx->RCR |= USART_RS485POLARITY_LOW; + } + else + { + USARTx->RCR &= USART_RS485POLARITY_HIGH; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART RS485 normal multi-drop operation mode. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_RS485NMMCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->RCR |= USART_RS485NMM_ON; + } + else + { + USARTx->RCR &= USART_RS485NMM_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the USART RS485 normal multi-drop operation mode. + * @param USARTx: Parameter to select the USART peripheral. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void USART_RS485AADCmd(HT_USART_TypeDef* USARTx, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + USARTx->RCR |= USART_RS485AAD_ON; + } + else + { + USARTx->RCR &= USART_RS485AAD_OFF; + } +} + +/*********************************************************************************************************//** + * @brief Set the specified USART RS485 address match value. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_AddressMatchValue: specify the USART RS485 address match value. + * @retval None + ************************************************************************************************************/ +void USART_SetAddressMatchValue(HT_USART_TypeDef* USARTx, u32 USART_AddressMatchValue) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_ADDRESS_MATCH_VALUE(USART_AddressMatchValue)); + + USARTx->RCR = (USARTx->RCR & RS485CR_ADDM_Mask) | (u32)(USART_AddressMatchValue << 0x08); +} + +/*********************************************************************************************************//** + * @brief Initialize the clock of the USART peripheral according to the specified parameters + * in the USART_ClockInitStruct. + * @param USARTx: Parameter to select the USART peripheral. + * @param USART_SynClock_InitStruct: pointer to a USART_SynClock_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_SynClockInit(HT_USART_TypeDef* USARTx, USART_SynClock_InitTypeDef* USART_SynClock_InitStruct) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_SYNCHRONOUS_CLOCK(USART_SynClock_InitStruct->USART_ClockEnable)); + Assert_Param(IS_USART_SYNCHRONOUS_PHASE(USART_SynClock_InitStruct->USART_ClockPhase)); + Assert_Param(IS_USART_SYNCHRONOUS_POLARITY(USART_SynClock_InitStruct->USART_ClockPolarity)); + Assert_Param(IS_USART_TRANSFER_MODE(USART_SynClock_InitStruct->USART_TransferSelectMode)); + + USARTx->SCR = USART_SynClock_InitStruct->USART_ClockEnable | USART_SynClock_InitStruct->USART_ClockPhase | + USART_SynClock_InitStruct->USART_ClockPolarity; + + USARTx->CR = (USARTx->CR & TRSM_CLEAR_Mask) | USART_SynClock_InitStruct->USART_TransferSelectMode; +} + +/*********************************************************************************************************//** + * @brief Fill each USART_SynClockInitStruct member with its default value. + * @param USART_SynClock_InitStruct: pointer to a USART_SynClock_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void USART_SynClockStructInit(USART_SynClock_InitTypeDef* USART_SynClock_InitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_SynClock_InitStruct->USART_ClockEnable = USART_SYN_CLOCK_DISABLE; + USART_SynClock_InitStruct->USART_ClockPhase = USART_SYN_CLOCK_PHASE_FIRST; + USART_SynClock_InitStruct->USART_ClockPolarity = USART_SYN_CLOCK_POLARITY_LOW; + USART_SynClock_InitStruct->USART_TransferSelectMode = USART_LSB_FIRST; +} + +#if (LIBCFG_USART_LIN) +/*********************************************************************************************************//** + * @brief USART/UART LIN Mode send break to Tx. + * @param USARTx: where USARTx is the selected USART/UART from the USART/UART peripherals. + * @retval None + ************************************************************************************************************/ +void USART_LIN_SendBreak(HT_USART_TypeDef* USARTx) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + + USARTx->CR |= USART_LINSENDBREAK; +} + + +/*********************************************************************************************************//** + * @brief Configure the break detection length in LIN mode. + * @param USARTx: where USARTx is the selected USART/UART from the USART/UART peripherals. + * @param length: data length in byte. + * This parameter can be one of the following values: + * @arg USART_LINLENGTH_11BIT + * @arg USART_LINLENGTH_10BIT + * @retval None + ************************************************************************************************************/ +void USART_LIN_LengthSelect(HT_USART_TypeDef* USARTx, u32 USART_LIN_Length) +{ + /* Check the parameters */ + Assert_Param(IS_USART(USARTx)); + Assert_Param(IS_USART_LINLENGTH(USART_LIN_Length)); + + if (USART_LIN_Length != USART_LINLENGTH_10BIT) + { + USARTx->CR |= USART_LINLENGTH_11BIT; + } + else + { + USARTx->CR &= USART_LINLENGTH_10BIT; + } +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usbd.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usbd.c new file mode 100644 index 00000000000..a6597e97b7e --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_usbd.c @@ -0,0 +1,855 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_usbd.c + * @version $Rev:: 7335 $ + * @date $Date:: 2023-11-09 #$ + * @brief The USB Device Peripheral Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32f5xxxx_usbdchk.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup USBDevice USB Device + * @brief USB Device driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Constant USB Device private constants + * @{ + */ +#define TCR_MASK (0x1FF) +#define EPLEN_MASK ((u32)0x000FFC00) +#define EPBUFA_MASK ((u32)0x000003FF) +#define ISR_EPn_OFFSET (8) + +/* USB Control and Status Register (USBCSR) */ +#define FRES ((u32)0x00000002) /* Force USB Reset */ +#define PDWN ((u32)0x00000004) /* Power Down */ +#define LPMODE ((u32)0x00000008) /* Low-power Mode */ +#define GENRSM ((u32)0x00000020) /* Generate Resume */ +#define ADRSET ((u32)0x00000100) /* Device Address Setting */ +#define SRAMRSTC ((u32)0x00000200) /* USB SRAM reset condition */ +#define DPPUEN ((u32)0x00000400) /* DP Pull Up Enable */ +#define DPWKEN ((u32)0x00000800) /* DP Wake Up Enable */ + +#define EPDIR_IN (1) +#define EPDIR_OUT (0) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Variable USB Device private variables + * @{ + */ +static u32 gIsFirstPowered = TRUE; +/** + * @} + */ + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Macro USB Device private macros + * @{ + */ +#ifndef USBDCore_LowPower + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#endif +/** + * @brief Convert Byte length to Word length + */ +#define ByteLen2WordLen(n) ((n + 3) >> 2) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void _USBD_CopyMemory(u32 *pFrom, u32 *pTo, u32 len); +static HT_USBEP_TypeDef * _USBD_GetEPTnAddr(USBD_EPTn_Enum USBD_EPTn); +static void _delay(u32 nCount); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Exported_Functions USB Device exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Pre initialization for USBD_Init function. + * @param pDriver: USB initialization structure + * @retval None + ***********************************************************************************************************/ +void USBD_PreInit(USBD_Driver_TypeDef *pDriver) +{ + pDriver->uInterruptMask = _UIER_ALL; + + pDriver->ept[USBD_EPT0].CFGR.word = _EP0_CFG; + pDriver->ept[USBD_EPT0].IER = _EP0_IER; + + #if (_EP1_ENABLE == 1) + pDriver->ept[USBD_EPT1].CFGR.word = _EP1_CFG; + pDriver->ept[USBD_EPT1].IER = _EP1_IER; + #endif + + #if (_EP2_ENABLE == 1) + pDriver->ept[USBD_EPT2].CFGR.word = _EP2_CFG; + pDriver->ept[USBD_EPT2].IER = _EP2_IER; + #endif + + #if (_EP3_ENABLE == 1) + pDriver->ept[USBD_EPT3].CFGR.word = _EP3_CFG; + pDriver->ept[USBD_EPT3].IER = _EP3_IER; + #endif + + #if (_EP4_ENABLE == 1) + pDriver->ept[USBD_EPT4].CFGR.word = _EP4_CFG; + pDriver->ept[USBD_EPT4].IER = _EP4_IER; + #endif + + #if (_EP5_ENABLE == 1) + pDriver->ept[USBD_EPT5].CFGR.word = _EP5_CFG; + pDriver->ept[USBD_EPT5].IER = _EP5_IER; + #endif + + #if (_EP6_ENABLE == 1) + pDriver->ept[USBD_EPT6].CFGR.word = _EP6_CFG; + pDriver->ept[USBD_EPT6].IER = _EP6_IER; + #endif + + #if (_EP7_ENABLE == 1) + pDriver->ept[USBD_EPT7].CFGR.word = _EP7_CFG; + pDriver->ept[USBD_EPT7].IER = _EP7_IER; + #endif + + #if (LIBCFG_USBD_V2) + #if (_EP8_ENABLE == 1) + pDriver->ept[USBD_EPT8].CFGR.word = _EP8_CFG; + pDriver->ept[USBD_EPT8].IER = _EP8_IER; + #endif + + #if (_EP9_ENABLE == 1) + pDriver->ept[USBD_EPT9].CFGR.word = _EP9_CFG; + pDriver->ept[USBD_EPT9].IER = _EP9_IER; + #endif + #endif + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Peripheral initialization. + * @param pDriver: USB initialization structure + * @retval None + ***********************************************************************************************************/ +void USBD_Init(u32 *pDriver) +{ + USBD_Driver_TypeDef *pDrv = (USBD_Driver_TypeDef *)pDriver; + + /* Init USB Device Driver struct */ + USBD_PreInit(pDrv); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Internal DP pull up. + * @param NewState: ENABLE or DISABLE + * @retval None + ***********************************************************************************************************/ +void USBD_DPpullupCmd(ControlStatus NewState) +{ + (NewState == ENABLE)?(HT_USB->CSR |= DPPUEN):(HT_USB->CSR &= ~DPPUEN); +} + +/*********************************************************************************************************//** + * @brief USB Device Wake Up when DP is high level. + * @param NewState: ENABLE or DISABLE + * @retval None + ***********************************************************************************************************/ +void USBD_DPWakeUpCmd(ControlStatus NewState) +{ + (NewState == ENABLE)?(HT_USB->CSR |= DPWKEN):(HT_USB->CSR &= ~DPWKEN); +} + +/*********************************************************************************************************//** + * @brief USB Device Peripheral deinitialization. + * @retval None + ***********************************************************************************************************/ +void USBD_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.USBD = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); + + return; +} + +/*********************************************************************************************************//** + * @brief USB power up procedure. + * @retval None + ***********************************************************************************************************/ +void USBD_PowerUp(u32 *pDriver, u32 uIsSelfPowered) +{ + USBD_Driver_TypeDef *pDrv = (USBD_Driver_TypeDef *)pDriver; + + if (gIsFirstPowered == TRUE) + { + gIsFirstPowered = FALSE; + + if (HT_USB->CSR & 0x40) + { + HT_USB->CSR = (DPPUEN | LPMODE | PDWN); + while((HT_USB->ISR & URSTIE) == 0); + HT_USB->ISR = 0xFFFFFFFF; + if (uIsSelfPowered == FALSE) + { + USBDCore_LowPower(); + } + USBD_EnableINT(pDrv->uInterruptMask); + } + else + { + HT_USB->CSR = (DPWKEN | DPPUEN | LPMODE | PDWN); + while((HT_USB->ISR & URSTIE) == 0); + HT_USB->ISR = 0xFFFFFFFF; + if (uIsSelfPowered == FALSE) + { + USBDCore_LowPower(); + } + USBD_DPWakeUpCmd(DISABLE); + USBD_EnableINT(pDrv->uInterruptMask); + USBD_DPpullupCmd(DISABLE); + _delay(200); + USBD_DPpullupCmd(ENABLE); + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief Enter USB Device Power Down mode. + * @retval None + ***********************************************************************************************************/ +void USBD_PowerOff(void) +{ + HT_USB->CSR |= (LPMODE | PDWN); + return; +} + +/*********************************************************************************************************//** + * @brief Exit USB Device Power Down mode. + * @retval None + ***********************************************************************************************************/ +void USBD_PowerOn(void) +{ + HT_USB->CSR |= 0x00001000; + HT_USB->CSR &= 0x00001400; + return; +} + +/*********************************************************************************************************//** + * @brief USB SRAM reset condition. + * @param NewState: ENABLE or DISABLE + * @retval None + ***********************************************************************************************************/ +void USBD_SRAMResetConditionCmd(ControlStatus NewState) +{ + (NewState == ENABLE)?(HT_USB->CSR |= SRAMRSTC):(HT_USB->CSR &= ~SRAMRSTC); +} + +/*********************************************************************************************************//** + * @brief Disable Default pull resistance of D+ and D-. + * @retval None + ***********************************************************************************************************/ +void USBD_DisableDefaultPull(void) +{ + HT_USB->CSR = FRES; // Clear PDWN and keep FRES = 1 +} + +/*********************************************************************************************************//** + * @brief Generate a resume request to USB Host for Remote Wakeup function. + * @retval None + ***********************************************************************************************************/ +void USBD_RemoteWakeup(void) +{ + HT_USB->CSR |= GENRSM; + return; +} + +/*********************************************************************************************************//** + * @brief Read Endpoint0 SETUP data from USB Buffer. + * @param pBuffer: Buffer for save SETUP data + * @retval None + ***********************************************************************************************************/ +void USBD_ReadSETUPData(u32 *pBuffer) +{ + u32 *pSrc = (u32 *)HT_USB_SRAM_BASE; + + *pBuffer = *pSrc; + *(pBuffer + 1) = *(pSrc + 1); + return; +} + +/*********************************************************************************************************//** + * @brief Set USB Device address. + * @param address: USB address which specified by Host + * @retval None + ***********************************************************************************************************/ +void USBD_SetAddress(u32 address) +{ + HT_USB->CSR |= ADRSET; + HT_USB->DEVAR = address; + return; +} + +/*********************************************************************************************************//** + * @brief Enable USB Device interrupt. + * @param INTFlag: USB Device global interrupt flag + * @arg UGIE | SOFIE | URSTIE | RSMIE | SUSPIE | ESOFIE + * EP0IE | EP1IE | EP2IE | EP3IE | EP4IE | EP5IE | EP6IE | EP7IE | EP8IE | EP9IE + * @retval None + ***********************************************************************************************************/ +void USBD_EnableINT(u32 INTFlag) +{ + HT_USB->IER |= INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Disable USB Device interrupt. + * @param INTFlag: USB Device global interrupt flag + * @arg UGIE | SOFIE | URSTIE | RSMIE | SUSPIE | ESOFIE + * EP0IE | EP1IE | EP2IE | EP3IE | EP4IE | EP5IE | EP6IE | EP7IE | EP8IE | EP9IE + * @retval None + ***********************************************************************************************************/ +void USBD_DisableINT(u32 INTFlag) +{ + HT_USB->IER &= (~INTFlag); + return; +} + +/*********************************************************************************************************//** + * @brief Get active USB Device interrupt flag. + * @retval USB ISR Flag + ***********************************************************************************************************/ +u32 USBD_GetINT(void) +{ + u32 IER = HT_USB->IER | FRESIE; + return (HT_USB->ISR & IER); +} + +/*********************************************************************************************************//** + * @brief Clear USB Device interrupt flag. + * @param INTFlag: USB Device global interrupt flag + * @arg SOFIF | URSTIF | RSMIF | SUSPIF | ESOFIF + * EP0IF | EP1IF | EP2IF | EP3IF | EP4IF | EP5IF | EP6IF | EP7IF | EP8IF | EP9IF + * @retval None + ***********************************************************************************************************/ +void USBD_ClearINT(u32 INTFlag) +{ + HT_USB->ISR = INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Get USB Endpoint number by interrupt flag. + * @param INTFlag: USB Device global interrupt flag + * @arg SOFIF | URSTIF | RSMIF | SUSPIF | ESOFIF + * EP0IF | EP1IF | EP2IF | EP3IF | EP4IF | EP5IF | EP6IF | EP7IF | EP8IF | EP9IF + * @retval USB Endpoint number from USBD_EPT1 ~ USBD_EPT9 + ***********************************************************************************************************/ +USBD_EPTn_Enum USBD_GetEPTnINTNumber(u32 INTFlag) +{ + s32 i; + for (i = MAX_EP_NUM - 1; i > 0; i--) + { + if ((INTFlag >> (i + ISR_EPn_OFFSET)) & SET) + { + return (USBD_EPTn_Enum)i; + } + } + + return USBD_NOEPT; +} + +/*********************************************************************************************************//** + * @brief USB Device Peripheral initialization for Endpoint. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @param pDriver: USB initialization structure + * @retval None + ***********************************************************************************************************/ +void USBD_EPTInit(USBD_EPTn_Enum USBD_EPTn, u32 *pDriver) +{ + USBD_Driver_TypeDef *pDrv = (USBD_Driver_TypeDef *)pDriver; + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + + USBEPn->CFGR = pDrv->ept[USBD_EPTn].CFGR.word; + USBEPn->IER = pDrv->ept[USBD_EPTn].IER; + + USBEPn->ISR = 0xFFFFFFFF; + + USBD_EPTReset(USBD_EPTn); + + return; +} + +/*********************************************************************************************************//** + * @brief Reset Endpoint Status. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTReset(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + USBEPn->CSR = (USBEPn->CSR) & (DTGTX | DTGRX | NAKRX); + return; +} + +/*********************************************************************************************************//** + * @brief Enable Interrupt for Endpoint. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @param INTFlag: Interrupt flag + * @arg OTRXIE | ODRXIE | ODOVIE | ITRXIE | IDTXIE | NAKIE | STLIE | UERIE | + * STRXIE | SDRXIE | SDERIE | ZLRXIE + * @retval None + ***********************************************************************************************************/ +void USBD_EPTEnableINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag) +{ + _USBD_GetEPTnAddr(USBD_EPTn)->IER = INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Get active USB Device Endpoint interrupt. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval USB Endpoint ISR Flag + ***********************************************************************************************************/ +u32 USBD_EPTGetINT(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + u32 IER = USBEPn->IER; + return (USBEPn->ISR & IER); +} + +/*********************************************************************************************************//** + * @brief Clear Interrupt for Endpoint. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @param INTFlag: Interrupt flag + * @arg OTRXIF | ODRXIF | ODOVIF | ITRXIF | IDTXIF | NAKIF | STLIF | UERIF | + * STRXIF | SDRXIF | SDERIF | ZLRXIF + * @retval None + ***********************************************************************************************************/ +void USBD_EPTClearINT(USBD_EPTn_Enum USBD_EPTn, u32 INTFlag) +{ + _USBD_GetEPTnAddr(USBD_EPTn)->ISR = INTFlag; + return; +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n Halt status (STLTX or STLRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval Endpoint Halt Status (1: Endpoint is Halt, 0: Endpoint is not Halt) + ***********************************************************************************************************/ +u32 USBD_EPTGetHalt(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + return (((USBEPn->CSR) & STLTX) ? 1 : 0); + } + else + { + return (((USBEPn->CSR) & STLRX) ? 1 : 0); + } +} + +/*********************************************************************************************************//** + * @brief Send STALL on Endpoint n. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTSendSTALL(USBD_EPTn_Enum USBD_EPTn) +{ + _USBD_GetEPTnAddr(USBD_EPTn)->CSR = STLTX; + return; +} + +/*********************************************************************************************************//** + * @brief Set Endpoint n Halt status (STLTX or STLRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTSetHalt(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + +#if 1 + /* Clean STLIF flag, for USBD_EPTWaitSTALLSent function */ + USBEPn->ISR = STLIF; + USBEPn->CSR = (~(USBEPn->CSR)) & (STLTX | STLRX); +#else + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + /* Clean STLIF flag, for USBD_EPTWaitSTALLSent function */ + USBEPn->ISR = STLIF; + /* Set only when STLTX = 0 */ + USBEPn->CSR = (~(USBEPn->CSR)) & STLTX; + } + else + { + /* Set only when STLRX = 0 */ + USBEPn->CSR = (~(USBEPn->CSR)) & STLRX; + } +#endif + + return; +} + +/*********************************************************************************************************//** + * @brief Clear Endpoint n Halt status (STLTX or STLRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTClearHalt(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + +#if 1 + USBEPn->CSR = (USBEPn->CSR) & (STLTX | STLRX); +#else + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + /* Clear only when STLTX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & STLTX; + } + else + { + /* Clear only when STLRX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & STLRX; + } +#endif + + return; +} + +/*********************************************************************************************************//** + * @brief Wait until STALL transmission is finished + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTWaitSTALLSent(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + u32 uSTALLState = (CFGR->EPDIR == EPDIR_IN) ? ((USBEPn->CSR) & STLTX) : ((USBEPn->CSR) & STLRX); + + if (uSTALLState) + { + while ((USBEPn->ISR & STLIF) == 0); + } + + return; +} + +/*********************************************************************************************************//** + * @brief Clear Endpoint n Data toggle bit (DTGTX or DTGRX). + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval None + ***********************************************************************************************************/ +void USBD_EPTClearDTG(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + +#if 1 + USBEPn->CSR = (USBEPn->CSR) & (DTGTX | DTGRX); +#else + USBD_EPTCFGR_Bit *CFGR = (USBD_EPTCFGR_Bit *)(&(USBEPn->CFGR)); + if (CFGR->EPDIR == EPDIR_IN) + { + /* Clear only when DTGTX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & DTGTX; + } + else + { + /* Clear only when DTGRX = 1 */ + USBEPn->CSR = (USBEPn->CSR) & DTGRX; + } +#endif + return; +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n buffer 0 address. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval USB Endpoint buffer 0 address + ***********************************************************************************************************/ +u32 USBD_EPTGetBuffer0Addr(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + return (HT_USB_SRAM_BASE + (USBEPn->CFGR & EPBUFA_MASK)); +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n buffer 1 address. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval USB Endpoint buffer 1 address + ***********************************************************************************************************/ +u32 USBD_EPTGetBuffer1Addr(USBD_EPTn_Enum USBD_EPTn) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + return (HT_USB_SRAM_BASE + (USBEPn->CFGR & EPBUFA_MASK) + USBD_EPTGetBufferLen(USBD_EPTn)); +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n buffer length. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval USB Endpoint buffer length + ***********************************************************************************************************/ +u32 USBD_EPTGetBufferLen(USBD_EPTn_Enum USBD_EPTn) +{ + return ((_USBD_GetEPTnAddr(USBD_EPTn)->CFGR & EPLEN_MASK) >> 10); +} + +/*********************************************************************************************************//** + * @brief Get Endpoint n Transfer Count. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @param USBD_TCR_n: USBD_TCR_0 or USBD_TCR_1 + * @retval Endpoint Transfer Count + ***********************************************************************************************************/ +u32 USBD_EPTGetTransferCount(USBD_EPTn_Enum USBD_EPTn, USBD_TCR_Enum USBD_TCR_n) +{ + return (((_USBD_GetEPTnAddr(USBD_EPTn)->TCR) >> USBD_TCR_n) & TCR_MASK); +} + +/*********************************************************************************************************//** + * @brief Write IN Data from User buffer to USB buffer. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @param pFrom: Source buffer + * @param len: Length for write IN data + * @retval Total length written by this function + ***********************************************************************************************************/ +u32 USBD_EPTWriteINData(USBD_EPTn_Enum USBD_EPTn, u32 *pFrom, u32 len) +{ + u32 bufferlen = USBD_EPTGetBufferLen(USBD_EPTn); + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + u32 EPTnLen; + u32 *pTo; + + EPTnLen = (USBD_EPTn == USBD_EPT0) ? USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTIN):USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTB0); + + if (len <= bufferlen && EPTnLen == 0) + { + pTo = (u32 *)USBD_EPTGetBuffer0Addr(USBD_EPTn); + _USBD_CopyMemory(pFrom, pTo, ByteLen2WordLen(len)); + USBEPn->TCR = len; + USBEPn->CSR = NAKTX; + return len; + } + else + { + return 0; + } +} + +/*********************************************************************************************************//** + * @brief Read OUT Data from USB buffer to User buffer. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @param pTo: Destination memory + * @param len: Length for read OUT data, set as 0 for discard current OUT data in the USB buffer + * @retval Total length read by this function + ***********************************************************************************************************/ +u32 USBD_EPTReadOUTData(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len) +{ + HT_USBEP_TypeDef *USBEPn = _USBD_GetEPTnAddr(USBD_EPTn); + u32 EPTnLen = 0; + + if (len != 0) + { + EPTnLen = USBD_EPTReadMemory(USBD_EPTn, pTo, len); + } + + if (EPTnLen != 0 || len == 0) + { + USBEPn->CSR = (USBEPn->CSR & NAKRX); + } + + return EPTnLen; +} + +/*********************************************************************************************************//** + * @brief Read memory from endpoint buffer. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @param pTo: Destination buffer + * @param len: Length for read OUT data + * @retval Total length read by this function + ***********************************************************************************************************/ +u32 USBD_EPTReadMemory(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len) +{ + u32 EPTnLen = 0; + u32 *pFrom; + + EPTnLen = (USBD_EPTn == USBD_EPT0) ? USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTOUT):USBD_EPTGetTransferCount(USBD_EPTn, USBD_CNTB0); + + if (EPTnLen <= len) + { + pFrom = (USBD_EPTn == USBD_EPT0) ? (u32 *)USBD_EPTGetBuffer1Addr(USBD_EPTn):(u32 *)USBD_EPTGetBuffer0Addr(USBD_EPTn); + _USBD_CopyMemory(pFrom, pTo, ByteLen2WordLen(EPTnLen)); + } + + return EPTnLen; +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDevice_Private_Function USB Device private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Copy 32 bits memory from pFrom to pTo. + * @param pFrom: Source buffer + * @param pTo: Destination buffer + * @param len: Copy length + * @retval None + ***********************************************************************************************************/ +static void _USBD_CopyMemory(u32 *pFrom, u32 *pTo, u32 len) +{ + s32 i; + u32 uFromAligned = (((u32)pFrom & 0x3) == 0) ? 1 : 0; + u32 uToAligned = (((u32)pTo & 0x3) == 0) ? 1 : 0; + u8 *pFromByte = (u8 *)pFrom; + u8 *pToByte = (u8 *)pTo; + + if (uFromAligned == 0) + { + if (uToAligned == 0) + { + for (i = len - 1; i >= 0; i--) + { + *pToByte++ = *pFromByte++; + *pToByte++ = *pFromByte++; + *pToByte++ = *pFromByte++; + *pToByte++ = *pFromByte++; + } + } + else + { + u32 uTemp = 0; + for (i = 0; i < (s32)len; i++) + { + uTemp = *(pFromByte++) << 0; + uTemp += *(pFromByte++) << 8; + uTemp += *(pFromByte++) << 16; + uTemp += *(pFromByte++) << 24; + pTo[i] = uTemp; + } + } + } + else + { + if (uToAligned == 0) + { + u32 uTemp = 0; + for (i = 0; i < (s32)len; i++) + { + uTemp = pFrom[i]; + *pToByte++ = (uTemp >> 0) & 0xFF; + *pToByte++ = (uTemp >> 8) & 0xFF; + *pToByte++ = (uTemp >> 16) & 0xFF; + *pToByte++ = (uTemp >> 24) & 0xFF; + } + } + else + { + for (i = len - 1; i >= 0; i--) + { + pTo[i] = pFrom[i]; + } + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief Convent USBD_EPTn_Enum to USBEP_TypeDef. + * @param USBD_EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT9 + * @retval USBEP0 ~ USBEP9 + ***********************************************************************************************************/ +static HT_USBEP_TypeDef * _USBD_GetEPTnAddr(USBD_EPTn_Enum USBD_EPTn) +{ + return ((HT_USBEP_TypeDef *)(HT_USBEP0 + USBD_EPTn)); +} + +/*********************************************************************************************************//** + * @brief Inserts a delay time. + * @param nCount: specifies the delay time length. + * @retval None + ***********************************************************************************************************/ +static void _delay(u32 nCount) +{ + u32 i; + + for (i = 0; i < nCount; i++) + { + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_wdt.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_wdt.c new file mode 100644 index 00000000000..b90f5b1face --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f5xxxx_wdt.c @@ -0,0 +1,343 @@ +/*********************************************************************************************************//** + * @file ht32f5xxxx_wdt.c + * @version $Rev:: 2772 $ + * @date $Date:: 2018-05-15 #$ + * @brief This file provides all the WDT firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f5xxxx_wdt.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup WDT WDT + * @brief WDT driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Private_Define WDT private definitions + * @{ + */ + +/* WDT Restart Key */ +#define RESTART_KEY ((u32)0x5FA00000) + +/* WDT Protect mask */ +#define PRCT_SET ((u32)0x0000CA35) +#define PRCT_RESET ((u32)0x000035CA) + +/* WDT WDTFIEN mask */ +#define MODE0_WDTFIEN_SET ((u32)0x00001000) +#define MODE0_WDTFIEN_RESET ((u32)0xFFFFEFFF) + +/* WDT WDTRSTEN mask */ +#define MODE0_WDTRETEN_SET ((u32)0x00002000) +#define MODE0_WDTRETEN_RESET ((u32)0xFFFFDFFF) + +/* WDT WDTEN mask */ +#define MODE0_WDTEN_SET ((u32)0x00010000) +#define MODE0_WDTEN_RESET ((u32)0xFFFEFFFF) + +/* WDT WDTLOCK mask */ +#define MODE0_WDTLOCK_SET ((u32)0x00000010) +#define MODE0_WDTLOCK_RESET ((u32)0x00000000) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup WDT_Exported_Functions WDT exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the WDT peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void WDT_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.WDT = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the WDT. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_Cmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_WDT->MR0 |= MODE0_WDTEN_SET; + } + else + { + HT_WDT->MR0 &= MODE0_WDTEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Configure the WDT to run or halt in sleep and deep sleep1 mode. + * @param WDT_Mode: + * This parameter can be one of the following values: + * @arg MODE0_WDTSHLT_BOTH : WDT runs in sleep and deep sleep1 mode + * @arg MODE0_WDTSHLT_SLEEP : WDT runs in sleep mode + * @arg MODE0_WDTSHLT_HALT : WDT halts in sleep and deep sleep1 mode + * @retval None + ************************************************************************************************************/ +void WDT_HaltConfig(u32 WDT_Mode) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_WDTSHLT_MODE(WDT_Mode)); + + HT_WDT->MR0 = ((WDT_Mode) | (HT_WDT->MR0 & 0x00013FFF)); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the WDT Reset when WDT meets underflow or error. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_ResetCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_WDT->MR0 |= MODE0_WDTRETEN_SET; + } + else + { + HT_WDT->MR0 &= MODE0_WDTRETEN_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable protection mechanism of the WDT. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_ProtectCmd(ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_WDT->PR = PRCT_SET; + } + else + { + HT_WDT->PR = PRCT_RESET; + } +} + +/*********************************************************************************************************//** + * @brief Set reload value of the WDT. + * @param WDT_WDTV : specify the WDT Reload value. + * This parameter must be a number between 0 and 0x0FFF + * @retval None + ************************************************************************************************************/ +void WDT_SetReloadValue(u16 WDT_WDTV) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_RELOAD(WDT_WDTV)); + + HT_WDT->MR0 = WDT_WDTV | (HT_WDT->MR0 & 0x0000F000); +} + +/*********************************************************************************************************//** + * @brief Get the current reload value of the WDT. + * @retval WDT reload value between 0 and 0x0FFF + ************************************************************************************************************/ +u16 WDT_GetReloadValue(void) +{ + return ((u16)(HT_WDT->MR0 & 0xFFF)); +} + +/*********************************************************************************************************//** + * @brief Set delta value of the WDT. + * @param WDT_WDTD : specify the WDT Delta value. + * This parameter must be a number between 0 and 0x0FFF + * @retval None + ************************************************************************************************************/ +void WDT_SetDeltaValue(u16 WDT_WDTD) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_DELTA(WDT_WDTD)); + + HT_WDT->MR1 = (WDT_WDTD | (HT_WDT->MR1 & 0x00007000)); +} + +/*********************************************************************************************************//** + * @brief Get current delta value of the WDT. + * @retval WDT delta value between 0 and 0x0FFF + ************************************************************************************************************/ +u16 WDT_GetDeltaValue(void) +{ + return ((u16)(HT_WDT->MR1 & 0xFFF)); +} + +/*********************************************************************************************************//** + * @brief Set prescaler value of the WDT. + * @param WDT_PRESCALER: specify the WDT Prescaler value. + * This parameter can be one of the following values: + * @arg WDT_PRESCALER_1 : WDT prescaler set to 1 + * @arg WDT_PRESCALER_2 : WDT prescaler set to 2 + * @arg WDT_PRESCALER_4 : WDT prescaler set to 4 + * @arg WDT_PRESCALER_8 : WDT prescaler set to 8 + * @arg WDT_PRESCALER_16 : WDT prescaler set to 16 + * @arg WDT_PRESCALER_32 : WDT prescaler set to 32 + * @arg WDT_PRESCALER_64 : WDT prescaler set to 64 + * @arg WDT_PRESCALER_128 : WDT prescaler set to 128 + * @retval None + ************************************************************************************************************/ +void WDT_SetPrescaler(u16 WDT_PRESCALER) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_PRESCALER(WDT_PRESCALER)); + + HT_WDT->MR1 = (WDT_PRESCALER | (HT_WDT->MR1 & 0x00000FFF)); +} + +/*********************************************************************************************************//** + * @brief Get the current prescaler value of the WDT. + * @retval WDT prescaler value + ************************************************************************************************************/ +u8 WDT_GetPrescaler(void) +{ + u32 tmp; + + tmp = HT_WDT->MR1 & 0x7000; + tmp >>= 12; + return ((u8)0x1 << tmp); +} + +/*********************************************************************************************************//** + * @brief WDT Restart (Reload WDT Counter) + * @retval None + ************************************************************************************************************/ +void WDT_Restart(void) +{ + HT_WDT->CR = RESTART_KEY | 0x1; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified WDT flag has been set. + * @param WDT_FLAG: specify the flag to be check. + * This parameter can be one of the following values: + * @arg WDT_FLAG_UNDERFLOW : WDT underflow active + * @arg WDT_FLAG_ERROR : WDT error active + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus WDT_GetFlagStatus(u32 WDT_FLAG) +{ + u32 statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + Assert_Param(IS_WDT_FLAG(WDT_FLAG)); + + statusreg = HT_WDT->SR; + + if (statusreg != WDT_FLAG) + { + bitstatus = RESET; + } + else + { + bitstatus = SET; + } + + return bitstatus; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the WDTLOCK. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void WDT_LockCmd(ControlStatus NewState) +{ + u32 uRegVale; + + /* Check the parameters */ + Assert_Param(IS_CONTROL_STATUS(NewState)); + + uRegVale = HT_WDT->CSR; + if (NewState != DISABLE) + { + HT_WDT->CSR |= (MODE0_WDTLOCK_SET | (uRegVale & 0x00000001)); + } + else + { + HT_WDT->CSR &= (MODE0_WDTLOCK_RESET | (uRegVale & 0x00000001)); + } +} + +#if (LIBCFG_LSE) +/*********************************************************************************************************//** + * @brief WDT source select. + * @param WDT_SOURCE: LSI or LSE of the WDT source. + * This parameter can be one of the following values: + * @arg WDT_SOURCE_LSI : + * @arg WDT_SOURCE_LSE : + * @retval None + ************************************************************************************************************/ +void WDT_SourceConfig(u32 WDT_SOURCE) +{ + /* Check the parameters */ + Assert_Param(IS_WDT_SOURCE_SELECT(WDT_SOURCE)); + + if (WDT_SOURCE != WDT_SOURCE_LSE) + { + HT_WDT->CSR = WDT_SOURCE_LSI; + } + else + { + HT_WDT->CSR = WDT_SOURCE_LSE; + } +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f652xx_adc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f652xx_adc.c new file mode 100644 index 00000000000..3071a5ac0a9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f652xx_adc.c @@ -0,0 +1,32 @@ +/*********************************************************************************************************//** + * @file ht32f652xx_adc.c + * @version $Rev:: 6921 $ + * @date $Date:: 2023-05-10 #$ + * @brief This file provides all the ADC firmware functions (for backward compatible). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f65xxx_66xxx_adc.c" + +// The original file has been renamed to ht32f65xxx_66xxx_adc.c +// This file is added for backward compatibility. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f652xx_opa.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f652xx_opa.c new file mode 100644 index 00000000000..dad9694c5f2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f652xx_opa.c @@ -0,0 +1,32 @@ +/*********************************************************************************************************//** + * @file ht32f652xx_opa.c + * @version $Rev:: 6919 $ + * @date $Date:: 2023-05-10 #$ + * @brief This file provides all the OPA firmware functions (for backward compatible). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f65xxx_66xxx_opa.c" + +// The original file has been renamed to ht32f65xxx_66xxx_opa.c +// This file is added for backward compatibility. diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_adc.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_adc.c new file mode 100644 index 00000000000..88c5d8acede --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_adc.c @@ -0,0 +1,784 @@ +/*********************************************************************************************************//** + * @file ht32f65xxx_66xxx_adc.c + * @version $Rev:: 7367 $ + * @date $Date:: 2023-12-06 #$ + * @brief This file provides all the ADC firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f65xxx_66xxx_adc.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC driver modules + * @{ + */ + + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup ADC_Private_Define ADC private definitions + * @{ + */ +#define ADC_ENABLE_BIT (0x00000080) +#define DUAL_MODE_MASK (0x00000003) +#define ADC_SOFTWARE_RESET (0x00000001) +#define LST_SEQ_SET (0x0000001F) +#define TCR_SC_SET (0x00000001) + +#define HLST_SEQ_SET (0x0000001F) +#define HTCR_SC_SET (0x00000001) + +#define OFR_ADOF_MASK (0x00000FFF) +#define OFR_ADAL (1 << 14) +#define OFR_ADOFE (1 << 15) +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions ADC exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the HT_ADCn peripheral registers to their default reset values. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + if (HT_ADCn == HT_ADC0) + { + RSTCUReset.Bit.ADC0 = 1; + } + #if (LIBCFG_ADC1) + else if (HT_ADCn == HT_ADC1) + { + RSTCUReset.Bit.ADC1 = 1; + } + #endif + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Reset ADC. + * @param HT_ADCn: is the selected ADC from the ADC peripherals. + * @retval None + ************************************************************************************************************/ +void ADC_Reset(HT_ADC_TypeDef* HT_ADCn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + HT_ADCn->RST |= ADC_SOFTWARE_RESET; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->CONV |= ADC_ENABLE_BIT; + } + else + { + HT_ADCn->CONV &= ~(ADC_ENABLE_BIT); + } +} + +#if (LIBCFG_ADC1) +/*********************************************************************************************************//** + * @brief Configure the ADC dual mode. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. (ADC1 only) + * @param DUAL_X: ADC dual mode configuration. + * This parameter can be one of the following values: + * @arg DUAL_INDEPENDENT : Independent mode (dual mode off). + * @arg DUAL_CASCADE_REGULAR : Cascade mode in regular conversion. + * @arg DUAL_CASCADE_REGULAR_H_PRIORITY : Cascade mode in regular/high priority conversion. + * @param HDelayTime: High priority ADC trigger delay. + * This parameter must be between 0x00 to 0xFF. + * @param DelayTime: Regular ADC trigger delay. + * This parameter must be between 0x00 to 0xFF. + * @retval None + ************************************************************************************************************/ +void ADC_DualModeConfig(HT_ADC_TypeDef* HT_ADCn, u32 DUAL_X, u8 HDelayTime, u8 DelayTime) +{ + u32 uTmpReg1, uTmpReg2; + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_DUAL_MODE(DUAL_X)); + + uTmpReg1 = HT_ADCn->CFGR; + uTmpReg2 = (DUAL_MODE_MASK | 0x00FFFF00); + uTmpReg1 &= ~uTmpReg2; + uTmpReg2 = (DUAL_X | HDelayTime << 16 | DelayTime << 8); + uTmpReg1 |= uTmpReg2; + + HT_ADCn->CFGR = uTmpReg1; +} +#endif + +/*********************************************************************************************************//** + * @brief Configure conversion mode and length of list queue for regular group. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_MODE: ADC Cyclic Conversion Mode. + * This parameter can be one of the following values: + * @arg ONE_SHOT_MODE : + * @arg CONTINUOUS_MODE : + * @arg DISCONTINUOUS_MODE : + * @param Length: must between 1 ~ 16 + * @param SubLength: must between 1 ~ 16, only valid for DISCONTINUOUS_MODE. + * @retval None + ************************************************************************************************************/ +void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CONVERSION_MODE(ADC_MODE)); + Assert_Param(IS_ADC_REGULAR_LENGTH(Length)); + if (ADC_MODE == DISCONTINUOUS_MODE) + { + Assert_Param(IS_ADC_REGULAR_SUB_LENGTH(SubLength)); + } + + /* Config cyclic conversion mode and length of list queue and sub length for regular group */ + HT_ADCn->CONV = ((u32)(SubLength - 1) << 16) | ((u32)(Length - 1) << 8) | ADC_MODE | (HT_ADCn->CONV & ADC_ENABLE_BIT); +} + +/*********************************************************************************************************//** + * @brief Configure conversion mode and length of list queue for high priority group. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_MODE: ADC Cyclic Conversion Mode. + * This parameter can be one of the following values: + * @arg ONE_SHOT_MODE : + * @arg CONTINUOUS_MODE : + * @arg DISCONTINUOUS_MODE : + * @param Length: must between 1 ~ 4 + * @param SubLength: must between 1 ~ 4 + * @retval None + ************************************************************************************************************/ +void ADC_HPGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CONVERSION_MODE(ADC_MODE)); + Assert_Param(IS_ADC_HP_LENGTH(Length)); + Assert_Param(IS_ADC_HP_SUB_LENGTH(SubLength)); + + /* Config cyclic conversion mode and length of list queue and sub length for regular group */ + HT_ADCn->HCONV = ((u32)(SubLength - 1) << 16) | ((u32)(Length - 1) << 8) | ADC_MODE; +} + +/*********************************************************************************************************//** + * @brief Configure the corresponding rank in the sequencer and the sampling time for the regular channel + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected, x must between 0 ~ 7 + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param Rank: The rank in the regular group sequencer. + * This parameter must be between 0 to 7. + * @param SampleClock: Number of sampling clocks. + * This parameter must be between 0x00 to 0xFF. + * @retval None + ************************************************************************************************************/ +void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock) +{ + u32 tmpreg1, tmpreg2; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_REGULAR_RANK(Rank)); + Assert_Param(IS_ADC_INPUT_SAMPLING_TIME(SampleClock)); + + /* config sampling clock of correspond ADC input channel */ + HT_ADCn->STR[ADC_CH_n] = SampleClock; + + /* Get the old register value */ + tmpreg1 = HT_ADCn->LST[Rank >> 2]; + /* Calculate the mask to clear */ + tmpreg2 = LST_SEQ_SET << (8 * (Rank & 0x3)); + /* Clear the old SEQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_CH_n << (8 * (Rank & 0x3)); + /* Set the SEQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + HT_ADCn->LST[Rank >> 2] = tmpreg1; +} + +/*********************************************************************************************************//** + * @brief Configure the corresponding rank in the sequencer and the sample time for the High Priority channel + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected, x must between 0 ~ 7 + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param Rank: The rank in the high priority group sequencer. + * This parameter must be between 0 to 3. + * @param SampleClock: Number of sampling clocks. + * This parameter must be between 0x00 to 0xFF. + * @retval None + ************************************************************************************************************/ +void ADC_HPChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, u8 SampleClock) +{ + u32 tmpreg1, tmpreg2; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_HP_RANK(Rank)); + Assert_Param(IS_ADC_INPUT_SAMPLING_TIME(SampleClock)); + + /* config sampling clock of correspond ADC input channel */ + HT_ADCn->STR[ADC_CH_n] = SampleClock; + + /* Get the old register value */ + tmpreg1 = HT_ADCn->HLST; + /* Calculate the mask to clear */ + tmpreg2 = HLST_SEQ_SET << (8 * (Rank & 0x3)); + /* Clear the old SEQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_CH_n << (8 * (Rank & 0x3)); + /* Set the SEQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + HT_ADCn->HLST = tmpreg1; +} + +/*********************************************************************************************************//** + * @brief Configure the ADC trigger source for regular channels conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_TRIG_x: + * This parameter can be one of the following values: + * @arg ADC_TRIG_SOFTWARE : S/W trigger + * @arg ADC_TRIG_EXTI_n : where n can be 0 ~ 15 + * @arg ADC_TRIG_MCTMn_MEVx : where n can be 0 + * @arg ADC_TRIG_MCTM0_DMEVx : where n can be 0* + * @arg ADC_TRIG_MCTM0_MEVxDEVz : where n can be 0 + * @arg ADC_TRIG_MCTMn_MTO : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CHmMEV : where n can be 0, m can be 0 ~ 3 + * @arg ADC_TRIG_MCTMn_CHmDEV : where n can be 0, m can be 0 ~ 3 + * @arg ADC_TRIG_MCTMn_CHmMDEV : where n can be 0, m can be 0 ~ 3 + * @arg ADC_TRIG_MCTMn_CHALLMEV : where n can be 0 + * @arg ADC_TRIG_MCTMn_CHALLDEV : where n can be 0 + * @arg ADC_TRIG_MCTMn_CHALLMDEV : where n can be 0 + * @arg ADC_TRIG_BFTMn : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_MTO : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_CMPn : where n can be 0 ~ 3 + * @retval None + ************************************************************************************************************/ +void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_TRIG(ADC_TRIG_x)); + + /* Config external trigger conversion source of regular group */ + HT_ADCn->TCR = ADC_TRIG_x & 0x0000001F; + HT_ADCn->TSR = ADC_TRIG_x & (~0x0000001F); +} + +/*********************************************************************************************************//** + * @brief Configure the ADC trigger source for high priority channels conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_TRIG_x: + * This parameter can be one of the following values: + * @arg ADC_TRIG_SOFTWARE : S/W trigger + * @arg ADC_TRIG_EXTI_n : where n can be 0 ~ 15 + * @arg ADC_TRIG_MCTMn_MEVx : where n can be 0 + * @arg ADC_TRIG_MCTM0_DMEVx : where n can be 0* + * @arg ADC_TRIG_MCTM0_MEVxDEVz : where n can be 0 + * @arg ADC_TRIG_MCTMn_MTO : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_MCTMn_CHmMEV : where n can be 0, m can be 0 ~ 3 + * @arg ADC_TRIG_MCTMn_CHmDEV : where n can be 0, m can be 0 ~ 3 + * @arg ADC_TRIG_MCTMn_CHmMDEV : where n can be 0, m can be 0 ~ 3 + * @arg ADC_TRIG_MCTMn_CHALLMEV : where n can be 0 + * @arg ADC_TRIG_MCTMn_CHALLDEV : where n can be 0 + * @arg ADC_TRIG_MCTMn_CHALLMDEV : where n can be 0 + * @arg ADC_TRIG_BFTMn : where n can be 0 ~ 1 + * @arg ADC_TRIG_GPTMn_MTO : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH0O : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH1O : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH2O : where n can be 0 + * @arg ADC_TRIG_GPTMn_CH3O : where n can be 0 + * @arg ADC_TRIG_CMPn : where n can be 0 ~ 3 + * @retval None + ************************************************************************************************************/ +void ADC_HPTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_TRIG(ADC_TRIG_x)); + + HT_ADCn->HTCR = ADC_TRIG_x & 0x0000001F; + HT_ADCn->HTSR = ADC_TRIG_x & (~0x0000001F); +} + +#if (!LIBCFG_ADC_NO_OFFSET_REG) +/*********************************************************************************************************//** + * @brief Configure the channel data alignment format. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected + * @arg ADC_CH_OPAn : ADC channel for OPAn + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param ADC_ALIGN_x: ADC_ALIGN_RIGHT or ADC_ALIGN_LEFT + * @retval None + ************************************************************************************************************/ +void ADC_ChannelDataAlign(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ADC_ALIGN_Enum ADC_ALIGN_x) +{ + u32 OFRValue; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_ALIGN(ADC_ALIGN_x)); + + OFRValue = HT_ADCn->OFR[ADC_CH_n] & (~(OFR_ADAL)); + OFRValue |= ADC_ALIGN_x; + + HT_ADCn->OFR[ADC_CH_n] = OFRValue; +} + +/*********************************************************************************************************//** + * @brief Configure the offset value for channel offset cancellation. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected + * @arg ADC_CH_OPAn : ADC channel for OPAn + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param OffsetValue: The offset value + * @retval None + ************************************************************************************************************/ +void ADC_ChannelOffsetValue(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u16 OffsetValue) +{ + u32 OFRValue; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_ADC_OFFSET(OffsetValue)); + + OFRValue = HT_ADCn->OFR[ADC_CH_n] & (~OFR_ADOF_MASK); + OFRValue |= (OffsetValue & 0xFFF); + HT_ADCn->OFR[ADC_CH_n] = OFRValue; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the channel offset cancellation function. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: the ADC channel to configure + * This parameter can be one of the following values: + * @arg ADC_CH_n : ADC Channel x selected + * @arg ADC_CH_OPAn : ADC channel for OPAn + * @arg ADC_CH_GND_VREF : ADC GND VREF selected + * @arg ADC_CH_VDD_VREF : ADC VDD VREF selected + * @param NewState: ENABLE DISABLE + * @retval None + ************************************************************************************************************/ +void ADC_ChannelOffsetCmd(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, ControlStatus NewState) +{ + u32 OFRValue; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_CHANNEL(ADC_CH_n)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + OFRValue = HT_ADCn->OFR[ADC_CH_n] & (~(OFR_ADOFE)); + + if (NewState == ENABLE) + { + OFRValue |= OFR_ADOFE; + } + + HT_ADCn->OFR[ADC_CH_n] = OFRValue; +} +#endif + +#if (LIBCFG_ADC_TRIG_DELAY) +/*********************************************************************************************************//** + * @brief Configure the ADC Trigger Delay. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. (ADC1 only) + * @param HDelayTime: High priority ADC trigger delay. + * This parameter must be between 0x00 to 0xFF. + * @param DelayTime: Regular ADC trigger delay. + * This parameter must be between 0x00 to 0xFF. + * @retval None + ************************************************************************************************************/ +void ADC_TrigDelayConfig(HT_ADC_TypeDef* HT_ADCn, u8 HDelayTime, u8 DelayTime) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + + HT_ADCn->CFGR = (HDelayTime << 16 | DelayTime << 8); +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable software start of the regular channel conversion of the selected ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Start Conversion */ + if (NewState != DISABLE) + { + HT_ADCn->TSR |= TCR_SC_SET; + } + else + { + HT_ADCn->TSR &= ~TCR_SC_SET; + } +} + +/*********************************************************************************************************//** + * @brief Enable or Disable software start of the high priority channel conversion of the selected ADC. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_HPSoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + /* Start Conversion */ + if (NewState != DISABLE) + { + HT_ADCn->HTSR |= HTCR_SC_SET; + } + else + { + HT_ADCn->HTSR &= ~HTCR_SC_SET; + } +} + +/*********************************************************************************************************//** + * @brief Return the result of ADC regular channel conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_REGULAR_DATAn: where n can be 0 ~ 7 + * @retval The Value of data conversion. + ************************************************************************************************************/ +u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_REGULAR_DATA(ADC_REGULAR_DATAn)); + + return ((u16)HT_ADCn->DR[ADC_REGULAR_DATAn]); +} + +/*********************************************************************************************************//** + * @brief Return the result of ADC high priority channel conversion. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_HP_DATAn: where x can be 0 ~ 3 + * @retval The Value of data conversion. + ************************************************************************************************************/ +u16 ADC_GetHPConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_HP_DATAn) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_HP_DATA(ADC_HP_DATAn)); + + return ((u16)HT_ADCn->HDR[ADC_HP_DATAn]); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified ADC interrupts. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the ADC interrupt sources that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_HP_SINGLE_EOC : + * @arg ADC_INT_HP_SUB_GROUP_EOC : + * @arg ADC_INT_HP_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_HP_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->IER |= ADC_INT_x; + } + else + { + HT_ADCn->IER &= ~ADC_INT_x; + } +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC interrupt has occurred. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt status to check. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_HP_SINGLE_EOC : + * @arg ADC_INT_HP_SUB_GROUP_EOC : + * @arg ADC_INT_HP_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_HP_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + if ((HT_ADCn->ISR & ADC_INT_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Clear the ADC interrupt pending bits. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_INT_x: Specify the interrupt pending bits to be cleared. + * This parameter can be any combination of the following values: + * @arg ADC_INT_SINGLE_EOC : + * @arg ADC_INT_SUB_GROUP_EOC : + * @arg ADC_INT_CYCLE_EOC : + * @arg ADC_INT_HP_SINGLE_EOC : + * @arg ADC_INT_HP_SUB_GROUP_EOC : + * @arg ADC_INT_HP_CYCLE_EOC : + * @arg ADC_INT_DATA_OVERWRITE : + * @arg ADC_INT_HP_DATA_OVERWRITE : + * @arg ADC_INT_AWD_LOWER : + * @arg ADC_INT_AWD_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INT(ADC_INT_x)); + + HT_ADCn->ICLR = ADC_INT_x; +} + +/*********************************************************************************************************//** + * @brief Check whether the specified ADC flag has been set. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_FLAG_x: Specify the flag to check. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_SINGLE_EOC : + * @arg ADC_FLAG_SUB_GROUP_EOC : + * @arg ADC_FLAG_CYCLE_EOC : + * @arg ADC_FLAG_HP_SINGLE_EOC : + * @arg ADC_FLAG_HP_SUB_GROUP_EOC : + * @arg ADC_FLAG_HP_CYCLE_EOC : + * @arg ADC_FLAG_DATA_OVERWRITE : + * @arg ADC_FLAG_HP_DATA_OVERWRITE : + * @arg ADC_FLAG_AWD_LOWER : + * @arg ADC_FLAG_AWD_UPPER : + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x) +{ + FlagStatus Status; + + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_FLAG(ADC_FLAG_x)); + + if ((HT_ADCn->IRAW & ADC_FLAG_x) != RESET) + { + Status = SET; + } + else + { + Status = RESET; + } + + return Status; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable Lower/Upper threshold warning of the analog watchdog on single/all channels. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_AWD_x: + * This parameter can be any combination of the following values: + * @arg ADC_AWD_DISABLE : + * @arg ADC_AWD_ALL_LOWER : + * @arg ADC_AWD_ALL_UPPER : + * @arg ADC_AWD_ALL_LOWER_UPPER : + * @arg ADC_AWD_SINGLE_LOWER : + * @arg ADC_AWD_SINGLE_UPPER : + * @arg ADC_AWD_SINGLE_LOWER_UPPER : + * @retval None + ************************************************************************************************************/ +void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_AWD(ADC_AWD_x)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFFFF8) | ADC_AWD_x; +} + +/*********************************************************************************************************//** + * @brief Configure the analog watchdog that guards single channel. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_CH_n: where n must between 0 ~ 7 + * @retval None + ************************************************************************************************************/ +void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_INPUT_CHANNEL(ADC_CH_n)); + + HT_ADCn->WCR = (HT_ADCn->WCR & 0xFFFFF0FF) | ((u32)ADC_CH_n << 8); +} + +/*********************************************************************************************************//** + * @brief Configure the high and low thresholds of the analog watchdog. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param UPPER: must between 0x0000 ~ 0x0FFF + * @param LOWER: must between 0x0000 ~ 0x0FFF + * @retval None + ************************************************************************************************************/ +void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_THRESHOLD(UPPER)); + Assert_Param(IS_ADC_THRESHOLD(LOWER)); + + HT_ADCn->LTR = LOWER; + HT_ADCn->UTR = UPPER; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified PDMA request. + * @param HT_ADCn: where HT_ADCn is the selected ADC from the ADC peripherals. + * @param ADC_PDMA_x: Specify the ADC PDMA request that is to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_PDMA_REGULAR_SINGLE : + * @arg ADC_PDMA_REGULAR_SUBGROUP : + * @arg ADC_PDMA_REGULAR_CYCLE : + * @arg ADC_PDMA_HP_SINGLE : + * @arg ADC_PDMA_HP_SUBGROUP : + * @arg ADC_PDMA_HP_CYCLE : + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_ADC(HT_ADCn)); + Assert_Param(IS_ADC_PDMA(ADC_PDMA_x)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + if (NewState != DISABLE) + { + HT_ADCn->PDMAR |= ADC_PDMA_x; + } + else + { + HT_ADCn->PDMAR &= ~ADC_PDMA_x; + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_opa.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_opa.c new file mode 100644 index 00000000000..6df13c0c01f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_opa.c @@ -0,0 +1,456 @@ + /*********************************************************************************************************//** + * @file ht32f65xxx_66xxx_opa.c + * @version $Rev:: 6932 $ + * @date $Date:: 2023-05-11 #$ + * @brief This file provides all the OPA firmware functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f65xxx_66xxx_opa.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup OPA OPA + * @brief OPA driver modules + * @{ + */ + + +/* Private define ------------------------------------------------------------------------------------------*/ +/** @defgroup OPA_Private_Define OPA private definitions + * @{ + */ +#define OPA_ENABLE (0x00000001ul) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +static u32 gOPAUnProtectKey = 0; + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup OPA_Exported_Functions OPA exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Deinitialize the OPA peripheral registers to their default reset values. + * @retval None + ************************************************************************************************************/ +void OPA_DeInit(void) +{ + RSTCU_PeripReset_TypeDef RSTCUReset = {{0}}; + + RSTCUReset.Bit.OPA = 1; + RSTCU_PeripReset(RSTCUReset, ENABLE); +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the specified OPA peripheral. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals, x can be 0 or 1. + * @param NewState: new state of the HT_OPAn peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None +************************************************************************************************************/ +void OPA_Cmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState) +{ + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + HT_OPAn->CR = gOPAUnProtectKey; + + if (NewState != DISABLE) + { + /* Enable the selected HT_OPAn peripheral */ + HT_OPAn->CR |= OPA_ENABLE; + } + else + { + /* Disable the selected HT_OPAn peripheral */ + HT_OPAn->CR &= ~(u32)OPA_ENABLE; + } +} + +/*********************************************************************************************************//** + * @brief Set the unprotect key. + * @param uUnProtectKey: protect key, shall be OPA_UNPROTECT_KEY + * @retval None + ************************************************************************************************************/ +void OPA_SetUnProtectKey(u32 uUnProtectKey) +{ + gOPAUnProtectKey = uUnProtectKey << 16; +} + +/*********************************************************************************************************//** + * @brief Protect the selected OPA before setting the OPA Control Register. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @retval None + ************************************************************************************************************/ +void OPA_ProtectConfig(HT_OPA_TypeDef* HT_OPAn) +{ + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + + /* Write any value to bit 16 ~ 31 (PROTECT) and keep the other control bir */ + HT_OPAn->CR = HT_OPAn->CR; +} + +/*********************************************************************************************************//** + * @brief Unprotect the selected OPA before setting the OPA Control Register. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @retval None + ************************************************************************************************************/ +void OPA_UnprotectConfig(HT_OPA_TypeDef* HT_OPAn) +{ + u32 CRValue; + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + + /* Set the unlock code corresponding to selected OPA */ + CRValue = HT_OPAn->CR & 0x0000FFFF; + HT_OPAn->CR = gOPAUnProtectKey | CRValue; +} + +#if (LIBCFG_OPA_V2) +/*********************************************************************************************************//** + * @brief Initialize the OPA peripheral according to the specified parameters in the OPA_InitStruct. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param OPA_InitStruct: pointer to a OPA_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void OPA_Init(HT_OPA_TypeDef* HT_OPAn, OPA_InitTypeDef* OPA_InitStruct) +{ + /* !!! NOTICE !!! + Must call the following functions first. + OPA_SetUnProtectKey(OPA_UNPROTECT_KEY); + OPA_UnprotectConfig(); + */ + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_OPA_ScalerEnable(OPA_InitStruct->OPA_ScalerEnable)); + Assert_Param(IS_OPA_ExtPinEnable(OPA_InitStruct->OPA_ExternalPinEnable)); + #if (LIBCFG_OPA_PGA) + Assert_Param(IS_OPA_PGAEnable(OPA_InitStruct->OPA_PGAEnable)); + Assert_Param(IS_OPA_UnitGainEnable(OPA_InitStruct->OPA_UnitGainEnable)); + Assert_Param(IS_OPA_PGA_SEL(OPA_InitStruct->OPA_PGAGain)); + #endif + + #if (LIBCFG_OPA_PGA) + /* avoid both PGA and unit gain active at the same time */ + if (OPA_InitStruct->OPA_UnitGainEnable == OPA_UNITGAIN_ENABLE) + { + OPA_InitStruct->OPA_PGAEnable = OPA_PGA_DISABLE; + } + #endif + + #if (LIBCFG_OPA_PGA) + HT_OPAn->CR = OPA_InitStruct->OPA_ScalerEnable | OPA_InitStruct->OPA_PGAGain | \ + OPA_InitStruct->OPA_ExternalPinEnable | OPA_InitStruct->OPA_PGAEnable | \ + OPA_InitStruct->OPA_UnitGainEnable; + #else + HT_OPAn->CR = OPA_InitStruct->OPA_ScalerEnable | \ + OPA_InitStruct->OPA_ExternalPinEnable; + #endif +} + +/*********************************************************************************************************//** + * @brief Fill each OPA_InitStruct member with its default value. + * @param OPA_InitStruct: pointer to an OPA_InitTypeDef structure. + * @retval None + ************************************************************************************************************/ +void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct) +{ + /* OPA_InitStruct members default value */ + OPA_InitStruct->OPA_ScalerEnable = OPA_SCALER_DISABLE; + OPA_InitStruct->OPA_ExternalPinEnable = OPA_ExternalPin_DISABLE; + #if (LIBCFG_OPA_PGA) + OPA_InitStruct->OPA_PGAEnable = OPA_PGA_DISABLE; + OPA_InitStruct->OPA_UnitGainEnable = OPA_UNITGAIN_DISABLE; + OPA_InitStruct->OPA_PGAGain = PGA_GAIN_6; + #endif +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the OPA External Input. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void OPA_ExternalInputCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState) +{ + u32 OPA_CR = (u32)(&HT_OPAn->CR); + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + HT_OPAn->CR = gOPAUnProtectKey; + + if (NewState != DISABLE) + { + SetBit_BB(OPA_CR, 3); + } + else + { + ResetBit_BB(OPA_CR, 3); + } +} + +#if (LIBCFG_OPA_PGA) +/*********************************************************************************************************//** + * @brief Enable or Disable the Unit Gain. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void OPA_UnitGainCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState) +{ + u32 OPA_CR = (u32)(&HT_OPAn->CR); + u32 CRValue; + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + CRValue = HT_OPAn->CR & (~(0x06UL)); // reset unit gain & PGA + + if (NewState == ENABLE) + { + CRValue |= 0x2; + } + + HT_OPAn->CR = gOPAUnProtectKey; + HT_OPAn->CR = CRValue; +} + +/*********************************************************************************************************//** + * @brief Enable or Disable the PGA. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void OPA_PGACmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState) +{ + u32 OPA_CR = (u32)(&HT_OPAn->CR); + u32 CRValue; + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + CRValue = HT_OPAn->CR & (~(0x06UL)); // reset unit gain & PGA + + if (NewState == ENABLE) + { + CRValue |= 0x4; // set PGA + } + + HT_OPAn->CR = gOPAUnProtectKey; + HT_OPAn->CR = CRValue; +} + +/*********************************************************************************************************//** + * @brief Configure the Gain Selection for the PGA. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param GAIN_SEL : + * This parameter can be one of the following value: + * @arg PGA_GAIN_6 : + * @arg PGA_GAIN_8 : + * @arg PGA_GAIN_12 : + * @arg PGA_GAIN_16 : + * @arg PGA_GAIN_24 : + * @arg PGA_GAIN_32 : + * @arg PGA_GAIN_48 : + * @arg PGA_GAIN_64 : + * @arg PGA_GAIN_5 : + * @arg PGA_GAIN_7 : + * @arg PGA_GAIN_11 : + * @arg PGA_GAIN_15 : + * @arg PGA_GAIN_23 : + * @arg PGA_GAIN_31 : + * @arg PGA_GAIN_47 : + * @arg PGA_GAIN_63 : + * @retval None + ************************************************************************************************************/ +void OPA_PGAGain(HT_OPA_TypeDef* HT_OPAn, u8 bGAIN_SEL) +{ + u32 CRValue; + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_OPA_PGA_SEL(bGAIN_SEL)); + + CRValue = HT_OPAn->CR & (~0x70UL); + CRValue |= (u32)bGAIN_SEL << 4; + + HT_OPAn->CR = gOPAUnProtectKey; + HT_OPAn->CR = CRValue; +} +#endif + +/*********************************************************************************************************//** + * @brief Enable or Disable the 10bit Scaler. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param NewState: This parameter can be ENABLE or DISABLE. + * @retval None + ************************************************************************************************************/ +void OPA_ScalerCmd(HT_OPA_TypeDef* HT_OPAn, ControlStatus NewState) +{ + u32 OPA_CR = (u32)(&HT_OPAn->CR); + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_CONTROL_STATUS(NewState)); + + HT_OPAn->CR = gOPAUnProtectKey; + + if (NewState != DISABLE) + { + SetBit_BB(OPA_CR, 8); + } + else + { + ResetBit_BB(OPA_CR, 8); + } +} + +/*********************************************************************************************************//** + * @brief Set the specified reference value in the data register of the scaler. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param Scaler_Value: value to be loaded in the selected data register. + * @retval None + ************************************************************************************************************/ +void OPA_SetScalerValue(HT_OPA_TypeDef* HT_OPAn, u32 Scaler_Value) +{ + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_OPA_SCALER_VALUE(Scaler_Value)); + + HT_OPAn->DAC = Scaler_Value; +} + +/*********************************************************************************************************//** + * @brief Get the output status of the specified HT_OPAn. + * @param HT_OPAn: where CMPx is the selected OPA from the OPA peripherals. + * @retval SET or RESET + ************************************************************************************************************/ +FlagStatus OPA_GetOutputStatus(HT_OPA_TypeDef* HT_OPAn) +{ + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + + if ((HT_OPAn-> CR & OPA_OUTPUT_HIGH) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/*********************************************************************************************************//** + * @brief Select OPA Operation Mode. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param MODE: + * This parameter can be one of the following value: + * @arg OPA_OFFSET_CALIBRATION_MODE : + * @arg OPA_NORMAL_MODE : + * @retval None + ************************************************************************************************************/ +void OPA_OFMMode(HT_OPA_TypeDef* HT_OPAn, u8 MODE) +{ + u32 OPA_VOS = (u32)(&HT_OPAn->VOS); + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_OPA_OFMMODE(MODE)); + + if (MODE != OPA_NORMAL_MODE) + { + SetBit_BB(OPA_VOS, 7); + } + else + { + ResetBit_BB(OPA_VOS, 7); + } +} + +/*********************************************************************************************************//** + * @brief Select OPA Operation Mode. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param SEL: + * This parameter can be one of the following value: + * @arg OPA_INPUT_OFFSET_INN : + * @arg OPA_INPUT_OFFSET_INP : + * @retval None + ************************************************************************************************************/ +void OPA_OFM_InputOffsetReferenceSelect(HT_OPA_TypeDef* HT_OPAn, u8 SEL) +{ + u32 OPA_VOS = (u32)(&HT_OPAn->VOS); + + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_OPA_INPUTOFFSET_SEL(SEL)); + + if (SEL != OPA_INPUT_OFFSET_INN) + { + SetBit_BB(OPA_VOS, 6); + } + else + { + ResetBit_BB(OPA_VOS, 6); + } +} + +/*********************************************************************************************************//** + * @brief Configure the input offset calibration voltage for the OPA. + * @param HT_OPAn: where HT_OPAn is the selected OPA from the OPA peripherals. + * @param Data: Set the input offset calibration voltage value. + * @retval None + ************************************************************************************************************/ +void OPA_SetInputOffsetVoltage(HT_OPA_TypeDef* HT_OPAn, u8 Data) +{ + /* Check the parameters */ + Assert_Param(IS_OPA(HT_OPAn)); + Assert_Param(IS_OPA_INPUTOFFSET_VALUE(Data)); + + HT_OPAn->VOS = (HT_OPAn->VOS & 0xFFFFFF70) | (Data & 0x1F); +} +#endif +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_pga.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_pga.c new file mode 100644 index 00000000000..6dacca7f49f --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f65xxx_66xxx_pga.c @@ -0,0 +1,49 @@ +/*********************************************************************************************************//** + * @file ht32f65xxx_66xxx_pga.c + * @version $Rev:: 6914 $ + * @date $Date:: 2023-05-10 #$ + * @brief This file provides all the PGA firmware functions. (temporary file, not finish/support yet). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f65xxx_66xxx_pga.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup PGA PGA + * @brief PGA driver modules + * @{ + */ + + + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_cordic.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_cordic.c new file mode 100644 index 00000000000..724e166fbed --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_cordic.c @@ -0,0 +1,49 @@ +/*********************************************************************************************************//** + * @file ht32f66xxx_cordic.c + * @version $Rev:: 6914 $ + * @date $Date:: 2023-05-10 #$ + * @brief This file provides all the CORDIC firmware functions. (temporary file, not finish/support yet). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f66xxx_cordic.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup CORDIC CORDIC + * @brief CORDIC driver modules + * @{ + */ + + + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_pid.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_pid.c new file mode 100644 index 00000000000..d956f5fcf92 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ht32f66xxx_pid.c @@ -0,0 +1,49 @@ +/*********************************************************************************************************//** + * @file ht32f66xxx_pid.c + * @version $Rev:: 6914 $ + * @date $Date:: 2023-05-10 #$ + * @brief This file provides all the PID firmware functions. (temporary file, not finish/support yet). + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32f66xxx_pid.h" + +/** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver + * @{ + */ + +/** @defgroup PID PID + * @brief PID driver modules + * @{ + */ + + + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/printf.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/printf.c new file mode 100644 index 00000000000..4f3515330c2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/printf.c @@ -0,0 +1,390 @@ +/*********************************************************************************************************//** + * @file printf.c + * @version $Rev:: 93 $ + * @date $Date:: 2015-11-24 #$ + * @brief Print functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup PRINTF printf re-implementation + * @brief printf related functions + * @{ + */ + + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup PRINTF_Private_Macro printf private macros + * @{ + */ +#define vaStart(list, param) list = (char*)((int)¶m + sizeof(param)) +#define vaArg(list, type) ((type *)(list += sizeof(type)))[-1] +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static const char *FormatItem(const char *f, int a); +static void PutRepChar(const char c, int count); +static int PutString(const char *pString); +static int PutStringReverse(const char *pString, int index); +static void PutNumber(int value, int radix, int width, char fill); + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup PRINTF_Exported_Functions printf exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Print function. + * @param f: Format string. + * @retval String length. + ************************************************************************************************************/ +signed int printf(const char *f, ...) +{ + char *argP; + int i = 0; + + vaStart(argP, f); + while (*f) + { + if (*f == '%') + { + f = FormatItem(f + 1, vaArg(argP, int)); + } + else + { + fputc(*f++, (FILE *)1); + } + i++; + } + return i; +} + +/*********************************************************************************************************//** + * @brief Put string. + * @param pString: String. + * @retval String length. + ************************************************************************************************************/ +signed int puts(const char *pString) +{ + int i; + i = PutString(pString); + fputc('\n', (FILE *)1); + return i; +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup PRINTF_Private_Function printf private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief Format item for print function. + * @param f: Format string. + * @param a: Length of format string. + * @retval Point of string. + ************************************************************************************************************/ +static const char *FormatItem(const char *f, int a) +{ + char c; + int fieldwidth = 0; + int leftjust = FALSE; + int radix = 0; + char fill = ' '; + int i; + + if (*f == '0') + { + fill = '0'; + } + + while ((c = *f++) != 0) + { + if (c >= '0' && c <= '9') + { + fieldwidth = (fieldwidth * 10) + (c - '0'); + } + else + { + switch (c) + { + case '\000': + { + return (--f); + } + case '%': + { + fputc('%', (FILE *)1); + return (f); + } + case '-': + { + leftjust = TRUE; + break; + } + case 'c': + { + if (leftjust) + { + fputc(a & 0x7f, (FILE *)f); + } + if (fieldwidth > 0) + { + PutRepChar(fill, fieldwidth - 1); + } + if (!leftjust) + { + fputc(a & 0x7f, (FILE *)f); + return (f); + } + } + case 's': + { + i = 0; + while (*((char *)(a + i)) !='\0' ) + { + i++; + } + + if (leftjust) + { + PutString((char *)a); + } + + if (fieldwidth > i ) + { + PutRepChar(fill, fieldwidth - i); + } + + if (!leftjust) + { + PutString((char *)a); + } + return (f); + } + case 'l': + { + radix = -10; + f++; + break; + } + case 'd': + case 'i': + { + radix = -10; + break; + } + case 'u': + { + radix = 10; + break; + } + case 'x': + case 'X': + { + radix = 16; + break; + } + case 'o': + { + radix = 8; + break; + } + default: + { + radix = 3; + break; + } + } + } + if (radix) + { + break; + } + } + + if (leftjust) + { + fieldwidth = -fieldwidth; + } + + PutNumber(a, radix, fieldwidth, fill); + + return (f); +} + +/*********************************************************************************************************//** + * @brief Put repeat character. + * @param c: Character. + * @param count: Repeat count + ************************************************************************************************************/ +static void PutRepChar(const char c, int count) +{ + while (count--) + { + fputc(c, (FILE *)1); + } +} + +/*********************************************************************************************************//** + * @brief Put string. + * @param pString: String. + * @retval String length. + ************************************************************************************************************/ +static int PutString(const char *pString) +{ + int i = 0; + while (*pString != '\0') + { + fputc(*pString, (FILE *)1); + pString++; + i++; + } + + return i; +} + +/*********************************************************************************************************//** + * @brief Put string in reversed order. + * @param pString: String. + * @param index: String length + * @retval String length. + ************************************************************************************************************/ +static int PutStringReverse(const char *pString, int index) +{ + int i = 0; + while ((index--) > 0) + { + fputc(pString[index], (FILE *)1); + i++; + } + return i; +} + +/*********************************************************************************************************//** + * @brief Put number. + * @param value: Value of number. + * @param radix: Radix of number. + * @param width: Width of number. + * @param fill: fill character. + ************************************************************************************************************/ +static void PutNumber(int value, int radix, int width, char fill) +{ + char buffer[8]; + int bi = 0; + unsigned int uvalue; + unsigned short digit; + unsigned short left = FALSE; + unsigned short negative = FALSE; + + if (fill == 0) + { + fill = ' '; + } + + if (width < 0) + { + width = -width; + left = TRUE; + } + + if (width < 0 || width > 80) + { + width = 0; + } + + if (radix < 0) + { + radix = -radix; + if (value < 0) + { + negative = TRUE; + value = -value; + } + } + + uvalue = value; + + do + { + if (radix != 16) + { + digit = uvalue % radix; + uvalue = uvalue / radix; + } + else + { + digit = uvalue & 0xf; + uvalue = uvalue >> 4; + } + buffer[bi] = digit + ((digit <= 9) ? '0' : ('A' - 10)); + bi++; + } + while (uvalue != 0); + + if (negative) + { + buffer[bi] = '-'; + bi += 1; + } + + if (width <= bi) + { + PutStringReverse(buffer, bi); + } + else + { + width -= bi; + if (!left) + { + PutRepChar(fill, width); + } + + PutStringReverse(buffer, bi); + + if (left) + { + PutRepChar(fill, width); + } + } +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/syscalls.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/syscalls.c new file mode 100644 index 00000000000..566ad8da784 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/syscalls.c @@ -0,0 +1,127 @@ +/*********************************************************************************************************//** + * @file syscalls.c + * @version $Rev:: 6830 $ + * @date $Date:: 2023-03-27 #$ + * @brief Implementation of system call related functions. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include +#include +#include +#include + +/** @addtogroup HT32_Peripheral_Driver HT32 Peripheral Driver + * @{ + */ + +/** @defgroup SYSCALLS System call functions + * @brief System call functions for GNU toolchain + * @{ + */ + + +/* Global variables ----------------------------------------------------------------------------------------*/ +/** @defgroup SYSCALLS_Global_Variable System call global variables + * @{ + */ +#undef errno +extern int errno; +extern int _end; +/** + * @} + */ + +/* Global functions ----------------------------------------------------------------------------------------*/ +/** @defgroup SYSCALLS_Exported_Functions System call exported functions + * @{ + */ +caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char *prev_heap; + + if (heap == NULL) + { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t) prev_heap; +} + +int link(char *old, char *new) { +return -1; +} + +int _close(int fd) +{ + return -1; +} + +int _fstat(int fd, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int fd) +{ + return 1; +} + +int _lseek(int fd, int ptr, int dir) +{ + return 0; +} + +int _read(int fd, char *ptr, int len) +{ + return 0; +} + +int _write(int fd, char *ptr, int len) +{ + return len; +} + +void abort(void) +{ + /* Abort called */ + while (1); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.c new file mode 100644 index 00000000000..928fb2ef332 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.c @@ -0,0 +1,426 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_class.c + * @version $Rev:: 1234 $ + * @date $Date:: 2016-10-25 #$ + * @brief The USB Device Class. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_usbd_core.h" +#include "ht32_usbd_class.h" + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDClass USB Device Class + * @brief USB Device Class + * @{ + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Private_Define USB Device Class private definitions + * @{ + */ +#define CLASS_REQ_01_CMD1 (u16)(0x1 << 8) +#define CLASS_REQ_02_CMD2 (u16)(0x2 << 8) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void USBDClass_MainRoutine(u32 uPara); +static void USBDClass_ClassProcess(void); +static void USBDClass_EPT1Process(void); +static void USBDClass_EPT2Process(void); + +static void USBDClass_Reset(u32 uPara); +static void USBDClass_StartOfFrame(u32 uPara); + +static void USBDClass_Standard_GetDescriptor(USBDCore_Device_TypeDef *pDev); +static void USBDClass_Standard_SetInterface(USBDCore_Device_TypeDef *pDev); +static void USBDClass_Standard_GetInterface(USBDCore_Device_TypeDef *pDev); + +static void USBDClass_Request(USBDCore_Device_TypeDef *pDev); + +static void USBDClass_CMD1(USBDCore_Device_TypeDef *pDev); +static void USBDClass_CMD2(USBDCore_Device_TypeDef *pDev); + +static void USBDClass_Endpoint1(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint2(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint3(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint4(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint5(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint6(USBD_EPTn_Enum EPTn); +static void USBDClass_Endpoint7(USBD_EPTn_Enum EPTn); + +/* Global Function -----------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Exported_Functions USB Device Class exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Class initialization. + * @param pClass: pointer of USBDCore_Class_TypeDef + * @retval None + ***********************************************************************************************************/ +void USBDClass_Init(USBDCore_Class_TypeDef *pClass) +{ + pClass->CallBack_MainRoutine.func = USBDClass_MainRoutine; + //pClass->CallBack_MainRoutine.uPara = (u32)NULL; + + pClass->CallBack_Reset.func = USBDClass_Reset; + pClass->CallBack_Reset.uPara = (u32)NULL; + + pClass->CallBack_StartOfFrame.func = USBDClass_StartOfFrame; + pClass->CallBack_StartOfFrame.uPara = (u32)NULL; + + pClass->CallBack_ClassGetDescriptor = USBDClass_Standard_GetDescriptor; + pClass->CallBack_ClassSetInterface = USBDClass_Standard_SetInterface; + pClass->CallBack_ClassGetInterface = USBDClass_Standard_GetInterface; + + pClass->CallBack_ClassRequest = USBDClass_Request; + pClass->CallBack_EPTn[1] = USBDClass_Endpoint1; + pClass->CallBack_EPTn[2] = USBDClass_Endpoint2; + pClass->CallBack_EPTn[3] = USBDClass_Endpoint3; + pClass->CallBack_EPTn[4] = USBDClass_Endpoint4; + pClass->CallBack_EPTn[5] = USBDClass_Endpoint5; + pClass->CallBack_EPTn[6] = USBDClass_Endpoint6; + pClass->CallBack_EPTn[7] = USBDClass_Endpoint7; + + #ifdef RETARGET_IS_USB + pClass->CallBack_EPTn[RETARGET_RX_EPT] = SERIAL_USBDClass_RXHandler; + #endif + + return; +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Private_Functions USB Device Class private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Class main routine. + * @param uPara: Parameter for Class main routine + * @retval None + ***********************************************************************************************************/ +static void USBDClass_MainRoutine(u32 uPara) +{ + USBDClass_ClassProcess(); + USBDClass_EPT1INProcess(); + USBDClass_EPT2OUTProcess(); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Process for application. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_ClassProcess(void) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint 1 Process for application. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_EPT1Process(void) +{ + if (gIsEP1 == TRUE) + { + gIsEP1 = FALSE; + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint 2 Process for application. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_EPT2Process(void) +{ + if (gIsEP2 == TRUE) + { + gIsEP2 = FALSE; + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Reset. + * @param uPara: Parameter for Class Reset. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Reset(u32 uPara) +{ + +} + +/*********************************************************************************************************//** + * @brief USB Class Start of Frame. + * @param uPara: Parameter for Class Start of Frame. + * @retval None + ***********************************************************************************************************/ +static void USBDClass_StartOfFrame(u32 uPara) +{ + +} + +/*********************************************************************************************************//** + * @brief USB Device Class Request + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Request(USBDCore_Device_TypeDef *pDev) +{ + u16 uUSBCmd = *((u16 *)(&(pDev->Request))); + +#ifdef RETARGET_IS_USB + SERIAL_USBDClass_Request(pDev); +#endif + + switch (uUSBCmd) + { + /*------------------------------------------------------------------------------------------------------*/ + /* | bRequest | Data transfer direction | Type | Recipient | Data */ + /*------------------------------------------------------------------------------------------------------*/ + + /*------------------------------------------------------------------------------------------------------*/ + /* | 01_CMD1 | 80_Device-to-Host | 20_Class Request | 1_Interface | 01A1h */ + /*------------------------------------------------------------------------------------------------------*/ + case (CLASS_REQ_01_CMDID0 | REQ_DIR_01_D2H | REQ_TYPE_01_CLS | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld CMD0\t[%02d][%02d]\r\n", __DBG_USBCount, pDev->Request.wValueH, pDev->Request.wLength ); + USBDClass_RequestCMD1(pDev); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 02_CMD2 | 00_Host-to-Device | 20_Class Request | 1_Interface | 0221h */ + /*------------------------------------------------------------------------------------------------------*/ + case (CLASS_REQ_02_GET_IDLE | REQ_DIR_00_H2D | REQ_TYPE_01_CLS | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld CMD1\t[%02d][%02d]\r\n", __DBG_USBCount, pDev->Request.wValueH, pDev->Request.wLength ); + USBDClass_RequestCMD2(pDev); + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Class Standard Request - GET_DESCRIPTOR + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Standard_GetDescriptor(USBDCore_Device_TypeDef *pDev) +{ + u32 type = pDev->Request.wValueH; + + switch (type) + { + case DESC_TYPE_01_XXX + { + pDev->Transfer.pData = (uc8 *)(__BUFFER_POINTER__); + pDev->Transfer.sByteLength = DESC_LEN_XXX; + pDev->Transfer.Action = USB_ACTION_DATAIN; + break; + } + case DESC_TYPE_02_XXX: + { + pDev->Transfer.pData = (uc8 *)(__BUFFER_POINTER__); + pDev->Transfer.sByteLength = DESC_LEN_XXX; + pDev->Transfer.Action = USB_ACTION_DATAIN; + break; + } + } /* switch (type) */ + + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Class Standard Request - SET_INTERFACE + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Standard_SetInterface(USBDCore_Device_TypeDef *pDev) +{ + +} + +/*********************************************************************************************************//** + * @brief USB Device Class Standard Request - GET_INTERFACE + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Standard_GetInterface(USBDCore_Device_TypeDef *pDev) +{ + +} + + + +/*********************************************************************************************************//** + * @brief USB Device Class Request - CMD1 + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_CMD1(USBDCore_Device_TypeDef *pDev) +{ + /* Add your own Class request function here.... + For example.... + + u32 uReportID = pDev->Request.wValueL; + u32 uInterface = pDev->Request.wIndex; + + pDev->Transfer.pData = (uc8 *)&(__IDLE_DURATION_BUFFER[uReportID]); + pDev->Transfer.sByteLength = 1; + pDev->Transfer.Action= USB_ACTION_DATAIN; + + */ + return; +} + +/*********************************************************************************************************//** + * @brief USB Device Class Request - CMD2 + * @param pDev: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void USBDClass_CMD2(USBDCore_Device_TypeDef *pDev) +{ + /* Add your own Class request function here.... + For example.... + + u32 uReportID = pDev->Request.wValueL; + u32 uInterface = pDev->Request.wIndex; + + pDev->Transfer.pData = (uc8 *)&(__IDLE_DURATION_BUFFER[uReportID]); + pDev->Transfer.sByteLength = 1; + pDev->Transfer.Action= USB_ACTION_DATAIN; + + */ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint1(USBD_EPTn_Enum EPTn) +{ + gIsEP1 = TRUE; + + __DBG_USBPrintf("%06ld EP1\t[%02d]", ++__DBG_USBCount, (int)USBDCore_EPTGetBufferLen(EPTn)); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint2(USBD_EPTn_Enum EPTn) +{ + gIsEP2 = TRUE; + __DBG_USBPrintf("%06ld EP2\t[%02d]", ++__DBG_USBCount, (int)USBDCore_EPTGetBufferLen(EPTn)); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint3(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint4(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint5(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint6(USBD_EPTn_Enum EPTn) +{ + return; +} + +/*********************************************************************************************************//** + * @brief USB Class Endpoint handler + * @param EPTn: USB Endpoint number + * @arg USBD_EPT0 ~ USBD_EPT7 + * @retval None + ***********************************************************************************************************/ +static void USBDClass_Endpoint7(USBD_EPTn_Enum EPTn) +{ + return; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.h new file mode 100644 index 00000000000..2fe2598beee --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_class.h @@ -0,0 +1,87 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_class.h + * @version $Rev:: 47 $ + * @date $Date:: 2015-11-18 #$ + * @brief The header file of USB Device Class. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_USBD_CLASS_H +#define __HT32_USBD_CLASS_H + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDClass USB Device Class + * @brief USB Device Class + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Private_Define USB Device Class private definitions + * @{ + */ +/* For ht32_usbd_descriptor.c */ +#define CLASS_INF_CLASS (DESC_CLASS_03_XXX) +#define CLASS_INF_SUBCLASS (HID_SUBCLASS_00_NONE) +#define CLASS_INF_PTCO (HID_PROTOCOL_00_NONE) + +/* HID related definition */ +#define DESC_LEN_XXX ((u32)(9)) +#define DESC_LEN_XXX ((u16)(47)) + +#define DESC_TYPE_01_XXX (0x01) +#define DESC_TYPE_02_XXX (0x02) + +#define HID_SUBCLASS_00_NONE (0x00) +#define HID_SUBCLASS_01_BOOT (0x01) + +#define HID_PROTOCOL_00_NONE (0x00) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USBDClass_Exported_Functions USB Device Class exported functions + * @{ + */ +void USBDClass_Init(USBDCore_Class_TypeDef *pClass); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __HT32_USBD_CLASS_H ------------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.c new file mode 100644 index 00000000000..c33c0865b9d --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.c @@ -0,0 +1,368 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_descriptor.c + * @version $Rev:: 47 $ + * @date $Date:: 2015-11-18 #$ + * @brief The USB Descriptor. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_usbd_core.h" +#include "ht32_usbd_class.h" +#include "ht32_usbd_descriptor.h" + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDDescriptor USB Descriptor + * @brief USB descriptor + * @{ + */ + + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Device descriptor setting +// USB Specification Release number (bcdUSB) +// <0x0200=> USB 2.0 +// <0x0110=> USB 1.1 +// <0x0100=> USB 1.0 +// USB Class code (assigned by the USB-IF) +// <0x00=> Use class information in the Interface Descriptors (0x00) +// <0x02=> Communications and CDC Control (CDC, 0x02) +// <0xDC=> Diagnostic Device (0xDC) +// <0xEF=> Miscellaneous (0xEF) +// <0xFF=> Vendor Specific (0xFF) +// USB Subclass code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Protocol code (assigned by the USB-IF) <0x0-0xFF:1> +// USB Vendor ID <0x0-0xFFFF:1> +// USB Product ID <0x0-0xFFFF:1> +// USB Device Version <0x0-0xFFFF:1> +// USB String descriptor - Manufacturer +// USB String descriptor - Product +// USB String descriptor - Device serial number +// USB Number of possible configurations <0-255:1> +#define DESC_BCDUSB (0x0110) +#define DESC_BDEVCLASS (0x00) +#define DESC_BDEVSUBCLASS (0x00) +#define DESC_BDEVPROTOCOL (0x00) +#define DESC_IDVENDOR (0x04D9) +#define DESC_IDPRODUCT (0x8008) +#define DESC_BCDDEVICE (0x0100) +#define DESC_IMANUFACTURE (1) +#define DESC_IPRODUCT (1) +#define DESC_ISERIALNUM (1) +#define DESC_INUMCONFN (1) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#if (DESC_BDEVCLASS == 0x0 & DESC_BDEVSUBCLASS != 0x0) +#error "DESC_BDEVSUBCLASS must be reset to zero when the DESC_BDEVCLASS is equal to zero." +#endif +#define DESC_WMAXPACKETSIZE0 (_EP0LEN) +#define DESC_STR_MAN (1 * DESC_IMANUFACTURE) +#define DESC_STR_PRD (2 * DESC_IPRODUCT) +#define DESC_STR_SER (3 * DESC_ISERIALNUM) +#define DESC_NUM_STRING (1 + 3) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Device descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_DeviceDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Device descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_DEV, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_01_DEV, // bDescriptorType 1 DEVICE Descriptor Type + DESC_H2B(DESC_BCDUSB), // bcdUSB 2 USB Specification Release Number + DESC_BDEVCLASS, // bDeviceClass 1 Class code (assigned by the USB-IF) + DESC_BDEVSUBCLASS, // bDeviceSubClass 1 Subclass code (assigned by the USB-IF) + DESC_BDEVPROTOCOL, // bDeviceProtocol 1 Protocol code (assigned by the USB-IF) + DESC_WMAXPACKETSIZE0, // wMaxPacketSize0 1 Maximum packet size for endpoint zero + DESC_H2B(DESC_IDVENDOR), // idVendor 2 Vendor ID (assigned by USB-IF) + DESC_H2B(DESC_IDPRODUCT), // idProduct 2 Product ID (assigned by manufacturer) + DESC_H2B(DESC_BCDDEVICE), // bcdDevice 2 Device release number + DESC_STR_MAN, // iManufacturer 1 Index of string descriptor (Manufacturer) + DESC_STR_PRD, // iProduct 1 Index of string descriptor (Product) + DESC_STR_SER, // iSerialNumber 1 Index of string descriptor (Serial Number) + DESC_INUMCONFN, // iNumConfigurations 1 Number of possible configuration +}; + + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration descriptor setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Configuration descriptor setting +// Self-powered +// Bit 6 of bmAttributes +// Remote Wakeup +// Bit 5 of bmAttributes +// USB Device maximum power (mA) < 2-512:2> +#define DESC_BMATTR_SELF_POWER (0) +#define DESC_BMATTR_REMOTE_WAKEUP (1) +#define DESC_BMAXPOWER (100) +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor definition. DO NOT MODIFY. */ +/*----------------------------------------------------------------------------------------------------------*/ +#define DESC_BMATTRIBUTES (0x80 | (DESC_BMATTR_SELF_POWER << 6) | (DESC_BMATTR_REMOTE_WAKEUP << 5)) +#define DESC_TOTAL_LEN DESC_H2B((DESC_LEN_CONFN_T + RETARGET_DLEN)) + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Configuration Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_ConfnDesc[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Configuration descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_CONFN, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_02_CONFN, // bDescriptorType 1 CONFIGURATION Descriptor Type + DESC_TOTAL_LEN, // wTotalLength 2 Total length of data returned for this configuration + 0x01 + RETARGET_INF, // bNumberInterface 1 Number of interfaces supported by this configuration + 0x01, // bConfigurationValue 1 Value to use as an argument to the SetConfiguration() + 0x00, // iConfiguration 1 Index of string descriptor describing this configuration + DESC_BMATTRIBUTES, // bmAttributes 1 Configuration characteristics + // D6: Self-powered, D5: RemoteWakeup + DESC_POWER(DESC_BMAXPOWER), // bMaxPower 1 Maximum power consumption of the USB device (2 mA units) + + /*--------------------------------------------------------------------------------------------------------*/ + /* Interface descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_INF, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_04_INF, // bDescriptorType 1 INTERFACE Descriptor Type + 0x00, // bInterfaceNumber 1 Number of this interface (Zero-based 0) + 0x00, // bAlternateSetting 1 Value used to select this alternate setting + 2, // bNumEndpoints 1 Number of endpoints used by this interface + CLASS_INF_CLASS, // bInterfaceClass 1 Class code (assigned by USB-IF) + CLASS_INF_SUBCLASS, // bInterfaceSubClass 1 Subclass code (assigned by USB-IF) + CLASS_INF_PTCO, // bInterfaceProtocol 1 Protocol code (assigned by USB) + 0x00, // iInterface 1 Index of string descriptor describing this interface + + /*--------------------------------------------------------------------------------------------------------*/ + /* XXX descriptor */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_XXX, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_01_XXX, // bDescriptorType 1 XXX Descriptor type + DESC_H2B(0x0110), // bcdXXX 2 XXX Specification Release Number + 0x21, // bCountryCode 1 Country code of the localized hardware + 0x01, // bNumDescriptors 1 Number of class descriptors (at least 1) + DESC_TYPE_02_XXX, // bDescriptorType 1 REPORT Descriptor Type + DESC_H2B(DESC_LEN_XXXX), // bDescriptorLength 2 Total size of the Report descriptor + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + 0x81, // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x03, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(_EP1LEN), // wMaxPacketSize 2 Maximum packet size + 0x01, // bInterval 1 Interval for polling endpoint + + /*--------------------------------------------------------------------------------------------------------*/ + /* Endpoint */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_LEN_EPT, // bLength 1 Size of this descriptor in bytes + DESC_TYPE_05_EPT, // bDescriptorType 1 ENDPOINT Descriptor Type + 0x02, // bEndpointAddress 1 The address of the endpoint + // Bit 3..0: The endpoint number + // Bit 6..4: Reserved + // Bit 7 : Direction (0 = Out/1 = In) + 0x03, // bmAttribute 1 Endpoint Attribute + // Bit 1..0: Transfer type + // 00 = Control + // 01 = Isochronous + // 10 = Bulk + // 11 = Interrupt + // All other reserved + DESC_H2B(_EP2LEN), // wMaxPacketSize 2 Maximum packet size + 0x01, // bInterval 1 Interval for polling endpoint + + #ifdef RETARGET_IS_USB + #include "ht32_retarget_desc.h" + #endif + +}; + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB String Descriptor */ +/*----------------------------------------------------------------------------------------------------------*/ +__ALIGN4 static uc8 guUSB_StringDescLANGID[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* LANGID (Index = 0) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(1), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_H2B(0x0409), // wLANGID[0] 2 LANGID code zero +}; + +#if (DESC_IMANUFACTURE == 1) +__ALIGN4 static uc8 guUSB_StringDescManufacture[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Manufacture (Index = 1) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(6), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('H'), // bString N UNICODE encoded string + DESC_CHAR('O'), + DESC_CHAR('L'), + DESC_CHAR('T'), + DESC_CHAR('E'), + DESC_CHAR('K'), +}; +#endif + +#if (DESC_IPRODUCT == 1) +__ALIGN4 static uc8 guUSB_StringDescProduct[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Product (Index = 2) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(12), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('U'), // bString N UNICODE encoded string + DESC_CHAR('S'), + DESC_CHAR('B'), + DESC_CHAR('-'), + DESC_CHAR('X'), + DESC_CHAR('X'), + DESC_CHAR('X'), + DESC_CHAR(' '), + DESC_CHAR('D'), + DESC_CHAR('E'), + DESC_CHAR('M'), + DESC_CHAR('O'), +}; +#endif + + +#if (DESC_ISERIALNUM == 1) +__ALIGN4 static u8 guUSB_StringDescSerialNum[] = +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* Serial Number (Index = 3) */ + /*--------------------------------------------------------------------------------------------------------*/ + /* Field Size Description */ + /*----------------------------------------------------------------------------*/ + DESC_STRLEN(12), // bLength 1 Size of this descriptor in bytes + DESC_TYPE_03_STR, // bDescriptorType 1 STRING Descriptor Type + DESC_CHAR('S'), // bString N UNICODE encoded string + DESC_CHAR('N'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), + DESC_CHAR('0'), +}; +#endif + +uc8 *gpStringDesc[DESC_NUM_STRING] = +{ + + guUSB_StringDescLANGID, + + #if (DESC_IMANUFACTURE == 1) + guUSB_StringDescManufacture, + #else + NULL, + #endif + + #if (DESC_IPRODUCT == 1) + guUSB_StringDescProduct, + #else + NULL, + #endif + + #if (DESC_ISERIALNUM == 1) + guUSB_StringDescSerialNum + #else + NULL, + #endif + +}; + +/*********************************************************************************************************//** + * @brief USB Descriptor pointer initialization. + * @param pDesc: pointer of USBDCore_Desc_TypeDef + * @retval None + ***********************************************************************************************************/ +void USBDDesc_Init(USBDCore_Desc_TypeDef *pDesc) +{ + pDesc->pDeviceDesc = guUSB_DeviceDesc; + pDesc->pConfnDesc = guUSB_ConfnDesc; + pDesc->ppStringDesc = gpStringDesc; + pDesc->uStringDescNumber = DESC_NUM_STRING; + + return; +} + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.h new file mode 100644 index 00000000000..eebcf440bf1 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32_usbd_descriptor.h @@ -0,0 +1,59 @@ +/*********************************************************************************************************//** + * @file example/ht32_usbd_descriptor.h + * @version $Rev:: 47 $ + * @date $Date:: 2015-11-18 #$ + * @brief The USB descriptor. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_USBD_DESCRIPTOR_H +#define __HT32_USBD_DESCRIPTOR_H + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDDescriptor USB Descriptor + * @brief USB descriptor + * @{ + */ + + +/* Exported constants --------------------------------------------------------------------------------------*/ +#define DESC_LEN_CONFN_T (u16)(DESC_LEN_CONFN + DESC_LEN_INF + DESC_LEN_XXX + DESC_LEN_EPT * 2) + +/* Exported functions --------------------------------------------------------------------------------------*/ +void USBDDesc_Init(USBDCore_Desc_TypeDef *pDesc); + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __HT32_USBD_DESCRIPTOR_H -------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32fxxxxx_usbdconf.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32fxxxxx_usbdconf.h new file mode 100644 index 00000000000..a5157ea8fa9 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/example/ht32fxxxxx_usbdconf.h @@ -0,0 +1,453 @@ +/*********************************************************************************************************//** + * @file example/ht32fxxxxx_usbdconf.h + * @version $Rev:: 47 $ + * @date $Date:: 2015-11-18 #$ + * @brief The configuration file of USB Device Driver. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32FXXXX_USBDCONF_H +#define __HT32FXXXX_USBDCONF_H + +// Enter Low Power mode when Suspended +#define USBDCORE_ENABLE_LOW_POWER (0) +// + +#if (USBDCORE_ENABLE_LOW_POWER == 1) + #define USBDCore_LowPower() PWRCU_DeepSleep1(PWRCU_SLEEP_ENTRY_WFE) +#else + #define USBDCore_LowPower(...) +#endif + +/*----------------------------------------------------------------------------------------------------------*/ +/* USB Interrupt Enable */ +/*----------------------------------------------------------------------------------------------------------*/ +// USB Interrupt Setting (UIER) +// USB Global Interrupt Enable (UGIE) (Default) +// Start Of Frame Interrupt Enable (SOFIE) +// USB Reset Interrupt Enable (URSTIE) (Default) +// Resume Interrupt Enable (RSMIE) (Default) +// Suspend Interrupt Enable (SUSPIE) (Default) +// Expected Start of Frame Interrupt Enable (ESOFE) +// Control Endpoint Interrupt Enable (EP0IE) (Default) +// Endpoint1 Interrupt Enable (EP1IE) +// Endpoint2 Interrupt Enable (EP2IE) +// Endpoint3 Interrupt Enable (EP3IE) +// Endpoint4 Interrupt Enable (EP4IE) +// Endpoint5 Interrupt Enable (EP5IE) +// Endpoint6 Interrupt Enable (EP6IE) +// Endpoint7 Interrupt Enable (EP7IE) +#define _UIER (0x071D) +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint0 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Control Endpoint0 Configuration +// Endpoint Buffer Length (EPLEN) +// <8=> 8 bytes +// <16=> 16 bytes +// <32=> 32 bytes +// <64=> 64 bytes + /* Maximum: 64 Bytes */ +#define _EP0LEN (64) + + +// Control Endpoint0 Interrupt Enable Settings (EP0IER) +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) (Default) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) (Default) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +// SETUP Token Packet Received Interrupt Enable (STRXIE) +// SETUP Data Packet Received Interrupt Enable (SDRXIE) (Default) +// SETUP Data Error Interrupt Enable (SDERIE) +// Zero Length Data Packet Received Interrupt Enable (ZLRXIE) +#define _EP0_IER (0x212) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint1 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint1 Configuration +#define _EP1_ENABLE (1) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP1_CFG_EPADR (1) + +// Endpoint Enable (EPEN) +#define _EP1_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP1_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP1_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP1LEN_TMP (64) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP1_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint2 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint2 Configuration +#define _EP2_ENABLE (1) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP2_CFG_EPADR (2) + +// Endpoint Enable (EPEN) +#define _EP2_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP2_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP2_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP2LEN_TMP (64) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP2_IER (0x002) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint3 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint3 Configuration +#define _EP3_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP3_CFG_EPADR (3) + +// Endpoint Enable (EPEN) +#define _EP3_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <2=> Bulk +// <3=> Interrupt +#define _EP3_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP3_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-64:4> + /* Maximum: 64 Bytes */ +#define _EP3LEN_TMP (8) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP3_IER (0x10) +// +// + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint4 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint4 Configuration +#define _EP4_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP4_CFG_EPADR (4) + +// Endpoint Enable (EPEN) +#define _EP4_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP4_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP4_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP4LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP4_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP4_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint5 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint5 Configuration +#define _EP5_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP5_CFG_EPADR (5) + +// Endpoint Enable (EPEN) +#define _EP5_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP5_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP5_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP5LEN_TMP (8) + + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP5_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP5_IER (0x10) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint6 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint6 Configuration +#define _EP6_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP6_CFG_EPADR (6) + +// Endpoint Enable (EPEN) +#define _EP6_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP6_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP6_CFG_EPDIR (0) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP6LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP6_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP6_IER (0x02) +// +// + + +/*----------------------------------------------------------------------------------------------------------*/ +/* Endpoint7 Configuration Setting */ +/*----------------------------------------------------------------------------------------------------------*/ +// Endpoint7 Configuration +#define _EP7_ENABLE (0) + +// Endpoint Address (EPADR) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +#define _EP7_CFG_EPADR (7) + +// Endpoint Enable (EPEN) +#define _EP7_CFG_EPEN_TMP (1) + +// Endpoint Transfer Type +// <1=> Isochronous +// <2=> Bulk +// <3=> Interrupt +#define _EP7_TYPR (3) + +// Endpoint Direction (EPDIR) +// <1=> IN +// <0=> OUT +#define _EP7_CFG_EPDIR (1) + +// Endpoint Buffer Length (EPLEN) (in byte) <4-1000:4> + /* Maximum: 1000 Bytes */ +#define _EP7LEN_TMP (8) + +// Single/Double Buffer Selection (SDBS) +// <0=> Single Buffer +// <1=> Double Buffer +#define _EP7_CFG_SDBS (0) + +// Endpoint Interrupt Enable Settings (EPIER) +// Endpoint Interrupt Enable Settings (EPIER) <0x0-0xFF:1> +// OUT Token Packet Received Interrupt Enable (OTRXIE) +// OUT Data Packet Received Interrupt Enable (ODRXIE) +// OUT Data Buffer Overrun Interrupt Enable (ODOVIE) +// IN Token Packet Received Interrupt Enable (ITRXIE) +// IN Data Packet Transmitted Interrupt Enable (IDTXIE) +// NAK Transmitted Interrupt Enable (NAKIE) +// STALL Transmitted Interrupt Enable (STLIE) +// USB Error Interrupt Enable (UERIE) +#define _EP7_IER (0x10) +// +// + +#endif diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/inc/ht32_usbd_core.h b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/inc/ht32_usbd_core.h new file mode 100644 index 00000000000..00ff7d8e53a --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/inc/ht32_usbd_core.h @@ -0,0 +1,435 @@ +/*********************************************************************************************************//** + * @file ht32_usbd_core.h + * @version $Rev:: 5656 $ + * @date $Date:: 2021-11-24 #$ + * @brief The header file of standard protocol related function for HT32 USB Device Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> + +/* Define to prevent recursive inclusion -------------------------------------------------------------------*/ +#ifndef __HT32_USBD_CORE_H +#define __HT32_USBD_CORE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup HT32_USBD_Library + * @{ + */ + +/** @addtogroup USBDCore + * @{ + */ + + +/* Settings ------------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Settings USB Device Core settings + * @{ + */ +/* USBD Debug mode */ +// Enable USB Debug mode +// Dump USB Debug data +#ifndef USBDCORE_DEBUG + #define USBDCORE_DEBUG (0) /*!< Enable USB Debug mode */ + #define USBDCORE_DEBUG_DATA (0) /*!< Dump USB Debug data */ +#endif +/** + * @} + */ + +/* Exported types ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Type USB Device Core exported types + * @{ + */ +/** + * @brief USB Device Request. + */ +typedef __PACKED_H struct +{ + uc8 bmRequestType; + uc8 bRequest; + uc8 wValueL; + uc8 wValueH; + uc16 wIndex; + uc16 wLength; +} __PACKED_F USBDCore_Request_TypeDef; + +/** + * @brief USB Descriptor. + */ +typedef struct +{ + uc8 *pDeviceDesc; /*!< Device Descriptor */ + uc8 *pConfnDesc; /*!< Configuration Descriptor */ + uc8 **ppStringDesc; /*!< String Descriptor */ + u32 uStringDescNumber; /*!< Count of String Descriptor */ +} USBDCore_Desc_TypeDef; + +/** + * @brief STALL, control IN or control OUT. + */ +typedef enum +{ + USB_ACTION_STALL = 0, + USB_ACTION_DATAIN = 1, + USB_ACTION_DATAOUT = 2, +} USBDCore_Action_Enum; + +/** + * @brief Call back function. + */ +typedef struct +{ + void (*func) (u32 uPara); /*!< Call back function pointer */ + u32 uPara; /*!< Parameter of call back function */ +} USBDCore_CallBack_TypeDef; + +/** + * @brief Parameter for control IN/OUT Transfer. + */ +typedef struct +{ + u8 uBuffer[2]; /*!< Temporary buffer */ + uc8 *pData; /*!< Pointer of control IN/OUT Data */ + s32 sByteLength; /*!< Total length for control IN/OUT Transfer */ + USBDCore_Action_Enum Action; /*!< STALL, control IN or control OUT */ + USBDCore_CallBack_TypeDef CallBack_OUT; /*!< Call back function pointer for Control OUT */ +} USBDCore_Transfer_TypeDef; + +/** + * @brief USB Device. + */ +typedef struct +{ + USBDCore_Request_TypeDef Request; /*!< USB Device Request */ + USBDCore_Desc_TypeDef Desc; /*!< USB Descriptor */ + USBDCore_Transfer_TypeDef Transfer; /*!< Parameter for control IN/OUT Transfer */ +} USBDCore_Device_TypeDef; + +/** + * @brief Bit access for CurrentFeature. + */ +typedef __PACKED_H struct _FEATURE_TYPEBIT +{ + unsigned bSelfPowered :1; /*!< Remote Wakeup feature */ + unsigned bRemoteWakeup :1; /*!< Self Powered */ +} __PACKED_F USBDCore_Feature_TypeBit; + +/** + * @brief For Set/ClearFeature and GetStatus request. + */ +typedef __PACKED_H union _FEATURE_TYPEDEF +{ + u8 uByte; /*!< Byte access for CurrentFeature */ + USBDCore_Feature_TypeBit Bits; /*!< Bit access for CurrentFeature */ +} __PACKED_F USBDCore_Feature_TypeDef; + +/** + * @brief Device State. + */ +typedef enum +{ + USB_STATE_UNCONNECTED = 0, + USB_STATE_ATTACHED = 1, + USB_STATE_POWERED = 2, + USB_STATE_SUSPENDED = 3, + USB_STATE_DEFAULT = 4, + USB_STATE_ADDRESS = 5, + USB_STATE_CONFIGURED = 6, +} USBDCore_Status_Enum; + +/** + * @brief USB Device information. + */ +typedef struct +{ + u8 uCurrentConfiguration; /*!< For Set/GetConfiguration request */ + u8 uCurrentInterface; /*!< For Set/GetInterface request */ + volatile USBDCore_Status_Enum CurrentStatus; /*!< Device State */ + USBDCore_Status_Enum LastStatus; /*!< Device State before SUSPEND */ + USBDCore_Feature_TypeDef CurrentFeature; /*!< For Set/ClearFeature and GetStatus request */ + u32 uIsDiscardClearFeature; /*!< Discard ClearFeature flag for Mass Storage */ +} USBDCore_Info_TypeDef; + +typedef void (*USBDCore_CallBackClass_Typedef) (USBDCore_Device_TypeDef *pDev); +typedef void (*USBDCore_CallBackVendor_Typedef) (USBDCore_Device_TypeDef *pDev); +typedef void (*USBDCore_CallBackEPTn_Typedef) (USBD_EPTn_Enum EPTn); + +/** + * @brief USB Class call back function. + */ +typedef struct +{ + USBDCore_CallBack_TypeDef CallBack_MainRoutine; /*!< Class main routine call back function */ + USBDCore_CallBack_TypeDef CallBack_Reset; /*!< Class RESET call back function */ + USBDCore_CallBack_TypeDef CallBack_StartOfFrame; /*!< Class SOF call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassGetDescriptor; /*!< Class Get Descriptor call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassSetInterface; /*!< Set Interface call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassGetInterface; /*!< Get Interface call back function */ + USBDCore_CallBackClass_Typedef CallBack_ClassRequest; /*!< Class Request call back function */ + USBDCore_CallBackVendor_Typedef CallBack_VendorRequest; /*!< Vendor Request call back function */ + USBDCore_CallBackEPTn_Typedef CallBack_EPTn[MAX_EP_NUM]; /*!< Endpoint n call back function */ +} USBDCore_Class_TypeDef; + +/** + * @brief USB Device Power related call back function. + */ +typedef struct +{ + USBDCore_CallBack_TypeDef CallBack_Suspend; +} USBDCore_Power_TypeDef; + +/** + * @brief Major structure of USB Library. + */ +typedef struct +{ + USBDCore_Device_TypeDef Device; /*!< USB Device */ + USBDCore_Info_TypeDef Info; /*!< USB Device information */ + USBDCore_Class_TypeDef Class; /*!< USB Class call back function */ + u32 *pDriver; /*!< USB Device Driver initialization structure */ + USBDCore_Power_TypeDef Power; /*!< USB Device Power related call back function */ +} USBDCore_TypeDef; + +/*----------------------------------------------------------------------------------------------------------*/ +/* Variable architecture of USB Library */ +/*----------------------------------------------------------------------------------------------------------*/ +/* USBCore - USBDCore_TypeDef Major structure of USB Library */ +/* USBCore.Device - USBDCore_Device_TypeDef USB Device */ +/* USBCore.Device.Request - USBDCore_Request_TypeDef USB Device Request */ +/* USBCore.Device.Request.bmRequestType */ +/* USBCore.Device.Request.bRequest */ +/* USBCore.Device.Request.wValueL */ +/* USBCore.Device.Request.wValueH */ +/* USBCore.Device.Request.wIndex */ +/* USBCore.Device.Request.wLength */ +/* USBCore.Device.Desc - USBDCore_Desc_TypeDef USB Descriptor */ +/* USBCore.Device.Desc.pDeviceDesc Device Descriptor */ +/* USBCore.Device.Desc.pConfnDesc Configuration Descriptor */ +/* USBCore.Device.Desc.pStringDesc[DESC_NUM_STRING] String Descriptor */ +/* USBCore.Device.Desc.uStringDescNumber Count of String Descriptor */ +/* USBCore.Device.Transfer - USBDCore_Transfer_TypeDef Parameter for control IN/OUT Transfer */ +/* USBCore.Device.Transfer.uBuffer[2] Temporary buffer */ +/* USBCore.Device.Transfer.pData Pointer of control IN/OUT Data */ +/* USBCore.Device.Transfer.sByteLength Total length for control IN/OUT Transfer */ +/* USBCore.Device.Transfer.Action - USBDCore_Action_Enum STALL, control IN or control OUT */ +/* USBCore.Device.Transfer.CallBack_OUT.func(uPara) Call back function pointer for Control OUT */ +/* USBCore.Device.Transfer.CallBack_OUT.uPara Parameter of Control OUT call back function */ +/* */ +/* USBCore.Info - USBDCore_Info_TypeDef USB Device information */ +/* USBCore.Info.uCurrentConfiguration For Set/GetConfiguration request */ +/* USBCore.Info.uCurrentInterface For Set/GetInterface request */ +/* USBCore.Info.CurrentStatus - USBDCore_Status_Enum Device State */ +/* USBCore.Info.LastStatus - USBDCore_Status_Enum Device State before SUSPEND */ +/* USBCore.Info.CurrentFeature - USBDCore_Feature_TypeDef For Set/ClearFeature and GetStatus request */ +/* USBCore.Info.CurrentFeature.uByte Byte access for CurrentFeature */ +/* USBCore.Info.CurrentFeature.Bits.bRemoteWakeup Remote Wakeup feature */ +/* USBCore.Info.CurrentFeature.Bits.bSelfPowered Self Powered */ +/* USBCore.Info.uIsDiscardClearFeature Discard ClearFeature flag for Mass Storage */ +/* */ +/* USBCore.Class - USBDCore_Class_TypeDef USB Class call back function */ +/* USBCore.Class.CallBack_MainRoutine.func(uPara) Class main routine call back function */ +/* USBCore.Class.CallBack_MainRoutine.uPara Parameter of class main routine */ +/* USBCore.Class.CallBack_Reset.func(uPara) Class RESET call back function */ +/* USBCore.Class.CallBack_Reset.uPara Parameter of RESET call back function */ +/* USBCore.Class.CallBack_StartOfFrame.func(uPara) Class SOF call back function */ +/* USBCore.Class.CallBack_StartOfFrame.uPara Parameter of SOF call back function */ +/* USBCore.Class.CallBack_ClassGetDescriptor(pDev) Class Get Descriptor call back function */ +/* USBCore.Class.CallBack_ClassSetInterface(pDev) Set Interface call back function */ +/* USBCore.Class.CallBack_ClassGetInterface(pDev) Get Interface call back function */ +/* USBCore.Class.CallBack_ClassRequest(pDev) Class Request call back function */ +/* USBCore.Class.CallBack_EPTn[MAX_EP_NUM](EPTn) Endpoint n call back function */ +/* */ +/* USBCore.pDriver USB Device Driver initialization structure */ +/* */ +/* USBCore.Power - USBDCore_Power_TypeDef USB Device Power related call back function */ +/* USBCore.Power.CallBack_Suspend.func(uPara) System low power function for SUSPEND */ +/* USBCore.Power.CallBack_Suspend.uPara Parameter of system low power function */ +/*----------------------------------------------------------------------------------------------------------*/ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Constant USB Device Core exported constants + * @{ + */ + +/** @defgroup USBDCore_Descriptor Definitions for USB descriptor + * @{ + */ +#define DESC_TYPE_01_DEV (0x1) +#define DESC_TYPE_02_CONFN (0x2) +#define DESC_TYPE_03_STR (0x3) +#define DESC_TYPE_04_INF (0x4) +#define DESC_TYPE_05_EPT (0x5) +#define DESC_TYPE_06_DEV_QLF (0x6) +#define DESC_TYPE_08_INF_PWR (0x8) + +#define DESC_CLASS_00_BY_INF (0x00) +#define DESC_CLASS_01_AUDIO (0x01) +#define DESC_CLASS_02_CDC_CTRL (0x02) +#define DESC_CLASS_03_HID (0x03) +#define DESC_CLASS_05_PHY (0x05) +#define DESC_CLASS_06_STILL_IMG (0x06) +#define DESC_CLASS_07_PRINTER (0x07) +#define DESC_CLASS_08_MASS_STORAGE (0x08) +#define DESC_CLASS_09_HUB (0x09) +#define DESC_CLASS_0A_CDC_DATA (0x0A) +#define DESC_CLASS_0B_SMART_CARD (0x0B) +#define DESC_CLASS_0E_VIDEO (0x0E) +#define DESC_CLASS_0F_PHD (0x0F) +#define DESC_CLASS_FF_VENDOR (0xFF) + +#define DESC_LEN_DEV ((u32)(18)) +#define DESC_LEN_CONFN ((u32)(9)) +#define DESC_LEN_INF ((u32)(9)) +#define DESC_LEN_EPT ((u32)(7)) +/** + * @} + */ + +/** @defgroup USBDCore_Request Definitions for USB Request + * @{ + */ +#define REQ_DIR_00_H2D (0 << 7) +#define REQ_DIR_01_D2H (1 << 7) + +#define REQ_TYPE_00_STD (0 << 5) +#define REQ_TYPE_01_CLS (1 << 5) +#define REQ_TYPE_02_VND (2 << 5) + +#define REQ_REC_00_DEV (0) +#define REQ_REC_01_INF (1) +#define REQ_REC_02_EPT (2) +/** + * @} + */ + +/** + * @brief For USBDCore_EPTReadOUTData function. + */ +#define USB_DISCARD_OUT_DATA (0) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Macro USB Device Core exported macros + * @{ + */ +#define __DBG_USBPrintf(...) +#define __DBG_USBDump(a, b) + +#if (USBDCORE_DEBUG == 1) + #ifndef RETARGET_IS_USB + extern u32 __DBG_USBCount; + #undef __DBG_USBPrintf + #define __DBG_USBPrintf printf + #if (USBDCORE_DEBUG_DATA == 1) + #undef __DBG_USBDump + void __DBG_USBDump(uc8 *memory, u32 len); + #endif + #endif +#endif + +/** + * @brief Convert Half-Word to Byte for descriptor. + */ +#define DESC_H2B(Val) ((u8)(Val & 0x00FF)), ((u8)((Val & 0xFF00) >> 8)) + +/** + * @brief Padding 0 automatically for String descriptor. + */ +#define DESC_CHAR(c) (c), (0) + +/** + * @brief Calculate String length for String descriptor. + */ +#define DESC_STRLEN(n) (n * 2 + 2) + +/** + * @brief Calculate power for Configuration descriptor. + */ +#define DESC_POWER(mA) (mA / 2) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Functions USB Device Core exported functions + * @{ + */ +#define USBDCore_DeInit API_USB_DEINIT +#define USBDCore_EPTReset API_USB_EPTn_RESET +#define USBDCore_EPTGetBufferLen API_USB_EPTn_GET_BUFFLEN +#define USBDCore_EPTGetTransferCount API_USB_EPTn_GET_CNT +#define USBDCore_EPTSetSTALL API_USB_EPTn_SET_HALT +#define USBDCore_EPTWaitSTALLSent API_USB_EPTn_WAIT_STALL_SENT +#define USBDCore_EPTClearDataToggle API_USB_EPTn_CLR_DTG + +#define USBDCore_EPTWriteINData API_USB_EPTn_WRITE_IN +#define USBDCore_EPTReadOUTData API_USB_EPTn_READ_OUT +#define USBDCore_EPTReadMemory API_USB_EPTn_READ_MEM + +void USBDCore_Init(USBDCore_TypeDef *pCore); +void USBDCore_IRQHandler(USBDCore_TypeDef *pCore); +void USBDCore_MainRoutine(USBDCore_TypeDef *pCore); +u32 USBDCore_IsSuspend(USBDCore_TypeDef *pCore); +u32 USBDCore_GetRemoteWakeUpFeature(USBDCore_TypeDef *pCore); +void USBDCore_TriggerRemoteWakeup(void); +USBDCore_Status_Enum USBDCore_GetStatus(void); + +void USBDCore_EPTReset(USBD_EPTn_Enum USBD_EPTn); +u32 USBDCore_EPTGetBufferLen(USBD_EPTn_Enum USBD_EPTn); +u32 USBDCore_EPTGetTransferCount(USBD_EPTn_Enum USBD_EPTn, USBD_TCR_Enum type); +void USBDCore_EPTSetSTALL(USBD_EPTn_Enum USBD_EPTn); +void USBDCore_EPTWaitSTALLSent(USBD_EPTn_Enum USBD_EPTn); +void USBDCore_EPTClearDataToggle(USBD_EPTn_Enum USBD_EPTn); + +u32 USBDCore_EPTWriteINData(USBD_EPTn_Enum USBD_EPTn, u32 *pFrom, u32 len); +u32 USBDCore_EPTReadOUTData(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +u32 USBDCore_EPTReadMemory(USBD_EPTn_Enum USBD_EPTn, u32 *pTo, u32 len); +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HT32_USBD_CORE_H -------------------------------------------------------------------------------*/ diff --git a/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/src/ht32_usbd_core.c b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/src/ht32_usbd_core.c new file mode 100644 index 00000000000..bfc1abbb9c2 --- /dev/null +++ b/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32_USBD_Library/src/ht32_usbd_core.c @@ -0,0 +1,1037 @@ +/*********************************************************************************************************//** + * @file ht32_usbd_core.c + * @version $Rev:: 3813 $ + * @date $Date:: 2019-05-07 #$ + * @brief The standard protocol related function of HT32 USB Device Library. + ************************************************************************************************************* + * @attention + * + * Firmware Disclaimer Information + * + * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the + * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and + * other intellectual property laws. + * + * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the + * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties + * other than HOLTEK and the customer. + * + * 3. The program technical documentation, including the code, is provided "as is" and for customer reference + * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including + * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including + * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. + * + *

Copyright (C) Holtek Semiconductor Inc. All rights reserved

+ ************************************************************************************************************/ + +/* Includes ------------------------------------------------------------------------------------------------*/ +#include "ht32.h" +#include "ht32_usbd_core.h" + +#ifdef USBD_VENDOR_SUPPORT +#include "ht32_usbd_vendor.c" +#endif + +/** @addtogroup HT32_USBD_Library HT32 USB Device Library + * @{ + */ + +/** @defgroup USBDCore USB Device Core + * @brief USB Device Core standard protocol related function + * @{ + */ + + +/* Private types -------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_TypesDefinitions USB Device Core private types definitions + * @{ + */ +typedef enum +{ + Device = 0, + Interface = 1, + Endpoint = 2, + Other = 3, +} USBDCore_Recipient_Enum; + +typedef enum +{ + ClearFeature = 0, + SetFeature = 1, +} USBDCore_SetClearFeature_Enum; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Define USB Device Core private definitions + * @{ + */ +/* USBD Debug mode */ +#if (USBDCORE_DEBUG == 1) + #ifdef RETARGET_IS_USB + #warning "USB debug mode can not work when retaget to USB Virtual COM. Turn off automatically." + #undef USBDCORE_DEBUG + #define USBDCORE_DEBUG 0 + #else + u32 __DBG_USBCount; + #warning "USB debug mode has been enabled which degrade the performance." + #warning "After the debug operation, please remember to turn off USB debug mode." + #endif +#endif + +/** @defgroup USBDCore_STD Definition for standard request + * @{ + */ +#define REQ_00_GET_STAT ((u16)(0 << 8)) +#define REQ_01_CLR_FETU ((u16)(1 << 8)) +#define REQ_03_SET_FETU ((u16)(3 << 8)) +#define REQ_05_SET_ADDR ((u16)(5 << 8)) +#define REQ_06_GET_DESC ((u16)(6 << 8)) +#define REQ_07_SET_DESC ((u16)(7 << 8)) +#define REQ_08_GET_CONF ((u16)(8 << 8)) +#define REQ_09_SET_CONF ((u16)(9 << 8)) +#define REQ_10_GET_INF ((u16)(10 << 8)) +#define REQ_11_SET_INF ((u16)(11 << 8)) +#define REQ_12_SYN_FRME ((u16)(12 << 8)) +/** + * @} + */ + +#define DESC_TYPE_01_DEV (0x1) +#define DESC_TYPE_02_CONFN (0x2) +#define DESC_TYPE_03_STR (0x3) +#define USB_NO_DATA (-1) /*!< For Device.Transfer.sByteLength */ +#define BMREQUEST_TYPE_MASK (0x6 << 4) /*!< bmRequestType[6:5] */ +#define USB_FEATURE_REMOTE_WAKEUP (1) + +#define MAX_CONTROL_OUT_SIZE (64) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------------------------------------*/ +static void _USBDCore_PowerHandler(USBDCore_TypeDef *pCore); +static void _USBDCore_Reset(USBDCore_TypeDef *pCore); +static void _USBDCore_Resume(USBDCore_TypeDef *pCore); +static void _USBDCore_Suspend(USBDCore_TypeDef *pCore); +static void _USBDCore_Setup(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_Request(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_GetStatus(USBDCore_TypeDef *pCore, USBDCore_Recipient_Enum recipient); +static void _USBDCore_Standard_SetClearFeature(USBDCore_TypeDef *pCore, USBDCore_Recipient_Enum recipient, USBDCore_SetClearFeature_Enum type); +static void _USBDCore_Standard_SetAddress(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_GetDescriptor(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_GetConfiguration(USBDCore_TypeDef *pCore); +static void _USBDCore_Standard_SetConfiguration(USBDCore_TypeDef *pCore); +static void _USBDCore_ControlIN(USBDCore_TypeDef *pCore); +static void _USBDCore_ControlOUT(USBDCore_TypeDef *pCore); + +/* Private macro -------------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Macro USB Device Core private macros + * @{ + */ +/** + * @brief Get self powered bit from Device descriptor + */ +#define _GET_SELFPOWERED_FROM_DESC() (((pCore->Device.Desc.pConfnDesc[7]) >> 6) & 0x01) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Variable USB Device Core private variables + * @{ + */ +USBDCore_TypeDef *pUSBCore; +/** + * @} + */ + + +/* Global Function -----------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Exported_Functions USB Device Core exported functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Core initialization. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_Init(USBDCore_TypeDef *pCore) +{ + pUSBCore = pCore; + pCore->Info.CurrentStatus = USB_STATE_POWERED; + API_USB_INIT(pCore->pDriver); + __DBG_USBPrintf("\r\n%06ld \r\n", ++__DBG_USBCount); + return; +} + +/*********************************************************************************************************//** + * @brief USB Interrupt Service Routine. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_IRQHandler(USBDCore_TypeDef *pCore) +{ + u32 USBISRFlag = API_USB_GET_INT(); + u32 USBEPTISRFlag; + USBD_EPTn_Enum EPTn; + + #if (USBDCORE_DEBUG == 1) + u32 USBAddr = HT_USB->DEVAR; + #endif + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB SOF Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SOF_INT(USBISRFlag)) + { + __DBG_USBPrintf("%06ld SOF[%02d][%02lX]\r\n", ++__DBG_USBCount, pCore->Info.CurrentStatus, USBAddr); + if (pCore->Class.CallBack_StartOfFrame.func != NULL) + { + pCore->Class.CallBack_StartOfFrame.func(pCore->Class.CallBack_StartOfFrame.uPara); + } + API_USB_CLR_SOF_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB SUSPEND Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SUSPEND_INT(USBISRFlag)) + { + __DBG_USBPrintf("%06ld SUSPEND[%02d]\r\n", ++__DBG_USBCount, pCore->Info.CurrentStatus); + API_USB_CLR_SUSPEND_INT(); + _USBDCore_Suspend(pCore); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB RESET Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_RESET_INT(USBISRFlag)) + { + if (API_USB_IS_FRES_INT(USBISRFlag)) + { + API_USB_CLR_FRES_INT(); + } + else + { + __DBG_USBPrintf("%06ld RESET[%02d][%02lX]\r\n", ++__DBG_USBCount, pCore->Info.CurrentStatus, USBAddr); + _USBDCore_Reset(pCore); + if (pCore->Class.CallBack_Reset.func != NULL) + { + pCore->Class.CallBack_Reset.func(pCore->Class.CallBack_Reset.uPara); + } + } + API_USB_CLR_RESET_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB RESUME Interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_RESUME_INT(USBISRFlag)) + { + __DBG_USBPrintf("%06ld RESUME\r\n", ++__DBG_USBCount); + _USBDCore_Resume(pCore); + API_USB_CLR_RESUME_INT(); + } + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB Endpoint 0 interrupt */ + /*--------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_EPTn_INT(USBISRFlag, USBD_EPT0)) + { + USBEPTISRFlag = API_USB_EPTn_GET_INT(USBD_EPT0); + + /*------------------------------------------------------------------------------------------------------*/ + /* Control SETUP Stage */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_IS_SETUP_INT(USBEPTISRFlag)) + { + API_USB_READ_SETUP(&(pCore->Device.Request)); /* Read SETUP Command data from USB Buffer*/ + + __DBG_USBPrintf("%06ld SETUP\t[08]\r\n", ++__DBG_USBCount); + __DBG_USBDump((uc8 *)&(pCore->Device.Request), 8); + + _USBDCore_Setup(pCore); + API_USB_CLR_SETUP_INT(); /* Clear SETUP Interrupt */ + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Control Endpoint 0 IN */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_EPTn_IS_IN_INT(USBEPTISRFlag)) + { + __DBG_USBPrintf("%06ld EP0IN\t[%02ld]", ++__DBG_USBCount, pCore->Device.Transfer.sByteLength); + + _USBDCore_ControlIN(pCore); + API_USB_EPTn_CLR_IN_INT(USBD_EPT0); + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Control Endpoint 0 OUT */ + /*------------------------------------------------------------------------------------------------------*/ + if (API_USB_EPTn_IS_OUT_INT(USBEPTISRFlag)) + { + __DBG_USBPrintf("%06ld EP0OUT\t[%02ld]", ++__DBG_USBCount, pCore->Device.Transfer.sByteLength); + + /*----------------------------------------------------------------------------------------------------*/ + /* Clear interrupt flag before USBDCore_ControlOUT is meaning since USBDCore_ControlOUT clear NAKRX */ + /* bit which will cause another interrupt occur. */ + /*----------------------------------------------------------------------------------------------------*/ + API_USB_EPTn_CLR_OUT_INT(USBD_EPT0); + _USBDCore_ControlOUT(pCore); + } + + /*------------------------------------------------------------------------------------------------------*/ + /* Clear Control Endpoint 0 global interrupt */ + /*------------------------------------------------------------------------------------------------------*/ + API_USB_CLR_EPTn_INT(USBD_EPT0); + + } /* if (API_USB_IS_EP_INT(USBISRFlag, USBD_EPT0)) */ + + + /*--------------------------------------------------------------------------------------------------------*/ + /* USB Endpoint n call back function */ + /*--------------------------------------------------------------------------------------------------------*/ + while ((EPTn = API_USB_GET_EPT_NUM(API_USB_GET_INT())) != USBD_NOEPT) + { + USBEPTISRFlag = API_USB_EPTn_GET_INT((USBD_EPTn_Enum)EPTn); + + if (API_USB_EPTn_IS_INT(USBEPTISRFlag)) + { + API_USB_EPTn_CLR_INT(EPTn); + API_USB_CLR_EPTn_INT(EPTn); + + if (pCore->Class.CallBack_EPTn[EPTn] != NULL) + { + pCore->Class.CallBack_EPTn[EPTn](EPTn); + } + } + } /* while ((EPTn = API_USB_GET_EPTn_NUM(API_USB_GET_INT())) != USBD_NOEPT) */ + + return; +} + +/*********************************************************************************************************//** + * @brief USB Core Main Routine for application. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +void USBDCore_MainRoutine(USBDCore_TypeDef *pCore) +{ + _USBDCore_PowerHandler(pCore); + + /*--------------------------------------------------------------------------------------------------------*/ + /* Class main routine call back function */ + /*--------------------------------------------------------------------------------------------------------*/ + if ((pCore->Class.CallBack_MainRoutine.func != NULL) && (pCore->Info.CurrentStatus == USB_STATE_CONFIGURED)) + { + pCore->Class.CallBack_MainRoutine.func(pCore->Class.CallBack_MainRoutine.uPara); + } + + return; +} + +/*********************************************************************************************************//** + * @brief Return Suspend status + * @param pCore: pointer of USB Device + * @retval TRUE or FALSE + ***********************************************************************************************************/ +u32 USBDCore_IsSuspend(USBDCore_TypeDef *pCore) +{ + return ((pCore->Info.CurrentStatus == USB_STATE_SUSPENDED) ? TRUE : FALSE); +} + +/*********************************************************************************************************//** + * @brief Return remote wake status which set by SET FEATURE standard command + * @param pCore: pointer of USB Device + * @retval TRUE or FALSE + ***********************************************************************************************************/ +u32 USBDCore_GetRemoteWakeUpFeature(USBDCore_TypeDef *pCore) +{ + return (pCore->Info.CurrentFeature.Bits.bRemoteWakeup); +} + +/*********************************************************************************************************//** + * @brief Turn on USB power and remote wakeup the Host + * @retval None + ***********************************************************************************************************/ +void USBDCore_TriggerRemoteWakeup(void) +{ + API_USB_POWER_ON(); /* Turn on USB Power */ + API_USB_REMOTE_WAKEUP(); /* Generate Remote Wakeup request to Host (RESUME) */ + return; +} + +/*********************************************************************************************************//** + * @brief Get USB Device status + * @retval USBDCore_Status_Enum + ***********************************************************************************************************/ +USBDCore_Status_Enum USBDCore_GetStatus(void) +{ + return pUSBCore->Info.CurrentStatus; +} + +/*********************************************************************************************************//** + * @brief Dump memory data for debug purpose. + * @param memory: buffer pointer to dump + * @param len: dump length + * @retval None + ***********************************************************************************************************/ +#if (USBDCORE_DEBUG == 1 && USBDCORE_DEBUG_DATA == 1) +void __DBG_USBDump(uc8 *memory, u32 len) +{ + u32 i; + for (i = 0; i < len; i++) + { + if (i % 8 == 0) + { + if (i != 0) + { + __DBG_USBPrintf("\r\n"); + } + __DBG_USBPrintf("\t\t"); + } + __DBG_USBPrintf("%02X ", *((u8 *)(memory + i))); + } + __DBG_USBPrintf("\r\n"); + + return; +} +#endif +/** + * @} + */ + +/* Private functions ---------------------------------------------------------------------------------------*/ +/** @defgroup USBDCore_Private_Function USB Device Core private functions + * @{ + */ +/*********************************************************************************************************//** + * @brief USB Core Power handler for application. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_PowerHandler(USBDCore_TypeDef *pCore) +{ + API_USB_POWER_UP(pCore->pDriver, pCore->Info.CurrentFeature.Bits.bSelfPowered); + + if (pCore->Info.CurrentStatus == USB_STATE_SUSPENDED) + { + /*------------------------------------------------------------------------------------------------------*/ + /* System Low Power call back function */ + /*------------------------------------------------------------------------------------------------------*/ + if (pCore->Power.CallBack_Suspend.func != NULL) + { + __DBG_USBPrintf("%06ld >LOWPOWER\r\n", ++__DBG_USBCount); + + pCore->Power.CallBack_Suspend.func(pCore->Power.CallBack_Suspend.uPara); + + __DBG_USBPrintf("%06ld pDriver; + + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + pCore->Info.uCurrentConfiguration = 0; + pCore->Info.uCurrentInterface = 0; + pCore->Info.CurrentFeature.Bits.bRemoteWakeup = 0; + pCore->Info.CurrentStatus = USB_STATE_DEFAULT; + pCore->Info.uIsDiscardClearFeature = FALSE; + + API_USB_DEINIT(); + + API_USB_POWER_ON(); + + /* Endpoint 0 initialization */ + API_USB_EPTn_INIT(USBD_EPT0, pCore->pDriver); // To be modify, init from desc + + /* Enable USB interrupt */ + API_USB_ENABLE_INT(pDrv->uInterruptMask); + + return; +} + +/*********************************************************************************************************//** + * @brief USB Resume + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Resume(USBDCore_TypeDef *pCore) +{ + API_USB_POWER_ON(); + pCore->Info.CurrentStatus = pCore->Info.LastStatus; + return; +} + +/*********************************************************************************************************//** + * @brief USB Suspend + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Suspend(USBDCore_TypeDef *pCore) +{ + /*--------------------------------------------------------------------------------------------------------*/ + /* When Device has been suspended, Change CurrentStatus as SUSPEND and then USBDCore_PowerHandler will */ + /* turn off chip power. */ + /*--------------------------------------------------------------------------------------------------------*/ + if (pCore->Info.CurrentStatus >= USB_STATE_POWERED) + { + API_USB_POWER_OFF(); + pCore->Info.LastStatus = pCore->Info.CurrentStatus; + pCore->Info.CurrentStatus = USB_STATE_SUSPENDED; + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Setup Stage + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Setup(USBDCore_TypeDef *pCore) +{ + pCore->Device.Transfer.Action = USB_ACTION_STALL; + pCore->Device.Transfer.sByteLength = 0; + + switch (pCore->Device.Request.bmRequestType & BMREQUEST_TYPE_MASK) + { + /*------------------------------------------------------------------------------------------------------*/ + /* Standard requests */ + /*------------------------------------------------------------------------------------------------------*/ + case REQ_TYPE_00_STD: + { + _USBDCore_Standard_Request(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* Class requests */ + /*------------------------------------------------------------------------------------------------------*/ + case REQ_TYPE_01_CLS: + { + if (pCore->Class.CallBack_ClassRequest != NULL) + { + pCore->Class.CallBack_ClassRequest(&(pCore->Device)); + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* Vendor requests */ + /*------------------------------------------------------------------------------------------------------*/ + case REQ_TYPE_02_VND: + { + if (pCore->Class.CallBack_VendorRequest != NULL) + { + pCore->Class.CallBack_VendorRequest(&(pCore->Device)); + } + /* Add Vendor requests handler here.... */ + #ifdef USBD_VENDOR_SUPPORT + USBDVendor_Request(pCore); + #endif + break; + } + } /* switch (gUSBReq.bmRequestType.byte) */ + + switch (pCore->Device.Transfer.Action) + { + /*------------------------------------------------------------------------------------------------------*/ + /* Control IN */ + /*------------------------------------------------------------------------------------------------------*/ + case USB_ACTION_DATAIN: + { + /*----------------------------------------------------------------------------------------------------*/ + /* When the Control IN length is large than the Host required, transfer the length which specified */ + /* by SETUP Data Packet. */ + /*----------------------------------------------------------------------------------------------------*/ + if (pCore->Device.Transfer.sByteLength > pCore->Device.Request.wLength) + { + pCore->Device.Transfer.sByteLength = pCore->Device.Request.wLength; + } + __DBG_USBPrintf("%06ld EP0IN\t[%02ld]", __DBG_USBCount, pCore->Device.Transfer.sByteLength); + + _USBDCore_ControlIN(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* Control OUT */ + /*------------------------------------------------------------------------------------------------------*/ + case USB_ACTION_DATAOUT: + { + if (pCore->Device.Transfer.sByteLength == 0) + { + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32 *)0, 0); /* Prepare ZLP ack for Control OUT */ + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* STALL */ + /*------------------------------------------------------------------------------------------------------*/ + default: + { + __DBG_USBPrintf("%06ld EP0 STALL\r\n", __DBG_USBCount); + + API_USB_EPTn_SEND_STALL(USBD_EPT0); + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Stand Request. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_Request(USBDCore_TypeDef *pCore) +{ + u16 USBCmd = *((u16 *)(&(pCore->Device.Request))); + + switch (USBCmd) + { + /*------------------------------------------------------------------------------------------------------*/ + /* | bRequest | Data transfer direction | Type | Recipient | Data */ + /*------------------------------------------------------------------------------------------------------*/ + + /*------------------------------------------------------------------------------------------------------*/ + /* | 00_Get Status | 80_Device-to-Host | 00_Standard Request | 0_Device | 0080h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_00_GET_STAT | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld GET DST\t[%02d]\r\n", __DBG_USBCount, pCore->Info.CurrentFeature.uByte); + _USBDCore_Standard_GetStatus(pCore, Device); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 00_Get Status | 80_Device-to-Host | 00_Standard Request | 1_Interface | 0081h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_00_GET_STAT | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld GET IST\t[%02d]\r\n", __DBG_USBCount, 0); + _USBDCore_Standard_GetStatus(pCore, Interface); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 00_Get Status | 80_Device-to-Host | 00_Standard Request | 2_Endpoint | 0082h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_00_GET_STAT | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_02_EPT): + { + __DBG_USBPrintf("%06ld GET EST\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wIndex); + _USBDCore_Standard_GetStatus(pCore, Endpoint); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 01_Clear Feature | 00_Host-to-Device | 00_Standard Request | 0_Device | 0100h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_01_CLR_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld CLR DFEA\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetClearFeature(pCore, Device, ClearFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 01_Clear Feature | 00_Host-to-Device | 00_Standard Request | 2_Endpoint | 0102h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_01_CLR_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_02_EPT): + { + __DBG_USBPrintf("%06ld CLR EFEA\t[0x%02x]\r\n", __DBG_USBCount, pCore->Device.Request.wIndex); + _USBDCore_Standard_SetClearFeature(pCore, Endpoint, ClearFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 03_Set Feature | 00_Host-to-Device | 00_Standard Request | 0_Device | 0300h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_03_SET_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld SET DFEA\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetClearFeature(pCore, Device, SetFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 03_Set Feature | 00_Host-to-Device | 00_Standard Request | 2_Endpoint | 0302h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_03_SET_FETU | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_02_EPT): + { + __DBG_USBPrintf("%06ld SET EFEA\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wIndex); + _USBDCore_Standard_SetClearFeature(pCore, Endpoint, SetFeature); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 05_Set Address | 00_Host-to-Device | 00_Standard Request | 0_Device | 0500h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_05_SET_ADDR | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld SET ADDR\t[%02d]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetAddress(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 06_Get Descriptor | 80_Device-to-Host | 00_Standard Request | 0_Device | 0680h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_06_GET_DESC | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld GET DDESC\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueH); + _USBDCore_Standard_GetDescriptor(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 06_Get Descriptor | 80_Device-to-Host | 00_Standard Request | 1_Interface | 0681h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_06_GET_DESC | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld GET IDESC\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueH); + if (pCore->Class.CallBack_ClassGetDescriptor != NULL) + { + pCore->Class.CallBack_ClassGetDescriptor((USBDCore_Device_TypeDef *)&(pCore->Device)); + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 08_Get Configuration | 80_Host-to-Device | 00_Standard Request | 0_Device | 0880h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_08_GET_CONF | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld GET CONF\t[%02X]\r\n", __DBG_USBCount, pCore->Info.uCurrentConfiguration); + _USBDCore_Standard_GetConfiguration(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 09_Set Configuration | 00_Host-to-Device | 00_Standard Request | 0_Device | 0900h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_09_SET_CONF | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_00_DEV): + { + __DBG_USBPrintf("%06ld SET CONF\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + _USBDCore_Standard_SetConfiguration(pCore); + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 11_Set Interface | 00_Host-to-Device | 00_Standard Request | 1_Interface | 0B01h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_11_SET_INF | REQ_DIR_00_H2D | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld SET INF\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + if (pCore->Class.CallBack_ClassSetInterface != NULL) + { + pCore->Class.CallBack_ClassSetInterface((USBDCore_Device_TypeDef *)&(pCore->Device)); + } + break; + } + /*------------------------------------------------------------------------------------------------------*/ + /* | 10_Get Interface | 80_Device-to-Host | 00_Standard Request | 1_Interface | 0A81h */ + /*------------------------------------------------------------------------------------------------------*/ + case (REQ_10_GET_INF | REQ_DIR_01_D2H | REQ_TYPE_00_STD | REQ_REC_01_INF): + { + __DBG_USBPrintf("%06ld GET INF\t[%02X]\r\n", __DBG_USBCount, pCore->Device.Request.wValueL); + if (pCore->Class.CallBack_ClassGetInterface != NULL) + { + pCore->Class.CallBack_ClassGetInterface((USBDCore_Device_TypeDef *)&(pCore->Device)); + } + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - GET_STATUS. + * @param pCore: pointer of USB Device + * @param recipient: Recipient + * @arg Device: 0 + * @arg Interface: 1 + * @arg Endpoint: 2 + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_GetStatus(USBDCore_TypeDef *pCore, USBDCore_Recipient_Enum recipient) +{ + pCore->Device.Transfer.uBuffer[1] = 0; + switch (recipient) + { + case Device: + { + pCore->Device.Transfer.uBuffer[0] = pCore->Info.CurrentFeature.uByte; + break; + } + case Interface: + { + pCore->Device.Transfer.uBuffer[0] = 0; + break; + } + case Endpoint: + { + pCore->Device.Transfer.uBuffer[0] = API_USB_EPTn_GET_HALT((USBD_EPTn_Enum)(pCore->Device.Request.wIndex & 0xF)); + break; + } + default: + { + return; + } + } + + pCore->Device.Transfer.pData = (uc8 *)&(pCore->Device.Transfer.uBuffer); + pCore->Device.Transfer.sByteLength = 2; + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - SET_FEATURE / CLEAR_FEATURE. + * @param pCore: pointer of USB Device + * @param recipient: Recipient + * @arg Device: 0 + * @arg Interface: 1 + * @arg Endpoint: 2 + * @param type: + * @arg ClearFeature: 0 + @arg SerFeature: 1 + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_SetClearFeature(USBDCore_TypeDef *pCore, + USBDCore_Recipient_Enum recipient, + USBDCore_SetClearFeature_Enum type) +{ + u32 i; + switch (recipient) + { + case Device: + { + if (pCore->Device.Request.wValueL == USB_FEATURE_REMOTE_WAKEUP) + { + pCore->Info.CurrentFeature.Bits.bRemoteWakeup = type; + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + } + break; + } + case Endpoint: + { + i = pCore->Device.Request.wIndex & 0xF; + if (i != 0) + { + if (type == ClearFeature) + { + if (pCore->Info.uIsDiscardClearFeature == FALSE) + { + API_USB_EPTn_CLR_HALT((USBD_EPTn_Enum)i); + API_USB_EPTn_CLR_DTG((USBD_EPTn_Enum)i); + } + } + else + { + API_USB_EPTn_SET_HALT((USBD_EPTn_Enum)i); + } + } + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + break; + } + default: + { + break; + } + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - SET_ADDRESS. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_SetAddress(USBDCore_TypeDef *pCore) +{ + API_USB_SET_ADDR(pCore->Device.Request.wValueL); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + pCore->Info.CurrentStatus = USB_STATE_ADDRESS; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - GET_DESCRIPTOR. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_GetDescriptor(USBDCore_TypeDef *pCore) +{ + u32 value = pCore->Device.Request.wValueH; + uc8 *pTemp; + + switch (value) + { + case DESC_TYPE_01_DEV: + { + pCore->Device.Transfer.pData = pCore->Device.Desc.pDeviceDesc; + pCore->Device.Transfer.sByteLength = *(pCore->Device.Desc.pDeviceDesc); + pCore->Device.Transfer.Action= USB_ACTION_DATAIN; + break; + } + case DESC_TYPE_02_CONFN: + { + pCore->Device.Transfer.pData = pCore->Device.Desc.pConfnDesc; + pCore->Device.Transfer.sByteLength = *(u16 *)((pCore->Device.Desc.pConfnDesc) + 2); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + break; + } + case DESC_TYPE_03_STR: + { + value = pCore->Device.Request.wValueL; + if (value < pCore->Device.Desc.uStringDescNumber) + { + if (*(pCore->Device.Desc.ppStringDesc + value) != NULL) + { + pTemp = *(pCore->Device.Desc.ppStringDesc + value); + pCore->Device.Transfer.pData = (uc8 *)(pTemp); + pCore->Device.Transfer.sByteLength = *(pTemp); + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + } + } + break; + } + } + + #ifdef USBD_VENDOR_SUPPORT + USBDVendor_StandardGetDescriptor(pCore); + #endif + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - GET_CONFIGURATION. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_GetConfiguration(USBDCore_TypeDef *pCore) +{ + pCore->Device.Transfer.pData = &(pCore->Info.uCurrentConfiguration); + pCore->Device.Transfer.sByteLength = 1; + pCore->Device.Transfer.Action= USB_ACTION_DATAIN; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Standard Request - SET_CONFIGURATION. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_Standard_SetConfiguration(USBDCore_TypeDef *pCore) +{ + u32 i; + + pCore->Info.uCurrentConfiguration = pCore->Device.Request.wValueL; + pCore->Device.Transfer.Action= USB_ACTION_DATAIN; + + /* Endpoint n settings */ + for (i = 1; i < MAX_EP_NUM; i++) + { + API_USB_EPTn_INIT((USBD_EPTn_Enum)i, pCore->pDriver); // To be modify, init from desc + } + + pCore->Info.CurrentStatus = USB_STATE_CONFIGURED; + + return; +} + +/*********************************************************************************************************//** + * @brief USB Control IN transfer. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_ControlIN(USBDCore_TypeDef *pCore) +{ + s32 EP0INLen = API_USB_GET_CTRL_IN_LEN(); + u32 len; + + if (pCore->Device.Transfer.sByteLength != USB_NO_DATA && pCore->Device.Transfer.Action == USB_ACTION_DATAIN) + { + if (pCore->Device.Transfer.sByteLength >= EP0INLen) + { + len = EP0INLen; + pCore->Device.Transfer.sByteLength -= len; + } + else + { + len = pCore->Device.Transfer.sByteLength; + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + pCore->Device.Transfer.Action = USB_ACTION_DATAOUT; + } + + __DBG_USBPrintf("[%02ld]\r\n", len); + __DBG_USBDump((uc8 *)pCore->Device.Transfer.pData, len); + + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32 *)pCore->Device.Transfer.pData, len); + pCore->Device.Transfer.pData = pCore->Device.Transfer.pData + len; + } + else + { + __DBG_USBPrintf("[-1]\r\n"); + } + + return; +} + +/*********************************************************************************************************//** + * @brief USB Control OUT transfer. + * @param pCore: pointer of USB Device + * @retval None + ***********************************************************************************************************/ +static void _USBDCore_ControlOUT(USBDCore_TypeDef *pCore) +{ + u32 len; + + if (pCore->Device.Transfer.sByteLength != USB_NO_DATA && pCore->Device.Transfer.Action == USB_ACTION_DATAOUT) + { + len = API_USB_EPTn_READ_OUT(USBD_EPT0, (u32 *)pCore->Device.Transfer.pData, MAX_CONTROL_OUT_SIZE); + + __DBG_USBPrintf("[%02ld]\r\n", len); + __DBG_USBDump((uc8 *)pCore->Device.Transfer.pData, len); + + pCore->Device.Transfer.pData = pCore->Device.Transfer.pData + len; + pCore->Device.Transfer.sByteLength -= len; + + if (pCore->Device.Transfer.sByteLength == 0) + { + pCore->Device.Transfer.Action = USB_ACTION_DATAIN; + if (pCore->Device.Transfer.CallBack_OUT.func != NULL) + { + pCore->Device.Transfer.CallBack_OUT.func(pCore->Device.Transfer.CallBack_OUT.uPara); + pCore->Device.Transfer.CallBack_OUT.func = NULL; + } + pCore->Device.Transfer.sByteLength = USB_NO_DATA; + API_USB_EPTn_WRITE_IN(USBD_EPT0, (u32 *)0, 0); + } + } + else + { + __DBG_USBPrintf("[-1]\r\n"); + } + + return; +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/ht32/libraries/Kconfig b/bsp/ht32/libraries/Kconfig new file mode 100644 index 00000000000..80395cb727a --- /dev/null +++ b/bsp/ht32/libraries/Kconfig @@ -0,0 +1,12 @@ +config SOC_FAMILY_HT32 + bool + +config SOC_SERIES_HT32F5 + bool + select ARCH_ARM_CORTEX_M0 + select SOC_FAMILY_HT32 + +config SOC_SERIES_HT32F1 + bool + select ARCH_ARM_CORTEX_M3 + select SOC_FAMILY_HT32 diff --git a/bsp/ht32/libraries/ht32_drivers/SConscript b/bsp/ht32/libraries/ht32_drivers/SConscript new file mode 100644 index 00000000000..10c92e8492d --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/SConscript @@ -0,0 +1,37 @@ +#导入其他模块中的变量 +Import('RTT_ROOT') +Import('rtconfig') + +#导入使用到的模块 +from building import * + +#获取当前目录的路径 +cwd = GetCurrentDir() + +#创建一个列表，用于保存需要使用到的C文件路径 +src = Split(""" +drv_common.c +""") +#drv_common.c +#根据宏定义来对需要用到的C文件进行裁剪 +if GetDepend(['BSP_USING_GPIO']): + src += ['drv_gpio.c'] + +if GetDepend(['BSP_USING_UART']): + src += ['drv_usart.c'] + +if GetDepend(['BSP_USING_SPI']): + src += ['drv_spi.c'] + +if GetDepend(['BSP_USING_I2C']): + src += ['drv_i2c.c'] + +#创建一个列表，用于保存需要包含的H文件路径 +path = [cwd] + +#创建一个组别 +group = DefineGroup('Drivers', src ,depend = [''], CPPPATH = path) + +#返回创建好的组别 +Return('group') + diff --git a/bsp/ht32/libraries/ht32_drivers/drv_common.c b/bsp/ht32/libraries/ht32_drivers/drv_common.c new file mode 100644 index 00000000000..1bdb6a36e1e --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_common.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include +#include "drv_common.h" +#ifdef RT_USING_SERIAL + #include "drv_usart.h" +#endif + +#ifdef RT_USING_FINSH +#include +static void reboot(uint8_t argc, char **argv) +{ + rt_hw_cpu_reset(); +} +MSH_CMD_EXPORT(reboot, Reboot System); +#endif /* RT_USING_FINSH */ + +/* SysTick configuration */ +void rt_hw_systick_init(void) +{ + SYSTICK_ClockSourceConfig(SYSTICK_SRC_STCLK); + SYSTICK_SetReloadValue(SystemCoreClock / 8 / RT_TICK_PER_SECOND); + SYSTICK_IntConfig(ENABLE); + SYSTICK_CounterCmd(SYSTICK_COUNTER_CLEAR); + SYSTICK_CounterCmd(SYSTICK_COUNTER_ENABLE); +} + +/* This is the timer interrupt service routine */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/* This function is executed in case of error occurrence */ +void _Error_Handler(char *s, int num) +{ + /* User can add his own implementation to report the error return state */ + LOG_E("Error_Handler at file:%s num:%d", s, num); + while (1) + { + } +} + +/* This function will initial HT32 board */ +void rt_hw_board_init(void) +{ + /* Configure the System clock */ + rt_hw_board_clock_init(); + + /* Configure the SysTick */ + rt_hw_systick_init(); + + /* heap initialization */ +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + + /* board underlying hardware initialization */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + + /* set the shell console output device */ +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +} diff --git a/bsp/ht32/libraries/ht32_drivers/drv_common.h b/bsp/ht32/libraries/ht32_drivers/drv_common.h new file mode 100644 index 00000000000..f35cb885a6f --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_common.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __DRV_COMMON_H__ +#define __DRV_COMMON_H__ + +#include +#include +#ifdef RT_USING_DEVICE + #include +#endif +#include "board.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void _Error_Handler(char *s, int num); + +#ifndef Error_Handler +#define Error_Handler() _Error_Handler(__FILE__, __LINE__) +#endif + +#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/ht32/libraries/ht32_drivers/drv_gpio.c b/bsp/ht32/libraries/ht32_drivers/drv_gpio.c new file mode 100644 index 00000000000..5df27aad7b1 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_gpio.c @@ -0,0 +1,910 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "drv_gpio.h" + +#ifdef RT_USING_PIN + +#define __HT32_PIN(index, gpio, pin) \ + { \ + index, HT_GPIO##gpio, GPIO_PIN_##pin \ + } + +struct pin_index +{ + int index; + HT_GPIO_TypeDef *gpio; + uint32_t pin; +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; + +static const struct pin_index pins[] = +{ +#if defined(HT_GPIOA) + __HT32_PIN(0, A, 0), + __HT32_PIN(1, A, 1), + __HT32_PIN(2, A, 2), + __HT32_PIN(3, A, 3), + __HT32_PIN(4, A, 4), + __HT32_PIN(5, A, 5), + __HT32_PIN(6, A, 6), + __HT32_PIN(7, A, 7), + __HT32_PIN(8, A, 8), + __HT32_PIN(9, A, 9), + __HT32_PIN(10, A, 10), + __HT32_PIN(11, A, 11), + __HT32_PIN(12, A, 12), + __HT32_PIN(13, A, 13), + __HT32_PIN(14, A, 14), + __HT32_PIN(15, A, 15), +#if defined(HT_GPIOB) + __HT32_PIN(16, B, 0), + __HT32_PIN(17, B, 1), + __HT32_PIN(18, B, 2), + __HT32_PIN(19, B, 3), + __HT32_PIN(20, B, 4), + __HT32_PIN(21, B, 5), + __HT32_PIN(22, B, 6), + __HT32_PIN(23, B, 7), + __HT32_PIN(24, B, 8), + __HT32_PIN(25, B, 9), + __HT32_PIN(26, B, 10), + __HT32_PIN(27, B, 11), + __HT32_PIN(28, B, 12), + __HT32_PIN(29, B, 13), + __HT32_PIN(30, B, 14), + __HT32_PIN(31, B, 15), +#if defined(HT_GPIOC) + __HT32_PIN(32, C, 0), + __HT32_PIN(33, C, 1), + __HT32_PIN(34, C, 2), + __HT32_PIN(35, C, 3), + __HT32_PIN(36, C, 4), + __HT32_PIN(37, C, 5), + __HT32_PIN(38, C, 6), + __HT32_PIN(39, C, 7), + __HT32_PIN(40, C, 8), + __HT32_PIN(41, C, 9), + __HT32_PIN(42, C, 10), + __HT32_PIN(43, C, 11), + __HT32_PIN(44, C, 12), + __HT32_PIN(45, C, 13), + __HT32_PIN(46, C, 14), + __HT32_PIN(47, C, 15), +#if defined(HT_GPIOD) + __HT32_PIN(48, D, 0), + __HT32_PIN(49, D, 1), + __HT32_PIN(50, D, 2), + __HT32_PIN(51, D, 3), + __HT32_PIN(52, D, 4), + __HT32_PIN(53, D, 5), + __HT32_PIN(54, D, 6), + __HT32_PIN(55, D, 7), + __HT32_PIN(56, D, 8), + __HT32_PIN(57, D, 9), + __HT32_PIN(58, D, 10), + __HT32_PIN(59, D, 11), + __HT32_PIN(60, D, 12), + __HT32_PIN(61, D, 13), + __HT32_PIN(62, D, 14), + __HT32_PIN(63, D, 15), +#if defined(HT_GPIOE) + __HT32_PIN(64, E, 0), + __HT32_PIN(65, E, 1), + __HT32_PIN(66, E, 2), + __HT32_PIN(67, E, 3), + __HT32_PIN(68, E, 4), + __HT32_PIN(69, E, 5), + __HT32_PIN(70, E, 6), + __HT32_PIN(71, E, 7), + __HT32_PIN(72, E, 8), + __HT32_PIN(73, E, 9), + __HT32_PIN(74, E, 10), + __HT32_PIN(75, E, 11), + __HT32_PIN(76, E, 12), + __HT32_PIN(77, E, 13), + __HT32_PIN(78, E, 14), + __HT32_PIN(79, E, 15), +#if defined(HT_GPIOF) + __HT32_PIN(80, F, 0), + __HT32_PIN(81, F, 1), + __HT32_PIN(82, F, 2), + __HT32_PIN(83, F, 3), + __HT32_PIN(84, F, 4), + __HT32_PIN(85, F, 5), + __HT32_PIN(86, F, 6), + __HT32_PIN(87, F, 7), + __HT32_PIN(88, F, 8), + __HT32_PIN(89, F, 9), + __HT32_PIN(90, F, 10), + __HT32_PIN(91, F, 11), + __HT32_PIN(92, F, 12), + __HT32_PIN(93, F, 13), + __HT32_PIN(94, F, 14), + __HT32_PIN(95, F, 15), +#endif /* defined(HT_GPIOF) */ +#endif /* defined(HT_GPIOE) */ +#endif /* defined(HT_GPIOD) */ +#endif /* defined(HT_GPIOC) */ +#endif /* defined(HT_GPIOB) */ +#endif /* defined(HT_GPIOA) */ +}; + +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI5_IRQn}, + {GPIO_PIN_6, EXTI6_IRQn}, + {GPIO_PIN_7, EXTI7_IRQn}, + {GPIO_PIN_8, EXTI8_IRQn}, + {GPIO_PIN_9, EXTI9_IRQn}, + {GPIO_PIN_10, EXTI10_IRQn}, + {GPIO_PIN_11, EXTI11_IRQn}, + {GPIO_PIN_12, EXTI12_IRQn}, + {GPIO_PIN_13, EXTI13_IRQn}, + {GPIO_PIN_14, EXTI14_IRQn}, + {GPIO_PIN_15, EXTI15_IRQn}, +}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +static const struct pin_index *get_pin(rt_uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + return index; +} + +static void ht32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) +{ + const struct pin_index *index; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + if ((index->gpio) == HT_GPIOA) + CKCUClock.Bit.PA = 1; + else if ((index->gpio) == HT_GPIOB) + CKCUClock.Bit.PB = 1; +#if defined(HT_GPIOC) + else if ((index->gpio) == HT_GPIOC) + CKCUClock.Bit.PC = 1; +#endif +#if defined(HT_GPIOD) + else if ((index->gpio) == HT_GPIOD) + CKCUClock.Bit.PD = 1; +#endif +#if defined(HT_GPIOE) + else if ((index->gpio) == HT_GPIOE) + CKCUClock.Bit.PE = 1; +#endif +#if defined(HT_GPIOF) + else if ((index->gpio) == HT_GPIOF) + CKCUClock.Bit.PF = 1; +#endif + CKCUClock.Bit.AFIO = 1; + CKCUClock.Bit.BKP = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + if ((index->gpio) == HT_GPIOA) + AFIO_GPxConfig(GPIO_PA, index->pin, AFIO_MODE_1); + else if ((index->gpio) == HT_GPIOB) + AFIO_GPxConfig(GPIO_PB, index->pin, AFIO_MODE_1); +#if defined(HT_GPIOC) + else if ((index->gpio) == HT_GPIOC) + AFIO_GPxConfig(GPIO_PC, index->pin, AFIO_MODE_1); +#endif +#if defined(HT_GPIOD) + else if ((index->gpio) == HT_GPIOD) + AFIO_GPxConfig(GPIO_PD, index->pin, AFIO_MODE_1); +#endif +#if defined(HT_GPIOE) + else if ((index->gpio) == HT_GPIOE) + AFIO_GPxConfig(GPIO_PE, index->pin, AFIO_MODE_1); +#endif +#if defined(HT_GPIOF) + else if ((index->gpio) == HT_GPIOF) + AFIO_GPxConfig(GPIO_PF, index->pin, AFIO_MODE_1); +#endif + + switch (mode) + { + case PIN_MODE_OUTPUT: + /* output setting */ + GPIO_DirectionConfig(index->gpio, index->pin, GPIO_DIR_OUT); + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_DISABLE); + break; + case PIN_MODE_OUTPUT_OD: + /* output setting: od. */ + GPIO_DirectionConfig(index->gpio, index->pin, GPIO_DIR_OUT); + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_DISABLE); + break; + case PIN_MODE_INPUT: + /* input setting: not pull. */ + GPIO_DirectionConfig(index->gpio, index->pin, GPIO_DIR_IN); + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_DISABLE); + GPIO_InputConfig(index->gpio, index->pin, ENABLE); + break; + case PIN_MODE_INPUT_PULLUP: + /* input setting: pull up. */ + GPIO_DirectionConfig(index->gpio, index->pin, GPIO_DIR_IN); + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_UP); + GPIO_InputConfig(index->gpio, index->pin, ENABLE); + break; + case PIN_MODE_INPUT_PULLDOWN: + /* input setting: pull down. */ + GPIO_DirectionConfig(index->gpio, index->pin, GPIO_DIR_IN); + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_DOWN); + GPIO_InputConfig(index->gpio, index->pin, ENABLE); + break; + default: + break; + } +} + +static void ht32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + if (value == PIN_LOW) + { + GPIO_ClearOutBits(index->gpio, index->pin); + } + else + { + GPIO_SetOutBits(index->gpio, index->pin); + } +} + +static rt_ssize_t ht32_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + value = PIN_LOW; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + value = GPIO_ReadInBit(index->gpio, index->pin); + return value; +} + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + rt_uint8_t i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} + +rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +} + +static rt_err_t ht32_pin_attach_irq(struct rt_device *device, + rt_base_t pin, + rt_uint8_t mode, + void (*hdr)(void *args), + void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t hdr_index = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ERROR; + } + + hdr_index = bit2bitno(index->pin); + + if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) + { + return RT_ERROR; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[hdr_index].pin == pin && + pin_irq_hdr_tab[hdr_index].hdr == hdr && + pin_irq_hdr_tab[hdr_index].mode == mode && + pin_irq_hdr_tab[hdr_index].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[hdr_index].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_ERROR; + } + pin_irq_hdr_tab[hdr_index].pin = pin; + pin_irq_hdr_tab[hdr_index].hdr = hdr; + pin_irq_hdr_tab[hdr_index].mode = mode; + pin_irq_hdr_tab[hdr_index].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t ht32_pin_detach_irq(struct rt_device *device, rt_base_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t hdr_index = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ERROR; + } + + hdr_index = bit2bitno(index->pin); + if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) + { + return RT_ERROR; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[hdr_index].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[hdr_index].pin = -1; + pin_irq_hdr_tab[hdr_index].hdr = RT_NULL; + pin_irq_hdr_tab[hdr_index].mode = 0; + pin_irq_hdr_tab[hdr_index].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t ht32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t hdr_index = -1; + EXTI_InitTypeDef EXTI_InitStruct; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ERROR; + } + if (enabled == PIN_IRQ_ENABLE) + { + hdr_index = bit2bitno(index->pin); + if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) + { + return RT_ERROR; + } + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[hdr_index].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ERROR; + } + + irqmap = &pin_irq_map[hdr_index]; + + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + CKCUClock.Bit.AFIO = 1; + CKCUClock.Bit.EXTI = 1; + + if ((index->gpio) == HT_GPIOA) + CKCUClock.Bit.PA = 1; + else if ((index->gpio) == HT_GPIOB) + CKCUClock.Bit.PB = 1; +#if defined(HT_GPIOC) + else if ((index->gpio) == HT_GPIOC) + CKCUClock.Bit.PC = 1; +#endif +#if defined(HT_GPIOD) + else if ((index->gpio) == HT_GPIOD) + CKCUClock.Bit.PD = 1; +#endif +#if defined(HT_GPIOE) + else if ((index->gpio) == HT_GPIOE) + CKCUClock.Bit.PE = 1; +#endif +#if defined(HT_GPIOF) + else if ((index->gpio) == HT_GPIOF) + CKCUClock.Bit.PF = 1; +#endif + + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + if ((index->gpio) == HT_GPIOA) + { + AFIO_GPxConfig(GPIO_PA, index->pin, AFIO_MODE_1); + GPIO_InputConfig(HT_GPIOA, index->pin, ENABLE); + AFIO_EXTISourceConfig(hdr_index, AFIO_ESS_PA); + } + else if ((index->gpio) == HT_GPIOB) + { + AFIO_GPxConfig(GPIO_PB, index->pin, AFIO_MODE_1); + GPIO_InputConfig(HT_GPIOB, index->pin, ENABLE); + AFIO_EXTISourceConfig(hdr_index, AFIO_ESS_PB); + } +#if defined(HT_GPIOC) + else if ((index->gpio) == HT_GPIOC) + { + AFIO_GPxConfig(GPIO_PC, index->pin, AFIO_MODE_1); + GPIO_InputConfig(HT_GPIOC, index->pin, ENABLE); + AFIO_EXTISourceConfig(hdr_index, AFIO_ESS_PC); + } +#endif +#if defined(HT_GPIOD) + else if ((index->gpio) == HT_GPIOD) + { + AFIO_GPxConfig(GPIO_PD, index->pin, AFIO_MODE_1); + GPIO_InputConfig(HT_GPIOD, index->pin, ENABLE); + AFIO_EXTISourceConfig(hdr_index, AFIO_ESS_PD); + } +#endif +#if defined(HT_GPIOE) + else if ((index->gpio) == HT_GPIOE) + { + AFIO_GPxConfig(GPIO_PE, index->pin, AFIO_MODE_1); + GPIO_InputConfig(HT_GPIOE, index->pin, ENABLE); + AFIO_EXTISourceConfig(hdr_index, AFIO_ESS_PE); + } +#endif +#if defined(HT_GPIOF) + else if ((index->gpio) == HT_GPIOF) + { + AFIO_GPxConfig(GPIO_PF, index->pin, AFIO_MODE_1); + GPIO_InputConfig(HT_GPIOF, index->pin, ENABLE); + AFIO_EXTISourceConfig(hdr_index, AFIO_ESS_PF); + } +#endif + + switch (pin_irq_hdr_tab[hdr_index].mode) + { + case PIN_IRQ_MODE_RISING: + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_DOWN); + EXTI_InitStruct.EXTI_IntType = EXTI_POSITIVE_EDGE; + break; + case PIN_IRQ_MODE_FALLING: + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_UP); + EXTI_InitStruct.EXTI_IntType = EXTI_NEGATIVE_EDGE; + break; + case PIN_IRQ_MODE_RISING_FALLING: + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_DISABLE); + EXTI_InitStruct.EXTI_IntType = EXTI_BOTH_EDGE; + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_DOWN); + EXTI_InitStruct.EXTI_IntType = EXTI_HIGH_LEVEL; + break; + case PIN_IRQ_MODE_LOW_LEVEL: + GPIO_PullResistorConfig(index->gpio, index->pin, GPIO_PR_UP); + EXTI_InitStruct.EXTI_IntType = EXTI_LOW_LEVEL; + break; + default: + rt_hw_interrupt_enable(level); + return RT_ERROR; + } + + EXTI_InitStruct.EXTI_Channel = hdr_index; + + EXTI_InitStruct.EXTI_Debounce = EXTI_DEBOUNCE_DISABLE; + EXTI_InitStruct.EXTI_DebounceCnt = 0; + EXTI_Init(&EXTI_InitStruct); + + EXTI_IntConfig(hdr_index, ENABLE); + + NVIC_EnableIRQ((irqmap->irqno)); + rt_hw_interrupt_enable(level); + } + + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_ERROR; + } + if ((irqmap->irqno) == EXTI0_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_0, DISABLE); + else if ((irqmap->irqno) == EXTI1_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_1, DISABLE); + else if ((irqmap->irqno) == EXTI2_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_2, DISABLE); + else if ((irqmap->irqno) == EXTI3_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_3, DISABLE); + else if ((irqmap->irqno) == EXTI4_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_4, DISABLE); + else if ((irqmap->irqno) == EXTI5_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_5, DISABLE); + else if ((irqmap->irqno) == EXTI6_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_6, DISABLE); + else if ((irqmap->irqno) == EXTI7_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_7, DISABLE); + else if ((irqmap->irqno) == EXTI8_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_8, DISABLE); + else if ((irqmap->irqno) == EXTI9_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_9, DISABLE); + else if ((irqmap->irqno) == EXTI10_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_10, DISABLE); + else if ((irqmap->irqno) == EXTI11_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_11, DISABLE); + else if ((irqmap->irqno) == EXTI12_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_12, DISABLE); + else if ((irqmap->irqno) == EXTI13_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_13, DISABLE); + else if ((irqmap->irqno) == EXTI14_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_14, DISABLE); + else if ((irqmap->irqno) == EXTI15_IRQn) + EXTI_IntConfig(EXTI_CHANNEL_15, DISABLE); + } + else + { + return RT_ERROR; + } + return RT_EOK; +} + +const static struct rt_pin_ops _ht32_pin_ops = +{ + .pin_mode = ht32_pin_mode, + .pin_write = ht32_pin_write, + .pin_read = ht32_pin_read, + .pin_attach_irq = ht32_pin_attach_irq, + .pin_detach_irq = ht32_pin_detach_irq, + .pin_irq_enable = ht32_pin_irq_enable, + .pin_get = NULL, +}; + +int rt_hw_pin_init(void) +{ + int result; + + result = rt_device_pin_register("pin", &_ht32_pin_ops, RT_NULL); + + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} +#ifdef SOC_SERIES_HT32F5 +void EXTI0_1_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_0, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_0); + pin_irq_hdr(0); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_1, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_1); + pin_irq_hdr(1); + } + rt_interrupt_leave(); +} + +void EXTI2_3_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_2, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_2); + pin_irq_hdr(2); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_3, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_3); + pin_irq_hdr(3); + } + rt_interrupt_leave(); +} + +void EXTI4_15_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_4, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_4); + pin_irq_hdr(4); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_5, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_5); + pin_irq_hdr(5); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_6, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_6); + pin_irq_hdr(6); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_7, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_7); + pin_irq_hdr(7); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_8, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_8); + pin_irq_hdr(8); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_9, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_9); + pin_irq_hdr(9); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_10, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_10); + pin_irq_hdr(10); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_11, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_11); + pin_irq_hdr(11); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_12, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_12); + pin_irq_hdr(12); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_13, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_13); + pin_irq_hdr(13); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_14, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_14); + pin_irq_hdr(14); + } + else if (EXTI_GetEdgeStatus(EXTI_CHANNEL_15, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_15); + pin_irq_hdr(15); + } + rt_interrupt_leave(); +} +#endif + +#ifdef SOC_SERIES_HT32F1 +void EXTI0_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_0, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_0); + pin_irq_hdr(0); + } + rt_interrupt_leave(); +} +void EXTI1_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_1, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_1); + pin_irq_hdr(1); + } + rt_interrupt_leave(); +} +void EXTI2_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_2, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_2); + pin_irq_hdr(2); + } + rt_interrupt_leave(); +} +void EXTI3_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_3, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_3); + pin_irq_hdr(3); + } + rt_interrupt_leave(); +} +void EXTI4_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_4, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_4); + pin_irq_hdr(4); + } + rt_interrupt_leave(); +} +void EXTI5_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_5, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_5); + pin_irq_hdr(5); + } + rt_interrupt_leave(); +} +void EXTI6_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_6, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_6); + pin_irq_hdr(6); + } + rt_interrupt_leave(); +} +void EXTI7_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_7, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_7); + pin_irq_hdr(7); + } + rt_interrupt_leave(); +} +void EXTI8_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_8, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_8); + pin_irq_hdr(8); + } + rt_interrupt_leave(); +} +void EXTI9_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_9, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_9); + pin_irq_hdr(9); + } + rt_interrupt_leave(); +} +void EXTI10_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_10, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_10); + pin_irq_hdr(10); + } + rt_interrupt_leave(); +} +void EXTI11_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_11, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_11); + pin_irq_hdr(11); + } + rt_interrupt_leave(); +} +void EXTI12_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_12, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_12); + pin_irq_hdr(12); + } + rt_interrupt_leave(); +} +void EXTI13_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_13, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_13); + pin_irq_hdr(13); + } + rt_interrupt_leave(); +} +void EXTI14_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_14, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_14); + pin_irq_hdr(14); + } + rt_interrupt_leave(); +} +void EXTI15_IRQHandler(void) +{ + rt_interrupt_enter(); + if (EXTI_GetEdgeStatus(EXTI_CHANNEL_15, EXTI_EDGE_POSITIVE)) + { + EXTI_ClearEdgeFlag(EXTI_CHANNEL_15); + pin_irq_hdr(15); + } + rt_interrupt_leave(); +} +#endif + +#endif diff --git a/bsp/ht32/libraries/ht32_drivers/drv_gpio.h b/bsp/ht32/libraries/ht32_drivers/drv_gpio.h new file mode 100644 index 00000000000..01ec12fc247 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_gpio.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include +#include "drv_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define __HT32_PORT(port) HT_GPIO##port##_BASE + +#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__HT32_PORT(PORTx) - (rt_base_t)HT_GPIOA_BASE)/(0x2000UL) )) + PIN) + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_i2c.c b/bsp/ht32/libraries/ht32_drivers/drv_i2c.c new file mode 100644 index 00000000000..edf98127c50 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_i2c.c @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "drv_i2c.h" + +#ifdef RT_USING_I2C +#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1) + #error "Please define at least one BSP_USING_I2Cx" + /* this driver can be disabled at menuconfig RT-Thread Components Device Drivers */ +#endif + +struct ht32_i2c_config +{ + HT_I2C_TypeDef *i2c_x; + const char *i2c_name; + IRQn_Type irq; +}; + +struct ht32_i2c +{ + struct ht32_i2c_config *config; + struct rt_i2c_bus_device i2c_bus; +}; + +enum +{ +#ifdef BSP_USING_I2C0 + I2C0_INDEX, +#endif +#ifdef BSP_USING_I2C1 + I2C1_INDEX, +#endif +}; + +static struct ht32_i2c_config i2c_config[] = +{ +#ifdef BSP_USING_I2C0 + {HT_I2C0, "i2c0", I2C0_IRQn}, +#endif +#ifdef BSP_USING_I2C1 + {HT_I2C1, "i2c1", I2C1_IRQn}, +#endif +}; + +static struct ht32_i2c i2cs[sizeof(i2c_config) / sizeof(i2c_config[0])] = {0}; + +static rt_size_t ht32_i2c_init(struct ht32_i2c *i2c_drv) +{ + struct ht32_i2c_config *i2c_config = i2c_drv->config; + + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; +#ifdef BSP_USING_I2C0 + if (HT_I2C0 == i2c_config->i2c_x) + { + CKCUClock.Bit.I2C0 = 1; + } +#endif +#ifdef BSP_USING_I2C1 + if (HT_I2C1 == i2c_config->i2c_x) + { + CKCUClock.Bit.I2C1 = 1; + } +#endif + CKCUClock.Bit.AFIO = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + ht32_i2c_gpio_init(i2c_config->i2c_x); + + I2C_InitTypeDef I2C_InitStructure; + I2C_InitStructure.I2C_GeneralCall = DISABLE; + I2C_InitStructure.I2C_AddressingMode = I2C_ADDRESSING_7BIT; + I2C_InitStructure.I2C_Acknowledge = DISABLE; + I2C_InitStructure.I2C_OwnAddress = 0x00; + I2C_InitStructure.I2C_Speed = 400000; + I2C_InitStructure.I2C_SpeedOffset = 0; + + I2C_Init(i2c_config->i2c_x, &I2C_InitStructure); + I2C_Cmd(i2c_config->i2c_x, ENABLE); + + return RT_EOK; +} + +static int ht32_i2c_read(struct ht32_i2c_config *hi2c, + rt_uint16_t slave_address, + rt_uint8_t *p_buffer, + rt_uint16_t data_byte) +{ + uint16_t date_num = 0; + uint8_t data = 0xFF; + + I2C_TargetAddressConfig(hi2c->i2c_x, slave_address, I2C_MASTER_READ); + while (!I2C_CheckStatus(hi2c->i2c_x, I2C_MASTER_SEND_START)); + while (!I2C_CheckStatus(hi2c->i2c_x, I2C_MASTER_RECEIVER_MODE)); + I2C_AckCmd(hi2c->i2c_x, ENABLE); + while (date_num < data_byte) + { + date_num++; + + while (!I2C_CheckStatus(hi2c->i2c_x, I2C_MASTER_RX_NOT_EMPTY)); + data = I2C_ReceiveData(hi2c->i2c_x); + + if (date_num == (data_byte - 1)) + { + I2C_AckCmd(hi2c->i2c_x, DISABLE); + } + if (p_buffer != RT_NULL) + { + *p_buffer++ = data; + } + } + I2C_GenerateSTOP(hi2c->i2c_x); + while (I2C_ReadRegister(hi2c->i2c_x, I2C_REGISTER_SR) & 0x80000); + + return 0; +} + +static int ht32_i2c_write(struct ht32_i2c_config *hi2c, + uint16_t slave_address, + uint8_t *p_buffer, + uint16_t data_byte) +{ + uint16_t date_num = data_byte; + + I2C_TargetAddressConfig(hi2c->i2c_x, slave_address, I2C_MASTER_WRITE); + + while (!I2C_CheckStatus(hi2c->i2c_x, I2C_MASTER_SEND_START)); + + while (!I2C_CheckStatus(hi2c->i2c_x, I2C_MASTER_TRANSMITTER_MODE)); + while (date_num--) + { + while (!I2C_CheckStatus(hi2c->i2c_x, I2C_MASTER_TX_EMPTY)); + I2C_SendData(hi2c->i2c_x, *p_buffer++); + } + + while (!I2C_CheckStatus(hi2c->i2c_x, I2C_MASTER_TX_EMPTY)); + I2C_GenerateSTOP(hi2c->i2c_x); + while (I2C_ReadRegister(hi2c->i2c_x, I2C_REGISTER_SR) & 0x80000); + return 0; +} + +static rt_ssize_t ht32_master_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + struct ht32_i2c *i2c_instance; + struct rt_i2c_msg *msg; + rt_uint32_t i; + + i2c_instance = rt_container_of(bus, struct ht32_i2c, i2c_bus); + RT_ASSERT(bus != RT_NULL); + RT_ASSERT(msgs != RT_NULL); + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + + if (msg->flags & RT_I2C_RD) + { + if (ht32_i2c_read(i2c_instance->config, msg->addr, msg->buf, msg->len) != 0) + { + return i; + } + } + else + { + if (ht32_i2c_write(i2c_instance->config, msg->addr, msg->buf, msg->len) != 0) + { + return i; + } + } + } + return i; +} + +static struct rt_i2c_bus_device_ops ht32_i2c_ops = +{ + .master_xfer = ht32_master_xfer, + .slave_xfer = RT_NULL, + .i2c_bus_control = RT_NULL +}; + +int rt_hw_i2c_init(void) +{ + int i; + rt_err_t result; + rt_size_t obj_num = sizeof(i2cs) / sizeof(struct ht32_i2c); + + for (i = 0; i < obj_num; i++) + { + i2cs[i].config = &i2c_config[i]; + i2cs[i].i2c_bus.parent.user_data = (void *)&i2cs[i]; + i2cs[i].i2c_bus.ops = &ht32_i2c_ops; + + ht32_i2c_init(&i2cs[i]); + result = rt_i2c_bus_device_register(&i2cs[i].i2c_bus, i2cs[i].config->i2c_name); + } + return result; +} +INIT_BOARD_EXPORT(rt_hw_i2c_init); + +#endif /* RT_USING_I2C */ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_i2c.h b/bsp/ht32/libraries/ht32_drivers/drv_i2c.h new file mode 100644 index 00000000000..186aa12b535 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_i2c.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + +#include +#include +#ifdef RT_USING_DEVICE + #include +#endif +#include "drv_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_I2C_H__ */ + diff --git a/bsp/ht32/libraries/ht32_drivers/drv_spi.c b/bsp/ht32/libraries/ht32_drivers/drv_spi.c new file mode 100644 index 00000000000..c01867c909a --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_spi.c @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include +#include "drv_spi.h" + +#ifdef RT_USING_SPI +#if !defined(BSP_USING_SPI0) && !defined(BSP_USING_SPI1) + #error "Please define at least one BSP_USING_SPIx" +#endif + +struct ht32_spi_config +{ + HT_SPI_TypeDef *spi_x; + const char *spi_name; + IRQn_Type irq; +}; + +struct ht32_spi +{ + struct ht32_spi_config *config; + struct rt_spi_bus spi_bus; +}; + +struct ht32_spi_cs +{ + HT_GPIO_TypeDef *gpio_x; + uint32_t gpio_pin; +}; + +enum +{ +#ifdef BSP_USING_SPI0 + SPI0_INDEX, +#endif +#ifdef BSP_USING_SPI1 + SPI1_INDEX, +#endif +}; + +static struct ht32_spi_config spi_config[] = +{ +#ifdef BSP_USING_SPI0 + {HT_SPI0, "spi0", SPI0_IRQn}, +#endif +#ifdef BSP_USING_SPI1 + {HT_SPI1, "spi1", SPI1_IRQn}, +#endif +}; + +static struct ht32_spi spis[sizeof(spi_config) / sizeof(spi_config[0])] = {0}; + +/* attach the spi device to spi bus, this function must be used after initialization */ +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, HT_GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin) +{ + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + rt_err_t result; + struct rt_spi_device *spi_device; + struct ht32_spi_cs *cs_pin; + + if ((cs_gpiox) == HT_GPIOA) + { + CKCUClock.Bit.PA = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + AFIO_GPxConfig(GPIO_PA, cs_gpio_pin, AFIO_FUN_GPIO); + } + else if ((cs_gpiox) == HT_GPIOB) + { + CKCUClock.Bit.PB = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + AFIO_GPxConfig(GPIO_PB, cs_gpio_pin, AFIO_FUN_GPIO); + } +#if defined(HT_GPIOC) + else if ((cs_gpiox) == HT_GPIOC) + { + CKCUClock.Bit.PC = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + AFIO_GPxConfig(GPIO_PC, cs_gpio_pin, AFIO_FUN_GPIO); + } +#endif +#if defined(HT_GPIOD) + else if ((cs_gpiox) == HT_GPIOD) + { + CKCUClock.Bit.PD = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + AFIO_GPxConfig(GPIO_PD, cs_gpio_pin, AFIO_FUN_GPIO); + } +#endif +#if defined(HT_GPIOE) + else if ((cs_gpiox) == HT_GPIOE) + { + CKCUClock.Bit.PE = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + AFIO_GPxConfig(GPIO_PE, cs_gpio_pin, AFIO_FUN_GPIO); + } +#endif +#if defined(HT_GPIOF) + else if ((cs_gpiox) == HT_GPIOF) + { + CKCUClock.Bit.PF = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + AFIO_GPxConfig(GPIO_PF, cs_gpio_pin, AFIO_FUN_GPIO); + } +#endif + GPIO_PullResistorConfig(cs_gpiox, cs_gpio_pin, GPIO_PR_DISABLE); + GPIO_WriteOutBits(cs_gpiox, cs_gpio_pin, SET); + GPIO_DirectionConfig(cs_gpiox, cs_gpio_pin, GPIO_DIR_OUT); + + /* attach the device to spi bus */ + spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + cs_pin = (struct ht32_spi_cs *)rt_malloc(sizeof(struct ht32_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + cs_pin->gpio_x = cs_gpiox; + cs_pin->gpio_pin = cs_gpio_pin; + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + if (result != RT_EOK) + { + LOG_D("%s attach to %s faild, %d\n", device_name, bus_name, result); + } + + RT_ASSERT(result == RT_EOK); + + LOG_D("%s attach to %s done", device_name, bus_name); + + return result; +} + +static rt_err_t ht32_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) +{ + struct rt_spi_bus *spi_bus = (struct rt_spi_bus *)device->bus; + struct ht32_spi *spi_instance = (struct ht32_spi *)spi_bus->parent.user_data; + + SPI_InitTypeDef SPI_InitStructure; + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); +#ifdef BSP_USING_SPI0 + if (HT_SPI0 == spi_instance->config->spi_x) + { + CKCUClock.Bit.SPI0 = 1; + } +#endif +#ifdef BSP_USING_SPI1 + if (HT_SPI1 == spi_instance->config->spi_x) + { + CKCUClock.Bit.SPI1 = 1; + } +#endif + CKCUClock.Bit.AFIO = 1; + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + ht32_spi_gpio_init(spi_instance->config->spi_x); + + /* data_width */ + if (configuration->data_width <= 8) + { + SPI_InitStructure.SPI_DataLength = SPI_DATALENGTH_8; + } + else if (configuration->data_width <= 16) + { + SPI_InitStructure.SPI_DataLength = SPI_DATALENGTH_16; + } + else + { + return RT_ERROR; + } + + /* Set the polarity and phase of the SPI */ + switch (configuration->mode & RT_SPI_MODE_3) + { + case RT_SPI_MODE_0: + SPI_InitStructure.SPI_CPOL = SPI_CPOL_LOW; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_FIRST; + break; + case RT_SPI_MODE_1: + SPI_InitStructure.SPI_CPOL = SPI_CPOL_LOW; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_SECOND; + break; + case RT_SPI_MODE_2: + SPI_InitStructure.SPI_CPOL = SPI_CPOL_HIGH; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_FIRST; + break; + case RT_SPI_MODE_3: + SPI_InitStructure.SPI_CPOL = SPI_CPOL_HIGH; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_SECOND; + break; + } + + /* Set the SPI as a master or slave */ + SPI_InitStructure.SPI_Mode = (configuration->mode & RT_SPI_SLAVE) ? (SPI_SLAVE) : (SPI_MASTER); + + /* Set the data high or low first */ + SPI_InitStructure.SPI_FirstBit = (configuration->mode & RT_SPI_MSB) ? (SPI_FIRSTBIT_MSB) : (SPI_FIRSTBIT_LSB); + + /* SEL uses software by default */ + SPI_InitStructure.SPI_SELMode = SPI_SEL_SOFTWARE; + + /* SEL effective level */ + SPI_InitStructure.SPI_SELPolarity = (configuration->mode & RT_SPI_CS_HIGH) ? (SPI_SELPOLARITY_HIGH) : (SPI_SELPOLARITY_LOW); + + /* Configure the SCK clock frequency of the SPI */ + if (configuration->max_hz < 0xFFFF) + { + SPI_InitStructure.SPI_ClockPrescaler = ((configuration->max_hz) & 0xFFFF); + } + else + { + return RT_ERROR; + } + + SPI_InitStructure.SPI_FIFO = SPI_FIFO_DISABLE; + SPI_InitStructure.SPI_RxFIFOTriggerLevel = 0; + SPI_InitStructure.SPI_TxFIFOTriggerLevel = 0; + SPI_Init(spi_instance->config->spi_x, &SPI_InitStructure); +#if (!LIBCFG_SPI_NO_MULTI_MASTER) + SPI_SELOutputCmd(spi_instance->config->spi_x, ENABLE); +#endif + + SPI_Cmd(spi_instance->config->spi_x, ENABLE); + return RT_EOK; +} + +static rt_ssize_t ht32_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + struct rt_spi_bus *ht32_spi_bus = (struct rt_spi_bus *)device->bus; + struct ht32_spi *spi_instance = (struct ht32_spi *)ht32_spi_bus->parent.user_data; + struct rt_spi_configuration *config = &device->config; + struct ht32_spi_cs *ht32_spi_cs = device->parent.user_data; + + RT_ASSERT(device != NULL); + RT_ASSERT(message != NULL); + + /* take cs */ + if (message->cs_take) + { + GPIO_ClearOutBits(ht32_spi_cs->gpio_x, ht32_spi_cs->gpio_pin); + LOG_D("spi take cs\n"); + } + + if (config->data_width <= 8) + { + const rt_uint8_t *send_ptr = message->send_buf; + rt_uint8_t *recv_ptr = message->recv_buf; + rt_uint32_t size = message->length; + + LOG_D("spi poll transfer start: %d\n", size); + + while (size--) + { + rt_uint8_t data = 0xFF; + + if (send_ptr != RT_NULL) + { + data = *send_ptr++; + } + + /* wait until the transmit buffer is empty */ + while (SPI_GetFlagStatus(spi_instance->config->spi_x, SPI_FLAG_TXE) == RESET); + /* send the byte */ + SPI_SendData(spi_instance->config->spi_x, data); + + /* wait until a data is received */ + while (SPI_GetFlagStatus(spi_instance->config->spi_x, SPI_INT_RXBNE) == RESET); + /* get the received data */ + data = SPI_ReceiveData(spi_instance->config->spi_x); + + if (recv_ptr != RT_NULL) + { + *recv_ptr++ = data; + } + } + LOG_D("spi poll transfer finsh\n"); + } + else if (config->data_width <= 16) + { + const rt_uint16_t *send_ptr = message->send_buf; + rt_uint16_t *recv_ptr = message->recv_buf; + rt_uint32_t size = message->length; + + while (size--) + { + rt_uint16_t data = 0xFF; + + if (send_ptr != RT_NULL) + { + data = *send_ptr++; + } + + /* wait until the transmit buffer is empty */ + while (SPI_GetFlagStatus(spi_instance->config->spi_x, SPI_FLAG_TXE) == RESET); + /* send the byte */ + SPI_SendData(spi_instance->config->spi_x, data); + + /* wait until a data is received */ + while (SPI_GetFlagStatus(spi_instance->config->spi_x, SPI_INT_RXBNE) == RESET); + /* get the received data */ + data = SPI_ReceiveData(spi_instance->config->spi_x); + + if (recv_ptr != RT_NULL) + { + *recv_ptr++ = data; + } + } + } + + /* release cs */ + if (message->cs_release) + { + GPIO_SetOutBits(ht32_spi_cs->gpio_x, ht32_spi_cs->gpio_pin); + LOG_D("spi release cs\n"); + } + + return message->length; +} + +static struct rt_spi_ops ht32_spi_ops = +{ + .configure = ht32_configure, + .xfer = ht32_xfer +}; + +int rt_hw_spi_init(void) +{ + int i; + rt_err_t result; + rt_size_t obj_num = sizeof(spis) / sizeof(struct ht32_spi); + + for (i = 0; i < obj_num; i++) + { + spis[i].config = &spi_config[i]; + spis[i].spi_bus.parent.user_data = (void *)&spis[i]; + result = rt_spi_bus_register(&spis[i].spi_bus, spis[i].config->spi_name, &ht32_spi_ops); + } + return result; +} +INIT_BOARD_EXPORT(rt_hw_spi_init); + +#endif /* RT_USING_SPI */ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_spi.h b/bsp/ht32/libraries/ht32_drivers/drv_spi.h new file mode 100644 index 00000000000..65e63a5d3a1 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_spi.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include +#include +#include "drv_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* public function */ +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, HT_GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_SPI_H__ */ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_usart.c b/bsp/ht32/libraries/ht32_drivers/drv_usart.c new file mode 100644 index 00000000000..7e108e5f1ac --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_usart.c @@ -0,0 +1,372 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#include "drv_usart.h" + +#ifdef RT_USING_SERIAL +#if !defined(BSP_USING_USART0) && !defined(BSP_USING_USART1) && \ + !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && \ + !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) + #error "Please define at least one BSP_USING_UARTx" +#endif + +struct ht32_usart +{ + char *name; + HT_USART_TypeDef *usart_x; + IRQn_Type irq; + struct rt_serial_device serial; +}; + +enum +{ +#ifdef BSP_USING_USART0 + USART0_INDEX, +#endif +#ifdef BSP_USING_USART1 + USART1_INDEX, +#endif +#ifdef BSP_USING_UART0 + UART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif + +}; + +static struct ht32_usart usart_config[] = +{ +#ifdef BSP_USING_USART0 + { + "usart0", + HT_USART0, + USART0_IRQn, + RT_NULL + }, +#endif +#ifdef BSP_USING_USART1 + { + "usart1", + HT_USART1, + USART1_IRQn, + RT_NULL + }, +#endif +#ifdef BSP_USING_UART0 + { + "uart0", + HT_UART0, + UART0_IRQn, + RT_NULL + }, +#endif +#ifdef BSP_USING_UART1 + { + "uart1", + HT_UART1, + UART1_IRQn, + RT_NULL + }, +#endif +#ifdef BSP_USING_UART2 + { + "uart2", + HT_UART2, + UART0_UART2_IRQn, + RT_NULL + }, +#endif +#ifdef BSP_USING_UART3 + { + "uart3", + HT_UART3, + UART1_UART3_IRQn, + RT_NULL + }, +#endif +}; + +static rt_err_t ht32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + + CKCU_PeripClockConfig_TypeDef CKCUClock = {{0}}; + USART_InitTypeDef USART_InitStructure = {0}; + + struct ht32_usart *usart_instance = (struct ht32_usart *)serial->parent.user_data; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + CKCUClock.Bit.AFIO = 1; + + if ((usart_instance->usart_x) == HT_UART0) + CKCUClock.Bit.UART0 = 1; +#if defined(HT_USART0) + else if ((usart_instance->usart_x) == HT_USART0) + CKCUClock.Bit.USART0 = 1; +#endif +#if defined(HT_USART1) + else if ((usart_instance->usart_x) == HT_USART1) + CKCUClock.Bit.USART1 = 1; +#endif +#if defined(HT_UART1) + else if ((usart_instance->usart_x) == HT_UART1) + CKCUClock.Bit.UART1 = 1; +#endif +#if defined(HT_UART2) + else if ((usart_instance->usart_x) == HT_UART2) + CKCUClock.Bit.UART2 = 1; +#endif +#if defined(HT_UART3) + else if ((usart_instance->usart_x) == HT_UART3) + CKCUClock.Bit.UART3 = 1; +#endif + CKCU_PeripClockConfig(CKCUClock, ENABLE); + + /* UART gpio init */ + ht32_usart_gpio_init((void *)usart_instance->usart_x); + + /* baud rate */ + USART_InitStructure.USART_BaudRate = (cfg->baud_rate); + + /* data width */ + switch (cfg->data_bits) + { + case DATA_BITS_7: + USART_InitStructure.USART_WordLength = USART_WORDLENGTH_7B; + break; + case DATA_BITS_8: + USART_InitStructure.USART_WordLength = USART_WORDLENGTH_8B; + break; + case DATA_BITS_9: + USART_InitStructure.USART_WordLength = USART_WORDLENGTH_9B; + break; + default: + USART_InitStructure.USART_WordLength = USART_WORDLENGTH_8B; + break; + } + + /* stop bit */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + USART_InitStructure.USART_StopBits = USART_STOPBITS_1; + break; + case STOP_BITS_2: + USART_InitStructure.USART_StopBits = USART_STOPBITS_2; + break; + default: + USART_InitStructure.USART_StopBits = USART_STOPBITS_1; + break; + } + + switch (cfg->parity) + { + case PARITY_NONE: + USART_InitStructure.USART_Parity = USART_PARITY_NO; + break; + case PARITY_ODD: + USART_InitStructure.USART_Parity = USART_PARITY_ODD; + break; + case PARITY_EVEN: + USART_InitStructure.USART_Parity = USART_PARITY_EVEN; + break; + default: + USART_InitStructure.USART_Parity = USART_PARITY_NO; + break; + } + + /* UART mode */ + USART_InitStructure.USART_Mode = USART_MODE_NORMAL; + /* UART init */ + USART_Init((usart_instance->usart_x), &USART_InitStructure); + /*UART enable */ + USART_TxCmd((usart_instance->usart_x), ENABLE); + USART_RxCmd((usart_instance->usart_x), ENABLE); + + return RT_EOK; +} + +static rt_err_t ht32_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct ht32_usart *usart; + + RT_ASSERT(serial != RT_NULL); + usart = (struct ht32_usart *) serial->parent.user_data; + RT_ASSERT(usart != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + NVIC_DisableIRQ(usart->irq); + USART_IntConfig(usart->usart_x, USART_INT_RXDR, DISABLE); + break; + case RT_DEVICE_CTRL_SET_INT: + NVIC_EnableIRQ(usart->irq); + USART_IntConfig(usart->usart_x, USART_INT_RXDR, ENABLE); + break; + } + return RT_EOK; +} + +static int ht32_putc(struct rt_serial_device *serial, char c) +{ + struct ht32_usart *usart; + + RT_ASSERT(serial != RT_NULL); + usart = (struct ht32_usart *) serial->parent.user_data; + RT_ASSERT(usart != RT_NULL); + + while ((usart->usart_x->SR & USART_FLAG_TXC) == 0); + usart->usart_x->DR = (u8)c; + + return 1; +} + +static int ht32_getc(struct rt_serial_device *serial) +{ + int ch; + struct ht32_usart *usart; + + RT_ASSERT(serial != RT_NULL); + usart = (struct ht32_usart *) serial->parent.user_data; + RT_ASSERT(usart != RT_NULL); + + ch = -1; + if (USART_GetFlagStatus(usart->usart_x, USART_FLAG_RXDR) != RESET) + { + ch = USART_ReceiveData(usart->usart_x); + } + return ch; +} + +static rt_ssize_t ht32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ + return RT_ERROR; +} + +static const struct rt_uart_ops ht32_usart_ops = +{ + .configure = ht32_configure, + .control = ht32_control, + .putc = ht32_putc, + .getc = ht32_getc, + .dma_transmit = ht32_dma_transmit, +}; + +int rt_hw_usart_init(void) +{ + rt_size_t obj_num; + int index; + + obj_num = sizeof(usart_config) / sizeof(struct ht32_usart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t result = 0; + + for (index = 0; index < obj_num; index++) + { + usart_config[index].serial.ops = &ht32_usart_ops; + usart_config[index].serial.config = config; + + /* register uart device */ + result = rt_hw_serial_register(&usart_config[index].serial, + usart_config[index].name, + RT_DEVICE_FLAG_RDWR | + RT_DEVICE_FLAG_INT_RX | + RT_DEVICE_FLAG_INT_TX, + &usart_config[index]); + RT_ASSERT(result == RT_EOK); + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_usart_init); + +static void usart_isr(struct rt_serial_device *serial) +{ + + struct ht32_usart *usart = (struct ht32_usart *)serial->parent.user_data; + RT_ASSERT(usart != RT_NULL); + + if ((USART_GetFlagStatus(usart->usart_x, USART_FLAG_RXDR) != RESET) && ((usart->usart_x->IER & USART_INT_RXDR) != RESET)) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } +} + +#ifdef BSP_USING_USART0 +void USART0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + usart_isr(&usart_config[USART0_INDEX].serial); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_USART1 +void USART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + usart_isr(&usart_config[USART1_INDEX].serial); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_UART0 +void UART0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + usart_isr(&usart_config[UART0_INDEX].serial); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_UART1 +void UART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + usart_isr(&usart_config[UART1_INDEX].serial); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_UART2 +void UART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + usart_isr(&usart_config[UART2_INDEX].serial); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif +#ifdef BSP_USING_UART3 +void UART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + usart_isr(&usart_config[UART3_INDEX].serial); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#endif /* RT_USING_SERIAL */ diff --git a/bsp/ht32/libraries/ht32_drivers/drv_usart.h b/bsp/ht32/libraries/ht32_drivers/drv_usart.h new file mode 100644 index 00000000000..19fdaf68df4 --- /dev/null +++ b/bsp/ht32/libraries/ht32_drivers/drv_usart.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 QT-one first version + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +#include +#include +#include "drv_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_USART_H__ */ diff --git a/bsp/ht32/tools/sdk_dist.py b/bsp/ht32/tools/sdk_dist.py new file mode 100644 index 00000000000..2383b82a90f --- /dev/null +++ b/bsp/ht32/tools/sdk_dist.py @@ -0,0 +1,40 @@ +import os +import sys +import shutil +cwd_path = os.getcwd() +sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools')) + +def bsp_update_kconfig_library(dist_dir): + # change RTT_ROOT in Kconfig + if not os.path.isfile(os.path.join(dist_dir, 'Kconfig')): + return + + with open(os.path.join(dist_dir, 'Kconfig'), 'r') as f: + data = f.readlines() + with open(os.path.join(dist_dir, 'Kconfig'), 'w') as f: + found = 0 + for line in data: + if line.find('RTT_ROOT') != -1: + found = 1 + if line.find('../libraries') != -1 and found: + position = line.find('../libraries') + line = line[0:position] + 'libraries/Kconfig"\n' + found = 0 + f.write(line) + +# BSP dist function +def dist_do_building(BSP_ROOT, dist_dir): + from mkdist import bsp_copy_files + import rtconfig + + print("=> copy ht32 bsp library") + library_dir = os.path.join(dist_dir, 'libraries') + library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries') + bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), + os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE)) + + print("=> copy bsp drivers") + bsp_copy_files(os.path.join(library_path, 'ht32_drivers'), os.path.join(library_dir, 'ht32_drivers')) + shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) + bsp_update_kconfig_library(dist_dir) + diff --git a/bsp/k210/drivers/drv_gpio.c b/bsp/k210/drivers/drv_gpio.c index da8a507ed41..79c7bcc035e 100644 --- a/bsp/k210/drivers/drv_gpio.c +++ b/bsp/k210/drivers/drv_gpio.c @@ -111,13 +111,13 @@ static void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t va gpiohs_set_pin(pin_channel, value == PIN_HIGH ? GPIO_PV_HIGH : GPIO_PV_LOW); } -static rt_int8_t drv_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t drv_pin_read(struct rt_device *device, rt_base_t pin) { int pin_channel = get_pin_channel(pin); if(pin_channel == -1) { LOG_E("pin %d not set mode", pin); - return -1; + return -RT_EINVAL; } return gpiohs_get_pin(pin_channel) == GPIO_PV_HIGH ? PIN_HIGH : PIN_LOW; } @@ -248,7 +248,6 @@ const static struct rt_pin_ops drv_pin_ops = drv_pin_mode, drv_pin_write, drv_pin_read, - drv_pin_attach_irq, drv_pin_detach_irq, drv_pin_irq_enable diff --git a/bsp/lm3s8962/project.Uv2 b/bsp/lm3s8962/project.Uv2 index ac81e8bde65..38b934d0bcf 100644 --- a/bsp/lm3s8962/project.Uv2 +++ b/bsp/lm3s8962/project.Uv2 @@ -27,6 +27,7 @@ File 2,1,<..\..\components\libc\compilers\common\cunistd.c> File 2,1,<..\..\components\libc\compilers\common\cwchar.c> File 3,1,<..\..\components\drivers\core\device.c> File 3,1,<..\..\components\drivers\ipc\completion.c> +File 3,1,<..\..\components\drivers\ipc\condvar.c> File 3,1,<..\..\components\drivers\ipc\dataqueue.c> File 3,1,<..\..\components\drivers\ipc\pipe.c> File 3,1,<..\..\components\drivers\ipc\ringblk_buf.c> @@ -35,10 +36,10 @@ File 3,1,<..\..\components\drivers\ipc\waitqueue.c> File 3,1,<..\..\components\drivers\ipc\workqueue.c> File 3,1,<..\..\components\drivers\pin\pin.c> File 3,1,<..\..\components\drivers\serial\serial.c> -File 4,1, +File 4,1, File 4,1, File 4,1, -File 4,1, +File 4,1, File 5,1,<..\..\components\dfs\dfs_v1\filesystems\devfs\devfs.c> File 5,1,<..\..\components\dfs\dfs_v1\filesystems\elmfat\dfs_elm.c> File 5,1,<..\..\components\dfs\dfs_v1\filesystems\elmfat\ff.c> @@ -72,36 +73,36 @@ File 8,1,<..\..\libcpu\arm\common\div0.c> File 8,1,<..\..\libcpu\arm\common\showmem.c> File 8,2,<..\..\libcpu\arm\cortex-m3\context_rvds.S> File 8,1,<..\..\libcpu\arm\cortex-m3\cpuport.c> -File 9,1, -File 9,1, -File 9,1, -File 9,1, -File 9,1, +File 9,1, +File 9,1, File 9,1, -File 9,1, -File 9,1, -File 9,1, -File 9,1, +File 9,1, File 9,1, File 9,1, -File 9,1, -File 9,1, -File 9,1, +File 9,1, +File 9,1, +File 9,1, +File 9,1, File 9,1, -File 9,1, +File 9,1, +File 9,1, File 9,2, -File 9,1, -File 9,1, -File 9,1, +File 9,1, +File 9,1, +File 9,1, File 9,1, -File 9,1, -File 9,1, -File 9,1, +File 9,1, +File 9,1, +File 9,1, File 9,1, -File 9,1, -File 9,1, File 9,1, +File 9,1, +File 9,1, +File 9,1, +File 9,1, +File 9,1, File 9,1, +File 9,1, File 10,1,<..\..\components\net\lwip\lwip-1.4.1\src\api\api_lib.c> File 10,1,<..\..\components\net\lwip\lwip-1.4.1\src\api\api_msg.c> File 10,1,<..\..\components\net\lwip\lwip-1.4.1\src\api\err.c> diff --git a/bsp/lm3s9b9x/project.Uv2 b/bsp/lm3s9b9x/project.Uv2 index da6cced36fe..ae853366f41 100644 --- a/bsp/lm3s9b9x/project.Uv2 +++ b/bsp/lm3s9b9x/project.Uv2 @@ -27,6 +27,7 @@ File 2,1,<..\..\components\libc\compilers\common\cunistd.c> File 2,1,<..\..\components\libc\compilers\common\cwchar.c> File 3,1,<..\..\components\drivers\core\device.c> File 3,1,<..\..\components\drivers\ipc\completion.c> +File 3,1,<..\..\components\drivers\ipc\condvar.c> File 3,1,<..\..\components\drivers\ipc\dataqueue.c> File 3,1,<..\..\components\drivers\ipc\pipe.c> File 3,1,<..\..\components\drivers\ipc\ringblk_buf.c> @@ -35,11 +36,11 @@ File 3,1,<..\..\components\drivers\ipc\waitqueue.c> File 3,1,<..\..\components\drivers\ipc\workqueue.c> File 3,1,<..\..\components\drivers\pin\pin.c> File 3,1,<..\..\components\drivers\serial\serial.c> -File 4,1, -File 4,1, -File 4,1, File 4,1, File 4,1, +File 4,1, +File 4,1, +File 4,1, File 5,1,<..\..\components\dfs\dfs_v1\filesystems\devfs\devfs.c> File 5,1,<..\..\components\dfs\dfs_v1\filesystems\elmfat\dfs_elm.c> File 5,1,<..\..\components\dfs\dfs_v1\filesystems\elmfat\ff.c> @@ -73,36 +74,36 @@ File 8,1,<..\..\libcpu\arm\common\div0.c> File 8,1,<..\..\libcpu\arm\common\showmem.c> File 8,2,<..\..\libcpu\arm\cortex-m3\context_rvds.S> File 8,1,<..\..\libcpu\arm\cortex-m3\cpuport.c> -File 9,1, +File 9,1, +File 9,1, +File 9,1, +File 9,1, +File 9,1, +File 9,1, File 9,1, +File 9,1, +File 9,1, +File 9,1, +File 9,1, +File 9,1, File 9,1, +File 9,2, File 9,1, -File 9,1, -File 9,1, -File 9,1, +File 9,1, +File 9,1, +File 9,1, File 9,1, -File 9,1, -File 9,1, +File 9,1, +File 9,1, +File 9,1, File 9,1, -File 9,1, -File 9,1, +File 9,1, File 9,1, -File 9,1, +File 9,1, File 9,1, -File 9,1, -File 9,1, -File 9,1, -File 9,1, -File 9,1, -File 9,1, -File 9,1, -File 9,1, +File 9,1, File 9,1, -File 9,1, -File 9,2, -File 9,1, -File 9,1, -File 9,1, +File 9,1, File 10,1,<..\..\components\net\lwip\lwip-2.0.3\src\api\api_lib.c> File 10,1,<..\..\components\net\lwip\lwip-2.0.3\src\api\api_msg.c> File 10,1,<..\..\components\net\lwip\lwip-2.0.3\src\api\err.c> diff --git a/bsp/lm4f232/project.uvproj b/bsp/lm4f232/project.uvproj index 08e0114e51d..e50ca708fc9 100644 --- a/bsp/lm4f232/project.uvproj +++ b/bsp/lm4f232/project.uvproj @@ -384,16 +384,16 @@ Applications - startup.c + application.c 1 - applications\startup.c + applications\application.c - application.c + startup.c 1 - applications\application.c + applications\startup.c @@ -496,6 +496,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1027,9 +1046,16 @@ Libraries - comp.c + driverlib_timer.c 1 - Libraries\driverlib\comp.c + Libraries\driverlib\timer.c + + + + + uart.c + 1 + Libraries\driverlib\uart.c @@ -1041,23 +1067,23 @@ - fan.c + interrupt.c 1 - Libraries\driverlib\fan.c + Libraries\driverlib\interrupt.c - cpu.c + fpu.c 1 - Libraries\driverlib\cpu.c + Libraries\driverlib\fpu.c - sysctl.c + hibernate.c 1 - Libraries\driverlib\sysctl.c + Libraries\driverlib\hibernate.c @@ -1069,30 +1095,30 @@ - usb.c + fan.c 1 - Libraries\driverlib\usb.c + Libraries\driverlib\fan.c - peci.c + gpio.c 1 - Libraries\driverlib\peci.c + Libraries\driverlib\gpio.c - sysexc.c + sysctl.c 1 - Libraries\driverlib\sysexc.c + Libraries\driverlib\sysctl.c - mpu.c + comp.c 1 - Libraries\driverlib\mpu.c + Libraries\driverlib\comp.c @@ -1111,114 +1137,107 @@ - flash.c - 1 - Libraries\driverlib\flash.c - - - - - hibernate.c + ethernet.c 1 - Libraries\driverlib\hibernate.c + Libraries\driverlib\ethernet.c - eeprom.c + cpu.c 1 - Libraries\driverlib\eeprom.c + Libraries\driverlib\cpu.c - ethernet.c + i2s.c 1 - Libraries\driverlib\ethernet.c + Libraries\driverlib\i2s.c - uart.c + usb.c 1 - Libraries\driverlib\uart.c + Libraries\driverlib\usb.c - driverlib_timer.c + i2c.c 1 - Libraries\driverlib\timer.c + Libraries\driverlib\i2c.c - i2s.c + eeprom.c 1 - Libraries\driverlib\i2s.c + Libraries\driverlib\eeprom.c - adc.c + udma.c 1 - Libraries\driverlib\adc.c + Libraries\driverlib\udma.c - i2c.c + sysexc.c 1 - Libraries\driverlib\i2c.c + Libraries\driverlib\sysexc.c - systick.c + lpc.c 1 - Libraries\driverlib\systick.c + Libraries\driverlib\lpc.c - lpc.c + adc.c 1 - Libraries\driverlib\lpc.c + Libraries\driverlib\adc.c - watchdog.c + systick.c 1 - Libraries\driverlib\watchdog.c + Libraries\driverlib\systick.c - gpio.c + peci.c 1 - Libraries\driverlib\gpio.c + Libraries\driverlib\peci.c - qei.c + flash.c 1 - Libraries\driverlib\qei.c + Libraries\driverlib\flash.c - fpu.c + watchdog.c 1 - Libraries\driverlib\fpu.c + Libraries\driverlib\watchdog.c - udma.c + mpu.c 1 - Libraries\driverlib\udma.c + Libraries\driverlib\mpu.c @@ -1230,9 +1249,9 @@ - interrupt.c + qei.c 1 - Libraries\driverlib\interrupt.c + Libraries\driverlib\qei.c diff --git a/bsp/loongson/ls1cdev/drivers/drv_gpio.c b/bsp/loongson/ls1cdev/drivers/drv_gpio.c index ed6459441bb..fb75ab0d49e 100644 --- a/bsp/loongson/ls1cdev/drivers/drv_gpio.c +++ b/bsp/loongson/ls1cdev/drivers/drv_gpio.c @@ -51,10 +51,10 @@ void ls1c_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value) } -rt_int8_t ls1c_pin_read(struct rt_device *device, rt_base_t pin) +rt_ssize_t ls1c_pin_read(struct rt_device *device, rt_base_t pin) { unsigned int gpio = pin; - rt_int8_t value = PIN_LOW; + rt_ssize_t value = PIN_LOW; if (0 == gpio_get(gpio)) { @@ -119,7 +119,6 @@ const static struct rt_pin_ops _ls1c_pin_ops = ls1c_pin_mode, ls1c_pin_write, ls1c_pin_read, - ls1c_pin_attach_irq, ls1c_pin_detach_irq, ls1c_pin_irq_enable, diff --git a/bsp/loongson/ls2kdev/drivers/drv_gpio.c b/bsp/loongson/ls2kdev/drivers/drv_gpio.c index 5c3d913de1b..2a66825ef66 100644 --- a/bsp/loongson/ls2kdev/drivers/drv_gpio.c +++ b/bsp/loongson/ls2kdev/drivers/drv_gpio.c @@ -67,10 +67,10 @@ static void loongson_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8 else gpio->GPIO0_O &= ~m; } -static rt_int8_t loongson_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t loongson_pin_read(struct rt_device *device, rt_base_t pin) { struct loongson_gpio *gpio; - rt_int8_t rc; + rt_ssize_t rc; gpio = (void *)device->user_data; rt_uint64_t m; diff --git a/bsp/maxim/libraries/HAL_Drivers/drv_gpio.c b/bsp/maxim/libraries/HAL_Drivers/drv_gpio.c index 03d177f1fd5..b83221a999b 100644 --- a/bsp/maxim/libraries/HAL_Drivers/drv_gpio.c +++ b/bsp/maxim/libraries/HAL_Drivers/drv_gpio.c @@ -46,9 +46,9 @@ static void mcu_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } -static rt_int8_t mcu_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t mcu_pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value; + rt_ssize_t value; gpio_cfg_t tmp_gpio_cfg; tmp_gpio_cfg.port = PIN_PORT(pin); tmp_gpio_cfg.mask = PIN_MCU_PIN(pin); diff --git a/bsp/maxim/max32660-evsys/project.uvprojx b/bsp/maxim/max32660-evsys/project.uvprojx index f321223da89..a6deadf9c91 100644 --- a/bsp/maxim/max32660-evsys/project.uvprojx +++ b/bsp/maxim/max32660-evsys/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/mini2440/project.uvproj b/bsp/mini2440/project.uvproj index f175493867a..3ceb6004267 100644 --- a/bsp/mini2440/project.uvproj +++ b/bsp/mini2440/project.uvproj @@ -496,6 +496,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/mipssim/drivers/drv_uart.h b/bsp/mipssim/drivers/drv_uart.h index 0501337a396..64d51c06625 100644 --- a/bsp/mipssim/drivers/drv_uart.h +++ b/bsp/mipssim/drivers/drv_uart.h @@ -15,100 +15,100 @@ #include /* UART registers */ -#define UART_DAT(base) HWREG8(base + 0x00) -#define UART_IER(base) HWREG8(base + 0x01) -#define UART_IIR(base) HWREG8(base + 0x02) -#define UART_FCR(base) HWREG8(base + 0x02) -#define UART_LCR(base) HWREG8(base + 0x03) -#define UART_MCR(base) HWREG8(base + 0x04) -#define UART_LSR(base) HWREG8(base + 0x05) -#define UART_MSR(base) HWREG8(base + 0x06) +#define UART_DAT(base) HWREG8(base + 0x00) +#define UART_IER(base) HWREG8(base + 0x01) +#define UART_IIR(base) HWREG8(base + 0x02) +#define UART_FCR(base) HWREG8(base + 0x02) +#define UART_LCR(base) HWREG8(base + 0x03) +#define UART_MCR(base) HWREG8(base + 0x04) +#define UART_LSR(base) HWREG8(base + 0x05) +#define UART_MSR(base) HWREG8(base + 0x06) -#define UART_LSB(base) HWREG8(base + 0x00) -#define UART_MSB(base) HWREG8(base + 0x01) +#define UART_LSB(base) HWREG8(base + 0x00) +#define UART_MSB(base) HWREG8(base + 0x01) /* interrupt enable register */ -#define IER_IRxE 0x1 /* 接收有效数据中断使能 */ -#define IER_ITxE 0x2 /* 传输保存寄存器为空中断使能 */ -#define IER_ILE 0x4 /* 接收器线路状态中断使能 */ -#define IER_IME 0x8 /* Modem状态中断使能 */ +#define IER_IRxE 0x1 /* 接收有效数据中断使能 */ +#define IER_ITxE 0x2 /* 传输保存寄存器为空中断使能 */ +#define IER_ILE 0x4 /* 接收器线路状态中断使能 */ +#define IER_IME 0x8 /* Modem状态中断使能 */ /* interrupt identification register */ -#define IIR_IMASK 0xf /* mask */ -#define IIR_RXTOUT 0xc /* receive timeout */ -#define IIR_RLS 0x6 /* receive line status */ -#define IIR_RXRDY 0x4 /* receive ready */ -#define IIR_TXRDY 0x2 /* transmit ready */ -#define IIR_NOPEND 0x1 /* nothing */ -#define IIR_MLSC 0x0 /* modem status */ -#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ +#define IIR_IMASK 0xf /* mask */ +#define IIR_RXTOUT 0xc /* receive timeout */ +#define IIR_RLS 0x6 /* receive line status */ +#define IIR_RXRDY 0x4 /* receive ready */ +#define IIR_TXRDY 0x2 /* transmit ready */ +#define IIR_NOPEND 0x1 /* nothing */ +#define IIR_MLSC 0x0 /* modem status */ +#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ /* fifo control register */ -#define FIFO_ENABLE 0x01 /* enable fifo */ -#define FIFO_RCV_RST 0x02 /* reset receive fifo */ -#define FIFO_XMT_RST 0x04 /* reset transmit fifo */ -#define FIFO_DMA_MODE 0x08 /* enable dma mode */ -#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */ -#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */ -#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */ -#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */ +#define FIFO_ENABLE 0x01 /* enable fifo */ +#define FIFO_RCV_RST 0x02 /* reset receive fifo */ +#define FIFO_XMT_RST 0x04 /* reset transmit fifo */ +#define FIFO_DMA_MODE 0x08 /* enable dma mode */ +#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */ +#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */ +#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */ +#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */ // 线路控制寄存器 /* character format control register */ -#define CFCR_DLAB 0x80 /* divisor latch */ -#define CFCR_SBREAK 0x40 /* send break */ -#define CFCR_PZERO 0x30 /* zero parity */ -#define CFCR_PONE 0x20 /* one parity */ -#define CFCR_PEVEN 0x10 /* even parity */ -#define CFCR_PODD 0x00 /* odd parity */ -#define CFCR_PENAB 0x08 /* parity enable */ -#define CFCR_STOPB 0x04 /* 2 stop bits */ -#define CFCR_8BITS 0x03 /* 8 data bits */ -#define CFCR_7BITS 0x02 /* 7 data bits */ -#define CFCR_6BITS 0x01 /* 6 data bits */ -#define CFCR_5BITS 0x00 /* 5 data bits */ +#define CFCR_DLAB 0x80 /* divisor latch */ +#define CFCR_SBREAK 0x40 /* send break */ +#define CFCR_PZERO 0x30 /* zero parity */ +#define CFCR_PONE 0x20 /* one parity */ +#define CFCR_PEVEN 0x10 /* even parity */ +#define CFCR_PODD 0x00 /* odd parity */ +#define CFCR_PENAB 0x08 /* parity enable */ +#define CFCR_STOPB 0x04 /* 2 stop bits */ +#define CFCR_8BITS 0x03 /* 8 data bits */ +#define CFCR_7BITS 0x02 /* 7 data bits */ +#define CFCR_6BITS 0x01 /* 6 data bits */ +#define CFCR_5BITS 0x00 /* 5 data bits */ /* modem control register */ -#define MCR_LOOPBACK 0x10 /* loopback */ -#define MCR_IENABLE 0x08 /* output 2 = int enable */ -#define MCR_DRS 0x04 /* output 1 = xxx */ -#define MCR_RTS 0x02 /* enable RTS */ -#define MCR_DTR 0x01 /* enable DTR */ +#define MCR_LOOPBACK 0x10 /* loopback */ +#define MCR_IENABLE 0x08 /* output 2 = int enable */ +#define MCR_DRS 0x04 /* output 1 = xxx */ +#define MCR_RTS 0x02 /* enable RTS */ +#define MCR_DTR 0x01 /* enable DTR */ /* line status register */ -#define LSR_RCV_FIFO 0x80 /* error in receive fifo */ -#define LSR_TSRE 0x40 /* transmitter empty */ -#define LSR_TXRDY 0x20 /* transmitter ready */ -#define LSR_BI 0x10 /* break detected */ -#define LSR_FE 0x08 /* framing error */ -#define LSR_PE 0x04 /* parity error */ -#define LSR_OE 0x02 /* overrun error */ -#define LSR_RXRDY 0x01 /* receiver ready */ -#define LSR_RCV_MASK 0x1f +#define LSR_RCV_FIFO 0x80 /* error in receive fifo */ +#define LSR_TSRE 0x40 /* transmitter empty */ +#define LSR_TXRDY 0x20 /* transmitter ready */ +#define LSR_BI 0x10 /* break detected */ +#define LSR_FE 0x08 /* framing error */ +#define LSR_PE 0x04 /* parity error */ +#define LSR_OE 0x02 /* overrun error */ +#define LSR_RXRDY 0x01 /* receiver ready */ +#define LSR_RCV_MASK 0x1f /* UART interrupt enable register value */ -#define UARTIER_IME (1 << 3) -#define UARTIER_ILE (1 << 2) -#define UARTIER_ITXE (1 << 1) -#define UARTIER_IRXE (1 << 0) +#define UARTIER_IME (1 << 3) +#define UARTIER_ILE (1 << 2) +#define UARTIER_ITXE (1 << 1) +#define UARTIER_IRXE (1 << 0) /* UART line control register value */ -#define UARTLCR_DLAB (1 << 7) -#define UARTLCR_BCB (1 << 6) -#define UARTLCR_SPB (1 << 5) -#define UARTLCR_EPS (1 << 4) -#define UARTLCR_PE (1 << 3) -#define UARTLCR_SB (1 << 2) +#define UARTLCR_DLAB (1 << 7) +#define UARTLCR_BCB (1 << 6) +#define UARTLCR_SPB (1 << 5) +#define UARTLCR_EPS (1 << 4) +#define UARTLCR_PE (1 << 3) +#define UARTLCR_SB (1 << 2) /* UART line status register value */ -#define UARTLSR_ERROR (1 << 7) -#define UARTLSR_TE (1 << 6) -#define UARTLSR_TFE (1 << 5) -#define UARTLSR_BI (1 << 4) -#define UARTLSR_FE (1 << 3) -#define UARTLSR_PE (1 << 2) -#define UARTLSR_OE (1 << 1) -#define UARTLSR_DR (1 << 0) +#define UARTLSR_ERROR (1 << 7) +#define UARTLSR_TE (1 << 6) +#define UARTLSR_TFE (1 << 5) +#define UARTLSR_BI (1 << 4) +#define UARTLSR_FE (1 << 3) +#define UARTLSR_PE (1 << 2) +#define UARTLSR_OE (1 << 1) +#define UARTLSR_DR (1 << 0) -#endif \ No newline at end of file +#endif diff --git a/bsp/mm32/libraries/HAL_Drivers/drv_gpio.c b/bsp/mm32/libraries/HAL_Drivers/drv_gpio.c index 882212a4edd..311a51f6e08 100644 --- a/bsp/mm32/libraries/HAL_Drivers/drv_gpio.c +++ b/bsp/mm32/libraries/HAL_Drivers/drv_gpio.c @@ -134,11 +134,11 @@ static void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t mm32_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t mm32_pin_read(rt_device_t dev, rt_base_t pin) { GPIO_Type *gpio_port; uint16_t gpio_pin; - rt_int8_t value = PIN_LOW; + rt_ssize_t value = PIN_LOW; if (PIN_PORT(pin) < PIN_STPORT_MAX) { @@ -146,6 +146,10 @@ static rt_int8_t mm32_pin_read(rt_device_t dev, rt_base_t pin) gpio_pin = PIN_STPIN(pin); value = GPIO_ReadInDataBit(gpio_port, gpio_pin); } + else + { + return -RT_EINVAL; + } return value; } diff --git a/bsp/mm32/mm32f3270-100ask-pitaya/project.ewp b/bsp/mm32/mm32f3270-100ask-pitaya/project.ewp index 8715e9f6048..b506258b4d1 100644 --- a/bsp/mm32/mm32f3270-100ask-pitaya/project.ewp +++ b/bsp/mm32/mm32f3270-100ask-pitaya/project.ewp @@ -225,7 +225,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT MM32F3277G __RTTHREAD__ USE_HAL_DRIVER @@ -1294,7 +1293,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT MM32F3277G __RTTHREAD__ USE_HAL_DRIVER @@ -2200,6 +2198,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/mm32/mm32f3270-100ask-pitaya/project.uvprojx b/bsp/mm32/mm32f3270-100ask-pitaya/project.uvprojx index f3ab11dda61..6acb0756ef6 100644 --- a/bsp/mm32/mm32f3270-100ask-pitaya/project.uvprojx +++ b/bsp/mm32/mm32f3270-100ask-pitaya/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/mm32f103x/drivers/drv_gpio.c b/bsp/mm32f103x/drivers/drv_gpio.c index d823d556aa8..7db8bd95a95 100644 --- a/bsp/mm32f103x/drivers/drv_gpio.c +++ b/bsp/mm32f103x/drivers/drv_gpio.c @@ -175,16 +175,16 @@ void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -rt_int8_t mm32_pin_read(rt_device_t dev, rt_base_t pin) +rt_ssize_t mm32_pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value; + rt_ssize_t value; const struct pin_index *index; value = PIN_LOW; index = get_pin(pin); if (index == RT_NULL) { - return PIN_LOW; + return -RT_EINVAL; } if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) { diff --git a/bsp/mm32f103x/project.ewp b/bsp/mm32f103x/project.ewp index 07a4be8817d..f1077b7504d 100644 --- a/bsp/mm32f103x/project.ewp +++ b/bsp/mm32f103x/project.ewp @@ -2215,6 +2215,9 @@ $PROJ_DIR$\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c @@ -2336,25 +2339,28 @@ Libraries - $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_crc.c + $PROJ_DIR$\Libraries\MM32F103\Source\system_MM32F103.c - $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_misc.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_wwdg.c + + + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_gpio.c $PROJ_DIR$\Libraries\MM32F103\Source\IAR_StartAsm\startup_MM32F103.s - $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_dma.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_crc.c - $PROJ_DIR$\Libraries\MM32F103\Source\system_MM32F103.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_pwr.c - $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_rtc.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_iwdg.c - $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_bkp.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_i2c.c $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_spi.c @@ -2363,37 +2369,34 @@ $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_exti.c - $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_adc.c - - - $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_wwdg.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_misc.c - $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_uart.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_rcc.c - $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_gpio.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_adc.c - $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_pwr.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_dma.c $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_flash.c - $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_iwdg.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_can.c - $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_tim.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_rtc.c - $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_can.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_uart.c - $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_rcc.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_bkp.c - $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_i2c.c + $PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_tim.c diff --git a/bsp/mm32f103x/project.uvprojx b/bsp/mm32f103x/project.uvprojx index 4391d85b2f2..511232099e4 100644 --- a/bsp/mm32f103x/project.uvprojx +++ b/bsp/mm32f103x/project.uvprojx @@ -476,6 +476,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1026,9 +1045,9 @@ Libraries - HAL_flash.c + HAL_gpio.c 1 - Libraries\MM32F103\HAL_lib\src\HAL_flash.c + Libraries\MM32F103\HAL_lib\src\HAL_gpio.c @@ -1040,9 +1059,9 @@ - HAL_bkp.c + HAL_crc.c 1 - Libraries\MM32F103\HAL_lib\src\HAL_bkp.c + Libraries\MM32F103\HAL_lib\src\HAL_crc.c @@ -1054,9 +1073,9 @@ - HAL_can.c - 1 - Libraries\MM32F103\HAL_lib\src\HAL_can.c + startup_MM32F103.s + 2 + Libraries\MM32F103\Source\KEIL_StartAsm\startup_MM32F103.s @@ -1075,23 +1094,23 @@ - HAL_misc.c + HAL_bkp.c 1 - Libraries\MM32F103\HAL_lib\src\HAL_misc.c + Libraries\MM32F103\HAL_lib\src\HAL_bkp.c - HAL_rtc.c + HAL_uart.c 1 - Libraries\MM32F103\HAL_lib\src\HAL_rtc.c + Libraries\MM32F103\HAL_lib\src\HAL_uart.c - startup_MM32F103.s - 2 - Libraries\MM32F103\Source\KEIL_StartAsm\startup_MM32F103.s + HAL_flash.c + 1 + Libraries\MM32F103\HAL_lib\src\HAL_flash.c @@ -1103,23 +1122,23 @@ - HAL_pwr.c + HAL_rtc.c 1 - Libraries\MM32F103\HAL_lib\src\HAL_pwr.c + Libraries\MM32F103\HAL_lib\src\HAL_rtc.c - HAL_gpio.c + HAL_pwr.c 1 - Libraries\MM32F103\HAL_lib\src\HAL_gpio.c + Libraries\MM32F103\HAL_lib\src\HAL_pwr.c - HAL_spi.c + HAL_misc.c 1 - Libraries\MM32F103\HAL_lib\src\HAL_spi.c + Libraries\MM32F103\HAL_lib\src\HAL_misc.c @@ -1131,37 +1150,37 @@ - HAL_crc.c + HAL_rcc.c 1 - Libraries\MM32F103\HAL_lib\src\HAL_crc.c + Libraries\MM32F103\HAL_lib\src\HAL_rcc.c - HAL_tim.c + HAL_spi.c 1 - Libraries\MM32F103\HAL_lib\src\HAL_tim.c + Libraries\MM32F103\HAL_lib\src\HAL_spi.c - HAL_uart.c + HAL_can.c 1 - Libraries\MM32F103\HAL_lib\src\HAL_uart.c + Libraries\MM32F103\HAL_lib\src\HAL_can.c - HAL_rcc.c + HAL_iwdg.c 1 - Libraries\MM32F103\HAL_lib\src\HAL_rcc.c + Libraries\MM32F103\HAL_lib\src\HAL_iwdg.c - HAL_iwdg.c + HAL_tim.c 1 - Libraries\MM32F103\HAL_lib\src\HAL_iwdg.c + Libraries\MM32F103\HAL_lib\src\HAL_tim.c diff --git a/bsp/mm32f327x/drivers/drv_gpio.c b/bsp/mm32f327x/drivers/drv_gpio.c index f24602ec2d0..a3374960cbb 100644 --- a/bsp/mm32f327x/drivers/drv_gpio.c +++ b/bsp/mm32f327x/drivers/drv_gpio.c @@ -171,16 +171,16 @@ void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -rt_int8_t mm32_pin_read(rt_device_t dev, rt_base_t pin) +rt_ssize_t mm32_pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value; + rt_ssize_t value; const struct pin_index *index; value = PIN_LOW; index = get_pin(pin); if (index == RT_NULL) { - return PIN_LOW; + return -RT_EINVAL; } if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) { diff --git a/bsp/mm32f327x/project.ewp b/bsp/mm32f327x/project.ewp index 7c31e78dccf..847f7863b87 100644 --- a/bsp/mm32f327x/project.ewp +++ b/bsp/mm32f327x/project.ewp @@ -2200,6 +2200,9 @@ $PROJ_DIR$\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c @@ -2321,91 +2324,91 @@ Libraries - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_gpio.c - - - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_pwr.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_uart.c $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_crc.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_bkp.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_gpio.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_iwdg.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_dac.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_rcc.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_fsmc.c $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_i2c.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_spi.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_flash.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_crs.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_spi.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_exti.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_tim.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_dma.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_pwr.c $PROJ_DIR$\Libraries\MM32F327x\Source\system_mm32f327x.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_sdio.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_comp.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_ver.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_eth.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_dbg.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_bkp.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_tim.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_misc.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_can.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_sdio.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_misc.c + $PROJ_DIR$\Libraries\MM32F327x\Source\IAR_StartAsm\startup_mm32f327x_iar.s - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_dac.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_exti.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_eth.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_wwdg.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_comp.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_dbg.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_uid.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_iwdg.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_uart.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_rcc.c - $PROJ_DIR$\Libraries\MM32F327x\Source\IAR_StartAsm\startup_mm32f327x_iar.s + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_ver.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_flash.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_can.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_rtc.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_dma.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_fsmc.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_uid.c $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_adc.c - $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_wwdg.c + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_crs.c + + + $PROJ_DIR$\Libraries\MM32F327x\HAL_Lib\Src\hal_rtc.c diff --git a/bsp/mm32f327x/project.uvprojx b/bsp/mm32f327x/project.uvprojx index b9418d48dea..fc541064747 100644 --- a/bsp/mm32f327x/project.uvprojx +++ b/bsp/mm32f327x/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1036,205 +1055,205 @@ Libraries - hal_flash.c + hal_crc.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_flash.c + Libraries\MM32F327x\HAL_Lib\Src\hal_crc.c - hal_wwdg.c + hal_flash.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_wwdg.c + Libraries\MM32F327x\HAL_Lib\Src\hal_flash.c - hal_uart.c + hal_sdio.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_uart.c + Libraries\MM32F327x\HAL_Lib\Src\hal_sdio.c - hal_crs.c + hal_bkp.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_crs.c + Libraries\MM32F327x\HAL_Lib\Src\hal_bkp.c - hal_exti.c + hal_fsmc.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_exti.c + Libraries\MM32F327x\HAL_Lib\Src\hal_fsmc.c - hal_sdio.c + hal_dbg.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_sdio.c + Libraries\MM32F327x\HAL_Lib\Src\hal_dbg.c - hal_crc.c + hal_eth.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_crc.c + Libraries\MM32F327x\HAL_Lib\Src\hal_eth.c - hal_dbg.c + hal_uid.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_dbg.c + Libraries\MM32F327x\HAL_Lib\Src\hal_uid.c - hal_i2c.c + hal_comp.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_i2c.c + Libraries\MM32F327x\HAL_Lib\Src\hal_comp.c - system_mm32f327x.c + hal_misc.c 1 - Libraries\MM32F327x\Source\system_mm32f327x.c + Libraries\MM32F327x\HAL_Lib\Src\hal_misc.c - hal_misc.c + hal_uart.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_misc.c + Libraries\MM32F327x\HAL_Lib\Src\hal_uart.c - hal_eth.c + hal_tim.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_eth.c + Libraries\MM32F327x\HAL_Lib\Src\hal_tim.c - hal_rtc.c + system_mm32f327x.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_rtc.c + Libraries\MM32F327x\Source\system_mm32f327x.c - startup_mm32f327x_keil.s - 2 - Libraries\MM32F327x\Source\KEIL_StartAsm\startup_mm32f327x_keil.s + hal_exti.c + 1 + Libraries\MM32F327x\HAL_Lib\Src\hal_exti.c - hal_adc.c + hal_spi.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_adc.c + Libraries\MM32F327x\HAL_Lib\Src\hal_spi.c - hal_fsmc.c + hal_iwdg.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_fsmc.c + Libraries\MM32F327x\HAL_Lib\Src\hal_iwdg.c - hal_rcc.c - 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_rcc.c + startup_mm32f327x_keil.s + 2 + Libraries\MM32F327x\Source\KEIL_StartAsm\startup_mm32f327x_keil.s - hal_tim.c + hal_i2c.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_tim.c + Libraries\MM32F327x\HAL_Lib\Src\hal_i2c.c - hal_can.c + hal_ver.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_can.c + Libraries\MM32F327x\HAL_Lib\Src\hal_ver.c - hal_dma.c + hal_crs.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_dma.c + Libraries\MM32F327x\HAL_Lib\Src\hal_crs.c - hal_uid.c + hal_dma.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_uid.c + Libraries\MM32F327x\HAL_Lib\Src\hal_dma.c - hal_dac.c + hal_can.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_dac.c + Libraries\MM32F327x\HAL_Lib\Src\hal_can.c - hal_bkp.c + hal_gpio.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_bkp.c + Libraries\MM32F327x\HAL_Lib\Src\hal_gpio.c - hal_iwdg.c + hal_dac.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_iwdg.c + Libraries\MM32F327x\HAL_Lib\Src\hal_dac.c - hal_spi.c + hal_rtc.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_spi.c + Libraries\MM32F327x\HAL_Lib\Src\hal_rtc.c - hal_comp.c + hal_wwdg.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_comp.c + Libraries\MM32F327x\HAL_Lib\Src\hal_wwdg.c - hal_pwr.c + hal_adc.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_pwr.c + Libraries\MM32F327x\HAL_Lib\Src\hal_adc.c - hal_ver.c + hal_rcc.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_ver.c + Libraries\MM32F327x\HAL_Lib\Src\hal_rcc.c - hal_gpio.c + hal_pwr.c 1 - Libraries\MM32F327x\HAL_Lib\Src\hal_gpio.c + Libraries\MM32F327x\HAL_Lib\Src\hal_pwr.c diff --git a/bsp/mm32l07x/drivers/drv_uart.c b/bsp/mm32l07x/drivers/drv_uart.c index f7e54d1eda1..82007ed29b7 100644 --- a/bsp/mm32l07x/drivers/drv_uart.c +++ b/bsp/mm32l07x/drivers/drv_uart.c @@ -35,8 +35,8 @@ struct mm32_uart IRQn_Type irq; }; -static rt_err_t mm32_uart_configure(struct rt_serial_device *serial, - struct serial_configure *cfg) +static rt_err_t mm32_uart_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) { struct mm32_uart *uart; UART_InitTypeDef UART_InitStructure; @@ -59,8 +59,8 @@ static rt_err_t mm32_uart_configure(struct rt_serial_device *serial, return RT_EOK; } -static rt_err_t mm32_uart_control(struct rt_serial_device *serial, - int cmd, void *arg) +static rt_err_t mm32_uart_control(struct rt_serial_device *serial, + int cmd, void *arg) { struct mm32_uart *uart; RT_ASSERT(serial != RT_NULL); @@ -70,12 +70,12 @@ static rt_err_t mm32_uart_control(struct rt_serial_device *serial, case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ NVIC_DisableIRQ(uart->irq); - UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE); + UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ NVIC_EnableIRQ(uart->irq); - /* enable interrupt */ + /* enable interrupt */ UART_ITConfig(uart->uart, UART_IT_RXIEN, ENABLE); break; } @@ -88,7 +88,7 @@ static int mm32_uart_putc(struct rt_serial_device *serial, char c) RT_ASSERT(serial != RT_NULL); uart = (struct mm32_uart *)serial->parent.user_data; while ((uart->uart->CSR & UART_CSR_TXC) == 0); - uart->uart->TDR = c; + uart->uart->TDR = c; return 1; } @@ -167,8 +167,8 @@ void UART2_IRQHandler(void) static void UART1PINconfigStepA(void) { /* Enable UART clock */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_UART1, ENABLE); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_UART1, ENABLE); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_1); GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_1); } @@ -178,7 +178,7 @@ static void UART1PINconfigStepB(void) /* Configure USART Rx/tx PIN */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_Init(GPIOA, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; @@ -189,8 +189,8 @@ static void UART1PINconfigStepB(void) static void UART2PINconfigStepA(void) { /* Enable UART clock */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART2, ENABLE); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART2, ENABLE); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_1); GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_1); } @@ -198,9 +198,9 @@ static void UART2PINconfigStepB(void) { GPIO_InitTypeDef GPIO_InitStructure; /* Configure USART Rx/tx PIN */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_Init(GPIOA, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; @@ -215,8 +215,8 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART1 UART1PINconfigStepA(); uart = &uart1; - uart->uart = UART1; - uart->irq = UART1_IRQn; + uart->uart = UART1; + uart->irq = UART1_IRQn; config.baud_rate = BAUD_RATE_115200; serial1.ops = &mm32_uart_ops; serial1.config = config; @@ -229,8 +229,8 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART2 UART2PINconfigStepA(); uart = &uart2; - uart->uart = UART2; - uart->irq = UART2_IRQn; + uart->uart = UART2; + uart->irq = UART2_IRQn; config.baud_rate = BAUD_RATE_115200; serial2.ops = &mm32_uart_ops; serial2.config = config; diff --git a/bsp/mm32l07x/project.ewp b/bsp/mm32l07x/project.ewp index b605810e218..c75a166f891 100644 --- a/bsp/mm32l07x/project.ewp +++ b/bsp/mm32l07x/project.ewp @@ -2152,6 +2152,9 @@ $PROJ_DIR$\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c @@ -2273,58 +2276,58 @@ $PROJ_DIR$\Libraries\MM32L0xx\Source\system_MM32L0xx.c - $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_dma.c + $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_wwdg.c - $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_i2c.c + $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_pwr.c $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_flash.c - $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_rcc.c + $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_uart.c - $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_uart.c + $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_can.c - $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_misc.c + $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_dma.c - $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_gpio.c + $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_exti.c - $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_wwdg.c + $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_misc.c - $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_adc.c + $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_i2c.c $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_comp.c - $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_iwdg.c + $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_gpio.c - $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_syscfg.c + $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_adc.c - $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_spi.c + $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_iwdg.c - $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_exti.c + $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_rcc.c - $PROJ_DIR$\Libraries\MM32L0xx\Source\IAR_StartAsm\startup_MM32L0xx.s + $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_spi.c - $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_pwr.c + $PROJ_DIR$\Libraries\MM32L0xx\Source\IAR_StartAsm\startup_MM32L0xx.s $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_bkp.c - $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_can.c + $PROJ_DIR$\Libraries\MM32L0xx\HAL_lib\src\HAL_syscfg.c diff --git a/bsp/mm32l07x/project.uvprojx b/bsp/mm32l07x/project.uvprojx index 7760e62dc9b..b7519c3530e 100644 --- a/bsp/mm32l07x/project.uvprojx +++ b/bsp/mm32l07x/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1008,142 +1027,142 @@ Libraries - system_MM32L0xx.c + HAL_spi.c 1 - Libraries\MM32L0xx\Source\system_MM32L0xx.c + Libraries\MM32L0xx\HAL_lib\src\HAL_spi.c - HAL_adc.c + system_MM32L0xx.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_adc.c + Libraries\MM32L0xx\Source\system_MM32L0xx.c - HAL_gpio.c + HAL_iwdg.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_gpio.c + Libraries\MM32L0xx\HAL_lib\src\HAL_iwdg.c - HAL_spi.c + HAL_flash.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_spi.c + Libraries\MM32L0xx\HAL_lib\src\HAL_flash.c - HAL_i2c.c - 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_i2c.c + startup_MM32L0xx.s + 2 + Libraries\MM32L0xx\Source\KEIL_StartAsm\startup_MM32L0xx.s - HAL_iwdg.c + HAL_rcc.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_iwdg.c + Libraries\MM32L0xx\HAL_lib\src\HAL_rcc.c - HAL_uart.c + HAL_bkp.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_uart.c + Libraries\MM32L0xx\HAL_lib\src\HAL_bkp.c - HAL_comp.c + HAL_exti.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_comp.c + Libraries\MM32L0xx\HAL_lib\src\HAL_exti.c - HAL_exti.c + HAL_syscfg.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_exti.c + Libraries\MM32L0xx\HAL_lib\src\HAL_syscfg.c - startup_MM32L0xx.s - 2 - Libraries\MM32L0xx\Source\KEIL_StartAsm\startup_MM32L0xx.s + HAL_wwdg.c + 1 + Libraries\MM32L0xx\HAL_lib\src\HAL_wwdg.c - HAL_tim.c + HAL_dma.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_tim.c + Libraries\MM32L0xx\HAL_lib\src\HAL_dma.c - HAL_misc.c + HAL_uart.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_misc.c + Libraries\MM32L0xx\HAL_lib\src\HAL_uart.c - HAL_wwdg.c + HAL_can.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_wwdg.c + Libraries\MM32L0xx\HAL_lib\src\HAL_can.c - HAL_bkp.c + HAL_adc.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_bkp.c + Libraries\MM32L0xx\HAL_lib\src\HAL_adc.c - HAL_flash.c + HAL_gpio.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_flash.c + Libraries\MM32L0xx\HAL_lib\src\HAL_gpio.c - HAL_dma.c + HAL_tim.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_dma.c + Libraries\MM32L0xx\HAL_lib\src\HAL_tim.c - HAL_pwr.c + HAL_misc.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_pwr.c + Libraries\MM32L0xx\HAL_lib\src\HAL_misc.c - HAL_rcc.c + HAL_comp.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_rcc.c + Libraries\MM32L0xx\HAL_lib\src\HAL_comp.c - HAL_syscfg.c + HAL_i2c.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_syscfg.c + Libraries\MM32L0xx\HAL_lib\src\HAL_i2c.c - HAL_can.c + HAL_pwr.c 1 - Libraries\MM32L0xx\HAL_lib\src\HAL_can.c + Libraries\MM32L0xx\HAL_lib\src\HAL_pwr.c diff --git a/bsp/mm32l3xx/drivers/drv_gpio.c b/bsp/mm32l3xx/drivers/drv_gpio.c index b621dccbb82..57256dced60 100644 --- a/bsp/mm32l3xx/drivers/drv_gpio.c +++ b/bsp/mm32l3xx/drivers/drv_gpio.c @@ -160,16 +160,16 @@ void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -rt_int8_t mm32_pin_read(rt_device_t dev, rt_base_t pin) +rt_ssize_t mm32_pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value; + rt_ssize_t value; const struct pin_index *index; value = PIN_LOW; index = get_pin(pin); if (index == RT_NULL) { - return PIN_LOW; + return -RT_EINVAL; } if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) { diff --git a/bsp/mm32l3xx/drivers/drv_uart.c b/bsp/mm32l3xx/drivers/drv_uart.c index 65125b2339b..4ac6923bb59 100644 --- a/bsp/mm32l3xx/drivers/drv_uart.c +++ b/bsp/mm32l3xx/drivers/drv_uart.c @@ -67,12 +67,12 @@ static rt_err_t mm32_uart_control(struct rt_serial_device *serial, int cmd, void case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ NVIC_DisableIRQ(uart->irq); - UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE); + UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ NVIC_EnableIRQ(uart->irq); - /* enable interrupt */ + /* enable interrupt */ UART_ITConfig(uart->uart, UART_IT_RXIEN, ENABLE); break; } @@ -165,15 +165,15 @@ void UART2_IRQHandler(void) static void UART1PINconfigStepA(void) { /* Enable UART clock */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_UART1, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_UART1, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE); } static void UART1PINconfigStepB(void) { - + GPIO_InitTypeDef GPIO_InitStructure; /* Configure USART Rx/tx PIN */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; @@ -191,9 +191,9 @@ static void UART1PINconfigStepB(void) static void UART2PINconfigStepA(void) { /* Enable UART clock */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART2, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART2, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE); } @@ -219,8 +219,8 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART1 UART1PINconfigStepA(); uart = &uart1; - uart->uart = UART1; - uart->irq = UART1_IRQn; + uart->uart = UART1; + uart->irq = UART1_IRQn; config.baud_rate = BAUD_RATE_115200; serial1.ops = &mm32_uart_ops; serial1.config = config; @@ -234,8 +234,8 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART2 UART2PINconfigStepA(); uart = &uart2; - uart->uart = UART2; - uart->irq = UART2_IRQn; + uart->uart = UART2; + uart->irq = UART2_IRQn; config.baud_rate = BAUD_RATE_115200; serial2.ops = &mm32_uart_ops; serial2.config = config; diff --git a/bsp/mm32l3xx/project.ewp b/bsp/mm32l3xx/project.ewp index 74119398c65..117eec0e8d3 100644 --- a/bsp/mm32l3xx/project.ewp +++ b/bsp/mm32l3xx/project.ewp @@ -2152,6 +2152,9 @@ $PROJ_DIR$\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c @@ -2273,67 +2276,67 @@ Libraries - $PROJ_DIR$\Libraries\MM32L3xx\Source\IAR_StartAsm\startup_MM32L3xx.s + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_gpio.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_flash.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_i2c.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_iwdg.c + $PROJ_DIR$\Libraries\MM32L3xx\Source\IAR_StartAsm\startup_MM32L3xx.s - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_dma.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_exti.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_spi.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_iwdg.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_gpio.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_uart.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_uart.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_rcc.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_i2c.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_bkp.c $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_wwdg.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_tim.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_adc.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_adc.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_rtc.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_misc.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_can.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_bkp.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_pwr.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_can.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_crc.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_pwr.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_tim.c - $PROJ_DIR$\Libraries\MM32L3xx\Source\system_MM32L3xx.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_flash.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_rcc.c + $PROJ_DIR$\Libraries\MM32L3xx\Source\system_MM32L3xx.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_crc.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_dac.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_exti.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_misc.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_rtc.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_spi.c - $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_dac.c + $PROJ_DIR$\Libraries\MM32L3xx\HAL_lib\src\HAL_dma.c diff --git a/bsp/mm32l3xx/project.uvprojx b/bsp/mm32l3xx/project.uvprojx index dfdc8a6f440..7354fc59eb9 100644 --- a/bsp/mm32l3xx/project.uvprojx +++ b/bsp/mm32l3xx/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1035,9 +1054,16 @@ Libraries - HAL_rtc.c + HAL_spi.c 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_rtc.c + Libraries\MM32L3xx\HAL_lib\src\HAL_spi.c + + + + + HAL_rcc.c + 1 + Libraries\MM32L3xx\HAL_lib\src\HAL_rcc.c @@ -1049,44 +1075,44 @@ - HAL_flash.c + HAL_i2c.c 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_flash.c + Libraries\MM32L3xx\HAL_lib\src\HAL_i2c.c - HAL_misc.c + HAL_adc.c 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_misc.c + Libraries\MM32L3xx\HAL_lib\src\HAL_adc.c - HAL_dma.c + HAL_pwr.c 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_dma.c + Libraries\MM32L3xx\HAL_lib\src\HAL_pwr.c - HAL_i2c.c + HAL_misc.c 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_i2c.c + Libraries\MM32L3xx\HAL_lib\src\HAL_misc.c - HAL_pwr.c + HAL_iwdg.c 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_pwr.c + Libraries\MM32L3xx\HAL_lib\src\HAL_iwdg.c - HAL_rcc.c + HAL_exti.c 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_rcc.c + Libraries\MM32L3xx\HAL_lib\src\HAL_exti.c @@ -1098,30 +1124,30 @@ - HAL_uart.c + HAL_dac.c 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_uart.c + Libraries\MM32L3xx\HAL_lib\src\HAL_dac.c - HAL_dac.c + HAL_uart.c 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_dac.c + Libraries\MM32L3xx\HAL_lib\src\HAL_uart.c - HAL_gpio.c + HAL_wwdg.c 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_gpio.c + Libraries\MM32L3xx\HAL_lib\src\HAL_wwdg.c - HAL_crc.c + HAL_flash.c 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_crc.c + Libraries\MM32L3xx\HAL_lib\src\HAL_flash.c @@ -1140,23 +1166,23 @@ - HAL_adc.c + HAL_crc.c 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_adc.c + Libraries\MM32L3xx\HAL_lib\src\HAL_crc.c - HAL_spi.c + HAL_gpio.c 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_spi.c + Libraries\MM32L3xx\HAL_lib\src\HAL_gpio.c - HAL_iwdg.c + HAL_dma.c 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_iwdg.c + Libraries\MM32L3xx\HAL_lib\src\HAL_dma.c @@ -1168,16 +1194,9 @@ - HAL_exti.c - 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_exti.c - - - - - HAL_wwdg.c + HAL_rtc.c 1 - Libraries\MM32L3xx\HAL_lib\src\HAL_wwdg.c + Libraries\MM32L3xx\HAL_lib\src\HAL_rtc.c diff --git a/bsp/msp432e401y-LaunchPad/libraries/Drivers/drv_gpio.c b/bsp/msp432e401y-LaunchPad/libraries/Drivers/drv_gpio.c index b7ae061f277..f4d3b22e8ef 100644 --- a/bsp/msp432e401y-LaunchPad/libraries/Drivers/drv_gpio.c +++ b/bsp/msp432e401y-LaunchPad/libraries/Drivers/drv_gpio.c @@ -264,15 +264,19 @@ static void msp432_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t } } -static rt_int8_t msp432_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t msp432_pin_read(struct rt_device *device, rt_base_t pin) { const struct pin_index *index = RT_NULL; - rt_int8_t value = -1; + rt_ssize_t value = -1; index = _get_pin(pin); if (index != RT_NULL) { - value = (rt_int8_t)GPIOPinRead(index->gpioBaseAddress, index->pin); + value = (rt_ssize_t)GPIOPinRead(index->gpioBaseAddress, index->pin); + } + else + { + value = -RT_EINVAL; } return value; diff --git a/bsp/msp432e401y-LaunchPad/project.ewp b/bsp/msp432e401y-LaunchPad/project.ewp index 5b8d13ae217..6a13690c52a 100644 --- a/bsp/msp432e401y-LaunchPad/project.ewp +++ b/bsp/msp432e401y-LaunchPad/project.ewp @@ -2148,6 +2148,9 @@ $PROJ_DIR$\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/msp432e401y-LaunchPad/project.uvproj b/bsp/msp432e401y-LaunchPad/project.uvproj index dbc8bbb0ab1..0f8239cd39c 100644 --- a/bsp/msp432e401y-LaunchPad/project.uvproj +++ b/bsp/msp432e401y-LaunchPad/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/msp432e401y-LaunchPad/project.uvprojx b/bsp/msp432e401y-LaunchPad/project.uvprojx index c523dc1f723..bc1a2a60f4f 100644 --- a/bsp/msp432e401y-LaunchPad/project.uvprojx +++ b/bsp/msp432e401y-LaunchPad/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/n32/libraries/n32_drivers/drv_gpio.c b/bsp/n32/libraries/n32_drivers/drv_gpio.c index 9f8efb74f7a..1f8a120e56f 100644 --- a/bsp/n32/libraries/n32_drivers/drv_gpio.c +++ b/bsp/n32/libraries/n32_drivers/drv_gpio.c @@ -218,9 +218,9 @@ static void n32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) GPIO_WriteBit(index->gpio, index->pin, (Bit_OperateType)value); } -static rt_int8_t n32_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t n32_pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value; + rt_ssize_t value; const struct pin_index *index; value = PIN_LOW; @@ -228,7 +228,7 @@ static rt_int8_t n32_pin_read(rt_device_t dev, rt_base_t pin) index = get_pin(pin); if (index == RT_NULL) { - return value; + return -RT_EINVAL; } value = GPIO_ReadInputDataBit(index->gpio, index->pin); diff --git a/bsp/n32/n32g43xcl-stb/project.ewp b/bsp/n32/n32g43xcl-stb/project.ewp index 2e4638a4b7d..f4e02e89bf4 100644 --- a/bsp/n32/n32g43xcl-stb/project.ewp +++ b/bsp/n32/n32g43xcl-stb/project.ewp @@ -2247,6 +2247,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/n32/n32g43xcl-stb/project.uvprojx b/bsp/n32/n32g43xcl-stb/project.uvprojx index 7e165417890..48b3b00222d 100644 --- a/bsp/n32/n32g43xcl-stb/project.uvprojx +++ b/bsp/n32/n32g43xcl-stb/project.uvprojx @@ -581,6 +581,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/n32/n32g457qel-stb/project.ewp b/bsp/n32/n32g457qel-stb/project.ewp index e314998f061..4477ec234e5 100644 --- a/bsp/n32/n32g457qel-stb/project.ewp +++ b/bsp/n32/n32g457qel-stb/project.ewp @@ -2247,6 +2247,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/n32/n32g457qel-stb/project.uvprojx b/bsp/n32/n32g457qel-stb/project.uvprojx index fa4d5896505..7533e9cff2e 100644 --- a/bsp/n32/n32g457qel-stb/project.uvprojx +++ b/bsp/n32/n32g457qel-stb/project.uvprojx @@ -581,6 +581,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/n32/n32g45xcl-stb/project.ewp b/bsp/n32/n32g45xcl-stb/project.ewp index 30fd9c935a2..a1577d86248 100644 --- a/bsp/n32/n32g45xcl-stb/project.ewp +++ b/bsp/n32/n32g45xcl-stb/project.ewp @@ -2247,6 +2247,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/n32/n32g45xcl-stb/project.uvprojx b/bsp/n32/n32g45xcl-stb/project.uvprojx index 5dddbe2aa8f..ca8b3ed98d9 100644 --- a/bsp/n32/n32g45xcl-stb/project.uvprojx +++ b/bsp/n32/n32g45xcl-stb/project.uvprojx @@ -581,6 +581,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/n32/n32g45xml-stb/project.ewp b/bsp/n32/n32g45xml-stb/project.ewp index 6aa9d3588bc..137ac31f3d6 100644 --- a/bsp/n32/n32g45xml-stb/project.ewp +++ b/bsp/n32/n32g45xml-stb/project.ewp @@ -2247,6 +2247,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/n32/n32g45xml-stb/project.uvprojx b/bsp/n32/n32g45xml-stb/project.uvprojx index fd1230ca5b9..adcd9719e07 100644 --- a/bsp/n32/n32g45xml-stb/project.uvprojx +++ b/bsp/n32/n32g45xml-stb/project.uvprojx @@ -581,6 +581,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/n32/n32g45xrl-stb/project.ewp b/bsp/n32/n32g45xrl-stb/project.ewp index cfcbaf4f345..f80963a7306 100644 --- a/bsp/n32/n32g45xrl-stb/project.ewp +++ b/bsp/n32/n32g45xrl-stb/project.ewp @@ -2247,6 +2247,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/n32/n32g45xrl-stb/project.uvprojx b/bsp/n32/n32g45xrl-stb/project.uvprojx index a0cddcf553c..13b82fce396 100644 --- a/bsp/n32/n32g45xrl-stb/project.uvprojx +++ b/bsp/n32/n32g45xrl-stb/project.uvprojx @@ -581,6 +581,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/n32/n32g45xvl-stb/project.ewp b/bsp/n32/n32g45xvl-stb/project.ewp index 31e7bb1e438..435691ae757 100644 --- a/bsp/n32/n32g45xvl-stb/project.ewp +++ b/bsp/n32/n32g45xvl-stb/project.ewp @@ -2247,6 +2247,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/n32/n32g45xvl-stb/project.uvprojx b/bsp/n32/n32g45xvl-stb/project.uvprojx index dc2f8d0b9f6..378eac257ba 100644 --- a/bsp/n32/n32g45xvl-stb/project.uvprojx +++ b/bsp/n32/n32g45xvl-stb/project.uvprojx @@ -581,6 +581,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/n32/n32g4frml-stb/project.ewp b/bsp/n32/n32g4frml-stb/project.ewp index ff1d7cacc67..fd38fc028bd 100644 --- a/bsp/n32/n32g4frml-stb/project.ewp +++ b/bsp/n32/n32g4frml-stb/project.ewp @@ -2223,6 +2223,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/n32/n32g4frml-stb/project.uvprojx b/bsp/n32/n32g4frml-stb/project.uvprojx index 09fd33d0531..46a4f48f68e 100644 --- a/bsp/n32/n32g4frml-stb/project.uvprojx +++ b/bsp/n32/n32g4frml-stb/project.uvprojx @@ -581,6 +581,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/n32/n32l40xcl-stb/project.ewp b/bsp/n32/n32l40xcl-stb/project.ewp index 754c606aa86..b9c17fd8566 100644 --- a/bsp/n32/n32l40xcl-stb/project.ewp +++ b/bsp/n32/n32l40xcl-stb/project.ewp @@ -2247,6 +2247,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/n32/n32l40xcl-stb/project.uvprojx b/bsp/n32/n32l40xcl-stb/project.uvprojx index 6e9586eab59..06c2bdacaad 100644 --- a/bsp/n32/n32l40xcl-stb/project.uvprojx +++ b/bsp/n32/n32l40xcl-stb/project.uvprojx @@ -581,6 +581,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/n32/n32l436-evb/project.ewp b/bsp/n32/n32l436-evb/project.ewp index 7f0ca47b249..149f56d1879 100644 --- a/bsp/n32/n32l436-evb/project.ewp +++ b/bsp/n32/n32l436-evb/project.ewp @@ -2247,6 +2247,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/n32/n32l436-evb/project.uvprojx b/bsp/n32/n32l436-evb/project.uvprojx index 47e41952b4e..78644d11ff5 100644 --- a/bsp/n32/n32l436-evb/project.uvprojx +++ b/bsp/n32/n32l436-evb/project.uvprojx @@ -581,6 +581,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/n32/n32l43xml-stb/project.ewp b/bsp/n32/n32l43xml-stb/project.ewp index 7f0ca47b249..149f56d1879 100644 --- a/bsp/n32/n32l43xml-stb/project.ewp +++ b/bsp/n32/n32l43xml-stb/project.ewp @@ -2247,6 +2247,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/n32/n32l43xml-stb/project.uvprojx b/bsp/n32/n32l43xml-stb/project.uvprojx index 0c927be1506..3172641c3a2 100644 --- a/bsp/n32/n32l43xml-stb/project.uvprojx +++ b/bsp/n32/n32l43xml-stb/project.uvprojx @@ -581,6 +581,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/n32/n32l43xrl-stb/project.ewp b/bsp/n32/n32l43xrl-stb/project.ewp index eb86858ea66..94fef3069f6 100644 --- a/bsp/n32/n32l43xrl-stb/project.ewp +++ b/bsp/n32/n32l43xrl-stb/project.ewp @@ -2247,6 +2247,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/n32/n32l43xrl-stb/project.uvprojx b/bsp/n32/n32l43xrl-stb/project.uvprojx index 7e0824a73d5..63a19a6d3c8 100644 --- a/bsp/n32/n32l43xrl-stb/project.uvprojx +++ b/bsp/n32/n32l43xrl-stb/project.uvprojx @@ -581,6 +581,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/n32/n32wb45xl-evb/project.ewp b/bsp/n32/n32wb45xl-evb/project.ewp index df843a84ab2..f9037efd239 100644 --- a/bsp/n32/n32wb45xl-evb/project.ewp +++ b/bsp/n32/n32wb45xl-evb/project.ewp @@ -2247,6 +2247,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/n32/n32wb45xl-evb/project.uvprojx b/bsp/n32/n32wb45xl-evb/project.uvprojx index 4c6b4b624cf..c4245bb2716 100644 --- a/bsp/n32/n32wb45xl-evb/project.uvprojx +++ b/bsp/n32/n32wb45xl-evb/project.uvprojx @@ -581,6 +581,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c index bdc3b4eed4c..499ade914aa 100644 --- a/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c @@ -578,9 +578,9 @@ void n32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -rt_int8_t n32_pin_read(rt_device_t dev, rt_base_t pin) +rt_ssize_t n32_pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value; + rt_ssize_t value; const struct pin_index *index; value = PIN_LOW; @@ -588,7 +588,7 @@ rt_int8_t n32_pin_read(rt_device_t dev, rt_base_t pin) index = get_pin(pin); if (index == RT_NULL) { - return value; + return -RT_EINVAL; } if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) diff --git a/bsp/n32g452xx/n32g452xx-mini-system/project.uvprojx b/bsp/n32g452xx/n32g452xx-mini-system/project.uvprojx index 540c299f74e..ecc93f2b64e 100755 --- a/bsp/n32g452xx/n32g452xx-mini-system/project.uvprojx +++ b/bsp/n32g452xx/n32g452xx-mini-system/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1044,121 +1063,121 @@ Libraries - n32g45x_i2c.c + n32g45x_tsc.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_i2c.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_tsc.c - n32g45x_can.c + n32g45x_exti.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_can.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_exti.c - n32g45x_adc.c + n32g45x_rcc.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_adc.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_rcc.c - n32g45x_eth.c + n32g45x_rtc.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_eth.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_rtc.c - n32g45x_dbg.c + n32g45x_xfmc.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dbg.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_xfmc.c - n32g45x_xfmc.c + n32g45x_dma.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_xfmc.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dma.c - n32g45x_wwdg.c + n32g45x_can.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_wwdg.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_can.c - misc.c + n32g45x_dbg.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\misc.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dbg.c - n32g45x_comp.c + n32g45x_flash.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_comp.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_flash.c - n32g45x_pwr.c + n32g45x_wwdg.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_pwr.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_wwdg.c - n32g45x_flash.c + n32g45x_gpio.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_flash.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_gpio.c - n32g45x_iwdg.c + n32g45x_i2c.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_iwdg.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_i2c.c - n32g45x_tsc.c + n32g45x_pwr.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_tsc.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_pwr.c - n32g45x_crc.c + n32g45x_usart.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_crc.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_usart.c - n32g45x_gpio.c + n32g45x_iwdg.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_gpio.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_iwdg.c - n32g45x_exti.c + misc.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_exti.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\misc.c - n32g45x_qspi.c + n32g45x_opamp.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_qspi.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_opamp.c @@ -1170,58 +1189,58 @@ - n32g45x_dvp.c + n32g45x_spi.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dvp.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_spi.c - n32g45x_sdio.c + n32g45x_adc.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_sdio.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_adc.c - n32g45x_rtc.c + n32g45x_eth.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_rtc.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_eth.c - n32g45x_usart.c + n32g45x_dvp.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_usart.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dvp.c - n32g45x_spi.c + n32g45x_qspi.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_spi.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_qspi.c - n32g45x_rcc.c + n32g45x_comp.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_rcc.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_comp.c - n32g45x_dac.c + n32g45x_tim.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dac.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_tim.c - n32g45x_dma.c + n32g45x_sdio.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dma.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_sdio.c @@ -1233,16 +1252,16 @@ - n32g45x_tim.c + n32g45x_crc.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_tim.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_crc.c - n32g45x_opamp.c + n32g45x_dac.c 1 - ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_opamp.c + ..\Libraries\N32_Std_Driver\n32g45x_std_periph_driver\src\n32g45x_dac.c diff --git a/bsp/nrf5x/libraries/drivers/drv_gpio.c b/bsp/nrf5x/libraries/drivers/drv_gpio.c index 34933cdaaef..56297eb785b 100644 --- a/bsp/nrf5x/libraries/drivers/drv_gpio.c +++ b/bsp/nrf5x/libraries/drivers/drv_gpio.c @@ -114,9 +114,9 @@ static void nrf5x_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) nrf_gpio_pin_write(pin, value); } -static rt_int8_t nrf5x_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t nrf5x_pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value; + rt_ssize_t value; const struct pin_index *index; value = PIN_LOW; @@ -124,7 +124,7 @@ static rt_int8_t nrf5x_pin_read(rt_device_t dev, rt_base_t pin) index = get_pin(pin); if (index == RT_NULL) { - return value; + return -RT_EINVAL; } value = nrf_gpio_pin_read(pin); diff --git a/bsp/nrf5x/nrf51822/project.uvprojx b/bsp/nrf5x/nrf51822/project.uvprojx index 3f4099af414..3beb269a15d 100644 --- a/bsp/nrf5x/nrf51822/project.uvprojx +++ b/bsp/nrf5x/nrf51822/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1009,261 +1028,261 @@ nrf_Drivers - nrfx_nfct.c + nrfx_spi.c 1 - packages\nrfx-latest\drivers\src\nrfx_nfct.c + packages\nrfx-latest\drivers\src\nrfx_spi.c - nrfx_dppi.c + nrfx_twi_twim.c 1 - packages\nrfx-latest\drivers\src\nrfx_dppi.c + packages\nrfx-latest\drivers\src\nrfx_twi_twim.c - nrfx_rng.c + nrfx_lpcomp.c 1 - packages\nrfx-latest\drivers\src\nrfx_rng.c + packages\nrfx-latest\drivers\src\nrfx_lpcomp.c - nrfx_wdt.c + nrfx_pdm.c 1 - packages\nrfx-latest\drivers\src\nrfx_wdt.c + packages\nrfx-latest\drivers\src\nrfx_pdm.c - nrfx_ppi.c + nrfx_gpiote.c 1 - packages\nrfx-latest\drivers\src\nrfx_ppi.c + packages\nrfx-latest\drivers\src\nrfx_gpiote.c - nrfx_ipc.c + nrfx_systick.c 1 - packages\nrfx-latest\drivers\src\nrfx_ipc.c + packages\nrfx-latest\drivers\src\nrfx_systick.c - nrfx_adc.c + nrfx_usbreg.c 1 - packages\nrfx-latest\drivers\src\nrfx_adc.c + packages\nrfx-latest\drivers\src\nrfx_usbreg.c - nrfx_timer.c + nrfx_usbd.c 1 - packages\nrfx-latest\drivers\src\nrfx_timer.c + packages\nrfx-latest\drivers\src\nrfx_usbd.c - nrfx_qspi.c + nrfx_nvmc.c 1 - packages\nrfx-latest\drivers\src\nrfx_qspi.c + packages\nrfx-latest\drivers\src\nrfx_nvmc.c - nrfx_twim.c + nrfx_spis.c 1 - packages\nrfx-latest\drivers\src\nrfx_twim.c + packages\nrfx-latest\drivers\src\nrfx_spis.c - nrfx_twi.c + system_nrf51.c 1 - packages\nrfx-latest\drivers\src\nrfx_twi.c + packages\nrfx-latest\mdk\system_nrf51.c - nrfx_uarte.c + nrfx_temp.c 1 - packages\nrfx-latest\drivers\src\nrfx_uarte.c + packages\nrfx-latest\drivers\src\nrfx_temp.c - nrfx_usbreg.c + nrfx_wdt.c 1 - packages\nrfx-latest\drivers\src\nrfx_usbreg.c + packages\nrfx-latest\drivers\src\nrfx_wdt.c - nrfx_power.c + nrfx_pwm.c 1 - packages\nrfx-latest\drivers\src\nrfx_power.c + packages\nrfx-latest\drivers\src\nrfx_pwm.c - system_nrf51.c + nrfx_nfct.c 1 - packages\nrfx-latest\mdk\system_nrf51.c + packages\nrfx-latest\drivers\src\nrfx_nfct.c - nrfx_pwm.c + nrfx_saadc.c 1 - packages\nrfx-latest\drivers\src\nrfx_pwm.c + packages\nrfx-latest\drivers\src\nrfx_saadc.c - nrfx_uart.c + nrfx_i2s.c 1 - packages\nrfx-latest\drivers\src\nrfx_uart.c + packages\nrfx-latest\drivers\src\nrfx_i2s.c - nrfx_comp.c + nrfx_spim.c 1 - packages\nrfx-latest\drivers\src\nrfx_comp.c + packages\nrfx-latest\drivers\src\nrfx_spim.c - nrfx_usbd.c + nrfx_dppi.c 1 - packages\nrfx-latest\drivers\src\nrfx_usbd.c + packages\nrfx-latest\drivers\src\nrfx_dppi.c - nrfx_clock.c + nrfx_ipc.c 1 - packages\nrfx-latest\drivers\src\nrfx_clock.c + packages\nrfx-latest\drivers\src\nrfx_ipc.c - arm_startup_nrf51.s - 2 - packages\nrfx-latest\mdk\arm_startup_nrf51.s + nrfx_twi.c + 1 + packages\nrfx-latest\drivers\src\nrfx_twi.c - nrfx_pdm.c + nrfx_clock.c 1 - packages\nrfx-latest\drivers\src\nrfx_pdm.c + packages\nrfx-latest\drivers\src\nrfx_clock.c - nrfx_twi_twim.c - 1 - packages\nrfx-latest\drivers\src\nrfx_twi_twim.c + arm_startup_nrf51.s + 2 + packages\nrfx-latest\mdk\arm_startup_nrf51.s - nrfx_qdec.c + nrfx_twim.c 1 - packages\nrfx-latest\drivers\src\nrfx_qdec.c + packages\nrfx-latest\drivers\src\nrfx_twim.c - nrfx_temp.c + nrfx_ppi.c 1 - packages\nrfx-latest\drivers\src\nrfx_temp.c + packages\nrfx-latest\drivers\src\nrfx_ppi.c - nrfx_systick.c + nrfx_comp.c 1 - packages\nrfx-latest\drivers\src\nrfx_systick.c + packages\nrfx-latest\drivers\src\nrfx_comp.c - nrfx_spim.c + nrfx_rtc.c 1 - packages\nrfx-latest\drivers\src\nrfx_spim.c + packages\nrfx-latest\drivers\src\nrfx_rtc.c - nrfx_lpcomp.c + nrfx_adc.c 1 - packages\nrfx-latest\drivers\src\nrfx_lpcomp.c + packages\nrfx-latest\drivers\src\nrfx_adc.c - nrfx_spi.c + nrfx_qdec.c 1 - packages\nrfx-latest\drivers\src\nrfx_spi.c + packages\nrfx-latest\drivers\src\nrfx_qdec.c - nrfx_nvmc.c + nrfx_timer.c 1 - packages\nrfx-latest\drivers\src\nrfx_nvmc.c + packages\nrfx-latest\drivers\src\nrfx_timer.c - nrfx_spis.c + nrfx_rng.c 1 - packages\nrfx-latest\drivers\src\nrfx_spis.c + packages\nrfx-latest\drivers\src\nrfx_rng.c - nrfx_i2s.c + nrfx_egu.c 1 - packages\nrfx-latest\drivers\src\nrfx_i2s.c + packages\nrfx-latest\drivers\src\nrfx_egu.c - nrfx_twis.c + nrfx_uarte.c 1 - packages\nrfx-latest\drivers\src\nrfx_twis.c + packages\nrfx-latest\drivers\src\nrfx_uarte.c - nrfx_saadc.c + nrfx_power.c 1 - packages\nrfx-latest\drivers\src\nrfx_saadc.c + packages\nrfx-latest\drivers\src\nrfx_power.c - nrfx_egu.c + nrfx_uart.c 1 - packages\nrfx-latest\drivers\src\nrfx_egu.c + packages\nrfx-latest\drivers\src\nrfx_uart.c - nrfx_rtc.c + nrfx_qspi.c 1 - packages\nrfx-latest\drivers\src\nrfx_rtc.c + packages\nrfx-latest\drivers\src\nrfx_qspi.c - nrfx_gpiote.c + nrfx_twis.c 1 - packages\nrfx-latest\drivers\src\nrfx_gpiote.c + packages\nrfx-latest\drivers\src\nrfx_twis.c diff --git a/bsp/nrf5x/nrf52832/project.uvprojx b/bsp/nrf5x/nrf52832/project.uvprojx index c0ae420660f..b971fe4eb0c 100644 --- a/bsp/nrf5x/nrf52832/project.uvprojx +++ b/bsp/nrf5x/nrf52832/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1016,100 +1035,93 @@ nrf_Drivers - nrfx_adc.c - 1 - packages\nrfx-latest\drivers\src\nrfx_adc.c - - - - - nrfx_power.c + nrfx_ppi.c 1 - packages\nrfx-latest\drivers\src\nrfx_power.c + packages\nrfx-latest\drivers\src\nrfx_ppi.c - nrfx_spis.c + nrfx_dppi.c 1 - packages\nrfx-latest\drivers\src\nrfx_spis.c + packages\nrfx-latest\drivers\src\nrfx_dppi.c - nrfx_saadc.c + nrfx_lpcomp.c 1 - packages\nrfx-latest\drivers\src\nrfx_saadc.c + packages\nrfx-latest\drivers\src\nrfx_lpcomp.c - nrfx_i2s.c + nrfx_spi.c 1 - packages\nrfx-latest\drivers\src\nrfx_i2s.c + packages\nrfx-latest\drivers\src\nrfx_spi.c - nrfx_usbd.c + nrfx_temp.c 1 - packages\nrfx-latest\drivers\src\nrfx_usbd.c + packages\nrfx-latest\drivers\src\nrfx_temp.c - nrfx_temp.c + nrfx_qspi.c 1 - packages\nrfx-latest\drivers\src\nrfx_temp.c + packages\nrfx-latest\drivers\src\nrfx_qspi.c - nrfx_uart.c + nrfx_usbreg.c 1 - packages\nrfx-latest\drivers\src\nrfx_uart.c + packages\nrfx-latest\drivers\src\nrfx_usbreg.c - system_nrf52.c + nrfx_comp.c 1 - packages\nrfx-latest\mdk\system_nrf52.c + packages\nrfx-latest\drivers\src\nrfx_comp.c - nrfx_pwm.c + nrfx_adc.c 1 - packages\nrfx-latest\drivers\src\nrfx_pwm.c + packages\nrfx-latest\drivers\src\nrfx_adc.c - nrfx_spi.c + nrfx_qdec.c 1 - packages\nrfx-latest\drivers\src\nrfx_spi.c + packages\nrfx-latest\drivers\src\nrfx_qdec.c - nrfx_dppi.c + nrfx_timer.c 1 - packages\nrfx-latest\drivers\src\nrfx_dppi.c + packages\nrfx-latest\drivers\src\nrfx_timer.c - nrfx_clock.c + system_nrf52.c 1 - packages\nrfx-latest\drivers\src\nrfx_clock.c + packages\nrfx-latest\mdk\system_nrf52.c - nrfx_spim.c + nrfx_uart.c 1 - packages\nrfx-latest\drivers\src\nrfx_spim.c + packages\nrfx-latest\drivers\src\nrfx_uart.c @@ -1121,30 +1133,30 @@ - arm_startup_nrf52.s - 2 - packages\nrfx-latest\mdk\arm_startup_nrf52.s + nrfx_spim.c + 1 + packages\nrfx-latest\drivers\src\nrfx_spim.c - nrfx_twi.c + nrfx_twis.c 1 - packages\nrfx-latest\drivers\src\nrfx_twi.c + packages\nrfx-latest\drivers\src\nrfx_twis.c - nrfx_nfct.c + nrfx_saadc.c 1 - packages\nrfx-latest\drivers\src\nrfx_nfct.c + packages\nrfx-latest\drivers\src\nrfx_saadc.c - nrfx_ipc.c + nrfx_clock.c 1 - packages\nrfx-latest\drivers\src\nrfx_ipc.c + packages\nrfx-latest\drivers\src\nrfx_clock.c @@ -1156,121 +1168,128 @@ - nrfx_rng.c + arm_startup_nrf52.s + 2 + packages\nrfx-latest\mdk\arm_startup_nrf52.s + + + + + nrfx_spis.c 1 - packages\nrfx-latest\drivers\src\nrfx_rng.c + packages\nrfx-latest\drivers\src\nrfx_spis.c - nrfx_systick.c + nrfx_i2s.c 1 - packages\nrfx-latest\drivers\src\nrfx_systick.c + packages\nrfx-latest\drivers\src\nrfx_i2s.c - nrfx_egu.c + nrfx_pwm.c 1 - packages\nrfx-latest\drivers\src\nrfx_egu.c + packages\nrfx-latest\drivers\src\nrfx_pwm.c - nrfx_qdec.c + nrfx_power.c 1 - packages\nrfx-latest\drivers\src\nrfx_qdec.c + packages\nrfx-latest\drivers\src\nrfx_power.c - nrfx_twi_twim.c + nrfx_rng.c 1 - packages\nrfx-latest\drivers\src\nrfx_twi_twim.c + packages\nrfx-latest\drivers\src\nrfx_rng.c - nrfx_ppi.c + nrfx_twim.c 1 - packages\nrfx-latest\drivers\src\nrfx_ppi.c + packages\nrfx-latest\drivers\src\nrfx_twim.c - nrfx_timer.c + nrfx_nvmc.c 1 - packages\nrfx-latest\drivers\src\nrfx_timer.c + packages\nrfx-latest\drivers\src\nrfx_nvmc.c - nrfx_uarte.c + nrfx_systick.c 1 - packages\nrfx-latest\drivers\src\nrfx_uarte.c + packages\nrfx-latest\drivers\src\nrfx_systick.c - nrfx_comp.c + nrfx_usbd.c 1 - packages\nrfx-latest\drivers\src\nrfx_comp.c + packages\nrfx-latest\drivers\src\nrfx_usbd.c - nrfx_twim.c + nrfx_twi_twim.c 1 - packages\nrfx-latest\drivers\src\nrfx_twim.c + packages\nrfx-latest\drivers\src\nrfx_twi_twim.c - nrfx_nvmc.c + nrfx_nfct.c 1 - packages\nrfx-latest\drivers\src\nrfx_nvmc.c + packages\nrfx-latest\drivers\src\nrfx_nfct.c - nrfx_usbreg.c + nrfx_gpiote.c 1 - packages\nrfx-latest\drivers\src\nrfx_usbreg.c + packages\nrfx-latest\drivers\src\nrfx_gpiote.c - nrfx_twis.c + nrfx_egu.c 1 - packages\nrfx-latest\drivers\src\nrfx_twis.c + packages\nrfx-latest\drivers\src\nrfx_egu.c - nrfx_rtc.c + nrfx_ipc.c 1 - packages\nrfx-latest\drivers\src\nrfx_rtc.c + packages\nrfx-latest\drivers\src\nrfx_ipc.c - nrfx_gpiote.c + nrfx_uarte.c 1 - packages\nrfx-latest\drivers\src\nrfx_gpiote.c + packages\nrfx-latest\drivers\src\nrfx_uarte.c - nrfx_qspi.c + nrfx_rtc.c 1 - packages\nrfx-latest\drivers\src\nrfx_qspi.c + packages\nrfx-latest\drivers\src\nrfx_rtc.c - nrfx_lpcomp.c + nrfx_twi.c 1 - packages\nrfx-latest\drivers\src\nrfx_lpcomp.c + packages\nrfx-latest\drivers\src\nrfx_twi.c diff --git a/bsp/nrf5x/nrf52833/project.uvprojx b/bsp/nrf5x/nrf52833/project.uvprojx index 6fd89c57b87..1d5a9b1a58e 100644 --- a/bsp/nrf5x/nrf52833/project.uvprojx +++ b/bsp/nrf5x/nrf52833/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1009,9 +1028,16 @@ nrf_Drivers - nrfx_qdec.c + nrfx_comp.c 1 - packages\nrfx-latest\drivers\src\nrfx_qdec.c + packages\nrfx-latest\drivers\src\nrfx_comp.c + + + + + nrfx_qspi.c + 1 + packages\nrfx-latest\drivers\src\nrfx_qspi.c @@ -1023,135 +1049,135 @@ - nrfx_nfct.c + nrfx_dppi.c 1 - packages\nrfx-latest\drivers\src\nrfx_nfct.c + packages\nrfx-latest\drivers\src\nrfx_dppi.c - nrfx_i2s.c + nrfx_power.c 1 - packages\nrfx-latest\drivers\src\nrfx_i2s.c + packages\nrfx-latest\drivers\src\nrfx_power.c - nrfx_clock.c + nrfx_ipc.c 1 - packages\nrfx-latest\drivers\src\nrfx_clock.c + packages\nrfx-latest\drivers\src\nrfx_ipc.c - nrfx_lpcomp.c + nrfx_rtc.c 1 - packages\nrfx-latest\drivers\src\nrfx_lpcomp.c + packages\nrfx-latest\drivers\src\nrfx_rtc.c - nrfx_uart.c + nrfx_spi.c 1 - packages\nrfx-latest\drivers\src\nrfx_uart.c + packages\nrfx-latest\drivers\src\nrfx_spi.c - nrfx_gpiote.c + nrfx_twi_twim.c 1 - packages\nrfx-latest\drivers\src\nrfx_gpiote.c + packages\nrfx-latest\drivers\src\nrfx_twi_twim.c - nrfx_nvmc.c + nrfx_twim.c 1 - packages\nrfx-latest\drivers\src\nrfx_nvmc.c + packages\nrfx-latest\drivers\src\nrfx_twim.c - nrfx_dppi.c + nrfx_rng.c 1 - packages\nrfx-latest\drivers\src\nrfx_dppi.c + packages\nrfx-latest\drivers\src\nrfx_rng.c - nrfx_qspi.c + nrfx_qdec.c 1 - packages\nrfx-latest\drivers\src\nrfx_qspi.c + packages\nrfx-latest\drivers\src\nrfx_qdec.c - nrfx_egu.c + nrfx_systick.c 1 - packages\nrfx-latest\drivers\src\nrfx_egu.c + packages\nrfx-latest\drivers\src\nrfx_systick.c - nrfx_spis.c + nrfx_adc.c 1 - packages\nrfx-latest\drivers\src\nrfx_spis.c + packages\nrfx-latest\drivers\src\nrfx_adc.c - nrfx_spi.c + nrfx_pwm.c 1 - packages\nrfx-latest\drivers\src\nrfx_spi.c + packages\nrfx-latest\drivers\src\nrfx_pwm.c - nrfx_twim.c + nrfx_nvmc.c 1 - packages\nrfx-latest\drivers\src\nrfx_twim.c + packages\nrfx-latest\drivers\src\nrfx_nvmc.c - nrfx_rng.c + nrfx_uart.c 1 - packages\nrfx-latest\drivers\src\nrfx_rng.c + packages\nrfx-latest\drivers\src\nrfx_uart.c - nrfx_wdt.c + nrfx_lpcomp.c 1 - packages\nrfx-latest\drivers\src\nrfx_wdt.c + packages\nrfx-latest\drivers\src\nrfx_lpcomp.c - nrfx_pwm.c + nrfx_clock.c 1 - packages\nrfx-latest\drivers\src\nrfx_pwm.c + packages\nrfx-latest\drivers\src\nrfx_clock.c - nrfx_saadc.c + nrfx_nfct.c 1 - packages\nrfx-latest\drivers\src\nrfx_saadc.c + packages\nrfx-latest\drivers\src\nrfx_nfct.c - nrfx_usbd.c + nrfx_usbreg.c 1 - packages\nrfx-latest\drivers\src\nrfx_usbd.c + packages\nrfx-latest\drivers\src\nrfx_usbreg.c - nrfx_ipc.c + nrfx_pdm.c 1 - packages\nrfx-latest\drivers\src\nrfx_ipc.c + packages\nrfx-latest\drivers\src\nrfx_pdm.c @@ -1163,58 +1189,58 @@ - nrfx_twis.c + nrfx_gpiote.c 1 - packages\nrfx-latest\drivers\src\nrfx_twis.c + packages\nrfx-latest\drivers\src\nrfx_gpiote.c - nrfx_comp.c + nrfx_temp.c 1 - packages\nrfx-latest\drivers\src\nrfx_comp.c + packages\nrfx-latest\drivers\src\nrfx_temp.c - nrfx_power.c + nrfx_i2s.c 1 - packages\nrfx-latest\drivers\src\nrfx_power.c + packages\nrfx-latest\drivers\src\nrfx_i2s.c - nrfx_twi_twim.c + nrfx_spim.c 1 - packages\nrfx-latest\drivers\src\nrfx_twi_twim.c + packages\nrfx-latest\drivers\src\nrfx_spim.c - nrfx_rtc.c - 1 - packages\nrfx-latest\drivers\src\nrfx_rtc.c + arm_startup_nrf52833.s + 2 + packages\nrfx-latest\mdk\arm_startup_nrf52833.s - nrfx_systick.c + nrfx_spis.c 1 - packages\nrfx-latest\drivers\src\nrfx_systick.c + packages\nrfx-latest\drivers\src\nrfx_spis.c - arm_startup_nrf52833.s - 2 - packages\nrfx-latest\mdk\arm_startup_nrf52833.s + nrfx_wdt.c + 1 + packages\nrfx-latest\drivers\src\nrfx_wdt.c - nrfx_temp.c + nrfx_twis.c 1 - packages\nrfx-latest\drivers\src\nrfx_temp.c + packages\nrfx-latest\drivers\src\nrfx_twis.c @@ -1226,37 +1252,30 @@ - nrfx_twi.c - 1 - packages\nrfx-latest\drivers\src\nrfx_twi.c - - - - - nrfx_usbreg.c + nrfx_saadc.c 1 - packages\nrfx-latest\drivers\src\nrfx_usbreg.c + packages\nrfx-latest\drivers\src\nrfx_saadc.c - nrfx_adc.c + nrfx_usbd.c 1 - packages\nrfx-latest\drivers\src\nrfx_adc.c + packages\nrfx-latest\drivers\src\nrfx_usbd.c - nrfx_spim.c + nrfx_egu.c 1 - packages\nrfx-latest\drivers\src\nrfx_spim.c + packages\nrfx-latest\drivers\src\nrfx_egu.c - nrfx_pdm.c + nrfx_twi.c 1 - packages\nrfx-latest\drivers\src\nrfx_pdm.c + packages\nrfx-latest\drivers\src\nrfx_twi.c diff --git a/bsp/nrf5x/nrf52840/project.uvprojx b/bsp/nrf5x/nrf52840/project.uvprojx index 9d6fe7831fd..62a5782fd6b 100644 --- a/bsp/nrf5x/nrf52840/project.uvprojx +++ b/bsp/nrf5x/nrf52840/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1017,212 +1036,212 @@ nrf_Drivers - nrfx_qspi.c + nrfx_gpiote.c 1 - packages\nrfx-latest\drivers\src\nrfx_qspi.c + packages\nrfx-latest\drivers\src\nrfx_gpiote.c - nrfx_spim.c + nrfx_uarte.c 1 - packages\nrfx-latest\drivers\src\nrfx_spim.c + packages\nrfx-latest\drivers\src\nrfx_uarte.c - nrfx_rng.c + nrfx_comp.c 1 - packages\nrfx-latest\drivers\src\nrfx_rng.c + packages\nrfx-latest\drivers\src\nrfx_comp.c - nrfx_pwm.c + nrfx_lpcomp.c 1 - packages\nrfx-latest\drivers\src\nrfx_pwm.c + packages\nrfx-latest\drivers\src\nrfx_lpcomp.c - nrfx_egu.c + nrfx_power.c 1 - packages\nrfx-latest\drivers\src\nrfx_egu.c + packages\nrfx-latest\drivers\src\nrfx_power.c - nrfx_saadc.c + nrfx_twi_twim.c 1 - packages\nrfx-latest\drivers\src\nrfx_saadc.c + packages\nrfx-latest\drivers\src\nrfx_twi_twim.c - nrfx_dppi.c + nrfx_rng.c 1 - packages\nrfx-latest\drivers\src\nrfx_dppi.c + packages\nrfx-latest\drivers\src\nrfx_rng.c - nrfx_qdec.c + nrfx_uart.c 1 - packages\nrfx-latest\drivers\src\nrfx_qdec.c + packages\nrfx-latest\drivers\src\nrfx_uart.c - nrfx_spi.c + nrfx_dppi.c 1 - packages\nrfx-latest\drivers\src\nrfx_spi.c + packages\nrfx-latest\drivers\src\nrfx_dppi.c - nrfx_usbd.c + nrfx_spis.c 1 - packages\nrfx-latest\drivers\src\nrfx_usbd.c + packages\nrfx-latest\drivers\src\nrfx_spis.c - nrfx_uarte.c + nrfx_pwm.c 1 - packages\nrfx-latest\drivers\src\nrfx_uarte.c + packages\nrfx-latest\drivers\src\nrfx_pwm.c - nrfx_nfct.c + nrfx_qspi.c 1 - packages\nrfx-latest\drivers\src\nrfx_nfct.c + packages\nrfx-latest\drivers\src\nrfx_qspi.c - nrfx_ppi.c + nrfx_spim.c 1 - packages\nrfx-latest\drivers\src\nrfx_ppi.c + packages\nrfx-latest\drivers\src\nrfx_spim.c - nrfx_twi.c + nrfx_egu.c 1 - packages\nrfx-latest\drivers\src\nrfx_twi.c + packages\nrfx-latest\drivers\src\nrfx_egu.c - nrfx_lpcomp.c + nrfx_i2s.c 1 - packages\nrfx-latest\drivers\src\nrfx_lpcomp.c + packages\nrfx-latest\drivers\src\nrfx_i2s.c - nrfx_spis.c + nrfx_ppi.c 1 - packages\nrfx-latest\drivers\src\nrfx_spis.c + packages\nrfx-latest\drivers\src\nrfx_ppi.c - nrfx_clock.c + nrfx_adc.c 1 - packages\nrfx-latest\drivers\src\nrfx_clock.c + packages\nrfx-latest\drivers\src\nrfx_adc.c - nrfx_i2s.c + nrfx_qdec.c 1 - packages\nrfx-latest\drivers\src\nrfx_i2s.c + packages\nrfx-latest\drivers\src\nrfx_qdec.c - nrfx_wdt.c + nrfx_spi.c 1 - packages\nrfx-latest\drivers\src\nrfx_wdt.c + packages\nrfx-latest\drivers\src\nrfx_spi.c - arm_startup_nrf52840.s - 2 - packages\nrfx-latest\mdk\arm_startup_nrf52840.s + nrfx_rtc.c + 1 + packages\nrfx-latest\drivers\src\nrfx_rtc.c - nrfx_adc.c + nrfx_twim.c 1 - packages\nrfx-latest\drivers\src\nrfx_adc.c + packages\nrfx-latest\drivers\src\nrfx_twim.c - nrfx_pdm.c - 1 - packages\nrfx-latest\drivers\src\nrfx_pdm.c + arm_startup_nrf52840.s + 2 + packages\nrfx-latest\mdk\arm_startup_nrf52840.s - nrfx_comp.c + nrfx_nvmc.c 1 - packages\nrfx-latest\drivers\src\nrfx_comp.c + packages\nrfx-latest\drivers\src\nrfx_nvmc.c - nrfx_temp.c + nrfx_systick.c 1 - packages\nrfx-latest\drivers\src\nrfx_temp.c + packages\nrfx-latest\drivers\src\nrfx_systick.c - nrfx_rtc.c + nrfx_nfct.c 1 - packages\nrfx-latest\drivers\src\nrfx_rtc.c + packages\nrfx-latest\drivers\src\nrfx_nfct.c - nrfx_uart.c + nrfx_saadc.c 1 - packages\nrfx-latest\drivers\src\nrfx_uart.c + packages\nrfx-latest\drivers\src\nrfx_saadc.c - nrfx_power.c + nrfx_wdt.c 1 - packages\nrfx-latest\drivers\src\nrfx_power.c + packages\nrfx-latest\drivers\src\nrfx_wdt.c - nrfx_usbreg.c + nrfx_twi.c 1 - packages\nrfx-latest\drivers\src\nrfx_usbreg.c + packages\nrfx-latest\drivers\src\nrfx_twi.c - nrfx_timer.c + nrfx_usbreg.c 1 - packages\nrfx-latest\drivers\src\nrfx_timer.c + packages\nrfx-latest\drivers\src\nrfx_usbreg.c - nrfx_gpiote.c + nrfx_clock.c 1 - packages\nrfx-latest\drivers\src\nrfx_gpiote.c + packages\nrfx-latest\drivers\src\nrfx_clock.c @@ -1234,9 +1253,9 @@ - nrfx_systick.c + nrfx_usbd.c 1 - packages\nrfx-latest\drivers\src\nrfx_systick.c + packages\nrfx-latest\drivers\src\nrfx_usbd.c @@ -1248,30 +1267,30 @@ - nrfx_nvmc.c + nrfx_temp.c 1 - packages\nrfx-latest\drivers\src\nrfx_nvmc.c + packages\nrfx-latest\drivers\src\nrfx_temp.c - nrfx_twim.c + nrfx_pdm.c 1 - packages\nrfx-latest\drivers\src\nrfx_twim.c + packages\nrfx-latest\drivers\src\nrfx_pdm.c - nrfx_ipc.c + nrfx_timer.c 1 - packages\nrfx-latest\drivers\src\nrfx_ipc.c + packages\nrfx-latest\drivers\src\nrfx_timer.c - nrfx_twi_twim.c + nrfx_ipc.c 1 - packages\nrfx-latest\drivers\src\nrfx_twi_twim.c + packages\nrfx-latest\drivers\src\nrfx_ipc.c diff --git a/bsp/nrf5x/nrf5340/project.uvprojx b/bsp/nrf5x/nrf5340/project.uvprojx index ed3e2a42dfc..aa665339278 100644 --- a/bsp/nrf5x/nrf5340/project.uvprojx +++ b/bsp/nrf5x/nrf5340/project.uvprojx @@ -562,6 +562,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nuclei/libraries/demosoc/HAL_Drivers/drv_uart.c b/bsp/nuclei/libraries/demosoc/HAL_Drivers/drv_uart.c index 3d1c0e8454d..6337912468a 100644 --- a/bsp/nuclei/libraries/demosoc/HAL_Drivers/drv_uart.c +++ b/bsp/nuclei/libraries/demosoc/HAL_Drivers/drv_uart.c @@ -14,7 +14,7 @@ #if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) #error "Please define at least one BSP_USING_UARTx" - /* this driver can be enabled at menuconfig -> + /* this driver can be enabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable UART */ #endif diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c index 8db58f58c55..67a242fe7f3 100644 --- a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c @@ -174,9 +174,9 @@ static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) gpio_bit_write(index->gpio, index->pin, (bit_status)value); } -static rt_int8_t gd32_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t gd32_pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value; + rt_ssize_t value; const struct pin_index *index; value = PIN_LOW; @@ -184,7 +184,7 @@ static rt_int8_t gd32_pin_read(rt_device_t dev, rt_base_t pin) index = get_pin(pin); if (index == RT_NULL) { - return value; + return -RT_EINVAL; } value = gpio_input_bit_get(index->gpio, index->pin); diff --git a/bsp/nuvoton/libraries/m031/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/m031/rtt_port/drv_gpio.c index 1e52a459b00..2b234c313a4 100644 --- a/bsp/nuvoton/libraries/m031/rtt_port/drv_gpio.c +++ b/bsp/nuvoton/libraries/m031/rtt_port/drv_gpio.c @@ -31,7 +31,7 @@ static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode); static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value); -static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin); +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin); static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args); static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin); static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled); @@ -173,10 +173,12 @@ static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t va GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)) = value; } -static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin) { if (nu_port_check(pin)) - return PIN_LOW; + { + return -RT_EINVAL; + } return GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)); } diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_gpio.c index b9dce581e14..65c35bc69b4 100644 --- a/bsp/nuvoton/libraries/m2354/rtt_port/drv_gpio.c +++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_gpio.c @@ -31,7 +31,7 @@ static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode); static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value); -static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin); +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin); static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args); static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin); static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled); @@ -172,10 +172,12 @@ static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t va GPIO_PIN_DATA_S(NU_GET_PORT(pin), NU_GET_PINS(pin)) = value; } -static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin) { if (nu_port_check(pin)) - return PIN_LOW; + { + return -RT_EINVAL; + } return GPIO_PIN_DATA_S(NU_GET_PORT(pin), NU_GET_PINS(pin)); } diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_log.h b/bsp/nuvoton/libraries/m2354/rtt_port/drv_log.h index 325b6ab7518..04d7a177f8f 100644 --- a/bsp/nuvoton/libraries/m2354/rtt_port/drv_log.h +++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_log.h @@ -24,4 +24,4 @@ #define DBG_LVL DBG_INFO #endif /* DRV_DEBUG */ -#include \ No newline at end of file +#include diff --git a/bsp/nuvoton/libraries/m460/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/m460/rtt_port/drv_gpio.c index b971f9ba27f..37fed0f8473 100644 --- a/bsp/nuvoton/libraries/m460/rtt_port/drv_gpio.c +++ b/bsp/nuvoton/libraries/m460/rtt_port/drv_gpio.c @@ -31,7 +31,7 @@ static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode); static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value); -static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin); +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin); static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args); static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin); static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled); @@ -172,10 +172,12 @@ static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t va GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)) = value; } -static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin) { if (nu_port_check(pin)) - return PIN_LOW; + { + return -RT_EINVAL; + } return GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)); } diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c index c464e443899..f7c7f2e473c 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c @@ -31,7 +31,7 @@ static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode); static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value); -static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin); +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin); static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args); static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin); static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled); @@ -172,10 +172,12 @@ static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t va GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)) = value; } -static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin) { if (nu_port_check(pin)) - return PIN_LOW; + { + return -RT_EINVAL; + } return GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)); } diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_gpio.c index 9b18ad14876..43bab9bd90c 100644 --- a/bsp/nuvoton/libraries/ma35/rtt_port/drv_gpio.c +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_gpio.c @@ -30,7 +30,7 @@ static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode); static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value); -static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin); +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin); static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args); static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin); static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled); @@ -169,10 +169,12 @@ static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t va GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)) = value; } -static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin) { if (nu_port_check(pin)) - return PIN_LOW; + { + return -RT_EINVAL; + } return GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)); } diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_gpio.c index bef22d284df..f317ea7e288 100644 --- a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_gpio.c +++ b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_gpio.c @@ -39,7 +39,7 @@ static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode); static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value); -static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin); +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin); static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args); static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin); static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled); @@ -193,12 +193,14 @@ static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t va GPIO_ClrBit(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin))); } -static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin) { GPIO_PORT PORT; if (nu_port_check(pin)) - return PIN_LOW; + { + return -RT_EINVAL; + } PORT = (GPIO_PORT)(GPIOA + (NU_GET_PORT(pin) * PORT_OFFSET)); diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_gpio.c index d78442c36ae..0571823b439 100644 --- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_gpio.c +++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_gpio.c @@ -31,7 +31,7 @@ static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode); static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value); -static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin); +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin); static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args); static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin); static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled); @@ -170,10 +170,12 @@ static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_uint8_t va GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)) = value; } -static rt_int8_t nu_gpio_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t nu_gpio_read(struct rt_device *device, rt_base_t pin) { if (nu_port_check(pin)) - return PIN_LOW; + { + return -RT_EINVAL; + } return GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)); } diff --git a/bsp/nxp/imx/imx6ull-smart/.config b/bsp/nxp/imx/imx6ull-smart/.config index c22f23aec9a..e058baab514 100644 --- a/bsp/nxp/imx/imx6ull-smart/.config +++ b/bsp/nxp/imx/imx6ull-smart/.config @@ -162,6 +162,7 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DFS_ROMFS=y # CONFIG_RT_USING_DFS_ROMFS_USER_ROOT is not set +CONFIG_RT_USING_DFS_PTYFS=y # CONFIG_RT_USING_DFS_CROMFS is not set CONFIG_RT_USING_DFS_TMPFS=y # CONFIG_RT_USING_DFS_MQUEUE is not set @@ -192,8 +193,6 @@ CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 -CONFIG_RT_USING_TTY=y -# CONFIG_RT_TTY_DEBUG is not set # CONFIG_RT_USING_CAN is not set CONFIG_RT_USING_CPUTIME=y CONFIG_CPUTIME_TIMER_FREQ=0 @@ -238,7 +237,34 @@ CONFIG_RT_USING_LCD=y # CONFIG_RT_USING_PULSE_ENCODER is not set # CONFIG_RT_USING_INPUT_CAPTURE is not set CONFIG_RT_USING_DEV_BUS=y -# CONFIG_RT_USING_WIFI is not set +CONFIG_RT_USING_WIFI=y +CONFIG_RT_WLAN_DEVICE_STA_NAME="wlan0" +CONFIG_RT_WLAN_DEVICE_AP_NAME="wlan1" +CONFIG_RT_WLAN_SSID_MAX_LENGTH=32 +CONFIG_RT_WLAN_PASSWORD_MAX_LENGTH=32 +CONFIG_RT_WLAN_DEV_EVENT_NUM=2 +CONFIG_RT_WLAN_MANAGE_ENABLE=y +CONFIG_RT_WLAN_SCAN_WAIT_MS=10000 +CONFIG_RT_WLAN_CONNECT_WAIT_MS=10000 +CONFIG_RT_WLAN_SCAN_SORT=y +CONFIG_RT_WLAN_MSH_CMD_ENABLE=y +CONFIG_RT_WLAN_JOIN_SCAN_BY_MGNT=y +CONFIG_RT_WLAN_AUTO_CONNECT_ENABLE=y +CONFIG_AUTO_CONNECTION_PERIOD_MS=2000 +CONFIG_RT_WLAN_CFG_ENABLE=y +CONFIG_RT_WLAN_CFG_INFO_MAX=3 +CONFIG_RT_WLAN_PROT_ENABLE=y +CONFIG_RT_WLAN_PROT_NAME_LEN=8 +CONFIG_RT_WLAN_PROT_MAX=2 +CONFIG_RT_WLAN_DEFAULT_PROT="lwip" +CONFIG_RT_WLAN_PROT_LWIP_ENABLE=y +CONFIG_RT_WLAN_PROT_LWIP_NAME="lwip" +# CONFIG_RT_WLAN_PROT_LWIP_PBUF_FORCE is not set +CONFIG_RT_WLAN_WORK_THREAD_ENABLE=y +CONFIG_RT_WLAN_WORKQUEUE_THREAD_NAME="wlan" +CONFIG_RT_WLAN_WORKQUEUE_THREAD_SIZE=2048 +CONFIG_RT_WLAN_WORKQUEUE_THREAD_PRIO=15 +# CONFIG_RT_WLAN_DEBUG is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y @@ -377,7 +403,7 @@ CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=8192 # CONFIG_LWIP_NO_RX_THREAD is not set -# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_LWIP_NO_TX_THREAD=y CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=8192 CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 @@ -454,10 +480,11 @@ CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 CONFIG_LWP_TID_MAX_NR=64 CONFIG_LWP_ENABLE_ASID=y CONFIG_RT_LWP_SHM_MAX_NR=64 -# CONFIG_LWP_UNIX98_PTY is not set CONFIG_RT_USING_LDSO=y # CONFIG_ELF_DEBUG_ENABLE is not set # CONFIG_ELF_LOAD_RANDOMIZE is not set +CONFIG_LWP_USING_TERMINAL=y +CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # Memory management @@ -503,7 +530,19 @@ CONFIG_RT_USING_LDSO=y # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set +CONFIG_PKG_USING_RW007=y +CONFIG_PKG_RW007_PATH="/packages/iot/WiFi/rw007" +# CONFIG_PKG_USING_RW007_V210 is not set +# CONFIG_PKG_USING_RW007_V201 is not set +# CONFIG_PKG_USING_RW007_V200 is not set +# CONFIG_PKG_USING_RW007_V111 is not set +# CONFIG_PKG_USING_RW007_V110 is not set +# CONFIG_PKG_USING_RW007_V100 is not set +CONFIG_PKG_USING_RW007_LATEST_VERSION=y +CONFIG_PKG_RW007_VER="latest" +CONFIG_RW007_NOT_USE_EXAMPLE_DRIVERS=y +# CONFIG_RW007_USING_STM32_DRIVERS is not set +CONFIG_RW007_SPI_MAX_HZ=30000000 # # CYW43012 WiFi @@ -1307,10 +1346,10 @@ CONFIG_BSP_USING_UART1=y # Select SPI Driver # CONFIG_BSP_USING_SPI=y -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_USING_SPI2 is not set -# CONFIG_BSP_USING_SPI3 is not set -# CONFIG_BSP_USING_SPI4 is not set +CONFIG_BSP_USING_SPI1=y +CONFIG_BSP_USING_SPI2=y +CONFIG_BSP_USING_SPI3=y +CONFIG_BSP_USING_SPI4=y # # Select I2C Driver @@ -1371,12 +1410,14 @@ CONFIG_RT_USING_WDT2=y # Select ENET Driver # CONFIG_RT_USING_ENET1=y -# CONFIG_RT_USING_ENET2 is not set +CONFIG_RT_USING_ENET2=y # # Select Wifi Driver # -# CONFIG_RT_USING_WIFI_RW007 is not set +CONFIG_RT_USING_WIFI_RW007=y +CONFIG_RW007_DAFAULT_SSID="rt-thread" +CONFIG_RW007_DAFAULT_PASSWARD="12345678" # # Select USB Driver diff --git a/bsp/nxp/imx/imx6ull-smart/README.md b/bsp/nxp/imx/imx6ull-smart/README.md index 4ddd6e4adfe..29cfc832259 100644 --- a/bsp/nxp/imx/imx6ull-smart/README.md +++ b/bsp/nxp/imx/imx6ull-smart/README.md @@ -1,32 +1,70 @@ # RT-Thread Smart for i.MX6ULL -这是一份ART-pi smart开发板的BSP，支持smart模式也支持传统的RTOS模式； +这是一份ART-pi smart开发板的BSP，支持smart模式 ART-pi smart采用了米尔科技的imx6ull核心板，硬件由韦东山团队完成，由社区来完成整体的BSP。硬件规格情况如下： ![硬件资源](figures/hw_resources.png) -## 如何编译 +> ## 当前支持情况 +> ### 内核 +> * [ ] rt-thread +> * [x] rt-smart +> +> ### 驱动 +> * [x] uart +> * [x] SPI +> * [x] GPIO +> * [x] sdcard +> * [x] RW007 +> * [x] enet +> * [ ] usb +> * [x] emmc +> +> ### 组件 +> * [x] fat文件系统 +> * [x] LWIP网络协议栈 +> * [x] wlan +> +> ### 应用 +> * [x] xmake 构建环境 +> * [x] busybox +> * [x] smart-apps +> +> ### 待完善、修复 +> * [ ] ash 支持ash开机自启动 +> * [ ] 网络 以太网网络问题修复 +> * [ ] emmc 从emmc启动内核、挂载文件系统 + +## 应用编译 -如果使用smart的模式，请使用smart sdk环境，然后进入到这个bsp目录，执行 +参考https://github.com/RT-Thread/userapps.git的README.md搭建xmake编译环境并编译smart应用 + +生成的应用在userapps/apps/build/rootfs文件夹中，将它们拷贝到sd卡中 + +## 内核编译 + +* 注意：请使用xmake下载下来的工具链，工具链具体位置在 ```bash -scons +~/.xmake/packages/a/arm-smart-musleabi/211536-3de435f234/f5d0c3febbd2497fa950eb569871a3c0 ``` -进行编译； +* 更新在线wifi软件包 +```bash + source ~/.env/env.sh + pkgs --update + ``` -如果使用RTOS模式，请确保在menuconfig中不选择smart模式，然后执行 +* 进入到rt-thread/bsp/nxp/imx/imx6ull-smart目录，执行 ```bash -scons +scons -j12 ``` -进行编译。 - -## 如何运行 +## 启动内核 -* 从eMMC中加载运行 +* 从eMMC中加载运行(目前不推荐) ```bash bootcmd=fatload mmc 1:1 0x80001000 /kernel/rtthread.bin; dcache flush; go 0x80001000 @@ -39,3 +77,9 @@ tftp 0x80001000 rtthread.bin dcache flush go 0x80001000 ``` + +* 从sd卡启动 (目前推荐) + +```bash +fatload mmc 0:1 0x80001000 rtthread.bin; dcache flush; go 0x80001000 +``` diff --git a/bsp/nxp/imx/imx6ull-smart/applications/init_wifi.c b/bsp/nxp/imx/imx6ull-smart/applications/init_wifi.c index 680f6b0cb52..dcef9b379c9 100644 --- a/bsp/nxp/imx/imx6ull-smart/applications/init_wifi.c +++ b/bsp/nxp/imx/imx6ull-smart/applications/init_wifi.c @@ -28,7 +28,7 @@ int rw007_wifi_init(void) rt_kprintf("%s wi-fi configuration file not exist in sd card!\n", WIFI_SH_PATH); } - return 0 + return 0; } INIT_APP_EXPORT(rw007_wifi_init); #endif diff --git a/bsp/nxp/imx/imx6ull-smart/applications/mnt.c b/bsp/nxp/imx/imx6ull-smart/applications/mnt.c index 65879480c5a..7ff39c4a03f 100644 --- a/bsp/nxp/imx/imx6ull-smart/applications/mnt.c +++ b/bsp/nxp/imx/imx6ull-smart/applications/mnt.c @@ -20,20 +20,10 @@ int mnt_init(void) rt_thread_mdelay(500); int part_id = 0; - if (dfs_mount("emmc0", "/", "elm", 0, (void *)part_id) != 0) - { - rt_kprintf("Dir / emmc mount failed!\n"); - return -1; - } - else - { - rt_kprintf("emmc file system initialization done!\n"); - } - part_id = 0; - if (dfs_mount("sd0", "/mnt/sd0", "elm", 0, (void *)part_id) != 0) + if (dfs_mount("sd0", "/", "elm", 0, (void *)part_id) != 0) { - rt_kprintf("Dir /mnt/sd0 mount failed!\n"); + rt_kprintf("Dir / mount failed!\n"); return -1; } else diff --git a/bsp/nxp/imx/imx6ull-smart/drivers/board.c b/bsp/nxp/imx/imx6ull-smart/drivers/board.c index 8a77d5be096..d95362c5913 100644 --- a/bsp/nxp/imx/imx6ull-smart/drivers/board.c +++ b/bsp/nxp/imx/imx6ull-smart/drivers/board.c @@ -104,14 +104,19 @@ void assert_handler(const char *ex_string, const char *func, rt_size_t line) void rt_hw_board_init(void) { #ifdef RT_USING_SMART + rt_uint32_t mmutable_p = 0; rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xf0000000, 0x10000000, MMUTable, PV_OFFSET); - + rt_hw_init_mmu_table(platform_mem_desc, platform_mem_desc_size); + mmutable_p = (rt_uint32_t)MMUTable + (rt_uint32_t)PV_OFFSET ; + rt_hw_mmu_switch((void*)mmutable_p); rt_page_init(init_page_region); rt_hw_mmu_ioremap_init(&rt_kernel_space, (void*)0xf0000000, 0x10000000); arch_kuser_init(&rt_kernel_space, (void*)0xffff0000); #else rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x80000000, 0x10000000, MMUTable, 0); + rt_hw_init_mmu_table(platform_mem_desc,platform_mem_desc_size); + rt_hw_mmu_init(); rt_hw_mmu_ioremap_init(&rt_kernel_space, (void*)0x80000000, 0x10000000); #endif diff --git a/bsp/nxp/imx/imx6ull-smart/drivers/drv_pin.c b/bsp/nxp/imx/imx6ull-smart/drivers/drv_pin.c index 31499de14c7..986ee31dad8 100644 --- a/bsp/nxp/imx/imx6ull-smart/drivers/drv_pin.c +++ b/bsp/nxp/imx/imx6ull-smart/drivers/drv_pin.c @@ -279,9 +279,9 @@ static void imx6ull_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_ GPIO_WritePinOutput(mask_tab[port].gpio, pin_num, value); } -static rt_int8_t imx6ull_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t imx6ull_pin_read(struct rt_device *device, rt_base_t pin) { - rt_int8_t value = 0; + rt_ssize_t value = 0; rt_int8_t port = 0, pin_num = 0; value = PIN_LOW; diff --git a/bsp/nxp/imx/imx6ull-smart/drivers/drv_sdio.c b/bsp/nxp/imx/imx6ull-smart/drivers/drv_sdio.c index d5c483759d4..8ece4418c51 100644 --- a/bsp/nxp/imx/imx6ull-smart/drivers/drv_sdio.c +++ b/bsp/nxp/imx/imx6ull-smart/drivers/drv_sdio.c @@ -52,7 +52,7 @@ /* Endian mode. */ #define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle -uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS]; +static uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS]; struct rt_mmcsd_host *host1; struct rt_mmcsd_host *host2; static rt_mutex_t mmcsd_mutex = RT_NULL; diff --git a/bsp/nxp/imx/imx6ull-smart/drivers/drv_touch.c b/bsp/nxp/imx/imx6ull-smart/drivers/drv_touch.c index cb23b129835..1869fbfa907 100644 --- a/bsp/nxp/imx/imx6ull-smart/drivers/drv_touch.c +++ b/bsp/nxp/imx/imx6ull-smart/drivers/drv_touch.c @@ -293,9 +293,9 @@ static rt_size_t gt911_read_point(struct rt_touch_device *touch, void *buf, rt_s off_set = read_index * 8; read_id = read_buf[off_set] & 0x0f; pre_id[read_index] = read_id; - input_x = read_buf[off_set + 1] | (read_buf[off_set + 2] << 8); /* x */ - input_y = read_buf[off_set + 3] | (read_buf[off_set + 4] << 8); /* y */ - input_w = read_buf[off_set + 5] | (read_buf[off_set + 6] << 8); /* size */ + input_x = read_buf[off_set + 1] | (read_buf[off_set + 2] << 8); /* x */ + input_y = read_buf[off_set + 3] | (read_buf[off_set + 4] << 8); /* y */ + input_w = read_buf[off_set + 5] | (read_buf[off_set + 6] << 8); /* size */ gt911_touch_down(buf, read_id, input_x, input_y, input_w); } diff --git a/bsp/nxp/imx/imx6ull-smart/rtconfig.h b/bsp/nxp/imx/imx6ull-smart/rtconfig.h index 9ca3db02b4d..ad4ba014edf 100644 --- a/bsp/nxp/imx/imx6ull-smart/rtconfig.h +++ b/bsp/nxp/imx/imx6ull-smart/rtconfig.h @@ -116,6 +116,7 @@ #define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS #define RT_USING_DFS_ROMFS +#define RT_USING_DFS_PTYFS #define RT_USING_DFS_TMPFS #define RT_USING_PAGECACHE @@ -138,7 +139,6 @@ #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_TTY #define RT_USING_CPUTIME #define CPUTIME_TIMER_FREQ 0 #define RT_USING_I2C @@ -159,6 +159,32 @@ #define RT_TOUCH_PIN_IRQ #define RT_USING_LCD #define RT_USING_DEV_BUS +#define RT_USING_WIFI +#define RT_WLAN_DEVICE_STA_NAME "wlan0" +#define RT_WLAN_DEVICE_AP_NAME "wlan1" +#define RT_WLAN_SSID_MAX_LENGTH 32 +#define RT_WLAN_PASSWORD_MAX_LENGTH 32 +#define RT_WLAN_DEV_EVENT_NUM 2 +#define RT_WLAN_MANAGE_ENABLE +#define RT_WLAN_SCAN_WAIT_MS 10000 +#define RT_WLAN_CONNECT_WAIT_MS 10000 +#define RT_WLAN_SCAN_SORT +#define RT_WLAN_MSH_CMD_ENABLE +#define RT_WLAN_JOIN_SCAN_BY_MGNT +#define RT_WLAN_AUTO_CONNECT_ENABLE +#define AUTO_CONNECTION_PERIOD_MS 2000 +#define RT_WLAN_CFG_ENABLE +#define RT_WLAN_CFG_INFO_MAX 3 +#define RT_WLAN_PROT_ENABLE +#define RT_WLAN_PROT_NAME_LEN 8 +#define RT_WLAN_PROT_MAX 2 +#define RT_WLAN_DEFAULT_PROT "lwip" +#define RT_WLAN_PROT_LWIP_ENABLE +#define RT_WLAN_PROT_LWIP_NAME "lwip" +#define RT_WLAN_WORK_THREAD_ENABLE +#define RT_WLAN_WORKQUEUE_THREAD_NAME "wlan" +#define RT_WLAN_WORKQUEUE_THREAD_SIZE 2048 +#define RT_WLAN_WORKQUEUE_THREAD_PRIO 15 #define RT_USING_PIN #define RT_USING_KTIME @@ -249,6 +275,7 @@ #define RT_LWIP_TCPTHREAD_PRIORITY 10 #define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 #define RT_LWIP_TCPTHREAD_STACKSIZE 8192 +#define LWIP_NO_TX_THREAD #define RT_LWIP_ETHTHREAD_PRIORITY 12 #define RT_LWIP_ETHTHREAD_STACKSIZE 8192 #define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 @@ -297,6 +324,8 @@ #define LWP_ENABLE_ASID #define RT_LWP_SHM_MAX_NR 64 #define RT_USING_LDSO +#define LWP_USING_TERMINAL +#define LWP_PTY_MAX_PARIS_LIMIT 64 /* Memory management */ @@ -316,6 +345,10 @@ /* Wiced WiFi */ +#define PKG_USING_RW007 +#define PKG_USING_RW007_LATEST_VERSION +#define RW007_NOT_USE_EXAMPLE_DRIVERS +#define RW007_SPI_MAX_HZ 30000000 /* CYW43012 WiFi */ @@ -445,6 +478,10 @@ /* Select SPI Driver */ #define BSP_USING_SPI +#define BSP_USING_SPI1 +#define BSP_USING_SPI2 +#define BSP_USING_SPI3 +#define BSP_USING_SPI4 /* Select I2C Driver */ @@ -490,9 +527,13 @@ /* Select ENET Driver */ #define RT_USING_ENET1 +#define RT_USING_ENET2 /* Select Wifi Driver */ +#define RT_USING_WIFI_RW007 +#define RW007_DAFAULT_SSID "rt-thread" +#define RW007_DAFAULT_PASSWARD "12345678" /* Select USB Driver */ diff --git a/bsp/nxp/imx/imx6ull-smart/rtconfig.py b/bsp/nxp/imx/imx6ull-smart/rtconfig.py index ce6c3d61a09..42f84839715 100644 --- a/bsp/nxp/imx/imx6ull-smart/rtconfig.py +++ b/bsp/nxp/imx/imx6ull-smart/rtconfig.py @@ -5,12 +5,13 @@ CPU ='cortex-a' CROSS_TOOL = 'gcc' PLATFORM = 'gcc' -EXEC_PATH = os.getenv('RTT_EXEC_PATH') or '/usr/bin' +EXEC_PATH = os.getenv('RTT_EXEC_PATH') or r'/usr/bin' BUILD = 'debug' +LINK_SCRIPT = 'link.lds' + if PLATFORM == 'gcc': - # toolchains - PREFIX = os.getenv('RTT_CC_PREFIX') or 'arm-linux-musleabi-' + PREFIX = os.getenv('RTT_CC_PREFIX') or 'arm-none-eabi-' CC = PREFIX + 'gcc' CXX = PREFIX + 'g++' AS = PREFIX + 'gcc' @@ -22,26 +23,30 @@ OBJCPY = PREFIX + 'objcopy' STRIP = PREFIX + 'strip' CFPFLAGS = ' -msoft-float' - AFPFLAGS = ' -mfloat-abi=softfp -mfpu=vfpv3-d16' - DEVICE = ' -march=armv7-a -mtune=cortex-a7 -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing -fcommon' + AFPFLAGS = ' -mfloat-abi=softfp -mfpu=neon' + DEVICE = ' -march=armv7-a -mtune=cortex-a7 -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing' - CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall' - CFLAGS = DEVICE + CFPFLAGS + ' -Wall -std=gnu99' - AFLAGS = DEVICE + ' -c' + AFPFLAGS + ' -x assembler-with-cpp -D__ASSEMBLY__' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + ' -lgcc' + CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall -fdiagnostics-color=always' + CFLAGS = DEVICE + CFPFLAGS + ' -Wall -Wno-cpp -std=gnu99 -D_POSIX_SOURCE -fdiagnostics-color=always' + AFLAGS = DEVICE + ' -c' + AFPFLAGS + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T '+ LINK_SCRIPT + ' -lsupc++ -lgcc -static' CPATH = '' LPATH = '' if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2' + ' -Wno-unused-function' + CFLAGS += ' -O0 -gdwarf-2' CXXFLAGS += ' -O0 -gdwarf-2' AFLAGS += ' -gdwarf-2' else: CFLAGS += ' -Os' CXXFLAGS += ' -Os' - CXXFLAGS += ' -Woverloaded-virtual -fno-exceptions -fno-rtti' - MKIMAGE = '-t imximage -b rtthread.bin -o rtthread.imx -g rtthread.img -a 0x80001000' + CXXFLAGS += ' -Woverloaded-virtual -fno-rtti' + + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -nostdlib -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' -DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' -POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +\ - 'python3 mkimage.py ' + MKIMAGE + '\n' + DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/nxp/imx/imxrt/imxrt1021-nxp-evk/project.ewp b/bsp/nxp/imx/imxrt/imxrt1021-nxp-evk/project.ewp index fc7840ef6a5..be846fda902 100644 --- a/bsp/nxp/imx/imxrt/imxrt1021-nxp-evk/project.ewp +++ b/bsp/nxp/imx/imxrt/imxrt1021-nxp-evk/project.ewp @@ -229,7 +229,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT CPU_MIMXRT1021DAG5A ENDIANNESS STD=C99 @@ -1150,6 +1149,9 @@ $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\dataqueue.c @@ -1379,25 +1381,25 @@ rt_usbd - $PROJ_DIR$\..\..\..\..\..\components\drivers\usb\usbdevice\class\cdc_vcom.c + $PROJ_DIR$\..\..\..\..\..\components\drivers\usb\usbdevice\core\usbdevice_core.c - $PROJ_DIR$\..\..\..\..\..\components\drivers\usb\usbdevice\class\mstorage.c + $PROJ_DIR$\..\..\..\..\..\components\drivers\usb\usbdevice\core\usbdevice.c - $PROJ_DIR$\..\..\..\..\..\components\drivers\usb\usbdevice\core\usbdevice_core.c + $PROJ_DIR$\..\..\..\..\..\components\drivers\usb\usbdevice\class\cdc_vcom.c - $PROJ_DIR$\..\..\..\..\..\components\drivers\usb\usbdevice\core\usbdevice.c + $PROJ_DIR$\..\..\..\..\..\components\drivers\usb\usbdevice\class\mstorage.c xip - $PROJ_DIR$\xip\fsl_flexspi_nor_boot.c + $PROJ_DIR$\xip\fsl_flexspi_nor_flash.c - $PROJ_DIR$\xip\fsl_flexspi_nor_flash.c + $PROJ_DIR$\xip\fsl_flexspi_nor_boot.c diff --git a/bsp/nxp/imx/imxrt/imxrt1021-nxp-evk/project.uvprojx b/bsp/nxp/imx/imxrt/imxrt1021-nxp-evk/project.uvprojx index edb0b2e33c6..018806c2ccb 100644 --- a/bsp/nxp/imx/imxrt/imxrt1021-nxp-evk/project.uvprojx +++ b/bsp/nxp/imx/imxrt/imxrt1021-nxp-evk/project.uvprojx @@ -543,6 +543,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1462,9 +1481,9 @@ rt_usbd - cdc_vcom.c + mstorage.c 1 - ..\..\..\..\..\components\drivers\usb\usbdevice\class\cdc_vcom.c + ..\..\..\..\..\components\drivers\usb\usbdevice\class\mstorage.c @@ -1476,16 +1495,16 @@ - usbdevice.c + cdc_vcom.c 1 - ..\..\..\..\..\components\drivers\usb\usbdevice\core\usbdevice.c + ..\..\..\..\..\components\drivers\usb\usbdevice\class\cdc_vcom.c - mstorage.c + usbdevice.c 1 - ..\..\..\..\..\components\drivers\usb\usbdevice\class\mstorage.c + ..\..\..\..\..\components\drivers\usb\usbdevice\core\usbdevice.c @@ -1493,16 +1512,16 @@ xip - fsl_flexspi_nor_flash.c + fsl_flexspi_nor_boot.c 1 - xip\fsl_flexspi_nor_flash.c + xip\fsl_flexspi_nor_boot.c - fsl_flexspi_nor_boot.c + fsl_flexspi_nor_flash.c 1 - xip\fsl_flexspi_nor_boot.c + xip\fsl_flexspi_nor_flash.c diff --git a/bsp/nxp/imx/imxrt/imxrt1052-atk-commander/project.uvprojx b/bsp/nxp/imx/imxrt/imxrt1052-atk-commander/project.uvprojx index d27238eca22..0fd6c8dfee7 100644 --- a/bsp/nxp/imx/imxrt/imxrt1052-atk-commander/project.uvprojx +++ b/bsp/nxp/imx/imxrt/imxrt1052-atk-commander/project.uvprojx @@ -490,6 +490,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + --c99 + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/project.ewp b/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/project.ewp index 2371e19bc0d..24f9befd2e0 100644 --- a/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/project.ewp +++ b/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/project.ewp @@ -1130,6 +1130,9 @@ $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/project.uvprojx b/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/project.uvprojx index e72c6b2d281..21d821375d9 100644 --- a/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/project.uvprojx +++ b/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/project.uvprojx @@ -483,6 +483,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/imx/imxrt/imxrt1052-nxp-evk/project.ewp b/bsp/nxp/imx/imxrt/imxrt1052-nxp-evk/project.ewp index b53d717ec9e..130d087117e 100644 --- a/bsp/nxp/imx/imxrt/imxrt1052-nxp-evk/project.ewp +++ b/bsp/nxp/imx/imxrt/imxrt1052-nxp-evk/project.ewp @@ -1135,6 +1135,9 @@ $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/nxp/imx/imxrt/imxrt1052-nxp-evk/project.uvprojx b/bsp/nxp/imx/imxrt/imxrt1052-nxp-evk/project.uvprojx index 833f9f49990..8301e7c2569 100644 --- a/bsp/nxp/imx/imxrt/imxrt1052-nxp-evk/project.uvprojx +++ b/bsp/nxp/imx/imxrt/imxrt1052-nxp-evk/project.uvprojx @@ -490,6 +490,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/imx/imxrt/imxrt1052-seeed-ArchMix/project.uvprojx b/bsp/nxp/imx/imxrt/imxrt1052-seeed-ArchMix/project.uvprojx index 490a0687dc1..d00aa6d48da 100644 --- a/bsp/nxp/imx/imxrt/imxrt1052-seeed-ArchMix/project.uvprojx +++ b/bsp/nxp/imx/imxrt/imxrt1052-seeed-ArchMix/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/imx/imxrt/imxrt1060-nxp-evk/project.ewp b/bsp/nxp/imx/imxrt/imxrt1060-nxp-evk/project.ewp index f3f1858bf6b..6e0a21aa3f3 100644 --- a/bsp/nxp/imx/imxrt/imxrt1060-nxp-evk/project.ewp +++ b/bsp/nxp/imx/imxrt/imxrt1060-nxp-evk/project.ewp @@ -1111,10 +1111,10 @@ Applications - $PROJ_DIR$\applications\mnt.c + $PROJ_DIR$\applications\main.c - $PROJ_DIR$\applications\main.c + $PROJ_DIR$\applications\mnt.c @@ -1182,6 +1182,9 @@ $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\dataqueue.c @@ -1360,10 +1363,10 @@ xip - $PROJ_DIR$\xip\fsl_flexspi_nor_boot.c + $PROJ_DIR$\xip\evkmimxrt1060_flexspi_nor_config.c - $PROJ_DIR$\xip\evkmimxrt1060_flexspi_nor_config.c + $PROJ_DIR$\xip\fsl_flexspi_nor_boot.c diff --git a/bsp/nxp/imx/imxrt/imxrt1060-nxp-evk/project.uvprojx b/bsp/nxp/imx/imxrt/imxrt1060-nxp-evk/project.uvprojx index efab25ccae5..71ed8e1c96d 100644 --- a/bsp/nxp/imx/imxrt/imxrt1060-nxp-evk/project.uvprojx +++ b/bsp/nxp/imx/imxrt/imxrt1060-nxp-evk/project.uvprojx @@ -550,6 +550,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/imx/imxrt/imxrt1061-forlinx-OK1061-S/project.ewp b/bsp/nxp/imx/imxrt/imxrt1061-forlinx-OK1061-S/project.ewp index 71dc793c3b5..9b0922bde74 100644 --- a/bsp/nxp/imx/imxrt/imxrt1061-forlinx-OK1061-S/project.ewp +++ b/bsp/nxp/imx/imxrt/imxrt1061-forlinx-OK1061-S/project.ewp @@ -1165,6 +1165,9 @@ $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/nxp/imx/imxrt/imxrt1061-forlinx-OK1061-S/project.uvprojx b/bsp/nxp/imx/imxrt/imxrt1061-forlinx-OK1061-S/project.uvprojx index c674d323d33..40f44a44c59 100644 --- a/bsp/nxp/imx/imxrt/imxrt1061-forlinx-OK1061-S/project.uvprojx +++ b/bsp/nxp/imx/imxrt/imxrt1061-forlinx-OK1061-S/project.uvprojx @@ -487,6 +487,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/imx/imxrt/imxrt1064-nxp-evk/project.ewp b/bsp/nxp/imx/imxrt/imxrt1064-nxp-evk/project.ewp index 3c3ffbab2d9..6bffffd1b7b 100644 --- a/bsp/nxp/imx/imxrt/imxrt1064-nxp-evk/project.ewp +++ b/bsp/nxp/imx/imxrt/imxrt1064-nxp-evk/project.ewp @@ -1133,6 +1133,9 @@ $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\dataqueue.c @@ -1290,13 +1293,13 @@ xip - $PROJ_DIR$\xip\fsl_flexspi_nor_boot.c + $PROJ_DIR$\xip\evkmimxrt1064_sdram_ini_dcd.c - $PROJ_DIR$\xip\evkmimxrt1064_flexspi_nor_config.c + $PROJ_DIR$\xip\fsl_flexspi_nor_boot.c - $PROJ_DIR$\xip\evkmimxrt1064_sdram_ini_dcd.c + $PROJ_DIR$\xip\evkmimxrt1064_flexspi_nor_config.c diff --git a/bsp/nxp/imx/imxrt/imxrt1064-nxp-evk/project.uvprojx b/bsp/nxp/imx/imxrt/imxrt1064-nxp-evk/project.uvprojx index b8513f42b47..9644522d5c7 100644 --- a/bsp/nxp/imx/imxrt/imxrt1064-nxp-evk/project.uvprojx +++ b/bsp/nxp/imx/imxrt/imxrt1064-nxp-evk/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1102,16 +1121,16 @@ - fsl_flexspi_nor_boot.c + evkmimxrt1064_sdram_ini_dcd.c 1 - xip\fsl_flexspi_nor_boot.c + xip\evkmimxrt1064_sdram_ini_dcd.c - evkmimxrt1064_sdram_ini_dcd.c + fsl_flexspi_nor_boot.c 1 - xip\evkmimxrt1064_sdram_ini_dcd.c + xip\fsl_flexspi_nor_boot.c diff --git a/bsp/nxp/imx/imxrt/imxrt1170-nxp-evk/m7/project.ewp b/bsp/nxp/imx/imxrt/imxrt1170-nxp-evk/m7/project.ewp index 4b7e43d5c39..18ded95c2f3 100644 --- a/bsp/nxp/imx/imxrt/imxrt1170-nxp-evk/m7/project.ewp +++ b/bsp/nxp/imx/imxrt/imxrt1170-nxp-evk/m7/project.ewp @@ -1131,10 +1131,10 @@ Applications - $PROJ_DIR$\applications\main.c + $PROJ_DIR$\applications\mnt.c - $PROJ_DIR$\applications\mnt.c + $PROJ_DIR$\applications\main.c @@ -1193,6 +1193,9 @@ $PROJ_DIR$\..\..\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\..\..\components\drivers\ipc\dataqueue.c @@ -1416,10 +1419,10 @@ xip - $PROJ_DIR$\xip\evkmimxrt1170_flexspi_nor_config.c + $PROJ_DIR$\xip\fsl_flexspi_nor_boot.c - $PROJ_DIR$\xip\fsl_flexspi_nor_boot.c + $PROJ_DIR$\xip\evkmimxrt1170_flexspi_nor_config.c diff --git a/bsp/nxp/imx/imxrt/imxrt1170-nxp-evk/m7/project.uvprojx b/bsp/nxp/imx/imxrt/imxrt1170-nxp-evk/m7/project.uvprojx index a12e6c18921..50775b76980 100644 --- a/bsp/nxp/imx/imxrt/imxrt1170-nxp-evk/m7/project.uvprojx +++ b/bsp/nxp/imx/imxrt/imxrt1170-nxp-evk/m7/project.uvprojx @@ -493,6 +493,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c index 96d1dbb1182..018785b945c 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c @@ -622,9 +622,9 @@ static void imxrt_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) GPIO_PinInit(mask_tab[port].gpio, pin_num, &gpio); } -static rt_int8_t imxrt_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t imxrt_pin_read(rt_device_t dev, rt_base_t pin) { - int value; + rt_ssize_t value; rt_int8_t port, pin_num; value = PIN_LOW; @@ -634,7 +634,7 @@ static rt_int8_t imxrt_pin_read(rt_device_t dev, rt_base_t pin) if (PIN_INVALID_CHECK(port, pin_num)) { LOG_D("invalid pin,rtt pin: %d,port: %d,pin: %d \n", pin,port + 1,pin_num); - return value; + return -RT_EINVAL; } return GPIO_PinReadPadStatus(mask_tab[port].gpio, pin_num); diff --git a/bsp/nxp/lpc/lpc176x/project.ewp b/bsp/nxp/lpc/lpc176x/project.ewp index 19904095215..00fc7838ba6 100644 --- a/bsp/nxp/lpc/lpc176x/project.ewp +++ b/bsp/nxp/lpc/lpc176x/project.ewp @@ -160,7 +160,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT __RTTHREAD__ __RT_IPC_SOURCE__ __RT_KERNEL_SOURCE__ @@ -1060,7 +1059,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT __RTTHREAD__ __RT_IPC_SOURCE__ __RT_KERNEL_SOURCE__ @@ -1877,6 +1875,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c @@ -1905,22 +1906,22 @@ Drivers - $PROJ_DIR$\drivers\board.c + $PROJ_DIR$\drivers\sd.c - $PROJ_DIR$\drivers\sd.c + $PROJ_DIR$\drivers\led.c $PROJ_DIR$\drivers\spi.c - $PROJ_DIR$\drivers\emac.c + $PROJ_DIR$\drivers\board.c - $PROJ_DIR$\drivers\uart.c + $PROJ_DIR$\drivers\emac.c - $PROJ_DIR$\drivers\led.c + $PROJ_DIR$\drivers\uart.c diff --git a/bsp/nxp/lpc/lpc176x/project.uvproj b/bsp/nxp/lpc/lpc176x/project.uvproj index d15dd8d64ce..845e0b47414 100644 --- a/bsp/nxp/lpc/lpc176x/project.uvproj +++ b/bsp/nxp/lpc/lpc176x/project.uvproj @@ -396,23 +396,23 @@ Applications - platform.c + application.c 1 - applications\platform.c + applications\application.c - startup.c + platform.c 1 - applications\startup.c + applications\platform.c - application.c + startup.c 1 - applications\application.c + applications\startup.c @@ -532,6 +532,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -689,44 +708,44 @@ Drivers - emac.c + board.c 1 - drivers\emac.c + drivers\board.c - spi.c + led.c 1 - drivers\spi.c + drivers\led.c - sd.c + uart.c 1 - drivers\sd.c + drivers\uart.c - led.c + spi.c 1 - drivers\led.c + drivers\spi.c - board.c + sd.c 1 - drivers\board.c + drivers\sd.c - uart.c + emac.c 1 - drivers\uart.c + drivers\emac.c diff --git a/bsp/nxp/lpc/lpc178x/project.uvproj b/bsp/nxp/lpc/lpc178x/project.uvproj index 19d2ca0dbb7..a2b85fc0897 100644 --- a/bsp/nxp/lpc/lpc178x/project.uvproj +++ b/bsp/nxp/lpc/lpc178x/project.uvproj @@ -384,16 +384,16 @@ Applications - application.c + startup.c 1 - applications\application.c + applications\startup.c - startup.c + application.c 1 - applications\startup.c + applications\application.c @@ -520,6 +520,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -677,65 +696,65 @@ Drivers - lpc177x_8x_emc.c + uart.c 1 - drivers\lpc177x_8x_emc.c + drivers\uart.c - uart.c + lpc177x_8x_emc.c 1 - drivers\uart.c + drivers\lpc177x_8x_emc.c - lpc177x_8x_pinsel.c + sdram.c 1 - drivers\lpc177x_8x_pinsel.c + drivers\sdram.c - lpc177x_8x_uart.c + lpc17xx_lcd.c 1 - drivers\lpc177x_8x_uart.c + drivers\lpc17xx_lcd.c - board.c + lpc177x_8x_uart.c 1 - drivers\board.c + drivers\lpc177x_8x_uart.c - lpc17xx_lcd.c + drv_glcd.c 1 - drivers\lpc17xx_lcd.c + drivers\drv_glcd.c - sdram.c + lpc177x_8x_clkpwr.c 1 - drivers\sdram.c + drivers\lpc177x_8x_clkpwr.c - drv_glcd.c + board.c 1 - drivers\drv_glcd.c + drivers\board.c - lpc177x_8x_clkpwr.c + lpc177x_8x_pinsel.c 1 - drivers\lpc177x_8x_clkpwr.c + drivers\lpc177x_8x_pinsel.c diff --git a/bsp/nxp/lpc/lpc2148/project.Uv2 b/bsp/nxp/lpc/lpc2148/project.Uv2 index dc459198102..bad3933db9a 100644 --- a/bsp/nxp/lpc/lpc2148/project.Uv2 +++ b/bsp/nxp/lpc/lpc2148/project.Uv2 @@ -12,8 +12,8 @@ Group (Kernel) Group (libcpu) Group (POSIX) -File 1,1, File 1,1, +File 1,1, File 2,1,<..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c> File 2,1,<..\..\..\..\components\libc\compilers\armlibc\syscalls.c> File 2,1,<..\..\..\..\components\libc\compilers\common\cctype.c> @@ -24,6 +24,7 @@ File 2,1,<..\..\..\..\components\libc\compilers\common\cunistd.c> File 2,1,<..\..\..\..\components\libc\compilers\common\cwchar.c> File 3,1,<..\..\..\..\components\drivers\core\device.c> File 3,1,<..\..\..\..\components\drivers\ipc\completion.c> +File 3,1,<..\..\..\..\components\drivers\ipc\condvar.c> File 3,1,<..\..\..\..\components\drivers\ipc\dataqueue.c> File 3,1,<..\..\..\..\components\drivers\ipc\pipe.c> File 3,1,<..\..\..\..\components\drivers\ipc\ringblk_buf.c> diff --git a/bsp/nxp/lpc/lpc2478/project.uvproj b/bsp/nxp/lpc/lpc2478/project.uvproj index 4c3c56d03b2..fa5de9df8b7 100644 --- a/bsp/nxp/lpc/lpc2478/project.uvproj +++ b/bsp/nxp/lpc/lpc2478/project.uvproj @@ -396,16 +396,16 @@ Applications - startup.c + application.c 1 - applications\startup.c + applications\application.c - application.c + startup.c 1 - applications\application.c + applications\startup.c @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/lpc/lpc408x/project.uvproj b/bsp/nxp/lpc/lpc408x/project.uvproj index ab66c409a25..4b7a46cc029 100644 --- a/bsp/nxp/lpc/lpc408x/project.uvproj +++ b/bsp/nxp/lpc/lpc408x/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1067,23 +1086,23 @@ ktime - hrtimer.c + boottime.c 1 - ..\..\..\..\components\drivers\ktime\src\hrtimer.c + ..\..\..\..\components\drivers\ktime\src\boottime.c - boottime.c + cputimer.c 1 - ..\..\..\..\components\drivers\ktime\src\boottime.c + ..\..\..\..\components\drivers\ktime\src\cputimer.c - cputimer.c + hrtimer.c 1 - ..\..\..\..\components\drivers\ktime\src\cputimer.c + ..\..\..\..\components\drivers\ktime\src\hrtimer.c diff --git a/bsp/nxp/lpc/lpc408x/project.uvprojx b/bsp/nxp/lpc/lpc408x/project.uvprojx index f3c2dfa9cfb..1ee1e6b2adb 100644 --- a/bsp/nxp/lpc/lpc408x/project.uvprojx +++ b/bsp/nxp/lpc/lpc408x/project.uvprojx @@ -483,6 +483,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1049,16 +1068,16 @@ - boottime.c + hrtimer.c 1 - ..\..\..\..\components\drivers\ktime\src\boottime.c + ..\..\..\..\components\drivers\ktime\src\hrtimer.c - hrtimer.c + boottime.c 1 - ..\..\..\..\components\drivers\ktime\src\hrtimer.c + ..\..\..\..\components\drivers\ktime\src\boottime.c diff --git a/bsp/nxp/lpc/lpc43xx/M0/project.uvproj b/bsp/nxp/lpc/lpc43xx/M0/project.uvproj index fcf2bff1d18..1a442a93b7e 100644 --- a/bsp/nxp/lpc/lpc43xx/M0/project.uvproj +++ b/bsp/nxp/lpc/lpc43xx/M0/project.uvproj @@ -392,30 +392,30 @@ Applications - vbus_drv.c + application.c 1 - applications\vbus_drv.c + applications\application.c - startup.c + board.c 1 - applications\startup.c + applications\board.c - board.c + startup.c 1 - applications\board.c + applications\startup.c - application.c + vbus_drv.c 1 - applications\application.c + applications\vbus_drv.c @@ -535,6 +535,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1066,16 +1085,16 @@ - prio_queue.c + vbus.c 1 - ..\..\..\..\..\components\vbus\prio_queue.c + ..\..\..\..\..\components\vbus\vbus.c - vbus.c + prio_queue.c 1 - ..\..\..\..\..\components\vbus\vbus.c + ..\..\..\..\..\components\vbus\prio_queue.c diff --git a/bsp/nxp/lpc/lpc43xx/M4/project.uvproj b/bsp/nxp/lpc/lpc43xx/M4/project.uvproj index f15579d0823..93ba98a2180 100644 --- a/bsp/nxp/lpc/lpc43xx/M4/project.uvproj +++ b/bsp/nxp/lpc/lpc43xx/M4/project.uvproj @@ -391,30 +391,30 @@ Applications - vbus_drv.c + application.c 1 - applications\vbus_drv.c + applications\application.c - board.c + startup.c 1 - applications\board.c + applications\startup.c - startup.c + vbus_drv.c 1 - applications\startup.c + applications\vbus_drv.c - application.c + board.c 1 - applications\application.c + applications\board.c @@ -534,6 +534,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1051,30 +1070,30 @@ VBus - vbus_chnx.c + vbus.c 1 - ..\..\..\..\..\components\vbus\vbus_chnx.c + ..\..\..\..\..\components\vbus\vbus.c - watermark_queue.c + vbus_chnx.c 1 - ..\..\..\..\..\components\vbus\watermark_queue.c + ..\..\..\..\..\components\vbus\vbus_chnx.c - vbus.c + prio_queue.c 1 - ..\..\..\..\..\components\vbus\vbus.c + ..\..\..\..\..\components\vbus\prio_queue.c - prio_queue.c + watermark_queue.c 1 - ..\..\..\..\..\components\vbus\prio_queue.c + ..\..\..\..\..\components\vbus\watermark_queue.c diff --git a/bsp/nxp/lpc/lpc5410x/project.uvprojx b/bsp/nxp/lpc/lpc5410x/project.uvprojx index 056235934f7..85b353cd584 100644 --- a/bsp/nxp/lpc/lpc5410x/project.uvprojx +++ b/bsp/nxp/lpc/lpc5410x/project.uvprojx @@ -532,6 +532,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/lpc/lpc54114-lite/drivers/drv_gpio.c b/bsp/nxp/lpc/lpc54114-lite/drivers/drv_gpio.c index 3bff6ba4bec..581bf27fd56 100644 --- a/bsp/nxp/lpc/lpc54114-lite/drivers/drv_gpio.c +++ b/bsp/nxp/lpc/lpc54114-lite/drivers/drv_gpio.c @@ -141,18 +141,20 @@ static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) GPIO_PinWrite(GPIO, portx, piny, value); } -static rt_int8_t lpc_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t lpc_pin_read(rt_device_t dev, rt_base_t pin) { int portx, piny; - rt_int8_t value; + rt_ssize_t value; if(pin > PIN_MAX_VAL) - return -RT_ERROR; + { + return -RT_EINVAL; + } portx = get_port(pin); piny = get_pin(pin); - value = (rt_int8_t)(GPIO_PinRead(GPIO, portx, piny)); + value = (rt_ssize_t)(GPIO_PinRead(GPIO, portx, piny)); return value; } diff --git a/bsp/nxp/lpc/lpc54114-lite/project.ewp b/bsp/nxp/lpc/lpc54114-lite/project.ewp index 652f4782ea2..f2d9b8c6cfb 100644 --- a/bsp/nxp/lpc/lpc54114-lite/project.ewp +++ b/bsp/nxp/lpc/lpc54114-lite/project.ewp @@ -229,7 +229,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT __RTTHREAD__ SDK_DEBUGCONSOLE=0 CORE_M4 @@ -1302,7 +1301,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT __RTTHREAD__ SDK_DEBUGCONSOLE=0 CORE_M4 @@ -2220,6 +2218,9 @@ $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/nxp/lpc/lpc54114-lite/project.uvprojx b/bsp/nxp/lpc/lpc54114-lite/project.uvprojx index ffb5a85ac5d..258a5b983a2 100644 --- a/bsp/nxp/lpc/lpc54114-lite/project.uvprojx +++ b/bsp/nxp/lpc/lpc54114-lite/project.uvprojx @@ -549,6 +549,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + --c99 + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/project.uvprojx b/bsp/nxp/lpc/lpc54608-LPCXpresso/project.uvprojx index e091a4f64fa..851232c6a8c 100644 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/project.uvprojx +++ b/bsp/nxp/lpc/lpc54608-LPCXpresso/project.uvprojx @@ -377,23 +377,23 @@ Applications - application.c + mnt.c 1 - applications\application.c + applications\mnt.c - mnt.c + startup.c 1 - applications\mnt.c + applications\startup.c - startup.c + application.c 1 - applications\startup.c + applications\application.c @@ -587,6 +587,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -941,79 +960,79 @@ - fsl_phy.c + board.c 1 - drivers\fsl_phy.c + drivers\board.c - drv_ft5406.c + drv_i2c.c 1 - drivers\drv_ft5406.c + drivers\drv_i2c.c - drv_i2c.c + drt_mpu.c 1 - drivers\drv_i2c.c + drivers\drt_mpu.c - board.c + drv_sdram.c 1 - drivers\board.c + drivers\drv_sdram.c - drv_uart.c + drv_sd.c 1 - drivers\drv_uart.c + drivers\drv_sd.c - drv_sram.c + fsl_phy.c 1 - drivers\drv_sram.c + drivers\fsl_phy.c - drv_sd.c + drv_ft5406.c 1 - drivers\drv_sd.c + drivers\drv_ft5406.c - drv_lcd.c + drv_uart.c 1 - drivers\drv_lcd.c + drivers\drv_uart.c - drv_sdram.c + drv_lcd.c 1 - drivers\drv_sdram.c + drivers\drv_lcd.c - drt_mpu.c + clock_config.c 1 - drivers\drt_mpu.c + drivers\clock_config.c - clock_config.c + drv_sram.c 1 - drivers\clock_config.c + drivers\drv_sram.c diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_pin.c b/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_pin.c index 81f596786ea..a28a7fa1665 100644 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_pin.c +++ b/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_pin.c @@ -201,9 +201,9 @@ static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) GPIO_PinWrite(lpc_pin_map[pin].gpio, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, value); } -static rt_int8_t lpc_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t lpc_pin_read(rt_device_t dev, rt_base_t pin) { - int value; + rt_ssize_t value; if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0)) { return -RT_ERROR; diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_soft_spi.c b/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_soft_spi.c index 9a4d37fbcba..e80385a1a23 100644 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_soft_spi.c +++ b/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_soft_spi.c @@ -25,6 +25,8 @@ static struct lpc_soft_spi_config soft_spi_config[] = #endif }; +static struct lpc_soft_spi spi_obj[sizeof(soft_spi_config) / sizeof(soft_spi_config[0])]; + /** * Attach the spi device to soft SPI bus, this function must be used after initialization. */ @@ -179,9 +181,20 @@ static void lpc_udelay(rt_uint32_t us) } } +static void lpc_pin_init(void) +{ + rt_size_t obj_num = sizeof(spi_obj) / sizeof(struct lpc_soft_spi); + + for(rt_size_t i; i < obj_num; i++) + { + lpc_spi_gpio_init(&spi_obj[i]); + } +} + static struct rt_spi_bit_ops lpc_soft_spi_ops = { .data = RT_NULL, + .pin_init = lpc_pin_init, .tog_sclk = lpc_tog_sclk, .set_sclk = lpc_set_sclk, .set_mosi = lpc_set_mosi, @@ -195,20 +208,17 @@ static struct rt_spi_bit_ops lpc_soft_spi_ops = .delay_us = 1, }; -static struct lpc_soft_spi spi_obj[sizeof(soft_spi_config) / sizeof(soft_spi_config[0])]; - /* Soft SPI initialization function */ int rt_hw_softspi_init(void) { rt_size_t obj_num = sizeof(spi_obj) / sizeof(struct lpc_soft_spi); rt_err_t result; - for (int i = 0; i < obj_num; i++) + for (rt_size_t i = 0; i < obj_num; i++) { lpc_soft_spi_ops.data = (void *)&soft_spi_config[i]; spi_obj[i].spi.ops = &lpc_soft_spi_ops; spi_obj[i].cfg = (void *)&soft_spi_config[i]; - lpc_spi_gpio_init(&spi_obj[i]); result = rt_spi_bit_add_bus(&spi_obj[i].spi, soft_spi_config[i].bus_name, &lpc_soft_spi_ops); RT_ASSERT(result == RT_EOK); } diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/project.uvprojx b/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/project.uvprojx index b05b767880c..41184943933 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/project.uvprojx +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/project.uvprojx b/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/project.uvprojx index 133ba712085..081ebbe6008 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/project.uvprojx +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/project.uvprojx b/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/project.uvprojx index b6d9a537e76..6c972a9bd40 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/project.uvprojx +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/project.uvprojx b/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/project.uvprojx index 8c77a277231..2ab4162c85b 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/project.uvprojx +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/applications/arduino_pinout/SConscript b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/applications/arduino_pinout/SConscript +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/project.ewp b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/project.ewp index 76959324e28..2db167c943f 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/project.ewp +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/project.ewp @@ -1164,6 +1164,9 @@ $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/project.uvprojx b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/project.uvprojx index 12788f2175f..8eddac870bc 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/project.uvprojx +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_pin.c b/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_pin.c index 5ab4e53cc1e..115754fce7d 100644 --- a/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_pin.c +++ b/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_pin.c @@ -96,7 +96,7 @@ static void mcx_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) GPIO_PinWrite(PIN2GPIO(pin), GET_GPIO_PIN(pin), value); } -static rt_int8_t mcx_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t mcx_pin_read(rt_device_t dev, rt_base_t pin) { return GPIO_PinRead(PIN2GPIO(pin), GET_GPIO_PIN(pin)); } diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa153/project.uvprojx b/bsp/nxp/mcx/mcxa/frdm-mcxa153/project.uvprojx index a5b1108738b..be4d1cc58a4 100644 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa153/project.uvprojx +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa153/project.uvprojx @@ -506,6 +506,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/SConscript b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/SConscript index 9b806287b1f..334fdfe016d 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/MCXN947/SConscript +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN947/SConscript @@ -48,14 +48,17 @@ src += ['MCXN947/drivers/fsl_gpio.c'] src += ['MCXN947/drivers/fsl_i3c.c'] src += ['MCXN947/drivers/fsl_irtc.c'] src += ['MCXN947/drivers/fsl_itrc.c'] +src += ['MCXN947/drivers/fsl_lpadc.c'] src += ['MCXN947/drivers/fsl_lpflexcomm.c'] src += ['MCXN947/drivers/fsl_lpi2c.c'] src += ['MCXN947/drivers/fsl_lpi2c_edma.c'] src += ['MCXN947/drivers/fsl_lpspi.c'] +src += ['MCXN947/drivers/fsl_lpspi_edma.c'] src += ['MCXN947/drivers/fsl_lptmr.c'] src += ['MCXN947/drivers/fsl_lpuart.c'] src += ['MCXN947/drivers/fsl_mrt.c'] src += ['MCXN947/drivers/fsl_reset.c'] +src += ['MCXN947/drivers/fsl_spc.c'] src += ['MCXN947/drivers/fsl_vref.c'] src += ['MCXN947/drivers/fsl_usdhc.c'] diff --git a/bsp/nxp/mcx/mcxn/Libraries/drivers/SConscript b/bsp/nxp/mcx/mcxn/Libraries/drivers/SConscript index a83afdec908..de8052d465b 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/drivers/SConscript +++ b/bsp/nxp/mcx/mcxn/Libraries/drivers/SConscript @@ -25,6 +25,9 @@ if GetDepend('BSP_USING_I2C'): if GetDepend('BSP_USING_ADC'): src += ['drv_adc.c'] +if GetDepend('BSP_USING_DAC'): + src += ['drv_dac.c'] + if GetDepend('BSP_USING_HWTIMER'): src += ['drv_hwtimer.c'] @@ -34,6 +37,9 @@ if GetDepend('BSP_USING_WDT'): if GetDepend('BSP_USING_PWM'): src += ['drv_pwm.c'] +if GetDepend('BSP_USING_ETH'): + src += ['drv_eth.c'] + path = [cwd,cwd + '/config'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) diff --git a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_dac.c b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_dac.c new file mode 100644 index 00000000000..410547a1fdf --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_dac.c @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-24 Oxlm first version + */ + +#include +#include +#include "fsl_dac.h" +#include "fsl_dac14.h" + +#ifdef RT_USING_DAC + +// #define DRV_DEBUG +#define DBG_TAG "drv.dac" +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ +#include + +struct mcx_dac { + struct rt_dac_device mcxn_dac_device; + LPDAC_Type *dac_base; + clock_attach_id_t clock_attach_id; + clock_div_name_t clock_div_name; + uint8_t clock_div; + uint8_t referenceVoltageSource; /* kDAC_ReferenceVoltageSourceAlt1, VREFH reference pin */ + uint8_t SOC_CNTRL_BIT; + char *name; +}; + +static struct mcx_dac mcx_dac_obj[] = { +#ifdef BSP_USING_DAC0 + { + .dac_base = DAC0, + .clock_attach_id = kFRO_HF_to_DAC0, + .clock_div_name = kCLOCK_DivDac0Clk, + .clock_div = 1u, + .referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1, + .SOC_CNTRL_BIT = 4, + .name = "dac0", + }, +#endif +#ifdef BSP_USING_DAC1 + { + .dac_base = DAC1, + .clock_attach_id = kFRO_HF_to_DAC1, + .clock_div_name = kCLOCK_DivDac1Clk, + .clock_div = 1u, + .referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1, + .SOC_CNTRL_BIT = 5, + .name = "dac1", + }, +#endif +#ifdef BSP_USING_DAC2 + { + .dac_base = DAC2, + .clock_attach_id = kFRO_HF_to_DAC2, + .clock_div_name = kCLOCK_DivDac2Clk, + .clock_div = 1u, + .referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1, + .SOC_CNTRL_BIT = 6, + .name = "dac2", + }, +#endif + +}; + +rt_err_t mcxn_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel) { + RT_ASSERT(device != RT_NULL); + struct mcx_dac *dac = (struct mcx_dac *)device->parent.user_data; + + if (dac->dac_base == DAC2) { + DAC14_Deinit(dac->dac_base); + } else { + DAC_Deinit(dac->dac_base); + } + return RT_EOK; +} + +rt_err_t mcxn_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel) { + RT_ASSERT(device != RT_NULL); + struct mcx_dac *dac = (struct mcx_dac *)device->parent.user_data; + dac_config_t dacConfigStruct; + dac14_config_t dac14ConfigStruct; + + if (dac->dac_base == DAC2) { + DAC14_GetDefaultConfig(&dac14ConfigStruct); + dac14ConfigStruct.enableOpampBuffer = true; + dac14ConfigStruct.enableDAC = true; + DAC14_Init(dac->dac_base, &dac14ConfigStruct); + } else { + DAC_GetDefaultConfig(&dacConfigStruct); + dacConfigStruct.referenceVoltageSource = dac->referenceVoltageSource; + DAC_Init(dac->dac_base, &dacConfigStruct); + DAC_Enable(dac->dac_base, RT_TRUE); + } + + return RT_EOK; +} + +rt_err_t mcxn_dac_write(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value) { + RT_ASSERT(device != RT_NULL); + struct mcx_dac *dac = (struct mcx_dac *)device->parent.user_data; + + if (dac->dac_base == DAC2) { + if (*value > 0x3FFFU) { + *value = 0x3FFFU; + } + DAC14_SetData(dac->dac_base, *value); + } else { + if (*value > 0xFFFU) { + *value = 0xFFFU; + } + DAC_SetData(dac->dac_base, *value); + } + return RT_EOK; +} + +struct rt_dac_ops mcxn_dac_ops = { + .disabled = mcxn_dac_disabled, + .enabled = mcxn_dac_enabled, + .convert = mcxn_dac_write, +}; + +static int mcxn_dac_init(void) { + int i; + int dac_num = sizeof(mcx_dac_obj) / sizeof(struct mcx_dac); + + for (i = 0; i < dac_num; i++) { + CLOCK_SetClkDiv(mcx_dac_obj[i].clock_div_name, mcx_dac_obj[i].clock_div); + CLOCK_AttachClk(mcx_dac_obj[i].clock_attach_id); + + SPC0->ACTIVE_CFG1 |= 0x01; // Enable VREF + SPC0->ACTIVE_CFG1 |= (0x01 << mcx_dac_obj[i].SOC_CNTRL_BIT); + + if (RT_EOK != rt_hw_dac_register(&mcx_dac_obj[i].mcxn_dac_device, mcx_dac_obj[i].name, &mcxn_dac_ops, + (void *)(mcx_dac_obj + i))) { + LOG_E("%s register failed", mcx_dac_obj[i].name); + return -RT_ERROR; + } + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(mcxn_dac_init); + +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_hwtimer.c b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_hwtimer.c index b3b6dd6fdd7..cd65c534c67 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_hwtimer.c +++ b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_hwtimer.c @@ -180,4 +180,4 @@ void MRT0_IRQHandler(void) INIT_DEVICE_EXPORT(rt_hw_hwtimer_init); -#endif /* BSP_USING_HWTIMER */ \ No newline at end of file +#endif /* BSP_USING_HWTIMER */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_pin.c b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_pin.c index a2ba889672c..2c5517cad00 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_pin.c +++ b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_pin.c @@ -96,7 +96,7 @@ static void mcx_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) GPIO_PinWrite(PIN2GPIO(pin), GET_GPIO_PIN(pin), value); } -static rt_int8_t mcx_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t mcx_pin_read(rt_device_t dev, rt_base_t pin) { return GPIO_PinRead(PIN2GPIO(pin), GET_GPIO_PIN(pin)); } diff --git a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_pwm.c b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_pwm.c index 48aed6962e9..73752a1dfb7 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_pwm.c +++ b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_pwm.c @@ -377,4 +377,4 @@ int mcx_pwm_init(void) INIT_DEVICE_EXPORT(mcx_pwm_init); -#endif /* RT_USING_PWM */ \ No newline at end of file +#endif /* RT_USING_PWM */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.c b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.c index 9752e207955..c29a2caa54f 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.c +++ b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.c @@ -17,9 +17,20 @@ enum { +#ifdef BSP_USING_SPI1 + SPI1_INDEX, +#endif #ifdef BSP_USING_SPI3 SPI3_INDEX, #endif + +#ifdef BSP_USING_SPI6 + SPI6_INDEX, +#endif + +#ifdef BSP_USING_SPI7 + SPI7_INDEX, +#endif }; @@ -47,6 +58,20 @@ struct lpc_spi static struct lpc_spi lpc_obj[] = { +#ifdef BSP_USING_SPI1 + { + .LPSPIx = LPSPI1, + .clock_attach_id = kFRO_HF_DIV_to_FLEXCOMM1, + .clock_div_name = kCLOCK_DivFlexcom1Clk, + .clock_name = kCLOCK_FroHf, + .tx_dma_request = kDmaRequestMuxLpFlexcomm1Tx, + .rx_dma_request = kDmaRequestMuxLpFlexcomm1Rx, + .DMAx = DMA0, + .tx_dma_chl = 0, + .rx_dma_chl = 1, + .name = "spi1", + }, +#endif #ifdef BSP_USING_SPI3 { .LPSPIx = LPSPI3, @@ -60,7 +85,34 @@ static struct lpc_spi lpc_obj[] = .rx_dma_chl = 3, .name = "spi3", }, -#endif +#endif /* BSP_USING_SPI3 */ +#ifdef BSP_USING_SPI6 + { + .LPSPIx = LPSPI6, + .clock_attach_id = kFRO_HF_DIV_to_FLEXCOMM6, + .clock_div_name = kCLOCK_DivFlexcom6Clk, + .clock_name = kCLOCK_FroHf, + .tx_dma_request = kDmaRequestMuxLpFlexcomm6Tx, + .rx_dma_request = kDmaRequestMuxLpFlexcomm6Rx, + .DMAx = DMA0, + .tx_dma_chl = 4, + .rx_dma_chl = 5, + .name = "spi6", +#endif /* BSP_USING_SPI6 */ +#ifdef BSP_USING_SPI7 + { + .LPSPIx = LPSPI7, + .clock_attach_id = kFRO_HF_DIV_to_FLEXCOMM7, + .clock_div_name = kCLOCK_DivFlexcom7Clk, + .clock_name = kCLOCK_FroHf, + .tx_dma_request = kDmaRequestMuxLpFlexcomm7Tx, + .rx_dma_request = kDmaRequestMuxLpFlexcomm7Rx, + .DMAx = DMA0, + .tx_dma_chl = 2, + .rx_dma_chl = 3, + .name = "spi7", + }, +#endif /* BSP_USING_SPI7 */ }; @@ -70,8 +122,6 @@ struct lpc_sw_spi_cs }; - - rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin) { rt_err_t ret = RT_EOK; @@ -89,14 +139,12 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, } - static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) { rt_err_t ret = RT_EOK; // struct lpc_spi *spi = RT_NULL; // spi = (struct lpc_spi *)(device->bus->parent.user_data); // ret = lpc_spi_init(spi->SPIx, cfg); - return ret; } @@ -133,7 +181,7 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m // if(message->length < MAX_DMA_TRANSFER_SIZE) if(0) { - // SPI_MasterTransferBlocking(spi->SPIx, &transfer); + LPSPI_MasterTransferBlocking(spi->LPSPIx, &transfer); } else { diff --git a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.h b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.h new file mode 100644 index 00000000000..cd4aa180bbc --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_spi.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-22 Jisheng Zhang The first version for mcxn + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin); + +#endif /*__DRV_SPI_H__ */ diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/.config b/bsp/nxp/mcx/mcxn/frdm-mcxn947/.config index 338bd6419c7..06553601629 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/.config +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/.config @@ -1117,7 +1117,9 @@ CONFIG_BSP_USING_UART2=y # CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_DAC is not set # CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_WDT is not set # CONFIG_BSP_USING_HWTIMER is not set @@ -1126,3 +1128,4 @@ CONFIG_BSP_USING_UART2=y # # Board extended module Drivers # +# CONFIG_BSP_USING_RW007 is not set diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/applications/main.c b/bsp/nxp/mcx/mcxn/frdm-mcxn947/applications/main.c index 2cecd6c6940..2929981607a 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/applications/main.c +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/applications/main.c @@ -13,9 +13,10 @@ */ #include +#include #include "drv_pin.h" -#define LEDB_PIN ((0*32)+10) +#define LEDB_PIN ((1*32)+2) #define BUTTON_PIN ((0*32)+23) static void sw_pin_cb(void *args); diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/Kconfig b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/Kconfig index 673c8da05f1..c97957a5e2a 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/Kconfig +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/Kconfig @@ -60,10 +60,27 @@ menu "On-chip Peripheral Drivers" default y if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable Flexcomm1 as SPI" + default n + config BSP_USING_SPI3 bool "Enable Flexcomm3 as SPI" default n + config BSP_USING_SPI6 + bool "Enable Flexcomm6 as SPI" + default n + if BSP_USING_SPI6 + config BSP_USING_SPI6_SAMPLE + bool "Enable SPI6 BUS Sample" + default n + endif + + config BSP_USING_SPI7 + bool "Enable Flexcomm7 as SPI" + default n + config BSP_USING_SPI8 bool "Enable Flexcomm8 as High Speed SPI" default y @@ -76,26 +93,54 @@ menu "On-chip Peripheral Drivers" default y if BSP_USING_ADC + config BSP_USING_ADC0 + bool + default n + config BSP_USING_ADC0_CH0 bool "Enable ADC0 Channel0" + select BSP_USING_ADC0 default y config BSP_USING_ADC0_CH1 bool "Enable ADC0 Channel1" + select BSP_USING_ADC0 default n config BSP_USING_ADC0_CH8 bool "Enable ADC0 Channel8" + select BSP_USING_ADC0 default n - config BSP_USING_ADC0_CH13 bool "Enable ADC0 Channel13" + select BSP_USING_ADC0 default n - config BSP_USING_ADC0_CH26 bool "Enable ADC0 Channel26" + select BSP_USING_ADC0 + default n + + endif + + menuconfig BSP_USING_DAC + config BSP_USING_DAC + bool "Enable DAC Channel" + select RT_USING_DAC + default y + + if BSP_USING_DAC + config BSP_USING_DAC0 + bool "Enable DAC0 Channel" + default n + + config BSP_USING_DAC1 + bool "Enable DAC1 Channel" + default n + + config BSP_USING_DAC2 + bool "Enable DAC2 Channel" default n endif @@ -107,6 +152,13 @@ menu "On-chip Peripheral Drivers" select RT_USING_DFS_ELMFAT default y + config BSP_USING_ETH + bool "Enable Ethernet" + default n + select RT_USING_LWIP + select RT_USING_NETDEV + select RT_USING_SAL + config BSP_USING_RTC bool "Enable RTC" select RT_USING_RTC @@ -134,11 +186,36 @@ menu "On-chip Peripheral Drivers" bool "Enable on-board green LED as PWM output (pwm0, channel 3)" default y endif + endmenu menu "Board extended module Drivers" - + menuconfig BSP_USING_RW007 + bool "Enable RW007" + default n + select BSP_USING_SPI1 + select PKG_USING_RW007 + select RT_USING_MEMPOOL + select RW007_NOT_USE_EXAMPLE_DRIVERS + + if BSP_USING_RW007 + config BOARD_RW007_SPI_BUS_NAME + string "RW007 BUS NAME" + default "spi1" + + config BOARD_RW007_CS_PIN + hex "CS pin index" + default 27 + + config BOARD_RW007_INT_BUSY_PIN + hex "INT/BUSY pin index" + default 10 + + config BOARD_RW007_RST_PIN + hex "RESET pin index" + default 28 + endif endmenu endmenu diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/MCUX_Config/board/pin_mux.c b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/MCUX_Config/board/pin_mux.c index e5ff7dd0820..e9f7ca5f097 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/MCUX_Config/board/pin_mux.c +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/MCUX_Config/board/pin_mux.c @@ -1,4 +1,4 @@ - +#include "rtconfig.h" #include "fsl_common.h" #include "fsl_port.h" @@ -32,6 +32,10 @@ void BOARD_InitBootPins(void) PORT1->PCR[16] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC5_UART */ PORT1->PCR[17] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC5_UART */ + /* DAC */ + // PORT4->PCR[2] = PORT_PCR_MUX(0) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(0); /* DAC0 */ + // PORT4->PCR[3] = PORT_PCR_MUX(0) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(0); /* DAC1 */ + /* MCX_RST UART */ PORT4->PCR[2] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC2_UART */ PORT4->PCR[3] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC2_UART */ @@ -39,17 +43,27 @@ void BOARD_InitBootPins(void) PORT0->PCR[6] = PORT_PCR_MUX(12) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1) | PORT_PCR_SRE(0) | PORT_PCR_ODE(0); /* CLKOUT */ +#ifdef BSP_USING_I2C1 PORT0->PCR[24] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1) | PORT_PCR_SRE(0) | PORT_PCR_ODE(0); /* FC1 I2C_SDA */ PORT0->PCR[25] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1) | PORT_PCR_SRE(0) | PORT_PCR_ODE(0); /* FC1 I2C_SCL */ +#endif PORT0->PCR[16] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1) | PORT_PCR_SRE(0) | PORT_PCR_ODE(0); /* FC0 I2C_SDA */ PORT0->PCR[17] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1) | PORT_PCR_SRE(0) | PORT_PCR_ODE(0); /* FC0 I2C_SCL */ -// PORT0->PCR[24] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC1_0 */ -// PORT0->PCR[25] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC1_1 */ -// PORT0->PCR[26] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC1_2 */ -// PORT0->PCR[27] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC1_3 */ +#ifdef BSP_USING_SPI1 + /* Arduino D11(P0_24), D12(P0_26), D13(P0_25) as SPI function, for RW007 MOSI, MISO, CLK */ + PORT0->PCR[24] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_24: FC1_0 */ + PORT0->PCR[26] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_26: FC1_2 */ + PORT0->PCR[25] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_25: FC1_1 */ + + /* Arduino D8(P0_28), D9(P0_10), D10(P0_27) as GPIO function, for RW007 RST, INT, CS */ + /* drv_pin.c works well, follow lines just notice that pins we used as GPIO function */ + // PORT0->PCR[28] = PORT_PCR_MUX(0) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_28: P0_28 */ + // PORT0->PCR[10] = PORT_PCR_MUX(0) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_10: P0_27 */ + PORT0->PCR[27] = PORT_PCR_MUX(0) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_27: P0_27 */ +#endif /* PMOD */ PORT1->PCR[0] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC3_0 SDO/D[0], FC3_SPI_MOSI */ @@ -60,6 +74,12 @@ void BOARD_InitBootPins(void) // PORT1->PCR[4] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC3_4 D[3] */ // PORT1->PCR[5] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC3_5 D[2] */ + /* SPI */ + PORT3->PCR[8] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC7_P0, MOSI */ + PORT3->PCR[9] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC7_P2, MISO */ + PORT3->PCR[7] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC7_P1, CLK */ + PORT3->PCR[0] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC7_P1, CS */ + PORT1->PCR[8] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC4_UART */ PORT1->PCR[9] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC4_UART */ @@ -89,8 +109,12 @@ void BOARD_InitBootPins(void) PORT2->PCR[6] = PORT_PCR_MUX(3) | PORT_PCR_PE(1) | PORT_PCR_PS(1) | PORT_PCR_IBE(1); /* SDHC0_D3 */ PORT2->PCR[7] = PORT_PCR_MUX(3) | PORT_PCR_PE(1) | PORT_PCR_PS(1) | PORT_PCR_IBE(1); /* SDHC0_D2 */ - PORT3->PCR[20] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_IBE(1); /* FC6_P0 */ - PORT3->PCR[21] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_IBE(1); /* FC6_P1 */ + /* mikroBUS SPI6 */ + PORT3->PCR[20] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC6_P0 SDO/D[0], FC6_SPI_MOSI */ + PORT3->PCR[21] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC6_P1 SCK, FC6_SPI_CLK */ + PORT3->PCR[22] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC6_P2 SDI/D[1], FC3_SPI_MISO */ + PORT3->PCR[23] = PORT_PCR_MUX(0) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* CS */ + // PORT1->PCR[20] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC4_0 */ // PORT1->PCR[21] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC4_1 */ diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/SConscript b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/SConscript index c9a0d56a978..23650145573 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/SConscript +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/SConscript @@ -9,6 +9,16 @@ MCUX_Config/board/clock_config.c MCUX_Config/board/pin_mux.c """) +if GetDepend(['BSP_USING_SPI6_SAMPLE']): + src += Glob('ports/spi_sample.c') + +if GetDepend(['BSP_USING_RW007']): + src += Glob('ports/drv_spi_sample_rw007.c') + +if GetDepend(['RT_USING_SFUD']): + src += Glob('ports/drv_filesystem_spi_flash.c') + + CPPPATH = [cwd, cwd + '/MCUX_Config/board'] CPPDEFINES = ['DEBUG', 'CPU_MCXN947VDF_cm33_core0'] diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/ports/drv_filesystem.c b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/ports/drv_filesystem.c deleted file mode 100644 index df9a5ba356d..00000000000 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/ports/drv_filesystem.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2006-2024, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-12-14 balanceTWK add sdcard port file - * 2021-02-26 Meco Man fix a bug that cannot use fatfs in the main thread at starting up - */ - -#include -#include -#include -#include -#include - -#if DFS_FILESYSTEMS_MAX < 4 -#error "Please define DFS_FILESYSTEMS_MAX more than 4" -#endif -#if DFS_FILESYSTEM_TYPES_MAX < 4 -#error "Please define DFS_FILESYSTEM_TYPES_MAX more than 4" -#endif - -#define DBG_TAG "app.filesystem" -#define DBG_LVL DBG_INFO -#include - - - -static int filesystem_mount(void) -{ -#ifdef RT_USING_SDIO - rt_thread_mdelay(2000); - if (dfs_mount("sd", "/", "elm", 0, NULL) == 0) - { - rt_kprintf("sd mounted to /\n"); - } - else - { - rt_kprintf("sd mount to / failed\n"); - } -#endif - - return RT_EOK; -} -INIT_APP_EXPORT(filesystem_mount); diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/ports/drv_filesystem_spi_flash.c b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/ports/drv_filesystem_spi_flash.c new file mode 100644 index 00000000000..be61835796c --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/ports/drv_filesystem_spi_flash.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-14 balanceTWK add sdcard port file + * 2021-02-26 Meco Man fix a bug that cannot use fatfs in the main thread at starting up + */ + +#include + +#if defined(BSP_USING_SPI7) && defined(RT_USING_SFUD) && defined(RT_USING_DFS) && defined(RT_USING_DFS_ELMFAT) +#include +#include "spi_flash_sfud.h" +#include "dfs_fs.h" +#include "dfs.h" +#include "dfs_file.h" + +#define DBG_TAG "spi-flash" +#define DBG_LVL DBG_INFO +#include + +#if DFS_FILESYSTEMS_MAX < 4 +#error "Please define DFS_FILESYSTEMS_MAX more than 4" +#endif +#if DFS_FILESYSTEM_TYPES_MAX < 4 +#error "Please define DFS_FILESYSTEM_TYPES_MAX more than 4" +#endif + + +#define DBG_TAG "app.filesystem_spi_flash" +#define DBG_LVL DBG_INFO +#include + + +#define W25Q64_SPI_DEVICE_NAME "spi70" +#define W25Q64_SPI_BUS_NAME "spi7" +#define W25Q64_SPI_FLASH_NAME "w25qxx" + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin); + +static int filesystem_mount(void) +{ + struct rt_spi_device *spi70 = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + + if(!spi70) + { + LOG_W("spi sample run failed! can't find %s device!\n","spi7"); + return -RT_ERROR; + } + + struct rt_spi_configuration cfg; + cfg.data_width = 8; + cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_3 | RT_SPI_MSB; + cfg.max_hz = 50 * 1000 *1000; + rt_spi_configure(spi70, &cfg); + + /* legcy issue */ + + rt_hw_spi_device_attach(W25Q64_SPI_BUS_NAME, W25Q64_SPI_DEVICE_NAME, 96); + + if(RT_NULL == rt_sfud_flash_probe(W25Q64_SPI_FLASH_NAME, W25Q64_SPI_DEVICE_NAME)) + { + LOG_E("Flash sfud Failed!\n"); + return -RT_ERROR; + } + if(dfs_mount(W25Q64_SPI_FLASH_NAME, "/", "elm", 0, 0)) + { + LOG_E("dfs mount dev:%s failed!\n", W25Q64_SPI_FLASH_NAME); + return -RT_ERROR; + } + + return RT_EOK; +} +INIT_APP_EXPORT(filesystem_mount); + +#endif /* BSP_USING_SPI7/RT_USING_SFUD/RT_USING_DFS/RT_USING_DFS_ELMFAT */ \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/ports/drv_spi_sample_rw007.c b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/ports/drv_spi_sample_rw007.c new file mode 100644 index 00000000000..9f34ffba5c9 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/ports/drv_spi_sample_rw007.c @@ -0,0 +1,68 @@ +#include + +#ifdef BSP_USING_RW007 +#include +#include +#include +#include + +extern void spi_wifi_isr(int vector); + +static void rw007_gpio_init(void) +{ + /* Configure IO */ + rt_pin_mode(BOARD_RW007_RST_PIN, PIN_MODE_OUTPUT); + rt_pin_mode(BOARD_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN); + + /* Reset rw007 and config mode */ + rt_pin_write(BOARD_RW007_RST_PIN, PIN_LOW); + + rt_thread_delay(rt_tick_from_millisecond(1)); + rt_pin_write(BOARD_RW007_RST_PIN, PIN_HIGH); + + /* Wait rw007 ready(exit busy stat) */ + while (!(BOARD_RW007_INT_BUSY_PIN)) + { + rt_thread_delay(5); + } + + rt_thread_delay(rt_tick_from_millisecond(200)); + rt_pin_mode(BOARD_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP); +} + +extern rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin); + +int wifi_spi_device_init(void) +{ + char sn_version[32]; + uint32_t cs_pin = BOARD_RW007_CS_PIN; + + rw007_gpio_init(); + rt_hw_spi_device_attach(BOARD_RW007_SPI_BUS_NAME, "rw007", cs_pin); + rt_hw_wifi_init("rw007"); + + rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION); + rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP); + + rw007_sn_get(sn_version); + rt_kprintf("\nrw007 sn: [%s]\n", sn_version); + rw007_version_get(sn_version); + rt_kprintf("rw007 ver: [%s]\n\n", sn_version); + + return 0; +} +INIT_APP_EXPORT(wifi_spi_device_init); + +static void int_wifi_irq(void *p) +{ + ((void)p); + spi_wifi_isr(0); +} + +void spi_wifi_hw_init(void) +{ + rt_pin_attach_irq(BOARD_RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0); + rt_pin_irq_enable(BOARD_RW007_INT_BUSY_PIN, RT_TRUE); +} + +#endif \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/ports/spi_sample.c b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/ports/spi_sample.c new file mode 100644 index 00000000000..e2bc2ce932c --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/ports/spi_sample.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-07-19 Rbbb666 first version + * 2024-03-30 xhackerustc 2nd version for FRDM-MCXN947 + */ + +#include "board.h" + +#include + +#define SPI_NAME "spi60" +#define CS_PIN (3*32+23) +static struct rt_spi_device *spi_dev; + +/* attach spi device */ +static int rt_spi_device_init(void) +{ + struct rt_spi_configuration cfg; + + rt_hw_spi_device_attach("spi6", SPI_NAME, CS_PIN); + + cfg.data_width = 8; + cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB | RT_SPI_NO_CS; + cfg.max_hz = 1 *1000 *1000; + + spi_dev = (struct rt_spi_device *)rt_device_find(SPI_NAME); + + if (RT_NULL == spi_dev) + { + rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_NAME); + return -RT_ERROR; + } + + rt_spi_configure(spi_dev, &cfg); + + return RT_EOK; +} +INIT_APP_EXPORT(rt_spi_device_init); + +/* spi loopback mode test case */ +static int spi_sample(int argc, char **argv) +{ + rt_uint8_t t_buf[32], r_buf[32]; + int i = 0; + static struct rt_spi_message msg1; + + for (i = 0; i < sizeof(t_buf); i++) + { + t_buf[i] = i; + } + + msg1.send_buf = &t_buf; + msg1.recv_buf = &r_buf; + msg1.length = sizeof(t_buf); + msg1.cs_take = 1; + msg1.cs_release = 1; + msg1.next = RT_NULL; + + rt_spi_transfer_message(spi_dev, &msg1); + + rt_kprintf("spi rbuf : "); + for (i = 0; i < sizeof(r_buf); i++) + { + rt_kprintf("%x ", r_buf[i]); + } + + rt_kprintf("\nspi loopback mode test over!\n"); + + return RT_EOK; +} +MSH_CMD_EXPORT(spi_sample, spi loopback test); diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvprojx b/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvprojx index 0a0a9f036b4..9cd1f2f9649 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvprojx +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvprojx @@ -506,6 +506,25 @@ + + + condvar.c + 1 + ..\..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1126,6 +1145,13 @@ ..\Libraries\MCXN947\MCXN947\drivers\fsl_lpuart.c + + + fsl_lpspi_edma.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_lpspi_edma.c + + fsl_cmc.c @@ -1182,6 +1208,13 @@ ..\Libraries\MCXN947\MCXN947\drivers\fsl_reset.c + + + fsl_lpadc.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_lpadc.c + + fsl_vref.c @@ -1273,6 +1306,13 @@ ..\Libraries\MCXN947\MCXN947\system_MCXN947_cm33_core0.c + + + fsl_spc.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_spc.c + + fsl_flexio_i2c_master.c @@ -1407,16 +1447,16 @@ Utilities - ulog.c + console_be.c 1 - ..\..\..\..\..\components\utilities\ulog\ulog.c + ..\..\..\..\..\components\utilities\ulog\backend\console_be.c - console_be.c + ulog.c 1 - ..\..\..\..\..\components\utilities\ulog\backend\console_be.c + ..\..\..\..\..\components\utilities\ulog\ulog.c diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/rtconfig.py b/bsp/nxp/mcx/mcxn/frdm-mcxn947/rtconfig.py index 2996ef49563..d21ad58c872 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/rtconfig.py +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/rtconfig.py @@ -192,7 +192,7 @@ def dist_handle(BSP_ROOT, dist_dir): cwd_path = os.getcwd() - sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), '..', 'tools')) from sdk_dist import dist_do_building dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/nxp/mcx/tools/sdk_dist.py b/bsp/nxp/mcx/tools/sdk_dist.py index 6fbddfbd4ee..844fd61d9e8 100644 --- a/bsp/nxp/mcx/tools/sdk_dist.py +++ b/bsp/nxp/mcx/tools/sdk_dist.py @@ -18,3 +18,17 @@ def dist_do_building(BSP_ROOT, dist_dir): print("=> copy bsp library") bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE)) shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) + + # if project Kconfig not exists, no more work to do! + project_kconfig = os.path.join(dist_dir, 'Kconfig') + if not os.path.exists(project_kconfig): + print("project Kconfig not exists!") + return + + # replace '../Libraries/Kconfig' to 'Libraries/Kconfig' + with open(project_kconfig, 'r') as f: + data = f.readlines() + with open(project_kconfig, 'w') as f: + for line in data: + line = line.replace('../Libraries/Kconfig', 'Libraries/Kconfig') + f.write(line) diff --git a/bsp/phytium/README.md b/bsp/phytium/README.md index 7c853915e88..65245dfd2dc 100644 --- a/bsp/phytium/README.md +++ b/bsp/phytium/README.md @@ -58,6 +58,7 @@ 2. 启动 RT-Thread env 应用程序，在交互界面可以使用`cd`指令进入`aarch32`或`aarch64`目录 3. 按照指导安装 [aarch32](./aarch32/README.md)或[aarch64](./aarch64/README.md)编译链，并进行相关配置 4. 按照指导[启动镜像程序](./doc/how_to_flashed_binary.md) +5. 参考[使用文件系统](./doc/how_to_use_file_system.md)制作和使用文件系统 ### RT-Thread Studio 环境 diff --git a/bsp/phytium/aarch32/.config b/bsp/phytium/aarch32/.config index 5a4ca4888ba..8c9456d6a0e 100644 --- a/bsp/phytium/aarch32/.config +++ b/bsp/phytium/aarch32/.config @@ -1219,9 +1219,16 @@ CONFIG_RT_USING_SPIM0=y # CONFIG_RT_USING_SPIM1 is not set # CONFIG_RT_USING_SPIM2 is not set # CONFIG_RT_USING_SPIM3 is not set -# CONFIG_BSP_USING_CAN is not set +CONFIG_BSP_USING_CAN=y +# CONFIG_RT_USING_CANFD is not set +# CONFIG_RT_USING_FILTER is not set +# CONFIG_RT_USING_CAN0 is not set +# CONFIG_RT_USING_CAN1 is not set CONFIG_BSP_USING_GPIO=y -# CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_QSPI=y +CONFIG_RT_USING_QSPI0=y +CONFIG_USING_QSPI_CHANNEL0=y +# CONFIG_USING_QSPI_CHANNEL1 is not set CONFIG_BSP_USING_ETH=y CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 CONFIG_BSP_USING_PWM=y @@ -1252,10 +1259,15 @@ CONFIG_RT_USING_MIO1=y # CONFIG_RT_USING_MIO14 is not set # CONFIG_RT_USING_MIO15 is not set # CONFIG_I2C_USE_CONTROLLER is not set -# CONFIG_BSP_USING_SDIF is not set +CONFIG_BSP_USING_SDIF=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIF0 is not set +CONFIG_USING_SDIF1=y +CONFIG_USE_SDIF1_TF=y +# CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y CONFIG_RT_USING_DC_CHANNEL0=y -# CONFIG_RT_USING_DC_CHANNEL1 is not set +CONFIG_RT_USING_DC_CHANNEL1=y # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set @@ -1279,6 +1291,7 @@ CONFIG_TARGET_PHYTIUMPI=y # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="phytiumpi" CONFIG_SOC_CORE_NUM=4 CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000 @@ -1286,7 +1299,6 @@ CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 CONFIG_TARGET_E2000=y -# CONFIG_USE_SPINLOCK is not set CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set # CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set diff --git a/bsp/phytium/aarch32/applications/mnt.c b/bsp/phytium/aarch32/applications/mnt.c deleted file mode 100644 index e052a3e812c..00000000000 --- a/bsp/phytium/aarch32/applications/mnt.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Email: opensource_embedded@phytium.com.cn - * - * Change Logs: - * Date Author Notes - * 2023-04-27 huanghe first version - * 2023-07-14 liqiaozhong add SD file sys mount func - * - */ -#include -#if defined(RT_USING_DFS) -#include - -#include -#include - -static int ram_disk_mount(const char *mount_point) -{ -#ifdef RT_USING_DFS_RAMFS - extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size); - - rt_uint8_t *pool = RT_NULL; - rt_size_t size = 8 * 1024 * 1024; - - pool = rt_malloc(size); - if (pool == RT_NULL) - { - LOG_E("Malloc fail!"); - } - - if (dfs_mount(RT_NULL, mount_point, "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0) - { - LOG_I("RAM file system initializated!"); - } - else - { - LOG_E("RAM file system initializate failed!"); - } -#endif - - return RT_EOK; -} - -#ifdef BSP_USING_SDCARD_FATFS -extern void fsdif_change(void); -static int sd_disk_try_mount(char *device_name, char *mount_point, char *fs_type_name, int mkfs_count) -{ - struct statfs fs_stat; - int rc = 0; - - LOG_I("mount(\"%s\",\"%s\",\"%s\");", device_name, mount_point, fs_type_name); - - if (rt_device_find(device_name) == NULL) - { - LOG_I("%s not find!!!", device_name); - return -RT_EIO; - } - - mkdir(mount_point, 0); -_remount: - rc = dfs_mount(device_name, mount_point, fs_type_name, 0, 0); - if (rc == 0) - { - LOG_I("mounted %s on %s", device_name, mount_point); - if (dfs_statfs(mount_point, &fs_stat) >= 0) - { - LOG_I("%s size:%d, total: %d, free: %d", mount_point, - fs_stat.f_bsize, fs_stat.f_blocks, fs_stat.f_bfree); - } - } - else - { - if (mkfs_count > 0) - { - /* LOG_I("[%s]try mkfs -t %s %s ", mkfs_count, fs_type_name, device_name); - dfs_mkfs(fs_type_name, device_name); */ - mkfs_count--; - LOG_E("%s is not in %s, please format first !!!", device_name, fs_type_name); - goto _remount; - } - - LOG_I("mount failed :%d ", rc); - return -RT_EIO; - } - - return RT_EOK; -} - -static void sd_filesytem_task_entry(void *parameter) -{ - int result; - LOG_D("sdio host change: %d", change); - mmcsd_wait_cd_changed(0); /* clear */ - fsdif_change(); /* send cd change to host */ - - /* block until plug/unplug event happens */ - result = mmcsd_wait_cd_changed(RT_WAITING_FOREVER); - if (result == MMCSD_HOST_PLUGED) - { - rt_kprintf("mmcsd change pluged \n"); - /* mount sdcard partition as / */ - if (RT_EOK == sd_disk_try_mount(BSP_USING_SDCARD_PARTITION, "/", "elm", 0)) - { - ram_disk_mount("/ram"); /* mount ramdisk if configured */ - } - } -} - -int filesystem_mount(void) -{ - rt_thread_t tid; - tid = rt_thread_create("sd_filesytem", sd_filesytem_task_entry, - RT_NULL, - 4096, - RT_THREAD_PRIORITY_MAX - 2, 20); - if (tid != RT_NULL) - { - rt_thread_startup(tid); - } - else - { - LOG_E("create sd mount task error!"); - } - - return RT_EOK; -} -INIT_APP_EXPORT(filesystem_mount); - -#else -static int filesystem_mount(void) -{ - return ram_disk_mount("/"); /* mount ramdisk as / */ -} -INIT_APP_EXPORT(filesystem_mount); -#endif // #ifdef BSP_USING_SDCARD_FATFS -#endif // #if defined(RT_USING_DFS) \ No newline at end of file diff --git a/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart b/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart index 50307b51e01..7a28d9a0c60 100644 --- a/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart +++ b/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart @@ -78,7 +78,7 @@ CONFIG_RT_USING_HEAP=y CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_DEVICE_OPS=y # CONFIG_RT_USING_INTERRUPT_INFO is not set -# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_THREADSAFE_PRINTF=y CONFIG_RT_USING_SCHED_THREAD_CTX=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=256 @@ -135,7 +135,6 @@ CONFIG_RT_USING_DFS=y CONFIG_DFS_USING_POSIX=y CONFIG_DFS_USING_WORKDIR=y CONFIG_DFS_FD_MAX=16 -# CONFIG_RT_USING_DFS_V1 is not set CONFIG_RT_USING_DFS_V2=y CONFIG_RT_USING_DFS_ELMFAT=y @@ -163,6 +162,7 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 # CONFIG_RT_DFS_ELM_USE_EXFAT is not set CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +CONFIG_RT_USING_DFS_PTYFS=y # CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_TMPFS is not set CONFIG_RT_USING_DFS_MQUEUE=y @@ -193,10 +193,8 @@ CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=1024 -CONFIG_RT_USING_TTY=y -# CONFIG_RT_TTY_DEBUG is not set CONFIG_RT_USING_CAN=y -CONFIG_RT_CAN_USING_HDR=y +# CONFIG_RT_CAN_USING_HDR is not set CONFIG_RT_CAN_USING_CANFD=y # CONFIG_RT_USING_CPUTIME is not set CONFIG_RT_USING_I2C=y @@ -421,10 +419,11 @@ CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 CONFIG_LWP_TID_MAX_NR=64 CONFIG_LWP_ENABLE_ASID=y CONFIG_RT_LWP_SHM_MAX_NR=64 -# CONFIG_LWP_UNIX98_PTY is not set CONFIG_RT_USING_LDSO=y # CONFIG_ELF_DEBUG_ENABLE is not set # CONFIG_ELF_LOAD_RANDOMIZE is not set +CONFIG_LWP_USING_TERMINAL=y +CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # Memory management @@ -1246,13 +1245,13 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART2 is not set # CONFIG_RT_USING_UART3 is not set CONFIG_BSP_USING_SPI=y -# CONFIG_RT_USING_SPIM0 is not set +CONFIG_RT_USING_SPIM0=y # CONFIG_RT_USING_SPIM1 is not set -CONFIG_RT_USING_SPIM2=y +# CONFIG_RT_USING_SPIM2 is not set # CONFIG_RT_USING_SPIM3 is not set CONFIG_BSP_USING_CAN=y -CONFIG_RT_USING_CANFD=y -CONFIG_RT_USING_FILTER=y +# CONFIG_RT_USING_CANFD is not set +# CONFIG_RT_USING_FILTER is not set CONFIG_RT_USING_CAN0=y CONFIG_RT_USING_CAN1=y CONFIG_BSP_USING_GPIO=y @@ -1265,16 +1264,16 @@ CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 CONFIG_BSP_USING_PWM=y # CONFIG_RT_USING_PWM0 is not set # CONFIG_RT_USING_PWM1 is not set -# CONFIG_RT_USING_PWM2 is not set +CONFIG_RT_USING_PWM2=y # CONFIG_RT_USING_PWM3 is not set # CONFIG_RT_USING_PWM4 is not set # CONFIG_RT_USING_PWM5 is not set -CONFIG_RT_USING_PWM6=y +# CONFIG_RT_USING_PWM6 is not set # CONFIG_RT_USING_PWM7 is not set CONFIG_BSP_USING_I2C=y CONFIG_I2C_USE_MIO=y -# CONFIG_RT_USING_MIO0 is not set -# CONFIG_RT_USING_MIO1 is not set +CONFIG_RT_USING_MIO0=y +CONFIG_RT_USING_MIO1=y # CONFIG_RT_USING_MIO2 is not set # CONFIG_RT_USING_MIO3 is not set # CONFIG_RT_USING_MIO4 is not set @@ -1288,21 +1287,19 @@ CONFIG_I2C_USE_MIO=y # CONFIG_RT_USING_MIO12 is not set # CONFIG_RT_USING_MIO13 is not set # CONFIG_RT_USING_MIO14 is not set -CONFIG_RT_USING_MIO15=y -CONFIG_I2C_USE_CONTROLLER=y -CONFIG_RT_USING_I2C0=y -# CONFIG_RT_USING_I2C1 is not set -# CONFIG_RT_USING_I2C2 is not set -# CONFIG_RT_USING_I2C3 is not set +# CONFIG_RT_USING_MIO15 is not set +# CONFIG_I2C_USE_CONTROLLER is not set CONFIG_BSP_USING_SDIF=y CONFIG_BSP_USING_SDCARD_FATFS=y -CONFIG_BSP_USING_SDCARD_PARTITION="sd0" -# CONFIG_USING_SDIF0 is not set +CONFIG_USING_SDIF0=y +# CONFIG_USE_SDIF0_TF is not set +CONFIG_USE_SDIF0_EMMC=y CONFIG_USING_SDIF1=y -# CONFIG_USING_EMMC is not set +CONFIG_USE_SDIF1_TF=y +# CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y -# CONFIG_RT_USING_DC_CHANNEL0 is not set -CONFIG_RT_USING_DC_CHANNEL1=y +CONFIG_RT_USING_DC_CHANNEL0=y +# CONFIG_RT_USING_DC_CHANNEL1 is not set # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set @@ -1326,6 +1323,7 @@ CONFIG_TARGET_E2000D=y # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="e2000" CONFIG_TARGET_TYPE_NAME="d" CONFIG_SOC_CORE_NUM=2 @@ -1334,7 +1332,6 @@ CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 CONFIG_TARGET_E2000=y -# CONFIG_USE_SPINLOCK is not set CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set # CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set @@ -1358,6 +1355,7 @@ CONFIG_BOARD_NAME="demo" # CONFIG_USE_TACHO_IOPAD is not set # CONFIG_USE_UART_IOPAD is not set # CONFIG_USE_THIRD_PARTY_IOPAD is not set +# CONFIG_FIREFLY_DEMO_BOARD is not set # CONFIG_CUS_DEMO_BOARD is not set # diff --git a/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart.h b/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart.h index 8cd62cc4352..24f9866092f 100644 --- a/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart.h +++ b/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart.h @@ -53,6 +53,7 @@ #define RT_USING_HEAP #define RT_USING_DEVICE #define RT_USING_DEVICE_OPS +#define RT_USING_THREADSAFE_PRINTF #define RT_USING_SCHED_THREAD_CTX #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 256 @@ -114,6 +115,7 @@ #define RT_DFS_ELM_REENTRANT #define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS +#define RT_USING_DFS_PTYFS #define RT_USING_DFS_MQUEUE #define RT_USING_PAGECACHE @@ -137,9 +139,7 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 1024 -#define RT_USING_TTY #define RT_USING_CAN -#define RT_CAN_USING_HDR #define RT_CAN_USING_CANFD #define RT_USING_I2C #define RT_USING_I2C_BITOPS @@ -282,6 +282,8 @@ #define LWP_ENABLE_ASID #define RT_LWP_SHM_MAX_NR 64 #define RT_USING_LDSO +#define LWP_USING_TERMINAL +#define LWP_PTY_MAX_PARIS_LIMIT 64 /* Memory management */ @@ -421,10 +423,8 @@ #define RT_USING_UART0 #define RT_USING_UART1 #define BSP_USING_SPI -#define RT_USING_SPIM2 +#define RT_USING_SPIM0 #define BSP_USING_CAN -#define RT_USING_CANFD -#define RT_USING_FILTER #define RT_USING_CAN0 #define RT_USING_CAN1 #define BSP_USING_GPIO @@ -434,18 +434,19 @@ #define BSP_USING_ETH #define RT_LWIP_PBUF_POOL_BUFSIZE 1700 #define BSP_USING_PWM -#define RT_USING_PWM6 +#define RT_USING_PWM2 #define BSP_USING_I2C #define I2C_USE_MIO -#define RT_USING_MIO15 -#define I2C_USE_CONTROLLER -#define RT_USING_I2C0 +#define RT_USING_MIO0 +#define RT_USING_MIO1 #define BSP_USING_SDIF #define BSP_USING_SDCARD_FATFS -#define BSP_USING_SDCARD_PARTITION "sd0" +#define USING_SDIF0 +#define USE_SDIF0_EMMC #define USING_SDIF1 +#define USE_SDIF1_TF #define BSP_USING_DC -#define RT_USING_DC_CHANNEL1 +#define RT_USING_DC_CHANNEL0 /* Board extended module Drivers */ diff --git a/bsp/phytium/aarch32/configs/e2000d_demo_rtthread b/bsp/phytium/aarch32/configs/e2000d_demo_rtthread index c7b8fea0d80..ddda850c8a2 100644 --- a/bsp/phytium/aarch32/configs/e2000d_demo_rtthread +++ b/bsp/phytium/aarch32/configs/e2000d_demo_rtthread @@ -186,7 +186,7 @@ CONFIG_RT_USING_SERIAL_V1=y CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=1024 CONFIG_RT_USING_CAN=y -CONFIG_RT_CAN_USING_HDR=y +# CONFIG_RT_CAN_USING_HDR is not set CONFIG_RT_CAN_USING_CANFD=y # CONFIG_RT_USING_CPUTIME is not set CONFIG_RT_USING_I2C=y @@ -1215,15 +1215,15 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART2 is not set # CONFIG_RT_USING_UART3 is not set CONFIG_BSP_USING_SPI=y -# CONFIG_RT_USING_SPIM0 is not set +CONFIG_RT_USING_SPIM0=y # CONFIG_RT_USING_SPIM1 is not set -CONFIG_RT_USING_SPIM2=y +# CONFIG_RT_USING_SPIM2 is not set # CONFIG_RT_USING_SPIM3 is not set CONFIG_BSP_USING_CAN=y -CONFIG_RT_USING_CANFD=y -CONFIG_RT_USING_FILTER=y -CONFIG_RT_USING_CAN0=y -CONFIG_RT_USING_CAN1=y +# CONFIG_RT_USING_CANFD is not set +# CONFIG_RT_USING_FILTER is not set +# CONFIG_RT_USING_CAN0 is not set +# CONFIG_RT_USING_CAN1 is not set CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_QSPI=y CONFIG_RT_USING_QSPI0=y @@ -1234,16 +1234,16 @@ CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 CONFIG_BSP_USING_PWM=y # CONFIG_RT_USING_PWM0 is not set # CONFIG_RT_USING_PWM1 is not set -# CONFIG_RT_USING_PWM2 is not set +CONFIG_RT_USING_PWM2=y # CONFIG_RT_USING_PWM3 is not set # CONFIG_RT_USING_PWM4 is not set # CONFIG_RT_USING_PWM5 is not set -CONFIG_RT_USING_PWM6=y +# CONFIG_RT_USING_PWM6 is not set # CONFIG_RT_USING_PWM7 is not set CONFIG_BSP_USING_I2C=y CONFIG_I2C_USE_MIO=y -# CONFIG_RT_USING_MIO0 is not set -# CONFIG_RT_USING_MIO1 is not set +CONFIG_RT_USING_MIO0=y +CONFIG_RT_USING_MIO1=y # CONFIG_RT_USING_MIO2 is not set # CONFIG_RT_USING_MIO3 is not set # CONFIG_RT_USING_MIO4 is not set @@ -1257,20 +1257,18 @@ CONFIG_I2C_USE_MIO=y # CONFIG_RT_USING_MIO12 is not set # CONFIG_RT_USING_MIO13 is not set # CONFIG_RT_USING_MIO14 is not set -CONFIG_RT_USING_MIO15=y -CONFIG_I2C_USE_CONTROLLER=y -CONFIG_RT_USING_I2C0=y -# CONFIG_RT_USING_I2C1 is not set -# CONFIG_RT_USING_I2C2 is not set -# CONFIG_RT_USING_I2C3 is not set +# CONFIG_RT_USING_MIO15 is not set +# CONFIG_I2C_USE_CONTROLLER is not set CONFIG_BSP_USING_SDIF=y CONFIG_BSP_USING_SDCARD_FATFS=y -CONFIG_BSP_USING_SDCARD_PARTITION="sd0" -# CONFIG_USING_SDIF0 is not set +CONFIG_USING_SDIF0=y +# CONFIG_USE_SDIF0_TF is not set +CONFIG_USE_SDIF0_EMMC=y CONFIG_USING_SDIF1=y -# CONFIG_USING_EMMC is not set +CONFIG_USE_SDIF1_TF=y +# CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y -# CONFIG_RT_USING_DC_CHANNEL0 is not set +CONFIG_RT_USING_DC_CHANNEL0=y CONFIG_RT_USING_DC_CHANNEL1=y # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set @@ -1295,6 +1293,7 @@ CONFIG_TARGET_E2000D=y # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="e2000" CONFIG_TARGET_TYPE_NAME="d" CONFIG_SOC_CORE_NUM=2 @@ -1303,7 +1302,6 @@ CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 CONFIG_TARGET_E2000=y -# CONFIG_USE_SPINLOCK is not set CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set # CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set @@ -1327,6 +1325,7 @@ CONFIG_BOARD_NAME="demo" # CONFIG_USE_TACHO_IOPAD is not set # CONFIG_USE_UART_IOPAD is not set # CONFIG_USE_THIRD_PARTY_IOPAD is not set +# CONFIG_E2000Q_DEMO_BOARD is not set # CONFIG_CUS_DEMO_BOARD is not set # diff --git a/bsp/phytium/aarch32/configs/e2000d_demo_rtthread.h b/bsp/phytium/aarch32/configs/e2000d_demo_rtthread.h index 4cbca1aaf2c..7db829a50db 100644 --- a/bsp/phytium/aarch32/configs/e2000d_demo_rtthread.h +++ b/bsp/phytium/aarch32/configs/e2000d_demo_rtthread.h @@ -127,7 +127,6 @@ #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 1024 #define RT_USING_CAN -#define RT_CAN_USING_HDR #define RT_CAN_USING_CANFD #define RT_USING_I2C #define RT_USING_I2C_BITOPS @@ -394,12 +393,8 @@ #define RT_USING_UART0 #define RT_USING_UART1 #define BSP_USING_SPI -#define RT_USING_SPIM2 +#define RT_USING_SPIM0 #define BSP_USING_CAN -#define RT_USING_CANFD -#define RT_USING_FILTER -#define RT_USING_CAN0 -#define RT_USING_CAN1 #define BSP_USING_GPIO #define BSP_USING_QSPI #define RT_USING_QSPI0 @@ -407,17 +402,19 @@ #define BSP_USING_ETH #define RT_LWIP_PBUF_POOL_BUFSIZE 1700 #define BSP_USING_PWM -#define RT_USING_PWM6 +#define RT_USING_PWM2 #define BSP_USING_I2C #define I2C_USE_MIO -#define RT_USING_MIO15 -#define I2C_USE_CONTROLLER -#define RT_USING_I2C0 +#define RT_USING_MIO0 +#define RT_USING_MIO1 #define BSP_USING_SDIF #define BSP_USING_SDCARD_FATFS -#define BSP_USING_SDCARD_PARTITION "sd0" +#define USING_SDIF0 +#define USE_SDIF0_EMMC #define USING_SDIF1 +#define USE_SDIF1_TF #define BSP_USING_DC +#define RT_USING_DC_CHANNEL0 #define RT_USING_DC_CHANNEL1 /* Board extended module Drivers */ diff --git a/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart b/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart index 3383732ae92..c9208e8d0eb 100644 --- a/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart +++ b/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart @@ -162,6 +162,7 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 # CONFIG_RT_DFS_ELM_USE_EXFAT is not set CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +CONFIG_RT_USING_DFS_PTYFS=y # CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_TMPFS is not set CONFIG_RT_USING_DFS_MQUEUE=y @@ -192,8 +193,6 @@ CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=1024 -CONFIG_RT_USING_TTY=y -# CONFIG_RT_TTY_DEBUG is not set CONFIG_RT_USING_CAN=y # CONFIG_RT_CAN_USING_HDR is not set CONFIG_RT_CAN_USING_CANFD=y @@ -420,10 +419,11 @@ CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 CONFIG_LWP_TID_MAX_NR=64 CONFIG_LWP_ENABLE_ASID=y CONFIG_RT_LWP_SHM_MAX_NR=64 -# CONFIG_LWP_UNIX98_PTY is not set CONFIG_RT_USING_LDSO=y # CONFIG_ELF_DEBUG_ENABLE is not set # CONFIG_ELF_LOAD_RANDOMIZE is not set +CONFIG_LWP_USING_TERMINAL=y +CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # Memory management @@ -1249,9 +1249,16 @@ CONFIG_RT_USING_SPIM0=y # CONFIG_RT_USING_SPIM1 is not set # CONFIG_RT_USING_SPIM2 is not set # CONFIG_RT_USING_SPIM3 is not set -# CONFIG_BSP_USING_CAN is not set +CONFIG_BSP_USING_CAN=y +# CONFIG_RT_USING_CANFD is not set +# CONFIG_RT_USING_FILTER is not set +CONFIG_RT_USING_CAN0=y +CONFIG_RT_USING_CAN1=y CONFIG_BSP_USING_GPIO=y -# CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_QSPI=y +CONFIG_RT_USING_QSPI0=y +CONFIG_USING_QSPI_CHANNEL0=y +# CONFIG_USING_QSPI_CHANNEL1 is not set CONFIG_BSP_USING_ETH=y CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 CONFIG_BSP_USING_PWM=y @@ -1282,7 +1289,14 @@ CONFIG_RT_USING_MIO1=y # CONFIG_RT_USING_MIO14 is not set # CONFIG_RT_USING_MIO15 is not set # CONFIG_I2C_USE_CONTROLLER is not set -# CONFIG_BSP_USING_SDIF is not set +CONFIG_BSP_USING_SDIF=y +CONFIG_BSP_USING_SDCARD_FATFS=y +CONFIG_USING_SDIF0=y +# CONFIG_USE_SDIF0_TF is not set +CONFIG_USE_SDIF0_EMMC=y +CONFIG_USING_SDIF1=y +CONFIG_USE_SDIF1_TF=y +# CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y CONFIG_RT_USING_DC_CHANNEL0=y # CONFIG_RT_USING_DC_CHANNEL1 is not set @@ -1309,6 +1323,7 @@ CONFIG_TARGET_E2000Q=y # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="e2000" CONFIG_TARGET_TYPE_NAME="q" CONFIG_SOC_CORE_NUM=4 @@ -1317,7 +1332,6 @@ CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 CONFIG_TARGET_E2000=y -# CONFIG_USE_SPINLOCK is not set CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set # CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set @@ -1340,7 +1354,6 @@ CONFIG_E2000Q_DEMO_BOARD=y # # IO mux configuration when board start up # -# CONFIG_FIREFLY_DEMO_BOARD is not set # CONFIG_CUS_DEMO_BOARD is not set # diff --git a/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart.h b/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart.h index 560db767e02..56c5402ba14 100644 --- a/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart.h +++ b/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart.h @@ -115,6 +115,7 @@ #define RT_DFS_ELM_REENTRANT #define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS +#define RT_USING_DFS_PTYFS #define RT_USING_DFS_MQUEUE #define RT_USING_PAGECACHE @@ -138,7 +139,6 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 1024 -#define RT_USING_TTY #define RT_USING_CAN #define RT_CAN_USING_CANFD #define RT_USING_I2C @@ -282,6 +282,8 @@ #define LWP_ENABLE_ASID #define RT_LWP_SHM_MAX_NR 64 #define RT_USING_LDSO +#define LWP_USING_TERMINAL +#define LWP_PTY_MAX_PARIS_LIMIT 64 /* Memory management */ @@ -422,7 +424,13 @@ #define RT_USING_UART1 #define BSP_USING_SPI #define RT_USING_SPIM0 +#define BSP_USING_CAN +#define RT_USING_CAN0 +#define RT_USING_CAN1 #define BSP_USING_GPIO +#define BSP_USING_QSPI +#define RT_USING_QSPI0 +#define USING_QSPI_CHANNEL0 #define BSP_USING_ETH #define RT_LWIP_PBUF_POOL_BUFSIZE 1700 #define BSP_USING_PWM @@ -431,6 +439,12 @@ #define I2C_USE_MIO #define RT_USING_MIO0 #define RT_USING_MIO1 +#define BSP_USING_SDIF +#define BSP_USING_SDCARD_FATFS +#define USING_SDIF0 +#define USE_SDIF0_EMMC +#define USING_SDIF1 +#define USE_SDIF1_TF #define BSP_USING_DC #define RT_USING_DC_CHANNEL0 diff --git a/bsp/phytium/aarch32/configs/e2000q_demo_rtthread b/bsp/phytium/aarch32/configs/e2000q_demo_rtthread index 6fa95ea3e82..1e8a6d0c2b2 100644 --- a/bsp/phytium/aarch32/configs/e2000q_demo_rtthread +++ b/bsp/phytium/aarch32/configs/e2000q_demo_rtthread @@ -1219,9 +1219,16 @@ CONFIG_RT_USING_SPIM0=y # CONFIG_RT_USING_SPIM1 is not set # CONFIG_RT_USING_SPIM2 is not set # CONFIG_RT_USING_SPIM3 is not set -# CONFIG_BSP_USING_CAN is not set +CONFIG_BSP_USING_CAN=y +# CONFIG_RT_USING_CANFD is not set +# CONFIG_RT_USING_FILTER is not set +# CONFIG_RT_USING_CAN0 is not set +# CONFIG_RT_USING_CAN1 is not set CONFIG_BSP_USING_GPIO=y -# CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_QSPI=y +CONFIG_RT_USING_QSPI0=y +CONFIG_USING_QSPI_CHANNEL0=y +# CONFIG_USING_QSPI_CHANNEL1 is not set CONFIG_BSP_USING_ETH=y CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 CONFIG_BSP_USING_PWM=y @@ -1252,10 +1259,17 @@ CONFIG_RT_USING_MIO1=y # CONFIG_RT_USING_MIO14 is not set # CONFIG_RT_USING_MIO15 is not set # CONFIG_I2C_USE_CONTROLLER is not set -# CONFIG_BSP_USING_SDIF is not set +CONFIG_BSP_USING_SDIF=y +CONFIG_BSP_USING_SDCARD_FATFS=y +CONFIG_USING_SDIF0=y +# CONFIG_USE_SDIF0_TF is not set +CONFIG_USE_SDIF0_EMMC=y +CONFIG_USING_SDIF1=y +CONFIG_USE_SDIF1_TF=y +# CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y CONFIG_RT_USING_DC_CHANNEL0=y -# CONFIG_RT_USING_DC_CHANNEL1 is not set +CONFIG_RT_USING_DC_CHANNEL1=y # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set @@ -1279,6 +1293,7 @@ CONFIG_TARGET_E2000Q=y # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="e2000" CONFIG_TARGET_TYPE_NAME="q" CONFIG_SOC_CORE_NUM=4 @@ -1287,7 +1302,6 @@ CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 CONFIG_TARGET_E2000=y -# CONFIG_USE_SPINLOCK is not set CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set # CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set @@ -1310,7 +1324,6 @@ CONFIG_E2000Q_DEMO_BOARD=y # # IO mux configuration when board start up # -# CONFIG_FIREFLY_DEMO_BOARD is not set # CONFIG_CUS_DEMO_BOARD is not set # diff --git a/bsp/phytium/aarch32/configs/e2000q_demo_rtthread.h b/bsp/phytium/aarch32/configs/e2000q_demo_rtthread.h index 17213c998f4..39523811025 100644 --- a/bsp/phytium/aarch32/configs/e2000q_demo_rtthread.h +++ b/bsp/phytium/aarch32/configs/e2000q_demo_rtthread.h @@ -394,7 +394,11 @@ #define RT_USING_UART1 #define BSP_USING_SPI #define RT_USING_SPIM0 +#define BSP_USING_CAN #define BSP_USING_GPIO +#define BSP_USING_QSPI +#define RT_USING_QSPI0 +#define USING_QSPI_CHANNEL0 #define BSP_USING_ETH #define RT_LWIP_PBUF_POOL_BUFSIZE 1700 #define BSP_USING_PWM @@ -403,8 +407,15 @@ #define I2C_USE_MIO #define RT_USING_MIO0 #define RT_USING_MIO1 +#define BSP_USING_SDIF +#define BSP_USING_SDCARD_FATFS +#define USING_SDIF0 +#define USE_SDIF0_EMMC +#define USING_SDIF1 +#define USE_SDIF1_TF #define BSP_USING_DC #define RT_USING_DC_CHANNEL0 +#define RT_USING_DC_CHANNEL1 /* Board extended module Drivers */ diff --git a/bsp/phytium/aarch32/configs/phytium_pi_rtsmart b/bsp/phytium/aarch32/configs/phytium_pi_rtsmart index 6d97a19f493..a1e4572046b 100644 --- a/bsp/phytium/aarch32/configs/phytium_pi_rtsmart +++ b/bsp/phytium/aarch32/configs/phytium_pi_rtsmart @@ -162,6 +162,7 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 # CONFIG_RT_DFS_ELM_USE_EXFAT is not set CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +CONFIG_RT_USING_DFS_PTYFS=y # CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_TMPFS is not set CONFIG_RT_USING_DFS_MQUEUE=y @@ -192,8 +193,6 @@ CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=1024 -CONFIG_RT_USING_TTY=y -# CONFIG_RT_TTY_DEBUG is not set CONFIG_RT_USING_CAN=y # CONFIG_RT_CAN_USING_HDR is not set CONFIG_RT_CAN_USING_CANFD=y @@ -420,10 +419,11 @@ CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 CONFIG_LWP_TID_MAX_NR=64 CONFIG_LWP_ENABLE_ASID=y CONFIG_RT_LWP_SHM_MAX_NR=64 -# CONFIG_LWP_UNIX98_PTY is not set CONFIG_RT_USING_LDSO=y # CONFIG_ELF_DEBUG_ENABLE is not set # CONFIG_ELF_LOAD_RANDOMIZE is not set +CONFIG_LWP_USING_TERMINAL=y +CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # Memory management @@ -1249,9 +1249,16 @@ CONFIG_RT_USING_SPIM0=y # CONFIG_RT_USING_SPIM1 is not set # CONFIG_RT_USING_SPIM2 is not set # CONFIG_RT_USING_SPIM3 is not set -# CONFIG_BSP_USING_CAN is not set +CONFIG_BSP_USING_CAN=y +# CONFIG_RT_USING_CANFD is not set +# CONFIG_RT_USING_FILTER is not set +CONFIG_RT_USING_CAN0=y +CONFIG_RT_USING_CAN1=y CONFIG_BSP_USING_GPIO=y -# CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_QSPI=y +CONFIG_RT_USING_QSPI0=y +CONFIG_USING_QSPI_CHANNEL0=y +# CONFIG_USING_QSPI_CHANNEL1 is not set CONFIG_BSP_USING_ETH=y CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 CONFIG_BSP_USING_PWM=y @@ -1282,7 +1289,14 @@ CONFIG_RT_USING_MIO1=y # CONFIG_RT_USING_MIO14 is not set # CONFIG_RT_USING_MIO15 is not set # CONFIG_I2C_USE_CONTROLLER is not set -# CONFIG_BSP_USING_SDIF is not set +CONFIG_BSP_USING_SDIF=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIF0 is not set +# CONFIG_USE_SDIF0_TF is not set +# CONFIG_USE_SDIF0_EMMC is not set +CONFIG_USING_SDIF1=y +CONFIG_USE_SDIF1_TF=y +# CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y CONFIG_RT_USING_DC_CHANNEL0=y # CONFIG_RT_USING_DC_CHANNEL1 is not set @@ -1309,6 +1323,7 @@ CONFIG_TARGET_PHYTIUMPI=y # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="phytiumpi" CONFIG_SOC_CORE_NUM=4 CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000 @@ -1316,7 +1331,6 @@ CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 CONFIG_TARGET_E2000=y -# CONFIG_USE_SPINLOCK is not set CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set # CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set diff --git a/bsp/phytium/aarch32/configs/phytium_pi_rtsmart.h b/bsp/phytium/aarch32/configs/phytium_pi_rtsmart.h index 37466dda602..487404da67e 100644 --- a/bsp/phytium/aarch32/configs/phytium_pi_rtsmart.h +++ b/bsp/phytium/aarch32/configs/phytium_pi_rtsmart.h @@ -115,6 +115,7 @@ #define RT_DFS_ELM_REENTRANT #define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS +#define RT_USING_DFS_PTYFS #define RT_USING_DFS_MQUEUE #define RT_USING_PAGECACHE @@ -138,7 +139,6 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 1024 -#define RT_USING_TTY #define RT_USING_CAN #define RT_CAN_USING_CANFD #define RT_USING_I2C @@ -282,6 +282,8 @@ #define LWP_ENABLE_ASID #define RT_LWP_SHM_MAX_NR 64 #define RT_USING_LDSO +#define LWP_USING_TERMINAL +#define LWP_PTY_MAX_PARIS_LIMIT 64 /* Memory management */ @@ -422,7 +424,13 @@ #define RT_USING_UART1 #define BSP_USING_SPI #define RT_USING_SPIM0 +#define BSP_USING_CAN +#define RT_USING_CAN0 +#define RT_USING_CAN1 #define BSP_USING_GPIO +#define BSP_USING_QSPI +#define RT_USING_QSPI0 +#define USING_QSPI_CHANNEL0 #define BSP_USING_ETH #define RT_LWIP_PBUF_POOL_BUFSIZE 1700 #define BSP_USING_PWM @@ -431,6 +439,10 @@ #define I2C_USE_MIO #define RT_USING_MIO0 #define RT_USING_MIO1 +#define BSP_USING_SDIF +#define BSP_USING_SDCARD_FATFS +#define USING_SDIF1 +#define USE_SDIF1_TF #define BSP_USING_DC #define RT_USING_DC_CHANNEL0 diff --git a/bsp/phytium/aarch32/configs/phytium_pi_rtthread b/bsp/phytium/aarch32/configs/phytium_pi_rtthread index 5a4ca4888ba..a3f2877cdc2 100644 --- a/bsp/phytium/aarch32/configs/phytium_pi_rtthread +++ b/bsp/phytium/aarch32/configs/phytium_pi_rtthread @@ -1219,9 +1219,16 @@ CONFIG_RT_USING_SPIM0=y # CONFIG_RT_USING_SPIM1 is not set # CONFIG_RT_USING_SPIM2 is not set # CONFIG_RT_USING_SPIM3 is not set -# CONFIG_BSP_USING_CAN is not set +CONFIG_BSP_USING_CAN=y +# CONFIG_RT_USING_CANFD is not set +# CONFIG_RT_USING_FILTER is not set +# CONFIG_RT_USING_CAN0 is not set +# CONFIG_RT_USING_CAN1 is not set CONFIG_BSP_USING_GPIO=y -# CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_QSPI=y +CONFIG_RT_USING_QSPI0=y +CONFIG_USING_QSPI_CHANNEL0=y +# CONFIG_USING_QSPI_CHANNEL1 is not set CONFIG_BSP_USING_ETH=y CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 CONFIG_BSP_USING_PWM=y @@ -1252,10 +1259,17 @@ CONFIG_RT_USING_MIO1=y # CONFIG_RT_USING_MIO14 is not set # CONFIG_RT_USING_MIO15 is not set # CONFIG_I2C_USE_CONTROLLER is not set -# CONFIG_BSP_USING_SDIF is not set +CONFIG_BSP_USING_SDIF=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIF0 is not set +# CONFIG_USE_SDIF0_TF is not set +# CONFIG_USE_SDIF0_EMMC is not set +CONFIG_USING_SDIF1=y +CONFIG_USE_SDIF1_TF=y +# CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y CONFIG_RT_USING_DC_CHANNEL0=y -# CONFIG_RT_USING_DC_CHANNEL1 is not set +CONFIG_RT_USING_DC_CHANNEL1=y # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set @@ -1279,6 +1293,7 @@ CONFIG_TARGET_PHYTIUMPI=y # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="phytiumpi" CONFIG_SOC_CORE_NUM=4 CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000 @@ -1286,7 +1301,6 @@ CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 CONFIG_TARGET_E2000=y -# CONFIG_USE_SPINLOCK is not set CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set # CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set @@ -1294,6 +1308,7 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # # Board Configuration # +# CONFIG_E2000D_DEMO_BOARD is not set CONFIG_BOARD_NAME="firefly" # CONFIG_USE_SPI_IOPAD is not set # CONFIG_USE_GPIO_IOPAD is not set diff --git a/bsp/phytium/aarch32/configs/phytium_pi_rtthread.h b/bsp/phytium/aarch32/configs/phytium_pi_rtthread.h index 137ebf33c2e..986c3bb5c87 100644 --- a/bsp/phytium/aarch32/configs/phytium_pi_rtthread.h +++ b/bsp/phytium/aarch32/configs/phytium_pi_rtthread.h @@ -394,7 +394,11 @@ #define RT_USING_UART1 #define BSP_USING_SPI #define RT_USING_SPIM0 +#define BSP_USING_CAN #define BSP_USING_GPIO +#define BSP_USING_QSPI +#define RT_USING_QSPI0 +#define USING_QSPI_CHANNEL0 #define BSP_USING_ETH #define RT_LWIP_PBUF_POOL_BUFSIZE 1700 #define BSP_USING_PWM @@ -403,8 +407,13 @@ #define I2C_USE_MIO #define RT_USING_MIO0 #define RT_USING_MIO1 +#define BSP_USING_SDIF +#define BSP_USING_SDCARD_FATFS +#define USING_SDIF1 +#define USE_SDIF1_TF #define BSP_USING_DC #define RT_USING_DC_CHANNEL0 +#define RT_USING_DC_CHANNEL1 /* Board extended module Drivers */ diff --git a/bsp/phytium/aarch32/rtconfig.h b/bsp/phytium/aarch32/rtconfig.h index 137ebf33c2e..986c3bb5c87 100644 --- a/bsp/phytium/aarch32/rtconfig.h +++ b/bsp/phytium/aarch32/rtconfig.h @@ -394,7 +394,11 @@ #define RT_USING_UART1 #define BSP_USING_SPI #define RT_USING_SPIM0 +#define BSP_USING_CAN #define BSP_USING_GPIO +#define BSP_USING_QSPI +#define RT_USING_QSPI0 +#define USING_QSPI_CHANNEL0 #define BSP_USING_ETH #define RT_LWIP_PBUF_POOL_BUFSIZE 1700 #define BSP_USING_PWM @@ -403,8 +407,13 @@ #define I2C_USE_MIO #define RT_USING_MIO0 #define RT_USING_MIO1 +#define BSP_USING_SDIF +#define BSP_USING_SDCARD_FATFS +#define USING_SDIF1 +#define USE_SDIF1_TF #define BSP_USING_DC #define RT_USING_DC_CHANNEL0 +#define RT_USING_DC_CHANNEL1 /* Board extended module Drivers */ diff --git a/bsp/phytium/aarch64/.config b/bsp/phytium/aarch64/.config index 60c3f9756e5..a4eb4a3fec9 100644 --- a/bsp/phytium/aarch64/.config +++ b/bsp/phytium/aarch64/.config @@ -1279,7 +1279,12 @@ CONFIG_RT_USING_MIO10=y # CONFIG_RT_USING_MIO14 is not set # CONFIG_RT_USING_MIO15 is not set # CONFIG_I2C_USE_CONTROLLER is not set -# CONFIG_BSP_USING_SDIF is not set +CONFIG_BSP_USING_SDIF=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIF0 is not set +CONFIG_USING_SDIF1=y +CONFIG_USE_SDIF1_TF=y +# CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y # CONFIG_RT_USING_DC_CHANNEL0 is not set # CONFIG_RT_USING_DC_CHANNEL1 is not set @@ -1308,6 +1313,7 @@ CONFIG_TARGET_PHYTIUMPI=y # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="phytiumpi" CONFIG_SOC_CORE_NUM=4 CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000 @@ -1315,7 +1321,6 @@ CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 CONFIG_TARGET_E2000=y -# CONFIG_USE_SPINLOCK is not set CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set # CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set diff --git a/bsp/phytium/aarch64/applications/mnt.c b/bsp/phytium/aarch64/applications/mnt.c deleted file mode 100644 index 202f29ed894..00000000000 --- a/bsp/phytium/aarch64/applications/mnt.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Email: opensource_embedded@phytium.com.cn - * - * Change Logs: - * Date Author Notes - * 2023-04-27 huanghe first version - * 2023-07-14 liqiaozhong add SD file sys mount func - * - */ -#include -#if defined(RT_USING_DFS) -#include - -#include -#include - -static int ram_disk_mount(const char *mount_point) -{ -#ifdef RT_USING_DFS_RAMFS - extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size); - - rt_uint8_t *pool = RT_NULL; - rt_size_t size = 8 * 1024 * 1024; - rt_err_t err = RT_EOK; - - pool = rt_malloc(size); - if (pool == RT_NULL) - { - LOG_E("Malloc fail!"); - } - - err = dfs_mount(RT_NULL, mount_point, "ram", 0, (const void *)dfs_ramfs_create(pool, size)); - if (err == RT_EOK) - { - LOG_I("RAM file system initializated!"); - } - else - { - LOG_E("RAM file system initializate failed!, err = %d", err); - } -#endif - - return RT_EOK; -} - -#ifdef BSP_USING_SDCARD_FATFS -extern void fsdif_change(void); -static int sd_disk_try_mount(char *device_name, char *mount_point, char *fs_type_name, int mkfs_count) -{ - struct statfs fs_stat; - int rc = 0; - - LOG_I("mount(\"%s\",\"%s\",\"%s\");", device_name, mount_point, fs_type_name); - - if (rt_device_find(device_name) == NULL) - { - LOG_I("%s not find!!!", device_name); - return -RT_EIO; - } - - mkdir(mount_point, 0); -_remount: - rc = dfs_mount(device_name, mount_point, fs_type_name, 0, 0); - if (rc == 0) - { - LOG_I("mounted %s on %s", device_name, mount_point); - if (dfs_statfs(mount_point, &fs_stat) >= 0) - { - LOG_I("%s size:%d, total: %d, free: %d", mount_point, - fs_stat.f_bsize, fs_stat.f_blocks, fs_stat.f_bfree); - } - } - else - { - if (mkfs_count > 0) - { - /* LOG_I("[%s]try mkfs -t %s %s ", mkfs_count, fs_type_name, device_name); - dfs_mkfs(fs_type_name, device_name); */ - mkfs_count--; - LOG_E("%s is not in %s, please format first !!!", device_name, fs_type_name); - goto _remount; - } - - LOG_I("mount failed :%d ", rc); - return -RT_EIO; - } - - return RT_EOK; -} - -static void sd_filesytem_task_entry(void *parameter) -{ - int result; - LOG_D("sdio host change: %d", change); - mmcsd_wait_cd_changed(0); /* clear */ - fsdif_change(); /* send cd change to host */ - - /* block until plug/unplug event happens */ - result = mmcsd_wait_cd_changed(RT_WAITING_FOREVER); - if (result == MMCSD_HOST_PLUGED) - { - rt_kprintf("mmcsd change pluged \n"); - /* mount sdcard partition as / */ - if (RT_EOK == sd_disk_try_mount(BSP_USING_SDCARD_PARTITION, "/", "elm", 0)) - { - ram_disk_mount("/ram"); /* mount ramdisk if configured */ - } - } -} - -int filesystem_mount(void) -{ - rt_thread_t tid; - tid = rt_thread_create("sd_filesytem", sd_filesytem_task_entry, - RT_NULL, - 4096, - RT_THREAD_PRIORITY_MAX - 2, 20); - if (tid != RT_NULL) - { - rt_thread_startup(tid); - } - else - { - LOG_E("create sd mount task error!"); - } - - return RT_EOK; -} -INIT_APP_EXPORT(filesystem_mount); - -#else -static int filesystem_mount(void) -{ - return ram_disk_mount("/"); /* mount ramdisk as / */ -} -INIT_ENV_EXPORT(filesystem_mount); -#endif // #ifdef BSP_USING_SDCARD_FATFS -#endif // #if defined(RT_USING_DFS) \ No newline at end of file diff --git a/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart b/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart index 41262aded0e..8f31850ed99 100644 --- a/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart +++ b/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart @@ -165,6 +165,7 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 # CONFIG_RT_DFS_ELM_USE_EXFAT is not set CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +CONFIG_RT_USING_DFS_PTYFS=y # CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_TMPFS is not set # CONFIG_RT_USING_DFS_MQUEUE is not set @@ -195,8 +196,6 @@ CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 -CONFIG_RT_USING_TTY=y -# CONFIG_RT_TTY_DEBUG is not set CONFIG_RT_USING_CAN=y CONFIG_RT_CAN_USING_HDR=y CONFIG_RT_CAN_USING_CANFD=y @@ -385,7 +384,35 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set CONFIG_RT_LWIP_USING_PING=y # CONFIG_LWIP_USING_DHCPD is not set -# CONFIG_RT_LWIP_DEBUG is not set +CONFIG_RT_LWIP_DEBUG=y +# CONFIG_RT_LWIP_SYS_DEBUG is not set +# CONFIG_RT_LWIP_ETHARP_DEBUG is not set +# CONFIG_RT_LWIP_PPP_DEBUG is not set +# CONFIG_RT_LWIP_MEM_DEBUG is not set +# CONFIG_RT_LWIP_MEMP_DEBUG is not set +# CONFIG_RT_LWIP_PBUF_DEBUG is not set +# CONFIG_RT_LWIP_API_LIB_DEBUG is not set +# CONFIG_RT_LWIP_API_MSG_DEBUG is not set +# CONFIG_RT_LWIP_TCPIP_DEBUG is not set +CONFIG_RT_LWIP_NETIF_DEBUG=y +# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set +# CONFIG_RT_LWIP_DNS_DEBUG is not set +# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set +# CONFIG_RT_LWIP_DHCP_DEBUG is not set +# CONFIG_RT_LWIP_IP_DEBUG is not set +# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set +# CONFIG_RT_LWIP_ICMP_DEBUG is not set +# CONFIG_RT_LWIP_IGMP_DEBUG is not set +# CONFIG_RT_LWIP_UDP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set +# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set +# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set # CONFIG_RT_USING_AT is not set # @@ -419,10 +446,11 @@ CONFIG_RT_CH_MSG_MAX_NR=1024 CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 CONFIG_LWP_TID_MAX_NR=64 CONFIG_RT_LWP_SHM_MAX_NR=64 -# CONFIG_LWP_UNIX98_PTY is not set CONFIG_RT_USING_LDSO=y # CONFIG_ELF_DEBUG_ENABLE is not set # CONFIG_ELF_LOAD_RANDOMIZE is not set +CONFIG_LWP_USING_TERMINAL=y +CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # Memory management @@ -1273,9 +1301,9 @@ CONFIG_RT_USING_SPIM2=y CONFIG_RT_USING_SPIM3=y CONFIG_BSP_USING_CAN=y CONFIG_RT_USING_CANFD=y -# CONFIG_RT_USING_FILTER is not set +CONFIG_RT_USING_FILTER=y CONFIG_RT_USING_CAN0=y -# CONFIG_RT_USING_CAN1 is not set +CONFIG_RT_USING_CAN1=y CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_QSPI=y CONFIG_RT_USING_QSPI0=y @@ -1311,8 +1339,17 @@ CONFIG_I2C_USE_MIO=y # CONFIG_RT_USING_MIO14 is not set CONFIG_RT_USING_MIO15=y # CONFIG_I2C_USE_CONTROLLER is not set -# CONFIG_BSP_USING_SDIF is not set -# CONFIG_BSP_USING_DC is not set +CONFIG_BSP_USING_SDIF=y +CONFIG_BSP_USING_SDCARD_FATFS=y +CONFIG_USING_SDIF0=y +# CONFIG_USE_SDIF0_TF is not set +CONFIG_USE_SDIF0_EMMC=y +CONFIG_USING_SDIF1=y +CONFIG_USE_SDIF1_TF=y +# CONFIG_USE_SDIF1_EMMC is not set +CONFIG_BSP_USING_DC=y +# CONFIG_RT_USING_DC_CHANNEL0 is not set +CONFIG_RT_USING_DC_CHANNEL1=y # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set @@ -1338,6 +1375,7 @@ CONFIG_TARGET_E2000D=y # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="e2000" CONFIG_TARGET_TYPE_NAME="d" CONFIG_SOC_CORE_NUM=2 @@ -1346,7 +1384,6 @@ CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 CONFIG_TARGET_E2000=y -# CONFIG_USE_SPINLOCK is not set CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set # CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set diff --git a/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart.h b/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart.h index d3d78bf47a6..6fbe1140075 100644 --- a/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart.h +++ b/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart.h @@ -122,6 +122,7 @@ #define RT_DFS_ELM_REENTRANT #define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS +#define RT_USING_DFS_PTYFS #define RT_USING_PAGECACHE /* page cache config */ @@ -144,7 +145,6 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_TTY #define RT_USING_CAN #define RT_CAN_USING_HDR #define RT_CAN_USING_CANFD @@ -257,6 +257,8 @@ #define LWIP_SO_LINGER 0 #define LWIP_NETIF_LOOPBACK 0 #define RT_LWIP_USING_PING +#define RT_LWIP_DEBUG +#define RT_LWIP_NETIF_DEBUG /* Memory protection */ @@ -279,6 +281,8 @@ #define LWP_TID_MAX_NR 64 #define RT_LWP_SHM_MAX_NR 64 #define RT_USING_LDSO +#define LWP_USING_TERMINAL +#define LWP_PTY_MAX_PARIS_LIMIT 64 /* Memory management */ @@ -427,7 +431,9 @@ #define RT_USING_SPIM3 #define BSP_USING_CAN #define RT_USING_CANFD +#define RT_USING_FILTER #define RT_USING_CAN0 +#define RT_USING_CAN1 #define BSP_USING_GPIO #define BSP_USING_QSPI #define RT_USING_QSPI0 @@ -439,6 +445,14 @@ #define BSP_USING_I2C #define I2C_USE_MIO #define RT_USING_MIO15 +#define BSP_USING_SDIF +#define BSP_USING_SDCARD_FATFS +#define USING_SDIF0 +#define USE_SDIF0_EMMC +#define USING_SDIF1 +#define USE_SDIF1_TF +#define BSP_USING_DC +#define RT_USING_DC_CHANNEL1 /* Board extended module Drivers */ diff --git a/bsp/phytium/aarch64/configs/e2000d_demo_rtthread b/bsp/phytium/aarch64/configs/e2000d_demo_rtthread index a2e42a4dab9..933708b82a8 100644 --- a/bsp/phytium/aarch64/configs/e2000d_demo_rtthread +++ b/bsp/phytium/aarch64/configs/e2000d_demo_rtthread @@ -41,7 +41,7 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y CONFIG_RT_KPRINTF_USING_LONGLONG=y CONFIG_RT_USING_DEBUG=y CONFIG_RT_DEBUGING_COLOR=y -CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_CONTEXT is not set # CONFIG_RT_DEBUGING_AUTO_INIT is not set # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set @@ -1283,7 +1283,14 @@ CONFIG_I2C_USE_MIO=y # CONFIG_RT_USING_MIO14 is not set CONFIG_RT_USING_MIO15=y # CONFIG_I2C_USE_CONTROLLER is not set -# CONFIG_BSP_USING_SDIF is not set +CONFIG_BSP_USING_SDIF=y +CONFIG_BSP_USING_SDCARD_FATFS=y +CONFIG_USING_SDIF0=y +# CONFIG_USE_SDIF0_TF is not set +CONFIG_USE_SDIF0_EMMC=y +CONFIG_USING_SDIF1=y +CONFIG_USE_SDIF1_TF=y +# CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y # CONFIG_RT_USING_DC_CHANNEL0 is not set CONFIG_RT_USING_DC_CHANNEL1=y @@ -1312,6 +1319,7 @@ CONFIG_TARGET_E2000D=y # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="e2000" CONFIG_TARGET_TYPE_NAME="d" CONFIG_SOC_CORE_NUM=2 @@ -1320,7 +1328,6 @@ CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 CONFIG_TARGET_E2000=y -# CONFIG_USE_SPINLOCK is not set CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set # CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set diff --git a/bsp/phytium/aarch64/configs/e2000d_demo_rtthread.h b/bsp/phytium/aarch64/configs/e2000d_demo_rtthread.h index 28e4797cf65..18021fbfc52 100644 --- a/bsp/phytium/aarch64/configs/e2000d_demo_rtthread.h +++ b/bsp/phytium/aarch64/configs/e2000d_demo_rtthread.h @@ -30,7 +30,6 @@ #define RT_KPRINTF_USING_LONGLONG #define RT_USING_DEBUG #define RT_DEBUGING_COLOR -#define RT_DEBUGING_CONTEXT /* Inter-Thread communication */ @@ -411,6 +410,12 @@ #define BSP_USING_I2C #define I2C_USE_MIO #define RT_USING_MIO15 +#define BSP_USING_SDIF +#define BSP_USING_SDCARD_FATFS +#define USING_SDIF0 +#define USE_SDIF0_EMMC +#define USING_SDIF1 +#define USE_SDIF1_TF #define BSP_USING_DC #define RT_USING_DC_CHANNEL1 diff --git a/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart b/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart index 5ab396ebda8..2365473cbe9 100644 --- a/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart +++ b/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart @@ -165,6 +165,7 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 # CONFIG_RT_DFS_ELM_USE_EXFAT is not set CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +CONFIG_RT_USING_DFS_PTYFS=y # CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_TMPFS is not set # CONFIG_RT_USING_DFS_MQUEUE is not set @@ -195,8 +196,6 @@ CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 -CONFIG_RT_USING_TTY=y -# CONFIG_RT_TTY_DEBUG is not set CONFIG_RT_USING_CAN=y CONFIG_RT_CAN_USING_HDR=y CONFIG_RT_CAN_USING_CANFD=y @@ -447,10 +446,11 @@ CONFIG_RT_CH_MSG_MAX_NR=1024 CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 CONFIG_LWP_TID_MAX_NR=64 CONFIG_RT_LWP_SHM_MAX_NR=64 -# CONFIG_LWP_UNIX98_PTY is not set CONFIG_RT_USING_LDSO=y # CONFIG_ELF_DEBUG_ENABLE is not set # CONFIG_ELF_LOAD_RANDOMIZE is not set +CONFIG_LWP_USING_TERMINAL=y +CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # Memory management @@ -1341,11 +1341,15 @@ CONFIG_RT_USING_MIO15=y # CONFIG_I2C_USE_CONTROLLER is not set CONFIG_BSP_USING_SDIF=y CONFIG_BSP_USING_SDCARD_FATFS=y -CONFIG_BSP_USING_SDCARD_PARTITION="sd0" -# CONFIG_USING_SDIF0 is not set +CONFIG_USING_SDIF0=y +# CONFIG_USE_SDIF0_TF is not set +CONFIG_USE_SDIF0_EMMC=y CONFIG_USING_SDIF1=y -# CONFIG_USING_EMMC is not set -# CONFIG_BSP_USING_DC is not set +CONFIG_USE_SDIF1_TF=y +# CONFIG_USE_SDIF1_EMMC is not set +CONFIG_BSP_USING_DC=y +# CONFIG_RT_USING_DC_CHANNEL0 is not set +CONFIG_RT_USING_DC_CHANNEL1=y # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set @@ -1371,6 +1375,7 @@ CONFIG_TARGET_E2000Q=y # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="e2000" CONFIG_TARGET_TYPE_NAME="q" CONFIG_SOC_CORE_NUM=4 @@ -1379,7 +1384,6 @@ CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 CONFIG_TARGET_E2000=y -# CONFIG_USE_SPINLOCK is not set CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set # CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set diff --git a/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart.h b/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart.h index f7e611a0182..fd88a047a80 100644 --- a/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart.h +++ b/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart.h @@ -122,6 +122,7 @@ #define RT_DFS_ELM_REENTRANT #define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS +#define RT_USING_DFS_PTYFS #define RT_USING_PAGECACHE /* page cache config */ @@ -144,7 +145,6 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_TTY #define RT_USING_CAN #define RT_CAN_USING_HDR #define RT_CAN_USING_CANFD @@ -281,6 +281,8 @@ #define LWP_TID_MAX_NR 64 #define RT_LWP_SHM_MAX_NR 64 #define RT_USING_LDSO +#define LWP_USING_TERMINAL +#define LWP_PTY_MAX_PARIS_LIMIT 64 /* Memory management */ @@ -445,8 +447,12 @@ #define RT_USING_MIO15 #define BSP_USING_SDIF #define BSP_USING_SDCARD_FATFS -#define BSP_USING_SDCARD_PARTITION "sd0" +#define USING_SDIF0 +#define USE_SDIF0_EMMC #define USING_SDIF1 +#define USE_SDIF1_TF +#define BSP_USING_DC +#define RT_USING_DC_CHANNEL1 /* Board extended module Drivers */ diff --git a/bsp/phytium/aarch64/configs/e2000q_demo_rtthread b/bsp/phytium/aarch64/configs/e2000q_demo_rtthread index 88cc33eca66..df126633630 100644 --- a/bsp/phytium/aarch64/configs/e2000q_demo_rtthread +++ b/bsp/phytium/aarch64/configs/e2000q_demo_rtthread @@ -41,7 +41,7 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y CONFIG_RT_KPRINTF_USING_LONGLONG=y CONFIG_RT_USING_DEBUG=y CONFIG_RT_DEBUGING_COLOR=y -CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_CONTEXT is not set # CONFIG_RT_DEBUGING_AUTO_INIT is not set # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set @@ -374,35 +374,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set CONFIG_RT_LWIP_USING_PING=y # CONFIG_LWIP_USING_DHCPD is not set -CONFIG_RT_LWIP_DEBUG=y -# CONFIG_RT_LWIP_SYS_DEBUG is not set -# CONFIG_RT_LWIP_ETHARP_DEBUG is not set -# CONFIG_RT_LWIP_PPP_DEBUG is not set -# CONFIG_RT_LWIP_MEM_DEBUG is not set -# CONFIG_RT_LWIP_MEMP_DEBUG is not set -# CONFIG_RT_LWIP_PBUF_DEBUG is not set -# CONFIG_RT_LWIP_API_LIB_DEBUG is not set -# CONFIG_RT_LWIP_API_MSG_DEBUG is not set -# CONFIG_RT_LWIP_TCPIP_DEBUG is not set -CONFIG_RT_LWIP_NETIF_DEBUG=y -# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set -# CONFIG_RT_LWIP_DNS_DEBUG is not set -# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set -# CONFIG_RT_LWIP_DHCP_DEBUG is not set -# CONFIG_RT_LWIP_IP_DEBUG is not set -# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set -# CONFIG_RT_LWIP_ICMP_DEBUG is not set -# CONFIG_RT_LWIP_IGMP_DEBUG is not set -# CONFIG_RT_LWIP_UDP_DEBUG is not set -# CONFIG_RT_LWIP_TCP_DEBUG is not set -# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set -# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set -# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set -# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set -# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set -# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set -# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set -# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set +# CONFIG_RT_LWIP_DEBUG is not set # CONFIG_RT_USING_AT is not set # @@ -1273,9 +1245,9 @@ CONFIG_RT_USING_SPIM2=y CONFIG_RT_USING_SPIM3=y CONFIG_BSP_USING_CAN=y CONFIG_RT_USING_CANFD=y -CONFIG_RT_USING_FILTER=y +# CONFIG_RT_USING_FILTER is not set CONFIG_RT_USING_CAN0=y -CONFIG_RT_USING_CAN1=y +# CONFIG_RT_USING_CAN1 is not set CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_QSPI=y CONFIG_RT_USING_QSPI0=y @@ -1313,13 +1285,15 @@ CONFIG_RT_USING_MIO15=y # CONFIG_I2C_USE_CONTROLLER is not set CONFIG_BSP_USING_SDIF=y CONFIG_BSP_USING_SDCARD_FATFS=y -CONFIG_BSP_USING_SDCARD_PARTITION="sd0" -# CONFIG_USING_SDIF0 is not set +CONFIG_USING_SDIF0=y +# CONFIG_USE_SDIF0_TF is not set +CONFIG_USE_SDIF0_EMMC=y CONFIG_USING_SDIF1=y -# CONFIG_USING_EMMC is not set +CONFIG_USE_SDIF1_TF=y +# CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y -CONFIG_RT_USING_DC_CHANNEL0=y -# CONFIG_RT_USING_DC_CHANNEL1 is not set +# CONFIG_RT_USING_DC_CHANNEL0 is not set +CONFIG_RT_USING_DC_CHANNEL1=y # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set @@ -1345,6 +1319,7 @@ CONFIG_TARGET_E2000Q=y # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="e2000" CONFIG_TARGET_TYPE_NAME="q" CONFIG_SOC_CORE_NUM=4 @@ -1353,7 +1328,6 @@ CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 CONFIG_TARGET_E2000=y -# CONFIG_USE_SPINLOCK is not set CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set # CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set diff --git a/bsp/phytium/aarch64/configs/e2000q_demo_rtthread.h b/bsp/phytium/aarch64/configs/e2000q_demo_rtthread.h index 8b384d856c5..fdce69de6c1 100644 --- a/bsp/phytium/aarch64/configs/e2000q_demo_rtthread.h +++ b/bsp/phytium/aarch64/configs/e2000q_demo_rtthread.h @@ -30,7 +30,6 @@ #define RT_KPRINTF_USING_LONGLONG #define RT_USING_DEBUG #define RT_DEBUGING_COLOR -#define RT_DEBUGING_CONTEXT /* Inter-Thread communication */ @@ -240,8 +239,6 @@ #define LWIP_SO_LINGER 0 #define LWIP_NETIF_LOOPBACK 0 #define RT_LWIP_USING_PING -#define RT_LWIP_DEBUG -#define RT_LWIP_NETIF_DEBUG /* Memory protection */ @@ -401,9 +398,7 @@ #define RT_USING_SPIM3 #define BSP_USING_CAN #define RT_USING_CANFD -#define RT_USING_FILTER #define RT_USING_CAN0 -#define RT_USING_CAN1 #define BSP_USING_GPIO #define BSP_USING_QSPI #define RT_USING_QSPI0 @@ -417,10 +412,12 @@ #define RT_USING_MIO15 #define BSP_USING_SDIF #define BSP_USING_SDCARD_FATFS -#define BSP_USING_SDCARD_PARTITION "sd0" +#define USING_SDIF0 +#define USE_SDIF0_EMMC #define USING_SDIF1 +#define USE_SDIF1_TF #define BSP_USING_DC -#define RT_USING_DC_CHANNEL0 +#define RT_USING_DC_CHANNEL1 /* Board extended module Drivers */ diff --git a/bsp/phytium/aarch64/configs/phytium_pi_rtsmart b/bsp/phytium/aarch64/configs/phytium_pi_rtsmart index fb8c15b393b..a7ac979bcc8 100644 --- a/bsp/phytium/aarch64/configs/phytium_pi_rtsmart +++ b/bsp/phytium/aarch64/configs/phytium_pi_rtsmart @@ -165,6 +165,7 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 # CONFIG_RT_DFS_ELM_USE_EXFAT is not set CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set +CONFIG_RT_USING_DFS_PTYFS=y # CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_TMPFS is not set # CONFIG_RT_USING_DFS_MQUEUE is not set @@ -195,8 +196,6 @@ CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 -CONFIG_RT_USING_TTY=y -# CONFIG_RT_TTY_DEBUG is not set CONFIG_RT_USING_CAN=y # CONFIG_RT_CAN_USING_HDR is not set CONFIG_RT_CAN_USING_CANFD=y @@ -419,10 +418,11 @@ CONFIG_RT_CH_MSG_MAX_NR=1024 CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 CONFIG_LWP_TID_MAX_NR=64 CONFIG_RT_LWP_SHM_MAX_NR=64 -# CONFIG_LWP_UNIX98_PTY is not set CONFIG_RT_USING_LDSO=y # CONFIG_ELF_DEBUG_ENABLE is not set # CONFIG_ELF_LOAD_RANDOMIZE is not set +CONFIG_LWP_USING_TERMINAL=y +CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # Memory management @@ -1307,8 +1307,17 @@ CONFIG_RT_USING_MIO10=y # CONFIG_RT_USING_MIO14 is not set # CONFIG_RT_USING_MIO15 is not set # CONFIG_I2C_USE_CONTROLLER is not set -# CONFIG_BSP_USING_SDIF is not set -# CONFIG_BSP_USING_DC is not set +CONFIG_BSP_USING_SDIF=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIF0 is not set +# CONFIG_USE_SDIF0_TF is not set +# CONFIG_USE_SDIF0_EMMC is not set +CONFIG_USING_SDIF1=y +CONFIG_USE_SDIF1_TF=y +# CONFIG_USE_SDIF1_EMMC is not set +CONFIG_BSP_USING_DC=y +CONFIG_RT_USING_DC_CHANNEL0=y +CONFIG_RT_USING_DC_CHANNEL1=y # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set @@ -1334,6 +1343,7 @@ CONFIG_TARGET_PHYTIUMPI=y # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="phytiumpi" CONFIG_SOC_CORE_NUM=4 CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000 @@ -1341,7 +1351,6 @@ CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 CONFIG_TARGET_E2000=y -# CONFIG_USE_SPINLOCK is not set CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set # CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set diff --git a/bsp/phytium/aarch64/configs/phytium_pi_rtsmart.h b/bsp/phytium/aarch64/configs/phytium_pi_rtsmart.h index c9dd1d64180..cfdbf6208d8 100644 --- a/bsp/phytium/aarch64/configs/phytium_pi_rtsmart.h +++ b/bsp/phytium/aarch64/configs/phytium_pi_rtsmart.h @@ -122,6 +122,7 @@ #define RT_DFS_ELM_REENTRANT #define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS +#define RT_USING_DFS_PTYFS #define RT_USING_PAGECACHE /* page cache config */ @@ -144,7 +145,6 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_TTY #define RT_USING_CAN #define RT_CAN_USING_CANFD #define RT_USING_I2C @@ -278,6 +278,8 @@ #define LWP_TID_MAX_NR 64 #define RT_LWP_SHM_MAX_NR 64 #define RT_USING_LDSO +#define LWP_USING_TERMINAL +#define LWP_PTY_MAX_PARIS_LIMIT 64 /* Memory management */ @@ -438,6 +440,13 @@ #define RT_USING_MIO1 #define RT_USING_MIO2 #define RT_USING_MIO10 +#define BSP_USING_SDIF +#define BSP_USING_SDCARD_FATFS +#define USING_SDIF1 +#define USE_SDIF1_TF +#define BSP_USING_DC +#define RT_USING_DC_CHANNEL0 +#define RT_USING_DC_CHANNEL1 /* Board extended module Drivers */ diff --git a/bsp/phytium/aarch64/configs/phytium_pi_rtthread b/bsp/phytium/aarch64/configs/phytium_pi_rtthread index 60c3f9756e5..7e13aa1df4e 100644 --- a/bsp/phytium/aarch64/configs/phytium_pi_rtthread +++ b/bsp/phytium/aarch64/configs/phytium_pi_rtthread @@ -1279,7 +1279,14 @@ CONFIG_RT_USING_MIO10=y # CONFIG_RT_USING_MIO14 is not set # CONFIG_RT_USING_MIO15 is not set # CONFIG_I2C_USE_CONTROLLER is not set -# CONFIG_BSP_USING_SDIF is not set +CONFIG_BSP_USING_SDIF=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIF0 is not set +# CONFIG_USE_SDIF0_TF is not set +# CONFIG_USE_SDIF0_EMMC is not set +CONFIG_USING_SDIF1=y +CONFIG_USE_SDIF1_TF=y +# CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y # CONFIG_RT_USING_DC_CHANNEL0 is not set # CONFIG_RT_USING_DC_CHANNEL1 is not set @@ -1308,6 +1315,7 @@ CONFIG_TARGET_PHYTIUMPI=y # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="phytiumpi" CONFIG_SOC_CORE_NUM=4 CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000 @@ -1315,7 +1323,6 @@ CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 CONFIG_TARGET_E2000=y -# CONFIG_USE_SPINLOCK is not set CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set # CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set diff --git a/bsp/phytium/aarch64/configs/phytium_pi_rtthread.h b/bsp/phytium/aarch64/configs/phytium_pi_rtthread.h index f53549b1655..90c33ed22b1 100644 --- a/bsp/phytium/aarch64/configs/phytium_pi_rtthread.h +++ b/bsp/phytium/aarch64/configs/phytium_pi_rtthread.h @@ -410,6 +410,10 @@ #define RT_USING_MIO1 #define RT_USING_MIO2 #define RT_USING_MIO10 +#define BSP_USING_SDIF +#define BSP_USING_SDCARD_FATFS +#define USING_SDIF1 +#define USE_SDIF1_TF #define BSP_USING_DC /* Board extended module Drivers */ diff --git a/bsp/phytium/aarch64/rtconfig.h b/bsp/phytium/aarch64/rtconfig.h index f53549b1655..90c33ed22b1 100644 --- a/bsp/phytium/aarch64/rtconfig.h +++ b/bsp/phytium/aarch64/rtconfig.h @@ -410,6 +410,10 @@ #define RT_USING_MIO1 #define RT_USING_MIO2 #define RT_USING_MIO10 +#define BSP_USING_SDIF +#define BSP_USING_SDCARD_FATFS +#define USING_SDIF1 +#define USE_SDIF1_TF #define BSP_USING_DC /* Board extended module Drivers */ diff --git a/bsp/phytium/board/board.c b/bsp/phytium/board/board.c index 44f252d6331..132c71d86bd 100644 --- a/bsp/phytium/board/board.c +++ b/bsp/phytium/board/board.c @@ -21,6 +21,7 @@ #include #include /* TODO: why need application space when RT_SMART off */ #include +#include "phytium_interrupt.h" #ifdef RT_USING_SMART #include @@ -157,7 +158,7 @@ void rt_hw_board_aarch64_init(void) rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif - rt_hw_interrupt_init(); + phytium_interrupt_init(); rt_hw_gtimer_init(); diff --git a/bsp/phytium/board/phytium_cpu.c b/bsp/phytium/board/phytium_cpu.c index e7655b7e44b..cd9fcbabfd1 100644 --- a/bsp/phytium/board/phytium_cpu.c +++ b/bsp/phytium/board/phytium_cpu.c @@ -20,9 +20,6 @@ #include "phytium_cpu.h" - -#if defined(TARGET_ARMV8_AARCH64) - /** @name: phytium_cpu_id_mapping @msg: Map Phytium CPU ID @@ -33,7 +30,6 @@ int phytium_cpu_id_mapping(int cpu_id) { #if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI) -#if RT_CPUS_NR <= 2 switch (cpu_id) { case 0: @@ -52,9 +48,6 @@ int phytium_cpu_id_mapping(int cpu_id) #else return (int)cpu_id; #endif -#else - return (int)cpu_id; -#endif } int rt_hw_cpu_id(void) @@ -70,44 +63,7 @@ int rt_hw_cpu_id(void) return phytium_cpu_id_mapping(cpu_id); } -#else - -int phytium_cpu_id_mapping(int cpu_id) -{ -#if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI) - switch (cpu_id) - { - case 0: - return 2; - case 1: - return 3; - case 2: - return 0; - case 3: - return 1; - default: - RT_ASSERT(0); - return 0; - break; - } -#else - return (int)cpu_id; -#endif -} - -int rt_hw_cpu_id(void) -{ - FError ret; - u32 cpu_id; - ret = GetCpuId(&cpu_id); - - if (ret != ERR_SUCCESS) - { - RT_ASSERT(0); - } - - return phytium_cpu_id_mapping(cpu_id); -} +#if defined(TARGET_ARMV8_AARCH32) rt_uint64_t get_main_cpu_affval(void) { diff --git a/bsp/phytium/board/phytium_cpu.h b/bsp/phytium/board/phytium_cpu.h index 65fd20f6646..15b9e40f517 100644 --- a/bsp/phytium/board/phytium_cpu.h +++ b/bsp/phytium/board/phytium_cpu.h @@ -48,17 +48,12 @@ rt_inline rt_uint32_t platform_get_gic_dist_base(void) /* the basic constants and interfaces needed by gic */ rt_inline rt_uint32_t platform_get_gic_redist_base(void) { -#if RT_CPUS_NR <= 2 - return GICV3_RD_BASE_ADDR + 2 * GICV3_RD_OFFSET; -#else - return GICV3_RD_BASE_ADDR; -#endif return 0; } rt_inline rt_uint32_t platform_get_gic_cpu_base(void) { - return 0U; /* unused in gicv3 */ + return 0; /* unused in gicv3 */ } #endif @@ -66,6 +61,4 @@ rt_inline rt_uint32_t platform_get_gic_cpu_base(void) int phytium_cpu_id_mapping(int cpu_id); - - #endif // ! diff --git a/bsp/phytium/board/secondary_cpu.c b/bsp/phytium/board/secondary_cpu.c index 1a9d03cac4f..75e1eed1687 100644 --- a/bsp/phytium/board/secondary_cpu.c +++ b/bsp/phytium/board/secondary_cpu.c @@ -40,6 +40,7 @@ rt_uint64_t rt_cpu_mpidr_early[] = { + #if defined(TARGET_E2000D) [0] = 0x80000200, [1] = 0x80000201, @@ -78,7 +79,7 @@ void rt_hw_secondary_cpu_up(void) { continue; } - cpu_mask = 1 << phytium_cpu_id_mapping(i); + cpu_mask = 1<list device +device type ref count +---------------- -------------------- ---------- +sd10 Block Device 0 --> SD1 的第一个分区 +sd1 Block Device 1 --> SD1 +sd0 Block Device 1 +zero Miscellaneous Device 0 +urandom Miscellaneous Device 0 +random Miscellaneous Device 0 +null Miscellaneous Device 0 +e0 Network Interface 1 +SPI3 SPI Bus 0 +SPI2 SPI Bus 0 +SPI1 SPI Bus 0 +SPI0 SPI Bus 0 +PWM6 PWM Device 0 +MIO15 I2C Bus 0 +DC1 Graphic Device 0 +uart1 Character Device 2 +uart0 Character Device 0 +QSPI0 SPI Bus 0 +CAN0 CAN Device 0 +``` + +## 制作 SD 文件系统 + +- 如果之前 SD 卡里没有 FAT32 文件系统，自动挂载可能不会成功，需要启动 RT-Thread 后格式化一个 SD 设备，然后 mount + +``` +msh />mkfs sd1 / elm +msh />mount sd1 / elm +mount device sd1(elm) onto / ... succeed! +``` + +- 文件系统制作好后，下次启动会自动挂载成根目录 + +## 使用 SD 文件系统 + +- 参考[RT-Thread 的文件系统使用说明](https://www.rt-thread.org/document/api/group___d_f_s.html) \ No newline at end of file diff --git a/bsp/phytium/doc/use_phytium_pi_sd_image.md b/bsp/phytium/doc/use_phytium_pi_sd_image.md index c3233221469..0f8ca8db065 100644 --- a/bsp/phytium/doc/use_phytium_pi_sd_image.md +++ b/bsp/phytium/doc/use_phytium_pi_sd_image.md @@ -3,7 +3,6 @@ > 本文主要介绍如何在飞腾派中进行 RT-Thread 程序的开发和固化 - 飞腾派开发板是一款面向广大工程师和爱好者的开源硬件。主板处理器采用飞腾四核处理器,兼容 ARM v8 指令集,主频最高可达 1.8GHz -- 由于默认系统需要 16G 的空间，推荐使用 32G 的 SD 卡开发 RT-Thread 程序 ## 开发和调试程序 @@ -13,19 +12,19 @@ - 如果需要固化 RT-Thread 程序镜像在 SD 卡中，并实现开机自启动，可以使用下列的镜像，镜像中包含飞腾派的启动固件、飞腾派OS和一个 RT-Thread 的启动分区 -- [镜像下载链接](https://pan.baidu.com/s/1eL2ElKeVBU5GOyvzn2kl-A)，提取码：PIIM +- [镜像下载链接](https://pan.baidu.com/s/1asc3MdcIh71-fkjS6Rptvw)，提取码：PHYT - 下载之后解压，使用 sdcard-rtthread.img ``` - ----------------------------------------------------------------------------------- - | | | | - | 64MB (系统镜像) | 16G (Phytium Pi OS 根文件系统) | 4G (RT-Thread文件系统) | - | （无格式） | （ext4格式） | （fat32格式） | - ---------------------------------------------------------------------------------- + ------------------------------------------------------ + | | | + | 64MB (系统镜像) | 2G (RT-Thread文件系统) | + | （无格式） | （fat32格式） | + ----------------------------------------------------- ``` -- Windows 上使用 balenaEtcher 工具烧入一张 SD 卡（>= 32G），镜像的格式如下图所示，由3个分区组成，前 64MB 是二进制无格式的启动镜像，然后 16G 是 Phytium Pi OS 的根文件系统，格式为 ext4，最后 4G 是 RT-Thread 文件系统，格式为 fat32， +- Windows 上使用 balenaEtcher 工具烧入一张 SD 卡，镜像的格式如下图所示，由1个分区组成，前 64MB 是二进制无格式的启动镜像，后面 2G 是 RT-Thread 文件系统，格式为 fat32， - 在 linux 系统上，可以使用 dd 命令将镜像写入 SD 卡 (/dev/sdd) @@ -36,6 +35,7 @@ - SD 卡烧入完成之后插入飞腾派 SD 卡槽，重启飞腾派就会自动进入 RT-Thread 系统， ``` + PHYTIUM MCI: 0, PHYTIUM MCI: 1 Loading Environment from MMC... OK In: uart@2800d000 Out: uart@2800d000 @@ -44,95 +44,72 @@ scanning bus for devices... SATA link 0 timeout. AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl SATA mode - flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst + flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst SATA link 0 timeout. AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl SATA mode - flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst - Hit any key to stop autoboot: 0 - 739360 bytes read in 206 ms (3.4 MiB/s) + flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst + Hit any key to stop autoboot: 0 + 2740352 bytes read in 578 ms (4.5 MiB/s) ## Starting application at 0x80080000 ... \ | / - RT - Thread Operating System - / | \ 5.1.0 build Nov 9 2023 09:13:25 - 2006 - 2022 Copyright by RT-Thread team - do components initialization. - initialize rti_board_end:0 done - initialize dfs_init:0 done - initialize rt_work_sys_workqueue_init:0 done - initialize rt_mmcsd_core_init:0 done + / | \ 5.1.0 build Apr 9 2024 09:17:05 + 2006 - 2024 Copyright by RT-Thread team + lwIP-2.1.2 initialized! + [I/I2C] I2C bus [MIO15] registered + FXMAC OS Init Success! + Xmac e0 Initiailized! + Set netif e0 ip addr! + [E/drv] Auto negotiation is error. + FXMAC OS Init Success! + Xmac e1 Initiailized! + Set Xmac e1 ip addr! + Start Xmac NUM0 + Start Xmac NUM1 + [I/sal.skt] Socket Abstraction Layer initialize success. + msh />rt_device_find 0 + [I/SDIO] SD card capacity 31178752 KB. + found part[0], begin: 67108864, size: 2.0GB + [I/mnt.filesystem] sd00 mount to '/' + + msh />ls / + Directory /: + System Volume Inform + rtthread_a64.bin 2740352 + msh />df + disk free: 1.9 GB [ 4180704 block, 512 bytes per block ] + msh /> ``` -## 更新飞腾派 RT-Thread 镜像 - -- 有两种方式可以更新 SD 卡第三个分区中的 RT-Thread 镜像 -- 1. 将 SD 卡插入一台能识别第三个分区的电脑 (Ubuntu 系统能识别，Windows 可能不能识别)，直接将 RT-Thread 镜像复制入 SD 卡 -- 2. 可以通过 u-boot 上传 RT-Thread 镜像，然后保存在 SD 卡第三个分区中，注意保存文件的大小 (0xc0000)，要超过 tftpboot 加载的文件大小 - - ``` - Phytium-Pi#setenv ipaddr 192.168.4.20;setenv serverip 192.168.4.50;setenv gatewayip 192.168.4.1; - Phytium-Pi#tftpboot 0x90100000 rtthread_a64.bin - ethernet@3200c000: PHY present at 0 - ethernet@3200c000: Starting autonegotiation... - ethernet@3200c000: Autonegotiation complete - ethernet@3200c000: link up, 1000Mbps full-duplex (lpa: 0x2800) - ft sgmii speed 1000M! - Using ethernet@3200c000 device - TFTP from server 192.168.4.50; our IP address is 192.168.4.20 - Filename 'rtthread_a64.bin'. - Load address: 0x90100000 - Loading: ################################################################# - ################################################################# - ############### - 133.8 KiB/s - done - Bytes transferred = 739840 (b4a00 hex) - Phytium-Pi#fatls mmc 0:2 - rtthread-images/ - .Trash-1000/ - ram/ - System Volume Information/ - - 0 file(s), 4 dir(s) - - Phytium-Pi#fatwrite mmc 0:2 0x90100000 rtthread-images/rtthread_a64.bin 0xc0000 - 786432 bytes written in 398 ms (1.9 MiB/s) - Phytium-Pi#fatls mmc 0:2 rtthread-images - ./ - ../ - 786432 rtthread_a64.bin - 944384 rtsmart_a64.bin - 950828 rtsmart_a32.bin - 722580 rtthread_a32.bin - - 4 file(s), 2 dir(s) - - Phytium-Pi# - ``` ## 修改自启动的 RT-Thread 镜像 -- 通过在 u-boot 控制台修改 bootcmd，可以指定不同的 RT-Thread 镜像自启动，如下所示，指定启动 RT-Smart 镜像 `rtsmart_a64.bin` +- 通过在 u-boot 控制台修改 bootcmd，可以指定不同的 RT-Thread 镜像自启动，如下所示，指定启动 RT-Smart 镜像 `rtthread_a64.bin` - ``` - Phytium-Pi#printenv bootcmd - bootcmd=mw 0x32b301a8 0x275;mmc dev 0;mmc read 0x90000000 0x2000 0x10000;bootm 0x90000000#phytium - Phytium-Pi#setenv bootcmd "fatload mmc 0:2 0x80080000 rtthread-images/rtthread_a64.bin;dcache flush;go 0x80080000;" - Phytium-Pi#saveenv - ``` +``` +Phytium-Pi#printenv bootcmd +bootcmd=mw 0x32b301a8 0x275;mmc dev 0;mmc read 0x90000000 0x2000 0x10000;bootm 0x90000000#phytium +Phytium-Pi#setenv bootcmd "fatload mmc 0:1 0x80080000 rtthread_a64.bin;dcache flush;go 0x80080000;" +Phytium-Pi#saveenv +``` +## 在 RT-Thread 应用中访问 SD 卡分区 -## 切换成 linux 开发模式 +- 如前面介绍的，参考 libraries/port/fboard_port/firefly/mnt_sdcard.c，启动后会将 SD 卡的第一个分区（2GB 大小）自动挂载到根目录下 -- 本文提供的 RT-Thread 开发镜像中，有一个 linux 系统，需要的时候可以修改 bootcmd，切换成自启动 linux 系统 +``` +[I/SDIO] SD card capacity 31178752 KB. +found part[0], begin: 67108864, size: 2.0GB +[I/mnt.filesystem] sd00 mount to '/' - ``` - Phytium-Pi#setenv bootcmd "mw 0x32b301a8 0x275;mmc dev 0;mmc read 0x90000000 0x2000 0x10000;bootm 0x90000000#phytium" - Phytium-Pi#saveenv - Saving Environment to MMC... Writing to MMC(0)... OK - ``` - -## 在 RT-Thread 应用中访问 SD 卡分区 +msh /> +msh />ls +Directory /: +rtthread_a64.bin 2740352 +msh />df +disk free: 1.9 GB [ 4180704 block, 512 bytes per block ] +msh /> +``` -- 如前面介绍的，RT-Thread 应用可以使用第二个分区，分区文件系统格式为 FAT32 -- 打开配置 BSP_USING_SDCARD_FATFS 后， RT-Thread / RT-Smart 启动过程中会将 SD 卡挂载为根目录，将配置 BSP_USING_SDCARD_PARTITION 设置为 `sd1`，指定第二个分区为 RT-Thread 根目录，启动后创建的文件都会使用这个 SD 分区 \ No newline at end of file +- 如果需要替换 SD 卡中的 RT-Thread 镜像，直接取下 SD 卡插入 Windows/Ubuntu PC 中进行替换即可 \ No newline at end of file diff --git a/bsp/phytium/libraries/SConscript b/bsp/phytium/libraries/SConscript index 63e8a1766e6..38576ed343a 100644 --- a/bsp/phytium/libraries/SConscript +++ b/bsp/phytium/libraries/SConscript @@ -49,6 +49,28 @@ if GetDepend(['TARGET_D2000']): src += Glob(cwd+'/port/soc_port/d2000/*.c') path += [PHYTIUM_SDK_DIR + '/soc/d2000'] +# board port +if GetDepend(['E2000D_DEMO_BOARD']): + path += cwd + '/fboard_port/e2000d_demo' + +if GetDepend(['E2000D_DEMO_BOARD']): + path += cwd + '/fboard_port/e2000q_demo' + +if GetDepend(['FIREFLY_DEMO_BOARD']): + path += cwd + '/fboard_port/firefly' + +if GetDepend(['BSP_USING_SDCARD_FATFS']): + if GetDepend(['E2000D_DEMO_BOARD']): + src += Glob(cwd + '/port/fboard_port/e2000d_demo/mnt_sdcard.c') + + if GetDepend(['E2000Q_DEMO_BOARD']): + src += Glob(cwd + '/port/fboard_port/e2000q_demo/mnt_sdcard.c') + + if GetDepend(['FIREFLY_DEMO_BOARD']): + src += Glob(cwd + '/port/fboard_port/firefly/mnt_sdcard.c') +else: + src += Glob(cwd + '/port/fboard_port/mnt_ramdisk.c') + # driver path += [PORT_DRV_DIR] @@ -148,7 +170,6 @@ src += Glob(cwd+'/port/fdriver_port/*.c') path += [cwd + '/port/fdriver_port'] ## fboard port -src += Glob(cwd+'/port/fboard_port/*.c') path += [cwd + '/port/fboard_port'] ## lwip port diff --git a/bsp/phytium/libraries/common/phytium_interrupt.c b/bsp/phytium/libraries/common/phytium_interrupt.c new file mode 100644 index 00000000000..0714c563f42 --- /dev/null +++ b/bsp/phytium/libraries/common/phytium_interrupt.c @@ -0,0 +1,150 @@ +#include "rtconfig.h" +#if defined(TARGET_ARMV8_AARCH64) +#include +#include +#include "interrupt.h" +#include "gic.h" +#include "gicv3.h" +#include "ioremap.h" +#include "phytium_cpu.h" +#include "ftypes.h" +#include "fparameters.h" + +struct arm_gic *phytium_gic_table; + +extern struct rt_irq_desc isr_table[MAX_HANDLERS]; + +int arm_gic_redist_address_set(rt_uint64_t index, rt_uint64_t redist_addr, int cpu_id) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + if (cpu_id == 0) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, &cpu_id, sizeof(cpu_id)); + } + + phytium_gic_table[index].redist_hw_base[cpu_id] = redist_addr; + + return 0; +} + +static int arm_gicv3_wait_rwp(rt_uint64_t index, rt_uint64_t irq) +{ + rt_uint64_t rwp_bit; + rt_uint64_t base; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + if (irq < 32) + { + rt_int32_t cpu_id = rt_hw_cpu_id(); + + base = phytium_gic_table[index].redist_hw_base[cpu_id]; + rwp_bit = GICR_CTLR_RWP; + } + else + { + base = phytium_gic_table[index].dist_hw_base; + rwp_bit = GICD_CTLR_RWP; + } + + while (HWREG32(base) & rwp_bit) + { + } + + return 0; +} + +int phytium_aarch64_arm_gic_redist_init() +{ + rt_uint64_t cpu_id = rt_hw_cpu_id(); + rt_uint64_t redist_base = phytium_gic_table[0].redist_hw_base[cpu_id]; + + /* redistributor enable */ + GIC_RDIST_WAKER(redist_base) &= ~(1 << 1); + while (GIC_RDIST_WAKER(redist_base) & (1 << 2)) + { + } + + /* Disable all sgi and ppi interrupt */ + GIC_RDISTSGI_ICENABLER0(redist_base) = 0xffffffff; + arm_gicv3_wait_rwp(0, 0); + + /* Clear all inetrrupt pending */ + GIC_RDISTSGI_ICPENDR0(redist_base) = 0xffffffff; + + /* the corresponding interrupt is Group 1 or Non-secure Group 1. */ + GIC_RDISTSGI_IGROUPR0(redist_base, 0) = 0xffffffff; + GIC_RDISTSGI_IGRPMODR0(redist_base, 0) = 0xffffffff; + + /* Configure default priorities for SGI 0:15 and PPI 16:31. */ + for (int i = 0; i < 32; i += 4) + { + GIC_RDISTSGI_IPRIORITYR(redist_base, i) = 0xa0a0a0a0U; + } + + /* Trigger level for PPI interrupts*/ + GIC_RDISTSGI_ICFGR1(redist_base) = 0; + + return 0; +} + +void phytium_interrupt_init(void) +{ + rt_uint64_t gic_cpu_base; + rt_uint64_t gic_dist_base; + rt_uint64_t gic_irq_start; + rt_uint64_t redist_addr; + + phytium_gic_table = (struct arm_gic *)arm_gic_get_gic_table_addr(); + /* initialize vector table */ + rt_hw_vector_init(); + + /* initialize exceptions table */ + rt_memset(isr_table, 0x00, sizeof(isr_table)); + +#if defined(RT_USING_SMART) + gic_dist_base = (rt_uint64_t)rt_ioremap((void *)platform_get_gic_dist_base(), 0x40000); + gic_cpu_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_cpu_base(), 0x1000); + redist_addr = (rt_uint64_t)rt_ioremap(GICV3_RD_BASE_ADDR, 4 * GICV3_RD_OFFSET); +#else + gic_dist_base = platform_get_gic_dist_base(); + gic_cpu_base = platform_get_gic_cpu_base(); + redist_addr = GICV3_RD_BASE_ADDR; +#endif + + gic_irq_start = 0; + arm_gic_dist_init(0, gic_dist_base, gic_irq_start); + arm_gic_cpu_init(0, gic_cpu_base); + arm_gic_redist_address_set(0, redist_addr + 2 * GICV3_RD_OFFSET, 0); + +#if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI) +#if RT_CPUS_NR == 2 + arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1); +#elif RT_CPUS_NR == 3 + arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1); + arm_gic_redist_address_set(0, redist_addr, 2); +#elif RT_CPUS_NR == 4 + arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1); + arm_gic_redist_address_set(0, redist_addr, 2); + arm_gic_redist_address_set(0, redist_addr + GICV3_RD_OFFSET, 3); +#endif +#else +#if defined(TARGET_E2000D) + rt_uint32_t cpu_offset = 2; +#endif +#if RT_CPUS_NR == 2 + arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1); +#elif RT_CPUS_NR == 3 + arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1); + arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2); +#elif RT_CPUS_NR == 4 + arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1); + arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2); + arm_gic_redist_address_set(0, redist_addr + (3 + cpu_offset) * GICV3_RD_OFFSET, 3); +#endif +#endif + + phytium_aarch64_arm_gic_redist_init(); +} +#endif diff --git a/bsp/phytium/libraries/common/phytium_interrupt.h b/bsp/phytium/libraries/common/phytium_interrupt.h new file mode 100644 index 00000000000..33cc0c3b1fe --- /dev/null +++ b/bsp/phytium/libraries/common/phytium_interrupt.h @@ -0,0 +1,17 @@ +#ifndef PHYTIUM_INTERRUPT_H +#define PHYTIUM_INTERRUPT_H + +#ifdef __cplusplus +extern "C" +{ +#endif +#include "rtconfig.h" +#if defined(TARGET_ARMV8_AARCH64) +void phytium_interrupt_init(void); + +int phytium_aarch64_arm_gic_redist_init(void); +#endif +#ifdef __cplusplus +} +#endif +#endif \ No newline at end of file diff --git a/bsp/phytium/libraries/drivers/Kconfig b/bsp/phytium/libraries/drivers/Kconfig index 361413c6b59..b49f464e531 100644 --- a/bsp/phytium/libraries/drivers/Kconfig +++ b/bsp/phytium/libraries/drivers/Kconfig @@ -228,25 +228,36 @@ menu "On-chip Peripheral Drivers" select RT_USING_DFS_ELMFAT default n - if BSP_USING_SDCARD_FATFS - config BSP_USING_SDCARD_PARTITION - string "Set SDCARD (FATFS) partition index" - default "sd0" - endif + config USING_SDIF0 + bool "Use SDIF0" + + if USING_SDIF0 + choice + prompt "Select SD0 Usage" + default USE_SDIF0_TF + config USE_SDIF0_TF + bool "SD0(TF)" - choice - prompt "Choose a card to mount" - default USING_SDIF1 + config USE_SDIF0_EMMC + bool "SD0(eMMC)" - config USING_SDIF0 - bool "Use SDIF0" + endchoice + endif - config USING_SDIF1 - bool "Use SDIF1" + config USING_SDIF1 + bool "Use SDIF1" - config USING_EMMC - bool "Use EMMC" - endchoice + if USING_SDIF1 + choice + prompt "Select SD1 Usage" + default USE_SDIF1_TF + config USE_SDIF1_TF + bool "SD1(TF)" + + config USE_SDIF1_EMMC + bool "SD1(eMMC)" + endchoice + endif endif diff --git a/bsp/phytium/libraries/drivers/drv_can.c b/bsp/phytium/libraries/drivers/drv_can.c index adc9d639f27..f531bcc0fd7 100644 --- a/bsp/phytium/libraries/drivers/drv_can.c +++ b/bsp/phytium/libraries/drivers/drv_can.c @@ -166,7 +166,7 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) struct phytium_can *drv_can; drv_can = (struct phytium_can *)can->parent.user_data; RT_ASSERT(drv_can != RT_NULL); - rt_uint32_t cpu_id; + rt_uint32_t cpu_id = rt_hw_cpu_id(); FCanIntrEventConfig intr_event; FError status = FT_SUCCESS; @@ -177,7 +177,6 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) switch (cmd) { case RT_DEVICE_CTRL_SET_INT: - GetCpuId(&cpu_id); rt_hw_interrupt_set_target_cpus(drv_can->can_handle.config.irq_num, cpu_id); argval = (rt_uint32_t) arg; /*Open different interrupts*/ @@ -329,7 +328,7 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) return RT_EOK; } -static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num) +static rt_ssize_t _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num) { RT_ASSERT(can); RT_ASSERT(buf); @@ -366,7 +365,7 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t return (FCanSend(&drv_can->can_handle, &can_frame) == RT_EOK) ? RT_EOK : -RT_ERROR; } -static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) +static rt_ssize_t _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) { RT_ASSERT(can); RT_ASSERT(buf); @@ -465,4 +464,4 @@ int rt_hw_can_init(void) return 0; } -INIT_BOARD_EXPORT(rt_hw_can_init); \ No newline at end of file +INIT_BOARD_EXPORT(rt_hw_can_init); diff --git a/bsp/phytium/libraries/drivers/drv_dc.h b/bsp/phytium/libraries/drivers/drv_dc.h index abc95393833..293dd7e5bc4 100644 --- a/bsp/phytium/libraries/drivers/drv_dc.h +++ b/bsp/phytium/libraries/drivers/drv_dc.h @@ -42,4 +42,4 @@ struct phytium_dc_bus } #endif -#endif /* __DRV_DC_H__ */ \ No newline at end of file +#endif /* __DRV_DC_H__ */ diff --git a/bsp/phytium/libraries/drivers/drv_gpio.c b/bsp/phytium/libraries/drivers/drv_gpio.c index 97271b8e638..ae5ed5762d8 100644 --- a/bsp/phytium/libraries/drivers/drv_gpio.c +++ b/bsp/phytium/libraries/drivers/drv_gpio.c @@ -63,10 +63,9 @@ extern FIOPadCtrl iopad_ctrl; /*******************************Api Functions*********************************/ static void FGpioOpsSetupCtrlIRQ(FGpio *ctrl) { - u32 cpu_id; + rt_uint32_t cpu_id = rt_hw_cpu_id(); u32 irq_num = ctrl->config.irq_num[0]; - GetCpuId(&cpu_id); LOG_D("In FGpioOpsSetupCtrlIRQ() -> cpu_id %d, irq_num %d\r\n", cpu_id, irq_num); rt_hw_interrupt_set_target_cpus(irq_num, cpu_id); rt_hw_interrupt_set_priority(irq_num, ctrl->config.irq_priority); /* setup interrupt */ @@ -78,10 +77,9 @@ static void FGpioOpsSetupCtrlIRQ(FGpio *ctrl) /* setup gpio pin interrupt */ static void FGpioOpsSetupPinIRQ(FGpio *ctrl, FGpioPin *const pin, FGpioOpsPinConfig *config) { - u32 cpu_id; + rt_uint32_t cpu_id = rt_hw_cpu_id(); u32 irq_num = ctrl->config.irq_num[pin->index.pin]; - GetCpuId(&cpu_id); LOG_D("in FGpioOpsSetupPinIRQ() -> cpu_id %d, irq_num %d", cpu_id, irq_num); rt_hw_interrupt_set_target_cpus(irq_num, cpu_id); rt_hw_interrupt_set_priority(irq_num, ctrl->config.irq_priority); /* setup interrupt */ @@ -186,7 +184,7 @@ void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value) FGpioSetOutputValue(pin_instance, (value == PIN_HIGH) ? FGPIO_PIN_HIGH : FGPIO_PIN_LOW); } -rt_int8_t drv_pin_read(struct rt_device *device, rt_base_t pin) +rt_ssize_t drv_pin_read(struct rt_device *device, rt_base_t pin) { u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin); u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin); @@ -195,11 +193,7 @@ rt_int8_t drv_pin_read(struct rt_device *device, rt_base_t pin) if (pin_instance == RT_NULL) { - rt_kprintf("Pin %d-%c-%d not set mode\n", - ctrl_id, - port_id == 0 ? 'a' : 'b', - pin_id); - return -RT_ERROR; + return -RT_EINVAL; } return FGpioGetInputValue(pin_instance) == FGPIO_PIN_HIGH ? PIN_HIGH : PIN_LOW; } @@ -229,19 +223,12 @@ rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_base_t pin, if (pin_config->en_irq) { FGpioSetInterruptMask(pin_instance, FALSE); - FGpioPinId pin_of_ctrl = - { - .ctrl = ctrl_id, - .port = FGPIO_PORT_A, - .pin = FGPIO_PIN_0 - }; - - if (FGPIO_IRQ_BY_CONTROLLER == FGpioGetPinIrqSourceType(pin_of_ctrl)) /* setup for ctrl report interrupt */ + if (FGPIO_IRQ_BY_CONTROLLER == FGpioGetPinIrqSourceType(*pin_instance)) /* setup for ctrl report interrupt */ { FGpioOpsSetupCtrlIRQ(instance); LOG_I("GPIO-%d report irq by controller", ctrl_id); } - else if (FGPIO_IRQ_BY_PIN == FGpioGetPinIrqSourceType(pin_of_ctrl)) + else if (FGPIO_IRQ_BY_PIN == FGpioGetPinIrqSourceType(*pin_instance)) { FGpioOpsSetupPinIRQ(instance, pin_instance, pin_config); LOG_I("GPIO-%d report irq by pin", ctrl_id); @@ -340,4 +327,4 @@ int ft_pin_init(void) rt_kprintf("Register pin with return: %d\n", ret); return ret; } -INIT_DEVICE_EXPORT(ft_pin_init); \ No newline at end of file +INIT_DEVICE_EXPORT(ft_pin_init); diff --git a/bsp/phytium/libraries/drivers/drv_gpio.h b/bsp/phytium/libraries/drivers/drv_gpio.h index 769a689af02..5fe55deac3c 100644 --- a/bsp/phytium/libraries/drivers/drv_gpio.h +++ b/bsp/phytium/libraries/drivers/drv_gpio.h @@ -17,4 +17,4 @@ /**************************** Type Definitions *******************************/ /************************** Function Prototypes ******************************/ -#endif \ No newline at end of file +#endif diff --git a/bsp/phytium/libraries/drivers/drv_i2c.c b/bsp/phytium/libraries/drivers/drv_i2c.c index 71b43ec2042..0ad78327006 100644 --- a/bsp/phytium/libraries/drivers/drv_i2c.c +++ b/bsp/phytium/libraries/drivers/drv_i2c.c @@ -26,6 +26,10 @@ #include #endif +/*Please define the length of the mem_addr of the device*/ +#ifndef FI2C_DEVICE_MEMADDR_LEN + #define FI2C_DEVICE_MEMADDR_LEN 1 +#endif #define FI2C_DEFAULT_ID 0 #define I2C_USE_MIO #if defined(I2C_USE_MIO) @@ -165,17 +169,22 @@ static rt_ssize_t i2c_master_xfer(struct rt_i2c_bus_device *device, struct rt_i2 RT_ASSERT(device); u32 ret; struct rt_i2c_msg *pmsg; + rt_ssize_t i; struct phytium_i2c_bus *i2c_bus; i2c_bus = (struct phytium_i2c_bus *)(device); - u8 mem_addr = msgs->buf[0]; + u32 mem_addr; - for (int i = 0; i < num; i++) + for (i = 0; i < num; i++) { - pmsg = i2c_bus->msg = &msgs[i]; + pmsg = &msgs[i]; + for (u32 j = 0; j i2c_handle.config.slave_addr = pmsg->addr; if (pmsg->flags & RT_I2C_RD) { - ret = FI2cMasterReadPoll(&i2c_bus->i2c_handle, mem_addr, 1, &pmsg->buf[0], sizeof(pmsg->buf)); + ret = FI2cMasterReadPoll(&i2c_bus->i2c_handle, mem_addr, FI2C_DEVICE_MEMADDR_LEN, &pmsg->buf[0], pmsg->len); if (ret != FI2C_SUCCESS) { LOG_E("I2C master read failed!\n"); @@ -184,7 +193,7 @@ static rt_ssize_t i2c_master_xfer(struct rt_i2c_bus_device *device, struct rt_i2 } else { - ret = FI2cMasterWritePoll(&i2c_bus->i2c_handle, mem_addr, 1, &pmsg->buf[1], sizeof(pmsg->buf) - 1); + ret = FI2cMasterWritePoll(&i2c_bus->i2c_handle, mem_addr, FI2C_DEVICE_MEMADDR_LEN, &pmsg->buf[FI2C_DEVICE_MEMADDR_LEN], pmsg->len); if (ret != FI2C_SUCCESS) { LOG_E("I2C master write failed!\n"); @@ -193,7 +202,7 @@ static rt_ssize_t i2c_master_xfer(struct rt_i2c_bus_device *device, struct rt_i2 } } - return RT_EOK; + return i; } static const struct rt_i2c_bus_device_ops _i2c_ops = @@ -403,4 +412,4 @@ int rt_hw_i2c_init(void) return 0; } -INIT_DEVICE_EXPORT(rt_hw_i2c_init); \ No newline at end of file +INIT_DEVICE_EXPORT(rt_hw_i2c_init); diff --git a/bsp/phytium/libraries/drivers/drv_log.h b/bsp/phytium/libraries/drivers/drv_log.h index 95e0f6ebd4b..b7c6537a2c8 100644 --- a/bsp/phytium/libraries/drivers/drv_log.h +++ b/bsp/phytium/libraries/drivers/drv_log.h @@ -20,7 +20,7 @@ #ifdef DRV_DEBUG #define DBG_LVL DBG_LOG #else - #define DBG_LVL DBG_INFO + #define DBG_LVL DBG_ERROR #endif /* DRV_DEBUG */ #include diff --git a/bsp/phytium/libraries/drivers/drv_pwm.c b/bsp/phytium/libraries/drivers/drv_pwm.c index e3c1fd4d254..6703e3af3ef 100644 --- a/bsp/phytium/libraries/drivers/drv_pwm.c +++ b/bsp/phytium/libraries/drivers/drv_pwm.c @@ -289,4 +289,4 @@ int rt_hw_pwm_init(void) return 0; } -INIT_DEVICE_EXPORT(rt_hw_pwm_init); \ No newline at end of file +INIT_DEVICE_EXPORT(rt_hw_pwm_init); diff --git a/bsp/phytium/libraries/drivers/drv_qspi.c b/bsp/phytium/libraries/drivers/drv_qspi.c index b953bbd1821..db3e14c8952 100644 --- a/bsp/phytium/libraries/drivers/drv_qspi.c +++ b/bsp/phytium/libraries/drivers/drv_qspi.c @@ -320,14 +320,16 @@ static rt_ssize_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi_ { RT_ASSERT(device != RT_NULL); RT_ASSERT(message != RT_NULL); + FError ret = FT_SUCCESS; phytium_qspi_bus *qspi_bus; struct rt_qspi_message *qspi_message = (struct rt_qspi_message *)message; + rt_uint32_t cmd = qspi_message->instruction.content; rt_uint32_t flash_addr = qspi_message->address.content; + rt_uint32_t len = message->length; const void *rcvb = message->recv_buf; const void *sndb = message->send_buf; - FError ret = FT_SUCCESS; qspi_bus = (phytium_qspi_bus *)(struct phytium_qspi_bus *) device->bus->parent.user_data; @@ -345,8 +347,6 @@ static rt_ssize_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi_ /*Distinguish the write mode according to different commands*/ if (cmd == FQSPI_FLASH_CMD_PP || cmd == FQSPI_FLASH_CMD_QPP || cmd == FQSPI_FLASH_CMD_4PP || cmd == FQSPI_FLASH_CMD_4QPP) { - rt_uint8_t len = message->length; - rt_memcpy(&wr_buf, (char *)message->send_buf, len); ret = FQspiFlashErase(&(qspi_bus->fqspi), FQSPI_FLASH_CMD_SE, flash_addr); if (FT_SUCCESS != ret) @@ -381,22 +381,20 @@ static rt_ssize_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi_ return -RT_ERROR; } /* read norflash data */ - size_t read_len = QspiFlashReadData(&(qspi_bus->fqspi), addr, (u8 *)&rd_buf, DAT_LENGTH); - message->length = read_len; - if (read_len != DAT_LENGTH) + size_t read_len = QspiFlashReadData(&(qspi_bus->fqspi), addr, (u8 *)&rd_buf, len); + if (read_len != len) { rt_kprintf("Failed to read mem, read len = %d.\r\n", read_len); return -RT_ERROR; } else { - rt_kprintf("Read successfully!!!\r\n"); + rt_kprintf("Read successfully!!!, read_len = %d\r\n", read_len); message->recv_buf = &rd_buf; - } FtDumpHexByte(message->recv_buf, read_len); - return RT_EOK; + return read_len; } if (rcvb) @@ -411,7 +409,7 @@ static rt_ssize_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi_ } } - return RT_EOK; + return 1; } if (sndb) @@ -430,8 +428,9 @@ static rt_ssize_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi_ return -RT_ERROR; } - return RT_EOK; + return 1; } + rt_kprintf("cmd not found!!!\r\n"); return ret; } @@ -502,4 +501,4 @@ int rt_hw_qspi_init(void) #endif return 0; } -INIT_BOARD_EXPORT(rt_hw_qspi_init); \ No newline at end of file +INIT_BOARD_EXPORT(rt_hw_qspi_init); diff --git a/bsp/phytium/libraries/drivers/drv_sdif.c b/bsp/phytium/libraries/drivers/drv_sdif.c index 864969f7f7c..aef51194583 100644 --- a/bsp/phytium/libraries/drivers/drv_sdif.c +++ b/bsp/phytium/libraries/drivers/drv_sdif.c @@ -9,10 +9,11 @@ * Date Author Notes * 2023/7/11 liqiaozhong init SD card and mount file system * 2023/11/8 zhugengyu add interrupt handling for dma waiting, unify function naming + * 2024/4/7 zhugengyu support use two sdif device */ /***************************** Include Files *********************************/ -#include"rtconfig.h" +#include "rtconfig.h" #ifdef BSP_USING_SDIF #include @@ -23,12 +24,12 @@ #include #ifdef RT_USING_SMART - #include "ioremap.h" +#include "ioremap.h" #endif #include "mm_aspace.h" #include "interrupt.h" -#define LOG_TAG "sdif_drv" +#define LOG_TAG "sdif_drv" #include "drv_log.h" #include "ftypes.h" @@ -42,185 +43,292 @@ #include "drv_sdif.h" /************************** Constant Definitions *****************************/ -#ifdef USING_SDIF0 - #define SDIF_CONTROLLER_ID FSDIF0_ID -#elif defined (USING_SDIF1) - #define SDIF_CONTROLLER_ID FSDIF1_ID -#endif -#define SDIF_MALLOC_CAP_DESC 256U -#define SDIF_DMA_ALIGN 512U -#define SDIF_DMA_BLK_SZ 512U -#define SDIF_VALID_OCR 0x00FFFF80 /* supported voltage range is 1.65v-3.6v (VDD_165_195-VDD_35_36) */ -#define SDIF_MAX_BLK_TRANS 20U - -#ifndef CONFIG_SDCARD_OFFSET - #define CONFIG_SDCARD_OFFSET 0x0U -#endif +#define SDIF_CARD_TYPE_MICRO_SD 1 +#define SDIF_CARD_TYPE_EMMC 2 +#define SDIF_CARD_TYPE_SDIO 3 + +#define SDIF_DMA_BLK_SZ 512U +#define SDIF_MAX_BLK_TRANS 20U +#define SDIF_DMA_ALIGN SDIF_DMA_BLK_SZ /* preserve pointer to host instance */ static struct rt_mmcsd_host *mmc_host[FSDIF_NUM] = {RT_NULL}; /**************************** Type Definitions *******************************/ + typedef struct { - FSdif *mmcsd_instance; + FSdif sdif; + rt_int32_t sd_type; FSdifIDmaDesc *rw_desc; - rt_err_t (*transfer)(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req, FSdifCmdData *cmd_data_p); + uintptr_t rw_desc_dma; + rt_size_t rw_desc_num; struct rt_event event; -#define SDIF_EVENT_CARD_DETECTED (1 << 0) -#define SDIF_EVENT_COMMAND_DONE (1 << 1) -#define SDIF_EVENT_DATA_DONE (1 << 2) -#define SDIF_EVENT_ERROR_OCCUR (1 << 3) -#define SDIF_EVENT_SDIO_IRQ (1 << 4) -} fsdif_info_t; +#define SDIF_EVENT_CARD_DETECTED (1 << 0) +#define SDIF_EVENT_COMMAND_DONE (1 << 1) +#define SDIF_EVENT_DATA_DONE (1 << 2) +#define SDIF_EVENT_ERROR_OCCUR (1 << 3) +#define SDIF_EVENT_SDIO_IRQ (1 << 4) + void *aligned_buffer; + uintptr_t aligned_buffer_dma; + rt_size_t aligned_buffer_size; + FSdifCmdData req_cmd; + FSdifCmdData req_stop; + FSdifData req_data; +} sdif_info_t; /************************** Variable Definitions *****************************/ /***************** Macros (Inline Functions) Definitions *********************/ -void fsdif_change(void); -/*******************************Api Functions*********************************/ -static void fsdif_host_relax(void) +/******************************* Functions *********************************/ +static void sdif_host_relax(void) { rt_thread_mdelay(1); } -static void fsdif_card_detect_callback(FSdif *const mmcsd_instance, void *args, u32 status, u32 dmac_status) +void sdif_change(rt_uint32_t id) { - struct rt_mmcsd_host *host = (struct rt_mmcsd_host *)args; - fsdif_info_t *private_data = (fsdif_info_t *)host->private_data; + RT_ASSERT(id < FSDIF_NUM); + if (mmc_host[id]) + { + mmcsd_change(mmc_host[id]); + } +} - rt_event_send(&private_data->event, SDIF_EVENT_CARD_DETECTED); - fsdif_change(); +rt_int32_t sdif_card_inserted(rt_uint32_t id) +{ + RT_ASSERT(id < FSDIF_NUM); + if (mmc_host[id]) + { + return mmc_host[id]->ops->get_card_status(mmc_host[id]); + } + + return 0; } -static void fsdif_command_done_callback(FSdif *const mmcsd_instance, void *args, u32 status, u32 dmac_status) +static void sdif_card_detect_callback(FSdif *const sdif, void *args, u32 status, u32 dmac_status) { struct rt_mmcsd_host *host = (struct rt_mmcsd_host *)args; - fsdif_info_t *private_data = (fsdif_info_t *)host->private_data; + sdif_info_t *host_info = (sdif_info_t *)host->private_data; - rt_event_send(&private_data->event, SDIF_EVENT_COMMAND_DONE); + rt_event_send(&host_info->event, SDIF_EVENT_CARD_DETECTED); + sdif_change(host_info->sdif.config.instance_id); } -static void fsdif_data_done_callback(FSdif *const mmcsd_instance, void *args, u32 status, u32 dmac_status) +static void sdif_command_done_callback(FSdif *const sdif, void *args, u32 status, u32 dmac_status) { struct rt_mmcsd_host *host = (struct rt_mmcsd_host *)args; - fsdif_info_t *private_data = (fsdif_info_t *)host->private_data; + sdif_info_t *host_info = (sdif_info_t *)host->private_data; - rt_event_send(&private_data->event, SDIF_EVENT_DATA_DONE); + rt_event_send(&host_info->event, SDIF_EVENT_COMMAND_DONE); } -static void fsdif_sdio_irq_callback(FSdif *const mmcsd_instance, void *args, u32 status, u32 dmac_status) +static void sdif_data_done_callback(FSdif *const sdif, void *args, u32 status, u32 dmac_status) { struct rt_mmcsd_host *host = (struct rt_mmcsd_host *)args; - fsdif_info_t *private_data = (fsdif_info_t *)host->private_data; + sdif_info_t *host_info = (sdif_info_t *)host->private_data; - rt_event_send(&private_data->event, SDIF_EVENT_SDIO_IRQ); + rt_event_send(&host_info->event, SDIF_EVENT_DATA_DONE); } -static void fsdif_error_occur_callback(FSdif *const mmcsd_instance, void *args, u32 status, u32 dmac_status) +static void sdif_sdio_irq_callback(FSdif *const sdif, void *args, u32 status, u32 dmac_status) { struct rt_mmcsd_host *host = (struct rt_mmcsd_host *)args; - fsdif_info_t *private_data = (fsdif_info_t *)host->private_data; + sdif_info_t *host_info = (sdif_info_t *)host->private_data; - rt_event_send(&private_data->event, SDIF_EVENT_ERROR_OCCUR); + rt_event_send(&host_info->event, SDIF_EVENT_SDIO_IRQ); } -static void fsdif_ctrl_setup_interrupt(struct rt_mmcsd_host *host) +static void sdif_error_occur_callback(FSdif *const sdif, void *args, u32 status, u32 dmac_status) { - fsdif_info_t *private_data = (fsdif_info_t *)host->private_data; - FSdif *mmcsd_instance = private_data->mmcsd_instance; - FSdifConfig *config_p = &mmcsd_instance->config; - rt_uint32_t cpu_id = 0; + struct rt_mmcsd_host *host = (struct rt_mmcsd_host *)args; + sdif_info_t *host_info = (sdif_info_t *)host->private_data; + LOG_E("Error occur !!!"); + LOG_E("Status: 0x%x, dmac status: 0x%x.", status, dmac_status); - GetCpuId((u32 *)&cpu_id); - rt_hw_interrupt_set_target_cpus(config_p->irq_num, cpu_id); - rt_hw_interrupt_set_priority(config_p->irq_num, 0xd0); + if (status & FSDIF_INT_RE_BIT) + LOG_E("Response err. 0x%x", FSDIF_INT_RE_BIT); - /* register intr callback */ - rt_hw_interrupt_install(config_p->irq_num, - FSdifInterruptHandler, - mmcsd_instance, - NULL); + if (status & FSDIF_INT_RTO_BIT) + LOG_E("Response timeout. 0x%x", FSDIF_INT_RTO_BIT); - /* enable irq */ - rt_hw_interrupt_umask(config_p->irq_num); + if (dmac_status & FSDIF_DMAC_STATUS_DU) + LOG_E("Descriptor un-readable. 0x%x", FSDIF_DMAC_STATUS_DU); - FSdifRegisterEvtHandler(mmcsd_instance, FSDIF_EVT_CARD_DETECTED, fsdif_card_detect_callback, host); - FSdifRegisterEvtHandler(mmcsd_instance, FSDIF_EVT_ERR_OCCURE, fsdif_error_occur_callback, host); - FSdifRegisterEvtHandler(mmcsd_instance, FSDIF_EVT_CMD_DONE, fsdif_command_done_callback, host); - FSdifRegisterEvtHandler(mmcsd_instance, FSDIF_EVT_DATA_DONE, fsdif_data_done_callback, host); - FSdifRegisterEvtHandler(mmcsd_instance, FSDIF_EVT_SDIO_IRQ, fsdif_sdio_irq_callback, host); + if (status & FSDIF_INT_DCRC_BIT) + LOG_E("Data CRC error. 0x%x", FSDIF_INT_DCRC_BIT); - return; + if (status & FSDIF_INT_RCRC_BIT) + LOG_E("Data CRC error. 0x%x", FSDIF_INT_RCRC_BIT); + + rt_event_send(&host_info->event, SDIF_EVENT_ERROR_OCCUR); } -static rt_err_t fsdif_ctrl_init(struct rt_mmcsd_host *host) +static rt_err_t sdif_pre_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) { - fsdif_info_t *private_data = (fsdif_info_t *)host->private_data; - FSdif *mmcsd_instance = RT_NULL; - const FSdifConfig *default_mmcsd_config = RT_NULL; - FSdifConfig mmcsd_config; - FSdifIDmaDesc *rw_desc = RT_NULL; + rt_err_t err = RT_EOK; + sdif_info_t *host_info = (sdif_info_t *)host->private_data; - mmcsd_instance = rt_malloc(sizeof(FSdif)); - if (!mmcsd_instance) + if (host_info->sd_type != SDIF_CARD_TYPE_SDIO) { - LOG_E("Malloc mmcsd_instance failed"); - return -RT_ERROR; + /* ignore SDIO detect command */ + if ((req->cmd->cmd_code == SD_IO_SEND_OP_COND) || + (req->cmd->cmd_code == SD_IO_RW_DIRECT)) + { + req->cmd->err = -1; + mmcsd_req_complete(host); + err = RT_EEMPTY; + } } - rw_desc = rt_malloc_align(SDIF_MAX_BLK_TRANS * sizeof(FSdifIDmaDesc), SDIF_MALLOC_CAP_DESC); - if (!rw_desc) + if (host_info->sd_type == SDIF_CARD_TYPE_EMMC) { - LOG_E("Malloc rw_desc failed"); - return -RT_ERROR; + /* ignore micro SD detect command, not in eMMC spec. */ + if ((req->cmd->cmd_code == SD_APP_OP_COND) || + (req->cmd->cmd_code == APP_CMD)) + { + req->cmd->err = -1; + mmcsd_req_complete(host); + err = RT_EEMPTY; + } + + /* ignore mmcsd_send_if_cond(CMD-8) which will failed for eMMC + but check cmd arg to let SEND_EXT_CSD (CMD-8) run */ + if ((req->cmd->cmd_code == SD_SEND_IF_COND) && + (req->cmd->arg == 0x1AA)) /* 0x1AA is the send_if_cond pattern, use it by care */ + { + req->cmd->err = -1; + mmcsd_req_complete(host); + err = RT_EEMPTY; + } } - rt_memset(mmcsd_instance, 0, sizeof(FSdif)); - rt_memset(rw_desc, 0, SDIF_MAX_BLK_TRANS * sizeof(FSdifIDmaDesc)); + if ((req->cmd->cmd_code == READ_MULTIPLE_BLOCK) || + (req->cmd->cmd_code == WRITE_MULTIPLE_BLOCK)) /* set block count */ + { + struct rt_mmcsd_req sbc; + struct rt_mmcsd_cmd sbc_cmd; - /* SDIF controller init */ - RT_ASSERT((default_mmcsd_config = FSdifLookupConfig(SDIF_CONTROLLER_ID)) != RT_NULL); - mmcsd_config = *default_mmcsd_config; /* load default config */ -#ifdef RT_USING_SMART - mmcsd_config.base_addr = (uintptr)rt_ioremap((void *)mmcsd_config.base_addr, 0x1000); -#endif - mmcsd_config.trans_mode = FSDIF_IDMA_TRANS_MODE; -#ifdef USING_EMMC - mmcsd_config.non_removable = TRUE; /* eMMC is unremovable on board */ -#else - mmcsd_config.non_removable = FALSE; /* TF card is removable on board */ -#endif - mmcsd_config.get_tuning = FSdifGetTimingSetting; + rt_memset(&sbc, 0, sizeof(sbc)); + rt_memset(&sbc_cmd, 0, sizeof(sbc_cmd)); + + sbc_cmd.cmd_code = SET_BLOCK_COUNT; + RT_ASSERT(req->data); + sbc_cmd.arg = req->data->blks; + sbc_cmd.flags = RESP_R1; + + LOG_I("set block_count = %d", req->data->blks); + + sbc.data = RT_NULL; + sbc.cmd = &sbc_cmd; + sbc.stop = RT_NULL; + sbc.sbc = RT_NULL; + mmcsd_send_request(host, &sbc); - if (FSDIF_SUCCESS != FSdifCfgInitialize(mmcsd_instance, &mmcsd_config)) + err = sbc_cmd.err; + if (req->cmd->busy_timeout < 1000) /* in case rt-thread do not give wait timeout */ + { + req->cmd->busy_timeout = 5000; + } + } + + return err; +} + +static void sdif_convert_command_info(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *in_cmd, struct rt_mmcsd_data *in_data, FSdifCmdData *out_req) +{ + FSdifCmdData *out_cmd = out_req; + FSdifData *out_data = out_req->data_p; + sdif_info_t *host_info = (sdif_info_t *)host->private_data; + + out_cmd->flag = 0U; + + if (in_cmd->cmd_code == GO_IDLE_STATE) { - LOG_E("SDIF controller init failed."); - return -RT_ERROR; + out_cmd->flag |= FSDIF_CMD_FLAG_NEED_INIT; } - if (FSDIF_SUCCESS != FSdifSetIDMAList(mmcsd_instance, rw_desc, (uintptr)rw_desc + PV_OFFSET, SDIF_MAX_BLK_TRANS)) + if (in_cmd->cmd_code == GO_INACTIVE_STATE) { - LOG_E("SDIF controller setup DMA failed."); - return -RT_ERROR; + out_cmd->flag |= FSDIF_CMD_FLAG_NEED_AUTO_STOP | FSDIF_CMD_FLAG_ABORT; } - mmcsd_instance->desc_list.first_desc_dma = (uintptr)rw_desc + PV_OFFSET; - FSdifRegisterRelaxHandler(mmcsd_instance, fsdif_host_relax); /* SDIF delay for a while */ + if (resp_type(in_cmd) != RESP_NONE) + { + out_cmd->flag |= FSDIF_CMD_FLAG_EXP_RESP; - private_data->mmcsd_instance = mmcsd_instance; - private_data->rw_desc = rw_desc; + if (resp_type(in_cmd) == RESP_R2) + { + /* need 136 bits long response */ + out_cmd->flag |= FSDIF_CMD_FLAG_EXP_LONG_RESP; + } - fsdif_ctrl_setup_interrupt(host); - return RT_EOK; + if ((resp_type(in_cmd) != RESP_R3) && + (resp_type(in_cmd) != RESP_R4)) + { + /* most cmds need CRC */ + out_cmd->flag |= FSDIF_CMD_FLAG_NEED_RESP_CRC; + } + } + + if (in_data) + { + RT_ASSERT(out_data); + out_cmd->flag |= FSDIF_CMD_FLAG_EXP_DATA; + + if (in_data->flags & DATA_DIR_READ) + { + out_cmd->flag |= FSDIF_CMD_FLAG_READ_DATA; + out_data->buf = (void *)in_data->buf; + out_data->buf_dma = (uintptr_t)in_data->buf + PV_OFFSET; + } + else if (in_data->flags & DATA_DIR_WRITE) + { + out_cmd->flag |= FSDIF_CMD_FLAG_WRITE_DATA; + out_data->buf = (void *)in_data->buf; + out_data->buf_dma = (uintptr_t)in_data->buf + PV_OFFSET; + } + else + { + RT_ASSERT(0); + } + + out_data->blksz = in_data->blksize; + out_data->blkcnt = in_data->blks; + out_data->datalen = in_data->blksize * in_data->blks; + + /* handle unaligned input buffer */ + if (out_data->buf_dma % SDIF_DMA_ALIGN) + { + RT_ASSERT(out_data->datalen <= host_info->aligned_buffer_size); + out_data->buf = host_info->aligned_buffer; + out_data->buf_dma = (uintptr_t)host_info->aligned_buffer + PV_OFFSET; + + if (in_data->flags & DATA_DIR_WRITE) + { + /* copy the data need to write to sd card */ + memcpy(out_data->buf, in_data->buf, out_data->datalen); + } + } + + LOG_D("buf@%p, blksz: %d, datalen: %ld", + out_data->buf, + out_data->blksz, + out_data->datalen); + } + + out_cmd->cmdidx = in_cmd->cmd_code; + out_cmd->cmdarg = in_cmd->arg; + LOG_D("cmdarg: 0x%x", out_cmd->cmdarg); } -rt_inline rt_err_t fsdif_dma_transfer(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req, FSdifCmdData *req_cmd) +static rt_err_t sdif_do_transfer(struct rt_mmcsd_host *host, FSdifCmdData *req_cmd, rt_int32_t timeout_ms) { FError ret = FT_SUCCESS; + sdif_info_t *host_info = (sdif_info_t *)host->private_data; rt_uint32_t event = 0U; rt_uint32_t wait_event = 0U; - fsdif_info_t *private_data = (fsdif_info_t *)host->private_data; - FSdif *mmcsd_instance = private_data->mmcsd_instance; + + LOG_I("cmd-%d sending", req_cmd->cmdidx); if (req_cmd->data_p == RT_NULL) { @@ -231,7 +339,7 @@ rt_inline rt_err_t fsdif_dma_transfer(struct rt_mmcsd_host *host, struct rt_mmcs wait_event = SDIF_EVENT_COMMAND_DONE | SDIF_EVENT_DATA_DONE; } - ret = FSdifDMATransfer(mmcsd_instance, req_cmd); + ret = FSdifDMATransfer(&host_info->sdif, req_cmd); if (ret != FT_SUCCESS) { LOG_E("FSdifDMATransfer() fail."); @@ -240,189 +348,111 @@ rt_inline rt_err_t fsdif_dma_transfer(struct rt_mmcsd_host *host, struct rt_mmcs while (TRUE) { - if (rt_event_recv(&private_data->event, + /* + * transfer without data: wait COMMAND_DONE event + * transfer with data: wait COMMAND_DONE and DATA_DONE event + */ + if (rt_event_recv(&host_info->event, (wait_event), - (RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR | RT_WAITING_NO), - rt_tick_from_millisecond(5000), + (RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR), + rt_tick_from_millisecond(1000), &event) == RT_EOK) { - (void)FSdifGetCmdResponse(mmcsd_instance, req_cmd); + (void)FSdifGetCmdResponse(&host_info->sdif, req_cmd); break; } - else - { - if (rt_event_recv(&private_data->event, - (SDIF_EVENT_ERROR_OCCUR), - (RT_EVENT_FLAG_CLEAR | RT_WAITING_NO), - rt_tick_from_millisecond(5000), - &event) == RT_EOK) - { - LOG_E("Sdif DMA transfer endup with error !!!"); - return -RT_EIO; - } - } - fsdif_host_relax(); - } - - if (resp_type(req->cmd) & RESP_MASK) - { - if (resp_type(req->cmd) == RESP_R2) + /* + * transfer with error: check if ERROR_OCCUR event exists, no wait + */ + if (rt_event_recv(&host_info->event, + (SDIF_EVENT_ERROR_OCCUR), + (RT_EVENT_FLAG_AND | RT_WAITING_NO), + 0, + &event) == RT_EOK) { - req->cmd->resp[3] = req_cmd->response[0]; - req->cmd->resp[2] = req_cmd->response[1]; - req->cmd->resp[1] = req_cmd->response[2]; - req->cmd->resp[0] = req_cmd->response[3]; + LOG_E("Sdif DMA transfer endup with error !!!"); + return -RT_EIO; } - else + + timeout_ms -= 1000; + if (timeout_ms <= 0) { - req->cmd->resp[0] = req_cmd->response[0]; + LOG_E("Sdif DMA transfer endup with timeout !!!"); + return -RT_EIO; } } return RT_EOK; } -static void fsdif_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +static void sdif_send_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) { - /* ignore some SDIF-ONIY cmd */ - if ((req->cmd->cmd_code == SD_IO_SEND_OP_COND) || (req->cmd->cmd_code == SD_IO_RW_DIRECT)) - { - req->cmd->err = -1; - goto skip_cmd; - } - - fsdif_info_t *private_data = (fsdif_info_t *)host->private_data; - FSdifCmdData req_cmd; - FSdifCmdData req_stop; - FSdifData req_data; - rt_uint32_t *data_buf_aligned = RT_NULL; - rt_uint32_t cmd_flag = resp_type(req->cmd); - - rt_memset(&req_cmd, 0, sizeof(FSdifCmdData)); - rt_memset(&req_stop, 0, sizeof(FSdifCmdData)); - rt_memset(&req_data, 0, sizeof(FSdifData)); + sdif_info_t *host_info = (sdif_info_t *)host->private_data; + FSdifCmdData *req_cmd = &host_info->req_cmd; + FSdifData *req_data = &host_info->req_data; - /* convert req into ft driver type */ - if (req->cmd->cmd_code == GO_IDLE_STATE) + rt_err_t err = sdif_pre_request(host, req); + if (err != RT_EOK) { - req_cmd.flag |= FSDIF_CMD_FLAG_NEED_INIT; + return; } - if (req->cmd->cmd_code == GO_INACTIVE_STATE) - { - req_cmd.flag |= FSDIF_CMD_FLAG_NEED_AUTO_STOP; - } + memset(req_cmd, 0, sizeof(*req_cmd)); - if ((cmd_flag != RESP_R3) && (cmd_flag != RESP_R4) && (cmd_flag != RESP_NONE)) + if (req->data) { - req_cmd.flag |= FSDIF_CMD_FLAG_NEED_RESP_CRC; + memset(req_data, 0, sizeof(*req_data)); + req_cmd->data_p = req_data; } - - if (cmd_flag & RESP_MASK) + else { - req_cmd.flag |= FSDIF_CMD_FLAG_EXP_RESP; - - if (cmd_flag == RESP_R2) - { - req_cmd.flag |= FSDIF_CMD_FLAG_EXP_LONG_RESP; - } + req_cmd->data_p = RT_NULL; } - if (req->data) /* transfer command with data */ - { - data_buf_aligned = rt_malloc_align(SDIF_DMA_BLK_SZ * req->data->blks, SDIF_DMA_ALIGN); - if (!data_buf_aligned) - { - LOG_E("Malloc data_buf_aligned failed"); - return; - } - rt_memset(data_buf_aligned, 0, SDIF_DMA_BLK_SZ * req->data->blks); + sdif_convert_command_info(host, req->cmd, req->data, req_cmd); - req_cmd.flag |= FSDIF_CMD_FLAG_EXP_DATA; + req->cmd->err = sdif_do_transfer(host, req_cmd, req->cmd->busy_timeout); - req_data.blksz = req->data->blksize; - req_data.blkcnt = req->data->blks + CONFIG_SDCARD_OFFSET; - req_data.datalen = req->data->blksize * req->data->blks; - if ((uintptr)req->data->buf % SDIF_DMA_ALIGN) /* data buffer should be 512-aligned */ + if (resp_type(req->cmd) & RESP_MASK) + { + if (resp_type(req->cmd) == RESP_R2) { - if (req->data->flags & DATA_DIR_WRITE) - { - rt_memcpy((void *)data_buf_aligned, (void *)req->data->buf, req_data.datalen); - } - req_data.buf = (rt_uint8_t *)data_buf_aligned; - req_data.buf_dma = (uintptr)data_buf_aligned + PV_OFFSET; + req->cmd->resp[3] = req_cmd->response[0]; + req->cmd->resp[2] = req_cmd->response[1]; + req->cmd->resp[1] = req_cmd->response[2]; + req->cmd->resp[0] = req_cmd->response[3]; } else { - req_data.buf = (rt_uint8_t *)req->data->buf; - req_data.buf_dma = (uintptr)req->data->buf + PV_OFFSET; - } - req_cmd.data_p = &req_data; - - if (req->data->flags & DATA_DIR_READ) - { - req_cmd.flag |= FSDIF_CMD_FLAG_READ_DATA; - } - else if (req->data->flags & DATA_DIR_WRITE) - { - req_cmd.flag |= FSDIF_CMD_FLAG_WRITE_DATA; + req->cmd->resp[0] = req_cmd->response[0]; } } - req_cmd.cmdidx = req->cmd->cmd_code; - req_cmd.cmdarg = req->cmd->arg; - - /* do cmd and data transfer */ - req->cmd->err = (private_data->transfer)(host, req, &req_cmd); - if (req->cmd->err != RT_EOK) - { - LOG_E("transfer failed in %s", __func__); - } - if (req->data && (req->data->flags & DATA_DIR_READ)) { - if ((uintptr)req->data->buf % SDIF_DMA_ALIGN) /* data buffer should be 512-aligned */ + /* if it is read sd card, copy data to unaligned buffer and return */ + if ((uintptr)req->data->buf % SDIF_DMA_ALIGN) { - rt_memcpy((void *)req->data->buf, (void *)data_buf_aligned, req_data.datalen); + rt_memcpy((void *)req->data->buf, + (void *)host_info->aligned_buffer, + req_cmd->data_p->datalen); } } - /* stop cmd */ - if (req->stop) - { - req_stop.cmdidx = req->stop->cmd_code; - req_stop.cmdarg = req->stop->arg; - if (req->stop->flags & RESP_MASK) - { - req_stop.flag |= FSDIF_CMD_FLAG_READ_DATA; - if (resp_type(req->stop) == RESP_R2) - { - req_stop.flag |= FSDIF_CMD_FLAG_EXP_LONG_RESP; - } - } - req->stop->err = (private_data->transfer)(host, req, &req_stop); - } - - if (data_buf_aligned) - { - rt_free_align(data_buf_aligned); - } - -skip_cmd: mmcsd_req_complete(host); } -static void fsdif_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +static void sdif_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) { FError ret = FT_SUCCESS; - fsdif_info_t *private_data = (fsdif_info_t *)host->private_data; - FSdif *mmcsd_instance = private_data->mmcsd_instance; - uintptr base_addr = mmcsd_instance->config.base_addr; + sdif_info_t *host_info = (sdif_info_t *)host->private_data; + FSdif *sdif = &host_info->sdif; + uintptr base_addr = sdif->config.base_addr; if (0 != io_cfg->clock) { - ret = FSdifSetClkFreq(mmcsd_instance, io_cfg->clock); + ret = FSdifSetClkFreq(sdif, io_cfg->clock); if (ret != FT_SUCCESS) { LOG_E("FSdifSetClkFreq fail."); @@ -431,102 +461,257 @@ static void fsdif_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg * switch (io_cfg->bus_width) { - case MMCSD_BUS_WIDTH_1: - FSdifSetBusWidth(base_addr, 1U); - break; - case MMCSD_BUS_WIDTH_4: - FSdifSetBusWidth(base_addr, 4U); - break; - case MMCSD_BUS_WIDTH_8: - FSdifSetBusWidth(base_addr, 8U); - break; - default: - LOG_E("Invalid bus width %d", io_cfg->bus_width); - break; + case MMCSD_BUS_WIDTH_1: + FSdifSetBusWidth(base_addr, 1U); + break; + case MMCSD_BUS_WIDTH_4: + FSdifSetBusWidth(base_addr, 4U); + break; + case MMCSD_BUS_WIDTH_8: + FSdifSetBusWidth(base_addr, 8U); + break; + default: + LOG_E("Invalid bus width %d", io_cfg->bus_width); + break; } } -static const struct rt_mmcsd_host_ops ops = +static rt_int32_t sdif_card_status(struct rt_mmcsd_host *host) { - fsdif_request_send, - fsdif_set_iocfg, - RT_NULL, - RT_NULL, - RT_NULL, + sdif_info_t *host_info = (sdif_info_t *)host->private_data; + FSdif *sdif = &host_info->sdif; + uintptr base_addr = sdif->config.base_addr; + + return FSdifCheckIfCardExists(base_addr) ? 1 : 0; +} + +static const struct rt_mmcsd_host_ops ops = + { + .request = sdif_send_request, + .set_iocfg = sdif_set_iocfg, + .get_card_status = sdif_card_status, + .enable_sdio_irq = RT_NULL, + .execute_tuning = RT_NULL, }; -void fsdif_change(void) +static void sdif_ctrl_setup_interrupt(struct rt_mmcsd_host *host) { - mmcsd_change(mmc_host[SDIF_CONTROLLER_ID]); + sdif_info_t *host_info = (sdif_info_t *)host->private_data; + FSdif *sdif = &(host_info->sdif); + FSdifConfig *config_p = &sdif->config; + rt_uint32_t cpu_id = rt_hw_cpu_id(); + + rt_hw_interrupt_set_target_cpus(config_p->irq_num, cpu_id); + rt_hw_interrupt_set_priority(config_p->irq_num, 0xd0); + + /* register intr callback */ + rt_hw_interrupt_install(config_p->irq_num, + FSdifInterruptHandler, + sdif, + NULL); + + /* enable irq */ + rt_hw_interrupt_umask(config_p->irq_num); + + FSdifRegisterEvtHandler(sdif, FSDIF_EVT_CARD_DETECTED, sdif_card_detect_callback, host); + FSdifRegisterEvtHandler(sdif, FSDIF_EVT_ERR_OCCURE, sdif_error_occur_callback, host); + FSdifRegisterEvtHandler(sdif, FSDIF_EVT_CMD_DONE, sdif_command_done_callback, host); + FSdifRegisterEvtHandler(sdif, FSDIF_EVT_DATA_DONE, sdif_data_done_callback, host); + FSdifRegisterEvtHandler(sdif, FSDIF_EVT_SDIO_IRQ, sdif_sdio_irq_callback, host); + + return; } -int rt_hw_fsdif_init(void) +static rt_err_t sdif_host_init(rt_uint32_t id, rt_uint32_t type) { - /* variables init */ struct rt_mmcsd_host *host = RT_NULL; - fsdif_info_t *private_data = RT_NULL; + sdif_info_t *host_info = RT_NULL; + const FSdifConfig *default_sdif_config = RT_NULL; + FSdifConfig sdif_config; rt_err_t result = RT_EOK; host = mmcsd_alloc_host(); if (!host) { LOG_E("Alloc host failed"); + result = RT_ENOMEM; goto err_free; } - private_data = rt_malloc(sizeof(fsdif_info_t)); - if (!private_data) + host_info = rt_malloc(sizeof(sdif_info_t)); + if (!host_info) { - LOG_E("Malloc private_data failed"); + LOG_E("Malloc host_info failed"); + result = RT_ENOMEM; goto err_free; } + rt_memset(host_info, 0, sizeof(*host_info)); - rt_memset(private_data, 0, sizeof(fsdif_info_t)); - private_data->transfer = fsdif_dma_transfer; - result = rt_event_init(&private_data->event, "sdif_event", RT_IPC_FLAG_FIFO); + result = rt_event_init(&host_info->event, "sdif_event", RT_IPC_FLAG_FIFO); RT_ASSERT(RT_EOK == result); + host_info->aligned_buffer_size = SDIF_DMA_BLK_SZ * SDIF_MAX_BLK_TRANS; + host_info->aligned_buffer = rt_malloc_align(host_info->aligned_buffer_size, + SDIF_DMA_ALIGN); + if (!host_info->aligned_buffer) + { + LOG_E("Malloc aligned buffer failed"); + result = RT_ENOMEM; + goto err_free; + } + + host_info->aligned_buffer_dma = (uintptr_t)host_info->aligned_buffer + PV_OFFSET; + rt_memset(host_info->aligned_buffer, 0, host_info->aligned_buffer_size); + + host_info->rw_desc_num = (SDIF_DMA_BLK_SZ * SDIF_MAX_BLK_TRANS) / FSDIF_IDMAC_MAX_BUF_SIZE + 1; + host_info->rw_desc = rt_malloc_align(host_info->rw_desc_num * sizeof(FSdifIDmaDesc), + SDIF_DMA_ALIGN); + if (!host_info->rw_desc) + { + LOG_E("Malloc rw_desc failed"); + result = RT_ENOMEM; + goto err_free; + } + + host_info->rw_desc_dma = (uintptr_t)host_info->rw_desc + PV_OFFSET; + rt_memset(host_info->rw_desc, 0, host_info->rw_desc_num * sizeof(FSdifIDmaDesc)); + /* host data init */ host->ops = &ops; - host->freq_min = 400000; - host->freq_max = 50000000; - host->valid_ocr = SDIF_VALID_OCR; /* the voltage range supported is 1.65v-3.6v */ + host->freq_min = FSDIF_CLK_SPEED_400KHZ; + if (type == SDIF_CARD_TYPE_MICRO_SD) + { + host->freq_max = FSDIF_CLK_SPEED_50_MHZ; + } + else + { + host->freq_max = FSDIF_CLK_SPEED_52_MHZ; + } + + host->valid_ocr = VDD_32_33 | VDD_33_34; /* voltage 3.3v */ host->flags = MMCSD_MUTBLKWRITE | MMCSD_BUSWIDTH_4; - host->max_seg_size = SDIF_DMA_BLK_SZ; /* used in block_dev.c */ + host->max_seg_size = SDIF_DMA_BLK_SZ; /* used in block_dev.c */ host->max_dma_segs = SDIF_MAX_BLK_TRANS; /* physical segment number */ - host->max_blk_size = SDIF_DMA_BLK_SZ; /* all the 4 para limits size of one blk tran */ + host->max_blk_size = SDIF_DMA_BLK_SZ; /* all the 4 para limits size of one blk tran */ host->max_blk_count = SDIF_MAX_BLK_TRANS; - host->private_data = private_data; + host->private_data = host_info; + host->name[0] = 's'; + host->name[1] = 'd'; + host->name[2] = '0' + id; + host->name[3] = '\0'; + + mmc_host[id] = host; + + RT_ASSERT((default_sdif_config = FSdifLookupConfig(id)) != RT_NULL); + sdif_config = *default_sdif_config; +#ifdef RT_USING_SMART + sdif_config.base_addr = (uintptr)rt_ioremap((void *)sdif_config.base_addr, 0x1000); +#endif + sdif_config.trans_mode = FSDIF_IDMA_TRANS_MODE; - mmc_host[SDIF_CONTROLLER_ID] = host; + if (type == SDIF_CARD_TYPE_MICRO_SD) + { + sdif_config.non_removable = FALSE; /* TF card is removable on board */ + } + else if (type == SDIF_CARD_TYPE_EMMC) + { + sdif_config.non_removable = TRUE; /* eMMC is unremovable on board */ + } - if (RT_EOK != fsdif_ctrl_init(host)) + sdif_config.get_tuning = FSdifGetTimingSetting; + + if (FSDIF_SUCCESS != FSdifCfgInitialize(&host_info->sdif, &sdif_config)) { - LOG_E("fsdif_ctrl_init() failed"); + LOG_E("SDIF controller init failed."); + result = RT_EIO; goto err_free; } - return RT_EOK; + if (FSDIF_SUCCESS != FSdifSetIDMAList(&host_info->sdif, + host_info->rw_desc, + host_info->rw_desc_dma, + host_info->rw_desc_num)) + { + LOG_E("SDIF controller setup DMA failed."); + result = RT_EIO; + goto err_free; + } + + FSdifRegisterRelaxHandler(&host_info->sdif, sdif_host_relax); /* SDIF delay for a while */ + + host_info->sd_type = type; + LOG_I("Init sdif-%d as %d", id, type); + + /* setup interrupt */ + sdif_ctrl_setup_interrupt(host); + return result; err_free: if (host) { - rt_free(host); + mmcsd_free_host(host); } - if (private_data->mmcsd_instance) + + if (host_info) { - rt_free(private_data->mmcsd_instance); + if (host_info->aligned_buffer) + { + rt_free(host_info->aligned_buffer); + host_info->aligned_buffer = RT_NULL; + host_info->aligned_buffer_size = 0U; + } + + if (host_info->rw_desc) + { + rt_free(host_info->rw_desc); + host_info->rw_desc = RT_NULL; + host_info->rw_desc_num = 0; + } + + rt_free(host_info); } - if (private_data->rw_desc) + + return result; +} + +int rt_hw_sdif_init(void) +{ + int status = RT_EOK; + rt_uint32_t sd_type; + + FSdifTimingInit(); + +#ifdef USING_SDIF0 +#if defined(USE_SDIF0_TF) + sd_type = SDIF_CARD_TYPE_MICRO_SD; +#elif defined(USE_SDIF0_EMMC) + sd_type = SDIF_CARD_TYPE_EMMC; +#endif + status = sdif_host_init(FSDIF0_ID, sd_type); + + if (status != RT_EOK) { - rt_free_align(private_data->rw_desc); + LOG_E("SDIF0 init failed, status = %d", status); + return status; } - if (private_data) +#endif + +#ifdef USING_SDIF1 +#if defined(USE_SDIF1_TF) + sd_type = SDIF_CARD_TYPE_MICRO_SD; +#elif defined(USE_SDIF1_EMMC) + sd_type = SDIF_CARD_TYPE_EMMC; +#endif + status = sdif_host_init(FSDIF1_ID, sd_type); + + if (status != RT_EOK) { - rt_free(private_data); + LOG_E("SDIF0 init failed, status = %d", status); + return status; } +#endif - return -RT_EOK; + return status; } -INIT_DEVICE_EXPORT(rt_hw_fsdif_init); -#endif // #ifdef RT_USING_SDIO \ No newline at end of file +INIT_DEVICE_EXPORT(rt_hw_sdif_init); +#endif // #ifdef BSP_USING_SDIF \ No newline at end of file diff --git a/bsp/phytium/libraries/drivers/drv_sdif.h b/bsp/phytium/libraries/drivers/drv_sdif.h index 5ced05a4c89..36001f6753c 100644 --- a/bsp/phytium/libraries/drivers/drv_sdif.h +++ b/bsp/phytium/libraries/drivers/drv_sdif.h @@ -25,4 +25,4 @@ /*******************************Api Functions*********************************/ -#endif \ No newline at end of file +#endif diff --git a/bsp/phytium/libraries/drivers/drv_spi.c b/bsp/phytium/libraries/drivers/drv_spi.c index a13ec108395..e1648f2b2d0 100644 --- a/bsp/phytium/libraries/drivers/drv_spi.c +++ b/bsp/phytium/libraries/drivers/drv_spi.c @@ -47,16 +47,15 @@ static struct rt_event rx_done_event; #define EVENT_RX_DONE (1 << 1) /*******************************Api Functions*********************************/ static rt_err_t spim_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); -static rt_uint32_t spim_xfer(struct rt_spi_device *device, struct rt_spi_message *message); +static rt_ssize_t spim_xfer(struct rt_spi_device *device, struct rt_spi_message *message); static FError FSpimSetupInterrupt(FSpim *instance_p) { FASSERT(instance_p); FSpimConfig *config_p = &instance_p->config; uintptr base_addr = config_p->base_addr; - u32 cpu_id = 0; + rt_uint32_t cpu_id = rt_hw_cpu_id(); - GetCpuId(&cpu_id); LOG_D("cpu_id is %d, irq_num is %d\n", cpu_id, config_p->irq_num); config_p->irq_prority = 0xd0; rt_hw_interrupt_set_target_cpus(config_p->irq_num, cpu_id); @@ -148,12 +147,12 @@ static rt_err_t spim_configure(struct rt_spi_device *device, return ret; } -static rt_uint32_t spim_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +static rt_ssize_t spim_xfer(struct rt_spi_device *device, struct rt_spi_message *message) { RT_ASSERT(device != RT_NULL); RT_ASSERT(device->parent.user_data != RT_NULL); RT_ASSERT(message != RT_NULL); - rt_size_t message_length; + rt_ssize_t message_length; rt_uint8_t *recv_buf; const rt_uint8_t *send_buf; @@ -264,4 +263,4 @@ int rt_hw_spi_init(void) return 0; } -INIT_DEVICE_EXPORT(rt_hw_spi_init); \ No newline at end of file +INIT_DEVICE_EXPORT(rt_hw_spi_init); diff --git a/bsp/phytium/libraries/drivers/drv_usart.c b/bsp/phytium/libraries/drivers/drv_usart.c index b4a7f1839eb..2f10ec42a41 100644 --- a/bsp/phytium/libraries/drivers/drv_usart.c +++ b/bsp/phytium/libraries/drivers/drv_usart.c @@ -234,4 +234,4 @@ int rt_hw_uart_init(void) return 0; } -INIT_BOARD_EXPORT(rt_hw_uart_init); \ No newline at end of file +INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/phytium/libraries/drivers/drv_usart.h b/bsp/phytium/libraries/drivers/drv_usart.h index 2e78be8232c..2295114e53a 100644 --- a/bsp/phytium/libraries/drivers/drv_usart.h +++ b/bsp/phytium/libraries/drivers/drv_usart.h @@ -44,4 +44,4 @@ struct drv_usart struct rt_serial_device serial; }; -#endif // ! \ No newline at end of file +#endif // ! diff --git a/bsp/phytium/libraries/drivers/drv_xmac.c b/bsp/phytium/libraries/drivers/drv_xmac.c index 07e599c7241..37cdc98cf20 100644 --- a/bsp/phytium/libraries/drivers/drv_xmac.c +++ b/bsp/phytium/libraries/drivers/drv_xmac.c @@ -1001,8 +1001,7 @@ static void FxmacOsIntrHandler(s32 vector, void *args) static void FXmacSetupIsr(FXmacOs *instance_p) { - u32 cpu_id; - GetCpuId(&cpu_id); + rt_uint32_t cpu_id = rt_hw_cpu_id(); /* Setup callbacks */ FXmacSetHandler(&instance_p->instance, FXMAC_HANDLER_DMARECV, FXmacRecvSemaphoreHandler, instance_p); diff --git a/bsp/phytium/libraries/phytium_standalone_sdk_install.py b/bsp/phytium/libraries/phytium_standalone_sdk_install.py index ced6db85a95..d660f702acf 100644 --- a/bsp/phytium/libraries/phytium_standalone_sdk_install.py +++ b/bsp/phytium/libraries/phytium_standalone_sdk_install.py @@ -19,6 +19,6 @@ def clone_repository(branch, commit_hash): if __name__ == "__main__": branch_to_clone = "master" - commit_to_clone = "13657081faf9f2d504592f7110159c4e63dc6f29" + commit_to_clone = "cd15b23000d0c52968dc322b6d99025195bbf446" clone_repository(branch_to_clone, commit_to_clone) \ No newline at end of file diff --git a/bsp/phytium/libraries/port/cherryusb_port/drv_pusb2_dc.c b/bsp/phytium/libraries/port/cherryusb_port/drv_pusb2_dc.c index 62d8db20938..08ea83a38f6 100644 --- a/bsp/phytium/libraries/port/cherryusb_port/drv_pusb2_dc.c +++ b/bsp/phytium/libraries/port/cherryusb_port/drv_pusb2_dc.c @@ -90,4 +90,4 @@ void usb_assert(const char *filename, int linenum) RT_ASSERT(0); } -#endif \ No newline at end of file +#endif diff --git a/bsp/phytium/libraries/port/cherryusb_port/drv_pusb2_hc.c b/bsp/phytium/libraries/port/cherryusb_port/drv_pusb2_hc.c index 46b7cc6ae6c..b280f89f800 100644 --- a/bsp/phytium/libraries/port/cherryusb_port/drv_pusb2_hc.c +++ b/bsp/phytium/libraries/port/cherryusb_port/drv_pusb2_hc.c @@ -95,4 +95,4 @@ void usb_assert(const char *filename, int linenum) RT_ASSERT(0); } -#endif \ No newline at end of file +#endif diff --git a/bsp/phytium/libraries/port/cherryusb_port/drv_xhci.c b/bsp/phytium/libraries/port/cherryusb_port/drv_xhci.c index 4627a5f4537..d60de3f3252 100644 --- a/bsp/phytium/libraries/port/cherryusb_port/drv_xhci.c +++ b/bsp/phytium/libraries/port/cherryusb_port/drv_xhci.c @@ -95,4 +95,4 @@ void usb_assert(const char *filename, int linenum) RT_ASSERT(0); } -#endif \ No newline at end of file +#endif diff --git a/bsp/phytium/libraries/port/fboard_port/e2000d_demo/mnt_sdcard.c b/bsp/phytium/libraries/port/fboard_port/e2000d_demo/mnt_sdcard.c new file mode 100644 index 00000000000..e19d613c8a5 --- /dev/null +++ b/bsp/phytium/libraries/port/fboard_port/e2000d_demo/mnt_sdcard.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Email: opensource_embedded@phytium.com.cn + * + * Change Logs: + * Date Author Notes + * 2023-04-27 huanghe first version + * 2023-07-14 liqiaozhong add SD file sys mount func + * 2024-04-08 zhugengyu define mount table by board + */ +#include +#include + +#define DBG_TAG "mnt.filesystem" +#define DBG_LVL DBG_INFO +#include + +#define FS_SD_MOUNT_POINT "/" +#define FS_SD_DEVICE_NAME "sd1" +#define FS_SD_DEVICE_INDEX 1 + +#define FS_EMMC_MOUNT_POINT "/sd0" +#define FS_EMMC_DEVICE_NAME "sd0" +#define FS_EMMC_DEVICE_INDEX 0 + +extern void sdif_change(rt_uint32_t id); +extern rt_int32_t sdif_card_inserted(rt_uint32_t id); + +static rt_int32_t card_inserted = 0; + +static void _sdcard_mount(void) +{ + rt_device_t device; + + device = rt_device_find(FS_SD_DEVICE_NAME); + rt_kprintf("rt_device_find %x \r\n", device); + if (device == NULL) + { + mmcsd_wait_cd_changed(0); + sdif_change(FS_SD_DEVICE_INDEX); + mmcsd_wait_cd_changed(RT_WAITING_FOREVER); + device = rt_device_find(FS_SD_DEVICE_NAME); + } + + if (device != RT_NULL) + { + if (dfs_mount(FS_SD_DEVICE_NAME, FS_SD_MOUNT_POINT, "elm", 0, 0) == RT_EOK) + { + LOG_I("%s mount to '%s'", FS_SD_DEVICE_NAME, FS_SD_MOUNT_POINT); + mkdir(FS_EMMC_MOUNT_POINT, 0); + if (dfs_mount(FS_EMMC_DEVICE_NAME, FS_EMMC_MOUNT_POINT, "elm", 0, 0) == RT_EOK) + { + LOG_I("%s mount to '%s'", FS_EMMC_DEVICE_NAME, FS_EMMC_MOUNT_POINT); + } + + card_inserted = 1; + } + else + { + LOG_W("%s mount to '%s' failed!", FS_SD_DEVICE_NAME, FS_SD_MOUNT_POINT); + } + } +} + +static void _sdcard_unmount(void) +{ + rt_thread_mdelay(200); + dfs_unmount(FS_SD_MOUNT_POINT); + LOG_I("Unmount %s", FS_SD_MOUNT_POINT); + + mmcsd_wait_cd_changed(0); + sdif_change(FS_SD_DEVICE_INDEX); + mmcsd_wait_cd_changed(RT_WAITING_FOREVER); + + card_inserted = 0; +} + +static void sd_auto_mount(void *parameter) +{ + rt_thread_mdelay(20); + + /* detect eMMC */ + mmcsd_wait_cd_changed(0); + sdif_change(FS_EMMC_DEVICE_INDEX); + mmcsd_wait_cd_changed(RT_WAITING_FOREVER); + + if ((card_inserted == 0) && (sdif_card_inserted(FS_SD_DEVICE_INDEX) == 1)) + { + _sdcard_mount(); + } + + while (RT_TRUE) + { + rt_thread_mdelay(200); + + if ((card_inserted == 0) && (sdif_card_inserted(FS_SD_DEVICE_INDEX) == 1)) + { + _sdcard_mount(); + } + + if ((card_inserted == 1) && (sdif_card_inserted(FS_SD_DEVICE_INDEX) == 0)) + { + _sdcard_unmount(); + } + } +} + +static void sd_mount(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("sd_mount", sd_auto_mount, RT_NULL, + 4096, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + return; + } +} + +int filesystem_mount(void) +{ + sd_mount(); + return RT_EOK; +} +INIT_APP_EXPORT(filesystem_mount); diff --git a/bsp/phytium/libraries/port/fboard_port/e2000q_demo/mnt_sdcard.c b/bsp/phytium/libraries/port/fboard_port/e2000q_demo/mnt_sdcard.c new file mode 100644 index 00000000000..e19d613c8a5 --- /dev/null +++ b/bsp/phytium/libraries/port/fboard_port/e2000q_demo/mnt_sdcard.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Email: opensource_embedded@phytium.com.cn + * + * Change Logs: + * Date Author Notes + * 2023-04-27 huanghe first version + * 2023-07-14 liqiaozhong add SD file sys mount func + * 2024-04-08 zhugengyu define mount table by board + */ +#include +#include + +#define DBG_TAG "mnt.filesystem" +#define DBG_LVL DBG_INFO +#include + +#define FS_SD_MOUNT_POINT "/" +#define FS_SD_DEVICE_NAME "sd1" +#define FS_SD_DEVICE_INDEX 1 + +#define FS_EMMC_MOUNT_POINT "/sd0" +#define FS_EMMC_DEVICE_NAME "sd0" +#define FS_EMMC_DEVICE_INDEX 0 + +extern void sdif_change(rt_uint32_t id); +extern rt_int32_t sdif_card_inserted(rt_uint32_t id); + +static rt_int32_t card_inserted = 0; + +static void _sdcard_mount(void) +{ + rt_device_t device; + + device = rt_device_find(FS_SD_DEVICE_NAME); + rt_kprintf("rt_device_find %x \r\n", device); + if (device == NULL) + { + mmcsd_wait_cd_changed(0); + sdif_change(FS_SD_DEVICE_INDEX); + mmcsd_wait_cd_changed(RT_WAITING_FOREVER); + device = rt_device_find(FS_SD_DEVICE_NAME); + } + + if (device != RT_NULL) + { + if (dfs_mount(FS_SD_DEVICE_NAME, FS_SD_MOUNT_POINT, "elm", 0, 0) == RT_EOK) + { + LOG_I("%s mount to '%s'", FS_SD_DEVICE_NAME, FS_SD_MOUNT_POINT); + mkdir(FS_EMMC_MOUNT_POINT, 0); + if (dfs_mount(FS_EMMC_DEVICE_NAME, FS_EMMC_MOUNT_POINT, "elm", 0, 0) == RT_EOK) + { + LOG_I("%s mount to '%s'", FS_EMMC_DEVICE_NAME, FS_EMMC_MOUNT_POINT); + } + + card_inserted = 1; + } + else + { + LOG_W("%s mount to '%s' failed!", FS_SD_DEVICE_NAME, FS_SD_MOUNT_POINT); + } + } +} + +static void _sdcard_unmount(void) +{ + rt_thread_mdelay(200); + dfs_unmount(FS_SD_MOUNT_POINT); + LOG_I("Unmount %s", FS_SD_MOUNT_POINT); + + mmcsd_wait_cd_changed(0); + sdif_change(FS_SD_DEVICE_INDEX); + mmcsd_wait_cd_changed(RT_WAITING_FOREVER); + + card_inserted = 0; +} + +static void sd_auto_mount(void *parameter) +{ + rt_thread_mdelay(20); + + /* detect eMMC */ + mmcsd_wait_cd_changed(0); + sdif_change(FS_EMMC_DEVICE_INDEX); + mmcsd_wait_cd_changed(RT_WAITING_FOREVER); + + if ((card_inserted == 0) && (sdif_card_inserted(FS_SD_DEVICE_INDEX) == 1)) + { + _sdcard_mount(); + } + + while (RT_TRUE) + { + rt_thread_mdelay(200); + + if ((card_inserted == 0) && (sdif_card_inserted(FS_SD_DEVICE_INDEX) == 1)) + { + _sdcard_mount(); + } + + if ((card_inserted == 1) && (sdif_card_inserted(FS_SD_DEVICE_INDEX) == 0)) + { + _sdcard_unmount(); + } + } +} + +static void sd_mount(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("sd_mount", sd_auto_mount, RT_NULL, + 4096, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + return; + } +} + +int filesystem_mount(void) +{ + sd_mount(); + return RT_EOK; +} +INIT_APP_EXPORT(filesystem_mount); diff --git a/bsp/phytium/libraries/port/fboard_port/firefly/mnt_sdcard.c b/bsp/phytium/libraries/port/fboard_port/firefly/mnt_sdcard.c new file mode 100644 index 00000000000..1d40e824aac --- /dev/null +++ b/bsp/phytium/libraries/port/fboard_port/firefly/mnt_sdcard.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Email: opensource_embedded@phytium.com.cn + * + * Change Logs: + * Date Author Notes + * 2023-04-27 huanghe first version + * 2023-07-14 liqiaozhong add SD file sys mount func + * 2024-04-08 zhugengyu define mount table by board + */ +#include +#include + +#define DBG_TAG "mnt.filesystem" +#define DBG_LVL DBG_INFO +#include + +#define FS_SD_MOUNT_POINT "/" +#define FS_SD_DEVICE_NAME "sd00" /* first partition of SD0 */ +#define FS_SD_DEVICE_INDEX 0 + +extern void sdif_change(rt_uint32_t id); +extern rt_int32_t sdif_card_inserted(rt_uint32_t id); + +static rt_int32_t card_inserted = 0; + +static void _sdcard_mount(void) +{ + rt_device_t device; + + device = rt_device_find(FS_SD_DEVICE_NAME); + rt_kprintf("rt_device_find %x \r\n", device); + if (device == NULL) + { + mmcsd_wait_cd_changed(0); + sdif_change(FS_SD_DEVICE_INDEX); + mmcsd_wait_cd_changed(RT_WAITING_FOREVER); + device = rt_device_find(FS_SD_DEVICE_NAME); + } + + if (device != RT_NULL) + { + if (dfs_mount(FS_SD_DEVICE_NAME, FS_SD_MOUNT_POINT, "elm", 0, 0) == RT_EOK) + { + LOG_I("%s mount to '%s'", FS_SD_DEVICE_NAME, FS_SD_MOUNT_POINT); + card_inserted = 1; + } + else + { + LOG_W("%s mount to '%s' failed!", FS_SD_DEVICE_NAME, FS_SD_MOUNT_POINT); + } + } +} + +static void _sdcard_unmount(void) +{ + rt_thread_mdelay(200); + dfs_unmount(FS_SD_MOUNT_POINT); + LOG_I("Unmount %s", FS_SD_MOUNT_POINT); + + mmcsd_wait_cd_changed(0); + sdif_change(FS_SD_DEVICE_INDEX); + mmcsd_wait_cd_changed(RT_WAITING_FOREVER); + + card_inserted = 0; +} + +static void sd_auto_mount(void *parameter) +{ + rt_thread_mdelay(20); + + if ((card_inserted == 0) && (sdif_card_inserted(FS_SD_DEVICE_INDEX) == 1)) + { + _sdcard_mount(); + } + + while (RT_TRUE) + { + rt_thread_mdelay(200); + + if ((card_inserted == 0) && (sdif_card_inserted(FS_SD_DEVICE_INDEX) == 1)) + { + _sdcard_mount(); + } + + if ((card_inserted == 1) && (sdif_card_inserted(FS_SD_DEVICE_INDEX) == 0)) + { + _sdcard_unmount(); + } + } +} + +static void sd_mount(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("sd_mount", sd_auto_mount, RT_NULL, + 4096, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + return; + } +} + +int filesystem_mount(void) +{ + sd_mount(); + return RT_EOK; +} +INIT_APP_EXPORT(filesystem_mount); diff --git a/bsp/phytium/libraries/port/fboard_port/mnt_ramdisk.c b/bsp/phytium/libraries/port/fboard_port/mnt_ramdisk.c new file mode 100644 index 00000000000..bf05816e076 --- /dev/null +++ b/bsp/phytium/libraries/port/fboard_port/mnt_ramdisk.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Email: opensource_embedded@phytium.com.cn + * + * Change Logs: + * Date Author Notes + * 2023-04-27 huanghe first version + * 2023-07-14 liqiaozhong add SD file sys mount func + * + */ +#include +#include +#ifndef RT_USING_SMART +#include +#include + +static int ram_disk_mount(const char *mount_point) +{ + extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size); + + rt_uint8_t *pool = RT_NULL; + rt_size_t size = 8 * 1024 * 1024; + + pool = rt_malloc(size); + if (pool == RT_NULL) + { + LOG_E("Malloc fail!"); + } + + if (dfs_mount(RT_NULL, mount_point, "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0) + { + LOG_I("RAM file system initializated!"); + } + else + { + LOG_E("RAM file system initializate failed!"); + } + + return RT_EOK; +} + +static int filesystem_mount(void) +{ + return ram_disk_mount("/"); /* mount ramdisk as / */ +} +INIT_APP_EXPORT(filesystem_mount); +#endif \ No newline at end of file diff --git a/bsp/phytium/libraries/port/fdriver_port/fdrivers_port.c b/bsp/phytium/libraries/port/fdriver_port/fdrivers_port.c index f80f6a04752..fb767d60925 100644 --- a/bsp/phytium/libraries/port/fdriver_port/fdrivers_port.c +++ b/bsp/phytium/libraries/port/fdriver_port/fdrivers_port.c @@ -29,12 +29,12 @@ /* cache */ void FDriverDCacheRangeFlush(uintptr_t adr, size_t len) { - __asm_flush_dcache_range(adr, len); + __asm_flush_dcache_range((void *)adr, len); } void FDriverDCacheRangeInvalidate(uintptr_t adr, size_t len) { - rt_hw_cpu_dcache_invalidate(adr, len); + rt_hw_cpu_dcache_invalidate((void *)adr, len); } void FDriverICacheRangeInvalidate(uintptr_t adr, size_t len) @@ -42,37 +42,26 @@ void FDriverICacheRangeInvalidate(uintptr_t adr, size_t len) __asm_invalidate_icache_all(); } -void FDriverMdelay(u32 msec) -{ - for(rt_uint32_t wait = 0; wait < 10000000; wait ++); -} - #else #include "rthw.h" /* cache */ void FDriverDCacheRangeFlush(uintptr_t adr, size_t len) { - rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, adr, len); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)adr, len); } void FDriverDCacheRangeInvalidate(uintptr_t adr, size_t len) { - rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, adr, len); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)adr, len); } void FDriverICacheRangeInvalidate(uintptr_t adr, size_t len) { - rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, adr, len); -} - -void FDriverMdelay(u32 msec) -{ - rt_thread_mdelay(msec); + rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, (void *)adr, len); } #endif - /* time delay */ void FDriverUdelay(u32 usec) @@ -85,3 +74,8 @@ void FDriverSdelay(u32 sec) u32 msec = sec * 1000; rt_thread_mdelay(msec); } + +void FDriverMdelay(u32 msec) +{ + rt_thread_mdelay(msec); +} diff --git a/bsp/qemu-vexpress-a9/.config b/bsp/qemu-vexpress-a9/.config index 24cc1277ed8..a172cde778b 100644 --- a/bsp/qemu-vexpress-a9/.config +++ b/bsp/qemu-vexpress-a9/.config @@ -28,7 +28,7 @@ CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=4096 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 # # kservice optimization @@ -81,7 +81,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_VER_NUM=0x50100 -# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_USING_STDC_ATOMIC=y CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 CONFIG_RT_USING_CACHE=y CONFIG_RT_USING_HW_ATOMIC=y @@ -104,7 +104,7 @@ CONFIG_ARCH_ARM_CORTEX_A9=y # CONFIG_RT_USING_COMPONENTS_INIT=y CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_STACK_SIZE=8196 CONFIG_RT_MAIN_THREAD_PRIORITY=10 CONFIG_RT_USING_LEGACY=y CONFIG_RT_USING_MSH=y @@ -172,7 +172,7 @@ CONFIG_RT_USING_DFS_MQUEUE=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y -CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8196 CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V1=y @@ -201,9 +201,9 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_ALARM is not set CONFIG_RT_USING_SOFT_RTC=y CONFIG_RT_USING_SDIO=y -CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_STACK_SIZE=4096 CONFIG_RT_SDIO_THREAD_PRIORITY=15 -CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_STACK_SIZE=16384 CONFIG_RT_MMCSD_THREAD_PREORITY=22 CONFIG_RT_MMCSD_MAX_PARTITION=16 # CONFIG_RT_SDIO_DEBUG is not set diff --git a/bsp/qemu-vexpress-a9/rtconfig.h b/bsp/qemu-vexpress-a9/rtconfig.h index eb1fd3df622..7e208cdc461 100644 --- a/bsp/qemu-vexpress-a9/rtconfig.h +++ b/bsp/qemu-vexpress-a9/rtconfig.h @@ -20,7 +20,7 @@ #define IDLE_THREAD_STACK_SIZE 4096 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 1024 +#define RT_TIMER_THREAD_STACK_SIZE 4096 /* kservice optimization */ @@ -54,6 +54,7 @@ #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_VER_NUM 0x50100 +#define RT_USING_STDC_ATOMIC #define RT_BACKTRACE_LEVEL_MAX_NR 32 #define RT_USING_CACHE #define RT_USING_HW_ATOMIC @@ -69,7 +70,7 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_STACK_SIZE 8196 #define RT_MAIN_THREAD_PRIORITY 10 #define RT_USING_LEGACY #define RT_USING_MSH @@ -119,7 +120,7 @@ #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE -#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8196 #define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 @@ -136,9 +137,9 @@ #define RT_USING_RTC #define RT_USING_SOFT_RTC #define RT_USING_SDIO -#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_STACK_SIZE 4096 #define RT_SDIO_THREAD_PRIORITY 15 -#define RT_MMCSD_STACK_SIZE 1024 +#define RT_MMCSD_STACK_SIZE 16384 #define RT_MMCSD_THREAD_PREORITY 22 #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI diff --git a/bsp/qemu-virt64-aarch64/applications/console.c b/bsp/qemu-virt64-aarch64/applications/console.c index f560206a3fd..b69b9b3b978 100644 --- a/bsp/qemu-virt64-aarch64/applications/console.c +++ b/bsp/qemu-virt64-aarch64/applications/console.c @@ -10,10 +10,6 @@ #include -#if defined(RT_USING_POSIX_DEVIO) && defined(RT_USING_SMART) -#include -#endif - #include static int console_init() @@ -36,8 +32,6 @@ static int console_init() } INIT_ENV_EXPORT(console_init); -#ifdef FINSH_USING_MSH - static int console(int argc, char **argv) { rt_err_t result = RT_EOK; @@ -48,23 +42,6 @@ static int console(int argc, char **argv) { rt_kprintf("console change to %s\n", argv[2]); rt_console_set_device(argv[2]); - - #ifdef RT_USING_POSIX_DEVIO - { - rt_device_t dev = rt_device_find(argv[2]); - - if (dev != RT_NULL) - { - #ifdef RT_USING_SMART - console_set_iodev(dev); - #else - rt_kprintf("TODO not supported\n"); - #endif - } - } - #else - finsh_set_device(argv[2]); - #endif /* RT_USING_POSIX_DEVIO */ } else { @@ -81,5 +58,3 @@ static int console(int argc, char **argv) return result; } MSH_CMD_EXPORT(console, set console name); - -#endif /* FINSH_USING_MSH */ diff --git a/bsp/qemu-virt64-aarch64/applications/main.c b/bsp/qemu-virt64-aarch64/applications/main.c index 63833efc208..4447a4f47de 100644 --- a/bsp/qemu-virt64-aarch64/applications/main.c +++ b/bsp/qemu-virt64-aarch64/applications/main.c @@ -8,7 +8,6 @@ * 2020/10/7 bernard the first version */ -#include #include int main(void) diff --git a/bsp/qemu-virt64-aarch64/drivers/drv_gpio.c b/bsp/qemu-virt64-aarch64/drivers/drv_gpio.c index 73088927a98..bcf6677d2ca 100644 --- a/bsp/qemu-virt64-aarch64/drivers/drv_gpio.c +++ b/bsp/qemu-virt64-aarch64/drivers/drv_gpio.c @@ -106,7 +106,7 @@ static void pl061_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t pl061_write8(BIT(pin + 2), !!value << pin); } -static rt_int8_t pl061_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t pl061_pin_read(struct rt_device *device, rt_base_t pin) { return !!pl061_read8((BIT(pin + 2))); } diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c index 9a2f7ba44a0..a17471fcf43 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c @@ -141,7 +141,7 @@ static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t val } -static rt_int8_t raspi_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t raspi_pin_read(struct rt_device *device, rt_base_t pin) { RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL)); return (BCM2835_GPIO_GPLEV(pin / 32) & (1 << (pin % 32)))? PIN_HIGH : PIN_LOW; diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c index c948f430b0b..728f1514b64 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c @@ -142,7 +142,7 @@ static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t val } -static rt_int8_t raspi_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t raspi_pin_read(struct rt_device *device, rt_base_t pin) { RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL)); return (BCM2835_GPIO_GPLEV(pin / 32) & (1 << (pin % 32)))? PIN_HIGH : PIN_LOW; diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c index 0067bd9f1b9..b54c96a7a99 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c @@ -180,10 +180,10 @@ static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t val prev_raspi_pin_write(pin, value); } -static rt_int8_t raspi_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t raspi_pin_read(struct rt_device *device, rt_base_t pin) { uint32_t num = pin / 32; - rt_int8_t pin_level = 0; + rt_ssize_t pin_level = 0; if(num == 0) { diff --git a/bsp/raspberry-pi/raspi4-64/.config b/bsp/raspberry-pi/raspi4-64/.config index ba0ba001b60..6e304792735 100644 --- a/bsp/raspberry-pi/raspi4-64/.config +++ b/bsp/raspberry-pi/raspi4-64/.config @@ -74,7 +74,7 @@ CONFIG_RT_USING_SLAB_AS_HEAP=y # CONFIG_RT_USING_HEAP_ISR is not set CONFIG_RT_USING_HEAP=y CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set +CONFIG_RT_USING_DEVICE_OPS=y CONFIG_RT_USING_INTERRUPT_INFO=y # CONFIG_RT_USING_THREADSAFE_PRINTF is not set CONFIG_RT_USING_SCHED_THREAD_CTX=y @@ -82,7 +82,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_VER_NUM=0x50100 -# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_USING_STDC_ATOMIC=y CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # @@ -134,12 +134,9 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y CONFIG_RT_USING_DFS=y CONFIG_DFS_USING_POSIX=y CONFIG_DFS_USING_WORKDIR=y -# CONFIG_RT_USING_DFS_MNTTABLE is not set CONFIG_DFS_FD_MAX=32 -CONFIG_RT_USING_DFS_V1=y -# CONFIG_RT_USING_DFS_V2 is not set -CONFIG_DFS_FILESYSTEMS_MAX=4 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +# CONFIG_RT_USING_DFS_V1 is not set +CONFIG_RT_USING_DFS_V2=y CONFIG_RT_USING_DFS_ELMFAT=y # @@ -167,10 +164,8 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_CROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set CONFIG_RT_USING_DFS_TMPFS=y # CONFIG_RT_USING_DFS_MQUEUE is not set -# CONFIG_RT_USING_DFS_NFS is not set # CONFIG_RT_USING_FAL is not set # @@ -267,7 +262,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 CONFIG_RT_USING_POSIX_FS=y CONFIG_RT_USING_POSIX_DEVIO=y CONFIG_RT_USING_POSIX_STDIO=y -# CONFIG_RT_USING_POSIX_POLL is not set +CONFIG_RT_USING_POSIX_POLL=y # CONFIG_RT_USING_POSIX_SELECT is not set # CONFIG_RT_USING_POSIX_EVENTFD is not set # CONFIG_RT_USING_POSIX_TIMERFD is not set diff --git a/bsp/raspberry-pi/raspi4-64/SConstruct b/bsp/raspberry-pi/raspi4-64/SConstruct index 9bbc8af56e5..55cab354639 100644 --- a/bsp/raspberry-pi/raspi4-64/SConstruct +++ b/bsp/raspberry-pi/raspi4-64/SConstruct @@ -13,7 +13,7 @@ DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + CPP = rtconfig.CPP, CXXFLAGS = rtconfig.CXXFLAGS, AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) @@ -26,9 +26,5 @@ Export('rtconfig') # prepare building environment objs = PrepareBuilding(env, RTT_ROOT) -if GetDepend('RT_USING_SMART'): - # use smart link.lds - env['LINKFLAGS'] = env['LINKFLAGS'].replace('link.lds', 'link_smart.lds') - # make a building DoBuilding(TARGET, objs) diff --git a/bsp/raspberry-pi/raspi4-64/applications/mnt.c b/bsp/raspberry-pi/raspi4-64/applications/mnt.c index ea67a4a46a8..d204e788b5f 100644 --- a/bsp/raspberry-pi/raspi4-64/applications/mnt.c +++ b/bsp/raspberry-pi/raspi4-64/applications/mnt.c @@ -10,16 +10,29 @@ #include -#ifdef BSP_USING_SDIO0 +#ifdef BSP_USING_SDIO #include int mnt_init(void) { - rt_thread_delay(RT_TICK_PER_SECOND); - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + rt_thread_delay(RT_TICK_PER_SECOND/100); + if (dfs_mount("sd1", "/", "ext", 0, 0) == 0) { rt_kprintf("file system initialization done!\n"); } + else if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("file system initialization done!\n"); + } + +#ifdef RT_USING_DFS_ROMFS + mkdir("/rom", 0777); + extern const struct romfs_dirent romfs_root; + if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) + { + rt_kprintf("ROM File System initialized!\n"); + } +#endif return 0; } diff --git a/bsp/raspberry-pi/raspi4-64/drivers/board.c b/bsp/raspberry-pi/raspi4-64/drivers/board.c index babc073166f..e66a4bc09ed 100644 --- a/bsp/raspberry-pi/raspi4-64/drivers/board.c +++ b/bsp/raspberry-pi/raspi4-64/drivers/board.c @@ -10,6 +10,9 @@ * 2023-03-28 WangXiaoyao sync works & memory layout fixups * code formats */ +#define DBG_TAG "board" +#define DBG_LVL DBG_INFO +#include #include #include @@ -60,7 +63,7 @@ struct mem_desc platform_mem_desc[] = { }; #else struct mem_desc platform_mem_desc[] = { - {0x00200000, (128ul << 20) - 1, 0x00200000, NORMAL_MEM}, + {0x00200000, (256ul << 20) - 1, 0x00200000, NORMAL_MEM}, {0xFC000000, 0x000100000000 - 1, 0xFC000000, DEVICE_MEM}, }; #endif @@ -90,12 +93,14 @@ rt_region_t init_page_region = { */ void rt_hw_board_init(void) { + rt_hw_earlycon_ioremap_early(); + /* io device remap */ #ifdef RT_USING_SMART rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET); #else - rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x000400000000, 0x10000000, MMUTable, 0); -#endif + rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x080000000000, 0x10000000, MMUTable, 0); +#endif /* RT_USING_SMART */ rt_page_init(init_page_region); rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size); @@ -147,8 +152,6 @@ void rt_hw_board_init(void) rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif /* RT_USING_CONSOLE */ - rt_kprintf("heap: 0x%08x - 0x%08x\n", HEAP_BEGIN, HEAP_END); - #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif @@ -170,33 +173,6 @@ static unsigned long cpu_release_paddr[] = [4] = 0x00 }; -#ifndef RT_USING_SMART -static void *_remap(void *paddr, size_t size) -{ - int ret; - static void *va = 0; - size_t low_off = (size_t)paddr & ARCH_PAGE_MASK; - if (va) - return va + low_off; - - va = rt_kernel_space.start; - while (1) - { - int rt_kmem_map_phy(void *va, void *pa, rt_size_t length, rt_size_t attr); - ret = rt_kmem_map_phy(va, 0x0, ARCH_PAGE_SIZE, MMU_MAP_K_DEVICE); - if (ret == RT_EOK) - { - break; - } - else - { - va += ARCH_PAGE_SIZE; - } - } - return va + low_off; -} -#endif /* RT_USING_SMART */ - void rt_hw_secondary_cpu_up(void) { int i; @@ -204,11 +180,7 @@ void rt_hw_secondary_cpu_up(void) for (i = 1; i < RT_CPUS_NR && cpu_release_paddr[i]; ++i) { -#ifdef RT_USING_SMART release_addr = rt_ioremap((void *)cpu_release_paddr[i], sizeof(cpu_release_paddr[0])); -#else - release_addr = _remap((void *)cpu_release_paddr[i], sizeof(cpu_release_paddr[0])); -#endif __asm__ volatile ("str %0, [%1]"::"rZ"((unsigned long)_secondary_cpu_entry + PV_OFFSET), "r"(release_addr)); rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, release_addr, sizeof(release_addr)); asm volatile ("dsb sy"); diff --git a/bsp/raspberry-pi/raspi4-64/drivers/board.h b/bsp/raspberry-pi/raspi4-64/drivers/board.h index 9bab3223953..9d28915ba32 100644 --- a/bsp/raspberry-pi/raspi4-64/drivers/board.h +++ b/bsp/raspberry-pi/raspi4-64/drivers/board.h @@ -26,9 +26,9 @@ extern int __bss_end; #else #define KERNEL_VADDR_START 0x0 -#define HEAP_END (KERNEL_VADDR_START + 64 * 1024 * 1024) +#define HEAP_END (KERNEL_VADDR_START + 32 * 1024 * 1024) #define PAGE_START HEAP_END -#define PAGE_END ((size_t)PAGE_START + 64 * 1024 * 1024) +#define PAGE_END ((size_t)PAGE_START + 128 * 1024 * 1024) #endif void rt_hw_board_init(void); diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_eth.c b/bsp/raspberry-pi/raspi4-64/drivers/drv_eth.c index 317cd54dd08..81380896c5f 100644 --- a/bsp/raspberry-pi/raspi4-64/drivers/drv_eth.c +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_eth.c @@ -20,9 +20,9 @@ #include "raspi4.h" #include "drv_eth.h" -#define DBG_LEVEL DBG_LOG +#define LOG_LVL DBG_LOG +#define LOG_TAG "drv.eth" #include -#define LOG_TAG "drv.eth" static int link_speed = 0; static int link_flag = 0; @@ -536,17 +536,17 @@ static void link_task_entry(void *param) if ((bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 10)) || (bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 11))) { link_speed = 1000; - rt_kprintf("Support link mode Speed 1000M\n"); + LOG_I("Support link mode Speed 1000M\n"); } else if ((bcmgenet_mdio_read(1, 0x05) & (1 << 7)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 8)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 9))) { link_speed = 100; - rt_kprintf("Support link mode Speed 100M\n"); + LOG_I("Support link mode Speed 100M\n"); } else { link_speed = 10; - rt_kprintf("Support link mode Speed 10M\n"); + LOG_I("Support link mode Speed 10M\n"); } bcmgenet_gmac_eth_start(); @@ -573,7 +573,7 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device) else if (major == 0) major = 1; - rt_kprintf("Uns upported GENETv%d.%d\n", major, (hw_reg >> 16) & 0x0f); + LOG_W("Unsupported GENETv%d.%d\n", major, (hw_reg >> 16) & 0x0f); return -RT_ERROR; } /* set interface */ @@ -623,7 +623,7 @@ rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p) /* lock eth device */ if (link_flag != 1) { - rt_kprintf("link disconnected\n"); + LOG_I("link disconnected\n"); return -RT_ERROR; } @@ -631,7 +631,7 @@ rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p) if (copy_len == 0) { - rt_kprintf("copy len is zero\n"); + LOG_I("copy len is zero\n"); return -RT_ERROR; } bcmgenet_gmac_eth_send((void *)eth_send_no_cache, p->tot_len); @@ -664,9 +664,16 @@ struct pbuf *rt_eth_rx(rt_device_t device) return pbuf; } +#ifdef RT_USING_DEVICE_OPS +static struct rt_device_ops eth_devops = { + .init = bcmgenet_eth_init, + .control = bcmgenet_eth_control, +}; +#endif /* RT_USING_DEVICE_OPS */ + int rt_hw_eth_init(void) { - rt_uint8_t mac_addr[6]; + rt_uint8_t mac_addr[6] = {0xdc, 0xa6, 0x32, 0x28, 0x22, 0x50}; rt_sem_init(&link_ack, "link_ack", 0, RT_IPC_FLAG_FIFO); @@ -685,12 +692,16 @@ int rt_hw_eth_init(void) eth_dev.dev_addr[5] = mac_addr[5]; eth_dev.parent.parent.type = RT_Device_Class_NetIf; +#ifdef RT_USING_DEVICE_OPS + eth_dev.parent.parent.ops = ð_devops; +#else /* !RT_USING_DEVICE_OPS */ eth_dev.parent.parent.init = bcmgenet_eth_init; eth_dev.parent.parent.open = RT_NULL; eth_dev.parent.parent.close = RT_NULL; eth_dev.parent.parent.read = RT_NULL; eth_dev.parent.parent.write = RT_NULL; eth_dev.parent.parent.control = bcmgenet_eth_control; +#endif /* RT_USING_DEVICE_OPS */ eth_dev.parent.parent.user_data = RT_NULL; eth_dev.parent.eth_tx = rt_eth_tx; diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_gpio.c b/bsp/raspberry-pi/raspi4-64/drivers/drv_gpio.c index ff284e546bb..602d508e6b8 100644 --- a/bsp/raspberry-pi/raspi4-64/drivers/drv_gpio.c +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_gpio.c @@ -180,10 +180,10 @@ static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t val prev_raspi_pin_write(pin, value); } -static rt_int8_t raspi_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t raspi_pin_read(struct rt_device *device, rt_base_t pin) { uint32_t num = pin / 32; - uint32_t pin_level = 0; + rt_ssize_t pin_level = 0; if(num == 0) { diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_uart.c b/bsp/raspberry-pi/raspi4-64/drivers/drv_uart.c index 2479d3e6441..5d4b07a9fb7 100644 --- a/bsp/raspberry-pi/raspi4-64/drivers/drv_uart.c +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_uart.c @@ -187,8 +187,8 @@ static const struct rt_uart_ops _uart_ops = uart_getc, }; -void *earlycon_base = (void *)AUX_BASE; -size_t earlycon_size = 0x1000; +volatile void *earlycon_base = 0; +const size_t earlycon_size = 0x1000; extern void early_putc(int c) { @@ -200,6 +200,11 @@ extern void early_putc(int c) AUX_MU_IO_REG(earlycon_base) = c; } +void rt_hw_earlycon_ioremap_early(void) +{ + earlycon_base = rt_ioremap_early((void *)AUX_BASE, earlycon_size); +} + void rt_hw_console_output(const char *str) { if (earlycon_base) @@ -230,7 +235,7 @@ void early_printhex(rt_ubase_t number) #ifdef RT_USING_UART1 static void rt_hw_aux_uart_isr(int irqno, void *param) { - struct rt_serial_device *serial = (struct rt_serial_device*)param; + struct rt_serial_device *serial = (struct rt_serial_device*)param; rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } #endif @@ -239,7 +244,7 @@ static void rt_hw_uart_isr(int irqno, void *param) { #ifdef RT_USING_UART0 if((PACTL_CS & IRQ_UART0) == IRQ_UART0) - { + { PACTL_CS &= ~(IRQ_UART0); rt_hw_serial_isr(&_serial0, RT_SERIAL_EVENT_RX_IND); PL011_REG_ICR(uart0_addr) = PL011_INTERRUPT_RECEIVE; @@ -333,13 +338,13 @@ int rt_hw_uart_init(void) earlycon_base = (void *)uart0_addr; uart0->hw_base = uart0_addr; - + /* register UART0 device */ rt_hw_serial_register(&_serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart0); rt_hw_interrupt_install(uart0->irqno, rt_hw_uart_isr, &_serial0, "uart0"); - + #endif #ifdef RT_USING_UART1 @@ -348,7 +353,7 @@ int rt_hw_uart_init(void) _serial1.ops = &_uart_ops; _serial1.config = config; - + uart1->hw_base = (size_t)rt_ioremap((void*)AUX_BASE, 0x1000); /* register UART1 device */ diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_uart.h b/bsp/raspberry-pi/raspi4-64/drivers/drv_uart.h index 89612004538..4b2c565c318 100644 --- a/bsp/raspberry-pi/raspi4-64/drivers/drv_uart.h +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_uart.h @@ -103,5 +103,6 @@ #define AUX_SPI1_CNTL1_REG(BASE) HWREG32(BASE + 0xC4) /* SPI 2 Control register 1 8bit */ int rt_hw_uart_init(void); +void rt_hw_earlycon_ioremap_early(void); #endif /* DRV_UART_H__ */ diff --git a/bsp/raspberry-pi/raspi4-64/drivers/drv_wdt.c b/bsp/raspberry-pi/raspi4-64/drivers/drv_wdt.c index 8eac6e7659a..ce7e8c2a6c0 100644 --- a/bsp/raspberry-pi/raspi4-64/drivers/drv_wdt.c +++ b/bsp/raspberry-pi/raspi4-64/drivers/drv_wdt.c @@ -116,7 +116,7 @@ int rt_hw_wdt_init(void) } INIT_DEVICE_EXPORT(rt_hw_wdt_init); -void reboot(void) +void rt_hw_cpu_reset(void) { unsigned int r; @@ -128,8 +128,8 @@ void reboot(void) PM_RSTS |= (PM_PASSWORD | r); // boot from partition 0 PM_WDOG |= (PM_PASSWORD | 0x0A); PM_RSTC |= (PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET); - + while (1); } -MSH_CMD_EXPORT(reboot,reboot system...); +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reboot system...); #endif /*BSP_USING_WDT */ diff --git a/bsp/raspberry-pi/raspi4-64/link.lds b/bsp/raspberry-pi/raspi4-64/link.lds deleted file mode 100644 index b859ddefe7d..00000000000 --- a/bsp/raspberry-pi/raspi4-64/link.lds +++ /dev/null @@ -1,109 +0,0 @@ -OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") -OUTPUT_ARCH(aarch64) -SECTIONS -{ - . = 0x208000; - /* . = 0xffff000000008000; */ - - __text_start = .; - .text : - { - KEEP(*(.text.entrypoint)) - KEEP(*(.vectors)) - *(.text) - *(.text.*) - - /* section information for utest */ - . = ALIGN(4); - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* section information for initialization */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - } =0 - __text_end = .; - - .ARM.exidx : - { - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - } - - __rodata_start = .; - .rodata : { *(.rodata) *(.rodata.*) } - __rodata_end = .; - - . = ALIGN(4); - .ctors : - { - PROVIDE(__ctors_start__ = .); - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - } - - .dtors : - { - PROVIDE(__dtors_start__ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(__dtors_end__ = .); - } - - . = ALIGN(8); - __data_start = .; - .data : - { - *(.data) - *(.data.*) - } - __data_end = .; - - . = ALIGN(8); - __bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - } - . = ALIGN(4); - __bss_end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - - __data_size = SIZEOF(.data); - __bss_size = SIZEOF(.bss); - - _end = .; -} diff --git a/bsp/raspberry-pi/raspi4-64/link_smart.lds b/bsp/raspberry-pi/raspi4-64/link_smart.lds deleted file mode 100644 index 435053f8919..00000000000 --- a/bsp/raspberry-pi/raspi4-64/link_smart.lds +++ /dev/null @@ -1,109 +0,0 @@ -OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") -OUTPUT_ARCH(aarch64) -SECTIONS -{ - /* . = 0x208000; */ - . = 0xffff000000008000; - - __text_start = .; - .text : - { - KEEP(*(.text.entrypoint)) - KEEP(*(.vectors)) - *(.text) - *(.text.*) - - /* section information for utest */ - . = ALIGN(4); - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* section information for initialization */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - } =0 - __text_end = .; - - .ARM.exidx : - { - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - } - - __rodata_start = .; - .rodata : { *(.rodata) *(.rodata.*) } - __rodata_end = .; - - . = ALIGN(4); - .ctors : - { - PROVIDE(__ctors_start__ = .); - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - } - - .dtors : - { - PROVIDE(__dtors_start__ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(__dtors_end__ = .); - } - - . = ALIGN(8); - __data_start = .; - .data : - { - *(.data) - *(.data.*) - } - __data_end = .; - - . = ALIGN(8); - __bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - } - . = ALIGN(4); - __bss_end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - - __data_size = SIZEOF(.data); - __bss_size = SIZEOF(.bss); - - _end = .; -} diff --git a/bsp/raspberry-pi/raspi4-64/rtconfig.h b/bsp/raspberry-pi/raspi4-64/rtconfig.h index 0748d8d9fa0..75d2e110b67 100644 --- a/bsp/raspberry-pi/raspi4-64/rtconfig.h +++ b/bsp/raspberry-pi/raspi4-64/rtconfig.h @@ -47,12 +47,14 @@ #define RT_USING_SLAB_AS_HEAP #define RT_USING_HEAP #define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS #define RT_USING_INTERRUPT_INFO #define RT_USING_SCHED_THREAD_CTX #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_VER_NUM 0x50100 +#define RT_USING_STDC_ATOMIC #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* AArch64 Architecture Configuration */ @@ -96,9 +98,7 @@ #define DFS_USING_POSIX #define DFS_USING_WORKDIR #define DFS_FD_MAX 32 -#define RT_USING_DFS_V1 -#define DFS_FILESYSTEMS_MAX 4 -#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_V2 #define RT_USING_DFS_ELMFAT /* elm-chan's FatFs, Generic FAT Filesystem Module */ @@ -169,6 +169,7 @@ #define RT_USING_POSIX_FS #define RT_USING_POSIX_DEVIO #define RT_USING_POSIX_STDIO +#define RT_USING_POSIX_POLL #define RT_USING_POSIX_TERMIOS #define RT_USING_POSIX_DELAY #define RT_USING_POSIX_CLOCK diff --git a/bsp/raspberry-pi/raspi4-64/rtconfig.py b/bsp/raspberry-pi/raspi4-64/rtconfig.py index ded95340fcb..17edd896c51 100644 --- a/bsp/raspberry-pi/raspi4-64/rtconfig.py +++ b/bsp/raspberry-pi/raspi4-64/rtconfig.py @@ -14,7 +14,7 @@ CROSS_TOOL = os.getenv('RTT_CC') PLATFORM = 'gcc' -EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/' +EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -25,7 +25,7 @@ # toolchains PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-' CC = PREFIX + 'gcc' - CXX = PREFIX + 'g++' + CPP = PREFIX + 'g++' AS = PREFIX + 'gcc' AR = PREFIX + 'ar' LINK = PREFIX + 'gcc' @@ -35,9 +35,10 @@ OBJCPY = PREFIX + 'objcopy' DEVICE = ' -march=armv8-a -mtune=cortex-a72' + CPPFLAGS = ' -E -P -x assembler-with-cpp' CFLAGS = DEVICE + ' -Wall -Wno-cpp -D_POSIX_SOURCE' AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__' - LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' CPATH = '' LPATH = '' diff --git a/bsp/raspberry-pico/.ci/attachconfig/c-posix.attach b/bsp/raspberry-pico/.ci/attachconfig/c-posix.attach new file mode 100644 index 00000000000..95008fa70be --- /dev/null +++ b/bsp/raspberry-pico/.ci/attachconfig/c-posix.attach @@ -0,0 +1,2 @@ +# scons: --strict +CONFIG_RT_USING_CPLUSPLUS=y diff --git a/bsp/raspberry-pico/.ci/attachconfig/rtduino/communication.attach b/bsp/raspberry-pico/.ci/attachconfig/rtduino/communication.attach new file mode 100644 index 00000000000..61a3b7e3177 --- /dev/null +++ b/bsp/raspberry-pico/.ci/attachconfig/rtduino/communication.attach @@ -0,0 +1,4 @@ +CONFIG_BSP_USING_ARDUINO=y + +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713=y diff --git a/bsp/raspberry-pico/.ci/attachconfig/rtduino.attach b/bsp/raspberry-pico/.ci/attachconfig/rtduino/dataprocessing.attach similarity index 64% rename from bsp/raspberry-pico/.ci/attachconfig/rtduino.attach rename to bsp/raspberry-pico/.ci/attachconfig/rtduino/dataprocessing.attach index 55e991c8024..d833d95631d 100644 --- a/bsp/raspberry-pico/.ci/attachconfig/rtduino.attach +++ b/bsp/raspberry-pico/.ci/attachconfig/rtduino/dataprocessing.attach @@ -1,6 +1,6 @@ -# scons: --strict CONFIG_BSP_USING_ARDUINO=y -# check some important arduino libraries +CONFIG_PKG_USING_ARDUINO_ARDUINOJSON=y +CONFIG_PKG_USING_ARDUINO_KALMANFILTER=y CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO=y CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO_EXAMPLE_HELLO_WORLD=y diff --git a/bsp/raspberry-pico/.ci/attachconfig/rtduino/devicecontrol.attach b/bsp/raspberry-pico/.ci/attachconfig/rtduino/devicecontrol.attach new file mode 100644 index 00000000000..b816e5bf55a --- /dev/null +++ b/bsp/raspberry-pico/.ci/attachconfig/rtduino/devicecontrol.attach @@ -0,0 +1,9 @@ +CONFIG_BSP_USING_ARDUINO=y + +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502=y +CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP=y diff --git a/bsp/raspberry-pico/.ci/attachconfig/rtduino/display.attach b/bsp/raspberry-pico/.ci/attachconfig/rtduino/display.attach new file mode 100644 index 00000000000..8019bd9c281 --- /dev/null +++ b/bsp/raspberry-pico/.ci/attachconfig/rtduino/display.attach @@ -0,0 +1,10 @@ +CONFIG_BSP_USING_ARDUINO=y + +# Adafruit Drivers +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735=y + +# u8g2 +CONFIG_PKG_USING_ARDUINO_U8G2=y diff --git a/bsp/raspberry-pico/.ci/attachconfig/rtduino/other.attach b/bsp/raspberry-pico/.ci/attachconfig/rtduino/other.attach new file mode 100644 index 00000000000..b731b70a8b2 --- /dev/null +++ b/bsp/raspberry-pico/.ci/attachconfig/rtduino/other.attach @@ -0,0 +1,4 @@ +CONFIG_BSP_USING_ARDUINO=y + +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351=y diff --git a/bsp/raspberry-pico/.ci/attachconfig/rtduino/projects.attach b/bsp/raspberry-pico/.ci/attachconfig/rtduino/projects.attach new file mode 100644 index 00000000000..48c9c4f1a1b --- /dev/null +++ b/bsp/raspberry-pico/.ci/attachconfig/rtduino/projects.attach @@ -0,0 +1,5 @@ +CONFIG_BSP_USING_ARDUINO=y +CONFIG_PKG_USING_ARDUINO_SENSOR_KIT=y +CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR=y +CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO=y +CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD=y diff --git a/bsp/raspberry-pico/.ci/attachconfig/rtduino/rtduino.attach b/bsp/raspberry-pico/.ci/attachconfig/rtduino/rtduino.attach new file mode 100644 index 00000000000..c14014d5c7e --- /dev/null +++ b/bsp/raspberry-pico/.ci/attachconfig/rtduino/rtduino.attach @@ -0,0 +1,2 @@ +# scons: --strict +CONFIG_BSP_USING_ARDUINO=y diff --git a/bsp/raspberry-pico/.ci/attachconfig/rtduino/sensors-adafruit.attach b/bsp/raspberry-pico/.ci/attachconfig/rtduino/sensors-adafruit.attach new file mode 100644 index 00000000000..b5002c42469 --- /dev/null +++ b/bsp/raspberry-pico/.ci/attachconfig/rtduino/sensors-adafruit.attach @@ -0,0 +1,105 @@ +CONFIG_BSP_USING_ARDUINO=y + +# Adafruit Sensor Libraries Check +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0=y +CONFIG_ARDUINO_ADAFRUIT_AHTX0_USING_SENSOR_DEVICE=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700=y diff --git a/bsp/raspberry-pico/.ci/attachconfig/rtduino/sensors-others.attach b/bsp/raspberry-pico/.ci/attachconfig/rtduino/sensors-others.attach new file mode 100644 index 00000000000..716dbcf0684 --- /dev/null +++ b/bsp/raspberry-pico/.ci/attachconfig/rtduino/sensors-others.attach @@ -0,0 +1,4 @@ +CONFIG_BSP_USING_ARDUINO=y + +# Other Sensors +CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR=y diff --git a/bsp/raspberry-pico/.ci/attachconfig/rtduino/sensors-seeed.attach b/bsp/raspberry-pico/.ci/attachconfig/rtduino/sensors-seeed.attach new file mode 100644 index 00000000000..753062eccc1 --- /dev/null +++ b/bsp/raspberry-pico/.ci/attachconfig/rtduino/sensors-seeed.attach @@ -0,0 +1,35 @@ +CONFIG_BSP_USING_ARDUINO=y + +# Seeed Sensors +CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR=y +CONFIG_PKG_USING_ARDUINO_SEEED_DHT=y +CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335=y +CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345=y +CONFIG_PKG_USING_ARDUINO_SEEED_BME280=y +CONFIG_PKG_USING_ARDUINO_SEEED_BMP280=y +CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL=y +CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660=y +CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561=y +CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620=y +#CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X=y +#CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200=y +CONFIG_PKG_USING_ARDUINO_SEEED_SHT31=y +CONFIG_PKG_USING_ARDUINO_SEEED_HP20X=y +#CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L=y +CONFIG_PKG_USING_ARDUINO_SEEED_BBM150=y +#CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L=y +CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH=y +CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS=y +CONFIG_PKG_USING_ARDUINO_SEEED_MP503=y +CONFIG_PKG_USING_ARDUINO_SEEED_BMP085=y +CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP=y +CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070=y +CONFIG_PKG_USING_ARDUINO_SEEED_SI1145=y +CONFIG_PKG_USING_ARDUINO_SEEED_SHT35=y +CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070=y +CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3=y +CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000=y +CONFIG_PKG_USING_ARDUINO_SEEED_HM3301=y +CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600=y +CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941=y +CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612=y diff --git a/bsp/raspberry-pico/.ci/attachconfig/rtduino/signalio.attach b/bsp/raspberry-pico/.ci/attachconfig/rtduino/signalio.attach new file mode 100644 index 00000000000..035acf75272 --- /dev/null +++ b/bsp/raspberry-pico/.ci/attachconfig/rtduino/signalio.attach @@ -0,0 +1,11 @@ +CONFIG_BSP_USING_ARDUINO=y + +# Adafruit Signal IO Drivers +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725=y +CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS=y diff --git a/bsp/raspberry-pico/.ci/attachconfig/rtduino/timing.attach b/bsp/raspberry-pico/.ci/attachconfig/rtduino/timing.attach new file mode 100644 index 00000000000..d7698dad7c2 --- /dev/null +++ b/bsp/raspberry-pico/.ci/attachconfig/rtduino/timing.attach @@ -0,0 +1,6 @@ +CONFIG_BSP_USING_ARDUINO=y + +CONFIG_PKG_USING_ARDUINO_RTCLIB=y +CONFIG_PKG_USING_ARDUINO_MSTIMER2=y +#CONFIG_PKG_USING_ARDUINO_TICKER=y +CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER=y diff --git a/bsp/raspberry-pico/applications/arduino_pinout/SConscript b/bsp/raspberry-pico/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/raspberry-pico/applications/arduino_pinout/SConscript +++ b/bsp/raspberry-pico/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/raspberry-pico/applications/arduino_pinout/pins_arduino.c b/bsp/raspberry-pico/applications/arduino_pinout/pins_arduino.c index f497891722d..30975e42398 100644 --- a/bsp/raspberry-pico/applications/arduino_pinout/pins_arduino.c +++ b/bsp/raspberry-pico/applications/arduino_pinout/pins_arduino.c @@ -11,6 +11,14 @@ #include #include #include "pins_arduino.h" +#include +#include +#include +#include + +#define DBG_TAG "RTduino.pins_arduino" +#define DBG_LVL DBG_INFO +#include /* * {Arduino Pin, RT-Thread Pin [, Device Name, Channel]} @@ -51,3 +59,28 @@ const pin_map_t pin_map_table[]= {A1, 27, "adc1", 1}, /* ADC */ {A2, 28, "adc2", 2}, /* ADC */ }; + +#ifdef RTDUINO_USING_SPI +void switchToSPI(const char *bus_name) +{ + if(!rt_strcmp(bus_name, "spi0")) + { + /**SPI0 GPIO Configuration + 18u ------> SPI0_SCK + 16u ------> SPI0_MISO + 19u ------> SPI0_MOSI + 17u ------> SPI0_CS + */ + gpio_set_function(BSP_SPI0_SCK_PIN, GPIO_FUNC_SPI); + gpio_set_function(BSP_SPI0_MISO_PIN, GPIO_FUNC_SPI); + gpio_set_function(BSP_SPI0_MOSI_PIN, GPIO_FUNC_SPI); + gpio_init(BSP_SPI0_CS_PIN); + // Make the SPI pins available to picotool + bi_decl(bi_3pins_with_func(BSP_SPI0_MISO_PIN, BSP_SPI0_MOSI_PIN, BSP_SPI0_SCK_PIN, GPIO_FUNC_SPI)); + // Make the CS pin available to picotool + bi_decl(bi_1pin_with_name(BSP_SPI0_CS_PIN, "SPI CS")); + + LOG_I("D16, D17, D18 and D19 will switch from PWM to SPI"); + } +} +#endif /* RTDUINO_USING_SPI */ diff --git a/bsp/raspberry-pico/applications/arduino_pinout/pins_arduino.h b/bsp/raspberry-pico/applications/arduino_pinout/pins_arduino.h index 4c1b8c1f6da..b48c0b0cfbe 100644 --- a/bsp/raspberry-pico/applications/arduino_pinout/pins_arduino.h +++ b/bsp/raspberry-pico/applications/arduino_pinout/pins_arduino.h @@ -51,4 +51,10 @@ /* Serial2 : P-TX P-RX */ #define RTDUINO_SERIAL2_DEVICE_NAME "uart1" +#define SS D17 +#define RTDUINO_DEFAULT_SPI_BUS_NAME "spi0" + +/* i2c0 : D4-SDA D5-SCL */ +#define RTDUINO_DEFAULT_IIC_BUS_NAME "i2c0" + #endif /* Pins_Arduino_h */ diff --git a/bsp/raspberry-pico/board/Kconfig b/bsp/raspberry-pico/board/Kconfig index 53dac120357..a2d6677a98f 100644 --- a/bsp/raspberry-pico/board/Kconfig +++ b/bsp/raspberry-pico/board/Kconfig @@ -22,6 +22,10 @@ menu "Onboard Peripheral Drivers" select BSP_USING_PWM7 select BSP_USING_I2C select BSP_USING_I2C0 + select BSP_USING_SPI + select BSP_USING_SPI0 + select RTDUINO_USING_WIRE + select RTDUINO_USING_SPI imply RTDUINO_USING_SERVO default n @@ -158,15 +162,15 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_SOFT_SPI0 config BSP_S_SPI0_SCK_PIN - int "spi0 sck pin number (GP)" + int "spi0 SCK pin number (GP)" range 0 28 default 6 config BSP_S_SPI0_MOSI_PIN - int "spi0 mosi pin number (GP)" + int "spi0 MOSI pin number (GP)" range 0 28 default 7 config BSP_S_SPI0_MISO_PIN - int "spi0 miso pin number (GP)" + int "spi0 MISO pin number (GP)" range 0 28 default 4 endif @@ -175,15 +179,15 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_SOFT_SPI1 config BSP_S_SPI1_SCK_PIN - int "spi1 sck pin number (GP)" + int "spi1 SCK pin number (GP)" range 0 28 default 10 config BSP_S_SPI1_MOSI_PIN - int "spi1 mosi pin number (GP)" + int "spi1 MOSI pin number (GP)" range 0 28 default 11 config BSP_S_SPI1_MISO_PIN - int "spi1 miso pin number (GP)" + int "spi1 MISO pin number (GP)" range 0 28 default 12 endif @@ -227,66 +231,66 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_SPI0 choice - prompt "spi0 tx pin number (GP)" + prompt "spi0 MOSI pin number (GP)" depends on BSP_USING_SPI0 - default BSP_SPI0_TX_PIN_3 - config BSP_SPI0_TX_PIN_3 + default BSP_SPI0_MOSI_PIN_19 if BSP_USING_ARDUINO + config BSP_SPI0_MOSI_PIN_19 + bool "19" + config BSP_SPI0_MOSI_PIN_3 bool "3" - config BSP_SPI0_TX_PIN_7 + config BSP_SPI0_MOSI_PIN_7 bool "7" - config BSP_SPI0_TX_PIN_19 - bool "19" endchoice - config BSP_SPI0_TX_PIN + config BSP_SPI0_MOSI_PIN int - default 3 if BSP_SPI0_TX_PIN_3 - default 7 if BSP_SPI0_TX_PIN_7 - default 19 if BSP_SPI0_TX_PIN_19 + default 3 if BSP_SPI0_MOSI_PIN_3 + default 7 if BSP_SPI0_MOSI_PIN_7 + default 19 if BSP_SPI0_MOSI_PIN_19 choice - prompt "spi0 rx pin number (GP)" + prompt "spi0 MISO pin number (GP)" depends on BSP_USING_SPI0 - default BSP_SPI0_RX_PIN_4 - config BSP_SPI0_RX_PIN_0 + default BSP_SPI0_MISO_PIN_16 if BSP_USING_ARDUINO + config BSP_SPI0_MISO_PIN_16 + bool "16" + config BSP_SPI0_MISO_PIN_0 bool "0" - config BSP_SPI0_RX_PIN_4 + config BSP_SPI0_MISO_PIN_4 bool "4" - config BSP_SPI0_RX_PIN_16 - bool "16" endchoice - config BSP_SPI0_RX_PIN + config BSP_SPI0_MISO_PIN int - default 0 if BSP_SPI0_RX_PIN_0 - default 4 if BSP_SPI0_RX_PIN_4 - default 16 if BSP_SPI0_RX_PIN_16 + default 0 if BSP_SPI0_MISO_PIN_0 + default 4 if BSP_SPI0_MISO_PIN_4 + default 16 if BSP_SPI0_MISO_PIN_16 choice - prompt "spi0 sck pin number (GP)" + prompt "spi0 SCK pin number (GP)" depends on BSP_USING_SPI0 - default BSP_SPI0_SCK_PIN_2 + default BSP_SPI0_SCK_PIN_18 if BSP_USING_ARDUINO + config BSP_SPI0_SCK_PIN_18 + bool "18" config BSP_SPI0_SCK_PIN_2 bool "2" config BSP_SPI0_SCK_PIN_6 bool "6" - config BSP_SPI0_SCK_PIN_8 - bool "8" endchoice config BSP_SPI0_SCK_PIN int default 2 if BSP_SPI0_SCK_PIN_2 default 6 if BSP_SPI0_SCK_PIN_6 - default 8 if BSP_SPI0_SCK_PIN_8 + default 18 if BSP_SPI0_SCK_PIN_18 choice - prompt "spi0 cs pin number (GP)" + prompt "spi0 CS pin number (GP)" depends on BSP_USING_SPI0 - default BSP_SPI0_CS_PIN_5 + default BSP_SPI0_CS_PIN_17 if BSP_USING_ARDUINO + config BSP_SPI0_CS_PIN_17 + bool "17" config BSP_SPI0_CS_PIN_1 bool "1" config BSP_SPI0_CS_PIN_5 bool "5" - config BSP_SPI0_CS_PIN_17 - bool "17" endchoice config BSP_SPI0_CS_PIN int @@ -300,41 +304,41 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_SPI1 choice - prompt "spi1 tx pin number (GP)" + prompt "spi1 MOSI pin number (GP)" depends on BSP_USING_SPI1 - default BSP_SPI1_TX_PIN_11 - config BSP_SPI1_TX_PIN_11 - bool "11" - config BSP_SPI1_TX_PIN_15 + default BSP_SPI1_MOSI_PIN_15 if BSP_USING_ARDUINO + config BSP_SPI1_MOSI_PIN_15 bool "15" + config BSP_SPI1_MOSI_PIN_11 + bool "11" endchoice - config BSP_SPI1_TX_PIN + config BSP_SPI1_MOSI_PIN int - default 11 if BSP_SPI1_TX_PIN_11 - default 15 if BSP_SPI1_TX_PIN_15 + default 11 if BSP_SPI1_MOSI_PIN_11 + default 15 if BSP_SPI1_MOSI_PIN_15 choice - prompt "spi1 rx pin number (GP)" + prompt "spi1 MISO pin number (GP)" depends on BSP_USING_SPI1 - default BSP_SPI1_RX_PIN_12 - config BSP_SPI1_RX_PIN_8 - bool "8" - config BSP_SPI1_RX_PIN_12 + default BSP_SPI1_MISO_PIN_12 if BSP_USING_ARDUINO + config BSP_SPI1_MISO_PIN_12 bool "12" + config BSP_SPI1_MISO_PIN_8 + bool "8" endchoice - config BSP_SPI1_RX_PIN + config BSP_SPI1_MISO_PIN int - default 8 if BSP_SPI1_RX_PIN_8 - default 12 if BSP_SPI1_RX_PIN_12 + default 8 if BSP_SPI0_MISO_PIN_8 + default 12 if BSP_SPI0_MISO_PIN_12 choice - prompt "spi1 sck pin number (GP)" - depends on BSP_USING_SPI0 - default BSP_SPI1_SCK_PIN_10 - config BSP_SPI1_SCK_PIN_10 - bool "10" + prompt "spi1 SCK pin number (GP)" + depends on BSP_USING_SPI1 + default BSP_SPI1_SCK_PIN_14 if BSP_USING_ARDUINO config BSP_SPI1_SCK_PIN_14 bool "14" + config BSP_SPI1_SCK_PIN_10 + bool "10" endchoice config BSP_SPI1_SCK_PIN int @@ -342,13 +346,13 @@ menu "On-chip Peripheral Drivers" default 14 if BSP_SPI1_SCK_PIN_14 choice - prompt "spi1 cs pin number (GP)" + prompt "spi1 CS pin number (GP)" depends on BSP_USING_SPI0 - default BSP_SPI1_CS_PIN_13 - config BSP_SPI1_CS_PIN_9 - bool "9" + default BSP_SPI1_CS_PIN_13 if BSP_USING_ARDUINO config BSP_SPI1_CS_PIN_13 bool "13" + config BSP_SPI1_CS_PIN_9 + bool "9" endchoice config BSP_SPI1_CS_PIN int @@ -692,11 +696,11 @@ menu "On-chip Peripheral Drivers" choice prompt "i2c0 scl pin number (GP)" depends on BSP_USING_I2C0 - default BSP_I2C0_SCL_PIN_21 - config BSP_I2C0_SCL_PIN_1 - bool "1" + default BSP_I2C0_SCL_PIN_5 if BSP_USING_ARDUINO config BSP_I2C0_SCL_PIN_5 bool "5" + config BSP_I2C0_SCL_PIN_1 + bool "1" config BSP_I2C0_SCL_PIN_9 bool "9" config BSP_I2C0_SCL_PIN_13 @@ -718,11 +722,11 @@ menu "On-chip Peripheral Drivers" choice prompt "i2c0 sda pin number (GP)" depends on BSP_USING_I2C0 - default BSP_I2C0_SDA_PIN_20 - config BSP_I2C0_SDA_PIN_0 - bool "0" + default BSP_I2C0_SDA_PIN_4 if BSP_USING_ARDUINO config BSP_I2C0_SDA_PIN_4 bool "4" + config BSP_I2C0_SDA_PIN_0 + bool "0" config BSP_I2C0_SDA_PIN_8 bool "8" config BSP_I2C0_SDA_PIN_12 diff --git a/bsp/raspberry-pico/drivers/drv_gpio.c b/bsp/raspberry-pico/drivers/drv_gpio.c index 14b8d87b4c4..2f1873dd163 100644 --- a/bsp/raspberry-pico/drivers/drv_gpio.c +++ b/bsp/raspberry-pico/drivers/drv_gpio.c @@ -43,7 +43,7 @@ static void pico_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t valu gpio_put(pin, value); } -static rt_int8_t pico_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t pico_pin_read(struct rt_device *device, rt_base_t pin) { RT_ASSERT((0 <= pin) && (pin < NUM_BANK0_GPIOS)); return (gpio_get(pin)? PIN_HIGH : PIN_LOW); diff --git a/bsp/raspberry-pico/drivers/drv_soft_spi.c b/bsp/raspberry-pico/drivers/drv_soft_spi.c index e1addb2d907..11ac0db7af9 100644 --- a/bsp/raspberry-pico/drivers/drv_soft_spi.c +++ b/bsp/raspberry-pico/drivers/drv_soft_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -24,6 +24,8 @@ static struct pico_soft_spi_config soft_spi_config[] = #endif }; +static struct pico_soft_spi spi_obj[sizeof(soft_spi_config) / sizeof(soft_spi_config[0])]; + /** * Attach the spi device to soft SPI bus, this function must be used after initialization. */ @@ -153,9 +155,20 @@ static void pico_udelay(rt_uint32_t us) busy_wait_us_32(us); } +static void pico_pin_init(void) +{ + rt_size_t obj_num = sizeof(spi_obj) / sizeof(struct pico_soft_spi); + + for(rt_size_t i; i < obj_num; i++) + { + pico_spi_gpio_init(&spi_obj[i]); + } +} + static struct rt_spi_bit_ops pico_soft_spi_ops = { .data = RT_NULL, + .pin_init = pico_pin_init, .tog_sclk = pico_tog_sclk, .set_sclk = pico_set_sclk, .set_mosi = pico_set_mosi, @@ -169,20 +182,18 @@ static struct rt_spi_bit_ops pico_soft_spi_ops = .delay_us = 1, }; -static struct pico_soft_spi spi_obj[sizeof(soft_spi_config) / sizeof(soft_spi_config[0])]; - /* Soft SPI initialization function */ int rt_hw_softspi_init(void) { rt_size_t obj_num = sizeof(spi_obj) / sizeof(struct pico_soft_spi); rt_err_t result; - for (int i = 0; i < obj_num; i++) + for (rt_size_t i = 0; i < obj_num; i++) { pico_soft_spi_ops.data = (void *)&soft_spi_config[i]; spi_obj[i].spi.ops = &pico_soft_spi_ops; spi_obj[i].cfg = (void *)&soft_spi_config[i]; - pico_spi_gpio_init(&spi_obj[i]); + result = rt_spi_bit_add_bus(&spi_obj[i].spi, soft_spi_config[i].bus_name, &pico_soft_spi_ops); RT_ASSERT(result == RT_EOK); } diff --git a/bsp/raspberry-pico/drivers/drv_spi.c b/bsp/raspberry-pico/drivers/drv_spi.c index 86ce30cfbd5..597a1b70a3c 100644 --- a/bsp/raspberry-pico/drivers/drv_spi.c +++ b/bsp/raspberry-pico/drivers/drv_spi.c @@ -38,8 +38,8 @@ static struct pico_spi pico_spi_obj[] = #ifdef BSP_USING_SPI0 { .handle = spi0, - .spi_rx_pin = BSP_SPI0_RX_PIN, - .spi_tx_pin = BSP_SPI0_TX_PIN, + .spi_rx_pin = BSP_SPI0_MISO_PIN, + .spi_tx_pin = BSP_SPI0_MOSI_PIN, .spi_sck_pin = BSP_SPI0_SCK_PIN, .spi_cs_pin = BSP_SPI0_CS_PIN, .device_name = "spi0", @@ -48,8 +48,8 @@ static struct pico_spi pico_spi_obj[] = #ifdef BSP_USING_SPI1 { .handle = spi1, - .spi_rx_pin = BSP_SPI1_RX_PIN, - .spi_tx_pin = BSP_SPI1_TX_PIN, + .spi_rx_pin = BSP_SPI1_MISO_PIN, + .spi_tx_pin = BSP_SPI1_MOSI_PIN, .spi_sck_pin = BSP_SPI1_SCK_PIN, .spi_cs_pin = BSP_SPI1_CS_PIN, .device_name = "spi1", diff --git a/bsp/renesas/README.md b/bsp/renesas/README.md index b043b36d6ce..e7e95d78804 100644 --- a/bsp/renesas/README.md +++ b/bsp/renesas/README.md @@ -19,6 +19,7 @@ RA 系列 BSP 目前支持情况如下表所示： | [ra8m1-ek](ra8m1-ek) | Renesas 官方 EK-RA8M1 开发板 | | [ra8d1-ek](ra8d1-ek) | Renesas 官方 EK-RA8D1 开发板 | | [ra8d1-vision-board](ra8d1-vision-board) | Renesas 联合 RT-Thread RA8D1-Vision-Board 开发板 | +| [rzt2m_rsk](rzt2m_rsk) | Renesas 官方 RSK-RZT2M 开发板 | 可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示： diff --git a/bsp/renesas/ebf_qi_min_6m5/.config b/bsp/renesas/ebf_qi_min_6m5/.config index 0234fa65ffa..e46c497cf9a 100644 --- a/bsp/renesas/ebf_qi_min_6m5/.config +++ b/bsp/renesas/ebf_qi_min_6m5/.config @@ -1058,6 +1058,7 @@ CONFIG_SOC_FAMILY_RENESAS=y CONFIG_SOC_SERIES_R7FA6M5=y # CONFIG_SOC_SERIES_R7FA4M2 is not set # CONFIG_SOC_SERIES_R7FA8M85 is not set +# CONFIG_SOC_SERIES_R9A07G0 is not set # # Hardware Drivers Config @@ -1081,9 +1082,10 @@ CONFIG_BSP_USING_UART4=y # CONFIG_BSP_UART4_TX_USING_DMA is not set CONFIG_BSP_UART4_RX_BUFSIZE=256 CONFIG_BSP_UART4_TX_BUFSIZE=0 -# CONFIG_BSP_USING_I2C is not set -# CONFIG_BSP_USING_SCI_SPI is not set +# CONFIG_BSP_USING_HW_I2C is not set +# CONFIG_BSP_USING_SOFT_I2C is not set # CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_SCI is not set # # Board extended module Drivers diff --git a/bsp/renesas/ebf_qi_min_6m5/board/Kconfig b/bsp/renesas/ebf_qi_min_6m5/board/Kconfig index 2890268e746..a5f477dde2f 100644 --- a/bsp/renesas/ebf_qi_min_6m5/board/Kconfig +++ b/bsp/renesas/ebf_qi_min_6m5/board/Kconfig @@ -21,7 +21,6 @@ menu "Hardware Drivers Config" select RT_USING_SERIAL select RT_USING_SERIAL_V2 if BSP_USING_UART - menuconfig BSP_USING_UART4 bool "Enable UART4" default n @@ -50,109 +49,385 @@ menu "Hardware Drivers Config" endif endif - menuconfig BSP_USING_I2C - bool "Enable I2C BUS" + menuconfig BSP_USING_HW_I2C + bool "Enable hardware I2C BUS" default n + if BSP_USING_HW_I2C + config BSP_USING_HW_I2C1 + bool "Enable Hardware I2C1 BUS" + default n + endif + + menuconfig BSP_USING_SOFT_I2C + bool "Enable software I2C bus" select RT_USING_I2C select RT_USING_I2C_BITOPS select RT_USING_PIN - if BSP_USING_I2C - menuconfig BSP_USING_SCI_I2C - bool "Enable SCI I2C BUS" + default n + if BSP_USING_SOFT_I2C + config BSP_USING_SOFT_I2C + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 Bus (software simulation)" default n - if BSP_USING_SCI_I2C - config BSP_USING_SCI_I2C0 - bool "Enable SCI I2C0 BUS" - default n - config BSP_USING_SCI_I2C1 - bool "Enable SCI I2C1 BUS" - default n - config BSP_USING_SCI_I2C2 - bool "Enable SCI I2C2 BUS" - default n - config BSP_USING_SCI_I2C3 - bool "Enable SCI I2C3 BUS" - default n - config BSP_USING_SCI_I2C4 - bool "Enable SCI I2C4 BUS" - default n - config BSP_USING_SCI_I2C5 - bool "Enable SCI I2C5 BUS" - default n - config BSP_USING_SCI_I2C6 - bool "Enable SCI I2C6 BUS" - default n - config BSP_USING_SCI_I2C7 - bool "Enable SCI I2C7 BUS" - default n - config BSP_USING_SCI_I2C8 - bool "Enable SCI I2C8 BUS" - default n - config BSP_USING_SCI_I2C9 - bool "Enable SCI I2C9 BUS" - default n + if BSP_USING_I2C1 + comment "Please refer to the 'bsp_io.h' file to configure the pins" + config BSP_I2C1_SCL_PIN + hex "i2c1 scl pin number (hex)" + range 0x0000 0xFFFF + default 0x050C + config BSP_I2C1_SDA_PIN + hex "i2c1 sda pin number (hex)" + range 0x0000 0xFFFF + default 0x050B endif - config BSP_USING_HW_I2C - bool "Enable Hardware I2C BUS" + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0 BUS" + default n + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" default n - if BSP_USING_HW_I2C - config BSP_USING_HW_I2C1 - bool "Enable Hardware I2C1 BUS" - default n - endif - if !BSP_USING_HW_I2C - menuconfig BSP_USING_I2C1 - bool "Enable I2C1 BUS (software simulation)" - default n - if BSP_USING_I2C1 - config BSP_I2C1_SCL_PIN - hex "i2c1 scl pin number" - range 0x0000 0x0B0F - default 0x050C - config BSP_I2C1_SDA_PIN - hex "I2C1 sda pin number" - range 0x0000 0x0B0F - default 0x050B - endif - endif endif - menuconfig BSP_USING_SCI_SPI - bool "Enable SCI SPI BUS" + menuconfig BSP_USING_SCI + bool "Enable SCI Controller" default n + config BSP_USING_SCIn_SPI + bool + default n + depends on BSP_USING_SCI select RT_USING_SPI - if BSP_USING_SCI_SPI - config BSP_USING_SCI_SPI0 - bool "Enable SCI SPI0 BUS" + + config BSP_USING_SCIn_I2C + bool + default n + depends on BSP_USING_SCI + select RT_USING_I2C + + config BSP_USING_SCIn_UART + bool + default n + depends on BSP_USING_SCI + select RT_USING_SERIAL + select RT_USING_SERIAL_V2 + + if BSP_USING_SCI + config BSP_USING_SCI0 + bool "Enable SCI0" + default n + if BSP_USING_SCI0 + choice + prompt "choice sci mode" + default BSP_USING_SCI0_SPI + config BSP_USING_SCI0_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI0_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI0_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI0_UART + config BSP_SCI0_UART_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI0_UART_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI1 + bool "Enable SCI1" default n - config BSP_USING_SCI_SPI1 - bool "Enable SCI SPI1 BUS" + if BSP_USING_SCI1 + choice + prompt "choice sci mode" + default BSP_USING_SCI1_SPI + config BSP_USING_SCI1_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI1_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI1_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI1_UART + config BSP_SCI1_UART_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI1_UART_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI2 + bool "Enable SCI2" default n - config BSP_USING_SCI_SPI2 - bool "Enable SCI SPI2 BUS" + if BSP_USING_SCI2 + choice + prompt "choice sci mode" + default BSP_USING_SCI2_SPI + config BSP_USING_SCI2_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI2_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI2_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI2_UART + config BSP_SCI2_UART_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI2_UART_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI3 + bool "Enable SCI3" default n - config BSP_USING_SCI_SPI3 - bool "Enable SCI SPI3 BUS" + if BSP_USING_SCI3 + choice + prompt "choice sci mode" + default BSP_USING_SCI3_SPI + config BSP_USING_SCI3_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI3_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI3_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI3_UART + config BSP_SCI3_UART_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI3_UART_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI4 + bool "Enable SCI4" default n - config BSP_USING_SCI_SPI5 - bool "Enable SCI SPI5 BUS" + if BSP_USING_SCI4 + choice + prompt "choice sci mode" + default BSP_USING_SCI4_SPI + config BSP_USING_SCI4_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI4_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI4_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI4_UART + config BSP_SCI4_UART_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI4_UART_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI5 + bool "Enable SCI5" default n - config BSP_USING_SCI_SPI6 - bool "Enable SCI SPI6 BUS" + if BSP_USING_SCI5 + choice + prompt "choice sci mode" + default BSP_USING_SCI5_SPI + config BSP_USING_SCI5_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI5_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI5_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI5_UART + config BSP_SCI5_UART_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI5_UART_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI6 + bool "Enable SCI6" default n - endif + if BSP_USING_SCI6 + choice + prompt "choice sci mode" + default BSP_USING_SCI6_SPI + config BSP_USING_SCI6_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI6_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI6_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI6_UART + config BSP_SCI6_UART_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 - menuconfig BSP_USING_SPI - bool "Enable SPI BUS" - default n - select RT_USING_SPI - if BSP_USING_SPI - config BSP_USING_SPI0 - bool "Enable SPI0 BUS" + config BSP_SCI6_UART_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI7 + bool "Enable SCI7" default n - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" + if BSP_USING_SCI7 + choice + prompt "choice sci mode" + default BSP_USING_SCI7_SPI + config BSP_USING_SCI7_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI7_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI7_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI7_UART + config BSP_SCI7_UART_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI7_UART_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI8 + bool "Enable SCI8" default n + if BSP_USING_SCI8 + choice + prompt "choice sci mode" + default BSP_USING_SCI8_SPI + config BSP_USING_SCI8_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI8_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI8_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI8_UART + config BSP_SCI8_UART_RX_BUFSIZE + int "Set UART8 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI8_UART_TX_BUFSIZE + int "Set UART8 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI9 + bool "Enable SCI9" + default n + if BSP_USING_SCI9 + choice + prompt "choice sci mode" + default BSP_USING_SCI9_SPI + config BSP_USING_SCI9_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI9_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI9_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI9_UART + config BSP_SCI9_UART_RX_BUFSIZE + int "Set UART9 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI9_UART_TX_BUFSIZE + int "Set UART9 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif endif endmenu diff --git a/bsp/renesas/ebf_qi_min_6m5/project.uvprojx b/bsp/renesas/ebf_qi_min_6m5/project.uvprojx index 9df61322cb6..a5ec66975b1 100644 --- a/bsp/renesas/ebf_qi_min_6m5/project.uvprojx +++ b/bsp/renesas/ebf_qi_min_6m5/project.uvprojx @@ -475,6 +475,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/renesas/libraries/HAL_Drivers/SConscript b/bsp/renesas/libraries/HAL_Drivers/SConscript index d6c927393d1..0a99bbc1f94 100644 --- a/bsp/renesas/libraries/HAL_Drivers/SConscript +++ b/bsp/renesas/libraries/HAL_Drivers/SConscript @@ -32,15 +32,9 @@ if GetDepend(['BSP_USING_SOFT_I2C']): if GetDepend(['BSP_USING_HW_I2C']): src += ['drv_i2c.c'] -if GetDepend(['BSP_USING_SCI_I2C']): - src += ['drv_sci_i2c.c'] - if GetDepend(['BSP_USING_SPI']): src += ['drv_spi.c'] -if GetDepend(['BSP_USING_SCI_SPI']): - src += ['drv_sci_spi.c'] - if GetDepend(['BSP_USING_SOFT_SPI']): src += ['drv_soft_spi.c'] diff --git a/bsp/renesas/libraries/HAL_Drivers/config/drv_config.h b/bsp/renesas/libraries/HAL_Drivers/config/drv_config.h index 2e62e560856..b44abab812f 100644 --- a/bsp/renesas/libraries/HAL_Drivers/config/drv_config.h +++ b/bsp/renesas/libraries/HAL_Drivers/config/drv_config.h @@ -141,6 +141,20 @@ extern "C" #endif /* SOC_SERIES_R7FA8M85 */ +#ifdef SOC_SERIES_R9A07G0 +#include "rzt/uart_config.h" +#include "rzt/timer_config.h" + +#ifdef BSP_USING_PWM +#include "rzt/pwm_config.h" +#endif + +#ifdef BSP_USING_ADC +#include "rzt/adc_config.h" +#endif + +#endif /* SOC_SERIES_R9A07G0 */ + #ifdef __cplusplus } #endif diff --git a/bsp/renesas/libraries/HAL_Drivers/config/ra2l1/adc_config.h b/bsp/renesas/libraries/HAL_Drivers/config/ra2l1/adc_config.h index 4575d4dff1b..b6dab3ca6a2 100644 --- a/bsp/renesas/libraries/HAL_Drivers/config/ra2l1/adc_config.h +++ b/bsp/renesas/libraries/HAL_Drivers/config/ra2l1/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,18 +19,19 @@ extern "C" { #endif #if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1) -struct ra_adc_map + +struct rt_adc_dev { - char name; - const adc_cfg_t *g_cfg; - const adc_instance_ctrl_t *g_ctrl; - const adc_channel_cfg_t *g_channel_cfg; + struct rt_adc_ops ops; + struct rt_adc_device adc_device; }; -struct ra_dev +struct ra_adc_map { - rt_adc_device_t ra_adc_device_t; - struct ra_adc_map *ra_adc_dev; + const char *device_name; + const adc_cfg_t *g_cfg; + const adc_ctrl_t *g_ctrl; + const adc_channel_cfg_t *g_channel_cfg; }; #endif #endif diff --git a/bsp/renesas/libraries/HAL_Drivers/config/ra4m2/adc_config.h b/bsp/renesas/libraries/HAL_Drivers/config/ra4m2/adc_config.h index 4575d4dff1b..b6dab3ca6a2 100644 --- a/bsp/renesas/libraries/HAL_Drivers/config/ra4m2/adc_config.h +++ b/bsp/renesas/libraries/HAL_Drivers/config/ra4m2/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,18 +19,19 @@ extern "C" { #endif #if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1) -struct ra_adc_map + +struct rt_adc_dev { - char name; - const adc_cfg_t *g_cfg; - const adc_instance_ctrl_t *g_ctrl; - const adc_channel_cfg_t *g_channel_cfg; + struct rt_adc_ops ops; + struct rt_adc_device adc_device; }; -struct ra_dev +struct ra_adc_map { - rt_adc_device_t ra_adc_device_t; - struct ra_adc_map *ra_adc_dev; + const char *device_name; + const adc_cfg_t *g_cfg; + const adc_ctrl_t *g_ctrl; + const adc_channel_cfg_t *g_channel_cfg; }; #endif #endif diff --git a/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/adc_config.h b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/adc_config.h index d0856ae9dba..b6dab3ca6a2 100644 --- a/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/adc_config.h +++ b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,18 +19,19 @@ extern "C" { #endif #if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1) -struct ra_adc_map + +struct rt_adc_dev { - char name; - const adc_cfg_t *g_cfg; - const adc_instance_ctrl_t *g_ctrl; - const adc_channel_cfg_t *g_channel_cfg; + struct rt_adc_ops ops; + struct rt_adc_device adc_device; }; -struct ra_dev +struct ra_adc_map { - rt_adc_device_t ra_adc_device_t; - struct ra_adc_map *ra_adc_dev; + const char *device_name; + const adc_cfg_t *g_cfg; + const adc_ctrl_t *g_ctrl; + const adc_channel_cfg_t *g_channel_cfg; }; #endif #endif diff --git a/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/lcd_config.h b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/lcd_config.h new file mode 100644 index 00000000000..92eda2da19f --- /dev/null +++ b/bsp/renesas/libraries/HAL_Drivers/config/ra6m3/lcd_config.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-01 Rbb666 the first version + */ +#ifndef __LCD_CONFIG_H_ +#define __LCD_CONFIG_H_ + +typedef enum +{ + ROTATION_ZERO = 0, + ROTATION_090 = 90, + ROTATION_180 = 180, + ROTATION_270 = 270, +} bsp_rotation; + +#define LCD_WIDTH DISPLAY_HSIZE_INPUT0 +#define LCD_HEIGHT DISPLAY_VSIZE_INPUT0 +#define LCD_BITS_PER_PIXEL DISPLAY_BITS_PER_PIXEL_INPUT1 +#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565 +#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8) + +#define ENABLE_DOUBLE_BUFFER (0) + +#define LCD_BL_PIN BSP_IO_PORT_01_PIN_00 + +#endif diff --git a/bsp/renesas/libraries/HAL_Drivers/config/ra6m4/adc_config.h b/bsp/renesas/libraries/HAL_Drivers/config/ra6m4/adc_config.h index 4575d4dff1b..b6dab3ca6a2 100644 --- a/bsp/renesas/libraries/HAL_Drivers/config/ra6m4/adc_config.h +++ b/bsp/renesas/libraries/HAL_Drivers/config/ra6m4/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,18 +19,19 @@ extern "C" { #endif #if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1) -struct ra_adc_map + +struct rt_adc_dev { - char name; - const adc_cfg_t *g_cfg; - const adc_instance_ctrl_t *g_ctrl; - const adc_channel_cfg_t *g_channel_cfg; + struct rt_adc_ops ops; + struct rt_adc_device adc_device; }; -struct ra_dev +struct ra_adc_map { - rt_adc_device_t ra_adc_device_t; - struct ra_adc_map *ra_adc_dev; + const char *device_name; + const adc_cfg_t *g_cfg; + const adc_ctrl_t *g_ctrl; + const adc_channel_cfg_t *g_channel_cfg; }; #endif #endif diff --git a/bsp/renesas/libraries/HAL_Drivers/config/ra6m5/adc_config.h b/bsp/renesas/libraries/HAL_Drivers/config/ra6m5/adc_config.h index 4575d4dff1b..b6dab3ca6a2 100644 --- a/bsp/renesas/libraries/HAL_Drivers/config/ra6m5/adc_config.h +++ b/bsp/renesas/libraries/HAL_Drivers/config/ra6m5/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,18 +19,19 @@ extern "C" { #endif #if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1) -struct ra_adc_map + +struct rt_adc_dev { - char name; - const adc_cfg_t *g_cfg; - const adc_instance_ctrl_t *g_ctrl; - const adc_channel_cfg_t *g_channel_cfg; + struct rt_adc_ops ops; + struct rt_adc_device adc_device; }; -struct ra_dev +struct ra_adc_map { - rt_adc_device_t ra_adc_device_t; - struct ra_adc_map *ra_adc_dev; + const char *device_name; + const adc_cfg_t *g_cfg; + const adc_ctrl_t *g_ctrl; + const adc_channel_cfg_t *g_channel_cfg; }; #endif #endif diff --git a/bsp/renesas/libraries/HAL_Drivers/config/ra8/adc_config.h b/bsp/renesas/libraries/HAL_Drivers/config/ra8/adc_config.h index d0856ae9dba..b6dab3ca6a2 100644 --- a/bsp/renesas/libraries/HAL_Drivers/config/ra8/adc_config.h +++ b/bsp/renesas/libraries/HAL_Drivers/config/ra8/adc_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,18 +19,19 @@ extern "C" { #endif #if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1) -struct ra_adc_map + +struct rt_adc_dev { - char name; - const adc_cfg_t *g_cfg; - const adc_instance_ctrl_t *g_ctrl; - const adc_channel_cfg_t *g_channel_cfg; + struct rt_adc_ops ops; + struct rt_adc_device adc_device; }; -struct ra_dev +struct ra_adc_map { - rt_adc_device_t ra_adc_device_t; - struct ra_adc_map *ra_adc_dev; + const char *device_name; + const adc_cfg_t *g_cfg; + const adc_ctrl_t *g_ctrl; + const adc_channel_cfg_t *g_channel_cfg; }; #endif #endif diff --git a/bsp/renesas/libraries/HAL_Drivers/config/ra8/lcd_config.h b/bsp/renesas/libraries/HAL_Drivers/config/ra8/lcd_config.h new file mode 100644 index 00000000000..62e8e575adc --- /dev/null +++ b/bsp/renesas/libraries/HAL_Drivers/config/ra8/lcd_config.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-01 Rbb666 the first version + */ +#ifndef __LCD_CONFIG_H_ +#define __LCD_CONFIG_H_ + +typedef enum +{ + ROTATION_ZERO = 0, + ROTATION_090 = 90, + ROTATION_180 = 180, + ROTATION_270 = 270, +} bsp_rotation; + +#define LCD_WIDTH DISPLAY_HSIZE_INPUT0 +#define LCD_HEIGHT DISPLAY_VSIZE_INPUT0 +#define LCD_BITS_PER_PIXEL DISPLAY_BITS_PER_PIXEL_INPUT1 +#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565 +#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8) + +#define LCD_NUM_FRAMEBUFFERS (2) +#define ENABLE_DOUBLE_BUFFER (1) + +#define LCD_BL_PIN BSP_IO_PORT_10_PIN_11 +#define LCD_RST_PIN BSP_IO_PORT_11_PIN_04 + +#endif diff --git a/bsp/renesas/libraries/HAL_Drivers/config/rzt/adc_config.h b/bsp/renesas/libraries/HAL_Drivers/config/rzt/adc_config.h new file mode 100644 index 00000000000..b6dab3ca6a2 --- /dev/null +++ b/bsp/renesas/libraries/HAL_Drivers/config/rzt/adc_config.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-19 Mr.Tiger first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#include +#include +#include "hal_data.h" +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1) + +struct rt_adc_dev +{ + struct rt_adc_ops ops; + struct rt_adc_device adc_device; +}; + +struct ra_adc_map +{ + const char *device_name; + const adc_cfg_t *g_cfg; + const adc_ctrl_t *g_ctrl; + const adc_channel_cfg_t *g_channel_cfg; +}; +#endif +#endif + +#ifdef __cplusplus +} +#endif + diff --git a/bsp/renesas/libraries/HAL_Drivers/config/rzt/pwm_config.h b/bsp/renesas/libraries/HAL_Drivers/config/rzt/pwm_config.h new file mode 100644 index 00000000000..217cbc0b645 --- /dev/null +++ b/bsp/renesas/libraries/HAL_Drivers/config/rzt/pwm_config.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-26 KevinXu first version + */ +#ifndef __PWM_CONFIG_H__ +#define __PWM_CONFIG_H__ + +#include +#include +#include "hal_data.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum +{ +#ifdef BSP_USING_PWM0 + BSP_PWM0_INDEX, +#endif +#ifdef BSP_USING_PWM1 + BSP_PWM1_INDEX, +#endif +#ifdef BSP_USING_PWM2 + BSP_PWM2_INDEX, +#endif +#ifdef BSP_USING_PWM3 + BSP_PWM3_INDEX, +#endif +#ifdef BSP_USING_PWM4 + BSP_PWM4_INDEX, +#endif +#ifdef BSP_USING_PWM5 + BSP_PWM5_INDEX, +#endif +#ifdef BSP_USING_PWM6 + BSP_PWM6_INDEX, +#endif +#ifdef BSP_USING_PWM7 + BSP_PWM7_INDEX, +#endif +#ifdef BSP_USING_PWM8 + BSP_PWM8_INDEX, +#endif +#ifdef BSP_USING_PWM9 + BSP_PWM9_INDEX, +#endif + BSP_PWMS_NUM +}; + +#define PWM_DRV_INITIALIZER(num) \ + { \ + .name = "pwm"#num , \ + .g_cfg = &g_timer##num##_cfg, \ + .g_ctrl = &g_timer##num##_ctrl, \ + .g_timer = &g_timer##num, \ + } + +#ifdef __cplusplus +} +#endif + +#endif /* __PWM_CONFIG_H__ */ diff --git a/bsp/renesas/libraries/HAL_Drivers/config/rzt/timer_config.h b/bsp/renesas/libraries/HAL_Drivers/config/rzt/timer_config.h new file mode 100644 index 00000000000..5aeb3bad71f --- /dev/null +++ b/bsp/renesas/libraries/HAL_Drivers/config/rzt/timer_config.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-09-04 Rbb666 first version + */ + +#ifndef __TIMER_CONFIG_H__ +#define __TIMER_CONFIG_H__ + +#include +#include "hal_data.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define PLCKD_PRESCALER_MAX_SELECT 8 + +/* RSK-RZN2L: Frequency ratio: PCLKA:PCLKD = 1:N (N = 1/2/4/8/16/32/64) */ +#define PLCKD_PRESCALER_400M (BSP_PRV_PCLKGPTL_FREQ_400_MHZ) +#define PLCKD_PRESCALER_200M (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 2) +#define PLCKD_PRESCALER_100M (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 4) +#define PLCKD_PRESCALER_50M (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 8) +#define PLCKD_PRESCALER_25M (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 16) +#define PLCKD_PRESCALER_12_5M (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 32) +#define PLCKD_PRESCALER_6_25M (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 64) +#define PLCKD_PRESCALER_3_125M (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 128) +#define PLCKD_PRESCALER_1_5625M (BSP_PRV_PCLKGPTL_FREQ_400_MHZ / 256) + +#ifndef TMR_DEV_INFO_CONFIG +#define TMR_DEV_INFO_CONFIG \ + { \ + .maxfreq = 400000000, \ + .minfreq = 1562500, \ + .maxcnt = 0XFFFFFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +enum +{ +#ifdef BSP_USING_TIM0 + BSP_TIMER0_INDEX, +#endif +#ifdef BSP_USING_TIM1 + BSP_TIMER1_INDEX, +#endif + BSP_TIMERS_NUM +}; + +#define TIMER_DRV_INITIALIZER(num) \ + { \ + .name = "timer" #num, \ + .g_cfg = &g_timer##num##_cfg, \ + .g_ctrl = &g_timer##num##_ctrl, \ + .g_timer = &g_timer##num, \ + } + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_CONFIG_H__ */ diff --git a/bsp/renesas/libraries/HAL_Drivers/config/rzt/uart_config.h b/bsp/renesas/libraries/HAL_Drivers/config/rzt/uart_config.h new file mode 100644 index 00000000000..a374567b369 --- /dev/null +++ b/bsp/renesas/libraries/HAL_Drivers/config/rzt/uart_config.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-29 KyleChan first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include +#include "hal_data.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_UART0) +#ifndef UART0_CONFIG +#define UART0_CONFIG \ + { \ + .name = "uart0", \ + .p_api_ctrl = &g_uart0_ctrl, \ + .p_cfg = &g_uart0_cfg, \ + } +#endif /* UART0_CONFIG */ +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .p_api_ctrl = &g_uart1_ctrl, \ + .p_cfg = &g_uart1_cfg, \ + } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .p_api_ctrl = &g_uart2_ctrl, \ + .p_cfg = &g_uart2_cfg, \ + } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .p_api_ctrl = &g_uart3_ctrl, \ + .p_cfg = &g_uart3_cfg, \ + } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .p_api_ctrl = &g_uart4_ctrl, \ + .p_cfg = &g_uart4_cfg, \ + } +#endif /* UART4_CONFIG */ +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .p_api_ctrl = &g_uart5_ctrl, \ + .p_cfg = &g_uart5_cfg, \ + } +#endif /* UART5_CONFIG */ +#endif /* BSP_USING_UART5 */ + + +#if defined(BSP_USING_UART6) +#ifndef UART6_CONFIG +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .p_api_ctrl = &g_uart6_ctrl, \ + .p_cfg = &g_uart6_cfg, \ + } +#endif /* UART6_CONFIG */ +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +#ifndef UART7_CONFIG +#define UART7_CONFIG \ + { \ + .name = "uart7", \ + .p_api_ctrl = &g_uart7_ctrl, \ + .p_cfg = &g_uart7_cfg, \ + } +#endif /* UART7_CONFIG */ +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_UART8) +#ifndef UART8_CONFIG +#define UART8_CONFIG \ + { \ + .name = "uart8", \ + .p_api_ctrl = &g_uart8_ctrl, \ + .p_cfg = &g_uart8_cfg, \ + } +#endif /* UART8_CONFIG */ +#endif /* BSP_USING_UART8 */ + +#if defined(BSP_USING_UART9) +#ifndef UART9_CONFIG +#define UART9_CONFIG \ + { \ + .name = "uart9", \ + .p_api_ctrl = &g_uart9_ctrl, \ + .p_cfg = &g_uart9_cfg, \ + } +#endif /* UART9_CONFIG */ +#endif /* BSP_USING_UART9 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_adc.c b/bsp/renesas/libraries/HAL_Drivers/drv_adc.c index ebe7eed9b8a..c741a49f699 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_adc.c +++ b/bsp/renesas/libraries/HAL_Drivers/drv_adc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,7 +11,7 @@ #include "drv_config.h" #ifdef RT_USING_ADC -// #define DRV_DEBUG +#define DRV_DEBUG #define DBG_TAG "drv.adc" #ifdef DRV_DEBUG #define DBG_LVL DBG_LOG @@ -22,24 +22,25 @@ struct ra_adc_map ra_adc[] = { -#if defined(BSP_USING_ADC0) - {'0', &g_adc0_cfg, &g_adc0_ctrl, &g_adc0_channel_cfg}, +#ifdef BSP_USING_ADC0 + { + .device_name = "adc0", + .g_cfg = &g_adc0_cfg, + .g_ctrl = &g_adc0_ctrl, + .g_channel_cfg = &g_adc0_channel_cfg, + }, #endif - -#if defined(BSP_USING_ADC1) - {'1', &g_adc1_cfg, &g_adc1_ctrl, &g_adc1_channel_cfg}, +#ifdef BSP_USING_ADC1 + { + .device_name = "adc1", + .g_cfg = &g_adc1_cfg, + .g_ctrl = &g_adc1_ctrl, + .g_channel_cfg = &g_adc1_channel_cfg, + }, #endif }; -#if defined(BSP_USING_ADC0) -struct rt_adc_device adc0_device; -struct ra_dev _ra_adc0_device = {.ra_adc_device_t = &adc0_device, .ra_adc_dev = &ra_adc[0]}; -#endif - -#if defined(BSP_USING_ADC1) -struct rt_adc_device adc1_device; -struct ra_dev _ra_adc1_device = {.ra_adc_device_t = &adc1_device, .ra_adc_dev = &ra_adc[1]}; -#endif +static struct rt_adc_dev adc_obj[sizeof(ra_adc) / sizeof(ra_adc[0])] = {0}; static rt_err_t ra_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled) { @@ -50,7 +51,7 @@ static rt_err_t ra_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, { if (FSP_SUCCESS != R_ADC_ScanStart((adc_ctrl_t *)adc->g_ctrl)) { - LOG_E("start adc%c failed.", adc->name); + LOG_E("start %s failed.", adc->device_name); return -RT_ERROR; } } @@ -59,7 +60,7 @@ static rt_err_t ra_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, /**< stop adc*/ if (FSP_SUCCESS != R_ADC_ScanStop((adc_ctrl_t *)adc->g_ctrl)) { - LOG_E("stop adc%c failed.", adc->name); + LOG_E("stop %s failed.", adc->device_name); return -RT_ERROR; } } @@ -69,10 +70,10 @@ static rt_err_t ra_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_err_t ra_adc_close(struct rt_adc_device *device) { RT_ASSERT(device != RT_NULL); - struct ra_adc_map *adc = (struct ra_adc_map *)(struct ra_adc_map *)device->parent.user_data; + struct ra_adc_map *adc = (struct ra_adc_map *)device->parent.user_data; if (FSP_SUCCESS != R_ADC_Close((adc_ctrl_t *)adc->g_ctrl)) { - LOG_E("close adc%c failed.", adc->name); + LOG_E("close %s failed.", adc->device_name); return -RT_ERROR; } return RT_EOK; @@ -98,35 +99,32 @@ static const struct rt_adc_ops ra_adc_ops = static int ra_adc_init(void) { -#if defined(BSP_USING_ADC0) - R_ADC_Open((adc_ctrl_t *)_ra_adc0_device.ra_adc_dev->g_ctrl, - (adc_cfg_t const * const)_ra_adc0_device.ra_adc_dev->g_cfg); - - R_ADC_ScanCfg((adc_ctrl_t *)_ra_adc0_device.ra_adc_dev->g_ctrl, - (adc_cfg_t const * const)_ra_adc0_device.ra_adc_dev->g_channel_cfg); + rt_err_t result = 0; + rt_size_t obj_num = sizeof(adc_obj) / sizeof(struct rt_adc_dev); - if (RT_EOK != rt_hw_adc_register(_ra_adc0_device.ra_adc_device_t, "adc0", &ra_adc_ops, (void *)_ra_adc0_device.ra_adc_dev)) + for (int i = 0; i < obj_num; i++) { - LOG_E("adc0 register failed"); - return -RT_ERROR; - } -#endif - -#if defined(BSP_USING_ADC1) - R_ADC_Open((adc_ctrl_t *)_ra_adc1_device.ra_adc_dev->g_ctrl, - (adc_cfg_t const * const)_ra_adc1_device.ra_adc_dev->g_cfg); + /* init ADC object */ + result = R_ADC_Open((adc_ctrl_t *)ra_adc[i].g_ctrl, ra_adc[i].g_cfg); - R_ADC_ScanCfg((adc_ctrl_t *)_ra_adc1_device.ra_adc_dev->g_ctrl, - (adc_cfg_t const * const)_ra_adc1_device.ra_adc_dev->g_channel_cfg); + result = R_ADC_ScanCfg((adc_ctrl_t *)ra_adc[i].g_ctrl, ra_adc[i].g_channel_cfg); - if (RT_EOK != rt_hw_adc_register(_ra_adc1_device.ra_adc_device_t, "adc1", &ra_adc_ops, (void *)_ra_adc1_device.ra_adc_dev)) - { - LOG_E("adc1 register failed"); - return -RT_ERROR; + /* register ADC device */ + if(rt_hw_adc_register(&adc_obj[i].adc_device, + ra_adc[i].device_name, + &ra_adc_ops, + &ra_adc[i]) == RT_EOK) + { + LOG_D("%s init success", ra_adc[i].device_name); + } + else + { + LOG_E("%s register failed", ra_adc[i].device_name); + result = -RT_ERROR; + } + RT_ASSERT(result == RT_EOK); } -#endif - return RT_EOK; } -INIT_BOARD_EXPORT(ra_adc_init); +INIT_DEVICE_EXPORT(ra_adc_init); #endif diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_common.c b/bsp/renesas/libraries/HAL_Drivers/drv_common.c index dd2bc38e239..0d9cb7b45be 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_common.c +++ b/bsp/renesas/libraries/HAL_Drivers/drv_common.c @@ -24,11 +24,22 @@ #endif #endif +#ifdef SOC_SERIES_R9A07G0 +#include "gicv3.h" +static uint64_t rtt_timer_delay; +extern fsp_vector_t g_sgi_ppi_vector_table[BSP_CORTEX_VECTOR_TABLE_ENTRIES]; +static void SysTimerInterrupt(void); +#endif + #ifdef RT_USING_FINSH #include static void reboot(uint8_t argc, char **argv) { +#ifdef SOC_SERIES_R9A07G0 + return; +#else NVIC_SystemReset(); +#endif } MSH_CMD_EXPORT(reboot, Reboot System); #endif /* RT_USING_FINSH */ @@ -36,8 +47,12 @@ MSH_CMD_EXPORT(reboot, Reboot System); /* SysTick configuration */ void rt_hw_systick_init(void) { +#ifdef SOC_SERIES_R9A07G0 + SysTimerInterrupt(); +#else SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); NVIC_SetPriority(SysTick_IRQn, 0xFF); +#endif } /** @@ -49,6 +64,10 @@ void SysTick_Handler(void) /* enter interrupt */ rt_interrupt_enter(); +#ifdef SOC_SERIES_R9A07G0 + __set_CNTP_CVAL(__get_CNTP_CVAL() + rtt_timer_delay); +#endif + rt_tick_increase(); /* leave interrupt */ @@ -78,6 +97,7 @@ void _Error_Handler(char *s, int num) */ void rt_hw_us_delay(rt_uint32_t us) { +#ifdef ARCH_ARM_CORTEX_M rt_uint32_t ticks; rt_uint32_t told, tnow, tcnt = 0; rt_uint32_t reload = SysTick->LOAD; @@ -104,13 +124,50 @@ void rt_hw_us_delay(rt_uint32_t us) } } } +#endif } +#ifdef SOC_SERIES_R9A07G0 +static void SysTimerInterrupt(void) +{ + uint64_t tempCNTPCT = __get_CNTPCT(); + + /* Wait for counter supply */ + while (__get_CNTPCT() == tempCNTPCT) + { + R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS); + } + + /* generic timer initialize */ + /* set interrupt handler */ + g_sgi_ppi_vector_table[(int32_t) BSP_VECTOR_NUM_OFFSET + + NonSecurePhysicalTimerInt] = SysTick_Handler; + + rtt_timer_delay = R_GSC->CNTFID0 / RT_TICK_PER_SECOND; + + /* set timer expiration from current counter value */ + __set_CNTP_CVAL(__get_CNTPCT() + rtt_timer_delay); + + /* configure CNTP_CTL to enable timer interrupts */ + __set_CNTP_CTL(1); + R_BSP_IrqCfgEnable(NonSecurePhysicalTimerInt, (int32_t) BSP_VECTOR_NUM_OFFSET + + NonSecurePhysicalTimerInt, RT_NULL); +} +#endif + /** - * This function will initial STM32 board. + * This function will initial board. */ rt_weak void rt_hw_board_init() { +#ifdef SOC_SERIES_R9A07G0 + /* initialize hardware interrupt */ + rt_uint32_t redis_gic_base = platform_get_gic_dist_base(); + rt_int32_t cpu_id = rt_hw_cpu_id(); + arm_gic_redist_address_set(0, redis_gic_base, cpu_id); + rt_hw_interrupt_init(); +#endif + rt_hw_systick_init(); /* Heap initialization */ @@ -140,7 +197,11 @@ rt_weak void rt_hw_board_init() } FSP_CPP_HEADER +#ifdef SOC_SERIES_R9A07G0 +void R_BSP_WarmStart(bsp_warm_start_event_t event) BSP_PLACE_IN_SECTION(".warm_start"); +#else void R_BSP_WarmStart(bsp_warm_start_event_t event); +#endif FSP_CPP_FOOTER /*******************************************************************************************************************//** diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_gpio.c b/bsp/renesas/libraries/HAL_Drivers/drv_gpio.c index ca9827dc9f2..13dc033a4e3 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_gpio.c +++ b/bsp/renesas/libraries/HAL_Drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -114,6 +114,7 @@ static void ra_pin_map_init(void) static void ra_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) { fsp_err_t err; + /* Initialize the IOPORT module and configure the pins */ err = R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg); @@ -126,7 +127,7 @@ static void ra_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) switch (mode) { case PIN_MODE_OUTPUT: - err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, BSP_IO_DIRECTION_OUTPUT); + err = R_IOPORT_PinCfg(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, BSP_IO_DIRECTION_OUTPUT); if (err != FSP_SUCCESS) { LOG_E("PIN_MODE_OUTPUT configuration failed"); @@ -135,7 +136,7 @@ static void ra_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) break; case PIN_MODE_INPUT: - err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, BSP_IO_DIRECTION_INPUT); + err = R_IOPORT_PinCfg(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, BSP_IO_DIRECTION_INPUT); if (err != FSP_SUCCESS) { LOG_E("PIN_MODE_INPUT configuration failed"); @@ -144,7 +145,7 @@ static void ra_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) break; case PIN_MODE_OUTPUT_OD: - err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, IOPORT_CFG_NMOS_ENABLE); + err = R_IOPORT_PinCfg(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, IOPORT_CFG_NMOS_ENABLE); if (err != FSP_SUCCESS) { LOG_E("PIN_MODE_OUTPUT_OD configuration failed"); @@ -164,18 +165,27 @@ static void ra_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } R_BSP_PinAccessEnable(); +#ifdef SOC_SERIES_R9A07G0 + R_IOPORT_PinWrite(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, (bsp_io_level_t)level); +#else R_BSP_PinWrite(pin, level); +#endif R_BSP_PinAccessDisable(); } -static rt_int8_t ra_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t ra_pin_read(rt_device_t dev, rt_base_t pin) { if ((pin > RA_MAX_PIN_VALUE) || (pin < RA_MIN_PIN_VALUE)) { - LOG_E("GPIO pin value is illegal"); - return -1; + return -RT_EINVAL; } +#ifdef SOC_SERIES_R9A07G0 + bsp_io_level_t io_level; + R_IOPORT_PinRead(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, &io_level); + return io_level; +#else return R_BSP_PinRead(pin); +#endif } static rt_err_t ra_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) @@ -295,28 +305,36 @@ static rt_err_t ra_pin_dettach_irq(struct rt_device *device, rt_base_t pin) static rt_base_t ra_pin_get(const char *name) { int pin_number = -1, port = -1, pin = -1; + if (rt_strlen(name) != 4) return -1; - if ((name[0] == 'P') || (name[0] == 'p')) + + if ((name[0] == 'P' || name[0] == 'p')) { - if ('0' <= (int)name[1] && (int)name[1] <= '9') + if ('0' <= name[1] && name[1] <= '9') { - port = ((int)name[1] - 48) * 16 * 16; - if ('0' <= (int)name[2] && (int)name[2] <= '9') + port = (name[1] - '0') * 16 * 16; + if ('0' <= name[2] && name[2] <= '9' && '0' <= name[3] && name[3] <= '9') { - if ('0' <= (int)name[3] && (int)name[3] <= '9') - { - pin = ((int)name[2] - 48) * 10; - pin += (int)name[3] - 48; - pin_number = port + pin; - } - else return -1; + pin = (name[2] - '0') * 10 + (name[3] - '0'); + pin_number = port + pin; + + return pin_number; + } + } + else if ('A' <= name[1] && name[1] <= 'Z') + { + port = (name[1] - '0' - 7) * 16 * 16; + if ('0' <= name[2] && name[2] <= '9' && '0' <= name[3] && name[3] <= '9') + { + pin = (name[2] - '0') * 10 + (name[3] - '0'); + pin_number = port + pin; + + return pin_number; } - else return -1; } - else return -1; } - return pin_number; + return -1; } const static struct rt_pin_ops _ra_pin_ops = @@ -336,6 +354,7 @@ int rt_hw_pin_init(void) ra_irq_tab_init(); ra_pin_map_init(); #endif + return rt_device_pin_register("pin", &_ra_pin_ops, RT_NULL); } diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_gpio.h b/bsp/renesas/libraries/HAL_Drivers/drv_gpio.h index c13a125108a..d627d1957d4 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_gpio.h +++ b/bsp/renesas/libraries/HAL_Drivers/drv_gpio.h @@ -23,8 +23,13 @@ extern "C" { #endif +#ifdef SOC_SERIES_R9A07G0 +#define RA_MIN_PIN_VALUE BSP_IO_PORT_00_PIN_0 +#define RA_MAX_PIN_VALUE BSP_IO_PORT_24_PIN_7 +#else #define RA_MIN_PIN_VALUE BSP_IO_PORT_00_PIN_00 #define RA_MAX_PIN_VALUE BSP_IO_PORT_11_PIN_15 +#endif #ifdef R_ICU_H struct ra_pin_irq_map diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_i2c.c b/bsp/renesas/libraries/HAL_Drivers/drv_i2c.c index 585f6d04ad2..8a79b675dd8 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_i2c.c +++ b/bsp/renesas/libraries/HAL_Drivers/drv_i2c.c @@ -16,69 +16,91 @@ #ifdef BSP_USING_HW_I2C -#define DBG_TAG "drv.hwi2c" -#ifdef DRV_DEBUG - #define DBG_LVL DBG_LOG -#else - #define DBG_LVL DBG_INFO -#endif /* DRV_DEBUG */ -#include +#define DRV_DEBUG +#define LOG_TAG "drv.hwi2c" +#include #include -static struct rt_i2c_bus_device prv_ra_i2c; -static volatile i2c_master_event_t i2c_event = I2C_MASTER_EVENT_ABORTED; +#define RA_SCI_EVENT_ABORTED 1 +#define RA_SCI_EVENT_RX_COMPLETE 2 +#define RA_SCI_EVENT_TX_COMPLETE 4 +#define RA_SCI_EVENT_ERROR 8 +#define RA_SCI_EVENT_ALL 15 + +struct ra_i2c_handle +{ + struct rt_i2c_bus_device bus; + char bus_name[RT_NAME_MAX]; + const i2c_master_cfg_t *i2c_cfg; + void *i2c_ctrl; + struct rt_event event; +}; + +static struct ra_i2c_handle ra_i2cs[] = +{ +#ifdef BSP_USING_HW_I2C0 + {.bus_name = "i2c0", .i2c_cfg = &g_i2c_master0_cfg, .i2c_ctrl = &g_i2c_master0_ctrl,}, +#endif +#ifdef BSP_USING_HW_I2C1 + {.bus_name = "i2c1", .i2c_cfg = &g_i2c_master1_cfg, .i2c_ctrl = &g_i2c_master1_ctrl,}, +#endif +}; void i2c_master_callback(i2c_master_callback_args_t *p_args) { + rt_interrupt_enter(); if (NULL != p_args) { /* capture callback event for validating the i2c transfer event*/ - i2c_event = p_args->event; + struct ra_i2c_handle *obj = (struct ra_i2c_handle *)p_args->p_context; + uint32_t event = 0; + RT_ASSERT(obj != RT_NULL); + switch (p_args->event) + { + case I2C_MASTER_EVENT_ABORTED: + event |= RA_SCI_EVENT_ABORTED; + break; + case I2C_MASTER_EVENT_RX_COMPLETE: + event |= RA_SCI_EVENT_RX_COMPLETE; + break; + case I2C_MASTER_EVENT_TX_COMPLETE: + event |= RA_SCI_EVENT_TX_COMPLETE; + break; + } + rt_event_send(&obj->event, event); } + rt_interrupt_leave(); } -static fsp_err_t validate_i2c_event(void) +static rt_err_t validate_i2c_event(struct ra_i2c_handle *handle) { - uint16_t local_time_out = UINT16_MAX; - - /* resetting call back event capture variable */ - i2c_event = (i2c_master_event_t)0; - - do + rt_uint32_t event = 0; + if (RT_EOK != rt_event_recv(&handle->event, RA_SCI_EVENT_ALL, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, (int32_t)rt_tick_from_millisecond(100), &event)) { - /* This is to avoid infinite loop */ - --local_time_out; - - if(0 == local_time_out) - { - return FSP_ERR_TRANSFER_ABORTED; - } - - }while(i2c_event == 0); - - if(i2c_event != I2C_MASTER_EVENT_ABORTED) + return -RT_ETIMEOUT; + } + if ((event & (RA_SCI_EVENT_ABORTED | RA_SCI_EVENT_ERROR)) == 0) { - /* Make sure this is always Reset before return*/ - i2c_event = (i2c_master_event_t)0; - return FSP_SUCCESS; + return RT_EOK; } - /* Make sure this is always Reset before return */ - i2c_event = (i2c_master_event_t)0; - return FSP_ERR_TRANSFER_ABORTED; + return -RT_ERROR; } static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num) + struct rt_i2c_msg msgs[], + rt_uint32_t num) { rt_size_t i; struct rt_i2c_msg *msg = msgs; RT_ASSERT(bus != RT_NULL); - fsp_err_t err = FSP_SUCCESS; + fsp_err_t err = FSP_SUCCESS; bool restart = false; + struct ra_i2c_handle *ra_i2c = rt_container_of(bus, struct ra_i2c_handle, bus); + i2c_master_ctrl_t *master_ctrl = ra_i2c->i2c_ctrl; + for (i = 0; i < num; i++) { if (msg[i].flags & RT_I2C_NO_START) @@ -87,22 +109,19 @@ static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus, } if (msg[i].flags & RT_I2C_ADDR_10BIT) { - LOG_E("10Bit not support"); - break; + R_IIC_MASTER_SlaveAddressSet(master_ctrl, msg[i].addr, I2C_MASTER_ADDR_MODE_10BIT); } else { - g_i2c_master1_ctrl.slave = msg[i].addr; + R_IIC_MASTER_SlaveAddressSet(master_ctrl, msg[i].addr, I2C_MASTER_ADDR_MODE_7BIT); } if (msg[i].flags & RT_I2C_RD) { - err = R_IIC_MASTER_Read(&g_i2c_master1_ctrl, msg[i].buf, msg[i].len, restart); + err = R_IIC_MASTER_Read(master_ctrl, msg[i].buf, msg[i].len, restart); if (FSP_SUCCESS == err) { - err = validate_i2c_event(); - /* handle error */ - if(FSP_ERR_TRANSFER_ABORTED == err) + if (RT_EOK != validate_i2c_event(ra_i2c)) { LOG_E("POWER_CTL reg I2C read failed"); break; @@ -112,18 +131,16 @@ static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus, else { /* Write API returns itself is not successful */ - LOG_E("R_IIC_MASTER_Write API failed"); + LOG_E("R_I2C_MASTER_Write API failed"); break; } } else { - err = R_IIC_MASTER_Write(&g_i2c_master1_ctrl, msg[i].buf, msg[i].len, restart); + err = R_IIC_MASTER_Write(master_ctrl, msg[i].buf, msg[i].len, restart); if (FSP_SUCCESS == err) { - err = validate_i2c_event(); - /* handle error */ - if(FSP_ERR_TRANSFER_ABORTED == err) + if (RT_EOK != validate_i2c_event(ra_i2c)) { LOG_E("POWER_CTL reg I2C write failed"); break; @@ -133,12 +150,12 @@ static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus, else { /* Write API returns itself is not successful */ - LOG_E("R_IIC_MASTER_Write API failed"); + LOG_E("R_I2C_MASTER_Write API failed"); break; } } } - return i; + return (rt_ssize_t)i; } static const struct rt_i2c_bus_device_ops ra_i2c_ops = @@ -151,17 +168,32 @@ static const struct rt_i2c_bus_device_ops ra_i2c_ops = int ra_hw_i2c_init(void) { fsp_err_t err = FSP_SUCCESS; - prv_ra_i2c.ops = &ra_i2c_ops; - prv_ra_i2c.priv = 0; - /* opening IIC master module */ - err = R_IIC_MASTER_Open(&g_i2c_master1_ctrl, &g_i2c_master1_cfg); - /* handle error */ - if (FSP_SUCCESS != err) + for (rt_uint32_t i = 0; i < sizeof(ra_i2cs) / sizeof(ra_i2cs[0]); i++) { - LOG_E("R_IIC_MASTER_Open API failed"); - return err; + ra_i2cs[i].bus.ops = &ra_i2c_ops; + ra_i2cs[i].bus.priv = 0; + + if (RT_EOK != rt_event_init(&ra_i2cs[i].event, ra_i2cs[i].bus_name, RT_IPC_FLAG_FIFO)) + { + LOG_E("Init event failed"); + continue; + } + /* opening IIC master module */ + err = R_IIC_MASTER_Open(ra_i2cs[i].i2c_ctrl, ra_i2cs[i].i2c_cfg); + if (FSP_SUCCESS != err) + { + LOG_E("R_I2C_MASTER_Open API failed,%d", err); + continue; + } + err = R_IIC_MASTER_CallbackSet(ra_i2cs[i].i2c_ctrl, i2c_master_callback, &ra_i2cs[i], RT_NULL); + /* handle error */ + if (FSP_SUCCESS != err) + { + LOG_E("R_I2C_CallbackSet API failed,%d", err); + continue; + } + rt_i2c_bus_device_register(&ra_i2cs[i].bus, ra_i2cs[i].bus_name); } - rt_i2c_bus_device_register(&prv_ra_i2c, "i2c1"); return 0; } diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_lcd.c b/bsp/renesas/libraries/HAL_Drivers/drv_lcd.c index 60a5088a6c1..1c1d770b7ca 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_lcd.c +++ b/bsp/renesas/libraries/HAL_Drivers/drv_lcd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,114 +9,89 @@ */ #include +#include -#if (defined(BSP_USING_LCD)) || (defined(SOC_SERIES_R7FA6M3)) - -#include +#ifdef BSP_USING_LCD +#ifdef SOC_SERIES_R7FA8M85 +#include +#else +#include +#endif +#include -#include "r_display_api.h" #include "hal_data.h" -//#define DRV_DEBUG -//#define LOG_TAG "drv.lcd" -//#include - +#define DRV_DEBUG +#define LOG_TAG "drv_lcd" +#include struct drv_lcd_device { struct rt_device parent; struct rt_device_graphic_info lcd_info; - - void *framebuffer; }; struct drv_lcd_device _lcd; +static uint16_t screen_rotation; +static struct rt_completion sync_completion; + +static uint16_t *gp_single_buffer = NULL; +static uint16_t *gp_double_buffer = NULL; +static uint16_t *lcd_current_working_buffer = (uint16_t *) &fb_background[0]; + +#ifdef SOC_SERIES_R7FA8M85 +static uint8_t lcd_framebuffer[LCD_BUF_SIZE] BSP_ALIGN_VARIABLE(64) BSP_PLACE_IN_SECTION(".sdram"); +#endif -uint16_t screen_rotation; -uint16_t *lcd_current_working_buffer = (uint16_t *) &fb_background[0]; +// G2D +extern d2_device *d2_handle0; +static d2_device **_d2_handle_user = &d2_handle0; +static d2_renderbuffer *renderbuffer; -// jpeg and lvgl can only select one -__WEAK void _ra_port_display_callback(display_callback_args_t *p_args) +#ifdef SOC_SERIES_R7FA8M85 +extern void ra8_mipi_lcd_init(void); +#endif + +rt_weak void DisplayVsyncCallback(display_callback_args_t *p_args) { + rt_interrupt_enter(); if (DISPLAY_EVENT_LINE_DETECTION == p_args->event) { + rt_completion_done(&sync_completion); } + rt_interrupt_leave(); } -void turn_on_lcd_backlight(void) +// Wait until Vsync is triggered through callback function +static void vsync_wait(void) { -#ifdef BSP_USING_PWM5 -#define LCD_PWM_DEV_NAME "pwm5" -#define LCD_PWM_DEV_CHANNEL 0 + rt_completion_wait(&sync_completion, RT_WAITING_FOREVER); +} +static void turn_on_lcd_backlight(void) +{ +#ifdef BSP_USING_LCD_PWM_BACKLIGHT struct rt_device_pwm *pwm_dev; /* turn on the LCD backlight */ pwm_dev = (struct rt_device_pwm *)rt_device_find(LCD_PWM_DEV_NAME); /* pwm frequency:100K = 10000ns */ - rt_pwm_set(pwm_dev, LCD_PWM_DEV_CHANNEL, 10000, 7000); - rt_pwm_enable(pwm_dev, LCD_PWM_DEV_CHANNEL); -#endif + rt_pwm_set(pwm_dev, 0, 10000, 7000); + rt_pwm_enable(pwm_dev, 0); +#else rt_pin_mode(LCD_BL_PIN, PIN_MODE_OUTPUT); /* LCD_BL */ rt_pin_write(LCD_BL_PIN, PIN_HIGH); +#endif } -void ra_bsp_lcd_init(void) -{ - fsp_err_t error; - // Set screen rotation to default view - screen_rotation = ROTATION_ZERO; - - /** Display driver open */ - error = R_GLCDC_Open(&g_display0_ctrl, &g_display0_cfg); - if (FSP_SUCCESS == error) - { - /** Display driver start */ - error = R_GLCDC_Start(&g_display0_ctrl); - } -} - -void ra_bsp_lcd_set_display_buffer(uint8_t index) -{ - R_GLCDC_BufferChange(&g_display0_ctrl, fb_background[index - 1], DISPLAY_FRAME_LAYER_1); -} - -void ra_bsp_lcd_set_working_buffer(uint8_t index) -{ - if (index >= 1 && index <= 2) - { - lcd_current_working_buffer = (uint16_t *)fb_background[index - 1]; - } -} - -void ra_bsp_lcd_enable_double_buffer(void) -{ - ra_bsp_lcd_set_display_buffer(1); - ra_bsp_lcd_set_working_buffer(2); -} - -void ra_bsp_lcd_clear(uint16_t color) +static void ra_bsp_lcd_clear(uint16_t color) { - for (uint32_t i = 0; i < (LCD_WIDTH * LCD_HEIGHT); i++) + for (uint32_t i = 0; i < LCD_BUF_SIZE; i++) { lcd_current_working_buffer[i] = color; } } -void ra_bsp_lcd_swap_buffer(void) -{ - if (lcd_current_working_buffer == (uint16_t *)fb_background[0]) - { - ra_bsp_lcd_set_display_buffer(1); - ra_bsp_lcd_set_working_buffer(2); - } - else - { - ra_bsp_lcd_set_display_buffer(2); - ra_bsp_lcd_set_working_buffer(1); - } -} - -void bsp_lcd_draw_pixel(uint32_t x, uint32_t y, uint16_t color) +void lcd_draw_pixel(uint32_t x, uint32_t y, uint16_t color) { // Verify pixel is within LCD range if ((x <= LCD_WIDTH) && (y <= LCD_HEIGHT)) @@ -142,7 +117,7 @@ void bsp_lcd_draw_pixel(uint32_t x, uint32_t y, uint16_t color) } else { - rt_kprintf("draw pixel outof range:%d,%d\n", x, y); + LOG_D("draw pixel outof range:%d,%d", x, y); } } @@ -157,17 +132,124 @@ void lcd_fill_array(uint16_t x_start, uint16_t y_start, uint16_t x_end, uint16_t { for (x_offset = 0; x_start + x_offset <= x_end; x_offset++) { - bsp_lcd_draw_pixel(x_start + x_offset, cycle_y, *pixel++); + lcd_draw_pixel(x_start + x_offset, cycle_y, *pixel++); } cycle_y++; } } -static rt_err_t ra_lcd_init(rt_device_t device) +d2_device *d2_handle_obj_get(void) +{ + return *_d2_handle_user; +} + +d2_renderbuffer *d2_renderbuffer_get(void) { - RT_ASSERT(device != RT_NULL); + return renderbuffer; +} - ra_bsp_lcd_init(); +void lcd_draw_jpg(int32_t x, int32_t y, const void *p, int32_t xSize, int32_t ySize) +{ + uint32_t ModeSrc; + ModeSrc = d2_mode_rgb565; + + // Generate render operations + d2_framebuffer(d2_handle_obj_get(), (uint16_t *)&fb_background[0], LCD_WIDTH, LCD_WIDTH, LCD_HEIGHT, ModeSrc); + + d2_selectrenderbuffer(d2_handle_obj_get(), d2_renderbuffer_get()); + d2_cliprect(d2_handle_obj_get(), 0, 0, LCD_WIDTH, LCD_HEIGHT); + d2_setblitsrc(d2_handle_obj_get(), (void *) p, xSize, xSize, ySize, ModeSrc); + d2_blitcopy(d2_handle_obj_get(), xSize, ySize, 0, 0, (d2_width)(LCD_WIDTH << 4), (d2_width)(LCD_HEIGHT << 4), + (d2_point)(x << 4), (d2_point)(y << 4), 0); + + // Execute render operations + d2_executerenderbuffer(d2_handle_obj_get(), d2_renderbuffer_get(), 0); + + // In single-buffered mode always wait for DRW to finish before returning + d2_flushframe(d2_handle_obj_get()); +} + +void lcd_gpu_fill_array(size_t x1, size_t y1, size_t x2, size_t y2, uint16_t *color_data) +{ + uint32_t ModeSrc; + int32_t width; + int32_t heigh; + + width = (x2 - x1) + 1; + heigh = (y2 - y1) + 1; + + ModeSrc = d2_mode_rgb565; + + // Generate render operations + d2_framebuffer(d2_handle_obj_get(), (uint16_t *)&fb_background[0], LCD_WIDTH, LCD_WIDTH, LCD_HEIGHT, ModeSrc); + + d2_selectrenderbuffer(d2_handle_obj_get(), d2_renderbuffer_get()); + d2_cliprect(d2_handle_obj_get(), 0, 0, LCD_WIDTH, LCD_HEIGHT); + d2_setblitsrc(d2_handle_obj_get(), (void *) color_data, width, width, heigh, ModeSrc); + d2_blitcopy(d2_handle_obj_get(), width, heigh, 0, 0, (d2_width)(LCD_WIDTH << 4), (d2_width)(LCD_HEIGHT << 4), + (d2_point)(x1 << 4), (d2_point)(y1 << 4), 0); + + // Execute render operations + d2_executerenderbuffer(d2_handle_obj_get(), d2_renderbuffer_get(), 0); + // In single-buffered mode always wait for DRW to finish before returning + d2_flushframe(d2_handle_obj_get()); +} + +void g2d_display_write_area(const void *pSrc, void *pDst, int WidthSrc, int HeightSrc, int x, int y) +{ + uint32_t ModeSrc; + ModeSrc = d2_mode_rgb565; + + /* Set the new buffer to the current draw buffer */ + d2_framebuffer(d2_handle_obj_get(), (uint16_t *)pDst, LCD_WIDTH, LCD_WIDTH, LCD_HEIGHT, ModeSrc); + + d2_selectrenderbuffer(d2_handle_obj_get(), d2_renderbuffer_get()); + d2_cliprect(d2_handle_obj_get(), 0, 0, LCD_WIDTH, LCD_HEIGHT); + d2_setblitsrc(d2_handle_obj_get(), (void *) pSrc, WidthSrc, WidthSrc, HeightSrc, ModeSrc); + d2_blitcopy(d2_handle_obj_get(), WidthSrc, HeightSrc, 0, 0, (d2_width)(WidthSrc << 4), (d2_width)(HeightSrc << 4), + (d2_point)(x << 4), (d2_point)(y << 4), 0); + + /* End the current display list */ + d2_executerenderbuffer(d2_handle_obj_get(), d2_renderbuffer_get(), 0); + d2_flushframe(d2_handle_obj_get()); +} + +static int g2d_drv_hwInit(void) +{ + d2_s32 d2_err; + uint32_t ModeSrc; + ModeSrc = d2_mode_rgb565; + + // Initialize D/AVE 2D driver + *_d2_handle_user = d2_opendevice(0); + d2_err = d2_inithw(*_d2_handle_user, 0); + if (d2_err != D2_OK) + { + LOG_E("g2d init fail"); + d2_closedevice(*_d2_handle_user); + return -RT_ERROR; + } + + // Clear both buffers + d2_framebuffer(*_d2_handle_user, (uint16_t *)&fb_background[0], LCD_WIDTH, LCD_WIDTH, + LCD_HEIGHT, ModeSrc); + d2_clear(*_d2_handle_user, 0x000000); + + // Set various D2 parameters + d2_setblendmode(*_d2_handle_user, d2_bm_alpha, d2_bm_one_minus_alpha); + d2_setalphamode(*_d2_handle_user, d2_am_constant); + d2_setalpha(*_d2_handle_user, UINT8_MAX); + d2_setantialiasing(*_d2_handle_user, 1); + d2_setlinecap(*_d2_handle_user, d2_lc_butt); + d2_setlinejoin(*_d2_handle_user, d2_lj_miter); + + renderbuffer = d2_newrenderbuffer(*_d2_handle_user, 20, 20); + if (!renderbuffer) + { + LOG_E("no renderbuffer"); + d2_closedevice(*_d2_handle_user); + return -RT_ERROR; + } return RT_EOK; } @@ -180,15 +262,31 @@ static rt_err_t ra_lcd_control(rt_device_t device, int cmd, void *args) { case RTGRAPHIC_CTRL_RECT_UPDATE: { +#ifdef SOC_SERIES_R7FA8M85 struct rt_device_rect_info *info = (struct rt_device_rect_info *)args; +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + SCB_CleanInvalidateDCache_by_Addr((uint32_t *)lcd->lcd_info.framebuffer, sizeof(fb_background[0])); +#endif +#if defined(ENABLE_DOUBLE_BUFFER) && ENABLE_DOUBLE_BUFFER + /* Swap the active framebuffer */ + lcd_current_working_buffer = (lcd_current_working_buffer == gp_single_buffer) ? gp_double_buffer : gp_single_buffer; +#endif - (void)info; /* nothing, right now */ - rt_kprintf("update screen...\n"); + g2d_display_write_area((uint8_t *)lcd->lcd_info.framebuffer, lcd_current_working_buffer, + info->width, info->height, info->x, info->y); +#if defined(ENABLE_DOUBLE_BUFFER) && ENABLE_DOUBLE_BUFFER + /* Now that the framebuffer is ready, update the GLCDC buffer pointer on the next Vsync */ + fsp_err_t err = R_GLCDC_BufferChange(&g_display0_ctrl, (uint8_t *) lcd_current_working_buffer, DISPLAY_FRAME_LAYER_1); + RT_ASSERT(err == 0); +#endif +#endif /* SOC_SERIES_R7FA8M85 */ + /* wait for vsync interrupt */ + vsync_wait(); } break; case RTGRAPHIC_CTRL_POWERON: - rt_pin_write(LCD_BL_PIN, PIN_HIGH); + turn_on_lcd_backlight(); break; case RTGRAPHIC_CTRL_POWEROFF: @@ -215,9 +313,49 @@ static rt_err_t ra_lcd_control(rt_device_t device, int cmd, void *args) return RT_EOK; } +static rt_err_t drv_lcd_init(struct rt_device *device) +{ + return RT_EOK; +} + +static void reset_lcd_panel(void) +{ +#ifdef LCD_RST_PIN + rt_pin_mode(LCD_RST_PIN, PIN_MODE_OUTPUT); + rt_pin_write(LCD_RST_PIN, PIN_LOW); + rt_thread_mdelay(100); + rt_pin_write(LCD_RST_PIN, PIN_HIGH); + rt_thread_mdelay(100); +#endif +} + +static rt_err_t ra_bsp_lcd_init(void) +{ + fsp_err_t error; + + /* Set screen rotation to default view */ + screen_rotation = ROTATION_ZERO; + + /* Display driver open */ + error = R_GLCDC_Open(&g_display0_ctrl, &g_display0_cfg); + if (FSP_SUCCESS == error) + { +#ifdef SOC_SERIES_R7FA8M85 + /* config mipi */ + ra8_mipi_lcd_init(); +#endif + /* Initialize g2d */ + error = g2d_drv_hwInit(); + + /* Display driver start */ + error = R_GLCDC_Start(&g_display0_ctrl); + } + + return error; +} + int rt_hw_lcd_init(void) { - rt_err_t result = RT_EOK; struct rt_device *device = &_lcd.parent; /* memset _lcd to zero */ @@ -228,40 +366,67 @@ int rt_hw_lcd_init(void) _lcd.lcd_info.width = LCD_WIDTH; _lcd.lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL; _lcd.lcd_info.pixel_format = LCD_PIXEL_FORMAT; - +#ifdef SOC_SERIES_R7FA8M85 + _lcd.lcd_info.framebuffer = (uint8_t *)lcd_framebuffer; +#else _lcd.lcd_info.framebuffer = (uint8_t *)&fb_background[0]; +#endif + LOG_D("\nlcd framebuffer address:%#x", _lcd.lcd_info.framebuffer); + memset(_lcd.lcd_info.framebuffer, 0x0, LCD_BUF_SIZE); device->type = RT_Device_Class_Graphic; #ifdef RT_USING_DEVICE_OPS device->ops = &lcd_ops; #else - device->init = ra_lcd_init; + device->init = drv_lcd_init; device->control = ra_lcd_control; #endif /* register lcd device */ rt_device_register(device, "lcd", RT_DEVICE_FLAG_RDWR); - turn_on_lcd_backlight(); + rt_completion_init(&sync_completion); + + /* Initialize buffer pointers */ + gp_single_buffer = (uint16_t *) g_display0_cfg.input[0].p_base; + + /* Double buffer for drawing color bands with good quality */ + gp_double_buffer = gp_single_buffer + LCD_BUF_SIZE; + + reset_lcd_panel(); - // Initialize lcd controller - ra_lcd_init(device); + ra_bsp_lcd_init(); + + /* turn on lcd backlight */ + turn_on_lcd_backlight(); - ra_bsp_lcd_set_display_buffer(1); + ra_bsp_lcd_clear(0x0); screen_rotation = ROTATION_ZERO; - return result; + return RT_EOK; } - INIT_DEVICE_EXPORT(rt_hw_lcd_init); -int lcd_test() +#ifdef SOC_SERIES_R7FA8M85 +rt_weak void ra8_mipi_lcd_init(void) +{ + LOG_E("please Implementation function %s", __func__); +} +#endif + +int lcd_test(void) { struct drv_lcd_device *lcd; + struct rt_device_rect_info rect_info; + rect_info.x = 0; + rect_info.y = 0; + rect_info.width = LCD_WIDTH; + rect_info.height = LCD_HEIGHT; + lcd = (struct drv_lcd_device *)rt_device_find("lcd"); - while (1) + for (int i = 0; i < 2; i++) { /* red */ for (int i = 0; i < LCD_BUF_SIZE / 2; i++) @@ -269,7 +434,8 @@ int lcd_test() lcd->lcd_info.framebuffer[2 * i] = 0x00; lcd->lcd_info.framebuffer[2 * i + 1] = 0xF8; } - lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL); + LOG_D("red buffer..."); + lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, &rect_info); rt_thread_mdelay(1000); /* green */ for (int i = 0; i < LCD_BUF_SIZE / 2; i++) @@ -277,7 +443,8 @@ int lcd_test() lcd->lcd_info.framebuffer[2 * i] = 0xE0; lcd->lcd_info.framebuffer[2 * i + 1] = 0x07; } - lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL); + LOG_D("green buffer..."); + lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, &rect_info); rt_thread_mdelay(1000); /* blue */ for (int i = 0; i < LCD_BUF_SIZE / 2; i++) @@ -285,10 +452,12 @@ int lcd_test() lcd->lcd_info.framebuffer[2 * i] = 0x1F; lcd->lcd_info.framebuffer[2 * i + 1] = 0x00; } - lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL); + LOG_D("blue buffer..."); + lcd->parent.control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, &rect_info); rt_thread_mdelay(1000); } + return RT_EOK; } -MSH_CMD_EXPORT(lcd_test, lcd_test); +MSH_CMD_EXPORT(lcd_test, lcd test cmd); #endif /* BSP_USING_LCD */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_lcd.h b/bsp/renesas/libraries/HAL_Drivers/drv_lcd.h new file mode 100644 index 00000000000..090cd7e6ac6 --- /dev/null +++ b/bsp/renesas/libraries/HAL_Drivers/drv_lcd.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-28 Rbb666 first commit + */ +#ifndef __DRV_LCD_H_ +#define __DRV_LCD_H_ + +void lcd_draw_pixel(uint32_t x, uint32_t y, uint16_t color); +void lcd_draw_jpg(int32_t x, int32_t y, const void *p, int32_t xSize, int32_t ySize); +void lcd_gpu_fill_array(size_t x1, size_t y1, size_t x2, size_t y2, uint16_t *color_data); + +#endif \ No newline at end of file diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_pwm.c b/bsp/renesas/libraries/HAL_Drivers/drv_pwm.c index 9b6369d9b34..60f91a0ca9d 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_pwm.c +++ b/bsp/renesas/libraries/HAL_Drivers/drv_pwm.c @@ -10,7 +10,7 @@ #include "drv_pwm.h" -#ifdef RT_USING_PWM +#ifdef BSP_USING_PWM /* Declare the control function first */ static rt_err_t drv_pwm_control(struct rt_device_pwm *, int, void *); @@ -217,4 +217,4 @@ int rt_hw_pwm_init(void) return ret; } INIT_BOARD_EXPORT(rt_hw_pwm_init); -#endif /* RT_USING_PWM */ +#endif /* BSP_USING_PWM */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_sci.c b/bsp/renesas/libraries/HAL_Drivers/drv_sci.c index 38023e25fab..93d31dd2e3f 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_sci.c +++ b/bsp/renesas/libraries/HAL_Drivers/drv_sci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -80,7 +80,7 @@ struct ra_sci_param #ifdef RT_USING_SPI rt_weak const struct rt_spi_ops sci_ops_spi; #endif -#ifdef RT_USING_UART +#ifdef RT_USING_SERIAL rt_weak const struct rt_uart_ops sci_ops_uart; #endif @@ -101,7 +101,7 @@ struct ra_sci_object struct rt_i2c_bus_device ibus; }; #endif -#ifdef RT_USING_UART +#ifdef RT_USING_SERIAL struct { struct rt_serial_device ubus; @@ -112,23 +112,22 @@ struct ra_sci_object struct rt_event event; }; -#ifndef BIT - #define BIT(idx) (1ul << (idx)) -#endif - -#ifndef BITS - #define BITS(b,e) ((((uint32_t)-1)<<(b))&(((uint32_t)-1)>>(31-(e)))) -#endif - #define _TO_STR(_a) #_a #define CONCAT3STR(_a,_b,_c) _TO_STR(_a##_b##_c) -#define RA_SCI_EVENT_ABORTED BIT(0) -#define RA_SCI_EVENT_RX_COMPLETE BIT(1) -#define RA_SCI_EVENT_TX_COMPLETE BIT(2) -#define RA_SCI_EVENT_ERROR BIT(3) -#define RA_SCI_EVENT_ALL BITS(0,3) +#define RA_SCI_EVENT_ABORTED 1 +#define RA_SCI_EVENT_RX_COMPLETE 2 +#define RA_SCI_EVENT_TX_COMPLETE 4 +#define RA_SCI_EVENT_ERROR 8 +#define RA_SCI_EVENT_ALL 15 +/** + * Bus name format: sci[x][y], where x=0~9 and y=s/i/u + * Example: + * - sci_spi: sci0s + * - sci_i2c: sci0i + * - sci_uart: sci0u + */ #define RA_SCI_HANDLE_ITEM(idx,type,id) {.bus_name=CONCAT3STR(sci,idx,id),.sci_ctrl=&g_sci##idx##_ctrl,.sci_cfg=&g_sci##idx##_cfg,.ops=&sci_ops_##type} const static struct ra_sci_param sci_param[] = @@ -671,7 +670,7 @@ static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device, #ifdef R_SCI_B_SPI_H R_SCI_B_SPI_CalculateBitrate(obj->spi_cfg->max_hz, SCI_B_SPI_SOURCE_CLOCK_PCLK, &spi_cfg.clk_div); #else - R_SCI_SPI_CalculateBitrate(obj->spi_cfg->max_hz, &cfg_ext->clk_div, false); + R_SCI_SPI_CalculateBitrate(obj->spi_cfg->max_hz, &spi_cfg->clk_div, false); #endif /**< init */ @@ -752,6 +751,7 @@ const struct rt_spi_ops sci_ops_spi = static int ra_hw_sci_init(void) { + int bufsz_idx = 0; for (rt_uint8_t idx = 0; idx < RA_SCI_INDEX_MAX; idx++) { struct ra_sci_object *obj = &sci_obj[idx]; diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_sci.h b/bsp/renesas/libraries/HAL_Drivers/drv_sci.h index fc3f40c21b1..1090e5ebaff 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_sci.h +++ b/bsp/renesas/libraries/HAL_Drivers/drv_sci.h @@ -23,7 +23,9 @@ extern "C" { #endif -rt_err_t drv_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin); +#ifdef BSP_USING_SCIn_SPI +rt_err_t rt_hw_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin); +#endif #ifdef __cplusplus } diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_sci_i2c.c b/bsp/renesas/libraries/HAL_Drivers/drv_sci_i2c.c deleted file mode 100644 index 9e7763e8749..00000000000 --- a/bsp/renesas/libraries/HAL_Drivers/drv_sci_i2c.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023-06-04 vandoul first version - */ - -#include -#include -#include "board.h" - -#include - -#ifdef BSP_USING_SCI_I2C - -#define DBG_TAG "drv.sci2c" -#ifdef DRV_DEBUG - #define DBG_LVL DBG_LOG -#else - #define DBG_LVL DBG_INFO -#endif /* DRV_DEBUG */ -#include - -#include - -struct ra_sci_i2c_handle -{ - struct rt_i2c_bus_device bus; - char bus_name[RT_NAME_MAX]; - const i2c_master_cfg_t *i2c_cfg; - void *i2c_ctrl; - struct rt_event event; -}; - -enum -{ - I2C_EVENT_ABORTED = 1UL<p_context; - rt_event_send(&ra_sci_i2c->event, 1UL << p_args->event); - LOG_D("event:%x", p_args->event); - } - LOG_D("p_args:%p", p_args); -} - -static rt_err_t validate_i2c_event(struct ra_sci_i2c_handle *handle) -{ - rt_uint32_t event = 0; - if(RT_EOK != rt_event_recv(&handle->event, I2C_EVENT_ALL, RT_EVENT_FLAG_OR|RT_EVENT_FLAG_CLEAR, (rt_int32_t)rt_tick_from_millisecond(10), &event)) - { - return -RT_ETIMEOUT; - } - if(event != I2C_EVENT_ABORTED) - { - return RT_EOK; - } - - return -RT_ERROR; -} - -static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num) -{ - rt_size_t i; - struct rt_i2c_msg *msg = msgs; - RT_ASSERT(bus != RT_NULL); - struct ra_sci_i2c_handle *ra_sci_i2c = rt_container_of(bus, struct ra_sci_i2c_handle, bus); - i2c_master_ctrl_t *master_ctrl = ra_sci_i2c->i2c_ctrl; - fsp_err_t err = FSP_SUCCESS; - bool restart = false; - - for (i = 0; i < num; i++) - { - if (msg[i].flags & RT_I2C_NO_START) - { - restart = true; - } - if (msg[i].flags & RT_I2C_ADDR_10BIT) - { - //LOG_E("10Bit not support"); - //break; - R_SCI_I2C_SlaveAddressSet(master_ctrl, msg[i].addr, I2C_MASTER_ADDR_MODE_10BIT); - } - else - { - //master_ctrl->slave = msg[i].addr; - R_SCI_I2C_SlaveAddressSet(master_ctrl, msg[i].addr, I2C_MASTER_ADDR_MODE_7BIT); - } - - if (msg[i].flags & RT_I2C_RD) - { - err = R_SCI_I2C_Read(master_ctrl, msg[i].buf, msg[i].len, restart); - if (FSP_SUCCESS == err) - { - /* handle error */ - if(RT_EOK != validate_i2c_event(ra_sci_i2c)) - { - //LOG_E("POWER_CTL reg I2C read failed,%d", ra_sci_i2c->event); - break; - } - } - /* handle error */ - else - { - /* Write API returns itself is not successful */ - //LOG_E("R_IIC_MASTER_Write API failed"); - break; - } - } - else - { - err = R_SCI_I2C_Write(master_ctrl, msg[i].buf, msg[i].len, restart); - if (FSP_SUCCESS == err) - { - if(RT_EOK != validate_i2c_event(ra_sci_i2c)) - { - //LOG_E("POWER_CTL reg I2C write failed,%d", ra_sci_i2c->event); - break; - } - } - /* handle error */ - else - { - /* Write API returns itself is not successful */ - //LOG_E("R_IIC_MASTER_Write API failed"); - break; - } - } - } - return (rt_ssize_t)i; -} - -static const struct rt_i2c_bus_device_ops ra_i2c_ops = -{ - .master_xfer = ra_i2c_mst_xfer, - .slave_xfer = RT_NULL, - .i2c_bus_control = RT_NULL -}; - -int ra_hw_i2c_init(void) -{ - fsp_err_t err = FSP_SUCCESS; - for(rt_uint32_t i=0; i - -#ifdef R_SCI_B_SPI_H -#define R_SCI_SPI_Write R_SCI_B_SPI_Write -#define R_SCI_SPI_Read R_SCI_B_SPI_Read -#define R_SCI_SPI_WriteRead R_SCI_B_SPI_WriteRead -#define R_SCI_SPI_Open R_SCI_B_SPI_Open -#define R_SCI_SPI_Close R_SCI_B_SPI_Close -#endif - -#define RA_SCI_SPI0_EVENT 0x0001 -#define RA_SCI_SPI1_EVENT 0x0002 -#define RA_SCI_SPI2_EVENT 0x0004 -#define RA_SCI_SPI3_EVENT 0x0008 -#define RA_SCI_SPI4_EVENT 0x0010 -#define RA_SCI_SPI5_EVENT 0x0020 -#define RA_SCI_SPI6_EVENT 0x0040 -#define RA_SCI_SPI7_EVENT 0x0080 -#define RA_SCI_SPI8_EVENT 0x0100 -#define RA_SCI_SPI9_EVENT 0x0200 -static struct rt_event complete_event = {0}; - -static struct ra_sci_spi_handle spi_handle[] = -{ -#ifdef BSP_USING_SCI_SPI0 - {.bus_name = "scpi0", .spi_ctrl_t = &g_sci_spi0_ctrl, .spi_cfg_t = &g_sci_spi0_cfg,}, -#endif - -#ifdef BSP_USING_SCI_SPI1 - {.bus_name = "scpi1", .spi_ctrl_t = &g_sci_spi1_ctrl, .spi_cfg_t = &g_sci_spi1_cfg,}, -#endif - -#ifdef BSP_USING_SCI_SPI2 - {.bus_name = "scpi2", .spi_ctrl_t = &g_sci_spi2_ctrl, .spi_cfg_t = &g_sci_spi2_cfg,}, -#endif - -#ifdef BSP_USING_SCI_SPI3 - {.bus_name = "scpi3", .spi_ctrl_t = &g_sci_spi3_ctrl, .spi_cfg_t = &g_sci_spi3_cfg,}, -#endif - -#ifdef BSP_USING_SCI_SPI4 - {.bus_name = "scpi4", .spi_ctrl_t = &g_sci_spi4_ctrl, .spi_cfg_t = &g_sci_spi4_cfg,}, -#endif - -#ifdef BSP_USING_SCI_SPI5 - {.bus_name = "scpi5", .spi_ctrl_t = &g_sci_spi5_ctrl, .spi_cfg_t = &g_sci_spi5_cfg,}, -#endif - -#ifdef BSP_USING_SCI_SPI6 - {.bus_name = "scpi6", .spi_ctrl_t = &g_sci_spi6_ctrl, .spi_cfg_t = &g_sci_spi6_cfg,}, -#endif - -#ifdef BSP_USING_SCI_SPI7 - {.bus_name = "scpi7", .spi_ctrl_t = &g_sci_spi7_ctrl, .spi_cfg_t = &g_sci_spi7_cfg,}, -#endif - -#ifdef BSP_USING_SCI_SPI8 - {.bus_name = "scpi8", .spi_ctrl_t = &g_sci_spi8_ctrl, .spi_cfg_t = &g_sci_spi8_cfg,}, -#endif - -#ifdef BSP_USING_SCI_SPI9 - {.bus_name = "scpi9", .spi_ctrl_t = &g_sci_spi9_ctrl, .spi_cfg_t = &g_sci_spi9_cfg,}, -#endif -}; - -static struct ra_sci_spi spi_config[sizeof(spi_handle) / sizeof(spi_handle[0])] = {0}; -#define SCI_SPIx_CALLBACK(n) \ -void sci_spi##n##_callback(spi_callback_args_t *p_args) \ -{ \ - rt_interrupt_enter(); \ - if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event) \ - { \ - rt_event_send(&complete_event, RA_SCI_SPI##n##_EVENT); \ - } \ - rt_interrupt_leave(); \ -} - -SCI_SPIx_CALLBACK(0); -SCI_SPIx_CALLBACK(1); -SCI_SPIx_CALLBACK(2); -SCI_SPIx_CALLBACK(3); -SCI_SPIx_CALLBACK(4); -SCI_SPIx_CALLBACK(5); -SCI_SPIx_CALLBACK(6); -SCI_SPIx_CALLBACK(7); -SCI_SPIx_CALLBACK(8); -SCI_SPIx_CALLBACK(9); - -#define SCI_SPIx_EVENT_RECV(n) \ - rt_event_recv(event, \ - RA_SCI_SPI##n##_EVENT, \ - RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, \ - rt_tick_from_millisecond(1000), \ - &recved); - -static rt_err_t ra_wait_complete(rt_event_t event, const char bus_name[RT_NAME_MAX]) -{ - rt_uint32_t recved = 0x00; - rt_err_t ret = RT_EOK; - - switch (bus_name[4]) - { - case '0': - ret = SCI_SPIx_EVENT_RECV(0); - break; - case '1': - ret = SCI_SPIx_EVENT_RECV(1); - break; - case '2': - ret = SCI_SPIx_EVENT_RECV(2); - break; - case '3': - ret = SCI_SPIx_EVENT_RECV(3); - break; - case '4': - ret = SCI_SPIx_EVENT_RECV(4); - break; - case '5': - ret = SCI_SPIx_EVENT_RECV(5); - break; - case '6': - ret = SCI_SPIx_EVENT_RECV(6); - break; - case '7': - ret = SCI_SPIx_EVENT_RECV(7); - break; - case '8': - ret = SCI_SPIx_EVENT_RECV(8); - break; - case '9': - ret = SCI_SPIx_EVENT_RECV(9); - break; - default: - break; - } - if (ret != RT_EOK) - { - LOG_D("%s ra_wait_complete failed!", bus_name); - return ret; - } - return -RT_EINVAL; -} - -static spi_bit_width_t ra_width_shift(rt_uint8_t data_width) -{ - spi_bit_width_t bit_width = SPI_BIT_WIDTH_8_BITS; - if(data_width == 1) - bit_width = SPI_BIT_WIDTH_8_BITS; - else if(data_width == 2) - bit_width = SPI_BIT_WIDTH_16_BITS; - else if(data_width == 4) - bit_width = SPI_BIT_WIDTH_32_BITS; - - return bit_width; -} - -static rt_err_t ra_write_message(struct rt_spi_device *device, const void *send_buf, const rt_size_t len) -{ - RT_ASSERT(device != NULL); - RT_ASSERT(send_buf != NULL); - RT_ASSERT(len > 0); - rt_err_t err = RT_EOK; - struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus); - - spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width); - /**< send msessage */ - err = R_SCI_SPI_Write((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, send_buf, len, bit_width); - if (RT_EOK != err) - { - LOG_E("%s write failed. %d", spi_dev->ra_spi_handle_t->bus_name, err); - return -RT_ERROR; - } - /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */ - ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name); - return len; -} - -static rt_err_t ra_read_message(struct rt_spi_device *device, void *recv_buf, const rt_size_t len) -{ - RT_ASSERT(device != NULL); - RT_ASSERT(recv_buf != NULL); - RT_ASSERT(len > 0); - rt_err_t err = RT_EOK; - struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus); - - spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width); - /**< receive message */ - err = R_SCI_SPI_Read((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, recv_buf, len, bit_width); - if (RT_EOK != err) - { - LOG_E("%s write failed. %d", spi_dev->ra_spi_handle_t->bus_name, err); - return -RT_ERROR; - } - /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */ - ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name); - return len; -} - -static rt_err_t ra_write_read_message(struct rt_spi_device *device, struct rt_spi_message *message) -{ - RT_ASSERT(device != NULL); - RT_ASSERT(message != NULL); - RT_ASSERT(message->length > 0); - rt_err_t err = RT_EOK; - struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus); - - spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width); - /**< write and receive message */ - err = R_SCI_SPI_WriteRead((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, message->send_buf, message->recv_buf, message->length, bit_width); - if (RT_EOK != err) - { - LOG_E("%s write and read failed. %d", spi_dev->ra_spi_handle_t->bus_name, err); - return -RT_ERROR; - } - /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */ - ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name); - return message->length; -} - -/**< init spi TODO : MSB does not support modification */ -static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device, - struct rt_spi_configuration *configuration) -{ - RT_ASSERT(device != NULL); - RT_ASSERT(configuration != NULL); - rt_err_t err = RT_EOK; - - struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus); - - /**< data_width : 1 -> 8 bits , 2 -> 16 bits, 4 -> 32 bits, default 32 bits*/ - rt_uint8_t data_width = configuration->data_width / 8; - RT_ASSERT(data_width == 1 || data_width == 2 || data_width == 4); - configuration->data_width = configuration->data_width / 8; - spi_dev->rt_spi_cfg_t = configuration; - -#ifdef R_SCI_B_SPI_H - sci_b_spi_extended_cfg_t spi_cfg = *(sci_b_spi_extended_cfg_t *)spi_dev->ra_spi_handle_t->spi_cfg_t->p_extend; -#else - sci_spi_extended_cfg_t *spi_cfg = (sci_spi_extended_cfg_t *)spi_dev->ra_spi_handle_t->spi_cfg_t->p_extend; -#endif - - /**< Configure Select Line */ - rt_pin_write(device->cs_pin, PIN_HIGH); - - /**< config bitrate */ -#ifdef R_SCI_B_SPI_H - R_SCI_B_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, SCI_B_SPI_SOURCE_CLOCK_PCLK, &spi_cfg.clk_div); -#else - R_SCI_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, &spi_cfg->clk_div, false); -#endif - - /**< init */ - err = R_SCI_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t); - /* handle error */ - if(err == FSP_ERR_IN_USE) { - R_SCI_SPI_Close((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t); - err = R_SCI_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t); - } - if (RT_EOK != err) - { - LOG_E("%s init failed. %d", spi_dev->ra_spi_handle_t->bus_name, err); - return -RT_ERROR; - } - return RT_EOK; -} - -static rt_ssize_t ra_spixfer(struct rt_spi_device *device, struct rt_spi_message *message) -{ - RT_ASSERT(device != RT_NULL); - RT_ASSERT(device->bus != RT_NULL); - RT_ASSERT(message != RT_NULL); - - rt_err_t err = RT_EOK; - - if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE)) - { - if (device->config.mode & RT_SPI_CS_HIGH) - rt_pin_write(device->cs_pin, PIN_HIGH); - else - rt_pin_write(device->cs_pin, PIN_LOW); - } - - if (message->length > 0) - { - if (message->send_buf == RT_NULL && message->recv_buf != RT_NULL) - { - /**< receive message */ - err = ra_read_message(device, (void *)message->recv_buf, (const rt_size_t)message->length); - } - else if (message->send_buf != RT_NULL && message->recv_buf == RT_NULL) - { - /**< send message */ - err = ra_write_message(device, (const void *)message->send_buf, (const rt_size_t)message->length); - } - else if (message->send_buf != RT_NULL && message->recv_buf != RT_NULL) - { - /**< send and receive message */ - err = ra_write_read_message(device, message); - } - } - - if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE)) - { - if (device->config.mode & RT_SPI_CS_HIGH) - rt_pin_write(device->cs_pin, PIN_LOW); - else - rt_pin_write(device->cs_pin, PIN_HIGH); - } - return err; -} - -static const struct rt_spi_ops ra_spi_ops = -{ - .configure = ra_hw_spi_configure, - .xfer = ra_spixfer, -}; - -int ra_hw_sci_spi_init(void) -{ - for (rt_uint8_t spi_index = 0; spi_index < sizeof(spi_handle) / sizeof(spi_handle[0]); spi_index++) - { - spi_config[spi_index].ra_spi_handle_t = &spi_handle[spi_index]; - - /**< register spi bus */ - rt_err_t err = rt_spi_bus_register(&spi_config[spi_index].bus, spi_handle[spi_index].bus_name, &ra_spi_ops); - if (RT_EOK != err) - { - LOG_E("%s bus register failed. %d", spi_config[spi_index].ra_spi_handle_t->bus_name, err); - return -RT_ERROR; - } - } - - if (RT_EOK != rt_event_init(&complete_event, "ra_scispi", RT_IPC_FLAG_PRIO)) - { - LOG_E("SPI transfer event init fail!"); - return -RT_ERROR; - } - return RT_EOK; -} -INIT_BOARD_EXPORT(ra_hw_sci_spi_init); - -/** - * Attach the spi device to SPI bus, this function must be used after initialization. - */ -rt_err_t rt_hw_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin) -{ - RT_ASSERT(bus_name != RT_NULL); - RT_ASSERT(device_name != RT_NULL); - - rt_err_t result; - struct rt_spi_device *spi_device; - - /* attach the device to spi bus*/ - spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); - RT_ASSERT(spi_device != RT_NULL); - - result = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, cs_pin, RT_NULL); - if (result != RT_EOK) - { - LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result); - } - - LOG_D("%s attach to %s done", device_name, bus_name); - - return result; -} -#endif /* RT_USING_SPI */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_sci_spi.h b/bsp/renesas/libraries/HAL_Drivers/drv_sci_spi.h deleted file mode 100644 index 4ffc808cc59..00000000000 --- a/bsp/renesas/libraries/HAL_Drivers/drv_sci_spi.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 Mr.Tiger first version - * 2022-12-7 Vandoul ADD sci spi - */ - -#ifndef __DRV_SCI_SPI_H__ -#define __DRV_SCI_SPI_H__ - -#include -#include -#include "hal_data.h" -#include "board.h" -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(R_SCI_SPI_H) || defined(R_SCI_B_SPI_H) -struct ra_sci_spi_handle -{ - const char bus_name[RT_NAME_MAX]; - const spi_cfg_t *spi_cfg_t; -#ifdef R_SCI_B_SPI_H - const sci_b_spi_instance_ctrl_t *spi_ctrl_t; -#else - const sci_spi_instance_ctrl_t *spi_ctrl_t; -#endif -}; - -struct ra_sci_spi -{ - rt_uint32_t cs_pin; - struct ra_sci_spi_handle *ra_spi_handle_t; - struct rt_spi_configuration *rt_spi_cfg_t; - struct rt_spi_bus bus; -}; -#endif - -rt_err_t rt_hw_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin); - -#ifdef __cplusplus -} -#endif - -/* stm32 spi dirver class */ - -#endif /*__DRV_SPI_H__ */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_soft_spi.c b/bsp/renesas/libraries/HAL_Drivers/drv_soft_spi.c index 47535f0f066..a89bf9f92d0 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_soft_spi.c +++ b/bsp/renesas/libraries/HAL_Drivers/drv_soft_spi.c @@ -28,6 +28,8 @@ static struct ra_soft_spi_config soft_spi_config[] = #endif }; +static struct ra_soft_spi spi_obj[sizeof(soft_spi_config) / sizeof(soft_spi_config[0])]; + /** * Attach the spi device to soft SPI bus, this function must be used after initialization. */ @@ -183,9 +185,20 @@ static void ra_udelay(rt_uint32_t us) } } +static void ra_pin_init(void) +{ + rt_size_t obj_num = sizeof(spi_obj) / sizeof(struct ra_soft_spi); + + for(rt_size_t i; i < obj_num; i++) + { + ra_spi_gpio_init(&spi_obj[i]); + } +} + static struct rt_spi_bit_ops ra_soft_spi_ops = { .data = RT_NULL, + .pin_init = ra_pin_init, .tog_sclk = ra_tog_sclk, .set_sclk = ra_set_sclk, .set_mosi = ra_set_mosi, @@ -199,21 +212,18 @@ static struct rt_spi_bit_ops ra_soft_spi_ops = .delay_us = 1, }; -static struct ra_soft_spi spi_obj[sizeof(soft_spi_config) / sizeof(soft_spi_config[0])]; - /* Soft SPI initialization function */ int rt_hw_softspi_init(void) { rt_size_t obj_num = sizeof(spi_obj) / sizeof(struct ra_soft_spi); rt_err_t result; - for (int i = 0; i < obj_num; i++) + for (rt_size_t i = 0; i < obj_num; i++) { memcpy(&spi_obj[i].ops, &ra_soft_spi_ops, sizeof(struct rt_spi_bit_ops)); spi_obj[i].ops.data = (void *)&soft_spi_config[i]; spi_obj[i].spi.ops = &ra_soft_spi_ops; spi_obj[i].cfg = (void *)&soft_spi_config[i]; - ra_spi_gpio_init(&spi_obj[i]); result = rt_spi_bit_add_bus(&spi_obj[i].spi, soft_spi_config[i].bus_name, &spi_obj[i].ops); RT_ASSERT(result == RT_EOK); } diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_soft_spi.h b/bsp/renesas/libraries/HAL_Drivers/drv_soft_spi.h index 018aa9aea32..5f45f1fca0f 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_soft_spi.h +++ b/bsp/renesas/libraries/HAL_Drivers/drv_soft_spi.h @@ -54,4 +54,4 @@ struct ra_soft_spi rt_err_t rt_soft_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin); int rt_soft_spi_init(void); -#endif /* __DRV_SOFT_SPI__ */ \ No newline at end of file +#endif /* __DRV_SOFT_SPI__ */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_spi.c b/bsp/renesas/libraries/HAL_Drivers/drv_spi.c index 992d35ac057..ea3816bd255 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_spi.c +++ b/bsp/renesas/libraries/HAL_Drivers/drv_spi.c @@ -13,7 +13,7 @@ #include "drv_spi.h" -#ifdef RT_USING_SPI +#ifdef BSP_USING_SPI //#define DRV_DEBUG #define DBG_TAG "drv.spi" @@ -310,4 +310,4 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, return result; } -#endif /* RT_USING_SPI */ +#endif /* BSP_USING_SPI */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_usart_v2.c b/bsp/renesas/libraries/HAL_Drivers/drv_usart_v2.c index 0e1e957222e..26c305007a8 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_usart_v2.c +++ b/bsp/renesas/libraries/HAL_Drivers/drv_usart_v2.c @@ -7,6 +7,7 @@ * Date Author Notes * 2021-07-29 KyleChan first version * 2023-10-17 Rbb666 add ra8 adapt + * 2024-03-11 Wangyuqiang add rzt2m adapt */ #include @@ -244,7 +245,7 @@ static int ra_uart_putc(struct rt_serial_device *serial, char c) p_ctrl->p_reg->TDR = c; -#ifdef SOC_SERIES_R7FA8M85 +#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R9A07G0) while ((p_ctrl->p_reg->CSR_b.TEND) == 0); #else while ((p_ctrl->p_reg->SSR_b.TEND) == 0); diff --git a/bsp/renesas/libraries/Kconfig b/bsp/renesas/libraries/Kconfig index 583f1e4a0bd..37b8fcc847c 100644 --- a/bsp/renesas/libraries/Kconfig +++ b/bsp/renesas/libraries/Kconfig @@ -38,3 +38,9 @@ config SOC_SERIES_R7FA8M85 select ARCH_ARM_CORTEX_M85 select SOC_FAMILY_RENESAS default n + +config SOC_SERIES_R9A07G0 + bool + select ARCH_ARM_CORTEX_R52 + select SOC_FAMILY_RENESAS + default n \ No newline at end of file diff --git a/bsp/renesas/ra2l1-cpk/.config b/bsp/renesas/ra2l1-cpk/.config index 6390857ddf1..0d8b8ef3010 100644 --- a/bsp/renesas/ra2l1-cpk/.config +++ b/bsp/renesas/ra2l1-cpk/.config @@ -1074,6 +1074,7 @@ CONFIG_SOC_SERIES_R7FA2L1=y # CONFIG_SOC_SERIES_R7FA6M5 is not set # CONFIG_SOC_SERIES_R7FA4M2 is not set # CONFIG_SOC_SERIES_R7FA8M85 is not set +# CONFIG_SOC_SERIES_R9A07G0 is not set # # Hardware Drivers Config @@ -1102,13 +1103,15 @@ CONFIG_BSP_USING_UART9=y # CONFIG_BSP_UART9_TX_USING_DMA is not set CONFIG_BSP_UART9_RX_BUFSIZE=256 CONFIG_BSP_UART9_TX_BUFSIZE=0 -# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_HW_I2C is not set +# CONFIG_BSP_USING_SOFT_I2C is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_DAC is not set # CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_CAN is not set # CONFIG_BSP_USING_LPM is not set +# CONFIG_BSP_USING_SCI is not set # # Board extended module Drivers diff --git a/bsp/renesas/ra2l1-cpk/.settings/standalone.prefs b/bsp/renesas/ra2l1-cpk/.settings/standalone.prefs index 424c387404c..89e7ade6941 100644 --- a/bsp/renesas/ra2l1-cpk/.settings/standalone.prefs +++ b/bsp/renesas/ra2l1-cpk/.settings/standalone.prefs @@ -1,21 +1,19 @@ -#Fri Jul 22 15:41:36 CST 2022 +#Sat Apr 13 23:24:56 CST 2024 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries= com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra2l1_cpk\#\#\#\#3.5.0/all=2985489297,ra/board/ra2l1_cpk/board_init.h|383876238,ra/board/ra2l1_cpk/board_leds.h|2918861270,ra/board/ra2l1_cpk/board_leds.c|586415029,ra/board/ra2l1_cpk/board.h|1521504391,ra/board/ra2l1_cpk/board_init.c -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|2425160085,ra/fsp/inc/api/bsp_api.h|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2208590403,ra/fsp/inc/instances/r_ioport.h|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|3297195641,ra/fsp/inc/fsp_version.h|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|546480625,ra/fsp/inc/fsp_common_api.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|1728953905,ra/fsp/inc/fsp_features.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra2l1_cpk\#\#\#\#3.5.0/all=ra/board/ra2l1_cpk/board_init.h|ra/board/ra2l1_cpk/board_leds.h|ra/board/ra2l1_cpk/board_leds.c|ra/board/ra2l1_cpk/board.h|ra/board/ra2l1_cpk/board_init.c +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|3297195641,ra/fsp/inc/fsp_version.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|2208590403,ra/fsp/inc/instances/r_ioport.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1728953905,ra/fsp/inc/fsp_features.h|2425160085,ra/fsp/inc/api/bsp_api.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|546480625,ra/fsp/inc/fsp_common_api.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#device\#\#R7FA2L1AB2DFM\#\#3.5.0/libraries= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries= -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#fsp\#\#\#\#3.5.0/all=3828286676,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h|3050420323,ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h|4018024988,ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h|4234922905,ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h|286820788,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c|3229315956,ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#fsp\#\#\#\#3.5.0/all=3050420323,ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h|4018024988,ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h|3828286676,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h|3229315956,ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h|4234922905,ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h|286820788,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator -com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h +com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra2l1_cpk\#\#\#\#3.5.0/libraries= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#device\#\#\#\#3.5.0/libraries= -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/libraries= -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=1939984091,ra/fsp/inc/api/r_ioport_api.h|3254285722,ra/fsp/src/r_ioport/r_ioport.c|2208590403,ra/fsp/inc/instances/r_ioport.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=3254285722,ra/fsp/src/r_ioport/r_ioport.c|1939984091,ra/fsp/inc/api/r_ioport_api.h|2208590403,ra/fsp/inc/instances/r_ioport.h com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#fsp\#\#\#\#3.5.0/libraries= -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/all=2545672180,ra/fsp/inc/instances/r_icu.h|1906465970,ra/fsp/inc/api/r_external_irq_api.h|3018483678,ra/fsp/src/r_icu/r_icu.c -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=1889256766,ra/fsp/inc/instances/r_sci_uart.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|3916852077,ra/fsp/inc/api/r_uart_api.h|1610456547,ra/fsp/inc/api/r_transfer_api.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=1610456547,ra/fsp/inc/api/r_transfer_api.h|1889256766,ra/fsp/inc/instances/r_sci_uart.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|3916852077,ra/fsp/inc/api/r_uart_api.h com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.629312687=false com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries= diff --git a/bsp/renesas/ra2l1-cpk/board/Kconfig b/bsp/renesas/ra2l1-cpk/board/Kconfig index c1113b4bc7d..ae81aec2f29 100644 --- a/bsp/renesas/ra2l1-cpk/board/Kconfig +++ b/bsp/renesas/ra2l1-cpk/board/Kconfig @@ -161,36 +161,37 @@ menu "Hardware Drivers Config" endif endif - menuconfig BSP_USING_I2C - bool "Enable I2C BUS" + menuconfig BSP_USING_HW_I2C + bool "Enable hardware I2C BUS" default n + if BSP_USING_HW_I2C + config BSP_USING_HW_I2C1 + bool "Enable Hardware I2C1 BUS" + default n + endif + + menuconfig BSP_USING_SOFT_I2C + bool "Enable software I2C bus" select RT_USING_I2C select RT_USING_I2C_BITOPS select RT_USING_PIN - if BSP_USING_I2C - config BSP_USING_HW_I2C - bool "Enable Hardware I2C BUS" - default n - if BSP_USING_HW_I2C - config BSP_USING_HW_I2C1 - bool "Enable Hardware I2C1 BUS" - default n - endif - if !BSP_USING_HW_I2C - menuconfig BSP_USING_I2C1 - bool "Enable I2C1 BUS (software simulation)" - default y - if BSP_USING_I2C1 - config BSP_I2C1_SCL_PIN - hex "i2c1 scl pin number" - range 0x0000 0x0B0F - default 0x050C - config BSP_I2C1_SDA_PIN - hex "I2C1 sda pin number" - range 0x0000 0x0B0F - default 0x050B - endif - endif + default n + if BSP_USING_SOFT_I2C + config BSP_USING_SOFT_I2C + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 Bus (software simulation)" + default n + if BSP_USING_I2C1 + comment "Please refer to the 'bsp_io.h' file to configure the pins" + config BSP_I2C1_SCL_PIN + hex "i2c1 scl pin number (hex)" + range 0x0000 0xFFFF + default 0x050C + config BSP_I2C1_SDA_PIN + hex "i2c1 sda pin number (hex)" + range 0x0000 0xFFFF + default 0x050B + endif endif menuconfig BSP_USING_SPI @@ -305,6 +306,325 @@ menu "Hardware Drivers Config" default n endif + menuconfig BSP_USING_SCI + bool "Enable SCI Controller" + default n + + + + if BSP_USING_SCI + config BSP_USING_SCI0 + bool "Enable SCI0" + default n + if BSP_USING_SCI0 + choice + prompt "choice sci mode" + default BSP_USING_SCI0_SPI + config BSP_USING_SCI0_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI0_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI0_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI0_UART + config BSP_SCI0_UART_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI0_UART_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI1 + bool "Enable SCI1" + default n + if BSP_USING_SCI1 + choice + prompt "choice sci mode" + default BSP_USING_SCI1_SPI + config BSP_USING_SCI1_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI1_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI1_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI1_UART + config BSP_SCI1_UART_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI1_UART_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI2 + bool "Enable SCI2" + default n + if BSP_USING_SCI2 + choice + prompt "choice sci mode" + default BSP_USING_SCI2_SPI + config BSP_USING_SCI2_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI2_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI2_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI2_UART + config BSP_SCI2_UART_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI2_UART_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI3 + bool "Enable SCI3" + default n + if BSP_USING_SCI3 + choice + prompt "choice sci mode" + default BSP_USING_SCI3_SPI + config BSP_USING_SCI3_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI3_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI3_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI3_UART + config BSP_SCI3_UART_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI3_UART_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI4 + bool "Enable SCI4" + default n + if BSP_USING_SCI4 + choice + prompt "choice sci mode" + default BSP_USING_SCI4_SPI + config BSP_USING_SCI4_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI4_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI4_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI4_UART + config BSP_SCI4_UART_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI4_UART_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI5 + bool "Enable SCI5" + default n + if BSP_USING_SCI5 + choice + prompt "choice sci mode" + default BSP_USING_SCI5_SPI + config BSP_USING_SCI5_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI5_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI5_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI5_UART + config BSP_SCI5_UART_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI5_UART_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI6 + bool "Enable SCI6" + default n + if BSP_USING_SCI6 + choice + prompt "choice sci mode" + default BSP_USING_SCI6_SPI + config BSP_USING_SCI6_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI6_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI6_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI6_UART + config BSP_SCI6_UART_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI6_UART_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI7 + bool "Enable SCI7" + default n + if BSP_USING_SCI7 + choice + prompt "choice sci mode" + default BSP_USING_SCI7_SPI + config BSP_USING_SCI7_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI7_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI7_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI7_UART + config BSP_SCI7_UART_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI7_UART_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI8 + bool "Enable SCI8" + default n + if BSP_USING_SCI8 + choice + prompt "choice sci mode" + default BSP_USING_SCI8_SPI + config BSP_USING_SCI8_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI8_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI8_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI8_UART + config BSP_SCI8_UART_RX_BUFSIZE + int "Set UART8 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI8_UART_TX_BUFSIZE + int "Set UART8 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI9 + bool "Enable SCI9" + default n + if BSP_USING_SCI9 + choice + prompt "choice sci mode" + default BSP_USING_SCI9_SPI + config BSP_USING_SCI9_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI9_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI9_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI9_UART + config BSP_SCI9_UART_RX_BUFSIZE + int "Set UART9 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI9_UART_TX_BUFSIZE + int "Set UART9 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + endif + endmenu menu "Board extended module Drivers" diff --git a/bsp/renesas/ra2l1-cpk/buildinfo.gpdsc b/bsp/renesas/ra2l1-cpk/buildinfo.gpdsc index ac952351b88..350c6657007 100644 --- a/bsp/renesas/ra2l1-cpk/buildinfo.gpdsc +++ b/bsp/renesas/ra2l1-cpk/buildinfo.gpdsc @@ -56,45 +56,56 @@ - - + + + + + + + + + + + + + @@ -102,9 +113,12 @@ - + + + + @@ -112,13 +126,11 @@ - - diff --git a/bsp/renesas/ra2l1-cpk/configuration.xml b/bsp/renesas/ra2l1-cpk/configuration.xml index 6d86fbaad90..d16698ac4d6 100644 --- a/bsp/renesas/ra2l1-cpk/configuration.xml +++ b/bsp/renesas/ra2l1-cpk/configuration.xml @@ -150,10 +150,6 @@ SCI UART Renesas.RA.3.5.0.pack - - External Interrupt - Renesas.RA.3.5.0.pack - @@ -192,26 +188,13 @@ - - - - - - - - - - - - - diff --git a/bsp/renesas/ra2l1-cpk/project.uvprojx b/bsp/renesas/ra2l1-cpk/project.uvprojx index bcd71bdc9d5..1ff85fde47d 100644 --- a/bsp/renesas/ra2l1-cpk/project.uvprojx +++ b/bsp/renesas/ra2l1-cpk/project.uvprojx @@ -476,6 +476,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/renesas/ra2l1-cpk/ra/fsp/inc/api/r_external_irq_api.h b/bsp/renesas/ra2l1-cpk/ra/fsp/inc/api/r_external_irq_api.h deleted file mode 100644 index c024a94c1f6..00000000000 --- a/bsp/renesas/ra2l1-cpk/ra/fsp/inc/api/r_external_irq_api.h +++ /dev/null @@ -1,177 +0,0 @@ -/*********************************************************************************************************************** - * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. - * - * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products - * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are - * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use - * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property - * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas - * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION - * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT - * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR - * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM - * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION - * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, - * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, - * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY - * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @ingroup RENESAS_INTERFACES - * @defgroup EXTERNAL_IRQ_API External IRQ Interface - * @brief Interface for detecting external interrupts. - * - * @section EXTERNAL_IRQ_API_Summary Summary - * The External IRQ Interface is for configuring interrupts to fire when a trigger condition is detected on an - * external IRQ pin. - * - * The External IRQ Interface can be implemented by: - * - @ref ICU - * - * @{ - **********************************************************************************************************************/ - -#ifndef R_EXTERNAL_IRQ_API_H -#define R_EXTERNAL_IRQ_API_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ - -/* Includes board and MCU related header files. */ -#include "bsp_api.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/********************************************************************************************************************** - * Macro definitions - *********************************************************************************************************************/ - -/********************************************************************************************************************* - * Typedef definitions - *********************************************************************************************************************/ - -/** Callback function parameter data */ -typedef struct st_external_irq_callback_args -{ - /** Placeholder for user data. Set in @ref external_irq_api_t::open function in @ref external_irq_cfg_t. */ - void const * p_context; - uint32_t channel; ///< The physical hardware channel that caused the interrupt. -} external_irq_callback_args_t; - -/** Condition that will trigger an interrupt when detected. */ -typedef enum e_external_irq_trigger -{ - EXTERNAL_IRQ_TRIG_FALLING = 0, ///< Falling edge trigger - EXTERNAL_IRQ_TRIG_RISING = 1, ///< Rising edge trigger - EXTERNAL_IRQ_TRIG_BOTH_EDGE = 2, ///< Both edges trigger - EXTERNAL_IRQ_TRIG_LEVEL_LOW = 3, ///< Low level trigger -} external_irq_trigger_t; - -/** External IRQ input pin digital filtering sample clock divisor settings. The digital filter rejects trigger - * conditions that are shorter than 3 periods of the filter clock. - */ -typedef enum e_external_irq_pclk_div -{ - EXTERNAL_IRQ_PCLK_DIV_BY_1 = 0, ///< Filter using PCLK divided by 1 - EXTERNAL_IRQ_PCLK_DIV_BY_8 = 1, ///< Filter using PCLK divided by 8 - EXTERNAL_IRQ_PCLK_DIV_BY_32 = 2, ///< Filter using PCLK divided by 32 - EXTERNAL_IRQ_PCLK_DIV_BY_64 = 3, ///< Filter using PCLK divided by 64 -} external_irq_pclk_div_t; - -/** User configuration structure, used in open function */ -typedef struct st_external_irq_cfg -{ - uint8_t channel; ///< Hardware channel used. - uint8_t ipl; ///< Interrupt priority - IRQn_Type irq; ///< NVIC interrupt number assigned to this instance - external_irq_trigger_t trigger; ///< Trigger setting. - external_irq_pclk_div_t pclk_div; ///< Digital filter clock divisor setting. - bool filter_enable; ///< Digital filter enable/disable setting. - - /** Callback provided external input trigger occurs. */ - void (* p_callback)(external_irq_callback_args_t * p_args); - - /** Placeholder for user data. Passed to the user callback in @ref external_irq_callback_args_t. */ - void const * p_context; - void const * p_extend; ///< External IRQ hardware dependent configuration. -} external_irq_cfg_t; - -/** External IRQ control block. Allocate an instance specific control block to pass into the external IRQ API calls. - * @par Implemented as - * - icu_instance_ctrl_t - */ -typedef void external_irq_ctrl_t; - -/** External interrupt driver structure. External interrupt functions implemented at the HAL layer will follow this API. */ -typedef struct st_external_irq_api -{ - /** Initial configuration. - * @par Implemented as - * - @ref R_ICU_ExternalIrqOpen() - * - * @param[out] p_ctrl Pointer to control block. Must be declared by user. Value set here. - * @param[in] p_cfg Pointer to configuration structure. All elements of the structure must be set by user. - */ - fsp_err_t (* open)(external_irq_ctrl_t * const p_ctrl, external_irq_cfg_t const * const p_cfg); - - /** Enable callback when an external trigger condition occurs. - * @par Implemented as - * - @ref R_ICU_ExternalIrqEnable() - * - * @param[in] p_ctrl Control block set in Open call for this external interrupt. - */ - fsp_err_t (* enable)(external_irq_ctrl_t * const p_ctrl); - - /** Disable callback when external trigger condition occurs. - * @par Implemented as - * - @ref R_ICU_ExternalIrqDisable() - * - * @param[in] p_ctrl Control block set in Open call for this external interrupt. - */ - fsp_err_t (* disable)(external_irq_ctrl_t * const p_ctrl); - - /** - * Specify callback function and optional context pointer and working memory pointer. - * @par Implemented as - * - R_ICU_ExternalIrqCallbackSet() - * - * @param[in] p_ctrl Pointer to the Extneral IRQ control block. - * @param[in] p_callback Callback function - * @param[in] p_context Pointer to send to callback function - * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. - * Callback arguments allocated here are only valid during the callback. - */ - fsp_err_t (* callbackSet)(external_irq_ctrl_t * const p_api_ctrl, - void ( * p_callback)(external_irq_callback_args_t *), - void const * const p_context, - external_irq_callback_args_t * const p_callback_memory); - - /** Allow driver to be reconfigured. May reduce power consumption. - * @par Implemented as - * - @ref R_ICU_ExternalIrqClose() - * - * @param[in] p_ctrl Control block set in Open call for this external interrupt. - */ - fsp_err_t (* close)(external_irq_ctrl_t * const p_ctrl); -} external_irq_api_t; - -/** This structure encompasses everything that is needed to use an instance of this interface. */ -typedef struct st_external_irq_instance -{ - external_irq_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance - external_irq_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance - external_irq_api_t const * p_api; ///< Pointer to the API structure for this instance -} external_irq_instance_t; - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -/*******************************************************************************************************************//** - * @} (end defgroup EXTERNAL_IRQ_API) - **********************************************************************************************************************/ - -#endif diff --git a/bsp/renesas/ra2l1-cpk/ra/fsp/inc/instances/r_icu.h b/bsp/renesas/ra2l1-cpk/ra/fsp/inc/instances/r_icu.h deleted file mode 100644 index 800091b6b9a..00000000000 --- a/bsp/renesas/ra2l1-cpk/ra/fsp/inc/instances/r_icu.h +++ /dev/null @@ -1,95 +0,0 @@ -/*********************************************************************************************************************** - * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. - * - * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products - * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are - * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use - * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property - * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas - * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION - * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT - * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR - * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM - * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION - * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, - * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, - * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY - * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * @addtogroup ICU - * @{ - **********************************************************************************************************************/ - -#ifndef R_ICU_H -#define R_ICU_H - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "bsp_api.h" -#include "r_external_irq_api.h" - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ -FSP_HEADER - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/********************************************************************************************************************* - * Typedef definitions - *********************************************************************************************************************/ - -/** ICU private control block. DO NOT MODIFY. Initialization occurs when R_ICU_ExternalIrqOpen is called. */ -typedef struct st_icu_instance_ctrl -{ - uint32_t open; ///< Used to determine if channel control block is in use - IRQn_Type irq; ///< NVIC interrupt number - uint8_t channel; ///< Channel - -#if BSP_TZ_SECURE_BUILD - external_irq_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. -#endif - void (* p_callback)(external_irq_callback_args_t * p_args); // Pointer to callback that is called when an edge is detected on the external irq pin. - - /** Placeholder for user data. Passed to the user callback in ::external_irq_callback_args_t. */ - void const * p_context; -} icu_instance_ctrl_t; - -/********************************************************************************************************************** - * Exported global variables - **********************************************************************************************************************/ - -/** @cond INC_HEADER_DEFS_SEC */ -/** Filled in Interface API structure for this Instance. */ -extern const external_irq_api_t g_external_irq_on_icu; - -/** @endcond */ - -/*********************************************************************************************************************** - * Public APIs - **********************************************************************************************************************/ -fsp_err_t R_ICU_ExternalIrqOpen(external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg); - -fsp_err_t R_ICU_ExternalIrqEnable(external_irq_ctrl_t * const p_api_ctrl); - -fsp_err_t R_ICU_ExternalIrqDisable(external_irq_ctrl_t * const p_api_ctrl); - -fsp_err_t R_ICU_ExternalIrqCallbackSet(external_irq_ctrl_t * const p_api_ctrl, - void ( * p_callback)(external_irq_callback_args_t *), - void const * const p_context, - external_irq_callback_args_t * const p_callback_memory); - -fsp_err_t R_ICU_ExternalIrqClose(external_irq_ctrl_t * const p_api_ctrl); - -/*******************************************************************************************************************//** - * @} (end defgroup ICU) - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ -FSP_FOOTER - -#endif // R_ICU_H diff --git a/bsp/renesas/ra2l1-cpk/ra/fsp/src/r_icu/r_icu.c b/bsp/renesas/ra2l1-cpk/ra/fsp/src/r_icu/r_icu.c deleted file mode 100644 index 69b5e3ed944..00000000000 --- a/bsp/renesas/ra2l1-cpk/ra/fsp/src/r_icu/r_icu.c +++ /dev/null @@ -1,370 +0,0 @@ -/*********************************************************************************************************************** - * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. - * - * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products - * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are - * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use - * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property - * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas - * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION - * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT - * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR - * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM - * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION - * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, - * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, - * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY - * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ -#include "r_icu.h" -#include "r_icu_cfg.h" - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/** "ICU" in ASCII, used to determine if channel is open. */ -#define ICU_OPEN (0x00494355U) - -#define ICU_IRQMD_OFFSET (0) -#define ICU_FCLKSEL_OFFSET (4) -#define ICU_FLTEN_OFFSET (7) - -/*********************************************************************************************************************** - * Typedef definitions - **********************************************************************************************************************/ - -#if defined(__ARMCC_VERSION) || defined(__ICCARM__) -typedef void (BSP_CMSE_NONSECURE_CALL * icu_prv_ns_callback)(external_irq_callback_args_t * p_args); -#elif defined(__GNUC__) -typedef BSP_CMSE_NONSECURE_CALL void (*volatile icu_prv_ns_callback)(external_irq_callback_args_t * p_args); -#endif - -/*********************************************************************************************************************** - * Private function prototypes - **********************************************************************************************************************/ -void r_icu_isr(void); - -/*********************************************************************************************************************** - * Private global variables - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Global Variables - **********************************************************************************************************************/ - -/* ICU implementation of External IRQ API. */ -const external_irq_api_t g_external_irq_on_icu = -{ - .open = R_ICU_ExternalIrqOpen, - .enable = R_ICU_ExternalIrqEnable, - .disable = R_ICU_ExternalIrqDisable, - .callbackSet = R_ICU_ExternalIrqCallbackSet, - .close = R_ICU_ExternalIrqClose, -}; - -/*******************************************************************************************************************//** - * @addtogroup ICU - * @{ - **********************************************************************************************************************/ - -/*********************************************************************************************************************** - * Functions - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * Configure an IRQ input pin for use with the external interrupt interface. Implements @ref external_irq_api_t::open. - * - * The Open function is responsible for preparing an external IRQ pin for operation. - * - * @retval FSP_SUCCESS Open successful. - * @retval FSP_ERR_ASSERTION One of the following is invalid: - * - p_ctrl or p_cfg is NULL - * @retval FSP_ERR_ALREADY_OPEN The channel specified has already been opened. No configurations were changed. - * Call the associated Close function to reconfigure the channel. - * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in p_cfg is not available on the device selected in - * r_bsp_cfg.h. - * @retval FSP_ERR_INVALID_ARGUMENT p_cfg->p_callback is not NULL, but ISR is not enabled. ISR must be enabled to - * use callback function. - * - * @note This function is reentrant for different channels. It is not reentrant for the same channel. - **********************************************************************************************************************/ -fsp_err_t R_ICU_ExternalIrqOpen (external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg) -{ - icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl; - -#if ICU_CFG_PARAM_CHECKING_ENABLE - FSP_ASSERT(NULL != p_ctrl); - FSP_ERROR_RETURN(ICU_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); - FSP_ASSERT(NULL != p_cfg); - FSP_ERROR_RETURN(0 != ((1U << p_cfg->channel) & BSP_FEATURE_ICU_IRQ_CHANNELS_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT); - - /* Callback must be used with a valid interrupt priority otherwise it will never be called. */ - if (p_cfg->p_callback) - { - FSP_ERROR_RETURN(BSP_IRQ_DISABLED != p_cfg->ipl, FSP_ERR_INVALID_ARGUMENT); - } -#endif - - p_ctrl->irq = p_cfg->irq; - - /* IELSR Must be zero when modifying the IRQCR bits. - * (See ICU Section 14.2.1 of the RA6M3 manual R01UH0886EJ0100). */ - uint32_t ielsr = R_ICU->IELSR[p_ctrl->irq]; - R_ICU->IELSR[p_ctrl->irq] = 0; - -#if BSP_TZ_SECURE_BUILD - - /* If this is a secure build, the callback provided in p_cfg must be secure. */ - p_ctrl->p_callback_memory = NULL; -#endif - - /* Initialize control block. */ - p_ctrl->p_callback = p_cfg->p_callback; - p_ctrl->p_context = p_cfg->p_context; - p_ctrl->channel = p_cfg->channel; - - /* Disable digital filter */ - R_ICU->IRQCR[p_ctrl->channel] = 0U; - - /* Set the digital filter divider. */ - uint8_t irqcr = (uint8_t) (p_cfg->pclk_div << ICU_FCLKSEL_OFFSET); - - /* Enable/Disable digital filter. */ - irqcr |= (uint8_t) (p_cfg->filter_enable << ICU_FLTEN_OFFSET); - - /* Set the IRQ trigger. */ - irqcr |= (uint8_t) (p_cfg->trigger << ICU_IRQMD_OFFSET); - - /* Write IRQCR */ - R_ICU->IRQCR[p_ctrl->channel] = irqcr; - - /* Restore IELSR. */ - R_ICU->IELSR[p_ctrl->irq] = ielsr; - - /* NOTE: User can have the driver opened when the IRQ is not in the vector table. This is for use cases - * where the external IRQ driver is used to generate ELC events only (without CPU interrupts). - * In such cases we will not set the IRQ priority but will continue with the processing. - */ - if (p_ctrl->irq >= 0) - { - R_BSP_IrqCfg(p_ctrl->irq, p_cfg->ipl, p_ctrl); - } - - /* Mark the control block as open */ - p_ctrl->open = ICU_OPEN; - - return FSP_SUCCESS; -} - -/*******************************************************************************************************************//** - * Enable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::enable. - * - * @retval FSP_SUCCESS Interrupt Enabled successfully. - * @retval FSP_ERR_ASSERTION The p_ctrl parameter was null. - * @retval FSP_ERR_NOT_OPEN The channel is not opened. - * @retval FSP_ERR_IRQ_BSP_DISABLED Requested IRQ is not defined in this system - **********************************************************************************************************************/ -fsp_err_t R_ICU_ExternalIrqEnable (external_irq_ctrl_t * const p_api_ctrl) -{ - icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl; - -#if ICU_CFG_PARAM_CHECKING_ENABLE - FSP_ASSERT(NULL != p_ctrl); - FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); - FSP_ERROR_RETURN(p_ctrl->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); -#endif - - /* Clear the interrupt status and Pending bits, before the interrupt is enabled. */ - R_BSP_IrqEnable(p_ctrl->irq); - - return FSP_SUCCESS; -} - -/*******************************************************************************************************************//** - * Disable external interrupt for specified channel at NVIC. Implements @ref external_irq_api_t::disable. - * - * @retval FSP_SUCCESS Interrupt disabled successfully. - * @retval FSP_ERR_ASSERTION The p_ctrl parameter was null. - * @retval FSP_ERR_NOT_OPEN The channel is not opened. - * @retval FSP_ERR_IRQ_BSP_DISABLED Requested IRQ is not defined in this system - **********************************************************************************************************************/ -fsp_err_t R_ICU_ExternalIrqDisable (external_irq_ctrl_t * const p_api_ctrl) -{ - icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl; - -#if ICU_CFG_PARAM_CHECKING_ENABLE - FSP_ASSERT(NULL != p_ctrl); - FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); - FSP_ERROR_RETURN(p_ctrl->irq >= 0, FSP_ERR_IRQ_BSP_DISABLED); -#endif - - /* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */ - R_BSP_IrqDisable(p_ctrl->irq); - - return FSP_SUCCESS; -} - -/*******************************************************************************************************************//** - * Updates the user callback and has option of providing memory for callback structure. - * Implements external_irq_api_t::callbackSet - * - * @retval FSP_SUCCESS Callback updated successfully. - * @retval FSP_ERR_ASSERTION A required pointer is NULL. - * @retval FSP_ERR_NOT_OPEN The control block has not been opened. - * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. - **********************************************************************************************************************/ -fsp_err_t R_ICU_ExternalIrqCallbackSet (external_irq_ctrl_t * const p_api_ctrl, - void ( * p_callback)( - external_irq_callback_args_t *), - void const * const p_context, - external_irq_callback_args_t * const p_callback_memory) -{ - icu_instance_ctrl_t * p_ctrl = p_api_ctrl; - -#if BSP_TZ_SECURE_BUILD - - /* cmse_check_address_range returns NULL if p_callback is located in secure memory */ - bool callback_is_secure = - (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); -#else - FSP_PARAMETER_NOT_USED(p_callback_memory); -#endif - -#if ICU_CFG_PARAM_CHECKING_ENABLE - FSP_ASSERT(NULL != p_ctrl); - FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); - FSP_ASSERT(NULL != p_callback); - - #if BSP_TZ_SECURE_BUILD - - /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ - external_irq_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, - CMSE_AU_NONSECURE); - FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); - #endif -#endif - -#if BSP_TZ_SECURE_BUILD - p_ctrl->p_callback_memory = p_callback_memory; - p_ctrl->p_callback = callback_is_secure ? p_callback : - (void (*)(external_irq_callback_args_t *))cmse_nsfptr_create(p_callback); -#else - p_ctrl->p_callback = p_callback; -#endif - p_ctrl->p_context = p_context; - - return FSP_SUCCESS; -} - -/*******************************************************************************************************************//** - * Close the external interrupt channel. Implements @ref external_irq_api_t::close. - * - * @retval FSP_SUCCESS Successfully closed. - * @retval FSP_ERR_ASSERTION The parameter p_ctrl is NULL. - * @retval FSP_ERR_NOT_OPEN The channel is not opened. - **********************************************************************************************************************/ -fsp_err_t R_ICU_ExternalIrqClose (external_irq_ctrl_t * const p_api_ctrl) -{ - icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) p_api_ctrl; - -#if ICU_CFG_PARAM_CHECKING_ENABLE - FSP_ASSERT(NULL != p_ctrl); - FSP_ERROR_RETURN(ICU_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); -#endif - - /* Cleanup. Disable interrupt */ - if (p_ctrl->irq >= 0) - { - /* Disable the interrupt, and then clear the interrupt pending bits and interrupt status. */ - R_BSP_IrqDisable(p_ctrl->irq); - R_FSP_IsrContextSet(p_ctrl->irq, NULL); - } - - p_ctrl->open = 0U; - - return FSP_SUCCESS; -} - -/*******************************************************************************************************************//** - * @} (end addtogroup ICU) - **********************************************************************************************************************/ - -/*******************************************************************************************************************//** - * ICU External Interrupt ISR. - **********************************************************************************************************************/ -void r_icu_isr (void) -{ - /* Save context if RTOS is used */ - FSP_CONTEXT_SAVE - - IRQn_Type irq = R_FSP_CurrentIrqGet(); - icu_instance_ctrl_t * p_ctrl = (icu_instance_ctrl_t *) R_FSP_IsrContextGet(irq); - - bool level_irq = false; - if (EXTERNAL_IRQ_TRIG_LEVEL_LOW == R_ICU->IRQCR_b[p_ctrl->channel].IRQMD) - { - level_irq = true; - } - else - { - /* Clear the IR bit before calling the user callback so that if an edge is detected while the ISR is active - * it will not be missed. */ - R_BSP_IrqStatusClear(irq); - } - - if ((NULL != p_ctrl) && (NULL != p_ctrl->p_callback)) - { -#if BSP_TZ_SECURE_BUILD - - /* p_callback can point to a secure function or a non-secure function. */ - external_irq_callback_args_t args; - if (!cmse_is_nsfptr(p_ctrl->p_callback)) - { - /* If p_callback is secure, then the project does not need to change security state. */ - args.channel = p_ctrl->channel; - args.p_context = p_ctrl->p_context; - p_ctrl->p_callback(&args); - } - else - { - /* Save current state of p_callback_args so that it can be shared between interrupts. */ - args = *p_ctrl->p_callback_memory; - - /* Set the callback args passed to the Non-secure calback. */ - p_ctrl->p_callback_memory->channel = p_ctrl->channel; - p_ctrl->p_callback_memory->p_context = p_ctrl->p_context; - - /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ - icu_prv_ns_callback p_callback = (icu_prv_ns_callback) (p_ctrl->p_callback); - p_callback(p_ctrl->p_callback_memory); - - /* Restore the state of p_callback_args. */ - *p_ctrl->p_callback_memory = args; - } - -#else - - /* Set data to identify callback to user, then call user callback. */ - external_irq_callback_args_t args; - args.channel = p_ctrl->channel; - args.p_context = p_ctrl->p_context; - p_ctrl->p_callback(&args); -#endif - } - - if (level_irq) - { - /* Clear the IR bit after calling the user callback so that if the condition is cleared the ISR will not - * be called again. */ - R_BSP_IrqStatusClear(irq); - } - - /* Restore context if RTOS is used */ - FSP_CONTEXT_RESTORE -} diff --git a/bsp/renesas/ra2l1-cpk/ra_cfg/fsp_cfg/r_icu_cfg.h b/bsp/renesas/ra2l1-cpk/ra_cfg/fsp_cfg/r_icu_cfg.h deleted file mode 100644 index 5e77b6980f4..00000000000 --- a/bsp/renesas/ra2l1-cpk/ra_cfg/fsp_cfg/r_icu_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_ICU_CFG_H_ -#define R_ICU_CFG_H_ -#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#endif /* R_ICU_CFG_H_ */ diff --git a/bsp/renesas/ra2l1-cpk/ra_gen/hal_data.c b/bsp/renesas/ra2l1-cpk/ra_gen/hal_data.c index 7a8f64ba85b..0e609580bdc 100644 --- a/bsp/renesas/ra2l1-cpk/ra_gen/hal_data.c +++ b/bsp/renesas/ra2l1-cpk/ra_gen/hal_data.c @@ -1,34 +1,5 @@ /* generated HAL source file - do not edit */ #include "hal_data.h" -icu_instance_ctrl_t g_external_irq3_ctrl; -const external_irq_cfg_t g_external_irq3_cfg = -{ - .channel = 3, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = irq_callback, - /** If NULL then do not add & */ -#if defined(NULL) - .p_context = NULL, -#else - .p_context = &NULL, -#endif - .p_extend = NULL, - .ipl = (2), -#if defined(VECTOR_NUMBER_ICU_IRQ3) - .irq = VECTOR_NUMBER_ICU_IRQ3, -#else - .irq = FSP_INVALID_VECTOR, -#endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq3 = -{ - .p_ctrl = &g_external_irq3_ctrl, - .p_cfg = &g_external_irq3_cfg, - .p_api = &g_external_irq_on_icu -}; sci_uart_instance_ctrl_t g_uart9_ctrl; baud_setting_t g_uart9_baud_setting = diff --git a/bsp/renesas/ra2l1-cpk/ra_gen/hal_data.h b/bsp/renesas/ra2l1-cpk/ra_gen/hal_data.h index da137063093..7e3e2152a57 100644 --- a/bsp/renesas/ra2l1-cpk/ra_gen/hal_data.h +++ b/bsp/renesas/ra2l1-cpk/ra_gen/hal_data.h @@ -4,21 +4,9 @@ #include #include "bsp_api.h" #include "common_data.h" -#include "r_icu.h" -#include "r_external_irq_api.h" #include "r_sci_uart.h" #include "r_uart_api.h" FSP_HEADER -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq3; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq3_ctrl; -extern const external_irq_cfg_t g_external_irq3_cfg; - -#ifndef irq_callback -void irq_callback(external_irq_callback_args_t * p_args); -#endif /** UART on SCI Instance. */ extern const uart_instance_t g_uart9; diff --git a/bsp/renesas/ra2l1-cpk/ra_gen/vector_data.c b/bsp/renesas/ra2l1-cpk/ra_gen/vector_data.c index 05f6fb9ca9a..da99e3229bc 100644 --- a/bsp/renesas/ra2l1-cpk/ra_gen/vector_data.c +++ b/bsp/renesas/ra2l1-cpk/ra_gen/vector_data.c @@ -4,15 +4,13 @@ #if VECTOR_DATA_IRQ_COUNT > 0 BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = { - [3] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */ - [4] = sci_uart_rxi_isr, /* SCI9 RXI (Received data full) */ + [4] = sci_uart_rxi_isr, /* SCI9 RXI (Received data full) */ [5] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */ [6] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */ [7] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */ }; const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = { - [3] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */ [4] = BSP_PRV_IELS_ENUM(EVENT_SCI9_RXI), /* SCI9 RXI (Received data full) */ [5] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI), /* SCI9 TXI (Transmit data empty) */ [6] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */ diff --git a/bsp/renesas/ra2l1-cpk/ra_gen/vector_data.h b/bsp/renesas/ra2l1-cpk/ra_gen/vector_data.h index ab18b96c480..5d9b696e2e6 100644 --- a/bsp/renesas/ra2l1-cpk/ra_gen/vector_data.h +++ b/bsp/renesas/ra2l1-cpk/ra_gen/vector_data.h @@ -3,18 +3,15 @@ #define VECTOR_DATA_H /* Number of interrupts allocated */ #ifndef VECTOR_DATA_IRQ_COUNT - #define VECTOR_DATA_IRQ_COUNT (5) + #define VECTOR_DATA_IRQ_COUNT (4) #endif /* ISR prototypes */ - void r_icu_isr(void); void sci_uart_rxi_isr(void); void sci_uart_txi_isr(void); void sci_uart_tei_isr(void); void sci_uart_eri_isr(void); /* Vector table allocations */ - #define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type) 3) /* ICU IRQ3 (External pin interrupt 3) */ - #define ICU_IRQ3_IRQn ((IRQn_Type) 3) /* ICU IRQ3 (External pin interrupt 3) */ #define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type) 4) /* SCI9 RXI (Received data full) */ #define SCI9_RXI_IRQn ((IRQn_Type) 4) /* SCI9 RXI (Received data full) */ #define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type) 5) /* SCI9 TXI (Transmit data empty) */ diff --git a/bsp/renesas/ra4m2-eco/.config b/bsp/renesas/ra4m2-eco/.config index d74a535eee2..d2ac4f53986 100644 --- a/bsp/renesas/ra4m2-eco/.config +++ b/bsp/renesas/ra4m2-eco/.config @@ -160,13 +160,7 @@ CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_SPI_BITOPS is not set -# CONFIG_RT_USING_QSPI is not set -CONFIG_RT_USING_SPI_MSD=y -# CONFIG_RT_USING_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -1081,6 +1075,7 @@ CONFIG_SOC_FAMILY_RENESAS=y # CONFIG_SOC_SERIES_R7FA6M5 is not set CONFIG_SOC_SERIES_R7FA4M2=y # CONFIG_SOC_SERIES_R7FA8M85 is not set +# CONFIG_SOC_SERIES_R9A07G0 is not set # # Hardware Drivers Config @@ -1090,6 +1085,7 @@ CONFIG_SOC_R7FA4M2AD=y # # Onboard Peripheral Drivers # +# CONFIG_BSP_USING_FS is not set # # On-chip Peripheral Drivers @@ -1114,13 +1110,7 @@ CONFIG_BSP_UART4_RX_BUFSIZE=256 CONFIG_BSP_UART4_TX_BUFSIZE=0 # CONFIG_BSP_USING_UART9 is not set # CONFIG_BSP_USING_SPI is not set -CONFIG_BSP_USING_SCI_SPI=y -# CONFIG_BSP_USING_SCI_SPI0 is not set -# CONFIG_BSP_USING_SCI_SPI1 is not set -# CONFIG_BSP_USING_SCI_SPI2 is not set -# CONFIG_BSP_USING_SCI_SPI3 is not set -# CONFIG_BSP_USING_SCI_SPI4 is not set -CONFIG_BSP_USING_SCI_SPI9=y +# CONFIG_BSP_USING_SCI is not set # # Board extended module Drivers diff --git a/bsp/renesas/ra4m2-eco/.secure_azone b/bsp/renesas/ra4m2-eco/.secure_azone index f0b4ed884d2..b27471091c3 100644 --- a/bsp/renesas/ra4m2-eco/.secure_azone +++ b/bsp/renesas/ra4m2-eco/.secure_azone @@ -22,7 +22,6 @@ - @@ -32,10 +31,6 @@ - - - - diff --git a/bsp/renesas/ra4m2-eco/.secure_xml b/bsp/renesas/ra4m2-eco/.secure_xml index 31702d3286b..4fa57c9f87e 100644 --- a/bsp/renesas/ra4m2-eco/.secure_xml +++ b/bsp/renesas/ra4m2-eco/.secure_xml @@ -9,7 +9,7 @@ @@ -115,9 +127,7 @@ - - diff --git a/bsp/renesas/ra4m2-eco/configuration.xml b/bsp/renesas/ra4m2-eco/configuration.xml index b58c8d40d95..d8bb2067999 100644 --- a/bsp/renesas/ra4m2-eco/configuration.xml +++ b/bsp/renesas/ra4m2-eco/configuration.xml @@ -9,7 +9,7 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/renesas/ra8m1-ek/rasc_version.txt b/bsp/renesas/ra8m1-ek/rasc_version.txt deleted file mode 100644 index 03a436fda08..00000000000 --- a/bsp/renesas/ra8m1-ek/rasc_version.txt +++ /dev/null @@ -1,3 +0,0 @@ -# RASC version and installation file -5.1.0 -E:\mcu_sw\Renesas\RA\sc_v2023-10_fsp_v5.1.0\eclipse\rasc.exe diff --git a/bsp/renesas/rzt2m_rsk/.api_xml b/bsp/renesas/rzt2m_rsk/.api_xml new file mode 100644 index 00000000000..fc9bf0b30e4 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/.api_xml @@ -0,0 +1,2 @@ + + diff --git a/bsp/renesas/rzt2m_rsk/.config b/bsp/renesas/rzt2m_rsk/.config new file mode 100644 index 00000000000..cc8f38aa0e8 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/.config @@ -0,0 +1,1095 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=512 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50100 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# CONFIG_RT_USING_CACHE is not set +CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_R=y +CONFIG_ARCH_ARM_CORTEX_R52=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# +CONFIG_SOC_FAMILY_RENESAS=y +# CONFIG_SOC_SERIES_R7FA6M3 is not set +# CONFIG_SOC_SERIES_R7FA6M4 is not set +# CONFIG_SOC_SERIES_R7FA2L1 is not set +# CONFIG_SOC_SERIES_R7FA6M5 is not set +# CONFIG_SOC_SERIES_R7FA4M2 is not set +# CONFIG_SOC_SERIES_R7FA8M85 is not set +CONFIG_SOC_SERIES_R9A07G0=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_R9A07G084=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_ONCHIP_FLASH is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_ADC is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_UART0_RX_USING_DMA is not set +# CONFIG_BSP_UART0_TX_USING_DMA is not set +CONFIG_BSP_UART0_RX_BUFSIZE=256 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +# CONFIG_BSP_USING_HW_I2C is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_SCI is not set + +# +# Board extended module Drivers +# +# CONFIG_BSP_USING_RW007 is not set diff --git a/bsp/renesas/rzt2m_rsk/.secure_azone b/bsp/renesas/rzt2m_rsk/.secure_azone new file mode 100644 index 00000000000..9d12b29da62 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/.secure_azone @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/bsp/renesas/rzt2m_rsk/.secure_xml b/bsp/renesas/rzt2m_rsk/.secure_xml new file mode 100644 index 00000000000..c38d3c2469f --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/.secure_xml @@ -0,0 +1,201 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/renesas/rzt2m_rsk/.settings/standalone.prefs b/bsp/renesas/rzt2m_rsk/.settings/standalone.prefs new file mode 100644 index 00000000000..de81a8444d1 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/.settings/standalone.prefs @@ -0,0 +1,26 @@ +#Mon Apr 08 13:09:11 CST 2024 +com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzt2m\#\#device\#\#R9A07G075M24GBG\#\#2.0.0/all= +com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#Core\#\#\#\#5.7.0+renesas.2.fsp.2.0.0/all=1441545198,rzt/arm/CMSIS_5/LICENSE.txt|4247764709,rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h|1135074086,rzt/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h|510668081,rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h|4245531541,rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h|1887099957,rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h|3334069041,rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#2.0.0/all=2125590488,rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|2342355920,rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|3551460177,rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c|1161373106,rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c|3243637314,rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|4182329316,rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|4105817883,rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G075.h|1374413851,rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G074.h|1310386533,rzt/fsp/src/bsp/mcu/all/bsp_io.h|2629912170,rzt/fsp/src/bsp/mcu/all/bsp_cache.h|1033616941,rzt/fsp/src/bsp/mcu/all/bsp_register_protection.h|1572168446,rzt/fsp/src/bsp/mcu/all/bsp_io.c|3477977344,rzt/fsp/src/bsp/mcu/all/bsp_common.h|1877066376,rzt/fsp/src/bsp/mcu/all/bsp_reset.h|196026331,rzt/fsp/src/bsp/mcu/all/bsp_module_stop.h|4193244082,rzt/fsp/src/bsp/mcu/all/bsp_irq.h|2136575248,rzt/fsp/src/bsp/mcu/all/bsp_tfu.h|331468717,rzt/fsp/src/bsp/mcu/all/bsp_delay.c|526389185,rzt/fsp/src/bsp/mcu/all/bsp_compiler_support.h|3148546749,rzt/fsp/src/bsp/mcu/all/bsp_clocks.h|3667757780,rzt/fsp/src/bsp/mcu/all/bsp_common.c|743638166,rzt/fsp/src/bsp/mcu/all/bsp_clocks.c|1289851302,rzt/fsp/src/bsp/mcu/all/bsp_irq.c|358242822,rzt/fsp/src/bsp/mcu/all/bsp_sbrk.c|2321472163,rzt/fsp/src/bsp/mcu/all/bsp_cache.c|225356254,rzt/fsp/src/bsp/mcu/all/bsp_exceptions.h|2518644892,rzt/fsp/src/bsp/mcu/all/bsp_register_protection.c|1694677016,rzt/fsp/src/bsp/mcu/all/bsp_reset.c|2238656401,rzt/fsp/src/bsp/mcu/all/bsp_mcu_api.h|660154216,rzt/fsp/src/bsp/mcu/all/bsp_semaphore.h|1611830052,rzt/fsp/src/bsp/mcu/all/bsp_delay.h|580264793,rzt/fsp/src/bsp/mcu/all/bsp_semaphore.c|2060190483,rzt/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h|1543064539,rzt/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h|3717942516,rzt/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c|3396795463,rzt/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c|2195931215,rzt/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c|3179784258,rzt/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h|3060862852,rzt/fsp/inc/fsp_features.h|2432215399,rzt/fsp/inc/fsp_version.h|3571247719,rzt/fsp/inc/fsp_common_api.h|3347087544,rzt/fsp/inc/instances/r_ioport.h|1765016794,rzt/fsp/inc/api/bsp_api.h|250199021,rzt/fsp/inc/api/r_ioport_api.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzt2m\#\#fsp\#\#\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Projects\#\#all\#\#baremetal_blinky\#\#\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.project.standalone.projectgenerationoptions/isCpp=false +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#all\#\#Memory\#\#\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#all\#\#Memory\#\#\#\#2.0.0/all= +com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.1915235820=false +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzt2m\#\#device\#\#\#\#2.0.0/all=3243637314,rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h +com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp_xspi0_boot.icf +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzt2m_rsk\#\#xspi0_x1_boot\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzt2m\#\#device\#\#R9A07G075M24GBG\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator +com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#Core\#\#\#\#5.7.0+renesas.2.fsp.2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzt2m\#\#fsp\#\#\#\#2.0.0/all=776928720,rzt/fsp/src/bsp/mcu/rzt2m/bsp_loader_param.c|837767265,rzt/fsp/src/bsp/mcu/rzt2m/bsp_feature.h|2235589357,rzt/fsp/src/bsp/mcu/rzt2m/bsp_elc.h|999934569,rzt/fsp/src/bsp/mcu/rzt2m/bsp_irq_sense.c|3480910282,rzt/fsp/src/bsp/mcu/rzt2m/bsp_override.h|3746719614,rzt/fsp/src/bsp/mcu/rzt2m/bsp_mcu_info.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#2.0.0/all=2921827146,rzt/fsp/src/r_sci_uart/r_sci_uart.c|4093801030,rzt/fsp/inc/instances/r_sci_uart.h|1119704027,rzt/fsp/inc/api/r_uart_api.h|3586794436,rzt/fsp/inc/api/r_transfer_api.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzt2m_rsk\#\#xspi0_x1_boot\#\#2.0.0/all=2087307037,script/fsp_xspi0_boot.icf|4175174005,rzt/board/rzt2m_rsk/board_leds.c|2320060512,rzt/board/rzt2m_rsk/board_init.c|1194250187,rzt/board/rzt2m_rsk/board.h|1055392802,rzt/board/rzt2m_rsk/board_ethernet_phy.h|2914887204,rzt/board/rzt2m_rsk/board_leds.h|705179139,rzt/board/rzt2m_rsk/board_init.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzt2m\#\#device\#\#\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Projects\#\#all\#\#baremetal_blinky\#\#\#\#2.0.0/all= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#2.0.0/all=1551356638,rzt/fsp/src/r_ioport/r_ioport.c|3347087544,rzt/fsp/inc/instances/r_ioport.h|250199021,rzt/fsp/inc/api/r_ioport_api.h diff --git a/bsp/renesas/rzt2m_rsk/Kconfig b/bsp/renesas/rzt2m_rsk/Kconfig new file mode 100644 index 00000000000..ec50fa3d63e --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/Kconfig @@ -0,0 +1,29 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +# you can change the RTT_ROOT default "rt-thread" +# example : default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config ENV_DIR + string + option env="ENV_ROOT" + default "/" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "$BSP_DIR/board/Kconfig" diff --git a/bsp/renesas/rzt2m_rsk/README.md b/bsp/renesas/rzt2m_rsk/README.md new file mode 100644 index 00000000000..81c85e4dce4 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/README.md @@ -0,0 +1,166 @@ +# Renesas RSK-RZT2M Development Board BSP Guide + +**English** | [**中文**](./README_zh.md) + +## Introduction + +This document provides the Board Support Package (BSP) guide for the Renesas RSK-RZT2M development board. By reading the quick start section, developers can quickly get started with this BSP and run RT-Thread on the development board. + +The main contents are as follows: + +- Board introduction +- BSP quick start guide + +## Board Introduction + +The RSK-RZT2M MCU evaluation board, based on the Renesas RZ/T2M development, is designed to assist users in evaluating the features of the RA6M4 MCU group and developing embedded system applications through flexible configuration of software packages and IDEs. + +The front appearance of the development board is as follows: + +![](figures/board.png) + +The commonly used **on-board resources** of this development board are as follows: + +- MCU: R9A07G075M24GBG, with a maximum operating frequency of 800MHz, dual Arm Cortex®-R52 cores, tightly coupled memory 576KB (with ECC), internal RAM 2 MB (with ECC) +- Debug interface: On-board J-Link interface +- Expansion interface: Two PMOD connectors + +**More detailed information and tools** + +## Peripheral Support + +The current support status of peripherals in this BSP is as follows: + +| **On-chip Peripheral** | **Support Status** | **Remarks** | +| :--------------------- | :----------------- | :----------------------------------- | +| UART | Supported | UART0 is the default log output port | +| GPIO | Supported | | +| HWIMER | Supported | | +| I2C | Not supported | | +| WDT | Not supported | | +| RTC | Not supported | | +| ADC | Not supported | | +| DAC | Not supported | | +| SPI | Not supported | | +| FLASH | Not supported | | +| PWM | Not supported | | +| CAN | Not supported | | +| ETH | Not supported | | +| More to come... | | | + +## Usage Guide + +The usage guide is divided into the following two sections: + +- Quick Start + + This section is prepared for beginners who are new to RT-Thread. Follow simple steps to run the RT-Thread operating system on this development board and see experimental results. + +- Advanced Usage + + This section is prepared for developers who need to utilize more development board resources on the RT-Thread operating system. By using the ENV tool to configure the BSP, more on-board resources can be enabled to achieve more advanced functionalities. + +### Quick Start + +Currently, this BSP only provides an IAR project. Below is an example of how to get the system up and running using [IAR Embedded Workbench for Arm](https://www.iar.com/products/architectures/arm/iar-embedded-workbench-for-arm/) development environment. + +**Hardware Connection** + +Connect the development board to the PC using a USB data cable and use the J-link interface for downloading and debugging programs. + +**Compilation and Download** + +- Navigate to the bsp directory, open ENV, and use the command `scons --target=iar` to generate an IAR project. +- Compilation: Double-click the project.eww file to open the IAR project and compile the program. +- Debugging: Click `Project->Download and Debug` on the top-left navigation bar of IAR to download and start debugging. + +**Viewing Execution Results** + +After successfully downloading the program, the system will automatically run and print system information. + +Connect the corresponding serial port of the development board to the PC, open the terminal tool, and select the corresponding serial port (115200-8-1-N). After resetting the device, you can see the output information from RT-Thread. Enter the help command to view the supported commands in the system. + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Mar 14 2024 18:26:01 + 2006 - 2024 Copyright by RT-Thread team + +Hello RT-Thread! +================================================== +This is a iar project which mode is ram execution! +================================================== +msh >help +RT-Thread shell commands: +clear - clear the terminal screen +version - show RT-Thread version information +list - list objects +backtrace - print backtrace of a thread +help - RT-Thread shell help +ps - List threads in the system +free - Show the memory usage in the system +pin - pin [option] + +msh > +``` + +**Application Entry Function** + +The entry function of the application layer is in **src\hal_entry.c** under `void hal_entry(void)`. User-written source files can be directly placed in the src directory. + +```c +void hal_entry(void) +{ + rt_kprintf("\nHello RT-Thread!\n"); + rt_kprintf("==================================================\n"); + rt_kprintf("This is a iar project which mode is ram execution!\n"); + rt_kprintf("==================================================\n"); + + while (1) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} +``` + +### Advanced Usage + +**Documentation and Resources** + +- [Development Board Official Page](https://www.renesas.cn/cn/zh/products/microcontrollers-microprocessors/rz-mpus/rzt2m-high-performance-multi-function-mpu-realizing-high-speed-processing-and-high-precision-control#overview) +- [Development Board Datasheet](https://www.renesas.cn/cn/zh/document/dst/rzt2m-group-datasheet?r=1574901) +- [Development Board Hardware Manual](https://www.renesas.cn/cn/zh/document/mah/rzt2m-group-users-manual-hardware?r=1574901) +- [RZ/T2M Easy Download Guide](https://www.renesas.cn/cn/zh/document/gde/rzt2m-easy-download-guide?r=1574901) +- [Renesas RZ/T2M Group](https://www.renesas.cn/cn/zh/document/fly/renesas-rzt2m-group?r=1574901) + +**FSP Configuration** + +To modify Renesas BSP peripheral configurations or add new peripheral ports, the Renesas [Flexible Software Package (FSP)](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) configuration tool is required. Please follow the steps below for configuration. For any configuration issues, feel free to ask in the [RT-Thread Community Forum](https://club.rt-thread.org/). + +1. [Download Flexible Software Package (FSP) | Renesas](https://github.com/renesas/rzn-fsp/releases/download/v1.3.0/setup_rznfsp_v1_3_0_rzsc_v2023-07.exe), please use FSP version 1.3.0. + +2. Refer to the document [How to import the board support package](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191) on how to add the "RSK-RZT2M board support package" to FSP. +3. Refer to the document: [RA Series Using FSP to Configure Peripheral Drivers](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动). + +**ENV Configuration** + +- How to use the ENV tool: [RT-Thread env tool user manual](https://www.rt-thread.org/document/site/#/development-tools/env/env) + +This BSP only enables the UART1 function by default. If you need to use more advanced features such as components, software packages, etc., you need to configure it using the ENV tool. + +The steps are as follows: +1. Open the env tool under bsp. +2. Enter the `menuconfig` command to configure the project, save and exit after configuration. +3. Enter the `pkgs --update` command to update the software packages. +4. Enter the `scons --target=iar` command to regenerate the project. + +## Contact Information + +If you have any ideas or suggestions during use, we recommend contacting us through the [RT-Thread Community Forum](https://club.rt-thread.org/). + +## Code Contribution + +If you are interested in RSK-RZT2M and have some interesting projects to share with everyone, feel free to contribute code to us. You can refer to [How to Contribute to RT-Thread Code](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github). \ No newline at end of file diff --git a/bsp/renesas/rzt2m_rsk/README_zh.md b/bsp/renesas/rzt2m_rsk/README_zh.md new file mode 100644 index 00000000000..6e327fa22e1 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/README_zh.md @@ -0,0 +1,167 @@ +# 瑞萨 RSK-RZT2M 开发板 BSP 说明 + +**中文** | [**English**](./README.md) + +## 简介 + +本文档为瑞萨 RSK-RZT2M 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +主要内容如下： + +- 开发板介绍 +- BSP 快速上手指南 + +## 开发板介绍 + +基于瑞萨 RZ/T2M 开发的 RSK-RZT2M MCU 评估板，通过灵活配置软件包和 IDE，对嵌入系统应用程序进行开发。 + +开发板正面外观如下图： + +![](figures/board.png) + +该开发板常用 **板载资源** 如下： + +- MPU：R9A07G075M24GBG，最大工作频率 800MHz，双Arm Cortex®-R52 内核，紧密耦合内存 576KB（带 ECC），内部 RAM 2 MB（带 ECC） +- 调试接口：板载 J-Link 接口 +- 扩展接口：两个 PMOD 连接器 + +**更多详细资料及工具** + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :----------------- | :----------------- | :------------- | +| UART | 支持 | UART0 为默认日志输出端口 | +| GPIO | 支持 | | +| HWIMER | 支持 | | +| IIC | 不支持 | | +| WDT | 不支持 | | +| RTC | 不支持 | | +| ADC | 不支持 | | +| DAC | 不支持 | | +| SPI | 不支持 | | +| FLASH | 不支持 | | +| PWM | 不支持 | | +| CAN | 不支持 | | +| ETH | 不支持 | | +| 持续更新中... | | | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + +### 快速上手 + +本 BSP 目前仅提供 IAR 工程。下面以 [IAR Embedded Workbench for Arm](https://www.iar.com/products/architectures/arm/iar-embedded-workbench-for-arm/) 开发环境为例，介绍如何将系统运行起来。 + +**硬件连接** + +使用 USB 数据线连接开发板到 PC，使用 J-link 接口下载和 DEBUG 程序。 + +**编译下载** + +- 进入 bsp 目录下，打开 ENV 使用命令 `scons --target=iar` 生成 IAR工程。 +- 编译：双击 project.eww 文件，打开 IAR 工程，编译程序。 +- 调试：IAR 左上方导航栏点击 `Project->Download and Debug`下载并启动调试。 + + + +**查看运行结果** + +下载程序成功之后，系统会自动运行并打印系统信息。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。 + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Mar 14 2024 18:26:01 + 2006 - 2024 Copyright by RT-Thread team + +Hello RT-Thread! +================================================== +This is a iar project which mode is ram execution! +================================================== +msh >help +RT-Thread shell commands: +clear - clear the terminal screen +version - show RT-Thread version information +list - list objects +backtrace - print backtrace of a thread +help - RT-Thread shell help +ps - List threads in the system +free - Show the memory usage in the system +pin - pin [option] + +msh > +``` + +**应用入口函数** + +应用层的入口函数在 **src\hal_entry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。 + +```c +void hal_entry(void) +{ + rt_kprintf("\nHello RT-Thread!\n"); + rt_kprintf("==================================================\n"); + rt_kprintf("This is a iar project which mode is ram execution!\n"); + rt_kprintf("==================================================\n"); + + while (1) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} +``` + +### 进阶使用 + +**资料及文档** + +- [开发板官网主页](https://www.renesas.cn/cn/zh/products/microcontrollers-microprocessors/rz-mpus/rzt2m-high-performance-multi-function-mpu-realizing-high-speed-processing-and-high-precision-control#overview) +- [开发板数据手册](https://www.renesas.cn/cn/zh/document/dst/rzt2m-group-datasheet?r=1574901) +- [开发板硬件手册](https://www.renesas.cn/cn/zh/document/mah/rzt2m-group-users-manual-hardware?r=1574901) +- [RZ/T2M Easy Download Guide](https://www.renesas.cn/cn/zh/document/gde/rzt2m-easy-download-guide?r=1574901) +- [Renesas RZ/T2M Group](https://www.renesas.cn/cn/zh/document/fly/renesas-rzt2m-group?r=1574901) + +**FSP 配置** + +需要修改瑞萨的 BSP 外设配置或添加新的外设端口，需要用到瑞萨的 [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到[RT-Thread 社区论坛](https://club.rt-thread.org/)中提问。 + +1. [下载灵活配置软件包 (FSP) | Renesas](https://github.com/renesas/rzn-fsp/releases/download/v1.3.0/setup_rznfsp_v1_3_0_rzsc_v2023-07.exe)，请使用 FSP 1.3.0 版本 +2. 如何将 **”RSK-RZT2M板级支持包“**添加到 FSP 中，请参考文档[如何导入板级支持包](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191) +3. 请参考文档：[RA系列使用FSP配置外设驱动](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动)。 + +**ENV 配置** + +- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env) + +此 BSP 默认只开启了 UART1 的功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。 + +步骤如下： +1. 在 bsp 下打开 env 工具。 +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 +3. 输入`pkgs --update`命令更新软件包。 +4. 输入`scons --target=iar` 命令重新生成工程。 + +## 联系人信息 + +在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/) + +## 贡献代码 + +如果您对 RSK-RZT2M 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。 diff --git a/bsp/renesas/rzt2m_rsk/SConscript b/bsp/renesas/rzt2m_rsk/SConscript new file mode 100644 index 00000000000..889ba12c85f --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/SConscript @@ -0,0 +1,28 @@ +# for module compiling +import os +Import('RTT_ROOT') +Import('rtconfig') +from building import * +from gcc import * + +cwd = GetCurrentDir() +src = [] +CPPPATH = [cwd] +group = [] +list = os.listdir(cwd) + +if rtconfig.PLATFORM in ['iccarm']: + group = DefineGroup('', src, depend = [''], CPPPATH = CPPPATH) +elif rtconfig.PLATFORM in GetGCCLikePLATFORM(): + if GetOption('target') != 'mdk5': + CPPPATH = [cwd] + src = Glob('./src/*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + group = group + SConscript(os.path.join(d, 'SConscript')) + +Return('group') diff --git a/bsp/renesas/rzt2m_rsk/SConstruct b/bsp/renesas/rzt2m_rsk/SConstruct new file mode 100644 index 00000000000..a66fe568f37 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/SConstruct @@ -0,0 +1,66 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +rtconfig.BSP_LIBRARY_TYPE = None + +def startup_check(): + import subprocess + startup_check_path = os.getcwd() + "/../tools/startup_check.py" + + if os.path.exists(startup_check_path): + try: + subprocess.call(["python", startup_check_path]) + except: + subprocess.call(["python3", startup_check_path]) + +RegisterPreBuildingAction(startup_check) + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/renesas/rzt2m_rsk/board/Kconfig b/bsp/renesas/rzt2m_rsk/board/Kconfig new file mode 100644 index 00000000000..e5f52ba54c3 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/board/Kconfig @@ -0,0 +1,502 @@ +menu "Hardware Drivers Config" + + config SOC_R9A07G084 + bool + select SOC_SERIES_R9A07G0 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + + menu "Onboard Peripheral Drivers" + + endmenu + + menu "On-chip Peripheral Drivers" + + source "../libraries/HAL_Drivers/Kconfig" + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + endif + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + select RT_USING_SERIAL_V2 + if BSP_USING_UART + + menuconfig BSP_USING_UART0 + bool "Enable UART0" + default n + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + menuconfig BSP_USING_HW_I2C + bool "Enable hardware I2C BUS" + default n + if BSP_USING_HW_I2C + config BSP_USING_HW_I2C0 + bool "Enable Hardware I2C0 BUS" + default n + config BSP_USING_HW_I2C1 + bool "Enable Hardware I2C1 BUS" + default n + endif + + menuconfig BSP_USING_SOFT_I2C + bool "Enable software I2C bus" + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + default n + if BSP_USING_SOFT_I2C + config BSP_USING_SOFT_I2C + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 Bus (software simulation)" + default n + if BSP_USING_I2C1 + comment "Please refer to the 'bsp_io.h' file to configure the pins" + config BSP_I2C1_SCL_PIN + hex "i2c1 scl pin number (hex)" + range 0x0000 0xFFFF + default 0x0B03 + config BSP_I2C1_SDA_PIN + hex "i2c1 sda pin number (hex)" + range 0x0000 0xFFFF + default 0x050E + endif + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0 BUS" + default n + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM0 + bool "Enable TIM0" + default n + config BSP_USING_TIM1 + bool "Enable TIM1" + default n + endif + + menuconfig BSP_USING_SCI + bool "Enable SCI Controller" + default n + config BSP_USING_SCIn_SPI + bool + depends on BSP_USING_SCI + select RT_USING_SPI + default n + + config BSP_USING_SCIn_I2C + bool + depends on BSP_USING_SCI + select RT_USING_I2C + default n + + config BSP_USING_SCIn_UART + bool + depends on BSP_USING_SCI + select RT_USING_SERIAL + select RT_USING_SERIAL_V2 + default n + + if BSP_USING_SCI + config BSP_USING_SCI0 + bool "Enable SCI0" + default n + if BSP_USING_SCI0 + choice + prompt "choice sci mode" + default BSP_USING_SCI0_SPI + config BSP_USING_SCI0_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI0_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI0_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI0_UART + config BSP_SCI0_UART_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI0_UART_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI1 + bool "Enable SCI1" + default n + if BSP_USING_SCI1 + choice + prompt "choice sci mode" + default BSP_USING_SCI1_SPI + config BSP_USING_SCI1_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI1_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI1_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI1_UART + config BSP_SCI1_UART_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI1_UART_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI2 + bool "Enable SCI2" + default n + if BSP_USING_SCI2 + choice + prompt "choice sci mode" + default BSP_USING_SCI2_SPI + config BSP_USING_SCI2_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI2_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI2_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI2_UART + config BSP_SCI2_UART_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI2_UART_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI3 + bool "Enable SCI3" + default n + if BSP_USING_SCI3 + choice + prompt "choice sci mode" + default BSP_USING_SCI3_SPI + config BSP_USING_SCI3_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI3_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI3_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI3_UART + config BSP_SCI3_UART_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI3_UART_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI4 + bool "Enable SCI4" + default n + if BSP_USING_SCI4 + choice + prompt "choice sci mode" + default BSP_USING_SCI4_SPI + config BSP_USING_SCI4_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI4_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI4_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI4_UART + config BSP_SCI4_UART_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI4_UART_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI5 + bool "Enable SCI5" + default n + if BSP_USING_SCI5 + choice + prompt "choice sci mode" + default BSP_USING_SCI5_SPI + config BSP_USING_SCI5_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI5_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI5_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI5_UART + config BSP_SCI5_UART_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI5_UART_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI6 + bool "Enable SCI6" + default n + if BSP_USING_SCI6 + choice + prompt "choice sci mode" + default BSP_USING_SCI6_SPI + config BSP_USING_SCI6_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI6_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI6_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI6_UART + config BSP_SCI6_UART_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI6_UART_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI7 + bool "Enable SCI7" + default n + if BSP_USING_SCI7 + choice + prompt "choice sci mode" + default BSP_USING_SCI7_SPI + config BSP_USING_SCI7_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI7_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI7_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI7_UART + config BSP_SCI7_UART_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI7_UART_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI8 + bool "Enable SCI8" + default n + if BSP_USING_SCI8 + choice + prompt "choice sci mode" + default BSP_USING_SCI8_SPI + config BSP_USING_SCI8_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI8_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI8_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI8_UART + config BSP_SCI8_UART_RX_BUFSIZE + int "Set UART8 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI8_UART_TX_BUFSIZE + int "Set UART8 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI9 + bool "Enable SCI9" + default n + if BSP_USING_SCI9 + choice + prompt "choice sci mode" + default BSP_USING_SCI9_SPI + config BSP_USING_SCI9_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI9_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI9_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI9_UART + config BSP_SCI9_UART_RX_BUFSIZE + int "Set UART9 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI9_UART_TX_BUFSIZE + int "Set UART9 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + endif + + endmenu + + menu "Board extended module Drivers" + + menuconfig BSP_USING_RW007 + bool "Enable RW007" + default n + select PKG_USING_RW007 + select BSP_USING_SPI + select BSP_USING_SPI2 + select RT_USING_MEMPOOL + select RW007_NOT_USE_EXAMPLE_DRIVERS + + if BSP_USING_RW007 + config RA_RW007_SPI_BUS_NAME + string "RW007 BUS NAME" + default "spi2" + + config RA_RW007_CS_PIN + hex "(HEX)CS pin index" + default 0x1207 + + config RA_RW007_BOOT0_PIN + hex "(HEX)BOOT0 pin index (same as spi clk pin)" + default 0x1204 + + config RA_RW007_BOOT1_PIN + hex "(HEX)BOOT1 pin index (same as spi cs pin)" + default 0x1207 + + config RA_RW007_INT_BUSY_PIN + hex "(HEX)INT/BUSY pin index" + default 0x1102 + + config RA_RW007_RST_PIN + hex "(HEX)RESET pin index" + default 0x1706 + endif + endmenu +endmenu diff --git a/bsp/renesas/rzt2m_rsk/board/SConscript b/bsp/renesas/rzt2m_rsk/board/SConscript new file mode 100644 index 00000000000..a27ea8e470c --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/board/SConscript @@ -0,0 +1,16 @@ +import os +from building import * + +objs = [] +cwd = GetCurrentDir() +list = os.listdir(cwd) +CPPPATH = [cwd] +src = Glob('*.c') + +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/renesas/rzt2m_rsk/board/board.h b/bsp/renesas/rzt2m_rsk/board/board.h new file mode 100644 index 00000000000..786f0abe674 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/board/board.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-11 Wangyuqiang first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#define RZ_SRAM_SIZE 1536 /* The SRAM size of the chip needs to be modified */ +#define RZ_SRAM_END (0x10000000 + RZ_SRAM_SIZE * 1024) + +#ifdef __ARMCC_VERSION +extern int Image$$RAM_END$$ZI$$Base; +#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base) +#else +#define HEAP_BEGIN (0x10000000) +#endif + +#define HEAP_END RZ_SRAM_END + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define MAX_HANDLERS (512) +#define GIC_IRQ_START 0 +#define GIC_ACK_INTID_MASK (0x000003FFU) +/* number of interrupts on board */ +#define ARM_GIC_NR_IRQS (448) +/* only one GIC available */ +#define ARM_GIC_MAX_NR 1 +/* end defined */ + +#define GICV3_DISTRIBUTOR_BASE_ADDR (0x100000) + +/* the basic constants and interfaces needed by gic */ +rt_inline rt_uint32_t platform_get_gic_dist_base(void) +{ + rt_uint32_t gic_base; + + __get_cp(15, 1, gic_base, 15, 3, 0); + return gic_base + GICV3_DISTRIBUTOR_BASE_ADDR; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/renesas/rzt2m_rsk/board/ports/SConscript b/bsp/renesas/rzt2m_rsk/board/ports/SConscript new file mode 100644 index 00000000000..e8ac9ae59e6 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/board/ports/SConscript @@ -0,0 +1,16 @@ +import os +from building import * + +objs = [] +src = Glob('*.c') +cwd = GetCurrentDir() +CPPPATH = [cwd] + +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/renesas/rzt2m_rsk/board/ports/gpio_cfg.h b/bsp/renesas/rzt2m_rsk/board/ports/gpio_cfg.h new file mode 100644 index 00000000000..d179d4ab6ca --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/board/ports/gpio_cfg.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-11 Wangyuqiang first version + */ + +/* Number of IRQ channels on the device */ +#define RA_IRQ_MAX 16 + +/* PIN to IRQx table */ +#define PIN2IRQX_TABLE \ +{ \ + switch (pin) \ + { \ + case BSP_IO_PORT_00_PIN_1: \ + case BSP_IO_PORT_09_PIN_2: \ + case BSP_IO_PORT_18_PIN_3: \ + return 0; \ + case BSP_IO_PORT_00_PIN_3: \ + case BSP_IO_PORT_07_PIN_4: \ + case BSP_IO_PORT_18_PIN_4: \ + return 1; \ + case BSP_IO_PORT_01_PIN_2: \ + return 2; \ + case BSP_IO_PORT_01_PIN_4: \ + return 3; \ + case BSP_IO_PORT_02_PIN_0: \ + case BSP_IO_PORT_22_PIN_2: \ + return 4; \ + case BSP_IO_PORT_03_PIN_5: \ + case BSP_IO_PORT_13_PIN_2: \ + return 5; \ + case BSP_IO_PORT_14_PIN_2: \ + case BSP_IO_PORT_21_PIN_5: \ + return 6; \ + case BSP_IO_PORT_16_PIN_3: \ + return 7; \ + case BSP_IO_PORT_03_PIN_6: \ + case BSP_IO_PORT_16_PIN_6: \ + return 8; \ + case BSP_IO_PORT_03_PIN_7: \ + case BSP_IO_PORT_21_PIN_6: \ + return 9; \ + case BSP_IO_PORT_04_PIN_4: \ + case BSP_IO_PORT_18_PIN_1: \ + case BSP_IO_PORT_21_PIN_7: \ + return 10; \ + case BSP_IO_PORT_10_PIN_4: \ + case BSP_IO_PORT_18_PIN_6: \ + return 11; \ + case BSP_IO_PORT_05_PIN_0: \ + case BSP_IO_PORT_05_PIN_4: \ + case BSP_IO_PORT_05_PIN_6: \ + return 12; \ + case BSP_IO_PORT_00_PIN_4: \ + case BSP_IO_PORT_00_PIN_7: \ + case BSP_IO_PORT_05_PIN_1: \ + return 13; \ + case BSP_IO_PORT_02_PIN_2: \ + case BSP_IO_PORT_03_PIN_0: \ + case BSP_IO_PORT_05_PIN_2: \ + return 14; \ + case BSP_IO_PORT_02_PIN_3: \ + case BSP_IO_PORT_05_PIN_3: \ + case BSP_IO_PORT_22_PIN_0: \ + return 15; \ + default : \ + return -1; \ + } \ +} diff --git a/bsp/renesas/rzt2m_rsk/board/ports/wifi/SConscript b/bsp/renesas/rzt2m_rsk/board/ports/wifi/SConscript new file mode 100644 index 00000000000..9e73f9555d1 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/board/ports/wifi/SConscript @@ -0,0 +1,22 @@ + +from building import * +import rtconfig + +cwd = GetCurrentDir() + +src = [] + +if GetDepend(['BSP_USING_RW007']): + src += Glob('drv_rw007.c') + +CPPPATH = [cwd] +LOCAL_CFLAGS = '' + +if rtconfig.PLATFORM in ['gcc', 'armclang']: + LOCAL_CFLAGS += ' -std=c99' +elif rtconfig.PLATFORM in ['armcc']: + LOCAL_CFLAGS += ' --c99' + +group = DefineGroup('Drivers', src, depend = [], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS) + +Return('group') diff --git a/bsp/renesas/rzt2m_rsk/board/ports/wifi/drv_rw007.c b/bsp/renesas/rzt2m_rsk/board/ports/wifi/drv_rw007.c new file mode 100644 index 00000000000..6eadff1bf33 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/board/ports/wifi/drv_rw007.c @@ -0,0 +1,65 @@ +#include +#include +#ifdef BSP_USING_RW007 +#include +#include +#include +#include + +extern void spi_wifi_isr(int vector); + +static void rw007_gpio_init(void) +{ + /* Configure IO */ + rt_pin_mode(RA_RW007_RST_PIN, PIN_MODE_OUTPUT); + rt_pin_mode(RA_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN); + + /* Reset rw007 and config mode */ + rt_pin_write(RA_RW007_RST_PIN, PIN_LOW); + rt_thread_delay(rt_tick_from_millisecond(100)); + rt_pin_write(RA_RW007_RST_PIN, PIN_HIGH); + + /* Wait rw007 ready(exit busy stat) */ + while (!rt_pin_read(RA_RW007_INT_BUSY_PIN)) + { + rt_thread_delay(5); + } + + rt_thread_delay(rt_tick_from_millisecond(200)); + rt_pin_mode(RA_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP); +} + +int wifi_spi_device_init(void) +{ + char sn_version[32]; + uint32_t cs_pin = RA_RW007_CS_PIN; + + rw007_gpio_init(); + rt_hw_spi_device_attach(RA_RW007_SPI_BUS_NAME, "wspi", cs_pin); + rt_hw_wifi_init("wspi"); + + rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION); + rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP); + + rw007_sn_get(sn_version); + rt_kprintf("\nrw007 sn: [%s]\n", sn_version); + rw007_version_get(sn_version); + rt_kprintf("rw007 ver: [%s]\n\n", sn_version); + + return 0; +} +INIT_APP_EXPORT(wifi_spi_device_init); + +static void int_wifi_irq(void *p) +{ + ((void)p); + spi_wifi_isr(0); +} + +void spi_wifi_hw_init(void) +{ + rt_pin_attach_irq(RA_RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0); + rt_pin_irq_enable(RA_RW007_INT_BUSY_PIN, RT_TRUE); +} + +#endif /* BSP_USING_RW007 */ diff --git a/bsp/renesas/rzt2m_rsk/buildinfo.ipcf b/bsp/renesas/rzt2m_rsk/buildinfo.ipcf new file mode 100644 index 00000000000..f88fbccfa6e --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/buildinfo.ipcf @@ -0,0 +1,159 @@ + + + + R9A07G075M24_CPU0 + + + $PROJ_DIR$/rzt/arm/CMSIS_5/CMSIS/Core_R/Include + $PROJ_DIR$/rzt/fsp/inc + $PROJ_DIR$/rzt/fsp/inc/api + $PROJ_DIR$/rzt/fsp/inc/instances + $PROJ_DIR$/rzt/fsp/src/bsp/mcu/all/cr + $PROJ_DIR$/rzt_cfg/fsp_cfg + $PROJ_DIR$/rzt_cfg/fsp_cfg/bsp + $PROJ_DIR$/rzt_gen + $PROJ_DIR$/src + $PROJ_DIR$ + + + _RENESAS_RZT_ + _RZT_CORE=CR52_0 + _RZT_ORDINAL=1 + + + $PROJ_DIR$/rzt/arm/CMSIS_5/CMSIS/Core_R/Include + $PROJ_DIR$/rzt/fsp/inc + $PROJ_DIR$/rzt/fsp/inc/api + $PROJ_DIR$/rzt/fsp/inc/instances + $PROJ_DIR$/rzt/fsp/src/bsp/mcu/all/cr + $PROJ_DIR$/rzt_cfg/fsp_cfg + $PROJ_DIR$/rzt_cfg/fsp_cfg/bsp + $PROJ_DIR$/rzt_gen + $PROJ_DIR$/src + $PROJ_DIR$ + + + _RENESAS_RZT_ + _RZT_CORE=CR52_0 + _RZT_ORDINAL=1 + + + true + $PROJ_DIR$/script/fsp_xspi0_boot.icf + + + --config_search "$PROJ_DIR$" + + + system_init + + + + + RASC_EXE_PATH + C:\Renesas\rzt\sc_v2024-01.1_fsp_v2.0.0\eclipse\rasc.exe + + + + + + rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h + rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h + rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h + rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h + rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h + rzt/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h + rzt/arm/CMSIS_5/LICENSE.txt + rzt/board/rzt2m_rsk/board.h + rzt/board/rzt2m_rsk/board_ethernet_phy.h + rzt/board/rzt2m_rsk/board_init.c + rzt/board/rzt2m_rsk/board_init.h + rzt/board/rzt2m_rsk/board_leds.c + rzt/board/rzt2m_rsk/board_leds.h + rzt/fsp/inc/api/bsp_api.h + rzt/fsp/inc/api/r_ioport_api.h + rzt/fsp/inc/api/r_transfer_api.h + rzt/fsp/inc/api/r_uart_api.h + rzt/fsp/inc/fsp_common_api.h + rzt/fsp/inc/fsp_features.h + rzt/fsp/inc/fsp_version.h + rzt/fsp/inc/instances/r_ioport.h + rzt/fsp/inc/instances/r_sci_uart.h + rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G074.h + rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G075.h + rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h + rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h + rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c + rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c + rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c + rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c + rzt/fsp/src/bsp/mcu/all/bsp_cache.c + rzt/fsp/src/bsp/mcu/all/bsp_cache.h + rzt/fsp/src/bsp/mcu/all/bsp_clocks.c + rzt/fsp/src/bsp/mcu/all/bsp_clocks.h + rzt/fsp/src/bsp/mcu/all/bsp_common.c + rzt/fsp/src/bsp/mcu/all/bsp_common.h + rzt/fsp/src/bsp/mcu/all/bsp_compiler_support.h + rzt/fsp/src/bsp/mcu/all/bsp_delay.c + rzt/fsp/src/bsp/mcu/all/bsp_delay.h + rzt/fsp/src/bsp/mcu/all/bsp_exceptions.h + rzt/fsp/src/bsp/mcu/all/bsp_io.c + rzt/fsp/src/bsp/mcu/all/bsp_io.h + rzt/fsp/src/bsp/mcu/all/bsp_irq.c + rzt/fsp/src/bsp/mcu/all/bsp_irq.h + rzt/fsp/src/bsp/mcu/all/bsp_mcu_api.h + rzt/fsp/src/bsp/mcu/all/bsp_module_stop.h + rzt/fsp/src/bsp/mcu/all/bsp_register_protection.c + rzt/fsp/src/bsp/mcu/all/bsp_register_protection.h + rzt/fsp/src/bsp/mcu/all/bsp_reset.c + rzt/fsp/src/bsp/mcu/all/bsp_reset.h + rzt/fsp/src/bsp/mcu/all/bsp_sbrk.c + rzt/fsp/src/bsp/mcu/all/bsp_semaphore.c + rzt/fsp/src/bsp/mcu/all/bsp_semaphore.h + rzt/fsp/src/bsp/mcu/all/bsp_tfu.h + rzt/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c + rzt/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h + rzt/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c + rzt/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h + rzt/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c + rzt/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h + rzt/fsp/src/bsp/mcu/rzt2m/bsp_elc.h + rzt/fsp/src/bsp/mcu/rzt2m/bsp_feature.h + rzt/fsp/src/bsp/mcu/rzt2m/bsp_irq_sense.c + rzt/fsp/src/bsp/mcu/rzt2m/bsp_loader_param.c + rzt/fsp/src/bsp/mcu/rzt2m/bsp_mcu_info.h + rzt/fsp/src/bsp/mcu/rzt2m/bsp_override.h + rzt/fsp/src/r_ioport/r_ioport.c + rzt/fsp/src/r_sci_uart/r_sci_uart.c + rzt/SConscript + + + rzt_cfg/fsp_cfg/bsp/board_cfg.h + rzt_cfg/fsp_cfg/bsp/bsp_cfg.h + rzt_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h + rzt_cfg/fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h + rzt_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h + rzt_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h + rzt_cfg/fsp_cfg/bsp/bsp_memory_cfg.h + rzt_cfg/fsp_cfg/bsp/bsp_pin_cfg.h + rzt_cfg/fsp_cfg/r_ioport_cfg.h + rzt_cfg/fsp_cfg/r_sci_uart_cfg.h + rzt_cfg/SConscript + + + rzt_gen/bsp_clock_cfg.h + rzt_gen/common_data.c + rzt_gen/common_data.h + rzt_gen/hal_data.c + rzt_gen/hal_data.h + rzt_gen/main.c + rzt_gen/pin_data.c + rzt_gen/SConscript + rzt_gen/vector_data.c + rzt_gen/vector_data.h + + + src/hal_entry.c + + + diff --git a/bsp/renesas/rzt2m_rsk/configuration.xml b/bsp/renesas/rzt2m_rsk/configuration.xml new file mode 100644 index 00000000000..518b88259cd --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/configuration.xml @@ -0,0 +1,1390 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Simple application that blinks an LED. No RTOS included. + Renesas.RZT_baremetal_blinky.2.0.0.pack + + + Board Support Package Common Files + Renesas.RZT.2.0.0.pack + + + Memory Config Checking + Renesas.RZT.2.0.0.pack + + + I/O Port + Renesas.RZT.2.0.0.pack + + + RSK+RZT2M Board Support Files (xSPI0 x1 boot mode) + Renesas.RZT_board_rzt2m_rsk.2.0.0.pack + + + Arm CMSIS Version 5 - Core + Arm.CMSIS5.5.7.0+renesas.2.fsp.2.0.0.pack + + + Board support package for R9A07G075M24GBG + Renesas.RZT_mcu_rzt2m.2.0.0.pack + + + Board support package for RZT2M + Renesas.RZT_mcu_rzt2m.2.0.0.pack + + + Board support package for RZT2M - FSP Data + Renesas.RZT_mcu_rzt2m.2.0.0.pack + + + SCI UART + Renesas.RZT.2.0.0.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/renesas/rzt2m_rsk/figures/board.png b/bsp/renesas/rzt2m_rsk/figures/board.png new file mode 100644 index 00000000000..f69e04d4f1f Binary files /dev/null and b/bsp/renesas/rzt2m_rsk/figures/board.png differ diff --git a/bsp/renesas/rzt2m_rsk/memory_regions.icf b/bsp/renesas/rzt2m_rsk/memory_regions.icf new file mode 100644 index 00000000000..fac7609d466 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/memory_regions.icf @@ -0,0 +1,43 @@ + + /* generated memory regions file - do not edit */ + define symbol ATCM_START = 0x00000000; + define symbol ATCM_LENGTH = 0x80000; + define symbol BTCM_START = 0x00100000; + define symbol BTCM_LENGTH = 0x10000; + define symbol SYSTEM_RAM_START = 0x10000000; + define symbol SYSTEM_RAM_LENGTH = 0x200000; + define symbol SYSTEM_RAM_MIRROR_START = 0x30000000; + define symbol SYSTEM_RAM_MIRROR_LENGTH = 0x200000; + define symbol xSPI0_CS0_SPACE_MIRROR_START = 0x40000000; + define symbol xSPI0_CS0_SPACE_MIRROR_LENGTH = 0x4000000; + define symbol xSPI0_CS1_SPACE_MIRROR_START = 0x44000000; + define symbol xSPI0_CS1_SPACE_MIRROR_LENGTH = 0x4000000; + define symbol xSPI1_CS0_SPACE_MIRROR_START = 0x48000000; + define symbol xSPI1_CS0_SPACE_MIRROR_LENGTH = 0x4000000; + define symbol xSPI1_CS1_SPACE_MIRROR_START = 0x4C000000; + define symbol xSPI1_CS1_SPACE_MIRROR_LENGTH = 0x4000000; + define symbol CS0_SPACE_MIRROR_START = 0x50000000; + define symbol CS0_SPACE_MIRROR_LENGTH = 0x4000000; + define symbol CS2_SPACE_MIRROR_START = 0x54000000; + define symbol CS2_SPACE_MIRROR_LENGTH = 0x4000000; + define symbol CS3_SPACE_MIRROR_START = 0x58000000; + define symbol CS3_SPACE_MIRROR_LENGTH = 0x4000000; + define symbol CS5_SPACE_MIRROR_START = 0x5C000000; + define symbol CS5_SPACE_MIRROR_LENGTH = 0x4000000; + define symbol xSPI0_CS0_SPACE_START = 0x60000000; + define symbol xSPI0_CS0_SPACE_LENGTH = 0x4000000; + define symbol xSPI0_CS1_SPACE_START = 0x64000000; + define symbol xSPI0_CS1_SPACE_LENGTH = 0x4000000; + define symbol xSPI1_CS0_SPACE_START = 0x68000000; + define symbol xSPI1_CS0_SPACE_LENGTH = 0x4000000; + define symbol xSPI1_CS1_SPACE_START = 0x6C000000; + define symbol xSPI1_CS1_SPACE_LENGTH = 0x4000000; + define symbol CS0_SPACE_START = 0x70000000; + define symbol CS0_SPACE_LENGTH = 0x4000000; + define symbol CS2_SPACE_START = 0x74000000; + define symbol CS2_SPACE_LENGTH = 0x4000000; + define symbol CS3_SPACE_START = 0x78000000; + define symbol CS3_SPACE_LENGTH = 0x4000000; + define symbol CS5_SPACE_START = 0x7C000000; + define symbol CS5_SPACE_LENGTH = 0x4000000; + define symbol CR52_0 = 1; diff --git a/bsp/renesas/rzt2m_rsk/project.custom_argvars b/bsp/renesas/rzt2m_rsk/project.custom_argvars new file mode 100644 index 00000000000..35fef7a1ec0 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/project.custom_argvars @@ -0,0 +1,9 @@ + + + + + RASC_EXE_PATH + C:\Renesas\rzt\sc_v2024-01.1_fsp_v2.0.0\eclipse\rasc.exe + + + diff --git a/bsp/renesas/rzt2m_rsk/project.ewd b/bsp/renesas/rzt2m_rsk/project.ewd new file mode 100644 index 00000000000..c6044908c89 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/project.ewd @@ -0,0 +1,3276 @@ + + + 4 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + GPLINK_ID + 2 + + 0 + 1 + 1 + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 33 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + GPLINK_ID + 2 + + 0 + 1 + 0 + + + + + + + IJET_ID + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 0 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/renesas/rzt2m_rsk/project.ewp b/bsp/renesas/rzt2m_rsk/project.ewp new file mode 100644 index 00000000000..60201486a4e --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/project.ewp @@ -0,0 +1,2805 @@ + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 38 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + ILINK + 0 + + 27 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + cmd /c ""$RASC_EXE_PATH$" -nosplash --launcher.suppressErrors --generate --compiler IAR --devicefamily rzt "$PROJ_DIR$\configuration.xml" 2> "%TEMP%\rasc_stderr.out"" + $PROJ_DIR$ + preCompile + + + $BUILD_FILES_DIR$/.prebuild + + + + + cmd /c ""$RASC_EXE_PATH$" -nosplash --launcher.suppressErrors --gensmartbundle --compiler IAR --devicefamily rzt "$PROJ_DIR$\configuration.xml" "$TARGET_PATH$" 2> "%TEMP%\rasc_stderr.out"" && echo > "$BUILD_FILES_DIR$/.postbuild" + $PROJ_DIR$ + postLink + + + $BUILD_FILES_DIR$/.postbuild + + + + + + + + + Release + + ARM + + 0 + + General + 3 + + 36 + 1 + 0 + + + + + + + + + + + + + + + + + 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--launcher.suppressErrors --gensmartbundle --compiler IAR --devicefamily rzt "$PROJ_DIR$\configuration.xml" "$TARGET_PATH$" 2> "%TEMP%\rasc_stderr.out"" && echo > "$BUILD_FILES_DIR$/.postbuild" + $PROJ_DIR$ + postLink + + + $BUILD_FILES_DIR$/.postbuild + + + + + + + + + Flex Software + + Build Configuration + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\board_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\bsp_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\bsp_mcu_device_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\bsp_mcu_device_memory_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\bsp_mcu_device_pn_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\bsp_mcu_family_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\bsp_memory_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\bsp_pin_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\r_ioport_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\r_sci_uart_cfg.h + + + + Components + + $PROJ_DIR$\rzt\board\rzt2m_rsk\board.h + + + $PROJ_DIR$\rzt\board\rzt2m_rsk\board_ethernet_phy.h + + + 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$PROJ_DIR$\rzt\fsp\src\bsp\cmsis\Device\RENESAS\Source\startup.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\cmsis\Device\RENESAS\Source\cr\startup_core.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\cmsis\Device\RENESAS\Source\system.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\cmsis\Device\RENESAS\Include\system.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\cmsis\Device\RENESAS\Source\cr\system_core.c + + + + Generated Data + + $PROJ_DIR$\rzt_gen\bsp_clock_cfg.h + + + $PROJ_DIR$\rzt_gen\common_data.c + + + $PROJ_DIR$\rzt_gen\common_data.h + + + $PROJ_DIR$\rzt_gen\hal_data.c + + + $PROJ_DIR$\rzt_gen\hal_data.h + + + $PROJ_DIR$\rzt_gen\main.c + + + $PROJ_DIR$\rzt_gen\pin_data.c + + + $PROJ_DIR$\rzt_gen\SConscript + + + $PROJ_DIR$\rzt_gen\vector_data.c + + + $PROJ_DIR$\rzt_gen\vector_data.h + + + + Program Entry + + $PROJ_DIR$\src\hal_entry.c + + + + + Kernel + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\klibc\kstdio.c + + + $PROJ_DIR$\..\..\..\src\klibc\kstring.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\scheduler_comm.c + + + $PROJ_DIR$\..\..\..\src\scheduler_up.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + + libcpu + + $PROJ_DIR$\..\..\..\libcpu\arm\common\atomic_arm.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + + + + POSIX + + + $PROJ_DIR$\buildinfo.ipcf + + diff --git a/bsp/renesas/rzt2m_rsk/project.eww b/bsp/renesas/rzt2m_rsk/project.eww new file mode 100644 index 00000000000..c2cb02eb1e8 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/renesas/rzt2m_rsk/rtconfig.h b/bsp/renesas/rzt2m_rsk/rtconfig.h new file mode 100644 index 00000000000..90e4d52d4df --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rtconfig.h @@ -0,0 +1,274 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 512 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50100 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +#define RT_USING_HW_ATOMIC +#define ARCH_ARM +#define ARCH_ARM_CORTEX_R +#define ARCH_ARM_CORTEX_R52 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_USING_DMA +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Memory protection */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* BL808 WiFi */ + + +/* CYW43439 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + + +/* Kendryte SDK */ + + +/* sensors drivers */ + + +/* touch drivers */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +#define SOC_FAMILY_RENESAS +#define SOC_SERIES_R9A07G0 + +/* Hardware Drivers Config */ + +#define SOC_R9A07G084 + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_UART0_RX_BUFSIZE 256 +#define BSP_UART0_TX_BUFSIZE 0 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rtconfig.py b/bsp/renesas/rzt2m_rsk/rtconfig.py new file mode 100644 index 00000000000..57a98c2bcb6 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rtconfig.py @@ -0,0 +1,123 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-r52' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'D:/IAR Systems/Embedded Workbench 9.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +# BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + NM = PREFIX + 'nm' + + DEVICE = ' -mcpu=cortex-r52 -marm -mfloat-abi=hard -mfpu=neon-fp-armv8 -munaligned-access -fdiagnostics-parseable-fixits -Og -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -funwind-tables' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=arm ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T script/fsp_xspi0_boot.ld -L script/' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g -Wall' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -Os' + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' + # POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-R52' + CFLAGS += ' -e' + CFLAGS += ' --arm' + CFLAGS += ' --float-abi=hard' + CFLAGS += ' --fpu=neon-fp-armv8' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-R52' + AFLAGS += ' --arm' + AFLAGS += ' --float-abi hard' + AFLAGS += ' --fpu neon-fp-armv8' + # AFLAGS += ' --unaligned-access' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "script/fsp_xspi0_boot.icf"' + LFLAGS += ' --entry Reset_Handler' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/renesas/rzt2m_rsk/rzt/SConscript b/bsp/renesas/rzt2m_rsk/rzt/SConscript new file mode 100644 index 00000000000..a740db16aaf --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/SConscript @@ -0,0 +1,28 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +from gcc import * + +cwd = GetCurrentDir() +src = [] +group = [] +CPPPATH = [] + +if rtconfig.PLATFORM in ['iccarm']: + Return('group') +elif rtconfig.PLATFORM in GetGCCLikePLATFORM(): + if GetOption('target') != 'mdk5': + src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c') + src += Glob(cwd + '/fsp/src/bsp/mcu/all/cr/*.c') + src += Glob(cwd + '/fsp/src/bsp/mcu/r*/*.c') + src += Glob(cwd + '/fsp/src/r_*/*.c') + src += Glob(cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/*.c') + src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c'] + src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c'] + CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core_R/Include', + cwd + '/fsp/inc', + cwd + '/fsp/inc/api', + cwd + '/fsp/inc/instances',] + +group = DefineGroup('rzt', src, depend = [''], CPPPATH = CPPPATH) +Return('group') diff --git a/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h new file mode 100644 index 00000000000..e1e68604b26 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h @@ -0,0 +1,290 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @date 31. August 2021 + ******************************************************************************/ +/* + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This file is based on the "\CMSIS\Core\Include\cmsis_compliler.h" + * + * Changes: + * - No Changes. + */ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h new file mode 100644 index 00000000000..174b5b8e561 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h @@ -0,0 +1,783 @@ +/**************************************************************************//** + * @file cmsis_cp15.h + * @brief CMSIS compiler specific macros, functions, instructions + * @date 02. February 2024 + ******************************************************************************/ +/* + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This file is based on the "CMSIS\Core_A\Include\cmsis_cp15.h" + * + * Changes: + * Renesas Electronics Corporation on 2021-08-31 + * - Changed to be related to Cortex-R52 by + * Renesas Electronics Corporation on 2024-02-02 + * - Functions are sorted according to the Arm technical reference. + * - Added some functions to convert BSP into C language. + */ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_CP15_H +#define __CMSIS_CP15_H + +/** \brief Get CTR + \return Cache Type Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CTR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 1); + return result; +} + +/** \brief Get MPIDR + + This function returns the value of the Multiprocessor Affinity Register. + + \return Multiprocessor Affinity Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 5); + return result; +} + +/** \brief Get CCSIDR + \return CCSIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) +{ + uint32_t result; + __get_CP(15, 1, result, 0, 0, 0); + return result; +} + +/** \brief Get CLIDR + \return CLIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CLIDR(void) +{ + uint32_t result; + __get_CP(15, 1, result, 0, 0, 1); + return result; +} + +/** \brief Get CSSELR + \return CSSELR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CSSELR(void) +{ + uint32_t result; + __get_CP(15, 2, result, 0, 0, 0); + return result; +} + +/** \brief Set CSSELR + */ +__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value) +{ + __set_CP(15, 2, value, 0, 0, 0); +} + +/** \brief Get SCTLR + + This function assigns the given value to the System Control Register. + + \return System Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_SCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 0); + return result; +} + +/** \brief Set SCTLR + \param [in] value System Control Register value to set + */ +__STATIC_FORCEINLINE void __set_SCTLR(uint32_t value) +{ + __set_CP(15, 0, value, 1, 0, 0); +} + + +/** \brief Get ACTLR + \return Auxiliary Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return(result); +} + +/** \brief Set ACTLR + \param [in] value Auxiliary Control value to set + */ +__STATIC_FORCEINLINE void __set_ACTLR(uint32_t value) +{ + __set_CP(15, 0, value, 1, 0, 1); +} + +/** \brief Get CPACR + \return Coprocessor Access Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 2); + return result; +} + +/** \brief Set CPACR + \param [in] value Coprocessor Access Control value to set + */ +__STATIC_FORCEINLINE void __set_CPACR(uint32_t value) +{ + __set_CP(15, 0, value, 1, 0, 2); +} + +/** \brief Get TTBR0 + + This function returns the value of the Translation Table Base Register 0. + + \return Translation Table Base Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_TTBR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 2, 0, 0); + return result; +} + +/** \brief Set TTBR0 + + This function assigns the given value to the Translation Table Base Register 0. + + \param [in] value Translation Table Base Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_TTBR0(uint32_t value) +{ + __set_CP(15, 0, value, 2, 0, 0); +} + +/** \brief Get DACR + + This function returns the value of the Domain Access Control Register. + + \return Domain Access Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 3, 0, 0); + return result; +} + +/** \brief Set DACR + + This function assigns the given value to the Domain Access Control Register. + + \param [in] value Domain Access Control Register value to set + */ +__STATIC_FORCEINLINE void __set_DACR(uint32_t value) +{ + __set_CP(15, 0, value, 3, 0, 0); +} + +/** \brief Get ICC_PMR + */ +__STATIC_FORCEINLINE uint32_t __get_ICC_PMR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 4, 6, 0); + return result; +} + +/** \brief Set ICC_PMR + */ +__STATIC_FORCEINLINE void __set_ICC_PMR(uint32_t value) +{ + __set_CP(15, 0, value, 4, 6, 0); +} + +/** \brief Get DFSR + \return Data Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 0); + return result; +} + +/** \brief Set DFSR + \param [in] value Data Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_DFSR(uint32_t value) +{ + __set_CP(15, 0, value, 5, 0, 0); +} + +/** \brief Get IFSR + \return Instruction Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 1); + return result; +} + +/** \brief Set IFSR + \param [in] value Instruction Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_IFSR(uint32_t value) +{ + __set_CP(15, 0, value, 5, 0, 1); +} + +/** \brief Set PRSELR + + This function assigns the given value to the Protection Region Selection Register. + + \param [in] value Protection Region Selection Register to set + */ +__STATIC_FORCEINLINE void __set_PRSELR(uint32_t value) +{ + __set_CP(15, 0, value, 6, 2, 1); +} + +/** \brief Get PRBAR + + This function returns the value of the Protection Region Base Address Register. + + \return Protection Region Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_PRBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 6, 3, 0); + return result; +} + +/** \brief Set PRBAR + + This function assigns the given value to the Protection Region Base Address Register. + + \param [in] value Protection Region Base Address Register to set + */ +__STATIC_FORCEINLINE void __set_PRBAR(uint32_t value) +{ + __set_CP(15, 0, value, 6, 3, 0); +} + +/** \brief Get PRLAR + + This function returns the value of the Protection Region Limit Address Register. + + \return Protection Region Limit Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_PRLAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 6, 3, 1); + return result; +} + +/** \brief Set PRLAR + + This function assigns the given value to the Protection Region Limit Address Register. + + \param [in] value Protection Region Limit Address Register to set + */ +__STATIC_FORCEINLINE void __set_PRLAR(uint32_t value) +{ + __set_CP(15, 0, value, 6, 3, 1); +} + +/** \brief Set ICIALLU + + Instruction Cache Invalidate All + */ +__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 0); +} + +/** \brief Set ICIVAU + */ +__STATIC_FORCEINLINE void __set_ICIVAU(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 1); +} + +/** \brief Set BPIALL. + + Branch Predictor Invalidate All + */ +__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 6); +} + +/** \brief Set DCIMVAC + + Data cache invalidate + */ +__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 1); +} + +/** \brief Set DCIVAC + */ +__STATIC_FORCEINLINE void __set_DCIVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 1); +} + +/** \brief Set DCISW + */ +__STATIC_FORCEINLINE void __set_DCISW(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 2); +} + +/** \brief Set DCCMVAC + + Data cache clean + */ +__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 1); +} + +/** \brief Set DCCVAC + */ +__STATIC_FORCEINLINE void __set_DCCVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 1); +} + +/** \brief Set DCCSW + */ +__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 2); +} + +/** \brief Set DCCIMVAC + + Data cache clean and invalidate + */ +__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 1); +} + +/** \brief Set DCCIVAC + */ +__STATIC_FORCEINLINE void __set_DCCIVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 1); +} + +/** \brief Set DCCISW + */ +__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 2); +} + +/** \brief Set TLBIALL + + TLB Invalidate All + */ +__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) +{ + __set_CP(15, 0, value, 8, 7, 0); +} + +/** \brief Set MAIR0 + + This function assigns the given value to the Memory Attribute Indirection Registers 0. + + \param [in] value Memory Attribute Indirection Registers 0 to set + */ +__STATIC_FORCEINLINE void __set_MAIR0(uint32_t value) +{ + __set_CP(15, 0, value, 10, 2, 0); +} + +/** \brief Set MAIR1 + + This function assigns the given value to the Memory Attribute Indirection Registers 1. + + \param [in] value Memory Attribute Indirection Registers 1 to set + */ +__STATIC_FORCEINLINE void __set_MAIR1(uint32_t value) +{ + __set_CP(15, 0, value, 10, 2, 1); +} + +/** \brief Get IMP_SLAVEPCTLR + + This function returns the value of the Slave Port Control Register. + + \return Slave Port Control Register + */ +__STATIC_FORCEINLINE uint32_t __get_IMP_SLAVEPCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 11, 0, 0); + return result; +} + +/** \brief Set IMP_SLAVEPCTLR + + This function assigns the given value to the Slave Port Control Register. + + \param [in] value Slave Port Control Register value to set + */ +__STATIC_FORCEINLINE void __set_IMP_SLAVEPCTLR(uint32_t value) +{ + __set_CP(15, 0, value, 11, 0, 0); +} + +/** \brief Get VBAR + + This function returns the value of the Vector Base Address Register. + + \return Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_VBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 0); + return result; +} + +/** \brief Set VBAR + + This function assigns the given value to the Vector Base Address Register. + + \param [in] value Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_VBAR(uint32_t value) +{ + __set_CP(15, 0, value, 12, 0, 0); +} + +/** \brief Get MVBAR + + This function returns the value of the Monitor Vector Base Address Register. + + \return Monitor Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_MVBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 1); + return result; +} + +/** \brief Set MVBAR + + This function assigns the given value to the Monitor Vector Base Address Register. + + \param [in] value Monitor Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_MVBAR(uint32_t value) +{ + __set_CP(15, 0, value, 12, 0, 1); +} + +/** \brief Get ISR + \return Interrupt Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ISR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 1, 0); + return result; +} + +/** \brief Get ICC_RPR + */ +__STATIC_FORCEINLINE uint32_t __get_ICC_RPR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 11, 3); + return result; +} + +/** \brief Get ICC_IAR1 + */ +__STATIC_FORCEINLINE uint32_t __get_ICC_IAR1(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 12, 0); + return result; +} + +/** \brief Set ICC_EOIR1 + */ +__STATIC_FORCEINLINE void __set_ICC_EOIR1(uint32_t value) +{ + __set_CP(15, 0, value, 12, 12, 0); +} + +/** \brief Get ICC_HPPIR1 + */ +__STATIC_FORCEINLINE uint32_t __get_ICC_HPPIR1(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 12, 2); + return result; +} + +/** \brief Get ICC_BPR1 + */ +__STATIC_FORCEINLINE uint32_t __get_ICC_BPR1(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 12, 3); + return result; +} + +/** \brief Set ICC_BPR1 + */ +__STATIC_FORCEINLINE void __set_ICC_BPR1(uint32_t value) +{ + __set_CP(15, 0, value, 12, 12, 3); +} + +/** \brief Get ICC_CTLR + */ +__STATIC_FORCEINLINE uint32_t __get_ICC_CTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 12, 4); + return result; +} + +/** \brief Set ICC_CTLR + */ +__STATIC_FORCEINLINE void __set_ICC_CTLR(uint32_t value) +{ + __set_CP(15, 0, value, 12, 12, 4); +} + +/** \brief Set ICC_IGRPEN1 + */ +__STATIC_FORCEINLINE void __set_ICC_IGRPEN1(uint32_t value) +{ + __set_CP(15, 0, value, 12, 12, 7); +} + +/** \brief Set CNTFRQ + + This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \param [in] value CNTFRQ Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) +{ + __set_CP(15, 0, value, 14, 0, 0); +} + +/** \brief Get CNTFRQ + + This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \return CNTFRQ Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 0, 0); + return result; +} + +/** \brief Set CNTKCTL + + This function assigns the given value to Counter-timer Kernel Control Register (CNTKCTL). + + \param [in] value CNTKCTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTKCTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 1, 0); +} + +/** \brief Get CNTKCTL + + This function returns the value of the Counter-timer kernel Control Register (CNTKCTL). + + \return CNTFRQ Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTKCTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 1, 0); + return result; +} + +/** \brief Set CNTP_TVAL + + This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + + \param [in] value CNTP_TVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 0); +} + +/** \brief Get CNTP_TVAL + + This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + + \return CNTP_TVAL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 0); + return result; +} + +/** \brief Set CNTP_CTL + + This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + + \param [in] value CNTP_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 1); +} + +/** \brief Get CNTP_CTL register + \return CNTP_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 1); + return result; +} + +/** \brief Set CNTV_CTL + + This function assigns the given value to PL1 Virtual Timer Control Register (CNTV_CTL). + + \param [in] value CNTV_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTV_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 3, 1); +} + +/** \brief Get CNTV_CTL register + \return CNTV_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTV_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 3, 1); + return result; +} + +/** \brief Get CBAR + \return Configuration Base Address register value + */ +__STATIC_FORCEINLINE uint32_t __get_CBAR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 15, 0, 0); + return result; +} + +/** \brief Get CNTPCT + + This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + + \return CNTPCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void) +{ + uint64_t result; + __get_CP64(15, 0, result, 14); + return result; +} + +/** \brief Set ICC_SGI1R + */ +__STATIC_FORCEINLINE void __set_ICC_SGI1R(uint64_t value) +{ + __set_CP64(15, 0, value, 12); +} + +/** \brief Get CNTVCT + + This function returns the value of the 64 bits PL1 Virtual Count Register (CNTVCT). + + \return CNTVCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTVCT(void) +{ + uint64_t result; + __get_CP64(15, 1, result, 14); + return result; +} + +/** \brief Set CNTP_CVAL + + This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \param [in] value CNTP_CVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value) +{ + __set_CP64(15, 2, value, 14); +} + +/** \brief Get CNTP_CVAL + + This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \return CNTP_CVAL Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void) +{ + uint64_t result; + __get_CP64(15, 2, result, 14); + return result; +} + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h new file mode 100644 index 00000000000..1e6e8bddcb3 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h @@ -0,0 +1,2233 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @date 02. February 2024 + ******************************************************************************/ +/* + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This file is based on the "\CMSIS\Core\Include\cmsis_gcc.h" + * + * Changes: + * Renesas Electronics Corporation on 2021-08-31 + * - Add CP15 descriptions by + * Renesas Electronics Corporation on 2024-02-02 + * - Added functions related to FPEXC registers. + */ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +/** + * \brief Get FPEXC + * \details Returns the current value of the Floating Point Exception Control register. + * \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC (void) +{ +#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined(__FPU_USED) && (__FPU_USED == 1U))) + + uint32_t result; + + __ASM volatile ("VMRS %0, fpexc" : "=r" (result)); + + return result; +#else + + return 0U; +#endif +} + +/** + * \brief Set FPEXC + * \details Assigns the given value to the Floating Point Exception Control register. + * \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC (uint32_t fpexc) +{ +#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined(__FPU_USED) && (__FPU_USED == 1U))) + + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#else + (void) fpexc; +#endif +} + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h new file mode 100644 index 00000000000..a6882cfe80b --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h @@ -0,0 +1,958 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @date 02. February 2024 + ******************************************************************************/ +// ------------------------------------------------------------------------------ +// +// Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. +// +// This file is based on the "\CMSIS\Core\Include\cmsis_iccarm.h" +// +// Changes: +// Renesas Electronics Corporation on 2021-08-31 +// - Changed to be related to Cortex-R52 by +// Renesas Electronics Corporation on 2024-02-02 +// - Added functions related to FPEXC registers. +// - Moved the process of defining compiler macros for CPU architectures to renesas.h. +// +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + + #define __get_FPEXC() (__arm_rsr("FPEXC")) + #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", (VALUE))) + #else + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void) VALUE) + + #define __get_FPEXC() (0) + #define __set_FPEXC(VALUE) ((void) VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __get_CP(cp, op1, RT, CRn, CRm, op2) \ + ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2)) + + #define __set_CP(cp, op1, RT, CRn, CRm, op2) \ + (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT))) + + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + + #define __get_FPEXC() (0) + #define __set_FPEXC(VALUE) ((void) VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h new file mode 100644 index 00000000000..fa9f84c16f7 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @date 31. August 2021 + ******************************************************************************/ +/* + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This file is based on the "\CMSIS\Core\Include\cmsis_version.h" + * + * Changes: + * - No Changes. + */ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h new file mode 100644 index 00000000000..615ae49a34d --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h @@ -0,0 +1,312 @@ +/**************************************************************************//** + * @file core_cr52.h + * @brief CMSIS Cortex-R52 Core Peripheral Access Layer Header File + * @date 31. August 2021 + ******************************************************************************/ +/* + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This file is based on the "\CMSIS\Core\Include\core_armv8mml.h" + * + * Changes: + * Renesas Electronics Corporation on 2021-08-31 + * - Changed to be related to Cortex-R52 by + */ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CR52_H_GENERIC +#define __CORE_CR52_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_R52 + @{ + */ + +#if defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #define __FPU_D32 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #ifndef __ARMVFP_D16__ + #define __FPU_D32 1U + #endif + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif +#endif + +#include "cmsis_version.h" + +/* CMSIS CR52 definitions */ +#define __CR52_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CR52_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CR52_CMSIS_VERSION ((__CR52_CMSIS_VERSION_MAIN << 16U) | \ + __CR52_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_R (52U) /*!< Cortex-R Core */ + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CR52_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CR52_H_DEPENDANT +#define __CORE_CR52_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_R52 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_GIC Generic Interrupt Controller (GIC) + \brief Type definitions for the GIC Registers + @{ +*/ + + /** + \brief Structure type to access the Generic Interrupt Controller (GIC) for GICD. + */ +typedef struct +{ + __IOM uint32_t GICD_CTLR; /*!< Offset: 0x0000 (R/W) Distributor Control Register */ + __IM uint32_t GICD_TYPER; /*!< Offset: 0x0004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t GICD_IIDR; /*!< Offset: 0x0008 (R/ ) Distributor Implementer Identification Register */ + uint32_t RESERVED0[30U]; + __IOM uint32_t GICD_IGROUPR[30U]; /*!< Offset: 0x0084 (R/W) Interrupt Group Registers 1 - 30 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t GICD_ISENABLER[30U]; /*!< Offset: 0x0104 (R/W) Interrupt Set-Enable Registers 1 - 30 */ + uint32_t RESERVED2[2U]; + __IOM uint32_t GICD_ICENABLER[30U]; /*!< Offset: 0x0184 (R/W) Interrupt Clear-Enable Registers 1 - 30 */ + uint32_t RESERVED3[2U]; + __IOM uint32_t GICD_ISPENDR[30U]; /*!< Offset: 0x0204 (R/W) Interrupt Set-Pending Registers 1 - 30 */ + uint32_t RESERVED4[2U]; + __IOM uint32_t GICD_ICPENDR[30U]; /*!< Offset: 0x0284 (R/W) Interrupt Clear-Pending Registers 1 - 30 */ + uint32_t RESERVED5[2U]; + __IOM uint32_t GICD_ISACTIVER[30U]; /*!< Offset: 0x0304 (R/W) Interrupt Set-Active Registers 1 - 30 */ + uint32_t RESERVED6[2U]; + __IOM uint32_t GICD_ICACTIVER[30U]; /*!< Offset: 0x0384 (R/W) Interrupt Clear-Active Registers 1 - 30 */ + uint32_t RESERVED7[9U]; + __IOM uint32_t GICD_IPRIORITYR[240U]; /*!< Offset: 0x0420 (R/W) Interrupt Priority Registers 8 - 247 */ + uint32_t RESERVED8[266U]; + __IOM uint32_t GICD_ICFGR[60U]; /*!< Offset: 0x0C08 (R/W) Interrupt Configuration Registers 2 - 61 */ +} GICD_Type; + + /** + \brief Structure type to access the Generic Interrupt Controller (GIC) for GICR for Control target. + */ +typedef struct +{ + __IM uint32_t GICR_CTLR; /*!< Offset: 0x0000 (R/ ) Redistributor Control Register */ + __IM uint32_t GICR_IIDR; /*!< Offset: 0x0004 (R/ ) Redistributor Implementer Identification Register */ + __IM uint32_t GICR_TYPER[2]; /*!< Offset: 0x0008 (R/ ) Redistributor Type Register */ + uint32_t RESERVED0; + __IOM uint32_t GICR_WAKER; /*!< Offset: 0x0014 (R/W) Redistributor Wake Register */ +} GICR_CONTROL_TARGET_Type; + + /** + \brief Structure type to access the Generic Interrupt Controller (GIC) for GICR for SGI and PPI. + */ +typedef struct +{ + uint32_t RESERVED0[32]; + __IOM uint32_t GICR_IGROUPR0; /*!< Offset: 0x0080 (R/W) Interrupt Group Register 0 */ + uint32_t RESERVED1[31]; + __IOM uint32_t GICR_ISENABLER0; /*!< Offset: 0x0100 (R/W) Interrupt Set-Enable Register 0 */ + uint32_t RESERVED2[31]; + __IOM uint32_t GICR_ICENABLER0; /*!< Offset: 0x0180 (R/W) Interrupt Clear-Enable Register 0 */ + uint32_t RESERVED3[31]; + __IOM uint32_t GICR_ISPENDR0; /*!< Offset: 0x0200 (R/W) Interrupt Set-Pending Register 0 */ + uint32_t RESERVED4[31]; + __IOM uint32_t GICR_ICPENDR0; /*!< Offset: 0x0280 (R/W) Interrupt Clear-Pending Register 0 */ + uint32_t RESERVED5[31]; + __IOM uint32_t GICR_ISACTIVER0; /*!< Offset: 0x0300 (R/W) Interrupt Set-Active Register 0 */ + uint32_t RESERVED6[31]; + __IOM uint32_t GICR_ICACTIVER0; /*!< Offset: 0x0380 (R/W) Interrupt Clear-Active Register 0 */ + uint32_t RESERVED7[31]; + __IOM uint32_t GICR_IPRIORITYR[8]; /*!< Offset: 0x0400 (R/W) Interrupt Priority Registers 0 - 7 */ + uint32_t RESERVED8[504]; + __IM uint32_t GICR_ICFGR0; /*!< Offset: 0x0C00 (R/ ) Interrupt Configuration Register 0 */ + __IOM uint32_t GICR_ICFGR1; /*!< Offset: 0x0C04 (R/W) Interrupt Configuration Register 1 */ +} GICR_SGI_PPI_Type; + +/*@} end of group CMSIS_GIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define GIC0_BASE (0x94000000UL) /*!< GIC0 Base Address */ +#define GIC1_BASE (0x9C000000UL) /*!< GIC1 Base Address */ +#define GICR_TARGET0_BASE (0x00100000UL) /*!< GICR Base Address (for Control target 0) */ +#define GICR_TARGET0_SGI_PPI_BASE (0x00110000UL) /*!< GICR Base Address (for SGI and PPI target 0) */ + +#define GICD0 ((GICD_Type *) GIC0_BASE ) /*!< GICD configuration struct */ +#define GICD1 ((GICD_Type *) GIC1_BASE ) /*!< GICD configuration struct */ +#define GICR0_TARGET0_IFREG ((GICR_CONTROL_TARGET_Type *) (GIC0_BASE + GICR_TARGET0_BASE) ) /*!< GICR configuration struct for Control target 0 */ +#define GICR1_TARGET0_IFREG ((GICR_CONTROL_TARGET_Type *) (GIC1_BASE + GICR_TARGET0_BASE) ) /*!< GICR configuration struct for Control target 0 */ +#define GICR0_TARGET0_INTREG ((GICR_SGI_PPI_Type *) (GIC0_BASE + GICR_TARGET0_SGI_PPI_BASE) ) /*!< GICR configuration struct for SGI and PPI target 0 */ +#define GICR1_TARGET0_INTREG ((GICR_SGI_PPI_Type *) (GIC1_BASE + GICR_TARGET0_SGI_PPI_BASE) ) /*!< GICR configuration struct for SGI and PPI target 0 */ + +/*@} */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief Get CPSR Register + + This function returns the content of the CPSR Register. + + \return CPSR Register value + */ +__STATIC_INLINE uint32_t __get_CPSR(void) +{ + register uint32_t __regCPSR __ASM("cpsr"); + return(__regCPSR); +} + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ + + +#include + + +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* __CORE_CR52_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/LICENSE.txt b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/LICENSE.txt new file mode 100644 index 00000000000..8dada3edaf5 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board.h b/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board.h new file mode 100644 index 00000000000..248ea7aaeb2 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board.h @@ -0,0 +1,67 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * File Name : board.h + * Description : Includes and API function available for this board. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RZT2M_RSK + * @brief BSP for the RZT2M_RSK Board + * + * The RZT2M_RSK is a development kit for the Renesas RZT2M microcontroller. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_leds.h" +#include "board_ethernet_phy.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RZT2M_RSK + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_CONFIG_RZT2M) */ + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_ethernet_phy.h b/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_ethernet_phy.h new file mode 100644 index 00000000000..ee9c82e060c --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_ethernet_phy.h @@ -0,0 +1,60 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RZT2M_RSK + * @defgroup BOARD_RZT2M_RSK_ETHERNET_PHY Board Ethernet Phy + * @brief Ethernet Phy information for this board. + * + * This is code specific to the RZT2M_RSK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_ETHERNET_PHY_H +#define BSP_ETHERNET_PHY_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define ETHER_PHY_CFG_TARGET_VSC8541_ENABLE (1) +#define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_VSC8541 + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RZT2M_RSK_ETHERNET_PHY) */ diff --git a/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_init.c b/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_init.c new file mode 100644 index 00000000000..b1ab1649004 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_init.c @@ -0,0 +1,67 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * File Name : board_init.c + * Description : This module calls any initialization code specific to this BSP. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RZT2M_RSK_INIT + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RZT2M_RSK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RZT2M_RSK_INIT) */ diff --git a/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_init.h b/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_init.h new file mode 100644 index 00000000000..d9e014ba8b2 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_init.h @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * File Name : board_init.h + * Description : This module calls any initialization code specific to this BSP. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RZT2M_RSK + * @defgroup BOARD_RZT2M_RSK_INIT + * @brief Board specific code for the RZT2M_RSK Board + * + * This include file is specific to the RZT2M_RSK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RZT2M_RSK_INIT) */ diff --git a/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_leds.c b/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_leds.c new file mode 100644 index 00000000000..ad28218f917 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_leds.c @@ -0,0 +1,82 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * File Name : board_leds.c + * Description : This module has information about the LEDs on this board. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RZT2M_RSK_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if defined(BOARD_RZT2M_RSK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED IOPORT pins. */ +static const uint32_t g_bsp_prv_leds[][2] = +{ + #if defined(BSP_CFG_CORE_CR52) + #if (0 == BSP_CFG_CORE_CR52) + {(uint32_t) BSP_IO_PORT_19_PIN_6, (uint32_t) BSP_IO_REGION_SAFE}, ///< LED0(Green) + {(uint32_t) BSP_IO_PORT_19_PIN_4, (uint32_t) BSP_IO_REGION_SAFE} ///< LED1(Yellow) + #elif (1 == BSP_CFG_CORE_CR52) + {(uint32_t) BSP_IO_PORT_20_PIN_0, (uint32_t) BSP_IO_REGION_SAFE}, ///< LED2(Red) + {(uint32_t) BSP_IO_PORT_23_PIN_4, (uint32_t) BSP_IO_REGION_SAFE} ///< LED3(Red) + #endif + #endif +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) (sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0])), + .p_leds = g_bsp_prv_leds +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_RZT2M_RSK_LEDS) */ diff --git a/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_leds.h b/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_leds.h new file mode 100644 index 00000000000..4712d7558ec --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/board/rzt2m_rsk/board_leds.h @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * File Name : board_leds.h + * Description : This module has information about the LEDs on this board. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RZT2M_RSK + * @defgroup BOARD_RZT2M_RSK_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the RZT2M_RSK board. It includes info on the number of LEDs and which pins are they + * are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint32_t const (*p_leds)[2]; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ +#if defined(BSP_CFG_CORE_CR52) + #if (0 == BSP_CFG_CORE_CR52) + BSP_LED_RLED0 = 0, ///< Green + BSP_LED_RLED1 = 1, ///< Yellow + #elif (1 == BSP_CFG_CORE_CR52) + BSP_LED_RLED2 = 0, ///< Red + BSP_LED_RLED3 = 1, ///< Red + #endif +#endif +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RZT2M_RSK_LEDS) */ diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/api/bsp_api.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/api/bsp_api.h new file mode 100644 index 00000000000..b2c951b125b --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/api/bsp_api.h @@ -0,0 +1,111 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_API_H +#define BSP_API_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* FSP Common Includes. */ +#include "fsp_common_api.h" + +/* Gets MCU configuration information. */ +#include "bsp_cfg.h" + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + +/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ + #pragma GCC diagnostic push + +/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h. + * We are not modifying these files so we will ignore these warnings temporarily. */ + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wsign-conversion" +#endif + +/* Vector information for this project. This is generated by the tooling. */ +#include "../../src/bsp/mcu/all/bsp_exceptions.h" +#include "vector_data.h" + +/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */ +#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h" +#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h" + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + +/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ + #pragma GCC diagnostic pop +#endif + +#if defined(BSP_API_OVERRIDE) + #include BSP_API_OVERRIDE +#else + +/* BSP Common Includes. */ + #include "../../src/bsp/mcu/all/bsp_common.h" + +/* BSP MCU Specific Includes. */ + #include "../../src/bsp/mcu/all/bsp_register_protection.h" + #include "../../src/bsp/mcu/all/bsp_irq.h" + #include "../../src/bsp/mcu/all/bsp_io.h" + #include "../../src/bsp/mcu/all/bsp_group_irq.h" + #include "../../src/bsp/mcu/all/bsp_clocks.h" + #include "../../src/bsp/mcu/all/bsp_module_stop.h" + #include "../../src/bsp/mcu/all/bsp_security.h" + +/* Factory MCU information. */ + #include "../../inc/fsp_features.h" + +/* BSP Common Includes (Other than bsp_common.h) */ + #include "../../src/bsp/mcu/all/bsp_delay.h" + #include "../../src/bsp/mcu/all/bsp_mcu_api.h" + +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version); + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/api/r_ioport_api.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/api/r_ioport_api.h new file mode 100644 index 00000000000..d6b3049b844 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/api/r_ioport_api.h @@ -0,0 +1,206 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_SYSTEM_INTERFACES + * @defgroup IOPORT_API I/O Port Interface + * @brief Interface for accessing I/O ports and configuring I/O functionality. + * + * @section IOPORT_API_SUMMARY Summary + * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. + * Port and pin direction can be changed. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_IOPORT_API_H +#define R_IOPORT_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_IOPORT_SIZE_T + +/** IO port type used with ports */ +typedef uint16_t ioport_size_t; ///< IO port size +#endif + +/** Pin identifier and pin configuration value */ +typedef struct st_ioport_pin_cfg +{ + uint32_t pin_cfg; ///< Pin configuration - Use ioport_cfg_options_t parameters to configure + bsp_io_port_pin_t pin; ///< Pin identifier +} ioport_pin_cfg_t; + +/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */ +typedef struct st_ioport_cfg +{ + uint16_t number_of_pins; ///< Number of pins for which there is configuration data + ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data + const void * p_extend; ///< Pointer to hardware extend configuration +} ioport_cfg_t; + +/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. + */ +typedef void ioport_ctrl_t; + +/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */ +typedef struct st_ioport_api +{ + /** Initialize internal driver data and initial pin configurations. Called during startup. Do + * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of + * multiple pins. + * + * @param[in] p_ctrl Pointer to control structure. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Close the API. + * + * @param[in] p_ctrl Pointer to control structure. + **/ + fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); + + /** Configure multiple pins. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Configure settings for an individual pin. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. + * @param[in] cfg Configuration options for the pin. + */ + fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); + + /** Read the event input data of the specified pin and return the level. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. + * @param[in] p_pin_event Pointer to return the event data. + */ + fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); + + /** Write pin event data. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin event data is to be written to. + * @param[in] pin_value Level to be written to pin output event. + */ + fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); + + /** Read level of a pin. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. + * @param[in] p_pin_value Pointer to return the pin level. + */ + fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); + + /** Write specified level to a pin. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be written to. + * @param[in] level State to be written to the pin. + */ + fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); + + /** Set the direction of one or more pins on a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port being configured. + * @param[in] direction_values Value controlling direction of pins on port. + * @param[in] mask Mask controlling which pins on the port are to be configured. + */ + fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, + ioport_size_t mask); + + /** Read captured event data for a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port to be read. + * @param[in] p_event_data Pointer to return the event data. + */ + fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); + + /** Write event output data for a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port event data will be written to. + * @param[in] event_data Data to be written as event data to specified port. + * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. + * being written to port. + */ + fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, + ioport_size_t mask_value); + + /** Read states of pins on the specified port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port to be read. + * @param[in] p_port_value Pointer to return the port value. + */ + fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); + + /** Write to multiple pins on a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port to be written to. + * @param[in] value Value to be written to the port. + * @param[in] mask Mask controlling which pins on the port are written to. + */ + fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); +} ioport_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_ioport_instance +{ + ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + ioport_api_t const * p_api; ///< Pointer to the API structure for this instance +} ioport_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup IOPORT_API) + **********************************************************************************************************************/ diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/api/r_transfer_api.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/api/r_transfer_api.h new file mode 100644 index 00000000000..530c88dc9de --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/api/r_transfer_api.h @@ -0,0 +1,402 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_TRANSFER_INTERFACES + * @defgroup TRANSFER_API Transfer Interface + * + * @brief Interface for data transfer functions. + * + * @section TRANSFER_API_SUMMARY Summary + * The transfer interface supports background data transfer (no CPU intervention). + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_TRANSFER_API_H +#define R_TRANSFER_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define TRANSFER_SETTINGS_MODE_BITS (30U) +#define TRANSFER_SETTINGS_SIZE_BITS (28U) +#define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U) +#define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U) +#define TRANSFER_SETTINGS_IRQ_BITS (21U) +#define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U) +#define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls. + */ +typedef void transfer_ctrl_t; + +#ifndef BSP_OVERRIDE_TRANSFER_MODE_T + +/** Transfer mode describes what will happen when a transfer request occurs. */ +typedef enum e_transfer_mode +{ + /** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to + * the destination pointer. The transfer length is decremented and the source and address pointers are + * updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests + * will not cause any further transfers. */ + TRANSFER_MODE_NORMAL = 0, + + /** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the + * repeat area and the transfer length will be reset to their initial values. If DMAC is used, the + * transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats + * transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is + * used, the transfer repeats continuously (no limit to the number of repeat transfers). */ + TRANSFER_MODE_REPEAT = 1, + + /** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t. + * After each individual transfer, the source and destination pointers are updated according to + * @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is + * decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any + * further transfers. */ + TRANSFER_MODE_BLOCK = 2, + + /** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets + * within a block (to split blocks into arrays of their first data, second data, etc.) */ + TRANSFER_MODE_REPEAT_BLOCK = 3 +} transfer_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_SIZE_T + +/** Transfer size specifies the size of each individual transfer. + * Total transfer length = transfer_size_t * transfer_length_t + */ +typedef enum e_transfer_size +{ + TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value + TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value + TRANSFER_SIZE_4_BYTE = 2 ///< Each transfer transfers a 32-bit value +} transfer_size_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_ADDR_MODE_T + +/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */ +typedef enum e_transfer_addr_mode +{ + /** Address pointer remains fixed after each transfer. */ + TRANSFER_ADDR_MODE_FIXED = 0, + + /** Offset is added to the address pointer after each transfer. */ + TRANSFER_ADDR_MODE_OFFSET = 1, + + /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_INCREMENTED = 2, + + /** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_DECREMENTED = 3 +} transfer_addr_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_REPEAT_AREA_T + +/** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its + * original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK, + * the selected pointer returns to its original value after each transfer. */ +typedef enum e_transfer_repeat_area +{ + /** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ + TRANSFER_REPEAT_AREA_DESTINATION = 0, + + /** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ + TRANSFER_REPEAT_AREA_SOURCE = 1 +} transfer_repeat_area_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_CHAIN_MODE_T + +/** Chain transfer mode options. + * @note Only applies for DTC. */ +typedef enum e_transfer_chain_mode +{ + /** Chain mode not used. */ + TRANSFER_CHAIN_MODE_DISABLED = 0, + + /** Switch to next transfer after a single transfer from this @ref transfer_info_t. */ + TRANSFER_CHAIN_MODE_EACH = 2, + + /** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */ + TRANSFER_CHAIN_MODE_END = 3 +} transfer_chain_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_IRQ_T + +/** Interrupt options. */ +typedef enum e_transfer_irq +{ + /** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer, + * the interrupt will occur only after subsequent chained transfer(s) are complete. + * @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will + * prevent activation source interrupts until the transfer is complete. */ + TRANSFER_IRQ_END = 0, + + /** Interrupt occurs after each transfer. + * @note Not available in all HAL drivers. See HAL driver for details. */ + TRANSFER_IRQ_EACH = 1 +} transfer_irq_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_CALLBACK_ARGS_T + +/** Callback function parameter data. */ +typedef struct st_transfer_callback_args_t +{ + void const * p_context; ///< Placeholder for user data. Set in @ref transfer_api_t::open function in ::transfer_cfg_t. +} transfer_callback_args_t; + +#endif + +/** Driver specific information. */ +typedef struct st_transfer_properties +{ + uint32_t block_count_max; ///< Maximum number of blocks + uint32_t block_count_remaining; ///< Number of blocks remaining + uint32_t transfer_length_max; ///< Maximum number of transfers + uint32_t transfer_length_remaining; ///< Number of transfers remaining +} transfer_properties_t; + +#ifndef BSP_OVERRIDE_TRANSFER_INFO_T + +/** This structure specifies the properties of the transfer. + * @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC. + * The following components may be modified by the driver: p_src, p_dest, num_blocks, and length. + * @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must + * have a unique transfer_info_t. + * @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this + * structure must remain in scope until the transfer it is used for is closed. + * @note When using DTC, consider placing instances of this structure in a protected section of memory. */ +typedef struct st_transfer_info +{ + union + { + struct + { + uint32_t : 16; + uint32_t : 2; + + /** Select what happens to destination pointer after each transfer. */ + transfer_addr_mode_t dest_addr_mode : 2; + + /** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */ + transfer_repeat_area_t repeat_area : 1; + + /** Select if interrupts should occur after each individual transfer or after the completion of all planned + * transfers. */ + transfer_irq_t irq : 1; + + /** Select when the chain transfer ends. */ + transfer_chain_mode_t chain_mode : 2; + + uint32_t : 2; + + /** Select what happens to source pointer after each transfer. */ + transfer_addr_mode_t src_addr_mode : 2; + + /** Select number of bytes to transfer at once. @see transfer_info_t::length. */ + transfer_size_t size : 2; + + /** Select mode from @ref transfer_mode_t. */ + transfer_mode_t mode : 2; + } transfer_settings_word_b; + + uint32_t transfer_settings_word; + }; + + void const * volatile p_src; ///< Source pointer + void * volatile p_dest; ///< Destination pointer + + /** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or + * @ref TRANSFER_MODE_REPEAT (DMAC only) or + * @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */ + volatile uint16_t num_blocks; + + /** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT, + * and @ref TRANSFER_MODE_REPEAT_BLOCK + * see HAL driver for details. */ + volatile uint16_t length; +} transfer_info_t; + +#endif + +/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be + * initialized. */ +typedef struct st_transfer_cfg +{ + /** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to + * an array of chained transfers that will be completed in order. */ + transfer_info_t * p_info; + + void const * p_extend; ///< Extension parameter for hardware specific settings. +} transfer_cfg_t; + +/** Select whether to start single or repeated transfer with software start. */ +typedef enum e_transfer_start_mode +{ + TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer. + TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete. +} transfer_start_mode_t; + +/** Transfer functions implemented at the HAL layer will follow this API. */ +typedef struct st_transfer_api +{ + /** Initial configuration. + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure + * must be set by user. + */ + fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg); + + /** Reconfigure the transfer. + * Enable the transfer if p_info is valid. + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_info Pointer to a new transfer info structure. + */ + fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info); + + /** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same. + * Enable the transfer if p_src, p_dest, and length are valid. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. + * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. + * @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only, + * resets number of repeats (initially stored in transfer_info_t::num_blocks) in + * repeat mode. Not used in repeat mode for DTC. + */ + fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, + uint16_t const num_transfers); + + /** Enable transfer. Transfers occur after the activation source event (or when + * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as activation source). + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl); + + /** Disable transfer. Transfers do not occur after the activation source event (or when + * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as the DMAC activation source). + * @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a + * transfer. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl); + + /** Start transfer in software. + * @warning Only works if no peripheral event is chosen as the DMAC activation source. + * @note Not supported for DTC. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] mode Select mode from @ref transfer_start_mode_t. + */ + fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode); + + /** Stop transfer in software. The transfer will stop after completion of the current transfer. + * @note Not supported for DTC. + * @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT. + * @warning Only works if no peripheral event is chosen as the DMAC activation source. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl); + + /** Provides information about this transfer. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[out] p_properties Driver specific information. + */ + fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties); + + /** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl); + + /** To update next transfer information without interruption during transfer. + * Allow further transfer continuation. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. + * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. + * @param[in] num_transfers Transfer length in normal mode or block mode. + */ + fsp_err_t (* reload)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, + uint32_t const num_transfers); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(transfer_ctrl_t * const p_ctrl, void (* p_callback)(transfer_callback_args_t *), + void const * const p_context, transfer_callback_args_t * const p_callback_memory); +} transfer_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_transfer_instance +{ + transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + transfer_api_t const * p_api; ///< Pointer to the API structure for this instance +} transfer_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup TRANSFER_API) + **********************************************************************************************************************/ diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/api/r_uart_api.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/api/r_uart_api.h new file mode 100644 index 00000000000..23585bd3903 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/api/r_uart_api.h @@ -0,0 +1,268 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup UART_API UART Interface + * @brief Interface for UART communications. + * + * @section UART_INTERFACE_SUMMARY Summary + * The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features: + * - Full-duplex UART communication + * - Interrupt driven transmit/receive processing + * - Callback function with returned event code + * - Runtime baud-rate change + * - Hardware resource locking during a transaction + * - CTS/RTS hardware flow control support (with an associated IOPORT pin) + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_UART_API_H +#define R_UART_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** UART Event codes */ +#ifndef BSP_OVERRIDE_UART_EVENT_T +typedef enum e_sf_event +{ + UART_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event + UART_EVENT_TX_COMPLETE = (1UL << 1), ///< Transmit complete event + UART_EVENT_RX_CHAR = (1UL << 2), ///< Character received + UART_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event + UART_EVENT_ERR_FRAMING = (1UL << 4), ///< Mode fault error event + UART_EVENT_ERR_OVERFLOW = (1UL << 5), ///< FIFO Overflow error event + UART_EVENT_BREAK_DETECT = (1UL << 6), ///< Break detect error event + UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data +} uart_event_t; +#endif +#ifndef BSP_OVERRIDE_UART_DATA_BITS_T + +/** UART Data bit length definition */ +typedef enum e_uart_data_bits +{ + UART_DATA_BITS_9 = 0U, ///< Data bits 9-bit + UART_DATA_BITS_8 = 2U, ///< Data bits 8-bit + UART_DATA_BITS_7 = 3U, ///< Data bits 7-bit +} uart_data_bits_t; +#endif +#ifndef BSP_OVERRIDE_UART_PARITY_T + +/** UART Parity definition */ +typedef enum e_uart_parity +{ + UART_PARITY_OFF = 0U, ///< No parity + UART_PARITY_ZERO = 1U, ///< Zero parity + UART_PARITY_EVEN = 2U, ///< Even parity + UART_PARITY_ODD = 3U, ///< Odd parity +} uart_parity_t; +#endif + +/** UART Stop bits definition */ +typedef enum e_uart_stop_bits +{ + UART_STOP_BITS_1 = 0U, ///< Stop bit 1-bit + UART_STOP_BITS_2 = 1U, ///< Stop bits 2-bit +} uart_stop_bits_t; + +/** UART transaction definition */ +typedef enum e_uart_dir +{ + UART_DIR_RX_TX = 3U, ///< Both RX and TX + UART_DIR_RX = 1U, ///< Only RX + UART_DIR_TX = 2U, ///< Only TX +} uart_dir_t; + +/** UART driver specific information */ +typedef struct st_uart_info +{ + /** Maximum bytes that can be written at this time. Only applies if uart_cfg_t::p_transfer_tx is not NULL. */ + uint32_t write_bytes_max; + + /** Maximum bytes that are available to read at one time. Only applies if uart_cfg_t::p_transfer_rx is not NULL. */ + uint32_t read_bytes_max; +} uart_info_t; + +/** UART Callback parameter definition */ +typedef struct st_uart_callback_arg +{ + uint32_t channel; ///< Device channel number + uart_event_t event; ///< Event code + + /** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY, + * UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW. Otherwise unused. */ + uint32_t data; + void const * p_context; ///< Context provided to user during callback +} uart_callback_args_t; + +/** UART Configuration */ +typedef struct st_uart_cfg +{ + /* UART generic configuration */ + uint8_t channel; ///< Select a channel corresponding to the channel number of the hardware. + uart_data_bits_t data_bits; ///< Data bit length (8 or 7 or 9) + uart_parity_t parity; ///< Parity type (none or odd or even) + uart_stop_bits_t stop_bits; ///< Stop bit length (1 or 2) + uint8_t rxi_ipl; ///< Receive interrupt priority + IRQn_Type rxi_irq; ///< Receive interrupt IRQ number + uint8_t txi_ipl; ///< Transmit interrupt priority + IRQn_Type txi_irq; ///< Transmit interrupt IRQ number + uint8_t tei_ipl; ///< Transmit end interrupt priority + IRQn_Type tei_irq; ///< Transmit end interrupt IRQ number + uint8_t eri_ipl; ///< Error interrupt priority + IRQn_Type eri_irq; ///< Error interrupt IRQ number + + /** Optional transfer instance used to receive multiple bytes without interrupts. Set to NULL if unused. + * If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */ + transfer_instance_t const * p_transfer_rx; + + /** Optional transfer instance used to send multiple bytes without interrupts. Set to NULL if unused. + * If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */ + transfer_instance_t const * p_transfer_tx; + + /* Configuration for UART Event processing */ + void (* p_callback)(uart_callback_args_t * p_args); ///< Pointer to callback function + void const * p_context; ///< User defined context passed into callback function + + /* Pointer to UART peripheral specific configuration */ + void const * p_extend; ///< UART hardware dependent configuration +} uart_cfg_t; + +/** UART control block. Allocate an instance specific control block to pass into the UART API calls. + */ +typedef void uart_ctrl_t; + +/** Shared Interface definition for UART */ +typedef struct st_uart_api +{ + /** Open UART device. + * + * @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here. + * @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by + * user. + */ + fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + + /** Read from UART device. The read buffer is used until the read is complete. When a transfer is complete, the + * callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in + * the callback function with event UART_EVENT_RX_CHAR. + * The maximum transfer size is reported by infoGet(). + * + * @param[in] p_ctrl Pointer to the UART control block for the channel. + * @param[in] p_dest Destination address to read data from. + * @param[in] bytes Read data length. + */ + fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); + + /** Write to UART device. The write buffer is used until write is complete. Do not overwrite write buffer + * contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire), + * the callback called with event UART_EVENT_TX_COMPLETE. + * The maximum transfer size is reported by infoGet(). + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_src Source address to write data to. + * @param[in] bytes Write data length. + */ + fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes); + + /** Change baud rate. + * @warning Calling this API aborts any in-progress transmission and disables reception until the new baud + * settings have been applied. + * + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate. + */ + fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info); + + /** Get the driver specific information. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] baudrate Baud rate in bps. + */ + fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info); + + /** + * Abort ongoing transfer. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] communication_to_abort Type of abort request. + */ + fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(uart_ctrl_t * const p_ctrl, void (* p_callback)(uart_callback_args_t *), + void const * const p_context, uart_callback_args_t * const p_callback_memory); + + /** Close UART device. + * + * @param[in] p_ctrl Pointer to the UART control block. + */ + fsp_err_t (* close)(uart_ctrl_t * const p_ctrl); + + /** Stop ongoing read and return the number of bytes remaining in the read. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read. + */ + fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes); +} uart_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_uart_instance +{ + uart_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + uart_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + uart_api_t const * p_api; ///< Pointer to the API structure for this instance +} uart_instance_t; + +/** @} (end defgroup UART_API) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/fsp_common_api.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/fsp_common_api.h new file mode 100644 index 00000000000..6bc678d533a --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/fsp_common_api.h @@ -0,0 +1,394 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef FSP_COMMON_API_H +#define FSP_COMMON_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include + +/* Includes FSP version macros. */ +#include "fsp_version.h" + +/*******************************************************************************************************************//** + * @ingroup RENESAS_COMMON + * @defgroup RENESAS_ERROR_CODES Common Error Codes + * All FSP modules share these common error codes. + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing + * about using this implementation is that it does not take any extra RAM or ROM. */ + +#define FSP_PARAMETER_NOT_USED(p) (void) ((p)) + +/** Determine if a C++ compiler is being used. + * If so, ensure that standard C is used to process the API information. */ +#if defined(__cplusplus) + #define FSP_CPP_HEADER extern "C" { + #define FSP_CPP_FOOTER } +#else + #define FSP_CPP_HEADER + #define FSP_CPP_FOOTER +#endif + +/** FSP Header and Footer definitions */ +#define FSP_HEADER FSP_CPP_HEADER +#define FSP_FOOTER FSP_CPP_FOOTER + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically + * defined on the Secure side. */ +#define FSP_SECURE_ARGUMENT (NULL) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Common error codes */ +typedef enum e_fsp_err +{ + FSP_SUCCESS = 0, + + FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed + FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location + FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter + FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist + FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode + FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API + FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open + FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy + FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h + FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked + FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP + FSP_ERR_OVERFLOW = 12, ///< Hardware overflow + FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow + FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration + FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result + FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason + FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met + FSP_ERR_ABORTED = 18, ///< An operation was aborted + FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled + FSP_ERR_TIMEOUT = 20, ///< Timeout error + FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied + FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied + FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation + FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed + FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed + FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made + FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition + FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU + FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state + FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed + FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed + FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete + FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found + FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback + FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer + FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed + + /* Start of RTOS only error codes */ + FSP_ERR_INTERNAL = 100, ///< Internal error + FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted + + /* Start of UART specific */ + FSP_ERR_FRAMING = 200, ///< Framing error occurs + FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects + FSP_ERR_PARITY = 202, ///< Parity error occurs + FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow + FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue + FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer + FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer + + /* Start of SPI specific */ + FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted. + FSP_ERR_MODE_FAULT = 301, ///< Mode fault error. + FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow. + FSP_ERR_SPI_PARITY = 303, ///< Parity error. + FSP_ERR_OVERRUN = 304, ///< Overrun error. + + /* Start of CGC Specific */ + FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock. + FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first. + FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off + FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off + FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled + FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set + FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active + FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit + FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled + FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out + FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode + + /* Start of FLASH Specific */ + FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode. + FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state + FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz + FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory + FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed + + /* Start of CAC Specific */ + FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate + + /* Start of IIRFA Specific */ + FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity. + + /* Start of GLCD Specific */ + FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock + FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter + FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter + FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found + FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter + FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer + FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register update + FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry + FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting + FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter + + /* Start of JPEG Specific */ + FSP_ERR_JPEG_ERR = 1100, ///< JPEG error + FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected. + FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected. + FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected. + FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected. + FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected. + FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4. + FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS. + FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected. + FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected. + FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default) + FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected. + FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected. + FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected. + FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected. + FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough + FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU + + /* Start of touch panel framework specific */ + FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed + + /* Start of IIRFA specific */ + FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected + FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected + + /* Start of IP specific */ + FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device + FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device + FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device + + /* Start of USB specific */ + FSP_ERR_USB_FAILED = 1500, + FSP_ERR_USB_BUSY = 1501, + FSP_ERR_USB_SIZE_SHORT = 1502, + FSP_ERR_USB_SIZE_OVER = 1503, + FSP_ERR_USB_NOT_OPEN = 1504, + FSP_ERR_USB_NOT_SUSPEND = 1505, + FSP_ERR_USB_PARAMETER = 1506, + + /* Start of Message framework specific */ + FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool + FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool + FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid + FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid + FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many + FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found + FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue + FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue + FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal + FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released + + /* Start of 2DG Driver specific */ + FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering + FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering + + /* Start of ETHER Driver specific */ + FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer. + FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation + FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled + FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty + FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable + FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication + FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active. + + /* Start of ETHER_PHY Driver specific */ + FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up. + FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation + + /* Start of BYTEQ library specific */ + FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data + FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue + + /* Start of CTSU Driver specific */ + FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning. + FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data. + FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning. + FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet. + FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed. + FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed. + FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed. + FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed. + FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed. + FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed. + FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed. + FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed. + FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed. + FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed. + FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed. + FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed. + FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed. + FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed. + + /* Start of SDMMC specific */ + FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize. + FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed. + FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing. + FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed. + FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected. + FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress. + FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error. + + /* Start of FX_IO specific */ + FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed. + FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed. + + /* Start of CAN specific */ + FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available. + FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed. + FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed. + FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress. + FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox. + FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox. + FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun. + FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full. + + /* Start of SF_WIFI Specific */ + FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed. + FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed. + FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed + FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode + FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed. + FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed. + FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point + FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16200 Unknown AT command Error + FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16200 Insufficient parameter + FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16200 Too many parameters + FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16200 Wrong parameter value + FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16200 No result + FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16200 Response buffer overflow + FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16200 Function is not configured + FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16200 NVRAM write failure + FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16200 Retention memory write failure + FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16200 unknown error + + /* Start of SF_CELLULAR Specific */ + FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed. + FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed. + FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed + FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is uptodate + FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed + FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed. + FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state. + FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed + + /* Start of SF_BLE specific */ + FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed + FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed + FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed + FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled + FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled + + /* Start of SF_BLE_ABS specific */ + FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed. + FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found. + + /* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */ + FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function + FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy + FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty + FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index + FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry + FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed + FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened + FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized + FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred + FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter + FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented + FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified + FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred + FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid + FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state + FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened + FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid. + FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed + FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher + FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed + FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input date is illegal. + FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred. + + /* Start of Crypto RSIP specific (0x10100) */ + FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT = 0x10100, ///< Hardware resource is busy + FSP_ERR_CRYPTO_RSIP_FATAL = 0x10101, ///< Hardware fatal error or unexpected return + FSP_ERR_CRYPTO_RSIP_FAIL = 0x10102, ///< Internal error + FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL = 0x10103, ///< Input key type is illegal + FSP_ERR_CRYPTO_RSIP_AUTHENTICATION = 0x10104, ///< Authentication failed + + /* Start of SF_CRYPTO specific */ + FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened + FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error + FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key + FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold + FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode. + FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long. + FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error. + + /** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module. + * Refer to sf_cryoto_err.h for Crypto error codes. + */ + + /* Start of Sensor specific */ + FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid. + FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing. + FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished. + + /* Start of COMMS specific */ + FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open. +} fsp_err_t; + +/** @} */ + +/*********************************************************************************************************************** + * Function prototypes + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/fsp_features.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/fsp_features.h new file mode 100644 index 00000000000..ed531b153d2 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/fsp_features.h @@ -0,0 +1,585 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef FSP_FEATURES_H +#define FSP_FEATURES_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include + +/* Different compiler support. */ +#include "fsp_common_api.h" +#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Available modules. */ +typedef enum e_fsp_ip +{ + FSP_IP_CGC = 1, ///< Clock Generation Circuit + FSP_IP_CLMA = 2, ///< Clock Monitor Circuit + FSP_IP_MSTP = 3, ///< Module Stop + FSP_IP_ICU = 4, ///< Interrupt Control Unit + FSP_IP_BSC = 5, ///< Bus State Contoller + FSP_IP_CKIO = 6, ///< CKIO + FSP_IP_DMAC = 7, ///< DMA Controller + FSP_IP_ELC = 8, ///< Event Link Controller + FSP_IP_IOPORT = 9, ///< I/O Ports + FSP_IP_MTU3 = 10, ///< Multi-Function Timer Pulse Unit + FSP_IP_POE3 = 11, ///< Port Output Enable for MTU3 + FSP_IP_GPT = 12, ///< General PWM Timer + FSP_IP_POEG = 13, ///< Port Output Enable for GPT + FSP_IP_TFU = 14, ///< Arithmetic Unit for Trigonometric Functions + FSP_IP_CMT = 15, ///< Compare Match Timer + FSP_IP_CMTW = 16, ///< Compare Match Timer W + FSP_IP_WDT = 17, ///< Watch Dog Timer + FSP_IP_RTC = 18, ///< Real Time Clock + FSP_IP_ETHSS = 19, ///< Ethernet Subsystem + FSP_IP_GMAC = 20, ///< Ethernet MAC + FSP_IP_ETHSW = 21, ///< Ethernet Switch + FSP_IP_ESC = 22, ///< EtherCAT Slave Controller + FSP_IP_USBHS = 23, ///< USB High Speed + FSP_IP_SCI = 24, ///< Serial Communications Interface + FSP_IP_IIC = 25, ///< I2C Bus Interface + FSP_IP_CANFD = 26, ///< Controller Area Network with Flexible Data Rate + FSP_IP_SPI = 27, ///< Serial Peripheral Interface + FSP_IP_XSPI = 28, ///< expanded Serial Peripheral Interface + FSP_IP_CRC = 29, ///< Cyclic Redundancy Check Calculator + FSP_IP_BSCAN = 30, ///< Boundary Scan + FSP_IP_DSMIF = 31, ///< Delta Sigma Interface + FSP_IP_ADC12 = 32, ///< 12-Bit A/D Converter + FSP_IP_TSU = 33, ///< Temperature Sensor + FSP_IP_DOC = 34, ///< Data Operation Circuit + FSP_IP_SYSRAM = 35, ///< System SRAM + FSP_IP_ENCIF = 36, ///< Encoder Interface + FSP_IP_SHOSTIF = 37, ///< Serial Host Interface + FSP_IP_AFMT = 38, ///< A-Format + FSP_IP_HDSL = 39, ///< HIPERFACE DSL + FSP_IP_BISS = 40, ///< BiSS-C + FSP_IP_ENDAT = 41, ///< EnDat 2.2 +} fsp_ip_t; + +/** Signals that can be mapped to an interrupt. */ +typedef enum e_fsp_signal +{ + FSP_SIGNAL_INTCPU0 = (0), ///< Software interrupt 0 + FSP_SIGNAL_INTCPU1 = (1), ///< Software interrupt 1 + FSP_SIGNAL_INTCPU2 = (2), ///< Software interrupt 2 + FSP_SIGNAL_INTCPU3 = (3), ///< Software interrupt 3 + FSP_SIGNAL_INTCPU4 = (4), ///< Software interrupt 4 + FSP_SIGNAL_INTCPU5 = (5), ///< Software interrupt 5 + FSP_SIGNAL_IRQ0 = (6), ///< External pin interrupt 0 + FSP_SIGNAL_IRQ1 = (7), ///< External pin interrupt 1 + FSP_SIGNAL_IRQ2 = (8), ///< External pin interrupt 2 + FSP_SIGNAL_IRQ3 = (9), ///< External pin interrupt 3 + FSP_SIGNAL_IRQ4 = (10), ///< External pin interrupt 4 + FSP_SIGNAL_IRQ5 = (11), ///< External pin interrupt 5 + FSP_SIGNAL_IRQ6 = (12), ///< External pin interrupt 6 + FSP_SIGNAL_IRQ7 = (13), ///< External pin interrupt 7 + FSP_SIGNAL_IRQ8 = (14), ///< External pin interrupt 8 + FSP_SIGNAL_IRQ9 = (15), ///< External pin interrupt 9 + FSP_SIGNAL_IRQ10 = (16), ///< External pin interrupt 10 + FSP_SIGNAL_IRQ11 = (17), ///< External pin interrupt 11 + FSP_SIGNAL_IRQ12 = (18), ///< External pin interrupt 12 + FSP_SIGNAL_IRQ13 = (19), ///< External pin interrupt 13 + FSP_SIGNAL_BSC_CMI = (20), ///< Refresh compare match interrupt + FSP_SIGNAL_DMAC0_INT0 = (21), ///< DMAC0 transfer completion 0 + FSP_SIGNAL_DMAC0_INT1 = (22), ///< DMAC0 transfer completion 1 + FSP_SIGNAL_DMAC0_INT2 = (23), ///< DMAC0 transfer completion 2 + FSP_SIGNAL_DMAC0_INT3 = (24), ///< DMAC0 transfer completion 3 + FSP_SIGNAL_DMAC0_INT4 = (25), ///< DMAC0 transfer completion 4 + FSP_SIGNAL_DMAC0_INT5 = (26), ///< DMAC0 transfer completion 5 + FSP_SIGNAL_DMAC0_INT6 = (27), ///< DMAC0 transfer completion 6 + FSP_SIGNAL_DMAC0_INT7 = (28), ///< DMAC0 transfer completion 7 + FSP_SIGNAL_DMAC0_INT8 = (29), ///< DMAC0 transfer completion 8 + FSP_SIGNAL_DMAC0_INT9 = (30), ///< DMAC0 transfer completion 9 + FSP_SIGNAL_DMAC0_INT10 = (31), ///< DMAC0 transfer completion 10 + FSP_SIGNAL_DMAC0_INT11 = (32), ///< DMAC0 transfer completion 11 + FSP_SIGNAL_DMAC0_INT12 = (33), ///< DMAC0 transfer completion 12 + FSP_SIGNAL_DMAC0_INT13 = (34), ///< DMAC0 transfer completion 13 + FSP_SIGNAL_DMAC0_INT14 = (35), ///< DMAC0 transfer completion 14 + FSP_SIGNAL_DMAC0_INT15 = (36), ///< DMAC0 transfer completion 15 + FSP_SIGNAL_DMAC1_INT0 = (37), ///< DMAC1 transfer completion 0 + FSP_SIGNAL_DMAC1_INT1 = (38), ///< DMAC1 transfer completion 1 + FSP_SIGNAL_DMAC1_INT2 = (39), ///< DMAC1 transfer completion 2 + FSP_SIGNAL_DMAC1_INT3 = (40), ///< DMAC1 transfer completion 3 + FSP_SIGNAL_DMAC1_INT4 = (41), ///< DMAC1 transfer completion 4 + FSP_SIGNAL_DMAC1_INT5 = (42), ///< DMAC1 transfer completion 5 + FSP_SIGNAL_DMAC1_INT6 = (43), ///< DMAC1 transfer completion 6 + FSP_SIGNAL_DMAC1_INT7 = (44), ///< DMAC1 transfer completion 7 + FSP_SIGNAL_DMAC1_INT8 = (45), ///< DMAC1 transfer completion 8 + FSP_SIGNAL_DMAC1_INT9 = (46), ///< DMAC1 transfer completion 9 + FSP_SIGNAL_DMAC1_INT10 = (47), ///< DMAC1 transfer completion 10 + FSP_SIGNAL_DMAC1_INT11 = (48), ///< DMAC1 transfer completion 11 + FSP_SIGNAL_DMAC1_INT12 = (49), ///< DMAC1 transfer completion 12 + FSP_SIGNAL_DMAC1_INT13 = (50), ///< DMAC1 transfer completion 13 + FSP_SIGNAL_DMAC1_INT14 = (51), ///< DMAC1 transfer completion 14 + FSP_SIGNAL_DMAC1_INT15 = (52), ///< DMAC1 transfer completion 15 + FSP_SIGNAL_CMT0_CMI = (53), ///< CMT0 Compare match + FSP_SIGNAL_CMT1_CMI = (54), ///< CMT1 Compare match + FSP_SIGNAL_CMT2_CMI = (55), ///< CMT2 Compare match + FSP_SIGNAL_CMT3_CMI = (56), ///< CMT3 Compare match + FSP_SIGNAL_CMT4_CMI = (57), ///< CMT4 Compare match + FSP_SIGNAL_CMT5_CMI = (58), ///< CMT5 Compare match + FSP_SIGNAL_CMTW0_CMWI = (59), ///< CMTW0 Compare match + FSP_SIGNAL_CMTW0_IC0I = (60), ///< CMTW0 Input capture of register 0 + FSP_SIGNAL_CMTW0_IC1I = (61), ///< CMTW0 Input capture of register 1 + FSP_SIGNAL_CMTW0_OC0I = (62), ///< CMTW0 Output compare of register 0 + FSP_SIGNAL_CMTW0_OC1I = (63), ///< CMTW0 Output compare of register 1 + FSP_SIGNAL_CMTW1_CMWI = (64), ///< CMTW1 Compare match + FSP_SIGNAL_CMTW1_IC0I = (65), ///< CMTW1 Input capture of register 0 + FSP_SIGNAL_CMTW1_IC1I = (66), ///< CMTW1 Input capture of register 1 + FSP_SIGNAL_CMTW1_OC0I = (67), ///< CMTW1 Output compare of register 0 + FSP_SIGNAL_CMTW1_OC1I = (68), ///< CMTW1 Output compare of register 1 + FSP_SIGNAL_TGIA0 = (69), ///< MTU0.TGRA input capture/compare match + FSP_SIGNAL_TGIB0 = (70), ///< MTU0.TGRB input capture/compare match + FSP_SIGNAL_TGIC0 = (71), ///< MTU0.TGRC input capture/compare match + FSP_SIGNAL_TGID0 = (72), ///< MTU0.TGRD input capture/compare match + FSP_SIGNAL_TCIV0 = (73), ///< MTU0.TCNT overflow + FSP_SIGNAL_TGIE0 = (74), ///< MTU0.TGRE compare match + FSP_SIGNAL_TGIF0 = (75), ///< MTU0.TGRF compare match + FSP_SIGNAL_TGIA1 = (76), ///< MTU1.TGRA input capture/compare match + FSP_SIGNAL_TGIB1 = (77), ///< MTU1.TGRB input capture/compare match + FSP_SIGNAL_TCIV1 = (78), ///< MTU1.TCNT overflow + FSP_SIGNAL_TCIU1 = (79), ///< MTU1.TCNT underflow + FSP_SIGNAL_TGIA2 = (80), ///< MTU2.TGRA input capture/compare match + FSP_SIGNAL_TGIB2 = (81), ///< MTU2.TGRB input capture/compare match + FSP_SIGNAL_TCIV2 = (82), ///< MTU2.TCNT overflow + FSP_SIGNAL_TCIU2 = (83), ///< MTU2.TCNT underflow + FSP_SIGNAL_TGIA3 = (84), ///< MTU3.TGRA input capture/compare match + FSP_SIGNAL_TGIB3 = (85), ///< MTU3.TGRB input capture/compare match + FSP_SIGNAL_TGIC3 = (86), ///< MTU3.TGRC input capture/compare match + FSP_SIGNAL_TGID3 = (87), ///< MTU3.TGRD input capture/compare match + FSP_SIGNAL_TCIV3 = (88), ///< MTU3.TCNT overflow + FSP_SIGNAL_TGIA4 = (89), ///< MTU4.TGRA input capture/compare match + FSP_SIGNAL_TGIB4 = (90), ///< MTU4.TGRB input capture/compare match + FSP_SIGNAL_TGIC4 = (91), ///< MTU4.TGRC input capture/compare match + FSP_SIGNAL_TGID4 = (92), ///< MTU4.TGRD input capture/compare match + FSP_SIGNAL_TCIV4 = (93), ///< MTU4.TCNT overflow/underflow + FSP_SIGNAL_TGIU5 = (94), ///< MTU5.TGRU input capture/compare match + FSP_SIGNAL_TGIV5 = (95), ///< MTU5.TGRV input capture/compare match + FSP_SIGNAL_TGIW5 = (96), ///< MTU5.TGRW input capture/compare match + FSP_SIGNAL_TGIA6 = (97), ///< MTU6.TGRA input capture/compare match + FSP_SIGNAL_TGIB6 = (98), ///< MTU6.TGRB input capture/compare match + FSP_SIGNAL_TGIC6 = (99), ///< MTU6.TGRC input capture/compare match + FSP_SIGNAL_TGID6 = (100), ///< MTU6.TGRD input capture/compare match + FSP_SIGNAL_TCIV6 = (101), ///< MTU6.TCNT overflow + FSP_SIGNAL_TGIA7 = (102), ///< MTU7.TGRA input capture/compare match + FSP_SIGNAL_TGIB7 = (103), ///< MTU7.TGRB input capture/compare match + FSP_SIGNAL_TGIC7 = (104), ///< MTU7.TGRC input capture/compare match + FSP_SIGNAL_TGID7 = (105), ///< MTU7.TGRD input capture/compare match + FSP_SIGNAL_TCIV7 = (106), ///< MTU7.TCNT overflow/underflow + FSP_SIGNAL_TGIA8 = (107), ///< MTU8.TGRA input capture/compare match + FSP_SIGNAL_TGIB8 = (108), ///< MTU8.TGRB input capture/compare match + FSP_SIGNAL_TGIC8 = (109), ///< MTU8.TGRC input capture/compare match + FSP_SIGNAL_TGID8 = (110), ///< MTU8.TGRD input capture/compare match + FSP_SIGNAL_TCIV8 = (111), ///< MTU8.TCNT overflow + FSP_SIGNAL_OEI1 = (112), ///< Output enable interrupt 1 + FSP_SIGNAL_OEI2 = (113), ///< Output enable interrupt 2 + FSP_SIGNAL_OEI3 = (114), ///< Output enable interrupt 3 + FSP_SIGNAL_OEI4 = (115), ///< Output enable interrupt 4 + FSP_SIGNAL_GPT0_CCMPA = (116), ///< GPT0 GTCCRA input capture/compare match + FSP_SIGNAL_GPT0_CCMPB = (117), ///< GPT0 GTCCRB input capture/compare match + FSP_SIGNAL_GPT0_CMPC = (118), ///< GPT0 GTCCRC compare match + FSP_SIGNAL_GPT0_CMPD = (119), ///< GPT0 GTCCRD compare match + FSP_SIGNAL_GPT0_CMPE = (120), ///< GPT0 GTCCRE compare match + FSP_SIGNAL_GPT0_CMPF = (121), ///< GPT0 GTCCRF compare match + FSP_SIGNAL_GPT0_OVF = (122), ///< GPT0 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT0_UDF = (123), ///< GPT0 GTCNT underflow + FSP_SIGNAL_GPT0_DTE = (124), ///< GPT0 Dead time error + FSP_SIGNAL_GPT1_CCMPA = (125), ///< GPT1 GTCCRA input capture/compare match + FSP_SIGNAL_GPT1_CCMPB = (126), ///< GPT1 GTCCRB input capture/compare match + FSP_SIGNAL_GPT1_CMPC = (127), ///< GPT1 GTCCRC compare match + FSP_SIGNAL_GPT1_CMPD = (128), ///< GPT1 GTCCRD compare match + FSP_SIGNAL_GPT1_CMPE = (129), ///< GPT1 GTCCRE compare match + FSP_SIGNAL_GPT1_CMPF = (130), ///< GPT1 GTCCRF compare match + FSP_SIGNAL_GPT1_OVF = (131), ///< GPT1 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT1_UDF = (132), ///< GPT1 GTCNT underflow + FSP_SIGNAL_GPT1_DTE = (133), ///< GPT1 Dead time error + FSP_SIGNAL_GPT2_CCMPA = (134), ///< GPT2 GTCCRA input capture/compare match + FSP_SIGNAL_GPT2_CCMPB = (135), ///< GPT2 GTCCRB input capture/compare match + FSP_SIGNAL_GPT2_CMPC = (136), ///< GPT2 GTCCRC compare match + FSP_SIGNAL_GPT2_CMPD = (137), ///< GPT2 GTCCRD compare match + FSP_SIGNAL_GPT2_CMPE = (138), ///< GPT2 GTCCRE compare match + FSP_SIGNAL_GPT2_CMPF = (139), ///< GPT2 GTCCRF compare match + FSP_SIGNAL_GPT2_OVF = (140), ///< GPT2 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT2_UDF = (141), ///< GPT2 GTCNT underflow + FSP_SIGNAL_GPT2_DTE = (142), ///< GPT2 Dead time error + FSP_SIGNAL_GPT3_CCMPA = (143), ///< GPT3 GTCCRA input capture/compare match + FSP_SIGNAL_GPT3_CCMPB = (144), ///< GPT3 GTCCRB input capture/compare match + FSP_SIGNAL_GPT3_CMPC = (145), ///< GPT3 GTCCRC compare match + FSP_SIGNAL_GPT3_CMPD = (146), ///< GPT3 GTCCRD compare match + FSP_SIGNAL_GPT3_CMPE = (147), ///< GPT3 GTCCRE compare match + FSP_SIGNAL_GPT3_CMPF = (148), ///< GPT3 GTCCRF compare match + FSP_SIGNAL_GPT3_OVF = (149), ///< GPT3 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT3_UDF = (150), ///< GPT3 GTCNT underflow + FSP_SIGNAL_GPT3_DTE = (151), ///< GPT3 Dead time error + FSP_SIGNAL_GPT4_CCMPA = (152), ///< GPT4 GTCCRA input capture/compare match + FSP_SIGNAL_GPT4_CCMPB = (153), ///< GPT4 GTCCRB input capture/compare match + FSP_SIGNAL_GPT4_CMPC = (154), ///< GPT4 GTCCRC compare match + FSP_SIGNAL_GPT4_CMPD = (155), ///< GPT4 GTCCRD compare match + FSP_SIGNAL_GPT4_CMPE = (156), ///< GPT4 GTCCRE compare match + FSP_SIGNAL_GPT4_CMPF = (157), ///< GPT4 GTCCRF compare match + FSP_SIGNAL_GPT4_OVF = (158), ///< GPT4 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT4_UDF = (159), ///< GPT4 GTCNT underflow + FSP_SIGNAL_GPT4_DTE = (160), ///< GPT4 Dead time error + FSP_SIGNAL_GPT5_CCMPA = (161), ///< GPT5 GTCCRA input capture/compare match + FSP_SIGNAL_GPT5_CCMPB = (162), ///< GPT5 GTCCRB input capture/compare match + FSP_SIGNAL_GPT5_CMPC = (163), ///< GPT5 GTCCRC compare match + FSP_SIGNAL_GPT5_CMPD = (164), ///< GPT5 GTCCRD compare match + FSP_SIGNAL_GPT5_CMPE = (165), ///< GPT5 GTCCRE compare match + FSP_SIGNAL_GPT5_CMPF = (166), ///< GPT5 GTCCRF compare match + FSP_SIGNAL_GPT5_OVF = (167), ///< GPT5 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT5_UDF = (168), ///< GPT5 GTCNT underflow + FSP_SIGNAL_GPT5_DTE = (169), ///< GPT5 Dead time error + FSP_SIGNAL_GPT6_CCMPA = (170), ///< GPT6 GTCCRA input capture/compare match + FSP_SIGNAL_GPT6_CCMPB = (171), ///< GPT6 GTCCRB input capture/compare match + FSP_SIGNAL_GPT6_CMPC = (172), ///< GPT6 GTCCRC compare match + FSP_SIGNAL_GPT6_CMPD = (173), ///< GPT6 GTCCRD compare match + FSP_SIGNAL_GPT6_CMPE = (174), ///< GPT6 GTCCRE compare match + FSP_SIGNAL_GPT6_CMPF = (175), ///< GPT6 GTCCRF compare match + FSP_SIGNAL_GPT6_OVF = (176), ///< GPT6 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT6_UDF = (177), ///< GPT6 GTCNT underflow + FSP_SIGNAL_GPT6_DTE = (178), ///< GPT6 Dead time error + FSP_SIGNAL_GPT7_CCMPA = (179), ///< GPT7 GTCCRA input capture/compare match + FSP_SIGNAL_GPT7_CCMPB = (180), ///< GPT7 GTCCRB input capture/compare match + FSP_SIGNAL_GPT7_CMPC = (181), ///< GPT7 GTCCRC compare match + FSP_SIGNAL_GPT7_CMPD = (182), ///< GPT7 GTCCRD compare match + FSP_SIGNAL_GPT7_CMPE = (183), ///< GPT7 GTCCRE compare match + FSP_SIGNAL_GPT7_CMPF = (184), ///< GPT7 GTCCRF compare match + FSP_SIGNAL_GPT7_OVF = (185), ///< GPT7 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT7_UDF = (186), ///< GPT7 GTCNT underflow + FSP_SIGNAL_GPT7_DTE = (187), ///< GPT7 Dead time error + FSP_SIGNAL_GPT8_CCMPA = (188), ///< GPT8 GTCCRA input capture/compare match + FSP_SIGNAL_GPT8_CCMPB = (189), ///< GPT8 GTCCRB input capture/compare match + FSP_SIGNAL_GPT8_CMPC = (190), ///< GPT8 GTCCRC compare match + FSP_SIGNAL_GPT8_CMPD = (191), ///< GPT8 GTCCRD compare match + FSP_SIGNAL_GPT8_CMPE = (192), ///< GPT8 GTCCRE compare match + FSP_SIGNAL_GPT8_CMPF = (193), ///< GPT8 GTCCRF compare match + FSP_SIGNAL_GPT8_OVF = (194), ///< GPT8 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT8_UDF = (195), ///< GPT8 GTCNT underflow + FSP_SIGNAL_GPT8_DTE = (196), ///< GPT8 Dead time error + FSP_SIGNAL_GPT9_CCMPA = (197), ///< GPT9 GTCCRA input capture/compare match + FSP_SIGNAL_GPT9_CCMPB = (198), ///< GPT9 GTCCRB input capture/compare match + FSP_SIGNAL_GPT9_CMPC = (199), ///< GPT9 GTCCRC compare match + FSP_SIGNAL_GPT9_CMPD = (200), ///< GPT9 GTCCRD compare match + FSP_SIGNAL_GPT9_CMPE = (201), ///< GPT9 GTCCRE compare match + FSP_SIGNAL_GPT9_CMPF = (202), ///< GPT9 GTCCRF compare match + FSP_SIGNAL_GPT9_OVF = (203), ///< GPT9 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT9_UDF = (204), ///< GPT9 GTCNT underflow + FSP_SIGNAL_GPT9_DTE = (205), ///< GPT9 Dead time error + FSP_SIGNAL_GPT10_CCMPA = (206), ///< GPT10 GTCCRA input capture/compare match + FSP_SIGNAL_GPT10_CCMPB = (207), ///< GPT10 GTCCRB input capture/compare match + FSP_SIGNAL_GPT10_CMPC = (208), ///< GPT10 GTCCRC compare match + FSP_SIGNAL_GPT10_CMPD = (209), ///< GPT10 GTCCRD compare match + FSP_SIGNAL_GPT10_CMPE = (210), ///< GPT10 GTCCRE compare match + FSP_SIGNAL_GPT10_CMPF = (211), ///< GPT10 GTCCRF compare match + FSP_SIGNAL_GPT10_OVF = (212), ///< GPT10 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT10_UDF = (213), ///< GPT10 GTCNT underflow + FSP_SIGNAL_GPT10_DTE = (214), ///< GPT10 Dead time error + FSP_SIGNAL_GPT11_CCMPA = (215), ///< GPT11 GTCCRA input capture/compare match + FSP_SIGNAL_GPT11_CCMPB = (216), ///< GPT11 GTCCRB input capture/compare match + FSP_SIGNAL_GPT11_CMPC = (217), ///< GPT11 GTCCRC compare match + FSP_SIGNAL_GPT11_CMPD = (218), ///< GPT11 GTCCRD compare match + FSP_SIGNAL_GPT11_CMPE = (219), ///< GPT11 GTCCRE compare match + FSP_SIGNAL_GPT11_CMPF = (220), ///< GPT11 GTCCRF compare match + FSP_SIGNAL_GPT11_OVF = (221), ///< GPT11 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT11_UDF = (222), ///< GPT11 GTCNT underflow + FSP_SIGNAL_GPT11_DTE = (223), ///< GPT11 Dead time error + FSP_SIGNAL_GPT12_CCMPA = (224), ///< GPT12 GTCCRA input capture/compare match + FSP_SIGNAL_GPT12_CCMPB = (225), ///< GPT12 GTCCRB input capture/compare match + FSP_SIGNAL_GPT12_CMPC = (226), ///< GPT12 GTCCRC compare match + FSP_SIGNAL_GPT12_CMPD = (227), ///< GPT12 GTCCRD compare match + FSP_SIGNAL_GPT12_CMPE = (228), ///< GPT12 GTCCRE compare match + FSP_SIGNAL_GPT12_CMPF = (229), ///< GPT12 GTCCRF compare match + FSP_SIGNAL_GPT12_OVF = (230), ///< GPT12 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT12_UDF = (231), ///< GPT12 GTCNT underflow + FSP_SIGNAL_GPT12_DTE = (232), ///< GPT12 Dead time error + FSP_SIGNAL_GPT13_CCMPA = (233), ///< GPT13 GTCCRA input capture/compare match + FSP_SIGNAL_GPT13_CCMPB = (234), ///< GPT13 GTCCRB input capture/compare match + FSP_SIGNAL_GPT13_CMPC = (235), ///< GPT13 GTCCRC compare match + FSP_SIGNAL_GPT13_CMPD = (236), ///< GPT13 GTCCRD compare match + FSP_SIGNAL_GPT13_CMPE = (237), ///< GPT13 GTCCRE compare match + FSP_SIGNAL_GPT13_CMPF = (238), ///< GPT13 GTCCRF compare match + FSP_SIGNAL_GPT13_OVF = (239), ///< GPT13 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT13_UDF = (240), ///< GPT13 GTCNT underflow + FSP_SIGNAL_GPT13_DTE = (241), ///< GPT13 Dead time error + FSP_SIGNAL_POEG0_GROUP0 = (242), ///< POEG group A interrupt for channels in LLPP + FSP_SIGNAL_POEG0_GROUP1 = (243), ///< POEG group B interrupt for channels in LLPP + FSP_SIGNAL_POEG0_GROUP2 = (244), ///< POEG group C interrupt for channels in LLPP + FSP_SIGNAL_POEG0_GROUP3 = (245), ///< POEG group D interrupt for channels in LLPP + FSP_SIGNAL_POEG1_GROUP0 = (246), ///< POEG group A interrupt for channels in NONSAFETY + FSP_SIGNAL_POEG1_GROUP1 = (247), ///< POEG group B interrupt for channels in NONSAFETY + FSP_SIGNAL_POEG1_GROUP2 = (248), ///< POEG group C interrupt for channels in NONSAFETY + FSP_SIGNAL_POEG1_GROUP3 = (249), ///< POEG group D interrupt for channels in NONSAFETY + FSP_SIGNAL_GMAC_LPI = (250), ///< GMAC1 energy efficient + FSP_SIGNAL_GMAC_PMT = (251), ///< GMAC1 power management + FSP_SIGNAL_GMAC_SBD = (252), ///< GMAC1 general interrupt + FSP_SIGNAL_ETHSW_INTR = (253), ///< Ethernet Switch interrupt + FSP_SIGNAL_ETHSW_DLR = (254), ///< Ethernet Switch DLR interrupt + FSP_SIGNAL_ETHSW_PRP = (255), ///< Ethernet Switch PRP interrupt + FSP_SIGNAL_ETHSW_IHUB = (256), ///< Ethernet Switch Integrated Hub interrupt + FSP_SIGNAL_ETHSW_PTRN0 = (257), ///< Ethernet Switch RX Pattern Matcher interrupt 0 + FSP_SIGNAL_ETHSW_PTRN1 = (258), ///< Ethernet Switch RX Pattern Matcher interrupt 1 + FSP_SIGNAL_ETHSW_PTRN2 = (259), ///< Ethernet Switch RX Pattern Matcher interrupt 2 + FSP_SIGNAL_ETHSW_PTRN3 = (260), ///< Ethernet Switch RX Pattern Matcher interrupt 3 + FSP_SIGNAL_ETHSW_PTRN4 = (261), ///< Ethernet Switch RX Pattern Matcher interrupt 4 + FSP_SIGNAL_ETHSW_PTRN5 = (262), ///< Ethernet Switch RX Pattern Matcher interrupt 5 + FSP_SIGNAL_ETHSW_PTRN6 = (263), ///< Ethernet Switch RX Pattern Matcher interrupt 6 + FSP_SIGNAL_ETHSW_PTRN7 = (264), ///< Ethernet Switch RX Pattern Matcher interrupt 7 + FSP_SIGNAL_ETHSW_PTRN8 = (265), ///< Ethernet Switch RX Pattern Matcher interrupt 8 + FSP_SIGNAL_ETHSW_PTRN9 = (266), ///< Ethernet Switch RX Pattern Matcher interrupt 9 + FSP_SIGNAL_ETHSW_PTRN10 = (267), ///< Ethernet Switch RX Pattern Matcher interrupt 10 + FSP_SIGNAL_ETHSW_PTRN11 = (268), ///< Ethernet Switch RX Pattern Matcher interrupt 11 + FSP_SIGNAL_ETHSW_PTPOUT0 = (269), ///< Ethernet switch timer pulse output 0 + FSP_SIGNAL_ETHSW_PTPOUT1 = (270), ///< Ethernet switch timer pulse output 1 + FSP_SIGNAL_ETHSW_PTPOUT2 = (271), ///< Ethernet switch timer pulse output 2 + FSP_SIGNAL_ETHSW_PTPOUT3 = (272), ///< Ethernet switch timer pulse output 3 + FSP_SIGNAL_ETHSW_TDMAOUT0 = (273), ///< Ethernet Switch TDMA timer output 0 + FSP_SIGNAL_ETHSW_TDMAOUT1 = (274), ///< Ethernet Switch TDMA timer output 1 + FSP_SIGNAL_ETHSW_TDMAOUT2 = (275), ///< Ethernet Switch TDMA timer output 2 + FSP_SIGNAL_ETHSW_TDMAOUT3 = (276), ///< Ethernet Switch TDMA timer output 3 + FSP_SIGNAL_ESC_SYNC0 = (277), ///< EtherCAT Sync0 interrupt + FSP_SIGNAL_ESC_SYNC1 = (278), ///< EtherCAT Sync1 interrupt + FSP_SIGNAL_ESC_CAT = (279), ///< EtherCAT interrupt + FSP_SIGNAL_ESC_SOF = (280), ///< EtherCAT SOF interrupt + FSP_SIGNAL_ESC_EOF = (281), ///< EtherCAT EOF interrupt + FSP_SIGNAL_ESC_WDT = (282), ///< EtherCAT WDT interrupt + FSP_SIGNAL_ESC_RST = (283), ///< EtherCAT RESET interrupt + FSP_SIGNAL_USB_HI = (284), ///< USB (Host) interrupt + FSP_SIGNAL_USB_FI = (285), ///< USB (Function) interrupt + FSP_SIGNAL_USB_FDMA0 = (286), ///< USB (Function) DMA 0 transmit completion + FSP_SIGNAL_USB_FDMA1 = (287), ///< USB (Function) DMA 1 transmit completion + FSP_SIGNAL_SCI0_ERI = (288), ///< SCI0 Receive error + FSP_SIGNAL_SCI0_RXI = (289), ///< SCI0 Receive data full + FSP_SIGNAL_SCI0_TXI = (290), ///< SCI0 Transmit data empty + FSP_SIGNAL_SCI0_TEI = (291), ///< SCI0 Transmit end + FSP_SIGNAL_SCI1_ERI = (292), ///< SCI1 Receive error + FSP_SIGNAL_SCI1_RXI = (293), ///< SCI1 Receive data full + FSP_SIGNAL_SCI1_TXI = (294), ///< SCI1 Transmit data empty + FSP_SIGNAL_SCI1_TEI = (295), ///< SCI1 Transmit end + FSP_SIGNAL_SCI2_ERI = (296), ///< SCI2 Receive error + FSP_SIGNAL_SCI2_RXI = (297), ///< SCI2 Receive data full + FSP_SIGNAL_SCI2_TXI = (298), ///< SCI2 Transmit data empty + FSP_SIGNAL_SCI2_TEI = (299), ///< SCI2 Transmit end + FSP_SIGNAL_SCI3_ERI = (300), ///< SCI3 Receive error + FSP_SIGNAL_SCI3_RXI = (301), ///< SCI3 Receive data full + FSP_SIGNAL_SCI3_TXI = (302), ///< SCI3 Transmit data empty + FSP_SIGNAL_SCI3_TEI = (303), ///< SCI3 Transmit end + FSP_SIGNAL_SCI4_ERI = (304), ///< SCI4 Receive error + FSP_SIGNAL_SCI4_RXI = (305), ///< SCI4 Receive data full + FSP_SIGNAL_SCI4_TXI = (306), ///< SCI4 Transmit data empty + FSP_SIGNAL_SCI4_TEI = (307), ///< SCI4 Transmit end + FSP_SIGNAL_IIC0_EEI = (308), ///< IIC0 Transfer error or event generation + FSP_SIGNAL_IIC0_RXI = (309), ///< IIC0 Receive data full + FSP_SIGNAL_IIC0_TXI = (310), ///< IIC0 Transmit data empty + FSP_SIGNAL_IIC0_TEI = (311), ///< IIC0 Transmit end + FSP_SIGNAL_IIC1_EEI = (312), ///< IIC1 Transfer error or event generation + FSP_SIGNAL_IIC1_RXI = (313), ///< IIC1 Receive data full + FSP_SIGNAL_IIC1_TXI = (314), ///< IIC1 Transmit data empty + FSP_SIGNAL_IIC1_TEI = (315), ///< IIC1 Transmit end + FSP_SIGNAL_CAN_RXF = (316), ///< CANFD RX FIFO interrupt + FSP_SIGNAL_CAN_GLERR = (317), ///< CANFD Global error interrupt + FSP_SIGNAL_CAN0_TX = (318), ///< CAFND0 Channel TX interrupt + FSP_SIGNAL_CAN0_CHERR = (319), ///< CAFND0 Channel CAN error interrupt + FSP_SIGNAL_CAN0_COMFRX = (320), ///< CAFND0 Common RX FIFO or TXQ interrupt + FSP_SIGNAL_CAN1_TX = (321), ///< CAFND1 Channel TX interrupt + FSP_SIGNAL_CAN1_CHERR = (322), ///< CAFND1 Channel CAN error interrupt + FSP_SIGNAL_CAN1_COMFRX = (323), ///< CAFND1 Common RX FIFO or TXQ interrupt + FSP_SIGNAL_SPI0_SPRI = (324), ///< SPI0 Reception buffer full + FSP_SIGNAL_SPI0_SPTI = (325), ///< SPI0 Transmit buffer empty + FSP_SIGNAL_SPI0_SPII = (326), ///< SPI0 SPI idle + FSP_SIGNAL_SPI0_SPEI = (327), ///< SPI0 errors + FSP_SIGNAL_SPI0_SPCEND = (328), ///< SPI0 Communication complete + FSP_SIGNAL_SPI1_SPRI = (329), ///< SPI1 Reception buffer full + FSP_SIGNAL_SPI1_SPTI = (330), ///< SPI1 Transmit buffer empty + FSP_SIGNAL_SPI1_SPII = (331), ///< SPI1 SPI idle + FSP_SIGNAL_SPI1_SPEI = (332), ///< SPI1 errors + FSP_SIGNAL_SPI1_SPCEND = (333), ///< SPI1 Communication complete + FSP_SIGNAL_SPI2_SPRI = (334), ///< SPI2 Reception buffer full + FSP_SIGNAL_SPI2_SPTI = (335), ///< SPI2 Transmit buffer empty + FSP_SIGNAL_SPI2_SPII = (336), ///< SPI2 SPI idle + FSP_SIGNAL_SPI2_SPEI = (337), ///< SPI2 errors + FSP_SIGNAL_SPI2_SPCEND = (338), ///< SPI2 Communication complete + FSP_SIGNAL_XSPI0_INT = (339), ///< xSPI0 Interrupt + FSP_SIGNAL_XSPI0_INTERR = (340), ///< xSPI0 Error interrupt + FSP_SIGNAL_XSPI1_INT = (341), ///< xSPI1 Interrupt + FSP_SIGNAL_XSPI1_INTERR = (342), ///< xSPI1 Error interrupt + FSP_SIGNAL_DSMIF0_CDRUI = (343), ///< DSMIF0 current data register update (ORed ch0 to ch2) + FSP_SIGNAL_DSMIF1_CDRUI = (344), ///< DSMIF1 current data register update (ORed ch3 to ch5) + FSP_SIGNAL_ADC0_ADI = (345), ///< ADC0 A/D scan end interrupt + FSP_SIGNAL_ADC0_GBADI = (346), ///< ADC0 A/D scan end interrupt for Group B + FSP_SIGNAL_ADC0_GCADI = (347), ///< ADC0 A/D scan end interrupt for Group C + FSP_SIGNAL_ADC0_CMPAI = (348), ///< ADC0 Window A compare match + FSP_SIGNAL_ADC0_CMPBI = (349), ///< ADC0 Window B compare match + FSP_SIGNAL_ADC1_ADI = (350), ///< ADC1 A/D scan end interrupt + FSP_SIGNAL_ADC1_GBADI = (351), ///< ADC1 A/D scan end interrupt for Group B + FSP_SIGNAL_ADC1_GCADI = (352), ///< ADC1 A/D scan end interrupt for Group C + FSP_SIGNAL_ADC1_CMPAI = (353), ///< ADC1 Window A compare match + FSP_SIGNAL_ADC1_CMPBI = (354), ///< ADC1 Window B compare match + FSP_SIGNAL_ENCIF_INT0 = (372), ///< ENCIF CH0 Interrupt A + FSP_SIGNAL_ENCIF_INT1 = (373), ///< ENCIF CH0 Interrupt B + FSP_SIGNAL_ENCIF_INT2 = (374), ///< ENCIF CH0 OUTPUT FIFO Interrupt + FSP_SIGNAL_ENCIF_INT3 = (375), ///< ENCIF CH0 INPUT FIFO Interrupt + FSP_SIGNAL_ENCIF_INT4 = (376), ///< ENCIF CH1 Interrupt A + FSP_SIGNAL_ENCIF_INT5 = (377), ///< ENCIF CH1 Interrupt B + FSP_SIGNAL_ENCIF_INT6 = (378), ///< ENCIF CH1 OUTPUT FIFO Interrupt + FSP_SIGNAL_ENCIF_INT7 = (379), ///< ENCIF CH1 INPUT FIFO Interrupt + FSP_SIGNAL_CPU0_ERR0 = (384), ///< Cortex-R52 CPU0 error event 0 + FSP_SIGNAL_CPU0_ERR1 = (385), ///< Cortex-R52 CPU0 error event 1 + FSP_SIGNAL_CPU1_ERR0 = (386), ///< Cortex-R52 CPU1 error event 0 + FSP_SIGNAL_CPU1_ERR1 = (387), ///< Cortex-R52 CPU1 error event 1 + FSP_SIGNAL_PERI_ERR0 = (388), ///< Peripherals error event 0 + FSP_SIGNAL_PERI_ERR1 = (389), ///< Peripherals error event 1 + FSP_SIGNAL_INTCPU6 = (392), ///< Software interrupt 6 + FSP_SIGNAL_INTCPU7 = (393), ///< Software interrupt 7 + FSP_SIGNAL_IRQ14 = (394), ///< External pin interrupt 14 + FSP_SIGNAL_IRQ15 = (395), ///< External pin interrupt 15 + FSP_SIGNAL_GPT14_CCMPA = (396), ///< GPT14 GTCCRA input capture/compare match + FSP_SIGNAL_GPT14_CCMPB = (397), ///< GPT14 GTCCRB input capture/compare match + FSP_SIGNAL_GPT14_CMPC = (398), ///< GPT14 GTCCRC compare match + FSP_SIGNAL_GPT14_CMPD = (399), ///< GPT14 GTCCRD compare match + FSP_SIGNAL_GPT14_CMPE = (400), ///< GPT14 GTCCRE compare match + FSP_SIGNAL_GPT14_CMPF = (401), ///< GPT14 GTCCRF compare match + FSP_SIGNAL_GPT14_OVF = (402), ///< GPT14 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT14_UDF = (403), ///< GPT14 GTCNT underflow + FSP_SIGNAL_GPT15_CCMPA = (404), ///< GPT15 GTCCRA input capture/compare match + FSP_SIGNAL_GPT15_CCMPB = (405), ///< GPT15 GTCCRB input capture/compare match + FSP_SIGNAL_GPT15_CMPC = (406), ///< GPT15 GTCCRC compare match + FSP_SIGNAL_GPT15_CMPD = (407), ///< GPT15 GTCCRD compare match + FSP_SIGNAL_GPT15_CMPE = (408), ///< GPT15 GTCCRE compare match + FSP_SIGNAL_GPT15_CMPF = (409), ///< GPT15 GTCCRF compare match + FSP_SIGNAL_GPT15_OVF = (410), ///< GPT15 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT15_UDF = (411), ///< GPT15 GTCNT underflow + FSP_SIGNAL_GPT16_CCMPA = (412), ///< GPT16 GTCCRA input capture/compare match + FSP_SIGNAL_GPT16_CCMPB = (413), ///< GPT16 GTCCRB input capture/compare match + FSP_SIGNAL_GPT16_CMPC = (414), ///< GPT16 GTCCRC compare match + FSP_SIGNAL_GPT16_CMPD = (415), ///< GPT16 GTCCRD compare match + FSP_SIGNAL_GPT16_CMPE = (416), ///< GPT16 GTCCRE compare match + FSP_SIGNAL_GPT16_CMPF = (417), ///< GPT16 GTCCRF compare match + FSP_SIGNAL_GPT16_OVF = (418), ///< GPT16 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT16_UDF = (419), ///< GPT16 GTCNT underflow + FSP_SIGNAL_GPT17_CCMPA = (420), ///< GPT17 GTCCRA input capture/compare match + FSP_SIGNAL_GPT17_CCMPB = (421), ///< GPT17 GTCCRB input capture/compare match + FSP_SIGNAL_GPT17_CMPC = (422), ///< GPT17 GTCCRC compare match + FSP_SIGNAL_GPT17_CMPD = (423), ///< GPT17 GTCCRD compare match + FSP_SIGNAL_GPT17_CMPE = (424), ///< GPT17 GTCCRE compare match + FSP_SIGNAL_GPT17_CMPF = (425), ///< GPT17 GTCCRF compare match + FSP_SIGNAL_GPT17_OVF = (426), ///< GPT17 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT17_UDF = (427), ///< GPT17 GTCNT underflow + FSP_SIGNAL_POEG2_GROUP0 = (428), ///< POEG group A interrupt for channels in SAFETY + FSP_SIGNAL_POEG2_GROUP1 = (429), ///< POEG group B interrupt for channels in SAFETY + FSP_SIGNAL_POEG2_GROUP2 = (430), ///< POEG group C interrupt for channels in SAFETY + FSP_SIGNAL_POEG2_GROUP3 = (431), ///< POEG group D interrupt for channels in SAFETY + FSP_SIGNAL_RTC_ALM = (432), ///< Alarm interrupt + FSP_SIGNAL_RTC_1S = (433), ///< 1 second interrupt + FSP_SIGNAL_RTC_PRD = (434), ///< Fixed interval interrupt + FSP_SIGNAL_SCI5_ERI = (435), ///< SCI5 Receive error + FSP_SIGNAL_SCI5_RXI = (436), ///< SCI5 Receive data full + FSP_SIGNAL_SCI5_TXI = (437), ///< SCI5 Transmit data empty + FSP_SIGNAL_SCI5_TEI = (438), ///< SCI5 Transmit end + FSP_SIGNAL_IIC2_EEI = (439), ///< IIC2 Transfer error or event generation + FSP_SIGNAL_IIC2_RXI = (440), ///< IIC2 Receive data full + FSP_SIGNAL_IIC2_TXI = (441), ///< IIC2 Transmit data empty + FSP_SIGNAL_IIC2_TEI = (442), ///< IIC2 Transmit end + FSP_SIGNAL_SPI3_SPRI = (443), ///< SPI3 Reception buffer full + FSP_SIGNAL_SPI3_SPTI = (444), ///< SPI3 Transmit buffer empty + FSP_SIGNAL_SPI3_SPII = (445), ///< SPI3 SPI idle + FSP_SIGNAL_SPI3_SPEI = (446), ///< SPI3 errors + FSP_SIGNAL_SPI3_SPCEND = (447), ///< SPI3 Communication complete + FSP_SIGNAL_DREQ = (448), ///< External DMA request + FSP_SIGNAL_CAN_RF_DMAREQ0 = (449), ///< CAFND RX FIFO 0 DMA request + FSP_SIGNAL_CAN_RF_DMAREQ1 = (450), ///< CAFND RX FIFO 1 DMA request + FSP_SIGNAL_CAN_RF_DMAREQ2 = (451), ///< CAFND RX FIFO 2 DMA request + FSP_SIGNAL_CAN_RF_DMAREQ3 = (452), ///< CAFND RX FIFO 3 DMA request + FSP_SIGNAL_CAN_RF_DMAREQ4 = (453), ///< CAFND RX FIFO 4 DMA request + FSP_SIGNAL_CAN_RF_DMAREQ5 = (454), ///< CAFND RX FIFO 5 DMA request + FSP_SIGNAL_CAN_RF_DMAREQ6 = (455), ///< CAFND RX FIFO 6 DMA request + FSP_SIGNAL_CAN_RF_DMAREQ7 = (456), ///< CAFND RX FIFO 7 DMA request + FSP_SIGNAL_CAN0_CF_DMAREQ = (457), ///< CAFND0 First common FIFO DMA request + FSP_SIGNAL_CAN1_CF_DMAREQ = (458), ///< CAFND1 First common FIFO DMA request + FSP_SIGNAL_ADC0_WCMPM = (459), ///< ADC0 compare match + FSP_SIGNAL_ADC0_WCMPUM = (460), ///< ADC0 compare mismatch + FSP_SIGNAL_ADC1_WCMPM = (461), ///< ADC1 compare match + FSP_SIGNAL_ADC1_WCMPUM = (462), ///< ADC1 compare mismatch + FSP_SIGNAL_TCIV4_OF = (463), ///< MTU4.TCNT overflow + FSP_SIGNAL_TCIV4_UF = (464), ///< MTU4.TCNT underflow + FSP_SIGNAL_TCIV7_OF = (465), ///< MTU7.TCNT overflow + FSP_SIGNAL_TCIV7_UF = (466), ///< MTU7.TCNT underflow + FSP_SIGNAL_IOPORT_GROUP1 = (467), ///< Input edge detection of input port group 1 + FSP_SIGNAL_IOPORT_GROUP2 = (468), ///< Input edge detection of input port group 2 + FSP_SIGNAL_IOPORT_SINGLE0 = (469), ///< Input edge detection of single input port 0 + FSP_SIGNAL_IOPORT_SINGLE1 = (470), ///< Input edge detection of single input port 1 + FSP_SIGNAL_IOPORT_SINGLE2 = (471), ///< Input edge detection of single input port 2 + FSP_SIGNAL_IOPORT_SINGLE3 = (472), ///< Input edge detection of single input port 3 + FSP_SIGNAL_GPT0_ADTRGA = (473), ///< GPT0 GTADTRA compare match + FSP_SIGNAL_GPT0_ADTRGB = (474), ///< GPT0 GTADTRB compare match + FSP_SIGNAL_GPT1_ADTRGA = (475), ///< GPT1 GTADTRA compare match + FSP_SIGNAL_GPT1_ADTRGB = (476), ///< GPT1 GTADTRB compare match + FSP_SIGNAL_GPT2_ADTRGA = (477), ///< GPT2 GTADTRA compare match + FSP_SIGNAL_GPT2_ADTRGB = (478), ///< GPT2 GTADTRB compare match + FSP_SIGNAL_GPT3_ADTRGA = (479), ///< GPT3 GTADTRA compare match + FSP_SIGNAL_GPT3_ADTRGB = (480), ///< GPT3 GTADTRB compare match + FSP_SIGNAL_GPT4_ADTRGA = (481), ///< GPT4 GTADTRA compare match + FSP_SIGNAL_GPT4_ADTRGB = (482), ///< GPT4 GTADTRB compare match + FSP_SIGNAL_GPT5_ADTRGA = (483), ///< GPT5 GTADTRA compare match + FSP_SIGNAL_GPT5_ADTRGB = (484), ///< GPT5 GTADTRB compare match + FSP_SIGNAL_GPT6_ADTRGA = (485), ///< GPT6 GTADTRA compare match + FSP_SIGNAL_GPT6_ADTRGB = (486), ///< GPT6 GTADTRB compare match + FSP_SIGNAL_GPT7_ADTRGA = (487), ///< GPT7 GTADTRA compare match + FSP_SIGNAL_GPT7_ADTRGB = (488), ///< GPT7 GTADTRB compare match + FSP_SIGNAL_GPT8_ADTRGA = (489), ///< GPT8 GTADTRA compare match + FSP_SIGNAL_GPT8_ADTRGB = (490), ///< GPT8 GTADTRB compare match + FSP_SIGNAL_GPT9_ADTRGA = (491), ///< GPT9 GTADTRA compare match + FSP_SIGNAL_GPT9_ADTRGB = (492), ///< GPT9 GTADTRB compare match + FSP_SIGNAL_GPT10_ADTRGA = (493), ///< GPT10 GTADTRA compare match + FSP_SIGNAL_GPT10_ADTRGB = (494), ///< GPT10 GTADTRB compare match + FSP_SIGNAL_GPT11_ADTRGA = (495), ///< GPT11 GTADTRA compare match + FSP_SIGNAL_GPT11_ADTRGB = (496), ///< GPT11 GTADTRB compare match + FSP_SIGNAL_GPT12_ADTRGA = (497), ///< GPT12 GTADTRA compare match + FSP_SIGNAL_GPT12_ADTRGB = (498), ///< GPT12 GTADTRB compare match + FSP_SIGNAL_GPT13_ADTRGA = (499), ///< GPT13 GTADTRA compare match + FSP_SIGNAL_GPT13_ADTRGB = (500), ///< GPT13 GTADTRB compare match + FSP_SIGNAL_NONE +} fsp_signal_t; + +typedef void (* fsp_vector_t)(void); + +/** @} (end addtogroup BSP_MCU) */ + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/fsp_version.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/fsp_version.h new file mode 100644 index 00000000000..0db44ea78f6 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/fsp_version.h @@ -0,0 +1,80 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef FSP_VERSION_H +#define FSP_VERSION_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/*******************************************************************************************************************//** + * @addtogroup RENESAS_COMMON + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** FSP pack major version. */ +#define FSP_VERSION_MAJOR (2U) + +/** FSP pack minor version. */ +#define FSP_VERSION_MINOR (0U) + +/** FSP pack patch version. */ +#define FSP_VERSION_PATCH (0U) + +/** FSP pack version build number (currently unused). */ +#define FSP_VERSION_BUILD (0U) + +/** Public FSP version name. */ +#define FSP_VERSION_STRING ("2.0.0") + +/** Unique FSP version ID. */ +#define FSP_VERSION_BUILD_STRING ("Built with RZ/T Flexible Software Package version 2.0.0") + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** FSP Pack version structure */ +typedef union st_fsp_pack_version +{ + /** Version id */ + uint32_t version_id; + + /** Code version parameters, little endian order. */ + struct version_id_b_s + { + uint8_t build; ///< Build version of FSP Pack + uint8_t patch; ///< Patch version of FSP Pack + uint8_t minor; ///< Minor version of FSP Pack + uint8_t major; ///< Major version of FSP Pack + } version_id_b; +} fsp_pack_version_t; + +/** @} */ + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/instances/r_ioport.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/instances/r_ioport.h new file mode 100644 index 00000000000..b9f4e1b93e3 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/instances/r_ioport.h @@ -0,0 +1,212 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup IOPORT + * @{ + **********************************************************************************************************************/ + +#ifndef R_IOPORT_H +#define R_IOPORT_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#include "r_ioport_api.h" +#include "r_ioport_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define IOPORT_SINGLE_PORT_NUM (4) +#define IOPORT_PORT_GROUP_NUM (2) +#define IOPORT_PORT_GROUP_1 (0) +#define IOPORT_PORT_GROUP_2 (1) +#define IOPORT_SINGLE_PORT_0 (0) +#define IOPORT_SINGLE_PORT_1 (1) +#define IOPORT_SINGLE_PORT_2 (2) +#define IOPORT_SINGLE_PORT_3 (3) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Pin selection for port group + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_pin_selection +{ + IOPORT_EVENT_PIN_SELECTION_NONE = 0x00, ///< No pin selection for port group + IOPORT_EVENT_PIN_SELECTION_PIN_0 = 0x01, ///< Select pin 0 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_1 = 0x02, ///< Select pin 1 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_2 = 0x04, ///< Select pin 2 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_3 = 0x08, ///< Select pin 3 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_4 = 0x10, ///< Select pin 4 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_5 = 0x20, ///< Select pin 5 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_6 = 0x40, ///< Select pin 6 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_7 = 0x80, ///< Select pin 7 to port group +} ioport_event_pin_selection_t; + +/** Port group operation + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_output_operation +{ + IOPORT_EVENT_OUTPUT_OPERATION_LOW = 0x0, ///< Set Low output to output operation + IOPORT_EVENT_OUTPUT_OPERATION_HIGH = 0x1, ///< Set High output to output operation + IOPORT_EVENT_OUTPUT_OPERATION_TOGGLE = 0x2, ///< Set toggle output to output operation + IOPORT_EVENT_OUTPUT_OPERATION_BUFFER = 0x3, ///< Set buffer value output to output operation +} ioport_event_output_operation_t; + +/** Input port group event control + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_control +{ + IOPORT_EVENT_CONTROL_DISABLE = 0x0, ///< Disable function related with event link + IOPORT_EVENT_CONTROL_ENABLE = 0x1, ///< Enable function related with event link +} ioport_event_control_t; + +/** Single port event direction + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_direction +{ + IOPORT_EVENT_DIRECTION_OUTPUT = 0x0, ///< Set output direction to single port + IOPORT_EVENT_DIRECTION_INPUT = 0x1, ///< Set input direction to single port +} ioport_event_direction_t; + +/** Input event edge detection + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_detection +{ + IOPORT_EVENT_DETECTION_RISING_EDGE = 0x0, ///< Set rising edge to event detection for input event + IOPORT_EVENT_DETECTION_FALLING_EDGE = 0x1, ///< Set falling edge to event detection for input event + IOPORT_EVENT_DETECTION_BOTH_EGDE = 0x2, ///< Set both edges to event detection for input event +} ioport_event_detection_t; + +/** Initial value for buffer register + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_initial_buffer_value +{ + IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW = 0U, ///< Set low input to initial value of buffer register for input port group + IOPORT_EVENT_INITIAL_BUFFER_VALUE_HIGH = 1U, ///< Set high input to initial value of buffer register for input port group +} ioport_event_initial_buffer_value_t; + +/** Single port configuration + * @note Event link must be configured by the ELC + */ +typedef struct st_ioport_event_single +{ + ioport_event_control_t event_control; ///< Event link control for single port + ioport_event_direction_t direction; ///< Event direction for single port + uint16_t port_num; ///< Port number specified to single port + ioport_event_output_operation_t operation; ///< Single port operation select + ioport_event_detection_t edge_detection; ///< Edge detection select +} ioport_event_single_t; + +/** Output port group configuration + * @note Event link must be configured by the ELC + */ +typedef struct st_ioport_event_group_output +{ + uint8_t pin_select; ///< Port number specified to output port group + ioport_event_output_operation_t operation; ///< Port group operation select +} ioport_event_group_output_t; + +/** Input port group configuration + * @note Event link must be configured by the ELC + */ +typedef struct st_ioport_event_group_input +{ + ioport_event_control_t event_control; ///< Event link control for input port group + ioport_event_detection_t edge_detection; ///< Edge detection select + ioport_event_control_t overwrite_control; ///< Buffer register overwrite control + uint8_t pin_select; ///< Port number specified to input port group + uint8_t buffer_init_value; ///< Buffer register initial value +} ioport_event_group_input_t; + +/** IOPORT extended configuration for event link function + * @note Event link must be configured by the ELC + */ +typedef struct st_ioport_extend_cfg +{ + ioport_event_group_output_t port_group_output_cfg[IOPORT_PORT_GROUP_NUM]; ///< Output port group configuration + ioport_event_group_input_t port_group_input_cfg[IOPORT_PORT_GROUP_NUM]; ///< Input port group configuration + ioport_event_single_t single_port_cfg[IOPORT_SINGLE_PORT_NUM]; ///< Single input port configuration +} ioport_extend_cfg_t; + +/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */ +typedef struct st_ioport_instance_ctrl +{ + uint32_t open; // Whether or not ioport is open + void const * p_context; // Pointer to context to be passed into callback + ioport_cfg_t const * p_cfg; // Pointer to the configuration block +} ioport_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const ioport_api_t g_ioport_on_ioport; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ + +fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl); +fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); +fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); +fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); +fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); +fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); +fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t direction_values, + ioport_size_t mask); +fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); +fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t event_data, + ioport_size_t mask_value); +fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); +fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); + +/*******************************************************************************************************************//** + * @} (end defgroup IOPORT) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_IOPORT_H diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/instances/r_sci_uart.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/instances/r_sci_uart.h new file mode 100644 index 00000000000..fd403941112 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/inc/instances/r_sci_uart.h @@ -0,0 +1,246 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_SCI_UART_H +#define R_SCI_UART_H + +/*******************************************************************************************************************//** + * @addtogroup SCI_UART + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_uart_api.h" +#include "r_sci_uart_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Enumeration for SCI clock source */ +typedef enum e_sci_uart_clock +{ + SCI_UART_CLOCK_INT, ///< Use internal clock for baud generation + SCI_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK + SCI_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate + SCI_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate +} sci_uart_clock_t; + +/** UART flow control mode definition */ +typedef enum e_sci_uart_flow_control +{ + SCI_UART_FLOW_CONTROL_RTS = 0U, ///< Use CTSn_RTSn pin for RTS + SCI_UART_FLOW_CONTROL_CTS = 1U, ///< Use CTSn_RTSn pin for CTS + SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 3U, ///< Use CTSn pin for CTS, CTSn_RTSn pin for RTS + SCI_UART_FLOW_CONTROL_CTSRTS = 5U, ///< Use SCI pin for CTS, external pin for RTS +} sci_uart_flow_control_t; + +/** UART instance control block. */ +typedef struct st_sci_uart_instance_ctrl +{ + /* Parameters to control UART peripheral device */ + uint8_t fifo_depth; // FIFO depth of the UART channel + uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise + uint8_t data_bytes : 2; // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data + uint8_t bitrate_modulation : 1; // 1 if bit rate modulation is enabled, 0 otherwise + uint32_t open; // Used to determine if the channel is configured + + bsp_io_port_pin_t flow_pin; + + /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint8_t const * p_tx_src; + + /* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint32_t tx_src_bytes; + + /* Destination buffer pointer used for receiving data. */ + uint8_t const * p_rx_dest; + + /* Size of destination buffer pointer used for receiving data. */ + uint32_t rx_dest_bytes; + + /* Pointer to the configuration block. */ + uart_cfg_t const * p_cfg; + + /* Base register for this channel */ + R_SCI0_Type * p_reg; + + void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs. + uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + /* Pointer to context to be passed into callback function */ + void const * p_context; +} sci_uart_instance_ctrl_t; + +/** Receive FIFO trigger configuration. */ +typedef enum e_sci_uart_rx_fifo_trigger +{ + SCI_UART_RX_FIFO_TRIGGER_1 = 0x1, ///< Callback after each byte is received without buffering + SCI_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts) +} sci_uart_rx_fifo_trigger_t; + +/** Asynchronous Start Bit Edge Detection configuration. */ +typedef enum e_sci_uart_start_bit +{ + SCI_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit + SCI_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit +} sci_uart_start_bit_t; + +/** Noise cancellation configuration. */ +typedef enum e_sci_uart_noise_cancellation +{ + SCI_UART_NOISE_CANCELLATION_DISABLE = 0x0, ///< Disable noise cancellation + SCI_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation, The base clock signal divided by 1 + SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_1 = 0x2, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 1 + SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_2 = 0x3, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 2 + SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_4 = 0x4, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 4 + SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_8 = 0x5, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 8 +} sci_uart_noise_cancellation_t; + +/** RS-485 Enable/Disable. */ +typedef enum e_sci_uart_rs485_enable +{ + SCI_UART_RS485_DISABLE = 0, ///< RS-485 disabled. + SCI_UART_RS485_ENABLE = 1, ///< RS-485 enabled. +} sci_uart_rs485_enable_t; + +/** The polarity of the RS-485 DE signal. */ +typedef enum e_sci_uart_rs485_de_polarity +{ + SCI_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress. + SCI_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress. +} sci_uart_rs485_de_polarity_t; + +/** Source clock selection options for SCI. */ +typedef enum e_sci_uart_clock_source +{ + SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK = 0, + SCI_UART_CLOCK_SOURCE_SCI1ASYNCCLK = 1, + SCI_UART_CLOCK_SOURCE_SCI2ASYNCCLK = 2, + SCI_UART_CLOCK_SOURCE_SCI3ASYNCCLK = 3, + SCI_UART_CLOCK_SOURCE_SCI4ASYNCCLK = 4, + SCI_UART_CLOCK_SOURCE_SCI5ASYNCCLK = 5, + SCI_UART_CLOCK_SOURCE_PCLKM = 6, +} sci_uart_clock_source_t; + +/** Baudrate calculation configuration. */ +typedef struct st_sci_uart_baud_calculation +{ + uint32_t baudrate; ///< Target baudrate + bool bitrate_modulation; ///< Whether bitrate modulation use or not + uint32_t baud_rate_error_x_1000; ///< Max baudrate percent error +} sci_uart_baud_calculation_t; + +/** Register settings to achieve a desired baud rate and modulation duty. */ +typedef struct st_sci_baud_setting_t +{ + union + { + uint32_t baudrate_bits; + + struct + { + uint32_t : 4; + uint32_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select + uint32_t abcs : 1; ///< Asynchronous Mode Base Clock Select + uint32_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select 1 + uint32_t : 1; + uint32_t brr : 8; ///< Bit Rate Register setting + uint32_t brme : 1; ///< Bit Rate Modulation Enable + uint32_t : 3; + uint32_t cks : 2; ///< CKS value to get divisor (CKS = N) + uint32_t : 2; + uint32_t mddr : 8; ///< Modulation Duty Register setting + } baudrate_bits_b; + }; +} sci_baud_setting_t; + +/** Configuration settings for controlling the DE signal for RS-485. */ +typedef struct st_sci_uart_rs485_setting +{ + sci_uart_rs485_enable_t enable; ///< Enable the DE signal. + sci_uart_rs485_de_polarity_t polarity; ///< DE signal polarity. + uint8_t assertion_time : 5; ///< Time in baseclock units after assertion of the DE signal and before the start of the write transfer. + uint8_t negation_time : 5; ///< Time in baseclock units after the end of a write transfer and before the DE signal is negated. +} sci_uart_rs485_setting_t; + +/** UART on SCI device Configuration */ +typedef struct st_sci_uart_extended_cfg +{ + sci_uart_clock_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK + sci_uart_start_bit_t rx_edge_start; ///< Start reception on falling edge + sci_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting + + sci_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. + + sci_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DMAC is used. + + bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin + sci_uart_flow_control_t flow_control; ///< CTS/RTS function + sci_uart_rs485_setting_t rs485_setting; ///< RS-485 settings. + + /** Clock source to generate SCK can either be selected as PCLKM or SCInASYNCCLK. */ + sci_uart_clock_source_t clock_source; +} sci_uart_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const uart_api_t g_uart_on_sci; + +/** @endcond */ + +fsp_err_t R_SCI_UART_Open(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); +fsp_err_t R_SCI_UART_Read(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_SCI_UART_Write(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes); +fsp_err_t R_SCI_UART_BaudSet(uart_ctrl_t * const p_ctrl, void const * const p_baud_setting); +fsp_err_t R_SCI_UART_InfoGet(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info); +fsp_err_t R_SCI_UART_Close(uart_ctrl_t * const p_ctrl); +fsp_err_t R_SCI_UART_Abort(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort); +fsp_err_t R_SCI_UART_BaudCalculate(sci_uart_baud_calculation_t const * const p_baud_target, + sci_uart_clock_source_t clock_source, + sci_baud_setting_t * const p_baud_setting); +fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const p_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void const * const p_context, + uart_callback_args_t * const p_callback_memory); +fsp_err_t R_SCI_UART_ReadStop(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes); + +/*******************************************************************************************************************//** + * @} (end addtogroup SCI_UART) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G074.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G074.h new file mode 100644 index 00000000000..2761da89686 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G074.h @@ -0,0 +1,31871 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R9A07G074 + * @{ + */ + +#ifndef R9A07G074_H + #define R9A07G074_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ----------------Configuration of the Cortex-M Processor and Core Peripherals---------------- */ + #ifdef RENESAS_CORTEX_M4 + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ + #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ + #elif defined(RENESAS_CORTEX_M0PLUS) + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 0 /*!< FPU present or not */ + #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */ + #include "core_cm0plus.h" /*!< Cortex-M0 processor and core peripherals */ + #elif defined(RENESAS_CORTEX_M23) + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 0 /*!< FPU present or not */ + #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */ + #include "core_cm23.h" /*!< Cortex-M23 processor and core peripherals */ + #elif defined(RENESAS_CORTEX_M33) + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ + #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */ + #define __DSP_PRESENT 1 /*!< DSP present or not */ + #include "core_cm33.h" /*!< Cortex-M33 processor and core peripherals */ + #elif defined(RENESAS_CORTEX_R52) + #define __FPU_PRESENT 1 /*!< FPU present or not */ + #include "core_cr52.h" /*!< Cortex-R52 processor and core peripherals */ + #endif + + #include "system.h" /*!< System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_CANFD_CFDC [CFDC] (CANFD Channel [0..1] Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel n Nominal Bit Rate Configuration Register */ + + struct + { + __IOM uint32_t NBRP : 10; /*!< [9..0] Nominal Bit Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Nominal Bit Rate Resynchronization Jump Width Control */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Nominal Bit Rate Time Segment 1 Control */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Nominal Bit Rate Time Segment 2 Control */ + } NCFG_b; + }; + + union + { + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel n Control Register */ + + struct + { + __IOM uint32_t CHMDC : 2; /*!< [1..0] Mode Select */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Stop Mode */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Forcible Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission Abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error Occurrence Counter Overflow Interrupt Enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt Enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Bus-Off Recovery Mode Select */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Error Display Mode Select */ + __IOM uint32_t CTME : 1; /*!< [24..24] Communication Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Communication Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test Enable */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode Enable */ + } CTR_b; + }; + + union + { + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel n Status Register */ + + struct + { + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel Reset Status Flag */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel Halt Status Flag */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel Stop Status Flag */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Error Passive Status Flag */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Bus-Off Status Flag */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Transmit Status Flag */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Receive Status Flag */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Communication Status Flag */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; + }; + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel n Error Flag Register */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error Flag */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error Flag */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error Flag */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error Flag */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Recessive Bit Error Flag */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Dominant Bit Error Flag */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error Flag */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Calculation Data (CRC length: 15 bits) */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bit Rate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Data Bit Rate Prescaler Division Ratio Setting */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Data Bit Rate Time Segment 1 Control */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Data Bit Rate Time Segment 2 Control */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Data Bit Rate Resynchronization Jump Width Control */ + uint32_t : 4; + } DCFG_b; + }; + + union + { + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel n CAN-FD Configuration Register */ + + struct + { + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transmitter Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD Multi Gateway Enable */ + __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF Configuration Bit */ + __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS Configuration Bit */ + uint32_t : 1; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD-Only Enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX Edge Filter Enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN-Only Enable */ + __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD Frame Distinction Enable */ + } FDCFG_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel n CAN-FD Control Register */ + + struct + { + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel n CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error Occurrence Counter Overflow Flag */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful Occurrence Counter Overflow Flag */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error Occurrence Counter */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful Occurrence Counter */ + } FDSTS_b; + }; + + union + { + __IM uint32_t FDCRC; /*!< (@ 0x00000010) Channel n CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register Value */ + uint32_t : 4; + __IM uint32_t SCNT : 4; /*!< [28..25] Stuff Bit Count */ + uint32_t : 3; + } FDCRC_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel n Bus Load Control Register */ + + struct + { + __IOM uint32_t BLCE : 1; /*!< [0..0] Bus Load Counter Enable */ + uint32_t : 7; + __OM uint32_t BLCLD : 1; /*!< [8..8] Bus Load Counter Load */ + uint32_t : 23; + } BLCT_b; + }; + + union + { + __IM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel n Bus Load Status Register */ + + struct + { + uint32_t : 3; + __IM uint32_t BLC : 29; /*!< [31..3] Bus Load Counter Status */ + } BLSTS_b; + }; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Register n */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; + + union + { + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Register n */ + + struct + { + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; + }; + + union + { + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Register + * n */ + + struct + { + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing Destination + * 0 */ + __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing Destination + * 1 */ + __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing Destination + * 2 */ + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer */ + } P0_b; + }; + + union + { + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Register + * n */ + + struct + { + __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 18; + } P1_b; + }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Bit */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + + struct + { + __IOM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IOM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + union + { + __IM uint32_t DF_WD[16]; /*!< (@ 0x0000000C) RX Message Buffer Data Field p Register n (p + * = 0 to 15, n = 0 to 31) */ + + struct + { + __IM uint32_t RMDB_LL : 8; /*!< [7..0] RX Message Buffer Data Byte (4 * p) */ + __IM uint32_t RMDB_LH : 8; /*!< [15..8] RX Message Buffer Data Byte (4 * p + 1) */ + __IM uint32_t RMDB_HL : 8; /*!< [23..16] RX Message Buffer Data Byte (4 * p + 2) */ + __IM uint32_t RMDB_HH : 8; /*!< [31..24] RX Message Buffer Data Byte (4 * p + 3) */ + } DF_WD_b[16]; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field p Register n (p + * = 0 to 63, n = 0 to 31) */ + + struct + { + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; + }; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register n */ + + struct + { + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR bit */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register n */ + + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Value */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register n */ + + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t CFDRFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + union + { + __IM uint32_t DF_WD[16]; /*!< (@ 0x0000000C) RX FIFO Access Data Field p Register n (p = 0 + * to 15, n = 0 to 7) */ + + struct + { + __IM uint32_t RFDB_LL : 8; /*!< [7..0] RX FIFO Buffer Data Byte (4 * p) */ + __IM uint32_t RFDB_LH : 8; /*!< [15..8] RX FIFO Buffer Data Byte (4 * p + 1) */ + __IM uint32_t RFDB_HL : 8; /*!< [23..16] RX FIFO Buffer Data Byte (4 * p + 2) */ + __IM uint32_t RFDB_HH : 8; /*!< [31..24] RX FIFO Buffer Data Byte (4 * p + 3) */ + } DF_WD_b[16]; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field p Register n (p = 0 + * to 63, n = 0 to 7) */ + + struct + { + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; + }; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + + struct + { + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry Enable */ + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR bit */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register n */ + + struct + { + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Value */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Control/Status Register + * n */ + + struct + { + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] COMMON FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDCSTS_b; + }; + + union + { + union + { + __IOM uint32_t DF_WD[16]; /*!< (@ 0x0000000C) Common FIFO Access Data Field p Register n (p + * = 0 to 15, n = 0 to 5) */ + + struct + { + __IOM uint32_t CFDB_LL : 8; /*!< [7..0] Common FIFO Buffer Data Bytes (4 * p) */ + __IOM uint32_t CFDB_LH : 8; /*!< [15..8] Common FIFO Buffer Data Bytes (4 * p + 1) */ + __IOM uint32_t CFDB_HL : 8; /*!< [23..16] Common FIFO Buffer Data Bytes (4 * p + 2) */ + __IOM uint32_t CFDB_HH : 8; /*!< [31..24] Common FIFO Buffer Data Bytes (4 * p + 3) */ + } DF_WD_b[16]; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field p Register n (p + * = 0 to 63, n = 0 to 5) */ + + struct + { + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Bytes */ + } DF_b[64]; + }; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ + union + { + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + + struct + { + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer Number */ + uint32_t : 5; + __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer Indication */ + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; + + union + { + __IM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register n (n = 0 to 127) */ + + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR bit */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register n (n = 0 to + * 127) */ + + struct + { + uint32_t : 28; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register n (n + * = 0 to 127) */ + + struct + { + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; + }; + + union + { + union + { + __IOM uint32_t DF_WD[16]; /*!< (@ 0x0000000C) TX Message Buffer Data Field p Register n (p + * = 0 to 15, n = 0 to 127) */ + + struct + { + __IOM uint32_t TMDB_LL : 8; /*!< [7..0] TX Message Buffer Data Byte (4 * p) */ + __IOM uint32_t TMDB_LH : 8; /*!< [15..8] TX Message Buffer Data Byte (4 * p + 1) */ + __IOM uint32_t TMDB_HL : 8; /*!< [23..16] TX Message Buffer Data Byte (4 * p + 2) */ + __IOM uint32_t TMDB_HH : 8; /*!< [31..24] TX Message Buffer Data Byte (4 * p + 3) */ + } DF_WD_b[16]; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field p Register n (p + * = 0 to 63, n = 0 to 5) */ + + struct + { + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Bytes */ + } DF_b[64]; + }; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CMT_UNT_CM [CM] (2 Timer Start Register Pairs) + */ +typedef struct +{ + union + { + __IOM uint16_t CR; /*!< (@ 0x00000000) Compare Match Timer Control Register */ + + struct + { + __IOM uint16_t CKS : 2; /*!< [1..0] Clock Select */ + uint16_t : 4; + __IOM uint16_t CMIE : 1; /*!< [6..6] Compare Match Interrupt Enable */ + uint16_t : 9; + } CR_b; + }; + __IOM uint16_t CNT; /*!< (@ 0x00000002) Compare Match Timer Counter Register */ + __IOM uint16_t COR; /*!< (@ 0x00000004) Compare Match Timer Constant Register */ +} R_CMT_UNT_CM_Type; /*!< Size = 6 (0x6) */ + +/** + * @brief R_CMT_UNT [UNT] (3 Timer Start Register Units) + */ +typedef struct +{ + union + { + __IOM uint16_t CMSTR0; /*!< (@ 0x00000000) Compare Match Timer Start Register */ + + struct + { + __IOM uint16_t STR0 : 1; /*!< [0..0] CMT Channel n Count Start */ + __IOM uint16_t STR1 : 1; /*!< [1..1] CMT Channel n+1 Count Start */ + uint16_t : 14; + } CMSTR0_b; + }; + __IOM R_CMT_UNT_CM_Type CM[2]; /*!< (@ 0x00000002) 2 Timer Start Register Pairs */ + __IM uint16_t RESERVED[505]; +} R_CMT_UNT_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L y (y = 0 to 2) */ + + struct + { + __IOM uint8_t SVA0 : 1; /*!< [0..0] 10-bit Address LSB */ + __IOM uint8_t SVA : 7; /*!< [7..1] 7-bit Address/10-bit Address Lower Bits */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U y (y = 0 to 2) */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-bit/10-bit Address Format Select */ + __IOM uint8_t SVA : 2; /*!< [2..1] 10-bit Address Upper Bits */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_DMAC0_GRP_CH_N [N] (DMAC Address Registers [0..1]) + */ +typedef struct +{ + __IOM uint32_t SA; /*!< (@ 0x00000000) Nextm0 Source Address Register n */ + __IOM uint32_t DA; /*!< (@ 0x00000004) Nextm0 Destination Address Register n (m = 0, + * 1) (n = 0 to 15) */ + __IOM uint32_t TB; /*!< (@ 0x00000008) Nextm0 Transaction Byte Register n (m = 0, 1) + * (n = 0 to 15) */ +} R_DMAC0_GRP_CH_N_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_DMAC0_GRP_CH [CH] (DMAC channel Control Register [0..7]) + */ +typedef struct +{ + __IOM R_DMAC0_GRP_CH_N_Type N[2]; /*!< (@ 0x00000000) DMAC Address Registers [0..1] */ + __IM uint32_t CRSA; /*!< (@ 0x00000018) Current Source Address Register n (n = 0 to 15) */ + __IM uint32_t CRDA; /*!< (@ 0x0000001C) Current Destination Address Register n (n = 0 + * to 15) */ + __IM uint32_t CRTB; /*!< (@ 0x00000020) Current Transaction Byte Register n */ + + union + { + __IM uint32_t CHSTAT; /*!< (@ 0x00000024) Channel Status Register n */ + + struct + { + __IM uint32_t EN : 1; /*!< [0..0] DMA Activation Enable */ + __IM uint32_t RQST : 1; /*!< [1..1] DMA Transfer Request */ + __IM uint32_t TACT : 1; /*!< [2..2] DMAC Operating Status */ + __IM uint32_t SUS : 1; /*!< [3..3] Suspend */ + __IM uint32_t ER : 1; /*!< [4..4] DMA Error */ + __IM uint32_t END : 1; /*!< [5..5] DMA Transfer Completion Interrupt */ + __IM uint32_t TC : 1; /*!< [6..6] DMA Transfer Completion (total number of data bytes for + * transaction) */ + __IM uint32_t SR : 1; /*!< [7..7] Next Register Select */ + __IM uint32_t DL : 1; /*!< [8..8] Descriptor Load */ + __IM uint32_t DW : 1; /*!< [9..9] Descriptor Write Back */ + __IM uint32_t DER : 1; /*!< [10..10] Descriptor Error */ + __IM uint32_t MODE : 1; /*!< [11..11] DMA Mode */ + uint32_t : 4; + __IM uint32_t INTM : 1; /*!< [16..16] DMA Transfer Completion Interrupt Request Mask */ + uint32_t : 15; + } CHSTAT_b; + }; + + union + { + __IOM uint32_t CHCTRL; /*!< (@ 0x00000028) Channel Control Register n */ + + struct + { + __IOM uint32_t SETEN : 1; /*!< [0..0] DMA Activation Enable */ + __IOM uint32_t CLREN : 1; /*!< [1..1] DMA Activation Enable Clear */ + __IOM uint32_t STG : 1; /*!< [2..2] Software Trigger */ + __IOM uint32_t SWRST : 1; /*!< [3..3] Software Reset */ + __IOM uint32_t CLRRQ : 1; /*!< [4..4] DMA Transfer Request Clear */ + __IOM uint32_t CLREND : 1; /*!< [5..5] END Clear */ + __IOM uint32_t CLRTC : 1; /*!< [6..6] TC Clear */ + uint32_t : 1; + __IOM uint32_t SETSUS : 1; /*!< [8..8] Suspend Request */ + __IOM uint32_t CLRSUS : 1; /*!< [9..9] Suspend Clear */ + uint32_t : 6; + __IOM uint32_t SETINTM : 1; /*!< [16..16] DMA Transfer Completion Interrupt Request Mask */ + __IOM uint32_t CLRINTM : 1; /*!< [17..17] DMA Transfer Completion Interrupt Request Mask Clear */ + uint32_t : 14; + } CHCTRL_b; + }; + + union + { + __IOM uint32_t CHCFG; /*!< (@ 0x0000002C) Channel Configuration Register n */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Pin Select */ + __IOM uint32_t REQD : 1; /*!< [3..3] DMA Activation Request Source Select */ + __IOM uint32_t LOEN : 1; /*!< [4..4] L Detection Enable */ + __IOM uint32_t HIEN : 1; /*!< [5..5] H Detection Enable */ + __IOM uint32_t LVL : 1; /*!< [6..6] Level Detection Enable */ + uint32_t : 1; + __IOM uint32_t AM : 3; /*!< [10..8] ACK Mode */ + uint32_t : 1; + __IOM uint32_t SDS : 4; /*!< [15..12] Source Data Size */ + __IOM uint32_t DDS : 4; /*!< [19..16] Destination Data Size */ + __IOM uint32_t SAD : 1; /*!< [20..20] Source Address Count Direction */ + __IOM uint32_t DAD : 1; /*!< [21..21] Destination Address Count Direction */ + __IOM uint32_t TM : 1; /*!< [22..22] Transfer Mode */ + uint32_t : 1; + __IOM uint32_t DEM : 1; /*!< [24..24] DMA Transfer Completion Interrupt Mask */ + __IOM uint32_t TCM : 1; /*!< [25..25] TEND Mask */ + uint32_t : 1; + __IOM uint32_t SBE : 1; /*!< [27..27] Buffer Flush Enable */ + __IOM uint32_t RSEL : 1; /*!< [28..28] Next Register Select */ + __IOM uint32_t RSW : 1; /*!< [29..29] RSEL Reverse */ + __IOM uint32_t REN : 1; /*!< [30..30] Register Set Enable */ + __IOM uint32_t DMS : 1; /*!< [31..31] DMA Mode Select */ + } CHCFG_b; + }; + + union + { + __IOM uint32_t CHITVL; /*!< (@ 0x00000030) Channel Interval Register n */ + + struct + { + __IOM uint32_t ITVL : 16; /*!< [15..0] Interval */ + uint32_t : 16; + } CHITVL_b; + }; + + union + { + __IOM uint32_t CHEXT; /*!< (@ 0x00000034) Channel Extension Register n */ + + struct + { + __IOM uint32_t SPR : 3; /*!< [2..0] Source PROT */ + uint32_t : 1; + __IOM uint32_t SCA : 4; /*!< [7..4] Source CACHE */ + __IOM uint32_t DPR : 3; /*!< [10..8] Destination PROT */ + uint32_t : 1; + __IOM uint32_t DCA : 4; /*!< [15..12] Destination CACHE */ + uint32_t : 16; + } CHEXT_b; + }; + __IOM uint32_t NXLA; /*!< (@ 0x00000038) DMA Destination Address Register */ + __IM uint32_t CRLA; /*!< (@ 0x0000003C) Current Link Address Register n */ +} R_DMAC0_GRP_CH_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_DMAC0_GRP [GRP] (8 channel Registers) + */ +typedef struct +{ + __IOM R_DMAC0_GRP_CH_Type CH[8]; /*!< (@ 0x00000000) DMAC channel Control Register [0..7] */ + __IM uint32_t RESERVED[64]; + + union + { + __IOM uint32_t DCTRL; /*!< (@ 0x00000300) DMA Control Register A/B */ + + struct + { + __IOM uint32_t PR : 1; /*!< [0..0] Priority Control Select */ + __IOM uint32_t LVINT : 1; /*!< [1..1] DMA Interrupt Output Select */ + uint32_t : 30; + } DCTRL_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IM uint32_t DSTAT_EN; /*!< (@ 0x00000310) DMA Status EN Register A/B */ + + struct + { + __IM uint32_t EN0008 : 1; /*!< [0..0] Channel 0/8 EN */ + __IM uint32_t EN0109 : 1; /*!< [1..1] Channel 1/9 EN */ + __IM uint32_t EN0210 : 1; /*!< [2..2] Channel 2/10 EN */ + __IM uint32_t EN0311 : 1; /*!< [3..3] Channel 3/11 EN */ + __IM uint32_t EN0412 : 1; /*!< [4..4] Channel 4/12 EN */ + __IM uint32_t EN0513 : 1; /*!< [5..5] Channel 5/13 EN */ + __IM uint32_t EN0614 : 1; /*!< [6..6] Channel 6/14 EN */ + __IM uint32_t EN0715 : 1; /*!< [7..7] Channel 7/15 EN */ + uint32_t : 24; + } DSTAT_EN_b; + }; + + union + { + __IM uint32_t DSTAT_ER; /*!< (@ 0x00000314) DMA Status ER Register A/B */ + + struct + { + __IM uint32_t ER0008 : 1; /*!< [0..0] Channel 0/8 ER */ + __IM uint32_t ER0109 : 1; /*!< [1..1] Channel 1/9 ER */ + __IM uint32_t ER0210 : 1; /*!< [2..2] Channel 2/10 ER */ + __IM uint32_t ER0311 : 1; /*!< [3..3] Channel 3/11 ER */ + __IM uint32_t ER0412 : 1; /*!< [4..4] Channel 4/12 ER */ + __IM uint32_t ER0513 : 1; /*!< [5..5] Channel 5/13 ER */ + __IM uint32_t ER0614 : 1; /*!< [6..6] Channel 6/14 ER */ + __IM uint32_t ER0715 : 1; /*!< [7..7] Channel 7/15 ER */ + uint32_t : 24; + } DSTAT_ER_b; + }; + + union + { + __IM uint32_t DSTAT_END; /*!< (@ 0x00000318) DMA Status END Register A/B */ + + struct + { + __IM uint32_t END0008 : 1; /*!< [0..0] Channel 0/8 END */ + __IM uint32_t END0109 : 1; /*!< [1..1] Channel 1/9 END */ + __IM uint32_t END0210 : 1; /*!< [2..2] Channel 2/10 END */ + __IM uint32_t END0311 : 1; /*!< [3..3] Channel 3/11 END */ + __IM uint32_t END0412 : 1; /*!< [4..4] Channel 4/12 END */ + __IM uint32_t END0513 : 1; /*!< [5..5] Channel 5/13 END */ + __IM uint32_t END0614 : 1; /*!< [6..6] Channel 6/14 END */ + __IM uint32_t END0715 : 1; /*!< [7..7] Channel 7/15 END */ + uint32_t : 24; + } DSTAT_END_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t DSTAT_SUS; /*!< (@ 0x00000320) DMA Status SUS Register A/B */ + + struct + { + __IM uint32_t SUS0008 : 1; /*!< [0..0] Channel 0/8 SUS */ + __IM uint32_t SUS0109 : 1; /*!< [1..1] Channel 1/9 SUS */ + __IM uint32_t SUS0210 : 1; /*!< [2..2] Channel 2/10 SUS */ + __IM uint32_t SUS0311 : 1; /*!< [3..3] Channel 3/11 SUS */ + __IM uint32_t SUS0412 : 1; /*!< [4..4] Channel 4/12 SUS */ + __IM uint32_t SUS0513 : 1; /*!< [5..5] Channel 5/13 SUS */ + __IM uint32_t SUS0614 : 1; /*!< [6..6] Channel 6/14 SUS */ + __IM uint32_t SUS0715 : 1; /*!< [7..7] Channel 7/15 SUS */ + uint32_t : 24; + } DSTAT_SUS_b; + }; + __IM uint32_t RESERVED3[55]; +} R_DMAC0_GRP_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_PORT_DRCTL [DRCTL] (I/O Buffer [0..24] Function Switching Register) + */ +typedef struct +{ + union + { + __IOM uint32_t L; /*!< (@ 0x00000000) I/O Buffer m Function Switching Register 0-3 */ + + struct + { + __IOM uint32_t DRV0 : 2; /*!< [1..0] Pm_0 Driving Ability Control */ + __IOM uint32_t PUD0 : 2; /*!< [3..2] Pm_0 Pull-Up/Down Control */ + __IOM uint32_t SMT0 : 1; /*!< [4..4] Pm_0 Schmitt Trigger Control */ + __IOM uint32_t SR0 : 1; /*!< [5..5] Pm_0 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV1 : 2; /*!< [9..8] Pm_1 Driving Ability Control */ + __IOM uint32_t PUD1 : 2; /*!< [11..10] Pm_1 Pull-Up/Down Control */ + __IOM uint32_t SMT1 : 1; /*!< [12..12] Pm_1 Schmitt Trigger Control */ + __IOM uint32_t SR1 : 1; /*!< [13..13] Pm_1 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV2 : 2; /*!< [17..16] Pm_2 Driving Ability Control */ + __IOM uint32_t PUD2 : 2; /*!< [19..18] Pm_2 Pull-Up/Down Control */ + __IOM uint32_t SMT2 : 1; /*!< [20..20] Pm_2 Schmitt Trigger Control */ + __IOM uint32_t SR2 : 1; /*!< [21..21] Pm_2 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV3 : 2; /*!< [25..24] Pm_3 Driving Ability Control */ + __IOM uint32_t PUD3 : 2; /*!< [27..26] Pm_3 Pull-Up/Down Control */ + __IOM uint32_t SMT3 : 1; /*!< [28..28] Pm_3 Schmitt Trigger Control */ + __IOM uint32_t SR3 : 1; /*!< [29..29] Pm_3 Slew Rate Control */ + uint32_t : 2; + } L_b; + }; + + union + { + __IOM uint32_t H; /*!< (@ 0x00000004) I/O Buffer m Function Switching Register 4-7 */ + + struct + { + __IOM uint32_t DRV4 : 2; /*!< [1..0] Pm_4 Driving Ability Control */ + __IOM uint32_t PUD4 : 2; /*!< [3..2] Pm_4 Pull-Up/Down Control */ + __IOM uint32_t SMT4 : 1; /*!< [4..4] Pm_4 Schmitt Trigger Control */ + __IOM uint32_t SR4 : 1; /*!< [5..5] Pm_4 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV5 : 2; /*!< [9..8] Pm_5 Driving Ability Control */ + __IOM uint32_t PUD5 : 2; /*!< [11..10] Pm_5 Pull-Up/Down Control */ + __IOM uint32_t SMT5 : 1; /*!< [12..12] Pm_5 Schmitt Trigger Control */ + __IOM uint32_t SR5 : 1; /*!< [13..13] Pm_5 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV6 : 2; /*!< [17..16] Pm_6 Driving Ability Control */ + __IOM uint32_t PUD6 : 2; /*!< [19..18] Pm_6 Pull-Up/Down Control */ + __IOM uint32_t SMT6 : 1; /*!< [20..20] Pm_6 Schmitt Trigger Control */ + __IOM uint32_t SR6 : 1; /*!< [21..21] Pm_6 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV7 : 2; /*!< [25..24] Pm_7 Driving Ability Control */ + __IOM uint32_t PUD7 : 2; /*!< [27..26] Pm_7 Pull-Up/Down Control */ + __IOM uint32_t SMT7 : 1; /*!< [28..28] Pm_7 Schmitt Trigger Control */ + __IOM uint32_t SR7 : 1; /*!< [29..29] Pm_7 Slew Rate Control */ + uint32_t : 2; + } H_b; + }; +} R_PORT_DRCTL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_PORT_NSR_ELC_PDBF [ELC_PDBF] (ELC Port Buffer Register [0..1]) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) ELC Port Buffer Register n */ + + struct + { + __IOM uint8_t PB0 : 1; /*!< [0..0] Port Buffer 0 */ + __IOM uint8_t PB1 : 1; /*!< [1..1] Port Buffer 1 */ + __IOM uint8_t PB2 : 1; /*!< [2..2] Port Buffer 2 */ + __IOM uint8_t PB3 : 1; /*!< [3..3] Port Buffer 3 */ + __IOM uint8_t PB4 : 1; /*!< [4..4] Port Buffer 4 */ + __IOM uint8_t PB5 : 1; /*!< [5..5] Port Buffer 5 */ + __IOM uint8_t PB6 : 1; /*!< [6..6] Port Buffer 6 */ + __IOM uint8_t PB7 : 1; /*!< [7..7] Port Buffer 7 */ + } BY_b; + }; + __IM uint8_t RESERVED[3]; +} R_PORT_NSR_ELC_PDBF_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_GMAC_PTP_SWTM [SWTM] (GMAC Switch Timer output pins 0-3 Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t EN; /*!< (@ 0x00000000) PTP Timer Pulse Output Enable n Register (n = + * 0 to 3) */ + + struct + { + __IOM uint32_t OUTEN : 1; /*!< [0..0] Enable GMAC_PTPOUTn Signal Output */ + uint32_t : 31; + } EN_b; + }; + + union + { + __IOM uint32_t STSEC; /*!< (@ 0x00000004) PTP Timer Pulse Start Second n Register (n = + * 0 to 3) */ + + struct + { + __IOM uint32_t STSEC : 32; /*!< [31..0] STSEC */ + } STSEC_b; + }; + + union + { + __IOM uint32_t STNS; /*!< (@ 0x00000008) PTP Timer Pulse Start Nanosecond n Register (n + * = 0 to 3) */ + + struct + { + __IOM uint32_t STNS : 32; /*!< [31..0] Start Time by Nanosecond */ + } STNS_b; + }; + + union + { + __IOM uint32_t PSEC; /*!< (@ 0x0000000C) PTP Timer Pulse Period Second n Register (n = + * 0 to 3) */ + + struct + { + __IOM uint32_t PSEC : 32; /*!< [31..0] PSEC */ + } PSEC_b; + }; + + union + { + __IOM uint32_t PNS; /*!< (@ 0x00000010) PTP Timer Pulse Period Nanosecond n Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t PNS : 32; /*!< [31..0] Period by Nanosecond */ + } PNS_b; + }; + + union + { + __IOM uint32_t WTH; /*!< (@ 0x00000014) PTP Timer Pulse Width n Register (n = 0 to 3) */ + + struct + { + __IOM uint32_t WIDTH : 16; /*!< [15..0] Set the Pulse Width of GMAC_PTPOUTn in the cycle number + * of GMAC_PTP_REFCLK_I (8 ns). */ + uint32_t : 16; + } WTH_b; + }; + + union + { + __IOM uint32_t MAXP; /*!< (@ 0x00000018) PTP Timer Pulse Max Nanosecond n Register (n + * = 0 to 3) */ + + struct + { + __IOM uint32_t MAXP : 32; /*!< [31..0] Sets the boundary value in nanoseconds to carry from + * the nanosecond field to the second field. This register + * must be set to 0x3B9ACA00 (= 109) when TSCTRLSSR bit in + * Timestamp_Control register is set to 1. This register must + * be set to 0x80000000 (= 231) when TSCTRLSSR bit in Timestamp_Control + * register is reset to 0. */ + } MAXP_b; + }; + + union + { + __IOM uint32_t LATSEC; /*!< (@ 0x0000001C) PTP Timer Pulse Latch Second n Register (n = + * 0 to 3) */ + + struct + { + __IOM uint32_t LATSEC : 32; /*!< [31..0] LATSEC */ + } LATSEC_b; + }; + + union + { + __IOM uint32_t LATNS; /*!< (@ 0x00000020) PTP Timer Pulse Latch Nanosecond n Register (n + * = 0 to 3) */ + + struct + { + __IOM uint32_t LATNS : 32; /*!< [31..0] LATNS */ + } LATNS_b; + }; + __IM uint32_t RESERVED[55]; +} R_GMAC_PTP_SWTM_Type; /*!< Size = 256 (0x100) */ + +/** + * @brief R_ESC_FMMU [FMMU] (FMMU [0..7] Registers (n = 0 to 7)) + */ +typedef struct +{ + union + { + __IM uint32_t L_START_ADR; /*!< (@ 0x00000000) FMMU Logical Start Address n Register (n = 0 + * to 7) */ + + struct + { + __IM uint32_t LSTAADR : 32; /*!< [31..0] Logical Start Address Setting */ + } L_START_ADR_b; + }; + + union + { + __IM uint16_t LEN; /*!< (@ 0x00000004) FMMU Length n Register (n = 0 to 7) */ + + struct + { + __IM uint16_t FMMULEN : 16; /*!< [15..0] Area Size Specification */ + } LEN_b; + }; + + union + { + __IM uint8_t L_START_BIT; /*!< (@ 0x00000006) FMMU Logical Start Bit n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t LSTABIT : 3; /*!< [2..0] Start Bit Setting */ + uint8_t : 5; + } L_START_BIT_b; + }; + + union + { + __IM uint8_t L_STOP_BIT; /*!< (@ 0x00000007) FMMU Logical Stop Bit n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t LSTPBIT : 3; /*!< [2..0] Last Bit Setting */ + uint8_t : 5; + } L_STOP_BIT_b; + }; + + union + { + __IM uint16_t P_START_ADR; /*!< (@ 0x00000008) FMMU Physical Start Address n Register (n = 0 + * to 7) */ + + struct + { + __IM uint16_t PHYSTAADR : 16; /*!< [15..0] Physical Start Address Setting */ + } P_START_ADR_b; + }; + + union + { + __IM uint8_t P_START_BIT; /*!< (@ 0x0000000A) FMMU Physical Start Bit n Register (n = 0 to + * 7) */ + + struct + { + __IM uint8_t PHYSTABIT : 3; /*!< [2..0] Physical Start Bit Setting */ + uint8_t : 5; + } P_START_BIT_b; + }; + + union + { + __IM uint8_t TYPE; /*!< (@ 0x0000000B) FMMU Type n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t READ : 1; /*!< [0..0] Read Access Mapping Setting */ + __IM uint8_t WRITE : 1; /*!< [1..1] Write Access Mapping Setting */ + uint8_t : 6; + } TYPE_b; + }; + + union + { + __IM uint8_t ACT; /*!< (@ 0x0000000C) FMMU Activate n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t ACTIVATE : 1; /*!< [0..0] FMMU Enable/Disable */ + uint8_t : 7; + } ACT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; +} R_ESC_FMMU_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ESC_SM [SM] (SyncManager [0..7] Registers (n = 0 to 7)) + */ +typedef struct +{ + union + { + __IM uint16_t P_START_ADR; /*!< (@ 0x00000000) SyncManager Physical Start Address n Register + * (n = 0 to 7) */ + + struct + { + __IM uint16_t SMSTAADDR : 16; /*!< [15..0] Physical Start Address Setting */ + } P_START_ADR_b; + }; + + union + { + __IM uint16_t LEN; /*!< (@ 0x00000002) SyncManager Length n Register (n = 0 to 7) */ + + struct + { + __IM uint16_t SMLEN : 16; /*!< [15..0] Area Size Setting */ + } LEN_b; + }; + + union + { + __IM uint8_t CONTROL; /*!< (@ 0x00000004) SyncManager Control n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t OPEMODE : 2; /*!< [1..0] Operating Mode Setting */ + __IM uint8_t DIR : 2; /*!< [3..2] Transfer Direction Setting */ + __IM uint8_t IRQECAT : 1; /*!< [4..4] ECAT Event Interrupt Setting */ + __IM uint8_t IRQPDI : 1; /*!< [5..5] AL Event Interrupt Setting */ + __IM uint8_t WDTRGEN : 1; /*!< [6..6] Watchdog Trigger Setting */ + uint8_t : 1; + } CONTROL_b; + }; + + union + { + __IM uint8_t STATUS; /*!< (@ 0x00000005) SyncManager Status n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t INTWR : 1; /*!< [0..0] Write Complete Interrupt State Indication */ + __IM uint8_t INTRD : 1; /*!< [1..1] Read Complete Interrupt State Indication */ + uint8_t : 1; + __IM uint8_t MAILBOX : 1; /*!< [3..3] Mailbox Status Indication */ + __IM uint8_t BUFFERED : 2; /*!< [5..4] Buffer Status Indication */ + __IM uint8_t RDBUF : 1; /*!< [6..6] Read State Indication */ + __IM uint8_t WRBUF : 1; /*!< [7..7] Write State Indication */ + } STATUS_b; + }; + + union + { + __IM uint8_t ACT; /*!< (@ 0x00000006) SyncManager Activate n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t SMEN : 1; /*!< [0..0] SyncManager Enable/Disable */ + __IM uint8_t REPEATREQ : 1; /*!< [1..1] Repeat Request */ + uint8_t : 4; + __IM uint8_t LATCHECAT : 1; /*!< [6..6] ECAT Latch Event Specification */ + __IM uint8_t LATCHPDI : 1; /*!< [7..7] PDI Latch Event Specification */ + } ACT_b; + }; + + union + { + __IOM uint8_t PDI_CONT; /*!< (@ 0x00000007) SyncManager PDI Control n Register (n = 0 to + * 7) */ + + struct + { + __IOM uint8_t DEACTIVE : 1; /*!< [0..0] SyncManager Operation Indication/Setting */ + __IOM uint8_t REPEATACK : 1; /*!< [1..1] Repeat Acknowledge */ + uint8_t : 6; + } PDI_CONT_b; + }; +} R_ESC_SM_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_USBF_PIPE_TR [PIPE_TR] (PIPEn Transaction Counter Registers (n=1-5)) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPEn Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) PIPEn Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USBF_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USBF_CHa_N [N] (Address Registers n (n=0-1)) + */ +typedef struct +{ + union + { + __IOM uint32_t SA; /*!< (@ 0x00000000) Next Source Address Register */ + + struct + { + __IOM uint32_t SAWD : 32; /*!< [31..0] Source Address or Write Data */ + } SA_b; + }; + + union + { + __IOM uint32_t DA; /*!< (@ 0x00000004) Next Destination Address Register */ + + struct + { + __IOM uint32_t DA : 32; /*!< [31..0] Destination Address */ + } DA_b; + }; + + union + { + __IOM uint32_t TB; /*!< (@ 0x00000008) Next Transaction Byte Register */ + + struct + { + __IOM uint32_t TB : 32; /*!< [31..0] Transaction Byte */ + } TB_b; + }; +} R_USBF_CHa_N_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_USBF_CHa [CHa] (Next Register Set) + */ +typedef struct +{ + __IOM R_USBF_CHa_N_Type N[2]; /*!< (@ 0x00000000) Address Registers n (n=0-1) */ + + union + { + __IM uint32_t CRSA; /*!< (@ 0x00000018) Current Source Address Register */ + + struct + { + __IM uint32_t CRSA : 32; /*!< [31..0] Source Address */ + } CRSA_b; + }; + + union + { + __IM uint32_t CRDA; /*!< (@ 0x0000001C) Current Destination Address Register */ + + struct + { + __IM uint32_t CRDA : 32; /*!< [31..0] Destination Address */ + } CRDA_b; + }; + + union + { + __IM uint32_t CRTB; /*!< (@ 0x00000020) Current Transaction Byte Register */ + + struct + { + __IM uint32_t CRTB : 32; /*!< [31..0] Transaction Byte */ + } CRTB_b; + }; + + union + { + __IM uint32_t CHSTAT; /*!< (@ 0x00000024) Channel Status Register */ + + struct + { + __IM uint32_t EN : 1; /*!< [0..0] Enable */ + __IM uint32_t RQST : 1; /*!< [1..1] Request */ + __IM uint32_t TACT : 1; /*!< [2..2] Transaction Active */ + __IM uint32_t SUS : 1; /*!< [3..3] Suspend */ + __IM uint32_t ER : 1; /*!< [4..4] Error */ + __IM uint32_t END : 1; /*!< [5..5] USB_FDMAn Interrupted */ + __IM uint32_t TC : 1; /*!< [6..6] Terminal Count */ + __IM uint32_t SR : 1; /*!< [7..7] Selected Register Set */ + __IM uint32_t DL : 1; /*!< [8..8] Descriptor Load */ + __IM uint32_t DW : 1; /*!< [9..9] Descriptor WriteBack */ + __IM uint32_t DER : 1; /*!< [10..10] Descriptor Error */ + __IM uint32_t MODE : 1; /*!< [11..11] DMA Mode */ + uint32_t : 4; + __IM uint32_t INTM : 1; /*!< [16..16] Interrupt Mask */ + __IM uint32_t DMARQM : 1; /*!< [17..17] DMAREQ Mask */ + __IM uint32_t SWPRQ : 1; /*!< [18..18] Sweep Request */ + uint32_t : 5; + __IM uint32_t DNUM : 8; /*!< [31..24] Data Number */ + } CHSTAT_b; + }; + + union + { + __OM uint32_t CHCTRL; /*!< (@ 0x00000028) Channel Control Register */ + + struct + { + __OM uint32_t SETEN : 1; /*!< [0..0] Set Enable */ + __OM uint32_t CLREN : 1; /*!< [1..1] Clear Enable */ + __OM uint32_t STG : 1; /*!< [2..2] Software Trigger */ + __OM uint32_t SWRST : 1; /*!< [3..3] Software Reset */ + __OM uint32_t CLRRQ : 1; /*!< [4..4] Clear Request */ + __OM uint32_t CLREND : 1; /*!< [5..5] Clear End */ + __OM uint32_t CLRTC : 1; /*!< [6..6] Clear TC */ + __OM uint32_t CLRDER : 1; /*!< [7..7] Clear DER */ + __OM uint32_t SETSUS : 1; /*!< [8..8] Set Suspend */ + __OM uint32_t CLRSUS : 1; /*!< [9..9] Clear Suspend */ + uint32_t : 2; + __OM uint32_t SETREN : 1; /*!< [12..12] Set Register Set Enable */ + uint32_t : 1; + __OM uint32_t SETSSWPRQ : 1; /*!< [14..14] Set Software Sweep Request */ + uint32_t : 1; + __OM uint32_t SETINTM : 1; /*!< [16..16] Set Interrupt Mask */ + __OM uint32_t CLRINTM : 1; /*!< [17..17] Clear Interrupt Mask */ + __OM uint32_t SETDMARQM : 1; /*!< [18..18] SET DMAREQ Mask */ + __OM uint32_t CLRDMARQM : 1; /*!< [19..19] Clear DMAREQ Mask */ + uint32_t : 12; + } CHCTRL_b; + }; + + union + { + __IOM uint32_t CHCFG; /*!< (@ 0x0000002C) Channel Configuration Register */ + + struct + { + __IOM uint32_t SEL : 1; /*!< [0..0] Terminal Select */ + uint32_t : 2; + __IOM uint32_t REQD : 1; /*!< [3..3] Request Direction */ + __IOM uint32_t LOEN : 1; /*!< [4..4] Sets the transfer request signal between the USB control + * and the DMAC. */ + __IOM uint32_t HIEN : 1; /*!< [5..5] Sets the transfer request signal between the USB control + * and the DMAC. */ + __IOM uint32_t LVL : 1; /*!< [6..6] Sets the transfer request signal between the USB control + * and the DMAC. */ + uint32_t : 1; + __IOM uint32_t AM : 3; /*!< [10..8] These bits set the transfer request signal between the + * USB control and the DMAC. */ + __IOM uint32_t DRRP : 1; /*!< [11..11] Descriptor Read Repeat */ + __IOM uint32_t SDS : 4; /*!< [15..12] Source Data Size */ + __IOM uint32_t DDS : 4; /*!< [19..16] Destination Data Size */ + __IOM uint32_t SAD : 1; /*!< [20..20] Source Address Direction */ + __IOM uint32_t DAD : 1; /*!< [21..21] Destination Address Direction */ + __IOM uint32_t TM : 1; /*!< [22..22] Sets the transfer request signal between the USB control + * and the DMAC. */ + __IOM uint32_t WONLY : 1; /*!< [23..23] Write Only Mode */ + __IOM uint32_t DEM : 1; /*!< [24..24] USB_FDMAn Mask */ + uint32_t : 1; + __IOM uint32_t DIM : 1; /*!< [26..26] Descriptor Interrupt Mask */ + __IOM uint32_t SBE : 1; /*!< [27..27] Sweep Buffer Enable */ + __IOM uint32_t RSEL : 1; /*!< [28..28] Register Set Select */ + __IOM uint32_t RSW : 1; /*!< [29..29] Register Select Switch */ + __IOM uint32_t REN : 1; /*!< [30..30] Register Set Enable */ + __IOM uint32_t DMS : 1; /*!< [31..31] DMA Mode Select */ + } CHCFG_b; + }; + + union + { + __IOM uint32_t CHITVL; /*!< (@ 0x00000030) Channel Interval Register */ + + struct + { + __IOM uint32_t ITVL : 16; /*!< [15..0] Interval */ + uint32_t : 16; + } CHITVL_b; + }; + + union + { + __IOM uint32_t CHEXT; /*!< (@ 0x00000034) Channel Extension Register */ + + struct + { + __IOM uint32_t SPR : 4; /*!< [3..0] Source PROT */ + uint32_t : 4; + __IOM uint32_t DPR : 4; /*!< [11..8] Destination PROT */ + uint32_t : 20; + } CHEXT_b; + }; + + union + { + __IOM uint32_t NXLA; /*!< (@ 0x00000038) Next Link Address Register */ + + struct + { + __IOM uint32_t NXLA : 32; /*!< [31..0] Next Link Address */ + } NXLA_b; + }; + + union + { + __IM uint32_t CRLA; /*!< (@ 0x0000003C) Current Link Address Register */ + + struct + { + __IM uint32_t CRLA : 32; /*!< [31..0] Current Link Address */ + } CRLA_b; + }; +} R_USBF_CHa_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_USBF_CHb [CHb] (Skip Register Set) + */ +typedef struct +{ + union + { + __IOM uint32_t SCNT; /*!< (@ 0x00000000) Source Continuous Register */ + + struct + { + __IOM uint32_t SCNT : 32; /*!< [31..0] Source Continuous */ + } SCNT_b; + }; + + union + { + __IOM uint32_t SSKP; /*!< (@ 0x00000004) Source Skip Register */ + + struct + { + __IOM uint32_t SSKP : 32; /*!< [31..0] Source Skip */ + } SSKP_b; + }; + + union + { + __IOM uint32_t DCNT; /*!< (@ 0x00000008) Destination Continuous Register */ + + struct + { + __IOM uint32_t DCNT : 32; /*!< [31..0] Destination Continuous */ + } DCNT_b; + }; + + union + { + __IOM uint32_t DSKP; /*!< (@ 0x0000000C) Destination Skip Register */ + + struct + { + __IOM uint32_t DSKP : 32; /*!< [31..0] Destination Skip */ + } DSKP_b; + }; + __IM uint32_t RESERVED[4]; +} R_USBF_CHb_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_XSPI0_CSa [CSa] (xSPI Command Map Configuration Register [0..1]) + */ +typedef struct +{ + union + { + __IOM uint32_t CMCFG0; /*!< (@ 0x00000000) xSPI Command Map Configuration Register 0 CSn */ + + struct + { + __IOM uint32_t FFMT : 2; /*!< [1..0] Frame format */ + __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size */ + uint32_t : 12; + __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable */ + __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code */ + } CMCFG0_b; + }; + + union + { + __IOM uint32_t CMCFG1; /*!< (@ 0x00000004) xSPI Command Map Configuration Register 1 CSn */ + + struct + { + __IOM uint32_t RDCMD : 16; /*!< [15..0] Read command */ + __IOM uint32_t RDLATE : 5; /*!< [20..16] Read latency cycle */ + uint32_t : 11; + } CMCFG1_b; + }; + + union + { + __IOM uint32_t CMCFG2; /*!< (@ 0x00000008) xSPI Command Map Configuration Register 2 CSn */ + + struct + { + __IOM uint32_t WRCMD : 16; /*!< [15..0] Write command */ + __IOM uint32_t WRLATE : 5; /*!< [20..16] Write latency cycle */ + uint32_t : 11; + } CMCFG2_b; + }; + __IM uint32_t RESERVED; +} R_XSPI0_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_BUF [BUF] (xSPI Command Manual Buf [0..3]) + */ +typedef struct +{ + union + { + __IOM uint32_t CDT; /*!< (@ 0x00000000) xSPI Command Manual Type Buf */ + + struct + { + __IOM uint32_t CMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t ADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t DATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + __IOM uint32_t LATE : 5; /*!< [13..9] Latency cycle */ + uint32_t : 1; + __IOM uint32_t TRTYPE : 1; /*!< [15..15] Transaction Type */ + __IOM uint32_t CMD : 16; /*!< [31..16] Command (1-2 bytes) */ + } CDT_b; + }; + + union + { + __IOM uint32_t CDA; /*!< (@ 0x00000004) xSPI Command Manual Address Buf */ + + struct + { + __IOM uint32_t ADD : 32; /*!< [31..0] Address */ + } CDA_b; + }; + + union + { + __IOM uint32_t CDD0; /*!< (@ 0x00000008) xSPI Command Manual Data 0 Buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD0_b; + }; + + union + { + __IOM uint32_t CDD1; /*!< (@ 0x0000000C) xSPI Command Manual Data 1 Buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD1_b; + }; +} R_XSPI0_BUF_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_CSb [CSb] (xSPI Command Calibration Control register [0..1]) + */ +typedef struct +{ + union + { + __IOM uint32_t CCCTL0; /*!< (@ 0x00000000) xSPI Command Calibration Control Register 0 CSn */ + + struct + { + __IOM uint32_t CAEN : 1; /*!< [0..0] Automatic Calibration Enable */ + __IOM uint32_t CANOWR : 1; /*!< [1..1] Calibration no write mode */ + uint32_t : 6; + __IOM uint32_t CAITV : 5; /*!< [12..8] Calibration interval */ + uint32_t : 3; + __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value */ + uint32_t : 3; + __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value */ + uint32_t : 3; + } CCCTL0_b; + }; + + union + { + __IOM uint32_t CCCTL1; /*!< (@ 0x00000004) xSPI Command Calibration Control Register 1 CSn */ + + struct + { + __IOM uint32_t CACMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t CAADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + uint32_t : 7; + __IOM uint32_t CAWRLATE : 5; /*!< [20..16] Write Latency cycle */ + uint32_t : 3; + __IOM uint32_t CARDLATE : 5; /*!< [28..24] Read Latency cycle */ + uint32_t : 3; + } CCCTL1_b; + }; + + union + { + __IOM uint32_t CCCTL2; /*!< (@ 0x00000008) xSPI Command Calibration Control Register 2 CSn */ + + struct + { + __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command */ + __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command */ + } CCCTL2_b; + }; + + union + { + __IOM uint32_t CCCTL3; /*!< (@ 0x0000000C) xSPI Command Calibration Control Register 3 CSn */ + + struct + { + __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address */ + } CCCTL3_b; + }; + + union + { + __IOM uint32_t CCCTL4; /*!< (@ 0x00000010) xSPI Command Calibration Control Register 4 CSn */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL4_b; + }; + + union + { + __IOM uint32_t CCCTL5; /*!< (@ 0x00000014) xSPI Command Calibration Control Register 5 CSn */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL5_b; + }; + + union + { + __IOM uint32_t CCCTL6; /*!< (@ 0x00000018) xSPI Command Calibration Control Register 6 CSn */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL6_b; + }; + + union + { + __IOM uint32_t CCCTL7; /*!< (@ 0x0000001C) xSPI Command Calibration Control Register 7 CSn */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL7_b; + }; +} R_XSPI0_CSb_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_SYSRAM0_W [W] (System SRAM Wn Registers (n = 0 to 3)) + */ +typedef struct +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Indicate Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] 1-Bit ECC Error Detection/Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-Bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] 1-Bit ECC Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] 2-Bit ECC Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] 1-Bit ECC Error Correction Enable */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Determination Enable */ + __IOM uint32_t ECTHM : 1; /*!< [7..7] ECC Function Through Mode Enable */ + uint32_t : 1; + __IOM uint32_t ECER1C : 1; /*!< [9..9] 1-Bit ECC Error Detection Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-Bit ECC Error Detection Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Error Address Capture Overflow Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Selection */ + __IM uint32_t ECEDF0 : 2; /*!< [17..16] ECC Error Address Capture Flag m (m = 0) */ + __IM uint32_t ECEDF1 : 2; /*!< [19..18] ECC Error Address Capture Flag m (m = 1) */ + __IM uint32_t ECEDF2 : 2; /*!< [21..20] ECC Error Address Capture Flag m (m = 2) */ + __IM uint32_t ECEDF3 : 2; /*!< [23..22] ECC Error Address Capture Flag m (m = 3) */ + __IM uint32_t ECEDF4 : 2; /*!< [25..24] ECC Error Address Capture Flag m (m = 4) */ + __IM uint32_t ECEDF5 : 2; /*!< [27..26] ECC Error Address Capture Flag m (m = 5) */ + __IM uint32_t ECEDF6 : 2; /*!< [29..28] ECC Error Address Capture Flag m (m = 6) */ + __IM uint32_t ECEDF7 : 2; /*!< [31..30] ECC Error Address Capture Flag m (m = 7) */ + } EC710CTL_b; + }; + + union + { + __IOM uint32_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + __IOM uint32_t ECREIS : 1; /*!< [0..0] ECC Redundancy Bit Input Data Select */ + __IOM uint32_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + __IOM uint32_t ECENS : 1; /*!< [2..2] ECC Encode Input Select */ + __IOM uint32_t ECREOS : 1; /*!< [3..3] ECC Redundancy Bit Output Data Select */ + __IOM uint32_t ECTRRS : 1; /*!< [4..4] RAM Read Test Mode Select */ + uint32_t : 2; + __IOM uint32_t ECTMCE : 1; /*!< [7..7] Test Mode Enable */ + uint32_t : 6; + __IOM uint32_t ETMA : 2; /*!< [15..14] ECTMCE Write Enable */ + uint32_t : 16; + } EC710TMC_b; + }; + + union + { + __IOM uint32_t EC710TRC; /*!< (@ 0x00000008) ECC Redundancy Bit Data Control Test Register */ + + struct + { + __IOM uint32_t ECERDB : 7; /*!< [6..0] ECC Redundancy Bit Input/Output Substitute Buffer Register */ + uint32_t : 1; + __IM uint32_t ECECRD : 7; /*!< [14..8] ECC Encode Test Register */ + uint32_t : 1; + __IM uint32_t ECHORD : 7; /*!< [22..16] ECC 7-Redundancy-Bit Data Retain Test Register */ + uint32_t : 1; + __IM uint32_t ECSYND : 7; /*!< [30..24] ECC Decode Syndrome Register */ + uint32_t : 1; + } EC710TRC_b; + }; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Encode/Decode Input/Output Switchover Test + * Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] 32-Bit Data Test Register for ECC Encode/Decode */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD[8]; /*!< (@ 0x00000010) ECC Error Address [0..7] Register 0 */ + + struct + { + __IM uint32_t ECEAD : 15; /*!< [14..0] Bit Error Address */ + uint32_t : 17; + } EC710EAD_b[8]; + }; + __IM uint32_t RESERVED[4]; +} R_SYSRAM0_W_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_MPU0_RGN [RGN] (Master MPU Safety Region Start Address Register [0..7]) + */ +typedef struct +{ + union + { + __IOM uint32_t STADD; /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register */ + + struct + { + __IOM uint32_t RDPR : 1; /*!< [0..0] Enable read protection for region m of master MPU */ + __IOM uint32_t WRPR : 1; /*!< [1..1] Enable write protection for region m of master MPU */ + uint32_t : 8; + __IOM uint32_t STADDR : 22; /*!< [31..10] Start address for MPU region */ + } STADD_b; + }; + + union + { + __IOM uint32_t ENDADD; /*!< (@ 0x00000004) Master MPU Safety Region End Address Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t ENDADDR : 22; /*!< [31..10] End address for MPU region */ + } ENDADD_b; + }; + __IM uint32_t RESERVED[2]; +} R_MPU0_RGN_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_DSMIF0_CH_TR [TR] (Overcurrent Threshold Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DSOCL; /*!< (@ 0x00000000) Overcurrent Low Threshold Register */ + + struct + { + __IOM uint32_t OCMPTBL0 : 16; /*!< [15..0] Overcurrent detection lower limit 0 */ + uint32_t : 16; + } DSOCL_b; + }; + + union + { + __IOM uint32_t DSOCH; /*!< (@ 0x00000004) Overcurrent High Threshold Register */ + + struct + { + __IOM uint32_t OCMPTBH0 : 16; /*!< [15..0] Overcurrent detection upper limit 0 */ + uint32_t : 16; + } DSOCH_b; + }; +} R_DSMIF0_CH_TR_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_DSMIF0_CH_DR [DR] (Overcurrent Threshold Registers) + */ +typedef struct +{ + union + { + __IM uint32_t DSCOC; /*!< (@ 0x00000000) Capture Overcurrent Data Register */ + + struct + { + __IM uint32_t CODR0 : 16; /*!< [15..0] Capture overcurrent data 0 */ + uint32_t : 16; + } DSCOC_b; + }; +} R_DSMIF0_CH_DR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_DSMIF0_CH [CH] (Channel Registers [0..2]) + */ +typedef struct +{ + union + { + __IOM uint32_t DSICR; /*!< (@ 0x00000000) Interrupt Control Register */ + + struct + { + __IOM uint32_t IUE : 1; /*!< [0..0] Current data register update interrupt enable */ + __IOM uint32_t IAUE : 1; /*!< [1..1] Capture current data register A update interrupt enable */ + __IOM uint32_t IBUE : 1; /*!< [2..2] Capture current data register B update interrupt enable */ + __IOM uint32_t ISE : 1; /*!< [3..3] Short circuit detection error interrupt enable bit */ + uint32_t : 4; + __IOM uint32_t IOEL0 : 1; /*!< [8..8] Overcurrent lower limit detection interrupt 0 */ + __IOM uint32_t IOEH0 : 1; /*!< [9..9] Overcurrent upper limit exceeded detection interrupt + * 0 */ + __IOM uint32_t IOEL1 : 1; /*!< [10..10] Overcurrent lower limit detection interrupt 1 */ + __IOM uint32_t IOEH1 : 1; /*!< [11..11] Overcurrent upper limit exceeded detection interrupt + * 1 */ + __IOM uint32_t IOEL2 : 1; /*!< [12..12] Overcurrent lower limit detection interrupt 2 */ + __IOM uint32_t IOEH2 : 1; /*!< [13..13] Overcurrent upper limit exceeded detection interrupt + * 2 */ + uint32_t : 2; + __IOM uint32_t OWNE0 : 1; /*!< [16..16] Overcurrent detection window notification 0 output + * enable */ + __IOM uint32_t OWNE1 : 1; /*!< [17..17] Overcurrent detection window notification 1 output + * enable */ + __IOM uint32_t OWNE2 : 1; /*!< [18..18] Overcurrent detection window notification 2 output + * enable */ + __IOM uint32_t OWNE3 : 1; /*!< [19..19] Overcurrent detection window notification 3 output + * enable */ + uint32_t : 12; + } DSICR_b; + }; + + union + { + __IOM uint32_t DSCMCCR; /*!< (@ 0x00000004) Current Measurement Clock Control Register */ + + struct + { + __IOM uint32_t CKDIR : 1; /*!< [0..0] A/D conversion clock master/slave switching */ + uint32_t : 6; + __IOM uint32_t SEDGE : 1; /*!< [7..7] Sampling edge selection */ + __IOM uint32_t CKDIV : 6; /*!< [13..8] A/D conversion clock division ratio */ + uint32_t : 18; + } DSCMCCR_b; + }; + + union + { + __IOM uint32_t DSCMFCR; /*!< (@ 0x00000008) Current Measurement Filter Control Register */ + + struct + { + __IOM uint32_t CMSINC : 2; /*!< [1..0] Current measurement filter order setting */ + uint32_t : 6; + __IOM uint32_t CMDEC : 8; /*!< [15..8] Decimation ratio selection for current measurement */ + __IOM uint32_t CMSH : 5; /*!< [20..16] Data shift setting for current measurement */ + uint32_t : 11; + } DSCMFCR_b; + }; + + union + { + __IOM uint32_t DSCMCTCR; /*!< (@ 0x0000000C) Current Measurement Capture Trigger Control Register */ + + struct + { + __IOM uint32_t CTSELA : 3; /*!< [2..0] Current capture trigger A selection bit */ + uint32_t : 5; + __IOM uint32_t CTSELB : 3; /*!< [10..8] Current capture trigger B selection bit */ + uint32_t : 5; + __IOM uint32_t DITSEL : 2; /*!< [17..16] Current measurement filter initialization trigger selection + * bit for frequency division counter for decimation. */ + uint32_t : 5; + __IOM uint32_t DEDGE : 1; /*!< [23..23] Current measurement filter initialization trigger for + * division counter for decimation edge selection bit. The + * trigger from ELC is usually used positive edge. Change + * from the initial value if necessary. */ + uint32_t : 8; + } DSCMCTCR_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t DSEDCR; /*!< (@ 0x00000020) Error Detect Control Register */ + + struct + { + __IOM uint32_t SDE : 1; /*!< [0..0] Short circuit detection enable bit */ + uint32_t : 31; + } DSEDCR_b; + }; + + union + { + __IOM uint32_t DSSCTSR; /*!< (@ 0x00000024) Short Circuit Threshold Setting Register */ + + struct + { + __IOM uint32_t SCNTL : 13; /*!< [12..0] Short circuit detection low continuous detection count */ + uint32_t : 3; + __IOM uint32_t SCNTH : 13; /*!< [28..16] Short circuit detection high continuous detection count */ + uint32_t : 3; + } DSSCTSR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t DSOCFCR; /*!< (@ 0x00000030) Overcurrent Detect Filter Control Register */ + + struct + { + __IOM uint32_t OCSINC : 2; /*!< [1..0] Overcurrent detection filter order setting */ + uint32_t : 6; + __IOM uint32_t OCDEC : 8; /*!< [15..8] Decimation ratio selection for overcurrent detection */ + __IOM uint32_t OCSH : 5; /*!< [20..16] Data shift setting for overcurrent detection */ + uint32_t : 11; + } DSOCFCR_b; + }; + + union + { + __IOM uint32_t DSODCR; /*!< (@ 0x00000034) Overcurrent Detect Control Register */ + + struct + { + __IOM uint32_t ODEL0 : 1; /*!< [0..0] Current lower limit detection 0 enable */ + __IOM uint32_t ODEH0 : 1; /*!< [1..1] Current upper limit exceeded detection 0 enable */ + __IOM uint32_t ODEL1 : 1; /*!< [2..2] Current lower limit detection 1 enable */ + __IOM uint32_t ODEH1 : 1; /*!< [3..3] Current upper limit exceeded detection 1 enable */ + __IOM uint32_t ODEL2 : 1; /*!< [4..4] Current lower limit detection 2 enable */ + __IOM uint32_t ODEH2 : 1; /*!< [5..5] Current upper limit exceeded detection 2 enable */ + uint32_t : 2; + __IOM uint32_t OWFE0 : 1; /*!< [8..8] Overcurrent lower limit detection interrupt 0 */ + __IOM uint32_t OWFE1 : 1; /*!< [9..9] Overcurrent detection window function 0 enable */ + __IOM uint32_t OWFE2 : 1; /*!< [10..10] Overcurrent detection window function 1 enable */ + __IOM uint32_t OWFE3 : 1; /*!< [11..11] Overcurrent detection window function 2 enable */ + uint32_t : 20; + } DSODCR_b; + }; + + union + { + __IOM uint32_t DSODWCR; /*!< (@ 0x00000038) Overcurrent Detect Window Control Register */ + + struct + { + __IOM uint32_t OWNM0 : 1; /*!< [0..0] Channel n overcurrent detection window notification 0 + * mode select */ + __IOM uint32_t OWNM1 : 1; /*!< [1..1] Channel n overcurrent detection window notification 1 + * mode select */ + __IOM uint32_t OWNM2 : 1; /*!< [2..2] Channel n overcurrent detection window notification 2 + * mode select */ + __IOM uint32_t OWNM3 : 4; /*!< [6..3] Channel n overcurrent detection window notification 3 + * mode select */ + uint32_t : 25; + } DSODWCR_b; + }; + __IM uint32_t RESERVED2[25]; + __IOM R_DSMIF0_CH_TR_Type TR[3]; /*!< (@ 0x000000A0) Overcurrent Threshold Registers */ + __IM uint32_t RESERVED3[10]; + + union + { + __IOM uint32_t DSCSTRTR; /*!< (@ 0x000000E0) Software Start Trigger Register */ + + struct + { + __IOM uint32_t STRTRG : 1; /*!< [0..0] Channel start trigger */ + uint32_t : 31; + } DSCSTRTR_b; + }; + + union + { + __IOM uint32_t DSCSTPTR; /*!< (@ 0x000000E4) Software Stop Trigger Register */ + + struct + { + __IOM uint32_t STPTRG : 1; /*!< [0..0] Channel stop trigger */ + uint32_t : 31; + } DSCSTPTR_b; + }; + __IM uint32_t RESERVED4[2]; + + union + { + __IM uint32_t DSCDR; /*!< (@ 0x000000F0) Current Data Register */ + + struct + { + __IM uint32_t ADDR : 16; /*!< [15..0] Current data */ + uint32_t : 16; + } DSCDR_b; + }; + + union + { + __IM uint32_t DSCCDRA; /*!< (@ 0x000000F4) Capture Current Data Register A */ + + struct + { + __IM uint32_t CDRA : 16; /*!< [15..0] Capture current data A */ + uint32_t : 16; + } DSCCDRA_b; + }; + + union + { + __IM uint32_t DSCCDRB; /*!< (@ 0x000000F8) Capture Current Data Register B */ + + struct + { + __IM uint32_t CDRB : 16; /*!< [15..0] Capture current data B */ + uint32_t : 16; + } DSCCDRB_b; + }; + + union + { + __IM uint32_t DSOCDR; /*!< (@ 0x000000FC) Overcurrent Data Register */ + + struct + { + __IM uint32_t ODR : 16; /*!< [15..0] Overcurrent data */ + uint32_t : 16; + } DSOCDR_b; + }; + __IOM R_DSMIF0_CH_DR_Type DR[3]; /*!< (@ 0x00000100) Overcurrent Threshold Registers */ + __IM uint32_t RESERVED5[5]; + + union + { + __IM uint32_t DSCSR; /*!< (@ 0x00000120) Status Register */ + + struct + { + __IM uint32_t DUF : 1; /*!< [0..0] Channel n data update flag */ + __IM uint32_t CAUF : 1; /*!< [1..1] Channel n capture data A update flag */ + __IM uint32_t CBUF : 1; /*!< [2..2] Channel n capture data B update flag */ + __IM uint32_t SCF : 1; /*!< [3..3] Channel n short circuit detection flag */ + uint32_t : 3; + __IM uint32_t CHSTATE : 1; /*!< [7..7] Channel n state */ + __IM uint32_t OC0FL : 1; /*!< [8..8] Channel n overcurrent lower limit detection 0 flag */ + __IM uint32_t OC0FH : 1; /*!< [9..9] Channel n overcurrent upper limit exceeded 0 flag */ + __IM uint32_t OC1FL : 1; /*!< [10..10] Channel n overcurrent lower limit detection 1 flag */ + __IM uint32_t OC1FH : 1; /*!< [11..11] Channel n overcurrent upper limit exceeded 1 flag */ + __IM uint32_t OC2FL : 1; /*!< [12..12] Channel n overcurrent lower limit detection 2 flag */ + __IM uint32_t OC2FH : 1; /*!< [13..13] Channel n overcurrent upper limit exceeded 2 flag */ + uint32_t : 2; + __IM uint32_t OWD0N : 1; /*!< [16..16] Channel n overcurrent detection window notification + * 0 */ + __IM uint32_t OWD1N : 1; /*!< [17..17] Channel n overcurrent detection window notification + * 1 */ + __IM uint32_t OWD2N : 1; /*!< [18..18] Channel n overcurrent detection window notification + * 2 */ + __IM uint32_t OWD3N : 1; /*!< [19..19] Channel n overcurrent detection window notification + * 3 */ + uint32_t : 4; + __IM uint32_t OC0CMPL : 1; /*!< [24..24] Channel n overcurrent detect 0 lower limit compare + * result */ + __IM uint32_t OC0CMPH : 1; /*!< [25..25] Channel n overcurrent detect 0 upper limit compare + * result */ + __IM uint32_t OC1CMPL : 1; /*!< [26..26] Channel n overcurrent detect 1 lower limit compare + * result */ + __IM uint32_t OC1CMPH : 1; /*!< [27..27] Channel n overcurrent detect 1 upper limit compare + * result */ + __IM uint32_t OC2CMPL : 1; /*!< [28..28] Channel n overcurrent detect 2 lower limit compare + * result */ + __IM uint32_t OC2CMPH : 1; /*!< [29..29] Channel n overcurrent detect 2 upper limit compare + * result */ + uint32_t : 2; + } DSCSR_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __OM uint32_t DSCSCR; /*!< (@ 0x00000130) Status Clear Register */ + + struct + { + __OM uint32_t CLRDUF : 1; /*!< [0..0] Channel n data update flag clear */ + __OM uint32_t CLRCAUF : 1; /*!< [1..1] Channel n capture data A update flag clear */ + __OM uint32_t CLRCBUF : 1; /*!< [2..2] Channel n capture data B update flag clear */ + __OM uint32_t CLRSCF : 1; /*!< [3..3] Channel n short circuit detection flag clear */ + uint32_t : 4; + __OM uint32_t CLROC0FL : 1; /*!< [8..8] Channel n overcurrent lower limit detection flag 0 clear */ + __OM uint32_t CLROC0FH : 1; /*!< [9..9] Channel n overcurrent upper limit exceeded flag 0 clear */ + __OM uint32_t CLROC1FL : 1; /*!< [10..10] Channel n overcurrent lower limit detection flag 1 + * clear */ + __OM uint32_t CLROC1FH : 1; /*!< [11..11] Channel n overcurrent upper limit exceeded flag 1 clear */ + __OM uint32_t CLROC2FL : 1; /*!< [12..12] Channel n overcurrent lower limit detection flag 2 + * clear */ + __OM uint32_t CLROC2FH : 1; /*!< [13..13] Channel n overcurrent upper limit exceeded flag 2 clear */ + uint32_t : 2; + __OM uint32_t CLROWD0N : 1; /*!< [16..16] Channel n overcurrent detection window notification + * 0 flag clear */ + __OM uint32_t CLROWD1N : 1; /*!< [17..17] Channel n overcurrent detection window notification + * 1 flag clear */ + __OM uint32_t CLROWD2N : 1; /*!< [18..18] Channel n overcurrent detection window notification + * 2 flag clear */ + __OM uint32_t CLROWD3N : 1; /*!< [19..19] Channel n overcurrent detection window notification + * 3 flag clear */ + uint32_t : 12; + } DSCSCR_b; + }; + __IM uint32_t RESERVED7[3]; +} R_DSMIF0_CH_Type; /*!< Size = 320 (0x140) */ + +/** + * @brief R_BISS0_SCDATA [SCDATA] (Sensor Data [0..7]) + */ +typedef struct +{ + __IOM uint32_t L; /*!< (@ 0x00000000) Sensor Data L */ + __IOM uint32_t H; /*!< (@ 0x00000004) Sensor Data H */ +} R_BISS0_SCDATA_Type; /*!< Size = 8 (0x8) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_GPT7 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer 7 (R_GPT7) + */ + +typedef struct /*!< (@ 0x80000000) R_GPT7 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disabled */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disabled */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disabled */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disabled */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel 0 Count Start */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel 1 Count Start */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel 2 Count Start */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel 3 Count Start */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel 4 Count Start */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel 5 Count Start */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel 6 Count Start */ + uint32_t : 25; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel 0 Count Stop */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel 1 Count Stop */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel 2 Count Stop */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel 3 Count Stop */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel 4 Count Stop */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel 5 Count Stop */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel 6 Count Stop */ + uint32_t : 25; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel 0 Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel 1 Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel 2 Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel 3 Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel 4 Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel 5 Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel 6 Count Clear */ + uint32_t : 25; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAFR : 2; /*!< [1..0] SSGTRGAFR */ + __IOM uint32_t SSGTRGBFR : 2; /*!< [3..2] SSGTRGBFR */ + __IOM uint32_t SSGTRGCFR : 2; /*!< [5..4] SSGTRGCFR */ + __IOM uint32_t SSGTRGDFR : 2; /*!< [7..6] SSGTRGDFR */ + __IOM uint32_t SSCARBHL : 2; /*!< [9..8] SSCARBHL */ + __IOM uint32_t SSCAFBHL : 2; /*!< [11..10] SSCAFBHL */ + __IOM uint32_t SSCBRAHL : 2; /*!< [13..12] SSCBRAHL */ + __IOM uint32_t SSCBFAHL : 2; /*!< [15..14] SSCBFAHL */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] SSELCA */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] SSELCB */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] SSELCC */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] SSELCD */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] SSELCE */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] SSELCF */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] SSELCG */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] SSELCH */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Count Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAFR : 2; /*!< [1..0] PSGTRGAFR */ + __IOM uint32_t PSGTRGBFR : 2; /*!< [3..2] PSGTRGBFR */ + __IOM uint32_t PSGTRGCFR : 2; /*!< [5..4] PSGTRGCFR */ + __IOM uint32_t PSGTRGDFR : 2; /*!< [7..6] PSGTRGDFR */ + __IOM uint32_t PSCARBHL : 2; /*!< [9..8] PSCARBHL */ + __IOM uint32_t PSCAFBHL : 2; /*!< [11..10] PSCAFBHL */ + __IOM uint32_t PSCBRAHL : 2; /*!< [13..12] PSCBRAHL */ + __IOM uint32_t PSCBFAHL : 2; /*!< [15..14] PSCBFAHL */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] PSELCA */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] PSELCB */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] PSELCC */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] PSELCD */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] PSELCE */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] PSELCF */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] PSELCG */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] PSELCH */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] CSTOP */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAFR : 2; /*!< [1..0] CSGTRGAFR */ + __IOM uint32_t CSGTRGBFR : 2; /*!< [3..2] CSGTRGBFR */ + __IOM uint32_t CSGTRGCFR : 2; /*!< [5..4] CSGTRGCFR */ + __IOM uint32_t CSGTRGDFR : 2; /*!< [7..6] CSGTRGDFR */ + __IOM uint32_t CSCARBHL : 2; /*!< [9..8] CSCARBHL */ + __IOM uint32_t CSCAFBHL : 2; /*!< [11..10] CSCAFBHL */ + __IOM uint32_t CSCBRAHL : 2; /*!< [13..12] CSCBRAHL */ + __IOM uint32_t CSCBFAHL : 2; /*!< [15..14] CSCBFAHL */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] CSELCA */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] CSELCB */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] CSELCC */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] CSELCD */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] CSELCE */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] CSELCF */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] CSELCG */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] CSELCH */ + uint32_t : 7; + __IOM uint32_t CCLR : 1; /*!< [31..31] CCLR */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Count-Up Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAFR : 2; /*!< [1..0] USGTRGAFR */ + __IOM uint32_t USGTRGBFR : 2; /*!< [3..2] USGTRGBFR */ + __IOM uint32_t USGTRGCFR : 2; /*!< [5..4] USGTRGCFR */ + __IOM uint32_t USGTRGDFR : 2; /*!< [7..6] USGTRGDFR */ + __IOM uint32_t USCARBHL : 2; /*!< [9..8] USCARBHL */ + __IOM uint32_t USCAFBHL : 2; /*!< [11..10] USCAFBHL */ + __IOM uint32_t USCBRAHL : 2; /*!< [13..12] USCBRAHL */ + __IOM uint32_t USCBFAHL : 2; /*!< [15..14] USCBFAHL */ + __IOM uint32_t USELCA : 1; /*!< [16..16] USELCA */ + __IOM uint32_t USELCB : 1; /*!< [17..17] USELCB */ + __IOM uint32_t USELCC : 1; /*!< [18..18] USELCC */ + __IOM uint32_t USELCD : 1; /*!< [19..19] USELCD */ + __IOM uint32_t USELCE : 1; /*!< [20..20] USELCE */ + __IOM uint32_t USELCF : 1; /*!< [21..21] USELCF */ + __IOM uint32_t USELCG : 1; /*!< [22..22] USELCG */ + __IOM uint32_t USELCH : 1; /*!< [23..23] USELCH */ + uint32_t : 8; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Count-Down Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAFR : 2; /*!< [1..0] DSGTRGAFR */ + __IOM uint32_t DSGTRGBFR : 2; /*!< [3..2] DSGTRGBFR */ + __IOM uint32_t DSGTRGCFR : 2; /*!< [5..4] DSGTRGCFR */ + __IOM uint32_t DSGTRGDFR : 2; /*!< [7..6] DSGTRGDFR */ + __IOM uint32_t DSCARBHL : 2; /*!< [9..8] DSCARBHL */ + __IOM uint32_t DSCAFBHL : 2; /*!< [11..10] DSCAFBHL */ + __IOM uint32_t DSCBRAHL : 2; /*!< [13..12] DSCBRAHL */ + __IOM uint32_t DSCBFAHL : 2; /*!< [15..14] DSCBFAHL */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] DSELCA */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] DSELCB */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] DSELCC */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] DSELCD */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] DSELCE */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] DSELCF */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] DSELCG */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] DSELCH */ + uint32_t : 8; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAFR : 2; /*!< [1..0] ASGTRGAFR */ + __IOM uint32_t ASGTRGBFR : 2; /*!< [3..2] ASGTRGBFR */ + __IOM uint32_t ASGTRGCFR : 2; /*!< [5..4] ASGTRGCFR */ + __IOM uint32_t ASGTRGDFR : 2; /*!< [7..6] ASGTRGDFR */ + __IOM uint32_t ASCARBHL : 2; /*!< [9..8] ASCARBHL */ + __IOM uint32_t ASCAFBHL : 2; /*!< [11..10] ASCAFBHL */ + __IOM uint32_t ASCBRAHL : 2; /*!< [13..12] ASCBRAHL */ + __IOM uint32_t ASCBFAHL : 2; /*!< [15..14] ASCBFAHL */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ASELCA */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ASELCB */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ASELCC */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ASELCD */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ASELCE */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ASELCF */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ASELCG */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ASELCH */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAFR : 2; /*!< [1..0] BSGTRGAFR */ + __IOM uint32_t BSGTRGBFR : 2; /*!< [3..2] BSGTRGBFR */ + __IOM uint32_t BSGTRGCFR : 2; /*!< [5..4] BSGTRGCFR */ + __IOM uint32_t BSGTRGDFR : 2; /*!< [7..6] BSGTRGDFR */ + __IOM uint32_t BSCARBHL : 2; /*!< [9..8] BSCARBHL */ + __IOM uint32_t BSCAFBHL : 2; /*!< [11..10] BSCAFBHL */ + __IOM uint32_t BSCBRAHL : 2; /*!< [13..12] BSCBRAHL */ + __IOM uint32_t BSCBFAHL : 2; /*!< [15..14] BSCBFAHL */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] BSELCA */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] BSELCB */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] BSELCC */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] BSELCD */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] BSELCE */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] BSELCF */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] BSELCG */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] BSELCH */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 7; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select at Count Stop */ + uint32_t : 7; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 2; + __IOM uint32_t SWMD : 3; /*!< [31..29] Switch Mode Select */ + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCnA Pin Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] GTIOCnA Pin Output Duty Forced Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] Output after Release of GTIOCnA Pin Output 0%/100% + * Duty Cycle Settings */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCnB Pin Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] GTIOCnB Pin Output Duty Forced Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] Output after Release of GTIOCnB Pin Output 0%/100% + * Duty Cycle Settings */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] Output after Release of GTIOCnB Pin Output 0%/100% + * Duty Cycle Settings */ + uint32_t : 3; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCnA Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCnA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCnA Pin Output Retention at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCnA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCnA Pin Negate Value Setting */ + uint32_t : 2; + __IOM uint32_t NFAEN : 1; /*!< [13..13] GTIOCnA Pin Input Noise Filter Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] GTIOCnA Pin Input Noise Filter Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCnB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCnB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCnB Pin Output Retention at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCnB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCnB Pin Negate Value Setting */ + uint32_t : 2; + __IOM uint32_t NFBEN : 1; /*!< [29..29] GTIOCnB Pin Input Noise Filter Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] GTIOCnB Pin Input Noise Filter Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTINTA */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTINTB */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTINTC */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTINTD */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTINTE */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTINTF */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTINTPR */ + uint32_t : 8; + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] ADTRAUEN */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] ADTRADEN */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] ADTRBUEN */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] ADTRBDEN */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Select the group to detect disabling of output (dead-time + * error or simultaneous driving of outputs to the high or + * low level) to POEG and to request of disabling of output + * from POEG. */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] GRPDTE */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] (GTIOCnA pin and GTIOCnB output) */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] (GTIOCnA pin and GTIOCnB output) */ + uint32_t : 1; + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + uint32_t : 8; + __IM uint32_t ITCNT : 3; /*!< [10..8] GPTn_OVF/GPTn_UDF Interrupt Skipping Count Counter */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Register Compare Match (Up-Counting) A/D Converter + * Start Request Flag */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Register Compare Match (Down-Counting) A/D + * Converter Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Register Compare Match (Up-Counting) A/D Converter + * Start Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Register Compare Match (Down-Counting) A/D + * Converter Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Stop Request Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Simultaneous High Output Flag */ + __IM uint32_t OABLF : 1; /*!< [30..30] Simultaneous Low Output Flag */ + uint32_t : 1; + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] GTCCRA/GTCCRB Registers Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] GTPR Register Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] GTADTRA/GTADTRB Registers Buffer Operation Disable */ + __IOM uint32_t BD3 : 1; /*!< [3..3] GTDVU/GTDVD Registers Buffer Operation Disable */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRA Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRB Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Register Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Register Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Register Buffer Operation */ + __IOM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Registers Forcible Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Register Buffer Transfer Timing Select */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Register Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Register Buffer Transfer Timing Select */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Register Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] ITLA */ + __IOM uint32_t ITLB : 1; /*!< [1..1] ITLB */ + __IOM uint32_t ITLC : 1; /*!< [2..2] ITLC */ + __IOM uint32_t ITLD : 1; /*!< [3..3] ITLD */ + __IOM uint32_t ITLE : 1; /*!< [4..4] ITLE */ + __IOM uint32_t ITLF : 1; /*!< [5..5] ITLF */ + __IOM uint32_t IVTC : 2; /*!< [7..6] IVTC */ + __IOM uint32_t IVTT : 3; /*!< [10..8] IVTT */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] ADTAL */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] ADTBL */ + uint32_t : 17; + } GTITC_b; + }; + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register m + * (m = A,B,C,E,D,F) */ + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A + * (m = A, B) */ + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A (m = A, B) */ + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B + * (m = A, B) */ + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B (m = A, B) */ + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Register Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Register Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Register Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U + * (m = U, D) */ + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D + * (m = U, D) */ + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Value Buffer Register + * U (m = U, D) */ + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Value Buffer Register + * D (m = U, D) */ + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + + union + { + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ + + struct + { + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; + }; + + union + { + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ + + struct + { + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * Select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; + }; + + union + { + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ + + struct + { + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; + }; + + union + { + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ + + struct + { + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA A/D Converter Start Request Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB A/D Converter Start Request Extended Skipping + * Function Select */ + uint32_t : 25; + } GTEITLI2_b; + }; + + union + { + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ + + struct + { + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; + }; + __IM uint32_t RESERVED[6]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 25; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 20; + } GTSECR_b; + }; + + union + { + __IOM uint32_t GTSWSR; /*!< (@ 0x000000D8) General PWM Timer Switch Source Select Register */ + + struct + { + __IOM uint32_t WSGTRGA : 2; /*!< [1..0] GTETRGA Signal Edge Select to Switch Counter (GTETRGSA + * Signal for SAFTY) */ + __IOM uint32_t WSGTRGB : 2; /*!< [3..2] GTETRGB Signal Edge Select to Switch Counter (GTETRGSB + * Signal for SAFTY) */ + __IOM uint32_t WSGTRGC : 2; /*!< [5..4] GTETRGC Signal Edge Select to Switch Counter (GTETRGSC + * Signal for SAFTY) */ + __IOM uint32_t WSGTRGD : 2; /*!< [7..6] GTETRGD Signal Edge Select to Switch Counter (GTETRGSD + * Signal for SAFTY) */ + uint32_t : 8; + __IOM uint32_t WSELCA : 1; /*!< [16..16] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCB : 1; /*!< [17..17] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCC : 1; /*!< [18..18] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCD : 1; /*!< [19..19] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCE : 1; /*!< [20..20] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCF : 1; /*!< [21..21] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCG : 1; /*!< [22..22] Event Source Counter Switch Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] Event Source Counter Switch Enable */ + uint32_t : 8; + } GTSWSR_b; + }; + __IOM uint32_t GTSWOS; /*!< (@ 0x000000DC) General PWM Timer Switch Offset Setting Register */ +} R_GPT0_Type; /*!< Size = 224 (0xe0) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communication Interface 0 (R_SCI0) + */ + +typedef struct /*!< (@ 0x80001000) R_SCI0 Structure */ +{ + union + { + __IM uint32_t RDR; /*!< (@ 0x00000000) Receive Data Register */ + + struct + { + __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data */ + __IM uint32_t MPB : 1; /*!< [9..9] Multi-processor flag */ + __IM uint32_t DR : 1; /*!< [10..10] Receive data ready flag */ + __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag */ + __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag */ + uint32_t : 11; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag */ + uint32_t : 2; + __IM uint32_t PER : 1; /*!< [27..27] Parity error flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing error flag */ + uint32_t : 3; + } RDR_b; + }; + + union + { + __IOM uint32_t TDR; /*!< (@ 0x00000004) Transmit Data Register */ + + struct + { + __IOM uint32_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint32_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag */ + uint32_t : 22; + } TDR_b; + }; + + union + { + __IOM uint32_t CCR0; /*!< (@ 0x00000008) Common Control Register 0 */ + + struct + { + __IOM uint32_t RE : 1; /*!< [0..0] Receive Enable */ + uint32_t : 3; + __IOM uint32_t TE : 1; /*!< [4..4] Transmit Enable */ + uint32_t : 3; + __IOM uint32_t MPIE : 1; /*!< [8..8] Multi-Processor Interrupt Enable */ + __IOM uint32_t DCME : 1; /*!< [9..9] Data Compare Match Enable */ + __IOM uint32_t IDSEL : 1; /*!< [10..10] ID frame select */ + uint32_t : 5; + __IOM uint32_t RIE : 1; /*!< [16..16] Receive Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TIE : 1; /*!< [20..20] Transmit Interrupt Enable */ + __IOM uint32_t TEIE : 1; /*!< [21..21] Transmit End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SSE : 1; /*!< [24..24] SSn# Pin Function Enable */ + uint32_t : 7; + } CCR0_b; + }; + + union + { + __IOM uint32_t CCR1; /*!< (@ 0x0000000C) Common Control Register 1 */ + + struct + { + __IOM uint32_t CTSE : 1; /*!< [0..0] CTS Enable */ + __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable */ + uint32_t : 2; + __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select */ + __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O */ + uint32_t : 2; + __IOM uint32_t PE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t PM : 1; /*!< [9..9] Parity Mode */ + uint32_t : 2; + __IOM uint32_t TINV : 1; /*!< [12..12] TXD invert */ + __IOM uint32_t RINV : 1; /*!< [13..13] RXD invert */ + uint32_t : 2; + __IOM uint32_t SPLP : 1; /*!< [16..16] Loopback Control */ + uint32_t : 3; + __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select */ + uint32_t : 3; + __IOM uint32_t NFCS : 3; /*!< [26..24] Noise Filter Clock Select */ + uint32_t : 1; + __IOM uint32_t NFEN : 1; /*!< [28..28] Digital Noise Filter Function Enable */ + uint32_t : 3; + } CCR1_b; + }; + + union + { + __IOM uint32_t CCR2; /*!< (@ 0x00000010) Common Control Register 2 */ + + struct + { + __IOM uint32_t BCP : 3; /*!< [2..0] Base Clock Pulse */ + uint32_t : 1; + __IOM uint32_t BGDM : 1; /*!< [4..4] Baud Rate Generator Double-Speed Mode Select */ + __IOM uint32_t ABCS : 1; /*!< [5..5] Asynchronous Mode Base Clock Select */ + __IOM uint32_t ABCSE : 1; /*!< [6..6] Asynchronous Mode Extended Base Clock Select */ + uint32_t : 1; + __IOM uint32_t BRR : 8; /*!< [15..8] Bit rate setting */ + __IOM uint32_t BRME : 1; /*!< [16..16] BRME */ + uint32_t : 3; + __IOM uint32_t CKS : 2; /*!< [21..20] Clock Select */ + uint32_t : 2; + __IOM uint32_t MDDR : 8; /*!< [31..24] Modulation Duty setting */ + } CCR2_b; + }; + + union + { + __IOM uint32_t CCR3; /*!< (@ 0x00000014) Common Control Register 3 */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] Clock Phase Select */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock Polarity Select */ + uint32_t : 5; + __IOM uint32_t BPEN : 1; /*!< [7..7] Synchronizer bypass enable */ + __IOM uint32_t CHR : 2; /*!< [9..8] Character Length */ + uint32_t : 2; + __IOM uint32_t LSBF : 1; /*!< [12..12] LSB First select */ + __IOM uint32_t SINV : 1; /*!< [13..13] Transmitted/Received Data Invert */ + __IOM uint32_t STP : 1; /*!< [14..14] Stop Bit Length */ + __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select */ + __IOM uint32_t MOD : 3; /*!< [18..16] Communication mode select */ + __IOM uint32_t MP : 1; /*!< [19..19] Multi-Processor Mode */ + __IOM uint32_t FM : 1; /*!< [20..20] FIFO Mode select */ + __IOM uint32_t DEN : 1; /*!< [21..21] Driver enable */ + uint32_t : 2; + __IOM uint32_t CKE : 2; /*!< [25..24] Clock enable */ + uint32_t : 2; + __IOM uint32_t GM : 1; /*!< [28..28] GSM Mode */ + __IOM uint32_t BLK : 1; /*!< [29..29] Block Transfer Mode */ + uint32_t : 2; + } CCR3_b; + }; + + union + { + __IOM uint32_t CCR4; /*!< (@ 0x00000018) Common Control Register 4 */ + + struct + { + __IOM uint32_t CMPD : 9; /*!< [8..0] Compare Match Data */ + uint32_t : 7; + __IOM uint32_t ASEN : 1; /*!< [16..16] Adjust receive sampling timing enable */ + __IOM uint32_t ATEN : 1; /*!< [17..17] Adjust transmit timing enable */ + uint32_t : 6; + __IOM uint32_t AST : 3; /*!< [26..24] Adjustment value for receive Sampling Timing */ + __IOM uint32_t AJD : 1; /*!< [27..27] Adjustment Direction for receive sampling timing */ + __IOM uint32_t ATT : 3; /*!< [30..28] Adjustment value for Transmit timing */ + __IOM uint32_t AET : 1; /*!< [31..31] Adjustment edge for transmit timing */ + } CCR4_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000020) Simple I2C Control Register */ + + struct + { + __IOM uint32_t IICDL : 5; /*!< [4..0] SDA Delay Output Select */ + uint32_t : 3; + __IOM uint32_t IICINTM : 1; /*!< [8..8] IICINTM */ + __IOM uint32_t IICCSC : 1; /*!< [9..9] IICCSC */ + uint32_t : 3; + __IOM uint32_t IICACKT : 1; /*!< [13..13] IICACKT */ + uint32_t : 2; + __IOM uint32_t IICSTAREQ : 1; /*!< [16..16] IICSTAREQ */ + __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] IICRSTAREQ */ + __IOM uint32_t IICSTPREQ : 1; /*!< [18..18] IICSTPREQ */ + uint32_t : 1; + __IOM uint32_t IICSDAS : 2; /*!< [21..20] IICSDAS */ + __IOM uint32_t IICSCLS : 2; /*!< [23..22] IICSCLS */ + uint32_t : 8; + } ICR_b; + }; + + union + { + __IOM uint32_t FCR; /*!< (@ 0x00000024) FIFO Control Register */ + + struct + { + __IOM uint32_t DRES : 1; /*!< [0..0] Receive data ready error select */ + uint32_t : 7; + __IOM uint32_t TTRG : 5; /*!< [12..8] Transmit FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t TFRST : 1; /*!< [15..15] Transmit FIFO Data Register Reset */ + __IOM uint32_t RTRG : 5; /*!< [20..16] Receive FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t RFRST : 1; /*!< [23..23] Receive FIFO Data Register Reset */ + __IOM uint32_t RSTRG : 5; /*!< [28..24] RTS# Output Active Trigger Number Select */ + uint32_t : 3; + } FCR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t DCR; /*!< (@ 0x00000030) Driver Control Register */ + + struct + { + __IOM uint32_t DEPOL : 1; /*!< [0..0] Driver effective polarity select */ + uint32_t : 7; + __IOM uint32_t DEAST : 5; /*!< [12..8] Driver Assertion Time */ + uint32_t : 3; + __IOM uint32_t DENGT : 5; /*!< [20..16] Driver negate time */ + uint32_t : 11; + } DCR_b; + }; + __IM uint32_t RESERVED2[5]; + + union + { + __IM uint32_t CSR; /*!< (@ 0x00000048) Common Status Register */ + + struct + { + uint32_t : 4; + __IM uint32_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + uint32_t : 10; + __IM uint32_t RXDMON : 1; /*!< [15..15] Serial input data monitor */ + __IM uint32_t DCMF : 1; /*!< [16..16] Data Compare Match Flag */ + __IM uint32_t DPER : 1; /*!< [17..17] Data Compare Match Parity Error Flag */ + __IM uint32_t DFER : 1; /*!< [18..18] Data Compare Match Framing Error Flag */ + uint32_t : 5; + __IM uint32_t ORER : 1; /*!< [24..24] ORER */ + uint32_t : 1; + __IM uint32_t MFF : 1; /*!< [26..26] Mode Fault Error Flag */ + __IM uint32_t PER : 1; /*!< [27..27] PER */ + __IM uint32_t FER : 1; /*!< [28..28] FER */ + __IM uint32_t TDRE : 1; /*!< [29..29] Transmit Data Empty Flag */ + __IM uint32_t TEND : 1; /*!< [30..30] TEND */ + __IM uint32_t RDRF : 1; /*!< [31..31] RDRF */ + } CSR_b; + }; + + union + { + __IM uint32_t ISR; /*!< (@ 0x0000004C) Simple I2C Status Register */ + + struct + { + __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint32_t : 2; + __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag */ + uint32_t : 28; + } ISR_b; + }; + + union + { + __IM uint32_t FRSR; /*!< (@ 0x00000050) FIFO Receive Status Register */ + + struct + { + __IM uint32_t DR : 1; /*!< [0..0] DR */ + uint32_t : 7; + __IM uint32_t R : 6; /*!< [13..8] Receive FIFO Data Count */ + uint32_t : 2; + __IM uint32_t PNUM : 6; /*!< [21..16] Parity Error Count */ + uint32_t : 2; + __IM uint32_t FNUM : 6; /*!< [29..24] Framing Error Count */ + uint32_t : 2; + } FRSR_b; + }; + + union + { + __IM uint32_t FTSR; /*!< (@ 0x00000054) FIFO Transmit Status Register */ + + struct + { + __IM uint32_t T : 6; /*!< [5..0] Transmit FIFO Data Count */ + uint32_t : 26; + } FTSR_b; + }; + __IM uint32_t RESERVED3[4]; + + union + { + __OM uint32_t CFCLR; /*!< (@ 0x00000068) Common Flag Clear Register */ + + struct + { + uint32_t : 4; + __OM uint32_t ERSC : 1; /*!< [4..4] ERSC */ + uint32_t : 11; + __OM uint32_t DCMFC : 1; /*!< [16..16] DCMFC */ + __OM uint32_t DPERC : 1; /*!< [17..17] DPERC */ + __OM uint32_t DFERC : 1; /*!< [18..18] DFERC */ + uint32_t : 5; + __OM uint32_t ORERC : 1; /*!< [24..24] ORERC */ + uint32_t : 1; + __OM uint32_t MFFC : 1; /*!< [26..26] MFFC */ + __OM uint32_t PERC : 1; /*!< [27..27] PERC */ + __OM uint32_t FERC : 1; /*!< [28..28] FERC */ + __OM uint32_t TDREC : 1; /*!< [29..29] TDREC */ + uint32_t : 1; + __OM uint32_t RDRFC : 1; /*!< [31..31] RDRFC */ + } CFCLR_b; + }; + + union + { + __OM uint32_t ICFCLR; /*!< (@ 0x0000006C) Simple I2C Flag Clear Register */ + + struct + { + uint32_t : 3; + __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIFC */ + uint32_t : 28; + } ICFCLR_b; + }; + + union + { + __OM uint32_t FFCLR; /*!< (@ 0x00000070) FIFO Flag Clear Register */ + + struct + { + __OM uint32_t DRC : 1; /*!< [0..0] DRC */ + uint32_t : 31; + } FFCLR_b; + }; +} R_SCI0_Type; /*!< Size = 116 (0x74) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface 0 (R_SPI0) + */ + +typedef struct /*!< (@ 0x80003000) R_SPI0 Structure */ +{ + union + { + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000000) SPI Data Register */ + + struct + { + __IOM uint32_t SPD : 32; /*!< [31..0] The SPI data register (SPDR) is used to store SPI's + * transmit data and receive data. Transmit buffers and receive + * buffers independently function. */ + } SPDR_b; + }; + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000000) SPI Data Register */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000000) SPI Data Register */ + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x00000004) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x00000005) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Bits */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x00000006) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Bits */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t MRCKD; /*!< (@ 0x00000007) SPI ClocK Digital control Register for Master + * Receive */ + + struct + { + __IOM uint8_t ARST : 3; /*!< [2..0] Receive Sampling Timing Adjustment Bits */ + uint8_t : 5; + } MRCKD_b; + }; + + union + { + __IOM uint32_t SPCR; /*!< (@ 0x00000008) SPI Control Register */ + + struct + { + __IOM uint32_t SPE : 1; /*!< [0..0] SPI Function Enable */ + uint32_t : 6; + __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] SPI Master Receive Clock Select */ + __IOM uint32_t SPPE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t SPOE : 1; /*!< [9..9] Parity Mode */ + uint32_t : 1; + __IOM uint32_t PTE : 1; /*!< [11..11] Parity Self-Diagnosis Enable */ + __IOM uint32_t SCKASE : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable */ + __IOM uint32_t BFDS : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select */ + __IOM uint32_t MODFEN : 1; /*!< [14..14] Mode Fault Error Detection Enable */ + uint32_t : 1; + __IOM uint32_t SPEIE : 1; /*!< [16..16] SPI Error Interrupt Enable */ + __IOM uint32_t SPRIE : 1; /*!< [17..17] SPI Receive Buffer Full Interrupt Enable */ + __IOM uint32_t SPIIE : 1; /*!< [18..18] SPI Idle Interrupt Enable */ + __IOM uint32_t SPDRES : 1; /*!< [19..19] SPI Receive Data Ready Error Select */ + __IOM uint32_t SPTIE : 1; /*!< [20..20] SPI Transmit Buffer Empty Interrupt Enable */ + __IOM uint32_t CENDIE : 1; /*!< [21..21] SPI Communication End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SPMS : 1; /*!< [24..24] SPI Function Enable */ + __IOM uint32_t SPFRF : 1; /*!< [25..25] SPI Frame Format Select */ + uint32_t : 2; + __IOM uint32_t TXMD : 2; /*!< [29..28] Communication Mode Select */ + __IOM uint32_t MSTR : 1; /*!< [30..30] SPI Master/Slave Mode Select */ + __IOM uint32_t BPEN : 1; /*!< [31..31] Synchronization Circuit Bypass Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SPCRRM; /*!< (@ 0x0000000C) SPI Control Register for Master Receive only */ + + struct + { + __IOM uint8_t RMFM : 5; /*!< [4..0] Frame processing count setting in Master Receive only */ + uint8_t : 1; + __OM uint8_t RMEDTG : 1; /*!< [6..6] Reading value is always 0. */ + __OM uint8_t RMSTTG : 1; /*!< [7..7] Reading value is always 0. */ + } SPCRRM_b; + }; + + union + { + __IOM uint8_t SPDRCR; /*!< (@ 0x0000000D) SPI Control Register for Received Data Ready + * Detection */ + + struct + { + __IOM uint8_t SPDRC : 8; /*!< [7..0] SPDRC */ + } SPDRCR_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x0000000E) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + __IOM uint8_t SPOM : 1; /*!< [2..2] SPI Output Pin Mode */ + uint8_t : 1; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPSCKDL : 3; /*!< [2..0] SPI Master Receive Clock Analog Delay */ + uint8_t : 5; + } SPCR2_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000010) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + uint8_t : 4; + } SSLP_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x00000011) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] The SPBR register is used to set the bit rate in master + * mode. If SPBR is modified while SPCR.MSTR = 1 and SPCR.SPE + * = 1, subsequent operation is not guaranteed. */ + } SPBR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000013) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] SPI Sequence Length Specification */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IOM uint32_t SPCMD[8]; /*!< (@ 0x00000014) SPI Command Register [0..7] (m = 0 to 7) */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] SPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 2; /*!< [25..24] SSL Signal Assertion */ + uint32_t : 6; + } SPCMD_b[8]; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint16_t SPDCR; /*!< (@ 0x00000040) SPI Data Control Register */ + + struct + { + __IOM uint16_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint16_t SLSEL : 2; /*!< [2..1] SSL Pin Output Select */ + __IOM uint16_t SPRDTD : 1; /*!< [3..3] SPI Receive Data or Transmit Data Selection */ + __IOM uint16_t SINV : 1; /*!< [4..4] Serial data invert */ + uint16_t : 3; + __IOM uint16_t SPFC : 2; /*!< [9..8] Frame Count */ + uint16_t : 6; + } SPDCR_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPDCR2; /*!< (@ 0x00000044) SPI Data Control Register 2 */ + + struct + { + __IOM uint16_t RTRG : 2; /*!< [1..0] Receive FIFO threshold setting */ + uint16_t : 6; + __IOM uint16_t TTRG : 2; /*!< [9..8] Transmission FIFO threshold setting */ + uint16_t : 6; + } SPDCR2_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[2]; + __IM uint8_t RESERVED5; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000051) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] SPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] SPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IM uint16_t SPSR; /*!< (@ 0x00000052) SPI Status Register */ + + struct + { + uint16_t : 7; + __IM uint16_t SPDRF : 1; /*!< [7..7] SPI Receive Data Ready Flag */ + __IM uint16_t OVRF : 1; /*!< [8..8] Overrun Error Flag */ + __IM uint16_t IDLNF : 1; /*!< [9..9] SPI Idle Flag */ + __IM uint16_t MODF : 1; /*!< [10..10] Mode Fault Error Flag */ + __IM uint16_t PERF : 1; /*!< [11..11] Parity Error Flag */ + __IM uint16_t UDRF : 1; /*!< [12..12] Underrun Error Flag */ + __IM uint16_t SPTEF : 1; /*!< [13..13] SPI Transmit Buffer Empty Flag */ + __IM uint16_t CENDF : 1; /*!< [14..14] Communication End Flag */ + __IM uint16_t SPRF : 1; /*!< [15..15] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IM uint8_t SPTFSR; /*!< (@ 0x00000058) SPI Transfer FIFO Status Register */ + + struct + { + __IM uint8_t TFDN : 3; /*!< [2..0] Transmit FIFO data empty stage number */ + uint8_t : 5; + } SPTFSR_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IM uint8_t SPRFSR; /*!< (@ 0x0000005C) SPI Receive FIFO Status Register */ + + struct + { + __IM uint8_t RFDN : 3; /*!< [2..0] Receive FIFO data store stage number */ + uint8_t : 5; + } SPRFSR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + + union + { + __IM uint32_t SPPSR; /*!< (@ 0x00000060) SPI Poling Register */ + + struct + { + __IM uint32_t SPEPS : 1; /*!< [0..0] SPI Polling Status */ + uint32_t : 31; + } SPPSR_b; + }; + __IM uint32_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t SPSRC; /*!< (@ 0x0000006A) SPI Status Clear Register */ + + struct + { + uint16_t : 7; + __OM uint16_t SPDRFC : 1; /*!< [7..7] SPI Receive Data Ready Flag Clear */ + __OM uint16_t OVRFC : 1; /*!< [8..8] Overrun Error Flag Clear */ + uint16_t : 1; + __OM uint16_t MODFC : 1; /*!< [10..10] Mode Fault Error Flag Clear */ + __OM uint16_t PERFC : 1; /*!< [11..11] Parity Error Flag Clear */ + __OM uint16_t UDRFC : 1; /*!< [12..12] Underrun Error Flag Clear */ + __OM uint16_t SPTEFC : 1; /*!< [13..13] SPI Transmit Buffer Empty Flag Clear */ + __OM uint16_t CENDFC : 1; /*!< [14..14] Communication End Flag Clear */ + __OM uint16_t SPRFC : 1; /*!< [15..15] SPI Receive Buffer Full Flag Clear */ + } SPSRC_b; + }; + + union + { + __OM uint8_t SPFCR; /*!< (@ 0x0000006C) SPI FIFO Clear Register */ + + struct + { + __OM uint8_t SPFRST : 1; /*!< [0..0] SPI FIFO clear */ + uint8_t : 7; + } SPFCR_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; +} R_SPI0_Type; /*!< Size = 112 (0x70) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CRC Unit 0 (R_CRC0) + */ + +typedef struct /*!< (@ 0x80004000) R_CRC0 Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register 0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register */ + }; + + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register */ + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register */ + }; +} R_CRC0_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CAN-FD (R_CANFD) + */ + +typedef struct /*!< (@ 0x80020000) R_CANFD Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) CANFD Channel [0..1] Registers */ + __IM uint32_t RESERVED[24]; + + union + { + __IM uint32_t CFDGIPV; /*!< (@ 0x00000080) Global IP Version Register */ + + struct + { + __IM uint32_t IPV : 8; /*!< [7..0] IP Version */ + __IM uint32_t IPT : 2; /*!< [9..8] IP Type */ + uint32_t : 6; + __IM uint32_t PSI : 14; /*!< [29..16] Parameter Status Information */ + uint32_t : 2; + } CFDGIPV_b; + }; + + union + { + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ + + struct + { + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD Message Payload Overflow Configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; + + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ + + struct + { + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC Check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message Lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD Message Payload Overflow Flag Interrupt Enable */ + __IOM uint32_t QOWEIE : 1; /*!< [12..12] TXQ Message Overwrite Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message Lost Error Interrupt Enable */ + __IOM uint32_t MOWEIE : 1; /*!< [15..15] Message Lost Error Interrupt Enable */ + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + uint32_t : 15; + } CFDGCTR_b; + }; + + union + { + __IM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ + + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialization */ + uint32_t : 28; + } CFDGSTS_b; + }; + + union + { + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */ + + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD Message Payload Overflow Flag */ + __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message Overwrite Error Status */ + uint32_t : 1; + __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */ + __IM uint32_t MOWES : 1; /*!< [7..7] Message Overwrite Error Status */ + uint32_t : 8; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */ + uint32_t : 14; + } CFDGERFL_b; + }; + + union + { + __IM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */ + + struct + { + __IM uint32_t TS : 16; /*!< [15..0] Timestamp value */ + uint32_t : 16; + } CFDGTSC_b; + }; + + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */ + + struct + { + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; + + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register + * 0 */ + + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */ + + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; + }; + + union + { + __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */ + + struct + { + __IOM uint32_t RMNS : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration/Control Register [0..7] */ + + struct + { + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size Configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full Interrupt Enable */ + uint32_t : 15; + } CFDRFCC_b[8]; + }; + + union + { + __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Register [0..7] */ + + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */ + uint32_t : 15; + } CFDRFSTS_b[8]; + }; + + union + { + __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Register [0..7] */ + + struct + { + __IOM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[8]; + }; + + union + { + __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration/Control Register [0..5] */ + + struct + { + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data Size Configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[6]; + }; + __IM uint32_t RESERVED3[18]; + + union + { + __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration/Control Enhancement + * Register [0..5] */ + + struct + { + __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full Interrupt Enable */ + __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */ + __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO Message Overwrite Mode */ + uint32_t : 7; + __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */ + uint32_t : 15; + } CFDCFCCE_b[6]; + }; + __IM uint32_t RESERVED4[18]; + + union + { + __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Register [0..5] */ + + struct + { + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */ + __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */ + __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */ + uint32_t : 5; + __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO Message Overwrite */ + uint32_t : 7; + } CFDCFSTS_b[6]; + }; + __IM uint32_t RESERVED5[18]; + + union + { + __OM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Register [0..5] */ + + struct + { + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[6]; + }; + __IM uint32_t RESERVED6[18]; + + union + { + __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */ + + struct + { + __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIFO Empty Status */ + __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIFO Empty Status */ + uint32_t : 18; + } CFDFESTS_b; + }; + + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */ + + struct + { + __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIFO Full Status */ + __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIFO Full Status */ + uint32_t : 18; + } CFDFFSTS_b; + }; + + union + { + __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */ + + struct + { + __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Message Lost Status */ + __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Message Lost Status */ + uint32_t : 18; + } CFDFMSTS_b; + }; + + union + { + __IM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */ + + struct + { + __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 8; + __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */ + uint32_t : 8; + } CFDRFISTS_b; + }; + + union + { + __IM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */ + + struct + { + __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFRISTS_b; + }; + + union + { + __IM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */ + + struct + { + __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFTISTS_b; + }; + + union + { + __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status + * Register */ + + struct + { + __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO One Frame RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFRISTS_b; + }; + + union + { + __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status + * Register */ + + struct + { + __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO One Frame TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFTISTS_b; + }; + + union + { + __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Overwrite Status Register */ + + struct + { + __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO Massage Overwrite Status */ + uint32_t : 26; + } CFDCFMOWSTS_b; + }; + + union + { + __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */ + + struct + { + __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC Level Full Status */ + __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC Level Full Status */ + uint32_t : 18; + } CFDFFFSTS_b; + }; + __IM uint32_t RESERVED7[2]; + + union + { + __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Register [0..127] */ + + struct + { + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission Abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[128]; + }; + __IM uint32_t RESERVED8[288]; + + union + { + __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Register [0..127] */ + + struct + { + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission Abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[128]; + }; + __IM uint32_t RESERVED9[288]; + + union + { + __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status + * Register [0..3] */ + + struct + { + __IM uint32_t TMTRSTS : 16; /*!< [15..0] TX Message Buffer Transmission Request Status */ + uint32_t : 16; + } CFDTMTRSTS_b[4]; + }; + __IM uint32_t RESERVED10[36]; + + union + { + __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request + * Status Register [0..3] */ + + struct + { + __IM uint32_t TMTARSTS : 16; /*!< [15..0] TX Message Buffer Transmission Abort Request Status */ + uint32_t : 16; + } CFDTMTARSTS_b[4]; + }; + __IM uint32_t RESERVED11[36]; + + union + { + __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status + * Register [0..3] */ + + struct + { + __IM uint32_t TMTCSTS : 16; /*!< [15..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 16; + } CFDTMTCSTS_b[4]; + }; + __IM uint32_t RESERVED12[36]; + + union + { + __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register + * [0..3] */ + + struct + { + __IM uint32_t TMTASTS : 16; /*!< [15..0] TX Message Buffer Transmission Abort Status */ + uint32_t : 16; + } CFDTMTASTS_b[4]; + }; + __IM uint32_t RESERVED13[36]; + + union + { + __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Transmission Interrupt Enable + * Register [0..3] */ + + struct + { + __IOM uint32_t TMIE : 16; /*!< [15..0] TX Message Buffer Interrupt Enable */ + uint32_t : 16; + } CFDTMIEC_b[4]; + }; + __IM uint32_t RESERVED14[40]; + + union + { + __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration/Control Register 0[0..1] */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC0_b[2]; + }; + __IM uint32_t RESERVED15[6]; + + union + { + __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Register 0[0..1] */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS0_b[2]; + }; + __IM uint32_t RESERVED16[6]; + + union + { + __OM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Register 0[0..1] */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[2]; + }; + __IM uint32_t RESERVED17[6]; + + union + { + __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration/Control Register 1[0..1] */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC1_b[2]; + }; + __IM uint32_t RESERVED18[6]; + + union + { + __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Register 1[0..1] */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS1_b[2]; + }; + __IM uint32_t RESERVED19[6]; + + union + { + __OM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Register 1[0..1] */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR1_b[2]; + }; + __IM uint32_t RESERVED20[6]; + + union + { + __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration/Control Register 2[0..1] */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC2_b[2]; + }; + __IM uint32_t RESERVED21[6]; + + union + { + __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Register 2[0..1] */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS2_b[2]; + }; + __IM uint32_t RESERVED22[6]; + + union + { + __OM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Register 2[0..1] */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR2_b[2]; + }; + __IM uint32_t RESERVED23[6]; + + union + { + __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration/Control Register 3[0..1] */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 1; + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 5; + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC3_b[2]; + }; + __IM uint32_t RESERVED24[6]; + + union + { + __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Register 3[0..1] */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 4; + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + uint32_t : 1; + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS3_b[2]; + }; + __IM uint32_t RESERVED25[6]; + + union + { + __OM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Register 3[0..1] */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR3_b[2]; + }; + __IM uint32_t RESERVED26[6]; + + union + { + __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */ + + struct + { + __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ Empty Status */ + uint32_t : 24; + } CFDTXQESTS_b; + }; + + union + { + __IM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status Flag for Channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status Flag for Channel 1 */ + uint32_t : 25; + } CFDTXQFISTS_b; + }; + + union + { + __IM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */ + + struct + { + __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ Message Lost Status Flag for Channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ Message Lost Status Flag for Channel 1 */ + uint32_t : 25; + } CFDTXQMSTS_b; + }; + __IM uint32_t RESERVED27; + + union + { + __IM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for Channel 0 */ + __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for Channel 1 */ + uint32_t : 24; + } CFDTXQISTS_b; + }; + + union + { + __IM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for Channel 0 */ + __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for Channel 1 */ + uint32_t : 24; + } CFDTXQOFTISTS_b; + }; + + union + { + __IM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag for Channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag for Channel 1 */ + uint32_t : 25; + } CFDTXQOFRISTS_b; + }; + + union + { + __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */ + + struct + { + __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for Channel 0 */ + __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for Channel 1 */ + uint32_t : 24; + } CFDTXQFSTS_b; + }; + __IM uint32_t RESERVED28[24]; + + union + { + __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration/Control Register + * [0..1] */ + + struct + { + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated Gateway Enable */ + uint32_t : 20; + } CFDTHLCC_b[2]; + }; + __IM uint32_t RESERVED29[6]; + + union + { + __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register [0..1] */ + + struct + { + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[2]; + }; + __IM uint32_t RESERVED30[6]; + + union + { + __OM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Register [0..1] */ + + struct + { + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[2]; + }; + __IM uint32_t RESERVED31[46]; + + union + { + __IM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */ + + struct + { + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel + * 0 */ + __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel + * 0 */ + uint32_t : 1; + __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */ + __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */ + __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */ + __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */ + __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */ + __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel + * 1 */ + __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel + * 1 */ + uint32_t : 17; + } CFDGTINTSTS0_b; + }; + __IM uint32_t RESERVED32; + + union + { + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */ + + struct + { + __IOM uint32_t C0ICBCE : 1; /*!< [0..0] Channel 0 Internal CAN Bus Communication Test Mode Enable */ + __IOM uint32_t C1ICBCE : 1; /*!< [1..1] Channel 1 Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 14; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; + }; + + union + { + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */ + + struct + { + __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 1; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; + }; + __IM uint32_t RESERVED33; + + union + { + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration Register */ + + struct + { + __IOM uint32_t RPED : 1; /*!< [0..0] RES Bit Protocol Exception Disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp Capture Configuration */ + uint32_t : 22; + } CFDGFDCFG_b; + }; + __IM uint32_t RESERVED34; + + union + { + __OM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */ + + struct + { + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; + }; + __IM uint32_t RESERVED35[4]; + + union + { + __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */ + + struct + { + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RX FIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RX FIFO 1 */ + __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RX FIFO 2 */ + __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RX FIFO 3 */ + __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RX FIFO 4 */ + __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RX FIFO 5 */ + __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RX FIFO 6 */ + __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RX FIFO 7 */ + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of Channel 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of Channel 1 */ + uint32_t : 22; + } CFDCDTCT_b; + }; + + union + { + __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */ + + struct + { + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */ + __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */ + __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */ + __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */ + __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */ + __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */ + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of Channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of Channel + * 1 */ + uint32_t : 22; + } CFDCDTSTS_b; + }; + __IM uint32_t RESERVED36[2]; + + union + { + __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */ + + struct + { + __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of Channel 0 */ + __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of Channel 1 */ + uint32_t : 6; + __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of Channel 0 */ + __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of Channel 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of Channel + * 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of Channel + * 1 */ + uint32_t : 14; + } CFDCDTTCT_b; + }; + + union + { + __IM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */ + + struct + { + __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of Channel 0 */ + __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of Channel 1 */ + uint32_t : 6; + __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of Channel 0 */ + __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of Channel 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status for Common FIFO 2 of Channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status for Common FIFO 2 of Channel + * 1 */ + uint32_t : 14; + } CFDCDTTSTS_b; + }; + __IM uint32_t RESERVED37[2]; + + union + { + __IM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register [0..1] */ + + struct + { + __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n (n = 0, 1) */ + uint32_t : 1; + __IM uint32_t BQFIF : 2; /*!< [5..4] Borrowed TXQ Full Interrupt Flag Channel n (n = 0, 1) */ + uint32_t : 2; + __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n (n = 0, 1) */ + uint32_t : 1; + __IM uint32_t BQOFRIF : 2; /*!< [13..12] Borrowed TXQ One Frame RX Interrupt Flag Channel n + * (n = 0, 1) */ + uint32_t : 2; + __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n (n = 0, 1) */ + uint32_t : 5; + __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC Level Full Interrupt Flag Channel n + * (n = 0, 1) */ + uint32_t : 1; + __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n (n + * = 0, 1) */ + uint32_t : 1; + } CFDGRINTSTS_b[2]; + }; + __IM uint32_t RESERVED38[10]; + + union + { + __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global Reset Control Register */ + + struct + { + __IOM uint32_t SRST : 1; /*!< [0..0] Software Reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key Code */ + uint32_t : 16; + } CFDGRSTC_b; + }; + + union + { + __IOM uint32_t CFDGFCMC; /*!< (@ 0x00001384) Global Flexible CAN Mode Configuration Register */ + + struct + { + __IOM uint32_t FLXC0 : 1; /*!< [0..0] Flexible CAN Mode between Channel 0 and Channel 1 */ + uint32_t : 31; + } CFDGFCMC_b; + }; + __IM uint32_t RESERVED39; + + union + { + __IOM uint32_t CFDGFTBAC; /*!< (@ 0x0000138C) Global Flexible Transmission Buffer Assignment + * Configuration Register */ + + struct + { + __IOM uint32_t FLXMB0 : 4; /*!< [3..0] Flexible Transmission Buffer Assignment between Channel + * 0 and Channel 1 */ + uint32_t : 28; + } CFDGFTBAC_b; + }; + __IM uint32_t RESERVED40[28]; + __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ + __IM uint32_t RESERVED41[240]; + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED42[448]; + __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED43[3072]; + __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */ + __IM uint32_t RESERVED44[1600]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ + __IM uint32_t RESERVED45[252]; + + union + { + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Register [0..63] */ + + struct + { + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; + }; + __IM uint32_t RESERVED46[7872]; + __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Registers */ +} R_CANFD_Type; /*!< Size = 81920 (0x14000) */ + +/* =========================================================================================================================== */ +/* ================ R_CMT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Compare Match Timer Control (R_CMT) + */ + +typedef struct /*!< (@ 0x80040000) R_CMT Structure */ +{ + __IOM R_CMT_UNT_Type UNT[3]; /*!< (@ 0x00000000) 3 Timer Start Register Units */ +} R_CMT_Type; /*!< Size = 3072 (0xc00) */ + +/* =========================================================================================================================== */ +/* ================ R_CMTW0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Compare Match Timer W (R_CMTW0) + */ + +typedef struct /*!< (@ 0x80041000) R_CMTW0 Structure */ +{ + union + { + __IOM uint16_t CMWSTR; /*!< (@ 0x00000000) Timer Start Register */ + + struct + { + __IOM uint16_t STR : 1; /*!< [0..0] Counter Start */ + uint16_t : 15; + } CMWSTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CMWCR; /*!< (@ 0x00000004) Timer Control Register */ + + struct + { + __IOM uint16_t CKS : 2; /*!< [1..0] Clock Select */ + uint16_t : 1; + __IOM uint16_t CMWIE : 1; /*!< [3..3] Compare Match Interrupt Enable */ + __IOM uint16_t IC0IE : 1; /*!< [4..4] Input Capture 0 Interrupt Enable */ + __IOM uint16_t IC1IE : 1; /*!< [5..5] Input Capture 1 Interrupt Enable */ + __IOM uint16_t OC0IE : 1; /*!< [6..6] Output Compare 0 Interrupt Enable */ + __IOM uint16_t OC1IE : 1; /*!< [7..7] Output Compare 1 Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t CMS : 1; /*!< [9..9] Timer Counter Size */ + uint16_t : 3; + __IOM uint16_t CCLR : 3; /*!< [15..13] Counter Clear */ + } CMWCR_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t CMWIOR; /*!< (@ 0x00000008) Timer I/O Control Register */ + + struct + { + __IOM uint16_t IC0 : 2; /*!< [1..0] Input Capture Control 0 */ + __IOM uint16_t IC1 : 2; /*!< [3..2] Input Capture Control 1 */ + __IOM uint16_t IC0E : 1; /*!< [4..4] Input Capture Enable 0 */ + __IOM uint16_t IC1E : 1; /*!< [5..5] Input Capture Enable 1 */ + uint16_t : 2; + __IOM uint16_t OC0 : 2; /*!< [9..8] Output Compare Control 0 */ + __IOM uint16_t OC1 : 2; /*!< [11..10] Output Compare Control 1 */ + __IOM uint16_t OC0E : 1; /*!< [12..12] Compare Match Enable 0 */ + __IOM uint16_t OC1E : 1; /*!< [13..13] Compare Match Enable 1 */ + uint16_t : 1; + __IOM uint16_t CMWE : 1; /*!< [15..15] Compare Match Enable */ + } CMWIOR_b; + }; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3; + __IOM uint32_t CMWCNT; /*!< (@ 0x00000010) Timer Counter */ + __IOM uint32_t CMWCOR; /*!< (@ 0x00000014) Compare Match Constant Register */ + __IM uint32_t CMWICR0; /*!< (@ 0x00000018) Input Capture Registers */ + __IM uint32_t CMWICR1; /*!< (@ 0x0000001C) Input Capture Registers */ + __IOM uint32_t CMWOCR0; /*!< (@ 0x00000020) Output Compare Registers */ + __IOM uint32_t CMWOCR1; /*!< (@ 0x00000024) Output Compare Registers */ +} R_CMTW0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer 0 (R_WDT0) + */ + +typedef struct /*!< (@ 0x80042000) R_WDT0 Structure */ +{ + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_WDT0_Type; /*!< Size = 10 (0xa) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface 0 (R_IIC0) + */ + +typedef struct /*!< (@ 0x80043000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __OM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] IIC-Bus Interface Internal Reset */ + __IOM uint8_t ICE : 1; /*!< [7..7] IIC-Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance Request */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance Request */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance Request */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock Select */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Select */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Select */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAIT */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/IIC-Bus Select */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + uint8_t : 1; + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period */ + uint8_t : 3; + } ICBRH_b; + }; + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ +} R_IIC0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x80044000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 1; + __IOM uint8_t DOPCIE : 1; /*!< [4..4] Data Operation Circuit Interrupt Enable */ + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __OM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Flag Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_TSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor Unit (R_TSU) + */ + +typedef struct /*!< (@ 0x80046000) R_TSU Structure */ +{ + union + { + __IOM uint32_t TSUSM; /*!< (@ 0x00000000) Sensor Mode Register */ + + struct + { + __IOM uint32_t TSEN : 1; /*!< [0..0] Temperature Sensor Enable */ + __IOM uint32_t ADCEN : 1; /*!< [1..1] ADC Enable */ + uint32_t : 30; + } TSUSM_b; + }; + + union + { + __IOM uint32_t TSUST; /*!< (@ 0x00000004) Sensor Trigger Register */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] A/D Conversion Control */ + uint32_t : 31; + } TSUST_b; + }; + + union + { + __IOM uint32_t TSUSCS; /*!< (@ 0x00000008) Sensor Configuration Setting Register */ + + struct + { + uint32_t : 3; + __IOM uint32_t CKDIV : 1; /*!< [3..3] Divider Value for PCLKL */ + uint32_t : 28; + } TSUSCS_b; + }; + + union + { + __IM uint32_t TSUSAD; /*!< (@ 0x0000000C) Sensor ADC Data Register */ + + struct + { + __IM uint32_t DOUT : 12; /*!< [11..0] Temperature Sensor Data Output */ + uint32_t : 20; + } TSUSAD_b; + }; + + union + { + __IM uint32_t TSUSS; /*!< (@ 0x00000010) Sensor Status Register */ + + struct + { + __IM uint32_t CONV : 1; /*!< [0..0] A/D Conversion Status */ + uint32_t : 31; + } TSUSS_b; + }; +} R_TSU_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG1 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GPT Port Output Enable 1 (R_POEG1) + */ + +typedef struct /*!< (@ 0x80047000) R_POEG1 Structure */ +{ + union + { + __IOM uint32_t POEG1GA; /*!< (@ 0x00000000) POEG1 Group A Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG1GA_b; + }; + __IM uint32_t RESERVED[255]; + + union + { + __IOM uint32_t POEG1GB; /*!< (@ 0x00000400) POEG1 Group B Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG1GB_b; + }; + __IM uint32_t RESERVED1[255]; + + union + { + __IOM uint32_t POEG1GC; /*!< (@ 0x00000800) POEG1 Group C Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG1GC_b; + }; + __IM uint32_t RESERVED2[255]; + + union + { + __IOM uint32_t POEG1GD; /*!< (@ 0x00000C00) POEG1 Group D Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG1GD_b; + }; +} R_POEG1_Type; /*!< Size = 3076 (0xc04) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller 0 (R_DMAC0) + */ + +typedef struct /*!< (@ 0x80080000) R_DMAC0 Structure */ +{ + __IOM R_DMAC0_GRP_Type GRP[2]; /*!< (@ 0x00000000) 8 channel Registers */ +} R_DMAC0_Type; /*!< Size = 2048 (0x800) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU_NS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller in Non Safety Domain (R_ICU_NS) + */ + +typedef struct /*!< (@ 0x80090000) R_ICU_NS Structure */ +{ + union + { + __OM uint32_t NS_SWINT; /*!< (@ 0x00000000) Software Interrupt Register */ + + struct + { + __OM uint32_t IC0 : 1; /*!< [0..0] Software Interrupt register */ + __OM uint32_t IC1 : 1; /*!< [1..1] Software Interrupt register */ + __OM uint32_t IC2 : 1; /*!< [2..2] Software Interrupt register */ + __OM uint32_t IC3 : 1; /*!< [3..3] Software Interrupt register */ + __OM uint32_t IC4 : 1; /*!< [4..4] Software Interrupt register */ + __OM uint32_t IC5 : 1; /*!< [5..5] Software Interrupt register */ + uint32_t : 26; + } NS_SWINT_b; + }; + + union + { + __IOM uint32_t NS_PORTNF_FLTSEL; /*!< (@ 0x00000004) Interrupt Noise Filter Enable Register */ + + struct + { + __IOM uint32_t FLT0 : 1; /*!< [0..0] Noise filter enable for IRQ0 */ + __IOM uint32_t FLT1 : 1; /*!< [1..1] Noise filter enable for IRQ1 */ + __IOM uint32_t FLT2 : 1; /*!< [2..2] Noise filter enable for IRQ2 */ + __IOM uint32_t FLT3 : 1; /*!< [3..3] Noise filter enable for IRQ3 */ + __IOM uint32_t FLT4 : 1; /*!< [4..4] Noise filter enable for IRQ4 */ + __IOM uint32_t FLT5 : 1; /*!< [5..5] Noise filter enable for IRQ5 */ + __IOM uint32_t FLT6 : 1; /*!< [6..6] Noise filter enable for IRQ6 */ + __IOM uint32_t FLT7 : 1; /*!< [7..7] Noise filter enable for IRQ7 */ + __IOM uint32_t FLT8 : 1; /*!< [8..8] Noise filter enable for IRQ8 */ + __IOM uint32_t FLT9 : 1; /*!< [9..9] Noise filter enable for IRQ9 */ + __IOM uint32_t FLT10 : 1; /*!< [10..10] Noise filter enable for IRQ10 */ + __IOM uint32_t FLT11 : 1; /*!< [11..11] Noise filter enable for IRQ11 */ + __IOM uint32_t FLT12 : 1; /*!< [12..12] Noise filter enable for IRQ12 */ + __IOM uint32_t FLT13 : 1; /*!< [13..13] Noise filter enable for IRQ13 */ + __IOM uint32_t FLTDRQ : 1; /*!< [14..14] Noise filter enable for External DMA request (DREQ) */ + uint32_t : 17; + } NS_PORTNF_FLTSEL_b; + }; + + union + { + __IOM uint32_t NS_PORTNF_CLKSEL; /*!< (@ 0x00000008) Interrupt Noise Filter Setting Register */ + + struct + { + __IOM uint32_t CKSEL0 : 2; /*!< [1..0] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL1 : 2; /*!< [3..2] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL2 : 2; /*!< [5..4] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL3 : 2; /*!< [7..6] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL4 : 2; /*!< [9..8] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL5 : 2; /*!< [11..10] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL6 : 2; /*!< [13..12] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL7 : 2; /*!< [15..14] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL8 : 2; /*!< [17..16] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL9 : 2; /*!< [19..18] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL10 : 2; /*!< [21..20] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL11 : 2; /*!< [23..22] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL12 : 2; /*!< [25..24] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL13 : 2; /*!< [27..26] Noise filter sampling clock selector */ + __IOM uint32_t CKSELDREQ : 2; /*!< [29..28] Noise filter sampling clock selector */ + uint32_t : 2; + } NS_PORTNF_CLKSEL_b; + }; + + union + { + __IOM uint32_t NS_PORTNF_MD; /*!< (@ 0x0000000C) Interrupt Edge Detection Setting Register */ + + struct + { + __IOM uint32_t MD0 : 2; /*!< [1..0] Select detection mode for IRQ0 */ + __IOM uint32_t MD1 : 2; /*!< [3..2] Select detection mode for IRQ1 */ + __IOM uint32_t MD2 : 2; /*!< [5..4] Select detection mode for IRQ2 */ + __IOM uint32_t MD3 : 2; /*!< [7..6] Select detection mode for IRQ3 */ + __IOM uint32_t MD4 : 2; /*!< [9..8] Select detection mode for IRQ4 */ + __IOM uint32_t MD5 : 2; /*!< [11..10] Select detection mode for IRQ5 */ + __IOM uint32_t MD6 : 2; /*!< [13..12] Select detection mode for IRQ6 */ + __IOM uint32_t MD7 : 2; /*!< [15..14] Select detection mode for IRQ7 */ + __IOM uint32_t MD8 : 2; /*!< [17..16] Select detection mode for IRQ8 */ + __IOM uint32_t MD9 : 2; /*!< [19..18] Select detection mode for IRQ9 */ + __IOM uint32_t MD10 : 2; /*!< [21..20] Select detection mode for IRQ10 */ + __IOM uint32_t MD11 : 2; /*!< [23..22] Select detection mode for IRQ11 */ + __IOM uint32_t MD12 : 2; /*!< [25..24] Select detection mode for IRQ12 */ + __IOM uint32_t MD13 : 2; /*!< [27..26] Select detection mode for IRQ13 */ + __IOM uint32_t MDDRQ : 2; /*!< [29..28] Select detection mode for DREQ of DMAC */ + uint32_t : 2; + } NS_PORTNF_MD_b; + }; +} R_ICU_NS_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Evnet Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x80090010) R_ELC Structure */ +{ + union + { + __IOM uint32_t ELC_SSEL[19]; /*!< (@ 0x00000000) ELC Event Source Select Register [0..18] */ + + struct + { + __IOM uint32_t ELC_SEL0 : 10; /*!< [9..0] Set the number for ELC event source to be linked to the + * ELC destination. */ + __IOM uint32_t ELC_SEL1 : 10; /*!< [19..10] Set the number for ELC event source to be linked to + * the ELC destination. */ + __IOM uint32_t ELC_SEL2 : 10; /*!< [29..20] Set the number for ELC event source to be linked to + * the ELC destination. */ + uint32_t : 2; + } ELC_SSEL_b[19]; + }; +} R_ELC_Type; /*!< Size = 76 (0x4c) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMAC Configuration (R_DMA) + */ + +typedef struct /*!< (@ 0x80090060) R_DMA Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DMAC0_RSSEL[6]; /*!< (@ 0x0000000C) DMAC Unit 0 Resource Select Register [0..5] */ + + struct + { + __IOM uint32_t REQ_SELA : 9; /*!< [8..0] DMA Resource Select for Channel n */ + uint32_t : 1; + __IOM uint32_t REQ_SELB : 9; /*!< [18..10] DMA Resource Select for Channel n + 1 */ + uint32_t : 1; + __IOM uint32_t REQ_SELC : 9; /*!< [28..20] DMA Resource Select for Channel n + 2 */ + uint32_t : 3; + } DMAC0_RSSEL_b[6]; + }; + + union + { + __IOM uint32_t DMAC1_RSSEL[6]; /*!< (@ 0x00000024) DMAC Unit 1 Resource Select Register [0..5] */ + + struct + { + __IOM uint32_t REQ_SELA : 9; /*!< [8..0] DMA Resource Select for Channel n */ + uint32_t : 1; + __IOM uint32_t REQ_SELB : 9; /*!< [18..10] DMA Resource Select for Channel n + 1 */ + uint32_t : 1; + __IOM uint32_t REQ_SELC : 9; /*!< [28..20] DMA Resource Select for Channel n + 2 */ + uint32_t : 3; + } DMAC1_RSSEL_b[6]; + }; +} R_DMA_Type; /*!< Size = 60 (0x3c) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT_NSR ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (Non safety region) (R_PORT_NSR) + */ + +typedef struct /*!< (@ 0x800A0000) R_PORT_NSR Structure */ +{ + union + { + __IOM uint8_t P[25]; /*!< (@ 0x00000000) Port [0..24] Register */ + + struct + { + __IOM uint8_t POUT_0 : 1; /*!< [0..0] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_1 : 1; /*!< [1..1] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_2 : 1; /*!< [2..2] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_3 : 1; /*!< [3..3] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_4 : 1; /*!< [4..4] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_5 : 1; /*!< [5..5] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_6 : 1; /*!< [6..6] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_7 : 1; /*!< [7..7] Pm_n Output Data Store (n: bit position) */ + } P_b[25]; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[121]; + + union + { + __IOM uint16_t PM[25]; /*!< (@ 0x00000200) Port [0..24] Mode Register */ + + struct + { + __IOM uint16_t PM0 : 2; /*!< [1..0] Pm_0 I/O Select */ + __IOM uint16_t PM1 : 2; /*!< [3..2] Pm_1 I/O Select */ + __IOM uint16_t PM2 : 2; /*!< [5..4] Pm_2 I/O Select */ + __IOM uint16_t PM3 : 2; /*!< [7..6] Pm_3 I/O Select */ + __IOM uint16_t PM4 : 2; /*!< [9..8] Pm_4 I/O Select */ + __IOM uint16_t PM5 : 2; /*!< [11..10] Pm_5 I/O Select */ + __IOM uint16_t PM6 : 2; /*!< [13..12] Pm_6 I/O Select */ + __IOM uint16_t PM7 : 2; /*!< [15..14] Pm_7 I/O Select */ + } PM_b[25]; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[115]; + + union + { + __IOM uint8_t PMC[25]; /*!< (@ 0x00000400) Port [0..24] Mode Control Register */ + + struct + { + __IOM uint8_t PMC0 : 1; /*!< [0..0] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC1 : 1; /*!< [1..1] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC2 : 1; /*!< [2..2] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC3 : 1; /*!< [3..3] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC4 : 1; /*!< [4..4] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC5 : 1; /*!< [5..5] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC6 : 1; /*!< [6..6] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC7 : 1; /*!< [7..7] Pm_n Pin Mode Control (n: bit position) */ + } PMC_b[25]; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[121]; + + union + { + __IOM uint32_t PFC[25]; /*!< (@ 0x00000600) Port [0..24] Function Control Register */ + + struct + { + __IOM uint32_t PFC0 : 4; /*!< [3..0] Pm_0 Pin function Select */ + __IOM uint32_t PFC1 : 4; /*!< [7..4] Pm_1 Pin function Select */ + __IOM uint32_t PFC2 : 4; /*!< [11..8] Pm_2 Pin function Select */ + __IOM uint32_t PFC3 : 4; /*!< [15..12] Pm_3 Pin function Select */ + __IOM uint32_t PFC4 : 4; /*!< [19..16] Pm_4 Pin function Select */ + __IOM uint32_t PFC5 : 4; /*!< [23..20] Pm_5 Pin function Select */ + __IOM uint32_t PFC6 : 4; /*!< [27..24] Pm_6 Pin function Select */ + __IOM uint32_t PFC7 : 4; /*!< [31..28] Pm_7 Pin function Select */ + } PFC_b[25]; + }; + __IM uint32_t RESERVED8[103]; + + union + { + __IM uint8_t PIN[25]; /*!< (@ 0x00000800) Port [0..24] Input Register */ + + struct + { + __IM uint8_t PIN0 : 1; /*!< [0..0] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN1 : 1; /*!< [1..1] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN2 : 1; /*!< [2..2] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN3 : 1; /*!< [3..3] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN4 : 1; /*!< [4..4] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN5 : 1; /*!< [5..5] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN6 : 1; /*!< [6..6] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN7 : 1; /*!< [7..7] Pm_n Pin Input (n: bit position) */ + } PIN_b[25]; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11[121]; + __IOM R_PORT_DRCTL_Type DRCTL[25]; /*!< (@ 0x00000A00) I/O Buffer [0..24] Function Switching Register */ + __IM uint32_t RESERVED12[206]; + + union + { + __IOM uint8_t ELC_PGR[2]; /*!< (@ 0x00000E00) ELC Port Group Setting Register [0..1] */ + + struct + { + __IOM uint8_t PG0 : 1; /*!< [0..0] Port Group Setting */ + __IOM uint8_t PG1 : 1; /*!< [1..1] Port Group Setting */ + __IOM uint8_t PG2 : 1; /*!< [2..2] Port Group Setting */ + __IOM uint8_t PG3 : 1; /*!< [3..3] Port Group Setting */ + __IOM uint8_t PG4 : 1; /*!< [4..4] Port Group Setting */ + __IOM uint8_t PG5 : 1; /*!< [5..5] Port Group Setting */ + __IOM uint8_t PG6 : 1; /*!< [6..6] Port Group Setting */ + __IOM uint8_t PG7 : 1; /*!< [7..7] Port Group Setting */ + } ELC_PGR_b[2]; + }; + + union + { + __IOM uint8_t ELC_PGC[2]; /*!< (@ 0x00000E02) ELC Port Group Control Register [0..1] */ + + struct + { + __IOM uint8_t PGCI : 2; /*!< [1..0] Event Output Edge Select */ + __IOM uint8_t PGCOVE : 1; /*!< [2..2] PDBF Overwrite */ + uint8_t : 1; + __IOM uint8_t PGCO : 3; /*!< [6..4] Port Group Operation Select */ + uint8_t : 1; + } ELC_PGC_b[2]; + }; + __IOM R_PORT_NSR_ELC_PDBF_Type ELC_PDBF[2]; /*!< (@ 0x00000E04) ELC Port Buffer Register [0..1] */ + + union + { + __IOM uint8_t ELC_PEL[4]; /*!< (@ 0x00000E0C) ELC Port Setting Register [0..3] */ + + struct + { + __IOM uint8_t PSB : 3; /*!< [2..0] Bit Number Specification */ + __IOM uint8_t PSP : 2; /*!< [4..3] Port Number Specification */ + __IOM uint8_t PSM : 2; /*!< [6..5] Event Link Specification */ + uint8_t : 1; + } ELC_PEL_b[4]; + }; + + union + { + __IOM uint8_t ELC_DPTC; /*!< (@ 0x00000E10) ELC Edge Detection Control Register */ + + struct + { + __IOM uint8_t PTC0 : 1; /*!< [0..0] Single Input Port n Edge Detection */ + __IOM uint8_t PTC1 : 1; /*!< [1..1] Single Input Port n Edge Detection */ + __IOM uint8_t PTC2 : 1; /*!< [2..2] Single Input Port n Edge Detection */ + __IOM uint8_t PTC3 : 1; /*!< [3..3] Single Input Port n Edge Detection */ + uint8_t : 4; + } ELC_DPTC_b; + }; + + union + { + __IOM uint8_t ELC_ELSR2; /*!< (@ 0x00000E11) ELC Port Event Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t PEG1 : 1; /*!< [2..2] ELC Port Buffer Register (ELC_PDBFn) write access control. + * When set to 1, writing to the ELC_PDBFn register via Internal + * peripheral bus is disabled, preventing overwriting. */ + __IOM uint8_t PEG2 : 1; /*!< [3..3] ELC Port Buffer Register (ELC_PDBFn) write access control. + * When set to 1, writing to the ELC_PDBFn register via Internal + * peripheral bus is disabled, preventing overwriting. */ + __IOM uint8_t PES0 : 1; /*!< [4..4] Single Port n Event Link Function Enable */ + __IOM uint8_t PES1 : 1; /*!< [5..5] Single Port n Event Link Function Enable */ + __IOM uint8_t PES2 : 1; /*!< [6..6] Single Port n Event Link Function Enable */ + __IOM uint8_t PES3 : 1; /*!< [7..7] Single Port n Event Link Function Enable */ + } ELC_ELSR2_b; + }; + __IM uint16_t RESERVED13; +} R_PORT_COMMON_Type; /*!< Size = 3604 (0xe14) */ + +/* =========================================================================================================================== */ +/* ================ R_GMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC (R_GMAC) + */ + +typedef struct /*!< (@ 0x80100000) R_GMAC Structure */ +{ + union + { + __IOM uint32_t MAC_Configuration; /*!< (@ 0x00000000) MAC Configuration Register */ + + struct + { + __IOM uint32_t PRELEN : 2; /*!< [1..0] Preamble Length for Transmit Frames */ + __IOM uint32_t RE : 1; /*!< [2..2] Receiver Enable */ + __IOM uint32_t TE : 1; /*!< [3..3] Transmitter Enable */ + __IOM uint32_t DC : 1; /*!< [4..4] Deferral Check */ + __IOM uint32_t BL : 2; /*!< [6..5] Back-Off Limit */ + __IOM uint32_t ACS : 1; /*!< [7..7] Automatic Pad or CRC Stripping */ + uint32_t : 1; + __IOM uint32_t DR : 1; /*!< [9..9] Disable Retry */ + __IOM uint32_t IPC : 1; /*!< [10..10] Checksum Offload */ + __IOM uint32_t DM : 1; /*!< [11..11] Duplex Mode */ + __IOM uint32_t LM : 1; /*!< [12..12] Loopback Mode */ + __IOM uint32_t DO : 1; /*!< [13..13] Disable Receive Own */ + __IOM uint32_t FES : 1; /*!< [14..14] Speed */ + __IOM uint32_t PS : 1; /*!< [15..15] Port Select */ + __IOM uint32_t DCRS : 1; /*!< [16..16] Disable Carrier Sense During Transmission */ + __IOM uint32_t IFG : 3; /*!< [19..17] Inter-Frame Gap */ + __IOM uint32_t JE : 1; /*!< [20..20] Jumbo Frame Enable */ + __IOM uint32_t BE : 1; /*!< [21..21] Frame Burst Enable */ + __IOM uint32_t JD : 1; /*!< [22..22] Jabber Disable */ + __IOM uint32_t WD : 1; /*!< [23..23] Watchdog Disable */ + uint32_t : 1; + __IOM uint32_t CST : 1; /*!< [25..25] CRC Stripping for Type Frames */ + uint32_t : 1; + __IOM uint32_t TWOKPE : 1; /*!< [27..27] IEEE 802.3 as Support for 2 K Packets */ + uint32_t : 4; + } MAC_Configuration_b; + }; + + union + { + __IOM uint32_t MAC_Frame_Filter; /*!< (@ 0x00000004) MAC Frame Filter Register */ + + struct + { + __IOM uint32_t PR : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t HUC : 1; /*!< [1..1] Hash Unicast */ + __IOM uint32_t HMC : 1; /*!< [2..2] Hash Multicast */ + __IOM uint32_t DAIF : 1; /*!< [3..3] DA Inverse Filtering */ + __IOM uint32_t PM : 1; /*!< [4..4] Pass All Multicast */ + __IOM uint32_t DBF : 1; /*!< [5..5] Disable Broadcast Frames */ + __IOM uint32_t PCF : 2; /*!< [7..6] Pass Control Frames */ + __IOM uint32_t SAIF : 1; /*!< [8..8] SA Inverse Filtering */ + __IOM uint32_t SAF : 1; /*!< [9..9] Source Address Filter Enable */ + __IOM uint32_t HPF : 1; /*!< [10..10] Hash or Perfect Filter */ + uint32_t : 5; + __IOM uint32_t VTFE : 1; /*!< [16..16] VLAN Tag Filter Enable */ + uint32_t : 14; + __IOM uint32_t RA : 1; /*!< [31..31] Receive All */ + } MAC_Frame_Filter_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GMII_Address; /*!< (@ 0x00000010) GMII Address Register */ + + struct + { + __IOM uint32_t GB : 1; /*!< [0..0] GMII Busy */ + __IOM uint32_t GW : 1; /*!< [1..1] GMII Write */ + __IOM uint32_t CR : 4; /*!< [5..2] CSR Clock Range */ + __IOM uint32_t GR : 5; /*!< [10..6] GMII Register */ + __IOM uint32_t PA : 5; /*!< [15..11] Physical Layer Address */ + uint32_t : 16; + } GMII_Address_b; + }; + + union + { + __IOM uint32_t GMII_Data; /*!< (@ 0x00000014) GMII Data Register */ + + struct + { + __IOM uint32_t GD : 16; /*!< [15..0] GMII Data */ + uint32_t : 16; + } GMII_Data_b; + }; + + union + { + __IOM uint32_t Flow_Control; /*!< (@ 0x00000018) Flow Control Register */ + + struct + { + __IOM uint32_t FCA_BPA : 1; /*!< [0..0] Flow Control Busy or Backpressure Activate */ + __IOM uint32_t TFE : 1; /*!< [1..1] Transmit Flow Control Enable */ + __IOM uint32_t RFE : 1; /*!< [2..2] Receive Flow Control Enable */ + __IOM uint32_t UP : 1; /*!< [3..3] Unicast Pause Frame Detect */ + __IOM uint32_t PLT : 2; /*!< [5..4] Pause Low Threshold */ + uint32_t : 1; + __IOM uint32_t DZPQ : 1; /*!< [7..7] Disable Zero-Quanta Pause */ + uint32_t : 8; + __IOM uint32_t PT : 16; /*!< [31..16] Pause Time */ + } Flow_Control_b; + }; + + union + { + __IOM uint32_t VLAN_Tag; /*!< (@ 0x0000001C) VLAN Tag Register */ + + struct + { + __IOM uint32_t VL : 16; /*!< [15..0] VLAN Tag Identifier for Receive Frames */ + __IOM uint32_t ETV : 1; /*!< [16..16] Enable 12-Bit VLAN Tag Comparison */ + __IOM uint32_t VTIM : 1; /*!< [17..17] VLAN Tag Inverse Match Enable */ + __IOM uint32_t ESVL : 1; /*!< [18..18] Enable S-VLAN */ + __IOM uint32_t VTHM : 1; /*!< [19..19] VLAN Tag Hash Table Match Enable */ + uint32_t : 12; + } VLAN_Tag_b; + }; + + union + { + __IM uint32_t Version; /*!< (@ 0x00000020) Version Register */ + + struct + { + __IM uint32_t VER : 16; /*!< [15..0] Version (GMAC: 0x3137) */ + uint32_t : 16; + } Version_b; + }; + + union + { + __IM uint32_t Debug; /*!< (@ 0x00000024) Debug Register */ + + struct + { + __IM uint32_t RPESTS : 1; /*!< [0..0] GMAC GMII or MII Receive Protocol Engine Status */ + __IM uint32_t RFCFCSTS : 2; /*!< [2..1] GMAC Receive Frame Controller FIFO Status */ + uint32_t : 1; + __IM uint32_t RWCSTS : 1; /*!< [4..4] MTL RX FIFO Write Controller Active Status */ + __IM uint32_t RRCSTS : 2; /*!< [6..5] MTL RX FIFO Read Controller State */ + uint32_t : 1; + __IM uint32_t RXFSTS : 2; /*!< [9..8] MTL RX FIFO Fill-level Status */ + uint32_t : 6; + __IM uint32_t TPESTS : 1; /*!< [16..16] GMAC GMII or MII Transmit Protocol Engine Status */ + __IM uint32_t TFCSTS : 2; /*!< [18..17] GMAC Transmit Frame Controller Status */ + __IM uint32_t TXPAUSED : 1; /*!< [19..19] GMAC transmitter in PAUSE */ + __IM uint32_t TRCSTS : 2; /*!< [21..20] MTL TX FIFO Read Controller Status */ + __IM uint32_t TWCSTS : 1; /*!< [22..22] MTL TX FIFO Write Controller Active Status */ + uint32_t : 1; + __IM uint32_t TXFSTS : 1; /*!< [24..24] MTL TX FIFO Not Empty Status */ + __IM uint32_t TXSTSFSTS : 1; /*!< [25..25] MTL TX Status FIFO Full Status */ + uint32_t : 6; + } Debug_b; + }; + + union + { + __IOM uint32_t Remote_Wake_Up_Frame_Filter; /*!< (@ 0x00000028) Remote Wake-Up Frame Filter Register */ + + struct + { + __IOM uint32_t WKUPFRMFTR : 32; /*!< [31..0] Remote Wake-Up Frame Filter */ + } Remote_Wake_Up_Frame_Filter_b; + }; + + union + { + __IOM uint32_t PMT_Control_Status; /*!< (@ 0x0000002C) PMT Control and Status Register */ + + struct + { + __IOM uint32_t PWRDWN : 1; /*!< [0..0] Power Down */ + __IOM uint32_t MGKPKTEN : 1; /*!< [1..1] Magic Packet Enable */ + __IOM uint32_t RWKPKTEN : 1; /*!< [2..2] Wake-Up Frame Enable */ + uint32_t : 2; + __IM uint32_t MGKPRCVD : 1; /*!< [5..5] Magic Packet Received */ + __IM uint32_t RWKPRCVD : 1; /*!< [6..6] Wake-Up Frame Received */ + uint32_t : 2; + __IOM uint32_t GLBLUCAST : 1; /*!< [9..9] Global Unicast */ + uint32_t : 14; + __IM uint32_t RWKPTR : 3; /*!< [26..24] Remote Wake-Up FIFO Pointer */ + uint32_t : 4; + __IOM uint32_t RWKFILTRST : 1; /*!< [31..31] Wake-Up Frame Filter Register Pointer Reset */ + } PMT_Control_Status_b; + }; + + union + { + __IOM uint32_t LPI_Control_Status; /*!< (@ 0x00000030) LPI Control and Status Register */ + + struct + { + __IM uint32_t TLPIEN : 1; /*!< [0..0] Transmit LPI Entry */ + __IM uint32_t TLPIEX : 1; /*!< [1..1] Transmit LPI Exit */ + __IM uint32_t RLPIEN : 1; /*!< [2..2] Receive LPI Entry */ + __IM uint32_t RLPIEX : 1; /*!< [3..3] Receive LPI Exit */ + uint32_t : 4; + __IM uint32_t TLPIST : 1; /*!< [8..8] Transmit LPI State */ + __IM uint32_t RLPIST : 1; /*!< [9..9] Receive LPI State */ + uint32_t : 6; + __IOM uint32_t LPIEN : 1; /*!< [16..16] LPI Enable */ + __IOM uint32_t PLS : 1; /*!< [17..17] PHY Link Status */ + uint32_t : 1; + __IOM uint32_t LPITXA : 1; /*!< [19..19] LPI TX Automate */ + uint32_t : 12; + } LPI_Control_Status_b; + }; + + union + { + __IOM uint32_t LPI_Timers_Control; /*!< (@ 0x00000034) LPI Timers Control Register */ + + struct + { + __IOM uint32_t TWT : 16; /*!< [15..0] LPI TW Timer */ + __IOM uint32_t LST : 10; /*!< [25..16] LPI LS Timer */ + uint32_t : 6; + } LPI_Timers_Control_b; + }; + + union + { + __IM uint32_t Interrupt_Status; /*!< (@ 0x00000038) Interrupt Status Register */ + + struct + { + uint32_t : 3; + __IM uint32_t PMTIS : 1; /*!< [3..3] PMT Interrupt Status */ + __IM uint32_t MMCIS : 1; /*!< [4..4] MMC Interrupt Status */ + __IM uint32_t MMCRXIS : 1; /*!< [5..5] MMC Receive Interrupt Status */ + __IM uint32_t MMCTXIS : 1; /*!< [6..6] MMC Transmit Interrupt Status */ + __IM uint32_t MMCRXIPIS : 1; /*!< [7..7] MMC Receive Checksum Offload Interrupt Status */ + uint32_t : 1; + __IM uint32_t TSIS : 1; /*!< [9..9] Timestamp Interrupt Status */ + __IM uint32_t LPIIS : 1; /*!< [10..10] LPI Interrupt Status */ + uint32_t : 21; + } Interrupt_Status_b; + }; + + union + { + __IOM uint32_t Interrupt_Mask; /*!< (@ 0x0000003C) Interrupt Mask Register */ + + struct + { + uint32_t : 3; + __IOM uint32_t PMTIM : 1; /*!< [3..3] PMT Interrupt Mask */ + uint32_t : 5; + __IOM uint32_t TSIM : 1; /*!< [9..9] Timestamp Interrupt Mask */ + __IOM uint32_t LPIIM : 1; /*!< [10..10] LPI Interrupt Mask */ + uint32_t : 21; + } Interrupt_Mask_b; + }; + + union + { + __IOM uint32_t MAR0_H; /*!< (@ 0x00000040) MAC Address 0 High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address0[47:32] */ + uint32_t : 15; + __IM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR0_H_b; + }; + + union + { + __IOM uint32_t MAR0_L; /*!< (@ 0x00000044) MAC Address 0 Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address0[31:0] */ + } MAR0_L_b; + }; + + union + { + __IOM uint32_t MAR1_H; /*!< (@ 0x00000048) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR1_H_b; + }; + + union + { + __IOM uint32_t MAR1_L; /*!< (@ 0x0000004C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR1_L_b; + }; + + union + { + __IOM uint32_t MAR2_H; /*!< (@ 0x00000050) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR2_H_b; + }; + + union + { + __IOM uint32_t MAR2_L; /*!< (@ 0x00000054) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR2_L_b; + }; + + union + { + __IOM uint32_t MAR3_H; /*!< (@ 0x00000058) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR3_H_b; + }; + + union + { + __IOM uint32_t MAR3_L; /*!< (@ 0x0000005C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR3_L_b; + }; + + union + { + __IOM uint32_t MAR4_H; /*!< (@ 0x00000060) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR4_H_b; + }; + + union + { + __IOM uint32_t MAR4_L; /*!< (@ 0x00000064) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR4_L_b; + }; + + union + { + __IOM uint32_t MAR5_H; /*!< (@ 0x00000068) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR5_H_b; + }; + + union + { + __IOM uint32_t MAR5_L; /*!< (@ 0x0000006C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR5_L_b; + }; + + union + { + __IOM uint32_t MAR6_H; /*!< (@ 0x00000070) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR6_H_b; + }; + + union + { + __IOM uint32_t MAR6_L; /*!< (@ 0x00000074) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR6_L_b; + }; + + union + { + __IOM uint32_t MAR7_H; /*!< (@ 0x00000078) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR7_H_b; + }; + + union + { + __IOM uint32_t MAR7_L; /*!< (@ 0x0000007C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR7_L_b; + }; + + union + { + __IOM uint32_t MAR8_H; /*!< (@ 0x00000080) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR8_H_b; + }; + + union + { + __IOM uint32_t MAR8_L; /*!< (@ 0x00000084) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR8_L_b; + }; + + union + { + __IOM uint32_t MAR9_H; /*!< (@ 0x00000088) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR9_H_b; + }; + + union + { + __IOM uint32_t MAR9_L; /*!< (@ 0x0000008C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR9_L_b; + }; + + union + { + __IOM uint32_t MAR10_H; /*!< (@ 0x00000090) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR10_H_b; + }; + + union + { + __IOM uint32_t MAR10_L; /*!< (@ 0x00000094) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR10_L_b; + }; + + union + { + __IOM uint32_t MAR11_H; /*!< (@ 0x00000098) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR11_H_b; + }; + + union + { + __IOM uint32_t MAR11_L; /*!< (@ 0x0000009C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR11_L_b; + }; + + union + { + __IOM uint32_t MAR12_H; /*!< (@ 0x000000A0) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR12_H_b; + }; + + union + { + __IOM uint32_t MAR12_L; /*!< (@ 0x000000A4) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR12_L_b; + }; + + union + { + __IOM uint32_t MAR13_H; /*!< (@ 0x000000A8) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR13_H_b; + }; + + union + { + __IOM uint32_t MAR13_L; /*!< (@ 0x000000AC) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR13_L_b; + }; + + union + { + __IOM uint32_t MAR14_H; /*!< (@ 0x000000B0) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR14_H_b; + }; + + union + { + __IOM uint32_t MAR14_L; /*!< (@ 0x000000B4) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR14_L_b; + }; + + union + { + __IOM uint32_t MAR15_H; /*!< (@ 0x000000B8) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR15_H_b; + }; + + union + { + __IOM uint32_t MAR15_L; /*!< (@ 0x000000BC) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR15_L_b; + }; + __IM uint32_t RESERVED1[7]; + + union + { + __IOM uint32_t WDog_Timeout; /*!< (@ 0x000000DC) Watchdog Timeout Register */ + + struct + { + __IOM uint32_t WTO : 14; /*!< [13..0] Watchdog Timeout */ + uint32_t : 2; + __IOM uint32_t PWE : 1; /*!< [16..16] Programmable Watchdog Enable */ + uint32_t : 15; + } WDog_Timeout_b; + }; + __IM uint32_t RESERVED2[8]; + + union + { + __IOM uint32_t MMC_Control; /*!< (@ 0x00000100) MMC Control Register */ + + struct + { + __IOM uint32_t CNTRST : 1; /*!< [0..0] Counters Reset */ + __IOM uint32_t CNTSTOPRO : 1; /*!< [1..1] Counters Stop Rollover */ + __IOM uint32_t RSTONRD : 1; /*!< [2..2] Reset on Read */ + __IOM uint32_t CNTFREEZ : 1; /*!< [3..3] MMC Counter Freeze */ + __IOM uint32_t CNTPRST : 1; /*!< [4..4] Counters Preset */ + __IOM uint32_t CNTPRSTLVL : 1; /*!< [5..5] Full-Half Preset */ + uint32_t : 2; + __IOM uint32_t UCDBC : 1; /*!< [8..8] Update MMC Counters for Dropped Broadcast Frames */ + uint32_t : 23; + } MMC_Control_b; + }; + + union + { + __IM uint32_t MMC_Receive_Interrupt; /*!< (@ 0x00000104) MMC Receive Interrupt Register */ + + struct + { + __IM uint32_t RXGBFRMIS : 1; /*!< [0..0] MMC Receive Good Bad Frame Counter Interrupt Status */ + __IM uint32_t RXGBOCTIS : 1; /*!< [1..1] MMC Receive Good Bad Octet Counter Interrupt Status */ + __IM uint32_t RXGOCTIS : 1; /*!< [2..2] MMC Receive Good Octet Counter Interrupt Status */ + __IM uint32_t RXBCGFIS : 1; /*!< [3..3] MMC Receive Broadcast Good Frame Counter Interrupt Status */ + __IM uint32_t RXMCGFIS : 1; /*!< [4..4] MMC Receive Multicast Good Frame Counter Interrupt Status */ + __IM uint32_t RXCRCERFIS : 1; /*!< [5..5] MMC Receive CRC Error Frame Counter Interrupt Status */ + __IM uint32_t RXALGNERFIS : 1; /*!< [6..6] MMC Receive Alignment Error Frame Counter Interrupt Status */ + __IM uint32_t RXRUNTFIS : 1; /*!< [7..7] MMC Receive Runt Frame Counter Interrupt Status */ + __IM uint32_t RXJABERFIS : 1; /*!< [8..8] MMC Receive Jabber Error Frame Counter Interrupt Status */ + __IM uint32_t RXUSIZEGFIS : 1; /*!< [9..9] MMC Receive Undersize Good Frame Counter Interrupt Status */ + __IM uint32_t RXOSIZEGFIS : 1; /*!< [10..10] MMC Receive Oversize Good Frame Counter Interrupt Status */ + __IM uint32_t RX64OCTGBFIS : 1; /*!< [11..11] MMC Receive 64 Octet Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t RX65T127OCTGBFIS : 1; /*!< [12..12] MMC Receive 65 to 127 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t RX128T255OCTGBFIS : 1; /*!< [13..13] MMC Receive 128 to 255 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t RX256T511OCTGBFIS : 1; /*!< [14..14] MMC Receive 256 to 511 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t RX512T1023OCTGBFIS : 1; /*!< [15..15] MMC Receive 512 to 1023 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t RX1024TMAXOCTGBFIS : 1; /*!< [16..16] MMC Receive 1024 to Maximum Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t RXUCGFIS : 1; /*!< [17..17] MMC Receive Unicast Good Frame Counter Interrupt Status */ + __IM uint32_t RXLENERFIS : 1; /*!< [18..18] MMC Receive Length Error Frame Counter Interrupt Status */ + __IM uint32_t RXORANGEFIS : 1; /*!< [19..19] MMC Receive Out Of Range Error Frame Counter Interrupt + * Status */ + __IM uint32_t RXPAUSFIS : 1; /*!< [20..20] MMC Receive Pause Frame Counter Interrupt Status */ + __IM uint32_t RXFOVFIS : 1; /*!< [21..21] MMC Receive FIFO Overflow Frame Counter Interrupt Status */ + __IM uint32_t RXVLANGBFIS : 1; /*!< [22..22] MMC Receive VLAN Good Bad Frame Counter Interrupt Status */ + __IM uint32_t RXWDOGFIS : 1; /*!< [23..23] MMC Receive Watchdog Error Frame Counter Interrupt + * Status */ + __IM uint32_t RXRCVERRFIS : 1; /*!< [24..24] MMC Receive Error Frame Counter Interrupt Status */ + __IM uint32_t RXCTRLFIS : 1; /*!< [25..25] MMC Receive Control Frame Counter Interrupt Status */ + uint32_t : 6; + } MMC_Receive_Interrupt_b; + }; + + union + { + __IM uint32_t MMC_Transmit_Interrupt; /*!< (@ 0x00000108) MMC Transmit Interrupt Register */ + + struct + { + __IM uint32_t TXGBOCTIS : 1; /*!< [0..0] MMC Transmit Good Bad Octet Counter Interrupt Status */ + __IM uint32_t TXGBFRMIS : 1; /*!< [1..1] MMC Transmit Good Bad Frame Counter Interrupt Status */ + __IM uint32_t TXBCGFIS : 1; /*!< [2..2] MMC Transmit Broadcast Good Frame Counter Interrupt Status */ + __IM uint32_t TXMCGFIS : 1; /*!< [3..3] MMC Transmit Multicast Good Frame Counter Interrupt Status */ + __IM uint32_t TX64OCTGBFIS : 1; /*!< [4..4] MMC Transmit 64 Octet Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t TX65T127OCTGBFIS : 1; /*!< [5..5] MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t TX128T255OCTGBFIS : 1; /*!< [6..6] MMC Transmit 128 to 255 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t TX256T511OCTGBFIS : 1; /*!< [7..7] MMC Transmit 256 to 511 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t TX512T1023OCTGBFIS : 1; /*!< [8..8] MMC Transmit 512 to 1023 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t TX1024TMAXOCTGBFIS : 1; /*!< [9..9] MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t TXUCGBFIS : 1; /*!< [10..10] MMC Transmit Unicast Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t TXMCGBFIS : 1; /*!< [11..11] MMC Transmit Multicast Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t TXBCGBFIS : 1; /*!< [12..12] MMC Transmit Broadcast Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t TXUFLOWERFIS : 1; /*!< [13..13] MMC Transmit Underflow Error Frame Counter Interrupt + * Status */ + __IM uint32_t TXSCOLGFIS : 1; /*!< [14..14] MMC Transmit Single Collision Good Frame Counter Interrupt + * Status */ + __IM uint32_t TXMCOLGFIS : 1; /*!< [15..15] MMC Transmit Multiple Collision Good Frame Counter + * Interrupt Status */ + __IM uint32_t TXDEFFIS : 1; /*!< [16..16] MMC Transmit Deferred Frame Counter Interrupt Status */ + __IM uint32_t TXLATCOLFIS : 1; /*!< [17..17] MMC Transmit Late Collision Frame Counter Interrupt + * Status */ + __IM uint32_t TXEXCOLFIS : 1; /*!< [18..18] MMC Transmit Excessive Collision Frame Counter Interrupt + * Status */ + __IM uint32_t TXCARERFIS : 1; /*!< [19..19] MMC Transmit Carrier Error Frame Counter Interrupt + * Status */ + __IM uint32_t TXGOCTIS : 1; /*!< [20..20] MMC Transmit Good Octet Counter Interrupt Status */ + __IM uint32_t TXGFRMIS : 1; /*!< [21..21] MMC Transmit Good Frame Counter Interrupt Status */ + __IM uint32_t TXEXDEFFIS : 1; /*!< [22..22] MMC Transmit Excessive Deferral Frame Counter Interrupt + * Status */ + __IM uint32_t TXPAUSFIS : 1; /*!< [23..23] MMC Transmit Pause Frame Counter Interrupt Status */ + __IM uint32_t TXVLANGFIS : 1; /*!< [24..24] MMC Transmit VLAN Good Frame Counter Interrupt Status */ + __IM uint32_t TXOSIZEGFIS : 1; /*!< [25..25] MMC Transmit Oversize Good Frame Counter Interrupt + * Status */ + uint32_t : 6; + } MMC_Transmit_Interrupt_b; + }; + + union + { + __IOM uint32_t MMC_Receive_Interrupt_Mask; /*!< (@ 0x0000010C) MMC Receive Interrupt Mask Register */ + + struct + { + __IOM uint32_t RXGBFRMIM : 1; /*!< [0..0] MMC Receive Good Bad Frame Counter Interrupt Mask */ + __IOM uint32_t RXGBOCTIM : 1; /*!< [1..1] MMC Receive Good Bad Octet Counter Interrupt Mask */ + __IOM uint32_t RXGOCTIM : 1; /*!< [2..2] MMC Receive Good Octet Counter Interrupt Mask */ + __IOM uint32_t RXBCGFIM : 1; /*!< [3..3] MMC Receive Broadcast Good Frame Counter Interrupt Mask */ + __IOM uint32_t RXMCGFIM : 1; /*!< [4..4] MMC Receive Multicast Good Frame Counter Interrupt Mask */ + __IOM uint32_t RXCRCERFIM : 1; /*!< [5..5] MMC Receive CRC Error Frame Counter Interrupt Mask */ + __IOM uint32_t RXALGNERFIM : 1; /*!< [6..6] MMC Receive Alignment Error Frame Counter Interrupt Mask */ + __IOM uint32_t RXRUNTFIM : 1; /*!< [7..7] MMC Receive Runt Frame Counter Interrupt Mask */ + __IOM uint32_t RXJABERFIM : 1; /*!< [8..8] MMC Receive Jabber Error Frame Counter Interrupt Mask */ + __IOM uint32_t RXUSIZEGFIM : 1; /*!< [9..9] MMC Receive Undersize Good Frame Counter Interrupt Mask */ + __IOM uint32_t RXOSIZEGFIM : 1; /*!< [10..10] MMC Receive Oversize Good Frame Counter Interrupt Mask */ + __IOM uint32_t RX64OCTGBFIM : 1; /*!< [11..11] MMC Receive 64 Octet Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t RX65T127OCTGBFIM : 1; /*!< [12..12] MMC Receive 65 to 127 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t RX128T255OCTGBFIM : 1; /*!< [13..13] MMC Receive 128 to 255 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t RX256T511OCTGBFIM : 1; /*!< [14..14] MMC Receive 256 to 511 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t RX512T1023OCTGBFIM : 1; /*!< [15..15] MMC Receive 512 to 1023 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t RX1024TMAXOCTGBFIM : 1; /*!< [16..16] MMC Receive 1024 to Maximum Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t RXUCGFIM : 1; /*!< [17..17] MMC Receive Unicast Good Frame Counter Interrupt Mask */ + __IOM uint32_t RXLENERFIM : 1; /*!< [18..18] MMC Receive Length Error Frame Counter Interrupt Mask */ + __IOM uint32_t RXORANGEFIM : 1; /*!< [19..19] MMC Receive Out Of Range Error Frame Counter Interrupt + * Mask */ + __IOM uint32_t RXPAUSFIM : 1; /*!< [20..20] MMC Receive Pause Frame Counter Interrupt Mask */ + __IOM uint32_t RXFOVFIM : 1; /*!< [21..21] MMC Receive FIFO Overflow Frame Counter Interrupt Mask */ + __IOM uint32_t RXVLANGBFIM : 1; /*!< [22..22] MMC Receive VLAN Good Bad Frame Counter Interrupt Mask */ + __IOM uint32_t RXWDOGFIM : 1; /*!< [23..23] MMC Receive Watchdog Error Frame Counter Interrupt + * Mask */ + __IOM uint32_t RXRCVERRFIM : 1; /*!< [24..24] MMC Receive Error Frame Counter Interrupt Mask */ + __IOM uint32_t RXCTRLFIM : 1; /*!< [25..25] MMC Receive Control Frame Counter Interrupt Mask */ + uint32_t : 6; + } MMC_Receive_Interrupt_Mask_b; + }; + + union + { + __IOM uint32_t MMC_Transmit_Interrupt_Mask; /*!< (@ 0x00000110) MMC Transmit Interrupt Mask Register */ + + struct + { + __IOM uint32_t TXGBOCTIM : 1; /*!< [0..0] MMC Transmit Good Bad Octet Counter Interrupt Mask */ + __IOM uint32_t TXGBFRMIM : 1; /*!< [1..1] MMC Transmit Good Bad Frame Counter Interrupt Mask */ + __IOM uint32_t TXBCGFIM : 1; /*!< [2..2] MMC Transmit Broadcast Good Frame Counter Interrupt Mask */ + __IOM uint32_t TXMCGFIM : 1; /*!< [3..3] MMC Transmit Multicast Good Frame Counter Interrupt Mask */ + __IOM uint32_t TX64OCTGBFIM : 1; /*!< [4..4] MMC Transmit 64 Octet Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t TX65T127OCTGBFIM : 1; /*!< [5..5] MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t TX128T255OCTGBFIM : 1; /*!< [6..6] MMC Transmit 128 to 255 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t TX256T511OCTGBFIM : 1; /*!< [7..7] MMC Transmit 256 to 511 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t TX512T1023OCTGBFIM : 1; /*!< [8..8] MMC Transmit 512 to 1023 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t TX1024TMAXOCTGBFIM : 1; /*!< [9..9] MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t TXUCGBFIM : 1; /*!< [10..10] MMC Transmit Unicast Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXMCGBFIM : 1; /*!< [11..11] MMC Transmit Multicast Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXBCGBFIM : 1; /*!< [12..12] MMC Transmit Broadcast Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXUFLOWERFIM : 1; /*!< [13..13] MMC Transmit Underflow Error Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXSCOLGFIM : 1; /*!< [14..14] MMC Transmit Single Collision Good Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXMCOLGFIM : 1; /*!< [15..15] MMC Transmit Multiple Collision Good Frame Counter + * Interrupt Mask */ + __IOM uint32_t TXDEFFIM : 1; /*!< [16..16] MMC Transmit Deferred Frame Counter Interrupt Mask */ + __IOM uint32_t TXLATCOLFIM : 1; /*!< [17..17] MMC Transmit Late Collision Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXEXCOLFIM : 1; /*!< [18..18] MMC Transmit Excessive Collision Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXCARERFIM : 1; /*!< [19..19] MMC Transmit Carrier Error Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXGOCTIM : 1; /*!< [20..20] MMC Transmit Good Octet Counter Interrupt Mask */ + __IOM uint32_t TXGFRMIM : 1; /*!< [21..21] MMC Transmit Good Frame Counter Interrupt Mask */ + __IOM uint32_t TXEXDEFFIM : 1; /*!< [22..22] MMC Transmit Excessive Deferral Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXPAUSFIM : 1; /*!< [23..23] MMC Transmit Pause Frame Counter Interrupt Mask */ + __IOM uint32_t TXVLANGFIM : 1; /*!< [24..24] MMC Transmit VLAN Good Frame Counter Interrupt Mask */ + __IOM uint32_t TXOSIZEGFIM : 1; /*!< [25..25] MMC Transmit Oversize Good Frame Counter Interrupt + * Mask */ + uint32_t : 6; + } MMC_Transmit_Interrupt_Mask_b; + }; + + union + { + __IM uint32_t Tx_Octet_Count_Good_Bad; /*!< (@ 0x00000114) Transmit Octet Count for Good and Bad Frames */ + + struct + { + __IM uint32_t TXOCTGB : 32; /*!< [31..0] This field indicates the number of bytes transmitted + * in good and bad frames exclusive of preamble and retried + * bytes. */ + } Tx_Octet_Count_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Frame_Count_Good_Bad; /*!< (@ 0x00000118) Transmit Frame Count for Good and Bad Frames */ + + struct + { + __IM uint32_t TXFRMGB : 32; /*!< [31..0] This field indicates the number of good and bad frames + * transmitted, exclusive of retried frames. */ + } Tx_Frame_Count_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Broadcast_Frames_Good; /*!< (@ 0x0000011C) Transmit Frame Count for Good Broadcast Frames */ + + struct + { + __IM uint32_t TXBCASTG : 32; /*!< [31..0] This field indicates the number of transmitted good + * broadcast frames. */ + } Tx_Broadcast_Frames_Good_b; + }; + + union + { + __IM uint32_t Tx_Multicast_Frames_Good; /*!< (@ 0x00000120) Transmit Frame Count for Good Multicast Frames */ + + struct + { + __IM uint32_t TXMCASTG : 32; /*!< [31..0] This field indicates the number of transmitted good + * multicast frames. */ + } Tx_Multicast_Frames_Good_b; + }; + + union + { + __IM uint32_t Tx_64Octets_Frames_Good_Bad; /*!< (@ 0x00000124) Transmit Octet Count for Good and Bad 64 Byte + * Frames */ + + struct + { + __IM uint32_t TX64OCTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad frames with length of 64 bytes, exclusive of preamble + * and retried frames. */ + } Tx_64Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_65To127Octets_Frames_Good_Bad; /*!< (@ 0x00000128) Transmit Octet Count for Good and Bad 65 to 127 + * Bytes Frames */ + + struct + { + __IM uint32_t TX65_127OCTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad frames with length between 65 and 127 (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Tx_65To127Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_128To255Octets_Frames_Good_Bad; /*!< (@ 0x0000012C) Transmit Octet Count for Good and Bad 128 to + * 255 Bytes Frames */ + + struct + { + __IM uint32_t TX128_255OCTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad frames with length between 128 and 255 (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Tx_128To255Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_256To511Octets_Frames_Good_Bad; /*!< (@ 0x00000130) Transmit Octet Count for Good and Bad 256 to + * 511 Bytes Frames */ + + struct + { + __IM uint32_t TX256_511OCTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad frames with length between 256 and 511 (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Tx_256To511Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_512To1023Octets_Frames_Good_Bad; /*!< (@ 0x00000134) Transmit Octet Count for Good and Bad 512 to + * 1023 Bytes Frames */ + + struct + { + __IM uint32_t TX512_1023OCTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad frames with length between 512 and 1,023 (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Tx_512To1023Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_1024ToMaxOctets_Frames_Good_Bad; /*!< (@ 0x00000138) Transmit Octet Count for Good and Bad 1024 to + * Maxsize Bytes Frames */ + + struct + { + __IM uint32_t TX1024_MAXOCTGB : 32; /*!< [31..0] This field indicates the number of good and bad frames + * transmitted with length between 1,024 and maxsize (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Tx_1024ToMaxOctets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Unicast_Frames_Good_Bad; /*!< (@ 0x0000013C) Transmit Frame Count for Good and Bad Unicast + * Frames */ + + struct + { + __IM uint32_t TXUCASTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad unicast frames. */ + } Tx_Unicast_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Multicast_Frames_Good_Bad; /*!< (@ 0x00000140) Transmit Frame Count for Good and Bad Multicast + * Frames */ + + struct + { + __IM uint32_t TXMCASTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad multicast frames. */ + } Tx_Multicast_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Broadcast_Frames_Good_Bad; /*!< (@ 0x00000144) Transmit Frame Count for Good and Bad Broadcast + * Frames */ + + struct + { + __IM uint32_t TXBCASTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad broadcast frames. */ + } Tx_Broadcast_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Underflow_Error_Frames; /*!< (@ 0x00000148) Transmit Frame Count for Underflow Error Frames */ + + struct + { + __IM uint32_t TXUNDRFLW : 16; /*!< [15..0] This field indicates the number of frames aborted because + * of frame underflow error. */ + uint32_t : 16; + } Tx_Underflow_Error_Frames_b; + }; + + union + { + __IM uint32_t Tx_Single_Collision_Good_Frames; /*!< (@ 0x0000014C) Transmit Frame Count for Frames Transmitted after + * Single Collision */ + + struct + { + __IM uint32_t TXSNGLCOLG : 16; /*!< [15..0] This field indicates the number of successfully transmitted + * frames after a single collision in the half-duplex mode. */ + uint32_t : 16; + } Tx_Single_Collision_Good_Frames_b; + }; + + union + { + __IM uint32_t Tx_Multiple_Collision_Good_Frames; /*!< (@ 0x00000150) Transmit Frame Count for Frames Transmitted after + * Multiple Collision */ + + struct + { + __IM uint32_t TXMULTCOLG : 16; /*!< [15..0] This field indicates the number of successfully transmitted + * frames after multiple collisions in the half-duplex mode. */ + uint32_t : 16; + } Tx_Multiple_Collision_Good_Frames_b; + }; + + union + { + __IM uint32_t Tx_Deferred_Frames; /*!< (@ 0x00000154) Transmit Frame Count for Deferred Frames */ + + struct + { + __IM uint32_t TXDEFRD : 16; /*!< [15..0] This field indicates the number of successfully transmitted + * frames after a deferral in the half-duplex mode. */ + uint32_t : 16; + } Tx_Deferred_Frames_b; + }; + + union + { + __IM uint32_t Tx_Late_Collision_Frames; /*!< (@ 0x00000158) Transmit Frame Count for Late Collision Error + * Frames */ + + struct + { + __IM uint32_t TXLATECOL : 16; /*!< [15..0] This field indicates the number of frames aborted because + * of late collision error. */ + uint32_t : 16; + } Tx_Late_Collision_Frames_b; + }; + + union + { + __IM uint32_t Tx_Excessive_Collision_Frames; /*!< (@ 0x0000015C) Transmit Frame Count for Excessive Collision + * Error Frames */ + + struct + { + __IM uint32_t TXEXSCOL : 16; /*!< [15..0] This field indicates the number of frames aborted because + * of excessive (16) collision error. */ + uint32_t : 16; + } Tx_Excessive_Collision_Frames_b; + }; + + union + { + __IM uint32_t Tx_Carrier_Error_Frames; /*!< (@ 0x00000160) Transmit Frame Count for Carrier Sense Error + * Frames */ + + struct + { + __IM uint32_t TXCARR : 16; /*!< [15..0] This field indicates the number of frames aborted because + * of carrier sense error (no carrier or loss of carrier). */ + uint32_t : 16; + } Tx_Carrier_Error_Frames_b; + }; + + union + { + __IM uint32_t Tx_Octet_Count_Good; /*!< (@ 0x00000164) Transmit Octet Count for Good Frames */ + + struct + { + __IM uint32_t TXOCTG : 32; /*!< [31..0] TXOCTG */ + } Tx_Octet_Count_Good_b; + }; + + union + { + __IM uint32_t Tx_Frame_Count_Good; /*!< (@ 0x00000168) Transmit Frame Count for Good Frames */ + + struct + { + __IM uint32_t TXFRMG : 32; /*!< [31..0] This field indicates the number of transmitted good + * frames, exclusive of preamble. */ + } Tx_Frame_Count_Good_b; + }; + + union + { + __IM uint32_t Tx_Excessive_Deferral_Error; /*!< (@ 0x0000016C) Transmit Frame Count for Excessive Deferral Error + * Frames */ + + struct + { + __IM uint32_t TXEXSDEF : 16; /*!< [15..0] This field indicates the number of frames aborted because + * of excessive deferral error, that is, frames deferred for + * more than two max sized frame times. */ + uint32_t : 16; + } Tx_Excessive_Deferral_Error_b; + }; + + union + { + __IM uint32_t Tx_Pause_Frames; /*!< (@ 0x00000170) Transmit Frame Count for Good PAUSE Frames */ + + struct + { + __IM uint32_t TXPAUSE : 16; /*!< [15..0] This field indicates the number of transmitted good + * PAUSE frames. */ + uint32_t : 16; + } Tx_Pause_Frames_b; + }; + + union + { + __IM uint32_t Tx_VLAN_Frames_Good; /*!< (@ 0x00000174) Transmit Frame Count for Good VLAN Frames */ + + struct + { + __IM uint32_t TXVLANG : 32; /*!< [31..0] This register maintains the number of transmitted good + * VLAN frames, exclusive of retried frames. */ + } Tx_VLAN_Frames_Good_b; + }; + + union + { + __IM uint32_t Tx_OSize_Frames_Good; /*!< (@ 0x00000178) Transmit Frame Count for Good Oversize Frames */ + + struct + { + __IM uint32_t TXOSIZG : 16; /*!< [15..0] This field indicates the number of frames transmitted + * without errors and with length greater than the maxsize + * (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes + * if enabled in bit [27] of MAC Configuration Register (MAC_Configuration)) + */ + uint32_t : 16; + } Tx_OSize_Frames_Good_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t Rx_Frames_Count_Good_Bad; /*!< (@ 0x00000180) Receive Frame Count for Good and Bad Frames */ + + struct + { + __IM uint32_t RXFRMGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames. */ + } Rx_Frames_Count_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_Octet_Count_Good_Bad; /*!< (@ 0x00000184) Receive Octet Count for Good and Bad Frames */ + + struct + { + __IM uint32_t RXOCTGB : 32; /*!< [31..0] This field indicates the number of bytes received, exclusive + * of preamble, in good and bad frames. */ + } Rx_Octet_Count_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_Octet_Count_Good; /*!< (@ 0x00000188) Receive Octet Count for Good Frames */ + + struct + { + __IM uint32_t RXOCTG : 32; /*!< [31..0] This field indicates the number of bytes received, exclusive + * of preamble, only in good frames. */ + } Rx_Octet_Count_Good_b; + }; + + union + { + __IM uint32_t Rx_Broadcast_Frames_Good; /*!< (@ 0x0000018C) Receive Frame Count for Good Broadcast Frames */ + + struct + { + __IM uint32_t RXBCASTG : 32; /*!< [31..0] This field indicates the number of received good broadcast + * frames. */ + } Rx_Broadcast_Frames_Good_b; + }; + + union + { + __IM uint32_t Rx_Multicast_Frames_Good; /*!< (@ 0x00000190) Receive Frame Count for Good Multicast Frames */ + + struct + { + __IM uint32_t RXMCASTG : 32; /*!< [31..0] This field indicates the number of received good multicast + * frames. */ + } Rx_Multicast_Frames_Good_b; + }; + + union + { + __IM uint32_t Rx_CRC_Error_Frames; /*!< (@ 0x00000194) Receive Frame Count for CRC Error Frames */ + + struct + { + __IM uint32_t RXCRCERR : 16; /*!< [15..0] This field indicates the number of frames received with + * CRC error. */ + uint32_t : 16; + } Rx_CRC_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Alignment_Error_Frames; /*!< (@ 0x00000198) Receive Frame Count for Alignment Error Frames */ + + struct + { + __IM uint32_t RXALGNERR : 16; /*!< [15..0] This field indicates the number of frames received with + * alignment (dribble) error. This field is valid only in + * the 10 or 100 Mbps mode. */ + uint32_t : 16; + } Rx_Alignment_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Runt_Error_Frames; /*!< (@ 0x0000019C) Receive Frame Count for Runt Error Frames */ + + struct + { + __IM uint32_t RXRUNTERR : 16; /*!< [15..0] This field indicates the number of frames received with + * runt error (< 64 bytes and CRC error). */ + uint32_t : 16; + } Rx_Runt_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Jabber_Error_Frames; /*!< (@ 0x000001A0) Receive Frame Count for Jabber Error Frames */ + + struct + { + __IM uint32_t RXJABERR : 16; /*!< [15..0] This field indicates the number of giant frames received + * with length (including CRC) greater than 1,518 bytes (1,522 + * bytes for VLAN tagged) and with CRC error. If Jumbo Frame + * mode is enabled, then frames of length greater than 9,018 + * bytes (9,022 for VLAN tagged) are considered as giant frames. */ + uint32_t : 16; + } Rx_Jabber_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Undersize_Frames_Good; /*!< (@ 0x000001A4) Receive Frame Count for Undersize Frames */ + + struct + { + __IM uint32_t RXUNDERSZG : 16; /*!< [15..0] This field indicates the number of frames received with + * length less than 64 bytes and without errors. */ + uint32_t : 16; + } Rx_Undersize_Frames_Good_b; + }; + + union + { + __IM uint32_t Rx_Oversize_Frames_Good; /*!< (@ 0x000001A8) Receive Frame Count for Oversize Frames */ + + struct + { + __IM uint32_t RXOVERSZG : 16; /*!< [15..0] This field indicates the number of frames received without + * errors, with length greater than the maxsize (1,518 or + * 1,522 for VLAN tagged frames; 2,000 bytes if enabled in + * bit [27] of MAC Configuration Register (MAC_Configuration)). */ + uint32_t : 16; + } Rx_Oversize_Frames_Good_b; + }; + + union + { + __IM uint32_t Rx_64Octets_Frames_Good_Bad; /*!< (@ 0x000001AC) Receive Frame Count for Good and Bad 64 Byte + * Frames */ + + struct + { + __IM uint32_t RX64OCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames with length 64 bytes, exclusive of preamble. */ + } Rx_64Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_65To127Octets_Frames_Good_Bad; /*!< (@ 0x000001B0) Receive Frame Count for Good and Bad 65 to 127 + * Bytes Frames */ + + struct + { + __IM uint32_t RX65_127OCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames received with length between 65 and 127 (inclusive) + * bytes, exclusive of preamble. */ + } Rx_65To127Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_128To255Octets_Frames_Good_Bad; /*!< (@ 0x000001B4) Receive Frame Count for Good and Bad 128 to 255 + * Bytes Frames */ + + struct + { + __IM uint32_t RX128_255OCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames with length between 128 and 255 (inclusive) + * bytes, exclusive of preamble. */ + } Rx_128To255Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_256To511Octets_Frames_Good_Bad; /*!< (@ 0x000001B8) Receive Frame Count for Good and Bad 256 to 511 + * Bytes Frames */ + + struct + { + __IM uint32_t RX256_511OCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames with length between 256 and 511 (inclusive) + * bytes, exclusive of preamble. */ + } Rx_256To511Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_512To1023Octets_Frames_Good_Bad; /*!< (@ 0x000001BC) Receive Frame Count for Good and Bad 512 to 1,023 + * Bytes Frames */ + + struct + { + __IM uint32_t RX512_1023OCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames with length between 512 and 1,023 (inclusive) + * bytes, exclusive of preamble. */ + } Rx_512To1023Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_1024ToMaxOctets_Frames_Good_Bad; /*!< (@ 0x000001C0) Receive Frame Count for Good and Bad 1,024 to + * Maxsize Bytes Frames */ + + struct + { + __IM uint32_t RX1024_MAXOCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames with length between 1,024 and maxsize (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Rx_1024ToMaxOctets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_Unicast_Frames_Good; /*!< (@ 0x000001C4) Receive Frame Count for Good Unicast Frames */ + + struct + { + __IM uint32_t RXUCASTG : 32; /*!< [31..0] This field indicates the number of received good unicast + * frames. */ + } Rx_Unicast_Frames_Good_b; + }; + + union + { + __IM uint32_t Rx_Length_Error_Frames; /*!< (@ 0x000001C8) Receive Frame Count for Length Error Frames */ + + struct + { + __IM uint32_t RXLENERR : 16; /*!< [15..0] RXLENERR */ + uint32_t : 16; + } Rx_Length_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Out_Of_Range_Type_Frames; /*!< (@ 0x000001CC) Receive Frame Count for Out of Range Frames */ + + struct + { + __IM uint32_t RXOUTOFRNG : 16; /*!< [15..0] This field indicates the number of received frames with + * length field not equal to the valid frame size (greater + * than 1,500 but less than 1,536). */ + uint32_t : 16; + } Rx_Out_Of_Range_Type_Frames_b; + }; + + union + { + __IM uint32_t Rx_Pause_Frames; /*!< (@ 0x000001D0) Receive Frame Count for PAUSE Frames */ + + struct + { + __IM uint32_t RXPAUSEFRM : 16; /*!< [15..0] This field indicates the number of received good and + * valid PAUSE frames. */ + uint32_t : 16; + } Rx_Pause_Frames_b; + }; + + union + { + __IM uint32_t Rx_FIFO_Overflow_Frames; /*!< (@ 0x000001D4) Receive Frame Count for FIFO Overflow Frames */ + + struct + { + __IM uint32_t RXFIFOOVFL : 16; /*!< [15..0] This field indicates the number of received frames missed + * because of FIFO overflow. */ + uint32_t : 16; + } Rx_FIFO_Overflow_Frames_b; + }; + + union + { + __IM uint32_t Rx_VLAN_Frames_Good_Bad; /*!< (@ 0x000001D8) Receive Frame Count for Good and Bad VLAN Frames */ + + struct + { + __IM uint32_t RXVLANFRGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad VLAN frames. */ + } Rx_VLAN_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_Watchdog_Error_Frames; /*!< (@ 0x000001DC) Receive Frame Count for Watchdog Error Frames */ + + struct + { + __IM uint32_t RXWDGERR : 16; /*!< [15..0] This field indicates the number of frames received with + * error because of the watchdog timeout error (frames with + * more than 2,048 bytes or value programmed in Watchdog Timeout + * Register (WDog_Timeout)). */ + uint32_t : 16; + } Rx_Watchdog_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Receive_Error_Frames; /*!< (@ 0x000001E0) Receive Frame Count for Receive Error Frames */ + + struct + { + __IM uint32_t RXRCVERR : 16; /*!< [15..0] This field indicates the number of frames received with + * error because of the GMII/MII RXER error or Frame Extension + * error on GMII. */ + uint32_t : 16; + } Rx_Receive_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Control_Frames_Good; /*!< (@ 0x000001E4) Receive Frame Count for Good Control Frames */ + + struct + { + __IM uint32_t RXCTRLG : 32; /*!< [31..0] This field indicates the number of good control frames + * received. */ + } Rx_Control_Frames_Good_b; + }; + __IM uint32_t RESERVED4[134]; + + union + { + __IOM uint32_t GMACTRGSEL; /*!< (@ 0x00000400) GMAC PTP Trigger Select Register */ + + struct + { + __IOM uint32_t TRGSEL : 2; /*!< [1..0] Select PTP Timestamp Trigger for GMAC IP */ + uint32_t : 30; + } GMACTRGSEL_b; + }; + __IM uint32_t RESERVED5[63]; + + union + { + __IOM uint32_t HASH_TABLE_REG[8]; /*!< (@ 0x00000500) Hash Table Register [0..7] (n = 0 to 7) */ + + struct + { + __IOM uint32_t HT : 32; /*!< [31..0] This field contains the nth 32 bits [31:0] of the Hash + * table. */ + } HASH_TABLE_REG_b[8]; + }; + __IM uint32_t RESERVED6[26]; + + union + { + __IOM uint32_t VLAN_Hash_Table_Reg; /*!< (@ 0x00000588) VLAN Hash Table Register */ + + struct + { + __IOM uint32_t VLHT : 16; /*!< [15..0] VLAN Hash Table */ + uint32_t : 16; + } VLAN_Hash_Table_Reg_b; + }; + __IM uint32_t RESERVED7[93]; + + union + { + __IOM uint32_t Timestamp_Control; /*!< (@ 0x00000700) Timestamp Control Register */ + + struct + { + __IOM uint32_t TSENA : 1; /*!< [0..0] Timestamp Enable */ + __IOM uint32_t TSCFUPDT : 1; /*!< [1..1] Timestamp Fine or Coarse Update */ + __IOM uint32_t TSINIT : 1; /*!< [2..2] Timestamp Initialize */ + __IOM uint32_t TSUPDT : 1; /*!< [3..3] Timestamp Update */ + __IOM uint32_t TSTRIG : 1; /*!< [4..4] Timestamp Interrupt Trigger Enable */ + __IOM uint32_t TSADDREG : 1; /*!< [5..5] Addend Reg Update */ + uint32_t : 2; + __IOM uint32_t TSENALL : 1; /*!< [8..8] Enable Timestamp for all Frames */ + __IOM uint32_t TSCTRLSSR : 1; /*!< [9..9] Timestamp Digital or Binary Rollover Control */ + __IOM uint32_t TSVER2ENA : 1; /*!< [10..10] Enable PTP packet Processing for Version 2 Format */ + __IOM uint32_t TSIPENA : 1; /*!< [11..11] Enable Processing of PTP over Ethernet Frames */ + __IOM uint32_t TSIPV6ENA : 1; /*!< [12..12] Enable Processing of PTP Frames Sent Over IPv6 UDP */ + __IOM uint32_t TSIPV4ENA : 1; /*!< [13..13] Enable Processing of PTP Frames Sent over IPv4 UDP */ + __IOM uint32_t TSEVNTENA : 1; /*!< [14..14] Enable Timestamp Snapshot for Event Messages */ + __IOM uint32_t TSMSTRENA : 1; /*!< [15..15] Enable Snapshot for Messages Relevant to Master */ + __IOM uint32_t SNAPTYPSEL : 2; /*!< [17..16] Select PTP packets for Taking Snapshots */ + __IOM uint32_t TSENMACADDR : 1; /*!< [18..18] Enable MAC address for PTP Frame Filtering */ + uint32_t : 5; + __IOM uint32_t ATSFC : 1; /*!< [24..24] Auxiliary Snapshot FIFO Clear */ + __IOM uint32_t ATSEN0 : 1; /*!< [25..25] Auxiliary Snapshot 0 Enable */ + __IOM uint32_t ATSEN1 : 1; /*!< [26..26] Auxiliary Snapshot 1 Enable */ + uint32_t : 5; + } Timestamp_Control_b; + }; + + union + { + __IOM uint32_t Sub_Second_Increment; /*!< (@ 0x00000704) Sub-Second Increment Register */ + + struct + { + __IOM uint32_t SSINC : 8; /*!< [7..0] Sub-second Increment Value */ + uint32_t : 24; + } Sub_Second_Increment_b; + }; + + union + { + __IM uint32_t System_Time_Seconds; /*!< (@ 0x00000708) System Time - Seconds Register */ + + struct + { + __IM uint32_t TSS : 32; /*!< [31..0] Timestamp Second */ + } System_Time_Seconds_b; + }; + + union + { + __IM uint32_t System_Time_Nanoseconds; /*!< (@ 0x0000070C) System Time - Nanoseconds Register */ + + struct + { + __IM uint32_t TSSS : 31; /*!< [30..0] Timestamp Sub Seconds */ + uint32_t : 1; + } System_Time_Nanoseconds_b; + }; + + union + { + __IOM uint32_t System_Time_Seconds_Update; /*!< (@ 0x00000710) System Time - Seconds Update Register */ + + struct + { + __IOM uint32_t TSS : 32; /*!< [31..0] Timestamp Second */ + } System_Time_Seconds_Update_b; + }; + + union + { + __IOM uint32_t System_Time_Nanoseconds_Update; /*!< (@ 0x00000714) System Time - Nanoseconds Update Register */ + + struct + { + __IOM uint32_t TSSS : 31; /*!< [30..0] Timestamp Sub Seconds */ + __IOM uint32_t ADDSUB : 1; /*!< [31..31] Add or subtract time */ + } System_Time_Nanoseconds_Update_b; + }; + + union + { + __IOM uint32_t Timestamp_Addend; /*!< (@ 0x00000718) Timestamp Addend Register */ + + struct + { + __IOM uint32_t TSAR : 32; /*!< [31..0] Timestamp Addend */ + } Timestamp_Addend_b; + }; + + union + { + __IOM uint32_t Target_Time_Seconds; /*!< (@ 0x0000071C) Target Time Seconds Register */ + + struct + { + __IOM uint32_t TSTR : 32; /*!< [31..0] Target Time Seconds */ + } Target_Time_Seconds_b; + }; + + union + { + __IOM uint32_t Target_Time_Nanoseconds; /*!< (@ 0x00000720) Target Time Nanoseconds Register */ + + struct + { + __IOM uint32_t TTSLO : 31; /*!< [30..0] Target Timestamp Low Register */ + __IM uint32_t TRGTBUSY : 1; /*!< [31..31] Target Time Register Busy */ + } Target_Time_Nanoseconds_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IM uint32_t Timestamp_Status; /*!< (@ 0x00000728) Timestamp Status Register */ + + struct + { + uint32_t : 2; + __IM uint32_t AUXTSTRIG : 1; /*!< [2..2] Auxiliary Timestamp Trigger Snapshot */ + uint32_t : 13; + __IM uint32_t ATSSTN : 4; /*!< [19..16] Auxiliary Timestamp Snapshot Trigger Identifier */ + uint32_t : 4; + __IM uint32_t ATSSTM : 1; /*!< [24..24] Auxiliary Timestamp Snapshot Trigger Missed */ + __IM uint32_t ATSNS : 5; /*!< [29..25] Number of Auxiliary Timestamp Snapshots */ + uint32_t : 2; + } Timestamp_Status_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IM uint32_t Auxiliary_Timestamp_Nanoseconds; /*!< (@ 0x00000730) Auxiliary Timestamp - Nanoseconds Register */ + + struct + { + __IM uint32_t AUXTSLO : 31; /*!< [30..0] Contains the lower 32 bits (nanoseconds field) of the + * auxiliary timestamp. */ + uint32_t : 1; + } Auxiliary_Timestamp_Nanoseconds_b; + }; + + union + { + __IM uint32_t Auxiliary_Timestamp_Seconds; /*!< (@ 0x00000734) Auxiliary Timestamp - Seconds Register */ + + struct + { + __IM uint32_t AUXTSHI : 32; /*!< [31..0] Contains the upper 32 bits (Seconds field) of the auxiliary + * timestamp. */ + } Auxiliary_Timestamp_Seconds_b; + }; + __IM uint32_t RESERVED10[50]; + + union + { + __IOM uint32_t MAR16_H; /*!< (@ 0x00000800) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR16_H_b; + }; + + union + { + __IOM uint32_t MAR16_L; /*!< (@ 0x00000804) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR16_L_b; + }; + + union + { + __IOM uint32_t MAR17_H; /*!< (@ 0x00000808) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR17_H_b; + }; + + union + { + __IOM uint32_t MAR17_L; /*!< (@ 0x0000080C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR17_L_b; + }; + __IM uint32_t RESERVED11[508]; + + union + { + __IOM uint32_t Bus_Mode; /*!< (@ 0x00001000) Bus Mode Register */ + + struct + { + __IOM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + __IM uint32_t DA : 1; /*!< [1..1] DMA Arbitration Scheme */ + __IOM uint32_t DSL : 5; /*!< [6..2] Descriptor Skip Length */ + __IOM uint32_t ATDS : 1; /*!< [7..7] Enhanced Descriptor Size */ + __IOM uint32_t PBL : 6; /*!< [13..8] Programmable Burst Length */ + __IM uint32_t PR : 2; /*!< [15..14] Priority Ratio */ + __IOM uint32_t FB : 1; /*!< [16..16] Fixed Burst */ + __IOM uint32_t RPBL : 6; /*!< [22..17] RX DMA PBL */ + __IOM uint32_t USP : 1; /*!< [23..23] Use Separate PBL */ + __IOM uint32_t PBLx8 : 1; /*!< [24..24] PBLx8 Mode */ + __IOM uint32_t AAL : 1; /*!< [25..25] Address Aligned Beats */ + __IM uint32_t MB : 1; /*!< [26..26] Mixed Burst */ + __IM uint32_t TXPR : 1; /*!< [27..27] Transmit Priority */ + __IM uint32_t PRWG : 2; /*!< [29..28] Channel Priority Weights */ + uint32_t : 1; + __IM uint32_t RIB : 1; /*!< [31..31] Rebuild INCRx Burst */ + } Bus_Mode_b; + }; + + union + { + __IOM uint32_t Transmit_Poll_Demand; /*!< (@ 0x00001004) Transmit Poll Demand Register */ + + struct + { + __IOM uint32_t TPD : 32; /*!< [31..0] Transmit Poll Demand */ + } Transmit_Poll_Demand_b; + }; + + union + { + __IOM uint32_t Receive_Poll_Demand; /*!< (@ 0x00001008) Receive Poll Demand Register */ + + struct + { + __IOM uint32_t RPD : 32; /*!< [31..0] Receive Poll Demand */ + } Receive_Poll_Demand_b; + }; + + union + { + __IOM uint32_t Receive_Descriptor_List_Address; /*!< (@ 0x0000100C) Receive Descriptor List Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t RDESLA_32bit : 30; /*!< [31..2] Start of Receive List */ + } Receive_Descriptor_List_Address_b; + }; + + union + { + __IOM uint32_t Transmit_Descriptor_List_Address; /*!< (@ 0x00001010) Transmit Descriptor List Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t TDESLA_32bit : 30; /*!< [31..2] Start of Transmit List */ + } Transmit_Descriptor_List_Address_b; + }; + + union + { + __IOM uint32_t Status; /*!< (@ 0x00001014) Status Register */ + + struct + { + __IOM uint32_t TI : 1; /*!< [0..0] Transmit Interrupt */ + __IOM uint32_t TPS : 1; /*!< [1..1] Transmit Process Stopped */ + __IOM uint32_t TU : 1; /*!< [2..2] Transmit Buffer Unavailable */ + __IOM uint32_t TJT : 1; /*!< [3..3] Transmit Jabber Timeout */ + __IOM uint32_t OVF : 1; /*!< [4..4] Receive Overflow */ + __IOM uint32_t UNF : 1; /*!< [5..5] Transmit Underflow */ + __IOM uint32_t RI : 1; /*!< [6..6] Receive Interrupt */ + __IOM uint32_t RU : 1; /*!< [7..7] Receive Buffer Unavailable */ + __IOM uint32_t RPS : 1; /*!< [8..8] Receive Process Stopped */ + __IOM uint32_t RWT : 1; /*!< [9..9] Receive Watchdog Timeout */ + __IOM uint32_t ETI : 1; /*!< [10..10] Early Transmit Interrupt */ + uint32_t : 2; + __IOM uint32_t FBI : 1; /*!< [13..13] Fatal Bus Error Interrupt */ + __IOM uint32_t ERI : 1; /*!< [14..14] Early Receive Interrupt */ + __IOM uint32_t AIS : 1; /*!< [15..15] Abnormal Interrupt Summary */ + __IOM uint32_t NIS : 1; /*!< [16..16] Normal Interrupt Summary */ + __IM uint32_t RS : 3; /*!< [19..17] Received Process State */ + __IM uint32_t TS : 3; /*!< [22..20] Transmit Process State */ + __IM uint32_t EB : 3; /*!< [25..23] Error Bits */ + uint32_t : 1; + __IM uint32_t GMI : 1; /*!< [27..27] GMAC MMC Interrupt */ + __IM uint32_t GPI : 1; /*!< [28..28] GMAC PMT Interrupt */ + __IM uint32_t TTI : 1; /*!< [29..29] Timestamp Trigger Interrupt */ + __IM uint32_t GLPII : 1; /*!< [30..30] GMAC LPI Interrupt */ + uint32_t : 1; + } Status_b; + }; + + union + { + __IOM uint32_t Operation_Mode; /*!< (@ 0x00001018) Operation Mode Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t SR : 1; /*!< [1..1] Start or Stop Receive */ + __IOM uint32_t OSF : 1; /*!< [2..2] Operate on Second Frame */ + __IOM uint32_t RTC : 2; /*!< [4..3] Receive Threshold Control */ + __IOM uint32_t DGF : 1; /*!< [5..5] Drop Giant Frames */ + __IOM uint32_t FUF : 1; /*!< [6..6] Forward Undersized Good Frames */ + __IOM uint32_t FEF : 1; /*!< [7..7] Forward Error Frames */ + __IOM uint32_t EFC : 1; /*!< [8..8] Enable HW Flow Control */ + __IOM uint32_t RFA : 2; /*!< [10..9] Threshold for Activating Flow Control (in half-duplex + * and full-duplex) */ + __IOM uint32_t RFD : 2; /*!< [12..11] Threshold for Deactivating Flow Control (in half-duplex + * and full-duplex) */ + __IOM uint32_t ST : 1; /*!< [13..13] Start or Stop Transmission Command */ + __IOM uint32_t TTC : 3; /*!< [16..14] Transmit Threshold Control */ + uint32_t : 3; + __IOM uint32_t FTF : 1; /*!< [20..20] Flush Transmit FIFO */ + __IOM uint32_t TSF : 1; /*!< [21..21] Transmit Store and Forward */ + uint32_t : 3; + __IOM uint32_t RSF : 1; /*!< [25..25] Receive Store and Forward */ + __IOM uint32_t DT : 1; /*!< [26..26] Disable Dropping of TCP/IP Checksum Error Frames */ + uint32_t : 5; + } Operation_Mode_b; + }; + + union + { + __IOM uint32_t Interrupt_Enable; /*!< (@ 0x0000101C) Interrupt Enable Register */ + + struct + { + __IOM uint32_t TIE : 1; /*!< [0..0] Transmit Interrupt Enable */ + __IOM uint32_t TSE : 1; /*!< [1..1] Transmit Stopped Enable */ + __IOM uint32_t TUE : 1; /*!< [2..2] Transmit Buffer Unavailable Enable */ + __IOM uint32_t TJE : 1; /*!< [3..3] Transmit Jabber Timeout Enable */ + __IOM uint32_t OVE : 1; /*!< [4..4] Overflow Interrupt Enable */ + __IOM uint32_t UNE : 1; /*!< [5..5] Underflow Interrupt Enable */ + __IOM uint32_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint32_t RUE : 1; /*!< [7..7] Receive Buffer Unavailable Enable */ + __IOM uint32_t RSE : 1; /*!< [8..8] Receive Stopped Enable */ + __IOM uint32_t RWE : 1; /*!< [9..9] Receive Watchdog Timeout Enable */ + __IOM uint32_t ETE : 1; /*!< [10..10] Early Transmit Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t FBE : 1; /*!< [13..13] Fatal Bus Error Enable */ + __IOM uint32_t ERE : 1; /*!< [14..14] Early Receive Interrupt Enable */ + __IOM uint32_t AIE : 1; /*!< [15..15] Abnormal Interrupt Summary Enable */ + __IOM uint32_t NIE : 1; /*!< [16..16] Normal Interrupt Summary Enable */ + uint32_t : 15; + } Interrupt_Enable_b; + }; + + union + { + __IM uint32_t Missed_Frame_And_Buffer_Overflow_Counter; /*!< (@ 0x00001020) Missed Frame and Buffer Overflow Counter Register */ + + struct + { + __IM uint32_t MISFRMCNT : 16; /*!< [15..0] Missed Frame Counter */ + __IM uint32_t MISCNTOVF : 1; /*!< [16..16] Overflow Bit for Missed Frame Counter */ + __IM uint32_t OVFFRMCNT : 11; /*!< [27..17] Overflow Frame Counter */ + __IM uint32_t OVFCNTOVF : 1; /*!< [28..28] Overflow Bit for FIFO Overflow Counter */ + uint32_t : 3; + } Missed_Frame_And_Buffer_Overflow_Counter_b; + }; + + union + { + __IOM uint32_t Receive_Interrupt_Watchdog_Timer; /*!< (@ 0x00001024) Receive Interrupt Watchdog Timer Register */ + + struct + { + __IOM uint32_t RIWT : 8; /*!< [7..0] RI Watchdog Timer Count */ + uint32_t : 24; + } Receive_Interrupt_Watchdog_Timer_b; + }; + + union + { + __IOM uint32_t AXI_Bus_Mode; /*!< (@ 0x00001028) AXI Bus Mode Register */ + + struct + { + __IM uint32_t UNDEF : 1; /*!< [0..0] AXI Undefined Burst Length */ + __IOM uint32_t BLEN4 : 1; /*!< [1..1] AXI Burst Length 4 */ + __IOM uint32_t BLEN8 : 1; /*!< [2..2] AXI Burst Length 8 */ + __IOM uint32_t BLEN16 : 1; /*!< [3..3] AXI Burst Length 16 */ + uint32_t : 8; + __IM uint32_t AXI_AAL : 1; /*!< [12..12] Address-Aligned Beats */ + __IOM uint32_t ONEKBBE : 1; /*!< [13..13] 1 KB Boundary Crossing Enable for the GMAC-AXI Master */ + uint32_t : 2; + __IOM uint32_t RD_OSR_LMT : 2; /*!< [17..16] AXI Maximum Read OutStanding Request Limit */ + uint32_t : 2; + __IOM uint32_t WR_OSR_LMT : 2; /*!< [21..20] AXI Maximum Write OutStanding Request Limit */ + uint32_t : 8; + __IOM uint32_t LPI_XIT_FRM : 1; /*!< [30..30] Unlock on Magic Packet or Remote Wake-Up Frame */ + __IOM uint32_t EN_LPI : 1; /*!< [31..31] Enable Low Power Interface (LPI) */ + } AXI_Bus_Mode_b; + }; + + union + { + __IM uint32_t AXI_Status; /*!< (@ 0x0000102C) AXI Status Register */ + + struct + { + __IM uint32_t AXWHSTS : 1; /*!< [0..0] AXI Master Write Channel */ + __IM uint32_t AXIRDSTS : 1; /*!< [1..1] AXI Master Read Channel Status */ + uint32_t : 30; + } AXI_Status_b; + }; + __IM uint32_t RESERVED12[6]; + + union + { + __IM uint32_t Current_Host_Transmit_Descriptor; /*!< (@ 0x00001048) Current Host Transmit Descriptor Register */ + + struct + { + __IM uint32_t CURTDESAPTR : 32; /*!< [31..0] Host Transmit Descriptor Address Pointer */ + } Current_Host_Transmit_Descriptor_b; + }; + + union + { + __IM uint32_t Current_Host_Receive_Descriptor; /*!< (@ 0x0000104C) Current Host Receive Descriptor Register */ + + struct + { + __IM uint32_t CURRDESAPTR : 32; /*!< [31..0] Host Receive Descriptor Address Pointer */ + } Current_Host_Receive_Descriptor_b; + }; + + union + { + __IM uint32_t Current_Host_Transmit_Buffer_Address; /*!< (@ 0x00001050) Current Host Transmit Buffer Address Register */ + + struct + { + __IM uint32_t CURTBUFAPTR : 32; /*!< [31..0] Host Transmit Buffer Address Pointer */ + } Current_Host_Transmit_Buffer_Address_b; + }; + + union + { + __IM uint32_t Current_Host_Receive_Buffer_Address; /*!< (@ 0x00001054) Current Host Receive Buffer Address Register */ + + struct + { + __IM uint32_t CURRBUFAPTR : 32; /*!< [31..0] Host Receive Buffer Address Pointer */ + } Current_Host_Receive_Buffer_Address_b; + }; + + union + { + __IM uint32_t HW_Feature; /*!< (@ 0x00001058) HW Feature Register */ + + struct + { + __IM uint32_t MIISEL : 1; /*!< [0..0] 10 or 100 Mbps support */ + __IM uint32_t GMIISEL : 1; /*!< [1..1] 1000 Mbps support */ + __IM uint32_t HDSEL : 1; /*!< [2..2] Half-Duplex support */ + __IM uint32_t EXTHASHEN : 1; /*!< [3..3] Expanded DA Hash Filter */ + __IM uint32_t HASHSEL : 1; /*!< [4..4] HASH Filter */ + __IM uint32_t ADDMACADRSEL : 1; /*!< [5..5] Multiple MAC Address Registers */ + uint32_t : 1; + __IM uint32_t L3L4FLTREN : 1; /*!< [7..7] Layer 3 and Layer 4 Filter Feature */ + __IM uint32_t SMASEL : 1; /*!< [8..8] SMA (MDIO) Interface */ + __IM uint32_t RWKSEL : 1; /*!< [9..9] PMT Remote wakeup */ + __IM uint32_t MGKSEL : 1; /*!< [10..10] PMT Magic Packet */ + __IM uint32_t MMCSEL : 1; /*!< [11..11] RMON Module */ + __IM uint32_t TSVER1SEL : 1; /*!< [12..12] Only IEEE 1588-2002 Timestamp */ + __IM uint32_t TSVER2SEL : 1; /*!< [13..13] IEEE 1588-2008 Advanced Timestamp */ + __IM uint32_t EEESEL : 1; /*!< [14..14] Energy Efficient Ethernet */ + __IM uint32_t AVSEL : 1; /*!< [15..15] AV Feature */ + __IM uint32_t TXCOESEL : 1; /*!< [16..16] Checksum Offload in TX */ + __IM uint32_t RXTYP1COE : 1; /*!< [17..17] IP Checksum Offload (Type 1) in RX */ + __IM uint32_t RXTYP2COE : 1; /*!< [18..18] IP Checksum Offload (Type 2) in RX */ + __IM uint32_t RXFIFOSIZE : 1; /*!< [19..19] RX FIFO > 2,048 Bytes */ + __IM uint32_t RXCHCNT : 2; /*!< [21..20] Number of additional RX channels */ + __IM uint32_t TXCHCNT : 2; /*!< [23..22] Number of additional TX channels */ + __IM uint32_t ENHDESSEL : 1; /*!< [24..24] Enhanced Descriptor */ + __IM uint32_t INTTSEN : 1; /*!< [25..25] Timestamping with Internal System Time */ + __IM uint32_t FLEXIPPSEN : 1; /*!< [26..26] Flexible Pulse-Per-Second Output (GMAC: 0) */ + __IM uint32_t SAVLANINS : 1; /*!< [27..27] Source Address or VLAN Insertion */ + __IM uint32_t ACTPHYIF : 3; /*!< [30..28] Active or Selected PHY interface */ + uint32_t : 1; + } HW_Feature_b; + }; +} R_GMAC_Type; /*!< Size = 4188 (0x105c) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHSS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet Subsystem (R_ETHSS) + */ + +typedef struct /*!< (@ 0x80110000) R_ETHSS Structure */ +{ + __IOM uint32_t PRCMD; /*!< (@ 0x00000000) Ethernet Protect Register */ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t MODCTRL; /*!< (@ 0x00000008) Mode Control Register */ + + struct + { + __IOM uint32_t SW_MODE : 1; /*!< [0..0] Media I/F connectionSW_MODEMedia I/FPort 0Port 1Port + * 20ESC Port 0ESC Port 1GMAC Port1ESC Port 0ESC Port 1ESC + * Port 2 */ + uint32_t : 31; + } MODCTRL_b; + }; + + union + { + __IOM uint32_t PTPMCTRL; /*!< (@ 0x0000000C) PTP Mode Control Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t PTP_PLS_RSTn : 1; /*!< [16..16] Reset control for Pulse Generator (unit 0 - 3) */ + uint32_t : 15; + } PTPMCTRL_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t PHYLNK; /*!< (@ 0x00000014) Ethernet PHY Link Mode Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t CATLNK : 3; /*!< [6..4] Specify the active level of the ESC_PHYLINKn signal using + * the EtherCAT interface */ + uint32_t : 25; + } PHYLNK_b; + }; + __IM uint32_t RESERVED2[58]; + + union + { + __IOM uint32_t CONVCTRL[3]; /*!< (@ 0x00000100) RGMII/RMII Converter [0..2] Control Register */ + + struct + { + __IOM uint32_t CONV_MODE : 5; /*!< [4..0] Converter operation mode */ + uint32_t : 3; + __IOM uint32_t FULLD : 1; /*!< [8..8] FULLD */ + __IOM uint32_t RMII_RX_ER_EN : 1; /*!< [9..9] RMII_RX_ER_EN */ + __IOM uint32_t RMII_CRS_MODE : 1; /*!< [10..10] RMII_CRS_MODE */ + uint32_t : 1; + __IM uint32_t RGMII_LINK : 1; /*!< [12..12] RGMII_LINK */ + __IM uint32_t RGMII_DUPLEX : 1; /*!< [13..13] RGMII_DUPLEX */ + __IM uint32_t RGMII_SPEED : 2; /*!< [15..14] RGMII_SPEED */ + uint32_t : 16; + } CONVCTRL_b[3]; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t CONVRST; /*!< (@ 0x00000114) RGMII/RMII Converter Reset Control Register */ + + struct + { + __IOM uint32_t PHYIR : 3; /*!< [2..0] PHYIR */ + uint32_t : 29; + } CONVRST_b; + }; +} R_ETHSS_Type; /*!< Size = 280 (0x118) */ + +/* =========================================================================================================================== */ +/* ================ R_ESC_INI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Initial Configuration 1 for EtherCAT Slave Controller (R_ESC_INI) + */ + +typedef struct /*!< (@ 0x80110200) R_ESC_INI Structure */ +{ + union + { + __IOM uint32_t ECATOFFADR; /*!< (@ 0x00000000) EtherCAT PHY Offset Address Setting Register */ + + struct + { + __IOM uint32_t OADD : 5; /*!< [4..0] PHY Offset Address Setting */ + uint32_t : 27; + } ECATOFFADR_b; + }; + + union + { + __IOM uint32_t ECATOPMOD; /*!< (@ 0x00000004) EtherCAT Operation Mode Register */ + + struct + { + __IOM uint32_t EEPROMSIZE : 1; /*!< [0..0] EEPROM Memory Size Specification */ + uint32_t : 31; + } ECATOPMOD_b; + }; + + union + { + __IOM uint32_t ECATDBGC; /*!< (@ 0x00000008) EtherCAT Debug Control Register */ + + struct + { + __IOM uint32_t TXSFT0 : 2; /*!< [1..0] Set the delay time for ETH0_TXC of the EtherCAT */ + __IOM uint32_t TXSFT1 : 2; /*!< [3..2] Set the delay time for ETH1_TXC of the EtherCAT */ + __IOM uint32_t TXSFT2 : 2; /*!< [5..4] Set the delay time for ETH2_TXC of the EtherCAT */ + uint32_t : 26; + } ECATDBGC_b; + }; + + union + { + __IOM uint32_t ECATTRGSEL; /*!< (@ 0x0000000C) EtherCAT DC Latch Trigger Select Register */ + + struct + { + __IOM uint32_t TRGSEL0 : 1; /*!< [0..0] Select DC Latch Trigger 0 for ESC */ + __IOM uint32_t TRGSEL1 : 1; /*!< [1..1] Select DC Latch Trigger 1 for ESC */ + uint32_t : 30; + } ECATTRGSEL_b; + }; +} R_ESC_INI_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_GMAC_PTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GMAC for PTP (R_GMAC_PTP) + */ + +typedef struct /*!< (@ 0x80110400) R_GMAC_PTP Structure */ +{ + __IM uint32_t RESERVED[256]; + __IOM R_GMAC_PTP_SWTM_Type SWTM[4]; /*!< (@ 0x00000400) GMAC Switch Timer output pins 0-3 Registers */ +} R_GMAC_PTP_Type; /*!< Size = 2048 (0x800) */ + +/* =========================================================================================================================== */ +/* ================ R_ESC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief EtherCAT Slave Controller (R_ESC) + */ + +typedef struct /*!< (@ 0x80130000) R_ESC Structure */ +{ + union + { + __IM uint8_t TYPE; /*!< (@ 0x00000000) Type Register */ + + struct + { + __IM uint8_t TYPE : 8; /*!< [7..0] Type of the EtherCAT slave controller */ + } TYPE_b; + }; + + union + { + __IM uint8_t REVISION; /*!< (@ 0x00000001) Revision Register */ + + struct + { + __IM uint8_t REV : 8; /*!< [7..0] Revision of the EtherCAT slave controller */ + } REVISION_b; + }; + + union + { + __IM uint8_t BUILD; /*!< (@ 0x00000002) Build Register */ + + struct + { + __IM uint8_t BUILD : 8; /*!< [7..0] Build number of the EtherCAT slave controller */ + } BUILD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IM uint8_t FMMU_NUM; /*!< (@ 0x00000004) FMMU Supported Register */ + + struct + { + __IM uint8_t NUMFMMU : 8; /*!< [7..0] Number of FMMU channels supported in the EtherCAT slave + * controller */ + } FMMU_NUM_b; + }; + + union + { + __IM uint8_t SYNC_MANAGER; /*!< (@ 0x00000005) SyncManager Supported Register */ + + struct + { + __IM uint8_t NUMSYNC : 8; /*!< [7..0] Number of SyncManager channels supported in the EtherCAT + * slave controller */ + } SYNC_MANAGER_b; + }; + + union + { + __IM uint8_t RAM_SIZE; /*!< (@ 0x00000006) RAM Size Register */ + + struct + { + __IM uint8_t RAMSIZE : 8; /*!< [7..0] Process data RAM size supported in the EtherCAT slave + * controller (unit: KB) */ + } RAM_SIZE_b; + }; + + union + { + __IM uint8_t PORT_DESC; /*!< (@ 0x00000007) Port Descriptor Register */ + + struct + { + __IM uint8_t P0 : 2; /*!< [1..0] Port 0 configuration */ + __IM uint8_t P1 : 2; /*!< [3..2] Port 1 configuration */ + __IM uint8_t P2 : 2; /*!< [5..4] Port 2 configuration */ + __IM uint8_t P3 : 2; /*!< [7..6] Port 3 configuration */ + } PORT_DESC_b; + }; + + union + { + __IM uint16_t FEATURE; /*!< (@ 0x00000008) ESC Features Supported Register */ + + struct + { + __IM uint16_t FMMU : 1; /*!< [0..0] FMMU Operation */ + uint16_t : 1; + __IM uint16_t DC : 1; /*!< [2..2] Distributed Clock */ + __IM uint16_t DCWID : 1; /*!< [3..3] Distributed Clock Width */ + uint16_t : 2; + __IM uint16_t LINKDECMII : 1; /*!< [6..6] Enhanced Link Detection in MII */ + __IM uint16_t FCS : 1; /*!< [7..7] Separate handling of FCS errors */ + __IM uint16_t DCSYNC : 1; /*!< [8..8] Enhanced DC SYNC activation */ + __IM uint16_t LRW : 1; /*!< [9..9] EtherCAT LRW command support */ + __IM uint16_t RWSUPP : 1; /*!< [10..10] EtherCAT read/write command support (BRW, APRW, FPRW) */ + __IM uint16_t FSCONFIG : 1; /*!< [11..11] Fixed FMMU/SyncManager configuration */ + uint16_t : 4; + } FEATURE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IM uint16_t STATION_ADR; /*!< (@ 0x00000010) Configured Station Address Register */ + + struct + { + __IM uint16_t NODADDR : 16; /*!< [15..0] Node Addressing Address Indication */ + } STATION_ADR_b; + }; + + union + { + __IOM uint16_t STATION_ALIAS; /*!< (@ 0x00000012) Configured Station Alias Register */ + + struct + { + __IOM uint16_t NODALIADDR : 16; /*!< [15..0] Alias Address Indication */ + } STATION_ALIAS_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IM uint8_t WR_REG_ENABLE; /*!< (@ 0x00000020) Write Register Enable Register */ + + struct + { + __IM uint8_t ENABLE : 1; /*!< [0..0] Register Write Protection Unlock */ + uint8_t : 7; + } WR_REG_ENABLE_b; + }; + + union + { + __IM uint8_t WR_REG_PROTECT; /*!< (@ 0x00000021) Write Register Protection Register */ + + struct + { + __IM uint8_t PROTECT : 1; /*!< [0..0] Register Write Protection Specification */ + uint8_t : 7; + } WR_REG_PROTECT_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IM uint8_t ESC_WR_ENABLE; /*!< (@ 0x00000030) ESC Write Enable Register */ + + struct + { + __IM uint8_t ENABLE : 1; /*!< [0..0] Register/Memory Write Protection Unlock */ + uint8_t : 7; + } ESC_WR_ENABLE_b; + }; + + union + { + __IM uint8_t ESC_WR_PROTECT; /*!< (@ 0x00000031) ESC Write Protection Register */ + + struct + { + __IM uint8_t PROTECT : 1; /*!< [0..0] Register/Memory Write Protection Specification */ + uint8_t : 7; + } ESC_WR_PROTECT_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + union + { + __IM uint8_t ESC_RESET_ECAT_R; /*!< (@ 0x00000040) ESC Reset ECAT Register for read */ + + struct + { + __IM uint8_t RESET_ECAT : 2; /*!< [1..0] Reset Progress Status */ + uint8_t : 6; + } ESC_RESET_ECAT_R_b; + }; + + union + { + __IM uint8_t ESC_RESET_ECAT_W; /*!< (@ 0x00000040) ESC Reset ECAT Register for write */ + + struct + { + __IM uint8_t RESET_ECAT : 8; /*!< [7..0] Software Reset Setting */ + } ESC_RESET_ECAT_W_b; + }; + }; + + union + { + union + { + __IOM uint8_t ESC_RESET_PDI_R; /*!< (@ 0x00000041) ESC Reset PDI Register for read */ + + struct + { + __IOM uint8_t RESET_PDI : 2; /*!< [1..0] Reset Progress Status */ + uint8_t : 6; + } ESC_RESET_PDI_R_b; + }; + + union + { + __IOM uint8_t ESC_RESET_PDI_W; /*!< (@ 0x00000041) ESC Reset PDI Register for write */ + + struct + { + __IOM uint8_t RESET_PDI : 8; /*!< [7..0] Software Reset Setting */ + } ESC_RESET_PDI_W_b; + }; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[47]; + + union + { + __IM uint32_t ESC_DL_CONTROL; /*!< (@ 0x00000100) ESC DL Control Register */ + + struct + { + __IM uint32_t FWDRULE : 1; /*!< [0..0] Forwarding Rule */ + __IM uint32_t TEMPUSE : 1; /*!< [1..1] Temporary Use of Bits 15 to 8 Settings */ + uint32_t : 6; + __IM uint32_t LP0 : 2; /*!< [9..8] Loop Port 0 Configuration */ + __IM uint32_t LP1 : 2; /*!< [11..10] Loop Port 1 Configuration */ + __IM uint32_t LP2 : 2; /*!< [13..12] Loop Port 2 Configuration */ + __IM uint32_t LP3 : 2; /*!< [15..14] Loop Port 3 Configuration */ + __IM uint32_t RXFIFO : 3; /*!< [18..16] RX FIFO Size */ + uint32_t : 5; + __IM uint32_t STAALIAS : 1; /*!< [24..24] Station Alias Status */ + uint32_t : 7; + } ESC_DL_CONTROL_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IM uint16_t PHYSICAL_RW_OFFSET; /*!< (@ 0x00000108) Physical Read/Write Offset Register */ + + struct + { + __IM uint16_t RWOFFSET : 16; /*!< [15..0] Offset between Read and Write Addresses */ + } PHYSICAL_RW_OFFSET_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12; + + union + { + __IM uint16_t ESC_DL_STATUS; /*!< (@ 0x00000110) ESC DL Status Register */ + + struct + { + __IM uint16_t PDIOPE : 1; /*!< [0..0] PDI/EEPROM Load State Indication */ + __IM uint16_t PDIWDST : 1; /*!< [1..1] PDI Watchdog Timer Status */ + __IM uint16_t ENHLINKD : 1; /*!< [2..2] Enhanced Link Detection Indication */ + uint16_t : 1; + __IM uint16_t PHYP0 : 1; /*!< [4..4] Port 0 Link State Indication */ + __IM uint16_t PHYP1 : 1; /*!< [5..5] Port 1 Link State Indication */ + __IM uint16_t PHYP2 : 1; /*!< [6..6] Port 2 Link State Indication */ + __IM uint16_t PHYP3 : 1; /*!< [7..7] Port 3 Link State Indication */ + __IM uint16_t LP0 : 1; /*!< [8..8] Loop Port 0 State Indication */ + __IM uint16_t COMP0 : 1; /*!< [9..9] Port 0 Communication State Indication */ + __IM uint16_t LP1 : 1; /*!< [10..10] Loop Port 1 State Indication */ + __IM uint16_t COMP1 : 1; /*!< [11..11] Port 1 Communication State Indication */ + __IM uint16_t LP2 : 1; /*!< [12..12] Loop Port 2 State Indication */ + __IM uint16_t COMP2 : 1; /*!< [13..13] Port 2 Communication State Indication */ + __IM uint16_t LP3 : 1; /*!< [14..14] Loop Port 3 State Indication */ + __IM uint16_t COMP3 : 1; /*!< [15..15] Port 3 Communication State Indication */ + } ESC_DL_STATUS_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + + union + { + __IM uint16_t AL_CONTROL; /*!< (@ 0x00000120) AL Control Register */ + + struct + { + __IM uint16_t INISTATE : 4; /*!< [3..0] Change the state transition of the device state machine. */ + __IM uint16_t ERRINDACK : 1; /*!< [4..4] Error Indication Acknowledge (Response) */ + __IM uint16_t DEVICEID : 1; /*!< [5..5] Device ID Request */ + uint16_t : 10; + } AL_CONTROL_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint16_t AL_STATUS; /*!< (@ 0x00000130) AL Status Register */ + + struct + { + __IOM uint16_t ACTSTATE : 4; /*!< [3..0] State Machine State Indication */ + __IOM uint16_t ERR : 1; /*!< [4..4] Error State Indication */ + __IOM uint16_t DEVICEID : 1; /*!< [5..5] Device ID Load State Indication */ + uint16_t : 10; + } AL_STATUS_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t AL_STATUS_CODE; /*!< (@ 0x00000134) AL Status Code Register */ + + struct + { + __IOM uint16_t STATUSCODE : 16; /*!< [15..0] AL status code */ + } AL_STATUS_CODE_b; + }; + __IM uint16_t RESERVED18; + + union + { + __IOM uint8_t RUN_LED_OVERRIDE; /*!< (@ 0x00000138) RUN LED Override Register */ + + struct + { + __IOM uint8_t LEDCODE : 4; /*!< [3..0] LED Code Indication (FSM state: Bits [3:0] of the AL + * Status register, AL_STATUS) */ + __IOM uint8_t OVERRIDEEN : 1; /*!< [4..4] Override Setting */ + uint8_t : 3; + } RUN_LED_OVERRIDE_b; + }; + + union + { + __IOM uint8_t ERR_LED_OVERRIDE; /*!< (@ 0x00000139) ERR LED Override Register */ + + struct + { + __IOM uint8_t LEDCODE : 4; /*!< [3..0] LED Code Indication */ + __IOM uint8_t OVERRIDEEN : 1; /*!< [4..4] Override Setting */ + uint8_t : 3; + } ERR_LED_OVERRIDE_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20; + + union + { + __IM uint8_t PDI_CONTROL; /*!< (@ 0x00000140) PDI Control Register */ + + struct + { + __IM uint8_t PDI : 8; /*!< [7..0] Process Data Interface. In this LSI, the following value + * is indicated. */ + } PDI_CONTROL_b; + }; + + union + { + __IM uint8_t ESC_CONFIG; /*!< (@ 0x00000141) ESC Configuration Register */ + + struct + { + __IM uint8_t DEVEMU : 1; /*!< [0..0] Device emulation (control of AL status) */ + __IM uint8_t ENLALLP : 1; /*!< [1..1] Sets enhanced link detection for all ports */ + __IM uint8_t DCSYNC : 1; /*!< [2..2] Sets the SYNC output unit for distributed clocks (fixed + * to 1 in this LSI) */ + __IM uint8_t DCLATCH : 1; /*!< [3..3] Sets the latch input unit for distributed clocks */ + __IM uint8_t ENLP0 : 1; /*!< [4..4] Port 0 Enhanced Link Detection Setting */ + __IM uint8_t ENLP1 : 1; /*!< [5..5] Port 1 Enhanced Link Detection Setting */ + __IM uint8_t ENLP2 : 1; /*!< [6..6] Port 2 Enhanced Link Detection Setting */ + __IM uint8_t ENLP3 : 1; /*!< [7..7] Port 3 Enhanced Link Detection Setting */ + } ESC_CONFIG_b; + }; + __IM uint16_t RESERVED21; + __IM uint32_t RESERVED22[3]; + + union + { + __IM uint8_t PDI_CONFIG; /*!< (@ 0x00000150) PDI Configuration Register */ + + struct + { + __IM uint8_t ONCHIPBUSCLK : 5; /*!< [4..0] On-Chip Bus Clock Indication */ + __IM uint8_t ONCHIPBUS : 3; /*!< [7..5] On-Chip Bus Type Indication */ + } PDI_CONFIG_b; + }; + + union + { + __IM uint8_t SYNC_LATCH_CONFIG; /*!< (@ 0x00000151) SYNC/LATCH PDI Configuration Register */ + + struct + { + __IM uint8_t SYNC0OUT : 2; /*!< [1..0] SYNC0 Output Driver and Polarity Indication */ + __IM uint8_t SYNCLAT0 : 1; /*!< [2..2] SYNC0/LATCH0 Indication */ + __IM uint8_t SYNC0MAP : 1; /*!< [3..3] SYNC0 State Mapping Indication */ + __IM uint8_t SYNC1OUT : 2; /*!< [5..4] SYNC1 Output Driver and Polarity Indication */ + __IM uint8_t SYNCLAT1 : 1; /*!< [6..6] SYNC1/LATCH1 Indication */ + __IM uint8_t SYNC1MAP : 1; /*!< [7..7] SYNC1 State Mapping Indication */ + } SYNC_LATCH_CONFIG_b; + }; + + union + { + __IM uint16_t EXT_PDI_CONFIG; /*!< (@ 0x00000152) Extended PDI Configuration Register */ + + struct + { + __IM uint16_t DATABUSWID : 2; /*!< [1..0] PDI Data Bus Width Indication */ + uint16_t : 14; + } EXT_PDI_CONFIG_b; + }; + __IM uint32_t RESERVED23[43]; + + union + { + __IM uint16_t ECAT_EVENT_MASK; /*!< (@ 0x00000200) ECAT Event Mask Register */ + + struct + { + __IM uint16_t ECATEVMASK : 16; /*!< [15..0] Event Request Mask Setting */ + } ECAT_EVENT_MASK_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint32_t AL_EVENT_MASK; /*!< (@ 0x00000204) AL Event Mask Register */ + + struct + { + __IOM uint32_t ALEVMASK : 32; /*!< [31..0] Event Request Mask Setting */ + } AL_EVENT_MASK_b; + }; + __IM uint32_t RESERVED25[2]; + + union + { + __IM uint16_t ECAT_EVENT_REQ; /*!< (@ 0x00000210) ECAT Event Request Register */ + + struct + { + __IM uint16_t DCLATCH : 1; /*!< [0..0] DC Latch Event State Indication */ + uint16_t : 1; + __IM uint16_t DLSTA : 1; /*!< [2..2] DL Status Event State Indication */ + __IM uint16_t ALSTA : 1; /*!< [3..3] AL Status Event State Indication */ + __IM uint16_t SMSTA0 : 1; /*!< [4..4] Mirror value of SyncManager 0 Status Indication */ + __IM uint16_t SMSTA1 : 1; /*!< [5..5] Mirror value of SyncManager 1 Status Indication */ + __IM uint16_t SMSTA2 : 1; /*!< [6..6] Mirror value of SyncManager 2 Status Indication */ + __IM uint16_t SMSTA3 : 1; /*!< [7..7] Mirror value of SyncManager 3 Status Indication */ + __IM uint16_t SMSTA4 : 1; /*!< [8..8] Mirror value of SyncManager 4 Status Indication */ + __IM uint16_t SMSTA5 : 1; /*!< [9..9] Mirror value of SyncManager 5 Status Indication */ + __IM uint16_t SMSTA6 : 1; /*!< [10..10] Mirror value of SyncManager 6 Status Indication */ + __IM uint16_t SMSTA7 : 1; /*!< [11..11] Mirror value of SyncManager 7 Status Indication */ + uint16_t : 4; + } ECAT_EVENT_REQ_b; + }; + __IM uint16_t RESERVED26; + __IM uint32_t RESERVED27[3]; + + union + { + __IM uint32_t AL_EVENT_REQ; /*!< (@ 0x00000220) AL Event Request Register */ + + struct + { + __IM uint32_t ALCTRL : 1; /*!< [0..0] AL Control Event State Indication */ + __IM uint32_t DCLATCH : 1; /*!< [1..1] DC Latch Event State Indication */ + __IM uint32_t DCSYNC0STA : 1; /*!< [2..2] DC SYNC0 State Indication */ + __IM uint32_t DCSYNC1STA : 1; /*!< [3..3] DC SYNC1 State Indication */ + __IM uint32_t SYNCACT : 1; /*!< [4..4] SyncManager Activation Indication */ + uint32_t : 1; + __IM uint32_t WDPD : 1; /*!< [6..6] Watchdog Process Data Indication */ + uint32_t : 1; + __IM uint32_t SMINT0 : 1; /*!< [8..8] SyncManager 0 interrupt (bit 0 or 1 of the SyncManager + * status register (0x0805)) */ + __IM uint32_t SMINT1 : 1; /*!< [9..9] SyncManager 1 interrupt (bit 0 or 1 of the SyncManager + * status register (0x080D)) */ + __IM uint32_t SMINT2 : 1; /*!< [10..10] SyncManager 2 interrupt (bit 0 or 1 of the SyncManager + * status register (0x0815)) */ + __IM uint32_t SMINT3 : 1; /*!< [11..11] SyncManager 3 interrupt (bit 0 or 1 of the SyncManager + * status register (0x081D)) */ + __IM uint32_t SMINT4 : 1; /*!< [12..12] SyncManager 4 interrupt (bit 0 or 1 of the SyncManager + * status register (0x0825)) */ + __IM uint32_t SMINT5 : 1; /*!< [13..13] SyncManager 5 interrupt (bit 0 or 1 of the SyncManager + * status register (0x082D)) */ + __IM uint32_t SMINT6 : 1; /*!< [14..14] SyncManager 6 interrupt (bit 0 or 1 of the SyncManager + * status register (0x0835)) */ + __IM uint32_t SMINT7 : 1; /*!< [15..15] SyncManager 7 interrupt (bit 0 or 1 of the SyncManager + * status register (0x083D)) */ + uint32_t : 16; + } AL_EVENT_REQ_b; + }; + __IM uint32_t RESERVED28[55]; + + union + { + __IM uint16_t RX_ERR_COUNT[3]; /*!< (@ 0x00000300) RX Error Counter [0..2] Register (n = 0 to 2) */ + + struct + { + __IM uint16_t INVFRMCNT : 8; /*!< [7..0] Invalid Frame Counter Value Indication */ + __IM uint16_t RXERRCNT : 8; /*!< [15..8] RX Frame Error Counter Value Indication */ + } RX_ERR_COUNT_b[3]; + }; + __IM uint16_t RESERVED29; + + union + { + __IM uint8_t FWD_RX_ERR_COUNT[3]; /*!< (@ 0x00000308) Forwarded RX Error Counter [0..2] Register (n + * = 0 to 2) */ + + struct + { + __IM uint8_t FWDERRCNT : 8; /*!< [7..0] Forwarded Error Counter Value Indication */ + } FWD_RX_ERR_COUNT_b[3]; + }; + __IM uint8_t RESERVED30; + + union + { + __IM uint8_t ECAT_PROC_ERR_COUNT; /*!< (@ 0x0000030C) ECAT Processing Unit Error Counter Register */ + + struct + { + __IM uint8_t EPUERRCNT : 8; /*!< [7..0] Processing Unit Error Counter Value Indication */ + } ECAT_PROC_ERR_COUNT_b; + }; + + union + { + __IM uint8_t PDI_ERR_COUNT; /*!< (@ 0x0000030D) PDI Error Counter Register */ + + struct + { + __IM uint8_t PDIERRCNT : 8; /*!< [7..0] PDI Error Counter Value Indication */ + } PDI_ERR_COUNT_b; + }; + __IM uint16_t RESERVED31; + + union + { + __IM uint8_t LOST_LINK_COUNT[3]; /*!< (@ 0x00000310) Lost Link Counter [0..2] Register (n = 0 to 2) */ + + struct + { + __IM uint8_t LOSTLINKCNT : 8; /*!< [7..0] Lost Link Counter Value Indication */ + } LOST_LINK_COUNT_b[3]; + }; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[59]; + + union + { + __IM uint16_t WD_DIVIDE; /*!< (@ 0x00000400) Watchdog Divider Register */ + + struct + { + __IM uint16_t WDDIV : 16; /*!< [15..0] Watchdog Clock Frequency Divisor Setting */ + } WD_DIVIDE_b; + }; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; + + union + { + __IM uint16_t WDT_PDI; /*!< (@ 0x00000410) Watchdog Time PDI Register */ + + struct + { + __IM uint16_t WDTIMPDI : 16; /*!< [15..0] Watchdog Overflow Time Setting */ + } WDT_PDI_b; + }; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; + + union + { + __IM uint16_t WDT_DATA; /*!< (@ 0x00000420) Watchdog Time Process Data Register */ + + struct + { + __IM uint16_t WDTIMPD : 16; /*!< [15..0] Watchdog Overflow Time Setting */ + } WDT_DATA_b; + }; + __IM uint16_t RESERVED38; + __IM uint32_t RESERVED39[7]; + + union + { + __IM uint16_t WDS_DATA; /*!< (@ 0x00000440) Watchdog Status Process Data Register */ + + struct + { + __IM uint16_t WDSTAPD : 1; /*!< [0..0] Watchdog State Indication */ + uint16_t : 15; + } WDS_DATA_b; + }; + + union + { + __IM uint8_t WDC_DATA; /*!< (@ 0x00000442) Watchdog Counter Process Data Register */ + + struct + { + __IM uint8_t WDCNTPD : 8; /*!< [7..0] Watchdog Counter Value Indication */ + } WDC_DATA_b; + }; + + union + { + __IM uint8_t WDC_PDI; /*!< (@ 0x00000443) Watchdog Counter PDI Register */ + + struct + { + __IM uint8_t WDCNTPDI : 8; /*!< [7..0] Watchdog Counter Value Indication */ + } WDC_PDI_b; + }; + __IM uint32_t RESERVED40[47]; + + union + { + __IM uint8_t EEP_CONF; /*!< (@ 0x00000500) EEPROM Configuration Register */ + + struct + { + __IM uint8_t CTRLPDI : 1; /*!< [0..0] PDI EEPROM Control */ + __IM uint8_t FORCEECAT : 1; /*!< [1..1] EEPROM Access Right Change */ + uint8_t : 6; + } EEP_CONF_b; + }; + + union + { + __IOM uint8_t EEP_STATE; /*!< (@ 0x00000501) EEPROM PDI Access State Register */ + + struct + { + __IOM uint8_t PDIACCESS : 1; /*!< [0..0] EEPROM Access Right Setting */ + uint8_t : 7; + } EEP_STATE_b; + }; + + union + { + __IOM uint16_t EEP_CONT_STAT; /*!< (@ 0x00000502) EEPROM Control/Status Register */ + + struct + { + __IM uint16_t ECATWREN : 1; /*!< [0..0] ECAT Write Enable */ + uint16_t : 5; + __IM uint16_t READBYTE : 1; /*!< [6..6] EEPROM Read Byte Indication */ + __IM uint16_t PROMSIZE : 1; /*!< [7..7] EEPROM Algorithm Indication */ + __IOM uint16_t COMMAND : 3; /*!< [10..8] Command */ + __IM uint16_t CKSUMERR : 1; /*!< [11..11] Checksum Error Indication */ + __IM uint16_t LOADSTA : 1; /*!< [12..12] EEPROM Loading Status Indication */ + __IM uint16_t ACKCMDERR : 1; /*!< [13..13] Acknowledge/Command Error Indication */ + __IM uint16_t WRENERR : 1; /*!< [14..14] Write Enable Error Indication */ + __IM uint16_t BUSY : 1; /*!< [15..15] EEPROM Interface State Indication */ + } EEP_CONT_STAT_b; + }; + + union + { + __IOM uint32_t EEP_ADR; /*!< (@ 0x00000504) EEPROM Address Register */ + + struct + { + __IOM uint32_t ADDRESS : 32; /*!< [31..0] EEPROM Address Setting */ + } EEP_ADR_b; + }; + + union + { + __IOM uint32_t EEP_DATA; /*!< (@ 0x00000508) EEPROM Data Register */ + + struct + { + __IOM uint32_t LODATA : 16; /*!< [15..0] Data to be written to the EEPROM or data read from the + * EEPROM (lower 2 bytes) */ + __IM uint32_t HIDATA : 16; /*!< [31..16] Data read from the EEPROM (upper 2 bytes) */ + } EEP_DATA_b; + }; + __IM uint32_t RESERVED41; + + union + { + __IOM uint16_t MII_CONT_STAT; /*!< (@ 0x00000510) MII Management Control/Status Register */ + + struct + { + __IM uint16_t WREN : 1; /*!< [0..0] Write Enable */ + __IM uint16_t PDICTRL : 1; /*!< [1..1] PDI Control Indication */ + __IM uint16_t MILINK : 1; /*!< [2..2] MI Link Detection */ + __IM uint16_t PHYOFFSET : 5; /*!< [7..3] PHY Address Offset Indication */ + __IOM uint16_t COMMAND : 2; /*!< [9..8] Command */ + uint16_t : 3; + __IOM uint16_t READERR : 1; /*!< [13..13] Read Error Indication */ + __IM uint16_t CMDERR : 1; /*!< [14..14] Command Error Indication */ + __IM uint16_t BUSY : 1; /*!< [15..15] MII Management State Indication */ + } MII_CONT_STAT_b; + }; + + union + { + __IOM uint8_t PHY_ADR; /*!< (@ 0x00000512) PHY Address Register */ + + struct + { + __IOM uint8_t PHYADDR : 5; /*!< [4..0] PHY Address Setting */ + uint8_t : 3; + } PHY_ADR_b; + }; + + union + { + __IOM uint8_t PHY_REG_ADR; /*!< (@ 0x00000513) PHY Register Address Register */ + + struct + { + __IOM uint8_t PHYREGADDR : 5; /*!< [4..0] Address of PHY register */ + uint8_t : 3; + } PHY_REG_ADR_b; + }; + + union + { + __IOM uint16_t PHY_DATA; /*!< (@ 0x00000514) PHY Data Register */ + + struct + { + __IOM uint16_t PHYREGDATA : 16; /*!< [15..0] PHY Register Data Indication/Setting */ + } PHY_DATA_b; + }; + + union + { + __IM uint8_t MII_ECAT_ACS_STAT; /*!< (@ 0x00000516) MII Management ECAT Access State Register */ + + struct + { + __IM uint8_t ACSMII : 1; /*!< [0..0] MII Management Interface Access Right Setting */ + uint8_t : 7; + } MII_ECAT_ACS_STAT_b; + }; + + union + { + __IOM uint8_t MII_PDI_ACS_STAT; /*!< (@ 0x00000517) MII Management PDI Access State Register */ + + struct + { + __IOM uint8_t ACSMII : 1; /*!< [0..0] Right of access to the MII management interface */ + __IM uint8_t FORPDI : 1; /*!< [1..1] Forced change of access by the PDI (forced change of + * bit 0) */ + uint8_t : 6; + } MII_PDI_ACS_STAT_b; + }; + __IM uint32_t RESERVED42[58]; + __IOM R_ESC_FMMU_Type FMMU[8]; /*!< (@ 0x00000600) FMMU [0..7] Registers (n = 0 to 7) */ + __IM uint32_t RESERVED43[96]; + __IOM R_ESC_SM_Type SM[8]; /*!< (@ 0x00000800) SyncManager [0..7] Registers (n = 0 to 7) */ + __IM uint32_t RESERVED44[48]; + + union + { + __IM uint32_t DC_RCV_TIME_PORT[3]; /*!< (@ 0x00000900) Receive Time Port [0..2] Register */ + + struct + { + __IM uint32_t RCVTIME0 : 32; /*!< [31..0] Receive Time Indication/Latch */ + } DC_RCV_TIME_PORT_b[3]; + }; + __IM uint32_t RESERVED45; + __IM uint32_t DC_SYS_TIME_L; /*!< (@ 0x00000910) System Time Register L */ + __IM uint32_t DC_SYS_TIME_H; /*!< (@ 0x00000914) System Time Register H */ + __IM uint32_t DC_RCV_TIME_UNIT_L; /*!< (@ 0x00000918) Receive Time ECAT Processing Unit Register L */ + __IM uint32_t DC_RCV_TIME_UNIT_H; /*!< (@ 0x0000091C) Receive Time ECAT Processing Unit Register H */ + __IM uint32_t DC_SYS_TIME_OFFSET_L; /*!< (@ 0x00000920) System Time Offset Register L */ + __IM uint32_t DC_SYS_TIME_OFFSET_H; /*!< (@ 0x00000924) System Time Offset Register H */ + + union + { + __IM uint32_t DC_SYS_TIME_DELAY; /*!< (@ 0x00000928) System Time Delay Register */ + + struct + { + __IM uint32_t SYSTIMDLY : 32; /*!< [31..0] Propagation Delay Indication */ + } DC_SYS_TIME_DELAY_b; + }; + + union + { + __IM uint32_t DC_SYS_TIME_DIFF; /*!< (@ 0x0000092C) System Time Difference Register */ + + struct + { + __IM uint32_t DIFF : 31; /*!< [30..0] System Time Mean Difference Indication */ + __IM uint32_t LCP : 1; /*!< [31..31] System Time Greater/Less Indication */ + } DC_SYS_TIME_DIFF_b; + }; + + union + { + __IM uint16_t DC_SPEED_COUNT_START; /*!< (@ 0x00000930) Speed Counter Start Register */ + + struct + { + __IM uint16_t SPDCNTSTRT : 15; /*!< [14..0] Drift Correction Bandwidth Setting */ + uint16_t : 1; + } DC_SPEED_COUNT_START_b; + }; + + union + { + __IM uint16_t DC_SPEED_COUNT_DIFF; /*!< (@ 0x00000932) Speed Counter Difference Register */ + + struct + { + __IM uint16_t SPDCNTDIFF : 16; /*!< [15..0] Clock Period Deviation Indication */ + } DC_SPEED_COUNT_DIFF_b; + }; + + union + { + __IM uint8_t DC_SYS_TIME_DIFF_FIL_DEPTH; /*!< (@ 0x00000934) System Time Difference Filter Depth Register */ + + struct + { + __IM uint8_t SYSTIMDEP : 4; /*!< [3..0] Filter Depth Setting */ + uint8_t : 4; + } DC_SYS_TIME_DIFF_FIL_DEPTH_b; + }; + + union + { + __IM uint8_t DC_SPEED_COUNT_FIL_DEPTH; /*!< (@ 0x00000935) Speed Counter Filter Depth Register */ + + struct + { + __IM uint8_t CLKPERDEP : 4; /*!< [3..0] Filter Depth Setting */ + uint8_t : 4; + } DC_SPEED_COUNT_FIL_DEPTH_b; + }; + __IM uint16_t RESERVED46; + __IM uint32_t RESERVED47[18]; + + union + { + __IM uint8_t DC_CYC_CONT; /*!< (@ 0x00000980) Cyclic Unit Control Register */ + + struct + { + __IM uint8_t SYNCOUT : 1; /*!< [0..0] SYNC Output Unit Control Setting */ + uint8_t : 3; + __IM uint8_t LATCH0 : 1; /*!< [4..4] Latch Input Unit 0 Control Setting */ + __IM uint8_t LATCH1 : 1; /*!< [5..5] Latch Input Unit 1 Control Setting */ + uint8_t : 2; + } DC_CYC_CONT_b; + }; + + union + { + __IOM uint8_t DC_ACT; /*!< (@ 0x00000981) Activation Register */ + + struct + { + __IOM uint8_t SYNCACT : 1; /*!< [0..0] Sync Output Unit Activation */ + __IOM uint8_t SYNC0 : 1; /*!< [1..1] SYNC0 Output Setting */ + __IOM uint8_t SYNC1 : 1; /*!< [2..2] SYNC1 Output Setting */ + __IOM uint8_t AUTOACT : 1; /*!< [3..3] SYNC Output Unit Activation */ + __IOM uint8_t EXTSTARTTIME : 1; /*!< [4..4] Start Time Cyclic Operation Extension */ + __IOM uint8_t STARTTIME : 1; /*!< [5..5] Start Time Plausibility */ + __IOM uint8_t NEARFUTURE : 1; /*!< [6..6] Near Future Range Setting */ + __IOM uint8_t DBGPULSE : 1; /*!< [7..7] Debug Pulse Setting */ + } DC_ACT_b; + }; + + union + { + __IM uint16_t DC_PULSE_LEN; /*!< (@ 0x00000982) SYNC Signal Pulse Length Register */ + + struct + { + __IM uint16_t PULSELEN : 16; /*!< [15..0] SYNC Signal Pulse Length Indication */ + } DC_PULSE_LEN_b; + }; + + union + { + __IM uint8_t DC_ACT_STAT; /*!< (@ 0x00000984) Activation Status Register */ + + struct + { + __IM uint8_t SYNC0ACT : 1; /*!< [0..0] SYNC0 Status Indication */ + __IM uint8_t SYNC1ACT : 1; /*!< [1..1] SYNC1 Status Indication */ + __IM uint8_t STARTTIME : 1; /*!< [2..2] Plausibility Result Indication */ + uint8_t : 5; + } DC_ACT_STAT_b; + }; + __IM uint8_t RESERVED48; + __IM uint16_t RESERVED49; + __IM uint32_t RESERVED50; + __IM uint16_t RESERVED51; + + union + { + __IM uint8_t DC_SYNC0_STAT; /*!< (@ 0x0000098E) SYNC0 Status Register */ + + struct + { + __IM uint8_t SYNC0STA : 1; /*!< [0..0] SYNC0 State Indication */ + uint8_t : 7; + } DC_SYNC0_STAT_b; + }; + + union + { + __IM uint8_t DC_SYNC1_STAT; /*!< (@ 0x0000098F) SYNC1 Status Register */ + + struct + { + __IM uint8_t SYNC1STA : 1; /*!< [0..0] SYNC1 State Indication */ + uint8_t : 7; + } DC_SYNC1_STAT_b; + }; + __IOM uint32_t DC_CYC_START_TIME_L; /*!< (@ 0x00000990) Start Time Cyclic Operation/Next SYNC0 Pulse + * Register L */ + __IOM uint32_t DC_CYC_START_TIME_H; /*!< (@ 0x00000994) Start Time Cyclic Operation/Next SYNC0 Pulse + * Register H */ + __IM uint32_t DC_NEXT_SYNC1_PULSE_L; /*!< (@ 0x00000998) Next SYNC1 Pulse Register L */ + __IM uint32_t DC_NEXT_SYNC1_PULSE_H; /*!< (@ 0x0000099C) Next SYNC1 Pulse Register H */ + + union + { + __IOM uint32_t DC_SYNC0_CYC_TIME; /*!< (@ 0x000009A0) SYNC0 Cycle Time Register */ + + struct + { + __IOM uint32_t SYNC0CYC : 32; /*!< [31..0] Time Between Consecutive SYNC0 Pulses */ + } DC_SYNC0_CYC_TIME_b; + }; + + union + { + __IOM uint32_t DC_SYNC1_CYC_TIME; /*!< (@ 0x000009A4) SYNC1 Cycle Time Register */ + + struct + { + __IOM uint32_t SYNC1CYC : 32; /*!< [31..0] Time between SYNC1 and SYNC0 Pulses */ + } DC_SYNC1_CYC_TIME_b; + }; + + union + { + __IOM uint8_t DC_LATCH0_CONT; /*!< (@ 0x000009A8) Latch 0 Control Register */ + + struct + { + __IOM uint8_t POSEDGE : 1; /*!< [0..0] Latch 0 Positive Edge Function Setting */ + __IOM uint8_t NEGEDGE : 1; /*!< [1..1] Latch 0 Negative Edge Function Setting */ + uint8_t : 6; + } DC_LATCH0_CONT_b; + }; + + union + { + __IOM uint8_t DC_LATCH1_CONT; /*!< (@ 0x000009A9) Latch 1 Control Register */ + + struct + { + __IOM uint8_t POSEDGE : 1; /*!< [0..0] Latch 1 Positive Edge Function Setting */ + __IOM uint8_t NEGEDGE : 1; /*!< [1..1] Latch 1 Negative Edge Function Setting */ + uint8_t : 6; + } DC_LATCH1_CONT_b; + }; + __IM uint16_t RESERVED52[2]; + + union + { + __IM uint8_t DC_LATCH0_STAT; /*!< (@ 0x000009AE) Latch 0 Status Register */ + + struct + { + __IM uint8_t EVENTPOS : 1; /*!< [0..0] Latch 0 Positive Edge Event Indication */ + __IM uint8_t EVENTNEG : 1; /*!< [1..1] Latch 0 Negative Edge Event Indication */ + __IM uint8_t PINSTATE : 1; /*!< [2..2] Latch 0 Input Pin State Indication */ + uint8_t : 5; + } DC_LATCH0_STAT_b; + }; + + union + { + __IM uint8_t DC_LATCH1_STAT; /*!< (@ 0x000009AF) Latch 1 Status Register */ + + struct + { + __IM uint8_t EVENTPOS : 1; /*!< [0..0] Latch 1 Positive Edge Event Indication */ + __IM uint8_t EVENTNEG : 1; /*!< [1..1] Latch 1 Negative Edge Event Indication */ + __IM uint8_t PINSTATE : 1; /*!< [2..2] Latch 1 Input Pin State Indication */ + uint8_t : 5; + } DC_LATCH1_STAT_b; + }; + __IM uint32_t DC_LATCH0_TIME_POS_L; /*!< (@ 0x000009B0) Latch 0 Time Positive Edge Register L */ + __IM uint32_t DC_LATCH0_TIME_POS_H; /*!< (@ 0x000009B4) Latch 0 Time Positive Edge Register H */ + __IM uint32_t DC_LATCH0_TIME_NEG_L; /*!< (@ 0x000009B8) Latch 0 Time Negative Edge Register L */ + __IM uint32_t DC_LATCH0_TIME_NEG_H; /*!< (@ 0x000009BC) Latch 0 Time Negative Edge Register H */ + __IM uint32_t DC_LATCH1_TIME_POS_L; /*!< (@ 0x000009C0) Latch 1 Time Positive Edge Register L */ + __IM uint32_t DC_LATCH1_TIME_POS_H; /*!< (@ 0x000009C4) Latch 1 Time Positive Edge Register H */ + __IM uint32_t DC_LATCH1_TIME_NEG_L; /*!< (@ 0x000009C8) Latch 1 Time Negative Edge Register L */ + __IM uint32_t DC_LATCH1_TIME_NEG_H; /*!< (@ 0x000009CC) Latch 1 Time Negative Edge Register H */ + __IM uint32_t RESERVED53[8]; + + union + { + __IM uint32_t DC_ECAT_CNG_EV_TIME; /*!< (@ 0x000009F0) Buffer Change Event Time Register */ + + struct + { + __IM uint32_t ECATCHANGE : 32; /*!< [31..0] Local Time Indication */ + } DC_ECAT_CNG_EV_TIME_b; + }; + __IM uint32_t RESERVED54; + + union + { + __IM uint32_t DC_PDI_START_EV_TIME; /*!< (@ 0x000009F8) PDI Buffer Start Event Time Register */ + + struct + { + __IM uint32_t PDISTART : 32; /*!< [31..0] Local Time Indication */ + } DC_PDI_START_EV_TIME_b; + }; + + union + { + __IM uint32_t DC_PDI_CNG_EV_TIME; /*!< (@ 0x000009FC) PDI Buffer Change Event Time Register */ + + struct + { + __IM uint32_t PDICHANGE : 32; /*!< [31..0] Local Time Indication */ + } DC_PDI_CNG_EV_TIME_b; + }; + __IM uint32_t RESERVED55[256]; + __IM uint32_t PRODUCT_ID_L; /*!< (@ 0x00000E00) Product ID Register L */ + __IM uint32_t PRODUCT_ID_H; /*!< (@ 0x00000E04) Product ID Register H */ + + union + { + __IM uint32_t VENDOR_ID_L; /*!< (@ 0x00000E08) Vendor ID Register L */ + + struct + { + __IM uint32_t VENDORID : 32; /*!< [31..0] Vendor ID Indication */ + } VENDOR_ID_L_b; + }; +} R_ESC_Type; /*!< Size = 3596 (0xe0c) */ + +/* =========================================================================================================================== */ +/* ================ R_USBHC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 HS Host Module (R_USBHC) + */ + +typedef struct /*!< (@ 0x80200000) R_USBHC Structure */ +{ + union + { + __IM uint32_t HCREVISION; /*!< (@ 0x00000000) HcRevision Register */ + + struct + { + __IM uint32_t REV : 8; /*!< [7..0] HCI revision */ + uint32_t : 24; + } HCREVISION_b; + }; + + union + { + __IOM uint32_t HCCONTROL; /*!< (@ 0x00000004) HcControl Register */ + + struct + { + __IOM uint32_t CBSR : 2; /*!< [1..0] Control/bulk transfer service ratio (ControlBulkServiceRatio) */ + __IOM uint32_t PLE : 1; /*!< [2..2] Periodic list setting (PeriodicListEnable) */ + __IOM uint32_t IE : 1; /*!< [3..3] Isochronous ED processing setting (IsochronousEnable) */ + __IOM uint32_t CLE : 1; /*!< [4..4] Control list processing setting (ControlListEnable) */ + __IOM uint32_t BLE : 1; /*!< [5..5] Bulk list processing setting (BulkListEnable) */ + __IOM uint32_t HCFS : 2; /*!< [7..6] Host logic operation status (Host Controller FunctionalState) */ + __IOM uint32_t IR : 1; /*!< [8..8] HcInterruptStatus interrupt path setting (InterruptRouting) */ + __IOM uint32_t RWC : 1; /*!< [9..9] Remote Wakeup support setting (RemoteWakeUpConnect) */ + __IOM uint32_t RWE : 1; /*!< [10..10] PME assertion control (RemoteWakeUpEnable) */ + uint32_t : 21; + } HCCONTROL_b; + }; + + union + { + __IOM uint32_t HCCOMMANDSTATUS; /*!< (@ 0x00000008) HcCommandStatus Register */ + + struct + { + __OM uint32_t HCR : 1; /*!< [0..0] Host logic software reset start (HostController Reset) */ + __IOM uint32_t CLF : 1; /*!< [1..1] Control list TD (ControlList Filled) */ + __IOM uint32_t BLF : 1; /*!< [2..2] Bulk list TD (BulkListFilled) */ + __OM uint32_t OCR : 1; /*!< [3..3] Host logic control right change (OwnershipChangeRequest) */ + uint32_t : 12; + __IM uint32_t SOC : 2; /*!< [17..16] Schedule overrun count (Scheduling OverrunCount) */ + uint32_t : 14; + } HCCOMMANDSTATUS_b; + }; + + union + { + __IOM uint32_t HCINTERRUPTSTATUS; /*!< (@ 0x0000000C) HcInterruptStatus Register */ + + struct + { + __IOM uint32_t SO : 1; /*!< [0..0] USB schedule overrun (Scheduling Overrun) */ + __IOM uint32_t WDH : 1; /*!< [1..1] Host logic HccaDoneHead update (Writeback Done Head) */ + __IOM uint32_t SF : 1; /*!< [2..2] HccaFrameNumber update (StartOfFrame) */ + __IOM uint32_t RD : 1; /*!< [3..3] Resume detection (Resume Detected) */ + __IOM uint32_t UE : 1; /*!< [4..4] USB non-related system error detection (Unrecoverable + * Error) */ + __IOM uint32_t FNO : 1; /*!< [5..5] FrameNumber bit MSB change (Frame Number Overflow) */ + __IOM uint32_t RHSC : 1; /*!< [6..6] HcRhStatus/HcRhPortStatus register status (RootHubStatus + * Change) */ + uint32_t : 23; + __IOM uint32_t OC : 1; /*!< [30..30] Host logic control right change (OwnershipChange) */ + uint32_t : 1; + } HCINTERRUPTSTATUS_b; + }; + + union + { + __IOM uint32_t HCINTERRUPTENABLE; /*!< (@ 0x00000010) HcInterruptEnable Register */ + + struct + { + __IOM uint32_t SOE : 1; /*!< [0..0] SO interrupt source enable (Scheduling OverrunEnable) */ + __IOM uint32_t WDHE : 1; /*!< [1..1] WDH interrupt source enable (WritebackDone HeadEnable) */ + __IOM uint32_t SFE : 1; /*!< [2..2] SF interrupt source enable (StartOfFrame) */ + __IOM uint32_t RDE : 1; /*!< [3..3] RD interrupt source enable (Resume DetectedEnable) */ + __IOM uint32_t UEE : 1; /*!< [4..4] UE interrupt source enable (Unrecoverable ErrorEnable) */ + __IOM uint32_t FNOE : 1; /*!< [5..5] FNO interrupt source enable (FrameNumber OverflowEnable) */ + __IOM uint32_t RHSCE : 1; /*!< [6..6] RHSC interrupt source enable (RootHubStatus ChangeEnable) */ + uint32_t : 23; + __IOM uint32_t OCE : 1; /*!< [30..30] OC interrupt source enable (OwnershipChangeEnable) */ + __IOM uint32_t MIE : 1; /*!< [31..31] Interrupt 8 source enable (MasterInterrupt Enable) */ + } HCINTERRUPTENABLE_b; + }; + + union + { + __IOM uint32_t HCINTERRUPTDISABLE; /*!< (@ 0x00000014) HcInterruptDisable Register */ + + struct + { + __IOM uint32_t SOD : 1; /*!< [0..0] SO interrupt source disable (Scheduling Overrun Disable) */ + __IOM uint32_t WDHD : 1; /*!< [1..1] WDH interrupt source disable (Writeback DoneHead Disable) */ + __IOM uint32_t SFD : 1; /*!< [2..2] SF interrupt source disable (StartOfFrame Disable) */ + __IOM uint32_t RDD : 1; /*!< [3..3] RD interrupt source disable (Resume Detected Disable) */ + __IOM uint32_t UED : 1; /*!< [4..4] UE interrupt source disable (Unrecoverable ErrorDisable) */ + __IOM uint32_t FNOD : 1; /*!< [5..5] FNO interrupt source disable (FrameNumberOverflow Disable) */ + __IOM uint32_t RHSCD : 1; /*!< [6..6] RHSC interrupt source disable (RootHub StatusChange Disable) */ + uint32_t : 23; + __IOM uint32_t OCD : 1; /*!< [30..30] OC interrupt source disable (OwnershipChangeDisable) */ + __IOM uint32_t MID : 1; /*!< [31..31] Interrupt 8 source disable (Master Interrupt Disable) */ + } HCINTERRUPTDISABLE_b; + }; + + union + { + __IOM uint32_t HCHCCA; /*!< (@ 0x00000018) HcHCCA Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t RAMBA : 24; /*!< [31..8] RAM base address setting */ + } HCHCCA_b; + }; + + union + { + __IM uint32_t HCPERIODCCURRENTIED; /*!< (@ 0x0000001C) HcPeriodicCurrentED Register */ + + struct + { + uint32_t : 4; + __IM uint32_t PCED : 28; /*!< [31..4] ED physical address (PeriodicCurrentED) */ + } HCPERIODCCURRENTIED_b; + }; + + union + { + __IOM uint32_t HCCONTROLHEADED; /*!< (@ 0x00000020) HcControlHeadED Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t CHED : 28; /*!< [31..4] Start ED physical address (ControlHeadED) */ + } HCCONTROLHEADED_b; + }; + + union + { + __IOM uint32_t HCCONTROLCURRENTED; /*!< (@ 0x00000024) HcControlCurrentED Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t CCED : 28; /*!< [31..4] ED physical address (ControlCurrentED) */ + } HCCONTROLCURRENTED_b; + }; + + union + { + __IOM uint32_t HCBULKHEADED; /*!< (@ 0x00000028) HcBulkHeadED Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t BHED : 28; /*!< [31..4] Start ED physical address (BulkHeadED) */ + } HCBULKHEADED_b; + }; + + union + { + __IOM uint32_t HCBULKCURRENTED; /*!< (@ 0x0000002C) HcBulkCurrentED Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t BCED : 28; /*!< [31..4] ED physical address (BulkCurrentED) */ + } HCBULKCURRENTED_b; + }; + + union + { + __IM uint32_t HCDONEHEAD; /*!< (@ 0x00000030) HcDoneHead Register */ + + struct + { + uint32_t : 4; + __IM uint32_t DH : 28; /*!< [31..4] HcDoneHead physical address (DoneHead) */ + } HCDONEHEAD_b; + }; + + union + { + __IOM uint32_t HCFMINTERVAL; /*!< (@ 0x00000034) HcFmInterval Register */ + + struct + { + __IOM uint32_t FI : 14; /*!< [13..0] Frame interval setting (FrameInterval) */ + uint32_t : 2; + __IOM uint32_t FSMPS : 15; /*!< [30..16] FS transfer packet maximum size setting (FSLagest DataPacket) */ + __IOM uint32_t FIT : 1; /*!< [31..31] Frame synchronization (FrameInterval Toggle) */ + } HCFMINTERVAL_b; + }; + + union + { + __IM uint32_t HCFNREMAINING; /*!< (@ 0x00000038) HcFmRemaining Register */ + + struct + { + __IM uint32_t FR : 14; /*!< [13..0] Down counter frame (FrameRemaining) */ + uint32_t : 17; + __IM uint32_t FRT : 1; /*!< [31..31] Frame synchronization (FrameRemainingToggle) */ + } HCFNREMAINING_b; + }; + + union + { + __IM uint32_t HCFMNUMBER; /*!< (@ 0x0000003C) HcFmNumber Register */ + + struct + { + __IM uint32_t FN : 16; /*!< [15..0] Elapsed frame number (FrameNumber) */ + uint32_t : 16; + } HCFMNUMBER_b; + }; + + union + { + __IOM uint32_t HCPERIODSTART; /*!< (@ 0x00000040) HcPeriodicStart Register */ + + struct + { + __IOM uint32_t PS : 14; /*!< [13..0] Periodic list processing start time (PeriodicStart) */ + uint32_t : 18; + } HCPERIODSTART_b; + }; + + union + { + __IOM uint32_t HCLSTHRESHOLD; /*!< (@ 0x00000044) HcLSThreshold Register */ + + struct + { + __IOM uint32_t LS : 12; /*!< [11..0] Transferrable threshold (LSThreshold) */ + uint32_t : 20; + } HCLSTHRESHOLD_b; + }; + + union + { + __IOM uint32_t HCRHDESCRIPTORA; /*!< (@ 0x00000048) HcRhDescriptorA Register */ + + struct + { + __IM uint32_t NDP : 8; /*!< [7..0] Downstream port number (NumberDownstreamPorts) */ + __IOM uint32_t PSM : 1; /*!< [8..8] Power switch control (PowerSwitchingMode) */ + __IOM uint32_t NPS : 1; /*!< [9..9] Power control (NoPower Switching) */ + __IM uint32_t DT : 1; /*!< [10..10] Device type (DeviceType) */ + __IOM uint32_t OCPM : 1; /*!< [11..11] Overcurrent state reporting (OverCurrentProtection + * Mode) */ + __IOM uint32_t NOCP : 1; /*!< [12..12] Overcurrent function support (NoOver Current Protection) */ + uint32_t : 11; + __IOM uint32_t POTPGT : 8; /*!< [31..24] Wait time (PowerOnToPowerGood Time) */ + } HCRHDESCRIPTORA_b; + }; + + union + { + __IOM uint32_t HCRHDESCRIPTORB; /*!< (@ 0x0000004C) HcRhDescriptorB Register */ + + struct + { + __IOM uint32_t DR : 16; /*!< [15..0] Device Removable */ + __IOM uint32_t PPCM : 16; /*!< [31..16] Port Power Control Mask */ + } HCRHDESCRIPTORB_b; + }; + + union + { + __IOM uint32_t HCRHSTATUS; /*!< (@ 0x00000050) HcRhStatus Register */ + + struct + { + __IOM uint32_t LPS : 1; /*!< [0..0] Local power status (LocalPowerStatus) */ + __IM uint32_t OCI : 1; /*!< [1..1] Overcurrent indicator (OverCurrent Indicator) */ + uint32_t : 13; + __IOM uint32_t DRWE : 1; /*!< [15..15] Device remote start enable (DeviceRemoteWakeupEnable) */ + __IOM uint32_t LPSC : 1; /*!< [16..16] Local power status change (LocalPowerStatusChange) */ + __IOM uint32_t OCIC : 1; /*!< [17..17] OCI bit change report (OverCurrent Indicate Change) */ + uint32_t : 13; + __OM uint32_t CRWE : 1; /*!< [31..31] DRWE bit clear (Clear Remote Wakeup Enable) */ + } HCRHSTATUS_b; + }; + + union + { + __IOM uint32_t HCRHPORTSTATUS1; /*!< (@ 0x00000054) HcRhPortStatus1 Register */ + + struct + { + __IOM uint32_t CCS : 1; /*!< [0..0] Connection status indication (CurrentConnectStatus) */ + __IOM uint32_t PES : 1; /*!< [1..1] Port enable status (PortEnableStatus) */ + __IOM uint32_t PSS : 1; /*!< [2..2] Suspend/Resume status (PortSuspendStatus) */ + __IM uint32_t POCI : 1; /*!< [3..3] Downstream port overcurrent detection (PortOverCurrentIndicator) */ + __IOM uint32_t PRS : 1; /*!< [4..4] Port reset status (PortResetStatus) */ + uint32_t : 3; + __IOM uint32_t PPS : 1; /*!< [8..8] Power status (PortPowerStatus) */ + __IOM uint32_t LSDA : 1; /*!< [9..9] Device speed (LowSpeedDeviceAttached) */ + uint32_t : 6; + __IOM uint32_t CSC : 1; /*!< [16..16] CCS bit status (ConnectStatus Change) */ + __IOM uint32_t PESC : 1; /*!< [17..17] PES bit status (PortEnable StatusChange) */ + __IOM uint32_t PSSC : 1; /*!< [18..18] RESUME sequence complete (PortSuspend StatusChange) */ + __IOM uint32_t OCIC : 1; /*!< [19..19] Overcurrent state detection (OverCurrent IndicateChange) */ + __IOM uint32_t PRSC : 1; /*!< [20..20] Port reset complete (PortReset StatusChange) */ + uint32_t : 11; + } HCRHPORTSTATUS1_b; + }; + __IM uint32_t RESERVED[42]; + + union + { + __IM uint32_t CAPL_VERSION; /*!< (@ 0x00000100) Capability Registers Length and EHCI Version + * Number Register */ + + struct + { + __IM uint32_t CRL : 8; /*!< [7..0] Capability Registers Length */ + uint32_t : 8; + __IM uint32_t HCIVN : 16; /*!< [31..16] EHCI Version Number */ + } CAPL_VERSION_b; + }; + + union + { + __IM uint32_t HCSPARAMS; /*!< (@ 0x00000104) Structural Parameters Register */ + + struct + { + __IM uint32_t N_PORTS : 4; /*!< [3..0] Number of downstream ports (Number of Ports) */ + __IM uint32_t PPC : 1; /*!< [4..4] Port power control (Port Power Control) */ + uint32_t : 2; + __IM uint32_t PTRR : 1; /*!< [7..7] Port routing rules */ + __IM uint32_t N_PCC : 4; /*!< [11..8] Number of ports (Number of Ports per Companion Controller) */ + __IM uint32_t N_CC : 4; /*!< [15..12] Number of OHCI host logic (Number of Companion Controller) */ + __IM uint32_t P_INDICATOR : 1; /*!< [16..16] Port indicator control support */ + uint32_t : 3; + __IM uint32_t DBGPTNUM : 4; /*!< [23..20] Debug port number */ + uint32_t : 8; + } HCSPARAMS_b; + }; + + union + { + __IM uint32_t HCCPARAMS; /*!< (@ 0x00000108) Capability Parameters Register */ + + struct + { + __IM uint32_t AC64 : 1; /*!< [0..0] Memory pointer selection */ + __IM uint32_t PFLF : 1; /*!< [1..1] Programming frame list flag */ + __IM uint32_t ASPC : 1; /*!< [2..2] Asynchronous schedule park support capability */ + uint32_t : 1; + __IM uint32_t IST : 4; /*!< [7..4] Isochronous data structure threshold */ + __IM uint32_t EECP : 8; /*!< [15..8] Offset address (EHCI Extend Capabilities Pointer) */ + __IM uint32_t HP : 1; /*!< [16..16] Hardware prefetch capability */ + __IM uint32_t LPMC : 1; /*!< [17..17] Link power management capability */ + __IM uint32_t PCEC : 1; /*!< [18..18] Per-port change event capability */ + __IM uint32_t PL32 : 1; /*!< [19..19] 32-frame periodic list capability */ + uint32_t : 12; + } HCCPARAMS_b; + }; + __IM uint32_t HCSP_PORTROUTE; /*!< (@ 0x0000010C) Companion Port Route Description Register */ + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t USBCMD; /*!< (@ 0x00000120) USB Command Register */ + + struct + { + __IOM uint32_t RS : 1; /*!< [0..0] EHCI host logic run/stop (Run/Stop) */ + __IOM uint32_t HCRESET : 1; /*!< [1..1] Host logic initialization (Host Controller Reset) */ + __IOM uint32_t FLS : 2; /*!< [3..2] Frame list size */ + __IOM uint32_t PSE : 1; /*!< [4..4] Periodic schedule enable */ + __IOM uint32_t ASYNSE : 1; /*!< [5..5] Asynchronous schedule enable */ + __IOM uint32_t IAAD : 1; /*!< [6..6] Interrupt on Async Advance Doorbell */ + __IM uint32_t LHCR : 1; /*!< [7..7] Light host controller reset execution status */ + __IOM uint32_t ASPMC : 2; /*!< [9..8] Asynchronous schedule park mode count */ + uint32_t : 1; + __IOM uint32_t ASPME : 1; /*!< [11..11] Asynchronous schedule park mode enable */ + uint32_t : 3; + __IOM uint32_t PPCEE : 1; /*!< [15..15] Per-port change event enable */ + __IOM uint32_t ITC : 8; /*!< [23..16] Host logic interrupt generation maximum rate (Interrupt + * Threshold Control) */ + __IOM uint32_t HIRD : 4; /*!< [27..24] Host-Initiated Resume Duration (Minimum K-state drive + * time) */ + uint32_t : 4; + } USBCMD_b; + }; + + union + { + __IOM uint32_t USBSTS; /*!< (@ 0x00000124) USB Status Register */ + + struct + { + __IOM uint32_t USBINT : 1; /*!< [0..0] USB transfer complete (USB Interrupt) */ + __IOM uint32_t USBERRINT : 1; /*!< [1..1] USB transaction status (USB Error Interrupt) */ + __IOM uint32_t PTCGDET : 1; /*!< [2..2] Port state change detection */ + __IOM uint32_t FLROV : 1; /*!< [3..3] Frame list rollover */ + __IOM uint32_t HSYSE : 1; /*!< [4..4] Host system error */ + __IOM uint32_t IAAIS : 1; /*!< [5..5] Async advance interrupt status */ + uint32_t : 6; + __IM uint32_t EHCSTS : 1; /*!< [12..12] EHCI host logic status (HCHalted) */ + __IM uint32_t RECLAM : 1; /*!< [13..13] Empty asynchronous schedule detection (Reclamation) */ + __IM uint32_t PSCHSTS : 1; /*!< [14..14] Periodic schedule status */ + __IM uint32_t ASS : 1; /*!< [15..15] Asynchronous schedule status */ + __IOM uint32_t PTCGDETC : 16; /*!< [31..16] Port-n Change Detect */ + } USBSTS_b; + }; + + union + { + __IOM uint32_t USBINTR; /*!< (@ 0x00000128) USB Interrupt Enable Register */ + + struct + { + __IOM uint32_t USBIE : 1; /*!< [0..0] USB interrupt enable */ + __IOM uint32_t USBEIE : 1; /*!< [1..1] USB error interrupt enable */ + __IOM uint32_t PTCGIE : 1; /*!< [2..2] Port change interrupt enable */ + __IOM uint32_t FMLSTROE : 1; /*!< [3..3] Frame list rollover enable */ + __IOM uint32_t HSEE : 1; /*!< [4..4] Host system error enable */ + __IOM uint32_t INTAADVE : 1; /*!< [5..5] Interrupt on async advance enable */ + uint32_t : 10; + __IOM uint32_t PCGIE : 16; /*!< [31..16] Port-n Change Interrupt Enable */ + } USBINTR_b; + }; + + union + { + __IOM uint32_t FRINDEX; /*!< (@ 0x0000012C) USB Frame Index Register */ + + struct + { + __IOM uint32_t FRAMEINDEX : 14; /*!< [13..0] Frame index */ + uint32_t : 18; + } FRINDEX_b; + }; + __IM uint32_t CTRLDSSEGMENT; /*!< (@ 0x00000130) Control Data Structure Segment Register */ + + union + { + __IOM uint32_t PERIODICLISTBASE; /*!< (@ 0x00000134) Periodic Frame List Base Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t PFLSA : 20; /*!< [31..12] Periodic frame list start address */ + } PERIODICLISTBASE_b; + }; + + union + { + __IOM uint32_t ASYNCLISTADDR; /*!< (@ 0x00000138) Next Asynchronous List Address Register */ + + struct + { + uint32_t : 5; + __IOM uint32_t LPL : 27; /*!< [31..5] Asynchronous Queue Head link pointer address (Link Pointer + * Low) */ + } ASYNCLISTADDR_b; + }; + __IM uint32_t RESERVED2[9]; + + union + { + __IOM uint32_t CONFIGFLAG; /*!< (@ 0x00000160) Configure Flag Register */ + + struct + { + __IOM uint32_t CF : 1; /*!< [0..0] Port routing control circuit configuration flag (Configure + * Flag) */ + uint32_t : 31; + } CONFIGFLAG_b; + }; + + union + { + __IOM uint32_t PORTSC1; /*!< (@ 0x00000164) Port 1 Status and Control Register */ + + struct + { + __IM uint32_t CCSTS : 1; /*!< [0..0] Port connection status */ + __IOM uint32_t CSC : 1; /*!< [1..1] Connect status change */ + __IOM uint32_t PTE : 1; /*!< [2..2] Port enable/disable status */ + __IOM uint32_t PTESC : 1; /*!< [3..3] Port enable/disable status change */ + __IM uint32_t OVCACT : 1; /*!< [4..4] Port overcurrent status */ + __IOM uint32_t OVCC : 1; /*!< [5..5] Over-current Change */ + __IOM uint32_t FRCPTRSM : 1; /*!< [6..6] Force Port Resume (Port resume detection flag) */ + __IOM uint32_t SUSPEND : 1; /*!< [7..7] Port suspend */ + __IOM uint32_t PTRST : 1; /*!< [8..8] Port reset status */ + __IOM uint32_t LPMCTL : 1; /*!< [9..9] LPM control */ + __IM uint32_t LINESTS : 2; /*!< [11..10] D+/D- logic level */ + __IOM uint32_t PP : 1; /*!< [12..12] Port Power Supply Control (Port Power) */ + __IOM uint32_t PTOWNR : 1; /*!< [13..13] Port ownership */ + __IM uint32_t PTINDCTL : 2; /*!< [15..14] As the host logic does not support the port indicator + * control function, these bits are set to 00b. */ + __IOM uint32_t PTTST : 4; /*!< [19..16] Pin test control */ + __IOM uint32_t WKCNNT_E : 1; /*!< [20..20] Device connection detection enable (Wake on Connect + * Enable) */ + __IOM uint32_t WKDSCNNT_E : 1; /*!< [21..21] Device disconnection detection enable (Wake on Disconnect + * Enable) */ + __IOM uint32_t WKOC_E : 1; /*!< [22..22] Overcurrent state detection enable (Wake on Over-current + * Enable) */ + __IOM uint32_t SUSPSTS : 2; /*!< [24..23] Suspend status */ + __IOM uint32_t DVADDR : 7; /*!< [31..25] USB device address */ + } PORTSC1_b; + }; + __IM uint32_t RESERVED3[38]; + + union + { + __IOM uint32_t INTENABLE; /*!< (@ 0x00000200) INT_ENABLE Register */ + + struct + { + __IOM uint32_t AHB_INTEN : 1; /*!< [0..0] AHB_INT bit control */ + __IOM uint32_t USBH_INTAEN : 1; /*!< [1..1] USBH_INTA bit control */ + __IOM uint32_t USBH_INTBEN : 1; /*!< [2..2] USBH_INTB bit control */ + __IOM uint32_t UCOM_INTEN : 1; /*!< [3..3] UCOM_INT bit control */ + __IOM uint32_t WAKEON_INTEN : 1; /*!< [4..4] WAKEON_INT bit control */ + uint32_t : 27; + } INTENABLE_b; + }; + + union + { + __IOM uint32_t INTSTATUS; /*!< (@ 0x00000204) INT_STATUS Register */ + + struct + { + __IOM uint32_t AHB_INT : 1; /*!< [0..0] AHB bus error indication */ + __IM uint32_t USBH_INTA : 1; /*!< [1..1] OHCI interrupt status */ + __IM uint32_t USBH_INTB : 1; /*!< [2..2] USBH_INTB EHCI interrupt status */ + __IM uint32_t UCOM_INT : 1; /*!< [3..3] UCOM register interrupt status */ + __IOM uint32_t WAKEON_INT : 1; /*!< [4..4] WAKEON interrupt status */ + uint32_t : 27; + } INTSTATUS_b; + }; + + union + { + __IOM uint32_t AHBBUSCTR; /*!< (@ 0x00000208) AHB_BUS_CTR Register */ + + struct + { + __IOM uint32_t MAX_BURST_LEN : 2; /*!< [1..0] Maximum burst length */ + uint32_t : 2; + __IOM uint32_t ALIGN_ADDRESS : 2; /*!< [5..4] Address boundary setting */ + uint32_t : 2; + __IOM uint32_t PROT_MODE : 1; /*!< [8..8] This bit selects the MHPROT[3:0] mode when the AHB master + * interface initiates a transfer. */ + uint32_t : 3; + __IOM uint32_t PROT_TYPE : 4; /*!< [15..12] These bits set MHPROT[3:0] when the AHB master interface + * initiates a transfer. */ + uint32_t : 16; + } AHBBUSCTR_b; + }; + + union + { + __IOM uint32_t USBCTR; /*!< (@ 0x0000020C) USBCTR Register */ + + struct + { + __OM uint32_t USBH_RST : 1; /*!< [0..0] Software reset for the core */ + __IOM uint32_t PLL_RST : 1; /*!< [1..1] Reset of USB PHY PLL */ + __IOM uint32_t DIRPD : 1; /*!< [2..2] Direct transition to power-down state */ + uint32_t : 29; + } USBCTR_b; + }; + __IM uint32_t RESERVED4[60]; + + union + { + __IM uint32_t REVID; /*!< (@ 0x00000300) Revision and Core ID Register */ + + struct + { + __IM uint32_t MINV : 8; /*!< [7..0] Minor Version */ + __IM uint32_t MAJV : 8; /*!< [15..8] Major Version */ + uint32_t : 8; + __IM uint32_t COREID : 8; /*!< [31..24] Core ID */ + } REVID_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint32_t OCSLPTIMSET; /*!< (@ 0x00000310) Overcurrent Detection/Sleep Timer Setting Register */ + + struct + { + __IOM uint32_t TIMER_OC : 20; /*!< [19..0] Overcurrent Timer setting */ + __IOM uint32_t TIMER_SLEEP : 9; /*!< [28..20] Detection/Sleep Timer Setting */ + uint32_t : 3; + } OCSLPTIMSET_b; + }; + __IM uint32_t RESERVED6[315]; + + union + { + __IOM uint32_t COMMCTRL; /*!< (@ 0x00000800) Common Control Register */ + + struct + { + uint32_t : 31; + __IOM uint32_t PERI : 1; /*!< [31..31] USB mode setting */ + } COMMCTRL_b; + }; + + union + { + __IOM uint32_t OBINTSTA; /*!< (@ 0x00000804) OTG-BC Interrupt Status Register */ + + struct + { + __IOM uint32_t IDCHG_STA : 1; /*!< [0..0] USB_OTGID change status */ + __IOM uint32_t OCINT_STA : 1; /*!< [1..1] USB_OVRCUR assertion status */ + __IOM uint32_t VBSTACHG_STA : 1; /*!< [2..2] VBSTA[3:0] change status */ + __IOM uint32_t VBSTAINT_STA : 1; /*!< [3..3] VBUS voltage status interrupt */ + uint32_t : 12; + __IOM uint32_t DMMONCHG_STA : 1; /*!< [16..16] DMMON change status */ + __IOM uint32_t DPMONCHG_STA : 1; /*!< [17..17] DPMON change status */ + uint32_t : 14; + } OBINTSTA_b; + }; + + union + { + __IOM uint32_t OBINTEN; /*!< (@ 0x00000808) OTG-BC Interrupt Enable Register */ + + struct + { + __IOM uint32_t IDCHG_EN : 1; /*!< [0..0] IDCHG_STA Interrupt enable */ + __IOM uint32_t OCINT_EN : 1; /*!< [1..1] OCINT_STA interrupt enable */ + __IOM uint32_t VBSTACHG_EN : 1; /*!< [2..2] VBSTACHG_STA interrupt enable */ + __IOM uint32_t VBSTAINT_EN : 1; /*!< [3..3] VBSTAINT_STA interrupt enable */ + uint32_t : 12; + __IOM uint32_t DMMONCHG_EN : 1; /*!< [16..16] DMMONCHG_STA interrupt enable */ + __IOM uint32_t DPMONCHG_EN : 1; /*!< [17..17] DPMONCHG_STA interrupt enable */ + uint32_t : 14; + } OBINTEN_b; + }; + + union + { + __IOM uint32_t VBCTRL; /*!< (@ 0x0000080C) VBUS Control Register */ + + struct + { + __IOM uint32_t VBOUT : 1; /*!< [0..0] VBUS drive control (USB_VBUSEN pin) */ + __IOM uint32_t VBUSENSEL : 1; /*!< [1..1] USB_VBUSEN pin control */ + uint32_t : 2; + __IOM uint32_t VGPUO : 1; /*!< [4..4] USB_EXICEN pin control */ + uint32_t : 11; + __IOM uint32_t OCCLRIEN : 1; /*!< [16..16] USB_VBUSEN pin control at occurrence of overcurrent */ + __IOM uint32_t OCISEL : 1; /*!< [17..17] Overcurrent detection */ + uint32_t : 2; + __IOM uint32_t VBLVL : 4; /*!< [23..20] VBUS level detection */ + uint32_t : 4; + __IM uint32_t VBSTA : 4; /*!< [31..28] VBUS indication */ + } VBCTRL_b; + }; + + union + { + __IOM uint32_t LINECTRL1; /*!< (@ 0x00000810) Line Control Port 1 Register */ + + struct + { + __IM uint32_t IDMON : 1; /*!< [0..0] Indicates a value of USB_OTGID input pin. */ + uint32_t : 1; + __IM uint32_t DMMON : 1; /*!< [2..2] Indicates a value of USB bus DM. */ + __IM uint32_t DPMON : 1; /*!< [3..3] Indicates a value of USB bus DP. */ + uint32_t : 12; + __IOM uint32_t DM_RPD : 1; /*!< [16..16] Controls USB bus (DM) 15 kOhm pulldown resistor when + * DMPPD_EN = 1. */ + __IOM uint32_t DMRPD_EN : 1; /*!< [17..17] Enables DM_RPD to control USB bus (DM) 15 kOhm pulldown + * resistor. */ + __IOM uint32_t DP_RPD : 1; /*!< [18..18] Controls USB bus (DP) 15 kOhm pulldown resistor when + * DRPPD_EN = 1. */ + __IOM uint32_t DPRPD_EN : 1; /*!< [19..19] Enables DP_RPD to control USB bus (DP) 15 kOhm pulldown + * resistor. */ + uint32_t : 12; + } LINECTRL1_b; + }; +} R_USBHC_Type; /*!< Size = 2068 (0x814) */ + +/* =========================================================================================================================== */ +/* ================ R_USBF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Host and Function Module (R_USBF) + */ + +typedef struct /*!< (@ 0x80201000) R_USBF Structure */ +{ + union + { + __IOM uint16_t SYSCFG0; /*!< (@ 0x00000000) System Configuration Control Register 0 */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Block Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + uint16_t : 1; + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] Single-End Receiver Operation Enable */ + uint16_t : 7; + } SYSCFG0_b; + }; + + union + { + __IOM uint16_t SYSCFG1; /*!< (@ 0x00000002) System Configuration Control Register 1 */ + + struct + { + __IOM uint16_t BWAIT : 6; /*!< [5..0] CPU Bus Access Wait Specification */ + uint16_t : 2; + __IOM uint16_t AWAIT : 6; /*!< [13..8] AHB-DMA Bridge Bus Access Wait Specification */ + uint16_t : 2; + } SYSCFG1_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + uint16_t : 14; + } SYSSTS0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] Reset Handshake */ + uint16_t : 5; + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + uint16_t : 7; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3; + + union + { + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port */ + } CFIFO_b; + }; + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) FIFO Port Register */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) FIFO Port Register */ + }; + + union + { + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) FIFO Port Register */ + + struct + { + __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port */ + } CFIFOH_b; + }; + + struct + { + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) FIFO Port Register */ + + struct + { + __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port */ + } CFIFOHH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port */ + } D0FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) FIFO Port Register */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) FIFO Port Register */ + }; + + union + { + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) FIFO Port Register */ + + struct + { + __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port */ + } D0FIFOH_b; + }; + + struct + { + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) FIFO Port Register */ + + struct + { + __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port */ + } D0FIFOHH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port */ + } D1FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) FIFO Port Register */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) FIFO Port Register */ + }; + + union + { + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) FIFO Port Register */ + + struct + { + __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port */ + } D1FIFOH_b; + }; + + struct + { + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) FIFO Port Register */ + + struct + { + __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port */ + } D1FIFOHH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode after Specified Pipe + * Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode after Specified Pipe + * Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE : 1; /*!< [0..0] PDDETINT Detection Interrupt Enable */ + uint16_t : 15; + } INTENB1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing */ + uint16_t : 9; + } SOFCFG_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] BRDY Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] NRDY Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] BEMP Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Update Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Change Detect Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT : 1; /*!< [0..0] PDDET Detection Interrupt Status */ + uint16_t : 15; + } INTSTS1_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IM uint16_t UFRMNUM; /*!< (@ 0x0000004E) Frame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] Microframe Number */ + uint16_t : 13; + } UFRMNUM_b; + }; + + union + { + __IM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address */ + uint16_t : 9; + } USBADDR_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request Type */ + __IM uint16_t BREQUEST : 8; /*!< [15..8] Request */ + } USBREQ_b; + }; + + union + { + __IM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IM uint16_t WVALUE : 16; /*!< [15..0] Value */ + } USBVAL_b; + }; + + union + { + __IM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IM uint16_t WINDEX : 16; /*!< [15..0] Index */ + } USBINDX_b; + }; + + union + { + __IM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IM uint16_t WLENGTH : 16; /*!< [15..0] Length */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Disabling PIPE at the End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet Size */ + uint16_t : 9; + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] PIPE Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + uint16_t : 6; + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disable at the End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Specification Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer number */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer size */ + uint16_t : 1; + } PIPEBUF_b; + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet Size */ + uint16_t : 5; + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Timing Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection Spacing */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE[0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] PIPE Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit Confirm */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 3; + __IM uint16_t INBUFM : 1; /*!< [14..14] Transfer Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[3]; + __IOM R_USBF_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) PIPEn Transaction Counter Registers (n=1-5) */ + __IM uint32_t RESERVED16[23]; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED18[191]; + __IOM R_USBF_CHa_Type CHa[2]; /*!< (@ 0x00000400) Next Register Set */ + __IM uint32_t RESERVED19[96]; + __IOM R_USBF_CHb_Type CHb[2]; /*!< (@ 0x00000600) Skip Register Set */ + __IM uint32_t RESERVED20[48]; + + union + { + __IOM uint32_t DCTRL; /*!< (@ 0x00000700) DMA Control Register */ + + struct + { + __IOM uint32_t PR : 1; /*!< [0..0] Priority */ + uint32_t : 15; + __IOM uint32_t LDPR : 4; /*!< [19..16] Link Descriptor PROT */ + uint32_t : 4; + __IOM uint32_t LWPR : 4; /*!< [27..24] Link WriteBack PROT */ + uint32_t : 4; + } DCTRL_b; + }; + + union + { + __IOM uint32_t DSCITVL; /*!< (@ 0x00000704) Descriptor Interval Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t DITVL : 8; /*!< [15..8] Descriptor Interval */ + uint32_t : 16; + } DSCITVL_b; + }; + __IM uint32_t RESERVED21[2]; + + union + { + __IM uint32_t DSTAT_EN; /*!< (@ 0x00000710) DMA Status EN Register */ + + struct + { + __IM uint32_t EN0 : 1; /*!< [0..0] Channel 0 EN */ + __IM uint32_t EN1 : 1; /*!< [1..1] Channel 1 EN */ + uint32_t : 30; + } DSTAT_EN_b; + }; + + union + { + __IM uint32_t DSTAT_ER; /*!< (@ 0x00000714) DMA Status ER Register */ + + struct + { + __IM uint32_t ER0 : 1; /*!< [0..0] Channel 0 ER */ + __IM uint32_t ER1 : 1; /*!< [1..1] Channel 1 ER */ + uint32_t : 30; + } DSTAT_ER_b; + }; + + union + { + __IM uint32_t DSTAT_END; /*!< (@ 0x00000718) DMA Status END Register */ + + struct + { + __IM uint32_t END0 : 1; /*!< [0..0] Channel 0 END */ + __IM uint32_t END1 : 1; /*!< [1..1] Channel 1 END */ + uint32_t : 30; + } DSTAT_END_b; + }; + + union + { + __IM uint32_t DSTAT_TC; /*!< (@ 0x0000071C) DMA Status TC Register */ + + struct + { + __IM uint32_t TC0 : 1; /*!< [0..0] Channel 0 TC */ + __IM uint32_t TC1 : 1; /*!< [1..1] Channel 1 TC */ + uint32_t : 30; + } DSTAT_TC_b; + }; + + union + { + __IM uint32_t DSTAT_SUS; /*!< (@ 0x00000720) DMA Status SUS Register */ + + struct + { + __IM uint32_t SUS0 : 1; /*!< [0..0] Channel 0 SUS */ + __IM uint32_t SUS1 : 1; /*!< [1..1] Channel 1 SUS */ + uint32_t : 30; + } DSTAT_SUS_b; + }; +} R_USBF_Type; /*!< Size = 1828 (0x724) */ + +/* =========================================================================================================================== */ +/* ================ R_BSC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus State Controller (R_BSC) + */ + +typedef struct /*!< (@ 0x80210000) R_BSC Structure */ +{ + union + { + __IOM uint32_t CMNCR; /*!< (@ 0x00000000) Common Control Register */ + + struct + { + uint32_t : 9; + __IOM uint32_t DPRTY : 2; /*!< [10..9] DMA Burst Transfer Priority */ + uint32_t : 13; + __IOM uint32_t AL : 1; /*!< [24..24] Acknowledge Level */ + uint32_t : 3; + __IOM uint32_t TL : 1; /*!< [28..28] Transfer End Level */ + uint32_t : 3; + } CMNCR_b; + }; + + union + { + __IOM uint32_t CSnBCR[6]; /*!< (@ 0x00000004) CS[0..5] Space Bus Control Register */ + + struct + { + uint32_t : 9; + __IOM uint32_t BSZ : 2; /*!< [10..9] Data Bus Width Specification */ + uint32_t : 1; + __IOM uint32_t TYPE : 3; /*!< [14..12] Memory Connected to a Space */ + uint32_t : 1; + __IOM uint32_t IWRRS : 3; /*!< [18..16] Idle State Insertion between Read-Read Cycles in the + * Same CS Space */ + __IOM uint32_t IWRRD : 3; /*!< [21..19] Idle State Insertion between Read-Read Cycles in Different + * CS Spaces */ + __IOM uint32_t IWRWS : 3; /*!< [24..22] Idle State Insertion between Read-Write Cycles in the + * Same CS Space */ + __IOM uint32_t IWRWD : 3; /*!< [27..25] Idle State Insertion between Read-Write Cycles in Different + * CS Spaces */ + __IOM uint32_t IWW : 3; /*!< [30..28] Idle Cycles between Write-Read Cycles and Write-Write + * Cycles */ + uint32_t : 1; + } CSnBCR_b[6]; + }; + __IM uint32_t RESERVED[3]; + + union + { + union + { + __IOM uint32_t CS0WCR_0; /*!< (@ 0x00000028) CS0 Space Wait Control Register for Normal Space, + * SRAM with Byte Selection */ + + struct + { + __IOM uint32_t HW : 2; /*!< [1..0] Delay States from RD#, WEn# Negation to Address, CS0# + * Negation */ + uint32_t : 4; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t WR : 4; /*!< [10..7] Number of Access Waits */ + __IOM uint32_t SW : 2; /*!< [12..11] Number of Delay Cycles from Address, CSn# Assertion + * to RD#, WEn# Assertion */ + uint32_t : 7; + __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select */ + uint32_t : 11; + } CS0WCR_0_b; + }; + + union + { + __IOM uint32_t CS0WCR_1; /*!< (@ 0x00000028) CS0 Space Wait Control Register for Burst ROM + * with Clocked Asynchronous */ + + struct + { + uint32_t : 6; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t W : 4; /*!< [10..7] Number of Access Waits */ + uint32_t : 5; + __IOM uint32_t BW : 2; /*!< [17..16] Number of Waits during Burst Access */ + uint32_t : 2; + __IOM uint32_t BST : 2; /*!< [21..20] Burst Count Specification */ + uint32_t : 10; + } CS0WCR_1_b; + }; + + union + { + __IOM uint32_t CS0WCR_2; /*!< (@ 0x00000028) CS0 Space Wait Control Register for Burst ROM + * with Clocked Synchronous */ + + struct + { + uint32_t : 6; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t W : 4; /*!< [10..7] Number of Access Waits */ + uint32_t : 5; + __IOM uint32_t BW : 2; /*!< [17..16] Number of Burst Wait Cycles */ + uint32_t : 14; + } CS0WCR_2_b; + }; + }; + __IM uint32_t RESERVED1; + + union + { + union + { + __IOM uint32_t CS2WCR_0; /*!< (@ 0x00000030) CS2 Space Wait Control Register for Normal Space, + * SRAM with Byte Selection */ + + struct + { + uint32_t : 6; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t WR : 4; /*!< [10..7] Number of Access Waits */ + uint32_t : 9; + __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select */ + uint32_t : 11; + } CS2WCR_0_b; + }; + + union + { + __IOM uint32_t CS2WCR_1; /*!< (@ 0x00000030) CS2 Space Wait Control Register for SDRAM */ + + struct + { + uint32_t : 7; + __IOM uint32_t A2CL : 2; /*!< [8..7] CAS Latency for Area 2 */ + uint32_t : 23; + } CS2WCR_1_b; + }; + }; + + union + { + union + { + __IOM uint32_t CS3WCR_0; /*!< (@ 0x00000034) CS3 Space Wait Control Register for Normal Space, + * SRAM with Byte Selection */ + + struct + { + uint32_t : 6; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t WR : 4; /*!< [10..7] Number of Access Waits */ + uint32_t : 9; + __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select */ + uint32_t : 11; + } CS3WCR_0_b; + }; + + union + { + __IOM uint32_t CS3WCR_1; /*!< (@ 0x00000034) CS3 Space Wait Control Register for SDRAM */ + + struct + { + __IOM uint32_t WTRC : 2; /*!< [1..0] Number of Idle States from REF Command/Self-Refresh Release + * to ACTV/REF/MRS Command */ + uint32_t : 1; + __IOM uint32_t TRWL : 2; /*!< [4..3] Number of Auto-Precharge Startup Wait Cycles */ + uint32_t : 2; + __IOM uint32_t A3CL : 2; /*!< [8..7] CAS Latency for Area 3 */ + uint32_t : 1; + __IOM uint32_t WTRCD : 2; /*!< [11..10] Number of Waits between ACTV Command and READ(A)/WRIT(A) + * Command */ + uint32_t : 1; + __IOM uint32_t WTRP : 2; /*!< [14..13] Number of Auto-Precharge Completion Wait States */ + uint32_t : 17; + } CS3WCR_1_b; + }; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CS5WCR; /*!< (@ 0x0000003C) CS5 Space Wait Control Register for Normal Space, + * SRAM with Byte Selection, and MPX-I/O */ + + struct + { + __IOM uint32_t HW : 2; /*!< [1..0] Delay Cycles from RD#, WEn# to Address, CS5# */ + uint32_t : 4; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t WR : 4; /*!< [10..7] Number of Read Access Waits */ + __IOM uint32_t SW : 2; /*!< [12..11] Number of Delay Cycles from Address, CS5# Assertion + * to RD#, WEn# Assertion */ + uint32_t : 3; + __IOM uint32_t WW : 3; /*!< [18..16] Number of Write Access Waits */ + uint32_t : 1; + __IOM uint32_t MPXWSBAS : 1; /*!< [20..20] MPX-I/O Interface Address Cycle Wait and SRAM with + * Byte Selection Byte Access Select */ + __IOM uint32_t SZSEL : 1; /*!< [21..21] MPX-I/O Interface Bus Width Specification */ + uint32_t : 10; + } CS5WCR_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t SDCR; /*!< (@ 0x0000004C) SDRAM Control Register */ + + struct + { + __IOM uint32_t A3COL : 2; /*!< [1..0] Number of Bits of Column Address for Area 3 */ + uint32_t : 1; + __IOM uint32_t A3ROW : 2; /*!< [4..3] Number of Bits of Row Address for Area 3 */ + uint32_t : 3; + __IOM uint32_t BACTV : 1; /*!< [8..8] Bank Active Mode */ + __IOM uint32_t PDOWN : 1; /*!< [9..9] Power-Down Mode */ + __IOM uint32_t RMODE : 1; /*!< [10..10] Refresh Mode */ + __IOM uint32_t RFSH : 1; /*!< [11..11] Refresh Control */ + uint32_t : 1; + __IOM uint32_t DEEP : 1; /*!< [13..13] Deep Power-Down Mode */ + uint32_t : 2; + __IOM uint32_t A2COL : 2; /*!< [17..16] Number of Bits of Column Address for Area 2 */ + uint32_t : 1; + __IOM uint32_t A2ROW : 2; /*!< [20..19] Number of Bits of Row Address for Area 2 */ + uint32_t : 11; + } SDCR_b; + }; + __IOM uint32_t RTCSR; /*!< (@ 0x00000050) Refresh Timer Control/Status Register */ + __IOM uint32_t RTCNT; /*!< (@ 0x00000054) Refresh Timer Counter */ + __IOM uint32_t RTCOR; /*!< (@ 0x00000058) Refresh Time Constant Register */ + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t TOSCOR[6]; /*!< (@ 0x00000060) Timeout Cycle Constant Register [0..5] */ + + struct + { + __IOM uint32_t TOCNUM : 16; /*!< [15..0] Timeout Cycle Number */ + uint32_t : 16; + } TOSCOR_b[6]; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t TOSTR; /*!< (@ 0x00000080) Timeout Status Register */ + + struct + { + __IOM uint32_t CS0TOSTF : 1; /*!< [0..0] CS0 Space Timeout Status Flag */ + uint32_t : 1; + __IOM uint32_t CS2TOSTF : 1; /*!< [2..2] CS2 Space Timeout Status Flag */ + __IOM uint32_t CS3TOSTF : 1; /*!< [3..3] CS3 Space Timeout Status Flag */ + uint32_t : 1; + __IOM uint32_t CS5TOSTF : 1; /*!< [5..5] CS5 Space Timeout Status Flag */ + uint32_t : 26; + } TOSTR_b; + }; + + union + { + __IOM uint32_t TOENR; /*!< (@ 0x00000084) Timeout Enable Register */ + + struct + { + __IOM uint32_t CS0TOEN : 1; /*!< [0..0] CS0 Space Timeout Detection Enable */ + uint32_t : 1; + __IOM uint32_t CS2TOEN : 1; /*!< [2..2] CS2 Space Timeout Detection Enable */ + __IOM uint32_t CS3TOEN : 1; /*!< [3..3] CS3 Space Timeout Detection Enable */ + uint32_t : 1; + __IOM uint32_t CS5TOEN : 1; /*!< [5..5] CS5 Space Timeout Detection Enable */ + uint32_t : 26; + } TOENR_b; + }; +} R_BSC_Type; /*!< Size = 136 (0x88) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief xSPI (R_XSPI0) + */ + +typedef struct /*!< (@ 0x80220000) R_XSPI0 Structure */ +{ + union + { + __IOM uint32_t WRAPCFG; /*!< (@ 0x00000000) xSPI Wrapper Configuration Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0 */ + uint32_t : 11; + __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1 */ + uint32_t : 3; + } WRAPCFG_b; + }; + + union + { + __IOM uint32_t COMCFG; /*!< (@ 0x00000004) xSPI Common Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t OEASTEX : 1; /*!< [16..16] Output Enable Asserting extension */ + __IOM uint32_t OENEGEX : 1; /*!< [17..17] Output Enable Negating extension */ + uint32_t : 14; + } COMCFG_b; + }; + + union + { + __IOM uint32_t BMCFG; /*!< (@ 0x00000008) xSPI Bridge Map Configuration Register */ + + struct + { + __IOM uint32_t WRMD : 1; /*!< [0..0] AHB Write Response mode */ + uint32_t : 6; + __IOM uint32_t MWRCOMB : 1; /*!< [7..7] Memory Write Combination mode */ + __IOM uint32_t MWRSIZE : 8; /*!< [15..8] Memory Write Size */ + __IOM uint32_t PREEN : 1; /*!< [16..16] Prefetch enable */ + uint32_t : 15; + } BMCFG_b; + }; + __IM uint32_t RESERVED; + __IOM R_XSPI0_CSa_Type CSa[2]; /*!< (@ 0x00000010) xSPI Command Map Configuration Register [0..1] */ + __IM uint32_t RESERVED1[8]; + + union + { + __IOM uint32_t LIOCFGCS[2]; /*!< (@ 0x00000050) xSPI Link I/O Configuration Register CSn */ + + struct + { + __IOM uint32_t PRTMD : 10; /*!< [9..0] Protocol mode */ + __IOM uint32_t LATEMD : 1; /*!< [10..10] Latency mode */ + __IOM uint32_t WRMSKMD : 1; /*!< [11..11] Write mask mode */ + uint32_t : 4; + __IOM uint32_t CSMIN : 4; /*!< [19..16] CS minimum idle term */ + __IOM uint32_t CSASTEX : 1; /*!< [20..20] CS asserting extension */ + __IOM uint32_t CSNEGEX : 1; /*!< [21..21] CS negating extension */ + __IOM uint32_t SDRDRV : 1; /*!< [22..22] SDR driving timing */ + __IOM uint32_t SDRSMPMD : 1; /*!< [23..23] SDR Sampling mode */ + __IOM uint32_t SDRSMPSFT : 4; /*!< [27..24] SDR Sampling window shift */ + __IOM uint32_t DDRSMPEX : 4; /*!< [31..28] DDR sampling window extend */ + } LIOCFGCS_b[2]; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t BMCTL0; /*!< (@ 0x00000060) xSPI Bridge Map Control Register 0 */ + + struct + { + __IOM uint32_t CS0ACC : 2; /*!< [1..0] AHB channel to slave0 memory area access enable */ + __IOM uint32_t CS1ACC : 2; /*!< [3..2] AHB channel to slave1 memory area access enable */ + uint32_t : 28; + } BMCTL0_b; + }; + + union + { + __OM uint32_t BMCTL1; /*!< (@ 0x00000064) xSPI Bridge Map Control Register 1 */ + + struct + { + uint32_t : 8; + __OM uint32_t MWRPUSH : 1; /*!< [8..8] Memory Write Data Push */ + uint32_t : 1; + __OM uint32_t PBUFCLR : 1; /*!< [10..10] Prefetch Buffer clear */ + uint32_t : 21; + } BMCTL1_b; + }; + + union + { + __IOM uint32_t CMCTL; /*!< (@ 0x00000068) xSPI Command Map Control Register */ + + struct + { + __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code */ + __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code */ + __IOM uint32_t XIPEN : 1; /*!< [16..16] XiP mode enable */ + uint32_t : 15; + } CMCTL_b; + }; + + union + { + __IOM uint32_t CSSCTL; /*!< (@ 0x0000006C) xSPI CS Size Control Register */ + + struct + { + __IOM uint32_t CS0SIZE : 6; /*!< [5..0] CS0 (slave0) size */ + uint32_t : 2; + __IOM uint32_t CS1SIZE : 6; /*!< [13..8] CS1 (slave1) size */ + uint32_t : 18; + } CSSCTL_b; + }; + + union + { + __IOM uint32_t CDCTL0; /*!< (@ 0x00000070) xSPI Command Manual Control Register 0 */ + + struct + { + __IOM uint32_t TRREQ : 1; /*!< [0..0] Transaction request */ + __IOM uint32_t PERMD : 1; /*!< [1..1] Periodic mode */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t TRNUM : 2; /*!< [5..4] Transaction number */ + uint32_t : 10; + __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval */ + uint32_t : 3; + __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat */ + uint32_t : 4; + } CDCTL0_b; + }; + + union + { + __IOM uint32_t CDCTL1; /*!< (@ 0x00000074) xSPI Command Manual Control Register 1 */ + + struct + { + __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value */ + } CDCTL1_b; + }; + + union + { + __IOM uint32_t CDCTL2; /*!< (@ 0x00000078) xSPI Command Manual Control Register 2 */ + + struct + { + __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value */ + } CDCTL2_b; + }; + __IM uint32_t RESERVED3; + __IOM R_XSPI0_BUF_Type BUF[4]; /*!< (@ 0x00000080) xSPI Command Manual Buf [0..3] */ + __IM uint32_t RESERVED4[16]; + + union + { + __IOM uint32_t LPCTL0; /*!< (@ 0x00000100) xSPI Link Pattern Control Register 0 */ + + struct + { + __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request */ + uint32_t : 2; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t XDPIN : 2; /*!< [5..4] XiP Disable pattern pin */ + uint32_t : 10; + __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length */ + uint32_t : 2; + __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value */ + __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length */ + uint32_t : 2; + __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value */ + } LPCTL0_b; + }; + + union + { + __IOM uint32_t LPCTL1; /*!< (@ 0x00000104) xSPI Link Pattern Control Register 1 */ + + struct + { + __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat */ + uint32_t : 2; + __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width */ + uint32_t : 1; + __IOM uint32_t RSTSU : 3; /*!< [14..12] Reset pattern data output setup time */ + uint32_t : 17; + } LPCTL1_b; + }; + + union + { + __IOM uint32_t LIOCTL; /*!< (@ 0x00000108) xSPI Link I/O Control Register */ + + struct + { + __IOM uint32_t WPCS0 : 1; /*!< [0..0] WP drive for slave0 */ + __IOM uint32_t WPCS1 : 1; /*!< [1..1] WP drive for slave1 */ + uint32_t : 14; + __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave0 */ + __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave1 */ + uint32_t : 14; + } LIOCTL_b; + }; + __IM uint32_t RESERVED5[9]; + __IOM R_XSPI0_CSb_Type CSb[2]; /*!< (@ 0x00000130) xSPI Command Calibration Control register [0..1] */ + __IM uint32_t RESERVED6[4]; + + union + { + __IM uint32_t VERSTT; /*!< (@ 0x00000180) xSPI Version Register */ + + struct + { + __IM uint32_t VER : 32; /*!< [31..0] Version */ + } VERSTT_b; + }; + + union + { + __IM uint32_t COMSTT; /*!< (@ 0x00000184) xSPI Common Status Register */ + + struct + { + __IM uint32_t MEMACC : 1; /*!< [0..0] Memory access ongoing */ + uint32_t : 3; + __IM uint32_t PBUFNE : 1; /*!< [4..4] Prefetch Buffer Not Empty */ + uint32_t : 1; + __IM uint32_t WRBUFNE : 1; /*!< [6..6] Write Buffer Not Empty */ + uint32_t : 9; + __IM uint32_t ECSCS0 : 1; /*!< [16..16] ECS monitor for slave0 */ + __IM uint32_t INTCS0 : 1; /*!< [17..17] INT monitor for slave0 */ + __IM uint32_t RSTOCS0 : 1; /*!< [18..18] RSTO monitor for slave0 */ + uint32_t : 1; + __IM uint32_t ECSCS1 : 1; /*!< [20..20] ECS monitor for slave1 */ + __IM uint32_t INTCS1 : 1; /*!< [21..21] INT monitor for slave1 */ + __IM uint32_t RSTOCS1 : 1; /*!< [22..22] RSTO monitor for slave1 */ + uint32_t : 9; + } COMSTT_b; + }; + + union + { + __IM uint32_t CASTTCS[2]; /*!< (@ 0x00000188) xSPI Calibration Status Register CSn */ + + struct + { + __IM uint32_t CASUC : 32; /*!< [31..0] Calibration Success */ + } CASTTCS_b[2]; + }; + + union + { + __IM uint32_t INTS; /*!< (@ 0x00000190) xSPI Interrupt Status Register */ + + struct + { + __IM uint32_t CMDCMP : 1; /*!< [0..0] Command Completed */ + __IM uint32_t PATCMP : 1; /*!< [1..1] Pattern Completed */ + __IM uint32_t INICMP : 1; /*!< [2..2] Initial Sequence Completed */ + __IM uint32_t PERTO : 1; /*!< [3..3] Periodic transaction timeout */ + __IM uint32_t DSTOCS0 : 1; /*!< [4..4] DS timeout for slave0 */ + __IM uint32_t DSTOCS1 : 1; /*!< [5..5] DS timeout for slave1 */ + uint32_t : 2; + __IM uint32_t ECSCS0 : 1; /*!< [8..8] ECC error detection for slave0 */ + __IM uint32_t ECSCS1 : 1; /*!< [9..9] ECC error detection for slave1 */ + uint32_t : 2; + __IM uint32_t INTCS0 : 1; /*!< [12..12] Interrupt detection for slave0 */ + __IM uint32_t INTCS1 : 1; /*!< [13..13] Interrupt detection for slave1 */ + uint32_t : 2; + __IM uint32_t BRGOF : 1; /*!< [16..16] Bridge Buffer overflow */ + uint32_t : 1; + __IM uint32_t BRGUF : 1; /*!< [18..18] Bridge Buffer underflow */ + uint32_t : 1; + __IM uint32_t BUSERR : 1; /*!< [20..20] AHB bus error */ + uint32_t : 7; + __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0 */ + __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1 */ + __IM uint32_t CASUCCS0 : 1; /*!< [30..30] Calibration success for slave0 */ + __IM uint32_t CASUCCS1 : 1; /*!< [31..31] Calibration success for slave1 */ + } INTS_b; + }; + + union + { + __OM uint32_t INTC; /*!< (@ 0x00000194) xSPI Interrupt Clear Register */ + + struct + { + __OM uint32_t CMDCMPC : 1; /*!< [0..0] Command Completed interrupt clear */ + __OM uint32_t PATCMPC : 1; /*!< [1..1] Pattern Completed interrupt clear */ + __OM uint32_t INICMPC : 1; /*!< [2..2] Initial Sequence Completed interrupt clear */ + __OM uint32_t PERTOC : 1; /*!< [3..3] Periodic transaction timeout interrupt clear */ + __OM uint32_t DSTOCS0C : 1; /*!< [4..4] DS timeout for slave0 interrupt clear */ + __OM uint32_t DSTOCS1C : 1; /*!< [5..5] DS timeout for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t ECSCS0C : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear */ + __OM uint32_t ECSCS1C : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t INTCS0C : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear */ + __OM uint32_t INTCS1C : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t BRGOFC : 1; /*!< [16..16] Bridge Buffer overflow interrupt clear */ + uint32_t : 1; + __OM uint32_t BRGUFC : 1; /*!< [18..18] Bridge Buffer underflow interrupt clear */ + uint32_t : 1; + __OM uint32_t BUSERRC : 1; /*!< [20..20] AHB bus error interrupt clear */ + uint32_t : 7; + __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear */ + __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear */ + __OM uint32_t CASUCCS0C : 1; /*!< [30..30] Calibration success for slave0 interrupt clear */ + __OM uint32_t CASUCCS1C : 1; /*!< [31..31] Calibration success for slave1 interrupt clear */ + } INTC_b; + }; + + union + { + __IOM uint32_t INTE; /*!< (@ 0x00000198) xSPI Interrupt Enable Register */ + + struct + { + __IOM uint32_t CMDCMPE : 1; /*!< [0..0] Command Completed interrupt enable */ + __IOM uint32_t PATCMPE : 1; /*!< [1..1] Pattern Completed interrupt enable */ + __IOM uint32_t INICMPE : 1; /*!< [2..2] Initial Sequence Completed interrupt enable */ + __IOM uint32_t PERTOE : 1; /*!< [3..3] Periodic transaction timeout interrupt enable */ + __IOM uint32_t DSTOCS0E : 1; /*!< [4..4] DS timeout for slave0 interrupt enable */ + __IOM uint32_t DSTOCS1E : 1; /*!< [5..5] DS timeout for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t ECSCS0E : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable */ + __IOM uint32_t ECSCS1E : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t INTCS0E : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable */ + __IOM uint32_t INTCS1E : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t BRGOFE : 1; /*!< [16..16] Bridge Buffer overflow interrupt enable */ + uint32_t : 1; + __IOM uint32_t BRGUFE : 1; /*!< [18..18] Bridge Buffer underflow interrupt enable */ + uint32_t : 1; + __IOM uint32_t BUSERRE : 1; /*!< [20..20] AHB bus error interrupt enable */ + uint32_t : 7; + __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable */ + __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable */ + __IOM uint32_t CASUCCS0E : 1; /*!< [30..30] Calibration success for slave0 interrupt enable */ + __IOM uint32_t CASUCCS1E : 1; /*!< [31..31] Calibration success for slave1 interrupt enable */ + } INTE_b; + }; +} R_XSPI0_Type; /*!< Size = 412 (0x19c) */ + +/* =========================================================================================================================== */ +/* ================ R_MBXSEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Mailbox and Semaphore (R_MBXSEM) + */ + +typedef struct /*!< (@ 0x80240000) R_MBXSEM Structure */ +{ + union + { + __IOM uint32_t SEM[8]; /*!< (@ 0x00000000) Semaphore Register [0..7] */ + + struct + { + __IOM uint32_t SEM : 1; /*!< [0..0] Semaphore bit */ + uint32_t : 31; + } SEM_b[8]; + }; + + union + { + __IOM uint32_t SEMRCEN; /*!< (@ 0x00000020) Semaphore Read Clear Enable Register */ + + struct + { + __IOM uint32_t SEMRCEN0 : 1; /*!< [0..0] SEMRCEN0 */ + __IOM uint32_t SEMRCEN1 : 1; /*!< [1..1] SEMRCEN1 */ + __IOM uint32_t SEMRCEN2 : 1; /*!< [2..2] SEMRCEN2 */ + __IOM uint32_t SEMRCEN3 : 1; /*!< [3..3] SEMRCEN3 */ + __IOM uint32_t SEMRCEN4 : 1; /*!< [4..4] SEMRCEN4 */ + __IOM uint32_t SEMRCEN5 : 1; /*!< [5..5] SEMRCEN5 */ + __IOM uint32_t SEMRCEN6 : 1; /*!< [6..6] SEMRCEN6 */ + __IOM uint32_t SEMRCEN7 : 1; /*!< [7..7] SEMRCEN7 */ + uint32_t : 24; + } SEMRCEN_b; + }; + __IM uint32_t RESERVED[7]; + + union + { + __IM uint32_t MBXH2C[4]; /*!< (@ 0x00000040) Host to CR52 Mailbox Register [0..3] */ + + struct + { + __IM uint32_t MBX : 32; /*!< [31..0] MBX */ + } MBXH2C_b[4]; + }; + + union + { + __IM uint32_t MBXISETH2C; /*!< (@ 0x00000050) Host to CR52 Mailbox Interrupt Set Register */ + + struct + { + __IM uint32_t MBX_INT0S : 1; /*!< [0..0] Generates or indicates MBX_INT0 interrupt of mailbox + * from external host CPU to internal Cortex-R52. */ + __IM uint32_t MBX_INT1S : 1; /*!< [1..1] Generates or indicates MBX_INT1 interrupt of mailbox + * from external host CPU to internal Cortex-R52. */ + __IM uint32_t MBX_INT2S : 1; /*!< [2..2] Generates or indicates MBX_INT2 interrupt of mailbox + * from external host CPU to internal Cortex-R52. */ + __IM uint32_t MBX_INT3S : 1; /*!< [3..3] Generates or indicates MBX_INT3 interrupt of mailbox + * from external host CPU to internal Cortex-R52. */ + uint32_t : 28; + } MBXISETH2C_b; + }; + + union + { + __IOM uint32_t MBXICLRH2C; /*!< (@ 0x00000054) Host to CR52 Mailbox Interrupt Clear Register */ + + struct + { + __IOM uint32_t MBX_INT0C : 1; /*!< [0..0] Clears or indicates MBX_INT0 interrupt of mailbox from + * external host CPU to internal Cortex-R52. */ + __IOM uint32_t MBX_INT1C : 1; /*!< [1..1] Clears or indicates MBX_INT1 interrupt of mailbox from + * external host CPU to internal Cortex-R52. */ + __IOM uint32_t MBX_INT2C : 1; /*!< [2..2] Clears or indicates MBX_INT2 interrupt of mailbox from + * external host CPU to internal Cortex-R52. */ + __IOM uint32_t MBX_INT3C : 1; /*!< [3..3] Clears or indicates MBX_INT3 interrupt of mailbox from + * external host CPU to internal Cortex-R52. */ + uint32_t : 28; + } MBXICLRH2C_b; + }; + __IM uint32_t RESERVED1[10]; + + union + { + __IOM uint32_t MBXC2H[4]; /*!< (@ 0x00000080) CR52 to Host Mailbox Register [0..3] */ + + struct + { + __IOM uint32_t MBX : 32; /*!< [31..0] MBX */ + } MBXC2H_b[4]; + }; + + union + { + __IOM uint32_t MBXISETC2H; /*!< (@ 0x00000090) CR52 to Host Mailbox Interrupt Set Register */ + + struct + { + __IOM uint32_t MBX_HINT0S : 1; /*!< [0..0] Generates or indicates MBX_HINT0 interrupt of mailbox + * from internal Cortex-R52 to external host CPU. */ + __IOM uint32_t MBX_HINT1S : 1; /*!< [1..1] Generates or indicates MBX_HINT1 interrupt of mailbox + * from internal Cortex-R52 to external host CPU. */ + __IOM uint32_t MBX_HINT2S : 1; /*!< [2..2] Generates or indicates MBX_HINT2 interrupt of mailbox + * from internal Cortex-R52 to external host CPU. */ + __IOM uint32_t MBX_HINT3S : 1; /*!< [3..3] Generates or indicates MBX_HINT3 interrupt of mailbox + * from internal Cortex-R52 to external host CPU. */ + uint32_t : 28; + } MBXISETC2H_b; + }; + + union + { + __IM uint32_t MBXICLRC2H; /*!< (@ 0x00000094) CR52 to Host Mailbox Interrupt Clear Register */ + + struct + { + __IM uint32_t MBX_HINT0C : 1; /*!< [0..0] Clears or indicates MBX_HINT0 interrupt of mailbox from + * internal Cortex-R52 to external host CPU. */ + __IM uint32_t MBX_HINT1C : 1; /*!< [1..1] Clears or indicates MBX_HINT1 interrupt of mailbox from + * internal Cortex-R52 to external host CPU. */ + __IM uint32_t MBX_HINT2C : 1; /*!< [2..2] Clears or indicates MBX_HINT2 interrupt of mailbox from + * internal Cortex-R52 to external host CPU. */ + __IM uint32_t MBX_HINT3C : 1; /*!< [3..3] Clears or indicates MBX_HINT3 interrupt of mailbox from + * internal Cortex-R52 to external host CPU. */ + uint32_t : 28; + } MBXICLRC2H_b; + }; +} R_MBXSEM_Type; /*!< Size = 152 (0x98) */ + +/* =========================================================================================================================== */ +/* ================ R_SHOSTIF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Host Interface (R_SHOSTIF) + */ + +typedef struct /*!< (@ 0x80241000) R_SHOSTIF Structure */ +{ + union + { + __IOM uint32_t CTRLR0; /*!< (@ 0x00000000) Control Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t SCPH : 1; /*!< [8..8] Serial Clock Phase */ + __IOM uint32_t SCPOL : 1; /*!< [9..9] Serial Clock Polarity */ + uint32_t : 22; + } CTRLR0_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t ENR; /*!< (@ 0x00000008) Enable Register */ + + struct + { + __IOM uint32_t ENABLE : 1; /*!< [0..0] SHOSTIF Enable */ + uint32_t : 31; + } ENR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t RXFBTR; /*!< (@ 0x00000014) Receive FIFO Burst Threshold Register */ + + struct + { + __IOM uint32_t RXFBTL : 6; /*!< [5..0] Receive FIFO Burst Threshold */ + uint32_t : 26; + } RXFBTR_b; + }; + + union + { + __IOM uint32_t TXFTLR; /*!< (@ 0x00000018) Transmit FIFO Threshold Level Register */ + + struct + { + __IOM uint32_t TFT : 6; /*!< [5..0] Transmit FIFO Threshold */ + uint32_t : 26; + } TXFTLR_b; + }; + + union + { + __IOM uint32_t RXFTLR; /*!< (@ 0x0000001C) Receive FIFO Threshold Level Register */ + + struct + { + __IOM uint32_t RFT : 6; /*!< [5..0] Receive FIFO Threshold */ + uint32_t : 26; + } RXFTLR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IM uint32_t SR; /*!< (@ 0x00000028) Status Register */ + + struct + { + __IM uint32_t BUSY : 1; /*!< [0..0] Busy Flag */ + uint32_t : 31; + } SR_b; + }; + + union + { + __IOM uint32_t IMR; /*!< (@ 0x0000002C) Interrupt Mask Register */ + + struct + { + __IOM uint32_t TXEIM : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Mask */ + uint32_t : 2; + __IOM uint32_t RXOIM : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Mask */ + __IOM uint32_t RXFIM : 1; /*!< [4..4] Receive FIFO Full Interrupt Mask */ + uint32_t : 2; + __IOM uint32_t TXUIM : 1; /*!< [7..7] Transmit FIFO Underflow Mask */ + __IOM uint32_t AHBEM : 1; /*!< [8..8] AHB Error Interrupt Mask */ + __IOM uint32_t SPIMEM : 1; /*!< [9..9] SPI Master Error Interrupt Mask */ + uint32_t : 22; + } IMR_b; + }; + + union + { + __IM uint32_t ISR; /*!< (@ 0x00000030) Interrupt Status Register */ + + struct + { + __IM uint32_t TXEIS : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Status */ + uint32_t : 2; + __IM uint32_t RXOIS : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Status */ + __IM uint32_t RXFIS : 1; /*!< [4..4] Receive FIFO Full Interrupt Status */ + uint32_t : 2; + __IM uint32_t TXUIS : 1; /*!< [7..7] Transmit FIFO Underflow Status */ + __IM uint32_t AHBES : 1; /*!< [8..8] AHB Error Interrupt Status */ + __IM uint32_t SPIMES : 1; /*!< [9..9] SPI Master Error Interrupt Status */ + uint32_t : 22; + } ISR_b; + }; + + union + { + __IM uint32_t RISR; /*!< (@ 0x00000034) Raw Interrupt Status Register */ + + struct + { + __IM uint32_t TXEIR : 1; /*!< [0..0] Transmit FIFO Empty Raw Interrupt Status */ + uint32_t : 2; + __IM uint32_t RXOIR : 1; /*!< [3..3] Receive FIFO Overflow Raw Interrupt Status */ + __IM uint32_t RXFIR : 1; /*!< [4..4] Receive FIFO Full Raw Interrupt Status */ + uint32_t : 2; + __IM uint32_t TXUIR : 1; /*!< [7..7] Transmit FIFO Underflow Raw Interrupt Status */ + __IM uint32_t AHBER : 1; /*!< [8..8] AHB Error Raw Interrupt Status */ + __IM uint32_t SPIMER : 1; /*!< [9..9] SPI Master Error Raw Interrupt Status */ + uint32_t : 22; + } RISR_b; + }; + + union + { + __IM uint32_t TXUICR; /*!< (@ 0x00000038) Transmit FIFO Underflow Interrupt Clear Register */ + + struct + { + __IM uint32_t TXUICR : 1; /*!< [0..0] Clear Transmit FIFO Underflow Interrupt */ + uint32_t : 31; + } TXUICR_b; + }; + + union + { + __IM uint32_t RXOICR; /*!< (@ 0x0000003C) Receive FIFO Overflow Interrupt Clear Register */ + + struct + { + __IM uint32_t RXOICR : 1; /*!< [0..0] Clear Receive FIFO Overflow Interrupt */ + uint32_t : 31; + } RXOICR_b; + }; + + union + { + __IM uint32_t SPIMECR; /*!< (@ 0x00000040) SPI Master Interrupt Clear Register */ + + struct + { + __IM uint32_t SPIMECR : 1; /*!< [0..0] Clear SPI Master Error interrupt */ + uint32_t : 31; + } SPIMECR_b; + }; + + union + { + __IM uint32_t AHBECR; /*!< (@ 0x00000044) AHB Error Clear Register */ + + struct + { + __IM uint32_t AHBECR : 1; /*!< [0..0] Clear AHB Error Interrupt */ + uint32_t : 31; + } AHBECR_b; + }; + + union + { + __IM uint32_t ICR; /*!< (@ 0x00000048) Interrupt Clear Register */ + + struct + { + __IM uint32_t ICR : 1; /*!< [0..0] Clear Interrupts */ + uint32_t : 31; + } ICR_b; + }; +} R_SHOSTIF_Type; /*!< Size = 76 (0x4c) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSC_NS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Control for Non-safety region (R_SYSC_NS) + */ + +typedef struct /*!< (@ 0x80280000) R_SYSC_NS Structure */ +{ + union + { + __IOM uint32_t SCKCR; /*!< (@ 0x00000000) System Clock Control Register */ + + struct + { + __IOM uint32_t FSELXSPI0 : 3; /*!< [2..0] Set the frequency of the clock provided to xSPI Unit + * 0 in combination with bit 6 (DIVSELXSPI0). The combination + * is shown below. */ + uint32_t : 3; + __IOM uint32_t DIVSELXSPI0 : 1; /*!< [6..6] Select the base clock to generate serial clock for xSPI + * Unit 0 */ + uint32_t : 1; + __IOM uint32_t FSELXSPI1 : 3; /*!< [10..8] Set the frequency of the clock provided to xSPI Unit + * 1 in combination with bit 14 (DIVSELXSPI1). */ + uint32_t : 3; + __IOM uint32_t DIVSELXSPI1 : 1; /*!< [14..14] Select the base clock to generate serial clock for + * xSPI Unit 1 */ + uint32_t : 1; + __IOM uint32_t CKIO : 3; /*!< [18..16] Set the frequency of the external bus clock (CKIO) + * and the clock supplied to BSC in combination with the DIVSELSUB + * in the SCKCR2 register. The combination is shown below. */ + uint32_t : 1; + __IOM uint32_t FSELCANFD : 1; /*!< [20..20] Select the frequency of the clock supplied to CANFD */ + __IOM uint32_t PHYSEL : 1; /*!< [21..21] Select the Ethernet PHY reference clock output (ETHn_REFCLK, + * n = 0 to 2) */ + __IOM uint32_t CLMASEL : 1; /*!< [22..22] Select alternative clock when main clock abnormal oscillation + * is detected in CLMA3 */ + uint32_t : 1; + __IOM uint32_t SPI0ASYNCSEL : 1; /*!< [24..24] Select clock frequency when asynchronous serial clock + * is selected in SPI0 */ + __IOM uint32_t SPI1ASYNCSEL : 1; /*!< [25..25] Select clock frequency when asynchronous serial clock + * is selected in SPI1 */ + __IOM uint32_t SPI2ASYNCSEL : 1; /*!< [26..26] Select clock frequency when asynchronous serial clock + * is selected in SPI2 */ + __IOM uint32_t SCI0ASYNCSEL : 1; /*!< [27..27] Select clock frequency when asynchronous serial clock + * is selected in SCI0 */ + __IOM uint32_t SCI1ASYNCSEL : 1; /*!< [28..28] Select clock frequency when asynchronous serial clock + * is selected in SCI1 */ + __IOM uint32_t SCI2ASYNCSEL : 1; /*!< [29..29] Select clock frequency when asynchronous serial clock + * is selected in SCI2 */ + __IOM uint32_t SCI3ASYNCSEL : 1; /*!< [30..30] Select clock frequency when asynchronous serial clock + * is selected in SCI3 */ + __IOM uint32_t SCI4ASYNCSEL : 1; /*!< [31..31] Select clock frequency when asynchronous serial clock + * is selected in SCI4 */ + } SCKCR_b; + }; + __IM uint32_t RESERVED[127]; + + union + { + __IOM uint32_t RSTSR0; /*!< (@ 0x00000200) Reset Status Register 0 */ + + struct + { + uint32_t : 1; + __IOM uint32_t TRF : 1; /*!< [1..1] RES# Pin Reset Detect Flag */ + __IOM uint32_t ERRF : 1; /*!< [2..2] Error Reset Detect Flag */ + __IOM uint32_t SWRSF : 1; /*!< [3..3] System Software Reset Detect Flag */ + __IOM uint32_t SWR0F : 1; /*!< [4..4] CPU0 Software Reset Detect Flag */ + uint32_t : 27; + } RSTSR0_b; + }; + __IM uint32_t RESERVED1[15]; + + union + { + __IOM uint32_t MRCTLA; /*!< (@ 0x00000240) Module Reset Control Register A */ + + struct + { + uint32_t : 4; + __IOM uint32_t MRCTLA04 : 1; /*!< [4..4] xSPI Unit 0 Reset Control */ + __IOM uint32_t MRCTLA05 : 1; /*!< [5..5] xSPI Unit 1 Reset Control */ + uint32_t : 26; + } MRCTLA_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MRCTLE; /*!< (@ 0x00000250) Module Reset Control Register E */ + + struct + { + __IOM uint32_t MRCTLE00 : 1; /*!< [0..0] GMAC (PCLKH clock domain) Reset Control */ + __IOM uint32_t MRCTLE01 : 1; /*!< [1..1] GMAC (PCLKM clock domain) Reset Control */ + uint32_t : 1; + __IOM uint32_t MRCTLE03 : 1; /*!< [3..3] ESC (Bus clock domain) Reset Control */ + __IOM uint32_t MRCTLE04 : 1; /*!< [4..4] ESC (IP clock domain) Reset Control */ + __IOM uint32_t MRCTLE05 : 1; /*!< [5..5] Ethernet Subsystem Register Reset Control */ + __IOM uint32_t MRCTLE06 : 1; /*!< [6..6] MII Converter Reset Control */ + uint32_t : 25; + } MRCTLE_b; + }; + __IM uint32_t RESERVED3[4]; + + union + { + __IOM uint32_t MRCTLJ; /*!< (@ 0x00000264) Module Reset Control Register J */ + + struct + { + __IOM uint32_t MRCTLJ00 : 1; /*!< [0..0] AFMT0 Reset Control */ + __IOM uint32_t MRCTLJ01 : 1; /*!< [1..1] HDSL0 Reset Control */ + __IOM uint32_t MRCTLJ02 : 1; /*!< [2..2] BISS0 Reset Control */ + __IOM uint32_t MRCTLJ03 : 1; /*!< [3..3] ENDAT0 Reset Control */ + uint32_t : 28; + } MRCTLJ_b; + }; + + union + { + __IOM uint32_t MRCTLK; /*!< (@ 0x00000268) Module Reset Control Register K */ + + struct + { + __IOM uint32_t MRCTLK00 : 1; /*!< [0..0] AFMT1 Reset Control */ + __IOM uint32_t MRCTLK01 : 1; /*!< [1..1] HDSL1 Reset Control */ + __IOM uint32_t MRCTLK02 : 1; /*!< [2..2] BISS1 Reset Control */ + __IOM uint32_t MRCTLK03 : 1; /*!< [3..3] ENDAT1 Reset Control */ + uint32_t : 28; + } MRCTLK_b; + }; + __IM uint32_t RESERVED4[37]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000300) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPCRA00 : 1; /*!< [0..0] BSC Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPCRA04 : 1; /*!< [4..4] xSPI Unit 0 Module Stop */ + __IOM uint32_t MSTPCRA05 : 1; /*!< [5..5] xSPI Unit 1 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPCRA08 : 1; /*!< [8..8] SCI Unit 0 Module Stop */ + __IOM uint32_t MSTPCRA09 : 1; /*!< [9..9] SCI Unit 1 Module Stop */ + __IOM uint32_t MSTPCRA10 : 1; /*!< [10..10] SCI Unit 2 Module Stop */ + __IOM uint32_t MSTPCRA11 : 1; /*!< [11..11] SCI Unit 3 Module Stop */ + __IOM uint32_t MSTPCRA12 : 1; /*!< [12..12] SCI Unit 4 Module Stop */ + uint32_t : 19; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000304) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPCRB00 : 1; /*!< [0..0] IIC Unit 0 Module Stop */ + __IOM uint32_t MSTPCRB01 : 1; /*!< [1..1] IIC Unit 1 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPCRB04 : 1; /*!< [4..4] SPI Unit 0 Module Stop */ + __IOM uint32_t MSTPCRB05 : 1; /*!< [5..5] SPI Unit 1 Module Stop */ + __IOM uint32_t MSTPCRB06 : 1; /*!< [6..6] SPI Unit 2 Module Stop */ + uint32_t : 25; + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000308) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPCRC00 : 1; /*!< [0..0] MTU3 Module Stop */ + __IOM uint32_t MSTPCRC01 : 1; /*!< [1..1] GPT Unit 0 Module Stop */ + __IOM uint32_t MSTPCRC02 : 1; /*!< [2..2] GPT Unit 1 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPCRC05 : 1; /*!< [5..5] TFU Module Stop */ + __IOM uint32_t MSTPCRC06 : 1; /*!< [6..6] ADC12 Unit 0 Module Stop */ + __IOM uint32_t MSTPCRC07 : 1; /*!< [7..7] ADC12 Unit 1 Module Stop */ + uint32_t : 24; + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000030C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPCRD00 : 1; /*!< [0..0] DSMIF Unit 0 Module Stop */ + __IOM uint32_t MSTPCRD01 : 1; /*!< [1..1] DSMIF Unit 1 Module Stop */ + __IOM uint32_t MSTPCRD02 : 1; /*!< [2..2] CMT Unit 0 Module Stop */ + __IOM uint32_t MSTPCRD03 : 1; /*!< [3..3] CMT Unit 1 Module Stop */ + __IOM uint32_t MSTPCRD04 : 1; /*!< [4..4] CMT Unit 2 Module Stop */ + __IOM uint32_t MSTPCRD05 : 1; /*!< [5..5] CMTW Unit 0 Module Stop */ + __IOM uint32_t MSTPCRD06 : 1; /*!< [6..6] CMTW Unit 1 Module Stop */ + __IOM uint32_t MSTPCRD07 : 1; /*!< [7..7] TSU Module Stop */ + __IOM uint32_t MSTPCRD08 : 1; /*!< [8..8] DOC Module Stop */ + __IOM uint32_t MSTPCRD09 : 1; /*!< [9..9] CRC Unit 0 Module Stop */ + __IOM uint32_t MSTPCRD10 : 1; /*!< [10..10] CANFD Module Stop */ + __IOM uint32_t MSTPCRD11 : 1; /*!< [11..11] CKIO Module Stop */ + uint32_t : 20; + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000310) Module Stop Control Register E */ + + struct + { + __IOM uint32_t MSTPCRE00 : 1; /*!< [0..0] GMAC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPCRE02 : 1; /*!< [2..2] ESC Module Stop */ + __IOM uint32_t MSTPCRE03 : 1; /*!< [3..3] Ethernet Subsystem Register Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPCRE08 : 1; /*!< [8..8] USB Module Stop */ + uint32_t : 23; + } MSTPCRE_b; + }; + __IM uint32_t RESERVED5[4]; + + union + { + __IOM uint32_t MSTPCRJ; /*!< (@ 0x00000324) Module Stop Control Register J */ + + struct + { + __IOM uint32_t MSTPCRJ00 : 1; /*!< [0..0] AFMT0 Module Stop */ + __IOM uint32_t MSTPCRJ01 : 1; /*!< [1..1] HDSL0 Module Stop */ + __IOM uint32_t MSTPCRJ02 : 1; /*!< [2..2] BISS0 Module Stop */ + __IOM uint32_t MSTPCRJ03 : 1; /*!< [3..3] ENDAT0 Module Stop */ + uint32_t : 28; + } MSTPCRJ_b; + }; + + union + { + __IOM uint32_t MSTPCRK; /*!< (@ 0x00000328) Module Stop Control Register K */ + + struct + { + __IOM uint32_t MSTPCRK00 : 1; /*!< [0..0] AFMT1 Module Stop */ + __IOM uint32_t MSTPCRK01 : 1; /*!< [1..1] HDSL1 Module Stop */ + __IOM uint32_t MSTPCRK02 : 1; /*!< [2..2] BISS1 Module Stop */ + __IOM uint32_t MSTPCRK03 : 1; /*!< [3..3] ENDAT1 Module Stop */ + uint32_t : 28; + } MSTPCRK_b; + }; + + union + { + __IOM uint32_t MSTPCRL; /*!< (@ 0x0000032C) Module Stop Control Register L */ + + struct + { + __IOM uint32_t MSTPCRL00 : 1; /*!< [0..0] ENCOUT Module Stop */ + uint32_t : 31; + } MSTPCRL_b; + }; + __IM uint32_t RESERVED6[884]; + + union + { + __IM uint32_t MD_MON; /*!< (@ 0x00001100) Operating Mode Monitor Register */ + + struct + { + __IM uint32_t MDDMON : 1; /*!< [0..0] MDD status flag */ + uint32_t : 11; + __IM uint32_t MD0MON : 1; /*!< [12..12] MD0 pin status flag */ + __IM uint32_t MD1MON : 1; /*!< [13..13] MD1 pin status flag */ + __IM uint32_t MD2MON : 1; /*!< [14..14] MD2 pin status flag */ + uint32_t : 1; + __IM uint32_t MDV0MON : 1; /*!< [16..16] MDV0 status flag (ETH0 domain) */ + __IM uint32_t MDV1MON : 1; /*!< [17..17] MDV1 status flag (ETH1 domain) */ + __IM uint32_t MDV2MON : 1; /*!< [18..18] MDV2 status flag (ETH2 domain) */ + __IM uint32_t MDV3MON : 1; /*!< [19..19] MDV3 status flag (xSPI0 domain) */ + __IM uint32_t MDV4MON : 1; /*!< [20..20] MDV4 status flag (xSPI1 domain) */ + uint32_t : 11; + } MD_MON_b; + }; +} R_SYSC_NS_Type; /*!< Size = 4356 (0x1104) */ + +/* =========================================================================================================================== */ +/* ================ R_ELO ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Evnet Link Option Setting (R_ELO) + */ + +typedef struct /*!< (@ 0x80281200) R_ELO Structure */ +{ + union + { + __IOM uint32_t ELOPA; /*!< (@ 0x00000000) Event Link Option Setting Register A */ + + struct + { + __IOM uint32_t MTU0MD : 2; /*!< [1..0] MTU0 Operation Select */ + uint32_t : 4; + __IOM uint32_t MTU3MD : 2; /*!< [7..6] MTU3 Operation Select */ + uint32_t : 24; + } ELOPA_b; + }; + + union + { + __IOM uint32_t ELOPB; /*!< (@ 0x00000004) Event Link Option Setting Register B */ + + struct + { + __IOM uint32_t MTU4MD : 2; /*!< [1..0] MTU4 Operation Select */ + uint32_t : 30; + } ELOPB_b; + }; +} R_ELO_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_ENCSS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Encoder Interface Subsystem (R_ENCSS) + */ + +typedef struct /*!< (@ 0x80281400) R_ENCSS Structure */ +{ + union + { + __IOM uint32_t ENCODER_CFG; /*!< (@ 0x00000000) Encoder IF Configuration Register */ + + struct + { + __IOM uint32_t HF0ENDIAN : 1; /*!< [0..0] HIPERFACE DSL Unit 0 Endian Mode */ + __IOM uint32_t HF0SAFE1SEL : 1; /*!< [1..1] HIPERFACE DSL Unit 0 Safe 1 Interface Select */ + __IOM uint32_t EVTSRC0 : 1; /*!< [2..2] Event Source Select */ + __IOM uint32_t SS0SEL : 2; /*!< [4..3] Encoder Interface Port Select */ + __IOM uint32_t TRGSEL0 : 1; /*!< [5..5] Trigger Source Select for Encoder Interface Subsystem + * Unit 1 */ + uint32_t : 10; + __IOM uint32_t HF1ENDIAN : 1; /*!< [16..16] HIPERFACE DSL Unit 1 Endian Mode */ + __IOM uint32_t HF1SAFE1SEL : 1; /*!< [17..17] HIPERFACE DSL Unit 1 Safe 1 Interface Select */ + __IOM uint32_t EVTSRC1 : 1; /*!< [18..18] Event Source Select */ + __IOM uint32_t SS1SEL : 2; /*!< [20..19] Encoder Interface Port Select */ + __IOM uint32_t TRGSEL1 : 1; /*!< [21..21] Trigger Source Select for Encoder Interface Unit 0 */ + uint32_t : 10; + } ENCODER_CFG_b; + }; + + union + { + __IM uint32_t BISS_STAT; /*!< (@ 0x00000004) BiSS-C Status Register */ + + struct + { + __IM uint32_t BISS0_ERR : 1; /*!< [0..0] BiSS-C Unit 0 Error */ + uint32_t : 3; + __IM uint32_t BISS0_EOT : 1; /*!< [4..4] End-of-Transmission from BiSS-C Unit 0 */ + uint32_t : 11; + __IM uint32_t BISS1_ERR : 1; /*!< [16..16] BiSS-C Unit 1 Error */ + uint32_t : 3; + __IM uint32_t BISS1_EOT : 1; /*!< [20..20] End-of-Transmission from BiSS-C Unit 1 */ + uint32_t : 11; + } BISS_STAT_b; + }; + + union + { + __IM uint32_t HDSL_STAT; /*!< (@ 0x00000008) HIPERFACE DSL Status Register */ + + struct + { + __IM uint32_t HDSL0_LINK : 1; /*!< [0..0] HIPERFACE-DSL Link */ + __IM uint32_t HDSL0_SYNCLCKD : 1; /*!< [1..1] HIPERFACE-DSL Sync Locked */ + uint32_t : 2; + __IM uint32_t HDSL0_ESTON : 1; /*!< [4..4] HIPERFACE-DSL Estimator ON */ + __IM uint32_t HDSL0_SCHERR : 1; /*!< [5..5] HIPERFACE-DSL Safe Channel Error */ + __IM uint32_t HDSL0_SPERR : 1; /*!< [6..6] HIPERFACE-DSL Safe Position Error */ + __IM uint32_t HDSL0_EDTERR : 1; /*!< [7..7] HIPERFACE-DSL Estimator Deviation Threshold Error */ + __IM uint32_t HDSL0_ACCERR : 1; /*!< [8..8] HIPERFACE-DSL Acceleration Error */ + __IM uint32_t HDSL0_ACTHERR : 1; /*!< [9..9] HIPERFACE-DSL Acceleration Threshold Error */ + __IM uint32_t HDSL0_ENCERR : 1; /*!< [10..10] HIPERFACE-DSL Encoding Error */ + uint32_t : 5; + __IM uint32_t HDSL1_LINK : 1; /*!< [16..16] HIPERFACE-DSL Link */ + __IM uint32_t HDSL1_SYNCLCKD : 1; /*!< [17..17] HIPERFACE-DSL Sync Locked */ + uint32_t : 2; + __IM uint32_t HDSL1_ESTON : 1; /*!< [20..20] HIPERFACE-DSL Estimator ON */ + __IM uint32_t HDSL1_SCHERR : 1; /*!< [21..21] HIPERFACE-DSL Safe Channel Error */ + __IM uint32_t HDSL1_SPERR : 1; /*!< [22..22] HIPERFACE-DSL Safe Position Error */ + __IM uint32_t HDSL1_EDTERR : 1; /*!< [23..23] HIPERFACE-DSL Estimator Deviation Threshold Error */ + __IM uint32_t HDSL1_ACCERR : 1; /*!< [24..24] HIPERFACE-DSL Acceleration Error */ + __IM uint32_t HDSL1_ACTHERR : 1; /*!< [25..25] HIPERFACE-DSL Acceleration Threshold Error */ + __IM uint32_t HDSL1_ENCERR : 1; /*!< [26..26] HIPERFACE-DSL Encoding Error */ + uint32_t : 5; + } HDSL_STAT_b; + }; + + union + { + __IOM uint32_t ENDAT_CFG; /*!< (@ 0x0000000C) EnDat Configuration Register */ + + struct + { + __IOM uint32_t ENDAT0_AXADD : 5; /*!< [4..0] EnDat Unit 0 Axis Address */ + uint32_t : 11; + __IOM uint32_t ENDAT1_AXADD : 5; /*!< [20..16] EnDat Unit 1 Axis Address */ + uint32_t : 11; + } ENDAT_CFG_b; + }; + + union + { + __IM uint32_t AFMT_STAT; /*!< (@ 0x00000010) A-Format Status Register */ + + struct + { + __IM uint32_t AFMT0_BUSY : 1; /*!< [0..0] A-format Busy */ + __IM uint32_t AFMT0_EOT : 1; /*!< [1..1] A-format End-Of-Frame */ + __IM uint32_t AFMT0_TMOUT : 1; /*!< [2..2] A-format Timeout */ + uint32_t : 13; + __IM uint32_t AFMT1_BUSY : 1; /*!< [16..16] A-format Busy */ + __IM uint32_t AFMT1_EOT : 1; /*!< [17..17] A-format End-of-Frame */ + __IM uint32_t AFMT1_TMOUT : 1; /*!< [18..18] A-format Timeout */ + uint32_t : 13; + } AFMT_STAT_b; + }; + + union + { + __IM uint32_t HDSL0_OS_D; /*!< (@ 0x00000014) HIPERFACE_DSL (SSn) Online Status (Drive) Register */ + + struct + { + uint32_t : 1; + __IM uint32_t FREL : 1; /*!< [1..1] Channel Status for long message */ + __IM uint32_t QMLW : 1; /*!< [2..2] Quality monitoring at Low level */ + uint32_t : 1; + __IM uint32_t ANS : 1; /*!< [4..4] Incorrect Answer Detected */ + __IM uint32_t MIN : 1; /*!< [5..5] Acknowledgment of Message Initialization */ + __IM uint32_t POSTX : 2; /*!< [7..6] Position Transmission Status */ + __IM uint32_t PRST : 1; /*!< [8..8] Protocol Reset */ + __IM uint32_t DTE : 1; /*!< [9..9] Deviation Threshold Error */ + uint32_t : 1; + __IM uint32_t POS : 1; /*!< [11..11] Estimator Turned On */ + uint32_t : 2; + __IM uint32_t SUM : 1; /*!< [14..14] Summary Byte */ + __IM uint32_t INT : 1; /*!< [15..15] Status of the Interrupt Output */ + uint32_t : 16; + } HDSL0_OS_D_b; + }; + + union + { + __IM uint32_t HDSL0_OS_1; /*!< (@ 0x00000018) HIPERFACE_DSL (SS0) Online Status (Safe1) Register */ + + struct + { + __IM uint32_t FRES : 1; /*!< [0..0] Channel Status for the short message */ + uint32_t : 1; + __IM uint32_t QMLW : 1; /*!< [2..2] Quality Monitoring at Low level */ + uint32_t : 2; + __IM uint32_t MIN : 1; /*!< [5..5] Acknowledgment of Message Initialization */ + __IM uint32_t POSTX : 2; /*!< [7..6] Position Transmission Status */ + __IM uint32_t PRST : 1; /*!< [8..8] Protocol Reset */ + uint32_t : 1; + __IM uint32_t VPOS : 1; /*!< [10..10] Safe Position Invalid */ + uint32_t : 2; + __IM uint32_t SCE : 1; /*!< [13..13] CRC Error on the Safe Channel */ + __IM uint32_t SSUM : 1; /*!< [14..14] Safe Summary Bit */ + __IM uint32_t SINT : 1; /*!< [15..15] Status of the Interrupt Output */ + uint32_t : 16; + } HDSL0_OS_1_b; + }; + + union + { + __IM uint32_t HDSL0_OS_2; /*!< (@ 0x0000001C) HIPERFACE_DSL (SS0) Online Status (Safe2) Register */ + + struct + { + uint32_t : 2; + __IM uint32_t QMLW : 1; /*!< [2..2] Quality Monitoring at Low level */ + uint32_t : 3; + __IM uint32_t POSTX : 2; /*!< [7..6] Position Transmission Status */ + __IM uint32_t PRST : 1; /*!< [8..8] Protocol Reset */ + uint32_t : 1; + __IM uint32_t VPOS2 : 1; /*!< [10..10] Safe Position 2 Invalid */ + uint32_t : 2; + __IM uint32_t SCE2 : 1; /*!< [13..13] Transmission Error Channel 2 */ + __IM uint32_t SSUM2 : 1; /*!< [14..14] Summary Bit Channel 2 */ + uint32_t : 17; + } HDSL0_OS_2_b; + }; + + union + { + __IM uint32_t HDSL1_OS_D; /*!< (@ 0x00000020) HIPERFACE_DSL (SSn) Online Status (Drive) Register */ + + struct + { + uint32_t : 1; + __IM uint32_t FREL : 1; /*!< [1..1] Channel Status for long message */ + __IM uint32_t QMLW : 1; /*!< [2..2] Quality monitoring at Low level */ + uint32_t : 1; + __IM uint32_t ANS : 1; /*!< [4..4] Incorrect Answer Detected */ + __IM uint32_t MIN : 1; /*!< [5..5] Acknowledgment of Message Initialization */ + __IM uint32_t POSTX : 2; /*!< [7..6] Position Transmission Status */ + __IM uint32_t PRST : 1; /*!< [8..8] Protocol Reset */ + __IM uint32_t DTE : 1; /*!< [9..9] Deviation Threshold Error */ + uint32_t : 1; + __IM uint32_t POS : 1; /*!< [11..11] Estimator Turned On */ + uint32_t : 2; + __IM uint32_t SUM : 1; /*!< [14..14] Summary Byte */ + __IM uint32_t INT : 1; /*!< [15..15] Status of the Interrupt Output */ + uint32_t : 16; + } HDSL1_OS_D_b; + }; +} R_ENCSS_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_RWP_NS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Register Write Protection for Non-safety Area (R_RWP_NS) + */ + +typedef struct /*!< (@ 0x80281A10) R_RWP_NS Structure */ +{ + union + { + __IOM uint32_t PRCRN; /*!< (@ 0x00000000) Non_Safety Area Protect Register */ + + struct + { + __IOM uint32_t PRC0 : 1; /*!< [0..0] Protect 0 */ + __IOM uint32_t PRC1 : 1; /*!< [1..1] Protect 1 */ + __IOM uint32_t PRC2 : 1; /*!< [2..2] Protect 2 */ + __IOM uint32_t PRC3 : 1; /*!< [3..3] Protect 3 */ + uint32_t : 4; + __OM uint32_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + uint32_t : 16; + } PRCRN_b; + }; +} R_RWP_NS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Real Time Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x81009000) R_RTC Structure */ +{ + union + { + __IOM uint32_t RTCA0CTL0; /*!< (@ 0x00000000) RTC Control Register 0 */ + + struct + { + uint32_t : 4; + __IOM uint32_t RTCA0SLSB : 1; /*!< [4..4] RTCA0SCMP enable/disable setting */ + __IOM uint32_t RTCA0AMPM : 1; /*!< [5..5] RTCA0HOUR, RTCA0ALH display format selection bit */ + __IM uint32_t RTCA0CEST : 1; /*!< [6..6] RTC Controller Enable Status */ + __IOM uint32_t RTCA0CE : 1; /*!< [7..7] RTC Controller Enable Bit */ + uint32_t : 24; + } RTCA0CTL0_b; + }; + + union + { + __IOM uint32_t RTCA0CTL1; /*!< (@ 0x00000004) RTC Control Register 1 */ + + struct + { + __IOM uint32_t RTCA0CT : 3; /*!< [2..0] Fixed interval interrupt (RTC_PRD) output setting bit */ + __IOM uint32_t RTCA01SE : 1; /*!< [3..3] 1 second interrupt (RTC_1S) output enable bit */ + __IOM uint32_t RTCA0ALME : 1; /*!< [4..4] Alarm interrupt (RTC_ALM) output enable bit */ + __IOM uint32_t RTCA01HZE : 1; /*!< [5..5] This bit enables/disables 1 Hz pulse output (RTCAT1HZ). */ + uint32_t : 26; + } RTCA0CTL1_b; + }; + + union + { + __IOM uint32_t RTCA0CTL2; /*!< (@ 0x00000008) RTC Control Register 2 */ + + struct + { + __IOM uint32_t RTCA0WAIT : 1; /*!< [0..0] RTC Controller Counter Wait Control */ + __IM uint32_t RTCA0WST : 1; /*!< [1..1] RTC Controller Counter Wait Status */ + __IOM uint32_t RTCA0RSUB : 1; /*!< [2..2] RTCA0SUBC Data Transfer Control */ + __IM uint32_t RTCA0RSST : 1; /*!< [3..3] RTCA0SRBU Transfer Status */ + __IM uint32_t RTCA0WSST : 1; /*!< [4..4] RTCA0SCMP Write Status */ + uint32_t : 27; + } RTCA0CTL2_b; + }; + + union + { + __IM uint32_t RTCA0SUBC; /*!< (@ 0x0000000C) RTC Sub Count Register */ + + struct + { + __IM uint32_t RTCA0SUBC : 22; /*!< [21..0] Register that counts the 1 second reference time */ + uint32_t : 10; + } RTCA0SUBC_b; + }; + + union + { + __IM uint32_t RTCA0SRBU; /*!< (@ 0x00000010) RTC Sub Count Register Read Buffer */ + + struct + { + __IM uint32_t RTCA0SRBU : 22; /*!< [21..0] Read buffer register of RTCA0SUBC */ + uint32_t : 10; + } RTCA0SRBU_b; + }; + + union + { + __IOM uint32_t RTCA0SEC; /*!< (@ 0x00000014) RTC Sec Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0SEC : 7; /*!< [6..0] Buffer register to read/write RTC Second Count register + * (RTCA0SECC). */ + uint32_t : 25; + } RTCA0SEC_b; + }; + + union + { + __IOM uint32_t RTCA0MIN; /*!< (@ 0x00000018) RTC Min Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0MIN : 7; /*!< [6..0] Buffer register to read/write RTC Minute Count register + * (RTCA0MINC). */ + uint32_t : 25; + } RTCA0MIN_b; + }; + + union + { + __IOM uint32_t RTCA0HOUR; /*!< (@ 0x0000001C) RTC Hour Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0HOUR : 6; /*!< [5..0] Buffer register to read/write RTC Hour Count register + * (RTCA0HOURC). */ + uint32_t : 26; + } RTCA0HOUR_b; + }; + + union + { + __IOM uint32_t RTCA0WEEK; /*!< (@ 0x00000020) RTC Week Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0WEEK : 3; /*!< [2..0] Buffer register to read/write RTC Week Count register + * (RTCA0WEEKC). */ + uint32_t : 29; + } RTCA0WEEK_b; + }; + + union + { + __IOM uint32_t RTCA0DAY; /*!< (@ 0x00000024) RTC Day Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0DAY : 6; /*!< [5..0] Buffer register to read/write RTC Day Count register + * (RTCA0DAYC). */ + uint32_t : 26; + } RTCA0DAY_b; + }; + + union + { + __IOM uint32_t RTCA0MONTH; /*!< (@ 0x00000028) RTC Month Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0MONTH : 5; /*!< [4..0] Buffer register to read/write RTC Month Count register + * (RTCA0MONC). */ + uint32_t : 27; + } RTCA0MONTH_b; + }; + + union + { + __IOM uint32_t RTCA0YEAR; /*!< (@ 0x0000002C) RTC Year Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0YEAR : 8; /*!< [7..0] Buffer register to read/write RTC Year Count register + * (RTCA0YEARC). */ + uint32_t : 24; + } RTCA0YEAR_b; + }; + + union + { + __IOM uint32_t RTCA0TIME; /*!< (@ 0x00000030) RTC Time Set Register */ + + struct + { + __IOM uint32_t RTCA0SEC : 8; /*!< [7..0] See RTCA0SEC register */ + __IOM uint32_t RTCA0MIN : 8; /*!< [15..8] See RTCA0MIN register */ + __IOM uint32_t RTCA0HOUR : 8; /*!< [23..16] See RTCA0HOUR register */ + uint32_t : 8; + } RTCA0TIME_b; + }; + + union + { + __IOM uint32_t RTCA0CAL; /*!< (@ 0x00000034) RTC Calendar Set Register */ + + struct + { + __IOM uint32_t RTCA0WEEK : 8; /*!< [7..0] See RTCA0WEEK register */ + __IOM uint32_t RTCA0DAY : 8; /*!< [15..8] See RTCA0DAY register */ + __IOM uint32_t RTCA0MONTH : 8; /*!< [23..16] See RTCA0MONTH register */ + __IOM uint32_t RTCA0YEAR : 8; /*!< [31..24] See RTCA0YEAR register */ + } RTCA0CAL_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t RTCA0SCMP; /*!< (@ 0x0000003C) RTC Sub Count Compare Register */ + + struct + { + __IOM uint32_t RTCA0SCMP : 22; /*!< [21..0] Register that sets the compare value of RTCA0SUBC (sub-counter). */ + uint32_t : 10; + } RTCA0SCMP_b; + }; + + union + { + __IOM uint32_t RTCA0ALM; /*!< (@ 0x00000040) RTC Alarm Min Set Register */ + + struct + { + __IOM uint32_t RTCA0ALM : 7; /*!< [6..0] RTCA0ALM is a register that performs the minute setting + * for the alarm interrupt. */ + uint32_t : 25; + } RTCA0ALM_b; + }; + + union + { + __IOM uint32_t RTCA0ALH; /*!< (@ 0x00000044) RTC Alarm Hour Set Register */ + + struct + { + __IOM uint32_t RTCA0ALH : 6; /*!< [5..0] RTCA0ALH is a register that performs the hour setting + * for the alarm interrupt. */ + uint32_t : 26; + } RTCA0ALH_b; + }; + + union + { + __IOM uint32_t RTCA0ALW; /*!< (@ 0x00000048) RTC Alarm Week Set Register */ + + struct + { + __IOM uint32_t RTCA0ALW0 : 1; /*!< [0..0] Alarm interrupt day of the week setting bit 0 */ + __IOM uint32_t RTCA0ALW1 : 1; /*!< [1..1] Alarm interrupt day of the week setting bit 1 */ + __IOM uint32_t RTCA0ALW2 : 1; /*!< [2..2] Alarm interrupt day of the week setting bit 2 */ + __IOM uint32_t RTCA0ALW3 : 1; /*!< [3..3] Alarm interrupt day of the week setting bit 3 */ + __IOM uint32_t RTCA0ALW4 : 1; /*!< [4..4] Alarm interrupt day of the week setting bit 4 */ + __IOM uint32_t RTCA0ALW5 : 1; /*!< [5..5] Alarm interrupt day of the week setting bit 5 */ + __IOM uint32_t RTCA0ALW6 : 1; /*!< [6..6] Alarm interrupt day of the week setting bit 6 */ + uint32_t : 25; + } RTCA0ALW_b; + }; + + union + { + __IM uint32_t RTCA0SECC; /*!< (@ 0x0000004C) RTC Second Count Register */ + + struct + { + __IM uint32_t RTCA0SECC : 7; /*!< [6..0] Counts up the seconds */ + uint32_t : 25; + } RTCA0SECC_b; + }; + + union + { + __IM uint32_t RTCA0MINC; /*!< (@ 0x00000050) RTC Minute Count Register */ + + struct + { + __IM uint32_t RTCA0MINC : 7; /*!< [6..0] Counts up the minutes */ + uint32_t : 25; + } RTCA0MINC_b; + }; + + union + { + __IM uint32_t RTCA0HOURC; /*!< (@ 0x00000054) RTC Hour Count Register */ + + struct + { + __IM uint32_t RTCA0HOURC : 6; /*!< [5..0] Counts up the hours */ + uint32_t : 26; + } RTCA0HOURC_b; + }; + + union + { + __IM uint32_t RTCA0WEEKC; /*!< (@ 0x00000058) RTC Week Count Register */ + + struct + { + __IM uint32_t RTCA0WEEKC : 3; /*!< [2..0] Counts up the weeks */ + uint32_t : 29; + } RTCA0WEEKC_b; + }; + + union + { + __IM uint32_t RTCA0DAYC; /*!< (@ 0x0000005C) RTC Day Count Register */ + + struct + { + __IM uint32_t RTCA0DAYC : 6; /*!< [5..0] Counts up the days */ + uint32_t : 26; + } RTCA0DAYC_b; + }; + + union + { + __IM uint32_t RTCA0MONC; /*!< (@ 0x00000060) RTC Month Count Register */ + + struct + { + __IM uint32_t RTCA0MONC : 5; /*!< [4..0] Counts up the months */ + uint32_t : 27; + } RTCA0MONC_b; + }; + + union + { + __IM uint32_t RTCA0YEARC; /*!< (@ 0x00000064) RTC Year Count Register */ + + struct + { + __IM uint32_t RTCA0YEARC : 8; /*!< [7..0] Counts up the years */ + uint32_t : 24; + } RTCA0YEARC_b; + }; + + union + { + __IM uint32_t RTCA0TIMEC; /*!< (@ 0x00000068) RTC Time Count Register */ + + struct + { + __IM uint32_t RTCA0SECC : 8; /*!< [7..0] See RTCA0SECC register */ + __IM uint32_t RTCA0MINC : 8; /*!< [15..8] See RTCA0MINC register */ + __IM uint32_t RTCA0HOURC : 8; /*!< [23..16] See RTCA0HOURC register */ + uint32_t : 8; + } RTCA0TIMEC_b; + }; + + union + { + __IM uint32_t RTCA0CALC; /*!< (@ 0x0000006C) RTC Calendar Count Register */ + + struct + { + __IM uint32_t RTCA0WEEKC : 8; /*!< [7..0] See RTCA0WEEKC register */ + __IM uint32_t RTCA0DAYC : 8; /*!< [15..8] See RTCA0DAYC register */ + __IM uint32_t RTCA0MONC : 8; /*!< [23..16] See RTCA0MONC register */ + __IM uint32_t RTCA0YEARC : 8; /*!< [31..24] See RTCA0YEARC register */ + } RTCA0CALC_b; + }; +} R_RTC_Type; /*!< Size = 112 (0x70) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG2 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GPT Port Output Enable 2 (R_POEG2) + */ + +typedef struct /*!< (@ 0x8100A000) R_POEG2 Structure */ +{ + union + { + __IOM uint32_t POEG2GA; /*!< (@ 0x00000000) POEG2 Group A Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG2GA_b; + }; + __IM uint32_t RESERVED[255]; + + union + { + __IOM uint32_t POEG2GB; /*!< (@ 0x00000400) POEG2 Group B Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG2GB_b; + }; + __IM uint32_t RESERVED1[255]; + + union + { + __IOM uint32_t POEG2GC; /*!< (@ 0x00000800) POEG2 Group C Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG2GC_b; + }; + __IM uint32_t RESERVED2[255]; + + union + { + __IOM uint32_t POEG2GD; /*!< (@ 0x00000C00) POEG2 Group D Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG2GD_b; + }; +} R_POEG2_Type; /*!< Size = 3076 (0xc04) */ + +/* =========================================================================================================================== */ +/* ================ R_OTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief One-Time Programmable Memory (R_OTP) + */ + +typedef struct /*!< (@ 0x81028000) R_OTP Structure */ +{ + union + { + __IOM uint32_t OTPPWR; /*!< (@ 0x00000000) OTP Power Control Register */ + + struct + { + __IOM uint32_t PWR : 1; /*!< [0..0] OTP power on/off setting */ + uint32_t : 3; + __IOM uint32_t ACCL : 1; /*!< [4..4] Selects OTP access I/F */ + uint32_t : 27; + } OTPPWR_b; + }; + + union + { + __IOM uint32_t OTPSTR; /*!< (@ 0x00000004) OTP Access Status Register */ + + struct + { + __IM uint32_t CMD_RDY : 1; /*!< [0..0] Indicates whether OTP controller is ready to receive + * command or not. */ + __IM uint32_t ERR_WR : 2; /*!< [2..1] OTP write status */ + __IM uint32_t ERR_WP : 1; /*!< [3..3] Write protection error */ + __IM uint32_t ERR_RP : 1; /*!< [4..4] Read protection error */ + uint32_t : 3; + __IOM uint32_t ERR_RDY_WR : 1; /*!< [8..8] OTP write command ready error */ + __IOM uint32_t ERR_RDY_RD : 1; /*!< [9..9] OTP read command ready error */ + uint32_t : 5; + __IM uint32_t CNT_ST_IDLE : 1; /*!< [15..15] Indicates status of OTP controller */ + uint32_t : 16; + } OTPSTR_b; + }; + + union + { + __IOM uint32_t OTPSTAWR; /*!< (@ 0x00000008) OTP Write Command Register */ + + struct + { + __IOM uint32_t STAWR : 1; /*!< [0..0] OTP write start */ + uint32_t : 31; + } OTPSTAWR_b; + }; + + union + { + __IOM uint32_t OTPADRWR; /*!< (@ 0x0000000C) OTP Write Address Register */ + + struct + { + __IOM uint32_t ADRWR : 9; /*!< [8..0] OTP write address */ + uint32_t : 23; + } OTPADRWR_b; + }; + + union + { + __IOM uint32_t OTPDATAWR; /*!< (@ 0x00000010) OTP Write Data Register */ + + struct + { + __IOM uint32_t DATAWR : 16; /*!< [15..0] OTP write data */ + uint32_t : 16; + } OTPDATAWR_b; + }; + + union + { + __IOM uint32_t OTPADRRD; /*!< (@ 0x00000014) OTP Read Address Register */ + + struct + { + __IOM uint32_t ADRRD : 9; /*!< [8..0] OTP read address */ + uint32_t : 23; + } OTPADRRD_b; + }; + + union + { + __IM uint32_t OTPDATARD; /*!< (@ 0x00000018) OTP Read Data Register */ + + struct + { + __IM uint32_t DATARD : 16; /*!< [15..0] OTP read data */ + uint32_t : 16; + } OTPDATARD_b; + }; +} R_OTP_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== */ +/* ================ R_PTADR ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Address Selection (R_PTADR) + */ + +typedef struct /*!< (@ 0x81030C00) R_PTADR Structure */ +{ + union + { + __IOM uint8_t RSELP[25]; /*!< (@ 0x00000000) Port [0..24] Region Select Register */ + + struct + { + __IOM uint8_t RS0 : 1; /*!< [0..0] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS1 : 1; /*!< [1..1] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS2 : 1; /*!< [2..2] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS3 : 1; /*!< [3..3] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS4 : 1; /*!< [4..4] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS5 : 1; /*!< [5..5] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS6 : 1; /*!< [6..6] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS7 : 1; /*!< [7..7] Pm_n pin I/O port registers Region Select (n = bit position) */ + } RSELP_b[25]; + }; +} R_PTADR_Type; /*!< Size = 25 (0x19) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSRAM0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System SRAM 0 (R_SYSRAM0) + */ + +typedef struct /*!< (@ 0x81040000) R_SYSRAM0 Structure */ +{ + __IOM R_SYSRAM0_W_Type W[4]; /*!< (@ 0x00000000) System SRAM Wn Registers (n = 0 to 3) */ +} R_SYSRAM0_Type; /*!< Size = 256 (0x100) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller (R_ICU) + */ + +typedef struct /*!< (@ 0x81048000) R_ICU Structure */ +{ + union + { + __OM uint32_t S_SWINT; /*!< (@ 0x00000000) Software Interrupt Register for Safety Register */ + + struct + { + __OM uint32_t IC6 : 1; /*!< [0..0] Software Interrupt register */ + __OM uint32_t IC7 : 1; /*!< [1..1] Software Interrupt register */ + uint32_t : 30; + } S_SWINT_b; + }; + + union + { + __IOM uint32_t S_PORTNF_FLTSEL; /*!< (@ 0x00000004) Interrupt Noise Filter Enable Register for Safety + * Register */ + + struct + { + __IOM uint32_t FLT14 : 1; /*!< [0..0] Noise filter enable for IRQ14 */ + __IOM uint32_t FLT15 : 1; /*!< [1..1] Noise filter enable for IRQ15 */ + __IOM uint32_t FLTNMI : 1; /*!< [2..2] Noise filter enable for NMI */ + uint32_t : 29; + } S_PORTNF_FLTSEL_b; + }; + + union + { + __IOM uint32_t S_PORTNF_CLKSEL; /*!< (@ 0x00000008) Interrupt Noise Filter Setting Register for Safety + * Register */ + + struct + { + __IOM uint32_t CKSEL14 : 2; /*!< [1..0] Select noise filter sampling frequency dividend rate + * for IRQ14. */ + __IOM uint32_t CKSEL15 : 2; /*!< [3..2] Select noise filter sampling frequency dividend rate + * for IRQ15. */ + __IOM uint32_t CKSELNMI : 2; /*!< [5..4] Select noise filter sampling frequency dividend rate + * for NMI. */ + uint32_t : 26; + } S_PORTNF_CLKSEL_b; + }; + + union + { + __IOM uint32_t S_PORTNF_MD; /*!< (@ 0x0000000C) Interrupt Edge Detection Setting Register for + * Safety Register */ + + struct + { + __IOM uint32_t MD14 : 2; /*!< [1..0] Select detection mode for IRQ14 */ + __IOM uint32_t MD15 : 2; /*!< [3..2] Select detection mode for IRQ15 */ + __IOM uint32_t MDNMI : 2; /*!< [5..4] Select detection mode for NMI */ + uint32_t : 26; + } S_PORTNF_MD_b; + }; + __IM uint32_t RESERVED[20]; + + union + { + __IM uint32_t CPU0ERR_STAT; /*!< (@ 0x00000060) CPU0 Error Event Status Register */ + + struct + { + __IM uint32_t ER_ST0 : 1; /*!< [0..0] Indicate captured error status for CPU0_ERREVENT0 */ + __IM uint32_t ER_ST1 : 1; /*!< [1..1] Indicate captured error status for CPU0_ERREVENT1 */ + __IM uint32_t ER_ST2 : 1; /*!< [2..2] Indicate captured error status for CPU0_ERREVENT2 */ + __IM uint32_t ER_ST3 : 1; /*!< [3..3] Indicate captured error status for CPU0_ERREVENT3 */ + __IM uint32_t ER_ST4 : 1; /*!< [4..4] Indicate captured error status for CPU0_ERREVENT4 */ + __IM uint32_t ER_ST5 : 1; /*!< [5..5] Indicate captured error status for CPU0_ERREVENT5 */ + __IM uint32_t ER_ST6 : 1; /*!< [6..6] Indicate captured error status for CPU0_ERREVENT6 */ + __IM uint32_t ER_ST7 : 1; /*!< [7..7] Indicate captured error status for CPU0_ERREVENT7 */ + __IM uint32_t ER_ST8 : 1; /*!< [8..8] Indicate captured error status for CPU0_ERREVENT8 */ + __IM uint32_t ER_ST9 : 1; /*!< [9..9] Indicate captured error status for CPU0_ERREVENT9 */ + __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate captured error status for CPU0_ERREVENT10 */ + __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate captured error status for CPU0_ERREVENT11 */ + __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate captured error status for CPU0_ERREVENT12 */ + __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for CPU0_ERREVENT13 */ + __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate captured error status for CPU0_ERREVENT14 */ + __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for CPU0_ERREVENT15 */ + __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for CPU0_ERREVENT16 */ + __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for CPU0_ERREVENT17 */ + __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for CPU0_ERREVENT18 */ + __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for CPU0_ERREVENT19 */ + __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for CPU0_ERREVENT20 */ + __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for CPU0_ERREVENT21 */ + __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for CPU0_ERREVENT22 */ + __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for CPU0_ERREVENT23 */ + __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for CPU0_ERREVENT24 */ + __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate captured error status for CPU0_ERREVENT25 */ + uint32_t : 6; + } CPU0ERR_STAT_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t PERIERR_STAT0; /*!< (@ 0x00000068) Peripheral Error Event Status Register 0 */ + + struct + { + __IM uint32_t ER_ST0 : 1; /*!< [0..0] Indicate captured error status for CLMA3_INT */ + __IM uint32_t ER_ST1 : 1; /*!< [1..1] Indicate captured error status for CLMA0_INT */ + __IM uint32_t ER_ST2 : 1; /*!< [2..2] Indicate captured error status for CLMA1_INT */ + __IM uint32_t ER_ST3 : 1; /*!< [3..3] Indicate captured error status for CLMA2_INT */ + __IM uint32_t ER_ST4 : 1; /*!< [4..4] Indicate captured error status for BSC_WTO */ + __IM uint32_t ER_ST5 : 1; /*!< [5..5] Indicate captured error status for DMAC0_ERR */ + __IM uint32_t ER_ST6 : 1; /*!< [6..6] Indicate captured error status for DMAC1_ERR */ + __IM uint32_t ER_ST7 : 1; /*!< [7..7] Indicate captured error status for WDT_NMIUNDF0 */ + uint32_t : 1; + __IM uint32_t ER_ST9 : 1; /*!< [9..9] Indicate captured error status for USB_FDMAERR */ + __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate captured error status for DSMIF0_LTCSE */ + __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate captured error status for DSMIF0_UTCSE */ + __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate captured error status for DSMIF0_LTODE0 */ + __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for DSMIF0_LTODE1 */ + __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate captured error status for DSMIF0_LTODE2 */ + __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for DSMIF0_UTODE0 */ + __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for DSMIF0_UTODE1 */ + __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for DSMIF0_UTODE2 */ + __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for DSMIF0_SCDE0 */ + __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for DSMIF0_SCDE1 */ + __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for DSMIF0_SCDE2 */ + __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for DSMIF1_LTCSE */ + __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for DSMIF1_UTCSE */ + __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for DSMIF1_LTODE0 */ + __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for DSMIF1_LTODE1 */ + __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate captured error status for DSMIF1_LTODE2 */ + __IM uint32_t ER_ST26 : 1; /*!< [26..26] Indicate captured error status for DSMIF1_UTODE0 */ + __IM uint32_t ER_ST27 : 1; /*!< [27..27] Indicate captured error status for DSMIF1_UTODE1 */ + __IM uint32_t ER_ST28 : 1; /*!< [28..28] Indicate captured error status for DSMIF1_UTODE2 */ + __IM uint32_t ER_ST29 : 1; /*!< [29..29] Indicate captured error status for DSMIF1_SCDE0 */ + __IM uint32_t ER_ST30 : 1; /*!< [30..30] Indicate captured error status for DSMIF1_SCDE1 */ + __IM uint32_t ER_ST31 : 1; /*!< [31..31] Indicate captured error status for DSMIF1_SCDE2 */ + } PERIERR_STAT0_b; + }; + + union + { + __IM uint32_t PERIERR_STAT1; /*!< (@ 0x0000006C) Peripheral Error Event Status Register 1 */ + + struct + { + __IM uint32_t ER_ST0 : 1; /*!< [0..0] Indicate captured error status for DOC_DOPCI */ + __IM uint32_t ER_ST1 : 1; /*!< [1..1] Indicate captured error status for SRAM0_IE1 */ + __IM uint32_t ER_ST2 : 1; /*!< [2..2] Indicate captured error status for SRAM0_IE2 */ + __IM uint32_t ER_ST3 : 1; /*!< [3..3] Indicate captured error status for SRAM0_OVF */ + __IM uint32_t ER_ST4 : 1; /*!< [4..4] Indicate captured error status for SRAM1_IE1 */ + __IM uint32_t ER_ST5 : 1; /*!< [5..5] Indicate captured error status for SRAM1_IE2 */ + __IM uint32_t ER_ST6 : 1; /*!< [6..6] Indicate captured error status for SRAM1_OVF */ + uint32_t : 6; + __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for MAIN_BUS_ERRINT */ + uint32_t : 1; + __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for MPU_SHOSTIF */ + uint32_t : 1; + __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for MPU_DMACR0 */ + __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for MPU_DMACW0 */ + __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for MPU_DMACR1 */ + __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for MPU_DMACW1 */ + __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for MPU_GMACR */ + __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for MPU_GMACW */ + __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for MPU_USBH */ + __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for MPU_USBF */ + uint32_t : 2; + __IM uint32_t ER_ST27 : 1; /*!< [27..27] Indicate captured error status for MPU_DBGR */ + __IM uint32_t ER_ST28 : 1; /*!< [28..28] Indicate captured error status for MPU_DBGW */ + __IM uint32_t ER_ST29 : 1; /*!< [29..29] Indicate capture error status for DSMIF0_OVC1EL0 */ + __IM uint32_t ER_ST30 : 1; /*!< [30..30] Indicate capture error status for DSMIF0_OVC1EH0 */ + __IM uint32_t ER_ST31 : 1; /*!< [31..31] Indicate capture error status for DSMIF0_OVC2EL0 */ + } PERIERR_STAT1_b; + }; + + union + { + __OM uint32_t CPU0ERR_CLR; /*!< (@ 0x00000070) CPU0 Error Event Status Clear Register */ + + struct + { + __OM uint32_t ER_CL0 : 1; /*!< [0..0] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL1 : 1; /*!< [1..1] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL2 : 1; /*!< [2..2] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL3 : 1; /*!< [3..3] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL4 : 1; /*!< [4..4] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL5 : 1; /*!< [5..5] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL6 : 1; /*!< [6..6] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL7 : 1; /*!< [7..7] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL8 : 1; /*!< [8..8] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL9 : 1; /*!< [9..9] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL17 : 1; /*!< [17..17] ER_CL17 */ + __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL25 : 1; /*!< [25..25] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + uint32_t : 6; + } CPU0ERR_CLR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __OM uint32_t PERIERR_CLR0; /*!< (@ 0x00000078) Peripheral Error Event Status Clear Register + * 0 */ + + struct + { + __OM uint32_t ER_CL0 : 1; /*!< [0..0] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL1 : 1; /*!< [1..1] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL2 : 1; /*!< [2..2] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL3 : 1; /*!< [3..3] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL4 : 1; /*!< [4..4] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL5 : 1; /*!< [5..5] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL6 : 1; /*!< [6..6] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL7 : 1; /*!< [7..7] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + uint32_t : 1; + __OM uint32_t ER_CL9 : 1; /*!< [9..9] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL25 : 1; /*!< [25..25] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL26 : 1; /*!< [26..26] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL27 : 1; /*!< [27..27] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL28 : 1; /*!< [28..28] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL29 : 1; /*!< [29..29] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL30 : 1; /*!< [30..30] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL31 : 1; /*!< [31..31] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + } PERIERR_CLR0_b; + }; + + union + { + __OM uint32_t PERIERR_CLR1; /*!< (@ 0x0000007C) Peripheral Error Event Status Clear Register + * 1 */ + + struct + { + __OM uint32_t ER_CL0 : 1; /*!< [0..0] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL1 : 1; /*!< [1..1] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL2 : 1; /*!< [2..2] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL3 : 1; /*!< [3..3] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL4 : 1; /*!< [4..4] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL5 : 1; /*!< [5..5] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL6 : 1; /*!< [6..6] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + uint32_t : 6; + __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + uint32_t : 1; + __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + uint32_t : 1; + __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + uint32_t : 2; + __OM uint32_t ER_CL27 : 1; /*!< [27..27] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL28 : 1; /*!< [28..28] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL29 : 1; /*!< [29..29] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL30 : 1; /*!< [30..30] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL31 : 1; /*!< [31..31] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + } PERIERR_CLR1_b; + }; + + union + { + __IOM uint32_t CPU0ERR_RSTMSK; /*!< (@ 0x00000080) CPU0 Error Event Reset Mask Register */ + + struct + { + __IOM uint32_t RS_MK0 : 1; /*!< [0..0] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK1 : 1; /*!< [1..1] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK2 : 1; /*!< [2..2] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK3 : 1; /*!< [3..3] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK4 : 1; /*!< [4..4] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK5 : 1; /*!< [5..5] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK6 : 1; /*!< [6..6] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK7 : 1; /*!< [7..7] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK8 : 1; /*!< [8..8] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK9 : 1; /*!< [9..9] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK25 : 1; /*!< [25..25] Mask captured error status as a reset event for CPU0ERR_STAT */ + uint32_t : 6; + } CPU0ERR_RSTMSK_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PERIERR_RSTMSK0; /*!< (@ 0x00000088) Peripheral Error Event Reset Mask Register 0 */ + + struct + { + __IOM uint32_t RS_MK0 : 1; /*!< [0..0] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK1 : 1; /*!< [1..1] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK2 : 1; /*!< [2..2] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK3 : 1; /*!< [3..3] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK4 : 1; /*!< [4..4] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK5 : 1; /*!< [5..5] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK6 : 1; /*!< [6..6] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK7 : 1; /*!< [7..7] Mask captured error status as a reset event for PERIERR_STAT0 */ + uint32_t : 1; + __IOM uint32_t RS_MK9 : 1; /*!< [9..9] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK25 : 1; /*!< [25..25] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK26 : 1; /*!< [26..26] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK27 : 1; /*!< [27..27] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK28 : 1; /*!< [28..28] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK29 : 1; /*!< [29..29] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK30 : 1; /*!< [30..30] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK31 : 1; /*!< [31..31] Mask captured error status as a reset event for PERIERR_STAT0 */ + } PERIERR_RSTMSK0_b; + }; + + union + { + __IOM uint32_t PERIERR_RSTMSK1; /*!< (@ 0x0000008C) Peripheral Error Event Reset Mask Register 1 */ + + struct + { + __IOM uint32_t RS_MK0 : 1; /*!< [0..0] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK1 : 1; /*!< [1..1] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK2 : 1; /*!< [2..2] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK3 : 1; /*!< [3..3] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK4 : 1; /*!< [4..4] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK5 : 1; /*!< [5..5] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK6 : 1; /*!< [6..6] Mask captured error status as a reset event for PERIERR_STAT1 */ + uint32_t : 6; + __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for PERIERR_STAT1 */ + uint32_t : 1; + __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for PERIERR_STAT1 */ + uint32_t : 1; + __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for PERIERR_STAT1 */ + uint32_t : 2; + __IOM uint32_t RS_MK27 : 1; /*!< [27..27] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK28 : 1; /*!< [28..28] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK29 : 1; /*!< [29..29] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK30 : 1; /*!< [30..30] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK31 : 1; /*!< [31..31] Mask captured error status as a reset event for PERIERR_STAT1 */ + } PERIERR_RSTMSK1_b; + }; + + union + { + __IOM uint32_t CPU0ERR_E0MSK; /*!< (@ 0x00000090) CPU0 E0 Error Event Mask Register */ + + struct + { + __IOM uint32_t E0_MK0 : 1; /*!< [0..0] Mask captured error status as a CPU0_ERR0 event for CPU0ERR_STAT */ + __IOM uint32_t E0_MK1 : 1; /*!< [1..1] Mask captured error status as a CPU0_ERR0 event for CPU0ERR_STAT */ + __IOM uint32_t E0_MK2 : 1; /*!< [2..2] Mask captured error status as a CPU0_ERR0 event for CPU0ERR_STAT */ + __IOM uint32_t E0_MK3 : 1; /*!< [3..3] Mask captured error status as a CPU0_ERR0 event for CPU0ERR_STAT */ + __IOM uint32_t E0_MK4 : 1; /*!< [4..4] Mask captured error status as a CPU0_ERR0 event for CPU0ERR_STAT */ + __IOM uint32_t E0_MK5 : 1; /*!< [5..5] Mask captured error status as a CPU0_ERR0 event for CPU0ERR_STAT */ + __IOM uint32_t E0_MK6 : 1; /*!< [6..6] Mask captured error status as a CPU0_ERR0 event for CPU0ERR_STAT */ + __IOM uint32_t E0_MK7 : 1; /*!< [7..7] Mask captured error status as a CPU0_ERR0 event for CPU0ERR_STAT */ + __IOM uint32_t E0_MK8 : 1; /*!< [8..8] Mask captured error status as a CPU0_ERR0 event for CPU0ERR_STAT */ + __IOM uint32_t E0_MK9 : 1; /*!< [9..9] Mask captured error status as a CPU0_ERR0 event for CPU0ERR_STAT */ + __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK25 : 1; /*!< [25..25] Mask captured error status as a CPU0_ERR0 event for + * CPU0ERR_STAT */ + uint32_t : 6; + } CPU0ERR_E0MSK_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t PERIERR_E0MSK0; /*!< (@ 0x00000098) Peripheral E0 Error Event Mask Register 0 */ + + struct + { + __IOM uint32_t E0_MK0 : 1; /*!< [0..0] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT0 */ + __IOM uint32_t E0_MK1 : 1; /*!< [1..1] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT0 */ + __IOM uint32_t E0_MK2 : 1; /*!< [2..2] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT0 */ + __IOM uint32_t E0_MK3 : 1; /*!< [3..3] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT0 */ + __IOM uint32_t E0_MK4 : 1; /*!< [4..4] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT0 */ + __IOM uint32_t E0_MK5 : 1; /*!< [5..5] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT0 */ + __IOM uint32_t E0_MK6 : 1; /*!< [6..6] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT0 */ + __IOM uint32_t E0_MK7 : 1; /*!< [7..7] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT0 */ + uint32_t : 1; + __IOM uint32_t E0_MK9 : 1; /*!< [9..9] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT0 */ + __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK25 : 1; /*!< [25..25] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK26 : 1; /*!< [26..26] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK27 : 1; /*!< [27..27] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK28 : 1; /*!< [28..28] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK29 : 1; /*!< [29..29] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK30 : 1; /*!< [30..30] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK31 : 1; /*!< [31..31] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT0 */ + } PERIERR_E0MSK0_b; + }; + + union + { + __IOM uint32_t PERIERR_E0MSK1; /*!< (@ 0x0000009C) Peripheral E0 Error Event Mask Register 1 */ + + struct + { + __IOM uint32_t E0_MK0 : 1; /*!< [0..0] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT1 */ + __IOM uint32_t E0_MK1 : 1; /*!< [1..1] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT1 */ + __IOM uint32_t E0_MK2 : 1; /*!< [2..2] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT1 */ + __IOM uint32_t E0_MK3 : 1; /*!< [3..3] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT1 */ + __IOM uint32_t E0_MK4 : 1; /*!< [4..4] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT1 */ + __IOM uint32_t E0_MK5 : 1; /*!< [5..5] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT1 */ + __IOM uint32_t E0_MK6 : 1; /*!< [6..6] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT1 */ + uint32_t : 6; + __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT1 */ + uint32_t : 1; + __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT1 */ + uint32_t : 1; + __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT1 */ + uint32_t : 2; + __IOM uint32_t E0_MK27 : 1; /*!< [27..27] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK28 : 1; /*!< [28..28] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK29 : 1; /*!< [29..29] Mask capture error status as a PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK30 : 1; /*!< [30..30] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK31 : 1; /*!< [31..31] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT1 */ + } PERIERR_E0MSK1_b; + }; + __IM uint32_t RESERVED5[24]; + + union + { + __IOM uint32_t CPU0ERR_E1MSK; /*!< (@ 0x00000100) CPU0 E1 Error Event Mask Register */ + + struct + { + __IOM uint32_t E1_MK0 : 1; /*!< [0..0] Mask captured error status as a CPU0_ERR1 event for CPU0ERR_STAT */ + __IOM uint32_t E1_MK1 : 1; /*!< [1..1] Mask captured error status as a CPU0_ERR1 event for CPU0ERR_STAT */ + __IOM uint32_t E1_MK2 : 1; /*!< [2..2] Mask captured error status as a CPU0_ERR1 event for CPU0ERR_STAT */ + __IOM uint32_t E1_MK3 : 1; /*!< [3..3] Mask captured error status as a CPU0_ERR1 event for CPU0ERR_STAT */ + __IOM uint32_t E1_MK4 : 1; /*!< [4..4] Mask captured error status as a CPU0_ERR1 event for CPU0ERR_STAT */ + __IOM uint32_t E1_MK5 : 1; /*!< [5..5] Mask captured error status as a CPU0_ERR1 event for CPU0ERR_STAT */ + __IOM uint32_t E1_MK6 : 1; /*!< [6..6] Mask captured error status as a CPU0_ERR1 event for CPU0ERR_STAT */ + __IOM uint32_t E1_MK7 : 1; /*!< [7..7] Mask captured error status as a CPU0_ERR1 event for CPU0ERR_STAT */ + __IOM uint32_t E1_MK8 : 1; /*!< [8..8] Mask captured error status as a CPU0_ERR1 event for CPU0ERR_STAT */ + __IOM uint32_t E1_MK9 : 1; /*!< [9..9] Mask captured error status as a CPU0_ERR1 event for CPU0ERR_STAT */ + __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK25 : 1; /*!< [25..25] Mask captured error status as a CPU0_ERR1 event for + * CPU0ERR_STAT */ + uint32_t : 6; + } CPU0ERR_E1MSK_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t PERIERR_E1MSK0; /*!< (@ 0x00000108) Peripheral E1 Error Event Mask Register 0 */ + + struct + { + __IOM uint32_t E1_MK0 : 1; /*!< [0..0] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT0 */ + __IOM uint32_t E1_MK1 : 1; /*!< [1..1] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT0 */ + __IOM uint32_t E1_MK2 : 1; /*!< [2..2] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT0 */ + __IOM uint32_t E1_MK3 : 1; /*!< [3..3] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT0 */ + __IOM uint32_t E1_MK4 : 1; /*!< [4..4] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT0 */ + __IOM uint32_t E1_MK5 : 1; /*!< [5..5] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT0 */ + __IOM uint32_t E1_MK6 : 1; /*!< [6..6] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT0 */ + __IOM uint32_t E1_MK7 : 1; /*!< [7..7] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT0 */ + uint32_t : 1; + __IOM uint32_t E1_MK9 : 1; /*!< [9..9] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT0 */ + __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK25 : 1; /*!< [25..25] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK26 : 1; /*!< [26..26] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK27 : 1; /*!< [27..27] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK28 : 1; /*!< [28..28] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK29 : 1; /*!< [29..29] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK30 : 1; /*!< [30..30] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK31 : 1; /*!< [31..31] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT0 */ + } PERIERR_E1MSK0_b; + }; + + union + { + __IOM uint32_t PERIERR_E1MSK1; /*!< (@ 0x0000010C) Peripheral E1 Error Event Mask Register 1 */ + + struct + { + __IOM uint32_t E1_MK0 : 1; /*!< [0..0] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT1 */ + __IOM uint32_t E1_MK1 : 1; /*!< [1..1] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT1 */ + __IOM uint32_t E1_MK2 : 1; /*!< [2..2] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT1 */ + __IOM uint32_t E1_MK3 : 1; /*!< [3..3] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT1 */ + __IOM uint32_t E1_MK4 : 1; /*!< [4..4] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT1 */ + __IOM uint32_t E1_MK5 : 1; /*!< [5..5] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT1 */ + __IOM uint32_t E1_MK6 : 1; /*!< [6..6] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT1 */ + uint32_t : 6; + __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT1 */ + uint32_t : 1; + __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT1 */ + uint32_t : 1; + __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT1 */ + uint32_t : 2; + __IOM uint32_t E1_MK27 : 1; /*!< [27..27] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK28 : 1; /*!< [28..28] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK29 : 1; /*!< [29..29] Mask capture error status as a PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK30 : 1; /*!< [30..30] Mask capture error status as a PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK31 : 1; /*!< [31..31] Mask capture error status as a PERI_ERR1 event for + * PERIERR_STAT1 */ + } PERIERR_E1MSK1_b; + }; + __IM uint32_t RESERVED7[4]; + + union + { + __IM uint32_t PERIERR_STAT2; /*!< (@ 0x00000120) Peripheral Error Event Status Register 2 */ + + struct + { + __IM uint32_t ER_ST0 : 1; /*!< [0..0] Indicate capture error status for DSMIF0_OVC2EH0 */ + __IM uint32_t ER_ST1 : 1; /*!< [1..1] Indicate capture error status for DSMIF0_OVC1EL1 */ + __IM uint32_t ER_ST2 : 1; /*!< [2..2] Indicate capture error status for DSMIF0_OVC1EH1 */ + __IM uint32_t ER_ST3 : 1; /*!< [3..3] Indicate capture error status for DSMIF0_OVC2EL1 */ + __IM uint32_t ER_ST4 : 1; /*!< [4..4] Indicate capture error status for DSMIF0_OVC2EH1 */ + __IM uint32_t ER_ST5 : 1; /*!< [5..5] Indicate capture error status for DSMIF0_OVC1EL2 */ + __IM uint32_t ER_ST6 : 1; /*!< [6..6] Indicate capture error status for DSMIF0_OVC1EH2 */ + __IM uint32_t ER_ST7 : 1; /*!< [7..7] Indicate capture error status for DSMIF0_OVC2EL2 */ + __IM uint32_t ER_ST8 : 1; /*!< [8..8] Indicate capture error status for DSMIF0_OVC2EH2 */ + __IM uint32_t ER_ST9 : 1; /*!< [9..9] Indicate capture error status for DSMIF0_OVC0WN0 */ + __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate capture error status for DSMIF0_OVC1WN0 */ + __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate capture error status for DSMIF0_OVC2WN0 */ + __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate capture error status for DSMIF0_OVC3WN0 */ + __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate capture error status for DSMIF0_OVC0WN1 */ + __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate capture error status for DSMIF0_OVC1WN1 */ + __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate capture error status for DSMIF0_OVC2WN1 */ + __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate capture error status for DSMIF0_OVC3WN1 */ + __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate capture error status for DSMIF0_OVC0WN2 */ + __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate capture error status for DSMIF0_OVC1WN2 */ + __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate capture error status for DSMIF0_OVC2WN2 */ + __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate capture error status for DSMIF0_OVC3WN2 */ + __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate capture error status for DSMIF1_OVC1EL0 */ + __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate capture error status for DSMIF1_OVC1EH0 */ + __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate capture error status for DSMIF1_OVC2EL0 */ + __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate capture error status for DSMIF1_OVC2EH0 */ + __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate capture error status for DSMIF1_OVC1EL1 */ + __IM uint32_t ER_ST26 : 1; /*!< [26..26] Indicate capture error status for DSMIF1_OVC1EH1 */ + __IM uint32_t ER_ST27 : 1; /*!< [27..27] Indicate capture error status for DSMIF1_OVC2EL1 */ + __IM uint32_t ER_ST28 : 1; /*!< [28..28] Indicate capture error status for DSMIF1_OVC2EH1 */ + __IM uint32_t ER_ST29 : 1; /*!< [29..29] Indicate capture error status for DSMIF1_OVC1EL2 */ + __IM uint32_t ER_ST30 : 1; /*!< [30..30] Indicate capture error status for DSMIF1_OVC1EH2 */ + __IM uint32_t ER_ST31 : 1; /*!< [31..31] Indicate capture error status for DSMIF1_OVC2EL2 */ + } PERIERR_STAT2_b; + }; + + union + { + __IM uint32_t PERIERR_STAT3; /*!< (@ 0x00000124) Peripheral Error Event Status Register 3 */ + + struct + { + __IM uint32_t ER_ST0 : 1; /*!< [0..0] Indicate capture error status for DSMIF1_OVC2EH2 */ + __IM uint32_t ER_ST1 : 1; /*!< [1..1] Indicate capture error status for DSMIF1_OVC0WN0 */ + __IM uint32_t ER_ST2 : 1; /*!< [2..2] Indicate capture error status for DSMIF1_OVC1WN0 */ + __IM uint32_t ER_ST3 : 1; /*!< [3..3] Indicate capture error status for DSMIF1_OVC2WN0 */ + __IM uint32_t ER_ST4 : 1; /*!< [4..4] Indicate capture error status for DSMIF1_OVC3WN0 */ + __IM uint32_t ER_ST5 : 1; /*!< [5..5] Indicate capture error status for DSMIF1_OVC0WN1 */ + __IM uint32_t ER_ST6 : 1; /*!< [6..6] Indicate capture error status for DSMIF1_OVC1WN1 */ + __IM uint32_t ER_ST7 : 1; /*!< [7..7] Indicate capture error status for DSMIF1_OVC2WN1 */ + __IM uint32_t ER_ST8 : 1; /*!< [8..8] Indicate capture error status for DSMIF1_OVC3WN1 */ + __IM uint32_t ER_ST9 : 1; /*!< [9..9] Indicate capture error status for DSMIF1_OVC0WN2 */ + __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate capture error status for DSMIF1_OVC1WN2 */ + __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate capture error status for DSMIF1_OVC2WN2 */ + __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate capture error status for DSMIF1_OVC3WN2 */ + __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate capture error status for BISS0_NER */ + __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate capture error status for BISS1_NER */ + __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate capture error status for HDSL0_estimator_on */ + __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate capture error status for HDSL0_safe_channel_err */ + __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate capture error status for HDSL0_safe_pos_err */ + __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate capture error status for HDSL0_acceleration_err */ + __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate capture error status for HDSL0_acc_thr_err */ + __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate capture error status for HDSL0_encoding_err */ + __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate capture error status for HDSL0_dev_thr_err */ + __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate capture error status for HDSL1_estimator_on */ + __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate capture error status for HDSL1_safe_channel_err */ + __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate capture error status for HDSL1_safe_pos_err */ + __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate capture error status for HDSL1_acceleration_err */ + __IM uint32_t ER_ST26 : 1; /*!< [26..26] Indicate capture error status for HDSL1_acc_thr_err */ + __IM uint32_t ER_ST27 : 1; /*!< [27..27] Indicate capture error status for HDSL1_encoding_err */ + __IM uint32_t ER_ST28 : 1; /*!< [28..28] Indicate capture error status for HDSL1_dev_thr_err */ + __IM uint32_t ER_ST29 : 1; /*!< [29..29] Indicate capture error status for AFMT0_TMOUT */ + __IM uint32_t ER_ST30 : 1; /*!< [30..30] Indicate capture error status for AFMT1_TMOUT */ + uint32_t : 1; + } PERIERR_STAT3_b; + }; + __IM uint32_t RESERVED8[2]; + + union + { + __OM uint32_t PERIERR_CLR2; /*!< (@ 0x00000130) Peripheral Error Event Status Clear Register + * 2 */ + + struct + { + __OM uint32_t ER_CL0 : 1; /*!< [0..0] ER_CL0 */ + __OM uint32_t ER_CL1 : 1; /*!< [1..1] ER_CL1 */ + __OM uint32_t ER_CL2 : 1; /*!< [2..2] ER_CL2 */ + __OM uint32_t ER_CL3 : 1; /*!< [3..3] ER_CL3 */ + __OM uint32_t ER_CL4 : 1; /*!< [4..4] ER_CL4 */ + __OM uint32_t ER_CL5 : 1; /*!< [5..5] ER_CL5 */ + __OM uint32_t ER_CL6 : 1; /*!< [6..6] ER_CL6 */ + __OM uint32_t ER_CL7 : 1; /*!< [7..7] ER_CL7 */ + __OM uint32_t ER_CL8 : 1; /*!< [8..8] ER_CL8 */ + __OM uint32_t ER_CL9 : 1; /*!< [9..9] ER_CL9 */ + __OM uint32_t ER_CL10 : 1; /*!< [10..10] ER_CL10 */ + __OM uint32_t ER_CL11 : 1; /*!< [11..11] ER_CL11 */ + __OM uint32_t ER_CL12 : 1; /*!< [12..12] ER_CL12 */ + __OM uint32_t ER_CL13 : 1; /*!< [13..13] ER_CL13 */ + __OM uint32_t ER_CL14 : 1; /*!< [14..14] ER_CL14 */ + __OM uint32_t ER_CL15 : 1; /*!< [15..15] ER_CL15 */ + __OM uint32_t ER_CL16 : 1; /*!< [16..16] ER_CL16 */ + __OM uint32_t ER_CL17 : 1; /*!< [17..17] ER_CL17 */ + __OM uint32_t ER_CL18 : 1; /*!< [18..18] ER_CL18 */ + __OM uint32_t ER_CL19 : 1; /*!< [19..19] ER_CL19 */ + __OM uint32_t ER_CL20 : 1; /*!< [20..20] ER_CL20 */ + __OM uint32_t ER_CL21 : 1; /*!< [21..21] ER_CL21 */ + __OM uint32_t ER_CL22 : 1; /*!< [22..22] ER_CL22 */ + __OM uint32_t ER_CL23 : 1; /*!< [23..23] ER_CL23 */ + __OM uint32_t ER_CL24 : 1; /*!< [24..24] ER_CL24 */ + __OM uint32_t ER_CL25 : 1; /*!< [25..25] ER_CL25 */ + __OM uint32_t ER_CL26 : 1; /*!< [26..26] ER_CL26 */ + __OM uint32_t ER_CL27 : 1; /*!< [27..27] ER_CL27 */ + __OM uint32_t ER_CL28 : 1; /*!< [28..28] ER_CL28 */ + __OM uint32_t ER_CL29 : 1; /*!< [29..29] ER_CL29 */ + __OM uint32_t ER_CL30 : 1; /*!< [30..30] ER_CL30 */ + __OM uint32_t ER_CL31 : 1; /*!< [31..31] ER_CL31 */ + } PERIERR_CLR2_b; + }; + + union + { + __OM uint32_t PERIERR_CLR3; /*!< (@ 0x00000134) Peripheral Error Event Status Clear Register + * 3 */ + + struct + { + __OM uint32_t ER_CL0 : 1; /*!< [0..0] ER_CL0 */ + __OM uint32_t ER_CL1 : 1; /*!< [1..1] ER_CL1 */ + __OM uint32_t ER_CL2 : 1; /*!< [2..2] ER_CL2 */ + __OM uint32_t ER_CL3 : 1; /*!< [3..3] ER_CL3 */ + __OM uint32_t ER_CL4 : 1; /*!< [4..4] ER_CL4 */ + __OM uint32_t ER_CL5 : 1; /*!< [5..5] ER_CL5 */ + __OM uint32_t ER_CL6 : 1; /*!< [6..6] ER_CL6 */ + __OM uint32_t ER_CL7 : 1; /*!< [7..7] ER_CL7 */ + __OM uint32_t ER_CL8 : 1; /*!< [8..8] ER_CL8 */ + __OM uint32_t ER_CL9 : 1; /*!< [9..9] ER_CL9 */ + __OM uint32_t ER_CL10 : 1; /*!< [10..10] ER_CL10 */ + __OM uint32_t ER_CL11 : 1; /*!< [11..11] ER_CL11 */ + __OM uint32_t ER_CL12 : 1; /*!< [12..12] ER_CL12 */ + __OM uint32_t ER_CL13 : 1; /*!< [13..13] ER_CL13 */ + __OM uint32_t ER_CL14 : 1; /*!< [14..14] ER_CL14 */ + __OM uint32_t ER_CL15 : 1; /*!< [15..15] ER_CL15 */ + __OM uint32_t ER_CL16 : 1; /*!< [16..16] ER_CL16 */ + __OM uint32_t ER_CL17 : 1; /*!< [17..17] ER_CL17 */ + __OM uint32_t ER_CL18 : 1; /*!< [18..18] ER_CL18 */ + __OM uint32_t ER_CL19 : 1; /*!< [19..19] ER_CL19 */ + __OM uint32_t ER_CL20 : 1; /*!< [20..20] ER_CL20 */ + __OM uint32_t ER_CL21 : 1; /*!< [21..21] ER_CL21 */ + __OM uint32_t ER_CL22 : 1; /*!< [22..22] ER_CL22 */ + __OM uint32_t ER_CL23 : 1; /*!< [23..23] ER_CL23 */ + __OM uint32_t ER_CL24 : 1; /*!< [24..24] ER_CL24 */ + __OM uint32_t ER_CL25 : 1; /*!< [25..25] ER_CL25 */ + __OM uint32_t ER_CL26 : 1; /*!< [26..26] ER_CL26 */ + __OM uint32_t ER_CL27 : 1; /*!< [27..27] ER_CL27 */ + __OM uint32_t ER_CL28 : 1; /*!< [28..28] ER_CL28 */ + __OM uint32_t ER_CL29 : 1; /*!< [29..29] ER_CL29 */ + __OM uint32_t ER_CL30 : 1; /*!< [30..30] ER_CL30 */ + uint32_t : 1; + } PERIERR_CLR3_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IOM uint32_t PERIERR_RSTMSK2; /*!< (@ 0x00000140) Peripheral Error Event Reset Mask Register 2 */ + + struct + { + __IOM uint32_t RS_MK0 : 1; /*!< [0..0] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK1 : 1; /*!< [1..1] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK2 : 1; /*!< [2..2] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK3 : 1; /*!< [3..3] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK4 : 1; /*!< [4..4] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK5 : 1; /*!< [5..5] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK6 : 1; /*!< [6..6] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK7 : 1; /*!< [7..7] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK8 : 1; /*!< [8..8] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK9 : 1; /*!< [9..9] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK25 : 1; /*!< [25..25] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK26 : 1; /*!< [26..26] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK27 : 1; /*!< [27..27] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK28 : 1; /*!< [28..28] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK29 : 1; /*!< [29..29] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK30 : 1; /*!< [30..30] Mask captured error status as a reset event for PERIERR_STAT2 */ + __IOM uint32_t RS_MK31 : 1; /*!< [31..31] Mask captured error status as a reset event for PERIERR_STAT2 */ + } PERIERR_RSTMSK2_b; + }; + + union + { + __IOM uint32_t PERIERR_RSTMSK3; /*!< (@ 0x00000144) Peripheral Error Event Reset Mask Register 3 */ + + struct + { + __IOM uint32_t RS_MK0 : 1; /*!< [0..0] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK1 : 1; /*!< [1..1] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK2 : 1; /*!< [2..2] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK3 : 1; /*!< [3..3] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK4 : 1; /*!< [4..4] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK5 : 1; /*!< [5..5] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK6 : 1; /*!< [6..6] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK7 : 1; /*!< [7..7] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK8 : 1; /*!< [8..8] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK9 : 1; /*!< [9..9] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK25 : 1; /*!< [25..25] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK26 : 1; /*!< [26..26] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK27 : 1; /*!< [27..27] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK28 : 1; /*!< [28..28] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK29 : 1; /*!< [29..29] Mask captured error status as a reset event for PERIERR_STAT3 */ + __IOM uint32_t RS_MK30 : 1; /*!< [30..30] Mask captured error status as a reset event for PERIERR_STAT3 */ + uint32_t : 1; + } PERIERR_RSTMSK3_b; + }; + __IM uint32_t RESERVED10[2]; + + union + { + __IOM uint32_t PERIERR_E0MSK2; /*!< (@ 0x00000150) Peripheral E0 Error Event Mask Register 2 */ + + struct + { + __IOM uint32_t E0_MK0 : 1; /*!< [0..0] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT2 */ + __IOM uint32_t E0_MK1 : 1; /*!< [1..1] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT2 */ + __IOM uint32_t E0_MK2 : 1; /*!< [2..2] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT2 */ + __IOM uint32_t E0_MK3 : 1; /*!< [3..3] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT2 */ + __IOM uint32_t E0_MK4 : 1; /*!< [4..4] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT2 */ + __IOM uint32_t E0_MK5 : 1; /*!< [5..5] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT2 */ + __IOM uint32_t E0_MK6 : 1; /*!< [6..6] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT2 */ + __IOM uint32_t E0_MK7 : 1; /*!< [7..7] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT2 */ + __IOM uint32_t E0_MK8 : 1; /*!< [8..8] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT2 */ + __IOM uint32_t E0_MK9 : 1; /*!< [9..9] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT2 */ + __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK25 : 1; /*!< [25..25] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK26 : 1; /*!< [26..26] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK27 : 1; /*!< [27..27] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK28 : 1; /*!< [28..28] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK29 : 1; /*!< [29..29] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK30 : 1; /*!< [30..30] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + __IOM uint32_t E0_MK31 : 1; /*!< [31..31] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT2 */ + } PERIERR_E0MSK2_b; + }; + + union + { + __IOM uint32_t PERIERR_E0MSK3; /*!< (@ 0x00000154) Peripheral E0 Error Event Mask Register 3 */ + + struct + { + __IOM uint32_t E0_MK0 : 1; /*!< [0..0] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT3 */ + __IOM uint32_t E0_MK1 : 1; /*!< [1..1] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT3 */ + __IOM uint32_t E0_MK2 : 1; /*!< [2..2] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT3 */ + __IOM uint32_t E0_MK3 : 1; /*!< [3..3] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT3 */ + __IOM uint32_t E0_MK4 : 1; /*!< [4..4] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT3 */ + __IOM uint32_t E0_MK5 : 1; /*!< [5..5] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT3 */ + __IOM uint32_t E0_MK6 : 1; /*!< [6..6] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT3 */ + __IOM uint32_t E0_MK7 : 1; /*!< [7..7] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT3 */ + __IOM uint32_t E0_MK8 : 1; /*!< [8..8] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT3 */ + __IOM uint32_t E0_MK9 : 1; /*!< [9..9] Mask captured error status as a PERI_ERR0 event for PERIERR_STAT3 */ + __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK25 : 1; /*!< [25..25] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK26 : 1; /*!< [26..26] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK27 : 1; /*!< [27..27] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK28 : 1; /*!< [28..28] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK29 : 1; /*!< [29..29] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + __IOM uint32_t E0_MK30 : 1; /*!< [30..30] Mask captured error status as a PERI_ERR0 event for + * PERIERR_STAT3 */ + uint32_t : 1; + } PERIERR_E0MSK3_b; + }; + __IM uint32_t RESERVED11[26]; + + union + { + __IOM uint32_t PERIERR_E1MSK2; /*!< (@ 0x000001C0) Peripheral E1 Error Event Mask Register 2 */ + + struct + { + __IOM uint32_t E1_MK0 : 1; /*!< [0..0] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT2 */ + __IOM uint32_t E1_MK1 : 1; /*!< [1..1] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT2 */ + __IOM uint32_t E1_MK2 : 1; /*!< [2..2] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT2 */ + __IOM uint32_t E1_MK3 : 1; /*!< [3..3] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT2 */ + __IOM uint32_t E1_MK4 : 1; /*!< [4..4] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT2 */ + __IOM uint32_t E1_MK5 : 1; /*!< [5..5] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT2 */ + __IOM uint32_t E1_MK6 : 1; /*!< [6..6] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT2 */ + __IOM uint32_t E1_MK7 : 1; /*!< [7..7] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT2 */ + __IOM uint32_t E1_MK8 : 1; /*!< [8..8] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT2 */ + __IOM uint32_t E1_MK9 : 1; /*!< [9..9] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT2 */ + __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK25 : 1; /*!< [25..25] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK26 : 1; /*!< [26..26] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK27 : 1; /*!< [27..27] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK28 : 1; /*!< [28..28] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK29 : 1; /*!< [29..29] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK30 : 1; /*!< [30..30] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + __IOM uint32_t E1_MK31 : 1; /*!< [31..31] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT2 */ + } PERIERR_E1MSK2_b; + }; + + union + { + __IOM uint32_t PERIERR_E1MSK3; /*!< (@ 0x000001C4) Peripheral E1 Error Event Mask Register 3 */ + + struct + { + __IOM uint32_t E1_MK0 : 1; /*!< [0..0] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT3 */ + __IOM uint32_t E1_MK1 : 1; /*!< [1..1] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT3 */ + __IOM uint32_t E1_MK2 : 1; /*!< [2..2] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT3 */ + __IOM uint32_t E1_MK3 : 1; /*!< [3..3] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT3 */ + __IOM uint32_t E1_MK4 : 1; /*!< [4..4] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT3 */ + __IOM uint32_t E1_MK5 : 1; /*!< [5..5] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT3 */ + __IOM uint32_t E1_MK6 : 1; /*!< [6..6] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT3 */ + __IOM uint32_t E1_MK7 : 1; /*!< [7..7] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT3 */ + __IOM uint32_t E1_MK8 : 1; /*!< [8..8] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT3 */ + __IOM uint32_t E1_MK9 : 1; /*!< [9..9] Mask captured error status as a PERI_ERR1 event for PERIERR_STAT3 */ + __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK25 : 1; /*!< [25..25] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK26 : 1; /*!< [26..26] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK27 : 1; /*!< [27..27] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK28 : 1; /*!< [28..28] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK29 : 1; /*!< [29..29] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + __IOM uint32_t E1_MK30 : 1; /*!< [30..30] Mask captured error status as a PERI_ERR1 event for + * PERIERR_STAT3 */ + uint32_t : 1; + } PERIERR_E1MSK3_b; + }; +} R_ICU_Type; /*!< Size = 456 (0x1c8) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSC_S ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Register Write Protection for Safety Area (R_SYSC_S) + */ + +typedef struct /*!< (@ 0x81280000) R_SYSC_S Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SCKCR2; /*!< (@ 0x00000004) System Clock Control Register 2 */ + + struct + { + __IOM uint32_t FSELCPU0 : 2; /*!< [1..0] Set the frequency of the clock provided to Coretex-R52 + * CPU0 in combination with bit 5 (DIVSELSUB). The combination + * is shown below. */ + uint32_t : 2; + __IOM uint32_t FSELTRACE : 1; /*!< [4..4] FSELTRACE */ + __IOM uint32_t DIVSELSUB : 1; /*!< [5..5] Select the base clock frequency for peripheral module. */ + uint32_t : 18; + __IOM uint32_t SPI3ASYNCSEL : 1; /*!< [24..24] Select clock frequency when asynchronous serial clock + * is selected in SPI3 */ + __IOM uint32_t SCI5ASYNCSEL : 1; /*!< [25..25] Select clock frequency when asynchronous serial clock + * is selected in SCI5 */ + uint32_t : 6; + } SCKCR2_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IM uint32_t PLL0MON; /*!< (@ 0x00000020) PLL0 Monitor Register */ + + struct + { + __IM uint32_t PLL0MON : 1; /*!< [0..0] PLL0 Lock State Monitor */ + uint32_t : 31; + } PLL0MON_b; + }; + __IM uint32_t RESERVED2[7]; + + union + { + __IM uint32_t PLL1MON; /*!< (@ 0x00000040) PLL1 Monitor Register */ + + struct + { + __IM uint32_t PLL1MON : 1; /*!< [0..0] PLL1 Lock State Monitor */ + uint32_t : 31; + } PLL1MON_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t PLL1EN; /*!< (@ 0x00000050) PLL1 Enable Register */ + + struct + { + __IOM uint32_t PLL1EN : 1; /*!< [0..0] PLL1 Enable */ + uint32_t : 31; + } PLL1EN_b; + }; + __IM uint32_t RESERVED4[7]; + + union + { + __IOM uint32_t LOCOCR; /*!< (@ 0x00000070) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint32_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint32_t : 31; + } LOCOCR_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint32_t HIZCTRLEN; /*!< (@ 0x00000080) High-Impedance Control Enable Register */ + + struct + { + __IOM uint32_t CLMA3MASK : 1; /*!< [0..0] CLMA3 error mask to POE3 and POEG */ + __IOM uint32_t CLMA0MASK : 1; /*!< [1..1] CLMA0 error mask to POE3 and POEG */ + __IOM uint32_t CLMA1MASK : 1; /*!< [2..2] CLMA1 error mask to POE3 and POEG */ + uint32_t : 29; + } HIZCTRLEN_b; + }; + __IM uint32_t RESERVED6[99]; + + union + { + __OM uint32_t SWRSYS; /*!< (@ 0x00000210) System Software Reset Register */ + + struct + { + __OM uint32_t SWR : 32; /*!< [31..0] System Software Reset */ + } SWRSYS_b; + }; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint32_t SWRCPU0; /*!< (@ 0x00000220) CPU0 Software Reset Register */ + + struct + { + __IOM uint32_t SWR : 32; /*!< [31..0] CPU0 Software Reset */ + } SWRCPU0_b; + }; + __IM uint32_t RESERVED8[15]; + + union + { + __IOM uint32_t MRCTLI; /*!< (@ 0x00000260) Module Reset Control Register I */ + + struct + { + uint32_t : 1; + __IOM uint32_t MRCTLI01 : 1; /*!< [1..1] MRCTLI01 */ + __IOM uint32_t MRCTLI02 : 1; /*!< [2..2] MRCTLI02 */ + __IOM uint32_t MRCTLI03 : 1; /*!< [3..3] MRCTLI03 */ + uint32_t : 28; + } MRCTLI_b; + }; + __IM uint32_t RESERVED9[44]; + + union + { + __IOM uint32_t MSTPCRF; /*!< (@ 0x00000314) Module Stop Control Register F */ + + struct + { + __IOM uint32_t MSTPCRF00 : 1; /*!< [0..0] Trace Clock for Debugging Interface Module Stop */ + uint32_t : 31; + } MSTPCRF_b; + }; + + union + { + __IOM uint32_t MSTPCRG; /*!< (@ 0x00000318) Module Stop Control Register G */ + + struct + { + __IOM uint32_t MSTPCRG00 : 1; /*!< [0..0] SCI Unit 5 Module Stop */ + __IOM uint32_t MSTPCRG01 : 1; /*!< [1..1] IIC Unit 2 Module Stop */ + __IOM uint32_t MSTPCRG02 : 1; /*!< [2..2] SPI Unit 3 Module Stop */ + __IOM uint32_t MSTPCRG03 : 1; /*!< [3..3] GPT Unit 2 Module Stop */ + __IOM uint32_t MSTPCRG04 : 1; /*!< [4..4] CRC Unit 1 Module Stop */ + __IOM uint32_t MSTPCRG05 : 1; /*!< [5..5] RTC Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPCRG08 : 1; /*!< [8..8] CLMA3 Module Stop */ + __IOM uint32_t MSTPCRG09 : 1; /*!< [9..9] CLMA0 Module Stop */ + __IOM uint32_t MSTPCRG10 : 1; /*!< [10..10] CLMA1 Module Stop */ + __IOM uint32_t MSTPCRG11 : 1; /*!< [11..11] CLMA2 Module Stop */ + uint32_t : 20; + } MSTPCRG_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t MSTPCRI; /*!< (@ 0x00000320) Module Stop Control Register I */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPCRI01 : 1; /*!< [1..1] SHOSTIF Module Stop */ + uint32_t : 30; + } MSTPCRI_b; + }; +} R_SYSC_S_Type; /*!< Size = 804 (0x324) */ + +/* =========================================================================================================================== */ +/* ================ R_CLMA0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Monitor Circuit 0 (R_CLMA0) + */ + +typedef struct /*!< (@ 0x81280800) R_CLMA0 Structure */ +{ + union + { + __IOM uint8_t CTL0; /*!< (@ 0x00000000) CLMA Control Register 0 */ + + struct + { + __IOM uint8_t CLME : 1; /*!< [0..0] Clock Monitor m Enable (m = 0 to 3) */ + uint8_t : 7; + } CTL0_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t CMPL; /*!< (@ 0x00000008) CLMA Compare Register L */ + + struct + { + __IOM uint16_t CMPL : 12; /*!< [11..0] Clock Monitor m Compare L (m = 0 to 3) */ + uint16_t : 4; + } CMPL_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t CMPH; /*!< (@ 0x0000000C) CLMA Compare Register H */ + + struct + { + __IOM uint16_t CMPH : 12; /*!< [11..0] Clock Monitor m Compare H (m = 0 to 3) */ + uint16_t : 4; + } CMPH_b; + }; + __IM uint16_t RESERVED3; + __OM uint8_t PCMD; /*!< (@ 0x00000010) CLMA Command Register */ + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IM uint8_t PROTSR; /*!< (@ 0x00000014) CLMA Protection Status Register */ + + struct + { + __IM uint8_t PRERR : 1; /*!< [0..0] CLMAm Error (m = 0 to 3) */ + uint8_t : 7; + } PROTSR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; +} R_CLMA0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Master MPU 0 (R_MPU0) + */ + +typedef struct /*!< (@ 0x81281100) R_MPU0 Structure */ +{ + __IOM R_MPU0_RGN_Type RGN[8]; /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register + * [0..7] */ + + union + { + __IOM uint32_t ERRINF_R; /*!< (@ 0x00000080) Master MPU Error Information Register for AXI + * type */ + + struct + { + __IOM uint32_t VALID : 1; /*!< [0..0] Validity of access error information */ + __IM uint32_t RW : 1; /*!< [1..1] Access error type */ + __IM uint32_t ERRADDR : 30; /*!< [31..2] Access error address */ + } ERRINF_R_b; + }; + + union + { + __IOM uint32_t ERRINF_W; /*!< (@ 0x00000084) Master MPU Error Information Register for AXI + * type */ + + struct + { + __IOM uint32_t VALID : 1; /*!< [0..0] Validity of access error information */ + __IM uint32_t RW : 1; /*!< [1..1] Access error type */ + __IM uint32_t ERRADDR : 30; /*!< [31..2] Access error address */ + } ERRINF_W_b; + }; +} R_MPU0_Type; /*!< Size = 136 (0x88) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU3 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Master MPU 3 (R_MPU3) + */ + +typedef struct /*!< (@ 0x81281400) R_MPU3 Structure */ +{ + __IOM R_MPU0_RGN_Type RGN[8]; /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register + * [0..7] */ + + union + { + __IOM uint32_t ERRINF; /*!< (@ 0x00000080) Master MPU Error Information Register for AHB + * type */ + + struct + { + __IOM uint32_t VALID : 1; /*!< [0..0] Validity of Access Error Information */ + __IM uint32_t RW : 1; /*!< [1..1] Access error type */ + __IM uint32_t ERRADDR : 30; /*!< [31..2] Access Error Address */ + } ERRINF_b; + }; +} R_MPU3_Type; /*!< Size = 132 (0x84) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSRAM_CTL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System SRAM Control (R_SYSRAM_CTL) + */ + +typedef struct /*!< (@ 0x81281800) R_SYSRAM_CTL Structure */ +{ + union + { + __IOM uint32_t SYSRAM_CTRL0; /*!< (@ 0x00000000) System SRAM Control Register 0 */ + + struct + { + __IOM uint32_t VECEN : 1; /*!< [0..0] Enables or disables error correction with ECC */ + uint32_t : 15; + __IOM uint32_t VRWEN : 4; /*!< [19..16] Enables write for each page of RAM */ + __IOM uint32_t VCEN : 1; /*!< [20..20] Enables access to RAM */ + __IOM uint32_t VLWEN : 1; /*!< [21..21] Enables write for RAM */ + uint32_t : 2; + __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors */ + uint32_t : 7; + } SYSRAM_CTRL0_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SYSRAM_CTRL1; /*!< (@ 0x00000010) System SRAM Control Register 1 */ + + struct + { + __IOM uint32_t VECEN : 1; /*!< [0..0] Enables or disables error correction with ECC */ + uint32_t : 15; + __IOM uint32_t VRWEN : 4; /*!< [19..16] Enables write for each page of RAM */ + __IOM uint32_t VCEN : 1; /*!< [20..20] Enables access to RAM */ + __IOM uint32_t VLWEN : 1; /*!< [21..21] Enables write for RAM */ + uint32_t : 2; + __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors */ + uint32_t : 7; + } SYSRAM_CTRL1_b; + }; +} R_SYSRAM_CTL_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_TCMAW ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TCM access wait state (R_TCMAW) + */ + +typedef struct /*!< (@ 0x81281900) R_TCMAW Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IM uint32_t CPU0WAIT; /*!< (@ 0x00000010) ATCM CPU0 Wait State Register */ + + struct + { + __IM uint32_t CPU0WAIT : 1; /*!< [0..0] ATCM CPU0 Wait state */ + uint32_t : 31; + } CPU0WAIT_b; + }; +} R_TCMAW_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_SHOSTIF_CFG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Host Interface Configuration (R_SHOSTIF_CFG) + */ + +typedef struct /*!< (@ 0x81281920) R_SHOSTIF_CFG Structure */ +{ + union + { + __IOM uint32_t SHCFG; /*!< (@ 0x00000000) SHOSTIF Configuration Register */ + + struct + { + __IOM uint32_t SPIMODE : 2; /*!< [1..0] SPI Frame Format Select */ + __IOM uint32_t BYTESWAP : 1; /*!< [2..2] Byte Swap Mode */ + __IOM uint32_t ADDRESSING : 1; /*!< [3..3] Addressing Mode */ + __IM uint32_t SLEEP : 1; /*!< [4..4] SHOSTIF Enable Flag Monitor */ + uint32_t : 11; + __IOM uint32_t INTMASKI : 6; /*!< [21..16] Interrupt Mask Enable for Internal Interrupt (SHOST_INT) */ + uint32_t : 2; + __IOM uint32_t INTMASKE : 6; /*!< [29..24] Interrupt Mask Enable for External Interrupt (HSPI_INT# + * signal) */ + uint32_t : 2; + } SHCFG_b; + }; +} R_SHOSTIF_CFG_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_RWP_S ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Register Write Protection for Safety Area (R_RWP_S) + */ + +typedef struct /*!< (@ 0x81281A00) R_RWP_S Structure */ +{ + union + { + __IOM uint32_t PRCRS; /*!< (@ 0x00000000) Safety Area Protect Register */ + + struct + { + __IOM uint32_t PRC0 : 1; /*!< [0..0] Protect 0 */ + __IOM uint32_t PRC1 : 1; /*!< [1..1] Protect 1 */ + __IOM uint32_t PRC2 : 1; /*!< [2..2] Protect 2 */ + __IOM uint32_t PRC3 : 1; /*!< [3..3] Protect 3 */ + uint32_t : 4; + __OM uint32_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + uint32_t : 16; + } PRCRS_b; + }; +} R_RWP_S_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit (R_MTU) + */ + +typedef struct /*!< (@ 0x90001000) R_MTU Structure */ +{ + __IM uint16_t RESERVED[261]; + + union + { + __IOM uint8_t TOERA; /*!< (@ 0x0000020A) Timer Output Master Enable Register A */ + + struct + { + __IOM uint8_t OE3B : 1; /*!< [0..0] Master Enable MTIOC3B */ + __IOM uint8_t OE4A : 1; /*!< [1..1] Master Enable MTIOC4A */ + __IOM uint8_t OE4B : 1; /*!< [2..2] Master Enable MTIOC4B */ + __IOM uint8_t OE3D : 1; /*!< [3..3] Master Enable MTIOC3D */ + __IOM uint8_t OE4C : 1; /*!< [4..4] Master Enable MTIOC4C */ + __IOM uint8_t OE4D : 1; /*!< [5..5] Master Enable MTIOC4D */ + uint8_t : 2; + } TOERA_b; + }; + __IM uint8_t RESERVED1[2]; + + union + { + __IOM uint8_t TGCRA; /*!< (@ 0x0000020D) Timer Gate Control Register A */ + + struct + { + __IOM uint8_t UF : 1; /*!< [0..0] Output Phase Switch */ + __IOM uint8_t VF : 1; /*!< [1..1] Output Phase Switch */ + __IOM uint8_t WF : 1; /*!< [2..2] Output Phase Switch */ + __IOM uint8_t FB : 1; /*!< [3..3] External Feedback Signal Enable */ + __IOM uint8_t P : 1; /*!< [4..4] Positive-Phase Output (P) Control */ + __IOM uint8_t N : 1; /*!< [5..5] Negative-Phase Output (N) Control */ + __IOM uint8_t BDC : 1; /*!< [6..6] Brushless DC Motor */ + uint8_t : 1; + } TGCRA_b; + }; + + union + { + __IOM uint8_t TOCR1A; /*!< (@ 0x0000020E) Timer Output Control Register 1A */ + + struct + { + __IOM uint8_t OLSP : 1; /*!< [0..0] Output Level Select P */ + __IOM uint8_t OLSN : 1; /*!< [1..1] Output Level Select N */ + __IOM uint8_t TOCS : 1; /*!< [2..2] TOC Select */ + __IOM uint8_t TOCL : 1; /*!< [3..3] TOC Register Write Protection */ + uint8_t : 2; + __IOM uint8_t PSYE : 1; /*!< [6..6] PWM Synchronous Output Enable */ + uint8_t : 1; + } TOCR1A_b; + }; + + union + { + __IOM uint8_t TOCR2A; /*!< (@ 0x0000020F) Timer Output Control Register 2A */ + + struct + { + __IOM uint8_t OLS1P : 1; /*!< [0..0] Output Level Select 1P */ + __IOM uint8_t OLS1N : 1; /*!< [1..1] Output Level Select 1N */ + __IOM uint8_t OLS2P : 1; /*!< [2..2] Output Level Select 2P */ + __IOM uint8_t OLS2N : 1; /*!< [3..3] Output Level Select 2N */ + __IOM uint8_t OLS3P : 1; /*!< [4..4] Output Level Select 3P */ + __IOM uint8_t OLS3N : 1; /*!< [5..5] Output Level Select 3N */ + __IOM uint8_t BF : 2; /*!< [7..6] TOLBR Buffer Transfer Timing Select */ + } TOCR2A_b; + }; + __IM uint16_t RESERVED2[2]; + __IOM uint16_t TCDRA; /*!< (@ 0x00000214) Timer Cycle Data Register A */ + __IOM uint16_t TDDRA; /*!< (@ 0x00000216) Timer Dead Time Data Register A */ + __IM uint16_t RESERVED3[4]; + __IM uint16_t TCNTSA; /*!< (@ 0x00000220) Timer Subcounter A */ + __IOM uint16_t TCBRA; /*!< (@ 0x00000222) Timer Cycle Buffer Register A */ + __IM uint16_t RESERVED4[6]; + + union + { + __IOM uint8_t TITCR1A; /*!< (@ 0x00000230) Timer Interrupt Skipping Set Register 1A */ + + struct + { + __IOM uint8_t T4VCOR : 3; /*!< [2..0] TCIV4 Interrupt Skipping Count Setting */ + __IOM uint8_t T4VEN : 1; /*!< [3..3] TCIV4 Interrupt Skipping Enable */ + __IOM uint8_t T3ACOR : 3; /*!< [6..4] TGIA3 Interrupt Skipping Count Setting */ + __IOM uint8_t T3AEN : 1; /*!< [7..7] TGIA3 Interrupt Skipping Enable */ + } TITCR1A_b; + }; + + union + { + __IM uint8_t TITCNT1A; /*!< (@ 0x00000231) Timer Interrupt Skipping Counter 1A */ + + struct + { + __IM uint8_t T4VCNT : 3; /*!< [2..0] TCIV4 Interrupt Counter */ + uint8_t : 1; + __IM uint8_t T3ACNT : 3; /*!< [6..4] TGIA3 Interrupt Counter */ + uint8_t : 1; + } TITCNT1A_b; + }; + + union + { + __IOM uint8_t TBTERA; /*!< (@ 0x00000232) Timer Buffer Transfer Set Register A */ + + struct + { + __IOM uint8_t BTE : 2; /*!< [1..0] Buffer Transfer Disable and Interrupt Skipping Link Setting */ + uint8_t : 6; + } TBTERA_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t TDERA; /*!< (@ 0x00000234) Timer Dead Time Enable Register A */ + + struct + { + __IOM uint8_t TDER : 1; /*!< [0..0] Dead Time Enable */ + uint8_t : 7; + } TDERA_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t TOLBRA; /*!< (@ 0x00000236) Timer Output Level Buffer Register A */ + + struct + { + __IOM uint8_t OLS1P : 1; /*!< [0..0] Output Level Select 1P */ + __IOM uint8_t OLS1N : 1; /*!< [1..1] Output Level Select 1N */ + __IOM uint8_t OLS2P : 1; /*!< [2..2] Output Level Select 2P */ + __IOM uint8_t OLS2N : 1; /*!< [3..3] Output Level Select 2N */ + __IOM uint8_t OLS3P : 1; /*!< [4..4] Output Level Select 3P */ + __IOM uint8_t OLS3N : 1; /*!< [5..5] Output Level Select 3N */ + uint8_t : 2; + } TOLBRA_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint8_t TITMRA; /*!< (@ 0x0000023A) Timer Interrupt Skipping Mode Register A */ + + struct + { + __IOM uint8_t TITM : 1; /*!< [0..0] Interrupt Skipping Function Select */ + uint8_t : 7; + } TITMRA_b; + }; + + union + { + __IOM uint8_t TITCR2A; /*!< (@ 0x0000023B) Timer Interrupt Skipping Set Register 2A */ + + struct + { + __IOM uint8_t TRG4COR : 3; /*!< [2..0] TRG4AN/TRG4BN Interrupt Skipping Count Setting */ + uint8_t : 5; + } TITCR2A_b; + }; + + union + { + __IM uint8_t TITCNT2A; /*!< (@ 0x0000023C) Timer Interrupt Skipping Counter 2A */ + + struct + { + __IM uint8_t TRG4CNT : 3; /*!< [2..0] TRG4AN/TRG4BN Interrupt Counter */ + uint8_t : 5; + } TITCNT2A_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10[17]; + + union + { + __IOM uint8_t TWCRA; /*!< (@ 0x00000260) Timer Waveform Control Register A */ + + struct + { + __IOM uint8_t WRE : 1; /*!< [0..0] Waveform Retain Enable */ + __IOM uint8_t SCC : 1; /*!< [1..1] Synchronous Clearing Control (Only valid in TWCRB) */ + uint8_t : 5; + __IOM uint8_t CCE : 1; /*!< [7..7] Compare Match Clear Enable */ + } TWCRA_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12[7]; + + union + { + __IOM uint8_t TMDR2A; /*!< (@ 0x00000270) Timer Mode Register 2A */ + + struct + { + __IOM uint8_t DRS : 1; /*!< [0..0] Double Buffer Select */ + uint8_t : 7; + } TMDR2A_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14[7]; + + union + { + __IOM uint8_t TSTRA; /*!< (@ 0x00000280) Timer Start Register A */ + + struct + { + __IOM uint8_t CST0 : 1; /*!< [0..0] Counter Start 0 */ + __IOM uint8_t CST1 : 1; /*!< [1..1] Counter Start 1 */ + __IOM uint8_t CST2 : 1; /*!< [2..2] Counter Start 2 */ + __IOM uint8_t CST8 : 1; /*!< [3..3] Counter Start 8 */ + uint8_t : 2; + __IOM uint8_t CST3 : 1; /*!< [6..6] Counter Start 3 */ + __IOM uint8_t CST4 : 1; /*!< [7..7] Counter Start 4 */ + } TSTRA_b; + }; + + union + { + __IOM uint8_t TSYRA; /*!< (@ 0x00000281) Timer Synchronous Register A */ + + struct + { + __IOM uint8_t SYNC0 : 1; /*!< [0..0] Timer Synchronous Operation 0 */ + __IOM uint8_t SYNC1 : 1; /*!< [1..1] Timer Synchronous Operation 1 */ + __IOM uint8_t SYNC2 : 1; /*!< [2..2] Timer Synchronous Operation 2 */ + uint8_t : 3; + __IOM uint8_t SYNC3 : 1; /*!< [6..6] Timer Synchronous Operation 3 */ + __IOM uint8_t SYNC4 : 1; /*!< [7..7] Timer Synchronous Operation 4 */ + } TSYRA_b; + }; + + union + { + __IOM uint8_t TCSYSTR; /*!< (@ 0x00000282) Timer Counter Synchronous Start Register */ + + struct + { + __IOM uint8_t SCH7 : 1; /*!< [0..0] Synchronous Start 7 */ + __IOM uint8_t SCH6 : 1; /*!< [1..1] Synchronous Start 6 */ + uint8_t : 1; + __IOM uint8_t SCH4 : 1; /*!< [3..3] Synchronous Start 4 */ + __IOM uint8_t SCH3 : 1; /*!< [4..4] Synchronous Start 3 */ + __IOM uint8_t SCH2 : 1; /*!< [5..5] Synchronous Start 2 */ + __IOM uint8_t SCH1 : 1; /*!< [6..6] Synchronous Start 1 */ + __IOM uint8_t SCH0 : 1; /*!< [7..7] Synchronous Start 0 */ + } TCSYSTR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t TRWERA; /*!< (@ 0x00000284) Timer Read/Write Enable Register */ + + struct + { + __IOM uint8_t RWE : 1; /*!< [0..0] Read/Write Enable */ + uint8_t : 7; + } TRWERA_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17[962]; + + union + { + __IOM uint8_t TOERB; /*!< (@ 0x00000A0A) Timer Output Master Enable Register B */ + + struct + { + __IOM uint8_t OE6B : 1; /*!< [0..0] Master Enable MTIOC6B */ + __IOM uint8_t OE7A : 1; /*!< [1..1] Master Enable MTIOC7A */ + __IOM uint8_t OE7B : 1; /*!< [2..2] Master Enable MTIOC7B */ + __IOM uint8_t OE6D : 1; /*!< [3..3] Master Enable MTIOC6D */ + __IOM uint8_t OE7C : 1; /*!< [4..4] Master Enable MTIOC7C */ + __IOM uint8_t OE7D : 1; /*!< [5..5] Master Enable MTIOC7D */ + uint8_t : 2; + } TOERB_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint8_t TOCR1B; /*!< (@ 0x00000A0E) Timer Output Control Register 1B */ + + struct + { + __IOM uint8_t OLSP : 1; /*!< [0..0] Output Level Select P */ + __IOM uint8_t OLSN : 1; /*!< [1..1] Output Level Select N */ + __IOM uint8_t TOCS : 1; /*!< [2..2] TOC Select */ + __IOM uint8_t TOCL : 1; /*!< [3..3] TOC Register Write Protection */ + uint8_t : 2; + __IOM uint8_t PSYE : 1; /*!< [6..6] PWM Synchronous Output Enable */ + uint8_t : 1; + } TOCR1B_b; + }; + + union + { + __IOM uint8_t TOCR2B; /*!< (@ 0x00000A0F) Timer Output Control Register 2B */ + + struct + { + __IOM uint8_t OLS1P : 1; /*!< [0..0] Output Level Select 1P */ + __IOM uint8_t OLS1N : 1; /*!< [1..1] Output Level Select 1N */ + __IOM uint8_t OLS2P : 1; /*!< [2..2] Output Level Select 2P */ + __IOM uint8_t OLS2N : 1; /*!< [3..3] Output Level Select 2N */ + __IOM uint8_t OLS3P : 1; /*!< [4..4] Output Level Select 3P */ + __IOM uint8_t OLS3N : 1; /*!< [5..5] Output Level Select 3N */ + __IOM uint8_t BF : 2; /*!< [7..6] TOLBR Buffer Transfer Timing Select */ + } TOCR2B_b; + }; + __IM uint16_t RESERVED20[2]; + __IOM uint16_t TCDRB; /*!< (@ 0x00000A14) Timer Cycle Data Register B */ + __IOM uint16_t TDDRB; /*!< (@ 0x00000A16) Timer Dead Time Data Register B */ + __IM uint16_t RESERVED21[4]; + __IM uint16_t TCNTSB; /*!< (@ 0x00000A20) Timer Subcounter B */ + __IOM uint16_t TCBRB; /*!< (@ 0x00000A22) Timer Cycle Buffer Register B */ + __IM uint16_t RESERVED22[6]; + + union + { + __IOM uint8_t TITCR1B; /*!< (@ 0x00000A30) Timer Interrupt Skipping Set Register 1B */ + + struct + { + __IOM uint8_t T7VCOR : 3; /*!< [2..0] TCIV7 Interrupt Skipping Count Setting */ + __IOM uint8_t T7VEN : 1; /*!< [3..3] TCIV7 Interrupt Skipping Enable */ + __IOM uint8_t T6ACOR : 3; /*!< [6..4] TGIA6 Interrupt Skipping Count Setting */ + __IOM uint8_t T6AEN : 1; /*!< [7..7] TGIA6 Interrupt Skipping Enable */ + } TITCR1B_b; + }; + + union + { + __IM uint8_t TITCNT1B; /*!< (@ 0x00000A31) Timer Interrupt Skipping Counter 1B */ + + struct + { + __IM uint8_t T7VCNT : 3; /*!< [2..0] TCIV7 Interrupt Counter */ + uint8_t : 1; + __IM uint8_t T6ACNT : 3; /*!< [6..4] TGIA6 Interrupt Counter */ + uint8_t : 1; + } TITCNT1B_b; + }; + + union + { + __IOM uint8_t TBTERB; /*!< (@ 0x00000A32) Timer Buffer Transfer Set Register B */ + + struct + { + __IOM uint8_t BTE : 2; /*!< [1..0] Buffer Transfer Disable and Interrupt Skipping Link Setting */ + uint8_t : 6; + } TBTERB_b; + }; + __IM uint8_t RESERVED23; + + union + { + __IOM uint8_t TDERB; /*!< (@ 0x00000A34) Timer Dead Time Enable Register B */ + + struct + { + __IOM uint8_t TDER : 1; /*!< [0..0] Dead Time Enable */ + uint8_t : 7; + } TDERB_b; + }; + __IM uint8_t RESERVED24; + + union + { + __IOM uint8_t TOLBRB; /*!< (@ 0x00000A36) Timer Output Level Buffer Register B */ + + struct + { + __IOM uint8_t OLS1P : 1; /*!< [0..0] Output Level Select 1P */ + __IOM uint8_t OLS1N : 1; /*!< [1..1] Output Level Select 1N */ + __IOM uint8_t OLS2P : 1; /*!< [2..2] Output Level Select 2P */ + __IOM uint8_t OLS2N : 1; /*!< [3..3] Output Level Select 2N */ + __IOM uint8_t OLS3P : 1; /*!< [4..4] Output Level Select 3P */ + __IOM uint8_t OLS3N : 1; /*!< [5..5] Output Level Select 3N */ + uint8_t : 2; + } TOLBRB_b; + }; + __IM uint8_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t TITMRB; /*!< (@ 0x00000A3A) Timer Interrupt Skipping Mode Register B */ + + struct + { + __IOM uint8_t TITM : 1; /*!< [0..0] Interrupt Skipping Function Select */ + uint8_t : 7; + } TITMRB_b; + }; + + union + { + __IOM uint8_t TITCR2B; /*!< (@ 0x00000A3B) Timer Interrupt Skipping Set Register 2B */ + + struct + { + __IOM uint8_t TRG7COR : 3; /*!< [2..0] TRG7AN/TRG7BN Interrupt Skipping Count Setting */ + uint8_t : 5; + } TITCR2B_b; + }; + + union + { + __IM uint8_t TITCNT2B; /*!< (@ 0x00000A3C) Timer Interrupt Skipping Counter 2B */ + + struct + { + __IM uint8_t TRG7CNT : 3; /*!< [2..0] TRG7AN/TRG7BN Interrupt Counter */ + uint8_t : 5; + } TITCNT2B_b; + }; + __IM uint8_t RESERVED27; + __IM uint16_t RESERVED28[17]; + + union + { + __IOM uint8_t TWCRB; /*!< (@ 0x00000A60) Timer Waveform Control Register B */ + + struct + { + __IOM uint8_t WRE : 1; /*!< [0..0] Waveform Retain Enable */ + __IOM uint8_t SCC : 1; /*!< [1..1] Synchronous Clearing Control (Only valid in TWCRB) */ + uint8_t : 5; + __IOM uint8_t CCE : 1; /*!< [7..7] Compare Match Clear Enable */ + } TWCRB_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30[7]; + + union + { + __IOM uint8_t TMDR2B; /*!< (@ 0x00000A70) Timer Mode Register 2B */ + + struct + { + __IOM uint8_t DRS : 1; /*!< [0..0] Double Buffer Select */ + uint8_t : 7; + } TMDR2B_b; + }; + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32[7]; + + union + { + __IOM uint8_t TSTRB; /*!< (@ 0x00000A80) Timer Start Register B */ + + struct + { + uint8_t : 6; + __IOM uint8_t CST6 : 1; /*!< [6..6] Counter Start 6 */ + __IOM uint8_t CST7 : 1; /*!< [7..7] Counter Start 7 */ + } TSTRB_b; + }; + + union + { + __IOM uint8_t TSYRB; /*!< (@ 0x00000A81) Timer Synchronous Register B */ + + struct + { + uint8_t : 6; + __IOM uint8_t SYNC6 : 1; /*!< [6..6] Timer Synchronous Operation 6 */ + __IOM uint8_t SYNC7 : 1; /*!< [7..7] Timer Synchronous Operation 7 */ + } TSYRB_b; + }; + __IM uint16_t RESERVED33; + + union + { + __IOM uint8_t TRWERB; /*!< (@ 0x00000A84) Timer Read/Write Enable Register */ + + struct + { + __IOM uint8_t RWE : 1; /*!< [0..0] Read/Write Enable */ + uint8_t : 7; + } TRWERB_b; + }; + __IM uint8_t RESERVED34; + __IM uint16_t RESERVED35; +} R_MTU_Type; /*!< Size = 2696 (0xa88) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU3 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 3 (R_MTU3) + */ + +typedef struct /*!< (@ 0x90001100) R_MTU3 Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000100) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000102) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + uint8_t : 2; + } TMDR1_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000104) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000105) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000108) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5[3]; + __IOM uint16_t TCNT; /*!< (@ 0x00000110) Timer Counter */ + __IM uint16_t RESERVED6[3]; + __IOM uint16_t TGRA; /*!< (@ 0x00000118) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000011A) Timer General Register B */ + __IM uint16_t RESERVED7[4]; + __IOM uint16_t TGRC; /*!< (@ 0x00000124) Timer General Register C */ + __IOM uint16_t TGRD; /*!< (@ 0x00000126) Timer General Register D */ + __IM uint16_t RESERVED8[2]; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x0000012C) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10[5]; + + union + { + __IOM uint8_t TBTM; /*!< (@ 0x00000138) Timer Buffer Operation Transfer Mode Register */ + + struct + { + __IOM uint8_t TTSA : 1; /*!< [0..0] Timing Select A */ + __IOM uint8_t TTSB : 1; /*!< [1..1] Timing Select B */ + uint8_t : 6; + } TBTM_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12[9]; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x0000014C) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14[18]; + __IOM uint16_t TGRE; /*!< (@ 0x00000172) Timer General Register E */ +} R_MTU3_Type; /*!< Size = 372 (0x174) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU4 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 4 (R_MTU4) + */ + +typedef struct /*!< (@ 0x90001200) R_MTU4 Structure */ +{ + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000001) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000003) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + uint8_t : 2; + } TMDR1_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000006) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000007) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000009) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 1; + __IOM uint8_t TTGE2 : 1; /*!< [6..6] A/D Converter Start Request Enable 2 */ + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + __IM uint16_t RESERVED4[4]; + __IOM uint16_t TCNT; /*!< (@ 0x00000012) Timer Counter */ + __IM uint16_t RESERVED5[4]; + __IOM uint16_t TGRA; /*!< (@ 0x0000001C) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000001E) Timer General Register B */ + __IM uint16_t RESERVED6[4]; + __IOM uint16_t TGRC; /*!< (@ 0x00000028) Timer General Register C */ + __IOM uint16_t TGRD; /*!< (@ 0x0000002A) Timer General Register D */ + __IM uint8_t RESERVED7; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x0000002D) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IM uint16_t RESERVED8[5]; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t TBTM; /*!< (@ 0x00000039) Timer Buffer Operation Transfer Mode Register */ + + struct + { + __IOM uint8_t TTSA : 1; /*!< [0..0] Timing Select A */ + __IOM uint8_t TTSB : 1; /*!< [1..1] Timing Select B */ + uint8_t : 6; + } TBTM_b; + }; + __IM uint16_t RESERVED10[3]; + + union + { + __IOM uint16_t TADCR; /*!< (@ 0x00000040) Timer A/D Converter Start Request Control Register */ + + struct + { + __IOM uint16_t ITB4VE : 1; /*!< [0..0] TCIV4 Interrupt Skipping Link Enable */ + __IOM uint16_t ITB3AE : 1; /*!< [1..1] TGIA3 Interrupt Skipping Link Enable */ + __IOM uint16_t ITA4VE : 1; /*!< [2..2] TCIV4 Interrupt Skipping Link Enable */ + __IOM uint16_t ITA3AE : 1; /*!< [3..3] TGIA3 Interrupt Skipping Link Enable */ + __IOM uint16_t DT4BE : 1; /*!< [4..4] Down-Count TRG4BN Enable */ + __IOM uint16_t UT4BE : 1; /*!< [5..5] Up-Count TRG4BN Enable */ + __IOM uint16_t DT4AE : 1; /*!< [6..6] Down-Count TRG4AN Enable */ + __IOM uint16_t UT4AE : 1; /*!< [7..7] Up-Count TRG4AN Enable */ + uint16_t : 6; + __IOM uint16_t BF : 2; /*!< [15..14] MTU4.TADCOBRA/TADCOBRB Transfer Timing Select */ + } TADCR_b; + }; + __IM uint16_t RESERVED11; + __IOM uint16_t TADCORA; /*!< (@ 0x00000044) Timer A/D Converter Start Request Cycle Set Register + * A */ + __IOM uint16_t TADCORB; /*!< (@ 0x00000046) Timer A/D Converter Start Request Cycle Set Register + * B */ + __IOM uint16_t TADCOBRA; /*!< (@ 0x00000048) Timer A/D Converter Start Request Cycle Set Buffer + * Register A */ + __IOM uint16_t TADCOBRB; /*!< (@ 0x0000004A) Timer A/D Converter Start Request Cycle Set Buffer + * Register B */ + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x0000004D) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint16_t RESERVED13[19]; + __IOM uint16_t TGRE; /*!< (@ 0x00000074) Timer General Register E */ + __IOM uint16_t TGRF; /*!< (@ 0x00000076) Timer General Register F */ +} R_MTU4_Type; /*!< Size = 120 (0x78) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU_NF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Noise Filter (R_MTU_NF) + */ + +typedef struct /*!< (@ 0x90001290) R_MTU_NF Structure */ +{ + union + { + __IOM uint8_t NFCR0; /*!< (@ 0x00000000) Noise Filter Control Register 0 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR0_b; + }; + + union + { + __IOM uint8_t NFCR1; /*!< (@ 0x00000001) Noise Filter Control Register 1 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + uint8_t : 2; + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR1_b; + }; + + union + { + __IOM uint8_t NFCR2; /*!< (@ 0x00000002) Noise Filter Control Register 2 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + uint8_t : 2; + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR2_b; + }; + + union + { + __IOM uint8_t NFCR3; /*!< (@ 0x00000003) Noise Filter Control Register 3 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR3_b; + }; + + union + { + __IOM uint8_t NFCR4; /*!< (@ 0x00000004) Noise Filter Control Register 4 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR4_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t NFCR8; /*!< (@ 0x00000008) Noise Filter Control Register 8 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR8_b; + }; + + union + { + __IOM uint8_t NFCRC; /*!< (@ 0x00000009) Noise Filter Control Register C */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCRC_b; + }; + __IM uint8_t RESERVED1[2041]; + + union + { + __IOM uint8_t NFCR6; /*!< (@ 0x00000803) Noise Filter Control Register 6 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR6_b; + }; + + union + { + __IOM uint8_t NFCR7; /*!< (@ 0x00000804) Noise Filter Control Register 7 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR7_b; + }; + + union + { + __IOM uint8_t NFCR5; /*!< (@ 0x00000805) Noise Filter Control Register 5 */ + + struct + { + __IOM uint8_t NFUEN : 1; /*!< [0..0] Noise Filter U Enable */ + __IOM uint8_t NFVEN : 1; /*!< [1..1] Noise Filter V Enable */ + __IOM uint8_t NFWEN : 1; /*!< [2..2] Noise Filter W Enable */ + uint8_t : 1; + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR5_b; + }; +} R_MTU_NF_Type; /*!< Size = 2054 (0x806) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 0 (R_MTU0) + */ + +typedef struct /*!< (@ 0x90001300) R_MTU0 Structure */ +{ + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000001) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + __IOM uint8_t BFE : 1; /*!< [6..6] Buffer Operation E */ + uint8_t : 1; + } TMDR1_b; + }; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000002) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000003) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000004) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + __IM uint8_t RESERVED; + __IOM uint16_t TCNT; /*!< (@ 0x00000006) Timer Counter */ + __IOM uint16_t TGRA; /*!< (@ 0x00000008) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000000A) Timer General Register B */ + __IOM uint16_t TGRC; /*!< (@ 0x0000000C) Timer General Register C */ + __IOM uint16_t TGRD; /*!< (@ 0x0000000E) Timer General Register D */ + __IM uint16_t RESERVED1[8]; + __IOM uint16_t TGRE; /*!< (@ 0x00000020) Timer General Register E */ + __IOM uint16_t TGRF; /*!< (@ 0x00000022) Timer General Register F */ + + union + { + __IOM uint8_t TIER2; /*!< (@ 0x00000024) Timer Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t TGIEE : 1; /*!< [0..0] TGR Interrupt Enable E */ + __IOM uint8_t TGIEF : 1; /*!< [1..1] TGR Interrupt Enable F */ + uint8_t : 5; + __IOM uint8_t TTGE2 : 1; /*!< [7..7] A/D Converter Start Request Enable 2 */ + } TIER2_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t TBTM; /*!< (@ 0x00000026) Timer Buffer Operation Transfer Mode Register */ + + struct + { + __IOM uint8_t TTSA : 1; /*!< [0..0] Timing Select A */ + __IOM uint8_t TTSB : 1; /*!< [1..1] Timing Select B */ + __IOM uint8_t TTSE : 1; /*!< [2..2] Timing Select E */ + uint8_t : 5; + } TBTM_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x00000028) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; +} R_MTU0_Type; /*!< Size = 44 (0x2c) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU1 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 1 (R_MTU1) + */ + +typedef struct /*!< (@ 0x90001380) R_MTU1 Structure */ +{ + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000001) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + uint8_t : 4; + } TMDR1_b; + }; + + union + { + __IOM uint8_t TIOR; /*!< (@ 0x00000002) Timer I/O Control Register */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIOR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000004) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + uint8_t : 2; + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + __IOM uint8_t TCIEU : 1; /*!< [5..5] Underflow Interrupt Enable */ + uint8_t : 1; + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x00000005) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IOM uint16_t TCNT; /*!< (@ 0x00000006) Timer Counter */ + __IOM uint16_t TGRA; /*!< (@ 0x00000008) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000000A) Timer General Register B */ + __IM uint32_t RESERVED1; + + union + { + __IOM uint8_t TICCR; /*!< (@ 0x00000010) Timer Input Capture Control Register */ + + struct + { + __IOM uint8_t I1AE : 1; /*!< [0..0] Input Capture Enable */ + __IOM uint8_t I1BE : 1; /*!< [1..1] Input Capture Enable */ + __IOM uint8_t I2AE : 1; /*!< [2..2] Input Capture Enable */ + __IOM uint8_t I2BE : 1; /*!< [3..3] Input Capture Enable */ + uint8_t : 4; + } TICCR_b; + }; + + union + { + __IOM uint8_t TMDR3; /*!< (@ 0x00000011) Timer Mode Register 3 */ + + struct + { + __IOM uint8_t LWA : 1; /*!< [0..0] MTU1/MTU2 Combination Longword Access Control */ + __IOM uint8_t PHCKSEL : 1; /*!< [1..1] External Input Phase Clock Select */ + uint8_t : 6; + } TMDR3_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x00000014) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t PCB : 2; /*!< [4..3] Functional Expansion Control for Phase Counting Modes + * 2, 3, and 5 */ + uint8_t : 3; + } TCR2_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + __IOM uint32_t TCNTLW; /*!< (@ 0x00000020) Timer Longword Counter */ + __IOM uint32_t TGRALW; /*!< (@ 0x00000024) Timer Longword General Register A */ + __IOM uint32_t TGRBLW; /*!< (@ 0x00000028) Timer Longword General Register B */ +} R_MTU1_Type; /*!< Size = 44 (0x2c) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU2 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 2 (R_MTU2) + */ + +typedef struct /*!< (@ 0x90001400) R_MTU2 Structure */ +{ + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000001) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + uint8_t : 4; + } TMDR1_b; + }; + + union + { + __IOM uint8_t TIOR; /*!< (@ 0x00000002) Timer I/O Control Register */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIOR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000004) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + uint8_t : 2; + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + __IOM uint8_t TCIEU : 1; /*!< [5..5] Underflow Interrupt Enable */ + uint8_t : 1; + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x00000005) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IOM uint16_t TCNT; /*!< (@ 0x00000006) Timer Counter */ + __IOM uint16_t TGRA; /*!< (@ 0x00000008) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000000A) Timer General Register B */ + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x0000000C) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t PCB : 2; /*!< [4..3] Functional Expansion Control for Phase Counting Modes + * 2, 3, and 5 */ + uint8_t : 3; + } TCR2_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_MTU2_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU8 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 8 (R_MTU8) + */ + +typedef struct /*!< (@ 0x90001600) R_MTU8 Structure */ +{ + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000001) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + uint8_t : 2; + } TMDR1_b; + }; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000002) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000003) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000004) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 3; + } TIER_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x00000006) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint8_t RESERVED1; + __IOM uint32_t TCNT; /*!< (@ 0x00000008) Timer Counter */ + __IOM uint32_t TGRA; /*!< (@ 0x0000000C) Timer General Register A */ + __IOM uint32_t TGRB; /*!< (@ 0x00000010) Timer General Register B */ + __IOM uint32_t TGRC; /*!< (@ 0x00000014) Timer General Register C */ + __IOM uint32_t TGRD; /*!< (@ 0x00000018) Timer General Register D */ +} R_MTU8_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU6 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 6 (R_MTU6) + */ + +typedef struct /*!< (@ 0x90001900) R_MTU6 Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000100) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000102) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + uint8_t : 2; + } TMDR1_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000104) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000105) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000108) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5[3]; + __IOM uint16_t TCNT; /*!< (@ 0x00000110) Timer Counter */ + __IM uint16_t RESERVED6[3]; + __IOM uint16_t TGRA; /*!< (@ 0x00000118) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000011A) Timer General Register B */ + __IM uint16_t RESERVED7[4]; + __IOM uint16_t TGRC; /*!< (@ 0x00000124) Timer General Register C */ + __IOM uint16_t TGRD; /*!< (@ 0x00000126) Timer General Register D */ + __IM uint16_t RESERVED8[2]; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x0000012C) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10[5]; + + union + { + __IOM uint8_t TBTM; /*!< (@ 0x00000138) Timer Buffer Operation Transfer Mode Register */ + + struct + { + __IOM uint8_t TTSA : 1; /*!< [0..0] Timing Select A */ + __IOM uint8_t TTSB : 1; /*!< [1..1] Timing Select B */ + uint8_t : 6; + } TBTM_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12[9]; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x0000014C) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t TSYCR; /*!< (@ 0x00000150) Timer Synchronous Clear Register */ + + struct + { + __IOM uint8_t CE2B : 1; /*!< [0..0] Clear Enable 2B */ + __IOM uint8_t CE2A : 1; /*!< [1..1] Clear Enable 2A */ + __IOM uint8_t CE1B : 1; /*!< [2..2] Clear Enable 1B */ + __IOM uint8_t CE1A : 1; /*!< [3..3] Clear Enable 1A */ + __IOM uint8_t CE0D : 1; /*!< [4..4] Clear Enable 0D */ + __IOM uint8_t CE0C : 1; /*!< [5..5] Clear Enable 0C */ + __IOM uint8_t CE0B : 1; /*!< [6..6] Clear Enable 0B */ + __IOM uint8_t CE0A : 1; /*!< [7..7] Clear Enable 0A */ + } TSYCR_b; + }; + __IM uint8_t RESERVED15; + __IM uint16_t RESERVED16[16]; + __IOM uint16_t TGRE; /*!< (@ 0x00000172) Timer General Register E */ +} R_MTU6_Type; /*!< Size = 372 (0x174) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU7 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 7 (R_MTU7) + */ + +typedef struct /*!< (@ 0x90001A00) R_MTU7 Structure */ +{ + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000001) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000003) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + uint8_t : 2; + } TMDR1_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000006) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000007) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000009) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 1; + __IOM uint8_t TTGE2 : 1; /*!< [6..6] A/D Converter Start Request Enable 2 */ + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + __IM uint16_t RESERVED4[4]; + __IOM uint16_t TCNT; /*!< (@ 0x00000012) Timer Counter */ + __IM uint16_t RESERVED5[4]; + __IOM uint16_t TGRA; /*!< (@ 0x0000001C) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000001E) Timer General Register B */ + __IM uint16_t RESERVED6[4]; + __IOM uint16_t TGRC; /*!< (@ 0x00000028) Timer General Register C */ + __IOM uint16_t TGRD; /*!< (@ 0x0000002A) Timer General Register D */ + __IM uint8_t RESERVED7; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x0000002D) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IM uint16_t RESERVED8[5]; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t TBTM; /*!< (@ 0x00000039) Timer Buffer Operation Transfer Mode Register */ + + struct + { + __IOM uint8_t TTSA : 1; /*!< [0..0] Timing Select A */ + __IOM uint8_t TTSB : 1; /*!< [1..1] Timing Select B */ + uint8_t : 6; + } TBTM_b; + }; + __IM uint16_t RESERVED10[3]; + + union + { + __IOM uint16_t TADCR; /*!< (@ 0x00000040) Timer A/D Converter Start Request Control Register */ + + struct + { + __IOM uint16_t ITB7VE : 1; /*!< [0..0] TCIV7 Interrupt Skipping Link Enable */ + __IOM uint16_t ITB6AE : 1; /*!< [1..1] TGIA6 Interrupt Skipping Link Enable */ + __IOM uint16_t ITA7VE : 1; /*!< [2..2] TCIV7 Interrupt Skipping Link Enable */ + __IOM uint16_t ITA6AE : 1; /*!< [3..3] TGIA6 Interrupt Skipping Link Enable */ + __IOM uint16_t DT7BE : 1; /*!< [4..4] Down-Count TRG7BN Enable */ + __IOM uint16_t UT7BE : 1; /*!< [5..5] Up-Count TRG7BN Enable */ + __IOM uint16_t DT7AE : 1; /*!< [6..6] Down-Count TRG7AN Enable */ + __IOM uint16_t UT7AE : 1; /*!< [7..7] Up-Count TRG7AN Enable */ + uint16_t : 6; + __IOM uint16_t BF : 2; /*!< [15..14] MTU7.TADCOBRA/TADCOBRB Transfer Timing Select */ + } TADCR_b; + }; + __IM uint16_t RESERVED11; + __IOM uint16_t TADCORA; /*!< (@ 0x00000044) Timer A/D Converter Start Request Cycle Set Register + * A */ + __IOM uint16_t TADCORB; /*!< (@ 0x00000046) Timer A/D Converter Start Request Cycle Set Register + * B */ + __IOM uint16_t TADCOBRA; /*!< (@ 0x00000048) Timer A/D Converter Start Request Cycle Set Buffer + * Register A */ + __IOM uint16_t TADCOBRB; /*!< (@ 0x0000004A) Timer A/D Converter Start Request Cycle Set Buffer + * Register B */ + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x0000004D) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint16_t RESERVED13[19]; + __IOM uint16_t TGRE; /*!< (@ 0x00000074) Timer General Register E */ + __IOM uint16_t TGRF; /*!< (@ 0x00000076) Timer General Register F */ +} R_MTU7_Type; /*!< Size = 120 (0x78) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU5 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 5 (R_MTU5) + */ + +typedef struct /*!< (@ 0x90001C00) R_MTU5 Structure */ +{ + __IM uint16_t RESERVED[64]; + __IOM uint16_t TCNTU; /*!< (@ 0x00000080) Timer Counter U */ + __IOM uint16_t TGRU; /*!< (@ 0x00000082) Timer General Register U */ + + union + { + __IOM uint8_t TCRU; /*!< (@ 0x00000084) Timer Control Register U */ + + struct + { + __IOM uint8_t TPSC : 2; /*!< [1..0] Time Prescaler Select */ + uint8_t : 6; + } TCRU_b; + }; + + union + { + __IOM uint8_t TCR2U; /*!< (@ 0x00000085) Timer Control Register 2U */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + uint8_t : 3; + } TCR2U_b; + }; + + union + { + __IOM uint8_t TIORU; /*!< (@ 0x00000086) Timer I/O Control Register U */ + + struct + { + __IOM uint8_t IOC : 5; /*!< [4..0] I/O Control C */ + uint8_t : 3; + } TIORU_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[4]; + __IOM uint16_t TCNTV; /*!< (@ 0x00000090) Timer Counter V */ + __IOM uint16_t TGRV; /*!< (@ 0x00000092) Timer General Register V */ + + union + { + __IOM uint8_t TCRV; /*!< (@ 0x00000094) Timer Control Register V */ + + struct + { + __IOM uint8_t TPSC : 2; /*!< [1..0] Time Prescaler Select */ + uint8_t : 6; + } TCRV_b; + }; + + union + { + __IOM uint8_t TCR2V; /*!< (@ 0x00000095) Timer Control Register 2V */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + uint8_t : 3; + } TCR2V_b; + }; + + union + { + __IOM uint8_t TIORV; /*!< (@ 0x00000096) Timer I/O Control Register V */ + + struct + { + __IOM uint8_t IOC : 5; /*!< [4..0] I/O Control C */ + uint8_t : 3; + } TIORV_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[4]; + __IOM uint16_t TCNTW; /*!< (@ 0x000000A0) Timer Counter W */ + __IOM uint16_t TGRW; /*!< (@ 0x000000A2) Timer General Register W */ + + union + { + __IOM uint8_t TCRW; /*!< (@ 0x000000A4) Timer Control Register W */ + + struct + { + __IOM uint8_t TPSC : 2; /*!< [1..0] Time Prescaler Select */ + uint8_t : 6; + } TCRW_b; + }; + + union + { + __IOM uint8_t TCR2W; /*!< (@ 0x000000A5) Timer Control Register 2W */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + uint8_t : 3; + } TCR2W_b; + }; + + union + { + __IOM uint8_t TIORW; /*!< (@ 0x000000A6) Timer I/O Control Register W */ + + struct + { + __IOM uint8_t IOC : 5; /*!< [4..0] I/O Control C */ + uint8_t : 3; + } TIORW_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6[5]; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x000000B2) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIE5W : 1; /*!< [0..0] TGR Interrupt Enable 5W */ + __IOM uint8_t TGIE5V : 1; /*!< [1..1] TGR Interrupt Enable 5V */ + __IOM uint8_t TGIE5U : 1; /*!< [2..2] TGR Interrupt Enable 5U */ + uint8_t : 5; + } TIER_b; + }; + __IM uint8_t RESERVED7; + + union + { + __IOM uint8_t TSTR; /*!< (@ 0x000000B4) Timer Start Register */ + + struct + { + __IOM uint8_t CSTW5 : 1; /*!< [0..0] Counter Start W5 */ + __IOM uint8_t CSTV5 : 1; /*!< [1..1] Counter Start V5 */ + __IOM uint8_t CSTU5 : 1; /*!< [2..2] Counter Start U5 */ + uint8_t : 5; + } TSTR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t TCNTCMPCLR; /*!< (@ 0x000000B6) Timer Compare Match Clear Register */ + + struct + { + __IOM uint8_t CMPCLR5W : 1; /*!< [0..0] TCNT Compare Clear 5W */ + __IOM uint8_t CMPCLR5V : 1; /*!< [1..1] TCNT Compare Clear 5V */ + __IOM uint8_t CMPCLR5U : 1; /*!< [2..2] TCNT Compare Clear 5U */ + uint8_t : 5; + } TCNTCMPCLR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; +} R_MTU5_Type; /*!< Size = 186 (0xba) */ + +/* =========================================================================================================================== */ +/* ================ R_TFU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Trigonometric Function Unit (R_TFU) + */ + +typedef struct /*!< (@ 0x90003000) R_TFU Structure */ +{ + __IM uint32_t RESERVED[2]; + + union + { + __IM uint8_t TRGSTS; /*!< (@ 0x00000008) Trigonometric Status Register */ + + struct + { + __IM uint8_t BSYF : 1; /*!< [0..0] Calculation in progress flag */ + __IM uint8_t ERRF : 1; /*!< [1..1] Input error flag */ + uint8_t : 6; + } TRGSTS_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3; + + union + { + __IOM float SCDT0; /*!< (@ 0x00000010) Sine Cosine Data Register 0 */ + + struct + { + __IOM uint32_t SCDT0 : 32; /*!< [31..0] Sine Cosine Data Register 0 (single-precision floating-point) */ + } SCDT0_b; + }; + + union + { + __IOM float SCDT1; /*!< (@ 0x00000014) Sine Cosine Data Register 1 */ + + struct + { + __IOM uint32_t SCDT1 : 32; /*!< [31..0] Sine Cosine Data Register 1 (single-precision floating-point) */ + } SCDT1_b; + }; + + union + { + __IOM float ATDT0; /*!< (@ 0x00000018) Arctangent Data Register 0 */ + + struct + { + __IOM uint32_t ATDT0 : 32; /*!< [31..0] Arctangent Data Register 0 (single-precision floating-point) */ + } ATDT0_b; + }; + + union + { + __IOM float ATDT1; /*!< (@ 0x0000001C) Arctangent Data Register 1 */ + + struct + { + __IOM uint32_t ATDT1 : 32; /*!< [31..0] Arctangent Data Register 1 (single-precision floating-point) */ + } ATDT1_b; + }; +} R_TFU_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC120 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 12-Bit A/D converter (R_ADC120) + */ + +typedef struct /*!< (@ 0x90004000) R_ADC120 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel Select */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + uint16_t : 2; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D conversion Start */ + } ADCSR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t ADANSA0; /*!< (@ 0x00000004) A/D Channel Select Register A0 */ + + struct + { + __IOM uint16_t ANSA0 : 4; /*!< [3..0] A/D conversion Analog input Channel Select */ + uint16_t : 12; + } ADANSA0_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t ADADS0; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Function + * Channel Select Register 0 */ + + struct + { + __IOM uint16_t ADS0 : 4; /*!< [3..0] A/D-Converted Value Addition/Average Channel Select */ + uint16_t : 12; + } ADADS0_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition Count Select */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable */ + } ADADC_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 2; + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 9; + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group B */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger Select */ + uint16_t : 2; + } ADSTRGR_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ADANSB0; /*!< (@ 0x00000014) A/D Channel Select Register B0 */ + + struct + { + __IOM uint16_t ANSB0 : 4; /*!< [3..0] A/D Conversion Analog Input Channel Select */ + uint16_t : 12; + } ADANSB0_b; + }; + __IM uint16_t RESERVED5; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t DBLDR : 16; /*!< [15..0] The result of A/D conversion in response to the second + * trigger in double trigger mode. */ + } ADDBLDR_b; + }; + __IM uint16_t RESERVED6[3]; + + union + { + __IM uint16_t ADDR[4]; /*!< (@ 0x00000020) A/D Data Register n (n = 0 to 3) */ + + struct + { + __IM uint16_t DR : 16; /*!< [15..0] The result of A/D conversion (n: Number of channel) */ + } ADDR_b[4]; + }; + __IM uint16_t RESERVED7[31]; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Sample and hold period setting */ + __IOM uint16_t SHANS : 3; /*!< [10..8] Sample and hold use or bypass select for ch0-2 */ + uint16_t : 5; + } ADSHCR_b; + }; + __IM uint16_t RESERVED8[10]; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADELCCR; /*!< (@ 0x0000007D) A/D Event Link Control Register */ + + struct + { + __IOM uint8_t ELCC : 2; /*!< [1..0] Event link control bits */ + __IOM uint8_t GCELC : 1; /*!< [2..2] Event control bit for Group C */ + uint8_t : 5; + } ADELCCR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group Priority Control Setting */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting */ + uint16_t : 12; + __IOM uint16_t LGRRS : 1; /*!< [14..14] Restart Channel Select */ + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start */ + } ADGSPCR_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplication Register A */ + + struct + { + __IM uint16_t DBLDRA : 16; /*!< [15..0] The result of A/D conversion during extended operation + * in double trigger mode */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplication Register B */ + + struct + { + __IM uint16_t DBLDRB : 16; /*!< [15..0] The result of A/D conversion during extended operation + * in double trigger mode */ + } ADDBLDRB_b; + }; + __IM uint16_t RESERVED12[2]; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitoring + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitor */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparing result monitor for window A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparing result monitor for window B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B combination condition setting */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Window B operation permission */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Window A operation permission */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare window B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function enable */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare window A Interrupt Enable */ + } ADCMPCR_b; + }; + __IM uint16_t RESERVED15; + + union + { + __IOM uint16_t ADCMPANSR0; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register 0 */ + + struct + { + __IOM uint16_t CMPCHA0 : 16; /*!< [15..0] Window A Channel Select */ + } ADCMPANSR0_b; + }; + __IM uint16_t RESERVED16; + + union + { + __IOM uint16_t ADCMPLR0; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register 0 */ + + struct + { + __IOM uint16_t CMPLCHA0 : 4; /*!< [3..0] Window A comparison condition for target channel (ch0-3) + * setting */ + uint16_t : 12; + } ADCMPLR0_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Comparison Function Window A Lower Level + * Setting Register */ + + struct + { + __IOM uint16_t CMPLLA : 16; /*!< [15..0] Reference data setting when using the compare function + * window A */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) AD Comparison Function Window A Upper Level Setting + * Register */ + + struct + { + __IOM uint16_t CMPULA : 16; /*!< [15..0] Reference data setting when using the compare function + * window A */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR0; /*!< (@ 0x000000A0) A/D Comparison Function Window A Channel Status + * Register 0 */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 16; /*!< [15..0] Window A Status Flag */ + } ADCMPSR0_b; + }; + __IM uint16_t RESERVED18[2]; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Select + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Window B Channel Select */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Window B Comparison Condition Setting */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED19; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t CMPLLB : 16; /*!< [15..0] Reference lower data setting when using the compare + * function window B */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t CMPULB : 16; /*!< [15..0] Reference upper data setting when using the compare + * function window B */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Window B Flag */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21[19]; + + union + { + __IOM uint16_t ADANSC0; /*!< (@ 0x000000D4) A/D Channel Select Register C0 */ + + struct + { + __IOM uint16_t ANSC0 : 4; /*!< [3..0] A/D-Converted Channel Select for Group C in Group Scan + * Mode */ + uint16_t : 12; + } ADANSC0_b; + }; + __IM uint16_t RESERVED22; + __IM uint8_t RESERVED23; + + union + { + __IOM uint8_t ADGCTRGR; /*!< (@ 0x000000D9) A/D Group C Trigger Select Register */ + + struct + { + __IOM uint8_t TRSC : 6; /*!< [5..0] Group C A/D Conversion Start Trigger Select */ + __IOM uint8_t GCADIE : 1; /*!< [6..6] Group C Scan Completion Interrupt Enable */ + __IOM uint8_t GRCE : 1; /*!< [7..7] Group C A/D Conversion Enable */ + } ADGCTRGR_b; + }; + __IM uint16_t RESERVED24[3]; + + union + { + __IOM uint8_t ADSSTR[4]; /*!< (@ 0x000000E0) A/D Sampling State Register n (n = 0 to 3) */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting */ + } ADSSTR_b[4]; + }; +} R_ADC120_Type; /*!< Size = 228 (0xe4) */ + +/* =========================================================================================================================== */ +/* ================ R_POE3 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable 3 (R_POE3) + */ + +typedef struct /*!< (@ 0x90005000) R_POE3 Structure */ +{ + union + { + __IOM uint16_t ICSR1; /*!< (@ 0x00000000) Input Level Control/Status Register 1 */ + + struct + { + __IOM uint16_t POE0M : 2; /*!< [1..0] POE0 Mode Select */ + uint16_t : 6; + __IOM uint16_t PIE1 : 1; /*!< [8..8] Port Interrupt Enable 1 */ + uint16_t : 3; + __IOM uint16_t POE0F : 1; /*!< [12..12] POE0 Flag */ + uint16_t : 3; + } ICSR1_b; + }; + + union + { + __IOM uint16_t OCSR1; /*!< (@ 0x00000002) Output Level Control/Status Register 1 */ + + struct + { + uint16_t : 8; + __IOM uint16_t OIE1 : 1; /*!< [8..8] Output Short Circuit Interrupt Enable 1 */ + __IOM uint16_t OCE1 : 1; /*!< [9..9] Output Short Circuit High-Impedance Enable 1 */ + uint16_t : 5; + __IOM uint16_t OSF1 : 1; /*!< [15..15] Output Short Circuit Flag 1 */ + } OCSR1_b; + }; + + union + { + __IOM uint16_t ICSR2; /*!< (@ 0x00000004) Input Level Control/Status Register 2 */ + + struct + { + __IOM uint16_t POE4M : 2; /*!< [1..0] POE4 Mode Select */ + uint16_t : 6; + __IOM uint16_t PIE2 : 1; /*!< [8..8] Port Interrupt Enable 2 */ + uint16_t : 3; + __IOM uint16_t POE4F : 1; /*!< [12..12] POE4 Flag */ + uint16_t : 3; + } ICSR2_b; + }; + + union + { + __IOM uint16_t OCSR2; /*!< (@ 0x00000006) Output Level Control/Status Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t OIE2 : 1; /*!< [8..8] Output Short Circuit Interrupt Enable 2 */ + __IOM uint16_t OCE2 : 1; /*!< [9..9] Output Short Circuit High-Impedance Enable 2 */ + uint16_t : 5; + __IOM uint16_t OSF2 : 1; /*!< [15..15] Output Short Circuit Flag 2 */ + } OCSR2_b; + }; + + union + { + __IOM uint16_t ICSR3; /*!< (@ 0x00000008) Input Level Control/Status Register 3 */ + + struct + { + __IOM uint16_t POE8M : 2; /*!< [1..0] POE8 Mode Select */ + uint16_t : 6; + __IOM uint16_t PIE3 : 1; /*!< [8..8] Port Interrupt Enable 3 */ + __IOM uint16_t POE8E : 1; /*!< [9..9] POE8 High-Impedance Enable */ + uint16_t : 2; + __IOM uint16_t POE8F : 1; /*!< [12..12] POE8 Flag */ + uint16_t : 3; + } ICSR3_b; + }; + + union + { + __IOM uint8_t SPOER; /*!< (@ 0x0000000A) Software Port Output Enable Register */ + + struct + { + __IOM uint8_t MTUCH34HIZ : 1; /*!< [0..0] MTU3 and MTU4 Output High-Impedance Enable */ + __IOM uint8_t MTUCH67HIZ : 1; /*!< [1..1] MTU6 and MTU7 Output High-Impedance Enable */ + __IOM uint8_t MTUCH0HIZ : 1; /*!< [2..2] MTU0 Pin High-Impedance Enable */ + uint8_t : 5; + } SPOER_b; + }; + + union + { + __IOM uint8_t POECR1; /*!< (@ 0x0000000B) Port Output Enable Control Register 1 */ + + struct + { + __IOM uint8_t MTU0AZE : 1; /*!< [0..0] MTIOC0A High-Impedance Enable */ + __IOM uint8_t MTU0BZE : 1; /*!< [1..1] MTIOC0B High-Impedance Enable */ + __IOM uint8_t MTU0CZE : 1; /*!< [2..2] MTIOC0C High-Impedance Enable */ + __IOM uint8_t MTU0DZE : 1; /*!< [3..3] MTIOC0D High-Impedance Enable */ + uint8_t : 4; + } POECR1_b; + }; + + union + { + __IOM uint16_t POECR2; /*!< (@ 0x0000000C) Port Output Enable Control Register 2 */ + + struct + { + __IOM uint16_t MTU7BDZE : 1; /*!< [0..0] MTIOC7B/MTIOC7D High-Impedance Enable */ + __IOM uint16_t MTU7ACZE : 1; /*!< [1..1] MTIOC7A/MTIOC7C High-Impedance Enable */ + __IOM uint16_t MTU6BDZE : 1; /*!< [2..2] MTIOC6B/MTIOC6D High-Impedance Enable */ + uint16_t : 5; + __IOM uint16_t MTU4BDZE : 1; /*!< [8..8] MTIOC4B/MTIOC4D High-Impedance Enable */ + __IOM uint16_t MTU4ACZE : 1; /*!< [9..9] MTIOC4A/MTIOC4C High-Impedance Enable */ + __IOM uint16_t MTU3BDZE : 1; /*!< [10..10] MTIOC3B/MTIOC3D High-Impedance Enable */ + uint16_t : 5; + } POECR2_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t POECR4; /*!< (@ 0x00000010) Port Output Enable Control Register 4 */ + + struct + { + __IOM uint16_t D0E1ADDMT34ZE : 1; /*!< [0..0] MTU3 and MTU4 High-Impedance D0ERR1ST Add */ + __IOM uint16_t D1E1ADDMT34ZE : 1; /*!< [1..1] MTU3 and MTU4 High-Impedance D1ERR1ST Add */ + __IOM uint16_t IC2ADDMT34ZE : 1; /*!< [2..2] MTU3 and MTU4 High-Impedance POE4F Add */ + __IOM uint16_t IC3ADDMT34ZE : 1; /*!< [3..3] MTU3 and MTU4 High-Impedance POE8F Add */ + __IOM uint16_t IC4ADDMT34ZE : 1; /*!< [4..4] MTU3 and MTU4 High-Impedance POE10F Add */ + __IOM uint16_t IC5ADDMT34ZE : 1; /*!< [5..5] MTU3 and MTU4 High-Impedance POE11F Add */ + __IOM uint16_t D0E0ADDMT34ZE : 1; /*!< [6..6] MTU3 and MTU4 High-Impedance D0ERR0ST Add */ + __IOM uint16_t D1E0ADDMT34ZE : 1; /*!< [7..7] MTU3 and MTU4 High-Impedance D1ERR0ST Add */ + __IOM uint16_t D0E1ADDMT67ZE : 1; /*!< [8..8] MTU6 and MTU7 High-Impedance D0ERR1ST Add */ + __IOM uint16_t IC1ADDMT67ZE : 1; /*!< [9..9] MTU6 and MTU7 High-Impedance POE0F Add */ + __IOM uint16_t D1E1ADDMT67ZE : 1; /*!< [10..10] MTU6 and MTU7 High-Impedance D1ERR1ST Add */ + __IOM uint16_t IC3ADDMT67ZE : 1; /*!< [11..11] MTU6 and MTU7 High-Impedance POE8F Add */ + __IOM uint16_t IC4ADDMT67ZE : 1; /*!< [12..12] MTU6 and MTU7 High-Impedance POE10F Add */ + __IOM uint16_t IC5ADDMT67ZE : 1; /*!< [13..13] MTU6 and MTU7 High-Impedance POE11F Add */ + __IOM uint16_t D0E0ADDMT67ZE : 1; /*!< [14..14] MTU6 and MTU7 High-Impedance D0ERR0ST Add */ + __IOM uint16_t D1E0ADDMT67ZE : 1; /*!< [15..15] MTU6 and MTU7 High-Impedance D1ERR0ST Add */ + } POECR4_b; + }; + + union + { + __IOM uint16_t POECR5; /*!< (@ 0x00000012) Port Output Enable Control Register 5 */ + + struct + { + __IOM uint16_t D0E1ADDMT0ZE : 1; /*!< [0..0] MTU0 High-Impedance D0ERR1ST Add */ + __IOM uint16_t IC1ADDMT0ZE : 1; /*!< [1..1] MTU0 High-Impedance POE0F Add */ + __IOM uint16_t IC2ADDMT0ZE : 1; /*!< [2..2] MTU0 High-Impedance POE4F Add */ + __IOM uint16_t D1E1ADDMT0ZE : 1; /*!< [3..3] MTU0 High-Impedance D1ERR1ST Add */ + __IOM uint16_t IC4ADDMT0ZE : 1; /*!< [4..4] MTU0 High-Impedance POE10F Add */ + __IOM uint16_t IC5ADDMT0ZE : 1; /*!< [5..5] MTU0 High-Impedance POE11F Add */ + __IOM uint16_t D0E0ADDMT0ZE : 1; /*!< [6..6] MTU0 High-Impedance D0ERR0ST Add */ + __IOM uint16_t D1E0ADDMT0ZE : 1; /*!< [7..7] MTU0 High-Impedance D1ERR0ST Add */ + uint16_t : 8; + } POECR5_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t ICSR4; /*!< (@ 0x00000016) Input Level Control/Status Register 4 */ + + struct + { + __IOM uint16_t POE10M : 2; /*!< [1..0] POE10 Mode Select */ + uint16_t : 6; + __IOM uint16_t PIE4 : 1; /*!< [8..8] Port Interrupt Enable 4 */ + __IOM uint16_t POE10E : 1; /*!< [9..9] POE10 High-Impedance Enable */ + uint16_t : 2; + __IOM uint16_t POE10F : 1; /*!< [12..12] POE10 Flag */ + uint16_t : 3; + } ICSR4_b; + }; + + union + { + __IOM uint16_t ICSR5; /*!< (@ 0x00000018) Input Level Control/Status Register 5 */ + + struct + { + __IOM uint16_t POE11M : 2; /*!< [1..0] POE11 Mode Select */ + uint16_t : 6; + __IOM uint16_t PIE5 : 1; /*!< [8..8] Port Interrupt Enable 5 */ + __IOM uint16_t POE11E : 1; /*!< [9..9] POE11 High-Impedance Enable */ + uint16_t : 2; + __IOM uint16_t POE11F : 1; /*!< [12..12] POE11 Flag */ + uint16_t : 3; + } ICSR5_b; + }; + + union + { + __IOM uint16_t ALR1; /*!< (@ 0x0000001A) Active Level Setting Register 1 */ + + struct + { + __IOM uint16_t OLSG0A : 1; /*!< [0..0] MTIOC3B Pin Active Level Setting */ + __IOM uint16_t OLSG0B : 1; /*!< [1..1] MTIOC3D Pin Active Level Setting */ + __IOM uint16_t OLSG1A : 1; /*!< [2..2] MTIOC4A Pin Active Level Setting */ + __IOM uint16_t OLSG1B : 1; /*!< [3..3] MTIOC4C Pin Active Level Setting */ + __IOM uint16_t OLSG2A : 1; /*!< [4..4] MTIOC4B Pin Active Level Setting */ + __IOM uint16_t OLSG2B : 1; /*!< [5..5] MTIOC4D Pin Active Level Setting */ + uint16_t : 1; + __IOM uint16_t OLSEN : 1; /*!< [7..7] Active Level Setting Enable */ + uint16_t : 8; + } ALR1_b; + }; + + union + { + __IOM uint16_t ICSR6; /*!< (@ 0x0000001C) Input Level Control/Status Register 6 */ + + struct + { + uint16_t : 9; + __IOM uint16_t OSTSTE : 1; /*!< [9..9] Oscillation Stop High-Impedance Enable */ + uint16_t : 2; + __IOM uint16_t OSTSTF : 1; /*!< [12..12] Oscillation Stop High-Impedance Flag */ + uint16_t : 3; + } ICSR6_b; + }; + + union + { + __IOM uint16_t ICSR7; /*!< (@ 0x0000001E) Input Level Control/Status Register 7 */ + + struct + { + uint16_t : 4; + __IOM uint16_t D0ERR1IE : 1; /*!< [4..4] DSMIF0 Error 1 Interrupt enable */ + __IOM uint16_t D1ERR1IE : 1; /*!< [5..5] DSMIF1 Error 1 Interrupt enable */ + __IOM uint16_t D0ERR0IE : 1; /*!< [6..6] DSMIF0 Error 0 Interrupt Enable */ + __IOM uint16_t D1ERR0IE : 1; /*!< [7..7] DSMIF1 Error 0 Interrupt Enable */ + uint16_t : 3; + __IM uint16_t D0ERR1ST : 1; /*!< [11..11] DSMIF0 Error 1 Status */ + __IM uint16_t D1ERR1ST : 1; /*!< [12..12] DSMIF1 Error 1 Status */ + __IM uint16_t D0ERR0ST : 1; /*!< [13..13] DSMIF0 Error 0 Status */ + __IM uint16_t D1ERR0ST : 1; /*!< [14..14] DSMIF1 Error 0 Status */ + uint16_t : 1; + } ICSR7_b; + }; + __IM uint16_t RESERVED2[2]; + + union + { + __IOM uint8_t M0SELR1; /*!< (@ 0x00000024) MTU0 Pin Select Register 1 */ + + struct + { + __IOM uint8_t M0ASEL : 4; /*!< [3..0] MTU0-A (MTIOC0A) Pin Select */ + __IOM uint8_t M0BSEL : 4; /*!< [7..4] MTU0-B (MTIOC0B) Pin Select */ + } M0SELR1_b; + }; + + union + { + __IOM uint8_t M0SELR2; /*!< (@ 0x00000025) MTU0 Pin Select Register 2 */ + + struct + { + __IOM uint8_t M0CSEL : 4; /*!< [3..0] MTU0-C (MTIOC0C) Pin Select */ + __IOM uint8_t M0DSEL : 4; /*!< [7..4] MTU0-D (MTIOC0D) Pin Select */ + } M0SELR2_b; + }; + + union + { + __IOM uint8_t M3SELR; /*!< (@ 0x00000026) MTU3 Pin Select Register */ + + struct + { + __IOM uint8_t M3BSEL : 4; /*!< [3..0] MTU3-B (MTIOC3B) Pin Select */ + __IOM uint8_t M3DSEL : 4; /*!< [7..4] MTU3-D (MTIOC3D) Pin Select */ + } M3SELR_b; + }; + + union + { + __IOM uint8_t M4SELR1; /*!< (@ 0x00000027) MTU4 Pin Select Register 1 */ + + struct + { + __IOM uint8_t M4ASEL : 4; /*!< [3..0] MTU4-A (MTIOC4A) Pin Select */ + __IOM uint8_t M4CSEL : 4; /*!< [7..4] MTU4-C (MTIOC4C) Pin Select */ + } M4SELR1_b; + }; + + union + { + __IOM uint8_t M4SELR2; /*!< (@ 0x00000028) MTU4 Pin Select Register 2 */ + + struct + { + __IOM uint8_t M4BSEL : 4; /*!< [3..0] MTU4-B (MTIOC4B) Pin Select */ + __IOM uint8_t M4DSEL : 4; /*!< [7..4] MTU4-D (MTIOC4D) Pin Select */ + } M4SELR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t M6SELR; /*!< (@ 0x0000002A) MTU6 Pin Select Register */ + + struct + { + __IOM uint8_t M6BSEL : 4; /*!< [3..0] MTU6-B (MTIOC6B) Pin Select */ + __IOM uint8_t M6DSEL : 4; /*!< [7..4] MTU6-D (MTIOC6D) Pin Select */ + } M6SELR_b; + }; + + union + { + __IOM uint8_t M7SELR1; /*!< (@ 0x0000002B) MTU7 Pin Select Register 1 */ + + struct + { + __IOM uint8_t M7ASEL : 4; /*!< [3..0] MTU7-A (MTIOC7A) Pin Select */ + __IOM uint8_t M7CSEL : 4; /*!< [7..4] MTU7-C (MTIOC7C) Pin Select */ + } M7SELR1_b; + }; + + union + { + __IOM uint8_t M7SELR2; /*!< (@ 0x0000002C) MTU7 Pin Select Register 2 */ + + struct + { + __IOM uint8_t M7BSEL : 4; /*!< [3..0] MTU7-B (MTIOC7B) Pin Select */ + __IOM uint8_t M7DSEL : 4; /*!< [7..4] MTU7-D (MTIOC7D) Pin Select */ + } M7SELR2_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; +} R_POE3_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GPT Port Output Enable 0 (R_POEG0) + */ + +typedef struct /*!< (@ 0x90006000) R_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEG0GA; /*!< (@ 0x00000000) POEG0 Group A Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 3; + __IM uint32_t D0ERR1ST : 1; /*!< [20..20] DSMIF0 error 1 status */ + __IM uint32_t D1ERR1ST : 1; /*!< [21..21] DSMIF1 error 1 status */ + __IOM uint32_t D0ERR1E : 1; /*!< [22..22] Permit output disabled by DSMIF0 error 1 detection */ + __IOM uint32_t D1ERR1E : 1; /*!< [23..23] Permit output disabled by DSMIF1 error 1 detection */ + __IM uint32_t D0ERR0ST : 1; /*!< [24..24] DSMIF0 error 0 status */ + __IM uint32_t D1ERR0ST : 1; /*!< [25..25] DSMIF1 error 0 status */ + __IOM uint32_t D0ERR0E : 1; /*!< [26..26] Permit output disabled by DSMIF0 error 0 detection */ + __IOM uint32_t D1ERR0E : 1; /*!< [27..27] Permit output disabled by DSMIF1 error 0 detection */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG0GA_b; + }; + __IM uint32_t RESERVED[255]; + + union + { + __IOM uint32_t POEG0GB; /*!< (@ 0x00000400) POEG0 Group B Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 3; + __IM uint32_t D0ERR1ST : 1; /*!< [20..20] DSMIF0 error 1 status */ + __IM uint32_t D1ERR1ST : 1; /*!< [21..21] DSMIF1 error 1 status */ + __IOM uint32_t D0ERR1E : 1; /*!< [22..22] Permit output disabled by DSMIF0 error 1 detection */ + __IOM uint32_t D1ERR1E : 1; /*!< [23..23] Permit output disabled by DSMIF1 error 1 detection */ + __IM uint32_t D0ERR0ST : 1; /*!< [24..24] DSMIF0 error 0 status */ + __IM uint32_t D1ERR0ST : 1; /*!< [25..25] DSMIF1 error 0 status */ + __IOM uint32_t D0ERR0E : 1; /*!< [26..26] Permit output disabled by DSMIF0 error 0 detection */ + __IOM uint32_t D1ERR0E : 1; /*!< [27..27] Permit output disabled by DSMIF1 error 0 detection */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG0GB_b; + }; + __IM uint32_t RESERVED1[255]; + + union + { + __IOM uint32_t POEG0GC; /*!< (@ 0x00000800) POEG0 Group C Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 3; + __IM uint32_t D0ERR1ST : 1; /*!< [20..20] DSMIF0 error 1 status */ + __IM uint32_t D1ERR1ST : 1; /*!< [21..21] DSMIF1 error 1 status */ + __IOM uint32_t D0ERR1E : 1; /*!< [22..22] Permit output disabled by DSMIF0 error 1 detection */ + __IOM uint32_t D1ERR1E : 1; /*!< [23..23] Permit output disabled by DSMIF1 error 1 detection */ + __IM uint32_t D0ERR0ST : 1; /*!< [24..24] DSMIF0 error 0 status */ + __IM uint32_t D1ERR0ST : 1; /*!< [25..25] DSMIF1 error 0 status */ + __IOM uint32_t D0ERR0E : 1; /*!< [26..26] Permit output disabled by DSMIF0 error 0 detection */ + __IOM uint32_t D1ERR0E : 1; /*!< [27..27] Permit output disabled by DSMIF1 error 0 detection */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG0GC_b; + }; + __IM uint32_t RESERVED2[255]; + + union + { + __IOM uint32_t POEG0GD; /*!< (@ 0x00000C00) POEG0 Group D Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 3; + __IM uint32_t D0ERR1ST : 1; /*!< [20..20] DSMIF0 error 1 status */ + __IM uint32_t D1ERR1ST : 1; /*!< [21..21] DSMIF1 error 1 status */ + __IOM uint32_t D0ERR1E : 1; /*!< [22..22] Permit output disabled by DSMIF0 error 1 detection */ + __IOM uint32_t D1ERR1E : 1; /*!< [23..23] Permit output disabled by DSMIF1 error 1 detection */ + __IM uint32_t D0ERR0ST : 1; /*!< [24..24] DSMIF0 error 0 status */ + __IM uint32_t D1ERR0ST : 1; /*!< [25..25] DSMIF1 error 0 status */ + __IOM uint32_t D0ERR0E : 1; /*!< [26..26] Permit output disabled by DSMIF0 error 0 detection */ + __IOM uint32_t D1ERR0E : 1; /*!< [27..27] Permit output disabled by DSMIF1 error 0 detection */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG0GD_b; + }; +} R_POEG0_Type; /*!< Size = 3076 (0xc04) */ + +/* =========================================================================================================================== */ +/* ================ R_DSMIF0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Delta-sigma Interface 0 (R_DSMIF0) + */ + +typedef struct /*!< (@ 0x90008000) R_DSMIF0 Structure */ +{ + __IM uint32_t RESERVED[32]; + + union + { + __IOM uint32_t DSSEICR; /*!< (@ 0x00000080) Overcurrent Sum Error Detect Interrupt Control + * Register */ + + struct + { + __IOM uint32_t ISEL : 1; /*!< [0..0] Overcurrent sum error lower limit detection interrupt + * enable bit */ + __IOM uint32_t ISEH : 1; /*!< [1..1] Overcurrent sum error upper limit detection interrupt + * enable bit */ + uint32_t : 30; + } DSSEICR_b; + }; + + union + { + __IOM uint32_t DSSECSR; /*!< (@ 0x00000084) Overcurrent Sum Error Detect Channel Setting + * Register */ + + struct + { + __IOM uint32_t SEDM : 3; /*!< [2..0] Overcurrent sum error detect mode setting bit */ + uint32_t : 29; + } DSSECSR_b; + }; + + union + { + __IOM uint32_t DSSELTR; /*!< (@ 0x00000088) Overcurrent Sum Error Detect Low Threshold Register */ + + struct + { + __IOM uint32_t SCMPTBL : 18; /*!< [17..0] Overcurrent sum error detect lower limit */ + uint32_t : 14; + } DSSELTR_b; + }; + + union + { + __IOM uint32_t DSSEHTR; /*!< (@ 0x0000008C) Overcurrent Sum Error Detect High Threshold Register */ + + struct + { + __IOM uint32_t SCMPTBH : 18; /*!< [17..0] Overcurrent sum error detect upper limit */ + uint32_t : 14; + } DSSEHTR_b; + }; + + union + { + __IOM uint32_t DSSECR; /*!< (@ 0x00000090) Overcurrent Sum Error Detect Control Register */ + + struct + { + __IOM uint32_t SEEL : 1; /*!< [0..0] Overcurrent sum error lower limit detection enable bit */ + __IOM uint32_t SEEH : 1; /*!< [1..1] Overcurrent sum error upper limit detection enable bit */ + uint32_t : 30; + } DSSECR_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t DSSECDR[3]; /*!< (@ 0x000000A0) Overcurrent Sum Error Detect Capture Data Register + * [0..2] */ + + struct + { + __IOM uint32_t SECDR : 16; /*!< [15..0] Overcurrent sum error detect capture data n */ + uint32_t : 16; + } DSSECDR_b[3]; + }; + __IM uint32_t RESERVED2[5]; + + union + { + __IOM uint32_t DSCMSR; /*!< (@ 0x000000C0) Common Mode Setting Register */ + + struct + { + __IOM uint32_t DFS : 1; /*!< [0..0] Data Format Select */ + __IOM uint32_t CISM : 2; /*!< [2..1] Common Interrupt Synchronous channel Mode */ + uint32_t : 29; + } DSCMSR_b; + }; + + union + { + __IOM uint32_t DSCICR; /*!< (@ 0x000000C4) Common Interrupt Control Register */ + + struct + { + __IOM uint32_t IUCE : 1; /*!< [0..0] Current data register update channel common interrupt + * enable */ + __IOM uint32_t IAUCE : 1; /*!< [1..1] Capture current data register A update channel common + * interrupt enable */ + __IOM uint32_t IBUCE : 1; /*!< [2..2] Capture current data register B update channel common + * interrupt enable */ + uint32_t : 29; + } DSCICR_b; + }; + __IM uint32_t RESERVED3[78]; + + union + { + __IOM uint32_t DSCSTRTR; /*!< (@ 0x00000200) Channel Software Start Trigger Register */ + + struct + { + __IOM uint32_t STRTRG0 : 1; /*!< [0..0] Channel 0 start trigger */ + __IOM uint32_t STRTRG1 : 1; /*!< [1..1] Channel 1 start trigger */ + __IOM uint32_t STRTRG2 : 1; /*!< [2..2] Channel 2 start trigger */ + uint32_t : 29; + } DSCSTRTR_b; + }; + + union + { + __IOM uint32_t DSCSTPTR; /*!< (@ 0x00000204) Channel Software Stop Trigger Register */ + + struct + { + __IOM uint32_t STPTRG0 : 1; /*!< [0..0] Channel 0 stop trigger */ + __IOM uint32_t STPTRG1 : 1; /*!< [1..1] Channel 1 stop trigger */ + __IOM uint32_t STPTRG2 : 1; /*!< [2..2] Channel 2 stop trigger */ + uint32_t : 29; + } DSCSTPTR_b; + }; + __IM uint32_t RESERVED4[6]; + + union + { + __IM uint32_t DSCESR; /*!< (@ 0x00000220) Channel Error Status Register */ + + struct + { + __IM uint32_t SCF0 : 1; /*!< [0..0] Channel 0 short circuit detection flag */ + __IM uint32_t SCF1 : 1; /*!< [1..1] Channel 1 short circuit detection flag */ + __IM uint32_t SCF2 : 1; /*!< [2..2] Channel 2 short circuit detection flag */ + uint32_t : 13; + __IM uint32_t SUMERRL : 1; /*!< [16..16] Overcurrent sum error lower limit detection flag */ + __IM uint32_t SUMERRH : 1; /*!< [17..17] Overcurrent sum error upper limit detection flag */ + uint32_t : 14; + } DSCESR_b; + }; + + union + { + __IM uint32_t DSCOCESR; /*!< (@ 0x00000224) Channel Overcurrent Error Status Register */ + + struct + { + __IM uint32_t OC0FL0 : 1; /*!< [0..0] Channel 0 overcurrent lower limit detection 0 flag */ + __IM uint32_t OC0FL1 : 1; /*!< [1..1] Channel 1 overcurrent lower limit detection 0 flag */ + __IM uint32_t OC0FL2 : 1; /*!< [2..2] Channel 2 overcurrent lower limit detection 0 flag */ + uint32_t : 1; + __IM uint32_t OC0FH0 : 1; /*!< [4..4] Channel 0 overcurrent upper limit exceeded 0 flag */ + __IM uint32_t OC0FH1 : 1; /*!< [5..5] Channel 1 overcurrent upper limit exceeded 0 flag */ + __IM uint32_t OC0FH2 : 1; /*!< [6..6] Channel 2 overcurrent upper limit exceeded 0 flag */ + uint32_t : 1; + __IM uint32_t OC1FL0 : 1; /*!< [8..8] Channel 0 overcurrent lower limit detection 1 flag */ + __IM uint32_t OC1FL1 : 1; /*!< [9..9] Channel 1 overcurrent lower limit detection 1 flag */ + __IM uint32_t OC1FL2 : 1; /*!< [10..10] Channel 2 overcurrent lower limit detection 1 flag */ + uint32_t : 1; + __IM uint32_t OC1FH0 : 1; /*!< [12..12] Channel 0 overcurrent upper limit exceeded 1 flag */ + __IM uint32_t OC1FH1 : 1; /*!< [13..13] Channel 1 overcurrent upper limit exceeded 1 flag */ + __IM uint32_t OC1FH2 : 1; /*!< [14..14] Channel 2 overcurrent upper limit exceeded 1 flag */ + uint32_t : 1; + __IM uint32_t OC2FL0 : 1; /*!< [16..16] Channel 0 overcurrent lower limit detection 2 flag */ + __IM uint32_t OC2FL1 : 1; /*!< [17..17] Channel 1 overcurrent lower limit detection 2 flag */ + __IM uint32_t OC2FL2 : 1; /*!< [18..18] Channel 2 overcurrent lower limit detection 2 flag */ + uint32_t : 1; + __IM uint32_t OC2FH0 : 1; /*!< [20..20] Channel 0 overcurrent upper limit exceeded 2 flag */ + __IM uint32_t OC2FH1 : 1; /*!< [21..21] Channel 1 overcurrent upper limit exceeded 2 flag */ + __IM uint32_t OC2FH2 : 1; /*!< [22..22] Channel 2 overcurrent upper limit exceeded 2 flag */ + uint32_t : 9; + } DSCOCESR_b; + }; + + union + { + __IM uint32_t DSCOCNSR; /*!< (@ 0x00000228) Channel Overcurrent Notification Status Register */ + + struct + { + __IM uint32_t OWD0N0 : 1; /*!< [0..0] Channel 0 overcurrent detection window notification 0 + * flag */ + __IM uint32_t OWD0N1 : 1; /*!< [1..1] Channel 1 overcurrent detection window notification 0 + * flag */ + __IM uint32_t OWD0N2 : 1; /*!< [2..2] Channel 2 overcurrent detection window notification 0 + * flag */ + uint32_t : 1; + __IM uint32_t OWD1N0 : 1; /*!< [4..4] Channel 0 overcurrent detection window notification 1 + * flag */ + __IM uint32_t OWD1N1 : 1; /*!< [5..5] Channel 1 overcurrent detection window notification 1 + * flag */ + __IM uint32_t OWD1N2 : 1; /*!< [6..6] Channel 2 overcurrent detection window notification 1 + * flag */ + uint32_t : 1; + __IM uint32_t OWD2N0 : 1; /*!< [8..8] Channel 0 overcurrent detection window notification 2 + * flag */ + __IM uint32_t OWD2N1 : 1; /*!< [9..9] Channel 1 overcurrent detection window notification 2 + * flag */ + __IM uint32_t OWD2N2 : 1; /*!< [10..10] Channel 2 overcurrent detection window notification + * 2 flag */ + uint32_t : 1; + __IM uint32_t OWD3N0 : 1; /*!< [12..12] Channel 0 overcurrent detection window notification + * 3 flag */ + __IM uint32_t OWD3N1 : 1; /*!< [13..13] Channel 1 overcurrent detection window notification + * 3 flag */ + __IM uint32_t OWD3N2 : 1; /*!< [14..14] Channel 2 overcurrent detection window notification + * 3 flag */ + uint32_t : 17; + } DSCOCNSR_b; + }; + + union + { + __IM uint32_t DSCOCRMR; /*!< (@ 0x0000022C) Channel Overcurrent Comparator Result Monitor + * Register */ + + struct + { + __IM uint32_t OC0CMPL0 : 1; /*!< [0..0] Channel 0 overcurrent detect 0 lower limit compare result */ + __IM uint32_t OC0CMPL1 : 1; /*!< [1..1] Channel 1 overcurrent detect 0 lower limit compare result */ + __IM uint32_t OC0CMPL2 : 1; /*!< [2..2] Channel 2 overcurrent detect 0 lower limit compare result */ + uint32_t : 1; + __IM uint32_t OC0CMPH0 : 1; /*!< [4..4] Channel 0 overcurrent detect 0 upper limit compare result */ + __IM uint32_t OC0CMPH1 : 1; /*!< [5..5] Channel 1 overcurrent detect 0 upper limit compare result */ + __IM uint32_t OC0CMPH2 : 1; /*!< [6..6] Channel 2 overcurrent detect 0 upper limit compare result */ + uint32_t : 1; + __IM uint32_t OC1CMPL0 : 1; /*!< [8..8] Channel 0 overcurrent detect 1 lower limit compare result */ + __IM uint32_t OC1CMPL1 : 1; /*!< [9..9] Channel 1 overcurrent detect 1 lower limit compare result */ + __IM uint32_t OC1CMPL2 : 1; /*!< [10..10] Channel 2 overcurrent detect 1 lower limit compare + * result */ + uint32_t : 1; + __IM uint32_t OC1CMPH0 : 1; /*!< [12..12] Channel 0 overcurrent detect 1 upper limit compare + * result */ + __IM uint32_t OC1CMPH1 : 1; /*!< [13..13] Channel 1 overcurrent detect 1 upper limit compare + * result */ + __IM uint32_t OC1CMPH2 : 1; /*!< [14..14] Channel 2 overcurrent detect 1 upper limit compare + * result */ + uint32_t : 1; + __IM uint32_t OC2CMPL0 : 1; /*!< [16..16] Channel 0 overcurrent detect 2 lower limit compare + * result */ + __IM uint32_t OC2CMPL1 : 1; /*!< [17..17] Channel 1 overcurrent detect 2 lower limit compare + * result */ + __IM uint32_t OC2CMPL2 : 1; /*!< [18..18] Channel 2 overcurrent detect 2 lower limit compare + * result */ + uint32_t : 1; + __IM uint32_t OC2CMPH0 : 1; /*!< [20..20] Channel 0 overcurrent detect 2 upper limit compare + * result */ + __IM uint32_t OC2CMPH1 : 1; /*!< [21..21] Channel 1 overcurrent detect 2 upper limit compare + * result */ + __IM uint32_t OC2CMPH2 : 1; /*!< [22..22] Channel 2 overcurrent detect 2 upper limit compare + * result */ + uint32_t : 9; + } DSCOCRMR_b; + }; + __IM uint32_t RESERVED5[4]; + + union + { + __IM uint32_t DSCSR; /*!< (@ 0x00000240) Channel Status Register */ + + struct + { + __IM uint32_t DUF0 : 1; /*!< [0..0] Channel 0 Data Update flag */ + __IM uint32_t DUF1 : 1; /*!< [1..1] Channel 1 Data Update flag */ + __IM uint32_t DUF2 : 1; /*!< [2..2] Channel 2 Data Update flag */ + uint32_t : 1; + __IM uint32_t CAUF0 : 1; /*!< [4..4] Channel 0 capture data A update flag */ + __IM uint32_t CAUF1 : 1; /*!< [5..5] Channel 1 capture data A update flag */ + __IM uint32_t CAUF2 : 1; /*!< [6..6] Channel 2 capture data A update flag */ + uint32_t : 1; + __IM uint32_t CBUF0 : 1; /*!< [8..8] Channel 0 capture data B update flag */ + __IM uint32_t CBUF1 : 1; /*!< [9..9] Channel 1 capture data B update flag */ + __IM uint32_t CBUF2 : 1; /*!< [10..10] Channel 2 capture data B update flag */ + uint32_t : 21; + } DSCSR_b; + }; + + union + { + __IM uint32_t DSCSSR; /*!< (@ 0x00000244) Channel State Status Register */ + + struct + { + __IM uint32_t CHSTATE0 : 1; /*!< [0..0] Channel 0 state */ + uint32_t : 3; + __IM uint32_t CHSTATE1 : 1; /*!< [4..4] Channel 1 state */ + uint32_t : 3; + __IM uint32_t CHSTATE2 : 1; /*!< [8..8] Channel 2 state */ + uint32_t : 23; + } DSCSSR_b; + }; + __IM uint32_t RESERVED6[6]; + + union + { + __OM uint32_t DSCESCR; /*!< (@ 0x00000260) Channel Error Status Clear Register */ + + struct + { + __OM uint32_t CLRSCF0 : 1; /*!< [0..0] Channel 0 Overcurrent Lower Limit Detection Flag Clear */ + __OM uint32_t CLRSCF1 : 1; /*!< [1..1] Channel 1 Overcurrent Lower Limit Detection Flag Clear */ + __OM uint32_t CLRSCF2 : 1; /*!< [2..2] Channel 2 Overcurrent Lower Limit Detection Flag Clear */ + uint32_t : 13; + __OM uint32_t CLRSUMERRL : 1; /*!< [16..16] Overcurrent Sum Error Lower Limit Detection Flag Clear */ + __OM uint32_t CLRSUMERRH : 1; /*!< [17..17] Overcurrent Sum Error Upper Limit Detection Flag Clear */ + uint32_t : 14; + } DSCESCR_b; + }; + + union + { + __OM uint32_t DSCOCESCR; /*!< (@ 0x00000264) Channel Overcurrent Error Status Clear Register */ + + struct + { + __OM uint32_t CLROC0FL0 : 1; /*!< [0..0] Channel 0 overcurrent lower limit detection 0 flag clear */ + __OM uint32_t CLROC0FL1 : 1; /*!< [1..1] Channel 1 overcurrent lower limit detection 0 flag clear */ + __OM uint32_t CLROC0FL2 : 1; /*!< [2..2] Channel 2 overcurrent lower limit detection 0 flag clear */ + uint32_t : 1; + __OM uint32_t CLROC0FH0 : 1; /*!< [4..4] Channel 0 overcurrent upper limit exceeded 0 flag clear */ + __OM uint32_t CLROC0FH1 : 1; /*!< [5..5] Channel 1 overcurrent upper limit exceeded 0 flag clear */ + __OM uint32_t CLROC0FH2 : 1; /*!< [6..6] Channel 2 overcurrent upper limit exceeded 0 flag clear */ + uint32_t : 1; + __OM uint32_t CLROC1FL0 : 1; /*!< [8..8] Channel 0 overcurrent lower limit detection 1 flag clear */ + __OM uint32_t CLROC1FL1 : 1; /*!< [9..9] Channel 1 overcurrent lower limit detection 1 flag clear */ + __OM uint32_t CLROC1FL2 : 1; /*!< [10..10] Channel 2 overcurrent lower limit detection 1 flag + * clear */ + uint32_t : 1; + __OM uint32_t CLROC1FH0 : 1; /*!< [12..12] Channel 0 overcurrent upper limit exceeded 1 flag clear */ + __OM uint32_t CLROC1FH1 : 1; /*!< [13..13] Channel 1 overcurrent upper limit exceeded 1 flag clear */ + __OM uint32_t CLROC1FH2 : 1; /*!< [14..14] Channel 2 overcurrent upper limit exceeded 1 flag clear */ + uint32_t : 1; + __OM uint32_t CLROC2FL0 : 1; /*!< [16..16] Channel 0 overcurrent lower limit detection 2 flag + * clear */ + __OM uint32_t CLROC2FL1 : 1; /*!< [17..17] Channel 1 overcurrent lower limit detection 2 flag + * clear */ + __OM uint32_t CLROC2FL2 : 1; /*!< [18..18] Channel 2 overcurrent lower limit detection 2 flag + * clear */ + uint32_t : 1; + __OM uint32_t CLROC2FH0 : 1; /*!< [20..20] Channel 0 overcurrent upper limit exceeded 2 flag clear */ + __OM uint32_t CLROC2FH1 : 1; /*!< [21..21] Channel 1 overcurrent upper limit exceeded 2 flag */ + __OM uint32_t CLROC2FH2 : 1; /*!< [22..22] Channel 2 overcurrent upper limit exceeded 2 flag clear */ + uint32_t : 9; + } DSCOCESCR_b; + }; + + union + { + __OM uint32_t DSCOCNSCR; /*!< (@ 0x00000268) Channel Overcurrent Notification Status Clear + * Register */ + + struct + { + __OM uint32_t CLROWD0N0 : 1; /*!< [0..0] Channel 0 overcurrent detection window notification 0 + * flag clear */ + __OM uint32_t CLROWD0N1 : 1; /*!< [1..1] Channel 1 overcurrent detection window notification 0 + * flag clear */ + __OM uint32_t CLROWD0N2 : 1; /*!< [2..2] Channel 2 overcurrent detection window notification 0 + * flag clear */ + uint32_t : 1; + __OM uint32_t CLROWD1N0 : 1; /*!< [4..4] Channel 0 overcurrent detection window notification 1 + * flag clear */ + __OM uint32_t CLROWD1N1 : 1; /*!< [5..5] Channel 1 overcurrent detection window notification 1 + * flag clear */ + __OM uint32_t CLROWD1N2 : 1; /*!< [6..6] Channel 2 overcurrent detection window notification 1 + * flag clear */ + uint32_t : 1; + __OM uint32_t CLROWD2N0 : 1; /*!< [8..8] Channel 0 overcurrent detection window notification 2 + * flag clear */ + __OM uint32_t CLROWD2N1 : 1; /*!< [9..9] Channel 1 overcurrent detection window notification 2 + * flag clear */ + __OM uint32_t CLROWD2N2 : 1; /*!< [10..10] Channel 2 overcurrent detection window notification + * 2 flag clear */ + uint32_t : 1; + __OM uint32_t CLROWD3N0 : 1; /*!< [12..12] Channel 0 overcurrent detection window notification + * 3 flag clear */ + __OM uint32_t CLROWD3N1 : 1; /*!< [13..13] Channel 1 overcurrent detection window notification + * 3 flag clear */ + __OM uint32_t CLROWD3N2 : 1; /*!< [14..14] Channel 2 overcurrent detection window notification + * 3 flag clear */ + uint32_t : 17; + } DSCOCNSCR_b; + }; + __IM uint32_t RESERVED7[5]; + + union + { + __OM uint32_t DSCSCR; /*!< (@ 0x00000280) Channel Status Clear Register */ + + struct + { + __OM uint32_t CLRDUF0 : 1; /*!< [0..0] Channel 0 Data Update Flag Clear */ + __OM uint32_t CLRDUF1 : 1; /*!< [1..1] Channel 1 Data Update Flag Clear */ + __OM uint32_t CLRDUF2 : 1; /*!< [2..2] Channel 2 Data Update Flag Clear */ + uint32_t : 1; + __OM uint32_t CLRCAUF0 : 1; /*!< [4..4] Channel 0 Capture Data A Update Flag Clear */ + __OM uint32_t CLRCAUF1 : 1; /*!< [5..5] Channel 1 Capture Data A Update Flag Clear */ + __OM uint32_t CLRCAUF2 : 1; /*!< [6..6] Channel 2 Capture Data A Update Flag Clear */ + uint32_t : 1; + __OM uint32_t CLRCBUF0 : 1; /*!< [8..8] Channel 0 Capture Data B Update Flag Clear */ + __OM uint32_t CLRCBUF1 : 1; /*!< [9..9] Channel 1 Capture Data B Update Flag Clear */ + __OM uint32_t CLRCBUF2 : 1; /*!< [10..10] Channel 2 Capture Data B Update Flag Clear */ + uint32_t : 21; + } DSCSCR_b; + }; + __IM uint32_t RESERVED8[31]; + __IOM R_DSMIF0_CH_Type CH[3]; /*!< (@ 0x00000300) Channel Registers [0..2] */ +} R_DSMIF0_Type; /*!< Size = 1728 (0x6c0) */ + +/* =========================================================================================================================== */ +/* ================ R_HDSLD0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief HIPERFACE DSL for Drive Interface Unit 0 (R_HDSLD0) + */ + +typedef struct /*!< (@ 0x90040000) R_HDSLD0 Structure */ +{ + union + { + __IOM uint8_t SYS_CTRL; /*!< (@ 0x00000000) System Control Register */ + + struct + { + __IOM uint8_t OEN : 1; /*!< [0..0] Activation of the output */ + __IOM uint8_t SPOL : 1; /*!< [1..1] Polarity of the synchronization pulse */ + uint8_t : 2; + __IOM uint8_t LOOP : 1; /*!< [4..4] Test drive interface */ + __IOM uint8_t FRST : 1; /*!< [5..5] Pipeline FIFO, reset */ + __IOM uint8_t MRST : 1; /*!< [6..6] Messages reset */ + __IOM uint8_t PRST : 1; /*!< [7..7] Protocol reset */ + } SYS_CTRL_b; + }; + + union + { + __OM uint8_t SYNC_CTRL; /*!< (@ 0x00000001) Synchronization Control Register */ + + struct + { + __OM uint8_t ES : 8; /*!< [7..0] External synchronization */ + } SYNC_CTRL_b; + }; + __IM uint8_t RESERVED; + + union + { + __IM uint8_t MASTER_QM; /*!< (@ 0x00000003) Quality Monitoring Register */ + + struct + { + __IM uint8_t QM : 4; /*!< [3..0] Quality monitoring bits */ + uint8_t : 3; + __IM uint8_t LINK : 1; /*!< [7..7] DSL protocol connection status */ + } MASTER_QM_b; + }; + + union + { + __IOM uint8_t EVENT_H; /*!< (@ 0x00000004) High Byte Event Register */ + + struct + { + __IOM uint8_t PRST : 1; /*!< [0..0] Protocol reset warning */ + __IOM uint8_t DTE : 1; /*!< [1..1] Estimator deviation threshold error */ + uint8_t : 1; + __IOM uint8_t POS : 1; /*!< [3..3] Estimator turned on */ + uint8_t : 2; + __IOM uint8_t SUM : 1; /*!< [6..6] Remote event monitoring */ + __IM uint8_t INT : 1; /*!< [7..7] Interrupt status */ + } EVENT_H_b; + }; + + union + { + __IOM uint8_t EVENT_L; /*!< (@ 0x00000005) Low Byte Event Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t FREL : 1; /*!< [1..1] Channel free for "long message" */ + __IOM uint8_t QMLW : 1; /*!< [2..2] Quality monitoring low-value warning */ + uint8_t : 1; + __IOM uint8_t ANS : 1; /*!< [4..4] Erroneous answer to "long message" */ + __IOM uint8_t MIN : 1; /*!< [5..5] Message initialization */ + uint8_t : 2; + } EVENT_L_b; + }; + + union + { + __OM uint8_t MASK_H; /*!< (@ 0x00000006) High Byte Event Mask Register */ + + struct + { + __OM uint8_t MPRST : 1; /*!< [0..0] Mask for protocol reset warning */ + __OM uint8_t MDTE : 1; /*!< [1..1] Mask for estimator deviation threshold error warning */ + uint8_t : 1; + __OM uint8_t MPOS : 1; /*!< [3..3] Mask for fast position error */ + uint8_t : 2; + __OM uint8_t MSUM : 1; /*!< [6..6] Mask for remote event monitoring */ + uint8_t : 1; + } MASK_H_b; + }; + + union + { + __OM uint8_t MASK_L; /*!< (@ 0x00000007) Low Byte Event Mask Register */ + + struct + { + uint8_t : 1; + __OM uint8_t MFREL : 1; /*!< [1..1] Mask for "channel free for "long message"" */ + __OM uint8_t MQMLW : 1; /*!< [2..2] Mask for low-quality monitoring value warning */ + uint8_t : 1; + __OM uint8_t MANS : 1; /*!< [4..4] Mask for erroneous answer to "long message" */ + __OM uint8_t MMIN : 1; /*!< [5..5] Mask for message initialization confirmation */ + uint8_t : 2; + } MASK_L_b; + }; + + union + { + __OM uint8_t MASK_SUM; /*!< (@ 0x00000008) Summary Mask Register */ + + struct + { + __OM uint8_t MSUM : 8; /*!< [7..0] Mask for status summary bits */ + } MASK_SUM_b; + }; + + union + { + __IM uint8_t EDGES; /*!< (@ 0x00000009) Edge Register */ + + struct + { + __IM uint8_t EDGES : 8; /*!< [7..0] Identification of edges in the cable signal */ + } EDGES_b; + }; + + union + { + __IM uint8_t DELAY; /*!< (@ 0x0000000A) Run Time Delay Register */ + + struct + { + __IM uint8_t CBLDLY : 4; /*!< [3..0] 4-bit value for cable delay */ + __IM uint8_t RSSI : 4; /*!< [7..4] Indication of the received signal strength */ + } DELAY_b; + }; + + union + { + __IM uint8_t VERSION; /*!< (@ 0x0000000B) Version Register */ + + struct + { + __IM uint8_t MINOR : 4; /*!< [3..0] Minor release number */ + __IM uint8_t MAJOR : 2; /*!< [5..4] Major release number */ + __IM uint8_t CODE : 2; /*!< [7..6] Type of module */ + } VERSION_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IM uint8_t ENC_ID2; /*!< (@ 0x0000000D) Encoder ID 2 Register */ + + struct + { + __IM uint8_t ENCID : 4; /*!< [3..0] Encoder designation code bit 19 to bit 16 */ + __IM uint8_t SCI : 3; /*!< [6..4] Indication of special characters */ + uint8_t : 1; + } ENC_ID2_b; + }; + + union + { + __IM uint8_t ENC_ID1; /*!< (@ 0x0000000E) Encoder ID 1 Register */ + + struct + { + __IM uint8_t ENCID : 8; /*!< [7..0] Encoder designation code, byte n */ + } ENC_ID1_b; + }; + + union + { + __IM uint8_t ENC_ID0; /*!< (@ 0x0000000F) Encoder ID 0 Register */ + + struct + { + __IM uint8_t ENCID : 8; /*!< [7..0] Encoder designation code, byte n */ + } ENC_ID0_b; + }; + + union + { + __IM uint8_t POS4; /*!< (@ 0x00000010) Fast Position Byte 4 Register */ + + struct + { + __IM uint8_t POS : 8; /*!< [7..0] Fast position, byte n */ + } POS4_b; + }; + + union + { + __IM uint8_t POS3; /*!< (@ 0x00000011) Fast Position Byte 3 Register */ + + struct + { + __IM uint8_t POS : 8; /*!< [7..0] Fast position, byte n */ + } POS3_b; + }; + + union + { + __IM uint8_t POS2; /*!< (@ 0x00000012) Fast Position Byte 2 Register */ + + struct + { + __IM uint8_t POS : 8; /*!< [7..0] Fast position, byte n */ + } POS2_b; + }; + + union + { + __IM uint8_t POS1; /*!< (@ 0x00000013) Fast Position Byte 1 Register */ + + struct + { + __IM uint8_t POS : 8; /*!< [7..0] Fast position, byte n */ + } POS1_b; + }; + + union + { + __IM uint8_t POS0; /*!< (@ 0x00000014) Fast Position Byte 0 Register */ + + struct + { + __IM uint8_t POS : 8; /*!< [7..0] Fast position, byte n */ + } POS0_b; + }; + + union + { + __IM uint8_t VEL2; /*!< (@ 0x00000015) Speed Byte 2 Register */ + + struct + { + __IM uint8_t VEL : 8; /*!< [7..0] Speed, byte n */ + } VEL2_b; + }; + + union + { + __IM uint8_t VEL1; /*!< (@ 0x00000016) Speed Byte 1 Register */ + + struct + { + __IM uint8_t VEL : 8; /*!< [7..0] Speed, byte n */ + } VEL1_b; + }; + + union + { + __IM uint8_t VEL0; /*!< (@ 0x00000017) Speed Byte 0 Register */ + + struct + { + __IM uint8_t VEL : 8; /*!< [7..0] Speed, byte n */ + } VEL0_b; + }; + + union + { + __IM uint8_t MIR_SUM; /*!< (@ 0x00000018) Mirror Status Summary Register */ + + struct + { + __IM uint8_t SUM : 8; /*!< [7..0] Status summary bit */ + } MIR_SUM_b; + }; + __IM uint8_t RESERVED2[7]; + + union + { + __IOM uint8_t PC_BUF[8]; /*!< (@ 0x00000020) Parameter Channel Buffer n Register (n = 0 to + * 7) */ + + struct + { + __IOM uint8_t PCBUF : 8; /*!< [7..0] Parameter Channel, byte n */ + } PC_BUF_b[8]; + }; + + union + { + __IOM uint8_t PC_ADD_H; /*!< (@ 0x00000028) High Byte Long Message Address Register */ + + struct + { + __OM uint8_t LADDH : 2; /*!< [1..0] Long message address, bit 9 to bit 8 */ + __OM uint8_t LLEN : 2; /*!< [3..2] Data length of the "long message" */ + __OM uint8_t LIND : 1; /*!< [4..4] Indirect addressing of long messages */ + __IOM uint8_t LOFF : 1; /*!< [5..5] Long message addressing mode/long message error */ + __OM uint8_t LRW : 1; /*!< [6..6] Long message, read/write mode */ + uint8_t : 1; + } PC_ADD_H_b; + }; + + union + { + __OM uint8_t PC_ADD_L; /*!< (@ 0x00000029) Low Byte Long Message Address Register */ + + struct + { + __OM uint8_t LADDL : 8; /*!< [7..0] Long message address, bit 7 to bit 0 */ + } PC_ADD_L_b; + }; + + union + { + __IOM uint8_t PC_OFF_H; /*!< (@ 0x0000002A) High Byte Long Message Address Offset Register */ + + struct + { + __OM uint8_t LOFFADDH : 7; /*!< [6..0] Long message offset value, bit 14 to bit 8 */ + __IM uint8_t LID : 1; /*!< [7..7] Long message identification */ + } PC_OFF_H_b; + }; + + union + { + __OM uint8_t PC_OFF_L; /*!< (@ 0x0000002B) Low Byte Long Message Address Offset Register */ + + struct + { + __OM uint8_t LOFFADDL : 8; /*!< [7..0] Long message offset value, bit 7 to bit 0 */ + } PC_OFF_L_b; + }; + + union + { + __OM uint8_t PC_CTRL; /*!< (@ 0x0000002C) Parameter Channel Control Register */ + + struct + { + __OM uint8_t LSTA : 1; /*!< [0..0] Control of the long message start */ + uint8_t : 7; + } PC_CTRL_b; + }; + + union + { + __IM uint8_t PIPE_S; /*!< (@ 0x0000002D) SensorHub Channel Status Register */ + + struct + { + __IM uint8_t PSCI : 1; /*!< [0..0] Indication for special characters in the SensorHub Channel */ + __IM uint8_t PERR : 1; /*!< [1..1] Coding error of the bits in the SensorHub Channel */ + __IM uint8_t PEMP : 1; /*!< [2..2] The SensorHub channel buffer is empty */ + __IM uint8_t POVR : 1; /*!< [3..3] SensorHub Channel overflow */ + uint8_t : 4; + } PIPE_S_b; + }; + + union + { + __IM uint8_t PIPE_D; /*!< (@ 0x0000002E) SensorHub Channel Data Register */ + + struct + { + __IM uint8_t SCDATA : 8; /*!< [7..0] SensorHub Channel data */ + } PIPE_D_b; + }; + + union + { + __IM uint8_t PC_DATA; /*!< (@ 0x0000002F) Parameter Channel Short Message Mirror Register */ + + struct + { + __IM uint8_t PCDATA : 8; /*!< [7..0] "Short message" Mirror register data */ + } PC_DATA_b; + }; + __IM uint8_t RESERVED3[8]; + + union + { + __IOM uint8_t ACC_ERR_CNT; /*!< (@ 0x00000038) Fast Position Error Counter Register */ + + struct + { + __IOM uint8_t CNT : 5; /*!< [4..0] Position error count/threshold */ + uint8_t : 3; + } ACC_ERR_CNT_b; + }; + + union + { + __OM uint8_t MAXACC; /*!< (@ 0x00000039) Fast Position Acceleration Boundary Register */ + + struct + { + __OM uint8_t MNT : 6; /*!< [5..0] Mantissa of fast position acceleration boundary */ + __OM uint8_t RES : 2; /*!< [7..6] Resolution of fast position acceleration boundary */ + } MAXACC_b; + }; + + union + { + __IOM uint8_t MAXDEV_H; /*!< (@ 0x0000003A) Fast Position Estimator Deviation High Byte Register */ + + struct + { + __IOM uint8_t DEVH : 8; /*!< [7..0] Fast position estimator deviation high byte */ + } MAXDEV_H_b; + }; + + union + { + __IOM uint8_t MAXDEV_L; /*!< (@ 0x0000003B) Fast Position Estimator Deviation Low Byte Register */ + + struct + { + __IOM uint8_t DEVL : 8; /*!< [7..0] Fast position estimator deviation low byte */ + } MAXDEV_L_b; + }; + __IM uint8_t RESERVED4[3]; + + union + { + __IM uint8_t DUMMY; /*!< (@ 0x0000003F) Dummy Register */ + + struct + { + __IM uint8_t DUMMY : 8; /*!< [7..0] Due to the transmission of the online-status, Online + * Status read transactions need less time for transmission. + * Therefore, dummy read transactions must be inserted to + * avoid unwanted extra transactions. */ + } DUMMY_b; + }; + __IM uint8_t RESERVED5[32]; + + union + { + __IOM uint8_t MIR_ST[8]; /*!< (@ 0x00000060) Mirror Status n Register (n = 0 to 7) */ + + struct + { + __IOM uint8_t MIRST : 8; /*!< [7..0] Mirror status, byte n */ + } MIR_ST_b[8]; + }; +} R_HDSLD0_Type; /*!< Size = 104 (0x68) */ + +/* =========================================================================================================================== */ +/* ================ R_HDSLS10 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief HIPERFACE DSL for Safe Channel 1 Unit 0 (R_HDSLS10) + */ + +typedef struct /*!< (@ 0x90041000) R_HDSLS10 Structure */ +{ + __IM uint8_t RESERVED[9]; + + union + { + __IM uint8_t EDGES; /*!< (@ 0x00000009) Edge Register */ + + struct + { + __IM uint8_t EDGES : 8; /*!< [7..0] Identification of edges in the cable signal */ + } EDGES_b; + }; + + union + { + __IM uint8_t DELAY; /*!< (@ 0x0000000A) Run Time Delay Register */ + + struct + { + __IM uint8_t CBLDLY : 4; /*!< [3..0] 4-bit value for cable delay */ + __IM uint8_t RSSI : 4; /*!< [7..4] Indication of the received signal strength */ + } DELAY_b; + }; + + union + { + __IM uint8_t VERSION; /*!< (@ 0x0000000B) Version Register */ + + struct + { + __IM uint8_t MINOR : 4; /*!< [3..0] Minor release number */ + __IM uint8_t MAJOR : 2; /*!< [5..4] Major release number */ + __IM uint8_t CODE : 2; /*!< [7..6] Type of module */ + } VERSION_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IM uint8_t ENC_ID2; /*!< (@ 0x0000000D) Encoder ID 2 Register */ + + struct + { + __IM uint8_t ENCID : 4; /*!< [3..0] Encoder designation code bit 19 to bit 16 */ + __IM uint8_t SCI : 3; /*!< [6..4] Indication of special characters */ + uint8_t : 1; + } ENC_ID2_b; + }; + + union + { + __IM uint8_t ENC_ID1; /*!< (@ 0x0000000E) Encoder ID 1 Register */ + + struct + { + __IM uint8_t ENCID : 8; /*!< [7..0] Encoder designation code, byte n */ + } ENC_ID1_b; + }; + + union + { + __IM uint8_t ENC_ID0; /*!< (@ 0x0000000F) Encoder ID 0 Register */ + + struct + { + __IM uint8_t ENCID : 8; /*!< [7..0] Encoder designation code, byte n */ + } ENC_ID0_b; + }; + __IM uint8_t RESERVED2[9]; + + union + { + __IM uint8_t VPOS4; /*!< (@ 0x00000019) Safe Position 4 Register */ + + struct + { + __IM uint8_t VPOS : 8; /*!< [7..0] Safe position, byte n */ + } VPOS4_b; + }; + + union + { + __IM uint8_t VPOS3; /*!< (@ 0x0000001A) Safe Position 3 Register */ + + struct + { + __IM uint8_t VPOS : 8; /*!< [7..0] Safe position, byte n */ + } VPOS3_b; + }; + + union + { + __IM uint8_t VPOS2; /*!< (@ 0x0000001B) Safe Position 2 Register */ + + struct + { + __IM uint8_t VPOS : 8; /*!< [7..0] Safe position, byte n */ + } VPOS2_b; + }; + + union + { + __IM uint8_t VPOS1; /*!< (@ 0x0000001C) Safe Position 1 Register */ + + struct + { + __IM uint8_t VPOS : 8; /*!< [7..0] Safe position, byte n */ + } VPOS1_b; + }; + + union + { + __IM uint8_t VPOS0; /*!< (@ 0x0000001D) Safe Position 0 Register */ + + struct + { + __IM uint8_t VPOS : 8; /*!< [7..0] Safe position, byte n */ + } VPOS0_b; + }; + + union + { + __IM uint8_t VPOSCRC_H; /*!< (@ 0x0000001E) Safe Position CRC High Byte Register */ + + struct + { + __IM uint8_t VPOSCRCH : 8; /*!< [7..0] CRC of the safe position, bit 15 to bit 8 */ + } VPOSCRC_H_b; + }; + + union + { + __IM uint8_t VPOSCRC_L; /*!< (@ 0x0000001F) Safe Position CRC Low Byte Register */ + + struct + { + __IM uint8_t VPOSCRCL : 8; /*!< [7..0] CRC of the safe position, bit 7 to bit 0 */ + } VPOSCRC_L_b; + }; + __IM uint8_t RESERVED3[21]; + + union + { + __IOM uint8_t SAFE_CTRL; /*!< (@ 0x00000035) Safe System Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t MRST : 1; /*!< [6..6] Message reset */ + __IOM uint8_t PRST : 1; /*!< [7..7] Protocol reset */ + } SAFE_CTRL_b; + }; + + union + { + __IM uint8_t SAFE_SUM; /*!< (@ 0x00000036) Safety Status Summary Register */ + + struct + { + __IM uint8_t SSUM : 8; /*!< [7..0] Status summary bit */ + } SAFE_SUM_b; + }; + + union + { + __IM uint8_t S_PC_DATA; /*!< (@ 0x00000037) Parameter Channel Short Message Register */ + + struct + { + __IM uint8_t SPCDATA : 8; /*!< [7..0] "Short message" Parameter Channel data */ + } S_PC_DATA_b; + }; + __IM uint8_t RESERVED4[5]; + + union + { + __IOM uint8_t EVENT_S; /*!< (@ 0x0000003D) Safe Event Register */ + + struct + { + __IOM uint8_t FRES : 1; /*!< [0..0] Channel free for "short message" */ + __IOM uint8_t MIN : 1; /*!< [1..1] Message init */ + __IOM uint8_t PRST : 1; /*!< [2..2] Protocol reset warning */ + __IOM uint8_t QMLW : 1; /*!< [3..3] Quality monitoring low-value warning */ + __IOM uint8_t VPOS : 1; /*!< [4..4] Safe position error */ + __IOM uint8_t SCE : 1; /*!< [5..5] Error on the Safe Channel */ + __IOM uint8_t SSUM : 1; /*!< [6..6] Remote event monitoring */ + __IM uint8_t SINT : 1; /*!< [7..7] Safe interrupt status */ + } EVENT_S_b; + }; + + union + { + __OM uint8_t MASK_S; /*!< (@ 0x0000003E) Safe Event Mask Register */ + + struct + { + __OM uint8_t MFRES : 1; /*!< [0..0] Mask for "channel free for "short message"" */ + __OM uint8_t MMIN : 1; /*!< [1..1] Mask for message initialization confirmation */ + __OM uint8_t MPRST : 1; /*!< [2..2] Mask for protocol reset warning */ + __OM uint8_t MQMLW : 1; /*!< [3..3] Mask for low-quality monitoring value warning */ + __OM uint8_t MVPOS : 1; /*!< [4..4] Mask for safe position error */ + __OM uint8_t MSCE : 1; /*!< [5..5] Mask for transmission errors on the Safe Channel */ + __OM uint8_t MSSUM : 1; /*!< [6..6] Mask for remote event monitoring */ + uint8_t : 1; + } MASK_S_b; + }; + + union + { + __IM uint8_t DUMMY; /*!< (@ 0x0000003F) Dummy Register */ + + struct + { + __IM uint8_t DUMMY : 8; /*!< [7..0] Due to the transmission of the online-status, Online + * Status read transactions need less time for transmission. + * Therefore, dummy read transactions must be inserted to + * avoid unwanted extra transactions. */ + } DUMMY_b; + }; + + union + { + __IOM uint8_t ENC_ST[8]; /*!< (@ 0x00000040) Encoder Status n Register (n = 0 to 7) */ + + struct + { + __IOM uint8_t ENCST : 8; /*!< [7..0] Encoder status, byte n */ + } ENC_ST_b[8]; + }; + __IM uint8_t RESERVED5[52]; + + union + { + __IM uint8_t SRSSI; /*!< (@ 0x0000007C) Slave RSSI Register */ + + struct + { + __IM uint8_t SRSSI : 3; /*!< [2..0] Value of the Slave RSSI */ + uint8_t : 5; + } SRSSI_b; + }; + __IM uint8_t RESERVED6; + + union + { + __OM uint8_t MAIL; /*!< (@ 0x0000007E) Slave Mail Register */ + + struct + { + __OM uint8_t MAIL : 8; /*!< [7..0] Slave-Mail */ + } MAIL_b; + }; + + union + { + __IOM uint8_t PING; /*!< (@ 0x0000007F) Slave Ping Register */ + + struct + { + __IOM uint8_t PING : 8; /*!< [7..0] Slave-Ping */ + } PING_b; + }; +} R_HDSLS10_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_BISS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief BiSS-C Unit 0 (R_BISS0) + */ + +typedef struct /*!< (@ 0x90042000) R_BISS0 Structure */ +{ + __IOM R_BISS0_SCDATA_Type SCDATA[8]; /*!< (@ 0x00000000) Sensor Data [0..7] */ + __IM uint32_t RESERVED[16]; + __IOM uint32_t RDATA[16]; /*!< (@ 0x00000080) Register Data n (n = 1 to 16) */ + + union + { + __IOM uint32_t CNFSLV[8]; /*!< (@ 0x000000C0) Configuration Slave n (n = 1 to 8) */ + + struct + { + __IOM uint32_t SCDLEN : 6; /*!< [5..0] Single-cycle data length of slave n */ + __IOM uint32_t ENSCD : 1; /*!< [6..6] Enable single-cycle data for slave n */ + uint32_t : 1; + __IOM uint32_t SCRCLENPOLY : 7; /*!< [14..8] ● CRC length with predefined CRC polynomial for slave + * n (SCRCLEN[6:0]) */ + __IOM uint32_t SELCRCS : 1; /*!< [15..15] CRC polynomial selection for slave n */ + __IOM uint32_t SCRCSTART : 16; /*!< [31..16] CRC calculation start value for slave n */ + } CNFSLV_b[8]; + }; + + union + { + __IOM uint32_t REGACC; /*!< (@ 0x000000E0) Register Access */ + + struct + { + uint32_t : 16; + __IOM uint32_t REGADR : 7; /*!< [22..16] Register communication start address */ + __IOM uint32_t WNR : 1; /*!< [23..23] Register communication direction */ + __IOM uint32_t REGNUM : 6; /*!< [29..24] Number of consecutive registers to access */ + uint32_t : 2; + } REGACC_b; + }; + + union + { + __IOM uint32_t CTRLCOMM; /*!< (@ 0x000000E4) Control Communication */ + + struct + { + uint32_t : 8; + __IOM uint32_t HOLDCDM : 1; /*!< [8..8] Behavior of MA signal at the end of frame */ + uint32_t : 2; + __IOM uint32_t SID_CMD_IDT : 3; /*!< [13..11] ● Slave addressing for register communication (SLAVEID[2:0]) */ + __IOM uint32_t REGVERS : 1; /*!< [14..14] Type of protocol for register communication */ + __IOM uint32_t CTS : 1; /*!< [15..15] Type of control communication */ + __IOM uint32_t FREQS : 5; /*!< [20..16] Single-cycle data clock frequency at MA (fMA) */ + __IOM uint32_t FREQR : 3; /*!< [23..21] BiSS register data frequency */ + __IOM uint32_t SINGLEBANK : 1; /*!< [24..24] Usage of one/two RAM bank(s) for SCDATA */ + __IOM uint32_t NOCRC : 1; /*!< [25..25] Storage of received CRC in SCDATA */ + uint32_t : 6; + } CTRLCOMM_b; + }; + + union + { + __IOM uint32_t MSTRCNF; /*!< (@ 0x000000E8) Master Configuration */ + + struct + { + __IOM uint32_t FREQAGS : 8; /*!< [7..0] Frame repetition rate (AGS frequency divider) */ + uint32_t : 8; + __IM uint32_t REVISION : 8; /*!< [23..16] Design ID */ + __IM uint32_t VERSION : 8; /*!< [31..24] Version */ + } MSTRCNF_b; + }; + + union + { + __IOM uint32_t CHCNF; /*!< (@ 0x000000EC) Channel Configuration */ + + struct + { + uint32_t : 8; + __IOM uint32_t CFGCH1 : 2; /*!< [9..8] Channel configuration */ + uint32_t : 22; + } CHCNF_b; + }; + + union + { + __IOM uint32_t STINF; /*!< (@ 0x000000F0) Status Information */ + + struct + { + __IM uint32_t EOT : 1; /*!< [0..0] End of transmission */ + uint32_t : 1; + __IM uint32_t REGEND : 1; /*!< [2..2] End of Control Communication */ + __IM uint32_t nREGERR : 1; /*!< [3..3] Control communication error */ + __IM uint32_t nSCDERR : 1; /*!< [4..4] Single-cycle data (SCD) transmission error */ + __IM uint32_t nDELAYERR : 1; /*!< [5..5] Start bit in register communication */ + __IM uint32_t nAGSERR : 1; /*!< [6..6] Automatic Get Sensor (AGS) error */ + __IM uint32_t nERR : 1; /*!< [7..7] State of the error interrupt (NER) */ + __IOM uint32_t SVALID : 16; /*!< [23..8] SCDATAn validity indication (n: slave, n = 1 to 8) */ + __IM uint32_t REGBYTES : 6; /*!< [29..24] Number of valid register bytes */ + __IM uint32_t CDSSEL : 1; /*!< [30..30] State of Control Data Slave (CDS) */ + __IM uint32_t CDMTIMEOUT : 1; /*!< [31..31] Control Data Master (CDM) timeout reached */ + } STINF_b; + }; + + union + { + __IOM uint32_t INSTREG; /*!< (@ 0x000000F4) Instruction Register */ + + struct + { + __IOM uint32_t AGS : 1; /*!< [0..0] Automatic Get Sensor Data (AGS) */ + __IOM uint32_t INSTR : 3; /*!< [3..1] Single-Cycle Data (SCD) Control Instruction */ + __IOM uint32_t INIT : 1; /*!< [4..4] Start initialization sequence */ + __IOM uint32_t SWBANK : 1; /*!< [5..5] RAM Bank Switching */ + __IOM uint32_t HOLDBANK : 1; /*!< [6..6] RAM Bank Control */ + __IOM uint32_t BREAK : 1; /*!< [7..7] Start BREAK Sequence */ + uint32_t : 4; + __IOM uint32_t MAFS : 1; /*!< [12..12] Control of the MA line */ + __IOM uint32_t MAVS : 1; /*!< [13..13] MA line force level */ + uint32_t : 18; + } INSTREG_b; + }; + + union + { + __IM uint32_t STINF2; /*!< (@ 0x000000F8) Status Information 2 */ + + struct + { + __IM uint32_t SL1 : 1; /*!< [0..0] SL input line state */ + __IM uint32_t CDS1 : 1; /*!< [1..1] Control Data Slave (CDS) bit value */ + uint32_t : 14; + __IM uint32_t IDL : 4; /*!< [19..16] Number of set ID lock bits during control communication */ + uint32_t : 4; + __IM uint32_t SWBANKFAIL : 1; /*!< [24..24] Bank switching status */ + uint32_t : 7; + } STINF2_b; + }; +} R_BISS0_Type; /*!< Size = 252 (0xfc) */ + +/* =========================================================================================================================== */ +/* ================ R_ENDAT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief EnDat2.2 Unit 0 (R_ENDAT0) + */ + +typedef struct /*!< (@ 0x90043000) R_ENDAT0 Structure */ +{ + union + { + __IOM uint32_t SEND; /*!< (@ 0x00000000) Send Register */ + + struct + { + __IOM uint32_t D : 16; /*!< [15..0] Parameters, Instructions */ + __IOM uint32_t A : 8; /*!< [23..16] Memory Range Select (MRS) code, Address, Port address */ + __IOM uint32_t M : 6; /*!< [29..24] Mode command */ + uint32_t : 2; + } SEND_b; + }; + + union + { + __IM uint32_t EMPFR1_L; /*!< (@ 0x00000004) Receive Register 1, Low Double Word */ + + struct + { + __IM uint32_t RDATA_L : 32; /*!< [31..0] Received data, bit 31 to bit 0 */ + } EMPFR1_L_b; + }; + + union + { + __IM uint32_t EMPFR1_H; /*!< (@ 0x00000008) Receive Register 1, High Double Word */ + + struct + { + __IM uint32_t RDATA_H : 16; /*!< [15..0] Received data, bit 47 to bit 32 */ + __IM uint32_t CRC : 5; /*!< [20..16] Received CRC */ + __IM uint32_t F1 : 1; /*!< [21..21] Safety-relevant error bit F1 */ + __IM uint32_t IF2 : 1; /*!< [22..22] Safety-relevant error bit F2 inversion */ + __IM uint32_t POS1 : 1; /*!< [23..23] Absolute position value 1 */ + uint32_t : 8; + } EMPFR1_H_b; + }; + + union + { + __IM uint32_t EMPFR2; /*!< (@ 0x0000000C) Receive Register 2 */ + + struct + { + __IM uint32_t RDATA2 : 32; /*!< [31..0] Received data 2 */ + } EMPFR2_b; + }; + + union + { + __IM uint32_t EMPFR3; /*!< (@ 0x00000010) Receive Register 3 */ + + struct + { + __IM uint32_t D : 16; /*!< [15..0] Data in the additional information 1 */ + __IM uint32_t C : 8; /*!< [23..16] Memory Range Select (MRS) code in the additional information + * 1 */ + __IM uint32_t CRC : 5; /*!< [28..24] CRC for additional information 1 */ + uint32_t : 3; + } EMPFR3_b; + }; + + union + { + __IOM uint32_t KONFR1; /*!< (@ 0x00000014) Configuration Register 1 */ + + struct + { + __IOM uint32_t HWSTRB : 1; /*!< [0..0] Hardware strobe */ + __IOM uint32_t DU : 1; /*!< [1..1] DU */ + __IOM uint32_t DT : 1; /*!< [2..2] DT */ + uint32_t : 1; + __IOM uint32_t FTCLK : 4; /*!< [7..4] fTCLK */ + __IOM uint32_t DWLG : 6; /*!< [13..8] Data word length */ + __IOM uint32_t RSTWD : 1; /*!< [14..14] Reset window */ + __IOM uint32_t AUTORST : 1; /*!< [15..15] Automatic reset */ + __IOM uint32_t CPTIME : 8; /*!< [23..16] Cable propagation time */ + __IOM uint32_t DELAYCMP : 1; /*!< [24..24] Delay compensation */ + uint32_t : 1; + __IOM uint32_t FSYS : 3; /*!< [28..26] System clock frequency (fsys) */ + __IOM uint32_t ICRST : 1; /*!< [29..29] IC reset */ + __IOM uint32_t SET : 2; /*!< [31..30] EnDat set */ + } KONFR1_b; + }; + + union + { + __IOM uint32_t KONFR2; /*!< (@ 0x00000018) Configuration Register 2 */ + + struct + { + __IOM uint32_t TMSMPLRATE : 8; /*!< [7..0] Timer for sampling rate */ + __IOM uint32_t WTDOG : 8; /*!< [15..8] Watchdog */ + __IOM uint32_t RCVTIME : 3; /*!< [18..16] Recovery time III tST */ + __IOM uint32_t FILTER : 3; /*!< [21..19] Filter */ + uint32_t : 2; + __IOM uint32_t HWSTRBDLY : 8; /*!< [31..24] Hardware strobe delay */ + } KONFR2_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t STATR; /*!< (@ 0x00000020) Status Register */ + + struct + { + __IOM uint32_t EMPFR1 : 1; /*!< [0..0] EMPFR1 register update */ + __IOM uint32_t ERR1 : 1; /*!< [1..1] Error 1 */ + __IOM uint32_t CRC_PRTY : 1; /*!< [2..2] CRC-PW / parity */ + __IOM uint32_t FTYPI : 1; /*!< [3..3] F Type I */ + __IOM uint32_t FTYPII : 1; /*!< [4..4] F Type II */ + __IOM uint32_t MRS_ADR : 1; /*!< [5..5] MRS/Adr */ + uint32_t : 2; + __IOM uint32_t EMPFR2 : 1; /*!< [8..8] EMPFR2 register update */ + __IOM uint32_t EMPFR3 : 1; /*!< [9..9] EMPFR3 register update */ + __IOM uint32_t IERR2 : 1; /*!< [10..10] /Error2 */ + __IOM uint32_t CRCZI1 : 1; /*!< [11..11] CRC-ZI1 */ + __IOM uint32_t CRCZI2 : 1; /*!< [12..12] CRC-ZI2 */ + __IOM uint32_t BUSY : 1; /*!< [13..13] Busy */ + __IOM uint32_t RM : 1; /*!< [14..14] RM */ + __IOM uint32_t WRN : 1; /*!< [15..15] WRN */ + __IOM uint32_t SPIKE : 1; /*!< [16..16] Spike */ + __IOM uint32_t WTDG : 1; /*!< [17..17] Watchdog */ + __IOM uint32_t FTYPIII : 1; /*!< [18..18] F Type III */ + uint32_t : 3; + __IOM uint32_t LZK : 1; /*!< [22..22] Delay compensation */ + __IOM uint32_t LZM : 1; /*!< [23..23] Propagation time measurement */ + uint32_t : 5; + __IOM uint32_t SPDRDY : 1; /*!< [29..29] Speed ready */ + __IOM uint32_t RDY4STRB : 1; /*!< [30..30] Ready for strobe */ + __IOM uint32_t RDY : 1; /*!< [31..31] Ready */ + } STATR_b; + }; + + union + { + __IOM uint32_t INTMR; /*!< (@ 0x00000024) Interrupt Mask Register */ + + struct + { + __IOM uint32_t EMPFR1 : 1; /*!< [0..0] Interrupt mask for EMPFR1 register update */ + __IOM uint32_t ERR1 : 1; /*!< [1..1] Interrupt mask for Error 1 */ + __IOM uint32_t CRC_PRTY : 1; /*!< [2..2] Interrupt mask for CRC-PW / parity */ + __IOM uint32_t FTYPI : 1; /*!< [3..3] Interrupt mask for F Type I */ + __IOM uint32_t FTYPII : 1; /*!< [4..4] Interrupt mask for F Type II */ + __IOM uint32_t MRS_ADR : 1; /*!< [5..5] Interrupt mask for MRS/Adr */ + uint32_t : 2; + __IOM uint32_t EMPFR2 : 1; /*!< [8..8] Interrupt mask for EMPFR2 register update */ + __IOM uint32_t EMPFR3 : 1; /*!< [9..9] Interrupt mask for EMPFR3 register update */ + __IOM uint32_t IERR2 : 1; /*!< [10..10] Interrupt mask for /Error2 */ + __IOM uint32_t CRCZI1 : 1; /*!< [11..11] Interrupt mask for CRC-ZI1 */ + __IOM uint32_t CRCZI2 : 1; /*!< [12..12] Interrupt mask for CRC-ZI2 */ + __IOM uint32_t BUSY : 1; /*!< [13..13] Interrupt mask for Busy */ + __IOM uint32_t RM : 1; /*!< [14..14] Interrupt mask for RM */ + __IOM uint32_t WRN : 1; /*!< [15..15] Interrupt mask for WRN */ + __IOM uint32_t SPIKE : 1; /*!< [16..16] Interrupt mask for Spike */ + __IOM uint32_t WTDG : 1; /*!< [17..17] Interrupt mask for Watchdog */ + __IOM uint32_t FTYPIII : 1; /*!< [18..18] Interrupt mask for F Type III */ + uint32_t : 10; + __IOM uint32_t SPDRDY : 1; /*!< [29..29] Interrupt mask for Speed ready */ + uint32_t : 1; + __IOM uint32_t RDY : 1; /*!< [31..31] Interrupt mask for Ready */ + } INTMR_b; + }; + __IM uint32_t RESERVED1[4]; + __OM uint32_t SWSTRBR; /*!< (@ 0x00000038) SW Strobe Register */ + __IM uint32_t IDR; /*!< (@ 0x0000003C) ID Register */ +} R_ENDAT0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_AFMT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A-format Unit 0 (R_AFMT0) + */ + +typedef struct /*!< (@ 0x90045000) R_AFMT0 Structure */ +{ + union + { + union + { + __OM uint32_t COMMAND; /*!< (@ 0x00000000) Command Code Encoder Address Register */ + + struct + { + __OM uint32_t XEA : 3; /*!< [2..0] Encoder address */ + __OM uint32_t CC : 5; /*!< [7..3] Command code */ + __OM uint32_t SID : 5; /*!< [12..8] Subcommand ID */ + uint32_t : 19; + } COMMAND_b; + }; + + union + { + __IM uint32_t ENC1RXDATA0; /*!< (@ 0x00000000) ENC1 Receive Data 0 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC1RXDATA0_b; + }; + }; + + union + { + union + { + __IM uint32_t ENC1RXDATA1; /*!< (@ 0x00000004) ENC1 Receive Data 1 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC1RXDATA1_b; + }; + + union + { + __OM uint32_t ROMDATA; /*!< (@ 0x00000004) EEPROM Address and Write Data Register */ + + struct + { + __OM uint32_t DATA : 16; /*!< [15..0] 16-bit EEPROM data */ + __OM uint32_t ADDR : 8; /*!< [23..16] 8-bit EEPROM address */ + uint32_t : 8; + } ROMDATA_b; + }; + }; + + union + { + union + { + __IM uint32_t ENC1RXDATA2; /*!< (@ 0x00000008) ENC1 Receive Data 2 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC1RXDATA2_b; + }; + + union + { + __OM uint32_t ID; /*!< (@ 0x00000008) ID Code Register */ + + struct + { + __OM uint32_t ID_L : 16; /*!< [15..0] 24-bit ID code, low word */ + __OM uint32_t ID_H : 8; /*!< [23..16] 24-bit ID code, high byte */ + uint32_t : 8; + } ID_b; + }; + }; + + union + { + __IM uint32_t ENC1RXDATA3; /*!< (@ 0x0000000C) ENC1 Receive Data 3 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC1RXDATA3_b; + }; + + union + { + __IM uint32_t ENC1RXDATA4; /*!< (@ 0x00000010) ENC1 Receive Data 4 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC1RXDATA4_b; + }; + + union + { + __IM uint32_t ENC1RXDATA5; /*!< (@ 0x00000014) ENC1 Receive Data 5 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC1RXDATA5_b; + }; + + union + { + __IM uint32_t ENC1RXDATA6; /*!< (@ 0x00000018) ENC1 Receive Data 6 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC1RXDATA6_b; + }; + + union + { + __IM uint32_t ENC1RXDATA7; /*!< (@ 0x0000001C) ENC1 Receive Data 7 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC1RXDATA7_b; + }; + + union + { + __IM uint32_t ENC2RXDATA0; /*!< (@ 0x00000020) ENC2 Receive Data 0 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC2RXDATA0_b; + }; + + union + { + __IM uint32_t ENC2RXDATA1; /*!< (@ 0x00000024) ENC2 Receive Data 1 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC2RXDATA1_b; + }; + + union + { + __IM uint32_t ENC2RXDATA2; /*!< (@ 0x00000028) ENC2 Receive Data 2 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC2RXDATA2_b; + }; + + union + { + __IM uint32_t ENC2RXDATA3; /*!< (@ 0x0000002C) ENC2 Receive Data 3 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC2RXDATA3_b; + }; + + union + { + __IM uint32_t ENC2RXDATA4; /*!< (@ 0x00000030) ENC2 Receive Data 4 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC2RXDATA4_b; + }; + + union + { + __IM uint32_t ENC2RXDATA5; /*!< (@ 0x00000034) ENC2 Receive Data 5 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC2RXDATA5_b; + }; + + union + { + __IM uint32_t ENC2RXDATA6; /*!< (@ 0x00000038) ENC2 Receive Data 6 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC2RXDATA6_b; + }; + + union + { + __IM uint32_t ENC2RXDATA7; /*!< (@ 0x0000003C) ENC2 Receive Data 7 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC2RXDATA7_b; + }; + + union + { + __IM uint32_t ENC3RXDATA0; /*!< (@ 0x00000040) ENC3 Receive Data 0 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC3RXDATA0_b; + }; + + union + { + __IM uint32_t ENC3RXDATA1; /*!< (@ 0x00000044) ENC3 Receive Data 1 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC3RXDATA1_b; + }; + + union + { + __IM uint32_t ENC3RXDATA2; /*!< (@ 0x00000048) ENC3 Receive Data 2 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC3RXDATA2_b; + }; + + union + { + __IM uint32_t ENC3RXDATA3; /*!< (@ 0x0000004C) ENC3 Receive Data 3 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC3RXDATA3_b; + }; + + union + { + __IM uint32_t ENC3RXDATA4; /*!< (@ 0x00000050) ENC3 Receive Data 4 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC3RXDATA4_b; + }; + + union + { + __IM uint32_t ENC3RXDATA5; /*!< (@ 0x00000054) ENC3 Receive Data 5 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC3RXDATA5_b; + }; + + union + { + __IM uint32_t ENC3RXDATA6; /*!< (@ 0x00000058) ENC3 Receive Data 6 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC3RXDATA6_b; + }; + + union + { + __IM uint32_t ENC3RXDATA7; /*!< (@ 0x0000005C) ENC3 Receive Data 7 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC3RXDATA7_b; + }; + + union + { + __IM uint32_t ENC4RXDATA0; /*!< (@ 0x00000060) ENC4 Receive Data 0 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC4RXDATA0_b; + }; + + union + { + __IM uint32_t ENC4RXDATA1; /*!< (@ 0x00000064) ENC4 Receive Data 1 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC4RXDATA1_b; + }; + + union + { + __IM uint32_t ENC4RXDATA2; /*!< (@ 0x00000068) ENC4 Receive Data 2 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC4RXDATA2_b; + }; + + union + { + __IM uint32_t ENC4RXDATA3; /*!< (@ 0x0000006C) ENC4 Receive Data 3 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC4RXDATA3_b; + }; + + union + { + __IM uint32_t ENC4RXDATA4; /*!< (@ 0x00000070) ENC4 Receive Data 4 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC4RXDATA4_b; + }; + + union + { + __IM uint32_t ENC4RXDATA5; /*!< (@ 0x00000074) ENC4 Receive Data 5 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC4RXDATA5_b; + }; + + union + { + __IM uint32_t ENC4RXDATA6; /*!< (@ 0x00000078) ENC4 Receive Data 6 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC4RXDATA6_b; + }; + + union + { + __IM uint32_t ENC4RXDATA7; /*!< (@ 0x0000007C) ENC4 Receive Data 7 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC4RXDATA7_b; + }; + + union + { + __IM uint32_t ENC5RXDATA0; /*!< (@ 0x00000080) ENC5 Receive Data 0 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC5RXDATA0_b; + }; + + union + { + __IM uint32_t ENC5RXDATA1; /*!< (@ 0x00000084) ENC5 Receive Data 1 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC5RXDATA1_b; + }; + + union + { + __IM uint32_t ENC5RXDATA2; /*!< (@ 0x00000088) ENC5 Receive Data 2 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC5RXDATA2_b; + }; + + union + { + __IM uint32_t ENC5RXDATA3; /*!< (@ 0x0000008C) ENC5 Receive Data 3 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC5RXDATA3_b; + }; + + union + { + __IM uint32_t ENC5RXDATA4; /*!< (@ 0x00000090) ENC5 Receive Data 4 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC5RXDATA4_b; + }; + + union + { + __IM uint32_t ENC5RXDATA5; /*!< (@ 0x00000094) ENC5 Receive Data 5 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC5RXDATA5_b; + }; + + union + { + __IM uint32_t ENC5RXDATA6; /*!< (@ 0x00000098) ENC5 Receive Data 6 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC5RXDATA6_b; + }; + + union + { + __IM uint32_t ENC5RXDATA7; /*!< (@ 0x0000009C) ENC5 Receive Data 7 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC5RXDATA7_b; + }; + + union + { + __IM uint32_t ENC6RXDATA0; /*!< (@ 0x000000A0) ENC6 Receive Data 0 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC6RXDATA0_b; + }; + + union + { + __IM uint32_t ENC6RXDATA1; /*!< (@ 0x000000A4) ENC6 Receive Data 1 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC6RXDATA1_b; + }; + + union + { + __IM uint32_t ENC6RXDATA2; /*!< (@ 0x000000A8) ENC6 Receive Data 2 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC6RXDATA2_b; + }; + + union + { + __IM uint32_t ENC6RXDATA3; /*!< (@ 0x000000AC) ENC6 Receive Data 3 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC6RXDATA3_b; + }; + + union + { + __IM uint32_t ENC6RXDATA4; /*!< (@ 0x000000B0) ENC6 Receive Data 4 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC6RXDATA4_b; + }; + + union + { + __IM uint32_t ENC6RXDATA5; /*!< (@ 0x000000B4) ENC6 Receive Data 5 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC6RXDATA5_b; + }; + + union + { + __IM uint32_t ENC6RXDATA6; /*!< (@ 0x000000B8) ENC6 Receive Data 6 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC6RXDATA6_b; + }; + + union + { + __IM uint32_t ENC6RXDATA7; /*!< (@ 0x000000BC) ENC6 Receive Data 7 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC6RXDATA7_b; + }; + + union + { + __IM uint32_t ENC7RXDATA0; /*!< (@ 0x000000C0) ENC7 Receive Data 0 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC7RXDATA0_b; + }; + + union + { + __IM uint32_t ENC7RXDATA1; /*!< (@ 0x000000C4) ENC7 Receive Data 1 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC7RXDATA1_b; + }; + + union + { + __IM uint32_t ENC7RXDATA2; /*!< (@ 0x000000C8) ENC7 Receive Data 2 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC7RXDATA2_b; + }; + + union + { + __IM uint32_t ENC7RXDATA3; /*!< (@ 0x000000CC) ENC7 Receive Data 3 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC7RXDATA3_b; + }; + + union + { + __IM uint32_t ENC7RXDATA4; /*!< (@ 0x000000D0) ENC7 Receive Data 4 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC7RXDATA4_b; + }; + + union + { + __IM uint32_t ENC7RXDATA5; /*!< (@ 0x000000D4) ENC7 Receive Data 5 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC7RXDATA5_b; + }; + + union + { + __IM uint32_t ENC7RXDATA6; /*!< (@ 0x000000D8) ENC7 Receive Data 6 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC7RXDATA6_b; + }; + + union + { + __IM uint32_t ENC7RXDATA7; /*!< (@ 0x000000DC) ENC7 Receive Data 7 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC7RXDATA7_b; + }; + + union + { + __IM uint32_t ENC8RXDATA0; /*!< (@ 0x000000E0) ENC8 Receive Data 0 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC8RXDATA0_b; + }; + + union + { + __IM uint32_t ENC8RXDATA1; /*!< (@ 0x000000E4) ENC8 Receive Data 1 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC8RXDATA1_b; + }; + + union + { + __IM uint32_t ENC8RXDATA2; /*!< (@ 0x000000E8) ENC8 Receive Data 2 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC8RXDATA2_b; + }; + + union + { + __IM uint32_t ENC8RXDATA3; /*!< (@ 0x000000EC) ENC8 Receive Data 3 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC8RXDATA3_b; + }; + + union + { + __IM uint32_t ENC8RXDATA4; /*!< (@ 0x000000F0) ENC8 Receive Data 4 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC8RXDATA4_b; + }; + + union + { + __IM uint32_t ENC8RXDATA5; /*!< (@ 0x000000F4) ENC8 Receive Data 5 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC8RXDATA5_b; + }; + + union + { + __IM uint32_t ENC8RXDATA6; /*!< (@ 0x000000F8) ENC8 Receive Data 6 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC8RXDATA6_b; + }; + + union + { + __IM uint32_t ENC8RXDATA7; /*!< (@ 0x000000FC) ENC8 Receive Data 7 Register */ + + struct + { + __IM uint32_t DATA : 32; /*!< [31..0] Encoder read data */ + } ENC8RXDATA7_b; + }; + + union + { + __OM uint32_t TRGSEL; /*!< (@ 0x00000100) Trigger Select Register */ + + struct + { + __OM uint32_t EXT : 1; /*!< [0..0] Trigger select */ + uint32_t : 31; + } TRGSEL_b; + }; + + union + { + __OM uint32_t TXTRG; /*!< (@ 0x00000104) Transmission Trigger Register */ + + struct + { + __OM uint32_t TRG : 1; /*!< [0..0] Command data transmission trigger generation */ + uint32_t : 31; + } TXTRG_b; + }; + __IM uint32_t RESERVED[62]; + + union + { + __OM uint32_t BRSEL; /*!< (@ 0x00000200) Baud Rate Setting Register */ + + struct + { + __OM uint32_t BR : 3; /*!< [2..0] Baud rate setting */ + __OM uint32_t AS : 1; /*!< [3..3] A-Safety enable */ + __OM uint32_t TM : 8; /*!< [11..4] t2 time setting N */ + uint32_t : 20; + } BRSEL_b; + }; +} R_AFMT0_Type; /*!< Size = 516 (0x204) */ + +/* =========================================================================================================================== */ +/* ================ R_ENCOUT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Encoder Divided-Output Module (R_ENCOUT) + */ + +typedef struct /*!< (@ 0x90060000) R_ENCOUT Structure */ +{ + union + { + __IOM uint32_t CTL; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t POL : 1; /*!< [0..0] Polarity of Phase B */ + __IOM uint32_t ZW : 3; /*!< [3..1] Pulse Width of Phase Z */ + __IOM uint32_t ZS : 1; /*!< [4..4] Synchronization phase of Phase Z */ + uint32_t : 27; + } CTL_b; + }; + + union + { + __IOM uint32_t STR; /*!< (@ 0x00000004) Start Register */ + + struct + { + __IOM uint32_t ENCE : 1; /*!< [0..0] ENCOUT Operation Start */ + uint32_t : 31; + } STR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t POSMAX_PERIOD; /*!< (@ 0x0000000C) Maximum Position and Carrier Period Register */ + + struct + { + __IOM uint32_t PERIOD : 16; /*!< [15..0] Carrier Period Setting */ + __IOM uint32_t POSMAX : 16; /*!< [31..16] Maximum Position Setting */ + } POSMAX_PERIOD_b; + }; + + union + { + __IOM uint32_t OUTCNT; /*!< (@ 0x00000010) Output Count Register */ + + struct + { + __IOM uint32_t EDGCNT : 16; /*!< [15..0] Edge Count Setting */ + uint32_t : 16; + } OUTCNT_b; + }; + + union + { + __IOM uint32_t POSCNT; /*!< (@ 0x00000014) Position Count Register */ + + struct + { + __IOM uint32_t POSCNT : 16; /*!< [15..0] Current Position */ + uint32_t : 16; + } POSCNT_b; + }; +} R_ENCOUT_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_GSC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Global System Counter (R_GSC) + */ + +typedef struct /*!< (@ 0xC0060000) R_GSC Structure */ +{ + union + { + __IOM uint32_t CNTCR; /*!< (@ 0x00000000) Global System Counter Control Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Counter Enable */ + __IOM uint32_t HDBG : 1; /*!< [1..1] Halt on Debug */ + uint32_t : 30; + } CNTCR_b; + }; + + union + { + __IM uint32_t CNTSR; /*!< (@ 0x00000004) Global System Counter Status Register */ + + struct + { + uint32_t : 1; + __IM uint32_t DBGH : 1; /*!< [1..1] Debug Halted */ + uint32_t : 30; + } CNTSR_b; + }; + + union + { + __IOM uint32_t CNTCVL; /*!< (@ 0x00000008) Global System Counter Current Value Lower Register */ + + struct + { + __IOM uint32_t CNTCVL_L_32 : 32; /*!< [31..0] Current value of the counter, lower 32 bits */ + } CNTCVL_b; + }; + + union + { + __IOM uint32_t CNTCVU; /*!< (@ 0x0000000C) Global System Counter Current Value Upper Register */ + + struct + { + __IOM uint32_t CNTCVU_U_32 : 32; /*!< [31..0] Current value of the counter, upper 32 bits */ + } CNTCVU_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t CNTFID0; /*!< (@ 0x00000020) Global System Counter Base Frequency ID Register */ + + struct + { + __IOM uint32_t FREQ : 32; /*!< [31..0] Frequency in number of ticks per second */ + } CNTFID0_b; + }; +} R_GSC_Type; /*!< Size = 36 (0x24) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_GPT7_BASE 0x80000000UL + #define R_GPT8_BASE 0x80000100UL + #define R_GPT9_BASE 0x80000200UL + #define R_GPT10_BASE 0x80000300UL + #define R_GPT11_BASE 0x80000400UL + #define R_GPT12_BASE 0x80000500UL + #define R_GPT13_BASE 0x80000600UL + #define R_SCI0_BASE 0x80001000UL + #define R_SCI1_BASE 0x80001400UL + #define R_SCI2_BASE 0x80001800UL + #define R_SCI3_BASE 0x80001C00UL + #define R_SCI4_BASE 0x80002000UL + #define R_SPI0_BASE 0x80003000UL + #define R_SPI1_BASE 0x80003400UL + #define R_SPI2_BASE 0x80003800UL + #define R_CRC0_BASE 0x80004000UL + #define R_CANFD_BASE 0x80020000UL + #define R_CMT_BASE 0x80040000UL + #define R_CMTW0_BASE 0x80041000UL + #define R_CMTW1_BASE 0x80041400UL + #define R_WDT0_BASE 0x80042000UL + #define R_IIC0_BASE 0x80043000UL + #define R_IIC1_BASE 0x80043400UL + #define R_DOC_BASE 0x80044000UL + #define R_TSU_BASE 0x80046000UL + #define R_POEG1_BASE 0x80047000UL + #define R_DMAC0_BASE 0x80080000UL + #define R_DMAC1_BASE 0x80081000UL + #define R_ICU_NS_BASE 0x80090000UL + #define R_ELC_BASE 0x80090010UL + #define R_DMA_BASE 0x80090060UL + #define R_PORT_NSR_BASE 0x800A0000UL + #define R_GMAC_BASE 0x80100000UL + #define R_ETHSS_BASE 0x80110000UL + #define R_ESC_INI_BASE 0x80110200UL + #define R_GMAC_PTP_BASE 0x80110400UL + #define R_ESC_BASE 0x80130000UL + #define R_USBHC_BASE 0x80200000UL + #define R_USBF_BASE 0x80201000UL + #define R_BSC_BASE 0x80210000UL + #define R_XSPI0_BASE 0x80220000UL + #define R_XSPI1_BASE 0x80221000UL + #define R_MBXSEM_BASE 0x80240000UL + #define R_SHOSTIF_BASE 0x80241000UL + #define R_SYSC_NS_BASE 0x80280000UL + #define R_ELO_BASE 0x80281200UL + #define R_ENCSS_BASE 0x80281400UL + #define R_RWP_NS_BASE 0x80281A10UL + #define R_GPT14_BASE 0x81000000UL + #define R_GPT15_BASE 0x81000100UL + #define R_GPT16_BASE 0x81000200UL + #define R_GPT17_BASE 0x81000300UL + #define R_SCI5_BASE 0x81001000UL + #define R_SPI3_BASE 0x81002000UL + #define R_CRC1_BASE 0x81003000UL + #define R_IIC2_BASE 0x81008000UL + #define R_RTC_BASE 0x81009000UL + #define R_POEG2_BASE 0x8100A000UL + #define R_OTP_BASE 0x81028000UL + #define R_PORT_SR_BASE 0x81030000UL + #define R_PTADR_BASE 0x81030C00UL + #define R_SYSRAM0_BASE 0x81040000UL + #define R_SYSRAM1_BASE 0x81041000UL + #define R_ICU_BASE 0x81048000UL + #define R_SYSC_S_BASE 0x81280000UL + #define R_CLMA0_BASE 0x81280800UL + #define R_CLMA1_BASE 0x81280820UL + #define R_CLMA2_BASE 0x81280840UL + #define R_CLMA3_BASE 0x81280860UL + #define R_MPU0_BASE 0x81281100UL + #define R_MPU1_BASE 0x81281200UL + #define R_MPU2_BASE 0x81281300UL + #define R_MPU3_BASE 0x81281400UL + #define R_MPU4_BASE 0x81281500UL + #define R_MPU6_BASE 0x81281700UL + #define R_SYSRAM_CTL_BASE 0x81281800UL + #define R_TCMAW_BASE 0x81281900UL + #define R_SHOSTIF_CFG_BASE 0x81281920UL + #define R_RWP_S_BASE 0x81281A00UL + #define R_MPU7_BASE 0x81281C00UL + #define R_MTU_BASE 0x90001000UL + #define R_MTU3_BASE 0x90001100UL + #define R_MTU4_BASE 0x90001200UL + #define R_MTU_NF_BASE 0x90001290UL + #define R_MTU0_BASE 0x90001300UL + #define R_MTU1_BASE 0x90001380UL + #define R_MTU2_BASE 0x90001400UL + #define R_MTU8_BASE 0x90001600UL + #define R_MTU6_BASE 0x90001900UL + #define R_MTU7_BASE 0x90001A00UL + #define R_MTU5_BASE 0x90001C00UL + #define R_GPT0_BASE 0x90002000UL + #define R_GPT1_BASE 0x90002100UL + #define R_GPT2_BASE 0x90002200UL + #define R_GPT3_BASE 0x90002300UL + #define R_GPT4_BASE 0x90002400UL + #define R_GPT5_BASE 0x90002500UL + #define R_GPT6_BASE 0x90002600UL + #define R_TFU_BASE 0x90003000UL + #define R_ADC120_BASE 0x90004000UL + #define R_ADC121_BASE 0x90004800UL + #define R_POE3_BASE 0x90005000UL + #define R_POEG0_BASE 0x90006000UL + #define R_DSMIF0_BASE 0x90008000UL + #define R_DSMIF1_BASE 0x90008800UL + #define R_HDSLD0_BASE 0x90040000UL + #define R_HDSLS10_BASE 0x90041000UL + #define R_BISS0_BASE 0x90042000UL + #define R_ENDAT0_BASE 0x90043000UL + #define R_AFMT0_BASE 0x90045000UL + #define R_HDSLD1_BASE 0x90050000UL + #define R_HDSLS11_BASE 0x90051000UL + #define R_BISS1_BASE 0x90052000UL + #define R_ENDAT1_BASE 0x90053000UL + #define R_AFMT1_BASE 0x90055000UL + #define R_ENCOUT_BASE 0x90060000UL + #define R_GSC_BASE 0xC0060000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) + #define R_CRC0 ((R_CRC0_Type *) R_CRC0_BASE) + #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CMT ((R_CMT_Type *) R_CMT_BASE) + #define R_CMTW0 ((R_CMTW0_Type *) R_CMTW0_BASE) + #define R_CMTW1 ((R_CMTW0_Type *) R_CMTW1_BASE) + #define R_WDT0 ((R_WDT0_Type *) R_WDT0_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_TSU ((R_TSU_Type *) R_TSU_BASE) + #define R_POEG1 ((R_POEG1_Type *) R_POEG1_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_ICU_NS ((R_ICU_NS_Type *) R_ICU_NS_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_PORT_NSR ((R_PORT_COMMON_Type *) R_PORT_NSR_BASE) + #define R_GMAC ((R_GMAC_Type *) R_GMAC_BASE) + #define R_ETHSS ((R_ETHSS_Type *) R_ETHSS_BASE) + #define R_ESC_INI ((R_ESC_INI_Type *) R_ESC_INI_BASE) + #define R_GMAC_PTP ((R_GMAC_PTP_Type *) R_GMAC_PTP_BASE) + #define R_ESC ((R_ESC_Type *) R_ESC_BASE) + #define R_USBHC ((R_USBHC_Type *) R_USBHC_BASE) + #define R_USBF ((R_USBF_Type *) R_USBF_BASE) + #define R_BSC ((R_BSC_Type *) R_BSC_BASE) + #define R_XSPI0 ((R_XSPI0_Type *) R_XSPI0_BASE) + #define R_XSPI1 ((R_XSPI0_Type *) R_XSPI1_BASE) + #define R_MBXSEM ((R_MBXSEM_Type *) R_MBXSEM_BASE) + #define R_SHOSTIF ((R_SHOSTIF_Type *) R_SHOSTIF_BASE) + #define R_SYSC_NS ((R_SYSC_NS_Type *) R_SYSC_NS_BASE) + #define R_ELO ((R_ELO_Type *) R_ELO_BASE) + #define R_ENCSS ((R_ENCSS_Type *) R_ENCSS_BASE) + #define R_RWP_NS ((R_RWP_NS_Type *) R_RWP_NS_BASE) + #define R_GPT14 ((R_GPT0_Type *) R_GPT14_BASE) + #define R_GPT15 ((R_GPT0_Type *) R_GPT15_BASE) + #define R_GPT16 ((R_GPT0_Type *) R_GPT16_BASE) + #define R_GPT17 ((R_GPT0_Type *) R_GPT17_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SPI3 ((R_SPI0_Type *) R_SPI3_BASE) + #define R_CRC1 ((R_CRC0_Type *) R_CRC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_POEG2 ((R_POEG2_Type *) R_POEG2_BASE) + #define R_OTP ((R_OTP_Type *) R_OTP_BASE) + #define R_PORT_SR ((R_PORT_COMMON_Type *) R_PORT_SR_BASE) + #define R_PTADR ((R_PTADR_Type *) R_PTADR_BASE) + #define R_SYSRAM0 ((R_SYSRAM0_Type *) R_SYSRAM0_BASE) + #define R_SYSRAM1 ((R_SYSRAM0_Type *) R_SYSRAM1_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_SYSC_S ((R_SYSC_S_Type *) R_SYSC_S_BASE) + #define R_CLMA0 ((R_CLMA0_Type *) R_CLMA0_BASE) + #define R_CLMA1 ((R_CLMA0_Type *) R_CLMA1_BASE) + #define R_CLMA2 ((R_CLMA0_Type *) R_CLMA2_BASE) + #define R_CLMA3 ((R_CLMA0_Type *) R_CLMA3_BASE) + #define R_MPU0 ((R_MPU0_Type *) R_MPU0_BASE) + #define R_MPU1 ((R_MPU0_Type *) R_MPU1_BASE) + #define R_MPU2 ((R_MPU0_Type *) R_MPU2_BASE) + #define R_MPU3 ((R_MPU3_Type *) R_MPU3_BASE) + #define R_MPU4 ((R_MPU3_Type *) R_MPU4_BASE) + #define R_MPU6 ((R_MPU0_Type *) R_MPU6_BASE) + #define R_SYSRAM_CTL ((R_SYSRAM_CTL_Type *) R_SYSRAM_CTL_BASE) + #define R_TCMAW ((R_TCMAW_Type *) R_TCMAW_BASE) + #define R_SHOSTIF_CFG ((R_SHOSTIF_CFG_Type *) R_SHOSTIF_CFG_BASE) + #define R_RWP_S ((R_RWP_S_Type *) R_RWP_S_BASE) + #define R_MPU7 ((R_MPU3_Type *) R_MPU7_BASE) + #define R_MTU ((R_MTU_Type *) R_MTU_BASE) + #define R_MTU3 ((R_MTU3_Type *) R_MTU3_BASE) + #define R_MTU4 ((R_MTU4_Type *) R_MTU4_BASE) + #define R_MTU_NF ((R_MTU_NF_Type *) R_MTU_NF_BASE) + #define R_MTU0 ((R_MTU0_Type *) R_MTU0_BASE) + #define R_MTU1 ((R_MTU1_Type *) R_MTU1_BASE) + #define R_MTU2 ((R_MTU2_Type *) R_MTU2_BASE) + #define R_MTU8 ((R_MTU8_Type *) R_MTU8_BASE) + #define R_MTU6 ((R_MTU6_Type *) R_MTU6_BASE) + #define R_MTU7 ((R_MTU7_Type *) R_MTU7_BASE) + #define R_MTU5 ((R_MTU5_Type *) R_MTU5_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_TFU ((R_TFU_Type *) R_TFU_BASE) + #define R_ADC120 ((R_ADC120_Type *) R_ADC120_BASE) + #define R_ADC121 ((R_ADC120_Type *) R_ADC121_BASE) + #define R_POE3 ((R_POE3_Type *) R_POE3_BASE) + #define R_POEG0 ((R_POEG0_Type *) R_POEG0_BASE) + #define R_DSMIF0 ((R_DSMIF0_Type *) R_DSMIF0_BASE) + #define R_DSMIF1 ((R_DSMIF0_Type *) R_DSMIF1_BASE) + #define R_HDSLD0 ((R_HDSLD0_Type *) R_HDSLD0_BASE) + #define R_HDSLS10 ((R_HDSLS10_Type *) R_HDSLS10_BASE) + #define R_BISS0 ((R_BISS0_Type *) R_BISS0_BASE) + #define R_ENDAT0 ((R_ENDAT0_Type *) R_ENDAT0_BASE) + #define R_AFMT0 ((R_AFMT0_Type *) R_AFMT0_BASE) + #define R_HDSLD1 ((R_HDSLD0_Type *) R_HDSLD1_BASE) + #define R_HDSLS11 ((R_HDSLS10_Type *) R_HDSLS11_BASE) + #define R_BISS1 ((R_BISS0_Type *) R_BISS1_BASE) + #define R_ENDAT1 ((R_ENDAT0_Type *) R_ENDAT1_BASE) + #define R_AFMT1 ((R_AFMT0_Type *) R_AFMT1_BASE) + #define R_ENCOUT ((R_ENCOUT_Type *) R_ENCOUT_BASE) + #define R_GSC ((R_GSC_Type *) R_GSC_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CFDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NCFG ========================================================== */ + #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ + #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ + #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ + #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ + #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ + #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ + #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ + #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ + #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ + #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ + #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ + #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ + #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ + #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ + #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ + #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ + #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ + #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ + #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ + #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ + #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ + #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ + #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ + #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ + #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ + #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ + #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ + #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ + #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ + #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ + #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ + #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ + #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ + #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ + #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ + #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ + #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ + #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ + #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ + #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ + #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ + #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ + #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ + #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ + #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ + #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ + #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ + #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDCFG_GWEN_Pos (24UL) /*!< GWEN (Bit 24) */ + #define R_CANFD_CFDC2_FDCFG_GWEN_Msk (0x1000000UL) /*!< GWEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos (25UL) /*!< GWFDF (Bit 25) */ + #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk (0x2000000UL) /*!< GWFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos (26UL) /*!< GWBRS (Bit 26) */ + #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk (0x4000000UL) /*!< GWBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos (31UL) /*!< CFDTE (Bit 31) */ + #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (25UL) /*!< SCNT (Bit 25) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0x1e000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ +/* ========================================================= BLCT ========================================================== */ + #define R_CANFD_CFDC2_BLCT_BLCE_Pos (0UL) /*!< BLCE (Bit 0) */ + #define R_CANFD_CFDC2_BLCT_BLCE_Msk (0x1UL) /*!< BLCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_BLCT_BLCLD_Pos (8UL) /*!< BLCLD (Bit 8) */ + #define R_CANFD_CFDC2_BLCT_BLCLD_Msk (0x100UL) /*!< BLCLD (Bitfield-Mask: 0x01) */ +/* ========================================================= BLSTS ========================================================= */ + #define R_CANFD_CFDC2_BLSTS_BLC_Pos (3UL) /*!< BLC (Bit 3) */ + #define R_CANFD_CFDC2_BLSTS_BLC_Msk (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos (4UL) /*!< GAFLSRD0 (Bit 4) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk (0x10UL) /*!< GAFLSRD0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos (5UL) /*!< GAFLSRD1 (Bit 5) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk (0x20UL) /*!< GAFLSRD1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos (6UL) /*!< GAFLSRD2 (Bit 6) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk (0x40UL) /*!< GAFLSRD2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x3fffUL) /*!< GAFLFDP (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFD_CFDRM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFD_CFDRM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFD_CFDRM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFD_CFDRM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFD_CFDRM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFD_CFDRM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DF_WD ========================================================= */ + #define R_CANFD_CFDRM_DF_WD_RMDB_LL_Pos (0UL) /*!< RMDB_LL (Bit 0) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_LL_Msk (0xffUL) /*!< RMDB_LL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_LH_Pos (8UL) /*!< RMDB_LH (Bit 8) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_LH_Msk (0xff00UL) /*!< RMDB_LH (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_HL_Pos (16UL) /*!< RMDB_HL (Bit 16) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_HL_Msk (0xff0000UL) /*!< RMDB_HL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_HH_Pos (24UL) /*!< RMDB_HH (Bit 24) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_HH_Msk (0xff000000UL) /*!< RMDB_HH (Bitfield-Mask: 0xff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFD_CFDRM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ + #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ + #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ + #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ + #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRF_FDSTS_CFDRFPTR_Pos (16UL) /*!< CFDRFPTR (Bit 16) */ + #define R_CANFD_CFDRF_FDSTS_CFDRFPTR_Msk (0xffff0000UL) /*!< CFDRFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ + #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ +/* ========================================================= DF_WD ========================================================= */ + #define R_CANFD_CFDRF_DF_WD_RFDB_LL_Pos (0UL) /*!< RFDB_LL (Bit 0) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_LL_Msk (0xffUL) /*!< RFDB_LL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_LH_Pos (8UL) /*!< RFDB_LH (Bit 8) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_LH_Msk (0xff00UL) /*!< RFDB_LH (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_HL_Pos (16UL) /*!< RFDB_HL (Bit 16) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_HL_Msk (0xff0000UL) /*!< RFDB_HL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_HH_Pos (24UL) /*!< RFDB_HH (Bit 24) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_HH_Msk (0xff000000UL) /*!< RFDB_HH (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ + #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ + #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ + #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ + #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ======================================================== FDCSTS ========================================================= */ + #define R_CANFD_CFDCF_FDCSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ + #define R_CANFD_CFDCF_FDCSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDCSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ + #define R_CANFD_CFDCF_FDCSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDCSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ + #define R_CANFD_CFDCF_FDCSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDCSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ + #define R_CANFD_CFDCF_FDCSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCF_FDCSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ + #define R_CANFD_CFDCF_FDCSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DF_WD ========================================================= */ + #define R_CANFD_CFDCF_DF_WD_CFDB_LL_Pos (0UL) /*!< CFDB_LL (Bit 0) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_LL_Msk (0xffUL) /*!< CFDB_LL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_LH_Pos (8UL) /*!< CFDB_LH (Bit 8) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_LH_Msk (0xff00UL) /*!< CFDB_LH (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_HL_Pos (16UL) /*!< CFDB_HL (Bit 16) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_HL_Msk (0xff0000UL) /*!< CFDB_HL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_HH_Pos (24UL) /*!< CFDB_HH (Bit 24) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_HH_Msk (0xff000000UL) /*!< CFDB_HH (Bitfield-Mask: 0xff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ + #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ + #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ + #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ + #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDTHL_ACC0_TGW_Pos (15UL) /*!< TGW (Bit 15) */ + #define R_CANFD_CFDTHL_ACC0_TGW_Msk (0x8000UL) /*!< TGW (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ + #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ + #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ + #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ + #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ + #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DF_WD ========================================================= */ + #define R_CANFD_CFDTM_DF_WD_TMDB_LL_Pos (0UL) /*!< TMDB_LL (Bit 0) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_LL_Msk (0xffUL) /*!< TMDB_LL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_LH_Pos (8UL) /*!< TMDB_LH (Bit 8) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_LH_Msk (0xff00UL) /*!< TMDB_LH (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_HL_Pos (16UL) /*!< TMDB_HL (Bit 16) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_HL_Msk (0xff0000UL) /*!< TMDB_HL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_HH_Pos (24UL) /*!< TMDB_HH (Bit 24) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_HH_Msk (0xff000000UL) /*!< TMDB_HH (Bitfield-Mask: 0xff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ + #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_CMT_UNT_CM_CR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_CMT_UNT_CM_CR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_CMT_UNT_CM_CR_CMIE_Pos (6UL) /*!< CMIE (Bit 6) */ + #define R_CMT_UNT_CM_CR_CMIE_Msk (0x40UL) /*!< CMIE (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +/* ========================================================== COR ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ UNT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMSTR0 ========================================================= */ + #define R_CMT_UNT_CMSTR0_STR0_Pos (0UL) /*!< STR0 (Bit 0) */ + #define R_CMT_UNT_CMSTR0_STR0_Msk (0x1UL) /*!< STR0 (Bitfield-Mask: 0x01) */ + #define R_CMT_UNT_CMSTR0_STR1_Pos (1UL) /*!< STR1 (Bit 1) */ + #define R_CMT_UNT_CMSTR0_STR1_Msk (0x2UL) /*!< STR1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA0_Pos (0UL) /*!< SVA0 (Bit 0) */ + #define R_IIC0_SAR_L_SVA0_Msk (0x1UL) /*!< SVA0 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_L_SVA_Pos (1UL) /*!< SVA (Bit 1) */ + #define R_IIC0_SAR_L_SVA_Msk (0xfeUL) /*!< SVA (Bitfield-Mask: 0x7f) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA_Pos (1UL) /*!< SVA (Bit 1) */ + #define R_IIC0_SAR_U_SVA_Msk (0x6UL) /*!< SVA (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ N ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SA =========================================================== */ +/* ========================================================== DA =========================================================== */ +/* ========================================================== TB =========================================================== */ + +/* =========================================================================================================================== */ +/* ================ CH ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CRSA ========================================================== */ +/* ========================================================= CRDA ========================================================== */ +/* ========================================================= CRTB ========================================================== */ +/* ======================================================== CHSTAT ========================================================= */ + #define R_DMAC0_GRP_CH_CHSTAT_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_DMAC0_GRP_CH_CHSTAT_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_RQST_Pos (1UL) /*!< RQST (Bit 1) */ + #define R_DMAC0_GRP_CH_CHSTAT_RQST_Msk (0x2UL) /*!< RQST (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_TACT_Pos (2UL) /*!< TACT (Bit 2) */ + #define R_DMAC0_GRP_CH_CHSTAT_TACT_Msk (0x4UL) /*!< TACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_SUS_Pos (3UL) /*!< SUS (Bit 3) */ + #define R_DMAC0_GRP_CH_CHSTAT_SUS_Msk (0x8UL) /*!< SUS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_ER_Pos (4UL) /*!< ER (Bit 4) */ + #define R_DMAC0_GRP_CH_CHSTAT_ER_Msk (0x10UL) /*!< ER (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_END_Pos (5UL) /*!< END (Bit 5) */ + #define R_DMAC0_GRP_CH_CHSTAT_END_Msk (0x20UL) /*!< END (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_TC_Pos (6UL) /*!< TC (Bit 6) */ + #define R_DMAC0_GRP_CH_CHSTAT_TC_Msk (0x40UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_SR_Pos (7UL) /*!< SR (Bit 7) */ + #define R_DMAC0_GRP_CH_CHSTAT_SR_Msk (0x80UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_DL_Pos (8UL) /*!< DL (Bit 8) */ + #define R_DMAC0_GRP_CH_CHSTAT_DL_Msk (0x100UL) /*!< DL (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_DW_Pos (9UL) /*!< DW (Bit 9) */ + #define R_DMAC0_GRP_CH_CHSTAT_DW_Msk (0x200UL) /*!< DW (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_DER_Pos (10UL) /*!< DER (Bit 10) */ + #define R_DMAC0_GRP_CH_CHSTAT_DER_Msk (0x400UL) /*!< DER (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_MODE_Pos (11UL) /*!< MODE (Bit 11) */ + #define R_DMAC0_GRP_CH_CHSTAT_MODE_Msk (0x800UL) /*!< MODE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_INTM_Pos (16UL) /*!< INTM (Bit 16) */ + #define R_DMAC0_GRP_CH_CHSTAT_INTM_Msk (0x10000UL) /*!< INTM (Bitfield-Mask: 0x01) */ +/* ======================================================== CHCTRL ========================================================= */ + #define R_DMAC0_GRP_CH_CHCTRL_SETEN_Pos (0UL) /*!< SETEN (Bit 0) */ + #define R_DMAC0_GRP_CH_CHCTRL_SETEN_Msk (0x1UL) /*!< SETEN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLREN_Pos (1UL) /*!< CLREN (Bit 1) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLREN_Msk (0x2UL) /*!< CLREN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_STG_Pos (2UL) /*!< STG (Bit 2) */ + #define R_DMAC0_GRP_CH_CHCTRL_STG_Msk (0x4UL) /*!< STG (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_SWRST_Pos (3UL) /*!< SWRST (Bit 3) */ + #define R_DMAC0_GRP_CH_CHCTRL_SWRST_Msk (0x8UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRRQ_Pos (4UL) /*!< CLRRQ (Bit 4) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRRQ_Msk (0x10UL) /*!< CLRRQ (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLREND_Pos (5UL) /*!< CLREND (Bit 5) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLREND_Msk (0x20UL) /*!< CLREND (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRTC_Pos (6UL) /*!< CLRTC (Bit 6) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRTC_Msk (0x40UL) /*!< CLRTC (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_SETSUS_Pos (8UL) /*!< SETSUS (Bit 8) */ + #define R_DMAC0_GRP_CH_CHCTRL_SETSUS_Msk (0x100UL) /*!< SETSUS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRSUS_Pos (9UL) /*!< CLRSUS (Bit 9) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRSUS_Msk (0x200UL) /*!< CLRSUS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_SETINTM_Pos (16UL) /*!< SETINTM (Bit 16) */ + #define R_DMAC0_GRP_CH_CHCTRL_SETINTM_Msk (0x10000UL) /*!< SETINTM (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRINTM_Pos (17UL) /*!< CLRINTM (Bit 17) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRINTM_Msk (0x20000UL) /*!< CLRINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= CHCFG ========================================================= */ + #define R_DMAC0_GRP_CH_CHCFG_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_DMAC0_GRP_CH_CHCFG_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ + #define R_DMAC0_GRP_CH_CHCFG_REQD_Pos (3UL) /*!< REQD (Bit 3) */ + #define R_DMAC0_GRP_CH_CHCFG_REQD_Msk (0x8UL) /*!< REQD (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_LOEN_Pos (4UL) /*!< LOEN (Bit 4) */ + #define R_DMAC0_GRP_CH_CHCFG_LOEN_Msk (0x10UL) /*!< LOEN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_HIEN_Pos (5UL) /*!< HIEN (Bit 5) */ + #define R_DMAC0_GRP_CH_CHCFG_HIEN_Msk (0x20UL) /*!< HIEN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_LVL_Pos (6UL) /*!< LVL (Bit 6) */ + #define R_DMAC0_GRP_CH_CHCFG_LVL_Msk (0x40UL) /*!< LVL (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_AM_Pos (8UL) /*!< AM (Bit 8) */ + #define R_DMAC0_GRP_CH_CHCFG_AM_Msk (0x700UL) /*!< AM (Bitfield-Mask: 0x07) */ + #define R_DMAC0_GRP_CH_CHCFG_SDS_Pos (12UL) /*!< SDS (Bit 12) */ + #define R_DMAC0_GRP_CH_CHCFG_SDS_Msk (0xf000UL) /*!< SDS (Bitfield-Mask: 0x0f) */ + #define R_DMAC0_GRP_CH_CHCFG_DDS_Pos (16UL) /*!< DDS (Bit 16) */ + #define R_DMAC0_GRP_CH_CHCFG_DDS_Msk (0xf0000UL) /*!< DDS (Bitfield-Mask: 0x0f) */ + #define R_DMAC0_GRP_CH_CHCFG_SAD_Pos (20UL) /*!< SAD (Bit 20) */ + #define R_DMAC0_GRP_CH_CHCFG_SAD_Msk (0x100000UL) /*!< SAD (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_DAD_Pos (21UL) /*!< DAD (Bit 21) */ + #define R_DMAC0_GRP_CH_CHCFG_DAD_Msk (0x200000UL) /*!< DAD (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_TM_Pos (22UL) /*!< TM (Bit 22) */ + #define R_DMAC0_GRP_CH_CHCFG_TM_Msk (0x400000UL) /*!< TM (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_DEM_Pos (24UL) /*!< DEM (Bit 24) */ + #define R_DMAC0_GRP_CH_CHCFG_DEM_Msk (0x1000000UL) /*!< DEM (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_TCM_Pos (25UL) /*!< TCM (Bit 25) */ + #define R_DMAC0_GRP_CH_CHCFG_TCM_Msk (0x2000000UL) /*!< TCM (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_SBE_Pos (27UL) /*!< SBE (Bit 27) */ + #define R_DMAC0_GRP_CH_CHCFG_SBE_Msk (0x8000000UL) /*!< SBE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_RSEL_Pos (28UL) /*!< RSEL (Bit 28) */ + #define R_DMAC0_GRP_CH_CHCFG_RSEL_Msk (0x10000000UL) /*!< RSEL (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_RSW_Pos (29UL) /*!< RSW (Bit 29) */ + #define R_DMAC0_GRP_CH_CHCFG_RSW_Msk (0x20000000UL) /*!< RSW (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_REN_Pos (30UL) /*!< REN (Bit 30) */ + #define R_DMAC0_GRP_CH_CHCFG_REN_Msk (0x40000000UL) /*!< REN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_DMS_Pos (31UL) /*!< DMS (Bit 31) */ + #define R_DMAC0_GRP_CH_CHCFG_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */ +/* ======================================================== CHITVL ========================================================= */ + #define R_DMAC0_GRP_CH_CHITVL_ITVL_Pos (0UL) /*!< ITVL (Bit 0) */ + #define R_DMAC0_GRP_CH_CHITVL_ITVL_Msk (0xffffUL) /*!< ITVL (Bitfield-Mask: 0xffff) */ +/* ========================================================= CHEXT ========================================================= */ + #define R_DMAC0_GRP_CH_CHEXT_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_DMAC0_GRP_CH_CHEXT_SPR_Msk (0x7UL) /*!< SPR (Bitfield-Mask: 0x07) */ + #define R_DMAC0_GRP_CH_CHEXT_SCA_Pos (4UL) /*!< SCA (Bit 4) */ + #define R_DMAC0_GRP_CH_CHEXT_SCA_Msk (0xf0UL) /*!< SCA (Bitfield-Mask: 0x0f) */ + #define R_DMAC0_GRP_CH_CHEXT_DPR_Pos (8UL) /*!< DPR (Bit 8) */ + #define R_DMAC0_GRP_CH_CHEXT_DPR_Msk (0x700UL) /*!< DPR (Bitfield-Mask: 0x07) */ + #define R_DMAC0_GRP_CH_CHEXT_DCA_Pos (12UL) /*!< DCA (Bit 12) */ + #define R_DMAC0_GRP_CH_CHEXT_DCA_Msk (0xf000UL) /*!< DCA (Bitfield-Mask: 0x0f) */ +/* ========================================================= NXLA ========================================================== */ +/* ========================================================= CRLA ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ GRP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCTRL ========================================================= */ + #define R_DMAC0_GRP_DCTRL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMAC0_GRP_DCTRL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DCTRL_LVINT_Pos (1UL) /*!< LVINT (Bit 1) */ + #define R_DMAC0_GRP_DCTRL_LVINT_Msk (0x2UL) /*!< LVINT (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_EN ======================================================== */ + #define R_DMAC0_GRP_DSTAT_EN_EN0008_Pos (0UL) /*!< EN0008 (Bit 0) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0008_Msk (0x1UL) /*!< EN0008 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0109_Pos (1UL) /*!< EN0109 (Bit 1) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0109_Msk (0x2UL) /*!< EN0109 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0210_Pos (2UL) /*!< EN0210 (Bit 2) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0210_Msk (0x4UL) /*!< EN0210 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0311_Pos (3UL) /*!< EN0311 (Bit 3) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0311_Msk (0x8UL) /*!< EN0311 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0412_Pos (4UL) /*!< EN0412 (Bit 4) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0412_Msk (0x10UL) /*!< EN0412 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0513_Pos (5UL) /*!< EN0513 (Bit 5) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0513_Msk (0x20UL) /*!< EN0513 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0614_Pos (6UL) /*!< EN0614 (Bit 6) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0614_Msk (0x40UL) /*!< EN0614 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0715_Pos (7UL) /*!< EN0715 (Bit 7) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0715_Msk (0x80UL) /*!< EN0715 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_ER ======================================================== */ + #define R_DMAC0_GRP_DSTAT_ER_ER0008_Pos (0UL) /*!< ER0008 (Bit 0) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0008_Msk (0x1UL) /*!< ER0008 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0109_Pos (1UL) /*!< ER0109 (Bit 1) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0109_Msk (0x2UL) /*!< ER0109 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0210_Pos (2UL) /*!< ER0210 (Bit 2) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0210_Msk (0x4UL) /*!< ER0210 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0311_Pos (3UL) /*!< ER0311 (Bit 3) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0311_Msk (0x8UL) /*!< ER0311 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0412_Pos (4UL) /*!< ER0412 (Bit 4) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0412_Msk (0x10UL) /*!< ER0412 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0513_Pos (5UL) /*!< ER0513 (Bit 5) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0513_Msk (0x20UL) /*!< ER0513 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0614_Pos (6UL) /*!< ER0614 (Bit 6) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0614_Msk (0x40UL) /*!< ER0614 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0715_Pos (7UL) /*!< ER0715 (Bit 7) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0715_Msk (0x80UL) /*!< ER0715 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_END ======================================================= */ + #define R_DMAC0_GRP_DSTAT_END_END0008_Pos (0UL) /*!< END0008 (Bit 0) */ + #define R_DMAC0_GRP_DSTAT_END_END0008_Msk (0x1UL) /*!< END0008 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END0109_Pos (1UL) /*!< END0109 (Bit 1) */ + #define R_DMAC0_GRP_DSTAT_END_END0109_Msk (0x2UL) /*!< END0109 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END0210_Pos (2UL) /*!< END0210 (Bit 2) */ + #define R_DMAC0_GRP_DSTAT_END_END0210_Msk (0x4UL) /*!< END0210 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END0311_Pos (3UL) /*!< END0311 (Bit 3) */ + #define R_DMAC0_GRP_DSTAT_END_END0311_Msk (0x8UL) /*!< END0311 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END0412_Pos (4UL) /*!< END0412 (Bit 4) */ + #define R_DMAC0_GRP_DSTAT_END_END0412_Msk (0x10UL) /*!< END0412 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END0513_Pos (5UL) /*!< END0513 (Bit 5) */ + #define R_DMAC0_GRP_DSTAT_END_END0513_Msk (0x20UL) /*!< END0513 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END0614_Pos (6UL) /*!< END0614 (Bit 6) */ + #define R_DMAC0_GRP_DSTAT_END_END0614_Msk (0x40UL) /*!< END0614 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END0715_Pos (7UL) /*!< END0715 (Bit 7) */ + #define R_DMAC0_GRP_DSTAT_END_END0715_Msk (0x80UL) /*!< END0715 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_SUS ======================================================= */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0008_Pos (0UL) /*!< SUS0008 (Bit 0) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0008_Msk (0x1UL) /*!< SUS0008 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0109_Pos (1UL) /*!< SUS0109 (Bit 1) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0109_Msk (0x2UL) /*!< SUS0109 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0210_Pos (2UL) /*!< SUS0210 (Bit 2) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0210_Msk (0x4UL) /*!< SUS0210 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0311_Pos (3UL) /*!< SUS0311 (Bit 3) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0311_Msk (0x8UL) /*!< SUS0311 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0412_Pos (4UL) /*!< SUS0412 (Bit 4) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0412_Msk (0x10UL) /*!< SUS0412 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0513_Pos (5UL) /*!< SUS0513 (Bit 5) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0513_Msk (0x20UL) /*!< SUS0513 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0614_Pos (6UL) /*!< SUS0614 (Bit 6) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0614_Msk (0x40UL) /*!< SUS0614 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0715_Pos (7UL) /*!< SUS0715 (Bit 7) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0715_Msk (0x80UL) /*!< SUS0715 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DRCTL ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_PORT_NSR_DRCTL_L_DRV0_Pos (0UL) /*!< DRV0 (Bit 0) */ + #define R_PORT_NSR_DRCTL_L_DRV0_Msk (0x3UL) /*!< DRV0 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_PUD0_Pos (2UL) /*!< PUD0 (Bit 2) */ + #define R_PORT_NSR_DRCTL_L_PUD0_Msk (0xcUL) /*!< PUD0 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_SMT0_Pos (4UL) /*!< SMT0 (Bit 4) */ + #define R_PORT_NSR_DRCTL_L_SMT0_Msk (0x10UL) /*!< SMT0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_SR0_Pos (5UL) /*!< SR0 (Bit 5) */ + #define R_PORT_NSR_DRCTL_L_SR0_Msk (0x20UL) /*!< SR0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_DRV1_Pos (8UL) /*!< DRV1 (Bit 8) */ + #define R_PORT_NSR_DRCTL_L_DRV1_Msk (0x300UL) /*!< DRV1 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_PUD1_Pos (10UL) /*!< PUD1 (Bit 10) */ + #define R_PORT_NSR_DRCTL_L_PUD1_Msk (0xc00UL) /*!< PUD1 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_SMT1_Pos (12UL) /*!< SMT1 (Bit 12) */ + #define R_PORT_NSR_DRCTL_L_SMT1_Msk (0x1000UL) /*!< SMT1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_SR1_Pos (13UL) /*!< SR1 (Bit 13) */ + #define R_PORT_NSR_DRCTL_L_SR1_Msk (0x2000UL) /*!< SR1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_DRV2_Pos (16UL) /*!< DRV2 (Bit 16) */ + #define R_PORT_NSR_DRCTL_L_DRV2_Msk (0x30000UL) /*!< DRV2 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_PUD2_Pos (18UL) /*!< PUD2 (Bit 18) */ + #define R_PORT_NSR_DRCTL_L_PUD2_Msk (0xc0000UL) /*!< PUD2 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_SMT2_Pos (20UL) /*!< SMT2 (Bit 20) */ + #define R_PORT_NSR_DRCTL_L_SMT2_Msk (0x100000UL) /*!< SMT2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_SR2_Pos (21UL) /*!< SR2 (Bit 21) */ + #define R_PORT_NSR_DRCTL_L_SR2_Msk (0x200000UL) /*!< SR2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_DRV3_Pos (24UL) /*!< DRV3 (Bit 24) */ + #define R_PORT_NSR_DRCTL_L_DRV3_Msk (0x3000000UL) /*!< DRV3 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_PUD3_Pos (26UL) /*!< PUD3 (Bit 26) */ + #define R_PORT_NSR_DRCTL_L_PUD3_Msk (0xc000000UL) /*!< PUD3 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_SMT3_Pos (28UL) /*!< SMT3 (Bit 28) */ + #define R_PORT_NSR_DRCTL_L_SMT3_Msk (0x10000000UL) /*!< SMT3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_SR3_Pos (29UL) /*!< SR3 (Bit 29) */ + #define R_PORT_NSR_DRCTL_L_SR3_Msk (0x20000000UL) /*!< SR3 (Bitfield-Mask: 0x01) */ +/* =========================================================== H =========================================================== */ + #define R_PORT_NSR_DRCTL_H_DRV4_Pos (0UL) /*!< DRV4 (Bit 0) */ + #define R_PORT_NSR_DRCTL_H_DRV4_Msk (0x3UL) /*!< DRV4 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_PUD4_Pos (2UL) /*!< PUD4 (Bit 2) */ + #define R_PORT_NSR_DRCTL_H_PUD4_Msk (0xcUL) /*!< PUD4 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_SMT4_Pos (4UL) /*!< SMT4 (Bit 4) */ + #define R_PORT_NSR_DRCTL_H_SMT4_Msk (0x10UL) /*!< SMT4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_SR4_Pos (5UL) /*!< SR4 (Bit 5) */ + #define R_PORT_NSR_DRCTL_H_SR4_Msk (0x20UL) /*!< SR4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_DRV5_Pos (8UL) /*!< DRV5 (Bit 8) */ + #define R_PORT_NSR_DRCTL_H_DRV5_Msk (0x300UL) /*!< DRV5 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_PUD5_Pos (10UL) /*!< PUD5 (Bit 10) */ + #define R_PORT_NSR_DRCTL_H_PUD5_Msk (0xc00UL) /*!< PUD5 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_SMT5_Pos (12UL) /*!< SMT5 (Bit 12) */ + #define R_PORT_NSR_DRCTL_H_SMT5_Msk (0x1000UL) /*!< SMT5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_SR5_Pos (13UL) /*!< SR5 (Bit 13) */ + #define R_PORT_NSR_DRCTL_H_SR5_Msk (0x2000UL) /*!< SR5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_DRV6_Pos (16UL) /*!< DRV6 (Bit 16) */ + #define R_PORT_NSR_DRCTL_H_DRV6_Msk (0x30000UL) /*!< DRV6 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_PUD6_Pos (18UL) /*!< PUD6 (Bit 18) */ + #define R_PORT_NSR_DRCTL_H_PUD6_Msk (0xc0000UL) /*!< PUD6 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_SMT6_Pos (20UL) /*!< SMT6 (Bit 20) */ + #define R_PORT_NSR_DRCTL_H_SMT6_Msk (0x100000UL) /*!< SMT6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_SR6_Pos (21UL) /*!< SR6 (Bit 21) */ + #define R_PORT_NSR_DRCTL_H_SR6_Msk (0x200000UL) /*!< SR6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_DRV7_Pos (24UL) /*!< DRV7 (Bit 24) */ + #define R_PORT_NSR_DRCTL_H_DRV7_Msk (0x3000000UL) /*!< DRV7 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_PUD7_Pos (26UL) /*!< PUD7 (Bit 26) */ + #define R_PORT_NSR_DRCTL_H_PUD7_Msk (0xc000000UL) /*!< PUD7 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_SMT7_Pos (28UL) /*!< SMT7 (Bit 28) */ + #define R_PORT_NSR_DRCTL_H_SMT7_Msk (0x10000000UL) /*!< SMT7 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_SR7_Pos (29UL) /*!< SR7 (Bit 29) */ + #define R_PORT_NSR_DRCTL_H_SR7_Msk (0x20000000UL) /*!< SR7 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELC_PDBF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_PORT_NSR_ELC_PDBF_BY_PB0_Pos (0UL) /*!< PB0 (Bit 0) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB0_Msk (0x1UL) /*!< PB0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB1_Pos (1UL) /*!< PB1 (Bit 1) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB1_Msk (0x2UL) /*!< PB1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB2_Pos (2UL) /*!< PB2 (Bit 2) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB2_Msk (0x4UL) /*!< PB2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB3_Pos (3UL) /*!< PB3 (Bit 3) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB3_Msk (0x8UL) /*!< PB3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB4_Pos (4UL) /*!< PB4 (Bit 4) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB4_Msk (0x10UL) /*!< PB4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB5_Pos (5UL) /*!< PB5 (Bit 5) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB5_Msk (0x20UL) /*!< PB5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB6_Pos (6UL) /*!< PB6 (Bit 6) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB6_Msk (0x40UL) /*!< PB6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB7_Pos (7UL) /*!< PB7 (Bit 7) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB7_Msk (0x80UL) /*!< PB7 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SWTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_GMAC_PTP_SWTM_EN_OUTEN_Pos (0UL) /*!< OUTEN (Bit 0) */ + #define R_GMAC_PTP_SWTM_EN_OUTEN_Msk (0x1UL) /*!< OUTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STSEC ========================================================= */ + #define R_GMAC_PTP_SWTM_STSEC_STSEC_Pos (0UL) /*!< STSEC (Bit 0) */ + #define R_GMAC_PTP_SWTM_STSEC_STSEC_Msk (0xffffffffUL) /*!< STSEC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STNS ========================================================== */ + #define R_GMAC_PTP_SWTM_STNS_STNS_Pos (0UL) /*!< STNS (Bit 0) */ + #define R_GMAC_PTP_SWTM_STNS_STNS_Msk (0xffffffffUL) /*!< STNS (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PSEC ========================================================== */ + #define R_GMAC_PTP_SWTM_PSEC_PSEC_Pos (0UL) /*!< PSEC (Bit 0) */ + #define R_GMAC_PTP_SWTM_PSEC_PSEC_Msk (0xffffffffUL) /*!< PSEC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== PNS ========================================================== */ + #define R_GMAC_PTP_SWTM_PNS_PNS_Pos (0UL) /*!< PNS (Bit 0) */ + #define R_GMAC_PTP_SWTM_PNS_PNS_Msk (0xffffffffUL) /*!< PNS (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== WTH ========================================================== */ + #define R_GMAC_PTP_SWTM_WTH_WIDTH_Pos (0UL) /*!< WIDTH (Bit 0) */ + #define R_GMAC_PTP_SWTM_WTH_WIDTH_Msk (0xffffUL) /*!< WIDTH (Bitfield-Mask: 0xffff) */ +/* ========================================================= MAXP ========================================================== */ + #define R_GMAC_PTP_SWTM_MAXP_MAXP_Pos (0UL) /*!< MAXP (Bit 0) */ + #define R_GMAC_PTP_SWTM_MAXP_MAXP_Msk (0xffffffffUL) /*!< MAXP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LATSEC ========================================================= */ + #define R_GMAC_PTP_SWTM_LATSEC_LATSEC_Pos (0UL) /*!< LATSEC (Bit 0) */ + #define R_GMAC_PTP_SWTM_LATSEC_LATSEC_Msk (0xffffffffUL) /*!< LATSEC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= LATNS ========================================================= */ + #define R_GMAC_PTP_SWTM_LATNS_LATNS_Pos (0UL) /*!< LATNS (Bit 0) */ + #define R_GMAC_PTP_SWTM_LATNS_LATNS_Msk (0xffffffffUL) /*!< LATNS (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ FMMU ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== L_START_ADR ====================================================== */ + #define R_ESC_FMMU_L_START_ADR_LSTAADR_Pos (0UL) /*!< LSTAADR (Bit 0) */ + #define R_ESC_FMMU_L_START_ADR_LSTAADR_Msk (0xffffffffUL) /*!< LSTAADR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== LEN ========================================================== */ + #define R_ESC_FMMU_LEN_FMMULEN_Pos (0UL) /*!< FMMULEN (Bit 0) */ + #define R_ESC_FMMU_LEN_FMMULEN_Msk (0xffffUL) /*!< FMMULEN (Bitfield-Mask: 0xffff) */ +/* ====================================================== L_START_BIT ====================================================== */ + #define R_ESC_FMMU_L_START_BIT_LSTABIT_Pos (0UL) /*!< LSTABIT (Bit 0) */ + #define R_ESC_FMMU_L_START_BIT_LSTABIT_Msk (0x7UL) /*!< LSTABIT (Bitfield-Mask: 0x07) */ +/* ====================================================== L_STOP_BIT ======================================================= */ + #define R_ESC_FMMU_L_STOP_BIT_LSTPBIT_Pos (0UL) /*!< LSTPBIT (Bit 0) */ + #define R_ESC_FMMU_L_STOP_BIT_LSTPBIT_Msk (0x7UL) /*!< LSTPBIT (Bitfield-Mask: 0x07) */ +/* ====================================================== P_START_ADR ====================================================== */ + #define R_ESC_FMMU_P_START_ADR_PHYSTAADR_Pos (0UL) /*!< PHYSTAADR (Bit 0) */ + #define R_ESC_FMMU_P_START_ADR_PHYSTAADR_Msk (0xffffUL) /*!< PHYSTAADR (Bitfield-Mask: 0xffff) */ +/* ====================================================== P_START_BIT ====================================================== */ + #define R_ESC_FMMU_P_START_BIT_PHYSTABIT_Pos (0UL) /*!< PHYSTABIT (Bit 0) */ + #define R_ESC_FMMU_P_START_BIT_PHYSTABIT_Msk (0x7UL) /*!< PHYSTABIT (Bitfield-Mask: 0x07) */ +/* ========================================================= TYPE ========================================================== */ + #define R_ESC_FMMU_TYPE_READ_Pos (0UL) /*!< READ (Bit 0) */ + #define R_ESC_FMMU_TYPE_READ_Msk (0x1UL) /*!< READ (Bitfield-Mask: 0x01) */ + #define R_ESC_FMMU_TYPE_WRITE_Pos (1UL) /*!< WRITE (Bit 1) */ + #define R_ESC_FMMU_TYPE_WRITE_Msk (0x2UL) /*!< WRITE (Bitfield-Mask: 0x01) */ +/* ========================================================== ACT ========================================================== */ + #define R_ESC_FMMU_ACT_ACTIVATE_Pos (0UL) /*!< ACTIVATE (Bit 0) */ + #define R_ESC_FMMU_ACT_ACTIVATE_Msk (0x1UL) /*!< ACTIVATE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SM ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== P_START_ADR ====================================================== */ + #define R_ESC_SM_P_START_ADR_SMSTAADDR_Pos (0UL) /*!< SMSTAADDR (Bit 0) */ + #define R_ESC_SM_P_START_ADR_SMSTAADDR_Msk (0xffffUL) /*!< SMSTAADDR (Bitfield-Mask: 0xffff) */ +/* ========================================================== LEN ========================================================== */ + #define R_ESC_SM_LEN_SMLEN_Pos (0UL) /*!< SMLEN (Bit 0) */ + #define R_ESC_SM_LEN_SMLEN_Msk (0xffffUL) /*!< SMLEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== CONTROL ======================================================== */ + #define R_ESC_SM_CONTROL_OPEMODE_Pos (0UL) /*!< OPEMODE (Bit 0) */ + #define R_ESC_SM_CONTROL_OPEMODE_Msk (0x3UL) /*!< OPEMODE (Bitfield-Mask: 0x03) */ + #define R_ESC_SM_CONTROL_DIR_Pos (2UL) /*!< DIR (Bit 2) */ + #define R_ESC_SM_CONTROL_DIR_Msk (0xcUL) /*!< DIR (Bitfield-Mask: 0x03) */ + #define R_ESC_SM_CONTROL_IRQECAT_Pos (4UL) /*!< IRQECAT (Bit 4) */ + #define R_ESC_SM_CONTROL_IRQECAT_Msk (0x10UL) /*!< IRQECAT (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_CONTROL_IRQPDI_Pos (5UL) /*!< IRQPDI (Bit 5) */ + #define R_ESC_SM_CONTROL_IRQPDI_Msk (0x20UL) /*!< IRQPDI (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_CONTROL_WDTRGEN_Pos (6UL) /*!< WDTRGEN (Bit 6) */ + #define R_ESC_SM_CONTROL_WDTRGEN_Msk (0x40UL) /*!< WDTRGEN (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ + #define R_ESC_SM_STATUS_INTWR_Pos (0UL) /*!< INTWR (Bit 0) */ + #define R_ESC_SM_STATUS_INTWR_Msk (0x1UL) /*!< INTWR (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_STATUS_INTRD_Pos (1UL) /*!< INTRD (Bit 1) */ + #define R_ESC_SM_STATUS_INTRD_Msk (0x2UL) /*!< INTRD (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_STATUS_MAILBOX_Pos (3UL) /*!< MAILBOX (Bit 3) */ + #define R_ESC_SM_STATUS_MAILBOX_Msk (0x8UL) /*!< MAILBOX (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_STATUS_BUFFERED_Pos (4UL) /*!< BUFFERED (Bit 4) */ + #define R_ESC_SM_STATUS_BUFFERED_Msk (0x30UL) /*!< BUFFERED (Bitfield-Mask: 0x03) */ + #define R_ESC_SM_STATUS_RDBUF_Pos (6UL) /*!< RDBUF (Bit 6) */ + #define R_ESC_SM_STATUS_RDBUF_Msk (0x40UL) /*!< RDBUF (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_STATUS_WRBUF_Pos (7UL) /*!< WRBUF (Bit 7) */ + #define R_ESC_SM_STATUS_WRBUF_Msk (0x80UL) /*!< WRBUF (Bitfield-Mask: 0x01) */ +/* ========================================================== ACT ========================================================== */ + #define R_ESC_SM_ACT_SMEN_Pos (0UL) /*!< SMEN (Bit 0) */ + #define R_ESC_SM_ACT_SMEN_Msk (0x1UL) /*!< SMEN (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_ACT_REPEATREQ_Pos (1UL) /*!< REPEATREQ (Bit 1) */ + #define R_ESC_SM_ACT_REPEATREQ_Msk (0x2UL) /*!< REPEATREQ (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_ACT_LATCHECAT_Pos (6UL) /*!< LATCHECAT (Bit 6) */ + #define R_ESC_SM_ACT_LATCHECAT_Msk (0x40UL) /*!< LATCHECAT (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_ACT_LATCHPDI_Pos (7UL) /*!< LATCHPDI (Bit 7) */ + #define R_ESC_SM_ACT_LATCHPDI_Msk (0x80UL) /*!< LATCHPDI (Bitfield-Mask: 0x01) */ +/* ======================================================= PDI_CONT ======================================================== */ + #define R_ESC_SM_PDI_CONT_DEACTIVE_Pos (0UL) /*!< DEACTIVE (Bit 0) */ + #define R_ESC_SM_PDI_CONT_DEACTIVE_Msk (0x1UL) /*!< DEACTIVE (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_PDI_CONT_REPEATACK_Pos (1UL) /*!< REPEATACK (Bit 1) */ + #define R_ESC_SM_PDI_CONT_REPEATACK_Msk (0x2UL) /*!< REPEATACK (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USBF_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USBF_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USBF_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USBF_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USBF_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ N ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SA =========================================================== */ + #define R_USBF_CHa_N_SA_SAWD_Pos (0UL) /*!< SAWD (Bit 0) */ + #define R_USBF_CHa_N_SA_SAWD_Msk (0xffffffffUL) /*!< SAWD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== DA =========================================================== */ + #define R_USBF_CHa_N_DA_DA_Pos (0UL) /*!< DA (Bit 0) */ + #define R_USBF_CHa_N_DA_DA_Msk (0xffffffffUL) /*!< DA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== TB =========================================================== */ + #define R_USBF_CHa_N_TB_TB_Pos (0UL) /*!< TB (Bit 0) */ + #define R_USBF_CHa_N_TB_TB_Msk (0xffffffffUL) /*!< TB (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CHa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CRSA ========================================================== */ + #define R_USBF_CHa_CRSA_CRSA_Pos (0UL) /*!< CRSA (Bit 0) */ + #define R_USBF_CHa_CRSA_CRSA_Msk (0xffffffffUL) /*!< CRSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CRDA ========================================================== */ + #define R_USBF_CHa_CRDA_CRDA_Pos (0UL) /*!< CRDA (Bit 0) */ + #define R_USBF_CHa_CRDA_CRDA_Msk (0xffffffffUL) /*!< CRDA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CRTB ========================================================== */ + #define R_USBF_CHa_CRTB_CRTB_Pos (0UL) /*!< CRTB (Bit 0) */ + #define R_USBF_CHa_CRTB_CRTB_Msk (0xffffffffUL) /*!< CRTB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CHSTAT ========================================================= */ + #define R_USBF_CHa_CHSTAT_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_USBF_CHa_CHSTAT_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_RQST_Pos (1UL) /*!< RQST (Bit 1) */ + #define R_USBF_CHa_CHSTAT_RQST_Msk (0x2UL) /*!< RQST (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_TACT_Pos (2UL) /*!< TACT (Bit 2) */ + #define R_USBF_CHa_CHSTAT_TACT_Msk (0x4UL) /*!< TACT (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_SUS_Pos (3UL) /*!< SUS (Bit 3) */ + #define R_USBF_CHa_CHSTAT_SUS_Msk (0x8UL) /*!< SUS (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_ER_Pos (4UL) /*!< ER (Bit 4) */ + #define R_USBF_CHa_CHSTAT_ER_Msk (0x10UL) /*!< ER (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_END_Pos (5UL) /*!< END (Bit 5) */ + #define R_USBF_CHa_CHSTAT_END_Msk (0x20UL) /*!< END (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_TC_Pos (6UL) /*!< TC (Bit 6) */ + #define R_USBF_CHa_CHSTAT_TC_Msk (0x40UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_SR_Pos (7UL) /*!< SR (Bit 7) */ + #define R_USBF_CHa_CHSTAT_SR_Msk (0x80UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_DL_Pos (8UL) /*!< DL (Bit 8) */ + #define R_USBF_CHa_CHSTAT_DL_Msk (0x100UL) /*!< DL (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_DW_Pos (9UL) /*!< DW (Bit 9) */ + #define R_USBF_CHa_CHSTAT_DW_Msk (0x200UL) /*!< DW (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_DER_Pos (10UL) /*!< DER (Bit 10) */ + #define R_USBF_CHa_CHSTAT_DER_Msk (0x400UL) /*!< DER (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_MODE_Pos (11UL) /*!< MODE (Bit 11) */ + #define R_USBF_CHa_CHSTAT_MODE_Msk (0x800UL) /*!< MODE (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_INTM_Pos (16UL) /*!< INTM (Bit 16) */ + #define R_USBF_CHa_CHSTAT_INTM_Msk (0x10000UL) /*!< INTM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_DMARQM_Pos (17UL) /*!< DMARQM (Bit 17) */ + #define R_USBF_CHa_CHSTAT_DMARQM_Msk (0x20000UL) /*!< DMARQM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_SWPRQ_Pos (18UL) /*!< SWPRQ (Bit 18) */ + #define R_USBF_CHa_CHSTAT_SWPRQ_Msk (0x40000UL) /*!< SWPRQ (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_DNUM_Pos (24UL) /*!< DNUM (Bit 24) */ + #define R_USBF_CHa_CHSTAT_DNUM_Msk (0xff000000UL) /*!< DNUM (Bitfield-Mask: 0xff) */ +/* ======================================================== CHCTRL ========================================================= */ + #define R_USBF_CHa_CHCTRL_SETEN_Pos (0UL) /*!< SETEN (Bit 0) */ + #define R_USBF_CHa_CHCTRL_SETEN_Msk (0x1UL) /*!< SETEN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLREN_Pos (1UL) /*!< CLREN (Bit 1) */ + #define R_USBF_CHa_CHCTRL_CLREN_Msk (0x2UL) /*!< CLREN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_STG_Pos (2UL) /*!< STG (Bit 2) */ + #define R_USBF_CHa_CHCTRL_STG_Msk (0x4UL) /*!< STG (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SWRST_Pos (3UL) /*!< SWRST (Bit 3) */ + #define R_USBF_CHa_CHCTRL_SWRST_Msk (0x8UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRRQ_Pos (4UL) /*!< CLRRQ (Bit 4) */ + #define R_USBF_CHa_CHCTRL_CLRRQ_Msk (0x10UL) /*!< CLRRQ (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLREND_Pos (5UL) /*!< CLREND (Bit 5) */ + #define R_USBF_CHa_CHCTRL_CLREND_Msk (0x20UL) /*!< CLREND (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRTC_Pos (6UL) /*!< CLRTC (Bit 6) */ + #define R_USBF_CHa_CHCTRL_CLRTC_Msk (0x40UL) /*!< CLRTC (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRDER_Pos (7UL) /*!< CLRDER (Bit 7) */ + #define R_USBF_CHa_CHCTRL_CLRDER_Msk (0x80UL) /*!< CLRDER (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SETSUS_Pos (8UL) /*!< SETSUS (Bit 8) */ + #define R_USBF_CHa_CHCTRL_SETSUS_Msk (0x100UL) /*!< SETSUS (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRSUS_Pos (9UL) /*!< CLRSUS (Bit 9) */ + #define R_USBF_CHa_CHCTRL_CLRSUS_Msk (0x200UL) /*!< CLRSUS (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SETREN_Pos (12UL) /*!< SETREN (Bit 12) */ + #define R_USBF_CHa_CHCTRL_SETREN_Msk (0x1000UL) /*!< SETREN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SETSSWPRQ_Pos (14UL) /*!< SETSSWPRQ (Bit 14) */ + #define R_USBF_CHa_CHCTRL_SETSSWPRQ_Msk (0x4000UL) /*!< SETSSWPRQ (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SETINTM_Pos (16UL) /*!< SETINTM (Bit 16) */ + #define R_USBF_CHa_CHCTRL_SETINTM_Msk (0x10000UL) /*!< SETINTM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRINTM_Pos (17UL) /*!< CLRINTM (Bit 17) */ + #define R_USBF_CHa_CHCTRL_CLRINTM_Msk (0x20000UL) /*!< CLRINTM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SETDMARQM_Pos (18UL) /*!< SETDMARQM (Bit 18) */ + #define R_USBF_CHa_CHCTRL_SETDMARQM_Msk (0x40000UL) /*!< SETDMARQM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRDMARQM_Pos (19UL) /*!< CLRDMARQM (Bit 19) */ + #define R_USBF_CHa_CHCTRL_CLRDMARQM_Msk (0x80000UL) /*!< CLRDMARQM (Bitfield-Mask: 0x01) */ +/* ========================================================= CHCFG ========================================================= */ + #define R_USBF_CHa_CHCFG_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_USBF_CHa_CHCFG_SEL_Msk (0x1UL) /*!< SEL (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_REQD_Pos (3UL) /*!< REQD (Bit 3) */ + #define R_USBF_CHa_CHCFG_REQD_Msk (0x8UL) /*!< REQD (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_LOEN_Pos (4UL) /*!< LOEN (Bit 4) */ + #define R_USBF_CHa_CHCFG_LOEN_Msk (0x10UL) /*!< LOEN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_HIEN_Pos (5UL) /*!< HIEN (Bit 5) */ + #define R_USBF_CHa_CHCFG_HIEN_Msk (0x20UL) /*!< HIEN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_LVL_Pos (6UL) /*!< LVL (Bit 6) */ + #define R_USBF_CHa_CHCFG_LVL_Msk (0x40UL) /*!< LVL (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_AM_Pos (8UL) /*!< AM (Bit 8) */ + #define R_USBF_CHa_CHCFG_AM_Msk (0x700UL) /*!< AM (Bitfield-Mask: 0x07) */ + #define R_USBF_CHa_CHCFG_DRRP_Pos (11UL) /*!< DRRP (Bit 11) */ + #define R_USBF_CHa_CHCFG_DRRP_Msk (0x800UL) /*!< DRRP (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_SDS_Pos (12UL) /*!< SDS (Bit 12) */ + #define R_USBF_CHa_CHCFG_SDS_Msk (0xf000UL) /*!< SDS (Bitfield-Mask: 0x0f) */ + #define R_USBF_CHa_CHCFG_DDS_Pos (16UL) /*!< DDS (Bit 16) */ + #define R_USBF_CHa_CHCFG_DDS_Msk (0xf0000UL) /*!< DDS (Bitfield-Mask: 0x0f) */ + #define R_USBF_CHa_CHCFG_SAD_Pos (20UL) /*!< SAD (Bit 20) */ + #define R_USBF_CHa_CHCFG_SAD_Msk (0x100000UL) /*!< SAD (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_DAD_Pos (21UL) /*!< DAD (Bit 21) */ + #define R_USBF_CHa_CHCFG_DAD_Msk (0x200000UL) /*!< DAD (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_TM_Pos (22UL) /*!< TM (Bit 22) */ + #define R_USBF_CHa_CHCFG_TM_Msk (0x400000UL) /*!< TM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_WONLY_Pos (23UL) /*!< WONLY (Bit 23) */ + #define R_USBF_CHa_CHCFG_WONLY_Msk (0x800000UL) /*!< WONLY (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_DEM_Pos (24UL) /*!< DEM (Bit 24) */ + #define R_USBF_CHa_CHCFG_DEM_Msk (0x1000000UL) /*!< DEM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_DIM_Pos (26UL) /*!< DIM (Bit 26) */ + #define R_USBF_CHa_CHCFG_DIM_Msk (0x4000000UL) /*!< DIM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_SBE_Pos (27UL) /*!< SBE (Bit 27) */ + #define R_USBF_CHa_CHCFG_SBE_Msk (0x8000000UL) /*!< SBE (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_RSEL_Pos (28UL) /*!< RSEL (Bit 28) */ + #define R_USBF_CHa_CHCFG_RSEL_Msk (0x10000000UL) /*!< RSEL (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_RSW_Pos (29UL) /*!< RSW (Bit 29) */ + #define R_USBF_CHa_CHCFG_RSW_Msk (0x20000000UL) /*!< RSW (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_REN_Pos (30UL) /*!< REN (Bit 30) */ + #define R_USBF_CHa_CHCFG_REN_Msk (0x40000000UL) /*!< REN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_DMS_Pos (31UL) /*!< DMS (Bit 31) */ + #define R_USBF_CHa_CHCFG_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */ +/* ======================================================== CHITVL ========================================================= */ + #define R_USBF_CHa_CHITVL_ITVL_Pos (0UL) /*!< ITVL (Bit 0) */ + #define R_USBF_CHa_CHITVL_ITVL_Msk (0xffffUL) /*!< ITVL (Bitfield-Mask: 0xffff) */ +/* ========================================================= CHEXT ========================================================= */ + #define R_USBF_CHa_CHEXT_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_USBF_CHa_CHEXT_SPR_Msk (0xfUL) /*!< SPR (Bitfield-Mask: 0x0f) */ + #define R_USBF_CHa_CHEXT_DPR_Pos (8UL) /*!< DPR (Bit 8) */ + #define R_USBF_CHa_CHEXT_DPR_Msk (0xf00UL) /*!< DPR (Bitfield-Mask: 0x0f) */ +/* ========================================================= NXLA ========================================================== */ + #define R_USBF_CHa_NXLA_NXLA_Pos (0UL) /*!< NXLA (Bit 0) */ + #define R_USBF_CHa_NXLA_NXLA_Msk (0xffffffffUL) /*!< NXLA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CRLA ========================================================== */ + #define R_USBF_CHa_CRLA_CRLA_Pos (0UL) /*!< CRLA (Bit 0) */ + #define R_USBF_CHa_CRLA_CRLA_Msk (0xffffffffUL) /*!< CRLA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CHb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SCNT ========================================================== */ + #define R_USBF_CHb_SCNT_SCNT_Pos (0UL) /*!< SCNT (Bit 0) */ + #define R_USBF_CHb_SCNT_SCNT_Msk (0xffffffffUL) /*!< SCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SSKP ========================================================== */ + #define R_USBF_CHb_SSKP_SSKP_Pos (0UL) /*!< SSKP (Bit 0) */ + #define R_USBF_CHb_SSKP_SSKP_Msk (0xffffffffUL) /*!< SSKP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DCNT ========================================================== */ + #define R_USBF_CHb_DCNT_DCNT_Pos (0UL) /*!< DCNT (Bit 0) */ + #define R_USBF_CHb_DCNT_DCNT_Msk (0xffffffffUL) /*!< DCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DSKP ========================================================== */ + #define R_USBF_CHb_DSKP_DSKP_Pos (0UL) /*!< DSKP (Bit 0) */ + #define R_USBF_CHb_DSKP_DSKP_Msk (0xffffffffUL) /*!< DSKP (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMCFG0 ========================================================= */ + #define R_XSPI0_CSa_CMCFG0_FFMT_Pos (0UL) /*!< FFMT (Bit 0) */ + #define R_XSPI0_CSa_CMCFG0_FFMT_Msk (0x3UL) /*!< FFMT (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CSa_CMCFG0_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_CSa_CMCFG0_ADDSIZE_Msk (0xcUL) /*!< ADDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CSa_CMCFG0_ADDRPEN_Pos (16UL) /*!< ADDRPEN (Bit 16) */ + #define R_XSPI0_CSa_CMCFG0_ADDRPEN_Msk (0xff0000UL) /*!< ADDRPEN (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CSa_CMCFG0_ADDRPCD_Pos (24UL) /*!< ADDRPCD (Bit 24) */ + #define R_XSPI0_CSa_CMCFG0_ADDRPCD_Msk (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff) */ +/* ======================================================== CMCFG1 ========================================================= */ + #define R_XSPI0_CSa_CMCFG1_RDCMD_Pos (0UL) /*!< RDCMD (Bit 0) */ + #define R_XSPI0_CSa_CMCFG1_RDCMD_Msk (0xffffUL) /*!< RDCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CSa_CMCFG1_RDLATE_Pos (16UL) /*!< RDLATE (Bit 16) */ + #define R_XSPI0_CSa_CMCFG1_RDLATE_Msk (0x1f0000UL) /*!< RDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CMCFG2 ========================================================= */ + #define R_XSPI0_CSa_CMCFG2_WRCMD_Pos (0UL) /*!< WRCMD (Bit 0) */ + #define R_XSPI0_CSa_CMCFG2_WRCMD_Msk (0xffffUL) /*!< WRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CSa_CMCFG2_WRLATE_Pos (16UL) /*!< WRLATE (Bit 16) */ + #define R_XSPI0_CSa_CMCFG2_WRLATE_Msk (0x1f0000UL) /*!< WRLATE (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ BUF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CDT ========================================================== */ + #define R_XSPI0_BUF_CDT_CMDSIZE_Pos (0UL) /*!< CMDSIZE (Bit 0) */ + #define R_XSPI0_BUF_CDT_CMDSIZE_Msk (0x3UL) /*!< CMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BUF_CDT_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_BUF_CDT_ADDSIZE_Msk (0x1cUL) /*!< ADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_BUF_CDT_DATASIZE_Pos (5UL) /*!< DATASIZE (Bit 5) */ + #define R_XSPI0_BUF_CDT_DATASIZE_Msk (0x1e0UL) /*!< DATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_BUF_CDT_LATE_Pos (9UL) /*!< LATE (Bit 9) */ + #define R_XSPI0_BUF_CDT_LATE_Msk (0x3e00UL) /*!< LATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_BUF_CDT_TRTYPE_Pos (15UL) /*!< TRTYPE (Bit 15) */ + #define R_XSPI0_BUF_CDT_TRTYPE_Msk (0x8000UL) /*!< TRTYPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BUF_CDT_CMD_Pos (16UL) /*!< CMD (Bit 16) */ + #define R_XSPI0_BUF_CDT_CMD_Msk (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff) */ +/* ========================================================== CDA ========================================================== */ + #define R_XSPI0_BUF_CDA_ADD_Pos (0UL) /*!< ADD (Bit 0) */ + #define R_XSPI0_BUF_CDA_ADD_Msk (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD0 ========================================================== */ + #define R_XSPI0_BUF_CDD0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_BUF_CDD0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD1 ========================================================== */ + #define R_XSPI0_BUF_CDD1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_BUF_CDD1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCCTL0 ========================================================= */ + #define R_XSPI0_CSb_CCCTL0_CAEN_Pos (0UL) /*!< CAEN (Bit 0) */ + #define R_XSPI0_CSb_CCCTL0_CAEN_Msk (0x1UL) /*!< CAEN (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CSb_CCCTL0_CANOWR_Pos (1UL) /*!< CANOWR (Bit 1) */ + #define R_XSPI0_CSb_CCCTL0_CANOWR_Msk (0x2UL) /*!< CANOWR (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CSb_CCCTL0_CAITV_Pos (8UL) /*!< CAITV (Bit 8) */ + #define R_XSPI0_CSb_CCCTL0_CAITV_Msk (0x1f00UL) /*!< CAITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CSb_CCCTL0_CASFTSTA_Pos (16UL) /*!< CASFTSTA (Bit 16) */ + #define R_XSPI0_CSb_CCCTL0_CASFTSTA_Msk (0x1f0000UL) /*!< CASFTSTA (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CSb_CCCTL0_CASFTEND_Pos (24UL) /*!< CASFTEND (Bit 24) */ + #define R_XSPI0_CSb_CCCTL0_CASFTEND_Msk (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL1 ========================================================= */ + #define R_XSPI0_CSb_CCCTL1_CACMDSIZE_Pos (0UL) /*!< CACMDSIZE (Bit 0) */ + #define R_XSPI0_CSb_CCCTL1_CACMDSIZE_Msk (0x3UL) /*!< CACMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CSb_CCCTL1_CAADDSIZE_Pos (2UL) /*!< CAADDSIZE (Bit 2) */ + #define R_XSPI0_CSb_CCCTL1_CAADDSIZE_Msk (0x1cUL) /*!< CAADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_CSb_CCCTL1_CADATASIZE_Pos (5UL) /*!< CADATASIZE (Bit 5) */ + #define R_XSPI0_CSb_CCCTL1_CADATASIZE_Msk (0x1e0UL) /*!< CADATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_CSb_CCCTL1_CAWRLATE_Pos (16UL) /*!< CAWRLATE (Bit 16) */ + #define R_XSPI0_CSb_CCCTL1_CAWRLATE_Msk (0x1f0000UL) /*!< CAWRLATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CSb_CCCTL1_CARDLATE_Pos (24UL) /*!< CARDLATE (Bit 24) */ + #define R_XSPI0_CSb_CCCTL1_CARDLATE_Msk (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL2 ========================================================= */ + #define R_XSPI0_CSb_CCCTL2_CAWRCMD_Pos (0UL) /*!< CAWRCMD (Bit 0) */ + #define R_XSPI0_CSb_CCCTL2_CAWRCMD_Msk (0xffffUL) /*!< CAWRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CSb_CCCTL2_CARDCMD_Pos (16UL) /*!< CARDCMD (Bit 16) */ + #define R_XSPI0_CSb_CCCTL2_CARDCMD_Msk (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff) */ +/* ======================================================== CCCTL3 ========================================================= */ + #define R_XSPI0_CSb_CCCTL3_CAADD_Pos (0UL) /*!< CAADD (Bit 0) */ + #define R_XSPI0_CSb_CCCTL3_CAADD_Msk (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL4 ========================================================= */ + #define R_XSPI0_CSb_CCCTL4_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CSb_CCCTL4_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL5 ========================================================= */ + #define R_XSPI0_CSb_CCCTL5_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CSb_CCCTL5_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL6 ========================================================= */ + #define R_XSPI0_CSb_CCCTL6_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CSb_CCCTL6_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL7 ========================================================= */ + #define R_XSPI0_CSb_CCCTL7_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CSb_CCCTL7_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ W ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_SYSRAM0_W_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_SYSRAM0_W_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_SYSRAM0_W_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_SYSRAM0_W_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_SYSRAM0_W_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_SYSRAM0_W_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_SYSRAM0_W_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_SYSRAM0_W_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECTHM_Pos (7UL) /*!< ECTHM (Bit 7) */ + #define R_SYSRAM0_W_EC710CTL_ECTHM_Msk (0x80UL) /*!< ECTHM (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_SYSRAM0_W_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_SYSRAM0_W_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_SYSRAM0_W_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_SYSRAM0_W_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF0_Pos (16UL) /*!< ECEDF0 (Bit 16) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF0_Msk (0x30000UL) /*!< ECEDF0 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF1_Pos (18UL) /*!< ECEDF1 (Bit 18) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF1_Msk (0xc0000UL) /*!< ECEDF1 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF2_Pos (20UL) /*!< ECEDF2 (Bit 20) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF2_Msk (0x300000UL) /*!< ECEDF2 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF3_Pos (22UL) /*!< ECEDF3 (Bit 22) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF3_Msk (0xc00000UL) /*!< ECEDF3 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF4_Pos (24UL) /*!< ECEDF4 (Bit 24) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF4_Msk (0x3000000UL) /*!< ECEDF4 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF5_Pos (26UL) /*!< ECEDF5 (Bit 26) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF5_Msk (0xc000000UL) /*!< ECEDF5 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF6_Pos (28UL) /*!< ECEDF6 (Bit 28) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF6_Msk (0x30000000UL) /*!< ECEDF6 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF7_Pos (30UL) /*!< ECEDF7 (Bit 30) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF7_Msk (0xc0000000UL) /*!< ECEDF7 (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_SYSRAM0_W_EC710TMC_ECREIS_Pos (0UL) /*!< ECREIS (Bit 0) */ + #define R_SYSRAM0_W_EC710TMC_ECREIS_Msk (0x1UL) /*!< ECREIS (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_SYSRAM0_W_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ECENS_Pos (2UL) /*!< ECENS (Bit 2) */ + #define R_SYSRAM0_W_EC710TMC_ECENS_Msk (0x4UL) /*!< ECENS (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ECREOS_Pos (3UL) /*!< ECREOS (Bit 3) */ + #define R_SYSRAM0_W_EC710TMC_ECREOS_Msk (0x8UL) /*!< ECREOS (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ECTRRS_Pos (4UL) /*!< ECTRRS (Bit 4) */ + #define R_SYSRAM0_W_EC710TMC_ECTRRS_Msk (0x10UL) /*!< ECTRRS (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_SYSRAM0_W_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_SYSRAM0_W_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TRC ======================================================== */ + #define R_SYSRAM0_W_EC710TRC_ECERDB_Pos (0UL) /*!< ECERDB (Bit 0) */ + #define R_SYSRAM0_W_EC710TRC_ECERDB_Msk (0x7fUL) /*!< ECERDB (Bitfield-Mask: 0x7f) */ + #define R_SYSRAM0_W_EC710TRC_ECECRD_Pos (8UL) /*!< ECECRD (Bit 8) */ + #define R_SYSRAM0_W_EC710TRC_ECECRD_Msk (0x7f00UL) /*!< ECECRD (Bitfield-Mask: 0x7f) */ + #define R_SYSRAM0_W_EC710TRC_ECHORD_Pos (16UL) /*!< ECHORD (Bit 16) */ + #define R_SYSRAM0_W_EC710TRC_ECHORD_Msk (0x7f0000UL) /*!< ECHORD (Bitfield-Mask: 0x7f) */ + #define R_SYSRAM0_W_EC710TRC_ECSYND_Pos (24UL) /*!< ECSYND (Bit 24) */ + #define R_SYSRAM0_W_EC710TRC_ECSYND_Msk (0x7f000000UL) /*!< ECSYND (Bitfield-Mask: 0x7f) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_SYSRAM0_W_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_SYSRAM0_W_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD ======================================================== */ + #define R_SYSRAM0_W_EC710EAD_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_SYSRAM0_W_EC710EAD_ECEAD_Msk (0x7fffUL) /*!< ECEAD (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ RGN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STADD ========================================================= */ + #define R_MPU0_RGN_STADD_RDPR_Pos (0UL) /*!< RDPR (Bit 0) */ + #define R_MPU0_RGN_STADD_RDPR_Msk (0x1UL) /*!< RDPR (Bitfield-Mask: 0x01) */ + #define R_MPU0_RGN_STADD_WRPR_Pos (1UL) /*!< WRPR (Bit 1) */ + #define R_MPU0_RGN_STADD_WRPR_Msk (0x2UL) /*!< WRPR (Bitfield-Mask: 0x01) */ + #define R_MPU0_RGN_STADD_STADDR_Pos (10UL) /*!< STADDR (Bit 10) */ + #define R_MPU0_RGN_STADD_STADDR_Msk (0xfffffc00UL) /*!< STADDR (Bitfield-Mask: 0x3fffff) */ +/* ======================================================== ENDADD ========================================================= */ + #define R_MPU0_RGN_ENDADD_ENDADDR_Pos (10UL) /*!< ENDADDR (Bit 10) */ + #define R_MPU0_RGN_ENDADD_ENDADDR_Msk (0xfffffc00UL) /*!< ENDADDR (Bitfield-Mask: 0x3fffff) */ + +/* =========================================================================================================================== */ +/* ================ TR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DSOCL ========================================================= */ + #define R_DSMIF0_CH_TR_DSOCL_OCMPTBL0_Pos (0UL) /*!< OCMPTBL0 (Bit 0) */ + #define R_DSMIF0_CH_TR_DSOCL_OCMPTBL0_Msk (0xffffUL) /*!< OCMPTBL0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= DSOCH ========================================================= */ + #define R_DSMIF0_CH_TR_DSOCH_OCMPTBH0_Pos (0UL) /*!< OCMPTBH0 (Bit 0) */ + #define R_DSMIF0_CH_TR_DSOCH_OCMPTBH0_Msk (0xffffUL) /*!< OCMPTBH0 (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ DR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DSCOC ========================================================= */ + #define R_DSMIF0_CH_DR_DSCOC_CODR0_Pos (0UL) /*!< CODR0 (Bit 0) */ + #define R_DSMIF0_CH_DR_DSCOC_CODR0_Msk (0xffffUL) /*!< CODR0 (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ CH ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DSICR ========================================================= */ + #define R_DSMIF0_CH_DSICR_IUE_Pos (0UL) /*!< IUE (Bit 0) */ + #define R_DSMIF0_CH_DSICR_IUE_Msk (0x1UL) /*!< IUE (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_IAUE_Pos (1UL) /*!< IAUE (Bit 1) */ + #define R_DSMIF0_CH_DSICR_IAUE_Msk (0x2UL) /*!< IAUE (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_IBUE_Pos (2UL) /*!< IBUE (Bit 2) */ + #define R_DSMIF0_CH_DSICR_IBUE_Msk (0x4UL) /*!< IBUE (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_ISE_Pos (3UL) /*!< ISE (Bit 3) */ + #define R_DSMIF0_CH_DSICR_ISE_Msk (0x8UL) /*!< ISE (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_IOEL0_Pos (8UL) /*!< IOEL0 (Bit 8) */ + #define R_DSMIF0_CH_DSICR_IOEL0_Msk (0x100UL) /*!< IOEL0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_IOEH0_Pos (9UL) /*!< IOEH0 (Bit 9) */ + #define R_DSMIF0_CH_DSICR_IOEH0_Msk (0x200UL) /*!< IOEH0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_IOEL1_Pos (10UL) /*!< IOEL1 (Bit 10) */ + #define R_DSMIF0_CH_DSICR_IOEL1_Msk (0x400UL) /*!< IOEL1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_IOEH1_Pos (11UL) /*!< IOEH1 (Bit 11) */ + #define R_DSMIF0_CH_DSICR_IOEH1_Msk (0x800UL) /*!< IOEH1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_IOEL2_Pos (12UL) /*!< IOEL2 (Bit 12) */ + #define R_DSMIF0_CH_DSICR_IOEL2_Msk (0x1000UL) /*!< IOEL2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_IOEH2_Pos (13UL) /*!< IOEH2 (Bit 13) */ + #define R_DSMIF0_CH_DSICR_IOEH2_Msk (0x2000UL) /*!< IOEH2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_OWNE0_Pos (16UL) /*!< OWNE0 (Bit 16) */ + #define R_DSMIF0_CH_DSICR_OWNE0_Msk (0x10000UL) /*!< OWNE0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_OWNE1_Pos (17UL) /*!< OWNE1 (Bit 17) */ + #define R_DSMIF0_CH_DSICR_OWNE1_Msk (0x20000UL) /*!< OWNE1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_OWNE2_Pos (18UL) /*!< OWNE2 (Bit 18) */ + #define R_DSMIF0_CH_DSICR_OWNE2_Msk (0x40000UL) /*!< OWNE2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_OWNE3_Pos (19UL) /*!< OWNE3 (Bit 19) */ + #define R_DSMIF0_CH_DSICR_OWNE3_Msk (0x80000UL) /*!< OWNE3 (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCMCCR ======================================================== */ + #define R_DSMIF0_CH_DSCMCCR_CKDIR_Pos (0UL) /*!< CKDIR (Bit 0) */ + #define R_DSMIF0_CH_DSCMCCR_CKDIR_Msk (0x1UL) /*!< CKDIR (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCMCCR_SEDGE_Pos (7UL) /*!< SEDGE (Bit 7) */ + #define R_DSMIF0_CH_DSCMCCR_SEDGE_Msk (0x80UL) /*!< SEDGE (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCMCCR_CKDIV_Pos (8UL) /*!< CKDIV (Bit 8) */ + #define R_DSMIF0_CH_DSCMCCR_CKDIV_Msk (0x3f00UL) /*!< CKDIV (Bitfield-Mask: 0x3f) */ +/* ======================================================== DSCMFCR ======================================================== */ + #define R_DSMIF0_CH_DSCMFCR_CMSINC_Pos (0UL) /*!< CMSINC (Bit 0) */ + #define R_DSMIF0_CH_DSCMFCR_CMSINC_Msk (0x3UL) /*!< CMSINC (Bitfield-Mask: 0x03) */ + #define R_DSMIF0_CH_DSCMFCR_CMDEC_Pos (8UL) /*!< CMDEC (Bit 8) */ + #define R_DSMIF0_CH_DSCMFCR_CMDEC_Msk (0xff00UL) /*!< CMDEC (Bitfield-Mask: 0xff) */ + #define R_DSMIF0_CH_DSCMFCR_CMSH_Pos (16UL) /*!< CMSH (Bit 16) */ + #define R_DSMIF0_CH_DSCMFCR_CMSH_Msk (0x1f0000UL) /*!< CMSH (Bitfield-Mask: 0x1f) */ +/* ======================================================= DSCMCTCR ======================================================== */ + #define R_DSMIF0_CH_DSCMCTCR_CTSELA_Pos (0UL) /*!< CTSELA (Bit 0) */ + #define R_DSMIF0_CH_DSCMCTCR_CTSELA_Msk (0x7UL) /*!< CTSELA (Bitfield-Mask: 0x07) */ + #define R_DSMIF0_CH_DSCMCTCR_CTSELB_Pos (8UL) /*!< CTSELB (Bit 8) */ + #define R_DSMIF0_CH_DSCMCTCR_CTSELB_Msk (0x700UL) /*!< CTSELB (Bitfield-Mask: 0x07) */ + #define R_DSMIF0_CH_DSCMCTCR_DITSEL_Pos (16UL) /*!< DITSEL (Bit 16) */ + #define R_DSMIF0_CH_DSCMCTCR_DITSEL_Msk (0x30000UL) /*!< DITSEL (Bitfield-Mask: 0x03) */ + #define R_DSMIF0_CH_DSCMCTCR_DEDGE_Pos (23UL) /*!< DEDGE (Bit 23) */ + #define R_DSMIF0_CH_DSCMCTCR_DEDGE_Msk (0x800000UL) /*!< DEDGE (Bitfield-Mask: 0x01) */ +/* ======================================================== DSEDCR ========================================================= */ + #define R_DSMIF0_CH_DSEDCR_SDE_Pos (0UL) /*!< SDE (Bit 0) */ + #define R_DSMIF0_CH_DSEDCR_SDE_Msk (0x1UL) /*!< SDE (Bitfield-Mask: 0x01) */ +/* ======================================================== DSSCTSR ======================================================== */ + #define R_DSMIF0_CH_DSSCTSR_SCNTL_Pos (0UL) /*!< SCNTL (Bit 0) */ + #define R_DSMIF0_CH_DSSCTSR_SCNTL_Msk (0x1fffUL) /*!< SCNTL (Bitfield-Mask: 0x1fff) */ + #define R_DSMIF0_CH_DSSCTSR_SCNTH_Pos (16UL) /*!< SCNTH (Bit 16) */ + #define R_DSMIF0_CH_DSSCTSR_SCNTH_Msk (0x1fff0000UL) /*!< SCNTH (Bitfield-Mask: 0x1fff) */ +/* ======================================================== DSOCFCR ======================================================== */ + #define R_DSMIF0_CH_DSOCFCR_OCSINC_Pos (0UL) /*!< OCSINC (Bit 0) */ + #define R_DSMIF0_CH_DSOCFCR_OCSINC_Msk (0x3UL) /*!< OCSINC (Bitfield-Mask: 0x03) */ + #define R_DSMIF0_CH_DSOCFCR_OCDEC_Pos (8UL) /*!< OCDEC (Bit 8) */ + #define R_DSMIF0_CH_DSOCFCR_OCDEC_Msk (0xff00UL) /*!< OCDEC (Bitfield-Mask: 0xff) */ + #define R_DSMIF0_CH_DSOCFCR_OCSH_Pos (16UL) /*!< OCSH (Bit 16) */ + #define R_DSMIF0_CH_DSOCFCR_OCSH_Msk (0x1f0000UL) /*!< OCSH (Bitfield-Mask: 0x1f) */ +/* ======================================================== DSODCR ========================================================= */ + #define R_DSMIF0_CH_DSODCR_ODEL0_Pos (0UL) /*!< ODEL0 (Bit 0) */ + #define R_DSMIF0_CH_DSODCR_ODEL0_Msk (0x1UL) /*!< ODEL0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSODCR_ODEH0_Pos (1UL) /*!< ODEH0 (Bit 1) */ + #define R_DSMIF0_CH_DSODCR_ODEH0_Msk (0x2UL) /*!< ODEH0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSODCR_ODEL1_Pos (2UL) /*!< ODEL1 (Bit 2) */ + #define R_DSMIF0_CH_DSODCR_ODEL1_Msk (0x4UL) /*!< ODEL1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSODCR_ODEH1_Pos (3UL) /*!< ODEH1 (Bit 3) */ + #define R_DSMIF0_CH_DSODCR_ODEH1_Msk (0x8UL) /*!< ODEH1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSODCR_ODEL2_Pos (4UL) /*!< ODEL2 (Bit 4) */ + #define R_DSMIF0_CH_DSODCR_ODEL2_Msk (0x10UL) /*!< ODEL2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSODCR_ODEH2_Pos (5UL) /*!< ODEH2 (Bit 5) */ + #define R_DSMIF0_CH_DSODCR_ODEH2_Msk (0x20UL) /*!< ODEH2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSODCR_OWFE0_Pos (8UL) /*!< OWFE0 (Bit 8) */ + #define R_DSMIF0_CH_DSODCR_OWFE0_Msk (0x100UL) /*!< OWFE0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSODCR_OWFE1_Pos (9UL) /*!< OWFE1 (Bit 9) */ + #define R_DSMIF0_CH_DSODCR_OWFE1_Msk (0x200UL) /*!< OWFE1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSODCR_OWFE2_Pos (10UL) /*!< OWFE2 (Bit 10) */ + #define R_DSMIF0_CH_DSODCR_OWFE2_Msk (0x400UL) /*!< OWFE2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSODCR_OWFE3_Pos (11UL) /*!< OWFE3 (Bit 11) */ + #define R_DSMIF0_CH_DSODCR_OWFE3_Msk (0x800UL) /*!< OWFE3 (Bitfield-Mask: 0x01) */ +/* ======================================================== DSODWCR ======================================================== */ + #define R_DSMIF0_CH_DSODWCR_OWNM0_Pos (0UL) /*!< OWNM0 (Bit 0) */ + #define R_DSMIF0_CH_DSODWCR_OWNM0_Msk (0x1UL) /*!< OWNM0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSODWCR_OWNM1_Pos (1UL) /*!< OWNM1 (Bit 1) */ + #define R_DSMIF0_CH_DSODWCR_OWNM1_Msk (0x2UL) /*!< OWNM1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSODWCR_OWNM2_Pos (2UL) /*!< OWNM2 (Bit 2) */ + #define R_DSMIF0_CH_DSODWCR_OWNM2_Msk (0x4UL) /*!< OWNM2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSODWCR_OWNM3_Pos (3UL) /*!< OWNM3 (Bit 3) */ + #define R_DSMIF0_CH_DSODWCR_OWNM3_Msk (0x78UL) /*!< OWNM3 (Bitfield-Mask: 0x0f) */ +/* ======================================================= DSCSTRTR ======================================================== */ + #define R_DSMIF0_CH_DSCSTRTR_STRTRG_Pos (0UL) /*!< STRTRG (Bit 0) */ + #define R_DSMIF0_CH_DSCSTRTR_STRTRG_Msk (0x1UL) /*!< STRTRG (Bitfield-Mask: 0x01) */ +/* ======================================================= DSCSTPTR ======================================================== */ + #define R_DSMIF0_CH_DSCSTPTR_STPTRG_Pos (0UL) /*!< STPTRG (Bit 0) */ + #define R_DSMIF0_CH_DSCSTPTR_STPTRG_Msk (0x1UL) /*!< STPTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= DSCDR ========================================================= */ + #define R_DSMIF0_CH_DSCDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_DSMIF0_CH_DSCDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSCCDRA ======================================================== */ + #define R_DSMIF0_CH_DSCCDRA_CDRA_Pos (0UL) /*!< CDRA (Bit 0) */ + #define R_DSMIF0_CH_DSCCDRA_CDRA_Msk (0xffffUL) /*!< CDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSCCDRB ======================================================== */ + #define R_DSMIF0_CH_DSCCDRB_CDRB_Pos (0UL) /*!< CDRB (Bit 0) */ + #define R_DSMIF0_CH_DSCCDRB_CDRB_Msk (0xffffUL) /*!< CDRB (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSOCDR ========================================================= */ + #define R_DSMIF0_CH_DSOCDR_ODR_Pos (0UL) /*!< ODR (Bit 0) */ + #define R_DSMIF0_CH_DSOCDR_ODR_Msk (0xffffUL) /*!< ODR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DSCSR ========================================================= */ + #define R_DSMIF0_CH_DSCSR_DUF_Pos (0UL) /*!< DUF (Bit 0) */ + #define R_DSMIF0_CH_DSCSR_DUF_Msk (0x1UL) /*!< DUF (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_CAUF_Pos (1UL) /*!< CAUF (Bit 1) */ + #define R_DSMIF0_CH_DSCSR_CAUF_Msk (0x2UL) /*!< CAUF (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_CBUF_Pos (2UL) /*!< CBUF (Bit 2) */ + #define R_DSMIF0_CH_DSCSR_CBUF_Msk (0x4UL) /*!< CBUF (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_SCF_Pos (3UL) /*!< SCF (Bit 3) */ + #define R_DSMIF0_CH_DSCSR_SCF_Msk (0x8UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_CHSTATE_Pos (7UL) /*!< CHSTATE (Bit 7) */ + #define R_DSMIF0_CH_DSCSR_CHSTATE_Msk (0x80UL) /*!< CHSTATE (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OC0FL_Pos (8UL) /*!< OC0FL (Bit 8) */ + #define R_DSMIF0_CH_DSCSR_OC0FL_Msk (0x100UL) /*!< OC0FL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OC0FH_Pos (9UL) /*!< OC0FH (Bit 9) */ + #define R_DSMIF0_CH_DSCSR_OC0FH_Msk (0x200UL) /*!< OC0FH (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OC1FL_Pos (10UL) /*!< OC1FL (Bit 10) */ + #define R_DSMIF0_CH_DSCSR_OC1FL_Msk (0x400UL) /*!< OC1FL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OC1FH_Pos (11UL) /*!< OC1FH (Bit 11) */ + #define R_DSMIF0_CH_DSCSR_OC1FH_Msk (0x800UL) /*!< OC1FH (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OC2FL_Pos (12UL) /*!< OC2FL (Bit 12) */ + #define R_DSMIF0_CH_DSCSR_OC2FL_Msk (0x1000UL) /*!< OC2FL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OC2FH_Pos (13UL) /*!< OC2FH (Bit 13) */ + #define R_DSMIF0_CH_DSCSR_OC2FH_Msk (0x2000UL) /*!< OC2FH (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OWD0N_Pos (16UL) /*!< OWD0N (Bit 16) */ + #define R_DSMIF0_CH_DSCSR_OWD0N_Msk (0x10000UL) /*!< OWD0N (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OWD1N_Pos (17UL) /*!< OWD1N (Bit 17) */ + #define R_DSMIF0_CH_DSCSR_OWD1N_Msk (0x20000UL) /*!< OWD1N (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OWD2N_Pos (18UL) /*!< OWD2N (Bit 18) */ + #define R_DSMIF0_CH_DSCSR_OWD2N_Msk (0x40000UL) /*!< OWD2N (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OWD3N_Pos (19UL) /*!< OWD3N (Bit 19) */ + #define R_DSMIF0_CH_DSCSR_OWD3N_Msk (0x80000UL) /*!< OWD3N (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OC0CMPL_Pos (24UL) /*!< OC0CMPL (Bit 24) */ + #define R_DSMIF0_CH_DSCSR_OC0CMPL_Msk (0x1000000UL) /*!< OC0CMPL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OC0CMPH_Pos (25UL) /*!< OC0CMPH (Bit 25) */ + #define R_DSMIF0_CH_DSCSR_OC0CMPH_Msk (0x2000000UL) /*!< OC0CMPH (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OC1CMPL_Pos (26UL) /*!< OC1CMPL (Bit 26) */ + #define R_DSMIF0_CH_DSCSR_OC1CMPL_Msk (0x4000000UL) /*!< OC1CMPL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OC1CMPH_Pos (27UL) /*!< OC1CMPH (Bit 27) */ + #define R_DSMIF0_CH_DSCSR_OC1CMPH_Msk (0x8000000UL) /*!< OC1CMPH (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OC2CMPL_Pos (28UL) /*!< OC2CMPL (Bit 28) */ + #define R_DSMIF0_CH_DSCSR_OC2CMPL_Msk (0x10000000UL) /*!< OC2CMPL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OC2CMPH_Pos (29UL) /*!< OC2CMPH (Bit 29) */ + #define R_DSMIF0_CH_DSCSR_OC2CMPH_Msk (0x20000000UL) /*!< OC2CMPH (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCSCR ========================================================= */ + #define R_DSMIF0_CH_DSCSCR_CLRDUF_Pos (0UL) /*!< CLRDUF (Bit 0) */ + #define R_DSMIF0_CH_DSCSCR_CLRDUF_Msk (0x1UL) /*!< CLRDUF (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLRCAUF_Pos (1UL) /*!< CLRCAUF (Bit 1) */ + #define R_DSMIF0_CH_DSCSCR_CLRCAUF_Msk (0x2UL) /*!< CLRCAUF (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLRCBUF_Pos (2UL) /*!< CLRCBUF (Bit 2) */ + #define R_DSMIF0_CH_DSCSCR_CLRCBUF_Msk (0x4UL) /*!< CLRCBUF (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLRSCF_Pos (3UL) /*!< CLRSCF (Bit 3) */ + #define R_DSMIF0_CH_DSCSCR_CLRSCF_Msk (0x8UL) /*!< CLRSCF (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLROC0FL_Pos (8UL) /*!< CLROC0FL (Bit 8) */ + #define R_DSMIF0_CH_DSCSCR_CLROC0FL_Msk (0x100UL) /*!< CLROC0FL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLROC0FH_Pos (9UL) /*!< CLROC0FH (Bit 9) */ + #define R_DSMIF0_CH_DSCSCR_CLROC0FH_Msk (0x200UL) /*!< CLROC0FH (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLROC1FL_Pos (10UL) /*!< CLROC1FL (Bit 10) */ + #define R_DSMIF0_CH_DSCSCR_CLROC1FL_Msk (0x400UL) /*!< CLROC1FL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLROC1FH_Pos (11UL) /*!< CLROC1FH (Bit 11) */ + #define R_DSMIF0_CH_DSCSCR_CLROC1FH_Msk (0x800UL) /*!< CLROC1FH (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLROC2FL_Pos (12UL) /*!< CLROC2FL (Bit 12) */ + #define R_DSMIF0_CH_DSCSCR_CLROC2FL_Msk (0x1000UL) /*!< CLROC2FL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLROC2FH_Pos (13UL) /*!< CLROC2FH (Bit 13) */ + #define R_DSMIF0_CH_DSCSCR_CLROC2FH_Msk (0x2000UL) /*!< CLROC2FH (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLROWD0N_Pos (16UL) /*!< CLROWD0N (Bit 16) */ + #define R_DSMIF0_CH_DSCSCR_CLROWD0N_Msk (0x10000UL) /*!< CLROWD0N (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLROWD1N_Pos (17UL) /*!< CLROWD1N (Bit 17) */ + #define R_DSMIF0_CH_DSCSCR_CLROWD1N_Msk (0x20000UL) /*!< CLROWD1N (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLROWD2N_Pos (18UL) /*!< CLROWD2N (Bit 18) */ + #define R_DSMIF0_CH_DSCSCR_CLROWD2N_Msk (0x40000UL) /*!< CLROWD2N (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLROWD3N_Pos (19UL) /*!< CLROWD3N (Bit 19) */ + #define R_DSMIF0_CH_DSCSCR_CLROWD3N_Msk (0x80000UL) /*!< CLROWD3N (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SCDATA ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ +/* =========================================================== H =========================================================== */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT7_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT7_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT7_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT7_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT7_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT7_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT7_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT7_GTSTR_CSTRT0_Pos (0UL) /*!< CSTRT0 (Bit 0) */ + #define R_GPT7_GTSTR_CSTRT0_Msk (0x1UL) /*!< CSTRT0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT1_Pos (1UL) /*!< CSTRT1 (Bit 1) */ + #define R_GPT7_GTSTR_CSTRT1_Msk (0x2UL) /*!< CSTRT1 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT2_Pos (2UL) /*!< CSTRT2 (Bit 2) */ + #define R_GPT7_GTSTR_CSTRT2_Msk (0x4UL) /*!< CSTRT2 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT3_Pos (3UL) /*!< CSTRT3 (Bit 3) */ + #define R_GPT7_GTSTR_CSTRT3_Msk (0x8UL) /*!< CSTRT3 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT4_Pos (4UL) /*!< CSTRT4 (Bit 4) */ + #define R_GPT7_GTSTR_CSTRT4_Msk (0x10UL) /*!< CSTRT4 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT5_Pos (5UL) /*!< CSTRT5 (Bit 5) */ + #define R_GPT7_GTSTR_CSTRT5_Msk (0x20UL) /*!< CSTRT5 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT6_Pos (6UL) /*!< CSTRT6 (Bit 6) */ + #define R_GPT7_GTSTR_CSTRT6_Msk (0x40UL) /*!< CSTRT6 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT7_GTSTP_CSTOP0_Pos (0UL) /*!< CSTOP0 (Bit 0) */ + #define R_GPT7_GTSTP_CSTOP0_Msk (0x1UL) /*!< CSTOP0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP1_Pos (1UL) /*!< CSTOP1 (Bit 1) */ + #define R_GPT7_GTSTP_CSTOP1_Msk (0x2UL) /*!< CSTOP1 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP2_Pos (2UL) /*!< CSTOP2 (Bit 2) */ + #define R_GPT7_GTSTP_CSTOP2_Msk (0x4UL) /*!< CSTOP2 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP3_Pos (3UL) /*!< CSTOP3 (Bit 3) */ + #define R_GPT7_GTSTP_CSTOP3_Msk (0x8UL) /*!< CSTOP3 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP4_Pos (4UL) /*!< CSTOP4 (Bit 4) */ + #define R_GPT7_GTSTP_CSTOP4_Msk (0x10UL) /*!< CSTOP4 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP5_Pos (5UL) /*!< CSTOP5 (Bit 5) */ + #define R_GPT7_GTSTP_CSTOP5_Msk (0x20UL) /*!< CSTOP5 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP6_Pos (6UL) /*!< CSTOP6 (Bit 6) */ + #define R_GPT7_GTSTP_CSTOP6_Msk (0x40UL) /*!< CSTOP6 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT7_GTCLR_CCLR0_Pos (0UL) /*!< CCLR0 (Bit 0) */ + #define R_GPT7_GTCLR_CCLR0_Msk (0x1UL) /*!< CCLR0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR1_Pos (1UL) /*!< CCLR1 (Bit 1) */ + #define R_GPT7_GTCLR_CCLR1_Msk (0x2UL) /*!< CCLR1 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR2_Pos (2UL) /*!< CCLR2 (Bit 2) */ + #define R_GPT7_GTCLR_CCLR2_Msk (0x4UL) /*!< CCLR2 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR3_Pos (3UL) /*!< CCLR3 (Bit 3) */ + #define R_GPT7_GTCLR_CCLR3_Msk (0x8UL) /*!< CCLR3 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR4_Pos (4UL) /*!< CCLR4 (Bit 4) */ + #define R_GPT7_GTCLR_CCLR4_Msk (0x10UL) /*!< CCLR4 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR5_Pos (5UL) /*!< CCLR5 (Bit 5) */ + #define R_GPT7_GTCLR_CCLR5_Msk (0x20UL) /*!< CCLR5 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR6_Pos (6UL) /*!< CCLR6 (Bit 6) */ + #define R_GPT7_GTCLR_CCLR6_Msk (0x40UL) /*!< CCLR6 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT7_GTSSR_SSGTRGAFR_Pos (0UL) /*!< SSGTRGAFR (Bit 0) */ + #define R_GPT7_GTSSR_SSGTRGAFR_Msk (0x3UL) /*!< SSGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSGTRGBFR_Pos (2UL) /*!< SSGTRGBFR (Bit 2) */ + #define R_GPT7_GTSSR_SSGTRGBFR_Msk (0xcUL) /*!< SSGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSGTRGCFR_Pos (4UL) /*!< SSGTRGCFR (Bit 4) */ + #define R_GPT7_GTSSR_SSGTRGCFR_Msk (0x30UL) /*!< SSGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSGTRGDFR_Pos (6UL) /*!< SSGTRGDFR (Bit 6) */ + #define R_GPT7_GTSSR_SSGTRGDFR_Msk (0xc0UL) /*!< SSGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSCARBHL_Pos (8UL) /*!< SSCARBHL (Bit 8) */ + #define R_GPT7_GTSSR_SSCARBHL_Msk (0x300UL) /*!< SSCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSCAFBHL_Pos (10UL) /*!< SSCAFBHL (Bit 10) */ + #define R_GPT7_GTSSR_SSCAFBHL_Msk (0xc00UL) /*!< SSCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSCBRAHL_Pos (12UL) /*!< SSCBRAHL (Bit 12) */ + #define R_GPT7_GTSSR_SSCBRAHL_Msk (0x3000UL) /*!< SSCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSCBFAHL_Pos (14UL) /*!< SSCBFAHL (Bit 14) */ + #define R_GPT7_GTSSR_SSCBFAHL_Msk (0xc000UL) /*!< SSCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSELCA_Pos (16UL) /*!< SSELCA (Bit 16) */ + #define R_GPT7_GTSSR_SSELCA_Msk (0x10000UL) /*!< SSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCB_Pos (17UL) /*!< SSELCB (Bit 17) */ + #define R_GPT7_GTSSR_SSELCB_Msk (0x20000UL) /*!< SSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCC_Pos (18UL) /*!< SSELCC (Bit 18) */ + #define R_GPT7_GTSSR_SSELCC_Msk (0x40000UL) /*!< SSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCD_Pos (19UL) /*!< SSELCD (Bit 19) */ + #define R_GPT7_GTSSR_SSELCD_Msk (0x80000UL) /*!< SSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCE_Pos (20UL) /*!< SSELCE (Bit 20) */ + #define R_GPT7_GTSSR_SSELCE_Msk (0x100000UL) /*!< SSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCF_Pos (21UL) /*!< SSELCF (Bit 21) */ + #define R_GPT7_GTSSR_SSELCF_Msk (0x200000UL) /*!< SSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCG_Pos (22UL) /*!< SSELCG (Bit 22) */ + #define R_GPT7_GTSSR_SSELCG_Msk (0x400000UL) /*!< SSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCH_Pos (23UL) /*!< SSELCH (Bit 23) */ + #define R_GPT7_GTSSR_SSELCH_Msk (0x800000UL) /*!< SSELCH (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT7_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT7_GTPSR_PSGTRGAFR_Pos (0UL) /*!< PSGTRGAFR (Bit 0) */ + #define R_GPT7_GTPSR_PSGTRGAFR_Msk (0x3UL) /*!< PSGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSGTRGBFR_Pos (2UL) /*!< PSGTRGBFR (Bit 2) */ + #define R_GPT7_GTPSR_PSGTRGBFR_Msk (0xcUL) /*!< PSGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSGTRGCFR_Pos (4UL) /*!< PSGTRGCFR (Bit 4) */ + #define R_GPT7_GTPSR_PSGTRGCFR_Msk (0x30UL) /*!< PSGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSGTRGDFR_Pos (6UL) /*!< PSGTRGDFR (Bit 6) */ + #define R_GPT7_GTPSR_PSGTRGDFR_Msk (0xc0UL) /*!< PSGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSCARBHL_Pos (8UL) /*!< PSCARBHL (Bit 8) */ + #define R_GPT7_GTPSR_PSCARBHL_Msk (0x300UL) /*!< PSCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSCAFBHL_Pos (10UL) /*!< PSCAFBHL (Bit 10) */ + #define R_GPT7_GTPSR_PSCAFBHL_Msk (0xc00UL) /*!< PSCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSCBRAHL_Pos (12UL) /*!< PSCBRAHL (Bit 12) */ + #define R_GPT7_GTPSR_PSCBRAHL_Msk (0x3000UL) /*!< PSCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSCBFAHL_Pos (14UL) /*!< PSCBFAHL (Bit 14) */ + #define R_GPT7_GTPSR_PSCBFAHL_Msk (0xc000UL) /*!< PSCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSELCA_Pos (16UL) /*!< PSELCA (Bit 16) */ + #define R_GPT7_GTPSR_PSELCA_Msk (0x10000UL) /*!< PSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCB_Pos (17UL) /*!< PSELCB (Bit 17) */ + #define R_GPT7_GTPSR_PSELCB_Msk (0x20000UL) /*!< PSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCC_Pos (18UL) /*!< PSELCC (Bit 18) */ + #define R_GPT7_GTPSR_PSELCC_Msk (0x40000UL) /*!< PSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCD_Pos (19UL) /*!< PSELCD (Bit 19) */ + #define R_GPT7_GTPSR_PSELCD_Msk (0x80000UL) /*!< PSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCE_Pos (20UL) /*!< PSELCE (Bit 20) */ + #define R_GPT7_GTPSR_PSELCE_Msk (0x100000UL) /*!< PSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCF_Pos (21UL) /*!< PSELCF (Bit 21) */ + #define R_GPT7_GTPSR_PSELCF_Msk (0x200000UL) /*!< PSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCG_Pos (22UL) /*!< PSELCG (Bit 22) */ + #define R_GPT7_GTPSR_PSELCG_Msk (0x400000UL) /*!< PSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCH_Pos (23UL) /*!< PSELCH (Bit 23) */ + #define R_GPT7_GTPSR_PSELCH_Msk (0x800000UL) /*!< PSELCH (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT7_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT7_GTCSR_CSGTRGAFR_Pos (0UL) /*!< CSGTRGAFR (Bit 0) */ + #define R_GPT7_GTCSR_CSGTRGAFR_Msk (0x3UL) /*!< CSGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSGTRGBFR_Pos (2UL) /*!< CSGTRGBFR (Bit 2) */ + #define R_GPT7_GTCSR_CSGTRGBFR_Msk (0xcUL) /*!< CSGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSGTRGCFR_Pos (4UL) /*!< CSGTRGCFR (Bit 4) */ + #define R_GPT7_GTCSR_CSGTRGCFR_Msk (0x30UL) /*!< CSGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSGTRGDFR_Pos (6UL) /*!< CSGTRGDFR (Bit 6) */ + #define R_GPT7_GTCSR_CSGTRGDFR_Msk (0xc0UL) /*!< CSGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSCARBHL_Pos (8UL) /*!< CSCARBHL (Bit 8) */ + #define R_GPT7_GTCSR_CSCARBHL_Msk (0x300UL) /*!< CSCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSCAFBHL_Pos (10UL) /*!< CSCAFBHL (Bit 10) */ + #define R_GPT7_GTCSR_CSCAFBHL_Msk (0xc00UL) /*!< CSCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSCBRAHL_Pos (12UL) /*!< CSCBRAHL (Bit 12) */ + #define R_GPT7_GTCSR_CSCBRAHL_Msk (0x3000UL) /*!< CSCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSCBFAHL_Pos (14UL) /*!< CSCBFAHL (Bit 14) */ + #define R_GPT7_GTCSR_CSCBFAHL_Msk (0xc000UL) /*!< CSCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSELCA_Pos (16UL) /*!< CSELCA (Bit 16) */ + #define R_GPT7_GTCSR_CSELCA_Msk (0x10000UL) /*!< CSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCB_Pos (17UL) /*!< CSELCB (Bit 17) */ + #define R_GPT7_GTCSR_CSELCB_Msk (0x20000UL) /*!< CSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCC_Pos (18UL) /*!< CSELCC (Bit 18) */ + #define R_GPT7_GTCSR_CSELCC_Msk (0x40000UL) /*!< CSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCD_Pos (19UL) /*!< CSELCD (Bit 19) */ + #define R_GPT7_GTCSR_CSELCD_Msk (0x80000UL) /*!< CSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCE_Pos (20UL) /*!< CSELCE (Bit 20) */ + #define R_GPT7_GTCSR_CSELCE_Msk (0x100000UL) /*!< CSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCF_Pos (21UL) /*!< CSELCF (Bit 21) */ + #define R_GPT7_GTCSR_CSELCF_Msk (0x200000UL) /*!< CSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCG_Pos (22UL) /*!< CSELCG (Bit 22) */ + #define R_GPT7_GTCSR_CSELCG_Msk (0x400000UL) /*!< CSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCH_Pos (23UL) /*!< CSELCH (Bit 23) */ + #define R_GPT7_GTCSR_CSELCH_Msk (0x800000UL) /*!< CSELCH (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT7_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT7_GTUPSR_USGTRGAFR_Pos (0UL) /*!< USGTRGAFR (Bit 0) */ + #define R_GPT7_GTUPSR_USGTRGAFR_Msk (0x3UL) /*!< USGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USGTRGBFR_Pos (2UL) /*!< USGTRGBFR (Bit 2) */ + #define R_GPT7_GTUPSR_USGTRGBFR_Msk (0xcUL) /*!< USGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USGTRGCFR_Pos (4UL) /*!< USGTRGCFR (Bit 4) */ + #define R_GPT7_GTUPSR_USGTRGCFR_Msk (0x30UL) /*!< USGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USGTRGDFR_Pos (6UL) /*!< USGTRGDFR (Bit 6) */ + #define R_GPT7_GTUPSR_USGTRGDFR_Msk (0xc0UL) /*!< USGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USCARBHL_Pos (8UL) /*!< USCARBHL (Bit 8) */ + #define R_GPT7_GTUPSR_USCARBHL_Msk (0x300UL) /*!< USCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USCAFBHL_Pos (10UL) /*!< USCAFBHL (Bit 10) */ + #define R_GPT7_GTUPSR_USCAFBHL_Msk (0xc00UL) /*!< USCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USCBRAHL_Pos (12UL) /*!< USCBRAHL (Bit 12) */ + #define R_GPT7_GTUPSR_USCBRAHL_Msk (0x3000UL) /*!< USCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USCBFAHL_Pos (14UL) /*!< USCBFAHL (Bit 14) */ + #define R_GPT7_GTUPSR_USCBFAHL_Msk (0xc000UL) /*!< USCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USELCA_Pos (16UL) /*!< USELCA (Bit 16) */ + #define R_GPT7_GTUPSR_USELCA_Msk (0x10000UL) /*!< USELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCB_Pos (17UL) /*!< USELCB (Bit 17) */ + #define R_GPT7_GTUPSR_USELCB_Msk (0x20000UL) /*!< USELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCC_Pos (18UL) /*!< USELCC (Bit 18) */ + #define R_GPT7_GTUPSR_USELCC_Msk (0x40000UL) /*!< USELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCD_Pos (19UL) /*!< USELCD (Bit 19) */ + #define R_GPT7_GTUPSR_USELCD_Msk (0x80000UL) /*!< USELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCE_Pos (20UL) /*!< USELCE (Bit 20) */ + #define R_GPT7_GTUPSR_USELCE_Msk (0x100000UL) /*!< USELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCF_Pos (21UL) /*!< USELCF (Bit 21) */ + #define R_GPT7_GTUPSR_USELCF_Msk (0x200000UL) /*!< USELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCG_Pos (22UL) /*!< USELCG (Bit 22) */ + #define R_GPT7_GTUPSR_USELCG_Msk (0x400000UL) /*!< USELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCH_Pos (23UL) /*!< USELCH (Bit 23) */ + #define R_GPT7_GTUPSR_USELCH_Msk (0x800000UL) /*!< USELCH (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT7_GTDNSR_DSGTRGAFR_Pos (0UL) /*!< DSGTRGAFR (Bit 0) */ + #define R_GPT7_GTDNSR_DSGTRGAFR_Msk (0x3UL) /*!< DSGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSGTRGBFR_Pos (2UL) /*!< DSGTRGBFR (Bit 2) */ + #define R_GPT7_GTDNSR_DSGTRGBFR_Msk (0xcUL) /*!< DSGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSGTRGCFR_Pos (4UL) /*!< DSGTRGCFR (Bit 4) */ + #define R_GPT7_GTDNSR_DSGTRGCFR_Msk (0x30UL) /*!< DSGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSGTRGDFR_Pos (6UL) /*!< DSGTRGDFR (Bit 6) */ + #define R_GPT7_GTDNSR_DSGTRGDFR_Msk (0xc0UL) /*!< DSGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSCARBHL_Pos (8UL) /*!< DSCARBHL (Bit 8) */ + #define R_GPT7_GTDNSR_DSCARBHL_Msk (0x300UL) /*!< DSCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSCAFBHL_Pos (10UL) /*!< DSCAFBHL (Bit 10) */ + #define R_GPT7_GTDNSR_DSCAFBHL_Msk (0xc00UL) /*!< DSCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSCBRAHL_Pos (12UL) /*!< DSCBRAHL (Bit 12) */ + #define R_GPT7_GTDNSR_DSCBRAHL_Msk (0x3000UL) /*!< DSCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSCBFAHL_Pos (14UL) /*!< DSCBFAHL (Bit 14) */ + #define R_GPT7_GTDNSR_DSCBFAHL_Msk (0xc000UL) /*!< DSCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSELCA_Pos (16UL) /*!< DSELCA (Bit 16) */ + #define R_GPT7_GTDNSR_DSELCA_Msk (0x10000UL) /*!< DSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCB_Pos (17UL) /*!< DSELCB (Bit 17) */ + #define R_GPT7_GTDNSR_DSELCB_Msk (0x20000UL) /*!< DSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCC_Pos (18UL) /*!< DSELCC (Bit 18) */ + #define R_GPT7_GTDNSR_DSELCC_Msk (0x40000UL) /*!< DSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCD_Pos (19UL) /*!< DSELCD (Bit 19) */ + #define R_GPT7_GTDNSR_DSELCD_Msk (0x80000UL) /*!< DSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCE_Pos (20UL) /*!< DSELCE (Bit 20) */ + #define R_GPT7_GTDNSR_DSELCE_Msk (0x100000UL) /*!< DSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCF_Pos (21UL) /*!< DSELCF (Bit 21) */ + #define R_GPT7_GTDNSR_DSELCF_Msk (0x200000UL) /*!< DSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCG_Pos (22UL) /*!< DSELCG (Bit 22) */ + #define R_GPT7_GTDNSR_DSELCG_Msk (0x400000UL) /*!< DSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCH_Pos (23UL) /*!< DSELCH (Bit 23) */ + #define R_GPT7_GTDNSR_DSELCH_Msk (0x800000UL) /*!< DSELCH (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT7_GTICASR_ASGTRGAFR_Pos (0UL) /*!< ASGTRGAFR (Bit 0) */ + #define R_GPT7_GTICASR_ASGTRGAFR_Msk (0x3UL) /*!< ASGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASGTRGBFR_Pos (2UL) /*!< ASGTRGBFR (Bit 2) */ + #define R_GPT7_GTICASR_ASGTRGBFR_Msk (0xcUL) /*!< ASGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASGTRGCFR_Pos (4UL) /*!< ASGTRGCFR (Bit 4) */ + #define R_GPT7_GTICASR_ASGTRGCFR_Msk (0x30UL) /*!< ASGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASGTRGDFR_Pos (6UL) /*!< ASGTRGDFR (Bit 6) */ + #define R_GPT7_GTICASR_ASGTRGDFR_Msk (0xc0UL) /*!< ASGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASCARBHL_Pos (8UL) /*!< ASCARBHL (Bit 8) */ + #define R_GPT7_GTICASR_ASCARBHL_Msk (0x300UL) /*!< ASCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASCAFBHL_Pos (10UL) /*!< ASCAFBHL (Bit 10) */ + #define R_GPT7_GTICASR_ASCAFBHL_Msk (0xc00UL) /*!< ASCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASCBRAHL_Pos (12UL) /*!< ASCBRAHL (Bit 12) */ + #define R_GPT7_GTICASR_ASCBRAHL_Msk (0x3000UL) /*!< ASCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASCBFAHL_Pos (14UL) /*!< ASCBFAHL (Bit 14) */ + #define R_GPT7_GTICASR_ASCBFAHL_Msk (0xc000UL) /*!< ASCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASELCA_Pos (16UL) /*!< ASELCA (Bit 16) */ + #define R_GPT7_GTICASR_ASELCA_Msk (0x10000UL) /*!< ASELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCB_Pos (17UL) /*!< ASELCB (Bit 17) */ + #define R_GPT7_GTICASR_ASELCB_Msk (0x20000UL) /*!< ASELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCC_Pos (18UL) /*!< ASELCC (Bit 18) */ + #define R_GPT7_GTICASR_ASELCC_Msk (0x40000UL) /*!< ASELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCD_Pos (19UL) /*!< ASELCD (Bit 19) */ + #define R_GPT7_GTICASR_ASELCD_Msk (0x80000UL) /*!< ASELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCE_Pos (20UL) /*!< ASELCE (Bit 20) */ + #define R_GPT7_GTICASR_ASELCE_Msk (0x100000UL) /*!< ASELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCF_Pos (21UL) /*!< ASELCF (Bit 21) */ + #define R_GPT7_GTICASR_ASELCF_Msk (0x200000UL) /*!< ASELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCG_Pos (22UL) /*!< ASELCG (Bit 22) */ + #define R_GPT7_GTICASR_ASELCG_Msk (0x400000UL) /*!< ASELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCH_Pos (23UL) /*!< ASELCH (Bit 23) */ + #define R_GPT7_GTICASR_ASELCH_Msk (0x800000UL) /*!< ASELCH (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT7_GTICBSR_BSGTRGAFR_Pos (0UL) /*!< BSGTRGAFR (Bit 0) */ + #define R_GPT7_GTICBSR_BSGTRGAFR_Msk (0x3UL) /*!< BSGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSGTRGBFR_Pos (2UL) /*!< BSGTRGBFR (Bit 2) */ + #define R_GPT7_GTICBSR_BSGTRGBFR_Msk (0xcUL) /*!< BSGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSGTRGCFR_Pos (4UL) /*!< BSGTRGCFR (Bit 4) */ + #define R_GPT7_GTICBSR_BSGTRGCFR_Msk (0x30UL) /*!< BSGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSGTRGDFR_Pos (6UL) /*!< BSGTRGDFR (Bit 6) */ + #define R_GPT7_GTICBSR_BSGTRGDFR_Msk (0xc0UL) /*!< BSGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSCARBHL_Pos (8UL) /*!< BSCARBHL (Bit 8) */ + #define R_GPT7_GTICBSR_BSCARBHL_Msk (0x300UL) /*!< BSCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSCAFBHL_Pos (10UL) /*!< BSCAFBHL (Bit 10) */ + #define R_GPT7_GTICBSR_BSCAFBHL_Msk (0xc00UL) /*!< BSCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSCBRAHL_Pos (12UL) /*!< BSCBRAHL (Bit 12) */ + #define R_GPT7_GTICBSR_BSCBRAHL_Msk (0x3000UL) /*!< BSCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSCBFAHL_Pos (14UL) /*!< BSCBFAHL (Bit 14) */ + #define R_GPT7_GTICBSR_BSCBFAHL_Msk (0xc000UL) /*!< BSCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSELCA_Pos (16UL) /*!< BSELCA (Bit 16) */ + #define R_GPT7_GTICBSR_BSELCA_Msk (0x10000UL) /*!< BSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCB_Pos (17UL) /*!< BSELCB (Bit 17) */ + #define R_GPT7_GTICBSR_BSELCB_Msk (0x20000UL) /*!< BSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCC_Pos (18UL) /*!< BSELCC (Bit 18) */ + #define R_GPT7_GTICBSR_BSELCC_Msk (0x40000UL) /*!< BSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCD_Pos (19UL) /*!< BSELCD (Bit 19) */ + #define R_GPT7_GTICBSR_BSELCD_Msk (0x80000UL) /*!< BSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCE_Pos (20UL) /*!< BSELCE (Bit 20) */ + #define R_GPT7_GTICBSR_BSELCE_Msk (0x100000UL) /*!< BSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCF_Pos (21UL) /*!< BSELCF (Bit 21) */ + #define R_GPT7_GTICBSR_BSELCF_Msk (0x200000UL) /*!< BSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCG_Pos (22UL) /*!< BSELCG (Bit 22) */ + #define R_GPT7_GTICBSR_BSELCG_Msk (0x400000UL) /*!< BSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCH_Pos (23UL) /*!< BSELCH (Bit 23) */ + #define R_GPT7_GTICBSR_BSELCH_Msk (0x800000UL) /*!< BSELCH (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT7_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT7_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ + #define R_GPT7_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT7_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT7_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT7_GTCR_SWMD_Pos (29UL) /*!< SWMD (Bit 29) */ + #define R_GPT7_GTCR_SWMD_Msk (0xe0000000UL) /*!< SWMD (Bitfield-Mask: 0x07) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT7_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT7_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT7_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT7_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT7_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT7_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT7_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT7_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT7_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT7_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT7_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT7_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ + #define R_GPT7_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT7_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT7_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT7_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT7_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT7_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT7_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT7_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT7_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT7_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT7_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT7_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT7_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT7_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT7_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT7_GTINTAD_GTINTA_Pos (0UL) /*!< GTINTA (Bit 0) */ + #define R_GPT7_GTINTAD_GTINTA_Msk (0x1UL) /*!< GTINTA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTB_Pos (1UL) /*!< GTINTB (Bit 1) */ + #define R_GPT7_GTINTAD_GTINTB_Msk (0x2UL) /*!< GTINTB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTC_Pos (2UL) /*!< GTINTC (Bit 2) */ + #define R_GPT7_GTINTAD_GTINTC_Msk (0x4UL) /*!< GTINTC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTD_Pos (3UL) /*!< GTINTD (Bit 3) */ + #define R_GPT7_GTINTAD_GTINTD_Msk (0x8UL) /*!< GTINTD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTE_Pos (4UL) /*!< GTINTE (Bit 4) */ + #define R_GPT7_GTINTAD_GTINTE_Msk (0x10UL) /*!< GTINTE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTF_Pos (5UL) /*!< GTINTF (Bit 5) */ + #define R_GPT7_GTINTAD_GTINTF_Msk (0x20UL) /*!< GTINTF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT7_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTINTAD_ADTRAUEN_Pos (16UL) /*!< ADTRAUEN (Bit 16) */ + #define R_GPT7_GTINTAD_ADTRAUEN_Msk (0x10000UL) /*!< ADTRAUEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_ADTRADEN_Pos (17UL) /*!< ADTRADEN (Bit 17) */ + #define R_GPT7_GTINTAD_ADTRADEN_Msk (0x20000UL) /*!< ADTRADEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_ADTRBUEN_Pos (18UL) /*!< ADTRBUEN (Bit 18) */ + #define R_GPT7_GTINTAD_ADTRBUEN_Msk (0x40000UL) /*!< ADTRBUEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_ADTRBDEN_Pos (19UL) /*!< ADTRBDEN (Bit 19) */ + #define R_GPT7_GTINTAD_ADTRBDEN_Msk (0x80000UL) /*!< ADTRBDEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT7_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT7_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT7_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT7_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT7_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT7_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT7_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT7_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT7_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT7_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT7_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT7_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT7_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT7_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT7_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT7_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT7_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT7_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT7_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT7_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_DBRTECA_Pos (8UL) /*!< DBRTECA (Bit 8) */ + #define R_GPT7_GTBER_DBRTECA_Msk (0x100UL) /*!< DBRTECA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_DBRTECB_Pos (10UL) /*!< DBRTECB (Bit 10) */ + #define R_GPT7_GTBER_DBRTECB_Msk (0x400UL) /*!< DBRTECB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT7_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT7_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT7_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT7_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT7_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT7_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT7_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT7_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT7_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT7_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT7_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT7_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT7_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT7_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT7_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT7_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT7_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT7_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT7_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ +/* ========================================================= GTCCR ========================================================= */ +/* ========================================================= GTPR ========================================================== */ +/* ========================================================= GTPBR ========================================================= */ +/* ======================================================== GTPDBR ========================================================= */ +/* ======================================================== GTADTRA ======================================================== */ +/* ======================================================= GTADTBRA ======================================================== */ +/* ======================================================= GTADTDBRA ======================================================= */ +/* ======================================================== GTADTRB ======================================================== */ +/* ======================================================= GTADTBRB ======================================================== */ +/* ======================================================= GTADTDBRB ======================================================= */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT7_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT7_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT7_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT7_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT7_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ +/* ========================================================= GTDVD ========================================================= */ +/* ========================================================= GTDBU ========================================================= */ +/* ========================================================= GTDBD ========================================================= */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT7_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT7_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT7_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT7_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTADSMR ======================================================== */ + #define R_GPT7_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ + #define R_GPT7_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ + #define R_GPT7_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ + #define R_GPT7_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ + #define R_GPT7_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTEITC ========================================================= */ + #define R_GPT7_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ + #define R_GPT7_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ + #define R_GPT7_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT7_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ + #define R_GPT7_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT7_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ + #define R_GPT7_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ + #define R_GPT7_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ + #define R_GPT7_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ + #define R_GPT7_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ + #define R_GPT7_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ + #define R_GPT7_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= GTEITLI1 ======================================================== */ + #define R_GPT7_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ + #define R_GPT7_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ + #define R_GPT7_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ + #define R_GPT7_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ + #define R_GPT7_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ + #define R_GPT7_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ + #define R_GPT7_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ + #define R_GPT7_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ + #define R_GPT7_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ +/* ======================================================= GTEITLI2 ======================================================== */ + #define R_GPT7_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ + #define R_GPT7_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ + #define R_GPT7_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ +/* ======================================================== GTEITLB ======================================================== */ + #define R_GPT7_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ + #define R_GPT7_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ + #define R_GPT7_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ + #define R_GPT7_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ + #define R_GPT7_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ + #define R_GPT7_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ + #define R_GPT7_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ + #define R_GPT7_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT7_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT7_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT7_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT7_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT7_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT7_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT7_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT7_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT7_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT7_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT7_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ + #define R_GPT7_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ + #define R_GPT7_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT7_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT7_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ + #define R_GPT7_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ + #define R_GPT7_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSWSR ========================================================= */ + #define R_GPT7_GTSWSR_WSGTRGA_Pos (0UL) /*!< WSGTRGA (Bit 0) */ + #define R_GPT7_GTSWSR_WSGTRGA_Msk (0x3UL) /*!< WSGTRGA (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSWSR_WSGTRGB_Pos (2UL) /*!< WSGTRGB (Bit 2) */ + #define R_GPT7_GTSWSR_WSGTRGB_Msk (0xcUL) /*!< WSGTRGB (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSWSR_WSGTRGC_Pos (4UL) /*!< WSGTRGC (Bit 4) */ + #define R_GPT7_GTSWSR_WSGTRGC_Msk (0x30UL) /*!< WSGTRGC (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSWSR_WSGTRGD_Pos (6UL) /*!< WSGTRGD (Bit 6) */ + #define R_GPT7_GTSWSR_WSGTRGD_Msk (0xc0UL) /*!< WSGTRGD (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSWSR_WSELCA_Pos (16UL) /*!< WSELCA (Bit 16) */ + #define R_GPT7_GTSWSR_WSELCA_Msk (0x10000UL) /*!< WSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCB_Pos (17UL) /*!< WSELCB (Bit 17) */ + #define R_GPT7_GTSWSR_WSELCB_Msk (0x20000UL) /*!< WSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCC_Pos (18UL) /*!< WSELCC (Bit 18) */ + #define R_GPT7_GTSWSR_WSELCC_Msk (0x40000UL) /*!< WSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCD_Pos (19UL) /*!< WSELCD (Bit 19) */ + #define R_GPT7_GTSWSR_WSELCD_Msk (0x80000UL) /*!< WSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCE_Pos (20UL) /*!< WSELCE (Bit 20) */ + #define R_GPT7_GTSWSR_WSELCE_Msk (0x100000UL) /*!< WSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCF_Pos (21UL) /*!< WSELCF (Bit 21) */ + #define R_GPT7_GTSWSR_WSELCF_Msk (0x200000UL) /*!< WSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCG_Pos (22UL) /*!< WSELCG (Bit 22) */ + #define R_GPT7_GTSWSR_WSELCG_Msk (0x400000UL) /*!< WSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_CSELCH_Pos (23UL) /*!< CSELCH (Bit 23) */ + #define R_GPT7_GTSWSR_CSELCH_Msk (0x800000UL) /*!< CSELCH (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSWOS ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_RDR_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_RDR_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_RDR_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_RDR_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_FPER_Pos (11UL) /*!< FPER (Bit 11) */ + #define R_SCI0_RDR_FPER_Msk (0x800UL) /*!< FPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_FFER_Pos (12UL) /*!< FFER (Bit 12) */ + #define R_SCI0_RDR_FFER_Msk (0x1000UL) /*!< FFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI0_RDR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI0_RDR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI0_RDR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_TDR_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_TDR_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_TDR_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR0 ========================================================== */ + #define R_SCI0_CCR0_RE_Pos (0UL) /*!< RE (Bit 0) */ + #define R_SCI0_CCR0_RE_Msk (0x1UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_TE_Pos (4UL) /*!< TE (Bit 4) */ + #define R_SCI0_CCR0_TE_Msk (0x10UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_MPIE_Pos (8UL) /*!< MPIE (Bit 8) */ + #define R_SCI0_CCR0_MPIE_Msk (0x100UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_DCME_Pos (9UL) /*!< DCME (Bit 9) */ + #define R_SCI0_CCR0_DCME_Msk (0x200UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_IDSEL_Pos (10UL) /*!< IDSEL (Bit 10) */ + #define R_SCI0_CCR0_IDSEL_Msk (0x400UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_RIE_Pos (16UL) /*!< RIE (Bit 16) */ + #define R_SCI0_CCR0_RIE_Msk (0x10000UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_TIE_Pos (20UL) /*!< TIE (Bit 20) */ + #define R_SCI0_CCR0_TIE_Msk (0x100000UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_TEIE_Pos (21UL) /*!< TEIE (Bit 21) */ + #define R_SCI0_CCR0_TEIE_Msk (0x200000UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_SSE_Pos (24UL) /*!< SSE (Bit 24) */ + #define R_SCI0_CCR0_SSE_Msk (0x1000000UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR1 ========================================================== */ + #define R_SCI0_CCR1_CTSE_Pos (0UL) /*!< CTSE (Bit 0) */ + #define R_SCI0_CCR1_CTSE_Msk (0x1UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_CTSPEN_Pos (1UL) /*!< CTSPEN (Bit 1) */ + #define R_SCI0_CCR1_CTSPEN_Msk (0x2UL) /*!< CTSPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_SPB2DT_Pos (4UL) /*!< SPB2DT (Bit 4) */ + #define R_SCI0_CCR1_SPB2DT_Msk (0x10UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_SPB2IO_Pos (5UL) /*!< SPB2IO (Bit 5) */ + #define R_SCI0_CCR1_SPB2IO_Msk (0x20UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_PE_Pos (8UL) /*!< PE (Bit 8) */ + #define R_SCI0_CCR1_PE_Msk (0x100UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_PM_Pos (9UL) /*!< PM (Bit 9) */ + #define R_SCI0_CCR1_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_TINV_Pos (12UL) /*!< TINV (Bit 12) */ + #define R_SCI0_CCR1_TINV_Msk (0x1000UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_RINV_Pos (13UL) /*!< RINV (Bit 13) */ + #define R_SCI0_CCR1_RINV_Msk (0x2000UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SCI0_CCR1_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_SHARPS_Pos (20UL) /*!< SHARPS (Bit 20) */ + #define R_SCI0_CCR1_SHARPS_Msk (0x100000UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_NFCS_Pos (24UL) /*!< NFCS (Bit 24) */ + #define R_SCI0_CCR1_NFCS_Msk (0x7000000UL) /*!< NFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CCR1_NFEN_Pos (28UL) /*!< NFEN (Bit 28) */ + #define R_SCI0_CCR1_NFEN_Msk (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR2 ========================================================== */ + #define R_SCI0_CCR2_BCP_Pos (0UL) /*!< BCP (Bit 0) */ + #define R_SCI0_CCR2_BCP_Msk (0x7UL) /*!< BCP (Bitfield-Mask: 0x07) */ + #define R_SCI0_CCR2_BGDM_Pos (4UL) /*!< BGDM (Bit 4) */ + #define R_SCI0_CCR2_BGDM_Msk (0x10UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR2_ABCS_Pos (5UL) /*!< ABCS (Bit 5) */ + #define R_SCI0_CCR2_ABCS_Msk (0x20UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR2_ABCSE_Pos (6UL) /*!< ABCSE (Bit 6) */ + #define R_SCI0_CCR2_ABCSE_Msk (0x40UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR2_BRR_Pos (8UL) /*!< BRR (Bit 8) */ + #define R_SCI0_CCR2_BRR_Msk (0xff00UL) /*!< BRR (Bitfield-Mask: 0xff) */ + #define R_SCI0_CCR2_BRME_Pos (16UL) /*!< BRME (Bit 16) */ + #define R_SCI0_CCR2_BRME_Msk (0x10000UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR2_CKS_Pos (20UL) /*!< CKS (Bit 20) */ + #define R_SCI0_CCR2_CKS_Msk (0x300000UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CCR2_MDDR_Pos (24UL) /*!< MDDR (Bit 24) */ + #define R_SCI0_CCR2_MDDR_Msk (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR3 ========================================================== */ + #define R_SCI0_CCR3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SCI0_CCR3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SCI0_CCR3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_BPEN_Pos (7UL) /*!< BPEN (Bit 7) */ + #define R_SCI0_CCR3_BPEN_Msk (0x80UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_CHR_Pos (8UL) /*!< CHR (Bit 8) */ + #define R_SCI0_CCR3_CHR_Msk (0x300UL) /*!< CHR (Bitfield-Mask: 0x03) */ + #define R_SCI0_CCR3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SCI0_CCR3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_SINV_Pos (13UL) /*!< SINV (Bit 13) */ + #define R_SCI0_CCR3_SINV_Msk (0x2000UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_STP_Pos (14UL) /*!< STP (Bit 14) */ + #define R_SCI0_CCR3_STP_Msk (0x4000UL) /*!< STP (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_RXDESEL_Pos (15UL) /*!< RXDESEL (Bit 15) */ + #define R_SCI0_CCR3_RXDESEL_Msk (0x8000UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_MOD_Pos (16UL) /*!< MOD (Bit 16) */ + #define R_SCI0_CCR3_MOD_Msk (0x70000UL) /*!< MOD (Bitfield-Mask: 0x07) */ + #define R_SCI0_CCR3_MP_Pos (19UL) /*!< MP (Bit 19) */ + #define R_SCI0_CCR3_MP_Msk (0x80000UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_FM_Pos (20UL) /*!< FM (Bit 20) */ + #define R_SCI0_CCR3_FM_Msk (0x100000UL) /*!< FM (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_DEN_Pos (21UL) /*!< DEN (Bit 21) */ + #define R_SCI0_CCR3_DEN_Msk (0x200000UL) /*!< DEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_CKE_Pos (24UL) /*!< CKE (Bit 24) */ + #define R_SCI0_CCR3_CKE_Msk (0x3000000UL) /*!< CKE (Bitfield-Mask: 0x03) */ + #define R_SCI0_CCR3_GM_Pos (28UL) /*!< GM (Bit 28) */ + #define R_SCI0_CCR3_GM_Msk (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_BLK_Pos (29UL) /*!< BLK (Bit 29) */ + #define R_SCI0_CCR3_BLK_Msk (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR4 ========================================================== */ + #define R_SCI0_CCR4_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CCR4_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_CCR4_ASEN_Pos (16UL) /*!< ASEN (Bit 16) */ + #define R_SCI0_CCR4_ASEN_Msk (0x10000UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR4_ATEN_Pos (17UL) /*!< ATEN (Bit 17) */ + #define R_SCI0_CCR4_ATEN_Msk (0x20000UL) /*!< ATEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR4_AST_Pos (24UL) /*!< AST (Bit 24) */ + #define R_SCI0_CCR4_AST_Msk (0x7000000UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_CCR4_AJD_Pos (27UL) /*!< AJD (Bit 27) */ + #define R_SCI0_CCR4_AJD_Msk (0x8000000UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR4_ATT_Pos (28UL) /*!< ATT (Bit 28) */ + #define R_SCI0_CCR4_ATT_Msk (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_CCR4_AET_Pos (31UL) /*!< AET (Bit 31) */ + #define R_SCI0_CCR4_AET_Msk (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_IICDL_Pos (0UL) /*!< IICDL (Bit 0) */ + #define R_SCI0_ICR_IICDL_Msk (0x1fUL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_ICR_IICINTM_Pos (8UL) /*!< IICINTM (Bit 8) */ + #define R_SCI0_ICR_IICINTM_Msk (0x100UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICCSC_Pos (9UL) /*!< IICCSC (Bit 9) */ + #define R_SCI0_ICR_IICCSC_Msk (0x200UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICACKT_Pos (13UL) /*!< IICACKT (Bit 13) */ + #define R_SCI0_ICR_IICACKT_Msk (0x2000UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICSTAREQ_Pos (16UL) /*!< IICSTAREQ (Bit 16) */ + #define R_SCI0_ICR_IICSTAREQ_Msk (0x10000UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICRSTAREQ_Pos (17UL) /*!< IICRSTAREQ (Bit 17) */ + #define R_SCI0_ICR_IICRSTAREQ_Msk (0x20000UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICSTPREQ_Pos (18UL) /*!< IICSTPREQ (Bit 18) */ + #define R_SCI0_ICR_IICSTPREQ_Msk (0x40000UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICSDAS_Pos (20UL) /*!< IICSDAS (Bit 20) */ + #define R_SCI0_ICR_IICSDAS_Msk (0x300000UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_ICR_IICSCLS_Pos (22UL) /*!< IICSCLS (Bit 22) */ + #define R_SCI0_ICR_IICSCLS_Msk (0xc00000UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_DRES_Pos (0UL) /*!< DRES (Bit 0) */ + #define R_SCI0_FCR_DRES_Msk (0x1UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SCI0_FCR_TTRG_Msk (0x1f00UL) /*!< TTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FCR_TFRST_Pos (15UL) /*!< TFRST (Bit 15) */ + #define R_SCI0_FCR_TFRST_Msk (0x8000UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RTRG_Pos (16UL) /*!< RTRG (Bit 16) */ + #define R_SCI0_FCR_RTRG_Msk (0x1f0000UL) /*!< RTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FCR_RFRST_Pos (23UL) /*!< RFRST (Bit 23) */ + #define R_SCI0_FCR_RFRST_Msk (0x800000UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RSTRG_Pos (24UL) /*!< RSTRG (Bit 24) */ + #define R_SCI0_FCR_RSTRG_Msk (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f) */ +/* ========================================================== DCR ========================================================== */ + #define R_SCI0_DCR_DEPOL_Pos (0UL) /*!< DEPOL (Bit 0) */ + #define R_SCI0_DCR_DEPOL_Msk (0x1UL) /*!< DEPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCR_DEAST_Pos (8UL) /*!< DEAST (Bit 8) */ + #define R_SCI0_DCR_DEAST_Msk (0x1f00UL) /*!< DEAST (Bitfield-Mask: 0x1f) */ + #define R_SCI0_DCR_DENGT_Pos (16UL) /*!< DENGT (Bit 16) */ + #define R_SCI0_DCR_DENGT_Msk (0x1f0000UL) /*!< DENGT (Bitfield-Mask: 0x1f) */ +/* ========================================================== CSR ========================================================== */ + #define R_SCI0_CSR_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_CSR_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_RXDMON_Pos (15UL) /*!< RXDMON (Bit 15) */ + #define R_SCI0_CSR_RXDMON_Msk (0x8000UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_DCMF_Pos (16UL) /*!< DCMF (Bit 16) */ + #define R_SCI0_CSR_DCMF_Msk (0x10000UL) /*!< DCMF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_DPER_Pos (17UL) /*!< DPER (Bit 17) */ + #define R_SCI0_CSR_DPER_Msk (0x20000UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_DFER_Pos (18UL) /*!< DFER (Bit 18) */ + #define R_SCI0_CSR_DFER_Msk (0x40000UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI0_CSR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_MFF_Pos (26UL) /*!< MFF (Bit 26) */ + #define R_SCI0_CSR_MFF_Msk (0x4000000UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI0_CSR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI0_CSR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_TDRE_Pos (29UL) /*!< TDRE (Bit 29) */ + #define R_SCI0_CSR_TDRE_Msk (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_TEND_Pos (30UL) /*!< TEND (Bit 30) */ + #define R_SCI0_CSR_TEND_Msk (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_RDRF_Pos (31UL) /*!< RDRF (Bit 31) */ + #define R_SCI0_CSR_RDRF_Msk (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ + #define R_SCI0_ISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_ISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ + #define R_SCI0_ISR_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_ISR_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ +/* ========================================================= FRSR ========================================================== */ + #define R_SCI0_FRSR_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_FRSR_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRSR_R_Pos (8UL) /*!< R (Bit 8) */ + #define R_SCI0_FRSR_R_Msk (0x3f00UL) /*!< R (Bitfield-Mask: 0x3f) */ + #define R_SCI0_FRSR_PNUM_Pos (16UL) /*!< PNUM (Bit 16) */ + #define R_SCI0_FRSR_PNUM_Msk (0x3f0000UL) /*!< PNUM (Bitfield-Mask: 0x3f) */ + #define R_SCI0_FRSR_FNUM_Pos (24UL) /*!< FNUM (Bit 24) */ + #define R_SCI0_FRSR_FNUM_Msk (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f) */ +/* ========================================================= FTSR ========================================================== */ + #define R_SCI0_FTSR_T_Pos (0UL) /*!< T (Bit 0) */ + #define R_SCI0_FTSR_T_Msk (0x3fUL) /*!< T (Bitfield-Mask: 0x3f) */ +/* ========================================================= CFCLR ========================================================= */ + #define R_SCI0_CFCLR_ERSC_Pos (4UL) /*!< ERSC (Bit 4) */ + #define R_SCI0_CFCLR_ERSC_Msk (0x10UL) /*!< ERSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_DCMFC_Pos (16UL) /*!< DCMFC (Bit 16) */ + #define R_SCI0_CFCLR_DCMFC_Msk (0x10000UL) /*!< DCMFC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_DPERC_Pos (17UL) /*!< DPERC (Bit 17) */ + #define R_SCI0_CFCLR_DPERC_Msk (0x20000UL) /*!< DPERC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_DFERC_Pos (18UL) /*!< DFERC (Bit 18) */ + #define R_SCI0_CFCLR_DFERC_Msk (0x40000UL) /*!< DFERC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_ORERC_Pos (24UL) /*!< ORERC (Bit 24) */ + #define R_SCI0_CFCLR_ORERC_Msk (0x1000000UL) /*!< ORERC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_MFFC_Pos (26UL) /*!< MFFC (Bit 26) */ + #define R_SCI0_CFCLR_MFFC_Msk (0x4000000UL) /*!< MFFC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_PERC_Pos (27UL) /*!< PERC (Bit 27) */ + #define R_SCI0_CFCLR_PERC_Msk (0x8000000UL) /*!< PERC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_FERC_Pos (28UL) /*!< FERC (Bit 28) */ + #define R_SCI0_CFCLR_FERC_Msk (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_TDREC_Pos (29UL) /*!< TDREC (Bit 29) */ + #define R_SCI0_CFCLR_TDREC_Msk (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_RDRFC_Pos (31UL) /*!< RDRFC (Bit 31) */ + #define R_SCI0_CFCLR_RDRFC_Msk (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01) */ +/* ======================================================== ICFCLR ========================================================= */ + #define R_SCI0_ICFCLR_IICSTIFC_Pos (3UL) /*!< IICSTIFC (Bit 3) */ + #define R_SCI0_ICFCLR_IICSTIFC_Msk (0x8UL) /*!< IICSTIFC (Bitfield-Mask: 0x01) */ +/* ========================================================= FFCLR ========================================================= */ + #define R_SCI0_FFCLR_DRC_Pos (0UL) /*!< DRC (Bit 0) */ + #define R_SCI0_FFCLR_DRC_Msk (0x1UL) /*!< DRC (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPDR ========================================================== */ + #define R_SPI0_SPDR_SPD_Pos (0UL) /*!< SPD (Bit 0) */ + #define R_SPI0_SPDR_SPD_Msk (0xffffffffUL) /*!< SPD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= MRCKD ========================================================= */ + #define R_SPI0_MRCKD_ARST_Pos (0UL) /*!< ARST (Bit 0) */ + #define R_SPI0_MRCKD_ARST_Msk (0x7UL) /*!< ARST (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPE_Pos (0UL) /*!< SPE (Bit 0) */ + #define R_SPI0_SPCR_SPE_Msk (0x1UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPSCKSEL_Pos (7UL) /*!< SPSCKSEL (Bit 7) */ + #define R_SPI0_SPCR_SPSCKSEL_Msk (0x80UL) /*!< SPSCKSEL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPPE_Pos (8UL) /*!< SPPE (Bit 8) */ + #define R_SPI0_SPCR_SPPE_Msk (0x100UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPOE_Pos (9UL) /*!< SPOE (Bit 9) */ + #define R_SPI0_SPCR_SPOE_Msk (0x200UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_PTE_Pos (11UL) /*!< PTE (Bit 11) */ + #define R_SPI0_SPCR_PTE_Msk (0x800UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SCKASE_Pos (12UL) /*!< SCKASE (Bit 12) */ + #define R_SPI0_SPCR_SCKASE_Msk (0x1000UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_BFDS_Pos (13UL) /*!< BFDS (Bit 13) */ + #define R_SPI0_SPCR_BFDS_Msk (0x2000UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (14UL) /*!< MODFEN (Bit 14) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4000UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (16UL) /*!< SPEIE (Bit 16) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10000UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPRIE_Pos (17UL) /*!< SPRIE (Bit 17) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x20000UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPIIE_Pos (18UL) /*!< SPIIE (Bit 18) */ + #define R_SPI0_SPCR_SPIIE_Msk (0x40000UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPDRES_Pos (19UL) /*!< SPDRES (Bit 19) */ + #define R_SPI0_SPCR_SPDRES_Msk (0x80000UL) /*!< SPDRES (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (20UL) /*!< SPTIE (Bit 20) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x100000UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_CENDIE_Pos (21UL) /*!< CENDIE (Bit 21) */ + #define R_SPI0_SPCR_CENDIE_Msk (0x200000UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (24UL) /*!< SPMS (Bit 24) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1000000UL) /*!< SPMS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPFRF_Pos (25UL) /*!< SPFRF (Bit 25) */ + #define R_SPI0_SPCR_SPFRF_Msk (0x2000000UL) /*!< SPFRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (28UL) /*!< TXMD (Bit 28) */ + #define R_SPI0_SPCR_TXMD_Msk (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCR_MSTR_Pos (30UL) /*!< MSTR (Bit 30) */ + #define R_SPI0_SPCR_MSTR_Msk (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_BPEN_Pos (31UL) /*!< BPEN (Bit 31) */ + #define R_SPI0_SPCR_BPEN_Msk (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SPCRRM ========================================================= */ + #define R_SPI0_SPCRRM_RMFM_Pos (0UL) /*!< RMFM (Bit 0) */ + #define R_SPI0_SPCRRM_RMFM_Msk (0x1fUL) /*!< RMFM (Bitfield-Mask: 0x1f) */ + #define R_SPI0_SPCRRM_RMEDTG_Pos (6UL) /*!< RMEDTG (Bit 6) */ + #define R_SPI0_SPCRRM_RMEDTG_Msk (0x40UL) /*!< RMEDTG (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCRRM_RMSTTG_Pos (7UL) /*!< RMSTTG (Bit 7) */ + #define R_SPI0_SPCRRM_RMSTTG_Msk (0x80UL) /*!< RMSTTG (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDRCR ========================================================= */ + #define R_SPI0_SPDRCR_SPDRC_Pos (0UL) /*!< SPDRC (Bit 0) */ + #define R_SPI0_SPDRCR_SPDRC_Msk (0xffUL) /*!< SPDRC (Bitfield-Mask: 0xff) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPOM_Pos (2UL) /*!< SPOM (Bit 2) */ + #define R_SPI0_SPPCR_SPOM_Msk (0x4UL) /*!< SPOM (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SPSCKDL_Pos (0UL) /*!< SPSCKDL (Bit 0) */ + #define R_SPI0_SPCR2_SPSCKDL_Msk (0x7UL) /*!< SPSCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI0_SPCMD_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI0_SPCMD_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x3000000UL) /*!< SSLA (Bitfield-Mask: 0x03) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SLSEL_Pos (1UL) /*!< SLSEL (Bit 1) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0x6UL) /*!< SLSEL (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (3UL) /*!< SPRDTD (Bit 3) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x8UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SINV_Pos (4UL) /*!< SINV (Bit 4) */ + #define R_SPI0_SPDCR_SINV_Msk (0x10UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (8UL) /*!< SPFC (Bit 8) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x300UL) /*!< SPFC (Bitfield-Mask: 0x03) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_RTRG_Pos (0UL) /*!< RTRG (Bit 0) */ + #define R_SPI0_SPDCR2_RTRG_Msk (0x3UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR2_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SPI0_SPDCR2_TTRG_Msk (0x300UL) /*!< TTRG (Bitfield-Mask: 0x03) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPDRF_Pos (7UL) /*!< SPDRF (Bit 7) */ + #define R_SPI0_SPSR_SPDRF_Msk (0x80UL) /*!< SPDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (8UL) /*!< OVRF (Bit 8) */ + #define R_SPI0_SPSR_OVRF_Msk (0x100UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (9UL) /*!< IDLNF (Bit 9) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x200UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (10UL) /*!< MODF (Bit 10) */ + #define R_SPI0_SPSR_MODF_Msk (0x400UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (11UL) /*!< PERF (Bit 11) */ + #define R_SPI0_SPSR_PERF_Msk (0x800UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (12UL) /*!< UDRF (Bit 12) */ + #define R_SPI0_SPSR_UDRF_Msk (0x1000UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (13UL) /*!< SPTEF (Bit 13) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x2000UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (14UL) /*!< CENDF (Bit 14) */ + #define R_SPI0_SPSR_CENDF_Msk (0x4000UL) /*!< CENDF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPRF_Pos (15UL) /*!< SPRF (Bit 15) */ + #define R_SPI0_SPSR_SPRF_Msk (0x8000UL) /*!< SPRF (Bitfield-Mask: 0x01) */ +/* ======================================================== SPTFSR ========================================================= */ + #define R_SPI0_SPTFSR_TFDN_Pos (0UL) /*!< TFDN (Bit 0) */ + #define R_SPI0_SPTFSR_TFDN_Msk (0x7UL) /*!< TFDN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPRFSR ========================================================= */ + #define R_SPI0_SPRFSR_RFDN_Pos (0UL) /*!< RFDN (Bit 0) */ + #define R_SPI0_SPRFSR_RFDN_Msk (0x7UL) /*!< RFDN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPPSR ========================================================= */ + #define R_SPI0_SPPSR_SPEPS_Pos (0UL) /*!< SPEPS (Bit 0) */ + #define R_SPI0_SPPSR_SPEPS_Msk (0x1UL) /*!< SPEPS (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSRC ========================================================= */ + #define R_SPI0_SPSRC_SPDRFC_Pos (7UL) /*!< SPDRFC (Bit 7) */ + #define R_SPI0_SPSRC_SPDRFC_Msk (0x80UL) /*!< SPDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_OVRFC_Pos (8UL) /*!< OVRFC (Bit 8) */ + #define R_SPI0_SPSRC_OVRFC_Msk (0x100UL) /*!< OVRFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_MODFC_Pos (10UL) /*!< MODFC (Bit 10) */ + #define R_SPI0_SPSRC_MODFC_Msk (0x400UL) /*!< MODFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_PERFC_Pos (11UL) /*!< PERFC (Bit 11) */ + #define R_SPI0_SPSRC_PERFC_Msk (0x800UL) /*!< PERFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_UDRFC_Pos (12UL) /*!< UDRFC (Bit 12) */ + #define R_SPI0_SPSRC_UDRFC_Msk (0x1000UL) /*!< UDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_SPTEFC_Pos (13UL) /*!< SPTEFC (Bit 13) */ + #define R_SPI0_SPSRC_SPTEFC_Msk (0x2000UL) /*!< SPTEFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_CENDFC_Pos (14UL) /*!< CENDFC (Bit 14) */ + #define R_SPI0_SPSRC_CENDFC_Msk (0x4000UL) /*!< CENDFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_SPRFC_Pos (15UL) /*!< SPRFC (Bit 15) */ + #define R_SPI0_SPSRC_SPRFC_Msk (0x8000UL) /*!< SPRFC (Bitfield-Mask: 0x01) */ +/* ========================================================= SPFCR ========================================================= */ + #define R_SPI0_SPFCR_SPFRST_Pos (0UL) /*!< SPFRST (Bit 0) */ + #define R_SPI0_SPFCR_SPFRST_Msk (0x1UL) /*!< SPFRST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC0_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC0_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ + #define R_CRC0_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC0_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC0_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC0_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ +/* ======================================================= CRCDIR_BY ======================================================= */ +/* ======================================================== CRCDOR ========================================================= */ +/* ======================================================= CRCDOR_HA ======================================================= */ +/* ======================================================= CRCDOR_BY ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGIPV ======================================================== */ + #define R_CANFD_CFDGIPV_IPV_Pos (0UL) /*!< IPV (Bit 0) */ + #define R_CANFD_CFDGIPV_IPV_Msk (0xffUL) /*!< IPV (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDGIPV_IPT_Pos (8UL) /*!< IPT (Bit 8) */ + #define R_CANFD_CFDGIPV_IPT_Msk (0x300UL) /*!< IPT (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGIPV_PSI_Pos (16UL) /*!< PSI (Bit 16) */ + #define R_CANFD_CFDGIPV_PSI_Msk (0x3fff0000UL) /*!< PSI (Bitfield-Mask: 0x3fff) */ +/* ======================================================== CFDGCFG ======================================================== */ + #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ + #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ + #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ + #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ + #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ + #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ + #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ + #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ + #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSBTCS_Pos (13UL) /*!< TSBTCS (Bit 13) */ + #define R_CANFD_CFDGCFG_TSBTCS_Msk (0xe000UL) /*!< TSBTCS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ + #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ + #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ + #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ + #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ + #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ + #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ + #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_QOWEIE_Pos (12UL) /*!< QOWEIE (Bit 12) */ + #define R_CANFD_CFDGCTR_QOWEIE_Msk (0x1000UL) /*!< QOWEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_QMEIE_Pos (14UL) /*!< QMEIE (Bit 14) */ + #define R_CANFD_CFDGCTR_QMEIE_Msk (0x4000UL) /*!< QMEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MOWEIE_Pos (15UL) /*!< MOWEIE (Bit 15) */ + #define R_CANFD_CFDGCTR_MOWEIE_Msk (0x8000UL) /*!< MOWEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ + #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ + #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ + #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ + #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ + #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ + #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ + #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ + #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_QOWES_Pos (4UL) /*!< QOWES (Bit 4) */ + #define R_CANFD_CFDGERFL_QOWES_Msk (0x10UL) /*!< QOWES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_QMES_Pos (6UL) /*!< QMES (Bit 6) */ + #define R_CANFD_CFDGERFL_QMES_Msk (0x40UL) /*!< QMES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MOWES_Pos (7UL) /*!< MOWES (Bit 7) */ + #define R_CANFD_CFDGERFL_MOWES_Msk (0x80UL) /*!< MOWES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ + #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF1_Pos (17UL) /*!< EEF1 (Bit 17) */ + #define R_CANFD_CFDGERFL_EEF1_Msk (0x20000UL) /*!< EEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ + #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ + #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ + #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ + #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ + #define R_CANFD_CFDRMND0_RMNS_Pos (0UL) /*!< RMNS (Bit 0) */ + #define R_CANFD_CFDRMND0_RMNS_Msk (0xffffffffUL) /*!< RMNS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ + #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ + #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ + #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ + #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ + #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ + #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFFIE_Pos (16UL) /*!< RFFIE (Bit 16) */ + #define R_CANFD_CFDRFCC_RFFIE_Msk (0x10000UL) /*!< RFFIE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFSTS ======================================================== */ + #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ + #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ + #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ + #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ + #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ + #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRFSTS_RFFIF_Pos (16UL) /*!< RFFIF (Bit 16) */ + #define R_CANFD_CFDRFSTS_RFFIF_Msk (0x10000UL) /*!< RFFIF (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFPCTR ======================================================= */ + #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ + #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ + #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ + #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ + #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ + #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ + #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ + #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ + #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ + #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ + #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ + #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ + #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFCCE ======================================================== */ + #define R_CANFD_CFDCFCCE_CFFIE_Pos (0UL) /*!< CFFIE (Bit 0) */ + #define R_CANFD_CFDCFCCE_CFFIE_Msk (0x1UL) /*!< CFFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos (1UL) /*!< CFOFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk (0x2UL) /*!< CFOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos (2UL) /*!< CFOFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk (0x4UL) /*!< CFOFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFMOWM_Pos (8UL) /*!< CFMOWM (Bit 8) */ + #define R_CANFD_CFDCFCCE_CFMOWM_Msk (0x100UL) /*!< CFMOWM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFBME_Pos (16UL) /*!< CFBME (Bit 16) */ + #define R_CANFD_CFDCFCCE_CFBME_Msk (0x10000UL) /*!< CFBME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCFSTS ======================================================== */ + #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ + #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ + #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ + #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ + #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDCFSTS_CFFIF_Pos (16UL) /*!< CFFIF (Bit 16) */ + #define R_CANFD_CFDCFSTS_CFFIF_Msk (0x10000UL) /*!< CFFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos (17UL) /*!< CFOFRXIF (Bit 17) */ + #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk (0x20000UL) /*!< CFOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos (18UL) /*!< CFOFTXIF (Bit 18) */ + #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk (0x40000UL) /*!< CFOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMOW_Pos (24UL) /*!< CFMOW (Bit 24) */ + #define R_CANFD_CFDCFSTS_CFMOW_Msk (0x1000000UL) /*!< CFMOW (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCFPCTR ======================================================= */ + #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ + #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ + #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ + #define R_CANFD_CFDFESTS_RFXEMP_Msk (0xffUL) /*!< RFXEMP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ + #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x3f00UL) /*!< CFXEMP (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFFSTS ======================================================== */ + #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ + #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0xffUL) /*!< RFXFLL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x3f00UL) /*!< CFXFLL (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFMSTS ======================================================== */ + #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ + #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0xffUL) /*!< RFXMLT (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x3f00UL) /*!< CFXMLT (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDRFISTS ======================================================= */ + #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0xffUL) /*!< RFXIF (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRFISTS_RFXFFLL_Pos (16UL) /*!< RFXFFLL (Bit 16) */ + #define R_CANFD_CFDRFISTS_RFXFFLL_Msk (0xff0000UL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDCFRISTS ======================================================= */ + #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos (0UL) /*!< CFXRXIF (Bit 0) */ + #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk (0x3fUL) /*!< CFXRXIF (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDCFTISTS ======================================================= */ + #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos (0UL) /*!< CFXTXIF (Bit 0) */ + #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk (0x3fUL) /*!< CFXTXIF (Bitfield-Mask: 0x3f) */ +/* ===================================================== CFDCFOFRISTS ====================================================== */ + #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos (0UL) /*!< CFXOFRXIF (Bit 0) */ + #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk (0x3fUL) /*!< CFXOFRXIF (Bitfield-Mask: 0x3f) */ +/* ===================================================== CFDCFOFTISTS ====================================================== */ + #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos (0UL) /*!< CFXOFTXIF (Bit 0) */ + #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk (0x3fUL) /*!< CFXOFTXIF (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDCFMOWSTS ====================================================== */ + #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos (0UL) /*!< CFXMOW (Bit 0) */ + #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk (0x3fUL) /*!< CFXMOW (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFFFSTS ======================================================= */ + #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos (0UL) /*!< RFXFFLL (Bit 0) */ + #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk (0xffUL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos (8UL) /*!< CFXFFLL (Bit 8) */ + #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk (0x3f00UL) /*!< CFXFFLL (Bitfield-Mask: 0x3f) */ +/* ======================================================== CFDTMC ========================================================= */ + #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ + #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ + #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ + #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ + #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ + #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ + #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ + #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ + #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ + #define R_CANFD_CFDTMTRSTS_TMTRSTS_Pos (0UL) /*!< TMTRSTS (Bit 0) */ + #define R_CANFD_CFDTMTRSTS_TMTRSTS_Msk (0xffffUL) /*!< TMTRSTS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ + #define R_CANFD_CFDTMTARSTS_TMTARSTS_Pos (0UL) /*!< TMTARSTS (Bit 0) */ + #define R_CANFD_CFDTMTARSTS_TMTARSTS_Msk (0xffffUL) /*!< TMTARSTS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ + #define R_CANFD_CFDTMTCSTS_TMTCSTS_Pos (0UL) /*!< TMTCSTS (Bit 0) */ + #define R_CANFD_CFDTMTCSTS_TMTCSTS_Msk (0xffffUL) /*!< TMTCSTS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDTMTASTS ======================================================= */ + #define R_CANFD_CFDTMTASTS_TMTASTS_Pos (0UL) /*!< TMTASTS (Bit 0) */ + #define R_CANFD_CFDTMTASTS_TMTASTS_Msk (0xffffUL) /*!< TMTASTS (Bitfield-Mask: 0xffff) */ +/* ======================================================= CFDTMIEC ======================================================== */ + #define R_CANFD_CFDTMIEC_TMIE_Pos (0UL) /*!< TMIE (Bit 0) */ + #define R_CANFD_CFDTMIEC_TMIE_Msk (0xffffUL) /*!< TMIE (Bitfield-Mask: 0xffff) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ + #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC0_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ + #define R_CANFD_CFDTXQCC0_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC0_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC0_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ + #define R_CANFD_CFDTXQSTS0_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC1 ======================================================= */ + #define R_CANFD_CFDTXQCC1_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC1_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC1_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ + #define R_CANFD_CFDTXQCC1_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC1_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC1_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC1_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC1_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS1 ======================================================= */ + #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS1_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ + #define R_CANFD_CFDTXQSTS1_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR1 ====================================================== */ + #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC2 ======================================================= */ + #define R_CANFD_CFDTXQCC2_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC2_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC2_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ + #define R_CANFD_CFDTXQCC2_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC2_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC2_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC2_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC2_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS2 ======================================================= */ + #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS2_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ + #define R_CANFD_CFDTXQSTS2_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR2 ====================================================== */ + #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC3 ======================================================= */ + #define R_CANFD_CFDTXQCC3_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC3_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ + #define R_CANFD_CFDTXQCC3_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC3_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC3_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS3 ======================================================= */ + #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS3_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ + #define R_CANFD_CFDTXQSTS3_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR3 ====================================================== */ + #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTXQESTS ======================================================= */ + #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos (0UL) /*!< TXQxEMP (Bit 0) */ + #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk (0xffUL) /*!< TXQxEMP (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTXQFISTS ====================================================== */ + #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos (0UL) /*!< TXQ0FULL (Bit 0) */ + #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk (0x7UL) /*!< TXQ0FULL (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos (4UL) /*!< TXQ1FULL (Bit 4) */ + #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk (0x70UL) /*!< TXQ1FULL (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQMSTS ======================================================= */ + #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos (0UL) /*!< TXQ0ML (Bit 0) */ + #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk (0x7UL) /*!< TXQ0ML (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos (4UL) /*!< TXQ1ML (Bit 4) */ + #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk (0x70UL) /*!< TXQ1ML (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQISTS ======================================================= */ + #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos (0UL) /*!< TXQ0ISF (Bit 0) */ + #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk (0xfUL) /*!< TXQ0ISF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos (4UL) /*!< TXQ1ISF (Bit 4) */ + #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk (0xf0UL) /*!< TXQ1ISF (Bitfield-Mask: 0x0f) */ +/* ===================================================== CFDTXQOFTISTS ===================================================== */ + #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos (0UL) /*!< TXQ0OFTISF (Bit 0) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk (0xfUL) /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos (4UL) /*!< TXQ1OFTISF (Bit 4) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk (0xf0UL) /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f) */ +/* ===================================================== CFDTXQOFRISTS ===================================================== */ + #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos (0UL) /*!< TXQ0OFRISF (Bit 0) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk (0x7UL) /*!< TXQ0OFRISF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos (4UL) /*!< TXQ1OFRISF (Bit 4) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk (0x70UL) /*!< TXQ1OFRISF (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQFSTS ======================================================= */ + #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos (0UL) /*!< TXQ0FSF (Bit 0) */ + #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk (0xfUL) /*!< TXQ0FSF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos (4UL) /*!< TXQ1FSF (Bit 4) */ + #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk (0xf0UL) /*!< TXQ1FSF (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTHLCC ======================================================== */ + #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ + #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ + #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ + #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ + #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDGE_Pos (11UL) /*!< THLDGE (Bit 11) */ + #define R_CANFD_CFDTHLCC_THLDGE_Msk (0x800UL) /*!< THLDGE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ + #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ + #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ + #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ + #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ + #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ + #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ + #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos (5UL) /*!< TQOFIF0 (Bit 5) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk (0x20UL) /*!< TQOFIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos (6UL) /*!< CFOTIF0 (Bit 6) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk (0x40UL) /*!< CFOTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos (8UL) /*!< TSIF1 (Bit 8) */ + #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk (0x100UL) /*!< TSIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos (9UL) /*!< TAIF1 (Bit 9) */ + #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk (0x200UL) /*!< TAIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos (10UL) /*!< TQIF1 (Bit 10) */ + #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk (0x400UL) /*!< TQIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos (11UL) /*!< CFTIF1 (Bit 11) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk (0x800UL) /*!< CFTIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF1_Pos (12UL) /*!< THIF1 (Bit 12) */ + #define R_CANFD_CFDGTINTSTS0_THIF1_Msk (0x1000UL) /*!< THIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos (13UL) /*!< TQOFIF1 (Bit 13) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk (0x2000UL) /*!< TQOFIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos (14UL) /*!< CFOTIF1 (Bit 14) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk (0x4000UL) /*!< CFOTIF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ + #define R_CANFD_CFDGTSTCFG_C0ICBCE_Pos (0UL) /*!< C0ICBCE (Bit 0) */ + #define R_CANFD_CFDGTSTCFG_C0ICBCE_Msk (0x1UL) /*!< C0ICBCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTSTCFG_C1ICBCE_Pos (1UL) /*!< C1ICBCE (Bit 1) */ + #define R_CANFD_CFDGTSTCFG_C1ICBCE_Msk (0x2UL) /*!< C1ICBCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ + #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos (0UL) /*!< ICBCTME (Bit 0) */ + #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk (0x1UL) /*!< ICBCTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ + #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ + #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ + #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ======================================================= CFDGLOCKK ======================================================= */ + #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ======================================================= CFDCDTCT ======================================================== */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE2_Pos (2UL) /*!< RFDMAE2 (Bit 2) */ + #define R_CANFD_CFDCDTCT_RFDMAE2_Msk (0x4UL) /*!< RFDMAE2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE3_Pos (3UL) /*!< RFDMAE3 (Bit 3) */ + #define R_CANFD_CFDCDTCT_RFDMAE3_Msk (0x8UL) /*!< RFDMAE3 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE4_Pos (4UL) /*!< RFDMAE4 (Bit 4) */ + #define R_CANFD_CFDCDTCT_RFDMAE4_Msk (0x10UL) /*!< RFDMAE4 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE5_Pos (5UL) /*!< RFDMAE5 (Bit 5) */ + #define R_CANFD_CFDCDTCT_RFDMAE5_Msk (0x20UL) /*!< RFDMAE5 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE6_Pos (6UL) /*!< RFDMAE6 (Bit 6) */ + #define R_CANFD_CFDCDTCT_RFDMAE6_Msk (0x40UL) /*!< RFDMAE6 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE7_Pos (7UL) /*!< RFDMAE7 (Bit 7) */ + #define R_CANFD_CFDCDTCT_RFDMAE7_Msk (0x80UL) /*!< RFDMAE7 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE1_Pos (9UL) /*!< CFDMAE1 (Bit 9) */ + #define R_CANFD_CFDCDTCT_CFDMAE1_Msk (0x200UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos (2UL) /*!< RFDMASTS2 (Bit 2) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk (0x4UL) /*!< RFDMASTS2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos (3UL) /*!< RFDMASTS3 (Bit 3) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk (0x8UL) /*!< RFDMASTS3 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos (4UL) /*!< RFDMASTS4 (Bit 4) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk (0x10UL) /*!< RFDMASTS4 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos (5UL) /*!< RFDMASTS5 (Bit 5) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk (0x20UL) /*!< RFDMASTS5 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos (6UL) /*!< RFDMASTS6 (Bit 6) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk (0x40UL) /*!< RFDMASTS6 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos (7UL) /*!< RFDMASTS7 (Bit 7) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk (0x80UL) /*!< RFDMASTS7 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos (9UL) /*!< CFDMASTS1 (Bit 9) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk (0x200UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTTCT ======================================================= */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos (0UL) /*!< TQ0DMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk (0x1UL) /*!< TQ0DMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos (1UL) /*!< TQ0DMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk (0x2UL) /*!< TQ0DMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos (8UL) /*!< TQ3DMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk (0x100UL) /*!< TQ3DMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos (9UL) /*!< TQ3DMAE1 (Bit 9) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk (0x200UL) /*!< TQ3DMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos (16UL) /*!< CFDMAE0 (Bit 16) */ + #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk (0x10000UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos (17UL) /*!< CFDMAE1 (Bit 17) */ + #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk (0x20000UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDCDTTSTS ======================================================= */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos (0UL) /*!< TQ0DMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk (0x1UL) /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos (1UL) /*!< TQ0DMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk (0x2UL) /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos (8UL) /*!< TQ3DMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk (0x100UL) /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos (9UL) /*!< TQ3DMASTS1 (Bit 9) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk (0x200UL) /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos (16UL) /*!< CFDMASTS0 (Bit 16) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk (0x10000UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos (17UL) /*!< CFDMASTS1 (Bit 17) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk (0x20000UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGRINTSTS ====================================================== */ + #define R_CANFD_CFDGRINTSTS_QFIF_Pos (0UL) /*!< QFIF (Bit 0) */ + #define R_CANFD_CFDGRINTSTS_QFIF_Msk (0x7UL) /*!< QFIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_BQFIF_Pos (4UL) /*!< BQFIF (Bit 4) */ + #define R_CANFD_CFDGRINTSTS_BQFIF_Msk (0x30UL) /*!< BQFIF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos (8UL) /*!< QOFRIF (Bit 8) */ + #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk (0x700UL) /*!< QOFRIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_BQOFRIF_Pos (12UL) /*!< BQOFRIF (Bit 12) */ + #define R_CANFD_CFDGRINTSTS_BQOFRIF_Msk (0x3000UL) /*!< BQOFRIF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGRINTSTS_CFRIF_Pos (16UL) /*!< CFRIF (Bit 16) */ + #define R_CANFD_CFDGRINTSTS_CFRIF_Msk (0x70000UL) /*!< CFRIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos (24UL) /*!< CFRFIF (Bit 24) */ + #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk (0x7000000UL) /*!< CFRFIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos (28UL) /*!< CFOFRIF (Bit 28) */ + #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDGRSTC ======================================================== */ + #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ + #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDGFCMC ======================================================== */ + #define R_CANFD_CFDGFCMC_FLXC0_Pos (0UL) /*!< FLXC0 (Bit 0) */ + #define R_CANFD_CFDGFCMC_FLXC0_Msk (0x1UL) /*!< FLXC0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFTBAC ======================================================= */ + #define R_CANFD_CFDGFTBAC_FLXMB0_Pos (0UL) /*!< FLXMB0 (Bit 0) */ + #define R_CANFD_CFDGFTBAC_FLXMB0_Msk (0xfUL) /*!< FLXMB0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDRPGACC ======================================================= */ + #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ + #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CMT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_CMTW0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMWSTR ========================================================= */ + #define R_CMTW0_CMWSTR_STR_Pos (0UL) /*!< STR (Bit 0) */ + #define R_CMTW0_CMWSTR_STR_Msk (0x1UL) /*!< STR (Bitfield-Mask: 0x01) */ +/* ========================================================= CMWCR ========================================================= */ + #define R_CMTW0_CMWCR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_CMTW0_CMWCR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_CMTW0_CMWCR_CMWIE_Pos (3UL) /*!< CMWIE (Bit 3) */ + #define R_CMTW0_CMWCR_CMWIE_Msk (0x8UL) /*!< CMWIE (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_IC0IE_Pos (4UL) /*!< IC0IE (Bit 4) */ + #define R_CMTW0_CMWCR_IC0IE_Msk (0x10UL) /*!< IC0IE (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_IC1IE_Pos (5UL) /*!< IC1IE (Bit 5) */ + #define R_CMTW0_CMWCR_IC1IE_Msk (0x20UL) /*!< IC1IE (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_OC0IE_Pos (6UL) /*!< OC0IE (Bit 6) */ + #define R_CMTW0_CMWCR_OC0IE_Msk (0x40UL) /*!< OC0IE (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_OC1IE_Pos (7UL) /*!< OC1IE (Bit 7) */ + #define R_CMTW0_CMWCR_OC1IE_Msk (0x80UL) /*!< OC1IE (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_CMS_Pos (9UL) /*!< CMS (Bit 9) */ + #define R_CMTW0_CMWCR_CMS_Msk (0x200UL) /*!< CMS (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_CCLR_Pos (13UL) /*!< CCLR (Bit 13) */ + #define R_CMTW0_CMWCR_CCLR_Msk (0xe000UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMWIOR ========================================================= */ + #define R_CMTW0_CMWIOR_IC0_Pos (0UL) /*!< IC0 (Bit 0) */ + #define R_CMTW0_CMWIOR_IC0_Msk (0x3UL) /*!< IC0 (Bitfield-Mask: 0x03) */ + #define R_CMTW0_CMWIOR_IC1_Pos (2UL) /*!< IC1 (Bit 2) */ + #define R_CMTW0_CMWIOR_IC1_Msk (0xcUL) /*!< IC1 (Bitfield-Mask: 0x03) */ + #define R_CMTW0_CMWIOR_IC0E_Pos (4UL) /*!< IC0E (Bit 4) */ + #define R_CMTW0_CMWIOR_IC0E_Msk (0x10UL) /*!< IC0E (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWIOR_IC1E_Pos (5UL) /*!< IC1E (Bit 5) */ + #define R_CMTW0_CMWIOR_IC1E_Msk (0x20UL) /*!< IC1E (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWIOR_OC0_Pos (8UL) /*!< OC0 (Bit 8) */ + #define R_CMTW0_CMWIOR_OC0_Msk (0x300UL) /*!< OC0 (Bitfield-Mask: 0x03) */ + #define R_CMTW0_CMWIOR_OC1_Pos (10UL) /*!< OC1 (Bit 10) */ + #define R_CMTW0_CMWIOR_OC1_Msk (0xc00UL) /*!< OC1 (Bitfield-Mask: 0x03) */ + #define R_CMTW0_CMWIOR_OC0E_Pos (12UL) /*!< OC0E (Bit 12) */ + #define R_CMTW0_CMWIOR_OC0E_Msk (0x1000UL) /*!< OC0E (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWIOR_OC1E_Pos (13UL) /*!< OC1E (Bit 13) */ + #define R_CMTW0_CMWIOR_OC1E_Msk (0x2000UL) /*!< OC1E (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWIOR_CMWE_Pos (15UL) /*!< CMWE (Bit 15) */ + #define R_CMTW0_CMWIOR_CMWE_Msk (0x8000UL) /*!< CMWE (Bitfield-Mask: 0x01) */ +/* ======================================================== CMWCNT ========================================================= */ +/* ======================================================== CMWCOR ========================================================= */ +/* ======================================================== CMWICR0 ======================================================== */ +/* ======================================================== CMWICR1 ======================================================== */ +/* ======================================================== CMWOCR0 ======================================================== */ +/* ======================================================== CMWOCR1 ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_WDT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT0_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT0_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ + #define R_WDT0_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT0_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT0_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT0_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT0_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT0_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT0_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT0_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + #define R_WDT0_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT0_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT0_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT0_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT0_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT0_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ +/* ========================================================= ICDRR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCIE_Pos (4UL) /*!< DOPCIE (Bit 4) */ + #define R_DOC_DOCR_DOPCIE_Msk (0x10UL) /*!< DOPCIE (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ +/* ========================================================= DODIR ========================================================= */ +/* ========================================================= DODSR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_TSU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSUSM ========================================================= */ + #define R_TSU_TSUSM_TSEN_Pos (0UL) /*!< TSEN (Bit 0) */ + #define R_TSU_TSUSM_TSEN_Msk (0x1UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSU_TSUSM_ADCEN_Pos (1UL) /*!< ADCEN (Bit 1) */ + #define R_TSU_TSUSM_ADCEN_Msk (0x2UL) /*!< ADCEN (Bitfield-Mask: 0x01) */ +/* ========================================================= TSUST ========================================================= */ + #define R_TSU_TSUST_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_TSU_TSUST_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== TSUSCS ========================================================= */ + #define R_TSU_TSUSCS_CKDIV_Pos (3UL) /*!< CKDIV (Bit 3) */ + #define R_TSU_TSUSCS_CKDIV_Msk (0x8UL) /*!< CKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== TSUSAD ========================================================= */ + #define R_TSU_TSUSAD_DOUT_Pos (0UL) /*!< DOUT (Bit 0) */ + #define R_TSU_TSUSAD_DOUT_Msk (0xfffUL) /*!< DOUT (Bitfield-Mask: 0xfff) */ +/* ========================================================= TSUSS ========================================================= */ + #define R_TSU_TSUSS_CONV_Pos (0UL) /*!< CONV (Bit 0) */ + #define R_TSU_TSUSS_CONV_Msk (0x1UL) /*!< CONV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG1 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== POEG1GA ======================================================== */ + #define R_POEG1_POEG1GA_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG1_POEG1GA_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG1_POEG1GA_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG1_POEG1GA_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG1_POEG1GA_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG1_POEG1GA_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG1_POEG1GA_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG1_POEG1GA_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG1_POEG1GA_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG1_POEG1GA_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG1_POEG1GA_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG1_POEG1GA_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG1GB ======================================================== */ + #define R_POEG1_POEG1GB_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG1_POEG1GB_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG1_POEG1GB_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG1_POEG1GB_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG1_POEG1GB_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG1_POEG1GB_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG1_POEG1GB_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG1_POEG1GB_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG1_POEG1GB_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG1_POEG1GB_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG1_POEG1GB_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG1_POEG1GB_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG1GC ======================================================== */ + #define R_POEG1_POEG1GC_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG1_POEG1GC_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG1_POEG1GC_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG1_POEG1GC_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG1_POEG1GC_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG1_POEG1GC_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG1_POEG1GC_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG1_POEG1GC_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG1_POEG1GC_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG1_POEG1GC_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG1_POEG1GC_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG1_POEG1GC_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG1GD ======================================================== */ + #define R_POEG1_POEG1GD_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG1_POEG1GD_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG1_POEG1GD_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG1_POEG1GD_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG1_POEG1GD_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG1_POEG1GD_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG1_POEG1GD_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG1_POEG1GD_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG1_POEG1GD_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG1_POEG1GD_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG1_POEG1GD_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG1_POEG1GD_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_ICU_NS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= NS_SWINT ======================================================== */ + #define R_ICU_NS_NS_SWINT_IC0_Pos (0UL) /*!< IC0 (Bit 0) */ + #define R_ICU_NS_NS_SWINT_IC0_Msk (0x1UL) /*!< IC0 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_SWINT_IC1_Pos (1UL) /*!< IC1 (Bit 1) */ + #define R_ICU_NS_NS_SWINT_IC1_Msk (0x2UL) /*!< IC1 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_SWINT_IC2_Pos (2UL) /*!< IC2 (Bit 2) */ + #define R_ICU_NS_NS_SWINT_IC2_Msk (0x4UL) /*!< IC2 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_SWINT_IC3_Pos (3UL) /*!< IC3 (Bit 3) */ + #define R_ICU_NS_NS_SWINT_IC3_Msk (0x8UL) /*!< IC3 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_SWINT_IC4_Pos (4UL) /*!< IC4 (Bit 4) */ + #define R_ICU_NS_NS_SWINT_IC4_Msk (0x10UL) /*!< IC4 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_SWINT_IC5_Pos (5UL) /*!< IC5 (Bit 5) */ + #define R_ICU_NS_NS_SWINT_IC5_Msk (0x20UL) /*!< IC5 (Bitfield-Mask: 0x01) */ +/* =================================================== NS_PORTNF_FLTSEL ==================================================== */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT0_Pos (0UL) /*!< FLT0 (Bit 0) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT0_Msk (0x1UL) /*!< FLT0 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT1_Pos (1UL) /*!< FLT1 (Bit 1) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT1_Msk (0x2UL) /*!< FLT1 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT2_Pos (2UL) /*!< FLT2 (Bit 2) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT2_Msk (0x4UL) /*!< FLT2 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT3_Pos (3UL) /*!< FLT3 (Bit 3) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT3_Msk (0x8UL) /*!< FLT3 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT4_Pos (4UL) /*!< FLT4 (Bit 4) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT4_Msk (0x10UL) /*!< FLT4 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT5_Pos (5UL) /*!< FLT5 (Bit 5) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT5_Msk (0x20UL) /*!< FLT5 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT6_Pos (6UL) /*!< FLT6 (Bit 6) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT6_Msk (0x40UL) /*!< FLT6 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT7_Pos (7UL) /*!< FLT7 (Bit 7) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT7_Msk (0x80UL) /*!< FLT7 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT8_Pos (8UL) /*!< FLT8 (Bit 8) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT8_Msk (0x100UL) /*!< FLT8 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT9_Pos (9UL) /*!< FLT9 (Bit 9) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT9_Msk (0x200UL) /*!< FLT9 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT10_Pos (10UL) /*!< FLT10 (Bit 10) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT10_Msk (0x400UL) /*!< FLT10 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT11_Pos (11UL) /*!< FLT11 (Bit 11) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT11_Msk (0x800UL) /*!< FLT11 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT12_Pos (12UL) /*!< FLT12 (Bit 12) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT12_Msk (0x1000UL) /*!< FLT12 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT13_Pos (13UL) /*!< FLT13 (Bit 13) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT13_Msk (0x2000UL) /*!< FLT13 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLTDRQ_Pos (14UL) /*!< FLTDRQ (Bit 14) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLTDRQ_Msk (0x4000UL) /*!< FLTDRQ (Bitfield-Mask: 0x01) */ +/* =================================================== NS_PORTNF_CLKSEL ==================================================== */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL0_Pos (0UL) /*!< CKSEL0 (Bit 0) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL0_Msk (0x3UL) /*!< CKSEL0 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL1_Pos (2UL) /*!< CKSEL1 (Bit 2) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL1_Msk (0xcUL) /*!< CKSEL1 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL2_Pos (4UL) /*!< CKSEL2 (Bit 4) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL2_Msk (0x30UL) /*!< CKSEL2 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL3_Pos (6UL) /*!< CKSEL3 (Bit 6) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL3_Msk (0xc0UL) /*!< CKSEL3 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL4_Pos (8UL) /*!< CKSEL4 (Bit 8) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL4_Msk (0x300UL) /*!< CKSEL4 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL5_Pos (10UL) /*!< CKSEL5 (Bit 10) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL5_Msk (0xc00UL) /*!< CKSEL5 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL6_Pos (12UL) /*!< CKSEL6 (Bit 12) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL6_Msk (0x3000UL) /*!< CKSEL6 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL7_Pos (14UL) /*!< CKSEL7 (Bit 14) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL7_Msk (0xc000UL) /*!< CKSEL7 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL8_Pos (16UL) /*!< CKSEL8 (Bit 16) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL8_Msk (0x30000UL) /*!< CKSEL8 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL9_Pos (18UL) /*!< CKSEL9 (Bit 18) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL9_Msk (0xc0000UL) /*!< CKSEL9 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL10_Pos (20UL) /*!< CKSEL10 (Bit 20) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL10_Msk (0x300000UL) /*!< CKSEL10 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL11_Pos (22UL) /*!< CKSEL11 (Bit 22) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL11_Msk (0xc00000UL) /*!< CKSEL11 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL12_Pos (24UL) /*!< CKSEL12 (Bit 24) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL12_Msk (0x3000000UL) /*!< CKSEL12 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL13_Pos (26UL) /*!< CKSEL13 (Bit 26) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL13_Msk (0xc000000UL) /*!< CKSEL13 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSELDREQ_Pos (28UL) /*!< CKSELDREQ (Bit 28) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSELDREQ_Msk (0x30000000UL) /*!< CKSELDREQ (Bitfield-Mask: 0x03) */ +/* ===================================================== NS_PORTNF_MD ====================================================== */ + #define R_ICU_NS_NS_PORTNF_MD_MD0_Pos (0UL) /*!< MD0 (Bit 0) */ + #define R_ICU_NS_NS_PORTNF_MD_MD0_Msk (0x3UL) /*!< MD0 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD1_Pos (2UL) /*!< MD1 (Bit 2) */ + #define R_ICU_NS_NS_PORTNF_MD_MD1_Msk (0xcUL) /*!< MD1 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD2_Pos (4UL) /*!< MD2 (Bit 4) */ + #define R_ICU_NS_NS_PORTNF_MD_MD2_Msk (0x30UL) /*!< MD2 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD3_Pos (6UL) /*!< MD3 (Bit 6) */ + #define R_ICU_NS_NS_PORTNF_MD_MD3_Msk (0xc0UL) /*!< MD3 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD4_Pos (8UL) /*!< MD4 (Bit 8) */ + #define R_ICU_NS_NS_PORTNF_MD_MD4_Msk (0x300UL) /*!< MD4 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD5_Pos (10UL) /*!< MD5 (Bit 10) */ + #define R_ICU_NS_NS_PORTNF_MD_MD5_Msk (0xc00UL) /*!< MD5 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD6_Pos (12UL) /*!< MD6 (Bit 12) */ + #define R_ICU_NS_NS_PORTNF_MD_MD6_Msk (0x3000UL) /*!< MD6 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD7_Pos (14UL) /*!< MD7 (Bit 14) */ + #define R_ICU_NS_NS_PORTNF_MD_MD7_Msk (0xc000UL) /*!< MD7 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD8_Pos (16UL) /*!< MD8 (Bit 16) */ + #define R_ICU_NS_NS_PORTNF_MD_MD8_Msk (0x30000UL) /*!< MD8 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD9_Pos (18UL) /*!< MD9 (Bit 18) */ + #define R_ICU_NS_NS_PORTNF_MD_MD9_Msk (0xc0000UL) /*!< MD9 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD10_Pos (20UL) /*!< MD10 (Bit 20) */ + #define R_ICU_NS_NS_PORTNF_MD_MD10_Msk (0x300000UL) /*!< MD10 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD11_Pos (22UL) /*!< MD11 (Bit 22) */ + #define R_ICU_NS_NS_PORTNF_MD_MD11_Msk (0xc00000UL) /*!< MD11 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD12_Pos (24UL) /*!< MD12 (Bit 24) */ + #define R_ICU_NS_NS_PORTNF_MD_MD12_Msk (0x3000000UL) /*!< MD12 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD13_Pos (26UL) /*!< MD13 (Bit 26) */ + #define R_ICU_NS_NS_PORTNF_MD_MD13_Msk (0xc000000UL) /*!< MD13 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MDDRQ_Pos (28UL) /*!< MDDRQ (Bit 28) */ + #define R_ICU_NS_NS_PORTNF_MD_MDDRQ_Msk (0x30000000UL) /*!< MDDRQ (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= ELC_SSEL ======================================================== */ + #define R_ELC_ELC_SSEL_ELC_SEL0_Pos (0UL) /*!< ELC_SEL0 (Bit 0) */ + #define R_ELC_ELC_SSEL_ELC_SEL0_Msk (0x3ffUL) /*!< ELC_SEL0 (Bitfield-Mask: 0x3ff) */ + #define R_ELC_ELC_SSEL_ELC_SEL1_Pos (10UL) /*!< ELC_SEL1 (Bit 10) */ + #define R_ELC_ELC_SSEL_ELC_SEL1_Msk (0xffc00UL) /*!< ELC_SEL1 (Bitfield-Mask: 0x3ff) */ + #define R_ELC_ELC_SSEL_ELC_SEL2_Pos (20UL) /*!< ELC_SEL2 (Bit 20) */ + #define R_ELC_ELC_SSEL_ELC_SEL2_Msk (0x3ff00000UL) /*!< ELC_SEL2 (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== DMAC0_RSSEL ====================================================== */ + #define R_DMA_DMAC0_RSSEL_REQ_SELA_Pos (0UL) /*!< REQ_SELA (Bit 0) */ + #define R_DMA_DMAC0_RSSEL_REQ_SELA_Msk (0x1ffUL) /*!< REQ_SELA (Bitfield-Mask: 0x1ff) */ + #define R_DMA_DMAC0_RSSEL_REQ_SELB_Pos (10UL) /*!< REQ_SELB (Bit 10) */ + #define R_DMA_DMAC0_RSSEL_REQ_SELB_Msk (0x7fc00UL) /*!< REQ_SELB (Bitfield-Mask: 0x1ff) */ + #define R_DMA_DMAC0_RSSEL_REQ_SELC_Pos (20UL) /*!< REQ_SELC (Bit 20) */ + #define R_DMA_DMAC0_RSSEL_REQ_SELC_Msk (0x1ff00000UL) /*!< REQ_SELC (Bitfield-Mask: 0x1ff) */ +/* ====================================================== DMAC1_RSSEL ====================================================== */ + #define R_DMA_DMAC1_RSSEL_REQ_SELA_Pos (0UL) /*!< REQ_SELA (Bit 0) */ + #define R_DMA_DMAC1_RSSEL_REQ_SELA_Msk (0x1ffUL) /*!< REQ_SELA (Bitfield-Mask: 0x1ff) */ + #define R_DMA_DMAC1_RSSEL_REQ_SELB_Pos (10UL) /*!< REQ_SELB (Bit 10) */ + #define R_DMA_DMAC1_RSSEL_REQ_SELB_Msk (0x7fc00UL) /*!< REQ_SELB (Bitfield-Mask: 0x1ff) */ + #define R_DMA_DMAC1_RSSEL_REQ_SELC_Pos (20UL) /*!< REQ_SELC (Bit 20) */ + #define R_DMA_DMAC1_RSSEL_REQ_SELC_Msk (0x1ff00000UL) /*!< REQ_SELC (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT_COMMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== P =========================================================== */ + #define R_PORT_NSR_P_POUT_0_Pos (0UL) /*!< POUT_0 (Bit 0) */ + #define R_PORT_NSR_P_POUT_0_Msk (0x1UL) /*!< POUT_0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_1_Pos (1UL) /*!< POUT_1 (Bit 1) */ + #define R_PORT_NSR_P_POUT_1_Msk (0x2UL) /*!< POUT_1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_2_Pos (2UL) /*!< POUT_2 (Bit 2) */ + #define R_PORT_NSR_P_POUT_2_Msk (0x4UL) /*!< POUT_2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_3_Pos (3UL) /*!< POUT_3 (Bit 3) */ + #define R_PORT_NSR_P_POUT_3_Msk (0x8UL) /*!< POUT_3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_4_Pos (4UL) /*!< POUT_4 (Bit 4) */ + #define R_PORT_NSR_P_POUT_4_Msk (0x10UL) /*!< POUT_4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_5_Pos (5UL) /*!< POUT_5 (Bit 5) */ + #define R_PORT_NSR_P_POUT_5_Msk (0x20UL) /*!< POUT_5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_6_Pos (6UL) /*!< POUT_6 (Bit 6) */ + #define R_PORT_NSR_P_POUT_6_Msk (0x40UL) /*!< POUT_6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_7_Pos (7UL) /*!< POUT_7 (Bit 7) */ + #define R_PORT_NSR_P_POUT_7_Msk (0x80UL) /*!< POUT_7 (Bitfield-Mask: 0x01) */ +/* ========================================================== PM =========================================================== */ + #define R_PORT_NSR_PM_PM0_Pos (0UL) /*!< PM0 (Bit 0) */ + #define R_PORT_NSR_PM_PM0_Msk (0x3UL) /*!< PM0 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM1_Pos (2UL) /*!< PM1 (Bit 2) */ + #define R_PORT_NSR_PM_PM1_Msk (0xcUL) /*!< PM1 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM2_Pos (4UL) /*!< PM2 (Bit 4) */ + #define R_PORT_NSR_PM_PM2_Msk (0x30UL) /*!< PM2 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM3_Pos (6UL) /*!< PM3 (Bit 6) */ + #define R_PORT_NSR_PM_PM3_Msk (0xc0UL) /*!< PM3 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM4_Pos (8UL) /*!< PM4 (Bit 8) */ + #define R_PORT_NSR_PM_PM4_Msk (0x300UL) /*!< PM4 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM5_Pos (10UL) /*!< PM5 (Bit 10) */ + #define R_PORT_NSR_PM_PM5_Msk (0xc00UL) /*!< PM5 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM6_Pos (12UL) /*!< PM6 (Bit 12) */ + #define R_PORT_NSR_PM_PM6_Msk (0x3000UL) /*!< PM6 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM7_Pos (14UL) /*!< PM7 (Bit 14) */ + #define R_PORT_NSR_PM_PM7_Msk (0xc000UL) /*!< PM7 (Bitfield-Mask: 0x03) */ +/* ========================================================== PMC ========================================================== */ + #define R_PORT_NSR_PMC_PMC0_Pos (0UL) /*!< PMC0 (Bit 0) */ + #define R_PORT_NSR_PMC_PMC0_Msk (0x1UL) /*!< PMC0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC1_Pos (1UL) /*!< PMC1 (Bit 1) */ + #define R_PORT_NSR_PMC_PMC1_Msk (0x2UL) /*!< PMC1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC2_Pos (2UL) /*!< PMC2 (Bit 2) */ + #define R_PORT_NSR_PMC_PMC2_Msk (0x4UL) /*!< PMC2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC3_Pos (3UL) /*!< PMC3 (Bit 3) */ + #define R_PORT_NSR_PMC_PMC3_Msk (0x8UL) /*!< PMC3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC4_Pos (4UL) /*!< PMC4 (Bit 4) */ + #define R_PORT_NSR_PMC_PMC4_Msk (0x10UL) /*!< PMC4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC5_Pos (5UL) /*!< PMC5 (Bit 5) */ + #define R_PORT_NSR_PMC_PMC5_Msk (0x20UL) /*!< PMC5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC6_Pos (6UL) /*!< PMC6 (Bit 6) */ + #define R_PORT_NSR_PMC_PMC6_Msk (0x40UL) /*!< PMC6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC7_Pos (7UL) /*!< PMC7 (Bit 7) */ + #define R_PORT_NSR_PMC_PMC7_Msk (0x80UL) /*!< PMC7 (Bitfield-Mask: 0x01) */ +/* ========================================================== PFC ========================================================== */ + #define R_PORT_NSR_PFC_PFC0_Pos (0UL) /*!< PFC0 (Bit 0) */ + #define R_PORT_NSR_PFC_PFC0_Msk (0xfUL) /*!< PFC0 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC1_Pos (4UL) /*!< PFC1 (Bit 4) */ + #define R_PORT_NSR_PFC_PFC1_Msk (0xf0UL) /*!< PFC1 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC2_Pos (8UL) /*!< PFC2 (Bit 8) */ + #define R_PORT_NSR_PFC_PFC2_Msk (0xf00UL) /*!< PFC2 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC3_Pos (12UL) /*!< PFC3 (Bit 12) */ + #define R_PORT_NSR_PFC_PFC3_Msk (0xf000UL) /*!< PFC3 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC4_Pos (16UL) /*!< PFC4 (Bit 16) */ + #define R_PORT_NSR_PFC_PFC4_Msk (0xf0000UL) /*!< PFC4 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC5_Pos (20UL) /*!< PFC5 (Bit 20) */ + #define R_PORT_NSR_PFC_PFC5_Msk (0xf00000UL) /*!< PFC5 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC6_Pos (24UL) /*!< PFC6 (Bit 24) */ + #define R_PORT_NSR_PFC_PFC6_Msk (0xf000000UL) /*!< PFC6 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC7_Pos (28UL) /*!< PFC7 (Bit 28) */ + #define R_PORT_NSR_PFC_PFC7_Msk (0xf0000000UL) /*!< PFC7 (Bitfield-Mask: 0x0f) */ +/* ========================================================== PIN ========================================================== */ + #define R_PORT_NSR_PIN_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ + #define R_PORT_NSR_PIN_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ + #define R_PORT_NSR_PIN_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ + #define R_PORT_NSR_PIN_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ + #define R_PORT_NSR_PIN_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ + #define R_PORT_NSR_PIN_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ + #define R_PORT_NSR_PIN_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ + #define R_PORT_NSR_PIN_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ + #define R_PORT_NSR_PIN_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELC_PGR ======================================================== */ + #define R_PORT_NSR_ELC_PGR_PG0_Pos (0UL) /*!< PG0 (Bit 0) */ + #define R_PORT_NSR_ELC_PGR_PG0_Msk (0x1UL) /*!< PG0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG1_Pos (1UL) /*!< PG1 (Bit 1) */ + #define R_PORT_NSR_ELC_PGR_PG1_Msk (0x2UL) /*!< PG1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG2_Pos (2UL) /*!< PG2 (Bit 2) */ + #define R_PORT_NSR_ELC_PGR_PG2_Msk (0x4UL) /*!< PG2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG3_Pos (3UL) /*!< PG3 (Bit 3) */ + #define R_PORT_NSR_ELC_PGR_PG3_Msk (0x8UL) /*!< PG3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG4_Pos (4UL) /*!< PG4 (Bit 4) */ + #define R_PORT_NSR_ELC_PGR_PG4_Msk (0x10UL) /*!< PG4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG5_Pos (5UL) /*!< PG5 (Bit 5) */ + #define R_PORT_NSR_ELC_PGR_PG5_Msk (0x20UL) /*!< PG5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG6_Pos (6UL) /*!< PG6 (Bit 6) */ + #define R_PORT_NSR_ELC_PGR_PG6_Msk (0x40UL) /*!< PG6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG7_Pos (7UL) /*!< PG7 (Bit 7) */ + #define R_PORT_NSR_ELC_PGR_PG7_Msk (0x80UL) /*!< PG7 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELC_PGC ======================================================== */ + #define R_PORT_NSR_ELC_PGC_PGCI_Pos (0UL) /*!< PGCI (Bit 0) */ + #define R_PORT_NSR_ELC_PGC_PGCI_Msk (0x3UL) /*!< PGCI (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_ELC_PGC_PGCOVE_Pos (2UL) /*!< PGCOVE (Bit 2) */ + #define R_PORT_NSR_ELC_PGC_PGCOVE_Msk (0x4UL) /*!< PGCOVE (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGC_PGCO_Pos (4UL) /*!< PGCO (Bit 4) */ + #define R_PORT_NSR_ELC_PGC_PGCO_Msk (0x70UL) /*!< PGCO (Bitfield-Mask: 0x07) */ +/* ======================================================== ELC_PEL ======================================================== */ + #define R_PORT_NSR_ELC_PEL_PSB_Pos (0UL) /*!< PSB (Bit 0) */ + #define R_PORT_NSR_ELC_PEL_PSB_Msk (0x7UL) /*!< PSB (Bitfield-Mask: 0x07) */ + #define R_PORT_NSR_ELC_PEL_PSP_Pos (3UL) /*!< PSP (Bit 3) */ + #define R_PORT_NSR_ELC_PEL_PSP_Msk (0x18UL) /*!< PSP (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_ELC_PEL_PSM_Pos (5UL) /*!< PSM (Bit 5) */ + #define R_PORT_NSR_ELC_PEL_PSM_Msk (0x60UL) /*!< PSM (Bitfield-Mask: 0x03) */ +/* ======================================================= ELC_DPTC ======================================================== */ + #define R_PORT_NSR_ELC_DPTC_PTC0_Pos (0UL) /*!< PTC0 (Bit 0) */ + #define R_PORT_NSR_ELC_DPTC_PTC0_Msk (0x1UL) /*!< PTC0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_DPTC_PTC1_Pos (1UL) /*!< PTC1 (Bit 1) */ + #define R_PORT_NSR_ELC_DPTC_PTC1_Msk (0x2UL) /*!< PTC1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_DPTC_PTC2_Pos (2UL) /*!< PTC2 (Bit 2) */ + #define R_PORT_NSR_ELC_DPTC_PTC2_Msk (0x4UL) /*!< PTC2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_DPTC_PTC3_Pos (3UL) /*!< PTC3 (Bit 3) */ + #define R_PORT_NSR_ELC_DPTC_PTC3_Msk (0x8UL) /*!< PTC3 (Bitfield-Mask: 0x01) */ +/* ======================================================= ELC_ELSR2 ======================================================= */ + #define R_PORT_NSR_ELC_ELSR2_PEG1_Pos (2UL) /*!< PEG1 (Bit 2) */ + #define R_PORT_NSR_ELC_ELSR2_PEG1_Msk (0x4UL) /*!< PEG1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_ELSR2_PEG2_Pos (3UL) /*!< PEG2 (Bit 3) */ + #define R_PORT_NSR_ELC_ELSR2_PEG2_Msk (0x8UL) /*!< PEG2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_ELSR2_PES0_Pos (4UL) /*!< PES0 (Bit 4) */ + #define R_PORT_NSR_ELC_ELSR2_PES0_Msk (0x10UL) /*!< PES0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_ELSR2_PES1_Pos (5UL) /*!< PES1 (Bit 5) */ + #define R_PORT_NSR_ELC_ELSR2_PES1_Msk (0x20UL) /*!< PES1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_ELSR2_PES2_Pos (6UL) /*!< PES2 (Bit 6) */ + #define R_PORT_NSR_ELC_ELSR2_PES2_Msk (0x40UL) /*!< PES2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_ELSR2_PES3_Pos (7UL) /*!< PES3 (Bit 7) */ + #define R_PORT_NSR_ELC_ELSR2_PES3_Msk (0x80UL) /*!< PES3 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GMAC ================ */ +/* =========================================================================================================================== */ + +/* =================================================== MAC_Configuration =================================================== */ + #define R_GMAC_MAC_Configuration_PRELEN_Pos (0UL) /*!< PRELEN (Bit 0) */ + #define R_GMAC_MAC_Configuration_PRELEN_Msk (0x3UL) /*!< PRELEN (Bitfield-Mask: 0x03) */ + #define R_GMAC_MAC_Configuration_RE_Pos (2UL) /*!< RE (Bit 2) */ + #define R_GMAC_MAC_Configuration_RE_Msk (0x4UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_TE_Pos (3UL) /*!< TE (Bit 3) */ + #define R_GMAC_MAC_Configuration_TE_Msk (0x8UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_DC_Pos (4UL) /*!< DC (Bit 4) */ + #define R_GMAC_MAC_Configuration_DC_Msk (0x10UL) /*!< DC (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_BL_Pos (5UL) /*!< BL (Bit 5) */ + #define R_GMAC_MAC_Configuration_BL_Msk (0x60UL) /*!< BL (Bitfield-Mask: 0x03) */ + #define R_GMAC_MAC_Configuration_ACS_Pos (7UL) /*!< ACS (Bit 7) */ + #define R_GMAC_MAC_Configuration_ACS_Msk (0x80UL) /*!< ACS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_DR_Pos (9UL) /*!< DR (Bit 9) */ + #define R_GMAC_MAC_Configuration_DR_Msk (0x200UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_IPC_Pos (10UL) /*!< IPC (Bit 10) */ + #define R_GMAC_MAC_Configuration_IPC_Msk (0x400UL) /*!< IPC (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_DM_Pos (11UL) /*!< DM (Bit 11) */ + #define R_GMAC_MAC_Configuration_DM_Msk (0x800UL) /*!< DM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_LM_Pos (12UL) /*!< LM (Bit 12) */ + #define R_GMAC_MAC_Configuration_LM_Msk (0x1000UL) /*!< LM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_DO_Pos (13UL) /*!< DO (Bit 13) */ + #define R_GMAC_MAC_Configuration_DO_Msk (0x2000UL) /*!< DO (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_FES_Pos (14UL) /*!< FES (Bit 14) */ + #define R_GMAC_MAC_Configuration_FES_Msk (0x4000UL) /*!< FES (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_PS_Pos (15UL) /*!< PS (Bit 15) */ + #define R_GMAC_MAC_Configuration_PS_Msk (0x8000UL) /*!< PS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_DCRS_Pos (16UL) /*!< DCRS (Bit 16) */ + #define R_GMAC_MAC_Configuration_DCRS_Msk (0x10000UL) /*!< DCRS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_IFG_Pos (17UL) /*!< IFG (Bit 17) */ + #define R_GMAC_MAC_Configuration_IFG_Msk (0xe0000UL) /*!< IFG (Bitfield-Mask: 0x07) */ + #define R_GMAC_MAC_Configuration_JE_Pos (20UL) /*!< JE (Bit 20) */ + #define R_GMAC_MAC_Configuration_JE_Msk (0x100000UL) /*!< JE (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_BE_Pos (21UL) /*!< BE (Bit 21) */ + #define R_GMAC_MAC_Configuration_BE_Msk (0x200000UL) /*!< BE (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_JD_Pos (22UL) /*!< JD (Bit 22) */ + #define R_GMAC_MAC_Configuration_JD_Msk (0x400000UL) /*!< JD (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_WD_Pos (23UL) /*!< WD (Bit 23) */ + #define R_GMAC_MAC_Configuration_WD_Msk (0x800000UL) /*!< WD (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_CST_Pos (25UL) /*!< CST (Bit 25) */ + #define R_GMAC_MAC_Configuration_CST_Msk (0x2000000UL) /*!< CST (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_TWOKPE_Pos (27UL) /*!< TWOKPE (Bit 27) */ + #define R_GMAC_MAC_Configuration_TWOKPE_Msk (0x8000000UL) /*!< TWOKPE (Bitfield-Mask: 0x01) */ +/* =================================================== MAC_Frame_Filter ==================================================== */ + #define R_GMAC_MAC_Frame_Filter_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_GMAC_MAC_Frame_Filter_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_HUC_Pos (1UL) /*!< HUC (Bit 1) */ + #define R_GMAC_MAC_Frame_Filter_HUC_Msk (0x2UL) /*!< HUC (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_HMC_Pos (2UL) /*!< HMC (Bit 2) */ + #define R_GMAC_MAC_Frame_Filter_HMC_Msk (0x4UL) /*!< HMC (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_DAIF_Pos (3UL) /*!< DAIF (Bit 3) */ + #define R_GMAC_MAC_Frame_Filter_DAIF_Msk (0x8UL) /*!< DAIF (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_GMAC_MAC_Frame_Filter_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_DBF_Pos (5UL) /*!< DBF (Bit 5) */ + #define R_GMAC_MAC_Frame_Filter_DBF_Msk (0x20UL) /*!< DBF (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_PCF_Pos (6UL) /*!< PCF (Bit 6) */ + #define R_GMAC_MAC_Frame_Filter_PCF_Msk (0xc0UL) /*!< PCF (Bitfield-Mask: 0x03) */ + #define R_GMAC_MAC_Frame_Filter_SAIF_Pos (8UL) /*!< SAIF (Bit 8) */ + #define R_GMAC_MAC_Frame_Filter_SAIF_Msk (0x100UL) /*!< SAIF (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_SAF_Pos (9UL) /*!< SAF (Bit 9) */ + #define R_GMAC_MAC_Frame_Filter_SAF_Msk (0x200UL) /*!< SAF (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_HPF_Pos (10UL) /*!< HPF (Bit 10) */ + #define R_GMAC_MAC_Frame_Filter_HPF_Msk (0x400UL) /*!< HPF (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_VTFE_Pos (16UL) /*!< VTFE (Bit 16) */ + #define R_GMAC_MAC_Frame_Filter_VTFE_Msk (0x10000UL) /*!< VTFE (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_RA_Pos (31UL) /*!< RA (Bit 31) */ + #define R_GMAC_MAC_Frame_Filter_RA_Msk (0x80000000UL) /*!< RA (Bitfield-Mask: 0x01) */ +/* ===================================================== GMII_Address ====================================================== */ + #define R_GMAC_GMII_Address_GB_Pos (0UL) /*!< GB (Bit 0) */ + #define R_GMAC_GMII_Address_GB_Msk (0x1UL) /*!< GB (Bitfield-Mask: 0x01) */ + #define R_GMAC_GMII_Address_GW_Pos (1UL) /*!< GW (Bit 1) */ + #define R_GMAC_GMII_Address_GW_Msk (0x2UL) /*!< GW (Bitfield-Mask: 0x01) */ + #define R_GMAC_GMII_Address_CR_Pos (2UL) /*!< CR (Bit 2) */ + #define R_GMAC_GMII_Address_CR_Msk (0x3cUL) /*!< CR (Bitfield-Mask: 0x0f) */ + #define R_GMAC_GMII_Address_GR_Pos (6UL) /*!< GR (Bit 6) */ + #define R_GMAC_GMII_Address_GR_Msk (0x7c0UL) /*!< GR (Bitfield-Mask: 0x1f) */ + #define R_GMAC_GMII_Address_PA_Pos (11UL) /*!< PA (Bit 11) */ + #define R_GMAC_GMII_Address_PA_Msk (0xf800UL) /*!< PA (Bitfield-Mask: 0x1f) */ +/* ======================================================= GMII_Data ======================================================= */ + #define R_GMAC_GMII_Data_GD_Pos (0UL) /*!< GD (Bit 0) */ + #define R_GMAC_GMII_Data_GD_Msk (0xffffUL) /*!< GD (Bitfield-Mask: 0xffff) */ +/* ===================================================== Flow_Control ====================================================== */ + #define R_GMAC_Flow_Control_FCA_BPA_Pos (0UL) /*!< FCA_BPA (Bit 0) */ + #define R_GMAC_Flow_Control_FCA_BPA_Msk (0x1UL) /*!< FCA_BPA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Flow_Control_TFE_Pos (1UL) /*!< TFE (Bit 1) */ + #define R_GMAC_Flow_Control_TFE_Msk (0x2UL) /*!< TFE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Flow_Control_RFE_Pos (2UL) /*!< RFE (Bit 2) */ + #define R_GMAC_Flow_Control_RFE_Msk (0x4UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Flow_Control_UP_Pos (3UL) /*!< UP (Bit 3) */ + #define R_GMAC_Flow_Control_UP_Msk (0x8UL) /*!< UP (Bitfield-Mask: 0x01) */ + #define R_GMAC_Flow_Control_PLT_Pos (4UL) /*!< PLT (Bit 4) */ + #define R_GMAC_Flow_Control_PLT_Msk (0x30UL) /*!< PLT (Bitfield-Mask: 0x03) */ + #define R_GMAC_Flow_Control_DZPQ_Pos (7UL) /*!< DZPQ (Bit 7) */ + #define R_GMAC_Flow_Control_DZPQ_Msk (0x80UL) /*!< DZPQ (Bitfield-Mask: 0x01) */ + #define R_GMAC_Flow_Control_PT_Pos (16UL) /*!< PT (Bit 16) */ + #define R_GMAC_Flow_Control_PT_Msk (0xffff0000UL) /*!< PT (Bitfield-Mask: 0xffff) */ +/* ======================================================= VLAN_Tag ======================================================== */ + #define R_GMAC_VLAN_Tag_VL_Pos (0UL) /*!< VL (Bit 0) */ + #define R_GMAC_VLAN_Tag_VL_Msk (0xffffUL) /*!< VL (Bitfield-Mask: 0xffff) */ + #define R_GMAC_VLAN_Tag_ETV_Pos (16UL) /*!< ETV (Bit 16) */ + #define R_GMAC_VLAN_Tag_ETV_Msk (0x10000UL) /*!< ETV (Bitfield-Mask: 0x01) */ + #define R_GMAC_VLAN_Tag_VTIM_Pos (17UL) /*!< VTIM (Bit 17) */ + #define R_GMAC_VLAN_Tag_VTIM_Msk (0x20000UL) /*!< VTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_VLAN_Tag_ESVL_Pos (18UL) /*!< ESVL (Bit 18) */ + #define R_GMAC_VLAN_Tag_ESVL_Msk (0x40000UL) /*!< ESVL (Bitfield-Mask: 0x01) */ + #define R_GMAC_VLAN_Tag_VTHM_Pos (19UL) /*!< VTHM (Bit 19) */ + #define R_GMAC_VLAN_Tag_VTHM_Msk (0x80000UL) /*!< VTHM (Bitfield-Mask: 0x01) */ +/* ======================================================== Version ======================================================== */ + #define R_GMAC_Version_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_GMAC_Version_VER_Msk (0xffffUL) /*!< VER (Bitfield-Mask: 0xffff) */ +/* ========================================================= Debug ========================================================= */ + #define R_GMAC_Debug_RPESTS_Pos (0UL) /*!< RPESTS (Bit 0) */ + #define R_GMAC_Debug_RPESTS_Msk (0x1UL) /*!< RPESTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_RFCFCSTS_Pos (1UL) /*!< RFCFCSTS (Bit 1) */ + #define R_GMAC_Debug_RFCFCSTS_Msk (0x6UL) /*!< RFCFCSTS (Bitfield-Mask: 0x03) */ + #define R_GMAC_Debug_RWCSTS_Pos (4UL) /*!< RWCSTS (Bit 4) */ + #define R_GMAC_Debug_RWCSTS_Msk (0x10UL) /*!< RWCSTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_RRCSTS_Pos (5UL) /*!< RRCSTS (Bit 5) */ + #define R_GMAC_Debug_RRCSTS_Msk (0x60UL) /*!< RRCSTS (Bitfield-Mask: 0x03) */ + #define R_GMAC_Debug_RXFSTS_Pos (8UL) /*!< RXFSTS (Bit 8) */ + #define R_GMAC_Debug_RXFSTS_Msk (0x300UL) /*!< RXFSTS (Bitfield-Mask: 0x03) */ + #define R_GMAC_Debug_TPESTS_Pos (16UL) /*!< TPESTS (Bit 16) */ + #define R_GMAC_Debug_TPESTS_Msk (0x10000UL) /*!< TPESTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_TFCSTS_Pos (17UL) /*!< TFCSTS (Bit 17) */ + #define R_GMAC_Debug_TFCSTS_Msk (0x60000UL) /*!< TFCSTS (Bitfield-Mask: 0x03) */ + #define R_GMAC_Debug_TXPAUSED_Pos (19UL) /*!< TXPAUSED (Bit 19) */ + #define R_GMAC_Debug_TXPAUSED_Msk (0x80000UL) /*!< TXPAUSED (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_TRCSTS_Pos (20UL) /*!< TRCSTS (Bit 20) */ + #define R_GMAC_Debug_TRCSTS_Msk (0x300000UL) /*!< TRCSTS (Bitfield-Mask: 0x03) */ + #define R_GMAC_Debug_TWCSTS_Pos (22UL) /*!< TWCSTS (Bit 22) */ + #define R_GMAC_Debug_TWCSTS_Msk (0x400000UL) /*!< TWCSTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_TXFSTS_Pos (24UL) /*!< TXFSTS (Bit 24) */ + #define R_GMAC_Debug_TXFSTS_Msk (0x1000000UL) /*!< TXFSTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_TXSTSFSTS_Pos (25UL) /*!< TXSTSFSTS (Bit 25) */ + #define R_GMAC_Debug_TXSTSFSTS_Msk (0x2000000UL) /*!< TXSTSFSTS (Bitfield-Mask: 0x01) */ +/* ============================================== Remote_Wake_Up_Frame_Filter ============================================== */ + #define R_GMAC_Remote_Wake_Up_Frame_Filter_WKUPFRMFTR_Pos (0UL) /*!< WKUPFRMFTR (Bit 0) */ + #define R_GMAC_Remote_Wake_Up_Frame_Filter_WKUPFRMFTR_Msk (0xffffffffUL) /*!< WKUPFRMFTR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PMT_Control_Status =================================================== */ + #define R_GMAC_PMT_Control_Status_PWRDWN_Pos (0UL) /*!< PWRDWN (Bit 0) */ + #define R_GMAC_PMT_Control_Status_PWRDWN_Msk (0x1UL) /*!< PWRDWN (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_MGKPKTEN_Pos (1UL) /*!< MGKPKTEN (Bit 1) */ + #define R_GMAC_PMT_Control_Status_MGKPKTEN_Msk (0x2UL) /*!< MGKPKTEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_RWKPKTEN_Pos (2UL) /*!< RWKPKTEN (Bit 2) */ + #define R_GMAC_PMT_Control_Status_RWKPKTEN_Msk (0x4UL) /*!< RWKPKTEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_MGKPRCVD_Pos (5UL) /*!< MGKPRCVD (Bit 5) */ + #define R_GMAC_PMT_Control_Status_MGKPRCVD_Msk (0x20UL) /*!< MGKPRCVD (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_RWKPRCVD_Pos (6UL) /*!< RWKPRCVD (Bit 6) */ + #define R_GMAC_PMT_Control_Status_RWKPRCVD_Msk (0x40UL) /*!< RWKPRCVD (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_GLBLUCAST_Pos (9UL) /*!< GLBLUCAST (Bit 9) */ + #define R_GMAC_PMT_Control_Status_GLBLUCAST_Msk (0x200UL) /*!< GLBLUCAST (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_RWKPTR_Pos (24UL) /*!< RWKPTR (Bit 24) */ + #define R_GMAC_PMT_Control_Status_RWKPTR_Msk (0x7000000UL) /*!< RWKPTR (Bitfield-Mask: 0x07) */ + #define R_GMAC_PMT_Control_Status_RWKFILTRST_Pos (31UL) /*!< RWKFILTRST (Bit 31) */ + #define R_GMAC_PMT_Control_Status_RWKFILTRST_Msk (0x80000000UL) /*!< RWKFILTRST (Bitfield-Mask: 0x01) */ +/* ================================================== LPI_Control_Status =================================================== */ + #define R_GMAC_LPI_Control_Status_TLPIEN_Pos (0UL) /*!< TLPIEN (Bit 0) */ + #define R_GMAC_LPI_Control_Status_TLPIEN_Msk (0x1UL) /*!< TLPIEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_TLPIEX_Pos (1UL) /*!< TLPIEX (Bit 1) */ + #define R_GMAC_LPI_Control_Status_TLPIEX_Msk (0x2UL) /*!< TLPIEX (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_RLPIEN_Pos (2UL) /*!< RLPIEN (Bit 2) */ + #define R_GMAC_LPI_Control_Status_RLPIEN_Msk (0x4UL) /*!< RLPIEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_RLPIEX_Pos (3UL) /*!< RLPIEX (Bit 3) */ + #define R_GMAC_LPI_Control_Status_RLPIEX_Msk (0x8UL) /*!< RLPIEX (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_TLPIST_Pos (8UL) /*!< TLPIST (Bit 8) */ + #define R_GMAC_LPI_Control_Status_TLPIST_Msk (0x100UL) /*!< TLPIST (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_RLPIST_Pos (9UL) /*!< RLPIST (Bit 9) */ + #define R_GMAC_LPI_Control_Status_RLPIST_Msk (0x200UL) /*!< RLPIST (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_LPIEN_Pos (16UL) /*!< LPIEN (Bit 16) */ + #define R_GMAC_LPI_Control_Status_LPIEN_Msk (0x10000UL) /*!< LPIEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_PLS_Pos (17UL) /*!< PLS (Bit 17) */ + #define R_GMAC_LPI_Control_Status_PLS_Msk (0x20000UL) /*!< PLS (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_LPITXA_Pos (19UL) /*!< LPITXA (Bit 19) */ + #define R_GMAC_LPI_Control_Status_LPITXA_Msk (0x80000UL) /*!< LPITXA (Bitfield-Mask: 0x01) */ +/* ================================================== LPI_Timers_Control =================================================== */ + #define R_GMAC_LPI_Timers_Control_TWT_Pos (0UL) /*!< TWT (Bit 0) */ + #define R_GMAC_LPI_Timers_Control_TWT_Msk (0xffffUL) /*!< TWT (Bitfield-Mask: 0xffff) */ + #define R_GMAC_LPI_Timers_Control_LST_Pos (16UL) /*!< LST (Bit 16) */ + #define R_GMAC_LPI_Timers_Control_LST_Msk (0x3ff0000UL) /*!< LST (Bitfield-Mask: 0x3ff) */ +/* =================================================== Interrupt_Status ==================================================== */ + #define R_GMAC_Interrupt_Status_PMTIS_Pos (3UL) /*!< PMTIS (Bit 3) */ + #define R_GMAC_Interrupt_Status_PMTIS_Msk (0x8UL) /*!< PMTIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_MMCIS_Pos (4UL) /*!< MMCIS (Bit 4) */ + #define R_GMAC_Interrupt_Status_MMCIS_Msk (0x10UL) /*!< MMCIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_MMCRXIS_Pos (5UL) /*!< MMCRXIS (Bit 5) */ + #define R_GMAC_Interrupt_Status_MMCRXIS_Msk (0x20UL) /*!< MMCRXIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_MMCTXIS_Pos (6UL) /*!< MMCTXIS (Bit 6) */ + #define R_GMAC_Interrupt_Status_MMCTXIS_Msk (0x40UL) /*!< MMCTXIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_MMCRXIPIS_Pos (7UL) /*!< MMCRXIPIS (Bit 7) */ + #define R_GMAC_Interrupt_Status_MMCRXIPIS_Msk (0x80UL) /*!< MMCRXIPIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_TSIS_Pos (9UL) /*!< TSIS (Bit 9) */ + #define R_GMAC_Interrupt_Status_TSIS_Msk (0x200UL) /*!< TSIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_LPIIS_Pos (10UL) /*!< LPIIS (Bit 10) */ + #define R_GMAC_Interrupt_Status_LPIIS_Msk (0x400UL) /*!< LPIIS (Bitfield-Mask: 0x01) */ +/* ==================================================== Interrupt_Mask ===================================================== */ + #define R_GMAC_Interrupt_Mask_PMTIM_Pos (3UL) /*!< PMTIM (Bit 3) */ + #define R_GMAC_Interrupt_Mask_PMTIM_Msk (0x8UL) /*!< PMTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Mask_TSIM_Pos (9UL) /*!< TSIM (Bit 9) */ + #define R_GMAC_Interrupt_Mask_TSIM_Msk (0x200UL) /*!< TSIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Mask_LPIIM_Pos (10UL) /*!< LPIIM (Bit 10) */ + #define R_GMAC_Interrupt_Mask_LPIIM_Msk (0x400UL) /*!< LPIIM (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR0_H ========================================================= */ + #define R_GMAC_MAR0_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR0_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR0_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR0_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR0_L ========================================================= */ + #define R_GMAC_MAR0_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR0_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR1_H ========================================================= */ + #define R_GMAC_MAR1_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR1_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR1_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR1_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR1_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR1_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR1_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR1_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR2_H ========================================================= */ + #define R_GMAC_MAR2_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR2_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR2_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR2_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR2_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR2_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR2_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR2_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR3_H ========================================================= */ + #define R_GMAC_MAR3_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR3_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR3_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR3_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR3_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR3_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR3_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR3_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR4_H ========================================================= */ + #define R_GMAC_MAR4_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR4_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR4_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR4_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR4_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR4_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR4_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR4_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR5_H ========================================================= */ + #define R_GMAC_MAR5_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR5_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR5_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR5_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR5_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR5_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR5_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR5_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR6_H ========================================================= */ + #define R_GMAC_MAR6_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR6_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR6_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR6_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR6_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR6_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR6_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR6_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR7_H ========================================================= */ + #define R_GMAC_MAR7_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR7_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR7_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR7_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR7_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR7_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR7_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR7_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR8_H ========================================================= */ + #define R_GMAC_MAR8_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR8_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR8_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR8_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR8_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR8_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR8_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR8_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR9_H ========================================================= */ + #define R_GMAC_MAR9_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR9_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR9_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR9_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR9_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR9_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR9_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR9_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR10_H ======================================================== */ + #define R_GMAC_MAR10_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR10_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR10_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR10_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR10_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR10_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR10_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR10_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR11_H ======================================================== */ + #define R_GMAC_MAR11_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR11_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR11_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR11_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR11_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR11_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR11_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR11_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR12_H ======================================================== */ + #define R_GMAC_MAR12_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR12_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR12_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR12_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR12_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR12_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR12_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR12_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR13_H ======================================================== */ + #define R_GMAC_MAR13_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR13_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR13_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR13_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR13_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR13_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR13_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR13_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR14_H ======================================================== */ + #define R_GMAC_MAR14_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR14_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR14_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR14_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR14_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR14_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR14_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR14_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR15_H ======================================================== */ + #define R_GMAC_MAR15_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR15_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR15_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR15_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR15_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR15_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR15_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR15_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR1_L ========================================================= */ + #define R_GMAC_MAR1_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR1_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR2_L ========================================================= */ + #define R_GMAC_MAR2_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR2_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR3_L ========================================================= */ + #define R_GMAC_MAR3_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR3_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR4_L ========================================================= */ + #define R_GMAC_MAR4_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR4_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR5_L ========================================================= */ + #define R_GMAC_MAR5_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR5_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR6_L ========================================================= */ + #define R_GMAC_MAR6_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR6_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR7_L ========================================================= */ + #define R_GMAC_MAR7_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR7_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR8_L ========================================================= */ + #define R_GMAC_MAR8_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR8_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR9_L ========================================================= */ + #define R_GMAC_MAR9_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR9_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR10_L ======================================================== */ + #define R_GMAC_MAR10_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR10_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR11_L ======================================================== */ + #define R_GMAC_MAR11_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR11_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR12_L ======================================================== */ + #define R_GMAC_MAR12_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR12_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR13_L ======================================================== */ + #define R_GMAC_MAR13_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR13_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR14_L ======================================================== */ + #define R_GMAC_MAR14_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR14_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR15_L ======================================================== */ + #define R_GMAC_MAR15_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR15_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== WDog_Timeout ====================================================== */ + #define R_GMAC_WDog_Timeout_WTO_Pos (0UL) /*!< WTO (Bit 0) */ + #define R_GMAC_WDog_Timeout_WTO_Msk (0x3fffUL) /*!< WTO (Bitfield-Mask: 0x3fff) */ + #define R_GMAC_WDog_Timeout_PWE_Pos (16UL) /*!< PWE (Bit 16) */ + #define R_GMAC_WDog_Timeout_PWE_Msk (0x10000UL) /*!< PWE (Bitfield-Mask: 0x01) */ +/* ====================================================== MMC_Control ====================================================== */ + #define R_GMAC_MMC_Control_CNTRST_Pos (0UL) /*!< CNTRST (Bit 0) */ + #define R_GMAC_MMC_Control_CNTRST_Msk (0x1UL) /*!< CNTRST (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_CNTSTOPRO_Pos (1UL) /*!< CNTSTOPRO (Bit 1) */ + #define R_GMAC_MMC_Control_CNTSTOPRO_Msk (0x2UL) /*!< CNTSTOPRO (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_RSTONRD_Pos (2UL) /*!< RSTONRD (Bit 2) */ + #define R_GMAC_MMC_Control_RSTONRD_Msk (0x4UL) /*!< RSTONRD (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_CNTFREEZ_Pos (3UL) /*!< CNTFREEZ (Bit 3) */ + #define R_GMAC_MMC_Control_CNTFREEZ_Msk (0x8UL) /*!< CNTFREEZ (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_CNTPRST_Pos (4UL) /*!< CNTPRST (Bit 4) */ + #define R_GMAC_MMC_Control_CNTPRST_Msk (0x10UL) /*!< CNTPRST (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_CNTPRSTLVL_Pos (5UL) /*!< CNTPRSTLVL (Bit 5) */ + #define R_GMAC_MMC_Control_CNTPRSTLVL_Msk (0x20UL) /*!< CNTPRSTLVL (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_UCDBC_Pos (8UL) /*!< UCDBC (Bit 8) */ + #define R_GMAC_MMC_Control_UCDBC_Msk (0x100UL) /*!< UCDBC (Bitfield-Mask: 0x01) */ +/* ================================================= MMC_Receive_Interrupt ================================================= */ + #define R_GMAC_MMC_Receive_Interrupt_RXGBFRMIS_Pos (0UL) /*!< RXGBFRMIS (Bit 0) */ + #define R_GMAC_MMC_Receive_Interrupt_RXGBFRMIS_Msk (0x1UL) /*!< RXGBFRMIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXGBOCTIS_Pos (1UL) /*!< RXGBOCTIS (Bit 1) */ + #define R_GMAC_MMC_Receive_Interrupt_RXGBOCTIS_Msk (0x2UL) /*!< RXGBOCTIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXGOCTIS_Pos (2UL) /*!< RXGOCTIS (Bit 2) */ + #define R_GMAC_MMC_Receive_Interrupt_RXGOCTIS_Msk (0x4UL) /*!< RXGOCTIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXBCGFIS_Pos (3UL) /*!< RXBCGFIS (Bit 3) */ + #define R_GMAC_MMC_Receive_Interrupt_RXBCGFIS_Msk (0x8UL) /*!< RXBCGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXMCGFIS_Pos (4UL) /*!< RXMCGFIS (Bit 4) */ + #define R_GMAC_MMC_Receive_Interrupt_RXMCGFIS_Msk (0x10UL) /*!< RXMCGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXCRCERFIS_Pos (5UL) /*!< RXCRCERFIS (Bit 5) */ + #define R_GMAC_MMC_Receive_Interrupt_RXCRCERFIS_Msk (0x20UL) /*!< RXCRCERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXALGNERFIS_Pos (6UL) /*!< RXALGNERFIS (Bit 6) */ + #define R_GMAC_MMC_Receive_Interrupt_RXALGNERFIS_Msk (0x40UL) /*!< RXALGNERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXRUNTFIS_Pos (7UL) /*!< RXRUNTFIS (Bit 7) */ + #define R_GMAC_MMC_Receive_Interrupt_RXRUNTFIS_Msk (0x80UL) /*!< RXRUNTFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXJABERFIS_Pos (8UL) /*!< RXJABERFIS (Bit 8) */ + #define R_GMAC_MMC_Receive_Interrupt_RXJABERFIS_Msk (0x100UL) /*!< RXJABERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXUSIZEGFIS_Pos (9UL) /*!< RXUSIZEGFIS (Bit 9) */ + #define R_GMAC_MMC_Receive_Interrupt_RXUSIZEGFIS_Msk (0x200UL) /*!< RXUSIZEGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXOSIZEGFIS_Pos (10UL) /*!< RXOSIZEGFIS (Bit 10) */ + #define R_GMAC_MMC_Receive_Interrupt_RXOSIZEGFIS_Msk (0x400UL) /*!< RXOSIZEGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX64OCTGBFIS_Pos (11UL) /*!< RX64OCTGBFIS (Bit 11) */ + #define R_GMAC_MMC_Receive_Interrupt_RX64OCTGBFIS_Msk (0x800UL) /*!< RX64OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX65T127OCTGBFIS_Pos (12UL) /*!< RX65T127OCTGBFIS (Bit 12) */ + #define R_GMAC_MMC_Receive_Interrupt_RX65T127OCTGBFIS_Msk (0x1000UL) /*!< RX65T127OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX128T255OCTGBFIS_Pos (13UL) /*!< RX128T255OCTGBFIS (Bit 13) */ + #define R_GMAC_MMC_Receive_Interrupt_RX128T255OCTGBFIS_Msk (0x2000UL) /*!< RX128T255OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX256T511OCTGBFIS_Pos (14UL) /*!< RX256T511OCTGBFIS (Bit 14) */ + #define R_GMAC_MMC_Receive_Interrupt_RX256T511OCTGBFIS_Msk (0x4000UL) /*!< RX256T511OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX512T1023OCTGBFIS_Pos (15UL) /*!< RX512T1023OCTGBFIS (Bit 15) */ + #define R_GMAC_MMC_Receive_Interrupt_RX512T1023OCTGBFIS_Msk (0x8000UL) /*!< RX512T1023OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX1024TMAXOCTGBFIS_Pos (16UL) /*!< RX1024TMAXOCTGBFIS (Bit 16) */ + #define R_GMAC_MMC_Receive_Interrupt_RX1024TMAXOCTGBFIS_Msk (0x10000UL) /*!< RX1024TMAXOCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXUCGFIS_Pos (17UL) /*!< RXUCGFIS (Bit 17) */ + #define R_GMAC_MMC_Receive_Interrupt_RXUCGFIS_Msk (0x20000UL) /*!< RXUCGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXLENERFIS_Pos (18UL) /*!< RXLENERFIS (Bit 18) */ + #define R_GMAC_MMC_Receive_Interrupt_RXLENERFIS_Msk (0x40000UL) /*!< RXLENERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXORANGEFIS_Pos (19UL) /*!< RXORANGEFIS (Bit 19) */ + #define R_GMAC_MMC_Receive_Interrupt_RXORANGEFIS_Msk (0x80000UL) /*!< RXORANGEFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXPAUSFIS_Pos (20UL) /*!< RXPAUSFIS (Bit 20) */ + #define R_GMAC_MMC_Receive_Interrupt_RXPAUSFIS_Msk (0x100000UL) /*!< RXPAUSFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXFOVFIS_Pos (21UL) /*!< RXFOVFIS (Bit 21) */ + #define R_GMAC_MMC_Receive_Interrupt_RXFOVFIS_Msk (0x200000UL) /*!< RXFOVFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXVLANGBFIS_Pos (22UL) /*!< RXVLANGBFIS (Bit 22) */ + #define R_GMAC_MMC_Receive_Interrupt_RXVLANGBFIS_Msk (0x400000UL) /*!< RXVLANGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXWDOGFIS_Pos (23UL) /*!< RXWDOGFIS (Bit 23) */ + #define R_GMAC_MMC_Receive_Interrupt_RXWDOGFIS_Msk (0x800000UL) /*!< RXWDOGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXRCVERRFIS_Pos (24UL) /*!< RXRCVERRFIS (Bit 24) */ + #define R_GMAC_MMC_Receive_Interrupt_RXRCVERRFIS_Msk (0x1000000UL) /*!< RXRCVERRFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXCTRLFIS_Pos (25UL) /*!< RXCTRLFIS (Bit 25) */ + #define R_GMAC_MMC_Receive_Interrupt_RXCTRLFIS_Msk (0x2000000UL) /*!< RXCTRLFIS (Bitfield-Mask: 0x01) */ +/* ================================================ MMC_Transmit_Interrupt ================================================= */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGBOCTIS_Pos (0UL) /*!< TXGBOCTIS (Bit 0) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGBOCTIS_Msk (0x1UL) /*!< TXGBOCTIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGBFRMIS_Pos (1UL) /*!< TXGBFRMIS (Bit 1) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGBFRMIS_Msk (0x2UL) /*!< TXGBFRMIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXBCGFIS_Pos (2UL) /*!< TXBCGFIS (Bit 2) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXBCGFIS_Msk (0x4UL) /*!< TXBCGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCGFIS_Pos (3UL) /*!< TXMCGFIS (Bit 3) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCGFIS_Msk (0x8UL) /*!< TXMCGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX64OCTGBFIS_Pos (4UL) /*!< TX64OCTGBFIS (Bit 4) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX64OCTGBFIS_Msk (0x10UL) /*!< TX64OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX65T127OCTGBFIS_Pos (5UL) /*!< TX65T127OCTGBFIS (Bit 5) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX65T127OCTGBFIS_Msk (0x20UL) /*!< TX65T127OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX128T255OCTGBFIS_Pos (6UL) /*!< TX128T255OCTGBFIS (Bit 6) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX128T255OCTGBFIS_Msk (0x40UL) /*!< TX128T255OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX256T511OCTGBFIS_Pos (7UL) /*!< TX256T511OCTGBFIS (Bit 7) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX256T511OCTGBFIS_Msk (0x80UL) /*!< TX256T511OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX512T1023OCTGBFIS_Pos (8UL) /*!< TX512T1023OCTGBFIS (Bit 8) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX512T1023OCTGBFIS_Msk (0x100UL) /*!< TX512T1023OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX1024TMAXOCTGBFIS_Pos (9UL) /*!< TX1024TMAXOCTGBFIS (Bit 9) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX1024TMAXOCTGBFIS_Msk (0x200UL) /*!< TX1024TMAXOCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXUCGBFIS_Pos (10UL) /*!< TXUCGBFIS (Bit 10) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXUCGBFIS_Msk (0x400UL) /*!< TXUCGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCGBFIS_Pos (11UL) /*!< TXMCGBFIS (Bit 11) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCGBFIS_Msk (0x800UL) /*!< TXMCGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXBCGBFIS_Pos (12UL) /*!< TXBCGBFIS (Bit 12) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXBCGBFIS_Msk (0x1000UL) /*!< TXBCGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXUFLOWERFIS_Pos (13UL) /*!< TXUFLOWERFIS (Bit 13) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXUFLOWERFIS_Msk (0x2000UL) /*!< TXUFLOWERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXSCOLGFIS_Pos (14UL) /*!< TXSCOLGFIS (Bit 14) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXSCOLGFIS_Msk (0x4000UL) /*!< TXSCOLGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCOLGFIS_Pos (15UL) /*!< TXMCOLGFIS (Bit 15) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCOLGFIS_Msk (0x8000UL) /*!< TXMCOLGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXDEFFIS_Pos (16UL) /*!< TXDEFFIS (Bit 16) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXDEFFIS_Msk (0x10000UL) /*!< TXDEFFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXLATCOLFIS_Pos (17UL) /*!< TXLATCOLFIS (Bit 17) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXLATCOLFIS_Msk (0x20000UL) /*!< TXLATCOLFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXEXCOLFIS_Pos (18UL) /*!< TXEXCOLFIS (Bit 18) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXEXCOLFIS_Msk (0x40000UL) /*!< TXEXCOLFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXCARERFIS_Pos (19UL) /*!< TXCARERFIS (Bit 19) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXCARERFIS_Msk (0x80000UL) /*!< TXCARERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGOCTIS_Pos (20UL) /*!< TXGOCTIS (Bit 20) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGOCTIS_Msk (0x100000UL) /*!< TXGOCTIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGFRMIS_Pos (21UL) /*!< TXGFRMIS (Bit 21) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGFRMIS_Msk (0x200000UL) /*!< TXGFRMIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXEXDEFFIS_Pos (22UL) /*!< TXEXDEFFIS (Bit 22) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXEXDEFFIS_Msk (0x400000UL) /*!< TXEXDEFFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXPAUSFIS_Pos (23UL) /*!< TXPAUSFIS (Bit 23) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXPAUSFIS_Msk (0x800000UL) /*!< TXPAUSFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXVLANGFIS_Pos (24UL) /*!< TXVLANGFIS (Bit 24) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXVLANGFIS_Msk (0x1000000UL) /*!< TXVLANGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXOSIZEGFIS_Pos (25UL) /*!< TXOSIZEGFIS (Bit 25) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXOSIZEGFIS_Msk (0x2000000UL) /*!< TXOSIZEGFIS (Bitfield-Mask: 0x01) */ +/* ============================================== MMC_Receive_Interrupt_Mask =============================================== */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBFRMIM_Pos (0UL) /*!< RXGBFRMIM (Bit 0) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBFRMIM_Msk (0x1UL) /*!< RXGBFRMIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBOCTIM_Pos (1UL) /*!< RXGBOCTIM (Bit 1) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBOCTIM_Msk (0x2UL) /*!< RXGBOCTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGOCTIM_Pos (2UL) /*!< RXGOCTIM (Bit 2) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGOCTIM_Msk (0x4UL) /*!< RXGOCTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXBCGFIM_Pos (3UL) /*!< RXBCGFIM (Bit 3) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXBCGFIM_Msk (0x8UL) /*!< RXBCGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXMCGFIM_Pos (4UL) /*!< RXMCGFIM (Bit 4) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXMCGFIM_Msk (0x10UL) /*!< RXMCGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCRCERFIM_Pos (5UL) /*!< RXCRCERFIM (Bit 5) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCRCERFIM_Msk (0x20UL) /*!< RXCRCERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXALGNERFIM_Pos (6UL) /*!< RXALGNERFIM (Bit 6) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXALGNERFIM_Msk (0x40UL) /*!< RXALGNERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRUNTFIM_Pos (7UL) /*!< RXRUNTFIM (Bit 7) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRUNTFIM_Msk (0x80UL) /*!< RXRUNTFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXJABERFIM_Pos (8UL) /*!< RXJABERFIM (Bit 8) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXJABERFIM_Msk (0x100UL) /*!< RXJABERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUSIZEGFIM_Pos (9UL) /*!< RXUSIZEGFIM (Bit 9) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUSIZEGFIM_Msk (0x200UL) /*!< RXUSIZEGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXOSIZEGFIM_Pos (10UL) /*!< RXOSIZEGFIM (Bit 10) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXOSIZEGFIM_Msk (0x400UL) /*!< RXOSIZEGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX64OCTGBFIM_Pos (11UL) /*!< RX64OCTGBFIM (Bit 11) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX64OCTGBFIM_Msk (0x800UL) /*!< RX64OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX65T127OCTGBFIM_Pos (12UL) /*!< RX65T127OCTGBFIM (Bit 12) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX65T127OCTGBFIM_Msk (0x1000UL) /*!< RX65T127OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX128T255OCTGBFIM_Pos (13UL) /*!< RX128T255OCTGBFIM (Bit 13) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX128T255OCTGBFIM_Msk (0x2000UL) /*!< RX128T255OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX256T511OCTGBFIM_Pos (14UL) /*!< RX256T511OCTGBFIM (Bit 14) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX256T511OCTGBFIM_Msk (0x4000UL) /*!< RX256T511OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX512T1023OCTGBFIM_Pos (15UL) /*!< RX512T1023OCTGBFIM (Bit 15) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX512T1023OCTGBFIM_Msk (0x8000UL) /*!< RX512T1023OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX1024TMAXOCTGBFIM_Pos (16UL) /*!< RX1024TMAXOCTGBFIM (Bit 16) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX1024TMAXOCTGBFIM_Msk (0x10000UL) /*!< RX1024TMAXOCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUCGFIM_Pos (17UL) /*!< RXUCGFIM (Bit 17) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUCGFIM_Msk (0x20000UL) /*!< RXUCGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXLENERFIM_Pos (18UL) /*!< RXLENERFIM (Bit 18) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXLENERFIM_Msk (0x40000UL) /*!< RXLENERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXORANGEFIM_Pos (19UL) /*!< RXORANGEFIM (Bit 19) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXORANGEFIM_Msk (0x80000UL) /*!< RXORANGEFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXPAUSFIM_Pos (20UL) /*!< RXPAUSFIM (Bit 20) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXPAUSFIM_Msk (0x100000UL) /*!< RXPAUSFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXFOVFIM_Pos (21UL) /*!< RXFOVFIM (Bit 21) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXFOVFIM_Msk (0x200000UL) /*!< RXFOVFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXVLANGBFIM_Pos (22UL) /*!< RXVLANGBFIM (Bit 22) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXVLANGBFIM_Msk (0x400000UL) /*!< RXVLANGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXWDOGFIM_Pos (23UL) /*!< RXWDOGFIM (Bit 23) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXWDOGFIM_Msk (0x800000UL) /*!< RXWDOGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRCVERRFIM_Pos (24UL) /*!< RXRCVERRFIM (Bit 24) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRCVERRFIM_Msk (0x1000000UL) /*!< RXRCVERRFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCTRLFIM_Pos (25UL) /*!< RXCTRLFIM (Bit 25) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCTRLFIM_Msk (0x2000000UL) /*!< RXCTRLFIM (Bitfield-Mask: 0x01) */ +/* ============================================== MMC_Transmit_Interrupt_Mask ============================================== */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBOCTIM_Pos (0UL) /*!< TXGBOCTIM (Bit 0) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBOCTIM_Msk (0x1UL) /*!< TXGBOCTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBFRMIM_Pos (1UL) /*!< TXGBFRMIM (Bit 1) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBFRMIM_Msk (0x2UL) /*!< TXGBFRMIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGFIM_Pos (2UL) /*!< TXBCGFIM (Bit 2) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGFIM_Msk (0x4UL) /*!< TXBCGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGFIM_Pos (3UL) /*!< TXMCGFIM (Bit 3) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGFIM_Msk (0x8UL) /*!< TXMCGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX64OCTGBFIM_Pos (4UL) /*!< TX64OCTGBFIM (Bit 4) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX64OCTGBFIM_Msk (0x10UL) /*!< TX64OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX65T127OCTGBFIM_Pos (5UL) /*!< TX65T127OCTGBFIM (Bit 5) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX65T127OCTGBFIM_Msk (0x20UL) /*!< TX65T127OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX128T255OCTGBFIM_Pos (6UL) /*!< TX128T255OCTGBFIM (Bit 6) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX128T255OCTGBFIM_Msk (0x40UL) /*!< TX128T255OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX256T511OCTGBFIM_Pos (7UL) /*!< TX256T511OCTGBFIM (Bit 7) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX256T511OCTGBFIM_Msk (0x80UL) /*!< TX256T511OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX512T1023OCTGBFIM_Pos (8UL) /*!< TX512T1023OCTGBFIM (Bit 8) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX512T1023OCTGBFIM_Msk (0x100UL) /*!< TX512T1023OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX1024TMAXOCTGBFIM_Pos (9UL) /*!< TX1024TMAXOCTGBFIM (Bit 9) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX1024TMAXOCTGBFIM_Msk (0x200UL) /*!< TX1024TMAXOCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUCGBFIM_Pos (10UL) /*!< TXUCGBFIM (Bit 10) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUCGBFIM_Msk (0x400UL) /*!< TXUCGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGBFIM_Pos (11UL) /*!< TXMCGBFIM (Bit 11) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGBFIM_Msk (0x800UL) /*!< TXMCGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGBFIM_Pos (12UL) /*!< TXBCGBFIM (Bit 12) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGBFIM_Msk (0x1000UL) /*!< TXBCGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUFLOWERFIM_Pos (13UL) /*!< TXUFLOWERFIM (Bit 13) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUFLOWERFIM_Msk (0x2000UL) /*!< TXUFLOWERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXSCOLGFIM_Pos (14UL) /*!< TXSCOLGFIM (Bit 14) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXSCOLGFIM_Msk (0x4000UL) /*!< TXSCOLGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCOLGFIM_Pos (15UL) /*!< TXMCOLGFIM (Bit 15) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCOLGFIM_Msk (0x8000UL) /*!< TXMCOLGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXDEFFIM_Pos (16UL) /*!< TXDEFFIM (Bit 16) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXDEFFIM_Msk (0x10000UL) /*!< TXDEFFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXLATCOLFIM_Pos (17UL) /*!< TXLATCOLFIM (Bit 17) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXLATCOLFIM_Msk (0x20000UL) /*!< TXLATCOLFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXCOLFIM_Pos (18UL) /*!< TXEXCOLFIM (Bit 18) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXCOLFIM_Msk (0x40000UL) /*!< TXEXCOLFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXCARERFIM_Pos (19UL) /*!< TXCARERFIM (Bit 19) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXCARERFIM_Msk (0x80000UL) /*!< TXCARERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGOCTIM_Pos (20UL) /*!< TXGOCTIM (Bit 20) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGOCTIM_Msk (0x100000UL) /*!< TXGOCTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGFRMIM_Pos (21UL) /*!< TXGFRMIM (Bit 21) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGFRMIM_Msk (0x200000UL) /*!< TXGFRMIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXDEFFIM_Pos (22UL) /*!< TXEXDEFFIM (Bit 22) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXDEFFIM_Msk (0x400000UL) /*!< TXEXDEFFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXPAUSFIM_Pos (23UL) /*!< TXPAUSFIM (Bit 23) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXPAUSFIM_Msk (0x800000UL) /*!< TXPAUSFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXVLANGFIM_Pos (24UL) /*!< TXVLANGFIM (Bit 24) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXVLANGFIM_Msk (0x1000000UL) /*!< TXVLANGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXOSIZEGFIM_Pos (25UL) /*!< TXOSIZEGFIM (Bit 25) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXOSIZEGFIM_Msk (0x2000000UL) /*!< TXOSIZEGFIM (Bitfield-Mask: 0x01) */ +/* ================================================ Tx_Octet_Count_Good_Bad ================================================ */ + #define R_GMAC_Tx_Octet_Count_Good_Bad_TXOCTGB_Pos (0UL) /*!< TXOCTGB (Bit 0) */ + #define R_GMAC_Tx_Octet_Count_Good_Bad_TXOCTGB_Msk (0xffffffffUL) /*!< TXOCTGB (Bitfield-Mask: 0xffffffff) */ +/* ================================================ Tx_Frame_Count_Good_Bad ================================================ */ + #define R_GMAC_Tx_Frame_Count_Good_Bad_TXFRMGB_Pos (0UL) /*!< TXFRMGB (Bit 0) */ + #define R_GMAC_Tx_Frame_Count_Good_Bad_TXFRMGB_Msk (0xffffffffUL) /*!< TXFRMGB (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Tx_Broadcast_Frames_Good ================================================ */ + #define R_GMAC_Tx_Broadcast_Frames_Good_TXBCASTG_Pos (0UL) /*!< TXBCASTG (Bit 0) */ + #define R_GMAC_Tx_Broadcast_Frames_Good_TXBCASTG_Msk (0xffffffffUL) /*!< TXBCASTG (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Tx_Multicast_Frames_Good ================================================ */ + #define R_GMAC_Tx_Multicast_Frames_Good_TXMCASTG_Pos (0UL) /*!< TXMCASTG (Bit 0) */ + #define R_GMAC_Tx_Multicast_Frames_Good_TXMCASTG_Msk (0xffffffffUL) /*!< TXMCASTG (Bitfield-Mask: 0xffffffff) */ +/* ============================================== Tx_64Octets_Frames_Good_Bad ============================================== */ + #define R_GMAC_Tx_64Octets_Frames_Good_Bad_TX64OCTGB_Pos (0UL) /*!< TX64OCTGB (Bit 0) */ + #define R_GMAC_Tx_64Octets_Frames_Good_Bad_TX64OCTGB_Msk (0xffffffffUL) /*!< TX64OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Tx_65To127Octets_Frames_Good_Bad ============================================ */ + #define R_GMAC_Tx_65To127Octets_Frames_Good_Bad_TX65_127OCTGB_Pos (0UL) /*!< TX65_127OCTGB (Bit 0) */ + #define R_GMAC_Tx_65To127Octets_Frames_Good_Bad_TX65_127OCTGB_Msk (0xffffffffUL) /*!< TX65_127OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Tx_128To255Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Tx_128To255Octets_Frames_Good_Bad_TX128_255OCTGB_Pos (0UL) /*!< TX128_255OCTGB (Bit 0) */ + #define R_GMAC_Tx_128To255Octets_Frames_Good_Bad_TX128_255OCTGB_Msk (0xffffffffUL) /*!< TX128_255OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Tx_256To511Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Tx_256To511Octets_Frames_Good_Bad_TX256_511OCTGB_Pos (0UL) /*!< TX256_511OCTGB (Bit 0) */ + #define R_GMAC_Tx_256To511Octets_Frames_Good_Bad_TX256_511OCTGB_Msk (0xffffffffUL) /*!< TX256_511OCTGB (Bitfield-Mask: 0xffffffff) */ +/* ========================================== Tx_512To1023Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Tx_512To1023Octets_Frames_Good_Bad_TX512_1023OCTGB_Pos (0UL) /*!< TX512_1023OCTGB (Bit 0) */ + #define R_GMAC_Tx_512To1023Octets_Frames_Good_Bad_TX512_1023OCTGB_Msk (0xffffffffUL) /*!< TX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */ +/* ========================================== Tx_1024ToMaxOctets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Tx_1024ToMaxOctets_Frames_Good_Bad_TX1024_MAXOCTGB_Pos (0UL) /*!< TX1024_MAXOCTGB (Bit 0) */ + #define R_GMAC_Tx_1024ToMaxOctets_Frames_Good_Bad_TX1024_MAXOCTGB_Msk (0xffffffffUL) /*!< TX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */ +/* ============================================== Tx_Unicast_Frames_Good_Bad =============================================== */ + #define R_GMAC_Tx_Unicast_Frames_Good_Bad_TXUCASTGB_Pos (0UL) /*!< TXUCASTGB (Bit 0) */ + #define R_GMAC_Tx_Unicast_Frames_Good_Bad_TXUCASTGB_Msk (0xffffffffUL) /*!< TXUCASTGB (Bitfield-Mask: 0xffffffff) */ +/* ============================================= Tx_Multicast_Frames_Good_Bad ============================================== */ + #define R_GMAC_Tx_Multicast_Frames_Good_Bad_TXMCASTGB_Pos (0UL) /*!< TXMCASTGB (Bit 0) */ + #define R_GMAC_Tx_Multicast_Frames_Good_Bad_TXMCASTGB_Msk (0xffffffffUL) /*!< TXMCASTGB (Bitfield-Mask: 0xffffffff) */ +/* ============================================= Tx_Broadcast_Frames_Good_Bad ============================================== */ + #define R_GMAC_Tx_Broadcast_Frames_Good_Bad_TXBCASTGB_Pos (0UL) /*!< TXBCASTGB (Bit 0) */ + #define R_GMAC_Tx_Broadcast_Frames_Good_Bad_TXBCASTGB_Msk (0xffffffffUL) /*!< TXBCASTGB (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Tx_Underflow_Error_Frames =============================================== */ + #define R_GMAC_Tx_Underflow_Error_Frames_TXUNDRFLW_Pos (0UL) /*!< TXUNDRFLW (Bit 0) */ + #define R_GMAC_Tx_Underflow_Error_Frames_TXUNDRFLW_Msk (0xffffUL) /*!< TXUNDRFLW (Bitfield-Mask: 0xffff) */ +/* ============================================ Tx_Single_Collision_Good_Frames ============================================ */ + #define R_GMAC_Tx_Single_Collision_Good_Frames_TXSNGLCOLG_Pos (0UL) /*!< TXSNGLCOLG (Bit 0) */ + #define R_GMAC_Tx_Single_Collision_Good_Frames_TXSNGLCOLG_Msk (0xffffUL) /*!< TXSNGLCOLG (Bitfield-Mask: 0xffff) */ +/* =========================================== Tx_Multiple_Collision_Good_Frames =========================================== */ + #define R_GMAC_Tx_Multiple_Collision_Good_Frames_TXMULTCOLG_Pos (0UL) /*!< TXMULTCOLG (Bit 0) */ + #define R_GMAC_Tx_Multiple_Collision_Good_Frames_TXMULTCOLG_Msk (0xffffUL) /*!< TXMULTCOLG (Bitfield-Mask: 0xffff) */ +/* ================================================== Tx_Deferred_Frames =================================================== */ + #define R_GMAC_Tx_Deferred_Frames_TXDEFRD_Pos (0UL) /*!< TXDEFRD (Bit 0) */ + #define R_GMAC_Tx_Deferred_Frames_TXDEFRD_Msk (0xffffUL) /*!< TXDEFRD (Bitfield-Mask: 0xffff) */ +/* =============================================== Tx_Late_Collision_Frames ================================================ */ + #define R_GMAC_Tx_Late_Collision_Frames_TXLATECOL_Pos (0UL) /*!< TXLATECOL (Bit 0) */ + #define R_GMAC_Tx_Late_Collision_Frames_TXLATECOL_Msk (0xffffUL) /*!< TXLATECOL (Bitfield-Mask: 0xffff) */ +/* ============================================= Tx_Excessive_Collision_Frames ============================================= */ + #define R_GMAC_Tx_Excessive_Collision_Frames_TXEXSCOL_Pos (0UL) /*!< TXEXSCOL (Bit 0) */ + #define R_GMAC_Tx_Excessive_Collision_Frames_TXEXSCOL_Msk (0xffffUL) /*!< TXEXSCOL (Bitfield-Mask: 0xffff) */ +/* ================================================ Tx_Carrier_Error_Frames ================================================ */ + #define R_GMAC_Tx_Carrier_Error_Frames_TXCARR_Pos (0UL) /*!< TXCARR (Bit 0) */ + #define R_GMAC_Tx_Carrier_Error_Frames_TXCARR_Msk (0xffffUL) /*!< TXCARR (Bitfield-Mask: 0xffff) */ +/* ================================================== Tx_Octet_Count_Good ================================================== */ + #define R_GMAC_Tx_Octet_Count_Good_TXOCTG_Pos (0UL) /*!< TXOCTG (Bit 0) */ + #define R_GMAC_Tx_Octet_Count_Good_TXOCTG_Msk (0xffffffffUL) /*!< TXOCTG (Bitfield-Mask: 0xffffffff) */ +/* ================================================== Tx_Frame_Count_Good ================================================== */ + #define R_GMAC_Tx_Frame_Count_Good_TXFRMG_Pos (0UL) /*!< TXFRMG (Bit 0) */ + #define R_GMAC_Tx_Frame_Count_Good_TXFRMG_Msk (0xffffffffUL) /*!< TXFRMG (Bitfield-Mask: 0xffffffff) */ +/* ============================================== Tx_Excessive_Deferral_Error ============================================== */ + #define R_GMAC_Tx_Excessive_Deferral_Error_TXEXSDEF_Pos (0UL) /*!< TXEXSDEF (Bit 0) */ + #define R_GMAC_Tx_Excessive_Deferral_Error_TXEXSDEF_Msk (0xffffUL) /*!< TXEXSDEF (Bitfield-Mask: 0xffff) */ +/* ==================================================== Tx_Pause_Frames ==================================================== */ + #define R_GMAC_Tx_Pause_Frames_TXPAUSE_Pos (0UL) /*!< TXPAUSE (Bit 0) */ + #define R_GMAC_Tx_Pause_Frames_TXPAUSE_Msk (0xffffUL) /*!< TXPAUSE (Bitfield-Mask: 0xffff) */ +/* ================================================== Tx_VLAN_Frames_Good ================================================== */ + #define R_GMAC_Tx_VLAN_Frames_Good_TXVLANG_Pos (0UL) /*!< TXVLANG (Bit 0) */ + #define R_GMAC_Tx_VLAN_Frames_Good_TXVLANG_Msk (0xffffffffUL) /*!< TXVLANG (Bitfield-Mask: 0xffffffff) */ +/* ================================================= Tx_OSize_Frames_Good ================================================== */ + #define R_GMAC_Tx_OSize_Frames_Good_TXOSIZG_Pos (0UL) /*!< TXOSIZG (Bit 0) */ + #define R_GMAC_Tx_OSize_Frames_Good_TXOSIZG_Msk (0xffffUL) /*!< TXOSIZG (Bitfield-Mask: 0xffff) */ +/* =============================================== Rx_Frames_Count_Good_Bad ================================================ */ + #define R_GMAC_Rx_Frames_Count_Good_Bad_RXFRMGB_Pos (0UL) /*!< RXFRMGB (Bit 0) */ + #define R_GMAC_Rx_Frames_Count_Good_Bad_RXFRMGB_Msk (0xffffffffUL) /*!< RXFRMGB (Bitfield-Mask: 0xffffffff) */ +/* ================================================ Rx_Octet_Count_Good_Bad ================================================ */ + #define R_GMAC_Rx_Octet_Count_Good_Bad_RXOCTGB_Pos (0UL) /*!< RXOCTGB (Bit 0) */ + #define R_GMAC_Rx_Octet_Count_Good_Bad_RXOCTGB_Msk (0xffffffffUL) /*!< RXOCTGB (Bitfield-Mask: 0xffffffff) */ +/* ================================================== Rx_Octet_Count_Good ================================================== */ + #define R_GMAC_Rx_Octet_Count_Good_RXOCTG_Pos (0UL) /*!< RXOCTG (Bit 0) */ + #define R_GMAC_Rx_Octet_Count_Good_RXOCTG_Msk (0xffffffffUL) /*!< RXOCTG (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Rx_Broadcast_Frames_Good ================================================ */ + #define R_GMAC_Rx_Broadcast_Frames_Good_RXBCASTG_Pos (0UL) /*!< RXBCASTG (Bit 0) */ + #define R_GMAC_Rx_Broadcast_Frames_Good_RXBCASTG_Msk (0xffffffffUL) /*!< RXBCASTG (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Rx_Multicast_Frames_Good ================================================ */ + #define R_GMAC_Rx_Multicast_Frames_Good_RXMCASTG_Pos (0UL) /*!< RXMCASTG (Bit 0) */ + #define R_GMAC_Rx_Multicast_Frames_Good_RXMCASTG_Msk (0xffffffffUL) /*!< RXMCASTG (Bitfield-Mask: 0xffffffff) */ +/* ================================================== Rx_CRC_Error_Frames ================================================== */ + #define R_GMAC_Rx_CRC_Error_Frames_RXCRCERR_Pos (0UL) /*!< RXCRCERR (Bit 0) */ + #define R_GMAC_Rx_CRC_Error_Frames_RXCRCERR_Msk (0xffffUL) /*!< RXCRCERR (Bitfield-Mask: 0xffff) */ +/* =============================================== Rx_Alignment_Error_Frames =============================================== */ + #define R_GMAC_Rx_Alignment_Error_Frames_RXALGNERR_Pos (0UL) /*!< RXALGNERR (Bit 0) */ + #define R_GMAC_Rx_Alignment_Error_Frames_RXALGNERR_Msk (0xffffUL) /*!< RXALGNERR (Bitfield-Mask: 0xffff) */ +/* ================================================= Rx_Runt_Error_Frames ================================================== */ + #define R_GMAC_Rx_Runt_Error_Frames_RXRUNTERR_Pos (0UL) /*!< RXRUNTERR (Bit 0) */ + #define R_GMAC_Rx_Runt_Error_Frames_RXRUNTERR_Msk (0xffffUL) /*!< RXRUNTERR (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_Jabber_Error_Frames ================================================= */ + #define R_GMAC_Rx_Jabber_Error_Frames_RXJABERR_Pos (0UL) /*!< RXJABERR (Bit 0) */ + #define R_GMAC_Rx_Jabber_Error_Frames_RXJABERR_Msk (0xffffUL) /*!< RXJABERR (Bitfield-Mask: 0xffff) */ +/* =============================================== Rx_Undersize_Frames_Good ================================================ */ + #define R_GMAC_Rx_Undersize_Frames_Good_RXUNDERSZG_Pos (0UL) /*!< RXUNDERSZG (Bit 0) */ + #define R_GMAC_Rx_Undersize_Frames_Good_RXUNDERSZG_Msk (0xffffUL) /*!< RXUNDERSZG (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_Oversize_Frames_Good ================================================ */ + #define R_GMAC_Rx_Oversize_Frames_Good_RXOVERSZG_Pos (0UL) /*!< RXOVERSZG (Bit 0) */ + #define R_GMAC_Rx_Oversize_Frames_Good_RXOVERSZG_Msk (0xffffUL) /*!< RXOVERSZG (Bitfield-Mask: 0xffff) */ +/* ============================================== Rx_64Octets_Frames_Good_Bad ============================================== */ + #define R_GMAC_Rx_64Octets_Frames_Good_Bad_RX64OCTGB_Pos (0UL) /*!< RX64OCTGB (Bit 0) */ + #define R_GMAC_Rx_64Octets_Frames_Good_Bad_RX64OCTGB_Msk (0xffffffffUL) /*!< RX64OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Rx_65To127Octets_Frames_Good_Bad ============================================ */ + #define R_GMAC_Rx_65To127Octets_Frames_Good_Bad_RX65_127OCTGB_Pos (0UL) /*!< RX65_127OCTGB (Bit 0) */ + #define R_GMAC_Rx_65To127Octets_Frames_Good_Bad_RX65_127OCTGB_Msk (0xffffffffUL) /*!< RX65_127OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Rx_128To255Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Rx_128To255Octets_Frames_Good_Bad_RX128_255OCTGB_Pos (0UL) /*!< RX128_255OCTGB (Bit 0) */ + #define R_GMAC_Rx_128To255Octets_Frames_Good_Bad_RX128_255OCTGB_Msk (0xffffffffUL) /*!< RX128_255OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Rx_256To511Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Rx_256To511Octets_Frames_Good_Bad_RX256_511OCTGB_Pos (0UL) /*!< RX256_511OCTGB (Bit 0) */ + #define R_GMAC_Rx_256To511Octets_Frames_Good_Bad_RX256_511OCTGB_Msk (0xffffffffUL) /*!< RX256_511OCTGB (Bitfield-Mask: 0xffffffff) */ +/* ========================================== Rx_512To1023Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Rx_512To1023Octets_Frames_Good_Bad_RX512_1023OCTGB_Pos (0UL) /*!< RX512_1023OCTGB (Bit 0) */ + #define R_GMAC_Rx_512To1023Octets_Frames_Good_Bad_RX512_1023OCTGB_Msk (0xffffffffUL) /*!< RX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */ +/* ========================================== Rx_1024ToMaxOctets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Rx_1024ToMaxOctets_Frames_Good_Bad_RX1024_MAXOCTGB_Pos (0UL) /*!< RX1024_MAXOCTGB (Bit 0) */ + #define R_GMAC_Rx_1024ToMaxOctets_Frames_Good_Bad_RX1024_MAXOCTGB_Msk (0xffffffffUL) /*!< RX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */ +/* ================================================ Rx_Unicast_Frames_Good ================================================= */ + #define R_GMAC_Rx_Unicast_Frames_Good_RXUCASTG_Pos (0UL) /*!< RXUCASTG (Bit 0) */ + #define R_GMAC_Rx_Unicast_Frames_Good_RXUCASTG_Msk (0xffffffffUL) /*!< RXUCASTG (Bitfield-Mask: 0xffffffff) */ +/* ================================================ Rx_Length_Error_Frames ================================================= */ + #define R_GMAC_Rx_Length_Error_Frames_RXLENERR_Pos (0UL) /*!< RXLENERR (Bit 0) */ + #define R_GMAC_Rx_Length_Error_Frames_RXLENERR_Msk (0xffffUL) /*!< RXLENERR (Bitfield-Mask: 0xffff) */ +/* ============================================== Rx_Out_Of_Range_Type_Frames ============================================== */ + #define R_GMAC_Rx_Out_Of_Range_Type_Frames_RXOUTOFRNG_Pos (0UL) /*!< RXOUTOFRNG (Bit 0) */ + #define R_GMAC_Rx_Out_Of_Range_Type_Frames_RXOUTOFRNG_Msk (0xffffUL) /*!< RXOUTOFRNG (Bitfield-Mask: 0xffff) */ +/* ==================================================== Rx_Pause_Frames ==================================================== */ + #define R_GMAC_Rx_Pause_Frames_RXPAUSEFRM_Pos (0UL) /*!< RXPAUSEFRM (Bit 0) */ + #define R_GMAC_Rx_Pause_Frames_RXPAUSEFRM_Msk (0xffffUL) /*!< RXPAUSEFRM (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_FIFO_Overflow_Frames ================================================ */ + #define R_GMAC_Rx_FIFO_Overflow_Frames_RXFIFOOVFL_Pos (0UL) /*!< RXFIFOOVFL (Bit 0) */ + #define R_GMAC_Rx_FIFO_Overflow_Frames_RXFIFOOVFL_Msk (0xffffUL) /*!< RXFIFOOVFL (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_VLAN_Frames_Good_Bad ================================================ */ + #define R_GMAC_Rx_VLAN_Frames_Good_Bad_RXVLANFRGB_Pos (0UL) /*!< RXVLANFRGB (Bit 0) */ + #define R_GMAC_Rx_VLAN_Frames_Good_Bad_RXVLANFRGB_Msk (0xffffffffUL) /*!< RXVLANFRGB (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Rx_Watchdog_Error_Frames ================================================ */ + #define R_GMAC_Rx_Watchdog_Error_Frames_RXWDGERR_Pos (0UL) /*!< RXWDGERR (Bit 0) */ + #define R_GMAC_Rx_Watchdog_Error_Frames_RXWDGERR_Msk (0xffffUL) /*!< RXWDGERR (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_Receive_Error_Frames ================================================ */ + #define R_GMAC_Rx_Receive_Error_Frames_RXRCVERR_Pos (0UL) /*!< RXRCVERR (Bit 0) */ + #define R_GMAC_Rx_Receive_Error_Frames_RXRCVERR_Msk (0xffffUL) /*!< RXRCVERR (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_Control_Frames_Good ================================================= */ + #define R_GMAC_Rx_Control_Frames_Good_RXCTRLG_Pos (0UL) /*!< RXCTRLG (Bit 0) */ + #define R_GMAC_Rx_Control_Frames_Good_RXCTRLG_Msk (0xffffffffUL) /*!< RXCTRLG (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GMACTRGSEL ======================================================= */ + #define R_GMAC_GMACTRGSEL_TRGSEL_Pos (0UL) /*!< TRGSEL (Bit 0) */ + #define R_GMAC_GMACTRGSEL_TRGSEL_Msk (0x3UL) /*!< TRGSEL (Bitfield-Mask: 0x03) */ +/* ==================================================== HASH_TABLE_REG ===================================================== */ + #define R_GMAC_HASH_TABLE_REG_HT_Pos (0UL) /*!< HT (Bit 0) */ + #define R_GMAC_HASH_TABLE_REG_HT_Msk (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== VLAN_Hash_Table_Reg ================================================== */ + #define R_GMAC_VLAN_Hash_Table_Reg_VLHT_Pos (0UL) /*!< VLHT (Bit 0) */ + #define R_GMAC_VLAN_Hash_Table_Reg_VLHT_Msk (0xffffUL) /*!< VLHT (Bitfield-Mask: 0xffff) */ +/* =================================================== Timestamp_Control =================================================== */ + #define R_GMAC_Timestamp_Control_TSENA_Pos (0UL) /*!< TSENA (Bit 0) */ + #define R_GMAC_Timestamp_Control_TSENA_Msk (0x1UL) /*!< TSENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSCFUPDT_Pos (1UL) /*!< TSCFUPDT (Bit 1) */ + #define R_GMAC_Timestamp_Control_TSCFUPDT_Msk (0x2UL) /*!< TSCFUPDT (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSINIT_Pos (2UL) /*!< TSINIT (Bit 2) */ + #define R_GMAC_Timestamp_Control_TSINIT_Msk (0x4UL) /*!< TSINIT (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSUPDT_Pos (3UL) /*!< TSUPDT (Bit 3) */ + #define R_GMAC_Timestamp_Control_TSUPDT_Msk (0x8UL) /*!< TSUPDT (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSTRIG_Pos (4UL) /*!< TSTRIG (Bit 4) */ + #define R_GMAC_Timestamp_Control_TSTRIG_Msk (0x10UL) /*!< TSTRIG (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSADDREG_Pos (5UL) /*!< TSADDREG (Bit 5) */ + #define R_GMAC_Timestamp_Control_TSADDREG_Msk (0x20UL) /*!< TSADDREG (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSENALL_Pos (8UL) /*!< TSENALL (Bit 8) */ + #define R_GMAC_Timestamp_Control_TSENALL_Msk (0x100UL) /*!< TSENALL (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSCTRLSSR_Pos (9UL) /*!< TSCTRLSSR (Bit 9) */ + #define R_GMAC_Timestamp_Control_TSCTRLSSR_Msk (0x200UL) /*!< TSCTRLSSR (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSVER2ENA_Pos (10UL) /*!< TSVER2ENA (Bit 10) */ + #define R_GMAC_Timestamp_Control_TSVER2ENA_Msk (0x400UL) /*!< TSVER2ENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSIPENA_Pos (11UL) /*!< TSIPENA (Bit 11) */ + #define R_GMAC_Timestamp_Control_TSIPENA_Msk (0x800UL) /*!< TSIPENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSIPV6ENA_Pos (12UL) /*!< TSIPV6ENA (Bit 12) */ + #define R_GMAC_Timestamp_Control_TSIPV6ENA_Msk (0x1000UL) /*!< TSIPV6ENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSIPV4ENA_Pos (13UL) /*!< TSIPV4ENA (Bit 13) */ + #define R_GMAC_Timestamp_Control_TSIPV4ENA_Msk (0x2000UL) /*!< TSIPV4ENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSEVNTENA_Pos (14UL) /*!< TSEVNTENA (Bit 14) */ + #define R_GMAC_Timestamp_Control_TSEVNTENA_Msk (0x4000UL) /*!< TSEVNTENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSMSTRENA_Pos (15UL) /*!< TSMSTRENA (Bit 15) */ + #define R_GMAC_Timestamp_Control_TSMSTRENA_Msk (0x8000UL) /*!< TSMSTRENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_SNAPTYPSEL_Pos (16UL) /*!< SNAPTYPSEL (Bit 16) */ + #define R_GMAC_Timestamp_Control_SNAPTYPSEL_Msk (0x30000UL) /*!< SNAPTYPSEL (Bitfield-Mask: 0x03) */ + #define R_GMAC_Timestamp_Control_TSENMACADDR_Pos (18UL) /*!< TSENMACADDR (Bit 18) */ + #define R_GMAC_Timestamp_Control_TSENMACADDR_Msk (0x40000UL) /*!< TSENMACADDR (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_ATSFC_Pos (24UL) /*!< ATSFC (Bit 24) */ + #define R_GMAC_Timestamp_Control_ATSFC_Msk (0x1000000UL) /*!< ATSFC (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_ATSEN0_Pos (25UL) /*!< ATSEN0 (Bit 25) */ + #define R_GMAC_Timestamp_Control_ATSEN0_Msk (0x2000000UL) /*!< ATSEN0 (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_ATSEN1_Pos (26UL) /*!< ATSEN1 (Bit 26) */ + #define R_GMAC_Timestamp_Control_ATSEN1_Msk (0x4000000UL) /*!< ATSEN1 (Bitfield-Mask: 0x01) */ +/* ================================================= Sub_Second_Increment ================================================== */ + #define R_GMAC_Sub_Second_Increment_SSINC_Pos (0UL) /*!< SSINC (Bit 0) */ + #define R_GMAC_Sub_Second_Increment_SSINC_Msk (0xffUL) /*!< SSINC (Bitfield-Mask: 0xff) */ +/* ================================================== System_Time_Seconds ================================================== */ + #define R_GMAC_System_Time_Seconds_TSS_Pos (0UL) /*!< TSS (Bit 0) */ + #define R_GMAC_System_Time_Seconds_TSS_Msk (0xffffffffUL) /*!< TSS (Bitfield-Mask: 0xffffffff) */ +/* ================================================ System_Time_Nanoseconds ================================================ */ + #define R_GMAC_System_Time_Nanoseconds_TSSS_Pos (0UL) /*!< TSSS (Bit 0) */ + #define R_GMAC_System_Time_Nanoseconds_TSSS_Msk (0x7fffffffUL) /*!< TSSS (Bitfield-Mask: 0x7fffffff) */ +/* ============================================== System_Time_Seconds_Update =============================================== */ + #define R_GMAC_System_Time_Seconds_Update_TSS_Pos (0UL) /*!< TSS (Bit 0) */ + #define R_GMAC_System_Time_Seconds_Update_TSS_Msk (0xffffffffUL) /*!< TSS (Bitfield-Mask: 0xffffffff) */ +/* ============================================ System_Time_Nanoseconds_Update ============================================= */ + #define R_GMAC_System_Time_Nanoseconds_Update_TSSS_Pos (0UL) /*!< TSSS (Bit 0) */ + #define R_GMAC_System_Time_Nanoseconds_Update_TSSS_Msk (0x7fffffffUL) /*!< TSSS (Bitfield-Mask: 0x7fffffff) */ + #define R_GMAC_System_Time_Nanoseconds_Update_ADDSUB_Pos (31UL) /*!< ADDSUB (Bit 31) */ + #define R_GMAC_System_Time_Nanoseconds_Update_ADDSUB_Msk (0x80000000UL) /*!< ADDSUB (Bitfield-Mask: 0x01) */ +/* =================================================== Timestamp_Addend ==================================================== */ + #define R_GMAC_Timestamp_Addend_TSAR_Pos (0UL) /*!< TSAR (Bit 0) */ + #define R_GMAC_Timestamp_Addend_TSAR_Msk (0xffffffffUL) /*!< TSAR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== Target_Time_Seconds ================================================== */ + #define R_GMAC_Target_Time_Seconds_TSTR_Pos (0UL) /*!< TSTR (Bit 0) */ + #define R_GMAC_Target_Time_Seconds_TSTR_Msk (0xffffffffUL) /*!< TSTR (Bitfield-Mask: 0xffffffff) */ +/* ================================================ Target_Time_Nanoseconds ================================================ */ + #define R_GMAC_Target_Time_Nanoseconds_TTSLO_Pos (0UL) /*!< TTSLO (Bit 0) */ + #define R_GMAC_Target_Time_Nanoseconds_TTSLO_Msk (0x7fffffffUL) /*!< TTSLO (Bitfield-Mask: 0x7fffffff) */ + #define R_GMAC_Target_Time_Nanoseconds_TRGTBUSY_Pos (31UL) /*!< TRGTBUSY (Bit 31) */ + #define R_GMAC_Target_Time_Nanoseconds_TRGTBUSY_Msk (0x80000000UL) /*!< TRGTBUSY (Bitfield-Mask: 0x01) */ +/* =================================================== Timestamp_Status ==================================================== */ + #define R_GMAC_Timestamp_Status_AUXTSTRIG_Pos (2UL) /*!< AUXTSTRIG (Bit 2) */ + #define R_GMAC_Timestamp_Status_AUXTSTRIG_Msk (0x4UL) /*!< AUXTSTRIG (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Status_ATSSTN_Pos (16UL) /*!< ATSSTN (Bit 16) */ + #define R_GMAC_Timestamp_Status_ATSSTN_Msk (0xf0000UL) /*!< ATSSTN (Bitfield-Mask: 0x0f) */ + #define R_GMAC_Timestamp_Status_ATSSTM_Pos (24UL) /*!< ATSSTM (Bit 24) */ + #define R_GMAC_Timestamp_Status_ATSSTM_Msk (0x1000000UL) /*!< ATSSTM (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Status_ATSNS_Pos (25UL) /*!< ATSNS (Bit 25) */ + #define R_GMAC_Timestamp_Status_ATSNS_Msk (0x3e000000UL) /*!< ATSNS (Bitfield-Mask: 0x1f) */ +/* ============================================ Auxiliary_Timestamp_Nanoseconds ============================================ */ + #define R_GMAC_Auxiliary_Timestamp_Nanoseconds_AUXTSLO_Pos (0UL) /*!< AUXTSLO (Bit 0) */ + #define R_GMAC_Auxiliary_Timestamp_Nanoseconds_AUXTSLO_Msk (0x7fffffffUL) /*!< AUXTSLO (Bitfield-Mask: 0x7fffffff) */ +/* ============================================== Auxiliary_Timestamp_Seconds ============================================== */ + #define R_GMAC_Auxiliary_Timestamp_Seconds_AUXTSHI_Pos (0UL) /*!< AUXTSHI (Bit 0) */ + #define R_GMAC_Auxiliary_Timestamp_Seconds_AUXTSHI_Msk (0xffffffffUL) /*!< AUXTSHI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR16_H ======================================================== */ + #define R_GMAC_MAR16_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR16_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR16_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR16_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR16_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR16_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR16_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR16_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR16_L ======================================================== */ + #define R_GMAC_MAR16_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR16_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR17_H ======================================================== */ + #define R_GMAC_MAR17_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR17_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR17_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR17_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR17_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR17_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR17_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR17_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR17_L ======================================================== */ + #define R_GMAC_MAR17_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR17_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= Bus_Mode ======================================================== */ + #define R_GMAC_Bus_Mode_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_GMAC_Bus_Mode_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_DA_Pos (1UL) /*!< DA (Bit 1) */ + #define R_GMAC_Bus_Mode_DA_Msk (0x2UL) /*!< DA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_DSL_Pos (2UL) /*!< DSL (Bit 2) */ + #define R_GMAC_Bus_Mode_DSL_Msk (0x7cUL) /*!< DSL (Bitfield-Mask: 0x1f) */ + #define R_GMAC_Bus_Mode_ATDS_Pos (7UL) /*!< ATDS (Bit 7) */ + #define R_GMAC_Bus_Mode_ATDS_Msk (0x80UL) /*!< ATDS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_PBL_Pos (8UL) /*!< PBL (Bit 8) */ + #define R_GMAC_Bus_Mode_PBL_Msk (0x3f00UL) /*!< PBL (Bitfield-Mask: 0x3f) */ + #define R_GMAC_Bus_Mode_PR_Pos (14UL) /*!< PR (Bit 14) */ + #define R_GMAC_Bus_Mode_PR_Msk (0xc000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GMAC_Bus_Mode_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GMAC_Bus_Mode_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_RPBL_Pos (17UL) /*!< RPBL (Bit 17) */ + #define R_GMAC_Bus_Mode_RPBL_Msk (0x7e0000UL) /*!< RPBL (Bitfield-Mask: 0x3f) */ + #define R_GMAC_Bus_Mode_USP_Pos (23UL) /*!< USP (Bit 23) */ + #define R_GMAC_Bus_Mode_USP_Msk (0x800000UL) /*!< USP (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_PBLx8_Pos (24UL) /*!< PBLx8 (Bit 24) */ + #define R_GMAC_Bus_Mode_PBLx8_Msk (0x1000000UL) /*!< PBLx8 (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_AAL_Pos (25UL) /*!< AAL (Bit 25) */ + #define R_GMAC_Bus_Mode_AAL_Msk (0x2000000UL) /*!< AAL (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_MB_Pos (26UL) /*!< MB (Bit 26) */ + #define R_GMAC_Bus_Mode_MB_Msk (0x4000000UL) /*!< MB (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_TXPR_Pos (27UL) /*!< TXPR (Bit 27) */ + #define R_GMAC_Bus_Mode_TXPR_Msk (0x8000000UL) /*!< TXPR (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_PRWG_Pos (28UL) /*!< PRWG (Bit 28) */ + #define R_GMAC_Bus_Mode_PRWG_Msk (0x30000000UL) /*!< PRWG (Bitfield-Mask: 0x03) */ + #define R_GMAC_Bus_Mode_RIB_Pos (31UL) /*!< RIB (Bit 31) */ + #define R_GMAC_Bus_Mode_RIB_Msk (0x80000000UL) /*!< RIB (Bitfield-Mask: 0x01) */ +/* ================================================= Transmit_Poll_Demand ================================================== */ + #define R_GMAC_Transmit_Poll_Demand_TPD_Pos (0UL) /*!< TPD (Bit 0) */ + #define R_GMAC_Transmit_Poll_Demand_TPD_Msk (0xffffffffUL) /*!< TPD (Bitfield-Mask: 0xffffffff) */ +/* ================================================== Receive_Poll_Demand ================================================== */ + #define R_GMAC_Receive_Poll_Demand_RPD_Pos (0UL) /*!< RPD (Bit 0) */ + #define R_GMAC_Receive_Poll_Demand_RPD_Msk (0xffffffffUL) /*!< RPD (Bitfield-Mask: 0xffffffff) */ +/* ============================================ Receive_Descriptor_List_Address ============================================ */ + #define R_GMAC_Receive_Descriptor_List_Address_RDESLA_32bit_Pos (2UL) /*!< RDESLA_32bit (Bit 2) */ + #define R_GMAC_Receive_Descriptor_List_Address_RDESLA_32bit_Msk (0xfffffffcUL) /*!< RDESLA_32bit (Bitfield-Mask: 0x3fffffff) */ +/* =========================================== Transmit_Descriptor_List_Address ============================================ */ + #define R_GMAC_Transmit_Descriptor_List_Address_TDESLA_32bit_Pos (2UL) /*!< TDESLA_32bit (Bit 2) */ + #define R_GMAC_Transmit_Descriptor_List_Address_TDESLA_32bit_Msk (0xfffffffcUL) /*!< TDESLA_32bit (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================== Status ========================================================= */ + #define R_GMAC_Status_TI_Pos (0UL) /*!< TI (Bit 0) */ + #define R_GMAC_Status_TI_Msk (0x1UL) /*!< TI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_TPS_Pos (1UL) /*!< TPS (Bit 1) */ + #define R_GMAC_Status_TPS_Msk (0x2UL) /*!< TPS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_TU_Pos (2UL) /*!< TU (Bit 2) */ + #define R_GMAC_Status_TU_Msk (0x4UL) /*!< TU (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_TJT_Pos (3UL) /*!< TJT (Bit 3) */ + #define R_GMAC_Status_TJT_Msk (0x8UL) /*!< TJT (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_OVF_Pos (4UL) /*!< OVF (Bit 4) */ + #define R_GMAC_Status_OVF_Msk (0x10UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_UNF_Pos (5UL) /*!< UNF (Bit 5) */ + #define R_GMAC_Status_UNF_Msk (0x20UL) /*!< UNF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_GMAC_Status_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_RU_Pos (7UL) /*!< RU (Bit 7) */ + #define R_GMAC_Status_RU_Msk (0x80UL) /*!< RU (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_RPS_Pos (8UL) /*!< RPS (Bit 8) */ + #define R_GMAC_Status_RPS_Msk (0x100UL) /*!< RPS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_RWT_Pos (9UL) /*!< RWT (Bit 9) */ + #define R_GMAC_Status_RWT_Msk (0x200UL) /*!< RWT (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_ETI_Pos (10UL) /*!< ETI (Bit 10) */ + #define R_GMAC_Status_ETI_Msk (0x400UL) /*!< ETI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_FBI_Pos (13UL) /*!< FBI (Bit 13) */ + #define R_GMAC_Status_FBI_Msk (0x2000UL) /*!< FBI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_ERI_Pos (14UL) /*!< ERI (Bit 14) */ + #define R_GMAC_Status_ERI_Msk (0x4000UL) /*!< ERI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_AIS_Pos (15UL) /*!< AIS (Bit 15) */ + #define R_GMAC_Status_AIS_Msk (0x8000UL) /*!< AIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_NIS_Pos (16UL) /*!< NIS (Bit 16) */ + #define R_GMAC_Status_NIS_Msk (0x10000UL) /*!< NIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_RS_Pos (17UL) /*!< RS (Bit 17) */ + #define R_GMAC_Status_RS_Msk (0xe0000UL) /*!< RS (Bitfield-Mask: 0x07) */ + #define R_GMAC_Status_TS_Pos (20UL) /*!< TS (Bit 20) */ + #define R_GMAC_Status_TS_Msk (0x700000UL) /*!< TS (Bitfield-Mask: 0x07) */ + #define R_GMAC_Status_EB_Pos (23UL) /*!< EB (Bit 23) */ + #define R_GMAC_Status_EB_Msk (0x3800000UL) /*!< EB (Bitfield-Mask: 0x07) */ + #define R_GMAC_Status_GMI_Pos (27UL) /*!< GMI (Bit 27) */ + #define R_GMAC_Status_GMI_Msk (0x8000000UL) /*!< GMI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_GPI_Pos (28UL) /*!< GPI (Bit 28) */ + #define R_GMAC_Status_GPI_Msk (0x10000000UL) /*!< GPI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_TTI_Pos (29UL) /*!< TTI (Bit 29) */ + #define R_GMAC_Status_TTI_Msk (0x20000000UL) /*!< TTI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_GLPII_Pos (30UL) /*!< GLPII (Bit 30) */ + #define R_GMAC_Status_GLPII_Msk (0x40000000UL) /*!< GLPII (Bitfield-Mask: 0x01) */ +/* ==================================================== Operation_Mode ===================================================== */ + #define R_GMAC_Operation_Mode_SR_Pos (1UL) /*!< SR (Bit 1) */ + #define R_GMAC_Operation_Mode_SR_Msk (0x2UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_OSF_Pos (2UL) /*!< OSF (Bit 2) */ + #define R_GMAC_Operation_Mode_OSF_Msk (0x4UL) /*!< OSF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_RTC_Pos (3UL) /*!< RTC (Bit 3) */ + #define R_GMAC_Operation_Mode_RTC_Msk (0x18UL) /*!< RTC (Bitfield-Mask: 0x03) */ + #define R_GMAC_Operation_Mode_DGF_Pos (5UL) /*!< DGF (Bit 5) */ + #define R_GMAC_Operation_Mode_DGF_Msk (0x20UL) /*!< DGF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_FUF_Pos (6UL) /*!< FUF (Bit 6) */ + #define R_GMAC_Operation_Mode_FUF_Msk (0x40UL) /*!< FUF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_FEF_Pos (7UL) /*!< FEF (Bit 7) */ + #define R_GMAC_Operation_Mode_FEF_Msk (0x80UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_EFC_Pos (8UL) /*!< EFC (Bit 8) */ + #define R_GMAC_Operation_Mode_EFC_Msk (0x100UL) /*!< EFC (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_RFA_Pos (9UL) /*!< RFA (Bit 9) */ + #define R_GMAC_Operation_Mode_RFA_Msk (0x600UL) /*!< RFA (Bitfield-Mask: 0x03) */ + #define R_GMAC_Operation_Mode_RFD_Pos (11UL) /*!< RFD (Bit 11) */ + #define R_GMAC_Operation_Mode_RFD_Msk (0x1800UL) /*!< RFD (Bitfield-Mask: 0x03) */ + #define R_GMAC_Operation_Mode_ST_Pos (13UL) /*!< ST (Bit 13) */ + #define R_GMAC_Operation_Mode_ST_Msk (0x2000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_TTC_Pos (14UL) /*!< TTC (Bit 14) */ + #define R_GMAC_Operation_Mode_TTC_Msk (0x1c000UL) /*!< TTC (Bitfield-Mask: 0x07) */ + #define R_GMAC_Operation_Mode_FTF_Pos (20UL) /*!< FTF (Bit 20) */ + #define R_GMAC_Operation_Mode_FTF_Msk (0x100000UL) /*!< FTF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_TSF_Pos (21UL) /*!< TSF (Bit 21) */ + #define R_GMAC_Operation_Mode_TSF_Msk (0x200000UL) /*!< TSF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_RSF_Pos (25UL) /*!< RSF (Bit 25) */ + #define R_GMAC_Operation_Mode_RSF_Msk (0x2000000UL) /*!< RSF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_DT_Pos (26UL) /*!< DT (Bit 26) */ + #define R_GMAC_Operation_Mode_DT_Msk (0x4000000UL) /*!< DT (Bitfield-Mask: 0x01) */ +/* =================================================== Interrupt_Enable ==================================================== */ + #define R_GMAC_Interrupt_Enable_TIE_Pos (0UL) /*!< TIE (Bit 0) */ + #define R_GMAC_Interrupt_Enable_TIE_Msk (0x1UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_TSE_Pos (1UL) /*!< TSE (Bit 1) */ + #define R_GMAC_Interrupt_Enable_TSE_Msk (0x2UL) /*!< TSE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_TUE_Pos (2UL) /*!< TUE (Bit 2) */ + #define R_GMAC_Interrupt_Enable_TUE_Msk (0x4UL) /*!< TUE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_TJE_Pos (3UL) /*!< TJE (Bit 3) */ + #define R_GMAC_Interrupt_Enable_TJE_Msk (0x8UL) /*!< TJE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_OVE_Pos (4UL) /*!< OVE (Bit 4) */ + #define R_GMAC_Interrupt_Enable_OVE_Msk (0x10UL) /*!< OVE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_UNE_Pos (5UL) /*!< UNE (Bit 5) */ + #define R_GMAC_Interrupt_Enable_UNE_Msk (0x20UL) /*!< UNE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_GMAC_Interrupt_Enable_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_RUE_Pos (7UL) /*!< RUE (Bit 7) */ + #define R_GMAC_Interrupt_Enable_RUE_Msk (0x80UL) /*!< RUE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_RSE_Pos (8UL) /*!< RSE (Bit 8) */ + #define R_GMAC_Interrupt_Enable_RSE_Msk (0x100UL) /*!< RSE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_RWE_Pos (9UL) /*!< RWE (Bit 9) */ + #define R_GMAC_Interrupt_Enable_RWE_Msk (0x200UL) /*!< RWE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_ETE_Pos (10UL) /*!< ETE (Bit 10) */ + #define R_GMAC_Interrupt_Enable_ETE_Msk (0x400UL) /*!< ETE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_FBE_Pos (13UL) /*!< FBE (Bit 13) */ + #define R_GMAC_Interrupt_Enable_FBE_Msk (0x2000UL) /*!< FBE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_ERE_Pos (14UL) /*!< ERE (Bit 14) */ + #define R_GMAC_Interrupt_Enable_ERE_Msk (0x4000UL) /*!< ERE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_AIE_Pos (15UL) /*!< AIE (Bit 15) */ + #define R_GMAC_Interrupt_Enable_AIE_Msk (0x8000UL) /*!< AIE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_NIE_Pos (16UL) /*!< NIE (Bit 16) */ + #define R_GMAC_Interrupt_Enable_NIE_Msk (0x10000UL) /*!< NIE (Bitfield-Mask: 0x01) */ +/* ======================================= Missed_Frame_And_Buffer_Overflow_Counter ======================================== */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISFRMCNT_Pos (0UL) /*!< MISFRMCNT (Bit 0) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISFRMCNT_Msk (0xffffUL) /*!< MISFRMCNT (Bitfield-Mask: 0xffff) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISCNTOVF_Pos (16UL) /*!< MISCNTOVF (Bit 16) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISCNTOVF_Msk (0x10000UL) /*!< MISCNTOVF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFFRMCNT_Pos (17UL) /*!< OVFFRMCNT (Bit 17) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFFRMCNT_Msk (0xffe0000UL) /*!< OVFFRMCNT (Bitfield-Mask: 0x7ff) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFCNTOVF_Pos (28UL) /*!< OVFCNTOVF (Bit 28) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFCNTOVF_Msk (0x10000000UL) /*!< OVFCNTOVF (Bitfield-Mask: 0x01) */ +/* =========================================== Receive_Interrupt_Watchdog_Timer ============================================ */ + #define R_GMAC_Receive_Interrupt_Watchdog_Timer_RIWT_Pos (0UL) /*!< RIWT (Bit 0) */ + #define R_GMAC_Receive_Interrupt_Watchdog_Timer_RIWT_Msk (0xffUL) /*!< RIWT (Bitfield-Mask: 0xff) */ +/* ===================================================== AXI_Bus_Mode ====================================================== */ + #define R_GMAC_AXI_Bus_Mode_UNDEF_Pos (0UL) /*!< UNDEF (Bit 0) */ + #define R_GMAC_AXI_Bus_Mode_UNDEF_Msk (0x1UL) /*!< UNDEF (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_BLEN4_Pos (1UL) /*!< BLEN4 (Bit 1) */ + #define R_GMAC_AXI_Bus_Mode_BLEN4_Msk (0x2UL) /*!< BLEN4 (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_BLEN8_Pos (2UL) /*!< BLEN8 (Bit 2) */ + #define R_GMAC_AXI_Bus_Mode_BLEN8_Msk (0x4UL) /*!< BLEN8 (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_BLEN16_Pos (3UL) /*!< BLEN16 (Bit 3) */ + #define R_GMAC_AXI_Bus_Mode_BLEN16_Msk (0x8UL) /*!< BLEN16 (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_AXI_AAL_Pos (12UL) /*!< AXI_AAL (Bit 12) */ + #define R_GMAC_AXI_Bus_Mode_AXI_AAL_Msk (0x1000UL) /*!< AXI_AAL (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_ONEKBBE_Pos (13UL) /*!< ONEKBBE (Bit 13) */ + #define R_GMAC_AXI_Bus_Mode_ONEKBBE_Msk (0x2000UL) /*!< ONEKBBE (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_RD_OSR_LMT_Pos (16UL) /*!< RD_OSR_LMT (Bit 16) */ + #define R_GMAC_AXI_Bus_Mode_RD_OSR_LMT_Msk (0x30000UL) /*!< RD_OSR_LMT (Bitfield-Mask: 0x03) */ + #define R_GMAC_AXI_Bus_Mode_WR_OSR_LMT_Pos (20UL) /*!< WR_OSR_LMT (Bit 20) */ + #define R_GMAC_AXI_Bus_Mode_WR_OSR_LMT_Msk (0x300000UL) /*!< WR_OSR_LMT (Bitfield-Mask: 0x03) */ + #define R_GMAC_AXI_Bus_Mode_LPI_XIT_FRM_Pos (30UL) /*!< LPI_XIT_FRM (Bit 30) */ + #define R_GMAC_AXI_Bus_Mode_LPI_XIT_FRM_Msk (0x40000000UL) /*!< LPI_XIT_FRM (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_EN_LPI_Pos (31UL) /*!< EN_LPI (Bit 31) */ + #define R_GMAC_AXI_Bus_Mode_EN_LPI_Msk (0x80000000UL) /*!< EN_LPI (Bitfield-Mask: 0x01) */ +/* ====================================================== AXI_Status ======================================================= */ + #define R_GMAC_AXI_Status_AXWHSTS_Pos (0UL) /*!< AXWHSTS (Bit 0) */ + #define R_GMAC_AXI_Status_AXWHSTS_Msk (0x1UL) /*!< AXWHSTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Status_AXIRDSTS_Pos (1UL) /*!< AXIRDSTS (Bit 1) */ + #define R_GMAC_AXI_Status_AXIRDSTS_Msk (0x2UL) /*!< AXIRDSTS (Bitfield-Mask: 0x01) */ +/* =========================================== Current_Host_Transmit_Descriptor ============================================ */ + #define R_GMAC_Current_Host_Transmit_Descriptor_CURTDESAPTR_Pos (0UL) /*!< CURTDESAPTR (Bit 0) */ + #define R_GMAC_Current_Host_Transmit_Descriptor_CURTDESAPTR_Msk (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff) */ +/* ============================================ Current_Host_Receive_Descriptor ============================================ */ + #define R_GMAC_Current_Host_Receive_Descriptor_CURRDESAPTR_Pos (0UL) /*!< CURRDESAPTR (Bit 0) */ + #define R_GMAC_Current_Host_Receive_Descriptor_CURRDESAPTR_Msk (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff) */ +/* ========================================= Current_Host_Transmit_Buffer_Address ========================================== */ + #define R_GMAC_Current_Host_Transmit_Buffer_Address_CURTBUFAPTR_Pos (0UL) /*!< CURTBUFAPTR (Bit 0) */ + #define R_GMAC_Current_Host_Transmit_Buffer_Address_CURTBUFAPTR_Msk (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff) */ +/* ========================================== Current_Host_Receive_Buffer_Address ========================================== */ + #define R_GMAC_Current_Host_Receive_Buffer_Address_CURRBUFAPTR_Pos (0UL) /*!< CURRBUFAPTR (Bit 0) */ + #define R_GMAC_Current_Host_Receive_Buffer_Address_CURRBUFAPTR_Msk (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== HW_Feature ======================================================= */ + #define R_GMAC_HW_Feature_MIISEL_Pos (0UL) /*!< MIISEL (Bit 0) */ + #define R_GMAC_HW_Feature_MIISEL_Msk (0x1UL) /*!< MIISEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_GMIISEL_Pos (1UL) /*!< GMIISEL (Bit 1) */ + #define R_GMAC_HW_Feature_GMIISEL_Msk (0x2UL) /*!< GMIISEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_HDSEL_Pos (2UL) /*!< HDSEL (Bit 2) */ + #define R_GMAC_HW_Feature_HDSEL_Msk (0x4UL) /*!< HDSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_EXTHASHEN_Pos (3UL) /*!< EXTHASHEN (Bit 3) */ + #define R_GMAC_HW_Feature_EXTHASHEN_Msk (0x8UL) /*!< EXTHASHEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_HASHSEL_Pos (4UL) /*!< HASHSEL (Bit 4) */ + #define R_GMAC_HW_Feature_HASHSEL_Msk (0x10UL) /*!< HASHSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_ADDMACADRSEL_Pos (5UL) /*!< ADDMACADRSEL (Bit 5) */ + #define R_GMAC_HW_Feature_ADDMACADRSEL_Msk (0x20UL) /*!< ADDMACADRSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_L3L4FLTREN_Pos (7UL) /*!< L3L4FLTREN (Bit 7) */ + #define R_GMAC_HW_Feature_L3L4FLTREN_Msk (0x80UL) /*!< L3L4FLTREN (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_SMASEL_Pos (8UL) /*!< SMASEL (Bit 8) */ + #define R_GMAC_HW_Feature_SMASEL_Msk (0x100UL) /*!< SMASEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_RWKSEL_Pos (9UL) /*!< RWKSEL (Bit 9) */ + #define R_GMAC_HW_Feature_RWKSEL_Msk (0x200UL) /*!< RWKSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_MGKSEL_Pos (10UL) /*!< MGKSEL (Bit 10) */ + #define R_GMAC_HW_Feature_MGKSEL_Msk (0x400UL) /*!< MGKSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_MMCSEL_Pos (11UL) /*!< MMCSEL (Bit 11) */ + #define R_GMAC_HW_Feature_MMCSEL_Msk (0x800UL) /*!< MMCSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_TSVER1SEL_Pos (12UL) /*!< TSVER1SEL (Bit 12) */ + #define R_GMAC_HW_Feature_TSVER1SEL_Msk (0x1000UL) /*!< TSVER1SEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_TSVER2SEL_Pos (13UL) /*!< TSVER2SEL (Bit 13) */ + #define R_GMAC_HW_Feature_TSVER2SEL_Msk (0x2000UL) /*!< TSVER2SEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_EEESEL_Pos (14UL) /*!< EEESEL (Bit 14) */ + #define R_GMAC_HW_Feature_EEESEL_Msk (0x4000UL) /*!< EEESEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_AVSEL_Pos (15UL) /*!< AVSEL (Bit 15) */ + #define R_GMAC_HW_Feature_AVSEL_Msk (0x8000UL) /*!< AVSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_TXCOESEL_Pos (16UL) /*!< TXCOESEL (Bit 16) */ + #define R_GMAC_HW_Feature_TXCOESEL_Msk (0x10000UL) /*!< TXCOESEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_RXTYP1COE_Pos (17UL) /*!< RXTYP1COE (Bit 17) */ + #define R_GMAC_HW_Feature_RXTYP1COE_Msk (0x20000UL) /*!< RXTYP1COE (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_RXTYP2COE_Pos (18UL) /*!< RXTYP2COE (Bit 18) */ + #define R_GMAC_HW_Feature_RXTYP2COE_Msk (0x40000UL) /*!< RXTYP2COE (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_RXFIFOSIZE_Pos (19UL) /*!< RXFIFOSIZE (Bit 19) */ + #define R_GMAC_HW_Feature_RXFIFOSIZE_Msk (0x80000UL) /*!< RXFIFOSIZE (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_RXCHCNT_Pos (20UL) /*!< RXCHCNT (Bit 20) */ + #define R_GMAC_HW_Feature_RXCHCNT_Msk (0x300000UL) /*!< RXCHCNT (Bitfield-Mask: 0x03) */ + #define R_GMAC_HW_Feature_TXCHCNT_Pos (22UL) /*!< TXCHCNT (Bit 22) */ + #define R_GMAC_HW_Feature_TXCHCNT_Msk (0xc00000UL) /*!< TXCHCNT (Bitfield-Mask: 0x03) */ + #define R_GMAC_HW_Feature_ENHDESSEL_Pos (24UL) /*!< ENHDESSEL (Bit 24) */ + #define R_GMAC_HW_Feature_ENHDESSEL_Msk (0x1000000UL) /*!< ENHDESSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_INTTSEN_Pos (25UL) /*!< INTTSEN (Bit 25) */ + #define R_GMAC_HW_Feature_INTTSEN_Msk (0x2000000UL) /*!< INTTSEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_FLEXIPPSEN_Pos (26UL) /*!< FLEXIPPSEN (Bit 26) */ + #define R_GMAC_HW_Feature_FLEXIPPSEN_Msk (0x4000000UL) /*!< FLEXIPPSEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_SAVLANINS_Pos (27UL) /*!< SAVLANINS (Bit 27) */ + #define R_GMAC_HW_Feature_SAVLANINS_Msk (0x8000000UL) /*!< SAVLANINS (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_ACTPHYIF_Pos (28UL) /*!< ACTPHYIF (Bit 28) */ + #define R_GMAC_HW_Feature_ACTPHYIF_Msk (0x70000000UL) /*!< ACTPHYIF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRCMD ========================================================= */ +/* ======================================================== MODCTRL ======================================================== */ + #define R_ETHSS_MODCTRL_SW_MODE_Pos (0UL) /*!< SW_MODE (Bit 0) */ + #define R_ETHSS_MODCTRL_SW_MODE_Msk (0x1UL) /*!< SW_MODE (Bitfield-Mask: 0x01) */ +/* ======================================================= PTPMCTRL ======================================================== */ + #define R_ETHSS_PTPMCTRL_PTP_PLS_RSTn_Pos (16UL) /*!< PTP_PLS_RSTn (Bit 16) */ + #define R_ETHSS_PTPMCTRL_PTP_PLS_RSTn_Msk (0x10000UL) /*!< PTP_PLS_RSTn (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYLNK ========================================================= */ + #define R_ETHSS_PHYLNK_CATLNK_Pos (4UL) /*!< CATLNK (Bit 4) */ + #define R_ETHSS_PHYLNK_CATLNK_Msk (0x70UL) /*!< CATLNK (Bitfield-Mask: 0x07) */ +/* ======================================================= CONVCTRL ======================================================== */ + #define R_ETHSS_CONVCTRL_CONV_MODE_Pos (0UL) /*!< CONV_MODE (Bit 0) */ + #define R_ETHSS_CONVCTRL_CONV_MODE_Msk (0x1fUL) /*!< CONV_MODE (Bitfield-Mask: 0x1f) */ + #define R_ETHSS_CONVCTRL_FULLD_Pos (8UL) /*!< FULLD (Bit 8) */ + #define R_ETHSS_CONVCTRL_FULLD_Msk (0x100UL) /*!< FULLD (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CONVCTRL_RMII_RX_ER_EN_Pos (9UL) /*!< RMII_RX_ER_EN (Bit 9) */ + #define R_ETHSS_CONVCTRL_RMII_RX_ER_EN_Msk (0x200UL) /*!< RMII_RX_ER_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CONVCTRL_RMII_CRS_MODE_Pos (10UL) /*!< RMII_CRS_MODE (Bit 10) */ + #define R_ETHSS_CONVCTRL_RMII_CRS_MODE_Msk (0x400UL) /*!< RMII_CRS_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CONVCTRL_RGMII_LINK_Pos (12UL) /*!< RGMII_LINK (Bit 12) */ + #define R_ETHSS_CONVCTRL_RGMII_LINK_Msk (0x1000UL) /*!< RGMII_LINK (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CONVCTRL_RGMII_DUPLEX_Pos (13UL) /*!< RGMII_DUPLEX (Bit 13) */ + #define R_ETHSS_CONVCTRL_RGMII_DUPLEX_Msk (0x2000UL) /*!< RGMII_DUPLEX (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CONVCTRL_RGMII_SPEED_Pos (14UL) /*!< RGMII_SPEED (Bit 14) */ + #define R_ETHSS_CONVCTRL_RGMII_SPEED_Msk (0xc000UL) /*!< RGMII_SPEED (Bitfield-Mask: 0x03) */ +/* ======================================================== CONVRST ======================================================== */ + #define R_ETHSS_CONVRST_PHYIR_Pos (0UL) /*!< PHYIR (Bit 0) */ + #define R_ETHSS_CONVRST_PHYIR_Msk (0x7UL) /*!< PHYIR (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_ESC_INI ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== ECATOFFADR ======================================================= */ + #define R_ESC_INI_ECATOFFADR_OADD_Pos (0UL) /*!< OADD (Bit 0) */ + #define R_ESC_INI_ECATOFFADR_OADD_Msk (0x1fUL) /*!< OADD (Bitfield-Mask: 0x1f) */ +/* ======================================================= ECATOPMOD ======================================================= */ + #define R_ESC_INI_ECATOPMOD_EEPROMSIZE_Pos (0UL) /*!< EEPROMSIZE (Bit 0) */ + #define R_ESC_INI_ECATOPMOD_EEPROMSIZE_Msk (0x1UL) /*!< EEPROMSIZE (Bitfield-Mask: 0x01) */ +/* ======================================================= ECATDBGC ======================================================== */ + #define R_ESC_INI_ECATDBGC_TXSFT0_Pos (0UL) /*!< TXSFT0 (Bit 0) */ + #define R_ESC_INI_ECATDBGC_TXSFT0_Msk (0x3UL) /*!< TXSFT0 (Bitfield-Mask: 0x03) */ + #define R_ESC_INI_ECATDBGC_TXSFT1_Pos (2UL) /*!< TXSFT1 (Bit 2) */ + #define R_ESC_INI_ECATDBGC_TXSFT1_Msk (0xcUL) /*!< TXSFT1 (Bitfield-Mask: 0x03) */ + #define R_ESC_INI_ECATDBGC_TXSFT2_Pos (4UL) /*!< TXSFT2 (Bit 4) */ + #define R_ESC_INI_ECATDBGC_TXSFT2_Msk (0x30UL) /*!< TXSFT2 (Bitfield-Mask: 0x03) */ +/* ====================================================== ECATTRGSEL ======================================================= */ + #define R_ESC_INI_ECATTRGSEL_TRGSEL0_Pos (0UL) /*!< TRGSEL0 (Bit 0) */ + #define R_ESC_INI_ECATTRGSEL_TRGSEL0_Msk (0x1UL) /*!< TRGSEL0 (Bitfield-Mask: 0x01) */ + #define R_ESC_INI_ECATTRGSEL_TRGSEL1_Pos (1UL) /*!< TRGSEL1 (Bit 1) */ + #define R_ESC_INI_ECATTRGSEL_TRGSEL1_Msk (0x2UL) /*!< TRGSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GMAC_PTP ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_ESC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TYPE ========================================================== */ + #define R_ESC_TYPE_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ + #define R_ESC_TYPE_TYPE_Msk (0xffUL) /*!< TYPE (Bitfield-Mask: 0xff) */ +/* ======================================================= REVISION ======================================================== */ + #define R_ESC_REVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_ESC_REVISION_REV_Msk (0xffUL) /*!< REV (Bitfield-Mask: 0xff) */ +/* ========================================================= BUILD ========================================================= */ + #define R_ESC_BUILD_BUILD_Pos (0UL) /*!< BUILD (Bit 0) */ + #define R_ESC_BUILD_BUILD_Msk (0xffUL) /*!< BUILD (Bitfield-Mask: 0xff) */ +/* ======================================================= FMMU_NUM ======================================================== */ + #define R_ESC_FMMU_NUM_NUMFMMU_Pos (0UL) /*!< NUMFMMU (Bit 0) */ + #define R_ESC_FMMU_NUM_NUMFMMU_Msk (0xffUL) /*!< NUMFMMU (Bitfield-Mask: 0xff) */ +/* ===================================================== SYNC_MANAGER ====================================================== */ + #define R_ESC_SYNC_MANAGER_NUMSYNC_Pos (0UL) /*!< NUMSYNC (Bit 0) */ + #define R_ESC_SYNC_MANAGER_NUMSYNC_Msk (0xffUL) /*!< NUMSYNC (Bitfield-Mask: 0xff) */ +/* ======================================================= RAM_SIZE ======================================================== */ + #define R_ESC_RAM_SIZE_RAMSIZE_Pos (0UL) /*!< RAMSIZE (Bit 0) */ + #define R_ESC_RAM_SIZE_RAMSIZE_Msk (0xffUL) /*!< RAMSIZE (Bitfield-Mask: 0xff) */ +/* ======================================================= PORT_DESC ======================================================= */ + #define R_ESC_PORT_DESC_P0_Pos (0UL) /*!< P0 (Bit 0) */ + #define R_ESC_PORT_DESC_P0_Msk (0x3UL) /*!< P0 (Bitfield-Mask: 0x03) */ + #define R_ESC_PORT_DESC_P1_Pos (2UL) /*!< P1 (Bit 2) */ + #define R_ESC_PORT_DESC_P1_Msk (0xcUL) /*!< P1 (Bitfield-Mask: 0x03) */ + #define R_ESC_PORT_DESC_P2_Pos (4UL) /*!< P2 (Bit 4) */ + #define R_ESC_PORT_DESC_P2_Msk (0x30UL) /*!< P2 (Bitfield-Mask: 0x03) */ + #define R_ESC_PORT_DESC_P3_Pos (6UL) /*!< P3 (Bit 6) */ + #define R_ESC_PORT_DESC_P3_Msk (0xc0UL) /*!< P3 (Bitfield-Mask: 0x03) */ +/* ======================================================== FEATURE ======================================================== */ + #define R_ESC_FEATURE_FMMU_Pos (0UL) /*!< FMMU (Bit 0) */ + #define R_ESC_FEATURE_FMMU_Msk (0x1UL) /*!< FMMU (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_DC_Pos (2UL) /*!< DC (Bit 2) */ + #define R_ESC_FEATURE_DC_Msk (0x4UL) /*!< DC (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_DCWID_Pos (3UL) /*!< DCWID (Bit 3) */ + #define R_ESC_FEATURE_DCWID_Msk (0x8UL) /*!< DCWID (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_LINKDECMII_Pos (6UL) /*!< LINKDECMII (Bit 6) */ + #define R_ESC_FEATURE_LINKDECMII_Msk (0x40UL) /*!< LINKDECMII (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_FCS_Pos (7UL) /*!< FCS (Bit 7) */ + #define R_ESC_FEATURE_FCS_Msk (0x80UL) /*!< FCS (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_DCSYNC_Pos (8UL) /*!< DCSYNC (Bit 8) */ + #define R_ESC_FEATURE_DCSYNC_Msk (0x100UL) /*!< DCSYNC (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_LRW_Pos (9UL) /*!< LRW (Bit 9) */ + #define R_ESC_FEATURE_LRW_Msk (0x200UL) /*!< LRW (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_RWSUPP_Pos (10UL) /*!< RWSUPP (Bit 10) */ + #define R_ESC_FEATURE_RWSUPP_Msk (0x400UL) /*!< RWSUPP (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_FSCONFIG_Pos (11UL) /*!< FSCONFIG (Bit 11) */ + #define R_ESC_FEATURE_FSCONFIG_Msk (0x800UL) /*!< FSCONFIG (Bitfield-Mask: 0x01) */ +/* ====================================================== STATION_ADR ====================================================== */ + #define R_ESC_STATION_ADR_NODADDR_Pos (0UL) /*!< NODADDR (Bit 0) */ + #define R_ESC_STATION_ADR_NODADDR_Msk (0xffffUL) /*!< NODADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== STATION_ALIAS ===================================================== */ + #define R_ESC_STATION_ALIAS_NODALIADDR_Pos (0UL) /*!< NODALIADDR (Bit 0) */ + #define R_ESC_STATION_ALIAS_NODALIADDR_Msk (0xffffUL) /*!< NODALIADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== WR_REG_ENABLE ===================================================== */ + #define R_ESC_WR_REG_ENABLE_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_ESC_WR_REG_ENABLE_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ==================================================== WR_REG_PROTECT ===================================================== */ + #define R_ESC_WR_REG_PROTECT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_ESC_WR_REG_PROTECT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ===================================================== ESC_WR_ENABLE ===================================================== */ + #define R_ESC_ESC_WR_ENABLE_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_ESC_ESC_WR_ENABLE_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ==================================================== ESC_WR_PROTECT ===================================================== */ + #define R_ESC_ESC_WR_PROTECT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_ESC_ESC_WR_PROTECT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* =================================================== ESC_RESET_ECAT_R ==================================================== */ + #define R_ESC_ESC_RESET_ECAT_R_RESET_ECAT_Pos (0UL) /*!< RESET_ECAT (Bit 0) */ + #define R_ESC_ESC_RESET_ECAT_R_RESET_ECAT_Msk (0x3UL) /*!< RESET_ECAT (Bitfield-Mask: 0x03) */ +/* =================================================== ESC_RESET_ECAT_W ==================================================== */ + #define R_ESC_ESC_RESET_ECAT_W_RESET_ECAT_Pos (0UL) /*!< RESET_ECAT (Bit 0) */ + #define R_ESC_ESC_RESET_ECAT_W_RESET_ECAT_Msk (0xffUL) /*!< RESET_ECAT (Bitfield-Mask: 0xff) */ +/* ==================================================== ESC_RESET_PDI_R ==================================================== */ + #define R_ESC_ESC_RESET_PDI_R_RESET_PDI_Pos (0UL) /*!< RESET_PDI (Bit 0) */ + #define R_ESC_ESC_RESET_PDI_R_RESET_PDI_Msk (0x3UL) /*!< RESET_PDI (Bitfield-Mask: 0x03) */ +/* ==================================================== ESC_RESET_PDI_W ==================================================== */ + #define R_ESC_ESC_RESET_PDI_W_RESET_PDI_Pos (0UL) /*!< RESET_PDI (Bit 0) */ + #define R_ESC_ESC_RESET_PDI_W_RESET_PDI_Msk (0xffUL) /*!< RESET_PDI (Bitfield-Mask: 0xff) */ +/* ==================================================== ESC_DL_CONTROL ===================================================== */ + #define R_ESC_ESC_DL_CONTROL_FWDRULE_Pos (0UL) /*!< FWDRULE (Bit 0) */ + #define R_ESC_ESC_DL_CONTROL_FWDRULE_Msk (0x1UL) /*!< FWDRULE (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_CONTROL_TEMPUSE_Pos (1UL) /*!< TEMPUSE (Bit 1) */ + #define R_ESC_ESC_DL_CONTROL_TEMPUSE_Msk (0x2UL) /*!< TEMPUSE (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_CONTROL_LP0_Pos (8UL) /*!< LP0 (Bit 8) */ + #define R_ESC_ESC_DL_CONTROL_LP0_Msk (0x300UL) /*!< LP0 (Bitfield-Mask: 0x03) */ + #define R_ESC_ESC_DL_CONTROL_LP1_Pos (10UL) /*!< LP1 (Bit 10) */ + #define R_ESC_ESC_DL_CONTROL_LP1_Msk (0xc00UL) /*!< LP1 (Bitfield-Mask: 0x03) */ + #define R_ESC_ESC_DL_CONTROL_LP2_Pos (12UL) /*!< LP2 (Bit 12) */ + #define R_ESC_ESC_DL_CONTROL_LP2_Msk (0x3000UL) /*!< LP2 (Bitfield-Mask: 0x03) */ + #define R_ESC_ESC_DL_CONTROL_LP3_Pos (14UL) /*!< LP3 (Bit 14) */ + #define R_ESC_ESC_DL_CONTROL_LP3_Msk (0xc000UL) /*!< LP3 (Bitfield-Mask: 0x03) */ + #define R_ESC_ESC_DL_CONTROL_RXFIFO_Pos (16UL) /*!< RXFIFO (Bit 16) */ + #define R_ESC_ESC_DL_CONTROL_RXFIFO_Msk (0x70000UL) /*!< RXFIFO (Bitfield-Mask: 0x07) */ + #define R_ESC_ESC_DL_CONTROL_STAALIAS_Pos (24UL) /*!< STAALIAS (Bit 24) */ + #define R_ESC_ESC_DL_CONTROL_STAALIAS_Msk (0x1000000UL) /*!< STAALIAS (Bitfield-Mask: 0x01) */ +/* ================================================== PHYSICAL_RW_OFFSET =================================================== */ + #define R_ESC_PHYSICAL_RW_OFFSET_RWOFFSET_Pos (0UL) /*!< RWOFFSET (Bit 0) */ + #define R_ESC_PHYSICAL_RW_OFFSET_RWOFFSET_Msk (0xffffUL) /*!< RWOFFSET (Bitfield-Mask: 0xffff) */ +/* ===================================================== ESC_DL_STATUS ===================================================== */ + #define R_ESC_ESC_DL_STATUS_PDIOPE_Pos (0UL) /*!< PDIOPE (Bit 0) */ + #define R_ESC_ESC_DL_STATUS_PDIOPE_Msk (0x1UL) /*!< PDIOPE (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_PDIWDST_Pos (1UL) /*!< PDIWDST (Bit 1) */ + #define R_ESC_ESC_DL_STATUS_PDIWDST_Msk (0x2UL) /*!< PDIWDST (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_ENHLINKD_Pos (2UL) /*!< ENHLINKD (Bit 2) */ + #define R_ESC_ESC_DL_STATUS_ENHLINKD_Msk (0x4UL) /*!< ENHLINKD (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_PHYP0_Pos (4UL) /*!< PHYP0 (Bit 4) */ + #define R_ESC_ESC_DL_STATUS_PHYP0_Msk (0x10UL) /*!< PHYP0 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_PHYP1_Pos (5UL) /*!< PHYP1 (Bit 5) */ + #define R_ESC_ESC_DL_STATUS_PHYP1_Msk (0x20UL) /*!< PHYP1 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_PHYP2_Pos (6UL) /*!< PHYP2 (Bit 6) */ + #define R_ESC_ESC_DL_STATUS_PHYP2_Msk (0x40UL) /*!< PHYP2 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_PHYP3_Pos (7UL) /*!< PHYP3 (Bit 7) */ + #define R_ESC_ESC_DL_STATUS_PHYP3_Msk (0x80UL) /*!< PHYP3 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_LP0_Pos (8UL) /*!< LP0 (Bit 8) */ + #define R_ESC_ESC_DL_STATUS_LP0_Msk (0x100UL) /*!< LP0 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_COMP0_Pos (9UL) /*!< COMP0 (Bit 9) */ + #define R_ESC_ESC_DL_STATUS_COMP0_Msk (0x200UL) /*!< COMP0 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_LP1_Pos (10UL) /*!< LP1 (Bit 10) */ + #define R_ESC_ESC_DL_STATUS_LP1_Msk (0x400UL) /*!< LP1 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_COMP1_Pos (11UL) /*!< COMP1 (Bit 11) */ + #define R_ESC_ESC_DL_STATUS_COMP1_Msk (0x800UL) /*!< COMP1 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_LP2_Pos (12UL) /*!< LP2 (Bit 12) */ + #define R_ESC_ESC_DL_STATUS_LP2_Msk (0x1000UL) /*!< LP2 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_COMP2_Pos (13UL) /*!< COMP2 (Bit 13) */ + #define R_ESC_ESC_DL_STATUS_COMP2_Msk (0x2000UL) /*!< COMP2 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_LP3_Pos (14UL) /*!< LP3 (Bit 14) */ + #define R_ESC_ESC_DL_STATUS_LP3_Msk (0x4000UL) /*!< LP3 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_COMP3_Pos (15UL) /*!< COMP3 (Bit 15) */ + #define R_ESC_ESC_DL_STATUS_COMP3_Msk (0x8000UL) /*!< COMP3 (Bitfield-Mask: 0x01) */ +/* ====================================================== AL_CONTROL ======================================================= */ + #define R_ESC_AL_CONTROL_INISTATE_Pos (0UL) /*!< INISTATE (Bit 0) */ + #define R_ESC_AL_CONTROL_INISTATE_Msk (0xfUL) /*!< INISTATE (Bitfield-Mask: 0x0f) */ + #define R_ESC_AL_CONTROL_ERRINDACK_Pos (4UL) /*!< ERRINDACK (Bit 4) */ + #define R_ESC_AL_CONTROL_ERRINDACK_Msk (0x10UL) /*!< ERRINDACK (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_CONTROL_DEVICEID_Pos (5UL) /*!< DEVICEID (Bit 5) */ + #define R_ESC_AL_CONTROL_DEVICEID_Msk (0x20UL) /*!< DEVICEID (Bitfield-Mask: 0x01) */ +/* ======================================================= AL_STATUS ======================================================= */ + #define R_ESC_AL_STATUS_ACTSTATE_Pos (0UL) /*!< ACTSTATE (Bit 0) */ + #define R_ESC_AL_STATUS_ACTSTATE_Msk (0xfUL) /*!< ACTSTATE (Bitfield-Mask: 0x0f) */ + #define R_ESC_AL_STATUS_ERR_Pos (4UL) /*!< ERR (Bit 4) */ + #define R_ESC_AL_STATUS_ERR_Msk (0x10UL) /*!< ERR (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_STATUS_DEVICEID_Pos (5UL) /*!< DEVICEID (Bit 5) */ + #define R_ESC_AL_STATUS_DEVICEID_Msk (0x20UL) /*!< DEVICEID (Bitfield-Mask: 0x01) */ +/* ==================================================== AL_STATUS_CODE ===================================================== */ + #define R_ESC_AL_STATUS_CODE_STATUSCODE_Pos (0UL) /*!< STATUSCODE (Bit 0) */ + #define R_ESC_AL_STATUS_CODE_STATUSCODE_Msk (0xffffUL) /*!< STATUSCODE (Bitfield-Mask: 0xffff) */ +/* =================================================== RUN_LED_OVERRIDE ==================================================== */ + #define R_ESC_RUN_LED_OVERRIDE_LEDCODE_Pos (0UL) /*!< LEDCODE (Bit 0) */ + #define R_ESC_RUN_LED_OVERRIDE_LEDCODE_Msk (0xfUL) /*!< LEDCODE (Bitfield-Mask: 0x0f) */ + #define R_ESC_RUN_LED_OVERRIDE_OVERRIDEEN_Pos (4UL) /*!< OVERRIDEEN (Bit 4) */ + #define R_ESC_RUN_LED_OVERRIDE_OVERRIDEEN_Msk (0x10UL) /*!< OVERRIDEEN (Bitfield-Mask: 0x01) */ +/* =================================================== ERR_LED_OVERRIDE ==================================================== */ + #define R_ESC_ERR_LED_OVERRIDE_LEDCODE_Pos (0UL) /*!< LEDCODE (Bit 0) */ + #define R_ESC_ERR_LED_OVERRIDE_LEDCODE_Msk (0xfUL) /*!< LEDCODE (Bitfield-Mask: 0x0f) */ + #define R_ESC_ERR_LED_OVERRIDE_OVERRIDEEN_Pos (4UL) /*!< OVERRIDEEN (Bit 4) */ + #define R_ESC_ERR_LED_OVERRIDE_OVERRIDEEN_Msk (0x10UL) /*!< OVERRIDEEN (Bitfield-Mask: 0x01) */ +/* ====================================================== PDI_CONTROL ====================================================== */ + #define R_ESC_PDI_CONTROL_PDI_Pos (0UL) /*!< PDI (Bit 0) */ + #define R_ESC_PDI_CONTROL_PDI_Msk (0xffUL) /*!< PDI (Bitfield-Mask: 0xff) */ +/* ====================================================== ESC_CONFIG ======================================================= */ + #define R_ESC_ESC_CONFIG_DEVEMU_Pos (0UL) /*!< DEVEMU (Bit 0) */ + #define R_ESC_ESC_CONFIG_DEVEMU_Msk (0x1UL) /*!< DEVEMU (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_ENLALLP_Pos (1UL) /*!< ENLALLP (Bit 1) */ + #define R_ESC_ESC_CONFIG_ENLALLP_Msk (0x2UL) /*!< ENLALLP (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_DCSYNC_Pos (2UL) /*!< DCSYNC (Bit 2) */ + #define R_ESC_ESC_CONFIG_DCSYNC_Msk (0x4UL) /*!< DCSYNC (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_DCLATCH_Pos (3UL) /*!< DCLATCH (Bit 3) */ + #define R_ESC_ESC_CONFIG_DCLATCH_Msk (0x8UL) /*!< DCLATCH (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_ENLP0_Pos (4UL) /*!< ENLP0 (Bit 4) */ + #define R_ESC_ESC_CONFIG_ENLP0_Msk (0x10UL) /*!< ENLP0 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_ENLP1_Pos (5UL) /*!< ENLP1 (Bit 5) */ + #define R_ESC_ESC_CONFIG_ENLP1_Msk (0x20UL) /*!< ENLP1 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_ENLP2_Pos (6UL) /*!< ENLP2 (Bit 6) */ + #define R_ESC_ESC_CONFIG_ENLP2_Msk (0x40UL) /*!< ENLP2 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_ENLP3_Pos (7UL) /*!< ENLP3 (Bit 7) */ + #define R_ESC_ESC_CONFIG_ENLP3_Msk (0x80UL) /*!< ENLP3 (Bitfield-Mask: 0x01) */ +/* ====================================================== PDI_CONFIG ======================================================= */ + #define R_ESC_PDI_CONFIG_ONCHIPBUSCLK_Pos (0UL) /*!< ONCHIPBUSCLK (Bit 0) */ + #define R_ESC_PDI_CONFIG_ONCHIPBUSCLK_Msk (0x1fUL) /*!< ONCHIPBUSCLK (Bitfield-Mask: 0x1f) */ + #define R_ESC_PDI_CONFIG_ONCHIPBUS_Pos (5UL) /*!< ONCHIPBUS (Bit 5) */ + #define R_ESC_PDI_CONFIG_ONCHIPBUS_Msk (0xe0UL) /*!< ONCHIPBUS (Bitfield-Mask: 0x07) */ +/* =================================================== SYNC_LATCH_CONFIG =================================================== */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC0OUT_Pos (0UL) /*!< SYNC0OUT (Bit 0) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC0OUT_Msk (0x3UL) /*!< SYNC0OUT (Bitfield-Mask: 0x03) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT0_Pos (2UL) /*!< SYNCLAT0 (Bit 2) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT0_Msk (0x4UL) /*!< SYNCLAT0 (Bitfield-Mask: 0x01) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC0MAP_Pos (3UL) /*!< SYNC0MAP (Bit 3) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC0MAP_Msk (0x8UL) /*!< SYNC0MAP (Bitfield-Mask: 0x01) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC1OUT_Pos (4UL) /*!< SYNC1OUT (Bit 4) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC1OUT_Msk (0x30UL) /*!< SYNC1OUT (Bitfield-Mask: 0x03) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT1_Pos (6UL) /*!< SYNCLAT1 (Bit 6) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT1_Msk (0x40UL) /*!< SYNCLAT1 (Bitfield-Mask: 0x01) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC1MAP_Pos (7UL) /*!< SYNC1MAP (Bit 7) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC1MAP_Msk (0x80UL) /*!< SYNC1MAP (Bitfield-Mask: 0x01) */ +/* ==================================================== EXT_PDI_CONFIG ===================================================== */ + #define R_ESC_EXT_PDI_CONFIG_DATABUSWID_Pos (0UL) /*!< DATABUSWID (Bit 0) */ + #define R_ESC_EXT_PDI_CONFIG_DATABUSWID_Msk (0x3UL) /*!< DATABUSWID (Bitfield-Mask: 0x03) */ +/* ==================================================== ECAT_EVENT_MASK ==================================================== */ + #define R_ESC_ECAT_EVENT_MASK_ECATEVMASK_Pos (0UL) /*!< ECATEVMASK (Bit 0) */ + #define R_ESC_ECAT_EVENT_MASK_ECATEVMASK_Msk (0xffffUL) /*!< ECATEVMASK (Bitfield-Mask: 0xffff) */ +/* ===================================================== AL_EVENT_MASK ===================================================== */ + #define R_ESC_AL_EVENT_MASK_ALEVMASK_Pos (0UL) /*!< ALEVMASK (Bit 0) */ + #define R_ESC_AL_EVENT_MASK_ALEVMASK_Msk (0xffffffffUL) /*!< ALEVMASK (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== ECAT_EVENT_REQ ===================================================== */ + #define R_ESC_ECAT_EVENT_REQ_DCLATCH_Pos (0UL) /*!< DCLATCH (Bit 0) */ + #define R_ESC_ECAT_EVENT_REQ_DCLATCH_Msk (0x1UL) /*!< DCLATCH (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_DLSTA_Pos (2UL) /*!< DLSTA (Bit 2) */ + #define R_ESC_ECAT_EVENT_REQ_DLSTA_Msk (0x4UL) /*!< DLSTA (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_ALSTA_Pos (3UL) /*!< ALSTA (Bit 3) */ + #define R_ESC_ECAT_EVENT_REQ_ALSTA_Msk (0x8UL) /*!< ALSTA (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA0_Pos (4UL) /*!< SMSTA0 (Bit 4) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA0_Msk (0x10UL) /*!< SMSTA0 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA1_Pos (5UL) /*!< SMSTA1 (Bit 5) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA1_Msk (0x20UL) /*!< SMSTA1 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA2_Pos (6UL) /*!< SMSTA2 (Bit 6) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA2_Msk (0x40UL) /*!< SMSTA2 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA3_Pos (7UL) /*!< SMSTA3 (Bit 7) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA3_Msk (0x80UL) /*!< SMSTA3 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA4_Pos (8UL) /*!< SMSTA4 (Bit 8) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA4_Msk (0x100UL) /*!< SMSTA4 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA5_Pos (9UL) /*!< SMSTA5 (Bit 9) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA5_Msk (0x200UL) /*!< SMSTA5 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA6_Pos (10UL) /*!< SMSTA6 (Bit 10) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA6_Msk (0x400UL) /*!< SMSTA6 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA7_Pos (11UL) /*!< SMSTA7 (Bit 11) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA7_Msk (0x800UL) /*!< SMSTA7 (Bitfield-Mask: 0x01) */ +/* ===================================================== AL_EVENT_REQ ====================================================== */ + #define R_ESC_AL_EVENT_REQ_ALCTRL_Pos (0UL) /*!< ALCTRL (Bit 0) */ + #define R_ESC_AL_EVENT_REQ_ALCTRL_Msk (0x1UL) /*!< ALCTRL (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_DCLATCH_Pos (1UL) /*!< DCLATCH (Bit 1) */ + #define R_ESC_AL_EVENT_REQ_DCLATCH_Msk (0x2UL) /*!< DCLATCH (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_DCSYNC0STA_Pos (2UL) /*!< DCSYNC0STA (Bit 2) */ + #define R_ESC_AL_EVENT_REQ_DCSYNC0STA_Msk (0x4UL) /*!< DCSYNC0STA (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_DCSYNC1STA_Pos (3UL) /*!< DCSYNC1STA (Bit 3) */ + #define R_ESC_AL_EVENT_REQ_DCSYNC1STA_Msk (0x8UL) /*!< DCSYNC1STA (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SYNCACT_Pos (4UL) /*!< SYNCACT (Bit 4) */ + #define R_ESC_AL_EVENT_REQ_SYNCACT_Msk (0x10UL) /*!< SYNCACT (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_WDPD_Pos (6UL) /*!< WDPD (Bit 6) */ + #define R_ESC_AL_EVENT_REQ_WDPD_Msk (0x40UL) /*!< WDPD (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT0_Pos (8UL) /*!< SMINT0 (Bit 8) */ + #define R_ESC_AL_EVENT_REQ_SMINT0_Msk (0x100UL) /*!< SMINT0 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT1_Pos (9UL) /*!< SMINT1 (Bit 9) */ + #define R_ESC_AL_EVENT_REQ_SMINT1_Msk (0x200UL) /*!< SMINT1 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT2_Pos (10UL) /*!< SMINT2 (Bit 10) */ + #define R_ESC_AL_EVENT_REQ_SMINT2_Msk (0x400UL) /*!< SMINT2 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT3_Pos (11UL) /*!< SMINT3 (Bit 11) */ + #define R_ESC_AL_EVENT_REQ_SMINT3_Msk (0x800UL) /*!< SMINT3 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT4_Pos (12UL) /*!< SMINT4 (Bit 12) */ + #define R_ESC_AL_EVENT_REQ_SMINT4_Msk (0x1000UL) /*!< SMINT4 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT5_Pos (13UL) /*!< SMINT5 (Bit 13) */ + #define R_ESC_AL_EVENT_REQ_SMINT5_Msk (0x2000UL) /*!< SMINT5 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT6_Pos (14UL) /*!< SMINT6 (Bit 14) */ + #define R_ESC_AL_EVENT_REQ_SMINT6_Msk (0x4000UL) /*!< SMINT6 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT7_Pos (15UL) /*!< SMINT7 (Bit 15) */ + #define R_ESC_AL_EVENT_REQ_SMINT7_Msk (0x8000UL) /*!< SMINT7 (Bitfield-Mask: 0x01) */ +/* ===================================================== RX_ERR_COUNT ====================================================== */ + #define R_ESC_RX_ERR_COUNT_INVFRMCNT_Pos (0UL) /*!< INVFRMCNT (Bit 0) */ + #define R_ESC_RX_ERR_COUNT_INVFRMCNT_Msk (0xffUL) /*!< INVFRMCNT (Bitfield-Mask: 0xff) */ + #define R_ESC_RX_ERR_COUNT_RXERRCNT_Pos (8UL) /*!< RXERRCNT (Bit 8) */ + #define R_ESC_RX_ERR_COUNT_RXERRCNT_Msk (0xff00UL) /*!< RXERRCNT (Bitfield-Mask: 0xff) */ +/* =================================================== FWD_RX_ERR_COUNT ==================================================== */ + #define R_ESC_FWD_RX_ERR_COUNT_FWDERRCNT_Pos (0UL) /*!< FWDERRCNT (Bit 0) */ + #define R_ESC_FWD_RX_ERR_COUNT_FWDERRCNT_Msk (0xffUL) /*!< FWDERRCNT (Bitfield-Mask: 0xff) */ +/* ================================================== ECAT_PROC_ERR_COUNT ================================================== */ + #define R_ESC_ECAT_PROC_ERR_COUNT_EPUERRCNT_Pos (0UL) /*!< EPUERRCNT (Bit 0) */ + #define R_ESC_ECAT_PROC_ERR_COUNT_EPUERRCNT_Msk (0xffUL) /*!< EPUERRCNT (Bitfield-Mask: 0xff) */ +/* ===================================================== PDI_ERR_COUNT ===================================================== */ + #define R_ESC_PDI_ERR_COUNT_PDIERRCNT_Pos (0UL) /*!< PDIERRCNT (Bit 0) */ + #define R_ESC_PDI_ERR_COUNT_PDIERRCNT_Msk (0xffUL) /*!< PDIERRCNT (Bitfield-Mask: 0xff) */ +/* ==================================================== LOST_LINK_COUNT ==================================================== */ + #define R_ESC_LOST_LINK_COUNT_LOSTLINKCNT_Pos (0UL) /*!< LOSTLINKCNT (Bit 0) */ + #define R_ESC_LOST_LINK_COUNT_LOSTLINKCNT_Msk (0xffUL) /*!< LOSTLINKCNT (Bitfield-Mask: 0xff) */ +/* ======================================================= WD_DIVIDE ======================================================= */ + #define R_ESC_WD_DIVIDE_WDDIV_Pos (0UL) /*!< WDDIV (Bit 0) */ + #define R_ESC_WD_DIVIDE_WDDIV_Msk (0xffffUL) /*!< WDDIV (Bitfield-Mask: 0xffff) */ +/* ======================================================== WDT_PDI ======================================================== */ + #define R_ESC_WDT_PDI_WDTIMPDI_Pos (0UL) /*!< WDTIMPDI (Bit 0) */ + #define R_ESC_WDT_PDI_WDTIMPDI_Msk (0xffffUL) /*!< WDTIMPDI (Bitfield-Mask: 0xffff) */ +/* ======================================================= WDT_DATA ======================================================== */ + #define R_ESC_WDT_DATA_WDTIMPD_Pos (0UL) /*!< WDTIMPD (Bit 0) */ + #define R_ESC_WDT_DATA_WDTIMPD_Msk (0xffffUL) /*!< WDTIMPD (Bitfield-Mask: 0xffff) */ +/* ======================================================= WDS_DATA ======================================================== */ + #define R_ESC_WDS_DATA_WDSTAPD_Pos (0UL) /*!< WDSTAPD (Bit 0) */ + #define R_ESC_WDS_DATA_WDSTAPD_Msk (0x1UL) /*!< WDSTAPD (Bitfield-Mask: 0x01) */ +/* ======================================================= WDC_DATA ======================================================== */ + #define R_ESC_WDC_DATA_WDCNTPD_Pos (0UL) /*!< WDCNTPD (Bit 0) */ + #define R_ESC_WDC_DATA_WDCNTPD_Msk (0xffUL) /*!< WDCNTPD (Bitfield-Mask: 0xff) */ +/* ======================================================== WDC_PDI ======================================================== */ + #define R_ESC_WDC_PDI_WDCNTPDI_Pos (0UL) /*!< WDCNTPDI (Bit 0) */ + #define R_ESC_WDC_PDI_WDCNTPDI_Msk (0xffUL) /*!< WDCNTPDI (Bitfield-Mask: 0xff) */ +/* ======================================================= EEP_CONF ======================================================== */ + #define R_ESC_EEP_CONF_CTRLPDI_Pos (0UL) /*!< CTRLPDI (Bit 0) */ + #define R_ESC_EEP_CONF_CTRLPDI_Msk (0x1UL) /*!< CTRLPDI (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONF_FORCEECAT_Pos (1UL) /*!< FORCEECAT (Bit 1) */ + #define R_ESC_EEP_CONF_FORCEECAT_Msk (0x2UL) /*!< FORCEECAT (Bitfield-Mask: 0x01) */ +/* ======================================================= EEP_STATE ======================================================= */ + #define R_ESC_EEP_STATE_PDIACCESS_Pos (0UL) /*!< PDIACCESS (Bit 0) */ + #define R_ESC_EEP_STATE_PDIACCESS_Msk (0x1UL) /*!< PDIACCESS (Bitfield-Mask: 0x01) */ +/* ===================================================== EEP_CONT_STAT ===================================================== */ + #define R_ESC_EEP_CONT_STAT_ECATWREN_Pos (0UL) /*!< ECATWREN (Bit 0) */ + #define R_ESC_EEP_CONT_STAT_ECATWREN_Msk (0x1UL) /*!< ECATWREN (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_READBYTE_Pos (6UL) /*!< READBYTE (Bit 6) */ + #define R_ESC_EEP_CONT_STAT_READBYTE_Msk (0x40UL) /*!< READBYTE (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_PROMSIZE_Pos (7UL) /*!< PROMSIZE (Bit 7) */ + #define R_ESC_EEP_CONT_STAT_PROMSIZE_Msk (0x80UL) /*!< PROMSIZE (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_COMMAND_Pos (8UL) /*!< COMMAND (Bit 8) */ + #define R_ESC_EEP_CONT_STAT_COMMAND_Msk (0x700UL) /*!< COMMAND (Bitfield-Mask: 0x07) */ + #define R_ESC_EEP_CONT_STAT_CKSUMERR_Pos (11UL) /*!< CKSUMERR (Bit 11) */ + #define R_ESC_EEP_CONT_STAT_CKSUMERR_Msk (0x800UL) /*!< CKSUMERR (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_LOADSTA_Pos (12UL) /*!< LOADSTA (Bit 12) */ + #define R_ESC_EEP_CONT_STAT_LOADSTA_Msk (0x1000UL) /*!< LOADSTA (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_ACKCMDERR_Pos (13UL) /*!< ACKCMDERR (Bit 13) */ + #define R_ESC_EEP_CONT_STAT_ACKCMDERR_Msk (0x2000UL) /*!< ACKCMDERR (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_WRENERR_Pos (14UL) /*!< WRENERR (Bit 14) */ + #define R_ESC_EEP_CONT_STAT_WRENERR_Msk (0x4000UL) /*!< WRENERR (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_BUSY_Pos (15UL) /*!< BUSY (Bit 15) */ + #define R_ESC_EEP_CONT_STAT_BUSY_Msk (0x8000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== EEP_ADR ======================================================== */ + #define R_ESC_EEP_ADR_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ + #define R_ESC_EEP_ADR_ADDRESS_Msk (0xffffffffUL) /*!< ADDRESS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EEP_DATA ======================================================== */ + #define R_ESC_EEP_DATA_LODATA_Pos (0UL) /*!< LODATA (Bit 0) */ + #define R_ESC_EEP_DATA_LODATA_Msk (0xffffUL) /*!< LODATA (Bitfield-Mask: 0xffff) */ + #define R_ESC_EEP_DATA_HIDATA_Pos (16UL) /*!< HIDATA (Bit 16) */ + #define R_ESC_EEP_DATA_HIDATA_Msk (0xffff0000UL) /*!< HIDATA (Bitfield-Mask: 0xffff) */ +/* ===================================================== MII_CONT_STAT ===================================================== */ + #define R_ESC_MII_CONT_STAT_WREN_Pos (0UL) /*!< WREN (Bit 0) */ + #define R_ESC_MII_CONT_STAT_WREN_Msk (0x1UL) /*!< WREN (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_CONT_STAT_PDICTRL_Pos (1UL) /*!< PDICTRL (Bit 1) */ + #define R_ESC_MII_CONT_STAT_PDICTRL_Msk (0x2UL) /*!< PDICTRL (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_CONT_STAT_MILINK_Pos (2UL) /*!< MILINK (Bit 2) */ + #define R_ESC_MII_CONT_STAT_MILINK_Msk (0x4UL) /*!< MILINK (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_CONT_STAT_PHYOFFSET_Pos (3UL) /*!< PHYOFFSET (Bit 3) */ + #define R_ESC_MII_CONT_STAT_PHYOFFSET_Msk (0xf8UL) /*!< PHYOFFSET (Bitfield-Mask: 0x1f) */ + #define R_ESC_MII_CONT_STAT_COMMAND_Pos (8UL) /*!< COMMAND (Bit 8) */ + #define R_ESC_MII_CONT_STAT_COMMAND_Msk (0x300UL) /*!< COMMAND (Bitfield-Mask: 0x03) */ + #define R_ESC_MII_CONT_STAT_READERR_Pos (13UL) /*!< READERR (Bit 13) */ + #define R_ESC_MII_CONT_STAT_READERR_Msk (0x2000UL) /*!< READERR (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_CONT_STAT_CMDERR_Pos (14UL) /*!< CMDERR (Bit 14) */ + #define R_ESC_MII_CONT_STAT_CMDERR_Msk (0x4000UL) /*!< CMDERR (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_CONT_STAT_BUSY_Pos (15UL) /*!< BUSY (Bit 15) */ + #define R_ESC_MII_CONT_STAT_BUSY_Msk (0x8000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== PHY_ADR ======================================================== */ + #define R_ESC_PHY_ADR_PHYADDR_Pos (0UL) /*!< PHYADDR (Bit 0) */ + #define R_ESC_PHY_ADR_PHYADDR_Msk (0x1fUL) /*!< PHYADDR (Bitfield-Mask: 0x1f) */ +/* ====================================================== PHY_REG_ADR ====================================================== */ + #define R_ESC_PHY_REG_ADR_PHYREGADDR_Pos (0UL) /*!< PHYREGADDR (Bit 0) */ + #define R_ESC_PHY_REG_ADR_PHYREGADDR_Msk (0x1fUL) /*!< PHYREGADDR (Bitfield-Mask: 0x1f) */ +/* ======================================================= PHY_DATA ======================================================== */ + #define R_ESC_PHY_DATA_PHYREGDATA_Pos (0UL) /*!< PHYREGDATA (Bit 0) */ + #define R_ESC_PHY_DATA_PHYREGDATA_Msk (0xffffUL) /*!< PHYREGDATA (Bitfield-Mask: 0xffff) */ +/* =================================================== MII_ECAT_ACS_STAT =================================================== */ + #define R_ESC_MII_ECAT_ACS_STAT_ACSMII_Pos (0UL) /*!< ACSMII (Bit 0) */ + #define R_ESC_MII_ECAT_ACS_STAT_ACSMII_Msk (0x1UL) /*!< ACSMII (Bitfield-Mask: 0x01) */ +/* =================================================== MII_PDI_ACS_STAT ==================================================== */ + #define R_ESC_MII_PDI_ACS_STAT_ACSMII_Pos (0UL) /*!< ACSMII (Bit 0) */ + #define R_ESC_MII_PDI_ACS_STAT_ACSMII_Msk (0x1UL) /*!< ACSMII (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_PDI_ACS_STAT_FORPDI_Pos (1UL) /*!< FORPDI (Bit 1) */ + #define R_ESC_MII_PDI_ACS_STAT_FORPDI_Msk (0x2UL) /*!< FORPDI (Bitfield-Mask: 0x01) */ +/* =================================================== DC_RCV_TIME_PORT ==================================================== */ + #define R_ESC_DC_RCV_TIME_PORT_RCVTIME0_Pos (0UL) /*!< RCVTIME0 (Bit 0) */ + #define R_ESC_DC_RCV_TIME_PORT_RCVTIME0_Msk (0xffffffffUL) /*!< RCVTIME0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DC_SYS_TIME_L ===================================================== */ +/* ===================================================== DC_SYS_TIME_H ===================================================== */ +/* ================================================== DC_RCV_TIME_UNIT_L =================================================== */ +/* ================================================== DC_RCV_TIME_UNIT_H =================================================== */ +/* ================================================= DC_SYS_TIME_OFFSET_L ================================================== */ +/* ================================================= DC_SYS_TIME_OFFSET_H ================================================== */ +/* =================================================== DC_SYS_TIME_DELAY =================================================== */ + #define R_ESC_DC_SYS_TIME_DELAY_SYSTIMDLY_Pos (0UL) /*!< SYSTIMDLY (Bit 0) */ + #define R_ESC_DC_SYS_TIME_DELAY_SYSTIMDLY_Msk (0xffffffffUL) /*!< SYSTIMDLY (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DC_SYS_TIME_DIFF ==================================================== */ + #define R_ESC_DC_SYS_TIME_DIFF_DIFF_Pos (0UL) /*!< DIFF (Bit 0) */ + #define R_ESC_DC_SYS_TIME_DIFF_DIFF_Msk (0x7fffffffUL) /*!< DIFF (Bitfield-Mask: 0x7fffffff) */ + #define R_ESC_DC_SYS_TIME_DIFF_LCP_Pos (31UL) /*!< LCP (Bit 31) */ + #define R_ESC_DC_SYS_TIME_DIFF_LCP_Msk (0x80000000UL) /*!< LCP (Bitfield-Mask: 0x01) */ +/* ================================================= DC_SPEED_COUNT_START ================================================== */ + #define R_ESC_DC_SPEED_COUNT_START_SPDCNTSTRT_Pos (0UL) /*!< SPDCNTSTRT (Bit 0) */ + #define R_ESC_DC_SPEED_COUNT_START_SPDCNTSTRT_Msk (0x7fffUL) /*!< SPDCNTSTRT (Bitfield-Mask: 0x7fff) */ +/* ================================================== DC_SPEED_COUNT_DIFF ================================================== */ + #define R_ESC_DC_SPEED_COUNT_DIFF_SPDCNTDIFF_Pos (0UL) /*!< SPDCNTDIFF (Bit 0) */ + #define R_ESC_DC_SPEED_COUNT_DIFF_SPDCNTDIFF_Msk (0xffffUL) /*!< SPDCNTDIFF (Bitfield-Mask: 0xffff) */ +/* ============================================== DC_SYS_TIME_DIFF_FIL_DEPTH =============================================== */ + #define R_ESC_DC_SYS_TIME_DIFF_FIL_DEPTH_SYSTIMDEP_Pos (0UL) /*!< SYSTIMDEP (Bit 0) */ + #define R_ESC_DC_SYS_TIME_DIFF_FIL_DEPTH_SYSTIMDEP_Msk (0xfUL) /*!< SYSTIMDEP (Bitfield-Mask: 0x0f) */ +/* =============================================== DC_SPEED_COUNT_FIL_DEPTH ================================================ */ + #define R_ESC_DC_SPEED_COUNT_FIL_DEPTH_CLKPERDEP_Pos (0UL) /*!< CLKPERDEP (Bit 0) */ + #define R_ESC_DC_SPEED_COUNT_FIL_DEPTH_CLKPERDEP_Msk (0xfUL) /*!< CLKPERDEP (Bitfield-Mask: 0x0f) */ +/* ====================================================== DC_CYC_CONT ====================================================== */ + #define R_ESC_DC_CYC_CONT_SYNCOUT_Pos (0UL) /*!< SYNCOUT (Bit 0) */ + #define R_ESC_DC_CYC_CONT_SYNCOUT_Msk (0x1UL) /*!< SYNCOUT (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_CYC_CONT_LATCH0_Pos (4UL) /*!< LATCH0 (Bit 4) */ + #define R_ESC_DC_CYC_CONT_LATCH0_Msk (0x10UL) /*!< LATCH0 (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_CYC_CONT_LATCH1_Pos (5UL) /*!< LATCH1 (Bit 5) */ + #define R_ESC_DC_CYC_CONT_LATCH1_Msk (0x20UL) /*!< LATCH1 (Bitfield-Mask: 0x01) */ +/* ======================================================== DC_ACT ========================================================= */ + #define R_ESC_DC_ACT_SYNCACT_Pos (0UL) /*!< SYNCACT (Bit 0) */ + #define R_ESC_DC_ACT_SYNCACT_Msk (0x1UL) /*!< SYNCACT (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_SYNC0_Pos (1UL) /*!< SYNC0 (Bit 1) */ + #define R_ESC_DC_ACT_SYNC0_Msk (0x2UL) /*!< SYNC0 (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_SYNC1_Pos (2UL) /*!< SYNC1 (Bit 2) */ + #define R_ESC_DC_ACT_SYNC1_Msk (0x4UL) /*!< SYNC1 (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_AUTOACT_Pos (3UL) /*!< AUTOACT (Bit 3) */ + #define R_ESC_DC_ACT_AUTOACT_Msk (0x8UL) /*!< AUTOACT (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_EXTSTARTTIME_Pos (4UL) /*!< EXTSTARTTIME (Bit 4) */ + #define R_ESC_DC_ACT_EXTSTARTTIME_Msk (0x10UL) /*!< EXTSTARTTIME (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_STARTTIME_Pos (5UL) /*!< STARTTIME (Bit 5) */ + #define R_ESC_DC_ACT_STARTTIME_Msk (0x20UL) /*!< STARTTIME (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_NEARFUTURE_Pos (6UL) /*!< NEARFUTURE (Bit 6) */ + #define R_ESC_DC_ACT_NEARFUTURE_Msk (0x40UL) /*!< NEARFUTURE (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_DBGPULSE_Pos (7UL) /*!< DBGPULSE (Bit 7) */ + #define R_ESC_DC_ACT_DBGPULSE_Msk (0x80UL) /*!< DBGPULSE (Bitfield-Mask: 0x01) */ +/* ===================================================== DC_PULSE_LEN ====================================================== */ + #define R_ESC_DC_PULSE_LEN_PULSELEN_Pos (0UL) /*!< PULSELEN (Bit 0) */ + #define R_ESC_DC_PULSE_LEN_PULSELEN_Msk (0xffffUL) /*!< PULSELEN (Bitfield-Mask: 0xffff) */ +/* ====================================================== DC_ACT_STAT ====================================================== */ + #define R_ESC_DC_ACT_STAT_SYNC0ACT_Pos (0UL) /*!< SYNC0ACT (Bit 0) */ + #define R_ESC_DC_ACT_STAT_SYNC0ACT_Msk (0x1UL) /*!< SYNC0ACT (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_STAT_SYNC1ACT_Pos (1UL) /*!< SYNC1ACT (Bit 1) */ + #define R_ESC_DC_ACT_STAT_SYNC1ACT_Msk (0x2UL) /*!< SYNC1ACT (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_STAT_STARTTIME_Pos (2UL) /*!< STARTTIME (Bit 2) */ + #define R_ESC_DC_ACT_STAT_STARTTIME_Msk (0x4UL) /*!< STARTTIME (Bitfield-Mask: 0x01) */ +/* ===================================================== DC_SYNC0_STAT ===================================================== */ + #define R_ESC_DC_SYNC0_STAT_SYNC0STA_Pos (0UL) /*!< SYNC0STA (Bit 0) */ + #define R_ESC_DC_SYNC0_STAT_SYNC0STA_Msk (0x1UL) /*!< SYNC0STA (Bitfield-Mask: 0x01) */ +/* ===================================================== DC_SYNC1_STAT ===================================================== */ + #define R_ESC_DC_SYNC1_STAT_SYNC1STA_Pos (0UL) /*!< SYNC1STA (Bit 0) */ + #define R_ESC_DC_SYNC1_STAT_SYNC1STA_Msk (0x1UL) /*!< SYNC1STA (Bitfield-Mask: 0x01) */ +/* ================================================== DC_CYC_START_TIME_L ================================================== */ +/* ================================================== DC_CYC_START_TIME_H ================================================== */ +/* ================================================= DC_NEXT_SYNC1_PULSE_L ================================================= */ +/* ================================================= DC_NEXT_SYNC1_PULSE_H ================================================= */ +/* =================================================== DC_SYNC0_CYC_TIME =================================================== */ + #define R_ESC_DC_SYNC0_CYC_TIME_SYNC0CYC_Pos (0UL) /*!< SYNC0CYC (Bit 0) */ + #define R_ESC_DC_SYNC0_CYC_TIME_SYNC0CYC_Msk (0xffffffffUL) /*!< SYNC0CYC (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DC_SYNC1_CYC_TIME =================================================== */ + #define R_ESC_DC_SYNC1_CYC_TIME_SYNC1CYC_Pos (0UL) /*!< SYNC1CYC (Bit 0) */ + #define R_ESC_DC_SYNC1_CYC_TIME_SYNC1CYC_Msk (0xffffffffUL) /*!< SYNC1CYC (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DC_LATCH0_CONT ===================================================== */ + #define R_ESC_DC_LATCH0_CONT_POSEDGE_Pos (0UL) /*!< POSEDGE (Bit 0) */ + #define R_ESC_DC_LATCH0_CONT_POSEDGE_Msk (0x1UL) /*!< POSEDGE (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH0_CONT_NEGEDGE_Pos (1UL) /*!< NEGEDGE (Bit 1) */ + #define R_ESC_DC_LATCH0_CONT_NEGEDGE_Msk (0x2UL) /*!< NEGEDGE (Bitfield-Mask: 0x01) */ +/* ==================================================== DC_LATCH1_CONT ===================================================== */ + #define R_ESC_DC_LATCH1_CONT_POSEDGE_Pos (0UL) /*!< POSEDGE (Bit 0) */ + #define R_ESC_DC_LATCH1_CONT_POSEDGE_Msk (0x1UL) /*!< POSEDGE (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH1_CONT_NEGEDGE_Pos (1UL) /*!< NEGEDGE (Bit 1) */ + #define R_ESC_DC_LATCH1_CONT_NEGEDGE_Msk (0x2UL) /*!< NEGEDGE (Bitfield-Mask: 0x01) */ +/* ==================================================== DC_LATCH0_STAT ===================================================== */ + #define R_ESC_DC_LATCH0_STAT_EVENTPOS_Pos (0UL) /*!< EVENTPOS (Bit 0) */ + #define R_ESC_DC_LATCH0_STAT_EVENTPOS_Msk (0x1UL) /*!< EVENTPOS (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH0_STAT_EVENTNEG_Pos (1UL) /*!< EVENTNEG (Bit 1) */ + #define R_ESC_DC_LATCH0_STAT_EVENTNEG_Msk (0x2UL) /*!< EVENTNEG (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH0_STAT_PINSTATE_Pos (2UL) /*!< PINSTATE (Bit 2) */ + #define R_ESC_DC_LATCH0_STAT_PINSTATE_Msk (0x4UL) /*!< PINSTATE (Bitfield-Mask: 0x01) */ +/* ==================================================== DC_LATCH1_STAT ===================================================== */ + #define R_ESC_DC_LATCH1_STAT_EVENTPOS_Pos (0UL) /*!< EVENTPOS (Bit 0) */ + #define R_ESC_DC_LATCH1_STAT_EVENTPOS_Msk (0x1UL) /*!< EVENTPOS (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH1_STAT_EVENTNEG_Pos (1UL) /*!< EVENTNEG (Bit 1) */ + #define R_ESC_DC_LATCH1_STAT_EVENTNEG_Msk (0x2UL) /*!< EVENTNEG (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH1_STAT_PINSTATE_Pos (2UL) /*!< PINSTATE (Bit 2) */ + #define R_ESC_DC_LATCH1_STAT_PINSTATE_Msk (0x4UL) /*!< PINSTATE (Bitfield-Mask: 0x01) */ +/* ================================================= DC_LATCH0_TIME_POS_L ================================================== */ +/* ================================================= DC_LATCH0_TIME_POS_H ================================================== */ +/* ================================================= DC_LATCH0_TIME_NEG_L ================================================== */ +/* ================================================= DC_LATCH0_TIME_NEG_H ================================================== */ +/* ================================================= DC_LATCH1_TIME_POS_L ================================================== */ +/* ================================================= DC_LATCH1_TIME_POS_H ================================================== */ +/* ================================================= DC_LATCH1_TIME_NEG_L ================================================== */ +/* ================================================= DC_LATCH1_TIME_NEG_H ================================================== */ +/* ================================================== DC_ECAT_CNG_EV_TIME ================================================== */ + #define R_ESC_DC_ECAT_CNG_EV_TIME_ECATCHANGE_Pos (0UL) /*!< ECATCHANGE (Bit 0) */ + #define R_ESC_DC_ECAT_CNG_EV_TIME_ECATCHANGE_Msk (0xffffffffUL) /*!< ECATCHANGE (Bitfield-Mask: 0xffffffff) */ +/* ================================================= DC_PDI_START_EV_TIME ================================================== */ + #define R_ESC_DC_PDI_START_EV_TIME_PDISTART_Pos (0UL) /*!< PDISTART (Bit 0) */ + #define R_ESC_DC_PDI_START_EV_TIME_PDISTART_Msk (0xffffffffUL) /*!< PDISTART (Bitfield-Mask: 0xffffffff) */ +/* ================================================== DC_PDI_CNG_EV_TIME =================================================== */ + #define R_ESC_DC_PDI_CNG_EV_TIME_PDICHANGE_Pos (0UL) /*!< PDICHANGE (Bit 0) */ + #define R_ESC_DC_PDI_CNG_EV_TIME_PDICHANGE_Msk (0xffffffffUL) /*!< PDICHANGE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PRODUCT_ID_L ====================================================== */ +/* ===================================================== PRODUCT_ID_H ====================================================== */ +/* ====================================================== VENDOR_ID_L ====================================================== */ + #define R_ESC_VENDOR_ID_L_VENDORID_Pos (0UL) /*!< VENDORID (Bit 0) */ + #define R_ESC_VENDOR_ID_L_VENDORID_Msk (0xffffffffUL) /*!< VENDORID (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_USBHC ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== HCREVISION ======================================================= */ + #define R_USBHC_HCREVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_USBHC_HCREVISION_REV_Msk (0xffUL) /*!< REV (Bitfield-Mask: 0xff) */ +/* ======================================================= HCCONTROL ======================================================= */ + #define R_USBHC_HCCONTROL_CBSR_Pos (0UL) /*!< CBSR (Bit 0) */ + #define R_USBHC_HCCONTROL_CBSR_Msk (0x3UL) /*!< CBSR (Bitfield-Mask: 0x03) */ + #define R_USBHC_HCCONTROL_PLE_Pos (2UL) /*!< PLE (Bit 2) */ + #define R_USBHC_HCCONTROL_PLE_Msk (0x4UL) /*!< PLE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_IE_Pos (3UL) /*!< IE (Bit 3) */ + #define R_USBHC_HCCONTROL_IE_Msk (0x8UL) /*!< IE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_CLE_Pos (4UL) /*!< CLE (Bit 4) */ + #define R_USBHC_HCCONTROL_CLE_Msk (0x10UL) /*!< CLE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_BLE_Pos (5UL) /*!< BLE (Bit 5) */ + #define R_USBHC_HCCONTROL_BLE_Msk (0x20UL) /*!< BLE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_HCFS_Pos (6UL) /*!< HCFS (Bit 6) */ + #define R_USBHC_HCCONTROL_HCFS_Msk (0xc0UL) /*!< HCFS (Bitfield-Mask: 0x03) */ + #define R_USBHC_HCCONTROL_IR_Pos (8UL) /*!< IR (Bit 8) */ + #define R_USBHC_HCCONTROL_IR_Msk (0x100UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_RWC_Pos (9UL) /*!< RWC (Bit 9) */ + #define R_USBHC_HCCONTROL_RWC_Msk (0x200UL) /*!< RWC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_RWE_Pos (10UL) /*!< RWE (Bit 10) */ + #define R_USBHC_HCCONTROL_RWE_Msk (0x400UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ==================================================== HCCOMMANDSTATUS ==================================================== */ + #define R_USBHC_HCCOMMANDSTATUS_HCR_Pos (0UL) /*!< HCR (Bit 0) */ + #define R_USBHC_HCCOMMANDSTATUS_HCR_Msk (0x1UL) /*!< HCR (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCOMMANDSTATUS_CLF_Pos (1UL) /*!< CLF (Bit 1) */ + #define R_USBHC_HCCOMMANDSTATUS_CLF_Msk (0x2UL) /*!< CLF (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCOMMANDSTATUS_BLF_Pos (2UL) /*!< BLF (Bit 2) */ + #define R_USBHC_HCCOMMANDSTATUS_BLF_Msk (0x4UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCOMMANDSTATUS_OCR_Pos (3UL) /*!< OCR (Bit 3) */ + #define R_USBHC_HCCOMMANDSTATUS_OCR_Msk (0x8UL) /*!< OCR (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCOMMANDSTATUS_SOC_Pos (16UL) /*!< SOC (Bit 16) */ + #define R_USBHC_HCCOMMANDSTATUS_SOC_Msk (0x30000UL) /*!< SOC (Bitfield-Mask: 0x03) */ +/* =================================================== HCINTERRUPTSTATUS =================================================== */ + #define R_USBHC_HCINTERRUPTSTATUS_SO_Pos (0UL) /*!< SO (Bit 0) */ + #define R_USBHC_HCINTERRUPTSTATUS_SO_Msk (0x1UL) /*!< SO (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_WDH_Pos (1UL) /*!< WDH (Bit 1) */ + #define R_USBHC_HCINTERRUPTSTATUS_WDH_Msk (0x2UL) /*!< WDH (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_SF_Pos (2UL) /*!< SF (Bit 2) */ + #define R_USBHC_HCINTERRUPTSTATUS_SF_Msk (0x4UL) /*!< SF (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_RD_Pos (3UL) /*!< RD (Bit 3) */ + #define R_USBHC_HCINTERRUPTSTATUS_RD_Msk (0x8UL) /*!< RD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_UE_Pos (4UL) /*!< UE (Bit 4) */ + #define R_USBHC_HCINTERRUPTSTATUS_UE_Msk (0x10UL) /*!< UE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_FNO_Pos (5UL) /*!< FNO (Bit 5) */ + #define R_USBHC_HCINTERRUPTSTATUS_FNO_Msk (0x20UL) /*!< FNO (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_RHSC_Pos (6UL) /*!< RHSC (Bit 6) */ + #define R_USBHC_HCINTERRUPTSTATUS_RHSC_Msk (0x40UL) /*!< RHSC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_OC_Pos (30UL) /*!< OC (Bit 30) */ + #define R_USBHC_HCINTERRUPTSTATUS_OC_Msk (0x40000000UL) /*!< OC (Bitfield-Mask: 0x01) */ +/* =================================================== HCINTERRUPTENABLE =================================================== */ + #define R_USBHC_HCINTERRUPTENABLE_SOE_Pos (0UL) /*!< SOE (Bit 0) */ + #define R_USBHC_HCINTERRUPTENABLE_SOE_Msk (0x1UL) /*!< SOE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_WDHE_Pos (1UL) /*!< WDHE (Bit 1) */ + #define R_USBHC_HCINTERRUPTENABLE_WDHE_Msk (0x2UL) /*!< WDHE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_SFE_Pos (2UL) /*!< SFE (Bit 2) */ + #define R_USBHC_HCINTERRUPTENABLE_SFE_Msk (0x4UL) /*!< SFE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_RDE_Pos (3UL) /*!< RDE (Bit 3) */ + #define R_USBHC_HCINTERRUPTENABLE_RDE_Msk (0x8UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_UEE_Pos (4UL) /*!< UEE (Bit 4) */ + #define R_USBHC_HCINTERRUPTENABLE_UEE_Msk (0x10UL) /*!< UEE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_FNOE_Pos (5UL) /*!< FNOE (Bit 5) */ + #define R_USBHC_HCINTERRUPTENABLE_FNOE_Msk (0x20UL) /*!< FNOE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_RHSCE_Pos (6UL) /*!< RHSCE (Bit 6) */ + #define R_USBHC_HCINTERRUPTENABLE_RHSCE_Msk (0x40UL) /*!< RHSCE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_OCE_Pos (30UL) /*!< OCE (Bit 30) */ + #define R_USBHC_HCINTERRUPTENABLE_OCE_Msk (0x40000000UL) /*!< OCE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_MIE_Pos (31UL) /*!< MIE (Bit 31) */ + #define R_USBHC_HCINTERRUPTENABLE_MIE_Msk (0x80000000UL) /*!< MIE (Bitfield-Mask: 0x01) */ +/* ================================================== HCINTERRUPTDISABLE =================================================== */ + #define R_USBHC_HCINTERRUPTDISABLE_SOD_Pos (0UL) /*!< SOD (Bit 0) */ + #define R_USBHC_HCINTERRUPTDISABLE_SOD_Msk (0x1UL) /*!< SOD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_WDHD_Pos (1UL) /*!< WDHD (Bit 1) */ + #define R_USBHC_HCINTERRUPTDISABLE_WDHD_Msk (0x2UL) /*!< WDHD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_SFD_Pos (2UL) /*!< SFD (Bit 2) */ + #define R_USBHC_HCINTERRUPTDISABLE_SFD_Msk (0x4UL) /*!< SFD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_RDD_Pos (3UL) /*!< RDD (Bit 3) */ + #define R_USBHC_HCINTERRUPTDISABLE_RDD_Msk (0x8UL) /*!< RDD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_UED_Pos (4UL) /*!< UED (Bit 4) */ + #define R_USBHC_HCINTERRUPTDISABLE_UED_Msk (0x10UL) /*!< UED (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_FNOD_Pos (5UL) /*!< FNOD (Bit 5) */ + #define R_USBHC_HCINTERRUPTDISABLE_FNOD_Msk (0x20UL) /*!< FNOD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_RHSCD_Pos (6UL) /*!< RHSCD (Bit 6) */ + #define R_USBHC_HCINTERRUPTDISABLE_RHSCD_Msk (0x40UL) /*!< RHSCD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_OCD_Pos (30UL) /*!< OCD (Bit 30) */ + #define R_USBHC_HCINTERRUPTDISABLE_OCD_Msk (0x40000000UL) /*!< OCD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_MID_Pos (31UL) /*!< MID (Bit 31) */ + #define R_USBHC_HCINTERRUPTDISABLE_MID_Msk (0x80000000UL) /*!< MID (Bitfield-Mask: 0x01) */ +/* ======================================================== HCHCCA ========================================================= */ + #define R_USBHC_HCHCCA_RAMBA_Pos (8UL) /*!< RAMBA (Bit 8) */ + #define R_USBHC_HCHCCA_RAMBA_Msk (0xffffff00UL) /*!< RAMBA (Bitfield-Mask: 0xffffff) */ +/* ================================================== HCPERIODCCURRENTIED ================================================== */ + #define R_USBHC_HCPERIODCCURRENTIED_PCED_Pos (4UL) /*!< PCED (Bit 4) */ + #define R_USBHC_HCPERIODCCURRENTIED_PCED_Msk (0xfffffff0UL) /*!< PCED (Bitfield-Mask: 0xfffffff) */ +/* ==================================================== HCCONTROLHEADED ==================================================== */ + #define R_USBHC_HCCONTROLHEADED_CHED_Pos (4UL) /*!< CHED (Bit 4) */ + #define R_USBHC_HCCONTROLHEADED_CHED_Msk (0xfffffff0UL) /*!< CHED (Bitfield-Mask: 0xfffffff) */ +/* ================================================== HCCONTROLCURRENTED =================================================== */ + #define R_USBHC_HCCONTROLCURRENTED_CCED_Pos (4UL) /*!< CCED (Bit 4) */ + #define R_USBHC_HCCONTROLCURRENTED_CCED_Msk (0xfffffff0UL) /*!< CCED (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== HCBULKHEADED ====================================================== */ + #define R_USBHC_HCBULKHEADED_BHED_Pos (4UL) /*!< BHED (Bit 4) */ + #define R_USBHC_HCBULKHEADED_BHED_Msk (0xfffffff0UL) /*!< BHED (Bitfield-Mask: 0xfffffff) */ +/* ==================================================== HCBULKCURRENTED ==================================================== */ + #define R_USBHC_HCBULKCURRENTED_BCED_Pos (4UL) /*!< BCED (Bit 4) */ + #define R_USBHC_HCBULKCURRENTED_BCED_Msk (0xfffffff0UL) /*!< BCED (Bitfield-Mask: 0xfffffff) */ +/* ====================================================== HCDONEHEAD ======================================================= */ + #define R_USBHC_HCDONEHEAD_DH_Pos (4UL) /*!< DH (Bit 4) */ + #define R_USBHC_HCDONEHEAD_DH_Msk (0xfffffff0UL) /*!< DH (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== HCFMINTERVAL ====================================================== */ + #define R_USBHC_HCFMINTERVAL_FI_Pos (0UL) /*!< FI (Bit 0) */ + #define R_USBHC_HCFMINTERVAL_FI_Msk (0x3fffUL) /*!< FI (Bitfield-Mask: 0x3fff) */ + #define R_USBHC_HCFMINTERVAL_FSMPS_Pos (16UL) /*!< FSMPS (Bit 16) */ + #define R_USBHC_HCFMINTERVAL_FSMPS_Msk (0x7fff0000UL) /*!< FSMPS (Bitfield-Mask: 0x7fff) */ + #define R_USBHC_HCFMINTERVAL_FIT_Pos (31UL) /*!< FIT (Bit 31) */ + #define R_USBHC_HCFMINTERVAL_FIT_Msk (0x80000000UL) /*!< FIT (Bitfield-Mask: 0x01) */ +/* ===================================================== HCFNREMAINING ===================================================== */ + #define R_USBHC_HCFNREMAINING_FR_Pos (0UL) /*!< FR (Bit 0) */ + #define R_USBHC_HCFNREMAINING_FR_Msk (0x3fffUL) /*!< FR (Bitfield-Mask: 0x3fff) */ + #define R_USBHC_HCFNREMAINING_FRT_Pos (31UL) /*!< FRT (Bit 31) */ + #define R_USBHC_HCFNREMAINING_FRT_Msk (0x80000000UL) /*!< FRT (Bitfield-Mask: 0x01) */ +/* ====================================================== HCFMNUMBER ======================================================= */ + #define R_USBHC_HCFMNUMBER_FN_Pos (0UL) /*!< FN (Bit 0) */ + #define R_USBHC_HCFMNUMBER_FN_Msk (0xffffUL) /*!< FN (Bitfield-Mask: 0xffff) */ +/* ===================================================== HCPERIODSTART ===================================================== */ + #define R_USBHC_HCPERIODSTART_PS_Pos (0UL) /*!< PS (Bit 0) */ + #define R_USBHC_HCPERIODSTART_PS_Msk (0x3fffUL) /*!< PS (Bitfield-Mask: 0x3fff) */ +/* ===================================================== HCLSTHRESHOLD ===================================================== */ + #define R_USBHC_HCLSTHRESHOLD_LS_Pos (0UL) /*!< LS (Bit 0) */ + #define R_USBHC_HCLSTHRESHOLD_LS_Msk (0xfffUL) /*!< LS (Bitfield-Mask: 0xfff) */ +/* ==================================================== HCRHDESCRIPTORA ==================================================== */ + #define R_USBHC_HCRHDESCRIPTORA_NDP_Pos (0UL) /*!< NDP (Bit 0) */ + #define R_USBHC_HCRHDESCRIPTORA_NDP_Msk (0xffUL) /*!< NDP (Bitfield-Mask: 0xff) */ + #define R_USBHC_HCRHDESCRIPTORA_PSM_Pos (8UL) /*!< PSM (Bit 8) */ + #define R_USBHC_HCRHDESCRIPTORA_PSM_Msk (0x100UL) /*!< PSM (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHDESCRIPTORA_NPS_Pos (9UL) /*!< NPS (Bit 9) */ + #define R_USBHC_HCRHDESCRIPTORA_NPS_Msk (0x200UL) /*!< NPS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHDESCRIPTORA_DT_Pos (10UL) /*!< DT (Bit 10) */ + #define R_USBHC_HCRHDESCRIPTORA_DT_Msk (0x400UL) /*!< DT (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHDESCRIPTORA_OCPM_Pos (11UL) /*!< OCPM (Bit 11) */ + #define R_USBHC_HCRHDESCRIPTORA_OCPM_Msk (0x800UL) /*!< OCPM (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHDESCRIPTORA_NOCP_Pos (12UL) /*!< NOCP (Bit 12) */ + #define R_USBHC_HCRHDESCRIPTORA_NOCP_Msk (0x1000UL) /*!< NOCP (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHDESCRIPTORA_POTPGT_Pos (24UL) /*!< POTPGT (Bit 24) */ + #define R_USBHC_HCRHDESCRIPTORA_POTPGT_Msk (0xff000000UL) /*!< POTPGT (Bitfield-Mask: 0xff) */ +/* ==================================================== HCRHDESCRIPTORB ==================================================== */ + #define R_USBHC_HCRHDESCRIPTORB_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_USBHC_HCRHDESCRIPTORB_DR_Msk (0xffffUL) /*!< DR (Bitfield-Mask: 0xffff) */ + #define R_USBHC_HCRHDESCRIPTORB_PPCM_Pos (16UL) /*!< PPCM (Bit 16) */ + #define R_USBHC_HCRHDESCRIPTORB_PPCM_Msk (0xffff0000UL) /*!< PPCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== HCRHSTATUS ======================================================= */ + #define R_USBHC_HCRHSTATUS_LPS_Pos (0UL) /*!< LPS (Bit 0) */ + #define R_USBHC_HCRHSTATUS_LPS_Msk (0x1UL) /*!< LPS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHSTATUS_OCI_Pos (1UL) /*!< OCI (Bit 1) */ + #define R_USBHC_HCRHSTATUS_OCI_Msk (0x2UL) /*!< OCI (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHSTATUS_DRWE_Pos (15UL) /*!< DRWE (Bit 15) */ + #define R_USBHC_HCRHSTATUS_DRWE_Msk (0x8000UL) /*!< DRWE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHSTATUS_LPSC_Pos (16UL) /*!< LPSC (Bit 16) */ + #define R_USBHC_HCRHSTATUS_LPSC_Msk (0x10000UL) /*!< LPSC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHSTATUS_OCIC_Pos (17UL) /*!< OCIC (Bit 17) */ + #define R_USBHC_HCRHSTATUS_OCIC_Msk (0x20000UL) /*!< OCIC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHSTATUS_CRWE_Pos (31UL) /*!< CRWE (Bit 31) */ + #define R_USBHC_HCRHSTATUS_CRWE_Msk (0x80000000UL) /*!< CRWE (Bitfield-Mask: 0x01) */ +/* ==================================================== HCRHPORTSTATUS1 ==================================================== */ + #define R_USBHC_HCRHPORTSTATUS1_CCS_Pos (0UL) /*!< CCS (Bit 0) */ + #define R_USBHC_HCRHPORTSTATUS1_CCS_Msk (0x1UL) /*!< CCS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PES_Pos (1UL) /*!< PES (Bit 1) */ + #define R_USBHC_HCRHPORTSTATUS1_PES_Msk (0x2UL) /*!< PES (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PSS_Pos (2UL) /*!< PSS (Bit 2) */ + #define R_USBHC_HCRHPORTSTATUS1_PSS_Msk (0x4UL) /*!< PSS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_POCI_Pos (3UL) /*!< POCI (Bit 3) */ + #define R_USBHC_HCRHPORTSTATUS1_POCI_Msk (0x8UL) /*!< POCI (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PRS_Pos (4UL) /*!< PRS (Bit 4) */ + #define R_USBHC_HCRHPORTSTATUS1_PRS_Msk (0x10UL) /*!< PRS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PPS_Pos (8UL) /*!< PPS (Bit 8) */ + #define R_USBHC_HCRHPORTSTATUS1_PPS_Msk (0x100UL) /*!< PPS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_LSDA_Pos (9UL) /*!< LSDA (Bit 9) */ + #define R_USBHC_HCRHPORTSTATUS1_LSDA_Msk (0x200UL) /*!< LSDA (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_CSC_Pos (16UL) /*!< CSC (Bit 16) */ + #define R_USBHC_HCRHPORTSTATUS1_CSC_Msk (0x10000UL) /*!< CSC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PESC_Pos (17UL) /*!< PESC (Bit 17) */ + #define R_USBHC_HCRHPORTSTATUS1_PESC_Msk (0x20000UL) /*!< PESC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PSSC_Pos (18UL) /*!< PSSC (Bit 18) */ + #define R_USBHC_HCRHPORTSTATUS1_PSSC_Msk (0x40000UL) /*!< PSSC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_OCIC_Pos (19UL) /*!< OCIC (Bit 19) */ + #define R_USBHC_HCRHPORTSTATUS1_OCIC_Msk (0x80000UL) /*!< OCIC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PRSC_Pos (20UL) /*!< PRSC (Bit 20) */ + #define R_USBHC_HCRHPORTSTATUS1_PRSC_Msk (0x100000UL) /*!< PRSC (Bitfield-Mask: 0x01) */ +/* ===================================================== CAPL_VERSION ====================================================== */ + #define R_USBHC_CAPL_VERSION_CRL_Pos (0UL) /*!< CRL (Bit 0) */ + #define R_USBHC_CAPL_VERSION_CRL_Msk (0xffUL) /*!< CRL (Bitfield-Mask: 0xff) */ + #define R_USBHC_CAPL_VERSION_HCIVN_Pos (16UL) /*!< HCIVN (Bit 16) */ + #define R_USBHC_CAPL_VERSION_HCIVN_Msk (0xffff0000UL) /*!< HCIVN (Bitfield-Mask: 0xffff) */ +/* ======================================================= HCSPARAMS ======================================================= */ + #define R_USBHC_HCSPARAMS_N_PORTS_Pos (0UL) /*!< N_PORTS (Bit 0) */ + #define R_USBHC_HCSPARAMS_N_PORTS_Msk (0xfUL) /*!< N_PORTS (Bitfield-Mask: 0x0f) */ + #define R_USBHC_HCSPARAMS_PPC_Pos (4UL) /*!< PPC (Bit 4) */ + #define R_USBHC_HCSPARAMS_PPC_Msk (0x10UL) /*!< PPC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCSPARAMS_PTRR_Pos (7UL) /*!< PTRR (Bit 7) */ + #define R_USBHC_HCSPARAMS_PTRR_Msk (0x80UL) /*!< PTRR (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCSPARAMS_N_PCC_Pos (8UL) /*!< N_PCC (Bit 8) */ + #define R_USBHC_HCSPARAMS_N_PCC_Msk (0xf00UL) /*!< N_PCC (Bitfield-Mask: 0x0f) */ + #define R_USBHC_HCSPARAMS_N_CC_Pos (12UL) /*!< N_CC (Bit 12) */ + #define R_USBHC_HCSPARAMS_N_CC_Msk (0xf000UL) /*!< N_CC (Bitfield-Mask: 0x0f) */ + #define R_USBHC_HCSPARAMS_P_INDICATOR_Pos (16UL) /*!< P_INDICATOR (Bit 16) */ + #define R_USBHC_HCSPARAMS_P_INDICATOR_Msk (0x10000UL) /*!< P_INDICATOR (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCSPARAMS_DBGPTNUM_Pos (20UL) /*!< DBGPTNUM (Bit 20) */ + #define R_USBHC_HCSPARAMS_DBGPTNUM_Msk (0xf00000UL) /*!< DBGPTNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= HCCPARAMS ======================================================= */ + #define R_USBHC_HCCPARAMS_AC64_Pos (0UL) /*!< AC64 (Bit 0) */ + #define R_USBHC_HCCPARAMS_AC64_Msk (0x1UL) /*!< AC64 (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_PFLF_Pos (1UL) /*!< PFLF (Bit 1) */ + #define R_USBHC_HCCPARAMS_PFLF_Msk (0x2UL) /*!< PFLF (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_ASPC_Pos (2UL) /*!< ASPC (Bit 2) */ + #define R_USBHC_HCCPARAMS_ASPC_Msk (0x4UL) /*!< ASPC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_IST_Pos (4UL) /*!< IST (Bit 4) */ + #define R_USBHC_HCCPARAMS_IST_Msk (0xf0UL) /*!< IST (Bitfield-Mask: 0x0f) */ + #define R_USBHC_HCCPARAMS_EECP_Pos (8UL) /*!< EECP (Bit 8) */ + #define R_USBHC_HCCPARAMS_EECP_Msk (0xff00UL) /*!< EECP (Bitfield-Mask: 0xff) */ + #define R_USBHC_HCCPARAMS_HP_Pos (16UL) /*!< HP (Bit 16) */ + #define R_USBHC_HCCPARAMS_HP_Msk (0x10000UL) /*!< HP (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_LPMC_Pos (17UL) /*!< LPMC (Bit 17) */ + #define R_USBHC_HCCPARAMS_LPMC_Msk (0x20000UL) /*!< LPMC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_PCEC_Pos (18UL) /*!< PCEC (Bit 18) */ + #define R_USBHC_HCCPARAMS_PCEC_Msk (0x40000UL) /*!< PCEC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_PL32_Pos (19UL) /*!< PL32 (Bit 19) */ + #define R_USBHC_HCCPARAMS_PL32_Msk (0x80000UL) /*!< PL32 (Bitfield-Mask: 0x01) */ +/* ==================================================== HCSP_PORTROUTE ===================================================== */ +/* ======================================================== USBCMD ========================================================= */ + #define R_USBHC_USBCMD_RS_Pos (0UL) /*!< RS (Bit 0) */ + #define R_USBHC_USBCMD_RS_Msk (0x1UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_HCRESET_Pos (1UL) /*!< HCRESET (Bit 1) */ + #define R_USBHC_USBCMD_HCRESET_Msk (0x2UL) /*!< HCRESET (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_FLS_Pos (2UL) /*!< FLS (Bit 2) */ + #define R_USBHC_USBCMD_FLS_Msk (0xcUL) /*!< FLS (Bitfield-Mask: 0x03) */ + #define R_USBHC_USBCMD_PSE_Pos (4UL) /*!< PSE (Bit 4) */ + #define R_USBHC_USBCMD_PSE_Msk (0x10UL) /*!< PSE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_ASYNSE_Pos (5UL) /*!< ASYNSE (Bit 5) */ + #define R_USBHC_USBCMD_ASYNSE_Msk (0x20UL) /*!< ASYNSE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_IAAD_Pos (6UL) /*!< IAAD (Bit 6) */ + #define R_USBHC_USBCMD_IAAD_Msk (0x40UL) /*!< IAAD (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_LHCR_Pos (7UL) /*!< LHCR (Bit 7) */ + #define R_USBHC_USBCMD_LHCR_Msk (0x80UL) /*!< LHCR (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_ASPMC_Pos (8UL) /*!< ASPMC (Bit 8) */ + #define R_USBHC_USBCMD_ASPMC_Msk (0x300UL) /*!< ASPMC (Bitfield-Mask: 0x03) */ + #define R_USBHC_USBCMD_ASPME_Pos (11UL) /*!< ASPME (Bit 11) */ + #define R_USBHC_USBCMD_ASPME_Msk (0x800UL) /*!< ASPME (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_PPCEE_Pos (15UL) /*!< PPCEE (Bit 15) */ + #define R_USBHC_USBCMD_PPCEE_Msk (0x8000UL) /*!< PPCEE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_ITC_Pos (16UL) /*!< ITC (Bit 16) */ + #define R_USBHC_USBCMD_ITC_Msk (0xff0000UL) /*!< ITC (Bitfield-Mask: 0xff) */ + #define R_USBHC_USBCMD_HIRD_Pos (24UL) /*!< HIRD (Bit 24) */ + #define R_USBHC_USBCMD_HIRD_Msk (0xf000000UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ +/* ======================================================== USBSTS ========================================================= */ + #define R_USBHC_USBSTS_USBINT_Pos (0UL) /*!< USBINT (Bit 0) */ + #define R_USBHC_USBSTS_USBINT_Msk (0x1UL) /*!< USBINT (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_USBERRINT_Pos (1UL) /*!< USBERRINT (Bit 1) */ + #define R_USBHC_USBSTS_USBERRINT_Msk (0x2UL) /*!< USBERRINT (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_PTCGDET_Pos (2UL) /*!< PTCGDET (Bit 2) */ + #define R_USBHC_USBSTS_PTCGDET_Msk (0x4UL) /*!< PTCGDET (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_FLROV_Pos (3UL) /*!< FLROV (Bit 3) */ + #define R_USBHC_USBSTS_FLROV_Msk (0x8UL) /*!< FLROV (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_HSYSE_Pos (4UL) /*!< HSYSE (Bit 4) */ + #define R_USBHC_USBSTS_HSYSE_Msk (0x10UL) /*!< HSYSE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_IAAIS_Pos (5UL) /*!< IAAIS (Bit 5) */ + #define R_USBHC_USBSTS_IAAIS_Msk (0x20UL) /*!< IAAIS (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_EHCSTS_Pos (12UL) /*!< EHCSTS (Bit 12) */ + #define R_USBHC_USBSTS_EHCSTS_Msk (0x1000UL) /*!< EHCSTS (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_RECLAM_Pos (13UL) /*!< RECLAM (Bit 13) */ + #define R_USBHC_USBSTS_RECLAM_Msk (0x2000UL) /*!< RECLAM (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_PSCHSTS_Pos (14UL) /*!< PSCHSTS (Bit 14) */ + #define R_USBHC_USBSTS_PSCHSTS_Msk (0x4000UL) /*!< PSCHSTS (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_ASS_Pos (15UL) /*!< ASS (Bit 15) */ + #define R_USBHC_USBSTS_ASS_Msk (0x8000UL) /*!< ASS (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_PTCGDETC_Pos (16UL) /*!< PTCGDETC (Bit 16) */ + #define R_USBHC_USBSTS_PTCGDETC_Msk (0xffff0000UL) /*!< PTCGDETC (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINTR ======================================================== */ + #define R_USBHC_USBINTR_USBIE_Pos (0UL) /*!< USBIE (Bit 0) */ + #define R_USBHC_USBINTR_USBIE_Msk (0x1UL) /*!< USBIE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_USBEIE_Pos (1UL) /*!< USBEIE (Bit 1) */ + #define R_USBHC_USBINTR_USBEIE_Msk (0x2UL) /*!< USBEIE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_PTCGIE_Pos (2UL) /*!< PTCGIE (Bit 2) */ + #define R_USBHC_USBINTR_PTCGIE_Msk (0x4UL) /*!< PTCGIE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_FMLSTROE_Pos (3UL) /*!< FMLSTROE (Bit 3) */ + #define R_USBHC_USBINTR_FMLSTROE_Msk (0x8UL) /*!< FMLSTROE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_HSEE_Pos (4UL) /*!< HSEE (Bit 4) */ + #define R_USBHC_USBINTR_HSEE_Msk (0x10UL) /*!< HSEE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_INTAADVE_Pos (5UL) /*!< INTAADVE (Bit 5) */ + #define R_USBHC_USBINTR_INTAADVE_Msk (0x20UL) /*!< INTAADVE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_PCGIE_Pos (16UL) /*!< PCGIE (Bit 16) */ + #define R_USBHC_USBINTR_PCGIE_Msk (0xffff0000UL) /*!< PCGIE (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRINDEX ======================================================== */ + #define R_USBHC_FRINDEX_FRAMEINDEX_Pos (0UL) /*!< FRAMEINDEX (Bit 0) */ + #define R_USBHC_FRINDEX_FRAMEINDEX_Msk (0x3fffUL) /*!< FRAMEINDEX (Bitfield-Mask: 0x3fff) */ +/* ===================================================== CTRLDSSEGMENT ===================================================== */ +/* =================================================== PERIODICLISTBASE ==================================================== */ + #define R_USBHC_PERIODICLISTBASE_PFLSA_Pos (12UL) /*!< PFLSA (Bit 12) */ + #define R_USBHC_PERIODICLISTBASE_PFLSA_Msk (0xfffff000UL) /*!< PFLSA (Bitfield-Mask: 0xfffff) */ +/* ===================================================== ASYNCLISTADDR ===================================================== */ + #define R_USBHC_ASYNCLISTADDR_LPL_Pos (5UL) /*!< LPL (Bit 5) */ + #define R_USBHC_ASYNCLISTADDR_LPL_Msk (0xffffffe0UL) /*!< LPL (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== CONFIGFLAG ======================================================= */ + #define R_USBHC_CONFIGFLAG_CF_Pos (0UL) /*!< CF (Bit 0) */ + #define R_USBHC_CONFIGFLAG_CF_Msk (0x1UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ======================================================== PORTSC1 ======================================================== */ + #define R_USBHC_PORTSC1_CCSTS_Pos (0UL) /*!< CCSTS (Bit 0) */ + #define R_USBHC_PORTSC1_CCSTS_Msk (0x1UL) /*!< CCSTS (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_CSC_Pos (1UL) /*!< CSC (Bit 1) */ + #define R_USBHC_PORTSC1_CSC_Msk (0x2UL) /*!< CSC (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_PTE_Pos (2UL) /*!< PTE (Bit 2) */ + #define R_USBHC_PORTSC1_PTE_Msk (0x4UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_PTESC_Pos (3UL) /*!< PTESC (Bit 3) */ + #define R_USBHC_PORTSC1_PTESC_Msk (0x8UL) /*!< PTESC (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_OVCACT_Pos (4UL) /*!< OVCACT (Bit 4) */ + #define R_USBHC_PORTSC1_OVCACT_Msk (0x10UL) /*!< OVCACT (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_OVCC_Pos (5UL) /*!< OVCC (Bit 5) */ + #define R_USBHC_PORTSC1_OVCC_Msk (0x20UL) /*!< OVCC (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_FRCPTRSM_Pos (6UL) /*!< FRCPTRSM (Bit 6) */ + #define R_USBHC_PORTSC1_FRCPTRSM_Msk (0x40UL) /*!< FRCPTRSM (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_SUSPEND_Pos (7UL) /*!< SUSPEND (Bit 7) */ + #define R_USBHC_PORTSC1_SUSPEND_Msk (0x80UL) /*!< SUSPEND (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_PTRST_Pos (8UL) /*!< PTRST (Bit 8) */ + #define R_USBHC_PORTSC1_PTRST_Msk (0x100UL) /*!< PTRST (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_LPMCTL_Pos (9UL) /*!< LPMCTL (Bit 9) */ + #define R_USBHC_PORTSC1_LPMCTL_Msk (0x200UL) /*!< LPMCTL (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_LINESTS_Pos (10UL) /*!< LINESTS (Bit 10) */ + #define R_USBHC_PORTSC1_LINESTS_Msk (0xc00UL) /*!< LINESTS (Bitfield-Mask: 0x03) */ + #define R_USBHC_PORTSC1_PP_Pos (12UL) /*!< PP (Bit 12) */ + #define R_USBHC_PORTSC1_PP_Msk (0x1000UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_PTOWNR_Pos (13UL) /*!< PTOWNR (Bit 13) */ + #define R_USBHC_PORTSC1_PTOWNR_Msk (0x2000UL) /*!< PTOWNR (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_PTINDCTL_Pos (14UL) /*!< PTINDCTL (Bit 14) */ + #define R_USBHC_PORTSC1_PTINDCTL_Msk (0xc000UL) /*!< PTINDCTL (Bitfield-Mask: 0x03) */ + #define R_USBHC_PORTSC1_PTTST_Pos (16UL) /*!< PTTST (Bit 16) */ + #define R_USBHC_PORTSC1_PTTST_Msk (0xf0000UL) /*!< PTTST (Bitfield-Mask: 0x0f) */ + #define R_USBHC_PORTSC1_WKCNNT_E_Pos (20UL) /*!< WKCNNT_E (Bit 20) */ + #define R_USBHC_PORTSC1_WKCNNT_E_Msk (0x100000UL) /*!< WKCNNT_E (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_WKDSCNNT_E_Pos (21UL) /*!< WKDSCNNT_E (Bit 21) */ + #define R_USBHC_PORTSC1_WKDSCNNT_E_Msk (0x200000UL) /*!< WKDSCNNT_E (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_WKOC_E_Pos (22UL) /*!< WKOC_E (Bit 22) */ + #define R_USBHC_PORTSC1_WKOC_E_Msk (0x400000UL) /*!< WKOC_E (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_SUSPSTS_Pos (23UL) /*!< SUSPSTS (Bit 23) */ + #define R_USBHC_PORTSC1_SUSPSTS_Msk (0x1800000UL) /*!< SUSPSTS (Bitfield-Mask: 0x03) */ + #define R_USBHC_PORTSC1_DVADDR_Pos (25UL) /*!< DVADDR (Bit 25) */ + #define R_USBHC_PORTSC1_DVADDR_Msk (0xfe000000UL) /*!< DVADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================= INTENABLE ======================================================= */ + #define R_USBHC_INTENABLE_AHB_INTEN_Pos (0UL) /*!< AHB_INTEN (Bit 0) */ + #define R_USBHC_INTENABLE_AHB_INTEN_Msk (0x1UL) /*!< AHB_INTEN (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTENABLE_USBH_INTAEN_Pos (1UL) /*!< USBH_INTAEN (Bit 1) */ + #define R_USBHC_INTENABLE_USBH_INTAEN_Msk (0x2UL) /*!< USBH_INTAEN (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTENABLE_USBH_INTBEN_Pos (2UL) /*!< USBH_INTBEN (Bit 2) */ + #define R_USBHC_INTENABLE_USBH_INTBEN_Msk (0x4UL) /*!< USBH_INTBEN (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTENABLE_UCOM_INTEN_Pos (3UL) /*!< UCOM_INTEN (Bit 3) */ + #define R_USBHC_INTENABLE_UCOM_INTEN_Msk (0x8UL) /*!< UCOM_INTEN (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTENABLE_WAKEON_INTEN_Pos (4UL) /*!< WAKEON_INTEN (Bit 4) */ + #define R_USBHC_INTENABLE_WAKEON_INTEN_Msk (0x10UL) /*!< WAKEON_INTEN (Bitfield-Mask: 0x01) */ +/* ======================================================= INTSTATUS ======================================================= */ + #define R_USBHC_INTSTATUS_AHB_INT_Pos (0UL) /*!< AHB_INT (Bit 0) */ + #define R_USBHC_INTSTATUS_AHB_INT_Msk (0x1UL) /*!< AHB_INT (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTSTATUS_USBH_INTA_Pos (1UL) /*!< USBH_INTA (Bit 1) */ + #define R_USBHC_INTSTATUS_USBH_INTA_Msk (0x2UL) /*!< USBH_INTA (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTSTATUS_USBH_INTB_Pos (2UL) /*!< USBH_INTB (Bit 2) */ + #define R_USBHC_INTSTATUS_USBH_INTB_Msk (0x4UL) /*!< USBH_INTB (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTSTATUS_UCOM_INT_Pos (3UL) /*!< UCOM_INT (Bit 3) */ + #define R_USBHC_INTSTATUS_UCOM_INT_Msk (0x8UL) /*!< UCOM_INT (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTSTATUS_WAKEON_INT_Pos (4UL) /*!< WAKEON_INT (Bit 4) */ + #define R_USBHC_INTSTATUS_WAKEON_INT_Msk (0x10UL) /*!< WAKEON_INT (Bitfield-Mask: 0x01) */ +/* ======================================================= AHBBUSCTR ======================================================= */ + #define R_USBHC_AHBBUSCTR_MAX_BURST_LEN_Pos (0UL) /*!< MAX_BURST_LEN (Bit 0) */ + #define R_USBHC_AHBBUSCTR_MAX_BURST_LEN_Msk (0x3UL) /*!< MAX_BURST_LEN (Bitfield-Mask: 0x03) */ + #define R_USBHC_AHBBUSCTR_ALIGN_ADDRESS_Pos (4UL) /*!< ALIGN_ADDRESS (Bit 4) */ + #define R_USBHC_AHBBUSCTR_ALIGN_ADDRESS_Msk (0x30UL) /*!< ALIGN_ADDRESS (Bitfield-Mask: 0x03) */ + #define R_USBHC_AHBBUSCTR_PROT_MODE_Pos (8UL) /*!< PROT_MODE (Bit 8) */ + #define R_USBHC_AHBBUSCTR_PROT_MODE_Msk (0x100UL) /*!< PROT_MODE (Bitfield-Mask: 0x01) */ + #define R_USBHC_AHBBUSCTR_PROT_TYPE_Pos (12UL) /*!< PROT_TYPE (Bit 12) */ + #define R_USBHC_AHBBUSCTR_PROT_TYPE_Msk (0xf000UL) /*!< PROT_TYPE (Bitfield-Mask: 0x0f) */ +/* ======================================================== USBCTR ========================================================= */ + #define R_USBHC_USBCTR_USBH_RST_Pos (0UL) /*!< USBH_RST (Bit 0) */ + #define R_USBHC_USBCTR_USBH_RST_Msk (0x1UL) /*!< USBH_RST (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCTR_PLL_RST_Pos (1UL) /*!< PLL_RST (Bit 1) */ + #define R_USBHC_USBCTR_PLL_RST_Msk (0x2UL) /*!< PLL_RST (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCTR_DIRPD_Pos (2UL) /*!< DIRPD (Bit 2) */ + #define R_USBHC_USBCTR_DIRPD_Msk (0x4UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ========================================================= REVID ========================================================= */ + #define R_USBHC_REVID_MINV_Pos (0UL) /*!< MINV (Bit 0) */ + #define R_USBHC_REVID_MINV_Msk (0xffUL) /*!< MINV (Bitfield-Mask: 0xff) */ + #define R_USBHC_REVID_MAJV_Pos (8UL) /*!< MAJV (Bit 8) */ + #define R_USBHC_REVID_MAJV_Msk (0xff00UL) /*!< MAJV (Bitfield-Mask: 0xff) */ + #define R_USBHC_REVID_COREID_Pos (24UL) /*!< COREID (Bit 24) */ + #define R_USBHC_REVID_COREID_Msk (0xff000000UL) /*!< COREID (Bitfield-Mask: 0xff) */ +/* ====================================================== OCSLPTIMSET ====================================================== */ + #define R_USBHC_OCSLPTIMSET_TIMER_OC_Pos (0UL) /*!< TIMER_OC (Bit 0) */ + #define R_USBHC_OCSLPTIMSET_TIMER_OC_Msk (0xfffffUL) /*!< TIMER_OC (Bitfield-Mask: 0xfffff) */ + #define R_USBHC_OCSLPTIMSET_TIMER_SLEEP_Pos (20UL) /*!< TIMER_SLEEP (Bit 20) */ + #define R_USBHC_OCSLPTIMSET_TIMER_SLEEP_Msk (0x1ff00000UL) /*!< TIMER_SLEEP (Bitfield-Mask: 0x1ff) */ +/* ======================================================= COMMCTRL ======================================================== */ + #define R_USBHC_COMMCTRL_PERI_Pos (31UL) /*!< PERI (Bit 31) */ + #define R_USBHC_COMMCTRL_PERI_Msk (0x80000000UL) /*!< PERI (Bitfield-Mask: 0x01) */ +/* ======================================================= OBINTSTA ======================================================== */ + #define R_USBHC_OBINTSTA_IDCHG_STA_Pos (0UL) /*!< IDCHG_STA (Bit 0) */ + #define R_USBHC_OBINTSTA_IDCHG_STA_Msk (0x1UL) /*!< IDCHG_STA (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTSTA_OCINT_STA_Pos (1UL) /*!< OCINT_STA (Bit 1) */ + #define R_USBHC_OBINTSTA_OCINT_STA_Msk (0x2UL) /*!< OCINT_STA (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTSTA_VBSTACHG_STA_Pos (2UL) /*!< VBSTACHG_STA (Bit 2) */ + #define R_USBHC_OBINTSTA_VBSTACHG_STA_Msk (0x4UL) /*!< VBSTACHG_STA (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTSTA_VBSTAINT_STA_Pos (3UL) /*!< VBSTAINT_STA (Bit 3) */ + #define R_USBHC_OBINTSTA_VBSTAINT_STA_Msk (0x8UL) /*!< VBSTAINT_STA (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTSTA_DMMONCHG_STA_Pos (16UL) /*!< DMMONCHG_STA (Bit 16) */ + #define R_USBHC_OBINTSTA_DMMONCHG_STA_Msk (0x10000UL) /*!< DMMONCHG_STA (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTSTA_DPMONCHG_STA_Pos (17UL) /*!< DPMONCHG_STA (Bit 17) */ + #define R_USBHC_OBINTSTA_DPMONCHG_STA_Msk (0x20000UL) /*!< DPMONCHG_STA (Bitfield-Mask: 0x01) */ +/* ======================================================== OBINTEN ======================================================== */ + #define R_USBHC_OBINTEN_IDCHG_EN_Pos (0UL) /*!< IDCHG_EN (Bit 0) */ + #define R_USBHC_OBINTEN_IDCHG_EN_Msk (0x1UL) /*!< IDCHG_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTEN_OCINT_EN_Pos (1UL) /*!< OCINT_EN (Bit 1) */ + #define R_USBHC_OBINTEN_OCINT_EN_Msk (0x2UL) /*!< OCINT_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTEN_VBSTACHG_EN_Pos (2UL) /*!< VBSTACHG_EN (Bit 2) */ + #define R_USBHC_OBINTEN_VBSTACHG_EN_Msk (0x4UL) /*!< VBSTACHG_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTEN_VBSTAINT_EN_Pos (3UL) /*!< VBSTAINT_EN (Bit 3) */ + #define R_USBHC_OBINTEN_VBSTAINT_EN_Msk (0x8UL) /*!< VBSTAINT_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTEN_DMMONCHG_EN_Pos (16UL) /*!< DMMONCHG_EN (Bit 16) */ + #define R_USBHC_OBINTEN_DMMONCHG_EN_Msk (0x10000UL) /*!< DMMONCHG_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTEN_DPMONCHG_EN_Pos (17UL) /*!< DPMONCHG_EN (Bit 17) */ + #define R_USBHC_OBINTEN_DPMONCHG_EN_Msk (0x20000UL) /*!< DPMONCHG_EN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBCTRL ========================================================= */ + #define R_USBHC_VBCTRL_VBOUT_Pos (0UL) /*!< VBOUT (Bit 0) */ + #define R_USBHC_VBCTRL_VBOUT_Msk (0x1UL) /*!< VBOUT (Bitfield-Mask: 0x01) */ + #define R_USBHC_VBCTRL_VBUSENSEL_Pos (1UL) /*!< VBUSENSEL (Bit 1) */ + #define R_USBHC_VBCTRL_VBUSENSEL_Msk (0x2UL) /*!< VBUSENSEL (Bitfield-Mask: 0x01) */ + #define R_USBHC_VBCTRL_VGPUO_Pos (4UL) /*!< VGPUO (Bit 4) */ + #define R_USBHC_VBCTRL_VGPUO_Msk (0x10UL) /*!< VGPUO (Bitfield-Mask: 0x01) */ + #define R_USBHC_VBCTRL_OCCLRIEN_Pos (16UL) /*!< OCCLRIEN (Bit 16) */ + #define R_USBHC_VBCTRL_OCCLRIEN_Msk (0x10000UL) /*!< OCCLRIEN (Bitfield-Mask: 0x01) */ + #define R_USBHC_VBCTRL_OCISEL_Pos (17UL) /*!< OCISEL (Bit 17) */ + #define R_USBHC_VBCTRL_OCISEL_Msk (0x20000UL) /*!< OCISEL (Bitfield-Mask: 0x01) */ + #define R_USBHC_VBCTRL_VBLVL_Pos (20UL) /*!< VBLVL (Bit 20) */ + #define R_USBHC_VBCTRL_VBLVL_Msk (0xf00000UL) /*!< VBLVL (Bitfield-Mask: 0x0f) */ + #define R_USBHC_VBCTRL_VBSTA_Pos (28UL) /*!< VBSTA (Bit 28) */ + #define R_USBHC_VBCTRL_VBSTA_Msk (0xf0000000UL) /*!< VBSTA (Bitfield-Mask: 0x0f) */ +/* ======================================================= LINECTRL1 ======================================================= */ + #define R_USBHC_LINECTRL1_IDMON_Pos (0UL) /*!< IDMON (Bit 0) */ + #define R_USBHC_LINECTRL1_IDMON_Msk (0x1UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DMMON_Pos (2UL) /*!< DMMON (Bit 2) */ + #define R_USBHC_LINECTRL1_DMMON_Msk (0x4UL) /*!< DMMON (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DPMON_Pos (3UL) /*!< DPMON (Bit 3) */ + #define R_USBHC_LINECTRL1_DPMON_Msk (0x8UL) /*!< DPMON (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DM_RPD_Pos (16UL) /*!< DM_RPD (Bit 16) */ + #define R_USBHC_LINECTRL1_DM_RPD_Msk (0x10000UL) /*!< DM_RPD (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DMRPD_EN_Pos (17UL) /*!< DMRPD_EN (Bit 17) */ + #define R_USBHC_LINECTRL1_DMRPD_EN_Msk (0x20000UL) /*!< DMRPD_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DP_RPD_Pos (18UL) /*!< DP_RPD (Bit 18) */ + #define R_USBHC_LINECTRL1_DP_RPD_Msk (0x40000UL) /*!< DP_RPD (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DPRPD_EN_Pos (19UL) /*!< DPRPD_EN (Bit 19) */ + #define R_USBHC_LINECTRL1_DPRPD_EN_Msk (0x80000UL) /*!< DPRPD_EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USBF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG0 ======================================================== */ + #define R_USBF_SYSCFG0_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USBF_SYSCFG0_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ + #define R_USBF_SYSCFG0_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USBF_SYSCFG0_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USBF_SYSCFG0_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USBF_SYSCFG0_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USBF_SYSCFG0_HSE_Pos (7UL) /*!< HSE (Bit 7) */ + #define R_USBF_SYSCFG0_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ + #define R_USBF_SYSCFG0_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USBF_SYSCFG0_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SYSCFG1 ======================================================== */ + #define R_USBF_SYSCFG1_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USBF_SYSCFG1_BWAIT_Msk (0x3fUL) /*!< BWAIT (Bitfield-Mask: 0x3f) */ + #define R_USBF_SYSCFG1_AWAIT_Pos (8UL) /*!< AWAIT (Bit 8) */ + #define R_USBF_SYSCFG1_AWAIT_Msk (0x3f00UL) /*!< AWAIT (Bitfield-Mask: 0x3f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USBF_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USBF_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USBF_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USBF_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ + #define R_USBF_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USBF_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USBF_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USBF_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFIFO ========================================================= */ + #define R_USBF_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ======================================================== CFIFOH ========================================================= */ + #define R_USBF_CFIFOH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_CFIFOH_FIFOPORT_Msk (0xffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFIFOHH ======================================================== */ + #define R_USBF_CFIFOHH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_CFIFOHH_FIFOPORT_Msk (0xffUL) /*!< FIFOPORT (Bitfield-Mask: 0xff) */ +/* ======================================================== D0FIFO ========================================================= */ + #define R_USBF_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFOH ======================================================== */ + #define R_USBF_D0FIFOH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D0FIFOH_FIFOPORT_Msk (0xffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffff) */ +/* ======================================================= D0FIFOHH ======================================================== */ + #define R_USBF_D0FIFOHH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D0FIFOHH_FIFOPORT_Msk (0xffUL) /*!< FIFOPORT (Bitfield-Mask: 0xff) */ +/* ======================================================== D1FIFO ========================================================= */ + #define R_USBF_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFOH ======================================================== */ + #define R_USBF_D1FIFOH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D1FIFOH_FIFOPORT_Msk (0xffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffff) */ +/* ======================================================= D1FIFOHH ======================================================== */ + #define R_USBF_D1FIFOHH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D1FIFOHH_FIFOPORT_Msk (0xffUL) /*!< FIFOPORT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USBF_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USBF_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ + #define R_USBF_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USBF_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USBF_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USBF_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USBF_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USBF_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USBF_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USBF_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USBF_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USBF_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USBF_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USBF_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ + #define R_USBF_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USBF_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USBF_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USBF_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USBF_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USBF_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USBF_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ + #define R_USBF_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USBF_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USBF_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USBF_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USBF_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USBF_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USBF_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USBF_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USBF_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USBF_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ + #define R_USBF_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USBF_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USBF_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USBF_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USBF_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USBF_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USBF_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USBF_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USBF_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USBF_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ + #define R_USBF_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USBF_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USBF_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USBF_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USBF_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USBF_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ + #define R_USBF_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USBF_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USBF_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USBF_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USBF_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USBF_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USBF_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USBF_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USBF_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USBF_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USBF_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USBF_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USBF_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USBF_INTENB1_PDDETINTE_Pos (0UL) /*!< PDDETINTE (Bit 0) */ + #define R_USBF_INTENB1_PDDETINTE_Msk (0x1UL) /*!< PDDETINTE (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USBF_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USBF_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USBF_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USBF_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USBF_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USBF_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USBF_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USBF_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ + #define R_USBF_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USBF_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USBF_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USBF_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USBF_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USBF_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ + #define R_USBF_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USBF_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USBF_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USBF_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USBF_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USBF_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USBF_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USBF_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USBF_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USBF_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USBF_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USBF_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USBF_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USBF_INTSTS1_PDDETINT_Pos (0UL) /*!< PDDETINT (Bit 0) */ + #define R_USBF_INTSTS1_PDDETINT_Msk (0x1UL) /*!< PDDETINT (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USBF_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USBF_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USBF_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USBF_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USBF_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USBF_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USBF_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USBF_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ + #define R_USBF_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USBF_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USBF_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USBF_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USBF_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USBF_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USBF_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USBF_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USBF_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USBF_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ + #define R_USBF_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USBF_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USBF_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USBF_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USBF_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USBF_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USBF_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USBF_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USBF_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USBF_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USBF_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USBF_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USBF_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USBF_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USBF_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ + #define R_USBF_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USBF_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USBF_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USBF_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USBF_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USBF_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USBF_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USBF_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USBF_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USBF_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USBF_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ + #define R_USBF_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USBF_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USBF_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USBF_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USBF_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USBF_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USBF_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPEBUF ======================================================== */ + #define R_USBF_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ + #define R_USBF_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ + #define R_USBF_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ + #define R_USBF_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USBF_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USBF_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USBF_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USBF_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ + #define R_USBF_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USBF_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USBF_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USBF_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ + #define R_USBF_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USBF_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USBF_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USBF_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USBF_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USBF_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USBF_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USBF_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USBF_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USBF_LPSTS_SUSPM_Pos (14UL) /*!< SUSPM (Bit 14) */ + #define R_USBF_LPSTS_SUSPM_Msk (0x4000UL) /*!< SUSPM (Bitfield-Mask: 0x01) */ +/* ========================================================= DCTRL ========================================================= */ + #define R_USBF_DCTRL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_USBF_DCTRL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_USBF_DCTRL_LDPR_Pos (16UL) /*!< LDPR (Bit 16) */ + #define R_USBF_DCTRL_LDPR_Msk (0xf0000UL) /*!< LDPR (Bitfield-Mask: 0x0f) */ + #define R_USBF_DCTRL_LWPR_Pos (24UL) /*!< LWPR (Bit 24) */ + #define R_USBF_DCTRL_LWPR_Msk (0xf000000UL) /*!< LWPR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DSCITVL ======================================================== */ + #define R_USBF_DSCITVL_DITVL_Pos (8UL) /*!< DITVL (Bit 8) */ + #define R_USBF_DSCITVL_DITVL_Msk (0xff00UL) /*!< DITVL (Bitfield-Mask: 0xff) */ +/* ======================================================= DSTAT_EN ======================================================== */ + #define R_USBF_DSTAT_EN_EN0_Pos (0UL) /*!< EN0 (Bit 0) */ + #define R_USBF_DSTAT_EN_EN0_Msk (0x1UL) /*!< EN0 (Bitfield-Mask: 0x01) */ + #define R_USBF_DSTAT_EN_EN1_Pos (1UL) /*!< EN1 (Bit 1) */ + #define R_USBF_DSTAT_EN_EN1_Msk (0x2UL) /*!< EN1 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_ER ======================================================== */ + #define R_USBF_DSTAT_ER_ER0_Pos (0UL) /*!< ER0 (Bit 0) */ + #define R_USBF_DSTAT_ER_ER0_Msk (0x1UL) /*!< ER0 (Bitfield-Mask: 0x01) */ + #define R_USBF_DSTAT_ER_ER1_Pos (1UL) /*!< ER1 (Bit 1) */ + #define R_USBF_DSTAT_ER_ER1_Msk (0x2UL) /*!< ER1 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_END ======================================================= */ + #define R_USBF_DSTAT_END_END0_Pos (0UL) /*!< END0 (Bit 0) */ + #define R_USBF_DSTAT_END_END0_Msk (0x1UL) /*!< END0 (Bitfield-Mask: 0x01) */ + #define R_USBF_DSTAT_END_END1_Pos (1UL) /*!< END1 (Bit 1) */ + #define R_USBF_DSTAT_END_END1_Msk (0x2UL) /*!< END1 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_TC ======================================================== */ + #define R_USBF_DSTAT_TC_TC0_Pos (0UL) /*!< TC0 (Bit 0) */ + #define R_USBF_DSTAT_TC_TC0_Msk (0x1UL) /*!< TC0 (Bitfield-Mask: 0x01) */ + #define R_USBF_DSTAT_TC_TC1_Pos (1UL) /*!< TC1 (Bit 1) */ + #define R_USBF_DSTAT_TC_TC1_Msk (0x2UL) /*!< TC1 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_SUS ======================================================= */ + #define R_USBF_DSTAT_SUS_SUS0_Pos (0UL) /*!< SUS0 (Bit 0) */ + #define R_USBF_DSTAT_SUS_SUS0_Msk (0x1UL) /*!< SUS0 (Bitfield-Mask: 0x01) */ + #define R_USBF_DSTAT_SUS_SUS1_Pos (1UL) /*!< SUS1 (Bit 1) */ + #define R_USBF_DSTAT_SUS_SUS1_Msk (0x2UL) /*!< SUS1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_BSC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CMNCR ========================================================= */ + #define R_BSC_CMNCR_DPRTY_Pos (9UL) /*!< DPRTY (Bit 9) */ + #define R_BSC_CMNCR_DPRTY_Msk (0x600UL) /*!< DPRTY (Bitfield-Mask: 0x03) */ + #define R_BSC_CMNCR_AL_Pos (24UL) /*!< AL (Bit 24) */ + #define R_BSC_CMNCR_AL_Msk (0x1000000UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_BSC_CMNCR_TL_Pos (28UL) /*!< TL (Bit 28) */ + #define R_BSC_CMNCR_TL_Msk (0x10000000UL) /*!< TL (Bitfield-Mask: 0x01) */ +/* ======================================================== CSnBCR ========================================================= */ + #define R_BSC_CSnBCR_BSZ_Pos (9UL) /*!< BSZ (Bit 9) */ + #define R_BSC_CSnBCR_BSZ_Msk (0x600UL) /*!< BSZ (Bitfield-Mask: 0x03) */ + #define R_BSC_CSnBCR_TYPE_Pos (12UL) /*!< TYPE (Bit 12) */ + #define R_BSC_CSnBCR_TYPE_Msk (0x7000UL) /*!< TYPE (Bitfield-Mask: 0x07) */ + #define R_BSC_CSnBCR_IWRRS_Pos (16UL) /*!< IWRRS (Bit 16) */ + #define R_BSC_CSnBCR_IWRRS_Msk (0x70000UL) /*!< IWRRS (Bitfield-Mask: 0x07) */ + #define R_BSC_CSnBCR_IWRRD_Pos (19UL) /*!< IWRRD (Bit 19) */ + #define R_BSC_CSnBCR_IWRRD_Msk (0x380000UL) /*!< IWRRD (Bitfield-Mask: 0x07) */ + #define R_BSC_CSnBCR_IWRWS_Pos (22UL) /*!< IWRWS (Bit 22) */ + #define R_BSC_CSnBCR_IWRWS_Msk (0x1c00000UL) /*!< IWRWS (Bitfield-Mask: 0x07) */ + #define R_BSC_CSnBCR_IWRWD_Pos (25UL) /*!< IWRWD (Bit 25) */ + #define R_BSC_CSnBCR_IWRWD_Msk (0xe000000UL) /*!< IWRWD (Bitfield-Mask: 0x07) */ + #define R_BSC_CSnBCR_IWW_Pos (28UL) /*!< IWW (Bit 28) */ + #define R_BSC_CSnBCR_IWW_Msk (0x70000000UL) /*!< IWW (Bitfield-Mask: 0x07) */ +/* ======================================================= CS0WCR_0 ======================================================== */ + #define R_BSC_CS0WCR_0_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_BSC_CS0WCR_0_HW_Msk (0x3UL) /*!< HW (Bitfield-Mask: 0x03) */ + #define R_BSC_CS0WCR_0_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS0WCR_0_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS0WCR_0_WR_Pos (7UL) /*!< WR (Bit 7) */ + #define R_BSC_CS0WCR_0_WR_Msk (0x780UL) /*!< WR (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS0WCR_0_SW_Pos (11UL) /*!< SW (Bit 11) */ + #define R_BSC_CS0WCR_0_SW_Msk (0x1800UL) /*!< SW (Bitfield-Mask: 0x03) */ + #define R_BSC_CS0WCR_0_BAS_Pos (20UL) /*!< BAS (Bit 20) */ + #define R_BSC_CS0WCR_0_BAS_Msk (0x100000UL) /*!< BAS (Bitfield-Mask: 0x01) */ +/* ======================================================= CS0WCR_1 ======================================================== */ + #define R_BSC_CS0WCR_1_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS0WCR_1_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS0WCR_1_W_Pos (7UL) /*!< W (Bit 7) */ + #define R_BSC_CS0WCR_1_W_Msk (0x780UL) /*!< W (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS0WCR_1_BW_Pos (16UL) /*!< BW (Bit 16) */ + #define R_BSC_CS0WCR_1_BW_Msk (0x30000UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define R_BSC_CS0WCR_1_BST_Pos (20UL) /*!< BST (Bit 20) */ + #define R_BSC_CS0WCR_1_BST_Msk (0x300000UL) /*!< BST (Bitfield-Mask: 0x03) */ +/* ======================================================= CS0WCR_2 ======================================================== */ + #define R_BSC_CS0WCR_2_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS0WCR_2_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS0WCR_2_W_Pos (7UL) /*!< W (Bit 7) */ + #define R_BSC_CS0WCR_2_W_Msk (0x780UL) /*!< W (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS0WCR_2_BW_Pos (16UL) /*!< BW (Bit 16) */ + #define R_BSC_CS0WCR_2_BW_Msk (0x30000UL) /*!< BW (Bitfield-Mask: 0x03) */ +/* ======================================================= CS2WCR_0 ======================================================== */ + #define R_BSC_CS2WCR_0_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS2WCR_0_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS2WCR_0_WR_Pos (7UL) /*!< WR (Bit 7) */ + #define R_BSC_CS2WCR_0_WR_Msk (0x780UL) /*!< WR (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS2WCR_0_BAS_Pos (20UL) /*!< BAS (Bit 20) */ + #define R_BSC_CS2WCR_0_BAS_Msk (0x100000UL) /*!< BAS (Bitfield-Mask: 0x01) */ +/* ======================================================= CS2WCR_1 ======================================================== */ + #define R_BSC_CS2WCR_1_A2CL_Pos (7UL) /*!< A2CL (Bit 7) */ + #define R_BSC_CS2WCR_1_A2CL_Msk (0x180UL) /*!< A2CL (Bitfield-Mask: 0x03) */ +/* ======================================================= CS3WCR_0 ======================================================== */ + #define R_BSC_CS3WCR_0_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS3WCR_0_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS3WCR_0_WR_Pos (7UL) /*!< WR (Bit 7) */ + #define R_BSC_CS3WCR_0_WR_Msk (0x780UL) /*!< WR (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS3WCR_0_BAS_Pos (20UL) /*!< BAS (Bit 20) */ + #define R_BSC_CS3WCR_0_BAS_Msk (0x100000UL) /*!< BAS (Bitfield-Mask: 0x01) */ +/* ======================================================= CS3WCR_1 ======================================================== */ + #define R_BSC_CS3WCR_1_WTRC_Pos (0UL) /*!< WTRC (Bit 0) */ + #define R_BSC_CS3WCR_1_WTRC_Msk (0x3UL) /*!< WTRC (Bitfield-Mask: 0x03) */ + #define R_BSC_CS3WCR_1_TRWL_Pos (3UL) /*!< TRWL (Bit 3) */ + #define R_BSC_CS3WCR_1_TRWL_Msk (0x18UL) /*!< TRWL (Bitfield-Mask: 0x03) */ + #define R_BSC_CS3WCR_1_A3CL_Pos (7UL) /*!< A3CL (Bit 7) */ + #define R_BSC_CS3WCR_1_A3CL_Msk (0x180UL) /*!< A3CL (Bitfield-Mask: 0x03) */ + #define R_BSC_CS3WCR_1_WTRCD_Pos (10UL) /*!< WTRCD (Bit 10) */ + #define R_BSC_CS3WCR_1_WTRCD_Msk (0xc00UL) /*!< WTRCD (Bitfield-Mask: 0x03) */ + #define R_BSC_CS3WCR_1_WTRP_Pos (13UL) /*!< WTRP (Bit 13) */ + #define R_BSC_CS3WCR_1_WTRP_Msk (0x6000UL) /*!< WTRP (Bitfield-Mask: 0x03) */ +/* ======================================================== CS5WCR ========================================================= */ + #define R_BSC_CS5WCR_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_BSC_CS5WCR_HW_Msk (0x3UL) /*!< HW (Bitfield-Mask: 0x03) */ + #define R_BSC_CS5WCR_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS5WCR_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS5WCR_WR_Pos (7UL) /*!< WR (Bit 7) */ + #define R_BSC_CS5WCR_WR_Msk (0x780UL) /*!< WR (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS5WCR_SW_Pos (11UL) /*!< SW (Bit 11) */ + #define R_BSC_CS5WCR_SW_Msk (0x1800UL) /*!< SW (Bitfield-Mask: 0x03) */ + #define R_BSC_CS5WCR_WW_Pos (16UL) /*!< WW (Bit 16) */ + #define R_BSC_CS5WCR_WW_Msk (0x70000UL) /*!< WW (Bitfield-Mask: 0x07) */ + #define R_BSC_CS5WCR_MPXWSBAS_Pos (20UL) /*!< MPXWSBAS (Bit 20) */ + #define R_BSC_CS5WCR_MPXWSBAS_Msk (0x100000UL) /*!< MPXWSBAS (Bitfield-Mask: 0x01) */ + #define R_BSC_CS5WCR_SZSEL_Pos (21UL) /*!< SZSEL (Bit 21) */ + #define R_BSC_CS5WCR_SZSEL_Msk (0x200000UL) /*!< SZSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= SDCR ========================================================== */ + #define R_BSC_SDCR_A3COL_Pos (0UL) /*!< A3COL (Bit 0) */ + #define R_BSC_SDCR_A3COL_Msk (0x3UL) /*!< A3COL (Bitfield-Mask: 0x03) */ + #define R_BSC_SDCR_A3ROW_Pos (3UL) /*!< A3ROW (Bit 3) */ + #define R_BSC_SDCR_A3ROW_Msk (0x18UL) /*!< A3ROW (Bitfield-Mask: 0x03) */ + #define R_BSC_SDCR_BACTV_Pos (8UL) /*!< BACTV (Bit 8) */ + #define R_BSC_SDCR_BACTV_Msk (0x100UL) /*!< BACTV (Bitfield-Mask: 0x01) */ + #define R_BSC_SDCR_PDOWN_Pos (9UL) /*!< PDOWN (Bit 9) */ + #define R_BSC_SDCR_PDOWN_Msk (0x200UL) /*!< PDOWN (Bitfield-Mask: 0x01) */ + #define R_BSC_SDCR_RMODE_Pos (10UL) /*!< RMODE (Bit 10) */ + #define R_BSC_SDCR_RMODE_Msk (0x400UL) /*!< RMODE (Bitfield-Mask: 0x01) */ + #define R_BSC_SDCR_RFSH_Pos (11UL) /*!< RFSH (Bit 11) */ + #define R_BSC_SDCR_RFSH_Msk (0x800UL) /*!< RFSH (Bitfield-Mask: 0x01) */ + #define R_BSC_SDCR_DEEP_Pos (13UL) /*!< DEEP (Bit 13) */ + #define R_BSC_SDCR_DEEP_Msk (0x2000UL) /*!< DEEP (Bitfield-Mask: 0x01) */ + #define R_BSC_SDCR_A2COL_Pos (16UL) /*!< A2COL (Bit 16) */ + #define R_BSC_SDCR_A2COL_Msk (0x30000UL) /*!< A2COL (Bitfield-Mask: 0x03) */ + #define R_BSC_SDCR_A2ROW_Pos (19UL) /*!< A2ROW (Bit 19) */ + #define R_BSC_SDCR_A2ROW_Msk (0x180000UL) /*!< A2ROW (Bitfield-Mask: 0x03) */ +/* ========================================================= RTCSR ========================================================= */ +/* ========================================================= RTCNT ========================================================= */ +/* ========================================================= RTCOR ========================================================= */ +/* ======================================================== TOSCOR ========================================================= */ + #define R_BSC_TOSCOR_TOCNUM_Pos (0UL) /*!< TOCNUM (Bit 0) */ + #define R_BSC_TOSCOR_TOCNUM_Msk (0xffffUL) /*!< TOCNUM (Bitfield-Mask: 0xffff) */ +/* ========================================================= TOSTR ========================================================= */ + #define R_BSC_TOSTR_CS0TOSTF_Pos (0UL) /*!< CS0TOSTF (Bit 0) */ + #define R_BSC_TOSTR_CS0TOSTF_Msk (0x1UL) /*!< CS0TOSTF (Bitfield-Mask: 0x01) */ + #define R_BSC_TOSTR_CS2TOSTF_Pos (2UL) /*!< CS2TOSTF (Bit 2) */ + #define R_BSC_TOSTR_CS2TOSTF_Msk (0x4UL) /*!< CS2TOSTF (Bitfield-Mask: 0x01) */ + #define R_BSC_TOSTR_CS3TOSTF_Pos (3UL) /*!< CS3TOSTF (Bit 3) */ + #define R_BSC_TOSTR_CS3TOSTF_Msk (0x8UL) /*!< CS3TOSTF (Bitfield-Mask: 0x01) */ + #define R_BSC_TOSTR_CS5TOSTF_Pos (5UL) /*!< CS5TOSTF (Bit 5) */ + #define R_BSC_TOSTR_CS5TOSTF_Msk (0x20UL) /*!< CS5TOSTF (Bitfield-Mask: 0x01) */ +/* ========================================================= TOENR ========================================================= */ + #define R_BSC_TOENR_CS0TOEN_Pos (0UL) /*!< CS0TOEN (Bit 0) */ + #define R_BSC_TOENR_CS0TOEN_Msk (0x1UL) /*!< CS0TOEN (Bitfield-Mask: 0x01) */ + #define R_BSC_TOENR_CS2TOEN_Pos (2UL) /*!< CS2TOEN (Bit 2) */ + #define R_BSC_TOENR_CS2TOEN_Msk (0x4UL) /*!< CS2TOEN (Bitfield-Mask: 0x01) */ + #define R_BSC_TOENR_CS3TOEN_Pos (3UL) /*!< CS3TOEN (Bit 3) */ + #define R_BSC_TOENR_CS3TOEN_Msk (0x8UL) /*!< CS3TOEN (Bitfield-Mask: 0x01) */ + #define R_BSC_TOENR_CS5TOEN_Pos (5UL) /*!< CS5TOEN (Bit 5) */ + #define R_BSC_TOENR_CS5TOEN_Msk (0x20UL) /*!< CS5TOEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== WRAPCFG ======================================================== */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Pos (8UL) /*!< DSSFTCS0 (Bit 8) */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Msk (0x1f00UL) /*!< DSSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Pos (24UL) /*!< DSSFTCS1 (Bit 24) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Msk (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f) */ +/* ======================================================== COMCFG ========================================================= */ + #define R_XSPI0_COMCFG_OEASTEX_Pos (16UL) /*!< OEASTEX (Bit 16) */ + #define R_XSPI0_COMCFG_OEASTEX_Msk (0x10000UL) /*!< OEASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMCFG_OENEGEX_Pos (17UL) /*!< OENEGEX (Bit 17) */ + #define R_XSPI0_COMCFG_OENEGEX_Msk (0x20000UL) /*!< OENEGEX (Bitfield-Mask: 0x01) */ +/* ========================================================= BMCFG ========================================================= */ + #define R_XSPI0_BMCFG_WRMD_Pos (0UL) /*!< WRMD (Bit 0) */ + #define R_XSPI0_BMCFG_WRMD_Msk (0x1UL) /*!< WRMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFG_MWRCOMB_Pos (7UL) /*!< MWRCOMB (Bit 7) */ + #define R_XSPI0_BMCFG_MWRCOMB_Msk (0x80UL) /*!< MWRCOMB (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFG_MWRSIZE_Pos (8UL) /*!< MWRSIZE (Bit 8) */ + #define R_XSPI0_BMCFG_MWRSIZE_Msk (0xff00UL) /*!< MWRSIZE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_BMCFG_PREEN_Pos (16UL) /*!< PREEN (Bit 16) */ + #define R_XSPI0_BMCFG_PREEN_Msk (0x10000UL) /*!< PREEN (Bitfield-Mask: 0x01) */ +/* ======================================================= LIOCFGCS ======================================================== */ + #define R_XSPI0_LIOCFGCS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_XSPI0_LIOCFGCS_PRTMD_Msk (0x3ffUL) /*!< PRTMD (Bitfield-Mask: 0x3ff) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Pos (10UL) /*!< LATEMD (Bit 10) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Msk (0x400UL) /*!< LATEMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Pos (11UL) /*!< WRMSKMD (Bit 11) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Msk (0x800UL) /*!< WRMSKMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Pos (16UL) /*!< CSMIN (Bit 16) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Msk (0xf0000UL) /*!< CSMIN (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Pos (20UL) /*!< CSASTEX (Bit 20) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Msk (0x100000UL) /*!< CSASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Pos (21UL) /*!< CSNEGEX (Bit 21) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Msk (0x200000UL) /*!< CSNEGEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Pos (22UL) /*!< SDRDRV (Bit 22) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Msk (0x400000UL) /*!< SDRDRV (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Pos (23UL) /*!< SDRSMPMD (Bit 23) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Msk (0x800000UL) /*!< SDRSMPMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Pos (24UL) /*!< SDRSMPSFT (Bit 24) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Msk (0xf000000UL) /*!< SDRSMPSFT (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Pos (28UL) /*!< DDRSMPEX (Bit 28) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Msk (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f) */ +/* ======================================================== BMCTL0 ========================================================= */ + #define R_XSPI0_BMCTL0_CS0ACC_Pos (0UL) /*!< CS0ACC (Bit 0) */ + #define R_XSPI0_BMCTL0_CS0ACC_Msk (0x3UL) /*!< CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CS1ACC_Pos (2UL) /*!< CS1ACC (Bit 2) */ + #define R_XSPI0_BMCTL0_CS1ACC_Msk (0xcUL) /*!< CS1ACC (Bitfield-Mask: 0x03) */ +/* ======================================================== BMCTL1 ========================================================= */ + #define R_XSPI0_BMCTL1_MWRPUSH_Pos (8UL) /*!< MWRPUSH (Bit 8) */ + #define R_XSPI0_BMCTL1_MWRPUSH_Msk (0x100UL) /*!< MWRPUSH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCTL1_PBUFCLR_Pos (10UL) /*!< PBUFCLR (Bit 10) */ + #define R_XSPI0_BMCTL1_PBUFCLR_Msk (0x400UL) /*!< PBUFCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= CMCTL ========================================================= */ + #define R_XSPI0_CMCTL_XIPENCODE_Pos (0UL) /*!< XIPENCODE (Bit 0) */ + #define R_XSPI0_CMCTL_XIPENCODE_Msk (0xffUL) /*!< XIPENCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTL_XIPEXCODE_Pos (8UL) /*!< XIPEXCODE (Bit 8) */ + #define R_XSPI0_CMCTL_XIPEXCODE_Msk (0xff00UL) /*!< XIPEXCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTL_XIPEN_Pos (16UL) /*!< XIPEN (Bit 16) */ + #define R_XSPI0_CMCTL_XIPEN_Msk (0x10000UL) /*!< XIPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CSSCTL ========================================================= */ + #define R_XSPI0_CSSCTL_CS0SIZE_Pos (0UL) /*!< CS0SIZE (Bit 0) */ + #define R_XSPI0_CSSCTL_CS0SIZE_Msk (0x3fUL) /*!< CS0SIZE (Bitfield-Mask: 0x3f) */ + #define R_XSPI0_CSSCTL_CS1SIZE_Pos (8UL) /*!< CS1SIZE (Bit 8) */ + #define R_XSPI0_CSSCTL_CS1SIZE_Msk (0x3f00UL) /*!< CS1SIZE (Bitfield-Mask: 0x3f) */ +/* ======================================================== CDCTL0 ========================================================= */ + #define R_XSPI0_CDCTL0_TRREQ_Pos (0UL) /*!< TRREQ (Bit 0) */ + #define R_XSPI0_CDCTL0_TRREQ_Msk (0x1UL) /*!< TRREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_PERMD_Pos (1UL) /*!< PERMD (Bit 1) */ + #define R_XSPI0_CDCTL0_PERMD_Msk (0x2UL) /*!< PERMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_CDCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_TRNUM_Pos (4UL) /*!< TRNUM (Bit 4) */ + #define R_XSPI0_CDCTL0_TRNUM_Msk (0x30UL) /*!< TRNUM (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CDCTL0_PERITV_Pos (16UL) /*!< PERITV (Bit 16) */ + #define R_XSPI0_CDCTL0_PERITV_Msk (0x1f0000UL) /*!< PERITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CDCTL0_PERREP_Pos (24UL) /*!< PERREP (Bit 24) */ + #define R_XSPI0_CDCTL0_PERREP_Msk (0xf000000UL) /*!< PERREP (Bitfield-Mask: 0x0f) */ +/* ======================================================== CDCTL1 ========================================================= */ + #define R_XSPI0_CDCTL1_PEREXP_Pos (0UL) /*!< PEREXP (Bit 0) */ + #define R_XSPI0_CDCTL1_PEREXP_Msk (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDCTL2 ========================================================= */ + #define R_XSPI0_CDCTL2_PERMSK_Pos (0UL) /*!< PERMSK (Bit 0) */ + #define R_XSPI0_CDCTL2_PERMSK_Msk (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LPCTL0 ========================================================= */ + #define R_XSPI0_LPCTL0_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL0_PATREQ_Msk (0x1UL) /*!< PATREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XDPIN_Pos (4UL) /*!< XDPIN (Bit 4) */ + #define R_XSPI0_LPCTL0_XDPIN_Msk (0x30UL) /*!< XDPIN (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL0_XD1LEN_Pos (16UL) /*!< XD1LEN (Bit 16) */ + #define R_XSPI0_LPCTL0_XD1LEN_Msk (0x1f0000UL) /*!< XD1LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD1VAL_Pos (23UL) /*!< XD1VAL (Bit 23) */ + #define R_XSPI0_LPCTL0_XD1VAL_Msk (0x800000UL) /*!< XD1VAL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XD2LEN_Pos (24UL) /*!< XD2LEN (Bit 24) */ + #define R_XSPI0_LPCTL0_XD2LEN_Msk (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD2VAL_Pos (31UL) /*!< XD2VAL (Bit 31) */ + #define R_XSPI0_LPCTL0_XD2VAL_Msk (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTL1 ========================================================= */ + #define R_XSPI0_LPCTL1_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL1_PATREQ_Msk (0x3UL) /*!< PATREQ (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL1_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL1_RSTREP_Pos (4UL) /*!< RSTREP (Bit 4) */ + #define R_XSPI0_LPCTL1_RSTREP_Msk (0x30UL) /*!< RSTREP (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_RSTWID_Pos (8UL) /*!< RSTWID (Bit 8) */ + #define R_XSPI0_LPCTL1_RSTWID_Msk (0x700UL) /*!< RSTWID (Bitfield-Mask: 0x07) */ + #define R_XSPI0_LPCTL1_RSTSU_Pos (12UL) /*!< RSTSU (Bit 12) */ + #define R_XSPI0_LPCTL1_RSTSU_Msk (0x7000UL) /*!< RSTSU (Bitfield-Mask: 0x07) */ +/* ======================================================== LIOCTL ========================================================= */ + #define R_XSPI0_LIOCTL_WPCS0_Pos (0UL) /*!< WPCS0 (Bit 0) */ + #define R_XSPI0_LIOCTL_WPCS0_Msk (0x1UL) /*!< WPCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCTL_WPCS1_Pos (1UL) /*!< WPCS1 (Bit 1) */ + #define R_XSPI0_LIOCTL_WPCS1_Msk (0x2UL) /*!< WPCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCTL_RSTCS0_Pos (16UL) /*!< RSTCS0 (Bit 16) */ + #define R_XSPI0_LIOCTL_RSTCS0_Msk (0x10000UL) /*!< RSTCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCTL_RSTCS1_Pos (17UL) /*!< RSTCS1 (Bit 17) */ + #define R_XSPI0_LIOCTL_RSTCS1_Msk (0x20000UL) /*!< RSTCS1 (Bitfield-Mask: 0x01) */ +/* ======================================================== VERSTT ========================================================= */ + #define R_XSPI0_VERSTT_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_XSPI0_VERSTT_VER_Msk (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== COMSTT ========================================================= */ + #define R_XSPI0_COMSTT_MEMACC_Pos (0UL) /*!< MEMACC (Bit 0) */ + #define R_XSPI0_COMSTT_MEMACC_Msk (0x1UL) /*!< MEMACC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_PBUFNE_Pos (4UL) /*!< PBUFNE (Bit 4) */ + #define R_XSPI0_COMSTT_PBUFNE_Msk (0x10UL) /*!< PBUFNE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_WRBUFNE_Pos (6UL) /*!< WRBUFNE (Bit 6) */ + #define R_XSPI0_COMSTT_WRBUFNE_Msk (0x40UL) /*!< WRBUFNE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_ECSCS0_Pos (16UL) /*!< ECSCS0 (Bit 16) */ + #define R_XSPI0_COMSTT_ECSCS0_Msk (0x10000UL) /*!< ECSCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_INTCS0_Pos (17UL) /*!< INTCS0 (Bit 17) */ + #define R_XSPI0_COMSTT_INTCS0_Msk (0x20000UL) /*!< INTCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_RSTOCS0_Pos (18UL) /*!< RSTOCS0 (Bit 18) */ + #define R_XSPI0_COMSTT_RSTOCS0_Msk (0x40000UL) /*!< RSTOCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_ECSCS1_Pos (20UL) /*!< ECSCS1 (Bit 20) */ + #define R_XSPI0_COMSTT_ECSCS1_Msk (0x100000UL) /*!< ECSCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_INTCS1_Pos (21UL) /*!< INTCS1 (Bit 21) */ + #define R_XSPI0_COMSTT_INTCS1_Msk (0x200000UL) /*!< INTCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_RSTOCS1_Pos (22UL) /*!< RSTOCS1 (Bit 22) */ + #define R_XSPI0_COMSTT_RSTOCS1_Msk (0x400000UL) /*!< RSTOCS1 (Bitfield-Mask: 0x01) */ +/* ======================================================== CASTTCS ======================================================== */ + #define R_XSPI0_CASTTCS_CASUC_Pos (0UL) /*!< CASUC (Bit 0) */ + #define R_XSPI0_CASTTCS_CASUC_Msk (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTS ========================================================== */ + #define R_XSPI0_INTS_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ + #define R_XSPI0_INTS_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PATCMP_Pos (1UL) /*!< PATCMP (Bit 1) */ + #define R_XSPI0_INTS_PATCMP_Msk (0x2UL) /*!< PATCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INICMP_Pos (2UL) /*!< INICMP (Bit 2) */ + #define R_XSPI0_INTS_INICMP_Msk (0x4UL) /*!< INICMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PERTO_Pos (3UL) /*!< PERTO (Bit 3) */ + #define R_XSPI0_INTS_PERTO_Msk (0x8UL) /*!< PERTO (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_DSTOCS0_Pos (4UL) /*!< DSTOCS0 (Bit 4) */ + #define R_XSPI0_INTS_DSTOCS0_Msk (0x10UL) /*!< DSTOCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_DSTOCS1_Pos (5UL) /*!< DSTOCS1 (Bit 5) */ + #define R_XSPI0_INTS_DSTOCS1_Msk (0x20UL) /*!< DSTOCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_ECSCS0_Pos (8UL) /*!< ECSCS0 (Bit 8) */ + #define R_XSPI0_INTS_ECSCS0_Msk (0x100UL) /*!< ECSCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_ECSCS1_Pos (9UL) /*!< ECSCS1 (Bit 9) */ + #define R_XSPI0_INTS_ECSCS1_Msk (0x200UL) /*!< ECSCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INTCS0_Pos (12UL) /*!< INTCS0 (Bit 12) */ + #define R_XSPI0_INTS_INTCS0_Msk (0x1000UL) /*!< INTCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INTCS1_Pos (13UL) /*!< INTCS1 (Bit 13) */ + #define R_XSPI0_INTS_INTCS1_Msk (0x2000UL) /*!< INTCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGOF_Pos (16UL) /*!< BRGOF (Bit 16) */ + #define R_XSPI0_INTS_BRGOF_Msk (0x10000UL) /*!< BRGOF (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGUF_Pos (18UL) /*!< BRGUF (Bit 18) */ + #define R_XSPI0_INTS_BRGUF_Msk (0x40000UL) /*!< BRGUF (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BUSERR_Pos (20UL) /*!< BUSERR (Bit 20) */ + #define R_XSPI0_INTS_BUSERR_Msk (0x100000UL) /*!< BUSERR (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CAFAILCS0_Pos (28UL) /*!< CAFAILCS0 (Bit 28) */ + #define R_XSPI0_INTS_CAFAILCS0_Msk (0x10000000UL) /*!< CAFAILCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CAFAILCS1_Pos (29UL) /*!< CAFAILCS1 (Bit 29) */ + #define R_XSPI0_INTS_CAFAILCS1_Msk (0x20000000UL) /*!< CAFAILCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CASUCCS0_Pos (30UL) /*!< CASUCCS0 (Bit 30) */ + #define R_XSPI0_INTS_CASUCCS0_Msk (0x40000000UL) /*!< CASUCCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CASUCCS1_Pos (31UL) /*!< CASUCCS1 (Bit 31) */ + #define R_XSPI0_INTS_CASUCCS1_Msk (0x80000000UL) /*!< CASUCCS1 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTC ========================================================== */ + #define R_XSPI0_INTC_CMDCMPC_Pos (0UL) /*!< CMDCMPC (Bit 0) */ + #define R_XSPI0_INTC_CMDCMPC_Msk (0x1UL) /*!< CMDCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PATCMPC_Pos (1UL) /*!< PATCMPC (Bit 1) */ + #define R_XSPI0_INTC_PATCMPC_Msk (0x2UL) /*!< PATCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INICMPC_Pos (2UL) /*!< INICMPC (Bit 2) */ + #define R_XSPI0_INTC_INICMPC_Msk (0x4UL) /*!< INICMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PERTOC_Pos (3UL) /*!< PERTOC (Bit 3) */ + #define R_XSPI0_INTC_PERTOC_Msk (0x8UL) /*!< PERTOC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_DSTOCS0C_Pos (4UL) /*!< DSTOCS0C (Bit 4) */ + #define R_XSPI0_INTC_DSTOCS0C_Msk (0x10UL) /*!< DSTOCS0C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_DSTOCS1C_Pos (5UL) /*!< DSTOCS1C (Bit 5) */ + #define R_XSPI0_INTC_DSTOCS1C_Msk (0x20UL) /*!< DSTOCS1C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_ECSCS0C_Pos (8UL) /*!< ECSCS0C (Bit 8) */ + #define R_XSPI0_INTC_ECSCS0C_Msk (0x100UL) /*!< ECSCS0C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_ECSCS1C_Pos (9UL) /*!< ECSCS1C (Bit 9) */ + #define R_XSPI0_INTC_ECSCS1C_Msk (0x200UL) /*!< ECSCS1C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INTCS0C_Pos (12UL) /*!< INTCS0C (Bit 12) */ + #define R_XSPI0_INTC_INTCS0C_Msk (0x1000UL) /*!< INTCS0C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INTCS1C_Pos (13UL) /*!< INTCS1C (Bit 13) */ + #define R_XSPI0_INTC_INTCS1C_Msk (0x2000UL) /*!< INTCS1C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGOFC_Pos (16UL) /*!< BRGOFC (Bit 16) */ + #define R_XSPI0_INTC_BRGOFC_Msk (0x10000UL) /*!< BRGOFC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGUFC_Pos (18UL) /*!< BRGUFC (Bit 18) */ + #define R_XSPI0_INTC_BRGUFC_Msk (0x40000UL) /*!< BRGUFC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BUSERRC_Pos (20UL) /*!< BUSERRC (Bit 20) */ + #define R_XSPI0_INTC_BUSERRC_Msk (0x100000UL) /*!< BUSERRC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CAFAILCS0C_Pos (28UL) /*!< CAFAILCS0C (Bit 28) */ + #define R_XSPI0_INTC_CAFAILCS0C_Msk (0x10000000UL) /*!< CAFAILCS0C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CAFAILCS1C_Pos (29UL) /*!< CAFAILCS1C (Bit 29) */ + #define R_XSPI0_INTC_CAFAILCS1C_Msk (0x20000000UL) /*!< CAFAILCS1C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CASUCCS0C_Pos (30UL) /*!< CASUCCS0C (Bit 30) */ + #define R_XSPI0_INTC_CASUCCS0C_Msk (0x40000000UL) /*!< CASUCCS0C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CASUCCS1C_Pos (31UL) /*!< CASUCCS1C (Bit 31) */ + #define R_XSPI0_INTC_CASUCCS1C_Msk (0x80000000UL) /*!< CASUCCS1C (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ + #define R_XSPI0_INTE_CMDCMPE_Pos (0UL) /*!< CMDCMPE (Bit 0) */ + #define R_XSPI0_INTE_CMDCMPE_Msk (0x1UL) /*!< CMDCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PATCMPE_Pos (1UL) /*!< PATCMPE (Bit 1) */ + #define R_XSPI0_INTE_PATCMPE_Msk (0x2UL) /*!< PATCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INICMPE_Pos (2UL) /*!< INICMPE (Bit 2) */ + #define R_XSPI0_INTE_INICMPE_Msk (0x4UL) /*!< INICMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PERTOE_Pos (3UL) /*!< PERTOE (Bit 3) */ + #define R_XSPI0_INTE_PERTOE_Msk (0x8UL) /*!< PERTOE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_DSTOCS0E_Pos (4UL) /*!< DSTOCS0E (Bit 4) */ + #define R_XSPI0_INTE_DSTOCS0E_Msk (0x10UL) /*!< DSTOCS0E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_DSTOCS1E_Pos (5UL) /*!< DSTOCS1E (Bit 5) */ + #define R_XSPI0_INTE_DSTOCS1E_Msk (0x20UL) /*!< DSTOCS1E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_ECSCS0E_Pos (8UL) /*!< ECSCS0E (Bit 8) */ + #define R_XSPI0_INTE_ECSCS0E_Msk (0x100UL) /*!< ECSCS0E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_ECSCS1E_Pos (9UL) /*!< ECSCS1E (Bit 9) */ + #define R_XSPI0_INTE_ECSCS1E_Msk (0x200UL) /*!< ECSCS1E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INTCS0E_Pos (12UL) /*!< INTCS0E (Bit 12) */ + #define R_XSPI0_INTE_INTCS0E_Msk (0x1000UL) /*!< INTCS0E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INTCS1E_Pos (13UL) /*!< INTCS1E (Bit 13) */ + #define R_XSPI0_INTE_INTCS1E_Msk (0x2000UL) /*!< INTCS1E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGOFE_Pos (16UL) /*!< BRGOFE (Bit 16) */ + #define R_XSPI0_INTE_BRGOFE_Msk (0x10000UL) /*!< BRGOFE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGUFE_Pos (18UL) /*!< BRGUFE (Bit 18) */ + #define R_XSPI0_INTE_BRGUFE_Msk (0x40000UL) /*!< BRGUFE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BUSERRE_Pos (20UL) /*!< BUSERRE (Bit 20) */ + #define R_XSPI0_INTE_BUSERRE_Msk (0x100000UL) /*!< BUSERRE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CAFAILCS0E_Pos (28UL) /*!< CAFAILCS0E (Bit 28) */ + #define R_XSPI0_INTE_CAFAILCS0E_Msk (0x10000000UL) /*!< CAFAILCS0E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CAFAILCS1E_Pos (29UL) /*!< CAFAILCS1E (Bit 29) */ + #define R_XSPI0_INTE_CAFAILCS1E_Msk (0x20000000UL) /*!< CAFAILCS1E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CASUCCS0E_Pos (30UL) /*!< CASUCCS0E (Bit 30) */ + #define R_XSPI0_INTE_CASUCCS0E_Msk (0x40000000UL) /*!< CASUCCS0E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CASUCCS1E_Pos (31UL) /*!< CASUCCS1E (Bit 31) */ + #define R_XSPI0_INTE_CASUCCS1E_Msk (0x80000000UL) /*!< CASUCCS1E (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MBXSEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SEM ========================================================== */ + #define R_MBXSEM_SEM_SEM_Pos (0UL) /*!< SEM (Bit 0) */ + #define R_MBXSEM_SEM_SEM_Msk (0x1UL) /*!< SEM (Bitfield-Mask: 0x01) */ +/* ======================================================== SEMRCEN ======================================================== */ + #define R_MBXSEM_SEMRCEN_SEMRCEN0_Pos (0UL) /*!< SEMRCEN0 (Bit 0) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN0_Msk (0x1UL) /*!< SEMRCEN0 (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN1_Pos (1UL) /*!< SEMRCEN1 (Bit 1) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN1_Msk (0x2UL) /*!< SEMRCEN1 (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN2_Pos (2UL) /*!< SEMRCEN2 (Bit 2) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN2_Msk (0x4UL) /*!< SEMRCEN2 (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN3_Pos (3UL) /*!< SEMRCEN3 (Bit 3) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN3_Msk (0x8UL) /*!< SEMRCEN3 (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN4_Pos (4UL) /*!< SEMRCEN4 (Bit 4) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN4_Msk (0x10UL) /*!< SEMRCEN4 (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN5_Pos (5UL) /*!< SEMRCEN5 (Bit 5) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN5_Msk (0x20UL) /*!< SEMRCEN5 (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN6_Pos (6UL) /*!< SEMRCEN6 (Bit 6) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN6_Msk (0x40UL) /*!< SEMRCEN6 (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN7_Pos (7UL) /*!< SEMRCEN7 (Bit 7) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN7_Msk (0x80UL) /*!< SEMRCEN7 (Bitfield-Mask: 0x01) */ +/* ======================================================== MBXH2C ========================================================= */ + #define R_MBXSEM_MBXH2C_MBX_Pos (0UL) /*!< MBX (Bit 0) */ + #define R_MBXSEM_MBXH2C_MBX_Msk (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== MBXISETH2C ======================================================= */ + #define R_MBXSEM_MBXISETH2C_MBX_INT0S_Pos (0UL) /*!< MBX_INT0S (Bit 0) */ + #define R_MBXSEM_MBXISETH2C_MBX_INT0S_Msk (0x1UL) /*!< MBX_INT0S (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXISETH2C_MBX_INT1S_Pos (1UL) /*!< MBX_INT1S (Bit 1) */ + #define R_MBXSEM_MBXISETH2C_MBX_INT1S_Msk (0x2UL) /*!< MBX_INT1S (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXISETH2C_MBX_INT2S_Pos (2UL) /*!< MBX_INT2S (Bit 2) */ + #define R_MBXSEM_MBXISETH2C_MBX_INT2S_Msk (0x4UL) /*!< MBX_INT2S (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXISETH2C_MBX_INT3S_Pos (3UL) /*!< MBX_INT3S (Bit 3) */ + #define R_MBXSEM_MBXISETH2C_MBX_INT3S_Msk (0x8UL) /*!< MBX_INT3S (Bitfield-Mask: 0x01) */ +/* ====================================================== MBXICLRH2C ======================================================= */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT0C_Pos (0UL) /*!< MBX_INT0C (Bit 0) */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT0C_Msk (0x1UL) /*!< MBX_INT0C (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT1C_Pos (1UL) /*!< MBX_INT1C (Bit 1) */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT1C_Msk (0x2UL) /*!< MBX_INT1C (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT2C_Pos (2UL) /*!< MBX_INT2C (Bit 2) */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT2C_Msk (0x4UL) /*!< MBX_INT2C (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT3C_Pos (3UL) /*!< MBX_INT3C (Bit 3) */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT3C_Msk (0x8UL) /*!< MBX_INT3C (Bitfield-Mask: 0x01) */ +/* ======================================================== MBXC2H ========================================================= */ + #define R_MBXSEM_MBXC2H_MBX_Pos (0UL) /*!< MBX (Bit 0) */ + #define R_MBXSEM_MBXC2H_MBX_Msk (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== MBXISETC2H ======================================================= */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT0S_Pos (0UL) /*!< MBX_HINT0S (Bit 0) */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT0S_Msk (0x1UL) /*!< MBX_HINT0S (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT1S_Pos (1UL) /*!< MBX_HINT1S (Bit 1) */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT1S_Msk (0x2UL) /*!< MBX_HINT1S (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT2S_Pos (2UL) /*!< MBX_HINT2S (Bit 2) */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT2S_Msk (0x4UL) /*!< MBX_HINT2S (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT3S_Pos (3UL) /*!< MBX_HINT3S (Bit 3) */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT3S_Msk (0x8UL) /*!< MBX_HINT3S (Bitfield-Mask: 0x01) */ +/* ====================================================== MBXICLRC2H ======================================================= */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT0C_Pos (0UL) /*!< MBX_HINT0C (Bit 0) */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT0C_Msk (0x1UL) /*!< MBX_HINT0C (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT1C_Pos (1UL) /*!< MBX_HINT1C (Bit 1) */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT1C_Msk (0x2UL) /*!< MBX_HINT1C (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT2C_Pos (2UL) /*!< MBX_HINT2C (Bit 2) */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT2C_Msk (0x4UL) /*!< MBX_HINT2C (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT3C_Pos (3UL) /*!< MBX_HINT3C (Bit 3) */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT3C_Msk (0x8UL) /*!< MBX_HINT3C (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SHOSTIF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTRLR0 ========================================================= */ + #define R_SHOSTIF_CTRLR0_SCPH_Pos (8UL) /*!< SCPH (Bit 8) */ + #define R_SHOSTIF_CTRLR0_SCPH_Msk (0x100UL) /*!< SCPH (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_CTRLR0_SCPOL_Pos (9UL) /*!< SCPOL (Bit 9) */ + #define R_SHOSTIF_CTRLR0_SCPOL_Msk (0x200UL) /*!< SCPOL (Bitfield-Mask: 0x01) */ +/* ========================================================== ENR ========================================================== */ + #define R_SHOSTIF_ENR_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_SHOSTIF_ENR_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================== RXFBTR ========================================================= */ + #define R_SHOSTIF_RXFBTR_RXFBTL_Pos (0UL) /*!< RXFBTL (Bit 0) */ + #define R_SHOSTIF_RXFBTR_RXFBTL_Msk (0x3fUL) /*!< RXFBTL (Bitfield-Mask: 0x3f) */ +/* ======================================================== TXFTLR ========================================================= */ + #define R_SHOSTIF_TXFTLR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_SHOSTIF_TXFTLR_TFT_Msk (0x3fUL) /*!< TFT (Bitfield-Mask: 0x3f) */ +/* ======================================================== RXFTLR ========================================================= */ + #define R_SHOSTIF_RXFTLR_RFT_Pos (0UL) /*!< RFT (Bit 0) */ + #define R_SHOSTIF_RXFTLR_RFT_Msk (0x3fUL) /*!< RFT (Bitfield-Mask: 0x3f) */ +/* ========================================================== SR =========================================================== */ + #define R_SHOSTIF_SR_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ + #define R_SHOSTIF_SR_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ========================================================== IMR ========================================================== */ + #define R_SHOSTIF_IMR_TXEIM_Pos (0UL) /*!< TXEIM (Bit 0) */ + #define R_SHOSTIF_IMR_TXEIM_Msk (0x1UL) /*!< TXEIM (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_IMR_RXOIM_Pos (3UL) /*!< RXOIM (Bit 3) */ + #define R_SHOSTIF_IMR_RXOIM_Msk (0x8UL) /*!< RXOIM (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_IMR_RXFIM_Pos (4UL) /*!< RXFIM (Bit 4) */ + #define R_SHOSTIF_IMR_RXFIM_Msk (0x10UL) /*!< RXFIM (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_IMR_TXUIM_Pos (7UL) /*!< TXUIM (Bit 7) */ + #define R_SHOSTIF_IMR_TXUIM_Msk (0x80UL) /*!< TXUIM (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_IMR_AHBEM_Pos (8UL) /*!< AHBEM (Bit 8) */ + #define R_SHOSTIF_IMR_AHBEM_Msk (0x100UL) /*!< AHBEM (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_IMR_SPIMEM_Pos (9UL) /*!< SPIMEM (Bit 9) */ + #define R_SHOSTIF_IMR_SPIMEM_Msk (0x200UL) /*!< SPIMEM (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ + #define R_SHOSTIF_ISR_TXEIS_Pos (0UL) /*!< TXEIS (Bit 0) */ + #define R_SHOSTIF_ISR_TXEIS_Msk (0x1UL) /*!< TXEIS (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_ISR_RXOIS_Pos (3UL) /*!< RXOIS (Bit 3) */ + #define R_SHOSTIF_ISR_RXOIS_Msk (0x8UL) /*!< RXOIS (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_ISR_RXFIS_Pos (4UL) /*!< RXFIS (Bit 4) */ + #define R_SHOSTIF_ISR_RXFIS_Msk (0x10UL) /*!< RXFIS (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_ISR_TXUIS_Pos (7UL) /*!< TXUIS (Bit 7) */ + #define R_SHOSTIF_ISR_TXUIS_Msk (0x80UL) /*!< TXUIS (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_ISR_AHBES_Pos (8UL) /*!< AHBES (Bit 8) */ + #define R_SHOSTIF_ISR_AHBES_Msk (0x100UL) /*!< AHBES (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_ISR_SPIMES_Pos (9UL) /*!< SPIMES (Bit 9) */ + #define R_SHOSTIF_ISR_SPIMES_Msk (0x200UL) /*!< SPIMES (Bitfield-Mask: 0x01) */ +/* ========================================================= RISR ========================================================== */ + #define R_SHOSTIF_RISR_TXEIR_Pos (0UL) /*!< TXEIR (Bit 0) */ + #define R_SHOSTIF_RISR_TXEIR_Msk (0x1UL) /*!< TXEIR (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_RISR_RXOIR_Pos (3UL) /*!< RXOIR (Bit 3) */ + #define R_SHOSTIF_RISR_RXOIR_Msk (0x8UL) /*!< RXOIR (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_RISR_RXFIR_Pos (4UL) /*!< RXFIR (Bit 4) */ + #define R_SHOSTIF_RISR_RXFIR_Msk (0x10UL) /*!< RXFIR (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_RISR_TXUIR_Pos (7UL) /*!< TXUIR (Bit 7) */ + #define R_SHOSTIF_RISR_TXUIR_Msk (0x80UL) /*!< TXUIR (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_RISR_AHBER_Pos (8UL) /*!< AHBER (Bit 8) */ + #define R_SHOSTIF_RISR_AHBER_Msk (0x100UL) /*!< AHBER (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_RISR_SPIMER_Pos (9UL) /*!< SPIMER (Bit 9) */ + #define R_SHOSTIF_RISR_SPIMER_Msk (0x200UL) /*!< SPIMER (Bitfield-Mask: 0x01) */ +/* ======================================================== TXUICR ========================================================= */ + #define R_SHOSTIF_TXUICR_TXUICR_Pos (0UL) /*!< TXUICR (Bit 0) */ + #define R_SHOSTIF_TXUICR_TXUICR_Msk (0x1UL) /*!< TXUICR (Bitfield-Mask: 0x01) */ +/* ======================================================== RXOICR ========================================================= */ + #define R_SHOSTIF_RXOICR_RXOICR_Pos (0UL) /*!< RXOICR (Bit 0) */ + #define R_SHOSTIF_RXOICR_RXOICR_Msk (0x1UL) /*!< RXOICR (Bitfield-Mask: 0x01) */ +/* ======================================================== SPIMECR ======================================================== */ + #define R_SHOSTIF_SPIMECR_SPIMECR_Pos (0UL) /*!< SPIMECR (Bit 0) */ + #define R_SHOSTIF_SPIMECR_SPIMECR_Msk (0x1UL) /*!< SPIMECR (Bitfield-Mask: 0x01) */ +/* ======================================================== AHBECR ========================================================= */ + #define R_SHOSTIF_AHBECR_AHBECR_Pos (0UL) /*!< AHBECR (Bit 0) */ + #define R_SHOSTIF_AHBECR_AHBECR_Msk (0x1UL) /*!< AHBECR (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SHOSTIF_ICR_ICR_Pos (0UL) /*!< ICR (Bit 0) */ + #define R_SHOSTIF_ICR_ICR_Msk (0x1UL) /*!< ICR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSC_NS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SCKCR ========================================================= */ + #define R_SYSC_NS_SCKCR_FSELXSPI0_Pos (0UL) /*!< FSELXSPI0 (Bit 0) */ + #define R_SYSC_NS_SCKCR_FSELXSPI0_Msk (0x7UL) /*!< FSELXSPI0 (Bitfield-Mask: 0x07) */ + #define R_SYSC_NS_SCKCR_DIVSELXSPI0_Pos (6UL) /*!< DIVSELXSPI0 (Bit 6) */ + #define R_SYSC_NS_SCKCR_DIVSELXSPI0_Msk (0x40UL) /*!< DIVSELXSPI0 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_FSELXSPI1_Pos (8UL) /*!< FSELXSPI1 (Bit 8) */ + #define R_SYSC_NS_SCKCR_FSELXSPI1_Msk (0x700UL) /*!< FSELXSPI1 (Bitfield-Mask: 0x07) */ + #define R_SYSC_NS_SCKCR_DIVSELXSPI1_Pos (14UL) /*!< DIVSELXSPI1 (Bit 14) */ + #define R_SYSC_NS_SCKCR_DIVSELXSPI1_Msk (0x4000UL) /*!< DIVSELXSPI1 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_CKIO_Pos (16UL) /*!< CKIO (Bit 16) */ + #define R_SYSC_NS_SCKCR_CKIO_Msk (0x70000UL) /*!< CKIO (Bitfield-Mask: 0x07) */ + #define R_SYSC_NS_SCKCR_FSELCANFD_Pos (20UL) /*!< FSELCANFD (Bit 20) */ + #define R_SYSC_NS_SCKCR_FSELCANFD_Msk (0x100000UL) /*!< FSELCANFD (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_PHYSEL_Pos (21UL) /*!< PHYSEL (Bit 21) */ + #define R_SYSC_NS_SCKCR_PHYSEL_Msk (0x200000UL) /*!< PHYSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_CLMASEL_Pos (22UL) /*!< CLMASEL (Bit 22) */ + #define R_SYSC_NS_SCKCR_CLMASEL_Msk (0x400000UL) /*!< CLMASEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SPI0ASYNCSEL_Pos (24UL) /*!< SPI0ASYNCSEL (Bit 24) */ + #define R_SYSC_NS_SCKCR_SPI0ASYNCSEL_Msk (0x1000000UL) /*!< SPI0ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SPI1ASYNCSEL_Pos (25UL) /*!< SPI1ASYNCSEL (Bit 25) */ + #define R_SYSC_NS_SCKCR_SPI1ASYNCSEL_Msk (0x2000000UL) /*!< SPI1ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SPI2ASYNCSEL_Pos (26UL) /*!< SPI2ASYNCSEL (Bit 26) */ + #define R_SYSC_NS_SCKCR_SPI2ASYNCSEL_Msk (0x4000000UL) /*!< SPI2ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SCI0ASYNCSEL_Pos (27UL) /*!< SCI0ASYNCSEL (Bit 27) */ + #define R_SYSC_NS_SCKCR_SCI0ASYNCSEL_Msk (0x8000000UL) /*!< SCI0ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SCI1ASYNCSEL_Pos (28UL) /*!< SCI1ASYNCSEL (Bit 28) */ + #define R_SYSC_NS_SCKCR_SCI1ASYNCSEL_Msk (0x10000000UL) /*!< SCI1ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SCI2ASYNCSEL_Pos (29UL) /*!< SCI2ASYNCSEL (Bit 29) */ + #define R_SYSC_NS_SCKCR_SCI2ASYNCSEL_Msk (0x20000000UL) /*!< SCI2ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SCI3ASYNCSEL_Pos (30UL) /*!< SCI3ASYNCSEL (Bit 30) */ + #define R_SYSC_NS_SCKCR_SCI3ASYNCSEL_Msk (0x40000000UL) /*!< SCI3ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SCI4ASYNCSEL_Pos (31UL) /*!< SCI4ASYNCSEL (Bit 31) */ + #define R_SYSC_NS_SCKCR_SCI4ASYNCSEL_Msk (0x80000000UL) /*!< SCI4ASYNCSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSC_NS_RSTSR0_TRF_Pos (1UL) /*!< TRF (Bit 1) */ + #define R_SYSC_NS_RSTSR0_TRF_Msk (0x2UL) /*!< TRF (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_RSTSR0_ERRF_Pos (2UL) /*!< ERRF (Bit 2) */ + #define R_SYSC_NS_RSTSR0_ERRF_Msk (0x4UL) /*!< ERRF (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_RSTSR0_SWRSF_Pos (3UL) /*!< SWRSF (Bit 3) */ + #define R_SYSC_NS_RSTSR0_SWRSF_Msk (0x8UL) /*!< SWRSF (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_RSTSR0_SWR0F_Pos (4UL) /*!< SWR0F (Bit 4) */ + #define R_SYSC_NS_RSTSR0_SWR0F_Msk (0x10UL) /*!< SWR0F (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCTLA ========================================================= */ + #define R_SYSC_NS_MRCTLA_MRCTLA04_Pos (4UL) /*!< MRCTLA04 (Bit 4) */ + #define R_SYSC_NS_MRCTLA_MRCTLA04_Msk (0x10UL) /*!< MRCTLA04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLA_MRCTLA05_Pos (5UL) /*!< MRCTLA05 (Bit 5) */ + #define R_SYSC_NS_MRCTLA_MRCTLA05_Msk (0x20UL) /*!< MRCTLA05 (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCTLE ========================================================= */ + #define R_SYSC_NS_MRCTLE_MRCTLE00_Pos (0UL) /*!< MRCTLE00 (Bit 0) */ + #define R_SYSC_NS_MRCTLE_MRCTLE00_Msk (0x1UL) /*!< MRCTLE00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE01_Pos (1UL) /*!< MRCTLE01 (Bit 1) */ + #define R_SYSC_NS_MRCTLE_MRCTLE01_Msk (0x2UL) /*!< MRCTLE01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE03_Pos (3UL) /*!< MRCTLE03 (Bit 3) */ + #define R_SYSC_NS_MRCTLE_MRCTLE03_Msk (0x8UL) /*!< MRCTLE03 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE04_Pos (4UL) /*!< MRCTLE04 (Bit 4) */ + #define R_SYSC_NS_MRCTLE_MRCTLE04_Msk (0x10UL) /*!< MRCTLE04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE05_Pos (5UL) /*!< MRCTLE05 (Bit 5) */ + #define R_SYSC_NS_MRCTLE_MRCTLE05_Msk (0x20UL) /*!< MRCTLE05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE06_Pos (6UL) /*!< MRCTLE06 (Bit 6) */ + #define R_SYSC_NS_MRCTLE_MRCTLE06_Msk (0x40UL) /*!< MRCTLE06 (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCTLJ ========================================================= */ + #define R_SYSC_NS_MRCTLJ_MRCTLJ00_Pos (0UL) /*!< MRCTLJ00 (Bit 0) */ + #define R_SYSC_NS_MRCTLJ_MRCTLJ00_Msk (0x1UL) /*!< MRCTLJ00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLJ_MRCTLJ01_Pos (1UL) /*!< MRCTLJ01 (Bit 1) */ + #define R_SYSC_NS_MRCTLJ_MRCTLJ01_Msk (0x2UL) /*!< MRCTLJ01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLJ_MRCTLJ02_Pos (2UL) /*!< MRCTLJ02 (Bit 2) */ + #define R_SYSC_NS_MRCTLJ_MRCTLJ02_Msk (0x4UL) /*!< MRCTLJ02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLJ_MRCTLJ03_Pos (3UL) /*!< MRCTLJ03 (Bit 3) */ + #define R_SYSC_NS_MRCTLJ_MRCTLJ03_Msk (0x8UL) /*!< MRCTLJ03 (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCTLK ========================================================= */ + #define R_SYSC_NS_MRCTLK_MRCTLK00_Pos (0UL) /*!< MRCTLK00 (Bit 0) */ + #define R_SYSC_NS_MRCTLK_MRCTLK00_Msk (0x1UL) /*!< MRCTLK00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLK_MRCTLK01_Pos (1UL) /*!< MRCTLK01 (Bit 1) */ + #define R_SYSC_NS_MRCTLK_MRCTLK01_Msk (0x2UL) /*!< MRCTLK01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLK_MRCTLK02_Pos (2UL) /*!< MRCTLK02 (Bit 2) */ + #define R_SYSC_NS_MRCTLK_MRCTLK02_Msk (0x4UL) /*!< MRCTLK02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLK_MRCTLK03_Pos (3UL) /*!< MRCTLK03 (Bit 3) */ + #define R_SYSC_NS_MRCTLK_MRCTLK03_Msk (0x8UL) /*!< MRCTLK03 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA00_Pos (0UL) /*!< MSTPCRA00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA00_Msk (0x1UL) /*!< MSTPCRA00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA04_Pos (4UL) /*!< MSTPCRA04 (Bit 4) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA04_Msk (0x10UL) /*!< MSTPCRA04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA05_Pos (5UL) /*!< MSTPCRA05 (Bit 5) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA05_Msk (0x20UL) /*!< MSTPCRA05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA08_Pos (8UL) /*!< MSTPCRA08 (Bit 8) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA08_Msk (0x100UL) /*!< MSTPCRA08 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA09_Pos (9UL) /*!< MSTPCRA09 (Bit 9) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA09_Msk (0x200UL) /*!< MSTPCRA09 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA10_Pos (10UL) /*!< MSTPCRA10 (Bit 10) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA10_Msk (0x400UL) /*!< MSTPCRA10 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA11_Pos (11UL) /*!< MSTPCRA11 (Bit 11) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA11_Msk (0x800UL) /*!< MSTPCRA11 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA12_Pos (12UL) /*!< MSTPCRA12 (Bit 12) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA12_Msk (0x1000UL) /*!< MSTPCRA12 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB00_Pos (0UL) /*!< MSTPCRB00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB00_Msk (0x1UL) /*!< MSTPCRB00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB01_Pos (1UL) /*!< MSTPCRB01 (Bit 1) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB01_Msk (0x2UL) /*!< MSTPCRB01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB04_Pos (4UL) /*!< MSTPCRB04 (Bit 4) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB04_Msk (0x10UL) /*!< MSTPCRB04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB05_Pos (5UL) /*!< MSTPCRB05 (Bit 5) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB05_Msk (0x20UL) /*!< MSTPCRB05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB06_Pos (6UL) /*!< MSTPCRB06 (Bit 6) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB06_Msk (0x40UL) /*!< MSTPCRB06 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC00_Pos (0UL) /*!< MSTPCRC00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC00_Msk (0x1UL) /*!< MSTPCRC00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC01_Pos (1UL) /*!< MSTPCRC01 (Bit 1) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC01_Msk (0x2UL) /*!< MSTPCRC01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC02_Pos (2UL) /*!< MSTPCRC02 (Bit 2) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC02_Msk (0x4UL) /*!< MSTPCRC02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC05_Pos (5UL) /*!< MSTPCRC05 (Bit 5) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC05_Msk (0x20UL) /*!< MSTPCRC05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC06_Pos (6UL) /*!< MSTPCRC06 (Bit 6) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC06_Msk (0x40UL) /*!< MSTPCRC06 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC07_Pos (7UL) /*!< MSTPCRC07 (Bit 7) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC07_Msk (0x80UL) /*!< MSTPCRC07 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD00_Pos (0UL) /*!< MSTPCRD00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD00_Msk (0x1UL) /*!< MSTPCRD00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD01_Pos (1UL) /*!< MSTPCRD01 (Bit 1) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD01_Msk (0x2UL) /*!< MSTPCRD01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD02_Pos (2UL) /*!< MSTPCRD02 (Bit 2) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD02_Msk (0x4UL) /*!< MSTPCRD02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD03_Pos (3UL) /*!< MSTPCRD03 (Bit 3) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD03_Msk (0x8UL) /*!< MSTPCRD03 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD04_Pos (4UL) /*!< MSTPCRD04 (Bit 4) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD04_Msk (0x10UL) /*!< MSTPCRD04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD05_Pos (5UL) /*!< MSTPCRD05 (Bit 5) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD05_Msk (0x20UL) /*!< MSTPCRD05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD06_Pos (6UL) /*!< MSTPCRD06 (Bit 6) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD06_Msk (0x40UL) /*!< MSTPCRD06 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD07_Pos (7UL) /*!< MSTPCRD07 (Bit 7) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD07_Msk (0x80UL) /*!< MSTPCRD07 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD08_Pos (8UL) /*!< MSTPCRD08 (Bit 8) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD08_Msk (0x100UL) /*!< MSTPCRD08 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD09_Pos (9UL) /*!< MSTPCRD09 (Bit 9) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD09_Msk (0x200UL) /*!< MSTPCRD09 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD10_Pos (10UL) /*!< MSTPCRD10 (Bit 10) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD10_Msk (0x400UL) /*!< MSTPCRD10 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD11_Pos (11UL) /*!< MSTPCRD11 (Bit 11) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD11_Msk (0x800UL) /*!< MSTPCRD11 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE00_Pos (0UL) /*!< MSTPCRE00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE00_Msk (0x1UL) /*!< MSTPCRE00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE02_Pos (2UL) /*!< MSTPCRE02 (Bit 2) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE02_Msk (0x4UL) /*!< MSTPCRE02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE03_Pos (3UL) /*!< MSTPCRE03 (Bit 3) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE03_Msk (0x8UL) /*!< MSTPCRE03 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE08_Pos (8UL) /*!< MSTPCRE08 (Bit 8) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE08_Msk (0x100UL) /*!< MSTPCRE08 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRJ ======================================================== */ + #define R_SYSC_NS_MSTPCRJ_MSTPCRJ00_Pos (0UL) /*!< MSTPCRJ00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRJ_MSTPCRJ00_Msk (0x1UL) /*!< MSTPCRJ00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRJ_MSTPCRJ01_Pos (1UL) /*!< MSTPCRJ01 (Bit 1) */ + #define R_SYSC_NS_MSTPCRJ_MSTPCRJ01_Msk (0x2UL) /*!< MSTPCRJ01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRJ_MSTPCRJ02_Pos (2UL) /*!< MSTPCRJ02 (Bit 2) */ + #define R_SYSC_NS_MSTPCRJ_MSTPCRJ02_Msk (0x4UL) /*!< MSTPCRJ02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRJ_MSTPCRJ03_Pos (3UL) /*!< MSTPCRJ03 (Bit 3) */ + #define R_SYSC_NS_MSTPCRJ_MSTPCRJ03_Msk (0x8UL) /*!< MSTPCRJ03 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRK ======================================================== */ + #define R_SYSC_NS_MSTPCRK_MSTPCRK00_Pos (0UL) /*!< MSTPCRK00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRK_MSTPCRK00_Msk (0x1UL) /*!< MSTPCRK00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRK_MSTPCRK01_Pos (1UL) /*!< MSTPCRK01 (Bit 1) */ + #define R_SYSC_NS_MSTPCRK_MSTPCRK01_Msk (0x2UL) /*!< MSTPCRK01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRK_MSTPCRK02_Pos (2UL) /*!< MSTPCRK02 (Bit 2) */ + #define R_SYSC_NS_MSTPCRK_MSTPCRK02_Msk (0x4UL) /*!< MSTPCRK02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRK_MSTPCRK03_Pos (3UL) /*!< MSTPCRK03 (Bit 3) */ + #define R_SYSC_NS_MSTPCRK_MSTPCRK03_Msk (0x8UL) /*!< MSTPCRK03 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRL ======================================================== */ + #define R_SYSC_NS_MSTPCRL_MSTPCRL00_Pos (0UL) /*!< MSTPCRL00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRL_MSTPCRL00_Msk (0x1UL) /*!< MSTPCRL00 (Bitfield-Mask: 0x01) */ +/* ======================================================== MD_MON ========================================================= */ + #define R_SYSC_NS_MD_MON_MDDMON_Pos (0UL) /*!< MDDMON (Bit 0) */ + #define R_SYSC_NS_MD_MON_MDDMON_Msk (0x1UL) /*!< MDDMON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MD0MON_Pos (12UL) /*!< MD0MON (Bit 12) */ + #define R_SYSC_NS_MD_MON_MD0MON_Msk (0x1000UL) /*!< MD0MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MD1MON_Pos (13UL) /*!< MD1MON (Bit 13) */ + #define R_SYSC_NS_MD_MON_MD1MON_Msk (0x2000UL) /*!< MD1MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MD2MON_Pos (14UL) /*!< MD2MON (Bit 14) */ + #define R_SYSC_NS_MD_MON_MD2MON_Msk (0x4000UL) /*!< MD2MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDV0MON_Pos (16UL) /*!< MDV0MON (Bit 16) */ + #define R_SYSC_NS_MD_MON_MDV0MON_Msk (0x10000UL) /*!< MDV0MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDV1MON_Pos (17UL) /*!< MDV1MON (Bit 17) */ + #define R_SYSC_NS_MD_MON_MDV1MON_Msk (0x20000UL) /*!< MDV1MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDV2MON_Pos (18UL) /*!< MDV2MON (Bit 18) */ + #define R_SYSC_NS_MD_MON_MDV2MON_Msk (0x40000UL) /*!< MDV2MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDV3MON_Pos (19UL) /*!< MDV3MON (Bit 19) */ + #define R_SYSC_NS_MD_MON_MDV3MON_Msk (0x80000UL) /*!< MDV3MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDV4MON_Pos (20UL) /*!< MDV4MON (Bit 20) */ + #define R_SYSC_NS_MD_MON_MDV4MON_Msk (0x100000UL) /*!< MDV4MON (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELO ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELOPA ========================================================= */ + #define R_ELO_ELOPA_MTU0MD_Pos (0UL) /*!< MTU0MD (Bit 0) */ + #define R_ELO_ELOPA_MTU0MD_Msk (0x3UL) /*!< MTU0MD (Bitfield-Mask: 0x03) */ + #define R_ELO_ELOPA_MTU3MD_Pos (6UL) /*!< MTU3MD (Bit 6) */ + #define R_ELO_ELOPA_MTU3MD_Msk (0xc0UL) /*!< MTU3MD (Bitfield-Mask: 0x03) */ +/* ========================================================= ELOPB ========================================================= */ + #define R_ELO_ELOPB_MTU4MD_Pos (0UL) /*!< MTU4MD (Bit 0) */ + #define R_ELO_ELOPB_MTU4MD_Msk (0x3UL) /*!< MTU4MD (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_ENCSS ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== ENCODER_CFG ====================================================== */ + #define R_ENCSS_ENCODER_CFG_HF0ENDIAN_Pos (0UL) /*!< HF0ENDIAN (Bit 0) */ + #define R_ENCSS_ENCODER_CFG_HF0ENDIAN_Msk (0x1UL) /*!< HF0ENDIAN (Bitfield-Mask: 0x01) */ + #define R_ENCSS_ENCODER_CFG_HF0SAFE1SEL_Pos (1UL) /*!< HF0SAFE1SEL (Bit 1) */ + #define R_ENCSS_ENCODER_CFG_HF0SAFE1SEL_Msk (0x2UL) /*!< HF0SAFE1SEL (Bitfield-Mask: 0x01) */ + #define R_ENCSS_ENCODER_CFG_EVTSRC0_Pos (2UL) /*!< EVTSRC0 (Bit 2) */ + #define R_ENCSS_ENCODER_CFG_EVTSRC0_Msk (0x4UL) /*!< EVTSRC0 (Bitfield-Mask: 0x01) */ + #define R_ENCSS_ENCODER_CFG_SS0SEL_Pos (3UL) /*!< SS0SEL (Bit 3) */ + #define R_ENCSS_ENCODER_CFG_SS0SEL_Msk (0x18UL) /*!< SS0SEL (Bitfield-Mask: 0x03) */ + #define R_ENCSS_ENCODER_CFG_TRGSEL0_Pos (5UL) /*!< TRGSEL0 (Bit 5) */ + #define R_ENCSS_ENCODER_CFG_TRGSEL0_Msk (0x20UL) /*!< TRGSEL0 (Bitfield-Mask: 0x01) */ + #define R_ENCSS_ENCODER_CFG_HF1ENDIAN_Pos (16UL) /*!< HF1ENDIAN (Bit 16) */ + #define R_ENCSS_ENCODER_CFG_HF1ENDIAN_Msk (0x10000UL) /*!< HF1ENDIAN (Bitfield-Mask: 0x01) */ + #define R_ENCSS_ENCODER_CFG_HF1SAFE1SEL_Pos (17UL) /*!< HF1SAFE1SEL (Bit 17) */ + #define R_ENCSS_ENCODER_CFG_HF1SAFE1SEL_Msk (0x20000UL) /*!< HF1SAFE1SEL (Bitfield-Mask: 0x01) */ + #define R_ENCSS_ENCODER_CFG_EVTSRC1_Pos (18UL) /*!< EVTSRC1 (Bit 18) */ + #define R_ENCSS_ENCODER_CFG_EVTSRC1_Msk (0x40000UL) /*!< EVTSRC1 (Bitfield-Mask: 0x01) */ + #define R_ENCSS_ENCODER_CFG_SS1SEL_Pos (19UL) /*!< SS1SEL (Bit 19) */ + #define R_ENCSS_ENCODER_CFG_SS1SEL_Msk (0x180000UL) /*!< SS1SEL (Bitfield-Mask: 0x03) */ + #define R_ENCSS_ENCODER_CFG_TRGSEL1_Pos (21UL) /*!< TRGSEL1 (Bit 21) */ + #define R_ENCSS_ENCODER_CFG_TRGSEL1_Msk (0x200000UL) /*!< TRGSEL1 (Bitfield-Mask: 0x01) */ +/* ======================================================= BISS_STAT ======================================================= */ + #define R_ENCSS_BISS_STAT_BISS0_ERR_Pos (0UL) /*!< BISS0_ERR (Bit 0) */ + #define R_ENCSS_BISS_STAT_BISS0_ERR_Msk (0x1UL) /*!< BISS0_ERR (Bitfield-Mask: 0x01) */ + #define R_ENCSS_BISS_STAT_BISS0_EOT_Pos (4UL) /*!< BISS0_EOT (Bit 4) */ + #define R_ENCSS_BISS_STAT_BISS0_EOT_Msk (0x10UL) /*!< BISS0_EOT (Bitfield-Mask: 0x01) */ + #define R_ENCSS_BISS_STAT_BISS1_ERR_Pos (16UL) /*!< BISS1_ERR (Bit 16) */ + #define R_ENCSS_BISS_STAT_BISS1_ERR_Msk (0x10000UL) /*!< BISS1_ERR (Bitfield-Mask: 0x01) */ + #define R_ENCSS_BISS_STAT_BISS1_EOT_Pos (20UL) /*!< BISS1_EOT (Bit 20) */ + #define R_ENCSS_BISS_STAT_BISS1_EOT_Msk (0x100000UL) /*!< BISS1_EOT (Bitfield-Mask: 0x01) */ +/* ======================================================= HDSL_STAT ======================================================= */ + #define R_ENCSS_HDSL_STAT_HDSL0_LINK_Pos (0UL) /*!< HDSL0_LINK (Bit 0) */ + #define R_ENCSS_HDSL_STAT_HDSL0_LINK_Msk (0x1UL) /*!< HDSL0_LINK (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL0_SYNCLCKD_Pos (1UL) /*!< HDSL0_SYNCLCKD (Bit 1) */ + #define R_ENCSS_HDSL_STAT_HDSL0_SYNCLCKD_Msk (0x2UL) /*!< HDSL0_SYNCLCKD (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL0_ESTON_Pos (4UL) /*!< HDSL0_ESTON (Bit 4) */ + #define R_ENCSS_HDSL_STAT_HDSL0_ESTON_Msk (0x10UL) /*!< HDSL0_ESTON (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL0_SCHERR_Pos (5UL) /*!< HDSL0_SCHERR (Bit 5) */ + #define R_ENCSS_HDSL_STAT_HDSL0_SCHERR_Msk (0x20UL) /*!< HDSL0_SCHERR (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL0_SPERR_Pos (6UL) /*!< HDSL0_SPERR (Bit 6) */ + #define R_ENCSS_HDSL_STAT_HDSL0_SPERR_Msk (0x40UL) /*!< HDSL0_SPERR (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL0_EDTERR_Pos (7UL) /*!< HDSL0_EDTERR (Bit 7) */ + #define R_ENCSS_HDSL_STAT_HDSL0_EDTERR_Msk (0x80UL) /*!< HDSL0_EDTERR (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL0_ACCERR_Pos (8UL) /*!< HDSL0_ACCERR (Bit 8) */ + #define R_ENCSS_HDSL_STAT_HDSL0_ACCERR_Msk (0x100UL) /*!< HDSL0_ACCERR (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL0_ACTHERR_Pos (9UL) /*!< HDSL0_ACTHERR (Bit 9) */ + #define R_ENCSS_HDSL_STAT_HDSL0_ACTHERR_Msk (0x200UL) /*!< HDSL0_ACTHERR (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL0_ENCERR_Pos (10UL) /*!< HDSL0_ENCERR (Bit 10) */ + #define R_ENCSS_HDSL_STAT_HDSL0_ENCERR_Msk (0x400UL) /*!< HDSL0_ENCERR (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL1_LINK_Pos (16UL) /*!< HDSL1_LINK (Bit 16) */ + #define R_ENCSS_HDSL_STAT_HDSL1_LINK_Msk (0x10000UL) /*!< HDSL1_LINK (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL1_SYNCLCKD_Pos (17UL) /*!< HDSL1_SYNCLCKD (Bit 17) */ + #define R_ENCSS_HDSL_STAT_HDSL1_SYNCLCKD_Msk (0x20000UL) /*!< HDSL1_SYNCLCKD (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL1_ESTON_Pos (20UL) /*!< HDSL1_ESTON (Bit 20) */ + #define R_ENCSS_HDSL_STAT_HDSL1_ESTON_Msk (0x100000UL) /*!< HDSL1_ESTON (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL1_SCHERR_Pos (21UL) /*!< HDSL1_SCHERR (Bit 21) */ + #define R_ENCSS_HDSL_STAT_HDSL1_SCHERR_Msk (0x200000UL) /*!< HDSL1_SCHERR (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL1_SPERR_Pos (22UL) /*!< HDSL1_SPERR (Bit 22) */ + #define R_ENCSS_HDSL_STAT_HDSL1_SPERR_Msk (0x400000UL) /*!< HDSL1_SPERR (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL1_EDTERR_Pos (23UL) /*!< HDSL1_EDTERR (Bit 23) */ + #define R_ENCSS_HDSL_STAT_HDSL1_EDTERR_Msk (0x800000UL) /*!< HDSL1_EDTERR (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL1_ACCERR_Pos (24UL) /*!< HDSL1_ACCERR (Bit 24) */ + #define R_ENCSS_HDSL_STAT_HDSL1_ACCERR_Msk (0x1000000UL) /*!< HDSL1_ACCERR (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL1_ACTHERR_Pos (25UL) /*!< HDSL1_ACTHERR (Bit 25) */ + #define R_ENCSS_HDSL_STAT_HDSL1_ACTHERR_Msk (0x2000000UL) /*!< HDSL1_ACTHERR (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL_STAT_HDSL1_ENCERR_Pos (26UL) /*!< HDSL1_ENCERR (Bit 26) */ + #define R_ENCSS_HDSL_STAT_HDSL1_ENCERR_Msk (0x4000000UL) /*!< HDSL1_ENCERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ENDAT_CFG ======================================================= */ + #define R_ENCSS_ENDAT_CFG_ENDAT0_AXADD_Pos (0UL) /*!< ENDAT0_AXADD (Bit 0) */ + #define R_ENCSS_ENDAT_CFG_ENDAT0_AXADD_Msk (0x1fUL) /*!< ENDAT0_AXADD (Bitfield-Mask: 0x1f) */ + #define R_ENCSS_ENDAT_CFG_ENDAT1_AXADD_Pos (16UL) /*!< ENDAT1_AXADD (Bit 16) */ + #define R_ENCSS_ENDAT_CFG_ENDAT1_AXADD_Msk (0x1f0000UL) /*!< ENDAT1_AXADD (Bitfield-Mask: 0x1f) */ +/* ======================================================= AFMT_STAT ======================================================= */ + #define R_ENCSS_AFMT_STAT_AFMT0_BUSY_Pos (0UL) /*!< AFMT0_BUSY (Bit 0) */ + #define R_ENCSS_AFMT_STAT_AFMT0_BUSY_Msk (0x1UL) /*!< AFMT0_BUSY (Bitfield-Mask: 0x01) */ + #define R_ENCSS_AFMT_STAT_AFMT0_EOT_Pos (1UL) /*!< AFMT0_EOT (Bit 1) */ + #define R_ENCSS_AFMT_STAT_AFMT0_EOT_Msk (0x2UL) /*!< AFMT0_EOT (Bitfield-Mask: 0x01) */ + #define R_ENCSS_AFMT_STAT_AFMT0_TMOUT_Pos (2UL) /*!< AFMT0_TMOUT (Bit 2) */ + #define R_ENCSS_AFMT_STAT_AFMT0_TMOUT_Msk (0x4UL) /*!< AFMT0_TMOUT (Bitfield-Mask: 0x01) */ + #define R_ENCSS_AFMT_STAT_AFMT1_BUSY_Pos (16UL) /*!< AFMT1_BUSY (Bit 16) */ + #define R_ENCSS_AFMT_STAT_AFMT1_BUSY_Msk (0x10000UL) /*!< AFMT1_BUSY (Bitfield-Mask: 0x01) */ + #define R_ENCSS_AFMT_STAT_AFMT1_EOT_Pos (17UL) /*!< AFMT1_EOT (Bit 17) */ + #define R_ENCSS_AFMT_STAT_AFMT1_EOT_Msk (0x20000UL) /*!< AFMT1_EOT (Bitfield-Mask: 0x01) */ + #define R_ENCSS_AFMT_STAT_AFMT1_TMOUT_Pos (18UL) /*!< AFMT1_TMOUT (Bit 18) */ + #define R_ENCSS_AFMT_STAT_AFMT1_TMOUT_Msk (0x40000UL) /*!< AFMT1_TMOUT (Bitfield-Mask: 0x01) */ +/* ====================================================== HDSL0_OS_D ======================================================= */ + #define R_ENCSS_HDSL0_OS_D_FREL_Pos (1UL) /*!< FREL (Bit 1) */ + #define R_ENCSS_HDSL0_OS_D_FREL_Msk (0x2UL) /*!< FREL (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_D_QMLW_Pos (2UL) /*!< QMLW (Bit 2) */ + #define R_ENCSS_HDSL0_OS_D_QMLW_Msk (0x4UL) /*!< QMLW (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_D_ANS_Pos (4UL) /*!< ANS (Bit 4) */ + #define R_ENCSS_HDSL0_OS_D_ANS_Msk (0x10UL) /*!< ANS (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_D_MIN_Pos (5UL) /*!< MIN (Bit 5) */ + #define R_ENCSS_HDSL0_OS_D_MIN_Msk (0x20UL) /*!< MIN (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_D_POSTX_Pos (6UL) /*!< POSTX (Bit 6) */ + #define R_ENCSS_HDSL0_OS_D_POSTX_Msk (0xc0UL) /*!< POSTX (Bitfield-Mask: 0x03) */ + #define R_ENCSS_HDSL0_OS_D_PRST_Pos (8UL) /*!< PRST (Bit 8) */ + #define R_ENCSS_HDSL0_OS_D_PRST_Msk (0x100UL) /*!< PRST (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_D_DTE_Pos (9UL) /*!< DTE (Bit 9) */ + #define R_ENCSS_HDSL0_OS_D_DTE_Msk (0x200UL) /*!< DTE (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_D_POS_Pos (11UL) /*!< POS (Bit 11) */ + #define R_ENCSS_HDSL0_OS_D_POS_Msk (0x800UL) /*!< POS (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_D_SUM_Pos (14UL) /*!< SUM (Bit 14) */ + #define R_ENCSS_HDSL0_OS_D_SUM_Msk (0x4000UL) /*!< SUM (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_D_INT_Pos (15UL) /*!< INT (Bit 15) */ + #define R_ENCSS_HDSL0_OS_D_INT_Msk (0x8000UL) /*!< INT (Bitfield-Mask: 0x01) */ +/* ====================================================== HDSL1_OS_D ======================================================= */ + #define R_ENCSS_HDSL1_OS_D_FREL_Pos (1UL) /*!< FREL (Bit 1) */ + #define R_ENCSS_HDSL1_OS_D_FREL_Msk (0x2UL) /*!< FREL (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL1_OS_D_QMLW_Pos (2UL) /*!< QMLW (Bit 2) */ + #define R_ENCSS_HDSL1_OS_D_QMLW_Msk (0x4UL) /*!< QMLW (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL1_OS_D_ANS_Pos (4UL) /*!< ANS (Bit 4) */ + #define R_ENCSS_HDSL1_OS_D_ANS_Msk (0x10UL) /*!< ANS (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL1_OS_D_MIN_Pos (5UL) /*!< MIN (Bit 5) */ + #define R_ENCSS_HDSL1_OS_D_MIN_Msk (0x20UL) /*!< MIN (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL1_OS_D_POSTX_Pos (6UL) /*!< POSTX (Bit 6) */ + #define R_ENCSS_HDSL1_OS_D_POSTX_Msk (0xc0UL) /*!< POSTX (Bitfield-Mask: 0x03) */ + #define R_ENCSS_HDSL1_OS_D_PRST_Pos (8UL) /*!< PRST (Bit 8) */ + #define R_ENCSS_HDSL1_OS_D_PRST_Msk (0x100UL) /*!< PRST (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL1_OS_D_DTE_Pos (9UL) /*!< DTE (Bit 9) */ + #define R_ENCSS_HDSL1_OS_D_DTE_Msk (0x200UL) /*!< DTE (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL1_OS_D_POS_Pos (11UL) /*!< POS (Bit 11) */ + #define R_ENCSS_HDSL1_OS_D_POS_Msk (0x800UL) /*!< POS (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL1_OS_D_SUM_Pos (14UL) /*!< SUM (Bit 14) */ + #define R_ENCSS_HDSL1_OS_D_SUM_Msk (0x4000UL) /*!< SUM (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL1_OS_D_INT_Pos (15UL) /*!< INT (Bit 15) */ + #define R_ENCSS_HDSL1_OS_D_INT_Msk (0x8000UL) /*!< INT (Bitfield-Mask: 0x01) */ +/* ====================================================== HDSL0_OS_1 ======================================================= */ + #define R_ENCSS_HDSL0_OS_1_FRES_Pos (0UL) /*!< FRES (Bit 0) */ + #define R_ENCSS_HDSL0_OS_1_FRES_Msk (0x1UL) /*!< FRES (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_1_QMLW_Pos (2UL) /*!< QMLW (Bit 2) */ + #define R_ENCSS_HDSL0_OS_1_QMLW_Msk (0x4UL) /*!< QMLW (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_1_MIN_Pos (5UL) /*!< MIN (Bit 5) */ + #define R_ENCSS_HDSL0_OS_1_MIN_Msk (0x20UL) /*!< MIN (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_1_POSTX_Pos (6UL) /*!< POSTX (Bit 6) */ + #define R_ENCSS_HDSL0_OS_1_POSTX_Msk (0xc0UL) /*!< POSTX (Bitfield-Mask: 0x03) */ + #define R_ENCSS_HDSL0_OS_1_PRST_Pos (8UL) /*!< PRST (Bit 8) */ + #define R_ENCSS_HDSL0_OS_1_PRST_Msk (0x100UL) /*!< PRST (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_1_VPOS_Pos (10UL) /*!< VPOS (Bit 10) */ + #define R_ENCSS_HDSL0_OS_1_VPOS_Msk (0x400UL) /*!< VPOS (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_1_SCE_Pos (13UL) /*!< SCE (Bit 13) */ + #define R_ENCSS_HDSL0_OS_1_SCE_Msk (0x2000UL) /*!< SCE (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_1_SSUM_Pos (14UL) /*!< SSUM (Bit 14) */ + #define R_ENCSS_HDSL0_OS_1_SSUM_Msk (0x4000UL) /*!< SSUM (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_1_SINT_Pos (15UL) /*!< SINT (Bit 15) */ + #define R_ENCSS_HDSL0_OS_1_SINT_Msk (0x8000UL) /*!< SINT (Bitfield-Mask: 0x01) */ +/* ====================================================== HDSL0_OS_2 ======================================================= */ + #define R_ENCSS_HDSL0_OS_2_QMLW_Pos (2UL) /*!< QMLW (Bit 2) */ + #define R_ENCSS_HDSL0_OS_2_QMLW_Msk (0x4UL) /*!< QMLW (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_2_POSTX_Pos (6UL) /*!< POSTX (Bit 6) */ + #define R_ENCSS_HDSL0_OS_2_POSTX_Msk (0xc0UL) /*!< POSTX (Bitfield-Mask: 0x03) */ + #define R_ENCSS_HDSL0_OS_2_PRST_Pos (8UL) /*!< PRST (Bit 8) */ + #define R_ENCSS_HDSL0_OS_2_PRST_Msk (0x100UL) /*!< PRST (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_2_VPOS2_Pos (10UL) /*!< VPOS2 (Bit 10) */ + #define R_ENCSS_HDSL0_OS_2_VPOS2_Msk (0x400UL) /*!< VPOS2 (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_2_SCE2_Pos (13UL) /*!< SCE2 (Bit 13) */ + #define R_ENCSS_HDSL0_OS_2_SCE2_Msk (0x2000UL) /*!< SCE2 (Bitfield-Mask: 0x01) */ + #define R_ENCSS_HDSL0_OS_2_SSUM2_Pos (14UL) /*!< SSUM2 (Bit 14) */ + #define R_ENCSS_HDSL0_OS_2_SSUM2_Msk (0x4000UL) /*!< SSUM2 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RWP_NS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRCRN ========================================================= */ + #define R_RWP_NS_PRCRN_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_RWP_NS_PRCRN_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_RWP_NS_PRCRN_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_RWP_NS_PRCRN_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_RWP_NS_PRCRN_PRC2_Pos (2UL) /*!< PRC2 (Bit 2) */ + #define R_RWP_NS_PRCRN_PRC2_Msk (0x4UL) /*!< PRC2 (Bitfield-Mask: 0x01) */ + #define R_RWP_NS_PRCRN_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_RWP_NS_PRCRN_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_RWP_NS_PRCRN_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_RWP_NS_PRCRN_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= RTCA0CTL0 ======================================================= */ + #define R_RTC_RTCA0CTL0_RTCA0SLSB_Pos (4UL) /*!< RTCA0SLSB (Bit 4) */ + #define R_RTC_RTCA0CTL0_RTCA0SLSB_Msk (0x10UL) /*!< RTCA0SLSB (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL0_RTCA0AMPM_Pos (5UL) /*!< RTCA0AMPM (Bit 5) */ + #define R_RTC_RTCA0CTL0_RTCA0AMPM_Msk (0x20UL) /*!< RTCA0AMPM (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL0_RTCA0CEST_Pos (6UL) /*!< RTCA0CEST (Bit 6) */ + #define R_RTC_RTCA0CTL0_RTCA0CEST_Msk (0x40UL) /*!< RTCA0CEST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL0_RTCA0CE_Pos (7UL) /*!< RTCA0CE (Bit 7) */ + #define R_RTC_RTCA0CTL0_RTCA0CE_Msk (0x80UL) /*!< RTCA0CE (Bitfield-Mask: 0x01) */ +/* ======================================================= RTCA0CTL1 ======================================================= */ + #define R_RTC_RTCA0CTL1_RTCA0CT_Pos (0UL) /*!< RTCA0CT (Bit 0) */ + #define R_RTC_RTCA0CTL1_RTCA0CT_Msk (0x7UL) /*!< RTCA0CT (Bitfield-Mask: 0x07) */ + #define R_RTC_RTCA0CTL1_RTCA01SE_Pos (3UL) /*!< RTCA01SE (Bit 3) */ + #define R_RTC_RTCA0CTL1_RTCA01SE_Msk (0x8UL) /*!< RTCA01SE (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL1_RTCA0ALME_Pos (4UL) /*!< RTCA0ALME (Bit 4) */ + #define R_RTC_RTCA0CTL1_RTCA0ALME_Msk (0x10UL) /*!< RTCA0ALME (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL1_RTCA01HZE_Pos (5UL) /*!< RTCA01HZE (Bit 5) */ + #define R_RTC_RTCA0CTL1_RTCA01HZE_Msk (0x20UL) /*!< RTCA01HZE (Bitfield-Mask: 0x01) */ +/* ======================================================= RTCA0CTL2 ======================================================= */ + #define R_RTC_RTCA0CTL2_RTCA0WAIT_Pos (0UL) /*!< RTCA0WAIT (Bit 0) */ + #define R_RTC_RTCA0CTL2_RTCA0WAIT_Msk (0x1UL) /*!< RTCA0WAIT (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL2_RTCA0WST_Pos (1UL) /*!< RTCA0WST (Bit 1) */ + #define R_RTC_RTCA0CTL2_RTCA0WST_Msk (0x2UL) /*!< RTCA0WST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL2_RTCA0RSUB_Pos (2UL) /*!< RTCA0RSUB (Bit 2) */ + #define R_RTC_RTCA0CTL2_RTCA0RSUB_Msk (0x4UL) /*!< RTCA0RSUB (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL2_RTCA0RSST_Pos (3UL) /*!< RTCA0RSST (Bit 3) */ + #define R_RTC_RTCA0CTL2_RTCA0RSST_Msk (0x8UL) /*!< RTCA0RSST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL2_RTCA0WSST_Pos (4UL) /*!< RTCA0WSST (Bit 4) */ + #define R_RTC_RTCA0CTL2_RTCA0WSST_Msk (0x10UL) /*!< RTCA0WSST (Bitfield-Mask: 0x01) */ +/* ======================================================= RTCA0SUBC ======================================================= */ + #define R_RTC_RTCA0SUBC_RTCA0SUBC_Pos (0UL) /*!< RTCA0SUBC (Bit 0) */ + #define R_RTC_RTCA0SUBC_RTCA0SUBC_Msk (0x3fffffUL) /*!< RTCA0SUBC (Bitfield-Mask: 0x3fffff) */ +/* ======================================================= RTCA0SRBU ======================================================= */ + #define R_RTC_RTCA0SRBU_RTCA0SRBU_Pos (0UL) /*!< RTCA0SRBU (Bit 0) */ + #define R_RTC_RTCA0SRBU_RTCA0SRBU_Msk (0x3fffffUL) /*!< RTCA0SRBU (Bitfield-Mask: 0x3fffff) */ +/* ======================================================= RTCA0SEC ======================================================== */ + #define R_RTC_RTCA0SEC_RTCA0SEC_Pos (0UL) /*!< RTCA0SEC (Bit 0) */ + #define R_RTC_RTCA0SEC_RTCA0SEC_Msk (0x7fUL) /*!< RTCA0SEC (Bitfield-Mask: 0x7f) */ +/* ======================================================= RTCA0MIN ======================================================== */ + #define R_RTC_RTCA0MIN_RTCA0MIN_Pos (0UL) /*!< RTCA0MIN (Bit 0) */ + #define R_RTC_RTCA0MIN_RTCA0MIN_Msk (0x7fUL) /*!< RTCA0MIN (Bitfield-Mask: 0x7f) */ +/* ======================================================= RTCA0HOUR ======================================================= */ + #define R_RTC_RTCA0HOUR_RTCA0HOUR_Pos (0UL) /*!< RTCA0HOUR (Bit 0) */ + #define R_RTC_RTCA0HOUR_RTCA0HOUR_Msk (0x3fUL) /*!< RTCA0HOUR (Bitfield-Mask: 0x3f) */ +/* ======================================================= RTCA0WEEK ======================================================= */ + #define R_RTC_RTCA0WEEK_RTCA0WEEK_Pos (0UL) /*!< RTCA0WEEK (Bit 0) */ + #define R_RTC_RTCA0WEEK_RTCA0WEEK_Msk (0x7UL) /*!< RTCA0WEEK (Bitfield-Mask: 0x07) */ +/* ======================================================= RTCA0DAY ======================================================== */ + #define R_RTC_RTCA0DAY_RTCA0DAY_Pos (0UL) /*!< RTCA0DAY (Bit 0) */ + #define R_RTC_RTCA0DAY_RTCA0DAY_Msk (0x3fUL) /*!< RTCA0DAY (Bitfield-Mask: 0x3f) */ +/* ====================================================== RTCA0MONTH ======================================================= */ + #define R_RTC_RTCA0MONTH_RTCA0MONTH_Pos (0UL) /*!< RTCA0MONTH (Bit 0) */ + #define R_RTC_RTCA0MONTH_RTCA0MONTH_Msk (0x1fUL) /*!< RTCA0MONTH (Bitfield-Mask: 0x1f) */ +/* ======================================================= RTCA0YEAR ======================================================= */ + #define R_RTC_RTCA0YEAR_RTCA0YEAR_Pos (0UL) /*!< RTCA0YEAR (Bit 0) */ + #define R_RTC_RTCA0YEAR_RTCA0YEAR_Msk (0xffUL) /*!< RTCA0YEAR (Bitfield-Mask: 0xff) */ +/* ======================================================= RTCA0TIME ======================================================= */ + #define R_RTC_RTCA0TIME_RTCA0SEC_Pos (0UL) /*!< RTCA0SEC (Bit 0) */ + #define R_RTC_RTCA0TIME_RTCA0SEC_Msk (0xffUL) /*!< RTCA0SEC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0TIME_RTCA0MIN_Pos (8UL) /*!< RTCA0MIN (Bit 8) */ + #define R_RTC_RTCA0TIME_RTCA0MIN_Msk (0xff00UL) /*!< RTCA0MIN (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0TIME_RTCA0HOUR_Pos (16UL) /*!< RTCA0HOUR (Bit 16) */ + #define R_RTC_RTCA0TIME_RTCA0HOUR_Msk (0xff0000UL) /*!< RTCA0HOUR (Bitfield-Mask: 0xff) */ +/* ======================================================= RTCA0CAL ======================================================== */ + #define R_RTC_RTCA0CAL_RTCA0WEEK_Pos (0UL) /*!< RTCA0WEEK (Bit 0) */ + #define R_RTC_RTCA0CAL_RTCA0WEEK_Msk (0xffUL) /*!< RTCA0WEEK (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CAL_RTCA0DAY_Pos (8UL) /*!< RTCA0DAY (Bit 8) */ + #define R_RTC_RTCA0CAL_RTCA0DAY_Msk (0xff00UL) /*!< RTCA0DAY (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CAL_RTCA0MONTH_Pos (16UL) /*!< RTCA0MONTH (Bit 16) */ + #define R_RTC_RTCA0CAL_RTCA0MONTH_Msk (0xff0000UL) /*!< RTCA0MONTH (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CAL_RTCA0YEAR_Pos (24UL) /*!< RTCA0YEAR (Bit 24) */ + #define R_RTC_RTCA0CAL_RTCA0YEAR_Msk (0xff000000UL) /*!< RTCA0YEAR (Bitfield-Mask: 0xff) */ +/* ======================================================= RTCA0SCMP ======================================================= */ + #define R_RTC_RTCA0SCMP_RTCA0SCMP_Pos (0UL) /*!< RTCA0SCMP (Bit 0) */ + #define R_RTC_RTCA0SCMP_RTCA0SCMP_Msk (0x3fffffUL) /*!< RTCA0SCMP (Bitfield-Mask: 0x3fffff) */ +/* ======================================================= RTCA0ALM ======================================================== */ + #define R_RTC_RTCA0ALM_RTCA0ALM_Pos (0UL) /*!< RTCA0ALM (Bit 0) */ + #define R_RTC_RTCA0ALM_RTCA0ALM_Msk (0x7fUL) /*!< RTCA0ALM (Bitfield-Mask: 0x7f) */ +/* ======================================================= RTCA0ALH ======================================================== */ + #define R_RTC_RTCA0ALH_RTCA0ALH_Pos (0UL) /*!< RTCA0ALH (Bit 0) */ + #define R_RTC_RTCA0ALH_RTCA0ALH_Msk (0x3fUL) /*!< RTCA0ALH (Bitfield-Mask: 0x3f) */ +/* ======================================================= RTCA0ALW ======================================================== */ + #define R_RTC_RTCA0ALW_RTCA0ALW0_Pos (0UL) /*!< RTCA0ALW0 (Bit 0) */ + #define R_RTC_RTCA0ALW_RTCA0ALW0_Msk (0x1UL) /*!< RTCA0ALW0 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW1_Pos (1UL) /*!< RTCA0ALW1 (Bit 1) */ + #define R_RTC_RTCA0ALW_RTCA0ALW1_Msk (0x2UL) /*!< RTCA0ALW1 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW2_Pos (2UL) /*!< RTCA0ALW2 (Bit 2) */ + #define R_RTC_RTCA0ALW_RTCA0ALW2_Msk (0x4UL) /*!< RTCA0ALW2 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW3_Pos (3UL) /*!< RTCA0ALW3 (Bit 3) */ + #define R_RTC_RTCA0ALW_RTCA0ALW3_Msk (0x8UL) /*!< RTCA0ALW3 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW4_Pos (4UL) /*!< RTCA0ALW4 (Bit 4) */ + #define R_RTC_RTCA0ALW_RTCA0ALW4_Msk (0x10UL) /*!< RTCA0ALW4 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW5_Pos (5UL) /*!< RTCA0ALW5 (Bit 5) */ + #define R_RTC_RTCA0ALW_RTCA0ALW5_Msk (0x20UL) /*!< RTCA0ALW5 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW6_Pos (6UL) /*!< RTCA0ALW6 (Bit 6) */ + #define R_RTC_RTCA0ALW_RTCA0ALW6_Msk (0x40UL) /*!< RTCA0ALW6 (Bitfield-Mask: 0x01) */ +/* ======================================================= RTCA0SECC ======================================================= */ + #define R_RTC_RTCA0SECC_RTCA0SECC_Pos (0UL) /*!< RTCA0SECC (Bit 0) */ + #define R_RTC_RTCA0SECC_RTCA0SECC_Msk (0x7fUL) /*!< RTCA0SECC (Bitfield-Mask: 0x7f) */ +/* ======================================================= RTCA0MINC ======================================================= */ + #define R_RTC_RTCA0MINC_RTCA0MINC_Pos (0UL) /*!< RTCA0MINC (Bit 0) */ + #define R_RTC_RTCA0MINC_RTCA0MINC_Msk (0x7fUL) /*!< RTCA0MINC (Bitfield-Mask: 0x7f) */ +/* ====================================================== RTCA0HOURC ======================================================= */ + #define R_RTC_RTCA0HOURC_RTCA0HOURC_Pos (0UL) /*!< RTCA0HOURC (Bit 0) */ + #define R_RTC_RTCA0HOURC_RTCA0HOURC_Msk (0x3fUL) /*!< RTCA0HOURC (Bitfield-Mask: 0x3f) */ +/* ====================================================== RTCA0WEEKC ======================================================= */ + #define R_RTC_RTCA0WEEKC_RTCA0WEEKC_Pos (0UL) /*!< RTCA0WEEKC (Bit 0) */ + #define R_RTC_RTCA0WEEKC_RTCA0WEEKC_Msk (0x7UL) /*!< RTCA0WEEKC (Bitfield-Mask: 0x07) */ +/* ======================================================= RTCA0DAYC ======================================================= */ + #define R_RTC_RTCA0DAYC_RTCA0DAYC_Pos (0UL) /*!< RTCA0DAYC (Bit 0) */ + #define R_RTC_RTCA0DAYC_RTCA0DAYC_Msk (0x3fUL) /*!< RTCA0DAYC (Bitfield-Mask: 0x3f) */ +/* ======================================================= RTCA0MONC ======================================================= */ + #define R_RTC_RTCA0MONC_RTCA0MONC_Pos (0UL) /*!< RTCA0MONC (Bit 0) */ + #define R_RTC_RTCA0MONC_RTCA0MONC_Msk (0x1fUL) /*!< RTCA0MONC (Bitfield-Mask: 0x1f) */ +/* ====================================================== RTCA0YEARC ======================================================= */ + #define R_RTC_RTCA0YEARC_RTCA0YEARC_Pos (0UL) /*!< RTCA0YEARC (Bit 0) */ + #define R_RTC_RTCA0YEARC_RTCA0YEARC_Msk (0xffUL) /*!< RTCA0YEARC (Bitfield-Mask: 0xff) */ +/* ====================================================== RTCA0TIMEC ======================================================= */ + #define R_RTC_RTCA0TIMEC_RTCA0SECC_Pos (0UL) /*!< RTCA0SECC (Bit 0) */ + #define R_RTC_RTCA0TIMEC_RTCA0SECC_Msk (0xffUL) /*!< RTCA0SECC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0TIMEC_RTCA0MINC_Pos (8UL) /*!< RTCA0MINC (Bit 8) */ + #define R_RTC_RTCA0TIMEC_RTCA0MINC_Msk (0xff00UL) /*!< RTCA0MINC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0TIMEC_RTCA0HOURC_Pos (16UL) /*!< RTCA0HOURC (Bit 16) */ + #define R_RTC_RTCA0TIMEC_RTCA0HOURC_Msk (0xff0000UL) /*!< RTCA0HOURC (Bitfield-Mask: 0xff) */ +/* ======================================================= RTCA0CALC ======================================================= */ + #define R_RTC_RTCA0CALC_RTCA0WEEKC_Pos (0UL) /*!< RTCA0WEEKC (Bit 0) */ + #define R_RTC_RTCA0CALC_RTCA0WEEKC_Msk (0xffUL) /*!< RTCA0WEEKC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CALC_RTCA0DAYC_Pos (8UL) /*!< RTCA0DAYC (Bit 8) */ + #define R_RTC_RTCA0CALC_RTCA0DAYC_Msk (0xff00UL) /*!< RTCA0DAYC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CALC_RTCA0MONC_Pos (16UL) /*!< RTCA0MONC (Bit 16) */ + #define R_RTC_RTCA0CALC_RTCA0MONC_Msk (0xff0000UL) /*!< RTCA0MONC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CALC_RTCA0YEARC_Pos (24UL) /*!< RTCA0YEARC (Bit 24) */ + #define R_RTC_RTCA0CALC_RTCA0YEARC_Msk (0xff000000UL) /*!< RTCA0YEARC (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG2 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== POEG2GA ======================================================== */ + #define R_POEG2_POEG2GA_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG2_POEG2GA_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG2_POEG2GA_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG2_POEG2GA_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG2_POEG2GA_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG2_POEG2GA_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG2_POEG2GA_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG2_POEG2GA_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG2_POEG2GA_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG2_POEG2GA_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG2_POEG2GA_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG2_POEG2GA_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG2GB ======================================================== */ + #define R_POEG2_POEG2GB_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG2_POEG2GB_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG2_POEG2GB_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG2_POEG2GB_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG2_POEG2GB_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG2_POEG2GB_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG2_POEG2GB_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG2_POEG2GB_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG2_POEG2GB_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG2_POEG2GB_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG2_POEG2GB_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG2_POEG2GB_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG2GC ======================================================== */ + #define R_POEG2_POEG2GC_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG2_POEG2GC_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG2_POEG2GC_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG2_POEG2GC_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG2_POEG2GC_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG2_POEG2GC_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG2_POEG2GC_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG2_POEG2GC_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG2_POEG2GC_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG2_POEG2GC_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG2_POEG2GC_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG2_POEG2GC_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG2GD ======================================================== */ + #define R_POEG2_POEG2GD_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG2_POEG2GD_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG2_POEG2GD_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG2_POEG2GD_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG2_POEG2GD_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG2_POEG2GD_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG2_POEG2GD_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG2_POEG2GD_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG2_POEG2GD_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG2_POEG2GD_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG2_POEG2GD_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG2_POEG2GD_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_OTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== OTPPWR ========================================================= */ + #define R_OTP_OTPPWR_PWR_Pos (0UL) /*!< PWR (Bit 0) */ + #define R_OTP_OTPPWR_PWR_Msk (0x1UL) /*!< PWR (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPPWR_ACCL_Pos (4UL) /*!< ACCL (Bit 4) */ + #define R_OTP_OTPPWR_ACCL_Msk (0x10UL) /*!< ACCL (Bitfield-Mask: 0x01) */ +/* ======================================================== OTPSTR ========================================================= */ + #define R_OTP_OTPSTR_CMD_RDY_Pos (0UL) /*!< CMD_RDY (Bit 0) */ + #define R_OTP_OTPSTR_CMD_RDY_Msk (0x1UL) /*!< CMD_RDY (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPSTR_ERR_WR_Pos (1UL) /*!< ERR_WR (Bit 1) */ + #define R_OTP_OTPSTR_ERR_WR_Msk (0x6UL) /*!< ERR_WR (Bitfield-Mask: 0x03) */ + #define R_OTP_OTPSTR_ERR_WP_Pos (3UL) /*!< ERR_WP (Bit 3) */ + #define R_OTP_OTPSTR_ERR_WP_Msk (0x8UL) /*!< ERR_WP (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPSTR_ERR_RP_Pos (4UL) /*!< ERR_RP (Bit 4) */ + #define R_OTP_OTPSTR_ERR_RP_Msk (0x10UL) /*!< ERR_RP (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPSTR_ERR_RDY_WR_Pos (8UL) /*!< ERR_RDY_WR (Bit 8) */ + #define R_OTP_OTPSTR_ERR_RDY_WR_Msk (0x100UL) /*!< ERR_RDY_WR (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPSTR_ERR_RDY_RD_Pos (9UL) /*!< ERR_RDY_RD (Bit 9) */ + #define R_OTP_OTPSTR_ERR_RDY_RD_Msk (0x200UL) /*!< ERR_RDY_RD (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPSTR_CNT_ST_IDLE_Pos (15UL) /*!< CNT_ST_IDLE (Bit 15) */ + #define R_OTP_OTPSTR_CNT_ST_IDLE_Msk (0x8000UL) /*!< CNT_ST_IDLE (Bitfield-Mask: 0x01) */ +/* ======================================================= OTPSTAWR ======================================================== */ + #define R_OTP_OTPSTAWR_STAWR_Pos (0UL) /*!< STAWR (Bit 0) */ + #define R_OTP_OTPSTAWR_STAWR_Msk (0x1UL) /*!< STAWR (Bitfield-Mask: 0x01) */ +/* ======================================================= OTPADRWR ======================================================== */ + #define R_OTP_OTPADRWR_ADRWR_Pos (0UL) /*!< ADRWR (Bit 0) */ + #define R_OTP_OTPADRWR_ADRWR_Msk (0x1ffUL) /*!< ADRWR (Bitfield-Mask: 0x1ff) */ +/* ======================================================= OTPDATAWR ======================================================= */ + #define R_OTP_OTPDATAWR_DATAWR_Pos (0UL) /*!< DATAWR (Bit 0) */ + #define R_OTP_OTPDATAWR_DATAWR_Msk (0xffffUL) /*!< DATAWR (Bitfield-Mask: 0xffff) */ +/* ======================================================= OTPADRRD ======================================================== */ + #define R_OTP_OTPADRRD_ADRRD_Pos (0UL) /*!< ADRRD (Bit 0) */ + #define R_OTP_OTPADRRD_ADRRD_Msk (0x1ffUL) /*!< ADRRD (Bitfield-Mask: 0x1ff) */ +/* ======================================================= OTPDATARD ======================================================= */ + #define R_OTP_OTPDATARD_DATARD_Pos (0UL) /*!< DATARD (Bit 0) */ + #define R_OTP_OTPDATARD_DATARD_Msk (0xffffUL) /*!< DATARD (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_PTADR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSELP ========================================================= */ + #define R_PTADR_RSELP_RS0_Pos (0UL) /*!< RS0 (Bit 0) */ + #define R_PTADR_RSELP_RS0_Msk (0x1UL) /*!< RS0 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS1_Pos (1UL) /*!< RS1 (Bit 1) */ + #define R_PTADR_RSELP_RS1_Msk (0x2UL) /*!< RS1 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS2_Pos (2UL) /*!< RS2 (Bit 2) */ + #define R_PTADR_RSELP_RS2_Msk (0x4UL) /*!< RS2 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS3_Pos (3UL) /*!< RS3 (Bit 3) */ + #define R_PTADR_RSELP_RS3_Msk (0x8UL) /*!< RS3 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS4_Pos (4UL) /*!< RS4 (Bit 4) */ + #define R_PTADR_RSELP_RS4_Msk (0x10UL) /*!< RS4 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS5_Pos (5UL) /*!< RS5 (Bit 5) */ + #define R_PTADR_RSELP_RS5_Msk (0x20UL) /*!< RS5 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS6_Pos (6UL) /*!< RS6 (Bit 6) */ + #define R_PTADR_RSELP_RS6_Msk (0x40UL) /*!< RS6 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS7_Pos (7UL) /*!< RS7 (Bit 7) */ + #define R_PTADR_RSELP_RS7_Msk (0x80UL) /*!< RS7 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSRAM0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== S_SWINT ======================================================== */ + #define R_ICU_S_SWINT_IC6_Pos (0UL) /*!< IC6 (Bit 0) */ + #define R_ICU_S_SWINT_IC6_Msk (0x1UL) /*!< IC6 (Bitfield-Mask: 0x01) */ + #define R_ICU_S_SWINT_IC7_Pos (1UL) /*!< IC7 (Bit 1) */ + #define R_ICU_S_SWINT_IC7_Msk (0x2UL) /*!< IC7 (Bitfield-Mask: 0x01) */ +/* ==================================================== S_PORTNF_FLTSEL ==================================================== */ + #define R_ICU_S_PORTNF_FLTSEL_FLT14_Pos (0UL) /*!< FLT14 (Bit 0) */ + #define R_ICU_S_PORTNF_FLTSEL_FLT14_Msk (0x1UL) /*!< FLT14 (Bitfield-Mask: 0x01) */ + #define R_ICU_S_PORTNF_FLTSEL_FLT15_Pos (1UL) /*!< FLT15 (Bit 1) */ + #define R_ICU_S_PORTNF_FLTSEL_FLT15_Msk (0x2UL) /*!< FLT15 (Bitfield-Mask: 0x01) */ + #define R_ICU_S_PORTNF_FLTSEL_FLTNMI_Pos (2UL) /*!< FLTNMI (Bit 2) */ + #define R_ICU_S_PORTNF_FLTSEL_FLTNMI_Msk (0x4UL) /*!< FLTNMI (Bitfield-Mask: 0x01) */ +/* ==================================================== S_PORTNF_CLKSEL ==================================================== */ + #define R_ICU_S_PORTNF_CLKSEL_CKSEL14_Pos (0UL) /*!< CKSEL14 (Bit 0) */ + #define R_ICU_S_PORTNF_CLKSEL_CKSEL14_Msk (0x3UL) /*!< CKSEL14 (Bitfield-Mask: 0x03) */ + #define R_ICU_S_PORTNF_CLKSEL_CKSEL15_Pos (2UL) /*!< CKSEL15 (Bit 2) */ + #define R_ICU_S_PORTNF_CLKSEL_CKSEL15_Msk (0xcUL) /*!< CKSEL15 (Bitfield-Mask: 0x03) */ + #define R_ICU_S_PORTNF_CLKSEL_CKSELNMI_Pos (4UL) /*!< CKSELNMI (Bit 4) */ + #define R_ICU_S_PORTNF_CLKSEL_CKSELNMI_Msk (0x30UL) /*!< CKSELNMI (Bitfield-Mask: 0x03) */ +/* ====================================================== S_PORTNF_MD ====================================================== */ + #define R_ICU_S_PORTNF_MD_MD14_Pos (0UL) /*!< MD14 (Bit 0) */ + #define R_ICU_S_PORTNF_MD_MD14_Msk (0x3UL) /*!< MD14 (Bitfield-Mask: 0x03) */ + #define R_ICU_S_PORTNF_MD_MD15_Pos (2UL) /*!< MD15 (Bit 2) */ + #define R_ICU_S_PORTNF_MD_MD15_Msk (0xcUL) /*!< MD15 (Bitfield-Mask: 0x03) */ + #define R_ICU_S_PORTNF_MD_MDNMI_Pos (4UL) /*!< MDNMI (Bit 4) */ + #define R_ICU_S_PORTNF_MD_MDNMI_Msk (0x30UL) /*!< MDNMI (Bitfield-Mask: 0x03) */ +/* ===================================================== CPU0ERR_STAT ====================================================== */ + #define R_ICU_CPU0ERR_STAT_ER_ST0_Pos (0UL) /*!< ER_ST0 (Bit 0) */ + #define R_ICU_CPU0ERR_STAT_ER_ST0_Msk (0x1UL) /*!< ER_ST0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST1_Pos (1UL) /*!< ER_ST1 (Bit 1) */ + #define R_ICU_CPU0ERR_STAT_ER_ST1_Msk (0x2UL) /*!< ER_ST1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST2_Pos (2UL) /*!< ER_ST2 (Bit 2) */ + #define R_ICU_CPU0ERR_STAT_ER_ST2_Msk (0x4UL) /*!< ER_ST2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST3_Pos (3UL) /*!< ER_ST3 (Bit 3) */ + #define R_ICU_CPU0ERR_STAT_ER_ST3_Msk (0x8UL) /*!< ER_ST3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST4_Pos (4UL) /*!< ER_ST4 (Bit 4) */ + #define R_ICU_CPU0ERR_STAT_ER_ST4_Msk (0x10UL) /*!< ER_ST4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST5_Pos (5UL) /*!< ER_ST5 (Bit 5) */ + #define R_ICU_CPU0ERR_STAT_ER_ST5_Msk (0x20UL) /*!< ER_ST5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST6_Pos (6UL) /*!< ER_ST6 (Bit 6) */ + #define R_ICU_CPU0ERR_STAT_ER_ST6_Msk (0x40UL) /*!< ER_ST6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST7_Pos (7UL) /*!< ER_ST7 (Bit 7) */ + #define R_ICU_CPU0ERR_STAT_ER_ST7_Msk (0x80UL) /*!< ER_ST7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST8_Pos (8UL) /*!< ER_ST8 (Bit 8) */ + #define R_ICU_CPU0ERR_STAT_ER_ST8_Msk (0x100UL) /*!< ER_ST8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST9_Pos (9UL) /*!< ER_ST9 (Bit 9) */ + #define R_ICU_CPU0ERR_STAT_ER_ST9_Msk (0x200UL) /*!< ER_ST9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST10_Pos (10UL) /*!< ER_ST10 (Bit 10) */ + #define R_ICU_CPU0ERR_STAT_ER_ST10_Msk (0x400UL) /*!< ER_ST10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST11_Pos (11UL) /*!< ER_ST11 (Bit 11) */ + #define R_ICU_CPU0ERR_STAT_ER_ST11_Msk (0x800UL) /*!< ER_ST11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST12_Pos (12UL) /*!< ER_ST12 (Bit 12) */ + #define R_ICU_CPU0ERR_STAT_ER_ST12_Msk (0x1000UL) /*!< ER_ST12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST13_Pos (13UL) /*!< ER_ST13 (Bit 13) */ + #define R_ICU_CPU0ERR_STAT_ER_ST13_Msk (0x2000UL) /*!< ER_ST13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST14_Pos (14UL) /*!< ER_ST14 (Bit 14) */ + #define R_ICU_CPU0ERR_STAT_ER_ST14_Msk (0x4000UL) /*!< ER_ST14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST15_Pos (15UL) /*!< ER_ST15 (Bit 15) */ + #define R_ICU_CPU0ERR_STAT_ER_ST15_Msk (0x8000UL) /*!< ER_ST15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST16_Pos (16UL) /*!< ER_ST16 (Bit 16) */ + #define R_ICU_CPU0ERR_STAT_ER_ST16_Msk (0x10000UL) /*!< ER_ST16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST17_Pos (17UL) /*!< ER_ST17 (Bit 17) */ + #define R_ICU_CPU0ERR_STAT_ER_ST17_Msk (0x20000UL) /*!< ER_ST17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST18_Pos (18UL) /*!< ER_ST18 (Bit 18) */ + #define R_ICU_CPU0ERR_STAT_ER_ST18_Msk (0x40000UL) /*!< ER_ST18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST19_Pos (19UL) /*!< ER_ST19 (Bit 19) */ + #define R_ICU_CPU0ERR_STAT_ER_ST19_Msk (0x80000UL) /*!< ER_ST19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST20_Pos (20UL) /*!< ER_ST20 (Bit 20) */ + #define R_ICU_CPU0ERR_STAT_ER_ST20_Msk (0x100000UL) /*!< ER_ST20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST21_Pos (21UL) /*!< ER_ST21 (Bit 21) */ + #define R_ICU_CPU0ERR_STAT_ER_ST21_Msk (0x200000UL) /*!< ER_ST21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST22_Pos (22UL) /*!< ER_ST22 (Bit 22) */ + #define R_ICU_CPU0ERR_STAT_ER_ST22_Msk (0x400000UL) /*!< ER_ST22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST23_Pos (23UL) /*!< ER_ST23 (Bit 23) */ + #define R_ICU_CPU0ERR_STAT_ER_ST23_Msk (0x800000UL) /*!< ER_ST23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST24_Pos (24UL) /*!< ER_ST24 (Bit 24) */ + #define R_ICU_CPU0ERR_STAT_ER_ST24_Msk (0x1000000UL) /*!< ER_ST24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST25_Pos (25UL) /*!< ER_ST25 (Bit 25) */ + #define R_ICU_CPU0ERR_STAT_ER_ST25_Msk (0x2000000UL) /*!< ER_ST25 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_STAT0 ===================================================== */ + #define R_ICU_PERIERR_STAT0_ER_ST0_Pos (0UL) /*!< ER_ST0 (Bit 0) */ + #define R_ICU_PERIERR_STAT0_ER_ST0_Msk (0x1UL) /*!< ER_ST0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST1_Pos (1UL) /*!< ER_ST1 (Bit 1) */ + #define R_ICU_PERIERR_STAT0_ER_ST1_Msk (0x2UL) /*!< ER_ST1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST2_Pos (2UL) /*!< ER_ST2 (Bit 2) */ + #define R_ICU_PERIERR_STAT0_ER_ST2_Msk (0x4UL) /*!< ER_ST2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST3_Pos (3UL) /*!< ER_ST3 (Bit 3) */ + #define R_ICU_PERIERR_STAT0_ER_ST3_Msk (0x8UL) /*!< ER_ST3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST4_Pos (4UL) /*!< ER_ST4 (Bit 4) */ + #define R_ICU_PERIERR_STAT0_ER_ST4_Msk (0x10UL) /*!< ER_ST4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST5_Pos (5UL) /*!< ER_ST5 (Bit 5) */ + #define R_ICU_PERIERR_STAT0_ER_ST5_Msk (0x20UL) /*!< ER_ST5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST6_Pos (6UL) /*!< ER_ST6 (Bit 6) */ + #define R_ICU_PERIERR_STAT0_ER_ST6_Msk (0x40UL) /*!< ER_ST6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST7_Pos (7UL) /*!< ER_ST7 (Bit 7) */ + #define R_ICU_PERIERR_STAT0_ER_ST7_Msk (0x80UL) /*!< ER_ST7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST9_Pos (9UL) /*!< ER_ST9 (Bit 9) */ + #define R_ICU_PERIERR_STAT0_ER_ST9_Msk (0x200UL) /*!< ER_ST9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST10_Pos (10UL) /*!< ER_ST10 (Bit 10) */ + #define R_ICU_PERIERR_STAT0_ER_ST10_Msk (0x400UL) /*!< ER_ST10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST11_Pos (11UL) /*!< ER_ST11 (Bit 11) */ + #define R_ICU_PERIERR_STAT0_ER_ST11_Msk (0x800UL) /*!< ER_ST11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST12_Pos (12UL) /*!< ER_ST12 (Bit 12) */ + #define R_ICU_PERIERR_STAT0_ER_ST12_Msk (0x1000UL) /*!< ER_ST12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST13_Pos (13UL) /*!< ER_ST13 (Bit 13) */ + #define R_ICU_PERIERR_STAT0_ER_ST13_Msk (0x2000UL) /*!< ER_ST13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST14_Pos (14UL) /*!< ER_ST14 (Bit 14) */ + #define R_ICU_PERIERR_STAT0_ER_ST14_Msk (0x4000UL) /*!< ER_ST14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST15_Pos (15UL) /*!< ER_ST15 (Bit 15) */ + #define R_ICU_PERIERR_STAT0_ER_ST15_Msk (0x8000UL) /*!< ER_ST15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST16_Pos (16UL) /*!< ER_ST16 (Bit 16) */ + #define R_ICU_PERIERR_STAT0_ER_ST16_Msk (0x10000UL) /*!< ER_ST16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST17_Pos (17UL) /*!< ER_ST17 (Bit 17) */ + #define R_ICU_PERIERR_STAT0_ER_ST17_Msk (0x20000UL) /*!< ER_ST17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST18_Pos (18UL) /*!< ER_ST18 (Bit 18) */ + #define R_ICU_PERIERR_STAT0_ER_ST18_Msk (0x40000UL) /*!< ER_ST18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST19_Pos (19UL) /*!< ER_ST19 (Bit 19) */ + #define R_ICU_PERIERR_STAT0_ER_ST19_Msk (0x80000UL) /*!< ER_ST19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST20_Pos (20UL) /*!< ER_ST20 (Bit 20) */ + #define R_ICU_PERIERR_STAT0_ER_ST20_Msk (0x100000UL) /*!< ER_ST20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST21_Pos (21UL) /*!< ER_ST21 (Bit 21) */ + #define R_ICU_PERIERR_STAT0_ER_ST21_Msk (0x200000UL) /*!< ER_ST21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST22_Pos (22UL) /*!< ER_ST22 (Bit 22) */ + #define R_ICU_PERIERR_STAT0_ER_ST22_Msk (0x400000UL) /*!< ER_ST22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST23_Pos (23UL) /*!< ER_ST23 (Bit 23) */ + #define R_ICU_PERIERR_STAT0_ER_ST23_Msk (0x800000UL) /*!< ER_ST23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST24_Pos (24UL) /*!< ER_ST24 (Bit 24) */ + #define R_ICU_PERIERR_STAT0_ER_ST24_Msk (0x1000000UL) /*!< ER_ST24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST25_Pos (25UL) /*!< ER_ST25 (Bit 25) */ + #define R_ICU_PERIERR_STAT0_ER_ST25_Msk (0x2000000UL) /*!< ER_ST25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST26_Pos (26UL) /*!< ER_ST26 (Bit 26) */ + #define R_ICU_PERIERR_STAT0_ER_ST26_Msk (0x4000000UL) /*!< ER_ST26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST27_Pos (27UL) /*!< ER_ST27 (Bit 27) */ + #define R_ICU_PERIERR_STAT0_ER_ST27_Msk (0x8000000UL) /*!< ER_ST27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST28_Pos (28UL) /*!< ER_ST28 (Bit 28) */ + #define R_ICU_PERIERR_STAT0_ER_ST28_Msk (0x10000000UL) /*!< ER_ST28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST29_Pos (29UL) /*!< ER_ST29 (Bit 29) */ + #define R_ICU_PERIERR_STAT0_ER_ST29_Msk (0x20000000UL) /*!< ER_ST29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST30_Pos (30UL) /*!< ER_ST30 (Bit 30) */ + #define R_ICU_PERIERR_STAT0_ER_ST30_Msk (0x40000000UL) /*!< ER_ST30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST31_Pos (31UL) /*!< ER_ST31 (Bit 31) */ + #define R_ICU_PERIERR_STAT0_ER_ST31_Msk (0x80000000UL) /*!< ER_ST31 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_STAT1 ===================================================== */ + #define R_ICU_PERIERR_STAT1_ER_ST0_Pos (0UL) /*!< ER_ST0 (Bit 0) */ + #define R_ICU_PERIERR_STAT1_ER_ST0_Msk (0x1UL) /*!< ER_ST0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST1_Pos (1UL) /*!< ER_ST1 (Bit 1) */ + #define R_ICU_PERIERR_STAT1_ER_ST1_Msk (0x2UL) /*!< ER_ST1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST2_Pos (2UL) /*!< ER_ST2 (Bit 2) */ + #define R_ICU_PERIERR_STAT1_ER_ST2_Msk (0x4UL) /*!< ER_ST2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST3_Pos (3UL) /*!< ER_ST3 (Bit 3) */ + #define R_ICU_PERIERR_STAT1_ER_ST3_Msk (0x8UL) /*!< ER_ST3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST4_Pos (4UL) /*!< ER_ST4 (Bit 4) */ + #define R_ICU_PERIERR_STAT1_ER_ST4_Msk (0x10UL) /*!< ER_ST4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST5_Pos (5UL) /*!< ER_ST5 (Bit 5) */ + #define R_ICU_PERIERR_STAT1_ER_ST5_Msk (0x20UL) /*!< ER_ST5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST6_Pos (6UL) /*!< ER_ST6 (Bit 6) */ + #define R_ICU_PERIERR_STAT1_ER_ST6_Msk (0x40UL) /*!< ER_ST6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST13_Pos (13UL) /*!< ER_ST13 (Bit 13) */ + #define R_ICU_PERIERR_STAT1_ER_ST13_Msk (0x2000UL) /*!< ER_ST13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST15_Pos (15UL) /*!< ER_ST15 (Bit 15) */ + #define R_ICU_PERIERR_STAT1_ER_ST15_Msk (0x8000UL) /*!< ER_ST15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST17_Pos (17UL) /*!< ER_ST17 (Bit 17) */ + #define R_ICU_PERIERR_STAT1_ER_ST17_Msk (0x20000UL) /*!< ER_ST17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST18_Pos (18UL) /*!< ER_ST18 (Bit 18) */ + #define R_ICU_PERIERR_STAT1_ER_ST18_Msk (0x40000UL) /*!< ER_ST18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST19_Pos (19UL) /*!< ER_ST19 (Bit 19) */ + #define R_ICU_PERIERR_STAT1_ER_ST19_Msk (0x80000UL) /*!< ER_ST19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST20_Pos (20UL) /*!< ER_ST20 (Bit 20) */ + #define R_ICU_PERIERR_STAT1_ER_ST20_Msk (0x100000UL) /*!< ER_ST20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST21_Pos (21UL) /*!< ER_ST21 (Bit 21) */ + #define R_ICU_PERIERR_STAT1_ER_ST21_Msk (0x200000UL) /*!< ER_ST21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST22_Pos (22UL) /*!< ER_ST22 (Bit 22) */ + #define R_ICU_PERIERR_STAT1_ER_ST22_Msk (0x400000UL) /*!< ER_ST22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST23_Pos (23UL) /*!< ER_ST23 (Bit 23) */ + #define R_ICU_PERIERR_STAT1_ER_ST23_Msk (0x800000UL) /*!< ER_ST23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST24_Pos (24UL) /*!< ER_ST24 (Bit 24) */ + #define R_ICU_PERIERR_STAT1_ER_ST24_Msk (0x1000000UL) /*!< ER_ST24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST27_Pos (27UL) /*!< ER_ST27 (Bit 27) */ + #define R_ICU_PERIERR_STAT1_ER_ST27_Msk (0x8000000UL) /*!< ER_ST27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST28_Pos (28UL) /*!< ER_ST28 (Bit 28) */ + #define R_ICU_PERIERR_STAT1_ER_ST28_Msk (0x10000000UL) /*!< ER_ST28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST29_Pos (29UL) /*!< ER_ST29 (Bit 29) */ + #define R_ICU_PERIERR_STAT1_ER_ST29_Msk (0x20000000UL) /*!< ER_ST29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST30_Pos (30UL) /*!< ER_ST30 (Bit 30) */ + #define R_ICU_PERIERR_STAT1_ER_ST30_Msk (0x40000000UL) /*!< ER_ST30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST31_Pos (31UL) /*!< ER_ST31 (Bit 31) */ + #define R_ICU_PERIERR_STAT1_ER_ST31_Msk (0x80000000UL) /*!< ER_ST31 (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU0ERR_CLR ====================================================== */ + #define R_ICU_CPU0ERR_CLR_ER_CL0_Pos (0UL) /*!< ER_CL0 (Bit 0) */ + #define R_ICU_CPU0ERR_CLR_ER_CL0_Msk (0x1UL) /*!< ER_CL0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL1_Pos (1UL) /*!< ER_CL1 (Bit 1) */ + #define R_ICU_CPU0ERR_CLR_ER_CL1_Msk (0x2UL) /*!< ER_CL1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL2_Pos (2UL) /*!< ER_CL2 (Bit 2) */ + #define R_ICU_CPU0ERR_CLR_ER_CL2_Msk (0x4UL) /*!< ER_CL2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL3_Pos (3UL) /*!< ER_CL3 (Bit 3) */ + #define R_ICU_CPU0ERR_CLR_ER_CL3_Msk (0x8UL) /*!< ER_CL3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL4_Pos (4UL) /*!< ER_CL4 (Bit 4) */ + #define R_ICU_CPU0ERR_CLR_ER_CL4_Msk (0x10UL) /*!< ER_CL4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL5_Pos (5UL) /*!< ER_CL5 (Bit 5) */ + #define R_ICU_CPU0ERR_CLR_ER_CL5_Msk (0x20UL) /*!< ER_CL5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL6_Pos (6UL) /*!< ER_CL6 (Bit 6) */ + #define R_ICU_CPU0ERR_CLR_ER_CL6_Msk (0x40UL) /*!< ER_CL6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL7_Pos (7UL) /*!< ER_CL7 (Bit 7) */ + #define R_ICU_CPU0ERR_CLR_ER_CL7_Msk (0x80UL) /*!< ER_CL7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL8_Pos (8UL) /*!< ER_CL8 (Bit 8) */ + #define R_ICU_CPU0ERR_CLR_ER_CL8_Msk (0x100UL) /*!< ER_CL8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL9_Pos (9UL) /*!< ER_CL9 (Bit 9) */ + #define R_ICU_CPU0ERR_CLR_ER_CL9_Msk (0x200UL) /*!< ER_CL9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL10_Pos (10UL) /*!< ER_CL10 (Bit 10) */ + #define R_ICU_CPU0ERR_CLR_ER_CL10_Msk (0x400UL) /*!< ER_CL10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL11_Pos (11UL) /*!< ER_CL11 (Bit 11) */ + #define R_ICU_CPU0ERR_CLR_ER_CL11_Msk (0x800UL) /*!< ER_CL11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL12_Pos (12UL) /*!< ER_CL12 (Bit 12) */ + #define R_ICU_CPU0ERR_CLR_ER_CL12_Msk (0x1000UL) /*!< ER_CL12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL13_Pos (13UL) /*!< ER_CL13 (Bit 13) */ + #define R_ICU_CPU0ERR_CLR_ER_CL13_Msk (0x2000UL) /*!< ER_CL13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL14_Pos (14UL) /*!< ER_CL14 (Bit 14) */ + #define R_ICU_CPU0ERR_CLR_ER_CL14_Msk (0x4000UL) /*!< ER_CL14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL15_Pos (15UL) /*!< ER_CL15 (Bit 15) */ + #define R_ICU_CPU0ERR_CLR_ER_CL15_Msk (0x8000UL) /*!< ER_CL15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL16_Pos (16UL) /*!< ER_CL16 (Bit 16) */ + #define R_ICU_CPU0ERR_CLR_ER_CL16_Msk (0x10000UL) /*!< ER_CL16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL17_Pos (17UL) /*!< ER_CL17 (Bit 17) */ + #define R_ICU_CPU0ERR_CLR_ER_CL17_Msk (0x20000UL) /*!< ER_CL17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL18_Pos (18UL) /*!< ER_CL18 (Bit 18) */ + #define R_ICU_CPU0ERR_CLR_ER_CL18_Msk (0x40000UL) /*!< ER_CL18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL19_Pos (19UL) /*!< ER_CL19 (Bit 19) */ + #define R_ICU_CPU0ERR_CLR_ER_CL19_Msk (0x80000UL) /*!< ER_CL19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL20_Pos (20UL) /*!< ER_CL20 (Bit 20) */ + #define R_ICU_CPU0ERR_CLR_ER_CL20_Msk (0x100000UL) /*!< ER_CL20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL21_Pos (21UL) /*!< ER_CL21 (Bit 21) */ + #define R_ICU_CPU0ERR_CLR_ER_CL21_Msk (0x200000UL) /*!< ER_CL21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL22_Pos (22UL) /*!< ER_CL22 (Bit 22) */ + #define R_ICU_CPU0ERR_CLR_ER_CL22_Msk (0x400000UL) /*!< ER_CL22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL23_Pos (23UL) /*!< ER_CL23 (Bit 23) */ + #define R_ICU_CPU0ERR_CLR_ER_CL23_Msk (0x800000UL) /*!< ER_CL23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL24_Pos (24UL) /*!< ER_CL24 (Bit 24) */ + #define R_ICU_CPU0ERR_CLR_ER_CL24_Msk (0x1000000UL) /*!< ER_CL24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL25_Pos (25UL) /*!< ER_CL25 (Bit 25) */ + #define R_ICU_CPU0ERR_CLR_ER_CL25_Msk (0x2000000UL) /*!< ER_CL25 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_CLR0 ====================================================== */ + #define R_ICU_PERIERR_CLR0_ER_CL0_Pos (0UL) /*!< ER_CL0 (Bit 0) */ + #define R_ICU_PERIERR_CLR0_ER_CL0_Msk (0x1UL) /*!< ER_CL0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL1_Pos (1UL) /*!< ER_CL1 (Bit 1) */ + #define R_ICU_PERIERR_CLR0_ER_CL1_Msk (0x2UL) /*!< ER_CL1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL2_Pos (2UL) /*!< ER_CL2 (Bit 2) */ + #define R_ICU_PERIERR_CLR0_ER_CL2_Msk (0x4UL) /*!< ER_CL2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL3_Pos (3UL) /*!< ER_CL3 (Bit 3) */ + #define R_ICU_PERIERR_CLR0_ER_CL3_Msk (0x8UL) /*!< ER_CL3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL4_Pos (4UL) /*!< ER_CL4 (Bit 4) */ + #define R_ICU_PERIERR_CLR0_ER_CL4_Msk (0x10UL) /*!< ER_CL4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL5_Pos (5UL) /*!< ER_CL5 (Bit 5) */ + #define R_ICU_PERIERR_CLR0_ER_CL5_Msk (0x20UL) /*!< ER_CL5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL6_Pos (6UL) /*!< ER_CL6 (Bit 6) */ + #define R_ICU_PERIERR_CLR0_ER_CL6_Msk (0x40UL) /*!< ER_CL6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL7_Pos (7UL) /*!< ER_CL7 (Bit 7) */ + #define R_ICU_PERIERR_CLR0_ER_CL7_Msk (0x80UL) /*!< ER_CL7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL9_Pos (9UL) /*!< ER_CL9 (Bit 9) */ + #define R_ICU_PERIERR_CLR0_ER_CL9_Msk (0x200UL) /*!< ER_CL9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL10_Pos (10UL) /*!< ER_CL10 (Bit 10) */ + #define R_ICU_PERIERR_CLR0_ER_CL10_Msk (0x400UL) /*!< ER_CL10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL11_Pos (11UL) /*!< ER_CL11 (Bit 11) */ + #define R_ICU_PERIERR_CLR0_ER_CL11_Msk (0x800UL) /*!< ER_CL11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL12_Pos (12UL) /*!< ER_CL12 (Bit 12) */ + #define R_ICU_PERIERR_CLR0_ER_CL12_Msk (0x1000UL) /*!< ER_CL12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL13_Pos (13UL) /*!< ER_CL13 (Bit 13) */ + #define R_ICU_PERIERR_CLR0_ER_CL13_Msk (0x2000UL) /*!< ER_CL13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL14_Pos (14UL) /*!< ER_CL14 (Bit 14) */ + #define R_ICU_PERIERR_CLR0_ER_CL14_Msk (0x4000UL) /*!< ER_CL14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL15_Pos (15UL) /*!< ER_CL15 (Bit 15) */ + #define R_ICU_PERIERR_CLR0_ER_CL15_Msk (0x8000UL) /*!< ER_CL15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL16_Pos (16UL) /*!< ER_CL16 (Bit 16) */ + #define R_ICU_PERIERR_CLR0_ER_CL16_Msk (0x10000UL) /*!< ER_CL16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL17_Pos (17UL) /*!< ER_CL17 (Bit 17) */ + #define R_ICU_PERIERR_CLR0_ER_CL17_Msk (0x20000UL) /*!< ER_CL17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL18_Pos (18UL) /*!< ER_CL18 (Bit 18) */ + #define R_ICU_PERIERR_CLR0_ER_CL18_Msk (0x40000UL) /*!< ER_CL18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL19_Pos (19UL) /*!< ER_CL19 (Bit 19) */ + #define R_ICU_PERIERR_CLR0_ER_CL19_Msk (0x80000UL) /*!< ER_CL19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL20_Pos (20UL) /*!< ER_CL20 (Bit 20) */ + #define R_ICU_PERIERR_CLR0_ER_CL20_Msk (0x100000UL) /*!< ER_CL20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL21_Pos (21UL) /*!< ER_CL21 (Bit 21) */ + #define R_ICU_PERIERR_CLR0_ER_CL21_Msk (0x200000UL) /*!< ER_CL21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL22_Pos (22UL) /*!< ER_CL22 (Bit 22) */ + #define R_ICU_PERIERR_CLR0_ER_CL22_Msk (0x400000UL) /*!< ER_CL22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL23_Pos (23UL) /*!< ER_CL23 (Bit 23) */ + #define R_ICU_PERIERR_CLR0_ER_CL23_Msk (0x800000UL) /*!< ER_CL23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL24_Pos (24UL) /*!< ER_CL24 (Bit 24) */ + #define R_ICU_PERIERR_CLR0_ER_CL24_Msk (0x1000000UL) /*!< ER_CL24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL25_Pos (25UL) /*!< ER_CL25 (Bit 25) */ + #define R_ICU_PERIERR_CLR0_ER_CL25_Msk (0x2000000UL) /*!< ER_CL25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL26_Pos (26UL) /*!< ER_CL26 (Bit 26) */ + #define R_ICU_PERIERR_CLR0_ER_CL26_Msk (0x4000000UL) /*!< ER_CL26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL27_Pos (27UL) /*!< ER_CL27 (Bit 27) */ + #define R_ICU_PERIERR_CLR0_ER_CL27_Msk (0x8000000UL) /*!< ER_CL27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL28_Pos (28UL) /*!< ER_CL28 (Bit 28) */ + #define R_ICU_PERIERR_CLR0_ER_CL28_Msk (0x10000000UL) /*!< ER_CL28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL29_Pos (29UL) /*!< ER_CL29 (Bit 29) */ + #define R_ICU_PERIERR_CLR0_ER_CL29_Msk (0x20000000UL) /*!< ER_CL29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL30_Pos (30UL) /*!< ER_CL30 (Bit 30) */ + #define R_ICU_PERIERR_CLR0_ER_CL30_Msk (0x40000000UL) /*!< ER_CL30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL31_Pos (31UL) /*!< ER_CL31 (Bit 31) */ + #define R_ICU_PERIERR_CLR0_ER_CL31_Msk (0x80000000UL) /*!< ER_CL31 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_CLR1 ====================================================== */ + #define R_ICU_PERIERR_CLR1_ER_CL0_Pos (0UL) /*!< ER_CL0 (Bit 0) */ + #define R_ICU_PERIERR_CLR1_ER_CL0_Msk (0x1UL) /*!< ER_CL0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL1_Pos (1UL) /*!< ER_CL1 (Bit 1) */ + #define R_ICU_PERIERR_CLR1_ER_CL1_Msk (0x2UL) /*!< ER_CL1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL2_Pos (2UL) /*!< ER_CL2 (Bit 2) */ + #define R_ICU_PERIERR_CLR1_ER_CL2_Msk (0x4UL) /*!< ER_CL2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL3_Pos (3UL) /*!< ER_CL3 (Bit 3) */ + #define R_ICU_PERIERR_CLR1_ER_CL3_Msk (0x8UL) /*!< ER_CL3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL4_Pos (4UL) /*!< ER_CL4 (Bit 4) */ + #define R_ICU_PERIERR_CLR1_ER_CL4_Msk (0x10UL) /*!< ER_CL4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL5_Pos (5UL) /*!< ER_CL5 (Bit 5) */ + #define R_ICU_PERIERR_CLR1_ER_CL5_Msk (0x20UL) /*!< ER_CL5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL6_Pos (6UL) /*!< ER_CL6 (Bit 6) */ + #define R_ICU_PERIERR_CLR1_ER_CL6_Msk (0x40UL) /*!< ER_CL6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL13_Pos (13UL) /*!< ER_CL13 (Bit 13) */ + #define R_ICU_PERIERR_CLR1_ER_CL13_Msk (0x2000UL) /*!< ER_CL13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL15_Pos (15UL) /*!< ER_CL15 (Bit 15) */ + #define R_ICU_PERIERR_CLR1_ER_CL15_Msk (0x8000UL) /*!< ER_CL15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL17_Pos (17UL) /*!< ER_CL17 (Bit 17) */ + #define R_ICU_PERIERR_CLR1_ER_CL17_Msk (0x20000UL) /*!< ER_CL17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL18_Pos (18UL) /*!< ER_CL18 (Bit 18) */ + #define R_ICU_PERIERR_CLR1_ER_CL18_Msk (0x40000UL) /*!< ER_CL18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL19_Pos (19UL) /*!< ER_CL19 (Bit 19) */ + #define R_ICU_PERIERR_CLR1_ER_CL19_Msk (0x80000UL) /*!< ER_CL19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL20_Pos (20UL) /*!< ER_CL20 (Bit 20) */ + #define R_ICU_PERIERR_CLR1_ER_CL20_Msk (0x100000UL) /*!< ER_CL20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL21_Pos (21UL) /*!< ER_CL21 (Bit 21) */ + #define R_ICU_PERIERR_CLR1_ER_CL21_Msk (0x200000UL) /*!< ER_CL21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL22_Pos (22UL) /*!< ER_CL22 (Bit 22) */ + #define R_ICU_PERIERR_CLR1_ER_CL22_Msk (0x400000UL) /*!< ER_CL22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL23_Pos (23UL) /*!< ER_CL23 (Bit 23) */ + #define R_ICU_PERIERR_CLR1_ER_CL23_Msk (0x800000UL) /*!< ER_CL23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL24_Pos (24UL) /*!< ER_CL24 (Bit 24) */ + #define R_ICU_PERIERR_CLR1_ER_CL24_Msk (0x1000000UL) /*!< ER_CL24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL27_Pos (27UL) /*!< ER_CL27 (Bit 27) */ + #define R_ICU_PERIERR_CLR1_ER_CL27_Msk (0x8000000UL) /*!< ER_CL27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL28_Pos (28UL) /*!< ER_CL28 (Bit 28) */ + #define R_ICU_PERIERR_CLR1_ER_CL28_Msk (0x10000000UL) /*!< ER_CL28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL29_Pos (29UL) /*!< ER_CL29 (Bit 29) */ + #define R_ICU_PERIERR_CLR1_ER_CL29_Msk (0x20000000UL) /*!< ER_CL29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL30_Pos (30UL) /*!< ER_CL30 (Bit 30) */ + #define R_ICU_PERIERR_CLR1_ER_CL30_Msk (0x40000000UL) /*!< ER_CL30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL31_Pos (31UL) /*!< ER_CL31 (Bit 31) */ + #define R_ICU_PERIERR_CLR1_ER_CL31_Msk (0x80000000UL) /*!< ER_CL31 (Bitfield-Mask: 0x01) */ +/* ==================================================== CPU0ERR_RSTMSK ===================================================== */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK0_Pos (0UL) /*!< RS_MK0 (Bit 0) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK0_Msk (0x1UL) /*!< RS_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK1_Pos (1UL) /*!< RS_MK1 (Bit 1) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK1_Msk (0x2UL) /*!< RS_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK2_Pos (2UL) /*!< RS_MK2 (Bit 2) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK2_Msk (0x4UL) /*!< RS_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK3_Pos (3UL) /*!< RS_MK3 (Bit 3) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK3_Msk (0x8UL) /*!< RS_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK4_Pos (4UL) /*!< RS_MK4 (Bit 4) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK4_Msk (0x10UL) /*!< RS_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK5_Pos (5UL) /*!< RS_MK5 (Bit 5) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK5_Msk (0x20UL) /*!< RS_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK6_Pos (6UL) /*!< RS_MK6 (Bit 6) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK6_Msk (0x40UL) /*!< RS_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK7_Pos (7UL) /*!< RS_MK7 (Bit 7) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK7_Msk (0x80UL) /*!< RS_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK8_Pos (8UL) /*!< RS_MK8 (Bit 8) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK8_Msk (0x100UL) /*!< RS_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK9_Pos (9UL) /*!< RS_MK9 (Bit 9) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK9_Msk (0x200UL) /*!< RS_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK10_Pos (10UL) /*!< RS_MK10 (Bit 10) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK10_Msk (0x400UL) /*!< RS_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK11_Pos (11UL) /*!< RS_MK11 (Bit 11) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK11_Msk (0x800UL) /*!< RS_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK12_Pos (12UL) /*!< RS_MK12 (Bit 12) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK12_Msk (0x1000UL) /*!< RS_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK13_Pos (13UL) /*!< RS_MK13 (Bit 13) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK13_Msk (0x2000UL) /*!< RS_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK14_Pos (14UL) /*!< RS_MK14 (Bit 14) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK14_Msk (0x4000UL) /*!< RS_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK15_Pos (15UL) /*!< RS_MK15 (Bit 15) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK15_Msk (0x8000UL) /*!< RS_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK16_Pos (16UL) /*!< RS_MK16 (Bit 16) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK16_Msk (0x10000UL) /*!< RS_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK17_Pos (17UL) /*!< RS_MK17 (Bit 17) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK17_Msk (0x20000UL) /*!< RS_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK18_Pos (18UL) /*!< RS_MK18 (Bit 18) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK18_Msk (0x40000UL) /*!< RS_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK19_Pos (19UL) /*!< RS_MK19 (Bit 19) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK19_Msk (0x80000UL) /*!< RS_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK20_Pos (20UL) /*!< RS_MK20 (Bit 20) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK20_Msk (0x100000UL) /*!< RS_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK21_Pos (21UL) /*!< RS_MK21 (Bit 21) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK21_Msk (0x200000UL) /*!< RS_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK22_Pos (22UL) /*!< RS_MK22 (Bit 22) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK22_Msk (0x400000UL) /*!< RS_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK23_Pos (23UL) /*!< RS_MK23 (Bit 23) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK23_Msk (0x800000UL) /*!< RS_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK24_Pos (24UL) /*!< RS_MK24 (Bit 24) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK24_Msk (0x1000000UL) /*!< RS_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK25_Pos (25UL) /*!< RS_MK25 (Bit 25) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK25_Msk (0x2000000UL) /*!< RS_MK25 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_RSTMSK0 ==================================================== */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK0_Pos (0UL) /*!< RS_MK0 (Bit 0) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK0_Msk (0x1UL) /*!< RS_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK1_Pos (1UL) /*!< RS_MK1 (Bit 1) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK1_Msk (0x2UL) /*!< RS_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK2_Pos (2UL) /*!< RS_MK2 (Bit 2) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK2_Msk (0x4UL) /*!< RS_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK3_Pos (3UL) /*!< RS_MK3 (Bit 3) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK3_Msk (0x8UL) /*!< RS_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK4_Pos (4UL) /*!< RS_MK4 (Bit 4) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK4_Msk (0x10UL) /*!< RS_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK5_Pos (5UL) /*!< RS_MK5 (Bit 5) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK5_Msk (0x20UL) /*!< RS_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK6_Pos (6UL) /*!< RS_MK6 (Bit 6) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK6_Msk (0x40UL) /*!< RS_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK7_Pos (7UL) /*!< RS_MK7 (Bit 7) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK7_Msk (0x80UL) /*!< RS_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK9_Pos (9UL) /*!< RS_MK9 (Bit 9) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK9_Msk (0x200UL) /*!< RS_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK10_Pos (10UL) /*!< RS_MK10 (Bit 10) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK10_Msk (0x400UL) /*!< RS_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK11_Pos (11UL) /*!< RS_MK11 (Bit 11) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK11_Msk (0x800UL) /*!< RS_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK12_Pos (12UL) /*!< RS_MK12 (Bit 12) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK12_Msk (0x1000UL) /*!< RS_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK13_Pos (13UL) /*!< RS_MK13 (Bit 13) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK13_Msk (0x2000UL) /*!< RS_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK14_Pos (14UL) /*!< RS_MK14 (Bit 14) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK14_Msk (0x4000UL) /*!< RS_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK15_Pos (15UL) /*!< RS_MK15 (Bit 15) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK15_Msk (0x8000UL) /*!< RS_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK16_Pos (16UL) /*!< RS_MK16 (Bit 16) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK16_Msk (0x10000UL) /*!< RS_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK17_Pos (17UL) /*!< RS_MK17 (Bit 17) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK17_Msk (0x20000UL) /*!< RS_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK18_Pos (18UL) /*!< RS_MK18 (Bit 18) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK18_Msk (0x40000UL) /*!< RS_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK19_Pos (19UL) /*!< RS_MK19 (Bit 19) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK19_Msk (0x80000UL) /*!< RS_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK20_Pos (20UL) /*!< RS_MK20 (Bit 20) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK20_Msk (0x100000UL) /*!< RS_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK21_Pos (21UL) /*!< RS_MK21 (Bit 21) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK21_Msk (0x200000UL) /*!< RS_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK22_Pos (22UL) /*!< RS_MK22 (Bit 22) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK22_Msk (0x400000UL) /*!< RS_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK23_Pos (23UL) /*!< RS_MK23 (Bit 23) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK23_Msk (0x800000UL) /*!< RS_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK24_Pos (24UL) /*!< RS_MK24 (Bit 24) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK24_Msk (0x1000000UL) /*!< RS_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK25_Pos (25UL) /*!< RS_MK25 (Bit 25) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK25_Msk (0x2000000UL) /*!< RS_MK25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK26_Pos (26UL) /*!< RS_MK26 (Bit 26) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK26_Msk (0x4000000UL) /*!< RS_MK26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK27_Pos (27UL) /*!< RS_MK27 (Bit 27) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK27_Msk (0x8000000UL) /*!< RS_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK28_Pos (28UL) /*!< RS_MK28 (Bit 28) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK28_Msk (0x10000000UL) /*!< RS_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK29_Pos (29UL) /*!< RS_MK29 (Bit 29) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK29_Msk (0x20000000UL) /*!< RS_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK30_Pos (30UL) /*!< RS_MK30 (Bit 30) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK30_Msk (0x40000000UL) /*!< RS_MK30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK31_Pos (31UL) /*!< RS_MK31 (Bit 31) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK31_Msk (0x80000000UL) /*!< RS_MK31 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_RSTMSK1 ==================================================== */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK0_Pos (0UL) /*!< RS_MK0 (Bit 0) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK0_Msk (0x1UL) /*!< RS_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK1_Pos (1UL) /*!< RS_MK1 (Bit 1) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK1_Msk (0x2UL) /*!< RS_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK2_Pos (2UL) /*!< RS_MK2 (Bit 2) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK2_Msk (0x4UL) /*!< RS_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK3_Pos (3UL) /*!< RS_MK3 (Bit 3) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK3_Msk (0x8UL) /*!< RS_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK4_Pos (4UL) /*!< RS_MK4 (Bit 4) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK4_Msk (0x10UL) /*!< RS_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK5_Pos (5UL) /*!< RS_MK5 (Bit 5) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK5_Msk (0x20UL) /*!< RS_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK6_Pos (6UL) /*!< RS_MK6 (Bit 6) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK6_Msk (0x40UL) /*!< RS_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK13_Pos (13UL) /*!< RS_MK13 (Bit 13) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK13_Msk (0x2000UL) /*!< RS_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK15_Pos (15UL) /*!< RS_MK15 (Bit 15) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK15_Msk (0x8000UL) /*!< RS_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK17_Pos (17UL) /*!< RS_MK17 (Bit 17) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK17_Msk (0x20000UL) /*!< RS_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK18_Pos (18UL) /*!< RS_MK18 (Bit 18) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK18_Msk (0x40000UL) /*!< RS_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK19_Pos (19UL) /*!< RS_MK19 (Bit 19) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK19_Msk (0x80000UL) /*!< RS_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK20_Pos (20UL) /*!< RS_MK20 (Bit 20) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK20_Msk (0x100000UL) /*!< RS_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK21_Pos (21UL) /*!< RS_MK21 (Bit 21) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK21_Msk (0x200000UL) /*!< RS_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK22_Pos (22UL) /*!< RS_MK22 (Bit 22) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK22_Msk (0x400000UL) /*!< RS_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK23_Pos (23UL) /*!< RS_MK23 (Bit 23) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK23_Msk (0x800000UL) /*!< RS_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK24_Pos (24UL) /*!< RS_MK24 (Bit 24) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK24_Msk (0x1000000UL) /*!< RS_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK27_Pos (27UL) /*!< RS_MK27 (Bit 27) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK27_Msk (0x8000000UL) /*!< RS_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK28_Pos (28UL) /*!< RS_MK28 (Bit 28) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK28_Msk (0x10000000UL) /*!< RS_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK29_Pos (29UL) /*!< RS_MK29 (Bit 29) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK29_Msk (0x20000000UL) /*!< RS_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK30_Pos (30UL) /*!< RS_MK30 (Bit 30) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK30_Msk (0x40000000UL) /*!< RS_MK30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK31_Pos (31UL) /*!< RS_MK31 (Bit 31) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK31_Msk (0x80000000UL) /*!< RS_MK31 (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU0ERR_E0MSK ===================================================== */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK0_Pos (0UL) /*!< E0_MK0 (Bit 0) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK0_Msk (0x1UL) /*!< E0_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK1_Pos (1UL) /*!< E0_MK1 (Bit 1) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK1_Msk (0x2UL) /*!< E0_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK2_Pos (2UL) /*!< E0_MK2 (Bit 2) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK2_Msk (0x4UL) /*!< E0_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK3_Pos (3UL) /*!< E0_MK3 (Bit 3) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK3_Msk (0x8UL) /*!< E0_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK4_Pos (4UL) /*!< E0_MK4 (Bit 4) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK4_Msk (0x10UL) /*!< E0_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK5_Pos (5UL) /*!< E0_MK5 (Bit 5) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK5_Msk (0x20UL) /*!< E0_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK6_Pos (6UL) /*!< E0_MK6 (Bit 6) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK6_Msk (0x40UL) /*!< E0_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK7_Pos (7UL) /*!< E0_MK7 (Bit 7) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK7_Msk (0x80UL) /*!< E0_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK8_Pos (8UL) /*!< E0_MK8 (Bit 8) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK8_Msk (0x100UL) /*!< E0_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK9_Pos (9UL) /*!< E0_MK9 (Bit 9) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK9_Msk (0x200UL) /*!< E0_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK10_Pos (10UL) /*!< E0_MK10 (Bit 10) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK10_Msk (0x400UL) /*!< E0_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK11_Pos (11UL) /*!< E0_MK11 (Bit 11) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK11_Msk (0x800UL) /*!< E0_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK12_Pos (12UL) /*!< E0_MK12 (Bit 12) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK12_Msk (0x1000UL) /*!< E0_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK13_Pos (13UL) /*!< E0_MK13 (Bit 13) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK13_Msk (0x2000UL) /*!< E0_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK14_Pos (14UL) /*!< E0_MK14 (Bit 14) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK14_Msk (0x4000UL) /*!< E0_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK15_Pos (15UL) /*!< E0_MK15 (Bit 15) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK15_Msk (0x8000UL) /*!< E0_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK16_Pos (16UL) /*!< E0_MK16 (Bit 16) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK16_Msk (0x10000UL) /*!< E0_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK17_Pos (17UL) /*!< E0_MK17 (Bit 17) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK17_Msk (0x20000UL) /*!< E0_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK18_Pos (18UL) /*!< E0_MK18 (Bit 18) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK18_Msk (0x40000UL) /*!< E0_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK19_Pos (19UL) /*!< E0_MK19 (Bit 19) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK19_Msk (0x80000UL) /*!< E0_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK20_Pos (20UL) /*!< E0_MK20 (Bit 20) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK20_Msk (0x100000UL) /*!< E0_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK21_Pos (21UL) /*!< E0_MK21 (Bit 21) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK21_Msk (0x200000UL) /*!< E0_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK22_Pos (22UL) /*!< E0_MK22 (Bit 22) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK22_Msk (0x400000UL) /*!< E0_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK23_Pos (23UL) /*!< E0_MK23 (Bit 23) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK23_Msk (0x800000UL) /*!< E0_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK24_Pos (24UL) /*!< E0_MK24 (Bit 24) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK24_Msk (0x1000000UL) /*!< E0_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK25_Pos (25UL) /*!< E0_MK25 (Bit 25) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK25_Msk (0x2000000UL) /*!< E0_MK25 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E0MSK0 ===================================================== */ + #define R_ICU_PERIERR_E0MSK0_E0_MK0_Pos (0UL) /*!< E0_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK0_Msk (0x1UL) /*!< E0_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK1_Pos (1UL) /*!< E0_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK1_Msk (0x2UL) /*!< E0_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK2_Pos (2UL) /*!< E0_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK2_Msk (0x4UL) /*!< E0_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK3_Pos (3UL) /*!< E0_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK3_Msk (0x8UL) /*!< E0_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK4_Pos (4UL) /*!< E0_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK4_Msk (0x10UL) /*!< E0_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK5_Pos (5UL) /*!< E0_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK5_Msk (0x20UL) /*!< E0_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK6_Pos (6UL) /*!< E0_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK6_Msk (0x40UL) /*!< E0_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK7_Pos (7UL) /*!< E0_MK7 (Bit 7) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK7_Msk (0x80UL) /*!< E0_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK9_Pos (9UL) /*!< E0_MK9 (Bit 9) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK9_Msk (0x200UL) /*!< E0_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK10_Pos (10UL) /*!< E0_MK10 (Bit 10) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK10_Msk (0x400UL) /*!< E0_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK11_Pos (11UL) /*!< E0_MK11 (Bit 11) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK11_Msk (0x800UL) /*!< E0_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK12_Pos (12UL) /*!< E0_MK12 (Bit 12) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK12_Msk (0x1000UL) /*!< E0_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK13_Pos (13UL) /*!< E0_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK13_Msk (0x2000UL) /*!< E0_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK14_Pos (14UL) /*!< E0_MK14 (Bit 14) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK14_Msk (0x4000UL) /*!< E0_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK15_Pos (15UL) /*!< E0_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK15_Msk (0x8000UL) /*!< E0_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK16_Pos (16UL) /*!< E0_MK16 (Bit 16) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK16_Msk (0x10000UL) /*!< E0_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK17_Pos (17UL) /*!< E0_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK17_Msk (0x20000UL) /*!< E0_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK18_Pos (18UL) /*!< E0_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK18_Msk (0x40000UL) /*!< E0_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK19_Pos (19UL) /*!< E0_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK19_Msk (0x80000UL) /*!< E0_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK20_Pos (20UL) /*!< E0_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK20_Msk (0x100000UL) /*!< E0_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK21_Pos (21UL) /*!< E0_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK21_Msk (0x200000UL) /*!< E0_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK22_Pos (22UL) /*!< E0_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK22_Msk (0x400000UL) /*!< E0_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK23_Pos (23UL) /*!< E0_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK23_Msk (0x800000UL) /*!< E0_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK24_Pos (24UL) /*!< E0_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK24_Msk (0x1000000UL) /*!< E0_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK25_Pos (25UL) /*!< E0_MK25 (Bit 25) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK25_Msk (0x2000000UL) /*!< E0_MK25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK26_Pos (26UL) /*!< E0_MK26 (Bit 26) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK26_Msk (0x4000000UL) /*!< E0_MK26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK27_Pos (27UL) /*!< E0_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK27_Msk (0x8000000UL) /*!< E0_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK28_Pos (28UL) /*!< E0_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK28_Msk (0x10000000UL) /*!< E0_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK29_Pos (29UL) /*!< E0_MK29 (Bit 29) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK29_Msk (0x20000000UL) /*!< E0_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK30_Pos (30UL) /*!< E0_MK30 (Bit 30) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK30_Msk (0x40000000UL) /*!< E0_MK30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK31_Pos (31UL) /*!< E0_MK31 (Bit 31) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK31_Msk (0x80000000UL) /*!< E0_MK31 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E0MSK1 ===================================================== */ + #define R_ICU_PERIERR_E0MSK1_E0_MK0_Pos (0UL) /*!< E0_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK0_Msk (0x1UL) /*!< E0_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK1_Pos (1UL) /*!< E0_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK1_Msk (0x2UL) /*!< E0_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK2_Pos (2UL) /*!< E0_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK2_Msk (0x4UL) /*!< E0_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK3_Pos (3UL) /*!< E0_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK3_Msk (0x8UL) /*!< E0_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK4_Pos (4UL) /*!< E0_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK4_Msk (0x10UL) /*!< E0_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK5_Pos (5UL) /*!< E0_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK5_Msk (0x20UL) /*!< E0_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK6_Pos (6UL) /*!< E0_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK6_Msk (0x40UL) /*!< E0_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK13_Pos (13UL) /*!< E0_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK13_Msk (0x2000UL) /*!< E0_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK15_Pos (15UL) /*!< E0_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK15_Msk (0x8000UL) /*!< E0_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK17_Pos (17UL) /*!< E0_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK17_Msk (0x20000UL) /*!< E0_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK18_Pos (18UL) /*!< E0_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK18_Msk (0x40000UL) /*!< E0_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK19_Pos (19UL) /*!< E0_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK19_Msk (0x80000UL) /*!< E0_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK20_Pos (20UL) /*!< E0_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK20_Msk (0x100000UL) /*!< E0_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK21_Pos (21UL) /*!< E0_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK21_Msk (0x200000UL) /*!< E0_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK22_Pos (22UL) /*!< E0_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK22_Msk (0x400000UL) /*!< E0_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK23_Pos (23UL) /*!< E0_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK23_Msk (0x800000UL) /*!< E0_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK24_Pos (24UL) /*!< E0_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK24_Msk (0x1000000UL) /*!< E0_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK27_Pos (27UL) /*!< E0_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK27_Msk (0x8000000UL) /*!< E0_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK28_Pos (28UL) /*!< E0_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK28_Msk (0x10000000UL) /*!< E0_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK29_Pos (29UL) /*!< E0_MK29 (Bit 29) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK29_Msk (0x20000000UL) /*!< E0_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK30_Pos (30UL) /*!< E0_MK30 (Bit 30) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK30_Msk (0x40000000UL) /*!< E0_MK30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK31_Pos (31UL) /*!< E0_MK31 (Bit 31) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK31_Msk (0x80000000UL) /*!< E0_MK31 (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU0ERR_E1MSK ===================================================== */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK0_Pos (0UL) /*!< E1_MK0 (Bit 0) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK0_Msk (0x1UL) /*!< E1_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK1_Pos (1UL) /*!< E1_MK1 (Bit 1) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK1_Msk (0x2UL) /*!< E1_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK2_Pos (2UL) /*!< E1_MK2 (Bit 2) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK2_Msk (0x4UL) /*!< E1_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK3_Pos (3UL) /*!< E1_MK3 (Bit 3) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK3_Msk (0x8UL) /*!< E1_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK4_Pos (4UL) /*!< E1_MK4 (Bit 4) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK4_Msk (0x10UL) /*!< E1_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK5_Pos (5UL) /*!< E1_MK5 (Bit 5) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK5_Msk (0x20UL) /*!< E1_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK6_Pos (6UL) /*!< E1_MK6 (Bit 6) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK6_Msk (0x40UL) /*!< E1_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK7_Pos (7UL) /*!< E1_MK7 (Bit 7) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK7_Msk (0x80UL) /*!< E1_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK8_Pos (8UL) /*!< E1_MK8 (Bit 8) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK8_Msk (0x100UL) /*!< E1_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK9_Pos (9UL) /*!< E1_MK9 (Bit 9) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK9_Msk (0x200UL) /*!< E1_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK10_Pos (10UL) /*!< E1_MK10 (Bit 10) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK10_Msk (0x400UL) /*!< E1_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK11_Pos (11UL) /*!< E1_MK11 (Bit 11) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK11_Msk (0x800UL) /*!< E1_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK12_Pos (12UL) /*!< E1_MK12 (Bit 12) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK12_Msk (0x1000UL) /*!< E1_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK13_Pos (13UL) /*!< E1_MK13 (Bit 13) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK13_Msk (0x2000UL) /*!< E1_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK14_Pos (14UL) /*!< E1_MK14 (Bit 14) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK14_Msk (0x4000UL) /*!< E1_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK15_Pos (15UL) /*!< E1_MK15 (Bit 15) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK15_Msk (0x8000UL) /*!< E1_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK16_Pos (16UL) /*!< E1_MK16 (Bit 16) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK16_Msk (0x10000UL) /*!< E1_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK17_Pos (17UL) /*!< E1_MK17 (Bit 17) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK17_Msk (0x20000UL) /*!< E1_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK18_Pos (18UL) /*!< E1_MK18 (Bit 18) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK18_Msk (0x40000UL) /*!< E1_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK19_Pos (19UL) /*!< E1_MK19 (Bit 19) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK19_Msk (0x80000UL) /*!< E1_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK20_Pos (20UL) /*!< E1_MK20 (Bit 20) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK20_Msk (0x100000UL) /*!< E1_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK21_Pos (21UL) /*!< E1_MK21 (Bit 21) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK21_Msk (0x200000UL) /*!< E1_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK22_Pos (22UL) /*!< E1_MK22 (Bit 22) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK22_Msk (0x400000UL) /*!< E1_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK23_Pos (23UL) /*!< E1_MK23 (Bit 23) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK23_Msk (0x800000UL) /*!< E1_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK24_Pos (24UL) /*!< E1_MK24 (Bit 24) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK24_Msk (0x1000000UL) /*!< E1_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK25_Pos (25UL) /*!< E1_MK25 (Bit 25) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK25_Msk (0x2000000UL) /*!< E1_MK25 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E1MSK0 ===================================================== */ + #define R_ICU_PERIERR_E1MSK0_E1_MK0_Pos (0UL) /*!< E1_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK0_Msk (0x1UL) /*!< E1_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK1_Pos (1UL) /*!< E1_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK1_Msk (0x2UL) /*!< E1_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK2_Pos (2UL) /*!< E1_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK2_Msk (0x4UL) /*!< E1_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK3_Pos (3UL) /*!< E1_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK3_Msk (0x8UL) /*!< E1_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK4_Pos (4UL) /*!< E1_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK4_Msk (0x10UL) /*!< E1_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK5_Pos (5UL) /*!< E1_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK5_Msk (0x20UL) /*!< E1_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK6_Pos (6UL) /*!< E1_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK6_Msk (0x40UL) /*!< E1_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK7_Pos (7UL) /*!< E1_MK7 (Bit 7) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK7_Msk (0x80UL) /*!< E1_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK9_Pos (9UL) /*!< E1_MK9 (Bit 9) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK9_Msk (0x200UL) /*!< E1_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK10_Pos (10UL) /*!< E1_MK10 (Bit 10) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK10_Msk (0x400UL) /*!< E1_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK11_Pos (11UL) /*!< E1_MK11 (Bit 11) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK11_Msk (0x800UL) /*!< E1_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK12_Pos (12UL) /*!< E1_MK12 (Bit 12) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK12_Msk (0x1000UL) /*!< E1_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK13_Pos (13UL) /*!< E1_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK13_Msk (0x2000UL) /*!< E1_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK14_Pos (14UL) /*!< E1_MK14 (Bit 14) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK14_Msk (0x4000UL) /*!< E1_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK15_Pos (15UL) /*!< E1_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK15_Msk (0x8000UL) /*!< E1_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK16_Pos (16UL) /*!< E1_MK16 (Bit 16) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK16_Msk (0x10000UL) /*!< E1_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK17_Pos (17UL) /*!< E1_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK17_Msk (0x20000UL) /*!< E1_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK18_Pos (18UL) /*!< E1_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK18_Msk (0x40000UL) /*!< E1_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK19_Pos (19UL) /*!< E1_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK19_Msk (0x80000UL) /*!< E1_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK20_Pos (20UL) /*!< E1_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK20_Msk (0x100000UL) /*!< E1_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK21_Pos (21UL) /*!< E1_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK21_Msk (0x200000UL) /*!< E1_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK22_Pos (22UL) /*!< E1_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK22_Msk (0x400000UL) /*!< E1_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK23_Pos (23UL) /*!< E1_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK23_Msk (0x800000UL) /*!< E1_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK24_Pos (24UL) /*!< E1_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK24_Msk (0x1000000UL) /*!< E1_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK25_Pos (25UL) /*!< E1_MK25 (Bit 25) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK25_Msk (0x2000000UL) /*!< E1_MK25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK26_Pos (26UL) /*!< E1_MK26 (Bit 26) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK26_Msk (0x4000000UL) /*!< E1_MK26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK27_Pos (27UL) /*!< E1_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK27_Msk (0x8000000UL) /*!< E1_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK28_Pos (28UL) /*!< E1_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK28_Msk (0x10000000UL) /*!< E1_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK29_Pos (29UL) /*!< E1_MK29 (Bit 29) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK29_Msk (0x20000000UL) /*!< E1_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK30_Pos (30UL) /*!< E1_MK30 (Bit 30) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK30_Msk (0x40000000UL) /*!< E1_MK30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK31_Pos (31UL) /*!< E1_MK31 (Bit 31) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK31_Msk (0x80000000UL) /*!< E1_MK31 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E1MSK1 ===================================================== */ + #define R_ICU_PERIERR_E1MSK1_E1_MK0_Pos (0UL) /*!< E1_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK0_Msk (0x1UL) /*!< E1_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK1_Pos (1UL) /*!< E1_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK1_Msk (0x2UL) /*!< E1_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK2_Pos (2UL) /*!< E1_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK2_Msk (0x4UL) /*!< E1_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK3_Pos (3UL) /*!< E1_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK3_Msk (0x8UL) /*!< E1_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK4_Pos (4UL) /*!< E1_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK4_Msk (0x10UL) /*!< E1_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK5_Pos (5UL) /*!< E1_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK5_Msk (0x20UL) /*!< E1_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK6_Pos (6UL) /*!< E1_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK6_Msk (0x40UL) /*!< E1_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK13_Pos (13UL) /*!< E1_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK13_Msk (0x2000UL) /*!< E1_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK15_Pos (15UL) /*!< E1_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK15_Msk (0x8000UL) /*!< E1_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK17_Pos (17UL) /*!< E1_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK17_Msk (0x20000UL) /*!< E1_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK18_Pos (18UL) /*!< E1_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK18_Msk (0x40000UL) /*!< E1_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK19_Pos (19UL) /*!< E1_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK19_Msk (0x80000UL) /*!< E1_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK20_Pos (20UL) /*!< E1_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK20_Msk (0x100000UL) /*!< E1_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK21_Pos (21UL) /*!< E1_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK21_Msk (0x200000UL) /*!< E1_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK22_Pos (22UL) /*!< E1_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK22_Msk (0x400000UL) /*!< E1_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK23_Pos (23UL) /*!< E1_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK23_Msk (0x800000UL) /*!< E1_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK24_Pos (24UL) /*!< E1_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK24_Msk (0x1000000UL) /*!< E1_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK27_Pos (27UL) /*!< E1_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK27_Msk (0x8000000UL) /*!< E1_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK28_Pos (28UL) /*!< E1_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK28_Msk (0x10000000UL) /*!< E1_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK29_Pos (29UL) /*!< E1_MK29 (Bit 29) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK29_Msk (0x20000000UL) /*!< E1_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK30_Pos (30UL) /*!< E1_MK30 (Bit 30) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK30_Msk (0x40000000UL) /*!< E1_MK30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK31_Pos (31UL) /*!< E1_MK31 (Bit 31) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK31_Msk (0x80000000UL) /*!< E1_MK31 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_STAT2 ===================================================== */ + #define R_ICU_PERIERR_STAT2_ER_ST0_Pos (0UL) /*!< ER_ST0 (Bit 0) */ + #define R_ICU_PERIERR_STAT2_ER_ST0_Msk (0x1UL) /*!< ER_ST0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST1_Pos (1UL) /*!< ER_ST1 (Bit 1) */ + #define R_ICU_PERIERR_STAT2_ER_ST1_Msk (0x2UL) /*!< ER_ST1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST2_Pos (2UL) /*!< ER_ST2 (Bit 2) */ + #define R_ICU_PERIERR_STAT2_ER_ST2_Msk (0x4UL) /*!< ER_ST2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST3_Pos (3UL) /*!< ER_ST3 (Bit 3) */ + #define R_ICU_PERIERR_STAT2_ER_ST3_Msk (0x8UL) /*!< ER_ST3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST4_Pos (4UL) /*!< ER_ST4 (Bit 4) */ + #define R_ICU_PERIERR_STAT2_ER_ST4_Msk (0x10UL) /*!< ER_ST4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST5_Pos (5UL) /*!< ER_ST5 (Bit 5) */ + #define R_ICU_PERIERR_STAT2_ER_ST5_Msk (0x20UL) /*!< ER_ST5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST6_Pos (6UL) /*!< ER_ST6 (Bit 6) */ + #define R_ICU_PERIERR_STAT2_ER_ST6_Msk (0x40UL) /*!< ER_ST6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST7_Pos (7UL) /*!< ER_ST7 (Bit 7) */ + #define R_ICU_PERIERR_STAT2_ER_ST7_Msk (0x80UL) /*!< ER_ST7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST8_Pos (8UL) /*!< ER_ST8 (Bit 8) */ + #define R_ICU_PERIERR_STAT2_ER_ST8_Msk (0x100UL) /*!< ER_ST8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST9_Pos (9UL) /*!< ER_ST9 (Bit 9) */ + #define R_ICU_PERIERR_STAT2_ER_ST9_Msk (0x200UL) /*!< ER_ST9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST10_Pos (10UL) /*!< ER_ST10 (Bit 10) */ + #define R_ICU_PERIERR_STAT2_ER_ST10_Msk (0x400UL) /*!< ER_ST10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST11_Pos (11UL) /*!< ER_ST11 (Bit 11) */ + #define R_ICU_PERIERR_STAT2_ER_ST11_Msk (0x800UL) /*!< ER_ST11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST12_Pos (12UL) /*!< ER_ST12 (Bit 12) */ + #define R_ICU_PERIERR_STAT2_ER_ST12_Msk (0x1000UL) /*!< ER_ST12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST13_Pos (13UL) /*!< ER_ST13 (Bit 13) */ + #define R_ICU_PERIERR_STAT2_ER_ST13_Msk (0x2000UL) /*!< ER_ST13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST14_Pos (14UL) /*!< ER_ST14 (Bit 14) */ + #define R_ICU_PERIERR_STAT2_ER_ST14_Msk (0x4000UL) /*!< ER_ST14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST15_Pos (15UL) /*!< ER_ST15 (Bit 15) */ + #define R_ICU_PERIERR_STAT2_ER_ST15_Msk (0x8000UL) /*!< ER_ST15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST16_Pos (16UL) /*!< ER_ST16 (Bit 16) */ + #define R_ICU_PERIERR_STAT2_ER_ST16_Msk (0x10000UL) /*!< ER_ST16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST17_Pos (17UL) /*!< ER_ST17 (Bit 17) */ + #define R_ICU_PERIERR_STAT2_ER_ST17_Msk (0x20000UL) /*!< ER_ST17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST18_Pos (18UL) /*!< ER_ST18 (Bit 18) */ + #define R_ICU_PERIERR_STAT2_ER_ST18_Msk (0x40000UL) /*!< ER_ST18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST19_Pos (19UL) /*!< ER_ST19 (Bit 19) */ + #define R_ICU_PERIERR_STAT2_ER_ST19_Msk (0x80000UL) /*!< ER_ST19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST20_Pos (20UL) /*!< ER_ST20 (Bit 20) */ + #define R_ICU_PERIERR_STAT2_ER_ST20_Msk (0x100000UL) /*!< ER_ST20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST21_Pos (21UL) /*!< ER_ST21 (Bit 21) */ + #define R_ICU_PERIERR_STAT2_ER_ST21_Msk (0x200000UL) /*!< ER_ST21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST22_Pos (22UL) /*!< ER_ST22 (Bit 22) */ + #define R_ICU_PERIERR_STAT2_ER_ST22_Msk (0x400000UL) /*!< ER_ST22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST23_Pos (23UL) /*!< ER_ST23 (Bit 23) */ + #define R_ICU_PERIERR_STAT2_ER_ST23_Msk (0x800000UL) /*!< ER_ST23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST24_Pos (24UL) /*!< ER_ST24 (Bit 24) */ + #define R_ICU_PERIERR_STAT2_ER_ST24_Msk (0x1000000UL) /*!< ER_ST24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST25_Pos (25UL) /*!< ER_ST25 (Bit 25) */ + #define R_ICU_PERIERR_STAT2_ER_ST25_Msk (0x2000000UL) /*!< ER_ST25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST26_Pos (26UL) /*!< ER_ST26 (Bit 26) */ + #define R_ICU_PERIERR_STAT2_ER_ST26_Msk (0x4000000UL) /*!< ER_ST26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST27_Pos (27UL) /*!< ER_ST27 (Bit 27) */ + #define R_ICU_PERIERR_STAT2_ER_ST27_Msk (0x8000000UL) /*!< ER_ST27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST28_Pos (28UL) /*!< ER_ST28 (Bit 28) */ + #define R_ICU_PERIERR_STAT2_ER_ST28_Msk (0x10000000UL) /*!< ER_ST28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST29_Pos (29UL) /*!< ER_ST29 (Bit 29) */ + #define R_ICU_PERIERR_STAT2_ER_ST29_Msk (0x20000000UL) /*!< ER_ST29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST30_Pos (30UL) /*!< ER_ST30 (Bit 30) */ + #define R_ICU_PERIERR_STAT2_ER_ST30_Msk (0x40000000UL) /*!< ER_ST30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT2_ER_ST31_Pos (31UL) /*!< ER_ST31 (Bit 31) */ + #define R_ICU_PERIERR_STAT2_ER_ST31_Msk (0x80000000UL) /*!< ER_ST31 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_STAT3 ===================================================== */ + #define R_ICU_PERIERR_STAT3_ER_ST0_Pos (0UL) /*!< ER_ST0 (Bit 0) */ + #define R_ICU_PERIERR_STAT3_ER_ST0_Msk (0x1UL) /*!< ER_ST0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST1_Pos (1UL) /*!< ER_ST1 (Bit 1) */ + #define R_ICU_PERIERR_STAT3_ER_ST1_Msk (0x2UL) /*!< ER_ST1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST2_Pos (2UL) /*!< ER_ST2 (Bit 2) */ + #define R_ICU_PERIERR_STAT3_ER_ST2_Msk (0x4UL) /*!< ER_ST2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST3_Pos (3UL) /*!< ER_ST3 (Bit 3) */ + #define R_ICU_PERIERR_STAT3_ER_ST3_Msk (0x8UL) /*!< ER_ST3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST4_Pos (4UL) /*!< ER_ST4 (Bit 4) */ + #define R_ICU_PERIERR_STAT3_ER_ST4_Msk (0x10UL) /*!< ER_ST4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST5_Pos (5UL) /*!< ER_ST5 (Bit 5) */ + #define R_ICU_PERIERR_STAT3_ER_ST5_Msk (0x20UL) /*!< ER_ST5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST6_Pos (6UL) /*!< ER_ST6 (Bit 6) */ + #define R_ICU_PERIERR_STAT3_ER_ST6_Msk (0x40UL) /*!< ER_ST6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST7_Pos (7UL) /*!< ER_ST7 (Bit 7) */ + #define R_ICU_PERIERR_STAT3_ER_ST7_Msk (0x80UL) /*!< ER_ST7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST8_Pos (8UL) /*!< ER_ST8 (Bit 8) */ + #define R_ICU_PERIERR_STAT3_ER_ST8_Msk (0x100UL) /*!< ER_ST8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST9_Pos (9UL) /*!< ER_ST9 (Bit 9) */ + #define R_ICU_PERIERR_STAT3_ER_ST9_Msk (0x200UL) /*!< ER_ST9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST10_Pos (10UL) /*!< ER_ST10 (Bit 10) */ + #define R_ICU_PERIERR_STAT3_ER_ST10_Msk (0x400UL) /*!< ER_ST10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST11_Pos (11UL) /*!< ER_ST11 (Bit 11) */ + #define R_ICU_PERIERR_STAT3_ER_ST11_Msk (0x800UL) /*!< ER_ST11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST12_Pos (12UL) /*!< ER_ST12 (Bit 12) */ + #define R_ICU_PERIERR_STAT3_ER_ST12_Msk (0x1000UL) /*!< ER_ST12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST13_Pos (13UL) /*!< ER_ST13 (Bit 13) */ + #define R_ICU_PERIERR_STAT3_ER_ST13_Msk (0x2000UL) /*!< ER_ST13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST14_Pos (14UL) /*!< ER_ST14 (Bit 14) */ + #define R_ICU_PERIERR_STAT3_ER_ST14_Msk (0x4000UL) /*!< ER_ST14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST15_Pos (15UL) /*!< ER_ST15 (Bit 15) */ + #define R_ICU_PERIERR_STAT3_ER_ST15_Msk (0x8000UL) /*!< ER_ST15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST16_Pos (16UL) /*!< ER_ST16 (Bit 16) */ + #define R_ICU_PERIERR_STAT3_ER_ST16_Msk (0x10000UL) /*!< ER_ST16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST17_Pos (17UL) /*!< ER_ST17 (Bit 17) */ + #define R_ICU_PERIERR_STAT3_ER_ST17_Msk (0x20000UL) /*!< ER_ST17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST18_Pos (18UL) /*!< ER_ST18 (Bit 18) */ + #define R_ICU_PERIERR_STAT3_ER_ST18_Msk (0x40000UL) /*!< ER_ST18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST19_Pos (19UL) /*!< ER_ST19 (Bit 19) */ + #define R_ICU_PERIERR_STAT3_ER_ST19_Msk (0x80000UL) /*!< ER_ST19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST20_Pos (20UL) /*!< ER_ST20 (Bit 20) */ + #define R_ICU_PERIERR_STAT3_ER_ST20_Msk (0x100000UL) /*!< ER_ST20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST21_Pos (21UL) /*!< ER_ST21 (Bit 21) */ + #define R_ICU_PERIERR_STAT3_ER_ST21_Msk (0x200000UL) /*!< ER_ST21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST22_Pos (22UL) /*!< ER_ST22 (Bit 22) */ + #define R_ICU_PERIERR_STAT3_ER_ST22_Msk (0x400000UL) /*!< ER_ST22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST23_Pos (23UL) /*!< ER_ST23 (Bit 23) */ + #define R_ICU_PERIERR_STAT3_ER_ST23_Msk (0x800000UL) /*!< ER_ST23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST24_Pos (24UL) /*!< ER_ST24 (Bit 24) */ + #define R_ICU_PERIERR_STAT3_ER_ST24_Msk (0x1000000UL) /*!< ER_ST24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST25_Pos (25UL) /*!< ER_ST25 (Bit 25) */ + #define R_ICU_PERIERR_STAT3_ER_ST25_Msk (0x2000000UL) /*!< ER_ST25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST26_Pos (26UL) /*!< ER_ST26 (Bit 26) */ + #define R_ICU_PERIERR_STAT3_ER_ST26_Msk (0x4000000UL) /*!< ER_ST26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST27_Pos (27UL) /*!< ER_ST27 (Bit 27) */ + #define R_ICU_PERIERR_STAT3_ER_ST27_Msk (0x8000000UL) /*!< ER_ST27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST28_Pos (28UL) /*!< ER_ST28 (Bit 28) */ + #define R_ICU_PERIERR_STAT3_ER_ST28_Msk (0x10000000UL) /*!< ER_ST28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST29_Pos (29UL) /*!< ER_ST29 (Bit 29) */ + #define R_ICU_PERIERR_STAT3_ER_ST29_Msk (0x20000000UL) /*!< ER_ST29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT3_ER_ST30_Pos (30UL) /*!< ER_ST30 (Bit 30) */ + #define R_ICU_PERIERR_STAT3_ER_ST30_Msk (0x40000000UL) /*!< ER_ST30 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_CLR2 ====================================================== */ + #define R_ICU_PERIERR_CLR2_ER_CL0_Pos (0UL) /*!< ER_CL0 (Bit 0) */ + #define R_ICU_PERIERR_CLR2_ER_CL0_Msk (0x1UL) /*!< ER_CL0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL1_Pos (1UL) /*!< ER_CL1 (Bit 1) */ + #define R_ICU_PERIERR_CLR2_ER_CL1_Msk (0x2UL) /*!< ER_CL1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL2_Pos (2UL) /*!< ER_CL2 (Bit 2) */ + #define R_ICU_PERIERR_CLR2_ER_CL2_Msk (0x4UL) /*!< ER_CL2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL3_Pos (3UL) /*!< ER_CL3 (Bit 3) */ + #define R_ICU_PERIERR_CLR2_ER_CL3_Msk (0x8UL) /*!< ER_CL3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL4_Pos (4UL) /*!< ER_CL4 (Bit 4) */ + #define R_ICU_PERIERR_CLR2_ER_CL4_Msk (0x10UL) /*!< ER_CL4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL5_Pos (5UL) /*!< ER_CL5 (Bit 5) */ + #define R_ICU_PERIERR_CLR2_ER_CL5_Msk (0x20UL) /*!< ER_CL5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL6_Pos (6UL) /*!< ER_CL6 (Bit 6) */ + #define R_ICU_PERIERR_CLR2_ER_CL6_Msk (0x40UL) /*!< ER_CL6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL7_Pos (7UL) /*!< ER_CL7 (Bit 7) */ + #define R_ICU_PERIERR_CLR2_ER_CL7_Msk (0x80UL) /*!< ER_CL7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL8_Pos (8UL) /*!< ER_CL8 (Bit 8) */ + #define R_ICU_PERIERR_CLR2_ER_CL8_Msk (0x100UL) /*!< ER_CL8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL9_Pos (9UL) /*!< ER_CL9 (Bit 9) */ + #define R_ICU_PERIERR_CLR2_ER_CL9_Msk (0x200UL) /*!< ER_CL9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL10_Pos (10UL) /*!< ER_CL10 (Bit 10) */ + #define R_ICU_PERIERR_CLR2_ER_CL10_Msk (0x400UL) /*!< ER_CL10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL11_Pos (11UL) /*!< ER_CL11 (Bit 11) */ + #define R_ICU_PERIERR_CLR2_ER_CL11_Msk (0x800UL) /*!< ER_CL11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL12_Pos (12UL) /*!< ER_CL12 (Bit 12) */ + #define R_ICU_PERIERR_CLR2_ER_CL12_Msk (0x1000UL) /*!< ER_CL12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL13_Pos (13UL) /*!< ER_CL13 (Bit 13) */ + #define R_ICU_PERIERR_CLR2_ER_CL13_Msk (0x2000UL) /*!< ER_CL13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL14_Pos (14UL) /*!< ER_CL14 (Bit 14) */ + #define R_ICU_PERIERR_CLR2_ER_CL14_Msk (0x4000UL) /*!< ER_CL14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL15_Pos (15UL) /*!< ER_CL15 (Bit 15) */ + #define R_ICU_PERIERR_CLR2_ER_CL15_Msk (0x8000UL) /*!< ER_CL15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL16_Pos (16UL) /*!< ER_CL16 (Bit 16) */ + #define R_ICU_PERIERR_CLR2_ER_CL16_Msk (0x10000UL) /*!< ER_CL16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL17_Pos (17UL) /*!< ER_CL17 (Bit 17) */ + #define R_ICU_PERIERR_CLR2_ER_CL17_Msk (0x20000UL) /*!< ER_CL17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL18_Pos (18UL) /*!< ER_CL18 (Bit 18) */ + #define R_ICU_PERIERR_CLR2_ER_CL18_Msk (0x40000UL) /*!< ER_CL18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL19_Pos (19UL) /*!< ER_CL19 (Bit 19) */ + #define R_ICU_PERIERR_CLR2_ER_CL19_Msk (0x80000UL) /*!< ER_CL19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL20_Pos (20UL) /*!< ER_CL20 (Bit 20) */ + #define R_ICU_PERIERR_CLR2_ER_CL20_Msk (0x100000UL) /*!< ER_CL20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL21_Pos (21UL) /*!< ER_CL21 (Bit 21) */ + #define R_ICU_PERIERR_CLR2_ER_CL21_Msk (0x200000UL) /*!< ER_CL21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL22_Pos (22UL) /*!< ER_CL22 (Bit 22) */ + #define R_ICU_PERIERR_CLR2_ER_CL22_Msk (0x400000UL) /*!< ER_CL22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL23_Pos (23UL) /*!< ER_CL23 (Bit 23) */ + #define R_ICU_PERIERR_CLR2_ER_CL23_Msk (0x800000UL) /*!< ER_CL23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL24_Pos (24UL) /*!< ER_CL24 (Bit 24) */ + #define R_ICU_PERIERR_CLR2_ER_CL24_Msk (0x1000000UL) /*!< ER_CL24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL25_Pos (25UL) /*!< ER_CL25 (Bit 25) */ + #define R_ICU_PERIERR_CLR2_ER_CL25_Msk (0x2000000UL) /*!< ER_CL25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL26_Pos (26UL) /*!< ER_CL26 (Bit 26) */ + #define R_ICU_PERIERR_CLR2_ER_CL26_Msk (0x4000000UL) /*!< ER_CL26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL27_Pos (27UL) /*!< ER_CL27 (Bit 27) */ + #define R_ICU_PERIERR_CLR2_ER_CL27_Msk (0x8000000UL) /*!< ER_CL27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL28_Pos (28UL) /*!< ER_CL28 (Bit 28) */ + #define R_ICU_PERIERR_CLR2_ER_CL28_Msk (0x10000000UL) /*!< ER_CL28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL29_Pos (29UL) /*!< ER_CL29 (Bit 29) */ + #define R_ICU_PERIERR_CLR2_ER_CL29_Msk (0x20000000UL) /*!< ER_CL29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL30_Pos (30UL) /*!< ER_CL30 (Bit 30) */ + #define R_ICU_PERIERR_CLR2_ER_CL30_Msk (0x40000000UL) /*!< ER_CL30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR2_ER_CL31_Pos (31UL) /*!< ER_CL31 (Bit 31) */ + #define R_ICU_PERIERR_CLR2_ER_CL31_Msk (0x80000000UL) /*!< ER_CL31 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_CLR3 ====================================================== */ + #define R_ICU_PERIERR_CLR3_ER_CL0_Pos (0UL) /*!< ER_CL0 (Bit 0) */ + #define R_ICU_PERIERR_CLR3_ER_CL0_Msk (0x1UL) /*!< ER_CL0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL1_Pos (1UL) /*!< ER_CL1 (Bit 1) */ + #define R_ICU_PERIERR_CLR3_ER_CL1_Msk (0x2UL) /*!< ER_CL1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL2_Pos (2UL) /*!< ER_CL2 (Bit 2) */ + #define R_ICU_PERIERR_CLR3_ER_CL2_Msk (0x4UL) /*!< ER_CL2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL3_Pos (3UL) /*!< ER_CL3 (Bit 3) */ + #define R_ICU_PERIERR_CLR3_ER_CL3_Msk (0x8UL) /*!< ER_CL3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL4_Pos (4UL) /*!< ER_CL4 (Bit 4) */ + #define R_ICU_PERIERR_CLR3_ER_CL4_Msk (0x10UL) /*!< ER_CL4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL5_Pos (5UL) /*!< ER_CL5 (Bit 5) */ + #define R_ICU_PERIERR_CLR3_ER_CL5_Msk (0x20UL) /*!< ER_CL5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL6_Pos (6UL) /*!< ER_CL6 (Bit 6) */ + #define R_ICU_PERIERR_CLR3_ER_CL6_Msk (0x40UL) /*!< ER_CL6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL7_Pos (7UL) /*!< ER_CL7 (Bit 7) */ + #define R_ICU_PERIERR_CLR3_ER_CL7_Msk (0x80UL) /*!< ER_CL7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL8_Pos (8UL) /*!< ER_CL8 (Bit 8) */ + #define R_ICU_PERIERR_CLR3_ER_CL8_Msk (0x100UL) /*!< ER_CL8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL9_Pos (9UL) /*!< ER_CL9 (Bit 9) */ + #define R_ICU_PERIERR_CLR3_ER_CL9_Msk (0x200UL) /*!< ER_CL9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL10_Pos (10UL) /*!< ER_CL10 (Bit 10) */ + #define R_ICU_PERIERR_CLR3_ER_CL10_Msk (0x400UL) /*!< ER_CL10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL11_Pos (11UL) /*!< ER_CL11 (Bit 11) */ + #define R_ICU_PERIERR_CLR3_ER_CL11_Msk (0x800UL) /*!< ER_CL11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL12_Pos (12UL) /*!< ER_CL12 (Bit 12) */ + #define R_ICU_PERIERR_CLR3_ER_CL12_Msk (0x1000UL) /*!< ER_CL12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL13_Pos (13UL) /*!< ER_CL13 (Bit 13) */ + #define R_ICU_PERIERR_CLR3_ER_CL13_Msk (0x2000UL) /*!< ER_CL13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL14_Pos (14UL) /*!< ER_CL14 (Bit 14) */ + #define R_ICU_PERIERR_CLR3_ER_CL14_Msk (0x4000UL) /*!< ER_CL14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL15_Pos (15UL) /*!< ER_CL15 (Bit 15) */ + #define R_ICU_PERIERR_CLR3_ER_CL15_Msk (0x8000UL) /*!< ER_CL15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL16_Pos (16UL) /*!< ER_CL16 (Bit 16) */ + #define R_ICU_PERIERR_CLR3_ER_CL16_Msk (0x10000UL) /*!< ER_CL16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL17_Pos (17UL) /*!< ER_CL17 (Bit 17) */ + #define R_ICU_PERIERR_CLR3_ER_CL17_Msk (0x20000UL) /*!< ER_CL17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL18_Pos (18UL) /*!< ER_CL18 (Bit 18) */ + #define R_ICU_PERIERR_CLR3_ER_CL18_Msk (0x40000UL) /*!< ER_CL18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL19_Pos (19UL) /*!< ER_CL19 (Bit 19) */ + #define R_ICU_PERIERR_CLR3_ER_CL19_Msk (0x80000UL) /*!< ER_CL19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL20_Pos (20UL) /*!< ER_CL20 (Bit 20) */ + #define R_ICU_PERIERR_CLR3_ER_CL20_Msk (0x100000UL) /*!< ER_CL20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL21_Pos (21UL) /*!< ER_CL21 (Bit 21) */ + #define R_ICU_PERIERR_CLR3_ER_CL21_Msk (0x200000UL) /*!< ER_CL21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL22_Pos (22UL) /*!< ER_CL22 (Bit 22) */ + #define R_ICU_PERIERR_CLR3_ER_CL22_Msk (0x400000UL) /*!< ER_CL22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL23_Pos (23UL) /*!< ER_CL23 (Bit 23) */ + #define R_ICU_PERIERR_CLR3_ER_CL23_Msk (0x800000UL) /*!< ER_CL23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL24_Pos (24UL) /*!< ER_CL24 (Bit 24) */ + #define R_ICU_PERIERR_CLR3_ER_CL24_Msk (0x1000000UL) /*!< ER_CL24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL25_Pos (25UL) /*!< ER_CL25 (Bit 25) */ + #define R_ICU_PERIERR_CLR3_ER_CL25_Msk (0x2000000UL) /*!< ER_CL25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL26_Pos (26UL) /*!< ER_CL26 (Bit 26) */ + #define R_ICU_PERIERR_CLR3_ER_CL26_Msk (0x4000000UL) /*!< ER_CL26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL27_Pos (27UL) /*!< ER_CL27 (Bit 27) */ + #define R_ICU_PERIERR_CLR3_ER_CL27_Msk (0x8000000UL) /*!< ER_CL27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL28_Pos (28UL) /*!< ER_CL28 (Bit 28) */ + #define R_ICU_PERIERR_CLR3_ER_CL28_Msk (0x10000000UL) /*!< ER_CL28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL29_Pos (29UL) /*!< ER_CL29 (Bit 29) */ + #define R_ICU_PERIERR_CLR3_ER_CL29_Msk (0x20000000UL) /*!< ER_CL29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR3_ER_CL30_Pos (30UL) /*!< ER_CL30 (Bit 30) */ + #define R_ICU_PERIERR_CLR3_ER_CL30_Msk (0x40000000UL) /*!< ER_CL30 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_RSTMSK2 ==================================================== */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK0_Pos (0UL) /*!< RS_MK0 (Bit 0) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK0_Msk (0x1UL) /*!< RS_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK1_Pos (1UL) /*!< RS_MK1 (Bit 1) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK1_Msk (0x2UL) /*!< RS_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK2_Pos (2UL) /*!< RS_MK2 (Bit 2) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK2_Msk (0x4UL) /*!< RS_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK3_Pos (3UL) /*!< RS_MK3 (Bit 3) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK3_Msk (0x8UL) /*!< RS_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK4_Pos (4UL) /*!< RS_MK4 (Bit 4) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK4_Msk (0x10UL) /*!< RS_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK5_Pos (5UL) /*!< RS_MK5 (Bit 5) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK5_Msk (0x20UL) /*!< RS_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK6_Pos (6UL) /*!< RS_MK6 (Bit 6) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK6_Msk (0x40UL) /*!< RS_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK7_Pos (7UL) /*!< RS_MK7 (Bit 7) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK7_Msk (0x80UL) /*!< RS_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK8_Pos (8UL) /*!< RS_MK8 (Bit 8) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK8_Msk (0x100UL) /*!< RS_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK9_Pos (9UL) /*!< RS_MK9 (Bit 9) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK9_Msk (0x200UL) /*!< RS_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK10_Pos (10UL) /*!< RS_MK10 (Bit 10) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK10_Msk (0x400UL) /*!< RS_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK11_Pos (11UL) /*!< RS_MK11 (Bit 11) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK11_Msk (0x800UL) /*!< RS_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK12_Pos (12UL) /*!< RS_MK12 (Bit 12) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK12_Msk (0x1000UL) /*!< RS_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK13_Pos (13UL) /*!< RS_MK13 (Bit 13) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK13_Msk (0x2000UL) /*!< RS_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK14_Pos (14UL) /*!< RS_MK14 (Bit 14) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK14_Msk (0x4000UL) /*!< RS_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK15_Pos (15UL) /*!< RS_MK15 (Bit 15) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK15_Msk (0x8000UL) /*!< RS_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK16_Pos (16UL) /*!< RS_MK16 (Bit 16) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK16_Msk (0x10000UL) /*!< RS_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK17_Pos (17UL) /*!< RS_MK17 (Bit 17) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK17_Msk (0x20000UL) /*!< RS_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK18_Pos (18UL) /*!< RS_MK18 (Bit 18) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK18_Msk (0x40000UL) /*!< RS_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK19_Pos (19UL) /*!< RS_MK19 (Bit 19) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK19_Msk (0x80000UL) /*!< RS_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK20_Pos (20UL) /*!< RS_MK20 (Bit 20) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK20_Msk (0x100000UL) /*!< RS_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK21_Pos (21UL) /*!< RS_MK21 (Bit 21) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK21_Msk (0x200000UL) /*!< RS_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK22_Pos (22UL) /*!< RS_MK22 (Bit 22) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK22_Msk (0x400000UL) /*!< RS_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK23_Pos (23UL) /*!< RS_MK23 (Bit 23) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK23_Msk (0x800000UL) /*!< RS_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK24_Pos (24UL) /*!< RS_MK24 (Bit 24) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK24_Msk (0x1000000UL) /*!< RS_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK25_Pos (25UL) /*!< RS_MK25 (Bit 25) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK25_Msk (0x2000000UL) /*!< RS_MK25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK26_Pos (26UL) /*!< RS_MK26 (Bit 26) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK26_Msk (0x4000000UL) /*!< RS_MK26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK27_Pos (27UL) /*!< RS_MK27 (Bit 27) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK27_Msk (0x8000000UL) /*!< RS_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK28_Pos (28UL) /*!< RS_MK28 (Bit 28) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK28_Msk (0x10000000UL) /*!< RS_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK29_Pos (29UL) /*!< RS_MK29 (Bit 29) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK29_Msk (0x20000000UL) /*!< RS_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK30_Pos (30UL) /*!< RS_MK30 (Bit 30) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK30_Msk (0x40000000UL) /*!< RS_MK30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK31_Pos (31UL) /*!< RS_MK31 (Bit 31) */ + #define R_ICU_PERIERR_RSTMSK2_RS_MK31_Msk (0x80000000UL) /*!< RS_MK31 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_RSTMSK3 ==================================================== */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK0_Pos (0UL) /*!< RS_MK0 (Bit 0) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK0_Msk (0x1UL) /*!< RS_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK1_Pos (1UL) /*!< RS_MK1 (Bit 1) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK1_Msk (0x2UL) /*!< RS_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK2_Pos (2UL) /*!< RS_MK2 (Bit 2) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK2_Msk (0x4UL) /*!< RS_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK3_Pos (3UL) /*!< RS_MK3 (Bit 3) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK3_Msk (0x8UL) /*!< RS_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK4_Pos (4UL) /*!< RS_MK4 (Bit 4) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK4_Msk (0x10UL) /*!< RS_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK5_Pos (5UL) /*!< RS_MK5 (Bit 5) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK5_Msk (0x20UL) /*!< RS_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK6_Pos (6UL) /*!< RS_MK6 (Bit 6) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK6_Msk (0x40UL) /*!< RS_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK7_Pos (7UL) /*!< RS_MK7 (Bit 7) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK7_Msk (0x80UL) /*!< RS_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK8_Pos (8UL) /*!< RS_MK8 (Bit 8) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK8_Msk (0x100UL) /*!< RS_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK9_Pos (9UL) /*!< RS_MK9 (Bit 9) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK9_Msk (0x200UL) /*!< RS_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK10_Pos (10UL) /*!< RS_MK10 (Bit 10) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK10_Msk (0x400UL) /*!< RS_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK11_Pos (11UL) /*!< RS_MK11 (Bit 11) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK11_Msk (0x800UL) /*!< RS_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK12_Pos (12UL) /*!< RS_MK12 (Bit 12) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK12_Msk (0x1000UL) /*!< RS_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK13_Pos (13UL) /*!< RS_MK13 (Bit 13) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK13_Msk (0x2000UL) /*!< RS_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK14_Pos (14UL) /*!< RS_MK14 (Bit 14) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK14_Msk (0x4000UL) /*!< RS_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK15_Pos (15UL) /*!< RS_MK15 (Bit 15) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK15_Msk (0x8000UL) /*!< RS_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK16_Pos (16UL) /*!< RS_MK16 (Bit 16) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK16_Msk (0x10000UL) /*!< RS_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK17_Pos (17UL) /*!< RS_MK17 (Bit 17) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK17_Msk (0x20000UL) /*!< RS_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK18_Pos (18UL) /*!< RS_MK18 (Bit 18) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK18_Msk (0x40000UL) /*!< RS_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK19_Pos (19UL) /*!< RS_MK19 (Bit 19) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK19_Msk (0x80000UL) /*!< RS_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK20_Pos (20UL) /*!< RS_MK20 (Bit 20) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK20_Msk (0x100000UL) /*!< RS_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK21_Pos (21UL) /*!< RS_MK21 (Bit 21) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK21_Msk (0x200000UL) /*!< RS_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK22_Pos (22UL) /*!< RS_MK22 (Bit 22) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK22_Msk (0x400000UL) /*!< RS_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK23_Pos (23UL) /*!< RS_MK23 (Bit 23) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK23_Msk (0x800000UL) /*!< RS_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK24_Pos (24UL) /*!< RS_MK24 (Bit 24) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK24_Msk (0x1000000UL) /*!< RS_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK25_Pos (25UL) /*!< RS_MK25 (Bit 25) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK25_Msk (0x2000000UL) /*!< RS_MK25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK26_Pos (26UL) /*!< RS_MK26 (Bit 26) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK26_Msk (0x4000000UL) /*!< RS_MK26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK27_Pos (27UL) /*!< RS_MK27 (Bit 27) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK27_Msk (0x8000000UL) /*!< RS_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK28_Pos (28UL) /*!< RS_MK28 (Bit 28) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK28_Msk (0x10000000UL) /*!< RS_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK29_Pos (29UL) /*!< RS_MK29 (Bit 29) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK29_Msk (0x20000000UL) /*!< RS_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK30_Pos (30UL) /*!< RS_MK30 (Bit 30) */ + #define R_ICU_PERIERR_RSTMSK3_RS_MK30_Msk (0x40000000UL) /*!< RS_MK30 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E0MSK2 ===================================================== */ + #define R_ICU_PERIERR_E0MSK2_E0_MK0_Pos (0UL) /*!< E0_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK0_Msk (0x1UL) /*!< E0_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK1_Pos (1UL) /*!< E0_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK1_Msk (0x2UL) /*!< E0_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK2_Pos (2UL) /*!< E0_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK2_Msk (0x4UL) /*!< E0_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK3_Pos (3UL) /*!< E0_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK3_Msk (0x8UL) /*!< E0_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK4_Pos (4UL) /*!< E0_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK4_Msk (0x10UL) /*!< E0_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK5_Pos (5UL) /*!< E0_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK5_Msk (0x20UL) /*!< E0_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK6_Pos (6UL) /*!< E0_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK6_Msk (0x40UL) /*!< E0_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK7_Pos (7UL) /*!< E0_MK7 (Bit 7) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK7_Msk (0x80UL) /*!< E0_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK8_Pos (8UL) /*!< E0_MK8 (Bit 8) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK8_Msk (0x100UL) /*!< E0_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK9_Pos (9UL) /*!< E0_MK9 (Bit 9) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK9_Msk (0x200UL) /*!< E0_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK10_Pos (10UL) /*!< E0_MK10 (Bit 10) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK10_Msk (0x400UL) /*!< E0_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK11_Pos (11UL) /*!< E0_MK11 (Bit 11) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK11_Msk (0x800UL) /*!< E0_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK12_Pos (12UL) /*!< E0_MK12 (Bit 12) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK12_Msk (0x1000UL) /*!< E0_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK13_Pos (13UL) /*!< E0_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK13_Msk (0x2000UL) /*!< E0_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK14_Pos (14UL) /*!< E0_MK14 (Bit 14) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK14_Msk (0x4000UL) /*!< E0_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK15_Pos (15UL) /*!< E0_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK15_Msk (0x8000UL) /*!< E0_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK16_Pos (16UL) /*!< E0_MK16 (Bit 16) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK16_Msk (0x10000UL) /*!< E0_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK17_Pos (17UL) /*!< E0_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK17_Msk (0x20000UL) /*!< E0_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK18_Pos (18UL) /*!< E0_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK18_Msk (0x40000UL) /*!< E0_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK19_Pos (19UL) /*!< E0_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK19_Msk (0x80000UL) /*!< E0_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK20_Pos (20UL) /*!< E0_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK20_Msk (0x100000UL) /*!< E0_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK21_Pos (21UL) /*!< E0_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK21_Msk (0x200000UL) /*!< E0_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK22_Pos (22UL) /*!< E0_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK22_Msk (0x400000UL) /*!< E0_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK23_Pos (23UL) /*!< E0_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK23_Msk (0x800000UL) /*!< E0_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK24_Pos (24UL) /*!< E0_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK24_Msk (0x1000000UL) /*!< E0_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK25_Pos (25UL) /*!< E0_MK25 (Bit 25) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK25_Msk (0x2000000UL) /*!< E0_MK25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK26_Pos (26UL) /*!< E0_MK26 (Bit 26) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK26_Msk (0x4000000UL) /*!< E0_MK26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK27_Pos (27UL) /*!< E0_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK27_Msk (0x8000000UL) /*!< E0_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK28_Pos (28UL) /*!< E0_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK28_Msk (0x10000000UL) /*!< E0_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK29_Pos (29UL) /*!< E0_MK29 (Bit 29) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK29_Msk (0x20000000UL) /*!< E0_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK30_Pos (30UL) /*!< E0_MK30 (Bit 30) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK30_Msk (0x40000000UL) /*!< E0_MK30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK31_Pos (31UL) /*!< E0_MK31 (Bit 31) */ + #define R_ICU_PERIERR_E0MSK2_E0_MK31_Msk (0x80000000UL) /*!< E0_MK31 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E0MSK3 ===================================================== */ + #define R_ICU_PERIERR_E0MSK3_E0_MK0_Pos (0UL) /*!< E0_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK0_Msk (0x1UL) /*!< E0_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK1_Pos (1UL) /*!< E0_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK1_Msk (0x2UL) /*!< E0_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK2_Pos (2UL) /*!< E0_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK2_Msk (0x4UL) /*!< E0_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK3_Pos (3UL) /*!< E0_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK3_Msk (0x8UL) /*!< E0_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK4_Pos (4UL) /*!< E0_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK4_Msk (0x10UL) /*!< E0_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK5_Pos (5UL) /*!< E0_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK5_Msk (0x20UL) /*!< E0_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK6_Pos (6UL) /*!< E0_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK6_Msk (0x40UL) /*!< E0_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK7_Pos (7UL) /*!< E0_MK7 (Bit 7) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK7_Msk (0x80UL) /*!< E0_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK8_Pos (8UL) /*!< E0_MK8 (Bit 8) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK8_Msk (0x100UL) /*!< E0_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK9_Pos (9UL) /*!< E0_MK9 (Bit 9) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK9_Msk (0x200UL) /*!< E0_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK10_Pos (10UL) /*!< E0_MK10 (Bit 10) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK10_Msk (0x400UL) /*!< E0_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK11_Pos (11UL) /*!< E0_MK11 (Bit 11) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK11_Msk (0x800UL) /*!< E0_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK12_Pos (12UL) /*!< E0_MK12 (Bit 12) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK12_Msk (0x1000UL) /*!< E0_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK13_Pos (13UL) /*!< E0_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK13_Msk (0x2000UL) /*!< E0_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK14_Pos (14UL) /*!< E0_MK14 (Bit 14) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK14_Msk (0x4000UL) /*!< E0_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK15_Pos (15UL) /*!< E0_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK15_Msk (0x8000UL) /*!< E0_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK16_Pos (16UL) /*!< E0_MK16 (Bit 16) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK16_Msk (0x10000UL) /*!< E0_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK17_Pos (17UL) /*!< E0_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK17_Msk (0x20000UL) /*!< E0_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK18_Pos (18UL) /*!< E0_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK18_Msk (0x40000UL) /*!< E0_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK19_Pos (19UL) /*!< E0_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK19_Msk (0x80000UL) /*!< E0_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK20_Pos (20UL) /*!< E0_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK20_Msk (0x100000UL) /*!< E0_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK21_Pos (21UL) /*!< E0_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK21_Msk (0x200000UL) /*!< E0_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK22_Pos (22UL) /*!< E0_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK22_Msk (0x400000UL) /*!< E0_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK23_Pos (23UL) /*!< E0_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK23_Msk (0x800000UL) /*!< E0_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK24_Pos (24UL) /*!< E0_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK24_Msk (0x1000000UL) /*!< E0_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK25_Pos (25UL) /*!< E0_MK25 (Bit 25) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK25_Msk (0x2000000UL) /*!< E0_MK25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK26_Pos (26UL) /*!< E0_MK26 (Bit 26) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK26_Msk (0x4000000UL) /*!< E0_MK26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK27_Pos (27UL) /*!< E0_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK27_Msk (0x8000000UL) /*!< E0_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK28_Pos (28UL) /*!< E0_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK28_Msk (0x10000000UL) /*!< E0_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK29_Pos (29UL) /*!< E0_MK29 (Bit 29) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK29_Msk (0x20000000UL) /*!< E0_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK30_Pos (30UL) /*!< E0_MK30 (Bit 30) */ + #define R_ICU_PERIERR_E0MSK3_E0_MK30_Msk (0x40000000UL) /*!< E0_MK30 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E1MSK2 ===================================================== */ + #define R_ICU_PERIERR_E1MSK2_E1_MK0_Pos (0UL) /*!< E1_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK0_Msk (0x1UL) /*!< E1_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK1_Pos (1UL) /*!< E1_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK1_Msk (0x2UL) /*!< E1_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK2_Pos (2UL) /*!< E1_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK2_Msk (0x4UL) /*!< E1_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK3_Pos (3UL) /*!< E1_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK3_Msk (0x8UL) /*!< E1_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK4_Pos (4UL) /*!< E1_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK4_Msk (0x10UL) /*!< E1_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK5_Pos (5UL) /*!< E1_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK5_Msk (0x20UL) /*!< E1_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK6_Pos (6UL) /*!< E1_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK6_Msk (0x40UL) /*!< E1_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK7_Pos (7UL) /*!< E1_MK7 (Bit 7) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK7_Msk (0x80UL) /*!< E1_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK8_Pos (8UL) /*!< E1_MK8 (Bit 8) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK8_Msk (0x100UL) /*!< E1_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK9_Pos (9UL) /*!< E1_MK9 (Bit 9) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK9_Msk (0x200UL) /*!< E1_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK10_Pos (10UL) /*!< E1_MK10 (Bit 10) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK10_Msk (0x400UL) /*!< E1_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK11_Pos (11UL) /*!< E1_MK11 (Bit 11) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK11_Msk (0x800UL) /*!< E1_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK12_Pos (12UL) /*!< E1_MK12 (Bit 12) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK12_Msk (0x1000UL) /*!< E1_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK13_Pos (13UL) /*!< E1_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK13_Msk (0x2000UL) /*!< E1_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK14_Pos (14UL) /*!< E1_MK14 (Bit 14) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK14_Msk (0x4000UL) /*!< E1_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK15_Pos (15UL) /*!< E1_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK15_Msk (0x8000UL) /*!< E1_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK16_Pos (16UL) /*!< E1_MK16 (Bit 16) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK16_Msk (0x10000UL) /*!< E1_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK17_Pos (17UL) /*!< E1_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK17_Msk (0x20000UL) /*!< E1_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK18_Pos (18UL) /*!< E1_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK18_Msk (0x40000UL) /*!< E1_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK19_Pos (19UL) /*!< E1_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK19_Msk (0x80000UL) /*!< E1_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK20_Pos (20UL) /*!< E1_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK20_Msk (0x100000UL) /*!< E1_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK21_Pos (21UL) /*!< E1_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK21_Msk (0x200000UL) /*!< E1_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK22_Pos (22UL) /*!< E1_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK22_Msk (0x400000UL) /*!< E1_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK23_Pos (23UL) /*!< E1_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK23_Msk (0x800000UL) /*!< E1_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK24_Pos (24UL) /*!< E1_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK24_Msk (0x1000000UL) /*!< E1_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK25_Pos (25UL) /*!< E1_MK25 (Bit 25) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK25_Msk (0x2000000UL) /*!< E1_MK25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK26_Pos (26UL) /*!< E1_MK26 (Bit 26) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK26_Msk (0x4000000UL) /*!< E1_MK26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK27_Pos (27UL) /*!< E1_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK27_Msk (0x8000000UL) /*!< E1_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK28_Pos (28UL) /*!< E1_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK28_Msk (0x10000000UL) /*!< E1_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK29_Pos (29UL) /*!< E1_MK29 (Bit 29) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK29_Msk (0x20000000UL) /*!< E1_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK30_Pos (30UL) /*!< E1_MK30 (Bit 30) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK30_Msk (0x40000000UL) /*!< E1_MK30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK31_Pos (31UL) /*!< E1_MK31 (Bit 31) */ + #define R_ICU_PERIERR_E1MSK2_E1_MK31_Msk (0x80000000UL) /*!< E1_MK31 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E1MSK3 ===================================================== */ + #define R_ICU_PERIERR_E1MSK3_E1_MK0_Pos (0UL) /*!< E1_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK0_Msk (0x1UL) /*!< E1_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK1_Pos (1UL) /*!< E1_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK1_Msk (0x2UL) /*!< E1_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK2_Pos (2UL) /*!< E1_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK2_Msk (0x4UL) /*!< E1_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK3_Pos (3UL) /*!< E1_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK3_Msk (0x8UL) /*!< E1_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK4_Pos (4UL) /*!< E1_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK4_Msk (0x10UL) /*!< E1_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK5_Pos (5UL) /*!< E1_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK5_Msk (0x20UL) /*!< E1_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK6_Pos (6UL) /*!< E1_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK6_Msk (0x40UL) /*!< E1_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK7_Pos (7UL) /*!< E1_MK7 (Bit 7) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK7_Msk (0x80UL) /*!< E1_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK8_Pos (8UL) /*!< E1_MK8 (Bit 8) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK8_Msk (0x100UL) /*!< E1_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK9_Pos (9UL) /*!< E1_MK9 (Bit 9) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK9_Msk (0x200UL) /*!< E1_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK10_Pos (10UL) /*!< E1_MK10 (Bit 10) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK10_Msk (0x400UL) /*!< E1_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK11_Pos (11UL) /*!< E1_MK11 (Bit 11) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK11_Msk (0x800UL) /*!< E1_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK12_Pos (12UL) /*!< E1_MK12 (Bit 12) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK12_Msk (0x1000UL) /*!< E1_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK13_Pos (13UL) /*!< E1_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK13_Msk (0x2000UL) /*!< E1_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK14_Pos (14UL) /*!< E1_MK14 (Bit 14) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK14_Msk (0x4000UL) /*!< E1_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK15_Pos (15UL) /*!< E1_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK15_Msk (0x8000UL) /*!< E1_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK16_Pos (16UL) /*!< E1_MK16 (Bit 16) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK16_Msk (0x10000UL) /*!< E1_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK17_Pos (17UL) /*!< E1_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK17_Msk (0x20000UL) /*!< E1_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK18_Pos (18UL) /*!< E1_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK18_Msk (0x40000UL) /*!< E1_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK19_Pos (19UL) /*!< E1_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK19_Msk (0x80000UL) /*!< E1_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK20_Pos (20UL) /*!< E1_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK20_Msk (0x100000UL) /*!< E1_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK21_Pos (21UL) /*!< E1_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK21_Msk (0x200000UL) /*!< E1_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK22_Pos (22UL) /*!< E1_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK22_Msk (0x400000UL) /*!< E1_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK23_Pos (23UL) /*!< E1_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK23_Msk (0x800000UL) /*!< E1_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK24_Pos (24UL) /*!< E1_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK24_Msk (0x1000000UL) /*!< E1_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK25_Pos (25UL) /*!< E1_MK25 (Bit 25) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK25_Msk (0x2000000UL) /*!< E1_MK25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK26_Pos (26UL) /*!< E1_MK26 (Bit 26) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK26_Msk (0x4000000UL) /*!< E1_MK26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK27_Pos (27UL) /*!< E1_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK27_Msk (0x8000000UL) /*!< E1_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK28_Pos (28UL) /*!< E1_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK28_Msk (0x10000000UL) /*!< E1_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK29_Pos (29UL) /*!< E1_MK29 (Bit 29) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK29_Msk (0x20000000UL) /*!< E1_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK30_Pos (30UL) /*!< E1_MK30 (Bit 30) */ + #define R_ICU_PERIERR_E1MSK3_E1_MK30_Msk (0x40000000UL) /*!< E1_MK30 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSC_S ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SCKCR2 ========================================================= */ + #define R_SYSC_S_SCKCR2_FSELCPU0_Pos (0UL) /*!< FSELCPU0 (Bit 0) */ + #define R_SYSC_S_SCKCR2_FSELCPU0_Msk (0x3UL) /*!< FSELCPU0 (Bitfield-Mask: 0x03) */ + #define R_SYSC_S_SCKCR2_FSELTRACE_Pos (4UL) /*!< FSELTRACE (Bit 4) */ + #define R_SYSC_S_SCKCR2_FSELTRACE_Msk (0x10UL) /*!< FSELTRACE (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_SCKCR2_DIVSELSUB_Pos (5UL) /*!< DIVSELSUB (Bit 5) */ + #define R_SYSC_S_SCKCR2_DIVSELSUB_Msk (0x20UL) /*!< DIVSELSUB (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_SCKCR2_SPI3ASYNCSEL_Pos (24UL) /*!< SPI3ASYNCSEL (Bit 24) */ + #define R_SYSC_S_SCKCR2_SPI3ASYNCSEL_Msk (0x1000000UL) /*!< SPI3ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_SCKCR2_SCI5ASYNCSEL_Pos (25UL) /*!< SCI5ASYNCSEL (Bit 25) */ + #define R_SYSC_S_SCKCR2_SCI5ASYNCSEL_Msk (0x2000000UL) /*!< SCI5ASYNCSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL0MON ======================================================== */ + #define R_SYSC_S_PLL0MON_PLL0MON_Pos (0UL) /*!< PLL0MON (Bit 0) */ + #define R_SYSC_S_PLL0MON_PLL0MON_Msk (0x1UL) /*!< PLL0MON (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL1MON ======================================================== */ + #define R_SYSC_S_PLL1MON_PLL1MON_Pos (0UL) /*!< PLL1MON (Bit 0) */ + #define R_SYSC_S_PLL1MON_PLL1MON_Msk (0x1UL) /*!< PLL1MON (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL1EN ========================================================= */ + #define R_SYSC_S_PLL1EN_PLL1EN_Pos (0UL) /*!< PLL1EN (Bit 0) */ + #define R_SYSC_S_PLL1EN_PLL1EN_Msk (0x1UL) /*!< PLL1EN (Bitfield-Mask: 0x01) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSC_S_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSC_S_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= HIZCTRLEN ======================================================= */ + #define R_SYSC_S_HIZCTRLEN_CLMA3MASK_Pos (0UL) /*!< CLMA3MASK (Bit 0) */ + #define R_SYSC_S_HIZCTRLEN_CLMA3MASK_Msk (0x1UL) /*!< CLMA3MASK (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_HIZCTRLEN_CLMA0MASK_Pos (1UL) /*!< CLMA0MASK (Bit 1) */ + #define R_SYSC_S_HIZCTRLEN_CLMA0MASK_Msk (0x2UL) /*!< CLMA0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_HIZCTRLEN_CLMA1MASK_Pos (2UL) /*!< CLMA1MASK (Bit 2) */ + #define R_SYSC_S_HIZCTRLEN_CLMA1MASK_Msk (0x4UL) /*!< CLMA1MASK (Bitfield-Mask: 0x01) */ +/* ======================================================== SWRSYS ========================================================= */ + #define R_SYSC_S_SWRSYS_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_SYSC_S_SWRSYS_SWR_Msk (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SWRCPU0 ======================================================== */ + #define R_SYSC_S_SWRCPU0_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_SYSC_S_SWRCPU0_SWR_Msk (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRCTLI ========================================================= */ + #define R_SYSC_S_MRCTLI_MRCTLI01_Pos (1UL) /*!< MRCTLI01 (Bit 1) */ + #define R_SYSC_S_MRCTLI_MRCTLI01_Msk (0x2UL) /*!< MRCTLI01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MRCTLI_MRCTLI02_Pos (2UL) /*!< MRCTLI02 (Bit 2) */ + #define R_SYSC_S_MRCTLI_MRCTLI02_Msk (0x4UL) /*!< MRCTLI02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MRCTLI_MRCTLI03_Pos (3UL) /*!< MRCTLI03 (Bit 3) */ + #define R_SYSC_S_MRCTLI_MRCTLI03_Msk (0x8UL) /*!< MRCTLI03 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRF ======================================================== */ + #define R_SYSC_S_MSTPCRF_MSTPCRF00_Pos (0UL) /*!< MSTPCRF00 (Bit 0) */ + #define R_SYSC_S_MSTPCRF_MSTPCRF00_Msk (0x1UL) /*!< MSTPCRF00 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRG ======================================================== */ + #define R_SYSC_S_MSTPCRG_MSTPCRG00_Pos (0UL) /*!< MSTPCRG00 (Bit 0) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG00_Msk (0x1UL) /*!< MSTPCRG00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG01_Pos (1UL) /*!< MSTPCRG01 (Bit 1) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG01_Msk (0x2UL) /*!< MSTPCRG01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG02_Pos (2UL) /*!< MSTPCRG02 (Bit 2) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG02_Msk (0x4UL) /*!< MSTPCRG02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG03_Pos (3UL) /*!< MSTPCRG03 (Bit 3) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG03_Msk (0x8UL) /*!< MSTPCRG03 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG04_Pos (4UL) /*!< MSTPCRG04 (Bit 4) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG04_Msk (0x10UL) /*!< MSTPCRG04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG05_Pos (5UL) /*!< MSTPCRG05 (Bit 5) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG05_Msk (0x20UL) /*!< MSTPCRG05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG08_Pos (8UL) /*!< MSTPCRG08 (Bit 8) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG08_Msk (0x100UL) /*!< MSTPCRG08 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG09_Pos (9UL) /*!< MSTPCRG09 (Bit 9) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG09_Msk (0x200UL) /*!< MSTPCRG09 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG10_Pos (10UL) /*!< MSTPCRG10 (Bit 10) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG10_Msk (0x400UL) /*!< MSTPCRG10 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG11_Pos (11UL) /*!< MSTPCRG11 (Bit 11) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG11_Msk (0x800UL) /*!< MSTPCRG11 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRI ======================================================== */ + #define R_SYSC_S_MSTPCRI_MSTPCRI01_Pos (1UL) /*!< MSTPCRI01 (Bit 1) */ + #define R_SYSC_S_MSTPCRI_MSTPCRI01_Msk (0x2UL) /*!< MSTPCRI01 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CLMA0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTL0 ========================================================== */ + #define R_CLMA0_CTL0_CLME_Pos (0UL) /*!< CLME (Bit 0) */ + #define R_CLMA0_CTL0_CLME_Msk (0x1UL) /*!< CLME (Bitfield-Mask: 0x01) */ +/* ========================================================= CMPL ========================================================== */ + #define R_CLMA0_CMPL_CMPL_Pos (0UL) /*!< CMPL (Bit 0) */ + #define R_CLMA0_CMPL_CMPL_Msk (0xfffUL) /*!< CMPL (Bitfield-Mask: 0xfff) */ +/* ========================================================= CMPH ========================================================== */ + #define R_CLMA0_CMPH_CMPH_Pos (0UL) /*!< CMPH (Bit 0) */ + #define R_CLMA0_CMPH_CMPH_Msk (0xfffUL) /*!< CMPH (Bitfield-Mask: 0xfff) */ +/* ========================================================= PCMD ========================================================== */ +/* ======================================================== PROTSR ========================================================= */ + #define R_CLMA0_PROTSR_PRERR_Pos (0UL) /*!< PRERR (Bit 0) */ + #define R_CLMA0_PROTSR_PRERR_Msk (0x1UL) /*!< PRERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= ERRINF_R ======================================================== */ + #define R_MPU0_ERRINF_R_VALID_Pos (0UL) /*!< VALID (Bit 0) */ + #define R_MPU0_ERRINF_R_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_MPU0_ERRINF_R_RW_Pos (1UL) /*!< RW (Bit 1) */ + #define R_MPU0_ERRINF_R_RW_Msk (0x2UL) /*!< RW (Bitfield-Mask: 0x01) */ + #define R_MPU0_ERRINF_R_ERRADDR_Pos (2UL) /*!< ERRADDR (Bit 2) */ + #define R_MPU0_ERRINF_R_ERRADDR_Msk (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================= ERRINF_W ======================================================== */ + #define R_MPU0_ERRINF_W_VALID_Pos (0UL) /*!< VALID (Bit 0) */ + #define R_MPU0_ERRINF_W_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_MPU0_ERRINF_W_RW_Pos (1UL) /*!< RW (Bit 1) */ + #define R_MPU0_ERRINF_W_RW_Msk (0x2UL) /*!< RW (Bitfield-Mask: 0x01) */ + #define R_MPU0_ERRINF_W_ERRADDR_Pos (2UL) /*!< ERRADDR (Bit 2) */ + #define R_MPU0_ERRINF_W_ERRADDR_Msk (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU3 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== ERRINF ========================================================= */ + #define R_MPU3_ERRINF_VALID_Pos (0UL) /*!< VALID (Bit 0) */ + #define R_MPU3_ERRINF_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_MPU3_ERRINF_RW_Pos (1UL) /*!< RW (Bit 1) */ + #define R_MPU3_ERRINF_RW_Msk (0x2UL) /*!< RW (Bitfield-Mask: 0x01) */ + #define R_MPU3_ERRINF_ERRADDR_Pos (2UL) /*!< ERRADDR (Bit 2) */ + #define R_MPU3_ERRINF_ERRADDR_Msk (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSRAM_CTL ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== SYSRAM_CTRL0 ====================================================== */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VECEN_Pos (0UL) /*!< VECEN (Bit 0) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VECEN_Msk (0x1UL) /*!< VECEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VRWEN_Pos (16UL) /*!< VRWEN (Bit 16) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VRWEN_Msk (0xf0000UL) /*!< VRWEN (Bitfield-Mask: 0x0f) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VCEN_Pos (20UL) /*!< VCEN (Bit 20) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VCEN_Msk (0x100000UL) /*!< VCEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VLWEN_Pos (21UL) /*!< VLWEN (Bit 21) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VLWEN_Msk (0x200000UL) /*!< VLWEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_MKICCAXIERR_Pos (24UL) /*!< MKICCAXIERR (Bit 24) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_MKICCAXIERR_Msk (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01) */ +/* ===================================================== SYSRAM_CTRL1 ====================================================== */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VECEN_Pos (0UL) /*!< VECEN (Bit 0) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VECEN_Msk (0x1UL) /*!< VECEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VRWEN_Pos (16UL) /*!< VRWEN (Bit 16) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VRWEN_Msk (0xf0000UL) /*!< VRWEN (Bitfield-Mask: 0x0f) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VCEN_Pos (20UL) /*!< VCEN (Bit 20) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VCEN_Msk (0x100000UL) /*!< VCEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VLWEN_Pos (21UL) /*!< VLWEN (Bit 21) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VLWEN_Msk (0x200000UL) /*!< VLWEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_MKICCAXIERR_Pos (24UL) /*!< MKICCAXIERR (Bit 24) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_MKICCAXIERR_Msk (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TCMAW ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= CPU0WAIT ======================================================== */ + #define R_TCMAW_CPU0WAIT_CPU0WAIT_Pos (0UL) /*!< CPU0WAIT (Bit 0) */ + #define R_TCMAW_CPU0WAIT_CPU0WAIT_Msk (0x1UL) /*!< CPU0WAIT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SHOSTIF_CFG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SHCFG ========================================================= */ + #define R_SHOSTIF_CFG_SHCFG_SPIMODE_Pos (0UL) /*!< SPIMODE (Bit 0) */ + #define R_SHOSTIF_CFG_SHCFG_SPIMODE_Msk (0x3UL) /*!< SPIMODE (Bitfield-Mask: 0x03) */ + #define R_SHOSTIF_CFG_SHCFG_BYTESWAP_Pos (2UL) /*!< BYTESWAP (Bit 2) */ + #define R_SHOSTIF_CFG_SHCFG_BYTESWAP_Msk (0x4UL) /*!< BYTESWAP (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_CFG_SHCFG_ADDRESSING_Pos (3UL) /*!< ADDRESSING (Bit 3) */ + #define R_SHOSTIF_CFG_SHCFG_ADDRESSING_Msk (0x8UL) /*!< ADDRESSING (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_CFG_SHCFG_SLEEP_Pos (4UL) /*!< SLEEP (Bit 4) */ + #define R_SHOSTIF_CFG_SHCFG_SLEEP_Msk (0x10UL) /*!< SLEEP (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_CFG_SHCFG_INTMASKI_Pos (16UL) /*!< INTMASKI (Bit 16) */ + #define R_SHOSTIF_CFG_SHCFG_INTMASKI_Msk (0x3f0000UL) /*!< INTMASKI (Bitfield-Mask: 0x3f) */ + #define R_SHOSTIF_CFG_SHCFG_INTMASKE_Pos (24UL) /*!< INTMASKE (Bit 24) */ + #define R_SHOSTIF_CFG_SHCFG_INTMASKE_Msk (0x3f000000UL) /*!< INTMASKE (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_RWP_S ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRCRS ========================================================= */ + #define R_RWP_S_PRCRS_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_RWP_S_PRCRS_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_RWP_S_PRCRS_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_RWP_S_PRCRS_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_RWP_S_PRCRS_PRC2_Pos (2UL) /*!< PRC2 (Bit 2) */ + #define R_RWP_S_PRCRS_PRC2_Msk (0x4UL) /*!< PRC2 (Bitfield-Mask: 0x01) */ + #define R_RWP_S_PRCRS_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_RWP_S_PRCRS_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_RWP_S_PRCRS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_RWP_S_PRCRS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TOERA ========================================================= */ + #define R_MTU_TOERA_OE3B_Pos (0UL) /*!< OE3B (Bit 0) */ + #define R_MTU_TOERA_OE3B_Msk (0x1UL) /*!< OE3B (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERA_OE4A_Pos (1UL) /*!< OE4A (Bit 1) */ + #define R_MTU_TOERA_OE4A_Msk (0x2UL) /*!< OE4A (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERA_OE4B_Pos (2UL) /*!< OE4B (Bit 2) */ + #define R_MTU_TOERA_OE4B_Msk (0x4UL) /*!< OE4B (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERA_OE3D_Pos (3UL) /*!< OE3D (Bit 3) */ + #define R_MTU_TOERA_OE3D_Msk (0x8UL) /*!< OE3D (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERA_OE4C_Pos (4UL) /*!< OE4C (Bit 4) */ + #define R_MTU_TOERA_OE4C_Msk (0x10UL) /*!< OE4C (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERA_OE4D_Pos (5UL) /*!< OE4D (Bit 5) */ + #define R_MTU_TOERA_OE4D_Msk (0x20UL) /*!< OE4D (Bitfield-Mask: 0x01) */ +/* ========================================================= TGCRA ========================================================= */ + #define R_MTU_TGCRA_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_MTU_TGCRA_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_MTU_TGCRA_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_MTU_TGCRA_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_FB_Pos (3UL) /*!< FB (Bit 3) */ + #define R_MTU_TGCRA_FB_Msk (0x8UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_P_Pos (4UL) /*!< P (Bit 4) */ + #define R_MTU_TGCRA_P_Msk (0x10UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_N_Pos (5UL) /*!< N (Bit 5) */ + #define R_MTU_TGCRA_N_Msk (0x20UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_BDC_Pos (6UL) /*!< BDC (Bit 6) */ + #define R_MTU_TGCRA_BDC_Msk (0x40UL) /*!< BDC (Bitfield-Mask: 0x01) */ +/* ======================================================== TOCR1A ========================================================= */ + #define R_MTU_TOCR1A_OLSP_Pos (0UL) /*!< OLSP (Bit 0) */ + #define R_MTU_TOCR1A_OLSP_Msk (0x1UL) /*!< OLSP (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1A_OLSN_Pos (1UL) /*!< OLSN (Bit 1) */ + #define R_MTU_TOCR1A_OLSN_Msk (0x2UL) /*!< OLSN (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1A_TOCS_Pos (2UL) /*!< TOCS (Bit 2) */ + #define R_MTU_TOCR1A_TOCS_Msk (0x4UL) /*!< TOCS (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1A_TOCL_Pos (3UL) /*!< TOCL (Bit 3) */ + #define R_MTU_TOCR1A_TOCL_Msk (0x8UL) /*!< TOCL (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1A_PSYE_Pos (6UL) /*!< PSYE (Bit 6) */ + #define R_MTU_TOCR1A_PSYE_Msk (0x40UL) /*!< PSYE (Bitfield-Mask: 0x01) */ +/* ======================================================== TOCR2A ========================================================= */ + #define R_MTU_TOCR2A_OLS1P_Pos (0UL) /*!< OLS1P (Bit 0) */ + #define R_MTU_TOCR2A_OLS1P_Msk (0x1UL) /*!< OLS1P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_OLS1N_Pos (1UL) /*!< OLS1N (Bit 1) */ + #define R_MTU_TOCR2A_OLS1N_Msk (0x2UL) /*!< OLS1N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_OLS2P_Pos (2UL) /*!< OLS2P (Bit 2) */ + #define R_MTU_TOCR2A_OLS2P_Msk (0x4UL) /*!< OLS2P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_OLS2N_Pos (3UL) /*!< OLS2N (Bit 3) */ + #define R_MTU_TOCR2A_OLS2N_Msk (0x8UL) /*!< OLS2N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_OLS3P_Pos (4UL) /*!< OLS3P (Bit 4) */ + #define R_MTU_TOCR2A_OLS3P_Msk (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_OLS3N_Pos (5UL) /*!< OLS3N (Bit 5) */ + #define R_MTU_TOCR2A_OLS3N_Msk (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_BF_Pos (6UL) /*!< BF (Bit 6) */ + #define R_MTU_TOCR2A_BF_Msk (0xc0UL) /*!< BF (Bitfield-Mask: 0x03) */ +/* ========================================================= TCDRA ========================================================= */ +/* ========================================================= TDDRA ========================================================= */ +/* ======================================================== TCNTSA ========================================================= */ +/* ========================================================= TCBRA ========================================================= */ +/* ======================================================== TITCR1A ======================================================== */ + #define R_MTU_TITCR1A_T4VCOR_Pos (0UL) /*!< T4VCOR (Bit 0) */ + #define R_MTU_TITCR1A_T4VCOR_Msk (0x7UL) /*!< T4VCOR (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCR1A_T4VEN_Pos (3UL) /*!< T4VEN (Bit 3) */ + #define R_MTU_TITCR1A_T4VEN_Msk (0x8UL) /*!< T4VEN (Bitfield-Mask: 0x01) */ + #define R_MTU_TITCR1A_T3ACOR_Pos (4UL) /*!< T3ACOR (Bit 4) */ + #define R_MTU_TITCR1A_T3ACOR_Msk (0x70UL) /*!< T3ACOR (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCR1A_T3AEN_Pos (7UL) /*!< T3AEN (Bit 7) */ + #define R_MTU_TITCR1A_T3AEN_Msk (0x80UL) /*!< T3AEN (Bitfield-Mask: 0x01) */ +/* ======================================================= TITCNT1A ======================================================== */ + #define R_MTU_TITCNT1A_T4VCNT_Pos (0UL) /*!< T4VCNT (Bit 0) */ + #define R_MTU_TITCNT1A_T4VCNT_Msk (0x7UL) /*!< T4VCNT (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCNT1A_T3ACNT_Pos (4UL) /*!< T3ACNT (Bit 4) */ + #define R_MTU_TITCNT1A_T3ACNT_Msk (0x70UL) /*!< T3ACNT (Bitfield-Mask: 0x07) */ +/* ======================================================== TBTERA ========================================================= */ + #define R_MTU_TBTERA_BTE_Pos (0UL) /*!< BTE (Bit 0) */ + #define R_MTU_TBTERA_BTE_Msk (0x3UL) /*!< BTE (Bitfield-Mask: 0x03) */ +/* ========================================================= TDERA ========================================================= */ + #define R_MTU_TDERA_TDER_Pos (0UL) /*!< TDER (Bit 0) */ + #define R_MTU_TDERA_TDER_Msk (0x1UL) /*!< TDER (Bitfield-Mask: 0x01) */ +/* ======================================================== TOLBRA ========================================================= */ + #define R_MTU_TOLBRA_OLS1P_Pos (0UL) /*!< OLS1P (Bit 0) */ + #define R_MTU_TOLBRA_OLS1P_Msk (0x1UL) /*!< OLS1P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRA_OLS1N_Pos (1UL) /*!< OLS1N (Bit 1) */ + #define R_MTU_TOLBRA_OLS1N_Msk (0x2UL) /*!< OLS1N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRA_OLS2P_Pos (2UL) /*!< OLS2P (Bit 2) */ + #define R_MTU_TOLBRA_OLS2P_Msk (0x4UL) /*!< OLS2P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRA_OLS2N_Pos (3UL) /*!< OLS2N (Bit 3) */ + #define R_MTU_TOLBRA_OLS2N_Msk (0x8UL) /*!< OLS2N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRA_OLS3P_Pos (4UL) /*!< OLS3P (Bit 4) */ + #define R_MTU_TOLBRA_OLS3P_Msk (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRA_OLS3N_Pos (5UL) /*!< OLS3N (Bit 5) */ + #define R_MTU_TOLBRA_OLS3N_Msk (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01) */ +/* ======================================================== TITMRA ========================================================= */ + #define R_MTU_TITMRA_TITM_Pos (0UL) /*!< TITM (Bit 0) */ + #define R_MTU_TITMRA_TITM_Msk (0x1UL) /*!< TITM (Bitfield-Mask: 0x01) */ +/* ======================================================== TITCR2A ======================================================== */ + #define R_MTU_TITCR2A_TRG4COR_Pos (0UL) /*!< TRG4COR (Bit 0) */ + #define R_MTU_TITCR2A_TRG4COR_Msk (0x7UL) /*!< TRG4COR (Bitfield-Mask: 0x07) */ +/* ======================================================= TITCNT2A ======================================================== */ + #define R_MTU_TITCNT2A_TRG4CNT_Pos (0UL) /*!< TRG4CNT (Bit 0) */ + #define R_MTU_TITCNT2A_TRG4CNT_Msk (0x7UL) /*!< TRG4CNT (Bitfield-Mask: 0x07) */ +/* ========================================================= TWCRA ========================================================= */ + #define R_MTU_TWCRA_WRE_Pos (0UL) /*!< WRE (Bit 0) */ + #define R_MTU_TWCRA_WRE_Msk (0x1UL) /*!< WRE (Bitfield-Mask: 0x01) */ + #define R_MTU_TWCRA_SCC_Pos (1UL) /*!< SCC (Bit 1) */ + #define R_MTU_TWCRA_SCC_Msk (0x2UL) /*!< SCC (Bitfield-Mask: 0x01) */ + #define R_MTU_TWCRA_CCE_Pos (7UL) /*!< CCE (Bit 7) */ + #define R_MTU_TWCRA_CCE_Msk (0x80UL) /*!< CCE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMDR2A ========================================================= */ + #define R_MTU_TMDR2A_DRS_Pos (0UL) /*!< DRS (Bit 0) */ + #define R_MTU_TMDR2A_DRS_Msk (0x1UL) /*!< DRS (Bitfield-Mask: 0x01) */ +/* ========================================================= TSTRA ========================================================= */ + #define R_MTU_TSTRA_CST0_Pos (0UL) /*!< CST0 (Bit 0) */ + #define R_MTU_TSTRA_CST0_Msk (0x1UL) /*!< CST0 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRA_CST1_Pos (1UL) /*!< CST1 (Bit 1) */ + #define R_MTU_TSTRA_CST1_Msk (0x2UL) /*!< CST1 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRA_CST2_Pos (2UL) /*!< CST2 (Bit 2) */ + #define R_MTU_TSTRA_CST2_Msk (0x4UL) /*!< CST2 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRA_CST8_Pos (3UL) /*!< CST8 (Bit 3) */ + #define R_MTU_TSTRA_CST8_Msk (0x8UL) /*!< CST8 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRA_CST3_Pos (6UL) /*!< CST3 (Bit 6) */ + #define R_MTU_TSTRA_CST3_Msk (0x40UL) /*!< CST3 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRA_CST4_Pos (7UL) /*!< CST4 (Bit 7) */ + #define R_MTU_TSTRA_CST4_Msk (0x80UL) /*!< CST4 (Bitfield-Mask: 0x01) */ +/* ========================================================= TSYRA ========================================================= */ + #define R_MTU_TSYRA_SYNC0_Pos (0UL) /*!< SYNC0 (Bit 0) */ + #define R_MTU_TSYRA_SYNC0_Msk (0x1UL) /*!< SYNC0 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSYRA_SYNC1_Pos (1UL) /*!< SYNC1 (Bit 1) */ + #define R_MTU_TSYRA_SYNC1_Msk (0x2UL) /*!< SYNC1 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSYRA_SYNC2_Pos (2UL) /*!< SYNC2 (Bit 2) */ + #define R_MTU_TSYRA_SYNC2_Msk (0x4UL) /*!< SYNC2 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSYRA_SYNC3_Pos (6UL) /*!< SYNC3 (Bit 6) */ + #define R_MTU_TSYRA_SYNC3_Msk (0x40UL) /*!< SYNC3 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSYRA_SYNC4_Pos (7UL) /*!< SYNC4 (Bit 7) */ + #define R_MTU_TSYRA_SYNC4_Msk (0x80UL) /*!< SYNC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== TCSYSTR ======================================================== */ + #define R_MTU_TCSYSTR_SCH7_Pos (0UL) /*!< SCH7 (Bit 0) */ + #define R_MTU_TCSYSTR_SCH7_Msk (0x1UL) /*!< SCH7 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH6_Pos (1UL) /*!< SCH6 (Bit 1) */ + #define R_MTU_TCSYSTR_SCH6_Msk (0x2UL) /*!< SCH6 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH4_Pos (3UL) /*!< SCH4 (Bit 3) */ + #define R_MTU_TCSYSTR_SCH4_Msk (0x8UL) /*!< SCH4 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH3_Pos (4UL) /*!< SCH3 (Bit 4) */ + #define R_MTU_TCSYSTR_SCH3_Msk (0x10UL) /*!< SCH3 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH2_Pos (5UL) /*!< SCH2 (Bit 5) */ + #define R_MTU_TCSYSTR_SCH2_Msk (0x20UL) /*!< SCH2 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH1_Pos (6UL) /*!< SCH1 (Bit 6) */ + #define R_MTU_TCSYSTR_SCH1_Msk (0x40UL) /*!< SCH1 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH0_Pos (7UL) /*!< SCH0 (Bit 7) */ + #define R_MTU_TCSYSTR_SCH0_Msk (0x80UL) /*!< SCH0 (Bitfield-Mask: 0x01) */ +/* ======================================================== TRWERA ========================================================= */ + #define R_MTU_TRWERA_RWE_Pos (0UL) /*!< RWE (Bit 0) */ + #define R_MTU_TRWERA_RWE_Msk (0x1UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ========================================================= TOERB ========================================================= */ + #define R_MTU_TOERB_OE6B_Pos (0UL) /*!< OE6B (Bit 0) */ + #define R_MTU_TOERB_OE6B_Msk (0x1UL) /*!< OE6B (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERB_OE7A_Pos (1UL) /*!< OE7A (Bit 1) */ + #define R_MTU_TOERB_OE7A_Msk (0x2UL) /*!< OE7A (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERB_OE7B_Pos (2UL) /*!< OE7B (Bit 2) */ + #define R_MTU_TOERB_OE7B_Msk (0x4UL) /*!< OE7B (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERB_OE6D_Pos (3UL) /*!< OE6D (Bit 3) */ + #define R_MTU_TOERB_OE6D_Msk (0x8UL) /*!< OE6D (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERB_OE7C_Pos (4UL) /*!< OE7C (Bit 4) */ + #define R_MTU_TOERB_OE7C_Msk (0x10UL) /*!< OE7C (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERB_OE7D_Pos (5UL) /*!< OE7D (Bit 5) */ + #define R_MTU_TOERB_OE7D_Msk (0x20UL) /*!< OE7D (Bitfield-Mask: 0x01) */ +/* ======================================================== TOCR1B ========================================================= */ + #define R_MTU_TOCR1B_OLSP_Pos (0UL) /*!< OLSP (Bit 0) */ + #define R_MTU_TOCR1B_OLSP_Msk (0x1UL) /*!< OLSP (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1B_OLSN_Pos (1UL) /*!< OLSN (Bit 1) */ + #define R_MTU_TOCR1B_OLSN_Msk (0x2UL) /*!< OLSN (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1B_TOCS_Pos (2UL) /*!< TOCS (Bit 2) */ + #define R_MTU_TOCR1B_TOCS_Msk (0x4UL) /*!< TOCS (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1B_TOCL_Pos (3UL) /*!< TOCL (Bit 3) */ + #define R_MTU_TOCR1B_TOCL_Msk (0x8UL) /*!< TOCL (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1B_PSYE_Pos (6UL) /*!< PSYE (Bit 6) */ + #define R_MTU_TOCR1B_PSYE_Msk (0x40UL) /*!< PSYE (Bitfield-Mask: 0x01) */ +/* ======================================================== TOCR2B ========================================================= */ + #define R_MTU_TOCR2B_OLS1P_Pos (0UL) /*!< OLS1P (Bit 0) */ + #define R_MTU_TOCR2B_OLS1P_Msk (0x1UL) /*!< OLS1P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_OLS1N_Pos (1UL) /*!< OLS1N (Bit 1) */ + #define R_MTU_TOCR2B_OLS1N_Msk (0x2UL) /*!< OLS1N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_OLS2P_Pos (2UL) /*!< OLS2P (Bit 2) */ + #define R_MTU_TOCR2B_OLS2P_Msk (0x4UL) /*!< OLS2P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_OLS2N_Pos (3UL) /*!< OLS2N (Bit 3) */ + #define R_MTU_TOCR2B_OLS2N_Msk (0x8UL) /*!< OLS2N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_OLS3P_Pos (4UL) /*!< OLS3P (Bit 4) */ + #define R_MTU_TOCR2B_OLS3P_Msk (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_OLS3N_Pos (5UL) /*!< OLS3N (Bit 5) */ + #define R_MTU_TOCR2B_OLS3N_Msk (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_BF_Pos (6UL) /*!< BF (Bit 6) */ + #define R_MTU_TOCR2B_BF_Msk (0xc0UL) /*!< BF (Bitfield-Mask: 0x03) */ +/* ========================================================= TCDRB ========================================================= */ +/* ========================================================= TDDRB ========================================================= */ +/* ======================================================== TCNTSB ========================================================= */ +/* ========================================================= TCBRB ========================================================= */ +/* ======================================================== TITCR1B ======================================================== */ + #define R_MTU_TITCR1B_T7VCOR_Pos (0UL) /*!< T7VCOR (Bit 0) */ + #define R_MTU_TITCR1B_T7VCOR_Msk (0x7UL) /*!< T7VCOR (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCR1B_T7VEN_Pos (3UL) /*!< T7VEN (Bit 3) */ + #define R_MTU_TITCR1B_T7VEN_Msk (0x8UL) /*!< T7VEN (Bitfield-Mask: 0x01) */ + #define R_MTU_TITCR1B_T6ACOR_Pos (4UL) /*!< T6ACOR (Bit 4) */ + #define R_MTU_TITCR1B_T6ACOR_Msk (0x70UL) /*!< T6ACOR (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCR1B_T6AEN_Pos (7UL) /*!< T6AEN (Bit 7) */ + #define R_MTU_TITCR1B_T6AEN_Msk (0x80UL) /*!< T6AEN (Bitfield-Mask: 0x01) */ +/* ======================================================= TITCNT1B ======================================================== */ + #define R_MTU_TITCNT1B_T7VCNT_Pos (0UL) /*!< T7VCNT (Bit 0) */ + #define R_MTU_TITCNT1B_T7VCNT_Msk (0x7UL) /*!< T7VCNT (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCNT1B_T6ACNT_Pos (4UL) /*!< T6ACNT (Bit 4) */ + #define R_MTU_TITCNT1B_T6ACNT_Msk (0x70UL) /*!< T6ACNT (Bitfield-Mask: 0x07) */ +/* ======================================================== TBTERB ========================================================= */ + #define R_MTU_TBTERB_BTE_Pos (0UL) /*!< BTE (Bit 0) */ + #define R_MTU_TBTERB_BTE_Msk (0x3UL) /*!< BTE (Bitfield-Mask: 0x03) */ +/* ========================================================= TDERB ========================================================= */ + #define R_MTU_TDERB_TDER_Pos (0UL) /*!< TDER (Bit 0) */ + #define R_MTU_TDERB_TDER_Msk (0x1UL) /*!< TDER (Bitfield-Mask: 0x01) */ +/* ======================================================== TOLBRB ========================================================= */ + #define R_MTU_TOLBRB_OLS1P_Pos (0UL) /*!< OLS1P (Bit 0) */ + #define R_MTU_TOLBRB_OLS1P_Msk (0x1UL) /*!< OLS1P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRB_OLS1N_Pos (1UL) /*!< OLS1N (Bit 1) */ + #define R_MTU_TOLBRB_OLS1N_Msk (0x2UL) /*!< OLS1N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRB_OLS2P_Pos (2UL) /*!< OLS2P (Bit 2) */ + #define R_MTU_TOLBRB_OLS2P_Msk (0x4UL) /*!< OLS2P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRB_OLS2N_Pos (3UL) /*!< OLS2N (Bit 3) */ + #define R_MTU_TOLBRB_OLS2N_Msk (0x8UL) /*!< OLS2N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRB_OLS3P_Pos (4UL) /*!< OLS3P (Bit 4) */ + #define R_MTU_TOLBRB_OLS3P_Msk (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRB_OLS3N_Pos (5UL) /*!< OLS3N (Bit 5) */ + #define R_MTU_TOLBRB_OLS3N_Msk (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01) */ +/* ======================================================== TITMRB ========================================================= */ + #define R_MTU_TITMRB_TITM_Pos (0UL) /*!< TITM (Bit 0) */ + #define R_MTU_TITMRB_TITM_Msk (0x1UL) /*!< TITM (Bitfield-Mask: 0x01) */ +/* ======================================================== TITCR2B ======================================================== */ + #define R_MTU_TITCR2B_TRG7COR_Pos (0UL) /*!< TRG7COR (Bit 0) */ + #define R_MTU_TITCR2B_TRG7COR_Msk (0x7UL) /*!< TRG7COR (Bitfield-Mask: 0x07) */ +/* ======================================================= TITCNT2B ======================================================== */ + #define R_MTU_TITCNT2B_TRG7CNT_Pos (0UL) /*!< TRG7CNT (Bit 0) */ + #define R_MTU_TITCNT2B_TRG7CNT_Msk (0x7UL) /*!< TRG7CNT (Bitfield-Mask: 0x07) */ +/* ========================================================= TWCRB ========================================================= */ + #define R_MTU_TWCRB_WRE_Pos (0UL) /*!< WRE (Bit 0) */ + #define R_MTU_TWCRB_WRE_Msk (0x1UL) /*!< WRE (Bitfield-Mask: 0x01) */ + #define R_MTU_TWCRB_SCC_Pos (1UL) /*!< SCC (Bit 1) */ + #define R_MTU_TWCRB_SCC_Msk (0x2UL) /*!< SCC (Bitfield-Mask: 0x01) */ + #define R_MTU_TWCRB_CCE_Pos (7UL) /*!< CCE (Bit 7) */ + #define R_MTU_TWCRB_CCE_Msk (0x80UL) /*!< CCE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMDR2B ========================================================= */ + #define R_MTU_TMDR2B_DRS_Pos (0UL) /*!< DRS (Bit 0) */ + #define R_MTU_TMDR2B_DRS_Msk (0x1UL) /*!< DRS (Bitfield-Mask: 0x01) */ +/* ========================================================= TSTRB ========================================================= */ + #define R_MTU_TSTRB_CST6_Pos (6UL) /*!< CST6 (Bit 6) */ + #define R_MTU_TSTRB_CST6_Msk (0x40UL) /*!< CST6 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRB_CST7_Pos (7UL) /*!< CST7 (Bit 7) */ + #define R_MTU_TSTRB_CST7_Msk (0x80UL) /*!< CST7 (Bitfield-Mask: 0x01) */ +/* ========================================================= TSYRB ========================================================= */ + #define R_MTU_TSYRB_SYNC6_Pos (6UL) /*!< SYNC6 (Bit 6) */ + #define R_MTU_TSYRB_SYNC6_Msk (0x40UL) /*!< SYNC6 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSYRB_SYNC7_Pos (7UL) /*!< SYNC7 (Bit 7) */ + #define R_MTU_TSYRB_SYNC7_Msk (0x80UL) /*!< SYNC7 (Bitfield-Mask: 0x01) */ +/* ======================================================== TRWERB ========================================================= */ + #define R_MTU_TRWERB_RWE_Pos (0UL) /*!< RWE (Bit 0) */ + #define R_MTU_TRWERB_RWE_Msk (0x1UL) /*!< RWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU3 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU3_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU3_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU3_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU3_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU3_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU3_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU3_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU3_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU3_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU3_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU3_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU3_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU3_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU3_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU3_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU3_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU3_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU3_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU3_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU3_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU3_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU3_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU3_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU3_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU3_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU3_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU3_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU3_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU3_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU3_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU3_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU3_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU3_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU3_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU3_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU3_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU3_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU3_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU3_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU3_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TBTM ========================================================== */ + #define R_MTU3_TBTM_TTSA_Pos (0UL) /*!< TTSA (Bit 0) */ + #define R_MTU3_TBTM_TTSA_Msk (0x1UL) /*!< TTSA (Bitfield-Mask: 0x01) */ + #define R_MTU3_TBTM_TTSB_Pos (1UL) /*!< TTSB (Bit 1) */ + #define R_MTU3_TBTM_TTSB_Msk (0x2UL) /*!< TTSB (Bitfield-Mask: 0x01) */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU3_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU3_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ +/* ========================================================= TGRE ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MTU4 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU4_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU4_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU4_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU4_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU4_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU4_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU4_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU4_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU4_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU4_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU4_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU4_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU4_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU4_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU4_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU4_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU4_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU4_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU4_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU4_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU4_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU4_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU4_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU4_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU4_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU4_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TTGE2_Pos (6UL) /*!< TTGE2 (Bit 6) */ + #define R_MTU4_TIER_TTGE2_Msk (0x40UL) /*!< TTGE2 (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU4_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU4_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU4_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU4_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU4_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU4_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU4_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU4_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU4_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TBTM ========================================================== */ + #define R_MTU4_TBTM_TTSA_Pos (0UL) /*!< TTSA (Bit 0) */ + #define R_MTU4_TBTM_TTSA_Msk (0x1UL) /*!< TTSA (Bitfield-Mask: 0x01) */ + #define R_MTU4_TBTM_TTSB_Pos (1UL) /*!< TTSB (Bit 1) */ + #define R_MTU4_TBTM_TTSB_Msk (0x2UL) /*!< TTSB (Bitfield-Mask: 0x01) */ +/* ========================================================= TADCR ========================================================= */ + #define R_MTU4_TADCR_ITB4VE_Pos (0UL) /*!< ITB4VE (Bit 0) */ + #define R_MTU4_TADCR_ITB4VE_Msk (0x1UL) /*!< ITB4VE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_ITB3AE_Pos (1UL) /*!< ITB3AE (Bit 1) */ + #define R_MTU4_TADCR_ITB3AE_Msk (0x2UL) /*!< ITB3AE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_ITA4VE_Pos (2UL) /*!< ITA4VE (Bit 2) */ + #define R_MTU4_TADCR_ITA4VE_Msk (0x4UL) /*!< ITA4VE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_ITA3AE_Pos (3UL) /*!< ITA3AE (Bit 3) */ + #define R_MTU4_TADCR_ITA3AE_Msk (0x8UL) /*!< ITA3AE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_DT4BE_Pos (4UL) /*!< DT4BE (Bit 4) */ + #define R_MTU4_TADCR_DT4BE_Msk (0x10UL) /*!< DT4BE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_UT4BE_Pos (5UL) /*!< UT4BE (Bit 5) */ + #define R_MTU4_TADCR_UT4BE_Msk (0x20UL) /*!< UT4BE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_DT4AE_Pos (6UL) /*!< DT4AE (Bit 6) */ + #define R_MTU4_TADCR_DT4AE_Msk (0x40UL) /*!< DT4AE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_UT4AE_Pos (7UL) /*!< UT4AE (Bit 7) */ + #define R_MTU4_TADCR_UT4AE_Msk (0x80UL) /*!< UT4AE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_BF_Pos (14UL) /*!< BF (Bit 14) */ + #define R_MTU4_TADCR_BF_Msk (0xc000UL) /*!< BF (Bitfield-Mask: 0x03) */ +/* ======================================================== TADCORA ======================================================== */ +/* ======================================================== TADCORB ======================================================== */ +/* ======================================================= TADCOBRA ======================================================== */ +/* ======================================================= TADCOBRB ======================================================== */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU4_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU4_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ +/* ========================================================= TGRE ========================================================== */ +/* ========================================================= TGRF ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MTU_NF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NFCR0 ========================================================= */ + #define R_MTU_NF_NFCR0_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR0_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR0_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR0_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR0_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR0_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR0_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR0_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR0_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR0_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR1 ========================================================= */ + #define R_MTU_NF_NFCR1_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR1_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR1_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR1_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR1_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR1_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR2 ========================================================= */ + #define R_MTU_NF_NFCR2_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR2_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR2_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR2_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR2_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR2_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR3 ========================================================= */ + #define R_MTU_NF_NFCR3_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR3_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR3_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR3_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR3_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR3_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR3_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR3_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR3_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR3_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR4 ========================================================= */ + #define R_MTU_NF_NFCR4_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR4_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR4_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR4_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR4_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR4_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR4_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR4_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR4_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR4_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR8 ========================================================= */ + #define R_MTU_NF_NFCR8_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR8_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR8_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR8_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR8_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR8_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR8_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR8_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR8_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR8_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCRC ========================================================= */ + #define R_MTU_NF_NFCRC_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCRC_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCRC_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCRC_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCRC_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCRC_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCRC_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCRC_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCRC_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCRC_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR6 ========================================================= */ + #define R_MTU_NF_NFCR6_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR6_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR6_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR6_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR6_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR6_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR6_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR6_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR6_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR6_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR7 ========================================================= */ + #define R_MTU_NF_NFCR7_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR7_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR7_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR7_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR7_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR7_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR7_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR7_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR7_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR7_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR5 ========================================================= */ + #define R_MTU_NF_NFCR5_NFUEN_Pos (0UL) /*!< NFUEN (Bit 0) */ + #define R_MTU_NF_NFCR5_NFUEN_Msk (0x1UL) /*!< NFUEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR5_NFVEN_Pos (1UL) /*!< NFVEN (Bit 1) */ + #define R_MTU_NF_NFCR5_NFVEN_Msk (0x2UL) /*!< NFVEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR5_NFWEN_Pos (2UL) /*!< NFWEN (Bit 2) */ + #define R_MTU_NF_NFCR5_NFWEN_Msk (0x4UL) /*!< NFWEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR5_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR5_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU0_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU0_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU0_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU0_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU0_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU0_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU0_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU0_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU0_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU0_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU0_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU0_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ + #define R_MTU0_TMDR1_BFE_Pos (6UL) /*!< BFE (Bit 6) */ + #define R_MTU0_TMDR1_BFE_Msk (0x40UL) /*!< BFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU0_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU0_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU0_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU0_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU0_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU0_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU0_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU0_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU0_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU0_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU0_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU0_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU0_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU0_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU0_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ +/* ========================================================= TGRE ========================================================== */ +/* ========================================================= TGRF ========================================================== */ +/* ========================================================= TIER2 ========================================================= */ + #define R_MTU0_TIER2_TGIEE_Pos (0UL) /*!< TGIEE (Bit 0) */ + #define R_MTU0_TIER2_TGIEE_Msk (0x1UL) /*!< TGIEE (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER2_TGIEF_Pos (1UL) /*!< TGIEF (Bit 1) */ + #define R_MTU0_TIER2_TGIEF_Msk (0x2UL) /*!< TGIEF (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER2_TTGE2_Pos (7UL) /*!< TTGE2 (Bit 7) */ + #define R_MTU0_TIER2_TTGE2_Msk (0x80UL) /*!< TTGE2 (Bitfield-Mask: 0x01) */ +/* ========================================================= TBTM ========================================================== */ + #define R_MTU0_TBTM_TTSA_Pos (0UL) /*!< TTSA (Bit 0) */ + #define R_MTU0_TBTM_TTSA_Msk (0x1UL) /*!< TTSA (Bitfield-Mask: 0x01) */ + #define R_MTU0_TBTM_TTSB_Pos (1UL) /*!< TTSB (Bit 1) */ + #define R_MTU0_TBTM_TTSB_Msk (0x2UL) /*!< TTSB (Bitfield-Mask: 0x01) */ + #define R_MTU0_TBTM_TTSE_Pos (2UL) /*!< TTSE (Bit 2) */ + #define R_MTU0_TBTM_TTSE_Msk (0x4UL) /*!< TTSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU0_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU0_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU1_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU1_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU1_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU1_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU1_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU1_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU1_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU1_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIOR ========================================================== */ + #define R_MTU1_TIOR_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU1_TIOR_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU1_TIOR_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU1_TIOR_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU1_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU1_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU1_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU1_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU1_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU1_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU1_TIER_TCIEU_Pos (5UL) /*!< TCIEU (Bit 5) */ + #define R_MTU1_TIER_TCIEU_Msk (0x20UL) /*!< TCIEU (Bitfield-Mask: 0x01) */ + #define R_MTU1_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU1_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU1_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU1_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU1_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU1_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU1_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU1_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU1_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU1_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TICCR ========================================================= */ + #define R_MTU1_TICCR_I1AE_Pos (0UL) /*!< I1AE (Bit 0) */ + #define R_MTU1_TICCR_I1AE_Msk (0x1UL) /*!< I1AE (Bitfield-Mask: 0x01) */ + #define R_MTU1_TICCR_I1BE_Pos (1UL) /*!< I1BE (Bit 1) */ + #define R_MTU1_TICCR_I1BE_Msk (0x2UL) /*!< I1BE (Bitfield-Mask: 0x01) */ + #define R_MTU1_TICCR_I2AE_Pos (2UL) /*!< I2AE (Bit 2) */ + #define R_MTU1_TICCR_I2AE_Msk (0x4UL) /*!< I2AE (Bitfield-Mask: 0x01) */ + #define R_MTU1_TICCR_I2BE_Pos (3UL) /*!< I2BE (Bit 3) */ + #define R_MTU1_TICCR_I2BE_Msk (0x8UL) /*!< I2BE (Bitfield-Mask: 0x01) */ +/* ========================================================= TMDR3 ========================================================= */ + #define R_MTU1_TMDR3_LWA_Pos (0UL) /*!< LWA (Bit 0) */ + #define R_MTU1_TMDR3_LWA_Msk (0x1UL) /*!< LWA (Bitfield-Mask: 0x01) */ + #define R_MTU1_TMDR3_PHCKSEL_Pos (1UL) /*!< PHCKSEL (Bit 1) */ + #define R_MTU1_TMDR3_PHCKSEL_Msk (0x2UL) /*!< PHCKSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU1_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU1_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + #define R_MTU1_TCR2_PCB_Pos (3UL) /*!< PCB (Bit 3) */ + #define R_MTU1_TCR2_PCB_Msk (0x18UL) /*!< PCB (Bitfield-Mask: 0x03) */ +/* ======================================================== TCNTLW ========================================================= */ +/* ======================================================== TGRALW ========================================================= */ +/* ======================================================== TGRBLW ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_MTU2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU2_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU2_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU2_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU2_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU2_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU2_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU2_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU2_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIOR ========================================================== */ + #define R_MTU2_TIOR_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU2_TIOR_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU2_TIOR_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU2_TIOR_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU2_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU2_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU2_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU2_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU2_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU2_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU2_TIER_TCIEU_Pos (5UL) /*!< TCIEU (Bit 5) */ + #define R_MTU2_TIER_TCIEU_Msk (0x20UL) /*!< TCIEU (Bitfield-Mask: 0x01) */ + #define R_MTU2_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU2_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU2_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU2_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU2_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU2_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU2_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU2_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU2_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU2_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU2_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU2_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + #define R_MTU2_TCR2_PCB_Pos (3UL) /*!< PCB (Bit 3) */ + #define R_MTU2_TCR2_PCB_Msk (0x18UL) /*!< PCB (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU8 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU8_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU8_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU8_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU8_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU8_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU8_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU8_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU8_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU8_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU8_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU8_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU8_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU8_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU8_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU8_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU8_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU8_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU8_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU8_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU8_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU8_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU8_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU8_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU8_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU8_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU8_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU8_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU8_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU8_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU8_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU8_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU8_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MTU6 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU6_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU6_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU6_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU6_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU6_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU6_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU6_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU6_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU6_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU6_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU6_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU6_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU6_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU6_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU6_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU6_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU6_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU6_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU6_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU6_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU6_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU6_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU6_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU6_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU6_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU6_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU6_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU6_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU6_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU6_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU6_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU6_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU6_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU6_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU6_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU6_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU6_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU6_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU6_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU6_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TBTM ========================================================== */ + #define R_MTU6_TBTM_TTSA_Pos (0UL) /*!< TTSA (Bit 0) */ + #define R_MTU6_TBTM_TTSA_Msk (0x1UL) /*!< TTSA (Bitfield-Mask: 0x01) */ + #define R_MTU6_TBTM_TTSB_Pos (1UL) /*!< TTSB (Bit 1) */ + #define R_MTU6_TBTM_TTSB_Msk (0x2UL) /*!< TTSB (Bitfield-Mask: 0x01) */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU6_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU6_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ +/* ========================================================= TSYCR ========================================================= */ + #define R_MTU6_TSYCR_CE2B_Pos (0UL) /*!< CE2B (Bit 0) */ + #define R_MTU6_TSYCR_CE2B_Msk (0x1UL) /*!< CE2B (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE2A_Pos (1UL) /*!< CE2A (Bit 1) */ + #define R_MTU6_TSYCR_CE2A_Msk (0x2UL) /*!< CE2A (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE1B_Pos (2UL) /*!< CE1B (Bit 2) */ + #define R_MTU6_TSYCR_CE1B_Msk (0x4UL) /*!< CE1B (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE1A_Pos (3UL) /*!< CE1A (Bit 3) */ + #define R_MTU6_TSYCR_CE1A_Msk (0x8UL) /*!< CE1A (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE0D_Pos (4UL) /*!< CE0D (Bit 4) */ + #define R_MTU6_TSYCR_CE0D_Msk (0x10UL) /*!< CE0D (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE0C_Pos (5UL) /*!< CE0C (Bit 5) */ + #define R_MTU6_TSYCR_CE0C_Msk (0x20UL) /*!< CE0C (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE0B_Pos (6UL) /*!< CE0B (Bit 6) */ + #define R_MTU6_TSYCR_CE0B_Msk (0x40UL) /*!< CE0B (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE0A_Pos (7UL) /*!< CE0A (Bit 7) */ + #define R_MTU6_TSYCR_CE0A_Msk (0x80UL) /*!< CE0A (Bitfield-Mask: 0x01) */ +/* ========================================================= TGRE ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MTU7 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU7_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU7_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU7_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU7_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU7_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU7_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU7_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU7_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU7_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU7_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU7_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU7_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU7_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU7_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU7_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU7_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU7_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU7_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU7_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU7_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU7_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU7_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU7_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU7_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU7_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU7_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TTGE2_Pos (6UL) /*!< TTGE2 (Bit 6) */ + #define R_MTU7_TIER_TTGE2_Msk (0x40UL) /*!< TTGE2 (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU7_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU7_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU7_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU7_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU7_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU7_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU7_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU7_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU7_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TBTM ========================================================== */ + #define R_MTU7_TBTM_TTSA_Pos (0UL) /*!< TTSA (Bit 0) */ + #define R_MTU7_TBTM_TTSA_Msk (0x1UL) /*!< TTSA (Bitfield-Mask: 0x01) */ + #define R_MTU7_TBTM_TTSB_Pos (1UL) /*!< TTSB (Bit 1) */ + #define R_MTU7_TBTM_TTSB_Msk (0x2UL) /*!< TTSB (Bitfield-Mask: 0x01) */ +/* ========================================================= TADCR ========================================================= */ + #define R_MTU7_TADCR_ITB7VE_Pos (0UL) /*!< ITB7VE (Bit 0) */ + #define R_MTU7_TADCR_ITB7VE_Msk (0x1UL) /*!< ITB7VE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_ITB6AE_Pos (1UL) /*!< ITB6AE (Bit 1) */ + #define R_MTU7_TADCR_ITB6AE_Msk (0x2UL) /*!< ITB6AE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_ITA7VE_Pos (2UL) /*!< ITA7VE (Bit 2) */ + #define R_MTU7_TADCR_ITA7VE_Msk (0x4UL) /*!< ITA7VE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_ITA6AE_Pos (3UL) /*!< ITA6AE (Bit 3) */ + #define R_MTU7_TADCR_ITA6AE_Msk (0x8UL) /*!< ITA6AE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_DT7BE_Pos (4UL) /*!< DT7BE (Bit 4) */ + #define R_MTU7_TADCR_DT7BE_Msk (0x10UL) /*!< DT7BE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_UT7BE_Pos (5UL) /*!< UT7BE (Bit 5) */ + #define R_MTU7_TADCR_UT7BE_Msk (0x20UL) /*!< UT7BE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_DT7AE_Pos (6UL) /*!< DT7AE (Bit 6) */ + #define R_MTU7_TADCR_DT7AE_Msk (0x40UL) /*!< DT7AE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_UT7AE_Pos (7UL) /*!< UT7AE (Bit 7) */ + #define R_MTU7_TADCR_UT7AE_Msk (0x80UL) /*!< UT7AE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_BF_Pos (14UL) /*!< BF (Bit 14) */ + #define R_MTU7_TADCR_BF_Msk (0xc000UL) /*!< BF (Bitfield-Mask: 0x03) */ +/* ======================================================== TADCORA ======================================================== */ +/* ======================================================== TADCORB ======================================================== */ +/* ======================================================= TADCOBRA ======================================================== */ +/* ======================================================= TADCOBRB ======================================================== */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU7_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU7_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ +/* ========================================================= TGRE ========================================================== */ +/* ========================================================= TGRF ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MTU5 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TCNTU ========================================================= */ +/* ========================================================= TGRU ========================================================== */ +/* ========================================================= TCRU ========================================================== */ + #define R_MTU5_TCRU_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU5_TCRU_TPSC_Msk (0x3UL) /*!< TPSC (Bitfield-Mask: 0x03) */ +/* ========================================================= TCR2U ========================================================= */ + #define R_MTU5_TCR2U_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU5_TCR2U_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + #define R_MTU5_TCR2U_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU5_TCR2U_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ +/* ========================================================= TIORU ========================================================= */ + #define R_MTU5_TIORU_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU5_TIORU_IOC_Msk (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f) */ +/* ========================================================= TCNTV ========================================================= */ +/* ========================================================= TGRV ========================================================== */ +/* ========================================================= TCRV ========================================================== */ + #define R_MTU5_TCRV_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU5_TCRV_TPSC_Msk (0x3UL) /*!< TPSC (Bitfield-Mask: 0x03) */ +/* ========================================================= TCR2V ========================================================= */ + #define R_MTU5_TCR2V_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU5_TCR2V_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + #define R_MTU5_TCR2V_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU5_TCR2V_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ +/* ========================================================= TIORV ========================================================= */ + #define R_MTU5_TIORV_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU5_TIORV_IOC_Msk (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f) */ +/* ========================================================= TCNTW ========================================================= */ +/* ========================================================= TGRW ========================================================== */ +/* ========================================================= TCRW ========================================================== */ + #define R_MTU5_TCRW_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU5_TCRW_TPSC_Msk (0x3UL) /*!< TPSC (Bitfield-Mask: 0x03) */ +/* ========================================================= TCR2W ========================================================= */ + #define R_MTU5_TCR2W_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU5_TCR2W_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + #define R_MTU5_TCR2W_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU5_TCR2W_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ +/* ========================================================= TIORW ========================================================= */ + #define R_MTU5_TIORW_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU5_TIORW_IOC_Msk (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU5_TIER_TGIE5W_Pos (0UL) /*!< TGIE5W (Bit 0) */ + #define R_MTU5_TIER_TGIE5W_Msk (0x1UL) /*!< TGIE5W (Bitfield-Mask: 0x01) */ + #define R_MTU5_TIER_TGIE5V_Pos (1UL) /*!< TGIE5V (Bit 1) */ + #define R_MTU5_TIER_TGIE5V_Msk (0x2UL) /*!< TGIE5V (Bitfield-Mask: 0x01) */ + #define R_MTU5_TIER_TGIE5U_Pos (2UL) /*!< TGIE5U (Bit 2) */ + #define R_MTU5_TIER_TGIE5U_Msk (0x4UL) /*!< TGIE5U (Bitfield-Mask: 0x01) */ +/* ========================================================= TSTR ========================================================== */ + #define R_MTU5_TSTR_CSTW5_Pos (0UL) /*!< CSTW5 (Bit 0) */ + #define R_MTU5_TSTR_CSTW5_Msk (0x1UL) /*!< CSTW5 (Bitfield-Mask: 0x01) */ + #define R_MTU5_TSTR_CSTV5_Pos (1UL) /*!< CSTV5 (Bit 1) */ + #define R_MTU5_TSTR_CSTV5_Msk (0x2UL) /*!< CSTV5 (Bitfield-Mask: 0x01) */ + #define R_MTU5_TSTR_CSTU5_Pos (2UL) /*!< CSTU5 (Bit 2) */ + #define R_MTU5_TSTR_CSTU5_Msk (0x4UL) /*!< CSTU5 (Bitfield-Mask: 0x01) */ +/* ====================================================== TCNTCMPCLR ======================================================= */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5W_Pos (0UL) /*!< CMPCLR5W (Bit 0) */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5W_Msk (0x1UL) /*!< CMPCLR5W (Bitfield-Mask: 0x01) */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5V_Pos (1UL) /*!< CMPCLR5V (Bit 1) */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5V_Msk (0x2UL) /*!< CMPCLR5V (Bitfield-Mask: 0x01) */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5U_Pos (2UL) /*!< CMPCLR5U (Bit 2) */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5U_Msk (0x4UL) /*!< CMPCLR5U (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TFU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TRGSTS ========================================================= */ + #define R_TFU_TRGSTS_BSYF_Pos (0UL) /*!< BSYF (Bit 0) */ + #define R_TFU_TRGSTS_BSYF_Msk (0x1UL) /*!< BSYF (Bitfield-Mask: 0x01) */ + #define R_TFU_TRGSTS_ERRF_Pos (1UL) /*!< ERRF (Bit 1) */ + #define R_TFU_TRGSTS_ERRF_Msk (0x2UL) /*!< ERRF (Bitfield-Mask: 0x01) */ +/* ========================================================= SCDT0 ========================================================= */ + #define R_TFU_SCDT0_SCDT0_Pos (0UL) /*!< SCDT0 (Bit 0) */ + #define R_TFU_SCDT0_SCDT0_Msk (0xffffffffUL) /*!< SCDT0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SCDT1 ========================================================= */ + #define R_TFU_SCDT1_SCDT1_Pos (0UL) /*!< SCDT1 (Bit 0) */ + #define R_TFU_SCDT1_SCDT1_Msk (0xffffffffUL) /*!< SCDT1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ATDT0 ========================================================= */ + #define R_TFU_ATDT0_ATDT0_Pos (0UL) /*!< ATDT0 (Bit 0) */ + #define R_TFU_ATDT0_ATDT0_Msk (0xffffffffUL) /*!< ATDT0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ATDT1 ========================================================= */ + #define R_TFU_ATDT1_ATDT1_Pos (0UL) /*!< ATDT1 (Bit 0) */ + #define R_TFU_ATDT1_ATDT1_Msk (0xffffffffUL) /*!< ATDT1 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC120 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC120_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC120_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC120_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC120_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC120_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC120_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC120_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC120_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC120_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC120_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC120_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA0 ======================================================== */ + #define R_ADC120_ADANSA0_ANSA0_Pos (0UL) /*!< ANSA0 (Bit 0) */ + #define R_ADC120_ADANSA0_ANSA0_Msk (0xfUL) /*!< ANSA0 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADADS0 ========================================================= */ + #define R_ADC120_ADADS0_ADS0_Pos (0UL) /*!< ADS0 (Bit 0) */ + #define R_ADC120_ADADS0_ADS0_Msk (0xfUL) /*!< ADS0 (Bitfield-Mask: 0x0f) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC120_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC120_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC120_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC120_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC120_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC120_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC120_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC120_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC120_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC120_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC120_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ + #define R_ADC120_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC120_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADANSB0 ======================================================== */ + #define R_ADC120_ADANSB0_ANSB0_Pos (0UL) /*!< ANSB0 (Bit 0) */ + #define R_ADC120_ADANSB0_ANSB0_Msk (0xfUL) /*!< ANSB0 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC120_ADDBLDR_DBLDR_Pos (0UL) /*!< DBLDR (Bit 0) */ + #define R_ADC120_ADDBLDR_DBLDR_Msk (0xffffUL) /*!< DBLDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC120_ADDR_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_ADC120_ADDR_DR_Msk (0xffffUL) /*!< DR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC120_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC120_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ + #define R_ADC120_ADSHCR_SHANS_Pos (8UL) /*!< SHANS (Bit 8) */ + #define R_ADC120_ADSHCR_SHANS_Msk (0x700UL) /*!< SHANS (Bitfield-Mask: 0x07) */ +/* ======================================================== ADELCCR ======================================================== */ + #define R_ADC120_ADELCCR_ELCC_Pos (0UL) /*!< ELCC (Bit 0) */ + #define R_ADC120_ADELCCR_ELCC_Msk (0x3UL) /*!< ELCC (Bitfield-Mask: 0x03) */ + #define R_ADC120_ADELCCR_GCELC_Pos (2UL) /*!< GCELC (Bit 2) */ + #define R_ADC120_ADELCCR_GCELC_Msk (0x4UL) /*!< GCELC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC120_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC120_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC120_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADGSPCR_LGRRS_Pos (14UL) /*!< LGRRS (Bit 14) */ + #define R_ADC120_ADGSPCR_LGRRS_Msk (0x4000UL) /*!< LGRRS (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC120_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC120_ADDBLDRA_DBLDRA_Pos (0UL) /*!< DBLDRA (Bit 0) */ + #define R_ADC120_ADDBLDRA_DBLDRA_Msk (0xffffUL) /*!< DBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC120_ADDBLDRB_DBLDRB_Pos (0UL) /*!< DBLDRB (Bit 0) */ + #define R_ADC120_ADDBLDRB_DBLDRB_Msk (0xffffUL) /*!< DBLDRB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC120_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC120_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC120_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC120_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC120_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC120_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ + #define R_ADC120_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC120_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC120_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC120_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC120_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC120_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCMPANSR0 ======================================================= */ + #define R_ADC120_ADCMPANSR0_CMPCHA0_Pos (0UL) /*!< CMPCHA0 (Bit 0) */ + #define R_ADC120_ADCMPANSR0_CMPCHA0_Msk (0xffffUL) /*!< CMPCHA0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPLR0 ======================================================== */ + #define R_ADC120_ADCMPLR0_CMPLCHA0_Pos (0UL) /*!< CMPLCHA0 (Bit 0) */ + #define R_ADC120_ADCMPLR0_CMPLCHA0_Msk (0xfUL) /*!< CMPLCHA0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC120_ADCMPDR0_CMPLLA_Pos (0UL) /*!< CMPLLA (Bit 0) */ + #define R_ADC120_ADCMPDR0_CMPLLA_Msk (0xffffUL) /*!< CMPLLA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC120_ADCMPDR1_CMPULA_Pos (0UL) /*!< CMPULA (Bit 0) */ + #define R_ADC120_ADCMPDR1_CMPULA_Msk (0xffffUL) /*!< CMPULA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPSR0 ======================================================== */ + #define R_ADC120_ADCMPSR0_CMPSTCHA0_Pos (0UL) /*!< CMPSTCHA0 (Bit 0) */ + #define R_ADC120_ADCMPSR0_CMPSTCHA0_Msk (0xffffUL) /*!< CMPSTCHA0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC120_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC120_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ + #define R_ADC120_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC120_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC120_ADWINLLB_CMPLLB_Pos (0UL) /*!< CMPLLB (Bit 0) */ + #define R_ADC120_ADWINLLB_CMPLLB_Msk (0xffffUL) /*!< CMPLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC120_ADWINULB_CMPULB_Pos (0UL) /*!< CMPULB (Bit 0) */ + #define R_ADC120_ADWINULB_CMPULB_Msk (0xffffUL) /*!< CMPULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC120_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC120_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSC0 ======================================================== */ + #define R_ADC120_ADANSC0_ANSC0_Pos (0UL) /*!< ANSC0 (Bit 0) */ + #define R_ADC120_ADANSC0_ANSC0_Msk (0xfUL) /*!< ANSC0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADGCTRGR ======================================================== */ + #define R_ADC120_ADGCTRGR_TRSC_Pos (0UL) /*!< TRSC (Bit 0) */ + #define R_ADC120_ADGCTRGR_TRSC_Msk (0x3fUL) /*!< TRSC (Bitfield-Mask: 0x3f) */ + #define R_ADC120_ADGCTRGR_GCADIE_Pos (6UL) /*!< GCADIE (Bit 6) */ + #define R_ADC120_ADGCTRGR_GCADIE_Msk (0x40UL) /*!< GCADIE (Bitfield-Mask: 0x01) */ + #define R_ADC120_ADGCTRGR_GRCE_Pos (7UL) /*!< GRCE (Bit 7) */ + #define R_ADC120_ADGCTRGR_GRCE_Msk (0x80UL) /*!< GRCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC120_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC120_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_POE3 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICSR1 ========================================================= */ + #define R_POE3_ICSR1_POE0M_Pos (0UL) /*!< POE0M (Bit 0) */ + #define R_POE3_ICSR1_POE0M_Msk (0x3UL) /*!< POE0M (Bitfield-Mask: 0x03) */ + #define R_POE3_ICSR1_PIE1_Pos (8UL) /*!< PIE1 (Bit 8) */ + #define R_POE3_ICSR1_PIE1_Msk (0x100UL) /*!< PIE1 (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR1_POE0F_Pos (12UL) /*!< POE0F (Bit 12) */ + #define R_POE3_ICSR1_POE0F_Msk (0x1000UL) /*!< POE0F (Bitfield-Mask: 0x01) */ +/* ========================================================= OCSR1 ========================================================= */ + #define R_POE3_OCSR1_OIE1_Pos (8UL) /*!< OIE1 (Bit 8) */ + #define R_POE3_OCSR1_OIE1_Msk (0x100UL) /*!< OIE1 (Bitfield-Mask: 0x01) */ + #define R_POE3_OCSR1_OCE1_Pos (9UL) /*!< OCE1 (Bit 9) */ + #define R_POE3_OCSR1_OCE1_Msk (0x200UL) /*!< OCE1 (Bitfield-Mask: 0x01) */ + #define R_POE3_OCSR1_OSF1_Pos (15UL) /*!< OSF1 (Bit 15) */ + #define R_POE3_OCSR1_OSF1_Msk (0x8000UL) /*!< OSF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_POE3_ICSR2_POE4M_Pos (0UL) /*!< POE4M (Bit 0) */ + #define R_POE3_ICSR2_POE4M_Msk (0x3UL) /*!< POE4M (Bitfield-Mask: 0x03) */ + #define R_POE3_ICSR2_PIE2_Pos (8UL) /*!< PIE2 (Bit 8) */ + #define R_POE3_ICSR2_PIE2_Msk (0x100UL) /*!< PIE2 (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR2_POE4F_Pos (12UL) /*!< POE4F (Bit 12) */ + #define R_POE3_ICSR2_POE4F_Msk (0x1000UL) /*!< POE4F (Bitfield-Mask: 0x01) */ +/* ========================================================= OCSR2 ========================================================= */ + #define R_POE3_OCSR2_OIE2_Pos (8UL) /*!< OIE2 (Bit 8) */ + #define R_POE3_OCSR2_OIE2_Msk (0x100UL) /*!< OIE2 (Bitfield-Mask: 0x01) */ + #define R_POE3_OCSR2_OCE2_Pos (9UL) /*!< OCE2 (Bit 9) */ + #define R_POE3_OCSR2_OCE2_Msk (0x200UL) /*!< OCE2 (Bitfield-Mask: 0x01) */ + #define R_POE3_OCSR2_OSF2_Pos (15UL) /*!< OSF2 (Bit 15) */ + #define R_POE3_OCSR2_OSF2_Msk (0x8000UL) /*!< OSF2 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR3 ========================================================= */ + #define R_POE3_ICSR3_POE8M_Pos (0UL) /*!< POE8M (Bit 0) */ + #define R_POE3_ICSR3_POE8M_Msk (0x3UL) /*!< POE8M (Bitfield-Mask: 0x03) */ + #define R_POE3_ICSR3_PIE3_Pos (8UL) /*!< PIE3 (Bit 8) */ + #define R_POE3_ICSR3_PIE3_Msk (0x100UL) /*!< PIE3 (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR3_POE8E_Pos (9UL) /*!< POE8E (Bit 9) */ + #define R_POE3_ICSR3_POE8E_Msk (0x200UL) /*!< POE8E (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR3_POE8F_Pos (12UL) /*!< POE8F (Bit 12) */ + #define R_POE3_ICSR3_POE8F_Msk (0x1000UL) /*!< POE8F (Bitfield-Mask: 0x01) */ +/* ========================================================= SPOER ========================================================= */ + #define R_POE3_SPOER_MTUCH34HIZ_Pos (0UL) /*!< MTUCH34HIZ (Bit 0) */ + #define R_POE3_SPOER_MTUCH34HIZ_Msk (0x1UL) /*!< MTUCH34HIZ (Bitfield-Mask: 0x01) */ + #define R_POE3_SPOER_MTUCH67HIZ_Pos (1UL) /*!< MTUCH67HIZ (Bit 1) */ + #define R_POE3_SPOER_MTUCH67HIZ_Msk (0x2UL) /*!< MTUCH67HIZ (Bitfield-Mask: 0x01) */ + #define R_POE3_SPOER_MTUCH0HIZ_Pos (2UL) /*!< MTUCH0HIZ (Bit 2) */ + #define R_POE3_SPOER_MTUCH0HIZ_Msk (0x4UL) /*!< MTUCH0HIZ (Bitfield-Mask: 0x01) */ +/* ======================================================== POECR1 ========================================================= */ + #define R_POE3_POECR1_MTU0AZE_Pos (0UL) /*!< MTU0AZE (Bit 0) */ + #define R_POE3_POECR1_MTU0AZE_Msk (0x1UL) /*!< MTU0AZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR1_MTU0BZE_Pos (1UL) /*!< MTU0BZE (Bit 1) */ + #define R_POE3_POECR1_MTU0BZE_Msk (0x2UL) /*!< MTU0BZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR1_MTU0CZE_Pos (2UL) /*!< MTU0CZE (Bit 2) */ + #define R_POE3_POECR1_MTU0CZE_Msk (0x4UL) /*!< MTU0CZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR1_MTU0DZE_Pos (3UL) /*!< MTU0DZE (Bit 3) */ + #define R_POE3_POECR1_MTU0DZE_Msk (0x8UL) /*!< MTU0DZE (Bitfield-Mask: 0x01) */ +/* ======================================================== POECR2 ========================================================= */ + #define R_POE3_POECR2_MTU7BDZE_Pos (0UL) /*!< MTU7BDZE (Bit 0) */ + #define R_POE3_POECR2_MTU7BDZE_Msk (0x1UL) /*!< MTU7BDZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR2_MTU7ACZE_Pos (1UL) /*!< MTU7ACZE (Bit 1) */ + #define R_POE3_POECR2_MTU7ACZE_Msk (0x2UL) /*!< MTU7ACZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR2_MTU6BDZE_Pos (2UL) /*!< MTU6BDZE (Bit 2) */ + #define R_POE3_POECR2_MTU6BDZE_Msk (0x4UL) /*!< MTU6BDZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR2_MTU4BDZE_Pos (8UL) /*!< MTU4BDZE (Bit 8) */ + #define R_POE3_POECR2_MTU4BDZE_Msk (0x100UL) /*!< MTU4BDZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR2_MTU4ACZE_Pos (9UL) /*!< MTU4ACZE (Bit 9) */ + #define R_POE3_POECR2_MTU4ACZE_Msk (0x200UL) /*!< MTU4ACZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR2_MTU3BDZE_Pos (10UL) /*!< MTU3BDZE (Bit 10) */ + #define R_POE3_POECR2_MTU3BDZE_Msk (0x400UL) /*!< MTU3BDZE (Bitfield-Mask: 0x01) */ +/* ======================================================== POECR4 ========================================================= */ + #define R_POE3_POECR4_D0E1ADDMT34ZE_Pos (0UL) /*!< D0E1ADDMT34ZE (Bit 0) */ + #define R_POE3_POECR4_D0E1ADDMT34ZE_Msk (0x1UL) /*!< D0E1ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_D1E1ADDMT34ZE_Pos (1UL) /*!< D1E1ADDMT34ZE (Bit 1) */ + #define R_POE3_POECR4_D1E1ADDMT34ZE_Msk (0x2UL) /*!< D1E1ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC2ADDMT34ZE_Pos (2UL) /*!< IC2ADDMT34ZE (Bit 2) */ + #define R_POE3_POECR4_IC2ADDMT34ZE_Msk (0x4UL) /*!< IC2ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC3ADDMT34ZE_Pos (3UL) /*!< IC3ADDMT34ZE (Bit 3) */ + #define R_POE3_POECR4_IC3ADDMT34ZE_Msk (0x8UL) /*!< IC3ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC4ADDMT34ZE_Pos (4UL) /*!< IC4ADDMT34ZE (Bit 4) */ + #define R_POE3_POECR4_IC4ADDMT34ZE_Msk (0x10UL) /*!< IC4ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC5ADDMT34ZE_Pos (5UL) /*!< IC5ADDMT34ZE (Bit 5) */ + #define R_POE3_POECR4_IC5ADDMT34ZE_Msk (0x20UL) /*!< IC5ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_D0E0ADDMT34ZE_Pos (6UL) /*!< D0E0ADDMT34ZE (Bit 6) */ + #define R_POE3_POECR4_D0E0ADDMT34ZE_Msk (0x40UL) /*!< D0E0ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_D1E0ADDMT34ZE_Pos (7UL) /*!< D1E0ADDMT34ZE (Bit 7) */ + #define R_POE3_POECR4_D1E0ADDMT34ZE_Msk (0x80UL) /*!< D1E0ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_D0E1ADDMT67ZE_Pos (8UL) /*!< D0E1ADDMT67ZE (Bit 8) */ + #define R_POE3_POECR4_D0E1ADDMT67ZE_Msk (0x100UL) /*!< D0E1ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC1ADDMT67ZE_Pos (9UL) /*!< IC1ADDMT67ZE (Bit 9) */ + #define R_POE3_POECR4_IC1ADDMT67ZE_Msk (0x200UL) /*!< IC1ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_D1E1ADDMT67ZE_Pos (10UL) /*!< D1E1ADDMT67ZE (Bit 10) */ + #define R_POE3_POECR4_D1E1ADDMT67ZE_Msk (0x400UL) /*!< D1E1ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC3ADDMT67ZE_Pos (11UL) /*!< IC3ADDMT67ZE (Bit 11) */ + #define R_POE3_POECR4_IC3ADDMT67ZE_Msk (0x800UL) /*!< IC3ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC4ADDMT67ZE_Pos (12UL) /*!< IC4ADDMT67ZE (Bit 12) */ + #define R_POE3_POECR4_IC4ADDMT67ZE_Msk (0x1000UL) /*!< IC4ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC5ADDMT67ZE_Pos (13UL) /*!< IC5ADDMT67ZE (Bit 13) */ + #define R_POE3_POECR4_IC5ADDMT67ZE_Msk (0x2000UL) /*!< IC5ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_D0E0ADDMT67ZE_Pos (14UL) /*!< D0E0ADDMT67ZE (Bit 14) */ + #define R_POE3_POECR4_D0E0ADDMT67ZE_Msk (0x4000UL) /*!< D0E0ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_D1E0ADDMT67ZE_Pos (15UL) /*!< D1E0ADDMT67ZE (Bit 15) */ + #define R_POE3_POECR4_D1E0ADDMT67ZE_Msk (0x8000UL) /*!< D1E0ADDMT67ZE (Bitfield-Mask: 0x01) */ +/* ======================================================== POECR5 ========================================================= */ + #define R_POE3_POECR5_D0E1ADDMT0ZE_Pos (0UL) /*!< D0E1ADDMT0ZE (Bit 0) */ + #define R_POE3_POECR5_D0E1ADDMT0ZE_Msk (0x1UL) /*!< D0E1ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_IC1ADDMT0ZE_Pos (1UL) /*!< IC1ADDMT0ZE (Bit 1) */ + #define R_POE3_POECR5_IC1ADDMT0ZE_Msk (0x2UL) /*!< IC1ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_IC2ADDMT0ZE_Pos (2UL) /*!< IC2ADDMT0ZE (Bit 2) */ + #define R_POE3_POECR5_IC2ADDMT0ZE_Msk (0x4UL) /*!< IC2ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_D1E1ADDMT0ZE_Pos (3UL) /*!< D1E1ADDMT0ZE (Bit 3) */ + #define R_POE3_POECR5_D1E1ADDMT0ZE_Msk (0x8UL) /*!< D1E1ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_IC4ADDMT0ZE_Pos (4UL) /*!< IC4ADDMT0ZE (Bit 4) */ + #define R_POE3_POECR5_IC4ADDMT0ZE_Msk (0x10UL) /*!< IC4ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_IC5ADDMT0ZE_Pos (5UL) /*!< IC5ADDMT0ZE (Bit 5) */ + #define R_POE3_POECR5_IC5ADDMT0ZE_Msk (0x20UL) /*!< IC5ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_D0E0ADDMT0ZE_Pos (6UL) /*!< D0E0ADDMT0ZE (Bit 6) */ + #define R_POE3_POECR5_D0E0ADDMT0ZE_Msk (0x40UL) /*!< D0E0ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_D1E0ADDMT0ZE_Pos (7UL) /*!< D1E0ADDMT0ZE (Bit 7) */ + #define R_POE3_POECR5_D1E0ADDMT0ZE_Msk (0x80UL) /*!< D1E0ADDMT0ZE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR4 ========================================================= */ + #define R_POE3_ICSR4_POE10M_Pos (0UL) /*!< POE10M (Bit 0) */ + #define R_POE3_ICSR4_POE10M_Msk (0x3UL) /*!< POE10M (Bitfield-Mask: 0x03) */ + #define R_POE3_ICSR4_PIE4_Pos (8UL) /*!< PIE4 (Bit 8) */ + #define R_POE3_ICSR4_PIE4_Msk (0x100UL) /*!< PIE4 (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR4_POE10E_Pos (9UL) /*!< POE10E (Bit 9) */ + #define R_POE3_ICSR4_POE10E_Msk (0x200UL) /*!< POE10E (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR4_POE10F_Pos (12UL) /*!< POE10F (Bit 12) */ + #define R_POE3_ICSR4_POE10F_Msk (0x1000UL) /*!< POE10F (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR5 ========================================================= */ + #define R_POE3_ICSR5_POE11M_Pos (0UL) /*!< POE11M (Bit 0) */ + #define R_POE3_ICSR5_POE11M_Msk (0x3UL) /*!< POE11M (Bitfield-Mask: 0x03) */ + #define R_POE3_ICSR5_PIE5_Pos (8UL) /*!< PIE5 (Bit 8) */ + #define R_POE3_ICSR5_PIE5_Msk (0x100UL) /*!< PIE5 (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR5_POE11E_Pos (9UL) /*!< POE11E (Bit 9) */ + #define R_POE3_ICSR5_POE11E_Msk (0x200UL) /*!< POE11E (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR5_POE11F_Pos (12UL) /*!< POE11F (Bit 12) */ + #define R_POE3_ICSR5_POE11F_Msk (0x1000UL) /*!< POE11F (Bitfield-Mask: 0x01) */ +/* ========================================================= ALR1 ========================================================== */ + #define R_POE3_ALR1_OLSG0A_Pos (0UL) /*!< OLSG0A (Bit 0) */ + #define R_POE3_ALR1_OLSG0A_Msk (0x1UL) /*!< OLSG0A (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSG0B_Pos (1UL) /*!< OLSG0B (Bit 1) */ + #define R_POE3_ALR1_OLSG0B_Msk (0x2UL) /*!< OLSG0B (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSG1A_Pos (2UL) /*!< OLSG1A (Bit 2) */ + #define R_POE3_ALR1_OLSG1A_Msk (0x4UL) /*!< OLSG1A (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSG1B_Pos (3UL) /*!< OLSG1B (Bit 3) */ + #define R_POE3_ALR1_OLSG1B_Msk (0x8UL) /*!< OLSG1B (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSG2A_Pos (4UL) /*!< OLSG2A (Bit 4) */ + #define R_POE3_ALR1_OLSG2A_Msk (0x10UL) /*!< OLSG2A (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSG2B_Pos (5UL) /*!< OLSG2B (Bit 5) */ + #define R_POE3_ALR1_OLSG2B_Msk (0x20UL) /*!< OLSG2B (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSEN_Pos (7UL) /*!< OLSEN (Bit 7) */ + #define R_POE3_ALR1_OLSEN_Msk (0x80UL) /*!< OLSEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR6 ========================================================= */ + #define R_POE3_ICSR6_OSTSTE_Pos (9UL) /*!< OSTSTE (Bit 9) */ + #define R_POE3_ICSR6_OSTSTE_Msk (0x200UL) /*!< OSTSTE (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR6_OSTSTF_Pos (12UL) /*!< OSTSTF (Bit 12) */ + #define R_POE3_ICSR6_OSTSTF_Msk (0x1000UL) /*!< OSTSTF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR7 ========================================================= */ + #define R_POE3_ICSR7_D0ERR1IE_Pos (4UL) /*!< D0ERR1IE (Bit 4) */ + #define R_POE3_ICSR7_D0ERR1IE_Msk (0x10UL) /*!< D0ERR1IE (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR7_D1ERR1IE_Pos (5UL) /*!< D1ERR1IE (Bit 5) */ + #define R_POE3_ICSR7_D1ERR1IE_Msk (0x20UL) /*!< D1ERR1IE (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR7_D0ERR0IE_Pos (6UL) /*!< D0ERR0IE (Bit 6) */ + #define R_POE3_ICSR7_D0ERR0IE_Msk (0x40UL) /*!< D0ERR0IE (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR7_D1ERR0IE_Pos (7UL) /*!< D1ERR0IE (Bit 7) */ + #define R_POE3_ICSR7_D1ERR0IE_Msk (0x80UL) /*!< D1ERR0IE (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR7_D0ERR1ST_Pos (11UL) /*!< D0ERR1ST (Bit 11) */ + #define R_POE3_ICSR7_D0ERR1ST_Msk (0x800UL) /*!< D0ERR1ST (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR7_D1ERR1ST_Pos (12UL) /*!< D1ERR1ST (Bit 12) */ + #define R_POE3_ICSR7_D1ERR1ST_Msk (0x1000UL) /*!< D1ERR1ST (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR7_D0ERR0ST_Pos (13UL) /*!< D0ERR0ST (Bit 13) */ + #define R_POE3_ICSR7_D0ERR0ST_Msk (0x2000UL) /*!< D0ERR0ST (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR7_D1ERR0ST_Pos (14UL) /*!< D1ERR0ST (Bit 14) */ + #define R_POE3_ICSR7_D1ERR0ST_Msk (0x4000UL) /*!< D1ERR0ST (Bitfield-Mask: 0x01) */ +/* ======================================================== M0SELR1 ======================================================== */ + #define R_POE3_M0SELR1_M0ASEL_Pos (0UL) /*!< M0ASEL (Bit 0) */ + #define R_POE3_M0SELR1_M0ASEL_Msk (0xfUL) /*!< M0ASEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M0SELR1_M0BSEL_Pos (4UL) /*!< M0BSEL (Bit 4) */ + #define R_POE3_M0SELR1_M0BSEL_Msk (0xf0UL) /*!< M0BSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M0SELR2 ======================================================== */ + #define R_POE3_M0SELR2_M0CSEL_Pos (0UL) /*!< M0CSEL (Bit 0) */ + #define R_POE3_M0SELR2_M0CSEL_Msk (0xfUL) /*!< M0CSEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M0SELR2_M0DSEL_Pos (4UL) /*!< M0DSEL (Bit 4) */ + #define R_POE3_M0SELR2_M0DSEL_Msk (0xf0UL) /*!< M0DSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M3SELR ========================================================= */ + #define R_POE3_M3SELR_M3BSEL_Pos (0UL) /*!< M3BSEL (Bit 0) */ + #define R_POE3_M3SELR_M3BSEL_Msk (0xfUL) /*!< M3BSEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M3SELR_M3DSEL_Pos (4UL) /*!< M3DSEL (Bit 4) */ + #define R_POE3_M3SELR_M3DSEL_Msk (0xf0UL) /*!< M3DSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M4SELR1 ======================================================== */ + #define R_POE3_M4SELR1_M4ASEL_Pos (0UL) /*!< M4ASEL (Bit 0) */ + #define R_POE3_M4SELR1_M4ASEL_Msk (0xfUL) /*!< M4ASEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M4SELR1_M4CSEL_Pos (4UL) /*!< M4CSEL (Bit 4) */ + #define R_POE3_M4SELR1_M4CSEL_Msk (0xf0UL) /*!< M4CSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M4SELR2 ======================================================== */ + #define R_POE3_M4SELR2_M4BSEL_Pos (0UL) /*!< M4BSEL (Bit 0) */ + #define R_POE3_M4SELR2_M4BSEL_Msk (0xfUL) /*!< M4BSEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M4SELR2_M4DSEL_Pos (4UL) /*!< M4DSEL (Bit 4) */ + #define R_POE3_M4SELR2_M4DSEL_Msk (0xf0UL) /*!< M4DSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M6SELR ========================================================= */ + #define R_POE3_M6SELR_M6BSEL_Pos (0UL) /*!< M6BSEL (Bit 0) */ + #define R_POE3_M6SELR_M6BSEL_Msk (0xfUL) /*!< M6BSEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M6SELR_M6DSEL_Pos (4UL) /*!< M6DSEL (Bit 4) */ + #define R_POE3_M6SELR_M6DSEL_Msk (0xf0UL) /*!< M6DSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M7SELR1 ======================================================== */ + #define R_POE3_M7SELR1_M7ASEL_Pos (0UL) /*!< M7ASEL (Bit 0) */ + #define R_POE3_M7SELR1_M7ASEL_Msk (0xfUL) /*!< M7ASEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M7SELR1_M7CSEL_Pos (4UL) /*!< M7CSEL (Bit 4) */ + #define R_POE3_M7SELR1_M7CSEL_Msk (0xf0UL) /*!< M7CSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M7SELR2 ======================================================== */ + #define R_POE3_M7SELR2_M7BSEL_Pos (0UL) /*!< M7BSEL (Bit 0) */ + #define R_POE3_M7SELR2_M7BSEL_Msk (0xfUL) /*!< M7BSEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M7SELR2_M7DSEL_Pos (4UL) /*!< M7DSEL (Bit 4) */ + #define R_POE3_M7SELR2_M7DSEL_Msk (0xf0UL) /*!< M7DSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== POEG0GA ======================================================== */ + #define R_POEG0_POEG0GA_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG0_POEG0GA_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG0_POEG0GA_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG0_POEG0GA_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG0_POEG0GA_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG0_POEG0GA_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG0_POEG0GA_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG0_POEG0GA_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG0_POEG0GA_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_D0ERR1ST_Pos (20UL) /*!< D0ERR1ST (Bit 20) */ + #define R_POEG0_POEG0GA_D0ERR1ST_Msk (0x100000UL) /*!< D0ERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_D1ERR1ST_Pos (21UL) /*!< D1ERR1ST (Bit 21) */ + #define R_POEG0_POEG0GA_D1ERR1ST_Msk (0x200000UL) /*!< D1ERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_D0ERR1E_Pos (22UL) /*!< D0ERR1E (Bit 22) */ + #define R_POEG0_POEG0GA_D0ERR1E_Msk (0x400000UL) /*!< D0ERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_D1ERR1E_Pos (23UL) /*!< D1ERR1E (Bit 23) */ + #define R_POEG0_POEG0GA_D1ERR1E_Msk (0x800000UL) /*!< D1ERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_D0ERR0ST_Pos (24UL) /*!< D0ERR0ST (Bit 24) */ + #define R_POEG0_POEG0GA_D0ERR0ST_Msk (0x1000000UL) /*!< D0ERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_D1ERR0ST_Pos (25UL) /*!< D1ERR0ST (Bit 25) */ + #define R_POEG0_POEG0GA_D1ERR0ST_Msk (0x2000000UL) /*!< D1ERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_D0ERR0E_Pos (26UL) /*!< D0ERR0E (Bit 26) */ + #define R_POEG0_POEG0GA_D0ERR0E_Msk (0x4000000UL) /*!< D0ERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_D1ERR0E_Pos (27UL) /*!< D1ERR0E (Bit 27) */ + #define R_POEG0_POEG0GA_D1ERR0E_Msk (0x8000000UL) /*!< D1ERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG0_POEG0GA_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG0_POEG0GA_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG0_POEG0GA_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG0GB ======================================================== */ + #define R_POEG0_POEG0GB_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG0_POEG0GB_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG0_POEG0GB_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG0_POEG0GB_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG0_POEG0GB_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG0_POEG0GB_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG0_POEG0GB_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG0_POEG0GB_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG0_POEG0GB_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_D0ERR1ST_Pos (20UL) /*!< D0ERR1ST (Bit 20) */ + #define R_POEG0_POEG0GB_D0ERR1ST_Msk (0x100000UL) /*!< D0ERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_D1ERR1ST_Pos (21UL) /*!< D1ERR1ST (Bit 21) */ + #define R_POEG0_POEG0GB_D1ERR1ST_Msk (0x200000UL) /*!< D1ERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_D0ERR1E_Pos (22UL) /*!< D0ERR1E (Bit 22) */ + #define R_POEG0_POEG0GB_D0ERR1E_Msk (0x400000UL) /*!< D0ERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_D1ERR1E_Pos (23UL) /*!< D1ERR1E (Bit 23) */ + #define R_POEG0_POEG0GB_D1ERR1E_Msk (0x800000UL) /*!< D1ERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_D0ERR0ST_Pos (24UL) /*!< D0ERR0ST (Bit 24) */ + #define R_POEG0_POEG0GB_D0ERR0ST_Msk (0x1000000UL) /*!< D0ERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_D1ERR0ST_Pos (25UL) /*!< D1ERR0ST (Bit 25) */ + #define R_POEG0_POEG0GB_D1ERR0ST_Msk (0x2000000UL) /*!< D1ERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_D0ERR0E_Pos (26UL) /*!< D0ERR0E (Bit 26) */ + #define R_POEG0_POEG0GB_D0ERR0E_Msk (0x4000000UL) /*!< D0ERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_D1ERR0E_Pos (27UL) /*!< D1ERR0E (Bit 27) */ + #define R_POEG0_POEG0GB_D1ERR0E_Msk (0x8000000UL) /*!< D1ERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG0_POEG0GB_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG0_POEG0GB_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG0_POEG0GB_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG0GC ======================================================== */ + #define R_POEG0_POEG0GC_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG0_POEG0GC_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG0_POEG0GC_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG0_POEG0GC_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG0_POEG0GC_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG0_POEG0GC_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG0_POEG0GC_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG0_POEG0GC_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG0_POEG0GC_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_D0ERR1ST_Pos (20UL) /*!< D0ERR1ST (Bit 20) */ + #define R_POEG0_POEG0GC_D0ERR1ST_Msk (0x100000UL) /*!< D0ERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_D1ERR1ST_Pos (21UL) /*!< D1ERR1ST (Bit 21) */ + #define R_POEG0_POEG0GC_D1ERR1ST_Msk (0x200000UL) /*!< D1ERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_D0ERR1E_Pos (22UL) /*!< D0ERR1E (Bit 22) */ + #define R_POEG0_POEG0GC_D0ERR1E_Msk (0x400000UL) /*!< D0ERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_D1ERR1E_Pos (23UL) /*!< D1ERR1E (Bit 23) */ + #define R_POEG0_POEG0GC_D1ERR1E_Msk (0x800000UL) /*!< D1ERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_D0ERR0ST_Pos (24UL) /*!< D0ERR0ST (Bit 24) */ + #define R_POEG0_POEG0GC_D0ERR0ST_Msk (0x1000000UL) /*!< D0ERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_D1ERR0ST_Pos (25UL) /*!< D1ERR0ST (Bit 25) */ + #define R_POEG0_POEG0GC_D1ERR0ST_Msk (0x2000000UL) /*!< D1ERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_D0ERR0E_Pos (26UL) /*!< D0ERR0E (Bit 26) */ + #define R_POEG0_POEG0GC_D0ERR0E_Msk (0x4000000UL) /*!< D0ERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_D1ERR0E_Pos (27UL) /*!< D1ERR0E (Bit 27) */ + #define R_POEG0_POEG0GC_D1ERR0E_Msk (0x8000000UL) /*!< D1ERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG0_POEG0GC_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG0_POEG0GC_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG0_POEG0GC_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG0GD ======================================================== */ + #define R_POEG0_POEG0GD_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG0_POEG0GD_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG0_POEG0GD_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG0_POEG0GD_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG0_POEG0GD_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG0_POEG0GD_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG0_POEG0GD_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG0_POEG0GD_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG0_POEG0GD_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_D0ERR1ST_Pos (20UL) /*!< D0ERR1ST (Bit 20) */ + #define R_POEG0_POEG0GD_D0ERR1ST_Msk (0x100000UL) /*!< D0ERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_D1ERR1ST_Pos (21UL) /*!< D1ERR1ST (Bit 21) */ + #define R_POEG0_POEG0GD_D1ERR1ST_Msk (0x200000UL) /*!< D1ERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_D0ERR1E_Pos (22UL) /*!< D0ERR1E (Bit 22) */ + #define R_POEG0_POEG0GD_D0ERR1E_Msk (0x400000UL) /*!< D0ERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_D1ERR1E_Pos (23UL) /*!< D1ERR1E (Bit 23) */ + #define R_POEG0_POEG0GD_D1ERR1E_Msk (0x800000UL) /*!< D1ERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_D0ERR0ST_Pos (24UL) /*!< D0ERR0ST (Bit 24) */ + #define R_POEG0_POEG0GD_D0ERR0ST_Msk (0x1000000UL) /*!< D0ERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_D1ERR0ST_Pos (25UL) /*!< D1ERR0ST (Bit 25) */ + #define R_POEG0_POEG0GD_D1ERR0ST_Msk (0x2000000UL) /*!< D1ERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_D0ERR0E_Pos (26UL) /*!< D0ERR0E (Bit 26) */ + #define R_POEG0_POEG0GD_D0ERR0E_Msk (0x4000000UL) /*!< D0ERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_D1ERR0E_Pos (27UL) /*!< D1ERR0E (Bit 27) */ + #define R_POEG0_POEG0GD_D1ERR0E_Msk (0x8000000UL) /*!< D1ERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG0_POEG0GD_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG0_POEG0GD_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG0_POEG0GD_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_DSMIF0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DSSEICR ======================================================== */ + #define R_DSMIF0_DSSEICR_ISEL_Pos (0UL) /*!< ISEL (Bit 0) */ + #define R_DSMIF0_DSSEICR_ISEL_Msk (0x1UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSSEICR_ISEH_Pos (1UL) /*!< ISEH (Bit 1) */ + #define R_DSMIF0_DSSEICR_ISEH_Msk (0x2UL) /*!< ISEH (Bitfield-Mask: 0x01) */ +/* ======================================================== DSSECSR ======================================================== */ + #define R_DSMIF0_DSSECSR_SEDM_Pos (0UL) /*!< SEDM (Bit 0) */ + #define R_DSMIF0_DSSECSR_SEDM_Msk (0x7UL) /*!< SEDM (Bitfield-Mask: 0x07) */ +/* ======================================================== DSSELTR ======================================================== */ + #define R_DSMIF0_DSSELTR_SCMPTBL_Pos (0UL) /*!< SCMPTBL (Bit 0) */ + #define R_DSMIF0_DSSELTR_SCMPTBL_Msk (0x3ffffUL) /*!< SCMPTBL (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== DSSEHTR ======================================================== */ + #define R_DSMIF0_DSSEHTR_SCMPTBH_Pos (0UL) /*!< SCMPTBH (Bit 0) */ + #define R_DSMIF0_DSSEHTR_SCMPTBH_Msk (0x3ffffUL) /*!< SCMPTBH (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== DSSECR ========================================================= */ + #define R_DSMIF0_DSSECR_SEEL_Pos (0UL) /*!< SEEL (Bit 0) */ + #define R_DSMIF0_DSSECR_SEEL_Msk (0x1UL) /*!< SEEL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSSECR_SEEH_Pos (1UL) /*!< SEEH (Bit 1) */ + #define R_DSMIF0_DSSECR_SEEH_Msk (0x2UL) /*!< SEEH (Bitfield-Mask: 0x01) */ +/* ======================================================== DSSECDR ======================================================== */ + #define R_DSMIF0_DSSECDR_SECDR_Pos (0UL) /*!< SECDR (Bit 0) */ + #define R_DSMIF0_DSSECDR_SECDR_Msk (0xffffUL) /*!< SECDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSCMSR ========================================================= */ + #define R_DSMIF0_DSCMSR_DFS_Pos (0UL) /*!< DFS (Bit 0) */ + #define R_DSMIF0_DSCMSR_DFS_Msk (0x1UL) /*!< DFS (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCMSR_CISM_Pos (1UL) /*!< CISM (Bit 1) */ + #define R_DSMIF0_DSCMSR_CISM_Msk (0x6UL) /*!< CISM (Bitfield-Mask: 0x03) */ +/* ======================================================== DSCICR ========================================================= */ + #define R_DSMIF0_DSCICR_IUCE_Pos (0UL) /*!< IUCE (Bit 0) */ + #define R_DSMIF0_DSCICR_IUCE_Msk (0x1UL) /*!< IUCE (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCICR_IAUCE_Pos (1UL) /*!< IAUCE (Bit 1) */ + #define R_DSMIF0_DSCICR_IAUCE_Msk (0x2UL) /*!< IAUCE (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCICR_IBUCE_Pos (2UL) /*!< IBUCE (Bit 2) */ + #define R_DSMIF0_DSCICR_IBUCE_Msk (0x4UL) /*!< IBUCE (Bitfield-Mask: 0x01) */ +/* ======================================================= DSCSTRTR ======================================================== */ + #define R_DSMIF0_DSCSTRTR_STRTRG0_Pos (0UL) /*!< STRTRG0 (Bit 0) */ + #define R_DSMIF0_DSCSTRTR_STRTRG0_Msk (0x1UL) /*!< STRTRG0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSTRTR_STRTRG1_Pos (1UL) /*!< STRTRG1 (Bit 1) */ + #define R_DSMIF0_DSCSTRTR_STRTRG1_Msk (0x2UL) /*!< STRTRG1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSTRTR_STRTRG2_Pos (2UL) /*!< STRTRG2 (Bit 2) */ + #define R_DSMIF0_DSCSTRTR_STRTRG2_Msk (0x4UL) /*!< STRTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSCSTPTR ======================================================== */ + #define R_DSMIF0_DSCSTPTR_STPTRG0_Pos (0UL) /*!< STPTRG0 (Bit 0) */ + #define R_DSMIF0_DSCSTPTR_STPTRG0_Msk (0x1UL) /*!< STPTRG0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSTPTR_STPTRG1_Pos (1UL) /*!< STPTRG1 (Bit 1) */ + #define R_DSMIF0_DSCSTPTR_STPTRG1_Msk (0x2UL) /*!< STPTRG1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSTPTR_STPTRG2_Pos (2UL) /*!< STPTRG2 (Bit 2) */ + #define R_DSMIF0_DSCSTPTR_STPTRG2_Msk (0x4UL) /*!< STPTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCESR ========================================================= */ + #define R_DSMIF0_DSCESR_SCF0_Pos (0UL) /*!< SCF0 (Bit 0) */ + #define R_DSMIF0_DSCESR_SCF0_Msk (0x1UL) /*!< SCF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_SCF1_Pos (1UL) /*!< SCF1 (Bit 1) */ + #define R_DSMIF0_DSCESR_SCF1_Msk (0x2UL) /*!< SCF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_SCF2_Pos (2UL) /*!< SCF2 (Bit 2) */ + #define R_DSMIF0_DSCESR_SCF2_Msk (0x4UL) /*!< SCF2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_SUMERRL_Pos (16UL) /*!< SUMERRL (Bit 16) */ + #define R_DSMIF0_DSCESR_SUMERRL_Msk (0x10000UL) /*!< SUMERRL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_SUMERRH_Pos (17UL) /*!< SUMERRH (Bit 17) */ + #define R_DSMIF0_DSCESR_SUMERRH_Msk (0x20000UL) /*!< SUMERRH (Bitfield-Mask: 0x01) */ +/* ======================================================= DSCOCESR ======================================================== */ + #define R_DSMIF0_DSCOCESR_OC0FL0_Pos (0UL) /*!< OC0FL0 (Bit 0) */ + #define R_DSMIF0_DSCOCESR_OC0FL0_Msk (0x1UL) /*!< OC0FL0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC0FL1_Pos (1UL) /*!< OC0FL1 (Bit 1) */ + #define R_DSMIF0_DSCOCESR_OC0FL1_Msk (0x2UL) /*!< OC0FL1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC0FL2_Pos (2UL) /*!< OC0FL2 (Bit 2) */ + #define R_DSMIF0_DSCOCESR_OC0FL2_Msk (0x4UL) /*!< OC0FL2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC0FH0_Pos (4UL) /*!< OC0FH0 (Bit 4) */ + #define R_DSMIF0_DSCOCESR_OC0FH0_Msk (0x10UL) /*!< OC0FH0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC0FH1_Pos (5UL) /*!< OC0FH1 (Bit 5) */ + #define R_DSMIF0_DSCOCESR_OC0FH1_Msk (0x20UL) /*!< OC0FH1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC0FH2_Pos (6UL) /*!< OC0FH2 (Bit 6) */ + #define R_DSMIF0_DSCOCESR_OC0FH2_Msk (0x40UL) /*!< OC0FH2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC1FL0_Pos (8UL) /*!< OC1FL0 (Bit 8) */ + #define R_DSMIF0_DSCOCESR_OC1FL0_Msk (0x100UL) /*!< OC1FL0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC1FL1_Pos (9UL) /*!< OC1FL1 (Bit 9) */ + #define R_DSMIF0_DSCOCESR_OC1FL1_Msk (0x200UL) /*!< OC1FL1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC1FL2_Pos (10UL) /*!< OC1FL2 (Bit 10) */ + #define R_DSMIF0_DSCOCESR_OC1FL2_Msk (0x400UL) /*!< OC1FL2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC1FH0_Pos (12UL) /*!< OC1FH0 (Bit 12) */ + #define R_DSMIF0_DSCOCESR_OC1FH0_Msk (0x1000UL) /*!< OC1FH0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC1FH1_Pos (13UL) /*!< OC1FH1 (Bit 13) */ + #define R_DSMIF0_DSCOCESR_OC1FH1_Msk (0x2000UL) /*!< OC1FH1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC1FH2_Pos (14UL) /*!< OC1FH2 (Bit 14) */ + #define R_DSMIF0_DSCOCESR_OC1FH2_Msk (0x4000UL) /*!< OC1FH2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC2FL0_Pos (16UL) /*!< OC2FL0 (Bit 16) */ + #define R_DSMIF0_DSCOCESR_OC2FL0_Msk (0x10000UL) /*!< OC2FL0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC2FL1_Pos (17UL) /*!< OC2FL1 (Bit 17) */ + #define R_DSMIF0_DSCOCESR_OC2FL1_Msk (0x20000UL) /*!< OC2FL1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC2FL2_Pos (18UL) /*!< OC2FL2 (Bit 18) */ + #define R_DSMIF0_DSCOCESR_OC2FL2_Msk (0x40000UL) /*!< OC2FL2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC2FH0_Pos (20UL) /*!< OC2FH0 (Bit 20) */ + #define R_DSMIF0_DSCOCESR_OC2FH0_Msk (0x100000UL) /*!< OC2FH0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC2FH1_Pos (21UL) /*!< OC2FH1 (Bit 21) */ + #define R_DSMIF0_DSCOCESR_OC2FH1_Msk (0x200000UL) /*!< OC2FH1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESR_OC2FH2_Pos (22UL) /*!< OC2FH2 (Bit 22) */ + #define R_DSMIF0_DSCOCESR_OC2FH2_Msk (0x400000UL) /*!< OC2FH2 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSCOCNSR ======================================================== */ + #define R_DSMIF0_DSCOCNSR_OWD0N0_Pos (0UL) /*!< OWD0N0 (Bit 0) */ + #define R_DSMIF0_DSCOCNSR_OWD0N0_Msk (0x1UL) /*!< OWD0N0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSR_OWD0N1_Pos (1UL) /*!< OWD0N1 (Bit 1) */ + #define R_DSMIF0_DSCOCNSR_OWD0N1_Msk (0x2UL) /*!< OWD0N1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSR_OWD0N2_Pos (2UL) /*!< OWD0N2 (Bit 2) */ + #define R_DSMIF0_DSCOCNSR_OWD0N2_Msk (0x4UL) /*!< OWD0N2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSR_OWD1N0_Pos (4UL) /*!< OWD1N0 (Bit 4) */ + #define R_DSMIF0_DSCOCNSR_OWD1N0_Msk (0x10UL) /*!< OWD1N0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSR_OWD1N1_Pos (5UL) /*!< OWD1N1 (Bit 5) */ + #define R_DSMIF0_DSCOCNSR_OWD1N1_Msk (0x20UL) /*!< OWD1N1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSR_OWD1N2_Pos (6UL) /*!< OWD1N2 (Bit 6) */ + #define R_DSMIF0_DSCOCNSR_OWD1N2_Msk (0x40UL) /*!< OWD1N2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSR_OWD2N0_Pos (8UL) /*!< OWD2N0 (Bit 8) */ + #define R_DSMIF0_DSCOCNSR_OWD2N0_Msk (0x100UL) /*!< OWD2N0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSR_OWD2N1_Pos (9UL) /*!< OWD2N1 (Bit 9) */ + #define R_DSMIF0_DSCOCNSR_OWD2N1_Msk (0x200UL) /*!< OWD2N1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSR_OWD2N2_Pos (10UL) /*!< OWD2N2 (Bit 10) */ + #define R_DSMIF0_DSCOCNSR_OWD2N2_Msk (0x400UL) /*!< OWD2N2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSR_OWD3N0_Pos (12UL) /*!< OWD3N0 (Bit 12) */ + #define R_DSMIF0_DSCOCNSR_OWD3N0_Msk (0x1000UL) /*!< OWD3N0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSR_OWD3N1_Pos (13UL) /*!< OWD3N1 (Bit 13) */ + #define R_DSMIF0_DSCOCNSR_OWD3N1_Msk (0x2000UL) /*!< OWD3N1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSR_OWD3N2_Pos (14UL) /*!< OWD3N2 (Bit 14) */ + #define R_DSMIF0_DSCOCNSR_OWD3N2_Msk (0x4000UL) /*!< OWD3N2 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSCOCRMR ======================================================== */ + #define R_DSMIF0_DSCOCRMR_OC0CMPL0_Pos (0UL) /*!< OC0CMPL0 (Bit 0) */ + #define R_DSMIF0_DSCOCRMR_OC0CMPL0_Msk (0x1UL) /*!< OC0CMPL0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC0CMPL1_Pos (1UL) /*!< OC0CMPL1 (Bit 1) */ + #define R_DSMIF0_DSCOCRMR_OC0CMPL1_Msk (0x2UL) /*!< OC0CMPL1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC0CMPL2_Pos (2UL) /*!< OC0CMPL2 (Bit 2) */ + #define R_DSMIF0_DSCOCRMR_OC0CMPL2_Msk (0x4UL) /*!< OC0CMPL2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC0CMPH0_Pos (4UL) /*!< OC0CMPH0 (Bit 4) */ + #define R_DSMIF0_DSCOCRMR_OC0CMPH0_Msk (0x10UL) /*!< OC0CMPH0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC0CMPH1_Pos (5UL) /*!< OC0CMPH1 (Bit 5) */ + #define R_DSMIF0_DSCOCRMR_OC0CMPH1_Msk (0x20UL) /*!< OC0CMPH1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC0CMPH2_Pos (6UL) /*!< OC0CMPH2 (Bit 6) */ + #define R_DSMIF0_DSCOCRMR_OC0CMPH2_Msk (0x40UL) /*!< OC0CMPH2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC1CMPL0_Pos (8UL) /*!< OC1CMPL0 (Bit 8) */ + #define R_DSMIF0_DSCOCRMR_OC1CMPL0_Msk (0x100UL) /*!< OC1CMPL0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC1CMPL1_Pos (9UL) /*!< OC1CMPL1 (Bit 9) */ + #define R_DSMIF0_DSCOCRMR_OC1CMPL1_Msk (0x200UL) /*!< OC1CMPL1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC1CMPL2_Pos (10UL) /*!< OC1CMPL2 (Bit 10) */ + #define R_DSMIF0_DSCOCRMR_OC1CMPL2_Msk (0x400UL) /*!< OC1CMPL2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC1CMPH0_Pos (12UL) /*!< OC1CMPH0 (Bit 12) */ + #define R_DSMIF0_DSCOCRMR_OC1CMPH0_Msk (0x1000UL) /*!< OC1CMPH0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC1CMPH1_Pos (13UL) /*!< OC1CMPH1 (Bit 13) */ + #define R_DSMIF0_DSCOCRMR_OC1CMPH1_Msk (0x2000UL) /*!< OC1CMPH1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC1CMPH2_Pos (14UL) /*!< OC1CMPH2 (Bit 14) */ + #define R_DSMIF0_DSCOCRMR_OC1CMPH2_Msk (0x4000UL) /*!< OC1CMPH2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC2CMPL0_Pos (16UL) /*!< OC2CMPL0 (Bit 16) */ + #define R_DSMIF0_DSCOCRMR_OC2CMPL0_Msk (0x10000UL) /*!< OC2CMPL0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC2CMPL1_Pos (17UL) /*!< OC2CMPL1 (Bit 17) */ + #define R_DSMIF0_DSCOCRMR_OC2CMPL1_Msk (0x20000UL) /*!< OC2CMPL1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC2CMPL2_Pos (18UL) /*!< OC2CMPL2 (Bit 18) */ + #define R_DSMIF0_DSCOCRMR_OC2CMPL2_Msk (0x40000UL) /*!< OC2CMPL2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC2CMPH0_Pos (20UL) /*!< OC2CMPH0 (Bit 20) */ + #define R_DSMIF0_DSCOCRMR_OC2CMPH0_Msk (0x100000UL) /*!< OC2CMPH0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC2CMPH1_Pos (21UL) /*!< OC2CMPH1 (Bit 21) */ + #define R_DSMIF0_DSCOCRMR_OC2CMPH1_Msk (0x200000UL) /*!< OC2CMPH1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCRMR_OC2CMPH2_Pos (22UL) /*!< OC2CMPH2 (Bit 22) */ + #define R_DSMIF0_DSCOCRMR_OC2CMPH2_Msk (0x400000UL) /*!< OC2CMPH2 (Bitfield-Mask: 0x01) */ +/* ========================================================= DSCSR ========================================================= */ + #define R_DSMIF0_DSCSR_DUF0_Pos (0UL) /*!< DUF0 (Bit 0) */ + #define R_DSMIF0_DSCSR_DUF0_Msk (0x1UL) /*!< DUF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSR_DUF1_Pos (1UL) /*!< DUF1 (Bit 1) */ + #define R_DSMIF0_DSCSR_DUF1_Msk (0x2UL) /*!< DUF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSR_DUF2_Pos (2UL) /*!< DUF2 (Bit 2) */ + #define R_DSMIF0_DSCSR_DUF2_Msk (0x4UL) /*!< DUF2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSR_CAUF0_Pos (4UL) /*!< CAUF0 (Bit 4) */ + #define R_DSMIF0_DSCSR_CAUF0_Msk (0x10UL) /*!< CAUF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSR_CAUF1_Pos (5UL) /*!< CAUF1 (Bit 5) */ + #define R_DSMIF0_DSCSR_CAUF1_Msk (0x20UL) /*!< CAUF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSR_CAUF2_Pos (6UL) /*!< CAUF2 (Bit 6) */ + #define R_DSMIF0_DSCSR_CAUF2_Msk (0x40UL) /*!< CAUF2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSR_CBUF0_Pos (8UL) /*!< CBUF0 (Bit 8) */ + #define R_DSMIF0_DSCSR_CBUF0_Msk (0x100UL) /*!< CBUF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSR_CBUF1_Pos (9UL) /*!< CBUF1 (Bit 9) */ + #define R_DSMIF0_DSCSR_CBUF1_Msk (0x200UL) /*!< CBUF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSR_CBUF2_Pos (10UL) /*!< CBUF2 (Bit 10) */ + #define R_DSMIF0_DSCSR_CBUF2_Msk (0x400UL) /*!< CBUF2 (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCSSR ========================================================= */ + #define R_DSMIF0_DSCSSR_CHSTATE0_Pos (0UL) /*!< CHSTATE0 (Bit 0) */ + #define R_DSMIF0_DSCSSR_CHSTATE0_Msk (0x1UL) /*!< CHSTATE0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSSR_CHSTATE1_Pos (4UL) /*!< CHSTATE1 (Bit 4) */ + #define R_DSMIF0_DSCSSR_CHSTATE1_Msk (0x10UL) /*!< CHSTATE1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSSR_CHSTATE2_Pos (8UL) /*!< CHSTATE2 (Bit 8) */ + #define R_DSMIF0_DSCSSR_CHSTATE2_Msk (0x100UL) /*!< CHSTATE2 (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCESCR ======================================================== */ + #define R_DSMIF0_DSCESCR_CLRSCF0_Pos (0UL) /*!< CLRSCF0 (Bit 0) */ + #define R_DSMIF0_DSCESCR_CLRSCF0_Msk (0x1UL) /*!< CLRSCF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLRSCF1_Pos (1UL) /*!< CLRSCF1 (Bit 1) */ + #define R_DSMIF0_DSCESCR_CLRSCF1_Msk (0x2UL) /*!< CLRSCF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLRSCF2_Pos (2UL) /*!< CLRSCF2 (Bit 2) */ + #define R_DSMIF0_DSCESCR_CLRSCF2_Msk (0x4UL) /*!< CLRSCF2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLRSUMERRL_Pos (16UL) /*!< CLRSUMERRL (Bit 16) */ + #define R_DSMIF0_DSCESCR_CLRSUMERRL_Msk (0x10000UL) /*!< CLRSUMERRL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLRSUMERRH_Pos (17UL) /*!< CLRSUMERRH (Bit 17) */ + #define R_DSMIF0_DSCESCR_CLRSUMERRH_Msk (0x20000UL) /*!< CLRSUMERRH (Bitfield-Mask: 0x01) */ +/* ======================================================= DSCOCESCR ======================================================= */ + #define R_DSMIF0_DSCOCESCR_CLROC0FL0_Pos (0UL) /*!< CLROC0FL0 (Bit 0) */ + #define R_DSMIF0_DSCOCESCR_CLROC0FL0_Msk (0x1UL) /*!< CLROC0FL0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC0FL1_Pos (1UL) /*!< CLROC0FL1 (Bit 1) */ + #define R_DSMIF0_DSCOCESCR_CLROC0FL1_Msk (0x2UL) /*!< CLROC0FL1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC0FL2_Pos (2UL) /*!< CLROC0FL2 (Bit 2) */ + #define R_DSMIF0_DSCOCESCR_CLROC0FL2_Msk (0x4UL) /*!< CLROC0FL2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC0FH0_Pos (4UL) /*!< CLROC0FH0 (Bit 4) */ + #define R_DSMIF0_DSCOCESCR_CLROC0FH0_Msk (0x10UL) /*!< CLROC0FH0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC0FH1_Pos (5UL) /*!< CLROC0FH1 (Bit 5) */ + #define R_DSMIF0_DSCOCESCR_CLROC0FH1_Msk (0x20UL) /*!< CLROC0FH1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC0FH2_Pos (6UL) /*!< CLROC0FH2 (Bit 6) */ + #define R_DSMIF0_DSCOCESCR_CLROC0FH2_Msk (0x40UL) /*!< CLROC0FH2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC1FL0_Pos (8UL) /*!< CLROC1FL0 (Bit 8) */ + #define R_DSMIF0_DSCOCESCR_CLROC1FL0_Msk (0x100UL) /*!< CLROC1FL0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC1FL1_Pos (9UL) /*!< CLROC1FL1 (Bit 9) */ + #define R_DSMIF0_DSCOCESCR_CLROC1FL1_Msk (0x200UL) /*!< CLROC1FL1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC1FL2_Pos (10UL) /*!< CLROC1FL2 (Bit 10) */ + #define R_DSMIF0_DSCOCESCR_CLROC1FL2_Msk (0x400UL) /*!< CLROC1FL2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC1FH0_Pos (12UL) /*!< CLROC1FH0 (Bit 12) */ + #define R_DSMIF0_DSCOCESCR_CLROC1FH0_Msk (0x1000UL) /*!< CLROC1FH0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC1FH1_Pos (13UL) /*!< CLROC1FH1 (Bit 13) */ + #define R_DSMIF0_DSCOCESCR_CLROC1FH1_Msk (0x2000UL) /*!< CLROC1FH1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC1FH2_Pos (14UL) /*!< CLROC1FH2 (Bit 14) */ + #define R_DSMIF0_DSCOCESCR_CLROC1FH2_Msk (0x4000UL) /*!< CLROC1FH2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC2FL0_Pos (16UL) /*!< CLROC2FL0 (Bit 16) */ + #define R_DSMIF0_DSCOCESCR_CLROC2FL0_Msk (0x10000UL) /*!< CLROC2FL0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC2FL1_Pos (17UL) /*!< CLROC2FL1 (Bit 17) */ + #define R_DSMIF0_DSCOCESCR_CLROC2FL1_Msk (0x20000UL) /*!< CLROC2FL1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC2FL2_Pos (18UL) /*!< CLROC2FL2 (Bit 18) */ + #define R_DSMIF0_DSCOCESCR_CLROC2FL2_Msk (0x40000UL) /*!< CLROC2FL2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC2FH0_Pos (20UL) /*!< CLROC2FH0 (Bit 20) */ + #define R_DSMIF0_DSCOCESCR_CLROC2FH0_Msk (0x100000UL) /*!< CLROC2FH0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC2FH1_Pos (21UL) /*!< CLROC2FH1 (Bit 21) */ + #define R_DSMIF0_DSCOCESCR_CLROC2FH1_Msk (0x200000UL) /*!< CLROC2FH1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCESCR_CLROC2FH2_Pos (22UL) /*!< CLROC2FH2 (Bit 22) */ + #define R_DSMIF0_DSCOCESCR_CLROC2FH2_Msk (0x400000UL) /*!< CLROC2FH2 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSCOCNSCR ======================================================= */ + #define R_DSMIF0_DSCOCNSCR_CLROWD0N0_Pos (0UL) /*!< CLROWD0N0 (Bit 0) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD0N0_Msk (0x1UL) /*!< CLROWD0N0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD0N1_Pos (1UL) /*!< CLROWD0N1 (Bit 1) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD0N1_Msk (0x2UL) /*!< CLROWD0N1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD0N2_Pos (2UL) /*!< CLROWD0N2 (Bit 2) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD0N2_Msk (0x4UL) /*!< CLROWD0N2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD1N0_Pos (4UL) /*!< CLROWD1N0 (Bit 4) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD1N0_Msk (0x10UL) /*!< CLROWD1N0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD1N1_Pos (5UL) /*!< CLROWD1N1 (Bit 5) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD1N1_Msk (0x20UL) /*!< CLROWD1N1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD1N2_Pos (6UL) /*!< CLROWD1N2 (Bit 6) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD1N2_Msk (0x40UL) /*!< CLROWD1N2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD2N0_Pos (8UL) /*!< CLROWD2N0 (Bit 8) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD2N0_Msk (0x100UL) /*!< CLROWD2N0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD2N1_Pos (9UL) /*!< CLROWD2N1 (Bit 9) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD2N1_Msk (0x200UL) /*!< CLROWD2N1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD2N2_Pos (10UL) /*!< CLROWD2N2 (Bit 10) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD2N2_Msk (0x400UL) /*!< CLROWD2N2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD3N0_Pos (12UL) /*!< CLROWD3N0 (Bit 12) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD3N0_Msk (0x1000UL) /*!< CLROWD3N0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD3N1_Pos (13UL) /*!< CLROWD3N1 (Bit 13) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD3N1_Msk (0x2000UL) /*!< CLROWD3N1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD3N2_Pos (14UL) /*!< CLROWD3N2 (Bit 14) */ + #define R_DSMIF0_DSCOCNSCR_CLROWD3N2_Msk (0x4000UL) /*!< CLROWD3N2 (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCSCR ========================================================= */ + #define R_DSMIF0_DSCSCR_CLRDUF0_Pos (0UL) /*!< CLRDUF0 (Bit 0) */ + #define R_DSMIF0_DSCSCR_CLRDUF0_Msk (0x1UL) /*!< CLRDUF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSCR_CLRDUF1_Pos (1UL) /*!< CLRDUF1 (Bit 1) */ + #define R_DSMIF0_DSCSCR_CLRDUF1_Msk (0x2UL) /*!< CLRDUF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSCR_CLRDUF2_Pos (2UL) /*!< CLRDUF2 (Bit 2) */ + #define R_DSMIF0_DSCSCR_CLRDUF2_Msk (0x4UL) /*!< CLRDUF2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSCR_CLRCAUF0_Pos (4UL) /*!< CLRCAUF0 (Bit 4) */ + #define R_DSMIF0_DSCSCR_CLRCAUF0_Msk (0x10UL) /*!< CLRCAUF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSCR_CLRCAUF1_Pos (5UL) /*!< CLRCAUF1 (Bit 5) */ + #define R_DSMIF0_DSCSCR_CLRCAUF1_Msk (0x20UL) /*!< CLRCAUF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSCR_CLRCAUF2_Pos (6UL) /*!< CLRCAUF2 (Bit 6) */ + #define R_DSMIF0_DSCSCR_CLRCAUF2_Msk (0x40UL) /*!< CLRCAUF2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSCR_CLRCBUF0_Pos (8UL) /*!< CLRCBUF0 (Bit 8) */ + #define R_DSMIF0_DSCSCR_CLRCBUF0_Msk (0x100UL) /*!< CLRCBUF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSCR_CLRCBUF1_Pos (9UL) /*!< CLRCBUF1 (Bit 9) */ + #define R_DSMIF0_DSCSCR_CLRCBUF1_Msk (0x200UL) /*!< CLRCBUF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSCR_CLRCBUF2_Pos (10UL) /*!< CLRCBUF2 (Bit 10) */ + #define R_DSMIF0_DSCSCR_CLRCBUF2_Msk (0x400UL) /*!< CLRCBUF2 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_HDSLD0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SYS_CTRL ======================================================== */ + #define R_HDSLD0_SYS_CTRL_OEN_Pos (0UL) /*!< OEN (Bit 0) */ + #define R_HDSLD0_SYS_CTRL_OEN_Msk (0x1UL) /*!< OEN (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_SYS_CTRL_SPOL_Pos (1UL) /*!< SPOL (Bit 1) */ + #define R_HDSLD0_SYS_CTRL_SPOL_Msk (0x2UL) /*!< SPOL (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_SYS_CTRL_LOOP_Pos (4UL) /*!< LOOP (Bit 4) */ + #define R_HDSLD0_SYS_CTRL_LOOP_Msk (0x10UL) /*!< LOOP (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_SYS_CTRL_FRST_Pos (5UL) /*!< FRST (Bit 5) */ + #define R_HDSLD0_SYS_CTRL_FRST_Msk (0x20UL) /*!< FRST (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_SYS_CTRL_MRST_Pos (6UL) /*!< MRST (Bit 6) */ + #define R_HDSLD0_SYS_CTRL_MRST_Msk (0x40UL) /*!< MRST (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_SYS_CTRL_PRST_Pos (7UL) /*!< PRST (Bit 7) */ + #define R_HDSLD0_SYS_CTRL_PRST_Msk (0x80UL) /*!< PRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SYNC_CTRL ======================================================= */ + #define R_HDSLD0_SYNC_CTRL_ES_Pos (0UL) /*!< ES (Bit 0) */ + #define R_HDSLD0_SYNC_CTRL_ES_Msk (0xffUL) /*!< ES (Bitfield-Mask: 0xff) */ +/* ======================================================= MASTER_QM ======================================================= */ + #define R_HDSLD0_MASTER_QM_QM_Pos (0UL) /*!< QM (Bit 0) */ + #define R_HDSLD0_MASTER_QM_QM_Msk (0xfUL) /*!< QM (Bitfield-Mask: 0x0f) */ + #define R_HDSLD0_MASTER_QM_LINK_Pos (7UL) /*!< LINK (Bit 7) */ + #define R_HDSLD0_MASTER_QM_LINK_Msk (0x80UL) /*!< LINK (Bitfield-Mask: 0x01) */ +/* ======================================================== EVENT_H ======================================================== */ + #define R_HDSLD0_EVENT_H_PRST_Pos (0UL) /*!< PRST (Bit 0) */ + #define R_HDSLD0_EVENT_H_PRST_Msk (0x1UL) /*!< PRST (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_EVENT_H_DTE_Pos (1UL) /*!< DTE (Bit 1) */ + #define R_HDSLD0_EVENT_H_DTE_Msk (0x2UL) /*!< DTE (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_EVENT_H_POS_Pos (3UL) /*!< POS (Bit 3) */ + #define R_HDSLD0_EVENT_H_POS_Msk (0x8UL) /*!< POS (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_EVENT_H_SUM_Pos (6UL) /*!< SUM (Bit 6) */ + #define R_HDSLD0_EVENT_H_SUM_Msk (0x40UL) /*!< SUM (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_EVENT_H_INT_Pos (7UL) /*!< INT (Bit 7) */ + #define R_HDSLD0_EVENT_H_INT_Msk (0x80UL) /*!< INT (Bitfield-Mask: 0x01) */ +/* ======================================================== EVENT_L ======================================================== */ + #define R_HDSLD0_EVENT_L_FREL_Pos (1UL) /*!< FREL (Bit 1) */ + #define R_HDSLD0_EVENT_L_FREL_Msk (0x2UL) /*!< FREL (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_EVENT_L_QMLW_Pos (2UL) /*!< QMLW (Bit 2) */ + #define R_HDSLD0_EVENT_L_QMLW_Msk (0x4UL) /*!< QMLW (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_EVENT_L_ANS_Pos (4UL) /*!< ANS (Bit 4) */ + #define R_HDSLD0_EVENT_L_ANS_Msk (0x10UL) /*!< ANS (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_EVENT_L_MIN_Pos (5UL) /*!< MIN (Bit 5) */ + #define R_HDSLD0_EVENT_L_MIN_Msk (0x20UL) /*!< MIN (Bitfield-Mask: 0x01) */ +/* ======================================================== MASK_H ========================================================= */ + #define R_HDSLD0_MASK_H_MPRST_Pos (0UL) /*!< MPRST (Bit 0) */ + #define R_HDSLD0_MASK_H_MPRST_Msk (0x1UL) /*!< MPRST (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_MASK_H_MDTE_Pos (1UL) /*!< MDTE (Bit 1) */ + #define R_HDSLD0_MASK_H_MDTE_Msk (0x2UL) /*!< MDTE (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_MASK_H_MPOS_Pos (3UL) /*!< MPOS (Bit 3) */ + #define R_HDSLD0_MASK_H_MPOS_Msk (0x8UL) /*!< MPOS (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_MASK_H_MSUM_Pos (6UL) /*!< MSUM (Bit 6) */ + #define R_HDSLD0_MASK_H_MSUM_Msk (0x40UL) /*!< MSUM (Bitfield-Mask: 0x01) */ +/* ======================================================== MASK_L ========================================================= */ + #define R_HDSLD0_MASK_L_MFREL_Pos (1UL) /*!< MFREL (Bit 1) */ + #define R_HDSLD0_MASK_L_MFREL_Msk (0x2UL) /*!< MFREL (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_MASK_L_MQMLW_Pos (2UL) /*!< MQMLW (Bit 2) */ + #define R_HDSLD0_MASK_L_MQMLW_Msk (0x4UL) /*!< MQMLW (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_MASK_L_MANS_Pos (4UL) /*!< MANS (Bit 4) */ + #define R_HDSLD0_MASK_L_MANS_Msk (0x10UL) /*!< MANS (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_MASK_L_MMIN_Pos (5UL) /*!< MMIN (Bit 5) */ + #define R_HDSLD0_MASK_L_MMIN_Msk (0x20UL) /*!< MMIN (Bitfield-Mask: 0x01) */ +/* ======================================================= MASK_SUM ======================================================== */ + #define R_HDSLD0_MASK_SUM_MSUM_Pos (0UL) /*!< MSUM (Bit 0) */ + #define R_HDSLD0_MASK_SUM_MSUM_Msk (0xffUL) /*!< MSUM (Bitfield-Mask: 0xff) */ +/* ========================================================= EDGES ========================================================= */ + #define R_HDSLD0_EDGES_EDGES_Pos (0UL) /*!< EDGES (Bit 0) */ + #define R_HDSLD0_EDGES_EDGES_Msk (0xffUL) /*!< EDGES (Bitfield-Mask: 0xff) */ +/* ========================================================= DELAY ========================================================= */ + #define R_HDSLD0_DELAY_CBLDLY_Pos (0UL) /*!< CBLDLY (Bit 0) */ + #define R_HDSLD0_DELAY_CBLDLY_Msk (0xfUL) /*!< CBLDLY (Bitfield-Mask: 0x0f) */ + #define R_HDSLD0_DELAY_RSSI_Pos (4UL) /*!< RSSI (Bit 4) */ + #define R_HDSLD0_DELAY_RSSI_Msk (0xf0UL) /*!< RSSI (Bitfield-Mask: 0x0f) */ +/* ======================================================== VERSION ======================================================== */ + #define R_HDSLD0_VERSION_MINOR_Pos (0UL) /*!< MINOR (Bit 0) */ + #define R_HDSLD0_VERSION_MINOR_Msk (0xfUL) /*!< MINOR (Bitfield-Mask: 0x0f) */ + #define R_HDSLD0_VERSION_MAJOR_Pos (4UL) /*!< MAJOR (Bit 4) */ + #define R_HDSLD0_VERSION_MAJOR_Msk (0x30UL) /*!< MAJOR (Bitfield-Mask: 0x03) */ + #define R_HDSLD0_VERSION_CODE_Pos (6UL) /*!< CODE (Bit 6) */ + #define R_HDSLD0_VERSION_CODE_Msk (0xc0UL) /*!< CODE (Bitfield-Mask: 0x03) */ +/* ======================================================== ENC_ID2 ======================================================== */ + #define R_HDSLD0_ENC_ID2_ENCID_Pos (0UL) /*!< ENCID (Bit 0) */ + #define R_HDSLD0_ENC_ID2_ENCID_Msk (0xfUL) /*!< ENCID (Bitfield-Mask: 0x0f) */ + #define R_HDSLD0_ENC_ID2_SCI_Pos (4UL) /*!< SCI (Bit 4) */ + #define R_HDSLD0_ENC_ID2_SCI_Msk (0x70UL) /*!< SCI (Bitfield-Mask: 0x07) */ +/* ======================================================== ENC_ID1 ======================================================== */ + #define R_HDSLD0_ENC_ID1_ENCID_Pos (0UL) /*!< ENCID (Bit 0) */ + #define R_HDSLD0_ENC_ID1_ENCID_Msk (0xffUL) /*!< ENCID (Bitfield-Mask: 0xff) */ +/* ======================================================== ENC_ID0 ======================================================== */ + #define R_HDSLD0_ENC_ID0_ENCID_Pos (0UL) /*!< ENCID (Bit 0) */ + #define R_HDSLD0_ENC_ID0_ENCID_Msk (0xffUL) /*!< ENCID (Bitfield-Mask: 0xff) */ +/* ========================================================= POS4 ========================================================== */ + #define R_HDSLD0_POS4_POS_Pos (0UL) /*!< POS (Bit 0) */ + #define R_HDSLD0_POS4_POS_Msk (0xffUL) /*!< POS (Bitfield-Mask: 0xff) */ +/* ========================================================= POS3 ========================================================== */ + #define R_HDSLD0_POS3_POS_Pos (0UL) /*!< POS (Bit 0) */ + #define R_HDSLD0_POS3_POS_Msk (0xffUL) /*!< POS (Bitfield-Mask: 0xff) */ +/* ========================================================= POS2 ========================================================== */ + #define R_HDSLD0_POS2_POS_Pos (0UL) /*!< POS (Bit 0) */ + #define R_HDSLD0_POS2_POS_Msk (0xffUL) /*!< POS (Bitfield-Mask: 0xff) */ +/* ========================================================= POS1 ========================================================== */ + #define R_HDSLD0_POS1_POS_Pos (0UL) /*!< POS (Bit 0) */ + #define R_HDSLD0_POS1_POS_Msk (0xffUL) /*!< POS (Bitfield-Mask: 0xff) */ +/* ========================================================= POS0 ========================================================== */ + #define R_HDSLD0_POS0_POS_Pos (0UL) /*!< POS (Bit 0) */ + #define R_HDSLD0_POS0_POS_Msk (0xffUL) /*!< POS (Bitfield-Mask: 0xff) */ +/* ========================================================= VEL2 ========================================================== */ + #define R_HDSLD0_VEL2_VEL_Pos (0UL) /*!< VEL (Bit 0) */ + #define R_HDSLD0_VEL2_VEL_Msk (0xffUL) /*!< VEL (Bitfield-Mask: 0xff) */ +/* ========================================================= VEL1 ========================================================== */ + #define R_HDSLD0_VEL1_VEL_Pos (0UL) /*!< VEL (Bit 0) */ + #define R_HDSLD0_VEL1_VEL_Msk (0xffUL) /*!< VEL (Bitfield-Mask: 0xff) */ +/* ========================================================= VEL0 ========================================================== */ + #define R_HDSLD0_VEL0_VEL_Pos (0UL) /*!< VEL (Bit 0) */ + #define R_HDSLD0_VEL0_VEL_Msk (0xffUL) /*!< VEL (Bitfield-Mask: 0xff) */ +/* ======================================================== MIR_SUM ======================================================== */ + #define R_HDSLD0_MIR_SUM_SUM_Pos (0UL) /*!< SUM (Bit 0) */ + #define R_HDSLD0_MIR_SUM_SUM_Msk (0xffUL) /*!< SUM (Bitfield-Mask: 0xff) */ +/* ======================================================== PC_BUF ========================================================= */ + #define R_HDSLD0_PC_BUF_PCBUF_Pos (0UL) /*!< PCBUF (Bit 0) */ + #define R_HDSLD0_PC_BUF_PCBUF_Msk (0xffUL) /*!< PCBUF (Bitfield-Mask: 0xff) */ +/* ======================================================= PC_ADD_H ======================================================== */ + #define R_HDSLD0_PC_ADD_H_LADDH_Pos (0UL) /*!< LADDH (Bit 0) */ + #define R_HDSLD0_PC_ADD_H_LADDH_Msk (0x3UL) /*!< LADDH (Bitfield-Mask: 0x03) */ + #define R_HDSLD0_PC_ADD_H_LLEN_Pos (2UL) /*!< LLEN (Bit 2) */ + #define R_HDSLD0_PC_ADD_H_LLEN_Msk (0xcUL) /*!< LLEN (Bitfield-Mask: 0x03) */ + #define R_HDSLD0_PC_ADD_H_LIND_Pos (4UL) /*!< LIND (Bit 4) */ + #define R_HDSLD0_PC_ADD_H_LIND_Msk (0x10UL) /*!< LIND (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_PC_ADD_H_LOFF_Pos (5UL) /*!< LOFF (Bit 5) */ + #define R_HDSLD0_PC_ADD_H_LOFF_Msk (0x20UL) /*!< LOFF (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_PC_ADD_H_LRW_Pos (6UL) /*!< LRW (Bit 6) */ + #define R_HDSLD0_PC_ADD_H_LRW_Msk (0x40UL) /*!< LRW (Bitfield-Mask: 0x01) */ +/* ======================================================= PC_ADD_L ======================================================== */ + #define R_HDSLD0_PC_ADD_L_LADDL_Pos (0UL) /*!< LADDL (Bit 0) */ + #define R_HDSLD0_PC_ADD_L_LADDL_Msk (0xffUL) /*!< LADDL (Bitfield-Mask: 0xff) */ +/* ======================================================= PC_OFF_H ======================================================== */ + #define R_HDSLD0_PC_OFF_H_LOFFADDH_Pos (0UL) /*!< LOFFADDH (Bit 0) */ + #define R_HDSLD0_PC_OFF_H_LOFFADDH_Msk (0x7fUL) /*!< LOFFADDH (Bitfield-Mask: 0x7f) */ + #define R_HDSLD0_PC_OFF_H_LID_Pos (7UL) /*!< LID (Bit 7) */ + #define R_HDSLD0_PC_OFF_H_LID_Msk (0x80UL) /*!< LID (Bitfield-Mask: 0x01) */ +/* ======================================================= PC_OFF_L ======================================================== */ + #define R_HDSLD0_PC_OFF_L_LOFFADDL_Pos (0UL) /*!< LOFFADDL (Bit 0) */ + #define R_HDSLD0_PC_OFF_L_LOFFADDL_Msk (0xffUL) /*!< LOFFADDL (Bitfield-Mask: 0xff) */ +/* ======================================================== PC_CTRL ======================================================== */ + #define R_HDSLD0_PC_CTRL_LSTA_Pos (0UL) /*!< LSTA (Bit 0) */ + #define R_HDSLD0_PC_CTRL_LSTA_Msk (0x1UL) /*!< LSTA (Bitfield-Mask: 0x01) */ +/* ======================================================== PIPE_S ========================================================= */ + #define R_HDSLD0_PIPE_S_PSCI_Pos (0UL) /*!< PSCI (Bit 0) */ + #define R_HDSLD0_PIPE_S_PSCI_Msk (0x1UL) /*!< PSCI (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_PIPE_S_PERR_Pos (1UL) /*!< PERR (Bit 1) */ + #define R_HDSLD0_PIPE_S_PERR_Msk (0x2UL) /*!< PERR (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_PIPE_S_PEMP_Pos (2UL) /*!< PEMP (Bit 2) */ + #define R_HDSLD0_PIPE_S_PEMP_Msk (0x4UL) /*!< PEMP (Bitfield-Mask: 0x01) */ + #define R_HDSLD0_PIPE_S_POVR_Pos (3UL) /*!< POVR (Bit 3) */ + #define R_HDSLD0_PIPE_S_POVR_Msk (0x8UL) /*!< POVR (Bitfield-Mask: 0x01) */ +/* ======================================================== PIPE_D ========================================================= */ + #define R_HDSLD0_PIPE_D_SCDATA_Pos (0UL) /*!< SCDATA (Bit 0) */ + #define R_HDSLD0_PIPE_D_SCDATA_Msk (0xffUL) /*!< SCDATA (Bitfield-Mask: 0xff) */ +/* ======================================================== PC_DATA ======================================================== */ + #define R_HDSLD0_PC_DATA_PCDATA_Pos (0UL) /*!< PCDATA (Bit 0) */ + #define R_HDSLD0_PC_DATA_PCDATA_Msk (0xffUL) /*!< PCDATA (Bitfield-Mask: 0xff) */ +/* ====================================================== ACC_ERR_CNT ====================================================== */ + #define R_HDSLD0_ACC_ERR_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ + #define R_HDSLD0_ACC_ERR_CNT_CNT_Msk (0x1fUL) /*!< CNT (Bitfield-Mask: 0x1f) */ +/* ======================================================== MAXACC ========================================================= */ + #define R_HDSLD0_MAXACC_MNT_Pos (0UL) /*!< MNT (Bit 0) */ + #define R_HDSLD0_MAXACC_MNT_Msk (0x3fUL) /*!< MNT (Bitfield-Mask: 0x3f) */ + #define R_HDSLD0_MAXACC_RES_Pos (6UL) /*!< RES (Bit 6) */ + #define R_HDSLD0_MAXACC_RES_Msk (0xc0UL) /*!< RES (Bitfield-Mask: 0x03) */ +/* ======================================================= MAXDEV_H ======================================================== */ + #define R_HDSLD0_MAXDEV_H_DEVH_Pos (0UL) /*!< DEVH (Bit 0) */ + #define R_HDSLD0_MAXDEV_H_DEVH_Msk (0xffUL) /*!< DEVH (Bitfield-Mask: 0xff) */ +/* ======================================================= MAXDEV_L ======================================================== */ + #define R_HDSLD0_MAXDEV_L_DEVL_Pos (0UL) /*!< DEVL (Bit 0) */ + #define R_HDSLD0_MAXDEV_L_DEVL_Msk (0xffUL) /*!< DEVL (Bitfield-Mask: 0xff) */ +/* ========================================================= DUMMY ========================================================= */ + #define R_HDSLD0_DUMMY_DUMMY_Pos (0UL) /*!< DUMMY (Bit 0) */ + #define R_HDSLD0_DUMMY_DUMMY_Msk (0xffUL) /*!< DUMMY (Bitfield-Mask: 0xff) */ +/* ======================================================== MIR_ST ========================================================= */ + #define R_HDSLD0_MIR_ST_MIRST_Pos (0UL) /*!< MIRST (Bit 0) */ + #define R_HDSLD0_MIR_ST_MIRST_Msk (0xffUL) /*!< MIRST (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_HDSLS10 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EDGES ========================================================= */ + #define R_HDSLS10_EDGES_EDGES_Pos (0UL) /*!< EDGES (Bit 0) */ + #define R_HDSLS10_EDGES_EDGES_Msk (0xffUL) /*!< EDGES (Bitfield-Mask: 0xff) */ +/* ========================================================= DELAY ========================================================= */ + #define R_HDSLS10_DELAY_CBLDLY_Pos (0UL) /*!< CBLDLY (Bit 0) */ + #define R_HDSLS10_DELAY_CBLDLY_Msk (0xfUL) /*!< CBLDLY (Bitfield-Mask: 0x0f) */ + #define R_HDSLS10_DELAY_RSSI_Pos (4UL) /*!< RSSI (Bit 4) */ + #define R_HDSLS10_DELAY_RSSI_Msk (0xf0UL) /*!< RSSI (Bitfield-Mask: 0x0f) */ +/* ======================================================== VERSION ======================================================== */ + #define R_HDSLS10_VERSION_MINOR_Pos (0UL) /*!< MINOR (Bit 0) */ + #define R_HDSLS10_VERSION_MINOR_Msk (0xfUL) /*!< MINOR (Bitfield-Mask: 0x0f) */ + #define R_HDSLS10_VERSION_MAJOR_Pos (4UL) /*!< MAJOR (Bit 4) */ + #define R_HDSLS10_VERSION_MAJOR_Msk (0x30UL) /*!< MAJOR (Bitfield-Mask: 0x03) */ + #define R_HDSLS10_VERSION_CODE_Pos (6UL) /*!< CODE (Bit 6) */ + #define R_HDSLS10_VERSION_CODE_Msk (0xc0UL) /*!< CODE (Bitfield-Mask: 0x03) */ +/* ======================================================== ENC_ID2 ======================================================== */ + #define R_HDSLS10_ENC_ID2_ENCID_Pos (0UL) /*!< ENCID (Bit 0) */ + #define R_HDSLS10_ENC_ID2_ENCID_Msk (0xfUL) /*!< ENCID (Bitfield-Mask: 0x0f) */ + #define R_HDSLS10_ENC_ID2_SCI_Pos (4UL) /*!< SCI (Bit 4) */ + #define R_HDSLS10_ENC_ID2_SCI_Msk (0x70UL) /*!< SCI (Bitfield-Mask: 0x07) */ +/* ======================================================== ENC_ID1 ======================================================== */ + #define R_HDSLS10_ENC_ID1_ENCID_Pos (0UL) /*!< ENCID (Bit 0) */ + #define R_HDSLS10_ENC_ID1_ENCID_Msk (0xffUL) /*!< ENCID (Bitfield-Mask: 0xff) */ +/* ======================================================== ENC_ID0 ======================================================== */ + #define R_HDSLS10_ENC_ID0_ENCID_Pos (0UL) /*!< ENCID (Bit 0) */ + #define R_HDSLS10_ENC_ID0_ENCID_Msk (0xffUL) /*!< ENCID (Bitfield-Mask: 0xff) */ +/* ========================================================= VPOS4 ========================================================= */ + #define R_HDSLS10_VPOS4_VPOS_Pos (0UL) /*!< VPOS (Bit 0) */ + #define R_HDSLS10_VPOS4_VPOS_Msk (0xffUL) /*!< VPOS (Bitfield-Mask: 0xff) */ +/* ========================================================= VPOS3 ========================================================= */ + #define R_HDSLS10_VPOS3_VPOS_Pos (0UL) /*!< VPOS (Bit 0) */ + #define R_HDSLS10_VPOS3_VPOS_Msk (0xffUL) /*!< VPOS (Bitfield-Mask: 0xff) */ +/* ========================================================= VPOS2 ========================================================= */ + #define R_HDSLS10_VPOS2_VPOS_Pos (0UL) /*!< VPOS (Bit 0) */ + #define R_HDSLS10_VPOS2_VPOS_Msk (0xffUL) /*!< VPOS (Bitfield-Mask: 0xff) */ +/* ========================================================= VPOS1 ========================================================= */ + #define R_HDSLS10_VPOS1_VPOS_Pos (0UL) /*!< VPOS (Bit 0) */ + #define R_HDSLS10_VPOS1_VPOS_Msk (0xffUL) /*!< VPOS (Bitfield-Mask: 0xff) */ +/* ========================================================= VPOS0 ========================================================= */ + #define R_HDSLS10_VPOS0_VPOS_Pos (0UL) /*!< VPOS (Bit 0) */ + #define R_HDSLS10_VPOS0_VPOS_Msk (0xffUL) /*!< VPOS (Bitfield-Mask: 0xff) */ +/* ======================================================= VPOSCRC_H ======================================================= */ + #define R_HDSLS10_VPOSCRC_H_VPOSCRCH_Pos (0UL) /*!< VPOSCRCH (Bit 0) */ + #define R_HDSLS10_VPOSCRC_H_VPOSCRCH_Msk (0xffUL) /*!< VPOSCRCH (Bitfield-Mask: 0xff) */ +/* ======================================================= VPOSCRC_L ======================================================= */ + #define R_HDSLS10_VPOSCRC_L_VPOSCRCL_Pos (0UL) /*!< VPOSCRCL (Bit 0) */ + #define R_HDSLS10_VPOSCRC_L_VPOSCRCL_Msk (0xffUL) /*!< VPOSCRCL (Bitfield-Mask: 0xff) */ +/* ======================================================= SAFE_CTRL ======================================================= */ + #define R_HDSLS10_SAFE_CTRL_MRST_Pos (6UL) /*!< MRST (Bit 6) */ + #define R_HDSLS10_SAFE_CTRL_MRST_Msk (0x40UL) /*!< MRST (Bitfield-Mask: 0x01) */ + #define R_HDSLS10_SAFE_CTRL_PRST_Pos (7UL) /*!< PRST (Bit 7) */ + #define R_HDSLS10_SAFE_CTRL_PRST_Msk (0x80UL) /*!< PRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SAFE_SUM ======================================================== */ + #define R_HDSLS10_SAFE_SUM_SSUM_Pos (0UL) /*!< SSUM (Bit 0) */ + #define R_HDSLS10_SAFE_SUM_SSUM_Msk (0xffUL) /*!< SSUM (Bitfield-Mask: 0xff) */ +/* ======================================================= S_PC_DATA ======================================================= */ + #define R_HDSLS10_S_PC_DATA_SPCDATA_Pos (0UL) /*!< SPCDATA (Bit 0) */ + #define R_HDSLS10_S_PC_DATA_SPCDATA_Msk (0xffUL) /*!< SPCDATA (Bitfield-Mask: 0xff) */ +/* ======================================================== EVENT_S ======================================================== */ + #define R_HDSLS10_EVENT_S_FRES_Pos (0UL) /*!< FRES (Bit 0) */ + #define R_HDSLS10_EVENT_S_FRES_Msk (0x1UL) /*!< FRES (Bitfield-Mask: 0x01) */ + #define R_HDSLS10_EVENT_S_MIN_Pos (1UL) /*!< MIN (Bit 1) */ + #define R_HDSLS10_EVENT_S_MIN_Msk (0x2UL) /*!< MIN (Bitfield-Mask: 0x01) */ + #define R_HDSLS10_EVENT_S_PRST_Pos (2UL) /*!< PRST (Bit 2) */ + #define R_HDSLS10_EVENT_S_PRST_Msk (0x4UL) /*!< PRST (Bitfield-Mask: 0x01) */ + #define R_HDSLS10_EVENT_S_QMLW_Pos (3UL) /*!< QMLW (Bit 3) */ + #define R_HDSLS10_EVENT_S_QMLW_Msk (0x8UL) /*!< QMLW (Bitfield-Mask: 0x01) */ + #define R_HDSLS10_EVENT_S_VPOS_Pos (4UL) /*!< VPOS (Bit 4) */ + #define R_HDSLS10_EVENT_S_VPOS_Msk (0x10UL) /*!< VPOS (Bitfield-Mask: 0x01) */ + #define R_HDSLS10_EVENT_S_SCE_Pos (5UL) /*!< SCE (Bit 5) */ + #define R_HDSLS10_EVENT_S_SCE_Msk (0x20UL) /*!< SCE (Bitfield-Mask: 0x01) */ + #define R_HDSLS10_EVENT_S_SSUM_Pos (6UL) /*!< SSUM (Bit 6) */ + #define R_HDSLS10_EVENT_S_SSUM_Msk (0x40UL) /*!< SSUM (Bitfield-Mask: 0x01) */ + #define R_HDSLS10_EVENT_S_SINT_Pos (7UL) /*!< SINT (Bit 7) */ + #define R_HDSLS10_EVENT_S_SINT_Msk (0x80UL) /*!< SINT (Bitfield-Mask: 0x01) */ +/* ======================================================== MASK_S ========================================================= */ + #define R_HDSLS10_MASK_S_MFRES_Pos (0UL) /*!< MFRES (Bit 0) */ + #define R_HDSLS10_MASK_S_MFRES_Msk (0x1UL) /*!< MFRES (Bitfield-Mask: 0x01) */ + #define R_HDSLS10_MASK_S_MMIN_Pos (1UL) /*!< MMIN (Bit 1) */ + #define R_HDSLS10_MASK_S_MMIN_Msk (0x2UL) /*!< MMIN (Bitfield-Mask: 0x01) */ + #define R_HDSLS10_MASK_S_MPRST_Pos (2UL) /*!< MPRST (Bit 2) */ + #define R_HDSLS10_MASK_S_MPRST_Msk (0x4UL) /*!< MPRST (Bitfield-Mask: 0x01) */ + #define R_HDSLS10_MASK_S_MQMLW_Pos (3UL) /*!< MQMLW (Bit 3) */ + #define R_HDSLS10_MASK_S_MQMLW_Msk (0x8UL) /*!< MQMLW (Bitfield-Mask: 0x01) */ + #define R_HDSLS10_MASK_S_MVPOS_Pos (4UL) /*!< MVPOS (Bit 4) */ + #define R_HDSLS10_MASK_S_MVPOS_Msk (0x10UL) /*!< MVPOS (Bitfield-Mask: 0x01) */ + #define R_HDSLS10_MASK_S_MSCE_Pos (5UL) /*!< MSCE (Bit 5) */ + #define R_HDSLS10_MASK_S_MSCE_Msk (0x20UL) /*!< MSCE (Bitfield-Mask: 0x01) */ + #define R_HDSLS10_MASK_S_MSSUM_Pos (6UL) /*!< MSSUM (Bit 6) */ + #define R_HDSLS10_MASK_S_MSSUM_Msk (0x40UL) /*!< MSSUM (Bitfield-Mask: 0x01) */ +/* ========================================================= DUMMY ========================================================= */ + #define R_HDSLS10_DUMMY_DUMMY_Pos (0UL) /*!< DUMMY (Bit 0) */ + #define R_HDSLS10_DUMMY_DUMMY_Msk (0xffUL) /*!< DUMMY (Bitfield-Mask: 0xff) */ +/* ======================================================== ENC_ST ========================================================= */ + #define R_HDSLS10_ENC_ST_ENCST_Pos (0UL) /*!< ENCST (Bit 0) */ + #define R_HDSLS10_ENC_ST_ENCST_Msk (0xffUL) /*!< ENCST (Bitfield-Mask: 0xff) */ +/* ========================================================= SRSSI ========================================================= */ + #define R_HDSLS10_SRSSI_SRSSI_Pos (0UL) /*!< SRSSI (Bit 0) */ + #define R_HDSLS10_SRSSI_SRSSI_Msk (0x7UL) /*!< SRSSI (Bitfield-Mask: 0x07) */ +/* ========================================================= MAIL ========================================================== */ + #define R_HDSLS10_MAIL_MAIL_Pos (0UL) /*!< MAIL (Bit 0) */ + #define R_HDSLS10_MAIL_MAIL_Msk (0xffUL) /*!< MAIL (Bitfield-Mask: 0xff) */ +/* ========================================================= PING ========================================================== */ + #define R_HDSLS10_PING_PING_Pos (0UL) /*!< PING (Bit 0) */ + #define R_HDSLS10_PING_PING_Msk (0xffUL) /*!< PING (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_BISS0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RDATA ========================================================= */ +/* ======================================================== CNFSLV ========================================================= */ + #define R_BISS0_CNFSLV_SCDLEN_Pos (0UL) /*!< SCDLEN (Bit 0) */ + #define R_BISS0_CNFSLV_SCDLEN_Msk (0x3fUL) /*!< SCDLEN (Bitfield-Mask: 0x3f) */ + #define R_BISS0_CNFSLV_ENSCD_Pos (6UL) /*!< ENSCD (Bit 6) */ + #define R_BISS0_CNFSLV_ENSCD_Msk (0x40UL) /*!< ENSCD (Bitfield-Mask: 0x01) */ + #define R_BISS0_CNFSLV_SCRCLENPOLY_Pos (8UL) /*!< SCRCLENPOLY (Bit 8) */ + #define R_BISS0_CNFSLV_SCRCLENPOLY_Msk (0x7f00UL) /*!< SCRCLENPOLY (Bitfield-Mask: 0x7f) */ + #define R_BISS0_CNFSLV_SELCRCS_Pos (15UL) /*!< SELCRCS (Bit 15) */ + #define R_BISS0_CNFSLV_SELCRCS_Msk (0x8000UL) /*!< SELCRCS (Bitfield-Mask: 0x01) */ + #define R_BISS0_CNFSLV_SCRCSTART_Pos (16UL) /*!< SCRCSTART (Bit 16) */ + #define R_BISS0_CNFSLV_SCRCSTART_Msk (0xffff0000UL) /*!< SCRCSTART (Bitfield-Mask: 0xffff) */ +/* ======================================================== REGACC ========================================================= */ + #define R_BISS0_REGACC_REGADR_Pos (16UL) /*!< REGADR (Bit 16) */ + #define R_BISS0_REGACC_REGADR_Msk (0x7f0000UL) /*!< REGADR (Bitfield-Mask: 0x7f) */ + #define R_BISS0_REGACC_WNR_Pos (23UL) /*!< WNR (Bit 23) */ + #define R_BISS0_REGACC_WNR_Msk (0x800000UL) /*!< WNR (Bitfield-Mask: 0x01) */ + #define R_BISS0_REGACC_REGNUM_Pos (24UL) /*!< REGNUM (Bit 24) */ + #define R_BISS0_REGACC_REGNUM_Msk (0x3f000000UL) /*!< REGNUM (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTRLCOMM ======================================================== */ + #define R_BISS0_CTRLCOMM_HOLDCDM_Pos (8UL) /*!< HOLDCDM (Bit 8) */ + #define R_BISS0_CTRLCOMM_HOLDCDM_Msk (0x100UL) /*!< HOLDCDM (Bitfield-Mask: 0x01) */ + #define R_BISS0_CTRLCOMM_SID_CMD_IDT_Pos (11UL) /*!< SID_CMD_IDT (Bit 11) */ + #define R_BISS0_CTRLCOMM_SID_CMD_IDT_Msk (0x3800UL) /*!< SID_CMD_IDT (Bitfield-Mask: 0x07) */ + #define R_BISS0_CTRLCOMM_REGVERS_Pos (14UL) /*!< REGVERS (Bit 14) */ + #define R_BISS0_CTRLCOMM_REGVERS_Msk (0x4000UL) /*!< REGVERS (Bitfield-Mask: 0x01) */ + #define R_BISS0_CTRLCOMM_CTS_Pos (15UL) /*!< CTS (Bit 15) */ + #define R_BISS0_CTRLCOMM_CTS_Msk (0x8000UL) /*!< CTS (Bitfield-Mask: 0x01) */ + #define R_BISS0_CTRLCOMM_FREQS_Pos (16UL) /*!< FREQS (Bit 16) */ + #define R_BISS0_CTRLCOMM_FREQS_Msk (0x1f0000UL) /*!< FREQS (Bitfield-Mask: 0x1f) */ + #define R_BISS0_CTRLCOMM_FREQR_Pos (21UL) /*!< FREQR (Bit 21) */ + #define R_BISS0_CTRLCOMM_FREQR_Msk (0xe00000UL) /*!< FREQR (Bitfield-Mask: 0x07) */ + #define R_BISS0_CTRLCOMM_SINGLEBANK_Pos (24UL) /*!< SINGLEBANK (Bit 24) */ + #define R_BISS0_CTRLCOMM_SINGLEBANK_Msk (0x1000000UL) /*!< SINGLEBANK (Bitfield-Mask: 0x01) */ + #define R_BISS0_CTRLCOMM_NOCRC_Pos (25UL) /*!< NOCRC (Bit 25) */ + #define R_BISS0_CTRLCOMM_NOCRC_Msk (0x2000000UL) /*!< NOCRC (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTRCNF ======================================================== */ + #define R_BISS0_MSTRCNF_FREQAGS_Pos (0UL) /*!< FREQAGS (Bit 0) */ + #define R_BISS0_MSTRCNF_FREQAGS_Msk (0xffUL) /*!< FREQAGS (Bitfield-Mask: 0xff) */ + #define R_BISS0_MSTRCNF_REVISION_Pos (16UL) /*!< REVISION (Bit 16) */ + #define R_BISS0_MSTRCNF_REVISION_Msk (0xff0000UL) /*!< REVISION (Bitfield-Mask: 0xff) */ + #define R_BISS0_MSTRCNF_VERSION_Pos (24UL) /*!< VERSION (Bit 24) */ + #define R_BISS0_MSTRCNF_VERSION_Msk (0xff000000UL) /*!< VERSION (Bitfield-Mask: 0xff) */ +/* ========================================================= CHCNF ========================================================= */ + #define R_BISS0_CHCNF_CFGCH1_Pos (8UL) /*!< CFGCH1 (Bit 8) */ + #define R_BISS0_CHCNF_CFGCH1_Msk (0x300UL) /*!< CFGCH1 (Bitfield-Mask: 0x03) */ +/* ========================================================= STINF ========================================================= */ + #define R_BISS0_STINF_EOT_Pos (0UL) /*!< EOT (Bit 0) */ + #define R_BISS0_STINF_EOT_Msk (0x1UL) /*!< EOT (Bitfield-Mask: 0x01) */ + #define R_BISS0_STINF_REGEND_Pos (2UL) /*!< REGEND (Bit 2) */ + #define R_BISS0_STINF_REGEND_Msk (0x4UL) /*!< REGEND (Bitfield-Mask: 0x01) */ + #define R_BISS0_STINF_nREGERR_Pos (3UL) /*!< nREGERR (Bit 3) */ + #define R_BISS0_STINF_nREGERR_Msk (0x8UL) /*!< nREGERR (Bitfield-Mask: 0x01) */ + #define R_BISS0_STINF_nSCDERR_Pos (4UL) /*!< nSCDERR (Bit 4) */ + #define R_BISS0_STINF_nSCDERR_Msk (0x10UL) /*!< nSCDERR (Bitfield-Mask: 0x01) */ + #define R_BISS0_STINF_nDELAYERR_Pos (5UL) /*!< nDELAYERR (Bit 5) */ + #define R_BISS0_STINF_nDELAYERR_Msk (0x20UL) /*!< nDELAYERR (Bitfield-Mask: 0x01) */ + #define R_BISS0_STINF_nAGSERR_Pos (6UL) /*!< nAGSERR (Bit 6) */ + #define R_BISS0_STINF_nAGSERR_Msk (0x40UL) /*!< nAGSERR (Bitfield-Mask: 0x01) */ + #define R_BISS0_STINF_nERR_Pos (7UL) /*!< nERR (Bit 7) */ + #define R_BISS0_STINF_nERR_Msk (0x80UL) /*!< nERR (Bitfield-Mask: 0x01) */ + #define R_BISS0_STINF_SVALID_Pos (8UL) /*!< SVALID (Bit 8) */ + #define R_BISS0_STINF_SVALID_Msk (0xffff00UL) /*!< SVALID (Bitfield-Mask: 0xffff) */ + #define R_BISS0_STINF_REGBYTES_Pos (24UL) /*!< REGBYTES (Bit 24) */ + #define R_BISS0_STINF_REGBYTES_Msk (0x3f000000UL) /*!< REGBYTES (Bitfield-Mask: 0x3f) */ + #define R_BISS0_STINF_CDSSEL_Pos (30UL) /*!< CDSSEL (Bit 30) */ + #define R_BISS0_STINF_CDSSEL_Msk (0x40000000UL) /*!< CDSSEL (Bitfield-Mask: 0x01) */ + #define R_BISS0_STINF_CDMTIMEOUT_Pos (31UL) /*!< CDMTIMEOUT (Bit 31) */ + #define R_BISS0_STINF_CDMTIMEOUT_Msk (0x80000000UL) /*!< CDMTIMEOUT (Bitfield-Mask: 0x01) */ +/* ======================================================== INSTREG ======================================================== */ + #define R_BISS0_INSTREG_AGS_Pos (0UL) /*!< AGS (Bit 0) */ + #define R_BISS0_INSTREG_AGS_Msk (0x1UL) /*!< AGS (Bitfield-Mask: 0x01) */ + #define R_BISS0_INSTREG_INSTR_Pos (1UL) /*!< INSTR (Bit 1) */ + #define R_BISS0_INSTREG_INSTR_Msk (0xeUL) /*!< INSTR (Bitfield-Mask: 0x07) */ + #define R_BISS0_INSTREG_INIT_Pos (4UL) /*!< INIT (Bit 4) */ + #define R_BISS0_INSTREG_INIT_Msk (0x10UL) /*!< INIT (Bitfield-Mask: 0x01) */ + #define R_BISS0_INSTREG_SWBANK_Pos (5UL) /*!< SWBANK (Bit 5) */ + #define R_BISS0_INSTREG_SWBANK_Msk (0x20UL) /*!< SWBANK (Bitfield-Mask: 0x01) */ + #define R_BISS0_INSTREG_HOLDBANK_Pos (6UL) /*!< HOLDBANK (Bit 6) */ + #define R_BISS0_INSTREG_HOLDBANK_Msk (0x40UL) /*!< HOLDBANK (Bitfield-Mask: 0x01) */ + #define R_BISS0_INSTREG_BREAK_Pos (7UL) /*!< BREAK (Bit 7) */ + #define R_BISS0_INSTREG_BREAK_Msk (0x80UL) /*!< BREAK (Bitfield-Mask: 0x01) */ + #define R_BISS0_INSTREG_MAFS_Pos (12UL) /*!< MAFS (Bit 12) */ + #define R_BISS0_INSTREG_MAFS_Msk (0x1000UL) /*!< MAFS (Bitfield-Mask: 0x01) */ + #define R_BISS0_INSTREG_MAVS_Pos (13UL) /*!< MAVS (Bit 13) */ + #define R_BISS0_INSTREG_MAVS_Msk (0x2000UL) /*!< MAVS (Bitfield-Mask: 0x01) */ +/* ======================================================== STINF2 ========================================================= */ + #define R_BISS0_STINF2_SL1_Pos (0UL) /*!< SL1 (Bit 0) */ + #define R_BISS0_STINF2_SL1_Msk (0x1UL) /*!< SL1 (Bitfield-Mask: 0x01) */ + #define R_BISS0_STINF2_CDS1_Pos (1UL) /*!< CDS1 (Bit 1) */ + #define R_BISS0_STINF2_CDS1_Msk (0x2UL) /*!< CDS1 (Bitfield-Mask: 0x01) */ + #define R_BISS0_STINF2_IDL_Pos (16UL) /*!< IDL (Bit 16) */ + #define R_BISS0_STINF2_IDL_Msk (0xf0000UL) /*!< IDL (Bitfield-Mask: 0x0f) */ + #define R_BISS0_STINF2_SWBANKFAIL_Pos (24UL) /*!< SWBANKFAIL (Bit 24) */ + #define R_BISS0_STINF2_SWBANKFAIL_Msk (0x1000000UL) /*!< SWBANKFAIL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ENDAT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SEND ========================================================== */ + #define R_ENDAT0_SEND_D_Pos (0UL) /*!< D (Bit 0) */ + #define R_ENDAT0_SEND_D_Msk (0xffffUL) /*!< D (Bitfield-Mask: 0xffff) */ + #define R_ENDAT0_SEND_A_Pos (16UL) /*!< A (Bit 16) */ + #define R_ENDAT0_SEND_A_Msk (0xff0000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_ENDAT0_SEND_M_Pos (24UL) /*!< M (Bit 24) */ + #define R_ENDAT0_SEND_M_Msk (0x3f000000UL) /*!< M (Bitfield-Mask: 0x3f) */ +/* ======================================================= EMPFR1_L ======================================================== */ + #define R_ENDAT0_EMPFR1_L_RDATA_L_Pos (0UL) /*!< RDATA_L (Bit 0) */ + #define R_ENDAT0_EMPFR1_L_RDATA_L_Msk (0xffffffffUL) /*!< RDATA_L (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EMPFR1_H ======================================================== */ + #define R_ENDAT0_EMPFR1_H_RDATA_H_Pos (0UL) /*!< RDATA_H (Bit 0) */ + #define R_ENDAT0_EMPFR1_H_RDATA_H_Msk (0xffffUL) /*!< RDATA_H (Bitfield-Mask: 0xffff) */ + #define R_ENDAT0_EMPFR1_H_CRC_Pos (16UL) /*!< CRC (Bit 16) */ + #define R_ENDAT0_EMPFR1_H_CRC_Msk (0x1f0000UL) /*!< CRC (Bitfield-Mask: 0x1f) */ + #define R_ENDAT0_EMPFR1_H_F1_Pos (21UL) /*!< F1 (Bit 21) */ + #define R_ENDAT0_EMPFR1_H_F1_Msk (0x200000UL) /*!< F1 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_EMPFR1_H_IF2_Pos (22UL) /*!< IF2 (Bit 22) */ + #define R_ENDAT0_EMPFR1_H_IF2_Msk (0x400000UL) /*!< IF2 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_EMPFR1_H_POS1_Pos (23UL) /*!< POS1 (Bit 23) */ + #define R_ENDAT0_EMPFR1_H_POS1_Msk (0x800000UL) /*!< POS1 (Bitfield-Mask: 0x01) */ +/* ======================================================== EMPFR2 ========================================================= */ + #define R_ENDAT0_EMPFR2_RDATA2_Pos (0UL) /*!< RDATA2 (Bit 0) */ + #define R_ENDAT0_EMPFR2_RDATA2_Msk (0xffffffffUL) /*!< RDATA2 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== EMPFR3 ========================================================= */ + #define R_ENDAT0_EMPFR3_D_Pos (0UL) /*!< D (Bit 0) */ + #define R_ENDAT0_EMPFR3_D_Msk (0xffffUL) /*!< D (Bitfield-Mask: 0xffff) */ + #define R_ENDAT0_EMPFR3_C_Pos (16UL) /*!< C (Bit 16) */ + #define R_ENDAT0_EMPFR3_C_Msk (0xff0000UL) /*!< C (Bitfield-Mask: 0xff) */ + #define R_ENDAT0_EMPFR3_CRC_Pos (24UL) /*!< CRC (Bit 24) */ + #define R_ENDAT0_EMPFR3_CRC_Msk (0x1f000000UL) /*!< CRC (Bitfield-Mask: 0x1f) */ +/* ======================================================== KONFR1 ========================================================= */ + #define R_ENDAT0_KONFR1_HWSTRB_Pos (0UL) /*!< HWSTRB (Bit 0) */ + #define R_ENDAT0_KONFR1_HWSTRB_Msk (0x1UL) /*!< HWSTRB (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_KONFR1_DU_Pos (1UL) /*!< DU (Bit 1) */ + #define R_ENDAT0_KONFR1_DU_Msk (0x2UL) /*!< DU (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_KONFR1_DT_Pos (2UL) /*!< DT (Bit 2) */ + #define R_ENDAT0_KONFR1_DT_Msk (0x4UL) /*!< DT (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_KONFR1_FTCLK_Pos (4UL) /*!< FTCLK (Bit 4) */ + #define R_ENDAT0_KONFR1_FTCLK_Msk (0xf0UL) /*!< FTCLK (Bitfield-Mask: 0x0f) */ + #define R_ENDAT0_KONFR1_DWLG_Pos (8UL) /*!< DWLG (Bit 8) */ + #define R_ENDAT0_KONFR1_DWLG_Msk (0x3f00UL) /*!< DWLG (Bitfield-Mask: 0x3f) */ + #define R_ENDAT0_KONFR1_RSTWD_Pos (14UL) /*!< RSTWD (Bit 14) */ + #define R_ENDAT0_KONFR1_RSTWD_Msk (0x4000UL) /*!< RSTWD (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_KONFR1_AUTORST_Pos (15UL) /*!< AUTORST (Bit 15) */ + #define R_ENDAT0_KONFR1_AUTORST_Msk (0x8000UL) /*!< AUTORST (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_KONFR1_CPTIME_Pos (16UL) /*!< CPTIME (Bit 16) */ + #define R_ENDAT0_KONFR1_CPTIME_Msk (0xff0000UL) /*!< CPTIME (Bitfield-Mask: 0xff) */ + #define R_ENDAT0_KONFR1_DELAYCMP_Pos (24UL) /*!< DELAYCMP (Bit 24) */ + #define R_ENDAT0_KONFR1_DELAYCMP_Msk (0x1000000UL) /*!< DELAYCMP (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_KONFR1_FSYS_Pos (26UL) /*!< FSYS (Bit 26) */ + #define R_ENDAT0_KONFR1_FSYS_Msk (0x1c000000UL) /*!< FSYS (Bitfield-Mask: 0x07) */ + #define R_ENDAT0_KONFR1_ICRST_Pos (29UL) /*!< ICRST (Bit 29) */ + #define R_ENDAT0_KONFR1_ICRST_Msk (0x20000000UL) /*!< ICRST (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_KONFR1_SET_Pos (30UL) /*!< SET (Bit 30) */ + #define R_ENDAT0_KONFR1_SET_Msk (0xc0000000UL) /*!< SET (Bitfield-Mask: 0x03) */ +/* ======================================================== KONFR2 ========================================================= */ + #define R_ENDAT0_KONFR2_TMSMPLRATE_Pos (0UL) /*!< TMSMPLRATE (Bit 0) */ + #define R_ENDAT0_KONFR2_TMSMPLRATE_Msk (0xffUL) /*!< TMSMPLRATE (Bitfield-Mask: 0xff) */ + #define R_ENDAT0_KONFR2_WTDOG_Pos (8UL) /*!< WTDOG (Bit 8) */ + #define R_ENDAT0_KONFR2_WTDOG_Msk (0xff00UL) /*!< WTDOG (Bitfield-Mask: 0xff) */ + #define R_ENDAT0_KONFR2_RCVTIME_Pos (16UL) /*!< RCVTIME (Bit 16) */ + #define R_ENDAT0_KONFR2_RCVTIME_Msk (0x70000UL) /*!< RCVTIME (Bitfield-Mask: 0x07) */ + #define R_ENDAT0_KONFR2_FILTER_Pos (19UL) /*!< FILTER (Bit 19) */ + #define R_ENDAT0_KONFR2_FILTER_Msk (0x380000UL) /*!< FILTER (Bitfield-Mask: 0x07) */ + #define R_ENDAT0_KONFR2_HWSTRBDLY_Pos (24UL) /*!< HWSTRBDLY (Bit 24) */ + #define R_ENDAT0_KONFR2_HWSTRBDLY_Msk (0xff000000UL) /*!< HWSTRBDLY (Bitfield-Mask: 0xff) */ +/* ========================================================= STATR ========================================================= */ + #define R_ENDAT0_STATR_EMPFR1_Pos (0UL) /*!< EMPFR1 (Bit 0) */ + #define R_ENDAT0_STATR_EMPFR1_Msk (0x1UL) /*!< EMPFR1 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_ERR1_Pos (1UL) /*!< ERR1 (Bit 1) */ + #define R_ENDAT0_STATR_ERR1_Msk (0x2UL) /*!< ERR1 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_CRC_PRTY_Pos (2UL) /*!< CRC_PRTY (Bit 2) */ + #define R_ENDAT0_STATR_CRC_PRTY_Msk (0x4UL) /*!< CRC_PRTY (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_FTYPI_Pos (3UL) /*!< FTYPI (Bit 3) */ + #define R_ENDAT0_STATR_FTYPI_Msk (0x8UL) /*!< FTYPI (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_FTYPII_Pos (4UL) /*!< FTYPII (Bit 4) */ + #define R_ENDAT0_STATR_FTYPII_Msk (0x10UL) /*!< FTYPII (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_MRS_ADR_Pos (5UL) /*!< MRS_ADR (Bit 5) */ + #define R_ENDAT0_STATR_MRS_ADR_Msk (0x20UL) /*!< MRS_ADR (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_EMPFR2_Pos (8UL) /*!< EMPFR2 (Bit 8) */ + #define R_ENDAT0_STATR_EMPFR2_Msk (0x100UL) /*!< EMPFR2 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_EMPFR3_Pos (9UL) /*!< EMPFR3 (Bit 9) */ + #define R_ENDAT0_STATR_EMPFR3_Msk (0x200UL) /*!< EMPFR3 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_IERR2_Pos (10UL) /*!< IERR2 (Bit 10) */ + #define R_ENDAT0_STATR_IERR2_Msk (0x400UL) /*!< IERR2 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_CRCZI1_Pos (11UL) /*!< CRCZI1 (Bit 11) */ + #define R_ENDAT0_STATR_CRCZI1_Msk (0x800UL) /*!< CRCZI1 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_CRCZI2_Pos (12UL) /*!< CRCZI2 (Bit 12) */ + #define R_ENDAT0_STATR_CRCZI2_Msk (0x1000UL) /*!< CRCZI2 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_BUSY_Pos (13UL) /*!< BUSY (Bit 13) */ + #define R_ENDAT0_STATR_BUSY_Msk (0x2000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_RM_Pos (14UL) /*!< RM (Bit 14) */ + #define R_ENDAT0_STATR_RM_Msk (0x4000UL) /*!< RM (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_WRN_Pos (15UL) /*!< WRN (Bit 15) */ + #define R_ENDAT0_STATR_WRN_Msk (0x8000UL) /*!< WRN (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_SPIKE_Pos (16UL) /*!< SPIKE (Bit 16) */ + #define R_ENDAT0_STATR_SPIKE_Msk (0x10000UL) /*!< SPIKE (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_WTDG_Pos (17UL) /*!< WTDG (Bit 17) */ + #define R_ENDAT0_STATR_WTDG_Msk (0x20000UL) /*!< WTDG (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_FTYPIII_Pos (18UL) /*!< FTYPIII (Bit 18) */ + #define R_ENDAT0_STATR_FTYPIII_Msk (0x40000UL) /*!< FTYPIII (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_LZK_Pos (22UL) /*!< LZK (Bit 22) */ + #define R_ENDAT0_STATR_LZK_Msk (0x400000UL) /*!< LZK (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_LZM_Pos (23UL) /*!< LZM (Bit 23) */ + #define R_ENDAT0_STATR_LZM_Msk (0x800000UL) /*!< LZM (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_SPDRDY_Pos (29UL) /*!< SPDRDY (Bit 29) */ + #define R_ENDAT0_STATR_SPDRDY_Msk (0x20000000UL) /*!< SPDRDY (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_RDY4STRB_Pos (30UL) /*!< RDY4STRB (Bit 30) */ + #define R_ENDAT0_STATR_RDY4STRB_Msk (0x40000000UL) /*!< RDY4STRB (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_STATR_RDY_Pos (31UL) /*!< RDY (Bit 31) */ + #define R_ENDAT0_STATR_RDY_Msk (0x80000000UL) /*!< RDY (Bitfield-Mask: 0x01) */ +/* ========================================================= INTMR ========================================================= */ + #define R_ENDAT0_INTMR_EMPFR1_Pos (0UL) /*!< EMPFR1 (Bit 0) */ + #define R_ENDAT0_INTMR_EMPFR1_Msk (0x1UL) /*!< EMPFR1 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_ERR1_Pos (1UL) /*!< ERR1 (Bit 1) */ + #define R_ENDAT0_INTMR_ERR1_Msk (0x2UL) /*!< ERR1 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_CRC_PRTY_Pos (2UL) /*!< CRC_PRTY (Bit 2) */ + #define R_ENDAT0_INTMR_CRC_PRTY_Msk (0x4UL) /*!< CRC_PRTY (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_FTYPI_Pos (3UL) /*!< FTYPI (Bit 3) */ + #define R_ENDAT0_INTMR_FTYPI_Msk (0x8UL) /*!< FTYPI (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_FTYPII_Pos (4UL) /*!< FTYPII (Bit 4) */ + #define R_ENDAT0_INTMR_FTYPII_Msk (0x10UL) /*!< FTYPII (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_MRS_ADR_Pos (5UL) /*!< MRS_ADR (Bit 5) */ + #define R_ENDAT0_INTMR_MRS_ADR_Msk (0x20UL) /*!< MRS_ADR (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_EMPFR2_Pos (8UL) /*!< EMPFR2 (Bit 8) */ + #define R_ENDAT0_INTMR_EMPFR2_Msk (0x100UL) /*!< EMPFR2 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_EMPFR3_Pos (9UL) /*!< EMPFR3 (Bit 9) */ + #define R_ENDAT0_INTMR_EMPFR3_Msk (0x200UL) /*!< EMPFR3 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_IERR2_Pos (10UL) /*!< IERR2 (Bit 10) */ + #define R_ENDAT0_INTMR_IERR2_Msk (0x400UL) /*!< IERR2 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_CRCZI1_Pos (11UL) /*!< CRCZI1 (Bit 11) */ + #define R_ENDAT0_INTMR_CRCZI1_Msk (0x800UL) /*!< CRCZI1 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_CRCZI2_Pos (12UL) /*!< CRCZI2 (Bit 12) */ + #define R_ENDAT0_INTMR_CRCZI2_Msk (0x1000UL) /*!< CRCZI2 (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_BUSY_Pos (13UL) /*!< BUSY (Bit 13) */ + #define R_ENDAT0_INTMR_BUSY_Msk (0x2000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_RM_Pos (14UL) /*!< RM (Bit 14) */ + #define R_ENDAT0_INTMR_RM_Msk (0x4000UL) /*!< RM (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_WRN_Pos (15UL) /*!< WRN (Bit 15) */ + #define R_ENDAT0_INTMR_WRN_Msk (0x8000UL) /*!< WRN (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_SPIKE_Pos (16UL) /*!< SPIKE (Bit 16) */ + #define R_ENDAT0_INTMR_SPIKE_Msk (0x10000UL) /*!< SPIKE (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_WTDG_Pos (17UL) /*!< WTDG (Bit 17) */ + #define R_ENDAT0_INTMR_WTDG_Msk (0x20000UL) /*!< WTDG (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_FTYPIII_Pos (18UL) /*!< FTYPIII (Bit 18) */ + #define R_ENDAT0_INTMR_FTYPIII_Msk (0x40000UL) /*!< FTYPIII (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_SPDRDY_Pos (29UL) /*!< SPDRDY (Bit 29) */ + #define R_ENDAT0_INTMR_SPDRDY_Msk (0x20000000UL) /*!< SPDRDY (Bitfield-Mask: 0x01) */ + #define R_ENDAT0_INTMR_RDY_Pos (31UL) /*!< RDY (Bit 31) */ + #define R_ENDAT0_INTMR_RDY_Msk (0x80000000UL) /*!< RDY (Bitfield-Mask: 0x01) */ +/* ======================================================== SWSTRBR ======================================================== */ +/* ========================================================== IDR ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_AFMT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== COMMAND ======================================================== */ + #define R_AFMT0_COMMAND_XEA_Pos (0UL) /*!< XEA (Bit 0) */ + #define R_AFMT0_COMMAND_XEA_Msk (0x7UL) /*!< XEA (Bitfield-Mask: 0x07) */ + #define R_AFMT0_COMMAND_CC_Pos (3UL) /*!< CC (Bit 3) */ + #define R_AFMT0_COMMAND_CC_Msk (0xf8UL) /*!< CC (Bitfield-Mask: 0x1f) */ + #define R_AFMT0_COMMAND_SID_Pos (8UL) /*!< SID (Bit 8) */ + #define R_AFMT0_COMMAND_SID_Msk (0x1f00UL) /*!< SID (Bitfield-Mask: 0x1f) */ +/* ====================================================== ENC1RXDATA0 ====================================================== */ + #define R_AFMT0_ENC1RXDATA0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC1RXDATA0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC2RXDATA0 ====================================================== */ + #define R_AFMT0_ENC2RXDATA0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC2RXDATA0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC3RXDATA0 ====================================================== */ + #define R_AFMT0_ENC3RXDATA0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC3RXDATA0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC4RXDATA0 ====================================================== */ + #define R_AFMT0_ENC4RXDATA0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC4RXDATA0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC5RXDATA0 ====================================================== */ + #define R_AFMT0_ENC5RXDATA0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC5RXDATA0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC6RXDATA0 ====================================================== */ + #define R_AFMT0_ENC6RXDATA0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC6RXDATA0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC7RXDATA0 ====================================================== */ + #define R_AFMT0_ENC7RXDATA0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC7RXDATA0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC8RXDATA0 ====================================================== */ + #define R_AFMT0_ENC8RXDATA0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC8RXDATA0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC1RXDATA1 ====================================================== */ + #define R_AFMT0_ENC1RXDATA1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC1RXDATA1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC2RXDATA1 ====================================================== */ + #define R_AFMT0_ENC2RXDATA1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC2RXDATA1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC3RXDATA1 ====================================================== */ + #define R_AFMT0_ENC3RXDATA1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC3RXDATA1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC4RXDATA1 ====================================================== */ + #define R_AFMT0_ENC4RXDATA1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC4RXDATA1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC5RXDATA1 ====================================================== */ + #define R_AFMT0_ENC5RXDATA1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC5RXDATA1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC6RXDATA1 ====================================================== */ + #define R_AFMT0_ENC6RXDATA1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC6RXDATA1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC7RXDATA1 ====================================================== */ + #define R_AFMT0_ENC7RXDATA1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC7RXDATA1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC8RXDATA1 ====================================================== */ + #define R_AFMT0_ENC8RXDATA1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC8RXDATA1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ROMDATA ======================================================== */ + #define R_AFMT0_ROMDATA_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ROMDATA_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_AFMT0_ROMDATA_ADDR_Pos (16UL) /*!< ADDR (Bit 16) */ + #define R_AFMT0_ROMDATA_ADDR_Msk (0xff0000UL) /*!< ADDR (Bitfield-Mask: 0xff) */ +/* ====================================================== ENC1RXDATA2 ====================================================== */ + #define R_AFMT0_ENC1RXDATA2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC1RXDATA2_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC2RXDATA2 ====================================================== */ + #define R_AFMT0_ENC2RXDATA2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC2RXDATA2_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC3RXDATA2 ====================================================== */ + #define R_AFMT0_ENC3RXDATA2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC3RXDATA2_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC4RXDATA2 ====================================================== */ + #define R_AFMT0_ENC4RXDATA2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC4RXDATA2_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC5RXDATA2 ====================================================== */ + #define R_AFMT0_ENC5RXDATA2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC5RXDATA2_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC6RXDATA2 ====================================================== */ + #define R_AFMT0_ENC6RXDATA2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC6RXDATA2_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC7RXDATA2 ====================================================== */ + #define R_AFMT0_ENC7RXDATA2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC7RXDATA2_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC8RXDATA2 ====================================================== */ + #define R_AFMT0_ENC8RXDATA2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC8RXDATA2_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== ID =========================================================== */ + #define R_AFMT0_ID_ID_L_Pos (0UL) /*!< ID_L (Bit 0) */ + #define R_AFMT0_ID_ID_L_Msk (0xffffUL) /*!< ID_L (Bitfield-Mask: 0xffff) */ + #define R_AFMT0_ID_ID_H_Pos (16UL) /*!< ID_H (Bit 16) */ + #define R_AFMT0_ID_ID_H_Msk (0xff0000UL) /*!< ID_H (Bitfield-Mask: 0xff) */ +/* ====================================================== ENC1RXDATA3 ====================================================== */ + #define R_AFMT0_ENC1RXDATA3_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC1RXDATA3_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC2RXDATA3 ====================================================== */ + #define R_AFMT0_ENC2RXDATA3_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC2RXDATA3_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC3RXDATA3 ====================================================== */ + #define R_AFMT0_ENC3RXDATA3_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC3RXDATA3_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC4RXDATA3 ====================================================== */ + #define R_AFMT0_ENC4RXDATA3_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC4RXDATA3_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC5RXDATA3 ====================================================== */ + #define R_AFMT0_ENC5RXDATA3_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC5RXDATA3_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC6RXDATA3 ====================================================== */ + #define R_AFMT0_ENC6RXDATA3_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC6RXDATA3_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC7RXDATA3 ====================================================== */ + #define R_AFMT0_ENC7RXDATA3_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC7RXDATA3_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC8RXDATA3 ====================================================== */ + #define R_AFMT0_ENC8RXDATA3_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC8RXDATA3_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC1RXDATA4 ====================================================== */ + #define R_AFMT0_ENC1RXDATA4_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC1RXDATA4_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC2RXDATA4 ====================================================== */ + #define R_AFMT0_ENC2RXDATA4_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC2RXDATA4_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC3RXDATA4 ====================================================== */ + #define R_AFMT0_ENC3RXDATA4_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC3RXDATA4_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC4RXDATA4 ====================================================== */ + #define R_AFMT0_ENC4RXDATA4_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC4RXDATA4_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC5RXDATA4 ====================================================== */ + #define R_AFMT0_ENC5RXDATA4_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC5RXDATA4_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC6RXDATA4 ====================================================== */ + #define R_AFMT0_ENC6RXDATA4_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC6RXDATA4_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC7RXDATA4 ====================================================== */ + #define R_AFMT0_ENC7RXDATA4_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC7RXDATA4_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC8RXDATA4 ====================================================== */ + #define R_AFMT0_ENC8RXDATA4_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC8RXDATA4_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC1RXDATA5 ====================================================== */ + #define R_AFMT0_ENC1RXDATA5_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC1RXDATA5_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC2RXDATA5 ====================================================== */ + #define R_AFMT0_ENC2RXDATA5_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC2RXDATA5_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC3RXDATA5 ====================================================== */ + #define R_AFMT0_ENC3RXDATA5_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC3RXDATA5_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC4RXDATA5 ====================================================== */ + #define R_AFMT0_ENC4RXDATA5_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC4RXDATA5_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC5RXDATA5 ====================================================== */ + #define R_AFMT0_ENC5RXDATA5_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC5RXDATA5_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC6RXDATA5 ====================================================== */ + #define R_AFMT0_ENC6RXDATA5_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC6RXDATA5_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC7RXDATA5 ====================================================== */ + #define R_AFMT0_ENC7RXDATA5_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC7RXDATA5_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC8RXDATA5 ====================================================== */ + #define R_AFMT0_ENC8RXDATA5_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC8RXDATA5_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC1RXDATA6 ====================================================== */ + #define R_AFMT0_ENC1RXDATA6_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC1RXDATA6_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC2RXDATA6 ====================================================== */ + #define R_AFMT0_ENC2RXDATA6_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC2RXDATA6_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC3RXDATA6 ====================================================== */ + #define R_AFMT0_ENC3RXDATA6_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC3RXDATA6_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC4RXDATA6 ====================================================== */ + #define R_AFMT0_ENC4RXDATA6_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC4RXDATA6_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC5RXDATA6 ====================================================== */ + #define R_AFMT0_ENC5RXDATA6_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC5RXDATA6_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC6RXDATA6 ====================================================== */ + #define R_AFMT0_ENC6RXDATA6_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC6RXDATA6_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC7RXDATA6 ====================================================== */ + #define R_AFMT0_ENC7RXDATA6_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC7RXDATA6_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC8RXDATA6 ====================================================== */ + #define R_AFMT0_ENC8RXDATA6_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC8RXDATA6_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC1RXDATA7 ====================================================== */ + #define R_AFMT0_ENC1RXDATA7_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC1RXDATA7_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC2RXDATA7 ====================================================== */ + #define R_AFMT0_ENC2RXDATA7_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC2RXDATA7_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC3RXDATA7 ====================================================== */ + #define R_AFMT0_ENC3RXDATA7_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC3RXDATA7_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC4RXDATA7 ====================================================== */ + #define R_AFMT0_ENC4RXDATA7_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC4RXDATA7_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC5RXDATA7 ====================================================== */ + #define R_AFMT0_ENC5RXDATA7_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC5RXDATA7_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC6RXDATA7 ====================================================== */ + #define R_AFMT0_ENC6RXDATA7_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC6RXDATA7_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC7RXDATA7 ====================================================== */ + #define R_AFMT0_ENC7RXDATA7_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC7RXDATA7_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ENC8RXDATA7 ====================================================== */ + #define R_AFMT0_ENC8RXDATA7_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_AFMT0_ENC8RXDATA7_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TRGSEL ========================================================= */ + #define R_AFMT0_TRGSEL_EXT_Pos (0UL) /*!< EXT (Bit 0) */ + #define R_AFMT0_TRGSEL_EXT_Msk (0x1UL) /*!< EXT (Bitfield-Mask: 0x01) */ +/* ========================================================= TXTRG ========================================================= */ + #define R_AFMT0_TXTRG_TRG_Pos (0UL) /*!< TRG (Bit 0) */ + #define R_AFMT0_TXTRG_TRG_Msk (0x1UL) /*!< TRG (Bitfield-Mask: 0x01) */ +/* ========================================================= BRSEL ========================================================= */ + #define R_AFMT0_BRSEL_BR_Pos (0UL) /*!< BR (Bit 0) */ + #define R_AFMT0_BRSEL_BR_Msk (0x7UL) /*!< BR (Bitfield-Mask: 0x07) */ + #define R_AFMT0_BRSEL_AS_Pos (3UL) /*!< AS (Bit 3) */ + #define R_AFMT0_BRSEL_AS_Msk (0x8UL) /*!< AS (Bitfield-Mask: 0x01) */ + #define R_AFMT0_BRSEL_TM_Pos (4UL) /*!< TM (Bit 4) */ + #define R_AFMT0_BRSEL_TM_Msk (0xff0UL) /*!< TM (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_ENCOUT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CTL ========================================================== */ + #define R_ENCOUT_CTL_POL_Pos (0UL) /*!< POL (Bit 0) */ + #define R_ENCOUT_CTL_POL_Msk (0x1UL) /*!< POL (Bitfield-Mask: 0x01) */ + #define R_ENCOUT_CTL_ZW_Pos (1UL) /*!< ZW (Bit 1) */ + #define R_ENCOUT_CTL_ZW_Msk (0xeUL) /*!< ZW (Bitfield-Mask: 0x07) */ + #define R_ENCOUT_CTL_ZS_Pos (4UL) /*!< ZS (Bit 4) */ + #define R_ENCOUT_CTL_ZS_Msk (0x10UL) /*!< ZS (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_ENCOUT_STR_ENCE_Pos (0UL) /*!< ENCE (Bit 0) */ + #define R_ENCOUT_STR_ENCE_Msk (0x1UL) /*!< ENCE (Bitfield-Mask: 0x01) */ +/* ===================================================== POSMAX_PERIOD ===================================================== */ + #define R_ENCOUT_POSMAX_PERIOD_PERIOD_Pos (0UL) /*!< PERIOD (Bit 0) */ + #define R_ENCOUT_POSMAX_PERIOD_PERIOD_Msk (0xffffUL) /*!< PERIOD (Bitfield-Mask: 0xffff) */ + #define R_ENCOUT_POSMAX_PERIOD_POSMAX_Pos (16UL) /*!< POSMAX (Bit 16) */ + #define R_ENCOUT_POSMAX_PERIOD_POSMAX_Msk (0xffff0000UL) /*!< POSMAX (Bitfield-Mask: 0xffff) */ +/* ======================================================== OUTCNT ========================================================= */ + #define R_ENCOUT_OUTCNT_EDGCNT_Pos (0UL) /*!< EDGCNT (Bit 0) */ + #define R_ENCOUT_OUTCNT_EDGCNT_Msk (0xffffUL) /*!< EDGCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================== POSCNT ========================================================= */ + #define R_ENCOUT_POSCNT_POSCNT_Pos (0UL) /*!< POSCNT (Bit 0) */ + #define R_ENCOUT_POSCNT_POSCNT_Msk (0xffffUL) /*!< POSCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_GSC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CNTCR ========================================================= */ + #define R_GSC_CNTCR_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GSC_CNTCR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GSC_CNTCR_HDBG_Pos (1UL) /*!< HDBG (Bit 1) */ + #define R_GSC_CNTCR_HDBG_Msk (0x2UL) /*!< HDBG (Bitfield-Mask: 0x01) */ +/* ========================================================= CNTSR ========================================================= */ + #define R_GSC_CNTSR_DBGH_Pos (1UL) /*!< DBGH (Bit 1) */ + #define R_GSC_CNTSR_DBGH_Msk (0x2UL) /*!< DBGH (Bitfield-Mask: 0x01) */ +/* ======================================================== CNTCVL ========================================================= */ + #define R_GSC_CNTCVL_CNTCVL_L_32_Pos (0UL) /*!< CNTCVL_L_32 (Bit 0) */ + #define R_GSC_CNTCVL_CNTCVL_L_32_Msk (0xffffffffUL) /*!< CNTCVL_L_32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CNTCVU ========================================================= */ + #define R_GSC_CNTCVU_CNTCVU_U_32_Pos (0UL) /*!< CNTCVU_U_32 (Bit 0) */ + #define R_GSC_CNTCVU_CNTCVU_U_32_Msk (0xffffffffUL) /*!< CNTCVU_U_32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CNTFID0 ======================================================== */ + #define R_GSC_CNTFID0_FREQ_Pos (0UL) /*!< FREQ (Bit 0) */ + #define R_GSC_CNTFID0_FREQ_Msk (0xffffffffUL) /*!< FREQ (Bitfield-Mask: 0xffffffff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R9A07G074_H */ + +/** @} */ /* End of group R9A07G074 */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G075.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G075.h new file mode 100644 index 00000000000..e8dedd2309b --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G075.h @@ -0,0 +1,38375 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R9A07G075 + * @{ + */ + +#ifndef R9A07G075_H + #define R9A07G075_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ----------------Configuration of the Cortex-M Processor and Core Peripherals---------------- */ + #ifdef RENESAS_CORTEX_M4 + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ + #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ + #elif defined(RENESAS_CORTEX_M0PLUS) + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 0 /*!< FPU present or not */ + #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */ + #include "core_cm0plus.h" /*!< Cortex-M0 processor and core peripherals */ + #elif defined(RENESAS_CORTEX_M23) + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 0 /*!< FPU present or not */ + #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */ + #include "core_cm23.h" /*!< Cortex-M23 processor and core peripherals */ + #elif defined(RENESAS_CORTEX_M33) + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ + #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */ + #define __DSP_PRESENT 1 /*!< DSP present or not */ + #include "core_cm33.h" /*!< Cortex-M33 processor and core peripherals */ + #elif defined(RENESAS_CORTEX_R52) + #define __FPU_PRESENT 1 /*!< FPU present or not */ + #include "core_cr52.h" /*!< Cortex-R52 processor and core peripherals */ + #endif + + #include "system.h" /*!< System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_CANFD_CFDC [CFDC] (CANFD Channel [0..1] Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel n Nominal Bit Rate Configuration Register */ + + struct + { + __IOM uint32_t NBRP : 10; /*!< [9..0] Nominal Bit Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Nominal Bit Rate Resynchronization Jump Width Control */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Nominal Bit Rate Time Segment 1 Control */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Nominal Bit Rate Time Segment 2 Control */ + } NCFG_b; + }; + + union + { + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel n Control Register */ + + struct + { + __IOM uint32_t CHMDC : 2; /*!< [1..0] Mode Select */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Stop Mode */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Forcible Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission Abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error Occurrence Counter Overflow Interrupt Enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt Enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Bus-Off Recovery Mode Select */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Error Display Mode Select */ + __IOM uint32_t CTME : 1; /*!< [24..24] Communication Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Communication Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test Enable */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode Enable */ + } CTR_b; + }; + + union + { + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel n Status Register */ + + struct + { + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel Reset Status Flag */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel Halt Status Flag */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel Stop Status Flag */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Error Passive Status Flag */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Bus-Off Status Flag */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Transmit Status Flag */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Receive Status Flag */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Communication Status Flag */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; + }; + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel n Error Flag Register */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error Flag */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error Flag */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error Flag */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error Flag */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Recessive Bit Error Flag */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Dominant Bit Error Flag */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error Flag */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Calculation Data (CRC length: 15 bits) */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bit Rate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Data Bit Rate Prescaler Division Ratio Setting */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Data Bit Rate Time Segment 1 Control */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Data Bit Rate Time Segment 2 Control */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Data Bit Rate Resynchronization Jump Width Control */ + uint32_t : 4; + } DCFG_b; + }; + + union + { + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel n CAN-FD Configuration Register */ + + struct + { + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transmitter Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD Multi Gateway Enable */ + __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF Configuration Bit */ + __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS Configuration Bit */ + uint32_t : 1; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD-Only Enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX Edge Filter Enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN-Only Enable */ + __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD Frame Distinction Enable */ + } FDCFG_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel n CAN-FD Control Register */ + + struct + { + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel n CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error Occurrence Counter Overflow Flag */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful Occurrence Counter Overflow Flag */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error Occurrence Counter */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful Occurrence Counter */ + } FDSTS_b; + }; + + union + { + __IM uint32_t FDCRC; /*!< (@ 0x00000010) Channel n CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register Value */ + uint32_t : 4; + __IM uint32_t SCNT : 4; /*!< [28..25] Stuff Bit Count */ + uint32_t : 3; + } FDCRC_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel n Bus Load Control Register */ + + struct + { + __IOM uint32_t BLCE : 1; /*!< [0..0] Bus Load Counter Enable */ + uint32_t : 7; + __OM uint32_t BLCLD : 1; /*!< [8..8] Bus Load Counter Load */ + uint32_t : 23; + } BLCT_b; + }; + + union + { + __IM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel n Bus Load Status Register */ + + struct + { + uint32_t : 3; + __IM uint32_t BLC : 29; /*!< [31..3] Bus Load Counter Status */ + } BLSTS_b; + }; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Register n */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; + + union + { + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Register n */ + + struct + { + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; + }; + + union + { + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Register + * n */ + + struct + { + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing Destination + * 0 */ + __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing Destination + * 1 */ + __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing Destination + * 2 */ + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer */ + } P0_b; + }; + + union + { + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Register + * n */ + + struct + { + __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 18; + } P1_b; + }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Bit */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + + struct + { + __IOM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IOM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + union + { + __IM uint32_t DF_WD[16]; /*!< (@ 0x0000000C) RX Message Buffer Data Field p Register n (p + * = 0 to 15, n = 0 to 31) */ + + struct + { + __IM uint32_t RMDB_LL : 8; /*!< [7..0] RX Message Buffer Data Byte (4 * p) */ + __IM uint32_t RMDB_LH : 8; /*!< [15..8] RX Message Buffer Data Byte (4 * p + 1) */ + __IM uint32_t RMDB_HL : 8; /*!< [23..16] RX Message Buffer Data Byte (4 * p + 2) */ + __IM uint32_t RMDB_HH : 8; /*!< [31..24] RX Message Buffer Data Byte (4 * p + 3) */ + } DF_WD_b[16]; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field p Register n (p + * = 0 to 63, n = 0 to 31) */ + + struct + { + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; + }; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register n */ + + struct + { + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR bit */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register n */ + + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Value */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register n */ + + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t CFDRFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + union + { + __IM uint32_t DF_WD[16]; /*!< (@ 0x0000000C) RX FIFO Access Data Field p Register n (p = 0 + * to 15, n = 0 to 7) */ + + struct + { + __IM uint32_t RFDB_LL : 8; /*!< [7..0] RX FIFO Buffer Data Byte (4 * p) */ + __IM uint32_t RFDB_LH : 8; /*!< [15..8] RX FIFO Buffer Data Byte (4 * p + 1) */ + __IM uint32_t RFDB_HL : 8; /*!< [23..16] RX FIFO Buffer Data Byte (4 * p + 2) */ + __IM uint32_t RFDB_HH : 8; /*!< [31..24] RX FIFO Buffer Data Byte (4 * p + 3) */ + } DF_WD_b[16]; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field p Register n (p = 0 + * to 63, n = 0 to 7) */ + + struct + { + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; + }; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + + struct + { + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry Enable */ + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR bit */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register n */ + + struct + { + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Value */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Control/Status Register + * n */ + + struct + { + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] COMMON FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDCSTS_b; + }; + + union + { + union + { + __IOM uint32_t DF_WD[16]; /*!< (@ 0x0000000C) Common FIFO Access Data Field p Register n (p + * = 0 to 15, n = 0 to 5) */ + + struct + { + __IOM uint32_t CFDB_LL : 8; /*!< [7..0] Common FIFO Buffer Data Bytes (4 * p) */ + __IOM uint32_t CFDB_LH : 8; /*!< [15..8] Common FIFO Buffer Data Bytes (4 * p + 1) */ + __IOM uint32_t CFDB_HL : 8; /*!< [23..16] Common FIFO Buffer Data Bytes (4 * p + 2) */ + __IOM uint32_t CFDB_HH : 8; /*!< [31..24] Common FIFO Buffer Data Bytes (4 * p + 3) */ + } DF_WD_b[16]; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field p Register n (p + * = 0 to 63, n = 0 to 5) */ + + struct + { + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Bytes */ + } DF_b[64]; + }; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ + union + { + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + + struct + { + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer Number */ + uint32_t : 5; + __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer Indication */ + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; + + union + { + __IM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register n (n = 0 to 127) */ + + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR bit */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register n (n = 0 to + * 127) */ + + struct + { + uint32_t : 28; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register n (n + * = 0 to 127) */ + + struct + { + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; + }; + + union + { + union + { + __IOM uint32_t DF_WD[16]; /*!< (@ 0x0000000C) TX Message Buffer Data Field p Register n (p + * = 0 to 15, n = 0 to 127) */ + + struct + { + __IOM uint32_t TMDB_LL : 8; /*!< [7..0] TX Message Buffer Data Byte (4 * p) */ + __IOM uint32_t TMDB_LH : 8; /*!< [15..8] TX Message Buffer Data Byte (4 * p + 1) */ + __IOM uint32_t TMDB_HL : 8; /*!< [23..16] TX Message Buffer Data Byte (4 * p + 2) */ + __IOM uint32_t TMDB_HH : 8; /*!< [31..24] TX Message Buffer Data Byte (4 * p + 3) */ + } DF_WD_b[16]; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field p Register n (p + * = 0 to 63, n = 0 to 5) */ + + struct + { + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Bytes */ + } DF_b[64]; + }; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CMT_UNT_CM [CM] (2 Timer Start Register Pairs) + */ +typedef struct +{ + union + { + __IOM uint16_t CR; /*!< (@ 0x00000000) Compare Match Timer Control Register */ + + struct + { + __IOM uint16_t CKS : 2; /*!< [1..0] Clock Select */ + uint16_t : 4; + __IOM uint16_t CMIE : 1; /*!< [6..6] Compare Match Interrupt Enable */ + uint16_t : 9; + } CR_b; + }; + __IOM uint16_t CNT; /*!< (@ 0x00000002) Compare Match Timer Counter Register */ + __IOM uint16_t COR; /*!< (@ 0x00000004) Compare Match Timer Constant Register */ +} R_CMT_UNT_CM_Type; /*!< Size = 6 (0x6) */ + +/** + * @brief R_CMT_UNT [UNT] (3 Timer Start Register Units) + */ +typedef struct +{ + union + { + __IOM uint16_t CMSTR0; /*!< (@ 0x00000000) Compare Match Timer Start Register */ + + struct + { + __IOM uint16_t STR0 : 1; /*!< [0..0] CMT Channel n Count Start */ + __IOM uint16_t STR1 : 1; /*!< [1..1] CMT Channel n+1 Count Start */ + uint16_t : 14; + } CMSTR0_b; + }; + __IOM R_CMT_UNT_CM_Type CM[2]; /*!< (@ 0x00000002) 2 Timer Start Register Pairs */ + __IM uint16_t RESERVED[505]; +} R_CMT_UNT_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L y (y = 0 to 2) */ + + struct + { + __IOM uint8_t SVA0 : 1; /*!< [0..0] 10-bit Address LSB */ + __IOM uint8_t SVA : 7; /*!< [7..1] 7-bit Address/10-bit Address Lower Bits */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U y (y = 0 to 2) */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-bit/10-bit Address Format Select */ + __IOM uint8_t SVA : 2; /*!< [2..1] 10-bit Address Upper Bits */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_DMAC0_GRP_CH_N [N] (DMAC Address Registers [0..1]) + */ +typedef struct +{ + __IOM uint32_t SA; /*!< (@ 0x00000000) Nextm0 Source Address Register n */ + __IOM uint32_t DA; /*!< (@ 0x00000004) Nextm0 Destination Address Register n (m = 0, + * 1) (n = 0 to 15) */ + __IOM uint32_t TB; /*!< (@ 0x00000008) Nextm0 Transaction Byte Register n (m = 0, 1) + * (n = 0 to 15) */ +} R_DMAC0_GRP_CH_N_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_DMAC0_GRP_CH [CH] (DMAC channel Control Register [0..7]) + */ +typedef struct +{ + __IOM R_DMAC0_GRP_CH_N_Type N[2]; /*!< (@ 0x00000000) DMAC Address Registers [0..1] */ + __IM uint32_t CRSA; /*!< (@ 0x00000018) Current Source Address Register n (n = 0 to 15) */ + __IM uint32_t CRDA; /*!< (@ 0x0000001C) Current Destination Address Register n (n = 0 + * to 15) */ + __IM uint32_t CRTB; /*!< (@ 0x00000020) Current Transaction Byte Register n */ + + union + { + __IM uint32_t CHSTAT; /*!< (@ 0x00000024) Channel Status Register n */ + + struct + { + __IM uint32_t EN : 1; /*!< [0..0] DMA Activation Enable */ + __IM uint32_t RQST : 1; /*!< [1..1] DMA Transfer Request */ + __IM uint32_t TACT : 1; /*!< [2..2] DMAC Operating Status */ + __IM uint32_t SUS : 1; /*!< [3..3] Suspend */ + __IM uint32_t ER : 1; /*!< [4..4] DMA Error */ + __IM uint32_t END : 1; /*!< [5..5] DMA Transfer Completion Interrupt */ + __IM uint32_t TC : 1; /*!< [6..6] DMA Transfer Completion (total number of data bytes for + * transaction) */ + __IM uint32_t SR : 1; /*!< [7..7] Next Register Select */ + __IM uint32_t DL : 1; /*!< [8..8] Descriptor Load */ + __IM uint32_t DW : 1; /*!< [9..9] Descriptor Write Back */ + __IM uint32_t DER : 1; /*!< [10..10] Descriptor Error */ + __IM uint32_t MODE : 1; /*!< [11..11] DMA Mode */ + uint32_t : 4; + __IM uint32_t INTM : 1; /*!< [16..16] DMA Transfer Completion Interrupt Request Mask */ + uint32_t : 15; + } CHSTAT_b; + }; + + union + { + __IOM uint32_t CHCTRL; /*!< (@ 0x00000028) Channel Control Register n */ + + struct + { + __IOM uint32_t SETEN : 1; /*!< [0..0] DMA Activation Enable */ + __IOM uint32_t CLREN : 1; /*!< [1..1] DMA Activation Enable Clear */ + __IOM uint32_t STG : 1; /*!< [2..2] Software Trigger */ + __IOM uint32_t SWRST : 1; /*!< [3..3] Software Reset */ + __IOM uint32_t CLRRQ : 1; /*!< [4..4] DMA Transfer Request Clear */ + __IOM uint32_t CLREND : 1; /*!< [5..5] END Clear */ + __IOM uint32_t CLRTC : 1; /*!< [6..6] TC Clear */ + uint32_t : 1; + __IOM uint32_t SETSUS : 1; /*!< [8..8] Suspend Request */ + __IOM uint32_t CLRSUS : 1; /*!< [9..9] Suspend Clear */ + uint32_t : 6; + __IOM uint32_t SETINTM : 1; /*!< [16..16] DMA Transfer Completion Interrupt Request Mask */ + __IOM uint32_t CLRINTM : 1; /*!< [17..17] DMA Transfer Completion Interrupt Request Mask Clear */ + uint32_t : 14; + } CHCTRL_b; + }; + + union + { + __IOM uint32_t CHCFG; /*!< (@ 0x0000002C) Channel Configuration Register n */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Pin Select */ + __IOM uint32_t REQD : 1; /*!< [3..3] DMA Activation Request Source Select */ + __IOM uint32_t LOEN : 1; /*!< [4..4] L Detection Enable */ + __IOM uint32_t HIEN : 1; /*!< [5..5] H Detection Enable */ + __IOM uint32_t LVL : 1; /*!< [6..6] Level Detection Enable */ + uint32_t : 1; + __IOM uint32_t AM : 3; /*!< [10..8] ACK Mode */ + uint32_t : 1; + __IOM uint32_t SDS : 4; /*!< [15..12] Source Data Size */ + __IOM uint32_t DDS : 4; /*!< [19..16] Destination Data Size */ + __IOM uint32_t SAD : 1; /*!< [20..20] Source Address Count Direction */ + __IOM uint32_t DAD : 1; /*!< [21..21] Destination Address Count Direction */ + __IOM uint32_t TM : 1; /*!< [22..22] Transfer Mode */ + uint32_t : 1; + __IOM uint32_t DEM : 1; /*!< [24..24] DMA Transfer Completion Interrupt Mask */ + __IOM uint32_t TCM : 1; /*!< [25..25] TEND Mask */ + uint32_t : 1; + __IOM uint32_t SBE : 1; /*!< [27..27] Buffer Flush Enable */ + __IOM uint32_t RSEL : 1; /*!< [28..28] Next Register Select */ + __IOM uint32_t RSW : 1; /*!< [29..29] RSEL Reverse */ + __IOM uint32_t REN : 1; /*!< [30..30] Register Set Enable */ + __IOM uint32_t DMS : 1; /*!< [31..31] DMA Mode Select */ + } CHCFG_b; + }; + + union + { + __IOM uint32_t CHITVL; /*!< (@ 0x00000030) Channel Interval Register n */ + + struct + { + __IOM uint32_t ITVL : 16; /*!< [15..0] Interval */ + uint32_t : 16; + } CHITVL_b; + }; + + union + { + __IOM uint32_t CHEXT; /*!< (@ 0x00000034) Channel Extension Register n */ + + struct + { + __IOM uint32_t SPR : 3; /*!< [2..0] Source PROT */ + uint32_t : 1; + __IOM uint32_t SCA : 4; /*!< [7..4] Source CACHE */ + __IOM uint32_t DPR : 3; /*!< [10..8] Destination PROT */ + uint32_t : 1; + __IOM uint32_t DCA : 4; /*!< [15..12] Destination CACHE */ + uint32_t : 16; + } CHEXT_b; + }; + __IOM uint32_t NXLA; /*!< (@ 0x00000038) DMA Destination Address Register */ + __IM uint32_t CRLA; /*!< (@ 0x0000003C) Current Link Address Register n */ +} R_DMAC0_GRP_CH_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_DMAC0_GRP [GRP] (8 channel Registers) + */ +typedef struct +{ + __IOM R_DMAC0_GRP_CH_Type CH[8]; /*!< (@ 0x00000000) DMAC channel Control Register [0..7] */ + __IM uint32_t RESERVED[64]; + + union + { + __IOM uint32_t DCTRL; /*!< (@ 0x00000300) DMA Control Register A/B */ + + struct + { + __IOM uint32_t PR : 1; /*!< [0..0] Priority Control Select */ + __IOM uint32_t LVINT : 1; /*!< [1..1] DMA Interrupt Output Select */ + uint32_t : 30; + } DCTRL_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IM uint32_t DSTAT_EN; /*!< (@ 0x00000310) DMA Status EN Register A/B */ + + struct + { + __IM uint32_t EN0008 : 1; /*!< [0..0] Channel 0/8 EN */ + __IM uint32_t EN0109 : 1; /*!< [1..1] Channel 1/9 EN */ + __IM uint32_t EN0210 : 1; /*!< [2..2] Channel 2/10 EN */ + __IM uint32_t EN0311 : 1; /*!< [3..3] Channel 3/11 EN */ + __IM uint32_t EN0412 : 1; /*!< [4..4] Channel 4/12 EN */ + __IM uint32_t EN0513 : 1; /*!< [5..5] Channel 5/13 EN */ + __IM uint32_t EN0614 : 1; /*!< [6..6] Channel 6/14 EN */ + __IM uint32_t EN0715 : 1; /*!< [7..7] Channel 7/15 EN */ + uint32_t : 24; + } DSTAT_EN_b; + }; + + union + { + __IM uint32_t DSTAT_ER; /*!< (@ 0x00000314) DMA Status ER Register A/B */ + + struct + { + __IM uint32_t ER0008 : 1; /*!< [0..0] Channel 0/8 ER */ + __IM uint32_t ER0109 : 1; /*!< [1..1] Channel 1/9 ER */ + __IM uint32_t ER0210 : 1; /*!< [2..2] Channel 2/10 ER */ + __IM uint32_t ER0311 : 1; /*!< [3..3] Channel 3/11 ER */ + __IM uint32_t ER0412 : 1; /*!< [4..4] Channel 4/12 ER */ + __IM uint32_t ER0513 : 1; /*!< [5..5] Channel 5/13 ER */ + __IM uint32_t ER0614 : 1; /*!< [6..6] Channel 6/14 ER */ + __IM uint32_t ER0715 : 1; /*!< [7..7] Channel 7/15 ER */ + uint32_t : 24; + } DSTAT_ER_b; + }; + + union + { + __IM uint32_t DSTAT_END; /*!< (@ 0x00000318) DMA Status END Register A/B */ + + struct + { + __IM uint32_t END0008 : 1; /*!< [0..0] Channel 0/8 END */ + __IM uint32_t END0109 : 1; /*!< [1..1] Channel 1/9 END */ + __IM uint32_t END0210 : 1; /*!< [2..2] Channel 2/10 END */ + __IM uint32_t END0311 : 1; /*!< [3..3] Channel 3/11 END */ + __IM uint32_t END0412 : 1; /*!< [4..4] Channel 4/12 END */ + __IM uint32_t END0513 : 1; /*!< [5..5] Channel 5/13 END */ + __IM uint32_t END0614 : 1; /*!< [6..6] Channel 6/14 END */ + __IM uint32_t END0715 : 1; /*!< [7..7] Channel 7/15 END */ + uint32_t : 24; + } DSTAT_END_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t DSTAT_SUS; /*!< (@ 0x00000320) DMA Status SUS Register A/B */ + + struct + { + __IM uint32_t SUS0008 : 1; /*!< [0..0] Channel 0/8 SUS */ + __IM uint32_t SUS0109 : 1; /*!< [1..1] Channel 1/9 SUS */ + __IM uint32_t SUS0210 : 1; /*!< [2..2] Channel 2/10 SUS */ + __IM uint32_t SUS0311 : 1; /*!< [3..3] Channel 3/11 SUS */ + __IM uint32_t SUS0412 : 1; /*!< [4..4] Channel 4/12 SUS */ + __IM uint32_t SUS0513 : 1; /*!< [5..5] Channel 5/13 SUS */ + __IM uint32_t SUS0614 : 1; /*!< [6..6] Channel 6/14 SUS */ + __IM uint32_t SUS0715 : 1; /*!< [7..7] Channel 7/15 SUS */ + uint32_t : 24; + } DSTAT_SUS_b; + }; + __IM uint32_t RESERVED3[55]; +} R_DMAC0_GRP_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_PORT_DRCTL [DRCTL] (I/O Buffer [0..24] Function Switching Register) + */ +typedef struct +{ + union + { + __IOM uint32_t L; /*!< (@ 0x00000000) I/O Buffer m Function Switching Register 0-3 */ + + struct + { + __IOM uint32_t DRV0 : 2; /*!< [1..0] Pm_0 Driving Ability Control */ + __IOM uint32_t PUD0 : 2; /*!< [3..2] Pm_0 Pull-Up/Down Control */ + __IOM uint32_t SMT0 : 1; /*!< [4..4] Pm_0 Schmitt Trigger Control */ + __IOM uint32_t SR0 : 1; /*!< [5..5] Pm_0 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV1 : 2; /*!< [9..8] Pm_1 Driving Ability Control */ + __IOM uint32_t PUD1 : 2; /*!< [11..10] Pm_1 Pull-Up/Down Control */ + __IOM uint32_t SMT1 : 1; /*!< [12..12] Pm_1 Schmitt Trigger Control */ + __IOM uint32_t SR1 : 1; /*!< [13..13] Pm_1 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV2 : 2; /*!< [17..16] Pm_2 Driving Ability Control */ + __IOM uint32_t PUD2 : 2; /*!< [19..18] Pm_2 Pull-Up/Down Control */ + __IOM uint32_t SMT2 : 1; /*!< [20..20] Pm_2 Schmitt Trigger Control */ + __IOM uint32_t SR2 : 1; /*!< [21..21] Pm_2 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV3 : 2; /*!< [25..24] Pm_3 Driving Ability Control */ + __IOM uint32_t PUD3 : 2; /*!< [27..26] Pm_3 Pull-Up/Down Control */ + __IOM uint32_t SMT3 : 1; /*!< [28..28] Pm_3 Schmitt Trigger Control */ + __IOM uint32_t SR3 : 1; /*!< [29..29] Pm_3 Slew Rate Control */ + uint32_t : 2; + } L_b; + }; + + union + { + __IOM uint32_t H; /*!< (@ 0x00000004) I/O Buffer m Function Switching Register 4-7 */ + + struct + { + __IOM uint32_t DRV4 : 2; /*!< [1..0] Pm_4 Driving Ability Control */ + __IOM uint32_t PUD4 : 2; /*!< [3..2] Pm_4 Pull-Up/Down Control */ + __IOM uint32_t SMT4 : 1; /*!< [4..4] Pm_4 Schmitt Trigger Control */ + __IOM uint32_t SR4 : 1; /*!< [5..5] Pm_4 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV5 : 2; /*!< [9..8] Pm_5 Driving Ability Control */ + __IOM uint32_t PUD5 : 2; /*!< [11..10] Pm_5 Pull-Up/Down Control */ + __IOM uint32_t SMT5 : 1; /*!< [12..12] Pm_5 Schmitt Trigger Control */ + __IOM uint32_t SR5 : 1; /*!< [13..13] Pm_5 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV6 : 2; /*!< [17..16] Pm_6 Driving Ability Control */ + __IOM uint32_t PUD6 : 2; /*!< [19..18] Pm_6 Pull-Up/Down Control */ + __IOM uint32_t SMT6 : 1; /*!< [20..20] Pm_6 Schmitt Trigger Control */ + __IOM uint32_t SR6 : 1; /*!< [21..21] Pm_6 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV7 : 2; /*!< [25..24] Pm_7 Driving Ability Control */ + __IOM uint32_t PUD7 : 2; /*!< [27..26] Pm_7 Pull-Up/Down Control */ + __IOM uint32_t SMT7 : 1; /*!< [28..28] Pm_7 Schmitt Trigger Control */ + __IOM uint32_t SR7 : 1; /*!< [29..29] Pm_7 Slew Rate Control */ + uint32_t : 2; + } H_b; + }; +} R_PORT_DRCTL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_PORT_NSR_ELC_PDBF [ELC_PDBF] (ELC Port Buffer Register [0..1]) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) ELC Port Buffer Register n */ + + struct + { + __IOM uint8_t PB0 : 1; /*!< [0..0] Port Buffer 0 */ + __IOM uint8_t PB1 : 1; /*!< [1..1] Port Buffer 1 */ + __IOM uint8_t PB2 : 1; /*!< [2..2] Port Buffer 2 */ + __IOM uint8_t PB3 : 1; /*!< [3..3] Port Buffer 3 */ + __IOM uint8_t PB4 : 1; /*!< [4..4] Port Buffer 4 */ + __IOM uint8_t PB5 : 1; /*!< [5..5] Port Buffer 5 */ + __IOM uint8_t PB6 : 1; /*!< [6..6] Port Buffer 6 */ + __IOM uint8_t PB7 : 1; /*!< [7..7] Port Buffer 7 */ + } BY_b; + }; + __IM uint8_t RESERVED[3]; +} R_PORT_NSR_ELC_PDBF_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_ETHSW_PTP_SWTM [SWTM] (Ethernet Switch Timer output pins 0-3 Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t EN; /*!< (@ 0x00000000) PTP Timer Pulse Output Enable n Register */ + + struct + { + __IOM uint32_t OUTEN : 1; /*!< [0..0] Enable ETHSW_PTPOUTn Signal Output */ + uint32_t : 31; + } EN_b; + }; + + union + { + __IOM uint32_t STSEC; /*!< (@ 0x00000004) PTP Timer Pulse Start Second n Register */ + + struct + { + __IOM uint32_t STSEC : 32; /*!< [31..0] STSEC */ + } STSEC_b; + }; + + union + { + __IOM uint32_t STNS; /*!< (@ 0x00000008) PTP Timer Pulse Start Nanosecond n Register */ + + struct + { + __IOM uint32_t STNS : 32; /*!< [31..0] Start Time by Nanosecond */ + } STNS_b; + }; + + union + { + __IOM uint32_t PSEC; /*!< (@ 0x0000000C) PTP Timer Pulse Period Second n Register */ + + struct + { + __IOM uint32_t PSEC : 32; /*!< [31..0] PSEC */ + } PSEC_b; + }; + + union + { + __IOM uint32_t PNS; /*!< (@ 0x00000010) PTP Timer Pulse Period Nanosecond n Register */ + + struct + { + __IOM uint32_t PNS : 32; /*!< [31..0] Period by Nanosecond */ + } PNS_b; + }; + + union + { + __IOM uint32_t WTH; /*!< (@ 0x00000014) PTP Timer Pulse Width n Register */ + + struct + { + __IOM uint32_t WIDTH : 16; /*!< [15..0] Set the Pulse Width of ETHSW_PTPOUTn in the cycle number + * of ts_clk (8 ns). */ + uint32_t : 16; + } WTH_b; + }; + + union + { + __IOM uint32_t MAXP; /*!< (@ 0x00000018) PTP Timer Pulse Max Second n Register */ + + struct + { + __IOM uint32_t MAXP : 32; /*!< [31..0] Sets the boundary value in nanoseconds to carry from + * the nanosecond field to the second field. The same value + * as ATIME_EVT_PERIOD register must be set. */ + } MAXP_b; + }; + + union + { + __IOM uint32_t LATSEC; /*!< (@ 0x0000001C) PTP Timer Pulse Latch Second n Register */ + + struct + { + __IOM uint32_t LATSEC : 32; /*!< [31..0] LATSEC */ + } LATSEC_b; + }; + + union + { + __IOM uint32_t LATNS; /*!< (@ 0x00000020) PTP Timer Pulse Latch Nanosecond n Register */ + + struct + { + __IOM uint32_t LATNS : 32; /*!< [31..0] LATNS */ + } LATNS_b; + }; + __IM uint32_t RESERVED[55]; +} R_ETHSW_PTP_SWTM_Type; /*!< Size = 256 (0x100) */ + +/** + * @brief R_ETHSW_MGMT_ADDR [MGMT_ADDR] (MAC Address [0..3] for Bridge Protocol Frame Register) + */ +typedef struct +{ + union + { + __IOM uint32_t lo; /*!< (@ 0x00000000) Lower MAC Address */ + + struct + { + __IOM uint32_t BPDU_DST : 32; /*!< [31..0] Additional MAC address defining a Bridge Protocol Frame + * (BPDU) in addition to the commonly-known addresses */ + } lo_b; + }; + + union + { + __IOM uint32_t hi; /*!< (@ 0x00000004) Higher MAC Address */ + + struct + { + __IOM uint32_t BPDU_DST : 16; /*!< [15..0] Bits [7:0] is 5th byte, bits [15:8] is 6th (last) byte */ + __IOM uint32_t MASK : 8; /*!< [23..16] 8-bit mask for comparing the last byte of the MAC address. */ + uint32_t : 8; + } hi_b; + }; +} R_ETHSW_MGMT_ADDR_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_ESC_FMMU [FMMU] (FMMU [0..7] Registers (n = 0 to 7)) + */ +typedef struct +{ + union + { + __IM uint32_t L_START_ADR; /*!< (@ 0x00000000) FMMU Logical Start Address n Register (n = 0 + * to 7) */ + + struct + { + __IM uint32_t LSTAADR : 32; /*!< [31..0] Logical Start Address Setting */ + } L_START_ADR_b; + }; + + union + { + __IM uint16_t LEN; /*!< (@ 0x00000004) FMMU Length n Register (n = 0 to 7) */ + + struct + { + __IM uint16_t FMMULEN : 16; /*!< [15..0] Area Size Specification */ + } LEN_b; + }; + + union + { + __IM uint8_t L_START_BIT; /*!< (@ 0x00000006) FMMU Logical Start Bit n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t LSTABIT : 3; /*!< [2..0] Start Bit Setting */ + uint8_t : 5; + } L_START_BIT_b; + }; + + union + { + __IM uint8_t L_STOP_BIT; /*!< (@ 0x00000007) FMMU Logical Stop Bit n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t LSTPBIT : 3; /*!< [2..0] Last Bit Setting */ + uint8_t : 5; + } L_STOP_BIT_b; + }; + + union + { + __IM uint16_t P_START_ADR; /*!< (@ 0x00000008) FMMU Physical Start Address n Register (n = 0 + * to 7) */ + + struct + { + __IM uint16_t PHYSTAADR : 16; /*!< [15..0] Physical Start Address Setting */ + } P_START_ADR_b; + }; + + union + { + __IM uint8_t P_START_BIT; /*!< (@ 0x0000000A) FMMU Physical Start Bit n Register (n = 0 to + * 7) */ + + struct + { + __IM uint8_t PHYSTABIT : 3; /*!< [2..0] Physical Start Bit Setting */ + uint8_t : 5; + } P_START_BIT_b; + }; + + union + { + __IM uint8_t TYPE; /*!< (@ 0x0000000B) FMMU Type n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t READ : 1; /*!< [0..0] Read Access Mapping Setting */ + __IM uint8_t WRITE : 1; /*!< [1..1] Write Access Mapping Setting */ + uint8_t : 6; + } TYPE_b; + }; + + union + { + __IM uint8_t ACT; /*!< (@ 0x0000000C) FMMU Activate n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t ACTIVATE : 1; /*!< [0..0] FMMU Enable/Disable */ + uint8_t : 7; + } ACT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; +} R_ESC_FMMU_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ESC_SM [SM] (SyncManager [0..7] Registers (n = 0 to 7)) + */ +typedef struct +{ + union + { + __IM uint16_t P_START_ADR; /*!< (@ 0x00000000) SyncManager Physical Start Address n Register + * (n = 0 to 7) */ + + struct + { + __IM uint16_t SMSTAADDR : 16; /*!< [15..0] Physical Start Address Setting */ + } P_START_ADR_b; + }; + + union + { + __IM uint16_t LEN; /*!< (@ 0x00000002) SyncManager Length n Register (n = 0 to 7) */ + + struct + { + __IM uint16_t SMLEN : 16; /*!< [15..0] Area Size Setting */ + } LEN_b; + }; + + union + { + __IM uint8_t CONTROL; /*!< (@ 0x00000004) SyncManager Control n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t OPEMODE : 2; /*!< [1..0] Operating Mode Setting */ + __IM uint8_t DIR : 2; /*!< [3..2] Transfer Direction Setting */ + __IM uint8_t IRQECAT : 1; /*!< [4..4] ECAT Event Interrupt Setting */ + __IM uint8_t IRQPDI : 1; /*!< [5..5] AL Event Interrupt Setting */ + __IM uint8_t WDTRGEN : 1; /*!< [6..6] Watchdog Trigger Setting */ + uint8_t : 1; + } CONTROL_b; + }; + + union + { + __IM uint8_t STATUS; /*!< (@ 0x00000005) SyncManager Status n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t INTWR : 1; /*!< [0..0] Write Complete Interrupt State Indication */ + __IM uint8_t INTRD : 1; /*!< [1..1] Read Complete Interrupt State Indication */ + uint8_t : 1; + __IM uint8_t MAILBOX : 1; /*!< [3..3] Mailbox Status Indication */ + __IM uint8_t BUFFERED : 2; /*!< [5..4] Buffer Status Indication */ + __IM uint8_t RDBUF : 1; /*!< [6..6] Read State Indication */ + __IM uint8_t WRBUF : 1; /*!< [7..7] Write State Indication */ + } STATUS_b; + }; + + union + { + __IM uint8_t ACT; /*!< (@ 0x00000006) SyncManager Activate n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t SMEN : 1; /*!< [0..0] SyncManager Enable/Disable */ + __IM uint8_t REPEATREQ : 1; /*!< [1..1] Repeat Request */ + uint8_t : 4; + __IM uint8_t LATCHECAT : 1; /*!< [6..6] ECAT Latch Event Specification */ + __IM uint8_t LATCHPDI : 1; /*!< [7..7] PDI Latch Event Specification */ + } ACT_b; + }; + + union + { + __IOM uint8_t PDI_CONT; /*!< (@ 0x00000007) SyncManager PDI Control n Register (n = 0 to + * 7) */ + + struct + { + __IOM uint8_t DEACTIVE : 1; /*!< [0..0] SyncManager Operation Indication/Setting */ + __IOM uint8_t REPEATACK : 1; /*!< [1..1] Repeat Acknowledge */ + uint8_t : 6; + } PDI_CONT_b; + }; +} R_ESC_SM_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_USBF_PIPE_TR [PIPE_TR] (PIPEn Transaction Counter Registers (n=1-5)) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPEn Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) PIPEn Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USBF_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USBF_CHa_N [N] (Address Registers n (n=0-1)) + */ +typedef struct +{ + union + { + __IOM uint32_t SA; /*!< (@ 0x00000000) Next Source Address Register */ + + struct + { + __IOM uint32_t SAWD : 32; /*!< [31..0] Source Address or Write Data */ + } SA_b; + }; + + union + { + __IOM uint32_t DA; /*!< (@ 0x00000004) Next Destination Address Register */ + + struct + { + __IOM uint32_t DA : 32; /*!< [31..0] Destination Address */ + } DA_b; + }; + + union + { + __IOM uint32_t TB; /*!< (@ 0x00000008) Next Transaction Byte Register */ + + struct + { + __IOM uint32_t TB : 32; /*!< [31..0] Transaction Byte */ + } TB_b; + }; +} R_USBF_CHa_N_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_USBF_CHa [CHa] (Next Register Set) + */ +typedef struct +{ + __IOM R_USBF_CHa_N_Type N[2]; /*!< (@ 0x00000000) Address Registers n (n=0-1) */ + + union + { + __IM uint32_t CRSA; /*!< (@ 0x00000018) Current Source Address Register */ + + struct + { + __IM uint32_t CRSA : 32; /*!< [31..0] Source Address */ + } CRSA_b; + }; + + union + { + __IM uint32_t CRDA; /*!< (@ 0x0000001C) Current Destination Address Register */ + + struct + { + __IM uint32_t CRDA : 32; /*!< [31..0] Destination Address */ + } CRDA_b; + }; + + union + { + __IM uint32_t CRTB; /*!< (@ 0x00000020) Current Transaction Byte Register */ + + struct + { + __IM uint32_t CRTB : 32; /*!< [31..0] Transaction Byte */ + } CRTB_b; + }; + + union + { + __IM uint32_t CHSTAT; /*!< (@ 0x00000024) Channel Status Register */ + + struct + { + __IM uint32_t EN : 1; /*!< [0..0] Enable */ + __IM uint32_t RQST : 1; /*!< [1..1] Request */ + __IM uint32_t TACT : 1; /*!< [2..2] Transaction Active */ + __IM uint32_t SUS : 1; /*!< [3..3] Suspend */ + __IM uint32_t ER : 1; /*!< [4..4] Error */ + __IM uint32_t END : 1; /*!< [5..5] USB_FDMAn Interrupted */ + __IM uint32_t TC : 1; /*!< [6..6] Terminal Count */ + __IM uint32_t SR : 1; /*!< [7..7] Selected Register Set */ + __IM uint32_t DL : 1; /*!< [8..8] Descriptor Load */ + __IM uint32_t DW : 1; /*!< [9..9] Descriptor WriteBack */ + __IM uint32_t DER : 1; /*!< [10..10] Descriptor Error */ + __IM uint32_t MODE : 1; /*!< [11..11] DMA Mode */ + uint32_t : 4; + __IM uint32_t INTM : 1; /*!< [16..16] Interrupt Mask */ + __IM uint32_t DMARQM : 1; /*!< [17..17] DMAREQ Mask */ + __IM uint32_t SWPRQ : 1; /*!< [18..18] Sweep Request */ + uint32_t : 5; + __IM uint32_t DNUM : 8; /*!< [31..24] Data Number */ + } CHSTAT_b; + }; + + union + { + __OM uint32_t CHCTRL; /*!< (@ 0x00000028) Channel Control Register */ + + struct + { + __OM uint32_t SETEN : 1; /*!< [0..0] Set Enable */ + __OM uint32_t CLREN : 1; /*!< [1..1] Clear Enable */ + __OM uint32_t STG : 1; /*!< [2..2] Software Trigger */ + __OM uint32_t SWRST : 1; /*!< [3..3] Software Reset */ + __OM uint32_t CLRRQ : 1; /*!< [4..4] Clear Request */ + __OM uint32_t CLREND : 1; /*!< [5..5] Clear End */ + __OM uint32_t CLRTC : 1; /*!< [6..6] Clear TC */ + __OM uint32_t CLRDER : 1; /*!< [7..7] Clear DER */ + __OM uint32_t SETSUS : 1; /*!< [8..8] Set Suspend */ + __OM uint32_t CLRSUS : 1; /*!< [9..9] Clear Suspend */ + uint32_t : 2; + __OM uint32_t SETREN : 1; /*!< [12..12] Set Register Set Enable */ + uint32_t : 1; + __OM uint32_t SETSSWPRQ : 1; /*!< [14..14] Set Software Sweep Request */ + uint32_t : 1; + __OM uint32_t SETINTM : 1; /*!< [16..16] Set Interrupt Mask */ + __OM uint32_t CLRINTM : 1; /*!< [17..17] Clear Interrupt Mask */ + __OM uint32_t SETDMARQM : 1; /*!< [18..18] SET DMAREQ Mask */ + __OM uint32_t CLRDMARQM : 1; /*!< [19..19] Clear DMAREQ Mask */ + uint32_t : 12; + } CHCTRL_b; + }; + + union + { + __IOM uint32_t CHCFG; /*!< (@ 0x0000002C) Channel Configuration Register */ + + struct + { + __IOM uint32_t SEL : 1; /*!< [0..0] Terminal Select */ + uint32_t : 2; + __IOM uint32_t REQD : 1; /*!< [3..3] Request Direction */ + __IOM uint32_t LOEN : 1; /*!< [4..4] Sets the transfer request signal between the USB control + * and the DMAC. */ + __IOM uint32_t HIEN : 1; /*!< [5..5] Sets the transfer request signal between the USB control + * and the DMAC. */ + __IOM uint32_t LVL : 1; /*!< [6..6] Sets the transfer request signal between the USB control + * and the DMAC. */ + uint32_t : 1; + __IOM uint32_t AM : 3; /*!< [10..8] These bits set the transfer request signal between the + * USB control and the DMAC. */ + __IOM uint32_t DRRP : 1; /*!< [11..11] Descriptor Read Repeat */ + __IOM uint32_t SDS : 4; /*!< [15..12] Source Data Size */ + __IOM uint32_t DDS : 4; /*!< [19..16] Destination Data Size */ + __IOM uint32_t SAD : 1; /*!< [20..20] Source Address Direction */ + __IOM uint32_t DAD : 1; /*!< [21..21] Destination Address Direction */ + __IOM uint32_t TM : 1; /*!< [22..22] Sets the transfer request signal between the USB control + * and the DMAC. */ + __IOM uint32_t WONLY : 1; /*!< [23..23] Write Only Mode */ + __IOM uint32_t DEM : 1; /*!< [24..24] USB_FDMAn Mask */ + uint32_t : 1; + __IOM uint32_t DIM : 1; /*!< [26..26] Descriptor Interrupt Mask */ + __IOM uint32_t SBE : 1; /*!< [27..27] Sweep Buffer Enable */ + __IOM uint32_t RSEL : 1; /*!< [28..28] Register Set Select */ + __IOM uint32_t RSW : 1; /*!< [29..29] Register Select Switch */ + __IOM uint32_t REN : 1; /*!< [30..30] Register Set Enable */ + __IOM uint32_t DMS : 1; /*!< [31..31] DMA Mode Select */ + } CHCFG_b; + }; + + union + { + __IOM uint32_t CHITVL; /*!< (@ 0x00000030) Channel Interval Register */ + + struct + { + __IOM uint32_t ITVL : 16; /*!< [15..0] Interval */ + uint32_t : 16; + } CHITVL_b; + }; + + union + { + __IOM uint32_t CHEXT; /*!< (@ 0x00000034) Channel Extension Register */ + + struct + { + __IOM uint32_t SPR : 4; /*!< [3..0] Source PROT */ + uint32_t : 4; + __IOM uint32_t DPR : 4; /*!< [11..8] Destination PROT */ + uint32_t : 20; + } CHEXT_b; + }; + + union + { + __IOM uint32_t NXLA; /*!< (@ 0x00000038) Next Link Address Register */ + + struct + { + __IOM uint32_t NXLA : 32; /*!< [31..0] Next Link Address */ + } NXLA_b; + }; + + union + { + __IM uint32_t CRLA; /*!< (@ 0x0000003C) Current Link Address Register */ + + struct + { + __IM uint32_t CRLA : 32; /*!< [31..0] Current Link Address */ + } CRLA_b; + }; +} R_USBF_CHa_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_USBF_CHb [CHb] (Skip Register Set) + */ +typedef struct +{ + union + { + __IOM uint32_t SCNT; /*!< (@ 0x00000000) Source Continuous Register */ + + struct + { + __IOM uint32_t SCNT : 32; /*!< [31..0] Source Continuous */ + } SCNT_b; + }; + + union + { + __IOM uint32_t SSKP; /*!< (@ 0x00000004) Source Skip Register */ + + struct + { + __IOM uint32_t SSKP : 32; /*!< [31..0] Source Skip */ + } SSKP_b; + }; + + union + { + __IOM uint32_t DCNT; /*!< (@ 0x00000008) Destination Continuous Register */ + + struct + { + __IOM uint32_t DCNT : 32; /*!< [31..0] Destination Continuous */ + } DCNT_b; + }; + + union + { + __IOM uint32_t DSKP; /*!< (@ 0x0000000C) Destination Skip Register */ + + struct + { + __IOM uint32_t DSKP : 32; /*!< [31..0] Destination Skip */ + } DSKP_b; + }; + __IM uint32_t RESERVED[4]; +} R_USBF_CHb_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_XSPI0_CSa [CSa] (xSPI Command Map Configuration Register [0..1]) + */ +typedef struct +{ + union + { + __IOM uint32_t CMCFG0; /*!< (@ 0x00000000) xSPI Command Map Configuration Register 0 CSn */ + + struct + { + __IOM uint32_t FFMT : 2; /*!< [1..0] Frame format */ + __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size */ + uint32_t : 12; + __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable */ + __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code */ + } CMCFG0_b; + }; + + union + { + __IOM uint32_t CMCFG1; /*!< (@ 0x00000004) xSPI Command Map Configuration Register 1 CSn */ + + struct + { + __IOM uint32_t RDCMD : 16; /*!< [15..0] Read command */ + __IOM uint32_t RDLATE : 5; /*!< [20..16] Read latency cycle */ + uint32_t : 11; + } CMCFG1_b; + }; + + union + { + __IOM uint32_t CMCFG2; /*!< (@ 0x00000008) xSPI Command Map Configuration Register 2 CSn */ + + struct + { + __IOM uint32_t WRCMD : 16; /*!< [15..0] Write command */ + __IOM uint32_t WRLATE : 5; /*!< [20..16] Write latency cycle */ + uint32_t : 11; + } CMCFG2_b; + }; + __IM uint32_t RESERVED; +} R_XSPI0_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_BUF [BUF] (xSPI Command Manual Buf [0..3]) + */ +typedef struct +{ + union + { + __IOM uint32_t CDT; /*!< (@ 0x00000000) xSPI Command Manual Type Buf */ + + struct + { + __IOM uint32_t CMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t ADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t DATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + __IOM uint32_t LATE : 5; /*!< [13..9] Latency cycle */ + uint32_t : 1; + __IOM uint32_t TRTYPE : 1; /*!< [15..15] Transaction Type */ + __IOM uint32_t CMD : 16; /*!< [31..16] Command (1-2 bytes) */ + } CDT_b; + }; + + union + { + __IOM uint32_t CDA; /*!< (@ 0x00000004) xSPI Command Manual Address Buf */ + + struct + { + __IOM uint32_t ADD : 32; /*!< [31..0] Address */ + } CDA_b; + }; + + union + { + __IOM uint32_t CDD0; /*!< (@ 0x00000008) xSPI Command Manual Data 0 Buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD0_b; + }; + + union + { + __IOM uint32_t CDD1; /*!< (@ 0x0000000C) xSPI Command Manual Data 1 Buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD1_b; + }; +} R_XSPI0_BUF_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_CSb [CSb] (xSPI Command Calibration Control register [0..1]) + */ +typedef struct +{ + union + { + __IOM uint32_t CCCTL0; /*!< (@ 0x00000000) xSPI Command Calibration Control Register 0 CSn */ + + struct + { + __IOM uint32_t CAEN : 1; /*!< [0..0] Automatic Calibration Enable */ + __IOM uint32_t CANOWR : 1; /*!< [1..1] Calibration no write mode */ + uint32_t : 6; + __IOM uint32_t CAITV : 5; /*!< [12..8] Calibration interval */ + uint32_t : 3; + __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value */ + uint32_t : 3; + __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value */ + uint32_t : 3; + } CCCTL0_b; + }; + + union + { + __IOM uint32_t CCCTL1; /*!< (@ 0x00000004) xSPI Command Calibration Control Register 1 CSn */ + + struct + { + __IOM uint32_t CACMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t CAADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + uint32_t : 7; + __IOM uint32_t CAWRLATE : 5; /*!< [20..16] Write Latency cycle */ + uint32_t : 3; + __IOM uint32_t CARDLATE : 5; /*!< [28..24] Read Latency cycle */ + uint32_t : 3; + } CCCTL1_b; + }; + + union + { + __IOM uint32_t CCCTL2; /*!< (@ 0x00000008) xSPI Command Calibration Control Register 2 CSn */ + + struct + { + __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command */ + __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command */ + } CCCTL2_b; + }; + + union + { + __IOM uint32_t CCCTL3; /*!< (@ 0x0000000C) xSPI Command Calibration Control Register 3 CSn */ + + struct + { + __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address */ + } CCCTL3_b; + }; + + union + { + __IOM uint32_t CCCTL4; /*!< (@ 0x00000010) xSPI Command Calibration Control Register 4 CSn */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL4_b; + }; + + union + { + __IOM uint32_t CCCTL5; /*!< (@ 0x00000014) xSPI Command Calibration Control Register 5 CSn */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL5_b; + }; + + union + { + __IOM uint32_t CCCTL6; /*!< (@ 0x00000018) xSPI Command Calibration Control Register 6 CSn */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL6_b; + }; + + union + { + __IOM uint32_t CCCTL7; /*!< (@ 0x0000001C) xSPI Command Calibration Control Register 7 CSn */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL7_b; + }; +} R_XSPI0_CSb_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_SYSRAM0_W [W] (System SRAM Wn Registers (n = 0 to 3)) + */ +typedef struct +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Indicate Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] 1-Bit ECC Error Detection/Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-Bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] 1-Bit ECC Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] 2-Bit ECC Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] 1-Bit ECC Error Correction Enable */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Determination Enable */ + __IOM uint32_t ECTHM : 1; /*!< [7..7] ECC Function Through Mode Enable */ + uint32_t : 1; + __IOM uint32_t ECER1C : 1; /*!< [9..9] 1-Bit ECC Error Detection Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-Bit ECC Error Detection Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Error Address Capture Overflow Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Selection */ + __IM uint32_t ECEDF0 : 2; /*!< [17..16] ECC Error Address Capture Flag m (m = 0) */ + __IM uint32_t ECEDF1 : 2; /*!< [19..18] ECC Error Address Capture Flag m (m = 1) */ + __IM uint32_t ECEDF2 : 2; /*!< [21..20] ECC Error Address Capture Flag m (m = 2) */ + __IM uint32_t ECEDF3 : 2; /*!< [23..22] ECC Error Address Capture Flag m (m = 3) */ + __IM uint32_t ECEDF4 : 2; /*!< [25..24] ECC Error Address Capture Flag m (m = 4) */ + __IM uint32_t ECEDF5 : 2; /*!< [27..26] ECC Error Address Capture Flag m (m = 5) */ + __IM uint32_t ECEDF6 : 2; /*!< [29..28] ECC Error Address Capture Flag m (m = 6) */ + __IM uint32_t ECEDF7 : 2; /*!< [31..30] ECC Error Address Capture Flag m (m = 7) */ + } EC710CTL_b; + }; + + union + { + __IOM uint32_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + __IOM uint32_t ECREIS : 1; /*!< [0..0] ECC Redundancy Bit Input Data Select */ + __IOM uint32_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + __IOM uint32_t ECENS : 1; /*!< [2..2] ECC Encode Input Select */ + __IOM uint32_t ECREOS : 1; /*!< [3..3] ECC Redundancy Bit Output Data Select */ + __IOM uint32_t ECTRRS : 1; /*!< [4..4] RAM Read Test Mode Select */ + uint32_t : 2; + __IOM uint32_t ECTMCE : 1; /*!< [7..7] Test Mode Enable */ + uint32_t : 6; + __IOM uint32_t ETMA : 2; /*!< [15..14] ECTMCE Write Enable */ + uint32_t : 16; + } EC710TMC_b; + }; + + union + { + __IOM uint32_t EC710TRC; /*!< (@ 0x00000008) ECC Redundancy Bit Data Control Test Register */ + + struct + { + __IOM uint32_t ECERDB : 7; /*!< [6..0] ECC Redundancy Bit Input/Output Substitute Buffer Register */ + uint32_t : 1; + __IM uint32_t ECECRD : 7; /*!< [14..8] ECC Encode Test Register */ + uint32_t : 1; + __IM uint32_t ECHORD : 7; /*!< [22..16] ECC 7-Redundancy-Bit Data Retain Test Register */ + uint32_t : 1; + __IM uint32_t ECSYND : 7; /*!< [30..24] ECC Decode Syndrome Register */ + uint32_t : 1; + } EC710TRC_b; + }; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Encode/Decode Input/Output Switchover Test + * Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] 32-Bit Data Test Register for ECC Encode/Decode */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD[8]; /*!< (@ 0x00000010) ECC Error Address [0..7] Register 0 */ + + struct + { + __IM uint32_t ECEAD : 15; /*!< [14..0] Bit Error Address */ + uint32_t : 17; + } EC710EAD_b[8]; + }; + __IM uint32_t RESERVED[4]; +} R_SYSRAM0_W_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_MPU0_RGN [RGN] (Master MPU Safety Region Start Address Register [0..7]) + */ +typedef struct +{ + union + { + __IOM uint32_t STADD; /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register */ + + struct + { + __IOM uint32_t RDPR : 1; /*!< [0..0] Enable read protection for region m of master MPU */ + __IOM uint32_t WRPR : 1; /*!< [1..1] Enable write protection for region m of master MPU */ + uint32_t : 8; + __IOM uint32_t STADDR : 22; /*!< [31..10] Start address for MPU region */ + } STADD_b; + }; + + union + { + __IOM uint32_t ENDADD; /*!< (@ 0x00000004) Master MPU Safety Region End Address Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t ENDADDR : 22; /*!< [31..10] End address for MPU region */ + } ENDADD_b; + }; + __IM uint32_t RESERVED[2]; +} R_MPU0_RGN_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_DSMIF0_CH [CH] (Channel Registers [0..2]) + */ +typedef struct +{ + union + { + __IOM uint32_t DSICR; /*!< (@ 0x00000000) Interrupt Control Register */ + + struct + { + __IOM uint32_t IOEL : 1; /*!< [0..0] Overcurrent lower limit detection interrupt enable */ + __IOM uint32_t IOEH : 1; /*!< [1..1] Overcurrent upper limit exceeded output interrupt enable */ + __IOM uint32_t ISE : 1; /*!< [2..2] Short circuit detection error interrupt enable */ + __IOM uint32_t IUE : 1; /*!< [3..3] Current data register update interrupt enable */ + uint32_t : 28; + } DSICR_b; + }; + + union + { + __IOM uint32_t DSCMCCR; /*!< (@ 0x00000004) Current Measurement Clock Control Register */ + + struct + { + __IOM uint32_t CKDIR : 1; /*!< [0..0] A/D conversion clock master/slave switching */ + uint32_t : 6; + __IOM uint32_t SEDGE : 1; /*!< [7..7] Sampling edge selection */ + __IOM uint32_t CKDIV : 6; /*!< [13..8] A/D conversion clock division ratio */ + uint32_t : 18; + } DSCMCCR_b; + }; + + union + { + __IOM uint32_t DSCMFCR; /*!< (@ 0x00000008) Current Measurement Filter Control Register */ + + struct + { + __IOM uint32_t CMSINC : 2; /*!< [1..0] Current measurement filter order setting */ + uint32_t : 6; + __IOM uint32_t CMDEC : 8; /*!< [15..8] Decimation ratio selection for current measurement */ + __IOM uint32_t CMSH : 5; /*!< [20..16] Data shift setting for current measurement */ + uint32_t : 11; + } DSCMFCR_b; + }; + + union + { + __IOM uint32_t DSCMCTCR; /*!< (@ 0x0000000C) Current Measurement Capture Trigger Control Register */ + + struct + { + __IOM uint32_t CTSELA : 3; /*!< [2..0] Current capture trigger A selection bit */ + uint32_t : 5; + __IOM uint32_t CTSELB : 3; /*!< [10..8] Current capture trigger B selection bit */ + uint32_t : 5; + __IOM uint32_t DITSEL : 2; /*!< [17..16] Current measurement filter initialization trigger selection + * bit for frequency division counter for decimation. */ + uint32_t : 5; + __IOM uint32_t DEDGE : 1; /*!< [23..23] Current measurement filter initialization trigger for + * division counter for decimation edge selection bit. The + * trigger from ELC is usually used positive edge. Change + * from the initial value if necessary. */ + uint32_t : 8; + } DSCMCTCR_b; + }; + + union + { + __IOM uint32_t DSEDCR; /*!< (@ 0x00000010) Error Detect Control Register */ + + struct + { + __IOM uint32_t SDE : 1; /*!< [0..0] Short circuit detection enable bit */ + uint32_t : 31; + } DSEDCR_b; + }; + + union + { + __IOM uint32_t DSOCFCR; /*!< (@ 0x00000014) Overcurrent Detect Filter Control Register */ + + struct + { + __IOM uint32_t OCSINC : 2; /*!< [1..0] Overcurrent detection filter order setting */ + uint32_t : 6; + __IOM uint32_t OCDEC : 8; /*!< [15..8] Decimation ratio selection for overcurrent detection */ + __IOM uint32_t OCSH : 5; /*!< [20..16] Data shift setting for overcurrent detection */ + uint32_t : 11; + } DSOCFCR_b; + }; + + union + { + __IOM uint32_t DSOCLTR; /*!< (@ 0x00000018) Overcurrent Low Threshold Register */ + + struct + { + __IOM uint32_t OCMPTBL : 16; /*!< [15..0] Overcurrent detection lower limit */ + uint32_t : 16; + } DSOCLTR_b; + }; + + union + { + __IOM uint32_t DSOCHTR; /*!< (@ 0x0000001C) Overcurrent High Threshold Register */ + + struct + { + __IOM uint32_t OCMPTBH : 16; /*!< [15..0] Overcurrent detection upper limit */ + uint32_t : 16; + } DSOCHTR_b; + }; + + union + { + __IOM uint32_t DSSCTSR; /*!< (@ 0x00000020) Short Circuit Threshold Setting Register */ + + struct + { + __IOM uint32_t SCNTL : 13; /*!< [12..0] Short circuit detection low continuous detection count */ + uint32_t : 3; + __IOM uint32_t SCNTH : 13; /*!< [28..16] Short circuit detection high continuous detection count */ + uint32_t : 3; + } DSSCTSR_b; + }; + + union + { + __IOM uint32_t DSODCR; /*!< (@ 0x00000024) Overcurrent Detect Control Register */ + + struct + { + __IOM uint32_t ODEL : 1; /*!< [0..0] Overcurrent lower limit detection enable bit */ + __IOM uint32_t ODEH : 1; /*!< [1..1] Overcurrent upper limit exceeded detection enable bit */ + uint32_t : 30; + } DSODCR_b; + }; + __IM uint32_t RESERVED[6]; + + union + { + __IOM uint32_t DSCSTRTR; /*!< (@ 0x00000040) Software Start Trigger Register */ + + struct + { + __IOM uint32_t STRTRG : 1; /*!< [0..0] Channel start trigger */ + uint32_t : 31; + } DSCSTRTR_b; + }; + + union + { + __IOM uint32_t DSCSTPTR; /*!< (@ 0x00000044) Software Stop Trigger Register */ + + struct + { + __IOM uint32_t STPTRG : 1; /*!< [0..0] Channel stop trigger */ + uint32_t : 31; + } DSCSTPTR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IM uint32_t DSCDR; /*!< (@ 0x00000050) Current Data Register */ + + struct + { + __IM uint32_t ADDR : 16; /*!< [15..0] Current data */ + uint32_t : 16; + } DSCDR_b; + }; + + union + { + __IM uint32_t DSCCDRA; /*!< (@ 0x00000054) Capture Current Data Register A */ + + struct + { + __IM uint32_t CDRA : 16; /*!< [15..0] Capture current data A */ + uint32_t : 16; + } DSCCDRA_b; + }; + + union + { + __IM uint32_t DSCCDRB; /*!< (@ 0x00000058) Capture Current Data Register B */ + + struct + { + __IM uint32_t CDRB : 16; /*!< [15..0] Capture current data B */ + uint32_t : 16; + } DSCCDRB_b; + }; + + union + { + __IM uint32_t DSOCDR; /*!< (@ 0x0000005C) Overcurrent Data Register */ + + struct + { + __IM uint32_t ODR : 16; /*!< [15..0] Overcurrent data */ + uint32_t : 16; + } DSOCDR_b; + }; + + union + { + __IM uint32_t DSCOCDR; /*!< (@ 0x00000060) Capture Overcurrent Data Register */ + + struct + { + __IM uint32_t CODR : 16; /*!< [15..0] Capture Overcurrent data when overcurrent detected */ + uint32_t : 16; + } DSCOCDR_b; + }; + __IM uint32_t RESERVED2[7]; + + union + { + __IM uint32_t DSCSR; /*!< (@ 0x00000080) Status Register */ + + struct + { + __IM uint32_t DUF : 1; /*!< [0..0] Channel n data update flag */ + __IM uint32_t OCFL : 1; /*!< [1..1] Channel n overcurrent lower limit detection flag */ + __IM uint32_t OCFH : 1; /*!< [2..2] Channel n overcurrent upper limit exceeded flag */ + __IM uint32_t SCF : 1; /*!< [3..3] Channel n short circuit detection flag */ + uint32_t : 12; + __IM uint32_t CHSTATE : 1; /*!< [16..16] Channel n state */ + uint32_t : 15; + } DSCSR_b; + }; + + union + { + __IOM uint32_t DSCSCR; /*!< (@ 0x00000084) Status Clear Register */ + + struct + { + __IOM uint32_t CLRDUF : 1; /*!< [0..0] Channel n data update flag clear */ + __IOM uint32_t CLROCFL : 1; /*!< [1..1] Channel n overcurrent lower limit detection flag clear */ + __IOM uint32_t CLROCFH : 1; /*!< [2..2] Channel n overcurrent upper limit exceeded flag clear */ + __IOM uint32_t CLRSCF : 1; /*!< [3..3] Channel n short circuit detection flag clear */ + uint32_t : 28; + } DSCSCR_b; + }; + __IM uint32_t RESERVED3[2]; +} R_DSMIF0_CH_Type; /*!< Size = 144 (0x90) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_GPT7 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer 7 (R_GPT7) + */ + +typedef struct /*!< (@ 0x80000000) R_GPT7 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disabled */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disabled */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disabled */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disabled */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel 0 Count Start */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel 1 Count Start */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel 2 Count Start */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel 3 Count Start */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel 4 Count Start */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel 5 Count Start */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel 6 Count Start */ + uint32_t : 25; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel 0 Count Stop */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel 1 Count Stop */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel 2 Count Stop */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel 3 Count Stop */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel 4 Count Stop */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel 5 Count Stop */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel 6 Count Stop */ + uint32_t : 25; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel 0 Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel 1 Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel 2 Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel 3 Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel 4 Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel 5 Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel 6 Count Clear */ + uint32_t : 25; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAFR : 2; /*!< [1..0] SSGTRGAFR */ + __IOM uint32_t SSGTRGBFR : 2; /*!< [3..2] SSGTRGBFR */ + __IOM uint32_t SSGTRGCFR : 2; /*!< [5..4] SSGTRGCFR */ + __IOM uint32_t SSGTRGDFR : 2; /*!< [7..6] SSGTRGDFR */ + __IOM uint32_t SSCARBHL : 2; /*!< [9..8] SSCARBHL */ + __IOM uint32_t SSCAFBHL : 2; /*!< [11..10] SSCAFBHL */ + __IOM uint32_t SSCBRAHL : 2; /*!< [13..12] SSCBRAHL */ + __IOM uint32_t SSCBFAHL : 2; /*!< [15..14] SSCBFAHL */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] SSELCA */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] SSELCB */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] SSELCC */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] SSELCD */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] SSELCE */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] SSELCF */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] SSELCG */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] SSELCH */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Count Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAFR : 2; /*!< [1..0] PSGTRGAFR */ + __IOM uint32_t PSGTRGBFR : 2; /*!< [3..2] PSGTRGBFR */ + __IOM uint32_t PSGTRGCFR : 2; /*!< [5..4] PSGTRGCFR */ + __IOM uint32_t PSGTRGDFR : 2; /*!< [7..6] PSGTRGDFR */ + __IOM uint32_t PSCARBHL : 2; /*!< [9..8] PSCARBHL */ + __IOM uint32_t PSCAFBHL : 2; /*!< [11..10] PSCAFBHL */ + __IOM uint32_t PSCBRAHL : 2; /*!< [13..12] PSCBRAHL */ + __IOM uint32_t PSCBFAHL : 2; /*!< [15..14] PSCBFAHL */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] PSELCA */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] PSELCB */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] PSELCC */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] PSELCD */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] PSELCE */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] PSELCF */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] PSELCG */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] PSELCH */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] CSTOP */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAFR : 2; /*!< [1..0] CSGTRGAFR */ + __IOM uint32_t CSGTRGBFR : 2; /*!< [3..2] CSGTRGBFR */ + __IOM uint32_t CSGTRGCFR : 2; /*!< [5..4] CSGTRGCFR */ + __IOM uint32_t CSGTRGDFR : 2; /*!< [7..6] CSGTRGDFR */ + __IOM uint32_t CSCARBHL : 2; /*!< [9..8] CSCARBHL */ + __IOM uint32_t CSCAFBHL : 2; /*!< [11..10] CSCAFBHL */ + __IOM uint32_t CSCBRAHL : 2; /*!< [13..12] CSCBRAHL */ + __IOM uint32_t CSCBFAHL : 2; /*!< [15..14] CSCBFAHL */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] CSELCA */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] CSELCB */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] CSELCC */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] CSELCD */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] CSELCE */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] CSELCF */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] CSELCG */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] CSELCH */ + uint32_t : 7; + __IOM uint32_t CCLR : 1; /*!< [31..31] CCLR */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Count-Up Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAFR : 2; /*!< [1..0] USGTRGAFR */ + __IOM uint32_t USGTRGBFR : 2; /*!< [3..2] USGTRGBFR */ + __IOM uint32_t USGTRGCFR : 2; /*!< [5..4] USGTRGCFR */ + __IOM uint32_t USGTRGDFR : 2; /*!< [7..6] USGTRGDFR */ + __IOM uint32_t USCARBHL : 2; /*!< [9..8] USCARBHL */ + __IOM uint32_t USCAFBHL : 2; /*!< [11..10] USCAFBHL */ + __IOM uint32_t USCBRAHL : 2; /*!< [13..12] USCBRAHL */ + __IOM uint32_t USCBFAHL : 2; /*!< [15..14] USCBFAHL */ + __IOM uint32_t USELCA : 1; /*!< [16..16] USELCA */ + __IOM uint32_t USELCB : 1; /*!< [17..17] USELCB */ + __IOM uint32_t USELCC : 1; /*!< [18..18] USELCC */ + __IOM uint32_t USELCD : 1; /*!< [19..19] USELCD */ + __IOM uint32_t USELCE : 1; /*!< [20..20] USELCE */ + __IOM uint32_t USELCF : 1; /*!< [21..21] USELCF */ + __IOM uint32_t USELCG : 1; /*!< [22..22] USELCG */ + __IOM uint32_t USELCH : 1; /*!< [23..23] USELCH */ + uint32_t : 8; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Count-Down Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAFR : 2; /*!< [1..0] DSGTRGAFR */ + __IOM uint32_t DSGTRGBFR : 2; /*!< [3..2] DSGTRGBFR */ + __IOM uint32_t DSGTRGCFR : 2; /*!< [5..4] DSGTRGCFR */ + __IOM uint32_t DSGTRGDFR : 2; /*!< [7..6] DSGTRGDFR */ + __IOM uint32_t DSCARBHL : 2; /*!< [9..8] DSCARBHL */ + __IOM uint32_t DSCAFBHL : 2; /*!< [11..10] DSCAFBHL */ + __IOM uint32_t DSCBRAHL : 2; /*!< [13..12] DSCBRAHL */ + __IOM uint32_t DSCBFAHL : 2; /*!< [15..14] DSCBFAHL */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] DSELCA */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] DSELCB */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] DSELCC */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] DSELCD */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] DSELCE */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] DSELCF */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] DSELCG */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] DSELCH */ + uint32_t : 8; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAFR : 2; /*!< [1..0] ASGTRGAFR */ + __IOM uint32_t ASGTRGBFR : 2; /*!< [3..2] ASGTRGBFR */ + __IOM uint32_t ASGTRGCFR : 2; /*!< [5..4] ASGTRGCFR */ + __IOM uint32_t ASGTRGDFR : 2; /*!< [7..6] ASGTRGDFR */ + __IOM uint32_t ASCARBHL : 2; /*!< [9..8] ASCARBHL */ + __IOM uint32_t ASCAFBHL : 2; /*!< [11..10] ASCAFBHL */ + __IOM uint32_t ASCBRAHL : 2; /*!< [13..12] ASCBRAHL */ + __IOM uint32_t ASCBFAHL : 2; /*!< [15..14] ASCBFAHL */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ASELCA */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ASELCB */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ASELCC */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ASELCD */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ASELCE */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ASELCF */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ASELCG */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ASELCH */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAFR : 2; /*!< [1..0] BSGTRGAFR */ + __IOM uint32_t BSGTRGBFR : 2; /*!< [3..2] BSGTRGBFR */ + __IOM uint32_t BSGTRGCFR : 2; /*!< [5..4] BSGTRGCFR */ + __IOM uint32_t BSGTRGDFR : 2; /*!< [7..6] BSGTRGDFR */ + __IOM uint32_t BSCARBHL : 2; /*!< [9..8] BSCARBHL */ + __IOM uint32_t BSCAFBHL : 2; /*!< [11..10] BSCAFBHL */ + __IOM uint32_t BSCBRAHL : 2; /*!< [13..12] BSCBRAHL */ + __IOM uint32_t BSCBFAHL : 2; /*!< [15..14] BSCBFAHL */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] BSELCA */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] BSELCB */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] BSELCC */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] BSELCD */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] BSELCE */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] BSELCF */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] BSELCG */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] BSELCH */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 7; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select at Count Stop */ + uint32_t : 7; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 2; + __IOM uint32_t SWMD : 3; /*!< [31..29] Switch Mode Select */ + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCnA Pin Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] GTIOCnA Pin Output Duty Forced Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] Output after Release of GTIOCnA Pin Output 0%/100% + * Duty Cycle Settings */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCnB Pin Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] GTIOCnB Pin Output Duty Forced Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] Output after Release of GTIOCnB Pin Output 0%/100% + * Duty Cycle Settings */ + __IOM uint32_t OABDTYT : 1; /*!< [28..28] Setting this bit to 1 is prohibited except in triangle-wave + * mode. */ + uint32_t : 3; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCnA Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCnA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCnA Pin Output Retention at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCnA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCnA Pin Negate Value Setting */ + uint32_t : 2; + __IOM uint32_t NFAEN : 1; /*!< [13..13] GTIOCnA Pin Input Noise Filter Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] GTIOCnA Pin Input Noise Filter Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCnB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCnB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCnB Pin Output Retention at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCnB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCnB Pin Negate Value Setting */ + uint32_t : 2; + __IOM uint32_t NFBEN : 1; /*!< [29..29] GTIOCnB Pin Input Noise Filter Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] GTIOCnB Pin Input Noise Filter Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTINTA */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTINTB */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTINTC */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTINTD */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTINTE */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTINTF */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTINTPR */ + uint32_t : 8; + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] ADTRAUEN */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] ADTRADEN */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] ADTRBUEN */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] ADTRBDEN */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Select the group to detect disabling of output (dead-time + * error or simultaneous driving of outputs to the high or + * low level) to POEG and to request of disabling of output + * from POEG. */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] GRPDTE */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] (GTIOCnA pin and GTIOCnB output) */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] (GTIOCnA pin and GTIOCnB output) */ + uint32_t : 1; + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + uint32_t : 8; + __IM uint32_t ITCNT : 3; /*!< [10..8] GPTn_OVF/GPTn_UDF Interrupt Skipping Count Counter */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Register Compare Match (Up-Counting) A/D Converter + * Start Request Flag */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Register Compare Match (Down-Counting) A/D + * Converter Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Register Compare Match (Up-Counting) A/D Converter + * Start Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Register Compare Match (Down-Counting) A/D + * Converter Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Stop Request Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Simultaneous High Output Flag */ + __IM uint32_t OABLF : 1; /*!< [30..30] Simultaneous Low Output Flag */ + uint32_t : 1; + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] GTCCRA/GTCCRB Registers Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] GTPR Register Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] GTADTRA/GTADTRB Registers Buffer Operation Disable */ + __IOM uint32_t BD3 : 1; /*!< [3..3] GTDVU/GTDVD Registers Buffer Operation Disable */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRA Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRB Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Register Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Register Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Register Buffer Operation */ + __IOM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Registers Forcible Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Register Buffer Transfer Timing Select */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Register Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Register Buffer Transfer Timing Select */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Register Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] ITLA */ + __IOM uint32_t ITLB : 1; /*!< [1..1] ITLB */ + __IOM uint32_t ITLC : 1; /*!< [2..2] ITLC */ + __IOM uint32_t ITLD : 1; /*!< [3..3] ITLD */ + __IOM uint32_t ITLE : 1; /*!< [4..4] ITLE */ + __IOM uint32_t ITLF : 1; /*!< [5..5] ITLF */ + __IOM uint32_t IVTC : 2; /*!< [7..6] IVTC */ + __IOM uint32_t IVTT : 3; /*!< [10..8] IVTT */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] ADTAL */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] ADTBL */ + uint32_t : 17; + } GTITC_b; + }; + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register m + * (m = A,B,C,E,D,F) */ + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A + * (m = A, B) */ + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A (m = A, B) */ + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B + * (m = A, B) */ + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B (m = A, B) */ + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Register Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Register Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Register Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U + * (m = U, D) */ + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D + * (m = U, D) */ + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Value Buffer Register + * U (m = U, D) */ + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Value Buffer Register + * D (m = U, D) */ + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + + union + { + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ + + struct + { + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; + }; + + union + { + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ + + struct + { + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * Select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; + }; + + union + { + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ + + struct + { + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; + }; + + union + { + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ + + struct + { + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA A/D Converter Start Request Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB A/D Converter Start Request Extended Skipping + * Function Select */ + uint32_t : 25; + } GTEITLI2_b; + }; + + union + { + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ + + struct + { + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; + }; + __IM uint32_t RESERVED[6]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 25; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 20; + } GTSECR_b; + }; + + union + { + __IOM uint32_t GTSWSR; /*!< (@ 0x000000D8) General PWM Timer Switch Source Select Register */ + + struct + { + __IOM uint32_t WSGTRGA : 2; /*!< [1..0] GTETRGA Signal Edge Select to Switch Counter (GTETRGSA + * Signal for SAFTY) */ + __IOM uint32_t WSGTRGB : 2; /*!< [3..2] GTETRGB Signal Edge Select to Switch Counter (GTETRGSB + * Signal for SAFTY) */ + __IOM uint32_t WSGTRGC : 2; /*!< [5..4] GTETRGC Signal Edge Select to Switch Counter (GTETRGSC + * Signal for SAFTY) */ + __IOM uint32_t WSGTRGD : 2; /*!< [7..6] GTETRGD Signal Edge Select to Switch Counter (GTETRGSD + * Signal for SAFTY) */ + uint32_t : 8; + __IOM uint32_t WSELCA : 1; /*!< [16..16] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCB : 1; /*!< [17..17] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCC : 1; /*!< [18..18] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCD : 1; /*!< [19..19] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCE : 1; /*!< [20..20] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCF : 1; /*!< [21..21] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCG : 1; /*!< [22..22] Event Source Counter Switch Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] Event Source Counter Switch Enable */ + uint32_t : 8; + } GTSWSR_b; + }; + __IOM uint32_t GTSWOS; /*!< (@ 0x000000DC) General PWM Timer Switch Offset Setting Register */ +} R_GPT0_Type; /*!< Size = 224 (0xe0) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communication Interface 0 (R_SCI0) + */ + +typedef struct /*!< (@ 0x80001000) R_SCI0 Structure */ +{ + union + { + __IM uint32_t RDR; /*!< (@ 0x00000000) Receive Data Register */ + + struct + { + __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data */ + __IM uint32_t MPB : 1; /*!< [9..9] Multi-processor flag */ + __IM uint32_t DR : 1; /*!< [10..10] Receive data ready flag */ + __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag */ + __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag */ + uint32_t : 11; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag */ + uint32_t : 2; + __IM uint32_t PER : 1; /*!< [27..27] Parity error flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing error flag */ + uint32_t : 3; + } RDR_b; + }; + + union + { + __IOM uint32_t TDR; /*!< (@ 0x00000004) Transmit Data Register */ + + struct + { + __IOM uint32_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint32_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag */ + uint32_t : 22; + } TDR_b; + }; + + union + { + __IOM uint32_t CCR0; /*!< (@ 0x00000008) Common Control Register 0 */ + + struct + { + __IOM uint32_t RE : 1; /*!< [0..0] Receive Enable */ + uint32_t : 3; + __IOM uint32_t TE : 1; /*!< [4..4] Transmit Enable */ + uint32_t : 3; + __IOM uint32_t MPIE : 1; /*!< [8..8] Multi-Processor Interrupt Enable */ + __IOM uint32_t DCME : 1; /*!< [9..9] Data Compare Match Enable */ + __IOM uint32_t IDSEL : 1; /*!< [10..10] ID frame select */ + uint32_t : 5; + __IOM uint32_t RIE : 1; /*!< [16..16] Receive Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TIE : 1; /*!< [20..20] Transmit Interrupt Enable */ + __IOM uint32_t TEIE : 1; /*!< [21..21] Transmit End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SSE : 1; /*!< [24..24] SSn# Pin Function Enable */ + uint32_t : 7; + } CCR0_b; + }; + + union + { + __IOM uint32_t CCR1; /*!< (@ 0x0000000C) Common Control Register 1 */ + + struct + { + __IOM uint32_t CTSE : 1; /*!< [0..0] CTS Enable */ + __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable */ + uint32_t : 2; + __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select */ + __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O */ + uint32_t : 2; + __IOM uint32_t PE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t PM : 1; /*!< [9..9] Parity Mode */ + uint32_t : 2; + __IOM uint32_t TINV : 1; /*!< [12..12] TXD invert */ + __IOM uint32_t RINV : 1; /*!< [13..13] RXD invert */ + uint32_t : 2; + __IOM uint32_t SPLP : 1; /*!< [16..16] Loopback Control */ + uint32_t : 3; + __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select */ + uint32_t : 3; + __IOM uint32_t NFCS : 3; /*!< [26..24] Noise Filter Clock Select */ + uint32_t : 1; + __IOM uint32_t NFEN : 1; /*!< [28..28] Digital Noise Filter Function Enable */ + uint32_t : 3; + } CCR1_b; + }; + + union + { + __IOM uint32_t CCR2; /*!< (@ 0x00000010) Common Control Register 2 */ + + struct + { + __IOM uint32_t BCP : 3; /*!< [2..0] Base Clock Pulse */ + uint32_t : 1; + __IOM uint32_t BGDM : 1; /*!< [4..4] Baud Rate Generator Double-Speed Mode Select */ + __IOM uint32_t ABCS : 1; /*!< [5..5] Asynchronous Mode Base Clock Select */ + __IOM uint32_t ABCSE : 1; /*!< [6..6] Asynchronous Mode Extended Base Clock Select */ + uint32_t : 1; + __IOM uint32_t BRR : 8; /*!< [15..8] Bit rate setting */ + __IOM uint32_t BRME : 1; /*!< [16..16] BRME */ + uint32_t : 3; + __IOM uint32_t CKS : 2; /*!< [21..20] Clock Select */ + uint32_t : 2; + __IOM uint32_t MDDR : 8; /*!< [31..24] Modulation Duty setting */ + } CCR2_b; + }; + + union + { + __IOM uint32_t CCR3; /*!< (@ 0x00000014) Common Control Register 3 */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] Clock Phase Select */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock Polarity Select */ + uint32_t : 5; + __IOM uint32_t BPEN : 1; /*!< [7..7] Synchronizer bypass enable */ + __IOM uint32_t CHR : 2; /*!< [9..8] Character Length */ + uint32_t : 2; + __IOM uint32_t LSBF : 1; /*!< [12..12] LSB First select */ + __IOM uint32_t SINV : 1; /*!< [13..13] Transmitted/Received Data Invert */ + __IOM uint32_t STP : 1; /*!< [14..14] Stop Bit Length */ + __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select */ + __IOM uint32_t MOD : 3; /*!< [18..16] Communication mode select */ + __IOM uint32_t MP : 1; /*!< [19..19] Multi-Processor Mode */ + __IOM uint32_t FM : 1; /*!< [20..20] FIFO Mode select */ + __IOM uint32_t DEN : 1; /*!< [21..21] Driver enable */ + uint32_t : 2; + __IOM uint32_t CKE : 2; /*!< [25..24] Clock enable */ + uint32_t : 2; + __IOM uint32_t GM : 1; /*!< [28..28] GSM Mode */ + __IOM uint32_t BLK : 1; /*!< [29..29] Block Transfer Mode */ + uint32_t : 2; + } CCR3_b; + }; + + union + { + __IOM uint32_t CCR4; /*!< (@ 0x00000018) Common Control Register 4 */ + + struct + { + __IOM uint32_t CMPD : 9; /*!< [8..0] Compare Match Data */ + uint32_t : 7; + __IOM uint32_t ASEN : 1; /*!< [16..16] Adjust receive sampling timing enable */ + __IOM uint32_t ATEN : 1; /*!< [17..17] Adjust transmit timing enable */ + uint32_t : 6; + __IOM uint32_t AST : 3; /*!< [26..24] Adjustment value for receive Sampling Timing */ + __IOM uint32_t AJD : 1; /*!< [27..27] Adjustment Direction for receive sampling timing */ + __IOM uint32_t ATT : 3; /*!< [30..28] Adjustment value for Transmit timing */ + __IOM uint32_t AET : 1; /*!< [31..31] Adjustment edge for transmit timing */ + } CCR4_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000020) Simple I2C Control Register */ + + struct + { + __IOM uint32_t IICDL : 5; /*!< [4..0] SDA Delay Output Select */ + uint32_t : 3; + __IOM uint32_t IICINTM : 1; /*!< [8..8] IICINTM */ + __IOM uint32_t IICCSC : 1; /*!< [9..9] IICCSC */ + uint32_t : 3; + __IOM uint32_t IICACKT : 1; /*!< [13..13] IICACKT */ + uint32_t : 2; + __IOM uint32_t IICSTAREQ : 1; /*!< [16..16] IICSTAREQ */ + __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] IICRSTAREQ */ + __IOM uint32_t IICSTPREQ : 1; /*!< [18..18] IICSTPREQ */ + uint32_t : 1; + __IOM uint32_t IICSDAS : 2; /*!< [21..20] IICSDAS */ + __IOM uint32_t IICSCLS : 2; /*!< [23..22] IICSCLS */ + uint32_t : 8; + } ICR_b; + }; + + union + { + __IOM uint32_t FCR; /*!< (@ 0x00000024) FIFO Control Register */ + + struct + { + __IOM uint32_t DRES : 1; /*!< [0..0] Receive data ready error select */ + uint32_t : 7; + __IOM uint32_t TTRG : 5; /*!< [12..8] Transmit FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t TFRST : 1; /*!< [15..15] Transmit FIFO Data Register Reset */ + __IOM uint32_t RTRG : 5; /*!< [20..16] Receive FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t RFRST : 1; /*!< [23..23] Receive FIFO Data Register Reset */ + __IOM uint32_t RSTRG : 5; /*!< [28..24] RTS# Output Active Trigger Number Select */ + uint32_t : 3; + } FCR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t DCR; /*!< (@ 0x00000030) Driver Control Register */ + + struct + { + __IOM uint32_t DEPOL : 1; /*!< [0..0] Driver effective polarity select */ + uint32_t : 7; + __IOM uint32_t DEAST : 5; /*!< [12..8] Driver Assertion Time */ + uint32_t : 3; + __IOM uint32_t DENGT : 5; /*!< [20..16] Driver negate time */ + uint32_t : 11; + } DCR_b; + }; + __IM uint32_t RESERVED2[5]; + + union + { + __IM uint32_t CSR; /*!< (@ 0x00000048) Common Status Register */ + + struct + { + uint32_t : 4; + __IM uint32_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + uint32_t : 10; + __IM uint32_t RXDMON : 1; /*!< [15..15] Serial input data monitor */ + __IM uint32_t DCMF : 1; /*!< [16..16] Data Compare Match Flag */ + __IM uint32_t DPER : 1; /*!< [17..17] Data Compare Match Parity Error Flag */ + __IM uint32_t DFER : 1; /*!< [18..18] Data Compare Match Framing Error Flag */ + uint32_t : 5; + __IM uint32_t ORER : 1; /*!< [24..24] ORER */ + uint32_t : 1; + __IM uint32_t MFF : 1; /*!< [26..26] Mode Fault Error Flag */ + __IM uint32_t PER : 1; /*!< [27..27] PER */ + __IM uint32_t FER : 1; /*!< [28..28] FER */ + __IM uint32_t TDRE : 1; /*!< [29..29] Transmit Data Empty Flag */ + __IM uint32_t TEND : 1; /*!< [30..30] TEND */ + __IM uint32_t RDRF : 1; /*!< [31..31] RDRF */ + } CSR_b; + }; + + union + { + __IM uint32_t ISR; /*!< (@ 0x0000004C) Simple I2C Status Register */ + + struct + { + __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint32_t : 2; + __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag */ + uint32_t : 28; + } ISR_b; + }; + + union + { + __IM uint32_t FRSR; /*!< (@ 0x00000050) FIFO Receive Status Register */ + + struct + { + __IM uint32_t DR : 1; /*!< [0..0] DR */ + uint32_t : 7; + __IM uint32_t R : 6; /*!< [13..8] Receive FIFO Data Count */ + uint32_t : 2; + __IM uint32_t PNUM : 6; /*!< [21..16] Parity Error Count */ + uint32_t : 2; + __IM uint32_t FNUM : 6; /*!< [29..24] Framing Error Count */ + uint32_t : 2; + } FRSR_b; + }; + + union + { + __IM uint32_t FTSR; /*!< (@ 0x00000054) FIFO Transmit Status Register */ + + struct + { + __IM uint32_t T : 6; /*!< [5..0] Transmit FIFO Data Count */ + uint32_t : 26; + } FTSR_b; + }; + __IM uint32_t RESERVED3[4]; + + union + { + __OM uint32_t CFCLR; /*!< (@ 0x00000068) Common Flag Clear Register */ + + struct + { + uint32_t : 4; + __OM uint32_t ERSC : 1; /*!< [4..4] ERSC */ + uint32_t : 11; + __OM uint32_t DCMFC : 1; /*!< [16..16] DCMFC */ + __OM uint32_t DPERC : 1; /*!< [17..17] DPERC */ + __OM uint32_t DFERC : 1; /*!< [18..18] DFERC */ + uint32_t : 5; + __OM uint32_t ORERC : 1; /*!< [24..24] ORERC */ + uint32_t : 1; + __OM uint32_t MFFC : 1; /*!< [26..26] MFFC */ + __OM uint32_t PERC : 1; /*!< [27..27] PERC */ + __OM uint32_t FERC : 1; /*!< [28..28] FERC */ + __OM uint32_t TDREC : 1; /*!< [29..29] TDREC */ + uint32_t : 1; + __OM uint32_t RDRFC : 1; /*!< [31..31] RDRFC */ + } CFCLR_b; + }; + + union + { + __OM uint32_t ICFCLR; /*!< (@ 0x0000006C) Simple I2C Flag Clear Register */ + + struct + { + uint32_t : 3; + __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIFC */ + uint32_t : 28; + } ICFCLR_b; + }; + + union + { + __OM uint32_t FFCLR; /*!< (@ 0x00000070) FIFO Flag Clear Register */ + + struct + { + __OM uint32_t DRC : 1; /*!< [0..0] DRC */ + uint32_t : 31; + } FFCLR_b; + }; +} R_SCI0_Type; /*!< Size = 116 (0x74) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface 0 (R_SPI0) + */ + +typedef struct /*!< (@ 0x80003000) R_SPI0 Structure */ +{ + union + { + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000000) SPI Data Register */ + + struct + { + __IOM uint32_t SPD : 32; /*!< [31..0] The SPI data register (SPDR) is used to store SPI's + * transmit data and receive data. Transmit buffers and receive + * buffers independently function. */ + } SPDR_b; + }; + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000000) SPI Data Register */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000000) SPI Data Register */ + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x00000004) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x00000005) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Bits */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x00000006) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Bits */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t MRCKD; /*!< (@ 0x00000007) SPI ClocK Digital control Register for Master + * Receive */ + + struct + { + __IOM uint8_t ARST : 3; /*!< [2..0] Receive Sampling Timing Adjustment Bits */ + uint8_t : 5; + } MRCKD_b; + }; + + union + { + __IOM uint32_t SPCR; /*!< (@ 0x00000008) SPI Control Register */ + + struct + { + __IOM uint32_t SPE : 1; /*!< [0..0] SPI Function Enable */ + uint32_t : 6; + __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] SPI Master Receive Clock Select */ + __IOM uint32_t SPPE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t SPOE : 1; /*!< [9..9] Parity Mode */ + uint32_t : 1; + __IOM uint32_t PTE : 1; /*!< [11..11] Parity Self-Diagnosis Enable */ + __IOM uint32_t SCKASE : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable */ + __IOM uint32_t BFDS : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select */ + __IOM uint32_t MODFEN : 1; /*!< [14..14] Mode Fault Error Detection Enable */ + uint32_t : 1; + __IOM uint32_t SPEIE : 1; /*!< [16..16] SPI Error Interrupt Enable */ + __IOM uint32_t SPRIE : 1; /*!< [17..17] SPI Receive Buffer Full Interrupt Enable */ + __IOM uint32_t SPIIE : 1; /*!< [18..18] SPI Idle Interrupt Enable */ + __IOM uint32_t SPDRES : 1; /*!< [19..19] SPI Receive Data Ready Error Select */ + __IOM uint32_t SPTIE : 1; /*!< [20..20] SPI Transmit Buffer Empty Interrupt Enable */ + __IOM uint32_t CENDIE : 1; /*!< [21..21] SPI Communication End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SPMS : 1; /*!< [24..24] SPI Function Enable */ + __IOM uint32_t SPFRF : 1; /*!< [25..25] SPI Frame Format Select */ + uint32_t : 2; + __IOM uint32_t TXMD : 2; /*!< [29..28] Communication Mode Select */ + __IOM uint32_t MSTR : 1; /*!< [30..30] SPI Master/Slave Mode Select */ + __IOM uint32_t BPEN : 1; /*!< [31..31] Synchronization Circuit Bypass Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SPCRRM; /*!< (@ 0x0000000C) SPI Control Register for Master Receive only */ + + struct + { + __IOM uint8_t RMFM : 5; /*!< [4..0] Frame processing count setting in Master Receive only */ + uint8_t : 1; + __OM uint8_t RMEDTG : 1; /*!< [6..6] Reading value is always 0. */ + __OM uint8_t RMSTTG : 1; /*!< [7..7] Reading value is always 0. */ + } SPCRRM_b; + }; + + union + { + __IOM uint8_t SPDRCR; /*!< (@ 0x0000000D) SPI Control Register for Received Data Ready + * Detection */ + + struct + { + __IOM uint8_t SPDRC : 8; /*!< [7..0] SPDRC */ + } SPDRCR_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x0000000E) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + __IOM uint8_t SPOM : 1; /*!< [2..2] SPI Output Pin Mode */ + uint8_t : 1; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPSCKDL : 3; /*!< [2..0] SPI Master Receive Clock Analog Delay */ + uint8_t : 5; + } SPCR2_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000010) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + uint8_t : 4; + } SSLP_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x00000011) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] The SPBR register is used to set the bit rate in master + * mode. If SPBR is modified while SPCR.MSTR = 1 and SPCR.SPE + * = 1, subsequent operation is not guaranteed. */ + } SPBR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000013) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] SPI Sequence Length Specification */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IOM uint32_t SPCMD[8]; /*!< (@ 0x00000014) SPI Command Register [0..7] (m = 0 to 7) */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] SPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 2; /*!< [25..24] SSL Signal Assertion */ + uint32_t : 6; + } SPCMD_b[8]; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint16_t SPDCR; /*!< (@ 0x00000040) SPI Data Control Register */ + + struct + { + __IOM uint16_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint16_t SLSEL : 2; /*!< [2..1] SSL Pin Output Select */ + __IOM uint16_t SPRDTD : 1; /*!< [3..3] SPI Receive Data or Transmit Data Selection */ + __IOM uint16_t SINV : 1; /*!< [4..4] Serial data invert */ + uint16_t : 3; + __IOM uint16_t SPFC : 2; /*!< [9..8] Frame Count */ + uint16_t : 6; + } SPDCR_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPDCR2; /*!< (@ 0x00000044) SPI Data Control Register 2 */ + + struct + { + __IOM uint16_t RTRG : 2; /*!< [1..0] Receive FIFO threshold setting */ + uint16_t : 6; + __IOM uint16_t TTRG : 2; /*!< [9..8] Transmission FIFO threshold setting */ + uint16_t : 6; + } SPDCR2_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[2]; + __IM uint8_t RESERVED5; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000051) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] SPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] SPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IM uint16_t SPSR; /*!< (@ 0x00000052) SPI Status Register */ + + struct + { + uint16_t : 7; + __IM uint16_t SPDRF : 1; /*!< [7..7] SPI Receive Data Ready Flag */ + __IM uint16_t OVRF : 1; /*!< [8..8] Overrun Error Flag */ + __IM uint16_t IDLNF : 1; /*!< [9..9] SPI Idle Flag */ + __IM uint16_t MODF : 1; /*!< [10..10] Mode Fault Error Flag */ + __IM uint16_t PERF : 1; /*!< [11..11] Parity Error Flag */ + __IM uint16_t UDRF : 1; /*!< [12..12] Underrun Error Flag */ + __IM uint16_t SPTEF : 1; /*!< [13..13] SPI Transmit Buffer Empty Flag */ + __IM uint16_t CENDF : 1; /*!< [14..14] Communication End Flag */ + __IM uint16_t SPRF : 1; /*!< [15..15] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IM uint8_t SPTFSR; /*!< (@ 0x00000058) SPI Transfer FIFO Status Register */ + + struct + { + __IM uint8_t TFDN : 3; /*!< [2..0] Transmit FIFO data empty stage number */ + uint8_t : 5; + } SPTFSR_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IM uint8_t SPRFSR; /*!< (@ 0x0000005C) SPI Receive FIFO Status Register */ + + struct + { + __IM uint8_t RFDN : 3; /*!< [2..0] Receive FIFO data store stage number */ + uint8_t : 5; + } SPRFSR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + + union + { + __IM uint32_t SPPSR; /*!< (@ 0x00000060) SPI Poling Register */ + + struct + { + __IM uint32_t SPEPS : 1; /*!< [0..0] SPI Polling Status */ + uint32_t : 31; + } SPPSR_b; + }; + __IM uint32_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t SPSRC; /*!< (@ 0x0000006A) SPI Status Clear Register */ + + struct + { + uint16_t : 7; + __OM uint16_t SPDRFC : 1; /*!< [7..7] SPI Receive Data Ready Flag Clear */ + __OM uint16_t OVRFC : 1; /*!< [8..8] Overrun Error Flag Clear */ + uint16_t : 1; + __OM uint16_t MODFC : 1; /*!< [10..10] Mode Fault Error Flag Clear */ + __OM uint16_t PERFC : 1; /*!< [11..11] Parity Error Flag Clear */ + __OM uint16_t UDRFC : 1; /*!< [12..12] Underrun Error Flag Clear */ + __OM uint16_t SPTEFC : 1; /*!< [13..13] SPI Transmit Buffer Empty Flag Clear */ + __OM uint16_t CENDFC : 1; /*!< [14..14] Communication End Flag Clear */ + __OM uint16_t SPRFC : 1; /*!< [15..15] SPI Receive Buffer Full Flag Clear */ + } SPSRC_b; + }; + + union + { + __OM uint8_t SPFCR; /*!< (@ 0x0000006C) SPI FIFO Clear Register */ + + struct + { + __OM uint8_t SPFRST : 1; /*!< [0..0] SPI FIFO clear */ + uint8_t : 7; + } SPFCR_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; +} R_SPI0_Type; /*!< Size = 112 (0x70) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CRC Unit 0 (R_CRC0) + */ + +typedef struct /*!< (@ 0x80004000) R_CRC0 Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register 0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register */ + }; + + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register */ + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register */ + }; +} R_CRC0_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CAN-FD (R_CANFD) + */ + +typedef struct /*!< (@ 0x80020000) R_CANFD Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) CANFD Channel [0..1] Registers */ + __IM uint32_t RESERVED[24]; + + union + { + __IM uint32_t CFDGIPV; /*!< (@ 0x00000080) Global IP Version Register */ + + struct + { + __IM uint32_t IPV : 8; /*!< [7..0] IP Version */ + __IM uint32_t IPT : 2; /*!< [9..8] IP Type */ + uint32_t : 6; + __IM uint32_t PSI : 14; /*!< [29..16] Parameter Status Information */ + uint32_t : 2; + } CFDGIPV_b; + }; + + union + { + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ + + struct + { + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD Message Payload Overflow Configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; + + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ + + struct + { + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC Check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message Lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD Message Payload Overflow Flag Interrupt Enable */ + __IOM uint32_t QOWEIE : 1; /*!< [12..12] TXQ Message Overwrite Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message Lost Error Interrupt Enable */ + __IOM uint32_t MOWEIE : 1; /*!< [15..15] Message Lost Error Interrupt Enable */ + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + uint32_t : 15; + } CFDGCTR_b; + }; + + union + { + __IM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ + + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialization */ + uint32_t : 28; + } CFDGSTS_b; + }; + + union + { + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */ + + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD Message Payload Overflow Flag */ + __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message Overwrite Error Status */ + uint32_t : 1; + __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */ + __IM uint32_t MOWES : 1; /*!< [7..7] Message Overwrite Error Status */ + uint32_t : 8; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */ + uint32_t : 14; + } CFDGERFL_b; + }; + + union + { + __IM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */ + + struct + { + __IM uint32_t TS : 16; /*!< [15..0] Timestamp value */ + uint32_t : 16; + } CFDGTSC_b; + }; + + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */ + + struct + { + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; + + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register + * 0 */ + + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */ + + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; + }; + + union + { + __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */ + + struct + { + __IOM uint32_t RMNS : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration/Control Register [0..7] */ + + struct + { + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size Configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full Interrupt Enable */ + uint32_t : 15; + } CFDRFCC_b[8]; + }; + + union + { + __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Register [0..7] */ + + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */ + uint32_t : 15; + } CFDRFSTS_b[8]; + }; + + union + { + __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Register [0..7] */ + + struct + { + __IOM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[8]; + }; + + union + { + __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration/Control Register [0..5] */ + + struct + { + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data Size Configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[6]; + }; + __IM uint32_t RESERVED3[18]; + + union + { + __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration/Control Enhancement + * Register [0..5] */ + + struct + { + __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full Interrupt Enable */ + __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */ + __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO Message Overwrite Mode */ + uint32_t : 7; + __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */ + uint32_t : 15; + } CFDCFCCE_b[6]; + }; + __IM uint32_t RESERVED4[18]; + + union + { + __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Register [0..5] */ + + struct + { + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */ + __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */ + __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */ + uint32_t : 5; + __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO Message Overwrite */ + uint32_t : 7; + } CFDCFSTS_b[6]; + }; + __IM uint32_t RESERVED5[18]; + + union + { + __OM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Register [0..5] */ + + struct + { + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[6]; + }; + __IM uint32_t RESERVED6[18]; + + union + { + __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */ + + struct + { + __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIFO Empty Status */ + __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIFO Empty Status */ + uint32_t : 18; + } CFDFESTS_b; + }; + + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */ + + struct + { + __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIFO Full Status */ + __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIFO Full Status */ + uint32_t : 18; + } CFDFFSTS_b; + }; + + union + { + __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */ + + struct + { + __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Message Lost Status */ + __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Message Lost Status */ + uint32_t : 18; + } CFDFMSTS_b; + }; + + union + { + __IM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */ + + struct + { + __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 8; + __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */ + uint32_t : 8; + } CFDRFISTS_b; + }; + + union + { + __IM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */ + + struct + { + __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFRISTS_b; + }; + + union + { + __IM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */ + + struct + { + __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFTISTS_b; + }; + + union + { + __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status + * Register */ + + struct + { + __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO One Frame RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFRISTS_b; + }; + + union + { + __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status + * Register */ + + struct + { + __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO One Frame TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFTISTS_b; + }; + + union + { + __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Overwrite Status Register */ + + struct + { + __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO Massage Overwrite Status */ + uint32_t : 26; + } CFDCFMOWSTS_b; + }; + + union + { + __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */ + + struct + { + __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC Level Full Status */ + __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC Level Full Status */ + uint32_t : 18; + } CFDFFFSTS_b; + }; + __IM uint32_t RESERVED7[2]; + + union + { + __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Register [0..127] */ + + struct + { + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission Abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[128]; + }; + __IM uint32_t RESERVED8[288]; + + union + { + __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Register [0..127] */ + + struct + { + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission Abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[128]; + }; + __IM uint32_t RESERVED9[288]; + + union + { + __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status + * Register [0..3] */ + + struct + { + __IM uint32_t TMTRSTS : 16; /*!< [15..0] TX Message Buffer Transmission Request Status */ + uint32_t : 16; + } CFDTMTRSTS_b[4]; + }; + __IM uint32_t RESERVED10[36]; + + union + { + __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request + * Status Register [0..3] */ + + struct + { + __IM uint32_t TMTARSTS : 16; /*!< [15..0] TX Message Buffer Transmission Abort Request Status */ + uint32_t : 16; + } CFDTMTARSTS_b[4]; + }; + __IM uint32_t RESERVED11[36]; + + union + { + __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status + * Register [0..3] */ + + struct + { + __IM uint32_t TMTCSTS : 16; /*!< [15..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 16; + } CFDTMTCSTS_b[4]; + }; + __IM uint32_t RESERVED12[36]; + + union + { + __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register + * [0..3] */ + + struct + { + __IM uint32_t TMTASTS : 16; /*!< [15..0] TX Message Buffer Transmission Abort Status */ + uint32_t : 16; + } CFDTMTASTS_b[4]; + }; + __IM uint32_t RESERVED13[36]; + + union + { + __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Transmission Interrupt Enable + * Register [0..3] */ + + struct + { + __IOM uint32_t TMIE : 16; /*!< [15..0] TX Message Buffer Interrupt Enable */ + uint32_t : 16; + } CFDTMIEC_b[4]; + }; + __IM uint32_t RESERVED14[40]; + + union + { + __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration/Control Register 0[0..1] */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC0_b[2]; + }; + __IM uint32_t RESERVED15[6]; + + union + { + __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Register 0[0..1] */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS0_b[2]; + }; + __IM uint32_t RESERVED16[6]; + + union + { + __OM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Register 0[0..1] */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[2]; + }; + __IM uint32_t RESERVED17[6]; + + union + { + __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration/Control Register 1[0..1] */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC1_b[2]; + }; + __IM uint32_t RESERVED18[6]; + + union + { + __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Register 1[0..1] */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS1_b[2]; + }; + __IM uint32_t RESERVED19[6]; + + union + { + __OM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Register 1[0..1] */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR1_b[2]; + }; + __IM uint32_t RESERVED20[6]; + + union + { + __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration/Control Register 2[0..1] */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC2_b[2]; + }; + __IM uint32_t RESERVED21[6]; + + union + { + __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Register 2[0..1] */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS2_b[2]; + }; + __IM uint32_t RESERVED22[6]; + + union + { + __OM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Register 2[0..1] */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR2_b[2]; + }; + __IM uint32_t RESERVED23[6]; + + union + { + __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration/Control Register 3[0..1] */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 1; + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 5; + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC3_b[2]; + }; + __IM uint32_t RESERVED24[6]; + + union + { + __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Register 3[0..1] */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 4; + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + uint32_t : 1; + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS3_b[2]; + }; + __IM uint32_t RESERVED25[6]; + + union + { + __OM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Register 3[0..1] */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR3_b[2]; + }; + __IM uint32_t RESERVED26[6]; + + union + { + __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */ + + struct + { + __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ Empty Status */ + uint32_t : 24; + } CFDTXQESTS_b; + }; + + union + { + __IM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status Flag for Channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status Flag for Channel 1 */ + uint32_t : 25; + } CFDTXQFISTS_b; + }; + + union + { + __IM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */ + + struct + { + __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ Message Lost Status Flag for Channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ Message Lost Status Flag for Channel 1 */ + uint32_t : 25; + } CFDTXQMSTS_b; + }; + __IM uint32_t RESERVED27; + + union + { + __IM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for Channel 0 */ + __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for Channel 1 */ + uint32_t : 24; + } CFDTXQISTS_b; + }; + + union + { + __IM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for Channel 0 */ + __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for Channel 1 */ + uint32_t : 24; + } CFDTXQOFTISTS_b; + }; + + union + { + __IM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag for Channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag for Channel 1 */ + uint32_t : 25; + } CFDTXQOFRISTS_b; + }; + + union + { + __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */ + + struct + { + __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for Channel 0 */ + __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for Channel 1 */ + uint32_t : 24; + } CFDTXQFSTS_b; + }; + __IM uint32_t RESERVED28[24]; + + union + { + __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration/Control Register + * [0..1] */ + + struct + { + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated Gateway Enable */ + uint32_t : 20; + } CFDTHLCC_b[2]; + }; + __IM uint32_t RESERVED29[6]; + + union + { + __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register [0..1] */ + + struct + { + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[2]; + }; + __IM uint32_t RESERVED30[6]; + + union + { + __OM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Register [0..1] */ + + struct + { + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[2]; + }; + __IM uint32_t RESERVED31[46]; + + union + { + __IM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */ + + struct + { + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel + * 0 */ + __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel + * 0 */ + uint32_t : 1; + __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */ + __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */ + __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */ + __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */ + __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */ + __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel + * 1 */ + __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel + * 1 */ + uint32_t : 17; + } CFDGTINTSTS0_b; + }; + __IM uint32_t RESERVED32; + + union + { + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */ + + struct + { + __IOM uint32_t C0ICBCE : 1; /*!< [0..0] Channel 0 Internal CAN Bus Communication Test Mode Enable */ + __IOM uint32_t C1ICBCE : 1; /*!< [1..1] Channel 1 Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 14; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; + }; + + union + { + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */ + + struct + { + __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 1; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; + }; + __IM uint32_t RESERVED33; + + union + { + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration Register */ + + struct + { + __IOM uint32_t RPED : 1; /*!< [0..0] RES Bit Protocol Exception Disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp Capture Configuration */ + uint32_t : 22; + } CFDGFDCFG_b; + }; + __IM uint32_t RESERVED34; + + union + { + __OM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */ + + struct + { + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; + }; + __IM uint32_t RESERVED35[4]; + + union + { + __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */ + + struct + { + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RX FIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RX FIFO 1 */ + __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RX FIFO 2 */ + __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RX FIFO 3 */ + __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RX FIFO 4 */ + __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RX FIFO 5 */ + __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RX FIFO 6 */ + __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RX FIFO 7 */ + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of Channel 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of Channel 1 */ + uint32_t : 22; + } CFDCDTCT_b; + }; + + union + { + __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */ + + struct + { + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */ + __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */ + __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */ + __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */ + __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */ + __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */ + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of Channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of Channel + * 1 */ + uint32_t : 22; + } CFDCDTSTS_b; + }; + __IM uint32_t RESERVED36[2]; + + union + { + __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */ + + struct + { + __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of Channel 0 */ + __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of Channel 1 */ + uint32_t : 6; + __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of Channel 0 */ + __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of Channel 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of Channel + * 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of Channel + * 1 */ + uint32_t : 14; + } CFDCDTTCT_b; + }; + + union + { + __IM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */ + + struct + { + __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of Channel 0 */ + __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of Channel 1 */ + uint32_t : 6; + __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of Channel 0 */ + __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of Channel 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status for Common FIFO 2 of Channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status for Common FIFO 2 of Channel + * 1 */ + uint32_t : 14; + } CFDCDTTSTS_b; + }; + __IM uint32_t RESERVED37[2]; + + union + { + __IM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register [0..1] */ + + struct + { + __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n (n = 0, 1) */ + uint32_t : 1; + __IM uint32_t BQFIF : 2; /*!< [5..4] Borrowed TXQ Full Interrupt Flag Channel n (n = 0, 1) */ + uint32_t : 2; + __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n (n = 0, 1) */ + uint32_t : 1; + __IM uint32_t BQOFRIF : 2; /*!< [13..12] Borrowed TXQ One Frame RX Interrupt Flag Channel n + * (n = 0, 1) */ + uint32_t : 2; + __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n (n = 0, 1) */ + uint32_t : 5; + __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC Level Full Interrupt Flag Channel n + * (n = 0, 1) */ + uint32_t : 1; + __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n (n + * = 0, 1) */ + uint32_t : 1; + } CFDGRINTSTS_b[2]; + }; + __IM uint32_t RESERVED38[10]; + + union + { + __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global Reset Control Register */ + + struct + { + __IOM uint32_t SRST : 1; /*!< [0..0] Software Reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key Code */ + uint32_t : 16; + } CFDGRSTC_b; + }; + + union + { + __IOM uint32_t CFDGFCMC; /*!< (@ 0x00001384) Global Flexible CAN Mode Configuration Register */ + + struct + { + __IOM uint32_t FLXC0 : 1; /*!< [0..0] Flexible CAN Mode between Channel 0 and Channel 1 */ + uint32_t : 31; + } CFDGFCMC_b; + }; + __IM uint32_t RESERVED39; + + union + { + __IOM uint32_t CFDGFTBAC; /*!< (@ 0x0000138C) Global Flexible Transmission Buffer Assignment + * Configuration Register */ + + struct + { + __IOM uint32_t FLXMB0 : 4; /*!< [3..0] Flexible Transmission Buffer Assignment between Channel + * 0 and Channel 1 */ + uint32_t : 28; + } CFDGFTBAC_b; + }; + __IM uint32_t RESERVED40[28]; + __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ + __IM uint32_t RESERVED41[240]; + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED42[448]; + __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED43[3072]; + __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */ + __IM uint32_t RESERVED44[1600]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ + __IM uint32_t RESERVED45[252]; + + union + { + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Register [0..63] */ + + struct + { + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; + }; + __IM uint32_t RESERVED46[7872]; + __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Registers */ +} R_CANFD_Type; /*!< Size = 81920 (0x14000) */ + +/* =========================================================================================================================== */ +/* ================ R_CMT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Compare Match Timer Control (R_CMT) + */ + +typedef struct /*!< (@ 0x80040000) R_CMT Structure */ +{ + __IOM R_CMT_UNT_Type UNT[3]; /*!< (@ 0x00000000) 3 Timer Start Register Units */ +} R_CMT_Type; /*!< Size = 3072 (0xc00) */ + +/* =========================================================================================================================== */ +/* ================ R_CMTW0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Compare Match Timer W (R_CMTW0) + */ + +typedef struct /*!< (@ 0x80041000) R_CMTW0 Structure */ +{ + union + { + __IOM uint16_t CMWSTR; /*!< (@ 0x00000000) Timer Start Register */ + + struct + { + __IOM uint16_t STR : 1; /*!< [0..0] Counter Start */ + uint16_t : 15; + } CMWSTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CMWCR; /*!< (@ 0x00000004) Timer Control Register */ + + struct + { + __IOM uint16_t CKS : 2; /*!< [1..0] Clock Select */ + uint16_t : 1; + __IOM uint16_t CMWIE : 1; /*!< [3..3] Compare Match Interrupt Enable */ + __IOM uint16_t IC0IE : 1; /*!< [4..4] Input Capture 0 Interrupt Enable */ + __IOM uint16_t IC1IE : 1; /*!< [5..5] Input Capture 1 Interrupt Enable */ + __IOM uint16_t OC0IE : 1; /*!< [6..6] Output Compare 0 Interrupt Enable */ + __IOM uint16_t OC1IE : 1; /*!< [7..7] Output Compare 1 Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t CMS : 1; /*!< [9..9] Timer Counter Size */ + uint16_t : 3; + __IOM uint16_t CCLR : 3; /*!< [15..13] Counter Clear */ + } CMWCR_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t CMWIOR; /*!< (@ 0x00000008) Timer I/O Control Register */ + + struct + { + __IOM uint16_t IC0 : 2; /*!< [1..0] Input Capture Control 0 */ + __IOM uint16_t IC1 : 2; /*!< [3..2] Input Capture Control 1 */ + __IOM uint16_t IC0E : 1; /*!< [4..4] Input Capture Enable 0 */ + __IOM uint16_t IC1E : 1; /*!< [5..5] Input Capture Enable 1 */ + uint16_t : 2; + __IOM uint16_t OC0 : 2; /*!< [9..8] Output Compare Control 0 */ + __IOM uint16_t OC1 : 2; /*!< [11..10] Output Compare Control 1 */ + __IOM uint16_t OC0E : 1; /*!< [12..12] Compare Match Enable 0 */ + __IOM uint16_t OC1E : 1; /*!< [13..13] Compare Match Enable 1 */ + uint16_t : 1; + __IOM uint16_t CMWE : 1; /*!< [15..15] Compare Match Enable */ + } CMWIOR_b; + }; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3; + __IOM uint32_t CMWCNT; /*!< (@ 0x00000010) Timer Counter */ + __IOM uint32_t CMWCOR; /*!< (@ 0x00000014) Compare Match Constant Register */ + __IM uint32_t CMWICR0; /*!< (@ 0x00000018) Input Capture Registers */ + __IM uint32_t CMWICR1; /*!< (@ 0x0000001C) Input Capture Registers */ + __IOM uint32_t CMWOCR0; /*!< (@ 0x00000020) Output Compare Registers */ + __IOM uint32_t CMWOCR1; /*!< (@ 0x00000024) Output Compare Registers */ +} R_CMTW0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer 0 (R_WDT0) + */ + +typedef struct /*!< (@ 0x80042000) R_WDT0 Structure */ +{ + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_WDT0_Type; /*!< Size = 10 (0xa) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface 0 (R_IIC0) + */ + +typedef struct /*!< (@ 0x80043000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __OM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] IIC-Bus Interface Internal Reset */ + __IOM uint8_t ICE : 1; /*!< [7..7] IIC-Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance Request */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance Request */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance Request */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock Select */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Select */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Select */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAIT */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/IIC-Bus Select */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + uint8_t : 1; + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period */ + uint8_t : 3; + } ICBRH_b; + }; + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ +} R_IIC0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x80044000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 1; + __IOM uint8_t DOPCIE : 1; /*!< [4..4] Data Operation Circuit Interrupt Enable */ + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __OM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Flag Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC121 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 12-Bit A/D converter (R_ADC121) + */ + +typedef struct /*!< (@ 0x80045000) R_ADC121 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel Select */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + uint16_t : 2; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D conversion Start */ + } ADCSR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t ADANSA0; /*!< (@ 0x00000004) A/D Channel Select Register A0 */ + + struct + { + __IOM uint16_t ANSA0 : 16; /*!< [15..0] A/D conversion Analog input Channel Select */ + } ADANSA0_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t ADADS0; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Function + * Channel Select Register 0 */ + + struct + { + __IOM uint16_t ADS0 : 16; /*!< [15..0] A/D-Converted Value Addition/Average Channel Select */ + } ADADS0_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition Count Select */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable */ + } ADADC_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 2; + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 9; + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group B */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger Select */ + uint16_t : 2; + } ADSTRGR_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ADANSB0; /*!< (@ 0x00000014) A/D Channel Select Register B0 */ + + struct + { + __IOM uint16_t ANSB0 : 16; /*!< [15..0] A/D Conversion Analog Input Channel Select */ + } ADANSB0_b; + }; + __IM uint16_t RESERVED5; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t DBLDR : 16; /*!< [15..0] The result of A/D conversion in response to the second + * trigger in double trigger mode. */ + } ADDBLDR_b; + }; + __IM uint16_t RESERVED6[3]; + + union + { + __IM uint16_t ADDR[16]; /*!< (@ 0x00000020) A/D Data Register n (n = 0 to 7 for unit 0, n + * = 0 to 15 for unit1) */ + + struct + { + __IM uint16_t DR : 16; /*!< [15..0] The result of A/D conversion (n: Number of channel) */ + } ADDR_b[16]; + }; + __IM uint16_t RESERVED7[19]; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Sample and hold period setting */ + __IOM uint16_t SHANS : 3; /*!< [10..8] Sample and hold use or bypass select for ch0-2 */ + uint16_t : 5; + } ADSHCR_b; + }; + __IM uint16_t RESERVED8[10]; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADELCCR; /*!< (@ 0x0000007D) A/D Event Link Control Register */ + + struct + { + __IOM uint8_t ELCC : 2; /*!< [1..0] Event link control bits */ + __IOM uint8_t GCELC : 1; /*!< [2..2] Event control bit for Group C */ + uint8_t : 5; + } ADELCCR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group Priority Control Setting */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting */ + uint16_t : 12; + __IOM uint16_t LGRRS : 1; /*!< [14..14] Restart Channel Select */ + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start */ + } ADGSPCR_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplication Register A */ + + struct + { + __IM uint16_t DBLDRA : 16; /*!< [15..0] The result of A/D conversion during extended operation + * in double trigger mode */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplication Register B */ + + struct + { + __IM uint16_t DBLDRB : 16; /*!< [15..0] The result of A/D conversion during extended operation + * in double trigger mode */ + } ADDBLDRB_b; + }; + __IM uint16_t RESERVED12[2]; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitoring + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitor */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparing result monitor for window A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparing result monitor for window B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B combination condition setting */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Window B operation permission */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Window A operation permission */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare window B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function enable */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare window A Interrupt Enable */ + } ADCMPCR_b; + }; + __IM uint16_t RESERVED15; + + union + { + __IOM uint16_t ADCMPANSR0; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register 0 */ + + struct + { + __IOM uint16_t CMPCHA0 : 16; /*!< [15..0] Window A Channel Select */ + } ADCMPANSR0_b; + }; + __IM uint16_t RESERVED16; + + union + { + __IOM uint16_t ADCMPLR0; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register 0 */ + + struct + { + __IOM uint16_t CMPLCHA0 : 16; /*!< [15..0] Window A comparison condition for target channel (ch0-15) + * setting */ + } ADCMPLR0_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Comparison Function Window A Lower Level + * Setting Register */ + + struct + { + __IOM uint16_t CMPLLA : 16; /*!< [15..0] Reference data setting when using the compare function + * window A */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) AD Comparison Function Window A Upper Level Setting + * Register */ + + struct + { + __IOM uint16_t CMPULA : 16; /*!< [15..0] Reference data setting when using the compare function + * window A */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR0; /*!< (@ 0x000000A0) A/D Comparison Function Window A Channel Status + * Register 0 */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 16; /*!< [15..0] Window A Status Flag */ + } ADCMPSR0_b; + }; + __IM uint16_t RESERVED18[2]; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Select + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Window B Channel Select */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Window B Comparison Condition Setting */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED19; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t CMPLLB : 16; /*!< [15..0] Reference lower data setting when using the compare + * function window B */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t CMPULB : 16; /*!< [15..0] Reference upper data setting when using the compare + * function window B */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Window B Flag */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21[19]; + + union + { + __IOM uint16_t ADANSC0; /*!< (@ 0x000000D4) A/D Channel Select Register C0 */ + + struct + { + __IOM uint16_t ANSC0 : 16; /*!< [15..0] A/D-Converted Channel Select for Group C in Group Scan + * Mode */ + } ADANSC0_b; + }; + __IM uint16_t RESERVED22; + __IM uint8_t RESERVED23; + + union + { + __IOM uint8_t ADGCTRGR; /*!< (@ 0x000000D9) A/D Group C Trigger Select Register */ + + struct + { + __IOM uint8_t TRSC : 6; /*!< [5..0] Group C A/D Conversion Start Trigger Select */ + __IOM uint8_t GCADIE : 1; /*!< [6..6] Group C Scan Completion Interrupt Enable */ + __IOM uint8_t GRCE : 1; /*!< [7..7] Group C A/D Conversion Enable */ + } ADGCTRGR_b; + }; + __IM uint16_t RESERVED24[3]; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Register n (n = 0 to 7 for + * unit 0, n = 0 to 15 for unit1) */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting */ + } ADSSTR_b[16]; + }; +} R_ADC121_Type; /*!< Size = 240 (0xf0) */ + +/* =========================================================================================================================== */ +/* ================ R_TSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor Unit (R_TSU) + */ + +typedef struct /*!< (@ 0x80046000) R_TSU Structure */ +{ + union + { + __IOM uint32_t TSUSM; /*!< (@ 0x00000000) Sensor Mode Register */ + + struct + { + __IOM uint32_t TSEN : 1; /*!< [0..0] Temperature Sensor Enable */ + __IOM uint32_t ADCEN : 1; /*!< [1..1] ADC Enable */ + uint32_t : 30; + } TSUSM_b; + }; + + union + { + __IOM uint32_t TSUST; /*!< (@ 0x00000004) Sensor Trigger Register */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] A/D Conversion Control */ + uint32_t : 31; + } TSUST_b; + }; + + union + { + __IOM uint32_t TSUSCS; /*!< (@ 0x00000008) Sensor Configuration Setting Register */ + + struct + { + uint32_t : 3; + __IOM uint32_t CKDIV : 1; /*!< [3..3] Divider Value for PCLKL */ + uint32_t : 28; + } TSUSCS_b; + }; + + union + { + __IM uint32_t TSUSAD; /*!< (@ 0x0000000C) Sensor ADC Data Register */ + + struct + { + __IM uint32_t DOUT : 12; /*!< [11..0] Temperature Sensor Data Output */ + uint32_t : 20; + } TSUSAD_b; + }; + + union + { + __IM uint32_t TSUSS; /*!< (@ 0x00000010) Sensor Status Register */ + + struct + { + __IM uint32_t CONV : 1; /*!< [0..0] A/D Conversion Status */ + uint32_t : 31; + } TSUSS_b; + }; +} R_TSU_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG1 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GPT Port Output Enable 1 (R_POEG1) + */ + +typedef struct /*!< (@ 0x80047000) R_POEG1 Structure */ +{ + union + { + __IOM uint32_t POEG1GA; /*!< (@ 0x00000000) POEG1 Group A Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG1GA_b; + }; + __IM uint32_t RESERVED[255]; + + union + { + __IOM uint32_t POEG1GB; /*!< (@ 0x00000400) POEG1 Group B Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG1GB_b; + }; + __IM uint32_t RESERVED1[255]; + + union + { + __IOM uint32_t POEG1GC; /*!< (@ 0x00000800) POEG1 Group C Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG1GC_b; + }; + __IM uint32_t RESERVED2[255]; + + union + { + __IOM uint32_t POEG1GD; /*!< (@ 0x00000C00) POEG1 Group D Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG1GD_b; + }; +} R_POEG1_Type; /*!< Size = 3076 (0xc04) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller 0 (R_DMAC0) + */ + +typedef struct /*!< (@ 0x80080000) R_DMAC0 Structure */ +{ + __IOM R_DMAC0_GRP_Type GRP[2]; /*!< (@ 0x00000000) 8 channel Registers */ +} R_DMAC0_Type; /*!< Size = 2048 (0x800) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU_NS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller in Non Safety Domain (R_ICU_NS) + */ + +typedef struct /*!< (@ 0x80090000) R_ICU_NS Structure */ +{ + union + { + __OM uint32_t NS_SWINT; /*!< (@ 0x00000000) Software Interrupt Register */ + + struct + { + __OM uint32_t IC0 : 1; /*!< [0..0] Software Interrupt register */ + __OM uint32_t IC1 : 1; /*!< [1..1] Software Interrupt register */ + __OM uint32_t IC2 : 1; /*!< [2..2] Software Interrupt register */ + __OM uint32_t IC3 : 1; /*!< [3..3] Software Interrupt register */ + __OM uint32_t IC4 : 1; /*!< [4..4] Software Interrupt register */ + __OM uint32_t IC5 : 1; /*!< [5..5] Software Interrupt register */ + uint32_t : 26; + } NS_SWINT_b; + }; + + union + { + __IOM uint32_t NS_PORTNF_FLTSEL; /*!< (@ 0x00000004) Interrupt Noise Filter Enable Register */ + + struct + { + __IOM uint32_t FLT0 : 1; /*!< [0..0] Noise filter enable for IRQ0 */ + __IOM uint32_t FLT1 : 1; /*!< [1..1] Noise filter enable for IRQ1 */ + __IOM uint32_t FLT2 : 1; /*!< [2..2] Noise filter enable for IRQ2 */ + __IOM uint32_t FLT3 : 1; /*!< [3..3] Noise filter enable for IRQ3 */ + __IOM uint32_t FLT4 : 1; /*!< [4..4] Noise filter enable for IRQ4 */ + __IOM uint32_t FLT5 : 1; /*!< [5..5] Noise filter enable for IRQ5 */ + __IOM uint32_t FLT6 : 1; /*!< [6..6] Noise filter enable for IRQ6 */ + __IOM uint32_t FLT7 : 1; /*!< [7..7] Noise filter enable for IRQ7 */ + __IOM uint32_t FLT8 : 1; /*!< [8..8] Noise filter enable for IRQ8 */ + __IOM uint32_t FLT9 : 1; /*!< [9..9] Noise filter enable for IRQ9 */ + __IOM uint32_t FLT10 : 1; /*!< [10..10] Noise filter enable for IRQ10 */ + __IOM uint32_t FLT11 : 1; /*!< [11..11] Noise filter enable for IRQ11 */ + __IOM uint32_t FLT12 : 1; /*!< [12..12] Noise filter enable for IRQ12 */ + __IOM uint32_t FLT13 : 1; /*!< [13..13] Noise filter enable for IRQ13 */ + __IOM uint32_t FLTDRQ : 1; /*!< [14..14] Noise filter enable for External DMA request (DREQ) */ + uint32_t : 17; + } NS_PORTNF_FLTSEL_b; + }; + + union + { + __IOM uint32_t NS_PORTNF_CLKSEL; /*!< (@ 0x00000008) Interrupt Noise Filter Setting Register */ + + struct + { + __IOM uint32_t CKSEL0 : 2; /*!< [1..0] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL1 : 2; /*!< [3..2] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL2 : 2; /*!< [5..4] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL3 : 2; /*!< [7..6] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL4 : 2; /*!< [9..8] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL5 : 2; /*!< [11..10] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL6 : 2; /*!< [13..12] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL7 : 2; /*!< [15..14] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL8 : 2; /*!< [17..16] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL9 : 2; /*!< [19..18] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL10 : 2; /*!< [21..20] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL11 : 2; /*!< [23..22] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL12 : 2; /*!< [25..24] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL13 : 2; /*!< [27..26] Noise filter sampling clock selector */ + __IOM uint32_t CKSELDREQ : 2; /*!< [29..28] Noise filter sampling clock selector */ + uint32_t : 2; + } NS_PORTNF_CLKSEL_b; + }; + + union + { + __IOM uint32_t NS_PORTNF_MD; /*!< (@ 0x0000000C) Interrupt Edge Detection Setting Register */ + + struct + { + __IOM uint32_t MD0 : 2; /*!< [1..0] Select detection mode for IRQ0 */ + __IOM uint32_t MD1 : 2; /*!< [3..2] Select detection mode for IRQ1 */ + __IOM uint32_t MD2 : 2; /*!< [5..4] Select detection mode for IRQ2 */ + __IOM uint32_t MD3 : 2; /*!< [7..6] Select detection mode for IRQ3 */ + __IOM uint32_t MD4 : 2; /*!< [9..8] Select detection mode for IRQ4 */ + __IOM uint32_t MD5 : 2; /*!< [11..10] Select detection mode for IRQ5 */ + __IOM uint32_t MD6 : 2; /*!< [13..12] Select detection mode for IRQ6 */ + __IOM uint32_t MD7 : 2; /*!< [15..14] Select detection mode for IRQ7 */ + __IOM uint32_t MD8 : 2; /*!< [17..16] Select detection mode for IRQ8 */ + __IOM uint32_t MD9 : 2; /*!< [19..18] Select detection mode for IRQ9 */ + __IOM uint32_t MD10 : 2; /*!< [21..20] Select detection mode for IRQ10 */ + __IOM uint32_t MD11 : 2; /*!< [23..22] Select detection mode for IRQ11 */ + __IOM uint32_t MD12 : 2; /*!< [25..24] Select detection mode for IRQ12 */ + __IOM uint32_t MD13 : 2; /*!< [27..26] Select detection mode for IRQ13 */ + __IOM uint32_t MDDRQ : 2; /*!< [29..28] Select detection mode for DREQ of DMAC */ + uint32_t : 2; + } NS_PORTNF_MD_b; + }; +} R_ICU_NS_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Evnet Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x80090010) R_ELC Structure */ +{ + union + { + __IOM uint32_t ELC_SSEL[19]; /*!< (@ 0x00000000) ELC Event Source Select Register [0..18] */ + + struct + { + __IOM uint32_t ELC_SEL0 : 10; /*!< [9..0] Set the number for ELC event source to be linked to the + * ELC destination. */ + __IOM uint32_t ELC_SEL1 : 10; /*!< [19..10] Set the number for ELC event source to be linked to + * the ELC destination. */ + __IOM uint32_t ELC_SEL2 : 10; /*!< [29..20] Set the number for ELC event source to be linked to + * the ELC destination. */ + uint32_t : 2; + } ELC_SSEL_b[19]; + }; +} R_ELC_Type; /*!< Size = 76 (0x4c) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMAC Configuration (R_DMA) + */ + +typedef struct /*!< (@ 0x80090060) R_DMA Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DMAC0_RSSEL[6]; /*!< (@ 0x0000000C) DMAC Unit 0 Resource Select Register [0..5] */ + + struct + { + __IOM uint32_t REQ_SELA : 9; /*!< [8..0] DMA Resource Select for Channel n */ + uint32_t : 1; + __IOM uint32_t REQ_SELB : 9; /*!< [18..10] DMA Resource Select for Channel n + 1 */ + uint32_t : 1; + __IOM uint32_t REQ_SELC : 9; /*!< [28..20] DMA Resource Select for Channel n + 2 */ + uint32_t : 3; + } DMAC0_RSSEL_b[6]; + }; + + union + { + __IOM uint32_t DMAC1_RSSEL[6]; /*!< (@ 0x00000024) DMAC Unit 1 Resource Select Register [0..5] */ + + struct + { + __IOM uint32_t REQ_SELA : 9; /*!< [8..0] DMA Resource Select for Channel n */ + uint32_t : 1; + __IOM uint32_t REQ_SELB : 9; /*!< [18..10] DMA Resource Select for Channel n + 1 */ + uint32_t : 1; + __IOM uint32_t REQ_SELC : 9; /*!< [28..20] DMA Resource Select for Channel n + 2 */ + uint32_t : 3; + } DMAC1_RSSEL_b[6]; + }; +} R_DMA_Type; /*!< Size = 60 (0x3c) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT_NSR ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (Non safety region) (R_PORT_NSR) + */ + +typedef struct /*!< (@ 0x800A0000) R_PORT_NSR Structure */ +{ + union + { + __IOM uint8_t P[25]; /*!< (@ 0x00000000) Port [0..24] Register */ + + struct + { + __IOM uint8_t POUT_0 : 1; /*!< [0..0] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_1 : 1; /*!< [1..1] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_2 : 1; /*!< [2..2] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_3 : 1; /*!< [3..3] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_4 : 1; /*!< [4..4] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_5 : 1; /*!< [5..5] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_6 : 1; /*!< [6..6] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_7 : 1; /*!< [7..7] Pm_n Output Data Store (n: bit position) */ + } P_b[25]; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[121]; + + union + { + __IOM uint16_t PM[25]; /*!< (@ 0x00000200) Port [0..24] Mode Register */ + + struct + { + __IOM uint16_t PM0 : 2; /*!< [1..0] Pm_0 I/O Select */ + __IOM uint16_t PM1 : 2; /*!< [3..2] Pm_1 I/O Select */ + __IOM uint16_t PM2 : 2; /*!< [5..4] Pm_2 I/O Select */ + __IOM uint16_t PM3 : 2; /*!< [7..6] Pm_3 I/O Select */ + __IOM uint16_t PM4 : 2; /*!< [9..8] Pm_4 I/O Select */ + __IOM uint16_t PM5 : 2; /*!< [11..10] Pm_5 I/O Select */ + __IOM uint16_t PM6 : 2; /*!< [13..12] Pm_6 I/O Select */ + __IOM uint16_t PM7 : 2; /*!< [15..14] Pm_7 I/O Select */ + } PM_b[25]; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[115]; + + union + { + __IOM uint8_t PMC[25]; /*!< (@ 0x00000400) Port [0..24] Mode Control Register */ + + struct + { + __IOM uint8_t PMC0 : 1; /*!< [0..0] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC1 : 1; /*!< [1..1] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC2 : 1; /*!< [2..2] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC3 : 1; /*!< [3..3] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC4 : 1; /*!< [4..4] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC5 : 1; /*!< [5..5] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC6 : 1; /*!< [6..6] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC7 : 1; /*!< [7..7] Pm_n Pin Mode Control (n: bit position) */ + } PMC_b[25]; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[121]; + + union + { + __IOM uint32_t PFC[25]; /*!< (@ 0x00000600) Port [0..24] Function Control Register */ + + struct + { + __IOM uint32_t PFC0 : 4; /*!< [3..0] Pm_0 Pin function Select */ + __IOM uint32_t PFC1 : 4; /*!< [7..4] Pm_1 Pin function Select */ + __IOM uint32_t PFC2 : 4; /*!< [11..8] Pm_2 Pin function Select */ + __IOM uint32_t PFC3 : 4; /*!< [15..12] Pm_3 Pin function Select */ + __IOM uint32_t PFC4 : 4; /*!< [19..16] Pm_4 Pin function Select */ + __IOM uint32_t PFC5 : 4; /*!< [23..20] Pm_5 Pin function Select */ + __IOM uint32_t PFC6 : 4; /*!< [27..24] Pm_6 Pin function Select */ + __IOM uint32_t PFC7 : 4; /*!< [31..28] Pm_7 Pin function Select */ + } PFC_b[25]; + }; + __IM uint32_t RESERVED8[103]; + + union + { + __IM uint8_t PIN[25]; /*!< (@ 0x00000800) Port [0..24] Input Register */ + + struct + { + __IM uint8_t PIN0 : 1; /*!< [0..0] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN1 : 1; /*!< [1..1] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN2 : 1; /*!< [2..2] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN3 : 1; /*!< [3..3] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN4 : 1; /*!< [4..4] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN5 : 1; /*!< [5..5] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN6 : 1; /*!< [6..6] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN7 : 1; /*!< [7..7] Pm_n Pin Input (n: bit position) */ + } PIN_b[25]; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11[121]; + __IOM R_PORT_DRCTL_Type DRCTL[25]; /*!< (@ 0x00000A00) I/O Buffer [0..24] Function Switching Register */ + __IM uint32_t RESERVED12[206]; + + union + { + __IOM uint8_t ELC_PGR[2]; /*!< (@ 0x00000E00) ELC Port Group Setting Register [0..1] */ + + struct + { + __IOM uint8_t PG0 : 1; /*!< [0..0] Port Group Setting */ + __IOM uint8_t PG1 : 1; /*!< [1..1] Port Group Setting */ + __IOM uint8_t PG2 : 1; /*!< [2..2] Port Group Setting */ + __IOM uint8_t PG3 : 1; /*!< [3..3] Port Group Setting */ + __IOM uint8_t PG4 : 1; /*!< [4..4] Port Group Setting */ + __IOM uint8_t PG5 : 1; /*!< [5..5] Port Group Setting */ + __IOM uint8_t PG6 : 1; /*!< [6..6] Port Group Setting */ + __IOM uint8_t PG7 : 1; /*!< [7..7] Port Group Setting */ + } ELC_PGR_b[2]; + }; + + union + { + __IOM uint8_t ELC_PGC[2]; /*!< (@ 0x00000E02) ELC Port Group Control Register [0..1] */ + + struct + { + __IOM uint8_t PGCI : 2; /*!< [1..0] Event Output Edge Select */ + __IOM uint8_t PGCOVE : 1; /*!< [2..2] PDBF Overwrite */ + uint8_t : 1; + __IOM uint8_t PGCO : 3; /*!< [6..4] Port Group Operation Select */ + uint8_t : 1; + } ELC_PGC_b[2]; + }; + __IOM R_PORT_NSR_ELC_PDBF_Type ELC_PDBF[2]; /*!< (@ 0x00000E04) ELC Port Buffer Register [0..1] */ + + union + { + __IOM uint8_t ELC_PEL[4]; /*!< (@ 0x00000E0C) ELC Port Setting Register [0..3] */ + + struct + { + __IOM uint8_t PSB : 3; /*!< [2..0] Bit Number Specification */ + __IOM uint8_t PSP : 2; /*!< [4..3] Port Number Specification */ + __IOM uint8_t PSM : 2; /*!< [6..5] Event Link Specification */ + uint8_t : 1; + } ELC_PEL_b[4]; + }; + + union + { + __IOM uint8_t ELC_DPTC; /*!< (@ 0x00000E10) ELC Edge Detection Control Register */ + + struct + { + __IOM uint8_t PTC0 : 1; /*!< [0..0] Single Input Port n Edge Detection */ + __IOM uint8_t PTC1 : 1; /*!< [1..1] Single Input Port n Edge Detection */ + __IOM uint8_t PTC2 : 1; /*!< [2..2] Single Input Port n Edge Detection */ + __IOM uint8_t PTC3 : 1; /*!< [3..3] Single Input Port n Edge Detection */ + uint8_t : 4; + } ELC_DPTC_b; + }; + + union + { + __IOM uint8_t ELC_ELSR2; /*!< (@ 0x00000E11) ELC Port Event Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t PEG1 : 1; /*!< [2..2] ELC Port Buffer Register (ELC_PDBFn) write access control. + * When set to 1, writing to the ELC_PDBFn register via Internal + * peripheral bus is disabled, preventing overwriting. */ + __IOM uint8_t PEG2 : 1; /*!< [3..3] ELC Port Buffer Register (ELC_PDBFn) write access control. + * When set to 1, writing to the ELC_PDBFn register via Internal + * peripheral bus is disabled, preventing overwriting. */ + __IOM uint8_t PES0 : 1; /*!< [4..4] Single Port n Event Link Function Enable */ + __IOM uint8_t PES1 : 1; /*!< [5..5] Single Port n Event Link Function Enable */ + __IOM uint8_t PES2 : 1; /*!< [6..6] Single Port n Event Link Function Enable */ + __IOM uint8_t PES3 : 1; /*!< [7..7] Single Port n Event Link Function Enable */ + } ELC_ELSR2_b; + }; + __IM uint16_t RESERVED13; +} R_PORT_COMMON_Type; /*!< Size = 3604 (0xe14) */ + +/* =========================================================================================================================== */ +/* ================ R_GMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC (R_GMAC) + */ + +typedef struct /*!< (@ 0x80100000) R_GMAC Structure */ +{ + union + { + __IOM uint32_t MAC_Configuration; /*!< (@ 0x00000000) MAC Configuration Register */ + + struct + { + __IOM uint32_t PRELEN : 2; /*!< [1..0] Preamble Length for Transmit Frames */ + __IOM uint32_t RE : 1; /*!< [2..2] Receiver Enable */ + __IOM uint32_t TE : 1; /*!< [3..3] Transmitter Enable */ + __IOM uint32_t DC : 1; /*!< [4..4] Deferral Check */ + __IOM uint32_t BL : 2; /*!< [6..5] Back-Off Limit */ + __IOM uint32_t ACS : 1; /*!< [7..7] Automatic Pad or CRC Stripping */ + uint32_t : 1; + __IOM uint32_t DR : 1; /*!< [9..9] Disable Retry */ + __IOM uint32_t IPC : 1; /*!< [10..10] Checksum Offload */ + __IOM uint32_t DM : 1; /*!< [11..11] Duplex Mode */ + __IOM uint32_t LM : 1; /*!< [12..12] Loopback Mode */ + __IOM uint32_t DO : 1; /*!< [13..13] Disable Receive Own */ + __IOM uint32_t FES : 1; /*!< [14..14] Speed */ + __IOM uint32_t PS : 1; /*!< [15..15] Port Select */ + __IOM uint32_t DCRS : 1; /*!< [16..16] Disable Carrier Sense During Transmission */ + __IOM uint32_t IFG : 3; /*!< [19..17] Inter-Frame Gap */ + __IOM uint32_t JE : 1; /*!< [20..20] Jumbo Frame Enable */ + __IOM uint32_t BE : 1; /*!< [21..21] Frame Burst Enable */ + __IOM uint32_t JD : 1; /*!< [22..22] Jabber Disable */ + __IOM uint32_t WD : 1; /*!< [23..23] Watchdog Disable */ + uint32_t : 1; + __IOM uint32_t CST : 1; /*!< [25..25] CRC Stripping for Type Frames */ + uint32_t : 1; + __IOM uint32_t TWOKPE : 1; /*!< [27..27] IEEE 802.3 as Support for 2 K Packets */ + uint32_t : 4; + } MAC_Configuration_b; + }; + + union + { + __IOM uint32_t MAC_Frame_Filter; /*!< (@ 0x00000004) MAC Frame Filter Register */ + + struct + { + __IOM uint32_t PR : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t HUC : 1; /*!< [1..1] Hash Unicast */ + __IOM uint32_t HMC : 1; /*!< [2..2] Hash Multicast */ + __IOM uint32_t DAIF : 1; /*!< [3..3] DA Inverse Filtering */ + __IOM uint32_t PM : 1; /*!< [4..4] Pass All Multicast */ + __IOM uint32_t DBF : 1; /*!< [5..5] Disable Broadcast Frames */ + __IOM uint32_t PCF : 2; /*!< [7..6] Pass Control Frames */ + __IOM uint32_t SAIF : 1; /*!< [8..8] SA Inverse Filtering */ + __IOM uint32_t SAF : 1; /*!< [9..9] Source Address Filter Enable */ + __IOM uint32_t HPF : 1; /*!< [10..10] Hash or Perfect Filter */ + uint32_t : 5; + __IOM uint32_t VTFE : 1; /*!< [16..16] VLAN Tag Filter Enable */ + uint32_t : 14; + __IOM uint32_t RA : 1; /*!< [31..31] Receive All */ + } MAC_Frame_Filter_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GMII_Address; /*!< (@ 0x00000010) GMII Address Register */ + + struct + { + __IOM uint32_t GB : 1; /*!< [0..0] GMII Busy */ + __IOM uint32_t GW : 1; /*!< [1..1] GMII Write */ + __IOM uint32_t CR : 4; /*!< [5..2] CSR Clock Range */ + __IOM uint32_t GR : 5; /*!< [10..6] GMII Register */ + __IOM uint32_t PA : 5; /*!< [15..11] Physical Layer Address */ + uint32_t : 16; + } GMII_Address_b; + }; + + union + { + __IOM uint32_t GMII_Data; /*!< (@ 0x00000014) GMII Data Register */ + + struct + { + __IOM uint32_t GD : 16; /*!< [15..0] GMII Data */ + uint32_t : 16; + } GMII_Data_b; + }; + + union + { + __IOM uint32_t Flow_Control; /*!< (@ 0x00000018) Flow Control Register */ + + struct + { + __IOM uint32_t FCA_BPA : 1; /*!< [0..0] Flow Control Busy or Backpressure Activate */ + __IOM uint32_t TFE : 1; /*!< [1..1] Transmit Flow Control Enable */ + __IOM uint32_t RFE : 1; /*!< [2..2] Receive Flow Control Enable */ + __IOM uint32_t UP : 1; /*!< [3..3] Unicast Pause Frame Detect */ + __IOM uint32_t PLT : 2; /*!< [5..4] Pause Low Threshold */ + uint32_t : 1; + __IOM uint32_t DZPQ : 1; /*!< [7..7] Disable Zero-Quanta Pause */ + uint32_t : 8; + __IOM uint32_t PT : 16; /*!< [31..16] Pause Time */ + } Flow_Control_b; + }; + + union + { + __IOM uint32_t VLAN_Tag; /*!< (@ 0x0000001C) VLAN Tag Register */ + + struct + { + __IOM uint32_t VL : 16; /*!< [15..0] VLAN Tag Identifier for Receive Frames */ + __IOM uint32_t ETV : 1; /*!< [16..16] Enable 12-Bit VLAN Tag Comparison */ + __IOM uint32_t VTIM : 1; /*!< [17..17] VLAN Tag Inverse Match Enable */ + __IOM uint32_t ESVL : 1; /*!< [18..18] Enable S-VLAN */ + __IOM uint32_t VTHM : 1; /*!< [19..19] VLAN Tag Hash Table Match Enable */ + uint32_t : 12; + } VLAN_Tag_b; + }; + + union + { + __IM uint32_t Version; /*!< (@ 0x00000020) Version Register */ + + struct + { + __IM uint32_t VER : 16; /*!< [15..0] Version (GMAC: 0x3037) */ + uint32_t : 16; + } Version_b; + }; + + union + { + __IM uint32_t Debug; /*!< (@ 0x00000024) Debug Register */ + + struct + { + __IM uint32_t RPESTS : 1; /*!< [0..0] GMAC GMII or MII Receive Protocol Engine Status */ + __IM uint32_t RFCFCSTS : 2; /*!< [2..1] GMAC Receive Frame Controller FIFO Status */ + uint32_t : 1; + __IM uint32_t RWCSTS : 1; /*!< [4..4] MTL RX FIFO Write Controller Active Status */ + __IM uint32_t RRCSTS : 2; /*!< [6..5] MTL RX FIFO Read Controller State */ + uint32_t : 1; + __IM uint32_t RXFSTS : 2; /*!< [9..8] MTL RX FIFO Fill-level Status */ + uint32_t : 6; + __IM uint32_t TPESTS : 1; /*!< [16..16] GMAC GMII or MII Transmit Protocol Engine Status */ + __IM uint32_t TFCSTS : 2; /*!< [18..17] GMAC Transmit Frame Controller Status */ + __IM uint32_t TXPAUSED : 1; /*!< [19..19] GMAC transmitter in PAUSE */ + __IM uint32_t TRCSTS : 2; /*!< [21..20] MTL TX FIFO Read Controller Status */ + __IM uint32_t TWCSTS : 1; /*!< [22..22] MTL TX FIFO Write Controller Active Status */ + uint32_t : 1; + __IM uint32_t TXFSTS : 1; /*!< [24..24] MTL TX FIFO Not Empty Status */ + __IM uint32_t TXSTSFSTS : 1; /*!< [25..25] MTL TX Status FIFO Full Status */ + uint32_t : 6; + } Debug_b; + }; + + union + { + __IOM uint32_t Remote_Wake_Up_Frame_Filter; /*!< (@ 0x00000028) Remote Wake-Up Frame Filter Register */ + + struct + { + __IOM uint32_t WKUPFRMFTR : 32; /*!< [31..0] Remote Wake-Up Frame Filter */ + } Remote_Wake_Up_Frame_Filter_b; + }; + + union + { + __IOM uint32_t PMT_Control_Status; /*!< (@ 0x0000002C) PMT Control and Status Register */ + + struct + { + __IOM uint32_t PWRDWN : 1; /*!< [0..0] Power Down */ + __IOM uint32_t MGKPKTEN : 1; /*!< [1..1] Magic Packet Enable */ + __IOM uint32_t RWKPKTEN : 1; /*!< [2..2] Wake-Up Frame Enable */ + uint32_t : 2; + __IM uint32_t MGKPRCVD : 1; /*!< [5..5] Magic Packet Received */ + __IM uint32_t RWKPRCVD : 1; /*!< [6..6] Wake-Up Frame Received */ + uint32_t : 2; + __IOM uint32_t GLBLUCAST : 1; /*!< [9..9] Global Unicast */ + uint32_t : 14; + __IM uint32_t RWKPTR : 3; /*!< [26..24] Remote Wake-Up FIFO Pointer */ + uint32_t : 4; + __IOM uint32_t RWKFILTRST : 1; /*!< [31..31] Wake-Up Frame Filter Register Pointer Reset */ + } PMT_Control_Status_b; + }; + + union + { + __IOM uint32_t LPI_Control_Status; /*!< (@ 0x00000030) LPI Control and Status Register */ + + struct + { + __IM uint32_t TLPIEN : 1; /*!< [0..0] Transmit LPI Entry */ + __IM uint32_t TLPIEX : 1; /*!< [1..1] Transmit LPI Exit */ + __IM uint32_t RLPIEN : 1; /*!< [2..2] Receive LPI Entry */ + __IM uint32_t RLPIEX : 1; /*!< [3..3] Receive LPI Exit */ + uint32_t : 4; + __IM uint32_t TLPIST : 1; /*!< [8..8] Transmit LPI State */ + __IM uint32_t RLPIST : 1; /*!< [9..9] Receive LPI State */ + uint32_t : 6; + __IOM uint32_t LPIEN : 1; /*!< [16..16] LPI Enable */ + __IOM uint32_t PLS : 1; /*!< [17..17] PHY Link Status */ + uint32_t : 1; + __IOM uint32_t LPITXA : 1; /*!< [19..19] LPI TX Automate */ + uint32_t : 12; + } LPI_Control_Status_b; + }; + + union + { + __IOM uint32_t LPI_Timers_Control; /*!< (@ 0x00000034) LPI Timers Control Register */ + + struct + { + __IOM uint32_t TWT : 16; /*!< [15..0] LPI TW Timer */ + __IOM uint32_t LST : 10; /*!< [25..16] LPI LS Timer */ + uint32_t : 6; + } LPI_Timers_Control_b; + }; + + union + { + __IM uint32_t Interrupt_Status; /*!< (@ 0x00000038) Interrupt Status Register */ + + struct + { + uint32_t : 3; + __IM uint32_t PMTIS : 1; /*!< [3..3] PMT Interrupt Status */ + __IM uint32_t MMCIS : 1; /*!< [4..4] MMC Interrupt Status */ + __IM uint32_t MMCRXIS : 1; /*!< [5..5] MMC Receive Interrupt Status */ + __IM uint32_t MMCTXIS : 1; /*!< [6..6] MMC Transmit Interrupt Status */ + __IM uint32_t MMCRXIPIS : 1; /*!< [7..7] MMC Receive Checksum Offload Interrupt Status */ + uint32_t : 1; + __IM uint32_t TSIS : 1; /*!< [9..9] Timestamp Interrupt Status */ + __IM uint32_t LPIIS : 1; /*!< [10..10] LPI Interrupt Status */ + uint32_t : 21; + } Interrupt_Status_b; + }; + + union + { + __IOM uint32_t Interrupt_Mask; /*!< (@ 0x0000003C) Interrupt Mask Register */ + + struct + { + uint32_t : 3; + __IOM uint32_t PMTIM : 1; /*!< [3..3] PMT Interrupt Mask */ + uint32_t : 5; + __IOM uint32_t TSIM : 1; /*!< [9..9] Timestamp Interrupt Mask */ + __IOM uint32_t LPIIM : 1; /*!< [10..10] LPI Interrupt Mask */ + uint32_t : 21; + } Interrupt_Mask_b; + }; + + union + { + __IOM uint32_t MAR0_H; /*!< (@ 0x00000040) MAC Address 0 High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address0[47:32] */ + uint32_t : 15; + __IM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR0_H_b; + }; + + union + { + __IOM uint32_t MAR0_L; /*!< (@ 0x00000044) MAC Address 0 Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address0[31:0] */ + } MAR0_L_b; + }; + + union + { + __IOM uint32_t MAR1_H; /*!< (@ 0x00000048) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR1_H_b; + }; + + union + { + __IOM uint32_t MAR1_L; /*!< (@ 0x0000004C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR1_L_b; + }; + + union + { + __IOM uint32_t MAR2_H; /*!< (@ 0x00000050) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR2_H_b; + }; + + union + { + __IOM uint32_t MAR2_L; /*!< (@ 0x00000054) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR2_L_b; + }; + + union + { + __IOM uint32_t MAR3_H; /*!< (@ 0x00000058) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR3_H_b; + }; + + union + { + __IOM uint32_t MAR3_L; /*!< (@ 0x0000005C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR3_L_b; + }; + + union + { + __IOM uint32_t MAR4_H; /*!< (@ 0x00000060) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR4_H_b; + }; + + union + { + __IOM uint32_t MAR4_L; /*!< (@ 0x00000064) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR4_L_b; + }; + + union + { + __IOM uint32_t MAR5_H; /*!< (@ 0x00000068) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR5_H_b; + }; + + union + { + __IOM uint32_t MAR5_L; /*!< (@ 0x0000006C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR5_L_b; + }; + + union + { + __IOM uint32_t MAR6_H; /*!< (@ 0x00000070) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR6_H_b; + }; + + union + { + __IOM uint32_t MAR6_L; /*!< (@ 0x00000074) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR6_L_b; + }; + + union + { + __IOM uint32_t MAR7_H; /*!< (@ 0x00000078) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR7_H_b; + }; + + union + { + __IOM uint32_t MAR7_L; /*!< (@ 0x0000007C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR7_L_b; + }; + + union + { + __IOM uint32_t MAR8_H; /*!< (@ 0x00000080) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR8_H_b; + }; + + union + { + __IOM uint32_t MAR8_L; /*!< (@ 0x00000084) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR8_L_b; + }; + + union + { + __IOM uint32_t MAR9_H; /*!< (@ 0x00000088) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR9_H_b; + }; + + union + { + __IOM uint32_t MAR9_L; /*!< (@ 0x0000008C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR9_L_b; + }; + + union + { + __IOM uint32_t MAR10_H; /*!< (@ 0x00000090) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR10_H_b; + }; + + union + { + __IOM uint32_t MAR10_L; /*!< (@ 0x00000094) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR10_L_b; + }; + + union + { + __IOM uint32_t MAR11_H; /*!< (@ 0x00000098) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR11_H_b; + }; + + union + { + __IOM uint32_t MAR11_L; /*!< (@ 0x0000009C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR11_L_b; + }; + + union + { + __IOM uint32_t MAR12_H; /*!< (@ 0x000000A0) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR12_H_b; + }; + + union + { + __IOM uint32_t MAR12_L; /*!< (@ 0x000000A4) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR12_L_b; + }; + + union + { + __IOM uint32_t MAR13_H; /*!< (@ 0x000000A8) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR13_H_b; + }; + + union + { + __IOM uint32_t MAR13_L; /*!< (@ 0x000000AC) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR13_L_b; + }; + + union + { + __IOM uint32_t MAR14_H; /*!< (@ 0x000000B0) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR14_H_b; + }; + + union + { + __IOM uint32_t MAR14_L; /*!< (@ 0x000000B4) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR14_L_b; + }; + + union + { + __IOM uint32_t MAR15_H; /*!< (@ 0x000000B8) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR15_H_b; + }; + + union + { + __IOM uint32_t MAR15_L; /*!< (@ 0x000000BC) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR15_L_b; + }; + __IM uint32_t RESERVED1[7]; + + union + { + __IOM uint32_t WDog_Timeout; /*!< (@ 0x000000DC) Watchdog Timeout Register */ + + struct + { + __IOM uint32_t WTO : 14; /*!< [13..0] Watchdog Timeout */ + uint32_t : 2; + __IOM uint32_t PWE : 1; /*!< [16..16] Programmable Watchdog Enable */ + uint32_t : 15; + } WDog_Timeout_b; + }; + __IM uint32_t RESERVED2[8]; + + union + { + __IOM uint32_t MMC_Control; /*!< (@ 0x00000100) MMC Control Register */ + + struct + { + __IOM uint32_t CNTRST : 1; /*!< [0..0] Counters Reset */ + __IOM uint32_t CNTSTOPRO : 1; /*!< [1..1] Counters Stop Rollover */ + __IOM uint32_t RSTONRD : 1; /*!< [2..2] Reset on Read */ + __IOM uint32_t CNTFREEZ : 1; /*!< [3..3] MMC Counter Freeze */ + __IOM uint32_t CNTPRST : 1; /*!< [4..4] Counters Preset */ + __IOM uint32_t CNTPRSTLVL : 1; /*!< [5..5] Full-Half Preset */ + uint32_t : 2; + __IOM uint32_t UCDBC : 1; /*!< [8..8] Update MMC Counters for Dropped Broadcast Frames */ + uint32_t : 23; + } MMC_Control_b; + }; + + union + { + __IM uint32_t MMC_Receive_Interrupt; /*!< (@ 0x00000104) MMC Receive Interrupt Register */ + + struct + { + __IM uint32_t RXGBFRMIS : 1; /*!< [0..0] MMC Receive Good Bad Frame Counter Interrupt Status */ + __IM uint32_t RXGBOCTIS : 1; /*!< [1..1] MMC Receive Good Bad Octet Counter Interrupt Status */ + __IM uint32_t RXGOCTIS : 1; /*!< [2..2] MMC Receive Good Octet Counter Interrupt Status */ + __IM uint32_t RXBCGFIS : 1; /*!< [3..3] MMC Receive Broadcast Good Frame Counter Interrupt Status */ + __IM uint32_t RXMCGFIS : 1; /*!< [4..4] MMC Receive Multicast Good Frame Counter Interrupt Status */ + __IM uint32_t RXCRCERFIS : 1; /*!< [5..5] MMC Receive CRC Error Frame Counter Interrupt Status */ + __IM uint32_t RXALGNERFIS : 1; /*!< [6..6] MMC Receive Alignment Error Frame Counter Interrupt Status */ + __IM uint32_t RXRUNTFIS : 1; /*!< [7..7] MMC Receive Runt Frame Counter Interrupt Status */ + __IM uint32_t RXJABERFIS : 1; /*!< [8..8] MMC Receive Jabber Error Frame Counter Interrupt Status */ + __IM uint32_t RXUSIZEGFIS : 1; /*!< [9..9] MMC Receive Undersize Good Frame Counter Interrupt Status */ + __IM uint32_t RXOSIZEGFIS : 1; /*!< [10..10] MMC Receive Oversize Good Frame Counter Interrupt Status */ + __IM uint32_t RX64OCTGBFIS : 1; /*!< [11..11] MMC Receive 64 Octet Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t RX65T127OCTGBFIS : 1; /*!< [12..12] MMC Receive 65 to 127 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t RX128T255OCTGBFIS : 1; /*!< [13..13] MMC Receive 128 to 255 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t RX256T511OCTGBFIS : 1; /*!< [14..14] MMC Receive 256 to 511 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t RX512T1023OCTGBFIS : 1; /*!< [15..15] MMC Receive 512 to 1023 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t RX1024TMAXOCTGBFIS : 1; /*!< [16..16] MMC Receive 1024 to Maximum Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t RXUCGFIS : 1; /*!< [17..17] MMC Receive Unicast Good Frame Counter Interrupt Status */ + __IM uint32_t RXLENERFIS : 1; /*!< [18..18] MMC Receive Length Error Frame Counter Interrupt Status */ + __IM uint32_t RXORANGEFIS : 1; /*!< [19..19] MMC Receive Out Of Range Error Frame Counter Interrupt + * Status */ + __IM uint32_t RXPAUSFIS : 1; /*!< [20..20] MMC Receive Pause Frame Counter Interrupt Status */ + __IM uint32_t RXFOVFIS : 1; /*!< [21..21] MMC Receive FIFO Overflow Frame Counter Interrupt Status */ + __IM uint32_t RXVLANGBFIS : 1; /*!< [22..22] MMC Receive VLAN Good Bad Frame Counter Interrupt Status */ + __IM uint32_t RXWDOGFIS : 1; /*!< [23..23] MMC Receive Watchdog Error Frame Counter Interrupt + * Status */ + __IM uint32_t RXRCVERRFIS : 1; /*!< [24..24] MMC Receive Error Frame Counter Interrupt Status */ + __IM uint32_t RXCTRLFIS : 1; /*!< [25..25] MMC Receive Control Frame Counter Interrupt Status */ + uint32_t : 6; + } MMC_Receive_Interrupt_b; + }; + + union + { + __IM uint32_t MMC_Transmit_Interrupt; /*!< (@ 0x00000108) MMC Transmit Interrupt Register */ + + struct + { + __IM uint32_t TXGBOCTIS : 1; /*!< [0..0] MMC Transmit Good Bad Octet Counter Interrupt Status */ + __IM uint32_t TXGBFRMIS : 1; /*!< [1..1] MMC Transmit Good Bad Frame Counter Interrupt Status */ + __IM uint32_t TXBCGFIS : 1; /*!< [2..2] MMC Transmit Broadcast Good Frame Counter Interrupt Status */ + __IM uint32_t TXMCGFIS : 1; /*!< [3..3] MMC Transmit Multicast Good Frame Counter Interrupt Status */ + __IM uint32_t TX64OCTGBFIS : 1; /*!< [4..4] MMC Transmit 64 Octet Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t TX65T127OCTGBFIS : 1; /*!< [5..5] MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t TX128T255OCTGBFIS : 1; /*!< [6..6] MMC Transmit 128 to 255 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t TX256T511OCTGBFIS : 1; /*!< [7..7] MMC Transmit 256 to 511 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t TX512T1023OCTGBFIS : 1; /*!< [8..8] MMC Transmit 512 to 1023 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t TX1024TMAXOCTGBFIS : 1; /*!< [9..9] MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t TXUCGBFIS : 1; /*!< [10..10] MMC Transmit Unicast Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t TXMCGBFIS : 1; /*!< [11..11] MMC Transmit Multicast Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t TXBCGBFIS : 1; /*!< [12..12] MMC Transmit Broadcast Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t TXUFLOWERFIS : 1; /*!< [13..13] MMC Transmit Underflow Error Frame Counter Interrupt + * Status */ + __IM uint32_t TXSCOLGFIS : 1; /*!< [14..14] MMC Transmit Single Collision Good Frame Counter Interrupt + * Status */ + __IM uint32_t TXMCOLGFIS : 1; /*!< [15..15] MMC Transmit Multiple Collision Good Frame Counter + * Interrupt Status */ + __IM uint32_t TXDEFFIS : 1; /*!< [16..16] MMC Transmit Deferred Frame Counter Interrupt Status */ + __IM uint32_t TXLATCOLFIS : 1; /*!< [17..17] MMC Transmit Late Collision Frame Counter Interrupt + * Status */ + __IM uint32_t TXEXCOLFIS : 1; /*!< [18..18] MMC Transmit Excessive Collision Frame Counter Interrupt + * Status */ + __IM uint32_t TXCARERFIS : 1; /*!< [19..19] MMC Transmit Carrier Error Frame Counter Interrupt + * Status */ + __IM uint32_t TXGOCTIS : 1; /*!< [20..20] MMC Transmit Good Octet Counter Interrupt Status */ + __IM uint32_t TXGFRMIS : 1; /*!< [21..21] MMC Transmit Good Frame Counter Interrupt Status */ + __IM uint32_t TXEXDEFFIS : 1; /*!< [22..22] MMC Transmit Excessive Deferral Frame Counter Interrupt + * Status */ + __IM uint32_t TXPAUSFIS : 1; /*!< [23..23] MMC Transmit Pause Frame Counter Interrupt Status */ + __IM uint32_t TXVLANGFIS : 1; /*!< [24..24] MMC Transmit VLAN Good Frame Counter Interrupt Status */ + __IM uint32_t TXOSIZEGFIS : 1; /*!< [25..25] MMC Transmit Oversize Good Frame Counter Interrupt + * Status */ + uint32_t : 6; + } MMC_Transmit_Interrupt_b; + }; + + union + { + __IOM uint32_t MMC_Receive_Interrupt_Mask; /*!< (@ 0x0000010C) MMC Receive Interrupt Mask Register */ + + struct + { + __IOM uint32_t RXGBFRMIM : 1; /*!< [0..0] MMC Receive Good Bad Frame Counter Interrupt Mask */ + __IOM uint32_t RXGBOCTIM : 1; /*!< [1..1] MMC Receive Good Bad Octet Counter Interrupt Mask */ + __IOM uint32_t RXGOCTIM : 1; /*!< [2..2] MMC Receive Good Octet Counter Interrupt Mask */ + __IOM uint32_t RXBCGFIM : 1; /*!< [3..3] MMC Receive Broadcast Good Frame Counter Interrupt Mask */ + __IOM uint32_t RXMCGFIM : 1; /*!< [4..4] MMC Receive Multicast Good Frame Counter Interrupt Mask */ + __IOM uint32_t RXCRCERFIM : 1; /*!< [5..5] MMC Receive CRC Error Frame Counter Interrupt Mask */ + __IOM uint32_t RXALGNERFIM : 1; /*!< [6..6] MMC Receive Alignment Error Frame Counter Interrupt Mask */ + __IOM uint32_t RXRUNTFIM : 1; /*!< [7..7] MMC Receive Runt Frame Counter Interrupt Mask */ + __IOM uint32_t RXJABERFIM : 1; /*!< [8..8] MMC Receive Jabber Error Frame Counter Interrupt Mask */ + __IOM uint32_t RXUSIZEGFIM : 1; /*!< [9..9] MMC Receive Undersize Good Frame Counter Interrupt Mask */ + __IOM uint32_t RXOSIZEGFIM : 1; /*!< [10..10] MMC Receive Oversize Good Frame Counter Interrupt Mask */ + __IOM uint32_t RX64OCTGBFIM : 1; /*!< [11..11] MMC Receive 64 Octet Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t RX65T127OCTGBFIM : 1; /*!< [12..12] MMC Receive 65 to 127 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t RX128T255OCTGBFIM : 1; /*!< [13..13] MMC Receive 128 to 255 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t RX256T511OCTGBFIM : 1; /*!< [14..14] MMC Receive 256 to 511 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t RX512T1023OCTGBFIM : 1; /*!< [15..15] MMC Receive 512 to 1023 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t RX1024TMAXOCTGBFIM : 1; /*!< [16..16] MMC Receive 1024 to Maximum Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t RXUCGFIM : 1; /*!< [17..17] MMC Receive Unicast Good Frame Counter Interrupt Mask */ + __IOM uint32_t RXLENERFIM : 1; /*!< [18..18] MMC Receive Length Error Frame Counter Interrupt Mask */ + __IOM uint32_t RXORANGEFIM : 1; /*!< [19..19] MMC Receive Out Of Range Error Frame Counter Interrupt + * Mask */ + __IOM uint32_t RXPAUSFIM : 1; /*!< [20..20] MMC Receive Pause Frame Counter Interrupt Mask */ + __IOM uint32_t RXFOVFIM : 1; /*!< [21..21] MMC Receive FIFO Overflow Frame Counter Interrupt Mask */ + __IOM uint32_t RXVLANGBFIM : 1; /*!< [22..22] MMC Receive VLAN Good Bad Frame Counter Interrupt Mask */ + __IOM uint32_t RXWDOGFIM : 1; /*!< [23..23] MMC Receive Watchdog Error Frame Counter Interrupt + * Mask */ + __IOM uint32_t RXRCVERRFIM : 1; /*!< [24..24] MMC Receive Error Frame Counter Interrupt Mask */ + __IOM uint32_t RXCTRLFIM : 1; /*!< [25..25] MMC Receive Control Frame Counter Interrupt Mask */ + uint32_t : 6; + } MMC_Receive_Interrupt_Mask_b; + }; + + union + { + __IOM uint32_t MMC_Transmit_Interrupt_Mask; /*!< (@ 0x00000110) MMC Transmit Interrupt Mask Register */ + + struct + { + __IOM uint32_t TXGBOCTIM : 1; /*!< [0..0] MMC Transmit Good Bad Octet Counter Interrupt Mask */ + __IOM uint32_t TXGBFRMIM : 1; /*!< [1..1] MMC Transmit Good Bad Frame Counter Interrupt Mask */ + __IOM uint32_t TXBCGFIM : 1; /*!< [2..2] MMC Transmit Broadcast Good Frame Counter Interrupt Mask */ + __IOM uint32_t TXMCGFIM : 1; /*!< [3..3] MMC Transmit Multicast Good Frame Counter Interrupt Mask */ + __IOM uint32_t TX64OCTGBFIM : 1; /*!< [4..4] MMC Transmit 64 Octet Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t TX65T127OCTGBFIM : 1; /*!< [5..5] MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t TX128T255OCTGBFIM : 1; /*!< [6..6] MMC Transmit 128 to 255 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t TX256T511OCTGBFIM : 1; /*!< [7..7] MMC Transmit 256 to 511 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t TX512T1023OCTGBFIM : 1; /*!< [8..8] MMC Transmit 512 to 1023 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t TX1024TMAXOCTGBFIM : 1; /*!< [9..9] MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t TXUCGBFIM : 1; /*!< [10..10] MMC Transmit Unicast Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXMCGBFIM : 1; /*!< [11..11] MMC Transmit Multicast Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXBCGBFIM : 1; /*!< [12..12] MMC Transmit Broadcast Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXUFLOWERFIM : 1; /*!< [13..13] MMC Transmit Underflow Error Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXSCOLGFIM : 1; /*!< [14..14] MMC Transmit Single Collision Good Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXMCOLGFIM : 1; /*!< [15..15] MMC Transmit Multiple Collision Good Frame Counter + * Interrupt Mask */ + __IOM uint32_t TXDEFFIM : 1; /*!< [16..16] MMC Transmit Deferred Frame Counter Interrupt Mask */ + __IOM uint32_t TXLATCOLFIM : 1; /*!< [17..17] MMC Transmit Late Collision Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXEXCOLFIM : 1; /*!< [18..18] MMC Transmit Excessive Collision Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXCARERFIM : 1; /*!< [19..19] MMC Transmit Carrier Error Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXGOCTIM : 1; /*!< [20..20] MMC Transmit Good Octet Counter Interrupt Mask */ + __IOM uint32_t TXGFRMIM : 1; /*!< [21..21] MMC Transmit Good Frame Counter Interrupt Mask */ + __IOM uint32_t TXEXDEFFIM : 1; /*!< [22..22] MMC Transmit Excessive Deferral Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXPAUSFIM : 1; /*!< [23..23] MMC Transmit Pause Frame Counter Interrupt Mask */ + __IOM uint32_t TXVLANGFIM : 1; /*!< [24..24] MMC Transmit VLAN Good Frame Counter Interrupt Mask */ + __IOM uint32_t TXOSIZEGFIM : 1; /*!< [25..25] MMC Transmit Oversize Good Frame Counter Interrupt + * Mask */ + uint32_t : 6; + } MMC_Transmit_Interrupt_Mask_b; + }; + + union + { + __IM uint32_t Tx_Octet_Count_Good_Bad; /*!< (@ 0x00000114) Transmit Octet Count for Good and Bad Frames */ + + struct + { + __IM uint32_t TXOCTGB : 32; /*!< [31..0] This field indicates the number of bytes transmitted + * in good and bad frames exclusive of preamble and retried + * bytes. */ + } Tx_Octet_Count_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Frame_Count_Good_Bad; /*!< (@ 0x00000118) Transmit Frame Count for Good and Bad Frames */ + + struct + { + __IM uint32_t TXFRMGB : 32; /*!< [31..0] This field indicates the number of good and bad frames + * transmitted, exclusive of retried frames. */ + } Tx_Frame_Count_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Broadcast_Frames_Good; /*!< (@ 0x0000011C) Transmit Frame Count for Good Broadcast Frames */ + + struct + { + __IM uint32_t TXBCASTG : 32; /*!< [31..0] This field indicates the number of transmitted good + * broadcast frames. */ + } Tx_Broadcast_Frames_Good_b; + }; + + union + { + __IM uint32_t Tx_Multicast_Frames_Good; /*!< (@ 0x00000120) Transmit Frame Count for Good Multicast Frames */ + + struct + { + __IM uint32_t TXMCASTG : 32; /*!< [31..0] This field indicates the number of transmitted good + * multicast frames. */ + } Tx_Multicast_Frames_Good_b; + }; + + union + { + __IM uint32_t Tx_64Octets_Frames_Good_Bad; /*!< (@ 0x00000124) Transmit Octet Count for Good and Bad 64 Byte + * Frames */ + + struct + { + __IM uint32_t TX64OCTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad frames with length of 64 bytes, exclusive of preamble + * and retried frames. */ + } Tx_64Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_65To127Octets_Frames_Good_Bad; /*!< (@ 0x00000128) Transmit Octet Count for Good and Bad 65 to 127 + * Bytes Frames */ + + struct + { + __IM uint32_t TX65_127OCTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad frames with length between 65 and 127 (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Tx_65To127Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_128To255Octets_Frames_Good_Bad; /*!< (@ 0x0000012C) Transmit Octet Count for Good and Bad 128 to + * 255 Bytes Frames */ + + struct + { + __IM uint32_t TX128_255OCTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad frames with length between 128 and 255 (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Tx_128To255Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_256To511Octets_Frames_Good_Bad; /*!< (@ 0x00000130) Transmit Octet Count for Good and Bad 256 to + * 511 Bytes Frames */ + + struct + { + __IM uint32_t TX256_511OCTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad frames with length between 256 and 511 (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Tx_256To511Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_512To1023Octets_Frames_Good_Bad; /*!< (@ 0x00000134) Transmit Octet Count for Good and Bad 512 to + * 1023 Bytes Frames */ + + struct + { + __IM uint32_t TX512_1023OCTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad frames with length between 512 and 1,023 (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Tx_512To1023Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_1024ToMaxOctets_Frames_Good_Bad; /*!< (@ 0x00000138) Transmit Octet Count for Good and Bad 1024 to + * Maxsize Bytes Frames */ + + struct + { + __IM uint32_t TX1024_MAXOCTGB : 32; /*!< [31..0] This field indicates the number of good and bad frames + * transmitted with length between 1,024 and maxsize (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Tx_1024ToMaxOctets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Unicast_Frames_Good_Bad; /*!< (@ 0x0000013C) Transmit Frame Count for Good and Bad Unicast + * Frames */ + + struct + { + __IM uint32_t TXUCASTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad unicast frames. */ + } Tx_Unicast_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Multicast_Frames_Good_Bad; /*!< (@ 0x00000140) Transmit Frame Count for Good and Bad Multicast + * Frames */ + + struct + { + __IM uint32_t TXMCASTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad multicast frames. */ + } Tx_Multicast_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Broadcast_Frames_Good_Bad; /*!< (@ 0x00000144) Transmit Frame Count for Good and Bad Broadcast + * Frames */ + + struct + { + __IM uint32_t TXBCASTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad broadcast frames. */ + } Tx_Broadcast_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Underflow_Error_Frames; /*!< (@ 0x00000148) Transmit Frame Count for Underflow Error Frames */ + + struct + { + __IM uint32_t TXUNDRFLW : 16; /*!< [15..0] This field indicates the number of frames aborted because + * of frame underflow error. */ + uint32_t : 16; + } Tx_Underflow_Error_Frames_b; + }; + + union + { + __IM uint32_t Tx_Single_Collision_Good_Frames; /*!< (@ 0x0000014C) Transmit Frame Count for Frames Transmitted after + * Single Collision */ + + struct + { + __IM uint32_t TXSNGLCOLG : 16; /*!< [15..0] This field indicates the number of successfully transmitted + * frames after a single collision in the half-duplex mode. */ + uint32_t : 16; + } Tx_Single_Collision_Good_Frames_b; + }; + + union + { + __IM uint32_t Tx_Multiple_Collision_Good_Frames; /*!< (@ 0x00000150) Transmit Frame Count for Frames Transmitted after + * Multiple Collision */ + + struct + { + __IM uint32_t TXMULTCOLG : 16; /*!< [15..0] This field indicates the number of successfully transmitted + * frames after multiple collisions in the half-duplex mode. */ + uint32_t : 16; + } Tx_Multiple_Collision_Good_Frames_b; + }; + + union + { + __IM uint32_t Tx_Deferred_Frames; /*!< (@ 0x00000154) Transmit Frame Count for Deferred Frames */ + + struct + { + __IM uint32_t TXDEFRD : 16; /*!< [15..0] This field indicates the number of successfully transmitted + * frames after a deferral in the half-duplex mode. */ + uint32_t : 16; + } Tx_Deferred_Frames_b; + }; + + union + { + __IM uint32_t Tx_Late_Collision_Frames; /*!< (@ 0x00000158) Transmit Frame Count for Late Collision Error + * Frames */ + + struct + { + __IM uint32_t TXLATECOL : 16; /*!< [15..0] This field indicates the number of frames aborted because + * of late collision error. */ + uint32_t : 16; + } Tx_Late_Collision_Frames_b; + }; + + union + { + __IM uint32_t Tx_Excessive_Collision_Frames; /*!< (@ 0x0000015C) Transmit Frame Count for Excessive Collision + * Error Frames */ + + struct + { + __IM uint32_t TXEXSCOL : 16; /*!< [15..0] This field indicates the number of frames aborted because + * of excessive (16) collision error. */ + uint32_t : 16; + } Tx_Excessive_Collision_Frames_b; + }; + + union + { + __IM uint32_t Tx_Carrier_Error_Frames; /*!< (@ 0x00000160) Transmit Frame Count for Carrier Sense Error + * Frames */ + + struct + { + __IM uint32_t TXCARR : 16; /*!< [15..0] This field indicates the number of frames aborted because + * of carrier sense error (no carrier or loss of carrier). */ + uint32_t : 16; + } Tx_Carrier_Error_Frames_b; + }; + + union + { + __IM uint32_t Tx_Octet_Count_Good; /*!< (@ 0x00000164) Transmit Octet Count for Good Frames */ + + struct + { + __IM uint32_t TXOCTG : 32; /*!< [31..0] TXOCTG */ + } Tx_Octet_Count_Good_b; + }; + + union + { + __IM uint32_t Tx_Frame_Count_Good; /*!< (@ 0x00000168) Transmit Frame Count for Good Frames */ + + struct + { + __IM uint32_t TXFRMG : 32; /*!< [31..0] This field indicates the number of transmitted good + * frames, exclusive of preamble. */ + } Tx_Frame_Count_Good_b; + }; + + union + { + __IM uint32_t Tx_Excessive_Deferral_Error; /*!< (@ 0x0000016C) Transmit Frame Count for Excessive Deferral Error + * Frames */ + + struct + { + __IM uint32_t TXEXSDEF : 16; /*!< [15..0] This field indicates the number of frames aborted because + * of excessive deferral error, that is, frames deferred for + * more than two max sized frame times. */ + uint32_t : 16; + } Tx_Excessive_Deferral_Error_b; + }; + + union + { + __IM uint32_t Tx_Pause_Frames; /*!< (@ 0x00000170) Transmit Frame Count for Good PAUSE Frames */ + + struct + { + __IM uint32_t TXPAUSE : 16; /*!< [15..0] This field indicates the number of transmitted good + * PAUSE frames. */ + uint32_t : 16; + } Tx_Pause_Frames_b; + }; + + union + { + __IM uint32_t Tx_VLAN_Frames_Good; /*!< (@ 0x00000174) Transmit Frame Count for Good VLAN Frames */ + + struct + { + __IM uint32_t TXVLANG : 32; /*!< [31..0] This register maintains the number of transmitted good + * VLAN frames, exclusive of retried frames. */ + } Tx_VLAN_Frames_Good_b; + }; + + union + { + __IM uint32_t Tx_OSize_Frames_Good; /*!< (@ 0x00000178) Transmit Frame Count for Good Oversize Frames */ + + struct + { + __IM uint32_t TXOSIZG : 16; /*!< [15..0] This field indicates the number of frames transmitted + * without errors and with length greater than the maxsize + * (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes + * if enabled in bit [27] of MAC Configuration Register (MAC_Configuration)) + */ + uint32_t : 16; + } Tx_OSize_Frames_Good_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t Rx_Frames_Count_Good_Bad; /*!< (@ 0x00000180) Receive Frame Count for Good and Bad Frames */ + + struct + { + __IM uint32_t RXFRMGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames. */ + } Rx_Frames_Count_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_Octet_Count_Good_Bad; /*!< (@ 0x00000184) Receive Octet Count for Good and Bad Frames */ + + struct + { + __IM uint32_t RXOCTGB : 32; /*!< [31..0] This field indicates the number of bytes received, exclusive + * of preamble, in good and bad frames. */ + } Rx_Octet_Count_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_Octet_Count_Good; /*!< (@ 0x00000188) Receive Octet Count for Good Frames */ + + struct + { + __IM uint32_t RXOCTG : 32; /*!< [31..0] This field indicates the number of bytes received, exclusive + * of preamble, only in good frames. */ + } Rx_Octet_Count_Good_b; + }; + + union + { + __IM uint32_t Rx_Broadcast_Frames_Good; /*!< (@ 0x0000018C) Receive Frame Count for Good Broadcast Frames */ + + struct + { + __IM uint32_t RXBCASTG : 32; /*!< [31..0] This field indicates the number of received good broadcast + * frames. */ + } Rx_Broadcast_Frames_Good_b; + }; + + union + { + __IM uint32_t Rx_Multicast_Frames_Good; /*!< (@ 0x00000190) Receive Frame Count for Good Multicast Frames */ + + struct + { + __IM uint32_t RXMCASTG : 32; /*!< [31..0] This field indicates the number of received good multicast + * frames. */ + } Rx_Multicast_Frames_Good_b; + }; + + union + { + __IM uint32_t Rx_CRC_Error_Frames; /*!< (@ 0x00000194) Receive Frame Count for CRC Error Frames */ + + struct + { + __IM uint32_t RXCRCERR : 16; /*!< [15..0] This field indicates the number of frames received with + * CRC error. */ + uint32_t : 16; + } Rx_CRC_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Alignment_Error_Frames; /*!< (@ 0x00000198) Receive Frame Count for Alignment Error Frames */ + + struct + { + __IM uint32_t RXALGNERR : 16; /*!< [15..0] This field indicates the number of frames received with + * alignment (dribble) error. This field is valid only in + * the 10 or 100 Mbps mode. */ + uint32_t : 16; + } Rx_Alignment_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Runt_Error_Frames; /*!< (@ 0x0000019C) Receive Frame Count for Runt Error Frames */ + + struct + { + __IM uint32_t RXRUNTERR : 16; /*!< [15..0] This field indicates the number of frames received with + * runt error (< 64 bytes and CRC error). */ + uint32_t : 16; + } Rx_Runt_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Jabber_Error_Frames; /*!< (@ 0x000001A0) Receive Frame Count for Jabber Error Frames */ + + struct + { + __IM uint32_t RXJABERR : 16; /*!< [15..0] This field indicates the number of giant frames received + * with length (including CRC) greater than 1,518 bytes (1,522 + * bytes for VLAN tagged) and with CRC error. If Jumbo Frame + * mode is enabled, then frames of length greater than 9,018 + * bytes (9,022 for VLAN tagged) are considered as giant frames. */ + uint32_t : 16; + } Rx_Jabber_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Undersize_Frames_Good; /*!< (@ 0x000001A4) Receive Frame Count for Undersize Frames */ + + struct + { + __IM uint32_t RXUNDERSZG : 16; /*!< [15..0] This field indicates the number of frames received with + * length less than 64 bytes and without errors. */ + uint32_t : 16; + } Rx_Undersize_Frames_Good_b; + }; + + union + { + __IM uint32_t Rx_Oversize_Frames_Good; /*!< (@ 0x000001A8) Receive Frame Count for Oversize Frames */ + + struct + { + __IM uint32_t RXOVERSZG : 16; /*!< [15..0] This field indicates the number of frames received without + * errors, with length greater than the maxsize (1,518 or + * 1,522 for VLAN tagged frames; 2,000 bytes if enabled in + * bit [27] of MAC Configuration Register (MAC_Configuration)). */ + uint32_t : 16; + } Rx_Oversize_Frames_Good_b; + }; + + union + { + __IM uint32_t Rx_64Octets_Frames_Good_Bad; /*!< (@ 0x000001AC) Receive Frame Count for Good and Bad 64 Byte + * Frames */ + + struct + { + __IM uint32_t RX64OCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames with length 64 bytes, exclusive of preamble. */ + } Rx_64Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_65To127Octets_Frames_Good_Bad; /*!< (@ 0x000001B0) Receive Frame Count for Good and Bad 65 to 127 + * Bytes Frames */ + + struct + { + __IM uint32_t RX65_127OCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames received with length between 65 and 127 (inclusive) + * bytes, exclusive of preamble. */ + } Rx_65To127Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_128To255Octets_Frames_Good_Bad; /*!< (@ 0x000001B4) Receive Frame Count for Good and Bad 128 to 255 + * Bytes Frames */ + + struct + { + __IM uint32_t RX128_255OCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames with length between 128 and 255 (inclusive) + * bytes, exclusive of preamble. */ + } Rx_128To255Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_256To511Octets_Frames_Good_Bad; /*!< (@ 0x000001B8) Receive Frame Count for Good and Bad 256 to 511 + * Bytes Frames */ + + struct + { + __IM uint32_t RX256_511OCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames with length between 256 and 511 (inclusive) + * bytes, exclusive of preamble. */ + } Rx_256To511Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_512To1023Octets_Frames_Good_Bad; /*!< (@ 0x000001BC) Receive Frame Count for Good and Bad 512 to 1,023 + * Bytes Frames */ + + struct + { + __IM uint32_t RX512_1023OCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames with length between 512 and 1,023 (inclusive) + * bytes, exclusive of preamble. */ + } Rx_512To1023Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_1024ToMaxOctets_Frames_Good_Bad; /*!< (@ 0x000001C0) Receive Frame Count for Good and Bad 1,024 to + * Maxsize Bytes Frames */ + + struct + { + __IM uint32_t RX1024_MAXOCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames with length between 1,024 and maxsize (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Rx_1024ToMaxOctets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_Unicast_Frames_Good; /*!< (@ 0x000001C4) Receive Frame Count for Good Unicast Frames */ + + struct + { + __IM uint32_t RXUCASTG : 32; /*!< [31..0] This field indicates the number of received good unicast + * frames. */ + } Rx_Unicast_Frames_Good_b; + }; + + union + { + __IM uint32_t Rx_Length_Error_Frames; /*!< (@ 0x000001C8) Receive Frame Count for Length Error Frames */ + + struct + { + __IM uint32_t RXLENERR : 16; /*!< [15..0] RXLENERR */ + uint32_t : 16; + } Rx_Length_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Out_Of_Range_Type_Frames; /*!< (@ 0x000001CC) Receive Frame Count for Out of Range Frames */ + + struct + { + __IM uint32_t RXOUTOFRNG : 16; /*!< [15..0] This field indicates the number of received frames with + * length field not equal to the valid frame size (greater + * than 1,500 but less than 1,536). */ + uint32_t : 16; + } Rx_Out_Of_Range_Type_Frames_b; + }; + + union + { + __IM uint32_t Rx_Pause_Frames; /*!< (@ 0x000001D0) Receive Frame Count for PAUSE Frames */ + + struct + { + __IM uint32_t RXPAUSEFRM : 16; /*!< [15..0] This field indicates the number of received good and + * valid PAUSE frames. */ + uint32_t : 16; + } Rx_Pause_Frames_b; + }; + + union + { + __IM uint32_t Rx_FIFO_Overflow_Frames; /*!< (@ 0x000001D4) Receive Frame Count for FIFO Overflow Frames */ + + struct + { + __IM uint32_t RXFIFOOVFL : 16; /*!< [15..0] This field indicates the number of received frames missed + * because of FIFO overflow. */ + uint32_t : 16; + } Rx_FIFO_Overflow_Frames_b; + }; + + union + { + __IM uint32_t Rx_VLAN_Frames_Good_Bad; /*!< (@ 0x000001D8) Receive Frame Count for Good and Bad VLAN Frames */ + + struct + { + __IM uint32_t RXVLANFRGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad VLAN frames. */ + } Rx_VLAN_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_Watchdog_Error_Frames; /*!< (@ 0x000001DC) Receive Frame Count for Watchdog Error Frames */ + + struct + { + __IM uint32_t RXWDGERR : 16; /*!< [15..0] This field indicates the number of frames received with + * error because of the watchdog timeout error (frames with + * more than 2,048 bytes or value programmed in Watchdog Timeout + * Register (WDog_Timeout)). */ + uint32_t : 16; + } Rx_Watchdog_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Receive_Error_Frames; /*!< (@ 0x000001E0) Receive Frame Count for Receive Error Frames */ + + struct + { + __IM uint32_t RXRCVERR : 16; /*!< [15..0] This field indicates the number of frames received with + * error because of the GMII/MII RXER error or Frame Extension + * error on GMII. */ + uint32_t : 16; + } Rx_Receive_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Control_Frames_Good; /*!< (@ 0x000001E4) Receive Frame Count for Good Control Frames */ + + struct + { + __IM uint32_t RXCTRLG : 32; /*!< [31..0] This field indicates the number of good control frames + * received. */ + } Rx_Control_Frames_Good_b; + }; + __IM uint32_t RESERVED4[134]; + + union + { + __IOM uint32_t GMACTRGSEL; /*!< (@ 0x00000400) GMAC PTP Trigger Select Register */ + + struct + { + __IOM uint32_t TRGSEL : 2; /*!< [1..0] Select PTP Timestamp Trigger for GMAC IP */ + uint32_t : 30; + } GMACTRGSEL_b; + }; + __IM uint32_t RESERVED5[63]; + + union + { + __IOM uint32_t HASH_TABLE_REG[8]; /*!< (@ 0x00000500) Hash Table Register [0..7] (n = 0 to 7) */ + + struct + { + __IOM uint32_t HT : 32; /*!< [31..0] This field contains the nth 32 bits [31:0] of the Hash + * table. */ + } HASH_TABLE_REG_b[8]; + }; + __IM uint32_t RESERVED6[26]; + + union + { + __IOM uint32_t VLAN_Hash_Table_Reg; /*!< (@ 0x00000588) VLAN Hash Table Register */ + + struct + { + __IOM uint32_t VLHT : 16; /*!< [15..0] VLAN Hash Table */ + uint32_t : 16; + } VLAN_Hash_Table_Reg_b; + }; + __IM uint32_t RESERVED7[93]; + + union + { + __IOM uint32_t Timestamp_Control; /*!< (@ 0x00000700) Timestamp Control Register */ + + struct + { + __IOM uint32_t TSENA : 1; /*!< [0..0] Timestamp Enable */ + uint32_t : 7; + __IOM uint32_t TSENALL : 1; /*!< [8..8] Enable Timestamp for all Frames */ + __IOM uint32_t TSCTRLSSR : 1; /*!< [9..9] Timestamp Digital or Binary Rollover Control */ + __IOM uint32_t TSVER2ENA : 1; /*!< [10..10] Enable PTP packet Processing for Version 2 Format */ + __IOM uint32_t TSIPENA : 1; /*!< [11..11] Enable Processing of PTP over Ethernet Frames */ + __IOM uint32_t TSIPV6ENA : 1; /*!< [12..12] Enable Processing of PTP Frames Sent Over IPv6 UDP */ + __IOM uint32_t TSIPV4ENA : 1; /*!< [13..13] Enable Processing of PTP Frames Sent over IPv4 UDP */ + __IOM uint32_t TSEVNTENA : 1; /*!< [14..14] Enable Timestamp Snapshot for Event Messages */ + __IOM uint32_t TSMSTRENA : 1; /*!< [15..15] Enable Snapshot for Messages Relevant to Master */ + __IOM uint32_t SNAPTYPSEL : 2; /*!< [17..16] Select PTP packets for Taking Snapshots */ + __IOM uint32_t TSENMACADDR : 1; /*!< [18..18] Enable MAC address for PTP Frame Filtering */ + uint32_t : 5; + __IOM uint32_t ATSFC : 1; /*!< [24..24] Auxiliary Snapshot FIFO Clear */ + __IOM uint32_t ATSEN0 : 1; /*!< [25..25] Auxiliary Snapshot 0 Enable */ + __IOM uint32_t ATSEN1 : 1; /*!< [26..26] Auxiliary Snapshot 1 Enable */ + uint32_t : 5; + } Timestamp_Control_b; + }; + __IM uint32_t RESERVED8[9]; + + union + { + __IM uint32_t Timestamp_Status; /*!< (@ 0x00000728) Timestamp Status Register */ + + struct + { + uint32_t : 2; + __IM uint32_t AUXTSTRIG : 1; /*!< [2..2] Auxiliary Timestamp Trigger Snapshot */ + uint32_t : 13; + __IM uint32_t ATSSTN : 4; /*!< [19..16] Auxiliary Timestamp Snapshot Trigger Identifier */ + uint32_t : 4; + __IM uint32_t ATSSTM : 1; /*!< [24..24] Auxiliary Timestamp Snapshot Trigger Missed */ + __IM uint32_t ATSNS : 5; /*!< [29..25] Number of Auxiliary Timestamp Snapshots */ + uint32_t : 2; + } Timestamp_Status_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IM uint32_t Auxiliary_Timestamp_Nanoseconds; /*!< (@ 0x00000730) Auxiliary Timestamp - Nanoseconds Register */ + + struct + { + __IM uint32_t AUXTSLO : 31; /*!< [30..0] Contains the lower 32 bits (nanoseconds field) of the + * auxiliary timestamp. */ + uint32_t : 1; + } Auxiliary_Timestamp_Nanoseconds_b; + }; + + union + { + __IM uint32_t Auxiliary_Timestamp_Seconds; /*!< (@ 0x00000734) Auxiliary Timestamp - Seconds Register */ + + struct + { + __IM uint32_t AUXTSHI : 32; /*!< [31..0] Contains the upper 32 bits (Seconds field) of the auxiliary + * timestamp. */ + } Auxiliary_Timestamp_Seconds_b; + }; + __IM uint32_t RESERVED10[50]; + + union + { + __IOM uint32_t MAR16_H; /*!< (@ 0x00000800) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR16_H_b; + }; + + union + { + __IOM uint32_t MAR16_L; /*!< (@ 0x00000804) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR16_L_b; + }; + + union + { + __IOM uint32_t MAR17_H; /*!< (@ 0x00000808) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR17_H_b; + }; + + union + { + __IOM uint32_t MAR17_L; /*!< (@ 0x0000080C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR17_L_b; + }; + __IM uint32_t RESERVED11[508]; + + union + { + __IOM uint32_t Bus_Mode; /*!< (@ 0x00001000) Bus Mode Register */ + + struct + { + __IOM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + __IM uint32_t DA : 1; /*!< [1..1] DMA Arbitration Scheme */ + __IOM uint32_t DSL : 5; /*!< [6..2] Descriptor Skip Length */ + __IOM uint32_t ATDS : 1; /*!< [7..7] Enhanced Descriptor Size */ + __IOM uint32_t PBL : 6; /*!< [13..8] Programmable Burst Length */ + __IM uint32_t PR : 2; /*!< [15..14] Priority Ratio */ + __IOM uint32_t FB : 1; /*!< [16..16] Fixed Burst */ + __IOM uint32_t RPBL : 6; /*!< [22..17] RX DMA PBL */ + __IOM uint32_t USP : 1; /*!< [23..23] Use Separate PBL */ + __IOM uint32_t PBLx8 : 1; /*!< [24..24] PBLx8 Mode */ + __IOM uint32_t AAL : 1; /*!< [25..25] Address Aligned Beats */ + __IM uint32_t MB : 1; /*!< [26..26] Mixed Burst */ + __IM uint32_t TXPR : 1; /*!< [27..27] Transmit Priority */ + __IM uint32_t PRWG : 2; /*!< [29..28] Channel Priority Weights */ + uint32_t : 1; + __IM uint32_t RIB : 1; /*!< [31..31] Rebuild INCRx Burst */ + } Bus_Mode_b; + }; + + union + { + __IOM uint32_t Transmit_Poll_Demand; /*!< (@ 0x00001004) Transmit Poll Demand Register */ + + struct + { + __IOM uint32_t TPD : 32; /*!< [31..0] Transmit Poll Demand */ + } Transmit_Poll_Demand_b; + }; + + union + { + __IOM uint32_t Receive_Poll_Demand; /*!< (@ 0x00001008) Receive Poll Demand Register */ + + struct + { + __IOM uint32_t RPD : 32; /*!< [31..0] Receive Poll Demand */ + } Receive_Poll_Demand_b; + }; + + union + { + __IOM uint32_t Receive_Descriptor_List_Address; /*!< (@ 0x0000100C) Receive Descriptor List Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t RDESLA_32bit : 30; /*!< [31..2] Start of Receive List */ + } Receive_Descriptor_List_Address_b; + }; + + union + { + __IOM uint32_t Transmit_Descriptor_List_Address; /*!< (@ 0x00001010) Transmit Descriptor List Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t TDESLA_32bit : 30; /*!< [31..2] Start of Transmit List */ + } Transmit_Descriptor_List_Address_b; + }; + + union + { + __IOM uint32_t Status; /*!< (@ 0x00001014) Status Register */ + + struct + { + __IOM uint32_t TI : 1; /*!< [0..0] Transmit Interrupt */ + __IOM uint32_t TPS : 1; /*!< [1..1] Transmit Process Stopped */ + __IOM uint32_t TU : 1; /*!< [2..2] Transmit Buffer Unavailable */ + __IOM uint32_t TJT : 1; /*!< [3..3] Transmit Jabber Timeout */ + __IOM uint32_t OVF : 1; /*!< [4..4] Receive Overflow */ + __IOM uint32_t UNF : 1; /*!< [5..5] Transmit Underflow */ + __IOM uint32_t RI : 1; /*!< [6..6] Receive Interrupt */ + __IOM uint32_t RU : 1; /*!< [7..7] Receive Buffer Unavailable */ + __IOM uint32_t RPS : 1; /*!< [8..8] Receive Process Stopped */ + __IOM uint32_t RWT : 1; /*!< [9..9] Receive Watchdog Timeout */ + __IOM uint32_t ETI : 1; /*!< [10..10] Early Transmit Interrupt */ + uint32_t : 2; + __IOM uint32_t FBI : 1; /*!< [13..13] Fatal Bus Error Interrupt */ + __IOM uint32_t ERI : 1; /*!< [14..14] Early Receive Interrupt */ + __IOM uint32_t AIS : 1; /*!< [15..15] Abnormal Interrupt Summary */ + __IOM uint32_t NIS : 1; /*!< [16..16] Normal Interrupt Summary */ + __IM uint32_t RS : 3; /*!< [19..17] Received Process State */ + __IM uint32_t TS : 3; /*!< [22..20] Transmit Process State */ + __IM uint32_t EB : 3; /*!< [25..23] Error Bits */ + uint32_t : 1; + __IM uint32_t GMI : 1; /*!< [27..27] GMAC MMC Interrupt */ + __IM uint32_t GPI : 1; /*!< [28..28] GMAC PMT Interrupt */ + __IM uint32_t TTI : 1; /*!< [29..29] Timestamp Trigger Interrupt */ + __IM uint32_t GLPII : 1; /*!< [30..30] GMAC LPI Interrupt */ + uint32_t : 1; + } Status_b; + }; + + union + { + __IOM uint32_t Operation_Mode; /*!< (@ 0x00001018) Operation Mode Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t SR : 1; /*!< [1..1] Start or Stop Receive */ + __IOM uint32_t OSF : 1; /*!< [2..2] Operate on Second Frame */ + __IOM uint32_t RTC : 2; /*!< [4..3] Receive Threshold Control */ + __IOM uint32_t DGF : 1; /*!< [5..5] Drop Giant Frames */ + __IOM uint32_t FUF : 1; /*!< [6..6] Forward Undersized Good Frames */ + __IOM uint32_t FEF : 1; /*!< [7..7] Forward Error Frames */ + __IOM uint32_t EFC : 1; /*!< [8..8] Enable HW Flow Control */ + __IOM uint32_t RFA : 2; /*!< [10..9] Threshold for Activating Flow Control (in half-duplex + * and full-duplex) */ + __IOM uint32_t RFD : 2; /*!< [12..11] Threshold for Deactivating Flow Control (in half-duplex + * and full-duplex) */ + __IOM uint32_t ST : 1; /*!< [13..13] Start or Stop Transmission Command */ + __IOM uint32_t TTC : 3; /*!< [16..14] Transmit Threshold Control */ + uint32_t : 3; + __IOM uint32_t FTF : 1; /*!< [20..20] Flush Transmit FIFO */ + __IOM uint32_t TSF : 1; /*!< [21..21] Transmit Store and Forward */ + uint32_t : 3; + __IOM uint32_t RSF : 1; /*!< [25..25] Receive Store and Forward */ + __IOM uint32_t DT : 1; /*!< [26..26] Disable Dropping of TCP/IP Checksum Error Frames */ + uint32_t : 5; + } Operation_Mode_b; + }; + + union + { + __IOM uint32_t Interrupt_Enable; /*!< (@ 0x0000101C) Interrupt Enable Register */ + + struct + { + __IOM uint32_t TIE : 1; /*!< [0..0] Transmit Interrupt Enable */ + __IOM uint32_t TSE : 1; /*!< [1..1] Transmit Stopped Enable */ + __IOM uint32_t TUE : 1; /*!< [2..2] Transmit Buffer Unavailable Enable */ + __IOM uint32_t TJE : 1; /*!< [3..3] Transmit Jabber Timeout Enable */ + __IOM uint32_t OVE : 1; /*!< [4..4] Overflow Interrupt Enable */ + __IOM uint32_t UNE : 1; /*!< [5..5] Underflow Interrupt Enable */ + __IOM uint32_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint32_t RUE : 1; /*!< [7..7] Receive Buffer Unavailable Enable */ + __IOM uint32_t RSE : 1; /*!< [8..8] Receive Stopped Enable */ + __IOM uint32_t RWE : 1; /*!< [9..9] Receive Watchdog Timeout Enable */ + __IOM uint32_t ETE : 1; /*!< [10..10] Early Transmit Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t FBE : 1; /*!< [13..13] Fatal Bus Error Enable */ + __IOM uint32_t ERE : 1; /*!< [14..14] Early Receive Interrupt Enable */ + __IOM uint32_t AIE : 1; /*!< [15..15] Abnormal Interrupt Summary Enable */ + __IOM uint32_t NIE : 1; /*!< [16..16] Normal Interrupt Summary Enable */ + uint32_t : 15; + } Interrupt_Enable_b; + }; + + union + { + __IM uint32_t Missed_Frame_And_Buffer_Overflow_Counter; /*!< (@ 0x00001020) Missed Frame and Buffer Overflow Counter Register */ + + struct + { + __IM uint32_t MISFRMCNT : 16; /*!< [15..0] Missed Frame Counter */ + __IM uint32_t MISCNTOVF : 1; /*!< [16..16] Overflow Bit for Missed Frame Counter */ + __IM uint32_t OVFFRMCNT : 11; /*!< [27..17] Overflow Frame Counter */ + __IM uint32_t OVFCNTOVF : 1; /*!< [28..28] Overflow Bit for FIFO Overflow Counter */ + uint32_t : 3; + } Missed_Frame_And_Buffer_Overflow_Counter_b; + }; + + union + { + __IOM uint32_t Receive_Interrupt_Watchdog_Timer; /*!< (@ 0x00001024) Receive Interrupt Watchdog Timer Register */ + + struct + { + __IOM uint32_t RIWT : 8; /*!< [7..0] RI Watchdog Timer Count */ + uint32_t : 24; + } Receive_Interrupt_Watchdog_Timer_b; + }; + + union + { + __IOM uint32_t AXI_Bus_Mode; /*!< (@ 0x00001028) AXI Bus Mode Register */ + + struct + { + __IM uint32_t UNDEF : 1; /*!< [0..0] AXI Undefined Burst Length */ + __IOM uint32_t BLEN4 : 1; /*!< [1..1] AXI Burst Length 4 */ + __IOM uint32_t BLEN8 : 1; /*!< [2..2] AXI Burst Length 8 */ + __IOM uint32_t BLEN16 : 1; /*!< [3..3] AXI Burst Length 16 */ + uint32_t : 8; + __IM uint32_t AXI_AAL : 1; /*!< [12..12] Address-Aligned Beats */ + __IOM uint32_t ONEKBBE : 1; /*!< [13..13] 1 KB Boundary Crossing Enable for the GMAC-AXI Master */ + uint32_t : 2; + __IOM uint32_t RD_OSR_LMT : 2; /*!< [17..16] AXI Maximum Read OutStanding Request Limit */ + uint32_t : 2; + __IOM uint32_t WR_OSR_LMT : 2; /*!< [21..20] AXI Maximum Write OutStanding Request Limit */ + uint32_t : 8; + __IOM uint32_t LPI_XIT_FRM : 1; /*!< [30..30] Unlock on Magic Packet or Remote Wake-Up Frame */ + __IOM uint32_t EN_LPI : 1; /*!< [31..31] Enable Low Power Interface (LPI) */ + } AXI_Bus_Mode_b; + }; + + union + { + __IM uint32_t AXI_Status; /*!< (@ 0x0000102C) AXI Status Register */ + + struct + { + __IM uint32_t AXWHSTS : 1; /*!< [0..0] AXI Master Write Channel */ + __IM uint32_t AXIRDSTS : 1; /*!< [1..1] AXI Master Read Channel Status */ + uint32_t : 30; + } AXI_Status_b; + }; + __IM uint32_t RESERVED12[6]; + + union + { + __IM uint32_t Current_Host_Transmit_Descriptor; /*!< (@ 0x00001048) Current Host Transmit Descriptor Register */ + + struct + { + __IM uint32_t CURTDESAPTR : 32; /*!< [31..0] Host Transmit Descriptor Address Pointer */ + } Current_Host_Transmit_Descriptor_b; + }; + + union + { + __IM uint32_t Current_Host_Receive_Descriptor; /*!< (@ 0x0000104C) Current Host Receive Descriptor Register */ + + struct + { + __IM uint32_t CURRDESAPTR : 32; /*!< [31..0] Host Receive Descriptor Address Pointer */ + } Current_Host_Receive_Descriptor_b; + }; + + union + { + __IM uint32_t Current_Host_Transmit_Buffer_Address; /*!< (@ 0x00001050) Current Host Transmit Buffer Address Register */ + + struct + { + __IM uint32_t CURTBUFAPTR : 32; /*!< [31..0] Host Transmit Buffer Address Pointer */ + } Current_Host_Transmit_Buffer_Address_b; + }; + + union + { + __IM uint32_t Current_Host_Receive_Buffer_Address; /*!< (@ 0x00001054) Current Host Receive Buffer Address Register */ + + struct + { + __IM uint32_t CURRBUFAPTR : 32; /*!< [31..0] Host Receive Buffer Address Pointer */ + } Current_Host_Receive_Buffer_Address_b; + }; + + union + { + __IM uint32_t HW_Feature; /*!< (@ 0x00001058) HW Feature Register */ + + struct + { + __IM uint32_t MIISEL : 1; /*!< [0..0] 10 or 100 Mbps support */ + __IM uint32_t GMIISEL : 1; /*!< [1..1] 1000 Mbps support */ + __IM uint32_t HDSEL : 1; /*!< [2..2] Half-Duplex support */ + __IM uint32_t EXTHASHEN : 1; /*!< [3..3] Expanded DA Hash Filter */ + __IM uint32_t HASHSEL : 1; /*!< [4..4] HASH Filter */ + __IM uint32_t ADDMACADRSEL : 1; /*!< [5..5] Multiple MAC Address Registers */ + uint32_t : 1; + __IM uint32_t L3L4FLTREN : 1; /*!< [7..7] Layer 3 and Layer 4 Filter Feature */ + __IM uint32_t SMASEL : 1; /*!< [8..8] SMA (MDIO) Interface */ + __IM uint32_t RWKSEL : 1; /*!< [9..9] PMT Remote wakeup */ + __IM uint32_t MGKSEL : 1; /*!< [10..10] PMT Magic Packet */ + __IM uint32_t MMCSEL : 1; /*!< [11..11] RMON Module */ + __IM uint32_t TSVER1SEL : 1; /*!< [12..12] Only IEEE 1588-2002 Timestamp */ + __IM uint32_t TSVER2SEL : 1; /*!< [13..13] IEEE 1588-2008 Advanced Timestamp */ + __IM uint32_t EEESEL : 1; /*!< [14..14] Energy Efficient Ethernet */ + __IM uint32_t AVSEL : 1; /*!< [15..15] AV Feature */ + __IM uint32_t TXCOESEL : 1; /*!< [16..16] Checksum Offload in TX */ + __IM uint32_t RXTYP1COE : 1; /*!< [17..17] IP Checksum Offload (Type 1) in RX */ + __IM uint32_t RXTYP2COE : 1; /*!< [18..18] IP Checksum Offload (Type 2) in RX */ + __IM uint32_t RXFIFOSIZE : 1; /*!< [19..19] RX FIFO > 2,048 Bytes */ + __IM uint32_t RXCHCNT : 2; /*!< [21..20] Number of additional RX channels */ + __IM uint32_t TXCHCNT : 2; /*!< [23..22] Number of additional TX channels */ + __IM uint32_t ENHDESSEL : 1; /*!< [24..24] Enhanced Descriptor */ + __IM uint32_t INTTSEN : 1; /*!< [25..25] Timestamping with Internal System Time */ + __IM uint32_t FLEXIPPSEN : 1; /*!< [26..26] Flexible Pulse-Per-Second Output (GMAC: 0) */ + __IM uint32_t SAVLANINS : 1; /*!< [27..27] Source Address or VLAN Insertion */ + __IM uint32_t ACTPHYIF : 3; /*!< [30..28] Active or Selected PHY interface */ + uint32_t : 1; + } HW_Feature_b; + }; +} R_GMAC_Type; /*!< Size = 4188 (0x105c) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHSS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet Subsystem (R_ETHSS) + */ + +typedef struct /*!< (@ 0x80110000) R_ETHSS Structure */ +{ + __IOM uint32_t PRCMD; /*!< (@ 0x00000000) Ethernet Protect Register */ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t MODCTRL; /*!< (@ 0x00000008) Mode Control Register */ + + struct + { + __IOM uint32_t SW_MODE : 3; /*!< [2..0] Media I/F connectionSW_MODE[2:0]Media I/FPort 0Port 1Port + * 2000bETHSW Port 0ETHSW Port 1ETHSW Port 2001bESC Port 0ESC + * Port 1GMAC Port010bESC Port 0ESC Port 1ETHSW Port 2011bESC + * Port 0ESC Port 1ESC Port 2100bETHSW Port 0ESC Port 1ESC + * Port 2101bETHSW Port 0ESC Port 1ETHSW Port 2OthersSetting + * Prohibited */ + uint32_t : 29; + } MODCTRL_b; + }; + + union + { + __IOM uint32_t PTPMCTRL; /*!< (@ 0x0000000C) PTP Mode Control Register */ + + struct + { + __IOM uint32_t PTP_MODE : 1; /*!< [0..0] Select the unit number of PTP Timer for GMAC and Pulse + * Generator (unit 0 - 3) */ + uint32_t : 15; + __IOM uint32_t PTP_PLS_RSTn : 1; /*!< [16..16] Reset control for Pulse Generator (unit 0 - 3) */ + uint32_t : 15; + } PTPMCTRL_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t PHYLNK; /*!< (@ 0x00000014) Ethernet PHY Link Mode Register */ + + struct + { + __IOM uint32_t SWLINK : 3; /*!< [2..0] Specify the active level of the ETHSW_PHYLINKn signal + * using the Ethernet switch interface */ + uint32_t : 1; + __IOM uint32_t CATLNK : 3; /*!< [6..4] Specify the active level of the ESC_PHYLINKn signal using + * the EtherCAT interface */ + uint32_t : 25; + } PHYLNK_b; + }; + __IM uint32_t RESERVED2[58]; + + union + { + __IOM uint32_t CONVCTRL[3]; /*!< (@ 0x00000100) RGMII/RMII Converter [0..2] Control Register */ + + struct + { + __IOM uint32_t CONV_MODE : 5; /*!< [4..0] Converter operation mode */ + uint32_t : 3; + __IOM uint32_t FULLD : 1; /*!< [8..8] FULLD */ + __IOM uint32_t RMII_RX_ER_EN : 1; /*!< [9..9] RMII_RX_ER_EN */ + __IOM uint32_t RMII_CRS_MODE : 1; /*!< [10..10] RMII_CRS_MODE */ + uint32_t : 1; + __IM uint32_t RGMII_LINK : 1; /*!< [12..12] RGMII_LINK */ + __IM uint32_t RGMII_DUPLEX : 1; /*!< [13..13] RGMII_DUPLEX */ + __IM uint32_t RGMII_SPEED : 2; /*!< [15..14] RGMII_SPEED */ + uint32_t : 16; + } CONVCTRL_b[3]; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t CONVRST; /*!< (@ 0x00000114) RGMII/RMII Converter Reset Control Register */ + + struct + { + __IOM uint32_t PHYIR : 3; /*!< [2..0] PHYIR */ + uint32_t : 29; + } CONVRST_b; + }; + __IM uint32_t RESERVED4[123]; + + union + { + __IOM uint32_t SWCTRL; /*!< (@ 0x00000304) Switch Core Control Register */ + + struct + { + __IOM uint32_t SET10 : 3; /*!< [2..0] Port control to select use of 10 Mbps. Bit 0 = port 0, + * bit 1 = port 1, bit 2 = port 2. */ + uint32_t : 1; + __IOM uint32_t SET1000 : 3; /*!< [6..4] Port control to select use of 1000 Mbps. Bit 0 = port + * 0, bit 1 = port 1, bit 2 = port 2. */ + uint32_t : 9; + __IOM uint32_t STRAP_SX_ENB : 1; /*!< [16..16] Initialize switch after reset (set during module reset + * of ETHSW) */ + __IOM uint32_t STRAP_HUB_ENB : 1; /*!< [17..17] Initialize switch port 0 and 1 (set during module reset + * of ETHSW) */ + uint32_t : 14; + } SWCTRL_b; + }; + + union + { + __IOM uint32_t SWDUPC; /*!< (@ 0x00000308) Switch Core Duplex Mode Register */ + + struct + { + __IOM uint32_t PHY_DUPLEX : 3; /*!< [2..0] Configure the MAC of each port for full-duplex or half-duplex + * operation. Bit 0 = port 0, bit 1 = port 1, bit 2 = port + * 2. */ + uint32_t : 29; + } SWDUPC_b; + }; + __IM uint32_t RESERVED5[573]; + + union + { + __IOM uint32_t CDCR; /*!< (@ 0x00000C00) RGMII Clock Delay Control Register */ + + struct + { + __IOM uint32_t RXDLYEN : 1; /*!< [0..0] Enable delay for ETH2_RXCLK */ + __IOM uint32_t TXDLYEN : 1; /*!< [1..1] Enable delay for ETH2_TXCLK */ + __IOM uint32_t OSCCLKEN : 1; /*!< [2..2] Enable Oscillation mode for calibration */ + __IOM uint32_t CLKINEN : 1; /*!< [3..3] Enable Phase shift mode for normal operation */ + uint32_t : 28; + } CDCR_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IM uint32_t RXFCNT; /*!< (@ 0x00000C10) RGMII RX OSC Frequency Measurement Counter Register */ + + struct + { + __IM uint32_t RXFCNT : 16; /*!< [15..0] Oscillation frequency measurement counter for ETH2_RXCLK + * delay */ + uint32_t : 16; + } RXFCNT_b; + }; + + union + { + __IM uint32_t TXFCNT; /*!< (@ 0x00000C14) RGMII TX OSC Frequency Measurement Counter Register */ + + struct + { + __IM uint32_t TXFCNT : 16; /*!< [15..0] Oscillation frequency measurement counter for ETH2_TXCLK + * delay */ + uint32_t : 16; + } TXFCNT_b; + }; + + union + { + __IOM uint32_t RXTAPSEL; /*!< (@ 0x00000C18) RGMII RX TAP Selection Register */ + + struct + { + __IOM uint32_t RXTAPSEL : 7; /*!< [6..0] TAP selection for ETH2_RXCLK delay (number of taps for + * 90 degree phase shift) */ + uint32_t : 25; + } RXTAPSEL_b; + }; + + union + { + __IOM uint32_t TXTAPSEL; /*!< (@ 0x00000C1C) RGMII TX TAP Selection Register */ + + struct + { + __IOM uint32_t TXTAPSEL : 7; /*!< [6..0] TAP selection for ETH2_TXCLK delay (Number of taps for + * 90 degree phase shift) */ + uint32_t : 25; + } TXTAPSEL_b; + }; + + union + { + __IOM uint32_t MIIMCR; /*!< (@ 0x00000C20) MII Mode Control Register */ + + struct + { + __IOM uint32_t MIIM2MEN : 1; /*!< [0..0] Enable MAC-to-MAC MII Mode */ + uint32_t : 31; + } MIIMCR_b; + }; +} R_ETHSS_Type; /*!< Size = 3108 (0xc24) */ + +/* =========================================================================================================================== */ +/* ================ R_ESC_INI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Initial Configuration 1 for EtherCAT Slave Controller (R_ESC_INI) + */ + +typedef struct /*!< (@ 0x80110200) R_ESC_INI Structure */ +{ + union + { + __IOM uint32_t ECATOFFADR; /*!< (@ 0x00000000) EtherCAT PHY Offset Address Setting Register */ + + struct + { + __IOM uint32_t OADD : 5; /*!< [4..0] PHY Offset Address Setting */ + uint32_t : 27; + } ECATOFFADR_b; + }; + + union + { + __IOM uint32_t ECATOPMOD; /*!< (@ 0x00000004) EtherCAT Operation Mode Register */ + + struct + { + __IOM uint32_t EEPROMSIZE : 1; /*!< [0..0] EEPROM Memory Size Specification */ + uint32_t : 31; + } ECATOPMOD_b; + }; + + union + { + __IOM uint32_t ECATDBGC; /*!< (@ 0x00000008) EtherCAT Debug Control Register */ + + struct + { + __IOM uint32_t TXSFT0 : 2; /*!< [1..0] Set the delay time for ETH0_TXC of the EtherCAT */ + __IOM uint32_t TXSFT1 : 2; /*!< [3..2] Set the delay time for ETH1_TXC of the EtherCAT */ + __IOM uint32_t TXSFT2 : 2; /*!< [5..4] Set the delay time for ETH2_TXC of the EtherCAT */ + uint32_t : 26; + } ECATDBGC_b; + }; + + union + { + __IOM uint32_t ECATTRGSEL; /*!< (@ 0x0000000C) EtherCAT DC Latch Trigger Select Register */ + + struct + { + __IOM uint32_t TRGSEL0 : 1; /*!< [0..0] Select DC Latch Trigger 0 for ESC */ + __IOM uint32_t TRGSEL1 : 1; /*!< [1..1] Select DC Latch Trigger 1 for ESC */ + uint32_t : 30; + } ECATTRGSEL_b; + }; +} R_ESC_INI_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHSW_PTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet Switch for PTP (R_ETHSW_PTP) + */ + +typedef struct /*!< (@ 0x80110400) R_ETHSW_PTP Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SWPTPOUTSEL; /*!< (@ 0x00000004) ETHSW_PTPOUT Select Register */ + + struct + { + __IOM uint32_t IOSEL0 : 1; /*!< [0..0] Select the source of the ETHSW_PTPOUT0 output signal */ + __IOM uint32_t IOSEL1 : 1; /*!< [1..1] Select the source of the ETHSW_PTPOUT1 output signal */ + __IOM uint32_t IOSEL2 : 1; /*!< [2..2] Select the source of the ETHSW_PTPOUT2 output signal */ + __IOM uint32_t IOSEL3 : 1; /*!< [3..3] Select the source of the ETHSW_PTPOUT3 output signal */ + __IOM uint32_t EVTSEL0 : 1; /*!< [4..4] Select the source of the ETHSW_PTPOUT0 event for GIC, + * DMAC, and ELC */ + __IOM uint32_t EVTSEL1 : 1; /*!< [5..5] Select the source of the ETHSW_PTPOUT1 event for GIC, + * DMAC, and ELC */ + __IOM uint32_t EVTSEL2 : 1; /*!< [6..6] Select the source of the ETHSW_PTPOUT2 event for GIC, + * DMAC, and ELC */ + __IOM uint32_t EVTSEL3 : 1; /*!< [7..7] Select the source of the ETHSW_PTPOUT3 event for GIC, + * DMAC, and ELC */ + uint32_t : 24; + } SWPTPOUTSEL_b; + }; + __IM uint32_t RESERVED1[254]; + __IOM R_ETHSW_PTP_SWTM_Type SWTM[4]; /*!< (@ 0x00000400) Ethernet Switch Timer output pins 0-3 Registers */ +} R_ETHSW_PTP_Type; /*!< Size = 2048 (0x800) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHSW ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet Switch (R_ETHSW) + */ + +typedef struct /*!< (@ 0x80120000) R_ETHSW Structure */ +{ + union + { + __IM uint32_t REVISION; /*!< (@ 0x00000000) Switch Core Version Register */ + + struct + { + __IM uint32_t REV : 32; /*!< [31..0] Revision */ + } REVISION_b; + }; + + union + { + __IOM uint32_t SCRATCH; /*!< (@ 0x00000004) Scratch Register */ + + struct + { + __IOM uint32_t SCRATCH : 32; /*!< [31..0] The Scratch Register provides a memory location to test + * the register access. */ + } SCRATCH_b; + }; + + union + { + __IOM uint32_t PORT_ENA; /*!< (@ 0x00000008) Port Enable Register */ + + struct + { + __IOM uint32_t TXENA : 4; /*!< [3..0] Transmit Enable Mask */ + uint32_t : 12; + __IOM uint32_t RXENA : 4; /*!< [19..16] Receive Enable Mask */ + uint32_t : 12; + } PORT_ENA_b; + }; + + union + { + __IOM uint32_t UCAST_DEFAULT_MASK0; /*!< (@ 0x0000000C) Unicast Default Mask Register 0 */ + + struct + { + __IOM uint32_t UCASTDM : 4; /*!< [3..0] Default Unicast Resolution */ + uint32_t : 28; + } UCAST_DEFAULT_MASK0_b; + }; + + union + { + __IOM uint32_t VLAN_VERIFY; /*!< (@ 0x00000010) Verify VLAN Domain Register */ + + struct + { + __IOM uint32_t VLANVERI : 4; /*!< [3..0] Verify VLAN Domain */ + uint32_t : 12; + __IOM uint32_t VLANDISC : 4; /*!< [19..16] Discard Unknown */ + uint32_t : 12; + } VLAN_VERIFY_b; + }; + + union + { + __IOM uint32_t BCAST_DEFAULT_MASK0; /*!< (@ 0x00000014) Broadcast Default Mask Register 0 */ + + struct + { + __IOM uint32_t BCASTDM : 4; /*!< [3..0] Default Broadcast Resolution */ + uint32_t : 28; + } BCAST_DEFAULT_MASK0_b; + }; + + union + { + __IOM uint32_t MCAST_DEFAULT_MASK0; /*!< (@ 0x00000018) Multicast Default Mask Register 0 */ + + struct + { + __IOM uint32_t MCASTDM : 4; /*!< [3..0] Default Multicast Resolution */ + uint32_t : 28; + } MCAST_DEFAULT_MASK0_b; + }; + + union + { + __IOM uint32_t INPUT_LEARN_BLOCK; /*!< (@ 0x0000001C) Input Learning Block Register */ + + struct + { + __IOM uint32_t BLOCKEN : 4; /*!< [3..0] Blocking Enable */ + uint32_t : 12; + __IOM uint32_t LEARNDIS : 4; /*!< [19..16] Learning Disable */ + uint32_t : 12; + } INPUT_LEARN_BLOCK_b; + }; + + union + { + __IOM uint32_t MGMT_CONFIG; /*!< (@ 0x00000020) Management Configuration Register */ + + struct + { + __IOM uint32_t PORT : 4; /*!< [3..0] The Port number of the port that should act as a management + * port. Keep the initial value. */ + uint32_t : 1; + __IOM uint32_t MSG_TRANS : 1; /*!< [5..5] Set (latched) when a BPDU message is transmitted from + * the management port to any output port. This bit can be + * used for handshaking to indicate that the port mask bits + * are used and can now be changed again by setting it to + * 0. */ + __IOM uint32_t ENABLE : 1; /*!< [6..6] If set, all Bridge Protocol Frames (BPDU) are forwarded + * exclusively to the management port specified in bits [3:0]. */ + __IOM uint32_t DISCARD : 1; /*!< [7..7] If set, BPDU frames are discarded always. Setting has + * no effect, when the enable bit is set. */ + __IOM uint32_t MGMT_EN : 1; /*!< [8..8] If set, BPDU frames received at the management port are + * forwarded to the ports given in the portmask given in this + * register, bypassing the normal forwarding decisions (except + * forced forwarding). */ + __IOM uint32_t MGMT_DISC : 1; /*!< [9..9] This bit is the same as DISCARD (bit 7) but for the management + * port. */ + uint32_t : 3; + __IOM uint32_t PRIORITY : 3; /*!< [15..13] Priority to use for transmitted BPDU frames if non-zero. */ + __IOM uint32_t PORTMASK : 4; /*!< [19..16] Portmask for transmission of management frames. When + * the management port transmits a frame to the switch, it + * is forwarded to all ports in this portmask (bit 16 = port + * 0, bit 17 = port 1, ..., bit 19 = port 3). */ + uint32_t : 12; + } MGMT_CONFIG_b; + }; + + union + { + __IOM uint32_t MODE_CONFIG; /*!< (@ 0x00000024) Mode Configuration Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t CUT_THRU_EN : 4; /*!< [11..8] Port Cut through Support Enable */ + uint32_t : 19; + __IOM uint32_t STATSRESET : 1; /*!< [31..31] Reset Statistics Counters Command. */ + } MODE_CONFIG_b; + }; + + union + { + __IOM uint32_t VLAN_IN_MODE; /*!< (@ 0x00000028) VLAN Input Manipulation Mode Register */ + + struct + { + __IOM uint32_t P0VLANINMD : 2; /*!< [1..0] Port 0 Define Behavior of VLAN Input Manipulation Function */ + __IOM uint32_t P1VLANINMD : 2; /*!< [3..2] Port 1 Define Behavior of VLAN Input Manipulation Function */ + __IOM uint32_t P2VLANINMD : 2; /*!< [5..4] Port 2 Define Behavior of VLAN Input Manipulation Function */ + __IOM uint32_t P3VLANINMD : 2; /*!< [7..6] Port3 Define Behavior of VLAN Input Manipulation Function */ + uint32_t : 24; + } VLAN_IN_MODE_b; + }; + + union + { + __IOM uint32_t VLAN_OUT_MODE; /*!< (@ 0x0000002C) VLAN Output Manipulation Mode Register */ + + struct + { + __IOM uint32_t P0VLANOUTMD : 2; /*!< [1..0] Port 0 Define Behavior of VLAN Output Manipulation Function */ + __IOM uint32_t P1VLANOUTMD : 2; /*!< [3..2] Port 1 Define Behavior of VLAN Output Manipulation Function */ + __IOM uint32_t P2VLANOUTMD : 2; /*!< [5..4] Port 2 Define Behavior of VLAN Output Manipulation Function */ + __IOM uint32_t P3VLANOUTMD : 2; /*!< [7..6] Port 3 Define Behavior of VLAN Output Manipulation Function */ + uint32_t : 24; + } VLAN_OUT_MODE_b; + }; + + union + { + __IOM uint32_t VLAN_IN_MODE_ENA; /*!< (@ 0x00000030) VLAN Input Mode Enable Register */ + + struct + { + __IOM uint32_t VLANINMDEN : 4; /*!< [3..0] Enable the input processing according to the VLAN_IN_MODE + * for a port (1 bit per port). */ + uint32_t : 28; + } VLAN_IN_MODE_ENA_b; + }; + + union + { + __IOM uint32_t VLAN_TAG_ID; /*!< (@ 0x00000034) VLAN Tag ID Register */ + + struct + { + __IOM uint32_t VLANTAGID : 16; /*!< [15..0] The VLAN type field (TPID) value to expect to identify + * a VLAN tagged frame. */ + uint32_t : 16; + } VLAN_TAG_ID_b; + }; + + union + { + __IOM uint32_t BCAST_STORM_LIMIT; /*!< (@ 0x00000038) Broadcast Storm Protection Register */ + + struct + { + __IOM uint32_t TMOUT : 16; /*!< [15..0] Timeout in steps of 65535 switch operating clock cycles. */ + __IOM uint32_t BCASTLIMIT : 16; /*!< [31..16] Number of broadcast frames (-1) that can be accepted + * on a port during a timeout period. If more are received, + * they are discarded. The counter is implemented per port + * independently. However, the limit is used for all ports. */ + } BCAST_STORM_LIMIT_b; + }; + + union + { + __IOM uint32_t MCAST_STORM_LIMIT; /*!< (@ 0x0000003C) Multicast Storm Protection Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t MCASTLIMIT : 16; /*!< [31..16] Number of multicast frames (-1) that can be accepted + * on a port during a timeout period. If more are received, + * they are discarded. The counter is implemented per port + * independently. However, the limit is used for all ports. */ + } MCAST_STORM_LIMIT_b; + }; + + union + { + __IOM uint32_t MIRROR_CONTROL; /*!< (@ 0x00000040) Port Mirroring Configuration Register */ + + struct + { + __IOM uint32_t PORT : 2; /*!< [1..0] The port number of the port that acts as the mirror port + * and receives all mirrored frames. Valid setting range is + * 0 to 3. */ + uint32_t : 2; + __IOM uint32_t MIRROR_EN : 1; /*!< [4..4] MIRROR_EN */ + __IOM uint32_t ING_MAP_EN : 1; /*!< [5..5] If set, the ingress map is enabled (MIRROR_ING_MAP). */ + __IOM uint32_t EG_MAP_EN : 1; /*!< [6..6] If set, the egress map is enabled (MIRROR_EG_MAP). */ + __IOM uint32_t ING_SA_MATCH : 1; /*!< [7..7] If set, only frames received on an ingress port with + * a source address matching the value programmed in MIRROR_ISRC + * registers are mirrored. Other frames are not mirrored. */ + __IOM uint32_t ING_DA_MATCH : 1; /*!< [8..8] If set, only frames received on an ingress port with + * a destination address matching the value programmed in + * MIRROR_IDST registers are mirrored. Other frames are not + * mirrored. */ + __IOM uint32_t EG_SA_MATCH : 1; /*!< [9..9] If set, only frames transmitted on an egress port with + * a source address matching the value programmed in MIRROR_ESRC + * registers are mirrored. Other frames are not mirrored. */ + __IOM uint32_t EG_DA_MATCH : 1; /*!< [10..10] If set, only frames transmitted on an egress port with + * a destination address matching the value programmed in + * MIRROR_EDST registers are mirrored. Other frames are not + * mirrored. */ + uint32_t : 21; + } MIRROR_CONTROL_b; + }; + + union + { + __IOM uint32_t MIRROR_EG_MAP; /*!< (@ 0x00000044) Port Mirroring Egress Port Definition Register */ + + struct + { + __IOM uint32_t EMAP : 4; /*!< [3..0] Port Mirroring Egress Port Definitions */ + uint32_t : 28; + } MIRROR_EG_MAP_b; + }; + + union + { + __IOM uint32_t MIRROR_ING_MAP; /*!< (@ 0x00000048) Port Mirroring Ingress Port Definition Register */ + + struct + { + __IOM uint32_t IMAP : 4; /*!< [3..0] Port Mirroring Ingress Port Definitions */ + uint32_t : 28; + } MIRROR_ING_MAP_b; + }; + + union + { + __IOM uint32_t MIRROR_ISRC_0; /*!< (@ 0x0000004C) Ingress Source MAC Address for Mirror Filtering + * Register 0 */ + + struct + { + __IOM uint32_t ISRC : 32; /*!< [31..0] Ingress Source MAC Address for Mirror Filtering */ + } MIRROR_ISRC_0_b; + }; + + union + { + __IOM uint32_t MIRROR_ISRC_1; /*!< (@ 0x00000050) Ingress Source MAC Address for Mirror Filtering + * Register 1 */ + + struct + { + __IOM uint32_t ISRC : 16; /*!< [15..0] Ingress Source MAC Address for Mirror Filtering */ + uint32_t : 16; + } MIRROR_ISRC_1_b; + }; + + union + { + __IOM uint32_t MIRROR_IDST_0; /*!< (@ 0x00000054) Ingress Destination MAC Address for Mirror Filtering + * Register 0 */ + + struct + { + __IOM uint32_t IDST : 32; /*!< [31..0] Ingress Destination MAC Address for Mirror Filtering */ + } MIRROR_IDST_0_b; + }; + + union + { + __IOM uint32_t MIRROR_IDST_1; /*!< (@ 0x00000058) Ingress Destination MAC Address for Mirror Filtering + * Register 1 */ + + struct + { + __IOM uint32_t IDST : 16; /*!< [15..0] Ingress Destination MAC Address for Mirror Filtering */ + uint32_t : 16; + } MIRROR_IDST_1_b; + }; + + union + { + __IOM uint32_t MIRROR_ESRC_0; /*!< (@ 0x0000005C) Egress Source MAC Address for Mirror Filtering + * Register 0 */ + + struct + { + __IOM uint32_t ESRC : 32; /*!< [31..0] Egress Source MAC Address for Mirror Filtering */ + } MIRROR_ESRC_0_b; + }; + + union + { + __IOM uint32_t MIRROR_ESRC_1; /*!< (@ 0x00000060) Egress Source MAC Address for Mirror Filtering + * Register 1 */ + + struct + { + __IOM uint32_t ESRC : 16; /*!< [15..0] Egress Source MAC Address for Mirror Filtering */ + uint32_t : 16; + } MIRROR_ESRC_1_b; + }; + + union + { + __IOM uint32_t MIRROR_EDST_0; /*!< (@ 0x00000064) Egress Destination MAC Address for Mirror Filtering + * Register 0 */ + + struct + { + __IOM uint32_t EDST : 32; /*!< [31..0] Egress Destination MAC Address for Mirror Filtering */ + } MIRROR_EDST_0_b; + }; + + union + { + __IOM uint32_t MIRROR_EDST_1; /*!< (@ 0x00000068) Egress Destination MAC Address for Mirror Filtering + * Register 1 */ + + struct + { + __IOM uint32_t EDST : 16; /*!< [15..0] Egress Destination MAC Address for Mirror Filtering */ + uint32_t : 16; + } MIRROR_EDST_1_b; + }; + + union + { + __IOM uint32_t MIRROR_CNT; /*!< (@ 0x0000006C) Mirror Filtering Count Value Register */ + + struct + { + __IOM uint32_t CNT : 8; /*!< [7..0] Count Value for Mirror Filtering */ + uint32_t : 24; + } MIRROR_CNT_b; + }; + + union + { + __IOM uint32_t UCAST_DEFAULT_MASK1; /*!< (@ 0x00000070) Unicast Default Mask Register 1 */ + + struct + { + __IOM uint32_t UCASTDM1 : 4; /*!< [3..0] Default Unicast Resolution Mask 1 */ + uint32_t : 28; + } UCAST_DEFAULT_MASK1_b; + }; + + union + { + __IOM uint32_t BCAST_DEFAULT_MASK1; /*!< (@ 0x00000074) Broadcast Default Mask Register 1 */ + + struct + { + __IOM uint32_t BCASTDM1 : 4; /*!< [3..0] Default Broadcast Resolution Mask 1 */ + uint32_t : 28; + } BCAST_DEFAULT_MASK1_b; + }; + + union + { + __IOM uint32_t MCAST_DEFAULT_MASK1; /*!< (@ 0x00000078) Multicast Default Mask Register 1 */ + + struct + { + __IOM uint32_t MCASTDM1 : 4; /*!< [3..0] Default Multicast Resolution Mask 1 */ + uint32_t : 28; + } MCAST_DEFAULT_MASK1_b; + }; + + union + { + __IOM uint32_t PORT_XCAST_MASK_SEL; /*!< (@ 0x0000007C) Port Mask Select Register */ + + struct + { + __IOM uint32_t MSEL : 4; /*!< [3..0] Mask Select */ + uint32_t : 28; + } PORT_XCAST_MASK_SEL_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t QMGR_ST_MINCELLS; /*!< (@ 0x00000088) Minimum Memory Cell Statistics Register */ + + struct + { + __IOM uint32_t STMINCELLS : 11; /*!< [10..0] Minimum Free Cell Indication */ + uint32_t : 21; + } QMGR_ST_MINCELLS_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t QMGR_RED_MIN4; /*!< (@ 0x00000094) RED Minimum Threshold Register */ + + struct + { + __IOM uint32_t CFGRED_MINTH4 : 32; /*!< [31..0] Random Early Detection (RED) Minimum Threshold for Queues + * 0 to 3 */ + } QMGR_RED_MIN4_b; + }; + + union + { + __IOM uint32_t QMGR_RED_MAX4; /*!< (@ 0x00000098) RED Maximum Threshold Register */ + + struct + { + __IOM uint32_t CFGRED_MAXTH4 : 32; /*!< [31..0] Random Early Detection (RED) Maximum Threshold for Queues + * 0 to 3 */ + } QMGR_RED_MAX4_b; + }; + + union + { + __IOM uint32_t QMGR_RED_CONFIG; /*!< (@ 0x0000009C) RED Configuration Register */ + + struct + { + __IOM uint32_t QUEUE_RED_EN : 4; /*!< [3..0] Enable Random Early Detection (RED) (when this bit is + * 1) or Tail Drop (when this bit is 0) congestion management + * for a queue. */ + uint32_t : 4; + __IOM uint32_t GACTIVITY_EN : 1; /*!< [8..8] Enable Averaging on Global Switch Activity (when this + * bit is 1) or on port local activity (when this bit is 0) + * only. */ + uint32_t : 23; + } QMGR_RED_CONFIG_b; + }; + + union + { + __IM uint32_t IMC_STATUS; /*!< (@ 0x000000A0) Input Memory Controller Status Register */ + + struct + { + __IM uint32_t CELLS_AVAILABLE : 24; /*!< [23..0] Total number of memory cells (128-byte units) available + * in the shared memory (real time). */ + __IM uint32_t CF_ERR : 1; /*!< [24..24] Cell Factory Empty Error */ + __IM uint32_t DE_ERR : 1; /*!< [25..25] Deallocation Error */ + __IM uint32_t DE_INIT : 1; /*!< [26..26] Asserts during Memory Initialization (deallocation + * module) */ + __IM uint32_t MEM_FULL : 1; /*!< [27..27] Latched Indication that Memory is or was Full */ + uint32_t : 4; + } IMC_STATUS_b; + }; + + union + { + __IM uint32_t IMC_ERR_FULL; /*!< (@ 0x000000A4) Input Port Memory Full and Truncation Indicator + * Register */ + + struct + { + __IM uint32_t IPC_ERR_FULL : 4; /*!< [3..0] Memory was full at start of a frame reception. */ + uint32_t : 12; + __IM uint32_t IPC_ERR_TRUNC : 4; /*!< [19..16] Memory became full while a frame was received and was + * partly written into memory. */ + uint32_t : 12; + } IMC_ERR_FULL_b; + }; + + union + { + __IM uint32_t IMC_ERR_IFACE; /*!< (@ 0x000000A8) Input Port Memory Error Indicator Register */ + + struct + { + __IM uint32_t IPC_ERR_IFACE : 4; /*!< [3..0] Error indication on memory input (receive from MAC) that + * a frame has been truncated and discarded. */ + uint32_t : 12; + __IM uint32_t WBUF_OVF : 4; /*!< [19..16] Error indicating an overflow in the input write buffer + * to the memory controller (a small decoupling FIFO at every + * MAC RX). */ + uint32_t : 12; + } IMC_ERR_IFACE_b; + }; + + union + { + __IM uint32_t IMC_ERR_QOFLOW; /*!< (@ 0x000000AC) Output Port Queue Overflow Indicator Register */ + + struct + { + __IM uint32_t OP_ERR : 4; /*!< [3..0] A frame cannot be stored in an output queue of the port + * as the queue FIFO overflowed (write occurred into full + * fifo). The frame is ignored but stays stored in memory. + * This should not occur during normal operation. This is + * a fatal error as the memory allocated by that frame is + * not freed, and resulting in memory leakage. */ + uint32_t : 28; + } IMC_ERR_QOFLOW_b; + }; + + union + { + __IOM uint32_t IMC_CONFIG; /*!< (@ 0x000000B0) Input Memory Controller Configuration Register */ + + struct + { + __IOM uint32_t WFQ_EN : 1; /*!< [0..0] Enable weighted fair queuing (when this bit is 1) or + * strict priority (when this bit is 0, default) output queue + * scheduling. */ + __IOM uint32_t RSV_ENA : 1; /*!< [1..1] Enable Memory Reservations to Operate */ + __IOM uint32_t SPEED_HIPRI_THR : 3; /*!< [4..2] High-Priority Speed Threshold */ + __IOM uint32_t CTFL_EMPTY_MD : 1; /*!< [5..5] When this bit is set to 0, a frame received in Cut-Through + * mode that cannot allocate an entry in the CTFL is forwarded + * as store and forward. */ + uint32_t : 26; + } IMC_CONFIG_b; + }; + + union + { + __IM uint32_t IMC_ERR_ALLOC; /*!< (@ 0x000000B4) Input Port Error Indicator Register */ + + struct + { + __IM uint32_t DISC_FULL : 4; /*!< [3..0] Per port discard indication due to memory pool going + * empty. Per port indication that one of the queues was full + * and a frame was discarded. */ + uint32_t : 12; + __IM uint32_t DISC_LATE : 4; /*!< [19..16] Per port discard indication due to lateness in the + * priority resolution. The priority resolution can be delayed + * by the pattern matchers. If it arrives too late (after + * approximately 100 bytes into the frame), the frame is discarded. */ + uint32_t : 12; + } IMC_ERR_ALLOC_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t GPARSER0; /*!< (@ 0x000000C0) [n + 1]th Parser of 1st Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask will be compared with the data in the frame. + * All bits having a 0 will be 0 for the compare, however + * this requires the compare value to have those bits also + * set to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes where to find the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type/length field of the frame, that + * is, 0 = first byte of type/length field) or the payload + * following an IP header (see IPDATA). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicate that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field found within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represent the byte at + * the given offset and MASK_VAL2[7:0] represent the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields. For example, setting a compare + * value of 0x0800 and offset 0 matches IP frames. No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value. + * When set, the parser reports a match if the byte at given + * offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER0_b; + }; + + union + { + __IOM uint32_t GPARSER1; /*!< (@ 0x000000C4) [n + 1]th Parser of 1st Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask will be compared with the data in the frame. + * All bits having a 0 will be 0 for the compare, however + * this requires the compare value to have those bits also + * set to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes where to find the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type/length field of the frame, that + * is, 0 = first byte of type/length field) or the payload + * following an IP header (see IPDATA). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicate that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field found within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represent the byte at + * the given offset and MASK_VAL2[7:0] represent the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields. For example, setting a compare + * value of 0x0800 and offset 0 matches IP frames. No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value. + * When set, the parser reports a match if the byte at given + * offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER1_b; + }; + + union + { + __IOM uint32_t GPARSER2; /*!< (@ 0x000000C8) [n + 1]th Parser of 1st Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask will be compared with the data in the frame. + * All bits having a 0 will be 0 for the compare, however + * this requires the compare value to have those bits also + * set to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes where to find the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type/length field of the frame, that + * is, 0 = first byte of type/length field) or the payload + * following an IP header (see IPDATA). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicate that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field found within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represent the byte at + * the given offset and MASK_VAL2[7:0] represent the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields. For example, setting a compare + * value of 0x0800 and offset 0 matches IP frames. No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value. + * When set, the parser reports a match if the byte at given + * offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER2_b; + }; + + union + { + __IOM uint32_t GPARSER3; /*!< (@ 0x000000CC) [n + 1]th Parser of 1st Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask will be compared with the data in the frame. + * All bits having a 0 will be 0 for the compare, however + * this requires the compare value to have those bits also + * set to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes where to find the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type/length field of the frame, that + * is, 0 = first byte of type/length field) or the payload + * following an IP header (see IPDATA). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicate that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field found within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represent the byte at + * the given offset and MASK_VAL2[7:0] represent the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields. For example, setting a compare + * value of 0x0800 and offset 0 matches IP frames. No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value. + * When set, the parser reports a match if the byte at given + * offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER3_b; + }; + + union + { + __IOM uint32_t GARITH0; /*!< (@ 0x000000D0) Snoop Configuration for Arithmetic [n + 1]th + * Stage of 1st Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH0_b; + }; + + union + { + __IOM uint32_t GARITH1; /*!< (@ 0x000000D4) Snoop Configuration for Arithmetic [n + 1]th + * Stage of 1st Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH1_b; + }; + + union + { + __IOM uint32_t GARITH2; /*!< (@ 0x000000D8) Snoop Configuration for Arithmetic [n + 1]th + * Stage of 1st Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH2_b; + }; + + union + { + __IOM uint32_t GARITH3; /*!< (@ 0x000000DC) Snoop Configuration for Arithmetic [n + 1]th + * Stage of 1st Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH3_b; + }; + + union + { + __IOM uint32_t GPARSER4; /*!< (@ 0x000000E0) [n - 3]th Parser of 2nd Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask are compared with the data in the frame. All + * bits having a 0 will be 0 for the compare, however this + * requires the compare value to have those bits also set + * to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes to locate the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type or length field of the frame, for + * example 0 = first byte of type/length field) or the payload + * following an IP header (see bit 26). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicates that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field located within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. If the bit is set, but the frame is not + * an IPv4/v6 frame the parser reports a no match and does + * not continue to inspect the frame. When cleared, the offset + * is used normally on all frames. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represents the byte + * at the given offset and MASK_VAL2[7:0] represents the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields, (for example setting a compare + * value of 0x0800 and offset 0 matches IP frames). No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When + * set, the parser reports a match if the byte at given offset + * matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER4_b; + }; + + union + { + __IOM uint32_t GPARSER5; /*!< (@ 0x000000E4) [n - 3]th Parser of 2nd Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask are compared with the data in the frame. All + * bits having a 0 will be 0 for the compare, however this + * requires the compare value to have those bits also set + * to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes to locate the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type or length field of the frame, for + * example 0 = first byte of type/length field) or the payload + * following an IP header (see bit 26). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicates that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field located within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. If the bit is set, but the frame is not + * an IPv4/v6 frame the parser reports a no match and does + * not continue to inspect the frame. When cleared, the offset + * is used normally on all frames. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represents the byte + * at the given offset and MASK_VAL2[7:0] represents the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields, (for example setting a compare + * value of 0x0800 and offset 0 matches IP frames). No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When + * set, the parser reports a match if the byte at given offset + * matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER5_b; + }; + + union + { + __IOM uint32_t GPARSER6; /*!< (@ 0x000000E8) [n - 3]th Parser of 2nd Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask are compared with the data in the frame. All + * bits having a 0 will be 0 for the compare, however this + * requires the compare value to have those bits also set + * to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes to locate the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type or length field of the frame, for + * example 0 = first byte of type/length field) or the payload + * following an IP header (see bit 26). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicates that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field located within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. If the bit is set, but the frame is not + * an IPv4/v6 frame the parser reports a no match and does + * not continue to inspect the frame. When cleared, the offset + * is used normally on all frames. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represents the byte + * at the given offset and MASK_VAL2[7:0] represents the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields, (for example setting a compare + * value of 0x0800 and offset 0 matches IP frames). No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When + * set, the parser reports a match if the byte at given offset + * matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER6_b; + }; + + union + { + __IOM uint32_t GPARSER7; /*!< (@ 0x000000EC) [n - 3]th Parser of 2nd Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask are compared with the data in the frame. All + * bits having a 0 will be 0 for the compare, however this + * requires the compare value to have those bits also set + * to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes to locate the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type or length field of the frame, for + * example 0 = first byte of type/length field) or the payload + * following an IP header (see bit 26). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicates that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field located within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. If the bit is set, but the frame is not + * an IPv4/v6 frame the parser reports a no match and does + * not continue to inspect the frame. When cleared, the offset + * is used normally on all frames. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represents the byte + * at the given offset and MASK_VAL2[7:0] represents the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields, (for example setting a compare + * value of 0x0800 and offset 0 matches IP frames). No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When + * set, the parser reports a match if the byte at given offset + * matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER7_b; + }; + + union + { + __IOM uint32_t GARITH4; /*!< (@ 0x000000F0) Snoop Configuration for Arithmetic [n - 3]th + * Stage of 2nd Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH4_b; + }; + + union + { + __IOM uint32_t GARITH5; /*!< (@ 0x000000F4) Snoop Configuration for Arithmetic [n - 3]th + * Stage of 2nd Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH5_b; + }; + + union + { + __IOM uint32_t GARITH6; /*!< (@ 0x000000F8) Snoop Configuration for Arithmetic [n - 3]th + * Stage of 2nd Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH6_b; + }; + + union + { + __IOM uint32_t GARITH7; /*!< (@ 0x000000FC) Snoop Configuration for Arithmetic [n - 3]th + * Stage of 2nd Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH7_b; + }; + + union + { + __IOM uint32_t VLAN_PRIORITY[4]; /*!< (@ 0x00000100) VLAN Priority Register [0..3] */ + + struct + { + __IOM uint32_t PRIORITY0 : 3; /*!< [2..0] Priority 0 Setting */ + __IOM uint32_t PRIORITY1 : 3; /*!< [5..3] Priority 1 Setting */ + __IOM uint32_t PRIORITY2 : 3; /*!< [8..6] Priority 2 Setting */ + __IOM uint32_t PRIORITY3 : 3; /*!< [11..9] Priority 3 Setting */ + __IOM uint32_t PRIORITY4 : 3; /*!< [14..12] Priority 4 Setting */ + __IOM uint32_t PRIORITY5 : 3; /*!< [17..15] Priority 5 Setting */ + __IOM uint32_t PRIORITY6 : 3; /*!< [20..18] Priority 6 Setting */ + __IOM uint32_t PRIORITY7 : 3; /*!< [23..21] Priority 7 Setting */ + uint32_t : 8; + } VLAN_PRIORITY_b[4]; + }; + __IM uint32_t RESERVED3[12]; + + union + { + __IOM uint32_t IP_PRIORITY[4]; /*!< (@ 0x00000140) IP Priority Register [0..3] */ + + struct + { + __IOM uint32_t ADDRESS : 8; /*!< [7..0] COS Table Address Specifying */ + __IOM uint32_t IPV6SELECT : 1; /*!< [8..8] IPv6 COS Table Selection */ + __IOM uint32_t PRIORITY : 3; /*!< [11..9] COS Table Priority */ + uint32_t : 19; + __IOM uint32_t READ : 1; /*!< [31..31] COS Table Operation Switching */ + } IP_PRIORITY_b[4]; + }; + __IM uint32_t RESERVED4[12]; + + union + { + __IOM uint32_t PRIORITY_CFG[4]; /*!< (@ 0x00000180) Priority Configuration Register [0..3] */ + + struct + { + __IOM uint32_t VLANEN : 1; /*!< [0..0] VLAN Priority Enable */ + __IOM uint32_t IPEN : 1; /*!< [1..1] IP Priority Enable */ + __IOM uint32_t MACEN : 1; /*!< [2..2] MAC Based Priority Enable */ + __IOM uint32_t TYPE_EN : 1; /*!< [3..3] TYPE Based Priority Enable */ + __IOM uint32_t DEFAULTPRI : 3; /*!< [6..4] Default Priority Enable Setting */ + uint32_t : 25; + } PRIORITY_CFG_b[4]; + }; + __IM uint32_t RESERVED5[10]; + + union + { + __IOM uint32_t PRIORITY_TYPE1; /*!< (@ 0x000001B8) Priority Type Register 1 */ + + struct + { + __IOM uint32_t TYPEVAL : 16; /*!< [15..0] Type Priority */ + __IOM uint32_t VALID : 1; /*!< [16..16] If set indicates, this register contains valid data. */ + __IOM uint32_t PRIORITY : 3; /*!< [19..17] The priority value to use if a match occurs. */ + uint32_t : 12; + } PRIORITY_TYPE1_b; + }; + + union + { + __IOM uint32_t PRIORITY_TYPE2; /*!< (@ 0x000001BC) Priority Type Register 2 */ + + struct + { + __IOM uint32_t TYPEVAL : 16; /*!< [15..0] Type Priority */ + __IOM uint32_t VALID : 1; /*!< [16..16] If set indicates, this register contains valid data. */ + __IOM uint32_t PRIORITY : 3; /*!< [19..17] The priority value to use if a match occurs. */ + uint32_t : 12; + } PRIORITY_TYPE2_b; + }; + __IOM R_ETHSW_MGMT_ADDR_Type MGMT_ADDR[4]; /*!< (@ 0x000001C0) MAC Address [0..3] for Bridge Protocol Frame + * Register */ + + union + { + __IOM uint32_t SRCFLT_ENA; /*!< (@ 0x000001E0) MAC Source Address Filtering Enable Register */ + + struct + { + __IOM uint32_t SRCENA : 3; /*!< [2..0] Per-Source Port Enable */ + uint32_t : 13; + __IOM uint32_t DSTENA : 4; /*!< [19..16] Per-Destination Port Enable */ + uint32_t : 12; + } SRCFLT_ENA_b; + }; + + union + { + __IOM uint32_t SRCFLT_CONTROL; /*!< (@ 0x000001E4) MAC Source Address Filtering Control Register */ + + struct + { + __IOM uint32_t MGMT_FWD : 1; /*!< [0..0] Management Forward Enable */ + __IOM uint32_t WATCHDOG_ENA : 1; /*!< [1..1] When set to 1, a watchdog is enabled. */ + uint32_t : 14; + __IOM uint32_t WATCHDOG_TIME : 16; /*!< [31..16] Defines the watchdog expire time in milliseconds. The + * default is 2000 milliseconds. */ + } SRCFLT_CONTROL_b; + }; + + union + { + __IOM uint32_t SRCFLT_MACADDR_LO; /*!< (@ 0x000001E8) Lower MAC Filtering Address Register */ + + struct + { + __IOM uint32_t SRCFLT_MACADDR : 32; /*!< [31..0] MAC address to use in source filtering */ + } SRCFLT_MACADDR_LO_b; + }; + + union + { + __IOM uint32_t SRCFLT_MACADDR_HI; /*!< (@ 0x000001EC) Higher MAC Filtering Address Register */ + + struct + { + __IOM uint32_t SRCFLT_MACADDR : 16; /*!< [15..0] MAC address to use in source filtering */ + __IOM uint32_t MASK : 16; /*!< [31..16] The mask to apply to the last 16 bits of the MAC address */ + } SRCFLT_MACADDR_HI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t PHY_FILTER_CFG; /*!< (@ 0x000001FC) Debounce Filter Configuration Register */ + + struct + { + __IOM uint32_t FILTER_DURATION : 9; /*!< [8..0] This is the amount of time to wait after the last phy_link + * (ETHSW_PHYLINKn: n = port) transition from 0 to 1 to acknowledge + * the link-up condition. */ + uint32_t : 7; + __IOM uint32_t FLT_EN : 3; /*!< [18..16] Per-port Enable Mask */ + uint32_t : 13; + } PHY_FILTER_CFG_b; + }; + + union + { + __IOM uint32_t SYSTEM_TAGINFO[4]; /*!< (@ 0x00000200) One VLAN ID Field [0..3] for VLAN Input Manipulation */ + + struct + { + __IOM uint32_t SYSVLANINFO : 16; /*!< [15..0] System VLAN Info (prio/cfi/vid) for Port n */ + uint32_t : 16; + } SYSTEM_TAGINFO_b[4]; + }; + __IM uint32_t RESERVED7[12]; + + union + { + __IOM uint32_t AUTH_PORT[4]; /*!< (@ 0x00000240) Port [0..3] Authentication Control and Configuration */ + + struct + { + __IOM uint32_t AUTH : 1; /*!< [0..0] Authorized */ + __IOM uint32_t CTRL_BOTH : 1; /*!< [1..1] Controlled Both */ + __IOM uint32_t EAPOL_EN : 1; /*!< [2..2] EAPOL Enable */ + __IOM uint32_t GUEST_EN : 1; /*!< [3..3] Guest Enable */ + __IOM uint32_t BPDU_EN : 1; /*!< [4..4] BPDU Enable */ + __IOM uint32_t EAPOL_UC_EN : 1; /*!< [5..5] EAPOL Unicast Enable */ + uint32_t : 5; + __IOM uint32_t ACHG_UNAUTH : 1; /*!< [11..11] Automatic Port Change to Unauthorized */ + __IOM uint32_t EAPOL_PNUM : 4; /*!< [15..12] EAPOL Port Number */ + __IOM uint32_t GUEST_MASK : 4; /*!< [19..16] Destination port mask with all ports that are allowed + * to receive non-EAPOL frames from this port while it is + * unauthorized and guest (GUEST_EN) is enabled. */ + uint32_t : 12; + } AUTH_PORT_b[4]; + }; + __IM uint32_t RESERVED8[12]; + + union + { + __IOM uint32_t VLAN_RES_TABLE[32]; /*!< (@ 0x00000280) 32 VLAN Domain Entries */ + + struct + { + __IOM uint32_t PORTMASK : 4; /*!< [3..0] When this bit is set to 1, it defines a port as a member + * of the VLAN. When bit [28] or bit [29] is set, the tagged + * bit mask is read/written instead of port mask. */ + __IOM uint32_t VLANID : 12; /*!< [15..4] The 12-bit VLAN identifier (VLAN ID) of the entry. */ + uint32_t : 12; + __IOM uint32_t RD_TAGMSK : 1; /*!< [28..28] Read TAG Mask */ + __IOM uint32_t WT_TAGMSK : 1; /*!< [29..29] Write TAG Mask */ + __IOM uint32_t WT_PRTMSK : 1; /*!< [30..30] Write Port Mask */ + uint32_t : 1; + } VLAN_RES_TABLE_b[32]; + }; + + union + { + __IM uint32_t TOTAL_DISC; /*!< (@ 0x00000300) Discarded Frame Total Number Register */ + + struct + { + __IM uint32_t TOTAL_DISC : 32; /*!< [31..0] Total number of incoming frames accepted by MAC RX but + * discarded in the switch */ + } TOTAL_DISC_b; + }; + + union + { + __IM uint32_t TOTAL_BYT_DISC; /*!< (@ 0x00000304) Discarded Frame Total Bytes Register */ + + struct + { + __IM uint32_t TOTAL_BYT_DISC : 32; /*!< [31..0] Sum of bytes of frames counted in TOTAL_DISC */ + } TOTAL_BYT_DISC_b; + }; + + union + { + __IM uint32_t TOTAL_FRM; /*!< (@ 0x00000308) Processed Frame Total Number Register */ + + struct + { + __IM uint32_t TOTAL_FRM : 32; /*!< [31..0] Total number of incoming frames processed by the switch */ + } TOTAL_FRM_b; + }; + + union + { + __IM uint32_t TOTAL_BYT_FRM; /*!< (@ 0x0000030C) Processed Frame Total Bytes Register */ + + struct + { + __IM uint32_t TOTAL_BYT_FRM : 32; /*!< [31..0] Sum of bytes of frames counted in TOTAL_FRM */ + } TOTAL_BYT_FRM_b; + }; + __IM uint32_t RESERVED9[12]; + + union + { + __IOM uint32_t IALK_CONTROL; /*!< (@ 0x00000340) IA Lookup Function Enable Register */ + + struct + { + __IOM uint32_t IA_LKUP_ENA : 4; /*!< [3..0] Per-port Enable to the IA Lookup Table */ + uint32_t : 12; + __IOM uint32_t CT_ENA : 4; /*!< [19..16] Per-port Cut-Through Mode Enable */ + uint32_t : 12; + } IALK_CONTROL_b; + }; + + union + { + __IOM uint32_t IALK_OUI; /*!< (@ 0x00000344) IA Frames MAC Address OUI Register */ + + struct + { + __IOM uint32_t IALK_OUI : 24; /*!< [23..0] IA Frames MAC Address OUI */ + uint32_t : 8; + } IALK_OUI_b; + }; + + union + { + __IOM uint32_t IALK_ID_MIN; /*!< (@ 0x00000348) Minimum Value ID MAC Address Register */ + + struct + { + __IOM uint32_t IALK_ID_MIN : 24; /*!< [23..0] Minimum value for the 24-bit ID in the MAC address */ + uint32_t : 8; + } IALK_ID_MIN_b; + }; + + union + { + __IOM uint32_t IALK_ID_MAX; /*!< (@ 0x0000034C) Maximum Value ID MAC Address Register */ + + struct + { + __IOM uint32_t IALK_ID_MAX : 24; /*!< [23..0] Maximum value for the 24-bit ID in the MAC address */ + uint32_t : 8; + } IALK_ID_MAX_b; + }; + + union + { + __IOM uint32_t IALK_ID_SUB; /*!< (@ 0x00000350) Offset Value ID MAC Address Register */ + + struct + { + __IOM uint32_t IALK_ID_SUB : 24; /*!< [23..0] Offset value to subtract from the 24-bit ID in the MAC + * address */ + uint32_t : 8; + } IALK_ID_SUB_b; + }; + + union + { + __IOM uint32_t IALK_ID_CONFIG; /*!< (@ 0x00000354) Configures Lookup Response Unknown IDs Register */ + + struct + { + __IOM uint32_t INVLD_ID_FLOOD : 1; /*!< [0..0] Setting this bit to 1 causes the IA table to return a + * found response for frames whose ID lies outside the ID + * range defined by [IA_LK_MAX:IA_LK_MIN] using INVLD_ID_FLOOD_MASK[3:0] + * bits. */ + __IOM uint32_t INVLD_ID_LRN_ENA : 1; /*!< [1..1] Setting this bit to 1 allows automatic learning into + * the L2 FDB for frames with unknown IDs. When 0, learning + * is inhibited. This bit is only valid when INVLD_ID_FLOOD + * bit is set to 1. */ + uint32_t : 2; + __IOM uint32_t INVLD_ID_PRIO : 3; /*!< [6..4] Priority to use for found responses of an invalid ID. + * This bit is only valid when INVLD_ID_FLOOD bit is set to + * 1. */ + __IOM uint32_t INVLD_ID_PRIO_VLD : 1; /*!< [7..7] Indicates if the priority in INVLD_ID_PRIO is valid. + * This bit is valid only when INVLD_ID_FLOOD bit is set to + * 1. */ + uint32_t : 8; + __IOM uint32_t INVLD_ID_FLOOD_MASK : 4; /*!< [19..16] Forwarding mask used for frames whose ID is invalid. + * This bit is only valid when INVLD_ID_FLOOD bit is set to + * 1. Setting this mask to 0 causes the frame to be dropped. */ + uint32_t : 12; + } IALK_ID_CONFIG_b; + }; + + union + { + __IOM uint32_t IALK_VLAN_CONFIG; /*!< (@ 0x00000358) Configure Lookup Response Unknown VLAN Register */ + + struct + { + __IOM uint32_t UNKWN_VLAN_FLOOD : 1; /*!< [0..0] When this bit is set to 1, a frame matching the OUI and + * with a valid ID but having a VLAN ID not matching any of + * the enabled values in IALK_VLANIDn causes the IA table + * to return a found response using the forwarding mask in + * UNKWN_VLAN_FLOOD_MASK[3:0]. */ + __IOM uint32_t UNKWN_VLAN_LRN_ENA : 1; /*!< [1..1] Setting this bit to 1 allows automatic learning into + * the L2 FDB for frames with unknown VLANs. When 0, learning + * is inhibited. This bit is only valid when UNKWN_VLAN_FLOOD + * bit is set to 1. */ + uint32_t : 2; + __IOM uint32_t UNKWN_VLAN_PRIO : 3; /*!< [6..4] Priority to use for found responses for an unknown VLAN. + * This bit is only valid when UNKWN_VLAN_FLOOD bit is set + * to 1. */ + __IOM uint32_t UNKWN_VLAN_PRIO_VLD : 1; /*!< [7..7] Indicates if the priority in UNKWN_VLAN_PRIO[2:0] is + * valid. This bit is only valid when UNKWN_VLAN_FLOOD bit + * is set to 1. */ + __IOM uint32_t VLANS_ENABLED : 3; /*!< [10..8] Configures the logical geometry of the IA table by specifying + * the number of distinct VLAN IDs enabled. When set to 0, + * no VLANs are supported and the VLAN ID for the frames is + * ignored. */ + uint32_t : 5; + __IOM uint32_t UNKWN_VLAN_FLOOD_MASK : 4; /*!< [19..16] Forwarding mask used for frames with an unknown VLAN + * ID. */ + uint32_t : 12; + } IALK_VLAN_CONFIG_b; + }; + + union + { + __IOM uint32_t IALK_TBL_ADDR; /*!< (@ 0x0000035C) IA Lookup Database Address Register */ + + struct + { + __IOM uint32_t ADDR : 13; /*!< [12..0] Defines the address to write to or read from the IA + * Lookup table */ + uint32_t : 15; + __IOM uint32_t AINC : 4; /*!< [31..28] Auto-Increment Control */ + } IALK_TBL_ADDR_b; + }; + + union + { + __IOM uint32_t IALK_TBL_DATA; /*!< (@ 0x00000360) IA Lookup Database Data Register */ + + struct + { + __IOM uint32_t VALID : 1; /*!< [0..0] Indicates whether the entry indicated by ADDR is valid + * or not. */ + __IOM uint32_t FWD_MASK : 4; /*!< [4..1] Forwarding mask used for lookups that hit the entry and + * when VALID is set to 1. */ + uint32_t : 27; + } IALK_TBL_DATA_b; + }; + __IM uint32_t RESERVED10[7]; + + union + { + __IOM uint32_t IALK_VLANID[4]; /*!< (@ 0x00000380) IA Lookup VLANIDn Register */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] Configure the VLAN ID to be used for VLAN n (n: IALK_VLAN_CONFIG.VLANS + * ENABLED). This bit is only valid when VLANID_ENA bit is + * set to 1. A value of 0 matches any VLAN ID. */ + __IOM uint32_t VLANID_ENA : 1; /*!< [12..12] Enables this VLAN ID. When set to 1, the VLAN ID of + * the frame is compared against VLANID[11:0]. */ + __IOM uint32_t VLANID_LRN_ENA : 1; /*!< [13..13] Configures whether automatic learning in the L2 FDB + * is allowed for frames matching VLAN ID. This also includes + * frames that match the VLAN ID and that the entry in the + * IA table is invalid. */ + uint32_t : 2; + __IOM uint32_t VLANID_FLOOD_MASK : 4; /*!< [19..16] Flooding mask to be used for frames matching this VLAN + * ID but with an invalid entry in the IA table. */ + uint32_t : 8; + __IOM uint32_t VLANID_PRIO : 3; /*!< [30..28] Priority to use for found responses. */ + __IOM uint32_t VLANID_PRIO_VLD : 1; /*!< [31..31] Indicates if the priority in VLANID_PRIO[2:0] is valid. */ + } IALK_VLANID_b[4]; + }; + __IM uint32_t RESERVED11[12]; + + union + { + __IM uint32_t IMC_QLEVEL_P[4]; /*!< (@ 0x000003C0) Port [0..3] Queued Frame Count Register */ + + struct + { + __IM uint32_t QUEUE0 : 4; /*!< [3..0] A 4-bit value per queue indicating the number of frames + * stored in queue 0 */ + __IM uint32_t QUEUE1 : 4; /*!< [7..4] A 4-bit value per queue indicating the number of frames + * stored in queue 1 */ + __IM uint32_t QUEUE2 : 4; /*!< [11..8] A 4-bit value per queue indicating the number of frames + * stored in queue 2 */ + __IM uint32_t QUEUE3 : 4; /*!< [15..12] A 4-bit value per queue indicating the number of frames + * stored in queue 3 */ + __IM uint32_t QUEUE4 : 4; /*!< [19..16] A 4-bit value per queue indicating the number of frames + * stored in queue 4 */ + __IM uint32_t QUEUE5 : 4; /*!< [23..20] A 4-bit value per queue indicating the number of frames + * stored in queue 5 */ + __IM uint32_t QUEUE6 : 4; /*!< [27..24] A 4-bit value per queue indicating the number of frames + * stored in queue 6 */ + __IM uint32_t QUEUE7 : 4; /*!< [31..28] A 4-bit value per queue indicating the number of frames + * stored in queue 7 */ + } IMC_QLEVEL_P_b[4]; + }; + __IM uint32_t RESERVED12[12]; + + union + { + __IOM uint32_t LK_CTRL; /*!< (@ 0x00000400) Learning/Lookup Function Global Configuration + * Register */ + + struct + { + __IOM uint32_t LKUP_EN : 1; /*!< [0..0] Lookup Controller Enable */ + __IOM uint32_t LEARN_EN : 1; /*!< [1..1] Learning Enable */ + __IOM uint32_t AGING_EN : 1; /*!< [2..2] Aging Enable */ + __IOM uint32_t ALW_MGRT : 1; /*!< [3..3] Allow Migration */ + __IOM uint32_t DISC_UNK_DEST : 1; /*!< [4..4] Discard Unknown Destination */ + uint32_t : 1; + __IOM uint32_t CLRTBL : 1; /*!< [6..6] Clear Table */ + __IOM uint32_t IND_VLAN : 1; /*!< [7..7] Enable Independent VLAN Learning */ + uint32_t : 8; + __IOM uint32_t DISC_UNK_SRC : 4; /*!< [19..16] Discard Unknown Source */ + uint32_t : 12; + } LK_CTRL_b; + }; + + union + { + __IOM uint32_t LK_STATUS; /*!< (@ 0x00000404) Status Bits and Table Overflow Counter Register */ + + struct + { + __IM uint32_t AGEADDR : 16; /*!< [15..0] Address the aging process will inspect when the aging + * timer expires next time. */ + __IOM uint32_t OVRF : 14; /*!< [29..16] Counts number of table overflows that occurred (a new + * address was learned but the table had no storage and an + * older entry was deleted). The counter is cleared by writing + * into the register and having bit 16 set to 1. */ + uint32_t : 1; + __IOM uint32_t LRNEVNT : 1; /*!< [31..31] Learn Event */ + } LK_STATUS_b; + }; + + union + { + __IOM uint32_t LK_ADDR_CTRL; /*!< (@ 0x00000408) Address Table Transaction Control and Read/Write + * Address */ + + struct + { + __IOM uint32_t ADDR_MSK : 12; /*!< [11..0] Memory address for read and write transactions. This + * is the address of a 69-bit entry. For the DEL_PORT bit, + * a port mask can be provided in these bits instead of the + * address. Bit 0 represents port 0, bit 1 port 1, and so + * on. */ + uint32_t : 10; + __IOM uint32_t CLR_DYNAMIC : 1; /*!< [22..22] When set to 1, scans the complete table for valid dynamic + * entries and deletes them (writes entry with all 0s). This + * bit is cleared when the function has completed. */ + __IOM uint32_t CLR_STATIC : 1; /*!< [23..23] When set to 1, scans the complete table for valid static + * entries and deletes them (writes entry with all 0s). This + * bit is cleared when the function has completed. */ + __IOM uint32_t GETLASTNEW : 1; /*!< [24..24] When set to 1, retrieves the last source address that + * was not found in the table and places it into LK_DATA_LO/HI/HI2. + * The valid bit of the entry (bit LK_DATA_HI[16]) indicates + * if the address is new (when valid bit is 1) or not (when + * valid bit is 0) since the command was last issued. */ + __IOM uint32_t WRITE : 1; /*!< [25..25] When set to 1, perform a single write transaction. */ + __IOM uint32_t READ : 1; /*!< [26..26] When set to 1, perform a single read transaction. */ + __IOM uint32_t WAIT_COMP : 1; /*!< [27..27] When set to 1, instructs to stall the processor bus + * until the transaction is completed. This allows performing + * of consecutive writes into this register with varying commands + * without the need for polling the BUSY bit. */ + __IM uint32_t LOOKUP : 1; /*!< [28..28] When set to 1, perform a lookup of the MAC address + * given in LK_DATA_LO/HI/HI2. */ + __IOM uint32_t CLEAR : 1; /*!< [29..29] When set to 1, writes all 0s to the entry selected + * by the given address set in ADDR_MSK[11:0]. If this bit + * is set together with the LOOKUP bit, first a lookup is + * performed and if the lookup succeeds, the entry is then + * deleted. The registers LK_DATA_LO/HI/HI2 are also cleared. + * The memory address in this register is set from the lookup + * result. If the lookup failed, the clear command is ignored + * and memory address is arbitrary. */ + __IOM uint32_t DEL_PORT : 1; /*!< [30..30] When set to 1, scans the complete table for valid dynamic + * entries that contain the given ports in their destination + * port mask and deletes the ports or the complete entry. + * The port mask is provided in the ADDR_MSK[3:0] when writing + * this register (1 bit per port, bit 0 = port 0, bit 1 = + * port 1, and so on). */ + __IM uint32_t BUSY : 1; /*!< [31..31] Transaction Busy Indication */ + } LK_ADDR_CTRL_b; + }; + + union + { + __IOM uint32_t LK_DATA_LO; /*!< (@ 0x0000040C) Lower 32-Bit Data of Lookup Memory Entry */ + + struct + { + __IOM uint32_t MEMDATA : 32; /*!< [31..0] Memory Data [31:0] */ + } LK_DATA_LO_b; + }; + + union + { + __IOM uint32_t LK_DATA_HI; /*!< (@ 0x00000410) Higher 25-Bit Data of Lookup Memory Entry */ + + struct + { + __IOM uint32_t MEMDATA : 25; /*!< [24..0] Memory Data [56:32] */ + uint32_t : 7; + } LK_DATA_HI_b; + }; + + union + { + __IOM uint32_t LK_DATA_HI2; /*!< (@ 0x00000414) Higher2 12-Bit Data of Lookup Memory Entry */ + + struct + { + uint32_t : 8; + __IOM uint32_t MEMDATA : 12; /*!< [19..8] Memory Data [68:57] */ + uint32_t : 12; + } LK_DATA_HI2_b; + }; + + union + { + __IOM uint32_t LK_LEARNCOUNT; /*!< (@ 0x00000418) Learned Address Count Register */ + + struct + { + __IOM uint32_t LEARNCOUNT : 13; /*!< [12..0] Number of Learned Addresses */ + uint32_t : 17; + __IOM uint32_t WRITE_MD : 2; /*!< [31..30] These bits define how the LEARNCOUNT value is modified + * when writing into the register: */ + } LK_LEARNCOUNT_b; + }; + + union + { + __IOM uint32_t LK_AGETIME; /*!< (@ 0x0000041C) Period of the Aging Timer */ + + struct + { + __IOM uint32_t AGETIME : 24; /*!< [23..0] 24-bit Timer Value */ + uint32_t : 8; + } LK_AGETIME_b; + }; + __IM uint32_t RESERVED13[24]; + + union + { + __IOM uint32_t MGMT_TAG_CONFIG; /*!< (@ 0x00000480) Management Tag Configuration Register */ + + struct + { + __IOM uint32_t ENABLE : 1; /*!< [0..0] Enable Management Tag Insertion Module */ + __IOM uint32_t AL_FRAMES : 1; /*!< [1..1] Enable Tag Insertion for All Frames */ + uint32_t : 2; + __IOM uint32_t TYPE1_EN : 1; /*!< [4..4] When set, frames with a Type field that match the value + * in PRIORITY_TYPE1.TYPEVAL[15:0] have management tag inserted. + * This is in addition to BPDU frames which always have tag + * inserted. */ + __IOM uint32_t TYPE2_EN : 1; /*!< [5..5] When set, frames with a Type field that match the value + * in PRIORITY_TYPE2.TYPEVAL[15:0] have management tag inserted. + * This is in addition to BPDU frames which always have tag + * inserted. */ + uint32_t : 10; + __IOM uint32_t TAGFIELD : 16; /*!< [31..16] The value of the tag that is found in the first Type/Length + * field of the frame to identify that the control information + * is present within a frame. For example, [31:24] = first + * octet, [23:16] = 2nd octet. */ + } MGMT_TAG_CONFIG_b; + }; + __IM uint32_t RESERVED14[32]; + + union + { + __IOM uint32_t TSM_CONFIG; /*!< (@ 0x00000504) Timestamping Control Module Configuration Register */ + + struct + { + __IOM uint32_t IRQ_EN : 1; /*!< [0..0] Final Interrupt enable */ + __IOM uint32_t IRQ_TEST : 1; /*!< [1..1] Software controlled interrupt for testing purposes */ + __IOM uint32_t IRQ_TSFIFO_OVR : 1; /*!< [2..2] Trigger interrupt enable for Transmit Timestamp Capture + * Overflow event */ + uint32_t : 1; + __IOM uint32_t IRQ_EVT_OFFSET : 2; /*!< [5..4] Per-timer Trigger interrupt enable for the timer offset + * event */ + uint32_t : 2; + __IOM uint32_t IRQ_EVT_PERIOD : 2; /*!< [9..8] Per-timer Trigger interrupt enable for the timer periodical + * event */ + uint32_t : 2; + __IOM uint32_t IRQ_ATIME_OVER : 2; /*!< [13..12] Per-timer Trigger interrupt enable for the timer wrap + * (reached its maximum) */ + uint32_t : 2; + __IOM uint32_t IRQ_TX_EN : 4; /*!< [19..16] Per Port Transmit Timestamp Capture Interrupt Enable */ + uint32_t : 12; + } TSM_CONFIG_b; + }; + + union + { + __IOM uint32_t TSM_IRQ_STAT_ACK; /*!< (@ 0x00000508) Interrupt Status/Acknowledge Register */ + + struct + { + __IM uint32_t IRQ_STAT : 1; /*!< [0..0] Interrupt Pending Status */ + __IOM uint32_t IRQ_TEST : 1; /*!< [1..1] Test Interrupt Pending Status */ + __IM uint32_t IRQ_TSFIFO_OVR : 1; /*!< [2..2] Transmit Timestamp Capture Overflow Interrupt Pending + * Status */ + uint32_t : 1; + __IOM uint32_t IRQ_EVT_OFFSET : 2; /*!< [5..4] Per-timer Offset Interrupt Pending Status */ + uint32_t : 2; + __IOM uint32_t IRQ_EVT_PERIOD : 2; /*!< [9..8] Per-timer Periodical Interrupt Pending Status */ + uint32_t : 2; + __IOM uint32_t IRQ_ATIME_OVER : 2; /*!< [13..12] Per-timer Overflow Interrupt Pending Status */ + uint32_t : 2; + __IOM uint32_t IRQ_TX : 4; /*!< [19..16] Per Port Transmit Timestamp Capture Interrupt */ + uint32_t : 12; + } TSM_IRQ_STAT_ACK_b; + }; + + union + { + __IOM uint32_t PTP_DOMAIN; /*!< (@ 0x0000050C) Domain Number of PTP Frame */ + + struct + { + __IOM uint32_t DOMAIN0 : 8; /*!< [7..0] DomainNumber to Match Against for Timer 0 */ + __IOM uint32_t DOMAIN1 : 8; /*!< [15..8] DomainNumber to Match Against for Timer 1 */ + uint32_t : 16; + } PTP_DOMAIN_b; + }; + __IM uint32_t RESERVED15[12]; + + union + { + __IOM uint32_t PEERDELAY_P0_T0; /*!< (@ 0x00000540) Port 0 Peer Delay Value for Timer 0 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 0 */ + uint32_t : 2; + } PEERDELAY_P0_T0_b; + }; + + union + { + __IOM uint32_t PEERDELAY_P0_T1; /*!< (@ 0x00000544) Port 0 Peer Delay Value for Timer 1 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 1 */ + uint32_t : 2; + } PEERDELAY_P0_T1_b; + }; + __IM uint32_t RESERVED16[2]; + + union + { + __IOM uint32_t PEERDELAY_P1_T0; /*!< (@ 0x00000550) Port 1 Peer Delay Value for Timer 0 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 0 */ + uint32_t : 2; + } PEERDELAY_P1_T0_b; + }; + + union + { + __IOM uint32_t PEERDELAY_P1_T1; /*!< (@ 0x00000554) Port 1 Peer Delay Value for Timer 1 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 1 */ + uint32_t : 2; + } PEERDELAY_P1_T1_b; + }; + __IM uint32_t RESERVED17[2]; + + union + { + __IOM uint32_t PEERDELAY_P2_T0; /*!< (@ 0x00000560) Port 2 Peer Delay Value for Timer 0 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 0 */ + uint32_t : 2; + } PEERDELAY_P2_T0_b; + }; + + union + { + __IOM uint32_t PEERDELAY_P2_T1; /*!< (@ 0x00000564) Port 2 Peer Delay Value for Timer 1 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 1 */ + uint32_t : 2; + } PEERDELAY_P2_T1_b; + }; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint32_t PEERDELAY_P3_T0; /*!< (@ 0x00000570) Port 3 Peer Delay Value for Timer 0 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 0 */ + uint32_t : 2; + } PEERDELAY_P3_T0_b; + }; + + union + { + __IOM uint32_t PEERDELAY_P3_T1; /*!< (@ 0x00000574) Port 3 Peer Delay Value for Timer 1 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 1 */ + uint32_t : 2; + } PEERDELAY_P3_T1_b; + }; + __IM uint32_t RESERVED19[18]; + + union + { + __IOM uint32_t TS_FIFO_STATUS; /*!< (@ 0x000005C0) Transmit Timestamp FIFO Status Register */ + + struct + { + __IM uint32_t FF_VALID : 4; /*!< [3..0] Per-port indication that a valid timestamp is available + * in the corresponding FIFO of the port */ + uint32_t : 12; + __IOM uint32_t FF_OVR : 4; /*!< [19..16] Per-port indication that a timestamp cannot be written + * to the FIFO because of the FIFO being full. */ + uint32_t : 12; + } TS_FIFO_STATUS_b; + }; + + union + { + __IOM uint32_t TS_FIFO_READ_CTRL; /*!< (@ 0x000005C4) Transmit Timestamp FIFO Read Control Register */ + + struct + { + __IOM uint32_t PORT_NUM : 2; /*!< [1..0] Port Number to Read from */ + uint32_t : 2; + __IM uint32_t TS_VALID : 1; /*!< [4..4] When reading from this register, this bit is 1 if the + * FIFO indicated by PORT_NUM contained valid data. */ + uint32_t : 1; + __IM uint32_t TS_SEL : 1; /*!< [6..6] When TS_VALID is 1, TS_SEL indicates the timer used for + * the read timestamp. */ + uint32_t : 1; + __IM uint32_t TS_ID : 7; /*!< [14..8] When TS_VALID is 1, TS_ID indicates the ID specified + * by the application through the management tag control information, + * if present. */ + uint32_t : 17; + } TS_FIFO_READ_CTRL_b; + }; + + union + { + __IM uint32_t TS_FIFO_READ_TIMESTAMP; /*!< (@ 0x000005C8) 32-bit Timestamp Value Read from FIFO */ + + struct + { + __IM uint32_t TIMESTAMP : 32; /*!< [31..0] 32-bit timestamp value read from the FIFO */ + } TS_FIFO_READ_TIMESTAMP_b; + }; + __IM uint32_t RESERVED20[13]; + + union + { + __IOM uint32_t INT_CONFIG; /*!< (@ 0x00000600) Interrupt Enable Configuration Register */ + + struct + { + __IOM uint32_t IRQ_EN : 1; /*!< [0..0] Interrupt Global Enable */ + __IOM uint32_t MDIO1 : 1; /*!< [1..1] Enable Interrupt on Transaction Complete from MDIO Controller */ + uint32_t : 1; + __IOM uint32_t LK_NEW_SRC : 1; /*!< [3..3] Enable Interrupt for New Source Address */ + __IOM uint32_t IRQ_TEST : 1; /*!< [4..4] When set, an interrupt is triggered immediately. Can + * be used to cause a software controlled interrupt for testing + * purposes. */ + __IOM uint32_t DLR_INT : 1; /*!< [5..5] Enable Interrupt for DLR */ + __IOM uint32_t PRP_INT : 1; /*!< [6..6] Enable Interrupt for PRP */ + __IOM uint32_t HUB_INT : 1; /*!< [7..7] Enable Interrupt for HUB */ + __IOM uint32_t IRQ_LINK : 3; /*!< [10..8] Per Line Port Phy Link Change Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t IRQ_MAC_EEE : 3; /*!< [18..16] Per Line Port MAC interrupt */ + uint32_t : 9; + __IOM uint32_t SRCFLT_WD_INT : 1; /*!< [28..28] MAC Address Source Filtering Watchdog */ + __IOM uint32_t TSM_INT : 1; /*!< [29..29] Enable Interrupt for TSM (Timer, Timestamping) */ + __IOM uint32_t TDMA_INT : 1; /*!< [30..30] Enable Interrupt for TDMA scheduler */ + __IOM uint32_t PATTERN_INT : 1; /*!< [31..31] Enable Interrupt for RX Pattern Matcher */ + } INT_CONFIG_b; + }; + + union + { + __IOM uint32_t INT_STAT_ACK; /*!< (@ 0x00000604) Interrupt Status/ACK Register */ + + struct + { + __IM uint32_t IRQ_PEND : 1; /*!< [0..0] Interrupt Pending Status */ + __IOM uint32_t MDIO1 : 1; /*!< [1..1] Latched Interrupt Status for MDIO1 */ + uint32_t : 1; + __IOM uint32_t LK_NEW_SRC : 1; /*!< [3..3] Latched Interrupt Status for LK_NEW_SRC */ + __IM uint32_t IRQ_TEST : 1; /*!< [4..4] Interrupt Status for IRQ_TEST */ + __IM uint32_t DLR_INT : 1; /*!< [5..5] Interrupt Pending Status from DLR Module */ + __IM uint32_t PRP_INT : 1; /*!< [6..6] Interrupt Pending Status from PRP Module */ + __IM uint32_t HUB_INT : 1; /*!< [7..7] Interrupt Pending Status from Hub Module */ + __IOM uint32_t IRQ_LINK : 3; /*!< [10..8] Interrupt Pending per Line Port Phy Link Change Interrupt */ + uint32_t : 5; + __IOM uint32_t IRQ_MAC_EEE : 3; /*!< [18..16] Interrupt Pending Status per Line Port MAC Interrupt */ + uint32_t : 9; + __IOM uint32_t SRCFLT_WD_INT : 1; /*!< [28..28] Interrupt Pending Status for MAC Source Filtering Watchdog */ + __IM uint32_t TSM_INT : 1; /*!< [29..29] Interrupt Pending Interrupt Indication from TSM (Timestamping) + * module */ + __IM uint32_t TDMA_INT : 1; /*!< [30..30] Interrupt Pending Status from TDMA Scheduler */ + __IM uint32_t PATTERN_INT : 1; /*!< [31..31] Interrupt Pending Status from RX Pattern Matcher Module */ + } INT_STAT_ACK_b; + }; + __IM uint32_t RESERVED21[30]; + + union + { + __IOM uint32_t ATIME_CTRL0; /*!< (@ 0x00000680) Timer 0 Control Register (n = 0, 1) */ + + struct + { + __IOM uint32_t ENABLE : 1; /*!< [0..0] ENABLE */ + __IOM uint32_t ONE_SHOT : 1; /*!< [1..1] Avoid timer wrap around. If set, the timer stops at maximum. + * An overflow interrupt (TSM_CONFIG.IRQ_ATIME_OVER) occurs + * (if enabled) when the maximum is reached. */ + __IOM uint32_t EVT_OFFSET_ENA : 1; /*!< [2..2] Enable Offset Event */ + uint32_t : 1; + __IOM uint32_t EVT_PERIOD_ENA : 1; /*!< [4..4] Enable Periodical Event */ + __IOM uint32_t EVT_PERIOD_RST : 1; /*!< [5..5] Reset Timer on Periodical Event */ + uint32_t : 3; + __IOM uint32_t RESTART : 1; /*!< [9..9] Resets the Timer to Zero (Command Bit) */ + uint32_t : 1; + __IOM uint32_t CAPTURE : 1; /*!< [11..11] Capture Time Value (Command Bit) */ + __IOM uint32_t CAPTURE_ALL : 1; /*!< [12..12] Capture All Timers Value (Command Bit) */ + uint32_t : 19; + } ATIME_CTRL0_b; + }; + + union + { + __IOM uint32_t ATIME0; /*!< (@ 0x00000684) Timer 0 Count Register (n = 0, 1) */ + + struct + { + __IOM uint32_t TIMER_VAL : 32; /*!< [31..0] Timer Value */ + } ATIME0_b; + }; + + union + { + __IOM uint32_t ATIME_OFFSET0; /*!< (@ 0x00000688) Timer 0 Offset Register (n = 0, 1) */ + + struct + { + __IOM uint32_t OFFSET : 32; /*!< [31..0] Value used for performing offset corrections without + * changing the drift correction */ + } ATIME_OFFSET0_b; + }; + + union + { + __IOM uint32_t ATIME_EVT_PERIOD0; /*!< (@ 0x0000068C) Timer 0 Periodic Event Register (n = 0, 1) */ + + struct + { + __IOM uint32_t PERIOD : 32; /*!< [31..0] Value for generating periodic events */ + } ATIME_EVT_PERIOD0_b; + }; + + union + { + __IOM uint32_t ATIME_CORR0; /*!< (@ 0x00000690) Timer 0 Correction Period Register (n = 0, 1) */ + + struct + { + __IOM uint32_t CORR_PERIOD : 31; /*!< [30..0] Correction Period */ + uint32_t : 1; + } ATIME_CORR0_b; + }; + + union + { + __IOM uint32_t ATIME_INC0; /*!< (@ 0x00000694) Timer 0 Increment Register (n = 0, 1) */ + + struct + { + __IOM uint32_t CLK_PERIOD : 7; /*!< [6..0] Clock Period of the Timestamping Clock (125 MHz) in nanoseconds */ + uint32_t : 1; + __IOM uint32_t CORR_INC : 7; /*!< [14..8] Correction Increment Value */ + uint32_t : 1; + __IOM uint32_t OFFS_CORR_INC : 7; /*!< [22..16] Offset Correction Increment Value */ + uint32_t : 9; + } ATIME_INC0_b; + }; + + union + { + __IOM uint32_t ATIME_SEC0; /*!< (@ 0x00000698) Timer 0 Seconds Time Register (n = 0, 1) */ + + struct + { + __IOM uint32_t SEC_TIME : 32; /*!< [31..0] Seconds Time Value */ + } ATIME_SEC0_b; + }; + + union + { + __IOM uint32_t ATIME_OFFS_CORR0; /*!< (@ 0x0000069C) Timer 0 Offset Correction Counter Register (n + * = 0, 1) */ + + struct + { + __IOM uint32_t OFFS_CORR_CNT : 32; /*!< [31..0] Offset Correction Counter */ + } ATIME_OFFS_CORR0_b; + }; + + union + { + __IOM uint32_t ATIME_CTRL1; /*!< (@ 0x000006A0) Timer 1 Control Register (n = 0, 1) */ + + struct + { + __IOM uint32_t ENABLE : 1; /*!< [0..0] ENABLE */ + __IOM uint32_t ONE_SHOT : 1; /*!< [1..1] Avoid timer wrap around. If set, the timer stops at maximum. + * An overflow interrupt (TSM_CONFIG.IRQ_ATIME_OVER) occurs + * (if enabled) when the maximum is reached. */ + __IOM uint32_t EVT_OFFSET_ENA : 1; /*!< [2..2] Enable Offset Event */ + uint32_t : 1; + __IOM uint32_t EVT_PERIOD_ENA : 1; /*!< [4..4] Enable Periodical Event */ + __IOM uint32_t EVT_PERIOD_RST : 1; /*!< [5..5] Reset Timer on Periodical Event */ + uint32_t : 3; + __IOM uint32_t RESTART : 1; /*!< [9..9] Resets the Timer to Zero (Command Bit) */ + uint32_t : 1; + __IOM uint32_t CAPTURE : 1; /*!< [11..11] Capture Time Value (Command Bit) */ + __IOM uint32_t CAPTURE_ALL : 1; /*!< [12..12] Capture All Timers Value (Command Bit) */ + uint32_t : 19; + } ATIME_CTRL1_b; + }; + + union + { + __IOM uint32_t ATIME1; /*!< (@ 0x000006A4) Timer 1 Count Register (n = 0, 1) */ + + struct + { + __IOM uint32_t TIMER_VAL : 32; /*!< [31..0] Timer Value */ + } ATIME1_b; + }; + + union + { + __IOM uint32_t ATIME_OFFSET1; /*!< (@ 0x000006A8) Timer 1 Offset Register (n = 0, 1) */ + + struct + { + __IOM uint32_t OFFSET : 32; /*!< [31..0] Value used for performing offset corrections without + * changing the drift correction */ + } ATIME_OFFSET1_b; + }; + + union + { + __IOM uint32_t ATIME_EVT_PERIOD1; /*!< (@ 0x000006AC) Timer 1 Periodic Event Register (n = 0, 1) */ + + struct + { + __IOM uint32_t PERIOD : 32; /*!< [31..0] Value for generating periodic events */ + } ATIME_EVT_PERIOD1_b; + }; + + union + { + __IOM uint32_t ATIME_CORR1; /*!< (@ 0x000006B0) Timer 1 Correction Period Register (n = 0, 1) */ + + struct + { + __IOM uint32_t CORR_PERIOD : 31; /*!< [30..0] Correction Period */ + uint32_t : 1; + } ATIME_CORR1_b; + }; + + union + { + __IOM uint32_t ATIME_INC1; /*!< (@ 0x000006B4) Timer 1 Increment Register (n = 0, 1) */ + + struct + { + __IOM uint32_t CLK_PERIOD : 7; /*!< [6..0] Clock Period of the Timestamping Clock (125 MHz) in nanoseconds */ + uint32_t : 1; + __IOM uint32_t CORR_INC : 7; /*!< [14..8] Correction Increment Value */ + uint32_t : 1; + __IOM uint32_t OFFS_CORR_INC : 7; /*!< [22..16] Offset Correction Increment Value */ + uint32_t : 9; + } ATIME_INC1_b; + }; + + union + { + __IOM uint32_t ATIME_SEC1; /*!< (@ 0x000006B8) Timer 1 Seconds Time Register (n = 0, 1) */ + + struct + { + __IOM uint32_t SEC_TIME : 32; /*!< [31..0] Seconds Time Value */ + } ATIME_SEC1_b; + }; + + union + { + __IOM uint32_t ATIME_OFFS_CORR1; /*!< (@ 0x000006BC) Timer 1 Offset Correction Counter Register (n + * = 0, 1) */ + + struct + { + __IOM uint32_t OFFS_CORR_CNT : 32; /*!< [31..0] Offset Correction Counter */ + } ATIME_OFFS_CORR1_b; + }; + __IM uint32_t RESERVED22[16]; + + union + { + __IOM uint32_t MDIO_CFG_STATUS; /*!< (@ 0x00000700) MDIO Configuration and Status Register */ + + struct + { + __IM uint32_t BUSY : 1; /*!< [0..0] MDIO Busy */ + __IM uint32_t READERR : 1; /*!< [1..1] MDIO Read Error */ + __IOM uint32_t HOLD : 3; /*!< [4..2] MDIO Hold Time Setting */ + __IOM uint32_t DISPREAM : 1; /*!< [5..5] Disable Preamble */ + uint32_t : 1; + __IOM uint32_t CLKDIV : 9; /*!< [15..7] MDIO Clock Divisor */ + uint32_t : 16; + } MDIO_CFG_STATUS_b; + }; + + union + { + __IOM uint32_t MDIO_COMMAND; /*!< (@ 0x00000704) MDIO PHY Command Register */ + + struct + { + __IOM uint32_t REGADDR : 5; /*!< [4..0] Register Address */ + __IOM uint32_t PHYADDR : 5; /*!< [9..5] PHY Address */ + uint32_t : 5; + __IOM uint32_t TRANINIT : 1; /*!< [15..15] If set to 1, a read transaction is initiated. */ + uint32_t : 16; + } MDIO_COMMAND_b; + }; + + union + { + __IOM uint32_t MDIO_DATA; /*!< (@ 0x00000708) MDIO Data Register */ + + struct + { + __IOM uint32_t MDIO_DATA : 16; /*!< [15..0] MDIO_DATA */ + uint32_t : 16; + } MDIO_DATA_b; + }; + __IM uint32_t RESERVED23[61]; + + union + { + __IM uint32_t REV_P0; /*!< (@ 0x00000800) Port 0 MAC Core Revision (n = 0 to 3) */ + + struct + { + __IM uint32_t REV : 32; /*!< [31..0] MAC Core Revision */ + } REV_P0_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t COMMAND_CONFIG_P0; /*!< (@ 0x00000808) Port 0 Command Configuration Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t TX_ENA : 1; /*!< [0..0] Enable/Disable MAC Transmit Path */ + __IOM uint32_t RX_ENA : 1; /*!< [1..1] Enable/Disable MAC Receive Path */ + __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from + * the IMC until the current frame is completed. This can + * cause the IPG between frames to be more than the value + * in TX_IPG_LENGTH. */ + __IOM uint32_t ETH_SPEED : 1; /*!< [3..3] Operation Mode Definition */ + __IM uint32_t PROMIS_EN : 1; /*!< [4..4] Enable/Disable MAC Promiscuous Operation */ + __IM uint32_t PAD_EN : 1; /*!< [5..5] Enable/Disable Frame Padding Remove on Receive */ + uint32_t : 1; + __IM uint32_t PAUSE_FWD : 1; /*!< [7..7] Terminate/Forward Pause Frames */ + __IOM uint32_t PAUSE_IGNORE : 1; /*!< [8..8] Ignore Pause Frame Quanta */ + __IM uint32_t TX_ADDR_INS : 1; /*!< [9..9] Non writable bit, fixed to 0 always. */ + __IOM uint32_t HD_ENA : 1; /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or + * full-duplex only (set to 0). */ + __IOM uint32_t TX_CRC_APPEND : 1; /*!< [11..11] Enable CRC Append on Transmit */ + uint32_t : 1; + __IOM uint32_t SW_RESET : 1; /*!< [13..13] Self Clearing Reset Command Bit */ + uint32_t : 9; + __IOM uint32_t CNTL_FRM_ENA : 1; /*!< [23..23] MAC Control Frame Enable */ + __IOM uint32_t NO_LGTH_CHK : 1; /*!< [24..24] Payload Length Check Disable */ + __IOM uint32_t ENA_10 : 1; /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn + * register. */ + uint32_t : 4; + __IOM uint32_t TIMER_SEL : 1; /*!< [30..30] Selects the default timer to use for timestamping operations + * on transmit and on receive. The value is used when not + * overridden by the PTP auto-response function, pattern matchers + * or force forwarding information in a management tag. */ + uint32_t : 1; + } COMMAND_CONFIG_P0_b; + }; + + union + { + __IOM uint32_t MAC_ADDR_0_P0; /*!< (@ 0x0000080C) Port 0 MAC Address Register 0 (n = 0 to 2) */ + + struct + { + __IOM uint32_t MAC_ADDR : 32; /*!< [31..0] The first 4 bytes of the MAC address of the port. First + * byte is bits [7:0]. The MAC address is used on locally + * generated frames such as pause frames, peer-delay response. */ + } MAC_ADDR_0_P0_b; + }; + + union + { + __IOM uint32_t MAC_ADDR_1_P0; /*!< (@ 0x00000810) Port 0 MAC Address Register 1 (n = 0 to 2) */ + + struct + { + __IOM uint32_t MAC_ADDR : 16; /*!< [15..0] The last 2 bytes of the MAC address of the port. Bits + * [7:0] is the 5th byte and bits [15:8] is the 6th byte. */ + uint32_t : 16; + } MAC_ADDR_1_P0_b; + }; + + union + { + __IOM uint32_t FRM_LENGTH_P0; /*!< (@ 0x00000814) Port 0 Maximum Frame Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length */ + uint32_t : 18; + } FRM_LENGTH_P0_b; + }; + + union + { + __IM uint32_t PAUSE_QUANT_P0; /*!< (@ 0x00000818) Port 0 MAC Pause Quanta (n = 0 to 3) */ + + struct + { + __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta */ + uint32_t : 16; + } PAUSE_QUANT_P0_b; + }; + + union + { + __IOM uint32_t MAC_LINK_QTRIG_P0; /*!< (@ 0x0000081C) Port 0 Trigger Event Configuration Register (n + * = 0 to 2) */ + + struct + { + __IOM uint32_t PORT_MASK : 4; /*!< [3..0] Per-port Bit Mask */ + uint32_t : 12; + __IOM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame + * is transmitted from the ports indicated by PORT_MASK. A + * single frame is transmitted per indicated port in PORT_MASK + * among the queues indicated by QUEUE_MASK. */ + uint32_t : 4; + __IOM uint32_t TRIGGERED : 1; /*!< [28..28] When MODE is set to 1, TRIGGERED indicates whether + * a frame was transmitted. When MODE is set to 0, TRIGGERED + * is always 0. This flag clears when the register is written. */ + __IOM uint32_t DLR_MODE : 1; /*!< [29..29] When set to 0, the DLR state machine is ignored. When + * set to 1, the Link Queue Trigger occurs only if the DLR + * state machine is in the NORMAL or FAULT state. */ + __IOM uint32_t MODE : 1; /*!< [30..30] When set to 0, only a single Link_Status frame is generated. + * This is to prevent sending multiple frames due to link + * flapping. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Write to 1 to enable the Link Queue Trigger feature. + * When the link status (phy_link) transitions from 1 -> + * 0, a trigger event is generated to the memory controller + * for the ports and queues indicated in PORT_MASK and QUEUE_MASK. */ + } MAC_LINK_QTRIG_P0_b; + }; + __IM uint32_t RESERVED25[4]; + + union + { + __IOM uint32_t PTPCLOCKIDENTITY1_P0; /*!< (@ 0x00000830) Port 0 PTP Clock Identity 1 Register (n = 0 to + * 2) */ + + struct + { + __IOM uint32_t CLK_IDENTITY0 : 8; /*!< [7..0] 20, portIdentity.ClockIdentity[0] */ + __IOM uint32_t CLK_IDENTITY1 : 8; /*!< [15..8] 21, portIdentity.ClockIdentity[1] */ + __IOM uint32_t CLK_IDENTITY2 : 8; /*!< [23..16] 22, portIdentity.ClockIdentity[2] */ + __IOM uint32_t CLK_IDENTITY3 : 8; /*!< [31..24] 23, portIdentity.ClockIdentity[3] */ + } PTPCLOCKIDENTITY1_P0_b; + }; + + union + { + __IOM uint32_t PTPCLOCKIDENTITY2_P0; /*!< (@ 0x00000834) Port 0 PTP Clock Identity 2 Register (n = 0 to + * 2) */ + + struct + { + __IOM uint32_t CLK_IDENTITY4 : 8; /*!< [7..0] 24, portIdentity.ClockIdentity[4] */ + __IOM uint32_t CLK_IDENTITY5 : 8; /*!< [15..8] 25, portIdentity.ClockIdentity[5] */ + __IOM uint32_t CLK_IDENTITY6 : 8; /*!< [23..16] 26, portIdentity.ClockIdentity[6] */ + __IOM uint32_t CLK_IDENTITY7 : 8; /*!< [31..24] 27, portIdentity.ClockIdentity[7] */ + } PTPCLOCKIDENTITY2_P0_b; + }; + + union + { + __IOM uint32_t PTPAUTORESPONSE_P0; /*!< (@ 0x00000838) Port 0 PTP Auto Response Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t ARSP_EN : 1; /*!< [0..0] Auto Response Enable */ + __IOM uint32_t D_TIMER : 1; /*!< [1..1] Default timer to use for auto-response generation */ + uint32_t : 14; + __IOM uint32_t PORTNUM1 : 8; /*!< [23..16] 29, portIdentity.PortNumber[1] (lsb) */ + __IOM uint32_t PORTNUM0 : 8; /*!< [31..24] 28, portIdentity.PortNumber[0] (msb) */ + } PTPAUTORESPONSE_P0_b; + }; + __IM uint32_t RESERVED26; + + union + { + __IOM uint32_t STATUS_P0; /*!< (@ 0x00000840) Port 0 Status Register */ + + struct + { + __IM uint32_t PHYSPEED : 2; /*!< [1..0] Currently Active PHY Interface Speed */ + __IM uint32_t PHYLINK : 1; /*!< [2..2] Link status from PHY interface */ + __IM uint32_t PHYDUPLEX : 1; /*!< [3..3] Duplex status from PHY interface */ + __IOM uint32_t TX_UNDFLW : 1; /*!< [4..4] Indicates that the transmit MAC underflow. This shall + * never occur during normal operation. */ + __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed + * to complete in time before the next frame was received + * at the port. This should never occur under normal operation. + * The cause could be from IPG violations in the received + * frames. */ + __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according + * to clause 30.14.1.2 of the 802.3br specification */ + uint32_t : 23; + } STATUS_P0_b; + }; + + union + { + __IOM uint32_t TX_IPG_LENGTH_P0; /*!< (@ 0x00000844) Port 0 Transmit IPG Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values + * are in the range of 8 to 31. */ + uint32_t : 11; + __IOM uint32_t MINRTC3GAP : 5; /*!< [20..16] MINRTC3GAP */ + uint32_t : 11; + } TX_IPG_LENGTH_P0_b; + }; + + union + { + __IOM uint32_t EEE_CTL_STAT_P0; /*!< (@ 0x00000848) Port 0 MAC EEE Functions Control and Status (n + * = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_AUTO : 1; /*!< [0..0] EEE Automatic Mode of Operation */ + __IOM uint32_t LPI_REQ : 1; /*!< [1..1] Request LPI Transmission when MAC Becomes Idle */ + __IOM uint32_t LPI_TXHOLD : 1; /*!< [2..2] MAC Transmission Hold */ + uint32_t : 5; + __IM uint32_t ST_LPI_REQ : 1; /*!< [8..8] Status (real time) of Internal LPI_REQ to the MAC */ + __IM uint32_t ST_LPI_TXHOLD : 1; /*!< [9..9] Status (real time) of Internal LPI_TXHOLD to the MAC */ + __IM uint32_t ST_TXBUSY : 1; /*!< [10..10] Status (real time) if the MAC is currently transmitting. */ + __IM uint32_t ST_TXAVAIL : 1; /*!< [11..11] Status (real time) if the MAC transmit FIFO has data + * available for transmission. */ + __IM uint32_t ST_LPI_IND : 1; /*!< [12..12] Status (real time) of Received LPI */ + uint32_t : 3; + __IM uint32_t STLH_LPI_REQ : 1; /*!< [16..16] Status (latched high) of Internal LPI_REQ to the MAC */ + __IM uint32_t STLH_LPI_TXHOLD : 1; /*!< [17..17] Status (latched high) of Internal LPI_TXHOLD to the + * MAC */ + __IM uint32_t STLH_TXBUSY : 1; /*!< [18..18] Status (latched high) if the MAC is/was Transmitting */ + uint32_t : 1; + __IM uint32_t STLH_LPI_IND : 1; /*!< [20..20] Status (latched high) of Received LPI (ST_LPI_IND) */ + uint32_t : 11; + } EEE_CTL_STAT_P0_b; + }; + + union + { + __IOM uint32_t EEE_IDLE_TIME_P0; /*!< (@ 0x0000084C) Port 0 EEE Idle Time Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_IDLE_TIME : 32; /*!< [31..0] Time (-1) the transmitter must be idle before transmission + * of LPI begins. A 32-bit value in steps of 32 switch operating + * clock cycles. A value of 0 disables the timer. The value + * must be set to 1 less count. */ + } EEE_IDLE_TIME_P0_b; + }; + + union + { + __IOM uint32_t EEE_TWSYS_TIME_P0; /*!< (@ 0x00000850) Port 0 EEE Wake Up Time Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_WKUP_TIME : 32; /*!< [31..0] Time (-1) after PHY wakeup until the MAC is allowed + * to begin transmitting the first frame again. A 32-bit value + * in steps of switch operating clock cycles. A value of 0 + * disables the timer. The value must be set to 1 less count. */ + } EEE_TWSYS_TIME_P0_b; + }; + + union + { + __IOM uint32_t IDLE_SLOPE_P0; /*!< (@ 0x00000854) Port n MAC Traffic Shaper Bandwidth Control (n + * = 0 to 3) */ + + struct + { + __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control */ + uint32_t : 21; + } IDLE_SLOPE_P0_b; + }; + + union + { + __IOM uint32_t CT_DELAY_P0; /*!< (@ 0x00000858) Port n Cut-Through Delay Indication Register + * (n = 0 to 2) */ + + struct + { + __IOM uint32_t CT_DELAY : 9; /*!< [8..0] Delay Value in 400 ns / 40 ns / 8 ns increments (frequency + * of the MII PHY interface) */ + uint32_t : 23; + } CT_DELAY_P0_b; + }; + + union + { + __IOM uint32_t BR_CONTROL_P0; /*!< (@ 0x0000085C) Port 0 802.3br Frame Configuration Register */ + + struct + { + __IOM uint32_t PREEMPT_ENA : 1; /*!< [0..0] When set to 1, enables 802.3br Frame Preemption. */ + __IOM uint32_t VERIFY_DIS : 1; /*!< [1..1] When set to 1, disables the verify process required for + * preemption operation. */ + __IOM uint32_t RESPONSE_DIS : 1; /*!< [2..2] When set to 1 prevents the MAC from responding to "verify" + * frames. */ + uint32_t : 1; + __IOM uint32_t ADDFRAGSIZE : 2; /*!< [5..4] Minimum fragment size in increments of 64 bytes. */ + uint32_t : 2; + __IOM uint32_t TX_VERIFY_TIME : 7; /*!< [14..8] Preemption verification timeout in milliseconds. */ + uint32_t : 1; + __IOM uint32_t RX_STRICT_PRE : 1; /*!< [16..16] When set to 1, the preamble is checked so all bytes + * except the SFD are 0x55. When set to 0, only the last 2 + * bytes of the preamble are checked (SFD/SMD and FRAG_COUNT). + * It is recommended to set this bit to 1 to comply with the + * 802.3br specification. This bit must be set to 0 if only + * non-802.3br traffic is expected (for example, normal Ethernet + * traffic) and if custom preamble is used. */ + __IOM uint32_t RX_BR_SMD_DIS : 1; /*!< [17..17] When set to 1, the receiver does not decode the 802.3br + * SMDs and assumes all frames are express frames. This bit + * must be set to 0 for correct operation with 802.3br, and + * can be set to 1 when 802.3br is not enabled to avoid false + * detection of SMDs. */ + __IOM uint32_t RX_STRICT_BR_CTL : 1; /*!< [18..18] When set to 1, strict checking of VERIFY and RESPONSE + * frames is enabled. When set to 1, the frame contents and + * frame length checks are also performed on these frames. + * The mCRC is always checked regardless of the value of this + * register. This bit must be set to 0 to be compliant with + * the functionality described in IEEE 802.3br. */ + __IOM uint32_t TX_MCRC_INV : 1; /*!< [19..19] When set to 1, the 32-bit XOR mask used to calculate + * the mCRC for transmitted frames is inverted. This bit must + * always be written to 0 and only used for debugging. */ + __IOM uint32_t RX_MCRC_INV : 1; /*!< [20..20] When set to 1, the 32-bit XOR mask used to calculate + * the mCRC for received frames is inverted. This bit must + * always be written to 0 and only used for debugging. */ + uint32_t : 11; + } BR_CONTROL_P0_b; + }; + __IM uint32_t RESERVED27[2]; + + union + { + __IM uint32_t AFRAMESTRANSMITTEDOK_P0; /*!< (@ 0x00000868) Port 0 MAC Transmitted Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Transmitted, including pause. */ + } AFRAMESTRANSMITTEDOK_P0_b; + }; + + union + { + __IM uint32_t AFRAMESRECEIVEDOK_P0; /*!< (@ 0x0000086C) Port 0 MAC Received Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Received, including pause. */ + } AFRAMESRECEIVEDOK_P0_b; + }; + + union + { + __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P0; /*!< (@ 0x00000870) Port 0 MAC FCS Error Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t FCSERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Length except CRC error. */ + } AFRAMECHECKSEQUENCEERRORS_P0_b; + }; + + union + { + __IM uint32_t AALIGNMENTERRORS_P0; /*!< (@ 0x00000874) Port 0 MAC Alignment Error Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number + * of Nibbles (MII) Received. */ + } AALIGNMENTERRORS_P0_b; + }; + + union + { + __IM uint32_t AOCTETSTRANSMITTEDOK_P0; /*!< (@ 0x00000878) Port 0 MAC Transmitted Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Transmitted. */ + } AOCTETSTRANSMITTEDOK_P0_b; + }; + + union + { + __IM uint32_t AOCTETSRECEIVEDOK_P0; /*!< (@ 0x0000087C) Port 0 MAC Received Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Received. */ + } AOCTETSRECEIVEDOK_P0_b; + }; + + union + { + __IM uint32_t ATXPAUSEMACCTRLFRAMES_P0; /*!< (@ 0x00000880) Port 0 MAC Transmitted Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Transmitted. */ + } ATXPAUSEMACCTRLFRAMES_P0_b; + }; + + union + { + __IM uint32_t ARXPAUSEMACCTRLFRAMES_P0; /*!< (@ 0x00000884) Port 0 MAC Received Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Received. */ + } ARXPAUSEMACCTRLFRAMES_P0_b; + }; + + union + { + __IM uint32_t IFINERRORS_P0; /*!< (@ 0x00000888) Port 0 MAC Input Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error + * During Reception such as CRC, Length, PHY Error, RX FIFO + * Overflow. */ + } IFINERRORS_P0_b; + }; + + union + { + __IM uint32_t IFOUTERRORS_P0; /*!< (@ 0x0000088C) Port 0 MAC Output Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame + * Transmitted with PHY error. */ + } IFOUTERRORS_P0_b; + }; + + union + { + __IM uint32_t IFINUCASTPKTS_P0; /*!< (@ 0x00000890) Port 0 MAC Received Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Received. */ + } IFINUCASTPKTS_P0_b; + }; + + union + { + __IM uint32_t IFINMULTICASTPKTS_P0; /*!< (@ 0x00000894) Port 0 MAC Received Multicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Received. */ + } IFINMULTICASTPKTS_P0_b; + }; + + union + { + __IM uint32_t IFINBROADCASTPKTS_P0; /*!< (@ 0x00000898) Port 0 MAC Received Broadcast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Received. */ + } IFINBROADCASTPKTS_P0_b; + }; + + union + { + __IM uint32_t IFOUTDISCARDS_P0; /*!< (@ 0x0000089C) Port 0 MAC Discarded Outbound Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable */ + } IFOUTDISCARDS_P0_b; + }; + + union + { + __IM uint32_t IFOUTUCASTPKTS_P0; /*!< (@ 0x000008A0) Port 0 MAC Transmitted Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Transmitted. */ + } IFOUTUCASTPKTS_P0_b; + }; + + union + { + __IM uint32_t IFOUTMULTICASTPKTS_P0; /*!< (@ 0x000008A4) Port 0 MAC Transmitted Multicast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Transmitted. */ + } IFOUTMULTICASTPKTS_P0_b; + }; + + union + { + __IM uint32_t IFOUTBROADCASTPKTS_P0; /*!< (@ 0x000008A8) Port 0 MAC Transmitted Broadcast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Transmitted. */ + } IFOUTBROADCASTPKTS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSDROPEVENTS_P0; /*!< (@ 0x000008AC) Port 0 MAC Dropped Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t DROPCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO + * Full at frame start. */ + } ETHERSTATSDROPEVENTS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSOCTETS_P0; /*!< (@ 0x000008B0) Port 0 MAC All Frame Octets Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLOCTETS : 32; /*!< [31..0] ALLOCTETS */ + } ETHERSTATSOCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS_P0; /*!< (@ 0x000008B4) Port 0 MAC All Frame Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT */ + } ETHERSTATSPKTS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P0; /*!< (@ 0x000008B8) Port 0 MAC Too Short Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t TOOSHRTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Good CRC. */ + } ETHERSTATSUNDERSIZEPKTS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSOVERSIZEPKTS_P0; /*!< (@ 0x000008BC) Port 0 MAC Too Long Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t TOOLONGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Good CRC. */ + } ETHERSTATSOVERSIZEPKTS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS64OCTETS_P0; /*!< (@ 0x000008C0) Port 0 MAC 64 Octets Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT64 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 64 bytes). */ + } ETHERSTATSPKTS64OCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P0; /*!< (@ 0x000008C4) Port 0 MAC 65 to 127 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT65T127 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 65 to 127 bytes). */ + } ETHERSTATSPKTS65TO127OCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P0; /*!< (@ 0x000008C8) Port 0 MAC 128 to 255 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT128T255 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 128 to 255 bytes). */ + } ETHERSTATSPKTS128TO255OCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P0; /*!< (@ 0x000008CC) Port 0 MAC 256 to 511 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT256T511 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 256 to 511 bytes). */ + } ETHERSTATSPKTS256TO511OCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P0; /*!< (@ 0x000008D0) Port 0 MAC 512 to 1023 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT512T1023 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 512 to 1023 bytes). */ + } ETHERSTATSPKTS512TO1023OCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P0; /*!< (@ 0x000008D4) Port 0 MAC 1024 to 1518 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1024T1518 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 1024 to 1518 bytes). */ + } ETHERSTATSPKTS1024TO1518OCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P0; /*!< (@ 0x000008D8) Port 0 MAC Over 1519 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1519TX : 32; /*!< [31..0] PORT n, this field indicates the number of MAC all Frames, + * Good and Bad (Packet Size: over 1519 bytes). */ + } ETHERSTATSPKTS1519TOXOCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSJABBERS_P0; /*!< (@ 0x000008DC) Port 0 MAC Jabbers Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Bad CRC. */ + } ETHERSTATSJABBERS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSFRAGMENTS_P0; /*!< (@ 0x000008E0) Port 0 MAC Fragment Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t FRAGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Bad CRC. */ + } ETHERSTATSFRAGMENTS_P0_b; + }; + __IM uint32_t RESERVED28; + + union + { + __IM uint32_t VLANRECEIVEDOK_P0; /*!< (@ 0x000008E8) Port 0 MAC Received VLAN Tagged Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Received. */ + } VLANRECEIVEDOK_P0_b; + }; + __IM uint32_t RESERVED29[2]; + + union + { + __IM uint32_t VLANTRANSMITTEDOK_P0; /*!< (@ 0x000008F4) Port 0 MAC Transmitted VLAN Tagged Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Transmitted. */ + } VLANTRANSMITTEDOK_P0_b; + }; + + union + { + __IM uint32_t FRAMESRETRANSMITTED_P0; /*!< (@ 0x000008F8) Port 0 MAC Retransmitted Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RETXCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Transmitted + * Frames that experienced a collision and were retransmitted. */ + } FRAMESRETRANSMITTED_P0_b; + }; + __IM uint32_t RESERVED30; + + union + { + __IM uint32_t STATS_HIWORD_P0; /*!< (@ 0x00000900) Port 0 MAC Statistics Counter High Word Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics + * Counter Last Read */ + } STATS_HIWORD_P0_b; + }; + + union + { + __IOM uint32_t STATS_CTRL_P0; /*!< (@ 0x00000904) Port 0 MAC Statistics Control Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t CLRALL : 1; /*!< [0..0] Self Clearing Counter Initialize Command */ + __IM uint32_t CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication */ + uint32_t : 30; + } STATS_CTRL_P0_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUELO_P0; /*!< (@ 0x00000908) Port 0 MAC Statistics Clear Value Lower Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUELO_P0_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUEHI_P0; /*!< (@ 0x0000090C) Port 0 MAC Statistics Clear Value Higher Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUEHI_P0_b; + }; + + union + { + __IM uint32_t ADEFERRED_P0; /*!< (@ 0x00000910) Port 0 MAC Deferred Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted + * without collision but was deferred at begin. */ + } ADEFERRED_P0_b; + }; + + union + { + __IM uint32_t AMULTIPLECOLLISIONS_P0; /*!< (@ 0x00000914) Port 0 MAC Multiple Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after multiple collisions. */ + } AMULTIPLECOLLISIONS_P0_b; + }; + + union + { + __IM uint32_t ASINGLECOLLISIONS_P0; /*!< (@ 0x00000918) Port 0 MAC Single Collision Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after single collision. */ + } ASINGLECOLLISIONS_P0_b; + }; + + union + { + __IM uint32_t ALATECOLLISIONS_P0; /*!< (@ 0x0000091C) Port 0 MAC Late Collision Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late + * Collision. Frame was aborted and not retransmitted. */ + } ALATECOLLISIONS_P0_b; + }; + + union + { + __IM uint32_t AEXCESSIVECOLLISIONS_P0; /*!< (@ 0x00000920) Port 0 MAC Excessive Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t EXCCOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frames Discarded + * due to 16 consecutive collisions. */ + } AEXCESSIVECOLLISIONS_P0_b; + }; + + union + { + __IM uint32_t ACARRIERSENSEERRORS_P0; /*!< (@ 0x00000924) Port 0 MAC Carrier Sense Error Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t CSERRCOUNT : 32; /*!< [31..0] PORT n, increments during Transmission without Collisions + * the PHY Carrier Sense Signal (RX_CRS) dropped or never + * asserted. */ + } ACARRIERSENSEERRORS_P0_b; + }; + __IM uint32_t RESERVED31[182]; + + union + { + __IM uint32_t REV_P1; /*!< (@ 0x00000C00) Port 1 MAC Core Revision (n = 0 to 3) */ + + struct + { + __IM uint32_t REV : 32; /*!< [31..0] MAC Core Revision */ + } REV_P1_b; + }; + __IM uint32_t RESERVED32; + + union + { + __IOM uint32_t COMMAND_CONFIG_P1; /*!< (@ 0x00000C08) Port 1 Command Configuration Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t TX_ENA : 1; /*!< [0..0] Enable/Disable MAC Transmit Path */ + __IOM uint32_t RX_ENA : 1; /*!< [1..1] Enable/Disable MAC Receive Path */ + __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from + * the IMC until the current frame is completed. This can + * cause the IPG between frames to be more than the value + * in TX_IPG_LENGTH. */ + __IOM uint32_t ETH_SPEED : 1; /*!< [3..3] Operation Mode Definition */ + __IM uint32_t PROMIS_EN : 1; /*!< [4..4] Enable/Disable MAC Promiscuous Operation */ + __IM uint32_t PAD_EN : 1; /*!< [5..5] Enable/Disable Frame Padding Remove on Receive */ + uint32_t : 1; + __IM uint32_t PAUSE_FWD : 1; /*!< [7..7] Terminate/Forward Pause Frames */ + __IOM uint32_t PAUSE_IGNORE : 1; /*!< [8..8] Ignore Pause Frame Quanta */ + __IM uint32_t TX_ADDR_INS : 1; /*!< [9..9] Non writable bit, fixed to 0 always. */ + __IOM uint32_t HD_ENA : 1; /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or + * full-duplex only (set to 0). */ + __IOM uint32_t TX_CRC_APPEND : 1; /*!< [11..11] Enable CRC Append on Transmit */ + uint32_t : 1; + __IOM uint32_t SW_RESET : 1; /*!< [13..13] Self Clearing Reset Command Bit */ + uint32_t : 9; + __IOM uint32_t CNTL_FRM_ENA : 1; /*!< [23..23] MAC Control Frame Enable */ + __IOM uint32_t NO_LGTH_CHK : 1; /*!< [24..24] Payload Length Check Disable */ + __IOM uint32_t ENA_10 : 1; /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn + * register. */ + uint32_t : 4; + __IOM uint32_t TIMER_SEL : 1; /*!< [30..30] Selects the default timer to use for timestamping operations + * on transmit and on receive. The value is used when not + * overridden by the PTP auto-response function, pattern matchers + * or force forwarding information in a management tag. */ + uint32_t : 1; + } COMMAND_CONFIG_P1_b; + }; + + union + { + __IOM uint32_t MAC_ADDR_0_P1; /*!< (@ 0x00000C0C) Port 1 MAC Address Register 0 (n = 0 to 2) */ + + struct + { + __IOM uint32_t MAC_ADDR : 32; /*!< [31..0] The first 4 bytes of the MAC address of the port. First + * byte is bits [7:0]. The MAC address is used on locally + * generated frames such as pause frames, peer-delay response. */ + } MAC_ADDR_0_P1_b; + }; + + union + { + __IOM uint32_t MAC_ADDR_1_P1; /*!< (@ 0x00000C10) Port 1 MAC Address Register 1 (n = 0 to 2) */ + + struct + { + __IOM uint32_t MAC_ADDR : 16; /*!< [15..0] The last 2 bytes of the MAC address of the port. Bits + * [7:0] is the 5th byte and bits [15:8] is the 6th byte. */ + uint32_t : 16; + } MAC_ADDR_1_P1_b; + }; + + union + { + __IOM uint32_t FRM_LENGTH_P1; /*!< (@ 0x00000C14) Port 1 Maximum Frame Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length */ + uint32_t : 18; + } FRM_LENGTH_P1_b; + }; + + union + { + __IM uint32_t PAUSE_QUANT_P1; /*!< (@ 0x00000C18) Port 1 MAC Pause Quanta (n = 0 to 3) */ + + struct + { + __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta */ + uint32_t : 16; + } PAUSE_QUANT_P1_b; + }; + + union + { + __IOM uint32_t MAC_LINK_QTRIG_P1; /*!< (@ 0x00000C1C) Port 1 Trigger Event Configuration Register (n + * = 0 to 2) */ + + struct + { + __IOM uint32_t PORT_MASK : 4; /*!< [3..0] Per-port Bit Mask */ + uint32_t : 12; + __IOM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame + * is transmitted from the ports indicated by PORT_MASK. A + * single frame is transmitted per indicated port in PORT_MASK + * among the queues indicated by QUEUE_MASK. */ + uint32_t : 4; + __IOM uint32_t TRIGGERED : 1; /*!< [28..28] When MODE is set to 1, TRIGGERED indicates whether + * a frame was transmitted. When MODE is set to 0, TRIGGERED + * is always 0. This flag clears when the register is written. */ + __IOM uint32_t DLR_MODE : 1; /*!< [29..29] When set to 0, the DLR state machine is ignored. When + * set to 1, the Link Queue Trigger occurs only if the DLR + * state machine is in the NORMAL or FAULT state. */ + __IOM uint32_t MODE : 1; /*!< [30..30] When set to 0, only a single Link_Status frame is generated. + * This is to prevent sending multiple frames due to link + * flapping. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Write to 1 to enable the Link Queue Trigger feature. + * When the link status (phy_link) transitions from 1 -> + * 0, a trigger event is generated to the memory controller + * for the ports and queues indicated in PORT_MASK and QUEUE_MASK. */ + } MAC_LINK_QTRIG_P1_b; + }; + __IM uint32_t RESERVED33[4]; + + union + { + __IOM uint32_t PTPCLOCKIDENTITY1_P1; /*!< (@ 0x00000C30) Port 1 PTP Clock Identity 1 Register (n = 0 to + * 2) */ + + struct + { + __IOM uint32_t CLK_IDENTITY0 : 8; /*!< [7..0] 20, portIdentity.ClockIdentity[0] */ + __IOM uint32_t CLK_IDENTITY1 : 8; /*!< [15..8] 21, portIdentity.ClockIdentity[1] */ + __IOM uint32_t CLK_IDENTITY2 : 8; /*!< [23..16] 22, portIdentity.ClockIdentity[2] */ + __IOM uint32_t CLK_IDENTITY3 : 8; /*!< [31..24] 23, portIdentity.ClockIdentity[3] */ + } PTPCLOCKIDENTITY1_P1_b; + }; + + union + { + __IOM uint32_t PTPCLOCKIDENTITY2_P1; /*!< (@ 0x00000C34) Port 1 PTP Clock Identity 2 Register (n = 0 to + * 2) */ + + struct + { + __IOM uint32_t CLK_IDENTITY4 : 8; /*!< [7..0] 24, portIdentity.ClockIdentity[4] */ + __IOM uint32_t CLK_IDENTITY5 : 8; /*!< [15..8] 25, portIdentity.ClockIdentity[5] */ + __IOM uint32_t CLK_IDENTITY6 : 8; /*!< [23..16] 26, portIdentity.ClockIdentity[6] */ + __IOM uint32_t CLK_IDENTITY7 : 8; /*!< [31..24] 27, portIdentity.ClockIdentity[7] */ + } PTPCLOCKIDENTITY2_P1_b; + }; + + union + { + __IOM uint32_t PTPAUTORESPONSE_P1; /*!< (@ 0x00000C38) Port 1 PTP Auto Response Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t ARSP_EN : 1; /*!< [0..0] Auto Response Enable */ + __IOM uint32_t D_TIMER : 1; /*!< [1..1] Default timer to use for auto-response generation */ + uint32_t : 14; + __IOM uint32_t PORTNUM1 : 8; /*!< [23..16] 29, portIdentity.PortNumber[1] (lsb) */ + __IOM uint32_t PORTNUM0 : 8; /*!< [31..24] 28, portIdentity.PortNumber[0] (msb) */ + } PTPAUTORESPONSE_P1_b; + }; + __IM uint32_t RESERVED34; + + union + { + __IOM uint32_t STATUS_P1; /*!< (@ 0x00000C40) Port 1 Status Register */ + + struct + { + __IM uint32_t PHYSPEED : 2; /*!< [1..0] Currently Active PHY Interface Speed */ + __IM uint32_t PHYLINK : 1; /*!< [2..2] Link status from PHY interface */ + __IM uint32_t PHYDUPLEX : 1; /*!< [3..3] Duplex status from PHY interface */ + __IOM uint32_t TX_UNDFLW : 1; /*!< [4..4] Indicates that the transmit MAC underflow. This shall + * never occur during normal operation. */ + __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed + * to complete in time before the next frame was received + * at the port. This should never occur under normal operation. + * The cause could be from IPG violations in the received + * frames. */ + __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according + * to clause 30.14.1.2 of the 802.3br specification */ + uint32_t : 23; + } STATUS_P1_b; + }; + + union + { + __IOM uint32_t TX_IPG_LENGTH_P1; /*!< (@ 0x00000C44) Port 1 Transmit IPG Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values + * are in the range of 8 to 31. */ + uint32_t : 11; + __IOM uint32_t MINRTC3GAP : 5; /*!< [20..16] MINRTC3GAP */ + uint32_t : 11; + } TX_IPG_LENGTH_P1_b; + }; + + union + { + __IOM uint32_t EEE_CTL_STAT_P1; /*!< (@ 0x00000C48) Port 1 MAC EEE Functions Control and Status (n + * = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_AUTO : 1; /*!< [0..0] EEE Automatic Mode of Operation */ + __IOM uint32_t LPI_REQ : 1; /*!< [1..1] Request LPI Transmission when MAC Becomes Idle */ + __IOM uint32_t LPI_TXHOLD : 1; /*!< [2..2] MAC Transmission Hold */ + uint32_t : 5; + __IM uint32_t ST_LPI_REQ : 1; /*!< [8..8] Status (real time) of Internal LPI_REQ to the MAC */ + __IM uint32_t ST_LPI_TXHOLD : 1; /*!< [9..9] Status (real time) of Internal LPI_TXHOLD to the MAC */ + __IM uint32_t ST_TXBUSY : 1; /*!< [10..10] Status (real time) if the MAC is currently transmitting. */ + __IM uint32_t ST_TXAVAIL : 1; /*!< [11..11] Status (real time) if the MAC transmit FIFO has data + * available for transmission. */ + __IM uint32_t ST_LPI_IND : 1; /*!< [12..12] Status (real time) of Received LPI */ + uint32_t : 3; + __IM uint32_t STLH_LPI_REQ : 1; /*!< [16..16] Status (latched high) of Internal LPI_REQ to the MAC */ + __IM uint32_t STLH_LPI_TXHOLD : 1; /*!< [17..17] Status (latched high) of Internal LPI_TXHOLD to the + * MAC */ + __IM uint32_t STLH_TXBUSY : 1; /*!< [18..18] Status (latched high) if the MAC is/was Transmitting */ + uint32_t : 1; + __IM uint32_t STLH_LPI_IND : 1; /*!< [20..20] Status (latched high) of Received LPI (ST_LPI_IND) */ + uint32_t : 11; + } EEE_CTL_STAT_P1_b; + }; + + union + { + __IOM uint32_t EEE_IDLE_TIME_P1; /*!< (@ 0x00000C4C) Port 1 EEE Idle Time Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_IDLE_TIME : 32; /*!< [31..0] Time (-1) the transmitter must be idle before transmission + * of LPI begins. A 32-bit value in steps of 32 switch operating + * clock cycles. A value of 0 disables the timer. The value + * must be set to 1 less count. */ + } EEE_IDLE_TIME_P1_b; + }; + + union + { + __IOM uint32_t EEE_TWSYS_TIME_P1; /*!< (@ 0x00000C50) Port 1 EEE Wake Up Time Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_WKUP_TIME : 32; /*!< [31..0] Time (-1) after PHY wakeup until the MAC is allowed + * to begin transmitting the first frame again. A 32-bit value + * in steps of switch operating clock cycles. A value of 0 + * disables the timer. The value must be set to 1 less count. */ + } EEE_TWSYS_TIME_P1_b; + }; + + union + { + __IOM uint32_t IDLE_SLOPE_P1; /*!< (@ 0x00000C54) Port n MAC Traffic Shaper Bandwidth Control (n + * = 0 to 3) */ + + struct + { + __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control */ + uint32_t : 21; + } IDLE_SLOPE_P1_b; + }; + + union + { + __IOM uint32_t CT_DELAY_P1; /*!< (@ 0x00000C58) Port n Cut-Through Delay Indication Register + * (n = 0 to 2) */ + + struct + { + __IOM uint32_t CT_DELAY : 9; /*!< [8..0] Delay Value in 400 ns / 40 ns / 8 ns increments (frequency + * of the MII PHY interface) */ + uint32_t : 23; + } CT_DELAY_P1_b; + }; + + union + { + __IOM uint32_t BR_CONTROL_P1; /*!< (@ 0x00000C5C) Port 1 802.3br Frame Configuration Register */ + + struct + { + __IOM uint32_t PREEMPT_ENA : 1; /*!< [0..0] When set to 1, enables 802.3br Frame Preemption. */ + __IOM uint32_t VERIFY_DIS : 1; /*!< [1..1] When set to 1, disables the verify process required for + * preemption operation. */ + __IOM uint32_t RESPONSE_DIS : 1; /*!< [2..2] When set to 1 prevents the MAC from responding to "verify" + * frames. */ + uint32_t : 1; + __IOM uint32_t ADDFRAGSIZE : 2; /*!< [5..4] Minimum fragment size in increments of 64 bytes. */ + uint32_t : 2; + __IOM uint32_t TX_VERIFY_TIME : 7; /*!< [14..8] Preemption verification timeout in milliseconds. */ + uint32_t : 1; + __IOM uint32_t RX_STRICT_PRE : 1; /*!< [16..16] When set to 1, the preamble is checked so all bytes + * except the SFD are 0x55. When set to 0, only the last 2 + * bytes of the preamble are checked (SFD/SMD and FRAG_COUNT). + * It is recommended to set this bit to 1 to comply with the + * 802.3br specification. This bit must be set to 0 if only + * non-802.3br traffic is expected (for example, normal Ethernet + * traffic) and if custom preamble is used. */ + __IOM uint32_t RX_BR_SMD_DIS : 1; /*!< [17..17] When set to 1, the receiver does not decode the 802.3br + * SMDs and assumes all frames are express frames. This bit + * must be set to 0 for correct operation with 802.3br, and + * can be set to 1 when 802.3br is not enabled to avoid false + * detection of SMDs. */ + __IOM uint32_t RX_STRICT_BR_CTL : 1; /*!< [18..18] When set to 1, strict checking of VERIFY and RESPONSE + * frames is enabled. When set to 1, the frame contents and + * frame length checks are also performed on these frames. + * The mCRC is always checked regardless of the value of this + * register. This bit must be set to 0 to be compliant with + * the functionality described in IEEE 802.3br. */ + __IOM uint32_t TX_MCRC_INV : 1; /*!< [19..19] When set to 1, the 32-bit XOR mask used to calculate + * the mCRC for transmitted frames is inverted. This bit must + * always be written to 0 and only used for debugging. */ + __IOM uint32_t RX_MCRC_INV : 1; /*!< [20..20] When set to 1, the 32-bit XOR mask used to calculate + * the mCRC for received frames is inverted. This bit must + * always be written to 0 and only used for debugging. */ + uint32_t : 11; + } BR_CONTROL_P1_b; + }; + __IM uint32_t RESERVED35[2]; + + union + { + __IM uint32_t AFRAMESTRANSMITTEDOK_P1; /*!< (@ 0x00000C68) Port 1 MAC Transmitted Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Transmitted, including pause. */ + } AFRAMESTRANSMITTEDOK_P1_b; + }; + + union + { + __IM uint32_t AFRAMESRECEIVEDOK_P1; /*!< (@ 0x00000C6C) Port 1 MAC Received Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Received, including pause. */ + } AFRAMESRECEIVEDOK_P1_b; + }; + + union + { + __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P1; /*!< (@ 0x00000C70) Port 1 MAC FCS Error Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t FCSERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Length except CRC error. */ + } AFRAMECHECKSEQUENCEERRORS_P1_b; + }; + + union + { + __IM uint32_t AALIGNMENTERRORS_P1; /*!< (@ 0x00000C74) Port 1 MAC Alignment Error Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number + * of Nibbles (MII) Received. */ + } AALIGNMENTERRORS_P1_b; + }; + + union + { + __IM uint32_t AOCTETSTRANSMITTEDOK_P1; /*!< (@ 0x00000C78) Port 1 MAC Transmitted Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Transmitted. */ + } AOCTETSTRANSMITTEDOK_P1_b; + }; + + union + { + __IM uint32_t AOCTETSRECEIVEDOK_P1; /*!< (@ 0x00000C7C) Port 1 MAC Received Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Received. */ + } AOCTETSRECEIVEDOK_P1_b; + }; + + union + { + __IM uint32_t ATXPAUSEMACCTRLFRAMES_P1; /*!< (@ 0x00000C80) Port 1 MAC Transmitted Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Transmitted. */ + } ATXPAUSEMACCTRLFRAMES_P1_b; + }; + + union + { + __IM uint32_t ARXPAUSEMACCTRLFRAMES_P1; /*!< (@ 0x00000C84) Port 1 MAC Received Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Received. */ + } ARXPAUSEMACCTRLFRAMES_P1_b; + }; + + union + { + __IM uint32_t IFINERRORS_P1; /*!< (@ 0x00000C88) Port 1 MAC Input Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error + * During Reception such as CRC, Length, PHY Error, RX FIFO + * Overflow. */ + } IFINERRORS_P1_b; + }; + + union + { + __IM uint32_t IFOUTERRORS_P1; /*!< (@ 0x00000C8C) Port 1 MAC Output Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame + * Transmitted with PHY error. */ + } IFOUTERRORS_P1_b; + }; + + union + { + __IM uint32_t IFINUCASTPKTS_P1; /*!< (@ 0x00000C90) Port 1 MAC Received Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Received. */ + } IFINUCASTPKTS_P1_b; + }; + + union + { + __IM uint32_t IFINMULTICASTPKTS_P1; /*!< (@ 0x00000C94) Port 1 MAC Received Multicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Received. */ + } IFINMULTICASTPKTS_P1_b; + }; + + union + { + __IM uint32_t IFINBROADCASTPKTS_P1; /*!< (@ 0x00000C98) Port 1 MAC Received Broadcast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Received. */ + } IFINBROADCASTPKTS_P1_b; + }; + + union + { + __IM uint32_t IFOUTDISCARDS_P1; /*!< (@ 0x00000C9C) Port 1 MAC Discarded Outbound Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable */ + } IFOUTDISCARDS_P1_b; + }; + + union + { + __IM uint32_t IFOUTUCASTPKTS_P1; /*!< (@ 0x00000CA0) Port 1 MAC Transmitted Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Transmitted. */ + } IFOUTUCASTPKTS_P1_b; + }; + + union + { + __IM uint32_t IFOUTMULTICASTPKTS_P1; /*!< (@ 0x00000CA4) Port 1 MAC Transmitted Multicast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Transmitted. */ + } IFOUTMULTICASTPKTS_P1_b; + }; + + union + { + __IM uint32_t IFOUTBROADCASTPKTS_P1; /*!< (@ 0x00000CA8) Port 1 MAC Transmitted Broadcast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Transmitted. */ + } IFOUTBROADCASTPKTS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSDROPEVENTS_P1; /*!< (@ 0x00000CAC) Port 1 MAC Dropped Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t DROPCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO + * Full at frame start. */ + } ETHERSTATSDROPEVENTS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSOCTETS_P1; /*!< (@ 0x00000CB0) Port 1 MAC All Frame Octets Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLOCTETS : 32; /*!< [31..0] ALLOCTETS */ + } ETHERSTATSOCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS_P1; /*!< (@ 0x00000CB4) Port 1 MAC All Frame Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT */ + } ETHERSTATSPKTS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P1; /*!< (@ 0x00000CB8) Port 1 MAC Too Short Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t TOOSHRTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Good CRC. */ + } ETHERSTATSUNDERSIZEPKTS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSOVERSIZEPKTS_P1; /*!< (@ 0x00000CBC) Port 1 MAC Too Long Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t TOOLONGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Good CRC. */ + } ETHERSTATSOVERSIZEPKTS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS64OCTETS_P1; /*!< (@ 0x00000CC0) Port 1 MAC 64 Octets Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT64 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 64 bytes). */ + } ETHERSTATSPKTS64OCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P1; /*!< (@ 0x00000CC4) Port 1 MAC 65 to 127 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT65T127 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 65 to 127 bytes). */ + } ETHERSTATSPKTS65TO127OCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P1; /*!< (@ 0x00000CC8) Port 1 MAC 128 to 255 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT128T255 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 128 to 255 bytes). */ + } ETHERSTATSPKTS128TO255OCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P1; /*!< (@ 0x00000CCC) Port 1 MAC 256 to 511 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT256T511 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 256 to 511 bytes). */ + } ETHERSTATSPKTS256TO511OCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P1; /*!< (@ 0x00000CD0) Port 1 MAC 512 to 1023 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT512T1023 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 512 to 1023 bytes). */ + } ETHERSTATSPKTS512TO1023OCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P1; /*!< (@ 0x00000CD4) Port 1 MAC 1024 to 1518 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1024T1518 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 1024 to 1518 bytes). */ + } ETHERSTATSPKTS1024TO1518OCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P1; /*!< (@ 0x00000CD8) Port 1 MAC Over 1519 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1519TX : 32; /*!< [31..0] PORT n, this field indicates the number of MAC all Frames, + * Good and Bad (Packet Size: over 1519 bytes). */ + } ETHERSTATSPKTS1519TOXOCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSJABBERS_P1; /*!< (@ 0x00000CDC) Port 1 MAC Jabbers Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Bad CRC. */ + } ETHERSTATSJABBERS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSFRAGMENTS_P1; /*!< (@ 0x00000CE0) Port 1 MAC Fragment Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t FRAGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Bad CRC. */ + } ETHERSTATSFRAGMENTS_P1_b; + }; + __IM uint32_t RESERVED36; + + union + { + __IM uint32_t VLANRECEIVEDOK_P1; /*!< (@ 0x00000CE8) Port 1 MAC Received VLAN Tagged Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Received. */ + } VLANRECEIVEDOK_P1_b; + }; + __IM uint32_t RESERVED37[2]; + + union + { + __IM uint32_t VLANTRANSMITTEDOK_P1; /*!< (@ 0x00000CF4) Port 1 MAC Transmitted VLAN Tagged Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Transmitted. */ + } VLANTRANSMITTEDOK_P1_b; + }; + + union + { + __IM uint32_t FRAMESRETRANSMITTED_P1; /*!< (@ 0x00000CF8) Port 1 MAC Retransmitted Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RETXCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Transmitted + * Frames that experienced a collision and were retransmitted. */ + } FRAMESRETRANSMITTED_P1_b; + }; + __IM uint32_t RESERVED38; + + union + { + __IM uint32_t STATS_HIWORD_P1; /*!< (@ 0x00000D00) Port 1 MAC Statistics Counter High Word Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics + * Counter Last Read */ + } STATS_HIWORD_P1_b; + }; + + union + { + __IOM uint32_t STATS_CTRL_P1; /*!< (@ 0x00000D04) Port 1 MAC Statistics Control Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t CLRALL : 1; /*!< [0..0] Self Clearing Counter Initialize Command */ + __IM uint32_t CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication */ + uint32_t : 30; + } STATS_CTRL_P1_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUELO_P1; /*!< (@ 0x00000D08) Port 1 MAC Statistics Clear Value Lower Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUELO_P1_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUEHI_P1; /*!< (@ 0x00000D0C) Port 1 MAC Statistics Clear Value Higher Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUEHI_P1_b; + }; + + union + { + __IM uint32_t ADEFERRED_P1; /*!< (@ 0x00000D10) Port 1 MAC Deferred Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted + * without collision but was deferred at begin. */ + } ADEFERRED_P1_b; + }; + + union + { + __IM uint32_t AMULTIPLECOLLISIONS_P1; /*!< (@ 0x00000D14) Port 1 MAC Multiple Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after multiple collisions. */ + } AMULTIPLECOLLISIONS_P1_b; + }; + + union + { + __IM uint32_t ASINGLECOLLISIONS_P1; /*!< (@ 0x00000D18) Port 1 MAC Single Collision Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after single collision. */ + } ASINGLECOLLISIONS_P1_b; + }; + + union + { + __IM uint32_t ALATECOLLISIONS_P1; /*!< (@ 0x00000D1C) Port 1 MAC Late Collision Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late + * Collision. Frame was aborted and not retransmitted. */ + } ALATECOLLISIONS_P1_b; + }; + + union + { + __IM uint32_t AEXCESSIVECOLLISIONS_P1; /*!< (@ 0x00000D20) Port 1 MAC Excessive Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t EXCCOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frames Discarded + * due to 16 consecutive collisions. */ + } AEXCESSIVECOLLISIONS_P1_b; + }; + + union + { + __IM uint32_t ACARRIERSENSEERRORS_P1; /*!< (@ 0x00000D24) Port 1 MAC Carrier Sense Error Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t CSERRCOUNT : 32; /*!< [31..0] PORT n, increments during Transmission without Collisions + * the PHY Carrier Sense Signal (RX_CRS) dropped or never + * asserted. */ + } ACARRIERSENSEERRORS_P1_b; + }; + __IM uint32_t RESERVED39[182]; + + union + { + __IM uint32_t REV_P2; /*!< (@ 0x00001000) Port 2 MAC Core Revision (n = 0 to 3) */ + + struct + { + __IM uint32_t REV : 32; /*!< [31..0] MAC Core Revision */ + } REV_P2_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t COMMAND_CONFIG_P2; /*!< (@ 0x00001008) Port 2 Command Configuration Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t TX_ENA : 1; /*!< [0..0] Enable/Disable MAC Transmit Path */ + __IOM uint32_t RX_ENA : 1; /*!< [1..1] Enable/Disable MAC Receive Path */ + __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from + * the IMC until the current frame is completed. This can + * cause the IPG between frames to be more than the value + * in TX_IPG_LENGTH. */ + __IOM uint32_t ETH_SPEED : 1; /*!< [3..3] Operation Mode Definition */ + __IM uint32_t PROMIS_EN : 1; /*!< [4..4] Enable/Disable MAC Promiscuous Operation */ + __IM uint32_t PAD_EN : 1; /*!< [5..5] Enable/Disable Frame Padding Remove on Receive */ + uint32_t : 1; + __IM uint32_t PAUSE_FWD : 1; /*!< [7..7] Terminate/Forward Pause Frames */ + __IOM uint32_t PAUSE_IGNORE : 1; /*!< [8..8] Ignore Pause Frame Quanta */ + __IM uint32_t TX_ADDR_INS : 1; /*!< [9..9] Non writable bit, fixed to 0 always. */ + __IOM uint32_t HD_ENA : 1; /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or + * full-duplex only (set to 0). */ + __IOM uint32_t TX_CRC_APPEND : 1; /*!< [11..11] Enable CRC Append on Transmit */ + uint32_t : 1; + __IOM uint32_t SW_RESET : 1; /*!< [13..13] Self Clearing Reset Command Bit */ + uint32_t : 9; + __IOM uint32_t CNTL_FRM_ENA : 1; /*!< [23..23] MAC Control Frame Enable */ + __IOM uint32_t NO_LGTH_CHK : 1; /*!< [24..24] Payload Length Check Disable */ + __IOM uint32_t ENA_10 : 1; /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn + * register. */ + uint32_t : 4; + __IOM uint32_t TIMER_SEL : 1; /*!< [30..30] Selects the default timer to use for timestamping operations + * on transmit and on receive. The value is used when not + * overridden by the PTP auto-response function, pattern matchers + * or force forwarding information in a management tag. */ + uint32_t : 1; + } COMMAND_CONFIG_P2_b; + }; + + union + { + __IOM uint32_t MAC_ADDR_0_P2; /*!< (@ 0x0000100C) Port 2 MAC Address Register 0 (n = 0 to 2) */ + + struct + { + __IOM uint32_t MAC_ADDR : 32; /*!< [31..0] The first 4 bytes of the MAC address of the port. First + * byte is bits [7:0]. The MAC address is used on locally + * generated frames such as pause frames, peer-delay response. */ + } MAC_ADDR_0_P2_b; + }; + + union + { + __IOM uint32_t MAC_ADDR_1_P2; /*!< (@ 0x00001010) Port 2 MAC Address Register 1 (n = 0 to 2) */ + + struct + { + __IOM uint32_t MAC_ADDR : 16; /*!< [15..0] The last 2 bytes of the MAC address of the port. Bits + * [7:0] is the 5th byte and bits [15:8] is the 6th byte. */ + uint32_t : 16; + } MAC_ADDR_1_P2_b; + }; + + union + { + __IOM uint32_t FRM_LENGTH_P2; /*!< (@ 0x00001014) Port 2 Maximum Frame Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length */ + uint32_t : 18; + } FRM_LENGTH_P2_b; + }; + + union + { + __IM uint32_t PAUSE_QUANT_P2; /*!< (@ 0x00001018) Port 2 MAC Pause Quanta (n = 0 to 3) */ + + struct + { + __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta */ + uint32_t : 16; + } PAUSE_QUANT_P2_b; + }; + + union + { + __IOM uint32_t MAC_LINK_QTRIG_P2; /*!< (@ 0x0000101C) Port 2 Trigger Event Configuration Register (n + * = 0 to 2) */ + + struct + { + __IOM uint32_t PORT_MASK : 4; /*!< [3..0] Per-port Bit Mask */ + uint32_t : 12; + __IOM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame + * is transmitted from the ports indicated by PORT_MASK. A + * single frame is transmitted per indicated port in PORT_MASK + * among the queues indicated by QUEUE_MASK. */ + uint32_t : 4; + __IOM uint32_t TRIGGERED : 1; /*!< [28..28] When MODE is set to 1, TRIGGERED indicates whether + * a frame was transmitted. When MODE is set to 0, TRIGGERED + * is always 0. This flag clears when the register is written. */ + __IOM uint32_t DLR_MODE : 1; /*!< [29..29] When set to 0, the DLR state machine is ignored. When + * set to 1, the Link Queue Trigger occurs only if the DLR + * state machine is in the NORMAL or FAULT state. */ + __IOM uint32_t MODE : 1; /*!< [30..30] When set to 0, only a single Link_Status frame is generated. + * This is to prevent sending multiple frames due to link + * flapping. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Write to 1 to enable the Link Queue Trigger feature. + * When the link status (phy_link) transitions from 1 -> + * 0, a trigger event is generated to the memory controller + * for the ports and queues indicated in PORT_MASK and QUEUE_MASK. */ + } MAC_LINK_QTRIG_P2_b; + }; + __IM uint32_t RESERVED41[4]; + + union + { + __IOM uint32_t PTPCLOCKIDENTITY1_P2; /*!< (@ 0x00001030) Port 2 PTP Clock Identity 1 Register (n = 0 to + * 2) */ + + struct + { + __IOM uint32_t CLK_IDENTITY0 : 8; /*!< [7..0] 20, portIdentity.ClockIdentity[0] */ + __IOM uint32_t CLK_IDENTITY1 : 8; /*!< [15..8] 21, portIdentity.ClockIdentity[1] */ + __IOM uint32_t CLK_IDENTITY2 : 8; /*!< [23..16] 22, portIdentity.ClockIdentity[2] */ + __IOM uint32_t CLK_IDENTITY3 : 8; /*!< [31..24] 23, portIdentity.ClockIdentity[3] */ + } PTPCLOCKIDENTITY1_P2_b; + }; + + union + { + __IOM uint32_t PTPCLOCKIDENTITY2_P2; /*!< (@ 0x00001034) Port 2 PTP Clock Identity 2 Register (n = 0 to + * 2) */ + + struct + { + __IOM uint32_t CLK_IDENTITY4 : 8; /*!< [7..0] 24, portIdentity.ClockIdentity[4] */ + __IOM uint32_t CLK_IDENTITY5 : 8; /*!< [15..8] 25, portIdentity.ClockIdentity[5] */ + __IOM uint32_t CLK_IDENTITY6 : 8; /*!< [23..16] 26, portIdentity.ClockIdentity[6] */ + __IOM uint32_t CLK_IDENTITY7 : 8; /*!< [31..24] 27, portIdentity.ClockIdentity[7] */ + } PTPCLOCKIDENTITY2_P2_b; + }; + + union + { + __IOM uint32_t PTPAUTORESPONSE_P2; /*!< (@ 0x00001038) Port 2 PTP Auto Response Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t ARSP_EN : 1; /*!< [0..0] Auto Response Enable */ + __IOM uint32_t D_TIMER : 1; /*!< [1..1] Default timer to use for auto-response generation */ + uint32_t : 14; + __IOM uint32_t PORTNUM1 : 8; /*!< [23..16] 29, portIdentity.PortNumber[1] (lsb) */ + __IOM uint32_t PORTNUM0 : 8; /*!< [31..24] 28, portIdentity.PortNumber[0] (msb) */ + } PTPAUTORESPONSE_P2_b; + }; + __IM uint32_t RESERVED42; + + union + { + __IOM uint32_t STATUS_P2; /*!< (@ 0x00001040) Port 2 Status Register */ + + struct + { + __IM uint32_t PHYSPEED : 2; /*!< [1..0] Currently Active PHY Interface Speed */ + __IM uint32_t PHYLINK : 1; /*!< [2..2] Link status from PHY interface */ + __IM uint32_t PHYDUPLEX : 1; /*!< [3..3] Duplex status from PHY interface */ + __IOM uint32_t TX_UNDFLW : 1; /*!< [4..4] Indicates that the transmit MAC underflow. This shall + * never occur during normal operation. */ + __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed + * to complete in time before the next frame was received + * at the port. This should never occur under normal operation. + * The cause could be from IPG violations in the received + * frames. */ + __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according + * to clause 30.14.1.2 of the 802.3br specification */ + uint32_t : 23; + } STATUS_P2_b; + }; + + union + { + __IOM uint32_t TX_IPG_LENGTH_P2; /*!< (@ 0x00001044) Port 2 Transmit IPG Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values + * are in the range of 8 to 31. */ + uint32_t : 11; + __IOM uint32_t MINRTC3GAP : 5; /*!< [20..16] MINRTC3GAP */ + uint32_t : 11; + } TX_IPG_LENGTH_P2_b; + }; + + union + { + __IOM uint32_t EEE_CTL_STAT_P2; /*!< (@ 0x00001048) Port 2 MAC EEE Functions Control and Status (n + * = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_AUTO : 1; /*!< [0..0] EEE Automatic Mode of Operation */ + __IOM uint32_t LPI_REQ : 1; /*!< [1..1] Request LPI Transmission when MAC Becomes Idle */ + __IOM uint32_t LPI_TXHOLD : 1; /*!< [2..2] MAC Transmission Hold */ + uint32_t : 5; + __IM uint32_t ST_LPI_REQ : 1; /*!< [8..8] Status (real time) of Internal LPI_REQ to the MAC */ + __IM uint32_t ST_LPI_TXHOLD : 1; /*!< [9..9] Status (real time) of Internal LPI_TXHOLD to the MAC */ + __IM uint32_t ST_TXBUSY : 1; /*!< [10..10] Status (real time) if the MAC is currently transmitting. */ + __IM uint32_t ST_TXAVAIL : 1; /*!< [11..11] Status (real time) if the MAC transmit FIFO has data + * available for transmission. */ + __IM uint32_t ST_LPI_IND : 1; /*!< [12..12] Status (real time) of Received LPI */ + uint32_t : 3; + __IM uint32_t STLH_LPI_REQ : 1; /*!< [16..16] Status (latched high) of Internal LPI_REQ to the MAC */ + __IM uint32_t STLH_LPI_TXHOLD : 1; /*!< [17..17] Status (latched high) of Internal LPI_TXHOLD to the + * MAC */ + __IM uint32_t STLH_TXBUSY : 1; /*!< [18..18] Status (latched high) if the MAC is/was Transmitting */ + uint32_t : 1; + __IM uint32_t STLH_LPI_IND : 1; /*!< [20..20] Status (latched high) of Received LPI (ST_LPI_IND) */ + uint32_t : 11; + } EEE_CTL_STAT_P2_b; + }; + + union + { + __IOM uint32_t EEE_IDLE_TIME_P2; /*!< (@ 0x0000104C) Port 2 EEE Idle Time Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_IDLE_TIME : 32; /*!< [31..0] Time (-1) the transmitter must be idle before transmission + * of LPI begins. A 32-bit value in steps of 32 switch operating + * clock cycles. A value of 0 disables the timer. The value + * must be set to 1 less count. */ + } EEE_IDLE_TIME_P2_b; + }; + + union + { + __IOM uint32_t EEE_TWSYS_TIME_P2; /*!< (@ 0x00001050) Port 2 EEE Wake Up Time Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_WKUP_TIME : 32; /*!< [31..0] Time (-1) after PHY wakeup until the MAC is allowed + * to begin transmitting the first frame again. A 32-bit value + * in steps of switch operating clock cycles. A value of 0 + * disables the timer. The value must be set to 1 less count. */ + } EEE_TWSYS_TIME_P2_b; + }; + + union + { + __IOM uint32_t IDLE_SLOPE_P2; /*!< (@ 0x00001054) Port n MAC Traffic Shaper Bandwidth Control (n + * = 0 to 3) */ + + struct + { + __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control */ + uint32_t : 21; + } IDLE_SLOPE_P2_b; + }; + + union + { + __IOM uint32_t CT_DELAY_P2; /*!< (@ 0x00001058) Port n Cut-Through Delay Indication Register + * (n = 0 to 2) */ + + struct + { + __IOM uint32_t CT_DELAY : 9; /*!< [8..0] Delay Value in 400 ns / 40 ns / 8 ns increments (frequency + * of the MII PHY interface) */ + uint32_t : 23; + } CT_DELAY_P2_b; + }; + + union + { + __IOM uint32_t BR_CONTROL_P2; /*!< (@ 0x0000105C) Port 2 802.3br Frame Configuration Register */ + + struct + { + __IOM uint32_t PREEMPT_ENA : 1; /*!< [0..0] When set to 1, enables 802.3br Frame Preemption. */ + __IOM uint32_t VERIFY_DIS : 1; /*!< [1..1] When set to 1, disables the verify process required for + * preemption operation. */ + __IOM uint32_t RESPONSE_DIS : 1; /*!< [2..2] When set to 1 prevents the MAC from responding to "verify" + * frames. */ + uint32_t : 1; + __IOM uint32_t ADDFRAGSIZE : 2; /*!< [5..4] Minimum fragment size in increments of 64 bytes. */ + uint32_t : 2; + __IOM uint32_t TX_VERIFY_TIME : 7; /*!< [14..8] Preemption verification timeout in milliseconds. */ + uint32_t : 1; + __IOM uint32_t RX_STRICT_PRE : 1; /*!< [16..16] When set to 1, the preamble is checked so all bytes + * except the SFD are 0x55. When set to 0, only the last 2 + * bytes of the preamble are checked (SFD/SMD and FRAG_COUNT). + * It is recommended to set this bit to 1 to comply with the + * 802.3br specification. This bit must be set to 0 if only + * non-802.3br traffic is expected (for example, normal Ethernet + * traffic) and if custom preamble is used. */ + __IOM uint32_t RX_BR_SMD_DIS : 1; /*!< [17..17] When set to 1, the receiver does not decode the 802.3br + * SMDs and assumes all frames are express frames. This bit + * must be set to 0 for correct operation with 802.3br, and + * can be set to 1 when 802.3br is not enabled to avoid false + * detection of SMDs. */ + __IOM uint32_t RX_STRICT_BR_CTL : 1; /*!< [18..18] When set to 1, strict checking of VERIFY and RESPONSE + * frames is enabled. When set to 1, the frame contents and + * frame length checks are also performed on these frames. + * The mCRC is always checked regardless of the value of this + * register. This bit must be set to 0 to be compliant with + * the functionality described in IEEE 802.3br. */ + __IOM uint32_t TX_MCRC_INV : 1; /*!< [19..19] When set to 1, the 32-bit XOR mask used to calculate + * the mCRC for transmitted frames is inverted. This bit must + * always be written to 0 and only used for debugging. */ + __IOM uint32_t RX_MCRC_INV : 1; /*!< [20..20] When set to 1, the 32-bit XOR mask used to calculate + * the mCRC for received frames is inverted. This bit must + * always be written to 0 and only used for debugging. */ + uint32_t : 11; + } BR_CONTROL_P2_b; + }; + __IM uint32_t RESERVED43[2]; + + union + { + __IM uint32_t AFRAMESTRANSMITTEDOK_P2; /*!< (@ 0x00001068) Port 2 MAC Transmitted Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Transmitted, including pause. */ + } AFRAMESTRANSMITTEDOK_P2_b; + }; + + union + { + __IM uint32_t AFRAMESRECEIVEDOK_P2; /*!< (@ 0x0000106C) Port 2 MAC Received Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Received, including pause. */ + } AFRAMESRECEIVEDOK_P2_b; + }; + + union + { + __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P2; /*!< (@ 0x00001070) Port 2 MAC FCS Error Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t FCSERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Length except CRC error. */ + } AFRAMECHECKSEQUENCEERRORS_P2_b; + }; + + union + { + __IM uint32_t AALIGNMENTERRORS_P2; /*!< (@ 0x00001074) Port 2 MAC Alignment Error Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number + * of Nibbles (MII) Received. */ + } AALIGNMENTERRORS_P2_b; + }; + + union + { + __IM uint32_t AOCTETSTRANSMITTEDOK_P2; /*!< (@ 0x00001078) Port 2 MAC Transmitted Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Transmitted. */ + } AOCTETSTRANSMITTEDOK_P2_b; + }; + + union + { + __IM uint32_t AOCTETSRECEIVEDOK_P2; /*!< (@ 0x0000107C) Port 2 MAC Received Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Received. */ + } AOCTETSRECEIVEDOK_P2_b; + }; + + union + { + __IM uint32_t ATXPAUSEMACCTRLFRAMES_P2; /*!< (@ 0x00001080) Port 2 MAC Transmitted Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Transmitted. */ + } ATXPAUSEMACCTRLFRAMES_P2_b; + }; + + union + { + __IM uint32_t ARXPAUSEMACCTRLFRAMES_P2; /*!< (@ 0x00001084) Port 2 MAC Received Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Received. */ + } ARXPAUSEMACCTRLFRAMES_P2_b; + }; + + union + { + __IM uint32_t IFINERRORS_P2; /*!< (@ 0x00001088) Port 2 MAC Input Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error + * During Reception such as CRC, Length, PHY Error, RX FIFO + * Overflow. */ + } IFINERRORS_P2_b; + }; + + union + { + __IM uint32_t IFOUTERRORS_P2; /*!< (@ 0x0000108C) Port 2 MAC Output Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame + * Transmitted with PHY error. */ + } IFOUTERRORS_P2_b; + }; + + union + { + __IM uint32_t IFINUCASTPKTS_P2; /*!< (@ 0x00001090) Port 2 MAC Received Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Received. */ + } IFINUCASTPKTS_P2_b; + }; + + union + { + __IM uint32_t IFINMULTICASTPKTS_P2; /*!< (@ 0x00001094) Port 2 MAC Received Multicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Received. */ + } IFINMULTICASTPKTS_P2_b; + }; + + union + { + __IM uint32_t IFINBROADCASTPKTS_P2; /*!< (@ 0x00001098) Port 2 MAC Received Broadcast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Received. */ + } IFINBROADCASTPKTS_P2_b; + }; + + union + { + __IM uint32_t IFOUTDISCARDS_P2; /*!< (@ 0x0000109C) Port 2 MAC Discarded Outbound Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable */ + } IFOUTDISCARDS_P2_b; + }; + + union + { + __IM uint32_t IFOUTUCASTPKTS_P2; /*!< (@ 0x000010A0) Port 2 MAC Transmitted Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Transmitted. */ + } IFOUTUCASTPKTS_P2_b; + }; + + union + { + __IM uint32_t IFOUTMULTICASTPKTS_P2; /*!< (@ 0x000010A4) Port 2 MAC Transmitted Multicast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Transmitted. */ + } IFOUTMULTICASTPKTS_P2_b; + }; + + union + { + __IM uint32_t IFOUTBROADCASTPKTS_P2; /*!< (@ 0x000010A8) Port 2 MAC Transmitted Broadcast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Transmitted. */ + } IFOUTBROADCASTPKTS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSDROPEVENTS_P2; /*!< (@ 0x000010AC) Port 2 MAC Dropped Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t DROPCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO + * Full at frame start. */ + } ETHERSTATSDROPEVENTS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSOCTETS_P2; /*!< (@ 0x000010B0) Port 2 MAC All Frame Octets Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLOCTETS : 32; /*!< [31..0] ALLOCTETS */ + } ETHERSTATSOCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS_P2; /*!< (@ 0x000010B4) Port 2 MAC All Frame Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT */ + } ETHERSTATSPKTS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P2; /*!< (@ 0x000010B8) Port 2 MAC Too Short Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t TOOSHRTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Good CRC. */ + } ETHERSTATSUNDERSIZEPKTS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSOVERSIZEPKTS_P2; /*!< (@ 0x000010BC) Port 2 MAC Too Long Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t TOOLONGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Good CRC. */ + } ETHERSTATSOVERSIZEPKTS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS64OCTETS_P2; /*!< (@ 0x000010C0) Port 2 MAC 64 Octets Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT64 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 64 bytes). */ + } ETHERSTATSPKTS64OCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P2; /*!< (@ 0x000010C4) Port 2 MAC 65 to 127 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT65T127 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 65 to 127 bytes). */ + } ETHERSTATSPKTS65TO127OCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P2; /*!< (@ 0x000010C8) Port 2 MAC 128 to 255 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT128T255 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 128 to 255 bytes). */ + } ETHERSTATSPKTS128TO255OCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P2; /*!< (@ 0x000010CC) Port 2 MAC 256 to 511 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT256T511 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 256 to 511 bytes). */ + } ETHERSTATSPKTS256TO511OCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P2; /*!< (@ 0x000010D0) Port 2 MAC 512 to 1023 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT512T1023 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 512 to 1023 bytes). */ + } ETHERSTATSPKTS512TO1023OCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P2; /*!< (@ 0x000010D4) Port 2 MAC 1024 to 1518 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1024T1518 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 1024 to 1518 bytes). */ + } ETHERSTATSPKTS1024TO1518OCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P2; /*!< (@ 0x000010D8) Port 2 MAC Over 1519 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1519TX : 32; /*!< [31..0] PORT n, this field indicates the number of MAC all Frames, + * Good and Bad (Packet Size: over 1519 bytes). */ + } ETHERSTATSPKTS1519TOXOCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSJABBERS_P2; /*!< (@ 0x000010DC) Port 2 MAC Jabbers Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Bad CRC. */ + } ETHERSTATSJABBERS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSFRAGMENTS_P2; /*!< (@ 0x000010E0) Port 2 MAC Fragment Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t FRAGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Bad CRC. */ + } ETHERSTATSFRAGMENTS_P2_b; + }; + __IM uint32_t RESERVED44; + + union + { + __IM uint32_t VLANRECEIVEDOK_P2; /*!< (@ 0x000010E8) Port 2 MAC Received VLAN Tagged Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Received. */ + } VLANRECEIVEDOK_P2_b; + }; + __IM uint32_t RESERVED45[2]; + + union + { + __IM uint32_t VLANTRANSMITTEDOK_P2; /*!< (@ 0x000010F4) Port 2 MAC Transmitted VLAN Tagged Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Transmitted. */ + } VLANTRANSMITTEDOK_P2_b; + }; + + union + { + __IM uint32_t FRAMESRETRANSMITTED_P2; /*!< (@ 0x000010F8) Port 2 MAC Retransmitted Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RETXCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Transmitted + * Frames that experienced a collision and were retransmitted. */ + } FRAMESRETRANSMITTED_P2_b; + }; + __IM uint32_t RESERVED46; + + union + { + __IM uint32_t STATS_HIWORD_P2; /*!< (@ 0x00001100) Port 2 MAC Statistics Counter High Word Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics + * Counter Last Read */ + } STATS_HIWORD_P2_b; + }; + + union + { + __IOM uint32_t STATS_CTRL_P2; /*!< (@ 0x00001104) Port 2 MAC Statistics Control Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t CLRALL : 1; /*!< [0..0] Self Clearing Counter Initialize Command */ + __IM uint32_t CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication */ + uint32_t : 30; + } STATS_CTRL_P2_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUELO_P2; /*!< (@ 0x00001108) Port 2 MAC Statistics Clear Value Lower Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUELO_P2_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUEHI_P2; /*!< (@ 0x0000110C) Port 2 MAC Statistics Clear Value Higher Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUEHI_P2_b; + }; + + union + { + __IM uint32_t ADEFERRED_P2; /*!< (@ 0x00001110) Port 2 MAC Deferred Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted + * without collision but was deferred at begin. */ + } ADEFERRED_P2_b; + }; + + union + { + __IM uint32_t AMULTIPLECOLLISIONS_P2; /*!< (@ 0x00001114) Port 2 MAC Multiple Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after multiple collisions. */ + } AMULTIPLECOLLISIONS_P2_b; + }; + + union + { + __IM uint32_t ASINGLECOLLISIONS_P2; /*!< (@ 0x00001118) Port 2 MAC Single Collision Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after single collision. */ + } ASINGLECOLLISIONS_P2_b; + }; + + union + { + __IM uint32_t ALATECOLLISIONS_P2; /*!< (@ 0x0000111C) Port 2 MAC Late Collision Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late + * Collision. Frame was aborted and not retransmitted. */ + } ALATECOLLISIONS_P2_b; + }; + + union + { + __IM uint32_t AEXCESSIVECOLLISIONS_P2; /*!< (@ 0x00001120) Port 2 MAC Excessive Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t EXCCOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frames Discarded + * due to 16 consecutive collisions. */ + } AEXCESSIVECOLLISIONS_P2_b; + }; + + union + { + __IM uint32_t ACARRIERSENSEERRORS_P2; /*!< (@ 0x00001124) Port 2 MAC Carrier Sense Error Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t CSERRCOUNT : 32; /*!< [31..0] PORT n, increments during Transmission without Collisions + * the PHY Carrier Sense Signal (RX_CRS) dropped or never + * asserted. */ + } ACARRIERSENSEERRORS_P2_b; + }; + __IM uint32_t RESERVED47[182]; + + union + { + __IM uint32_t REV_P3; /*!< (@ 0x00001400) Port 3 MAC Core Revision (n = 0 to 3) */ + + struct + { + __IM uint32_t REV : 32; /*!< [31..0] MAC Core Revision */ + } REV_P3_b; + }; + __IM uint32_t RESERVED48; + + union + { + __IOM uint32_t COMMAND_CONFIG_P3; /*!< (@ 0x00001408) Port 3 Command Configuration Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t TX_ENA : 1; /*!< [0..0] Enable/Disable MAC Transmit Path */ + __IOM uint32_t RX_ENA : 1; /*!< [1..1] Enable/Disable MAC Receive Path */ + __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from + * the IMC until the current frame is completed. This can + * cause the IPG between frames to be more than the value + * in TX_IPG_LENGTH. */ + __IOM uint32_t ETH_SPEED : 1; /*!< [3..3] Operation Mode Definition */ + __IM uint32_t PROMIS_EN : 1; /*!< [4..4] Enable/Disable MAC Promiscuous Operation */ + __IM uint32_t PAD_EN : 1; /*!< [5..5] Enable/Disable Frame Padding Remove on Receive */ + uint32_t : 1; + __IM uint32_t PAUSE_FWD : 1; /*!< [7..7] Terminate/Forward Pause Frames */ + __IOM uint32_t PAUSE_IGNORE : 1; /*!< [8..8] Ignore Pause Frame Quanta */ + __IM uint32_t TX_ADDR_INS : 1; /*!< [9..9] Non writable bit, fixed to 0 always. */ + __IOM uint32_t HD_ENA : 1; /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or + * full-duplex only (set to 0). */ + __IOM uint32_t TX_CRC_APPEND : 1; /*!< [11..11] Enable CRC Append on Transmit */ + uint32_t : 1; + __IOM uint32_t SW_RESET : 1; /*!< [13..13] Self Clearing Reset Command Bit */ + uint32_t : 9; + __IOM uint32_t CNTL_FRM_ENA : 1; /*!< [23..23] MAC Control Frame Enable */ + __IOM uint32_t NO_LGTH_CHK : 1; /*!< [24..24] Payload Length Check Disable */ + __IOM uint32_t ENA_10 : 1; /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn + * register. */ + uint32_t : 4; + __IOM uint32_t TIMER_SEL : 1; /*!< [30..30] Selects the default timer to use for timestamping operations + * on transmit and on receive. The value is used when not + * overridden by the PTP auto-response function, pattern matchers + * or force forwarding information in a management tag. */ + uint32_t : 1; + } COMMAND_CONFIG_P3_b; + }; + __IM uint32_t RESERVED49[2]; + + union + { + __IOM uint32_t FRM_LENGTH_P3; /*!< (@ 0x00001414) Port 3 Maximum Frame Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length */ + uint32_t : 18; + } FRM_LENGTH_P3_b; + }; + + union + { + __IM uint32_t PAUSE_QUANT_P3; /*!< (@ 0x00001418) Port 3 MAC Pause Quanta (n = 0 to 3) */ + + struct + { + __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta */ + uint32_t : 16; + } PAUSE_QUANT_P3_b; + }; + __IM uint32_t RESERVED50[9]; + + union + { + __IOM uint32_t STATUS_P3; /*!< (@ 0x00001440) Port 3 Status Register */ + + struct + { + __IM uint32_t PHYSPEED : 2; /*!< [1..0] Currently Active PHY Interface Speed */ + __IM uint32_t PHYLINK : 1; /*!< [2..2] Link status from PHY interface */ + __IM uint32_t PHYDUPLEX : 1; /*!< [3..3] Duplex status from PHY interface */ + __IOM uint32_t TX_UNDFLW : 1; /*!< [4..4] Indicates that the transmit MAC underflow. This shall + * never occur during normal operation. */ + __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed + * to complete in time before the next frame was received + * at the port. This should never occur under normal operation. + * The cause could be from IPG violations in the received + * frames. */ + __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according + * to clause 30.14.1.2 of the 802.3br specification */ + uint32_t : 23; + } STATUS_P3_b; + }; + + union + { + __IOM uint32_t TX_IPG_LENGTH_P3; /*!< (@ 0x00001444) Port 3 Transmit IPG Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values + * are in the range of 8 to 31. */ + uint32_t : 11; + __IOM uint32_t MINRTC3GAP : 5; /*!< [20..16] MINRTC3GAP */ + uint32_t : 11; + } TX_IPG_LENGTH_P3_b; + }; + __IM uint32_t RESERVED51[3]; + + union + { + __IOM uint32_t IDLE_SLOPE_P3; /*!< (@ 0x00001454) Port n MAC Traffic Shaper Bandwidth Control (n + * = 0 to 3) */ + + struct + { + __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control */ + uint32_t : 21; + } IDLE_SLOPE_P3_b; + }; + __IM uint32_t RESERVED52[4]; + + union + { + __IM uint32_t AFRAMESTRANSMITTEDOK_P3; /*!< (@ 0x00001468) Port 3 MAC Transmitted Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Transmitted, including pause. */ + } AFRAMESTRANSMITTEDOK_P3_b; + }; + + union + { + __IM uint32_t AFRAMESRECEIVEDOK_P3; /*!< (@ 0x0000146C) Port 3 MAC Received Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Received, including pause. */ + } AFRAMESRECEIVEDOK_P3_b; + }; + + union + { + __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P3; /*!< (@ 0x00001470) Port 3 MAC FCS Error Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t FCSERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Length except CRC error. */ + } AFRAMECHECKSEQUENCEERRORS_P3_b; + }; + + union + { + __IM uint32_t AALIGNMENTERRORS_P3; /*!< (@ 0x00001474) Port 3 MAC Alignment Error Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number + * of Nibbles (MII) Received. */ + } AALIGNMENTERRORS_P3_b; + }; + + union + { + __IM uint32_t AOCTETSTRANSMITTEDOK_P3; /*!< (@ 0x00001478) Port 3 MAC Transmitted Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Transmitted. */ + } AOCTETSTRANSMITTEDOK_P3_b; + }; + + union + { + __IM uint32_t AOCTETSRECEIVEDOK_P3; /*!< (@ 0x0000147C) Port 3 MAC Received Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Received. */ + } AOCTETSRECEIVEDOK_P3_b; + }; + + union + { + __IM uint32_t ATXPAUSEMACCTRLFRAMES_P3; /*!< (@ 0x00001480) Port 3 MAC Transmitted Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Transmitted. */ + } ATXPAUSEMACCTRLFRAMES_P3_b; + }; + + union + { + __IM uint32_t ARXPAUSEMACCTRLFRAMES_P3; /*!< (@ 0x00001484) Port 3 MAC Received Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Received. */ + } ARXPAUSEMACCTRLFRAMES_P3_b; + }; + + union + { + __IM uint32_t IFINERRORS_P3; /*!< (@ 0x00001488) Port 3 MAC Input Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error + * During Reception such as CRC, Length, PHY Error, RX FIFO + * Overflow. */ + } IFINERRORS_P3_b; + }; + + union + { + __IM uint32_t IFOUTERRORS_P3; /*!< (@ 0x0000148C) Port 3 MAC Output Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame + * Transmitted with PHY error. */ + } IFOUTERRORS_P3_b; + }; + + union + { + __IM uint32_t IFINUCASTPKTS_P3; /*!< (@ 0x00001490) Port 3 MAC Received Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Received. */ + } IFINUCASTPKTS_P3_b; + }; + + union + { + __IM uint32_t IFINMULTICASTPKTS_P3; /*!< (@ 0x00001494) Port 3 MAC Received Multicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Received. */ + } IFINMULTICASTPKTS_P3_b; + }; + + union + { + __IM uint32_t IFINBROADCASTPKTS_P3; /*!< (@ 0x00001498) Port 3 MAC Received Broadcast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Received. */ + } IFINBROADCASTPKTS_P3_b; + }; + + union + { + __IM uint32_t IFOUTDISCARDS_P3; /*!< (@ 0x0000149C) Port 3 MAC Discarded Outbound Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable */ + } IFOUTDISCARDS_P3_b; + }; + + union + { + __IM uint32_t IFOUTUCASTPKTS_P3; /*!< (@ 0x000014A0) Port 3 MAC Transmitted Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Transmitted. */ + } IFOUTUCASTPKTS_P3_b; + }; + + union + { + __IM uint32_t IFOUTMULTICASTPKTS_P3; /*!< (@ 0x000014A4) Port 3 MAC Transmitted Multicast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Transmitted. */ + } IFOUTMULTICASTPKTS_P3_b; + }; + + union + { + __IM uint32_t IFOUTBROADCASTPKTS_P3; /*!< (@ 0x000014A8) Port 3 MAC Transmitted Broadcast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Transmitted. */ + } IFOUTBROADCASTPKTS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSDROPEVENTS_P3; /*!< (@ 0x000014AC) Port 3 MAC Dropped Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t DROPCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO + * Full at frame start. */ + } ETHERSTATSDROPEVENTS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSOCTETS_P3; /*!< (@ 0x000014B0) Port 3 MAC All Frame Octets Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLOCTETS : 32; /*!< [31..0] ALLOCTETS */ + } ETHERSTATSOCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS_P3; /*!< (@ 0x000014B4) Port 3 MAC All Frame Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT */ + } ETHERSTATSPKTS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P3; /*!< (@ 0x000014B8) Port 3 MAC Too Short Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t TOOSHRTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Good CRC. */ + } ETHERSTATSUNDERSIZEPKTS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSOVERSIZEPKTS_P3; /*!< (@ 0x000014BC) Port 3 MAC Too Long Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t TOOLONGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Good CRC. */ + } ETHERSTATSOVERSIZEPKTS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS64OCTETS_P3; /*!< (@ 0x000014C0) Port 3 MAC 64 Octets Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT64 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 64 bytes). */ + } ETHERSTATSPKTS64OCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P3; /*!< (@ 0x000014C4) Port 3 MAC 65 to 127 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT65T127 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 65 to 127 bytes). */ + } ETHERSTATSPKTS65TO127OCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P3; /*!< (@ 0x000014C8) Port 3 MAC 128 to 255 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT128T255 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 128 to 255 bytes). */ + } ETHERSTATSPKTS128TO255OCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P3; /*!< (@ 0x000014CC) Port 3 MAC 256 to 511 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT256T511 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 256 to 511 bytes). */ + } ETHERSTATSPKTS256TO511OCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P3; /*!< (@ 0x000014D0) Port 3 MAC 512 to 1023 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT512T1023 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 512 to 1023 bytes). */ + } ETHERSTATSPKTS512TO1023OCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P3; /*!< (@ 0x000014D4) Port 3 MAC 1024 to 1518 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1024T1518 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 1024 to 1518 bytes). */ + } ETHERSTATSPKTS1024TO1518OCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P3; /*!< (@ 0x000014D8) Port 3 MAC Over 1519 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1519TX : 32; /*!< [31..0] PORT n, this field indicates the number of MAC all Frames, + * Good and Bad (Packet Size: over 1519 bytes). */ + } ETHERSTATSPKTS1519TOXOCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSJABBERS_P3; /*!< (@ 0x000014DC) Port 3 MAC Jabbers Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Bad CRC. */ + } ETHERSTATSJABBERS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSFRAGMENTS_P3; /*!< (@ 0x000014E0) Port 3 MAC Fragment Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t FRAGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Bad CRC. */ + } ETHERSTATSFRAGMENTS_P3_b; + }; + __IM uint32_t RESERVED53; + + union + { + __IM uint32_t VLANRECEIVEDOK_P3; /*!< (@ 0x000014E8) Port 3 MAC Received VLAN Tagged Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Received. */ + } VLANRECEIVEDOK_P3_b; + }; + __IM uint32_t RESERVED54[2]; + + union + { + __IM uint32_t VLANTRANSMITTEDOK_P3; /*!< (@ 0x000014F4) Port 3 MAC Transmitted VLAN Tagged Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Transmitted. */ + } VLANTRANSMITTEDOK_P3_b; + }; + + union + { + __IM uint32_t FRAMESRETRANSMITTED_P3; /*!< (@ 0x000014F8) Port 3 MAC Retransmitted Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RETXCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Transmitted + * Frames that experienced a collision and were retransmitted. */ + } FRAMESRETRANSMITTED_P3_b; + }; + __IM uint32_t RESERVED55; + + union + { + __IM uint32_t STATS_HIWORD_P3; /*!< (@ 0x00001500) Port 3 MAC Statistics Counter High Word Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics + * Counter Last Read */ + } STATS_HIWORD_P3_b; + }; + + union + { + __IOM uint32_t STATS_CTRL_P3; /*!< (@ 0x00001504) Port 3 MAC Statistics Control Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t CLRALL : 1; /*!< [0..0] Self Clearing Counter Initialize Command */ + __IM uint32_t CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication */ + uint32_t : 30; + } STATS_CTRL_P3_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUELO_P3; /*!< (@ 0x00001508) Port 3 MAC Statistics Clear Value Lower Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUELO_P3_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUEHI_P3; /*!< (@ 0x0000150C) Port 3 MAC Statistics Clear Value Higher Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUEHI_P3_b; + }; + + union + { + __IM uint32_t ADEFERRED_P3; /*!< (@ 0x00001510) Port 3 MAC Deferred Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted + * without collision but was deferred at begin. */ + } ADEFERRED_P3_b; + }; + + union + { + __IM uint32_t AMULTIPLECOLLISIONS_P3; /*!< (@ 0x00001514) Port 3 MAC Multiple Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after multiple collisions. */ + } AMULTIPLECOLLISIONS_P3_b; + }; + + union + { + __IM uint32_t ASINGLECOLLISIONS_P3; /*!< (@ 0x00001518) Port 3 MAC Single Collision Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after single collision. */ + } ASINGLECOLLISIONS_P3_b; + }; + + union + { + __IM uint32_t ALATECOLLISIONS_P3; /*!< (@ 0x0000151C) Port 3 MAC Late Collision Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late + * Collision. Frame was aborted and not retransmitted. */ + } ALATECOLLISIONS_P3_b; + }; + + union + { + __IM uint32_t AEXCESSIVECOLLISIONS_P3; /*!< (@ 0x00001520) Port 3 MAC Excessive Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t EXCCOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frames Discarded + * due to 16 consecutive collisions. */ + } AEXCESSIVECOLLISIONS_P3_b; + }; + + union + { + __IM uint32_t ACARRIERSENSEERRORS_P3; /*!< (@ 0x00001524) Port 3 MAC Carrier Sense Error Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t CSERRCOUNT : 32; /*!< [31..0] PORT n, increments during Transmission without Collisions + * the PHY Carrier Sense Signal (RX_CRS) dropped or never + * asserted. */ + } ACARRIERSENSEERRORS_P3_b; + }; + __IM uint32_t RESERVED56[1975]; + + union + { + __IM uint32_t STATN_STATUS; /*!< (@ 0x00003404) Statistics Status Register */ + + struct + { + __IM uint32_t BUSY : 1; /*!< [0..0] Statistics module is busy */ + uint32_t : 31; + } STATN_STATUS_b; + }; + + union + { + __IOM uint32_t STATN_CONFIG; /*!< (@ 0x00003408) Statistics Configure Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t CLEAR_ON_READ : 1; /*!< [1..1] When set to 1, a read to a counter resets it to 0. When + * set to 0 (default), counters are not affected by read. */ + uint32_t : 29; + __IOM uint32_t RESET : 1; /*!< [31..31] When set to 1, all internal functions are aborted and + * return to a stable state (flushes prescalers). It also + * triggers a clear of all counter memory (all ports are cleared) + * by setting STATN_CONTROL.CMD_CLEAR with all mask bits. + * Capture memory is not reset. */ + } STATN_CONFIG_b; + }; + + union + { + __IOM uint32_t STATN_CONTROL; /*!< (@ 0x0000340C) Statistics Control Register */ + + struct + { + __IOM uint32_t CHANMASK : 4; /*!< [3..0] One bit per port. Bit 0 = port 0, bit 1 = port 1, and + * so on. */ + uint32_t : 25; + __IOM uint32_t CLEAR_PRE : 1; /*!< [29..29] Clear the internal pre-scaler counters of ports when + * a clear occurs. This bit can be used together with the + * CMD_CLEAR command to clear the internal pre-scaler counters + * of the ports. */ + uint32_t : 1; + __IOM uint32_t CMD_CLEAR : 1; /*!< [31..31] Clear Channel Counters Command */ + } STATN_CONTROL_b; + }; + + union + { + __IOM uint32_t STATN_CLEARVALUE_LO; /*!< (@ 0x00003410) Statistics Clear Value Lower Register */ + + struct + { + __IOM uint32_t STATN_CLEARVALUE_LO : 32; /*!< [31..0] 32-bit value written into statistics memory when a clear + * command (STATN_CONTROL.CMD_CLEAR) is triggered (see ), + * or when a clear-after-read is used. */ + } STATN_CLEARVALUE_LO_b; + }; + __IM uint32_t RESERVED57[21]; + + union + { + __IM uint32_t ODISC0; /*!< (@ 0x00003468) Port 0 Discarded Outgoing Frame Count Register */ + + struct + { + __IM uint32_t ODISC : 32; /*!< [31..0] Port n outgoing frames discarded due to output queue + * congestion. */ + } ODISC0_b; + }; + + union + { + __IM uint32_t IDISC_VLAN0; /*!< (@ 0x0000346C) Port 0 Discarded Incoming VLAN Tagged Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching + * or missing VLAN ID while VLAN verification was enabled. */ + } IDISC_VLAN0_b; + }; + + union + { + __IM uint32_t IDISC_UNTAGGED0; /*!< (@ 0x00003470) Port 0 Discarded Incoming VLAN Untagged Frame + * Count Register */ + + struct + { + __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN + * tag. */ + } IDISC_UNTAGGED0_b; + }; + + union + { + __IM uint32_t IDISC_BLOCKED0; /*!< (@ 0x00003474) Port 0 Discarded Incoming Blocked Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as + * the port is configured in blocking mode. */ + } IDISC_BLOCKED0_b; + }; + + union + { + __IM uint32_t IDISC_ANY0; /*!< (@ 0x00003478) Port 0 Discarded Any Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes + * IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED. */ + } IDISC_ANY0_b; + }; + + union + { + __IM uint32_t IDISC_SRCFLT0; /*!< (@ 0x0000347C) Port 0 Discarded Address Source Count Register */ + + struct + { + __IM uint32_t IDISC_SRCFLT : 32; /*!< [31..0] Port n counts the number of incoming frames discarded + * due to the MAC address source filter. */ + } IDISC_SRCFLT0_b; + }; + + union + { + __IM uint32_t TX_HOLD_REQ_CNT0; /*!< (@ 0x00003480) Port 0 TX Hold Request Count Register */ + + struct + { + __IM uint32_t TX_HOLD_REQ_CNT : 32; /*!< [31..0] TX_HOLD_REQ_CNT */ + } TX_HOLD_REQ_CNT0_b; + }; + + union + { + __IM uint32_t TX_FRAG_CNT0; /*!< (@ 0x00003484) Port 0 TX for Preemption Count Register */ + + struct + { + __IM uint32_t TX_FRAG_CNT : 32; /*!< [31..0] Port n increments when an additional mPacket is transmitted + * due to preemption. */ + } TX_FRAG_CNT0_b; + }; + + union + { + __IM uint32_t RX_FRAG_CNT0; /*!< (@ 0x00003488) Port 0 RX Continuation Count Register */ + + struct + { + __IM uint32_t RX_FRAG_CNT : 32; /*!< [31..0] Port n increments for every continuation mPacket received. */ + } RX_FRAG_CNT0_b; + }; + + union + { + __IM uint32_t RX_ASSY_OK_CNT0; /*!< (@ 0x0000348C) Port 0 RX Preempted Frame Success Count Register */ + + struct + { + __IM uint32_t RX_ASSY_OK_CNT : 32; /*!< [31..0] Port n increments when a preempted frame is successfully + * assembled. */ + } RX_ASSY_OK_CNT0_b; + }; + + union + { + __IM uint32_t RX_ASSY_ERR_CNT0; /*!< (@ 0x00003490) Port 0 RX Preempted Frame Incorrect Count Register */ + + struct + { + __IM uint32_t RX_ASSY_ERR_CNT : 16; /*!< [15..0] Port n increments when a preempted frame is incorrectly + * assembled. */ + uint32_t : 16; + } RX_ASSY_ERR_CNT0_b; + }; + + union + { + __IM uint32_t RX_SMD_ERR_CNT0; /*!< (@ 0x00003494) Port 0 RX SMD Frame Count Register */ + + struct + { + __IM uint32_t RX_SMD_ERR_CNT : 16; /*!< [15..0] Port n increments when a frame with an SMD-Cx is received + * and no assembly is in progress. */ + uint32_t : 16; + } RX_SMD_ERR_CNT0_b; + }; + + union + { + __IM uint32_t TX_VERIFY_OK_CNT0; /*!< (@ 0x00003498) Port 0 TX VERIFY Frame Count Register */ + + struct + { + __IM uint32_t TX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every VERIFY frame transmitted. */ + uint32_t : 24; + } TX_VERIFY_OK_CNT0_b; + }; + + union + { + __IM uint32_t TX_RESPONSE_OK_CNT0; /*!< (@ 0x0000349C) Port 0 TX RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t TX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every RESPONSE frame transmitted. */ + uint32_t : 24; + } TX_RESPONSE_OK_CNT0_b; + }; + + union + { + __IM uint32_t RX_VERIFY_OK_CNT0; /*!< (@ 0x000034A0) Port 0 RX VERIFY Frame Count Register */ + + struct + { + __IM uint32_t RX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every valid VERIFY frame received. */ + uint32_t : 24; + } RX_VERIFY_OK_CNT0_b; + }; + + union + { + __IM uint32_t RX_RESPONSE_OK_CNT0; /*!< (@ 0x000034A4) Port 0 RX RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t RX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every valid RESPONSE frame received. */ + uint32_t : 24; + } RX_RESPONSE_OK_CNT0_b; + }; + + union + { + __IM uint32_t RX_VERIFY_BAD_CNT0; /*!< (@ 0x000034A8) Port 0 RX Error VERIFY Frame Count Register */ + + struct + { + __IM uint32_t RX_VERIFY_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored VERIFY frame received. */ + uint32_t : 24; + } RX_VERIFY_BAD_CNT0_b; + }; + + union + { + __IM uint32_t RX_RESPONSE_BAD_CNT0; /*!< (@ 0x000034AC) Port 0 RX Error RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t RX_RESPONSE_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored RESPONSE frame received. */ + uint32_t : 24; + } RX_RESPONSE_BAD_CNT0_b; + }; + + union + { + __IM uint32_t ODISC1; /*!< (@ 0x000034B0) Port 1 Discarded Outgoing Frame Count Register */ + + struct + { + __IM uint32_t ODISC : 32; /*!< [31..0] Port n outgoing frames discarded due to output queue + * congestion. */ + } ODISC1_b; + }; + + union + { + __IM uint32_t IDISC_VLAN1; /*!< (@ 0x000034B4) Port 1 Discarded Incoming VLAN Tagged Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching + * or missing VLAN ID while VLAN verification was enabled. */ + } IDISC_VLAN1_b; + }; + + union + { + __IM uint32_t IDISC_UNTAGGED1; /*!< (@ 0x000034B8) Port 1 Discarded Incoming VLAN Untagged Frame + * Count Register */ + + struct + { + __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN + * tag. */ + } IDISC_UNTAGGED1_b; + }; + + union + { + __IM uint32_t IDISC_BLOCKED1; /*!< (@ 0x000034BC) Port 1 Discarded Incoming Blocked Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as + * the port is configured in blocking mode. */ + } IDISC_BLOCKED1_b; + }; + + union + { + __IM uint32_t IDISC_ANY1; /*!< (@ 0x000034C0) Port 1 Discarded Any Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes + * IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED. */ + } IDISC_ANY1_b; + }; + + union + { + __IM uint32_t IDISC_SRCFLT1; /*!< (@ 0x000034C4) Port 1 Discarded Address Source Count Register */ + + struct + { + __IM uint32_t IDISC_SRCFLT : 32; /*!< [31..0] Port n counts the number of incoming frames discarded + * due to the MAC address source filter. */ + } IDISC_SRCFLT1_b; + }; + + union + { + __IM uint32_t TX_HOLD_REQ_CNT1; /*!< (@ 0x000034C8) Port 1 TX Hold Request Count Register */ + + struct + { + __IM uint32_t TX_HOLD_REQ_CNT : 32; /*!< [31..0] TX_HOLD_REQ_CNT */ + } TX_HOLD_REQ_CNT1_b; + }; + + union + { + __IM uint32_t TX_FRAG_CNT1; /*!< (@ 0x000034CC) Port 1 TX for Preemption Count Register */ + + struct + { + __IM uint32_t TX_FRAG_CNT : 32; /*!< [31..0] Port n increments when an additional mPacket is transmitted + * due to preemption. */ + } TX_FRAG_CNT1_b; + }; + + union + { + __IM uint32_t RX_FRAG_CNT1; /*!< (@ 0x000034D0) Port 1 RX Continuation Count Register */ + + struct + { + __IM uint32_t RX_FRAG_CNT : 32; /*!< [31..0] Port n increments for every continuation mPacket received. */ + } RX_FRAG_CNT1_b; + }; + + union + { + __IM uint32_t RX_ASSY_OK_CNT1; /*!< (@ 0x000034D4) Port 1 RX Preempted Frame Success Count Register */ + + struct + { + __IM uint32_t RX_ASSY_OK_CNT : 32; /*!< [31..0] Port n increments when a preempted frame is successfully + * assembled. */ + } RX_ASSY_OK_CNT1_b; + }; + + union + { + __IM uint32_t RX_ASSY_ERR_CNT1; /*!< (@ 0x000034D8) Port 1 RX Preempted Frame Incorrect Count Register */ + + struct + { + __IM uint32_t RX_ASSY_ERR_CNT : 16; /*!< [15..0] Port n increments when a preempted frame is incorrectly + * assembled. */ + uint32_t : 16; + } RX_ASSY_ERR_CNT1_b; + }; + + union + { + __IM uint32_t RX_SMD_ERR_CNT1; /*!< (@ 0x000034DC) Port 1 RX SMD Frame Count Register */ + + struct + { + __IM uint32_t RX_SMD_ERR_CNT : 16; /*!< [15..0] Port n increments when a frame with an SMD-Cx is received + * and no assembly is in progress. */ + uint32_t : 16; + } RX_SMD_ERR_CNT1_b; + }; + + union + { + __IM uint32_t TX_VERIFY_OK_CNT1; /*!< (@ 0x000034E0) Port 1 TX VERIFY Frame Count Register */ + + struct + { + __IM uint32_t TX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every VERIFY frame transmitted. */ + uint32_t : 24; + } TX_VERIFY_OK_CNT1_b; + }; + + union + { + __IM uint32_t TX_RESPONSE_OK_CNT1; /*!< (@ 0x000034E4) Port 1 TX RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t TX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every RESPONSE frame transmitted. */ + uint32_t : 24; + } TX_RESPONSE_OK_CNT1_b; + }; + + union + { + __IM uint32_t RX_VERIFY_OK_CNT1; /*!< (@ 0x000034E8) Port 1 RX VERIFY Frame Count Register */ + + struct + { + __IM uint32_t RX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every valid VERIFY frame received. */ + uint32_t : 24; + } RX_VERIFY_OK_CNT1_b; + }; + + union + { + __IM uint32_t RX_RESPONSE_OK_CNT1; /*!< (@ 0x000034EC) Port 1 RX RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t RX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every valid RESPONSE frame received. */ + uint32_t : 24; + } RX_RESPONSE_OK_CNT1_b; + }; + + union + { + __IM uint32_t RX_VERIFY_BAD_CNT1; /*!< (@ 0x000034F0) Port 1 RX Error VERIFY Frame Count Register */ + + struct + { + __IM uint32_t RX_VERIFY_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored VERIFY frame received. */ + uint32_t : 24; + } RX_VERIFY_BAD_CNT1_b; + }; + + union + { + __IM uint32_t RX_RESPONSE_BAD_CNT1; /*!< (@ 0x000034F4) Port 1 RX Error RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t RX_RESPONSE_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored RESPONSE frame received. */ + uint32_t : 24; + } RX_RESPONSE_BAD_CNT1_b; + }; + + union + { + __IM uint32_t ODISC2; /*!< (@ 0x000034F8) Port 2 Discarded Outgoing Frame Count Register */ + + struct + { + __IM uint32_t ODISC : 32; /*!< [31..0] Port n outgoing frames discarded due to output queue + * congestion. */ + } ODISC2_b; + }; + + union + { + __IM uint32_t IDISC_VLAN2; /*!< (@ 0x000034FC) Port 2 Discarded Incoming VLAN Tagged Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching + * or missing VLAN ID while VLAN verification was enabled. */ + } IDISC_VLAN2_b; + }; + + union + { + __IM uint32_t IDISC_UNTAGGED2; /*!< (@ 0x00003500) Port 2 Discarded Incoming VLAN Untagged Frame + * Count Register */ + + struct + { + __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN + * tag. */ + } IDISC_UNTAGGED2_b; + }; + + union + { + __IM uint32_t IDISC_BLOCKED2; /*!< (@ 0x00003504) Port 2 Discarded Incoming Blocked Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as + * the port is configured in blocking mode. */ + } IDISC_BLOCKED2_b; + }; + + union + { + __IM uint32_t IDISC_ANY2; /*!< (@ 0x00003508) Port 2 Discarded Any Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes + * IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED. */ + } IDISC_ANY2_b; + }; + + union + { + __IM uint32_t IDISC_SRCFLT2; /*!< (@ 0x0000350C) Port 2 Discarded Address Source Count Register */ + + struct + { + __IM uint32_t IDISC_SRCFLT : 32; /*!< [31..0] Port n counts the number of incoming frames discarded + * due to the MAC address source filter. */ + } IDISC_SRCFLT2_b; + }; + + union + { + __IM uint32_t TX_HOLD_REQ_CNT2; /*!< (@ 0x00003510) Port 2 TX Hold Request Count Register */ + + struct + { + __IM uint32_t TX_HOLD_REQ_CNT : 32; /*!< [31..0] TX_HOLD_REQ_CNT */ + } TX_HOLD_REQ_CNT2_b; + }; + + union + { + __IM uint32_t TX_FRAG_CNT2; /*!< (@ 0x00003514) Port 2 TX for Preemption Count Register */ + + struct + { + __IM uint32_t TX_FRAG_CNT : 32; /*!< [31..0] Port n increments when an additional mPacket is transmitted + * due to preemption. */ + } TX_FRAG_CNT2_b; + }; + + union + { + __IM uint32_t RX_FRAG_CNT2; /*!< (@ 0x00003518) Port 2 RX Continuation Count Register */ + + struct + { + __IM uint32_t RX_FRAG_CNT : 32; /*!< [31..0] Port n increments for every continuation mPacket received. */ + } RX_FRAG_CNT2_b; + }; + + union + { + __IM uint32_t RX_ASSY_OK_CNT2; /*!< (@ 0x0000351C) Port 2 RX Preempted Frame Success Count Register */ + + struct + { + __IM uint32_t RX_ASSY_OK_CNT : 32; /*!< [31..0] Port n increments when a preempted frame is successfully + * assembled. */ + } RX_ASSY_OK_CNT2_b; + }; + + union + { + __IM uint32_t RX_ASSY_ERR_CNT2; /*!< (@ 0x00003520) Port 2 RX Preempted Frame Incorrect Count Register */ + + struct + { + __IM uint32_t RX_ASSY_ERR_CNT : 16; /*!< [15..0] Port n increments when a preempted frame is incorrectly + * assembled. */ + uint32_t : 16; + } RX_ASSY_ERR_CNT2_b; + }; + + union + { + __IM uint32_t RX_SMD_ERR_CNT2; /*!< (@ 0x00003524) Port 2 RX SMD Frame Count Register */ + + struct + { + __IM uint32_t RX_SMD_ERR_CNT : 16; /*!< [15..0] Port n increments when a frame with an SMD-Cx is received + * and no assembly is in progress. */ + uint32_t : 16; + } RX_SMD_ERR_CNT2_b; + }; + + union + { + __IM uint32_t TX_VERIFY_OK_CNT2; /*!< (@ 0x00003528) Port 2 TX VERIFY Frame Count Register */ + + struct + { + __IM uint32_t TX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every VERIFY frame transmitted. */ + uint32_t : 24; + } TX_VERIFY_OK_CNT2_b; + }; + + union + { + __IM uint32_t TX_RESPONSE_OK_CNT2; /*!< (@ 0x0000352C) Port 2 TX RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t TX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every RESPONSE frame transmitted. */ + uint32_t : 24; + } TX_RESPONSE_OK_CNT2_b; + }; + + union + { + __IM uint32_t RX_VERIFY_OK_CNT2; /*!< (@ 0x00003530) Port 2 RX VERIFY Frame Count Register */ + + struct + { + __IM uint32_t RX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every valid VERIFY frame received. */ + uint32_t : 24; + } RX_VERIFY_OK_CNT2_b; + }; + + union + { + __IM uint32_t RX_RESPONSE_OK_CNT2; /*!< (@ 0x00003534) Port 2 RX RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t RX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every valid RESPONSE frame received. */ + uint32_t : 24; + } RX_RESPONSE_OK_CNT2_b; + }; + + union + { + __IM uint32_t RX_VERIFY_BAD_CNT2; /*!< (@ 0x00003538) Port 2 RX Error VERIFY Frame Count Register */ + + struct + { + __IM uint32_t RX_VERIFY_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored VERIFY frame received. */ + uint32_t : 24; + } RX_VERIFY_BAD_CNT2_b; + }; + + union + { + __IM uint32_t RX_RESPONSE_BAD_CNT2; /*!< (@ 0x0000353C) Port 2 RX Error RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t RX_RESPONSE_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored RESPONSE frame received. */ + uint32_t : 24; + } RX_RESPONSE_BAD_CNT2_b; + }; + + union + { + __IM uint32_t ODISC3; /*!< (@ 0x00003540) Port 3 Discarded Outgoing Frame Count Register */ + + struct + { + __IM uint32_t ODISC : 32; /*!< [31..0] Port n outgoing frames discarded due to output queue + * congestion. */ + } ODISC3_b; + }; + + union + { + __IM uint32_t IDISC_VLAN3; /*!< (@ 0x00003544) Port 3 Discarded Incoming VLAN Tagged Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching + * or missing VLAN ID while VLAN verification was enabled. */ + } IDISC_VLAN3_b; + }; + + union + { + __IM uint32_t IDISC_UNTAGGED3; /*!< (@ 0x00003548) Port 3 Discarded Incoming VLAN Untagged Frame + * Count Register */ + + struct + { + __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN + * tag. */ + } IDISC_UNTAGGED3_b; + }; + + union + { + __IM uint32_t IDISC_BLOCKED3; /*!< (@ 0x0000354C) Port 3 Discarded Incoming Blocked Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as + * the port is configured in blocking mode. */ + } IDISC_BLOCKED3_b; + }; + + union + { + __IM uint32_t IDISC_ANY3; /*!< (@ 0x00003550) Port 3 Discarded Any Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes + * IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED. */ + } IDISC_ANY3_b; + }; + __IM uint32_t RESERVED58[363]; + + union + { + __IOM uint32_t MMCTL_OUT_CT; /*!< (@ 0x00003B00) Cut-Through Register */ + + struct + { + __IOM uint32_t CT_OVR_ENA : 3; /*!< [2..0] Per-port bit mask to enable overriding the Cut-Through + * (CT) behavior of the output ports with CT_OVR. When set + * to 0, the frames are transmitted CT if the CT flag of the + * frame context is set. */ + uint32_t : 13; + __IOM uint32_t CT_OVR : 3; /*!< [18..16] 1 bit per-port value to set the Cut Through behavior + * of the output ports. When set to 0, all frames are sent + * as Store & Forward (SF) frames. When set to 1, frames with + * the CT flag set in the frame context are started as soon + * as the frame context information is available. */ + uint32_t : 13; + } MMCTL_OUT_CT_b; + }; + + union + { + __IOM uint32_t MMCTL_CTFL_P0_3_ENA; /*!< (@ 0x00003B04) Cut-Through Frame Length Enable Register */ + + struct + { + __IOM uint32_t CTFL_P0_ENA : 8; /*!< [7..0] Port 0 bit mask of n bits, where n is the number of queues + * per port indicating whether the CTFL is used for Cut-Through + * (CT) frames. When set to 1, a CT frame requires a CTFL + * entry to be written as a CT frame in the output memory. */ + __IOM uint32_t CTFL_P1_ENA : 8; /*!< [15..8] Port 1 bit mask of n bits, where n is the number of + * queues per port indicating whether the CTFL is used for + * Cut-Through (CT) frames. When set to 1, a CT frame requires + * a CTFL entry to be written as a CT frame in the output + * memory. */ + __IOM uint32_t CTFL_P2_ENA : 8; /*!< [23..16] Port 2 bit mask of n bits, where n is the number of + * queues per port indicating whether the CTFL is used for + * Cut-Through (CT) frames. When set to 1, a CT frame requires + * a CTFL entry to be written as a CT frame in the output + * memory. */ + uint32_t : 8; + } MMCTL_CTFL_P0_3_ENA_b; + }; + __IM uint32_t RESERVED59[6]; + + union + { + __IOM uint32_t MMCTL_YELLOW_BYTE_LENGTH_P[3]; /*!< (@ 0x00003B20) Port [0..2] Yellow Period Byte Length Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t YELLOW_LEN : 14; /*!< [15..2] Length in bytes of the YELLOW period for port n. Determines + * whether a frame can be transmitted before the YELLOW period + * expires. The value is programmed in increments of 4 bytes + * excluding the MAC overhead (IPG, Preamble and FCS if appended) + * of the frame. */ + __IOM uint32_t YLEN_EN : 1; /*!< [16..16] When set to 1, enables transmission when OUT_CT_ENA + * is low only if the frame length is less than YELLOW_LEN. + * If cleared, YELLOW_LEN is ignored and frames are always + * transmitted in SF mode when OUT_CT_ENA is 0. */ + uint32_t : 15; + } MMCTL_YELLOW_BYTE_LENGTH_P_b[3]; + }; + __IM uint32_t RESERVED60[5]; + + union + { + __IOM uint32_t MMCTL_POOL0_CTR; /*!< (@ 0x00003B40) Memory Pool Counter (n = 0 to 1) */ + + struct + { + __IOM uint32_t CELLS : 10; /*!< [9..0] Memory pool configuration for pool n. Configures, in + * cells, the size of each memory pool. */ + uint32_t : 6; + __IM uint32_t USED : 10; /*!< [25..16] Reports the current available number of used cells + * for this memory pool. The used number of free cells can + * be calculated as CELLS - USED. */ + uint32_t : 6; + } MMCTL_POOL0_CTR_b; + }; + + union + { + __IOM uint32_t MMCTL_POOL1_CTR; /*!< (@ 0x00003B44) Memory Pool Counter (n = 0 to 1) */ + + struct + { + __IOM uint32_t CELLS : 10; /*!< [9..0] Memory pool configuration for pool n. Configures, in + * cells, the size of each memory pool. */ + uint32_t : 6; + __IM uint32_t USED : 10; /*!< [25..16] Reports the current available number of used cells + * for this memory pool. The used number of free cells can + * be calculated as CELLS - USED. */ + uint32_t : 6; + } MMCTL_POOL1_CTR_b; + }; + __IM uint32_t RESERVED61[6]; + + union + { + __IOM uint32_t MMCTL_POOL_GLOBAL; /*!< (@ 0x00003B60) Memory Pool Configuration Register */ + + struct + { + __IOM uint32_t CELLS : 10; /*!< [9..0] Memory pool configuration for the global pool. Configures, + * in cells, the size of the global shared pool. */ + uint32_t : 6; + __IM uint32_t USED : 10; /*!< [25..16] Reports the current number of used cells for the global + * shared pool. The used number of free cells can be calculated + * as CELLS - USED. */ + uint32_t : 6; + } MMCTL_POOL_GLOBAL_b; + }; + + union + { + __IM uint32_t MMCTL_POOL_STATUS; /*!< (@ 0x00003B64) Memory Pool Status Register */ + + struct + { + __IM uint32_t QUEUE_FULL : 8; /*!< [7..0] Per-queue pool full indication. Indicates for each queue + * whether all the blocks in the corresponding pool and global + * pool are allocated. */ + uint32_t : 24; + } MMCTL_POOL_STATUS_b; + }; + + union + { + __IOM uint32_t MMCTL_POOL_QMAP; /*!< (@ 0x00003B68) Queue MAP Register */ + + struct + { + __IOM uint32_t Q0_MAP : 1; /*!< [0..0] Queue 0 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q0_ENA : 1; /*!< [3..3] Queue 0 Memory Pool Enabled */ + __IOM uint32_t Q1_MAP : 1; /*!< [4..4] Queue 1 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q1_ENA : 1; /*!< [7..7] Queue 1 Memory Pool Enabled */ + __IOM uint32_t Q2_MAP : 1; /*!< [8..8] Queue 2 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q2_ENA : 1; /*!< [11..11] Queue 2 Memory Pool Enabled */ + __IOM uint32_t Q3_MAP : 1; /*!< [12..12] Queue 3 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q3_ENA : 1; /*!< [15..15] Queue 3 Memory Pool Enabled */ + __IOM uint32_t Q4_MAP : 1; /*!< [16..16] Queue 4 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q4_ENA : 1; /*!< [19..19] Queue 4 Memory Pool Enabled */ + __IOM uint32_t Q5_MAP : 1; /*!< [20..20] Queue 5 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q5_ENA : 1; /*!< [23..23] Queue 5 Memory Pool Enabled */ + __IOM uint32_t Q6_MAP : 1; /*!< [24..24] Queue 6 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q6_ENA : 1; /*!< [27..27] Queue 6 Memory Pool Enabled */ + __IOM uint32_t Q7_MAP : 1; /*!< [28..28] Queue 7 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q7_ENA : 1; /*!< [31..31] Queue 7 Memory Pool Enabled */ + } MMCTL_POOL_QMAP_b; + }; + + union + { + __OM uint32_t MMCTL_QGATE; /*!< (@ 0x00003B6C) Queue Gate State Register */ + + struct + { + __OM uint32_t PORT_MASK : 4; /*!< [3..0] Per-port bit mask. When set to 1 for a port, the queue + * gate state is changed for that port as indicated by QUEUE_GATE. */ + uint32_t : 12; + __OM uint32_t QUEUE_GATE : 16; /*!< [31..16] 2-bit per queue indicating the action to be performed + * on each queue of the ports indicated by PORT_MASK. */ + } MMCTL_QGATE_b; + }; + + union + { + __OM uint32_t MMCTL_QTRIG; /*!< (@ 0x00003B70) Queue Trigger Register */ + + struct + { + __OM uint32_t PORT_MASK : 4; /*!< [3..0] Per-port bit mask. When set to 1 for a port, a frame + * is triggered from the closed queues indicated by QUEUE_TRIG. */ + uint32_t : 12; + __OM uint32_t QUEUE_TRIG : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame + * is to be transmitted from the ports indicated by PORT_MASK. + * When set to 1, a single frame is transmitted per indicated + * port in PORT_MASK among the queues indicated by QUEUE_TRIG. */ + uint32_t : 8; + } MMCTL_QTRIG_b; + }; + + union + { + __OM uint32_t MMCTL_QFLUSH; /*!< (@ 0x00003B74) Flush Event Select Register */ + + struct + { + __OM uint32_t PORT_MASK : 4; /*!< [3..0] Per-port bit mask. When set to 1 for a port, the queue + * flush status is changed for that port for the queues indicated + * in QUEUE_MASK. */ + uint32_t : 12; + __OM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1 bit per queue indicating for which queues of the + * ports indicated by PORT_MASK the flush state is changed + * as indicated in ACTION. */ + __OM uint32_t ACTION : 2; /*!< [25..24] Selects the flush state for the queues indicated by + * QUEUE_MASK in the ports indicated by PORT_MASK. Possible + * actions are: */ + uint32_t : 6; + } MMCTL_QFLUSH_b; + }; + + union + { + __IM uint32_t MMCTL_QCLOSED_STATUS_P0_3; /*!< (@ 0x00003B78) Queue Closed Status Register */ + + struct + { + __IM uint32_t P0_STATUS : 8; /*!< [7..0] Per-queue closed status of Port 0 (1-bit per queue). + * A 0 indicates that the queue is open (enabled), and a 1 + * indicates that the queue is closed (disabled). */ + __IM uint32_t P1_STATUS : 8; /*!< [15..8] Per-queue closed status of Port 1 (1-bit per queue). + * A 0 indicates that the queue is open (enabled), and a 1 + * indicates that the queue is closed (disabled). */ + __IM uint32_t P2_STATUS : 8; /*!< [23..16] Per-queue closed status of Port 2 (1-bit per queue). + * A 0 indicates that the queue is open (enabled), and a 1 + * indicates that the queue is closed (disabled). */ + uint32_t : 8; + } MMCTL_QCLOSED_STATUS_P0_3_b; + }; + __IM uint32_t RESERVED62; + + union + { + __IOM uint32_t MMCTL_1FRAME_MODE_P[3]; /*!< (@ 0x00003B80) Port [0..2] 1-Frame Mode Configuration Register */ + + struct + { + __IOM uint32_t Q_1FRAME_ENA : 8; /*!< [7..0] 1 bit per queue. Setting a bit to 1 enables the 1-frame + * mode for that queue for port n. In this mode, only one + * frame is allowed in the queue. If a new frame is received, + * the old frame is discarded. */ + uint32_t : 8; + __IOM uint32_t Q_BUF_ENA : 8; /*!< [23..16] 1 bit per queue. Setting a bit to 1 enables the buffer + * mode behavior for that queue for port n. This mode requires + * also that Q_1FRAME_ENA is set to 1. */ + uint32_t : 8; + } MMCTL_1FRAME_MODE_P_b[3]; + }; + __IM uint32_t RESERVED63[5]; + + union + { + __IM uint32_t MMCTL_P0_3_QUEUE_STATUS; /*!< (@ 0x00003BA0) Queue Status Indicator */ + + struct + { + __IM uint32_t P0_Q_STATUS : 8; /*!< [7..0] Port 0 Per-Queue Bit Indication */ + __IM uint32_t P1_Q_STATUS : 8; /*!< [15..8] Port 1 Per-Queue Bit Indication */ + __IM uint32_t P2_Q_STATUS : 8; /*!< [23..16] Port 2 Per-Queue Bit Indication */ + uint32_t : 8; + } MMCTL_P0_3_QUEUE_STATUS_b; + }; + __IM uint32_t RESERVED64; + + union + { + __IM uint32_t MMCTL_P0_3_FLUSH_STATUS; /*!< (@ 0x00003BA8) Queue Flush Status Indicator */ + + struct + { + __IM uint32_t P0_F_STATUS : 8; /*!< [7..0] Port 0 per-Queue Bit Indication on whether the queue + * is flushing frames (read 1) or not (read 0). */ + __IM uint32_t P1_F_STATUS : 8; /*!< [15..8] Port 1 per-Queue Bit Indication on whether the queue + * is flushing frames (read 1) or not (read 0). */ + __IM uint32_t P2_F_STATUS : 8; /*!< [23..16] Port 2 per-Queue Bit Indication on whether the queue + * is flushing frames (read 1) or not (read 0). */ + uint32_t : 8; + } MMCTL_P0_3_FLUSH_STATUS_b; + }; + __IM uint32_t RESERVED65; + + union + { + __IOM uint32_t MMCTL_DLY_QTRIGGER_CTRL; /*!< (@ 0x00003BB0) Delayed Queue Trigger Control Register */ + + struct + { + __IOM uint32_t DELAY_TIME : 30; /*!< [29..0] 30-bit time in nanoseconds indicates the time after + * the trigger request from the pattern matchers to generate + * the event. */ + __IOM uint32_t TIMER_SEL : 1; /*!< [30..30] Select the source timer to use for calculating the + * time. */ + uint32_t : 1; + } MMCTL_DLY_QTRIGGER_CTRL_b; + }; + + union + { + __IOM uint32_t MMCTL_PREEMPT_QUEUES; /*!< (@ 0x00003BB4) Preemptable Queues Configures Register */ + + struct + { + __IOM uint32_t PREEMPT_ENA : 8; /*!< [7..0] Per-queue enable bit to configure which queues are used + * for preemptable traffic. Set to 1 the corresponding bit + * to configure a queue to be preemptable. */ + __IOM uint32_t PREEMPT_ON_QCLOSE : 8; /*!< [15..8] Per-queue configuration bit to enable preempting a frame + * when the queue goes from OPEN to CLOSED. When the corresponding + * bit is set to 1 and the queue is configured as preemptable + * in PREEMPT_ENA, a queue close event causes the current + * frame to be preempted, if preemption is operational. */ + uint32_t : 16; + } MMCTL_PREEMPT_QUEUES_b; + }; + + union + { + __IOM uint32_t MMCTL_HOLD_CONTROL; /*!< (@ 0x00003BB8) Request Preemption Register */ + + struct + { + __IOM uint32_t Q_HOLD_REQ_FORCE : 3; /*!< [2..0] A per-port bit that forces a preempt request using MM_CTL.request + * (hold_req). When this bit is set to 1, it overrides other + * sources of hold request, including the TDMA controller. */ + uint32_t : 13; + __IOM uint32_t Q_HOLD_REQ_RELEASE : 3; /*!< [18..16] A per-port bit that forces a release of preemption + * request using MM_CTL.request (hold_req). When this bit + * is set to 1, it overrides other sources of hold request, + * including the TDMA controller and Q_HOLD_REQ_FORCE[2:0]. */ + uint32_t : 13; + } MMCTL_HOLD_CONTROL_b; + }; + + union + { + __IM uint32_t MMCTL_PREEMPT_STATUS; /*!< (@ 0x00003BBC) Preemption State Register */ + + struct + { + __IM uint32_t PREEMPT_STATE : 3; /*!< [2..0] A per-port bit that indicates if a port is in a preempted + * state. This is a real-time indication meant for debugging. */ + uint32_t : 13; + __IM uint32_t HOLD_REQ_STATE : 3; /*!< [18..16] A per-port bit that indicates if a port is preempted + * using MM_CTL.request (hold_req). This is a real-time indication + * meant for debugging. */ + uint32_t : 13; + } MMCTL_PREEMPT_STATUS_b; + }; + + union + { + __IOM uint32_t MMCTL_CQF_CTRL_P[4]; /*!< (@ 0x00003BC0) Port [0..3] Cyclic Queuing and Forwarding Control + * Register */ + + struct + { + __IOM uint32_t PRIO_ENABLE0 : 8; /*!< [7..0] A per-queue enable to select which ingress priorities + * are queued in the two CQF queues. */ + __IOM uint32_t QUEUE_SEL0 : 3; /*!< [10..8] Select which two physical queues are used for CQF. The + * queues used are QUEUE_SEL0 and QUEUE_SEL0 + 1. Frames are + * written into QUEUE_SEL0 when the gate control selected + * with GATE_SEL0 is 0, and into QUEUE_SEL0 + 1 when the gate + * control is 1. */ + __IOM uint32_t GATE_SEL0 : 3; /*!< [13..11] Select which gate control signal is used for selecting + * the output queue (these signals are the same as the ETHSW_TDMAOUT + * pins). */ + __IOM uint32_t USE_SOP0 : 1; /*!< [14..14] When set to 1, the CFQ queue is determined when the + * SOP is received at the frame writer in the memory controller. + * When set to 0, the queue is determined when the EOP is + * received at the frame writer. */ + __IOM uint32_t REF_SEL0 : 1; /*!< [15..15] Select whether the gate control signal used for the + * CQF group is based on the egress port when set to 0, or + * the ingress port when set to 1. */ + uint32_t : 16; + } MMCTL_CQF_CTRL_P_b[4]; + }; + __IM uint32_t RESERVED66[4]; + + union + { + __IM uint32_t MMCTL_P0_3_QCLOSED_NONEMPTY; /*!< (@ 0x00003BE0) Port Queue Status Register */ + + struct + { + __IM uint32_t P0_Q_STATUS : 8; /*!< [7..0] Port 0 per-queue bit indication on whether the queue + * transitioned from open to closed state while frames were + * still queued. */ + __IM uint32_t P1_Q_STATUS : 8; /*!< [15..8] Port 1 per-queue bit indication on whether the queue + * transitioned from open to closed state while frames were + * still queued. */ + __IM uint32_t P2_Q_STATUS : 8; /*!< [23..16] Port 2 per-queue bit indication on whether the queue + * transitioned from open to closed state while frames were + * still queued. */ + __IM uint32_t P3_Q_STATUS : 8; /*!< [31..24] Port 3 per-queue bit indication on whether the queue + * transitioned from open to closed state while frames were + * still queued. */ + } MMCTL_P0_3_QCLOSED_NONEMPTY_b; + }; + __IM uint32_t RESERVED67; + + union + { + __IOM uint32_t MMCTL_PREEMPT_EXTRA; /*!< (@ 0x00003BE8) Frame Preemption Extra Configuration Register */ + + struct + { + __IOM uint32_t MIN_PFRM_ADJ : 4; /*!< [3..0] Adjust the minimum mPacket length, in increments of 4 + * bytes. */ + __IOM uint32_t LAST_PFRM_ADJ : 4; /*!< [7..4] Adjust the preemptable threshold when reaching the end + * of the frame, in increments of 4 bytes. Incrementing this + * value increments the length of the last mPacket. */ + uint32_t : 24; + } MMCTL_PREEMPT_EXTRA_b; + }; + __IM uint32_t RESERVED68[5]; + + union + { + __IOM uint32_t DLR_CONTROL; /*!< (@ 0x00003C00) DLR Control Register */ + + struct + { + __IOM uint32_t ENABLE : 1; /*!< [0..0] Enable DLR extension module. When set, the DLR module + * becomes active. When DLR is enabled, the LOOP_FILTER_ENA + * must also be enabled for proper DLR operation. */ + __IOM uint32_t AUTOFLUSH : 1; /*!< [1..1] Enable automatic flushing of unicast entries in address + * table if ring reconfiguration occurs (see also DLR interrupt + * IRQ_flush_macaddr_ena in DLR_IRQ_CONTROL). */ + __IOM uint32_t LOOP_FILTER_ENA : 1; /*!< [2..2] Enable the loop filter function. When set to 1, the ingress + * loop filter is enabled. This can be enabled regardless + * of the DLR ENABLE state, allowing the loop filter function + * to operate when DLR is not used. */ + uint32_t : 1; + __IOM uint32_t IGNORE_INVTM : 1; /*!< [4..4] Enable ignore beacon frames with invalid timeout timer. + * When enabled (set to 1) frames with timeout timer value + * not within a range of 200 microseconds to 500 milliseconds + * are ignored and parameters are not locally stored or considered + * for state transitions. The invalid timeout timer value + * is always stored within the DLR_INV_TMOUT register irrespective + * of the value of this bit. Ignored frames are forwarded + * normally. */ + uint32_t : 3; + __IOM uint32_t US_TIME : 12; /*!< [19..8] Number of clock cycles required for 1 microsecond for + * the switch operating clock. This LSI operates at 200 MHz, + * therefore this register must be set to 0xC8. The value + * after reset must be changed. */ + uint32_t : 12; + } DLR_CONTROL_b; + }; + + union + { + __IM uint32_t DLR_STATUS; /*!< (@ 0x00003C04) DLR Status Register */ + + struct + { + __IM uint32_t LastBcnRcvPort : 2; /*!< [1..0] Last Beacon Receive Port */ + uint32_t : 6; + __IM uint32_t NODE_STATE : 8; /*!< [15..8] Local Node Current State */ + __IM uint32_t LINK_STATUS : 2; /*!< [17..16] Link Status */ + uint32_t : 6; + __IM uint32_t TOPOLOGY : 8; /*!< [31..24] Current Network Topology */ + } DLR_STATUS_b; + }; + + union + { + __IOM uint32_t DLR_ETH_TYP; /*!< (@ 0x00003C08) DLR Ethernet Type Register */ + + struct + { + __IOM uint32_t DLR_ETH_TYP : 16; /*!< [15..0] Ethernet type to compare for DLR frame detection (initial + * value is 0x80E1) */ + uint32_t : 16; + } DLR_ETH_TYP_b; + }; + + union + { + __IOM uint32_t DLR_IRQ_CONTROL; /*!< (@ 0x00003C0C) DLR Interrupt Control Register */ + + struct + { + __IOM uint32_t IRQ_state_chng_ena : 1; /*!< [0..0] Enable Interrupt for State Change */ + __IOM uint32_t IRQ_flush_macaddr_ena : 1; /*!< [1..1] Enable Flush Local MAC Address Table Interrupt. */ + __IOM uint32_t IRQ_stop_nbchk0_ena : 1; /*!< [2..2] Enable Stop Request Neighbor Check Timeout Timer Interrupt + * for Port 0. */ + __IOM uint32_t IRQ_stop_nbchk1_ena : 1; /*!< [3..3] Enable Stop Request Neighbor Check Timeout Timer Interrupt + * for Port 1. */ + __IOM uint32_t IRQ_bec_tmr0_exp_ena : 1; /*!< [4..4] IRQ_bec_tmr0_exp_ena */ + __IOM uint32_t IRQ_bec_tmr1_exp_ena : 1; /*!< [5..5] Enable Interrupt on Beacon Timeout Timer Expire for Port + * 1. */ + __IOM uint32_t IRQ_supr_chng_ena : 1; /*!< [6..6] Enable Interrupt on Ring Supervisor Change. */ + __IOM uint32_t IRQ_link_chng0_ena : 1; /*!< [7..7] Enable Link Status Change Interrupt Event for Port 0. */ + __IOM uint32_t IRQ_link_chng1_ena : 1; /*!< [8..8] Enable Link Status Change Interrupt Event for Port 1. */ + __IOM uint32_t IRQ_sup_ignord_ena : 1; /*!< [9..9] Enable interrupt on beacon frame detection from a supervisor + * with lower precedence than the current ring supervisor + * or lower numeric value for MAC address when precedence + * is same. */ + __IOM uint32_t IRQ_ip_addr_chng_ena : 1; /*!< [10..10] Enable interrupt on IP address change detection within + * beacon frame from ring supervisor. */ + __IOM uint32_t IRQ_invalid_tmr_ena : 1; /*!< [11..11] Enable interrupt on invalid range for beacon timeout + * timer value detection. */ + __IOM uint32_t IRQ_bec_rcv0_ena : 1; /*!< [12..12] Enable interrupt on beacon frame detection on port + * 0. */ + __IOM uint32_t IRQ_bec_rcv1_ena : 1; /*!< [13..13] Enable interrupt on beacon frame detection on port + * 1. */ + __IOM uint32_t IRQ_frm_dscrd0 : 1; /*!< [14..14] Enable interrupt on frame discard due to source address + * match with the local address on port 0. */ + __IOM uint32_t IRQ_frm_dscrd1 : 1; /*!< [15..15] Enable Interrupt on Frame discard due to source address + * match with the local address on port 1. */ + uint32_t : 13; + __IOM uint32_t low_int_en : 1; /*!< [29..29] Enable active-low interrupt. Asserted to use active-low + * interrupt signal instead of active-high interrupt signal. */ + __OM uint32_t atomic_OR : 1; /*!< [30..30] When set during a register-write, the enable bits are + * ORed into the current setting of the register. By writing + * this bit at the same time, only the target bit can be set + * to 1. */ + __OM uint32_t atomic_AND : 1; /*!< [31..31] When set during a register-write, the enable bits are + * ANDed with the current setting of the register. By writing + * this bit at the same time, only the target bit can be set + * to 0. */ + } DLR_IRQ_CONTROL_b; + }; + + union + { + __IOM uint32_t DLR_IRQ_STAT_ACK; /*!< (@ 0x00003C10) DLR Interrupt Status/ACK Register */ + + struct + { + __IOM uint32_t state_chng_IRQ_pending : 1; /*!< [0..0] Latched State Change Event */ + __IOM uint32_t flush_IRQ_pending : 1; /*!< [1..1] Latched Flush Event for MAC Address Learning Table */ + __IOM uint32_t nbchk0_IRQ_pending : 1; /*!< [2..2] Stop Request Event for Neighbor Check Timeout Timer for + * Port 0 */ + __IOM uint32_t nbchk1_IRQ_pending : 1; /*!< [3..3] Stop Request Event for Neighbor Check Timeout Timer for + * Port 1 */ + __IOM uint32_t bec_tmr0_IRQ_pending : 1; /*!< [4..4] Beacon Timeout Timer Expire Event for Port 0 */ + __IOM uint32_t bec_tmr1_IRQ_pending : 1; /*!< [5..5] Beacon Timeout Timer Expire Event for Port 1 */ + __IOM uint32_t supr_chng_IRQ_pending : 1; /*!< [6..6] Latched Supervisor Change Event */ + __IOM uint32_t Link0_IRQ_pending : 1; /*!< [7..7] Latched Link Status Change Event for Port 0 */ + __IOM uint32_t Link1_IRQ_pending : 1; /*!< [8..8] Latched Link Status Change Event for Port 1 */ + __IOM uint32_t sup_ignord_IRQ_pending : 1; /*!< [9..9] Latched Event for Beacon Frame Detection from Ignored + * Supervisor */ + __IOM uint32_t ip_chng_IRQ_pending : 1; /*!< [10..10] Latched IP Address Change Event */ + __IOM uint32_t invalid_tmr_IRQ_pending : 1; /*!< [11..11] Latched Event on Invalid Beacon Timeout Timer Value + * Detection Within Beacon Frame on Port 0 or Port 1 */ + __IOM uint32_t bec_rcv0_IRQ_pending : 1; /*!< [12..12] Latched Event on Beacon Frame Detection on Port 0 */ + __IOM uint32_t bec_rcv1_IRQ_pending : 1; /*!< [13..13] Latched Event on Beacon Frame Detection on Port 1 */ + __IOM uint32_t frm_dscrd0_IRQ_pending : 1; /*!< [14..14] Latched Event on Frame Discard Due to Source Address + * Match with the Local Address on Port 0 (Loop Filter) */ + __IOM uint32_t frm_dscrd1_IRQ_pending : 1; /*!< [15..15] Latched Event on Frame Discard Due to Source Address + * Match with the Local Address on Port 1 (Loop Filter) */ + uint32_t : 16; + } DLR_IRQ_STAT_ACK_b; + }; + + union + { + __IOM uint32_t DLR_LOC_MAClo; /*!< (@ 0x00003C14) DLR Local MAC Address Low Register */ + + struct + { + __IOM uint32_t LOC_MAC : 32; /*!< [31..0] First 4 octets of the Local MAC address for loop filter */ + } DLR_LOC_MAClo_b; + }; + + union + { + __IOM uint32_t DLR_LOC_MAChi; /*!< (@ 0x00003C18) DLR Local MAC Address High Register */ + + struct + { + __IOM uint32_t LOC_MAC : 16; /*!< [15..0] Last 2 octets of local MAC address for loop filter */ + uint32_t : 16; + } DLR_LOC_MAChi_b; + }; + __IM uint32_t RESERVED69; + + union + { + __IM uint32_t DLR_SUPR_MAClo; /*!< (@ 0x00003C20) DLR Supervisor MAC Address Low Register */ + + struct + { + __IM uint32_t SUPR_MAC : 32; /*!< [31..0] First 4 octets of the active ring supervisor of the + * MAC address extracted from the Source Address field of + * the beacon frame. */ + } DLR_SUPR_MAClo_b; + }; + + union + { + __IM uint32_t DLR_SUPR_MAChi; /*!< (@ 0x00003C24) DLR Supervisor MAC Address High Register */ + + struct + { + __IM uint32_t SUPR_MAC : 16; /*!< [15..0] Last 2 octets of the active ring supervisor of the MAC + * address extracted from the Source Address field of the + * beacon frame. */ + __IM uint32_t PRECE : 8; /*!< [23..16] Precedence value of the ring supervisor extracted from + * the Supervisor precedence field of the beacon frame. */ + uint32_t : 8; + } DLR_SUPR_MAChi_b; + }; + + union + { + __IM uint32_t DLR_STATE_VLAN; /*!< (@ 0x00003C28) DLR Ring Status/VLAN Register */ + + struct + { + __IM uint32_t RINGSTAT : 8; /*!< [7..0] DLR ring state extracted from the Ring State field of + * the beacon frame. */ + __IM uint32_t VLANVALID : 1; /*!< [8..8] VLAN Valid */ + uint32_t : 7; + __IM uint32_t VLANINFO : 16; /*!< [31..16] IEEE 802.1Q VLAN Tag control field extracted from the + * VLAN info field of the beacon frame. */ + } DLR_STATE_VLAN_b; + }; + + union + { + __IM uint32_t DLR_BEC_TMOUT; /*!< (@ 0x00003C2C) DLR Beacon Timeout Register */ + + struct + { + __IM uint32_t BEC_TMOUT : 32; /*!< [31..0] Beacon timeout timer value extracted from the Beacon + * Timeout in microseconds field of the beacon frame. */ + } DLR_BEC_TMOUT_b; + }; + + union + { + __IM uint32_t DLR_BEC_INTRVL; /*!< (@ 0x00003C30) DLR Beacon Interval Register */ + + struct + { + __IM uint32_t BEC_INTRVL : 32; /*!< [31..0] Beacon interval extracted from the Beacon Interval field + * of the beacon frame */ + } DLR_BEC_INTRVL_b; + }; + + union + { + __IM uint32_t DLR_SUPR_IPADR; /*!< (@ 0x00003C34) DLR Supervisor IP Address Register */ + + struct + { + __IM uint32_t SUPR_IPADR : 32; /*!< [31..0] IP address of the ring supervisor extracted from the + * Source IP address field of the beacon frame. A value of + * 0x0 can be received when supervisor has no IP address. */ + } DLR_SUPR_IPADR_b; + }; + + union + { + __IM uint32_t DLR_ETH_STYP_VER; /*!< (@ 0x00003C38) DLR Sub Type/Protocol Version Register */ + + struct + { + __IM uint32_t SUBTYPE : 8; /*!< [7..0] DLR Ring Ether Sub Type extracted from the Ring Sub Type + * field of the beacon frame. */ + __IM uint32_t PROTVER : 8; /*!< [15..8] DLR Ring Protocol Version extracted from the Ring Protocol + * Version field of the beacon frame. */ + __IM uint32_t SPORT : 8; /*!< [23..16] Source port extracted from the Source Port field of + * the beacon frame. */ + uint32_t : 8; + } DLR_ETH_STYP_VER_b; + }; + + union + { + __IM uint32_t DLR_INV_TMOUT; /*!< (@ 0x00003C3C) DLR Beacon Timeout Timer Register */ + + struct + { + __IM uint32_t INV_TMOUT : 32; /*!< [31..0] Last out of range Beacon timeout timer value extracted + * from beacon frame on any of the port. */ + } DLR_INV_TMOUT_b; + }; + + union + { + __IM uint32_t DLR_SEQ_ID; /*!< (@ 0x00003C40) DLR Sequence ID Register */ + + struct + { + __IM uint32_t SEQ_ID : 32; /*!< [31..0] Sequence ID of the last beacon frame extracted from + * the Sequence ID field of the beacon frame on port 0 or + * port 1. Sequence ID of the ignored frames is not stored. */ + } DLR_SEQ_ID_b; + }; + __IM uint32_t RESERVED70[5]; + + union + { + __IOM uint32_t DLR_DSTlo; /*!< (@ 0x00003C58) DLR Beacon Destination Address Low Register */ + + struct + { + __IOM uint32_t DLR_DST : 32; /*!< [31..0] First 4 octets of the beacon frame destination multicast + * address (01-21-6C-00-00-01). */ + } DLR_DSTlo_b; + }; + + union + { + __IOM uint32_t DLR_DSThi; /*!< (@ 0x00003C5C) DLR Beacon Destination Address High Register */ + + struct + { + __IOM uint32_t DLR_DST : 16; /*!< [15..0] Last 2 octets of the beacon frame destination multicast + * address (01-21-6C-00-00-01). */ + uint32_t : 16; + } DLR_DSThi_b; + }; + + union + { + __IM uint32_t DLR_RX_STAT0; /*!< (@ 0x00003C60) DLR Received Frame Statistic Register 0 */ + + struct + { + __IM uint32_t RX_STAT0 : 32; /*!< [31..0] Number of Beacon Frames Received on Port 0 */ + } DLR_RX_STAT0_b; + }; + + union + { + __IM uint32_t DLR_RX_ERR_STAT0; /*!< (@ 0x00003C64) DLR Received Frame Error Statistic Register 0 */ + + struct + { + __IM uint32_t RX_ERR_STAT0 : 32; /*!< [31..0] Number of Beacon Frames Received with CRC Error on Port + * 0 */ + } DLR_RX_ERR_STAT0_b; + }; + __IM uint32_t RESERVED71; + + union + { + __IOM uint32_t DLR_RX_LF_STAT0; /*!< (@ 0x00003C6C) DLR Received Frame Loop Filter Statistic Register + * 0 */ + + struct + { + __IOM uint32_t RX_LF_STAT0 : 8; /*!< [7..0] Number of discarded frames in port 0 due to loop filtering + * when LOOP_FILTER_ENA is set to 1. Saturates at 255. */ + uint32_t : 24; + } DLR_RX_LF_STAT0_b; + }; + + union + { + __IM uint32_t DLR_RX_STAT1; /*!< (@ 0x00003C70) DLR Received Frame Statistic Register 1 */ + + struct + { + __IM uint32_t RX_STAT1 : 32; /*!< [31..0] Number of Beacon Frames Received on Port 1 */ + } DLR_RX_STAT1_b; + }; + + union + { + __IM uint32_t DLR_RX_ERR_STAT1; /*!< (@ 0x00003C74) DLR Received Frame Error Statistic Register 1 */ + + struct + { + __IM uint32_t RX_ERR_STAT1 : 32; /*!< [31..0] Number of Beacon Frames Received with CRC Error on Port + * 1 */ + } DLR_RX_ERR_STAT1_b; + }; + __IM uint32_t RESERVED72; + + union + { + __IOM uint32_t DLR_RX_LF_STAT1; /*!< (@ 0x00003C7C) DLR Received Frame Loop Filter Statistic Register + * 1 */ + + struct + { + __IOM uint32_t RX_LF_STAT1 : 8; /*!< [7..0] Number of discarded frames in port 1 due to loop filtering + * when LOOP_FILTER_ENA is set to 1. Saturates at 255. */ + uint32_t : 24; + } DLR_RX_LF_STAT1_b; + }; + __IM uint32_t RESERVED73[32]; + + union + { + __IOM uint32_t PRP_CONFIG; /*!< (@ 0x00003D00) PRP Configuration Register */ + + struct + { + __IOM uint32_t PRP_ENA : 1; /*!< [0..0] Enable PRP Operation */ + __IOM uint32_t RX_DUP_ACCEPT : 1; /*!< [1..1] Enable Duplicate Accept Mode of Operation at Receive */ + __IOM uint32_t RX_REMOVE_RCT : 1; /*!< [2..2] Allow PRP Port RX to Remove the RCT */ + __IOM uint32_t TX_RCT_MODE : 2; /*!< [4..3] Control Appending the RCT to Transmitted Frames on the + * Redundant Ports */ + __IOM uint32_t TX_RCT_BROADCAST : 1; /*!< [5..5] Should be 1 normally. */ + __IOM uint32_t TX_RCT_MULTICAST : 1; /*!< [6..6] Should be 1 normally. */ + __IOM uint32_t TX_RCT_UNKNOWN : 1; /*!< [7..7] Should be 1 normally. */ + __IOM uint32_t TX_RCT_1588 : 1; /*!< [8..8] Setting this bit affects IEEE 1588 frames that are forwarded + * through the switch (for example, when used as RedBox) to + * both PRP_GROUP ports. Locally generated IEEE 1588 frames + * (peer-delay request/response) are not affected by this + * setting. */ + __IOM uint32_t RCT_LEN_CHK_DIS : 1; /*!< [9..9] When set to 1, disables the RCT length field checking + * against the actual frame length. */ + uint32_t : 6; + __IOM uint32_t PRP_AGE_ENA : 1; /*!< [16..16] Enable History Memory Aging Timer */ + uint32_t : 15; + } PRP_CONFIG_b; + }; + + union + { + __IOM uint32_t PRP_GROUP; /*!< (@ 0x00003D04) PRP Port Group Register */ + + struct + { + __IOM uint32_t PRP_GROUP : 3; /*!< [2..0] Defines which two ports should be treated as redundant + * ports for PRP. */ + uint32_t : 13; + __IOM uint32_t LANB_MASK : 3; /*!< [18..16] Defines which of the ports is considered the LAN B + * port. */ + uint32_t : 13; + } PRP_GROUP_b; + }; + + union + { + __IOM uint32_t PRP_SUFFIX; /*!< (@ 0x00003D08) PRP RCT Suffix */ + + struct + { + __IOM uint32_t PRP_SUFFIX : 16; /*!< [15..0] The Redundancy Control Trailer (RCT) suffix (initial + * value is 0x88FB) */ + uint32_t : 16; + } PRP_SUFFIX_b; + }; + + union + { + __IOM uint32_t PRP_LANID; /*!< (@ 0x00003D0C) PRP LAN Identifier */ + + struct + { + __IOM uint32_t LANAID : 4; /*!< [3..0] LAN A Identifier */ + __IOM uint32_t LANBID : 4; /*!< [7..4] LAN B Identifier */ + uint32_t : 24; + } PRP_LANID_b; + }; + + union + { + __IOM uint32_t DUP_W; /*!< (@ 0x00003D10) PRP Max Duplicate Detection Window Size */ + + struct + { + __IOM uint32_t DUP_W : 8; /*!< [7..0] Maximum Duplicate Detect Window Size */ + uint32_t : 24; + } DUP_W_b; + }; + + union + { + __IOM uint32_t PRP_AGETIME; /*!< (@ 0x00003D14) PRP Aging Time Define Register */ + + struct + { + __IOM uint32_t PRP_AGETIME : 24; /*!< [23..0] Timeout in steps of 32 switch operating clock cycles + * to control aging of duplicate history data. */ + uint32_t : 8; + } PRP_AGETIME_b; + }; + + union + { + __IOM uint32_t PRP_IRQ_CONTROL; /*!< (@ 0x00003D18) PRP Interrupt Control Register */ + + struct + { + __IOM uint32_t MEMTOOLATE : 1; /*!< [0..0] Enable Interrupt for Memory Error Indications. */ + __IOM uint32_t WRONGLAN : 1; /*!< [1..1] Enable interrupt for frames received at a redundant port + * with an invalid LAN identifier in its redundancy trailer. */ + __IOM uint32_t OUTOFSEQ : 1; /*!< [2..2] Enable interrupt for frames received and accepted but + * have an unexpected sequence number. */ + __IOM uint32_t SEQMISSING : 1; /*!< [3..3] Enable interrupt for frames received and accepted that + * caused the history to skip a sequence number that was never + * received (for example, a missing sequence number is being + * ignored and is now treated as a candidate for dropping). */ + uint32_t : 28; + } PRP_IRQ_CONTROL_b; + }; + + union + { + __IOM uint32_t PRP_IRQ_STAT_ACK; /*!< (@ 0x00003D1C) PRP Interrupt Status/ACK Register */ + + struct + { + __IOM uint32_t MEMTOOLATE : 1; /*!< [0..0] Interrupt Pending Indication */ + __IOM uint32_t WRONGLAN : 1; /*!< [1..1] This bit functions the same as MEMTOOLATE bit. */ + __IOM uint32_t OUTOFSEQ : 1; /*!< [2..2] This bit functions the same as MEMTOOLATE bit. */ + __IOM uint32_t SEQMISSING : 1; /*!< [3..3] This bit functions the same as MEMTOOLATE bit. */ + uint32_t : 28; + } PRP_IRQ_STAT_ACK_b; + }; + + union + { + __IOM uint32_t RM_ADDR_CTRL; /*!< (@ 0x00003D20) PRP History Memory Transactions Control Register */ + + struct + { + __IOM uint32_t address : 12; /*!< [11..0] Memory Address for Read and Write Transactions */ + uint32_t : 10; + __IOM uint32_t CLEAR_DYNAMIC : 1; /*!< [22..22] When set to 1, scan the complete table for valid dynamic + * history entries and deletes them (writes entry with all + * 0s). */ + __IOM uint32_t CLEAR_MEMORY : 1; /*!< [23..23] When set to 1, write all memory locations with 0. */ + uint32_t : 1; + __IOM uint32_t WRITE : 1; /*!< [25..25] When set to 1, perform a Single Write Transaction. */ + __IOM uint32_t READ : 1; /*!< [26..26] When set to 1, perform Single Read Transaction. */ + uint32_t : 2; + __IOM uint32_t CLEAR : 1; /*!< [29..29] When set to 1, write all 0s to the entry selected by + * the given address. */ + uint32_t : 1; + __IM uint32_t BUSY : 1; /*!< [31..31] Transaction Busy Indication */ + } RM_ADDR_CTRL_b; + }; + + union + { + __IOM uint32_t RM_DATA; /*!< (@ 0x00003D24) PRP Memory Data Register */ + + struct + { + __IOM uint32_t RM_DATA : 32; /*!< [31..0] Memory data register for read/write transactions controlled + * by RM_ADDR_CTRL. */ + } RM_DATA_b; + }; + + union + { + __IOM uint32_t RM_DATA_HI; /*!< (@ 0x00003D28) PRP Memory Data Higher Register */ + + struct + { + __IOM uint32_t RM_DATA_HI : 32; /*!< [31..0] A Second Data Register */ + } RM_DATA_HI_b; + }; + + union + { + __IM uint32_t RM_STATUS; /*!< (@ 0x00003D2C) PRP Memory Controller Status Indication */ + + struct + { + __IM uint32_t ageaddress : 12; /*!< [11..0] Address of an entry which the aging process inspects + * when the aging timer expires next time. */ + uint32_t : 20; + } RM_STATUS_b; + }; + + union + { + __IOM uint32_t TxSeqTooLate; /*!< (@ 0x00003D30) PRP Frame Transmission Retrieval of Failed Sequence */ + + struct + { + __IOM uint32_t TxSeqTooLate : 4; /*!< [3..0] Retrieval of a Sequence Number Failed */ + uint32_t : 28; + } TxSeqTooLate_b; + }; + + union + { + __IM uint32_t CntErrWrongLanA; /*!< (@ 0x00003D34) PRP Wrong ID LAN-A Count Register */ + + struct + { + __IM uint32_t CntErrWrongLanA : 32; /*!< [31..0] Valid frames received on LAN A which have an RCT (valid + * length + suffix) but LAN ID is not matching LAN A. */ + } CntErrWrongLanA_b; + }; + + union + { + __IM uint32_t CntErrWrongLanB; /*!< (@ 0x00003D38) PRP Wrong ID LAN-B Count Register */ + + struct + { + __IM uint32_t CntErrWrongLanB : 32; /*!< [31..0] Valid frames received on LAN B which have an RCT (valid + * length + suffix) but LAN ID is not matching LAN B. */ + } CntErrWrongLanB_b; + }; + + union + { + __IM uint32_t CntDupLanA; /*!< (@ 0x00003D3C) PRP Duplicate LAN-A Count Register */ + + struct + { + __IM uint32_t CntDupLanA : 32; /*!< [31..0] Valid frames received on LAN A that were dropped by + * duplicate detection. */ + } CntDupLanA_b; + }; + + union + { + __IM uint32_t CntDupLanB; /*!< (@ 0x00003D40) PRP Duplicate LAN-B Count Register */ + + struct + { + __IM uint32_t CntDupLanB : 32; /*!< [31..0] Valid frames received on LAN B that were dropped by + * duplicate detection. */ + } CntDupLanB_b; + }; + + union + { + __IM uint32_t CntOutOfSeqLowA; /*!< (@ 0x00003D44) PRP Sequence Error Low LAN-A Count Register */ + + struct + { + __IM uint32_t CntOutOfSeqLowA : 32; /*!< [31..0] Valid and accepted frames received on LAN A with a sequence + * number less than last window (DUP_W). */ + } CntOutOfSeqLowA_b; + }; + + union + { + __IM uint32_t CntOutOfSeqLowB; /*!< (@ 0x00003D48) PRP Sequence Error Low LAN-B Count Register */ + + struct + { + __IM uint32_t CntOutOfSeqLowB : 32; /*!< [31..0] Valid and accepted frames received on LAN B with a sequence + * number less than last window (DUP_W). */ + } CntOutOfSeqLowB_b; + }; + + union + { + __IM uint32_t CntOutOfSeqA; /*!< (@ 0x00003D4C) PRP Sequence Error LAN-A Count Register */ + + struct + { + __IM uint32_t CntOutOfSeqA : 32; /*!< [31..0] Valid and accepted frames received on LAN A with an + * unexpected sequence number. */ + } CntOutOfSeqA_b; + }; + + union + { + __IM uint32_t CntOutOfSeqB; /*!< (@ 0x00003D50) PRP Sequence Error LAN-B Count Register */ + + struct + { + __IM uint32_t CntOutOfSeqB : 32; /*!< [31..0] Valid and accepted frames received on LAN B with an + * unexpected sequence number. */ + } CntOutOfSeqB_b; + }; + + union + { + __IM uint32_t CntAcceptA; /*!< (@ 0x00003D54) PRP Valid Frame LAN-A Count Register */ + + struct + { + __IM uint32_t CntAcceptA : 32; /*!< [31..0] Valid frames received on LAN A which had a valid sequence + * number in the expected range. */ + } CntAcceptA_b; + }; + + union + { + __IM uint32_t CntAcceptB; /*!< (@ 0x00003D58) PRP Valid Frame LAN-B Count Register */ + + struct + { + __IM uint32_t CntAcceptB : 32; /*!< [31..0] Valid frames received on LAN B which had a valid sequence + * number in the expected range. */ + } CntAcceptB_b; + }; + + union + { + __IM uint32_t CntMissing; /*!< (@ 0x00003D5C) PRP Drop History Adjustment Count */ + + struct + { + __IM uint32_t CntMissing : 32; /*!< [31..0] Indicates adjustment of the drop history as a frame + * was received with a sequence number of expected + history + + 1. This occurs if the same frame was dropped in both + + LAN segments (one sequence number is missing) and the history + + is now extended beyond that sequence number (causing it + + to be treated as drop allowed). */ + } CntMissing_b; + }; + __IM uint32_t RESERVED74[40]; + + union + { + __IOM uint32_t HUB_CONFIG; /*!< (@ 0x00003E00) HUB Configuration Register */ + + struct + { + __IOM uint32_t HUB_ENA : 1; /*!< [0..0] Enable Integrated HUB Operation */ + __IOM uint32_t RETRANSMIT_ENA : 1; /*!< [1..1] Enable Hub Retransmit Capability */ + __IOM uint32_t TRIGGER_MODE : 1; /*!< [2..2] Enable Single Frame Trigger Mode */ + __IOM uint32_t HUB_ISOLATE : 1; /*!< [3..3] Isolate all hub ports from the other ports of the switch + * and allow communication with management port only. It is + * then up to the application of the management port to implement + * some bridging functionality to other ports as required. */ + __IOM uint32_t TIMER_SEL : 1; /*!< [4..4] Select the timer to use for timed triggers */ + uint32_t : 1; + __IOM uint32_t IPG_WAIT : 3; /*!< [8..6] IPG_WAIT */ + __IOM uint32_t CRS_GEN : 1; /*!< [9..9] CRS_GEN */ + __IOM uint32_t PRMB_GEN_DIS : 1; /*!< [10..10] PRMB_GEN_DIS */ + __IOM uint32_t JAM_WAIT_IDLE : 1; /*!< [11..11] JAM_WAIT_IDLE */ + uint32_t : 20; + } HUB_CONFIG_b; + }; + + union + { + __IOM uint32_t HUB_GROUP; /*!< (@ 0x00003E04) HUB Port Group Register */ + + struct + { + __IOM uint32_t HUB_GROUP : 3; /*!< [2..0] Define all ports that should be combined to a Hub Group. */ + uint32_t : 29; + } HUB_GROUP_b; + }; + + union + { + __IOM uint32_t HUB_DEFPORT; /*!< (@ 0x00003E08) HUB Default Port Selection Register */ + + struct + { + __IOM uint32_t HUB_DEFPORT : 3; /*!< [2..0] The default port within the Hub Group where all traffic + * from a port outside the group is forwarded to port (bit + * 0 = port 0, bit 1 = port 1, and bit 2 = port 2). If a frame + * should be forwarded to any of the hub ports, the frame + * is sent to this port only. The copy function of the hub + * copies it to all PHY interfaces of the group eventually. */ + uint32_t : 29; + } HUB_DEFPORT_b; + }; + + union + { + __IOM uint32_t HUB_TRIGGER_IMMEDIATE; /*!< (@ 0x00003E0C) HUB Transmission Trigger Immediate Register */ + + struct + { + __IOM uint32_t HUB_TRIGGER_IMMEDIATE : 3; /*!< [2..0] Trigger immediate transmission of a single frame from + * given port within the hub group (bit 0 = port 0, bit 1 + * = port 1, and bit 2 = port 2). */ + uint32_t : 29; + } HUB_TRIGGER_IMMEDIATE_b; + }; + + union + { + __IOM uint32_t HUB_TRIGGER_AT; /*!< (@ 0x00003E10) HUB Transmission Trigger At Register */ + + struct + { + __IOM uint32_t HUB_TRIGGER_AT : 3; /*!< [2..0] Trigger Transmission of a Single Frame at a Specific + * Time (bit 0 = port 0, bit 1 = port 1, and bit 2 = port + * 2). */ + uint32_t : 29; + } HUB_TRIGGER_AT_b; + }; + + union + { + __IOM uint32_t HUB_TTIME; /*!< (@ 0x00003E14) HUB Transmission Time Define Register */ + + struct + { + __IOM uint32_t HUB_TTIME : 32; /*!< [31..0] Define the Time Value when a Trigger Should Occur */ + } HUB_TTIME_b; + }; + + union + { + __IOM uint32_t HUB_IRQ_CONTROL; /*!< (@ 0x00003E18) HUB Interrupt Control Register */ + + struct + { + __IOM uint32_t RX_TRIGGER : 3; /*!< [2..0] Enable Interrupt on Receive Pattern Match Trigger Function */ + __IOM uint32_t CHANGE_DET : 1; /*!< [3..3] Enable interrupt for hub TX state machine port state + * change request detection */ + __IOM uint32_t TRIGGER_IMMEDIATE : 1; /*!< [4..4] Enable interrupt when hub transmit started after writing + * the HUB_TRIGGER_IMMEDIATE register */ + __IOM uint32_t TRIGGER_TIMER : 1; /*!< [5..5] Enable interrupt when hub transmit started after writing + * the HUB_TRIGGER_TIME register and the timeout value is + * reached (register HUB_TTIME). */ + uint32_t : 26; + } HUB_IRQ_CONTROL_b; + }; + + union + { + __IOM uint32_t HUB_IRQ_STAT_ACK; /*!< (@ 0x00003E1C) HUB Interrupt Status/ACK Register */ + + struct + { + __IOM uint32_t RX_TRIGGER : 3; /*!< [2..0] Interrupt Pending Indication */ + __IOM uint32_t CHANGE_DET : 1; /*!< [3..3] This bit functions the same as RX_TRIGGER bit. */ + __IOM uint32_t TRIGGER_IMMEDIATE : 1; /*!< [4..4] This bit functions the same as RX_TRIGGER bit. */ + __IOM uint32_t TRIGGER_TIMER : 1; /*!< [5..5] This bit functions the same as RX_TRIGGER bit. */ + uint32_t : 26; + } HUB_IRQ_STAT_ACK_b; + }; + + union + { + __IM uint32_t HUB_STATUS; /*!< (@ 0x00003E20) HUB Status Register */ + + struct + { + __IM uint32_t PORTS_ACTIVE : 3; /*!< [2..0] When this bit is 1, it shows the currently active ports + * of the Hub group which are allowed for transmit. */ + uint32_t : 6; + __IM uint32_t TX_ACTIVE : 1; /*!< [9..9] When this bit is 1, the hub global transmit state machine + * has successfully entered Hub mode and is now controlling + * the hub group. */ + __IM uint32_t TX_BUSY : 1; /*!< [10..10] When this bit is 1, the local device currently transmits + * data to all ports within the hub group. */ + __IM uint32_t Speed_OK : 1; /*!< [11..11] When this bit is 1, it indicates that the port speed + * of all group ports match. */ + __IM uint32_t TX_Change_Pending : 1; /*!< [12..12] Indicate a pending change request in the hub transmitter + * that is unsolved and cause the hub to stop operation (no + * longer performing any transmissions). */ + uint32_t : 19; + } HUB_STATUS_b; + }; + + union + { + __IM uint32_t HUB_OPORT_STATUS; /*!< (@ 0x00003E24) HUB Output Port Status Register */ + + struct + { + __IM uint32_t HUB_OPORT_STATUS : 3; /*!< [2..0] Per Output Port Data Available Status */ + uint32_t : 29; + } HUB_OPORT_STATUS_b; + }; + __IM uint32_t RESERVED75[22]; + + union + { + __IOM uint32_t TDMA_CONFIG; /*!< (@ 0x00003E80) TDMA Configuration Register */ + + struct + { + __IOM uint32_t TDMA_ENA : 1; /*!< [0..0] Enable TDMA Scheduler */ + __IM uint32_t WAIT_START : 1; /*!< [1..1] Status bit which is set as long as the scheduler is enabled + * but has not yet reached the time given in register TDMA_START. */ + __IOM uint32_t TIMER_SEL : 1; /*!< [2..2] Select which timer to use as the time source for the + * scheduler */ + uint32_t : 1; + __IM uint32_t RED_PERIOD : 1; /*!< [4..4] Read only bit indicating the current period for Profinet */ + __IOM uint32_t RED_OVRD_ENA : 1; /*!< [5..5] Enables overriding the RED period status, regardless + * of the indication by the TCV. */ + __IOM uint32_t RED_OVRD : 1; /*!< [6..6] Override Value for the RED Period */ + __OM uint32_t IN_CT_WREN : 1; /*!< [7..7] IN_CT_WREN */ + __OM uint32_t OUT_CT_WREN : 1; /*!< [8..8] Enable writing the OUT_CT_ENA control to the egress ports. */ + __OM uint32_t HOLD_REQ_CLR : 1; /*!< [9..9] Writing 1 to this register clears the state of TDMA hold + * request. */ + uint32_t : 2; + __IM uint32_t TIMER_SEL_ACTIVE : 1; /*!< [12..12] Return the current timer being used for the TDMA Scheduler */ + uint32_t : 3; + __IOM uint32_t IN_CT_ENA : 4; /*!< [19..16] On read, return the current status of the ingress Cut-Through + * enable indicated by the TDMA scheduler. On write, override + * the ingress Cut-Through enable if IN_CT_WREN is also 1. */ + uint32_t : 4; + __IOM uint32_t OUT_CT_ENA : 4; /*!< [27..24] On read, return the current status of the egress Cut-Through + * enable indicated by the TDMA scheduler. On write, override + * the egress Cut-Through enable if OUT_CT_WREN is also 1. */ + uint32_t : 4; + } TDMA_CONFIG_b; + }; + + union + { + __IOM uint32_t TDMA_ENA_CTRL; /*!< (@ 0x00003E84) TDMA Scheduling Enable Control Register */ + + struct + { + __IOM uint32_t PORT_ENA : 4; /*!< [3..0] Set to 1 to indicate that a port is operating in TDMA + * mode. When set to 1 for a port, the port does not prefetch + * another frame until the current frame in progress is done + * and if TDMA_PREBUF_DIS in COMMAND_CONFIG is set to 1. This + * helps adding precision to the queue gating operations indicated + * by the TDMA at the expense of loss of line rate. */ + uint32_t : 12; + __IOM uint32_t QGATE_DIS : 8; /*!< [23..16] One bit per output queue. When a bit is set to 1, the + * TDMA scheduler gating commands do not affect the queue + * even if the queue mask in the TCV control data is set to + * 1. */ + __IOM uint32_t QTRIG_DIS : 8; /*!< [31..24] One bit per output queue. When a bit is set to 1, the + * TDMA scheduler triggering commands do not affect the queue + * even if the queue mask in the TCV control data is set to + * 1. */ + } TDMA_ENA_CTRL_b; + }; + + union + { + __IOM uint32_t TDMA_START; /*!< (@ 0x00003E88) TDMA Start Time Set Register */ + + struct + { + __IOM uint32_t TDMA_START : 32; /*!< [31..0] Set the start time for the very first cycle after system + * initialization has completed. The value is compared with + * the system time (selected in TDMA_CONFIG.TIMER_SEL) and + * when it is reached (crossed), the scheduler begins with + * its first cycle. The 2nd cycle is then at TDMA_START + + * TDMA_CYCLE. */ + } TDMA_START_b; + }; + + union + { + __IOM uint32_t TDMA_MODULO; /*!< (@ 0x00003E8C) TDMA System Timer Modulo */ + + struct + { + __IOM uint32_t TDMA_MODULO : 32; /*!< [31..0] The System Timer Modulo */ + } TDMA_MODULO_b; + }; + + union + { + __IOM uint32_t TDMA_CYCLE; /*!< (@ 0x00003E90) TDMA Periodic Cycle Set Register */ + + struct + { + __IOM uint32_t TDMA_CYCLE : 32; /*!< [31..0] The periodic cycle time for the scheduler given in system + * timer time. */ + } TDMA_CYCLE_b; + }; + + union + { + __IOM uint32_t TCV_SEQ_ADDR; /*!< (@ 0x00003E94) TCV Sequence Address Register */ + + struct + { + __IOM uint32_t TCV_S_ADDR : 12; /*!< [11..0] Address to write to or read from in the TCV sequence + * table. */ + uint32_t : 19; + __IOM uint32_t ADDR_AINC : 1; /*!< [31..31] When set to 1, read and write operations performed + * using TCV_SEQ_CTRL causes the address in TCV_S_ADDR to + * auto-increment after the operation. */ + } TCV_SEQ_ADDR_b; + }; + + union + { + __IOM uint32_t TCV_SEQ_CTRL; /*!< (@ 0x00003E98) TCV Sequence Table Control Register */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Indicate this TCV must be executed after the next cycle + * start */ + __IOM uint32_t INT : 1; /*!< [1..1] Indicates this TCV generates an interrupt to the CPU + * when activated */ + __IOM uint32_t TCV_D_IDX : 9; /*!< [10..2] Index to the TCV Data Entry */ + uint32_t : 11; + __IOM uint32_t GPIO : 8; /*!< [29..22] Generic bits that control the output pins ETHSW_TDMAOUTn + * (n = 0 to 7) */ + uint32_t : 1; + __IOM uint32_t READ_MODE : 1; /*!< [31..31] When set to 1, a read operation is performed instead + * of writing to the TCV sequence table. The read data (START, + * INT, TCV_D_IDX[8:0], and GPIO) can be obtained by reading + * this register afterwards. On read, this field always returns + * 0. */ + } TCV_SEQ_CTRL_b; + }; + + union + { + __IOM uint32_t TCV_SEQ_LAST; /*!< (@ 0x00003E9C) TCV Sequence Last Entry */ + + struct + { + __IOM uint32_t LAST : 12; /*!< [11..0] Defines the last entry to read from the TCV sequence + * table when the TDMA scheduler is operating. */ + uint32_t : 4; + __IM uint32_t ACTIVE : 12; /*!< [27..16] Return the active TCV sequence entry. */ + uint32_t : 4; + } TCV_SEQ_LAST_b; + }; + + union + { + __IOM uint32_t TCV_D_ADDR; /*!< (@ 0x00003EA0) TCV Data Address Register */ + + struct + { + __IOM uint32_t ADDR : 9; /*!< [8..0] Address to read from/write to in the TCV data table */ + uint32_t : 22; + __IOM uint32_t AINC_WR_ENA : 1; /*!< [31..31] Auto-Increment Enable */ + } TCV_D_ADDR_b; + }; + + union + { + __IOM uint32_t TCV_D_OFFSET; /*!< (@ 0x00003EA4) TCV Data Offset Register */ + + struct + { + __IOM uint32_t TCV_D_OFFSET : 32; /*!< [31..0] 32-bit time offset for the TCV data entry indicated + * by TCV_D_ADDR. When accessing the table, TCV_D_OFFSET must + * be read or written before TCV_D_CTRL. */ + } TCV_D_OFFSET_b; + }; + + union + { + __IOM uint32_t TCV_D_CTRL; /*!< (@ 0x00003EA8) TCV Data Control Register */ + + struct + { + __IOM uint32_t INC_CTR0 : 1; /*!< [0..0] Increment Control for Counter 0 */ + __IOM uint32_t INC_CTR1 : 1; /*!< [1..1] Increment Control for Counter 1 */ + __IOM uint32_t RED_PERIOD : 1; /*!< [2..2] Period Color Control (for Profinet IRT) */ + __IOM uint32_t OUT_CT_ENA : 1; /*!< [3..3] Output Cut-Through Enable */ + __IOM uint32_t IN_CT_ENA : 1; /*!< [4..4] Input Cut-Through Enable */ + __IOM uint32_t TRIGGER_MODE : 1; /*!< [5..5] Trigger mode enable when set to 1. GATE_MODE must be + * 0, otherwise, GATE_MODE has precedence. */ + __IOM uint32_t GATE_MODE : 1; /*!< [6..6] Gate mode enable when set to 1. */ + __IOM uint32_t HOLD_REQ : 1; /*!< [7..7] Preemption hold request. Generates a hold request to + * ports enabled in PMASK. */ + __IOM uint32_t QGATE : 8; /*!< [15..8] Bits mask, one per output queue */ + __IOM uint32_t PMASK : 4; /*!< [19..16] Bits mask, one per output port */ + uint32_t : 12; + } TCV_D_CTRL_b; + }; + + union + { + __IOM uint32_t TDMA_CTR0; /*!< (@ 0x00003EAC) TDMA Counter 0 */ + + struct + { + __IOM uint32_t TDMA_CTR0 : 32; /*!< [31..0] 32-bit counter that is incremented when the TCV field + * INC_CTR0 is set to 1. */ + } TDMA_CTR0_b; + }; + + union + { + __IOM uint32_t TDMA_CTR1; /*!< (@ 0x00003EB0) TDMA Counter 1 */ + + struct + { + __IOM uint32_t VALUE : 8; /*!< [7..0] Current Counter Value */ + __OM uint32_t WRITE_ENA : 1; /*!< [8..8] Write Enable for VALUE */ + uint32_t : 7; + __IOM uint32_t MAX : 8; /*!< [23..16] Counter Maximum Value */ + __IOM uint32_t INT_VALUE : 8; /*!< [31..24] Interrupt Value */ + } TDMA_CTR1_b; + }; + + union + { + __IOM uint32_t TDMA_TCV_START; /*!< (@ 0x00003EB4) TDMA TCV Sequence Entry Start */ + + struct + { + __IOM uint32_t TDMA_TCV_START : 12; /*!< [11..0] Define the TCV_SEQ entry to start from. */ + uint32_t : 20; + } TDMA_TCV_START_b; + }; + + union + { + __IM uint32_t TIME_LOAD_NEXT; /*!< (@ 0x00003EB8) TDMA Calculated Next Loading Time */ + + struct + { + __IM uint32_t TIME_LOAD_NEXT : 32; /*!< [31..0] Status giving the calculated time the scheduler loads + * into its internal compare register after the current running + * slot end is reached (not the end of the current slot). */ + } TIME_LOAD_NEXT_b; + }; + + union + { + __IOM uint32_t TDMA_IRQ_CONTROL; /*!< (@ 0x00003EBC) TDMA IRQ Control Register */ + + struct + { + __IOM uint32_t TCV_INT_EN : 1; /*!< [0..0] Enable Interrupts Generated by the TCV */ + uint32_t : 12; + __IOM uint32_t CTR1_INT_EN : 1; /*!< [13..13] Enable Interrupts Generated from Counter 1 */ + uint32_t : 18; + } TDMA_IRQ_CONTROL_b; + }; + + union + { + __IOM uint32_t TDMA_IRQ_STAT_ACK; /*!< (@ 0x00003EC0) TDMA IRQ Status/ACK Register */ + + struct + { + __IOM uint32_t TCV_ACK : 1; /*!< [0..0] TCV Execution Event */ + uint32_t : 12; + __IOM uint32_t CTR1_ACK : 1; /*!< [13..13] Counter 1 Event */ + uint32_t : 18; + } TDMA_IRQ_STAT_ACK_b; + }; + + union + { + __IOM uint32_t TDMA_GPIO; /*!< (@ 0x00003EC4) TDMA GPIO Register */ + + struct + { + __IM uint32_t GPIO_STATUS : 8; /*!< [7..0] Status of the GPIO Output Pins */ + uint32_t : 8; + __IOM uint32_t GPIO_MODE : 16; /*!< [31..16] 2 bits per GPIO pin to configure its operating mode */ + } TDMA_GPIO_b; + }; + __IM uint32_t RESERVED76[14]; + + union + { + __IOM uint32_t RXMATCH_CONFIG[4]; /*!< (@ 0x00003F00) RX Pattern Matcher Configuration for Port [0..3] */ + + struct + { + __IOM uint32_t PATTERN_EN : 12; /*!< [11..0] Enable Patterns on the Port (RX) */ + uint32_t : 20; + } RXMATCH_CONFIG_b[4]; + }; + __IM uint32_t RESERVED77[12]; + + union + { + __IOM uint32_t PATTERN_CTRL[12]; /*!< (@ 0x00003F40) RX Pattern Matcher Function Control for Pattern + * [0..11] */ + + struct + { + __IOM uint32_t MATCH_NOT : 1; /*!< [0..0] When set, a match is reported and the functions of this + * control are executed if the pattern does not match. */ + __IOM uint32_t MGMTFWD : 1; /*!< [1..1] When set, the frame is forwarded to the management port + * only (suppressing destination address lookup). */ + __IOM uint32_t DISCARD : 1; /*!< [2..2] When set, the frame is discarded. */ + __IOM uint32_t SET_PRIO : 1; /*!< [3..3] Set frame priority, overriding normal classification. */ + __IOM uint32_t MODE : 2; /*!< [5..4] Selects the operating mode */ + __IOM uint32_t TIMER_SEL_OVR : 1; /*!< [6..6] Overrides the default timer to use by timestamp operations + * when set to 1, using instead the value in TIMER_SEL. */ + __IOM uint32_t FORCE_FORWARD : 1; /*!< [7..7] When set, the frame is forwarded to the ports indicated + * in PORTMASK, ignoring the result from L2 lookups. */ + __IOM uint32_t HUBTRIGGER : 1; /*!< [8..8] When set, the port defined in the PORTMASK setting is + * allowed for transmitting one frame. */ + __IOM uint32_t MATCH_RED : 1; /*!< [9..9] Enable the pattern matcher only when the TDMA indicates + * that this is the RED period. */ + __IOM uint32_t MATCH_NOT_RED : 1; /*!< [10..10] Enable the pattern matcher only when the TDMA indicates + * that this is not the RED period. */ + __IOM uint32_t VLAN_SKIP : 1; /*!< [11..11] When set to 1, for operating modes 1, 2, and 3. The + * first Length/Type after the MAC source address is compared + * against 0x8100. If it matches, a VLAN tag is assumed and + * 4 bytes are skipped. */ + __IOM uint32_t PRIORITY : 3; /*!< [14..12] Priority of the frame used when SET_PRIO is set. The + * priority is used to forward the frame into the corresponding + * output queue of a port. */ + __IOM uint32_t LEARNING_DIS : 1; /*!< [15..15] When set to 1, the hardware learning function is not + * executed. */ + __IOM uint32_t PORTMASK : 4; /*!< [19..16] A port mask used depending on the control bits (for + * example, HUBTRIGGER). */ + uint32_t : 2; + __IOM uint32_t IMC_TRIGGER : 1; /*!< [22..22] When set, the ports defined in the PORTMASK setting + * are allowed for transmitting one frame from the queues + * indicated by QUEUESEL. The trigger request is sent to the + * integrated memory controller. */ + __IOM uint32_t IMC_TRIGGER_DLY : 1; /*!< [23..23] When set, the ports defined in the PORTMASK setting + * are allowed for transmitting one frame from the queues + * indicated by QUEUESEL. The trigger request is sent to the + * integrated memory controller and the event is delayed by + * the value programmed in MMCTL_DLY_QTRIGGER_CTRL. */ + __IOM uint32_t SWAP_BYTES : 1; /*!< [24..24] Applicable only for operating modes 1, 2, and 3. When + * set to 1, the byte order is swapped from the order received + * by the frame. When set to 0, the first byte received by + * the frame is set into position 0 for comparison. When set + * to 1, the first byte received is set into position 3 (for + * mode 1) or position 2 (for mode 2 and 3) for comparison. */ + __IOM uint32_t MATCH_LT : 1; /*!< [25..25] For operating modes 1, 2, and 3. When set to 1, the + * Length/Type field in the frame after the MAC source address + * is compared against the value in length_type in the compare + * register. If VLAN_SKIP is set and the frame has a VLAN + * tag with Length/Type of 0x8100 then the comparison is performed + * in the Length/Type following the VLAN tag. */ + __IOM uint32_t TIMER_SEL : 1; /*!< [26..26] Override value to use when TIMER_SEL_OVR is set to + * 1 for selecting the timer for this frame. */ + uint32_t : 1; + __IOM uint32_t QUEUESEL : 4; /*!< [31..28] A queue selector for the HUBTRIGGER function. Selects + * the queue to trigger a frame, or sets from 0x8 to 0xF to + * select one among all queues. */ + } PATTERN_CTRL_b[12]; + }; + __IM uint32_t RESERVED78[4]; + + union + { + __IOM uint32_t PATTERN_IRQ_CONTROL; /*!< (@ 0x00003F80) RX Pattern Matcher Interrupt Control Register */ + + struct + { + __IOM uint32_t MATCHINT : 12; /*!< [11..0] Enable Interrupt on Receive Pattern Match */ + uint32_t : 4; + __IOM uint32_t ERROR_INT : 4; /*!< [19..16] Enable Interrupt on Internal Pattern Matcher Error */ + uint32_t : 12; + } PATTERN_IRQ_CONTROL_b; + }; + + union + { + __IOM uint32_t PATTERN_IRQ_STAT_ACK; /*!< (@ 0x00003F84) RX Pattern Matcher Interrupt Status/ACK Register */ + + struct + { + __IOM uint32_t MATCHINT : 12; /*!< [11..0] Interrupt pending indication for the corresponding pattern + * match events (see ). */ + uint32_t : 4; + __IOM uint32_t ERROR_INT : 4; /*!< [19..16] Interrupt pending indication for a pattern matcher + * error, per port. */ + uint32_t : 12; + } PATTERN_IRQ_STAT_ACK_b; + }; + + union + { + __IOM uint32_t PTRN_VLANID; /*!< (@ 0x00003F88) Custom VLAN ID Register */ + + struct + { + __IOM uint32_t PTRN_VLANID : 16; /*!< [15..0] Custom VLAN ID to use. The default VLAN ID 0x8100 is + * always considered by the hardware. This value can be changed + * to detect other VLANs like 0x8808. */ + uint32_t : 16; + } PTRN_VLANID_b; + }; + + union + { + __IOM uint32_t PATTERN_SEL; /*!< (@ 0x00003F8C) RX Pattern Number Selection Register */ + + struct + { + __IOM uint32_t PATTERN_SEL : 4; /*!< [3..0] Define the pattern number which is selected for read/write + * through the PTRN_CMP_* and PTRN_MSK_* registers. */ + uint32_t : 28; + } PATTERN_SEL_b; + }; + __IM uint32_t RESERVED79[12]; + + union + { + __IOM uint32_t PTRN_CMP_30; /*!< (@ 0x00003FC0) Pattern Compare Value Bytes 3 .. 0 */ + + struct + { + __IOM uint32_t PTRN_CMP_30 : 32; /*!< [31..0] Pattern Compare Value Bytes 3 .. 0 */ + } PTRN_CMP_30_b; + }; + + union + { + __IOM uint32_t PTRN_CMP_74; /*!< (@ 0x00003FC4) Pattern Compare Value Bytes 7 .. 4 */ + + struct + { + __IOM uint32_t PTRN_CMP_74 : 32; /*!< [31..0] Pattern Compare Value Bytes 7 .. 4 */ + } PTRN_CMP_74_b; + }; + + union + { + __IOM uint32_t PTRN_CMP_118; /*!< (@ 0x00003FC8) Pattern Compare Value Bytes 11 .. 8 */ + + struct + { + __IOM uint32_t PTRN_CMP_118 : 32; /*!< [31..0] Pattern Compare Value Bytes 11 .. 8 */ + } PTRN_CMP_118_b; + }; + __IM uint32_t RESERVED80; + + union + { + __IOM uint32_t PTRN_MSK_30; /*!< (@ 0x00003FD0) Pattern Mask for Bytes 3 .. 0 */ + + struct + { + __IOM uint32_t PTRN_MSK_30 : 32; /*!< [31..0] PTRN_MSK_30 */ + } PTRN_MSK_30_b; + }; + + union + { + __IOM uint32_t PTRN_MSK_74; /*!< (@ 0x00003FD4) Pattern Mask for Bytes 7 .. 4 */ + + struct + { + __IOM uint32_t PTRN_MSK_74 : 32; /*!< [31..0] PTRN_MSK_74 */ + } PTRN_MSK_74_b; + }; + + union + { + __IOM uint32_t PTRN_MSK_118; /*!< (@ 0x00003FD8) Pattern Mask for Bytes 11 .. 8 */ + + struct + { + __IOM uint32_t PTRN_MSK_118 : 32; /*!< [31..0] PTRN_MSK_118 */ + } PTRN_MSK_118_b; + }; +} R_ETHSW_Type; /*!< Size = 16348 (0x3fdc) */ + +/* =========================================================================================================================== */ +/* ================ R_ESC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief EtherCAT Slave Controller (R_ESC) + */ + +typedef struct /*!< (@ 0x80130000) R_ESC Structure */ +{ + union + { + __IM uint8_t TYPE; /*!< (@ 0x00000000) Type Register */ + + struct + { + __IM uint8_t TYPE : 8; /*!< [7..0] Type of the EtherCAT slave controller */ + } TYPE_b; + }; + + union + { + __IM uint8_t REVISION; /*!< (@ 0x00000001) Revision Register */ + + struct + { + __IM uint8_t REV : 8; /*!< [7..0] Revision of the EtherCAT slave controller */ + } REVISION_b; + }; + + union + { + __IM uint8_t BUILD; /*!< (@ 0x00000002) Build Register */ + + struct + { + __IM uint8_t BUILD : 8; /*!< [7..0] Build number of the EtherCAT slave controller */ + } BUILD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IM uint8_t FMMU_NUM; /*!< (@ 0x00000004) FMMU Supported Register */ + + struct + { + __IM uint8_t NUMFMMU : 8; /*!< [7..0] Number of FMMU channels supported in the EtherCAT slave + * controller */ + } FMMU_NUM_b; + }; + + union + { + __IM uint8_t SYNC_MANAGER; /*!< (@ 0x00000005) SyncManager Supported Register */ + + struct + { + __IM uint8_t NUMSYNC : 8; /*!< [7..0] Number of SyncManager channels supported in the EtherCAT + * slave controller */ + } SYNC_MANAGER_b; + }; + + union + { + __IM uint8_t RAM_SIZE; /*!< (@ 0x00000006) RAM Size Register */ + + struct + { + __IM uint8_t RAMSIZE : 8; /*!< [7..0] Process data RAM size supported in the EtherCAT slave + * controller (unit: KB) */ + } RAM_SIZE_b; + }; + + union + { + __IM uint8_t PORT_DESC; /*!< (@ 0x00000007) Port Descriptor Register */ + + struct + { + __IM uint8_t P0 : 2; /*!< [1..0] Port 0 configuration */ + __IM uint8_t P1 : 2; /*!< [3..2] Port 1 configuration */ + __IM uint8_t P2 : 2; /*!< [5..4] Port 2 configuration */ + __IM uint8_t P3 : 2; /*!< [7..6] Port 3 configuration */ + } PORT_DESC_b; + }; + + union + { + __IM uint16_t FEATURE; /*!< (@ 0x00000008) ESC Features Supported Register */ + + struct + { + __IM uint16_t FMMU : 1; /*!< [0..0] FMMU Operation */ + uint16_t : 1; + __IM uint16_t DC : 1; /*!< [2..2] Distributed Clock */ + __IM uint16_t DCWID : 1; /*!< [3..3] Distributed Clock Width */ + uint16_t : 2; + __IM uint16_t LINKDECMII : 1; /*!< [6..6] Enhanced Link Detection in MII */ + __IM uint16_t FCS : 1; /*!< [7..7] Separate handling of FCS errors */ + __IM uint16_t DCSYNC : 1; /*!< [8..8] Enhanced DC SYNC activation */ + __IM uint16_t LRW : 1; /*!< [9..9] EtherCAT LRW command support */ + __IM uint16_t RWSUPP : 1; /*!< [10..10] EtherCAT read/write command support (BRW, APRW, FPRW) */ + __IM uint16_t FSCONFIG : 1; /*!< [11..11] Fixed FMMU/SyncManager configuration */ + uint16_t : 4; + } FEATURE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IM uint16_t STATION_ADR; /*!< (@ 0x00000010) Configured Station Address Register */ + + struct + { + __IM uint16_t NODADDR : 16; /*!< [15..0] Node Addressing Address Indication */ + } STATION_ADR_b; + }; + + union + { + __IOM uint16_t STATION_ALIAS; /*!< (@ 0x00000012) Configured Station Alias Register */ + + struct + { + __IOM uint16_t NODALIADDR : 16; /*!< [15..0] Alias Address Indication */ + } STATION_ALIAS_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IM uint8_t WR_REG_ENABLE; /*!< (@ 0x00000020) Write Register Enable Register */ + + struct + { + __IM uint8_t ENABLE : 1; /*!< [0..0] Register Write Protection Unlock */ + uint8_t : 7; + } WR_REG_ENABLE_b; + }; + + union + { + __IM uint8_t WR_REG_PROTECT; /*!< (@ 0x00000021) Write Register Protection Register */ + + struct + { + __IM uint8_t PROTECT : 1; /*!< [0..0] Register Write Protection Specification */ + uint8_t : 7; + } WR_REG_PROTECT_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IM uint8_t ESC_WR_ENABLE; /*!< (@ 0x00000030) ESC Write Enable Register */ + + struct + { + __IM uint8_t ENABLE : 1; /*!< [0..0] Register/Memory Write Protection Unlock */ + uint8_t : 7; + } ESC_WR_ENABLE_b; + }; + + union + { + __IM uint8_t ESC_WR_PROTECT; /*!< (@ 0x00000031) ESC Write Protection Register */ + + struct + { + __IM uint8_t PROTECT : 1; /*!< [0..0] Register/Memory Write Protection Specification */ + uint8_t : 7; + } ESC_WR_PROTECT_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + union + { + __IM uint8_t ESC_RESET_ECAT_R; /*!< (@ 0x00000040) ESC Reset ECAT Register for read */ + + struct + { + __IM uint8_t RESET_ECAT : 2; /*!< [1..0] Reset Progress Status */ + uint8_t : 6; + } ESC_RESET_ECAT_R_b; + }; + + union + { + __IM uint8_t ESC_RESET_ECAT_W; /*!< (@ 0x00000040) ESC Reset ECAT Register for write */ + + struct + { + __IM uint8_t RESET_ECAT : 8; /*!< [7..0] Software Reset Setting */ + } ESC_RESET_ECAT_W_b; + }; + }; + + union + { + union + { + __IOM uint8_t ESC_RESET_PDI_R; /*!< (@ 0x00000041) ESC Reset PDI Register for read */ + + struct + { + __IOM uint8_t RESET_PDI : 2; /*!< [1..0] Reset Progress Status */ + uint8_t : 6; + } ESC_RESET_PDI_R_b; + }; + + union + { + __IOM uint8_t ESC_RESET_PDI_W; /*!< (@ 0x00000041) ESC Reset PDI Register for write */ + + struct + { + __IOM uint8_t RESET_PDI : 8; /*!< [7..0] Software Reset Setting */ + } ESC_RESET_PDI_W_b; + }; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[47]; + + union + { + __IM uint32_t ESC_DL_CONTROL; /*!< (@ 0x00000100) ESC DL Control Register */ + + struct + { + __IM uint32_t FWDRULE : 1; /*!< [0..0] Forwarding Rule */ + __IM uint32_t TEMPUSE : 1; /*!< [1..1] Temporary Use of Bits 15 to 8 Settings */ + uint32_t : 6; + __IM uint32_t LP0 : 2; /*!< [9..8] Loop Port 0 Configuration */ + __IM uint32_t LP1 : 2; /*!< [11..10] Loop Port 1 Configuration */ + __IM uint32_t LP2 : 2; /*!< [13..12] Loop Port 2 Configuration */ + __IM uint32_t LP3 : 2; /*!< [15..14] Loop Port 3 Configuration */ + __IM uint32_t RXFIFO : 3; /*!< [18..16] RX FIFO Size */ + uint32_t : 5; + __IM uint32_t STAALIAS : 1; /*!< [24..24] Station Alias Status */ + uint32_t : 7; + } ESC_DL_CONTROL_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IM uint16_t PHYSICAL_RW_OFFSET; /*!< (@ 0x00000108) Physical Read/Write Offset Register */ + + struct + { + __IM uint16_t RWOFFSET : 16; /*!< [15..0] Offset between Read and Write Addresses */ + } PHYSICAL_RW_OFFSET_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12; + + union + { + __IM uint16_t ESC_DL_STATUS; /*!< (@ 0x00000110) ESC DL Status Register */ + + struct + { + __IM uint16_t PDIOPE : 1; /*!< [0..0] PDI/EEPROM Load State Indication */ + __IM uint16_t PDIWDST : 1; /*!< [1..1] PDI Watchdog Timer Status */ + __IM uint16_t ENHLINKD : 1; /*!< [2..2] Enhanced Link Detection Indication */ + uint16_t : 1; + __IM uint16_t PHYP0 : 1; /*!< [4..4] Port 0 Link State Indication */ + __IM uint16_t PHYP1 : 1; /*!< [5..5] Port 1 Link State Indication */ + __IM uint16_t PHYP2 : 1; /*!< [6..6] Port 2 Link State Indication */ + __IM uint16_t PHYP3 : 1; /*!< [7..7] Port 3 Link State Indication */ + __IM uint16_t LP0 : 1; /*!< [8..8] Loop Port 0 State Indication */ + __IM uint16_t COMP0 : 1; /*!< [9..9] Port 0 Communication State Indication */ + __IM uint16_t LP1 : 1; /*!< [10..10] Loop Port 1 State Indication */ + __IM uint16_t COMP1 : 1; /*!< [11..11] Port 1 Communication State Indication */ + __IM uint16_t LP2 : 1; /*!< [12..12] Loop Port 2 State Indication */ + __IM uint16_t COMP2 : 1; /*!< [13..13] Port 2 Communication State Indication */ + __IM uint16_t LP3 : 1; /*!< [14..14] Loop Port 3 State Indication */ + __IM uint16_t COMP3 : 1; /*!< [15..15] Port 3 Communication State Indication */ + } ESC_DL_STATUS_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + + union + { + __IM uint16_t AL_CONTROL; /*!< (@ 0x00000120) AL Control Register */ + + struct + { + __IM uint16_t INISTATE : 4; /*!< [3..0] Change the state transition of the device state machine. */ + __IM uint16_t ERRINDACK : 1; /*!< [4..4] Error Indication Acknowledge (Response) */ + __IM uint16_t DEVICEID : 1; /*!< [5..5] Device ID Request */ + uint16_t : 10; + } AL_CONTROL_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint16_t AL_STATUS; /*!< (@ 0x00000130) AL Status Register */ + + struct + { + __IOM uint16_t ACTSTATE : 4; /*!< [3..0] State Machine State Indication */ + __IOM uint16_t ERR : 1; /*!< [4..4] Error State Indication */ + __IOM uint16_t DEVICEID : 1; /*!< [5..5] Device ID Load State Indication */ + uint16_t : 10; + } AL_STATUS_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t AL_STATUS_CODE; /*!< (@ 0x00000134) AL Status Code Register */ + + struct + { + __IOM uint16_t STATUSCODE : 16; /*!< [15..0] AL status code */ + } AL_STATUS_CODE_b; + }; + __IM uint16_t RESERVED18; + + union + { + __IOM uint8_t RUN_LED_OVERRIDE; /*!< (@ 0x00000138) RUN LED Override Register */ + + struct + { + __IOM uint8_t LEDCODE : 4; /*!< [3..0] LED Code Indication (FSM state: Bits [3:0] of the AL + * Status register, AL_STATUS) */ + __IOM uint8_t OVERRIDEEN : 1; /*!< [4..4] Override Setting */ + uint8_t : 3; + } RUN_LED_OVERRIDE_b; + }; + + union + { + __IOM uint8_t ERR_LED_OVERRIDE; /*!< (@ 0x00000139) ERR LED Override Register */ + + struct + { + __IOM uint8_t LEDCODE : 4; /*!< [3..0] LED Code Indication */ + __IOM uint8_t OVERRIDEEN : 1; /*!< [4..4] Override Setting */ + uint8_t : 3; + } ERR_LED_OVERRIDE_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20; + + union + { + __IM uint8_t PDI_CONTROL; /*!< (@ 0x00000140) PDI Control Register */ + + struct + { + __IM uint8_t PDI : 8; /*!< [7..0] Process Data Interface. In this LSI, the following value + * is indicated. */ + } PDI_CONTROL_b; + }; + + union + { + __IM uint8_t ESC_CONFIG; /*!< (@ 0x00000141) ESC Configuration Register */ + + struct + { + __IM uint8_t DEVEMU : 1; /*!< [0..0] Device emulation (control of AL status) */ + __IM uint8_t ENLALLP : 1; /*!< [1..1] Sets enhanced link detection for all ports */ + __IM uint8_t DCSYNC : 1; /*!< [2..2] Sets the SYNC output unit for distributed clocks (fixed + * to 1 in this LSI) */ + __IM uint8_t DCLATCH : 1; /*!< [3..3] Sets the latch input unit for distributed clocks */ + __IM uint8_t ENLP0 : 1; /*!< [4..4] Port 0 Enhanced Link Detection Setting */ + __IM uint8_t ENLP1 : 1; /*!< [5..5] Port 1 Enhanced Link Detection Setting */ + __IM uint8_t ENLP2 : 1; /*!< [6..6] Port 2 Enhanced Link Detection Setting */ + __IM uint8_t ENLP3 : 1; /*!< [7..7] Port 3 Enhanced Link Detection Setting */ + } ESC_CONFIG_b; + }; + __IM uint16_t RESERVED21; + __IM uint32_t RESERVED22[3]; + + union + { + __IM uint8_t PDI_CONFIG; /*!< (@ 0x00000150) PDI Configuration Register */ + + struct + { + __IM uint8_t ONCHIPBUSCLK : 5; /*!< [4..0] On-Chip Bus Clock Indication */ + __IM uint8_t ONCHIPBUS : 3; /*!< [7..5] On-Chip Bus Type Indication */ + } PDI_CONFIG_b; + }; + + union + { + __IM uint8_t SYNC_LATCH_CONFIG; /*!< (@ 0x00000151) SYNC/LATCH PDI Configuration Register */ + + struct + { + __IM uint8_t SYNC0OUT : 2; /*!< [1..0] SYNC0 Output Driver and Polarity Indication */ + __IM uint8_t SYNCLAT0 : 1; /*!< [2..2] SYNC0/LATCH0 Indication */ + __IM uint8_t SYNC0MAP : 1; /*!< [3..3] SYNC0 State Mapping Indication */ + __IM uint8_t SYNC1OUT : 2; /*!< [5..4] SYNC1 Output Driver and Polarity Indication */ + __IM uint8_t SYNCLAT1 : 1; /*!< [6..6] SYNC1/LATCH1 Indication */ + __IM uint8_t SYNC1MAP : 1; /*!< [7..7] SYNC1 State Mapping Indication */ + } SYNC_LATCH_CONFIG_b; + }; + + union + { + __IM uint16_t EXT_PDI_CONFIG; /*!< (@ 0x00000152) Extended PDI Configuration Register */ + + struct + { + __IM uint16_t DATABUSWID : 2; /*!< [1..0] PDI Data Bus Width Indication */ + uint16_t : 14; + } EXT_PDI_CONFIG_b; + }; + __IM uint32_t RESERVED23[43]; + + union + { + __IM uint16_t ECAT_EVENT_MASK; /*!< (@ 0x00000200) ECAT Event Mask Register */ + + struct + { + __IM uint16_t ECATEVMASK : 16; /*!< [15..0] Event Request Mask Setting */ + } ECAT_EVENT_MASK_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint32_t AL_EVENT_MASK; /*!< (@ 0x00000204) AL Event Mask Register */ + + struct + { + __IOM uint32_t ALEVMASK : 32; /*!< [31..0] Event Request Mask Setting */ + } AL_EVENT_MASK_b; + }; + __IM uint32_t RESERVED25[2]; + + union + { + __IM uint16_t ECAT_EVENT_REQ; /*!< (@ 0x00000210) ECAT Event Request Register */ + + struct + { + __IM uint16_t DCLATCH : 1; /*!< [0..0] DC Latch Event State Indication */ + uint16_t : 1; + __IM uint16_t DLSTA : 1; /*!< [2..2] DL Status Event State Indication */ + __IM uint16_t ALSTA : 1; /*!< [3..3] AL Status Event State Indication */ + __IM uint16_t SMSTA0 : 1; /*!< [4..4] Mirror value of SyncManager 0 Status Indication */ + __IM uint16_t SMSTA1 : 1; /*!< [5..5] Mirror value of SyncManager 1 Status Indication */ + __IM uint16_t SMSTA2 : 1; /*!< [6..6] Mirror value of SyncManager 2 Status Indication */ + __IM uint16_t SMSTA3 : 1; /*!< [7..7] Mirror value of SyncManager 3 Status Indication */ + __IM uint16_t SMSTA4 : 1; /*!< [8..8] Mirror value of SyncManager 4 Status Indication */ + __IM uint16_t SMSTA5 : 1; /*!< [9..9] Mirror value of SyncManager 5 Status Indication */ + __IM uint16_t SMSTA6 : 1; /*!< [10..10] Mirror value of SyncManager 6 Status Indication */ + __IM uint16_t SMSTA7 : 1; /*!< [11..11] Mirror value of SyncManager 7 Status Indication */ + uint16_t : 4; + } ECAT_EVENT_REQ_b; + }; + __IM uint16_t RESERVED26; + __IM uint32_t RESERVED27[3]; + + union + { + __IM uint32_t AL_EVENT_REQ; /*!< (@ 0x00000220) AL Event Request Register */ + + struct + { + __IM uint32_t ALCTRL : 1; /*!< [0..0] AL Control Event State Indication */ + __IM uint32_t DCLATCH : 1; /*!< [1..1] DC Latch Event State Indication */ + __IM uint32_t DCSYNC0STA : 1; /*!< [2..2] DC SYNC0 State Indication */ + __IM uint32_t DCSYNC1STA : 1; /*!< [3..3] DC SYNC1 State Indication */ + __IM uint32_t SYNCACT : 1; /*!< [4..4] SyncManager Activation Indication */ + uint32_t : 1; + __IM uint32_t WDPD : 1; /*!< [6..6] Watchdog Process Data Indication */ + uint32_t : 1; + __IM uint32_t SMINT0 : 1; /*!< [8..8] SyncManager 0 interrupt (bit 0 or 1 of the SyncManager + * status register (0x0805)) */ + __IM uint32_t SMINT1 : 1; /*!< [9..9] SyncManager 1 interrupt (bit 0 or 1 of the SyncManager + * status register (0x080D)) */ + __IM uint32_t SMINT2 : 1; /*!< [10..10] SyncManager 2 interrupt (bit 0 or 1 of the SyncManager + * status register (0x0815)) */ + __IM uint32_t SMINT3 : 1; /*!< [11..11] SyncManager 3 interrupt (bit 0 or 1 of the SyncManager + * status register (0x081D)) */ + __IM uint32_t SMINT4 : 1; /*!< [12..12] SyncManager 4 interrupt (bit 0 or 1 of the SyncManager + * status register (0x0825)) */ + __IM uint32_t SMINT5 : 1; /*!< [13..13] SyncManager 5 interrupt (bit 0 or 1 of the SyncManager + * status register (0x082D)) */ + __IM uint32_t SMINT6 : 1; /*!< [14..14] SyncManager 6 interrupt (bit 0 or 1 of the SyncManager + * status register (0x0835)) */ + __IM uint32_t SMINT7 : 1; /*!< [15..15] SyncManager 7 interrupt (bit 0 or 1 of the SyncManager + * status register (0x083D)) */ + uint32_t : 16; + } AL_EVENT_REQ_b; + }; + __IM uint32_t RESERVED28[55]; + + union + { + __IM uint16_t RX_ERR_COUNT[3]; /*!< (@ 0x00000300) RX Error Counter [0..2] Register (n = 0 to 2) */ + + struct + { + __IM uint16_t INVFRMCNT : 8; /*!< [7..0] Invalid Frame Counter Value Indication */ + __IM uint16_t RXERRCNT : 8; /*!< [15..8] RX Frame Error Counter Value Indication */ + } RX_ERR_COUNT_b[3]; + }; + __IM uint16_t RESERVED29; + + union + { + __IM uint8_t FWD_RX_ERR_COUNT[3]; /*!< (@ 0x00000308) Forwarded RX Error Counter [0..2] Register (n + * = 0 to 2) */ + + struct + { + __IM uint8_t FWDERRCNT : 8; /*!< [7..0] Forwarded Error Counter Value Indication */ + } FWD_RX_ERR_COUNT_b[3]; + }; + __IM uint8_t RESERVED30; + + union + { + __IM uint8_t ECAT_PROC_ERR_COUNT; /*!< (@ 0x0000030C) ECAT Processing Unit Error Counter Register */ + + struct + { + __IM uint8_t EPUERRCNT : 8; /*!< [7..0] Processing Unit Error Counter Value Indication */ + } ECAT_PROC_ERR_COUNT_b; + }; + + union + { + __IM uint8_t PDI_ERR_COUNT; /*!< (@ 0x0000030D) PDI Error Counter Register */ + + struct + { + __IM uint8_t PDIERRCNT : 8; /*!< [7..0] PDI Error Counter Value Indication */ + } PDI_ERR_COUNT_b; + }; + __IM uint16_t RESERVED31; + + union + { + __IM uint8_t LOST_LINK_COUNT[3]; /*!< (@ 0x00000310) Lost Link Counter [0..2] Register (n = 0 to 2) */ + + struct + { + __IM uint8_t LOSTLINKCNT : 8; /*!< [7..0] Lost Link Counter Value Indication */ + } LOST_LINK_COUNT_b[3]; + }; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[59]; + + union + { + __IM uint16_t WD_DIVIDE; /*!< (@ 0x00000400) Watchdog Divider Register */ + + struct + { + __IM uint16_t WDDIV : 16; /*!< [15..0] Watchdog Clock Frequency Divisor Setting */ + } WD_DIVIDE_b; + }; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; + + union + { + __IM uint16_t WDT_PDI; /*!< (@ 0x00000410) Watchdog Time PDI Register */ + + struct + { + __IM uint16_t WDTIMPDI : 16; /*!< [15..0] Watchdog Overflow Time Setting */ + } WDT_PDI_b; + }; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; + + union + { + __IM uint16_t WDT_DATA; /*!< (@ 0x00000420) Watchdog Time Process Data Register */ + + struct + { + __IM uint16_t WDTIMPD : 16; /*!< [15..0] Watchdog Overflow Time Setting */ + } WDT_DATA_b; + }; + __IM uint16_t RESERVED38; + __IM uint32_t RESERVED39[7]; + + union + { + __IM uint16_t WDS_DATA; /*!< (@ 0x00000440) Watchdog Status Process Data Register */ + + struct + { + __IM uint16_t WDSTAPD : 1; /*!< [0..0] Watchdog State Indication */ + uint16_t : 15; + } WDS_DATA_b; + }; + + union + { + __IM uint8_t WDC_DATA; /*!< (@ 0x00000442) Watchdog Counter Process Data Register */ + + struct + { + __IM uint8_t WDCNTPD : 8; /*!< [7..0] Watchdog Counter Value Indication */ + } WDC_DATA_b; + }; + + union + { + __IM uint8_t WDC_PDI; /*!< (@ 0x00000443) Watchdog Counter PDI Register */ + + struct + { + __IM uint8_t WDCNTPDI : 8; /*!< [7..0] Watchdog Counter Value Indication */ + } WDC_PDI_b; + }; + __IM uint32_t RESERVED40[47]; + + union + { + __IM uint8_t EEP_CONF; /*!< (@ 0x00000500) EEPROM Configuration Register */ + + struct + { + __IM uint8_t CTRLPDI : 1; /*!< [0..0] PDI EEPROM Control */ + __IM uint8_t FORCEECAT : 1; /*!< [1..1] EEPROM Access Right Change */ + uint8_t : 6; + } EEP_CONF_b; + }; + + union + { + __IOM uint8_t EEP_STATE; /*!< (@ 0x00000501) EEPROM PDI Access State Register */ + + struct + { + __IOM uint8_t PDIACCESS : 1; /*!< [0..0] EEPROM Access Right Setting */ + uint8_t : 7; + } EEP_STATE_b; + }; + + union + { + __IOM uint16_t EEP_CONT_STAT; /*!< (@ 0x00000502) EEPROM Control/Status Register */ + + struct + { + __IM uint16_t ECATWREN : 1; /*!< [0..0] ECAT Write Enable */ + uint16_t : 5; + __IM uint16_t READBYTE : 1; /*!< [6..6] EEPROM Read Byte Indication */ + __IM uint16_t PROMSIZE : 1; /*!< [7..7] EEPROM Algorithm Indication */ + __IOM uint16_t COMMAND : 3; /*!< [10..8] Command */ + __IM uint16_t CKSUMERR : 1; /*!< [11..11] Checksum Error Indication */ + __IM uint16_t LOADSTA : 1; /*!< [12..12] EEPROM Loading Status Indication */ + __IM uint16_t ACKCMDERR : 1; /*!< [13..13] Acknowledge/Command Error Indication */ + __IM uint16_t WRENERR : 1; /*!< [14..14] Write Enable Error Indication */ + __IM uint16_t BUSY : 1; /*!< [15..15] EEPROM Interface State Indication */ + } EEP_CONT_STAT_b; + }; + + union + { + __IOM uint32_t EEP_ADR; /*!< (@ 0x00000504) EEPROM Address Register */ + + struct + { + __IOM uint32_t ADDRESS : 32; /*!< [31..0] EEPROM Address Setting */ + } EEP_ADR_b; + }; + + union + { + __IOM uint32_t EEP_DATA; /*!< (@ 0x00000508) EEPROM Data Register */ + + struct + { + __IOM uint32_t LODATA : 16; /*!< [15..0] Data to be written to the EEPROM or data read from the + * EEPROM (lower 2 bytes) */ + __IM uint32_t HIDATA : 16; /*!< [31..16] Data read from the EEPROM (upper 2 bytes) */ + } EEP_DATA_b; + }; + __IM uint32_t RESERVED41; + + union + { + __IOM uint16_t MII_CONT_STAT; /*!< (@ 0x00000510) MII Management Control/Status Register */ + + struct + { + __IM uint16_t WREN : 1; /*!< [0..0] Write Enable */ + __IM uint16_t PDICTRL : 1; /*!< [1..1] PDI Control Indication */ + __IM uint16_t MILINK : 1; /*!< [2..2] MI Link Detection */ + __IM uint16_t PHYOFFSET : 5; /*!< [7..3] PHY Address Offset Indication */ + __IOM uint16_t COMMAND : 2; /*!< [9..8] Command */ + uint16_t : 3; + __IOM uint16_t READERR : 1; /*!< [13..13] Read Error Indication */ + __IM uint16_t CMDERR : 1; /*!< [14..14] Command Error Indication */ + __IM uint16_t BUSY : 1; /*!< [15..15] MII Management State Indication */ + } MII_CONT_STAT_b; + }; + + union + { + __IOM uint8_t PHY_ADR; /*!< (@ 0x00000512) PHY Address Register */ + + struct + { + __IOM uint8_t PHYADDR : 5; /*!< [4..0] PHY Address Setting */ + uint8_t : 3; + } PHY_ADR_b; + }; + + union + { + __IOM uint8_t PHY_REG_ADR; /*!< (@ 0x00000513) PHY Register Address Register */ + + struct + { + __IOM uint8_t PHYREGADDR : 5; /*!< [4..0] Address of PHY register */ + uint8_t : 3; + } PHY_REG_ADR_b; + }; + + union + { + __IOM uint16_t PHY_DATA; /*!< (@ 0x00000514) PHY Data Register */ + + struct + { + __IOM uint16_t PHYREGDATA : 16; /*!< [15..0] PHY Register Data Indication/Setting */ + } PHY_DATA_b; + }; + + union + { + __IM uint8_t MII_ECAT_ACS_STAT; /*!< (@ 0x00000516) MII Management ECAT Access State Register */ + + struct + { + __IM uint8_t ACSMII : 1; /*!< [0..0] MII Management Interface Access Right Setting */ + uint8_t : 7; + } MII_ECAT_ACS_STAT_b; + }; + + union + { + __IOM uint8_t MII_PDI_ACS_STAT; /*!< (@ 0x00000517) MII Management PDI Access State Register */ + + struct + { + __IOM uint8_t ACSMII : 1; /*!< [0..0] Right of access to the MII management interface */ + __IM uint8_t FORPDI : 1; /*!< [1..1] Forced change of access by the PDI (forced change of + * bit 0) */ + uint8_t : 6; + } MII_PDI_ACS_STAT_b; + }; + __IM uint32_t RESERVED42[58]; + __IOM R_ESC_FMMU_Type FMMU[8]; /*!< (@ 0x00000600) FMMU [0..7] Registers (n = 0 to 7) */ + __IM uint32_t RESERVED43[96]; + __IOM R_ESC_SM_Type SM[8]; /*!< (@ 0x00000800) SyncManager [0..7] Registers (n = 0 to 7) */ + __IM uint32_t RESERVED44[48]; + + union + { + __IM uint32_t DC_RCV_TIME_PORT[3]; /*!< (@ 0x00000900) Receive Time Port [0..2] Register */ + + struct + { + __IM uint32_t RCVTIME0 : 32; /*!< [31..0] Receive Time Indication/Latch */ + } DC_RCV_TIME_PORT_b[3]; + }; + __IM uint32_t RESERVED45; + __IM uint32_t DC_SYS_TIME_L; /*!< (@ 0x00000910) System Time Register L */ + __IM uint32_t DC_SYS_TIME_H; /*!< (@ 0x00000914) System Time Register H */ + __IM uint32_t DC_RCV_TIME_UNIT_L; /*!< (@ 0x00000918) Receive Time ECAT Processing Unit Register L */ + __IM uint32_t DC_RCV_TIME_UNIT_H; /*!< (@ 0x0000091C) Receive Time ECAT Processing Unit Register H */ + __IM uint32_t DC_SYS_TIME_OFFSET_L; /*!< (@ 0x00000920) System Time Offset Register L */ + __IM uint32_t DC_SYS_TIME_OFFSET_H; /*!< (@ 0x00000924) System Time Offset Register H */ + + union + { + __IM uint32_t DC_SYS_TIME_DELAY; /*!< (@ 0x00000928) System Time Delay Register */ + + struct + { + __IM uint32_t SYSTIMDLY : 32; /*!< [31..0] Propagation Delay Indication */ + } DC_SYS_TIME_DELAY_b; + }; + + union + { + __IM uint32_t DC_SYS_TIME_DIFF; /*!< (@ 0x0000092C) System Time Difference Register */ + + struct + { + __IM uint32_t DIFF : 31; /*!< [30..0] System Time Mean Difference Indication */ + __IM uint32_t LCP : 1; /*!< [31..31] System Time Greater/Less Indication */ + } DC_SYS_TIME_DIFF_b; + }; + + union + { + __IM uint16_t DC_SPEED_COUNT_START; /*!< (@ 0x00000930) Speed Counter Start Register */ + + struct + { + __IM uint16_t SPDCNTSTRT : 15; /*!< [14..0] Drift Correction Bandwidth Setting */ + uint16_t : 1; + } DC_SPEED_COUNT_START_b; + }; + + union + { + __IM uint16_t DC_SPEED_COUNT_DIFF; /*!< (@ 0x00000932) Speed Counter Difference Register */ + + struct + { + __IM uint16_t SPDCNTDIFF : 16; /*!< [15..0] Clock Period Deviation Indication */ + } DC_SPEED_COUNT_DIFF_b; + }; + + union + { + __IM uint8_t DC_SYS_TIME_DIFF_FIL_DEPTH; /*!< (@ 0x00000934) System Time Difference Filter Depth Register */ + + struct + { + __IM uint8_t SYSTIMDEP : 4; /*!< [3..0] Filter Depth Setting */ + uint8_t : 4; + } DC_SYS_TIME_DIFF_FIL_DEPTH_b; + }; + + union + { + __IM uint8_t DC_SPEED_COUNT_FIL_DEPTH; /*!< (@ 0x00000935) Speed Counter Filter Depth Register */ + + struct + { + __IM uint8_t CLKPERDEP : 4; /*!< [3..0] Filter Depth Setting */ + uint8_t : 4; + } DC_SPEED_COUNT_FIL_DEPTH_b; + }; + __IM uint16_t RESERVED46; + __IM uint32_t RESERVED47[18]; + + union + { + __IM uint8_t DC_CYC_CONT; /*!< (@ 0x00000980) Cyclic Unit Control Register */ + + struct + { + __IM uint8_t SYNCOUT : 1; /*!< [0..0] SYNC Output Unit Control Setting */ + uint8_t : 3; + __IM uint8_t LATCH0 : 1; /*!< [4..4] Latch Input Unit 0 Control Setting */ + __IM uint8_t LATCH1 : 1; /*!< [5..5] Latch Input Unit 1 Control Setting */ + uint8_t : 2; + } DC_CYC_CONT_b; + }; + + union + { + __IOM uint8_t DC_ACT; /*!< (@ 0x00000981) Activation Register */ + + struct + { + __IOM uint8_t SYNCACT : 1; /*!< [0..0] Sync Output Unit Activation */ + __IOM uint8_t SYNC0 : 1; /*!< [1..1] SYNC0 Output Setting */ + __IOM uint8_t SYNC1 : 1; /*!< [2..2] SYNC1 Output Setting */ + __IOM uint8_t AUTOACT : 1; /*!< [3..3] SYNC Output Unit Activation */ + __IOM uint8_t EXTSTARTTIME : 1; /*!< [4..4] Start Time Cyclic Operation Extension */ + __IOM uint8_t STARTTIME : 1; /*!< [5..5] Start Time Plausibility */ + __IOM uint8_t NEARFUTURE : 1; /*!< [6..6] Near Future Range Setting */ + __IOM uint8_t DBGPULSE : 1; /*!< [7..7] Debug Pulse Setting */ + } DC_ACT_b; + }; + + union + { + __IM uint16_t DC_PULSE_LEN; /*!< (@ 0x00000982) SYNC Signal Pulse Length Register */ + + struct + { + __IM uint16_t PULSELEN : 16; /*!< [15..0] SYNC Signal Pulse Length Indication */ + } DC_PULSE_LEN_b; + }; + + union + { + __IM uint8_t DC_ACT_STAT; /*!< (@ 0x00000984) Activation Status Register */ + + struct + { + __IM uint8_t SYNC0ACT : 1; /*!< [0..0] SYNC0 Status Indication */ + __IM uint8_t SYNC1ACT : 1; /*!< [1..1] SYNC1 Status Indication */ + __IM uint8_t STARTTIME : 1; /*!< [2..2] Plausibility Result Indication */ + uint8_t : 5; + } DC_ACT_STAT_b; + }; + __IM uint8_t RESERVED48; + __IM uint16_t RESERVED49; + __IM uint32_t RESERVED50; + __IM uint16_t RESERVED51; + + union + { + __IM uint8_t DC_SYNC0_STAT; /*!< (@ 0x0000098E) SYNC0 Status Register */ + + struct + { + __IM uint8_t SYNC0STA : 1; /*!< [0..0] SYNC0 State Indication */ + uint8_t : 7; + } DC_SYNC0_STAT_b; + }; + + union + { + __IM uint8_t DC_SYNC1_STAT; /*!< (@ 0x0000098F) SYNC1 Status Register */ + + struct + { + __IM uint8_t SYNC1STA : 1; /*!< [0..0] SYNC1 State Indication */ + uint8_t : 7; + } DC_SYNC1_STAT_b; + }; + __IOM uint32_t DC_CYC_START_TIME_L; /*!< (@ 0x00000990) Start Time Cyclic Operation/Next SYNC0 Pulse + * Register L */ + __IOM uint32_t DC_CYC_START_TIME_H; /*!< (@ 0x00000994) Start Time Cyclic Operation/Next SYNC0 Pulse + * Register H */ + __IM uint32_t DC_NEXT_SYNC1_PULSE_L; /*!< (@ 0x00000998) Next SYNC1 Pulse Register L */ + __IM uint32_t DC_NEXT_SYNC1_PULSE_H; /*!< (@ 0x0000099C) Next SYNC1 Pulse Register H */ + + union + { + __IOM uint32_t DC_SYNC0_CYC_TIME; /*!< (@ 0x000009A0) SYNC0 Cycle Time Register */ + + struct + { + __IOM uint32_t SYNC0CYC : 32; /*!< [31..0] Time Between Consecutive SYNC0 Pulses */ + } DC_SYNC0_CYC_TIME_b; + }; + + union + { + __IOM uint32_t DC_SYNC1_CYC_TIME; /*!< (@ 0x000009A4) SYNC1 Cycle Time Register */ + + struct + { + __IOM uint32_t SYNC1CYC : 32; /*!< [31..0] Time between SYNC1 and SYNC0 Pulses */ + } DC_SYNC1_CYC_TIME_b; + }; + + union + { + __IOM uint8_t DC_LATCH0_CONT; /*!< (@ 0x000009A8) Latch 0 Control Register */ + + struct + { + __IOM uint8_t POSEDGE : 1; /*!< [0..0] Latch 0 Positive Edge Function Setting */ + __IOM uint8_t NEGEDGE : 1; /*!< [1..1] Latch 0 Negative Edge Function Setting */ + uint8_t : 6; + } DC_LATCH0_CONT_b; + }; + + union + { + __IOM uint8_t DC_LATCH1_CONT; /*!< (@ 0x000009A9) Latch 1 Control Register */ + + struct + { + __IOM uint8_t POSEDGE : 1; /*!< [0..0] Latch 1 Positive Edge Function Setting */ + __IOM uint8_t NEGEDGE : 1; /*!< [1..1] Latch 1 Negative Edge Function Setting */ + uint8_t : 6; + } DC_LATCH1_CONT_b; + }; + __IM uint16_t RESERVED52[2]; + + union + { + __IM uint8_t DC_LATCH0_STAT; /*!< (@ 0x000009AE) Latch 0 Status Register */ + + struct + { + __IM uint8_t EVENTPOS : 1; /*!< [0..0] Latch 0 Positive Edge Event Indication */ + __IM uint8_t EVENTNEG : 1; /*!< [1..1] Latch 0 Negative Edge Event Indication */ + __IM uint8_t PINSTATE : 1; /*!< [2..2] Latch 0 Input Pin State Indication */ + uint8_t : 5; + } DC_LATCH0_STAT_b; + }; + + union + { + __IM uint8_t DC_LATCH1_STAT; /*!< (@ 0x000009AF) Latch 1 Status Register */ + + struct + { + __IM uint8_t EVENTPOS : 1; /*!< [0..0] Latch 1 Positive Edge Event Indication */ + __IM uint8_t EVENTNEG : 1; /*!< [1..1] Latch 1 Negative Edge Event Indication */ + __IM uint8_t PINSTATE : 1; /*!< [2..2] Latch 1 Input Pin State Indication */ + uint8_t : 5; + } DC_LATCH1_STAT_b; + }; + __IM uint32_t DC_LATCH0_TIME_POS_L; /*!< (@ 0x000009B0) Latch 0 Time Positive Edge Register L */ + __IM uint32_t DC_LATCH0_TIME_POS_H; /*!< (@ 0x000009B4) Latch 0 Time Positive Edge Register H */ + __IM uint32_t DC_LATCH0_TIME_NEG_L; /*!< (@ 0x000009B8) Latch 0 Time Negative Edge Register L */ + __IM uint32_t DC_LATCH0_TIME_NEG_H; /*!< (@ 0x000009BC) Latch 0 Time Negative Edge Register H */ + __IM uint32_t DC_LATCH1_TIME_POS_L; /*!< (@ 0x000009C0) Latch 1 Time Positive Edge Register L */ + __IM uint32_t DC_LATCH1_TIME_POS_H; /*!< (@ 0x000009C4) Latch 1 Time Positive Edge Register H */ + __IM uint32_t DC_LATCH1_TIME_NEG_L; /*!< (@ 0x000009C8) Latch 1 Time Negative Edge Register L */ + __IM uint32_t DC_LATCH1_TIME_NEG_H; /*!< (@ 0x000009CC) Latch 1 Time Negative Edge Register H */ + __IM uint32_t RESERVED53[8]; + + union + { + __IM uint32_t DC_ECAT_CNG_EV_TIME; /*!< (@ 0x000009F0) Buffer Change Event Time Register */ + + struct + { + __IM uint32_t ECATCHANGE : 32; /*!< [31..0] Local Time Indication */ + } DC_ECAT_CNG_EV_TIME_b; + }; + __IM uint32_t RESERVED54; + + union + { + __IM uint32_t DC_PDI_START_EV_TIME; /*!< (@ 0x000009F8) PDI Buffer Start Event Time Register */ + + struct + { + __IM uint32_t PDISTART : 32; /*!< [31..0] Local Time Indication */ + } DC_PDI_START_EV_TIME_b; + }; + + union + { + __IM uint32_t DC_PDI_CNG_EV_TIME; /*!< (@ 0x000009FC) PDI Buffer Change Event Time Register */ + + struct + { + __IM uint32_t PDICHANGE : 32; /*!< [31..0] Local Time Indication */ + } DC_PDI_CNG_EV_TIME_b; + }; + __IM uint32_t RESERVED55[256]; + __IM uint32_t PRODUCT_ID_L; /*!< (@ 0x00000E00) Product ID Register L */ + __IM uint32_t PRODUCT_ID_H; /*!< (@ 0x00000E04) Product ID Register H */ + + union + { + __IM uint32_t VENDOR_ID_L; /*!< (@ 0x00000E08) Vendor ID Register L */ + + struct + { + __IM uint32_t VENDORID : 32; /*!< [31..0] Vendor ID Indication */ + } VENDOR_ID_L_b; + }; +} R_ESC_Type; /*!< Size = 3596 (0xe0c) */ + +/* =========================================================================================================================== */ +/* ================ R_USBHC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 HS Host Module (R_USBHC) + */ + +typedef struct /*!< (@ 0x80200000) R_USBHC Structure */ +{ + union + { + __IM uint32_t HCREVISION; /*!< (@ 0x00000000) HcRevision Register */ + + struct + { + __IM uint32_t REV : 8; /*!< [7..0] HCI revision */ + uint32_t : 24; + } HCREVISION_b; + }; + + union + { + __IOM uint32_t HCCONTROL; /*!< (@ 0x00000004) HcControl Register */ + + struct + { + __IOM uint32_t CBSR : 2; /*!< [1..0] Control/bulk transfer service ratio (ControlBulkServiceRatio) */ + __IOM uint32_t PLE : 1; /*!< [2..2] Periodic list setting (PeriodicListEnable) */ + __IOM uint32_t IE : 1; /*!< [3..3] Isochronous ED processing setting (IsochronousEnable) */ + __IOM uint32_t CLE : 1; /*!< [4..4] Control list processing setting (ControlListEnable) */ + __IOM uint32_t BLE : 1; /*!< [5..5] Bulk list processing setting (BulkListEnable) */ + __IOM uint32_t HCFS : 2; /*!< [7..6] Host logic operation status (Host Controller FunctionalState) */ + __IOM uint32_t IR : 1; /*!< [8..8] HcInterruptStatus interrupt path setting (InterruptRouting) */ + __IOM uint32_t RWC : 1; /*!< [9..9] Remote Wakeup support setting (RemoteWakeUpConnect) */ + __IOM uint32_t RWE : 1; /*!< [10..10] PME assertion control (RemoteWakeUpEnable) */ + uint32_t : 21; + } HCCONTROL_b; + }; + + union + { + __IOM uint32_t HCCOMMANDSTATUS; /*!< (@ 0x00000008) HcCommandStatus Register */ + + struct + { + __OM uint32_t HCR : 1; /*!< [0..0] Host logic software reset start (HostController Reset) */ + __IOM uint32_t CLF : 1; /*!< [1..1] Control list TD (ControlList Filled) */ + __IOM uint32_t BLF : 1; /*!< [2..2] Bulk list TD (BulkListFilled) */ + __OM uint32_t OCR : 1; /*!< [3..3] Host logic control right change (OwnershipChangeRequest) */ + uint32_t : 12; + __IM uint32_t SOC : 2; /*!< [17..16] Schedule overrun count (Scheduling OverrunCount) */ + uint32_t : 14; + } HCCOMMANDSTATUS_b; + }; + + union + { + __IOM uint32_t HCINTERRUPTSTATUS; /*!< (@ 0x0000000C) HcInterruptStatus Register */ + + struct + { + __IOM uint32_t SO : 1; /*!< [0..0] USB schedule overrun (Scheduling Overrun) */ + __IOM uint32_t WDH : 1; /*!< [1..1] Host logic HccaDoneHead update (Writeback Done Head) */ + __IOM uint32_t SF : 1; /*!< [2..2] HccaFrameNumber update (StartOfFrame) */ + __IOM uint32_t RD : 1; /*!< [3..3] Resume detection (Resume Detected) */ + __IOM uint32_t UE : 1; /*!< [4..4] USB non-related system error detection (Unrecoverable + * Error) */ + __IOM uint32_t FNO : 1; /*!< [5..5] FrameNumber bit MSB change (Frame Number Overflow) */ + __IOM uint32_t RHSC : 1; /*!< [6..6] HcRhStatus/HcRhPortStatus register status (RootHubStatus + * Change) */ + uint32_t : 23; + __IOM uint32_t OC : 1; /*!< [30..30] Host logic control right change (OwnershipChange) */ + uint32_t : 1; + } HCINTERRUPTSTATUS_b; + }; + + union + { + __IOM uint32_t HCINTERRUPTENABLE; /*!< (@ 0x00000010) HcInterruptEnable Register */ + + struct + { + __IOM uint32_t SOE : 1; /*!< [0..0] SO interrupt source enable (Scheduling OverrunEnable) */ + __IOM uint32_t WDHE : 1; /*!< [1..1] WDH interrupt source enable (WritebackDone HeadEnable) */ + __IOM uint32_t SFE : 1; /*!< [2..2] SF interrupt source enable (StartOfFrame) */ + __IOM uint32_t RDE : 1; /*!< [3..3] RD interrupt source enable (Resume DetectedEnable) */ + __IOM uint32_t UEE : 1; /*!< [4..4] UE interrupt source enable (Unrecoverable ErrorEnable) */ + __IOM uint32_t FNOE : 1; /*!< [5..5] FNO interrupt source enable (FrameNumber OverflowEnable) */ + __IOM uint32_t RHSCE : 1; /*!< [6..6] RHSC interrupt source enable (RootHubStatus ChangeEnable) */ + uint32_t : 23; + __IOM uint32_t OCE : 1; /*!< [30..30] OC interrupt source enable (OwnershipChangeEnable) */ + __IOM uint32_t MIE : 1; /*!< [31..31] Interrupt 8 source enable (MasterInterrupt Enable) */ + } HCINTERRUPTENABLE_b; + }; + + union + { + __IOM uint32_t HCINTERRUPTDISABLE; /*!< (@ 0x00000014) HcInterruptDisable Register */ + + struct + { + __IOM uint32_t SOD : 1; /*!< [0..0] SO interrupt source disable (Scheduling Overrun Disable) */ + __IOM uint32_t WDHD : 1; /*!< [1..1] WDH interrupt source disable (Writeback DoneHead Disable) */ + __IOM uint32_t SFD : 1; /*!< [2..2] SF interrupt source disable (StartOfFrame Disable) */ + __IOM uint32_t RDD : 1; /*!< [3..3] RD interrupt source disable (Resume Detected Disable) */ + __IOM uint32_t UED : 1; /*!< [4..4] UE interrupt source disable (Unrecoverable ErrorDisable) */ + __IOM uint32_t FNOD : 1; /*!< [5..5] FNO interrupt source disable (FrameNumberOverflow Disable) */ + __IOM uint32_t RHSCD : 1; /*!< [6..6] RHSC interrupt source disable (RootHub StatusChange Disable) */ + uint32_t : 23; + __IOM uint32_t OCD : 1; /*!< [30..30] OC interrupt source disable (OwnershipChangeDisable) */ + __IOM uint32_t MID : 1; /*!< [31..31] Interrupt 8 source disable (Master Interrupt Disable) */ + } HCINTERRUPTDISABLE_b; + }; + + union + { + __IOM uint32_t HCHCCA; /*!< (@ 0x00000018) HcHCCA Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t RAMBA : 24; /*!< [31..8] RAM base address setting */ + } HCHCCA_b; + }; + + union + { + __IM uint32_t HCPERIODCCURRENTIED; /*!< (@ 0x0000001C) HcPeriodicCurrentED Register */ + + struct + { + uint32_t : 4; + __IM uint32_t PCED : 28; /*!< [31..4] ED physical address (PeriodicCurrentED) */ + } HCPERIODCCURRENTIED_b; + }; + + union + { + __IOM uint32_t HCCONTROLHEADED; /*!< (@ 0x00000020) HcControlHeadED Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t CHED : 28; /*!< [31..4] Start ED physical address (ControlHeadED) */ + } HCCONTROLHEADED_b; + }; + + union + { + __IOM uint32_t HCCONTROLCURRENTED; /*!< (@ 0x00000024) HcControlCurrentED Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t CCED : 28; /*!< [31..4] ED physical address (ControlCurrentED) */ + } HCCONTROLCURRENTED_b; + }; + + union + { + __IOM uint32_t HCBULKHEADED; /*!< (@ 0x00000028) HcBulkHeadED Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t BHED : 28; /*!< [31..4] Start ED physical address (BulkHeadED) */ + } HCBULKHEADED_b; + }; + + union + { + __IOM uint32_t HCBULKCURRENTED; /*!< (@ 0x0000002C) HcBulkCurrentED Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t BCED : 28; /*!< [31..4] ED physical address (BulkCurrentED) */ + } HCBULKCURRENTED_b; + }; + + union + { + __IM uint32_t HCDONEHEAD; /*!< (@ 0x00000030) HcDoneHead Register */ + + struct + { + uint32_t : 4; + __IM uint32_t DH : 28; /*!< [31..4] HcDoneHead physical address (DoneHead) */ + } HCDONEHEAD_b; + }; + + union + { + __IOM uint32_t HCFMINTERVAL; /*!< (@ 0x00000034) HcFmInterval Register */ + + struct + { + __IOM uint32_t FI : 14; /*!< [13..0] Frame interval setting (FrameInterval) */ + uint32_t : 2; + __IOM uint32_t FSMPS : 15; /*!< [30..16] FS transfer packet maximum size setting (FSLagest DataPacket) */ + __IOM uint32_t FIT : 1; /*!< [31..31] Frame synchronization (FrameInterval Toggle) */ + } HCFMINTERVAL_b; + }; + + union + { + __IM uint32_t HCFNREMAINING; /*!< (@ 0x00000038) HcFmRemaining Register */ + + struct + { + __IM uint32_t FR : 14; /*!< [13..0] Down counter frame (FrameRemaining) */ + uint32_t : 17; + __IM uint32_t FRT : 1; /*!< [31..31] Frame synchronization (FrameRemainingToggle) */ + } HCFNREMAINING_b; + }; + + union + { + __IM uint32_t HCFMNUMBER; /*!< (@ 0x0000003C) HcFmNumber Register */ + + struct + { + __IM uint32_t FN : 16; /*!< [15..0] Elapsed frame number (FrameNumber) */ + uint32_t : 16; + } HCFMNUMBER_b; + }; + + union + { + __IOM uint32_t HCPERIODSTART; /*!< (@ 0x00000040) HcPeriodicStart Register */ + + struct + { + __IOM uint32_t PS : 14; /*!< [13..0] Periodic list processing start time (PeriodicStart) */ + uint32_t : 18; + } HCPERIODSTART_b; + }; + + union + { + __IOM uint32_t HCLSTHRESHOLD; /*!< (@ 0x00000044) HcLSThreshold Register */ + + struct + { + __IOM uint32_t LS : 12; /*!< [11..0] Transferrable threshold (LSThreshold) */ + uint32_t : 20; + } HCLSTHRESHOLD_b; + }; + + union + { + __IOM uint32_t HCRHDESCRIPTORA; /*!< (@ 0x00000048) HcRhDescriptorA Register */ + + struct + { + __IM uint32_t NDP : 8; /*!< [7..0] Downstream port number (NumberDownstreamPorts) */ + __IOM uint32_t PSM : 1; /*!< [8..8] Power switch control (PowerSwitchingMode) */ + __IOM uint32_t NPS : 1; /*!< [9..9] Power control (NoPower Switching) */ + __IM uint32_t DT : 1; /*!< [10..10] Device type (DeviceType) */ + __IOM uint32_t OCPM : 1; /*!< [11..11] Overcurrent state reporting (OverCurrentProtection + * Mode) */ + __IOM uint32_t NOCP : 1; /*!< [12..12] Overcurrent function support (NoOver Current Protection) */ + uint32_t : 11; + __IOM uint32_t POTPGT : 8; /*!< [31..24] Wait time (PowerOnToPowerGood Time) */ + } HCRHDESCRIPTORA_b; + }; + + union + { + __IOM uint32_t HCRHDESCRIPTORB; /*!< (@ 0x0000004C) HcRhDescriptorB Register */ + + struct + { + __IOM uint32_t DR : 16; /*!< [15..0] Device Removable */ + __IOM uint32_t PPCM : 16; /*!< [31..16] Port Power Control Mask */ + } HCRHDESCRIPTORB_b; + }; + + union + { + __IOM uint32_t HCRHSTATUS; /*!< (@ 0x00000050) HcRhStatus Register */ + + struct + { + __IOM uint32_t LPS : 1; /*!< [0..0] Local power status (LocalPowerStatus) */ + __IM uint32_t OCI : 1; /*!< [1..1] Overcurrent indicator (OverCurrent Indicator) */ + uint32_t : 13; + __IOM uint32_t DRWE : 1; /*!< [15..15] Device remote start enable (DeviceRemoteWakeupEnable) */ + __IOM uint32_t LPSC : 1; /*!< [16..16] Local power status change (LocalPowerStatusChange) */ + __IOM uint32_t OCIC : 1; /*!< [17..17] OCI bit change report (OverCurrent Indicate Change) */ + uint32_t : 13; + __OM uint32_t CRWE : 1; /*!< [31..31] DRWE bit clear (Clear Remote Wakeup Enable) */ + } HCRHSTATUS_b; + }; + + union + { + __IOM uint32_t HCRHPORTSTATUS1; /*!< (@ 0x00000054) HcRhPortStatus1 Register */ + + struct + { + __IOM uint32_t CCS : 1; /*!< [0..0] Connection status indication (CurrentConnectStatus) */ + __IOM uint32_t PES : 1; /*!< [1..1] Port enable status (PortEnableStatus) */ + __IOM uint32_t PSS : 1; /*!< [2..2] Suspend/Resume status (PortSuspendStatus) */ + __IM uint32_t POCI : 1; /*!< [3..3] Downstream port overcurrent detection (PortOverCurrentIndicator) */ + __IOM uint32_t PRS : 1; /*!< [4..4] Port reset status (PortResetStatus) */ + uint32_t : 3; + __IOM uint32_t PPS : 1; /*!< [8..8] Power status (PortPowerStatus) */ + __IOM uint32_t LSDA : 1; /*!< [9..9] Device speed (LowSpeedDeviceAttached) */ + uint32_t : 6; + __IOM uint32_t CSC : 1; /*!< [16..16] CCS bit status (ConnectStatus Change) */ + __IOM uint32_t PESC : 1; /*!< [17..17] PES bit status (PortEnable StatusChange) */ + __IOM uint32_t PSSC : 1; /*!< [18..18] RESUME sequence complete (PortSuspend StatusChange) */ + __IOM uint32_t OCIC : 1; /*!< [19..19] Overcurrent state detection (OverCurrent IndicateChange) */ + __IOM uint32_t PRSC : 1; /*!< [20..20] Port reset complete (PortReset StatusChange) */ + uint32_t : 11; + } HCRHPORTSTATUS1_b; + }; + __IM uint32_t RESERVED[42]; + + union + { + __IM uint32_t CAPL_VERSION; /*!< (@ 0x00000100) Capability Registers Length and EHCI Version + * Number Register */ + + struct + { + __IM uint32_t CRL : 8; /*!< [7..0] Capability Registers Length */ + uint32_t : 8; + __IM uint32_t HCIVN : 16; /*!< [31..16] EHCI Version Number */ + } CAPL_VERSION_b; + }; + + union + { + __IM uint32_t HCSPARAMS; /*!< (@ 0x00000104) Structural Parameters Register */ + + struct + { + __IM uint32_t N_PORTS : 4; /*!< [3..0] Number of downstream ports (Number of Ports) */ + __IM uint32_t PPC : 1; /*!< [4..4] Port power control (Port Power Control) */ + uint32_t : 2; + __IM uint32_t PTRR : 1; /*!< [7..7] Port routing rules */ + __IM uint32_t N_PCC : 4; /*!< [11..8] Number of ports (Number of Ports per Companion Controller) */ + __IM uint32_t N_CC : 4; /*!< [15..12] Number of OHCI host logic (Number of Companion Controller) */ + __IM uint32_t P_INDICATOR : 1; /*!< [16..16] Port indicator control support */ + uint32_t : 3; + __IM uint32_t DBGPTNUM : 4; /*!< [23..20] Debug port number */ + uint32_t : 8; + } HCSPARAMS_b; + }; + + union + { + __IM uint32_t HCCPARAMS; /*!< (@ 0x00000108) Capability Parameters Register */ + + struct + { + __IM uint32_t AC64 : 1; /*!< [0..0] Memory pointer selection */ + __IM uint32_t PFLF : 1; /*!< [1..1] Programming frame list flag */ + __IM uint32_t ASPC : 1; /*!< [2..2] Asynchronous schedule park support capability */ + uint32_t : 1; + __IM uint32_t IST : 4; /*!< [7..4] Isochronous data structure threshold */ + __IM uint32_t EECP : 8; /*!< [15..8] Offset address (EHCI Extend Capabilities Pointer) */ + __IM uint32_t HP : 1; /*!< [16..16] Hardware prefetch capability */ + __IM uint32_t LPMC : 1; /*!< [17..17] Link power management capability */ + __IM uint32_t PCEC : 1; /*!< [18..18] Per-port change event capability */ + __IM uint32_t PL32 : 1; /*!< [19..19] 32-frame periodic list capability */ + uint32_t : 12; + } HCCPARAMS_b; + }; + __IM uint32_t HCSP_PORTROUTE; /*!< (@ 0x0000010C) Companion Port Route Description Register */ + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t USBCMD; /*!< (@ 0x00000120) USB Command Register */ + + struct + { + __IOM uint32_t RS : 1; /*!< [0..0] EHCI host logic run/stop (Run/Stop) */ + __IOM uint32_t HCRESET : 1; /*!< [1..1] Host logic initialization (Host Controller Reset) */ + __IOM uint32_t FLS : 2; /*!< [3..2] Frame list size */ + __IOM uint32_t PSE : 1; /*!< [4..4] Periodic schedule enable */ + __IOM uint32_t ASYNSE : 1; /*!< [5..5] Asynchronous schedule enable */ + __IOM uint32_t IAAD : 1; /*!< [6..6] Interrupt on Async Advance Doorbell */ + __IM uint32_t LHCR : 1; /*!< [7..7] Light host controller reset execution status */ + __IOM uint32_t ASPMC : 2; /*!< [9..8] Asynchronous schedule park mode count */ + uint32_t : 1; + __IOM uint32_t ASPME : 1; /*!< [11..11] Asynchronous schedule park mode enable */ + uint32_t : 3; + __IOM uint32_t PPCEE : 1; /*!< [15..15] Per-port change event enable */ + __IOM uint32_t ITC : 8; /*!< [23..16] Host logic interrupt generation maximum rate (Interrupt + * Threshold Control) */ + __IOM uint32_t HIRD : 4; /*!< [27..24] Host-Initiated Resume Duration (Minimum K-state drive + * time) */ + uint32_t : 4; + } USBCMD_b; + }; + + union + { + __IOM uint32_t USBSTS; /*!< (@ 0x00000124) USB Status Register */ + + struct + { + __IOM uint32_t USBINT : 1; /*!< [0..0] USB transfer complete (USB Interrupt) */ + __IOM uint32_t USBERRINT : 1; /*!< [1..1] USB transaction status (USB Error Interrupt) */ + __IOM uint32_t PTCGDET : 1; /*!< [2..2] Port state change detection */ + __IOM uint32_t FLROV : 1; /*!< [3..3] Frame list rollover */ + __IOM uint32_t HSYSE : 1; /*!< [4..4] Host system error */ + __IOM uint32_t IAAIS : 1; /*!< [5..5] Async advance interrupt status */ + uint32_t : 6; + __IM uint32_t EHCSTS : 1; /*!< [12..12] EHCI host logic status (HCHalted) */ + __IM uint32_t RECLAM : 1; /*!< [13..13] Empty asynchronous schedule detection (Reclamation) */ + __IM uint32_t PSCHSTS : 1; /*!< [14..14] Periodic schedule status */ + __IM uint32_t ASS : 1; /*!< [15..15] Asynchronous schedule status */ + __IOM uint32_t PTCGDETC : 16; /*!< [31..16] Port-n Change Detect */ + } USBSTS_b; + }; + + union + { + __IOM uint32_t USBINTR; /*!< (@ 0x00000128) USB Interrupt Enable Register */ + + struct + { + __IOM uint32_t USBIE : 1; /*!< [0..0] USB interrupt enable */ + __IOM uint32_t USBEIE : 1; /*!< [1..1] USB error interrupt enable */ + __IOM uint32_t PTCGIE : 1; /*!< [2..2] Port change interrupt enable */ + __IOM uint32_t FMLSTROE : 1; /*!< [3..3] Frame list rollover enable */ + __IOM uint32_t HSEE : 1; /*!< [4..4] Host system error enable */ + __IOM uint32_t INTAADVE : 1; /*!< [5..5] Interrupt on async advance enable */ + uint32_t : 10; + __IOM uint32_t PCGIE : 16; /*!< [31..16] Port-n Change Interrupt Enable */ + } USBINTR_b; + }; + + union + { + __IOM uint32_t FRINDEX; /*!< (@ 0x0000012C) USB Frame Index Register */ + + struct + { + __IOM uint32_t FRAMEINDEX : 14; /*!< [13..0] Frame index */ + uint32_t : 18; + } FRINDEX_b; + }; + __IM uint32_t CTRLDSSEGMENT; /*!< (@ 0x00000130) Control Data Structure Segment Register */ + + union + { + __IOM uint32_t PERIODICLISTBASE; /*!< (@ 0x00000134) Periodic Frame List Base Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t PFLSA : 20; /*!< [31..12] Periodic frame list start address */ + } PERIODICLISTBASE_b; + }; + + union + { + __IOM uint32_t ASYNCLISTADDR; /*!< (@ 0x00000138) Next Asynchronous List Address Register */ + + struct + { + uint32_t : 5; + __IOM uint32_t LPL : 27; /*!< [31..5] Asynchronous Queue Head link pointer address (Link Pointer + * Low) */ + } ASYNCLISTADDR_b; + }; + __IM uint32_t RESERVED2[9]; + + union + { + __IOM uint32_t CONFIGFLAG; /*!< (@ 0x00000160) Configure Flag Register */ + + struct + { + __IOM uint32_t CF : 1; /*!< [0..0] Port routing control circuit configuration flag (Configure + * Flag) */ + uint32_t : 31; + } CONFIGFLAG_b; + }; + + union + { + __IOM uint32_t PORTSC1; /*!< (@ 0x00000164) Port 1 Status and Control Register */ + + struct + { + __IM uint32_t CCSTS : 1; /*!< [0..0] Port connection status */ + __IOM uint32_t CSC : 1; /*!< [1..1] Connect status change */ + __IOM uint32_t PTE : 1; /*!< [2..2] Port enable/disable status */ + __IOM uint32_t PTESC : 1; /*!< [3..3] Port enable/disable status change */ + __IM uint32_t OVCACT : 1; /*!< [4..4] Port overcurrent status */ + __IOM uint32_t OVCC : 1; /*!< [5..5] Over-current Change */ + __IOM uint32_t FRCPTRSM : 1; /*!< [6..6] Force Port Resume (Port resume detection flag) */ + __IOM uint32_t SUSPEND : 1; /*!< [7..7] Port suspend */ + __IOM uint32_t PTRST : 1; /*!< [8..8] Port reset status */ + __IOM uint32_t LPMCTL : 1; /*!< [9..9] LPM control */ + __IM uint32_t LINESTS : 2; /*!< [11..10] D+/D- logic level */ + __IOM uint32_t PP : 1; /*!< [12..12] Port Power Supply Control (Port Power) */ + __IOM uint32_t PTOWNR : 1; /*!< [13..13] Port ownership */ + __IM uint32_t PTINDCTL : 2; /*!< [15..14] As the host logic does not support the port indicator + * control function, these bits are set to 00b. */ + __IOM uint32_t PTTST : 4; /*!< [19..16] Pin test control */ + __IOM uint32_t WKCNNT_E : 1; /*!< [20..20] Device connection detection enable (Wake on Connect + * Enable) */ + __IOM uint32_t WKDSCNNT_E : 1; /*!< [21..21] Device disconnection detection enable (Wake on Disconnect + * Enable) */ + __IOM uint32_t WKOC_E : 1; /*!< [22..22] Overcurrent state detection enable (Wake on Over-current + * Enable) */ + __IOM uint32_t SUSPSTS : 2; /*!< [24..23] Suspend status */ + __IOM uint32_t DVADDR : 7; /*!< [31..25] USB device address */ + } PORTSC1_b; + }; + __IM uint32_t RESERVED3[38]; + + union + { + __IOM uint32_t INTENABLE; /*!< (@ 0x00000200) INT_ENABLE Register */ + + struct + { + __IOM uint32_t AHB_INTEN : 1; /*!< [0..0] AHB_INT bit control */ + __IOM uint32_t USBH_INTAEN : 1; /*!< [1..1] USBH_INTA bit control */ + __IOM uint32_t USBH_INTBEN : 1; /*!< [2..2] USBH_INTB bit control */ + __IOM uint32_t UCOM_INTEN : 1; /*!< [3..3] UCOM_INT bit control */ + __IOM uint32_t WAKEON_INTEN : 1; /*!< [4..4] WAKEON_INT bit control */ + uint32_t : 27; + } INTENABLE_b; + }; + + union + { + __IOM uint32_t INTSTATUS; /*!< (@ 0x00000204) INT_STATUS Register */ + + struct + { + __IOM uint32_t AHB_INT : 1; /*!< [0..0] AHB bus error indication */ + __IM uint32_t USBH_INTA : 1; /*!< [1..1] OHCI interrupt status */ + __IM uint32_t USBH_INTB : 1; /*!< [2..2] USBH_INTB EHCI interrupt status */ + __IM uint32_t UCOM_INT : 1; /*!< [3..3] UCOM register interrupt status */ + __IOM uint32_t WAKEON_INT : 1; /*!< [4..4] WAKEON interrupt status */ + uint32_t : 27; + } INTSTATUS_b; + }; + + union + { + __IOM uint32_t AHBBUSCTR; /*!< (@ 0x00000208) AHB_BUS_CTR Register */ + + struct + { + __IOM uint32_t MAX_BURST_LEN : 2; /*!< [1..0] Maximum burst length */ + uint32_t : 2; + __IOM uint32_t ALIGN_ADDRESS : 2; /*!< [5..4] Address boundary setting */ + uint32_t : 2; + __IOM uint32_t PROT_MODE : 1; /*!< [8..8] This bit selects the MHPROT[3:0] mode when the AHB master + * interface initiates a transfer. */ + uint32_t : 3; + __IOM uint32_t PROT_TYPE : 4; /*!< [15..12] These bits set MHPROT[3:0] when the AHB master interface + * initiates a transfer. */ + uint32_t : 16; + } AHBBUSCTR_b; + }; + + union + { + __IOM uint32_t USBCTR; /*!< (@ 0x0000020C) USBCTR Register */ + + struct + { + __OM uint32_t USBH_RST : 1; /*!< [0..0] Software reset for the core */ + __IOM uint32_t PLL_RST : 1; /*!< [1..1] Reset of USB PHY PLL */ + __IOM uint32_t DIRPD : 1; /*!< [2..2] Direct transition to power-down state */ + uint32_t : 29; + } USBCTR_b; + }; + __IM uint32_t RESERVED4[60]; + + union + { + __IM uint32_t REVID; /*!< (@ 0x00000300) Revision and Core ID Register */ + + struct + { + __IM uint32_t MINV : 8; /*!< [7..0] Minor Version */ + __IM uint32_t MAJV : 8; /*!< [15..8] Major Version */ + uint32_t : 8; + __IM uint32_t COREID : 8; /*!< [31..24] Core ID */ + } REVID_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint32_t OCSLPTIMSET; /*!< (@ 0x00000310) Overcurrent Detection/Sleep Timer Setting Register */ + + struct + { + __IOM uint32_t TIMER_OC : 20; /*!< [19..0] Overcurrent Timer setting */ + __IOM uint32_t TIMER_SLEEP : 9; /*!< [28..20] Detection/Sleep Timer Setting */ + uint32_t : 3; + } OCSLPTIMSET_b; + }; + __IM uint32_t RESERVED6[315]; + + union + { + __IOM uint32_t COMMCTRL; /*!< (@ 0x00000800) Common Control Register */ + + struct + { + uint32_t : 31; + __IOM uint32_t PERI : 1; /*!< [31..31] USB mode setting */ + } COMMCTRL_b; + }; + + union + { + __IOM uint32_t OBINTSTA; /*!< (@ 0x00000804) OTG-BC Interrupt Status Register */ + + struct + { + __IOM uint32_t IDCHG_STA : 1; /*!< [0..0] USB_OTGID change status */ + __IOM uint32_t OCINT_STA : 1; /*!< [1..1] USB_OVRCUR assertion status */ + __IOM uint32_t VBSTACHG_STA : 1; /*!< [2..2] VBSTA[3:0] change status */ + __IOM uint32_t VBSTAINT_STA : 1; /*!< [3..3] VBUS voltage status interrupt */ + uint32_t : 12; + __IOM uint32_t DMMONCHG_STA : 1; /*!< [16..16] DMMON change status */ + __IOM uint32_t DPMONCHG_STA : 1; /*!< [17..17] DPMON change status */ + uint32_t : 14; + } OBINTSTA_b; + }; + + union + { + __IOM uint32_t OBINTEN; /*!< (@ 0x00000808) OTG-BC Interrupt Enable Register */ + + struct + { + __IOM uint32_t IDCHG_EN : 1; /*!< [0..0] IDCHG_STA Interrupt enable */ + __IOM uint32_t OCINT_EN : 1; /*!< [1..1] OCINT_STA interrupt enable */ + __IOM uint32_t VBSTACHG_EN : 1; /*!< [2..2] VBSTACHG_STA interrupt enable */ + __IOM uint32_t VBSTAINT_EN : 1; /*!< [3..3] VBSTAINT_STA interrupt enable */ + uint32_t : 12; + __IOM uint32_t DMMONCHG_EN : 1; /*!< [16..16] DMMONCHG_STA interrupt enable */ + __IOM uint32_t DPMONCHG_EN : 1; /*!< [17..17] DPMONCHG_STA interrupt enable */ + uint32_t : 14; + } OBINTEN_b; + }; + + union + { + __IOM uint32_t VBCTRL; /*!< (@ 0x0000080C) VBUS Control Register */ + + struct + { + __IOM uint32_t VBOUT : 1; /*!< [0..0] VBUS drive control (USB_VBUSEN pin) */ + __IOM uint32_t VBUSENSEL : 1; /*!< [1..1] USB_VBUSEN pin control */ + uint32_t : 2; + __IOM uint32_t VGPUO : 1; /*!< [4..4] USB_EXICEN pin control */ + uint32_t : 11; + __IOM uint32_t OCCLRIEN : 1; /*!< [16..16] USB_VBUSEN pin control at occurrence of overcurrent */ + __IOM uint32_t OCISEL : 1; /*!< [17..17] Overcurrent detection */ + uint32_t : 2; + __IOM uint32_t VBLVL : 4; /*!< [23..20] VBUS level detection */ + uint32_t : 4; + __IM uint32_t VBSTA : 4; /*!< [31..28] VBUS indication */ + } VBCTRL_b; + }; + + union + { + __IOM uint32_t LINECTRL1; /*!< (@ 0x00000810) Line Control Port 1 Register */ + + struct + { + __IM uint32_t IDMON : 1; /*!< [0..0] Indicates a value of USB_OTGID input pin. */ + uint32_t : 1; + __IM uint32_t DMMON : 1; /*!< [2..2] Indicates a value of USB bus DM. */ + __IM uint32_t DPMON : 1; /*!< [3..3] Indicates a value of USB bus DP. */ + uint32_t : 12; + __IOM uint32_t DM_RPD : 1; /*!< [16..16] Controls USB bus (DM) 15 kOhm pulldown resistor when + * DMPPD_EN = 1. */ + __IOM uint32_t DMRPD_EN : 1; /*!< [17..17] Enables DM_RPD to control USB bus (DM) 15 kOhm pulldown + * resistor. */ + __IOM uint32_t DP_RPD : 1; /*!< [18..18] Controls USB bus (DP) 15 kOhm pulldown resistor when + * DRPPD_EN = 1. */ + __IOM uint32_t DPRPD_EN : 1; /*!< [19..19] Enables DP_RPD to control USB bus (DP) 15 kOhm pulldown + * resistor. */ + uint32_t : 12; + } LINECTRL1_b; + }; +} R_USBHC_Type; /*!< Size = 2068 (0x814) */ + +/* =========================================================================================================================== */ +/* ================ R_USBF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Host and Function Module (R_USBF) + */ + +typedef struct /*!< (@ 0x80201000) R_USBF Structure */ +{ + union + { + __IOM uint16_t SYSCFG0; /*!< (@ 0x00000000) System Configuration Control Register 0 */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Block Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + uint16_t : 1; + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] Single-End Receiver Operation Enable */ + uint16_t : 7; + } SYSCFG0_b; + }; + + union + { + __IOM uint16_t SYSCFG1; /*!< (@ 0x00000002) System Configuration Control Register 1 */ + + struct + { + __IOM uint16_t BWAIT : 6; /*!< [5..0] CPU Bus Access Wait Specification */ + uint16_t : 2; + __IOM uint16_t AWAIT : 6; /*!< [13..8] AHB-DMA Bridge Bus Access Wait Specification */ + uint16_t : 2; + } SYSCFG1_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + uint16_t : 14; + } SYSSTS0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] Reset Handshake */ + uint16_t : 5; + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + uint16_t : 7; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3; + + union + { + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port */ + } CFIFO_b; + }; + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) FIFO Port Register */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) FIFO Port Register */ + }; + + union + { + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) FIFO Port Register */ + + struct + { + __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port */ + } CFIFOH_b; + }; + + struct + { + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) FIFO Port Register */ + + struct + { + __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port */ + } CFIFOHH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port */ + } D0FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) FIFO Port Register */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) FIFO Port Register */ + }; + + union + { + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) FIFO Port Register */ + + struct + { + __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port */ + } D0FIFOH_b; + }; + + struct + { + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) FIFO Port Register */ + + struct + { + __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port */ + } D0FIFOHH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port */ + } D1FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) FIFO Port Register */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) FIFO Port Register */ + }; + + union + { + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) FIFO Port Register */ + + struct + { + __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port */ + } D1FIFOH_b; + }; + + struct + { + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) FIFO Port Register */ + + struct + { + __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port */ + } D1FIFOHH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode after Specified Pipe + * Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode after Specified Pipe + * Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE : 1; /*!< [0..0] PDDETINT Detection Interrupt Enable */ + uint16_t : 15; + } INTENB1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing */ + uint16_t : 9; + } SOFCFG_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] BRDY Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] NRDY Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] BEMP Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Update Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Change Detect Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT : 1; /*!< [0..0] PDDET Detection Interrupt Status */ + uint16_t : 15; + } INTSTS1_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IM uint16_t UFRMNUM; /*!< (@ 0x0000004E) Frame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] Microframe Number */ + uint16_t : 13; + } UFRMNUM_b; + }; + + union + { + __IM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address */ + uint16_t : 9; + } USBADDR_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request Type */ + __IM uint16_t BREQUEST : 8; /*!< [15..8] Request */ + } USBREQ_b; + }; + + union + { + __IM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IM uint16_t WVALUE : 16; /*!< [15..0] Value */ + } USBVAL_b; + }; + + union + { + __IM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IM uint16_t WINDEX : 16; /*!< [15..0] Index */ + } USBINDX_b; + }; + + union + { + __IM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IM uint16_t WLENGTH : 16; /*!< [15..0] Length */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Disabling PIPE at the End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet Size */ + uint16_t : 9; + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] PIPE Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + uint16_t : 6; + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disable at the End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Specification Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer number */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer size */ + uint16_t : 1; + } PIPEBUF_b; + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet Size */ + uint16_t : 5; + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Timing Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection Spacing */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE[0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] PIPE Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit Confirm */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 3; + __IM uint16_t INBUFM : 1; /*!< [14..14] Transfer Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[3]; + __IOM R_USBF_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) PIPEn Transaction Counter Registers (n=1-5) */ + __IM uint32_t RESERVED16[23]; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED18[191]; + __IOM R_USBF_CHa_Type CHa[2]; /*!< (@ 0x00000400) Next Register Set */ + __IM uint32_t RESERVED19[96]; + __IOM R_USBF_CHb_Type CHb[2]; /*!< (@ 0x00000600) Skip Register Set */ + __IM uint32_t RESERVED20[48]; + + union + { + __IOM uint32_t DCTRL; /*!< (@ 0x00000700) DMA Control Register */ + + struct + { + __IOM uint32_t PR : 1; /*!< [0..0] Priority */ + uint32_t : 15; + __IOM uint32_t LDPR : 4; /*!< [19..16] Link Descriptor PROT */ + uint32_t : 4; + __IOM uint32_t LWPR : 4; /*!< [27..24] Link WriteBack PROT */ + uint32_t : 4; + } DCTRL_b; + }; + + union + { + __IOM uint32_t DSCITVL; /*!< (@ 0x00000704) Descriptor Interval Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t DITVL : 8; /*!< [15..8] Descriptor Interval */ + uint32_t : 16; + } DSCITVL_b; + }; + __IM uint32_t RESERVED21[2]; + + union + { + __IM uint32_t DSTAT_EN; /*!< (@ 0x00000710) DMA Status EN Register */ + + struct + { + __IM uint32_t EN0 : 1; /*!< [0..0] Channel 0 EN */ + __IM uint32_t EN1 : 1; /*!< [1..1] Channel 1 EN */ + uint32_t : 30; + } DSTAT_EN_b; + }; + + union + { + __IM uint32_t DSTAT_ER; /*!< (@ 0x00000714) DMA Status ER Register */ + + struct + { + __IM uint32_t ER0 : 1; /*!< [0..0] Channel 0 ER */ + __IM uint32_t ER1 : 1; /*!< [1..1] Channel 1 ER */ + uint32_t : 30; + } DSTAT_ER_b; + }; + + union + { + __IM uint32_t DSTAT_END; /*!< (@ 0x00000718) DMA Status END Register */ + + struct + { + __IM uint32_t END0 : 1; /*!< [0..0] Channel 0 END */ + __IM uint32_t END1 : 1; /*!< [1..1] Channel 1 END */ + uint32_t : 30; + } DSTAT_END_b; + }; + + union + { + __IM uint32_t DSTAT_TC; /*!< (@ 0x0000071C) DMA Status TC Register */ + + struct + { + __IM uint32_t TC0 : 1; /*!< [0..0] Channel 0 TC */ + __IM uint32_t TC1 : 1; /*!< [1..1] Channel 1 TC */ + uint32_t : 30; + } DSTAT_TC_b; + }; + + union + { + __IM uint32_t DSTAT_SUS; /*!< (@ 0x00000720) DMA Status SUS Register */ + + struct + { + __IM uint32_t SUS0 : 1; /*!< [0..0] Channel 0 SUS */ + __IM uint32_t SUS1 : 1; /*!< [1..1] Channel 1 SUS */ + uint32_t : 30; + } DSTAT_SUS_b; + }; +} R_USBF_Type; /*!< Size = 1828 (0x724) */ + +/* =========================================================================================================================== */ +/* ================ R_BSC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus State Controller (R_BSC) + */ + +typedef struct /*!< (@ 0x80210000) R_BSC Structure */ +{ + union + { + __IOM uint32_t CMNCR; /*!< (@ 0x00000000) Common Control Register */ + + struct + { + uint32_t : 9; + __IOM uint32_t DPRTY : 2; /*!< [10..9] DMA Burst Transfer Priority */ + uint32_t : 13; + __IOM uint32_t AL : 1; /*!< [24..24] Acknowledge Level */ + uint32_t : 3; + __IOM uint32_t TL : 1; /*!< [28..28] Transfer End Level */ + uint32_t : 3; + } CMNCR_b; + }; + + union + { + __IOM uint32_t CSnBCR[6]; /*!< (@ 0x00000004) CS[0..5] Space Bus Control Register */ + + struct + { + uint32_t : 9; + __IOM uint32_t BSZ : 2; /*!< [10..9] Data Bus Width Specification */ + uint32_t : 1; + __IOM uint32_t TYPE : 3; /*!< [14..12] Memory Connected to a Space */ + uint32_t : 1; + __IOM uint32_t IWRRS : 3; /*!< [18..16] Idle State Insertion between Read-Read Cycles in the + * Same CS Space */ + __IOM uint32_t IWRRD : 3; /*!< [21..19] Idle State Insertion between Read-Read Cycles in Different + * CS Spaces */ + __IOM uint32_t IWRWS : 3; /*!< [24..22] Idle State Insertion between Read-Write Cycles in the + * Same CS Space */ + __IOM uint32_t IWRWD : 3; /*!< [27..25] Idle State Insertion between Read-Write Cycles in Different + * CS Spaces */ + __IOM uint32_t IWW : 3; /*!< [30..28] Idle Cycles between Write-Read Cycles and Write-Write + * Cycles */ + uint32_t : 1; + } CSnBCR_b[6]; + }; + __IM uint32_t RESERVED[3]; + + union + { + union + { + __IOM uint32_t CS0WCR_0; /*!< (@ 0x00000028) CS0 Space Wait Control Register for Normal Space, + * SRAM with Byte Selection */ + + struct + { + __IOM uint32_t HW : 2; /*!< [1..0] Delay States from RD#, WEn# Negation to Address, CS0# + * Negation */ + uint32_t : 4; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t WR : 4; /*!< [10..7] Number of Access Waits */ + __IOM uint32_t SW : 2; /*!< [12..11] Number of Delay Cycles from Address, CSn# Assertion + * to RD#, WEn# Assertion */ + uint32_t : 7; + __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select */ + uint32_t : 11; + } CS0WCR_0_b; + }; + + union + { + __IOM uint32_t CS0WCR_1; /*!< (@ 0x00000028) CS0 Space Wait Control Register for Burst ROM + * with Clocked Asynchronous */ + + struct + { + uint32_t : 6; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t W : 4; /*!< [10..7] Number of Access Waits */ + uint32_t : 5; + __IOM uint32_t BW : 2; /*!< [17..16] Number of Waits during Burst Access */ + uint32_t : 2; + __IOM uint32_t BST : 2; /*!< [21..20] Burst Count Specification */ + uint32_t : 10; + } CS0WCR_1_b; + }; + + union + { + __IOM uint32_t CS0WCR_2; /*!< (@ 0x00000028) CS0 Space Wait Control Register for Burst ROM + * with Clocked Synchronous */ + + struct + { + uint32_t : 6; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t W : 4; /*!< [10..7] Number of Access Waits */ + uint32_t : 5; + __IOM uint32_t BW : 2; /*!< [17..16] Number of Burst Wait Cycles */ + uint32_t : 14; + } CS0WCR_2_b; + }; + }; + __IM uint32_t RESERVED1; + + union + { + union + { + __IOM uint32_t CS2WCR_0; /*!< (@ 0x00000030) CS2 Space Wait Control Register for Normal Space, + * SRAM with Byte Selection */ + + struct + { + uint32_t : 6; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t WR : 4; /*!< [10..7] Number of Access Waits */ + uint32_t : 9; + __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select */ + uint32_t : 11; + } CS2WCR_0_b; + }; + + union + { + __IOM uint32_t CS2WCR_1; /*!< (@ 0x00000030) CS2 Space Wait Control Register for SDRAM */ + + struct + { + uint32_t : 7; + __IOM uint32_t A2CL : 2; /*!< [8..7] CAS Latency for Area 2 */ + uint32_t : 23; + } CS2WCR_1_b; + }; + }; + + union + { + union + { + __IOM uint32_t CS3WCR_0; /*!< (@ 0x00000034) CS3 Space Wait Control Register for Normal Space, + * SRAM with Byte Selection */ + + struct + { + uint32_t : 6; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t WR : 4; /*!< [10..7] Number of Access Waits */ + uint32_t : 9; + __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select */ + uint32_t : 11; + } CS3WCR_0_b; + }; + + union + { + __IOM uint32_t CS3WCR_1; /*!< (@ 0x00000034) CS3 Space Wait Control Register for SDRAM */ + + struct + { + __IOM uint32_t WTRC : 2; /*!< [1..0] Number of Idle States from REF Command/Self-Refresh Release + * to ACTV/REF/MRS Command */ + uint32_t : 1; + __IOM uint32_t TRWL : 2; /*!< [4..3] Number of Auto-Precharge Startup Wait Cycles */ + uint32_t : 2; + __IOM uint32_t A3CL : 2; /*!< [8..7] CAS Latency for Area 3 */ + uint32_t : 1; + __IOM uint32_t WTRCD : 2; /*!< [11..10] Number of Waits between ACTV Command and READ(A)/WRIT(A) + * Command */ + uint32_t : 1; + __IOM uint32_t WTRP : 2; /*!< [14..13] Number of Auto-Precharge Completion Wait States */ + uint32_t : 17; + } CS3WCR_1_b; + }; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CS5WCR; /*!< (@ 0x0000003C) CS5 Space Wait Control Register for Normal Space, + * SRAM with Byte Selection, and MPX-I/O */ + + struct + { + __IOM uint32_t HW : 2; /*!< [1..0] Delay Cycles from RD#, WEn# to Address, CS5# */ + uint32_t : 4; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t WR : 4; /*!< [10..7] Number of Read Access Waits */ + __IOM uint32_t SW : 2; /*!< [12..11] Number of Delay Cycles from Address, CS5# Assertion + * to RD#, WEn# Assertion */ + uint32_t : 3; + __IOM uint32_t WW : 3; /*!< [18..16] Number of Write Access Waits */ + uint32_t : 1; + __IOM uint32_t MPXWSBAS : 1; /*!< [20..20] MPX-I/O Interface Address Cycle Wait and SRAM with + * Byte Selection Byte Access Select */ + __IOM uint32_t SZSEL : 1; /*!< [21..21] MPX-I/O Interface Bus Width Specification */ + uint32_t : 10; + } CS5WCR_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t SDCR; /*!< (@ 0x0000004C) SDRAM Control Register */ + + struct + { + __IOM uint32_t A3COL : 2; /*!< [1..0] Number of Bits of Column Address for Area 3 */ + uint32_t : 1; + __IOM uint32_t A3ROW : 2; /*!< [4..3] Number of Bits of Row Address for Area 3 */ + uint32_t : 3; + __IOM uint32_t BACTV : 1; /*!< [8..8] Bank Active Mode */ + __IOM uint32_t PDOWN : 1; /*!< [9..9] Power-Down Mode */ + __IOM uint32_t RMODE : 1; /*!< [10..10] Refresh Mode */ + __IOM uint32_t RFSH : 1; /*!< [11..11] Refresh Control */ + uint32_t : 1; + __IOM uint32_t DEEP : 1; /*!< [13..13] Deep Power-Down Mode */ + uint32_t : 2; + __IOM uint32_t A2COL : 2; /*!< [17..16] Number of Bits of Column Address for Area 2 */ + uint32_t : 1; + __IOM uint32_t A2ROW : 2; /*!< [20..19] Number of Bits of Row Address for Area 2 */ + uint32_t : 11; + } SDCR_b; + }; + __IOM uint32_t RTCSR; /*!< (@ 0x00000050) Refresh Timer Control/Status Register */ + __IOM uint32_t RTCNT; /*!< (@ 0x00000054) Refresh Timer Counter */ + __IOM uint32_t RTCOR; /*!< (@ 0x00000058) Refresh Time Constant Register */ + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t TOSCOR[6]; /*!< (@ 0x00000060) Timeout Cycle Constant Register [0..5] */ + + struct + { + __IOM uint32_t TOCNUM : 16; /*!< [15..0] Timeout Cycle Number */ + uint32_t : 16; + } TOSCOR_b[6]; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t TOSTR; /*!< (@ 0x00000080) Timeout Status Register */ + + struct + { + __IOM uint32_t CS0TOSTF : 1; /*!< [0..0] CS0 Space Timeout Status Flag */ + uint32_t : 1; + __IOM uint32_t CS2TOSTF : 1; /*!< [2..2] CS2 Space Timeout Status Flag */ + __IOM uint32_t CS3TOSTF : 1; /*!< [3..3] CS3 Space Timeout Status Flag */ + uint32_t : 1; + __IOM uint32_t CS5TOSTF : 1; /*!< [5..5] CS5 Space Timeout Status Flag */ + uint32_t : 26; + } TOSTR_b; + }; + + union + { + __IOM uint32_t TOENR; /*!< (@ 0x00000084) Timeout Enable Register */ + + struct + { + __IOM uint32_t CS0TOEN : 1; /*!< [0..0] CS0 Space Timeout Detection Enable */ + uint32_t : 1; + __IOM uint32_t CS2TOEN : 1; /*!< [2..2] CS2 Space Timeout Detection Enable */ + __IOM uint32_t CS3TOEN : 1; /*!< [3..3] CS3 Space Timeout Detection Enable */ + uint32_t : 1; + __IOM uint32_t CS5TOEN : 1; /*!< [5..5] CS5 Space Timeout Detection Enable */ + uint32_t : 26; + } TOENR_b; + }; +} R_BSC_Type; /*!< Size = 136 (0x88) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief xSPI (R_XSPI0) + */ + +typedef struct /*!< (@ 0x80220000) R_XSPI0 Structure */ +{ + union + { + __IOM uint32_t WRAPCFG; /*!< (@ 0x00000000) xSPI Wrapper Configuration Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0 */ + uint32_t : 11; + __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1 */ + uint32_t : 3; + } WRAPCFG_b; + }; + + union + { + __IOM uint32_t COMCFG; /*!< (@ 0x00000004) xSPI Common Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t OEASTEX : 1; /*!< [16..16] Output Enable Asserting extension */ + __IOM uint32_t OENEGEX : 1; /*!< [17..17] Output Enable Negating extension */ + uint32_t : 14; + } COMCFG_b; + }; + + union + { + __IOM uint32_t BMCFG; /*!< (@ 0x00000008) xSPI Bridge Map Configuration Register */ + + struct + { + __IOM uint32_t WRMD : 1; /*!< [0..0] AHB Write Response mode */ + uint32_t : 6; + __IOM uint32_t MWRCOMB : 1; /*!< [7..7] Memory Write Combination mode */ + __IOM uint32_t MWRSIZE : 8; /*!< [15..8] Memory Write Size */ + __IOM uint32_t PREEN : 1; /*!< [16..16] Prefetch enable */ + uint32_t : 15; + } BMCFG_b; + }; + __IM uint32_t RESERVED; + __IOM R_XSPI0_CSa_Type CSa[2]; /*!< (@ 0x00000010) xSPI Command Map Configuration Register [0..1] */ + __IM uint32_t RESERVED1[8]; + + union + { + __IOM uint32_t LIOCFGCS[2]; /*!< (@ 0x00000050) xSPI Link I/O Configuration Register CSn */ + + struct + { + __IOM uint32_t PRTMD : 10; /*!< [9..0] Protocol mode */ + __IOM uint32_t LATEMD : 1; /*!< [10..10] Latency mode */ + __IOM uint32_t WRMSKMD : 1; /*!< [11..11] Write mask mode */ + uint32_t : 4; + __IOM uint32_t CSMIN : 4; /*!< [19..16] CS minimum idle term */ + __IOM uint32_t CSASTEX : 1; /*!< [20..20] CS asserting extension */ + __IOM uint32_t CSNEGEX : 1; /*!< [21..21] CS negating extension */ + __IOM uint32_t SDRDRV : 1; /*!< [22..22] SDR driving timing */ + __IOM uint32_t SDRSMPMD : 1; /*!< [23..23] SDR Sampling mode */ + __IOM uint32_t SDRSMPSFT : 4; /*!< [27..24] SDR Sampling window shift */ + __IOM uint32_t DDRSMPEX : 4; /*!< [31..28] DDR sampling window extend */ + } LIOCFGCS_b[2]; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t BMCTL0; /*!< (@ 0x00000060) xSPI Bridge Map Control Register 0 */ + + struct + { + __IOM uint32_t CS0ACC : 2; /*!< [1..0] AHB channel to slave0 memory area access enable */ + __IOM uint32_t CS1ACC : 2; /*!< [3..2] AHB channel to slave1 memory area access enable */ + uint32_t : 28; + } BMCTL0_b; + }; + + union + { + __OM uint32_t BMCTL1; /*!< (@ 0x00000064) xSPI Bridge Map Control Register 1 */ + + struct + { + uint32_t : 8; + __OM uint32_t MWRPUSH : 1; /*!< [8..8] Memory Write Data Push */ + uint32_t : 1; + __OM uint32_t PBUFCLR : 1; /*!< [10..10] Prefetch Buffer clear */ + uint32_t : 21; + } BMCTL1_b; + }; + + union + { + __IOM uint32_t CMCTL; /*!< (@ 0x00000068) xSPI Command Map Control Register */ + + struct + { + __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code */ + __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code */ + __IOM uint32_t XIPEN : 1; /*!< [16..16] XiP mode enable */ + uint32_t : 15; + } CMCTL_b; + }; + + union + { + __IOM uint32_t CSSCTL; /*!< (@ 0x0000006C) xSPI CS Size Control Register */ + + struct + { + __IOM uint32_t CS0SIZE : 6; /*!< [5..0] CS0 (slave0) size */ + uint32_t : 2; + __IOM uint32_t CS1SIZE : 6; /*!< [13..8] CS1 (slave1) size */ + uint32_t : 18; + } CSSCTL_b; + }; + + union + { + __IOM uint32_t CDCTL0; /*!< (@ 0x00000070) xSPI Command Manual Control Register 0 */ + + struct + { + __IOM uint32_t TRREQ : 1; /*!< [0..0] Transaction request */ + __IOM uint32_t PERMD : 1; /*!< [1..1] Periodic mode */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t TRNUM : 2; /*!< [5..4] Transaction number */ + uint32_t : 10; + __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval */ + uint32_t : 3; + __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat */ + uint32_t : 4; + } CDCTL0_b; + }; + + union + { + __IOM uint32_t CDCTL1; /*!< (@ 0x00000074) xSPI Command Manual Control Register 1 */ + + struct + { + __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value */ + } CDCTL1_b; + }; + + union + { + __IOM uint32_t CDCTL2; /*!< (@ 0x00000078) xSPI Command Manual Control Register 2 */ + + struct + { + __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value */ + } CDCTL2_b; + }; + __IM uint32_t RESERVED3; + __IOM R_XSPI0_BUF_Type BUF[4]; /*!< (@ 0x00000080) xSPI Command Manual Buf [0..3] */ + __IM uint32_t RESERVED4[16]; + + union + { + __IOM uint32_t LPCTL0; /*!< (@ 0x00000100) xSPI Link Pattern Control Register 0 */ + + struct + { + __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request */ + uint32_t : 2; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t XDPIN : 2; /*!< [5..4] XiP Disable pattern pin */ + uint32_t : 10; + __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length */ + uint32_t : 2; + __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value */ + __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length */ + uint32_t : 2; + __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value */ + } LPCTL0_b; + }; + + union + { + __IOM uint32_t LPCTL1; /*!< (@ 0x00000104) xSPI Link Pattern Control Register 1 */ + + struct + { + __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat */ + uint32_t : 2; + __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width */ + uint32_t : 1; + __IOM uint32_t RSTSU : 3; /*!< [14..12] Reset pattern data output setup time */ + uint32_t : 17; + } LPCTL1_b; + }; + + union + { + __IOM uint32_t LIOCTL; /*!< (@ 0x00000108) xSPI Link I/O Control Register */ + + struct + { + __IOM uint32_t WPCS0 : 1; /*!< [0..0] WP drive for slave0 */ + __IOM uint32_t WPCS1 : 1; /*!< [1..1] WP drive for slave1 */ + uint32_t : 14; + __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave0 */ + __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave1 */ + uint32_t : 14; + } LIOCTL_b; + }; + __IM uint32_t RESERVED5[9]; + __IOM R_XSPI0_CSb_Type CSb[2]; /*!< (@ 0x00000130) xSPI Command Calibration Control register [0..1] */ + __IM uint32_t RESERVED6[4]; + + union + { + __IM uint32_t VERSTT; /*!< (@ 0x00000180) xSPI Version Register */ + + struct + { + __IM uint32_t VER : 32; /*!< [31..0] Version */ + } VERSTT_b; + }; + + union + { + __IM uint32_t COMSTT; /*!< (@ 0x00000184) xSPI Common Status Register */ + + struct + { + __IM uint32_t MEMACC : 1; /*!< [0..0] Memory access ongoing */ + uint32_t : 3; + __IM uint32_t PBUFNE : 1; /*!< [4..4] Prefetch Buffer Not Empty */ + uint32_t : 1; + __IM uint32_t WRBUFNE : 1; /*!< [6..6] Write Buffer Not Empty */ + uint32_t : 9; + __IM uint32_t ECSCS0 : 1; /*!< [16..16] ECS monitor for slave0 */ + __IM uint32_t INTCS0 : 1; /*!< [17..17] INT monitor for slave0 */ + __IM uint32_t RSTOCS0 : 1; /*!< [18..18] RSTO monitor for slave0 */ + uint32_t : 1; + __IM uint32_t ECSCS1 : 1; /*!< [20..20] ECS monitor for slave1 */ + __IM uint32_t INTCS1 : 1; /*!< [21..21] INT monitor for slave1 */ + __IM uint32_t RSTOCS1 : 1; /*!< [22..22] RSTO monitor for slave1 */ + uint32_t : 9; + } COMSTT_b; + }; + + union + { + __IM uint32_t CASTTCS[2]; /*!< (@ 0x00000188) xSPI Calibration Status Register CSn */ + + struct + { + __IM uint32_t CASUC : 32; /*!< [31..0] Calibration Success */ + } CASTTCS_b[2]; + }; + + union + { + __IM uint32_t INTS; /*!< (@ 0x00000190) xSPI Interrupt Status Register */ + + struct + { + __IM uint32_t CMDCMP : 1; /*!< [0..0] Command Completed */ + __IM uint32_t PATCMP : 1; /*!< [1..1] Pattern Completed */ + __IM uint32_t INICMP : 1; /*!< [2..2] Initial Sequence Completed */ + __IM uint32_t PERTO : 1; /*!< [3..3] Periodic transaction timeout */ + __IM uint32_t DSTOCS0 : 1; /*!< [4..4] DS timeout for slave0 */ + __IM uint32_t DSTOCS1 : 1; /*!< [5..5] DS timeout for slave1 */ + uint32_t : 2; + __IM uint32_t ECSCS0 : 1; /*!< [8..8] ECC error detection for slave0 */ + __IM uint32_t ECSCS1 : 1; /*!< [9..9] ECC error detection for slave1 */ + uint32_t : 2; + __IM uint32_t INTCS0 : 1; /*!< [12..12] Interrupt detection for slave0 */ + __IM uint32_t INTCS1 : 1; /*!< [13..13] Interrupt detection for slave1 */ + uint32_t : 2; + __IM uint32_t BRGOF : 1; /*!< [16..16] Bridge Buffer overflow */ + uint32_t : 1; + __IM uint32_t BRGUF : 1; /*!< [18..18] Bridge Buffer underflow */ + uint32_t : 1; + __IM uint32_t BUSERR : 1; /*!< [20..20] AHB bus error */ + uint32_t : 7; + __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0 */ + __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1 */ + __IM uint32_t CASUCCS0 : 1; /*!< [30..30] Calibration success for slave0 */ + __IM uint32_t CASUCCS1 : 1; /*!< [31..31] Calibration success for slave1 */ + } INTS_b; + }; + + union + { + __OM uint32_t INTC; /*!< (@ 0x00000194) xSPI Interrupt Clear Register */ + + struct + { + __OM uint32_t CMDCMPC : 1; /*!< [0..0] Command Completed interrupt clear */ + __OM uint32_t PATCMPC : 1; /*!< [1..1] Pattern Completed interrupt clear */ + __OM uint32_t INICMPC : 1; /*!< [2..2] Initial Sequence Completed interrupt clear */ + __OM uint32_t PERTOC : 1; /*!< [3..3] Periodic transaction timeout interrupt clear */ + __OM uint32_t DSTOCS0C : 1; /*!< [4..4] DS timeout for slave0 interrupt clear */ + __OM uint32_t DSTOCS1C : 1; /*!< [5..5] DS timeout for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t ECSCS0C : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear */ + __OM uint32_t ECSCS1C : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t INTCS0C : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear */ + __OM uint32_t INTCS1C : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t BRGOFC : 1; /*!< [16..16] Bridge Buffer overflow interrupt clear */ + uint32_t : 1; + __OM uint32_t BRGUFC : 1; /*!< [18..18] Bridge Buffer underflow interrupt clear */ + uint32_t : 1; + __OM uint32_t BUSERRC : 1; /*!< [20..20] AHB bus error interrupt clear */ + uint32_t : 7; + __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear */ + __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear */ + __OM uint32_t CASUCCS0C : 1; /*!< [30..30] Calibration success for slave0 interrupt clear */ + __OM uint32_t CASUCCS1C : 1; /*!< [31..31] Calibration success for slave1 interrupt clear */ + } INTC_b; + }; + + union + { + __IOM uint32_t INTE; /*!< (@ 0x00000198) xSPI Interrupt Enable Register */ + + struct + { + __IOM uint32_t CMDCMPE : 1; /*!< [0..0] Command Completed interrupt enable */ + __IOM uint32_t PATCMPE : 1; /*!< [1..1] Pattern Completed interrupt enable */ + __IOM uint32_t INICMPE : 1; /*!< [2..2] Initial Sequence Completed interrupt enable */ + __IOM uint32_t PERTOE : 1; /*!< [3..3] Periodic transaction timeout interrupt enable */ + __IOM uint32_t DSTOCS0E : 1; /*!< [4..4] DS timeout for slave0 interrupt enable */ + __IOM uint32_t DSTOCS1E : 1; /*!< [5..5] DS timeout for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t ECSCS0E : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable */ + __IOM uint32_t ECSCS1E : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t INTCS0E : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable */ + __IOM uint32_t INTCS1E : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t BRGOFE : 1; /*!< [16..16] Bridge Buffer overflow interrupt enable */ + uint32_t : 1; + __IOM uint32_t BRGUFE : 1; /*!< [18..18] Bridge Buffer underflow interrupt enable */ + uint32_t : 1; + __IOM uint32_t BUSERRE : 1; /*!< [20..20] AHB bus error interrupt enable */ + uint32_t : 7; + __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable */ + __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable */ + __IOM uint32_t CASUCCS0E : 1; /*!< [30..30] Calibration success for slave0 interrupt enable */ + __IOM uint32_t CASUCCS1E : 1; /*!< [31..31] Calibration success for slave1 interrupt enable */ + } INTE_b; + }; +} R_XSPI0_Type; /*!< Size = 412 (0x19c) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSC_NS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Control for Non-safety region (R_SYSC_NS) + */ + +typedef struct /*!< (@ 0x80280000) R_SYSC_NS Structure */ +{ + union + { + __IOM uint32_t SCKCR; /*!< (@ 0x00000000) System Clock Control Register */ + + struct + { + __IOM uint32_t FSELXSPI0 : 3; /*!< [2..0] Set the frequency of the clock provided to xSPI Unit + * 0 in combination with bit 6 (DIVSELXSPI0). The combination + * is shown below. */ + uint32_t : 3; + __IOM uint32_t DIVSELXSPI0 : 1; /*!< [6..6] Select the base clock to generate serial clock for xSPI + * Unit 0 */ + uint32_t : 1; + __IOM uint32_t FSELXSPI1 : 3; /*!< [10..8] Set the frequency of the clock provided to xSPI Unit + * 1 in combination with bit 14 (DIVSELXSPI1). */ + uint32_t : 3; + __IOM uint32_t DIVSELXSPI1 : 1; /*!< [14..14] Select the base clock to generate serial clock for + * xSPI Unit 1 */ + uint32_t : 1; + __IOM uint32_t CKIO : 3; /*!< [18..16] Set the frequency of the external bus clock (CKIO) + * and the clock supplied to BSC in combination with the DIVSELSUB + * in the SCKCR2 register. The combination is shown below. */ + uint32_t : 1; + __IOM uint32_t FSELCANFD : 1; /*!< [20..20] Select the frequency of the clock supplied to CANFD */ + __IOM uint32_t PHYSEL : 1; /*!< [21..21] Select the Ethernet PHY reference clock output (ETHn_REFCLK, + * n = 0 to 2) */ + __IOM uint32_t CLMASEL : 1; /*!< [22..22] Select alternative clock when main clock abnormal oscillation + * is detected in CLMA3 */ + uint32_t : 1; + __IOM uint32_t SPI0ASYNCSEL : 1; /*!< [24..24] Select clock frequency when asynchronous serial clock + * is selected in SPI0 */ + __IOM uint32_t SPI1ASYNCSEL : 1; /*!< [25..25] Select clock frequency when asynchronous serial clock + * is selected in SPI1 */ + __IOM uint32_t SPI2ASYNCSEL : 1; /*!< [26..26] Select clock frequency when asynchronous serial clock + * is selected in SPI2 */ + __IOM uint32_t SCI0ASYNCSEL : 1; /*!< [27..27] Select clock frequency when asynchronous serial clock + * is selected in SCI0 */ + __IOM uint32_t SCI1ASYNCSEL : 1; /*!< [28..28] Select clock frequency when asynchronous serial clock + * is selected in SCI1 */ + __IOM uint32_t SCI2ASYNCSEL : 1; /*!< [29..29] Select clock frequency when asynchronous serial clock + * is selected in SCI2 */ + __IOM uint32_t SCI3ASYNCSEL : 1; /*!< [30..30] Select clock frequency when asynchronous serial clock + * is selected in SCI3 */ + __IOM uint32_t SCI4ASYNCSEL : 1; /*!< [31..31] Select clock frequency when asynchronous serial clock + * is selected in SCI4 */ + } SCKCR_b; + }; + __IM uint32_t RESERVED[127]; + + union + { + __IOM uint32_t RSTSR0; /*!< (@ 0x00000200) Reset Status Register 0 */ + + struct + { + uint32_t : 1; + __IOM uint32_t TRF : 1; /*!< [1..1] RES# Pin Reset Detect Flag */ + __IOM uint32_t ERRF : 1; /*!< [2..2] Error Reset Detect Flag */ + __IOM uint32_t SWRSF : 1; /*!< [3..3] System Software Reset Detect Flag */ + __IOM uint32_t SWR0F : 1; /*!< [4..4] CPU0 Software Reset Detect Flag */ + __IOM uint32_t SWR1F : 1; /*!< [5..5] CPU1 Software Reset Detect Flag */ + uint32_t : 26; + } RSTSR0_b; + }; + __IM uint32_t RESERVED1[15]; + + union + { + __IOM uint32_t MRCTLA; /*!< (@ 0x00000240) Module Reset Control Register A */ + + struct + { + uint32_t : 4; + __IOM uint32_t MRCTLA04 : 1; /*!< [4..4] xSPI Unit 0 Reset Control */ + __IOM uint32_t MRCTLA05 : 1; /*!< [5..5] xSPI Unit 1 Reset Control */ + uint32_t : 26; + } MRCTLA_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MRCTLE; /*!< (@ 0x00000250) Module Reset Control Register E */ + + struct + { + __IOM uint32_t MRCTLE00 : 1; /*!< [0..0] GMAC (PCLKH clock domain) Reset Control */ + __IOM uint32_t MRCTLE01 : 1; /*!< [1..1] GMAC (PCLKM clock domain) Reset Control */ + __IOM uint32_t MRCTLE02 : 1; /*!< [2..2] ETHSW Reset Control */ + __IOM uint32_t MRCTLE03 : 1; /*!< [3..3] ESC (Bus clock domain) Reset Control */ + __IOM uint32_t MRCTLE04 : 1; /*!< [4..4] ESC (IP clock domain) Reset Control */ + __IOM uint32_t MRCTLE05 : 1; /*!< [5..5] Ethernet Subsystem Register Reset Control */ + __IOM uint32_t MRCTLE06 : 1; /*!< [6..6] MII Converter Reset Control */ + uint32_t : 25; + } MRCTLE_b; + }; + __IM uint32_t RESERVED3[43]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000300) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPCRA00 : 1; /*!< [0..0] BSC Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPCRA04 : 1; /*!< [4..4] xSPI Unit 0 Module Stop */ + __IOM uint32_t MSTPCRA05 : 1; /*!< [5..5] xSPI Unit 1 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPCRA08 : 1; /*!< [8..8] SCI Unit 0 Module Stop */ + __IOM uint32_t MSTPCRA09 : 1; /*!< [9..9] SCI Unit 1 Module Stop */ + __IOM uint32_t MSTPCRA10 : 1; /*!< [10..10] SCI Unit 2 Module Stop */ + __IOM uint32_t MSTPCRA11 : 1; /*!< [11..11] SCI Unit 3 Module Stop */ + __IOM uint32_t MSTPCRA12 : 1; /*!< [12..12] SCI Unit 4 Module Stop */ + uint32_t : 19; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000304) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPCRB00 : 1; /*!< [0..0] IIC Unit 0 Module Stop */ + __IOM uint32_t MSTPCRB01 : 1; /*!< [1..1] IIC Unit 1 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPCRB04 : 1; /*!< [4..4] SPI Unit 0 Module Stop */ + __IOM uint32_t MSTPCRB05 : 1; /*!< [5..5] SPI Unit 1 Module Stop */ + __IOM uint32_t MSTPCRB06 : 1; /*!< [6..6] SPI Unit 2 Module Stop */ + uint32_t : 25; + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000308) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPCRC00 : 1; /*!< [0..0] MTU3 Module Stop */ + __IOM uint32_t MSTPCRC01 : 1; /*!< [1..1] GPT Unit 0 Module Stop */ + __IOM uint32_t MSTPCRC02 : 1; /*!< [2..2] GPT Unit 1 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPCRC05 : 1; /*!< [5..5] TFU Module Stop */ + __IOM uint32_t MSTPCRC06 : 1; /*!< [6..6] ADC12 Unit 0 Module Stop */ + __IOM uint32_t MSTPCRC07 : 1; /*!< [7..7] ADC12 Unit 1 Module Stop */ + uint32_t : 24; + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000030C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPCRD00 : 1; /*!< [0..0] DSMIF Unit 0 Module Stop */ + __IOM uint32_t MSTPCRD01 : 1; /*!< [1..1] DSMIF Unit 1 Module Stop */ + __IOM uint32_t MSTPCRD02 : 1; /*!< [2..2] CMT Unit 0 Module Stop */ + __IOM uint32_t MSTPCRD03 : 1; /*!< [3..3] CMT Unit 1 Module Stop */ + __IOM uint32_t MSTPCRD04 : 1; /*!< [4..4] CMT Unit 2 Module Stop */ + __IOM uint32_t MSTPCRD05 : 1; /*!< [5..5] CMTW Unit 0 Module Stop */ + __IOM uint32_t MSTPCRD06 : 1; /*!< [6..6] CMTW Unit 1 Module Stop */ + __IOM uint32_t MSTPCRD07 : 1; /*!< [7..7] TSU Module Stop */ + __IOM uint32_t MSTPCRD08 : 1; /*!< [8..8] DOC Module Stop */ + __IOM uint32_t MSTPCRD09 : 1; /*!< [9..9] CRC Unit 0 Module Stop */ + __IOM uint32_t MSTPCRD10 : 1; /*!< [10..10] CANFD Module Stop */ + __IOM uint32_t MSTPCRD11 : 1; /*!< [11..11] CKIO Module Stop */ + uint32_t : 20; + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000310) Module Stop Control Register E */ + + struct + { + __IOM uint32_t MSTPCRE00 : 1; /*!< [0..0] GMAC Module Stop */ + __IOM uint32_t MSTPCRE01 : 1; /*!< [1..1] ETHSW Module Stop */ + __IOM uint32_t MSTPCRE02 : 1; /*!< [2..2] ESC Module Stop */ + __IOM uint32_t MSTPCRE03 : 1; /*!< [3..3] Ethernet Subsystem Register Module Stop */ + __IOM uint32_t MSTPCRE04 : 1; /*!< [4..4] Encoder Interface Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPCRE08 : 1; /*!< [8..8] USB Module Stop */ + uint32_t : 23; + } MSTPCRE_b; + }; + __IM uint32_t RESERVED4[891]; + + union + { + __IM uint32_t MD_MON; /*!< (@ 0x00001100) Operating Mode Monitor Register */ + + struct + { + __IM uint32_t MDDMON : 1; /*!< [0..0] MDD status flag */ + uint32_t : 3; + __IM uint32_t MDWMON : 1; /*!< [4..4] MDW status flag */ + uint32_t : 3; + __IM uint32_t MDP : 2; /*!< [9..8] Package type */ + uint32_t : 2; + __IM uint32_t MD0MON : 1; /*!< [12..12] MD0 pin status flag */ + __IM uint32_t MD1MON : 1; /*!< [13..13] MD1 pin status flag */ + __IM uint32_t MD2MON : 1; /*!< [14..14] MD2 pin status flag */ + uint32_t : 1; + __IM uint32_t MDV0MON : 1; /*!< [16..16] MDV0 status flag (ETH0 domain) */ + __IM uint32_t MDV1MON : 1; /*!< [17..17] MDV1 status flag (ETH1 domain) */ + __IM uint32_t MDV2MON : 1; /*!< [18..18] MDV2 status flag (ETH2 domain) */ + __IM uint32_t MDV3MON : 1; /*!< [19..19] MDV3 status flag (xSPI0 domain) */ + __IM uint32_t MDV4MON : 1; /*!< [20..20] MDV4 status flag (xSPI1 domain) */ + uint32_t : 11; + } MD_MON_b; + }; +} R_SYSC_NS_Type; /*!< Size = 4356 (0x1104) */ + +/* =========================================================================================================================== */ +/* ================ R_SEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Semaphore (R_SEM) + */ + +typedef struct /*!< (@ 0x80281000) R_SEM Structure */ +{ + union + { + __IOM uint32_t SYTSEMFEN; /*!< (@ 0x00000000) Semaphore Enable Register */ + + struct + { + __IOM uint32_t SEMFEN : 1; /*!< [0..0] Semaphore Enable */ + uint32_t : 31; + } SYTSEMFEN_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SYTSEMF[8]; /*!< (@ 0x00000010) Semaphore Register [0..7] */ + + struct + { + __IOM uint32_t SEMF : 1; /*!< [0..0] Semaphore */ + uint32_t : 31; + } SYTSEMF_b[8]; + }; +} R_SEM_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_ELO ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Evnet Link Option Setting (R_ELO) + */ + +typedef struct /*!< (@ 0x80281200) R_ELO Structure */ +{ + union + { + __IOM uint32_t ELOPA; /*!< (@ 0x00000000) Event Link Option Setting Register A */ + + struct + { + __IOM uint32_t MTU0MD : 2; /*!< [1..0] MTU0 Operation Select */ + uint32_t : 4; + __IOM uint32_t MTU3MD : 2; /*!< [7..6] MTU3 Operation Select */ + uint32_t : 24; + } ELOPA_b; + }; + + union + { + __IOM uint32_t ELOPB; /*!< (@ 0x00000004) Event Link Option Setting Register B */ + + struct + { + __IOM uint32_t MTU4MD : 2; /*!< [1..0] MTU4 Operation Select */ + uint32_t : 30; + } ELOPB_b; + }; +} R_ELO_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_RWP_NS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Register Write Protection for Non-safety Area (R_RWP_NS) + */ + +typedef struct /*!< (@ 0x80281A10) R_RWP_NS Structure */ +{ + union + { + __IOM uint32_t PRCRN; /*!< (@ 0x00000000) Non_Safety Area Protect Register */ + + struct + { + __IOM uint32_t PRC0 : 1; /*!< [0..0] Protect 0 */ + __IOM uint32_t PRC1 : 1; /*!< [1..1] Protect 1 */ + __IOM uint32_t PRC2 : 1; /*!< [2..2] Protect 2 */ + uint32_t : 5; + __OM uint32_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + uint32_t : 16; + } PRCRN_b; + }; +} R_RWP_NS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Real Time Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x81009000) R_RTC Structure */ +{ + union + { + __IOM uint32_t RTCA0CTL0; /*!< (@ 0x00000000) RTC Control Register 0 */ + + struct + { + uint32_t : 4; + __IOM uint32_t RTCA0SLSB : 1; /*!< [4..4] RTCA0SCMP enable/disable setting */ + __IOM uint32_t RTCA0AMPM : 1; /*!< [5..5] RTCA0HOUR, RTCA0ALH display format selection bit */ + __IM uint32_t RTCA0CEST : 1; /*!< [6..6] RTC Controller Enable Status */ + __IOM uint32_t RTCA0CE : 1; /*!< [7..7] RTC Controller Enable Bit */ + uint32_t : 24; + } RTCA0CTL0_b; + }; + + union + { + __IOM uint32_t RTCA0CTL1; /*!< (@ 0x00000004) RTC Control Register 1 */ + + struct + { + __IOM uint32_t RTCA0CT : 3; /*!< [2..0] Fixed interval interrupt (RTC_PRD) output setting bit */ + __IOM uint32_t RTCA01SE : 1; /*!< [3..3] 1 second interrupt (RTC_1S) output enable bit */ + __IOM uint32_t RTCA0ALME : 1; /*!< [4..4] Alarm interrupt (RTC_ALM) output enable bit */ + __IOM uint32_t RTCA01HZE : 1; /*!< [5..5] This bit enables/disables 1 Hz pulse output (RTCAT1HZ). */ + uint32_t : 26; + } RTCA0CTL1_b; + }; + + union + { + __IOM uint32_t RTCA0CTL2; /*!< (@ 0x00000008) RTC Control Register 2 */ + + struct + { + __IOM uint32_t RTCA0WAIT : 1; /*!< [0..0] RTC Controller Counter Wait Control */ + __IM uint32_t RTCA0WST : 1; /*!< [1..1] RTC Controller Counter Wait Status */ + __IOM uint32_t RTCA0RSUB : 1; /*!< [2..2] RTCA0SUBC Data Transfer Control */ + __IM uint32_t RTCA0RSST : 1; /*!< [3..3] RTCA0SRBU Transfer Status */ + __IM uint32_t RTCA0WSST : 1; /*!< [4..4] RTCA0SCMP Write Status */ + uint32_t : 27; + } RTCA0CTL2_b; + }; + + union + { + __IM uint32_t RTCA0SUBC; /*!< (@ 0x0000000C) RTC Sub Count Register */ + + struct + { + __IM uint32_t RTCA0SUBC : 22; /*!< [21..0] Register that counts the 1 second reference time */ + uint32_t : 10; + } RTCA0SUBC_b; + }; + + union + { + __IM uint32_t RTCA0SRBU; /*!< (@ 0x00000010) RTC Sub Count Register Read Buffer */ + + struct + { + __IM uint32_t RTCA0SRBU : 22; /*!< [21..0] Read buffer register of RTCA0SUBC */ + uint32_t : 10; + } RTCA0SRBU_b; + }; + + union + { + __IOM uint32_t RTCA0SEC; /*!< (@ 0x00000014) RTC Sec Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0SEC : 7; /*!< [6..0] Buffer register to read/write RTC Second Count register + * (RTCA0SECC). */ + uint32_t : 25; + } RTCA0SEC_b; + }; + + union + { + __IOM uint32_t RTCA0MIN; /*!< (@ 0x00000018) RTC Min Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0MIN : 7; /*!< [6..0] Buffer register to read/write RTC Minute Count register + * (RTCA0MINC). */ + uint32_t : 25; + } RTCA0MIN_b; + }; + + union + { + __IOM uint32_t RTCA0HOUR; /*!< (@ 0x0000001C) RTC Hour Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0HOUR : 6; /*!< [5..0] Buffer register to read/write RTC Hour Count register + * (RTCA0HOURC). */ + uint32_t : 26; + } RTCA0HOUR_b; + }; + + union + { + __IOM uint32_t RTCA0WEEK; /*!< (@ 0x00000020) RTC Week Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0WEEK : 3; /*!< [2..0] Buffer register to read/write RTC Week Count register + * (RTCA0WEEKC). */ + uint32_t : 29; + } RTCA0WEEK_b; + }; + + union + { + __IOM uint32_t RTCA0DAY; /*!< (@ 0x00000024) RTC Day Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0DAY : 6; /*!< [5..0] Buffer register to read/write RTC Day Count register + * (RTCA0DAYC). */ + uint32_t : 26; + } RTCA0DAY_b; + }; + + union + { + __IOM uint32_t RTCA0MONTH; /*!< (@ 0x00000028) RTC Month Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0MONTH : 5; /*!< [4..0] Buffer register to read/write RTC Month Count register + * (RTCA0MONC). */ + uint32_t : 27; + } RTCA0MONTH_b; + }; + + union + { + __IOM uint32_t RTCA0YEAR; /*!< (@ 0x0000002C) RTC Year Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0YEAR : 8; /*!< [7..0] Buffer register to read/write RTC Year Count register + * (RTCA0YEARC). */ + uint32_t : 24; + } RTCA0YEAR_b; + }; + + union + { + __IOM uint32_t RTCA0TIME; /*!< (@ 0x00000030) RTC Time Set Register */ + + struct + { + __IOM uint32_t RTCA0SEC : 8; /*!< [7..0] See RTCA0SEC register */ + __IOM uint32_t RTCA0MIN : 8; /*!< [15..8] See RTCA0MIN register */ + __IOM uint32_t RTCA0HOUR : 8; /*!< [23..16] See RTCA0HOUR register */ + uint32_t : 8; + } RTCA0TIME_b; + }; + + union + { + __IOM uint32_t RTCA0CAL; /*!< (@ 0x00000034) RTC Calendar Set Register */ + + struct + { + __IOM uint32_t RTCA0WEEK : 8; /*!< [7..0] See RTCA0WEEK register */ + __IOM uint32_t RTCA0DAY : 8; /*!< [15..8] See RTCA0DAY register */ + __IOM uint32_t RTCA0MONTH : 8; /*!< [23..16] See RTCA0MONTH register */ + __IOM uint32_t RTCA0YEAR : 8; /*!< [31..24] See RTCA0YEAR register */ + } RTCA0CAL_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t RTCA0SCMP; /*!< (@ 0x0000003C) RTC Sub Count Compare Register */ + + struct + { + __IOM uint32_t RTCA0SCMP : 22; /*!< [21..0] Register that sets the compare value of RTCA0SUBC (sub-counter). */ + uint32_t : 10; + } RTCA0SCMP_b; + }; + + union + { + __IOM uint32_t RTCA0ALM; /*!< (@ 0x00000040) RTC Alarm Min Set Register */ + + struct + { + __IOM uint32_t RTCA0ALM : 7; /*!< [6..0] RTCA0ALM is a register that performs the minute setting + * for the alarm interrupt. */ + uint32_t : 25; + } RTCA0ALM_b; + }; + + union + { + __IOM uint32_t RTCA0ALH; /*!< (@ 0x00000044) RTC Alarm Hour Set Register */ + + struct + { + __IOM uint32_t RTCA0ALH : 6; /*!< [5..0] RTCA0ALH is a register that performs the hour setting + * for the alarm interrupt. */ + uint32_t : 26; + } RTCA0ALH_b; + }; + + union + { + __IOM uint32_t RTCA0ALW; /*!< (@ 0x00000048) RTC Alarm Week Set Register */ + + struct + { + __IOM uint32_t RTCA0ALW0 : 1; /*!< [0..0] Alarm interrupt day of the week setting bit 0 */ + __IOM uint32_t RTCA0ALW1 : 1; /*!< [1..1] Alarm interrupt day of the week setting bit 1 */ + __IOM uint32_t RTCA0ALW2 : 1; /*!< [2..2] Alarm interrupt day of the week setting bit 2 */ + __IOM uint32_t RTCA0ALW3 : 1; /*!< [3..3] Alarm interrupt day of the week setting bit 3 */ + __IOM uint32_t RTCA0ALW4 : 1; /*!< [4..4] Alarm interrupt day of the week setting bit 4 */ + __IOM uint32_t RTCA0ALW5 : 1; /*!< [5..5] Alarm interrupt day of the week setting bit 5 */ + __IOM uint32_t RTCA0ALW6 : 1; /*!< [6..6] Alarm interrupt day of the week setting bit 6 */ + uint32_t : 25; + } RTCA0ALW_b; + }; + + union + { + __IM uint32_t RTCA0SECC; /*!< (@ 0x0000004C) RTC Second Count Register */ + + struct + { + __IM uint32_t RTCA0SECC : 7; /*!< [6..0] Counts up the seconds */ + uint32_t : 25; + } RTCA0SECC_b; + }; + + union + { + __IM uint32_t RTCA0MINC; /*!< (@ 0x00000050) RTC Minute Count Register */ + + struct + { + __IM uint32_t RTCA0MINC : 7; /*!< [6..0] Counts up the minutes */ + uint32_t : 25; + } RTCA0MINC_b; + }; + + union + { + __IM uint32_t RTCA0HOURC; /*!< (@ 0x00000054) RTC Hour Count Register */ + + struct + { + __IM uint32_t RTCA0HOURC : 6; /*!< [5..0] Counts up the hours */ + uint32_t : 26; + } RTCA0HOURC_b; + }; + + union + { + __IM uint32_t RTCA0WEEKC; /*!< (@ 0x00000058) RTC Week Count Register */ + + struct + { + __IM uint32_t RTCA0WEEKC : 3; /*!< [2..0] Counts up the weeks */ + uint32_t : 29; + } RTCA0WEEKC_b; + }; + + union + { + __IM uint32_t RTCA0DAYC; /*!< (@ 0x0000005C) RTC Day Count Register */ + + struct + { + __IM uint32_t RTCA0DAYC : 6; /*!< [5..0] Counts up the days */ + uint32_t : 26; + } RTCA0DAYC_b; + }; + + union + { + __IM uint32_t RTCA0MONC; /*!< (@ 0x00000060) RTC Month Count Register */ + + struct + { + __IM uint32_t RTCA0MONC : 5; /*!< [4..0] Counts up the months */ + uint32_t : 27; + } RTCA0MONC_b; + }; + + union + { + __IM uint32_t RTCA0YEARC; /*!< (@ 0x00000064) RTC Year Count Register */ + + struct + { + __IM uint32_t RTCA0YEARC : 8; /*!< [7..0] Counts up the years */ + uint32_t : 24; + } RTCA0YEARC_b; + }; + + union + { + __IM uint32_t RTCA0TIMEC; /*!< (@ 0x00000068) RTC Time Count Register */ + + struct + { + __IM uint32_t RTCA0SECC : 8; /*!< [7..0] See RTCA0SECC register */ + __IM uint32_t RTCA0MINC : 8; /*!< [15..8] See RTCA0MINC register */ + __IM uint32_t RTCA0HOURC : 8; /*!< [23..16] See RTCA0HOURC register */ + uint32_t : 8; + } RTCA0TIMEC_b; + }; + + union + { + __IM uint32_t RTCA0CALC; /*!< (@ 0x0000006C) RTC Calendar Count Register */ + + struct + { + __IM uint32_t RTCA0WEEKC : 8; /*!< [7..0] See RTCA0WEEKC register */ + __IM uint32_t RTCA0DAYC : 8; /*!< [15..8] See RTCA0DAYC register */ + __IM uint32_t RTCA0MONC : 8; /*!< [23..16] See RTCA0MONC register */ + __IM uint32_t RTCA0YEARC : 8; /*!< [31..24] See RTCA0YEARC register */ + } RTCA0CALC_b; + }; +} R_RTC_Type; /*!< Size = 112 (0x70) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG2 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GPT Port Output Enable 2 (R_POEG2) + */ + +typedef struct /*!< (@ 0x8100A000) R_POEG2 Structure */ +{ + union + { + __IOM uint32_t POEG2GA; /*!< (@ 0x00000000) POEG2 Group A Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG2GA_b; + }; + __IM uint32_t RESERVED[255]; + + union + { + __IOM uint32_t POEG2GB; /*!< (@ 0x00000400) POEG2 Group B Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG2GB_b; + }; + __IM uint32_t RESERVED1[255]; + + union + { + __IOM uint32_t POEG2GC; /*!< (@ 0x00000800) POEG2 Group C Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG2GC_b; + }; + __IM uint32_t RESERVED2[255]; + + union + { + __IOM uint32_t POEG2GD; /*!< (@ 0x00000C00) POEG2 Group D Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG2GD_b; + }; +} R_POEG2_Type; /*!< Size = 3076 (0xc04) */ + +/* =========================================================================================================================== */ +/* ================ R_OTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief One-Time Programmable Memory (R_OTP) + */ + +typedef struct /*!< (@ 0x81028000) R_OTP Structure */ +{ + union + { + __IOM uint32_t OTPPWR; /*!< (@ 0x00000000) OTP Power Control Register */ + + struct + { + __IOM uint32_t PWR : 1; /*!< [0..0] OTP power on/off setting */ + uint32_t : 3; + __IOM uint32_t ACCL : 1; /*!< [4..4] Selects OTP access I/F */ + uint32_t : 27; + } OTPPWR_b; + }; + + union + { + __IOM uint32_t OTPSTR; /*!< (@ 0x00000004) OTP Access Status Register */ + + struct + { + __IM uint32_t CMD_RDY : 1; /*!< [0..0] Indicates whether OTP controller is ready to receive + * command or not. */ + __IM uint32_t ERR_WR : 2; /*!< [2..1] OTP write status */ + __IM uint32_t ERR_WP : 1; /*!< [3..3] Write protection error */ + __IM uint32_t ERR_RP : 1; /*!< [4..4] Read protection error */ + uint32_t : 3; + __IOM uint32_t ERR_RDY_WR : 1; /*!< [8..8] OTP write command ready error */ + __IOM uint32_t ERR_RDY_RD : 1; /*!< [9..9] OTP read command ready error */ + uint32_t : 5; + __IM uint32_t CNT_ST_IDLE : 1; /*!< [15..15] Indicates status of OTP controller */ + uint32_t : 16; + } OTPSTR_b; + }; + + union + { + __IOM uint32_t OTPSTAWR; /*!< (@ 0x00000008) OTP Write Command Register */ + + struct + { + __IOM uint32_t STAWR : 1; /*!< [0..0] OTP write start */ + uint32_t : 31; + } OTPSTAWR_b; + }; + + union + { + __IOM uint32_t OTPADRWR; /*!< (@ 0x0000000C) OTP Write Address Register */ + + struct + { + __IOM uint32_t ADRWR : 9; /*!< [8..0] OTP write address */ + uint32_t : 23; + } OTPADRWR_b; + }; + + union + { + __IOM uint32_t OTPDATAWR; /*!< (@ 0x00000010) OTP Write Data Register */ + + struct + { + __IOM uint32_t DATAWR : 16; /*!< [15..0] OTP write data */ + uint32_t : 16; + } OTPDATAWR_b; + }; + + union + { + __IOM uint32_t OTPADRRD; /*!< (@ 0x00000014) OTP Read Address Register */ + + struct + { + __IOM uint32_t ADRRD : 9; /*!< [8..0] OTP read address */ + uint32_t : 23; + } OTPADRRD_b; + }; + + union + { + __IM uint32_t OTPDATARD; /*!< (@ 0x00000018) OTP Read Data Register */ + + struct + { + __IM uint32_t DATARD : 16; /*!< [15..0] OTP read data */ + uint32_t : 16; + } OTPDATARD_b; + }; +} R_OTP_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== */ +/* ================ R_PTADR ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Address Selection (R_PTADR) + */ + +typedef struct /*!< (@ 0x81030C00) R_PTADR Structure */ +{ + union + { + __IOM uint8_t RSELP[25]; /*!< (@ 0x00000000) Port [0..24] Region Select Register */ + + struct + { + __IOM uint8_t RS0 : 1; /*!< [0..0] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS1 : 1; /*!< [1..1] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS2 : 1; /*!< [2..2] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS3 : 1; /*!< [3..3] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS4 : 1; /*!< [4..4] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS5 : 1; /*!< [5..5] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS6 : 1; /*!< [6..6] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS7 : 1; /*!< [7..7] Pm_n pin I/O port registers Region Select (n = bit position) */ + } RSELP_b[25]; + }; +} R_PTADR_Type; /*!< Size = 25 (0x19) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSRAM0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System SRAM 0 (R_SYSRAM0) + */ + +typedef struct /*!< (@ 0x81040000) R_SYSRAM0 Structure */ +{ + __IOM R_SYSRAM0_W_Type W[4]; /*!< (@ 0x00000000) System SRAM Wn Registers (n = 0 to 3) */ +} R_SYSRAM0_Type; /*!< Size = 256 (0x100) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller (R_ICU) + */ + +typedef struct /*!< (@ 0x81048000) R_ICU Structure */ +{ + union + { + __OM uint32_t S_SWINT; /*!< (@ 0x00000000) Software Interrupt Register for Safety Register */ + + struct + { + __OM uint32_t IC6 : 1; /*!< [0..0] Software Interrupt register */ + __OM uint32_t IC7 : 1; /*!< [1..1] Software Interrupt register */ + uint32_t : 30; + } S_SWINT_b; + }; + + union + { + __IOM uint32_t S_PORTNF_FLTSEL; /*!< (@ 0x00000004) Interrupt Noise Filter Enable Register for Safety + * Register */ + + struct + { + __IOM uint32_t FLT14 : 1; /*!< [0..0] Noise filter enable for IRQ14 */ + __IOM uint32_t FLT15 : 1; /*!< [1..1] Noise filter enable for IRQ15 */ + __IOM uint32_t FLTNMI : 1; /*!< [2..2] Noise filter enable for NMI */ + uint32_t : 29; + } S_PORTNF_FLTSEL_b; + }; + + union + { + __IOM uint32_t S_PORTNF_CLKSEL; /*!< (@ 0x00000008) Interrupt Noise Filter Setting Register for Safety + * Register */ + + struct + { + __IOM uint32_t CKSEL14 : 2; /*!< [1..0] Select noise filter sampling frequency dividend rate + * for IRQ14. */ + __IOM uint32_t CKSEL15 : 2; /*!< [3..2] Select noise filter sampling frequency dividend rate + * for IRQ15. */ + __IOM uint32_t CKSELNMI : 2; /*!< [5..4] Select noise filter sampling frequency dividend rate + * for NMI. */ + uint32_t : 26; + } S_PORTNF_CLKSEL_b; + }; + + union + { + __IOM uint32_t S_PORTNF_MD; /*!< (@ 0x0000000C) Interrupt Edge Detection Setting Register for + * Safety Register */ + + struct + { + __IOM uint32_t MD14 : 2; /*!< [1..0] Select detection mode for IRQ14 */ + __IOM uint32_t MD15 : 2; /*!< [3..2] Select detection mode for IRQ15 */ + __IOM uint32_t MDNMI : 2; /*!< [5..4] Select detection mode for NMI */ + uint32_t : 26; + } S_PORTNF_MD_b; + }; + __IM uint32_t RESERVED[20]; + + union + { + __IM uint32_t CPU0ERR_STAT; /*!< (@ 0x00000060) CPU0 Error Event Status Register */ + + struct + { + __IM uint32_t ER_ST0 : 1; /*!< [0..0] Indicate captured error status for CPU0_ERREVENT0 */ + __IM uint32_t ER_ST1 : 1; /*!< [1..1] Indicate captured error status for CPU0_ERREVENT1 */ + __IM uint32_t ER_ST2 : 1; /*!< [2..2] Indicate captured error status for CPU0_ERREVENT2 */ + __IM uint32_t ER_ST3 : 1; /*!< [3..3] Indicate captured error status for CPU0_ERREVENT3 */ + __IM uint32_t ER_ST4 : 1; /*!< [4..4] Indicate captured error status for CPU0_ERREVENT4 */ + __IM uint32_t ER_ST5 : 1; /*!< [5..5] Indicate captured error status for CPU0_ERREVENT5 */ + __IM uint32_t ER_ST6 : 1; /*!< [6..6] Indicate captured error status for CPU0_ERREVENT6 */ + __IM uint32_t ER_ST7 : 1; /*!< [7..7] Indicate captured error status for CPU0_ERREVENT7 */ + __IM uint32_t ER_ST8 : 1; /*!< [8..8] Indicate captured error status for CPU0_ERREVENT8 */ + __IM uint32_t ER_ST9 : 1; /*!< [9..9] Indicate captured error status for CPU0_ERREVENT9 */ + __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate captured error status for CPU0_ERREVENT10 */ + __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate captured error status for CPU0_ERREVENT11 */ + __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate captured error status for CPU0_ERREVENT12 */ + __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for CPU0_ERREVENT13 */ + __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate captured error status for CPU0_ERREVENT14 */ + __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for CPU0_ERREVENT15 */ + __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for CPU0_ERREVENT16 */ + __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for CPU0_ERREVENT17 */ + __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for CPU0_ERREVENT18 */ + __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for CPU0_ERREVENT19 */ + __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for CPU0_ERREVENT20 */ + __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for CPU0_ERREVENT21 */ + __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for CPU0_ERREVENT22 */ + __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for CPU0_ERREVENT23 */ + __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for CPU0_ERREVENT24 */ + __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate captured error status for CPU0_ERREVENT25 */ + uint32_t : 6; + } CPU0ERR_STAT_b; + }; + + union + { + __IM uint32_t CPU1ERR_STAT; /*!< (@ 0x00000064) CPU1 Error Event Status Register */ + + struct + { + __IM uint32_t ER_ST0 : 1; /*!< [0..0] Indicate captured error status for CPU1_ERREVENT0 */ + __IM uint32_t ER_ST1 : 1; /*!< [1..1] Indicate captured error status for CPU1_ERREVENT1 */ + __IM uint32_t ER_ST2 : 1; /*!< [2..2] Indicate captured error status for CPU1_ERREVENT2 */ + __IM uint32_t ER_ST3 : 1; /*!< [3..3] Indicate captured error status for CPU1_ERREVENT3 */ + __IM uint32_t ER_ST4 : 1; /*!< [4..4] Indicate captured error status for CPU1_ERREVENT4 */ + __IM uint32_t ER_ST5 : 1; /*!< [5..5] Indicate captured error status for CPU1_ERREVENT5 */ + __IM uint32_t ER_ST6 : 1; /*!< [6..6] Indicate captured error status for CPU1_ERREVENT6 */ + __IM uint32_t ER_ST7 : 1; /*!< [7..7] Indicate captured error status for CPU1_ERREVENT7 */ + __IM uint32_t ER_ST8 : 1; /*!< [8..8] Indicate captured error status for CPU1_ERREVENT8 */ + __IM uint32_t ER_ST9 : 1; /*!< [9..9] Indicate captured error status for CPU1_ERREVENT9 */ + __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate captured error status for CPU1_ERREVENT10 */ + __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate captured error status for CPU1_ERREVENT11 */ + __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate captured error status for CPU1_ERREVENT12 */ + __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for CPU1_ERREVENT13 */ + __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate captured error status for CPU1_ERREVENT14 */ + __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for CPU1_ERREVENT15 */ + __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for CPU1_ERREVENT16 */ + __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for CPU1_ERREVENT17 */ + __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for CPU1_ERREVENT18 */ + __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for CPU1_ERREVENT19 */ + __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for CPU1_ERREVENT20 */ + __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for CPU1_ERREVENT21 */ + __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for CPU1_ERREVENT22 */ + __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for CPU1_ERREVENT23 */ + __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for CPU1_ERREVENT24 */ + __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate captured error status for CPU1_ERREVENT25 */ + uint32_t : 6; + } CPU1ERR_STAT_b; + }; + + union + { + __IM uint32_t PERIERR_STAT0; /*!< (@ 0x00000068) Peripheral Error Event Status Register 0 */ + + struct + { + __IM uint32_t ER_ST0 : 1; /*!< [0..0] Indicate captured error status for CLMA3_INT */ + __IM uint32_t ER_ST1 : 1; /*!< [1..1] Indicate captured error status for CLMA0_INT */ + __IM uint32_t ER_ST2 : 1; /*!< [2..2] Indicate captured error status for CLMA1_INT */ + __IM uint32_t ER_ST3 : 1; /*!< [3..3] Indicate captured error status for CLMA2_INT */ + __IM uint32_t ER_ST4 : 1; /*!< [4..4] Indicate captured error status for BSC_WTO */ + __IM uint32_t ER_ST5 : 1; /*!< [5..5] Indicate captured error status for DMAC0_ERR */ + __IM uint32_t ER_ST6 : 1; /*!< [6..6] Indicate captured error status for DMAC1_ERR */ + __IM uint32_t ER_ST7 : 1; /*!< [7..7] Indicate captured error status for WDT_NMIUNDF0 */ + __IM uint32_t ER_ST8 : 1; /*!< [8..8] Indicate captured error status for WDT_NMIUNDF1 */ + __IM uint32_t ER_ST9 : 1; /*!< [9..9] Indicate captured error status for USB_FDMAERR */ + __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate captured error status for DSMIF0_LTCSE */ + __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate captured error status for DSMIF0_UTCSE */ + __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate captured error status for DSMIF0_LTODE0 */ + __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for DSMIF0_LTODE1 */ + __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate captured error status for DSMIF0_LTODE2 */ + __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for DSMIF0_UTODE0 */ + __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for DSMIF0_UTODE1 */ + __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for DSMIF0_UTODE2 */ + __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for DSMIF0_SCDE0 */ + __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for DSMIF0_SCDE1 */ + __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for DSMIF0_SCDE2 */ + __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for DSMIF1_LTCSE */ + __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for DSMIF1_UTCSE */ + __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for DSMIF1_LTODE0 */ + __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for DSMIF1_LTODE1 */ + __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate captured error status for DSMIF1_LTODE2 */ + __IM uint32_t ER_ST26 : 1; /*!< [26..26] Indicate captured error status for DSMIF1_UTODE0 */ + __IM uint32_t ER_ST27 : 1; /*!< [27..27] Indicate captured error status for DSMIF1_UTODE1 */ + __IM uint32_t ER_ST28 : 1; /*!< [28..28] Indicate captured error status for DSMIF1_UTODE2 */ + __IM uint32_t ER_ST29 : 1; /*!< [29..29] Indicate captured error status for DSMIF1_SCDE0 */ + __IM uint32_t ER_ST30 : 1; /*!< [30..30] Indicate captured error status for DSMIF1_SCDE1 */ + __IM uint32_t ER_ST31 : 1; /*!< [31..31] Indicate captured error status for DSMIF1_SCDE2 */ + } PERIERR_STAT0_b; + }; + + union + { + __IM uint32_t PERIERR_STAT1; /*!< (@ 0x0000006C) Peripheral Error Event Status Register 1 */ + + struct + { + __IM uint32_t ER_ST0 : 1; /*!< [0..0] Indicate captured error status for DOC_DOPCI */ + __IM uint32_t ER_ST1 : 1; /*!< [1..1] Indicate captured error status for SRAM0_IE1 */ + __IM uint32_t ER_ST2 : 1; /*!< [2..2] Indicate captured error status for SRAM0_IE2 */ + __IM uint32_t ER_ST3 : 1; /*!< [3..3] Indicate captured error status for SRAM0_OVF */ + __IM uint32_t ER_ST4 : 1; /*!< [4..4] Indicate captured error status for SRAM1_IE1 */ + __IM uint32_t ER_ST5 : 1; /*!< [5..5] Indicate captured error status for SRAM1_IE2 */ + __IM uint32_t ER_ST6 : 1; /*!< [6..6] Indicate captured error status for SRAM1_OVF */ + __IM uint32_t ER_ST7 : 1; /*!< [7..7] Indicate captured error status for SRAM2_IE1 */ + __IM uint32_t ER_ST8 : 1; /*!< [8..8] Indicate captured error status for SRAM2_IE2 */ + __IM uint32_t ER_ST9 : 1; /*!< [9..9] Indicate captured error status for SRAM2_OVF */ + __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate captured error status for SRAM3_IE1 */ + __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate captured error status for SRAM3_IE2 */ + __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate captured error status for SRAM3_OVF */ + __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for MAIN_BUS_ERRINT */ + __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate captured error status for LLPP_BUS_ERRINT */ + __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for CPU1RMPU */ + __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for CPU1WMPU */ + __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for MPU_DMACR0 */ + __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for MPU_DMACW0 */ + __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for MPU_DMACR1 */ + __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for MPU_DMACW1 */ + __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for MPU_GMACR */ + __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for MPU_GMACW */ + __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for MPU_USBH */ + __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for MPU_USBF */ + uint32_t : 2; + __IM uint32_t ER_ST27 : 1; /*!< [27..27] Indicate captured error status for MPU_DBGR */ + __IM uint32_t ER_ST28 : 1; /*!< [28..28] Indicate captured error status for MPU_DBGW */ + uint32_t : 3; + } PERIERR_STAT1_b; + }; + + union + { + __OM uint32_t CPU0ERR_CLR; /*!< (@ 0x00000070) CPU0 Error Event Status Clear Register */ + + struct + { + __OM uint32_t ER_CL0 : 1; /*!< [0..0] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL1 : 1; /*!< [1..1] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL2 : 1; /*!< [2..2] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL3 : 1; /*!< [3..3] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL4 : 1; /*!< [4..4] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL5 : 1; /*!< [5..5] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL6 : 1; /*!< [6..6] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL7 : 1; /*!< [7..7] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL8 : 1; /*!< [8..8] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL9 : 1; /*!< [9..9] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL17 : 1; /*!< [17..17] ER_CL17 */ + __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL25 : 1; /*!< [25..25] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + uint32_t : 6; + } CPU0ERR_CLR_b; + }; + + union + { + __OM uint32_t CPU1ERR_CLR; /*!< (@ 0x00000074) CPU1 Error Event Status Clear Register */ + + struct + { + __OM uint32_t ER_CL0 : 1; /*!< [0..0] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL1 : 1; /*!< [1..1] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL2 : 1; /*!< [2..2] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL3 : 1; /*!< [3..3] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL4 : 1; /*!< [4..4] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL5 : 1; /*!< [5..5] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL6 : 1; /*!< [6..6] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL7 : 1; /*!< [7..7] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL8 : 1; /*!< [8..8] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL9 : 1; /*!< [9..9] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL25 : 1; /*!< [25..25] Clear captured error status for CPU1ERR_STAT register + * by writing 1 */ + uint32_t : 6; + } CPU1ERR_CLR_b; + }; + + union + { + __OM uint32_t PERIERR_CLR0; /*!< (@ 0x00000078) Peripheral Error Event Status Clear Register + * 0 */ + + struct + { + __OM uint32_t ER_CL0 : 1; /*!< [0..0] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL1 : 1; /*!< [1..1] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL2 : 1; /*!< [2..2] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL3 : 1; /*!< [3..3] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL4 : 1; /*!< [4..4] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL5 : 1; /*!< [5..5] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL6 : 1; /*!< [6..6] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL7 : 1; /*!< [7..7] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL8 : 1; /*!< [8..8] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL9 : 1; /*!< [9..9] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL25 : 1; /*!< [25..25] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL26 : 1; /*!< [26..26] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL27 : 1; /*!< [27..27] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL28 : 1; /*!< [28..28] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL29 : 1; /*!< [29..29] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL30 : 1; /*!< [30..30] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL31 : 1; /*!< [31..31] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + } PERIERR_CLR0_b; + }; + + union + { + __OM uint32_t PERIERR_CLR1; /*!< (@ 0x0000007C) Peripheral Error Event Status Clear Register + * 1 */ + + struct + { + __OM uint32_t ER_CL0 : 1; /*!< [0..0] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL1 : 1; /*!< [1..1] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL2 : 1; /*!< [2..2] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL3 : 1; /*!< [3..3] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL4 : 1; /*!< [4..4] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL5 : 1; /*!< [5..5] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL6 : 1; /*!< [6..6] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL7 : 1; /*!< [7..7] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL8 : 1; /*!< [8..8] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL9 : 1; /*!< [9..9] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + uint32_t : 2; + __OM uint32_t ER_CL27 : 1; /*!< [27..27] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL28 : 1; /*!< [28..28] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + uint32_t : 3; + } PERIERR_CLR1_b; + }; + + union + { + __IOM uint32_t CPU0ERR_RSTMSK; /*!< (@ 0x00000080) CPU0 Error Event Reset Mask Register */ + + struct + { + __IOM uint32_t RS_MK0 : 1; /*!< [0..0] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK1 : 1; /*!< [1..1] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK2 : 1; /*!< [2..2] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK3 : 1; /*!< [3..3] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK4 : 1; /*!< [4..4] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK5 : 1; /*!< [5..5] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK6 : 1; /*!< [6..6] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK7 : 1; /*!< [7..7] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK8 : 1; /*!< [8..8] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK9 : 1; /*!< [9..9] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK25 : 1; /*!< [25..25] Mask captured error status as a reset event for CPU0ERR_STAT */ + uint32_t : 6; + } CPU0ERR_RSTMSK_b; + }; + + union + { + __IOM uint32_t CPU1ERR_RSTMSK; /*!< (@ 0x00000084) CPU1 Error Event Reset Mask Register */ + + struct + { + __IOM uint32_t RS_MK0 : 1; /*!< [0..0] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK1 : 1; /*!< [1..1] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK2 : 1; /*!< [2..2] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK3 : 1; /*!< [3..3] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK4 : 1; /*!< [4..4] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK5 : 1; /*!< [5..5] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK6 : 1; /*!< [6..6] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK7 : 1; /*!< [7..7] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK8 : 1; /*!< [8..8] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK9 : 1; /*!< [9..9] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for CPU1ERR_STAT */ + __IOM uint32_t RS_MK25 : 1; /*!< [25..25] Mask captured error status as a reset event for CPU1ERR_STAT */ + uint32_t : 6; + } CPU1ERR_RSTMSK_b; + }; + + union + { + __IOM uint32_t PERIERR_RSTMSK0; /*!< (@ 0x00000088) Peripheral Error Event Reset Mask Register 0 */ + + struct + { + __IOM uint32_t RS_MK0 : 1; /*!< [0..0] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK1 : 1; /*!< [1..1] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK2 : 1; /*!< [2..2] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK3 : 1; /*!< [3..3] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK4 : 1; /*!< [4..4] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK5 : 1; /*!< [5..5] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK6 : 1; /*!< [6..6] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK7 : 1; /*!< [7..7] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK8 : 1; /*!< [8..8] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK9 : 1; /*!< [9..9] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK25 : 1; /*!< [25..25] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK26 : 1; /*!< [26..26] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK27 : 1; /*!< [27..27] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK28 : 1; /*!< [28..28] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK29 : 1; /*!< [29..29] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK30 : 1; /*!< [30..30] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK31 : 1; /*!< [31..31] Mask captured error status as a reset event for PERIERR_STAT0 */ + } PERIERR_RSTMSK0_b; + }; + + union + { + __IOM uint32_t PERIERR_RSTMSK1; /*!< (@ 0x0000008C) Peripheral Error Event Reset Mask Register 1 */ + + struct + { + __IOM uint32_t RS_MK0 : 1; /*!< [0..0] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK1 : 1; /*!< [1..1] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK2 : 1; /*!< [2..2] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK3 : 1; /*!< [3..3] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK4 : 1; /*!< [4..4] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK5 : 1; /*!< [5..5] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK6 : 1; /*!< [6..6] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK7 : 1; /*!< [7..7] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK8 : 1; /*!< [8..8] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK9 : 1; /*!< [9..9] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for PERIERR_STAT1 */ + uint32_t : 2; + __IOM uint32_t RS_MK27 : 1; /*!< [27..27] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK28 : 1; /*!< [28..28] Mask captured error status as a reset event for PERIERR_STAT1 */ + uint32_t : 3; + } PERIERR_RSTMSK1_b; + }; + + union + { + __IOM uint32_t CPU0ERR_E0MSK; /*!< (@ 0x00000090) CPU0 E0 Error Event Mask Register */ + + struct + { + __IOM uint32_t E0_MK0 : 1; /*!< [0..0] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK1 : 1; /*!< [1..1] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK2 : 1; /*!< [2..2] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK3 : 1; /*!< [3..3] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK4 : 1; /*!< [4..4] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK5 : 1; /*!< [5..5] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK6 : 1; /*!< [6..6] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK7 : 1; /*!< [7..7] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK8 : 1; /*!< [8..8] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK9 : 1; /*!< [9..9] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK25 : 1; /*!< [25..25] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + uint32_t : 6; + } CPU0ERR_E0MSK_b; + }; + + union + { + __IOM uint32_t CPU1ERR_E0MSK; /*!< (@ 0x00000094) CPU1 E0 Error Event Mask Register */ + + struct + { + __IOM uint32_t E0_MK0 : 1; /*!< [0..0] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK1 : 1; /*!< [1..1] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK2 : 1; /*!< [2..2] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK3 : 1; /*!< [3..3] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK4 : 1; /*!< [4..4] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK5 : 1; /*!< [5..5] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK6 : 1; /*!< [6..6] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK7 : 1; /*!< [7..7] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK8 : 1; /*!< [8..8] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK9 : 1; /*!< [9..9] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + __IOM uint32_t E0_MK25 : 1; /*!< [25..25] Mask captured error status as an CPU1_ERR0 event for + * CPU1ERR_STAT */ + uint32_t : 6; + } CPU1ERR_E0MSK_b; + }; + + union + { + __IOM uint32_t PERIERR_E0MSK0; /*!< (@ 0x00000098) Peripheral E0 Error Event Mask Register 0 */ + + struct + { + __IOM uint32_t E0_MK0 : 1; /*!< [0..0] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK1 : 1; /*!< [1..1] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK2 : 1; /*!< [2..2] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK3 : 1; /*!< [3..3] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK4 : 1; /*!< [4..4] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK5 : 1; /*!< [5..5] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK6 : 1; /*!< [6..6] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK7 : 1; /*!< [7..7] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK8 : 1; /*!< [8..8] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK9 : 1; /*!< [9..9] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK25 : 1; /*!< [25..25] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK26 : 1; /*!< [26..26] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK29 : 1; /*!< [29..29] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK30 : 1; /*!< [30..30] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK31 : 1; /*!< [31..31] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + } PERIERR_E0MSK0_b; + }; + + union + { + __IOM uint32_t PERIERR_E0MSK1; /*!< (@ 0x0000009C) Peripheral E0 Error Event Mask Register 1 */ + + struct + { + __IOM uint32_t E0_MK0 : 1; /*!< [0..0] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK1 : 1; /*!< [1..1] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK2 : 1; /*!< [2..2] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK3 : 1; /*!< [3..3] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK4 : 1; /*!< [4..4] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK5 : 1; /*!< [5..5] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK6 : 1; /*!< [6..6] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK7 : 1; /*!< [7..7] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK8 : 1; /*!< [8..8] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK9 : 1; /*!< [9..9] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + uint32_t : 2; + __IOM uint32_t E0_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + uint32_t : 3; + } PERIERR_E0MSK1_b; + }; + __IM uint32_t RESERVED1[24]; + + union + { + __IOM uint32_t CPU0ERR_E1MSK; /*!< (@ 0x00000100) CPU0 E1 Error Event Mask Register */ + + struct + { + __IOM uint32_t E1_MK0 : 1; /*!< [0..0] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK1 : 1; /*!< [1..1] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK2 : 1; /*!< [2..2] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK3 : 1; /*!< [3..3] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK4 : 1; /*!< [4..4] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK5 : 1; /*!< [5..5] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK6 : 1; /*!< [6..6] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK7 : 1; /*!< [7..7] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK8 : 1; /*!< [8..8] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK9 : 1; /*!< [9..9] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK25 : 1; /*!< [25..25] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + uint32_t : 6; + } CPU0ERR_E1MSK_b; + }; + + union + { + __IOM uint32_t CPU1ERR_E1MSK; /*!< (@ 0x00000104) CPU1 E1 Error Event Mask Register */ + + struct + { + __IOM uint32_t E1_MK0 : 1; /*!< [0..0] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK1 : 1; /*!< [1..1] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK2 : 1; /*!< [2..2] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK3 : 1; /*!< [3..3] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK4 : 1; /*!< [4..4] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK5 : 1; /*!< [5..5] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK6 : 1; /*!< [6..6] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK7 : 1; /*!< [7..7] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK8 : 1; /*!< [8..8] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK9 : 1; /*!< [9..9] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + __IOM uint32_t E1_MK25 : 1; /*!< [25..25] Mask captured error status as an CPU1_ERR1 event for + * CPU1ERR_STAT */ + uint32_t : 6; + } CPU1ERR_E1MSK_b; + }; + + union + { + __IOM uint32_t PERIERR_E1MSK0; /*!< (@ 0x00000108) Peripheral E1 Error Event Mask Register 0 */ + + struct + { + __IOM uint32_t E1_MK0 : 1; /*!< [0..0] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK1 : 1; /*!< [1..1] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK2 : 1; /*!< [2..2] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK3 : 1; /*!< [3..3] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK4 : 1; /*!< [4..4] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK5 : 1; /*!< [5..5] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK6 : 1; /*!< [6..6] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK7 : 1; /*!< [7..7] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK8 : 1; /*!< [8..8] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK9 : 1; /*!< [9..9] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK25 : 1; /*!< [25..25] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK26 : 1; /*!< [26..26] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK29 : 1; /*!< [29..29] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK30 : 1; /*!< [30..30] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK31 : 1; /*!< [31..31] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + } PERIERR_E1MSK0_b; + }; + + union + { + __IOM uint32_t PERIERR_E1MSK1; /*!< (@ 0x0000010C) Peripheral E1 Error Event Mask Register 1 */ + + struct + { + __IOM uint32_t E1_MK0 : 1; /*!< [0..0] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK1 : 1; /*!< [1..1] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK2 : 1; /*!< [2..2] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK3 : 1; /*!< [3..3] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK4 : 1; /*!< [4..4] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK5 : 1; /*!< [5..5] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK6 : 1; /*!< [6..6] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK7 : 1; /*!< [7..7] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK8 : 1; /*!< [8..8] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK9 : 1; /*!< [9..9] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + uint32_t : 2; + __IOM uint32_t E1_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + uint32_t : 3; + } PERIERR_E1MSK1_b; + }; +} R_ICU_Type; /*!< Size = 272 (0x110) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSC_S ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Register Write Protection for Safety Area (R_SYSC_S) + */ + +typedef struct /*!< (@ 0x81280000) R_SYSC_S Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SCKCR2; /*!< (@ 0x00000004) System Clock Control Register 2 */ + + struct + { + __IOM uint32_t FSELCPU0 : 2; /*!< [1..0] Set the frequency of the clock provided to Coretex-R52 + * CPU0 in combination with bit 5 (DIVSELSUB). The combination + * is shown below. */ + __IOM uint32_t FSELCPU1 : 2; /*!< [3..2] Set the frequency of the clock provided to Coretex-R52 + * CPU1 in combination with bit 5 (DIVSELSUB). */ + uint32_t : 1; + __IOM uint32_t DIVSELSUB : 1; /*!< [5..5] Select the base clock frequency for peripheral module. */ + uint32_t : 18; + __IOM uint32_t SPI3ASYNCSEL : 1; /*!< [24..24] Select clock frequency when asynchronous serial clock + * is selected in SPI3 */ + __IOM uint32_t SCI5ASYNCSEL : 1; /*!< [25..25] Select clock frequency when asynchronous serial clock + * is selected in SCI5 */ + uint32_t : 6; + } SCKCR2_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IM uint32_t PLL0MON; /*!< (@ 0x00000020) PLL0 Monitor Register */ + + struct + { + __IM uint32_t PLL0MON : 1; /*!< [0..0] PLL0 Lock State Monitor */ + uint32_t : 31; + } PLL0MON_b; + }; + __IM uint32_t RESERVED2[7]; + + union + { + __IM uint32_t PLL1MON; /*!< (@ 0x00000040) PLL1 Monitor Register */ + + struct + { + __IM uint32_t PLL1MON : 1; /*!< [0..0] PLL1 Lock State Monitor */ + uint32_t : 31; + } PLL1MON_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t PLL1EN; /*!< (@ 0x00000050) PLL1 Enable Register */ + + struct + { + __IOM uint32_t PLL1EN : 1; /*!< [0..0] PLL1 Enable */ + uint32_t : 31; + } PLL1EN_b; + }; + __IM uint32_t RESERVED4[7]; + + union + { + __IOM uint32_t LOCOCR; /*!< (@ 0x00000070) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint32_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint32_t : 31; + } LOCOCR_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint32_t HIZCTRLEN; /*!< (@ 0x00000080) High-Impedance Control Enable Register */ + + struct + { + __IOM uint32_t CLMA3MASK : 1; /*!< [0..0] CLMA3 error mask to POE3 and POEG */ + __IOM uint32_t CLMA0MASK : 1; /*!< [1..1] CLMA0 error mask to POE3 and POEG */ + __IOM uint32_t CLMA1MASK : 1; /*!< [2..2] CLMA1 error mask to POE3 and POEG */ + uint32_t : 29; + } HIZCTRLEN_b; + }; + __IM uint32_t RESERVED6[99]; + + union + { + __OM uint32_t SWRSYS; /*!< (@ 0x00000210) System Software Reset Register */ + + struct + { + __OM uint32_t SWR : 32; /*!< [31..0] System Software Reset */ + } SWRSYS_b; + }; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint32_t SWRCPU0; /*!< (@ 0x00000220) CPU0 Software Reset Register */ + + struct + { + __IOM uint32_t SWR : 32; /*!< [31..0] CPU0 Software Reset */ + } SWRCPU0_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint32_t SWRCPU1; /*!< (@ 0x00000230) CPU1 Software Reset Register */ + + struct + { + __IOM uint32_t SWR : 32; /*!< [31..0] CPU1 Software Reset */ + } SWRCPU1_b; + }; + __IM uint32_t RESERVED9[56]; + + union + { + __IOM uint32_t MSTPCRF; /*!< (@ 0x00000314) Module Stop Control Register F */ + + struct + { + __IOM uint32_t MSTPCRF00 : 1; /*!< [0..0] Trace Clock for Debugging Interface Module Stop */ + uint32_t : 31; + } MSTPCRF_b; + }; + + union + { + __IOM uint32_t MSTPCRG; /*!< (@ 0x00000318) Module Stop Control Register G */ + + struct + { + __IOM uint32_t MSTPCRG00 : 1; /*!< [0..0] SCI Unit 5 Module Stop */ + __IOM uint32_t MSTPCRG01 : 1; /*!< [1..1] IIC Unit 2 Module Stop */ + __IOM uint32_t MSTPCRG02 : 1; /*!< [2..2] SPI Unit 3 Module Stop */ + __IOM uint32_t MSTPCRG03 : 1; /*!< [3..3] GPT Unit 2 Module Stop */ + __IOM uint32_t MSTPCRG04 : 1; /*!< [4..4] CRC Unit 1 Module Stop */ + __IOM uint32_t MSTPCRG05 : 1; /*!< [5..5] RTC Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPCRG08 : 1; /*!< [8..8] CLMA3 Module Stop */ + __IOM uint32_t MSTPCRG09 : 1; /*!< [9..9] CLMA0 Module Stop */ + __IOM uint32_t MSTPCRG10 : 1; /*!< [10..10] CLMA1 Module Stop */ + __IOM uint32_t MSTPCRG11 : 1; /*!< [11..11] CLMA2 Module Stop */ + uint32_t : 20; + } MSTPCRG_b; + }; + + union + { + __IOM uint32_t MSTPCRH; /*!< (@ 0x0000031C) Module Stop Control Register H */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPCRH01 : 1; /*!< [1..1] CPU1 Module Stop */ + uint32_t : 30; + } MSTPCRH_b; + }; +} R_SYSC_S_Type; /*!< Size = 800 (0x320) */ + +/* =========================================================================================================================== */ +/* ================ R_CLMA0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Monitor Circuit 0 (R_CLMA0) + */ + +typedef struct /*!< (@ 0x81280800) R_CLMA0 Structure */ +{ + union + { + __IOM uint8_t CTL0; /*!< (@ 0x00000000) CLMA Control Register 0 */ + + struct + { + __IOM uint8_t CLME : 1; /*!< [0..0] Clock Monitor m Enable (m = 0 to 3) */ + uint8_t : 7; + } CTL0_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t CMPL; /*!< (@ 0x00000008) CLMA Compare Register L */ + + struct + { + __IOM uint16_t CMPL : 12; /*!< [11..0] Clock Monitor m Compare L (m = 0 to 3) */ + uint16_t : 4; + } CMPL_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t CMPH; /*!< (@ 0x0000000C) CLMA Compare Register H */ + + struct + { + __IOM uint16_t CMPH : 12; /*!< [11..0] Clock Monitor m Compare H (m = 0 to 3) */ + uint16_t : 4; + } CMPH_b; + }; + __IM uint16_t RESERVED3; + __OM uint8_t PCMD; /*!< (@ 0x00000010) CLMA Command Register */ + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IM uint8_t PROTSR; /*!< (@ 0x00000014) CLMA Protection Status Register */ + + struct + { + __IM uint8_t PRERR : 1; /*!< [0..0] CLMAm Error (m = 0 to 3) */ + uint8_t : 7; + } PROTSR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; +} R_CLMA0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Master MPU 0 (R_MPU0) + */ + +typedef struct /*!< (@ 0x81281100) R_MPU0 Structure */ +{ + __IOM R_MPU0_RGN_Type RGN[8]; /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register + * [0..7] */ + + union + { + __IOM uint32_t ERRINF_R; /*!< (@ 0x00000080) Master MPU Error Information Register for AXI + * type */ + + struct + { + __IOM uint32_t VALID : 1; /*!< [0..0] Validity of access error information */ + __IM uint32_t RW : 1; /*!< [1..1] Access error type */ + __IM uint32_t ERRADDR : 30; /*!< [31..2] Access error address */ + } ERRINF_R_b; + }; + + union + { + __IOM uint32_t ERRINF_W; /*!< (@ 0x00000084) Master MPU Error Information Register for AXI + * type */ + + struct + { + __IOM uint32_t VALID : 1; /*!< [0..0] Validity of access error information */ + __IM uint32_t RW : 1; /*!< [1..1] Access error type */ + __IM uint32_t ERRADDR : 30; /*!< [31..2] Access error address */ + } ERRINF_W_b; + }; +} R_MPU0_Type; /*!< Size = 136 (0x88) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU3 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Master MPU 3 (R_MPU3) + */ + +typedef struct /*!< (@ 0x81281400) R_MPU3 Structure */ +{ + __IOM R_MPU0_RGN_Type RGN[8]; /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register + * [0..7] */ + + union + { + __IOM uint32_t ERRINF; /*!< (@ 0x00000080) Master MPU Error Information Register for AHB + * type */ + + struct + { + __IOM uint32_t VALID : 1; /*!< [0..0] Validity of Access Error Information */ + __IM uint32_t RW : 1; /*!< [1..1] Access error type */ + __IM uint32_t ERRADDR : 30; /*!< [31..2] Access Error Address */ + } ERRINF_b; + }; +} R_MPU3_Type; /*!< Size = 132 (0x84) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSRAM_CTL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System SRAM Control (R_SYSRAM_CTL) + */ + +typedef struct /*!< (@ 0x81281800) R_SYSRAM_CTL Structure */ +{ + union + { + __IOM uint32_t SYSRAM_CTRL0; /*!< (@ 0x00000000) System SRAM Control Register 0 */ + + struct + { + __IOM uint32_t VECEN : 1; /*!< [0..0] Enables or disables error correction with ECC */ + uint32_t : 15; + __IOM uint32_t VRWEN : 4; /*!< [19..16] Enables write for each page of RAM */ + __IOM uint32_t VCEN : 1; /*!< [20..20] Enables access to RAM */ + __IOM uint32_t VLWEN : 1; /*!< [21..21] Enables write for RAM */ + uint32_t : 2; + __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors */ + uint32_t : 7; + } SYSRAM_CTRL0_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SYSRAM_CTRL1; /*!< (@ 0x00000010) System SRAM Control Register 1 */ + + struct + { + __IOM uint32_t VECEN : 1; /*!< [0..0] Enables or disables error correction with ECC */ + uint32_t : 15; + __IOM uint32_t VRWEN : 4; /*!< [19..16] Enables write for each page of RAM */ + __IOM uint32_t VCEN : 1; /*!< [20..20] Enables access to RAM */ + __IOM uint32_t VLWEN : 1; /*!< [21..21] Enables write for RAM */ + uint32_t : 2; + __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors */ + uint32_t : 7; + } SYSRAM_CTRL1_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t SYSRAM_CTRL2; /*!< (@ 0x00000020) System SRAM Control Register 2 */ + + struct + { + __IOM uint32_t VECEN : 1; /*!< [0..0] Enables or disables error correction with ECC */ + uint32_t : 15; + __IOM uint32_t VRWEN : 4; /*!< [19..16] Enables write for each page of RAM */ + __IOM uint32_t VCEN : 1; /*!< [20..20] Enables access to RAM */ + __IOM uint32_t VLWEN : 1; /*!< [21..21] Enables write for RAM */ + uint32_t : 2; + __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors */ + uint32_t : 7; + } SYSRAM_CTRL2_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t SYSRAM_CTRL3; /*!< (@ 0x00000030) System SRAM Control Register 3 */ + + struct + { + __IOM uint32_t VECEN : 1; /*!< [0..0] Enables or disables error correction with ECC */ + uint32_t : 15; + __IOM uint32_t VRWEN : 4; /*!< [19..16] Enables write for each page of RAM */ + __IOM uint32_t VCEN : 1; /*!< [20..20] Enables access to RAM */ + __IOM uint32_t VLWEN : 1; /*!< [21..21] Enables write for RAM */ + uint32_t : 2; + __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors */ + uint32_t : 7; + } SYSRAM_CTRL3_b; + }; +} R_SYSRAM_CTL_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_TCMAW ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TCM access wait state (R_TCMAW) + */ + +typedef struct /*!< (@ 0x81281900) R_TCMAW Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IM uint32_t CPU0WAIT; /*!< (@ 0x00000010) CPU0 ATCM Wait State Register */ + + struct + { + __IM uint32_t CPU0WAIT : 1; /*!< [0..0] ATCM Wait state */ + uint32_t : 31; + } CPU0WAIT_b; + }; +} R_TCMAW_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_RWP_S ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Register Write Protection for Safety Area (R_RWP_S) + */ + +typedef struct /*!< (@ 0x81281A00) R_RWP_S Structure */ +{ + union + { + __IOM uint32_t PRCRS; /*!< (@ 0x00000000) Safety Area Protect Register */ + + struct + { + __IOM uint32_t PRC0 : 1; /*!< [0..0] Protect 0 */ + __IOM uint32_t PRC1 : 1; /*!< [1..1] Protect 1 */ + __IOM uint32_t PRC2 : 1; /*!< [2..2] Protect 2 */ + __IOM uint32_t PRC3 : 1; /*!< [3..3] Protect 3 */ + uint32_t : 4; + __OM uint32_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + uint32_t : 16; + } PRCRS_b; + }; +} R_RWP_S_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_AC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Master MPU Access Control (R_MPU_AC) + */ + +typedef struct /*!< (@ 0x81282000) R_MPU_AC Structure */ +{ + union + { + __IOM uint32_t CPU1_CTRL; /*!< (@ 0x00000000) CPU1 Access Permission Control Register */ + + struct + { + __IOM uint32_t CPU1_CTRL : 1; /*!< [0..0] CPU1 access permission control to Master MPU related + * registers */ + uint32_t : 31; + } CPU1_CTRL_b; + }; +} R_MPU_AC_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit (R_MTU) + */ + +typedef struct /*!< (@ 0x90001000) R_MTU Structure */ +{ + __IM uint16_t RESERVED[261]; + + union + { + __IOM uint8_t TOERA; /*!< (@ 0x0000020A) Timer Output Master Enable Register A */ + + struct + { + __IOM uint8_t OE3B : 1; /*!< [0..0] Master Enable MTIOC3B */ + __IOM uint8_t OE4A : 1; /*!< [1..1] Master Enable MTIOC4A */ + __IOM uint8_t OE4B : 1; /*!< [2..2] Master Enable MTIOC4B */ + __IOM uint8_t OE3D : 1; /*!< [3..3] Master Enable MTIOC3D */ + __IOM uint8_t OE4C : 1; /*!< [4..4] Master Enable MTIOC4C */ + __IOM uint8_t OE4D : 1; /*!< [5..5] Master Enable MTIOC4D */ + uint8_t : 2; + } TOERA_b; + }; + __IM uint8_t RESERVED1[2]; + + union + { + __IOM uint8_t TGCRA; /*!< (@ 0x0000020D) Timer Gate Control Register A */ + + struct + { + __IOM uint8_t UF : 1; /*!< [0..0] Output Phase Switch */ + __IOM uint8_t VF : 1; /*!< [1..1] Output Phase Switch */ + __IOM uint8_t WF : 1; /*!< [2..2] Output Phase Switch */ + __IOM uint8_t FB : 1; /*!< [3..3] External Feedback Signal Enable */ + __IOM uint8_t P : 1; /*!< [4..4] Positive-Phase Output (P) Control */ + __IOM uint8_t N : 1; /*!< [5..5] Negative-Phase Output (N) Control */ + __IOM uint8_t BDC : 1; /*!< [6..6] Brushless DC Motor */ + uint8_t : 1; + } TGCRA_b; + }; + + union + { + __IOM uint8_t TOCR1A; /*!< (@ 0x0000020E) Timer Output Control Register 1A */ + + struct + { + __IOM uint8_t OLSP : 1; /*!< [0..0] Output Level Select P */ + __IOM uint8_t OLSN : 1; /*!< [1..1] Output Level Select N */ + __IOM uint8_t TOCS : 1; /*!< [2..2] TOC Select */ + __IOM uint8_t TOCL : 1; /*!< [3..3] TOC Register Write Protection */ + uint8_t : 2; + __IOM uint8_t PSYE : 1; /*!< [6..6] PWM Synchronous Output Enable */ + uint8_t : 1; + } TOCR1A_b; + }; + + union + { + __IOM uint8_t TOCR2A; /*!< (@ 0x0000020F) Timer Output Control Register 2A */ + + struct + { + __IOM uint8_t OLS1P : 1; /*!< [0..0] Output Level Select 1P */ + __IOM uint8_t OLS1N : 1; /*!< [1..1] Output Level Select 1N */ + __IOM uint8_t OLS2P : 1; /*!< [2..2] Output Level Select 2P */ + __IOM uint8_t OLS2N : 1; /*!< [3..3] Output Level Select 2N */ + __IOM uint8_t OLS3P : 1; /*!< [4..4] Output Level Select 3P */ + __IOM uint8_t OLS3N : 1; /*!< [5..5] Output Level Select 3N */ + __IOM uint8_t BF : 2; /*!< [7..6] TOLBR Buffer Transfer Timing Select */ + } TOCR2A_b; + }; + __IM uint16_t RESERVED2[2]; + __IOM uint16_t TCDRA; /*!< (@ 0x00000214) Timer Cycle Data Register A */ + __IOM uint16_t TDDRA; /*!< (@ 0x00000216) Timer Dead Time Data Register A */ + __IM uint16_t RESERVED3[4]; + __IM uint16_t TCNTSA; /*!< (@ 0x00000220) Timer Subcounter A */ + __IOM uint16_t TCBRA; /*!< (@ 0x00000222) Timer Cycle Buffer Register A */ + __IM uint16_t RESERVED4[6]; + + union + { + __IOM uint8_t TITCR1A; /*!< (@ 0x00000230) Timer Interrupt Skipping Set Register 1A */ + + struct + { + __IOM uint8_t T4VCOR : 3; /*!< [2..0] TCIV4 Interrupt Skipping Count Setting */ + __IOM uint8_t T4VEN : 1; /*!< [3..3] TCIV4 Interrupt Skipping Enable */ + __IOM uint8_t T3ACOR : 3; /*!< [6..4] TGIA3 Interrupt Skipping Count Setting */ + __IOM uint8_t T3AEN : 1; /*!< [7..7] TGIA3 Interrupt Skipping Enable */ + } TITCR1A_b; + }; + + union + { + __IM uint8_t TITCNT1A; /*!< (@ 0x00000231) Timer Interrupt Skipping Counter 1A */ + + struct + { + __IM uint8_t T4VCNT : 3; /*!< [2..0] TCIV4 Interrupt Counter */ + uint8_t : 1; + __IM uint8_t T3ACNT : 3; /*!< [6..4] TGIA3 Interrupt Counter */ + uint8_t : 1; + } TITCNT1A_b; + }; + + union + { + __IOM uint8_t TBTERA; /*!< (@ 0x00000232) Timer Buffer Transfer Set Register A */ + + struct + { + __IOM uint8_t BTE : 2; /*!< [1..0] Buffer Transfer Disable and Interrupt Skipping Link Setting */ + uint8_t : 6; + } TBTERA_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t TDERA; /*!< (@ 0x00000234) Timer Dead Time Enable Register A */ + + struct + { + __IOM uint8_t TDER : 1; /*!< [0..0] Dead Time Enable */ + uint8_t : 7; + } TDERA_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t TOLBRA; /*!< (@ 0x00000236) Timer Output Level Buffer Register A */ + + struct + { + __IOM uint8_t OLS1P : 1; /*!< [0..0] Output Level Select 1P */ + __IOM uint8_t OLS1N : 1; /*!< [1..1] Output Level Select 1N */ + __IOM uint8_t OLS2P : 1; /*!< [2..2] Output Level Select 2P */ + __IOM uint8_t OLS2N : 1; /*!< [3..3] Output Level Select 2N */ + __IOM uint8_t OLS3P : 1; /*!< [4..4] Output Level Select 3P */ + __IOM uint8_t OLS3N : 1; /*!< [5..5] Output Level Select 3N */ + uint8_t : 2; + } TOLBRA_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint8_t TITMRA; /*!< (@ 0x0000023A) Timer Interrupt Skipping Mode Register A */ + + struct + { + __IOM uint8_t TITM : 1; /*!< [0..0] Interrupt Skipping Function Select */ + uint8_t : 7; + } TITMRA_b; + }; + + union + { + __IOM uint8_t TITCR2A; /*!< (@ 0x0000023B) Timer Interrupt Skipping Set Register 2A */ + + struct + { + __IOM uint8_t TRG4COR : 3; /*!< [2..0] TRG4AN/TRG4BN Interrupt Skipping Count Setting */ + uint8_t : 5; + } TITCR2A_b; + }; + + union + { + __IM uint8_t TITCNT2A; /*!< (@ 0x0000023C) Timer Interrupt Skipping Counter 2A */ + + struct + { + __IM uint8_t TRG4CNT : 3; /*!< [2..0] TRG4AN/TRG4BN Interrupt Counter */ + uint8_t : 5; + } TITCNT2A_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10[17]; + + union + { + __IOM uint8_t TWCRA; /*!< (@ 0x00000260) Timer Waveform Control Register A */ + + struct + { + __IOM uint8_t WRE : 1; /*!< [0..0] Waveform Retain Enable */ + __IOM uint8_t SCC : 1; /*!< [1..1] Synchronous Clearing Control (Only valid in TWCRB) */ + uint8_t : 5; + __IOM uint8_t CCE : 1; /*!< [7..7] Compare Match Clear Enable */ + } TWCRA_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12[7]; + + union + { + __IOM uint8_t TMDR2A; /*!< (@ 0x00000270) Timer Mode Register 2A */ + + struct + { + __IOM uint8_t DRS : 1; /*!< [0..0] Double Buffer Select */ + uint8_t : 7; + } TMDR2A_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14[7]; + + union + { + __IOM uint8_t TSTRA; /*!< (@ 0x00000280) Timer Start Register A */ + + struct + { + __IOM uint8_t CST0 : 1; /*!< [0..0] Counter Start 0 */ + __IOM uint8_t CST1 : 1; /*!< [1..1] Counter Start 1 */ + __IOM uint8_t CST2 : 1; /*!< [2..2] Counter Start 2 */ + __IOM uint8_t CST8 : 1; /*!< [3..3] Counter Start 8 */ + uint8_t : 2; + __IOM uint8_t CST3 : 1; /*!< [6..6] Counter Start 3 */ + __IOM uint8_t CST4 : 1; /*!< [7..7] Counter Start 4 */ + } TSTRA_b; + }; + + union + { + __IOM uint8_t TSYRA; /*!< (@ 0x00000281) Timer Synchronous Register A */ + + struct + { + __IOM uint8_t SYNC0 : 1; /*!< [0..0] Timer Synchronous Operation 0 */ + __IOM uint8_t SYNC1 : 1; /*!< [1..1] Timer Synchronous Operation 1 */ + __IOM uint8_t SYNC2 : 1; /*!< [2..2] Timer Synchronous Operation 2 */ + uint8_t : 3; + __IOM uint8_t SYNC3 : 1; /*!< [6..6] Timer Synchronous Operation 3 */ + __IOM uint8_t SYNC4 : 1; /*!< [7..7] Timer Synchronous Operation 4 */ + } TSYRA_b; + }; + + union + { + __IOM uint8_t TCSYSTR; /*!< (@ 0x00000282) Timer Counter Synchronous Start Register */ + + struct + { + __IOM uint8_t SCH7 : 1; /*!< [0..0] Synchronous Start 7 */ + __IOM uint8_t SCH6 : 1; /*!< [1..1] Synchronous Start 6 */ + uint8_t : 1; + __IOM uint8_t SCH4 : 1; /*!< [3..3] Synchronous Start 4 */ + __IOM uint8_t SCH3 : 1; /*!< [4..4] Synchronous Start 3 */ + __IOM uint8_t SCH2 : 1; /*!< [5..5] Synchronous Start 2 */ + __IOM uint8_t SCH1 : 1; /*!< [6..6] Synchronous Start 1 */ + __IOM uint8_t SCH0 : 1; /*!< [7..7] Synchronous Start 0 */ + } TCSYSTR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t TRWERA; /*!< (@ 0x00000284) Timer Read/Write Enable Register */ + + struct + { + __IOM uint8_t RWE : 1; /*!< [0..0] Read/Write Enable */ + uint8_t : 7; + } TRWERA_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17[962]; + + union + { + __IOM uint8_t TOERB; /*!< (@ 0x00000A0A) Timer Output Master Enable Register B */ + + struct + { + __IOM uint8_t OE6B : 1; /*!< [0..0] Master Enable MTIOC6B */ + __IOM uint8_t OE7A : 1; /*!< [1..1] Master Enable MTIOC7A */ + __IOM uint8_t OE7B : 1; /*!< [2..2] Master Enable MTIOC7B */ + __IOM uint8_t OE6D : 1; /*!< [3..3] Master Enable MTIOC6D */ + __IOM uint8_t OE7C : 1; /*!< [4..4] Master Enable MTIOC7C */ + __IOM uint8_t OE7D : 1; /*!< [5..5] Master Enable MTIOC7D */ + uint8_t : 2; + } TOERB_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint8_t TOCR1B; /*!< (@ 0x00000A0E) Timer Output Control Register 1B */ + + struct + { + __IOM uint8_t OLSP : 1; /*!< [0..0] Output Level Select P */ + __IOM uint8_t OLSN : 1; /*!< [1..1] Output Level Select N */ + __IOM uint8_t TOCS : 1; /*!< [2..2] TOC Select */ + __IOM uint8_t TOCL : 1; /*!< [3..3] TOC Register Write Protection */ + uint8_t : 2; + __IOM uint8_t PSYE : 1; /*!< [6..6] PWM Synchronous Output Enable */ + uint8_t : 1; + } TOCR1B_b; + }; + + union + { + __IOM uint8_t TOCR2B; /*!< (@ 0x00000A0F) Timer Output Control Register 2B */ + + struct + { + __IOM uint8_t OLS1P : 1; /*!< [0..0] Output Level Select 1P */ + __IOM uint8_t OLS1N : 1; /*!< [1..1] Output Level Select 1N */ + __IOM uint8_t OLS2P : 1; /*!< [2..2] Output Level Select 2P */ + __IOM uint8_t OLS2N : 1; /*!< [3..3] Output Level Select 2N */ + __IOM uint8_t OLS3P : 1; /*!< [4..4] Output Level Select 3P */ + __IOM uint8_t OLS3N : 1; /*!< [5..5] Output Level Select 3N */ + __IOM uint8_t BF : 2; /*!< [7..6] TOLBR Buffer Transfer Timing Select */ + } TOCR2B_b; + }; + __IM uint16_t RESERVED20[2]; + __IOM uint16_t TCDRB; /*!< (@ 0x00000A14) Timer Cycle Data Register B */ + __IOM uint16_t TDDRB; /*!< (@ 0x00000A16) Timer Dead Time Data Register B */ + __IM uint16_t RESERVED21[4]; + __IM uint16_t TCNTSB; /*!< (@ 0x00000A20) Timer Subcounter B */ + __IOM uint16_t TCBRB; /*!< (@ 0x00000A22) Timer Cycle Buffer Register B */ + __IM uint16_t RESERVED22[6]; + + union + { + __IOM uint8_t TITCR1B; /*!< (@ 0x00000A30) Timer Interrupt Skipping Set Register 1B */ + + struct + { + __IOM uint8_t T7VCOR : 3; /*!< [2..0] TCIV7 Interrupt Skipping Count Setting */ + __IOM uint8_t T7VEN : 1; /*!< [3..3] TCIV7 Interrupt Skipping Enable */ + __IOM uint8_t T6ACOR : 3; /*!< [6..4] TGIA6 Interrupt Skipping Count Setting */ + __IOM uint8_t T6AEN : 1; /*!< [7..7] TGIA6 Interrupt Skipping Enable */ + } TITCR1B_b; + }; + + union + { + __IM uint8_t TITCNT1B; /*!< (@ 0x00000A31) Timer Interrupt Skipping Counter 1B */ + + struct + { + __IM uint8_t T7VCNT : 3; /*!< [2..0] TCIV7 Interrupt Counter */ + uint8_t : 1; + __IM uint8_t T6ACNT : 3; /*!< [6..4] TGIA6 Interrupt Counter */ + uint8_t : 1; + } TITCNT1B_b; + }; + + union + { + __IOM uint8_t TBTERB; /*!< (@ 0x00000A32) Timer Buffer Transfer Set Register B */ + + struct + { + __IOM uint8_t BTE : 2; /*!< [1..0] Buffer Transfer Disable and Interrupt Skipping Link Setting */ + uint8_t : 6; + } TBTERB_b; + }; + __IM uint8_t RESERVED23; + + union + { + __IOM uint8_t TDERB; /*!< (@ 0x00000A34) Timer Dead Time Enable Register B */ + + struct + { + __IOM uint8_t TDER : 1; /*!< [0..0] Dead Time Enable */ + uint8_t : 7; + } TDERB_b; + }; + __IM uint8_t RESERVED24; + + union + { + __IOM uint8_t TOLBRB; /*!< (@ 0x00000A36) Timer Output Level Buffer Register B */ + + struct + { + __IOM uint8_t OLS1P : 1; /*!< [0..0] Output Level Select 1P */ + __IOM uint8_t OLS1N : 1; /*!< [1..1] Output Level Select 1N */ + __IOM uint8_t OLS2P : 1; /*!< [2..2] Output Level Select 2P */ + __IOM uint8_t OLS2N : 1; /*!< [3..3] Output Level Select 2N */ + __IOM uint8_t OLS3P : 1; /*!< [4..4] Output Level Select 3P */ + __IOM uint8_t OLS3N : 1; /*!< [5..5] Output Level Select 3N */ + uint8_t : 2; + } TOLBRB_b; + }; + __IM uint8_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t TITMRB; /*!< (@ 0x00000A3A) Timer Interrupt Skipping Mode Register B */ + + struct + { + __IOM uint8_t TITM : 1; /*!< [0..0] Interrupt Skipping Function Select */ + uint8_t : 7; + } TITMRB_b; + }; + + union + { + __IOM uint8_t TITCR2B; /*!< (@ 0x00000A3B) Timer Interrupt Skipping Set Register 2B */ + + struct + { + __IOM uint8_t TRG7COR : 3; /*!< [2..0] TRG7AN/TRG7BN Interrupt Skipping Count Setting */ + uint8_t : 5; + } TITCR2B_b; + }; + + union + { + __IM uint8_t TITCNT2B; /*!< (@ 0x00000A3C) Timer Interrupt Skipping Counter 2B */ + + struct + { + __IM uint8_t TRG7CNT : 3; /*!< [2..0] TRG7AN/TRG7BN Interrupt Counter */ + uint8_t : 5; + } TITCNT2B_b; + }; + __IM uint8_t RESERVED27; + __IM uint16_t RESERVED28[17]; + + union + { + __IOM uint8_t TWCRB; /*!< (@ 0x00000A60) Timer Waveform Control Register B */ + + struct + { + __IOM uint8_t WRE : 1; /*!< [0..0] Waveform Retain Enable */ + __IOM uint8_t SCC : 1; /*!< [1..1] Synchronous Clearing Control (Only valid in TWCRB) */ + uint8_t : 5; + __IOM uint8_t CCE : 1; /*!< [7..7] Compare Match Clear Enable */ + } TWCRB_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30[7]; + + union + { + __IOM uint8_t TMDR2B; /*!< (@ 0x00000A70) Timer Mode Register 2B */ + + struct + { + __IOM uint8_t DRS : 1; /*!< [0..0] Double Buffer Select */ + uint8_t : 7; + } TMDR2B_b; + }; + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32[7]; + + union + { + __IOM uint8_t TSTRB; /*!< (@ 0x00000A80) Timer Start Register B */ + + struct + { + uint8_t : 6; + __IOM uint8_t CST6 : 1; /*!< [6..6] Counter Start 6 */ + __IOM uint8_t CST7 : 1; /*!< [7..7] Counter Start 7 */ + } TSTRB_b; + }; + + union + { + __IOM uint8_t TSYRB; /*!< (@ 0x00000A81) Timer Synchronous Register B */ + + struct + { + uint8_t : 6; + __IOM uint8_t SYNC6 : 1; /*!< [6..6] Timer Synchronous Operation 6 */ + __IOM uint8_t SYNC7 : 1; /*!< [7..7] Timer Synchronous Operation 7 */ + } TSYRB_b; + }; + __IM uint16_t RESERVED33; + + union + { + __IOM uint8_t TRWERB; /*!< (@ 0x00000A84) Timer Read/Write Enable Register */ + + struct + { + __IOM uint8_t RWE : 1; /*!< [0..0] Read/Write Enable */ + uint8_t : 7; + } TRWERB_b; + }; + __IM uint8_t RESERVED34; + __IM uint16_t RESERVED35; +} R_MTU_Type; /*!< Size = 2696 (0xa88) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU3 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 3 (R_MTU3) + */ + +typedef struct /*!< (@ 0x90001100) R_MTU3 Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000100) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000102) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + uint8_t : 2; + } TMDR1_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000104) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000105) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000108) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5[3]; + __IOM uint16_t TCNT; /*!< (@ 0x00000110) Timer Counter */ + __IM uint16_t RESERVED6[3]; + __IOM uint16_t TGRA; /*!< (@ 0x00000118) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000011A) Timer General Register B */ + __IM uint16_t RESERVED7[4]; + __IOM uint16_t TGRC; /*!< (@ 0x00000124) Timer General Register C */ + __IOM uint16_t TGRD; /*!< (@ 0x00000126) Timer General Register D */ + __IM uint16_t RESERVED8[2]; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x0000012C) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10[5]; + + union + { + __IOM uint8_t TBTM; /*!< (@ 0x00000138) Timer Buffer Operation Transfer Mode Register */ + + struct + { + __IOM uint8_t TTSA : 1; /*!< [0..0] Timing Select A */ + __IOM uint8_t TTSB : 1; /*!< [1..1] Timing Select B */ + uint8_t : 6; + } TBTM_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12[9]; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x0000014C) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14[18]; + __IOM uint16_t TGRE; /*!< (@ 0x00000172) Timer General Register E */ +} R_MTU3_Type; /*!< Size = 372 (0x174) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU4 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 4 (R_MTU4) + */ + +typedef struct /*!< (@ 0x90001200) R_MTU4 Structure */ +{ + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000001) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000003) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + uint8_t : 2; + } TMDR1_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000006) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000007) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000009) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 1; + __IOM uint8_t TTGE2 : 1; /*!< [6..6] A/D Converter Start Request Enable 2 */ + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + __IM uint16_t RESERVED4[4]; + __IOM uint16_t TCNT; /*!< (@ 0x00000012) Timer Counter */ + __IM uint16_t RESERVED5[4]; + __IOM uint16_t TGRA; /*!< (@ 0x0000001C) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000001E) Timer General Register B */ + __IM uint16_t RESERVED6[4]; + __IOM uint16_t TGRC; /*!< (@ 0x00000028) Timer General Register C */ + __IOM uint16_t TGRD; /*!< (@ 0x0000002A) Timer General Register D */ + __IM uint8_t RESERVED7; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x0000002D) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IM uint16_t RESERVED8[5]; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t TBTM; /*!< (@ 0x00000039) Timer Buffer Operation Transfer Mode Register */ + + struct + { + __IOM uint8_t TTSA : 1; /*!< [0..0] Timing Select A */ + __IOM uint8_t TTSB : 1; /*!< [1..1] Timing Select B */ + uint8_t : 6; + } TBTM_b; + }; + __IM uint16_t RESERVED10[3]; + + union + { + __IOM uint16_t TADCR; /*!< (@ 0x00000040) Timer A/D Converter Start Request Control Register */ + + struct + { + __IOM uint16_t ITB4VE : 1; /*!< [0..0] TCIV4 Interrupt Skipping Link Enable */ + __IOM uint16_t ITB3AE : 1; /*!< [1..1] TGIA3 Interrupt Skipping Link Enable */ + __IOM uint16_t ITA4VE : 1; /*!< [2..2] TCIV4 Interrupt Skipping Link Enable */ + __IOM uint16_t ITA3AE : 1; /*!< [3..3] TGIA3 Interrupt Skipping Link Enable */ + __IOM uint16_t DT4BE : 1; /*!< [4..4] Down-Count TRG4BN Enable */ + __IOM uint16_t UT4BE : 1; /*!< [5..5] Up-Count TRG4BN Enable */ + __IOM uint16_t DT4AE : 1; /*!< [6..6] Down-Count TRG4AN Enable */ + __IOM uint16_t UT4AE : 1; /*!< [7..7] Up-Count TRG4AN Enable */ + uint16_t : 6; + __IOM uint16_t BF : 2; /*!< [15..14] MTU4.TADCOBRA/TADCOBRB Transfer Timing Select */ + } TADCR_b; + }; + __IM uint16_t RESERVED11; + __IOM uint16_t TADCORA; /*!< (@ 0x00000044) Timer A/D Converter Start Request Cycle Set Register + * A */ + __IOM uint16_t TADCORB; /*!< (@ 0x00000046) Timer A/D Converter Start Request Cycle Set Register + * B */ + __IOM uint16_t TADCOBRA; /*!< (@ 0x00000048) Timer A/D Converter Start Request Cycle Set Buffer + * Register A */ + __IOM uint16_t TADCOBRB; /*!< (@ 0x0000004A) Timer A/D Converter Start Request Cycle Set Buffer + * Register B */ + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x0000004D) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint16_t RESERVED13[19]; + __IOM uint16_t TGRE; /*!< (@ 0x00000074) Timer General Register E */ + __IOM uint16_t TGRF; /*!< (@ 0x00000076) Timer General Register F */ +} R_MTU4_Type; /*!< Size = 120 (0x78) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU_NF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Noise Filter (R_MTU_NF) + */ + +typedef struct /*!< (@ 0x90001290) R_MTU_NF Structure */ +{ + union + { + __IOM uint8_t NFCR0; /*!< (@ 0x00000000) Noise Filter Control Register 0 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR0_b; + }; + + union + { + __IOM uint8_t NFCR1; /*!< (@ 0x00000001) Noise Filter Control Register 1 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + uint8_t : 2; + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR1_b; + }; + + union + { + __IOM uint8_t NFCR2; /*!< (@ 0x00000002) Noise Filter Control Register 2 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + uint8_t : 2; + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR2_b; + }; + + union + { + __IOM uint8_t NFCR3; /*!< (@ 0x00000003) Noise Filter Control Register 3 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR3_b; + }; + + union + { + __IOM uint8_t NFCR4; /*!< (@ 0x00000004) Noise Filter Control Register 4 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR4_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t NFCR8; /*!< (@ 0x00000008) Noise Filter Control Register 8 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR8_b; + }; + + union + { + __IOM uint8_t NFCRC; /*!< (@ 0x00000009) Noise Filter Control Register C */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCRC_b; + }; + __IM uint8_t RESERVED1[2041]; + + union + { + __IOM uint8_t NFCR6; /*!< (@ 0x00000803) Noise Filter Control Register 6 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR6_b; + }; + + union + { + __IOM uint8_t NFCR7; /*!< (@ 0x00000804) Noise Filter Control Register 7 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR7_b; + }; + + union + { + __IOM uint8_t NFCR5; /*!< (@ 0x00000805) Noise Filter Control Register 5 */ + + struct + { + __IOM uint8_t NFUEN : 1; /*!< [0..0] Noise Filter U Enable */ + __IOM uint8_t NFVEN : 1; /*!< [1..1] Noise Filter V Enable */ + __IOM uint8_t NFWEN : 1; /*!< [2..2] Noise Filter W Enable */ + uint8_t : 1; + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR5_b; + }; +} R_MTU_NF_Type; /*!< Size = 2054 (0x806) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 0 (R_MTU0) + */ + +typedef struct /*!< (@ 0x90001300) R_MTU0 Structure */ +{ + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000001) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + __IOM uint8_t BFE : 1; /*!< [6..6] Buffer Operation E */ + uint8_t : 1; + } TMDR1_b; + }; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000002) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000003) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000004) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + __IM uint8_t RESERVED; + __IOM uint16_t TCNT; /*!< (@ 0x00000006) Timer Counter */ + __IOM uint16_t TGRA; /*!< (@ 0x00000008) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000000A) Timer General Register B */ + __IOM uint16_t TGRC; /*!< (@ 0x0000000C) Timer General Register C */ + __IOM uint16_t TGRD; /*!< (@ 0x0000000E) Timer General Register D */ + __IM uint16_t RESERVED1[8]; + __IOM uint16_t TGRE; /*!< (@ 0x00000020) Timer General Register E */ + __IOM uint16_t TGRF; /*!< (@ 0x00000022) Timer General Register F */ + + union + { + __IOM uint8_t TIER2; /*!< (@ 0x00000024) Timer Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t TGIEE : 1; /*!< [0..0] TGR Interrupt Enable E */ + __IOM uint8_t TGIEF : 1; /*!< [1..1] TGR Interrupt Enable F */ + uint8_t : 5; + __IOM uint8_t TTGE2 : 1; /*!< [7..7] A/D Converter Start Request Enable 2 */ + } TIER2_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t TBTM; /*!< (@ 0x00000026) Timer Buffer Operation Transfer Mode Register */ + + struct + { + __IOM uint8_t TTSA : 1; /*!< [0..0] Timing Select A */ + __IOM uint8_t TTSB : 1; /*!< [1..1] Timing Select B */ + __IOM uint8_t TTSE : 1; /*!< [2..2] Timing Select E */ + uint8_t : 5; + } TBTM_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x00000028) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; +} R_MTU0_Type; /*!< Size = 44 (0x2c) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU1 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 1 (R_MTU1) + */ + +typedef struct /*!< (@ 0x90001380) R_MTU1 Structure */ +{ + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000001) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + uint8_t : 4; + } TMDR1_b; + }; + + union + { + __IOM uint8_t TIOR; /*!< (@ 0x00000002) Timer I/O Control Register */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIOR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000004) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + uint8_t : 2; + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + __IOM uint8_t TCIEU : 1; /*!< [5..5] Underflow Interrupt Enable */ + uint8_t : 1; + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x00000005) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IOM uint16_t TCNT; /*!< (@ 0x00000006) Timer Counter */ + __IOM uint16_t TGRA; /*!< (@ 0x00000008) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000000A) Timer General Register B */ + __IM uint32_t RESERVED1; + + union + { + __IOM uint8_t TICCR; /*!< (@ 0x00000010) Timer Input Capture Control Register */ + + struct + { + __IOM uint8_t I1AE : 1; /*!< [0..0] Input Capture Enable */ + __IOM uint8_t I1BE : 1; /*!< [1..1] Input Capture Enable */ + __IOM uint8_t I2AE : 1; /*!< [2..2] Input Capture Enable */ + __IOM uint8_t I2BE : 1; /*!< [3..3] Input Capture Enable */ + uint8_t : 4; + } TICCR_b; + }; + + union + { + __IOM uint8_t TMDR3; /*!< (@ 0x00000011) Timer Mode Register 3 */ + + struct + { + __IOM uint8_t LWA : 1; /*!< [0..0] MTU1/MTU2 Combination Longword Access Control */ + __IOM uint8_t PHCKSEL : 1; /*!< [1..1] External Input Phase Clock Select */ + uint8_t : 6; + } TMDR3_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x00000014) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t PCB : 2; /*!< [4..3] Functional Expansion Control for Phase Counting Modes + * 2, 3, and 5 */ + uint8_t : 3; + } TCR2_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + __IOM uint32_t TCNTLW; /*!< (@ 0x00000020) Timer Longword Counter */ + __IOM uint32_t TGRALW; /*!< (@ 0x00000024) Timer Longword General Register A */ + __IOM uint32_t TGRBLW; /*!< (@ 0x00000028) Timer Longword General Register B */ +} R_MTU1_Type; /*!< Size = 44 (0x2c) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU2 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 2 (R_MTU2) + */ + +typedef struct /*!< (@ 0x90001400) R_MTU2 Structure */ +{ + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000001) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + uint8_t : 4; + } TMDR1_b; + }; + + union + { + __IOM uint8_t TIOR; /*!< (@ 0x00000002) Timer I/O Control Register */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIOR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000004) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + uint8_t : 2; + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + __IOM uint8_t TCIEU : 1; /*!< [5..5] Underflow Interrupt Enable */ + uint8_t : 1; + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x00000005) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IOM uint16_t TCNT; /*!< (@ 0x00000006) Timer Counter */ + __IOM uint16_t TGRA; /*!< (@ 0x00000008) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000000A) Timer General Register B */ + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x0000000C) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t PCB : 2; /*!< [4..3] Functional Expansion Control for Phase Counting Modes + * 2, 3, and 5 */ + uint8_t : 3; + } TCR2_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_MTU2_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU8 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 8 (R_MTU8) + */ + +typedef struct /*!< (@ 0x90001600) R_MTU8 Structure */ +{ + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000001) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + uint8_t : 2; + } TMDR1_b; + }; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000002) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000003) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000004) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 3; + } TIER_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x00000006) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint8_t RESERVED1; + __IOM uint32_t TCNT; /*!< (@ 0x00000008) Timer Counter */ + __IOM uint32_t TGRA; /*!< (@ 0x0000000C) Timer General Register A */ + __IOM uint32_t TGRB; /*!< (@ 0x00000010) Timer General Register B */ + __IOM uint32_t TGRC; /*!< (@ 0x00000014) Timer General Register C */ + __IOM uint32_t TGRD; /*!< (@ 0x00000018) Timer General Register D */ +} R_MTU8_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU6 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 6 (R_MTU6) + */ + +typedef struct /*!< (@ 0x90001900) R_MTU6 Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000100) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000102) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + uint8_t : 2; + } TMDR1_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000104) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000105) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000108) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5[3]; + __IOM uint16_t TCNT; /*!< (@ 0x00000110) Timer Counter */ + __IM uint16_t RESERVED6[3]; + __IOM uint16_t TGRA; /*!< (@ 0x00000118) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000011A) Timer General Register B */ + __IM uint16_t RESERVED7[4]; + __IOM uint16_t TGRC; /*!< (@ 0x00000124) Timer General Register C */ + __IOM uint16_t TGRD; /*!< (@ 0x00000126) Timer General Register D */ + __IM uint16_t RESERVED8[2]; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x0000012C) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10[5]; + + union + { + __IOM uint8_t TBTM; /*!< (@ 0x00000138) Timer Buffer Operation Transfer Mode Register */ + + struct + { + __IOM uint8_t TTSA : 1; /*!< [0..0] Timing Select A */ + __IOM uint8_t TTSB : 1; /*!< [1..1] Timing Select B */ + uint8_t : 6; + } TBTM_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12[9]; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x0000014C) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t TSYCR; /*!< (@ 0x00000150) Timer Synchronous Clear Register */ + + struct + { + __IOM uint8_t CE2B : 1; /*!< [0..0] Clear Enable 2B */ + __IOM uint8_t CE2A : 1; /*!< [1..1] Clear Enable 2A */ + __IOM uint8_t CE1B : 1; /*!< [2..2] Clear Enable 1B */ + __IOM uint8_t CE1A : 1; /*!< [3..3] Clear Enable 1A */ + __IOM uint8_t CE0D : 1; /*!< [4..4] Clear Enable 0D */ + __IOM uint8_t CE0C : 1; /*!< [5..5] Clear Enable 0C */ + __IOM uint8_t CE0B : 1; /*!< [6..6] Clear Enable 0B */ + __IOM uint8_t CE0A : 1; /*!< [7..7] Clear Enable 0A */ + } TSYCR_b; + }; + __IM uint8_t RESERVED15; + __IM uint16_t RESERVED16[16]; + __IOM uint16_t TGRE; /*!< (@ 0x00000172) Timer General Register E */ +} R_MTU6_Type; /*!< Size = 372 (0x174) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU7 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 7 (R_MTU7) + */ + +typedef struct /*!< (@ 0x90001A00) R_MTU7 Structure */ +{ + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000001) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000003) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + uint8_t : 2; + } TMDR1_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000006) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000007) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000009) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 1; + __IOM uint8_t TTGE2 : 1; /*!< [6..6] A/D Converter Start Request Enable 2 */ + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + __IM uint16_t RESERVED4[4]; + __IOM uint16_t TCNT; /*!< (@ 0x00000012) Timer Counter */ + __IM uint16_t RESERVED5[4]; + __IOM uint16_t TGRA; /*!< (@ 0x0000001C) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000001E) Timer General Register B */ + __IM uint16_t RESERVED6[4]; + __IOM uint16_t TGRC; /*!< (@ 0x00000028) Timer General Register C */ + __IOM uint16_t TGRD; /*!< (@ 0x0000002A) Timer General Register D */ + __IM uint8_t RESERVED7; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x0000002D) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IM uint16_t RESERVED8[5]; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t TBTM; /*!< (@ 0x00000039) Timer Buffer Operation Transfer Mode Register */ + + struct + { + __IOM uint8_t TTSA : 1; /*!< [0..0] Timing Select A */ + __IOM uint8_t TTSB : 1; /*!< [1..1] Timing Select B */ + uint8_t : 6; + } TBTM_b; + }; + __IM uint16_t RESERVED10[3]; + + union + { + __IOM uint16_t TADCR; /*!< (@ 0x00000040) Timer A/D Converter Start Request Control Register */ + + struct + { + __IOM uint16_t ITB7VE : 1; /*!< [0..0] TCIV7 Interrupt Skipping Link Enable */ + __IOM uint16_t ITB6AE : 1; /*!< [1..1] TGIA6 Interrupt Skipping Link Enable */ + __IOM uint16_t ITA7VE : 1; /*!< [2..2] TCIV7 Interrupt Skipping Link Enable */ + __IOM uint16_t ITA6AE : 1; /*!< [3..3] TGIA6 Interrupt Skipping Link Enable */ + __IOM uint16_t DT7BE : 1; /*!< [4..4] Down-Count TRG7BN Enable */ + __IOM uint16_t UT7BE : 1; /*!< [5..5] Up-Count TRG7BN Enable */ + __IOM uint16_t DT7AE : 1; /*!< [6..6] Down-Count TRG7AN Enable */ + __IOM uint16_t UT7AE : 1; /*!< [7..7] Up-Count TRG7AN Enable */ + uint16_t : 6; + __IOM uint16_t BF : 2; /*!< [15..14] MTU7.TADCOBRA/TADCOBRB Transfer Timing Select */ + } TADCR_b; + }; + __IM uint16_t RESERVED11; + __IOM uint16_t TADCORA; /*!< (@ 0x00000044) Timer A/D Converter Start Request Cycle Set Register + * A */ + __IOM uint16_t TADCORB; /*!< (@ 0x00000046) Timer A/D Converter Start Request Cycle Set Register + * B */ + __IOM uint16_t TADCOBRA; /*!< (@ 0x00000048) Timer A/D Converter Start Request Cycle Set Buffer + * Register A */ + __IOM uint16_t TADCOBRB; /*!< (@ 0x0000004A) Timer A/D Converter Start Request Cycle Set Buffer + * Register B */ + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x0000004D) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint16_t RESERVED13[19]; + __IOM uint16_t TGRE; /*!< (@ 0x00000074) Timer General Register E */ + __IOM uint16_t TGRF; /*!< (@ 0x00000076) Timer General Register F */ +} R_MTU7_Type; /*!< Size = 120 (0x78) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU5 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 5 (R_MTU5) + */ + +typedef struct /*!< (@ 0x90001C00) R_MTU5 Structure */ +{ + __IM uint16_t RESERVED[64]; + __IOM uint16_t TCNTU; /*!< (@ 0x00000080) Timer Counter U */ + __IOM uint16_t TGRU; /*!< (@ 0x00000082) Timer General Register U */ + + union + { + __IOM uint8_t TCRU; /*!< (@ 0x00000084) Timer Control Register U */ + + struct + { + __IOM uint8_t TPSC : 2; /*!< [1..0] Time Prescaler Select */ + uint8_t : 6; + } TCRU_b; + }; + + union + { + __IOM uint8_t TCR2U; /*!< (@ 0x00000085) Timer Control Register 2U */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + uint8_t : 3; + } TCR2U_b; + }; + + union + { + __IOM uint8_t TIORU; /*!< (@ 0x00000086) Timer I/O Control Register U */ + + struct + { + __IOM uint8_t IOC : 5; /*!< [4..0] I/O Control C */ + uint8_t : 3; + } TIORU_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[4]; + __IOM uint16_t TCNTV; /*!< (@ 0x00000090) Timer Counter V */ + __IOM uint16_t TGRV; /*!< (@ 0x00000092) Timer General Register V */ + + union + { + __IOM uint8_t TCRV; /*!< (@ 0x00000094) Timer Control Register V */ + + struct + { + __IOM uint8_t TPSC : 2; /*!< [1..0] Time Prescaler Select */ + uint8_t : 6; + } TCRV_b; + }; + + union + { + __IOM uint8_t TCR2V; /*!< (@ 0x00000095) Timer Control Register 2V */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + uint8_t : 3; + } TCR2V_b; + }; + + union + { + __IOM uint8_t TIORV; /*!< (@ 0x00000096) Timer I/O Control Register V */ + + struct + { + __IOM uint8_t IOC : 5; /*!< [4..0] I/O Control C */ + uint8_t : 3; + } TIORV_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[4]; + __IOM uint16_t TCNTW; /*!< (@ 0x000000A0) Timer Counter W */ + __IOM uint16_t TGRW; /*!< (@ 0x000000A2) Timer General Register W */ + + union + { + __IOM uint8_t TCRW; /*!< (@ 0x000000A4) Timer Control Register W */ + + struct + { + __IOM uint8_t TPSC : 2; /*!< [1..0] Time Prescaler Select */ + uint8_t : 6; + } TCRW_b; + }; + + union + { + __IOM uint8_t TCR2W; /*!< (@ 0x000000A5) Timer Control Register 2W */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + uint8_t : 3; + } TCR2W_b; + }; + + union + { + __IOM uint8_t TIORW; /*!< (@ 0x000000A6) Timer I/O Control Register W */ + + struct + { + __IOM uint8_t IOC : 5; /*!< [4..0] I/O Control C */ + uint8_t : 3; + } TIORW_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6[5]; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x000000B2) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIE5W : 1; /*!< [0..0] TGR Interrupt Enable 5W */ + __IOM uint8_t TGIE5V : 1; /*!< [1..1] TGR Interrupt Enable 5V */ + __IOM uint8_t TGIE5U : 1; /*!< [2..2] TGR Interrupt Enable 5U */ + uint8_t : 5; + } TIER_b; + }; + __IM uint8_t RESERVED7; + + union + { + __IOM uint8_t TSTR; /*!< (@ 0x000000B4) Timer Start Register */ + + struct + { + __IOM uint8_t CSTW5 : 1; /*!< [0..0] Counter Start W5 */ + __IOM uint8_t CSTV5 : 1; /*!< [1..1] Counter Start V5 */ + __IOM uint8_t CSTU5 : 1; /*!< [2..2] Counter Start U5 */ + uint8_t : 5; + } TSTR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t TCNTCMPCLR; /*!< (@ 0x000000B6) Timer Compare Match Clear Register */ + + struct + { + __IOM uint8_t CMPCLR5W : 1; /*!< [0..0] TCNT Compare Clear 5W */ + __IOM uint8_t CMPCLR5V : 1; /*!< [1..1] TCNT Compare Clear 5V */ + __IOM uint8_t CMPCLR5U : 1; /*!< [2..2] TCNT Compare Clear 5U */ + uint8_t : 5; + } TCNTCMPCLR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; +} R_MTU5_Type; /*!< Size = 186 (0xba) */ + +/* =========================================================================================================================== */ +/* ================ R_TFU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Arithmetic Unit for Trigonometric Functions (R_TFU) + */ + +typedef struct /*!< (@ 0x90003000) R_TFU Structure */ +{ + __IM uint32_t RESERVED[2]; + + union + { + __IM uint8_t TRGSTS; /*!< (@ 0x00000008) Trigonometric Status Register */ + + struct + { + __IM uint8_t BSYF : 1; /*!< [0..0] Calculation in progress flag */ + __IM uint8_t ERRF : 1; /*!< [1..1] Input error flag */ + uint8_t : 6; + } TRGSTS_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3; + + union + { + __IOM float SCDT0; /*!< (@ 0x00000010) Sine Cosine Data Register 0 */ + + struct + { + __IOM uint32_t SCDT0 : 32; /*!< [31..0] Sine Cosine Data Register 0 (single-precision floating-point) */ + } SCDT0_b; + }; + + union + { + __IOM float SCDT1; /*!< (@ 0x00000014) Sine Cosine Data Register 1 */ + + struct + { + __IOM uint32_t SCDT1 : 32; /*!< [31..0] Sine Cosine Data Register 1 (single-precision floating-point) */ + } SCDT1_b; + }; + + union + { + __IOM float ATDT0; /*!< (@ 0x00000018) Arctangent Data Register 0 */ + + struct + { + __IOM uint32_t ATDT0 : 32; /*!< [31..0] Arctangent Data Register 0 (single-precision floating-point) */ + } ATDT0_b; + }; + + union + { + __IOM float ATDT1; /*!< (@ 0x0000001C) Arctangent Data Register 1 */ + + struct + { + __IOM uint32_t ATDT1 : 32; /*!< [31..0] Arctangent Data Register 1 (single-precision floating-point) */ + } ATDT1_b; + }; +} R_TFU_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_POE3 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable 3 (R_POE3) + */ + +typedef struct /*!< (@ 0x90005000) R_POE3 Structure */ +{ + union + { + __IOM uint16_t ICSR1; /*!< (@ 0x00000000) Input Level Control/Status Register 1 */ + + struct + { + __IOM uint16_t POE0M : 2; /*!< [1..0] POE0 Mode Select */ + uint16_t : 6; + __IOM uint16_t PIE1 : 1; /*!< [8..8] Port Interrupt Enable 1 */ + uint16_t : 3; + __IOM uint16_t POE0F : 1; /*!< [12..12] POE0 Flag */ + uint16_t : 3; + } ICSR1_b; + }; + + union + { + __IOM uint16_t OCSR1; /*!< (@ 0x00000002) Output Level Control/Status Register 1 */ + + struct + { + uint16_t : 8; + __IOM uint16_t OIE1 : 1; /*!< [8..8] Output Short Circuit Interrupt Enable 1 */ + __IOM uint16_t OCE1 : 1; /*!< [9..9] Output Short Circuit High-Impedance Enable 1 */ + uint16_t : 5; + __IOM uint16_t OSF1 : 1; /*!< [15..15] Output Short Circuit Flag 1 */ + } OCSR1_b; + }; + + union + { + __IOM uint16_t ICSR2; /*!< (@ 0x00000004) Input Level Control/Status Register 2 */ + + struct + { + __IOM uint16_t POE4M : 2; /*!< [1..0] POE4 Mode Select */ + uint16_t : 6; + __IOM uint16_t PIE2 : 1; /*!< [8..8] Port Interrupt Enable 2 */ + uint16_t : 3; + __IOM uint16_t POE4F : 1; /*!< [12..12] POE4 Flag */ + uint16_t : 3; + } ICSR2_b; + }; + + union + { + __IOM uint16_t OCSR2; /*!< (@ 0x00000006) Output Level Control/Status Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t OIE2 : 1; /*!< [8..8] Output Short Circuit Interrupt Enable 2 */ + __IOM uint16_t OCE2 : 1; /*!< [9..9] Output Short Circuit High-Impedance Enable 2 */ + uint16_t : 5; + __IOM uint16_t OSF2 : 1; /*!< [15..15] Output Short Circuit Flag 2 */ + } OCSR2_b; + }; + + union + { + __IOM uint16_t ICSR3; /*!< (@ 0x00000008) Input Level Control/Status Register 3 */ + + struct + { + __IOM uint16_t POE8M : 2; /*!< [1..0] POE8 Mode Select */ + uint16_t : 6; + __IOM uint16_t PIE3 : 1; /*!< [8..8] Port Interrupt Enable 3 */ + __IOM uint16_t POE8E : 1; /*!< [9..9] POE8 High-Impedance Enable */ + uint16_t : 2; + __IOM uint16_t POE8F : 1; /*!< [12..12] POE8 Flag */ + uint16_t : 3; + } ICSR3_b; + }; + + union + { + __IOM uint8_t SPOER; /*!< (@ 0x0000000A) Software Port Output Enable Register */ + + struct + { + __IOM uint8_t MTUCH34HIZ : 1; /*!< [0..0] MTU3 and MTU4 Output High-Impedance Enable */ + __IOM uint8_t MTUCH67HIZ : 1; /*!< [1..1] MTU6 and MTU7 Output High-Impedance Enable */ + __IOM uint8_t MTUCH0HIZ : 1; /*!< [2..2] MTU0 Pin High-Impedance Enable */ + uint8_t : 5; + } SPOER_b; + }; + + union + { + __IOM uint8_t POECR1; /*!< (@ 0x0000000B) Port Output Enable Control Register 1 */ + + struct + { + __IOM uint8_t MTU0AZE : 1; /*!< [0..0] MTIOC0A High-Impedance Enable */ + __IOM uint8_t MTU0BZE : 1; /*!< [1..1] MTIOC0B High-Impedance Enable */ + __IOM uint8_t MTU0CZE : 1; /*!< [2..2] MTIOC0C High-Impedance Enable */ + __IOM uint8_t MTU0DZE : 1; /*!< [3..3] MTIOC0D High-Impedance Enable */ + uint8_t : 4; + } POECR1_b; + }; + + union + { + __IOM uint16_t POECR2; /*!< (@ 0x0000000C) Port Output Enable Control Register 2 */ + + struct + { + __IOM uint16_t MTU7BDZE : 1; /*!< [0..0] MTIOC7B/MTIOC7D High-Impedance Enable */ + __IOM uint16_t MTU7ACZE : 1; /*!< [1..1] MTIOC7A/MTIOC7C High-Impedance Enable */ + __IOM uint16_t MTU6BDZE : 1; /*!< [2..2] MTIOC6B/MTIOC6D High-Impedance Enable */ + uint16_t : 5; + __IOM uint16_t MTU4BDZE : 1; /*!< [8..8] MTIOC4B/MTIOC4D High-Impedance Enable */ + __IOM uint16_t MTU4ACZE : 1; /*!< [9..9] MTIOC4A/MTIOC4C High-Impedance Enable */ + __IOM uint16_t MTU3BDZE : 1; /*!< [10..10] MTIOC3B/MTIOC3D High-Impedance Enable */ + uint16_t : 5; + } POECR2_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t POECR4; /*!< (@ 0x00000010) Port Output Enable Control Register 4 */ + + struct + { + uint16_t : 2; + __IOM uint16_t IC2ADDMT34ZE : 1; /*!< [2..2] MTU3 and MTU4 High-Impedance POE4F Add */ + __IOM uint16_t IC3ADDMT34ZE : 1; /*!< [3..3] MTU3 and MTU4 High-Impedance POE8F Add */ + __IOM uint16_t IC4ADDMT34ZE : 1; /*!< [4..4] MTU3 and MTU4 High-Impedance POE10F Add */ + __IOM uint16_t IC5ADDMT34ZE : 1; /*!< [5..5] MTU3 and MTU4 High-Impedance POE11F Add */ + __IOM uint16_t DE0ADDMT34ZE : 1; /*!< [6..6] MTU3 and MTU4 High-Impedance DERR0ST Add */ + __IOM uint16_t DE1ADDMT34ZE : 1; /*!< [7..7] MTU3 and MTU4 High-Impedance DERR1ST Add */ + uint16_t : 1; + __IOM uint16_t IC1ADDMT67ZE : 1; /*!< [9..9] MTU6 and MTU7 High-Impedance POE0F Add */ + uint16_t : 1; + __IOM uint16_t IC3ADDMT67ZE : 1; /*!< [11..11] MTU6 and MTU7 High-Impedance POE8F Add */ + __IOM uint16_t IC4ADDMT67ZE : 1; /*!< [12..12] MTU6 and MTU7 High-Impedance POE10F Add */ + __IOM uint16_t IC5ADDMT67ZE : 1; /*!< [13..13] MTU6 and MTU7 High-Impedance POE11F Add */ + __IOM uint16_t DE0ADDMT67ZE : 1; /*!< [14..14] MTU6 and MTU7 High-Impedance DERR0ST Add */ + __IOM uint16_t DE1ADDMT67ZE : 1; /*!< [15..15] MTU6 and MTU7 High-Impedance DERR1ST Add */ + } POECR4_b; + }; + + union + { + __IOM uint16_t POECR5; /*!< (@ 0x00000012) Port Output Enable Control Register 5 */ + + struct + { + uint16_t : 1; + __IOM uint16_t IC1ADDMT0ZE : 1; /*!< [1..1] MTU0 High-Impedance POE0F Add */ + __IOM uint16_t IC2ADDMT0ZE : 1; /*!< [2..2] MTU0 High-Impedance POE4F Add */ + uint16_t : 1; + __IOM uint16_t IC4ADDMT0ZE : 1; /*!< [4..4] MTU0 High-Impedance POE10F Add */ + __IOM uint16_t IC5ADDMT0ZE : 1; /*!< [5..5] MTU0 High-Impedance POE11F Add */ + __IOM uint16_t DE0ADDMT0ZE : 1; /*!< [6..6] MTU0 High-Impedance DERR0ST Add */ + __IOM uint16_t DE1ADDMT0ZE : 1; /*!< [7..7] MTU0 High-Impedance DERR1ST Add */ + uint16_t : 8; + } POECR5_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t ICSR4; /*!< (@ 0x00000016) Input Level Control/Status Register 4 */ + + struct + { + __IOM uint16_t POE10M : 2; /*!< [1..0] POE10 Mode Select */ + uint16_t : 6; + __IOM uint16_t PIE4 : 1; /*!< [8..8] Port Interrupt Enable 4 */ + __IOM uint16_t POE10E : 1; /*!< [9..9] POE10 High-Impedance Enable */ + uint16_t : 2; + __IOM uint16_t POE10F : 1; /*!< [12..12] POE10 Flag */ + uint16_t : 3; + } ICSR4_b; + }; + + union + { + __IOM uint16_t ICSR5; /*!< (@ 0x00000018) Input Level Control/Status Register 5 */ + + struct + { + __IOM uint16_t POE11M : 2; /*!< [1..0] POE11 Mode Select */ + uint16_t : 6; + __IOM uint16_t PIE5 : 1; /*!< [8..8] Port Interrupt Enable 5 */ + __IOM uint16_t POE11E : 1; /*!< [9..9] POE11 High-Impedance Enable */ + uint16_t : 2; + __IOM uint16_t POE11F : 1; /*!< [12..12] POE11 Flag */ + uint16_t : 3; + } ICSR5_b; + }; + + union + { + __IOM uint16_t ALR1; /*!< (@ 0x0000001A) Active Level Setting Register 1 */ + + struct + { + __IOM uint16_t OLSG0A : 1; /*!< [0..0] MTIOC3B Pin Active Level Setting */ + __IOM uint16_t OLSG0B : 1; /*!< [1..1] MTIOC3D Pin Active Level Setting */ + __IOM uint16_t OLSG1A : 1; /*!< [2..2] MTIOC4A Pin Active Level Setting */ + __IOM uint16_t OLSG1B : 1; /*!< [3..3] MTIOC4C Pin Active Level Setting */ + __IOM uint16_t OLSG2A : 1; /*!< [4..4] MTIOC4B Pin Active Level Setting */ + __IOM uint16_t OLSG2B : 1; /*!< [5..5] MTIOC4D Pin Active Level Setting */ + uint16_t : 1; + __IOM uint16_t OLSEN : 1; /*!< [7..7] Active Level Setting Enable */ + uint16_t : 8; + } ALR1_b; + }; + + union + { + __IOM uint16_t ICSR6; /*!< (@ 0x0000001C) Input Level Control/Status Register 6 */ + + struct + { + uint16_t : 9; + __IOM uint16_t OSTSTE : 1; /*!< [9..9] Oscillation Stop High-Impedance Enable */ + uint16_t : 2; + __IOM uint16_t OSTSTF : 1; /*!< [12..12] Oscillation Stop High-Impedance Flag */ + uint16_t : 3; + } ICSR6_b; + }; + + union + { + __IOM uint16_t ICSR7; /*!< (@ 0x0000001E) Input Level Control/Status Register 7 */ + + struct + { + uint16_t : 6; + __IOM uint16_t DERR0IE : 1; /*!< [6..6] DSMIF0 Error Interrupt Enable */ + __IOM uint16_t DERR1IE : 1; /*!< [7..7] DSMIF1 Error Interrupt Enable */ + uint16_t : 5; + __IM uint16_t DERR0ST : 1; /*!< [13..13] DSMIF0 Error Status */ + __IM uint16_t DERR1ST : 1; /*!< [14..14] DSMIF1 Error Status */ + uint16_t : 1; + } ICSR7_b; + }; + __IM uint16_t RESERVED2[2]; + + union + { + __IOM uint8_t M0SELR1; /*!< (@ 0x00000024) MTU0 Pin Select Register 1 */ + + struct + { + __IOM uint8_t M0ASEL : 4; /*!< [3..0] MTU0-A (MTIOC0A) Pin Select */ + __IOM uint8_t M0BSEL : 4; /*!< [7..4] MTU0-B (MTIOC0B) Pin Select */ + } M0SELR1_b; + }; + + union + { + __IOM uint8_t M0SELR2; /*!< (@ 0x00000025) MTU0 Pin Select Register 2 */ + + struct + { + __IOM uint8_t M0CSEL : 4; /*!< [3..0] MTU0-C (MTIOC0C) Pin Select */ + __IOM uint8_t M0DSEL : 4; /*!< [7..4] MTU0-D (MTIOC0D) Pin Select */ + } M0SELR2_b; + }; + + union + { + __IOM uint8_t M3SELR; /*!< (@ 0x00000026) MTU3 Pin Select Register */ + + struct + { + __IOM uint8_t M3BSEL : 4; /*!< [3..0] MTU3-B (MTIOC3B) Pin Select */ + __IOM uint8_t M3DSEL : 4; /*!< [7..4] MTU3-D (MTIOC3D) Pin Select */ + } M3SELR_b; + }; + + union + { + __IOM uint8_t M4SELR1; /*!< (@ 0x00000027) MTU4 Pin Select Register 1 */ + + struct + { + __IOM uint8_t M4ASEL : 4; /*!< [3..0] MTU4-A (MTIOC4A) Pin Select */ + __IOM uint8_t M4CSEL : 4; /*!< [7..4] MTU4-C (MTIOC4C) Pin Select */ + } M4SELR1_b; + }; + + union + { + __IOM uint8_t M4SELR2; /*!< (@ 0x00000028) MTU4 Pin Select Register 2 */ + + struct + { + __IOM uint8_t M4BSEL : 4; /*!< [3..0] MTU4-B (MTIOC4B) Pin Select */ + __IOM uint8_t M4DSEL : 4; /*!< [7..4] MTU4-D (MTIOC4D) Pin Select */ + } M4SELR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t M6SELR; /*!< (@ 0x0000002A) MTU6 Pin Select Register */ + + struct + { + __IOM uint8_t M6BSEL : 4; /*!< [3..0] MTU6-B (MTIOC6B) Pin Select */ + __IOM uint8_t M6DSEL : 4; /*!< [7..4] MTU6-D (MTIOC6D) Pin Select */ + } M6SELR_b; + }; + + union + { + __IOM uint8_t M7SELR1; /*!< (@ 0x0000002B) MTU7 Pin Select Register 1 */ + + struct + { + __IOM uint8_t M7ASEL : 4; /*!< [3..0] MTU7-A (MTIOC7A) Pin Select */ + __IOM uint8_t M7CSEL : 4; /*!< [7..4] MTU7-C (MTIOC7C) Pin Select */ + } M7SELR1_b; + }; + + union + { + __IOM uint8_t M7SELR2; /*!< (@ 0x0000002C) MTU7 Pin Select Register 2 */ + + struct + { + __IOM uint8_t M7BSEL : 4; /*!< [3..0] MTU7-B (MTIOC7B) Pin Select */ + __IOM uint8_t M7DSEL : 4; /*!< [7..4] MTU7-D (MTIOC7D) Pin Select */ + } M7SELR2_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; +} R_POE3_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GPT Port Output Enable 0 (R_POEG0) + */ + +typedef struct /*!< (@ 0x90006000) R_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEG0GA; /*!< (@ 0x00000000) POEG0 Group A Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG0GA_b; + }; + __IM uint32_t RESERVED[255]; + + union + { + __IOM uint32_t POEG0GB; /*!< (@ 0x00000400) POEG0 Group B Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG0GB_b; + }; + __IM uint32_t RESERVED1[255]; + + union + { + __IOM uint32_t POEG0GC; /*!< (@ 0x00000800) POEG0 Group C Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG0GC_b; + }; + __IM uint32_t RESERVED2[255]; + + union + { + __IOM uint32_t POEG0GD; /*!< (@ 0x00000C00) POEG0 Group D Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG0GD_b; + }; +} R_POEG0_Type; /*!< Size = 3076 (0xc04) */ + +/* =========================================================================================================================== */ +/* ================ R_DSMIF0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Delta-sigma Interface 0 (R_DSMIF0) + */ + +typedef struct /*!< (@ 0x90008000) R_DSMIF0 Structure */ +{ + __IM uint32_t RESERVED[16]; + + union + { + __IOM uint32_t DSSEICR; /*!< (@ 0x00000040) Overcurrent Sum Error Detect Interrupt Control + * Register */ + + struct + { + __IOM uint32_t ISEL : 1; /*!< [0..0] Overcurrent sum error lower limit detection interrupt + * enable bit */ + __IOM uint32_t ISEH : 1; /*!< [1..1] Overcurrent sum error upper limit detection interrupt + * enable bit */ + uint32_t : 30; + } DSSEICR_b; + }; + + union + { + __IOM uint32_t DSSECSR; /*!< (@ 0x00000044) Overcurrent Sum Error Detect Channel Setting + * Register */ + + struct + { + __IOM uint32_t SEDM : 3; /*!< [2..0] Overcurrent sum error detect mode setting bit */ + uint32_t : 29; + } DSSECSR_b; + }; + + union + { + __IOM uint32_t DSSELTR; /*!< (@ 0x00000048) Overcurrent Sum Error Detect Low Threshold Register */ + + struct + { + __IOM uint32_t SCMPTBL : 18; /*!< [17..0] Overcurrent sum error detect lower limit */ + uint32_t : 14; + } DSSELTR_b; + }; + + union + { + __IOM uint32_t DSSEHTR; /*!< (@ 0x0000004C) Overcurrent Sum Error Detect High Threshold Register */ + + struct + { + __IOM uint32_t SCMPTBH : 18; /*!< [17..0] Overcurrent sum error detect upper limit */ + uint32_t : 14; + } DSSEHTR_b; + }; + + union + { + __IOM uint32_t DSSECR; /*!< (@ 0x00000050) Overcurrent Sum Error Detect Control Register */ + + struct + { + __IOM uint32_t SEEL : 1; /*!< [0..0] Overcurrent sum error lower limit detection enable bit */ + __IOM uint32_t SEEH : 1; /*!< [1..1] Overcurrent sum error upper limit detection enable bit */ + uint32_t : 30; + } DSSECR_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t DSSECDR[3]; /*!< (@ 0x00000060) Overcurrent Sum Error Detect Capture Data Register + * [0..2] */ + + struct + { + __IOM uint32_t SECDR : 16; /*!< [15..0] Overcurrent sum error detect capture data n */ + uint32_t : 16; + } DSSECDR_b[3]; + }; + __IM uint32_t RESERVED2[37]; + + union + { + __IOM uint32_t DSCSTRTR; /*!< (@ 0x00000100) Channel Software Start Trigger Register */ + + struct + { + __IOM uint32_t STRTRG0 : 1; /*!< [0..0] Channel 0 start trigger */ + __IOM uint32_t STRTRG1 : 1; /*!< [1..1] Channel 1 start trigger */ + __IOM uint32_t STRTRG2 : 1; /*!< [2..2] Channel 2 start trigger */ + uint32_t : 29; + } DSCSTRTR_b; + }; + + union + { + __IOM uint32_t DSCSTPTR; /*!< (@ 0x00000104) Channel Software Stop Trigger Register */ + + struct + { + __IOM uint32_t STPTRG0 : 1; /*!< [0..0] Channel 0 stop trigger */ + __IOM uint32_t STPTRG1 : 1; /*!< [1..1] Channel 1 stop trigger */ + __IOM uint32_t STPTRG2 : 1; /*!< [2..2] Channel 2 stop trigger */ + uint32_t : 29; + } DSCSTPTR_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IM uint32_t DSCESR; /*!< (@ 0x00000110) Channel Error Status Register */ + + struct + { + __IM uint32_t OCFL0 : 1; /*!< [0..0] Channel 0 overcurrent lower limit detection flag */ + __IM uint32_t OCFL1 : 1; /*!< [1..1] Channel 1 overcurrent lower limit detection flag */ + __IM uint32_t OCFL2 : 1; /*!< [2..2] Channel 2 overcurrent lower limit detection flag */ + uint32_t : 1; + __IM uint32_t OCFH0 : 1; /*!< [4..4] Channel 0 overcurrent upper limit detection flag */ + __IM uint32_t OCFH1 : 1; /*!< [5..5] Channel 1 overcurrent upper limit detection flag */ + __IM uint32_t OCFH2 : 1; /*!< [6..6] Channel 2 overcurrent upper limit detection flag */ + uint32_t : 1; + __IM uint32_t SCF0 : 1; /*!< [8..8] Channel 0 short circuit detection flag */ + __IM uint32_t SCF1 : 1; /*!< [9..9] Channel 1 short circuit detection flag */ + __IM uint32_t SCF2 : 1; /*!< [10..10] Channel 2 short circuit detection flag */ + uint32_t : 5; + __IM uint32_t SUMERRL : 1; /*!< [16..16] Overcurrent sum error lower limit detection flag */ + __IM uint32_t SUMERRH : 1; /*!< [17..17] Overcurrent sum error upper limit detection flag */ + uint32_t : 14; + } DSCESR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t DSCSR; /*!< (@ 0x00000118) Channel Status Register */ + + struct + { + __IM uint32_t DUF0 : 1; /*!< [0..0] Channel 0 Data Update flag */ + __IM uint32_t DUF1 : 1; /*!< [1..1] Channel 1 Data Update flag */ + __IM uint32_t DUF2 : 1; /*!< [2..2] Channel 2 Data Update flag */ + uint32_t : 29; + } DSCSR_b; + }; + + union + { + __IM uint32_t DSCSSR; /*!< (@ 0x0000011C) Channel State Status Register */ + + struct + { + __IM uint32_t CHSTATE0 : 1; /*!< [0..0] Channel 0 state */ + uint32_t : 3; + __IM uint32_t CHSTATE1 : 1; /*!< [4..4] Channel 1 state */ + uint32_t : 3; + __IM uint32_t CHSTATE2 : 1; /*!< [8..8] Channel 2 state */ + uint32_t : 23; + } DSCSSR_b; + }; + + union + { + __OM uint32_t DSCESCR; /*!< (@ 0x00000120) Channel Error Status Clear Register */ + + struct + { + __OM uint32_t CLROCFL0 : 1; /*!< [0..0] Channel 0 Overcurrent Lower Limit Detection Flag Clear */ + __OM uint32_t CLROCFL1 : 1; /*!< [1..1] Channel 1 Overcurrent Lower Limit Detection Flag Clear */ + __OM uint32_t CLROCFL2 : 1; /*!< [2..2] Channel 2 Overcurrent Lower Limit Detection Flag Clear */ + uint32_t : 1; + __OM uint32_t CLROCFH0 : 1; /*!< [4..4] Channel 0 Overcurrent Upper Limit Detection Flag Clear */ + __OM uint32_t CLROCFH1 : 1; /*!< [5..5] Channel 1 Overcurrent Upper Limit Detection Flag Clear */ + __OM uint32_t CLROCFH2 : 1; /*!< [6..6] Channel 2 Overcurrent Upper Limit Detection Flag Clear */ + uint32_t : 1; + __OM uint32_t CLRSCF0 : 1; /*!< [8..8] Channel 0 Short Circuit Detection Flag Clear */ + __OM uint32_t CLRSCF1 : 1; /*!< [9..9] Channel 1 Short Circuit Detection Flag Clear */ + __OM uint32_t CLRSCF2 : 1; /*!< [10..10] Channel 2 Short Circuit Detection Flag Clear */ + uint32_t : 5; + __OM uint32_t CLRSUMERRL : 1; /*!< [16..16] Overcurrent Sum Error Lower Limit Detection Flag Clear */ + __OM uint32_t CLRSUMERRH : 1; /*!< [17..17] Overcurrent Sum Error Upper Limit Detection Flag Clear */ + uint32_t : 14; + } DSCESCR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __OM uint32_t DSCSCR; /*!< (@ 0x00000128) Channel Status Clear Register */ + + struct + { + __OM uint32_t CLRDUF0 : 1; /*!< [0..0] Channel 0 Data Update Flag Clear */ + __OM uint32_t CLRDUF1 : 1; /*!< [1..1] Channel 1 Data Update Flag Clear */ + __OM uint32_t CLRDUF2 : 1; /*!< [2..2] Channel 2 Data Update Flag Clear */ + uint32_t : 29; + } DSCSCR_b; + }; + __IM uint32_t RESERVED6[21]; + __IOM R_DSMIF0_CH_Type CH[3]; /*!< (@ 0x00000180) Channel Registers [0..2] */ +} R_DSMIF0_Type; /*!< Size = 816 (0x330) */ + +/* =========================================================================================================================== */ +/* ================ R_GSC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Global System Counter (R_GSC) + */ + +typedef struct /*!< (@ 0xC0060000) R_GSC Structure */ +{ + union + { + __IOM uint32_t CNTCR; /*!< (@ 0x00000000) Global System Counter Control Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Counter Enable */ + __IOM uint32_t HDBG : 1; /*!< [1..1] Halt on Debug */ + uint32_t : 30; + } CNTCR_b; + }; + + union + { + __IM uint32_t CNTSR; /*!< (@ 0x00000004) Global System Counter Status Register */ + + struct + { + uint32_t : 1; + __IM uint32_t DBGH : 1; /*!< [1..1] Debug Halted */ + uint32_t : 30; + } CNTSR_b; + }; + + union + { + __IOM uint32_t CNTCVL; /*!< (@ 0x00000008) Global System Counter Current Value Lower Register */ + + struct + { + __IOM uint32_t CNTCVL_L_32 : 32; /*!< [31..0] Current value of the counter, lower 32 bits */ + } CNTCVL_b; + }; + + union + { + __IOM uint32_t CNTCVU; /*!< (@ 0x0000000C) Global System Counter Current Value Upper Register */ + + struct + { + __IOM uint32_t CNTCVU_U_32 : 32; /*!< [31..0] Current value of the counter, upper 32 bits */ + } CNTCVU_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t CNTFID0; /*!< (@ 0x00000020) Global System Counter Base Frequency ID Register */ + + struct + { + __IOM uint32_t FREQ : 32; /*!< [31..0] Frequency in number of ticks per second */ + } CNTFID0_b; + }; +} R_GSC_Type; /*!< Size = 36 (0x24) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_GPT7_BASE 0x80000000UL + #define R_GPT8_BASE 0x80000100UL + #define R_GPT9_BASE 0x80000200UL + #define R_GPT10_BASE 0x80000300UL + #define R_GPT11_BASE 0x80000400UL + #define R_GPT12_BASE 0x80000500UL + #define R_GPT13_BASE 0x80000600UL + #define R_SCI0_BASE 0x80001000UL + #define R_SCI1_BASE 0x80001400UL + #define R_SCI2_BASE 0x80001800UL + #define R_SCI3_BASE 0x80001C00UL + #define R_SCI4_BASE 0x80002000UL + #define R_SPI0_BASE 0x80003000UL + #define R_SPI1_BASE 0x80003400UL + #define R_SPI2_BASE 0x80003800UL + #define R_CRC0_BASE 0x80004000UL + #define R_CANFD_BASE 0x80020000UL + #define R_CMT_BASE 0x80040000UL + #define R_CMTW0_BASE 0x80041000UL + #define R_CMTW1_BASE 0x80041400UL + #define R_WDT0_BASE 0x80042000UL + #define R_WDT1_BASE 0x80042400UL + #define R_IIC0_BASE 0x80043000UL + #define R_IIC1_BASE 0x80043400UL + #define R_DOC_BASE 0x80044000UL + #define R_ADC121_BASE 0x80045000UL + #define R_TSU_BASE 0x80046000UL + #define R_POEG1_BASE 0x80047000UL + #define R_DMAC0_BASE 0x80080000UL + #define R_DMAC1_BASE 0x80081000UL + #define R_ICU_NS_BASE 0x80090000UL + #define R_ELC_BASE 0x80090010UL + #define R_DMA_BASE 0x80090060UL + #define R_PORT_NSR_BASE 0x800A0000UL + #define R_GMAC_BASE 0x80100000UL + #define R_ETHSS_BASE 0x80110000UL + #define R_ESC_INI_BASE 0x80110200UL + #define R_ETHSW_PTP_BASE 0x80110400UL + #define R_ETHSW_BASE 0x80120000UL + #define R_ESC_BASE 0x80130000UL + #define R_USBHC_BASE 0x80200000UL + #define R_USBF_BASE 0x80201000UL + #define R_BSC_BASE 0x80210000UL + #define R_XSPI0_BASE 0x80220000UL + #define R_XSPI1_BASE 0x80221000UL + #define R_SYSC_NS_BASE 0x80280000UL + #define R_SEM_BASE 0x80281000UL + #define R_ELO_BASE 0x80281200UL + #define R_RWP_NS_BASE 0x80281A10UL + #define R_GPT14_BASE 0x81000000UL + #define R_GPT15_BASE 0x81000100UL + #define R_GPT16_BASE 0x81000200UL + #define R_GPT17_BASE 0x81000300UL + #define R_SCI5_BASE 0x81001000UL + #define R_SPI3_BASE 0x81002000UL + #define R_CRC1_BASE 0x81003000UL + #define R_IIC2_BASE 0x81008000UL + #define R_RTC_BASE 0x81009000UL + #define R_POEG2_BASE 0x8100A000UL + #define R_OTP_BASE 0x81028000UL + #define R_PORT_SR_BASE 0x81030000UL + #define R_PTADR_BASE 0x81030C00UL + #define R_SYSRAM0_BASE 0x81040000UL + #define R_SYSRAM1_BASE 0x81041000UL + #define R_SYSRAM2_BASE 0x81042000UL + #define R_SYSRAM3_BASE 0x81043000UL + #define R_ICU_BASE 0x81048000UL + #define R_SYSC_S_BASE 0x81280000UL + #define R_CLMA0_BASE 0x81280800UL + #define R_CLMA1_BASE 0x81280820UL + #define R_CLMA2_BASE 0x81280840UL + #define R_CLMA3_BASE 0x81280860UL + #define R_MPU0_BASE 0x81281100UL + #define R_MPU1_BASE 0x81281200UL + #define R_MPU2_BASE 0x81281300UL + #define R_MPU3_BASE 0x81281400UL + #define R_MPU4_BASE 0x81281500UL + #define R_MPU6_BASE 0x81281700UL + #define R_SYSRAM_CTL_BASE 0x81281800UL + #define R_TCMAW_BASE 0x81281900UL + #define R_RWP_S_BASE 0x81281A00UL + #define R_MPU_AC_BASE 0x81282000UL + #define R_MTU_BASE 0x90001000UL + #define R_MTU3_BASE 0x90001100UL + #define R_MTU4_BASE 0x90001200UL + #define R_MTU_NF_BASE 0x90001290UL + #define R_MTU0_BASE 0x90001300UL + #define R_MTU1_BASE 0x90001380UL + #define R_MTU2_BASE 0x90001400UL + #define R_MTU8_BASE 0x90001600UL + #define R_MTU6_BASE 0x90001900UL + #define R_MTU7_BASE 0x90001A00UL + #define R_MTU5_BASE 0x90001C00UL + #define R_GPT0_BASE 0x90002000UL + #define R_GPT1_BASE 0x90002100UL + #define R_GPT2_BASE 0x90002200UL + #define R_GPT3_BASE 0x90002300UL + #define R_GPT4_BASE 0x90002400UL + #define R_GPT5_BASE 0x90002500UL + #define R_GPT6_BASE 0x90002600UL + #define R_TFU_BASE 0x90003000UL + #define R_ADC120_BASE 0x90004000UL + #define R_POE3_BASE 0x90005000UL + #define R_POEG0_BASE 0x90006000UL + #define R_DSMIF0_BASE 0x90008000UL + #define R_DSMIF1_BASE 0x90008400UL + #define R_GSC_BASE 0xC0060000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) + #define R_CRC0 ((R_CRC0_Type *) R_CRC0_BASE) + #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CMT ((R_CMT_Type *) R_CMT_BASE) + #define R_CMTW0 ((R_CMTW0_Type *) R_CMTW0_BASE) + #define R_CMTW1 ((R_CMTW0_Type *) R_CMTW1_BASE) + #define R_WDT0 ((R_WDT0_Type *) R_WDT0_BASE) + #define R_WDT1 ((R_WDT0_Type *) R_WDT1_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_ADC121 ((R_ADC121_Type *) R_ADC121_BASE) + #define R_TSU ((R_TSU_Type *) R_TSU_BASE) + #define R_POEG1 ((R_POEG1_Type *) R_POEG1_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_ICU_NS ((R_ICU_NS_Type *) R_ICU_NS_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_PORT_NSR ((R_PORT_COMMON_Type *) R_PORT_NSR_BASE) + #define R_GMAC ((R_GMAC_Type *) R_GMAC_BASE) + #define R_ETHSS ((R_ETHSS_Type *) R_ETHSS_BASE) + #define R_ESC_INI ((R_ESC_INI_Type *) R_ESC_INI_BASE) + #define R_ETHSW_PTP ((R_ETHSW_PTP_Type *) R_ETHSW_PTP_BASE) + #define R_ETHSW ((R_ETHSW_Type *) R_ETHSW_BASE) + #define R_ESC ((R_ESC_Type *) R_ESC_BASE) + #define R_USBHC ((R_USBHC_Type *) R_USBHC_BASE) + #define R_USBF ((R_USBF_Type *) R_USBF_BASE) + #define R_BSC ((R_BSC_Type *) R_BSC_BASE) + #define R_XSPI0 ((R_XSPI0_Type *) R_XSPI0_BASE) + #define R_XSPI1 ((R_XSPI0_Type *) R_XSPI1_BASE) + #define R_SYSC_NS ((R_SYSC_NS_Type *) R_SYSC_NS_BASE) + #define R_SEM ((R_SEM_Type *) R_SEM_BASE) + #define R_ELO ((R_ELO_Type *) R_ELO_BASE) + #define R_RWP_NS ((R_RWP_NS_Type *) R_RWP_NS_BASE) + #define R_GPT14 ((R_GPT0_Type *) R_GPT14_BASE) + #define R_GPT15 ((R_GPT0_Type *) R_GPT15_BASE) + #define R_GPT16 ((R_GPT0_Type *) R_GPT16_BASE) + #define R_GPT17 ((R_GPT0_Type *) R_GPT17_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SPI3 ((R_SPI0_Type *) R_SPI3_BASE) + #define R_CRC1 ((R_CRC0_Type *) R_CRC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_POEG2 ((R_POEG2_Type *) R_POEG2_BASE) + #define R_OTP ((R_OTP_Type *) R_OTP_BASE) + #define R_PORT_SR ((R_PORT_COMMON_Type *) R_PORT_SR_BASE) + #define R_PTADR ((R_PTADR_Type *) R_PTADR_BASE) + #define R_SYSRAM0 ((R_SYSRAM0_Type *) R_SYSRAM0_BASE) + #define R_SYSRAM1 ((R_SYSRAM0_Type *) R_SYSRAM1_BASE) + #define R_SYSRAM2 ((R_SYSRAM0_Type *) R_SYSRAM2_BASE) + #define R_SYSRAM3 ((R_SYSRAM0_Type *) R_SYSRAM3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_SYSC_S ((R_SYSC_S_Type *) R_SYSC_S_BASE) + #define R_CLMA0 ((R_CLMA0_Type *) R_CLMA0_BASE) + #define R_CLMA1 ((R_CLMA0_Type *) R_CLMA1_BASE) + #define R_CLMA2 ((R_CLMA0_Type *) R_CLMA2_BASE) + #define R_CLMA3 ((R_CLMA0_Type *) R_CLMA3_BASE) + #define R_MPU0 ((R_MPU0_Type *) R_MPU0_BASE) + #define R_MPU1 ((R_MPU0_Type *) R_MPU1_BASE) + #define R_MPU2 ((R_MPU0_Type *) R_MPU2_BASE) + #define R_MPU3 ((R_MPU3_Type *) R_MPU3_BASE) + #define R_MPU4 ((R_MPU3_Type *) R_MPU4_BASE) + #define R_MPU6 ((R_MPU0_Type *) R_MPU6_BASE) + #define R_SYSRAM_CTL ((R_SYSRAM_CTL_Type *) R_SYSRAM_CTL_BASE) + #define R_TCMAW ((R_TCMAW_Type *) R_TCMAW_BASE) + #define R_RWP_S ((R_RWP_S_Type *) R_RWP_S_BASE) + #define R_MPU_AC ((R_MPU_AC_Type *) R_MPU_AC_BASE) + #define R_MTU ((R_MTU_Type *) R_MTU_BASE) + #define R_MTU3 ((R_MTU3_Type *) R_MTU3_BASE) + #define R_MTU4 ((R_MTU4_Type *) R_MTU4_BASE) + #define R_MTU_NF ((R_MTU_NF_Type *) R_MTU_NF_BASE) + #define R_MTU0 ((R_MTU0_Type *) R_MTU0_BASE) + #define R_MTU1 ((R_MTU1_Type *) R_MTU1_BASE) + #define R_MTU2 ((R_MTU2_Type *) R_MTU2_BASE) + #define R_MTU8 ((R_MTU8_Type *) R_MTU8_BASE) + #define R_MTU6 ((R_MTU6_Type *) R_MTU6_BASE) + #define R_MTU7 ((R_MTU7_Type *) R_MTU7_BASE) + #define R_MTU5 ((R_MTU5_Type *) R_MTU5_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_TFU ((R_TFU_Type *) R_TFU_BASE) + #define R_ADC120 ((R_ADC121_Type *) R_ADC120_BASE) + #define R_POE3 ((R_POE3_Type *) R_POE3_BASE) + #define R_POEG0 ((R_POEG0_Type *) R_POEG0_BASE) + #define R_DSMIF0 ((R_DSMIF0_Type *) R_DSMIF0_BASE) + #define R_DSMIF1 ((R_DSMIF0_Type *) R_DSMIF1_BASE) + #define R_GSC ((R_GSC_Type *) R_GSC_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CFDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NCFG ========================================================== */ + #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ + #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ + #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ + #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ + #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ + #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ + #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ + #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ + #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ + #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ + #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ + #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ + #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ + #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ + #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ + #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ + #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ + #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ + #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ + #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ + #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ + #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ + #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ + #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ + #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ + #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ + #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ + #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ + #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ + #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ + #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ + #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ + #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ + #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ + #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ + #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ + #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ + #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ + #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ + #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ + #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ + #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ + #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ + #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ + #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ + #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ + #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ + #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDCFG_GWEN_Pos (24UL) /*!< GWEN (Bit 24) */ + #define R_CANFD_CFDC2_FDCFG_GWEN_Msk (0x1000000UL) /*!< GWEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos (25UL) /*!< GWFDF (Bit 25) */ + #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk (0x2000000UL) /*!< GWFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos (26UL) /*!< GWBRS (Bit 26) */ + #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk (0x4000000UL) /*!< GWBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos (31UL) /*!< CFDTE (Bit 31) */ + #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (25UL) /*!< SCNT (Bit 25) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0x1e000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ +/* ========================================================= BLCT ========================================================== */ + #define R_CANFD_CFDC2_BLCT_BLCE_Pos (0UL) /*!< BLCE (Bit 0) */ + #define R_CANFD_CFDC2_BLCT_BLCE_Msk (0x1UL) /*!< BLCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_BLCT_BLCLD_Pos (8UL) /*!< BLCLD (Bit 8) */ + #define R_CANFD_CFDC2_BLCT_BLCLD_Msk (0x100UL) /*!< BLCLD (Bitfield-Mask: 0x01) */ +/* ========================================================= BLSTS ========================================================= */ + #define R_CANFD_CFDC2_BLSTS_BLC_Pos (3UL) /*!< BLC (Bit 3) */ + #define R_CANFD_CFDC2_BLSTS_BLC_Msk (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos (4UL) /*!< GAFLSRD0 (Bit 4) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk (0x10UL) /*!< GAFLSRD0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos (5UL) /*!< GAFLSRD1 (Bit 5) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk (0x20UL) /*!< GAFLSRD1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos (6UL) /*!< GAFLSRD2 (Bit 6) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk (0x40UL) /*!< GAFLSRD2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x3fffUL) /*!< GAFLFDP (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFD_CFDRM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFD_CFDRM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFD_CFDRM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFD_CFDRM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFD_CFDRM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFD_CFDRM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DF_WD ========================================================= */ + #define R_CANFD_CFDRM_DF_WD_RMDB_LL_Pos (0UL) /*!< RMDB_LL (Bit 0) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_LL_Msk (0xffUL) /*!< RMDB_LL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_LH_Pos (8UL) /*!< RMDB_LH (Bit 8) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_LH_Msk (0xff00UL) /*!< RMDB_LH (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_HL_Pos (16UL) /*!< RMDB_HL (Bit 16) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_HL_Msk (0xff0000UL) /*!< RMDB_HL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_HH_Pos (24UL) /*!< RMDB_HH (Bit 24) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_HH_Msk (0xff000000UL) /*!< RMDB_HH (Bitfield-Mask: 0xff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFD_CFDRM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ + #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ + #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ + #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ + #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRF_FDSTS_CFDRFPTR_Pos (16UL) /*!< CFDRFPTR (Bit 16) */ + #define R_CANFD_CFDRF_FDSTS_CFDRFPTR_Msk (0xffff0000UL) /*!< CFDRFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ + #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ +/* ========================================================= DF_WD ========================================================= */ + #define R_CANFD_CFDRF_DF_WD_RFDB_LL_Pos (0UL) /*!< RFDB_LL (Bit 0) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_LL_Msk (0xffUL) /*!< RFDB_LL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_LH_Pos (8UL) /*!< RFDB_LH (Bit 8) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_LH_Msk (0xff00UL) /*!< RFDB_LH (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_HL_Pos (16UL) /*!< RFDB_HL (Bit 16) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_HL_Msk (0xff0000UL) /*!< RFDB_HL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_HH_Pos (24UL) /*!< RFDB_HH (Bit 24) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_HH_Msk (0xff000000UL) /*!< RFDB_HH (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ + #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ + #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ + #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ + #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ======================================================== FDCSTS ========================================================= */ + #define R_CANFD_CFDCF_FDCSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ + #define R_CANFD_CFDCF_FDCSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDCSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ + #define R_CANFD_CFDCF_FDCSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDCSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ + #define R_CANFD_CFDCF_FDCSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDCSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ + #define R_CANFD_CFDCF_FDCSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCF_FDCSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ + #define R_CANFD_CFDCF_FDCSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DF_WD ========================================================= */ + #define R_CANFD_CFDCF_DF_WD_CFDB_LL_Pos (0UL) /*!< CFDB_LL (Bit 0) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_LL_Msk (0xffUL) /*!< CFDB_LL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_LH_Pos (8UL) /*!< CFDB_LH (Bit 8) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_LH_Msk (0xff00UL) /*!< CFDB_LH (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_HL_Pos (16UL) /*!< CFDB_HL (Bit 16) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_HL_Msk (0xff0000UL) /*!< CFDB_HL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_HH_Pos (24UL) /*!< CFDB_HH (Bit 24) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_HH_Msk (0xff000000UL) /*!< CFDB_HH (Bitfield-Mask: 0xff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ + #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ + #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ + #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ + #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDTHL_ACC0_TGW_Pos (15UL) /*!< TGW (Bit 15) */ + #define R_CANFD_CFDTHL_ACC0_TGW_Msk (0x8000UL) /*!< TGW (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ + #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ + #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ + #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ + #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ + #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DF_WD ========================================================= */ + #define R_CANFD_CFDTM_DF_WD_TMDB_LL_Pos (0UL) /*!< TMDB_LL (Bit 0) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_LL_Msk (0xffUL) /*!< TMDB_LL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_LH_Pos (8UL) /*!< TMDB_LH (Bit 8) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_LH_Msk (0xff00UL) /*!< TMDB_LH (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_HL_Pos (16UL) /*!< TMDB_HL (Bit 16) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_HL_Msk (0xff0000UL) /*!< TMDB_HL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_HH_Pos (24UL) /*!< TMDB_HH (Bit 24) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_HH_Msk (0xff000000UL) /*!< TMDB_HH (Bitfield-Mask: 0xff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ + #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_CMT_UNT_CM_CR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_CMT_UNT_CM_CR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_CMT_UNT_CM_CR_CMIE_Pos (6UL) /*!< CMIE (Bit 6) */ + #define R_CMT_UNT_CM_CR_CMIE_Msk (0x40UL) /*!< CMIE (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +/* ========================================================== COR ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ UNT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMSTR0 ========================================================= */ + #define R_CMT_UNT_CMSTR0_STR0_Pos (0UL) /*!< STR0 (Bit 0) */ + #define R_CMT_UNT_CMSTR0_STR0_Msk (0x1UL) /*!< STR0 (Bitfield-Mask: 0x01) */ + #define R_CMT_UNT_CMSTR0_STR1_Pos (1UL) /*!< STR1 (Bit 1) */ + #define R_CMT_UNT_CMSTR0_STR1_Msk (0x2UL) /*!< STR1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA0_Pos (0UL) /*!< SVA0 (Bit 0) */ + #define R_IIC0_SAR_L_SVA0_Msk (0x1UL) /*!< SVA0 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_L_SVA_Pos (1UL) /*!< SVA (Bit 1) */ + #define R_IIC0_SAR_L_SVA_Msk (0xfeUL) /*!< SVA (Bitfield-Mask: 0x7f) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA_Pos (1UL) /*!< SVA (Bit 1) */ + #define R_IIC0_SAR_U_SVA_Msk (0x6UL) /*!< SVA (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ N ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SA =========================================================== */ +/* ========================================================== DA =========================================================== */ +/* ========================================================== TB =========================================================== */ + +/* =========================================================================================================================== */ +/* ================ CH ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CRSA ========================================================== */ +/* ========================================================= CRDA ========================================================== */ +/* ========================================================= CRTB ========================================================== */ +/* ======================================================== CHSTAT ========================================================= */ + #define R_DMAC0_GRP_CH_CHSTAT_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_DMAC0_GRP_CH_CHSTAT_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_RQST_Pos (1UL) /*!< RQST (Bit 1) */ + #define R_DMAC0_GRP_CH_CHSTAT_RQST_Msk (0x2UL) /*!< RQST (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_TACT_Pos (2UL) /*!< TACT (Bit 2) */ + #define R_DMAC0_GRP_CH_CHSTAT_TACT_Msk (0x4UL) /*!< TACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_SUS_Pos (3UL) /*!< SUS (Bit 3) */ + #define R_DMAC0_GRP_CH_CHSTAT_SUS_Msk (0x8UL) /*!< SUS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_ER_Pos (4UL) /*!< ER (Bit 4) */ + #define R_DMAC0_GRP_CH_CHSTAT_ER_Msk (0x10UL) /*!< ER (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_END_Pos (5UL) /*!< END (Bit 5) */ + #define R_DMAC0_GRP_CH_CHSTAT_END_Msk (0x20UL) /*!< END (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_TC_Pos (6UL) /*!< TC (Bit 6) */ + #define R_DMAC0_GRP_CH_CHSTAT_TC_Msk (0x40UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_SR_Pos (7UL) /*!< SR (Bit 7) */ + #define R_DMAC0_GRP_CH_CHSTAT_SR_Msk (0x80UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_DL_Pos (8UL) /*!< DL (Bit 8) */ + #define R_DMAC0_GRP_CH_CHSTAT_DL_Msk (0x100UL) /*!< DL (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_DW_Pos (9UL) /*!< DW (Bit 9) */ + #define R_DMAC0_GRP_CH_CHSTAT_DW_Msk (0x200UL) /*!< DW (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_DER_Pos (10UL) /*!< DER (Bit 10) */ + #define R_DMAC0_GRP_CH_CHSTAT_DER_Msk (0x400UL) /*!< DER (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_MODE_Pos (11UL) /*!< MODE (Bit 11) */ + #define R_DMAC0_GRP_CH_CHSTAT_MODE_Msk (0x800UL) /*!< MODE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_INTM_Pos (16UL) /*!< INTM (Bit 16) */ + #define R_DMAC0_GRP_CH_CHSTAT_INTM_Msk (0x10000UL) /*!< INTM (Bitfield-Mask: 0x01) */ +/* ======================================================== CHCTRL ========================================================= */ + #define R_DMAC0_GRP_CH_CHCTRL_SETEN_Pos (0UL) /*!< SETEN (Bit 0) */ + #define R_DMAC0_GRP_CH_CHCTRL_SETEN_Msk (0x1UL) /*!< SETEN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLREN_Pos (1UL) /*!< CLREN (Bit 1) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLREN_Msk (0x2UL) /*!< CLREN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_STG_Pos (2UL) /*!< STG (Bit 2) */ + #define R_DMAC0_GRP_CH_CHCTRL_STG_Msk (0x4UL) /*!< STG (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_SWRST_Pos (3UL) /*!< SWRST (Bit 3) */ + #define R_DMAC0_GRP_CH_CHCTRL_SWRST_Msk (0x8UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRRQ_Pos (4UL) /*!< CLRRQ (Bit 4) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRRQ_Msk (0x10UL) /*!< CLRRQ (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLREND_Pos (5UL) /*!< CLREND (Bit 5) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLREND_Msk (0x20UL) /*!< CLREND (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRTC_Pos (6UL) /*!< CLRTC (Bit 6) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRTC_Msk (0x40UL) /*!< CLRTC (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_SETSUS_Pos (8UL) /*!< SETSUS (Bit 8) */ + #define R_DMAC0_GRP_CH_CHCTRL_SETSUS_Msk (0x100UL) /*!< SETSUS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRSUS_Pos (9UL) /*!< CLRSUS (Bit 9) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRSUS_Msk (0x200UL) /*!< CLRSUS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_SETINTM_Pos (16UL) /*!< SETINTM (Bit 16) */ + #define R_DMAC0_GRP_CH_CHCTRL_SETINTM_Msk (0x10000UL) /*!< SETINTM (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRINTM_Pos (17UL) /*!< CLRINTM (Bit 17) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRINTM_Msk (0x20000UL) /*!< CLRINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= CHCFG ========================================================= */ + #define R_DMAC0_GRP_CH_CHCFG_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_DMAC0_GRP_CH_CHCFG_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ + #define R_DMAC0_GRP_CH_CHCFG_REQD_Pos (3UL) /*!< REQD (Bit 3) */ + #define R_DMAC0_GRP_CH_CHCFG_REQD_Msk (0x8UL) /*!< REQD (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_LOEN_Pos (4UL) /*!< LOEN (Bit 4) */ + #define R_DMAC0_GRP_CH_CHCFG_LOEN_Msk (0x10UL) /*!< LOEN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_HIEN_Pos (5UL) /*!< HIEN (Bit 5) */ + #define R_DMAC0_GRP_CH_CHCFG_HIEN_Msk (0x20UL) /*!< HIEN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_LVL_Pos (6UL) /*!< LVL (Bit 6) */ + #define R_DMAC0_GRP_CH_CHCFG_LVL_Msk (0x40UL) /*!< LVL (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_AM_Pos (8UL) /*!< AM (Bit 8) */ + #define R_DMAC0_GRP_CH_CHCFG_AM_Msk (0x700UL) /*!< AM (Bitfield-Mask: 0x07) */ + #define R_DMAC0_GRP_CH_CHCFG_SDS_Pos (12UL) /*!< SDS (Bit 12) */ + #define R_DMAC0_GRP_CH_CHCFG_SDS_Msk (0xf000UL) /*!< SDS (Bitfield-Mask: 0x0f) */ + #define R_DMAC0_GRP_CH_CHCFG_DDS_Pos (16UL) /*!< DDS (Bit 16) */ + #define R_DMAC0_GRP_CH_CHCFG_DDS_Msk (0xf0000UL) /*!< DDS (Bitfield-Mask: 0x0f) */ + #define R_DMAC0_GRP_CH_CHCFG_SAD_Pos (20UL) /*!< SAD (Bit 20) */ + #define R_DMAC0_GRP_CH_CHCFG_SAD_Msk (0x100000UL) /*!< SAD (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_DAD_Pos (21UL) /*!< DAD (Bit 21) */ + #define R_DMAC0_GRP_CH_CHCFG_DAD_Msk (0x200000UL) /*!< DAD (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_TM_Pos (22UL) /*!< TM (Bit 22) */ + #define R_DMAC0_GRP_CH_CHCFG_TM_Msk (0x400000UL) /*!< TM (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_DEM_Pos (24UL) /*!< DEM (Bit 24) */ + #define R_DMAC0_GRP_CH_CHCFG_DEM_Msk (0x1000000UL) /*!< DEM (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_TCM_Pos (25UL) /*!< TCM (Bit 25) */ + #define R_DMAC0_GRP_CH_CHCFG_TCM_Msk (0x2000000UL) /*!< TCM (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_SBE_Pos (27UL) /*!< SBE (Bit 27) */ + #define R_DMAC0_GRP_CH_CHCFG_SBE_Msk (0x8000000UL) /*!< SBE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_RSEL_Pos (28UL) /*!< RSEL (Bit 28) */ + #define R_DMAC0_GRP_CH_CHCFG_RSEL_Msk (0x10000000UL) /*!< RSEL (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_RSW_Pos (29UL) /*!< RSW (Bit 29) */ + #define R_DMAC0_GRP_CH_CHCFG_RSW_Msk (0x20000000UL) /*!< RSW (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_REN_Pos (30UL) /*!< REN (Bit 30) */ + #define R_DMAC0_GRP_CH_CHCFG_REN_Msk (0x40000000UL) /*!< REN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_DMS_Pos (31UL) /*!< DMS (Bit 31) */ + #define R_DMAC0_GRP_CH_CHCFG_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */ +/* ======================================================== CHITVL ========================================================= */ + #define R_DMAC0_GRP_CH_CHITVL_ITVL_Pos (0UL) /*!< ITVL (Bit 0) */ + #define R_DMAC0_GRP_CH_CHITVL_ITVL_Msk (0xffffUL) /*!< ITVL (Bitfield-Mask: 0xffff) */ +/* ========================================================= CHEXT ========================================================= */ + #define R_DMAC0_GRP_CH_CHEXT_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_DMAC0_GRP_CH_CHEXT_SPR_Msk (0x7UL) /*!< SPR (Bitfield-Mask: 0x07) */ + #define R_DMAC0_GRP_CH_CHEXT_SCA_Pos (4UL) /*!< SCA (Bit 4) */ + #define R_DMAC0_GRP_CH_CHEXT_SCA_Msk (0xf0UL) /*!< SCA (Bitfield-Mask: 0x0f) */ + #define R_DMAC0_GRP_CH_CHEXT_DPR_Pos (8UL) /*!< DPR (Bit 8) */ + #define R_DMAC0_GRP_CH_CHEXT_DPR_Msk (0x700UL) /*!< DPR (Bitfield-Mask: 0x07) */ + #define R_DMAC0_GRP_CH_CHEXT_DCA_Pos (12UL) /*!< DCA (Bit 12) */ + #define R_DMAC0_GRP_CH_CHEXT_DCA_Msk (0xf000UL) /*!< DCA (Bitfield-Mask: 0x0f) */ +/* ========================================================= NXLA ========================================================== */ +/* ========================================================= CRLA ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ GRP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCTRL ========================================================= */ + #define R_DMAC0_GRP_DCTRL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMAC0_GRP_DCTRL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DCTRL_LVINT_Pos (1UL) /*!< LVINT (Bit 1) */ + #define R_DMAC0_GRP_DCTRL_LVINT_Msk (0x2UL) /*!< LVINT (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_EN ======================================================== */ + #define R_DMAC0_GRP_DSTAT_EN_EN0008_Pos (0UL) /*!< EN0008 (Bit 0) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0008_Msk (0x1UL) /*!< EN0008 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0109_Pos (1UL) /*!< EN0109 (Bit 1) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0109_Msk (0x2UL) /*!< EN0109 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0210_Pos (2UL) /*!< EN0210 (Bit 2) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0210_Msk (0x4UL) /*!< EN0210 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0311_Pos (3UL) /*!< EN0311 (Bit 3) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0311_Msk (0x8UL) /*!< EN0311 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0412_Pos (4UL) /*!< EN0412 (Bit 4) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0412_Msk (0x10UL) /*!< EN0412 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0513_Pos (5UL) /*!< EN0513 (Bit 5) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0513_Msk (0x20UL) /*!< EN0513 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0614_Pos (6UL) /*!< EN0614 (Bit 6) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0614_Msk (0x40UL) /*!< EN0614 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0715_Pos (7UL) /*!< EN0715 (Bit 7) */ + #define R_DMAC0_GRP_DSTAT_EN_EN0715_Msk (0x80UL) /*!< EN0715 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_ER ======================================================== */ + #define R_DMAC0_GRP_DSTAT_ER_ER0008_Pos (0UL) /*!< ER0008 (Bit 0) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0008_Msk (0x1UL) /*!< ER0008 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0109_Pos (1UL) /*!< ER0109 (Bit 1) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0109_Msk (0x2UL) /*!< ER0109 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0210_Pos (2UL) /*!< ER0210 (Bit 2) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0210_Msk (0x4UL) /*!< ER0210 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0311_Pos (3UL) /*!< ER0311 (Bit 3) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0311_Msk (0x8UL) /*!< ER0311 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0412_Pos (4UL) /*!< ER0412 (Bit 4) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0412_Msk (0x10UL) /*!< ER0412 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0513_Pos (5UL) /*!< ER0513 (Bit 5) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0513_Msk (0x20UL) /*!< ER0513 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0614_Pos (6UL) /*!< ER0614 (Bit 6) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0614_Msk (0x40UL) /*!< ER0614 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0715_Pos (7UL) /*!< ER0715 (Bit 7) */ + #define R_DMAC0_GRP_DSTAT_ER_ER0715_Msk (0x80UL) /*!< ER0715 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_END ======================================================= */ + #define R_DMAC0_GRP_DSTAT_END_END0008_Pos (0UL) /*!< END0008 (Bit 0) */ + #define R_DMAC0_GRP_DSTAT_END_END0008_Msk (0x1UL) /*!< END0008 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END0109_Pos (1UL) /*!< END0109 (Bit 1) */ + #define R_DMAC0_GRP_DSTAT_END_END0109_Msk (0x2UL) /*!< END0109 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END0210_Pos (2UL) /*!< END0210 (Bit 2) */ + #define R_DMAC0_GRP_DSTAT_END_END0210_Msk (0x4UL) /*!< END0210 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END0311_Pos (3UL) /*!< END0311 (Bit 3) */ + #define R_DMAC0_GRP_DSTAT_END_END0311_Msk (0x8UL) /*!< END0311 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END0412_Pos (4UL) /*!< END0412 (Bit 4) */ + #define R_DMAC0_GRP_DSTAT_END_END0412_Msk (0x10UL) /*!< END0412 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END0513_Pos (5UL) /*!< END0513 (Bit 5) */ + #define R_DMAC0_GRP_DSTAT_END_END0513_Msk (0x20UL) /*!< END0513 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END0614_Pos (6UL) /*!< END0614 (Bit 6) */ + #define R_DMAC0_GRP_DSTAT_END_END0614_Msk (0x40UL) /*!< END0614 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END0715_Pos (7UL) /*!< END0715 (Bit 7) */ + #define R_DMAC0_GRP_DSTAT_END_END0715_Msk (0x80UL) /*!< END0715 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_SUS ======================================================= */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0008_Pos (0UL) /*!< SUS0008 (Bit 0) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0008_Msk (0x1UL) /*!< SUS0008 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0109_Pos (1UL) /*!< SUS0109 (Bit 1) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0109_Msk (0x2UL) /*!< SUS0109 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0210_Pos (2UL) /*!< SUS0210 (Bit 2) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0210_Msk (0x4UL) /*!< SUS0210 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0311_Pos (3UL) /*!< SUS0311 (Bit 3) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0311_Msk (0x8UL) /*!< SUS0311 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0412_Pos (4UL) /*!< SUS0412 (Bit 4) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0412_Msk (0x10UL) /*!< SUS0412 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0513_Pos (5UL) /*!< SUS0513 (Bit 5) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0513_Msk (0x20UL) /*!< SUS0513 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0614_Pos (6UL) /*!< SUS0614 (Bit 6) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0614_Msk (0x40UL) /*!< SUS0614 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0715_Pos (7UL) /*!< SUS0715 (Bit 7) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS0715_Msk (0x80UL) /*!< SUS0715 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DRCTL ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_PORT_NSR_DRCTL_L_DRV0_Pos (0UL) /*!< DRV0 (Bit 0) */ + #define R_PORT_NSR_DRCTL_L_DRV0_Msk (0x3UL) /*!< DRV0 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_PUD0_Pos (2UL) /*!< PUD0 (Bit 2) */ + #define R_PORT_NSR_DRCTL_L_PUD0_Msk (0xcUL) /*!< PUD0 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_SMT0_Pos (4UL) /*!< SMT0 (Bit 4) */ + #define R_PORT_NSR_DRCTL_L_SMT0_Msk (0x10UL) /*!< SMT0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_SR0_Pos (5UL) /*!< SR0 (Bit 5) */ + #define R_PORT_NSR_DRCTL_L_SR0_Msk (0x20UL) /*!< SR0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_DRV1_Pos (8UL) /*!< DRV1 (Bit 8) */ + #define R_PORT_NSR_DRCTL_L_DRV1_Msk (0x300UL) /*!< DRV1 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_PUD1_Pos (10UL) /*!< PUD1 (Bit 10) */ + #define R_PORT_NSR_DRCTL_L_PUD1_Msk (0xc00UL) /*!< PUD1 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_SMT1_Pos (12UL) /*!< SMT1 (Bit 12) */ + #define R_PORT_NSR_DRCTL_L_SMT1_Msk (0x1000UL) /*!< SMT1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_SR1_Pos (13UL) /*!< SR1 (Bit 13) */ + #define R_PORT_NSR_DRCTL_L_SR1_Msk (0x2000UL) /*!< SR1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_DRV2_Pos (16UL) /*!< DRV2 (Bit 16) */ + #define R_PORT_NSR_DRCTL_L_DRV2_Msk (0x30000UL) /*!< DRV2 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_PUD2_Pos (18UL) /*!< PUD2 (Bit 18) */ + #define R_PORT_NSR_DRCTL_L_PUD2_Msk (0xc0000UL) /*!< PUD2 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_SMT2_Pos (20UL) /*!< SMT2 (Bit 20) */ + #define R_PORT_NSR_DRCTL_L_SMT2_Msk (0x100000UL) /*!< SMT2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_SR2_Pos (21UL) /*!< SR2 (Bit 21) */ + #define R_PORT_NSR_DRCTL_L_SR2_Msk (0x200000UL) /*!< SR2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_DRV3_Pos (24UL) /*!< DRV3 (Bit 24) */ + #define R_PORT_NSR_DRCTL_L_DRV3_Msk (0x3000000UL) /*!< DRV3 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_PUD3_Pos (26UL) /*!< PUD3 (Bit 26) */ + #define R_PORT_NSR_DRCTL_L_PUD3_Msk (0xc000000UL) /*!< PUD3 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_SMT3_Pos (28UL) /*!< SMT3 (Bit 28) */ + #define R_PORT_NSR_DRCTL_L_SMT3_Msk (0x10000000UL) /*!< SMT3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_SR3_Pos (29UL) /*!< SR3 (Bit 29) */ + #define R_PORT_NSR_DRCTL_L_SR3_Msk (0x20000000UL) /*!< SR3 (Bitfield-Mask: 0x01) */ +/* =========================================================== H =========================================================== */ + #define R_PORT_NSR_DRCTL_H_DRV4_Pos (0UL) /*!< DRV4 (Bit 0) */ + #define R_PORT_NSR_DRCTL_H_DRV4_Msk (0x3UL) /*!< DRV4 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_PUD4_Pos (2UL) /*!< PUD4 (Bit 2) */ + #define R_PORT_NSR_DRCTL_H_PUD4_Msk (0xcUL) /*!< PUD4 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_SMT4_Pos (4UL) /*!< SMT4 (Bit 4) */ + #define R_PORT_NSR_DRCTL_H_SMT4_Msk (0x10UL) /*!< SMT4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_SR4_Pos (5UL) /*!< SR4 (Bit 5) */ + #define R_PORT_NSR_DRCTL_H_SR4_Msk (0x20UL) /*!< SR4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_DRV5_Pos (8UL) /*!< DRV5 (Bit 8) */ + #define R_PORT_NSR_DRCTL_H_DRV5_Msk (0x300UL) /*!< DRV5 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_PUD5_Pos (10UL) /*!< PUD5 (Bit 10) */ + #define R_PORT_NSR_DRCTL_H_PUD5_Msk (0xc00UL) /*!< PUD5 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_SMT5_Pos (12UL) /*!< SMT5 (Bit 12) */ + #define R_PORT_NSR_DRCTL_H_SMT5_Msk (0x1000UL) /*!< SMT5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_SR5_Pos (13UL) /*!< SR5 (Bit 13) */ + #define R_PORT_NSR_DRCTL_H_SR5_Msk (0x2000UL) /*!< SR5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_DRV6_Pos (16UL) /*!< DRV6 (Bit 16) */ + #define R_PORT_NSR_DRCTL_H_DRV6_Msk (0x30000UL) /*!< DRV6 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_PUD6_Pos (18UL) /*!< PUD6 (Bit 18) */ + #define R_PORT_NSR_DRCTL_H_PUD6_Msk (0xc0000UL) /*!< PUD6 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_SMT6_Pos (20UL) /*!< SMT6 (Bit 20) */ + #define R_PORT_NSR_DRCTL_H_SMT6_Msk (0x100000UL) /*!< SMT6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_SR6_Pos (21UL) /*!< SR6 (Bit 21) */ + #define R_PORT_NSR_DRCTL_H_SR6_Msk (0x200000UL) /*!< SR6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_DRV7_Pos (24UL) /*!< DRV7 (Bit 24) */ + #define R_PORT_NSR_DRCTL_H_DRV7_Msk (0x3000000UL) /*!< DRV7 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_PUD7_Pos (26UL) /*!< PUD7 (Bit 26) */ + #define R_PORT_NSR_DRCTL_H_PUD7_Msk (0xc000000UL) /*!< PUD7 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_SMT7_Pos (28UL) /*!< SMT7 (Bit 28) */ + #define R_PORT_NSR_DRCTL_H_SMT7_Msk (0x10000000UL) /*!< SMT7 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_SR7_Pos (29UL) /*!< SR7 (Bit 29) */ + #define R_PORT_NSR_DRCTL_H_SR7_Msk (0x20000000UL) /*!< SR7 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELC_PDBF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_PORT_NSR_ELC_PDBF_BY_PB0_Pos (0UL) /*!< PB0 (Bit 0) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB0_Msk (0x1UL) /*!< PB0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB1_Pos (1UL) /*!< PB1 (Bit 1) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB1_Msk (0x2UL) /*!< PB1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB2_Pos (2UL) /*!< PB2 (Bit 2) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB2_Msk (0x4UL) /*!< PB2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB3_Pos (3UL) /*!< PB3 (Bit 3) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB3_Msk (0x8UL) /*!< PB3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB4_Pos (4UL) /*!< PB4 (Bit 4) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB4_Msk (0x10UL) /*!< PB4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB5_Pos (5UL) /*!< PB5 (Bit 5) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB5_Msk (0x20UL) /*!< PB5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB6_Pos (6UL) /*!< PB6 (Bit 6) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB6_Msk (0x40UL) /*!< PB6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB7_Pos (7UL) /*!< PB7 (Bit 7) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB7_Msk (0x80UL) /*!< PB7 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SWTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_ETHSW_PTP_SWTM_EN_OUTEN_Pos (0UL) /*!< OUTEN (Bit 0) */ + #define R_ETHSW_PTP_SWTM_EN_OUTEN_Msk (0x1UL) /*!< OUTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STSEC ========================================================= */ + #define R_ETHSW_PTP_SWTM_STSEC_STSEC_Pos (0UL) /*!< STSEC (Bit 0) */ + #define R_ETHSW_PTP_SWTM_STSEC_STSEC_Msk (0xffffffffUL) /*!< STSEC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STNS ========================================================== */ + #define R_ETHSW_PTP_SWTM_STNS_STNS_Pos (0UL) /*!< STNS (Bit 0) */ + #define R_ETHSW_PTP_SWTM_STNS_STNS_Msk (0xffffffffUL) /*!< STNS (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PSEC ========================================================== */ + #define R_ETHSW_PTP_SWTM_PSEC_PSEC_Pos (0UL) /*!< PSEC (Bit 0) */ + #define R_ETHSW_PTP_SWTM_PSEC_PSEC_Msk (0xffffffffUL) /*!< PSEC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== PNS ========================================================== */ + #define R_ETHSW_PTP_SWTM_PNS_PNS_Pos (0UL) /*!< PNS (Bit 0) */ + #define R_ETHSW_PTP_SWTM_PNS_PNS_Msk (0xffffffffUL) /*!< PNS (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== WTH ========================================================== */ + #define R_ETHSW_PTP_SWTM_WTH_WIDTH_Pos (0UL) /*!< WIDTH (Bit 0) */ + #define R_ETHSW_PTP_SWTM_WTH_WIDTH_Msk (0xffffUL) /*!< WIDTH (Bitfield-Mask: 0xffff) */ +/* ========================================================= MAXP ========================================================== */ + #define R_ETHSW_PTP_SWTM_MAXP_MAXP_Pos (0UL) /*!< MAXP (Bit 0) */ + #define R_ETHSW_PTP_SWTM_MAXP_MAXP_Msk (0xffffffffUL) /*!< MAXP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LATSEC ========================================================= */ + #define R_ETHSW_PTP_SWTM_LATSEC_LATSEC_Pos (0UL) /*!< LATSEC (Bit 0) */ + #define R_ETHSW_PTP_SWTM_LATSEC_LATSEC_Msk (0xffffffffUL) /*!< LATSEC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= LATNS ========================================================= */ + #define R_ETHSW_PTP_SWTM_LATNS_LATNS_Pos (0UL) /*!< LATNS (Bit 0) */ + #define R_ETHSW_PTP_SWTM_LATNS_LATNS_Msk (0xffffffffUL) /*!< LATNS (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ MGMT_ADDR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== lo =========================================================== */ + #define R_ETHSW_MGMT_ADDR_lo_BPDU_DST_Pos (0UL) /*!< BPDU_DST (Bit 0) */ + #define R_ETHSW_MGMT_ADDR_lo_BPDU_DST_Msk (0xffffffffUL) /*!< BPDU_DST (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== hi =========================================================== */ + #define R_ETHSW_MGMT_ADDR_hi_BPDU_DST_Pos (0UL) /*!< BPDU_DST (Bit 0) */ + #define R_ETHSW_MGMT_ADDR_hi_BPDU_DST_Msk (0xffffUL) /*!< BPDU_DST (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_MGMT_ADDR_hi_MASK_Pos (16UL) /*!< MASK (Bit 16) */ + #define R_ETHSW_MGMT_ADDR_hi_MASK_Msk (0xff0000UL) /*!< MASK (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ FMMU ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== L_START_ADR ====================================================== */ + #define R_ESC_FMMU_L_START_ADR_LSTAADR_Pos (0UL) /*!< LSTAADR (Bit 0) */ + #define R_ESC_FMMU_L_START_ADR_LSTAADR_Msk (0xffffffffUL) /*!< LSTAADR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== LEN ========================================================== */ + #define R_ESC_FMMU_LEN_FMMULEN_Pos (0UL) /*!< FMMULEN (Bit 0) */ + #define R_ESC_FMMU_LEN_FMMULEN_Msk (0xffffUL) /*!< FMMULEN (Bitfield-Mask: 0xffff) */ +/* ====================================================== L_START_BIT ====================================================== */ + #define R_ESC_FMMU_L_START_BIT_LSTABIT_Pos (0UL) /*!< LSTABIT (Bit 0) */ + #define R_ESC_FMMU_L_START_BIT_LSTABIT_Msk (0x7UL) /*!< LSTABIT (Bitfield-Mask: 0x07) */ +/* ====================================================== L_STOP_BIT ======================================================= */ + #define R_ESC_FMMU_L_STOP_BIT_LSTPBIT_Pos (0UL) /*!< LSTPBIT (Bit 0) */ + #define R_ESC_FMMU_L_STOP_BIT_LSTPBIT_Msk (0x7UL) /*!< LSTPBIT (Bitfield-Mask: 0x07) */ +/* ====================================================== P_START_ADR ====================================================== */ + #define R_ESC_FMMU_P_START_ADR_PHYSTAADR_Pos (0UL) /*!< PHYSTAADR (Bit 0) */ + #define R_ESC_FMMU_P_START_ADR_PHYSTAADR_Msk (0xffffUL) /*!< PHYSTAADR (Bitfield-Mask: 0xffff) */ +/* ====================================================== P_START_BIT ====================================================== */ + #define R_ESC_FMMU_P_START_BIT_PHYSTABIT_Pos (0UL) /*!< PHYSTABIT (Bit 0) */ + #define R_ESC_FMMU_P_START_BIT_PHYSTABIT_Msk (0x7UL) /*!< PHYSTABIT (Bitfield-Mask: 0x07) */ +/* ========================================================= TYPE ========================================================== */ + #define R_ESC_FMMU_TYPE_READ_Pos (0UL) /*!< READ (Bit 0) */ + #define R_ESC_FMMU_TYPE_READ_Msk (0x1UL) /*!< READ (Bitfield-Mask: 0x01) */ + #define R_ESC_FMMU_TYPE_WRITE_Pos (1UL) /*!< WRITE (Bit 1) */ + #define R_ESC_FMMU_TYPE_WRITE_Msk (0x2UL) /*!< WRITE (Bitfield-Mask: 0x01) */ +/* ========================================================== ACT ========================================================== */ + #define R_ESC_FMMU_ACT_ACTIVATE_Pos (0UL) /*!< ACTIVATE (Bit 0) */ + #define R_ESC_FMMU_ACT_ACTIVATE_Msk (0x1UL) /*!< ACTIVATE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SM ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== P_START_ADR ====================================================== */ + #define R_ESC_SM_P_START_ADR_SMSTAADDR_Pos (0UL) /*!< SMSTAADDR (Bit 0) */ + #define R_ESC_SM_P_START_ADR_SMSTAADDR_Msk (0xffffUL) /*!< SMSTAADDR (Bitfield-Mask: 0xffff) */ +/* ========================================================== LEN ========================================================== */ + #define R_ESC_SM_LEN_SMLEN_Pos (0UL) /*!< SMLEN (Bit 0) */ + #define R_ESC_SM_LEN_SMLEN_Msk (0xffffUL) /*!< SMLEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== CONTROL ======================================================== */ + #define R_ESC_SM_CONTROL_OPEMODE_Pos (0UL) /*!< OPEMODE (Bit 0) */ + #define R_ESC_SM_CONTROL_OPEMODE_Msk (0x3UL) /*!< OPEMODE (Bitfield-Mask: 0x03) */ + #define R_ESC_SM_CONTROL_DIR_Pos (2UL) /*!< DIR (Bit 2) */ + #define R_ESC_SM_CONTROL_DIR_Msk (0xcUL) /*!< DIR (Bitfield-Mask: 0x03) */ + #define R_ESC_SM_CONTROL_IRQECAT_Pos (4UL) /*!< IRQECAT (Bit 4) */ + #define R_ESC_SM_CONTROL_IRQECAT_Msk (0x10UL) /*!< IRQECAT (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_CONTROL_IRQPDI_Pos (5UL) /*!< IRQPDI (Bit 5) */ + #define R_ESC_SM_CONTROL_IRQPDI_Msk (0x20UL) /*!< IRQPDI (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_CONTROL_WDTRGEN_Pos (6UL) /*!< WDTRGEN (Bit 6) */ + #define R_ESC_SM_CONTROL_WDTRGEN_Msk (0x40UL) /*!< WDTRGEN (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ + #define R_ESC_SM_STATUS_INTWR_Pos (0UL) /*!< INTWR (Bit 0) */ + #define R_ESC_SM_STATUS_INTWR_Msk (0x1UL) /*!< INTWR (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_STATUS_INTRD_Pos (1UL) /*!< INTRD (Bit 1) */ + #define R_ESC_SM_STATUS_INTRD_Msk (0x2UL) /*!< INTRD (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_STATUS_MAILBOX_Pos (3UL) /*!< MAILBOX (Bit 3) */ + #define R_ESC_SM_STATUS_MAILBOX_Msk (0x8UL) /*!< MAILBOX (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_STATUS_BUFFERED_Pos (4UL) /*!< BUFFERED (Bit 4) */ + #define R_ESC_SM_STATUS_BUFFERED_Msk (0x30UL) /*!< BUFFERED (Bitfield-Mask: 0x03) */ + #define R_ESC_SM_STATUS_RDBUF_Pos (6UL) /*!< RDBUF (Bit 6) */ + #define R_ESC_SM_STATUS_RDBUF_Msk (0x40UL) /*!< RDBUF (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_STATUS_WRBUF_Pos (7UL) /*!< WRBUF (Bit 7) */ + #define R_ESC_SM_STATUS_WRBUF_Msk (0x80UL) /*!< WRBUF (Bitfield-Mask: 0x01) */ +/* ========================================================== ACT ========================================================== */ + #define R_ESC_SM_ACT_SMEN_Pos (0UL) /*!< SMEN (Bit 0) */ + #define R_ESC_SM_ACT_SMEN_Msk (0x1UL) /*!< SMEN (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_ACT_REPEATREQ_Pos (1UL) /*!< REPEATREQ (Bit 1) */ + #define R_ESC_SM_ACT_REPEATREQ_Msk (0x2UL) /*!< REPEATREQ (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_ACT_LATCHECAT_Pos (6UL) /*!< LATCHECAT (Bit 6) */ + #define R_ESC_SM_ACT_LATCHECAT_Msk (0x40UL) /*!< LATCHECAT (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_ACT_LATCHPDI_Pos (7UL) /*!< LATCHPDI (Bit 7) */ + #define R_ESC_SM_ACT_LATCHPDI_Msk (0x80UL) /*!< LATCHPDI (Bitfield-Mask: 0x01) */ +/* ======================================================= PDI_CONT ======================================================== */ + #define R_ESC_SM_PDI_CONT_DEACTIVE_Pos (0UL) /*!< DEACTIVE (Bit 0) */ + #define R_ESC_SM_PDI_CONT_DEACTIVE_Msk (0x1UL) /*!< DEACTIVE (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_PDI_CONT_REPEATACK_Pos (1UL) /*!< REPEATACK (Bit 1) */ + #define R_ESC_SM_PDI_CONT_REPEATACK_Msk (0x2UL) /*!< REPEATACK (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USBF_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USBF_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USBF_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USBF_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USBF_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ N ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SA =========================================================== */ + #define R_USBF_CHa_N_SA_SAWD_Pos (0UL) /*!< SAWD (Bit 0) */ + #define R_USBF_CHa_N_SA_SAWD_Msk (0xffffffffUL) /*!< SAWD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== DA =========================================================== */ + #define R_USBF_CHa_N_DA_DA_Pos (0UL) /*!< DA (Bit 0) */ + #define R_USBF_CHa_N_DA_DA_Msk (0xffffffffUL) /*!< DA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== TB =========================================================== */ + #define R_USBF_CHa_N_TB_TB_Pos (0UL) /*!< TB (Bit 0) */ + #define R_USBF_CHa_N_TB_TB_Msk (0xffffffffUL) /*!< TB (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CHa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CRSA ========================================================== */ + #define R_USBF_CHa_CRSA_CRSA_Pos (0UL) /*!< CRSA (Bit 0) */ + #define R_USBF_CHa_CRSA_CRSA_Msk (0xffffffffUL) /*!< CRSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CRDA ========================================================== */ + #define R_USBF_CHa_CRDA_CRDA_Pos (0UL) /*!< CRDA (Bit 0) */ + #define R_USBF_CHa_CRDA_CRDA_Msk (0xffffffffUL) /*!< CRDA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CRTB ========================================================== */ + #define R_USBF_CHa_CRTB_CRTB_Pos (0UL) /*!< CRTB (Bit 0) */ + #define R_USBF_CHa_CRTB_CRTB_Msk (0xffffffffUL) /*!< CRTB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CHSTAT ========================================================= */ + #define R_USBF_CHa_CHSTAT_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_USBF_CHa_CHSTAT_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_RQST_Pos (1UL) /*!< RQST (Bit 1) */ + #define R_USBF_CHa_CHSTAT_RQST_Msk (0x2UL) /*!< RQST (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_TACT_Pos (2UL) /*!< TACT (Bit 2) */ + #define R_USBF_CHa_CHSTAT_TACT_Msk (0x4UL) /*!< TACT (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_SUS_Pos (3UL) /*!< SUS (Bit 3) */ + #define R_USBF_CHa_CHSTAT_SUS_Msk (0x8UL) /*!< SUS (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_ER_Pos (4UL) /*!< ER (Bit 4) */ + #define R_USBF_CHa_CHSTAT_ER_Msk (0x10UL) /*!< ER (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_END_Pos (5UL) /*!< END (Bit 5) */ + #define R_USBF_CHa_CHSTAT_END_Msk (0x20UL) /*!< END (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_TC_Pos (6UL) /*!< TC (Bit 6) */ + #define R_USBF_CHa_CHSTAT_TC_Msk (0x40UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_SR_Pos (7UL) /*!< SR (Bit 7) */ + #define R_USBF_CHa_CHSTAT_SR_Msk (0x80UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_DL_Pos (8UL) /*!< DL (Bit 8) */ + #define R_USBF_CHa_CHSTAT_DL_Msk (0x100UL) /*!< DL (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_DW_Pos (9UL) /*!< DW (Bit 9) */ + #define R_USBF_CHa_CHSTAT_DW_Msk (0x200UL) /*!< DW (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_DER_Pos (10UL) /*!< DER (Bit 10) */ + #define R_USBF_CHa_CHSTAT_DER_Msk (0x400UL) /*!< DER (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_MODE_Pos (11UL) /*!< MODE (Bit 11) */ + #define R_USBF_CHa_CHSTAT_MODE_Msk (0x800UL) /*!< MODE (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_INTM_Pos (16UL) /*!< INTM (Bit 16) */ + #define R_USBF_CHa_CHSTAT_INTM_Msk (0x10000UL) /*!< INTM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_DMARQM_Pos (17UL) /*!< DMARQM (Bit 17) */ + #define R_USBF_CHa_CHSTAT_DMARQM_Msk (0x20000UL) /*!< DMARQM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_SWPRQ_Pos (18UL) /*!< SWPRQ (Bit 18) */ + #define R_USBF_CHa_CHSTAT_SWPRQ_Msk (0x40000UL) /*!< SWPRQ (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_DNUM_Pos (24UL) /*!< DNUM (Bit 24) */ + #define R_USBF_CHa_CHSTAT_DNUM_Msk (0xff000000UL) /*!< DNUM (Bitfield-Mask: 0xff) */ +/* ======================================================== CHCTRL ========================================================= */ + #define R_USBF_CHa_CHCTRL_SETEN_Pos (0UL) /*!< SETEN (Bit 0) */ + #define R_USBF_CHa_CHCTRL_SETEN_Msk (0x1UL) /*!< SETEN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLREN_Pos (1UL) /*!< CLREN (Bit 1) */ + #define R_USBF_CHa_CHCTRL_CLREN_Msk (0x2UL) /*!< CLREN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_STG_Pos (2UL) /*!< STG (Bit 2) */ + #define R_USBF_CHa_CHCTRL_STG_Msk (0x4UL) /*!< STG (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SWRST_Pos (3UL) /*!< SWRST (Bit 3) */ + #define R_USBF_CHa_CHCTRL_SWRST_Msk (0x8UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRRQ_Pos (4UL) /*!< CLRRQ (Bit 4) */ + #define R_USBF_CHa_CHCTRL_CLRRQ_Msk (0x10UL) /*!< CLRRQ (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLREND_Pos (5UL) /*!< CLREND (Bit 5) */ + #define R_USBF_CHa_CHCTRL_CLREND_Msk (0x20UL) /*!< CLREND (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRTC_Pos (6UL) /*!< CLRTC (Bit 6) */ + #define R_USBF_CHa_CHCTRL_CLRTC_Msk (0x40UL) /*!< CLRTC (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRDER_Pos (7UL) /*!< CLRDER (Bit 7) */ + #define R_USBF_CHa_CHCTRL_CLRDER_Msk (0x80UL) /*!< CLRDER (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SETSUS_Pos (8UL) /*!< SETSUS (Bit 8) */ + #define R_USBF_CHa_CHCTRL_SETSUS_Msk (0x100UL) /*!< SETSUS (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRSUS_Pos (9UL) /*!< CLRSUS (Bit 9) */ + #define R_USBF_CHa_CHCTRL_CLRSUS_Msk (0x200UL) /*!< CLRSUS (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SETREN_Pos (12UL) /*!< SETREN (Bit 12) */ + #define R_USBF_CHa_CHCTRL_SETREN_Msk (0x1000UL) /*!< SETREN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SETSSWPRQ_Pos (14UL) /*!< SETSSWPRQ (Bit 14) */ + #define R_USBF_CHa_CHCTRL_SETSSWPRQ_Msk (0x4000UL) /*!< SETSSWPRQ (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SETINTM_Pos (16UL) /*!< SETINTM (Bit 16) */ + #define R_USBF_CHa_CHCTRL_SETINTM_Msk (0x10000UL) /*!< SETINTM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRINTM_Pos (17UL) /*!< CLRINTM (Bit 17) */ + #define R_USBF_CHa_CHCTRL_CLRINTM_Msk (0x20000UL) /*!< CLRINTM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SETDMARQM_Pos (18UL) /*!< SETDMARQM (Bit 18) */ + #define R_USBF_CHa_CHCTRL_SETDMARQM_Msk (0x40000UL) /*!< SETDMARQM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRDMARQM_Pos (19UL) /*!< CLRDMARQM (Bit 19) */ + #define R_USBF_CHa_CHCTRL_CLRDMARQM_Msk (0x80000UL) /*!< CLRDMARQM (Bitfield-Mask: 0x01) */ +/* ========================================================= CHCFG ========================================================= */ + #define R_USBF_CHa_CHCFG_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_USBF_CHa_CHCFG_SEL_Msk (0x1UL) /*!< SEL (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_REQD_Pos (3UL) /*!< REQD (Bit 3) */ + #define R_USBF_CHa_CHCFG_REQD_Msk (0x8UL) /*!< REQD (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_LOEN_Pos (4UL) /*!< LOEN (Bit 4) */ + #define R_USBF_CHa_CHCFG_LOEN_Msk (0x10UL) /*!< LOEN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_HIEN_Pos (5UL) /*!< HIEN (Bit 5) */ + #define R_USBF_CHa_CHCFG_HIEN_Msk (0x20UL) /*!< HIEN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_LVL_Pos (6UL) /*!< LVL (Bit 6) */ + #define R_USBF_CHa_CHCFG_LVL_Msk (0x40UL) /*!< LVL (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_AM_Pos (8UL) /*!< AM (Bit 8) */ + #define R_USBF_CHa_CHCFG_AM_Msk (0x700UL) /*!< AM (Bitfield-Mask: 0x07) */ + #define R_USBF_CHa_CHCFG_DRRP_Pos (11UL) /*!< DRRP (Bit 11) */ + #define R_USBF_CHa_CHCFG_DRRP_Msk (0x800UL) /*!< DRRP (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_SDS_Pos (12UL) /*!< SDS (Bit 12) */ + #define R_USBF_CHa_CHCFG_SDS_Msk (0xf000UL) /*!< SDS (Bitfield-Mask: 0x0f) */ + #define R_USBF_CHa_CHCFG_DDS_Pos (16UL) /*!< DDS (Bit 16) */ + #define R_USBF_CHa_CHCFG_DDS_Msk (0xf0000UL) /*!< DDS (Bitfield-Mask: 0x0f) */ + #define R_USBF_CHa_CHCFG_SAD_Pos (20UL) /*!< SAD (Bit 20) */ + #define R_USBF_CHa_CHCFG_SAD_Msk (0x100000UL) /*!< SAD (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_DAD_Pos (21UL) /*!< DAD (Bit 21) */ + #define R_USBF_CHa_CHCFG_DAD_Msk (0x200000UL) /*!< DAD (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_TM_Pos (22UL) /*!< TM (Bit 22) */ + #define R_USBF_CHa_CHCFG_TM_Msk (0x400000UL) /*!< TM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_WONLY_Pos (23UL) /*!< WONLY (Bit 23) */ + #define R_USBF_CHa_CHCFG_WONLY_Msk (0x800000UL) /*!< WONLY (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_DEM_Pos (24UL) /*!< DEM (Bit 24) */ + #define R_USBF_CHa_CHCFG_DEM_Msk (0x1000000UL) /*!< DEM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_DIM_Pos (26UL) /*!< DIM (Bit 26) */ + #define R_USBF_CHa_CHCFG_DIM_Msk (0x4000000UL) /*!< DIM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_SBE_Pos (27UL) /*!< SBE (Bit 27) */ + #define R_USBF_CHa_CHCFG_SBE_Msk (0x8000000UL) /*!< SBE (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_RSEL_Pos (28UL) /*!< RSEL (Bit 28) */ + #define R_USBF_CHa_CHCFG_RSEL_Msk (0x10000000UL) /*!< RSEL (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_RSW_Pos (29UL) /*!< RSW (Bit 29) */ + #define R_USBF_CHa_CHCFG_RSW_Msk (0x20000000UL) /*!< RSW (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_REN_Pos (30UL) /*!< REN (Bit 30) */ + #define R_USBF_CHa_CHCFG_REN_Msk (0x40000000UL) /*!< REN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_DMS_Pos (31UL) /*!< DMS (Bit 31) */ + #define R_USBF_CHa_CHCFG_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */ +/* ======================================================== CHITVL ========================================================= */ + #define R_USBF_CHa_CHITVL_ITVL_Pos (0UL) /*!< ITVL (Bit 0) */ + #define R_USBF_CHa_CHITVL_ITVL_Msk (0xffffUL) /*!< ITVL (Bitfield-Mask: 0xffff) */ +/* ========================================================= CHEXT ========================================================= */ + #define R_USBF_CHa_CHEXT_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_USBF_CHa_CHEXT_SPR_Msk (0xfUL) /*!< SPR (Bitfield-Mask: 0x0f) */ + #define R_USBF_CHa_CHEXT_DPR_Pos (8UL) /*!< DPR (Bit 8) */ + #define R_USBF_CHa_CHEXT_DPR_Msk (0xf00UL) /*!< DPR (Bitfield-Mask: 0x0f) */ +/* ========================================================= NXLA ========================================================== */ + #define R_USBF_CHa_NXLA_NXLA_Pos (0UL) /*!< NXLA (Bit 0) */ + #define R_USBF_CHa_NXLA_NXLA_Msk (0xffffffffUL) /*!< NXLA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CRLA ========================================================== */ + #define R_USBF_CHa_CRLA_CRLA_Pos (0UL) /*!< CRLA (Bit 0) */ + #define R_USBF_CHa_CRLA_CRLA_Msk (0xffffffffUL) /*!< CRLA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CHb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SCNT ========================================================== */ + #define R_USBF_CHb_SCNT_SCNT_Pos (0UL) /*!< SCNT (Bit 0) */ + #define R_USBF_CHb_SCNT_SCNT_Msk (0xffffffffUL) /*!< SCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SSKP ========================================================== */ + #define R_USBF_CHb_SSKP_SSKP_Pos (0UL) /*!< SSKP (Bit 0) */ + #define R_USBF_CHb_SSKP_SSKP_Msk (0xffffffffUL) /*!< SSKP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DCNT ========================================================== */ + #define R_USBF_CHb_DCNT_DCNT_Pos (0UL) /*!< DCNT (Bit 0) */ + #define R_USBF_CHb_DCNT_DCNT_Msk (0xffffffffUL) /*!< DCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DSKP ========================================================== */ + #define R_USBF_CHb_DSKP_DSKP_Pos (0UL) /*!< DSKP (Bit 0) */ + #define R_USBF_CHb_DSKP_DSKP_Msk (0xffffffffUL) /*!< DSKP (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMCFG0 ========================================================= */ + #define R_XSPI0_CSa_CMCFG0_FFMT_Pos (0UL) /*!< FFMT (Bit 0) */ + #define R_XSPI0_CSa_CMCFG0_FFMT_Msk (0x3UL) /*!< FFMT (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CSa_CMCFG0_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_CSa_CMCFG0_ADDSIZE_Msk (0xcUL) /*!< ADDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CSa_CMCFG0_ADDRPEN_Pos (16UL) /*!< ADDRPEN (Bit 16) */ + #define R_XSPI0_CSa_CMCFG0_ADDRPEN_Msk (0xff0000UL) /*!< ADDRPEN (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CSa_CMCFG0_ADDRPCD_Pos (24UL) /*!< ADDRPCD (Bit 24) */ + #define R_XSPI0_CSa_CMCFG0_ADDRPCD_Msk (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff) */ +/* ======================================================== CMCFG1 ========================================================= */ + #define R_XSPI0_CSa_CMCFG1_RDCMD_Pos (0UL) /*!< RDCMD (Bit 0) */ + #define R_XSPI0_CSa_CMCFG1_RDCMD_Msk (0xffffUL) /*!< RDCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CSa_CMCFG1_RDLATE_Pos (16UL) /*!< RDLATE (Bit 16) */ + #define R_XSPI0_CSa_CMCFG1_RDLATE_Msk (0x1f0000UL) /*!< RDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CMCFG2 ========================================================= */ + #define R_XSPI0_CSa_CMCFG2_WRCMD_Pos (0UL) /*!< WRCMD (Bit 0) */ + #define R_XSPI0_CSa_CMCFG2_WRCMD_Msk (0xffffUL) /*!< WRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CSa_CMCFG2_WRLATE_Pos (16UL) /*!< WRLATE (Bit 16) */ + #define R_XSPI0_CSa_CMCFG2_WRLATE_Msk (0x1f0000UL) /*!< WRLATE (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ BUF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CDT ========================================================== */ + #define R_XSPI0_BUF_CDT_CMDSIZE_Pos (0UL) /*!< CMDSIZE (Bit 0) */ + #define R_XSPI0_BUF_CDT_CMDSIZE_Msk (0x3UL) /*!< CMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BUF_CDT_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_BUF_CDT_ADDSIZE_Msk (0x1cUL) /*!< ADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_BUF_CDT_DATASIZE_Pos (5UL) /*!< DATASIZE (Bit 5) */ + #define R_XSPI0_BUF_CDT_DATASIZE_Msk (0x1e0UL) /*!< DATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_BUF_CDT_LATE_Pos (9UL) /*!< LATE (Bit 9) */ + #define R_XSPI0_BUF_CDT_LATE_Msk (0x3e00UL) /*!< LATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_BUF_CDT_TRTYPE_Pos (15UL) /*!< TRTYPE (Bit 15) */ + #define R_XSPI0_BUF_CDT_TRTYPE_Msk (0x8000UL) /*!< TRTYPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BUF_CDT_CMD_Pos (16UL) /*!< CMD (Bit 16) */ + #define R_XSPI0_BUF_CDT_CMD_Msk (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff) */ +/* ========================================================== CDA ========================================================== */ + #define R_XSPI0_BUF_CDA_ADD_Pos (0UL) /*!< ADD (Bit 0) */ + #define R_XSPI0_BUF_CDA_ADD_Msk (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD0 ========================================================== */ + #define R_XSPI0_BUF_CDD0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_BUF_CDD0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD1 ========================================================== */ + #define R_XSPI0_BUF_CDD1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_BUF_CDD1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCCTL0 ========================================================= */ + #define R_XSPI0_CSb_CCCTL0_CAEN_Pos (0UL) /*!< CAEN (Bit 0) */ + #define R_XSPI0_CSb_CCCTL0_CAEN_Msk (0x1UL) /*!< CAEN (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CSb_CCCTL0_CANOWR_Pos (1UL) /*!< CANOWR (Bit 1) */ + #define R_XSPI0_CSb_CCCTL0_CANOWR_Msk (0x2UL) /*!< CANOWR (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CSb_CCCTL0_CAITV_Pos (8UL) /*!< CAITV (Bit 8) */ + #define R_XSPI0_CSb_CCCTL0_CAITV_Msk (0x1f00UL) /*!< CAITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CSb_CCCTL0_CASFTSTA_Pos (16UL) /*!< CASFTSTA (Bit 16) */ + #define R_XSPI0_CSb_CCCTL0_CASFTSTA_Msk (0x1f0000UL) /*!< CASFTSTA (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CSb_CCCTL0_CASFTEND_Pos (24UL) /*!< CASFTEND (Bit 24) */ + #define R_XSPI0_CSb_CCCTL0_CASFTEND_Msk (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL1 ========================================================= */ + #define R_XSPI0_CSb_CCCTL1_CACMDSIZE_Pos (0UL) /*!< CACMDSIZE (Bit 0) */ + #define R_XSPI0_CSb_CCCTL1_CACMDSIZE_Msk (0x3UL) /*!< CACMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CSb_CCCTL1_CAADDSIZE_Pos (2UL) /*!< CAADDSIZE (Bit 2) */ + #define R_XSPI0_CSb_CCCTL1_CAADDSIZE_Msk (0x1cUL) /*!< CAADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_CSb_CCCTL1_CADATASIZE_Pos (5UL) /*!< CADATASIZE (Bit 5) */ + #define R_XSPI0_CSb_CCCTL1_CADATASIZE_Msk (0x1e0UL) /*!< CADATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_CSb_CCCTL1_CAWRLATE_Pos (16UL) /*!< CAWRLATE (Bit 16) */ + #define R_XSPI0_CSb_CCCTL1_CAWRLATE_Msk (0x1f0000UL) /*!< CAWRLATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CSb_CCCTL1_CARDLATE_Pos (24UL) /*!< CARDLATE (Bit 24) */ + #define R_XSPI0_CSb_CCCTL1_CARDLATE_Msk (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL2 ========================================================= */ + #define R_XSPI0_CSb_CCCTL2_CAWRCMD_Pos (0UL) /*!< CAWRCMD (Bit 0) */ + #define R_XSPI0_CSb_CCCTL2_CAWRCMD_Msk (0xffffUL) /*!< CAWRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CSb_CCCTL2_CARDCMD_Pos (16UL) /*!< CARDCMD (Bit 16) */ + #define R_XSPI0_CSb_CCCTL2_CARDCMD_Msk (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff) */ +/* ======================================================== CCCTL3 ========================================================= */ + #define R_XSPI0_CSb_CCCTL3_CAADD_Pos (0UL) /*!< CAADD (Bit 0) */ + #define R_XSPI0_CSb_CCCTL3_CAADD_Msk (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL4 ========================================================= */ + #define R_XSPI0_CSb_CCCTL4_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CSb_CCCTL4_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL5 ========================================================= */ + #define R_XSPI0_CSb_CCCTL5_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CSb_CCCTL5_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL6 ========================================================= */ + #define R_XSPI0_CSb_CCCTL6_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CSb_CCCTL6_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL7 ========================================================= */ + #define R_XSPI0_CSb_CCCTL7_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CSb_CCCTL7_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ W ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_SYSRAM0_W_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_SYSRAM0_W_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_SYSRAM0_W_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_SYSRAM0_W_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_SYSRAM0_W_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_SYSRAM0_W_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_SYSRAM0_W_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_SYSRAM0_W_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECTHM_Pos (7UL) /*!< ECTHM (Bit 7) */ + #define R_SYSRAM0_W_EC710CTL_ECTHM_Msk (0x80UL) /*!< ECTHM (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_SYSRAM0_W_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_SYSRAM0_W_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_SYSRAM0_W_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_SYSRAM0_W_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF0_Pos (16UL) /*!< ECEDF0 (Bit 16) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF0_Msk (0x30000UL) /*!< ECEDF0 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF1_Pos (18UL) /*!< ECEDF1 (Bit 18) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF1_Msk (0xc0000UL) /*!< ECEDF1 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF2_Pos (20UL) /*!< ECEDF2 (Bit 20) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF2_Msk (0x300000UL) /*!< ECEDF2 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF3_Pos (22UL) /*!< ECEDF3 (Bit 22) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF3_Msk (0xc00000UL) /*!< ECEDF3 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF4_Pos (24UL) /*!< ECEDF4 (Bit 24) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF4_Msk (0x3000000UL) /*!< ECEDF4 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF5_Pos (26UL) /*!< ECEDF5 (Bit 26) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF5_Msk (0xc000000UL) /*!< ECEDF5 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF6_Pos (28UL) /*!< ECEDF6 (Bit 28) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF6_Msk (0x30000000UL) /*!< ECEDF6 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF7_Pos (30UL) /*!< ECEDF7 (Bit 30) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF7_Msk (0xc0000000UL) /*!< ECEDF7 (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_SYSRAM0_W_EC710TMC_ECREIS_Pos (0UL) /*!< ECREIS (Bit 0) */ + #define R_SYSRAM0_W_EC710TMC_ECREIS_Msk (0x1UL) /*!< ECREIS (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_SYSRAM0_W_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ECENS_Pos (2UL) /*!< ECENS (Bit 2) */ + #define R_SYSRAM0_W_EC710TMC_ECENS_Msk (0x4UL) /*!< ECENS (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ECREOS_Pos (3UL) /*!< ECREOS (Bit 3) */ + #define R_SYSRAM0_W_EC710TMC_ECREOS_Msk (0x8UL) /*!< ECREOS (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ECTRRS_Pos (4UL) /*!< ECTRRS (Bit 4) */ + #define R_SYSRAM0_W_EC710TMC_ECTRRS_Msk (0x10UL) /*!< ECTRRS (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_SYSRAM0_W_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_SYSRAM0_W_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TRC ======================================================== */ + #define R_SYSRAM0_W_EC710TRC_ECERDB_Pos (0UL) /*!< ECERDB (Bit 0) */ + #define R_SYSRAM0_W_EC710TRC_ECERDB_Msk (0x7fUL) /*!< ECERDB (Bitfield-Mask: 0x7f) */ + #define R_SYSRAM0_W_EC710TRC_ECECRD_Pos (8UL) /*!< ECECRD (Bit 8) */ + #define R_SYSRAM0_W_EC710TRC_ECECRD_Msk (0x7f00UL) /*!< ECECRD (Bitfield-Mask: 0x7f) */ + #define R_SYSRAM0_W_EC710TRC_ECHORD_Pos (16UL) /*!< ECHORD (Bit 16) */ + #define R_SYSRAM0_W_EC710TRC_ECHORD_Msk (0x7f0000UL) /*!< ECHORD (Bitfield-Mask: 0x7f) */ + #define R_SYSRAM0_W_EC710TRC_ECSYND_Pos (24UL) /*!< ECSYND (Bit 24) */ + #define R_SYSRAM0_W_EC710TRC_ECSYND_Msk (0x7f000000UL) /*!< ECSYND (Bitfield-Mask: 0x7f) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_SYSRAM0_W_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_SYSRAM0_W_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD ======================================================== */ + #define R_SYSRAM0_W_EC710EAD_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_SYSRAM0_W_EC710EAD_ECEAD_Msk (0x7fffUL) /*!< ECEAD (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ RGN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STADD ========================================================= */ + #define R_MPU0_RGN_STADD_RDPR_Pos (0UL) /*!< RDPR (Bit 0) */ + #define R_MPU0_RGN_STADD_RDPR_Msk (0x1UL) /*!< RDPR (Bitfield-Mask: 0x01) */ + #define R_MPU0_RGN_STADD_WRPR_Pos (1UL) /*!< WRPR (Bit 1) */ + #define R_MPU0_RGN_STADD_WRPR_Msk (0x2UL) /*!< WRPR (Bitfield-Mask: 0x01) */ + #define R_MPU0_RGN_STADD_STADDR_Pos (10UL) /*!< STADDR (Bit 10) */ + #define R_MPU0_RGN_STADD_STADDR_Msk (0xfffffc00UL) /*!< STADDR (Bitfield-Mask: 0x3fffff) */ +/* ======================================================== ENDADD ========================================================= */ + #define R_MPU0_RGN_ENDADD_ENDADDR_Pos (10UL) /*!< ENDADDR (Bit 10) */ + #define R_MPU0_RGN_ENDADD_ENDADDR_Msk (0xfffffc00UL) /*!< ENDADDR (Bitfield-Mask: 0x3fffff) */ + +/* =========================================================================================================================== */ +/* ================ CH ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DSICR ========================================================= */ + #define R_DSMIF0_CH_DSICR_IOEL_Pos (0UL) /*!< IOEL (Bit 0) */ + #define R_DSMIF0_CH_DSICR_IOEL_Msk (0x1UL) /*!< IOEL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_IOEH_Pos (1UL) /*!< IOEH (Bit 1) */ + #define R_DSMIF0_CH_DSICR_IOEH_Msk (0x2UL) /*!< IOEH (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_ISE_Pos (2UL) /*!< ISE (Bit 2) */ + #define R_DSMIF0_CH_DSICR_ISE_Msk (0x4UL) /*!< ISE (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_IUE_Pos (3UL) /*!< IUE (Bit 3) */ + #define R_DSMIF0_CH_DSICR_IUE_Msk (0x8UL) /*!< IUE (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCMCCR ======================================================== */ + #define R_DSMIF0_CH_DSCMCCR_CKDIR_Pos (0UL) /*!< CKDIR (Bit 0) */ + #define R_DSMIF0_CH_DSCMCCR_CKDIR_Msk (0x1UL) /*!< CKDIR (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCMCCR_SEDGE_Pos (7UL) /*!< SEDGE (Bit 7) */ + #define R_DSMIF0_CH_DSCMCCR_SEDGE_Msk (0x80UL) /*!< SEDGE (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCMCCR_CKDIV_Pos (8UL) /*!< CKDIV (Bit 8) */ + #define R_DSMIF0_CH_DSCMCCR_CKDIV_Msk (0x3f00UL) /*!< CKDIV (Bitfield-Mask: 0x3f) */ +/* ======================================================== DSCMFCR ======================================================== */ + #define R_DSMIF0_CH_DSCMFCR_CMSINC_Pos (0UL) /*!< CMSINC (Bit 0) */ + #define R_DSMIF0_CH_DSCMFCR_CMSINC_Msk (0x3UL) /*!< CMSINC (Bitfield-Mask: 0x03) */ + #define R_DSMIF0_CH_DSCMFCR_CMDEC_Pos (8UL) /*!< CMDEC (Bit 8) */ + #define R_DSMIF0_CH_DSCMFCR_CMDEC_Msk (0xff00UL) /*!< CMDEC (Bitfield-Mask: 0xff) */ + #define R_DSMIF0_CH_DSCMFCR_CMSH_Pos (16UL) /*!< CMSH (Bit 16) */ + #define R_DSMIF0_CH_DSCMFCR_CMSH_Msk (0x1f0000UL) /*!< CMSH (Bitfield-Mask: 0x1f) */ +/* ======================================================= DSCMCTCR ======================================================== */ + #define R_DSMIF0_CH_DSCMCTCR_CTSELA_Pos (0UL) /*!< CTSELA (Bit 0) */ + #define R_DSMIF0_CH_DSCMCTCR_CTSELA_Msk (0x7UL) /*!< CTSELA (Bitfield-Mask: 0x07) */ + #define R_DSMIF0_CH_DSCMCTCR_CTSELB_Pos (8UL) /*!< CTSELB (Bit 8) */ + #define R_DSMIF0_CH_DSCMCTCR_CTSELB_Msk (0x700UL) /*!< CTSELB (Bitfield-Mask: 0x07) */ + #define R_DSMIF0_CH_DSCMCTCR_DITSEL_Pos (16UL) /*!< DITSEL (Bit 16) */ + #define R_DSMIF0_CH_DSCMCTCR_DITSEL_Msk (0x30000UL) /*!< DITSEL (Bitfield-Mask: 0x03) */ + #define R_DSMIF0_CH_DSCMCTCR_DEDGE_Pos (23UL) /*!< DEDGE (Bit 23) */ + #define R_DSMIF0_CH_DSCMCTCR_DEDGE_Msk (0x800000UL) /*!< DEDGE (Bitfield-Mask: 0x01) */ +/* ======================================================== DSEDCR ========================================================= */ + #define R_DSMIF0_CH_DSEDCR_SDE_Pos (0UL) /*!< SDE (Bit 0) */ + #define R_DSMIF0_CH_DSEDCR_SDE_Msk (0x1UL) /*!< SDE (Bitfield-Mask: 0x01) */ +/* ======================================================== DSOCFCR ======================================================== */ + #define R_DSMIF0_CH_DSOCFCR_OCSINC_Pos (0UL) /*!< OCSINC (Bit 0) */ + #define R_DSMIF0_CH_DSOCFCR_OCSINC_Msk (0x3UL) /*!< OCSINC (Bitfield-Mask: 0x03) */ + #define R_DSMIF0_CH_DSOCFCR_OCDEC_Pos (8UL) /*!< OCDEC (Bit 8) */ + #define R_DSMIF0_CH_DSOCFCR_OCDEC_Msk (0xff00UL) /*!< OCDEC (Bitfield-Mask: 0xff) */ + #define R_DSMIF0_CH_DSOCFCR_OCSH_Pos (16UL) /*!< OCSH (Bit 16) */ + #define R_DSMIF0_CH_DSOCFCR_OCSH_Msk (0x1f0000UL) /*!< OCSH (Bitfield-Mask: 0x1f) */ +/* ======================================================== DSOCLTR ======================================================== */ + #define R_DSMIF0_CH_DSOCLTR_OCMPTBL_Pos (0UL) /*!< OCMPTBL (Bit 0) */ + #define R_DSMIF0_CH_DSOCLTR_OCMPTBL_Msk (0xffffUL) /*!< OCMPTBL (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSOCHTR ======================================================== */ + #define R_DSMIF0_CH_DSOCHTR_OCMPTBH_Pos (0UL) /*!< OCMPTBH (Bit 0) */ + #define R_DSMIF0_CH_DSOCHTR_OCMPTBH_Msk (0xffffUL) /*!< OCMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSSCTSR ======================================================== */ + #define R_DSMIF0_CH_DSSCTSR_SCNTL_Pos (0UL) /*!< SCNTL (Bit 0) */ + #define R_DSMIF0_CH_DSSCTSR_SCNTL_Msk (0x1fffUL) /*!< SCNTL (Bitfield-Mask: 0x1fff) */ + #define R_DSMIF0_CH_DSSCTSR_SCNTH_Pos (16UL) /*!< SCNTH (Bit 16) */ + #define R_DSMIF0_CH_DSSCTSR_SCNTH_Msk (0x1fff0000UL) /*!< SCNTH (Bitfield-Mask: 0x1fff) */ +/* ======================================================== DSODCR ========================================================= */ + #define R_DSMIF0_CH_DSODCR_ODEL_Pos (0UL) /*!< ODEL (Bit 0) */ + #define R_DSMIF0_CH_DSODCR_ODEL_Msk (0x1UL) /*!< ODEL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSODCR_ODEH_Pos (1UL) /*!< ODEH (Bit 1) */ + #define R_DSMIF0_CH_DSODCR_ODEH_Msk (0x2UL) /*!< ODEH (Bitfield-Mask: 0x01) */ +/* ======================================================= DSCSTRTR ======================================================== */ + #define R_DSMIF0_CH_DSCSTRTR_STRTRG_Pos (0UL) /*!< STRTRG (Bit 0) */ + #define R_DSMIF0_CH_DSCSTRTR_STRTRG_Msk (0x1UL) /*!< STRTRG (Bitfield-Mask: 0x01) */ +/* ======================================================= DSCSTPTR ======================================================== */ + #define R_DSMIF0_CH_DSCSTPTR_STPTRG_Pos (0UL) /*!< STPTRG (Bit 0) */ + #define R_DSMIF0_CH_DSCSTPTR_STPTRG_Msk (0x1UL) /*!< STPTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= DSCDR ========================================================= */ + #define R_DSMIF0_CH_DSCDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_DSMIF0_CH_DSCDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSCCDRA ======================================================== */ + #define R_DSMIF0_CH_DSCCDRA_CDRA_Pos (0UL) /*!< CDRA (Bit 0) */ + #define R_DSMIF0_CH_DSCCDRA_CDRA_Msk (0xffffUL) /*!< CDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSCCDRB ======================================================== */ + #define R_DSMIF0_CH_DSCCDRB_CDRB_Pos (0UL) /*!< CDRB (Bit 0) */ + #define R_DSMIF0_CH_DSCCDRB_CDRB_Msk (0xffffUL) /*!< CDRB (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSOCDR ========================================================= */ + #define R_DSMIF0_CH_DSOCDR_ODR_Pos (0UL) /*!< ODR (Bit 0) */ + #define R_DSMIF0_CH_DSOCDR_ODR_Msk (0xffffUL) /*!< ODR (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSCOCDR ======================================================== */ + #define R_DSMIF0_CH_DSCOCDR_CODR_Pos (0UL) /*!< CODR (Bit 0) */ + #define R_DSMIF0_CH_DSCOCDR_CODR_Msk (0xffffUL) /*!< CODR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DSCSR ========================================================= */ + #define R_DSMIF0_CH_DSCSR_DUF_Pos (0UL) /*!< DUF (Bit 0) */ + #define R_DSMIF0_CH_DSCSR_DUF_Msk (0x1UL) /*!< DUF (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OCFL_Pos (1UL) /*!< OCFL (Bit 1) */ + #define R_DSMIF0_CH_DSCSR_OCFL_Msk (0x2UL) /*!< OCFL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OCFH_Pos (2UL) /*!< OCFH (Bit 2) */ + #define R_DSMIF0_CH_DSCSR_OCFH_Msk (0x4UL) /*!< OCFH (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_SCF_Pos (3UL) /*!< SCF (Bit 3) */ + #define R_DSMIF0_CH_DSCSR_SCF_Msk (0x8UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_CHSTATE_Pos (16UL) /*!< CHSTATE (Bit 16) */ + #define R_DSMIF0_CH_DSCSR_CHSTATE_Msk (0x10000UL) /*!< CHSTATE (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCSCR ========================================================= */ + #define R_DSMIF0_CH_DSCSCR_CLRDUF_Pos (0UL) /*!< CLRDUF (Bit 0) */ + #define R_DSMIF0_CH_DSCSCR_CLRDUF_Msk (0x1UL) /*!< CLRDUF (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLROCFL_Pos (1UL) /*!< CLROCFL (Bit 1) */ + #define R_DSMIF0_CH_DSCSCR_CLROCFL_Msk (0x2UL) /*!< CLROCFL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLROCFH_Pos (2UL) /*!< CLROCFH (Bit 2) */ + #define R_DSMIF0_CH_DSCSCR_CLROCFH_Msk (0x4UL) /*!< CLROCFH (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLRSCF_Pos (3UL) /*!< CLRSCF (Bit 3) */ + #define R_DSMIF0_CH_DSCSCR_CLRSCF_Msk (0x8UL) /*!< CLRSCF (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT7_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT7_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT7_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT7_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT7_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT7_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT7_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT7_GTSTR_CSTRT0_Pos (0UL) /*!< CSTRT0 (Bit 0) */ + #define R_GPT7_GTSTR_CSTRT0_Msk (0x1UL) /*!< CSTRT0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT1_Pos (1UL) /*!< CSTRT1 (Bit 1) */ + #define R_GPT7_GTSTR_CSTRT1_Msk (0x2UL) /*!< CSTRT1 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT2_Pos (2UL) /*!< CSTRT2 (Bit 2) */ + #define R_GPT7_GTSTR_CSTRT2_Msk (0x4UL) /*!< CSTRT2 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT3_Pos (3UL) /*!< CSTRT3 (Bit 3) */ + #define R_GPT7_GTSTR_CSTRT3_Msk (0x8UL) /*!< CSTRT3 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT4_Pos (4UL) /*!< CSTRT4 (Bit 4) */ + #define R_GPT7_GTSTR_CSTRT4_Msk (0x10UL) /*!< CSTRT4 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT5_Pos (5UL) /*!< CSTRT5 (Bit 5) */ + #define R_GPT7_GTSTR_CSTRT5_Msk (0x20UL) /*!< CSTRT5 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT6_Pos (6UL) /*!< CSTRT6 (Bit 6) */ + #define R_GPT7_GTSTR_CSTRT6_Msk (0x40UL) /*!< CSTRT6 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT7_GTSTP_CSTOP0_Pos (0UL) /*!< CSTOP0 (Bit 0) */ + #define R_GPT7_GTSTP_CSTOP0_Msk (0x1UL) /*!< CSTOP0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP1_Pos (1UL) /*!< CSTOP1 (Bit 1) */ + #define R_GPT7_GTSTP_CSTOP1_Msk (0x2UL) /*!< CSTOP1 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP2_Pos (2UL) /*!< CSTOP2 (Bit 2) */ + #define R_GPT7_GTSTP_CSTOP2_Msk (0x4UL) /*!< CSTOP2 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP3_Pos (3UL) /*!< CSTOP3 (Bit 3) */ + #define R_GPT7_GTSTP_CSTOP3_Msk (0x8UL) /*!< CSTOP3 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP4_Pos (4UL) /*!< CSTOP4 (Bit 4) */ + #define R_GPT7_GTSTP_CSTOP4_Msk (0x10UL) /*!< CSTOP4 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP5_Pos (5UL) /*!< CSTOP5 (Bit 5) */ + #define R_GPT7_GTSTP_CSTOP5_Msk (0x20UL) /*!< CSTOP5 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP6_Pos (6UL) /*!< CSTOP6 (Bit 6) */ + #define R_GPT7_GTSTP_CSTOP6_Msk (0x40UL) /*!< CSTOP6 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT7_GTCLR_CCLR0_Pos (0UL) /*!< CCLR0 (Bit 0) */ + #define R_GPT7_GTCLR_CCLR0_Msk (0x1UL) /*!< CCLR0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR1_Pos (1UL) /*!< CCLR1 (Bit 1) */ + #define R_GPT7_GTCLR_CCLR1_Msk (0x2UL) /*!< CCLR1 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR2_Pos (2UL) /*!< CCLR2 (Bit 2) */ + #define R_GPT7_GTCLR_CCLR2_Msk (0x4UL) /*!< CCLR2 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR3_Pos (3UL) /*!< CCLR3 (Bit 3) */ + #define R_GPT7_GTCLR_CCLR3_Msk (0x8UL) /*!< CCLR3 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR4_Pos (4UL) /*!< CCLR4 (Bit 4) */ + #define R_GPT7_GTCLR_CCLR4_Msk (0x10UL) /*!< CCLR4 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR5_Pos (5UL) /*!< CCLR5 (Bit 5) */ + #define R_GPT7_GTCLR_CCLR5_Msk (0x20UL) /*!< CCLR5 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR6_Pos (6UL) /*!< CCLR6 (Bit 6) */ + #define R_GPT7_GTCLR_CCLR6_Msk (0x40UL) /*!< CCLR6 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT7_GTSSR_SSGTRGAFR_Pos (0UL) /*!< SSGTRGAFR (Bit 0) */ + #define R_GPT7_GTSSR_SSGTRGAFR_Msk (0x3UL) /*!< SSGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSGTRGBFR_Pos (2UL) /*!< SSGTRGBFR (Bit 2) */ + #define R_GPT7_GTSSR_SSGTRGBFR_Msk (0xcUL) /*!< SSGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSGTRGCFR_Pos (4UL) /*!< SSGTRGCFR (Bit 4) */ + #define R_GPT7_GTSSR_SSGTRGCFR_Msk (0x30UL) /*!< SSGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSGTRGDFR_Pos (6UL) /*!< SSGTRGDFR (Bit 6) */ + #define R_GPT7_GTSSR_SSGTRGDFR_Msk (0xc0UL) /*!< SSGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSCARBHL_Pos (8UL) /*!< SSCARBHL (Bit 8) */ + #define R_GPT7_GTSSR_SSCARBHL_Msk (0x300UL) /*!< SSCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSCAFBHL_Pos (10UL) /*!< SSCAFBHL (Bit 10) */ + #define R_GPT7_GTSSR_SSCAFBHL_Msk (0xc00UL) /*!< SSCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSCBRAHL_Pos (12UL) /*!< SSCBRAHL (Bit 12) */ + #define R_GPT7_GTSSR_SSCBRAHL_Msk (0x3000UL) /*!< SSCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSCBFAHL_Pos (14UL) /*!< SSCBFAHL (Bit 14) */ + #define R_GPT7_GTSSR_SSCBFAHL_Msk (0xc000UL) /*!< SSCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSELCA_Pos (16UL) /*!< SSELCA (Bit 16) */ + #define R_GPT7_GTSSR_SSELCA_Msk (0x10000UL) /*!< SSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCB_Pos (17UL) /*!< SSELCB (Bit 17) */ + #define R_GPT7_GTSSR_SSELCB_Msk (0x20000UL) /*!< SSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCC_Pos (18UL) /*!< SSELCC (Bit 18) */ + #define R_GPT7_GTSSR_SSELCC_Msk (0x40000UL) /*!< SSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCD_Pos (19UL) /*!< SSELCD (Bit 19) */ + #define R_GPT7_GTSSR_SSELCD_Msk (0x80000UL) /*!< SSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCE_Pos (20UL) /*!< SSELCE (Bit 20) */ + #define R_GPT7_GTSSR_SSELCE_Msk (0x100000UL) /*!< SSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCF_Pos (21UL) /*!< SSELCF (Bit 21) */ + #define R_GPT7_GTSSR_SSELCF_Msk (0x200000UL) /*!< SSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCG_Pos (22UL) /*!< SSELCG (Bit 22) */ + #define R_GPT7_GTSSR_SSELCG_Msk (0x400000UL) /*!< SSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCH_Pos (23UL) /*!< SSELCH (Bit 23) */ + #define R_GPT7_GTSSR_SSELCH_Msk (0x800000UL) /*!< SSELCH (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT7_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT7_GTPSR_PSGTRGAFR_Pos (0UL) /*!< PSGTRGAFR (Bit 0) */ + #define R_GPT7_GTPSR_PSGTRGAFR_Msk (0x3UL) /*!< PSGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSGTRGBFR_Pos (2UL) /*!< PSGTRGBFR (Bit 2) */ + #define R_GPT7_GTPSR_PSGTRGBFR_Msk (0xcUL) /*!< PSGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSGTRGCFR_Pos (4UL) /*!< PSGTRGCFR (Bit 4) */ + #define R_GPT7_GTPSR_PSGTRGCFR_Msk (0x30UL) /*!< PSGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSGTRGDFR_Pos (6UL) /*!< PSGTRGDFR (Bit 6) */ + #define R_GPT7_GTPSR_PSGTRGDFR_Msk (0xc0UL) /*!< PSGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSCARBHL_Pos (8UL) /*!< PSCARBHL (Bit 8) */ + #define R_GPT7_GTPSR_PSCARBHL_Msk (0x300UL) /*!< PSCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSCAFBHL_Pos (10UL) /*!< PSCAFBHL (Bit 10) */ + #define R_GPT7_GTPSR_PSCAFBHL_Msk (0xc00UL) /*!< PSCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSCBRAHL_Pos (12UL) /*!< PSCBRAHL (Bit 12) */ + #define R_GPT7_GTPSR_PSCBRAHL_Msk (0x3000UL) /*!< PSCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSCBFAHL_Pos (14UL) /*!< PSCBFAHL (Bit 14) */ + #define R_GPT7_GTPSR_PSCBFAHL_Msk (0xc000UL) /*!< PSCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSELCA_Pos (16UL) /*!< PSELCA (Bit 16) */ + #define R_GPT7_GTPSR_PSELCA_Msk (0x10000UL) /*!< PSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCB_Pos (17UL) /*!< PSELCB (Bit 17) */ + #define R_GPT7_GTPSR_PSELCB_Msk (0x20000UL) /*!< PSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCC_Pos (18UL) /*!< PSELCC (Bit 18) */ + #define R_GPT7_GTPSR_PSELCC_Msk (0x40000UL) /*!< PSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCD_Pos (19UL) /*!< PSELCD (Bit 19) */ + #define R_GPT7_GTPSR_PSELCD_Msk (0x80000UL) /*!< PSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCE_Pos (20UL) /*!< PSELCE (Bit 20) */ + #define R_GPT7_GTPSR_PSELCE_Msk (0x100000UL) /*!< PSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCF_Pos (21UL) /*!< PSELCF (Bit 21) */ + #define R_GPT7_GTPSR_PSELCF_Msk (0x200000UL) /*!< PSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCG_Pos (22UL) /*!< PSELCG (Bit 22) */ + #define R_GPT7_GTPSR_PSELCG_Msk (0x400000UL) /*!< PSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCH_Pos (23UL) /*!< PSELCH (Bit 23) */ + #define R_GPT7_GTPSR_PSELCH_Msk (0x800000UL) /*!< PSELCH (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT7_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT7_GTCSR_CSGTRGAFR_Pos (0UL) /*!< CSGTRGAFR (Bit 0) */ + #define R_GPT7_GTCSR_CSGTRGAFR_Msk (0x3UL) /*!< CSGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSGTRGBFR_Pos (2UL) /*!< CSGTRGBFR (Bit 2) */ + #define R_GPT7_GTCSR_CSGTRGBFR_Msk (0xcUL) /*!< CSGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSGTRGCFR_Pos (4UL) /*!< CSGTRGCFR (Bit 4) */ + #define R_GPT7_GTCSR_CSGTRGCFR_Msk (0x30UL) /*!< CSGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSGTRGDFR_Pos (6UL) /*!< CSGTRGDFR (Bit 6) */ + #define R_GPT7_GTCSR_CSGTRGDFR_Msk (0xc0UL) /*!< CSGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSCARBHL_Pos (8UL) /*!< CSCARBHL (Bit 8) */ + #define R_GPT7_GTCSR_CSCARBHL_Msk (0x300UL) /*!< CSCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSCAFBHL_Pos (10UL) /*!< CSCAFBHL (Bit 10) */ + #define R_GPT7_GTCSR_CSCAFBHL_Msk (0xc00UL) /*!< CSCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSCBRAHL_Pos (12UL) /*!< CSCBRAHL (Bit 12) */ + #define R_GPT7_GTCSR_CSCBRAHL_Msk (0x3000UL) /*!< CSCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSCBFAHL_Pos (14UL) /*!< CSCBFAHL (Bit 14) */ + #define R_GPT7_GTCSR_CSCBFAHL_Msk (0xc000UL) /*!< CSCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSELCA_Pos (16UL) /*!< CSELCA (Bit 16) */ + #define R_GPT7_GTCSR_CSELCA_Msk (0x10000UL) /*!< CSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCB_Pos (17UL) /*!< CSELCB (Bit 17) */ + #define R_GPT7_GTCSR_CSELCB_Msk (0x20000UL) /*!< CSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCC_Pos (18UL) /*!< CSELCC (Bit 18) */ + #define R_GPT7_GTCSR_CSELCC_Msk (0x40000UL) /*!< CSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCD_Pos (19UL) /*!< CSELCD (Bit 19) */ + #define R_GPT7_GTCSR_CSELCD_Msk (0x80000UL) /*!< CSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCE_Pos (20UL) /*!< CSELCE (Bit 20) */ + #define R_GPT7_GTCSR_CSELCE_Msk (0x100000UL) /*!< CSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCF_Pos (21UL) /*!< CSELCF (Bit 21) */ + #define R_GPT7_GTCSR_CSELCF_Msk (0x200000UL) /*!< CSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCG_Pos (22UL) /*!< CSELCG (Bit 22) */ + #define R_GPT7_GTCSR_CSELCG_Msk (0x400000UL) /*!< CSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCH_Pos (23UL) /*!< CSELCH (Bit 23) */ + #define R_GPT7_GTCSR_CSELCH_Msk (0x800000UL) /*!< CSELCH (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT7_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT7_GTUPSR_USGTRGAFR_Pos (0UL) /*!< USGTRGAFR (Bit 0) */ + #define R_GPT7_GTUPSR_USGTRGAFR_Msk (0x3UL) /*!< USGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USGTRGBFR_Pos (2UL) /*!< USGTRGBFR (Bit 2) */ + #define R_GPT7_GTUPSR_USGTRGBFR_Msk (0xcUL) /*!< USGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USGTRGCFR_Pos (4UL) /*!< USGTRGCFR (Bit 4) */ + #define R_GPT7_GTUPSR_USGTRGCFR_Msk (0x30UL) /*!< USGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USGTRGDFR_Pos (6UL) /*!< USGTRGDFR (Bit 6) */ + #define R_GPT7_GTUPSR_USGTRGDFR_Msk (0xc0UL) /*!< USGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USCARBHL_Pos (8UL) /*!< USCARBHL (Bit 8) */ + #define R_GPT7_GTUPSR_USCARBHL_Msk (0x300UL) /*!< USCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USCAFBHL_Pos (10UL) /*!< USCAFBHL (Bit 10) */ + #define R_GPT7_GTUPSR_USCAFBHL_Msk (0xc00UL) /*!< USCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USCBRAHL_Pos (12UL) /*!< USCBRAHL (Bit 12) */ + #define R_GPT7_GTUPSR_USCBRAHL_Msk (0x3000UL) /*!< USCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USCBFAHL_Pos (14UL) /*!< USCBFAHL (Bit 14) */ + #define R_GPT7_GTUPSR_USCBFAHL_Msk (0xc000UL) /*!< USCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USELCA_Pos (16UL) /*!< USELCA (Bit 16) */ + #define R_GPT7_GTUPSR_USELCA_Msk (0x10000UL) /*!< USELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCB_Pos (17UL) /*!< USELCB (Bit 17) */ + #define R_GPT7_GTUPSR_USELCB_Msk (0x20000UL) /*!< USELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCC_Pos (18UL) /*!< USELCC (Bit 18) */ + #define R_GPT7_GTUPSR_USELCC_Msk (0x40000UL) /*!< USELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCD_Pos (19UL) /*!< USELCD (Bit 19) */ + #define R_GPT7_GTUPSR_USELCD_Msk (0x80000UL) /*!< USELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCE_Pos (20UL) /*!< USELCE (Bit 20) */ + #define R_GPT7_GTUPSR_USELCE_Msk (0x100000UL) /*!< USELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCF_Pos (21UL) /*!< USELCF (Bit 21) */ + #define R_GPT7_GTUPSR_USELCF_Msk (0x200000UL) /*!< USELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCG_Pos (22UL) /*!< USELCG (Bit 22) */ + #define R_GPT7_GTUPSR_USELCG_Msk (0x400000UL) /*!< USELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCH_Pos (23UL) /*!< USELCH (Bit 23) */ + #define R_GPT7_GTUPSR_USELCH_Msk (0x800000UL) /*!< USELCH (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT7_GTDNSR_DSGTRGAFR_Pos (0UL) /*!< DSGTRGAFR (Bit 0) */ + #define R_GPT7_GTDNSR_DSGTRGAFR_Msk (0x3UL) /*!< DSGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSGTRGBFR_Pos (2UL) /*!< DSGTRGBFR (Bit 2) */ + #define R_GPT7_GTDNSR_DSGTRGBFR_Msk (0xcUL) /*!< DSGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSGTRGCFR_Pos (4UL) /*!< DSGTRGCFR (Bit 4) */ + #define R_GPT7_GTDNSR_DSGTRGCFR_Msk (0x30UL) /*!< DSGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSGTRGDFR_Pos (6UL) /*!< DSGTRGDFR (Bit 6) */ + #define R_GPT7_GTDNSR_DSGTRGDFR_Msk (0xc0UL) /*!< DSGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSCARBHL_Pos (8UL) /*!< DSCARBHL (Bit 8) */ + #define R_GPT7_GTDNSR_DSCARBHL_Msk (0x300UL) /*!< DSCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSCAFBHL_Pos (10UL) /*!< DSCAFBHL (Bit 10) */ + #define R_GPT7_GTDNSR_DSCAFBHL_Msk (0xc00UL) /*!< DSCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSCBRAHL_Pos (12UL) /*!< DSCBRAHL (Bit 12) */ + #define R_GPT7_GTDNSR_DSCBRAHL_Msk (0x3000UL) /*!< DSCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSCBFAHL_Pos (14UL) /*!< DSCBFAHL (Bit 14) */ + #define R_GPT7_GTDNSR_DSCBFAHL_Msk (0xc000UL) /*!< DSCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSELCA_Pos (16UL) /*!< DSELCA (Bit 16) */ + #define R_GPT7_GTDNSR_DSELCA_Msk (0x10000UL) /*!< DSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCB_Pos (17UL) /*!< DSELCB (Bit 17) */ + #define R_GPT7_GTDNSR_DSELCB_Msk (0x20000UL) /*!< DSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCC_Pos (18UL) /*!< DSELCC (Bit 18) */ + #define R_GPT7_GTDNSR_DSELCC_Msk (0x40000UL) /*!< DSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCD_Pos (19UL) /*!< DSELCD (Bit 19) */ + #define R_GPT7_GTDNSR_DSELCD_Msk (0x80000UL) /*!< DSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCE_Pos (20UL) /*!< DSELCE (Bit 20) */ + #define R_GPT7_GTDNSR_DSELCE_Msk (0x100000UL) /*!< DSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCF_Pos (21UL) /*!< DSELCF (Bit 21) */ + #define R_GPT7_GTDNSR_DSELCF_Msk (0x200000UL) /*!< DSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCG_Pos (22UL) /*!< DSELCG (Bit 22) */ + #define R_GPT7_GTDNSR_DSELCG_Msk (0x400000UL) /*!< DSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCH_Pos (23UL) /*!< DSELCH (Bit 23) */ + #define R_GPT7_GTDNSR_DSELCH_Msk (0x800000UL) /*!< DSELCH (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT7_GTICASR_ASGTRGAFR_Pos (0UL) /*!< ASGTRGAFR (Bit 0) */ + #define R_GPT7_GTICASR_ASGTRGAFR_Msk (0x3UL) /*!< ASGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASGTRGBFR_Pos (2UL) /*!< ASGTRGBFR (Bit 2) */ + #define R_GPT7_GTICASR_ASGTRGBFR_Msk (0xcUL) /*!< ASGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASGTRGCFR_Pos (4UL) /*!< ASGTRGCFR (Bit 4) */ + #define R_GPT7_GTICASR_ASGTRGCFR_Msk (0x30UL) /*!< ASGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASGTRGDFR_Pos (6UL) /*!< ASGTRGDFR (Bit 6) */ + #define R_GPT7_GTICASR_ASGTRGDFR_Msk (0xc0UL) /*!< ASGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASCARBHL_Pos (8UL) /*!< ASCARBHL (Bit 8) */ + #define R_GPT7_GTICASR_ASCARBHL_Msk (0x300UL) /*!< ASCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASCAFBHL_Pos (10UL) /*!< ASCAFBHL (Bit 10) */ + #define R_GPT7_GTICASR_ASCAFBHL_Msk (0xc00UL) /*!< ASCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASCBRAHL_Pos (12UL) /*!< ASCBRAHL (Bit 12) */ + #define R_GPT7_GTICASR_ASCBRAHL_Msk (0x3000UL) /*!< ASCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASCBFAHL_Pos (14UL) /*!< ASCBFAHL (Bit 14) */ + #define R_GPT7_GTICASR_ASCBFAHL_Msk (0xc000UL) /*!< ASCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASELCA_Pos (16UL) /*!< ASELCA (Bit 16) */ + #define R_GPT7_GTICASR_ASELCA_Msk (0x10000UL) /*!< ASELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCB_Pos (17UL) /*!< ASELCB (Bit 17) */ + #define R_GPT7_GTICASR_ASELCB_Msk (0x20000UL) /*!< ASELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCC_Pos (18UL) /*!< ASELCC (Bit 18) */ + #define R_GPT7_GTICASR_ASELCC_Msk (0x40000UL) /*!< ASELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCD_Pos (19UL) /*!< ASELCD (Bit 19) */ + #define R_GPT7_GTICASR_ASELCD_Msk (0x80000UL) /*!< ASELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCE_Pos (20UL) /*!< ASELCE (Bit 20) */ + #define R_GPT7_GTICASR_ASELCE_Msk (0x100000UL) /*!< ASELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCF_Pos (21UL) /*!< ASELCF (Bit 21) */ + #define R_GPT7_GTICASR_ASELCF_Msk (0x200000UL) /*!< ASELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCG_Pos (22UL) /*!< ASELCG (Bit 22) */ + #define R_GPT7_GTICASR_ASELCG_Msk (0x400000UL) /*!< ASELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCH_Pos (23UL) /*!< ASELCH (Bit 23) */ + #define R_GPT7_GTICASR_ASELCH_Msk (0x800000UL) /*!< ASELCH (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT7_GTICBSR_BSGTRGAFR_Pos (0UL) /*!< BSGTRGAFR (Bit 0) */ + #define R_GPT7_GTICBSR_BSGTRGAFR_Msk (0x3UL) /*!< BSGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSGTRGBFR_Pos (2UL) /*!< BSGTRGBFR (Bit 2) */ + #define R_GPT7_GTICBSR_BSGTRGBFR_Msk (0xcUL) /*!< BSGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSGTRGCFR_Pos (4UL) /*!< BSGTRGCFR (Bit 4) */ + #define R_GPT7_GTICBSR_BSGTRGCFR_Msk (0x30UL) /*!< BSGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSGTRGDFR_Pos (6UL) /*!< BSGTRGDFR (Bit 6) */ + #define R_GPT7_GTICBSR_BSGTRGDFR_Msk (0xc0UL) /*!< BSGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSCARBHL_Pos (8UL) /*!< BSCARBHL (Bit 8) */ + #define R_GPT7_GTICBSR_BSCARBHL_Msk (0x300UL) /*!< BSCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSCAFBHL_Pos (10UL) /*!< BSCAFBHL (Bit 10) */ + #define R_GPT7_GTICBSR_BSCAFBHL_Msk (0xc00UL) /*!< BSCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSCBRAHL_Pos (12UL) /*!< BSCBRAHL (Bit 12) */ + #define R_GPT7_GTICBSR_BSCBRAHL_Msk (0x3000UL) /*!< BSCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSCBFAHL_Pos (14UL) /*!< BSCBFAHL (Bit 14) */ + #define R_GPT7_GTICBSR_BSCBFAHL_Msk (0xc000UL) /*!< BSCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSELCA_Pos (16UL) /*!< BSELCA (Bit 16) */ + #define R_GPT7_GTICBSR_BSELCA_Msk (0x10000UL) /*!< BSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCB_Pos (17UL) /*!< BSELCB (Bit 17) */ + #define R_GPT7_GTICBSR_BSELCB_Msk (0x20000UL) /*!< BSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCC_Pos (18UL) /*!< BSELCC (Bit 18) */ + #define R_GPT7_GTICBSR_BSELCC_Msk (0x40000UL) /*!< BSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCD_Pos (19UL) /*!< BSELCD (Bit 19) */ + #define R_GPT7_GTICBSR_BSELCD_Msk (0x80000UL) /*!< BSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCE_Pos (20UL) /*!< BSELCE (Bit 20) */ + #define R_GPT7_GTICBSR_BSELCE_Msk (0x100000UL) /*!< BSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCF_Pos (21UL) /*!< BSELCF (Bit 21) */ + #define R_GPT7_GTICBSR_BSELCF_Msk (0x200000UL) /*!< BSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCG_Pos (22UL) /*!< BSELCG (Bit 22) */ + #define R_GPT7_GTICBSR_BSELCG_Msk (0x400000UL) /*!< BSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCH_Pos (23UL) /*!< BSELCH (Bit 23) */ + #define R_GPT7_GTICBSR_BSELCH_Msk (0x800000UL) /*!< BSELCH (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT7_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT7_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ + #define R_GPT7_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT7_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT7_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT7_GTCR_SWMD_Pos (29UL) /*!< SWMD (Bit 29) */ + #define R_GPT7_GTCR_SWMD_Msk (0xe0000000UL) /*!< SWMD (Bitfield-Mask: 0x07) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT7_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT7_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT7_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT7_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT7_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT7_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT7_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT7_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT7_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_OABDTYT_Pos (28UL) /*!< OABDTYT (Bit 28) */ + #define R_GPT7_GTUDDTYC_OABDTYT_Msk (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT7_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT7_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ + #define R_GPT7_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT7_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT7_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT7_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT7_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT7_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT7_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT7_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT7_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT7_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT7_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT7_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT7_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT7_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT7_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT7_GTINTAD_GTINTA_Pos (0UL) /*!< GTINTA (Bit 0) */ + #define R_GPT7_GTINTAD_GTINTA_Msk (0x1UL) /*!< GTINTA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTB_Pos (1UL) /*!< GTINTB (Bit 1) */ + #define R_GPT7_GTINTAD_GTINTB_Msk (0x2UL) /*!< GTINTB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTC_Pos (2UL) /*!< GTINTC (Bit 2) */ + #define R_GPT7_GTINTAD_GTINTC_Msk (0x4UL) /*!< GTINTC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTD_Pos (3UL) /*!< GTINTD (Bit 3) */ + #define R_GPT7_GTINTAD_GTINTD_Msk (0x8UL) /*!< GTINTD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTE_Pos (4UL) /*!< GTINTE (Bit 4) */ + #define R_GPT7_GTINTAD_GTINTE_Msk (0x10UL) /*!< GTINTE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTF_Pos (5UL) /*!< GTINTF (Bit 5) */ + #define R_GPT7_GTINTAD_GTINTF_Msk (0x20UL) /*!< GTINTF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT7_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTINTAD_ADTRAUEN_Pos (16UL) /*!< ADTRAUEN (Bit 16) */ + #define R_GPT7_GTINTAD_ADTRAUEN_Msk (0x10000UL) /*!< ADTRAUEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_ADTRADEN_Pos (17UL) /*!< ADTRADEN (Bit 17) */ + #define R_GPT7_GTINTAD_ADTRADEN_Msk (0x20000UL) /*!< ADTRADEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_ADTRBUEN_Pos (18UL) /*!< ADTRBUEN (Bit 18) */ + #define R_GPT7_GTINTAD_ADTRBUEN_Msk (0x40000UL) /*!< ADTRBUEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_ADTRBDEN_Pos (19UL) /*!< ADTRBDEN (Bit 19) */ + #define R_GPT7_GTINTAD_ADTRBDEN_Msk (0x80000UL) /*!< ADTRBDEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT7_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT7_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT7_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT7_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT7_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT7_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT7_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT7_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT7_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT7_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT7_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT7_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT7_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT7_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT7_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT7_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT7_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT7_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT7_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT7_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_DBRTECA_Pos (8UL) /*!< DBRTECA (Bit 8) */ + #define R_GPT7_GTBER_DBRTECA_Msk (0x100UL) /*!< DBRTECA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_DBRTECB_Pos (10UL) /*!< DBRTECB (Bit 10) */ + #define R_GPT7_GTBER_DBRTECB_Msk (0x400UL) /*!< DBRTECB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT7_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT7_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT7_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT7_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT7_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT7_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT7_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT7_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT7_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT7_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT7_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT7_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT7_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT7_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT7_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT7_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT7_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT7_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT7_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ +/* ========================================================= GTCCR ========================================================= */ +/* ========================================================= GTPR ========================================================== */ +/* ========================================================= GTPBR ========================================================= */ +/* ======================================================== GTPDBR ========================================================= */ +/* ======================================================== GTADTRA ======================================================== */ +/* ======================================================= GTADTBRA ======================================================== */ +/* ======================================================= GTADTDBRA ======================================================= */ +/* ======================================================== GTADTRB ======================================================== */ +/* ======================================================= GTADTBRB ======================================================== */ +/* ======================================================= GTADTDBRB ======================================================= */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT7_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT7_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT7_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT7_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT7_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ +/* ========================================================= GTDVD ========================================================= */ +/* ========================================================= GTDBU ========================================================= */ +/* ========================================================= GTDBD ========================================================= */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT7_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT7_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT7_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT7_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTADSMR ======================================================== */ + #define R_GPT7_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ + #define R_GPT7_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ + #define R_GPT7_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ + #define R_GPT7_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ + #define R_GPT7_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTEITC ========================================================= */ + #define R_GPT7_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ + #define R_GPT7_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ + #define R_GPT7_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT7_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ + #define R_GPT7_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT7_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ + #define R_GPT7_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ + #define R_GPT7_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ + #define R_GPT7_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ + #define R_GPT7_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ + #define R_GPT7_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ + #define R_GPT7_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= GTEITLI1 ======================================================== */ + #define R_GPT7_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ + #define R_GPT7_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ + #define R_GPT7_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ + #define R_GPT7_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ + #define R_GPT7_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ + #define R_GPT7_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ + #define R_GPT7_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ + #define R_GPT7_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ + #define R_GPT7_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ +/* ======================================================= GTEITLI2 ======================================================== */ + #define R_GPT7_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ + #define R_GPT7_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ + #define R_GPT7_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ +/* ======================================================== GTEITLB ======================================================== */ + #define R_GPT7_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ + #define R_GPT7_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ + #define R_GPT7_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ + #define R_GPT7_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ + #define R_GPT7_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ + #define R_GPT7_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ + #define R_GPT7_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ + #define R_GPT7_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT7_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT7_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT7_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT7_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT7_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT7_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT7_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT7_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT7_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT7_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT7_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ + #define R_GPT7_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ + #define R_GPT7_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT7_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT7_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ + #define R_GPT7_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ + #define R_GPT7_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSWSR ========================================================= */ + #define R_GPT7_GTSWSR_WSGTRGA_Pos (0UL) /*!< WSGTRGA (Bit 0) */ + #define R_GPT7_GTSWSR_WSGTRGA_Msk (0x3UL) /*!< WSGTRGA (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSWSR_WSGTRGB_Pos (2UL) /*!< WSGTRGB (Bit 2) */ + #define R_GPT7_GTSWSR_WSGTRGB_Msk (0xcUL) /*!< WSGTRGB (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSWSR_WSGTRGC_Pos (4UL) /*!< WSGTRGC (Bit 4) */ + #define R_GPT7_GTSWSR_WSGTRGC_Msk (0x30UL) /*!< WSGTRGC (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSWSR_WSGTRGD_Pos (6UL) /*!< WSGTRGD (Bit 6) */ + #define R_GPT7_GTSWSR_WSGTRGD_Msk (0xc0UL) /*!< WSGTRGD (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSWSR_WSELCA_Pos (16UL) /*!< WSELCA (Bit 16) */ + #define R_GPT7_GTSWSR_WSELCA_Msk (0x10000UL) /*!< WSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCB_Pos (17UL) /*!< WSELCB (Bit 17) */ + #define R_GPT7_GTSWSR_WSELCB_Msk (0x20000UL) /*!< WSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCC_Pos (18UL) /*!< WSELCC (Bit 18) */ + #define R_GPT7_GTSWSR_WSELCC_Msk (0x40000UL) /*!< WSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCD_Pos (19UL) /*!< WSELCD (Bit 19) */ + #define R_GPT7_GTSWSR_WSELCD_Msk (0x80000UL) /*!< WSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCE_Pos (20UL) /*!< WSELCE (Bit 20) */ + #define R_GPT7_GTSWSR_WSELCE_Msk (0x100000UL) /*!< WSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCF_Pos (21UL) /*!< WSELCF (Bit 21) */ + #define R_GPT7_GTSWSR_WSELCF_Msk (0x200000UL) /*!< WSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCG_Pos (22UL) /*!< WSELCG (Bit 22) */ + #define R_GPT7_GTSWSR_WSELCG_Msk (0x400000UL) /*!< WSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_CSELCH_Pos (23UL) /*!< CSELCH (Bit 23) */ + #define R_GPT7_GTSWSR_CSELCH_Msk (0x800000UL) /*!< CSELCH (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSWOS ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_RDR_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_RDR_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_RDR_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_RDR_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_FPER_Pos (11UL) /*!< FPER (Bit 11) */ + #define R_SCI0_RDR_FPER_Msk (0x800UL) /*!< FPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_FFER_Pos (12UL) /*!< FFER (Bit 12) */ + #define R_SCI0_RDR_FFER_Msk (0x1000UL) /*!< FFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI0_RDR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI0_RDR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI0_RDR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_TDR_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_TDR_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_TDR_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR0 ========================================================== */ + #define R_SCI0_CCR0_RE_Pos (0UL) /*!< RE (Bit 0) */ + #define R_SCI0_CCR0_RE_Msk (0x1UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_TE_Pos (4UL) /*!< TE (Bit 4) */ + #define R_SCI0_CCR0_TE_Msk (0x10UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_MPIE_Pos (8UL) /*!< MPIE (Bit 8) */ + #define R_SCI0_CCR0_MPIE_Msk (0x100UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_DCME_Pos (9UL) /*!< DCME (Bit 9) */ + #define R_SCI0_CCR0_DCME_Msk (0x200UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_IDSEL_Pos (10UL) /*!< IDSEL (Bit 10) */ + #define R_SCI0_CCR0_IDSEL_Msk (0x400UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_RIE_Pos (16UL) /*!< RIE (Bit 16) */ + #define R_SCI0_CCR0_RIE_Msk (0x10000UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_TIE_Pos (20UL) /*!< TIE (Bit 20) */ + #define R_SCI0_CCR0_TIE_Msk (0x100000UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_TEIE_Pos (21UL) /*!< TEIE (Bit 21) */ + #define R_SCI0_CCR0_TEIE_Msk (0x200000UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_SSE_Pos (24UL) /*!< SSE (Bit 24) */ + #define R_SCI0_CCR0_SSE_Msk (0x1000000UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR1 ========================================================== */ + #define R_SCI0_CCR1_CTSE_Pos (0UL) /*!< CTSE (Bit 0) */ + #define R_SCI0_CCR1_CTSE_Msk (0x1UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_CTSPEN_Pos (1UL) /*!< CTSPEN (Bit 1) */ + #define R_SCI0_CCR1_CTSPEN_Msk (0x2UL) /*!< CTSPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_SPB2DT_Pos (4UL) /*!< SPB2DT (Bit 4) */ + #define R_SCI0_CCR1_SPB2DT_Msk (0x10UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_SPB2IO_Pos (5UL) /*!< SPB2IO (Bit 5) */ + #define R_SCI0_CCR1_SPB2IO_Msk (0x20UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_PE_Pos (8UL) /*!< PE (Bit 8) */ + #define R_SCI0_CCR1_PE_Msk (0x100UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_PM_Pos (9UL) /*!< PM (Bit 9) */ + #define R_SCI0_CCR1_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_TINV_Pos (12UL) /*!< TINV (Bit 12) */ + #define R_SCI0_CCR1_TINV_Msk (0x1000UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_RINV_Pos (13UL) /*!< RINV (Bit 13) */ + #define R_SCI0_CCR1_RINV_Msk (0x2000UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SCI0_CCR1_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_SHARPS_Pos (20UL) /*!< SHARPS (Bit 20) */ + #define R_SCI0_CCR1_SHARPS_Msk (0x100000UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_NFCS_Pos (24UL) /*!< NFCS (Bit 24) */ + #define R_SCI0_CCR1_NFCS_Msk (0x7000000UL) /*!< NFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CCR1_NFEN_Pos (28UL) /*!< NFEN (Bit 28) */ + #define R_SCI0_CCR1_NFEN_Msk (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR2 ========================================================== */ + #define R_SCI0_CCR2_BCP_Pos (0UL) /*!< BCP (Bit 0) */ + #define R_SCI0_CCR2_BCP_Msk (0x7UL) /*!< BCP (Bitfield-Mask: 0x07) */ + #define R_SCI0_CCR2_BGDM_Pos (4UL) /*!< BGDM (Bit 4) */ + #define R_SCI0_CCR2_BGDM_Msk (0x10UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR2_ABCS_Pos (5UL) /*!< ABCS (Bit 5) */ + #define R_SCI0_CCR2_ABCS_Msk (0x20UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR2_ABCSE_Pos (6UL) /*!< ABCSE (Bit 6) */ + #define R_SCI0_CCR2_ABCSE_Msk (0x40UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR2_BRR_Pos (8UL) /*!< BRR (Bit 8) */ + #define R_SCI0_CCR2_BRR_Msk (0xff00UL) /*!< BRR (Bitfield-Mask: 0xff) */ + #define R_SCI0_CCR2_BRME_Pos (16UL) /*!< BRME (Bit 16) */ + #define R_SCI0_CCR2_BRME_Msk (0x10000UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR2_CKS_Pos (20UL) /*!< CKS (Bit 20) */ + #define R_SCI0_CCR2_CKS_Msk (0x300000UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CCR2_MDDR_Pos (24UL) /*!< MDDR (Bit 24) */ + #define R_SCI0_CCR2_MDDR_Msk (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR3 ========================================================== */ + #define R_SCI0_CCR3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SCI0_CCR3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SCI0_CCR3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_BPEN_Pos (7UL) /*!< BPEN (Bit 7) */ + #define R_SCI0_CCR3_BPEN_Msk (0x80UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_CHR_Pos (8UL) /*!< CHR (Bit 8) */ + #define R_SCI0_CCR3_CHR_Msk (0x300UL) /*!< CHR (Bitfield-Mask: 0x03) */ + #define R_SCI0_CCR3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SCI0_CCR3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_SINV_Pos (13UL) /*!< SINV (Bit 13) */ + #define R_SCI0_CCR3_SINV_Msk (0x2000UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_STP_Pos (14UL) /*!< STP (Bit 14) */ + #define R_SCI0_CCR3_STP_Msk (0x4000UL) /*!< STP (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_RXDESEL_Pos (15UL) /*!< RXDESEL (Bit 15) */ + #define R_SCI0_CCR3_RXDESEL_Msk (0x8000UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_MOD_Pos (16UL) /*!< MOD (Bit 16) */ + #define R_SCI0_CCR3_MOD_Msk (0x70000UL) /*!< MOD (Bitfield-Mask: 0x07) */ + #define R_SCI0_CCR3_MP_Pos (19UL) /*!< MP (Bit 19) */ + #define R_SCI0_CCR3_MP_Msk (0x80000UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_FM_Pos (20UL) /*!< FM (Bit 20) */ + #define R_SCI0_CCR3_FM_Msk (0x100000UL) /*!< FM (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_DEN_Pos (21UL) /*!< DEN (Bit 21) */ + #define R_SCI0_CCR3_DEN_Msk (0x200000UL) /*!< DEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_CKE_Pos (24UL) /*!< CKE (Bit 24) */ + #define R_SCI0_CCR3_CKE_Msk (0x3000000UL) /*!< CKE (Bitfield-Mask: 0x03) */ + #define R_SCI0_CCR3_GM_Pos (28UL) /*!< GM (Bit 28) */ + #define R_SCI0_CCR3_GM_Msk (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_BLK_Pos (29UL) /*!< BLK (Bit 29) */ + #define R_SCI0_CCR3_BLK_Msk (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR4 ========================================================== */ + #define R_SCI0_CCR4_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CCR4_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_CCR4_ASEN_Pos (16UL) /*!< ASEN (Bit 16) */ + #define R_SCI0_CCR4_ASEN_Msk (0x10000UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR4_ATEN_Pos (17UL) /*!< ATEN (Bit 17) */ + #define R_SCI0_CCR4_ATEN_Msk (0x20000UL) /*!< ATEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR4_AST_Pos (24UL) /*!< AST (Bit 24) */ + #define R_SCI0_CCR4_AST_Msk (0x7000000UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_CCR4_AJD_Pos (27UL) /*!< AJD (Bit 27) */ + #define R_SCI0_CCR4_AJD_Msk (0x8000000UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR4_ATT_Pos (28UL) /*!< ATT (Bit 28) */ + #define R_SCI0_CCR4_ATT_Msk (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_CCR4_AET_Pos (31UL) /*!< AET (Bit 31) */ + #define R_SCI0_CCR4_AET_Msk (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_IICDL_Pos (0UL) /*!< IICDL (Bit 0) */ + #define R_SCI0_ICR_IICDL_Msk (0x1fUL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_ICR_IICINTM_Pos (8UL) /*!< IICINTM (Bit 8) */ + #define R_SCI0_ICR_IICINTM_Msk (0x100UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICCSC_Pos (9UL) /*!< IICCSC (Bit 9) */ + #define R_SCI0_ICR_IICCSC_Msk (0x200UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICACKT_Pos (13UL) /*!< IICACKT (Bit 13) */ + #define R_SCI0_ICR_IICACKT_Msk (0x2000UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICSTAREQ_Pos (16UL) /*!< IICSTAREQ (Bit 16) */ + #define R_SCI0_ICR_IICSTAREQ_Msk (0x10000UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICRSTAREQ_Pos (17UL) /*!< IICRSTAREQ (Bit 17) */ + #define R_SCI0_ICR_IICRSTAREQ_Msk (0x20000UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICSTPREQ_Pos (18UL) /*!< IICSTPREQ (Bit 18) */ + #define R_SCI0_ICR_IICSTPREQ_Msk (0x40000UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICSDAS_Pos (20UL) /*!< IICSDAS (Bit 20) */ + #define R_SCI0_ICR_IICSDAS_Msk (0x300000UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_ICR_IICSCLS_Pos (22UL) /*!< IICSCLS (Bit 22) */ + #define R_SCI0_ICR_IICSCLS_Msk (0xc00000UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_DRES_Pos (0UL) /*!< DRES (Bit 0) */ + #define R_SCI0_FCR_DRES_Msk (0x1UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SCI0_FCR_TTRG_Msk (0x1f00UL) /*!< TTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FCR_TFRST_Pos (15UL) /*!< TFRST (Bit 15) */ + #define R_SCI0_FCR_TFRST_Msk (0x8000UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RTRG_Pos (16UL) /*!< RTRG (Bit 16) */ + #define R_SCI0_FCR_RTRG_Msk (0x1f0000UL) /*!< RTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FCR_RFRST_Pos (23UL) /*!< RFRST (Bit 23) */ + #define R_SCI0_FCR_RFRST_Msk (0x800000UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RSTRG_Pos (24UL) /*!< RSTRG (Bit 24) */ + #define R_SCI0_FCR_RSTRG_Msk (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f) */ +/* ========================================================== DCR ========================================================== */ + #define R_SCI0_DCR_DEPOL_Pos (0UL) /*!< DEPOL (Bit 0) */ + #define R_SCI0_DCR_DEPOL_Msk (0x1UL) /*!< DEPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCR_DEAST_Pos (8UL) /*!< DEAST (Bit 8) */ + #define R_SCI0_DCR_DEAST_Msk (0x1f00UL) /*!< DEAST (Bitfield-Mask: 0x1f) */ + #define R_SCI0_DCR_DENGT_Pos (16UL) /*!< DENGT (Bit 16) */ + #define R_SCI0_DCR_DENGT_Msk (0x1f0000UL) /*!< DENGT (Bitfield-Mask: 0x1f) */ +/* ========================================================== CSR ========================================================== */ + #define R_SCI0_CSR_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_CSR_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_RXDMON_Pos (15UL) /*!< RXDMON (Bit 15) */ + #define R_SCI0_CSR_RXDMON_Msk (0x8000UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_DCMF_Pos (16UL) /*!< DCMF (Bit 16) */ + #define R_SCI0_CSR_DCMF_Msk (0x10000UL) /*!< DCMF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_DPER_Pos (17UL) /*!< DPER (Bit 17) */ + #define R_SCI0_CSR_DPER_Msk (0x20000UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_DFER_Pos (18UL) /*!< DFER (Bit 18) */ + #define R_SCI0_CSR_DFER_Msk (0x40000UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI0_CSR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_MFF_Pos (26UL) /*!< MFF (Bit 26) */ + #define R_SCI0_CSR_MFF_Msk (0x4000000UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI0_CSR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI0_CSR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_TDRE_Pos (29UL) /*!< TDRE (Bit 29) */ + #define R_SCI0_CSR_TDRE_Msk (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_TEND_Pos (30UL) /*!< TEND (Bit 30) */ + #define R_SCI0_CSR_TEND_Msk (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_RDRF_Pos (31UL) /*!< RDRF (Bit 31) */ + #define R_SCI0_CSR_RDRF_Msk (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ + #define R_SCI0_ISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_ISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ + #define R_SCI0_ISR_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_ISR_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ +/* ========================================================= FRSR ========================================================== */ + #define R_SCI0_FRSR_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_FRSR_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRSR_R_Pos (8UL) /*!< R (Bit 8) */ + #define R_SCI0_FRSR_R_Msk (0x3f00UL) /*!< R (Bitfield-Mask: 0x3f) */ + #define R_SCI0_FRSR_PNUM_Pos (16UL) /*!< PNUM (Bit 16) */ + #define R_SCI0_FRSR_PNUM_Msk (0x3f0000UL) /*!< PNUM (Bitfield-Mask: 0x3f) */ + #define R_SCI0_FRSR_FNUM_Pos (24UL) /*!< FNUM (Bit 24) */ + #define R_SCI0_FRSR_FNUM_Msk (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f) */ +/* ========================================================= FTSR ========================================================== */ + #define R_SCI0_FTSR_T_Pos (0UL) /*!< T (Bit 0) */ + #define R_SCI0_FTSR_T_Msk (0x3fUL) /*!< T (Bitfield-Mask: 0x3f) */ +/* ========================================================= CFCLR ========================================================= */ + #define R_SCI0_CFCLR_ERSC_Pos (4UL) /*!< ERSC (Bit 4) */ + #define R_SCI0_CFCLR_ERSC_Msk (0x10UL) /*!< ERSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_DCMFC_Pos (16UL) /*!< DCMFC (Bit 16) */ + #define R_SCI0_CFCLR_DCMFC_Msk (0x10000UL) /*!< DCMFC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_DPERC_Pos (17UL) /*!< DPERC (Bit 17) */ + #define R_SCI0_CFCLR_DPERC_Msk (0x20000UL) /*!< DPERC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_DFERC_Pos (18UL) /*!< DFERC (Bit 18) */ + #define R_SCI0_CFCLR_DFERC_Msk (0x40000UL) /*!< DFERC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_ORERC_Pos (24UL) /*!< ORERC (Bit 24) */ + #define R_SCI0_CFCLR_ORERC_Msk (0x1000000UL) /*!< ORERC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_MFFC_Pos (26UL) /*!< MFFC (Bit 26) */ + #define R_SCI0_CFCLR_MFFC_Msk (0x4000000UL) /*!< MFFC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_PERC_Pos (27UL) /*!< PERC (Bit 27) */ + #define R_SCI0_CFCLR_PERC_Msk (0x8000000UL) /*!< PERC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_FERC_Pos (28UL) /*!< FERC (Bit 28) */ + #define R_SCI0_CFCLR_FERC_Msk (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_TDREC_Pos (29UL) /*!< TDREC (Bit 29) */ + #define R_SCI0_CFCLR_TDREC_Msk (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_RDRFC_Pos (31UL) /*!< RDRFC (Bit 31) */ + #define R_SCI0_CFCLR_RDRFC_Msk (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01) */ +/* ======================================================== ICFCLR ========================================================= */ + #define R_SCI0_ICFCLR_IICSTIFC_Pos (3UL) /*!< IICSTIFC (Bit 3) */ + #define R_SCI0_ICFCLR_IICSTIFC_Msk (0x8UL) /*!< IICSTIFC (Bitfield-Mask: 0x01) */ +/* ========================================================= FFCLR ========================================================= */ + #define R_SCI0_FFCLR_DRC_Pos (0UL) /*!< DRC (Bit 0) */ + #define R_SCI0_FFCLR_DRC_Msk (0x1UL) /*!< DRC (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPDR ========================================================== */ + #define R_SPI0_SPDR_SPD_Pos (0UL) /*!< SPD (Bit 0) */ + #define R_SPI0_SPDR_SPD_Msk (0xffffffffUL) /*!< SPD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= MRCKD ========================================================= */ + #define R_SPI0_MRCKD_ARST_Pos (0UL) /*!< ARST (Bit 0) */ + #define R_SPI0_MRCKD_ARST_Msk (0x7UL) /*!< ARST (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPE_Pos (0UL) /*!< SPE (Bit 0) */ + #define R_SPI0_SPCR_SPE_Msk (0x1UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPSCKSEL_Pos (7UL) /*!< SPSCKSEL (Bit 7) */ + #define R_SPI0_SPCR_SPSCKSEL_Msk (0x80UL) /*!< SPSCKSEL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPPE_Pos (8UL) /*!< SPPE (Bit 8) */ + #define R_SPI0_SPCR_SPPE_Msk (0x100UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPOE_Pos (9UL) /*!< SPOE (Bit 9) */ + #define R_SPI0_SPCR_SPOE_Msk (0x200UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_PTE_Pos (11UL) /*!< PTE (Bit 11) */ + #define R_SPI0_SPCR_PTE_Msk (0x800UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SCKASE_Pos (12UL) /*!< SCKASE (Bit 12) */ + #define R_SPI0_SPCR_SCKASE_Msk (0x1000UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_BFDS_Pos (13UL) /*!< BFDS (Bit 13) */ + #define R_SPI0_SPCR_BFDS_Msk (0x2000UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (14UL) /*!< MODFEN (Bit 14) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4000UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (16UL) /*!< SPEIE (Bit 16) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10000UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPRIE_Pos (17UL) /*!< SPRIE (Bit 17) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x20000UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPIIE_Pos (18UL) /*!< SPIIE (Bit 18) */ + #define R_SPI0_SPCR_SPIIE_Msk (0x40000UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPDRES_Pos (19UL) /*!< SPDRES (Bit 19) */ + #define R_SPI0_SPCR_SPDRES_Msk (0x80000UL) /*!< SPDRES (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (20UL) /*!< SPTIE (Bit 20) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x100000UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_CENDIE_Pos (21UL) /*!< CENDIE (Bit 21) */ + #define R_SPI0_SPCR_CENDIE_Msk (0x200000UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (24UL) /*!< SPMS (Bit 24) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1000000UL) /*!< SPMS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPFRF_Pos (25UL) /*!< SPFRF (Bit 25) */ + #define R_SPI0_SPCR_SPFRF_Msk (0x2000000UL) /*!< SPFRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (28UL) /*!< TXMD (Bit 28) */ + #define R_SPI0_SPCR_TXMD_Msk (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCR_MSTR_Pos (30UL) /*!< MSTR (Bit 30) */ + #define R_SPI0_SPCR_MSTR_Msk (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_BPEN_Pos (31UL) /*!< BPEN (Bit 31) */ + #define R_SPI0_SPCR_BPEN_Msk (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SPCRRM ========================================================= */ + #define R_SPI0_SPCRRM_RMFM_Pos (0UL) /*!< RMFM (Bit 0) */ + #define R_SPI0_SPCRRM_RMFM_Msk (0x1fUL) /*!< RMFM (Bitfield-Mask: 0x1f) */ + #define R_SPI0_SPCRRM_RMEDTG_Pos (6UL) /*!< RMEDTG (Bit 6) */ + #define R_SPI0_SPCRRM_RMEDTG_Msk (0x40UL) /*!< RMEDTG (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCRRM_RMSTTG_Pos (7UL) /*!< RMSTTG (Bit 7) */ + #define R_SPI0_SPCRRM_RMSTTG_Msk (0x80UL) /*!< RMSTTG (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDRCR ========================================================= */ + #define R_SPI0_SPDRCR_SPDRC_Pos (0UL) /*!< SPDRC (Bit 0) */ + #define R_SPI0_SPDRCR_SPDRC_Msk (0xffUL) /*!< SPDRC (Bitfield-Mask: 0xff) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPOM_Pos (2UL) /*!< SPOM (Bit 2) */ + #define R_SPI0_SPPCR_SPOM_Msk (0x4UL) /*!< SPOM (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SPSCKDL_Pos (0UL) /*!< SPSCKDL (Bit 0) */ + #define R_SPI0_SPCR2_SPSCKDL_Msk (0x7UL) /*!< SPSCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI0_SPCMD_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI0_SPCMD_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x3000000UL) /*!< SSLA (Bitfield-Mask: 0x03) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SLSEL_Pos (1UL) /*!< SLSEL (Bit 1) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0x6UL) /*!< SLSEL (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (3UL) /*!< SPRDTD (Bit 3) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x8UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SINV_Pos (4UL) /*!< SINV (Bit 4) */ + #define R_SPI0_SPDCR_SINV_Msk (0x10UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (8UL) /*!< SPFC (Bit 8) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x300UL) /*!< SPFC (Bitfield-Mask: 0x03) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_RTRG_Pos (0UL) /*!< RTRG (Bit 0) */ + #define R_SPI0_SPDCR2_RTRG_Msk (0x3UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR2_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SPI0_SPDCR2_TTRG_Msk (0x300UL) /*!< TTRG (Bitfield-Mask: 0x03) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPDRF_Pos (7UL) /*!< SPDRF (Bit 7) */ + #define R_SPI0_SPSR_SPDRF_Msk (0x80UL) /*!< SPDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (8UL) /*!< OVRF (Bit 8) */ + #define R_SPI0_SPSR_OVRF_Msk (0x100UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (9UL) /*!< IDLNF (Bit 9) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x200UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (10UL) /*!< MODF (Bit 10) */ + #define R_SPI0_SPSR_MODF_Msk (0x400UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (11UL) /*!< PERF (Bit 11) */ + #define R_SPI0_SPSR_PERF_Msk (0x800UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (12UL) /*!< UDRF (Bit 12) */ + #define R_SPI0_SPSR_UDRF_Msk (0x1000UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (13UL) /*!< SPTEF (Bit 13) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x2000UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (14UL) /*!< CENDF (Bit 14) */ + #define R_SPI0_SPSR_CENDF_Msk (0x4000UL) /*!< CENDF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPRF_Pos (15UL) /*!< SPRF (Bit 15) */ + #define R_SPI0_SPSR_SPRF_Msk (0x8000UL) /*!< SPRF (Bitfield-Mask: 0x01) */ +/* ======================================================== SPTFSR ========================================================= */ + #define R_SPI0_SPTFSR_TFDN_Pos (0UL) /*!< TFDN (Bit 0) */ + #define R_SPI0_SPTFSR_TFDN_Msk (0x7UL) /*!< TFDN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPRFSR ========================================================= */ + #define R_SPI0_SPRFSR_RFDN_Pos (0UL) /*!< RFDN (Bit 0) */ + #define R_SPI0_SPRFSR_RFDN_Msk (0x7UL) /*!< RFDN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPPSR ========================================================= */ + #define R_SPI0_SPPSR_SPEPS_Pos (0UL) /*!< SPEPS (Bit 0) */ + #define R_SPI0_SPPSR_SPEPS_Msk (0x1UL) /*!< SPEPS (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSRC ========================================================= */ + #define R_SPI0_SPSRC_SPDRFC_Pos (7UL) /*!< SPDRFC (Bit 7) */ + #define R_SPI0_SPSRC_SPDRFC_Msk (0x80UL) /*!< SPDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_OVRFC_Pos (8UL) /*!< OVRFC (Bit 8) */ + #define R_SPI0_SPSRC_OVRFC_Msk (0x100UL) /*!< OVRFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_MODFC_Pos (10UL) /*!< MODFC (Bit 10) */ + #define R_SPI0_SPSRC_MODFC_Msk (0x400UL) /*!< MODFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_PERFC_Pos (11UL) /*!< PERFC (Bit 11) */ + #define R_SPI0_SPSRC_PERFC_Msk (0x800UL) /*!< PERFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_UDRFC_Pos (12UL) /*!< UDRFC (Bit 12) */ + #define R_SPI0_SPSRC_UDRFC_Msk (0x1000UL) /*!< UDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_SPTEFC_Pos (13UL) /*!< SPTEFC (Bit 13) */ + #define R_SPI0_SPSRC_SPTEFC_Msk (0x2000UL) /*!< SPTEFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_CENDFC_Pos (14UL) /*!< CENDFC (Bit 14) */ + #define R_SPI0_SPSRC_CENDFC_Msk (0x4000UL) /*!< CENDFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_SPRFC_Pos (15UL) /*!< SPRFC (Bit 15) */ + #define R_SPI0_SPSRC_SPRFC_Msk (0x8000UL) /*!< SPRFC (Bitfield-Mask: 0x01) */ +/* ========================================================= SPFCR ========================================================= */ + #define R_SPI0_SPFCR_SPFRST_Pos (0UL) /*!< SPFRST (Bit 0) */ + #define R_SPI0_SPFCR_SPFRST_Msk (0x1UL) /*!< SPFRST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC0_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC0_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ + #define R_CRC0_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC0_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC0_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC0_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ +/* ======================================================= CRCDIR_BY ======================================================= */ +/* ======================================================== CRCDOR ========================================================= */ +/* ======================================================= CRCDOR_HA ======================================================= */ +/* ======================================================= CRCDOR_BY ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGIPV ======================================================== */ + #define R_CANFD_CFDGIPV_IPV_Pos (0UL) /*!< IPV (Bit 0) */ + #define R_CANFD_CFDGIPV_IPV_Msk (0xffUL) /*!< IPV (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDGIPV_IPT_Pos (8UL) /*!< IPT (Bit 8) */ + #define R_CANFD_CFDGIPV_IPT_Msk (0x300UL) /*!< IPT (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGIPV_PSI_Pos (16UL) /*!< PSI (Bit 16) */ + #define R_CANFD_CFDGIPV_PSI_Msk (0x3fff0000UL) /*!< PSI (Bitfield-Mask: 0x3fff) */ +/* ======================================================== CFDGCFG ======================================================== */ + #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ + #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ + #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ + #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ + #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ + #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ + #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ + #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ + #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSBTCS_Pos (13UL) /*!< TSBTCS (Bit 13) */ + #define R_CANFD_CFDGCFG_TSBTCS_Msk (0xe000UL) /*!< TSBTCS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ + #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ + #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ + #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ + #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ + #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ + #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ + #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_QOWEIE_Pos (12UL) /*!< QOWEIE (Bit 12) */ + #define R_CANFD_CFDGCTR_QOWEIE_Msk (0x1000UL) /*!< QOWEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_QMEIE_Pos (14UL) /*!< QMEIE (Bit 14) */ + #define R_CANFD_CFDGCTR_QMEIE_Msk (0x4000UL) /*!< QMEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MOWEIE_Pos (15UL) /*!< MOWEIE (Bit 15) */ + #define R_CANFD_CFDGCTR_MOWEIE_Msk (0x8000UL) /*!< MOWEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ + #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ + #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ + #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ + #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ + #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ + #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ + #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ + #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_QOWES_Pos (4UL) /*!< QOWES (Bit 4) */ + #define R_CANFD_CFDGERFL_QOWES_Msk (0x10UL) /*!< QOWES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_QMES_Pos (6UL) /*!< QMES (Bit 6) */ + #define R_CANFD_CFDGERFL_QMES_Msk (0x40UL) /*!< QMES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MOWES_Pos (7UL) /*!< MOWES (Bit 7) */ + #define R_CANFD_CFDGERFL_MOWES_Msk (0x80UL) /*!< MOWES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ + #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF1_Pos (17UL) /*!< EEF1 (Bit 17) */ + #define R_CANFD_CFDGERFL_EEF1_Msk (0x20000UL) /*!< EEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ + #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ + #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ + #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ + #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ + #define R_CANFD_CFDRMND0_RMNS_Pos (0UL) /*!< RMNS (Bit 0) */ + #define R_CANFD_CFDRMND0_RMNS_Msk (0xffffffffUL) /*!< RMNS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ + #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ + #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ + #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ + #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ + #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ + #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFFIE_Pos (16UL) /*!< RFFIE (Bit 16) */ + #define R_CANFD_CFDRFCC_RFFIE_Msk (0x10000UL) /*!< RFFIE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFSTS ======================================================== */ + #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ + #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ + #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ + #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ + #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ + #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRFSTS_RFFIF_Pos (16UL) /*!< RFFIF (Bit 16) */ + #define R_CANFD_CFDRFSTS_RFFIF_Msk (0x10000UL) /*!< RFFIF (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFPCTR ======================================================= */ + #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ + #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ + #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ + #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ + #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ + #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ + #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ + #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ + #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ + #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ + #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ + #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ + #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFCCE ======================================================== */ + #define R_CANFD_CFDCFCCE_CFFIE_Pos (0UL) /*!< CFFIE (Bit 0) */ + #define R_CANFD_CFDCFCCE_CFFIE_Msk (0x1UL) /*!< CFFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos (1UL) /*!< CFOFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk (0x2UL) /*!< CFOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos (2UL) /*!< CFOFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk (0x4UL) /*!< CFOFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFMOWM_Pos (8UL) /*!< CFMOWM (Bit 8) */ + #define R_CANFD_CFDCFCCE_CFMOWM_Msk (0x100UL) /*!< CFMOWM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFBME_Pos (16UL) /*!< CFBME (Bit 16) */ + #define R_CANFD_CFDCFCCE_CFBME_Msk (0x10000UL) /*!< CFBME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCFSTS ======================================================== */ + #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ + #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ + #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ + #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ + #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDCFSTS_CFFIF_Pos (16UL) /*!< CFFIF (Bit 16) */ + #define R_CANFD_CFDCFSTS_CFFIF_Msk (0x10000UL) /*!< CFFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos (17UL) /*!< CFOFRXIF (Bit 17) */ + #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk (0x20000UL) /*!< CFOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos (18UL) /*!< CFOFTXIF (Bit 18) */ + #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk (0x40000UL) /*!< CFOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMOW_Pos (24UL) /*!< CFMOW (Bit 24) */ + #define R_CANFD_CFDCFSTS_CFMOW_Msk (0x1000000UL) /*!< CFMOW (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCFPCTR ======================================================= */ + #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ + #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ + #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ + #define R_CANFD_CFDFESTS_RFXEMP_Msk (0xffUL) /*!< RFXEMP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ + #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x3f00UL) /*!< CFXEMP (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFFSTS ======================================================== */ + #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ + #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0xffUL) /*!< RFXFLL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x3f00UL) /*!< CFXFLL (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFMSTS ======================================================== */ + #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ + #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0xffUL) /*!< RFXMLT (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x3f00UL) /*!< CFXMLT (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDRFISTS ======================================================= */ + #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0xffUL) /*!< RFXIF (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRFISTS_RFXFFLL_Pos (16UL) /*!< RFXFFLL (Bit 16) */ + #define R_CANFD_CFDRFISTS_RFXFFLL_Msk (0xff0000UL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDCFRISTS ======================================================= */ + #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos (0UL) /*!< CFXRXIF (Bit 0) */ + #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk (0x3fUL) /*!< CFXRXIF (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDCFTISTS ======================================================= */ + #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos (0UL) /*!< CFXTXIF (Bit 0) */ + #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk (0x3fUL) /*!< CFXTXIF (Bitfield-Mask: 0x3f) */ +/* ===================================================== CFDCFOFRISTS ====================================================== */ + #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos (0UL) /*!< CFXOFRXIF (Bit 0) */ + #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk (0x3fUL) /*!< CFXOFRXIF (Bitfield-Mask: 0x3f) */ +/* ===================================================== CFDCFOFTISTS ====================================================== */ + #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos (0UL) /*!< CFXOFTXIF (Bit 0) */ + #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk (0x3fUL) /*!< CFXOFTXIF (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDCFMOWSTS ====================================================== */ + #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos (0UL) /*!< CFXMOW (Bit 0) */ + #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk (0x3fUL) /*!< CFXMOW (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFFFSTS ======================================================= */ + #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos (0UL) /*!< RFXFFLL (Bit 0) */ + #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk (0xffUL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos (8UL) /*!< CFXFFLL (Bit 8) */ + #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk (0x3f00UL) /*!< CFXFFLL (Bitfield-Mask: 0x3f) */ +/* ======================================================== CFDTMC ========================================================= */ + #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ + #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ + #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ + #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ + #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ + #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ + #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ + #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ + #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ + #define R_CANFD_CFDTMTRSTS_TMTRSTS_Pos (0UL) /*!< TMTRSTS (Bit 0) */ + #define R_CANFD_CFDTMTRSTS_TMTRSTS_Msk (0xffffUL) /*!< TMTRSTS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ + #define R_CANFD_CFDTMTARSTS_TMTARSTS_Pos (0UL) /*!< TMTARSTS (Bit 0) */ + #define R_CANFD_CFDTMTARSTS_TMTARSTS_Msk (0xffffUL) /*!< TMTARSTS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ + #define R_CANFD_CFDTMTCSTS_TMTCSTS_Pos (0UL) /*!< TMTCSTS (Bit 0) */ + #define R_CANFD_CFDTMTCSTS_TMTCSTS_Msk (0xffffUL) /*!< TMTCSTS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDTMTASTS ======================================================= */ + #define R_CANFD_CFDTMTASTS_TMTASTS_Pos (0UL) /*!< TMTASTS (Bit 0) */ + #define R_CANFD_CFDTMTASTS_TMTASTS_Msk (0xffffUL) /*!< TMTASTS (Bitfield-Mask: 0xffff) */ +/* ======================================================= CFDTMIEC ======================================================== */ + #define R_CANFD_CFDTMIEC_TMIE_Pos (0UL) /*!< TMIE (Bit 0) */ + #define R_CANFD_CFDTMIEC_TMIE_Msk (0xffffUL) /*!< TMIE (Bitfield-Mask: 0xffff) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ + #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC0_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ + #define R_CANFD_CFDTXQCC0_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC0_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC0_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ + #define R_CANFD_CFDTXQSTS0_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC1 ======================================================= */ + #define R_CANFD_CFDTXQCC1_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC1_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC1_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ + #define R_CANFD_CFDTXQCC1_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC1_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC1_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC1_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC1_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS1 ======================================================= */ + #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS1_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ + #define R_CANFD_CFDTXQSTS1_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR1 ====================================================== */ + #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC2 ======================================================= */ + #define R_CANFD_CFDTXQCC2_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC2_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC2_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ + #define R_CANFD_CFDTXQCC2_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC2_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC2_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC2_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC2_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS2 ======================================================= */ + #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS2_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ + #define R_CANFD_CFDTXQSTS2_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR2 ====================================================== */ + #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC3 ======================================================= */ + #define R_CANFD_CFDTXQCC3_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC3_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ + #define R_CANFD_CFDTXQCC3_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC3_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC3_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS3 ======================================================= */ + #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS3_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ + #define R_CANFD_CFDTXQSTS3_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR3 ====================================================== */ + #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTXQESTS ======================================================= */ + #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos (0UL) /*!< TXQxEMP (Bit 0) */ + #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk (0xffUL) /*!< TXQxEMP (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTXQFISTS ====================================================== */ + #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos (0UL) /*!< TXQ0FULL (Bit 0) */ + #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk (0x7UL) /*!< TXQ0FULL (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos (4UL) /*!< TXQ1FULL (Bit 4) */ + #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk (0x70UL) /*!< TXQ1FULL (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQMSTS ======================================================= */ + #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos (0UL) /*!< TXQ0ML (Bit 0) */ + #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk (0x7UL) /*!< TXQ0ML (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos (4UL) /*!< TXQ1ML (Bit 4) */ + #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk (0x70UL) /*!< TXQ1ML (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQISTS ======================================================= */ + #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos (0UL) /*!< TXQ0ISF (Bit 0) */ + #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk (0xfUL) /*!< TXQ0ISF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos (4UL) /*!< TXQ1ISF (Bit 4) */ + #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk (0xf0UL) /*!< TXQ1ISF (Bitfield-Mask: 0x0f) */ +/* ===================================================== CFDTXQOFTISTS ===================================================== */ + #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos (0UL) /*!< TXQ0OFTISF (Bit 0) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk (0xfUL) /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos (4UL) /*!< TXQ1OFTISF (Bit 4) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk (0xf0UL) /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f) */ +/* ===================================================== CFDTXQOFRISTS ===================================================== */ + #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos (0UL) /*!< TXQ0OFRISF (Bit 0) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk (0x7UL) /*!< TXQ0OFRISF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos (4UL) /*!< TXQ1OFRISF (Bit 4) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk (0x70UL) /*!< TXQ1OFRISF (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQFSTS ======================================================= */ + #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos (0UL) /*!< TXQ0FSF (Bit 0) */ + #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk (0xfUL) /*!< TXQ0FSF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos (4UL) /*!< TXQ1FSF (Bit 4) */ + #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk (0xf0UL) /*!< TXQ1FSF (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTHLCC ======================================================== */ + #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ + #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ + #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ + #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ + #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDGE_Pos (11UL) /*!< THLDGE (Bit 11) */ + #define R_CANFD_CFDTHLCC_THLDGE_Msk (0x800UL) /*!< THLDGE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ + #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ + #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ + #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ + #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ + #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ + #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ + #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos (5UL) /*!< TQOFIF0 (Bit 5) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk (0x20UL) /*!< TQOFIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos (6UL) /*!< CFOTIF0 (Bit 6) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk (0x40UL) /*!< CFOTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos (8UL) /*!< TSIF1 (Bit 8) */ + #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk (0x100UL) /*!< TSIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos (9UL) /*!< TAIF1 (Bit 9) */ + #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk (0x200UL) /*!< TAIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos (10UL) /*!< TQIF1 (Bit 10) */ + #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk (0x400UL) /*!< TQIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos (11UL) /*!< CFTIF1 (Bit 11) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk (0x800UL) /*!< CFTIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF1_Pos (12UL) /*!< THIF1 (Bit 12) */ + #define R_CANFD_CFDGTINTSTS0_THIF1_Msk (0x1000UL) /*!< THIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos (13UL) /*!< TQOFIF1 (Bit 13) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk (0x2000UL) /*!< TQOFIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos (14UL) /*!< CFOTIF1 (Bit 14) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk (0x4000UL) /*!< CFOTIF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ + #define R_CANFD_CFDGTSTCFG_C0ICBCE_Pos (0UL) /*!< C0ICBCE (Bit 0) */ + #define R_CANFD_CFDGTSTCFG_C0ICBCE_Msk (0x1UL) /*!< C0ICBCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTSTCFG_C1ICBCE_Pos (1UL) /*!< C1ICBCE (Bit 1) */ + #define R_CANFD_CFDGTSTCFG_C1ICBCE_Msk (0x2UL) /*!< C1ICBCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ + #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos (0UL) /*!< ICBCTME (Bit 0) */ + #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk (0x1UL) /*!< ICBCTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ + #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ + #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ + #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ======================================================= CFDGLOCKK ======================================================= */ + #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ======================================================= CFDCDTCT ======================================================== */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE2_Pos (2UL) /*!< RFDMAE2 (Bit 2) */ + #define R_CANFD_CFDCDTCT_RFDMAE2_Msk (0x4UL) /*!< RFDMAE2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE3_Pos (3UL) /*!< RFDMAE3 (Bit 3) */ + #define R_CANFD_CFDCDTCT_RFDMAE3_Msk (0x8UL) /*!< RFDMAE3 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE4_Pos (4UL) /*!< RFDMAE4 (Bit 4) */ + #define R_CANFD_CFDCDTCT_RFDMAE4_Msk (0x10UL) /*!< RFDMAE4 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE5_Pos (5UL) /*!< RFDMAE5 (Bit 5) */ + #define R_CANFD_CFDCDTCT_RFDMAE5_Msk (0x20UL) /*!< RFDMAE5 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE6_Pos (6UL) /*!< RFDMAE6 (Bit 6) */ + #define R_CANFD_CFDCDTCT_RFDMAE6_Msk (0x40UL) /*!< RFDMAE6 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE7_Pos (7UL) /*!< RFDMAE7 (Bit 7) */ + #define R_CANFD_CFDCDTCT_RFDMAE7_Msk (0x80UL) /*!< RFDMAE7 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE1_Pos (9UL) /*!< CFDMAE1 (Bit 9) */ + #define R_CANFD_CFDCDTCT_CFDMAE1_Msk (0x200UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos (2UL) /*!< RFDMASTS2 (Bit 2) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk (0x4UL) /*!< RFDMASTS2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos (3UL) /*!< RFDMASTS3 (Bit 3) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk (0x8UL) /*!< RFDMASTS3 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos (4UL) /*!< RFDMASTS4 (Bit 4) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk (0x10UL) /*!< RFDMASTS4 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos (5UL) /*!< RFDMASTS5 (Bit 5) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk (0x20UL) /*!< RFDMASTS5 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos (6UL) /*!< RFDMASTS6 (Bit 6) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk (0x40UL) /*!< RFDMASTS6 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos (7UL) /*!< RFDMASTS7 (Bit 7) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk (0x80UL) /*!< RFDMASTS7 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos (9UL) /*!< CFDMASTS1 (Bit 9) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk (0x200UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTTCT ======================================================= */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos (0UL) /*!< TQ0DMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk (0x1UL) /*!< TQ0DMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos (1UL) /*!< TQ0DMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk (0x2UL) /*!< TQ0DMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos (8UL) /*!< TQ3DMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk (0x100UL) /*!< TQ3DMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos (9UL) /*!< TQ3DMAE1 (Bit 9) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk (0x200UL) /*!< TQ3DMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos (16UL) /*!< CFDMAE0 (Bit 16) */ + #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk (0x10000UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos (17UL) /*!< CFDMAE1 (Bit 17) */ + #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk (0x20000UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDCDTTSTS ======================================================= */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos (0UL) /*!< TQ0DMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk (0x1UL) /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos (1UL) /*!< TQ0DMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk (0x2UL) /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos (8UL) /*!< TQ3DMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk (0x100UL) /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos (9UL) /*!< TQ3DMASTS1 (Bit 9) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk (0x200UL) /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos (16UL) /*!< CFDMASTS0 (Bit 16) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk (0x10000UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos (17UL) /*!< CFDMASTS1 (Bit 17) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk (0x20000UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGRINTSTS ====================================================== */ + #define R_CANFD_CFDGRINTSTS_QFIF_Pos (0UL) /*!< QFIF (Bit 0) */ + #define R_CANFD_CFDGRINTSTS_QFIF_Msk (0x7UL) /*!< QFIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_BQFIF_Pos (4UL) /*!< BQFIF (Bit 4) */ + #define R_CANFD_CFDGRINTSTS_BQFIF_Msk (0x30UL) /*!< BQFIF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos (8UL) /*!< QOFRIF (Bit 8) */ + #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk (0x700UL) /*!< QOFRIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_BQOFRIF_Pos (12UL) /*!< BQOFRIF (Bit 12) */ + #define R_CANFD_CFDGRINTSTS_BQOFRIF_Msk (0x3000UL) /*!< BQOFRIF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGRINTSTS_CFRIF_Pos (16UL) /*!< CFRIF (Bit 16) */ + #define R_CANFD_CFDGRINTSTS_CFRIF_Msk (0x70000UL) /*!< CFRIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos (24UL) /*!< CFRFIF (Bit 24) */ + #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk (0x7000000UL) /*!< CFRFIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos (28UL) /*!< CFOFRIF (Bit 28) */ + #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDGRSTC ======================================================== */ + #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ + #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDGFCMC ======================================================== */ + #define R_CANFD_CFDGFCMC_FLXC0_Pos (0UL) /*!< FLXC0 (Bit 0) */ + #define R_CANFD_CFDGFCMC_FLXC0_Msk (0x1UL) /*!< FLXC0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFTBAC ======================================================= */ + #define R_CANFD_CFDGFTBAC_FLXMB0_Pos (0UL) /*!< FLXMB0 (Bit 0) */ + #define R_CANFD_CFDGFTBAC_FLXMB0_Msk (0xfUL) /*!< FLXMB0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDRPGACC ======================================================= */ + #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ + #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CMT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_CMTW0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMWSTR ========================================================= */ + #define R_CMTW0_CMWSTR_STR_Pos (0UL) /*!< STR (Bit 0) */ + #define R_CMTW0_CMWSTR_STR_Msk (0x1UL) /*!< STR (Bitfield-Mask: 0x01) */ +/* ========================================================= CMWCR ========================================================= */ + #define R_CMTW0_CMWCR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_CMTW0_CMWCR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_CMTW0_CMWCR_CMWIE_Pos (3UL) /*!< CMWIE (Bit 3) */ + #define R_CMTW0_CMWCR_CMWIE_Msk (0x8UL) /*!< CMWIE (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_IC0IE_Pos (4UL) /*!< IC0IE (Bit 4) */ + #define R_CMTW0_CMWCR_IC0IE_Msk (0x10UL) /*!< IC0IE (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_IC1IE_Pos (5UL) /*!< IC1IE (Bit 5) */ + #define R_CMTW0_CMWCR_IC1IE_Msk (0x20UL) /*!< IC1IE (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_OC0IE_Pos (6UL) /*!< OC0IE (Bit 6) */ + #define R_CMTW0_CMWCR_OC0IE_Msk (0x40UL) /*!< OC0IE (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_OC1IE_Pos (7UL) /*!< OC1IE (Bit 7) */ + #define R_CMTW0_CMWCR_OC1IE_Msk (0x80UL) /*!< OC1IE (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_CMS_Pos (9UL) /*!< CMS (Bit 9) */ + #define R_CMTW0_CMWCR_CMS_Msk (0x200UL) /*!< CMS (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_CCLR_Pos (13UL) /*!< CCLR (Bit 13) */ + #define R_CMTW0_CMWCR_CCLR_Msk (0xe000UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMWIOR ========================================================= */ + #define R_CMTW0_CMWIOR_IC0_Pos (0UL) /*!< IC0 (Bit 0) */ + #define R_CMTW0_CMWIOR_IC0_Msk (0x3UL) /*!< IC0 (Bitfield-Mask: 0x03) */ + #define R_CMTW0_CMWIOR_IC1_Pos (2UL) /*!< IC1 (Bit 2) */ + #define R_CMTW0_CMWIOR_IC1_Msk (0xcUL) /*!< IC1 (Bitfield-Mask: 0x03) */ + #define R_CMTW0_CMWIOR_IC0E_Pos (4UL) /*!< IC0E (Bit 4) */ + #define R_CMTW0_CMWIOR_IC0E_Msk (0x10UL) /*!< IC0E (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWIOR_IC1E_Pos (5UL) /*!< IC1E (Bit 5) */ + #define R_CMTW0_CMWIOR_IC1E_Msk (0x20UL) /*!< IC1E (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWIOR_OC0_Pos (8UL) /*!< OC0 (Bit 8) */ + #define R_CMTW0_CMWIOR_OC0_Msk (0x300UL) /*!< OC0 (Bitfield-Mask: 0x03) */ + #define R_CMTW0_CMWIOR_OC1_Pos (10UL) /*!< OC1 (Bit 10) */ + #define R_CMTW0_CMWIOR_OC1_Msk (0xc00UL) /*!< OC1 (Bitfield-Mask: 0x03) */ + #define R_CMTW0_CMWIOR_OC0E_Pos (12UL) /*!< OC0E (Bit 12) */ + #define R_CMTW0_CMWIOR_OC0E_Msk (0x1000UL) /*!< OC0E (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWIOR_OC1E_Pos (13UL) /*!< OC1E (Bit 13) */ + #define R_CMTW0_CMWIOR_OC1E_Msk (0x2000UL) /*!< OC1E (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWIOR_CMWE_Pos (15UL) /*!< CMWE (Bit 15) */ + #define R_CMTW0_CMWIOR_CMWE_Msk (0x8000UL) /*!< CMWE (Bitfield-Mask: 0x01) */ +/* ======================================================== CMWCNT ========================================================= */ +/* ======================================================== CMWCOR ========================================================= */ +/* ======================================================== CMWICR0 ======================================================== */ +/* ======================================================== CMWICR1 ======================================================== */ +/* ======================================================== CMWOCR0 ======================================================== */ +/* ======================================================== CMWOCR1 ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_WDT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT0_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT0_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ + #define R_WDT0_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT0_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT0_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT0_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT0_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT0_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT0_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT0_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + #define R_WDT0_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT0_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT0_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT0_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT0_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT0_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ +/* ========================================================= ICDRR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCIE_Pos (4UL) /*!< DOPCIE (Bit 4) */ + #define R_DOC_DOCR_DOPCIE_Msk (0x10UL) /*!< DOPCIE (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ +/* ========================================================= DODIR ========================================================= */ +/* ========================================================= DODSR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_ADC121 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC121_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC121_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC121_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC121_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC121_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC121_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC121_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC121_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC121_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC121_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC121_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA0 ======================================================== */ + #define R_ADC121_ADANSA0_ANSA0_Pos (0UL) /*!< ANSA0 (Bit 0) */ + #define R_ADC121_ADANSA0_ANSA0_Msk (0xffffUL) /*!< ANSA0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADADS0 ========================================================= */ + #define R_ADC121_ADADS0_ADS0_Pos (0UL) /*!< ADS0 (Bit 0) */ + #define R_ADC121_ADADS0_ADS0_Msk (0xffffUL) /*!< ADS0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC121_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC121_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC121_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC121_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC121_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC121_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC121_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC121_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC121_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC121_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC121_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ + #define R_ADC121_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC121_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADANSB0 ======================================================== */ + #define R_ADC121_ADANSB0_ANSB0_Pos (0UL) /*!< ANSB0 (Bit 0) */ + #define R_ADC121_ADANSB0_ANSB0_Msk (0xffffUL) /*!< ANSB0 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC121_ADDBLDR_DBLDR_Pos (0UL) /*!< DBLDR (Bit 0) */ + #define R_ADC121_ADDBLDR_DBLDR_Msk (0xffffUL) /*!< DBLDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC121_ADDR_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_ADC121_ADDR_DR_Msk (0xffffUL) /*!< DR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC121_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC121_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ + #define R_ADC121_ADSHCR_SHANS_Pos (8UL) /*!< SHANS (Bit 8) */ + #define R_ADC121_ADSHCR_SHANS_Msk (0x700UL) /*!< SHANS (Bitfield-Mask: 0x07) */ +/* ======================================================== ADELCCR ======================================================== */ + #define R_ADC121_ADELCCR_ELCC_Pos (0UL) /*!< ELCC (Bit 0) */ + #define R_ADC121_ADELCCR_ELCC_Msk (0x3UL) /*!< ELCC (Bitfield-Mask: 0x03) */ + #define R_ADC121_ADELCCR_GCELC_Pos (2UL) /*!< GCELC (Bit 2) */ + #define R_ADC121_ADELCCR_GCELC_Msk (0x4UL) /*!< GCELC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC121_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC121_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC121_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADGSPCR_LGRRS_Pos (14UL) /*!< LGRRS (Bit 14) */ + #define R_ADC121_ADGSPCR_LGRRS_Msk (0x4000UL) /*!< LGRRS (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC121_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC121_ADDBLDRA_DBLDRA_Pos (0UL) /*!< DBLDRA (Bit 0) */ + #define R_ADC121_ADDBLDRA_DBLDRA_Msk (0xffffUL) /*!< DBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC121_ADDBLDRB_DBLDRB_Pos (0UL) /*!< DBLDRB (Bit 0) */ + #define R_ADC121_ADDBLDRB_DBLDRB_Msk (0xffffUL) /*!< DBLDRB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC121_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC121_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC121_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC121_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC121_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC121_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ + #define R_ADC121_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC121_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC121_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC121_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC121_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC121_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCMPANSR0 ======================================================= */ + #define R_ADC121_ADCMPANSR0_CMPCHA0_Pos (0UL) /*!< CMPCHA0 (Bit 0) */ + #define R_ADC121_ADCMPANSR0_CMPCHA0_Msk (0xffffUL) /*!< CMPCHA0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPLR0 ======================================================== */ + #define R_ADC121_ADCMPLR0_CMPLCHA0_Pos (0UL) /*!< CMPLCHA0 (Bit 0) */ + #define R_ADC121_ADCMPLR0_CMPLCHA0_Msk (0xffffUL) /*!< CMPLCHA0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC121_ADCMPDR0_CMPLLA_Pos (0UL) /*!< CMPLLA (Bit 0) */ + #define R_ADC121_ADCMPDR0_CMPLLA_Msk (0xffffUL) /*!< CMPLLA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC121_ADCMPDR1_CMPULA_Pos (0UL) /*!< CMPULA (Bit 0) */ + #define R_ADC121_ADCMPDR1_CMPULA_Msk (0xffffUL) /*!< CMPULA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPSR0 ======================================================== */ + #define R_ADC121_ADCMPSR0_CMPSTCHA0_Pos (0UL) /*!< CMPSTCHA0 (Bit 0) */ + #define R_ADC121_ADCMPSR0_CMPSTCHA0_Msk (0xffffUL) /*!< CMPSTCHA0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC121_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC121_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ + #define R_ADC121_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC121_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC121_ADWINLLB_CMPLLB_Pos (0UL) /*!< CMPLLB (Bit 0) */ + #define R_ADC121_ADWINLLB_CMPLLB_Msk (0xffffUL) /*!< CMPLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC121_ADWINULB_CMPULB_Pos (0UL) /*!< CMPULB (Bit 0) */ + #define R_ADC121_ADWINULB_CMPULB_Msk (0xffffUL) /*!< CMPULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC121_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC121_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSC0 ======================================================== */ + #define R_ADC121_ADANSC0_ANSC0_Pos (0UL) /*!< ANSC0 (Bit 0) */ + #define R_ADC121_ADANSC0_ANSC0_Msk (0xffffUL) /*!< ANSC0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADGCTRGR ======================================================== */ + #define R_ADC121_ADGCTRGR_TRSC_Pos (0UL) /*!< TRSC (Bit 0) */ + #define R_ADC121_ADGCTRGR_TRSC_Msk (0x3fUL) /*!< TRSC (Bitfield-Mask: 0x3f) */ + #define R_ADC121_ADGCTRGR_GCADIE_Pos (6UL) /*!< GCADIE (Bit 6) */ + #define R_ADC121_ADGCTRGR_GCADIE_Msk (0x40UL) /*!< GCADIE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADGCTRGR_GRCE_Pos (7UL) /*!< GRCE (Bit 7) */ + #define R_ADC121_ADGCTRGR_GRCE_Msk (0x80UL) /*!< GRCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC121_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC121_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSUSM ========================================================= */ + #define R_TSU_TSUSM_TSEN_Pos (0UL) /*!< TSEN (Bit 0) */ + #define R_TSU_TSUSM_TSEN_Msk (0x1UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSU_TSUSM_ADCEN_Pos (1UL) /*!< ADCEN (Bit 1) */ + #define R_TSU_TSUSM_ADCEN_Msk (0x2UL) /*!< ADCEN (Bitfield-Mask: 0x01) */ +/* ========================================================= TSUST ========================================================= */ + #define R_TSU_TSUST_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_TSU_TSUST_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== TSUSCS ========================================================= */ + #define R_TSU_TSUSCS_CKDIV_Pos (3UL) /*!< CKDIV (Bit 3) */ + #define R_TSU_TSUSCS_CKDIV_Msk (0x8UL) /*!< CKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== TSUSAD ========================================================= */ + #define R_TSU_TSUSAD_DOUT_Pos (0UL) /*!< DOUT (Bit 0) */ + #define R_TSU_TSUSAD_DOUT_Msk (0xfffUL) /*!< DOUT (Bitfield-Mask: 0xfff) */ +/* ========================================================= TSUSS ========================================================= */ + #define R_TSU_TSUSS_CONV_Pos (0UL) /*!< CONV (Bit 0) */ + #define R_TSU_TSUSS_CONV_Msk (0x1UL) /*!< CONV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG1 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== POEG1GA ======================================================== */ + #define R_POEG1_POEG1GA_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG1_POEG1GA_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG1_POEG1GA_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG1_POEG1GA_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG1_POEG1GA_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG1_POEG1GA_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG1_POEG1GA_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG1_POEG1GA_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG1_POEG1GA_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG1_POEG1GA_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG1_POEG1GA_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG1_POEG1GA_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG1GB ======================================================== */ + #define R_POEG1_POEG1GB_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG1_POEG1GB_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG1_POEG1GB_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG1_POEG1GB_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG1_POEG1GB_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG1_POEG1GB_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG1_POEG1GB_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG1_POEG1GB_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG1_POEG1GB_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG1_POEG1GB_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG1_POEG1GB_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG1_POEG1GB_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG1GC ======================================================== */ + #define R_POEG1_POEG1GC_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG1_POEG1GC_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG1_POEG1GC_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG1_POEG1GC_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG1_POEG1GC_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG1_POEG1GC_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG1_POEG1GC_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG1_POEG1GC_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG1_POEG1GC_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG1_POEG1GC_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG1_POEG1GC_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG1_POEG1GC_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG1GD ======================================================== */ + #define R_POEG1_POEG1GD_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG1_POEG1GD_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG1_POEG1GD_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG1_POEG1GD_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG1_POEG1GD_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG1_POEG1GD_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG1_POEG1GD_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG1_POEG1GD_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG1_POEG1GD_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG1_POEG1GD_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG1_POEG1GD_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG1_POEG1GD_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_ICU_NS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= NS_SWINT ======================================================== */ + #define R_ICU_NS_NS_SWINT_IC0_Pos (0UL) /*!< IC0 (Bit 0) */ + #define R_ICU_NS_NS_SWINT_IC0_Msk (0x1UL) /*!< IC0 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_SWINT_IC1_Pos (1UL) /*!< IC1 (Bit 1) */ + #define R_ICU_NS_NS_SWINT_IC1_Msk (0x2UL) /*!< IC1 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_SWINT_IC2_Pos (2UL) /*!< IC2 (Bit 2) */ + #define R_ICU_NS_NS_SWINT_IC2_Msk (0x4UL) /*!< IC2 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_SWINT_IC3_Pos (3UL) /*!< IC3 (Bit 3) */ + #define R_ICU_NS_NS_SWINT_IC3_Msk (0x8UL) /*!< IC3 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_SWINT_IC4_Pos (4UL) /*!< IC4 (Bit 4) */ + #define R_ICU_NS_NS_SWINT_IC4_Msk (0x10UL) /*!< IC4 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_SWINT_IC5_Pos (5UL) /*!< IC5 (Bit 5) */ + #define R_ICU_NS_NS_SWINT_IC5_Msk (0x20UL) /*!< IC5 (Bitfield-Mask: 0x01) */ +/* =================================================== NS_PORTNF_FLTSEL ==================================================== */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT0_Pos (0UL) /*!< FLT0 (Bit 0) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT0_Msk (0x1UL) /*!< FLT0 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT1_Pos (1UL) /*!< FLT1 (Bit 1) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT1_Msk (0x2UL) /*!< FLT1 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT2_Pos (2UL) /*!< FLT2 (Bit 2) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT2_Msk (0x4UL) /*!< FLT2 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT3_Pos (3UL) /*!< FLT3 (Bit 3) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT3_Msk (0x8UL) /*!< FLT3 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT4_Pos (4UL) /*!< FLT4 (Bit 4) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT4_Msk (0x10UL) /*!< FLT4 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT5_Pos (5UL) /*!< FLT5 (Bit 5) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT5_Msk (0x20UL) /*!< FLT5 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT6_Pos (6UL) /*!< FLT6 (Bit 6) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT6_Msk (0x40UL) /*!< FLT6 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT7_Pos (7UL) /*!< FLT7 (Bit 7) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT7_Msk (0x80UL) /*!< FLT7 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT8_Pos (8UL) /*!< FLT8 (Bit 8) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT8_Msk (0x100UL) /*!< FLT8 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT9_Pos (9UL) /*!< FLT9 (Bit 9) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT9_Msk (0x200UL) /*!< FLT9 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT10_Pos (10UL) /*!< FLT10 (Bit 10) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT10_Msk (0x400UL) /*!< FLT10 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT11_Pos (11UL) /*!< FLT11 (Bit 11) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT11_Msk (0x800UL) /*!< FLT11 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT12_Pos (12UL) /*!< FLT12 (Bit 12) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT12_Msk (0x1000UL) /*!< FLT12 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT13_Pos (13UL) /*!< FLT13 (Bit 13) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT13_Msk (0x2000UL) /*!< FLT13 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLTDRQ_Pos (14UL) /*!< FLTDRQ (Bit 14) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLTDRQ_Msk (0x4000UL) /*!< FLTDRQ (Bitfield-Mask: 0x01) */ +/* =================================================== NS_PORTNF_CLKSEL ==================================================== */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL0_Pos (0UL) /*!< CKSEL0 (Bit 0) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL0_Msk (0x3UL) /*!< CKSEL0 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL1_Pos (2UL) /*!< CKSEL1 (Bit 2) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL1_Msk (0xcUL) /*!< CKSEL1 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL2_Pos (4UL) /*!< CKSEL2 (Bit 4) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL2_Msk (0x30UL) /*!< CKSEL2 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL3_Pos (6UL) /*!< CKSEL3 (Bit 6) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL3_Msk (0xc0UL) /*!< CKSEL3 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL4_Pos (8UL) /*!< CKSEL4 (Bit 8) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL4_Msk (0x300UL) /*!< CKSEL4 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL5_Pos (10UL) /*!< CKSEL5 (Bit 10) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL5_Msk (0xc00UL) /*!< CKSEL5 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL6_Pos (12UL) /*!< CKSEL6 (Bit 12) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL6_Msk (0x3000UL) /*!< CKSEL6 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL7_Pos (14UL) /*!< CKSEL7 (Bit 14) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL7_Msk (0xc000UL) /*!< CKSEL7 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL8_Pos (16UL) /*!< CKSEL8 (Bit 16) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL8_Msk (0x30000UL) /*!< CKSEL8 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL9_Pos (18UL) /*!< CKSEL9 (Bit 18) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL9_Msk (0xc0000UL) /*!< CKSEL9 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL10_Pos (20UL) /*!< CKSEL10 (Bit 20) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL10_Msk (0x300000UL) /*!< CKSEL10 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL11_Pos (22UL) /*!< CKSEL11 (Bit 22) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL11_Msk (0xc00000UL) /*!< CKSEL11 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL12_Pos (24UL) /*!< CKSEL12 (Bit 24) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL12_Msk (0x3000000UL) /*!< CKSEL12 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL13_Pos (26UL) /*!< CKSEL13 (Bit 26) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL13_Msk (0xc000000UL) /*!< CKSEL13 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSELDREQ_Pos (28UL) /*!< CKSELDREQ (Bit 28) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSELDREQ_Msk (0x30000000UL) /*!< CKSELDREQ (Bitfield-Mask: 0x03) */ +/* ===================================================== NS_PORTNF_MD ====================================================== */ + #define R_ICU_NS_NS_PORTNF_MD_MD0_Pos (0UL) /*!< MD0 (Bit 0) */ + #define R_ICU_NS_NS_PORTNF_MD_MD0_Msk (0x3UL) /*!< MD0 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD1_Pos (2UL) /*!< MD1 (Bit 2) */ + #define R_ICU_NS_NS_PORTNF_MD_MD1_Msk (0xcUL) /*!< MD1 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD2_Pos (4UL) /*!< MD2 (Bit 4) */ + #define R_ICU_NS_NS_PORTNF_MD_MD2_Msk (0x30UL) /*!< MD2 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD3_Pos (6UL) /*!< MD3 (Bit 6) */ + #define R_ICU_NS_NS_PORTNF_MD_MD3_Msk (0xc0UL) /*!< MD3 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD4_Pos (8UL) /*!< MD4 (Bit 8) */ + #define R_ICU_NS_NS_PORTNF_MD_MD4_Msk (0x300UL) /*!< MD4 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD5_Pos (10UL) /*!< MD5 (Bit 10) */ + #define R_ICU_NS_NS_PORTNF_MD_MD5_Msk (0xc00UL) /*!< MD5 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD6_Pos (12UL) /*!< MD6 (Bit 12) */ + #define R_ICU_NS_NS_PORTNF_MD_MD6_Msk (0x3000UL) /*!< MD6 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD7_Pos (14UL) /*!< MD7 (Bit 14) */ + #define R_ICU_NS_NS_PORTNF_MD_MD7_Msk (0xc000UL) /*!< MD7 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD8_Pos (16UL) /*!< MD8 (Bit 16) */ + #define R_ICU_NS_NS_PORTNF_MD_MD8_Msk (0x30000UL) /*!< MD8 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD9_Pos (18UL) /*!< MD9 (Bit 18) */ + #define R_ICU_NS_NS_PORTNF_MD_MD9_Msk (0xc0000UL) /*!< MD9 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD10_Pos (20UL) /*!< MD10 (Bit 20) */ + #define R_ICU_NS_NS_PORTNF_MD_MD10_Msk (0x300000UL) /*!< MD10 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD11_Pos (22UL) /*!< MD11 (Bit 22) */ + #define R_ICU_NS_NS_PORTNF_MD_MD11_Msk (0xc00000UL) /*!< MD11 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD12_Pos (24UL) /*!< MD12 (Bit 24) */ + #define R_ICU_NS_NS_PORTNF_MD_MD12_Msk (0x3000000UL) /*!< MD12 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD13_Pos (26UL) /*!< MD13 (Bit 26) */ + #define R_ICU_NS_NS_PORTNF_MD_MD13_Msk (0xc000000UL) /*!< MD13 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MDDRQ_Pos (28UL) /*!< MDDRQ (Bit 28) */ + #define R_ICU_NS_NS_PORTNF_MD_MDDRQ_Msk (0x30000000UL) /*!< MDDRQ (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= ELC_SSEL ======================================================== */ + #define R_ELC_ELC_SSEL_ELC_SEL0_Pos (0UL) /*!< ELC_SEL0 (Bit 0) */ + #define R_ELC_ELC_SSEL_ELC_SEL0_Msk (0x3ffUL) /*!< ELC_SEL0 (Bitfield-Mask: 0x3ff) */ + #define R_ELC_ELC_SSEL_ELC_SEL1_Pos (10UL) /*!< ELC_SEL1 (Bit 10) */ + #define R_ELC_ELC_SSEL_ELC_SEL1_Msk (0xffc00UL) /*!< ELC_SEL1 (Bitfield-Mask: 0x3ff) */ + #define R_ELC_ELC_SSEL_ELC_SEL2_Pos (20UL) /*!< ELC_SEL2 (Bit 20) */ + #define R_ELC_ELC_SSEL_ELC_SEL2_Msk (0x3ff00000UL) /*!< ELC_SEL2 (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== DMAC0_RSSEL ====================================================== */ + #define R_DMA_DMAC0_RSSEL_REQ_SELA_Pos (0UL) /*!< REQ_SELA (Bit 0) */ + #define R_DMA_DMAC0_RSSEL_REQ_SELA_Msk (0x1ffUL) /*!< REQ_SELA (Bitfield-Mask: 0x1ff) */ + #define R_DMA_DMAC0_RSSEL_REQ_SELB_Pos (10UL) /*!< REQ_SELB (Bit 10) */ + #define R_DMA_DMAC0_RSSEL_REQ_SELB_Msk (0x7fc00UL) /*!< REQ_SELB (Bitfield-Mask: 0x1ff) */ + #define R_DMA_DMAC0_RSSEL_REQ_SELC_Pos (20UL) /*!< REQ_SELC (Bit 20) */ + #define R_DMA_DMAC0_RSSEL_REQ_SELC_Msk (0x1ff00000UL) /*!< REQ_SELC (Bitfield-Mask: 0x1ff) */ +/* ====================================================== DMAC1_RSSEL ====================================================== */ + #define R_DMA_DMAC1_RSSEL_REQ_SELA_Pos (0UL) /*!< REQ_SELA (Bit 0) */ + #define R_DMA_DMAC1_RSSEL_REQ_SELA_Msk (0x1ffUL) /*!< REQ_SELA (Bitfield-Mask: 0x1ff) */ + #define R_DMA_DMAC1_RSSEL_REQ_SELB_Pos (10UL) /*!< REQ_SELB (Bit 10) */ + #define R_DMA_DMAC1_RSSEL_REQ_SELB_Msk (0x7fc00UL) /*!< REQ_SELB (Bitfield-Mask: 0x1ff) */ + #define R_DMA_DMAC1_RSSEL_REQ_SELC_Pos (20UL) /*!< REQ_SELC (Bit 20) */ + #define R_DMA_DMAC1_RSSEL_REQ_SELC_Msk (0x1ff00000UL) /*!< REQ_SELC (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT_COMMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== P =========================================================== */ + #define R_PORT_NSR_P_POUT_0_Pos (0UL) /*!< POUT_0 (Bit 0) */ + #define R_PORT_NSR_P_POUT_0_Msk (0x1UL) /*!< POUT_0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_1_Pos (1UL) /*!< POUT_1 (Bit 1) */ + #define R_PORT_NSR_P_POUT_1_Msk (0x2UL) /*!< POUT_1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_2_Pos (2UL) /*!< POUT_2 (Bit 2) */ + #define R_PORT_NSR_P_POUT_2_Msk (0x4UL) /*!< POUT_2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_3_Pos (3UL) /*!< POUT_3 (Bit 3) */ + #define R_PORT_NSR_P_POUT_3_Msk (0x8UL) /*!< POUT_3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_4_Pos (4UL) /*!< POUT_4 (Bit 4) */ + #define R_PORT_NSR_P_POUT_4_Msk (0x10UL) /*!< POUT_4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_5_Pos (5UL) /*!< POUT_5 (Bit 5) */ + #define R_PORT_NSR_P_POUT_5_Msk (0x20UL) /*!< POUT_5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_6_Pos (6UL) /*!< POUT_6 (Bit 6) */ + #define R_PORT_NSR_P_POUT_6_Msk (0x40UL) /*!< POUT_6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_7_Pos (7UL) /*!< POUT_7 (Bit 7) */ + #define R_PORT_NSR_P_POUT_7_Msk (0x80UL) /*!< POUT_7 (Bitfield-Mask: 0x01) */ +/* ========================================================== PM =========================================================== */ + #define R_PORT_NSR_PM_PM0_Pos (0UL) /*!< PM0 (Bit 0) */ + #define R_PORT_NSR_PM_PM0_Msk (0x3UL) /*!< PM0 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM1_Pos (2UL) /*!< PM1 (Bit 2) */ + #define R_PORT_NSR_PM_PM1_Msk (0xcUL) /*!< PM1 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM2_Pos (4UL) /*!< PM2 (Bit 4) */ + #define R_PORT_NSR_PM_PM2_Msk (0x30UL) /*!< PM2 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM3_Pos (6UL) /*!< PM3 (Bit 6) */ + #define R_PORT_NSR_PM_PM3_Msk (0xc0UL) /*!< PM3 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM4_Pos (8UL) /*!< PM4 (Bit 8) */ + #define R_PORT_NSR_PM_PM4_Msk (0x300UL) /*!< PM4 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM5_Pos (10UL) /*!< PM5 (Bit 10) */ + #define R_PORT_NSR_PM_PM5_Msk (0xc00UL) /*!< PM5 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM6_Pos (12UL) /*!< PM6 (Bit 12) */ + #define R_PORT_NSR_PM_PM6_Msk (0x3000UL) /*!< PM6 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM7_Pos (14UL) /*!< PM7 (Bit 14) */ + #define R_PORT_NSR_PM_PM7_Msk (0xc000UL) /*!< PM7 (Bitfield-Mask: 0x03) */ +/* ========================================================== PMC ========================================================== */ + #define R_PORT_NSR_PMC_PMC0_Pos (0UL) /*!< PMC0 (Bit 0) */ + #define R_PORT_NSR_PMC_PMC0_Msk (0x1UL) /*!< PMC0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC1_Pos (1UL) /*!< PMC1 (Bit 1) */ + #define R_PORT_NSR_PMC_PMC1_Msk (0x2UL) /*!< PMC1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC2_Pos (2UL) /*!< PMC2 (Bit 2) */ + #define R_PORT_NSR_PMC_PMC2_Msk (0x4UL) /*!< PMC2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC3_Pos (3UL) /*!< PMC3 (Bit 3) */ + #define R_PORT_NSR_PMC_PMC3_Msk (0x8UL) /*!< PMC3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC4_Pos (4UL) /*!< PMC4 (Bit 4) */ + #define R_PORT_NSR_PMC_PMC4_Msk (0x10UL) /*!< PMC4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC5_Pos (5UL) /*!< PMC5 (Bit 5) */ + #define R_PORT_NSR_PMC_PMC5_Msk (0x20UL) /*!< PMC5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC6_Pos (6UL) /*!< PMC6 (Bit 6) */ + #define R_PORT_NSR_PMC_PMC6_Msk (0x40UL) /*!< PMC6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC7_Pos (7UL) /*!< PMC7 (Bit 7) */ + #define R_PORT_NSR_PMC_PMC7_Msk (0x80UL) /*!< PMC7 (Bitfield-Mask: 0x01) */ +/* ========================================================== PFC ========================================================== */ + #define R_PORT_NSR_PFC_PFC0_Pos (0UL) /*!< PFC0 (Bit 0) */ + #define R_PORT_NSR_PFC_PFC0_Msk (0xfUL) /*!< PFC0 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC1_Pos (4UL) /*!< PFC1 (Bit 4) */ + #define R_PORT_NSR_PFC_PFC1_Msk (0xf0UL) /*!< PFC1 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC2_Pos (8UL) /*!< PFC2 (Bit 8) */ + #define R_PORT_NSR_PFC_PFC2_Msk (0xf00UL) /*!< PFC2 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC3_Pos (12UL) /*!< PFC3 (Bit 12) */ + #define R_PORT_NSR_PFC_PFC3_Msk (0xf000UL) /*!< PFC3 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC4_Pos (16UL) /*!< PFC4 (Bit 16) */ + #define R_PORT_NSR_PFC_PFC4_Msk (0xf0000UL) /*!< PFC4 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC5_Pos (20UL) /*!< PFC5 (Bit 20) */ + #define R_PORT_NSR_PFC_PFC5_Msk (0xf00000UL) /*!< PFC5 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC6_Pos (24UL) /*!< PFC6 (Bit 24) */ + #define R_PORT_NSR_PFC_PFC6_Msk (0xf000000UL) /*!< PFC6 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC7_Pos (28UL) /*!< PFC7 (Bit 28) */ + #define R_PORT_NSR_PFC_PFC7_Msk (0xf0000000UL) /*!< PFC7 (Bitfield-Mask: 0x0f) */ +/* ========================================================== PIN ========================================================== */ + #define R_PORT_NSR_PIN_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ + #define R_PORT_NSR_PIN_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ + #define R_PORT_NSR_PIN_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ + #define R_PORT_NSR_PIN_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ + #define R_PORT_NSR_PIN_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ + #define R_PORT_NSR_PIN_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ + #define R_PORT_NSR_PIN_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ + #define R_PORT_NSR_PIN_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ + #define R_PORT_NSR_PIN_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELC_PGR ======================================================== */ + #define R_PORT_NSR_ELC_PGR_PG0_Pos (0UL) /*!< PG0 (Bit 0) */ + #define R_PORT_NSR_ELC_PGR_PG0_Msk (0x1UL) /*!< PG0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG1_Pos (1UL) /*!< PG1 (Bit 1) */ + #define R_PORT_NSR_ELC_PGR_PG1_Msk (0x2UL) /*!< PG1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG2_Pos (2UL) /*!< PG2 (Bit 2) */ + #define R_PORT_NSR_ELC_PGR_PG2_Msk (0x4UL) /*!< PG2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG3_Pos (3UL) /*!< PG3 (Bit 3) */ + #define R_PORT_NSR_ELC_PGR_PG3_Msk (0x8UL) /*!< PG3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG4_Pos (4UL) /*!< PG4 (Bit 4) */ + #define R_PORT_NSR_ELC_PGR_PG4_Msk (0x10UL) /*!< PG4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG5_Pos (5UL) /*!< PG5 (Bit 5) */ + #define R_PORT_NSR_ELC_PGR_PG5_Msk (0x20UL) /*!< PG5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG6_Pos (6UL) /*!< PG6 (Bit 6) */ + #define R_PORT_NSR_ELC_PGR_PG6_Msk (0x40UL) /*!< PG6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG7_Pos (7UL) /*!< PG7 (Bit 7) */ + #define R_PORT_NSR_ELC_PGR_PG7_Msk (0x80UL) /*!< PG7 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELC_PGC ======================================================== */ + #define R_PORT_NSR_ELC_PGC_PGCI_Pos (0UL) /*!< PGCI (Bit 0) */ + #define R_PORT_NSR_ELC_PGC_PGCI_Msk (0x3UL) /*!< PGCI (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_ELC_PGC_PGCOVE_Pos (2UL) /*!< PGCOVE (Bit 2) */ + #define R_PORT_NSR_ELC_PGC_PGCOVE_Msk (0x4UL) /*!< PGCOVE (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGC_PGCO_Pos (4UL) /*!< PGCO (Bit 4) */ + #define R_PORT_NSR_ELC_PGC_PGCO_Msk (0x70UL) /*!< PGCO (Bitfield-Mask: 0x07) */ +/* ======================================================== ELC_PEL ======================================================== */ + #define R_PORT_NSR_ELC_PEL_PSB_Pos (0UL) /*!< PSB (Bit 0) */ + #define R_PORT_NSR_ELC_PEL_PSB_Msk (0x7UL) /*!< PSB (Bitfield-Mask: 0x07) */ + #define R_PORT_NSR_ELC_PEL_PSP_Pos (3UL) /*!< PSP (Bit 3) */ + #define R_PORT_NSR_ELC_PEL_PSP_Msk (0x18UL) /*!< PSP (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_ELC_PEL_PSM_Pos (5UL) /*!< PSM (Bit 5) */ + #define R_PORT_NSR_ELC_PEL_PSM_Msk (0x60UL) /*!< PSM (Bitfield-Mask: 0x03) */ +/* ======================================================= ELC_DPTC ======================================================== */ + #define R_PORT_NSR_ELC_DPTC_PTC0_Pos (0UL) /*!< PTC0 (Bit 0) */ + #define R_PORT_NSR_ELC_DPTC_PTC0_Msk (0x1UL) /*!< PTC0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_DPTC_PTC1_Pos (1UL) /*!< PTC1 (Bit 1) */ + #define R_PORT_NSR_ELC_DPTC_PTC1_Msk (0x2UL) /*!< PTC1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_DPTC_PTC2_Pos (2UL) /*!< PTC2 (Bit 2) */ + #define R_PORT_NSR_ELC_DPTC_PTC2_Msk (0x4UL) /*!< PTC2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_DPTC_PTC3_Pos (3UL) /*!< PTC3 (Bit 3) */ + #define R_PORT_NSR_ELC_DPTC_PTC3_Msk (0x8UL) /*!< PTC3 (Bitfield-Mask: 0x01) */ +/* ======================================================= ELC_ELSR2 ======================================================= */ + #define R_PORT_NSR_ELC_ELSR2_PEG1_Pos (2UL) /*!< PEG1 (Bit 2) */ + #define R_PORT_NSR_ELC_ELSR2_PEG1_Msk (0x4UL) /*!< PEG1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_ELSR2_PEG2_Pos (3UL) /*!< PEG2 (Bit 3) */ + #define R_PORT_NSR_ELC_ELSR2_PEG2_Msk (0x8UL) /*!< PEG2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_ELSR2_PES0_Pos (4UL) /*!< PES0 (Bit 4) */ + #define R_PORT_NSR_ELC_ELSR2_PES0_Msk (0x10UL) /*!< PES0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_ELSR2_PES1_Pos (5UL) /*!< PES1 (Bit 5) */ + #define R_PORT_NSR_ELC_ELSR2_PES1_Msk (0x20UL) /*!< PES1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_ELSR2_PES2_Pos (6UL) /*!< PES2 (Bit 6) */ + #define R_PORT_NSR_ELC_ELSR2_PES2_Msk (0x40UL) /*!< PES2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_ELSR2_PES3_Pos (7UL) /*!< PES3 (Bit 7) */ + #define R_PORT_NSR_ELC_ELSR2_PES3_Msk (0x80UL) /*!< PES3 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GMAC ================ */ +/* =========================================================================================================================== */ + +/* =================================================== MAC_Configuration =================================================== */ + #define R_GMAC_MAC_Configuration_PRELEN_Pos (0UL) /*!< PRELEN (Bit 0) */ + #define R_GMAC_MAC_Configuration_PRELEN_Msk (0x3UL) /*!< PRELEN (Bitfield-Mask: 0x03) */ + #define R_GMAC_MAC_Configuration_RE_Pos (2UL) /*!< RE (Bit 2) */ + #define R_GMAC_MAC_Configuration_RE_Msk (0x4UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_TE_Pos (3UL) /*!< TE (Bit 3) */ + #define R_GMAC_MAC_Configuration_TE_Msk (0x8UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_DC_Pos (4UL) /*!< DC (Bit 4) */ + #define R_GMAC_MAC_Configuration_DC_Msk (0x10UL) /*!< DC (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_BL_Pos (5UL) /*!< BL (Bit 5) */ + #define R_GMAC_MAC_Configuration_BL_Msk (0x60UL) /*!< BL (Bitfield-Mask: 0x03) */ + #define R_GMAC_MAC_Configuration_ACS_Pos (7UL) /*!< ACS (Bit 7) */ + #define R_GMAC_MAC_Configuration_ACS_Msk (0x80UL) /*!< ACS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_DR_Pos (9UL) /*!< DR (Bit 9) */ + #define R_GMAC_MAC_Configuration_DR_Msk (0x200UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_IPC_Pos (10UL) /*!< IPC (Bit 10) */ + #define R_GMAC_MAC_Configuration_IPC_Msk (0x400UL) /*!< IPC (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_DM_Pos (11UL) /*!< DM (Bit 11) */ + #define R_GMAC_MAC_Configuration_DM_Msk (0x800UL) /*!< DM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_LM_Pos (12UL) /*!< LM (Bit 12) */ + #define R_GMAC_MAC_Configuration_LM_Msk (0x1000UL) /*!< LM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_DO_Pos (13UL) /*!< DO (Bit 13) */ + #define R_GMAC_MAC_Configuration_DO_Msk (0x2000UL) /*!< DO (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_FES_Pos (14UL) /*!< FES (Bit 14) */ + #define R_GMAC_MAC_Configuration_FES_Msk (0x4000UL) /*!< FES (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_PS_Pos (15UL) /*!< PS (Bit 15) */ + #define R_GMAC_MAC_Configuration_PS_Msk (0x8000UL) /*!< PS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_DCRS_Pos (16UL) /*!< DCRS (Bit 16) */ + #define R_GMAC_MAC_Configuration_DCRS_Msk (0x10000UL) /*!< DCRS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_IFG_Pos (17UL) /*!< IFG (Bit 17) */ + #define R_GMAC_MAC_Configuration_IFG_Msk (0xe0000UL) /*!< IFG (Bitfield-Mask: 0x07) */ + #define R_GMAC_MAC_Configuration_JE_Pos (20UL) /*!< JE (Bit 20) */ + #define R_GMAC_MAC_Configuration_JE_Msk (0x100000UL) /*!< JE (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_BE_Pos (21UL) /*!< BE (Bit 21) */ + #define R_GMAC_MAC_Configuration_BE_Msk (0x200000UL) /*!< BE (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_JD_Pos (22UL) /*!< JD (Bit 22) */ + #define R_GMAC_MAC_Configuration_JD_Msk (0x400000UL) /*!< JD (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_WD_Pos (23UL) /*!< WD (Bit 23) */ + #define R_GMAC_MAC_Configuration_WD_Msk (0x800000UL) /*!< WD (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_CST_Pos (25UL) /*!< CST (Bit 25) */ + #define R_GMAC_MAC_Configuration_CST_Msk (0x2000000UL) /*!< CST (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_TWOKPE_Pos (27UL) /*!< TWOKPE (Bit 27) */ + #define R_GMAC_MAC_Configuration_TWOKPE_Msk (0x8000000UL) /*!< TWOKPE (Bitfield-Mask: 0x01) */ +/* =================================================== MAC_Frame_Filter ==================================================== */ + #define R_GMAC_MAC_Frame_Filter_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_GMAC_MAC_Frame_Filter_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_HUC_Pos (1UL) /*!< HUC (Bit 1) */ + #define R_GMAC_MAC_Frame_Filter_HUC_Msk (0x2UL) /*!< HUC (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_HMC_Pos (2UL) /*!< HMC (Bit 2) */ + #define R_GMAC_MAC_Frame_Filter_HMC_Msk (0x4UL) /*!< HMC (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_DAIF_Pos (3UL) /*!< DAIF (Bit 3) */ + #define R_GMAC_MAC_Frame_Filter_DAIF_Msk (0x8UL) /*!< DAIF (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_GMAC_MAC_Frame_Filter_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_DBF_Pos (5UL) /*!< DBF (Bit 5) */ + #define R_GMAC_MAC_Frame_Filter_DBF_Msk (0x20UL) /*!< DBF (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_PCF_Pos (6UL) /*!< PCF (Bit 6) */ + #define R_GMAC_MAC_Frame_Filter_PCF_Msk (0xc0UL) /*!< PCF (Bitfield-Mask: 0x03) */ + #define R_GMAC_MAC_Frame_Filter_SAIF_Pos (8UL) /*!< SAIF (Bit 8) */ + #define R_GMAC_MAC_Frame_Filter_SAIF_Msk (0x100UL) /*!< SAIF (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_SAF_Pos (9UL) /*!< SAF (Bit 9) */ + #define R_GMAC_MAC_Frame_Filter_SAF_Msk (0x200UL) /*!< SAF (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_HPF_Pos (10UL) /*!< HPF (Bit 10) */ + #define R_GMAC_MAC_Frame_Filter_HPF_Msk (0x400UL) /*!< HPF (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_VTFE_Pos (16UL) /*!< VTFE (Bit 16) */ + #define R_GMAC_MAC_Frame_Filter_VTFE_Msk (0x10000UL) /*!< VTFE (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_RA_Pos (31UL) /*!< RA (Bit 31) */ + #define R_GMAC_MAC_Frame_Filter_RA_Msk (0x80000000UL) /*!< RA (Bitfield-Mask: 0x01) */ +/* ===================================================== GMII_Address ====================================================== */ + #define R_GMAC_GMII_Address_GB_Pos (0UL) /*!< GB (Bit 0) */ + #define R_GMAC_GMII_Address_GB_Msk (0x1UL) /*!< GB (Bitfield-Mask: 0x01) */ + #define R_GMAC_GMII_Address_GW_Pos (1UL) /*!< GW (Bit 1) */ + #define R_GMAC_GMII_Address_GW_Msk (0x2UL) /*!< GW (Bitfield-Mask: 0x01) */ + #define R_GMAC_GMII_Address_CR_Pos (2UL) /*!< CR (Bit 2) */ + #define R_GMAC_GMII_Address_CR_Msk (0x3cUL) /*!< CR (Bitfield-Mask: 0x0f) */ + #define R_GMAC_GMII_Address_GR_Pos (6UL) /*!< GR (Bit 6) */ + #define R_GMAC_GMII_Address_GR_Msk (0x7c0UL) /*!< GR (Bitfield-Mask: 0x1f) */ + #define R_GMAC_GMII_Address_PA_Pos (11UL) /*!< PA (Bit 11) */ + #define R_GMAC_GMII_Address_PA_Msk (0xf800UL) /*!< PA (Bitfield-Mask: 0x1f) */ +/* ======================================================= GMII_Data ======================================================= */ + #define R_GMAC_GMII_Data_GD_Pos (0UL) /*!< GD (Bit 0) */ + #define R_GMAC_GMII_Data_GD_Msk (0xffffUL) /*!< GD (Bitfield-Mask: 0xffff) */ +/* ===================================================== Flow_Control ====================================================== */ + #define R_GMAC_Flow_Control_FCA_BPA_Pos (0UL) /*!< FCA_BPA (Bit 0) */ + #define R_GMAC_Flow_Control_FCA_BPA_Msk (0x1UL) /*!< FCA_BPA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Flow_Control_TFE_Pos (1UL) /*!< TFE (Bit 1) */ + #define R_GMAC_Flow_Control_TFE_Msk (0x2UL) /*!< TFE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Flow_Control_RFE_Pos (2UL) /*!< RFE (Bit 2) */ + #define R_GMAC_Flow_Control_RFE_Msk (0x4UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Flow_Control_UP_Pos (3UL) /*!< UP (Bit 3) */ + #define R_GMAC_Flow_Control_UP_Msk (0x8UL) /*!< UP (Bitfield-Mask: 0x01) */ + #define R_GMAC_Flow_Control_PLT_Pos (4UL) /*!< PLT (Bit 4) */ + #define R_GMAC_Flow_Control_PLT_Msk (0x30UL) /*!< PLT (Bitfield-Mask: 0x03) */ + #define R_GMAC_Flow_Control_DZPQ_Pos (7UL) /*!< DZPQ (Bit 7) */ + #define R_GMAC_Flow_Control_DZPQ_Msk (0x80UL) /*!< DZPQ (Bitfield-Mask: 0x01) */ + #define R_GMAC_Flow_Control_PT_Pos (16UL) /*!< PT (Bit 16) */ + #define R_GMAC_Flow_Control_PT_Msk (0xffff0000UL) /*!< PT (Bitfield-Mask: 0xffff) */ +/* ======================================================= VLAN_Tag ======================================================== */ + #define R_GMAC_VLAN_Tag_VL_Pos (0UL) /*!< VL (Bit 0) */ + #define R_GMAC_VLAN_Tag_VL_Msk (0xffffUL) /*!< VL (Bitfield-Mask: 0xffff) */ + #define R_GMAC_VLAN_Tag_ETV_Pos (16UL) /*!< ETV (Bit 16) */ + #define R_GMAC_VLAN_Tag_ETV_Msk (0x10000UL) /*!< ETV (Bitfield-Mask: 0x01) */ + #define R_GMAC_VLAN_Tag_VTIM_Pos (17UL) /*!< VTIM (Bit 17) */ + #define R_GMAC_VLAN_Tag_VTIM_Msk (0x20000UL) /*!< VTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_VLAN_Tag_ESVL_Pos (18UL) /*!< ESVL (Bit 18) */ + #define R_GMAC_VLAN_Tag_ESVL_Msk (0x40000UL) /*!< ESVL (Bitfield-Mask: 0x01) */ + #define R_GMAC_VLAN_Tag_VTHM_Pos (19UL) /*!< VTHM (Bit 19) */ + #define R_GMAC_VLAN_Tag_VTHM_Msk (0x80000UL) /*!< VTHM (Bitfield-Mask: 0x01) */ +/* ======================================================== Version ======================================================== */ + #define R_GMAC_Version_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_GMAC_Version_VER_Msk (0xffffUL) /*!< VER (Bitfield-Mask: 0xffff) */ +/* ========================================================= Debug ========================================================= */ + #define R_GMAC_Debug_RPESTS_Pos (0UL) /*!< RPESTS (Bit 0) */ + #define R_GMAC_Debug_RPESTS_Msk (0x1UL) /*!< RPESTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_RFCFCSTS_Pos (1UL) /*!< RFCFCSTS (Bit 1) */ + #define R_GMAC_Debug_RFCFCSTS_Msk (0x6UL) /*!< RFCFCSTS (Bitfield-Mask: 0x03) */ + #define R_GMAC_Debug_RWCSTS_Pos (4UL) /*!< RWCSTS (Bit 4) */ + #define R_GMAC_Debug_RWCSTS_Msk (0x10UL) /*!< RWCSTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_RRCSTS_Pos (5UL) /*!< RRCSTS (Bit 5) */ + #define R_GMAC_Debug_RRCSTS_Msk (0x60UL) /*!< RRCSTS (Bitfield-Mask: 0x03) */ + #define R_GMAC_Debug_RXFSTS_Pos (8UL) /*!< RXFSTS (Bit 8) */ + #define R_GMAC_Debug_RXFSTS_Msk (0x300UL) /*!< RXFSTS (Bitfield-Mask: 0x03) */ + #define R_GMAC_Debug_TPESTS_Pos (16UL) /*!< TPESTS (Bit 16) */ + #define R_GMAC_Debug_TPESTS_Msk (0x10000UL) /*!< TPESTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_TFCSTS_Pos (17UL) /*!< TFCSTS (Bit 17) */ + #define R_GMAC_Debug_TFCSTS_Msk (0x60000UL) /*!< TFCSTS (Bitfield-Mask: 0x03) */ + #define R_GMAC_Debug_TXPAUSED_Pos (19UL) /*!< TXPAUSED (Bit 19) */ + #define R_GMAC_Debug_TXPAUSED_Msk (0x80000UL) /*!< TXPAUSED (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_TRCSTS_Pos (20UL) /*!< TRCSTS (Bit 20) */ + #define R_GMAC_Debug_TRCSTS_Msk (0x300000UL) /*!< TRCSTS (Bitfield-Mask: 0x03) */ + #define R_GMAC_Debug_TWCSTS_Pos (22UL) /*!< TWCSTS (Bit 22) */ + #define R_GMAC_Debug_TWCSTS_Msk (0x400000UL) /*!< TWCSTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_TXFSTS_Pos (24UL) /*!< TXFSTS (Bit 24) */ + #define R_GMAC_Debug_TXFSTS_Msk (0x1000000UL) /*!< TXFSTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_TXSTSFSTS_Pos (25UL) /*!< TXSTSFSTS (Bit 25) */ + #define R_GMAC_Debug_TXSTSFSTS_Msk (0x2000000UL) /*!< TXSTSFSTS (Bitfield-Mask: 0x01) */ +/* ============================================== Remote_Wake_Up_Frame_Filter ============================================== */ + #define R_GMAC_Remote_Wake_Up_Frame_Filter_WKUPFRMFTR_Pos (0UL) /*!< WKUPFRMFTR (Bit 0) */ + #define R_GMAC_Remote_Wake_Up_Frame_Filter_WKUPFRMFTR_Msk (0xffffffffUL) /*!< WKUPFRMFTR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PMT_Control_Status =================================================== */ + #define R_GMAC_PMT_Control_Status_PWRDWN_Pos (0UL) /*!< PWRDWN (Bit 0) */ + #define R_GMAC_PMT_Control_Status_PWRDWN_Msk (0x1UL) /*!< PWRDWN (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_MGKPKTEN_Pos (1UL) /*!< MGKPKTEN (Bit 1) */ + #define R_GMAC_PMT_Control_Status_MGKPKTEN_Msk (0x2UL) /*!< MGKPKTEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_RWKPKTEN_Pos (2UL) /*!< RWKPKTEN (Bit 2) */ + #define R_GMAC_PMT_Control_Status_RWKPKTEN_Msk (0x4UL) /*!< RWKPKTEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_MGKPRCVD_Pos (5UL) /*!< MGKPRCVD (Bit 5) */ + #define R_GMAC_PMT_Control_Status_MGKPRCVD_Msk (0x20UL) /*!< MGKPRCVD (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_RWKPRCVD_Pos (6UL) /*!< RWKPRCVD (Bit 6) */ + #define R_GMAC_PMT_Control_Status_RWKPRCVD_Msk (0x40UL) /*!< RWKPRCVD (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_GLBLUCAST_Pos (9UL) /*!< GLBLUCAST (Bit 9) */ + #define R_GMAC_PMT_Control_Status_GLBLUCAST_Msk (0x200UL) /*!< GLBLUCAST (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_RWKPTR_Pos (24UL) /*!< RWKPTR (Bit 24) */ + #define R_GMAC_PMT_Control_Status_RWKPTR_Msk (0x7000000UL) /*!< RWKPTR (Bitfield-Mask: 0x07) */ + #define R_GMAC_PMT_Control_Status_RWKFILTRST_Pos (31UL) /*!< RWKFILTRST (Bit 31) */ + #define R_GMAC_PMT_Control_Status_RWKFILTRST_Msk (0x80000000UL) /*!< RWKFILTRST (Bitfield-Mask: 0x01) */ +/* ================================================== LPI_Control_Status =================================================== */ + #define R_GMAC_LPI_Control_Status_TLPIEN_Pos (0UL) /*!< TLPIEN (Bit 0) */ + #define R_GMAC_LPI_Control_Status_TLPIEN_Msk (0x1UL) /*!< TLPIEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_TLPIEX_Pos (1UL) /*!< TLPIEX (Bit 1) */ + #define R_GMAC_LPI_Control_Status_TLPIEX_Msk (0x2UL) /*!< TLPIEX (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_RLPIEN_Pos (2UL) /*!< RLPIEN (Bit 2) */ + #define R_GMAC_LPI_Control_Status_RLPIEN_Msk (0x4UL) /*!< RLPIEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_RLPIEX_Pos (3UL) /*!< RLPIEX (Bit 3) */ + #define R_GMAC_LPI_Control_Status_RLPIEX_Msk (0x8UL) /*!< RLPIEX (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_TLPIST_Pos (8UL) /*!< TLPIST (Bit 8) */ + #define R_GMAC_LPI_Control_Status_TLPIST_Msk (0x100UL) /*!< TLPIST (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_RLPIST_Pos (9UL) /*!< RLPIST (Bit 9) */ + #define R_GMAC_LPI_Control_Status_RLPIST_Msk (0x200UL) /*!< RLPIST (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_LPIEN_Pos (16UL) /*!< LPIEN (Bit 16) */ + #define R_GMAC_LPI_Control_Status_LPIEN_Msk (0x10000UL) /*!< LPIEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_PLS_Pos (17UL) /*!< PLS (Bit 17) */ + #define R_GMAC_LPI_Control_Status_PLS_Msk (0x20000UL) /*!< PLS (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_LPITXA_Pos (19UL) /*!< LPITXA (Bit 19) */ + #define R_GMAC_LPI_Control_Status_LPITXA_Msk (0x80000UL) /*!< LPITXA (Bitfield-Mask: 0x01) */ +/* ================================================== LPI_Timers_Control =================================================== */ + #define R_GMAC_LPI_Timers_Control_TWT_Pos (0UL) /*!< TWT (Bit 0) */ + #define R_GMAC_LPI_Timers_Control_TWT_Msk (0xffffUL) /*!< TWT (Bitfield-Mask: 0xffff) */ + #define R_GMAC_LPI_Timers_Control_LST_Pos (16UL) /*!< LST (Bit 16) */ + #define R_GMAC_LPI_Timers_Control_LST_Msk (0x3ff0000UL) /*!< LST (Bitfield-Mask: 0x3ff) */ +/* =================================================== Interrupt_Status ==================================================== */ + #define R_GMAC_Interrupt_Status_PMTIS_Pos (3UL) /*!< PMTIS (Bit 3) */ + #define R_GMAC_Interrupt_Status_PMTIS_Msk (0x8UL) /*!< PMTIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_MMCIS_Pos (4UL) /*!< MMCIS (Bit 4) */ + #define R_GMAC_Interrupt_Status_MMCIS_Msk (0x10UL) /*!< MMCIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_MMCRXIS_Pos (5UL) /*!< MMCRXIS (Bit 5) */ + #define R_GMAC_Interrupt_Status_MMCRXIS_Msk (0x20UL) /*!< MMCRXIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_MMCTXIS_Pos (6UL) /*!< MMCTXIS (Bit 6) */ + #define R_GMAC_Interrupt_Status_MMCTXIS_Msk (0x40UL) /*!< MMCTXIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_MMCRXIPIS_Pos (7UL) /*!< MMCRXIPIS (Bit 7) */ + #define R_GMAC_Interrupt_Status_MMCRXIPIS_Msk (0x80UL) /*!< MMCRXIPIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_TSIS_Pos (9UL) /*!< TSIS (Bit 9) */ + #define R_GMAC_Interrupt_Status_TSIS_Msk (0x200UL) /*!< TSIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_LPIIS_Pos (10UL) /*!< LPIIS (Bit 10) */ + #define R_GMAC_Interrupt_Status_LPIIS_Msk (0x400UL) /*!< LPIIS (Bitfield-Mask: 0x01) */ +/* ==================================================== Interrupt_Mask ===================================================== */ + #define R_GMAC_Interrupt_Mask_PMTIM_Pos (3UL) /*!< PMTIM (Bit 3) */ + #define R_GMAC_Interrupt_Mask_PMTIM_Msk (0x8UL) /*!< PMTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Mask_TSIM_Pos (9UL) /*!< TSIM (Bit 9) */ + #define R_GMAC_Interrupt_Mask_TSIM_Msk (0x200UL) /*!< TSIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Mask_LPIIM_Pos (10UL) /*!< LPIIM (Bit 10) */ + #define R_GMAC_Interrupt_Mask_LPIIM_Msk (0x400UL) /*!< LPIIM (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR0_H ========================================================= */ + #define R_GMAC_MAR0_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR0_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR0_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR0_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR0_L ========================================================= */ + #define R_GMAC_MAR0_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR0_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR1_H ========================================================= */ + #define R_GMAC_MAR1_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR1_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR1_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR1_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR1_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR1_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR1_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR1_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR2_H ========================================================= */ + #define R_GMAC_MAR2_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR2_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR2_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR2_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR2_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR2_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR2_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR2_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR3_H ========================================================= */ + #define R_GMAC_MAR3_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR3_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR3_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR3_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR3_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR3_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR3_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR3_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR4_H ========================================================= */ + #define R_GMAC_MAR4_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR4_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR4_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR4_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR4_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR4_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR4_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR4_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR5_H ========================================================= */ + #define R_GMAC_MAR5_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR5_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR5_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR5_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR5_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR5_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR5_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR5_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR6_H ========================================================= */ + #define R_GMAC_MAR6_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR6_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR6_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR6_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR6_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR6_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR6_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR6_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR7_H ========================================================= */ + #define R_GMAC_MAR7_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR7_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR7_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR7_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR7_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR7_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR7_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR7_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR8_H ========================================================= */ + #define R_GMAC_MAR8_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR8_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR8_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR8_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR8_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR8_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR8_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR8_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR9_H ========================================================= */ + #define R_GMAC_MAR9_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR9_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR9_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR9_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR9_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR9_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR9_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR9_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR10_H ======================================================== */ + #define R_GMAC_MAR10_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR10_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR10_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR10_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR10_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR10_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR10_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR10_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR11_H ======================================================== */ + #define R_GMAC_MAR11_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR11_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR11_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR11_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR11_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR11_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR11_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR11_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR12_H ======================================================== */ + #define R_GMAC_MAR12_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR12_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR12_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR12_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR12_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR12_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR12_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR12_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR13_H ======================================================== */ + #define R_GMAC_MAR13_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR13_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR13_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR13_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR13_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR13_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR13_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR13_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR14_H ======================================================== */ + #define R_GMAC_MAR14_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR14_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR14_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR14_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR14_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR14_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR14_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR14_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR15_H ======================================================== */ + #define R_GMAC_MAR15_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR15_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR15_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR15_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR15_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR15_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR15_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR15_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR1_L ========================================================= */ + #define R_GMAC_MAR1_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR1_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR2_L ========================================================= */ + #define R_GMAC_MAR2_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR2_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR3_L ========================================================= */ + #define R_GMAC_MAR3_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR3_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR4_L ========================================================= */ + #define R_GMAC_MAR4_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR4_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR5_L ========================================================= */ + #define R_GMAC_MAR5_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR5_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR6_L ========================================================= */ + #define R_GMAC_MAR6_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR6_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR7_L ========================================================= */ + #define R_GMAC_MAR7_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR7_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR8_L ========================================================= */ + #define R_GMAC_MAR8_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR8_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR9_L ========================================================= */ + #define R_GMAC_MAR9_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR9_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR10_L ======================================================== */ + #define R_GMAC_MAR10_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR10_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR11_L ======================================================== */ + #define R_GMAC_MAR11_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR11_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR12_L ======================================================== */ + #define R_GMAC_MAR12_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR12_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR13_L ======================================================== */ + #define R_GMAC_MAR13_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR13_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR14_L ======================================================== */ + #define R_GMAC_MAR14_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR14_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR15_L ======================================================== */ + #define R_GMAC_MAR15_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR15_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== WDog_Timeout ====================================================== */ + #define R_GMAC_WDog_Timeout_WTO_Pos (0UL) /*!< WTO (Bit 0) */ + #define R_GMAC_WDog_Timeout_WTO_Msk (0x3fffUL) /*!< WTO (Bitfield-Mask: 0x3fff) */ + #define R_GMAC_WDog_Timeout_PWE_Pos (16UL) /*!< PWE (Bit 16) */ + #define R_GMAC_WDog_Timeout_PWE_Msk (0x10000UL) /*!< PWE (Bitfield-Mask: 0x01) */ +/* ====================================================== MMC_Control ====================================================== */ + #define R_GMAC_MMC_Control_CNTRST_Pos (0UL) /*!< CNTRST (Bit 0) */ + #define R_GMAC_MMC_Control_CNTRST_Msk (0x1UL) /*!< CNTRST (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_CNTSTOPRO_Pos (1UL) /*!< CNTSTOPRO (Bit 1) */ + #define R_GMAC_MMC_Control_CNTSTOPRO_Msk (0x2UL) /*!< CNTSTOPRO (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_RSTONRD_Pos (2UL) /*!< RSTONRD (Bit 2) */ + #define R_GMAC_MMC_Control_RSTONRD_Msk (0x4UL) /*!< RSTONRD (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_CNTFREEZ_Pos (3UL) /*!< CNTFREEZ (Bit 3) */ + #define R_GMAC_MMC_Control_CNTFREEZ_Msk (0x8UL) /*!< CNTFREEZ (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_CNTPRST_Pos (4UL) /*!< CNTPRST (Bit 4) */ + #define R_GMAC_MMC_Control_CNTPRST_Msk (0x10UL) /*!< CNTPRST (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_CNTPRSTLVL_Pos (5UL) /*!< CNTPRSTLVL (Bit 5) */ + #define R_GMAC_MMC_Control_CNTPRSTLVL_Msk (0x20UL) /*!< CNTPRSTLVL (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_UCDBC_Pos (8UL) /*!< UCDBC (Bit 8) */ + #define R_GMAC_MMC_Control_UCDBC_Msk (0x100UL) /*!< UCDBC (Bitfield-Mask: 0x01) */ +/* ================================================= MMC_Receive_Interrupt ================================================= */ + #define R_GMAC_MMC_Receive_Interrupt_RXGBFRMIS_Pos (0UL) /*!< RXGBFRMIS (Bit 0) */ + #define R_GMAC_MMC_Receive_Interrupt_RXGBFRMIS_Msk (0x1UL) /*!< RXGBFRMIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXGBOCTIS_Pos (1UL) /*!< RXGBOCTIS (Bit 1) */ + #define R_GMAC_MMC_Receive_Interrupt_RXGBOCTIS_Msk (0x2UL) /*!< RXGBOCTIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXGOCTIS_Pos (2UL) /*!< RXGOCTIS (Bit 2) */ + #define R_GMAC_MMC_Receive_Interrupt_RXGOCTIS_Msk (0x4UL) /*!< RXGOCTIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXBCGFIS_Pos (3UL) /*!< RXBCGFIS (Bit 3) */ + #define R_GMAC_MMC_Receive_Interrupt_RXBCGFIS_Msk (0x8UL) /*!< RXBCGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXMCGFIS_Pos (4UL) /*!< RXMCGFIS (Bit 4) */ + #define R_GMAC_MMC_Receive_Interrupt_RXMCGFIS_Msk (0x10UL) /*!< RXMCGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXCRCERFIS_Pos (5UL) /*!< RXCRCERFIS (Bit 5) */ + #define R_GMAC_MMC_Receive_Interrupt_RXCRCERFIS_Msk (0x20UL) /*!< RXCRCERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXALGNERFIS_Pos (6UL) /*!< RXALGNERFIS (Bit 6) */ + #define R_GMAC_MMC_Receive_Interrupt_RXALGNERFIS_Msk (0x40UL) /*!< RXALGNERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXRUNTFIS_Pos (7UL) /*!< RXRUNTFIS (Bit 7) */ + #define R_GMAC_MMC_Receive_Interrupt_RXRUNTFIS_Msk (0x80UL) /*!< RXRUNTFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXJABERFIS_Pos (8UL) /*!< RXJABERFIS (Bit 8) */ + #define R_GMAC_MMC_Receive_Interrupt_RXJABERFIS_Msk (0x100UL) /*!< RXJABERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXUSIZEGFIS_Pos (9UL) /*!< RXUSIZEGFIS (Bit 9) */ + #define R_GMAC_MMC_Receive_Interrupt_RXUSIZEGFIS_Msk (0x200UL) /*!< RXUSIZEGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXOSIZEGFIS_Pos (10UL) /*!< RXOSIZEGFIS (Bit 10) */ + #define R_GMAC_MMC_Receive_Interrupt_RXOSIZEGFIS_Msk (0x400UL) /*!< RXOSIZEGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX64OCTGBFIS_Pos (11UL) /*!< RX64OCTGBFIS (Bit 11) */ + #define R_GMAC_MMC_Receive_Interrupt_RX64OCTGBFIS_Msk (0x800UL) /*!< RX64OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX65T127OCTGBFIS_Pos (12UL) /*!< RX65T127OCTGBFIS (Bit 12) */ + #define R_GMAC_MMC_Receive_Interrupt_RX65T127OCTGBFIS_Msk (0x1000UL) /*!< RX65T127OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX128T255OCTGBFIS_Pos (13UL) /*!< RX128T255OCTGBFIS (Bit 13) */ + #define R_GMAC_MMC_Receive_Interrupt_RX128T255OCTGBFIS_Msk (0x2000UL) /*!< RX128T255OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX256T511OCTGBFIS_Pos (14UL) /*!< RX256T511OCTGBFIS (Bit 14) */ + #define R_GMAC_MMC_Receive_Interrupt_RX256T511OCTGBFIS_Msk (0x4000UL) /*!< RX256T511OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX512T1023OCTGBFIS_Pos (15UL) /*!< RX512T1023OCTGBFIS (Bit 15) */ + #define R_GMAC_MMC_Receive_Interrupt_RX512T1023OCTGBFIS_Msk (0x8000UL) /*!< RX512T1023OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX1024TMAXOCTGBFIS_Pos (16UL) /*!< RX1024TMAXOCTGBFIS (Bit 16) */ + #define R_GMAC_MMC_Receive_Interrupt_RX1024TMAXOCTGBFIS_Msk (0x10000UL) /*!< RX1024TMAXOCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXUCGFIS_Pos (17UL) /*!< RXUCGFIS (Bit 17) */ + #define R_GMAC_MMC_Receive_Interrupt_RXUCGFIS_Msk (0x20000UL) /*!< RXUCGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXLENERFIS_Pos (18UL) /*!< RXLENERFIS (Bit 18) */ + #define R_GMAC_MMC_Receive_Interrupt_RXLENERFIS_Msk (0x40000UL) /*!< RXLENERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXORANGEFIS_Pos (19UL) /*!< RXORANGEFIS (Bit 19) */ + #define R_GMAC_MMC_Receive_Interrupt_RXORANGEFIS_Msk (0x80000UL) /*!< RXORANGEFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXPAUSFIS_Pos (20UL) /*!< RXPAUSFIS (Bit 20) */ + #define R_GMAC_MMC_Receive_Interrupt_RXPAUSFIS_Msk (0x100000UL) /*!< RXPAUSFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXFOVFIS_Pos (21UL) /*!< RXFOVFIS (Bit 21) */ + #define R_GMAC_MMC_Receive_Interrupt_RXFOVFIS_Msk (0x200000UL) /*!< RXFOVFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXVLANGBFIS_Pos (22UL) /*!< RXVLANGBFIS (Bit 22) */ + #define R_GMAC_MMC_Receive_Interrupt_RXVLANGBFIS_Msk (0x400000UL) /*!< RXVLANGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXWDOGFIS_Pos (23UL) /*!< RXWDOGFIS (Bit 23) */ + #define R_GMAC_MMC_Receive_Interrupt_RXWDOGFIS_Msk (0x800000UL) /*!< RXWDOGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXRCVERRFIS_Pos (24UL) /*!< RXRCVERRFIS (Bit 24) */ + #define R_GMAC_MMC_Receive_Interrupt_RXRCVERRFIS_Msk (0x1000000UL) /*!< RXRCVERRFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXCTRLFIS_Pos (25UL) /*!< RXCTRLFIS (Bit 25) */ + #define R_GMAC_MMC_Receive_Interrupt_RXCTRLFIS_Msk (0x2000000UL) /*!< RXCTRLFIS (Bitfield-Mask: 0x01) */ +/* ================================================ MMC_Transmit_Interrupt ================================================= */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGBOCTIS_Pos (0UL) /*!< TXGBOCTIS (Bit 0) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGBOCTIS_Msk (0x1UL) /*!< TXGBOCTIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGBFRMIS_Pos (1UL) /*!< TXGBFRMIS (Bit 1) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGBFRMIS_Msk (0x2UL) /*!< TXGBFRMIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXBCGFIS_Pos (2UL) /*!< TXBCGFIS (Bit 2) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXBCGFIS_Msk (0x4UL) /*!< TXBCGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCGFIS_Pos (3UL) /*!< TXMCGFIS (Bit 3) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCGFIS_Msk (0x8UL) /*!< TXMCGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX64OCTGBFIS_Pos (4UL) /*!< TX64OCTGBFIS (Bit 4) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX64OCTGBFIS_Msk (0x10UL) /*!< TX64OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX65T127OCTGBFIS_Pos (5UL) /*!< TX65T127OCTGBFIS (Bit 5) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX65T127OCTGBFIS_Msk (0x20UL) /*!< TX65T127OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX128T255OCTGBFIS_Pos (6UL) /*!< TX128T255OCTGBFIS (Bit 6) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX128T255OCTGBFIS_Msk (0x40UL) /*!< TX128T255OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX256T511OCTGBFIS_Pos (7UL) /*!< TX256T511OCTGBFIS (Bit 7) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX256T511OCTGBFIS_Msk (0x80UL) /*!< TX256T511OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX512T1023OCTGBFIS_Pos (8UL) /*!< TX512T1023OCTGBFIS (Bit 8) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX512T1023OCTGBFIS_Msk (0x100UL) /*!< TX512T1023OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX1024TMAXOCTGBFIS_Pos (9UL) /*!< TX1024TMAXOCTGBFIS (Bit 9) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX1024TMAXOCTGBFIS_Msk (0x200UL) /*!< TX1024TMAXOCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXUCGBFIS_Pos (10UL) /*!< TXUCGBFIS (Bit 10) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXUCGBFIS_Msk (0x400UL) /*!< TXUCGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCGBFIS_Pos (11UL) /*!< TXMCGBFIS (Bit 11) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCGBFIS_Msk (0x800UL) /*!< TXMCGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXBCGBFIS_Pos (12UL) /*!< TXBCGBFIS (Bit 12) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXBCGBFIS_Msk (0x1000UL) /*!< TXBCGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXUFLOWERFIS_Pos (13UL) /*!< TXUFLOWERFIS (Bit 13) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXUFLOWERFIS_Msk (0x2000UL) /*!< TXUFLOWERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXSCOLGFIS_Pos (14UL) /*!< TXSCOLGFIS (Bit 14) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXSCOLGFIS_Msk (0x4000UL) /*!< TXSCOLGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCOLGFIS_Pos (15UL) /*!< TXMCOLGFIS (Bit 15) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCOLGFIS_Msk (0x8000UL) /*!< TXMCOLGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXDEFFIS_Pos (16UL) /*!< TXDEFFIS (Bit 16) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXDEFFIS_Msk (0x10000UL) /*!< TXDEFFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXLATCOLFIS_Pos (17UL) /*!< TXLATCOLFIS (Bit 17) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXLATCOLFIS_Msk (0x20000UL) /*!< TXLATCOLFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXEXCOLFIS_Pos (18UL) /*!< TXEXCOLFIS (Bit 18) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXEXCOLFIS_Msk (0x40000UL) /*!< TXEXCOLFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXCARERFIS_Pos (19UL) /*!< TXCARERFIS (Bit 19) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXCARERFIS_Msk (0x80000UL) /*!< TXCARERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGOCTIS_Pos (20UL) /*!< TXGOCTIS (Bit 20) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGOCTIS_Msk (0x100000UL) /*!< TXGOCTIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGFRMIS_Pos (21UL) /*!< TXGFRMIS (Bit 21) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGFRMIS_Msk (0x200000UL) /*!< TXGFRMIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXEXDEFFIS_Pos (22UL) /*!< TXEXDEFFIS (Bit 22) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXEXDEFFIS_Msk (0x400000UL) /*!< TXEXDEFFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXPAUSFIS_Pos (23UL) /*!< TXPAUSFIS (Bit 23) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXPAUSFIS_Msk (0x800000UL) /*!< TXPAUSFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXVLANGFIS_Pos (24UL) /*!< TXVLANGFIS (Bit 24) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXVLANGFIS_Msk (0x1000000UL) /*!< TXVLANGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXOSIZEGFIS_Pos (25UL) /*!< TXOSIZEGFIS (Bit 25) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXOSIZEGFIS_Msk (0x2000000UL) /*!< TXOSIZEGFIS (Bitfield-Mask: 0x01) */ +/* ============================================== MMC_Receive_Interrupt_Mask =============================================== */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBFRMIM_Pos (0UL) /*!< RXGBFRMIM (Bit 0) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBFRMIM_Msk (0x1UL) /*!< RXGBFRMIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBOCTIM_Pos (1UL) /*!< RXGBOCTIM (Bit 1) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBOCTIM_Msk (0x2UL) /*!< RXGBOCTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGOCTIM_Pos (2UL) /*!< RXGOCTIM (Bit 2) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGOCTIM_Msk (0x4UL) /*!< RXGOCTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXBCGFIM_Pos (3UL) /*!< RXBCGFIM (Bit 3) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXBCGFIM_Msk (0x8UL) /*!< RXBCGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXMCGFIM_Pos (4UL) /*!< RXMCGFIM (Bit 4) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXMCGFIM_Msk (0x10UL) /*!< RXMCGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCRCERFIM_Pos (5UL) /*!< RXCRCERFIM (Bit 5) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCRCERFIM_Msk (0x20UL) /*!< RXCRCERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXALGNERFIM_Pos (6UL) /*!< RXALGNERFIM (Bit 6) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXALGNERFIM_Msk (0x40UL) /*!< RXALGNERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRUNTFIM_Pos (7UL) /*!< RXRUNTFIM (Bit 7) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRUNTFIM_Msk (0x80UL) /*!< RXRUNTFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXJABERFIM_Pos (8UL) /*!< RXJABERFIM (Bit 8) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXJABERFIM_Msk (0x100UL) /*!< RXJABERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUSIZEGFIM_Pos (9UL) /*!< RXUSIZEGFIM (Bit 9) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUSIZEGFIM_Msk (0x200UL) /*!< RXUSIZEGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXOSIZEGFIM_Pos (10UL) /*!< RXOSIZEGFIM (Bit 10) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXOSIZEGFIM_Msk (0x400UL) /*!< RXOSIZEGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX64OCTGBFIM_Pos (11UL) /*!< RX64OCTGBFIM (Bit 11) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX64OCTGBFIM_Msk (0x800UL) /*!< RX64OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX65T127OCTGBFIM_Pos (12UL) /*!< RX65T127OCTGBFIM (Bit 12) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX65T127OCTGBFIM_Msk (0x1000UL) /*!< RX65T127OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX128T255OCTGBFIM_Pos (13UL) /*!< RX128T255OCTGBFIM (Bit 13) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX128T255OCTGBFIM_Msk (0x2000UL) /*!< RX128T255OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX256T511OCTGBFIM_Pos (14UL) /*!< RX256T511OCTGBFIM (Bit 14) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX256T511OCTGBFIM_Msk (0x4000UL) /*!< RX256T511OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX512T1023OCTGBFIM_Pos (15UL) /*!< RX512T1023OCTGBFIM (Bit 15) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX512T1023OCTGBFIM_Msk (0x8000UL) /*!< RX512T1023OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX1024TMAXOCTGBFIM_Pos (16UL) /*!< RX1024TMAXOCTGBFIM (Bit 16) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX1024TMAXOCTGBFIM_Msk (0x10000UL) /*!< RX1024TMAXOCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUCGFIM_Pos (17UL) /*!< RXUCGFIM (Bit 17) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUCGFIM_Msk (0x20000UL) /*!< RXUCGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXLENERFIM_Pos (18UL) /*!< RXLENERFIM (Bit 18) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXLENERFIM_Msk (0x40000UL) /*!< RXLENERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXORANGEFIM_Pos (19UL) /*!< RXORANGEFIM (Bit 19) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXORANGEFIM_Msk (0x80000UL) /*!< RXORANGEFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXPAUSFIM_Pos (20UL) /*!< RXPAUSFIM (Bit 20) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXPAUSFIM_Msk (0x100000UL) /*!< RXPAUSFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXFOVFIM_Pos (21UL) /*!< RXFOVFIM (Bit 21) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXFOVFIM_Msk (0x200000UL) /*!< RXFOVFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXVLANGBFIM_Pos (22UL) /*!< RXVLANGBFIM (Bit 22) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXVLANGBFIM_Msk (0x400000UL) /*!< RXVLANGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXWDOGFIM_Pos (23UL) /*!< RXWDOGFIM (Bit 23) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXWDOGFIM_Msk (0x800000UL) /*!< RXWDOGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRCVERRFIM_Pos (24UL) /*!< RXRCVERRFIM (Bit 24) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRCVERRFIM_Msk (0x1000000UL) /*!< RXRCVERRFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCTRLFIM_Pos (25UL) /*!< RXCTRLFIM (Bit 25) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCTRLFIM_Msk (0x2000000UL) /*!< RXCTRLFIM (Bitfield-Mask: 0x01) */ +/* ============================================== MMC_Transmit_Interrupt_Mask ============================================== */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBOCTIM_Pos (0UL) /*!< TXGBOCTIM (Bit 0) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBOCTIM_Msk (0x1UL) /*!< TXGBOCTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBFRMIM_Pos (1UL) /*!< TXGBFRMIM (Bit 1) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBFRMIM_Msk (0x2UL) /*!< TXGBFRMIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGFIM_Pos (2UL) /*!< TXBCGFIM (Bit 2) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGFIM_Msk (0x4UL) /*!< TXBCGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGFIM_Pos (3UL) /*!< TXMCGFIM (Bit 3) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGFIM_Msk (0x8UL) /*!< TXMCGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX64OCTGBFIM_Pos (4UL) /*!< TX64OCTGBFIM (Bit 4) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX64OCTGBFIM_Msk (0x10UL) /*!< TX64OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX65T127OCTGBFIM_Pos (5UL) /*!< TX65T127OCTGBFIM (Bit 5) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX65T127OCTGBFIM_Msk (0x20UL) /*!< TX65T127OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX128T255OCTGBFIM_Pos (6UL) /*!< TX128T255OCTGBFIM (Bit 6) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX128T255OCTGBFIM_Msk (0x40UL) /*!< TX128T255OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX256T511OCTGBFIM_Pos (7UL) /*!< TX256T511OCTGBFIM (Bit 7) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX256T511OCTGBFIM_Msk (0x80UL) /*!< TX256T511OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX512T1023OCTGBFIM_Pos (8UL) /*!< TX512T1023OCTGBFIM (Bit 8) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX512T1023OCTGBFIM_Msk (0x100UL) /*!< TX512T1023OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX1024TMAXOCTGBFIM_Pos (9UL) /*!< TX1024TMAXOCTGBFIM (Bit 9) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX1024TMAXOCTGBFIM_Msk (0x200UL) /*!< TX1024TMAXOCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUCGBFIM_Pos (10UL) /*!< TXUCGBFIM (Bit 10) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUCGBFIM_Msk (0x400UL) /*!< TXUCGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGBFIM_Pos (11UL) /*!< TXMCGBFIM (Bit 11) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGBFIM_Msk (0x800UL) /*!< TXMCGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGBFIM_Pos (12UL) /*!< TXBCGBFIM (Bit 12) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGBFIM_Msk (0x1000UL) /*!< TXBCGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUFLOWERFIM_Pos (13UL) /*!< TXUFLOWERFIM (Bit 13) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUFLOWERFIM_Msk (0x2000UL) /*!< TXUFLOWERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXSCOLGFIM_Pos (14UL) /*!< TXSCOLGFIM (Bit 14) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXSCOLGFIM_Msk (0x4000UL) /*!< TXSCOLGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCOLGFIM_Pos (15UL) /*!< TXMCOLGFIM (Bit 15) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCOLGFIM_Msk (0x8000UL) /*!< TXMCOLGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXDEFFIM_Pos (16UL) /*!< TXDEFFIM (Bit 16) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXDEFFIM_Msk (0x10000UL) /*!< TXDEFFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXLATCOLFIM_Pos (17UL) /*!< TXLATCOLFIM (Bit 17) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXLATCOLFIM_Msk (0x20000UL) /*!< TXLATCOLFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXCOLFIM_Pos (18UL) /*!< TXEXCOLFIM (Bit 18) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXCOLFIM_Msk (0x40000UL) /*!< TXEXCOLFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXCARERFIM_Pos (19UL) /*!< TXCARERFIM (Bit 19) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXCARERFIM_Msk (0x80000UL) /*!< TXCARERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGOCTIM_Pos (20UL) /*!< TXGOCTIM (Bit 20) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGOCTIM_Msk (0x100000UL) /*!< TXGOCTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGFRMIM_Pos (21UL) /*!< TXGFRMIM (Bit 21) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGFRMIM_Msk (0x200000UL) /*!< TXGFRMIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXDEFFIM_Pos (22UL) /*!< TXEXDEFFIM (Bit 22) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXDEFFIM_Msk (0x400000UL) /*!< TXEXDEFFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXPAUSFIM_Pos (23UL) /*!< TXPAUSFIM (Bit 23) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXPAUSFIM_Msk (0x800000UL) /*!< TXPAUSFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXVLANGFIM_Pos (24UL) /*!< TXVLANGFIM (Bit 24) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXVLANGFIM_Msk (0x1000000UL) /*!< TXVLANGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXOSIZEGFIM_Pos (25UL) /*!< TXOSIZEGFIM (Bit 25) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXOSIZEGFIM_Msk (0x2000000UL) /*!< TXOSIZEGFIM (Bitfield-Mask: 0x01) */ +/* ================================================ Tx_Octet_Count_Good_Bad ================================================ */ + #define R_GMAC_Tx_Octet_Count_Good_Bad_TXOCTGB_Pos (0UL) /*!< TXOCTGB (Bit 0) */ + #define R_GMAC_Tx_Octet_Count_Good_Bad_TXOCTGB_Msk (0xffffffffUL) /*!< TXOCTGB (Bitfield-Mask: 0xffffffff) */ +/* ================================================ Tx_Frame_Count_Good_Bad ================================================ */ + #define R_GMAC_Tx_Frame_Count_Good_Bad_TXFRMGB_Pos (0UL) /*!< TXFRMGB (Bit 0) */ + #define R_GMAC_Tx_Frame_Count_Good_Bad_TXFRMGB_Msk (0xffffffffUL) /*!< TXFRMGB (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Tx_Broadcast_Frames_Good ================================================ */ + #define R_GMAC_Tx_Broadcast_Frames_Good_TXBCASTG_Pos (0UL) /*!< TXBCASTG (Bit 0) */ + #define R_GMAC_Tx_Broadcast_Frames_Good_TXBCASTG_Msk (0xffffffffUL) /*!< TXBCASTG (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Tx_Multicast_Frames_Good ================================================ */ + #define R_GMAC_Tx_Multicast_Frames_Good_TXMCASTG_Pos (0UL) /*!< TXMCASTG (Bit 0) */ + #define R_GMAC_Tx_Multicast_Frames_Good_TXMCASTG_Msk (0xffffffffUL) /*!< TXMCASTG (Bitfield-Mask: 0xffffffff) */ +/* ============================================== Tx_64Octets_Frames_Good_Bad ============================================== */ + #define R_GMAC_Tx_64Octets_Frames_Good_Bad_TX64OCTGB_Pos (0UL) /*!< TX64OCTGB (Bit 0) */ + #define R_GMAC_Tx_64Octets_Frames_Good_Bad_TX64OCTGB_Msk (0xffffffffUL) /*!< TX64OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Tx_65To127Octets_Frames_Good_Bad ============================================ */ + #define R_GMAC_Tx_65To127Octets_Frames_Good_Bad_TX65_127OCTGB_Pos (0UL) /*!< TX65_127OCTGB (Bit 0) */ + #define R_GMAC_Tx_65To127Octets_Frames_Good_Bad_TX65_127OCTGB_Msk (0xffffffffUL) /*!< TX65_127OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Tx_128To255Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Tx_128To255Octets_Frames_Good_Bad_TX128_255OCTGB_Pos (0UL) /*!< TX128_255OCTGB (Bit 0) */ + #define R_GMAC_Tx_128To255Octets_Frames_Good_Bad_TX128_255OCTGB_Msk (0xffffffffUL) /*!< TX128_255OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Tx_256To511Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Tx_256To511Octets_Frames_Good_Bad_TX256_511OCTGB_Pos (0UL) /*!< TX256_511OCTGB (Bit 0) */ + #define R_GMAC_Tx_256To511Octets_Frames_Good_Bad_TX256_511OCTGB_Msk (0xffffffffUL) /*!< TX256_511OCTGB (Bitfield-Mask: 0xffffffff) */ +/* ========================================== Tx_512To1023Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Tx_512To1023Octets_Frames_Good_Bad_TX512_1023OCTGB_Pos (0UL) /*!< TX512_1023OCTGB (Bit 0) */ + #define R_GMAC_Tx_512To1023Octets_Frames_Good_Bad_TX512_1023OCTGB_Msk (0xffffffffUL) /*!< TX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */ +/* ========================================== Tx_1024ToMaxOctets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Tx_1024ToMaxOctets_Frames_Good_Bad_TX1024_MAXOCTGB_Pos (0UL) /*!< TX1024_MAXOCTGB (Bit 0) */ + #define R_GMAC_Tx_1024ToMaxOctets_Frames_Good_Bad_TX1024_MAXOCTGB_Msk (0xffffffffUL) /*!< TX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */ +/* ============================================== Tx_Unicast_Frames_Good_Bad =============================================== */ + #define R_GMAC_Tx_Unicast_Frames_Good_Bad_TXUCASTGB_Pos (0UL) /*!< TXUCASTGB (Bit 0) */ + #define R_GMAC_Tx_Unicast_Frames_Good_Bad_TXUCASTGB_Msk (0xffffffffUL) /*!< TXUCASTGB (Bitfield-Mask: 0xffffffff) */ +/* ============================================= Tx_Multicast_Frames_Good_Bad ============================================== */ + #define R_GMAC_Tx_Multicast_Frames_Good_Bad_TXMCASTGB_Pos (0UL) /*!< TXMCASTGB (Bit 0) */ + #define R_GMAC_Tx_Multicast_Frames_Good_Bad_TXMCASTGB_Msk (0xffffffffUL) /*!< TXMCASTGB (Bitfield-Mask: 0xffffffff) */ +/* ============================================= Tx_Broadcast_Frames_Good_Bad ============================================== */ + #define R_GMAC_Tx_Broadcast_Frames_Good_Bad_TXBCASTGB_Pos (0UL) /*!< TXBCASTGB (Bit 0) */ + #define R_GMAC_Tx_Broadcast_Frames_Good_Bad_TXBCASTGB_Msk (0xffffffffUL) /*!< TXBCASTGB (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Tx_Underflow_Error_Frames =============================================== */ + #define R_GMAC_Tx_Underflow_Error_Frames_TXUNDRFLW_Pos (0UL) /*!< TXUNDRFLW (Bit 0) */ + #define R_GMAC_Tx_Underflow_Error_Frames_TXUNDRFLW_Msk (0xffffUL) /*!< TXUNDRFLW (Bitfield-Mask: 0xffff) */ +/* ============================================ Tx_Single_Collision_Good_Frames ============================================ */ + #define R_GMAC_Tx_Single_Collision_Good_Frames_TXSNGLCOLG_Pos (0UL) /*!< TXSNGLCOLG (Bit 0) */ + #define R_GMAC_Tx_Single_Collision_Good_Frames_TXSNGLCOLG_Msk (0xffffUL) /*!< TXSNGLCOLG (Bitfield-Mask: 0xffff) */ +/* =========================================== Tx_Multiple_Collision_Good_Frames =========================================== */ + #define R_GMAC_Tx_Multiple_Collision_Good_Frames_TXMULTCOLG_Pos (0UL) /*!< TXMULTCOLG (Bit 0) */ + #define R_GMAC_Tx_Multiple_Collision_Good_Frames_TXMULTCOLG_Msk (0xffffUL) /*!< TXMULTCOLG (Bitfield-Mask: 0xffff) */ +/* ================================================== Tx_Deferred_Frames =================================================== */ + #define R_GMAC_Tx_Deferred_Frames_TXDEFRD_Pos (0UL) /*!< TXDEFRD (Bit 0) */ + #define R_GMAC_Tx_Deferred_Frames_TXDEFRD_Msk (0xffffUL) /*!< TXDEFRD (Bitfield-Mask: 0xffff) */ +/* =============================================== Tx_Late_Collision_Frames ================================================ */ + #define R_GMAC_Tx_Late_Collision_Frames_TXLATECOL_Pos (0UL) /*!< TXLATECOL (Bit 0) */ + #define R_GMAC_Tx_Late_Collision_Frames_TXLATECOL_Msk (0xffffUL) /*!< TXLATECOL (Bitfield-Mask: 0xffff) */ +/* ============================================= Tx_Excessive_Collision_Frames ============================================= */ + #define R_GMAC_Tx_Excessive_Collision_Frames_TXEXSCOL_Pos (0UL) /*!< TXEXSCOL (Bit 0) */ + #define R_GMAC_Tx_Excessive_Collision_Frames_TXEXSCOL_Msk (0xffffUL) /*!< TXEXSCOL (Bitfield-Mask: 0xffff) */ +/* ================================================ Tx_Carrier_Error_Frames ================================================ */ + #define R_GMAC_Tx_Carrier_Error_Frames_TXCARR_Pos (0UL) /*!< TXCARR (Bit 0) */ + #define R_GMAC_Tx_Carrier_Error_Frames_TXCARR_Msk (0xffffUL) /*!< TXCARR (Bitfield-Mask: 0xffff) */ +/* ================================================== Tx_Octet_Count_Good ================================================== */ + #define R_GMAC_Tx_Octet_Count_Good_TXOCTG_Pos (0UL) /*!< TXOCTG (Bit 0) */ + #define R_GMAC_Tx_Octet_Count_Good_TXOCTG_Msk (0xffffffffUL) /*!< TXOCTG (Bitfield-Mask: 0xffffffff) */ +/* ================================================== Tx_Frame_Count_Good ================================================== */ + #define R_GMAC_Tx_Frame_Count_Good_TXFRMG_Pos (0UL) /*!< TXFRMG (Bit 0) */ + #define R_GMAC_Tx_Frame_Count_Good_TXFRMG_Msk (0xffffffffUL) /*!< TXFRMG (Bitfield-Mask: 0xffffffff) */ +/* ============================================== Tx_Excessive_Deferral_Error ============================================== */ + #define R_GMAC_Tx_Excessive_Deferral_Error_TXEXSDEF_Pos (0UL) /*!< TXEXSDEF (Bit 0) */ + #define R_GMAC_Tx_Excessive_Deferral_Error_TXEXSDEF_Msk (0xffffUL) /*!< TXEXSDEF (Bitfield-Mask: 0xffff) */ +/* ==================================================== Tx_Pause_Frames ==================================================== */ + #define R_GMAC_Tx_Pause_Frames_TXPAUSE_Pos (0UL) /*!< TXPAUSE (Bit 0) */ + #define R_GMAC_Tx_Pause_Frames_TXPAUSE_Msk (0xffffUL) /*!< TXPAUSE (Bitfield-Mask: 0xffff) */ +/* ================================================== Tx_VLAN_Frames_Good ================================================== */ + #define R_GMAC_Tx_VLAN_Frames_Good_TXVLANG_Pos (0UL) /*!< TXVLANG (Bit 0) */ + #define R_GMAC_Tx_VLAN_Frames_Good_TXVLANG_Msk (0xffffffffUL) /*!< TXVLANG (Bitfield-Mask: 0xffffffff) */ +/* ================================================= Tx_OSize_Frames_Good ================================================== */ + #define R_GMAC_Tx_OSize_Frames_Good_TXOSIZG_Pos (0UL) /*!< TXOSIZG (Bit 0) */ + #define R_GMAC_Tx_OSize_Frames_Good_TXOSIZG_Msk (0xffffUL) /*!< TXOSIZG (Bitfield-Mask: 0xffff) */ +/* =============================================== Rx_Frames_Count_Good_Bad ================================================ */ + #define R_GMAC_Rx_Frames_Count_Good_Bad_RXFRMGB_Pos (0UL) /*!< RXFRMGB (Bit 0) */ + #define R_GMAC_Rx_Frames_Count_Good_Bad_RXFRMGB_Msk (0xffffffffUL) /*!< RXFRMGB (Bitfield-Mask: 0xffffffff) */ +/* ================================================ Rx_Octet_Count_Good_Bad ================================================ */ + #define R_GMAC_Rx_Octet_Count_Good_Bad_RXOCTGB_Pos (0UL) /*!< RXOCTGB (Bit 0) */ + #define R_GMAC_Rx_Octet_Count_Good_Bad_RXOCTGB_Msk (0xffffffffUL) /*!< RXOCTGB (Bitfield-Mask: 0xffffffff) */ +/* ================================================== Rx_Octet_Count_Good ================================================== */ + #define R_GMAC_Rx_Octet_Count_Good_RXOCTG_Pos (0UL) /*!< RXOCTG (Bit 0) */ + #define R_GMAC_Rx_Octet_Count_Good_RXOCTG_Msk (0xffffffffUL) /*!< RXOCTG (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Rx_Broadcast_Frames_Good ================================================ */ + #define R_GMAC_Rx_Broadcast_Frames_Good_RXBCASTG_Pos (0UL) /*!< RXBCASTG (Bit 0) */ + #define R_GMAC_Rx_Broadcast_Frames_Good_RXBCASTG_Msk (0xffffffffUL) /*!< RXBCASTG (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Rx_Multicast_Frames_Good ================================================ */ + #define R_GMAC_Rx_Multicast_Frames_Good_RXMCASTG_Pos (0UL) /*!< RXMCASTG (Bit 0) */ + #define R_GMAC_Rx_Multicast_Frames_Good_RXMCASTG_Msk (0xffffffffUL) /*!< RXMCASTG (Bitfield-Mask: 0xffffffff) */ +/* ================================================== Rx_CRC_Error_Frames ================================================== */ + #define R_GMAC_Rx_CRC_Error_Frames_RXCRCERR_Pos (0UL) /*!< RXCRCERR (Bit 0) */ + #define R_GMAC_Rx_CRC_Error_Frames_RXCRCERR_Msk (0xffffUL) /*!< RXCRCERR (Bitfield-Mask: 0xffff) */ +/* =============================================== Rx_Alignment_Error_Frames =============================================== */ + #define R_GMAC_Rx_Alignment_Error_Frames_RXALGNERR_Pos (0UL) /*!< RXALGNERR (Bit 0) */ + #define R_GMAC_Rx_Alignment_Error_Frames_RXALGNERR_Msk (0xffffUL) /*!< RXALGNERR (Bitfield-Mask: 0xffff) */ +/* ================================================= Rx_Runt_Error_Frames ================================================== */ + #define R_GMAC_Rx_Runt_Error_Frames_RXRUNTERR_Pos (0UL) /*!< RXRUNTERR (Bit 0) */ + #define R_GMAC_Rx_Runt_Error_Frames_RXRUNTERR_Msk (0xffffUL) /*!< RXRUNTERR (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_Jabber_Error_Frames ================================================= */ + #define R_GMAC_Rx_Jabber_Error_Frames_RXJABERR_Pos (0UL) /*!< RXJABERR (Bit 0) */ + #define R_GMAC_Rx_Jabber_Error_Frames_RXJABERR_Msk (0xffffUL) /*!< RXJABERR (Bitfield-Mask: 0xffff) */ +/* =============================================== Rx_Undersize_Frames_Good ================================================ */ + #define R_GMAC_Rx_Undersize_Frames_Good_RXUNDERSZG_Pos (0UL) /*!< RXUNDERSZG (Bit 0) */ + #define R_GMAC_Rx_Undersize_Frames_Good_RXUNDERSZG_Msk (0xffffUL) /*!< RXUNDERSZG (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_Oversize_Frames_Good ================================================ */ + #define R_GMAC_Rx_Oversize_Frames_Good_RXOVERSZG_Pos (0UL) /*!< RXOVERSZG (Bit 0) */ + #define R_GMAC_Rx_Oversize_Frames_Good_RXOVERSZG_Msk (0xffffUL) /*!< RXOVERSZG (Bitfield-Mask: 0xffff) */ +/* ============================================== Rx_64Octets_Frames_Good_Bad ============================================== */ + #define R_GMAC_Rx_64Octets_Frames_Good_Bad_RX64OCTGB_Pos (0UL) /*!< RX64OCTGB (Bit 0) */ + #define R_GMAC_Rx_64Octets_Frames_Good_Bad_RX64OCTGB_Msk (0xffffffffUL) /*!< RX64OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Rx_65To127Octets_Frames_Good_Bad ============================================ */ + #define R_GMAC_Rx_65To127Octets_Frames_Good_Bad_RX65_127OCTGB_Pos (0UL) /*!< RX65_127OCTGB (Bit 0) */ + #define R_GMAC_Rx_65To127Octets_Frames_Good_Bad_RX65_127OCTGB_Msk (0xffffffffUL) /*!< RX65_127OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Rx_128To255Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Rx_128To255Octets_Frames_Good_Bad_RX128_255OCTGB_Pos (0UL) /*!< RX128_255OCTGB (Bit 0) */ + #define R_GMAC_Rx_128To255Octets_Frames_Good_Bad_RX128_255OCTGB_Msk (0xffffffffUL) /*!< RX128_255OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Rx_256To511Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Rx_256To511Octets_Frames_Good_Bad_RX256_511OCTGB_Pos (0UL) /*!< RX256_511OCTGB (Bit 0) */ + #define R_GMAC_Rx_256To511Octets_Frames_Good_Bad_RX256_511OCTGB_Msk (0xffffffffUL) /*!< RX256_511OCTGB (Bitfield-Mask: 0xffffffff) */ +/* ========================================== Rx_512To1023Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Rx_512To1023Octets_Frames_Good_Bad_RX512_1023OCTGB_Pos (0UL) /*!< RX512_1023OCTGB (Bit 0) */ + #define R_GMAC_Rx_512To1023Octets_Frames_Good_Bad_RX512_1023OCTGB_Msk (0xffffffffUL) /*!< RX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */ +/* ========================================== Rx_1024ToMaxOctets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Rx_1024ToMaxOctets_Frames_Good_Bad_RX1024_MAXOCTGB_Pos (0UL) /*!< RX1024_MAXOCTGB (Bit 0) */ + #define R_GMAC_Rx_1024ToMaxOctets_Frames_Good_Bad_RX1024_MAXOCTGB_Msk (0xffffffffUL) /*!< RX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */ +/* ================================================ Rx_Unicast_Frames_Good ================================================= */ + #define R_GMAC_Rx_Unicast_Frames_Good_RXUCASTG_Pos (0UL) /*!< RXUCASTG (Bit 0) */ + #define R_GMAC_Rx_Unicast_Frames_Good_RXUCASTG_Msk (0xffffffffUL) /*!< RXUCASTG (Bitfield-Mask: 0xffffffff) */ +/* ================================================ Rx_Length_Error_Frames ================================================= */ + #define R_GMAC_Rx_Length_Error_Frames_RXLENERR_Pos (0UL) /*!< RXLENERR (Bit 0) */ + #define R_GMAC_Rx_Length_Error_Frames_RXLENERR_Msk (0xffffUL) /*!< RXLENERR (Bitfield-Mask: 0xffff) */ +/* ============================================== Rx_Out_Of_Range_Type_Frames ============================================== */ + #define R_GMAC_Rx_Out_Of_Range_Type_Frames_RXOUTOFRNG_Pos (0UL) /*!< RXOUTOFRNG (Bit 0) */ + #define R_GMAC_Rx_Out_Of_Range_Type_Frames_RXOUTOFRNG_Msk (0xffffUL) /*!< RXOUTOFRNG (Bitfield-Mask: 0xffff) */ +/* ==================================================== Rx_Pause_Frames ==================================================== */ + #define R_GMAC_Rx_Pause_Frames_RXPAUSEFRM_Pos (0UL) /*!< RXPAUSEFRM (Bit 0) */ + #define R_GMAC_Rx_Pause_Frames_RXPAUSEFRM_Msk (0xffffUL) /*!< RXPAUSEFRM (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_FIFO_Overflow_Frames ================================================ */ + #define R_GMAC_Rx_FIFO_Overflow_Frames_RXFIFOOVFL_Pos (0UL) /*!< RXFIFOOVFL (Bit 0) */ + #define R_GMAC_Rx_FIFO_Overflow_Frames_RXFIFOOVFL_Msk (0xffffUL) /*!< RXFIFOOVFL (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_VLAN_Frames_Good_Bad ================================================ */ + #define R_GMAC_Rx_VLAN_Frames_Good_Bad_RXVLANFRGB_Pos (0UL) /*!< RXVLANFRGB (Bit 0) */ + #define R_GMAC_Rx_VLAN_Frames_Good_Bad_RXVLANFRGB_Msk (0xffffffffUL) /*!< RXVLANFRGB (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Rx_Watchdog_Error_Frames ================================================ */ + #define R_GMAC_Rx_Watchdog_Error_Frames_RXWDGERR_Pos (0UL) /*!< RXWDGERR (Bit 0) */ + #define R_GMAC_Rx_Watchdog_Error_Frames_RXWDGERR_Msk (0xffffUL) /*!< RXWDGERR (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_Receive_Error_Frames ================================================ */ + #define R_GMAC_Rx_Receive_Error_Frames_RXRCVERR_Pos (0UL) /*!< RXRCVERR (Bit 0) */ + #define R_GMAC_Rx_Receive_Error_Frames_RXRCVERR_Msk (0xffffUL) /*!< RXRCVERR (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_Control_Frames_Good ================================================= */ + #define R_GMAC_Rx_Control_Frames_Good_RXCTRLG_Pos (0UL) /*!< RXCTRLG (Bit 0) */ + #define R_GMAC_Rx_Control_Frames_Good_RXCTRLG_Msk (0xffffffffUL) /*!< RXCTRLG (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GMACTRGSEL ======================================================= */ + #define R_GMAC_GMACTRGSEL_TRGSEL_Pos (0UL) /*!< TRGSEL (Bit 0) */ + #define R_GMAC_GMACTRGSEL_TRGSEL_Msk (0x3UL) /*!< TRGSEL (Bitfield-Mask: 0x03) */ +/* ==================================================== HASH_TABLE_REG ===================================================== */ + #define R_GMAC_HASH_TABLE_REG_HT_Pos (0UL) /*!< HT (Bit 0) */ + #define R_GMAC_HASH_TABLE_REG_HT_Msk (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== VLAN_Hash_Table_Reg ================================================== */ + #define R_GMAC_VLAN_Hash_Table_Reg_VLHT_Pos (0UL) /*!< VLHT (Bit 0) */ + #define R_GMAC_VLAN_Hash_Table_Reg_VLHT_Msk (0xffffUL) /*!< VLHT (Bitfield-Mask: 0xffff) */ +/* =================================================== Timestamp_Control =================================================== */ + #define R_GMAC_Timestamp_Control_TSENA_Pos (0UL) /*!< TSENA (Bit 0) */ + #define R_GMAC_Timestamp_Control_TSENA_Msk (0x1UL) /*!< TSENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSENALL_Pos (8UL) /*!< TSENALL (Bit 8) */ + #define R_GMAC_Timestamp_Control_TSENALL_Msk (0x100UL) /*!< TSENALL (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSCTRLSSR_Pos (9UL) /*!< TSCTRLSSR (Bit 9) */ + #define R_GMAC_Timestamp_Control_TSCTRLSSR_Msk (0x200UL) /*!< TSCTRLSSR (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSVER2ENA_Pos (10UL) /*!< TSVER2ENA (Bit 10) */ + #define R_GMAC_Timestamp_Control_TSVER2ENA_Msk (0x400UL) /*!< TSVER2ENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSIPENA_Pos (11UL) /*!< TSIPENA (Bit 11) */ + #define R_GMAC_Timestamp_Control_TSIPENA_Msk (0x800UL) /*!< TSIPENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSIPV6ENA_Pos (12UL) /*!< TSIPV6ENA (Bit 12) */ + #define R_GMAC_Timestamp_Control_TSIPV6ENA_Msk (0x1000UL) /*!< TSIPV6ENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSIPV4ENA_Pos (13UL) /*!< TSIPV4ENA (Bit 13) */ + #define R_GMAC_Timestamp_Control_TSIPV4ENA_Msk (0x2000UL) /*!< TSIPV4ENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSEVNTENA_Pos (14UL) /*!< TSEVNTENA (Bit 14) */ + #define R_GMAC_Timestamp_Control_TSEVNTENA_Msk (0x4000UL) /*!< TSEVNTENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSMSTRENA_Pos (15UL) /*!< TSMSTRENA (Bit 15) */ + #define R_GMAC_Timestamp_Control_TSMSTRENA_Msk (0x8000UL) /*!< TSMSTRENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_SNAPTYPSEL_Pos (16UL) /*!< SNAPTYPSEL (Bit 16) */ + #define R_GMAC_Timestamp_Control_SNAPTYPSEL_Msk (0x30000UL) /*!< SNAPTYPSEL (Bitfield-Mask: 0x03) */ + #define R_GMAC_Timestamp_Control_TSENMACADDR_Pos (18UL) /*!< TSENMACADDR (Bit 18) */ + #define R_GMAC_Timestamp_Control_TSENMACADDR_Msk (0x40000UL) /*!< TSENMACADDR (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_ATSFC_Pos (24UL) /*!< ATSFC (Bit 24) */ + #define R_GMAC_Timestamp_Control_ATSFC_Msk (0x1000000UL) /*!< ATSFC (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_ATSEN0_Pos (25UL) /*!< ATSEN0 (Bit 25) */ + #define R_GMAC_Timestamp_Control_ATSEN0_Msk (0x2000000UL) /*!< ATSEN0 (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_ATSEN1_Pos (26UL) /*!< ATSEN1 (Bit 26) */ + #define R_GMAC_Timestamp_Control_ATSEN1_Msk (0x4000000UL) /*!< ATSEN1 (Bitfield-Mask: 0x01) */ +/* =================================================== Timestamp_Status ==================================================== */ + #define R_GMAC_Timestamp_Status_AUXTSTRIG_Pos (2UL) /*!< AUXTSTRIG (Bit 2) */ + #define R_GMAC_Timestamp_Status_AUXTSTRIG_Msk (0x4UL) /*!< AUXTSTRIG (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Status_ATSSTN_Pos (16UL) /*!< ATSSTN (Bit 16) */ + #define R_GMAC_Timestamp_Status_ATSSTN_Msk (0xf0000UL) /*!< ATSSTN (Bitfield-Mask: 0x0f) */ + #define R_GMAC_Timestamp_Status_ATSSTM_Pos (24UL) /*!< ATSSTM (Bit 24) */ + #define R_GMAC_Timestamp_Status_ATSSTM_Msk (0x1000000UL) /*!< ATSSTM (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Status_ATSNS_Pos (25UL) /*!< ATSNS (Bit 25) */ + #define R_GMAC_Timestamp_Status_ATSNS_Msk (0x3e000000UL) /*!< ATSNS (Bitfield-Mask: 0x1f) */ +/* ============================================ Auxiliary_Timestamp_Nanoseconds ============================================ */ + #define R_GMAC_Auxiliary_Timestamp_Nanoseconds_AUXTSLO_Pos (0UL) /*!< AUXTSLO (Bit 0) */ + #define R_GMAC_Auxiliary_Timestamp_Nanoseconds_AUXTSLO_Msk (0x7fffffffUL) /*!< AUXTSLO (Bitfield-Mask: 0x7fffffff) */ +/* ============================================== Auxiliary_Timestamp_Seconds ============================================== */ + #define R_GMAC_Auxiliary_Timestamp_Seconds_AUXTSHI_Pos (0UL) /*!< AUXTSHI (Bit 0) */ + #define R_GMAC_Auxiliary_Timestamp_Seconds_AUXTSHI_Msk (0xffffffffUL) /*!< AUXTSHI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR16_H ======================================================== */ + #define R_GMAC_MAR16_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR16_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR16_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR16_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR16_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR16_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR16_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR16_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR16_L ======================================================== */ + #define R_GMAC_MAR16_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR16_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR17_H ======================================================== */ + #define R_GMAC_MAR17_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR17_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR17_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR17_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR17_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR17_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR17_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR17_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR17_L ======================================================== */ + #define R_GMAC_MAR17_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR17_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= Bus_Mode ======================================================== */ + #define R_GMAC_Bus_Mode_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_GMAC_Bus_Mode_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_DA_Pos (1UL) /*!< DA (Bit 1) */ + #define R_GMAC_Bus_Mode_DA_Msk (0x2UL) /*!< DA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_DSL_Pos (2UL) /*!< DSL (Bit 2) */ + #define R_GMAC_Bus_Mode_DSL_Msk (0x7cUL) /*!< DSL (Bitfield-Mask: 0x1f) */ + #define R_GMAC_Bus_Mode_ATDS_Pos (7UL) /*!< ATDS (Bit 7) */ + #define R_GMAC_Bus_Mode_ATDS_Msk (0x80UL) /*!< ATDS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_PBL_Pos (8UL) /*!< PBL (Bit 8) */ + #define R_GMAC_Bus_Mode_PBL_Msk (0x3f00UL) /*!< PBL (Bitfield-Mask: 0x3f) */ + #define R_GMAC_Bus_Mode_PR_Pos (14UL) /*!< PR (Bit 14) */ + #define R_GMAC_Bus_Mode_PR_Msk (0xc000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GMAC_Bus_Mode_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GMAC_Bus_Mode_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_RPBL_Pos (17UL) /*!< RPBL (Bit 17) */ + #define R_GMAC_Bus_Mode_RPBL_Msk (0x7e0000UL) /*!< RPBL (Bitfield-Mask: 0x3f) */ + #define R_GMAC_Bus_Mode_USP_Pos (23UL) /*!< USP (Bit 23) */ + #define R_GMAC_Bus_Mode_USP_Msk (0x800000UL) /*!< USP (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_PBLx8_Pos (24UL) /*!< PBLx8 (Bit 24) */ + #define R_GMAC_Bus_Mode_PBLx8_Msk (0x1000000UL) /*!< PBLx8 (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_AAL_Pos (25UL) /*!< AAL (Bit 25) */ + #define R_GMAC_Bus_Mode_AAL_Msk (0x2000000UL) /*!< AAL (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_MB_Pos (26UL) /*!< MB (Bit 26) */ + #define R_GMAC_Bus_Mode_MB_Msk (0x4000000UL) /*!< MB (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_TXPR_Pos (27UL) /*!< TXPR (Bit 27) */ + #define R_GMAC_Bus_Mode_TXPR_Msk (0x8000000UL) /*!< TXPR (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_PRWG_Pos (28UL) /*!< PRWG (Bit 28) */ + #define R_GMAC_Bus_Mode_PRWG_Msk (0x30000000UL) /*!< PRWG (Bitfield-Mask: 0x03) */ + #define R_GMAC_Bus_Mode_RIB_Pos (31UL) /*!< RIB (Bit 31) */ + #define R_GMAC_Bus_Mode_RIB_Msk (0x80000000UL) /*!< RIB (Bitfield-Mask: 0x01) */ +/* ================================================= Transmit_Poll_Demand ================================================== */ + #define R_GMAC_Transmit_Poll_Demand_TPD_Pos (0UL) /*!< TPD (Bit 0) */ + #define R_GMAC_Transmit_Poll_Demand_TPD_Msk (0xffffffffUL) /*!< TPD (Bitfield-Mask: 0xffffffff) */ +/* ================================================== Receive_Poll_Demand ================================================== */ + #define R_GMAC_Receive_Poll_Demand_RPD_Pos (0UL) /*!< RPD (Bit 0) */ + #define R_GMAC_Receive_Poll_Demand_RPD_Msk (0xffffffffUL) /*!< RPD (Bitfield-Mask: 0xffffffff) */ +/* ============================================ Receive_Descriptor_List_Address ============================================ */ + #define R_GMAC_Receive_Descriptor_List_Address_RDESLA_32bit_Pos (2UL) /*!< RDESLA_32bit (Bit 2) */ + #define R_GMAC_Receive_Descriptor_List_Address_RDESLA_32bit_Msk (0xfffffffcUL) /*!< RDESLA_32bit (Bitfield-Mask: 0x3fffffff) */ +/* =========================================== Transmit_Descriptor_List_Address ============================================ */ + #define R_GMAC_Transmit_Descriptor_List_Address_TDESLA_32bit_Pos (2UL) /*!< TDESLA_32bit (Bit 2) */ + #define R_GMAC_Transmit_Descriptor_List_Address_TDESLA_32bit_Msk (0xfffffffcUL) /*!< TDESLA_32bit (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================== Status ========================================================= */ + #define R_GMAC_Status_TI_Pos (0UL) /*!< TI (Bit 0) */ + #define R_GMAC_Status_TI_Msk (0x1UL) /*!< TI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_TPS_Pos (1UL) /*!< TPS (Bit 1) */ + #define R_GMAC_Status_TPS_Msk (0x2UL) /*!< TPS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_TU_Pos (2UL) /*!< TU (Bit 2) */ + #define R_GMAC_Status_TU_Msk (0x4UL) /*!< TU (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_TJT_Pos (3UL) /*!< TJT (Bit 3) */ + #define R_GMAC_Status_TJT_Msk (0x8UL) /*!< TJT (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_OVF_Pos (4UL) /*!< OVF (Bit 4) */ + #define R_GMAC_Status_OVF_Msk (0x10UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_UNF_Pos (5UL) /*!< UNF (Bit 5) */ + #define R_GMAC_Status_UNF_Msk (0x20UL) /*!< UNF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_GMAC_Status_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_RU_Pos (7UL) /*!< RU (Bit 7) */ + #define R_GMAC_Status_RU_Msk (0x80UL) /*!< RU (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_RPS_Pos (8UL) /*!< RPS (Bit 8) */ + #define R_GMAC_Status_RPS_Msk (0x100UL) /*!< RPS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_RWT_Pos (9UL) /*!< RWT (Bit 9) */ + #define R_GMAC_Status_RWT_Msk (0x200UL) /*!< RWT (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_ETI_Pos (10UL) /*!< ETI (Bit 10) */ + #define R_GMAC_Status_ETI_Msk (0x400UL) /*!< ETI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_FBI_Pos (13UL) /*!< FBI (Bit 13) */ + #define R_GMAC_Status_FBI_Msk (0x2000UL) /*!< FBI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_ERI_Pos (14UL) /*!< ERI (Bit 14) */ + #define R_GMAC_Status_ERI_Msk (0x4000UL) /*!< ERI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_AIS_Pos (15UL) /*!< AIS (Bit 15) */ + #define R_GMAC_Status_AIS_Msk (0x8000UL) /*!< AIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_NIS_Pos (16UL) /*!< NIS (Bit 16) */ + #define R_GMAC_Status_NIS_Msk (0x10000UL) /*!< NIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_RS_Pos (17UL) /*!< RS (Bit 17) */ + #define R_GMAC_Status_RS_Msk (0xe0000UL) /*!< RS (Bitfield-Mask: 0x07) */ + #define R_GMAC_Status_TS_Pos (20UL) /*!< TS (Bit 20) */ + #define R_GMAC_Status_TS_Msk (0x700000UL) /*!< TS (Bitfield-Mask: 0x07) */ + #define R_GMAC_Status_EB_Pos (23UL) /*!< EB (Bit 23) */ + #define R_GMAC_Status_EB_Msk (0x3800000UL) /*!< EB (Bitfield-Mask: 0x07) */ + #define R_GMAC_Status_GMI_Pos (27UL) /*!< GMI (Bit 27) */ + #define R_GMAC_Status_GMI_Msk (0x8000000UL) /*!< GMI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_GPI_Pos (28UL) /*!< GPI (Bit 28) */ + #define R_GMAC_Status_GPI_Msk (0x10000000UL) /*!< GPI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_TTI_Pos (29UL) /*!< TTI (Bit 29) */ + #define R_GMAC_Status_TTI_Msk (0x20000000UL) /*!< TTI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_GLPII_Pos (30UL) /*!< GLPII (Bit 30) */ + #define R_GMAC_Status_GLPII_Msk (0x40000000UL) /*!< GLPII (Bitfield-Mask: 0x01) */ +/* ==================================================== Operation_Mode ===================================================== */ + #define R_GMAC_Operation_Mode_SR_Pos (1UL) /*!< SR (Bit 1) */ + #define R_GMAC_Operation_Mode_SR_Msk (0x2UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_OSF_Pos (2UL) /*!< OSF (Bit 2) */ + #define R_GMAC_Operation_Mode_OSF_Msk (0x4UL) /*!< OSF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_RTC_Pos (3UL) /*!< RTC (Bit 3) */ + #define R_GMAC_Operation_Mode_RTC_Msk (0x18UL) /*!< RTC (Bitfield-Mask: 0x03) */ + #define R_GMAC_Operation_Mode_DGF_Pos (5UL) /*!< DGF (Bit 5) */ + #define R_GMAC_Operation_Mode_DGF_Msk (0x20UL) /*!< DGF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_FUF_Pos (6UL) /*!< FUF (Bit 6) */ + #define R_GMAC_Operation_Mode_FUF_Msk (0x40UL) /*!< FUF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_FEF_Pos (7UL) /*!< FEF (Bit 7) */ + #define R_GMAC_Operation_Mode_FEF_Msk (0x80UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_EFC_Pos (8UL) /*!< EFC (Bit 8) */ + #define R_GMAC_Operation_Mode_EFC_Msk (0x100UL) /*!< EFC (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_RFA_Pos (9UL) /*!< RFA (Bit 9) */ + #define R_GMAC_Operation_Mode_RFA_Msk (0x600UL) /*!< RFA (Bitfield-Mask: 0x03) */ + #define R_GMAC_Operation_Mode_RFD_Pos (11UL) /*!< RFD (Bit 11) */ + #define R_GMAC_Operation_Mode_RFD_Msk (0x1800UL) /*!< RFD (Bitfield-Mask: 0x03) */ + #define R_GMAC_Operation_Mode_ST_Pos (13UL) /*!< ST (Bit 13) */ + #define R_GMAC_Operation_Mode_ST_Msk (0x2000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_TTC_Pos (14UL) /*!< TTC (Bit 14) */ + #define R_GMAC_Operation_Mode_TTC_Msk (0x1c000UL) /*!< TTC (Bitfield-Mask: 0x07) */ + #define R_GMAC_Operation_Mode_FTF_Pos (20UL) /*!< FTF (Bit 20) */ + #define R_GMAC_Operation_Mode_FTF_Msk (0x100000UL) /*!< FTF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_TSF_Pos (21UL) /*!< TSF (Bit 21) */ + #define R_GMAC_Operation_Mode_TSF_Msk (0x200000UL) /*!< TSF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_RSF_Pos (25UL) /*!< RSF (Bit 25) */ + #define R_GMAC_Operation_Mode_RSF_Msk (0x2000000UL) /*!< RSF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_DT_Pos (26UL) /*!< DT (Bit 26) */ + #define R_GMAC_Operation_Mode_DT_Msk (0x4000000UL) /*!< DT (Bitfield-Mask: 0x01) */ +/* =================================================== Interrupt_Enable ==================================================== */ + #define R_GMAC_Interrupt_Enable_TIE_Pos (0UL) /*!< TIE (Bit 0) */ + #define R_GMAC_Interrupt_Enable_TIE_Msk (0x1UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_TSE_Pos (1UL) /*!< TSE (Bit 1) */ + #define R_GMAC_Interrupt_Enable_TSE_Msk (0x2UL) /*!< TSE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_TUE_Pos (2UL) /*!< TUE (Bit 2) */ + #define R_GMAC_Interrupt_Enable_TUE_Msk (0x4UL) /*!< TUE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_TJE_Pos (3UL) /*!< TJE (Bit 3) */ + #define R_GMAC_Interrupt_Enable_TJE_Msk (0x8UL) /*!< TJE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_OVE_Pos (4UL) /*!< OVE (Bit 4) */ + #define R_GMAC_Interrupt_Enable_OVE_Msk (0x10UL) /*!< OVE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_UNE_Pos (5UL) /*!< UNE (Bit 5) */ + #define R_GMAC_Interrupt_Enable_UNE_Msk (0x20UL) /*!< UNE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_GMAC_Interrupt_Enable_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_RUE_Pos (7UL) /*!< RUE (Bit 7) */ + #define R_GMAC_Interrupt_Enable_RUE_Msk (0x80UL) /*!< RUE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_RSE_Pos (8UL) /*!< RSE (Bit 8) */ + #define R_GMAC_Interrupt_Enable_RSE_Msk (0x100UL) /*!< RSE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_RWE_Pos (9UL) /*!< RWE (Bit 9) */ + #define R_GMAC_Interrupt_Enable_RWE_Msk (0x200UL) /*!< RWE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_ETE_Pos (10UL) /*!< ETE (Bit 10) */ + #define R_GMAC_Interrupt_Enable_ETE_Msk (0x400UL) /*!< ETE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_FBE_Pos (13UL) /*!< FBE (Bit 13) */ + #define R_GMAC_Interrupt_Enable_FBE_Msk (0x2000UL) /*!< FBE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_ERE_Pos (14UL) /*!< ERE (Bit 14) */ + #define R_GMAC_Interrupt_Enable_ERE_Msk (0x4000UL) /*!< ERE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_AIE_Pos (15UL) /*!< AIE (Bit 15) */ + #define R_GMAC_Interrupt_Enable_AIE_Msk (0x8000UL) /*!< AIE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_NIE_Pos (16UL) /*!< NIE (Bit 16) */ + #define R_GMAC_Interrupt_Enable_NIE_Msk (0x10000UL) /*!< NIE (Bitfield-Mask: 0x01) */ +/* ======================================= Missed_Frame_And_Buffer_Overflow_Counter ======================================== */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISFRMCNT_Pos (0UL) /*!< MISFRMCNT (Bit 0) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISFRMCNT_Msk (0xffffUL) /*!< MISFRMCNT (Bitfield-Mask: 0xffff) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISCNTOVF_Pos (16UL) /*!< MISCNTOVF (Bit 16) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISCNTOVF_Msk (0x10000UL) /*!< MISCNTOVF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFFRMCNT_Pos (17UL) /*!< OVFFRMCNT (Bit 17) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFFRMCNT_Msk (0xffe0000UL) /*!< OVFFRMCNT (Bitfield-Mask: 0x7ff) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFCNTOVF_Pos (28UL) /*!< OVFCNTOVF (Bit 28) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFCNTOVF_Msk (0x10000000UL) /*!< OVFCNTOVF (Bitfield-Mask: 0x01) */ +/* =========================================== Receive_Interrupt_Watchdog_Timer ============================================ */ + #define R_GMAC_Receive_Interrupt_Watchdog_Timer_RIWT_Pos (0UL) /*!< RIWT (Bit 0) */ + #define R_GMAC_Receive_Interrupt_Watchdog_Timer_RIWT_Msk (0xffUL) /*!< RIWT (Bitfield-Mask: 0xff) */ +/* ===================================================== AXI_Bus_Mode ====================================================== */ + #define R_GMAC_AXI_Bus_Mode_UNDEF_Pos (0UL) /*!< UNDEF (Bit 0) */ + #define R_GMAC_AXI_Bus_Mode_UNDEF_Msk (0x1UL) /*!< UNDEF (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_BLEN4_Pos (1UL) /*!< BLEN4 (Bit 1) */ + #define R_GMAC_AXI_Bus_Mode_BLEN4_Msk (0x2UL) /*!< BLEN4 (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_BLEN8_Pos (2UL) /*!< BLEN8 (Bit 2) */ + #define R_GMAC_AXI_Bus_Mode_BLEN8_Msk (0x4UL) /*!< BLEN8 (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_BLEN16_Pos (3UL) /*!< BLEN16 (Bit 3) */ + #define R_GMAC_AXI_Bus_Mode_BLEN16_Msk (0x8UL) /*!< BLEN16 (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_AXI_AAL_Pos (12UL) /*!< AXI_AAL (Bit 12) */ + #define R_GMAC_AXI_Bus_Mode_AXI_AAL_Msk (0x1000UL) /*!< AXI_AAL (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_ONEKBBE_Pos (13UL) /*!< ONEKBBE (Bit 13) */ + #define R_GMAC_AXI_Bus_Mode_ONEKBBE_Msk (0x2000UL) /*!< ONEKBBE (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_RD_OSR_LMT_Pos (16UL) /*!< RD_OSR_LMT (Bit 16) */ + #define R_GMAC_AXI_Bus_Mode_RD_OSR_LMT_Msk (0x30000UL) /*!< RD_OSR_LMT (Bitfield-Mask: 0x03) */ + #define R_GMAC_AXI_Bus_Mode_WR_OSR_LMT_Pos (20UL) /*!< WR_OSR_LMT (Bit 20) */ + #define R_GMAC_AXI_Bus_Mode_WR_OSR_LMT_Msk (0x300000UL) /*!< WR_OSR_LMT (Bitfield-Mask: 0x03) */ + #define R_GMAC_AXI_Bus_Mode_LPI_XIT_FRM_Pos (30UL) /*!< LPI_XIT_FRM (Bit 30) */ + #define R_GMAC_AXI_Bus_Mode_LPI_XIT_FRM_Msk (0x40000000UL) /*!< LPI_XIT_FRM (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_EN_LPI_Pos (31UL) /*!< EN_LPI (Bit 31) */ + #define R_GMAC_AXI_Bus_Mode_EN_LPI_Msk (0x80000000UL) /*!< EN_LPI (Bitfield-Mask: 0x01) */ +/* ====================================================== AXI_Status ======================================================= */ + #define R_GMAC_AXI_Status_AXWHSTS_Pos (0UL) /*!< AXWHSTS (Bit 0) */ + #define R_GMAC_AXI_Status_AXWHSTS_Msk (0x1UL) /*!< AXWHSTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Status_AXIRDSTS_Pos (1UL) /*!< AXIRDSTS (Bit 1) */ + #define R_GMAC_AXI_Status_AXIRDSTS_Msk (0x2UL) /*!< AXIRDSTS (Bitfield-Mask: 0x01) */ +/* =========================================== Current_Host_Transmit_Descriptor ============================================ */ + #define R_GMAC_Current_Host_Transmit_Descriptor_CURTDESAPTR_Pos (0UL) /*!< CURTDESAPTR (Bit 0) */ + #define R_GMAC_Current_Host_Transmit_Descriptor_CURTDESAPTR_Msk (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff) */ +/* ============================================ Current_Host_Receive_Descriptor ============================================ */ + #define R_GMAC_Current_Host_Receive_Descriptor_CURRDESAPTR_Pos (0UL) /*!< CURRDESAPTR (Bit 0) */ + #define R_GMAC_Current_Host_Receive_Descriptor_CURRDESAPTR_Msk (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff) */ +/* ========================================= Current_Host_Transmit_Buffer_Address ========================================== */ + #define R_GMAC_Current_Host_Transmit_Buffer_Address_CURTBUFAPTR_Pos (0UL) /*!< CURTBUFAPTR (Bit 0) */ + #define R_GMAC_Current_Host_Transmit_Buffer_Address_CURTBUFAPTR_Msk (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff) */ +/* ========================================== Current_Host_Receive_Buffer_Address ========================================== */ + #define R_GMAC_Current_Host_Receive_Buffer_Address_CURRBUFAPTR_Pos (0UL) /*!< CURRBUFAPTR (Bit 0) */ + #define R_GMAC_Current_Host_Receive_Buffer_Address_CURRBUFAPTR_Msk (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== HW_Feature ======================================================= */ + #define R_GMAC_HW_Feature_MIISEL_Pos (0UL) /*!< MIISEL (Bit 0) */ + #define R_GMAC_HW_Feature_MIISEL_Msk (0x1UL) /*!< MIISEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_GMIISEL_Pos (1UL) /*!< GMIISEL (Bit 1) */ + #define R_GMAC_HW_Feature_GMIISEL_Msk (0x2UL) /*!< GMIISEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_HDSEL_Pos (2UL) /*!< HDSEL (Bit 2) */ + #define R_GMAC_HW_Feature_HDSEL_Msk (0x4UL) /*!< HDSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_EXTHASHEN_Pos (3UL) /*!< EXTHASHEN (Bit 3) */ + #define R_GMAC_HW_Feature_EXTHASHEN_Msk (0x8UL) /*!< EXTHASHEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_HASHSEL_Pos (4UL) /*!< HASHSEL (Bit 4) */ + #define R_GMAC_HW_Feature_HASHSEL_Msk (0x10UL) /*!< HASHSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_ADDMACADRSEL_Pos (5UL) /*!< ADDMACADRSEL (Bit 5) */ + #define R_GMAC_HW_Feature_ADDMACADRSEL_Msk (0x20UL) /*!< ADDMACADRSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_L3L4FLTREN_Pos (7UL) /*!< L3L4FLTREN (Bit 7) */ + #define R_GMAC_HW_Feature_L3L4FLTREN_Msk (0x80UL) /*!< L3L4FLTREN (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_SMASEL_Pos (8UL) /*!< SMASEL (Bit 8) */ + #define R_GMAC_HW_Feature_SMASEL_Msk (0x100UL) /*!< SMASEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_RWKSEL_Pos (9UL) /*!< RWKSEL (Bit 9) */ + #define R_GMAC_HW_Feature_RWKSEL_Msk (0x200UL) /*!< RWKSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_MGKSEL_Pos (10UL) /*!< MGKSEL (Bit 10) */ + #define R_GMAC_HW_Feature_MGKSEL_Msk (0x400UL) /*!< MGKSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_MMCSEL_Pos (11UL) /*!< MMCSEL (Bit 11) */ + #define R_GMAC_HW_Feature_MMCSEL_Msk (0x800UL) /*!< MMCSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_TSVER1SEL_Pos (12UL) /*!< TSVER1SEL (Bit 12) */ + #define R_GMAC_HW_Feature_TSVER1SEL_Msk (0x1000UL) /*!< TSVER1SEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_TSVER2SEL_Pos (13UL) /*!< TSVER2SEL (Bit 13) */ + #define R_GMAC_HW_Feature_TSVER2SEL_Msk (0x2000UL) /*!< TSVER2SEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_EEESEL_Pos (14UL) /*!< EEESEL (Bit 14) */ + #define R_GMAC_HW_Feature_EEESEL_Msk (0x4000UL) /*!< EEESEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_AVSEL_Pos (15UL) /*!< AVSEL (Bit 15) */ + #define R_GMAC_HW_Feature_AVSEL_Msk (0x8000UL) /*!< AVSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_TXCOESEL_Pos (16UL) /*!< TXCOESEL (Bit 16) */ + #define R_GMAC_HW_Feature_TXCOESEL_Msk (0x10000UL) /*!< TXCOESEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_RXTYP1COE_Pos (17UL) /*!< RXTYP1COE (Bit 17) */ + #define R_GMAC_HW_Feature_RXTYP1COE_Msk (0x20000UL) /*!< RXTYP1COE (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_RXTYP2COE_Pos (18UL) /*!< RXTYP2COE (Bit 18) */ + #define R_GMAC_HW_Feature_RXTYP2COE_Msk (0x40000UL) /*!< RXTYP2COE (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_RXFIFOSIZE_Pos (19UL) /*!< RXFIFOSIZE (Bit 19) */ + #define R_GMAC_HW_Feature_RXFIFOSIZE_Msk (0x80000UL) /*!< RXFIFOSIZE (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_RXCHCNT_Pos (20UL) /*!< RXCHCNT (Bit 20) */ + #define R_GMAC_HW_Feature_RXCHCNT_Msk (0x300000UL) /*!< RXCHCNT (Bitfield-Mask: 0x03) */ + #define R_GMAC_HW_Feature_TXCHCNT_Pos (22UL) /*!< TXCHCNT (Bit 22) */ + #define R_GMAC_HW_Feature_TXCHCNT_Msk (0xc00000UL) /*!< TXCHCNT (Bitfield-Mask: 0x03) */ + #define R_GMAC_HW_Feature_ENHDESSEL_Pos (24UL) /*!< ENHDESSEL (Bit 24) */ + #define R_GMAC_HW_Feature_ENHDESSEL_Msk (0x1000000UL) /*!< ENHDESSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_INTTSEN_Pos (25UL) /*!< INTTSEN (Bit 25) */ + #define R_GMAC_HW_Feature_INTTSEN_Msk (0x2000000UL) /*!< INTTSEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_FLEXIPPSEN_Pos (26UL) /*!< FLEXIPPSEN (Bit 26) */ + #define R_GMAC_HW_Feature_FLEXIPPSEN_Msk (0x4000000UL) /*!< FLEXIPPSEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_SAVLANINS_Pos (27UL) /*!< SAVLANINS (Bit 27) */ + #define R_GMAC_HW_Feature_SAVLANINS_Msk (0x8000000UL) /*!< SAVLANINS (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_ACTPHYIF_Pos (28UL) /*!< ACTPHYIF (Bit 28) */ + #define R_GMAC_HW_Feature_ACTPHYIF_Msk (0x70000000UL) /*!< ACTPHYIF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRCMD ========================================================= */ +/* ======================================================== MODCTRL ======================================================== */ + #define R_ETHSS_MODCTRL_SW_MODE_Pos (0UL) /*!< SW_MODE (Bit 0) */ + #define R_ETHSS_MODCTRL_SW_MODE_Msk (0x7UL) /*!< SW_MODE (Bitfield-Mask: 0x07) */ +/* ======================================================= PTPMCTRL ======================================================== */ + #define R_ETHSS_PTPMCTRL_PTP_MODE_Pos (0UL) /*!< PTP_MODE (Bit 0) */ + #define R_ETHSS_PTPMCTRL_PTP_MODE_Msk (0x1UL) /*!< PTP_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSS_PTPMCTRL_PTP_PLS_RSTn_Pos (16UL) /*!< PTP_PLS_RSTn (Bit 16) */ + #define R_ETHSS_PTPMCTRL_PTP_PLS_RSTn_Msk (0x10000UL) /*!< PTP_PLS_RSTn (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYLNK ========================================================= */ + #define R_ETHSS_PHYLNK_SWLINK_Pos (0UL) /*!< SWLINK (Bit 0) */ + #define R_ETHSS_PHYLNK_SWLINK_Msk (0x7UL) /*!< SWLINK (Bitfield-Mask: 0x07) */ + #define R_ETHSS_PHYLNK_CATLNK_Pos (4UL) /*!< CATLNK (Bit 4) */ + #define R_ETHSS_PHYLNK_CATLNK_Msk (0x70UL) /*!< CATLNK (Bitfield-Mask: 0x07) */ +/* ======================================================= CONVCTRL ======================================================== */ + #define R_ETHSS_CONVCTRL_CONV_MODE_Pos (0UL) /*!< CONV_MODE (Bit 0) */ + #define R_ETHSS_CONVCTRL_CONV_MODE_Msk (0x1fUL) /*!< CONV_MODE (Bitfield-Mask: 0x1f) */ + #define R_ETHSS_CONVCTRL_FULLD_Pos (8UL) /*!< FULLD (Bit 8) */ + #define R_ETHSS_CONVCTRL_FULLD_Msk (0x100UL) /*!< FULLD (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CONVCTRL_RMII_RX_ER_EN_Pos (9UL) /*!< RMII_RX_ER_EN (Bit 9) */ + #define R_ETHSS_CONVCTRL_RMII_RX_ER_EN_Msk (0x200UL) /*!< RMII_RX_ER_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CONVCTRL_RMII_CRS_MODE_Pos (10UL) /*!< RMII_CRS_MODE (Bit 10) */ + #define R_ETHSS_CONVCTRL_RMII_CRS_MODE_Msk (0x400UL) /*!< RMII_CRS_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CONVCTRL_RGMII_LINK_Pos (12UL) /*!< RGMII_LINK (Bit 12) */ + #define R_ETHSS_CONVCTRL_RGMII_LINK_Msk (0x1000UL) /*!< RGMII_LINK (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CONVCTRL_RGMII_DUPLEX_Pos (13UL) /*!< RGMII_DUPLEX (Bit 13) */ + #define R_ETHSS_CONVCTRL_RGMII_DUPLEX_Msk (0x2000UL) /*!< RGMII_DUPLEX (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CONVCTRL_RGMII_SPEED_Pos (14UL) /*!< RGMII_SPEED (Bit 14) */ + #define R_ETHSS_CONVCTRL_RGMII_SPEED_Msk (0xc000UL) /*!< RGMII_SPEED (Bitfield-Mask: 0x03) */ +/* ======================================================== CONVRST ======================================================== */ + #define R_ETHSS_CONVRST_PHYIR_Pos (0UL) /*!< PHYIR (Bit 0) */ + #define R_ETHSS_CONVRST_PHYIR_Msk (0x7UL) /*!< PHYIR (Bitfield-Mask: 0x07) */ +/* ======================================================== SWCTRL ========================================================= */ + #define R_ETHSS_SWCTRL_SET10_Pos (0UL) /*!< SET10 (Bit 0) */ + #define R_ETHSS_SWCTRL_SET10_Msk (0x7UL) /*!< SET10 (Bitfield-Mask: 0x07) */ + #define R_ETHSS_SWCTRL_SET1000_Pos (4UL) /*!< SET1000 (Bit 4) */ + #define R_ETHSS_SWCTRL_SET1000_Msk (0x70UL) /*!< SET1000 (Bitfield-Mask: 0x07) */ + #define R_ETHSS_SWCTRL_STRAP_SX_ENB_Pos (16UL) /*!< STRAP_SX_ENB (Bit 16) */ + #define R_ETHSS_SWCTRL_STRAP_SX_ENB_Msk (0x10000UL) /*!< STRAP_SX_ENB (Bitfield-Mask: 0x01) */ + #define R_ETHSS_SWCTRL_STRAP_HUB_ENB_Pos (17UL) /*!< STRAP_HUB_ENB (Bit 17) */ + #define R_ETHSS_SWCTRL_STRAP_HUB_ENB_Msk (0x20000UL) /*!< STRAP_HUB_ENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SWDUPC ========================================================= */ + #define R_ETHSS_SWDUPC_PHY_DUPLEX_Pos (0UL) /*!< PHY_DUPLEX (Bit 0) */ + #define R_ETHSS_SWDUPC_PHY_DUPLEX_Msk (0x7UL) /*!< PHY_DUPLEX (Bitfield-Mask: 0x07) */ +/* ========================================================= CDCR ========================================================== */ + #define R_ETHSS_CDCR_RXDLYEN_Pos (0UL) /*!< RXDLYEN (Bit 0) */ + #define R_ETHSS_CDCR_RXDLYEN_Msk (0x1UL) /*!< RXDLYEN (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CDCR_TXDLYEN_Pos (1UL) /*!< TXDLYEN (Bit 1) */ + #define R_ETHSS_CDCR_TXDLYEN_Msk (0x2UL) /*!< TXDLYEN (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CDCR_OSCCLKEN_Pos (2UL) /*!< OSCCLKEN (Bit 2) */ + #define R_ETHSS_CDCR_OSCCLKEN_Msk (0x4UL) /*!< OSCCLKEN (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CDCR_CLKINEN_Pos (3UL) /*!< CLKINEN (Bit 3) */ + #define R_ETHSS_CDCR_CLKINEN_Msk (0x8UL) /*!< CLKINEN (Bitfield-Mask: 0x01) */ +/* ======================================================== RXFCNT ========================================================= */ + #define R_ETHSS_RXFCNT_RXFCNT_Pos (0UL) /*!< RXFCNT (Bit 0) */ + #define R_ETHSS_RXFCNT_RXFCNT_Msk (0xffffUL) /*!< RXFCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================== TXFCNT ========================================================= */ + #define R_ETHSS_TXFCNT_TXFCNT_Pos (0UL) /*!< TXFCNT (Bit 0) */ + #define R_ETHSS_TXFCNT_TXFCNT_Msk (0xffffUL) /*!< TXFCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= RXTAPSEL ======================================================== */ + #define R_ETHSS_RXTAPSEL_RXTAPSEL_Pos (0UL) /*!< RXTAPSEL (Bit 0) */ + #define R_ETHSS_RXTAPSEL_RXTAPSEL_Msk (0x7fUL) /*!< RXTAPSEL (Bitfield-Mask: 0x7f) */ +/* ======================================================= TXTAPSEL ======================================================== */ + #define R_ETHSS_TXTAPSEL_TXTAPSEL_Pos (0UL) /*!< TXTAPSEL (Bit 0) */ + #define R_ETHSS_TXTAPSEL_TXTAPSEL_Msk (0x7fUL) /*!< TXTAPSEL (Bitfield-Mask: 0x7f) */ +/* ======================================================== MIIMCR ========================================================= */ + #define R_ETHSS_MIIMCR_MIIM2MEN_Pos (0UL) /*!< MIIM2MEN (Bit 0) */ + #define R_ETHSS_MIIMCR_MIIM2MEN_Msk (0x1UL) /*!< MIIM2MEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ESC_INI ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== ECATOFFADR ======================================================= */ + #define R_ESC_INI_ECATOFFADR_OADD_Pos (0UL) /*!< OADD (Bit 0) */ + #define R_ESC_INI_ECATOFFADR_OADD_Msk (0x1fUL) /*!< OADD (Bitfield-Mask: 0x1f) */ +/* ======================================================= ECATOPMOD ======================================================= */ + #define R_ESC_INI_ECATOPMOD_EEPROMSIZE_Pos (0UL) /*!< EEPROMSIZE (Bit 0) */ + #define R_ESC_INI_ECATOPMOD_EEPROMSIZE_Msk (0x1UL) /*!< EEPROMSIZE (Bitfield-Mask: 0x01) */ +/* ======================================================= ECATDBGC ======================================================== */ + #define R_ESC_INI_ECATDBGC_TXSFT0_Pos (0UL) /*!< TXSFT0 (Bit 0) */ + #define R_ESC_INI_ECATDBGC_TXSFT0_Msk (0x3UL) /*!< TXSFT0 (Bitfield-Mask: 0x03) */ + #define R_ESC_INI_ECATDBGC_TXSFT1_Pos (2UL) /*!< TXSFT1 (Bit 2) */ + #define R_ESC_INI_ECATDBGC_TXSFT1_Msk (0xcUL) /*!< TXSFT1 (Bitfield-Mask: 0x03) */ + #define R_ESC_INI_ECATDBGC_TXSFT2_Pos (4UL) /*!< TXSFT2 (Bit 4) */ + #define R_ESC_INI_ECATDBGC_TXSFT2_Msk (0x30UL) /*!< TXSFT2 (Bitfield-Mask: 0x03) */ +/* ====================================================== ECATTRGSEL ======================================================= */ + #define R_ESC_INI_ECATTRGSEL_TRGSEL0_Pos (0UL) /*!< TRGSEL0 (Bit 0) */ + #define R_ESC_INI_ECATTRGSEL_TRGSEL0_Msk (0x1UL) /*!< TRGSEL0 (Bitfield-Mask: 0x01) */ + #define R_ESC_INI_ECATTRGSEL_TRGSEL1_Pos (1UL) /*!< TRGSEL1 (Bit 1) */ + #define R_ESC_INI_ECATTRGSEL_TRGSEL1_Msk (0x2UL) /*!< TRGSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHSW_PTP ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== SWPTPOUTSEL ====================================================== */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL0_Pos (0UL) /*!< IOSEL0 (Bit 0) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL0_Msk (0x1UL) /*!< IOSEL0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL1_Pos (1UL) /*!< IOSEL1 (Bit 1) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL1_Msk (0x2UL) /*!< IOSEL1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL2_Pos (2UL) /*!< IOSEL2 (Bit 2) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL2_Msk (0x4UL) /*!< IOSEL2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL3_Pos (3UL) /*!< IOSEL3 (Bit 3) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL3_Msk (0x8UL) /*!< IOSEL3 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL0_Pos (4UL) /*!< EVTSEL0 (Bit 4) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL0_Msk (0x10UL) /*!< EVTSEL0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL1_Pos (5UL) /*!< EVTSEL1 (Bit 5) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL1_Msk (0x20UL) /*!< EVTSEL1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL2_Pos (6UL) /*!< EVTSEL2 (Bit 6) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL2_Msk (0x40UL) /*!< EVTSEL2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL3_Pos (7UL) /*!< EVTSEL3 (Bit 7) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL3_Msk (0x80UL) /*!< EVTSEL3 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHSW ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= REVISION ======================================================== */ + #define R_ETHSW_REVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_ETHSW_REVISION_REV_Msk (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCRATCH ======================================================== */ + #define R_ETHSW_SCRATCH_SCRATCH_Pos (0UL) /*!< SCRATCH (Bit 0) */ + #define R_ETHSW_SCRATCH_SCRATCH_Msk (0xffffffffUL) /*!< SCRATCH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PORT_ENA ======================================================== */ + #define R_ETHSW_PORT_ENA_TXENA_Pos (0UL) /*!< TXENA (Bit 0) */ + #define R_ETHSW_PORT_ENA_TXENA_Msk (0xfUL) /*!< TXENA (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_PORT_ENA_RXENA_Pos (16UL) /*!< RXENA (Bit 16) */ + #define R_ETHSW_PORT_ENA_RXENA_Msk (0xf0000UL) /*!< RXENA (Bitfield-Mask: 0x0f) */ +/* ================================================== UCAST_DEFAULT_MASK0 ================================================== */ + #define R_ETHSW_UCAST_DEFAULT_MASK0_UCASTDM_Pos (0UL) /*!< UCASTDM (Bit 0) */ + #define R_ETHSW_UCAST_DEFAULT_MASK0_UCASTDM_Msk (0xfUL) /*!< UCASTDM (Bitfield-Mask: 0x0f) */ +/* ====================================================== VLAN_VERIFY ====================================================== */ + #define R_ETHSW_VLAN_VERIFY_VLANVERI_Pos (0UL) /*!< VLANVERI (Bit 0) */ + #define R_ETHSW_VLAN_VERIFY_VLANVERI_Msk (0xfUL) /*!< VLANVERI (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_VLAN_VERIFY_VLANDISC_Pos (16UL) /*!< VLANDISC (Bit 16) */ + #define R_ETHSW_VLAN_VERIFY_VLANDISC_Msk (0xf0000UL) /*!< VLANDISC (Bitfield-Mask: 0x0f) */ +/* ================================================== BCAST_DEFAULT_MASK0 ================================================== */ + #define R_ETHSW_BCAST_DEFAULT_MASK0_BCASTDM_Pos (0UL) /*!< BCASTDM (Bit 0) */ + #define R_ETHSW_BCAST_DEFAULT_MASK0_BCASTDM_Msk (0xfUL) /*!< BCASTDM (Bitfield-Mask: 0x0f) */ +/* ================================================== MCAST_DEFAULT_MASK0 ================================================== */ + #define R_ETHSW_MCAST_DEFAULT_MASK0_MCASTDM_Pos (0UL) /*!< MCASTDM (Bit 0) */ + #define R_ETHSW_MCAST_DEFAULT_MASK0_MCASTDM_Msk (0xfUL) /*!< MCASTDM (Bitfield-Mask: 0x0f) */ +/* =================================================== INPUT_LEARN_BLOCK =================================================== */ + #define R_ETHSW_INPUT_LEARN_BLOCK_BLOCKEN_Pos (0UL) /*!< BLOCKEN (Bit 0) */ + #define R_ETHSW_INPUT_LEARN_BLOCK_BLOCKEN_Msk (0xfUL) /*!< BLOCKEN (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_INPUT_LEARN_BLOCK_LEARNDIS_Pos (16UL) /*!< LEARNDIS (Bit 16) */ + #define R_ETHSW_INPUT_LEARN_BLOCK_LEARNDIS_Msk (0xf0000UL) /*!< LEARNDIS (Bitfield-Mask: 0x0f) */ +/* ====================================================== MGMT_CONFIG ====================================================== */ + #define R_ETHSW_MGMT_CONFIG_PORT_Pos (0UL) /*!< PORT (Bit 0) */ + #define R_ETHSW_MGMT_CONFIG_PORT_Msk (0xfUL) /*!< PORT (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MGMT_CONFIG_MSG_TRANS_Pos (5UL) /*!< MSG_TRANS (Bit 5) */ + #define R_ETHSW_MGMT_CONFIG_MSG_TRANS_Msk (0x20UL) /*!< MSG_TRANS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_CONFIG_ENABLE_Pos (6UL) /*!< ENABLE (Bit 6) */ + #define R_ETHSW_MGMT_CONFIG_ENABLE_Msk (0x40UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_CONFIG_DISCARD_Pos (7UL) /*!< DISCARD (Bit 7) */ + #define R_ETHSW_MGMT_CONFIG_DISCARD_Msk (0x80UL) /*!< DISCARD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_CONFIG_MGMT_EN_Pos (8UL) /*!< MGMT_EN (Bit 8) */ + #define R_ETHSW_MGMT_CONFIG_MGMT_EN_Msk (0x100UL) /*!< MGMT_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_CONFIG_MGMT_DISC_Pos (9UL) /*!< MGMT_DISC (Bit 9) */ + #define R_ETHSW_MGMT_CONFIG_MGMT_DISC_Msk (0x200UL) /*!< MGMT_DISC (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_CONFIG_PRIORITY_Pos (13UL) /*!< PRIORITY (Bit 13) */ + #define R_ETHSW_MGMT_CONFIG_PRIORITY_Msk (0xe000UL) /*!< PRIORITY (Bitfield-Mask: 0x07) */ + #define R_ETHSW_MGMT_CONFIG_PORTMASK_Pos (16UL) /*!< PORTMASK (Bit 16) */ + #define R_ETHSW_MGMT_CONFIG_PORTMASK_Msk (0xf0000UL) /*!< PORTMASK (Bitfield-Mask: 0x0f) */ +/* ====================================================== MODE_CONFIG ====================================================== */ + #define R_ETHSW_MODE_CONFIG_CUT_THRU_EN_Pos (8UL) /*!< CUT_THRU_EN (Bit 8) */ + #define R_ETHSW_MODE_CONFIG_CUT_THRU_EN_Msk (0xf00UL) /*!< CUT_THRU_EN (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MODE_CONFIG_STATSRESET_Pos (31UL) /*!< STATSRESET (Bit 31) */ + #define R_ETHSW_MODE_CONFIG_STATSRESET_Msk (0x80000000UL) /*!< STATSRESET (Bitfield-Mask: 0x01) */ +/* ===================================================== VLAN_IN_MODE ====================================================== */ + #define R_ETHSW_VLAN_IN_MODE_P0VLANINMD_Pos (0UL) /*!< P0VLANINMD (Bit 0) */ + #define R_ETHSW_VLAN_IN_MODE_P0VLANINMD_Msk (0x3UL) /*!< P0VLANINMD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_VLAN_IN_MODE_P1VLANINMD_Pos (2UL) /*!< P1VLANINMD (Bit 2) */ + #define R_ETHSW_VLAN_IN_MODE_P1VLANINMD_Msk (0xcUL) /*!< P1VLANINMD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_VLAN_IN_MODE_P2VLANINMD_Pos (4UL) /*!< P2VLANINMD (Bit 4) */ + #define R_ETHSW_VLAN_IN_MODE_P2VLANINMD_Msk (0x30UL) /*!< P2VLANINMD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_VLAN_IN_MODE_P3VLANINMD_Pos (6UL) /*!< P3VLANINMD (Bit 6) */ + #define R_ETHSW_VLAN_IN_MODE_P3VLANINMD_Msk (0xc0UL) /*!< P3VLANINMD (Bitfield-Mask: 0x03) */ +/* ===================================================== VLAN_OUT_MODE ===================================================== */ + #define R_ETHSW_VLAN_OUT_MODE_P0VLANOUTMD_Pos (0UL) /*!< P0VLANOUTMD (Bit 0) */ + #define R_ETHSW_VLAN_OUT_MODE_P0VLANOUTMD_Msk (0x3UL) /*!< P0VLANOUTMD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_VLAN_OUT_MODE_P1VLANOUTMD_Pos (2UL) /*!< P1VLANOUTMD (Bit 2) */ + #define R_ETHSW_VLAN_OUT_MODE_P1VLANOUTMD_Msk (0xcUL) /*!< P1VLANOUTMD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_VLAN_OUT_MODE_P2VLANOUTMD_Pos (4UL) /*!< P2VLANOUTMD (Bit 4) */ + #define R_ETHSW_VLAN_OUT_MODE_P2VLANOUTMD_Msk (0x30UL) /*!< P2VLANOUTMD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_VLAN_OUT_MODE_P3VLANOUTMD_Pos (6UL) /*!< P3VLANOUTMD (Bit 6) */ + #define R_ETHSW_VLAN_OUT_MODE_P3VLANOUTMD_Msk (0xc0UL) /*!< P3VLANOUTMD (Bitfield-Mask: 0x03) */ +/* =================================================== VLAN_IN_MODE_ENA ==================================================== */ + #define R_ETHSW_VLAN_IN_MODE_ENA_VLANINMDEN_Pos (0UL) /*!< VLANINMDEN (Bit 0) */ + #define R_ETHSW_VLAN_IN_MODE_ENA_VLANINMDEN_Msk (0xfUL) /*!< VLANINMDEN (Bitfield-Mask: 0x0f) */ +/* ====================================================== VLAN_TAG_ID ====================================================== */ + #define R_ETHSW_VLAN_TAG_ID_VLANTAGID_Pos (0UL) /*!< VLANTAGID (Bit 0) */ + #define R_ETHSW_VLAN_TAG_ID_VLANTAGID_Msk (0xffffUL) /*!< VLANTAGID (Bitfield-Mask: 0xffff) */ +/* =================================================== BCAST_STORM_LIMIT =================================================== */ + #define R_ETHSW_BCAST_STORM_LIMIT_TMOUT_Pos (0UL) /*!< TMOUT (Bit 0) */ + #define R_ETHSW_BCAST_STORM_LIMIT_TMOUT_Msk (0xffffUL) /*!< TMOUT (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_BCAST_STORM_LIMIT_BCASTLIMIT_Pos (16UL) /*!< BCASTLIMIT (Bit 16) */ + #define R_ETHSW_BCAST_STORM_LIMIT_BCASTLIMIT_Msk (0xffff0000UL) /*!< BCASTLIMIT (Bitfield-Mask: 0xffff) */ +/* =================================================== MCAST_STORM_LIMIT =================================================== */ + #define R_ETHSW_MCAST_STORM_LIMIT_MCASTLIMIT_Pos (16UL) /*!< MCASTLIMIT (Bit 16) */ + #define R_ETHSW_MCAST_STORM_LIMIT_MCASTLIMIT_Msk (0xffff0000UL) /*!< MCASTLIMIT (Bitfield-Mask: 0xffff) */ +/* ==================================================== MIRROR_CONTROL ===================================================== */ + #define R_ETHSW_MIRROR_CONTROL_PORT_Pos (0UL) /*!< PORT (Bit 0) */ + #define R_ETHSW_MIRROR_CONTROL_PORT_Msk (0x3UL) /*!< PORT (Bitfield-Mask: 0x03) */ + #define R_ETHSW_MIRROR_CONTROL_MIRROR_EN_Pos (4UL) /*!< MIRROR_EN (Bit 4) */ + #define R_ETHSW_MIRROR_CONTROL_MIRROR_EN_Msk (0x10UL) /*!< MIRROR_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MIRROR_CONTROL_ING_MAP_EN_Pos (5UL) /*!< ING_MAP_EN (Bit 5) */ + #define R_ETHSW_MIRROR_CONTROL_ING_MAP_EN_Msk (0x20UL) /*!< ING_MAP_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MIRROR_CONTROL_EG_MAP_EN_Pos (6UL) /*!< EG_MAP_EN (Bit 6) */ + #define R_ETHSW_MIRROR_CONTROL_EG_MAP_EN_Msk (0x40UL) /*!< EG_MAP_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MIRROR_CONTROL_ING_SA_MATCH_Pos (7UL) /*!< ING_SA_MATCH (Bit 7) */ + #define R_ETHSW_MIRROR_CONTROL_ING_SA_MATCH_Msk (0x80UL) /*!< ING_SA_MATCH (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MIRROR_CONTROL_ING_DA_MATCH_Pos (8UL) /*!< ING_DA_MATCH (Bit 8) */ + #define R_ETHSW_MIRROR_CONTROL_ING_DA_MATCH_Msk (0x100UL) /*!< ING_DA_MATCH (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MIRROR_CONTROL_EG_SA_MATCH_Pos (9UL) /*!< EG_SA_MATCH (Bit 9) */ + #define R_ETHSW_MIRROR_CONTROL_EG_SA_MATCH_Msk (0x200UL) /*!< EG_SA_MATCH (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MIRROR_CONTROL_EG_DA_MATCH_Pos (10UL) /*!< EG_DA_MATCH (Bit 10) */ + #define R_ETHSW_MIRROR_CONTROL_EG_DA_MATCH_Msk (0x400UL) /*!< EG_DA_MATCH (Bitfield-Mask: 0x01) */ +/* ===================================================== MIRROR_EG_MAP ===================================================== */ + #define R_ETHSW_MIRROR_EG_MAP_EMAP_Pos (0UL) /*!< EMAP (Bit 0) */ + #define R_ETHSW_MIRROR_EG_MAP_EMAP_Msk (0xfUL) /*!< EMAP (Bitfield-Mask: 0x0f) */ +/* ==================================================== MIRROR_ING_MAP ===================================================== */ + #define R_ETHSW_MIRROR_ING_MAP_IMAP_Pos (0UL) /*!< IMAP (Bit 0) */ + #define R_ETHSW_MIRROR_ING_MAP_IMAP_Msk (0xfUL) /*!< IMAP (Bitfield-Mask: 0x0f) */ +/* ===================================================== MIRROR_ISRC_0 ===================================================== */ + #define R_ETHSW_MIRROR_ISRC_0_ISRC_Pos (0UL) /*!< ISRC (Bit 0) */ + #define R_ETHSW_MIRROR_ISRC_0_ISRC_Msk (0xffffffffUL) /*!< ISRC (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== MIRROR_ISRC_1 ===================================================== */ + #define R_ETHSW_MIRROR_ISRC_1_ISRC_Pos (0UL) /*!< ISRC (Bit 0) */ + #define R_ETHSW_MIRROR_ISRC_1_ISRC_Msk (0xffffUL) /*!< ISRC (Bitfield-Mask: 0xffff) */ +/* ===================================================== MIRROR_IDST_0 ===================================================== */ + #define R_ETHSW_MIRROR_IDST_0_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_ETHSW_MIRROR_IDST_0_IDST_Msk (0xffffffffUL) /*!< IDST (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== MIRROR_IDST_1 ===================================================== */ + #define R_ETHSW_MIRROR_IDST_1_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_ETHSW_MIRROR_IDST_1_IDST_Msk (0xffffUL) /*!< IDST (Bitfield-Mask: 0xffff) */ +/* ===================================================== MIRROR_ESRC_0 ===================================================== */ + #define R_ETHSW_MIRROR_ESRC_0_ESRC_Pos (0UL) /*!< ESRC (Bit 0) */ + #define R_ETHSW_MIRROR_ESRC_0_ESRC_Msk (0xffffffffUL) /*!< ESRC (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== MIRROR_ESRC_1 ===================================================== */ + #define R_ETHSW_MIRROR_ESRC_1_ESRC_Pos (0UL) /*!< ESRC (Bit 0) */ + #define R_ETHSW_MIRROR_ESRC_1_ESRC_Msk (0xffffUL) /*!< ESRC (Bitfield-Mask: 0xffff) */ +/* ===================================================== MIRROR_EDST_0 ===================================================== */ + #define R_ETHSW_MIRROR_EDST_0_EDST_Pos (0UL) /*!< EDST (Bit 0) */ + #define R_ETHSW_MIRROR_EDST_0_EDST_Msk (0xffffffffUL) /*!< EDST (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== MIRROR_EDST_1 ===================================================== */ + #define R_ETHSW_MIRROR_EDST_1_EDST_Pos (0UL) /*!< EDST (Bit 0) */ + #define R_ETHSW_MIRROR_EDST_1_EDST_Msk (0xffffUL) /*!< EDST (Bitfield-Mask: 0xffff) */ +/* ====================================================== MIRROR_CNT ======================================================= */ + #define R_ETHSW_MIRROR_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ + #define R_ETHSW_MIRROR_CNT_CNT_Msk (0xffUL) /*!< CNT (Bitfield-Mask: 0xff) */ +/* ================================================== UCAST_DEFAULT_MASK1 ================================================== */ + #define R_ETHSW_UCAST_DEFAULT_MASK1_UCASTDM1_Pos (0UL) /*!< UCASTDM1 (Bit 0) */ + #define R_ETHSW_UCAST_DEFAULT_MASK1_UCASTDM1_Msk (0xfUL) /*!< UCASTDM1 (Bitfield-Mask: 0x0f) */ +/* ================================================== BCAST_DEFAULT_MASK1 ================================================== */ + #define R_ETHSW_BCAST_DEFAULT_MASK1_BCASTDM1_Pos (0UL) /*!< BCASTDM1 (Bit 0) */ + #define R_ETHSW_BCAST_DEFAULT_MASK1_BCASTDM1_Msk (0xfUL) /*!< BCASTDM1 (Bitfield-Mask: 0x0f) */ +/* ================================================== MCAST_DEFAULT_MASK1 ================================================== */ + #define R_ETHSW_MCAST_DEFAULT_MASK1_MCASTDM1_Pos (0UL) /*!< MCASTDM1 (Bit 0) */ + #define R_ETHSW_MCAST_DEFAULT_MASK1_MCASTDM1_Msk (0xfUL) /*!< MCASTDM1 (Bitfield-Mask: 0x0f) */ +/* ================================================== PORT_XCAST_MASK_SEL ================================================== */ + #define R_ETHSW_PORT_XCAST_MASK_SEL_MSEL_Pos (0UL) /*!< MSEL (Bit 0) */ + #define R_ETHSW_PORT_XCAST_MASK_SEL_MSEL_Msk (0xfUL) /*!< MSEL (Bitfield-Mask: 0x0f) */ +/* =================================================== QMGR_ST_MINCELLS ==================================================== */ + #define R_ETHSW_QMGR_ST_MINCELLS_STMINCELLS_Pos (0UL) /*!< STMINCELLS (Bit 0) */ + #define R_ETHSW_QMGR_ST_MINCELLS_STMINCELLS_Msk (0x7ffUL) /*!< STMINCELLS (Bitfield-Mask: 0x7ff) */ +/* ===================================================== QMGR_RED_MIN4 ===================================================== */ + #define R_ETHSW_QMGR_RED_MIN4_CFGRED_MINTH4_Pos (0UL) /*!< CFGRED_MINTH4 (Bit 0) */ + #define R_ETHSW_QMGR_RED_MIN4_CFGRED_MINTH4_Msk (0xffffffffUL) /*!< CFGRED_MINTH4 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== QMGR_RED_MAX4 ===================================================== */ + #define R_ETHSW_QMGR_RED_MAX4_CFGRED_MAXTH4_Pos (0UL) /*!< CFGRED_MAXTH4 (Bit 0) */ + #define R_ETHSW_QMGR_RED_MAX4_CFGRED_MAXTH4_Msk (0xffffffffUL) /*!< CFGRED_MAXTH4 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== QMGR_RED_CONFIG ==================================================== */ + #define R_ETHSW_QMGR_RED_CONFIG_QUEUE_RED_EN_Pos (0UL) /*!< QUEUE_RED_EN (Bit 0) */ + #define R_ETHSW_QMGR_RED_CONFIG_QUEUE_RED_EN_Msk (0xfUL) /*!< QUEUE_RED_EN (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_QMGR_RED_CONFIG_GACTIVITY_EN_Pos (8UL) /*!< GACTIVITY_EN (Bit 8) */ + #define R_ETHSW_QMGR_RED_CONFIG_GACTIVITY_EN_Msk (0x100UL) /*!< GACTIVITY_EN (Bitfield-Mask: 0x01) */ +/* ====================================================== IMC_STATUS ======================================================= */ + #define R_ETHSW_IMC_STATUS_CELLS_AVAILABLE_Pos (0UL) /*!< CELLS_AVAILABLE (Bit 0) */ + #define R_ETHSW_IMC_STATUS_CELLS_AVAILABLE_Msk (0xffffffUL) /*!< CELLS_AVAILABLE (Bitfield-Mask: 0xffffff) */ + #define R_ETHSW_IMC_STATUS_CF_ERR_Pos (24UL) /*!< CF_ERR (Bit 24) */ + #define R_ETHSW_IMC_STATUS_CF_ERR_Msk (0x1000000UL) /*!< CF_ERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IMC_STATUS_DE_ERR_Pos (25UL) /*!< DE_ERR (Bit 25) */ + #define R_ETHSW_IMC_STATUS_DE_ERR_Msk (0x2000000UL) /*!< DE_ERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IMC_STATUS_DE_INIT_Pos (26UL) /*!< DE_INIT (Bit 26) */ + #define R_ETHSW_IMC_STATUS_DE_INIT_Msk (0x4000000UL) /*!< DE_INIT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IMC_STATUS_MEM_FULL_Pos (27UL) /*!< MEM_FULL (Bit 27) */ + #define R_ETHSW_IMC_STATUS_MEM_FULL_Msk (0x8000000UL) /*!< MEM_FULL (Bitfield-Mask: 0x01) */ +/* ===================================================== IMC_ERR_FULL ====================================================== */ + #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_FULL_Pos (0UL) /*!< IPC_ERR_FULL (Bit 0) */ + #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_FULL_Msk (0xfUL) /*!< IPC_ERR_FULL (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_TRUNC_Pos (16UL) /*!< IPC_ERR_TRUNC (Bit 16) */ + #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_TRUNC_Msk (0xf0000UL) /*!< IPC_ERR_TRUNC (Bitfield-Mask: 0x0f) */ +/* ===================================================== IMC_ERR_IFACE ===================================================== */ + #define R_ETHSW_IMC_ERR_IFACE_IPC_ERR_IFACE_Pos (0UL) /*!< IPC_ERR_IFACE (Bit 0) */ + #define R_ETHSW_IMC_ERR_IFACE_IPC_ERR_IFACE_Msk (0xfUL) /*!< IPC_ERR_IFACE (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_ERR_IFACE_WBUF_OVF_Pos (16UL) /*!< WBUF_OVF (Bit 16) */ + #define R_ETHSW_IMC_ERR_IFACE_WBUF_OVF_Msk (0xf0000UL) /*!< WBUF_OVF (Bitfield-Mask: 0x0f) */ +/* ==================================================== IMC_ERR_QOFLOW ===================================================== */ + #define R_ETHSW_IMC_ERR_QOFLOW_OP_ERR_Pos (0UL) /*!< OP_ERR (Bit 0) */ + #define R_ETHSW_IMC_ERR_QOFLOW_OP_ERR_Msk (0xfUL) /*!< OP_ERR (Bitfield-Mask: 0x0f) */ +/* ====================================================== IMC_CONFIG ======================================================= */ + #define R_ETHSW_IMC_CONFIG_WFQ_EN_Pos (0UL) /*!< WFQ_EN (Bit 0) */ + #define R_ETHSW_IMC_CONFIG_WFQ_EN_Msk (0x1UL) /*!< WFQ_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IMC_CONFIG_RSV_ENA_Pos (1UL) /*!< RSV_ENA (Bit 1) */ + #define R_ETHSW_IMC_CONFIG_RSV_ENA_Msk (0x2UL) /*!< RSV_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IMC_CONFIG_SPEED_HIPRI_THR_Pos (2UL) /*!< SPEED_HIPRI_THR (Bit 2) */ + #define R_ETHSW_IMC_CONFIG_SPEED_HIPRI_THR_Msk (0x1cUL) /*!< SPEED_HIPRI_THR (Bitfield-Mask: 0x07) */ + #define R_ETHSW_IMC_CONFIG_CTFL_EMPTY_MD_Pos (5UL) /*!< CTFL_EMPTY_MD (Bit 5) */ + #define R_ETHSW_IMC_CONFIG_CTFL_EMPTY_MD_Msk (0x20UL) /*!< CTFL_EMPTY_MD (Bitfield-Mask: 0x01) */ +/* ===================================================== IMC_ERR_ALLOC ===================================================== */ + #define R_ETHSW_IMC_ERR_ALLOC_DISC_FULL_Pos (0UL) /*!< DISC_FULL (Bit 0) */ + #define R_ETHSW_IMC_ERR_ALLOC_DISC_FULL_Msk (0xfUL) /*!< DISC_FULL (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_ERR_ALLOC_DISC_LATE_Pos (16UL) /*!< DISC_LATE (Bit 16) */ + #define R_ETHSW_IMC_ERR_ALLOC_DISC_LATE_Msk (0xf0000UL) /*!< DISC_LATE (Bitfield-Mask: 0x0f) */ +/* ======================================================= GPARSER0 ======================================================== */ + #define R_ETHSW_GPARSER0_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER0_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER0_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER0_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER0_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER0_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER0_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER0_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER0_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER0_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER0_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER0_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER0_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER0_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER0_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER0_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER0_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER0_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER0_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER0_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER0_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER0_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================= GPARSER1 ======================================================== */ + #define R_ETHSW_GPARSER1_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER1_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER1_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER1_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER1_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER1_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER1_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER1_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER1_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER1_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER1_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER1_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER1_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER1_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER1_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER1_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER1_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER1_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER1_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER1_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER1_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER1_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================= GPARSER2 ======================================================== */ + #define R_ETHSW_GPARSER2_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER2_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER2_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER2_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER2_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER2_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER2_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER2_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER2_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER2_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER2_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER2_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER2_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER2_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER2_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER2_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER2_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER2_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER2_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER2_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER2_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER2_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================= GPARSER3 ======================================================== */ + #define R_ETHSW_GPARSER3_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER3_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER3_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER3_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER3_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER3_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER3_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER3_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER3_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER3_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER3_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER3_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER3_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER3_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER3_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER3_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER3_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER3_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER3_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER3_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER3_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER3_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================== GARITH0 ======================================================== */ + #define R_ETHSW_GARITH0_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH0_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH0_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH0_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH0_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH0_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH0_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH0_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH0_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH0_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH0_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH0_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH0_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH0_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH0_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH0_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ======================================================== GARITH1 ======================================================== */ + #define R_ETHSW_GARITH1_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH1_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH1_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH1_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH1_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH1_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH1_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH1_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH1_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH1_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH1_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH1_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH1_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH1_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH1_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH1_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ======================================================== GARITH2 ======================================================== */ + #define R_ETHSW_GARITH2_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH2_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH2_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH2_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH2_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH2_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH2_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH2_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH2_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH2_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH2_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH2_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH2_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH2_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH2_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH2_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ======================================================== GARITH3 ======================================================== */ + #define R_ETHSW_GARITH3_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH3_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH3_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH3_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH3_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH3_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH3_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH3_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH3_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH3_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH3_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH3_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH3_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH3_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH3_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH3_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ======================================================= GPARSER4 ======================================================== */ + #define R_ETHSW_GPARSER4_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER4_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER4_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER4_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER4_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER4_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER4_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER4_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER4_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER4_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER4_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER4_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER4_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER4_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER4_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER4_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER4_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER4_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER4_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER4_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER4_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER4_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================= GPARSER5 ======================================================== */ + #define R_ETHSW_GPARSER5_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER5_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER5_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER5_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER5_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER5_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER5_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER5_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER5_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER5_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER5_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER5_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER5_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER5_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER5_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER5_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER5_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER5_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER5_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER5_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER5_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER5_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================= GPARSER6 ======================================================== */ + #define R_ETHSW_GPARSER6_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER6_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER6_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER6_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER6_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER6_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER6_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER6_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER6_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER6_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER6_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER6_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER6_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER6_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER6_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER6_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER6_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER6_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER6_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER6_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER6_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER6_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================= GPARSER7 ======================================================== */ + #define R_ETHSW_GPARSER7_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER7_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER7_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER7_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER7_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER7_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER7_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER7_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER7_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER7_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER7_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER7_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER7_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER7_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER7_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER7_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER7_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER7_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER7_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER7_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER7_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER7_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================== GARITH4 ======================================================== */ + #define R_ETHSW_GARITH4_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH4_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH4_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH4_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH4_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH4_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH4_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH4_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH4_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH4_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH4_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH4_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH4_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH4_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH4_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH4_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ======================================================== GARITH5 ======================================================== */ + #define R_ETHSW_GARITH5_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH5_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH5_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH5_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH5_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH5_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH5_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH5_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH5_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH5_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH5_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH5_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH5_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH5_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH5_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH5_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ======================================================== GARITH6 ======================================================== */ + #define R_ETHSW_GARITH6_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH6_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH6_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH6_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH6_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH6_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH6_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH6_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH6_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH6_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH6_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH6_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH6_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH6_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH6_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH6_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ======================================================== GARITH7 ======================================================== */ + #define R_ETHSW_GARITH7_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH7_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH7_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH7_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH7_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH7_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH7_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH7_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH7_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH7_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH7_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH7_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH7_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH7_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH7_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH7_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ===================================================== VLAN_PRIORITY ===================================================== */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY0_Pos (0UL) /*!< PRIORITY0 (Bit 0) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY0_Msk (0x7UL) /*!< PRIORITY0 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY1_Pos (3UL) /*!< PRIORITY1 (Bit 3) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY1_Msk (0x38UL) /*!< PRIORITY1 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY2_Pos (6UL) /*!< PRIORITY2 (Bit 6) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY2_Msk (0x1c0UL) /*!< PRIORITY2 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY3_Pos (9UL) /*!< PRIORITY3 (Bit 9) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY3_Msk (0xe00UL) /*!< PRIORITY3 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY4_Pos (12UL) /*!< PRIORITY4 (Bit 12) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY4_Msk (0x7000UL) /*!< PRIORITY4 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY5_Pos (15UL) /*!< PRIORITY5 (Bit 15) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY5_Msk (0x38000UL) /*!< PRIORITY5 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY6_Pos (18UL) /*!< PRIORITY6 (Bit 18) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY6_Msk (0x1c0000UL) /*!< PRIORITY6 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY7_Pos (21UL) /*!< PRIORITY7 (Bit 21) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY7_Msk (0xe00000UL) /*!< PRIORITY7 (Bitfield-Mask: 0x07) */ +/* ====================================================== IP_PRIORITY ====================================================== */ + #define R_ETHSW_IP_PRIORITY_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ + #define R_ETHSW_IP_PRIORITY_ADDRESS_Msk (0xffUL) /*!< ADDRESS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_IP_PRIORITY_IPV6SELECT_Pos (8UL) /*!< IPV6SELECT (Bit 8) */ + #define R_ETHSW_IP_PRIORITY_IPV6SELECT_Msk (0x100UL) /*!< IPV6SELECT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IP_PRIORITY_PRIORITY_Pos (9UL) /*!< PRIORITY (Bit 9) */ + #define R_ETHSW_IP_PRIORITY_PRIORITY_Msk (0xe00UL) /*!< PRIORITY (Bitfield-Mask: 0x07) */ + #define R_ETHSW_IP_PRIORITY_READ_Pos (31UL) /*!< READ (Bit 31) */ + #define R_ETHSW_IP_PRIORITY_READ_Msk (0x80000000UL) /*!< READ (Bitfield-Mask: 0x01) */ +/* ===================================================== PRIORITY_CFG ====================================================== */ + #define R_ETHSW_PRIORITY_CFG_VLANEN_Pos (0UL) /*!< VLANEN (Bit 0) */ + #define R_ETHSW_PRIORITY_CFG_VLANEN_Msk (0x1UL) /*!< VLANEN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRIORITY_CFG_IPEN_Pos (1UL) /*!< IPEN (Bit 1) */ + #define R_ETHSW_PRIORITY_CFG_IPEN_Msk (0x2UL) /*!< IPEN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRIORITY_CFG_MACEN_Pos (2UL) /*!< MACEN (Bit 2) */ + #define R_ETHSW_PRIORITY_CFG_MACEN_Msk (0x4UL) /*!< MACEN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRIORITY_CFG_TYPE_EN_Pos (3UL) /*!< TYPE_EN (Bit 3) */ + #define R_ETHSW_PRIORITY_CFG_TYPE_EN_Msk (0x8UL) /*!< TYPE_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRIORITY_CFG_DEFAULTPRI_Pos (4UL) /*!< DEFAULTPRI (Bit 4) */ + #define R_ETHSW_PRIORITY_CFG_DEFAULTPRI_Msk (0x70UL) /*!< DEFAULTPRI (Bitfield-Mask: 0x07) */ +/* ==================================================== PRIORITY_TYPE1 ===================================================== */ + #define R_ETHSW_PRIORITY_TYPE1_TYPEVAL_Pos (0UL) /*!< TYPEVAL (Bit 0) */ + #define R_ETHSW_PRIORITY_TYPE1_TYPEVAL_Msk (0xffffUL) /*!< TYPEVAL (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_PRIORITY_TYPE1_VALID_Pos (16UL) /*!< VALID (Bit 16) */ + #define R_ETHSW_PRIORITY_TYPE1_VALID_Msk (0x10000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRIORITY_TYPE1_PRIORITY_Pos (17UL) /*!< PRIORITY (Bit 17) */ + #define R_ETHSW_PRIORITY_TYPE1_PRIORITY_Msk (0xe0000UL) /*!< PRIORITY (Bitfield-Mask: 0x07) */ +/* ==================================================== PRIORITY_TYPE2 ===================================================== */ + #define R_ETHSW_PRIORITY_TYPE2_TYPEVAL_Pos (0UL) /*!< TYPEVAL (Bit 0) */ + #define R_ETHSW_PRIORITY_TYPE2_TYPEVAL_Msk (0xffffUL) /*!< TYPEVAL (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_PRIORITY_TYPE2_VALID_Pos (16UL) /*!< VALID (Bit 16) */ + #define R_ETHSW_PRIORITY_TYPE2_VALID_Msk (0x10000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRIORITY_TYPE2_PRIORITY_Pos (17UL) /*!< PRIORITY (Bit 17) */ + #define R_ETHSW_PRIORITY_TYPE2_PRIORITY_Msk (0xe0000UL) /*!< PRIORITY (Bitfield-Mask: 0x07) */ +/* ====================================================== SRCFLT_ENA ======================================================= */ + #define R_ETHSW_SRCFLT_ENA_SRCENA_Pos (0UL) /*!< SRCENA (Bit 0) */ + #define R_ETHSW_SRCFLT_ENA_SRCENA_Msk (0x7UL) /*!< SRCENA (Bitfield-Mask: 0x07) */ + #define R_ETHSW_SRCFLT_ENA_DSTENA_Pos (16UL) /*!< DSTENA (Bit 16) */ + #define R_ETHSW_SRCFLT_ENA_DSTENA_Msk (0xf0000UL) /*!< DSTENA (Bitfield-Mask: 0x0f) */ +/* ==================================================== SRCFLT_CONTROL ===================================================== */ + #define R_ETHSW_SRCFLT_CONTROL_MGMT_FWD_Pos (0UL) /*!< MGMT_FWD (Bit 0) */ + #define R_ETHSW_SRCFLT_CONTROL_MGMT_FWD_Msk (0x1UL) /*!< MGMT_FWD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_ENA_Pos (1UL) /*!< WATCHDOG_ENA (Bit 1) */ + #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_ENA_Msk (0x2UL) /*!< WATCHDOG_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_TIME_Pos (16UL) /*!< WATCHDOG_TIME (Bit 16) */ + #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_TIME_Msk (0xffff0000UL) /*!< WATCHDOG_TIME (Bitfield-Mask: 0xffff) */ +/* =================================================== SRCFLT_MACADDR_LO =================================================== */ + #define R_ETHSW_SRCFLT_MACADDR_LO_SRCFLT_MACADDR_Pos (0UL) /*!< SRCFLT_MACADDR (Bit 0) */ + #define R_ETHSW_SRCFLT_MACADDR_LO_SRCFLT_MACADDR_Msk (0xffffffffUL) /*!< SRCFLT_MACADDR (Bitfield-Mask: 0xffffffff) */ +/* =================================================== SRCFLT_MACADDR_HI =================================================== */ + #define R_ETHSW_SRCFLT_MACADDR_HI_SRCFLT_MACADDR_Pos (0UL) /*!< SRCFLT_MACADDR (Bit 0) */ + #define R_ETHSW_SRCFLT_MACADDR_HI_SRCFLT_MACADDR_Msk (0xffffUL) /*!< SRCFLT_MACADDR (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_SRCFLT_MACADDR_HI_MASK_Pos (16UL) /*!< MASK (Bit 16) */ + #define R_ETHSW_SRCFLT_MACADDR_HI_MASK_Msk (0xffff0000UL) /*!< MASK (Bitfield-Mask: 0xffff) */ +/* ==================================================== PHY_FILTER_CFG ===================================================== */ + #define R_ETHSW_PHY_FILTER_CFG_FILTER_DURATION_Pos (0UL) /*!< FILTER_DURATION (Bit 0) */ + #define R_ETHSW_PHY_FILTER_CFG_FILTER_DURATION_Msk (0x1ffUL) /*!< FILTER_DURATION (Bitfield-Mask: 0x1ff) */ + #define R_ETHSW_PHY_FILTER_CFG_FLT_EN_Pos (16UL) /*!< FLT_EN (Bit 16) */ + #define R_ETHSW_PHY_FILTER_CFG_FLT_EN_Msk (0x70000UL) /*!< FLT_EN (Bitfield-Mask: 0x07) */ +/* ==================================================== SYSTEM_TAGINFO ===================================================== */ + #define R_ETHSW_SYSTEM_TAGINFO_SYSVLANINFO_Pos (0UL) /*!< SYSVLANINFO (Bit 0) */ + #define R_ETHSW_SYSTEM_TAGINFO_SYSVLANINFO_Msk (0xffffUL) /*!< SYSVLANINFO (Bitfield-Mask: 0xffff) */ +/* ======================================================= AUTH_PORT ======================================================= */ + #define R_ETHSW_AUTH_PORT_AUTH_Pos (0UL) /*!< AUTH (Bit 0) */ + #define R_ETHSW_AUTH_PORT_AUTH_Msk (0x1UL) /*!< AUTH (Bitfield-Mask: 0x01) */ + #define R_ETHSW_AUTH_PORT_CTRL_BOTH_Pos (1UL) /*!< CTRL_BOTH (Bit 1) */ + #define R_ETHSW_AUTH_PORT_CTRL_BOTH_Msk (0x2UL) /*!< CTRL_BOTH (Bitfield-Mask: 0x01) */ + #define R_ETHSW_AUTH_PORT_EAPOL_EN_Pos (2UL) /*!< EAPOL_EN (Bit 2) */ + #define R_ETHSW_AUTH_PORT_EAPOL_EN_Msk (0x4UL) /*!< EAPOL_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_AUTH_PORT_GUEST_EN_Pos (3UL) /*!< GUEST_EN (Bit 3) */ + #define R_ETHSW_AUTH_PORT_GUEST_EN_Msk (0x8UL) /*!< GUEST_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_AUTH_PORT_BPDU_EN_Pos (4UL) /*!< BPDU_EN (Bit 4) */ + #define R_ETHSW_AUTH_PORT_BPDU_EN_Msk (0x10UL) /*!< BPDU_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_AUTH_PORT_EAPOL_UC_EN_Pos (5UL) /*!< EAPOL_UC_EN (Bit 5) */ + #define R_ETHSW_AUTH_PORT_EAPOL_UC_EN_Msk (0x20UL) /*!< EAPOL_UC_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_AUTH_PORT_ACHG_UNAUTH_Pos (11UL) /*!< ACHG_UNAUTH (Bit 11) */ + #define R_ETHSW_AUTH_PORT_ACHG_UNAUTH_Msk (0x800UL) /*!< ACHG_UNAUTH (Bitfield-Mask: 0x01) */ + #define R_ETHSW_AUTH_PORT_EAPOL_PNUM_Pos (12UL) /*!< EAPOL_PNUM (Bit 12) */ + #define R_ETHSW_AUTH_PORT_EAPOL_PNUM_Msk (0xf000UL) /*!< EAPOL_PNUM (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_AUTH_PORT_GUEST_MASK_Pos (16UL) /*!< GUEST_MASK (Bit 16) */ + #define R_ETHSW_AUTH_PORT_GUEST_MASK_Msk (0xf0000UL) /*!< GUEST_MASK (Bitfield-Mask: 0x0f) */ +/* ==================================================== VLAN_RES_TABLE ===================================================== */ + #define R_ETHSW_VLAN_RES_TABLE_PORTMASK_Pos (0UL) /*!< PORTMASK (Bit 0) */ + #define R_ETHSW_VLAN_RES_TABLE_PORTMASK_Msk (0xfUL) /*!< PORTMASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_VLAN_RES_TABLE_VLANID_Pos (4UL) /*!< VLANID (Bit 4) */ + #define R_ETHSW_VLAN_RES_TABLE_VLANID_Msk (0xfff0UL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_VLAN_RES_TABLE_RD_TAGMSK_Pos (28UL) /*!< RD_TAGMSK (Bit 28) */ + #define R_ETHSW_VLAN_RES_TABLE_RD_TAGMSK_Msk (0x10000000UL) /*!< RD_TAGMSK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_VLAN_RES_TABLE_WT_TAGMSK_Pos (29UL) /*!< WT_TAGMSK (Bit 29) */ + #define R_ETHSW_VLAN_RES_TABLE_WT_TAGMSK_Msk (0x20000000UL) /*!< WT_TAGMSK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_VLAN_RES_TABLE_WT_PRTMSK_Pos (30UL) /*!< WT_PRTMSK (Bit 30) */ + #define R_ETHSW_VLAN_RES_TABLE_WT_PRTMSK_Msk (0x40000000UL) /*!< WT_PRTMSK (Bitfield-Mask: 0x01) */ +/* ====================================================== TOTAL_DISC ======================================================= */ + #define R_ETHSW_TOTAL_DISC_TOTAL_DISC_Pos (0UL) /*!< TOTAL_DISC (Bit 0) */ + #define R_ETHSW_TOTAL_DISC_TOTAL_DISC_Msk (0xffffffffUL) /*!< TOTAL_DISC (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== TOTAL_BYT_DISC ===================================================== */ + #define R_ETHSW_TOTAL_BYT_DISC_TOTAL_BYT_DISC_Pos (0UL) /*!< TOTAL_BYT_DISC (Bit 0) */ + #define R_ETHSW_TOTAL_BYT_DISC_TOTAL_BYT_DISC_Msk (0xffffffffUL) /*!< TOTAL_BYT_DISC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TOTAL_FRM ======================================================= */ + #define R_ETHSW_TOTAL_FRM_TOTAL_FRM_Pos (0UL) /*!< TOTAL_FRM (Bit 0) */ + #define R_ETHSW_TOTAL_FRM_TOTAL_FRM_Msk (0xffffffffUL) /*!< TOTAL_FRM (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== TOTAL_BYT_FRM ===================================================== */ + #define R_ETHSW_TOTAL_BYT_FRM_TOTAL_BYT_FRM_Pos (0UL) /*!< TOTAL_BYT_FRM (Bit 0) */ + #define R_ETHSW_TOTAL_BYT_FRM_TOTAL_BYT_FRM_Msk (0xffffffffUL) /*!< TOTAL_BYT_FRM (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IALK_CONTROL ====================================================== */ + #define R_ETHSW_IALK_CONTROL_IA_LKUP_ENA_Pos (0UL) /*!< IA_LKUP_ENA (Bit 0) */ + #define R_ETHSW_IALK_CONTROL_IA_LKUP_ENA_Msk (0xfUL) /*!< IA_LKUP_ENA (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IALK_CONTROL_CT_ENA_Pos (16UL) /*!< CT_ENA (Bit 16) */ + #define R_ETHSW_IALK_CONTROL_CT_ENA_Msk (0xf0000UL) /*!< CT_ENA (Bitfield-Mask: 0x0f) */ +/* ======================================================= IALK_OUI ======================================================== */ + #define R_ETHSW_IALK_OUI_IALK_OUI_Pos (0UL) /*!< IALK_OUI (Bit 0) */ + #define R_ETHSW_IALK_OUI_IALK_OUI_Msk (0xffffffUL) /*!< IALK_OUI (Bitfield-Mask: 0xffffff) */ +/* ====================================================== IALK_ID_MIN ====================================================== */ + #define R_ETHSW_IALK_ID_MIN_IALK_ID_MIN_Pos (0UL) /*!< IALK_ID_MIN (Bit 0) */ + #define R_ETHSW_IALK_ID_MIN_IALK_ID_MIN_Msk (0xffffffUL) /*!< IALK_ID_MIN (Bitfield-Mask: 0xffffff) */ +/* ====================================================== IALK_ID_MAX ====================================================== */ + #define R_ETHSW_IALK_ID_MAX_IALK_ID_MAX_Pos (0UL) /*!< IALK_ID_MAX (Bit 0) */ + #define R_ETHSW_IALK_ID_MAX_IALK_ID_MAX_Msk (0xffffffUL) /*!< IALK_ID_MAX (Bitfield-Mask: 0xffffff) */ +/* ====================================================== IALK_ID_SUB ====================================================== */ + #define R_ETHSW_IALK_ID_SUB_IALK_ID_SUB_Pos (0UL) /*!< IALK_ID_SUB (Bit 0) */ + #define R_ETHSW_IALK_ID_SUB_IALK_ID_SUB_Msk (0xffffffUL) /*!< IALK_ID_SUB (Bitfield-Mask: 0xffffff) */ +/* ==================================================== IALK_ID_CONFIG ===================================================== */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_Pos (0UL) /*!< INVLD_ID_FLOOD (Bit 0) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_Msk (0x1UL) /*!< INVLD_ID_FLOOD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_LRN_ENA_Pos (1UL) /*!< INVLD_ID_LRN_ENA (Bit 1) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_LRN_ENA_Msk (0x2UL) /*!< INVLD_ID_LRN_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_Pos (4UL) /*!< INVLD_ID_PRIO (Bit 4) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_Msk (0x70UL) /*!< INVLD_ID_PRIO (Bitfield-Mask: 0x07) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_VLD_Pos (7UL) /*!< INVLD_ID_PRIO_VLD (Bit 7) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_VLD_Msk (0x80UL) /*!< INVLD_ID_PRIO_VLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_MASK_Pos (16UL) /*!< INVLD_ID_FLOOD_MASK (Bit 16) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_MASK_Msk (0xf0000UL) /*!< INVLD_ID_FLOOD_MASK (Bitfield-Mask: 0x0f) */ +/* =================================================== IALK_VLAN_CONFIG ==================================================== */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_Pos (0UL) /*!< UNKWN_VLAN_FLOOD (Bit 0) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_Msk (0x1UL) /*!< UNKWN_VLAN_FLOOD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_LRN_ENA_Pos (1UL) /*!< UNKWN_VLAN_LRN_ENA (Bit 1) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_LRN_ENA_Msk (0x2UL) /*!< UNKWN_VLAN_LRN_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_Pos (4UL) /*!< UNKWN_VLAN_PRIO (Bit 4) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_Msk (0x70UL) /*!< UNKWN_VLAN_PRIO (Bitfield-Mask: 0x07) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_VLD_Pos (7UL) /*!< UNKWN_VLAN_PRIO_VLD (Bit 7) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_VLD_Msk (0x80UL) /*!< UNKWN_VLAN_PRIO_VLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_VLAN_CONFIG_VLANS_ENABLED_Pos (8UL) /*!< VLANS_ENABLED (Bit 8) */ + #define R_ETHSW_IALK_VLAN_CONFIG_VLANS_ENABLED_Msk (0x700UL) /*!< VLANS_ENABLED (Bitfield-Mask: 0x07) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_MASK_Pos (16UL) /*!< UNKWN_VLAN_FLOOD_MASK (Bit 16) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_MASK_Msk (0xf0000UL) /*!< UNKWN_VLAN_FLOOD_MASK (Bitfield-Mask: 0x0f) */ +/* ===================================================== IALK_TBL_ADDR ===================================================== */ + #define R_ETHSW_IALK_TBL_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ETHSW_IALK_TBL_ADDR_ADDR_Msk (0x1fffUL) /*!< ADDR (Bitfield-Mask: 0x1fff) */ + #define R_ETHSW_IALK_TBL_ADDR_AINC_Pos (28UL) /*!< AINC (Bit 28) */ + #define R_ETHSW_IALK_TBL_ADDR_AINC_Msk (0xf0000000UL) /*!< AINC (Bitfield-Mask: 0x0f) */ +/* ===================================================== IALK_TBL_DATA ===================================================== */ + #define R_ETHSW_IALK_TBL_DATA_VALID_Pos (0UL) /*!< VALID (Bit 0) */ + #define R_ETHSW_IALK_TBL_DATA_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_TBL_DATA_FWD_MASK_Pos (1UL) /*!< FWD_MASK (Bit 1) */ + #define R_ETHSW_IALK_TBL_DATA_FWD_MASK_Msk (0x1eUL) /*!< FWD_MASK (Bitfield-Mask: 0x0f) */ +/* ====================================================== IALK_VLANID ====================================================== */ + #define R_ETHSW_IALK_VLANID_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_IALK_VLANID_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_IALK_VLANID_VLANID_ENA_Pos (12UL) /*!< VLANID_ENA (Bit 12) */ + #define R_ETHSW_IALK_VLANID_VLANID_ENA_Msk (0x1000UL) /*!< VLANID_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_VLANID_VLANID_LRN_ENA_Pos (13UL) /*!< VLANID_LRN_ENA (Bit 13) */ + #define R_ETHSW_IALK_VLANID_VLANID_LRN_ENA_Msk (0x2000UL) /*!< VLANID_LRN_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_VLANID_VLANID_FLOOD_MASK_Pos (16UL) /*!< VLANID_FLOOD_MASK (Bit 16) */ + #define R_ETHSW_IALK_VLANID_VLANID_FLOOD_MASK_Msk (0xf0000UL) /*!< VLANID_FLOOD_MASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IALK_VLANID_VLANID_PRIO_Pos (28UL) /*!< VLANID_PRIO (Bit 28) */ + #define R_ETHSW_IALK_VLANID_VLANID_PRIO_Msk (0x70000000UL) /*!< VLANID_PRIO (Bitfield-Mask: 0x07) */ + #define R_ETHSW_IALK_VLANID_VLANID_PRIO_VLD_Pos (31UL) /*!< VLANID_PRIO_VLD (Bit 31) */ + #define R_ETHSW_IALK_VLANID_VLANID_PRIO_VLD_Msk (0x80000000UL) /*!< VLANID_PRIO_VLD (Bitfield-Mask: 0x01) */ +/* ===================================================== IMC_QLEVEL_P ====================================================== */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE0_Pos (0UL) /*!< QUEUE0 (Bit 0) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE0_Msk (0xfUL) /*!< QUEUE0 (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE1_Pos (4UL) /*!< QUEUE1 (Bit 4) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE1_Msk (0xf0UL) /*!< QUEUE1 (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE2_Pos (8UL) /*!< QUEUE2 (Bit 8) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE2_Msk (0xf00UL) /*!< QUEUE2 (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE3_Pos (12UL) /*!< QUEUE3 (Bit 12) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE3_Msk (0xf000UL) /*!< QUEUE3 (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE4_Pos (16UL) /*!< QUEUE4 (Bit 16) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE4_Msk (0xf0000UL) /*!< QUEUE4 (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE5_Pos (20UL) /*!< QUEUE5 (Bit 20) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE5_Msk (0xf00000UL) /*!< QUEUE5 (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE6_Pos (24UL) /*!< QUEUE6 (Bit 24) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE6_Msk (0xf000000UL) /*!< QUEUE6 (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE7_Pos (28UL) /*!< QUEUE7 (Bit 28) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE7_Msk (0xf0000000UL) /*!< QUEUE7 (Bitfield-Mask: 0x0f) */ +/* ======================================================== LK_CTRL ======================================================== */ + #define R_ETHSW_LK_CTRL_LKUP_EN_Pos (0UL) /*!< LKUP_EN (Bit 0) */ + #define R_ETHSW_LK_CTRL_LKUP_EN_Msk (0x1UL) /*!< LKUP_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_CTRL_LEARN_EN_Pos (1UL) /*!< LEARN_EN (Bit 1) */ + #define R_ETHSW_LK_CTRL_LEARN_EN_Msk (0x2UL) /*!< LEARN_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_CTRL_AGING_EN_Pos (2UL) /*!< AGING_EN (Bit 2) */ + #define R_ETHSW_LK_CTRL_AGING_EN_Msk (0x4UL) /*!< AGING_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_CTRL_ALW_MGRT_Pos (3UL) /*!< ALW_MGRT (Bit 3) */ + #define R_ETHSW_LK_CTRL_ALW_MGRT_Msk (0x8UL) /*!< ALW_MGRT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_CTRL_DISC_UNK_DEST_Pos (4UL) /*!< DISC_UNK_DEST (Bit 4) */ + #define R_ETHSW_LK_CTRL_DISC_UNK_DEST_Msk (0x10UL) /*!< DISC_UNK_DEST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_CTRL_CLRTBL_Pos (6UL) /*!< CLRTBL (Bit 6) */ + #define R_ETHSW_LK_CTRL_CLRTBL_Msk (0x40UL) /*!< CLRTBL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_CTRL_IND_VLAN_Pos (7UL) /*!< IND_VLAN (Bit 7) */ + #define R_ETHSW_LK_CTRL_IND_VLAN_Msk (0x80UL) /*!< IND_VLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_CTRL_DISC_UNK_SRC_Pos (16UL) /*!< DISC_UNK_SRC (Bit 16) */ + #define R_ETHSW_LK_CTRL_DISC_UNK_SRC_Msk (0xf0000UL) /*!< DISC_UNK_SRC (Bitfield-Mask: 0x0f) */ +/* ======================================================= LK_STATUS ======================================================= */ + #define R_ETHSW_LK_STATUS_AGEADDR_Pos (0UL) /*!< AGEADDR (Bit 0) */ + #define R_ETHSW_LK_STATUS_AGEADDR_Msk (0xffffUL) /*!< AGEADDR (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_LK_STATUS_OVRF_Pos (16UL) /*!< OVRF (Bit 16) */ + #define R_ETHSW_LK_STATUS_OVRF_Msk (0x3fff0000UL) /*!< OVRF (Bitfield-Mask: 0x3fff) */ + #define R_ETHSW_LK_STATUS_LRNEVNT_Pos (31UL) /*!< LRNEVNT (Bit 31) */ + #define R_ETHSW_LK_STATUS_LRNEVNT_Msk (0x80000000UL) /*!< LRNEVNT (Bitfield-Mask: 0x01) */ +/* ===================================================== LK_ADDR_CTRL ====================================================== */ + #define R_ETHSW_LK_ADDR_CTRL_ADDR_MSK_Pos (0UL) /*!< ADDR_MSK (Bit 0) */ + #define R_ETHSW_LK_ADDR_CTRL_ADDR_MSK_Msk (0xfffUL) /*!< ADDR_MSK (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_LK_ADDR_CTRL_CLR_DYNAMIC_Pos (22UL) /*!< CLR_DYNAMIC (Bit 22) */ + #define R_ETHSW_LK_ADDR_CTRL_CLR_DYNAMIC_Msk (0x400000UL) /*!< CLR_DYNAMIC (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_CLR_STATIC_Pos (23UL) /*!< CLR_STATIC (Bit 23) */ + #define R_ETHSW_LK_ADDR_CTRL_CLR_STATIC_Msk (0x800000UL) /*!< CLR_STATIC (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_GETLASTNEW_Pos (24UL) /*!< GETLASTNEW (Bit 24) */ + #define R_ETHSW_LK_ADDR_CTRL_GETLASTNEW_Msk (0x1000000UL) /*!< GETLASTNEW (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_WRITE_Pos (25UL) /*!< WRITE (Bit 25) */ + #define R_ETHSW_LK_ADDR_CTRL_WRITE_Msk (0x2000000UL) /*!< WRITE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_READ_Pos (26UL) /*!< READ (Bit 26) */ + #define R_ETHSW_LK_ADDR_CTRL_READ_Msk (0x4000000UL) /*!< READ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_WAIT_COMP_Pos (27UL) /*!< WAIT_COMP (Bit 27) */ + #define R_ETHSW_LK_ADDR_CTRL_WAIT_COMP_Msk (0x8000000UL) /*!< WAIT_COMP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_LOOKUP_Pos (28UL) /*!< LOOKUP (Bit 28) */ + #define R_ETHSW_LK_ADDR_CTRL_LOOKUP_Msk (0x10000000UL) /*!< LOOKUP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_CLEAR_Pos (29UL) /*!< CLEAR (Bit 29) */ + #define R_ETHSW_LK_ADDR_CTRL_CLEAR_Msk (0x20000000UL) /*!< CLEAR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_DEL_PORT_Pos (30UL) /*!< DEL_PORT (Bit 30) */ + #define R_ETHSW_LK_ADDR_CTRL_DEL_PORT_Msk (0x40000000UL) /*!< DEL_PORT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_BUSY_Pos (31UL) /*!< BUSY (Bit 31) */ + #define R_ETHSW_LK_ADDR_CTRL_BUSY_Msk (0x80000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ====================================================== LK_DATA_LO ======================================================= */ + #define R_ETHSW_LK_DATA_LO_MEMDATA_Pos (0UL) /*!< MEMDATA (Bit 0) */ + #define R_ETHSW_LK_DATA_LO_MEMDATA_Msk (0xffffffffUL) /*!< MEMDATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== LK_DATA_HI ======================================================= */ + #define R_ETHSW_LK_DATA_HI_MEMDATA_Pos (0UL) /*!< MEMDATA (Bit 0) */ + #define R_ETHSW_LK_DATA_HI_MEMDATA_Msk (0x1ffffffUL) /*!< MEMDATA (Bitfield-Mask: 0x1ffffff) */ +/* ====================================================== LK_DATA_HI2 ====================================================== */ + #define R_ETHSW_LK_DATA_HI2_MEMDATA_Pos (8UL) /*!< MEMDATA (Bit 8) */ + #define R_ETHSW_LK_DATA_HI2_MEMDATA_Msk (0xfff00UL) /*!< MEMDATA (Bitfield-Mask: 0xfff) */ +/* ===================================================== LK_LEARNCOUNT ===================================================== */ + #define R_ETHSW_LK_LEARNCOUNT_LEARNCOUNT_Pos (0UL) /*!< LEARNCOUNT (Bit 0) */ + #define R_ETHSW_LK_LEARNCOUNT_LEARNCOUNT_Msk (0x1fffUL) /*!< LEARNCOUNT (Bitfield-Mask: 0x1fff) */ + #define R_ETHSW_LK_LEARNCOUNT_WRITE_MD_Pos (30UL) /*!< WRITE_MD (Bit 30) */ + #define R_ETHSW_LK_LEARNCOUNT_WRITE_MD_Msk (0xc0000000UL) /*!< WRITE_MD (Bitfield-Mask: 0x03) */ +/* ====================================================== LK_AGETIME ======================================================= */ + #define R_ETHSW_LK_AGETIME_AGETIME_Pos (0UL) /*!< AGETIME (Bit 0) */ + #define R_ETHSW_LK_AGETIME_AGETIME_Msk (0xffffffUL) /*!< AGETIME (Bitfield-Mask: 0xffffff) */ +/* ==================================================== MGMT_TAG_CONFIG ==================================================== */ + #define R_ETHSW_MGMT_TAG_CONFIG_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_ETHSW_MGMT_TAG_CONFIG_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_TAG_CONFIG_AL_FRAMES_Pos (1UL) /*!< AL_FRAMES (Bit 1) */ + #define R_ETHSW_MGMT_TAG_CONFIG_AL_FRAMES_Msk (0x2UL) /*!< AL_FRAMES (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_TAG_CONFIG_TYPE1_EN_Pos (4UL) /*!< TYPE1_EN (Bit 4) */ + #define R_ETHSW_MGMT_TAG_CONFIG_TYPE1_EN_Msk (0x10UL) /*!< TYPE1_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_TAG_CONFIG_TYPE2_EN_Pos (5UL) /*!< TYPE2_EN (Bit 5) */ + #define R_ETHSW_MGMT_TAG_CONFIG_TYPE2_EN_Msk (0x20UL) /*!< TYPE2_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_TAG_CONFIG_TAGFIELD_Pos (16UL) /*!< TAGFIELD (Bit 16) */ + #define R_ETHSW_MGMT_TAG_CONFIG_TAGFIELD_Msk (0xffff0000UL) /*!< TAGFIELD (Bitfield-Mask: 0xffff) */ +/* ====================================================== TSM_CONFIG ======================================================= */ + #define R_ETHSW_TSM_CONFIG_IRQ_EN_Pos (0UL) /*!< IRQ_EN (Bit 0) */ + #define R_ETHSW_TSM_CONFIG_IRQ_EN_Msk (0x1UL) /*!< IRQ_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TSM_CONFIG_IRQ_TEST_Pos (1UL) /*!< IRQ_TEST (Bit 1) */ + #define R_ETHSW_TSM_CONFIG_IRQ_TEST_Msk (0x2UL) /*!< IRQ_TEST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TSM_CONFIG_IRQ_TSFIFO_OVR_Pos (2UL) /*!< IRQ_TSFIFO_OVR (Bit 2) */ + #define R_ETHSW_TSM_CONFIG_IRQ_TSFIFO_OVR_Msk (0x4UL) /*!< IRQ_TSFIFO_OVR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TSM_CONFIG_IRQ_EVT_OFFSET_Pos (4UL) /*!< IRQ_EVT_OFFSET (Bit 4) */ + #define R_ETHSW_TSM_CONFIG_IRQ_EVT_OFFSET_Msk (0x30UL) /*!< IRQ_EVT_OFFSET (Bitfield-Mask: 0x03) */ + #define R_ETHSW_TSM_CONFIG_IRQ_EVT_PERIOD_Pos (8UL) /*!< IRQ_EVT_PERIOD (Bit 8) */ + #define R_ETHSW_TSM_CONFIG_IRQ_EVT_PERIOD_Msk (0x300UL) /*!< IRQ_EVT_PERIOD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_TSM_CONFIG_IRQ_ATIME_OVER_Pos (12UL) /*!< IRQ_ATIME_OVER (Bit 12) */ + #define R_ETHSW_TSM_CONFIG_IRQ_ATIME_OVER_Msk (0x3000UL) /*!< IRQ_ATIME_OVER (Bitfield-Mask: 0x03) */ + #define R_ETHSW_TSM_CONFIG_IRQ_TX_EN_Pos (16UL) /*!< IRQ_TX_EN (Bit 16) */ + #define R_ETHSW_TSM_CONFIG_IRQ_TX_EN_Msk (0xf0000UL) /*!< IRQ_TX_EN (Bitfield-Mask: 0x0f) */ +/* =================================================== TSM_IRQ_STAT_ACK ==================================================== */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_STAT_Pos (0UL) /*!< IRQ_STAT (Bit 0) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_STAT_Msk (0x1UL) /*!< IRQ_STAT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TEST_Pos (1UL) /*!< IRQ_TEST (Bit 1) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TEST_Msk (0x2UL) /*!< IRQ_TEST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TSFIFO_OVR_Pos (2UL) /*!< IRQ_TSFIFO_OVR (Bit 2) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TSFIFO_OVR_Msk (0x4UL) /*!< IRQ_TSFIFO_OVR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_OFFSET_Pos (4UL) /*!< IRQ_EVT_OFFSET (Bit 4) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_OFFSET_Msk (0x30UL) /*!< IRQ_EVT_OFFSET (Bitfield-Mask: 0x03) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_PERIOD_Pos (8UL) /*!< IRQ_EVT_PERIOD (Bit 8) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_PERIOD_Msk (0x300UL) /*!< IRQ_EVT_PERIOD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_ATIME_OVER_Pos (12UL) /*!< IRQ_ATIME_OVER (Bit 12) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_ATIME_OVER_Msk (0x3000UL) /*!< IRQ_ATIME_OVER (Bitfield-Mask: 0x03) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TX_Pos (16UL) /*!< IRQ_TX (Bit 16) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TX_Msk (0xf0000UL) /*!< IRQ_TX (Bitfield-Mask: 0x0f) */ +/* ====================================================== PTP_DOMAIN ======================================================= */ + #define R_ETHSW_PTP_DOMAIN_DOMAIN0_Pos (0UL) /*!< DOMAIN0 (Bit 0) */ + #define R_ETHSW_PTP_DOMAIN_DOMAIN0_Msk (0xffUL) /*!< DOMAIN0 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTP_DOMAIN_DOMAIN1_Pos (8UL) /*!< DOMAIN1 (Bit 8) */ + #define R_ETHSW_PTP_DOMAIN_DOMAIN1_Msk (0xff00UL) /*!< DOMAIN1 (Bitfield-Mask: 0xff) */ +/* ==================================================== PEERDELAY_P0_T0 ==================================================== */ + #define R_ETHSW_PEERDELAY_P0_T0_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P0_T0_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== PEERDELAY_P1_T0 ==================================================== */ + #define R_ETHSW_PEERDELAY_P1_T0_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P1_T0_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== PEERDELAY_P2_T0 ==================================================== */ + #define R_ETHSW_PEERDELAY_P2_T0_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P2_T0_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== PEERDELAY_P3_T0 ==================================================== */ + #define R_ETHSW_PEERDELAY_P3_T0_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P3_T0_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== PEERDELAY_P0_T1 ==================================================== */ + #define R_ETHSW_PEERDELAY_P0_T1_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P0_T1_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== PEERDELAY_P1_T1 ==================================================== */ + #define R_ETHSW_PEERDELAY_P1_T1_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P1_T1_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== PEERDELAY_P2_T1 ==================================================== */ + #define R_ETHSW_PEERDELAY_P2_T1_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P2_T1_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== PEERDELAY_P3_T1 ==================================================== */ + #define R_ETHSW_PEERDELAY_P3_T1_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P3_T1_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== TS_FIFO_STATUS ===================================================== */ + #define R_ETHSW_TS_FIFO_STATUS_FF_VALID_Pos (0UL) /*!< FF_VALID (Bit 0) */ + #define R_ETHSW_TS_FIFO_STATUS_FF_VALID_Msk (0xfUL) /*!< FF_VALID (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_TS_FIFO_STATUS_FF_OVR_Pos (16UL) /*!< FF_OVR (Bit 16) */ + #define R_ETHSW_TS_FIFO_STATUS_FF_OVR_Msk (0xf0000UL) /*!< FF_OVR (Bitfield-Mask: 0x0f) */ +/* =================================================== TS_FIFO_READ_CTRL =================================================== */ + #define R_ETHSW_TS_FIFO_READ_CTRL_PORT_NUM_Pos (0UL) /*!< PORT_NUM (Bit 0) */ + #define R_ETHSW_TS_FIFO_READ_CTRL_PORT_NUM_Msk (0x3UL) /*!< PORT_NUM (Bitfield-Mask: 0x03) */ + #define R_ETHSW_TS_FIFO_READ_CTRL_TS_VALID_Pos (4UL) /*!< TS_VALID (Bit 4) */ + #define R_ETHSW_TS_FIFO_READ_CTRL_TS_VALID_Msk (0x10UL) /*!< TS_VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TS_FIFO_READ_CTRL_TS_SEL_Pos (6UL) /*!< TS_SEL (Bit 6) */ + #define R_ETHSW_TS_FIFO_READ_CTRL_TS_SEL_Msk (0x40UL) /*!< TS_SEL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TS_FIFO_READ_CTRL_TS_ID_Pos (8UL) /*!< TS_ID (Bit 8) */ + #define R_ETHSW_TS_FIFO_READ_CTRL_TS_ID_Msk (0x7f00UL) /*!< TS_ID (Bitfield-Mask: 0x7f) */ +/* ================================================ TS_FIFO_READ_TIMESTAMP ================================================= */ + #define R_ETHSW_TS_FIFO_READ_TIMESTAMP_TIMESTAMP_Pos (0UL) /*!< TIMESTAMP (Bit 0) */ + #define R_ETHSW_TS_FIFO_READ_TIMESTAMP_TIMESTAMP_Msk (0xffffffffUL) /*!< TIMESTAMP (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== INT_CONFIG ======================================================= */ + #define R_ETHSW_INT_CONFIG_IRQ_EN_Pos (0UL) /*!< IRQ_EN (Bit 0) */ + #define R_ETHSW_INT_CONFIG_IRQ_EN_Msk (0x1UL) /*!< IRQ_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_MDIO1_Pos (1UL) /*!< MDIO1 (Bit 1) */ + #define R_ETHSW_INT_CONFIG_MDIO1_Msk (0x2UL) /*!< MDIO1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_LK_NEW_SRC_Pos (3UL) /*!< LK_NEW_SRC (Bit 3) */ + #define R_ETHSW_INT_CONFIG_LK_NEW_SRC_Msk (0x8UL) /*!< LK_NEW_SRC (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_IRQ_TEST_Pos (4UL) /*!< IRQ_TEST (Bit 4) */ + #define R_ETHSW_INT_CONFIG_IRQ_TEST_Msk (0x10UL) /*!< IRQ_TEST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_DLR_INT_Pos (5UL) /*!< DLR_INT (Bit 5) */ + #define R_ETHSW_INT_CONFIG_DLR_INT_Msk (0x20UL) /*!< DLR_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_PRP_INT_Pos (6UL) /*!< PRP_INT (Bit 6) */ + #define R_ETHSW_INT_CONFIG_PRP_INT_Msk (0x40UL) /*!< PRP_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_HUB_INT_Pos (7UL) /*!< HUB_INT (Bit 7) */ + #define R_ETHSW_INT_CONFIG_HUB_INT_Msk (0x80UL) /*!< HUB_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_IRQ_LINK_Pos (8UL) /*!< IRQ_LINK (Bit 8) */ + #define R_ETHSW_INT_CONFIG_IRQ_LINK_Msk (0x700UL) /*!< IRQ_LINK (Bitfield-Mask: 0x07) */ + #define R_ETHSW_INT_CONFIG_IRQ_MAC_EEE_Pos (16UL) /*!< IRQ_MAC_EEE (Bit 16) */ + #define R_ETHSW_INT_CONFIG_IRQ_MAC_EEE_Msk (0x70000UL) /*!< IRQ_MAC_EEE (Bitfield-Mask: 0x07) */ + #define R_ETHSW_INT_CONFIG_SRCFLT_WD_INT_Pos (28UL) /*!< SRCFLT_WD_INT (Bit 28) */ + #define R_ETHSW_INT_CONFIG_SRCFLT_WD_INT_Msk (0x10000000UL) /*!< SRCFLT_WD_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_TSM_INT_Pos (29UL) /*!< TSM_INT (Bit 29) */ + #define R_ETHSW_INT_CONFIG_TSM_INT_Msk (0x20000000UL) /*!< TSM_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_TDMA_INT_Pos (30UL) /*!< TDMA_INT (Bit 30) */ + #define R_ETHSW_INT_CONFIG_TDMA_INT_Msk (0x40000000UL) /*!< TDMA_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_PATTERN_INT_Pos (31UL) /*!< PATTERN_INT (Bit 31) */ + #define R_ETHSW_INT_CONFIG_PATTERN_INT_Msk (0x80000000UL) /*!< PATTERN_INT (Bitfield-Mask: 0x01) */ +/* ===================================================== INT_STAT_ACK ====================================================== */ + #define R_ETHSW_INT_STAT_ACK_IRQ_PEND_Pos (0UL) /*!< IRQ_PEND (Bit 0) */ + #define R_ETHSW_INT_STAT_ACK_IRQ_PEND_Msk (0x1UL) /*!< IRQ_PEND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_MDIO1_Pos (1UL) /*!< MDIO1 (Bit 1) */ + #define R_ETHSW_INT_STAT_ACK_MDIO1_Msk (0x2UL) /*!< MDIO1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_LK_NEW_SRC_Pos (3UL) /*!< LK_NEW_SRC (Bit 3) */ + #define R_ETHSW_INT_STAT_ACK_LK_NEW_SRC_Msk (0x8UL) /*!< LK_NEW_SRC (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_IRQ_TEST_Pos (4UL) /*!< IRQ_TEST (Bit 4) */ + #define R_ETHSW_INT_STAT_ACK_IRQ_TEST_Msk (0x10UL) /*!< IRQ_TEST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_DLR_INT_Pos (5UL) /*!< DLR_INT (Bit 5) */ + #define R_ETHSW_INT_STAT_ACK_DLR_INT_Msk (0x20UL) /*!< DLR_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_PRP_INT_Pos (6UL) /*!< PRP_INT (Bit 6) */ + #define R_ETHSW_INT_STAT_ACK_PRP_INT_Msk (0x40UL) /*!< PRP_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_HUB_INT_Pos (7UL) /*!< HUB_INT (Bit 7) */ + #define R_ETHSW_INT_STAT_ACK_HUB_INT_Msk (0x80UL) /*!< HUB_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_IRQ_LINK_Pos (8UL) /*!< IRQ_LINK (Bit 8) */ + #define R_ETHSW_INT_STAT_ACK_IRQ_LINK_Msk (0x700UL) /*!< IRQ_LINK (Bitfield-Mask: 0x07) */ + #define R_ETHSW_INT_STAT_ACK_IRQ_MAC_EEE_Pos (16UL) /*!< IRQ_MAC_EEE (Bit 16) */ + #define R_ETHSW_INT_STAT_ACK_IRQ_MAC_EEE_Msk (0x70000UL) /*!< IRQ_MAC_EEE (Bitfield-Mask: 0x07) */ + #define R_ETHSW_INT_STAT_ACK_SRCFLT_WD_INT_Pos (28UL) /*!< SRCFLT_WD_INT (Bit 28) */ + #define R_ETHSW_INT_STAT_ACK_SRCFLT_WD_INT_Msk (0x10000000UL) /*!< SRCFLT_WD_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_TSM_INT_Pos (29UL) /*!< TSM_INT (Bit 29) */ + #define R_ETHSW_INT_STAT_ACK_TSM_INT_Msk (0x20000000UL) /*!< TSM_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_TDMA_INT_Pos (30UL) /*!< TDMA_INT (Bit 30) */ + #define R_ETHSW_INT_STAT_ACK_TDMA_INT_Msk (0x40000000UL) /*!< TDMA_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_PATTERN_INT_Pos (31UL) /*!< PATTERN_INT (Bit 31) */ + #define R_ETHSW_INT_STAT_ACK_PATTERN_INT_Msk (0x80000000UL) /*!< PATTERN_INT (Bitfield-Mask: 0x01) */ +/* ====================================================== ATIME_CTRL0 ====================================================== */ + #define R_ETHSW_ATIME_CTRL0_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_ETHSW_ATIME_CTRL0_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL0_ONE_SHOT_Pos (1UL) /*!< ONE_SHOT (Bit 1) */ + #define R_ETHSW_ATIME_CTRL0_ONE_SHOT_Msk (0x2UL) /*!< ONE_SHOT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL0_EVT_OFFSET_ENA_Pos (2UL) /*!< EVT_OFFSET_ENA (Bit 2) */ + #define R_ETHSW_ATIME_CTRL0_EVT_OFFSET_ENA_Msk (0x4UL) /*!< EVT_OFFSET_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_ENA_Pos (4UL) /*!< EVT_PERIOD_ENA (Bit 4) */ + #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_ENA_Msk (0x10UL) /*!< EVT_PERIOD_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_RST_Pos (5UL) /*!< EVT_PERIOD_RST (Bit 5) */ + #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_RST_Msk (0x20UL) /*!< EVT_PERIOD_RST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL0_RESTART_Pos (9UL) /*!< RESTART (Bit 9) */ + #define R_ETHSW_ATIME_CTRL0_RESTART_Msk (0x200UL) /*!< RESTART (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL0_CAPTURE_Pos (11UL) /*!< CAPTURE (Bit 11) */ + #define R_ETHSW_ATIME_CTRL0_CAPTURE_Msk (0x800UL) /*!< CAPTURE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL0_CAPTURE_ALL_Pos (12UL) /*!< CAPTURE_ALL (Bit 12) */ + #define R_ETHSW_ATIME_CTRL0_CAPTURE_ALL_Msk (0x1000UL) /*!< CAPTURE_ALL (Bitfield-Mask: 0x01) */ +/* ====================================================== ATIME_CTRL1 ====================================================== */ + #define R_ETHSW_ATIME_CTRL1_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_ETHSW_ATIME_CTRL1_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL1_ONE_SHOT_Pos (1UL) /*!< ONE_SHOT (Bit 1) */ + #define R_ETHSW_ATIME_CTRL1_ONE_SHOT_Msk (0x2UL) /*!< ONE_SHOT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL1_EVT_OFFSET_ENA_Pos (2UL) /*!< EVT_OFFSET_ENA (Bit 2) */ + #define R_ETHSW_ATIME_CTRL1_EVT_OFFSET_ENA_Msk (0x4UL) /*!< EVT_OFFSET_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_ENA_Pos (4UL) /*!< EVT_PERIOD_ENA (Bit 4) */ + #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_ENA_Msk (0x10UL) /*!< EVT_PERIOD_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_RST_Pos (5UL) /*!< EVT_PERIOD_RST (Bit 5) */ + #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_RST_Msk (0x20UL) /*!< EVT_PERIOD_RST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL1_RESTART_Pos (9UL) /*!< RESTART (Bit 9) */ + #define R_ETHSW_ATIME_CTRL1_RESTART_Msk (0x200UL) /*!< RESTART (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL1_CAPTURE_Pos (11UL) /*!< CAPTURE (Bit 11) */ + #define R_ETHSW_ATIME_CTRL1_CAPTURE_Msk (0x800UL) /*!< CAPTURE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL1_CAPTURE_ALL_Pos (12UL) /*!< CAPTURE_ALL (Bit 12) */ + #define R_ETHSW_ATIME_CTRL1_CAPTURE_ALL_Msk (0x1000UL) /*!< CAPTURE_ALL (Bitfield-Mask: 0x01) */ +/* ======================================================== ATIME0 ========================================================= */ + #define R_ETHSW_ATIME0_TIMER_VAL_Pos (0UL) /*!< TIMER_VAL (Bit 0) */ + #define R_ETHSW_ATIME0_TIMER_VAL_Msk (0xffffffffUL) /*!< TIMER_VAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ATIME1 ========================================================= */ + #define R_ETHSW_ATIME1_TIMER_VAL_Pos (0UL) /*!< TIMER_VAL (Bit 0) */ + #define R_ETHSW_ATIME1_TIMER_VAL_Msk (0xffffffffUL) /*!< TIMER_VAL (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== ATIME_OFFSET0 ===================================================== */ + #define R_ETHSW_ATIME_OFFSET0_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */ + #define R_ETHSW_ATIME_OFFSET0_OFFSET_Msk (0xffffffffUL) /*!< OFFSET (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== ATIME_OFFSET1 ===================================================== */ + #define R_ETHSW_ATIME_OFFSET1_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */ + #define R_ETHSW_ATIME_OFFSET1_OFFSET_Msk (0xffffffffUL) /*!< OFFSET (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ATIME_EVT_PERIOD0 =================================================== */ + #define R_ETHSW_ATIME_EVT_PERIOD0_PERIOD_Pos (0UL) /*!< PERIOD (Bit 0) */ + #define R_ETHSW_ATIME_EVT_PERIOD0_PERIOD_Msk (0xffffffffUL) /*!< PERIOD (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ATIME_EVT_PERIOD1 =================================================== */ + #define R_ETHSW_ATIME_EVT_PERIOD1_PERIOD_Pos (0UL) /*!< PERIOD (Bit 0) */ + #define R_ETHSW_ATIME_EVT_PERIOD1_PERIOD_Msk (0xffffffffUL) /*!< PERIOD (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ATIME_CORR0 ====================================================== */ + #define R_ETHSW_ATIME_CORR0_CORR_PERIOD_Pos (0UL) /*!< CORR_PERIOD (Bit 0) */ + #define R_ETHSW_ATIME_CORR0_CORR_PERIOD_Msk (0x7fffffffUL) /*!< CORR_PERIOD (Bitfield-Mask: 0x7fffffff) */ +/* ====================================================== ATIME_CORR1 ====================================================== */ + #define R_ETHSW_ATIME_CORR1_CORR_PERIOD_Pos (0UL) /*!< CORR_PERIOD (Bit 0) */ + #define R_ETHSW_ATIME_CORR1_CORR_PERIOD_Msk (0x7fffffffUL) /*!< CORR_PERIOD (Bitfield-Mask: 0x7fffffff) */ +/* ====================================================== ATIME_INC0 ======================================================= */ + #define R_ETHSW_ATIME_INC0_CLK_PERIOD_Pos (0UL) /*!< CLK_PERIOD (Bit 0) */ + #define R_ETHSW_ATIME_INC0_CLK_PERIOD_Msk (0x7fUL) /*!< CLK_PERIOD (Bitfield-Mask: 0x7f) */ + #define R_ETHSW_ATIME_INC0_CORR_INC_Pos (8UL) /*!< CORR_INC (Bit 8) */ + #define R_ETHSW_ATIME_INC0_CORR_INC_Msk (0x7f00UL) /*!< CORR_INC (Bitfield-Mask: 0x7f) */ + #define R_ETHSW_ATIME_INC0_OFFS_CORR_INC_Pos (16UL) /*!< OFFS_CORR_INC (Bit 16) */ + #define R_ETHSW_ATIME_INC0_OFFS_CORR_INC_Msk (0x7f0000UL) /*!< OFFS_CORR_INC (Bitfield-Mask: 0x7f) */ +/* ====================================================== ATIME_INC1 ======================================================= */ + #define R_ETHSW_ATIME_INC1_CLK_PERIOD_Pos (0UL) /*!< CLK_PERIOD (Bit 0) */ + #define R_ETHSW_ATIME_INC1_CLK_PERIOD_Msk (0x7fUL) /*!< CLK_PERIOD (Bitfield-Mask: 0x7f) */ + #define R_ETHSW_ATIME_INC1_CORR_INC_Pos (8UL) /*!< CORR_INC (Bit 8) */ + #define R_ETHSW_ATIME_INC1_CORR_INC_Msk (0x7f00UL) /*!< CORR_INC (Bitfield-Mask: 0x7f) */ + #define R_ETHSW_ATIME_INC1_OFFS_CORR_INC_Pos (16UL) /*!< OFFS_CORR_INC (Bit 16) */ + #define R_ETHSW_ATIME_INC1_OFFS_CORR_INC_Msk (0x7f0000UL) /*!< OFFS_CORR_INC (Bitfield-Mask: 0x7f) */ +/* ====================================================== ATIME_SEC0 ======================================================= */ + #define R_ETHSW_ATIME_SEC0_SEC_TIME_Pos (0UL) /*!< SEC_TIME (Bit 0) */ + #define R_ETHSW_ATIME_SEC0_SEC_TIME_Msk (0xffffffffUL) /*!< SEC_TIME (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ATIME_SEC1 ======================================================= */ + #define R_ETHSW_ATIME_SEC1_SEC_TIME_Pos (0UL) /*!< SEC_TIME (Bit 0) */ + #define R_ETHSW_ATIME_SEC1_SEC_TIME_Msk (0xffffffffUL) /*!< SEC_TIME (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ATIME_OFFS_CORR0 ==================================================== */ + #define R_ETHSW_ATIME_OFFS_CORR0_OFFS_CORR_CNT_Pos (0UL) /*!< OFFS_CORR_CNT (Bit 0) */ + #define R_ETHSW_ATIME_OFFS_CORR0_OFFS_CORR_CNT_Msk (0xffffffffUL) /*!< OFFS_CORR_CNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ATIME_OFFS_CORR1 ==================================================== */ + #define R_ETHSW_ATIME_OFFS_CORR1_OFFS_CORR_CNT_Pos (0UL) /*!< OFFS_CORR_CNT (Bit 0) */ + #define R_ETHSW_ATIME_OFFS_CORR1_OFFS_CORR_CNT_Msk (0xffffffffUL) /*!< OFFS_CORR_CNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== MDIO_CFG_STATUS ==================================================== */ + #define R_ETHSW_MDIO_CFG_STATUS_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ + #define R_ETHSW_MDIO_CFG_STATUS_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MDIO_CFG_STATUS_READERR_Pos (1UL) /*!< READERR (Bit 1) */ + #define R_ETHSW_MDIO_CFG_STATUS_READERR_Msk (0x2UL) /*!< READERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MDIO_CFG_STATUS_HOLD_Pos (2UL) /*!< HOLD (Bit 2) */ + #define R_ETHSW_MDIO_CFG_STATUS_HOLD_Msk (0x1cUL) /*!< HOLD (Bitfield-Mask: 0x07) */ + #define R_ETHSW_MDIO_CFG_STATUS_DISPREAM_Pos (5UL) /*!< DISPREAM (Bit 5) */ + #define R_ETHSW_MDIO_CFG_STATUS_DISPREAM_Msk (0x20UL) /*!< DISPREAM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MDIO_CFG_STATUS_CLKDIV_Pos (7UL) /*!< CLKDIV (Bit 7) */ + #define R_ETHSW_MDIO_CFG_STATUS_CLKDIV_Msk (0xff80UL) /*!< CLKDIV (Bitfield-Mask: 0x1ff) */ +/* ===================================================== MDIO_COMMAND ====================================================== */ + #define R_ETHSW_MDIO_COMMAND_REGADDR_Pos (0UL) /*!< REGADDR (Bit 0) */ + #define R_ETHSW_MDIO_COMMAND_REGADDR_Msk (0x1fUL) /*!< REGADDR (Bitfield-Mask: 0x1f) */ + #define R_ETHSW_MDIO_COMMAND_PHYADDR_Pos (5UL) /*!< PHYADDR (Bit 5) */ + #define R_ETHSW_MDIO_COMMAND_PHYADDR_Msk (0x3e0UL) /*!< PHYADDR (Bitfield-Mask: 0x1f) */ + #define R_ETHSW_MDIO_COMMAND_TRANINIT_Pos (15UL) /*!< TRANINIT (Bit 15) */ + #define R_ETHSW_MDIO_COMMAND_TRANINIT_Msk (0x8000UL) /*!< TRANINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= MDIO_DATA ======================================================= */ + #define R_ETHSW_MDIO_DATA_MDIO_DATA_Pos (0UL) /*!< MDIO_DATA (Bit 0) */ + #define R_ETHSW_MDIO_DATA_MDIO_DATA_Msk (0xffffUL) /*!< MDIO_DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== REV_P0 ========================================================= */ + #define R_ETHSW_REV_P0_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_ETHSW_REV_P0_REV_Msk (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== REV_P1 ========================================================= */ + #define R_ETHSW_REV_P1_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_ETHSW_REV_P1_REV_Msk (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== REV_P2 ========================================================= */ + #define R_ETHSW_REV_P2_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_ETHSW_REV_P2_REV_Msk (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== REV_P3 ========================================================= */ + #define R_ETHSW_REV_P3_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_ETHSW_REV_P3_REV_Msk (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff) */ +/* =================================================== COMMAND_CONFIG_P0 =================================================== */ + #define R_ETHSW_COMMAND_CONFIG_P0_TX_ENA_Pos (0UL) /*!< TX_ENA (Bit 0) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TX_ENA_Msk (0x1UL) /*!< TX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_RX_ENA_Pos (1UL) /*!< RX_ENA (Bit 1) */ + #define R_ETHSW_COMMAND_CONFIG_P0_RX_ENA_Msk (0x2UL) /*!< RX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TDMA_PREBUF_DIS_Pos (2UL) /*!< TDMA_PREBUF_DIS (Bit 2) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TDMA_PREBUF_DIS_Msk (0x4UL) /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_ETH_SPEED_Pos (3UL) /*!< ETH_SPEED (Bit 3) */ + #define R_ETHSW_COMMAND_CONFIG_P0_ETH_SPEED_Msk (0x8UL) /*!< ETH_SPEED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PROMIS_EN_Pos (4UL) /*!< PROMIS_EN (Bit 4) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PROMIS_EN_Msk (0x10UL) /*!< PROMIS_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PAD_EN_Pos (5UL) /*!< PAD_EN (Bit 5) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PAD_EN_Msk (0x20UL) /*!< PAD_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_FWD_Pos (7UL) /*!< PAUSE_FWD (Bit 7) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_FWD_Msk (0x80UL) /*!< PAUSE_FWD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_IGNORE_Pos (8UL) /*!< PAUSE_IGNORE (Bit 8) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_IGNORE_Msk (0x100UL) /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TX_ADDR_INS_Pos (9UL) /*!< TX_ADDR_INS (Bit 9) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TX_ADDR_INS_Msk (0x200UL) /*!< TX_ADDR_INS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_HD_ENA_Pos (10UL) /*!< HD_ENA (Bit 10) */ + #define R_ETHSW_COMMAND_CONFIG_P0_HD_ENA_Msk (0x400UL) /*!< HD_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TX_CRC_APPEND_Pos (11UL) /*!< TX_CRC_APPEND (Bit 11) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TX_CRC_APPEND_Msk (0x800UL) /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_SW_RESET_Pos (13UL) /*!< SW_RESET (Bit 13) */ + #define R_ETHSW_COMMAND_CONFIG_P0_SW_RESET_Msk (0x2000UL) /*!< SW_RESET (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_CNTL_FRM_ENA_Pos (23UL) /*!< CNTL_FRM_ENA (Bit 23) */ + #define R_ETHSW_COMMAND_CONFIG_P0_CNTL_FRM_ENA_Msk (0x800000UL) /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_NO_LGTH_CHK_Pos (24UL) /*!< NO_LGTH_CHK (Bit 24) */ + #define R_ETHSW_COMMAND_CONFIG_P0_NO_LGTH_CHK_Msk (0x1000000UL) /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_ENA_10_Pos (25UL) /*!< ENA_10 (Bit 25) */ + #define R_ETHSW_COMMAND_CONFIG_P0_ENA_10_Msk (0x2000000UL) /*!< ENA_10 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TIMER_SEL_Pos (30UL) /*!< TIMER_SEL (Bit 30) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TIMER_SEL_Msk (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ +/* =================================================== COMMAND_CONFIG_P1 =================================================== */ + #define R_ETHSW_COMMAND_CONFIG_P1_TX_ENA_Pos (0UL) /*!< TX_ENA (Bit 0) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TX_ENA_Msk (0x1UL) /*!< TX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_RX_ENA_Pos (1UL) /*!< RX_ENA (Bit 1) */ + #define R_ETHSW_COMMAND_CONFIG_P1_RX_ENA_Msk (0x2UL) /*!< RX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TDMA_PREBUF_DIS_Pos (2UL) /*!< TDMA_PREBUF_DIS (Bit 2) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TDMA_PREBUF_DIS_Msk (0x4UL) /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_ETH_SPEED_Pos (3UL) /*!< ETH_SPEED (Bit 3) */ + #define R_ETHSW_COMMAND_CONFIG_P1_ETH_SPEED_Msk (0x8UL) /*!< ETH_SPEED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PROMIS_EN_Pos (4UL) /*!< PROMIS_EN (Bit 4) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PROMIS_EN_Msk (0x10UL) /*!< PROMIS_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PAD_EN_Pos (5UL) /*!< PAD_EN (Bit 5) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PAD_EN_Msk (0x20UL) /*!< PAD_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_FWD_Pos (7UL) /*!< PAUSE_FWD (Bit 7) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_FWD_Msk (0x80UL) /*!< PAUSE_FWD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_IGNORE_Pos (8UL) /*!< PAUSE_IGNORE (Bit 8) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_IGNORE_Msk (0x100UL) /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TX_ADDR_INS_Pos (9UL) /*!< TX_ADDR_INS (Bit 9) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TX_ADDR_INS_Msk (0x200UL) /*!< TX_ADDR_INS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_HD_ENA_Pos (10UL) /*!< HD_ENA (Bit 10) */ + #define R_ETHSW_COMMAND_CONFIG_P1_HD_ENA_Msk (0x400UL) /*!< HD_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TX_CRC_APPEND_Pos (11UL) /*!< TX_CRC_APPEND (Bit 11) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TX_CRC_APPEND_Msk (0x800UL) /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_SW_RESET_Pos (13UL) /*!< SW_RESET (Bit 13) */ + #define R_ETHSW_COMMAND_CONFIG_P1_SW_RESET_Msk (0x2000UL) /*!< SW_RESET (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_CNTL_FRM_ENA_Pos (23UL) /*!< CNTL_FRM_ENA (Bit 23) */ + #define R_ETHSW_COMMAND_CONFIG_P1_CNTL_FRM_ENA_Msk (0x800000UL) /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_NO_LGTH_CHK_Pos (24UL) /*!< NO_LGTH_CHK (Bit 24) */ + #define R_ETHSW_COMMAND_CONFIG_P1_NO_LGTH_CHK_Msk (0x1000000UL) /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_ENA_10_Pos (25UL) /*!< ENA_10 (Bit 25) */ + #define R_ETHSW_COMMAND_CONFIG_P1_ENA_10_Msk (0x2000000UL) /*!< ENA_10 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TIMER_SEL_Pos (30UL) /*!< TIMER_SEL (Bit 30) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TIMER_SEL_Msk (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ +/* =================================================== COMMAND_CONFIG_P2 =================================================== */ + #define R_ETHSW_COMMAND_CONFIG_P2_TX_ENA_Pos (0UL) /*!< TX_ENA (Bit 0) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TX_ENA_Msk (0x1UL) /*!< TX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_RX_ENA_Pos (1UL) /*!< RX_ENA (Bit 1) */ + #define R_ETHSW_COMMAND_CONFIG_P2_RX_ENA_Msk (0x2UL) /*!< RX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TDMA_PREBUF_DIS_Pos (2UL) /*!< TDMA_PREBUF_DIS (Bit 2) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TDMA_PREBUF_DIS_Msk (0x4UL) /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_ETH_SPEED_Pos (3UL) /*!< ETH_SPEED (Bit 3) */ + #define R_ETHSW_COMMAND_CONFIG_P2_ETH_SPEED_Msk (0x8UL) /*!< ETH_SPEED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PROMIS_EN_Pos (4UL) /*!< PROMIS_EN (Bit 4) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PROMIS_EN_Msk (0x10UL) /*!< PROMIS_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PAD_EN_Pos (5UL) /*!< PAD_EN (Bit 5) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PAD_EN_Msk (0x20UL) /*!< PAD_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_FWD_Pos (7UL) /*!< PAUSE_FWD (Bit 7) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_FWD_Msk (0x80UL) /*!< PAUSE_FWD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_IGNORE_Pos (8UL) /*!< PAUSE_IGNORE (Bit 8) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_IGNORE_Msk (0x100UL) /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TX_ADDR_INS_Pos (9UL) /*!< TX_ADDR_INS (Bit 9) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TX_ADDR_INS_Msk (0x200UL) /*!< TX_ADDR_INS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_HD_ENA_Pos (10UL) /*!< HD_ENA (Bit 10) */ + #define R_ETHSW_COMMAND_CONFIG_P2_HD_ENA_Msk (0x400UL) /*!< HD_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TX_CRC_APPEND_Pos (11UL) /*!< TX_CRC_APPEND (Bit 11) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TX_CRC_APPEND_Msk (0x800UL) /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_SW_RESET_Pos (13UL) /*!< SW_RESET (Bit 13) */ + #define R_ETHSW_COMMAND_CONFIG_P2_SW_RESET_Msk (0x2000UL) /*!< SW_RESET (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_CNTL_FRM_ENA_Pos (23UL) /*!< CNTL_FRM_ENA (Bit 23) */ + #define R_ETHSW_COMMAND_CONFIG_P2_CNTL_FRM_ENA_Msk (0x800000UL) /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_NO_LGTH_CHK_Pos (24UL) /*!< NO_LGTH_CHK (Bit 24) */ + #define R_ETHSW_COMMAND_CONFIG_P2_NO_LGTH_CHK_Msk (0x1000000UL) /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_ENA_10_Pos (25UL) /*!< ENA_10 (Bit 25) */ + #define R_ETHSW_COMMAND_CONFIG_P2_ENA_10_Msk (0x2000000UL) /*!< ENA_10 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TIMER_SEL_Pos (30UL) /*!< TIMER_SEL (Bit 30) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TIMER_SEL_Msk (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ +/* =================================================== COMMAND_CONFIG_P3 =================================================== */ + #define R_ETHSW_COMMAND_CONFIG_P3_TX_ENA_Pos (0UL) /*!< TX_ENA (Bit 0) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TX_ENA_Msk (0x1UL) /*!< TX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_RX_ENA_Pos (1UL) /*!< RX_ENA (Bit 1) */ + #define R_ETHSW_COMMAND_CONFIG_P3_RX_ENA_Msk (0x2UL) /*!< RX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TDMA_PREBUF_DIS_Pos (2UL) /*!< TDMA_PREBUF_DIS (Bit 2) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TDMA_PREBUF_DIS_Msk (0x4UL) /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_ETH_SPEED_Pos (3UL) /*!< ETH_SPEED (Bit 3) */ + #define R_ETHSW_COMMAND_CONFIG_P3_ETH_SPEED_Msk (0x8UL) /*!< ETH_SPEED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PROMIS_EN_Pos (4UL) /*!< PROMIS_EN (Bit 4) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PROMIS_EN_Msk (0x10UL) /*!< PROMIS_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PAD_EN_Pos (5UL) /*!< PAD_EN (Bit 5) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PAD_EN_Msk (0x20UL) /*!< PAD_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_FWD_Pos (7UL) /*!< PAUSE_FWD (Bit 7) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_FWD_Msk (0x80UL) /*!< PAUSE_FWD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_IGNORE_Pos (8UL) /*!< PAUSE_IGNORE (Bit 8) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_IGNORE_Msk (0x100UL) /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TX_ADDR_INS_Pos (9UL) /*!< TX_ADDR_INS (Bit 9) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TX_ADDR_INS_Msk (0x200UL) /*!< TX_ADDR_INS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_HD_ENA_Pos (10UL) /*!< HD_ENA (Bit 10) */ + #define R_ETHSW_COMMAND_CONFIG_P3_HD_ENA_Msk (0x400UL) /*!< HD_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TX_CRC_APPEND_Pos (11UL) /*!< TX_CRC_APPEND (Bit 11) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TX_CRC_APPEND_Msk (0x800UL) /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_SW_RESET_Pos (13UL) /*!< SW_RESET (Bit 13) */ + #define R_ETHSW_COMMAND_CONFIG_P3_SW_RESET_Msk (0x2000UL) /*!< SW_RESET (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_CNTL_FRM_ENA_Pos (23UL) /*!< CNTL_FRM_ENA (Bit 23) */ + #define R_ETHSW_COMMAND_CONFIG_P3_CNTL_FRM_ENA_Msk (0x800000UL) /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_NO_LGTH_CHK_Pos (24UL) /*!< NO_LGTH_CHK (Bit 24) */ + #define R_ETHSW_COMMAND_CONFIG_P3_NO_LGTH_CHK_Msk (0x1000000UL) /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_ENA_10_Pos (25UL) /*!< ENA_10 (Bit 25) */ + #define R_ETHSW_COMMAND_CONFIG_P3_ENA_10_Msk (0x2000000UL) /*!< ENA_10 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TIMER_SEL_Pos (30UL) /*!< TIMER_SEL (Bit 30) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TIMER_SEL_Msk (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ +/* ===================================================== MAC_ADDR_0_P0 ===================================================== */ + #define R_ETHSW_MAC_ADDR_0_P0_MAC_ADDR_Pos (0UL) /*!< MAC_ADDR (Bit 0) */ + #define R_ETHSW_MAC_ADDR_0_P0_MAC_ADDR_Msk (0xffffffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== MAC_ADDR_0_P1 ===================================================== */ + #define R_ETHSW_MAC_ADDR_0_P1_MAC_ADDR_Pos (0UL) /*!< MAC_ADDR (Bit 0) */ + #define R_ETHSW_MAC_ADDR_0_P1_MAC_ADDR_Msk (0xffffffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== MAC_ADDR_0_P2 ===================================================== */ + #define R_ETHSW_MAC_ADDR_0_P2_MAC_ADDR_Pos (0UL) /*!< MAC_ADDR (Bit 0) */ + #define R_ETHSW_MAC_ADDR_0_P2_MAC_ADDR_Msk (0xffffffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== MAC_ADDR_1_P0 ===================================================== */ + #define R_ETHSW_MAC_ADDR_1_P0_MAC_ADDR_Pos (0UL) /*!< MAC_ADDR (Bit 0) */ + #define R_ETHSW_MAC_ADDR_1_P0_MAC_ADDR_Msk (0xffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== MAC_ADDR_1_P1 ===================================================== */ + #define R_ETHSW_MAC_ADDR_1_P1_MAC_ADDR_Pos (0UL) /*!< MAC_ADDR (Bit 0) */ + #define R_ETHSW_MAC_ADDR_1_P1_MAC_ADDR_Msk (0xffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== MAC_ADDR_1_P2 ===================================================== */ + #define R_ETHSW_MAC_ADDR_1_P2_MAC_ADDR_Pos (0UL) /*!< MAC_ADDR (Bit 0) */ + #define R_ETHSW_MAC_ADDR_1_P2_MAC_ADDR_Msk (0xffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== FRM_LENGTH_P0 ===================================================== */ + #define R_ETHSW_FRM_LENGTH_P0_FRM_LENGTH_Pos (0UL) /*!< FRM_LENGTH (Bit 0) */ + #define R_ETHSW_FRM_LENGTH_P0_FRM_LENGTH_Msk (0x3fffUL) /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff) */ +/* ===================================================== FRM_LENGTH_P1 ===================================================== */ + #define R_ETHSW_FRM_LENGTH_P1_FRM_LENGTH_Pos (0UL) /*!< FRM_LENGTH (Bit 0) */ + #define R_ETHSW_FRM_LENGTH_P1_FRM_LENGTH_Msk (0x3fffUL) /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff) */ +/* ===================================================== FRM_LENGTH_P2 ===================================================== */ + #define R_ETHSW_FRM_LENGTH_P2_FRM_LENGTH_Pos (0UL) /*!< FRM_LENGTH (Bit 0) */ + #define R_ETHSW_FRM_LENGTH_P2_FRM_LENGTH_Msk (0x3fffUL) /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff) */ +/* ===================================================== FRM_LENGTH_P3 ===================================================== */ + #define R_ETHSW_FRM_LENGTH_P3_FRM_LENGTH_Pos (0UL) /*!< FRM_LENGTH (Bit 0) */ + #define R_ETHSW_FRM_LENGTH_P3_FRM_LENGTH_Msk (0x3fffUL) /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff) */ +/* ==================================================== PAUSE_QUANT_P0 ===================================================== */ + #define R_ETHSW_PAUSE_QUANT_P0_PAUSE_QUANT_Pos (0UL) /*!< PAUSE_QUANT (Bit 0) */ + #define R_ETHSW_PAUSE_QUANT_P0_PAUSE_QUANT_Msk (0xffffUL) /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff) */ +/* ==================================================== PAUSE_QUANT_P1 ===================================================== */ + #define R_ETHSW_PAUSE_QUANT_P1_PAUSE_QUANT_Pos (0UL) /*!< PAUSE_QUANT (Bit 0) */ + #define R_ETHSW_PAUSE_QUANT_P1_PAUSE_QUANT_Msk (0xffffUL) /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff) */ +/* ==================================================== PAUSE_QUANT_P2 ===================================================== */ + #define R_ETHSW_PAUSE_QUANT_P2_PAUSE_QUANT_Pos (0UL) /*!< PAUSE_QUANT (Bit 0) */ + #define R_ETHSW_PAUSE_QUANT_P2_PAUSE_QUANT_Msk (0xffffUL) /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff) */ +/* ==================================================== PAUSE_QUANT_P3 ===================================================== */ + #define R_ETHSW_PAUSE_QUANT_P3_PAUSE_QUANT_Pos (0UL) /*!< PAUSE_QUANT (Bit 0) */ + #define R_ETHSW_PAUSE_QUANT_P3_PAUSE_QUANT_Msk (0xffffUL) /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff) */ +/* =================================================== MAC_LINK_QTRIG_P0 =================================================== */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_PORT_MASK_Pos (0UL) /*!< PORT_MASK (Bit 0) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_PORT_MASK_Msk (0xfUL) /*!< PORT_MASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_QUEUE_MASK_Pos (16UL) /*!< QUEUE_MASK (Bit 16) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_QUEUE_MASK_Msk (0xff0000UL) /*!< QUEUE_MASK (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_TRIGGERED_Pos (28UL) /*!< TRIGGERED (Bit 28) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_TRIGGERED_Msk (0x10000000UL) /*!< TRIGGERED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_DLR_MODE_Pos (29UL) /*!< DLR_MODE (Bit 29) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_DLR_MODE_Msk (0x20000000UL) /*!< DLR_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_MODE_Pos (30UL) /*!< MODE (Bit 30) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_MODE_Msk (0x40000000UL) /*!< MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =================================================== MAC_LINK_QTRIG_P1 =================================================== */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_PORT_MASK_Pos (0UL) /*!< PORT_MASK (Bit 0) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_PORT_MASK_Msk (0xfUL) /*!< PORT_MASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_QUEUE_MASK_Pos (16UL) /*!< QUEUE_MASK (Bit 16) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_QUEUE_MASK_Msk (0xff0000UL) /*!< QUEUE_MASK (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_TRIGGERED_Pos (28UL) /*!< TRIGGERED (Bit 28) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_TRIGGERED_Msk (0x10000000UL) /*!< TRIGGERED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_DLR_MODE_Pos (29UL) /*!< DLR_MODE (Bit 29) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_DLR_MODE_Msk (0x20000000UL) /*!< DLR_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_MODE_Pos (30UL) /*!< MODE (Bit 30) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_MODE_Msk (0x40000000UL) /*!< MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =================================================== MAC_LINK_QTRIG_P2 =================================================== */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_PORT_MASK_Pos (0UL) /*!< PORT_MASK (Bit 0) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_PORT_MASK_Msk (0xfUL) /*!< PORT_MASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_QUEUE_MASK_Pos (16UL) /*!< QUEUE_MASK (Bit 16) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_QUEUE_MASK_Msk (0xff0000UL) /*!< QUEUE_MASK (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_TRIGGERED_Pos (28UL) /*!< TRIGGERED (Bit 28) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_TRIGGERED_Msk (0x10000000UL) /*!< TRIGGERED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_DLR_MODE_Pos (29UL) /*!< DLR_MODE (Bit 29) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_DLR_MODE_Msk (0x20000000UL) /*!< DLR_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_MODE_Pos (30UL) /*!< MODE (Bit 30) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_MODE_Msk (0x40000000UL) /*!< MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================= PTPCLOCKIDENTITY1_P0 ================================================== */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY0_Pos (0UL) /*!< CLK_IDENTITY0 (Bit 0) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY0_Msk (0xffUL) /*!< CLK_IDENTITY0 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY1_Pos (8UL) /*!< CLK_IDENTITY1 (Bit 8) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY1_Msk (0xff00UL) /*!< CLK_IDENTITY1 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY2_Pos (16UL) /*!< CLK_IDENTITY2 (Bit 16) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY2_Msk (0xff0000UL) /*!< CLK_IDENTITY2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY3_Pos (24UL) /*!< CLK_IDENTITY3 (Bit 24) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY3_Msk (0xff000000UL) /*!< CLK_IDENTITY3 (Bitfield-Mask: 0xff) */ +/* ================================================= PTPCLOCKIDENTITY1_P1 ================================================== */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY0_Pos (0UL) /*!< CLK_IDENTITY0 (Bit 0) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY0_Msk (0xffUL) /*!< CLK_IDENTITY0 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY1_Pos (8UL) /*!< CLK_IDENTITY1 (Bit 8) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY1_Msk (0xff00UL) /*!< CLK_IDENTITY1 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY2_Pos (16UL) /*!< CLK_IDENTITY2 (Bit 16) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY2_Msk (0xff0000UL) /*!< CLK_IDENTITY2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY3_Pos (24UL) /*!< CLK_IDENTITY3 (Bit 24) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY3_Msk (0xff000000UL) /*!< CLK_IDENTITY3 (Bitfield-Mask: 0xff) */ +/* ================================================= PTPCLOCKIDENTITY1_P2 ================================================== */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY0_Pos (0UL) /*!< CLK_IDENTITY0 (Bit 0) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY0_Msk (0xffUL) /*!< CLK_IDENTITY0 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY1_Pos (8UL) /*!< CLK_IDENTITY1 (Bit 8) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY1_Msk (0xff00UL) /*!< CLK_IDENTITY1 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY2_Pos (16UL) /*!< CLK_IDENTITY2 (Bit 16) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY2_Msk (0xff0000UL) /*!< CLK_IDENTITY2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY3_Pos (24UL) /*!< CLK_IDENTITY3 (Bit 24) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY3_Msk (0xff000000UL) /*!< CLK_IDENTITY3 (Bitfield-Mask: 0xff) */ +/* ================================================= PTPCLOCKIDENTITY2_P0 ================================================== */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY4_Pos (0UL) /*!< CLK_IDENTITY4 (Bit 0) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY4_Msk (0xffUL) /*!< CLK_IDENTITY4 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY5_Pos (8UL) /*!< CLK_IDENTITY5 (Bit 8) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY5_Msk (0xff00UL) /*!< CLK_IDENTITY5 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY6_Pos (16UL) /*!< CLK_IDENTITY6 (Bit 16) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY6_Msk (0xff0000UL) /*!< CLK_IDENTITY6 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY7_Pos (24UL) /*!< CLK_IDENTITY7 (Bit 24) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY7_Msk (0xff000000UL) /*!< CLK_IDENTITY7 (Bitfield-Mask: 0xff) */ +/* ================================================= PTPCLOCKIDENTITY2_P1 ================================================== */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY4_Pos (0UL) /*!< CLK_IDENTITY4 (Bit 0) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY4_Msk (0xffUL) /*!< CLK_IDENTITY4 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY5_Pos (8UL) /*!< CLK_IDENTITY5 (Bit 8) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY5_Msk (0xff00UL) /*!< CLK_IDENTITY5 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY6_Pos (16UL) /*!< CLK_IDENTITY6 (Bit 16) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY6_Msk (0xff0000UL) /*!< CLK_IDENTITY6 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY7_Pos (24UL) /*!< CLK_IDENTITY7 (Bit 24) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY7_Msk (0xff000000UL) /*!< CLK_IDENTITY7 (Bitfield-Mask: 0xff) */ +/* ================================================= PTPCLOCKIDENTITY2_P2 ================================================== */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY4_Pos (0UL) /*!< CLK_IDENTITY4 (Bit 0) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY4_Msk (0xffUL) /*!< CLK_IDENTITY4 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY5_Pos (8UL) /*!< CLK_IDENTITY5 (Bit 8) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY5_Msk (0xff00UL) /*!< CLK_IDENTITY5 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY6_Pos (16UL) /*!< CLK_IDENTITY6 (Bit 16) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY6_Msk (0xff0000UL) /*!< CLK_IDENTITY6 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY7_Pos (24UL) /*!< CLK_IDENTITY7 (Bit 24) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY7_Msk (0xff000000UL) /*!< CLK_IDENTITY7 (Bitfield-Mask: 0xff) */ +/* ================================================== PTPAUTORESPONSE_P0 =================================================== */ + #define R_ETHSW_PTPAUTORESPONSE_P0_ARSP_EN_Pos (0UL) /*!< ARSP_EN (Bit 0) */ + #define R_ETHSW_PTPAUTORESPONSE_P0_ARSP_EN_Msk (0x1UL) /*!< ARSP_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTPAUTORESPONSE_P0_D_TIMER_Pos (1UL) /*!< D_TIMER (Bit 1) */ + #define R_ETHSW_PTPAUTORESPONSE_P0_D_TIMER_Msk (0x2UL) /*!< D_TIMER (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM1_Pos (16UL) /*!< PORTNUM1 (Bit 16) */ + #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM1_Msk (0xff0000UL) /*!< PORTNUM1 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM0_Pos (24UL) /*!< PORTNUM0 (Bit 24) */ + #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM0_Msk (0xff000000UL) /*!< PORTNUM0 (Bitfield-Mask: 0xff) */ +/* ================================================== PTPAUTORESPONSE_P1 =================================================== */ + #define R_ETHSW_PTPAUTORESPONSE_P1_ARSP_EN_Pos (0UL) /*!< ARSP_EN (Bit 0) */ + #define R_ETHSW_PTPAUTORESPONSE_P1_ARSP_EN_Msk (0x1UL) /*!< ARSP_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTPAUTORESPONSE_P1_D_TIMER_Pos (1UL) /*!< D_TIMER (Bit 1) */ + #define R_ETHSW_PTPAUTORESPONSE_P1_D_TIMER_Msk (0x2UL) /*!< D_TIMER (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM1_Pos (16UL) /*!< PORTNUM1 (Bit 16) */ + #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM1_Msk (0xff0000UL) /*!< PORTNUM1 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM0_Pos (24UL) /*!< PORTNUM0 (Bit 24) */ + #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM0_Msk (0xff000000UL) /*!< PORTNUM0 (Bitfield-Mask: 0xff) */ +/* ================================================== PTPAUTORESPONSE_P2 =================================================== */ + #define R_ETHSW_PTPAUTORESPONSE_P2_ARSP_EN_Pos (0UL) /*!< ARSP_EN (Bit 0) */ + #define R_ETHSW_PTPAUTORESPONSE_P2_ARSP_EN_Msk (0x1UL) /*!< ARSP_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTPAUTORESPONSE_P2_D_TIMER_Pos (1UL) /*!< D_TIMER (Bit 1) */ + #define R_ETHSW_PTPAUTORESPONSE_P2_D_TIMER_Msk (0x2UL) /*!< D_TIMER (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM1_Pos (16UL) /*!< PORTNUM1 (Bit 16) */ + #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM1_Msk (0xff0000UL) /*!< PORTNUM1 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM0_Pos (24UL) /*!< PORTNUM0 (Bit 24) */ + #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM0_Msk (0xff000000UL) /*!< PORTNUM0 (Bitfield-Mask: 0xff) */ +/* ======================================================= STATUS_P0 ======================================================= */ + #define R_ETHSW_STATUS_P0_PHYSPEED_Pos (0UL) /*!< PHYSPEED (Bit 0) */ + #define R_ETHSW_STATUS_P0_PHYSPEED_Msk (0x3UL) /*!< PHYSPEED (Bitfield-Mask: 0x03) */ + #define R_ETHSW_STATUS_P0_PHYLINK_Pos (2UL) /*!< PHYLINK (Bit 2) */ + #define R_ETHSW_STATUS_P0_PHYLINK_Msk (0x4UL) /*!< PHYLINK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P0_PHYDUPLEX_Pos (3UL) /*!< PHYDUPLEX (Bit 3) */ + #define R_ETHSW_STATUS_P0_PHYDUPLEX_Msk (0x8UL) /*!< PHYDUPLEX (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P0_TX_UNDFLW_Pos (4UL) /*!< TX_UNDFLW (Bit 4) */ + #define R_ETHSW_STATUS_P0_TX_UNDFLW_Msk (0x10UL) /*!< TX_UNDFLW (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P0_LK_DST_ERR_Pos (5UL) /*!< LK_DST_ERR (Bit 5) */ + #define R_ETHSW_STATUS_P0_LK_DST_ERR_Msk (0x20UL) /*!< LK_DST_ERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P0_BR_VERIF_ST_Pos (6UL) /*!< BR_VERIF_ST (Bit 6) */ + #define R_ETHSW_STATUS_P0_BR_VERIF_ST_Msk (0x1c0UL) /*!< BR_VERIF_ST (Bitfield-Mask: 0x07) */ +/* ======================================================= STATUS_P1 ======================================================= */ + #define R_ETHSW_STATUS_P1_PHYSPEED_Pos (0UL) /*!< PHYSPEED (Bit 0) */ + #define R_ETHSW_STATUS_P1_PHYSPEED_Msk (0x3UL) /*!< PHYSPEED (Bitfield-Mask: 0x03) */ + #define R_ETHSW_STATUS_P1_PHYLINK_Pos (2UL) /*!< PHYLINK (Bit 2) */ + #define R_ETHSW_STATUS_P1_PHYLINK_Msk (0x4UL) /*!< PHYLINK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P1_PHYDUPLEX_Pos (3UL) /*!< PHYDUPLEX (Bit 3) */ + #define R_ETHSW_STATUS_P1_PHYDUPLEX_Msk (0x8UL) /*!< PHYDUPLEX (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P1_TX_UNDFLW_Pos (4UL) /*!< TX_UNDFLW (Bit 4) */ + #define R_ETHSW_STATUS_P1_TX_UNDFLW_Msk (0x10UL) /*!< TX_UNDFLW (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P1_LK_DST_ERR_Pos (5UL) /*!< LK_DST_ERR (Bit 5) */ + #define R_ETHSW_STATUS_P1_LK_DST_ERR_Msk (0x20UL) /*!< LK_DST_ERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P1_BR_VERIF_ST_Pos (6UL) /*!< BR_VERIF_ST (Bit 6) */ + #define R_ETHSW_STATUS_P1_BR_VERIF_ST_Msk (0x1c0UL) /*!< BR_VERIF_ST (Bitfield-Mask: 0x07) */ +/* ======================================================= STATUS_P2 ======================================================= */ + #define R_ETHSW_STATUS_P2_PHYSPEED_Pos (0UL) /*!< PHYSPEED (Bit 0) */ + #define R_ETHSW_STATUS_P2_PHYSPEED_Msk (0x3UL) /*!< PHYSPEED (Bitfield-Mask: 0x03) */ + #define R_ETHSW_STATUS_P2_PHYLINK_Pos (2UL) /*!< PHYLINK (Bit 2) */ + #define R_ETHSW_STATUS_P2_PHYLINK_Msk (0x4UL) /*!< PHYLINK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P2_PHYDUPLEX_Pos (3UL) /*!< PHYDUPLEX (Bit 3) */ + #define R_ETHSW_STATUS_P2_PHYDUPLEX_Msk (0x8UL) /*!< PHYDUPLEX (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P2_TX_UNDFLW_Pos (4UL) /*!< TX_UNDFLW (Bit 4) */ + #define R_ETHSW_STATUS_P2_TX_UNDFLW_Msk (0x10UL) /*!< TX_UNDFLW (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P2_LK_DST_ERR_Pos (5UL) /*!< LK_DST_ERR (Bit 5) */ + #define R_ETHSW_STATUS_P2_LK_DST_ERR_Msk (0x20UL) /*!< LK_DST_ERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P2_BR_VERIF_ST_Pos (6UL) /*!< BR_VERIF_ST (Bit 6) */ + #define R_ETHSW_STATUS_P2_BR_VERIF_ST_Msk (0x1c0UL) /*!< BR_VERIF_ST (Bitfield-Mask: 0x07) */ +/* ======================================================= STATUS_P3 ======================================================= */ + #define R_ETHSW_STATUS_P3_PHYSPEED_Pos (0UL) /*!< PHYSPEED (Bit 0) */ + #define R_ETHSW_STATUS_P3_PHYSPEED_Msk (0x3UL) /*!< PHYSPEED (Bitfield-Mask: 0x03) */ + #define R_ETHSW_STATUS_P3_PHYLINK_Pos (2UL) /*!< PHYLINK (Bit 2) */ + #define R_ETHSW_STATUS_P3_PHYLINK_Msk (0x4UL) /*!< PHYLINK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P3_PHYDUPLEX_Pos (3UL) /*!< PHYDUPLEX (Bit 3) */ + #define R_ETHSW_STATUS_P3_PHYDUPLEX_Msk (0x8UL) /*!< PHYDUPLEX (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P3_TX_UNDFLW_Pos (4UL) /*!< TX_UNDFLW (Bit 4) */ + #define R_ETHSW_STATUS_P3_TX_UNDFLW_Msk (0x10UL) /*!< TX_UNDFLW (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P3_LK_DST_ERR_Pos (5UL) /*!< LK_DST_ERR (Bit 5) */ + #define R_ETHSW_STATUS_P3_LK_DST_ERR_Msk (0x20UL) /*!< LK_DST_ERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P3_BR_VERIF_ST_Pos (6UL) /*!< BR_VERIF_ST (Bit 6) */ + #define R_ETHSW_STATUS_P3_BR_VERIF_ST_Msk (0x1c0UL) /*!< BR_VERIF_ST (Bitfield-Mask: 0x07) */ +/* =================================================== TX_IPG_LENGTH_P0 ==================================================== */ + #define R_ETHSW_TX_IPG_LENGTH_P0_TX_IPG_LENGTH_Pos (0UL) /*!< TX_IPG_LENGTH (Bit 0) */ + #define R_ETHSW_TX_IPG_LENGTH_P0_TX_IPG_LENGTH_Msk (0x1fUL) /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f) */ + #define R_ETHSW_TX_IPG_LENGTH_P0_MINRTC3GAP_Pos (16UL) /*!< MINRTC3GAP (Bit 16) */ + #define R_ETHSW_TX_IPG_LENGTH_P0_MINRTC3GAP_Msk (0x1f0000UL) /*!< MINRTC3GAP (Bitfield-Mask: 0x1f) */ +/* =================================================== TX_IPG_LENGTH_P1 ==================================================== */ + #define R_ETHSW_TX_IPG_LENGTH_P1_TX_IPG_LENGTH_Pos (0UL) /*!< TX_IPG_LENGTH (Bit 0) */ + #define R_ETHSW_TX_IPG_LENGTH_P1_TX_IPG_LENGTH_Msk (0x1fUL) /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f) */ + #define R_ETHSW_TX_IPG_LENGTH_P1_MINRTC3GAP_Pos (16UL) /*!< MINRTC3GAP (Bit 16) */ + #define R_ETHSW_TX_IPG_LENGTH_P1_MINRTC3GAP_Msk (0x1f0000UL) /*!< MINRTC3GAP (Bitfield-Mask: 0x1f) */ +/* =================================================== TX_IPG_LENGTH_P2 ==================================================== */ + #define R_ETHSW_TX_IPG_LENGTH_P2_TX_IPG_LENGTH_Pos (0UL) /*!< TX_IPG_LENGTH (Bit 0) */ + #define R_ETHSW_TX_IPG_LENGTH_P2_TX_IPG_LENGTH_Msk (0x1fUL) /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f) */ + #define R_ETHSW_TX_IPG_LENGTH_P2_MINRTC3GAP_Pos (16UL) /*!< MINRTC3GAP (Bit 16) */ + #define R_ETHSW_TX_IPG_LENGTH_P2_MINRTC3GAP_Msk (0x1f0000UL) /*!< MINRTC3GAP (Bitfield-Mask: 0x1f) */ +/* =================================================== TX_IPG_LENGTH_P3 ==================================================== */ + #define R_ETHSW_TX_IPG_LENGTH_P3_TX_IPG_LENGTH_Pos (0UL) /*!< TX_IPG_LENGTH (Bit 0) */ + #define R_ETHSW_TX_IPG_LENGTH_P3_TX_IPG_LENGTH_Msk (0x1fUL) /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f) */ + #define R_ETHSW_TX_IPG_LENGTH_P3_MINRTC3GAP_Pos (16UL) /*!< MINRTC3GAP (Bit 16) */ + #define R_ETHSW_TX_IPG_LENGTH_P3_MINRTC3GAP_Msk (0x1f0000UL) /*!< MINRTC3GAP (Bitfield-Mask: 0x1f) */ +/* ==================================================== EEE_CTL_STAT_P0 ==================================================== */ + #define R_ETHSW_EEE_CTL_STAT_P0_EEE_AUTO_Pos (0UL) /*!< EEE_AUTO (Bit 0) */ + #define R_ETHSW_EEE_CTL_STAT_P0_EEE_AUTO_Msk (0x1UL) /*!< EEE_AUTO (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_LPI_REQ_Pos (1UL) /*!< LPI_REQ (Bit 1) */ + #define R_ETHSW_EEE_CTL_STAT_P0_LPI_REQ_Msk (0x2UL) /*!< LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_LPI_TXHOLD_Pos (2UL) /*!< LPI_TXHOLD (Bit 2) */ + #define R_ETHSW_EEE_CTL_STAT_P0_LPI_TXHOLD_Msk (0x4UL) /*!< LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_REQ_Pos (8UL) /*!< ST_LPI_REQ (Bit 8) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_REQ_Msk (0x100UL) /*!< ST_LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_TXHOLD_Pos (9UL) /*!< ST_LPI_TXHOLD (Bit 9) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_TXHOLD_Msk (0x200UL) /*!< ST_LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXBUSY_Pos (10UL) /*!< ST_TXBUSY (Bit 10) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXBUSY_Msk (0x400UL) /*!< ST_TXBUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXAVAIL_Pos (11UL) /*!< ST_TXAVAIL (Bit 11) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXAVAIL_Msk (0x800UL) /*!< ST_TXAVAIL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_IND_Pos (12UL) /*!< ST_LPI_IND (Bit 12) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_IND_Msk (0x1000UL) /*!< ST_LPI_IND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_REQ_Pos (16UL) /*!< STLH_LPI_REQ (Bit 16) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_REQ_Msk (0x10000UL) /*!< STLH_LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_TXHOLD_Pos (17UL) /*!< STLH_LPI_TXHOLD (Bit 17) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_TXHOLD_Msk (0x20000UL) /*!< STLH_LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_TXBUSY_Pos (18UL) /*!< STLH_TXBUSY (Bit 18) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_TXBUSY_Msk (0x40000UL) /*!< STLH_TXBUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_IND_Pos (20UL) /*!< STLH_LPI_IND (Bit 20) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_IND_Msk (0x100000UL) /*!< STLH_LPI_IND (Bitfield-Mask: 0x01) */ +/* ==================================================== EEE_CTL_STAT_P1 ==================================================== */ + #define R_ETHSW_EEE_CTL_STAT_P1_EEE_AUTO_Pos (0UL) /*!< EEE_AUTO (Bit 0) */ + #define R_ETHSW_EEE_CTL_STAT_P1_EEE_AUTO_Msk (0x1UL) /*!< EEE_AUTO (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_LPI_REQ_Pos (1UL) /*!< LPI_REQ (Bit 1) */ + #define R_ETHSW_EEE_CTL_STAT_P1_LPI_REQ_Msk (0x2UL) /*!< LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_LPI_TXHOLD_Pos (2UL) /*!< LPI_TXHOLD (Bit 2) */ + #define R_ETHSW_EEE_CTL_STAT_P1_LPI_TXHOLD_Msk (0x4UL) /*!< LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_REQ_Pos (8UL) /*!< ST_LPI_REQ (Bit 8) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_REQ_Msk (0x100UL) /*!< ST_LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_TXHOLD_Pos (9UL) /*!< ST_LPI_TXHOLD (Bit 9) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_TXHOLD_Msk (0x200UL) /*!< ST_LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXBUSY_Pos (10UL) /*!< ST_TXBUSY (Bit 10) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXBUSY_Msk (0x400UL) /*!< ST_TXBUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXAVAIL_Pos (11UL) /*!< ST_TXAVAIL (Bit 11) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXAVAIL_Msk (0x800UL) /*!< ST_TXAVAIL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_IND_Pos (12UL) /*!< ST_LPI_IND (Bit 12) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_IND_Msk (0x1000UL) /*!< ST_LPI_IND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_REQ_Pos (16UL) /*!< STLH_LPI_REQ (Bit 16) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_REQ_Msk (0x10000UL) /*!< STLH_LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_TXHOLD_Pos (17UL) /*!< STLH_LPI_TXHOLD (Bit 17) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_TXHOLD_Msk (0x20000UL) /*!< STLH_LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_TXBUSY_Pos (18UL) /*!< STLH_TXBUSY (Bit 18) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_TXBUSY_Msk (0x40000UL) /*!< STLH_TXBUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_IND_Pos (20UL) /*!< STLH_LPI_IND (Bit 20) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_IND_Msk (0x100000UL) /*!< STLH_LPI_IND (Bitfield-Mask: 0x01) */ +/* ==================================================== EEE_CTL_STAT_P2 ==================================================== */ + #define R_ETHSW_EEE_CTL_STAT_P2_EEE_AUTO_Pos (0UL) /*!< EEE_AUTO (Bit 0) */ + #define R_ETHSW_EEE_CTL_STAT_P2_EEE_AUTO_Msk (0x1UL) /*!< EEE_AUTO (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_LPI_REQ_Pos (1UL) /*!< LPI_REQ (Bit 1) */ + #define R_ETHSW_EEE_CTL_STAT_P2_LPI_REQ_Msk (0x2UL) /*!< LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_LPI_TXHOLD_Pos (2UL) /*!< LPI_TXHOLD (Bit 2) */ + #define R_ETHSW_EEE_CTL_STAT_P2_LPI_TXHOLD_Msk (0x4UL) /*!< LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_REQ_Pos (8UL) /*!< ST_LPI_REQ (Bit 8) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_REQ_Msk (0x100UL) /*!< ST_LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_TXHOLD_Pos (9UL) /*!< ST_LPI_TXHOLD (Bit 9) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_TXHOLD_Msk (0x200UL) /*!< ST_LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXBUSY_Pos (10UL) /*!< ST_TXBUSY (Bit 10) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXBUSY_Msk (0x400UL) /*!< ST_TXBUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXAVAIL_Pos (11UL) /*!< ST_TXAVAIL (Bit 11) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXAVAIL_Msk (0x800UL) /*!< ST_TXAVAIL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_IND_Pos (12UL) /*!< ST_LPI_IND (Bit 12) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_IND_Msk (0x1000UL) /*!< ST_LPI_IND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_REQ_Pos (16UL) /*!< STLH_LPI_REQ (Bit 16) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_REQ_Msk (0x10000UL) /*!< STLH_LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_TXHOLD_Pos (17UL) /*!< STLH_LPI_TXHOLD (Bit 17) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_TXHOLD_Msk (0x20000UL) /*!< STLH_LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_TXBUSY_Pos (18UL) /*!< STLH_TXBUSY (Bit 18) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_TXBUSY_Msk (0x40000UL) /*!< STLH_TXBUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_IND_Pos (20UL) /*!< STLH_LPI_IND (Bit 20) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_IND_Msk (0x100000UL) /*!< STLH_LPI_IND (Bitfield-Mask: 0x01) */ +/* =================================================== EEE_IDLE_TIME_P0 ==================================================== */ + #define R_ETHSW_EEE_IDLE_TIME_P0_EEE_IDLE_TIME_Pos (0UL) /*!< EEE_IDLE_TIME (Bit 0) */ + #define R_ETHSW_EEE_IDLE_TIME_P0_EEE_IDLE_TIME_Msk (0xffffffffUL) /*!< EEE_IDLE_TIME (Bitfield-Mask: 0xffffffff) */ +/* =================================================== EEE_IDLE_TIME_P1 ==================================================== */ + #define R_ETHSW_EEE_IDLE_TIME_P1_EEE_IDLE_TIME_Pos (0UL) /*!< EEE_IDLE_TIME (Bit 0) */ + #define R_ETHSW_EEE_IDLE_TIME_P1_EEE_IDLE_TIME_Msk (0xffffffffUL) /*!< EEE_IDLE_TIME (Bitfield-Mask: 0xffffffff) */ +/* =================================================== EEE_IDLE_TIME_P2 ==================================================== */ + #define R_ETHSW_EEE_IDLE_TIME_P2_EEE_IDLE_TIME_Pos (0UL) /*!< EEE_IDLE_TIME (Bit 0) */ + #define R_ETHSW_EEE_IDLE_TIME_P2_EEE_IDLE_TIME_Msk (0xffffffffUL) /*!< EEE_IDLE_TIME (Bitfield-Mask: 0xffffffff) */ +/* =================================================== EEE_TWSYS_TIME_P0 =================================================== */ + #define R_ETHSW_EEE_TWSYS_TIME_P0_EEE_WKUP_TIME_Pos (0UL) /*!< EEE_WKUP_TIME (Bit 0) */ + #define R_ETHSW_EEE_TWSYS_TIME_P0_EEE_WKUP_TIME_Msk (0xffffffffUL) /*!< EEE_WKUP_TIME (Bitfield-Mask: 0xffffffff) */ +/* =================================================== EEE_TWSYS_TIME_P1 =================================================== */ + #define R_ETHSW_EEE_TWSYS_TIME_P1_EEE_WKUP_TIME_Pos (0UL) /*!< EEE_WKUP_TIME (Bit 0) */ + #define R_ETHSW_EEE_TWSYS_TIME_P1_EEE_WKUP_TIME_Msk (0xffffffffUL) /*!< EEE_WKUP_TIME (Bitfield-Mask: 0xffffffff) */ +/* =================================================== EEE_TWSYS_TIME_P2 =================================================== */ + #define R_ETHSW_EEE_TWSYS_TIME_P2_EEE_WKUP_TIME_Pos (0UL) /*!< EEE_WKUP_TIME (Bit 0) */ + #define R_ETHSW_EEE_TWSYS_TIME_P2_EEE_WKUP_TIME_Msk (0xffffffffUL) /*!< EEE_WKUP_TIME (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IDLE_SLOPE_P0 ===================================================== */ + #define R_ETHSW_IDLE_SLOPE_P0_IDLE_SLOPE_Pos (0UL) /*!< IDLE_SLOPE (Bit 0) */ + #define R_ETHSW_IDLE_SLOPE_P0_IDLE_SLOPE_Msk (0x7ffUL) /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff) */ +/* ===================================================== IDLE_SLOPE_P1 ===================================================== */ + #define R_ETHSW_IDLE_SLOPE_P1_IDLE_SLOPE_Pos (0UL) /*!< IDLE_SLOPE (Bit 0) */ + #define R_ETHSW_IDLE_SLOPE_P1_IDLE_SLOPE_Msk (0x7ffUL) /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff) */ +/* ===================================================== IDLE_SLOPE_P2 ===================================================== */ + #define R_ETHSW_IDLE_SLOPE_P2_IDLE_SLOPE_Pos (0UL) /*!< IDLE_SLOPE (Bit 0) */ + #define R_ETHSW_IDLE_SLOPE_P2_IDLE_SLOPE_Msk (0x7ffUL) /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff) */ +/* ===================================================== IDLE_SLOPE_P3 ===================================================== */ + #define R_ETHSW_IDLE_SLOPE_P3_IDLE_SLOPE_Pos (0UL) /*!< IDLE_SLOPE (Bit 0) */ + #define R_ETHSW_IDLE_SLOPE_P3_IDLE_SLOPE_Msk (0x7ffUL) /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff) */ +/* ====================================================== CT_DELAY_P0 ====================================================== */ + #define R_ETHSW_CT_DELAY_P0_CT_DELAY_Pos (0UL) /*!< CT_DELAY (Bit 0) */ + #define R_ETHSW_CT_DELAY_P0_CT_DELAY_Msk (0x1ffUL) /*!< CT_DELAY (Bitfield-Mask: 0x1ff) */ +/* ====================================================== CT_DELAY_P1 ====================================================== */ + #define R_ETHSW_CT_DELAY_P1_CT_DELAY_Pos (0UL) /*!< CT_DELAY (Bit 0) */ + #define R_ETHSW_CT_DELAY_P1_CT_DELAY_Msk (0x1ffUL) /*!< CT_DELAY (Bitfield-Mask: 0x1ff) */ +/* ====================================================== CT_DELAY_P2 ====================================================== */ + #define R_ETHSW_CT_DELAY_P2_CT_DELAY_Pos (0UL) /*!< CT_DELAY (Bit 0) */ + #define R_ETHSW_CT_DELAY_P2_CT_DELAY_Msk (0x1ffUL) /*!< CT_DELAY (Bitfield-Mask: 0x1ff) */ +/* ===================================================== BR_CONTROL_P0 ===================================================== */ + #define R_ETHSW_BR_CONTROL_P0_PREEMPT_ENA_Pos (0UL) /*!< PREEMPT_ENA (Bit 0) */ + #define R_ETHSW_BR_CONTROL_P0_PREEMPT_ENA_Msk (0x1UL) /*!< PREEMPT_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P0_VERIFY_DIS_Pos (1UL) /*!< VERIFY_DIS (Bit 1) */ + #define R_ETHSW_BR_CONTROL_P0_VERIFY_DIS_Msk (0x2UL) /*!< VERIFY_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P0_RESPONSE_DIS_Pos (2UL) /*!< RESPONSE_DIS (Bit 2) */ + #define R_ETHSW_BR_CONTROL_P0_RESPONSE_DIS_Msk (0x4UL) /*!< RESPONSE_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P0_ADDFRAGSIZE_Pos (4UL) /*!< ADDFRAGSIZE (Bit 4) */ + #define R_ETHSW_BR_CONTROL_P0_ADDFRAGSIZE_Msk (0x30UL) /*!< ADDFRAGSIZE (Bitfield-Mask: 0x03) */ + #define R_ETHSW_BR_CONTROL_P0_TX_VERIFY_TIME_Pos (8UL) /*!< TX_VERIFY_TIME (Bit 8) */ + #define R_ETHSW_BR_CONTROL_P0_TX_VERIFY_TIME_Msk (0x7f00UL) /*!< TX_VERIFY_TIME (Bitfield-Mask: 0x7f) */ + #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_PRE_Pos (16UL) /*!< RX_STRICT_PRE (Bit 16) */ + #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_PRE_Msk (0x10000UL) /*!< RX_STRICT_PRE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P0_RX_BR_SMD_DIS_Pos (17UL) /*!< RX_BR_SMD_DIS (Bit 17) */ + #define R_ETHSW_BR_CONTROL_P0_RX_BR_SMD_DIS_Msk (0x20000UL) /*!< RX_BR_SMD_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_BR_CTL_Pos (18UL) /*!< RX_STRICT_BR_CTL (Bit 18) */ + #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_BR_CTL_Msk (0x40000UL) /*!< RX_STRICT_BR_CTL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P0_TX_MCRC_INV_Pos (19UL) /*!< TX_MCRC_INV (Bit 19) */ + #define R_ETHSW_BR_CONTROL_P0_TX_MCRC_INV_Msk (0x80000UL) /*!< TX_MCRC_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P0_RX_MCRC_INV_Pos (20UL) /*!< RX_MCRC_INV (Bit 20) */ + #define R_ETHSW_BR_CONTROL_P0_RX_MCRC_INV_Msk (0x100000UL) /*!< RX_MCRC_INV (Bitfield-Mask: 0x01) */ +/* ===================================================== BR_CONTROL_P1 ===================================================== */ + #define R_ETHSW_BR_CONTROL_P1_PREEMPT_ENA_Pos (0UL) /*!< PREEMPT_ENA (Bit 0) */ + #define R_ETHSW_BR_CONTROL_P1_PREEMPT_ENA_Msk (0x1UL) /*!< PREEMPT_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P1_VERIFY_DIS_Pos (1UL) /*!< VERIFY_DIS (Bit 1) */ + #define R_ETHSW_BR_CONTROL_P1_VERIFY_DIS_Msk (0x2UL) /*!< VERIFY_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P1_RESPONSE_DIS_Pos (2UL) /*!< RESPONSE_DIS (Bit 2) */ + #define R_ETHSW_BR_CONTROL_P1_RESPONSE_DIS_Msk (0x4UL) /*!< RESPONSE_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P1_ADDFRAGSIZE_Pos (4UL) /*!< ADDFRAGSIZE (Bit 4) */ + #define R_ETHSW_BR_CONTROL_P1_ADDFRAGSIZE_Msk (0x30UL) /*!< ADDFRAGSIZE (Bitfield-Mask: 0x03) */ + #define R_ETHSW_BR_CONTROL_P1_TX_VERIFY_TIME_Pos (8UL) /*!< TX_VERIFY_TIME (Bit 8) */ + #define R_ETHSW_BR_CONTROL_P1_TX_VERIFY_TIME_Msk (0x7f00UL) /*!< TX_VERIFY_TIME (Bitfield-Mask: 0x7f) */ + #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_PRE_Pos (16UL) /*!< RX_STRICT_PRE (Bit 16) */ + #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_PRE_Msk (0x10000UL) /*!< RX_STRICT_PRE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P1_RX_BR_SMD_DIS_Pos (17UL) /*!< RX_BR_SMD_DIS (Bit 17) */ + #define R_ETHSW_BR_CONTROL_P1_RX_BR_SMD_DIS_Msk (0x20000UL) /*!< RX_BR_SMD_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_BR_CTL_Pos (18UL) /*!< RX_STRICT_BR_CTL (Bit 18) */ + #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_BR_CTL_Msk (0x40000UL) /*!< RX_STRICT_BR_CTL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P1_TX_MCRC_INV_Pos (19UL) /*!< TX_MCRC_INV (Bit 19) */ + #define R_ETHSW_BR_CONTROL_P1_TX_MCRC_INV_Msk (0x80000UL) /*!< TX_MCRC_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P1_RX_MCRC_INV_Pos (20UL) /*!< RX_MCRC_INV (Bit 20) */ + #define R_ETHSW_BR_CONTROL_P1_RX_MCRC_INV_Msk (0x100000UL) /*!< RX_MCRC_INV (Bitfield-Mask: 0x01) */ +/* ===================================================== BR_CONTROL_P2 ===================================================== */ + #define R_ETHSW_BR_CONTROL_P2_PREEMPT_ENA_Pos (0UL) /*!< PREEMPT_ENA (Bit 0) */ + #define R_ETHSW_BR_CONTROL_P2_PREEMPT_ENA_Msk (0x1UL) /*!< PREEMPT_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P2_VERIFY_DIS_Pos (1UL) /*!< VERIFY_DIS (Bit 1) */ + #define R_ETHSW_BR_CONTROL_P2_VERIFY_DIS_Msk (0x2UL) /*!< VERIFY_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P2_RESPONSE_DIS_Pos (2UL) /*!< RESPONSE_DIS (Bit 2) */ + #define R_ETHSW_BR_CONTROL_P2_RESPONSE_DIS_Msk (0x4UL) /*!< RESPONSE_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P2_ADDFRAGSIZE_Pos (4UL) /*!< ADDFRAGSIZE (Bit 4) */ + #define R_ETHSW_BR_CONTROL_P2_ADDFRAGSIZE_Msk (0x30UL) /*!< ADDFRAGSIZE (Bitfield-Mask: 0x03) */ + #define R_ETHSW_BR_CONTROL_P2_TX_VERIFY_TIME_Pos (8UL) /*!< TX_VERIFY_TIME (Bit 8) */ + #define R_ETHSW_BR_CONTROL_P2_TX_VERIFY_TIME_Msk (0x7f00UL) /*!< TX_VERIFY_TIME (Bitfield-Mask: 0x7f) */ + #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_PRE_Pos (16UL) /*!< RX_STRICT_PRE (Bit 16) */ + #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_PRE_Msk (0x10000UL) /*!< RX_STRICT_PRE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P2_RX_BR_SMD_DIS_Pos (17UL) /*!< RX_BR_SMD_DIS (Bit 17) */ + #define R_ETHSW_BR_CONTROL_P2_RX_BR_SMD_DIS_Msk (0x20000UL) /*!< RX_BR_SMD_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_BR_CTL_Pos (18UL) /*!< RX_STRICT_BR_CTL (Bit 18) */ + #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_BR_CTL_Msk (0x40000UL) /*!< RX_STRICT_BR_CTL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P2_TX_MCRC_INV_Pos (19UL) /*!< TX_MCRC_INV (Bit 19) */ + #define R_ETHSW_BR_CONTROL_P2_TX_MCRC_INV_Msk (0x80000UL) /*!< TX_MCRC_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P2_RX_MCRC_INV_Pos (20UL) /*!< RX_MCRC_INV (Bit 20) */ + #define R_ETHSW_BR_CONTROL_P2_RX_MCRC_INV_Msk (0x100000UL) /*!< RX_MCRC_INV (Bitfield-Mask: 0x01) */ +/* ================================================ AFRAMESTRANSMITTEDOK_P0 ================================================ */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P0_TXVALIDCOUNT_Pos (0UL) /*!< TXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P0_TXVALIDCOUNT_Msk (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AFRAMESTRANSMITTEDOK_P1 ================================================ */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P1_TXVALIDCOUNT_Pos (0UL) /*!< TXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P1_TXVALIDCOUNT_Msk (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AFRAMESTRANSMITTEDOK_P2 ================================================ */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P2_TXVALIDCOUNT_Pos (0UL) /*!< TXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P2_TXVALIDCOUNT_Msk (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AFRAMESTRANSMITTEDOK_P3 ================================================ */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P3_TXVALIDCOUNT_Pos (0UL) /*!< TXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P3_TXVALIDCOUNT_Msk (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AFRAMESRECEIVEDOK_P0 ================================================== */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P0_RXVALIDCOUNT_Pos (0UL) /*!< RXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P0_RXVALIDCOUNT_Msk (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AFRAMESRECEIVEDOK_P1 ================================================== */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P1_RXVALIDCOUNT_Pos (0UL) /*!< RXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P1_RXVALIDCOUNT_Msk (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AFRAMESRECEIVEDOK_P2 ================================================== */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P2_RXVALIDCOUNT_Pos (0UL) /*!< RXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P2_RXVALIDCOUNT_Msk (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AFRAMESRECEIVEDOK_P3 ================================================== */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P3_RXVALIDCOUNT_Pos (0UL) /*!< RXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P3_RXVALIDCOUNT_Msk (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================= AFRAMECHECKSEQUENCEERRORS_P0 ============================================== */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P0_FCSERRCOUNT_Pos (0UL) /*!< FCSERRCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P0_FCSERRCOUNT_Msk (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================= AFRAMECHECKSEQUENCEERRORS_P1 ============================================== */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P1_FCSERRCOUNT_Pos (0UL) /*!< FCSERRCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P1_FCSERRCOUNT_Msk (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================= AFRAMECHECKSEQUENCEERRORS_P2 ============================================== */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P2_FCSERRCOUNT_Pos (0UL) /*!< FCSERRCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P2_FCSERRCOUNT_Msk (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================= AFRAMECHECKSEQUENCEERRORS_P3 ============================================== */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P3_FCSERRCOUNT_Pos (0UL) /*!< FCSERRCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P3_FCSERRCOUNT_Msk (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== AALIGNMENTERRORS_P0 ================================================== */ + #define R_ETHSW_AALIGNMENTERRORS_P0_ALGNERRCOUNT_Pos (0UL) /*!< ALGNERRCOUNT (Bit 0) */ + #define R_ETHSW_AALIGNMENTERRORS_P0_ALGNERRCOUNT_Msk (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== AALIGNMENTERRORS_P1 ================================================== */ + #define R_ETHSW_AALIGNMENTERRORS_P1_ALGNERRCOUNT_Pos (0UL) /*!< ALGNERRCOUNT (Bit 0) */ + #define R_ETHSW_AALIGNMENTERRORS_P1_ALGNERRCOUNT_Msk (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== AALIGNMENTERRORS_P2 ================================================== */ + #define R_ETHSW_AALIGNMENTERRORS_P2_ALGNERRCOUNT_Pos (0UL) /*!< ALGNERRCOUNT (Bit 0) */ + #define R_ETHSW_AALIGNMENTERRORS_P2_ALGNERRCOUNT_Msk (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== AALIGNMENTERRORS_P3 ================================================== */ + #define R_ETHSW_AALIGNMENTERRORS_P3_ALGNERRCOUNT_Pos (0UL) /*!< ALGNERRCOUNT (Bit 0) */ + #define R_ETHSW_AALIGNMENTERRORS_P3_ALGNERRCOUNT_Msk (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AOCTETSTRANSMITTEDOK_P0 ================================================ */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P0_TXVALIDOCTETS_Pos (0UL) /*!< TXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P0_TXVALIDOCTETS_Msk (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AOCTETSTRANSMITTEDOK_P1 ================================================ */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P1_TXVALIDOCTETS_Pos (0UL) /*!< TXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P1_TXVALIDOCTETS_Msk (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AOCTETSTRANSMITTEDOK_P2 ================================================ */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P2_TXVALIDOCTETS_Pos (0UL) /*!< TXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P2_TXVALIDOCTETS_Msk (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AOCTETSTRANSMITTEDOK_P3 ================================================ */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P3_TXVALIDOCTETS_Pos (0UL) /*!< TXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P3_TXVALIDOCTETS_Msk (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AOCTETSRECEIVEDOK_P0 ================================================== */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P0_RXVALIDOCTETS_Pos (0UL) /*!< RXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P0_RXVALIDOCTETS_Msk (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AOCTETSRECEIVEDOK_P1 ================================================== */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P1_RXVALIDOCTETS_Pos (0UL) /*!< RXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P1_RXVALIDOCTETS_Msk (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AOCTETSRECEIVEDOK_P2 ================================================== */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P2_RXVALIDOCTETS_Pos (0UL) /*!< RXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P2_RXVALIDOCTETS_Msk (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AOCTETSRECEIVEDOK_P3 ================================================== */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P3_RXVALIDOCTETS_Pos (0UL) /*!< RXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P3_RXVALIDOCTETS_Msk (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ATXPAUSEMACCTRLFRAMES_P0 ================================================ */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P0_TXPAUSECOUNT_Pos (0UL) /*!< TXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P0_TXPAUSECOUNT_Msk (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ATXPAUSEMACCTRLFRAMES_P1 ================================================ */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P1_TXPAUSECOUNT_Pos (0UL) /*!< TXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P1_TXPAUSECOUNT_Msk (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ATXPAUSEMACCTRLFRAMES_P2 ================================================ */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P2_TXPAUSECOUNT_Pos (0UL) /*!< TXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P2_TXPAUSECOUNT_Msk (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ATXPAUSEMACCTRLFRAMES_P3 ================================================ */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P3_TXPAUSECOUNT_Pos (0UL) /*!< TXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P3_TXPAUSECOUNT_Msk (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ARXPAUSEMACCTRLFRAMES_P0 ================================================ */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P0_RXPAUSECOUNT_Pos (0UL) /*!< RXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P0_RXPAUSECOUNT_Msk (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ARXPAUSEMACCTRLFRAMES_P1 ================================================ */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P1_RXPAUSECOUNT_Pos (0UL) /*!< RXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P1_RXPAUSECOUNT_Msk (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ARXPAUSEMACCTRLFRAMES_P2 ================================================ */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P2_RXPAUSECOUNT_Pos (0UL) /*!< RXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P2_RXPAUSECOUNT_Msk (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ARXPAUSEMACCTRLFRAMES_P3 ================================================ */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P3_RXPAUSECOUNT_Pos (0UL) /*!< RXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P3_RXPAUSECOUNT_Msk (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IFINERRORS_P0 ===================================================== */ + #define R_ETHSW_IFINERRORS_P0_INERRCOUNT_Pos (0UL) /*!< INERRCOUNT (Bit 0) */ + #define R_ETHSW_IFINERRORS_P0_INERRCOUNT_Msk (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IFINERRORS_P1 ===================================================== */ + #define R_ETHSW_IFINERRORS_P1_INERRCOUNT_Pos (0UL) /*!< INERRCOUNT (Bit 0) */ + #define R_ETHSW_IFINERRORS_P1_INERRCOUNT_Msk (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IFINERRORS_P2 ===================================================== */ + #define R_ETHSW_IFINERRORS_P2_INERRCOUNT_Pos (0UL) /*!< INERRCOUNT (Bit 0) */ + #define R_ETHSW_IFINERRORS_P2_INERRCOUNT_Msk (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IFINERRORS_P3 ===================================================== */ + #define R_ETHSW_IFINERRORS_P3_INERRCOUNT_Pos (0UL) /*!< INERRCOUNT (Bit 0) */ + #define R_ETHSW_IFINERRORS_P3_INERRCOUNT_Msk (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IFOUTERRORS_P0 ===================================================== */ + #define R_ETHSW_IFOUTERRORS_P0_OUTERRCOUNT_Pos (0UL) /*!< OUTERRCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTERRORS_P0_OUTERRCOUNT_Msk (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IFOUTERRORS_P1 ===================================================== */ + #define R_ETHSW_IFOUTERRORS_P1_OUTERRCOUNT_Pos (0UL) /*!< OUTERRCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTERRORS_P1_OUTERRCOUNT_Msk (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IFOUTERRORS_P2 ===================================================== */ + #define R_ETHSW_IFOUTERRORS_P2_OUTERRCOUNT_Pos (0UL) /*!< OUTERRCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTERRORS_P2_OUTERRCOUNT_Msk (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IFOUTERRORS_P3 ===================================================== */ + #define R_ETHSW_IFOUTERRORS_P3_OUTERRCOUNT_Pos (0UL) /*!< OUTERRCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTERRORS_P3_OUTERRCOUNT_Msk (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFINUCASTPKTS_P0 ==================================================== */ + #define R_ETHSW_IFINUCASTPKTS_P0_RXUCASTCOUNT_Pos (0UL) /*!< RXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINUCASTPKTS_P0_RXUCASTCOUNT_Msk (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFINUCASTPKTS_P1 ==================================================== */ + #define R_ETHSW_IFINUCASTPKTS_P1_RXUCASTCOUNT_Pos (0UL) /*!< RXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINUCASTPKTS_P1_RXUCASTCOUNT_Msk (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFINUCASTPKTS_P2 ==================================================== */ + #define R_ETHSW_IFINUCASTPKTS_P2_RXUCASTCOUNT_Pos (0UL) /*!< RXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINUCASTPKTS_P2_RXUCASTCOUNT_Msk (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFINUCASTPKTS_P3 ==================================================== */ + #define R_ETHSW_IFINUCASTPKTS_P3_RXUCASTCOUNT_Pos (0UL) /*!< RXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINUCASTPKTS_P3_RXUCASTCOUNT_Msk (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINMULTICASTPKTS_P0 ================================================== */ + #define R_ETHSW_IFINMULTICASTPKTS_P0_RXMCASTCOUNT_Pos (0UL) /*!< RXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINMULTICASTPKTS_P0_RXMCASTCOUNT_Msk (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINMULTICASTPKTS_P1 ================================================== */ + #define R_ETHSW_IFINMULTICASTPKTS_P1_RXMCASTCOUNT_Pos (0UL) /*!< RXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINMULTICASTPKTS_P1_RXMCASTCOUNT_Msk (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINMULTICASTPKTS_P2 ================================================== */ + #define R_ETHSW_IFINMULTICASTPKTS_P2_RXMCASTCOUNT_Pos (0UL) /*!< RXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINMULTICASTPKTS_P2_RXMCASTCOUNT_Msk (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINMULTICASTPKTS_P3 ================================================== */ + #define R_ETHSW_IFINMULTICASTPKTS_P3_RXMCASTCOUNT_Pos (0UL) /*!< RXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINMULTICASTPKTS_P3_RXMCASTCOUNT_Msk (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINBROADCASTPKTS_P0 ================================================== */ + #define R_ETHSW_IFINBROADCASTPKTS_P0_RXBCASTCOUNT_Pos (0UL) /*!< RXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINBROADCASTPKTS_P0_RXBCASTCOUNT_Msk (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINBROADCASTPKTS_P1 ================================================== */ + #define R_ETHSW_IFINBROADCASTPKTS_P1_RXBCASTCOUNT_Pos (0UL) /*!< RXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINBROADCASTPKTS_P1_RXBCASTCOUNT_Msk (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINBROADCASTPKTS_P2 ================================================== */ + #define R_ETHSW_IFINBROADCASTPKTS_P2_RXBCASTCOUNT_Pos (0UL) /*!< RXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINBROADCASTPKTS_P2_RXBCASTCOUNT_Msk (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINBROADCASTPKTS_P3 ================================================== */ + #define R_ETHSW_IFINBROADCASTPKTS_P3_RXBCASTCOUNT_Pos (0UL) /*!< RXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINBROADCASTPKTS_P3_RXBCASTCOUNT_Msk (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTDISCARDS_P0 ==================================================== */ + #define R_ETHSW_IFOUTDISCARDS_P0_DISCOBCOUNT_Pos (0UL) /*!< DISCOBCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTDISCARDS_P0_DISCOBCOUNT_Msk (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTDISCARDS_P1 ==================================================== */ + #define R_ETHSW_IFOUTDISCARDS_P1_DISCOBCOUNT_Pos (0UL) /*!< DISCOBCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTDISCARDS_P1_DISCOBCOUNT_Msk (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTDISCARDS_P2 ==================================================== */ + #define R_ETHSW_IFOUTDISCARDS_P2_DISCOBCOUNT_Pos (0UL) /*!< DISCOBCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTDISCARDS_P2_DISCOBCOUNT_Msk (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTDISCARDS_P3 ==================================================== */ + #define R_ETHSW_IFOUTDISCARDS_P3_DISCOBCOUNT_Pos (0UL) /*!< DISCOBCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTDISCARDS_P3_DISCOBCOUNT_Msk (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTUCASTPKTS_P0 =================================================== */ + #define R_ETHSW_IFOUTUCASTPKTS_P0_TXUCASTCOUNT_Pos (0UL) /*!< TXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTUCASTPKTS_P0_TXUCASTCOUNT_Msk (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTUCASTPKTS_P1 =================================================== */ + #define R_ETHSW_IFOUTUCASTPKTS_P1_TXUCASTCOUNT_Pos (0UL) /*!< TXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTUCASTPKTS_P1_TXUCASTCOUNT_Msk (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTUCASTPKTS_P2 =================================================== */ + #define R_ETHSW_IFOUTUCASTPKTS_P2_TXUCASTCOUNT_Pos (0UL) /*!< TXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTUCASTPKTS_P2_TXUCASTCOUNT_Msk (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTUCASTPKTS_P3 =================================================== */ + #define R_ETHSW_IFOUTUCASTPKTS_P3_TXUCASTCOUNT_Pos (0UL) /*!< TXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTUCASTPKTS_P3_TXUCASTCOUNT_Msk (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTMULTICASTPKTS_P0 ================================================= */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P0_TXMCASTCOUNT_Pos (0UL) /*!< TXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P0_TXMCASTCOUNT_Msk (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTMULTICASTPKTS_P1 ================================================= */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P1_TXMCASTCOUNT_Pos (0UL) /*!< TXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P1_TXMCASTCOUNT_Msk (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTMULTICASTPKTS_P2 ================================================= */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P2_TXMCASTCOUNT_Pos (0UL) /*!< TXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P2_TXMCASTCOUNT_Msk (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTMULTICASTPKTS_P3 ================================================= */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P3_TXMCASTCOUNT_Pos (0UL) /*!< TXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P3_TXMCASTCOUNT_Msk (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTBROADCASTPKTS_P0 ================================================= */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P0_TXBCASTCOUNT_Pos (0UL) /*!< TXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P0_TXBCASTCOUNT_Msk (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTBROADCASTPKTS_P1 ================================================= */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P1_TXBCASTCOUNT_Pos (0UL) /*!< TXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P1_TXBCASTCOUNT_Msk (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTBROADCASTPKTS_P2 ================================================= */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P2_TXBCASTCOUNT_Pos (0UL) /*!< TXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P2_TXBCASTCOUNT_Msk (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTBROADCASTPKTS_P3 ================================================= */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P3_TXBCASTCOUNT_Pos (0UL) /*!< TXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P3_TXBCASTCOUNT_Msk (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSDROPEVENTS_P0 ================================================ */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P0_DROPCOUNT_Pos (0UL) /*!< DROPCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P0_DROPCOUNT_Msk (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSDROPEVENTS_P1 ================================================ */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P1_DROPCOUNT_Pos (0UL) /*!< DROPCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P1_DROPCOUNT_Msk (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSDROPEVENTS_P2 ================================================ */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P2_DROPCOUNT_Pos (0UL) /*!< DROPCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P2_DROPCOUNT_Msk (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSDROPEVENTS_P3 ================================================ */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P3_DROPCOUNT_Pos (0UL) /*!< DROPCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P3_DROPCOUNT_Msk (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ETHERSTATSOCTETS_P0 ================================================== */ + #define R_ETHSW_ETHERSTATSOCTETS_P0_ALLOCTETS_Pos (0UL) /*!< ALLOCTETS (Bit 0) */ + #define R_ETHSW_ETHERSTATSOCTETS_P0_ALLOCTETS_Msk (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ETHERSTATSOCTETS_P1 ================================================== */ + #define R_ETHSW_ETHERSTATSOCTETS_P1_ALLOCTETS_Pos (0UL) /*!< ALLOCTETS (Bit 0) */ + #define R_ETHSW_ETHERSTATSOCTETS_P1_ALLOCTETS_Msk (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ETHERSTATSOCTETS_P2 ================================================== */ + #define R_ETHSW_ETHERSTATSOCTETS_P2_ALLOCTETS_Pos (0UL) /*!< ALLOCTETS (Bit 0) */ + #define R_ETHSW_ETHERSTATSOCTETS_P2_ALLOCTETS_Msk (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ETHERSTATSOCTETS_P3 ================================================== */ + #define R_ETHSW_ETHERSTATSOCTETS_P3_ALLOCTETS_Pos (0UL) /*!< ALLOCTETS (Bit 0) */ + #define R_ETHSW_ETHERSTATSOCTETS_P3_ALLOCTETS_Msk (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ETHERSTATSPKTS_P0 =================================================== */ + #define R_ETHSW_ETHERSTATSPKTS_P0_ALLCOUNT_Pos (0UL) /*!< ALLCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS_P0_ALLCOUNT_Msk (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ETHERSTATSPKTS_P1 =================================================== */ + #define R_ETHSW_ETHERSTATSPKTS_P1_ALLCOUNT_Pos (0UL) /*!< ALLCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS_P1_ALLCOUNT_Msk (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ETHERSTATSPKTS_P2 =================================================== */ + #define R_ETHSW_ETHERSTATSPKTS_P2_ALLCOUNT_Pos (0UL) /*!< ALLCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS_P2_ALLCOUNT_Msk (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ETHERSTATSPKTS_P3 =================================================== */ + #define R_ETHSW_ETHERSTATSPKTS_P3_ALLCOUNT_Pos (0UL) /*!< ALLCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS_P3_ALLCOUNT_Msk (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ETHERSTATSUNDERSIZEPKTS_P0 =============================================== */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P0_TOOSHRTCOUNT_Pos (0UL) /*!< TOOSHRTCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P0_TOOSHRTCOUNT_Msk (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ETHERSTATSUNDERSIZEPKTS_P1 =============================================== */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P1_TOOSHRTCOUNT_Pos (0UL) /*!< TOOSHRTCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P1_TOOSHRTCOUNT_Msk (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ETHERSTATSUNDERSIZEPKTS_P2 =============================================== */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P2_TOOSHRTCOUNT_Pos (0UL) /*!< TOOSHRTCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P2_TOOSHRTCOUNT_Msk (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ETHERSTATSUNDERSIZEPKTS_P3 =============================================== */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P3_TOOSHRTCOUNT_Pos (0UL) /*!< TOOSHRTCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P3_TOOSHRTCOUNT_Msk (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSOVERSIZEPKTS_P0 =============================================== */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P0_TOOLONGCOUNT_Pos (0UL) /*!< TOOLONGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P0_TOOLONGCOUNT_Msk (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSOVERSIZEPKTS_P1 =============================================== */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P1_TOOLONGCOUNT_Pos (0UL) /*!< TOOLONGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P1_TOOLONGCOUNT_Msk (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSOVERSIZEPKTS_P2 =============================================== */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P2_TOOLONGCOUNT_Pos (0UL) /*!< TOOLONGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P2_TOOLONGCOUNT_Msk (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSOVERSIZEPKTS_P3 =============================================== */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P3_TOOLONGCOUNT_Pos (0UL) /*!< TOOLONGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P3_TOOLONGCOUNT_Msk (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSPKTS64OCTETS_P0 =============================================== */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P0_OCTCNT64_Pos (0UL) /*!< OCTCNT64 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P0_OCTCNT64_Msk (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSPKTS64OCTETS_P1 =============================================== */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P1_OCTCNT64_Pos (0UL) /*!< OCTCNT64 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P1_OCTCNT64_Msk (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSPKTS64OCTETS_P2 =============================================== */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P2_OCTCNT64_Pos (0UL) /*!< OCTCNT64 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P2_OCTCNT64_Msk (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSPKTS64OCTETS_P3 =============================================== */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P3_OCTCNT64_Pos (0UL) /*!< OCTCNT64 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P3_OCTCNT64_Msk (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS65TO127OCTETS_P0 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P0_OCTCNT65T127_Pos (0UL) /*!< OCTCNT65T127 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P0_OCTCNT65T127_Msk (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS65TO127OCTETS_P1 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P1_OCTCNT65T127_Pos (0UL) /*!< OCTCNT65T127 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P1_OCTCNT65T127_Msk (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS65TO127OCTETS_P2 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P2_OCTCNT65T127_Pos (0UL) /*!< OCTCNT65T127 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P2_OCTCNT65T127_Msk (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS65TO127OCTETS_P3 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P3_OCTCNT65T127_Pos (0UL) /*!< OCTCNT65T127 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P3_OCTCNT65T127_Msk (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS128TO255OCTETS_P0 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P0_OCTCNT128T255_Pos (0UL) /*!< OCTCNT128T255 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P0_OCTCNT128T255_Msk (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS128TO255OCTETS_P1 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P1_OCTCNT128T255_Pos (0UL) /*!< OCTCNT128T255 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P1_OCTCNT128T255_Msk (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS128TO255OCTETS_P2 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P2_OCTCNT128T255_Pos (0UL) /*!< OCTCNT128T255 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P2_OCTCNT128T255_Msk (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS128TO255OCTETS_P3 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P3_OCTCNT128T255_Pos (0UL) /*!< OCTCNT128T255 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P3_OCTCNT128T255_Msk (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS256TO511OCTETS_P0 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P0_OCTCNT256T511_Pos (0UL) /*!< OCTCNT256T511 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P0_OCTCNT256T511_Msk (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS256TO511OCTETS_P1 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P1_OCTCNT256T511_Pos (0UL) /*!< OCTCNT256T511 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P1_OCTCNT256T511_Msk (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS256TO511OCTETS_P2 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P2_OCTCNT256T511_Pos (0UL) /*!< OCTCNT256T511 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P2_OCTCNT256T511_Msk (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS256TO511OCTETS_P3 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P3_OCTCNT256T511_Pos (0UL) /*!< OCTCNT256T511 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P3_OCTCNT256T511_Msk (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS512TO1023OCTETS_P0 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P0_OCTCNT512T1023_Pos (0UL) /*!< OCTCNT512T1023 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P0_OCTCNT512T1023_Msk (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS512TO1023OCTETS_P1 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P1_OCTCNT512T1023_Pos (0UL) /*!< OCTCNT512T1023 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P1_OCTCNT512T1023_Msk (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS512TO1023OCTETS_P2 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P2_OCTCNT512T1023_Pos (0UL) /*!< OCTCNT512T1023 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P2_OCTCNT512T1023_Msk (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS512TO1023OCTETS_P3 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P3_OCTCNT512T1023_Pos (0UL) /*!< OCTCNT512T1023 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P3_OCTCNT512T1023_Msk (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS1024TO1518OCTETS_P0 =========================================== */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P0_OCTCNT1024T1518_Pos (0UL) /*!< OCTCNT1024T1518 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P0_OCTCNT1024T1518_Msk (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS1024TO1518OCTETS_P1 =========================================== */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P1_OCTCNT1024T1518_Pos (0UL) /*!< OCTCNT1024T1518 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P1_OCTCNT1024T1518_Msk (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS1024TO1518OCTETS_P2 =========================================== */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P2_OCTCNT1024T1518_Pos (0UL) /*!< OCTCNT1024T1518 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P2_OCTCNT1024T1518_Msk (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS1024TO1518OCTETS_P3 =========================================== */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P3_OCTCNT1024T1518_Pos (0UL) /*!< OCTCNT1024T1518 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P3_OCTCNT1024T1518_Msk (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS1519TOXOCTETS_P0 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P0_OCTCNT1519TX_Pos (0UL) /*!< OCTCNT1519TX (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P0_OCTCNT1519TX_Msk (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS1519TOXOCTETS_P1 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P1_OCTCNT1519TX_Pos (0UL) /*!< OCTCNT1519TX (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P1_OCTCNT1519TX_Msk (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS1519TOXOCTETS_P2 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P2_OCTCNT1519TX_Pos (0UL) /*!< OCTCNT1519TX (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P2_OCTCNT1519TX_Msk (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS1519TOXOCTETS_P3 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P3_OCTCNT1519TX_Pos (0UL) /*!< OCTCNT1519TX (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P3_OCTCNT1519TX_Msk (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ETHERSTATSJABBERS_P0 ================================================== */ + #define R_ETHSW_ETHERSTATSJABBERS_P0_JABBERCOUNT_Pos (0UL) /*!< JABBERCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSJABBERS_P0_JABBERCOUNT_Msk (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ETHERSTATSJABBERS_P1 ================================================== */ + #define R_ETHSW_ETHERSTATSJABBERS_P1_JABBERCOUNT_Pos (0UL) /*!< JABBERCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSJABBERS_P1_JABBERCOUNT_Msk (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ETHERSTATSJABBERS_P2 ================================================== */ + #define R_ETHSW_ETHERSTATSJABBERS_P2_JABBERCOUNT_Pos (0UL) /*!< JABBERCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSJABBERS_P2_JABBERCOUNT_Msk (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ETHERSTATSJABBERS_P3 ================================================== */ + #define R_ETHSW_ETHERSTATSJABBERS_P3_JABBERCOUNT_Pos (0UL) /*!< JABBERCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSJABBERS_P3_JABBERCOUNT_Msk (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSFRAGMENTS_P0 ================================================= */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P0_FRAGCOUNT_Pos (0UL) /*!< FRAGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P0_FRAGCOUNT_Msk (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSFRAGMENTS_P1 ================================================= */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P1_FRAGCOUNT_Pos (0UL) /*!< FRAGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P1_FRAGCOUNT_Msk (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSFRAGMENTS_P2 ================================================= */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P2_FRAGCOUNT_Pos (0UL) /*!< FRAGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P2_FRAGCOUNT_Msk (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSFRAGMENTS_P3 ================================================= */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P3_FRAGCOUNT_Pos (0UL) /*!< FRAGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P3_FRAGCOUNT_Msk (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== VLANRECEIVEDOK_P0 =================================================== */ + #define R_ETHSW_VLANRECEIVEDOK_P0_RXVLANTAGCNT_Pos (0UL) /*!< RXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANRECEIVEDOK_P0_RXVLANTAGCNT_Msk (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== VLANRECEIVEDOK_P1 =================================================== */ + #define R_ETHSW_VLANRECEIVEDOK_P1_RXVLANTAGCNT_Pos (0UL) /*!< RXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANRECEIVEDOK_P1_RXVLANTAGCNT_Msk (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== VLANRECEIVEDOK_P2 =================================================== */ + #define R_ETHSW_VLANRECEIVEDOK_P2_RXVLANTAGCNT_Pos (0UL) /*!< RXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANRECEIVEDOK_P2_RXVLANTAGCNT_Msk (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== VLANRECEIVEDOK_P3 =================================================== */ + #define R_ETHSW_VLANRECEIVEDOK_P3_RXVLANTAGCNT_Pos (0UL) /*!< RXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANRECEIVEDOK_P3_RXVLANTAGCNT_Msk (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= VLANTRANSMITTEDOK_P0 ================================================== */ + #define R_ETHSW_VLANTRANSMITTEDOK_P0_TXVLANTAGCNT_Pos (0UL) /*!< TXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANTRANSMITTEDOK_P0_TXVLANTAGCNT_Msk (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= VLANTRANSMITTEDOK_P1 ================================================== */ + #define R_ETHSW_VLANTRANSMITTEDOK_P1_TXVLANTAGCNT_Pos (0UL) /*!< TXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANTRANSMITTEDOK_P1_TXVLANTAGCNT_Msk (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= VLANTRANSMITTEDOK_P2 ================================================== */ + #define R_ETHSW_VLANTRANSMITTEDOK_P2_TXVLANTAGCNT_Pos (0UL) /*!< TXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANTRANSMITTEDOK_P2_TXVLANTAGCNT_Msk (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= VLANTRANSMITTEDOK_P3 ================================================== */ + #define R_ETHSW_VLANTRANSMITTEDOK_P3_TXVLANTAGCNT_Pos (0UL) /*!< TXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANTRANSMITTEDOK_P3_TXVLANTAGCNT_Msk (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ FRAMESRETRANSMITTED_P0 ================================================= */ + #define R_ETHSW_FRAMESRETRANSMITTED_P0_RETXCOUNT_Pos (0UL) /*!< RETXCOUNT (Bit 0) */ + #define R_ETHSW_FRAMESRETRANSMITTED_P0_RETXCOUNT_Msk (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ FRAMESRETRANSMITTED_P1 ================================================= */ + #define R_ETHSW_FRAMESRETRANSMITTED_P1_RETXCOUNT_Pos (0UL) /*!< RETXCOUNT (Bit 0) */ + #define R_ETHSW_FRAMESRETRANSMITTED_P1_RETXCOUNT_Msk (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ FRAMESRETRANSMITTED_P2 ================================================= */ + #define R_ETHSW_FRAMESRETRANSMITTED_P2_RETXCOUNT_Pos (0UL) /*!< RETXCOUNT (Bit 0) */ + #define R_ETHSW_FRAMESRETRANSMITTED_P2_RETXCOUNT_Msk (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ FRAMESRETRANSMITTED_P3 ================================================= */ + #define R_ETHSW_FRAMESRETRANSMITTED_P3_RETXCOUNT_Pos (0UL) /*!< RETXCOUNT (Bit 0) */ + #define R_ETHSW_FRAMESRETRANSMITTED_P3_RETXCOUNT_Msk (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== STATS_HIWORD_P0 ==================================================== */ + #define R_ETHSW_STATS_HIWORD_P0_STATS_HIWORD_Pos (0UL) /*!< STATS_HIWORD (Bit 0) */ + #define R_ETHSW_STATS_HIWORD_P0_STATS_HIWORD_Msk (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== STATS_HIWORD_P1 ==================================================== */ + #define R_ETHSW_STATS_HIWORD_P1_STATS_HIWORD_Pos (0UL) /*!< STATS_HIWORD (Bit 0) */ + #define R_ETHSW_STATS_HIWORD_P1_STATS_HIWORD_Msk (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== STATS_HIWORD_P2 ==================================================== */ + #define R_ETHSW_STATS_HIWORD_P2_STATS_HIWORD_Pos (0UL) /*!< STATS_HIWORD (Bit 0) */ + #define R_ETHSW_STATS_HIWORD_P2_STATS_HIWORD_Msk (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== STATS_HIWORD_P3 ==================================================== */ + #define R_ETHSW_STATS_HIWORD_P3_STATS_HIWORD_Pos (0UL) /*!< STATS_HIWORD (Bit 0) */ + #define R_ETHSW_STATS_HIWORD_P3_STATS_HIWORD_Msk (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== STATS_CTRL_P0 ===================================================== */ + #define R_ETHSW_STATS_CTRL_P0_CLRALL_Pos (0UL) /*!< CLRALL (Bit 0) */ + #define R_ETHSW_STATS_CTRL_P0_CLRALL_Msk (0x1UL) /*!< CLRALL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATS_CTRL_P0_CLRBUSY_Pos (1UL) /*!< CLRBUSY (Bit 1) */ + #define R_ETHSW_STATS_CTRL_P0_CLRBUSY_Msk (0x2UL) /*!< CLRBUSY (Bitfield-Mask: 0x01) */ +/* ===================================================== STATS_CTRL_P1 ===================================================== */ + #define R_ETHSW_STATS_CTRL_P1_CLRALL_Pos (0UL) /*!< CLRALL (Bit 0) */ + #define R_ETHSW_STATS_CTRL_P1_CLRALL_Msk (0x1UL) /*!< CLRALL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATS_CTRL_P1_CLRBUSY_Pos (1UL) /*!< CLRBUSY (Bit 1) */ + #define R_ETHSW_STATS_CTRL_P1_CLRBUSY_Msk (0x2UL) /*!< CLRBUSY (Bitfield-Mask: 0x01) */ +/* ===================================================== STATS_CTRL_P2 ===================================================== */ + #define R_ETHSW_STATS_CTRL_P2_CLRALL_Pos (0UL) /*!< CLRALL (Bit 0) */ + #define R_ETHSW_STATS_CTRL_P2_CLRALL_Msk (0x1UL) /*!< CLRALL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATS_CTRL_P2_CLRBUSY_Pos (1UL) /*!< CLRBUSY (Bit 1) */ + #define R_ETHSW_STATS_CTRL_P2_CLRBUSY_Msk (0x2UL) /*!< CLRBUSY (Bitfield-Mask: 0x01) */ +/* ===================================================== STATS_CTRL_P3 ===================================================== */ + #define R_ETHSW_STATS_CTRL_P3_CLRALL_Pos (0UL) /*!< CLRALL (Bit 0) */ + #define R_ETHSW_STATS_CTRL_P3_CLRALL_Msk (0x1UL) /*!< CLRALL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATS_CTRL_P3_CLRBUSY_Pos (1UL) /*!< CLRBUSY (Bit 1) */ + #define R_ETHSW_STATS_CTRL_P3_CLRBUSY_Msk (0x2UL) /*!< CLRBUSY (Bitfield-Mask: 0x01) */ +/* ================================================ STATS_CLEAR_VALUELO_P0 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P0_STATS_CLEAR_VALUELO_Pos (0UL) /*!< STATS_CLEAR_VALUELO (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P0_STATS_CLEAR_VALUELO_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */ +/* ================================================ STATS_CLEAR_VALUELO_P1 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P1_STATS_CLEAR_VALUELO_Pos (0UL) /*!< STATS_CLEAR_VALUELO (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P1_STATS_CLEAR_VALUELO_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */ +/* ================================================ STATS_CLEAR_VALUELO_P2 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P2_STATS_CLEAR_VALUELO_Pos (0UL) /*!< STATS_CLEAR_VALUELO (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P2_STATS_CLEAR_VALUELO_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */ +/* ================================================ STATS_CLEAR_VALUELO_P3 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P3_STATS_CLEAR_VALUELO_Pos (0UL) /*!< STATS_CLEAR_VALUELO (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P3_STATS_CLEAR_VALUELO_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */ +/* ================================================ STATS_CLEAR_VALUEHI_P0 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P0_STATS_CLEAR_VALUEHI_Pos (0UL) /*!< STATS_CLEAR_VALUEHI (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P0_STATS_CLEAR_VALUEHI_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */ +/* ================================================ STATS_CLEAR_VALUEHI_P1 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P1_STATS_CLEAR_VALUEHI_Pos (0UL) /*!< STATS_CLEAR_VALUEHI (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P1_STATS_CLEAR_VALUEHI_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */ +/* ================================================ STATS_CLEAR_VALUEHI_P2 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P2_STATS_CLEAR_VALUEHI_Pos (0UL) /*!< STATS_CLEAR_VALUEHI (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P2_STATS_CLEAR_VALUEHI_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */ +/* ================================================ STATS_CLEAR_VALUEHI_P3 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P3_STATS_CLEAR_VALUEHI_Pos (0UL) /*!< STATS_CLEAR_VALUEHI (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P3_STATS_CLEAR_VALUEHI_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== ADEFERRED_P0 ====================================================== */ + #define R_ETHSW_ADEFERRED_P0_DEFERCOUNT_Pos (0UL) /*!< DEFERCOUNT (Bit 0) */ + #define R_ETHSW_ADEFERRED_P0_DEFERCOUNT_Msk (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== ADEFERRED_P1 ====================================================== */ + #define R_ETHSW_ADEFERRED_P1_DEFERCOUNT_Pos (0UL) /*!< DEFERCOUNT (Bit 0) */ + #define R_ETHSW_ADEFERRED_P1_DEFERCOUNT_Msk (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== ADEFERRED_P2 ====================================================== */ + #define R_ETHSW_ADEFERRED_P2_DEFERCOUNT_Pos (0UL) /*!< DEFERCOUNT (Bit 0) */ + #define R_ETHSW_ADEFERRED_P2_DEFERCOUNT_Msk (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== ADEFERRED_P3 ====================================================== */ + #define R_ETHSW_ADEFERRED_P3_DEFERCOUNT_Pos (0UL) /*!< DEFERCOUNT (Bit 0) */ + #define R_ETHSW_ADEFERRED_P3_DEFERCOUNT_Msk (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AMULTIPLECOLLISIONS_P0 ================================================= */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P0_COUNTAFTMLTCOLL_Pos (0UL) /*!< COUNTAFTMLTCOLL (Bit 0) */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P0_COUNTAFTMLTCOLL_Msk (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AMULTIPLECOLLISIONS_P1 ================================================= */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P1_COUNTAFTMLTCOLL_Pos (0UL) /*!< COUNTAFTMLTCOLL (Bit 0) */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P1_COUNTAFTMLTCOLL_Msk (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AMULTIPLECOLLISIONS_P2 ================================================= */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P2_COUNTAFTMLTCOLL_Pos (0UL) /*!< COUNTAFTMLTCOLL (Bit 0) */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P2_COUNTAFTMLTCOLL_Msk (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AMULTIPLECOLLISIONS_P3 ================================================= */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P3_COUNTAFTMLTCOLL_Pos (0UL) /*!< COUNTAFTMLTCOLL (Bit 0) */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P3_COUNTAFTMLTCOLL_Msk (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ASINGLECOLLISIONS_P0 ================================================== */ + #define R_ETHSW_ASINGLECOLLISIONS_P0_COUNTAFTSNGLCOLL_Pos (0UL) /*!< COUNTAFTSNGLCOLL (Bit 0) */ + #define R_ETHSW_ASINGLECOLLISIONS_P0_COUNTAFTSNGLCOLL_Msk (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ASINGLECOLLISIONS_P1 ================================================== */ + #define R_ETHSW_ASINGLECOLLISIONS_P1_COUNTAFTSNGLCOLL_Pos (0UL) /*!< COUNTAFTSNGLCOLL (Bit 0) */ + #define R_ETHSW_ASINGLECOLLISIONS_P1_COUNTAFTSNGLCOLL_Msk (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ASINGLECOLLISIONS_P2 ================================================== */ + #define R_ETHSW_ASINGLECOLLISIONS_P2_COUNTAFTSNGLCOLL_Pos (0UL) /*!< COUNTAFTSNGLCOLL (Bit 0) */ + #define R_ETHSW_ASINGLECOLLISIONS_P2_COUNTAFTSNGLCOLL_Msk (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ASINGLECOLLISIONS_P3 ================================================== */ + #define R_ETHSW_ASINGLECOLLISIONS_P3_COUNTAFTSNGLCOLL_Pos (0UL) /*!< COUNTAFTSNGLCOLL (Bit 0) */ + #define R_ETHSW_ASINGLECOLLISIONS_P3_COUNTAFTSNGLCOLL_Msk (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ALATECOLLISIONS_P0 =================================================== */ + #define R_ETHSW_ALATECOLLISIONS_P0_LATECOLLCOUNT_Pos (0UL) /*!< LATECOLLCOUNT (Bit 0) */ + #define R_ETHSW_ALATECOLLISIONS_P0_LATECOLLCOUNT_Msk (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ALATECOLLISIONS_P1 =================================================== */ + #define R_ETHSW_ALATECOLLISIONS_P1_LATECOLLCOUNT_Pos (0UL) /*!< LATECOLLCOUNT (Bit 0) */ + #define R_ETHSW_ALATECOLLISIONS_P1_LATECOLLCOUNT_Msk (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ALATECOLLISIONS_P2 =================================================== */ + #define R_ETHSW_ALATECOLLISIONS_P2_LATECOLLCOUNT_Pos (0UL) /*!< LATECOLLCOUNT (Bit 0) */ + #define R_ETHSW_ALATECOLLISIONS_P2_LATECOLLCOUNT_Msk (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ALATECOLLISIONS_P3 =================================================== */ + #define R_ETHSW_ALATECOLLISIONS_P3_LATECOLLCOUNT_Pos (0UL) /*!< LATECOLLCOUNT (Bit 0) */ + #define R_ETHSW_ALATECOLLISIONS_P3_LATECOLLCOUNT_Msk (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AEXCESSIVECOLLISIONS_P0 ================================================ */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P0_EXCCOLLCOUNT_Pos (0UL) /*!< EXCCOLLCOUNT (Bit 0) */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P0_EXCCOLLCOUNT_Msk (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AEXCESSIVECOLLISIONS_P1 ================================================ */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P1_EXCCOLLCOUNT_Pos (0UL) /*!< EXCCOLLCOUNT (Bit 0) */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P1_EXCCOLLCOUNT_Msk (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AEXCESSIVECOLLISIONS_P2 ================================================ */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P2_EXCCOLLCOUNT_Pos (0UL) /*!< EXCCOLLCOUNT (Bit 0) */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P2_EXCCOLLCOUNT_Msk (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AEXCESSIVECOLLISIONS_P3 ================================================ */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P3_EXCCOLLCOUNT_Pos (0UL) /*!< EXCCOLLCOUNT (Bit 0) */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P3_EXCCOLLCOUNT_Msk (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ACARRIERSENSEERRORS_P0 ================================================= */ + #define R_ETHSW_ACARRIERSENSEERRORS_P0_CSERRCOUNT_Pos (0UL) /*!< CSERRCOUNT (Bit 0) */ + #define R_ETHSW_ACARRIERSENSEERRORS_P0_CSERRCOUNT_Msk (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ACARRIERSENSEERRORS_P1 ================================================= */ + #define R_ETHSW_ACARRIERSENSEERRORS_P1_CSERRCOUNT_Pos (0UL) /*!< CSERRCOUNT (Bit 0) */ + #define R_ETHSW_ACARRIERSENSEERRORS_P1_CSERRCOUNT_Msk (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ACARRIERSENSEERRORS_P2 ================================================= */ + #define R_ETHSW_ACARRIERSENSEERRORS_P2_CSERRCOUNT_Pos (0UL) /*!< CSERRCOUNT (Bit 0) */ + #define R_ETHSW_ACARRIERSENSEERRORS_P2_CSERRCOUNT_Msk (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ACARRIERSENSEERRORS_P3 ================================================= */ + #define R_ETHSW_ACARRIERSENSEERRORS_P3_CSERRCOUNT_Pos (0UL) /*!< CSERRCOUNT (Bit 0) */ + #define R_ETHSW_ACARRIERSENSEERRORS_P3_CSERRCOUNT_Msk (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== STATN_STATUS ====================================================== */ + #define R_ETHSW_STATN_STATUS_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ + #define R_ETHSW_STATN_STATUS_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ===================================================== STATN_CONFIG ====================================================== */ + #define R_ETHSW_STATN_CONFIG_CLEAR_ON_READ_Pos (1UL) /*!< CLEAR_ON_READ (Bit 1) */ + #define R_ETHSW_STATN_CONFIG_CLEAR_ON_READ_Msk (0x2UL) /*!< CLEAR_ON_READ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATN_CONFIG_RESET_Pos (31UL) /*!< RESET (Bit 31) */ + #define R_ETHSW_STATN_CONFIG_RESET_Msk (0x80000000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +/* ===================================================== STATN_CONTROL ===================================================== */ + #define R_ETHSW_STATN_CONTROL_CHANMASK_Pos (0UL) /*!< CHANMASK (Bit 0) */ + #define R_ETHSW_STATN_CONTROL_CHANMASK_Msk (0xfUL) /*!< CHANMASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_STATN_CONTROL_CLEAR_PRE_Pos (29UL) /*!< CLEAR_PRE (Bit 29) */ + #define R_ETHSW_STATN_CONTROL_CLEAR_PRE_Msk (0x20000000UL) /*!< CLEAR_PRE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATN_CONTROL_CMD_CLEAR_Pos (31UL) /*!< CMD_CLEAR (Bit 31) */ + #define R_ETHSW_STATN_CONTROL_CMD_CLEAR_Msk (0x80000000UL) /*!< CMD_CLEAR (Bitfield-Mask: 0x01) */ +/* ================================================== STATN_CLEARVALUE_LO ================================================== */ + #define R_ETHSW_STATN_CLEARVALUE_LO_STATN_CLEARVALUE_LO_Pos (0UL) /*!< STATN_CLEARVALUE_LO (Bit 0) */ + #define R_ETHSW_STATN_CLEARVALUE_LO_STATN_CLEARVALUE_LO_Msk (0xffffffffUL) /*!< STATN_CLEARVALUE_LO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ODISC0 ========================================================= */ + #define R_ETHSW_ODISC0_ODISC_Pos (0UL) /*!< ODISC (Bit 0) */ + #define R_ETHSW_ODISC0_ODISC_Msk (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ODISC1 ========================================================= */ + #define R_ETHSW_ODISC1_ODISC_Pos (0UL) /*!< ODISC (Bit 0) */ + #define R_ETHSW_ODISC1_ODISC_Msk (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ODISC2 ========================================================= */ + #define R_ETHSW_ODISC2_ODISC_Pos (0UL) /*!< ODISC (Bit 0) */ + #define R_ETHSW_ODISC2_ODISC_Msk (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ODISC3 ========================================================= */ + #define R_ETHSW_ODISC3_ODISC_Pos (0UL) /*!< ODISC (Bit 0) */ + #define R_ETHSW_ODISC3_ODISC_Msk (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_VLAN0 ====================================================== */ + #define R_ETHSW_IDISC_VLAN0_IDISC_VLAN_Pos (0UL) /*!< IDISC_VLAN (Bit 0) */ + #define R_ETHSW_IDISC_VLAN0_IDISC_VLAN_Msk (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_VLAN1 ====================================================== */ + #define R_ETHSW_IDISC_VLAN1_IDISC_VLAN_Pos (0UL) /*!< IDISC_VLAN (Bit 0) */ + #define R_ETHSW_IDISC_VLAN1_IDISC_VLAN_Msk (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_VLAN2 ====================================================== */ + #define R_ETHSW_IDISC_VLAN2_IDISC_VLAN_Pos (0UL) /*!< IDISC_VLAN (Bit 0) */ + #define R_ETHSW_IDISC_VLAN2_IDISC_VLAN_Msk (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_VLAN3 ====================================================== */ + #define R_ETHSW_IDISC_VLAN3_IDISC_VLAN_Pos (0UL) /*!< IDISC_VLAN (Bit 0) */ + #define R_ETHSW_IDISC_VLAN3_IDISC_VLAN_Msk (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_UNTAGGED0 ==================================================== */ + #define R_ETHSW_IDISC_UNTAGGED0_IDISC_UNTAGGED_Pos (0UL) /*!< IDISC_UNTAGGED (Bit 0) */ + #define R_ETHSW_IDISC_UNTAGGED0_IDISC_UNTAGGED_Msk (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_UNTAGGED1 ==================================================== */ + #define R_ETHSW_IDISC_UNTAGGED1_IDISC_UNTAGGED_Pos (0UL) /*!< IDISC_UNTAGGED (Bit 0) */ + #define R_ETHSW_IDISC_UNTAGGED1_IDISC_UNTAGGED_Msk (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_UNTAGGED2 ==================================================== */ + #define R_ETHSW_IDISC_UNTAGGED2_IDISC_UNTAGGED_Pos (0UL) /*!< IDISC_UNTAGGED (Bit 0) */ + #define R_ETHSW_IDISC_UNTAGGED2_IDISC_UNTAGGED_Msk (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_UNTAGGED3 ==================================================== */ + #define R_ETHSW_IDISC_UNTAGGED3_IDISC_UNTAGGED_Pos (0UL) /*!< IDISC_UNTAGGED (Bit 0) */ + #define R_ETHSW_IDISC_UNTAGGED3_IDISC_UNTAGGED_Msk (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_BLOCKED0 ===================================================== */ + #define R_ETHSW_IDISC_BLOCKED0_IDISC_BLOCKED_Pos (0UL) /*!< IDISC_BLOCKED (Bit 0) */ + #define R_ETHSW_IDISC_BLOCKED0_IDISC_BLOCKED_Msk (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_BLOCKED1 ===================================================== */ + #define R_ETHSW_IDISC_BLOCKED1_IDISC_BLOCKED_Pos (0UL) /*!< IDISC_BLOCKED (Bit 0) */ + #define R_ETHSW_IDISC_BLOCKED1_IDISC_BLOCKED_Msk (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_BLOCKED2 ===================================================== */ + #define R_ETHSW_IDISC_BLOCKED2_IDISC_BLOCKED_Pos (0UL) /*!< IDISC_BLOCKED (Bit 0) */ + #define R_ETHSW_IDISC_BLOCKED2_IDISC_BLOCKED_Msk (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_BLOCKED3 ===================================================== */ + #define R_ETHSW_IDISC_BLOCKED3_IDISC_BLOCKED_Pos (0UL) /*!< IDISC_BLOCKED (Bit 0) */ + #define R_ETHSW_IDISC_BLOCKED3_IDISC_BLOCKED_Msk (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_ANY0 ======================================================= */ + #define R_ETHSW_IDISC_ANY0_IDISC_ANY_Pos (0UL) /*!< IDISC_ANY (Bit 0) */ + #define R_ETHSW_IDISC_ANY0_IDISC_ANY_Msk (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_ANY1 ======================================================= */ + #define R_ETHSW_IDISC_ANY1_IDISC_ANY_Pos (0UL) /*!< IDISC_ANY (Bit 0) */ + #define R_ETHSW_IDISC_ANY1_IDISC_ANY_Msk (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_ANY2 ======================================================= */ + #define R_ETHSW_IDISC_ANY2_IDISC_ANY_Pos (0UL) /*!< IDISC_ANY (Bit 0) */ + #define R_ETHSW_IDISC_ANY2_IDISC_ANY_Msk (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_ANY3 ======================================================= */ + #define R_ETHSW_IDISC_ANY3_IDISC_ANY_Pos (0UL) /*!< IDISC_ANY (Bit 0) */ + #define R_ETHSW_IDISC_ANY3_IDISC_ANY_Msk (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IDISC_SRCFLT0 ===================================================== */ + #define R_ETHSW_IDISC_SRCFLT0_IDISC_SRCFLT_Pos (0UL) /*!< IDISC_SRCFLT (Bit 0) */ + #define R_ETHSW_IDISC_SRCFLT0_IDISC_SRCFLT_Msk (0xffffffffUL) /*!< IDISC_SRCFLT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IDISC_SRCFLT1 ===================================================== */ + #define R_ETHSW_IDISC_SRCFLT1_IDISC_SRCFLT_Pos (0UL) /*!< IDISC_SRCFLT (Bit 0) */ + #define R_ETHSW_IDISC_SRCFLT1_IDISC_SRCFLT_Msk (0xffffffffUL) /*!< IDISC_SRCFLT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IDISC_SRCFLT2 ===================================================== */ + #define R_ETHSW_IDISC_SRCFLT2_IDISC_SRCFLT_Pos (0UL) /*!< IDISC_SRCFLT (Bit 0) */ + #define R_ETHSW_IDISC_SRCFLT2_IDISC_SRCFLT_Msk (0xffffffffUL) /*!< IDISC_SRCFLT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TX_HOLD_REQ_CNT0 ==================================================== */ + #define R_ETHSW_TX_HOLD_REQ_CNT0_TX_HOLD_REQ_CNT_Pos (0UL) /*!< TX_HOLD_REQ_CNT (Bit 0) */ + #define R_ETHSW_TX_HOLD_REQ_CNT0_TX_HOLD_REQ_CNT_Msk (0xffffffffUL) /*!< TX_HOLD_REQ_CNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TX_HOLD_REQ_CNT1 ==================================================== */ + #define R_ETHSW_TX_HOLD_REQ_CNT1_TX_HOLD_REQ_CNT_Pos (0UL) /*!< TX_HOLD_REQ_CNT (Bit 0) */ + #define R_ETHSW_TX_HOLD_REQ_CNT1_TX_HOLD_REQ_CNT_Msk (0xffffffffUL) /*!< TX_HOLD_REQ_CNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TX_HOLD_REQ_CNT2 ==================================================== */ + #define R_ETHSW_TX_HOLD_REQ_CNT2_TX_HOLD_REQ_CNT_Pos (0UL) /*!< TX_HOLD_REQ_CNT (Bit 0) */ + #define R_ETHSW_TX_HOLD_REQ_CNT2_TX_HOLD_REQ_CNT_Msk (0xffffffffUL) /*!< TX_HOLD_REQ_CNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== TX_FRAG_CNT0 ====================================================== */ + #define R_ETHSW_TX_FRAG_CNT0_TX_FRAG_CNT_Pos (0UL) /*!< TX_FRAG_CNT (Bit 0) */ + #define R_ETHSW_TX_FRAG_CNT0_TX_FRAG_CNT_Msk (0xffffffffUL) /*!< TX_FRAG_CNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== TX_FRAG_CNT1 ====================================================== */ + #define R_ETHSW_TX_FRAG_CNT1_TX_FRAG_CNT_Pos (0UL) /*!< TX_FRAG_CNT (Bit 0) */ + #define R_ETHSW_TX_FRAG_CNT1_TX_FRAG_CNT_Msk (0xffffffffUL) /*!< TX_FRAG_CNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== TX_FRAG_CNT2 ====================================================== */ + #define R_ETHSW_TX_FRAG_CNT2_TX_FRAG_CNT_Pos (0UL) /*!< TX_FRAG_CNT (Bit 0) */ + #define R_ETHSW_TX_FRAG_CNT2_TX_FRAG_CNT_Msk (0xffffffffUL) /*!< TX_FRAG_CNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RX_FRAG_CNT0 ====================================================== */ + #define R_ETHSW_RX_FRAG_CNT0_RX_FRAG_CNT_Pos (0UL) /*!< RX_FRAG_CNT (Bit 0) */ + #define R_ETHSW_RX_FRAG_CNT0_RX_FRAG_CNT_Msk (0xffffffffUL) /*!< RX_FRAG_CNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RX_FRAG_CNT1 ====================================================== */ + #define R_ETHSW_RX_FRAG_CNT1_RX_FRAG_CNT_Pos (0UL) /*!< RX_FRAG_CNT (Bit 0) */ + #define R_ETHSW_RX_FRAG_CNT1_RX_FRAG_CNT_Msk (0xffffffffUL) /*!< RX_FRAG_CNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RX_FRAG_CNT2 ====================================================== */ + #define R_ETHSW_RX_FRAG_CNT2_RX_FRAG_CNT_Pos (0UL) /*!< RX_FRAG_CNT (Bit 0) */ + #define R_ETHSW_RX_FRAG_CNT2_RX_FRAG_CNT_Msk (0xffffffffUL) /*!< RX_FRAG_CNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== RX_ASSY_OK_CNT0 ==================================================== */ + #define R_ETHSW_RX_ASSY_OK_CNT0_RX_ASSY_OK_CNT_Pos (0UL) /*!< RX_ASSY_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_ASSY_OK_CNT0_RX_ASSY_OK_CNT_Msk (0xffffffffUL) /*!< RX_ASSY_OK_CNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== RX_ASSY_OK_CNT1 ==================================================== */ + #define R_ETHSW_RX_ASSY_OK_CNT1_RX_ASSY_OK_CNT_Pos (0UL) /*!< RX_ASSY_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_ASSY_OK_CNT1_RX_ASSY_OK_CNT_Msk (0xffffffffUL) /*!< RX_ASSY_OK_CNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== RX_ASSY_OK_CNT2 ==================================================== */ + #define R_ETHSW_RX_ASSY_OK_CNT2_RX_ASSY_OK_CNT_Pos (0UL) /*!< RX_ASSY_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_ASSY_OK_CNT2_RX_ASSY_OK_CNT_Msk (0xffffffffUL) /*!< RX_ASSY_OK_CNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== RX_ASSY_ERR_CNT0 ==================================================== */ + #define R_ETHSW_RX_ASSY_ERR_CNT0_RX_ASSY_ERR_CNT_Pos (0UL) /*!< RX_ASSY_ERR_CNT (Bit 0) */ + #define R_ETHSW_RX_ASSY_ERR_CNT0_RX_ASSY_ERR_CNT_Msk (0xffffUL) /*!< RX_ASSY_ERR_CNT (Bitfield-Mask: 0xffff) */ +/* =================================================== RX_ASSY_ERR_CNT1 ==================================================== */ + #define R_ETHSW_RX_ASSY_ERR_CNT1_RX_ASSY_ERR_CNT_Pos (0UL) /*!< RX_ASSY_ERR_CNT (Bit 0) */ + #define R_ETHSW_RX_ASSY_ERR_CNT1_RX_ASSY_ERR_CNT_Msk (0xffffUL) /*!< RX_ASSY_ERR_CNT (Bitfield-Mask: 0xffff) */ +/* =================================================== RX_ASSY_ERR_CNT2 ==================================================== */ + #define R_ETHSW_RX_ASSY_ERR_CNT2_RX_ASSY_ERR_CNT_Pos (0UL) /*!< RX_ASSY_ERR_CNT (Bit 0) */ + #define R_ETHSW_RX_ASSY_ERR_CNT2_RX_ASSY_ERR_CNT_Msk (0xffffUL) /*!< RX_ASSY_ERR_CNT (Bitfield-Mask: 0xffff) */ +/* ==================================================== RX_SMD_ERR_CNT0 ==================================================== */ + #define R_ETHSW_RX_SMD_ERR_CNT0_RX_SMD_ERR_CNT_Pos (0UL) /*!< RX_SMD_ERR_CNT (Bit 0) */ + #define R_ETHSW_RX_SMD_ERR_CNT0_RX_SMD_ERR_CNT_Msk (0xffffUL) /*!< RX_SMD_ERR_CNT (Bitfield-Mask: 0xffff) */ +/* ==================================================== RX_SMD_ERR_CNT1 ==================================================== */ + #define R_ETHSW_RX_SMD_ERR_CNT1_RX_SMD_ERR_CNT_Pos (0UL) /*!< RX_SMD_ERR_CNT (Bit 0) */ + #define R_ETHSW_RX_SMD_ERR_CNT1_RX_SMD_ERR_CNT_Msk (0xffffUL) /*!< RX_SMD_ERR_CNT (Bitfield-Mask: 0xffff) */ +/* ==================================================== RX_SMD_ERR_CNT2 ==================================================== */ + #define R_ETHSW_RX_SMD_ERR_CNT2_RX_SMD_ERR_CNT_Pos (0UL) /*!< RX_SMD_ERR_CNT (Bit 0) */ + #define R_ETHSW_RX_SMD_ERR_CNT2_RX_SMD_ERR_CNT_Msk (0xffffUL) /*!< RX_SMD_ERR_CNT (Bitfield-Mask: 0xffff) */ +/* =================================================== TX_VERIFY_OK_CNT0 =================================================== */ + #define R_ETHSW_TX_VERIFY_OK_CNT0_TX_VERIFY_OK_CNT_Pos (0UL) /*!< TX_VERIFY_OK_CNT (Bit 0) */ + #define R_ETHSW_TX_VERIFY_OK_CNT0_TX_VERIFY_OK_CNT_Msk (0xffUL) /*!< TX_VERIFY_OK_CNT (Bitfield-Mask: 0xff) */ +/* =================================================== TX_VERIFY_OK_CNT1 =================================================== */ + #define R_ETHSW_TX_VERIFY_OK_CNT1_TX_VERIFY_OK_CNT_Pos (0UL) /*!< TX_VERIFY_OK_CNT (Bit 0) */ + #define R_ETHSW_TX_VERIFY_OK_CNT1_TX_VERIFY_OK_CNT_Msk (0xffUL) /*!< TX_VERIFY_OK_CNT (Bitfield-Mask: 0xff) */ +/* =================================================== TX_VERIFY_OK_CNT2 =================================================== */ + #define R_ETHSW_TX_VERIFY_OK_CNT2_TX_VERIFY_OK_CNT_Pos (0UL) /*!< TX_VERIFY_OK_CNT (Bit 0) */ + #define R_ETHSW_TX_VERIFY_OK_CNT2_TX_VERIFY_OK_CNT_Msk (0xffUL) /*!< TX_VERIFY_OK_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== TX_RESPONSE_OK_CNT0 ================================================== */ + #define R_ETHSW_TX_RESPONSE_OK_CNT0_TX_RESPONSE_OK_CNT_Pos (0UL) /*!< TX_RESPONSE_OK_CNT (Bit 0) */ + #define R_ETHSW_TX_RESPONSE_OK_CNT0_TX_RESPONSE_OK_CNT_Msk (0xffUL) /*!< TX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== TX_RESPONSE_OK_CNT1 ================================================== */ + #define R_ETHSW_TX_RESPONSE_OK_CNT1_TX_RESPONSE_OK_CNT_Pos (0UL) /*!< TX_RESPONSE_OK_CNT (Bit 0) */ + #define R_ETHSW_TX_RESPONSE_OK_CNT1_TX_RESPONSE_OK_CNT_Msk (0xffUL) /*!< TX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== TX_RESPONSE_OK_CNT2 ================================================== */ + #define R_ETHSW_TX_RESPONSE_OK_CNT2_TX_RESPONSE_OK_CNT_Pos (0UL) /*!< TX_RESPONSE_OK_CNT (Bit 0) */ + #define R_ETHSW_TX_RESPONSE_OK_CNT2_TX_RESPONSE_OK_CNT_Msk (0xffUL) /*!< TX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff) */ +/* =================================================== RX_VERIFY_OK_CNT0 =================================================== */ + #define R_ETHSW_RX_VERIFY_OK_CNT0_RX_VERIFY_OK_CNT_Pos (0UL) /*!< RX_VERIFY_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_VERIFY_OK_CNT0_RX_VERIFY_OK_CNT_Msk (0xffUL) /*!< RX_VERIFY_OK_CNT (Bitfield-Mask: 0xff) */ +/* =================================================== RX_VERIFY_OK_CNT1 =================================================== */ + #define R_ETHSW_RX_VERIFY_OK_CNT1_RX_VERIFY_OK_CNT_Pos (0UL) /*!< RX_VERIFY_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_VERIFY_OK_CNT1_RX_VERIFY_OK_CNT_Msk (0xffUL) /*!< RX_VERIFY_OK_CNT (Bitfield-Mask: 0xff) */ +/* =================================================== RX_VERIFY_OK_CNT2 =================================================== */ + #define R_ETHSW_RX_VERIFY_OK_CNT2_RX_VERIFY_OK_CNT_Pos (0UL) /*!< RX_VERIFY_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_VERIFY_OK_CNT2_RX_VERIFY_OK_CNT_Msk (0xffUL) /*!< RX_VERIFY_OK_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== RX_RESPONSE_OK_CNT0 ================================================== */ + #define R_ETHSW_RX_RESPONSE_OK_CNT0_RX_RESPONSE_OK_CNT_Pos (0UL) /*!< RX_RESPONSE_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_RESPONSE_OK_CNT0_RX_RESPONSE_OK_CNT_Msk (0xffUL) /*!< RX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== RX_RESPONSE_OK_CNT1 ================================================== */ + #define R_ETHSW_RX_RESPONSE_OK_CNT1_RX_RESPONSE_OK_CNT_Pos (0UL) /*!< RX_RESPONSE_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_RESPONSE_OK_CNT1_RX_RESPONSE_OK_CNT_Msk (0xffUL) /*!< RX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== RX_RESPONSE_OK_CNT2 ================================================== */ + #define R_ETHSW_RX_RESPONSE_OK_CNT2_RX_RESPONSE_OK_CNT_Pos (0UL) /*!< RX_RESPONSE_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_RESPONSE_OK_CNT2_RX_RESPONSE_OK_CNT_Msk (0xffUL) /*!< RX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== RX_VERIFY_BAD_CNT0 =================================================== */ + #define R_ETHSW_RX_VERIFY_BAD_CNT0_RX_VERIFY_BAD_CNT_Pos (0UL) /*!< RX_VERIFY_BAD_CNT (Bit 0) */ + #define R_ETHSW_RX_VERIFY_BAD_CNT0_RX_VERIFY_BAD_CNT_Msk (0xffUL) /*!< RX_VERIFY_BAD_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== RX_VERIFY_BAD_CNT1 =================================================== */ + #define R_ETHSW_RX_VERIFY_BAD_CNT1_RX_VERIFY_BAD_CNT_Pos (0UL) /*!< RX_VERIFY_BAD_CNT (Bit 0) */ + #define R_ETHSW_RX_VERIFY_BAD_CNT1_RX_VERIFY_BAD_CNT_Msk (0xffUL) /*!< RX_VERIFY_BAD_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== RX_VERIFY_BAD_CNT2 =================================================== */ + #define R_ETHSW_RX_VERIFY_BAD_CNT2_RX_VERIFY_BAD_CNT_Pos (0UL) /*!< RX_VERIFY_BAD_CNT (Bit 0) */ + #define R_ETHSW_RX_VERIFY_BAD_CNT2_RX_VERIFY_BAD_CNT_Msk (0xffUL) /*!< RX_VERIFY_BAD_CNT (Bitfield-Mask: 0xff) */ +/* ================================================= RX_RESPONSE_BAD_CNT0 ================================================== */ + #define R_ETHSW_RX_RESPONSE_BAD_CNT0_RX_RESPONSE_BAD_CNT_Pos (0UL) /*!< RX_RESPONSE_BAD_CNT (Bit 0) */ + #define R_ETHSW_RX_RESPONSE_BAD_CNT0_RX_RESPONSE_BAD_CNT_Msk (0xffUL) /*!< RX_RESPONSE_BAD_CNT (Bitfield-Mask: 0xff) */ +/* ================================================= RX_RESPONSE_BAD_CNT1 ================================================== */ + #define R_ETHSW_RX_RESPONSE_BAD_CNT1_RX_RESPONSE_BAD_CNT_Pos (0UL) /*!< RX_RESPONSE_BAD_CNT (Bit 0) */ + #define R_ETHSW_RX_RESPONSE_BAD_CNT1_RX_RESPONSE_BAD_CNT_Msk (0xffUL) /*!< RX_RESPONSE_BAD_CNT (Bitfield-Mask: 0xff) */ +/* ================================================= RX_RESPONSE_BAD_CNT2 ================================================== */ + #define R_ETHSW_RX_RESPONSE_BAD_CNT2_RX_RESPONSE_BAD_CNT_Pos (0UL) /*!< RX_RESPONSE_BAD_CNT (Bit 0) */ + #define R_ETHSW_RX_RESPONSE_BAD_CNT2_RX_RESPONSE_BAD_CNT_Msk (0xffUL) /*!< RX_RESPONSE_BAD_CNT (Bitfield-Mask: 0xff) */ +/* ===================================================== MMCTL_OUT_CT ====================================================== */ + #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_ENA_Pos (0UL) /*!< CT_OVR_ENA (Bit 0) */ + #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_ENA_Msk (0x7UL) /*!< CT_OVR_ENA (Bitfield-Mask: 0x07) */ + #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_Pos (16UL) /*!< CT_OVR (Bit 16) */ + #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_Msk (0x70000UL) /*!< CT_OVR (Bitfield-Mask: 0x07) */ +/* ================================================== MMCTL_CTFL_P0_3_ENA ================================================== */ + #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P0_ENA_Pos (0UL) /*!< CTFL_P0_ENA (Bit 0) */ + #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P0_ENA_Msk (0xffUL) /*!< CTFL_P0_ENA (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P1_ENA_Pos (8UL) /*!< CTFL_P1_ENA (Bit 8) */ + #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P1_ENA_Msk (0xff00UL) /*!< CTFL_P1_ENA (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P2_ENA_Pos (16UL) /*!< CTFL_P2_ENA (Bit 16) */ + #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P2_ENA_Msk (0xff0000UL) /*!< CTFL_P2_ENA (Bitfield-Mask: 0xff) */ +/* ============================================== MMCTL_YELLOW_BYTE_LENGTH_P =============================================== */ + #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YELLOW_LEN_Pos (2UL) /*!< YELLOW_LEN (Bit 2) */ + #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YELLOW_LEN_Msk (0xfffcUL) /*!< YELLOW_LEN (Bitfield-Mask: 0x3fff) */ + #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YLEN_EN_Pos (16UL) /*!< YLEN_EN (Bit 16) */ + #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YLEN_EN_Msk (0x10000UL) /*!< YLEN_EN (Bitfield-Mask: 0x01) */ +/* ==================================================== MMCTL_POOL0_CTR ==================================================== */ + #define R_ETHSW_MMCTL_POOL0_CTR_CELLS_Pos (0UL) /*!< CELLS (Bit 0) */ + #define R_ETHSW_MMCTL_POOL0_CTR_CELLS_Msk (0x3ffUL) /*!< CELLS (Bitfield-Mask: 0x3ff) */ + #define R_ETHSW_MMCTL_POOL0_CTR_USED_Pos (16UL) /*!< USED (Bit 16) */ + #define R_ETHSW_MMCTL_POOL0_CTR_USED_Msk (0x3ff0000UL) /*!< USED (Bitfield-Mask: 0x3ff) */ +/* ==================================================== MMCTL_POOL1_CTR ==================================================== */ + #define R_ETHSW_MMCTL_POOL1_CTR_CELLS_Pos (0UL) /*!< CELLS (Bit 0) */ + #define R_ETHSW_MMCTL_POOL1_CTR_CELLS_Msk (0x3ffUL) /*!< CELLS (Bitfield-Mask: 0x3ff) */ + #define R_ETHSW_MMCTL_POOL1_CTR_USED_Pos (16UL) /*!< USED (Bit 16) */ + #define R_ETHSW_MMCTL_POOL1_CTR_USED_Msk (0x3ff0000UL) /*!< USED (Bitfield-Mask: 0x3ff) */ +/* =================================================== MMCTL_POOL_GLOBAL =================================================== */ + #define R_ETHSW_MMCTL_POOL_GLOBAL_CELLS_Pos (0UL) /*!< CELLS (Bit 0) */ + #define R_ETHSW_MMCTL_POOL_GLOBAL_CELLS_Msk (0x3ffUL) /*!< CELLS (Bitfield-Mask: 0x3ff) */ + #define R_ETHSW_MMCTL_POOL_GLOBAL_USED_Pos (16UL) /*!< USED (Bit 16) */ + #define R_ETHSW_MMCTL_POOL_GLOBAL_USED_Msk (0x3ff0000UL) /*!< USED (Bitfield-Mask: 0x3ff) */ +/* =================================================== MMCTL_POOL_STATUS =================================================== */ + #define R_ETHSW_MMCTL_POOL_STATUS_QUEUE_FULL_Pos (0UL) /*!< QUEUE_FULL (Bit 0) */ + #define R_ETHSW_MMCTL_POOL_STATUS_QUEUE_FULL_Msk (0xffUL) /*!< QUEUE_FULL (Bitfield-Mask: 0xff) */ +/* ==================================================== MMCTL_POOL_QMAP ==================================================== */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q0_MAP_Pos (0UL) /*!< Q0_MAP (Bit 0) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q0_MAP_Msk (0x1UL) /*!< Q0_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q0_ENA_Pos (3UL) /*!< Q0_ENA (Bit 3) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q0_ENA_Msk (0x8UL) /*!< Q0_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q1_MAP_Pos (4UL) /*!< Q1_MAP (Bit 4) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q1_MAP_Msk (0x10UL) /*!< Q1_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q1_ENA_Pos (7UL) /*!< Q1_ENA (Bit 7) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q1_ENA_Msk (0x80UL) /*!< Q1_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q2_MAP_Pos (8UL) /*!< Q2_MAP (Bit 8) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q2_MAP_Msk (0x100UL) /*!< Q2_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q2_ENA_Pos (11UL) /*!< Q2_ENA (Bit 11) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q2_ENA_Msk (0x800UL) /*!< Q2_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q3_MAP_Pos (12UL) /*!< Q3_MAP (Bit 12) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q3_MAP_Msk (0x1000UL) /*!< Q3_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q3_ENA_Pos (15UL) /*!< Q3_ENA (Bit 15) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q3_ENA_Msk (0x8000UL) /*!< Q3_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q4_MAP_Pos (16UL) /*!< Q4_MAP (Bit 16) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q4_MAP_Msk (0x10000UL) /*!< Q4_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q4_ENA_Pos (19UL) /*!< Q4_ENA (Bit 19) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q4_ENA_Msk (0x80000UL) /*!< Q4_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q5_MAP_Pos (20UL) /*!< Q5_MAP (Bit 20) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q5_MAP_Msk (0x100000UL) /*!< Q5_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q5_ENA_Pos (23UL) /*!< Q5_ENA (Bit 23) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q5_ENA_Msk (0x800000UL) /*!< Q5_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q6_MAP_Pos (24UL) /*!< Q6_MAP (Bit 24) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q6_MAP_Msk (0x1000000UL) /*!< Q6_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q6_ENA_Pos (27UL) /*!< Q6_ENA (Bit 27) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q6_ENA_Msk (0x8000000UL) /*!< Q6_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q7_MAP_Pos (28UL) /*!< Q7_MAP (Bit 28) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q7_MAP_Msk (0x10000000UL) /*!< Q7_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q7_ENA_Pos (31UL) /*!< Q7_ENA (Bit 31) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q7_ENA_Msk (0x80000000UL) /*!< Q7_ENA (Bitfield-Mask: 0x01) */ +/* ====================================================== MMCTL_QGATE ====================================================== */ + #define R_ETHSW_MMCTL_QGATE_PORT_MASK_Pos (0UL) /*!< PORT_MASK (Bit 0) */ + #define R_ETHSW_MMCTL_QGATE_PORT_MASK_Msk (0xfUL) /*!< PORT_MASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MMCTL_QGATE_QUEUE_GATE_Pos (16UL) /*!< QUEUE_GATE (Bit 16) */ + #define R_ETHSW_MMCTL_QGATE_QUEUE_GATE_Msk (0xffff0000UL) /*!< QUEUE_GATE (Bitfield-Mask: 0xffff) */ +/* ====================================================== MMCTL_QTRIG ====================================================== */ + #define R_ETHSW_MMCTL_QTRIG_PORT_MASK_Pos (0UL) /*!< PORT_MASK (Bit 0) */ + #define R_ETHSW_MMCTL_QTRIG_PORT_MASK_Msk (0xfUL) /*!< PORT_MASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MMCTL_QTRIG_QUEUE_TRIG_Pos (16UL) /*!< QUEUE_TRIG (Bit 16) */ + #define R_ETHSW_MMCTL_QTRIG_QUEUE_TRIG_Msk (0xff0000UL) /*!< QUEUE_TRIG (Bitfield-Mask: 0xff) */ +/* ===================================================== MMCTL_QFLUSH ====================================================== */ + #define R_ETHSW_MMCTL_QFLUSH_PORT_MASK_Pos (0UL) /*!< PORT_MASK (Bit 0) */ + #define R_ETHSW_MMCTL_QFLUSH_PORT_MASK_Msk (0xfUL) /*!< PORT_MASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MMCTL_QFLUSH_QUEUE_MASK_Pos (16UL) /*!< QUEUE_MASK (Bit 16) */ + #define R_ETHSW_MMCTL_QFLUSH_QUEUE_MASK_Msk (0xff0000UL) /*!< QUEUE_MASK (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_QFLUSH_ACTION_Pos (24UL) /*!< ACTION (Bit 24) */ + #define R_ETHSW_MMCTL_QFLUSH_ACTION_Msk (0x3000000UL) /*!< ACTION (Bitfield-Mask: 0x03) */ +/* =============================================== MMCTL_QCLOSED_STATUS_P0_3 =============================================== */ + #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P0_STATUS_Pos (0UL) /*!< P0_STATUS (Bit 0) */ + #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P0_STATUS_Msk (0xffUL) /*!< P0_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P1_STATUS_Pos (8UL) /*!< P1_STATUS (Bit 8) */ + #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P1_STATUS_Msk (0xff00UL) /*!< P1_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P2_STATUS_Pos (16UL) /*!< P2_STATUS (Bit 16) */ + #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P2_STATUS_Msk (0xff0000UL) /*!< P2_STATUS (Bitfield-Mask: 0xff) */ +/* ================================================== MMCTL_1FRAME_MODE_P ================================================== */ + #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_1FRAME_ENA_Pos (0UL) /*!< Q_1FRAME_ENA (Bit 0) */ + #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_1FRAME_ENA_Msk (0xffUL) /*!< Q_1FRAME_ENA (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_BUF_ENA_Pos (16UL) /*!< Q_BUF_ENA (Bit 16) */ + #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_BUF_ENA_Msk (0xff0000UL) /*!< Q_BUF_ENA (Bitfield-Mask: 0xff) */ +/* ================================================ MMCTL_P0_3_QUEUE_STATUS ================================================ */ + #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P0_Q_STATUS_Pos (0UL) /*!< P0_Q_STATUS (Bit 0) */ + #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P0_Q_STATUS_Msk (0xffUL) /*!< P0_Q_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P1_Q_STATUS_Pos (8UL) /*!< P1_Q_STATUS (Bit 8) */ + #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P1_Q_STATUS_Msk (0xff00UL) /*!< P1_Q_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P2_Q_STATUS_Pos (16UL) /*!< P2_Q_STATUS (Bit 16) */ + #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P2_Q_STATUS_Msk (0xff0000UL) /*!< P2_Q_STATUS (Bitfield-Mask: 0xff) */ +/* ================================================ MMCTL_P0_3_FLUSH_STATUS ================================================ */ + #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P0_F_STATUS_Pos (0UL) /*!< P0_F_STATUS (Bit 0) */ + #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P0_F_STATUS_Msk (0xffUL) /*!< P0_F_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P1_F_STATUS_Pos (8UL) /*!< P1_F_STATUS (Bit 8) */ + #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P1_F_STATUS_Msk (0xff00UL) /*!< P1_F_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P2_F_STATUS_Pos (16UL) /*!< P2_F_STATUS (Bit 16) */ + #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P2_F_STATUS_Msk (0xff0000UL) /*!< P2_F_STATUS (Bitfield-Mask: 0xff) */ +/* ================================================ MMCTL_DLY_QTRIGGER_CTRL ================================================ */ + #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_DELAY_TIME_Pos (0UL) /*!< DELAY_TIME (Bit 0) */ + #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_DELAY_TIME_Msk (0x3fffffffUL) /*!< DELAY_TIME (Bitfield-Mask: 0x3fffffff) */ + #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_TIMER_SEL_Pos (30UL) /*!< TIMER_SEL (Bit 30) */ + #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_TIMER_SEL_Msk (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ +/* ================================================= MMCTL_PREEMPT_QUEUES ================================================== */ + #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ENA_Pos (0UL) /*!< PREEMPT_ENA (Bit 0) */ + #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ENA_Msk (0xffUL) /*!< PREEMPT_ENA (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ON_QCLOSE_Pos (8UL) /*!< PREEMPT_ON_QCLOSE (Bit 8) */ + #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ON_QCLOSE_Msk (0xff00UL) /*!< PREEMPT_ON_QCLOSE (Bitfield-Mask: 0xff) */ +/* ================================================== MMCTL_HOLD_CONTROL =================================================== */ + #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_FORCE_Pos (0UL) /*!< Q_HOLD_REQ_FORCE (Bit 0) */ + #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_FORCE_Msk (0x7UL) /*!< Q_HOLD_REQ_FORCE (Bitfield-Mask: 0x07) */ + #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_RELEASE_Pos (16UL) /*!< Q_HOLD_REQ_RELEASE (Bit 16) */ + #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_RELEASE_Msk (0x70000UL) /*!< Q_HOLD_REQ_RELEASE (Bitfield-Mask: 0x07) */ +/* ================================================= MMCTL_PREEMPT_STATUS ================================================== */ + #define R_ETHSW_MMCTL_PREEMPT_STATUS_PREEMPT_STATE_Pos (0UL) /*!< PREEMPT_STATE (Bit 0) */ + #define R_ETHSW_MMCTL_PREEMPT_STATUS_PREEMPT_STATE_Msk (0x7UL) /*!< PREEMPT_STATE (Bitfield-Mask: 0x07) */ + #define R_ETHSW_MMCTL_PREEMPT_STATUS_HOLD_REQ_STATE_Pos (16UL) /*!< HOLD_REQ_STATE (Bit 16) */ + #define R_ETHSW_MMCTL_PREEMPT_STATUS_HOLD_REQ_STATE_Msk (0x70000UL) /*!< HOLD_REQ_STATE (Bitfield-Mask: 0x07) */ +/* =================================================== MMCTL_CQF_CTRL_P ==================================================== */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_PRIO_ENABLE0_Pos (0UL) /*!< PRIO_ENABLE0 (Bit 0) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_PRIO_ENABLE0_Msk (0xffUL) /*!< PRIO_ENABLE0 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_QUEUE_SEL0_Pos (8UL) /*!< QUEUE_SEL0 (Bit 8) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_QUEUE_SEL0_Msk (0x700UL) /*!< QUEUE_SEL0 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_GATE_SEL0_Pos (11UL) /*!< GATE_SEL0 (Bit 11) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_GATE_SEL0_Msk (0x3800UL) /*!< GATE_SEL0 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_USE_SOP0_Pos (14UL) /*!< USE_SOP0 (Bit 14) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_USE_SOP0_Msk (0x4000UL) /*!< USE_SOP0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_REF_SEL0_Pos (15UL) /*!< REF_SEL0 (Bit 15) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_REF_SEL0_Msk (0x8000UL) /*!< REF_SEL0 (Bitfield-Mask: 0x01) */ +/* ============================================== MMCTL_P0_3_QCLOSED_NONEMPTY ============================================== */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P0_Q_STATUS_Pos (0UL) /*!< P0_Q_STATUS (Bit 0) */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P0_Q_STATUS_Msk (0xffUL) /*!< P0_Q_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P1_Q_STATUS_Pos (8UL) /*!< P1_Q_STATUS (Bit 8) */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P1_Q_STATUS_Msk (0xff00UL) /*!< P1_Q_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P2_Q_STATUS_Pos (16UL) /*!< P2_Q_STATUS (Bit 16) */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P2_Q_STATUS_Msk (0xff0000UL) /*!< P2_Q_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P3_Q_STATUS_Pos (24UL) /*!< P3_Q_STATUS (Bit 24) */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P3_Q_STATUS_Msk (0xff000000UL) /*!< P3_Q_STATUS (Bitfield-Mask: 0xff) */ +/* ================================================== MMCTL_PREEMPT_EXTRA ================================================== */ + #define R_ETHSW_MMCTL_PREEMPT_EXTRA_MIN_PFRM_ADJ_Pos (0UL) /*!< MIN_PFRM_ADJ (Bit 0) */ + #define R_ETHSW_MMCTL_PREEMPT_EXTRA_MIN_PFRM_ADJ_Msk (0xfUL) /*!< MIN_PFRM_ADJ (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MMCTL_PREEMPT_EXTRA_LAST_PFRM_ADJ_Pos (4UL) /*!< LAST_PFRM_ADJ (Bit 4) */ + #define R_ETHSW_MMCTL_PREEMPT_EXTRA_LAST_PFRM_ADJ_Msk (0xf0UL) /*!< LAST_PFRM_ADJ (Bitfield-Mask: 0x0f) */ +/* ====================================================== DLR_CONTROL ====================================================== */ + #define R_ETHSW_DLR_CONTROL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_ETHSW_DLR_CONTROL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_CONTROL_AUTOFLUSH_Pos (1UL) /*!< AUTOFLUSH (Bit 1) */ + #define R_ETHSW_DLR_CONTROL_AUTOFLUSH_Msk (0x2UL) /*!< AUTOFLUSH (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_CONTROL_LOOP_FILTER_ENA_Pos (2UL) /*!< LOOP_FILTER_ENA (Bit 2) */ + #define R_ETHSW_DLR_CONTROL_LOOP_FILTER_ENA_Msk (0x4UL) /*!< LOOP_FILTER_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_CONTROL_IGNORE_INVTM_Pos (4UL) /*!< IGNORE_INVTM (Bit 4) */ + #define R_ETHSW_DLR_CONTROL_IGNORE_INVTM_Msk (0x10UL) /*!< IGNORE_INVTM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_CONTROL_US_TIME_Pos (8UL) /*!< US_TIME (Bit 8) */ + #define R_ETHSW_DLR_CONTROL_US_TIME_Msk (0xfff00UL) /*!< US_TIME (Bitfield-Mask: 0xfff) */ +/* ====================================================== DLR_STATUS ======================================================= */ + #define R_ETHSW_DLR_STATUS_LastBcnRcvPort_Pos (0UL) /*!< LastBcnRcvPort (Bit 0) */ + #define R_ETHSW_DLR_STATUS_LastBcnRcvPort_Msk (0x3UL) /*!< LastBcnRcvPort (Bitfield-Mask: 0x03) */ + #define R_ETHSW_DLR_STATUS_NODE_STATE_Pos (8UL) /*!< NODE_STATE (Bit 8) */ + #define R_ETHSW_DLR_STATUS_NODE_STATE_Msk (0xff00UL) /*!< NODE_STATE (Bitfield-Mask: 0xff) */ + #define R_ETHSW_DLR_STATUS_LINK_STATUS_Pos (16UL) /*!< LINK_STATUS (Bit 16) */ + #define R_ETHSW_DLR_STATUS_LINK_STATUS_Msk (0x30000UL) /*!< LINK_STATUS (Bitfield-Mask: 0x03) */ + #define R_ETHSW_DLR_STATUS_TOPOLOGY_Pos (24UL) /*!< TOPOLOGY (Bit 24) */ + #define R_ETHSW_DLR_STATUS_TOPOLOGY_Msk (0xff000000UL) /*!< TOPOLOGY (Bitfield-Mask: 0xff) */ +/* ====================================================== DLR_ETH_TYP ====================================================== */ + #define R_ETHSW_DLR_ETH_TYP_DLR_ETH_TYP_Pos (0UL) /*!< DLR_ETH_TYP (Bit 0) */ + #define R_ETHSW_DLR_ETH_TYP_DLR_ETH_TYP_Msk (0xffffUL) /*!< DLR_ETH_TYP (Bitfield-Mask: 0xffff) */ +/* ==================================================== DLR_IRQ_CONTROL ==================================================== */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_state_chng_ena_Pos (0UL) /*!< IRQ_state_chng_ena (Bit 0) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_state_chng_ena_Msk (0x1UL) /*!< IRQ_state_chng_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_flush_macaddr_ena_Pos (1UL) /*!< IRQ_flush_macaddr_ena (Bit 1) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_flush_macaddr_ena_Msk (0x2UL) /*!< IRQ_flush_macaddr_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk0_ena_Pos (2UL) /*!< IRQ_stop_nbchk0_ena (Bit 2) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk0_ena_Msk (0x4UL) /*!< IRQ_stop_nbchk0_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk1_ena_Pos (3UL) /*!< IRQ_stop_nbchk1_ena (Bit 3) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk1_ena_Msk (0x8UL) /*!< IRQ_stop_nbchk1_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr0_exp_ena_Pos (4UL) /*!< IRQ_bec_tmr0_exp_ena (Bit 4) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr0_exp_ena_Msk (0x10UL) /*!< IRQ_bec_tmr0_exp_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr1_exp_ena_Pos (5UL) /*!< IRQ_bec_tmr1_exp_ena (Bit 5) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr1_exp_ena_Msk (0x20UL) /*!< IRQ_bec_tmr1_exp_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_supr_chng_ena_Pos (6UL) /*!< IRQ_supr_chng_ena (Bit 6) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_supr_chng_ena_Msk (0x40UL) /*!< IRQ_supr_chng_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng0_ena_Pos (7UL) /*!< IRQ_link_chng0_ena (Bit 7) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng0_ena_Msk (0x80UL) /*!< IRQ_link_chng0_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng1_ena_Pos (8UL) /*!< IRQ_link_chng1_ena (Bit 8) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng1_ena_Msk (0x100UL) /*!< IRQ_link_chng1_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_sup_ignord_ena_Pos (9UL) /*!< IRQ_sup_ignord_ena (Bit 9) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_sup_ignord_ena_Msk (0x200UL) /*!< IRQ_sup_ignord_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_ip_addr_chng_ena_Pos (10UL) /*!< IRQ_ip_addr_chng_ena (Bit 10) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_ip_addr_chng_ena_Msk (0x400UL) /*!< IRQ_ip_addr_chng_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_invalid_tmr_ena_Pos (11UL) /*!< IRQ_invalid_tmr_ena (Bit 11) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_invalid_tmr_ena_Msk (0x800UL) /*!< IRQ_invalid_tmr_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv0_ena_Pos (12UL) /*!< IRQ_bec_rcv0_ena (Bit 12) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv0_ena_Msk (0x1000UL) /*!< IRQ_bec_rcv0_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv1_ena_Pos (13UL) /*!< IRQ_bec_rcv1_ena (Bit 13) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv1_ena_Msk (0x2000UL) /*!< IRQ_bec_rcv1_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd0_Pos (14UL) /*!< IRQ_frm_dscrd0 (Bit 14) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd0_Msk (0x4000UL) /*!< IRQ_frm_dscrd0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd1_Pos (15UL) /*!< IRQ_frm_dscrd1 (Bit 15) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd1_Msk (0x8000UL) /*!< IRQ_frm_dscrd1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_low_int_en_Pos (29UL) /*!< low_int_en (Bit 29) */ + #define R_ETHSW_DLR_IRQ_CONTROL_low_int_en_Msk (0x20000000UL) /*!< low_int_en (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_atomic_OR_Pos (30UL) /*!< atomic_OR (Bit 30) */ + #define R_ETHSW_DLR_IRQ_CONTROL_atomic_OR_Msk (0x40000000UL) /*!< atomic_OR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_atomic_AND_Pos (31UL) /*!< atomic_AND (Bit 31) */ + #define R_ETHSW_DLR_IRQ_CONTROL_atomic_AND_Msk (0x80000000UL) /*!< atomic_AND (Bitfield-Mask: 0x01) */ +/* =================================================== DLR_IRQ_STAT_ACK ==================================================== */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_state_chng_IRQ_pending_Pos (0UL) /*!< state_chng_IRQ_pending (Bit 0) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_state_chng_IRQ_pending_Msk (0x1UL) /*!< state_chng_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_flush_IRQ_pending_Pos (1UL) /*!< flush_IRQ_pending (Bit 1) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_flush_IRQ_pending_Msk (0x2UL) /*!< flush_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk0_IRQ_pending_Pos (2UL) /*!< nbchk0_IRQ_pending (Bit 2) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk0_IRQ_pending_Msk (0x4UL) /*!< nbchk0_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk1_IRQ_pending_Pos (3UL) /*!< nbchk1_IRQ_pending (Bit 3) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk1_IRQ_pending_Msk (0x8UL) /*!< nbchk1_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr0_IRQ_pending_Pos (4UL) /*!< bec_tmr0_IRQ_pending (Bit 4) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr0_IRQ_pending_Msk (0x10UL) /*!< bec_tmr0_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr1_IRQ_pending_Pos (5UL) /*!< bec_tmr1_IRQ_pending (Bit 5) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr1_IRQ_pending_Msk (0x20UL) /*!< bec_tmr1_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_supr_chng_IRQ_pending_Pos (6UL) /*!< supr_chng_IRQ_pending (Bit 6) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_supr_chng_IRQ_pending_Msk (0x40UL) /*!< supr_chng_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_Link0_IRQ_pending_Pos (7UL) /*!< Link0_IRQ_pending (Bit 7) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_Link0_IRQ_pending_Msk (0x80UL) /*!< Link0_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_Link1_IRQ_pending_Pos (8UL) /*!< Link1_IRQ_pending (Bit 8) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_Link1_IRQ_pending_Msk (0x100UL) /*!< Link1_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_sup_ignord_IRQ_pending_Pos (9UL) /*!< sup_ignord_IRQ_pending (Bit 9) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_sup_ignord_IRQ_pending_Msk (0x200UL) /*!< sup_ignord_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_ip_chng_IRQ_pending_Pos (10UL) /*!< ip_chng_IRQ_pending (Bit 10) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_ip_chng_IRQ_pending_Msk (0x400UL) /*!< ip_chng_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_invalid_tmr_IRQ_pending_Pos (11UL) /*!< invalid_tmr_IRQ_pending (Bit 11) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_invalid_tmr_IRQ_pending_Msk (0x800UL) /*!< invalid_tmr_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv0_IRQ_pending_Pos (12UL) /*!< bec_rcv0_IRQ_pending (Bit 12) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv0_IRQ_pending_Msk (0x1000UL) /*!< bec_rcv0_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv1_IRQ_pending_Pos (13UL) /*!< bec_rcv1_IRQ_pending (Bit 13) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv1_IRQ_pending_Msk (0x2000UL) /*!< bec_rcv1_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd0_IRQ_pending_Pos (14UL) /*!< frm_dscrd0_IRQ_pending (Bit 14) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd0_IRQ_pending_Msk (0x4000UL) /*!< frm_dscrd0_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd1_IRQ_pending_Pos (15UL) /*!< frm_dscrd1_IRQ_pending (Bit 15) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd1_IRQ_pending_Msk (0x8000UL) /*!< frm_dscrd1_IRQ_pending (Bitfield-Mask: 0x01) */ +/* ===================================================== DLR_LOC_MAClo ===================================================== */ + #define R_ETHSW_DLR_LOC_MAClo_LOC_MAC_Pos (0UL) /*!< LOC_MAC (Bit 0) */ + #define R_ETHSW_DLR_LOC_MAClo_LOC_MAC_Msk (0xffffffffUL) /*!< LOC_MAC (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DLR_LOC_MAChi ===================================================== */ + #define R_ETHSW_DLR_LOC_MAChi_LOC_MAC_Pos (0UL) /*!< LOC_MAC (Bit 0) */ + #define R_ETHSW_DLR_LOC_MAChi_LOC_MAC_Msk (0xffffUL) /*!< LOC_MAC (Bitfield-Mask: 0xffff) */ +/* ==================================================== DLR_SUPR_MAClo ===================================================== */ + #define R_ETHSW_DLR_SUPR_MAClo_SUPR_MAC_Pos (0UL) /*!< SUPR_MAC (Bit 0) */ + #define R_ETHSW_DLR_SUPR_MAClo_SUPR_MAC_Msk (0xffffffffUL) /*!< SUPR_MAC (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DLR_SUPR_MAChi ===================================================== */ + #define R_ETHSW_DLR_SUPR_MAChi_SUPR_MAC_Pos (0UL) /*!< SUPR_MAC (Bit 0) */ + #define R_ETHSW_DLR_SUPR_MAChi_SUPR_MAC_Msk (0xffffUL) /*!< SUPR_MAC (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_DLR_SUPR_MAChi_PRECE_Pos (16UL) /*!< PRECE (Bit 16) */ + #define R_ETHSW_DLR_SUPR_MAChi_PRECE_Msk (0xff0000UL) /*!< PRECE (Bitfield-Mask: 0xff) */ +/* ==================================================== DLR_STATE_VLAN ===================================================== */ + #define R_ETHSW_DLR_STATE_VLAN_RINGSTAT_Pos (0UL) /*!< RINGSTAT (Bit 0) */ + #define R_ETHSW_DLR_STATE_VLAN_RINGSTAT_Msk (0xffUL) /*!< RINGSTAT (Bitfield-Mask: 0xff) */ + #define R_ETHSW_DLR_STATE_VLAN_VLANVALID_Pos (8UL) /*!< VLANVALID (Bit 8) */ + #define R_ETHSW_DLR_STATE_VLAN_VLANVALID_Msk (0x100UL) /*!< VLANVALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_STATE_VLAN_VLANINFO_Pos (16UL) /*!< VLANINFO (Bit 16) */ + #define R_ETHSW_DLR_STATE_VLAN_VLANINFO_Msk (0xffff0000UL) /*!< VLANINFO (Bitfield-Mask: 0xffff) */ +/* ===================================================== DLR_BEC_TMOUT ===================================================== */ + #define R_ETHSW_DLR_BEC_TMOUT_BEC_TMOUT_Pos (0UL) /*!< BEC_TMOUT (Bit 0) */ + #define R_ETHSW_DLR_BEC_TMOUT_BEC_TMOUT_Msk (0xffffffffUL) /*!< BEC_TMOUT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DLR_BEC_INTRVL ===================================================== */ + #define R_ETHSW_DLR_BEC_INTRVL_BEC_INTRVL_Pos (0UL) /*!< BEC_INTRVL (Bit 0) */ + #define R_ETHSW_DLR_BEC_INTRVL_BEC_INTRVL_Msk (0xffffffffUL) /*!< BEC_INTRVL (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DLR_SUPR_IPADR ===================================================== */ + #define R_ETHSW_DLR_SUPR_IPADR_SUPR_IPADR_Pos (0UL) /*!< SUPR_IPADR (Bit 0) */ + #define R_ETHSW_DLR_SUPR_IPADR_SUPR_IPADR_Msk (0xffffffffUL) /*!< SUPR_IPADR (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DLR_ETH_STYP_VER ==================================================== */ + #define R_ETHSW_DLR_ETH_STYP_VER_SUBTYPE_Pos (0UL) /*!< SUBTYPE (Bit 0) */ + #define R_ETHSW_DLR_ETH_STYP_VER_SUBTYPE_Msk (0xffUL) /*!< SUBTYPE (Bitfield-Mask: 0xff) */ + #define R_ETHSW_DLR_ETH_STYP_VER_PROTVER_Pos (8UL) /*!< PROTVER (Bit 8) */ + #define R_ETHSW_DLR_ETH_STYP_VER_PROTVER_Msk (0xff00UL) /*!< PROTVER (Bitfield-Mask: 0xff) */ + #define R_ETHSW_DLR_ETH_STYP_VER_SPORT_Pos (16UL) /*!< SPORT (Bit 16) */ + #define R_ETHSW_DLR_ETH_STYP_VER_SPORT_Msk (0xff0000UL) /*!< SPORT (Bitfield-Mask: 0xff) */ +/* ===================================================== DLR_INV_TMOUT ===================================================== */ + #define R_ETHSW_DLR_INV_TMOUT_INV_TMOUT_Pos (0UL) /*!< INV_TMOUT (Bit 0) */ + #define R_ETHSW_DLR_INV_TMOUT_INV_TMOUT_Msk (0xffffffffUL) /*!< INV_TMOUT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DLR_SEQ_ID ======================================================= */ + #define R_ETHSW_DLR_SEQ_ID_SEQ_ID_Pos (0UL) /*!< SEQ_ID (Bit 0) */ + #define R_ETHSW_DLR_SEQ_ID_SEQ_ID_Msk (0xffffffffUL) /*!< SEQ_ID (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DLR_DSTlo ======================================================= */ + #define R_ETHSW_DLR_DSTlo_DLR_DST_Pos (0UL) /*!< DLR_DST (Bit 0) */ + #define R_ETHSW_DLR_DSTlo_DLR_DST_Msk (0xffffffffUL) /*!< DLR_DST (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DLR_DSThi ======================================================= */ + #define R_ETHSW_DLR_DSThi_DLR_DST_Pos (0UL) /*!< DLR_DST (Bit 0) */ + #define R_ETHSW_DLR_DSThi_DLR_DST_Msk (0xffffUL) /*!< DLR_DST (Bitfield-Mask: 0xffff) */ +/* ===================================================== DLR_RX_STAT0 ====================================================== */ + #define R_ETHSW_DLR_RX_STAT0_RX_STAT0_Pos (0UL) /*!< RX_STAT0 (Bit 0) */ + #define R_ETHSW_DLR_RX_STAT0_RX_STAT0_Msk (0xffffffffUL) /*!< RX_STAT0 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DLR_RX_ERR_STAT0 ==================================================== */ + #define R_ETHSW_DLR_RX_ERR_STAT0_RX_ERR_STAT0_Pos (0UL) /*!< RX_ERR_STAT0 (Bit 0) */ + #define R_ETHSW_DLR_RX_ERR_STAT0_RX_ERR_STAT0_Msk (0xffffffffUL) /*!< RX_ERR_STAT0 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DLR_RX_LF_STAT0 ==================================================== */ + #define R_ETHSW_DLR_RX_LF_STAT0_RX_LF_STAT0_Pos (0UL) /*!< RX_LF_STAT0 (Bit 0) */ + #define R_ETHSW_DLR_RX_LF_STAT0_RX_LF_STAT0_Msk (0xffUL) /*!< RX_LF_STAT0 (Bitfield-Mask: 0xff) */ +/* ===================================================== DLR_RX_STAT1 ====================================================== */ + #define R_ETHSW_DLR_RX_STAT1_RX_STAT1_Pos (0UL) /*!< RX_STAT1 (Bit 0) */ + #define R_ETHSW_DLR_RX_STAT1_RX_STAT1_Msk (0xffffffffUL) /*!< RX_STAT1 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DLR_RX_ERR_STAT1 ==================================================== */ + #define R_ETHSW_DLR_RX_ERR_STAT1_RX_ERR_STAT1_Pos (0UL) /*!< RX_ERR_STAT1 (Bit 0) */ + #define R_ETHSW_DLR_RX_ERR_STAT1_RX_ERR_STAT1_Msk (0xffffffffUL) /*!< RX_ERR_STAT1 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DLR_RX_LF_STAT1 ==================================================== */ + #define R_ETHSW_DLR_RX_LF_STAT1_RX_LF_STAT1_Pos (0UL) /*!< RX_LF_STAT1 (Bit 0) */ + #define R_ETHSW_DLR_RX_LF_STAT1_RX_LF_STAT1_Msk (0xffUL) /*!< RX_LF_STAT1 (Bitfield-Mask: 0xff) */ +/* ====================================================== PRP_CONFIG ======================================================= */ + #define R_ETHSW_PRP_CONFIG_PRP_ENA_Pos (0UL) /*!< PRP_ENA (Bit 0) */ + #define R_ETHSW_PRP_CONFIG_PRP_ENA_Msk (0x1UL) /*!< PRP_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_RX_DUP_ACCEPT_Pos (1UL) /*!< RX_DUP_ACCEPT (Bit 1) */ + #define R_ETHSW_PRP_CONFIG_RX_DUP_ACCEPT_Msk (0x2UL) /*!< RX_DUP_ACCEPT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_RX_REMOVE_RCT_Pos (2UL) /*!< RX_REMOVE_RCT (Bit 2) */ + #define R_ETHSW_PRP_CONFIG_RX_REMOVE_RCT_Msk (0x4UL) /*!< RX_REMOVE_RCT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_MODE_Pos (3UL) /*!< TX_RCT_MODE (Bit 3) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_MODE_Msk (0x18UL) /*!< TX_RCT_MODE (Bitfield-Mask: 0x03) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_BROADCAST_Pos (5UL) /*!< TX_RCT_BROADCAST (Bit 5) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_BROADCAST_Msk (0x20UL) /*!< TX_RCT_BROADCAST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_MULTICAST_Pos (6UL) /*!< TX_RCT_MULTICAST (Bit 6) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_MULTICAST_Msk (0x40UL) /*!< TX_RCT_MULTICAST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_UNKNOWN_Pos (7UL) /*!< TX_RCT_UNKNOWN (Bit 7) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_UNKNOWN_Msk (0x80UL) /*!< TX_RCT_UNKNOWN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_1588_Pos (8UL) /*!< TX_RCT_1588 (Bit 8) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_1588_Msk (0x100UL) /*!< TX_RCT_1588 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_RCT_LEN_CHK_DIS_Pos (9UL) /*!< RCT_LEN_CHK_DIS (Bit 9) */ + #define R_ETHSW_PRP_CONFIG_RCT_LEN_CHK_DIS_Msk (0x200UL) /*!< RCT_LEN_CHK_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_PRP_AGE_ENA_Pos (16UL) /*!< PRP_AGE_ENA (Bit 16) */ + #define R_ETHSW_PRP_CONFIG_PRP_AGE_ENA_Msk (0x10000UL) /*!< PRP_AGE_ENA (Bitfield-Mask: 0x01) */ +/* ======================================================= PRP_GROUP ======================================================= */ + #define R_ETHSW_PRP_GROUP_PRP_GROUP_Pos (0UL) /*!< PRP_GROUP (Bit 0) */ + #define R_ETHSW_PRP_GROUP_PRP_GROUP_Msk (0x7UL) /*!< PRP_GROUP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_PRP_GROUP_LANB_MASK_Pos (16UL) /*!< LANB_MASK (Bit 16) */ + #define R_ETHSW_PRP_GROUP_LANB_MASK_Msk (0x70000UL) /*!< LANB_MASK (Bitfield-Mask: 0x07) */ +/* ====================================================== PRP_SUFFIX ======================================================= */ + #define R_ETHSW_PRP_SUFFIX_PRP_SUFFIX_Pos (0UL) /*!< PRP_SUFFIX (Bit 0) */ + #define R_ETHSW_PRP_SUFFIX_PRP_SUFFIX_Msk (0xffffUL) /*!< PRP_SUFFIX (Bitfield-Mask: 0xffff) */ +/* ======================================================= PRP_LANID ======================================================= */ + #define R_ETHSW_PRP_LANID_LANAID_Pos (0UL) /*!< LANAID (Bit 0) */ + #define R_ETHSW_PRP_LANID_LANAID_Msk (0xfUL) /*!< LANAID (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_PRP_LANID_LANBID_Pos (4UL) /*!< LANBID (Bit 4) */ + #define R_ETHSW_PRP_LANID_LANBID_Msk (0xf0UL) /*!< LANBID (Bitfield-Mask: 0x0f) */ +/* ========================================================= DUP_W ========================================================= */ + #define R_ETHSW_DUP_W_DUP_W_Pos (0UL) /*!< DUP_W (Bit 0) */ + #define R_ETHSW_DUP_W_DUP_W_Msk (0xffUL) /*!< DUP_W (Bitfield-Mask: 0xff) */ +/* ====================================================== PRP_AGETIME ====================================================== */ + #define R_ETHSW_PRP_AGETIME_PRP_AGETIME_Pos (0UL) /*!< PRP_AGETIME (Bit 0) */ + #define R_ETHSW_PRP_AGETIME_PRP_AGETIME_Msk (0xffffffUL) /*!< PRP_AGETIME (Bitfield-Mask: 0xffffff) */ +/* ==================================================== PRP_IRQ_CONTROL ==================================================== */ + #define R_ETHSW_PRP_IRQ_CONTROL_MEMTOOLATE_Pos (0UL) /*!< MEMTOOLATE (Bit 0) */ + #define R_ETHSW_PRP_IRQ_CONTROL_MEMTOOLATE_Msk (0x1UL) /*!< MEMTOOLATE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_IRQ_CONTROL_WRONGLAN_Pos (1UL) /*!< WRONGLAN (Bit 1) */ + #define R_ETHSW_PRP_IRQ_CONTROL_WRONGLAN_Msk (0x2UL) /*!< WRONGLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_IRQ_CONTROL_OUTOFSEQ_Pos (2UL) /*!< OUTOFSEQ (Bit 2) */ + #define R_ETHSW_PRP_IRQ_CONTROL_OUTOFSEQ_Msk (0x4UL) /*!< OUTOFSEQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_IRQ_CONTROL_SEQMISSING_Pos (3UL) /*!< SEQMISSING (Bit 3) */ + #define R_ETHSW_PRP_IRQ_CONTROL_SEQMISSING_Msk (0x8UL) /*!< SEQMISSING (Bitfield-Mask: 0x01) */ +/* =================================================== PRP_IRQ_STAT_ACK ==================================================== */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_MEMTOOLATE_Pos (0UL) /*!< MEMTOOLATE (Bit 0) */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_MEMTOOLATE_Msk (0x1UL) /*!< MEMTOOLATE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_WRONGLAN_Pos (1UL) /*!< WRONGLAN (Bit 1) */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_WRONGLAN_Msk (0x2UL) /*!< WRONGLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_OUTOFSEQ_Pos (2UL) /*!< OUTOFSEQ (Bit 2) */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_OUTOFSEQ_Msk (0x4UL) /*!< OUTOFSEQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_SEQMISSING_Pos (3UL) /*!< SEQMISSING (Bit 3) */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_SEQMISSING_Msk (0x8UL) /*!< SEQMISSING (Bitfield-Mask: 0x01) */ +/* ===================================================== RM_ADDR_CTRL ====================================================== */ + #define R_ETHSW_RM_ADDR_CTRL_address_Pos (0UL) /*!< address (Bit 0) */ + #define R_ETHSW_RM_ADDR_CTRL_address_Msk (0xfffUL) /*!< address (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_RM_ADDR_CTRL_CLEAR_DYNAMIC_Pos (22UL) /*!< CLEAR_DYNAMIC (Bit 22) */ + #define R_ETHSW_RM_ADDR_CTRL_CLEAR_DYNAMIC_Msk (0x400000UL) /*!< CLEAR_DYNAMIC (Bitfield-Mask: 0x01) */ + #define R_ETHSW_RM_ADDR_CTRL_CLEAR_MEMORY_Pos (23UL) /*!< CLEAR_MEMORY (Bit 23) */ + #define R_ETHSW_RM_ADDR_CTRL_CLEAR_MEMORY_Msk (0x800000UL) /*!< CLEAR_MEMORY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_RM_ADDR_CTRL_WRITE_Pos (25UL) /*!< WRITE (Bit 25) */ + #define R_ETHSW_RM_ADDR_CTRL_WRITE_Msk (0x2000000UL) /*!< WRITE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_RM_ADDR_CTRL_READ_Pos (26UL) /*!< READ (Bit 26) */ + #define R_ETHSW_RM_ADDR_CTRL_READ_Msk (0x4000000UL) /*!< READ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_RM_ADDR_CTRL_CLEAR_Pos (29UL) /*!< CLEAR (Bit 29) */ + #define R_ETHSW_RM_ADDR_CTRL_CLEAR_Msk (0x20000000UL) /*!< CLEAR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_RM_ADDR_CTRL_BUSY_Pos (31UL) /*!< BUSY (Bit 31) */ + #define R_ETHSW_RM_ADDR_CTRL_BUSY_Msk (0x80000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== RM_DATA ======================================================== */ + #define R_ETHSW_RM_DATA_RM_DATA_Pos (0UL) /*!< RM_DATA (Bit 0) */ + #define R_ETHSW_RM_DATA_RM_DATA_Msk (0xffffffffUL) /*!< RM_DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== RM_DATA_HI ======================================================= */ + #define R_ETHSW_RM_DATA_HI_RM_DATA_HI_Pos (0UL) /*!< RM_DATA_HI (Bit 0) */ + #define R_ETHSW_RM_DATA_HI_RM_DATA_HI_Msk (0xffffffffUL) /*!< RM_DATA_HI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= RM_STATUS ======================================================= */ + #define R_ETHSW_RM_STATUS_ageaddress_Pos (0UL) /*!< ageaddress (Bit 0) */ + #define R_ETHSW_RM_STATUS_ageaddress_Msk (0xfffUL) /*!< ageaddress (Bitfield-Mask: 0xfff) */ +/* ===================================================== TxSeqTooLate ====================================================== */ + #define R_ETHSW_TxSeqTooLate_TxSeqTooLate_Pos (0UL) /*!< TxSeqTooLate (Bit 0) */ + #define R_ETHSW_TxSeqTooLate_TxSeqTooLate_Msk (0xfUL) /*!< TxSeqTooLate (Bitfield-Mask: 0x0f) */ +/* ==================================================== CntErrWrongLanA ==================================================== */ + #define R_ETHSW_CntErrWrongLanA_CntErrWrongLanA_Pos (0UL) /*!< CntErrWrongLanA (Bit 0) */ + #define R_ETHSW_CntErrWrongLanA_CntErrWrongLanA_Msk (0xffffffffUL) /*!< CntErrWrongLanA (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CntErrWrongLanB ==================================================== */ + #define R_ETHSW_CntErrWrongLanB_CntErrWrongLanB_Pos (0UL) /*!< CntErrWrongLanB (Bit 0) */ + #define R_ETHSW_CntErrWrongLanB_CntErrWrongLanB_Msk (0xffffffffUL) /*!< CntErrWrongLanB (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CntDupLanA ======================================================= */ + #define R_ETHSW_CntDupLanA_CntDupLanA_Pos (0UL) /*!< CntDupLanA (Bit 0) */ + #define R_ETHSW_CntDupLanA_CntDupLanA_Msk (0xffffffffUL) /*!< CntDupLanA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CntDupLanB ======================================================= */ + #define R_ETHSW_CntDupLanB_CntDupLanB_Pos (0UL) /*!< CntDupLanB (Bit 0) */ + #define R_ETHSW_CntDupLanB_CntDupLanB_Msk (0xffffffffUL) /*!< CntDupLanB (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CntOutOfSeqLowA ==================================================== */ + #define R_ETHSW_CntOutOfSeqLowA_CntOutOfSeqLowA_Pos (0UL) /*!< CntOutOfSeqLowA (Bit 0) */ + #define R_ETHSW_CntOutOfSeqLowA_CntOutOfSeqLowA_Msk (0xffffffffUL) /*!< CntOutOfSeqLowA (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CntOutOfSeqLowB ==================================================== */ + #define R_ETHSW_CntOutOfSeqLowB_CntOutOfSeqLowB_Pos (0UL) /*!< CntOutOfSeqLowB (Bit 0) */ + #define R_ETHSW_CntOutOfSeqLowB_CntOutOfSeqLowB_Msk (0xffffffffUL) /*!< CntOutOfSeqLowB (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CntOutOfSeqA ====================================================== */ + #define R_ETHSW_CntOutOfSeqA_CntOutOfSeqA_Pos (0UL) /*!< CntOutOfSeqA (Bit 0) */ + #define R_ETHSW_CntOutOfSeqA_CntOutOfSeqA_Msk (0xffffffffUL) /*!< CntOutOfSeqA (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CntOutOfSeqB ====================================================== */ + #define R_ETHSW_CntOutOfSeqB_CntOutOfSeqB_Pos (0UL) /*!< CntOutOfSeqB (Bit 0) */ + #define R_ETHSW_CntOutOfSeqB_CntOutOfSeqB_Msk (0xffffffffUL) /*!< CntOutOfSeqB (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CntAcceptA ======================================================= */ + #define R_ETHSW_CntAcceptA_CntAcceptA_Pos (0UL) /*!< CntAcceptA (Bit 0) */ + #define R_ETHSW_CntAcceptA_CntAcceptA_Msk (0xffffffffUL) /*!< CntAcceptA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CntAcceptB ======================================================= */ + #define R_ETHSW_CntAcceptB_CntAcceptB_Pos (0UL) /*!< CntAcceptB (Bit 0) */ + #define R_ETHSW_CntAcceptB_CntAcceptB_Msk (0xffffffffUL) /*!< CntAcceptB (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CntMissing ======================================================= */ + #define R_ETHSW_CntMissing_CntMissing_Pos (0UL) /*!< CntMissing (Bit 0) */ + #define R_ETHSW_CntMissing_CntMissing_Msk (0xffffffffUL) /*!< CntMissing (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== HUB_CONFIG ======================================================= */ + #define R_ETHSW_HUB_CONFIG_HUB_ENA_Pos (0UL) /*!< HUB_ENA (Bit 0) */ + #define R_ETHSW_HUB_CONFIG_HUB_ENA_Msk (0x1UL) /*!< HUB_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_CONFIG_RETRANSMIT_ENA_Pos (1UL) /*!< RETRANSMIT_ENA (Bit 1) */ + #define R_ETHSW_HUB_CONFIG_RETRANSMIT_ENA_Msk (0x2UL) /*!< RETRANSMIT_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_CONFIG_TRIGGER_MODE_Pos (2UL) /*!< TRIGGER_MODE (Bit 2) */ + #define R_ETHSW_HUB_CONFIG_TRIGGER_MODE_Msk (0x4UL) /*!< TRIGGER_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_CONFIG_HUB_ISOLATE_Pos (3UL) /*!< HUB_ISOLATE (Bit 3) */ + #define R_ETHSW_HUB_CONFIG_HUB_ISOLATE_Msk (0x8UL) /*!< HUB_ISOLATE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_CONFIG_TIMER_SEL_Pos (4UL) /*!< TIMER_SEL (Bit 4) */ + #define R_ETHSW_HUB_CONFIG_TIMER_SEL_Msk (0x10UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_CONFIG_IPG_WAIT_Pos (6UL) /*!< IPG_WAIT (Bit 6) */ + #define R_ETHSW_HUB_CONFIG_IPG_WAIT_Msk (0x1c0UL) /*!< IPG_WAIT (Bitfield-Mask: 0x07) */ + #define R_ETHSW_HUB_CONFIG_CRS_GEN_Pos (9UL) /*!< CRS_GEN (Bit 9) */ + #define R_ETHSW_HUB_CONFIG_CRS_GEN_Msk (0x200UL) /*!< CRS_GEN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_CONFIG_PRMB_GEN_DIS_Pos (10UL) /*!< PRMB_GEN_DIS (Bit 10) */ + #define R_ETHSW_HUB_CONFIG_PRMB_GEN_DIS_Msk (0x400UL) /*!< PRMB_GEN_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_CONFIG_JAM_WAIT_IDLE_Pos (11UL) /*!< JAM_WAIT_IDLE (Bit 11) */ + #define R_ETHSW_HUB_CONFIG_JAM_WAIT_IDLE_Msk (0x800UL) /*!< JAM_WAIT_IDLE (Bitfield-Mask: 0x01) */ +/* ======================================================= HUB_GROUP ======================================================= */ + #define R_ETHSW_HUB_GROUP_HUB_GROUP_Pos (0UL) /*!< HUB_GROUP (Bit 0) */ + #define R_ETHSW_HUB_GROUP_HUB_GROUP_Msk (0x7UL) /*!< HUB_GROUP (Bitfield-Mask: 0x07) */ +/* ====================================================== HUB_DEFPORT ====================================================== */ + #define R_ETHSW_HUB_DEFPORT_HUB_DEFPORT_Pos (0UL) /*!< HUB_DEFPORT (Bit 0) */ + #define R_ETHSW_HUB_DEFPORT_HUB_DEFPORT_Msk (0x7UL) /*!< HUB_DEFPORT (Bitfield-Mask: 0x07) */ +/* ================================================= HUB_TRIGGER_IMMEDIATE ================================================= */ + #define R_ETHSW_HUB_TRIGGER_IMMEDIATE_HUB_TRIGGER_IMMEDIATE_Pos (0UL) /*!< HUB_TRIGGER_IMMEDIATE (Bit 0) */ + #define R_ETHSW_HUB_TRIGGER_IMMEDIATE_HUB_TRIGGER_IMMEDIATE_Msk (0x7UL) /*!< HUB_TRIGGER_IMMEDIATE (Bitfield-Mask: 0x07) */ +/* ==================================================== HUB_TRIGGER_AT ===================================================== */ + #define R_ETHSW_HUB_TRIGGER_AT_HUB_TRIGGER_AT_Pos (0UL) /*!< HUB_TRIGGER_AT (Bit 0) */ + #define R_ETHSW_HUB_TRIGGER_AT_HUB_TRIGGER_AT_Msk (0x7UL) /*!< HUB_TRIGGER_AT (Bitfield-Mask: 0x07) */ +/* ======================================================= HUB_TTIME ======================================================= */ + #define R_ETHSW_HUB_TTIME_HUB_TTIME_Pos (0UL) /*!< HUB_TTIME (Bit 0) */ + #define R_ETHSW_HUB_TTIME_HUB_TTIME_Msk (0xffffffffUL) /*!< HUB_TTIME (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== HUB_IRQ_CONTROL ==================================================== */ + #define R_ETHSW_HUB_IRQ_CONTROL_RX_TRIGGER_Pos (0UL) /*!< RX_TRIGGER (Bit 0) */ + #define R_ETHSW_HUB_IRQ_CONTROL_RX_TRIGGER_Msk (0x7UL) /*!< RX_TRIGGER (Bitfield-Mask: 0x07) */ + #define R_ETHSW_HUB_IRQ_CONTROL_CHANGE_DET_Pos (3UL) /*!< CHANGE_DET (Bit 3) */ + #define R_ETHSW_HUB_IRQ_CONTROL_CHANGE_DET_Msk (0x8UL) /*!< CHANGE_DET (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_IMMEDIATE_Pos (4UL) /*!< TRIGGER_IMMEDIATE (Bit 4) */ + #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_IMMEDIATE_Msk (0x10UL) /*!< TRIGGER_IMMEDIATE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_TIMER_Pos (5UL) /*!< TRIGGER_TIMER (Bit 5) */ + #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_TIMER_Msk (0x20UL) /*!< TRIGGER_TIMER (Bitfield-Mask: 0x01) */ +/* =================================================== HUB_IRQ_STAT_ACK ==================================================== */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_RX_TRIGGER_Pos (0UL) /*!< RX_TRIGGER (Bit 0) */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_RX_TRIGGER_Msk (0x7UL) /*!< RX_TRIGGER (Bitfield-Mask: 0x07) */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_CHANGE_DET_Pos (3UL) /*!< CHANGE_DET (Bit 3) */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_CHANGE_DET_Msk (0x8UL) /*!< CHANGE_DET (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_IMMEDIATE_Pos (4UL) /*!< TRIGGER_IMMEDIATE (Bit 4) */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_IMMEDIATE_Msk (0x10UL) /*!< TRIGGER_IMMEDIATE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_TIMER_Pos (5UL) /*!< TRIGGER_TIMER (Bit 5) */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_TIMER_Msk (0x20UL) /*!< TRIGGER_TIMER (Bitfield-Mask: 0x01) */ +/* ====================================================== HUB_STATUS ======================================================= */ + #define R_ETHSW_HUB_STATUS_PORTS_ACTIVE_Pos (0UL) /*!< PORTS_ACTIVE (Bit 0) */ + #define R_ETHSW_HUB_STATUS_PORTS_ACTIVE_Msk (0x7UL) /*!< PORTS_ACTIVE (Bitfield-Mask: 0x07) */ + #define R_ETHSW_HUB_STATUS_TX_ACTIVE_Pos (9UL) /*!< TX_ACTIVE (Bit 9) */ + #define R_ETHSW_HUB_STATUS_TX_ACTIVE_Msk (0x200UL) /*!< TX_ACTIVE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_STATUS_TX_BUSY_Pos (10UL) /*!< TX_BUSY (Bit 10) */ + #define R_ETHSW_HUB_STATUS_TX_BUSY_Msk (0x400UL) /*!< TX_BUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_STATUS_Speed_OK_Pos (11UL) /*!< Speed_OK (Bit 11) */ + #define R_ETHSW_HUB_STATUS_Speed_OK_Msk (0x800UL) /*!< Speed_OK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_STATUS_TX_Change_Pending_Pos (12UL) /*!< TX_Change_Pending (Bit 12) */ + #define R_ETHSW_HUB_STATUS_TX_Change_Pending_Msk (0x1000UL) /*!< TX_Change_Pending (Bitfield-Mask: 0x01) */ +/* =================================================== HUB_OPORT_STATUS ==================================================== */ + #define R_ETHSW_HUB_OPORT_STATUS_HUB_OPORT_STATUS_Pos (0UL) /*!< HUB_OPORT_STATUS (Bit 0) */ + #define R_ETHSW_HUB_OPORT_STATUS_HUB_OPORT_STATUS_Msk (0x7UL) /*!< HUB_OPORT_STATUS (Bitfield-Mask: 0x07) */ +/* ====================================================== TDMA_CONFIG ====================================================== */ + #define R_ETHSW_TDMA_CONFIG_TDMA_ENA_Pos (0UL) /*!< TDMA_ENA (Bit 0) */ + #define R_ETHSW_TDMA_CONFIG_TDMA_ENA_Msk (0x1UL) /*!< TDMA_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_WAIT_START_Pos (1UL) /*!< WAIT_START (Bit 1) */ + #define R_ETHSW_TDMA_CONFIG_WAIT_START_Msk (0x2UL) /*!< WAIT_START (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_Pos (2UL) /*!< TIMER_SEL (Bit 2) */ + #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_Msk (0x4UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_RED_PERIOD_Pos (4UL) /*!< RED_PERIOD (Bit 4) */ + #define R_ETHSW_TDMA_CONFIG_RED_PERIOD_Msk (0x10UL) /*!< RED_PERIOD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_RED_OVRD_ENA_Pos (5UL) /*!< RED_OVRD_ENA (Bit 5) */ + #define R_ETHSW_TDMA_CONFIG_RED_OVRD_ENA_Msk (0x20UL) /*!< RED_OVRD_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_RED_OVRD_Pos (6UL) /*!< RED_OVRD (Bit 6) */ + #define R_ETHSW_TDMA_CONFIG_RED_OVRD_Msk (0x40UL) /*!< RED_OVRD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_IN_CT_WREN_Pos (7UL) /*!< IN_CT_WREN (Bit 7) */ + #define R_ETHSW_TDMA_CONFIG_IN_CT_WREN_Msk (0x80UL) /*!< IN_CT_WREN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_OUT_CT_WREN_Pos (8UL) /*!< OUT_CT_WREN (Bit 8) */ + #define R_ETHSW_TDMA_CONFIG_OUT_CT_WREN_Msk (0x100UL) /*!< OUT_CT_WREN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_HOLD_REQ_CLR_Pos (9UL) /*!< HOLD_REQ_CLR (Bit 9) */ + #define R_ETHSW_TDMA_CONFIG_HOLD_REQ_CLR_Msk (0x200UL) /*!< HOLD_REQ_CLR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_ACTIVE_Pos (12UL) /*!< TIMER_SEL_ACTIVE (Bit 12) */ + #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_ACTIVE_Msk (0x1000UL) /*!< TIMER_SEL_ACTIVE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_IN_CT_ENA_Pos (16UL) /*!< IN_CT_ENA (Bit 16) */ + #define R_ETHSW_TDMA_CONFIG_IN_CT_ENA_Msk (0xf0000UL) /*!< IN_CT_ENA (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_TDMA_CONFIG_OUT_CT_ENA_Pos (24UL) /*!< OUT_CT_ENA (Bit 24) */ + #define R_ETHSW_TDMA_CONFIG_OUT_CT_ENA_Msk (0xf000000UL) /*!< OUT_CT_ENA (Bitfield-Mask: 0x0f) */ +/* ===================================================== TDMA_ENA_CTRL ===================================================== */ + #define R_ETHSW_TDMA_ENA_CTRL_PORT_ENA_Pos (0UL) /*!< PORT_ENA (Bit 0) */ + #define R_ETHSW_TDMA_ENA_CTRL_PORT_ENA_Msk (0xfUL) /*!< PORT_ENA (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_TDMA_ENA_CTRL_QGATE_DIS_Pos (16UL) /*!< QGATE_DIS (Bit 16) */ + #define R_ETHSW_TDMA_ENA_CTRL_QGATE_DIS_Msk (0xff0000UL) /*!< QGATE_DIS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_TDMA_ENA_CTRL_QTRIG_DIS_Pos (24UL) /*!< QTRIG_DIS (Bit 24) */ + #define R_ETHSW_TDMA_ENA_CTRL_QTRIG_DIS_Msk (0xff000000UL) /*!< QTRIG_DIS (Bitfield-Mask: 0xff) */ +/* ====================================================== TDMA_START ======================================================= */ + #define R_ETHSW_TDMA_START_TDMA_START_Pos (0UL) /*!< TDMA_START (Bit 0) */ + #define R_ETHSW_TDMA_START_TDMA_START_Msk (0xffffffffUL) /*!< TDMA_START (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TDMA_MODULO ====================================================== */ + #define R_ETHSW_TDMA_MODULO_TDMA_MODULO_Pos (0UL) /*!< TDMA_MODULO (Bit 0) */ + #define R_ETHSW_TDMA_MODULO_TDMA_MODULO_Msk (0xffffffffUL) /*!< TDMA_MODULO (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TDMA_CYCLE ======================================================= */ + #define R_ETHSW_TDMA_CYCLE_TDMA_CYCLE_Pos (0UL) /*!< TDMA_CYCLE (Bit 0) */ + #define R_ETHSW_TDMA_CYCLE_TDMA_CYCLE_Msk (0xffffffffUL) /*!< TDMA_CYCLE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== TCV_SEQ_ADDR ====================================================== */ + #define R_ETHSW_TCV_SEQ_ADDR_TCV_S_ADDR_Pos (0UL) /*!< TCV_S_ADDR (Bit 0) */ + #define R_ETHSW_TCV_SEQ_ADDR_TCV_S_ADDR_Msk (0xfffUL) /*!< TCV_S_ADDR (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_TCV_SEQ_ADDR_ADDR_AINC_Pos (31UL) /*!< ADDR_AINC (Bit 31) */ + #define R_ETHSW_TCV_SEQ_ADDR_ADDR_AINC_Msk (0x80000000UL) /*!< ADDR_AINC (Bitfield-Mask: 0x01) */ +/* ===================================================== TCV_SEQ_CTRL ====================================================== */ + #define R_ETHSW_TCV_SEQ_CTRL_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_ETHSW_TCV_SEQ_CTRL_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_SEQ_CTRL_INT_Pos (1UL) /*!< INT (Bit 1) */ + #define R_ETHSW_TCV_SEQ_CTRL_INT_Msk (0x2UL) /*!< INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_SEQ_CTRL_TCV_D_IDX_Pos (2UL) /*!< TCV_D_IDX (Bit 2) */ + #define R_ETHSW_TCV_SEQ_CTRL_TCV_D_IDX_Msk (0x7fcUL) /*!< TCV_D_IDX (Bitfield-Mask: 0x1ff) */ + #define R_ETHSW_TCV_SEQ_CTRL_GPIO_Pos (22UL) /*!< GPIO (Bit 22) */ + #define R_ETHSW_TCV_SEQ_CTRL_GPIO_Msk (0x3fc00000UL) /*!< GPIO (Bitfield-Mask: 0xff) */ + #define R_ETHSW_TCV_SEQ_CTRL_READ_MODE_Pos (31UL) /*!< READ_MODE (Bit 31) */ + #define R_ETHSW_TCV_SEQ_CTRL_READ_MODE_Msk (0x80000000UL) /*!< READ_MODE (Bitfield-Mask: 0x01) */ +/* ===================================================== TCV_SEQ_LAST ====================================================== */ + #define R_ETHSW_TCV_SEQ_LAST_LAST_Pos (0UL) /*!< LAST (Bit 0) */ + #define R_ETHSW_TCV_SEQ_LAST_LAST_Msk (0xfffUL) /*!< LAST (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_TCV_SEQ_LAST_ACTIVE_Pos (16UL) /*!< ACTIVE (Bit 16) */ + #define R_ETHSW_TCV_SEQ_LAST_ACTIVE_Msk (0xfff0000UL) /*!< ACTIVE (Bitfield-Mask: 0xfff) */ +/* ====================================================== TCV_D_ADDR ======================================================= */ + #define R_ETHSW_TCV_D_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ETHSW_TCV_D_ADDR_ADDR_Msk (0x1ffUL) /*!< ADDR (Bitfield-Mask: 0x1ff) */ + #define R_ETHSW_TCV_D_ADDR_AINC_WR_ENA_Pos (31UL) /*!< AINC_WR_ENA (Bit 31) */ + #define R_ETHSW_TCV_D_ADDR_AINC_WR_ENA_Msk (0x80000000UL) /*!< AINC_WR_ENA (Bitfield-Mask: 0x01) */ +/* ===================================================== TCV_D_OFFSET ====================================================== */ + #define R_ETHSW_TCV_D_OFFSET_TCV_D_OFFSET_Pos (0UL) /*!< TCV_D_OFFSET (Bit 0) */ + #define R_ETHSW_TCV_D_OFFSET_TCV_D_OFFSET_Msk (0xffffffffUL) /*!< TCV_D_OFFSET (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TCV_D_CTRL ======================================================= */ + #define R_ETHSW_TCV_D_CTRL_INC_CTR0_Pos (0UL) /*!< INC_CTR0 (Bit 0) */ + #define R_ETHSW_TCV_D_CTRL_INC_CTR0_Msk (0x1UL) /*!< INC_CTR0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_INC_CTR1_Pos (1UL) /*!< INC_CTR1 (Bit 1) */ + #define R_ETHSW_TCV_D_CTRL_INC_CTR1_Msk (0x2UL) /*!< INC_CTR1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_RED_PERIOD_Pos (2UL) /*!< RED_PERIOD (Bit 2) */ + #define R_ETHSW_TCV_D_CTRL_RED_PERIOD_Msk (0x4UL) /*!< RED_PERIOD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_OUT_CT_ENA_Pos (3UL) /*!< OUT_CT_ENA (Bit 3) */ + #define R_ETHSW_TCV_D_CTRL_OUT_CT_ENA_Msk (0x8UL) /*!< OUT_CT_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_IN_CT_ENA_Pos (4UL) /*!< IN_CT_ENA (Bit 4) */ + #define R_ETHSW_TCV_D_CTRL_IN_CT_ENA_Msk (0x10UL) /*!< IN_CT_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_TRIGGER_MODE_Pos (5UL) /*!< TRIGGER_MODE (Bit 5) */ + #define R_ETHSW_TCV_D_CTRL_TRIGGER_MODE_Msk (0x20UL) /*!< TRIGGER_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_GATE_MODE_Pos (6UL) /*!< GATE_MODE (Bit 6) */ + #define R_ETHSW_TCV_D_CTRL_GATE_MODE_Msk (0x40UL) /*!< GATE_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_HOLD_REQ_Pos (7UL) /*!< HOLD_REQ (Bit 7) */ + #define R_ETHSW_TCV_D_CTRL_HOLD_REQ_Msk (0x80UL) /*!< HOLD_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_QGATE_Pos (8UL) /*!< QGATE (Bit 8) */ + #define R_ETHSW_TCV_D_CTRL_QGATE_Msk (0xff00UL) /*!< QGATE (Bitfield-Mask: 0xff) */ + #define R_ETHSW_TCV_D_CTRL_PMASK_Pos (16UL) /*!< PMASK (Bit 16) */ + #define R_ETHSW_TCV_D_CTRL_PMASK_Msk (0xf0000UL) /*!< PMASK (Bitfield-Mask: 0x0f) */ +/* ======================================================= TDMA_CTR0 ======================================================= */ + #define R_ETHSW_TDMA_CTR0_TDMA_CTR0_Pos (0UL) /*!< TDMA_CTR0 (Bit 0) */ + #define R_ETHSW_TDMA_CTR0_TDMA_CTR0_Msk (0xffffffffUL) /*!< TDMA_CTR0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TDMA_CTR1 ======================================================= */ + #define R_ETHSW_TDMA_CTR1_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ + #define R_ETHSW_TDMA_CTR1_VALUE_Msk (0xffUL) /*!< VALUE (Bitfield-Mask: 0xff) */ + #define R_ETHSW_TDMA_CTR1_WRITE_ENA_Pos (8UL) /*!< WRITE_ENA (Bit 8) */ + #define R_ETHSW_TDMA_CTR1_WRITE_ENA_Msk (0x100UL) /*!< WRITE_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CTR1_MAX_Pos (16UL) /*!< MAX (Bit 16) */ + #define R_ETHSW_TDMA_CTR1_MAX_Msk (0xff0000UL) /*!< MAX (Bitfield-Mask: 0xff) */ + #define R_ETHSW_TDMA_CTR1_INT_VALUE_Pos (24UL) /*!< INT_VALUE (Bit 24) */ + #define R_ETHSW_TDMA_CTR1_INT_VALUE_Msk (0xff000000UL) /*!< INT_VALUE (Bitfield-Mask: 0xff) */ +/* ==================================================== TDMA_TCV_START ===================================================== */ + #define R_ETHSW_TDMA_TCV_START_TDMA_TCV_START_Pos (0UL) /*!< TDMA_TCV_START (Bit 0) */ + #define R_ETHSW_TDMA_TCV_START_TDMA_TCV_START_Msk (0xfffUL) /*!< TDMA_TCV_START (Bitfield-Mask: 0xfff) */ +/* ==================================================== TIME_LOAD_NEXT ===================================================== */ + #define R_ETHSW_TIME_LOAD_NEXT_TIME_LOAD_NEXT_Pos (0UL) /*!< TIME_LOAD_NEXT (Bit 0) */ + #define R_ETHSW_TIME_LOAD_NEXT_TIME_LOAD_NEXT_Msk (0xffffffffUL) /*!< TIME_LOAD_NEXT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TDMA_IRQ_CONTROL ==================================================== */ + #define R_ETHSW_TDMA_IRQ_CONTROL_TCV_INT_EN_Pos (0UL) /*!< TCV_INT_EN (Bit 0) */ + #define R_ETHSW_TDMA_IRQ_CONTROL_TCV_INT_EN_Msk (0x1UL) /*!< TCV_INT_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_IRQ_CONTROL_CTR1_INT_EN_Pos (13UL) /*!< CTR1_INT_EN (Bit 13) */ + #define R_ETHSW_TDMA_IRQ_CONTROL_CTR1_INT_EN_Msk (0x2000UL) /*!< CTR1_INT_EN (Bitfield-Mask: 0x01) */ +/* =================================================== TDMA_IRQ_STAT_ACK =================================================== */ + #define R_ETHSW_TDMA_IRQ_STAT_ACK_TCV_ACK_Pos (0UL) /*!< TCV_ACK (Bit 0) */ + #define R_ETHSW_TDMA_IRQ_STAT_ACK_TCV_ACK_Msk (0x1UL) /*!< TCV_ACK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_IRQ_STAT_ACK_CTR1_ACK_Pos (13UL) /*!< CTR1_ACK (Bit 13) */ + #define R_ETHSW_TDMA_IRQ_STAT_ACK_CTR1_ACK_Msk (0x2000UL) /*!< CTR1_ACK (Bitfield-Mask: 0x01) */ +/* ======================================================= TDMA_GPIO ======================================================= */ + #define R_ETHSW_TDMA_GPIO_GPIO_STATUS_Pos (0UL) /*!< GPIO_STATUS (Bit 0) */ + #define R_ETHSW_TDMA_GPIO_GPIO_STATUS_Msk (0xffUL) /*!< GPIO_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_TDMA_GPIO_GPIO_MODE_Pos (16UL) /*!< GPIO_MODE (Bit 16) */ + #define R_ETHSW_TDMA_GPIO_GPIO_MODE_Msk (0xffff0000UL) /*!< GPIO_MODE (Bitfield-Mask: 0xffff) */ +/* ==================================================== RXMATCH_CONFIG ===================================================== */ + #define R_ETHSW_RXMATCH_CONFIG_PATTERN_EN_Pos (0UL) /*!< PATTERN_EN (Bit 0) */ + #define R_ETHSW_RXMATCH_CONFIG_PATTERN_EN_Msk (0xfffUL) /*!< PATTERN_EN (Bitfield-Mask: 0xfff) */ +/* ===================================================== PATTERN_CTRL ====================================================== */ + #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_Pos (0UL) /*!< MATCH_NOT (Bit 0) */ + #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_Msk (0x1UL) /*!< MATCH_NOT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_MGMTFWD_Pos (1UL) /*!< MGMTFWD (Bit 1) */ + #define R_ETHSW_PATTERN_CTRL_MGMTFWD_Msk (0x2UL) /*!< MGMTFWD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_DISCARD_Pos (2UL) /*!< DISCARD (Bit 2) */ + #define R_ETHSW_PATTERN_CTRL_DISCARD_Msk (0x4UL) /*!< DISCARD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_SET_PRIO_Pos (3UL) /*!< SET_PRIO (Bit 3) */ + #define R_ETHSW_PATTERN_CTRL_SET_PRIO_Msk (0x8UL) /*!< SET_PRIO (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_MODE_Pos (4UL) /*!< MODE (Bit 4) */ + #define R_ETHSW_PATTERN_CTRL_MODE_Msk (0x30UL) /*!< MODE (Bitfield-Mask: 0x03) */ + #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_OVR_Pos (6UL) /*!< TIMER_SEL_OVR (Bit 6) */ + #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_OVR_Msk (0x40UL) /*!< TIMER_SEL_OVR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_FORCE_FORWARD_Pos (7UL) /*!< FORCE_FORWARD (Bit 7) */ + #define R_ETHSW_PATTERN_CTRL_FORCE_FORWARD_Msk (0x80UL) /*!< FORCE_FORWARD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_HUBTRIGGER_Pos (8UL) /*!< HUBTRIGGER (Bit 8) */ + #define R_ETHSW_PATTERN_CTRL_HUBTRIGGER_Msk (0x100UL) /*!< HUBTRIGGER (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_MATCH_RED_Pos (9UL) /*!< MATCH_RED (Bit 9) */ + #define R_ETHSW_PATTERN_CTRL_MATCH_RED_Msk (0x200UL) /*!< MATCH_RED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_RED_Pos (10UL) /*!< MATCH_NOT_RED (Bit 10) */ + #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_RED_Msk (0x400UL) /*!< MATCH_NOT_RED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_VLAN_SKIP_Pos (11UL) /*!< VLAN_SKIP (Bit 11) */ + #define R_ETHSW_PATTERN_CTRL_VLAN_SKIP_Msk (0x800UL) /*!< VLAN_SKIP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_PRIORITY_Pos (12UL) /*!< PRIORITY (Bit 12) */ + #define R_ETHSW_PATTERN_CTRL_PRIORITY_Msk (0x7000UL) /*!< PRIORITY (Bitfield-Mask: 0x07) */ + #define R_ETHSW_PATTERN_CTRL_LEARNING_DIS_Pos (15UL) /*!< LEARNING_DIS (Bit 15) */ + #define R_ETHSW_PATTERN_CTRL_LEARNING_DIS_Msk (0x8000UL) /*!< LEARNING_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_PORTMASK_Pos (16UL) /*!< PORTMASK (Bit 16) */ + #define R_ETHSW_PATTERN_CTRL_PORTMASK_Msk (0xf0000UL) /*!< PORTMASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_Pos (22UL) /*!< IMC_TRIGGER (Bit 22) */ + #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_Msk (0x400000UL) /*!< IMC_TRIGGER (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_DLY_Pos (23UL) /*!< IMC_TRIGGER_DLY (Bit 23) */ + #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_DLY_Msk (0x800000UL) /*!< IMC_TRIGGER_DLY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_SWAP_BYTES_Pos (24UL) /*!< SWAP_BYTES (Bit 24) */ + #define R_ETHSW_PATTERN_CTRL_SWAP_BYTES_Msk (0x1000000UL) /*!< SWAP_BYTES (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_MATCH_LT_Pos (25UL) /*!< MATCH_LT (Bit 25) */ + #define R_ETHSW_PATTERN_CTRL_MATCH_LT_Msk (0x2000000UL) /*!< MATCH_LT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_Pos (26UL) /*!< TIMER_SEL (Bit 26) */ + #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_Msk (0x4000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_QUEUESEL_Pos (28UL) /*!< QUEUESEL (Bit 28) */ + #define R_ETHSW_PATTERN_CTRL_QUEUESEL_Msk (0xf0000000UL) /*!< QUEUESEL (Bitfield-Mask: 0x0f) */ +/* ================================================== PATTERN_IRQ_CONTROL ================================================== */ + #define R_ETHSW_PATTERN_IRQ_CONTROL_MATCHINT_Pos (0UL) /*!< MATCHINT (Bit 0) */ + #define R_ETHSW_PATTERN_IRQ_CONTROL_MATCHINT_Msk (0xfffUL) /*!< MATCHINT (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_PATTERN_IRQ_CONTROL_ERROR_INT_Pos (16UL) /*!< ERROR_INT (Bit 16) */ + #define R_ETHSW_PATTERN_IRQ_CONTROL_ERROR_INT_Msk (0xf0000UL) /*!< ERROR_INT (Bitfield-Mask: 0x0f) */ +/* ================================================= PATTERN_IRQ_STAT_ACK ================================================== */ + #define R_ETHSW_PATTERN_IRQ_STAT_ACK_MATCHINT_Pos (0UL) /*!< MATCHINT (Bit 0) */ + #define R_ETHSW_PATTERN_IRQ_STAT_ACK_MATCHINT_Msk (0xfffUL) /*!< MATCHINT (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_PATTERN_IRQ_STAT_ACK_ERROR_INT_Pos (16UL) /*!< ERROR_INT (Bit 16) */ + #define R_ETHSW_PATTERN_IRQ_STAT_ACK_ERROR_INT_Msk (0xf0000UL) /*!< ERROR_INT (Bitfield-Mask: 0x0f) */ +/* ====================================================== PTRN_VLANID ====================================================== */ + #define R_ETHSW_PTRN_VLANID_PTRN_VLANID_Pos (0UL) /*!< PTRN_VLANID (Bit 0) */ + #define R_ETHSW_PTRN_VLANID_PTRN_VLANID_Msk (0xffffUL) /*!< PTRN_VLANID (Bitfield-Mask: 0xffff) */ +/* ====================================================== PATTERN_SEL ====================================================== */ + #define R_ETHSW_PATTERN_SEL_PATTERN_SEL_Pos (0UL) /*!< PATTERN_SEL (Bit 0) */ + #define R_ETHSW_PATTERN_SEL_PATTERN_SEL_Msk (0xfUL) /*!< PATTERN_SEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== PTRN_CMP_30 ====================================================== */ + #define R_ETHSW_PTRN_CMP_30_PTRN_CMP_30_Pos (0UL) /*!< PTRN_CMP_30 (Bit 0) */ + #define R_ETHSW_PTRN_CMP_30_PTRN_CMP_30_Msk (0xffffffffUL) /*!< PTRN_CMP_30 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTRN_CMP_74 ====================================================== */ + #define R_ETHSW_PTRN_CMP_74_PTRN_CMP_74_Pos (0UL) /*!< PTRN_CMP_74 (Bit 0) */ + #define R_ETHSW_PTRN_CMP_74_PTRN_CMP_74_Msk (0xffffffffUL) /*!< PTRN_CMP_74 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PTRN_CMP_118 ====================================================== */ + #define R_ETHSW_PTRN_CMP_118_PTRN_CMP_118_Pos (0UL) /*!< PTRN_CMP_118 (Bit 0) */ + #define R_ETHSW_PTRN_CMP_118_PTRN_CMP_118_Msk (0xffffffffUL) /*!< PTRN_CMP_118 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTRN_MSK_30 ====================================================== */ + #define R_ETHSW_PTRN_MSK_30_PTRN_MSK_30_Pos (0UL) /*!< PTRN_MSK_30 (Bit 0) */ + #define R_ETHSW_PTRN_MSK_30_PTRN_MSK_30_Msk (0xffffffffUL) /*!< PTRN_MSK_30 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTRN_MSK_74 ====================================================== */ + #define R_ETHSW_PTRN_MSK_74_PTRN_MSK_74_Pos (0UL) /*!< PTRN_MSK_74 (Bit 0) */ + #define R_ETHSW_PTRN_MSK_74_PTRN_MSK_74_Msk (0xffffffffUL) /*!< PTRN_MSK_74 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PTRN_MSK_118 ====================================================== */ + #define R_ETHSW_PTRN_MSK_118_PTRN_MSK_118_Pos (0UL) /*!< PTRN_MSK_118 (Bit 0) */ + #define R_ETHSW_PTRN_MSK_118_PTRN_MSK_118_Msk (0xffffffffUL) /*!< PTRN_MSK_118 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ESC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TYPE ========================================================== */ + #define R_ESC_TYPE_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ + #define R_ESC_TYPE_TYPE_Msk (0xffUL) /*!< TYPE (Bitfield-Mask: 0xff) */ +/* ======================================================= REVISION ======================================================== */ + #define R_ESC_REVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_ESC_REVISION_REV_Msk (0xffUL) /*!< REV (Bitfield-Mask: 0xff) */ +/* ========================================================= BUILD ========================================================= */ + #define R_ESC_BUILD_BUILD_Pos (0UL) /*!< BUILD (Bit 0) */ + #define R_ESC_BUILD_BUILD_Msk (0xffUL) /*!< BUILD (Bitfield-Mask: 0xff) */ +/* ======================================================= FMMU_NUM ======================================================== */ + #define R_ESC_FMMU_NUM_NUMFMMU_Pos (0UL) /*!< NUMFMMU (Bit 0) */ + #define R_ESC_FMMU_NUM_NUMFMMU_Msk (0xffUL) /*!< NUMFMMU (Bitfield-Mask: 0xff) */ +/* ===================================================== SYNC_MANAGER ====================================================== */ + #define R_ESC_SYNC_MANAGER_NUMSYNC_Pos (0UL) /*!< NUMSYNC (Bit 0) */ + #define R_ESC_SYNC_MANAGER_NUMSYNC_Msk (0xffUL) /*!< NUMSYNC (Bitfield-Mask: 0xff) */ +/* ======================================================= RAM_SIZE ======================================================== */ + #define R_ESC_RAM_SIZE_RAMSIZE_Pos (0UL) /*!< RAMSIZE (Bit 0) */ + #define R_ESC_RAM_SIZE_RAMSIZE_Msk (0xffUL) /*!< RAMSIZE (Bitfield-Mask: 0xff) */ +/* ======================================================= PORT_DESC ======================================================= */ + #define R_ESC_PORT_DESC_P0_Pos (0UL) /*!< P0 (Bit 0) */ + #define R_ESC_PORT_DESC_P0_Msk (0x3UL) /*!< P0 (Bitfield-Mask: 0x03) */ + #define R_ESC_PORT_DESC_P1_Pos (2UL) /*!< P1 (Bit 2) */ + #define R_ESC_PORT_DESC_P1_Msk (0xcUL) /*!< P1 (Bitfield-Mask: 0x03) */ + #define R_ESC_PORT_DESC_P2_Pos (4UL) /*!< P2 (Bit 4) */ + #define R_ESC_PORT_DESC_P2_Msk (0x30UL) /*!< P2 (Bitfield-Mask: 0x03) */ + #define R_ESC_PORT_DESC_P3_Pos (6UL) /*!< P3 (Bit 6) */ + #define R_ESC_PORT_DESC_P3_Msk (0xc0UL) /*!< P3 (Bitfield-Mask: 0x03) */ +/* ======================================================== FEATURE ======================================================== */ + #define R_ESC_FEATURE_FMMU_Pos (0UL) /*!< FMMU (Bit 0) */ + #define R_ESC_FEATURE_FMMU_Msk (0x1UL) /*!< FMMU (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_DC_Pos (2UL) /*!< DC (Bit 2) */ + #define R_ESC_FEATURE_DC_Msk (0x4UL) /*!< DC (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_DCWID_Pos (3UL) /*!< DCWID (Bit 3) */ + #define R_ESC_FEATURE_DCWID_Msk (0x8UL) /*!< DCWID (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_LINKDECMII_Pos (6UL) /*!< LINKDECMII (Bit 6) */ + #define R_ESC_FEATURE_LINKDECMII_Msk (0x40UL) /*!< LINKDECMII (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_FCS_Pos (7UL) /*!< FCS (Bit 7) */ + #define R_ESC_FEATURE_FCS_Msk (0x80UL) /*!< FCS (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_DCSYNC_Pos (8UL) /*!< DCSYNC (Bit 8) */ + #define R_ESC_FEATURE_DCSYNC_Msk (0x100UL) /*!< DCSYNC (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_LRW_Pos (9UL) /*!< LRW (Bit 9) */ + #define R_ESC_FEATURE_LRW_Msk (0x200UL) /*!< LRW (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_RWSUPP_Pos (10UL) /*!< RWSUPP (Bit 10) */ + #define R_ESC_FEATURE_RWSUPP_Msk (0x400UL) /*!< RWSUPP (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_FSCONFIG_Pos (11UL) /*!< FSCONFIG (Bit 11) */ + #define R_ESC_FEATURE_FSCONFIG_Msk (0x800UL) /*!< FSCONFIG (Bitfield-Mask: 0x01) */ +/* ====================================================== STATION_ADR ====================================================== */ + #define R_ESC_STATION_ADR_NODADDR_Pos (0UL) /*!< NODADDR (Bit 0) */ + #define R_ESC_STATION_ADR_NODADDR_Msk (0xffffUL) /*!< NODADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== STATION_ALIAS ===================================================== */ + #define R_ESC_STATION_ALIAS_NODALIADDR_Pos (0UL) /*!< NODALIADDR (Bit 0) */ + #define R_ESC_STATION_ALIAS_NODALIADDR_Msk (0xffffUL) /*!< NODALIADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== WR_REG_ENABLE ===================================================== */ + #define R_ESC_WR_REG_ENABLE_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_ESC_WR_REG_ENABLE_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ==================================================== WR_REG_PROTECT ===================================================== */ + #define R_ESC_WR_REG_PROTECT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_ESC_WR_REG_PROTECT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ===================================================== ESC_WR_ENABLE ===================================================== */ + #define R_ESC_ESC_WR_ENABLE_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_ESC_ESC_WR_ENABLE_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ==================================================== ESC_WR_PROTECT ===================================================== */ + #define R_ESC_ESC_WR_PROTECT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_ESC_ESC_WR_PROTECT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* =================================================== ESC_RESET_ECAT_R ==================================================== */ + #define R_ESC_ESC_RESET_ECAT_R_RESET_ECAT_Pos (0UL) /*!< RESET_ECAT (Bit 0) */ + #define R_ESC_ESC_RESET_ECAT_R_RESET_ECAT_Msk (0x3UL) /*!< RESET_ECAT (Bitfield-Mask: 0x03) */ +/* =================================================== ESC_RESET_ECAT_W ==================================================== */ + #define R_ESC_ESC_RESET_ECAT_W_RESET_ECAT_Pos (0UL) /*!< RESET_ECAT (Bit 0) */ + #define R_ESC_ESC_RESET_ECAT_W_RESET_ECAT_Msk (0xffUL) /*!< RESET_ECAT (Bitfield-Mask: 0xff) */ +/* ==================================================== ESC_RESET_PDI_R ==================================================== */ + #define R_ESC_ESC_RESET_PDI_R_RESET_PDI_Pos (0UL) /*!< RESET_PDI (Bit 0) */ + #define R_ESC_ESC_RESET_PDI_R_RESET_PDI_Msk (0x3UL) /*!< RESET_PDI (Bitfield-Mask: 0x03) */ +/* ==================================================== ESC_RESET_PDI_W ==================================================== */ + #define R_ESC_ESC_RESET_PDI_W_RESET_PDI_Pos (0UL) /*!< RESET_PDI (Bit 0) */ + #define R_ESC_ESC_RESET_PDI_W_RESET_PDI_Msk (0xffUL) /*!< RESET_PDI (Bitfield-Mask: 0xff) */ +/* ==================================================== ESC_DL_CONTROL ===================================================== */ + #define R_ESC_ESC_DL_CONTROL_FWDRULE_Pos (0UL) /*!< FWDRULE (Bit 0) */ + #define R_ESC_ESC_DL_CONTROL_FWDRULE_Msk (0x1UL) /*!< FWDRULE (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_CONTROL_TEMPUSE_Pos (1UL) /*!< TEMPUSE (Bit 1) */ + #define R_ESC_ESC_DL_CONTROL_TEMPUSE_Msk (0x2UL) /*!< TEMPUSE (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_CONTROL_LP0_Pos (8UL) /*!< LP0 (Bit 8) */ + #define R_ESC_ESC_DL_CONTROL_LP0_Msk (0x300UL) /*!< LP0 (Bitfield-Mask: 0x03) */ + #define R_ESC_ESC_DL_CONTROL_LP1_Pos (10UL) /*!< LP1 (Bit 10) */ + #define R_ESC_ESC_DL_CONTROL_LP1_Msk (0xc00UL) /*!< LP1 (Bitfield-Mask: 0x03) */ + #define R_ESC_ESC_DL_CONTROL_LP2_Pos (12UL) /*!< LP2 (Bit 12) */ + #define R_ESC_ESC_DL_CONTROL_LP2_Msk (0x3000UL) /*!< LP2 (Bitfield-Mask: 0x03) */ + #define R_ESC_ESC_DL_CONTROL_LP3_Pos (14UL) /*!< LP3 (Bit 14) */ + #define R_ESC_ESC_DL_CONTROL_LP3_Msk (0xc000UL) /*!< LP3 (Bitfield-Mask: 0x03) */ + #define R_ESC_ESC_DL_CONTROL_RXFIFO_Pos (16UL) /*!< RXFIFO (Bit 16) */ + #define R_ESC_ESC_DL_CONTROL_RXFIFO_Msk (0x70000UL) /*!< RXFIFO (Bitfield-Mask: 0x07) */ + #define R_ESC_ESC_DL_CONTROL_STAALIAS_Pos (24UL) /*!< STAALIAS (Bit 24) */ + #define R_ESC_ESC_DL_CONTROL_STAALIAS_Msk (0x1000000UL) /*!< STAALIAS (Bitfield-Mask: 0x01) */ +/* ================================================== PHYSICAL_RW_OFFSET =================================================== */ + #define R_ESC_PHYSICAL_RW_OFFSET_RWOFFSET_Pos (0UL) /*!< RWOFFSET (Bit 0) */ + #define R_ESC_PHYSICAL_RW_OFFSET_RWOFFSET_Msk (0xffffUL) /*!< RWOFFSET (Bitfield-Mask: 0xffff) */ +/* ===================================================== ESC_DL_STATUS ===================================================== */ + #define R_ESC_ESC_DL_STATUS_PDIOPE_Pos (0UL) /*!< PDIOPE (Bit 0) */ + #define R_ESC_ESC_DL_STATUS_PDIOPE_Msk (0x1UL) /*!< PDIOPE (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_PDIWDST_Pos (1UL) /*!< PDIWDST (Bit 1) */ + #define R_ESC_ESC_DL_STATUS_PDIWDST_Msk (0x2UL) /*!< PDIWDST (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_ENHLINKD_Pos (2UL) /*!< ENHLINKD (Bit 2) */ + #define R_ESC_ESC_DL_STATUS_ENHLINKD_Msk (0x4UL) /*!< ENHLINKD (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_PHYP0_Pos (4UL) /*!< PHYP0 (Bit 4) */ + #define R_ESC_ESC_DL_STATUS_PHYP0_Msk (0x10UL) /*!< PHYP0 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_PHYP1_Pos (5UL) /*!< PHYP1 (Bit 5) */ + #define R_ESC_ESC_DL_STATUS_PHYP1_Msk (0x20UL) /*!< PHYP1 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_PHYP2_Pos (6UL) /*!< PHYP2 (Bit 6) */ + #define R_ESC_ESC_DL_STATUS_PHYP2_Msk (0x40UL) /*!< PHYP2 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_PHYP3_Pos (7UL) /*!< PHYP3 (Bit 7) */ + #define R_ESC_ESC_DL_STATUS_PHYP3_Msk (0x80UL) /*!< PHYP3 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_LP0_Pos (8UL) /*!< LP0 (Bit 8) */ + #define R_ESC_ESC_DL_STATUS_LP0_Msk (0x100UL) /*!< LP0 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_COMP0_Pos (9UL) /*!< COMP0 (Bit 9) */ + #define R_ESC_ESC_DL_STATUS_COMP0_Msk (0x200UL) /*!< COMP0 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_LP1_Pos (10UL) /*!< LP1 (Bit 10) */ + #define R_ESC_ESC_DL_STATUS_LP1_Msk (0x400UL) /*!< LP1 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_COMP1_Pos (11UL) /*!< COMP1 (Bit 11) */ + #define R_ESC_ESC_DL_STATUS_COMP1_Msk (0x800UL) /*!< COMP1 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_LP2_Pos (12UL) /*!< LP2 (Bit 12) */ + #define R_ESC_ESC_DL_STATUS_LP2_Msk (0x1000UL) /*!< LP2 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_COMP2_Pos (13UL) /*!< COMP2 (Bit 13) */ + #define R_ESC_ESC_DL_STATUS_COMP2_Msk (0x2000UL) /*!< COMP2 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_LP3_Pos (14UL) /*!< LP3 (Bit 14) */ + #define R_ESC_ESC_DL_STATUS_LP3_Msk (0x4000UL) /*!< LP3 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_COMP3_Pos (15UL) /*!< COMP3 (Bit 15) */ + #define R_ESC_ESC_DL_STATUS_COMP3_Msk (0x8000UL) /*!< COMP3 (Bitfield-Mask: 0x01) */ +/* ====================================================== AL_CONTROL ======================================================= */ + #define R_ESC_AL_CONTROL_INISTATE_Pos (0UL) /*!< INISTATE (Bit 0) */ + #define R_ESC_AL_CONTROL_INISTATE_Msk (0xfUL) /*!< INISTATE (Bitfield-Mask: 0x0f) */ + #define R_ESC_AL_CONTROL_ERRINDACK_Pos (4UL) /*!< ERRINDACK (Bit 4) */ + #define R_ESC_AL_CONTROL_ERRINDACK_Msk (0x10UL) /*!< ERRINDACK (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_CONTROL_DEVICEID_Pos (5UL) /*!< DEVICEID (Bit 5) */ + #define R_ESC_AL_CONTROL_DEVICEID_Msk (0x20UL) /*!< DEVICEID (Bitfield-Mask: 0x01) */ +/* ======================================================= AL_STATUS ======================================================= */ + #define R_ESC_AL_STATUS_ACTSTATE_Pos (0UL) /*!< ACTSTATE (Bit 0) */ + #define R_ESC_AL_STATUS_ACTSTATE_Msk (0xfUL) /*!< ACTSTATE (Bitfield-Mask: 0x0f) */ + #define R_ESC_AL_STATUS_ERR_Pos (4UL) /*!< ERR (Bit 4) */ + #define R_ESC_AL_STATUS_ERR_Msk (0x10UL) /*!< ERR (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_STATUS_DEVICEID_Pos (5UL) /*!< DEVICEID (Bit 5) */ + #define R_ESC_AL_STATUS_DEVICEID_Msk (0x20UL) /*!< DEVICEID (Bitfield-Mask: 0x01) */ +/* ==================================================== AL_STATUS_CODE ===================================================== */ + #define R_ESC_AL_STATUS_CODE_STATUSCODE_Pos (0UL) /*!< STATUSCODE (Bit 0) */ + #define R_ESC_AL_STATUS_CODE_STATUSCODE_Msk (0xffffUL) /*!< STATUSCODE (Bitfield-Mask: 0xffff) */ +/* =================================================== RUN_LED_OVERRIDE ==================================================== */ + #define R_ESC_RUN_LED_OVERRIDE_LEDCODE_Pos (0UL) /*!< LEDCODE (Bit 0) */ + #define R_ESC_RUN_LED_OVERRIDE_LEDCODE_Msk (0xfUL) /*!< LEDCODE (Bitfield-Mask: 0x0f) */ + #define R_ESC_RUN_LED_OVERRIDE_OVERRIDEEN_Pos (4UL) /*!< OVERRIDEEN (Bit 4) */ + #define R_ESC_RUN_LED_OVERRIDE_OVERRIDEEN_Msk (0x10UL) /*!< OVERRIDEEN (Bitfield-Mask: 0x01) */ +/* =================================================== ERR_LED_OVERRIDE ==================================================== */ + #define R_ESC_ERR_LED_OVERRIDE_LEDCODE_Pos (0UL) /*!< LEDCODE (Bit 0) */ + #define R_ESC_ERR_LED_OVERRIDE_LEDCODE_Msk (0xfUL) /*!< LEDCODE (Bitfield-Mask: 0x0f) */ + #define R_ESC_ERR_LED_OVERRIDE_OVERRIDEEN_Pos (4UL) /*!< OVERRIDEEN (Bit 4) */ + #define R_ESC_ERR_LED_OVERRIDE_OVERRIDEEN_Msk (0x10UL) /*!< OVERRIDEEN (Bitfield-Mask: 0x01) */ +/* ====================================================== PDI_CONTROL ====================================================== */ + #define R_ESC_PDI_CONTROL_PDI_Pos (0UL) /*!< PDI (Bit 0) */ + #define R_ESC_PDI_CONTROL_PDI_Msk (0xffUL) /*!< PDI (Bitfield-Mask: 0xff) */ +/* ====================================================== ESC_CONFIG ======================================================= */ + #define R_ESC_ESC_CONFIG_DEVEMU_Pos (0UL) /*!< DEVEMU (Bit 0) */ + #define R_ESC_ESC_CONFIG_DEVEMU_Msk (0x1UL) /*!< DEVEMU (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_ENLALLP_Pos (1UL) /*!< ENLALLP (Bit 1) */ + #define R_ESC_ESC_CONFIG_ENLALLP_Msk (0x2UL) /*!< ENLALLP (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_DCSYNC_Pos (2UL) /*!< DCSYNC (Bit 2) */ + #define R_ESC_ESC_CONFIG_DCSYNC_Msk (0x4UL) /*!< DCSYNC (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_DCLATCH_Pos (3UL) /*!< DCLATCH (Bit 3) */ + #define R_ESC_ESC_CONFIG_DCLATCH_Msk (0x8UL) /*!< DCLATCH (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_ENLP0_Pos (4UL) /*!< ENLP0 (Bit 4) */ + #define R_ESC_ESC_CONFIG_ENLP0_Msk (0x10UL) /*!< ENLP0 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_ENLP1_Pos (5UL) /*!< ENLP1 (Bit 5) */ + #define R_ESC_ESC_CONFIG_ENLP1_Msk (0x20UL) /*!< ENLP1 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_ENLP2_Pos (6UL) /*!< ENLP2 (Bit 6) */ + #define R_ESC_ESC_CONFIG_ENLP2_Msk (0x40UL) /*!< ENLP2 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_ENLP3_Pos (7UL) /*!< ENLP3 (Bit 7) */ + #define R_ESC_ESC_CONFIG_ENLP3_Msk (0x80UL) /*!< ENLP3 (Bitfield-Mask: 0x01) */ +/* ====================================================== PDI_CONFIG ======================================================= */ + #define R_ESC_PDI_CONFIG_ONCHIPBUSCLK_Pos (0UL) /*!< ONCHIPBUSCLK (Bit 0) */ + #define R_ESC_PDI_CONFIG_ONCHIPBUSCLK_Msk (0x1fUL) /*!< ONCHIPBUSCLK (Bitfield-Mask: 0x1f) */ + #define R_ESC_PDI_CONFIG_ONCHIPBUS_Pos (5UL) /*!< ONCHIPBUS (Bit 5) */ + #define R_ESC_PDI_CONFIG_ONCHIPBUS_Msk (0xe0UL) /*!< ONCHIPBUS (Bitfield-Mask: 0x07) */ +/* =================================================== SYNC_LATCH_CONFIG =================================================== */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC0OUT_Pos (0UL) /*!< SYNC0OUT (Bit 0) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC0OUT_Msk (0x3UL) /*!< SYNC0OUT (Bitfield-Mask: 0x03) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT0_Pos (2UL) /*!< SYNCLAT0 (Bit 2) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT0_Msk (0x4UL) /*!< SYNCLAT0 (Bitfield-Mask: 0x01) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC0MAP_Pos (3UL) /*!< SYNC0MAP (Bit 3) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC0MAP_Msk (0x8UL) /*!< SYNC0MAP (Bitfield-Mask: 0x01) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC1OUT_Pos (4UL) /*!< SYNC1OUT (Bit 4) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC1OUT_Msk (0x30UL) /*!< SYNC1OUT (Bitfield-Mask: 0x03) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT1_Pos (6UL) /*!< SYNCLAT1 (Bit 6) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT1_Msk (0x40UL) /*!< SYNCLAT1 (Bitfield-Mask: 0x01) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC1MAP_Pos (7UL) /*!< SYNC1MAP (Bit 7) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC1MAP_Msk (0x80UL) /*!< SYNC1MAP (Bitfield-Mask: 0x01) */ +/* ==================================================== EXT_PDI_CONFIG ===================================================== */ + #define R_ESC_EXT_PDI_CONFIG_DATABUSWID_Pos (0UL) /*!< DATABUSWID (Bit 0) */ + #define R_ESC_EXT_PDI_CONFIG_DATABUSWID_Msk (0x3UL) /*!< DATABUSWID (Bitfield-Mask: 0x03) */ +/* ==================================================== ECAT_EVENT_MASK ==================================================== */ + #define R_ESC_ECAT_EVENT_MASK_ECATEVMASK_Pos (0UL) /*!< ECATEVMASK (Bit 0) */ + #define R_ESC_ECAT_EVENT_MASK_ECATEVMASK_Msk (0xffffUL) /*!< ECATEVMASK (Bitfield-Mask: 0xffff) */ +/* ===================================================== AL_EVENT_MASK ===================================================== */ + #define R_ESC_AL_EVENT_MASK_ALEVMASK_Pos (0UL) /*!< ALEVMASK (Bit 0) */ + #define R_ESC_AL_EVENT_MASK_ALEVMASK_Msk (0xffffffffUL) /*!< ALEVMASK (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== ECAT_EVENT_REQ ===================================================== */ + #define R_ESC_ECAT_EVENT_REQ_DCLATCH_Pos (0UL) /*!< DCLATCH (Bit 0) */ + #define R_ESC_ECAT_EVENT_REQ_DCLATCH_Msk (0x1UL) /*!< DCLATCH (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_DLSTA_Pos (2UL) /*!< DLSTA (Bit 2) */ + #define R_ESC_ECAT_EVENT_REQ_DLSTA_Msk (0x4UL) /*!< DLSTA (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_ALSTA_Pos (3UL) /*!< ALSTA (Bit 3) */ + #define R_ESC_ECAT_EVENT_REQ_ALSTA_Msk (0x8UL) /*!< ALSTA (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA0_Pos (4UL) /*!< SMSTA0 (Bit 4) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA0_Msk (0x10UL) /*!< SMSTA0 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA1_Pos (5UL) /*!< SMSTA1 (Bit 5) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA1_Msk (0x20UL) /*!< SMSTA1 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA2_Pos (6UL) /*!< SMSTA2 (Bit 6) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA2_Msk (0x40UL) /*!< SMSTA2 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA3_Pos (7UL) /*!< SMSTA3 (Bit 7) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA3_Msk (0x80UL) /*!< SMSTA3 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA4_Pos (8UL) /*!< SMSTA4 (Bit 8) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA4_Msk (0x100UL) /*!< SMSTA4 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA5_Pos (9UL) /*!< SMSTA5 (Bit 9) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA5_Msk (0x200UL) /*!< SMSTA5 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA6_Pos (10UL) /*!< SMSTA6 (Bit 10) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA6_Msk (0x400UL) /*!< SMSTA6 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA7_Pos (11UL) /*!< SMSTA7 (Bit 11) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA7_Msk (0x800UL) /*!< SMSTA7 (Bitfield-Mask: 0x01) */ +/* ===================================================== AL_EVENT_REQ ====================================================== */ + #define R_ESC_AL_EVENT_REQ_ALCTRL_Pos (0UL) /*!< ALCTRL (Bit 0) */ + #define R_ESC_AL_EVENT_REQ_ALCTRL_Msk (0x1UL) /*!< ALCTRL (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_DCLATCH_Pos (1UL) /*!< DCLATCH (Bit 1) */ + #define R_ESC_AL_EVENT_REQ_DCLATCH_Msk (0x2UL) /*!< DCLATCH (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_DCSYNC0STA_Pos (2UL) /*!< DCSYNC0STA (Bit 2) */ + #define R_ESC_AL_EVENT_REQ_DCSYNC0STA_Msk (0x4UL) /*!< DCSYNC0STA (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_DCSYNC1STA_Pos (3UL) /*!< DCSYNC1STA (Bit 3) */ + #define R_ESC_AL_EVENT_REQ_DCSYNC1STA_Msk (0x8UL) /*!< DCSYNC1STA (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SYNCACT_Pos (4UL) /*!< SYNCACT (Bit 4) */ + #define R_ESC_AL_EVENT_REQ_SYNCACT_Msk (0x10UL) /*!< SYNCACT (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_WDPD_Pos (6UL) /*!< WDPD (Bit 6) */ + #define R_ESC_AL_EVENT_REQ_WDPD_Msk (0x40UL) /*!< WDPD (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT0_Pos (8UL) /*!< SMINT0 (Bit 8) */ + #define R_ESC_AL_EVENT_REQ_SMINT0_Msk (0x100UL) /*!< SMINT0 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT1_Pos (9UL) /*!< SMINT1 (Bit 9) */ + #define R_ESC_AL_EVENT_REQ_SMINT1_Msk (0x200UL) /*!< SMINT1 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT2_Pos (10UL) /*!< SMINT2 (Bit 10) */ + #define R_ESC_AL_EVENT_REQ_SMINT2_Msk (0x400UL) /*!< SMINT2 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT3_Pos (11UL) /*!< SMINT3 (Bit 11) */ + #define R_ESC_AL_EVENT_REQ_SMINT3_Msk (0x800UL) /*!< SMINT3 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT4_Pos (12UL) /*!< SMINT4 (Bit 12) */ + #define R_ESC_AL_EVENT_REQ_SMINT4_Msk (0x1000UL) /*!< SMINT4 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT5_Pos (13UL) /*!< SMINT5 (Bit 13) */ + #define R_ESC_AL_EVENT_REQ_SMINT5_Msk (0x2000UL) /*!< SMINT5 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT6_Pos (14UL) /*!< SMINT6 (Bit 14) */ + #define R_ESC_AL_EVENT_REQ_SMINT6_Msk (0x4000UL) /*!< SMINT6 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT7_Pos (15UL) /*!< SMINT7 (Bit 15) */ + #define R_ESC_AL_EVENT_REQ_SMINT7_Msk (0x8000UL) /*!< SMINT7 (Bitfield-Mask: 0x01) */ +/* ===================================================== RX_ERR_COUNT ====================================================== */ + #define R_ESC_RX_ERR_COUNT_INVFRMCNT_Pos (0UL) /*!< INVFRMCNT (Bit 0) */ + #define R_ESC_RX_ERR_COUNT_INVFRMCNT_Msk (0xffUL) /*!< INVFRMCNT (Bitfield-Mask: 0xff) */ + #define R_ESC_RX_ERR_COUNT_RXERRCNT_Pos (8UL) /*!< RXERRCNT (Bit 8) */ + #define R_ESC_RX_ERR_COUNT_RXERRCNT_Msk (0xff00UL) /*!< RXERRCNT (Bitfield-Mask: 0xff) */ +/* =================================================== FWD_RX_ERR_COUNT ==================================================== */ + #define R_ESC_FWD_RX_ERR_COUNT_FWDERRCNT_Pos (0UL) /*!< FWDERRCNT (Bit 0) */ + #define R_ESC_FWD_RX_ERR_COUNT_FWDERRCNT_Msk (0xffUL) /*!< FWDERRCNT (Bitfield-Mask: 0xff) */ +/* ================================================== ECAT_PROC_ERR_COUNT ================================================== */ + #define R_ESC_ECAT_PROC_ERR_COUNT_EPUERRCNT_Pos (0UL) /*!< EPUERRCNT (Bit 0) */ + #define R_ESC_ECAT_PROC_ERR_COUNT_EPUERRCNT_Msk (0xffUL) /*!< EPUERRCNT (Bitfield-Mask: 0xff) */ +/* ===================================================== PDI_ERR_COUNT ===================================================== */ + #define R_ESC_PDI_ERR_COUNT_PDIERRCNT_Pos (0UL) /*!< PDIERRCNT (Bit 0) */ + #define R_ESC_PDI_ERR_COUNT_PDIERRCNT_Msk (0xffUL) /*!< PDIERRCNT (Bitfield-Mask: 0xff) */ +/* ==================================================== LOST_LINK_COUNT ==================================================== */ + #define R_ESC_LOST_LINK_COUNT_LOSTLINKCNT_Pos (0UL) /*!< LOSTLINKCNT (Bit 0) */ + #define R_ESC_LOST_LINK_COUNT_LOSTLINKCNT_Msk (0xffUL) /*!< LOSTLINKCNT (Bitfield-Mask: 0xff) */ +/* ======================================================= WD_DIVIDE ======================================================= */ + #define R_ESC_WD_DIVIDE_WDDIV_Pos (0UL) /*!< WDDIV (Bit 0) */ + #define R_ESC_WD_DIVIDE_WDDIV_Msk (0xffffUL) /*!< WDDIV (Bitfield-Mask: 0xffff) */ +/* ======================================================== WDT_PDI ======================================================== */ + #define R_ESC_WDT_PDI_WDTIMPDI_Pos (0UL) /*!< WDTIMPDI (Bit 0) */ + #define R_ESC_WDT_PDI_WDTIMPDI_Msk (0xffffUL) /*!< WDTIMPDI (Bitfield-Mask: 0xffff) */ +/* ======================================================= WDT_DATA ======================================================== */ + #define R_ESC_WDT_DATA_WDTIMPD_Pos (0UL) /*!< WDTIMPD (Bit 0) */ + #define R_ESC_WDT_DATA_WDTIMPD_Msk (0xffffUL) /*!< WDTIMPD (Bitfield-Mask: 0xffff) */ +/* ======================================================= WDS_DATA ======================================================== */ + #define R_ESC_WDS_DATA_WDSTAPD_Pos (0UL) /*!< WDSTAPD (Bit 0) */ + #define R_ESC_WDS_DATA_WDSTAPD_Msk (0x1UL) /*!< WDSTAPD (Bitfield-Mask: 0x01) */ +/* ======================================================= WDC_DATA ======================================================== */ + #define R_ESC_WDC_DATA_WDCNTPD_Pos (0UL) /*!< WDCNTPD (Bit 0) */ + #define R_ESC_WDC_DATA_WDCNTPD_Msk (0xffUL) /*!< WDCNTPD (Bitfield-Mask: 0xff) */ +/* ======================================================== WDC_PDI ======================================================== */ + #define R_ESC_WDC_PDI_WDCNTPDI_Pos (0UL) /*!< WDCNTPDI (Bit 0) */ + #define R_ESC_WDC_PDI_WDCNTPDI_Msk (0xffUL) /*!< WDCNTPDI (Bitfield-Mask: 0xff) */ +/* ======================================================= EEP_CONF ======================================================== */ + #define R_ESC_EEP_CONF_CTRLPDI_Pos (0UL) /*!< CTRLPDI (Bit 0) */ + #define R_ESC_EEP_CONF_CTRLPDI_Msk (0x1UL) /*!< CTRLPDI (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONF_FORCEECAT_Pos (1UL) /*!< FORCEECAT (Bit 1) */ + #define R_ESC_EEP_CONF_FORCEECAT_Msk (0x2UL) /*!< FORCEECAT (Bitfield-Mask: 0x01) */ +/* ======================================================= EEP_STATE ======================================================= */ + #define R_ESC_EEP_STATE_PDIACCESS_Pos (0UL) /*!< PDIACCESS (Bit 0) */ + #define R_ESC_EEP_STATE_PDIACCESS_Msk (0x1UL) /*!< PDIACCESS (Bitfield-Mask: 0x01) */ +/* ===================================================== EEP_CONT_STAT ===================================================== */ + #define R_ESC_EEP_CONT_STAT_ECATWREN_Pos (0UL) /*!< ECATWREN (Bit 0) */ + #define R_ESC_EEP_CONT_STAT_ECATWREN_Msk (0x1UL) /*!< ECATWREN (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_READBYTE_Pos (6UL) /*!< READBYTE (Bit 6) */ + #define R_ESC_EEP_CONT_STAT_READBYTE_Msk (0x40UL) /*!< READBYTE (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_PROMSIZE_Pos (7UL) /*!< PROMSIZE (Bit 7) */ + #define R_ESC_EEP_CONT_STAT_PROMSIZE_Msk (0x80UL) /*!< PROMSIZE (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_COMMAND_Pos (8UL) /*!< COMMAND (Bit 8) */ + #define R_ESC_EEP_CONT_STAT_COMMAND_Msk (0x700UL) /*!< COMMAND (Bitfield-Mask: 0x07) */ + #define R_ESC_EEP_CONT_STAT_CKSUMERR_Pos (11UL) /*!< CKSUMERR (Bit 11) */ + #define R_ESC_EEP_CONT_STAT_CKSUMERR_Msk (0x800UL) /*!< CKSUMERR (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_LOADSTA_Pos (12UL) /*!< LOADSTA (Bit 12) */ + #define R_ESC_EEP_CONT_STAT_LOADSTA_Msk (0x1000UL) /*!< LOADSTA (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_ACKCMDERR_Pos (13UL) /*!< ACKCMDERR (Bit 13) */ + #define R_ESC_EEP_CONT_STAT_ACKCMDERR_Msk (0x2000UL) /*!< ACKCMDERR (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_WRENERR_Pos (14UL) /*!< WRENERR (Bit 14) */ + #define R_ESC_EEP_CONT_STAT_WRENERR_Msk (0x4000UL) /*!< WRENERR (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_BUSY_Pos (15UL) /*!< BUSY (Bit 15) */ + #define R_ESC_EEP_CONT_STAT_BUSY_Msk (0x8000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== EEP_ADR ======================================================== */ + #define R_ESC_EEP_ADR_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ + #define R_ESC_EEP_ADR_ADDRESS_Msk (0xffffffffUL) /*!< ADDRESS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EEP_DATA ======================================================== */ + #define R_ESC_EEP_DATA_LODATA_Pos (0UL) /*!< LODATA (Bit 0) */ + #define R_ESC_EEP_DATA_LODATA_Msk (0xffffUL) /*!< LODATA (Bitfield-Mask: 0xffff) */ + #define R_ESC_EEP_DATA_HIDATA_Pos (16UL) /*!< HIDATA (Bit 16) */ + #define R_ESC_EEP_DATA_HIDATA_Msk (0xffff0000UL) /*!< HIDATA (Bitfield-Mask: 0xffff) */ +/* ===================================================== MII_CONT_STAT ===================================================== */ + #define R_ESC_MII_CONT_STAT_WREN_Pos (0UL) /*!< WREN (Bit 0) */ + #define R_ESC_MII_CONT_STAT_WREN_Msk (0x1UL) /*!< WREN (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_CONT_STAT_PDICTRL_Pos (1UL) /*!< PDICTRL (Bit 1) */ + #define R_ESC_MII_CONT_STAT_PDICTRL_Msk (0x2UL) /*!< PDICTRL (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_CONT_STAT_MILINK_Pos (2UL) /*!< MILINK (Bit 2) */ + #define R_ESC_MII_CONT_STAT_MILINK_Msk (0x4UL) /*!< MILINK (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_CONT_STAT_PHYOFFSET_Pos (3UL) /*!< PHYOFFSET (Bit 3) */ + #define R_ESC_MII_CONT_STAT_PHYOFFSET_Msk (0xf8UL) /*!< PHYOFFSET (Bitfield-Mask: 0x1f) */ + #define R_ESC_MII_CONT_STAT_COMMAND_Pos (8UL) /*!< COMMAND (Bit 8) */ + #define R_ESC_MII_CONT_STAT_COMMAND_Msk (0x300UL) /*!< COMMAND (Bitfield-Mask: 0x03) */ + #define R_ESC_MII_CONT_STAT_READERR_Pos (13UL) /*!< READERR (Bit 13) */ + #define R_ESC_MII_CONT_STAT_READERR_Msk (0x2000UL) /*!< READERR (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_CONT_STAT_CMDERR_Pos (14UL) /*!< CMDERR (Bit 14) */ + #define R_ESC_MII_CONT_STAT_CMDERR_Msk (0x4000UL) /*!< CMDERR (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_CONT_STAT_BUSY_Pos (15UL) /*!< BUSY (Bit 15) */ + #define R_ESC_MII_CONT_STAT_BUSY_Msk (0x8000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== PHY_ADR ======================================================== */ + #define R_ESC_PHY_ADR_PHYADDR_Pos (0UL) /*!< PHYADDR (Bit 0) */ + #define R_ESC_PHY_ADR_PHYADDR_Msk (0x1fUL) /*!< PHYADDR (Bitfield-Mask: 0x1f) */ +/* ====================================================== PHY_REG_ADR ====================================================== */ + #define R_ESC_PHY_REG_ADR_PHYREGADDR_Pos (0UL) /*!< PHYREGADDR (Bit 0) */ + #define R_ESC_PHY_REG_ADR_PHYREGADDR_Msk (0x1fUL) /*!< PHYREGADDR (Bitfield-Mask: 0x1f) */ +/* ======================================================= PHY_DATA ======================================================== */ + #define R_ESC_PHY_DATA_PHYREGDATA_Pos (0UL) /*!< PHYREGDATA (Bit 0) */ + #define R_ESC_PHY_DATA_PHYREGDATA_Msk (0xffffUL) /*!< PHYREGDATA (Bitfield-Mask: 0xffff) */ +/* =================================================== MII_ECAT_ACS_STAT =================================================== */ + #define R_ESC_MII_ECAT_ACS_STAT_ACSMII_Pos (0UL) /*!< ACSMII (Bit 0) */ + #define R_ESC_MII_ECAT_ACS_STAT_ACSMII_Msk (0x1UL) /*!< ACSMII (Bitfield-Mask: 0x01) */ +/* =================================================== MII_PDI_ACS_STAT ==================================================== */ + #define R_ESC_MII_PDI_ACS_STAT_ACSMII_Pos (0UL) /*!< ACSMII (Bit 0) */ + #define R_ESC_MII_PDI_ACS_STAT_ACSMII_Msk (0x1UL) /*!< ACSMII (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_PDI_ACS_STAT_FORPDI_Pos (1UL) /*!< FORPDI (Bit 1) */ + #define R_ESC_MII_PDI_ACS_STAT_FORPDI_Msk (0x2UL) /*!< FORPDI (Bitfield-Mask: 0x01) */ +/* =================================================== DC_RCV_TIME_PORT ==================================================== */ + #define R_ESC_DC_RCV_TIME_PORT_RCVTIME0_Pos (0UL) /*!< RCVTIME0 (Bit 0) */ + #define R_ESC_DC_RCV_TIME_PORT_RCVTIME0_Msk (0xffffffffUL) /*!< RCVTIME0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DC_SYS_TIME_L ===================================================== */ +/* ===================================================== DC_SYS_TIME_H ===================================================== */ +/* ================================================== DC_RCV_TIME_UNIT_L =================================================== */ +/* ================================================== DC_RCV_TIME_UNIT_H =================================================== */ +/* ================================================= DC_SYS_TIME_OFFSET_L ================================================== */ +/* ================================================= DC_SYS_TIME_OFFSET_H ================================================== */ +/* =================================================== DC_SYS_TIME_DELAY =================================================== */ + #define R_ESC_DC_SYS_TIME_DELAY_SYSTIMDLY_Pos (0UL) /*!< SYSTIMDLY (Bit 0) */ + #define R_ESC_DC_SYS_TIME_DELAY_SYSTIMDLY_Msk (0xffffffffUL) /*!< SYSTIMDLY (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DC_SYS_TIME_DIFF ==================================================== */ + #define R_ESC_DC_SYS_TIME_DIFF_DIFF_Pos (0UL) /*!< DIFF (Bit 0) */ + #define R_ESC_DC_SYS_TIME_DIFF_DIFF_Msk (0x7fffffffUL) /*!< DIFF (Bitfield-Mask: 0x7fffffff) */ + #define R_ESC_DC_SYS_TIME_DIFF_LCP_Pos (31UL) /*!< LCP (Bit 31) */ + #define R_ESC_DC_SYS_TIME_DIFF_LCP_Msk (0x80000000UL) /*!< LCP (Bitfield-Mask: 0x01) */ +/* ================================================= DC_SPEED_COUNT_START ================================================== */ + #define R_ESC_DC_SPEED_COUNT_START_SPDCNTSTRT_Pos (0UL) /*!< SPDCNTSTRT (Bit 0) */ + #define R_ESC_DC_SPEED_COUNT_START_SPDCNTSTRT_Msk (0x7fffUL) /*!< SPDCNTSTRT (Bitfield-Mask: 0x7fff) */ +/* ================================================== DC_SPEED_COUNT_DIFF ================================================== */ + #define R_ESC_DC_SPEED_COUNT_DIFF_SPDCNTDIFF_Pos (0UL) /*!< SPDCNTDIFF (Bit 0) */ + #define R_ESC_DC_SPEED_COUNT_DIFF_SPDCNTDIFF_Msk (0xffffUL) /*!< SPDCNTDIFF (Bitfield-Mask: 0xffff) */ +/* ============================================== DC_SYS_TIME_DIFF_FIL_DEPTH =============================================== */ + #define R_ESC_DC_SYS_TIME_DIFF_FIL_DEPTH_SYSTIMDEP_Pos (0UL) /*!< SYSTIMDEP (Bit 0) */ + #define R_ESC_DC_SYS_TIME_DIFF_FIL_DEPTH_SYSTIMDEP_Msk (0xfUL) /*!< SYSTIMDEP (Bitfield-Mask: 0x0f) */ +/* =============================================== DC_SPEED_COUNT_FIL_DEPTH ================================================ */ + #define R_ESC_DC_SPEED_COUNT_FIL_DEPTH_CLKPERDEP_Pos (0UL) /*!< CLKPERDEP (Bit 0) */ + #define R_ESC_DC_SPEED_COUNT_FIL_DEPTH_CLKPERDEP_Msk (0xfUL) /*!< CLKPERDEP (Bitfield-Mask: 0x0f) */ +/* ====================================================== DC_CYC_CONT ====================================================== */ + #define R_ESC_DC_CYC_CONT_SYNCOUT_Pos (0UL) /*!< SYNCOUT (Bit 0) */ + #define R_ESC_DC_CYC_CONT_SYNCOUT_Msk (0x1UL) /*!< SYNCOUT (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_CYC_CONT_LATCH0_Pos (4UL) /*!< LATCH0 (Bit 4) */ + #define R_ESC_DC_CYC_CONT_LATCH0_Msk (0x10UL) /*!< LATCH0 (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_CYC_CONT_LATCH1_Pos (5UL) /*!< LATCH1 (Bit 5) */ + #define R_ESC_DC_CYC_CONT_LATCH1_Msk (0x20UL) /*!< LATCH1 (Bitfield-Mask: 0x01) */ +/* ======================================================== DC_ACT ========================================================= */ + #define R_ESC_DC_ACT_SYNCACT_Pos (0UL) /*!< SYNCACT (Bit 0) */ + #define R_ESC_DC_ACT_SYNCACT_Msk (0x1UL) /*!< SYNCACT (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_SYNC0_Pos (1UL) /*!< SYNC0 (Bit 1) */ + #define R_ESC_DC_ACT_SYNC0_Msk (0x2UL) /*!< SYNC0 (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_SYNC1_Pos (2UL) /*!< SYNC1 (Bit 2) */ + #define R_ESC_DC_ACT_SYNC1_Msk (0x4UL) /*!< SYNC1 (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_AUTOACT_Pos (3UL) /*!< AUTOACT (Bit 3) */ + #define R_ESC_DC_ACT_AUTOACT_Msk (0x8UL) /*!< AUTOACT (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_EXTSTARTTIME_Pos (4UL) /*!< EXTSTARTTIME (Bit 4) */ + #define R_ESC_DC_ACT_EXTSTARTTIME_Msk (0x10UL) /*!< EXTSTARTTIME (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_STARTTIME_Pos (5UL) /*!< STARTTIME (Bit 5) */ + #define R_ESC_DC_ACT_STARTTIME_Msk (0x20UL) /*!< STARTTIME (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_NEARFUTURE_Pos (6UL) /*!< NEARFUTURE (Bit 6) */ + #define R_ESC_DC_ACT_NEARFUTURE_Msk (0x40UL) /*!< NEARFUTURE (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_DBGPULSE_Pos (7UL) /*!< DBGPULSE (Bit 7) */ + #define R_ESC_DC_ACT_DBGPULSE_Msk (0x80UL) /*!< DBGPULSE (Bitfield-Mask: 0x01) */ +/* ===================================================== DC_PULSE_LEN ====================================================== */ + #define R_ESC_DC_PULSE_LEN_PULSELEN_Pos (0UL) /*!< PULSELEN (Bit 0) */ + #define R_ESC_DC_PULSE_LEN_PULSELEN_Msk (0xffffUL) /*!< PULSELEN (Bitfield-Mask: 0xffff) */ +/* ====================================================== DC_ACT_STAT ====================================================== */ + #define R_ESC_DC_ACT_STAT_SYNC0ACT_Pos (0UL) /*!< SYNC0ACT (Bit 0) */ + #define R_ESC_DC_ACT_STAT_SYNC0ACT_Msk (0x1UL) /*!< SYNC0ACT (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_STAT_SYNC1ACT_Pos (1UL) /*!< SYNC1ACT (Bit 1) */ + #define R_ESC_DC_ACT_STAT_SYNC1ACT_Msk (0x2UL) /*!< SYNC1ACT (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_STAT_STARTTIME_Pos (2UL) /*!< STARTTIME (Bit 2) */ + #define R_ESC_DC_ACT_STAT_STARTTIME_Msk (0x4UL) /*!< STARTTIME (Bitfield-Mask: 0x01) */ +/* ===================================================== DC_SYNC0_STAT ===================================================== */ + #define R_ESC_DC_SYNC0_STAT_SYNC0STA_Pos (0UL) /*!< SYNC0STA (Bit 0) */ + #define R_ESC_DC_SYNC0_STAT_SYNC0STA_Msk (0x1UL) /*!< SYNC0STA (Bitfield-Mask: 0x01) */ +/* ===================================================== DC_SYNC1_STAT ===================================================== */ + #define R_ESC_DC_SYNC1_STAT_SYNC1STA_Pos (0UL) /*!< SYNC1STA (Bit 0) */ + #define R_ESC_DC_SYNC1_STAT_SYNC1STA_Msk (0x1UL) /*!< SYNC1STA (Bitfield-Mask: 0x01) */ +/* ================================================== DC_CYC_START_TIME_L ================================================== */ +/* ================================================== DC_CYC_START_TIME_H ================================================== */ +/* ================================================= DC_NEXT_SYNC1_PULSE_L ================================================= */ +/* ================================================= DC_NEXT_SYNC1_PULSE_H ================================================= */ +/* =================================================== DC_SYNC0_CYC_TIME =================================================== */ + #define R_ESC_DC_SYNC0_CYC_TIME_SYNC0CYC_Pos (0UL) /*!< SYNC0CYC (Bit 0) */ + #define R_ESC_DC_SYNC0_CYC_TIME_SYNC0CYC_Msk (0xffffffffUL) /*!< SYNC0CYC (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DC_SYNC1_CYC_TIME =================================================== */ + #define R_ESC_DC_SYNC1_CYC_TIME_SYNC1CYC_Pos (0UL) /*!< SYNC1CYC (Bit 0) */ + #define R_ESC_DC_SYNC1_CYC_TIME_SYNC1CYC_Msk (0xffffffffUL) /*!< SYNC1CYC (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DC_LATCH0_CONT ===================================================== */ + #define R_ESC_DC_LATCH0_CONT_POSEDGE_Pos (0UL) /*!< POSEDGE (Bit 0) */ + #define R_ESC_DC_LATCH0_CONT_POSEDGE_Msk (0x1UL) /*!< POSEDGE (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH0_CONT_NEGEDGE_Pos (1UL) /*!< NEGEDGE (Bit 1) */ + #define R_ESC_DC_LATCH0_CONT_NEGEDGE_Msk (0x2UL) /*!< NEGEDGE (Bitfield-Mask: 0x01) */ +/* ==================================================== DC_LATCH1_CONT ===================================================== */ + #define R_ESC_DC_LATCH1_CONT_POSEDGE_Pos (0UL) /*!< POSEDGE (Bit 0) */ + #define R_ESC_DC_LATCH1_CONT_POSEDGE_Msk (0x1UL) /*!< POSEDGE (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH1_CONT_NEGEDGE_Pos (1UL) /*!< NEGEDGE (Bit 1) */ + #define R_ESC_DC_LATCH1_CONT_NEGEDGE_Msk (0x2UL) /*!< NEGEDGE (Bitfield-Mask: 0x01) */ +/* ==================================================== DC_LATCH0_STAT ===================================================== */ + #define R_ESC_DC_LATCH0_STAT_EVENTPOS_Pos (0UL) /*!< EVENTPOS (Bit 0) */ + #define R_ESC_DC_LATCH0_STAT_EVENTPOS_Msk (0x1UL) /*!< EVENTPOS (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH0_STAT_EVENTNEG_Pos (1UL) /*!< EVENTNEG (Bit 1) */ + #define R_ESC_DC_LATCH0_STAT_EVENTNEG_Msk (0x2UL) /*!< EVENTNEG (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH0_STAT_PINSTATE_Pos (2UL) /*!< PINSTATE (Bit 2) */ + #define R_ESC_DC_LATCH0_STAT_PINSTATE_Msk (0x4UL) /*!< PINSTATE (Bitfield-Mask: 0x01) */ +/* ==================================================== DC_LATCH1_STAT ===================================================== */ + #define R_ESC_DC_LATCH1_STAT_EVENTPOS_Pos (0UL) /*!< EVENTPOS (Bit 0) */ + #define R_ESC_DC_LATCH1_STAT_EVENTPOS_Msk (0x1UL) /*!< EVENTPOS (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH1_STAT_EVENTNEG_Pos (1UL) /*!< EVENTNEG (Bit 1) */ + #define R_ESC_DC_LATCH1_STAT_EVENTNEG_Msk (0x2UL) /*!< EVENTNEG (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH1_STAT_PINSTATE_Pos (2UL) /*!< PINSTATE (Bit 2) */ + #define R_ESC_DC_LATCH1_STAT_PINSTATE_Msk (0x4UL) /*!< PINSTATE (Bitfield-Mask: 0x01) */ +/* ================================================= DC_LATCH0_TIME_POS_L ================================================== */ +/* ================================================= DC_LATCH0_TIME_POS_H ================================================== */ +/* ================================================= DC_LATCH0_TIME_NEG_L ================================================== */ +/* ================================================= DC_LATCH0_TIME_NEG_H ================================================== */ +/* ================================================= DC_LATCH1_TIME_POS_L ================================================== */ +/* ================================================= DC_LATCH1_TIME_POS_H ================================================== */ +/* ================================================= DC_LATCH1_TIME_NEG_L ================================================== */ +/* ================================================= DC_LATCH1_TIME_NEG_H ================================================== */ +/* ================================================== DC_ECAT_CNG_EV_TIME ================================================== */ + #define R_ESC_DC_ECAT_CNG_EV_TIME_ECATCHANGE_Pos (0UL) /*!< ECATCHANGE (Bit 0) */ + #define R_ESC_DC_ECAT_CNG_EV_TIME_ECATCHANGE_Msk (0xffffffffUL) /*!< ECATCHANGE (Bitfield-Mask: 0xffffffff) */ +/* ================================================= DC_PDI_START_EV_TIME ================================================== */ + #define R_ESC_DC_PDI_START_EV_TIME_PDISTART_Pos (0UL) /*!< PDISTART (Bit 0) */ + #define R_ESC_DC_PDI_START_EV_TIME_PDISTART_Msk (0xffffffffUL) /*!< PDISTART (Bitfield-Mask: 0xffffffff) */ +/* ================================================== DC_PDI_CNG_EV_TIME =================================================== */ + #define R_ESC_DC_PDI_CNG_EV_TIME_PDICHANGE_Pos (0UL) /*!< PDICHANGE (Bit 0) */ + #define R_ESC_DC_PDI_CNG_EV_TIME_PDICHANGE_Msk (0xffffffffUL) /*!< PDICHANGE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PRODUCT_ID_L ====================================================== */ +/* ===================================================== PRODUCT_ID_H ====================================================== */ +/* ====================================================== VENDOR_ID_L ====================================================== */ + #define R_ESC_VENDOR_ID_L_VENDORID_Pos (0UL) /*!< VENDORID (Bit 0) */ + #define R_ESC_VENDOR_ID_L_VENDORID_Msk (0xffffffffUL) /*!< VENDORID (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_USBHC ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== HCREVISION ======================================================= */ + #define R_USBHC_HCREVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_USBHC_HCREVISION_REV_Msk (0xffUL) /*!< REV (Bitfield-Mask: 0xff) */ +/* ======================================================= HCCONTROL ======================================================= */ + #define R_USBHC_HCCONTROL_CBSR_Pos (0UL) /*!< CBSR (Bit 0) */ + #define R_USBHC_HCCONTROL_CBSR_Msk (0x3UL) /*!< CBSR (Bitfield-Mask: 0x03) */ + #define R_USBHC_HCCONTROL_PLE_Pos (2UL) /*!< PLE (Bit 2) */ + #define R_USBHC_HCCONTROL_PLE_Msk (0x4UL) /*!< PLE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_IE_Pos (3UL) /*!< IE (Bit 3) */ + #define R_USBHC_HCCONTROL_IE_Msk (0x8UL) /*!< IE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_CLE_Pos (4UL) /*!< CLE (Bit 4) */ + #define R_USBHC_HCCONTROL_CLE_Msk (0x10UL) /*!< CLE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_BLE_Pos (5UL) /*!< BLE (Bit 5) */ + #define R_USBHC_HCCONTROL_BLE_Msk (0x20UL) /*!< BLE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_HCFS_Pos (6UL) /*!< HCFS (Bit 6) */ + #define R_USBHC_HCCONTROL_HCFS_Msk (0xc0UL) /*!< HCFS (Bitfield-Mask: 0x03) */ + #define R_USBHC_HCCONTROL_IR_Pos (8UL) /*!< IR (Bit 8) */ + #define R_USBHC_HCCONTROL_IR_Msk (0x100UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_RWC_Pos (9UL) /*!< RWC (Bit 9) */ + #define R_USBHC_HCCONTROL_RWC_Msk (0x200UL) /*!< RWC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_RWE_Pos (10UL) /*!< RWE (Bit 10) */ + #define R_USBHC_HCCONTROL_RWE_Msk (0x400UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ==================================================== HCCOMMANDSTATUS ==================================================== */ + #define R_USBHC_HCCOMMANDSTATUS_HCR_Pos (0UL) /*!< HCR (Bit 0) */ + #define R_USBHC_HCCOMMANDSTATUS_HCR_Msk (0x1UL) /*!< HCR (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCOMMANDSTATUS_CLF_Pos (1UL) /*!< CLF (Bit 1) */ + #define R_USBHC_HCCOMMANDSTATUS_CLF_Msk (0x2UL) /*!< CLF (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCOMMANDSTATUS_BLF_Pos (2UL) /*!< BLF (Bit 2) */ + #define R_USBHC_HCCOMMANDSTATUS_BLF_Msk (0x4UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCOMMANDSTATUS_OCR_Pos (3UL) /*!< OCR (Bit 3) */ + #define R_USBHC_HCCOMMANDSTATUS_OCR_Msk (0x8UL) /*!< OCR (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCOMMANDSTATUS_SOC_Pos (16UL) /*!< SOC (Bit 16) */ + #define R_USBHC_HCCOMMANDSTATUS_SOC_Msk (0x30000UL) /*!< SOC (Bitfield-Mask: 0x03) */ +/* =================================================== HCINTERRUPTSTATUS =================================================== */ + #define R_USBHC_HCINTERRUPTSTATUS_SO_Pos (0UL) /*!< SO (Bit 0) */ + #define R_USBHC_HCINTERRUPTSTATUS_SO_Msk (0x1UL) /*!< SO (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_WDH_Pos (1UL) /*!< WDH (Bit 1) */ + #define R_USBHC_HCINTERRUPTSTATUS_WDH_Msk (0x2UL) /*!< WDH (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_SF_Pos (2UL) /*!< SF (Bit 2) */ + #define R_USBHC_HCINTERRUPTSTATUS_SF_Msk (0x4UL) /*!< SF (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_RD_Pos (3UL) /*!< RD (Bit 3) */ + #define R_USBHC_HCINTERRUPTSTATUS_RD_Msk (0x8UL) /*!< RD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_UE_Pos (4UL) /*!< UE (Bit 4) */ + #define R_USBHC_HCINTERRUPTSTATUS_UE_Msk (0x10UL) /*!< UE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_FNO_Pos (5UL) /*!< FNO (Bit 5) */ + #define R_USBHC_HCINTERRUPTSTATUS_FNO_Msk (0x20UL) /*!< FNO (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_RHSC_Pos (6UL) /*!< RHSC (Bit 6) */ + #define R_USBHC_HCINTERRUPTSTATUS_RHSC_Msk (0x40UL) /*!< RHSC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_OC_Pos (30UL) /*!< OC (Bit 30) */ + #define R_USBHC_HCINTERRUPTSTATUS_OC_Msk (0x40000000UL) /*!< OC (Bitfield-Mask: 0x01) */ +/* =================================================== HCINTERRUPTENABLE =================================================== */ + #define R_USBHC_HCINTERRUPTENABLE_SOE_Pos (0UL) /*!< SOE (Bit 0) */ + #define R_USBHC_HCINTERRUPTENABLE_SOE_Msk (0x1UL) /*!< SOE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_WDHE_Pos (1UL) /*!< WDHE (Bit 1) */ + #define R_USBHC_HCINTERRUPTENABLE_WDHE_Msk (0x2UL) /*!< WDHE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_SFE_Pos (2UL) /*!< SFE (Bit 2) */ + #define R_USBHC_HCINTERRUPTENABLE_SFE_Msk (0x4UL) /*!< SFE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_RDE_Pos (3UL) /*!< RDE (Bit 3) */ + #define R_USBHC_HCINTERRUPTENABLE_RDE_Msk (0x8UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_UEE_Pos (4UL) /*!< UEE (Bit 4) */ + #define R_USBHC_HCINTERRUPTENABLE_UEE_Msk (0x10UL) /*!< UEE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_FNOE_Pos (5UL) /*!< FNOE (Bit 5) */ + #define R_USBHC_HCINTERRUPTENABLE_FNOE_Msk (0x20UL) /*!< FNOE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_RHSCE_Pos (6UL) /*!< RHSCE (Bit 6) */ + #define R_USBHC_HCINTERRUPTENABLE_RHSCE_Msk (0x40UL) /*!< RHSCE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_OCE_Pos (30UL) /*!< OCE (Bit 30) */ + #define R_USBHC_HCINTERRUPTENABLE_OCE_Msk (0x40000000UL) /*!< OCE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_MIE_Pos (31UL) /*!< MIE (Bit 31) */ + #define R_USBHC_HCINTERRUPTENABLE_MIE_Msk (0x80000000UL) /*!< MIE (Bitfield-Mask: 0x01) */ +/* ================================================== HCINTERRUPTDISABLE =================================================== */ + #define R_USBHC_HCINTERRUPTDISABLE_SOD_Pos (0UL) /*!< SOD (Bit 0) */ + #define R_USBHC_HCINTERRUPTDISABLE_SOD_Msk (0x1UL) /*!< SOD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_WDHD_Pos (1UL) /*!< WDHD (Bit 1) */ + #define R_USBHC_HCINTERRUPTDISABLE_WDHD_Msk (0x2UL) /*!< WDHD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_SFD_Pos (2UL) /*!< SFD (Bit 2) */ + #define R_USBHC_HCINTERRUPTDISABLE_SFD_Msk (0x4UL) /*!< SFD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_RDD_Pos (3UL) /*!< RDD (Bit 3) */ + #define R_USBHC_HCINTERRUPTDISABLE_RDD_Msk (0x8UL) /*!< RDD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_UED_Pos (4UL) /*!< UED (Bit 4) */ + #define R_USBHC_HCINTERRUPTDISABLE_UED_Msk (0x10UL) /*!< UED (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_FNOD_Pos (5UL) /*!< FNOD (Bit 5) */ + #define R_USBHC_HCINTERRUPTDISABLE_FNOD_Msk (0x20UL) /*!< FNOD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_RHSCD_Pos (6UL) /*!< RHSCD (Bit 6) */ + #define R_USBHC_HCINTERRUPTDISABLE_RHSCD_Msk (0x40UL) /*!< RHSCD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_OCD_Pos (30UL) /*!< OCD (Bit 30) */ + #define R_USBHC_HCINTERRUPTDISABLE_OCD_Msk (0x40000000UL) /*!< OCD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_MID_Pos (31UL) /*!< MID (Bit 31) */ + #define R_USBHC_HCINTERRUPTDISABLE_MID_Msk (0x80000000UL) /*!< MID (Bitfield-Mask: 0x01) */ +/* ======================================================== HCHCCA ========================================================= */ + #define R_USBHC_HCHCCA_RAMBA_Pos (8UL) /*!< RAMBA (Bit 8) */ + #define R_USBHC_HCHCCA_RAMBA_Msk (0xffffff00UL) /*!< RAMBA (Bitfield-Mask: 0xffffff) */ +/* ================================================== HCPERIODCCURRENTIED ================================================== */ + #define R_USBHC_HCPERIODCCURRENTIED_PCED_Pos (4UL) /*!< PCED (Bit 4) */ + #define R_USBHC_HCPERIODCCURRENTIED_PCED_Msk (0xfffffff0UL) /*!< PCED (Bitfield-Mask: 0xfffffff) */ +/* ==================================================== HCCONTROLHEADED ==================================================== */ + #define R_USBHC_HCCONTROLHEADED_CHED_Pos (4UL) /*!< CHED (Bit 4) */ + #define R_USBHC_HCCONTROLHEADED_CHED_Msk (0xfffffff0UL) /*!< CHED (Bitfield-Mask: 0xfffffff) */ +/* ================================================== HCCONTROLCURRENTED =================================================== */ + #define R_USBHC_HCCONTROLCURRENTED_CCED_Pos (4UL) /*!< CCED (Bit 4) */ + #define R_USBHC_HCCONTROLCURRENTED_CCED_Msk (0xfffffff0UL) /*!< CCED (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== HCBULKHEADED ====================================================== */ + #define R_USBHC_HCBULKHEADED_BHED_Pos (4UL) /*!< BHED (Bit 4) */ + #define R_USBHC_HCBULKHEADED_BHED_Msk (0xfffffff0UL) /*!< BHED (Bitfield-Mask: 0xfffffff) */ +/* ==================================================== HCBULKCURRENTED ==================================================== */ + #define R_USBHC_HCBULKCURRENTED_BCED_Pos (4UL) /*!< BCED (Bit 4) */ + #define R_USBHC_HCBULKCURRENTED_BCED_Msk (0xfffffff0UL) /*!< BCED (Bitfield-Mask: 0xfffffff) */ +/* ====================================================== HCDONEHEAD ======================================================= */ + #define R_USBHC_HCDONEHEAD_DH_Pos (4UL) /*!< DH (Bit 4) */ + #define R_USBHC_HCDONEHEAD_DH_Msk (0xfffffff0UL) /*!< DH (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== HCFMINTERVAL ====================================================== */ + #define R_USBHC_HCFMINTERVAL_FI_Pos (0UL) /*!< FI (Bit 0) */ + #define R_USBHC_HCFMINTERVAL_FI_Msk (0x3fffUL) /*!< FI (Bitfield-Mask: 0x3fff) */ + #define R_USBHC_HCFMINTERVAL_FSMPS_Pos (16UL) /*!< FSMPS (Bit 16) */ + #define R_USBHC_HCFMINTERVAL_FSMPS_Msk (0x7fff0000UL) /*!< FSMPS (Bitfield-Mask: 0x7fff) */ + #define R_USBHC_HCFMINTERVAL_FIT_Pos (31UL) /*!< FIT (Bit 31) */ + #define R_USBHC_HCFMINTERVAL_FIT_Msk (0x80000000UL) /*!< FIT (Bitfield-Mask: 0x01) */ +/* ===================================================== HCFNREMAINING ===================================================== */ + #define R_USBHC_HCFNREMAINING_FR_Pos (0UL) /*!< FR (Bit 0) */ + #define R_USBHC_HCFNREMAINING_FR_Msk (0x3fffUL) /*!< FR (Bitfield-Mask: 0x3fff) */ + #define R_USBHC_HCFNREMAINING_FRT_Pos (31UL) /*!< FRT (Bit 31) */ + #define R_USBHC_HCFNREMAINING_FRT_Msk (0x80000000UL) /*!< FRT (Bitfield-Mask: 0x01) */ +/* ====================================================== HCFMNUMBER ======================================================= */ + #define R_USBHC_HCFMNUMBER_FN_Pos (0UL) /*!< FN (Bit 0) */ + #define R_USBHC_HCFMNUMBER_FN_Msk (0xffffUL) /*!< FN (Bitfield-Mask: 0xffff) */ +/* ===================================================== HCPERIODSTART ===================================================== */ + #define R_USBHC_HCPERIODSTART_PS_Pos (0UL) /*!< PS (Bit 0) */ + #define R_USBHC_HCPERIODSTART_PS_Msk (0x3fffUL) /*!< PS (Bitfield-Mask: 0x3fff) */ +/* ===================================================== HCLSTHRESHOLD ===================================================== */ + #define R_USBHC_HCLSTHRESHOLD_LS_Pos (0UL) /*!< LS (Bit 0) */ + #define R_USBHC_HCLSTHRESHOLD_LS_Msk (0xfffUL) /*!< LS (Bitfield-Mask: 0xfff) */ +/* ==================================================== HCRHDESCRIPTORA ==================================================== */ + #define R_USBHC_HCRHDESCRIPTORA_NDP_Pos (0UL) /*!< NDP (Bit 0) */ + #define R_USBHC_HCRHDESCRIPTORA_NDP_Msk (0xffUL) /*!< NDP (Bitfield-Mask: 0xff) */ + #define R_USBHC_HCRHDESCRIPTORA_PSM_Pos (8UL) /*!< PSM (Bit 8) */ + #define R_USBHC_HCRHDESCRIPTORA_PSM_Msk (0x100UL) /*!< PSM (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHDESCRIPTORA_NPS_Pos (9UL) /*!< NPS (Bit 9) */ + #define R_USBHC_HCRHDESCRIPTORA_NPS_Msk (0x200UL) /*!< NPS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHDESCRIPTORA_DT_Pos (10UL) /*!< DT (Bit 10) */ + #define R_USBHC_HCRHDESCRIPTORA_DT_Msk (0x400UL) /*!< DT (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHDESCRIPTORA_OCPM_Pos (11UL) /*!< OCPM (Bit 11) */ + #define R_USBHC_HCRHDESCRIPTORA_OCPM_Msk (0x800UL) /*!< OCPM (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHDESCRIPTORA_NOCP_Pos (12UL) /*!< NOCP (Bit 12) */ + #define R_USBHC_HCRHDESCRIPTORA_NOCP_Msk (0x1000UL) /*!< NOCP (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHDESCRIPTORA_POTPGT_Pos (24UL) /*!< POTPGT (Bit 24) */ + #define R_USBHC_HCRHDESCRIPTORA_POTPGT_Msk (0xff000000UL) /*!< POTPGT (Bitfield-Mask: 0xff) */ +/* ==================================================== HCRHDESCRIPTORB ==================================================== */ + #define R_USBHC_HCRHDESCRIPTORB_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_USBHC_HCRHDESCRIPTORB_DR_Msk (0xffffUL) /*!< DR (Bitfield-Mask: 0xffff) */ + #define R_USBHC_HCRHDESCRIPTORB_PPCM_Pos (16UL) /*!< PPCM (Bit 16) */ + #define R_USBHC_HCRHDESCRIPTORB_PPCM_Msk (0xffff0000UL) /*!< PPCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== HCRHSTATUS ======================================================= */ + #define R_USBHC_HCRHSTATUS_LPS_Pos (0UL) /*!< LPS (Bit 0) */ + #define R_USBHC_HCRHSTATUS_LPS_Msk (0x1UL) /*!< LPS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHSTATUS_OCI_Pos (1UL) /*!< OCI (Bit 1) */ + #define R_USBHC_HCRHSTATUS_OCI_Msk (0x2UL) /*!< OCI (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHSTATUS_DRWE_Pos (15UL) /*!< DRWE (Bit 15) */ + #define R_USBHC_HCRHSTATUS_DRWE_Msk (0x8000UL) /*!< DRWE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHSTATUS_LPSC_Pos (16UL) /*!< LPSC (Bit 16) */ + #define R_USBHC_HCRHSTATUS_LPSC_Msk (0x10000UL) /*!< LPSC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHSTATUS_OCIC_Pos (17UL) /*!< OCIC (Bit 17) */ + #define R_USBHC_HCRHSTATUS_OCIC_Msk (0x20000UL) /*!< OCIC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHSTATUS_CRWE_Pos (31UL) /*!< CRWE (Bit 31) */ + #define R_USBHC_HCRHSTATUS_CRWE_Msk (0x80000000UL) /*!< CRWE (Bitfield-Mask: 0x01) */ +/* ==================================================== HCRHPORTSTATUS1 ==================================================== */ + #define R_USBHC_HCRHPORTSTATUS1_CCS_Pos (0UL) /*!< CCS (Bit 0) */ + #define R_USBHC_HCRHPORTSTATUS1_CCS_Msk (0x1UL) /*!< CCS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PES_Pos (1UL) /*!< PES (Bit 1) */ + #define R_USBHC_HCRHPORTSTATUS1_PES_Msk (0x2UL) /*!< PES (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PSS_Pos (2UL) /*!< PSS (Bit 2) */ + #define R_USBHC_HCRHPORTSTATUS1_PSS_Msk (0x4UL) /*!< PSS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_POCI_Pos (3UL) /*!< POCI (Bit 3) */ + #define R_USBHC_HCRHPORTSTATUS1_POCI_Msk (0x8UL) /*!< POCI (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PRS_Pos (4UL) /*!< PRS (Bit 4) */ + #define R_USBHC_HCRHPORTSTATUS1_PRS_Msk (0x10UL) /*!< PRS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PPS_Pos (8UL) /*!< PPS (Bit 8) */ + #define R_USBHC_HCRHPORTSTATUS1_PPS_Msk (0x100UL) /*!< PPS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_LSDA_Pos (9UL) /*!< LSDA (Bit 9) */ + #define R_USBHC_HCRHPORTSTATUS1_LSDA_Msk (0x200UL) /*!< LSDA (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_CSC_Pos (16UL) /*!< CSC (Bit 16) */ + #define R_USBHC_HCRHPORTSTATUS1_CSC_Msk (0x10000UL) /*!< CSC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PESC_Pos (17UL) /*!< PESC (Bit 17) */ + #define R_USBHC_HCRHPORTSTATUS1_PESC_Msk (0x20000UL) /*!< PESC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PSSC_Pos (18UL) /*!< PSSC (Bit 18) */ + #define R_USBHC_HCRHPORTSTATUS1_PSSC_Msk (0x40000UL) /*!< PSSC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_OCIC_Pos (19UL) /*!< OCIC (Bit 19) */ + #define R_USBHC_HCRHPORTSTATUS1_OCIC_Msk (0x80000UL) /*!< OCIC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PRSC_Pos (20UL) /*!< PRSC (Bit 20) */ + #define R_USBHC_HCRHPORTSTATUS1_PRSC_Msk (0x100000UL) /*!< PRSC (Bitfield-Mask: 0x01) */ +/* ===================================================== CAPL_VERSION ====================================================== */ + #define R_USBHC_CAPL_VERSION_CRL_Pos (0UL) /*!< CRL (Bit 0) */ + #define R_USBHC_CAPL_VERSION_CRL_Msk (0xffUL) /*!< CRL (Bitfield-Mask: 0xff) */ + #define R_USBHC_CAPL_VERSION_HCIVN_Pos (16UL) /*!< HCIVN (Bit 16) */ + #define R_USBHC_CAPL_VERSION_HCIVN_Msk (0xffff0000UL) /*!< HCIVN (Bitfield-Mask: 0xffff) */ +/* ======================================================= HCSPARAMS ======================================================= */ + #define R_USBHC_HCSPARAMS_N_PORTS_Pos (0UL) /*!< N_PORTS (Bit 0) */ + #define R_USBHC_HCSPARAMS_N_PORTS_Msk (0xfUL) /*!< N_PORTS (Bitfield-Mask: 0x0f) */ + #define R_USBHC_HCSPARAMS_PPC_Pos (4UL) /*!< PPC (Bit 4) */ + #define R_USBHC_HCSPARAMS_PPC_Msk (0x10UL) /*!< PPC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCSPARAMS_PTRR_Pos (7UL) /*!< PTRR (Bit 7) */ + #define R_USBHC_HCSPARAMS_PTRR_Msk (0x80UL) /*!< PTRR (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCSPARAMS_N_PCC_Pos (8UL) /*!< N_PCC (Bit 8) */ + #define R_USBHC_HCSPARAMS_N_PCC_Msk (0xf00UL) /*!< N_PCC (Bitfield-Mask: 0x0f) */ + #define R_USBHC_HCSPARAMS_N_CC_Pos (12UL) /*!< N_CC (Bit 12) */ + #define R_USBHC_HCSPARAMS_N_CC_Msk (0xf000UL) /*!< N_CC (Bitfield-Mask: 0x0f) */ + #define R_USBHC_HCSPARAMS_P_INDICATOR_Pos (16UL) /*!< P_INDICATOR (Bit 16) */ + #define R_USBHC_HCSPARAMS_P_INDICATOR_Msk (0x10000UL) /*!< P_INDICATOR (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCSPARAMS_DBGPTNUM_Pos (20UL) /*!< DBGPTNUM (Bit 20) */ + #define R_USBHC_HCSPARAMS_DBGPTNUM_Msk (0xf00000UL) /*!< DBGPTNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= HCCPARAMS ======================================================= */ + #define R_USBHC_HCCPARAMS_AC64_Pos (0UL) /*!< AC64 (Bit 0) */ + #define R_USBHC_HCCPARAMS_AC64_Msk (0x1UL) /*!< AC64 (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_PFLF_Pos (1UL) /*!< PFLF (Bit 1) */ + #define R_USBHC_HCCPARAMS_PFLF_Msk (0x2UL) /*!< PFLF (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_ASPC_Pos (2UL) /*!< ASPC (Bit 2) */ + #define R_USBHC_HCCPARAMS_ASPC_Msk (0x4UL) /*!< ASPC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_IST_Pos (4UL) /*!< IST (Bit 4) */ + #define R_USBHC_HCCPARAMS_IST_Msk (0xf0UL) /*!< IST (Bitfield-Mask: 0x0f) */ + #define R_USBHC_HCCPARAMS_EECP_Pos (8UL) /*!< EECP (Bit 8) */ + #define R_USBHC_HCCPARAMS_EECP_Msk (0xff00UL) /*!< EECP (Bitfield-Mask: 0xff) */ + #define R_USBHC_HCCPARAMS_HP_Pos (16UL) /*!< HP (Bit 16) */ + #define R_USBHC_HCCPARAMS_HP_Msk (0x10000UL) /*!< HP (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_LPMC_Pos (17UL) /*!< LPMC (Bit 17) */ + #define R_USBHC_HCCPARAMS_LPMC_Msk (0x20000UL) /*!< LPMC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_PCEC_Pos (18UL) /*!< PCEC (Bit 18) */ + #define R_USBHC_HCCPARAMS_PCEC_Msk (0x40000UL) /*!< PCEC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_PL32_Pos (19UL) /*!< PL32 (Bit 19) */ + #define R_USBHC_HCCPARAMS_PL32_Msk (0x80000UL) /*!< PL32 (Bitfield-Mask: 0x01) */ +/* ==================================================== HCSP_PORTROUTE ===================================================== */ +/* ======================================================== USBCMD ========================================================= */ + #define R_USBHC_USBCMD_RS_Pos (0UL) /*!< RS (Bit 0) */ + #define R_USBHC_USBCMD_RS_Msk (0x1UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_HCRESET_Pos (1UL) /*!< HCRESET (Bit 1) */ + #define R_USBHC_USBCMD_HCRESET_Msk (0x2UL) /*!< HCRESET (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_FLS_Pos (2UL) /*!< FLS (Bit 2) */ + #define R_USBHC_USBCMD_FLS_Msk (0xcUL) /*!< FLS (Bitfield-Mask: 0x03) */ + #define R_USBHC_USBCMD_PSE_Pos (4UL) /*!< PSE (Bit 4) */ + #define R_USBHC_USBCMD_PSE_Msk (0x10UL) /*!< PSE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_ASYNSE_Pos (5UL) /*!< ASYNSE (Bit 5) */ + #define R_USBHC_USBCMD_ASYNSE_Msk (0x20UL) /*!< ASYNSE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_IAAD_Pos (6UL) /*!< IAAD (Bit 6) */ + #define R_USBHC_USBCMD_IAAD_Msk (0x40UL) /*!< IAAD (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_LHCR_Pos (7UL) /*!< LHCR (Bit 7) */ + #define R_USBHC_USBCMD_LHCR_Msk (0x80UL) /*!< LHCR (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_ASPMC_Pos (8UL) /*!< ASPMC (Bit 8) */ + #define R_USBHC_USBCMD_ASPMC_Msk (0x300UL) /*!< ASPMC (Bitfield-Mask: 0x03) */ + #define R_USBHC_USBCMD_ASPME_Pos (11UL) /*!< ASPME (Bit 11) */ + #define R_USBHC_USBCMD_ASPME_Msk (0x800UL) /*!< ASPME (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_PPCEE_Pos (15UL) /*!< PPCEE (Bit 15) */ + #define R_USBHC_USBCMD_PPCEE_Msk (0x8000UL) /*!< PPCEE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_ITC_Pos (16UL) /*!< ITC (Bit 16) */ + #define R_USBHC_USBCMD_ITC_Msk (0xff0000UL) /*!< ITC (Bitfield-Mask: 0xff) */ + #define R_USBHC_USBCMD_HIRD_Pos (24UL) /*!< HIRD (Bit 24) */ + #define R_USBHC_USBCMD_HIRD_Msk (0xf000000UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ +/* ======================================================== USBSTS ========================================================= */ + #define R_USBHC_USBSTS_USBINT_Pos (0UL) /*!< USBINT (Bit 0) */ + #define R_USBHC_USBSTS_USBINT_Msk (0x1UL) /*!< USBINT (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_USBERRINT_Pos (1UL) /*!< USBERRINT (Bit 1) */ + #define R_USBHC_USBSTS_USBERRINT_Msk (0x2UL) /*!< USBERRINT (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_PTCGDET_Pos (2UL) /*!< PTCGDET (Bit 2) */ + #define R_USBHC_USBSTS_PTCGDET_Msk (0x4UL) /*!< PTCGDET (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_FLROV_Pos (3UL) /*!< FLROV (Bit 3) */ + #define R_USBHC_USBSTS_FLROV_Msk (0x8UL) /*!< FLROV (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_HSYSE_Pos (4UL) /*!< HSYSE (Bit 4) */ + #define R_USBHC_USBSTS_HSYSE_Msk (0x10UL) /*!< HSYSE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_IAAIS_Pos (5UL) /*!< IAAIS (Bit 5) */ + #define R_USBHC_USBSTS_IAAIS_Msk (0x20UL) /*!< IAAIS (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_EHCSTS_Pos (12UL) /*!< EHCSTS (Bit 12) */ + #define R_USBHC_USBSTS_EHCSTS_Msk (0x1000UL) /*!< EHCSTS (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_RECLAM_Pos (13UL) /*!< RECLAM (Bit 13) */ + #define R_USBHC_USBSTS_RECLAM_Msk (0x2000UL) /*!< RECLAM (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_PSCHSTS_Pos (14UL) /*!< PSCHSTS (Bit 14) */ + #define R_USBHC_USBSTS_PSCHSTS_Msk (0x4000UL) /*!< PSCHSTS (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_ASS_Pos (15UL) /*!< ASS (Bit 15) */ + #define R_USBHC_USBSTS_ASS_Msk (0x8000UL) /*!< ASS (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_PTCGDETC_Pos (16UL) /*!< PTCGDETC (Bit 16) */ + #define R_USBHC_USBSTS_PTCGDETC_Msk (0xffff0000UL) /*!< PTCGDETC (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINTR ======================================================== */ + #define R_USBHC_USBINTR_USBIE_Pos (0UL) /*!< USBIE (Bit 0) */ + #define R_USBHC_USBINTR_USBIE_Msk (0x1UL) /*!< USBIE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_USBEIE_Pos (1UL) /*!< USBEIE (Bit 1) */ + #define R_USBHC_USBINTR_USBEIE_Msk (0x2UL) /*!< USBEIE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_PTCGIE_Pos (2UL) /*!< PTCGIE (Bit 2) */ + #define R_USBHC_USBINTR_PTCGIE_Msk (0x4UL) /*!< PTCGIE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_FMLSTROE_Pos (3UL) /*!< FMLSTROE (Bit 3) */ + #define R_USBHC_USBINTR_FMLSTROE_Msk (0x8UL) /*!< FMLSTROE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_HSEE_Pos (4UL) /*!< HSEE (Bit 4) */ + #define R_USBHC_USBINTR_HSEE_Msk (0x10UL) /*!< HSEE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_INTAADVE_Pos (5UL) /*!< INTAADVE (Bit 5) */ + #define R_USBHC_USBINTR_INTAADVE_Msk (0x20UL) /*!< INTAADVE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_PCGIE_Pos (16UL) /*!< PCGIE (Bit 16) */ + #define R_USBHC_USBINTR_PCGIE_Msk (0xffff0000UL) /*!< PCGIE (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRINDEX ======================================================== */ + #define R_USBHC_FRINDEX_FRAMEINDEX_Pos (0UL) /*!< FRAMEINDEX (Bit 0) */ + #define R_USBHC_FRINDEX_FRAMEINDEX_Msk (0x3fffUL) /*!< FRAMEINDEX (Bitfield-Mask: 0x3fff) */ +/* ===================================================== CTRLDSSEGMENT ===================================================== */ +/* =================================================== PERIODICLISTBASE ==================================================== */ + #define R_USBHC_PERIODICLISTBASE_PFLSA_Pos (12UL) /*!< PFLSA (Bit 12) */ + #define R_USBHC_PERIODICLISTBASE_PFLSA_Msk (0xfffff000UL) /*!< PFLSA (Bitfield-Mask: 0xfffff) */ +/* ===================================================== ASYNCLISTADDR ===================================================== */ + #define R_USBHC_ASYNCLISTADDR_LPL_Pos (5UL) /*!< LPL (Bit 5) */ + #define R_USBHC_ASYNCLISTADDR_LPL_Msk (0xffffffe0UL) /*!< LPL (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== CONFIGFLAG ======================================================= */ + #define R_USBHC_CONFIGFLAG_CF_Pos (0UL) /*!< CF (Bit 0) */ + #define R_USBHC_CONFIGFLAG_CF_Msk (0x1UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ======================================================== PORTSC1 ======================================================== */ + #define R_USBHC_PORTSC1_CCSTS_Pos (0UL) /*!< CCSTS (Bit 0) */ + #define R_USBHC_PORTSC1_CCSTS_Msk (0x1UL) /*!< CCSTS (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_CSC_Pos (1UL) /*!< CSC (Bit 1) */ + #define R_USBHC_PORTSC1_CSC_Msk (0x2UL) /*!< CSC (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_PTE_Pos (2UL) /*!< PTE (Bit 2) */ + #define R_USBHC_PORTSC1_PTE_Msk (0x4UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_PTESC_Pos (3UL) /*!< PTESC (Bit 3) */ + #define R_USBHC_PORTSC1_PTESC_Msk (0x8UL) /*!< PTESC (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_OVCACT_Pos (4UL) /*!< OVCACT (Bit 4) */ + #define R_USBHC_PORTSC1_OVCACT_Msk (0x10UL) /*!< OVCACT (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_OVCC_Pos (5UL) /*!< OVCC (Bit 5) */ + #define R_USBHC_PORTSC1_OVCC_Msk (0x20UL) /*!< OVCC (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_FRCPTRSM_Pos (6UL) /*!< FRCPTRSM (Bit 6) */ + #define R_USBHC_PORTSC1_FRCPTRSM_Msk (0x40UL) /*!< FRCPTRSM (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_SUSPEND_Pos (7UL) /*!< SUSPEND (Bit 7) */ + #define R_USBHC_PORTSC1_SUSPEND_Msk (0x80UL) /*!< SUSPEND (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_PTRST_Pos (8UL) /*!< PTRST (Bit 8) */ + #define R_USBHC_PORTSC1_PTRST_Msk (0x100UL) /*!< PTRST (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_LPMCTL_Pos (9UL) /*!< LPMCTL (Bit 9) */ + #define R_USBHC_PORTSC1_LPMCTL_Msk (0x200UL) /*!< LPMCTL (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_LINESTS_Pos (10UL) /*!< LINESTS (Bit 10) */ + #define R_USBHC_PORTSC1_LINESTS_Msk (0xc00UL) /*!< LINESTS (Bitfield-Mask: 0x03) */ + #define R_USBHC_PORTSC1_PP_Pos (12UL) /*!< PP (Bit 12) */ + #define R_USBHC_PORTSC1_PP_Msk (0x1000UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_PTOWNR_Pos (13UL) /*!< PTOWNR (Bit 13) */ + #define R_USBHC_PORTSC1_PTOWNR_Msk (0x2000UL) /*!< PTOWNR (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_PTINDCTL_Pos (14UL) /*!< PTINDCTL (Bit 14) */ + #define R_USBHC_PORTSC1_PTINDCTL_Msk (0xc000UL) /*!< PTINDCTL (Bitfield-Mask: 0x03) */ + #define R_USBHC_PORTSC1_PTTST_Pos (16UL) /*!< PTTST (Bit 16) */ + #define R_USBHC_PORTSC1_PTTST_Msk (0xf0000UL) /*!< PTTST (Bitfield-Mask: 0x0f) */ + #define R_USBHC_PORTSC1_WKCNNT_E_Pos (20UL) /*!< WKCNNT_E (Bit 20) */ + #define R_USBHC_PORTSC1_WKCNNT_E_Msk (0x100000UL) /*!< WKCNNT_E (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_WKDSCNNT_E_Pos (21UL) /*!< WKDSCNNT_E (Bit 21) */ + #define R_USBHC_PORTSC1_WKDSCNNT_E_Msk (0x200000UL) /*!< WKDSCNNT_E (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_WKOC_E_Pos (22UL) /*!< WKOC_E (Bit 22) */ + #define R_USBHC_PORTSC1_WKOC_E_Msk (0x400000UL) /*!< WKOC_E (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_SUSPSTS_Pos (23UL) /*!< SUSPSTS (Bit 23) */ + #define R_USBHC_PORTSC1_SUSPSTS_Msk (0x1800000UL) /*!< SUSPSTS (Bitfield-Mask: 0x03) */ + #define R_USBHC_PORTSC1_DVADDR_Pos (25UL) /*!< DVADDR (Bit 25) */ + #define R_USBHC_PORTSC1_DVADDR_Msk (0xfe000000UL) /*!< DVADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================= INTENABLE ======================================================= */ + #define R_USBHC_INTENABLE_AHB_INTEN_Pos (0UL) /*!< AHB_INTEN (Bit 0) */ + #define R_USBHC_INTENABLE_AHB_INTEN_Msk (0x1UL) /*!< AHB_INTEN (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTENABLE_USBH_INTAEN_Pos (1UL) /*!< USBH_INTAEN (Bit 1) */ + #define R_USBHC_INTENABLE_USBH_INTAEN_Msk (0x2UL) /*!< USBH_INTAEN (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTENABLE_USBH_INTBEN_Pos (2UL) /*!< USBH_INTBEN (Bit 2) */ + #define R_USBHC_INTENABLE_USBH_INTBEN_Msk (0x4UL) /*!< USBH_INTBEN (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTENABLE_UCOM_INTEN_Pos (3UL) /*!< UCOM_INTEN (Bit 3) */ + #define R_USBHC_INTENABLE_UCOM_INTEN_Msk (0x8UL) /*!< UCOM_INTEN (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTENABLE_WAKEON_INTEN_Pos (4UL) /*!< WAKEON_INTEN (Bit 4) */ + #define R_USBHC_INTENABLE_WAKEON_INTEN_Msk (0x10UL) /*!< WAKEON_INTEN (Bitfield-Mask: 0x01) */ +/* ======================================================= INTSTATUS ======================================================= */ + #define R_USBHC_INTSTATUS_AHB_INT_Pos (0UL) /*!< AHB_INT (Bit 0) */ + #define R_USBHC_INTSTATUS_AHB_INT_Msk (0x1UL) /*!< AHB_INT (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTSTATUS_USBH_INTA_Pos (1UL) /*!< USBH_INTA (Bit 1) */ + #define R_USBHC_INTSTATUS_USBH_INTA_Msk (0x2UL) /*!< USBH_INTA (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTSTATUS_USBH_INTB_Pos (2UL) /*!< USBH_INTB (Bit 2) */ + #define R_USBHC_INTSTATUS_USBH_INTB_Msk (0x4UL) /*!< USBH_INTB (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTSTATUS_UCOM_INT_Pos (3UL) /*!< UCOM_INT (Bit 3) */ + #define R_USBHC_INTSTATUS_UCOM_INT_Msk (0x8UL) /*!< UCOM_INT (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTSTATUS_WAKEON_INT_Pos (4UL) /*!< WAKEON_INT (Bit 4) */ + #define R_USBHC_INTSTATUS_WAKEON_INT_Msk (0x10UL) /*!< WAKEON_INT (Bitfield-Mask: 0x01) */ +/* ======================================================= AHBBUSCTR ======================================================= */ + #define R_USBHC_AHBBUSCTR_MAX_BURST_LEN_Pos (0UL) /*!< MAX_BURST_LEN (Bit 0) */ + #define R_USBHC_AHBBUSCTR_MAX_BURST_LEN_Msk (0x3UL) /*!< MAX_BURST_LEN (Bitfield-Mask: 0x03) */ + #define R_USBHC_AHBBUSCTR_ALIGN_ADDRESS_Pos (4UL) /*!< ALIGN_ADDRESS (Bit 4) */ + #define R_USBHC_AHBBUSCTR_ALIGN_ADDRESS_Msk (0x30UL) /*!< ALIGN_ADDRESS (Bitfield-Mask: 0x03) */ + #define R_USBHC_AHBBUSCTR_PROT_MODE_Pos (8UL) /*!< PROT_MODE (Bit 8) */ + #define R_USBHC_AHBBUSCTR_PROT_MODE_Msk (0x100UL) /*!< PROT_MODE (Bitfield-Mask: 0x01) */ + #define R_USBHC_AHBBUSCTR_PROT_TYPE_Pos (12UL) /*!< PROT_TYPE (Bit 12) */ + #define R_USBHC_AHBBUSCTR_PROT_TYPE_Msk (0xf000UL) /*!< PROT_TYPE (Bitfield-Mask: 0x0f) */ +/* ======================================================== USBCTR ========================================================= */ + #define R_USBHC_USBCTR_USBH_RST_Pos (0UL) /*!< USBH_RST (Bit 0) */ + #define R_USBHC_USBCTR_USBH_RST_Msk (0x1UL) /*!< USBH_RST (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCTR_PLL_RST_Pos (1UL) /*!< PLL_RST (Bit 1) */ + #define R_USBHC_USBCTR_PLL_RST_Msk (0x2UL) /*!< PLL_RST (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCTR_DIRPD_Pos (2UL) /*!< DIRPD (Bit 2) */ + #define R_USBHC_USBCTR_DIRPD_Msk (0x4UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ========================================================= REVID ========================================================= */ + #define R_USBHC_REVID_MINV_Pos (0UL) /*!< MINV (Bit 0) */ + #define R_USBHC_REVID_MINV_Msk (0xffUL) /*!< MINV (Bitfield-Mask: 0xff) */ + #define R_USBHC_REVID_MAJV_Pos (8UL) /*!< MAJV (Bit 8) */ + #define R_USBHC_REVID_MAJV_Msk (0xff00UL) /*!< MAJV (Bitfield-Mask: 0xff) */ + #define R_USBHC_REVID_COREID_Pos (24UL) /*!< COREID (Bit 24) */ + #define R_USBHC_REVID_COREID_Msk (0xff000000UL) /*!< COREID (Bitfield-Mask: 0xff) */ +/* ====================================================== OCSLPTIMSET ====================================================== */ + #define R_USBHC_OCSLPTIMSET_TIMER_OC_Pos (0UL) /*!< TIMER_OC (Bit 0) */ + #define R_USBHC_OCSLPTIMSET_TIMER_OC_Msk (0xfffffUL) /*!< TIMER_OC (Bitfield-Mask: 0xfffff) */ + #define R_USBHC_OCSLPTIMSET_TIMER_SLEEP_Pos (20UL) /*!< TIMER_SLEEP (Bit 20) */ + #define R_USBHC_OCSLPTIMSET_TIMER_SLEEP_Msk (0x1ff00000UL) /*!< TIMER_SLEEP (Bitfield-Mask: 0x1ff) */ +/* ======================================================= COMMCTRL ======================================================== */ + #define R_USBHC_COMMCTRL_PERI_Pos (31UL) /*!< PERI (Bit 31) */ + #define R_USBHC_COMMCTRL_PERI_Msk (0x80000000UL) /*!< PERI (Bitfield-Mask: 0x01) */ +/* ======================================================= OBINTSTA ======================================================== */ + #define R_USBHC_OBINTSTA_IDCHG_STA_Pos (0UL) /*!< IDCHG_STA (Bit 0) */ + #define R_USBHC_OBINTSTA_IDCHG_STA_Msk (0x1UL) /*!< IDCHG_STA (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTSTA_OCINT_STA_Pos (1UL) /*!< OCINT_STA (Bit 1) */ + #define R_USBHC_OBINTSTA_OCINT_STA_Msk (0x2UL) /*!< OCINT_STA (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTSTA_VBSTACHG_STA_Pos (2UL) /*!< VBSTACHG_STA (Bit 2) */ + #define R_USBHC_OBINTSTA_VBSTACHG_STA_Msk (0x4UL) /*!< VBSTACHG_STA (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTSTA_VBSTAINT_STA_Pos (3UL) /*!< VBSTAINT_STA (Bit 3) */ + #define R_USBHC_OBINTSTA_VBSTAINT_STA_Msk (0x8UL) /*!< VBSTAINT_STA (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTSTA_DMMONCHG_STA_Pos (16UL) /*!< DMMONCHG_STA (Bit 16) */ + #define R_USBHC_OBINTSTA_DMMONCHG_STA_Msk (0x10000UL) /*!< DMMONCHG_STA (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTSTA_DPMONCHG_STA_Pos (17UL) /*!< DPMONCHG_STA (Bit 17) */ + #define R_USBHC_OBINTSTA_DPMONCHG_STA_Msk (0x20000UL) /*!< DPMONCHG_STA (Bitfield-Mask: 0x01) */ +/* ======================================================== OBINTEN ======================================================== */ + #define R_USBHC_OBINTEN_IDCHG_EN_Pos (0UL) /*!< IDCHG_EN (Bit 0) */ + #define R_USBHC_OBINTEN_IDCHG_EN_Msk (0x1UL) /*!< IDCHG_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTEN_OCINT_EN_Pos (1UL) /*!< OCINT_EN (Bit 1) */ + #define R_USBHC_OBINTEN_OCINT_EN_Msk (0x2UL) /*!< OCINT_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTEN_VBSTACHG_EN_Pos (2UL) /*!< VBSTACHG_EN (Bit 2) */ + #define R_USBHC_OBINTEN_VBSTACHG_EN_Msk (0x4UL) /*!< VBSTACHG_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTEN_VBSTAINT_EN_Pos (3UL) /*!< VBSTAINT_EN (Bit 3) */ + #define R_USBHC_OBINTEN_VBSTAINT_EN_Msk (0x8UL) /*!< VBSTAINT_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTEN_DMMONCHG_EN_Pos (16UL) /*!< DMMONCHG_EN (Bit 16) */ + #define R_USBHC_OBINTEN_DMMONCHG_EN_Msk (0x10000UL) /*!< DMMONCHG_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTEN_DPMONCHG_EN_Pos (17UL) /*!< DPMONCHG_EN (Bit 17) */ + #define R_USBHC_OBINTEN_DPMONCHG_EN_Msk (0x20000UL) /*!< DPMONCHG_EN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBCTRL ========================================================= */ + #define R_USBHC_VBCTRL_VBOUT_Pos (0UL) /*!< VBOUT (Bit 0) */ + #define R_USBHC_VBCTRL_VBOUT_Msk (0x1UL) /*!< VBOUT (Bitfield-Mask: 0x01) */ + #define R_USBHC_VBCTRL_VBUSENSEL_Pos (1UL) /*!< VBUSENSEL (Bit 1) */ + #define R_USBHC_VBCTRL_VBUSENSEL_Msk (0x2UL) /*!< VBUSENSEL (Bitfield-Mask: 0x01) */ + #define R_USBHC_VBCTRL_VGPUO_Pos (4UL) /*!< VGPUO (Bit 4) */ + #define R_USBHC_VBCTRL_VGPUO_Msk (0x10UL) /*!< VGPUO (Bitfield-Mask: 0x01) */ + #define R_USBHC_VBCTRL_OCCLRIEN_Pos (16UL) /*!< OCCLRIEN (Bit 16) */ + #define R_USBHC_VBCTRL_OCCLRIEN_Msk (0x10000UL) /*!< OCCLRIEN (Bitfield-Mask: 0x01) */ + #define R_USBHC_VBCTRL_OCISEL_Pos (17UL) /*!< OCISEL (Bit 17) */ + #define R_USBHC_VBCTRL_OCISEL_Msk (0x20000UL) /*!< OCISEL (Bitfield-Mask: 0x01) */ + #define R_USBHC_VBCTRL_VBLVL_Pos (20UL) /*!< VBLVL (Bit 20) */ + #define R_USBHC_VBCTRL_VBLVL_Msk (0xf00000UL) /*!< VBLVL (Bitfield-Mask: 0x0f) */ + #define R_USBHC_VBCTRL_VBSTA_Pos (28UL) /*!< VBSTA (Bit 28) */ + #define R_USBHC_VBCTRL_VBSTA_Msk (0xf0000000UL) /*!< VBSTA (Bitfield-Mask: 0x0f) */ +/* ======================================================= LINECTRL1 ======================================================= */ + #define R_USBHC_LINECTRL1_IDMON_Pos (0UL) /*!< IDMON (Bit 0) */ + #define R_USBHC_LINECTRL1_IDMON_Msk (0x1UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DMMON_Pos (2UL) /*!< DMMON (Bit 2) */ + #define R_USBHC_LINECTRL1_DMMON_Msk (0x4UL) /*!< DMMON (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DPMON_Pos (3UL) /*!< DPMON (Bit 3) */ + #define R_USBHC_LINECTRL1_DPMON_Msk (0x8UL) /*!< DPMON (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DM_RPD_Pos (16UL) /*!< DM_RPD (Bit 16) */ + #define R_USBHC_LINECTRL1_DM_RPD_Msk (0x10000UL) /*!< DM_RPD (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DMRPD_EN_Pos (17UL) /*!< DMRPD_EN (Bit 17) */ + #define R_USBHC_LINECTRL1_DMRPD_EN_Msk (0x20000UL) /*!< DMRPD_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DP_RPD_Pos (18UL) /*!< DP_RPD (Bit 18) */ + #define R_USBHC_LINECTRL1_DP_RPD_Msk (0x40000UL) /*!< DP_RPD (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DPRPD_EN_Pos (19UL) /*!< DPRPD_EN (Bit 19) */ + #define R_USBHC_LINECTRL1_DPRPD_EN_Msk (0x80000UL) /*!< DPRPD_EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USBF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG0 ======================================================== */ + #define R_USBF_SYSCFG0_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USBF_SYSCFG0_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ + #define R_USBF_SYSCFG0_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USBF_SYSCFG0_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USBF_SYSCFG0_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USBF_SYSCFG0_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USBF_SYSCFG0_HSE_Pos (7UL) /*!< HSE (Bit 7) */ + #define R_USBF_SYSCFG0_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ + #define R_USBF_SYSCFG0_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USBF_SYSCFG0_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SYSCFG1 ======================================================== */ + #define R_USBF_SYSCFG1_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USBF_SYSCFG1_BWAIT_Msk (0x3fUL) /*!< BWAIT (Bitfield-Mask: 0x3f) */ + #define R_USBF_SYSCFG1_AWAIT_Pos (8UL) /*!< AWAIT (Bit 8) */ + #define R_USBF_SYSCFG1_AWAIT_Msk (0x3f00UL) /*!< AWAIT (Bitfield-Mask: 0x3f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USBF_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USBF_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USBF_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USBF_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ + #define R_USBF_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USBF_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USBF_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USBF_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFIFO ========================================================= */ + #define R_USBF_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ======================================================== CFIFOH ========================================================= */ + #define R_USBF_CFIFOH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_CFIFOH_FIFOPORT_Msk (0xffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFIFOHH ======================================================== */ + #define R_USBF_CFIFOHH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_CFIFOHH_FIFOPORT_Msk (0xffUL) /*!< FIFOPORT (Bitfield-Mask: 0xff) */ +/* ======================================================== D0FIFO ========================================================= */ + #define R_USBF_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFOH ======================================================== */ + #define R_USBF_D0FIFOH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D0FIFOH_FIFOPORT_Msk (0xffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffff) */ +/* ======================================================= D0FIFOHH ======================================================== */ + #define R_USBF_D0FIFOHH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D0FIFOHH_FIFOPORT_Msk (0xffUL) /*!< FIFOPORT (Bitfield-Mask: 0xff) */ +/* ======================================================== D1FIFO ========================================================= */ + #define R_USBF_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFOH ======================================================== */ + #define R_USBF_D1FIFOH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D1FIFOH_FIFOPORT_Msk (0xffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffff) */ +/* ======================================================= D1FIFOHH ======================================================== */ + #define R_USBF_D1FIFOHH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D1FIFOHH_FIFOPORT_Msk (0xffUL) /*!< FIFOPORT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USBF_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USBF_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ + #define R_USBF_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USBF_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USBF_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USBF_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USBF_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USBF_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USBF_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USBF_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USBF_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USBF_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USBF_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USBF_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ + #define R_USBF_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USBF_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USBF_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USBF_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USBF_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USBF_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USBF_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ + #define R_USBF_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USBF_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USBF_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USBF_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USBF_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USBF_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USBF_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USBF_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USBF_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USBF_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ + #define R_USBF_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USBF_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USBF_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USBF_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USBF_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USBF_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USBF_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USBF_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USBF_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USBF_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ + #define R_USBF_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USBF_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USBF_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USBF_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USBF_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USBF_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ + #define R_USBF_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USBF_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USBF_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USBF_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USBF_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USBF_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USBF_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USBF_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USBF_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USBF_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USBF_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USBF_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USBF_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USBF_INTENB1_PDDETINTE_Pos (0UL) /*!< PDDETINTE (Bit 0) */ + #define R_USBF_INTENB1_PDDETINTE_Msk (0x1UL) /*!< PDDETINTE (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USBF_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USBF_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USBF_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USBF_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USBF_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USBF_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USBF_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USBF_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ + #define R_USBF_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USBF_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USBF_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USBF_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USBF_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USBF_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ + #define R_USBF_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USBF_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USBF_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USBF_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USBF_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USBF_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USBF_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USBF_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USBF_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USBF_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USBF_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USBF_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USBF_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USBF_INTSTS1_PDDETINT_Pos (0UL) /*!< PDDETINT (Bit 0) */ + #define R_USBF_INTSTS1_PDDETINT_Msk (0x1UL) /*!< PDDETINT (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USBF_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USBF_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USBF_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USBF_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USBF_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USBF_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USBF_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USBF_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ + #define R_USBF_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USBF_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USBF_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USBF_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USBF_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USBF_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USBF_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USBF_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USBF_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USBF_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ + #define R_USBF_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USBF_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USBF_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USBF_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USBF_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USBF_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USBF_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USBF_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USBF_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USBF_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USBF_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USBF_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USBF_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USBF_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USBF_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ + #define R_USBF_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USBF_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USBF_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USBF_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USBF_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USBF_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USBF_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USBF_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USBF_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USBF_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USBF_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ + #define R_USBF_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USBF_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USBF_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USBF_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USBF_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USBF_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USBF_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPEBUF ======================================================== */ + #define R_USBF_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ + #define R_USBF_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ + #define R_USBF_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ + #define R_USBF_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USBF_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USBF_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USBF_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USBF_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ + #define R_USBF_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USBF_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USBF_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USBF_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ + #define R_USBF_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USBF_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USBF_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USBF_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USBF_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USBF_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USBF_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USBF_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USBF_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USBF_LPSTS_SUSPM_Pos (14UL) /*!< SUSPM (Bit 14) */ + #define R_USBF_LPSTS_SUSPM_Msk (0x4000UL) /*!< SUSPM (Bitfield-Mask: 0x01) */ +/* ========================================================= DCTRL ========================================================= */ + #define R_USBF_DCTRL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_USBF_DCTRL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_USBF_DCTRL_LDPR_Pos (16UL) /*!< LDPR (Bit 16) */ + #define R_USBF_DCTRL_LDPR_Msk (0xf0000UL) /*!< LDPR (Bitfield-Mask: 0x0f) */ + #define R_USBF_DCTRL_LWPR_Pos (24UL) /*!< LWPR (Bit 24) */ + #define R_USBF_DCTRL_LWPR_Msk (0xf000000UL) /*!< LWPR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DSCITVL ======================================================== */ + #define R_USBF_DSCITVL_DITVL_Pos (8UL) /*!< DITVL (Bit 8) */ + #define R_USBF_DSCITVL_DITVL_Msk (0xff00UL) /*!< DITVL (Bitfield-Mask: 0xff) */ +/* ======================================================= DSTAT_EN ======================================================== */ + #define R_USBF_DSTAT_EN_EN0_Pos (0UL) /*!< EN0 (Bit 0) */ + #define R_USBF_DSTAT_EN_EN0_Msk (0x1UL) /*!< EN0 (Bitfield-Mask: 0x01) */ + #define R_USBF_DSTAT_EN_EN1_Pos (1UL) /*!< EN1 (Bit 1) */ + #define R_USBF_DSTAT_EN_EN1_Msk (0x2UL) /*!< EN1 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_ER ======================================================== */ + #define R_USBF_DSTAT_ER_ER0_Pos (0UL) /*!< ER0 (Bit 0) */ + #define R_USBF_DSTAT_ER_ER0_Msk (0x1UL) /*!< ER0 (Bitfield-Mask: 0x01) */ + #define R_USBF_DSTAT_ER_ER1_Pos (1UL) /*!< ER1 (Bit 1) */ + #define R_USBF_DSTAT_ER_ER1_Msk (0x2UL) /*!< ER1 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_END ======================================================= */ + #define R_USBF_DSTAT_END_END0_Pos (0UL) /*!< END0 (Bit 0) */ + #define R_USBF_DSTAT_END_END0_Msk (0x1UL) /*!< END0 (Bitfield-Mask: 0x01) */ + #define R_USBF_DSTAT_END_END1_Pos (1UL) /*!< END1 (Bit 1) */ + #define R_USBF_DSTAT_END_END1_Msk (0x2UL) /*!< END1 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_TC ======================================================== */ + #define R_USBF_DSTAT_TC_TC0_Pos (0UL) /*!< TC0 (Bit 0) */ + #define R_USBF_DSTAT_TC_TC0_Msk (0x1UL) /*!< TC0 (Bitfield-Mask: 0x01) */ + #define R_USBF_DSTAT_TC_TC1_Pos (1UL) /*!< TC1 (Bit 1) */ + #define R_USBF_DSTAT_TC_TC1_Msk (0x2UL) /*!< TC1 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_SUS ======================================================= */ + #define R_USBF_DSTAT_SUS_SUS0_Pos (0UL) /*!< SUS0 (Bit 0) */ + #define R_USBF_DSTAT_SUS_SUS0_Msk (0x1UL) /*!< SUS0 (Bitfield-Mask: 0x01) */ + #define R_USBF_DSTAT_SUS_SUS1_Pos (1UL) /*!< SUS1 (Bit 1) */ + #define R_USBF_DSTAT_SUS_SUS1_Msk (0x2UL) /*!< SUS1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_BSC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CMNCR ========================================================= */ + #define R_BSC_CMNCR_DPRTY_Pos (9UL) /*!< DPRTY (Bit 9) */ + #define R_BSC_CMNCR_DPRTY_Msk (0x600UL) /*!< DPRTY (Bitfield-Mask: 0x03) */ + #define R_BSC_CMNCR_AL_Pos (24UL) /*!< AL (Bit 24) */ + #define R_BSC_CMNCR_AL_Msk (0x1000000UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_BSC_CMNCR_TL_Pos (28UL) /*!< TL (Bit 28) */ + #define R_BSC_CMNCR_TL_Msk (0x10000000UL) /*!< TL (Bitfield-Mask: 0x01) */ +/* ======================================================== CSnBCR ========================================================= */ + #define R_BSC_CSnBCR_BSZ_Pos (9UL) /*!< BSZ (Bit 9) */ + #define R_BSC_CSnBCR_BSZ_Msk (0x600UL) /*!< BSZ (Bitfield-Mask: 0x03) */ + #define R_BSC_CSnBCR_TYPE_Pos (12UL) /*!< TYPE (Bit 12) */ + #define R_BSC_CSnBCR_TYPE_Msk (0x7000UL) /*!< TYPE (Bitfield-Mask: 0x07) */ + #define R_BSC_CSnBCR_IWRRS_Pos (16UL) /*!< IWRRS (Bit 16) */ + #define R_BSC_CSnBCR_IWRRS_Msk (0x70000UL) /*!< IWRRS (Bitfield-Mask: 0x07) */ + #define R_BSC_CSnBCR_IWRRD_Pos (19UL) /*!< IWRRD (Bit 19) */ + #define R_BSC_CSnBCR_IWRRD_Msk (0x380000UL) /*!< IWRRD (Bitfield-Mask: 0x07) */ + #define R_BSC_CSnBCR_IWRWS_Pos (22UL) /*!< IWRWS (Bit 22) */ + #define R_BSC_CSnBCR_IWRWS_Msk (0x1c00000UL) /*!< IWRWS (Bitfield-Mask: 0x07) */ + #define R_BSC_CSnBCR_IWRWD_Pos (25UL) /*!< IWRWD (Bit 25) */ + #define R_BSC_CSnBCR_IWRWD_Msk (0xe000000UL) /*!< IWRWD (Bitfield-Mask: 0x07) */ + #define R_BSC_CSnBCR_IWW_Pos (28UL) /*!< IWW (Bit 28) */ + #define R_BSC_CSnBCR_IWW_Msk (0x70000000UL) /*!< IWW (Bitfield-Mask: 0x07) */ +/* ======================================================= CS0WCR_0 ======================================================== */ + #define R_BSC_CS0WCR_0_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_BSC_CS0WCR_0_HW_Msk (0x3UL) /*!< HW (Bitfield-Mask: 0x03) */ + #define R_BSC_CS0WCR_0_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS0WCR_0_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS0WCR_0_WR_Pos (7UL) /*!< WR (Bit 7) */ + #define R_BSC_CS0WCR_0_WR_Msk (0x780UL) /*!< WR (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS0WCR_0_SW_Pos (11UL) /*!< SW (Bit 11) */ + #define R_BSC_CS0WCR_0_SW_Msk (0x1800UL) /*!< SW (Bitfield-Mask: 0x03) */ + #define R_BSC_CS0WCR_0_BAS_Pos (20UL) /*!< BAS (Bit 20) */ + #define R_BSC_CS0WCR_0_BAS_Msk (0x100000UL) /*!< BAS (Bitfield-Mask: 0x01) */ +/* ======================================================= CS0WCR_1 ======================================================== */ + #define R_BSC_CS0WCR_1_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS0WCR_1_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS0WCR_1_W_Pos (7UL) /*!< W (Bit 7) */ + #define R_BSC_CS0WCR_1_W_Msk (0x780UL) /*!< W (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS0WCR_1_BW_Pos (16UL) /*!< BW (Bit 16) */ + #define R_BSC_CS0WCR_1_BW_Msk (0x30000UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define R_BSC_CS0WCR_1_BST_Pos (20UL) /*!< BST (Bit 20) */ + #define R_BSC_CS0WCR_1_BST_Msk (0x300000UL) /*!< BST (Bitfield-Mask: 0x03) */ +/* ======================================================= CS0WCR_2 ======================================================== */ + #define R_BSC_CS0WCR_2_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS0WCR_2_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS0WCR_2_W_Pos (7UL) /*!< W (Bit 7) */ + #define R_BSC_CS0WCR_2_W_Msk (0x780UL) /*!< W (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS0WCR_2_BW_Pos (16UL) /*!< BW (Bit 16) */ + #define R_BSC_CS0WCR_2_BW_Msk (0x30000UL) /*!< BW (Bitfield-Mask: 0x03) */ +/* ======================================================= CS2WCR_0 ======================================================== */ + #define R_BSC_CS2WCR_0_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS2WCR_0_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS2WCR_0_WR_Pos (7UL) /*!< WR (Bit 7) */ + #define R_BSC_CS2WCR_0_WR_Msk (0x780UL) /*!< WR (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS2WCR_0_BAS_Pos (20UL) /*!< BAS (Bit 20) */ + #define R_BSC_CS2WCR_0_BAS_Msk (0x100000UL) /*!< BAS (Bitfield-Mask: 0x01) */ +/* ======================================================= CS2WCR_1 ======================================================== */ + #define R_BSC_CS2WCR_1_A2CL_Pos (7UL) /*!< A2CL (Bit 7) */ + #define R_BSC_CS2WCR_1_A2CL_Msk (0x180UL) /*!< A2CL (Bitfield-Mask: 0x03) */ +/* ======================================================= CS3WCR_0 ======================================================== */ + #define R_BSC_CS3WCR_0_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS3WCR_0_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS3WCR_0_WR_Pos (7UL) /*!< WR (Bit 7) */ + #define R_BSC_CS3WCR_0_WR_Msk (0x780UL) /*!< WR (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS3WCR_0_BAS_Pos (20UL) /*!< BAS (Bit 20) */ + #define R_BSC_CS3WCR_0_BAS_Msk (0x100000UL) /*!< BAS (Bitfield-Mask: 0x01) */ +/* ======================================================= CS3WCR_1 ======================================================== */ + #define R_BSC_CS3WCR_1_WTRC_Pos (0UL) /*!< WTRC (Bit 0) */ + #define R_BSC_CS3WCR_1_WTRC_Msk (0x3UL) /*!< WTRC (Bitfield-Mask: 0x03) */ + #define R_BSC_CS3WCR_1_TRWL_Pos (3UL) /*!< TRWL (Bit 3) */ + #define R_BSC_CS3WCR_1_TRWL_Msk (0x18UL) /*!< TRWL (Bitfield-Mask: 0x03) */ + #define R_BSC_CS3WCR_1_A3CL_Pos (7UL) /*!< A3CL (Bit 7) */ + #define R_BSC_CS3WCR_1_A3CL_Msk (0x180UL) /*!< A3CL (Bitfield-Mask: 0x03) */ + #define R_BSC_CS3WCR_1_WTRCD_Pos (10UL) /*!< WTRCD (Bit 10) */ + #define R_BSC_CS3WCR_1_WTRCD_Msk (0xc00UL) /*!< WTRCD (Bitfield-Mask: 0x03) */ + #define R_BSC_CS3WCR_1_WTRP_Pos (13UL) /*!< WTRP (Bit 13) */ + #define R_BSC_CS3WCR_1_WTRP_Msk (0x6000UL) /*!< WTRP (Bitfield-Mask: 0x03) */ +/* ======================================================== CS5WCR ========================================================= */ + #define R_BSC_CS5WCR_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_BSC_CS5WCR_HW_Msk (0x3UL) /*!< HW (Bitfield-Mask: 0x03) */ + #define R_BSC_CS5WCR_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS5WCR_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS5WCR_WR_Pos (7UL) /*!< WR (Bit 7) */ + #define R_BSC_CS5WCR_WR_Msk (0x780UL) /*!< WR (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS5WCR_SW_Pos (11UL) /*!< SW (Bit 11) */ + #define R_BSC_CS5WCR_SW_Msk (0x1800UL) /*!< SW (Bitfield-Mask: 0x03) */ + #define R_BSC_CS5WCR_WW_Pos (16UL) /*!< WW (Bit 16) */ + #define R_BSC_CS5WCR_WW_Msk (0x70000UL) /*!< WW (Bitfield-Mask: 0x07) */ + #define R_BSC_CS5WCR_MPXWSBAS_Pos (20UL) /*!< MPXWSBAS (Bit 20) */ + #define R_BSC_CS5WCR_MPXWSBAS_Msk (0x100000UL) /*!< MPXWSBAS (Bitfield-Mask: 0x01) */ + #define R_BSC_CS5WCR_SZSEL_Pos (21UL) /*!< SZSEL (Bit 21) */ + #define R_BSC_CS5WCR_SZSEL_Msk (0x200000UL) /*!< SZSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= SDCR ========================================================== */ + #define R_BSC_SDCR_A3COL_Pos (0UL) /*!< A3COL (Bit 0) */ + #define R_BSC_SDCR_A3COL_Msk (0x3UL) /*!< A3COL (Bitfield-Mask: 0x03) */ + #define R_BSC_SDCR_A3ROW_Pos (3UL) /*!< A3ROW (Bit 3) */ + #define R_BSC_SDCR_A3ROW_Msk (0x18UL) /*!< A3ROW (Bitfield-Mask: 0x03) */ + #define R_BSC_SDCR_BACTV_Pos (8UL) /*!< BACTV (Bit 8) */ + #define R_BSC_SDCR_BACTV_Msk (0x100UL) /*!< BACTV (Bitfield-Mask: 0x01) */ + #define R_BSC_SDCR_PDOWN_Pos (9UL) /*!< PDOWN (Bit 9) */ + #define R_BSC_SDCR_PDOWN_Msk (0x200UL) /*!< PDOWN (Bitfield-Mask: 0x01) */ + #define R_BSC_SDCR_RMODE_Pos (10UL) /*!< RMODE (Bit 10) */ + #define R_BSC_SDCR_RMODE_Msk (0x400UL) /*!< RMODE (Bitfield-Mask: 0x01) */ + #define R_BSC_SDCR_RFSH_Pos (11UL) /*!< RFSH (Bit 11) */ + #define R_BSC_SDCR_RFSH_Msk (0x800UL) /*!< RFSH (Bitfield-Mask: 0x01) */ + #define R_BSC_SDCR_DEEP_Pos (13UL) /*!< DEEP (Bit 13) */ + #define R_BSC_SDCR_DEEP_Msk (0x2000UL) /*!< DEEP (Bitfield-Mask: 0x01) */ + #define R_BSC_SDCR_A2COL_Pos (16UL) /*!< A2COL (Bit 16) */ + #define R_BSC_SDCR_A2COL_Msk (0x30000UL) /*!< A2COL (Bitfield-Mask: 0x03) */ + #define R_BSC_SDCR_A2ROW_Pos (19UL) /*!< A2ROW (Bit 19) */ + #define R_BSC_SDCR_A2ROW_Msk (0x180000UL) /*!< A2ROW (Bitfield-Mask: 0x03) */ +/* ========================================================= RTCSR ========================================================= */ +/* ========================================================= RTCNT ========================================================= */ +/* ========================================================= RTCOR ========================================================= */ +/* ======================================================== TOSCOR ========================================================= */ + #define R_BSC_TOSCOR_TOCNUM_Pos (0UL) /*!< TOCNUM (Bit 0) */ + #define R_BSC_TOSCOR_TOCNUM_Msk (0xffffUL) /*!< TOCNUM (Bitfield-Mask: 0xffff) */ +/* ========================================================= TOSTR ========================================================= */ + #define R_BSC_TOSTR_CS0TOSTF_Pos (0UL) /*!< CS0TOSTF (Bit 0) */ + #define R_BSC_TOSTR_CS0TOSTF_Msk (0x1UL) /*!< CS0TOSTF (Bitfield-Mask: 0x01) */ + #define R_BSC_TOSTR_CS2TOSTF_Pos (2UL) /*!< CS2TOSTF (Bit 2) */ + #define R_BSC_TOSTR_CS2TOSTF_Msk (0x4UL) /*!< CS2TOSTF (Bitfield-Mask: 0x01) */ + #define R_BSC_TOSTR_CS3TOSTF_Pos (3UL) /*!< CS3TOSTF (Bit 3) */ + #define R_BSC_TOSTR_CS3TOSTF_Msk (0x8UL) /*!< CS3TOSTF (Bitfield-Mask: 0x01) */ + #define R_BSC_TOSTR_CS5TOSTF_Pos (5UL) /*!< CS5TOSTF (Bit 5) */ + #define R_BSC_TOSTR_CS5TOSTF_Msk (0x20UL) /*!< CS5TOSTF (Bitfield-Mask: 0x01) */ +/* ========================================================= TOENR ========================================================= */ + #define R_BSC_TOENR_CS0TOEN_Pos (0UL) /*!< CS0TOEN (Bit 0) */ + #define R_BSC_TOENR_CS0TOEN_Msk (0x1UL) /*!< CS0TOEN (Bitfield-Mask: 0x01) */ + #define R_BSC_TOENR_CS2TOEN_Pos (2UL) /*!< CS2TOEN (Bit 2) */ + #define R_BSC_TOENR_CS2TOEN_Msk (0x4UL) /*!< CS2TOEN (Bitfield-Mask: 0x01) */ + #define R_BSC_TOENR_CS3TOEN_Pos (3UL) /*!< CS3TOEN (Bit 3) */ + #define R_BSC_TOENR_CS3TOEN_Msk (0x8UL) /*!< CS3TOEN (Bitfield-Mask: 0x01) */ + #define R_BSC_TOENR_CS5TOEN_Pos (5UL) /*!< CS5TOEN (Bit 5) */ + #define R_BSC_TOENR_CS5TOEN_Msk (0x20UL) /*!< CS5TOEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== WRAPCFG ======================================================== */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Pos (8UL) /*!< DSSFTCS0 (Bit 8) */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Msk (0x1f00UL) /*!< DSSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Pos (24UL) /*!< DSSFTCS1 (Bit 24) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Msk (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f) */ +/* ======================================================== COMCFG ========================================================= */ + #define R_XSPI0_COMCFG_OEASTEX_Pos (16UL) /*!< OEASTEX (Bit 16) */ + #define R_XSPI0_COMCFG_OEASTEX_Msk (0x10000UL) /*!< OEASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMCFG_OENEGEX_Pos (17UL) /*!< OENEGEX (Bit 17) */ + #define R_XSPI0_COMCFG_OENEGEX_Msk (0x20000UL) /*!< OENEGEX (Bitfield-Mask: 0x01) */ +/* ========================================================= BMCFG ========================================================= */ + #define R_XSPI0_BMCFG_WRMD_Pos (0UL) /*!< WRMD (Bit 0) */ + #define R_XSPI0_BMCFG_WRMD_Msk (0x1UL) /*!< WRMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFG_MWRCOMB_Pos (7UL) /*!< MWRCOMB (Bit 7) */ + #define R_XSPI0_BMCFG_MWRCOMB_Msk (0x80UL) /*!< MWRCOMB (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFG_MWRSIZE_Pos (8UL) /*!< MWRSIZE (Bit 8) */ + #define R_XSPI0_BMCFG_MWRSIZE_Msk (0xff00UL) /*!< MWRSIZE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_BMCFG_PREEN_Pos (16UL) /*!< PREEN (Bit 16) */ + #define R_XSPI0_BMCFG_PREEN_Msk (0x10000UL) /*!< PREEN (Bitfield-Mask: 0x01) */ +/* ======================================================= LIOCFGCS ======================================================== */ + #define R_XSPI0_LIOCFGCS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_XSPI0_LIOCFGCS_PRTMD_Msk (0x3ffUL) /*!< PRTMD (Bitfield-Mask: 0x3ff) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Pos (10UL) /*!< LATEMD (Bit 10) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Msk (0x400UL) /*!< LATEMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Pos (11UL) /*!< WRMSKMD (Bit 11) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Msk (0x800UL) /*!< WRMSKMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Pos (16UL) /*!< CSMIN (Bit 16) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Msk (0xf0000UL) /*!< CSMIN (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Pos (20UL) /*!< CSASTEX (Bit 20) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Msk (0x100000UL) /*!< CSASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Pos (21UL) /*!< CSNEGEX (Bit 21) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Msk (0x200000UL) /*!< CSNEGEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Pos (22UL) /*!< SDRDRV (Bit 22) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Msk (0x400000UL) /*!< SDRDRV (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Pos (23UL) /*!< SDRSMPMD (Bit 23) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Msk (0x800000UL) /*!< SDRSMPMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Pos (24UL) /*!< SDRSMPSFT (Bit 24) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Msk (0xf000000UL) /*!< SDRSMPSFT (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Pos (28UL) /*!< DDRSMPEX (Bit 28) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Msk (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f) */ +/* ======================================================== BMCTL0 ========================================================= */ + #define R_XSPI0_BMCTL0_CS0ACC_Pos (0UL) /*!< CS0ACC (Bit 0) */ + #define R_XSPI0_BMCTL0_CS0ACC_Msk (0x3UL) /*!< CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CS1ACC_Pos (2UL) /*!< CS1ACC (Bit 2) */ + #define R_XSPI0_BMCTL0_CS1ACC_Msk (0xcUL) /*!< CS1ACC (Bitfield-Mask: 0x03) */ +/* ======================================================== BMCTL1 ========================================================= */ + #define R_XSPI0_BMCTL1_MWRPUSH_Pos (8UL) /*!< MWRPUSH (Bit 8) */ + #define R_XSPI0_BMCTL1_MWRPUSH_Msk (0x100UL) /*!< MWRPUSH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCTL1_PBUFCLR_Pos (10UL) /*!< PBUFCLR (Bit 10) */ + #define R_XSPI0_BMCTL1_PBUFCLR_Msk (0x400UL) /*!< PBUFCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= CMCTL ========================================================= */ + #define R_XSPI0_CMCTL_XIPENCODE_Pos (0UL) /*!< XIPENCODE (Bit 0) */ + #define R_XSPI0_CMCTL_XIPENCODE_Msk (0xffUL) /*!< XIPENCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTL_XIPEXCODE_Pos (8UL) /*!< XIPEXCODE (Bit 8) */ + #define R_XSPI0_CMCTL_XIPEXCODE_Msk (0xff00UL) /*!< XIPEXCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTL_XIPEN_Pos (16UL) /*!< XIPEN (Bit 16) */ + #define R_XSPI0_CMCTL_XIPEN_Msk (0x10000UL) /*!< XIPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CSSCTL ========================================================= */ + #define R_XSPI0_CSSCTL_CS0SIZE_Pos (0UL) /*!< CS0SIZE (Bit 0) */ + #define R_XSPI0_CSSCTL_CS0SIZE_Msk (0x3fUL) /*!< CS0SIZE (Bitfield-Mask: 0x3f) */ + #define R_XSPI0_CSSCTL_CS1SIZE_Pos (8UL) /*!< CS1SIZE (Bit 8) */ + #define R_XSPI0_CSSCTL_CS1SIZE_Msk (0x3f00UL) /*!< CS1SIZE (Bitfield-Mask: 0x3f) */ +/* ======================================================== CDCTL0 ========================================================= */ + #define R_XSPI0_CDCTL0_TRREQ_Pos (0UL) /*!< TRREQ (Bit 0) */ + #define R_XSPI0_CDCTL0_TRREQ_Msk (0x1UL) /*!< TRREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_PERMD_Pos (1UL) /*!< PERMD (Bit 1) */ + #define R_XSPI0_CDCTL0_PERMD_Msk (0x2UL) /*!< PERMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_CDCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_TRNUM_Pos (4UL) /*!< TRNUM (Bit 4) */ + #define R_XSPI0_CDCTL0_TRNUM_Msk (0x30UL) /*!< TRNUM (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CDCTL0_PERITV_Pos (16UL) /*!< PERITV (Bit 16) */ + #define R_XSPI0_CDCTL0_PERITV_Msk (0x1f0000UL) /*!< PERITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CDCTL0_PERREP_Pos (24UL) /*!< PERREP (Bit 24) */ + #define R_XSPI0_CDCTL0_PERREP_Msk (0xf000000UL) /*!< PERREP (Bitfield-Mask: 0x0f) */ +/* ======================================================== CDCTL1 ========================================================= */ + #define R_XSPI0_CDCTL1_PEREXP_Pos (0UL) /*!< PEREXP (Bit 0) */ + #define R_XSPI0_CDCTL1_PEREXP_Msk (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDCTL2 ========================================================= */ + #define R_XSPI0_CDCTL2_PERMSK_Pos (0UL) /*!< PERMSK (Bit 0) */ + #define R_XSPI0_CDCTL2_PERMSK_Msk (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LPCTL0 ========================================================= */ + #define R_XSPI0_LPCTL0_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL0_PATREQ_Msk (0x1UL) /*!< PATREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XDPIN_Pos (4UL) /*!< XDPIN (Bit 4) */ + #define R_XSPI0_LPCTL0_XDPIN_Msk (0x30UL) /*!< XDPIN (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL0_XD1LEN_Pos (16UL) /*!< XD1LEN (Bit 16) */ + #define R_XSPI0_LPCTL0_XD1LEN_Msk (0x1f0000UL) /*!< XD1LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD1VAL_Pos (23UL) /*!< XD1VAL (Bit 23) */ + #define R_XSPI0_LPCTL0_XD1VAL_Msk (0x800000UL) /*!< XD1VAL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XD2LEN_Pos (24UL) /*!< XD2LEN (Bit 24) */ + #define R_XSPI0_LPCTL0_XD2LEN_Msk (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD2VAL_Pos (31UL) /*!< XD2VAL (Bit 31) */ + #define R_XSPI0_LPCTL0_XD2VAL_Msk (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTL1 ========================================================= */ + #define R_XSPI0_LPCTL1_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL1_PATREQ_Msk (0x3UL) /*!< PATREQ (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL1_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL1_RSTREP_Pos (4UL) /*!< RSTREP (Bit 4) */ + #define R_XSPI0_LPCTL1_RSTREP_Msk (0x30UL) /*!< RSTREP (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_RSTWID_Pos (8UL) /*!< RSTWID (Bit 8) */ + #define R_XSPI0_LPCTL1_RSTWID_Msk (0x700UL) /*!< RSTWID (Bitfield-Mask: 0x07) */ + #define R_XSPI0_LPCTL1_RSTSU_Pos (12UL) /*!< RSTSU (Bit 12) */ + #define R_XSPI0_LPCTL1_RSTSU_Msk (0x7000UL) /*!< RSTSU (Bitfield-Mask: 0x07) */ +/* ======================================================== LIOCTL ========================================================= */ + #define R_XSPI0_LIOCTL_WPCS0_Pos (0UL) /*!< WPCS0 (Bit 0) */ + #define R_XSPI0_LIOCTL_WPCS0_Msk (0x1UL) /*!< WPCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCTL_WPCS1_Pos (1UL) /*!< WPCS1 (Bit 1) */ + #define R_XSPI0_LIOCTL_WPCS1_Msk (0x2UL) /*!< WPCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCTL_RSTCS0_Pos (16UL) /*!< RSTCS0 (Bit 16) */ + #define R_XSPI0_LIOCTL_RSTCS0_Msk (0x10000UL) /*!< RSTCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCTL_RSTCS1_Pos (17UL) /*!< RSTCS1 (Bit 17) */ + #define R_XSPI0_LIOCTL_RSTCS1_Msk (0x20000UL) /*!< RSTCS1 (Bitfield-Mask: 0x01) */ +/* ======================================================== VERSTT ========================================================= */ + #define R_XSPI0_VERSTT_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_XSPI0_VERSTT_VER_Msk (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== COMSTT ========================================================= */ + #define R_XSPI0_COMSTT_MEMACC_Pos (0UL) /*!< MEMACC (Bit 0) */ + #define R_XSPI0_COMSTT_MEMACC_Msk (0x1UL) /*!< MEMACC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_PBUFNE_Pos (4UL) /*!< PBUFNE (Bit 4) */ + #define R_XSPI0_COMSTT_PBUFNE_Msk (0x10UL) /*!< PBUFNE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_WRBUFNE_Pos (6UL) /*!< WRBUFNE (Bit 6) */ + #define R_XSPI0_COMSTT_WRBUFNE_Msk (0x40UL) /*!< WRBUFNE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_ECSCS0_Pos (16UL) /*!< ECSCS0 (Bit 16) */ + #define R_XSPI0_COMSTT_ECSCS0_Msk (0x10000UL) /*!< ECSCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_INTCS0_Pos (17UL) /*!< INTCS0 (Bit 17) */ + #define R_XSPI0_COMSTT_INTCS0_Msk (0x20000UL) /*!< INTCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_RSTOCS0_Pos (18UL) /*!< RSTOCS0 (Bit 18) */ + #define R_XSPI0_COMSTT_RSTOCS0_Msk (0x40000UL) /*!< RSTOCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_ECSCS1_Pos (20UL) /*!< ECSCS1 (Bit 20) */ + #define R_XSPI0_COMSTT_ECSCS1_Msk (0x100000UL) /*!< ECSCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_INTCS1_Pos (21UL) /*!< INTCS1 (Bit 21) */ + #define R_XSPI0_COMSTT_INTCS1_Msk (0x200000UL) /*!< INTCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_RSTOCS1_Pos (22UL) /*!< RSTOCS1 (Bit 22) */ + #define R_XSPI0_COMSTT_RSTOCS1_Msk (0x400000UL) /*!< RSTOCS1 (Bitfield-Mask: 0x01) */ +/* ======================================================== CASTTCS ======================================================== */ + #define R_XSPI0_CASTTCS_CASUC_Pos (0UL) /*!< CASUC (Bit 0) */ + #define R_XSPI0_CASTTCS_CASUC_Msk (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTS ========================================================== */ + #define R_XSPI0_INTS_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ + #define R_XSPI0_INTS_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PATCMP_Pos (1UL) /*!< PATCMP (Bit 1) */ + #define R_XSPI0_INTS_PATCMP_Msk (0x2UL) /*!< PATCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INICMP_Pos (2UL) /*!< INICMP (Bit 2) */ + #define R_XSPI0_INTS_INICMP_Msk (0x4UL) /*!< INICMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PERTO_Pos (3UL) /*!< PERTO (Bit 3) */ + #define R_XSPI0_INTS_PERTO_Msk (0x8UL) /*!< PERTO (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_DSTOCS0_Pos (4UL) /*!< DSTOCS0 (Bit 4) */ + #define R_XSPI0_INTS_DSTOCS0_Msk (0x10UL) /*!< DSTOCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_DSTOCS1_Pos (5UL) /*!< DSTOCS1 (Bit 5) */ + #define R_XSPI0_INTS_DSTOCS1_Msk (0x20UL) /*!< DSTOCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_ECSCS0_Pos (8UL) /*!< ECSCS0 (Bit 8) */ + #define R_XSPI0_INTS_ECSCS0_Msk (0x100UL) /*!< ECSCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_ECSCS1_Pos (9UL) /*!< ECSCS1 (Bit 9) */ + #define R_XSPI0_INTS_ECSCS1_Msk (0x200UL) /*!< ECSCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INTCS0_Pos (12UL) /*!< INTCS0 (Bit 12) */ + #define R_XSPI0_INTS_INTCS0_Msk (0x1000UL) /*!< INTCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INTCS1_Pos (13UL) /*!< INTCS1 (Bit 13) */ + #define R_XSPI0_INTS_INTCS1_Msk (0x2000UL) /*!< INTCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGOF_Pos (16UL) /*!< BRGOF (Bit 16) */ + #define R_XSPI0_INTS_BRGOF_Msk (0x10000UL) /*!< BRGOF (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGUF_Pos (18UL) /*!< BRGUF (Bit 18) */ + #define R_XSPI0_INTS_BRGUF_Msk (0x40000UL) /*!< BRGUF (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BUSERR_Pos (20UL) /*!< BUSERR (Bit 20) */ + #define R_XSPI0_INTS_BUSERR_Msk (0x100000UL) /*!< BUSERR (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CAFAILCS0_Pos (28UL) /*!< CAFAILCS0 (Bit 28) */ + #define R_XSPI0_INTS_CAFAILCS0_Msk (0x10000000UL) /*!< CAFAILCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CAFAILCS1_Pos (29UL) /*!< CAFAILCS1 (Bit 29) */ + #define R_XSPI0_INTS_CAFAILCS1_Msk (0x20000000UL) /*!< CAFAILCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CASUCCS0_Pos (30UL) /*!< CASUCCS0 (Bit 30) */ + #define R_XSPI0_INTS_CASUCCS0_Msk (0x40000000UL) /*!< CASUCCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CASUCCS1_Pos (31UL) /*!< CASUCCS1 (Bit 31) */ + #define R_XSPI0_INTS_CASUCCS1_Msk (0x80000000UL) /*!< CASUCCS1 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTC ========================================================== */ + #define R_XSPI0_INTC_CMDCMPC_Pos (0UL) /*!< CMDCMPC (Bit 0) */ + #define R_XSPI0_INTC_CMDCMPC_Msk (0x1UL) /*!< CMDCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PATCMPC_Pos (1UL) /*!< PATCMPC (Bit 1) */ + #define R_XSPI0_INTC_PATCMPC_Msk (0x2UL) /*!< PATCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INICMPC_Pos (2UL) /*!< INICMPC (Bit 2) */ + #define R_XSPI0_INTC_INICMPC_Msk (0x4UL) /*!< INICMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PERTOC_Pos (3UL) /*!< PERTOC (Bit 3) */ + #define R_XSPI0_INTC_PERTOC_Msk (0x8UL) /*!< PERTOC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_DSTOCS0C_Pos (4UL) /*!< DSTOCS0C (Bit 4) */ + #define R_XSPI0_INTC_DSTOCS0C_Msk (0x10UL) /*!< DSTOCS0C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_DSTOCS1C_Pos (5UL) /*!< DSTOCS1C (Bit 5) */ + #define R_XSPI0_INTC_DSTOCS1C_Msk (0x20UL) /*!< DSTOCS1C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_ECSCS0C_Pos (8UL) /*!< ECSCS0C (Bit 8) */ + #define R_XSPI0_INTC_ECSCS0C_Msk (0x100UL) /*!< ECSCS0C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_ECSCS1C_Pos (9UL) /*!< ECSCS1C (Bit 9) */ + #define R_XSPI0_INTC_ECSCS1C_Msk (0x200UL) /*!< ECSCS1C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INTCS0C_Pos (12UL) /*!< INTCS0C (Bit 12) */ + #define R_XSPI0_INTC_INTCS0C_Msk (0x1000UL) /*!< INTCS0C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INTCS1C_Pos (13UL) /*!< INTCS1C (Bit 13) */ + #define R_XSPI0_INTC_INTCS1C_Msk (0x2000UL) /*!< INTCS1C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGOFC_Pos (16UL) /*!< BRGOFC (Bit 16) */ + #define R_XSPI0_INTC_BRGOFC_Msk (0x10000UL) /*!< BRGOFC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGUFC_Pos (18UL) /*!< BRGUFC (Bit 18) */ + #define R_XSPI0_INTC_BRGUFC_Msk (0x40000UL) /*!< BRGUFC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BUSERRC_Pos (20UL) /*!< BUSERRC (Bit 20) */ + #define R_XSPI0_INTC_BUSERRC_Msk (0x100000UL) /*!< BUSERRC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CAFAILCS0C_Pos (28UL) /*!< CAFAILCS0C (Bit 28) */ + #define R_XSPI0_INTC_CAFAILCS0C_Msk (0x10000000UL) /*!< CAFAILCS0C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CAFAILCS1C_Pos (29UL) /*!< CAFAILCS1C (Bit 29) */ + #define R_XSPI0_INTC_CAFAILCS1C_Msk (0x20000000UL) /*!< CAFAILCS1C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CASUCCS0C_Pos (30UL) /*!< CASUCCS0C (Bit 30) */ + #define R_XSPI0_INTC_CASUCCS0C_Msk (0x40000000UL) /*!< CASUCCS0C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CASUCCS1C_Pos (31UL) /*!< CASUCCS1C (Bit 31) */ + #define R_XSPI0_INTC_CASUCCS1C_Msk (0x80000000UL) /*!< CASUCCS1C (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ + #define R_XSPI0_INTE_CMDCMPE_Pos (0UL) /*!< CMDCMPE (Bit 0) */ + #define R_XSPI0_INTE_CMDCMPE_Msk (0x1UL) /*!< CMDCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PATCMPE_Pos (1UL) /*!< PATCMPE (Bit 1) */ + #define R_XSPI0_INTE_PATCMPE_Msk (0x2UL) /*!< PATCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INICMPE_Pos (2UL) /*!< INICMPE (Bit 2) */ + #define R_XSPI0_INTE_INICMPE_Msk (0x4UL) /*!< INICMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PERTOE_Pos (3UL) /*!< PERTOE (Bit 3) */ + #define R_XSPI0_INTE_PERTOE_Msk (0x8UL) /*!< PERTOE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_DSTOCS0E_Pos (4UL) /*!< DSTOCS0E (Bit 4) */ + #define R_XSPI0_INTE_DSTOCS0E_Msk (0x10UL) /*!< DSTOCS0E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_DSTOCS1E_Pos (5UL) /*!< DSTOCS1E (Bit 5) */ + #define R_XSPI0_INTE_DSTOCS1E_Msk (0x20UL) /*!< DSTOCS1E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_ECSCS0E_Pos (8UL) /*!< ECSCS0E (Bit 8) */ + #define R_XSPI0_INTE_ECSCS0E_Msk (0x100UL) /*!< ECSCS0E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_ECSCS1E_Pos (9UL) /*!< ECSCS1E (Bit 9) */ + #define R_XSPI0_INTE_ECSCS1E_Msk (0x200UL) /*!< ECSCS1E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INTCS0E_Pos (12UL) /*!< INTCS0E (Bit 12) */ + #define R_XSPI0_INTE_INTCS0E_Msk (0x1000UL) /*!< INTCS0E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INTCS1E_Pos (13UL) /*!< INTCS1E (Bit 13) */ + #define R_XSPI0_INTE_INTCS1E_Msk (0x2000UL) /*!< INTCS1E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGOFE_Pos (16UL) /*!< BRGOFE (Bit 16) */ + #define R_XSPI0_INTE_BRGOFE_Msk (0x10000UL) /*!< BRGOFE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGUFE_Pos (18UL) /*!< BRGUFE (Bit 18) */ + #define R_XSPI0_INTE_BRGUFE_Msk (0x40000UL) /*!< BRGUFE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BUSERRE_Pos (20UL) /*!< BUSERRE (Bit 20) */ + #define R_XSPI0_INTE_BUSERRE_Msk (0x100000UL) /*!< BUSERRE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CAFAILCS0E_Pos (28UL) /*!< CAFAILCS0E (Bit 28) */ + #define R_XSPI0_INTE_CAFAILCS0E_Msk (0x10000000UL) /*!< CAFAILCS0E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CAFAILCS1E_Pos (29UL) /*!< CAFAILCS1E (Bit 29) */ + #define R_XSPI0_INTE_CAFAILCS1E_Msk (0x20000000UL) /*!< CAFAILCS1E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CASUCCS0E_Pos (30UL) /*!< CASUCCS0E (Bit 30) */ + #define R_XSPI0_INTE_CASUCCS0E_Msk (0x40000000UL) /*!< CASUCCS0E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CASUCCS1E_Pos (31UL) /*!< CASUCCS1E (Bit 31) */ + #define R_XSPI0_INTE_CASUCCS1E_Msk (0x80000000UL) /*!< CASUCCS1E (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSC_NS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SCKCR ========================================================= */ + #define R_SYSC_NS_SCKCR_FSELXSPI0_Pos (0UL) /*!< FSELXSPI0 (Bit 0) */ + #define R_SYSC_NS_SCKCR_FSELXSPI0_Msk (0x7UL) /*!< FSELXSPI0 (Bitfield-Mask: 0x07) */ + #define R_SYSC_NS_SCKCR_DIVSELXSPI0_Pos (6UL) /*!< DIVSELXSPI0 (Bit 6) */ + #define R_SYSC_NS_SCKCR_DIVSELXSPI0_Msk (0x40UL) /*!< DIVSELXSPI0 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_FSELXSPI1_Pos (8UL) /*!< FSELXSPI1 (Bit 8) */ + #define R_SYSC_NS_SCKCR_FSELXSPI1_Msk (0x700UL) /*!< FSELXSPI1 (Bitfield-Mask: 0x07) */ + #define R_SYSC_NS_SCKCR_DIVSELXSPI1_Pos (14UL) /*!< DIVSELXSPI1 (Bit 14) */ + #define R_SYSC_NS_SCKCR_DIVSELXSPI1_Msk (0x4000UL) /*!< DIVSELXSPI1 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_CKIO_Pos (16UL) /*!< CKIO (Bit 16) */ + #define R_SYSC_NS_SCKCR_CKIO_Msk (0x70000UL) /*!< CKIO (Bitfield-Mask: 0x07) */ + #define R_SYSC_NS_SCKCR_FSELCANFD_Pos (20UL) /*!< FSELCANFD (Bit 20) */ + #define R_SYSC_NS_SCKCR_FSELCANFD_Msk (0x100000UL) /*!< FSELCANFD (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_PHYSEL_Pos (21UL) /*!< PHYSEL (Bit 21) */ + #define R_SYSC_NS_SCKCR_PHYSEL_Msk (0x200000UL) /*!< PHYSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_CLMASEL_Pos (22UL) /*!< CLMASEL (Bit 22) */ + #define R_SYSC_NS_SCKCR_CLMASEL_Msk (0x400000UL) /*!< CLMASEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SPI0ASYNCSEL_Pos (24UL) /*!< SPI0ASYNCSEL (Bit 24) */ + #define R_SYSC_NS_SCKCR_SPI0ASYNCSEL_Msk (0x1000000UL) /*!< SPI0ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SPI1ASYNCSEL_Pos (25UL) /*!< SPI1ASYNCSEL (Bit 25) */ + #define R_SYSC_NS_SCKCR_SPI1ASYNCSEL_Msk (0x2000000UL) /*!< SPI1ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SPI2ASYNCSEL_Pos (26UL) /*!< SPI2ASYNCSEL (Bit 26) */ + #define R_SYSC_NS_SCKCR_SPI2ASYNCSEL_Msk (0x4000000UL) /*!< SPI2ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SCI0ASYNCSEL_Pos (27UL) /*!< SCI0ASYNCSEL (Bit 27) */ + #define R_SYSC_NS_SCKCR_SCI0ASYNCSEL_Msk (0x8000000UL) /*!< SCI0ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SCI1ASYNCSEL_Pos (28UL) /*!< SCI1ASYNCSEL (Bit 28) */ + #define R_SYSC_NS_SCKCR_SCI1ASYNCSEL_Msk (0x10000000UL) /*!< SCI1ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SCI2ASYNCSEL_Pos (29UL) /*!< SCI2ASYNCSEL (Bit 29) */ + #define R_SYSC_NS_SCKCR_SCI2ASYNCSEL_Msk (0x20000000UL) /*!< SCI2ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SCI3ASYNCSEL_Pos (30UL) /*!< SCI3ASYNCSEL (Bit 30) */ + #define R_SYSC_NS_SCKCR_SCI3ASYNCSEL_Msk (0x40000000UL) /*!< SCI3ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SCI4ASYNCSEL_Pos (31UL) /*!< SCI4ASYNCSEL (Bit 31) */ + #define R_SYSC_NS_SCKCR_SCI4ASYNCSEL_Msk (0x80000000UL) /*!< SCI4ASYNCSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSC_NS_RSTSR0_TRF_Pos (1UL) /*!< TRF (Bit 1) */ + #define R_SYSC_NS_RSTSR0_TRF_Msk (0x2UL) /*!< TRF (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_RSTSR0_ERRF_Pos (2UL) /*!< ERRF (Bit 2) */ + #define R_SYSC_NS_RSTSR0_ERRF_Msk (0x4UL) /*!< ERRF (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_RSTSR0_SWRSF_Pos (3UL) /*!< SWRSF (Bit 3) */ + #define R_SYSC_NS_RSTSR0_SWRSF_Msk (0x8UL) /*!< SWRSF (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_RSTSR0_SWR0F_Pos (4UL) /*!< SWR0F (Bit 4) */ + #define R_SYSC_NS_RSTSR0_SWR0F_Msk (0x10UL) /*!< SWR0F (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_RSTSR0_SWR1F_Pos (5UL) /*!< SWR1F (Bit 5) */ + #define R_SYSC_NS_RSTSR0_SWR1F_Msk (0x20UL) /*!< SWR1F (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCTLA ========================================================= */ + #define R_SYSC_NS_MRCTLA_MRCTLA04_Pos (4UL) /*!< MRCTLA04 (Bit 4) */ + #define R_SYSC_NS_MRCTLA_MRCTLA04_Msk (0x10UL) /*!< MRCTLA04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLA_MRCTLA05_Pos (5UL) /*!< MRCTLA05 (Bit 5) */ + #define R_SYSC_NS_MRCTLA_MRCTLA05_Msk (0x20UL) /*!< MRCTLA05 (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCTLE ========================================================= */ + #define R_SYSC_NS_MRCTLE_MRCTLE00_Pos (0UL) /*!< MRCTLE00 (Bit 0) */ + #define R_SYSC_NS_MRCTLE_MRCTLE00_Msk (0x1UL) /*!< MRCTLE00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE01_Pos (1UL) /*!< MRCTLE01 (Bit 1) */ + #define R_SYSC_NS_MRCTLE_MRCTLE01_Msk (0x2UL) /*!< MRCTLE01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE02_Pos (2UL) /*!< MRCTLE02 (Bit 2) */ + #define R_SYSC_NS_MRCTLE_MRCTLE02_Msk (0x4UL) /*!< MRCTLE02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE03_Pos (3UL) /*!< MRCTLE03 (Bit 3) */ + #define R_SYSC_NS_MRCTLE_MRCTLE03_Msk (0x8UL) /*!< MRCTLE03 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE04_Pos (4UL) /*!< MRCTLE04 (Bit 4) */ + #define R_SYSC_NS_MRCTLE_MRCTLE04_Msk (0x10UL) /*!< MRCTLE04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE05_Pos (5UL) /*!< MRCTLE05 (Bit 5) */ + #define R_SYSC_NS_MRCTLE_MRCTLE05_Msk (0x20UL) /*!< MRCTLE05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE06_Pos (6UL) /*!< MRCTLE06 (Bit 6) */ + #define R_SYSC_NS_MRCTLE_MRCTLE06_Msk (0x40UL) /*!< MRCTLE06 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA00_Pos (0UL) /*!< MSTPCRA00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA00_Msk (0x1UL) /*!< MSTPCRA00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA04_Pos (4UL) /*!< MSTPCRA04 (Bit 4) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA04_Msk (0x10UL) /*!< MSTPCRA04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA05_Pos (5UL) /*!< MSTPCRA05 (Bit 5) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA05_Msk (0x20UL) /*!< MSTPCRA05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA08_Pos (8UL) /*!< MSTPCRA08 (Bit 8) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA08_Msk (0x100UL) /*!< MSTPCRA08 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA09_Pos (9UL) /*!< MSTPCRA09 (Bit 9) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA09_Msk (0x200UL) /*!< MSTPCRA09 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA10_Pos (10UL) /*!< MSTPCRA10 (Bit 10) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA10_Msk (0x400UL) /*!< MSTPCRA10 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA11_Pos (11UL) /*!< MSTPCRA11 (Bit 11) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA11_Msk (0x800UL) /*!< MSTPCRA11 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA12_Pos (12UL) /*!< MSTPCRA12 (Bit 12) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA12_Msk (0x1000UL) /*!< MSTPCRA12 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB00_Pos (0UL) /*!< MSTPCRB00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB00_Msk (0x1UL) /*!< MSTPCRB00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB01_Pos (1UL) /*!< MSTPCRB01 (Bit 1) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB01_Msk (0x2UL) /*!< MSTPCRB01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB04_Pos (4UL) /*!< MSTPCRB04 (Bit 4) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB04_Msk (0x10UL) /*!< MSTPCRB04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB05_Pos (5UL) /*!< MSTPCRB05 (Bit 5) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB05_Msk (0x20UL) /*!< MSTPCRB05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB06_Pos (6UL) /*!< MSTPCRB06 (Bit 6) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB06_Msk (0x40UL) /*!< MSTPCRB06 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC00_Pos (0UL) /*!< MSTPCRC00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC00_Msk (0x1UL) /*!< MSTPCRC00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC01_Pos (1UL) /*!< MSTPCRC01 (Bit 1) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC01_Msk (0x2UL) /*!< MSTPCRC01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC02_Pos (2UL) /*!< MSTPCRC02 (Bit 2) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC02_Msk (0x4UL) /*!< MSTPCRC02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC05_Pos (5UL) /*!< MSTPCRC05 (Bit 5) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC05_Msk (0x20UL) /*!< MSTPCRC05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC06_Pos (6UL) /*!< MSTPCRC06 (Bit 6) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC06_Msk (0x40UL) /*!< MSTPCRC06 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC07_Pos (7UL) /*!< MSTPCRC07 (Bit 7) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC07_Msk (0x80UL) /*!< MSTPCRC07 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD00_Pos (0UL) /*!< MSTPCRD00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD00_Msk (0x1UL) /*!< MSTPCRD00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD01_Pos (1UL) /*!< MSTPCRD01 (Bit 1) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD01_Msk (0x2UL) /*!< MSTPCRD01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD02_Pos (2UL) /*!< MSTPCRD02 (Bit 2) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD02_Msk (0x4UL) /*!< MSTPCRD02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD03_Pos (3UL) /*!< MSTPCRD03 (Bit 3) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD03_Msk (0x8UL) /*!< MSTPCRD03 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD04_Pos (4UL) /*!< MSTPCRD04 (Bit 4) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD04_Msk (0x10UL) /*!< MSTPCRD04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD05_Pos (5UL) /*!< MSTPCRD05 (Bit 5) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD05_Msk (0x20UL) /*!< MSTPCRD05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD06_Pos (6UL) /*!< MSTPCRD06 (Bit 6) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD06_Msk (0x40UL) /*!< MSTPCRD06 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD07_Pos (7UL) /*!< MSTPCRD07 (Bit 7) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD07_Msk (0x80UL) /*!< MSTPCRD07 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD08_Pos (8UL) /*!< MSTPCRD08 (Bit 8) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD08_Msk (0x100UL) /*!< MSTPCRD08 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD09_Pos (9UL) /*!< MSTPCRD09 (Bit 9) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD09_Msk (0x200UL) /*!< MSTPCRD09 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD10_Pos (10UL) /*!< MSTPCRD10 (Bit 10) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD10_Msk (0x400UL) /*!< MSTPCRD10 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD11_Pos (11UL) /*!< MSTPCRD11 (Bit 11) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD11_Msk (0x800UL) /*!< MSTPCRD11 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE00_Pos (0UL) /*!< MSTPCRE00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE00_Msk (0x1UL) /*!< MSTPCRE00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE01_Pos (1UL) /*!< MSTPCRE01 (Bit 1) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE01_Msk (0x2UL) /*!< MSTPCRE01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE02_Pos (2UL) /*!< MSTPCRE02 (Bit 2) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE02_Msk (0x4UL) /*!< MSTPCRE02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE03_Pos (3UL) /*!< MSTPCRE03 (Bit 3) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE03_Msk (0x8UL) /*!< MSTPCRE03 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE04_Pos (4UL) /*!< MSTPCRE04 (Bit 4) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE04_Msk (0x10UL) /*!< MSTPCRE04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE08_Pos (8UL) /*!< MSTPCRE08 (Bit 8) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE08_Msk (0x100UL) /*!< MSTPCRE08 (Bitfield-Mask: 0x01) */ +/* ======================================================== MD_MON ========================================================= */ + #define R_SYSC_NS_MD_MON_MDDMON_Pos (0UL) /*!< MDDMON (Bit 0) */ + #define R_SYSC_NS_MD_MON_MDDMON_Msk (0x1UL) /*!< MDDMON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDWMON_Pos (4UL) /*!< MDWMON (Bit 4) */ + #define R_SYSC_NS_MD_MON_MDWMON_Msk (0x10UL) /*!< MDWMON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDP_Pos (8UL) /*!< MDP (Bit 8) */ + #define R_SYSC_NS_MD_MON_MDP_Msk (0x300UL) /*!< MDP (Bitfield-Mask: 0x03) */ + #define R_SYSC_NS_MD_MON_MD0MON_Pos (12UL) /*!< MD0MON (Bit 12) */ + #define R_SYSC_NS_MD_MON_MD0MON_Msk (0x1000UL) /*!< MD0MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MD1MON_Pos (13UL) /*!< MD1MON (Bit 13) */ + #define R_SYSC_NS_MD_MON_MD1MON_Msk (0x2000UL) /*!< MD1MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MD2MON_Pos (14UL) /*!< MD2MON (Bit 14) */ + #define R_SYSC_NS_MD_MON_MD2MON_Msk (0x4000UL) /*!< MD2MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDV0MON_Pos (16UL) /*!< MDV0MON (Bit 16) */ + #define R_SYSC_NS_MD_MON_MDV0MON_Msk (0x10000UL) /*!< MDV0MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDV1MON_Pos (17UL) /*!< MDV1MON (Bit 17) */ + #define R_SYSC_NS_MD_MON_MDV1MON_Msk (0x20000UL) /*!< MDV1MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDV2MON_Pos (18UL) /*!< MDV2MON (Bit 18) */ + #define R_SYSC_NS_MD_MON_MDV2MON_Msk (0x40000UL) /*!< MDV2MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDV3MON_Pos (19UL) /*!< MDV3MON (Bit 19) */ + #define R_SYSC_NS_MD_MON_MDV3MON_Msk (0x80000UL) /*!< MDV3MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDV4MON_Pos (20UL) /*!< MDV4MON (Bit 20) */ + #define R_SYSC_NS_MD_MON_MDV4MON_Msk (0x100000UL) /*!< MDV4MON (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SEM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= SYTSEMFEN ======================================================= */ + #define R_SEM_SYTSEMFEN_SEMFEN_Pos (0UL) /*!< SEMFEN (Bit 0) */ + #define R_SEM_SYTSEMFEN_SEMFEN_Msk (0x1UL) /*!< SEMFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SYTSEMF ======================================================== */ + #define R_SEM_SYTSEMF_SEMF_Pos (0UL) /*!< SEMF (Bit 0) */ + #define R_SEM_SYTSEMF_SEMF_Msk (0x1UL) /*!< SEMF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELO ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELOPA ========================================================= */ + #define R_ELO_ELOPA_MTU0MD_Pos (0UL) /*!< MTU0MD (Bit 0) */ + #define R_ELO_ELOPA_MTU0MD_Msk (0x3UL) /*!< MTU0MD (Bitfield-Mask: 0x03) */ + #define R_ELO_ELOPA_MTU3MD_Pos (6UL) /*!< MTU3MD (Bit 6) */ + #define R_ELO_ELOPA_MTU3MD_Msk (0xc0UL) /*!< MTU3MD (Bitfield-Mask: 0x03) */ +/* ========================================================= ELOPB ========================================================= */ + #define R_ELO_ELOPB_MTU4MD_Pos (0UL) /*!< MTU4MD (Bit 0) */ + #define R_ELO_ELOPB_MTU4MD_Msk (0x3UL) /*!< MTU4MD (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_RWP_NS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRCRN ========================================================= */ + #define R_RWP_NS_PRCRN_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_RWP_NS_PRCRN_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_RWP_NS_PRCRN_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_RWP_NS_PRCRN_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_RWP_NS_PRCRN_PRC2_Pos (2UL) /*!< PRC2 (Bit 2) */ + #define R_RWP_NS_PRCRN_PRC2_Msk (0x4UL) /*!< PRC2 (Bitfield-Mask: 0x01) */ + #define R_RWP_NS_PRCRN_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_RWP_NS_PRCRN_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= RTCA0CTL0 ======================================================= */ + #define R_RTC_RTCA0CTL0_RTCA0SLSB_Pos (4UL) /*!< RTCA0SLSB (Bit 4) */ + #define R_RTC_RTCA0CTL0_RTCA0SLSB_Msk (0x10UL) /*!< RTCA0SLSB (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL0_RTCA0AMPM_Pos (5UL) /*!< RTCA0AMPM (Bit 5) */ + #define R_RTC_RTCA0CTL0_RTCA0AMPM_Msk (0x20UL) /*!< RTCA0AMPM (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL0_RTCA0CEST_Pos (6UL) /*!< RTCA0CEST (Bit 6) */ + #define R_RTC_RTCA0CTL0_RTCA0CEST_Msk (0x40UL) /*!< RTCA0CEST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL0_RTCA0CE_Pos (7UL) /*!< RTCA0CE (Bit 7) */ + #define R_RTC_RTCA0CTL0_RTCA0CE_Msk (0x80UL) /*!< RTCA0CE (Bitfield-Mask: 0x01) */ +/* ======================================================= RTCA0CTL1 ======================================================= */ + #define R_RTC_RTCA0CTL1_RTCA0CT_Pos (0UL) /*!< RTCA0CT (Bit 0) */ + #define R_RTC_RTCA0CTL1_RTCA0CT_Msk (0x7UL) /*!< RTCA0CT (Bitfield-Mask: 0x07) */ + #define R_RTC_RTCA0CTL1_RTCA01SE_Pos (3UL) /*!< RTCA01SE (Bit 3) */ + #define R_RTC_RTCA0CTL1_RTCA01SE_Msk (0x8UL) /*!< RTCA01SE (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL1_RTCA0ALME_Pos (4UL) /*!< RTCA0ALME (Bit 4) */ + #define R_RTC_RTCA0CTL1_RTCA0ALME_Msk (0x10UL) /*!< RTCA0ALME (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL1_RTCA01HZE_Pos (5UL) /*!< RTCA01HZE (Bit 5) */ + #define R_RTC_RTCA0CTL1_RTCA01HZE_Msk (0x20UL) /*!< RTCA01HZE (Bitfield-Mask: 0x01) */ +/* ======================================================= RTCA0CTL2 ======================================================= */ + #define R_RTC_RTCA0CTL2_RTCA0WAIT_Pos (0UL) /*!< RTCA0WAIT (Bit 0) */ + #define R_RTC_RTCA0CTL2_RTCA0WAIT_Msk (0x1UL) /*!< RTCA0WAIT (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL2_RTCA0WST_Pos (1UL) /*!< RTCA0WST (Bit 1) */ + #define R_RTC_RTCA0CTL2_RTCA0WST_Msk (0x2UL) /*!< RTCA0WST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL2_RTCA0RSUB_Pos (2UL) /*!< RTCA0RSUB (Bit 2) */ + #define R_RTC_RTCA0CTL2_RTCA0RSUB_Msk (0x4UL) /*!< RTCA0RSUB (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL2_RTCA0RSST_Pos (3UL) /*!< RTCA0RSST (Bit 3) */ + #define R_RTC_RTCA0CTL2_RTCA0RSST_Msk (0x8UL) /*!< RTCA0RSST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL2_RTCA0WSST_Pos (4UL) /*!< RTCA0WSST (Bit 4) */ + #define R_RTC_RTCA0CTL2_RTCA0WSST_Msk (0x10UL) /*!< RTCA0WSST (Bitfield-Mask: 0x01) */ +/* ======================================================= RTCA0SUBC ======================================================= */ + #define R_RTC_RTCA0SUBC_RTCA0SUBC_Pos (0UL) /*!< RTCA0SUBC (Bit 0) */ + #define R_RTC_RTCA0SUBC_RTCA0SUBC_Msk (0x3fffffUL) /*!< RTCA0SUBC (Bitfield-Mask: 0x3fffff) */ +/* ======================================================= RTCA0SRBU ======================================================= */ + #define R_RTC_RTCA0SRBU_RTCA0SRBU_Pos (0UL) /*!< RTCA0SRBU (Bit 0) */ + #define R_RTC_RTCA0SRBU_RTCA0SRBU_Msk (0x3fffffUL) /*!< RTCA0SRBU (Bitfield-Mask: 0x3fffff) */ +/* ======================================================= RTCA0SEC ======================================================== */ + #define R_RTC_RTCA0SEC_RTCA0SEC_Pos (0UL) /*!< RTCA0SEC (Bit 0) */ + #define R_RTC_RTCA0SEC_RTCA0SEC_Msk (0x7fUL) /*!< RTCA0SEC (Bitfield-Mask: 0x7f) */ +/* ======================================================= RTCA0MIN ======================================================== */ + #define R_RTC_RTCA0MIN_RTCA0MIN_Pos (0UL) /*!< RTCA0MIN (Bit 0) */ + #define R_RTC_RTCA0MIN_RTCA0MIN_Msk (0x7fUL) /*!< RTCA0MIN (Bitfield-Mask: 0x7f) */ +/* ======================================================= RTCA0HOUR ======================================================= */ + #define R_RTC_RTCA0HOUR_RTCA0HOUR_Pos (0UL) /*!< RTCA0HOUR (Bit 0) */ + #define R_RTC_RTCA0HOUR_RTCA0HOUR_Msk (0x3fUL) /*!< RTCA0HOUR (Bitfield-Mask: 0x3f) */ +/* ======================================================= RTCA0WEEK ======================================================= */ + #define R_RTC_RTCA0WEEK_RTCA0WEEK_Pos (0UL) /*!< RTCA0WEEK (Bit 0) */ + #define R_RTC_RTCA0WEEK_RTCA0WEEK_Msk (0x7UL) /*!< RTCA0WEEK (Bitfield-Mask: 0x07) */ +/* ======================================================= RTCA0DAY ======================================================== */ + #define R_RTC_RTCA0DAY_RTCA0DAY_Pos (0UL) /*!< RTCA0DAY (Bit 0) */ + #define R_RTC_RTCA0DAY_RTCA0DAY_Msk (0x3fUL) /*!< RTCA0DAY (Bitfield-Mask: 0x3f) */ +/* ====================================================== RTCA0MONTH ======================================================= */ + #define R_RTC_RTCA0MONTH_RTCA0MONTH_Pos (0UL) /*!< RTCA0MONTH (Bit 0) */ + #define R_RTC_RTCA0MONTH_RTCA0MONTH_Msk (0x1fUL) /*!< RTCA0MONTH (Bitfield-Mask: 0x1f) */ +/* ======================================================= RTCA0YEAR ======================================================= */ + #define R_RTC_RTCA0YEAR_RTCA0YEAR_Pos (0UL) /*!< RTCA0YEAR (Bit 0) */ + #define R_RTC_RTCA0YEAR_RTCA0YEAR_Msk (0xffUL) /*!< RTCA0YEAR (Bitfield-Mask: 0xff) */ +/* ======================================================= RTCA0TIME ======================================================= */ + #define R_RTC_RTCA0TIME_RTCA0SEC_Pos (0UL) /*!< RTCA0SEC (Bit 0) */ + #define R_RTC_RTCA0TIME_RTCA0SEC_Msk (0xffUL) /*!< RTCA0SEC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0TIME_RTCA0MIN_Pos (8UL) /*!< RTCA0MIN (Bit 8) */ + #define R_RTC_RTCA0TIME_RTCA0MIN_Msk (0xff00UL) /*!< RTCA0MIN (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0TIME_RTCA0HOUR_Pos (16UL) /*!< RTCA0HOUR (Bit 16) */ + #define R_RTC_RTCA0TIME_RTCA0HOUR_Msk (0xff0000UL) /*!< RTCA0HOUR (Bitfield-Mask: 0xff) */ +/* ======================================================= RTCA0CAL ======================================================== */ + #define R_RTC_RTCA0CAL_RTCA0WEEK_Pos (0UL) /*!< RTCA0WEEK (Bit 0) */ + #define R_RTC_RTCA0CAL_RTCA0WEEK_Msk (0xffUL) /*!< RTCA0WEEK (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CAL_RTCA0DAY_Pos (8UL) /*!< RTCA0DAY (Bit 8) */ + #define R_RTC_RTCA0CAL_RTCA0DAY_Msk (0xff00UL) /*!< RTCA0DAY (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CAL_RTCA0MONTH_Pos (16UL) /*!< RTCA0MONTH (Bit 16) */ + #define R_RTC_RTCA0CAL_RTCA0MONTH_Msk (0xff0000UL) /*!< RTCA0MONTH (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CAL_RTCA0YEAR_Pos (24UL) /*!< RTCA0YEAR (Bit 24) */ + #define R_RTC_RTCA0CAL_RTCA0YEAR_Msk (0xff000000UL) /*!< RTCA0YEAR (Bitfield-Mask: 0xff) */ +/* ======================================================= RTCA0SCMP ======================================================= */ + #define R_RTC_RTCA0SCMP_RTCA0SCMP_Pos (0UL) /*!< RTCA0SCMP (Bit 0) */ + #define R_RTC_RTCA0SCMP_RTCA0SCMP_Msk (0x3fffffUL) /*!< RTCA0SCMP (Bitfield-Mask: 0x3fffff) */ +/* ======================================================= RTCA0ALM ======================================================== */ + #define R_RTC_RTCA0ALM_RTCA0ALM_Pos (0UL) /*!< RTCA0ALM (Bit 0) */ + #define R_RTC_RTCA0ALM_RTCA0ALM_Msk (0x7fUL) /*!< RTCA0ALM (Bitfield-Mask: 0x7f) */ +/* ======================================================= RTCA0ALH ======================================================== */ + #define R_RTC_RTCA0ALH_RTCA0ALH_Pos (0UL) /*!< RTCA0ALH (Bit 0) */ + #define R_RTC_RTCA0ALH_RTCA0ALH_Msk (0x3fUL) /*!< RTCA0ALH (Bitfield-Mask: 0x3f) */ +/* ======================================================= RTCA0ALW ======================================================== */ + #define R_RTC_RTCA0ALW_RTCA0ALW0_Pos (0UL) /*!< RTCA0ALW0 (Bit 0) */ + #define R_RTC_RTCA0ALW_RTCA0ALW0_Msk (0x1UL) /*!< RTCA0ALW0 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW1_Pos (1UL) /*!< RTCA0ALW1 (Bit 1) */ + #define R_RTC_RTCA0ALW_RTCA0ALW1_Msk (0x2UL) /*!< RTCA0ALW1 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW2_Pos (2UL) /*!< RTCA0ALW2 (Bit 2) */ + #define R_RTC_RTCA0ALW_RTCA0ALW2_Msk (0x4UL) /*!< RTCA0ALW2 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW3_Pos (3UL) /*!< RTCA0ALW3 (Bit 3) */ + #define R_RTC_RTCA0ALW_RTCA0ALW3_Msk (0x8UL) /*!< RTCA0ALW3 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW4_Pos (4UL) /*!< RTCA0ALW4 (Bit 4) */ + #define R_RTC_RTCA0ALW_RTCA0ALW4_Msk (0x10UL) /*!< RTCA0ALW4 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW5_Pos (5UL) /*!< RTCA0ALW5 (Bit 5) */ + #define R_RTC_RTCA0ALW_RTCA0ALW5_Msk (0x20UL) /*!< RTCA0ALW5 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW6_Pos (6UL) /*!< RTCA0ALW6 (Bit 6) */ + #define R_RTC_RTCA0ALW_RTCA0ALW6_Msk (0x40UL) /*!< RTCA0ALW6 (Bitfield-Mask: 0x01) */ +/* ======================================================= RTCA0SECC ======================================================= */ + #define R_RTC_RTCA0SECC_RTCA0SECC_Pos (0UL) /*!< RTCA0SECC (Bit 0) */ + #define R_RTC_RTCA0SECC_RTCA0SECC_Msk (0x7fUL) /*!< RTCA0SECC (Bitfield-Mask: 0x7f) */ +/* ======================================================= RTCA0MINC ======================================================= */ + #define R_RTC_RTCA0MINC_RTCA0MINC_Pos (0UL) /*!< RTCA0MINC (Bit 0) */ + #define R_RTC_RTCA0MINC_RTCA0MINC_Msk (0x7fUL) /*!< RTCA0MINC (Bitfield-Mask: 0x7f) */ +/* ====================================================== RTCA0HOURC ======================================================= */ + #define R_RTC_RTCA0HOURC_RTCA0HOURC_Pos (0UL) /*!< RTCA0HOURC (Bit 0) */ + #define R_RTC_RTCA0HOURC_RTCA0HOURC_Msk (0x3fUL) /*!< RTCA0HOURC (Bitfield-Mask: 0x3f) */ +/* ====================================================== RTCA0WEEKC ======================================================= */ + #define R_RTC_RTCA0WEEKC_RTCA0WEEKC_Pos (0UL) /*!< RTCA0WEEKC (Bit 0) */ + #define R_RTC_RTCA0WEEKC_RTCA0WEEKC_Msk (0x7UL) /*!< RTCA0WEEKC (Bitfield-Mask: 0x07) */ +/* ======================================================= RTCA0DAYC ======================================================= */ + #define R_RTC_RTCA0DAYC_RTCA0DAYC_Pos (0UL) /*!< RTCA0DAYC (Bit 0) */ + #define R_RTC_RTCA0DAYC_RTCA0DAYC_Msk (0x3fUL) /*!< RTCA0DAYC (Bitfield-Mask: 0x3f) */ +/* ======================================================= RTCA0MONC ======================================================= */ + #define R_RTC_RTCA0MONC_RTCA0MONC_Pos (0UL) /*!< RTCA0MONC (Bit 0) */ + #define R_RTC_RTCA0MONC_RTCA0MONC_Msk (0x1fUL) /*!< RTCA0MONC (Bitfield-Mask: 0x1f) */ +/* ====================================================== RTCA0YEARC ======================================================= */ + #define R_RTC_RTCA0YEARC_RTCA0YEARC_Pos (0UL) /*!< RTCA0YEARC (Bit 0) */ + #define R_RTC_RTCA0YEARC_RTCA0YEARC_Msk (0xffUL) /*!< RTCA0YEARC (Bitfield-Mask: 0xff) */ +/* ====================================================== RTCA0TIMEC ======================================================= */ + #define R_RTC_RTCA0TIMEC_RTCA0SECC_Pos (0UL) /*!< RTCA0SECC (Bit 0) */ + #define R_RTC_RTCA0TIMEC_RTCA0SECC_Msk (0xffUL) /*!< RTCA0SECC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0TIMEC_RTCA0MINC_Pos (8UL) /*!< RTCA0MINC (Bit 8) */ + #define R_RTC_RTCA0TIMEC_RTCA0MINC_Msk (0xff00UL) /*!< RTCA0MINC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0TIMEC_RTCA0HOURC_Pos (16UL) /*!< RTCA0HOURC (Bit 16) */ + #define R_RTC_RTCA0TIMEC_RTCA0HOURC_Msk (0xff0000UL) /*!< RTCA0HOURC (Bitfield-Mask: 0xff) */ +/* ======================================================= RTCA0CALC ======================================================= */ + #define R_RTC_RTCA0CALC_RTCA0WEEKC_Pos (0UL) /*!< RTCA0WEEKC (Bit 0) */ + #define R_RTC_RTCA0CALC_RTCA0WEEKC_Msk (0xffUL) /*!< RTCA0WEEKC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CALC_RTCA0DAYC_Pos (8UL) /*!< RTCA0DAYC (Bit 8) */ + #define R_RTC_RTCA0CALC_RTCA0DAYC_Msk (0xff00UL) /*!< RTCA0DAYC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CALC_RTCA0MONC_Pos (16UL) /*!< RTCA0MONC (Bit 16) */ + #define R_RTC_RTCA0CALC_RTCA0MONC_Msk (0xff0000UL) /*!< RTCA0MONC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CALC_RTCA0YEARC_Pos (24UL) /*!< RTCA0YEARC (Bit 24) */ + #define R_RTC_RTCA0CALC_RTCA0YEARC_Msk (0xff000000UL) /*!< RTCA0YEARC (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG2 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== POEG2GA ======================================================== */ + #define R_POEG2_POEG2GA_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG2_POEG2GA_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG2_POEG2GA_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG2_POEG2GA_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG2_POEG2GA_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG2_POEG2GA_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG2_POEG2GA_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG2_POEG2GA_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG2_POEG2GA_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG2_POEG2GA_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG2_POEG2GA_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG2_POEG2GA_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG2GB ======================================================== */ + #define R_POEG2_POEG2GB_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG2_POEG2GB_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG2_POEG2GB_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG2_POEG2GB_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG2_POEG2GB_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG2_POEG2GB_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG2_POEG2GB_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG2_POEG2GB_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG2_POEG2GB_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG2_POEG2GB_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG2_POEG2GB_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG2_POEG2GB_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG2GC ======================================================== */ + #define R_POEG2_POEG2GC_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG2_POEG2GC_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG2_POEG2GC_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG2_POEG2GC_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG2_POEG2GC_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG2_POEG2GC_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG2_POEG2GC_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG2_POEG2GC_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG2_POEG2GC_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG2_POEG2GC_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG2_POEG2GC_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG2_POEG2GC_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG2GD ======================================================== */ + #define R_POEG2_POEG2GD_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG2_POEG2GD_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG2_POEG2GD_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG2_POEG2GD_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG2_POEG2GD_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG2_POEG2GD_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG2_POEG2GD_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG2_POEG2GD_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG2_POEG2GD_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG2_POEG2GD_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG2_POEG2GD_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG2_POEG2GD_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_OTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== OTPPWR ========================================================= */ + #define R_OTP_OTPPWR_PWR_Pos (0UL) /*!< PWR (Bit 0) */ + #define R_OTP_OTPPWR_PWR_Msk (0x1UL) /*!< PWR (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPPWR_ACCL_Pos (4UL) /*!< ACCL (Bit 4) */ + #define R_OTP_OTPPWR_ACCL_Msk (0x10UL) /*!< ACCL (Bitfield-Mask: 0x01) */ +/* ======================================================== OTPSTR ========================================================= */ + #define R_OTP_OTPSTR_CMD_RDY_Pos (0UL) /*!< CMD_RDY (Bit 0) */ + #define R_OTP_OTPSTR_CMD_RDY_Msk (0x1UL) /*!< CMD_RDY (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPSTR_ERR_WR_Pos (1UL) /*!< ERR_WR (Bit 1) */ + #define R_OTP_OTPSTR_ERR_WR_Msk (0x6UL) /*!< ERR_WR (Bitfield-Mask: 0x03) */ + #define R_OTP_OTPSTR_ERR_WP_Pos (3UL) /*!< ERR_WP (Bit 3) */ + #define R_OTP_OTPSTR_ERR_WP_Msk (0x8UL) /*!< ERR_WP (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPSTR_ERR_RP_Pos (4UL) /*!< ERR_RP (Bit 4) */ + #define R_OTP_OTPSTR_ERR_RP_Msk (0x10UL) /*!< ERR_RP (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPSTR_ERR_RDY_WR_Pos (8UL) /*!< ERR_RDY_WR (Bit 8) */ + #define R_OTP_OTPSTR_ERR_RDY_WR_Msk (0x100UL) /*!< ERR_RDY_WR (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPSTR_ERR_RDY_RD_Pos (9UL) /*!< ERR_RDY_RD (Bit 9) */ + #define R_OTP_OTPSTR_ERR_RDY_RD_Msk (0x200UL) /*!< ERR_RDY_RD (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPSTR_CNT_ST_IDLE_Pos (15UL) /*!< CNT_ST_IDLE (Bit 15) */ + #define R_OTP_OTPSTR_CNT_ST_IDLE_Msk (0x8000UL) /*!< CNT_ST_IDLE (Bitfield-Mask: 0x01) */ +/* ======================================================= OTPSTAWR ======================================================== */ + #define R_OTP_OTPSTAWR_STAWR_Pos (0UL) /*!< STAWR (Bit 0) */ + #define R_OTP_OTPSTAWR_STAWR_Msk (0x1UL) /*!< STAWR (Bitfield-Mask: 0x01) */ +/* ======================================================= OTPADRWR ======================================================== */ + #define R_OTP_OTPADRWR_ADRWR_Pos (0UL) /*!< ADRWR (Bit 0) */ + #define R_OTP_OTPADRWR_ADRWR_Msk (0x1ffUL) /*!< ADRWR (Bitfield-Mask: 0x1ff) */ +/* ======================================================= OTPDATAWR ======================================================= */ + #define R_OTP_OTPDATAWR_DATAWR_Pos (0UL) /*!< DATAWR (Bit 0) */ + #define R_OTP_OTPDATAWR_DATAWR_Msk (0xffffUL) /*!< DATAWR (Bitfield-Mask: 0xffff) */ +/* ======================================================= OTPADRRD ======================================================== */ + #define R_OTP_OTPADRRD_ADRRD_Pos (0UL) /*!< ADRRD (Bit 0) */ + #define R_OTP_OTPADRRD_ADRRD_Msk (0x1ffUL) /*!< ADRRD (Bitfield-Mask: 0x1ff) */ +/* ======================================================= OTPDATARD ======================================================= */ + #define R_OTP_OTPDATARD_DATARD_Pos (0UL) /*!< DATARD (Bit 0) */ + #define R_OTP_OTPDATARD_DATARD_Msk (0xffffUL) /*!< DATARD (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_PTADR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSELP ========================================================= */ + #define R_PTADR_RSELP_RS0_Pos (0UL) /*!< RS0 (Bit 0) */ + #define R_PTADR_RSELP_RS0_Msk (0x1UL) /*!< RS0 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS1_Pos (1UL) /*!< RS1 (Bit 1) */ + #define R_PTADR_RSELP_RS1_Msk (0x2UL) /*!< RS1 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS2_Pos (2UL) /*!< RS2 (Bit 2) */ + #define R_PTADR_RSELP_RS2_Msk (0x4UL) /*!< RS2 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS3_Pos (3UL) /*!< RS3 (Bit 3) */ + #define R_PTADR_RSELP_RS3_Msk (0x8UL) /*!< RS3 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS4_Pos (4UL) /*!< RS4 (Bit 4) */ + #define R_PTADR_RSELP_RS4_Msk (0x10UL) /*!< RS4 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS5_Pos (5UL) /*!< RS5 (Bit 5) */ + #define R_PTADR_RSELP_RS5_Msk (0x20UL) /*!< RS5 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS6_Pos (6UL) /*!< RS6 (Bit 6) */ + #define R_PTADR_RSELP_RS6_Msk (0x40UL) /*!< RS6 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS7_Pos (7UL) /*!< RS7 (Bit 7) */ + #define R_PTADR_RSELP_RS7_Msk (0x80UL) /*!< RS7 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSRAM0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== S_SWINT ======================================================== */ + #define R_ICU_S_SWINT_IC6_Pos (0UL) /*!< IC6 (Bit 0) */ + #define R_ICU_S_SWINT_IC6_Msk (0x1UL) /*!< IC6 (Bitfield-Mask: 0x01) */ + #define R_ICU_S_SWINT_IC7_Pos (1UL) /*!< IC7 (Bit 1) */ + #define R_ICU_S_SWINT_IC7_Msk (0x2UL) /*!< IC7 (Bitfield-Mask: 0x01) */ +/* ==================================================== S_PORTNF_FLTSEL ==================================================== */ + #define R_ICU_S_PORTNF_FLTSEL_FLT14_Pos (0UL) /*!< FLT14 (Bit 0) */ + #define R_ICU_S_PORTNF_FLTSEL_FLT14_Msk (0x1UL) /*!< FLT14 (Bitfield-Mask: 0x01) */ + #define R_ICU_S_PORTNF_FLTSEL_FLT15_Pos (1UL) /*!< FLT15 (Bit 1) */ + #define R_ICU_S_PORTNF_FLTSEL_FLT15_Msk (0x2UL) /*!< FLT15 (Bitfield-Mask: 0x01) */ + #define R_ICU_S_PORTNF_FLTSEL_FLTNMI_Pos (2UL) /*!< FLTNMI (Bit 2) */ + #define R_ICU_S_PORTNF_FLTSEL_FLTNMI_Msk (0x4UL) /*!< FLTNMI (Bitfield-Mask: 0x01) */ +/* ==================================================== S_PORTNF_CLKSEL ==================================================== */ + #define R_ICU_S_PORTNF_CLKSEL_CKSEL14_Pos (0UL) /*!< CKSEL14 (Bit 0) */ + #define R_ICU_S_PORTNF_CLKSEL_CKSEL14_Msk (0x3UL) /*!< CKSEL14 (Bitfield-Mask: 0x03) */ + #define R_ICU_S_PORTNF_CLKSEL_CKSEL15_Pos (2UL) /*!< CKSEL15 (Bit 2) */ + #define R_ICU_S_PORTNF_CLKSEL_CKSEL15_Msk (0xcUL) /*!< CKSEL15 (Bitfield-Mask: 0x03) */ + #define R_ICU_S_PORTNF_CLKSEL_CKSELNMI_Pos (4UL) /*!< CKSELNMI (Bit 4) */ + #define R_ICU_S_PORTNF_CLKSEL_CKSELNMI_Msk (0x30UL) /*!< CKSELNMI (Bitfield-Mask: 0x03) */ +/* ====================================================== S_PORTNF_MD ====================================================== */ + #define R_ICU_S_PORTNF_MD_MD14_Pos (0UL) /*!< MD14 (Bit 0) */ + #define R_ICU_S_PORTNF_MD_MD14_Msk (0x3UL) /*!< MD14 (Bitfield-Mask: 0x03) */ + #define R_ICU_S_PORTNF_MD_MD15_Pos (2UL) /*!< MD15 (Bit 2) */ + #define R_ICU_S_PORTNF_MD_MD15_Msk (0xcUL) /*!< MD15 (Bitfield-Mask: 0x03) */ + #define R_ICU_S_PORTNF_MD_MDNMI_Pos (4UL) /*!< MDNMI (Bit 4) */ + #define R_ICU_S_PORTNF_MD_MDNMI_Msk (0x30UL) /*!< MDNMI (Bitfield-Mask: 0x03) */ +/* ===================================================== CPU0ERR_STAT ====================================================== */ + #define R_ICU_CPU0ERR_STAT_ER_ST0_Pos (0UL) /*!< ER_ST0 (Bit 0) */ + #define R_ICU_CPU0ERR_STAT_ER_ST0_Msk (0x1UL) /*!< ER_ST0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST1_Pos (1UL) /*!< ER_ST1 (Bit 1) */ + #define R_ICU_CPU0ERR_STAT_ER_ST1_Msk (0x2UL) /*!< ER_ST1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST2_Pos (2UL) /*!< ER_ST2 (Bit 2) */ + #define R_ICU_CPU0ERR_STAT_ER_ST2_Msk (0x4UL) /*!< ER_ST2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST3_Pos (3UL) /*!< ER_ST3 (Bit 3) */ + #define R_ICU_CPU0ERR_STAT_ER_ST3_Msk (0x8UL) /*!< ER_ST3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST4_Pos (4UL) /*!< ER_ST4 (Bit 4) */ + #define R_ICU_CPU0ERR_STAT_ER_ST4_Msk (0x10UL) /*!< ER_ST4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST5_Pos (5UL) /*!< ER_ST5 (Bit 5) */ + #define R_ICU_CPU0ERR_STAT_ER_ST5_Msk (0x20UL) /*!< ER_ST5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST6_Pos (6UL) /*!< ER_ST6 (Bit 6) */ + #define R_ICU_CPU0ERR_STAT_ER_ST6_Msk (0x40UL) /*!< ER_ST6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST7_Pos (7UL) /*!< ER_ST7 (Bit 7) */ + #define R_ICU_CPU0ERR_STAT_ER_ST7_Msk (0x80UL) /*!< ER_ST7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST8_Pos (8UL) /*!< ER_ST8 (Bit 8) */ + #define R_ICU_CPU0ERR_STAT_ER_ST8_Msk (0x100UL) /*!< ER_ST8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST9_Pos (9UL) /*!< ER_ST9 (Bit 9) */ + #define R_ICU_CPU0ERR_STAT_ER_ST9_Msk (0x200UL) /*!< ER_ST9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST10_Pos (10UL) /*!< ER_ST10 (Bit 10) */ + #define R_ICU_CPU0ERR_STAT_ER_ST10_Msk (0x400UL) /*!< ER_ST10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST11_Pos (11UL) /*!< ER_ST11 (Bit 11) */ + #define R_ICU_CPU0ERR_STAT_ER_ST11_Msk (0x800UL) /*!< ER_ST11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST12_Pos (12UL) /*!< ER_ST12 (Bit 12) */ + #define R_ICU_CPU0ERR_STAT_ER_ST12_Msk (0x1000UL) /*!< ER_ST12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST13_Pos (13UL) /*!< ER_ST13 (Bit 13) */ + #define R_ICU_CPU0ERR_STAT_ER_ST13_Msk (0x2000UL) /*!< ER_ST13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST14_Pos (14UL) /*!< ER_ST14 (Bit 14) */ + #define R_ICU_CPU0ERR_STAT_ER_ST14_Msk (0x4000UL) /*!< ER_ST14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST15_Pos (15UL) /*!< ER_ST15 (Bit 15) */ + #define R_ICU_CPU0ERR_STAT_ER_ST15_Msk (0x8000UL) /*!< ER_ST15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST16_Pos (16UL) /*!< ER_ST16 (Bit 16) */ + #define R_ICU_CPU0ERR_STAT_ER_ST16_Msk (0x10000UL) /*!< ER_ST16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST17_Pos (17UL) /*!< ER_ST17 (Bit 17) */ + #define R_ICU_CPU0ERR_STAT_ER_ST17_Msk (0x20000UL) /*!< ER_ST17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST18_Pos (18UL) /*!< ER_ST18 (Bit 18) */ + #define R_ICU_CPU0ERR_STAT_ER_ST18_Msk (0x40000UL) /*!< ER_ST18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST19_Pos (19UL) /*!< ER_ST19 (Bit 19) */ + #define R_ICU_CPU0ERR_STAT_ER_ST19_Msk (0x80000UL) /*!< ER_ST19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST20_Pos (20UL) /*!< ER_ST20 (Bit 20) */ + #define R_ICU_CPU0ERR_STAT_ER_ST20_Msk (0x100000UL) /*!< ER_ST20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST21_Pos (21UL) /*!< ER_ST21 (Bit 21) */ + #define R_ICU_CPU0ERR_STAT_ER_ST21_Msk (0x200000UL) /*!< ER_ST21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST22_Pos (22UL) /*!< ER_ST22 (Bit 22) */ + #define R_ICU_CPU0ERR_STAT_ER_ST22_Msk (0x400000UL) /*!< ER_ST22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST23_Pos (23UL) /*!< ER_ST23 (Bit 23) */ + #define R_ICU_CPU0ERR_STAT_ER_ST23_Msk (0x800000UL) /*!< ER_ST23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST24_Pos (24UL) /*!< ER_ST24 (Bit 24) */ + #define R_ICU_CPU0ERR_STAT_ER_ST24_Msk (0x1000000UL) /*!< ER_ST24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST25_Pos (25UL) /*!< ER_ST25 (Bit 25) */ + #define R_ICU_CPU0ERR_STAT_ER_ST25_Msk (0x2000000UL) /*!< ER_ST25 (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU1ERR_STAT ====================================================== */ + #define R_ICU_CPU1ERR_STAT_ER_ST0_Pos (0UL) /*!< ER_ST0 (Bit 0) */ + #define R_ICU_CPU1ERR_STAT_ER_ST0_Msk (0x1UL) /*!< ER_ST0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST1_Pos (1UL) /*!< ER_ST1 (Bit 1) */ + #define R_ICU_CPU1ERR_STAT_ER_ST1_Msk (0x2UL) /*!< ER_ST1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST2_Pos (2UL) /*!< ER_ST2 (Bit 2) */ + #define R_ICU_CPU1ERR_STAT_ER_ST2_Msk (0x4UL) /*!< ER_ST2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST3_Pos (3UL) /*!< ER_ST3 (Bit 3) */ + #define R_ICU_CPU1ERR_STAT_ER_ST3_Msk (0x8UL) /*!< ER_ST3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST4_Pos (4UL) /*!< ER_ST4 (Bit 4) */ + #define R_ICU_CPU1ERR_STAT_ER_ST4_Msk (0x10UL) /*!< ER_ST4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST5_Pos (5UL) /*!< ER_ST5 (Bit 5) */ + #define R_ICU_CPU1ERR_STAT_ER_ST5_Msk (0x20UL) /*!< ER_ST5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST6_Pos (6UL) /*!< ER_ST6 (Bit 6) */ + #define R_ICU_CPU1ERR_STAT_ER_ST6_Msk (0x40UL) /*!< ER_ST6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST7_Pos (7UL) /*!< ER_ST7 (Bit 7) */ + #define R_ICU_CPU1ERR_STAT_ER_ST7_Msk (0x80UL) /*!< ER_ST7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST8_Pos (8UL) /*!< ER_ST8 (Bit 8) */ + #define R_ICU_CPU1ERR_STAT_ER_ST8_Msk (0x100UL) /*!< ER_ST8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST9_Pos (9UL) /*!< ER_ST9 (Bit 9) */ + #define R_ICU_CPU1ERR_STAT_ER_ST9_Msk (0x200UL) /*!< ER_ST9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST10_Pos (10UL) /*!< ER_ST10 (Bit 10) */ + #define R_ICU_CPU1ERR_STAT_ER_ST10_Msk (0x400UL) /*!< ER_ST10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST11_Pos (11UL) /*!< ER_ST11 (Bit 11) */ + #define R_ICU_CPU1ERR_STAT_ER_ST11_Msk (0x800UL) /*!< ER_ST11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST12_Pos (12UL) /*!< ER_ST12 (Bit 12) */ + #define R_ICU_CPU1ERR_STAT_ER_ST12_Msk (0x1000UL) /*!< ER_ST12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST13_Pos (13UL) /*!< ER_ST13 (Bit 13) */ + #define R_ICU_CPU1ERR_STAT_ER_ST13_Msk (0x2000UL) /*!< ER_ST13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST14_Pos (14UL) /*!< ER_ST14 (Bit 14) */ + #define R_ICU_CPU1ERR_STAT_ER_ST14_Msk (0x4000UL) /*!< ER_ST14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST15_Pos (15UL) /*!< ER_ST15 (Bit 15) */ + #define R_ICU_CPU1ERR_STAT_ER_ST15_Msk (0x8000UL) /*!< ER_ST15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST16_Pos (16UL) /*!< ER_ST16 (Bit 16) */ + #define R_ICU_CPU1ERR_STAT_ER_ST16_Msk (0x10000UL) /*!< ER_ST16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST17_Pos (17UL) /*!< ER_ST17 (Bit 17) */ + #define R_ICU_CPU1ERR_STAT_ER_ST17_Msk (0x20000UL) /*!< ER_ST17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST18_Pos (18UL) /*!< ER_ST18 (Bit 18) */ + #define R_ICU_CPU1ERR_STAT_ER_ST18_Msk (0x40000UL) /*!< ER_ST18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST19_Pos (19UL) /*!< ER_ST19 (Bit 19) */ + #define R_ICU_CPU1ERR_STAT_ER_ST19_Msk (0x80000UL) /*!< ER_ST19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST20_Pos (20UL) /*!< ER_ST20 (Bit 20) */ + #define R_ICU_CPU1ERR_STAT_ER_ST20_Msk (0x100000UL) /*!< ER_ST20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST21_Pos (21UL) /*!< ER_ST21 (Bit 21) */ + #define R_ICU_CPU1ERR_STAT_ER_ST21_Msk (0x200000UL) /*!< ER_ST21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST22_Pos (22UL) /*!< ER_ST22 (Bit 22) */ + #define R_ICU_CPU1ERR_STAT_ER_ST22_Msk (0x400000UL) /*!< ER_ST22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST23_Pos (23UL) /*!< ER_ST23 (Bit 23) */ + #define R_ICU_CPU1ERR_STAT_ER_ST23_Msk (0x800000UL) /*!< ER_ST23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST24_Pos (24UL) /*!< ER_ST24 (Bit 24) */ + #define R_ICU_CPU1ERR_STAT_ER_ST24_Msk (0x1000000UL) /*!< ER_ST24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_STAT_ER_ST25_Pos (25UL) /*!< ER_ST25 (Bit 25) */ + #define R_ICU_CPU1ERR_STAT_ER_ST25_Msk (0x2000000UL) /*!< ER_ST25 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_STAT0 ===================================================== */ + #define R_ICU_PERIERR_STAT0_ER_ST0_Pos (0UL) /*!< ER_ST0 (Bit 0) */ + #define R_ICU_PERIERR_STAT0_ER_ST0_Msk (0x1UL) /*!< ER_ST0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST1_Pos (1UL) /*!< ER_ST1 (Bit 1) */ + #define R_ICU_PERIERR_STAT0_ER_ST1_Msk (0x2UL) /*!< ER_ST1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST2_Pos (2UL) /*!< ER_ST2 (Bit 2) */ + #define R_ICU_PERIERR_STAT0_ER_ST2_Msk (0x4UL) /*!< ER_ST2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST3_Pos (3UL) /*!< ER_ST3 (Bit 3) */ + #define R_ICU_PERIERR_STAT0_ER_ST3_Msk (0x8UL) /*!< ER_ST3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST4_Pos (4UL) /*!< ER_ST4 (Bit 4) */ + #define R_ICU_PERIERR_STAT0_ER_ST4_Msk (0x10UL) /*!< ER_ST4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST5_Pos (5UL) /*!< ER_ST5 (Bit 5) */ + #define R_ICU_PERIERR_STAT0_ER_ST5_Msk (0x20UL) /*!< ER_ST5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST6_Pos (6UL) /*!< ER_ST6 (Bit 6) */ + #define R_ICU_PERIERR_STAT0_ER_ST6_Msk (0x40UL) /*!< ER_ST6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST7_Pos (7UL) /*!< ER_ST7 (Bit 7) */ + #define R_ICU_PERIERR_STAT0_ER_ST7_Msk (0x80UL) /*!< ER_ST7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST8_Pos (8UL) /*!< ER_ST8 (Bit 8) */ + #define R_ICU_PERIERR_STAT0_ER_ST8_Msk (0x100UL) /*!< ER_ST8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST9_Pos (9UL) /*!< ER_ST9 (Bit 9) */ + #define R_ICU_PERIERR_STAT0_ER_ST9_Msk (0x200UL) /*!< ER_ST9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST10_Pos (10UL) /*!< ER_ST10 (Bit 10) */ + #define R_ICU_PERIERR_STAT0_ER_ST10_Msk (0x400UL) /*!< ER_ST10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST11_Pos (11UL) /*!< ER_ST11 (Bit 11) */ + #define R_ICU_PERIERR_STAT0_ER_ST11_Msk (0x800UL) /*!< ER_ST11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST12_Pos (12UL) /*!< ER_ST12 (Bit 12) */ + #define R_ICU_PERIERR_STAT0_ER_ST12_Msk (0x1000UL) /*!< ER_ST12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST13_Pos (13UL) /*!< ER_ST13 (Bit 13) */ + #define R_ICU_PERIERR_STAT0_ER_ST13_Msk (0x2000UL) /*!< ER_ST13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST14_Pos (14UL) /*!< ER_ST14 (Bit 14) */ + #define R_ICU_PERIERR_STAT0_ER_ST14_Msk (0x4000UL) /*!< ER_ST14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST15_Pos (15UL) /*!< ER_ST15 (Bit 15) */ + #define R_ICU_PERIERR_STAT0_ER_ST15_Msk (0x8000UL) /*!< ER_ST15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST16_Pos (16UL) /*!< ER_ST16 (Bit 16) */ + #define R_ICU_PERIERR_STAT0_ER_ST16_Msk (0x10000UL) /*!< ER_ST16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST17_Pos (17UL) /*!< ER_ST17 (Bit 17) */ + #define R_ICU_PERIERR_STAT0_ER_ST17_Msk (0x20000UL) /*!< ER_ST17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST18_Pos (18UL) /*!< ER_ST18 (Bit 18) */ + #define R_ICU_PERIERR_STAT0_ER_ST18_Msk (0x40000UL) /*!< ER_ST18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST19_Pos (19UL) /*!< ER_ST19 (Bit 19) */ + #define R_ICU_PERIERR_STAT0_ER_ST19_Msk (0x80000UL) /*!< ER_ST19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST20_Pos (20UL) /*!< ER_ST20 (Bit 20) */ + #define R_ICU_PERIERR_STAT0_ER_ST20_Msk (0x100000UL) /*!< ER_ST20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST21_Pos (21UL) /*!< ER_ST21 (Bit 21) */ + #define R_ICU_PERIERR_STAT0_ER_ST21_Msk (0x200000UL) /*!< ER_ST21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST22_Pos (22UL) /*!< ER_ST22 (Bit 22) */ + #define R_ICU_PERIERR_STAT0_ER_ST22_Msk (0x400000UL) /*!< ER_ST22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST23_Pos (23UL) /*!< ER_ST23 (Bit 23) */ + #define R_ICU_PERIERR_STAT0_ER_ST23_Msk (0x800000UL) /*!< ER_ST23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST24_Pos (24UL) /*!< ER_ST24 (Bit 24) */ + #define R_ICU_PERIERR_STAT0_ER_ST24_Msk (0x1000000UL) /*!< ER_ST24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST25_Pos (25UL) /*!< ER_ST25 (Bit 25) */ + #define R_ICU_PERIERR_STAT0_ER_ST25_Msk (0x2000000UL) /*!< ER_ST25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST26_Pos (26UL) /*!< ER_ST26 (Bit 26) */ + #define R_ICU_PERIERR_STAT0_ER_ST26_Msk (0x4000000UL) /*!< ER_ST26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST27_Pos (27UL) /*!< ER_ST27 (Bit 27) */ + #define R_ICU_PERIERR_STAT0_ER_ST27_Msk (0x8000000UL) /*!< ER_ST27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST28_Pos (28UL) /*!< ER_ST28 (Bit 28) */ + #define R_ICU_PERIERR_STAT0_ER_ST28_Msk (0x10000000UL) /*!< ER_ST28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST29_Pos (29UL) /*!< ER_ST29 (Bit 29) */ + #define R_ICU_PERIERR_STAT0_ER_ST29_Msk (0x20000000UL) /*!< ER_ST29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST30_Pos (30UL) /*!< ER_ST30 (Bit 30) */ + #define R_ICU_PERIERR_STAT0_ER_ST30_Msk (0x40000000UL) /*!< ER_ST30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST31_Pos (31UL) /*!< ER_ST31 (Bit 31) */ + #define R_ICU_PERIERR_STAT0_ER_ST31_Msk (0x80000000UL) /*!< ER_ST31 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_STAT1 ===================================================== */ + #define R_ICU_PERIERR_STAT1_ER_ST0_Pos (0UL) /*!< ER_ST0 (Bit 0) */ + #define R_ICU_PERIERR_STAT1_ER_ST0_Msk (0x1UL) /*!< ER_ST0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST1_Pos (1UL) /*!< ER_ST1 (Bit 1) */ + #define R_ICU_PERIERR_STAT1_ER_ST1_Msk (0x2UL) /*!< ER_ST1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST2_Pos (2UL) /*!< ER_ST2 (Bit 2) */ + #define R_ICU_PERIERR_STAT1_ER_ST2_Msk (0x4UL) /*!< ER_ST2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST3_Pos (3UL) /*!< ER_ST3 (Bit 3) */ + #define R_ICU_PERIERR_STAT1_ER_ST3_Msk (0x8UL) /*!< ER_ST3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST4_Pos (4UL) /*!< ER_ST4 (Bit 4) */ + #define R_ICU_PERIERR_STAT1_ER_ST4_Msk (0x10UL) /*!< ER_ST4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST5_Pos (5UL) /*!< ER_ST5 (Bit 5) */ + #define R_ICU_PERIERR_STAT1_ER_ST5_Msk (0x20UL) /*!< ER_ST5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST6_Pos (6UL) /*!< ER_ST6 (Bit 6) */ + #define R_ICU_PERIERR_STAT1_ER_ST6_Msk (0x40UL) /*!< ER_ST6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST7_Pos (7UL) /*!< ER_ST7 (Bit 7) */ + #define R_ICU_PERIERR_STAT1_ER_ST7_Msk (0x80UL) /*!< ER_ST7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST8_Pos (8UL) /*!< ER_ST8 (Bit 8) */ + #define R_ICU_PERIERR_STAT1_ER_ST8_Msk (0x100UL) /*!< ER_ST8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST9_Pos (9UL) /*!< ER_ST9 (Bit 9) */ + #define R_ICU_PERIERR_STAT1_ER_ST9_Msk (0x200UL) /*!< ER_ST9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST10_Pos (10UL) /*!< ER_ST10 (Bit 10) */ + #define R_ICU_PERIERR_STAT1_ER_ST10_Msk (0x400UL) /*!< ER_ST10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST11_Pos (11UL) /*!< ER_ST11 (Bit 11) */ + #define R_ICU_PERIERR_STAT1_ER_ST11_Msk (0x800UL) /*!< ER_ST11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST12_Pos (12UL) /*!< ER_ST12 (Bit 12) */ + #define R_ICU_PERIERR_STAT1_ER_ST12_Msk (0x1000UL) /*!< ER_ST12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST13_Pos (13UL) /*!< ER_ST13 (Bit 13) */ + #define R_ICU_PERIERR_STAT1_ER_ST13_Msk (0x2000UL) /*!< ER_ST13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST14_Pos (14UL) /*!< ER_ST14 (Bit 14) */ + #define R_ICU_PERIERR_STAT1_ER_ST14_Msk (0x4000UL) /*!< ER_ST14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST15_Pos (15UL) /*!< ER_ST15 (Bit 15) */ + #define R_ICU_PERIERR_STAT1_ER_ST15_Msk (0x8000UL) /*!< ER_ST15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST16_Pos (16UL) /*!< ER_ST16 (Bit 16) */ + #define R_ICU_PERIERR_STAT1_ER_ST16_Msk (0x10000UL) /*!< ER_ST16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST17_Pos (17UL) /*!< ER_ST17 (Bit 17) */ + #define R_ICU_PERIERR_STAT1_ER_ST17_Msk (0x20000UL) /*!< ER_ST17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST18_Pos (18UL) /*!< ER_ST18 (Bit 18) */ + #define R_ICU_PERIERR_STAT1_ER_ST18_Msk (0x40000UL) /*!< ER_ST18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST19_Pos (19UL) /*!< ER_ST19 (Bit 19) */ + #define R_ICU_PERIERR_STAT1_ER_ST19_Msk (0x80000UL) /*!< ER_ST19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST20_Pos (20UL) /*!< ER_ST20 (Bit 20) */ + #define R_ICU_PERIERR_STAT1_ER_ST20_Msk (0x100000UL) /*!< ER_ST20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST21_Pos (21UL) /*!< ER_ST21 (Bit 21) */ + #define R_ICU_PERIERR_STAT1_ER_ST21_Msk (0x200000UL) /*!< ER_ST21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST22_Pos (22UL) /*!< ER_ST22 (Bit 22) */ + #define R_ICU_PERIERR_STAT1_ER_ST22_Msk (0x400000UL) /*!< ER_ST22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST23_Pos (23UL) /*!< ER_ST23 (Bit 23) */ + #define R_ICU_PERIERR_STAT1_ER_ST23_Msk (0x800000UL) /*!< ER_ST23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST24_Pos (24UL) /*!< ER_ST24 (Bit 24) */ + #define R_ICU_PERIERR_STAT1_ER_ST24_Msk (0x1000000UL) /*!< ER_ST24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST27_Pos (27UL) /*!< ER_ST27 (Bit 27) */ + #define R_ICU_PERIERR_STAT1_ER_ST27_Msk (0x8000000UL) /*!< ER_ST27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST28_Pos (28UL) /*!< ER_ST28 (Bit 28) */ + #define R_ICU_PERIERR_STAT1_ER_ST28_Msk (0x10000000UL) /*!< ER_ST28 (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU0ERR_CLR ====================================================== */ + #define R_ICU_CPU0ERR_CLR_ER_CL0_Pos (0UL) /*!< ER_CL0 (Bit 0) */ + #define R_ICU_CPU0ERR_CLR_ER_CL0_Msk (0x1UL) /*!< ER_CL0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL1_Pos (1UL) /*!< ER_CL1 (Bit 1) */ + #define R_ICU_CPU0ERR_CLR_ER_CL1_Msk (0x2UL) /*!< ER_CL1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL2_Pos (2UL) /*!< ER_CL2 (Bit 2) */ + #define R_ICU_CPU0ERR_CLR_ER_CL2_Msk (0x4UL) /*!< ER_CL2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL3_Pos (3UL) /*!< ER_CL3 (Bit 3) */ + #define R_ICU_CPU0ERR_CLR_ER_CL3_Msk (0x8UL) /*!< ER_CL3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL4_Pos (4UL) /*!< ER_CL4 (Bit 4) */ + #define R_ICU_CPU0ERR_CLR_ER_CL4_Msk (0x10UL) /*!< ER_CL4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL5_Pos (5UL) /*!< ER_CL5 (Bit 5) */ + #define R_ICU_CPU0ERR_CLR_ER_CL5_Msk (0x20UL) /*!< ER_CL5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL6_Pos (6UL) /*!< ER_CL6 (Bit 6) */ + #define R_ICU_CPU0ERR_CLR_ER_CL6_Msk (0x40UL) /*!< ER_CL6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL7_Pos (7UL) /*!< ER_CL7 (Bit 7) */ + #define R_ICU_CPU0ERR_CLR_ER_CL7_Msk (0x80UL) /*!< ER_CL7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL8_Pos (8UL) /*!< ER_CL8 (Bit 8) */ + #define R_ICU_CPU0ERR_CLR_ER_CL8_Msk (0x100UL) /*!< ER_CL8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL9_Pos (9UL) /*!< ER_CL9 (Bit 9) */ + #define R_ICU_CPU0ERR_CLR_ER_CL9_Msk (0x200UL) /*!< ER_CL9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL10_Pos (10UL) /*!< ER_CL10 (Bit 10) */ + #define R_ICU_CPU0ERR_CLR_ER_CL10_Msk (0x400UL) /*!< ER_CL10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL11_Pos (11UL) /*!< ER_CL11 (Bit 11) */ + #define R_ICU_CPU0ERR_CLR_ER_CL11_Msk (0x800UL) /*!< ER_CL11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL12_Pos (12UL) /*!< ER_CL12 (Bit 12) */ + #define R_ICU_CPU0ERR_CLR_ER_CL12_Msk (0x1000UL) /*!< ER_CL12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL13_Pos (13UL) /*!< ER_CL13 (Bit 13) */ + #define R_ICU_CPU0ERR_CLR_ER_CL13_Msk (0x2000UL) /*!< ER_CL13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL14_Pos (14UL) /*!< ER_CL14 (Bit 14) */ + #define R_ICU_CPU0ERR_CLR_ER_CL14_Msk (0x4000UL) /*!< ER_CL14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL15_Pos (15UL) /*!< ER_CL15 (Bit 15) */ + #define R_ICU_CPU0ERR_CLR_ER_CL15_Msk (0x8000UL) /*!< ER_CL15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL16_Pos (16UL) /*!< ER_CL16 (Bit 16) */ + #define R_ICU_CPU0ERR_CLR_ER_CL16_Msk (0x10000UL) /*!< ER_CL16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL17_Pos (17UL) /*!< ER_CL17 (Bit 17) */ + #define R_ICU_CPU0ERR_CLR_ER_CL17_Msk (0x20000UL) /*!< ER_CL17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL18_Pos (18UL) /*!< ER_CL18 (Bit 18) */ + #define R_ICU_CPU0ERR_CLR_ER_CL18_Msk (0x40000UL) /*!< ER_CL18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL19_Pos (19UL) /*!< ER_CL19 (Bit 19) */ + #define R_ICU_CPU0ERR_CLR_ER_CL19_Msk (0x80000UL) /*!< ER_CL19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL20_Pos (20UL) /*!< ER_CL20 (Bit 20) */ + #define R_ICU_CPU0ERR_CLR_ER_CL20_Msk (0x100000UL) /*!< ER_CL20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL21_Pos (21UL) /*!< ER_CL21 (Bit 21) */ + #define R_ICU_CPU0ERR_CLR_ER_CL21_Msk (0x200000UL) /*!< ER_CL21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL22_Pos (22UL) /*!< ER_CL22 (Bit 22) */ + #define R_ICU_CPU0ERR_CLR_ER_CL22_Msk (0x400000UL) /*!< ER_CL22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL23_Pos (23UL) /*!< ER_CL23 (Bit 23) */ + #define R_ICU_CPU0ERR_CLR_ER_CL23_Msk (0x800000UL) /*!< ER_CL23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL24_Pos (24UL) /*!< ER_CL24 (Bit 24) */ + #define R_ICU_CPU0ERR_CLR_ER_CL24_Msk (0x1000000UL) /*!< ER_CL24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL25_Pos (25UL) /*!< ER_CL25 (Bit 25) */ + #define R_ICU_CPU0ERR_CLR_ER_CL25_Msk (0x2000000UL) /*!< ER_CL25 (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU1ERR_CLR ====================================================== */ + #define R_ICU_CPU1ERR_CLR_ER_CL0_Pos (0UL) /*!< ER_CL0 (Bit 0) */ + #define R_ICU_CPU1ERR_CLR_ER_CL0_Msk (0x1UL) /*!< ER_CL0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL1_Pos (1UL) /*!< ER_CL1 (Bit 1) */ + #define R_ICU_CPU1ERR_CLR_ER_CL1_Msk (0x2UL) /*!< ER_CL1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL2_Pos (2UL) /*!< ER_CL2 (Bit 2) */ + #define R_ICU_CPU1ERR_CLR_ER_CL2_Msk (0x4UL) /*!< ER_CL2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL3_Pos (3UL) /*!< ER_CL3 (Bit 3) */ + #define R_ICU_CPU1ERR_CLR_ER_CL3_Msk (0x8UL) /*!< ER_CL3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL4_Pos (4UL) /*!< ER_CL4 (Bit 4) */ + #define R_ICU_CPU1ERR_CLR_ER_CL4_Msk (0x10UL) /*!< ER_CL4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL5_Pos (5UL) /*!< ER_CL5 (Bit 5) */ + #define R_ICU_CPU1ERR_CLR_ER_CL5_Msk (0x20UL) /*!< ER_CL5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL6_Pos (6UL) /*!< ER_CL6 (Bit 6) */ + #define R_ICU_CPU1ERR_CLR_ER_CL6_Msk (0x40UL) /*!< ER_CL6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL7_Pos (7UL) /*!< ER_CL7 (Bit 7) */ + #define R_ICU_CPU1ERR_CLR_ER_CL7_Msk (0x80UL) /*!< ER_CL7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL8_Pos (8UL) /*!< ER_CL8 (Bit 8) */ + #define R_ICU_CPU1ERR_CLR_ER_CL8_Msk (0x100UL) /*!< ER_CL8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL9_Pos (9UL) /*!< ER_CL9 (Bit 9) */ + #define R_ICU_CPU1ERR_CLR_ER_CL9_Msk (0x200UL) /*!< ER_CL9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL10_Pos (10UL) /*!< ER_CL10 (Bit 10) */ + #define R_ICU_CPU1ERR_CLR_ER_CL10_Msk (0x400UL) /*!< ER_CL10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL11_Pos (11UL) /*!< ER_CL11 (Bit 11) */ + #define R_ICU_CPU1ERR_CLR_ER_CL11_Msk (0x800UL) /*!< ER_CL11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL12_Pos (12UL) /*!< ER_CL12 (Bit 12) */ + #define R_ICU_CPU1ERR_CLR_ER_CL12_Msk (0x1000UL) /*!< ER_CL12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL13_Pos (13UL) /*!< ER_CL13 (Bit 13) */ + #define R_ICU_CPU1ERR_CLR_ER_CL13_Msk (0x2000UL) /*!< ER_CL13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL14_Pos (14UL) /*!< ER_CL14 (Bit 14) */ + #define R_ICU_CPU1ERR_CLR_ER_CL14_Msk (0x4000UL) /*!< ER_CL14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL15_Pos (15UL) /*!< ER_CL15 (Bit 15) */ + #define R_ICU_CPU1ERR_CLR_ER_CL15_Msk (0x8000UL) /*!< ER_CL15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL16_Pos (16UL) /*!< ER_CL16 (Bit 16) */ + #define R_ICU_CPU1ERR_CLR_ER_CL16_Msk (0x10000UL) /*!< ER_CL16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL17_Pos (17UL) /*!< ER_CL17 (Bit 17) */ + #define R_ICU_CPU1ERR_CLR_ER_CL17_Msk (0x20000UL) /*!< ER_CL17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL18_Pos (18UL) /*!< ER_CL18 (Bit 18) */ + #define R_ICU_CPU1ERR_CLR_ER_CL18_Msk (0x40000UL) /*!< ER_CL18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL19_Pos (19UL) /*!< ER_CL19 (Bit 19) */ + #define R_ICU_CPU1ERR_CLR_ER_CL19_Msk (0x80000UL) /*!< ER_CL19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL20_Pos (20UL) /*!< ER_CL20 (Bit 20) */ + #define R_ICU_CPU1ERR_CLR_ER_CL20_Msk (0x100000UL) /*!< ER_CL20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL21_Pos (21UL) /*!< ER_CL21 (Bit 21) */ + #define R_ICU_CPU1ERR_CLR_ER_CL21_Msk (0x200000UL) /*!< ER_CL21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL22_Pos (22UL) /*!< ER_CL22 (Bit 22) */ + #define R_ICU_CPU1ERR_CLR_ER_CL22_Msk (0x400000UL) /*!< ER_CL22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL23_Pos (23UL) /*!< ER_CL23 (Bit 23) */ + #define R_ICU_CPU1ERR_CLR_ER_CL23_Msk (0x800000UL) /*!< ER_CL23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL24_Pos (24UL) /*!< ER_CL24 (Bit 24) */ + #define R_ICU_CPU1ERR_CLR_ER_CL24_Msk (0x1000000UL) /*!< ER_CL24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_CLR_ER_CL25_Pos (25UL) /*!< ER_CL25 (Bit 25) */ + #define R_ICU_CPU1ERR_CLR_ER_CL25_Msk (0x2000000UL) /*!< ER_CL25 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_CLR0 ====================================================== */ + #define R_ICU_PERIERR_CLR0_ER_CL0_Pos (0UL) /*!< ER_CL0 (Bit 0) */ + #define R_ICU_PERIERR_CLR0_ER_CL0_Msk (0x1UL) /*!< ER_CL0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL1_Pos (1UL) /*!< ER_CL1 (Bit 1) */ + #define R_ICU_PERIERR_CLR0_ER_CL1_Msk (0x2UL) /*!< ER_CL1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL2_Pos (2UL) /*!< ER_CL2 (Bit 2) */ + #define R_ICU_PERIERR_CLR0_ER_CL2_Msk (0x4UL) /*!< ER_CL2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL3_Pos (3UL) /*!< ER_CL3 (Bit 3) */ + #define R_ICU_PERIERR_CLR0_ER_CL3_Msk (0x8UL) /*!< ER_CL3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL4_Pos (4UL) /*!< ER_CL4 (Bit 4) */ + #define R_ICU_PERIERR_CLR0_ER_CL4_Msk (0x10UL) /*!< ER_CL4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL5_Pos (5UL) /*!< ER_CL5 (Bit 5) */ + #define R_ICU_PERIERR_CLR0_ER_CL5_Msk (0x20UL) /*!< ER_CL5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL6_Pos (6UL) /*!< ER_CL6 (Bit 6) */ + #define R_ICU_PERIERR_CLR0_ER_CL6_Msk (0x40UL) /*!< ER_CL6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL7_Pos (7UL) /*!< ER_CL7 (Bit 7) */ + #define R_ICU_PERIERR_CLR0_ER_CL7_Msk (0x80UL) /*!< ER_CL7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL8_Pos (8UL) /*!< ER_CL8 (Bit 8) */ + #define R_ICU_PERIERR_CLR0_ER_CL8_Msk (0x100UL) /*!< ER_CL8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL9_Pos (9UL) /*!< ER_CL9 (Bit 9) */ + #define R_ICU_PERIERR_CLR0_ER_CL9_Msk (0x200UL) /*!< ER_CL9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL10_Pos (10UL) /*!< ER_CL10 (Bit 10) */ + #define R_ICU_PERIERR_CLR0_ER_CL10_Msk (0x400UL) /*!< ER_CL10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL11_Pos (11UL) /*!< ER_CL11 (Bit 11) */ + #define R_ICU_PERIERR_CLR0_ER_CL11_Msk (0x800UL) /*!< ER_CL11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL12_Pos (12UL) /*!< ER_CL12 (Bit 12) */ + #define R_ICU_PERIERR_CLR0_ER_CL12_Msk (0x1000UL) /*!< ER_CL12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL13_Pos (13UL) /*!< ER_CL13 (Bit 13) */ + #define R_ICU_PERIERR_CLR0_ER_CL13_Msk (0x2000UL) /*!< ER_CL13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL14_Pos (14UL) /*!< ER_CL14 (Bit 14) */ + #define R_ICU_PERIERR_CLR0_ER_CL14_Msk (0x4000UL) /*!< ER_CL14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL15_Pos (15UL) /*!< ER_CL15 (Bit 15) */ + #define R_ICU_PERIERR_CLR0_ER_CL15_Msk (0x8000UL) /*!< ER_CL15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL16_Pos (16UL) /*!< ER_CL16 (Bit 16) */ + #define R_ICU_PERIERR_CLR0_ER_CL16_Msk (0x10000UL) /*!< ER_CL16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL17_Pos (17UL) /*!< ER_CL17 (Bit 17) */ + #define R_ICU_PERIERR_CLR0_ER_CL17_Msk (0x20000UL) /*!< ER_CL17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL18_Pos (18UL) /*!< ER_CL18 (Bit 18) */ + #define R_ICU_PERIERR_CLR0_ER_CL18_Msk (0x40000UL) /*!< ER_CL18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL19_Pos (19UL) /*!< ER_CL19 (Bit 19) */ + #define R_ICU_PERIERR_CLR0_ER_CL19_Msk (0x80000UL) /*!< ER_CL19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL20_Pos (20UL) /*!< ER_CL20 (Bit 20) */ + #define R_ICU_PERIERR_CLR0_ER_CL20_Msk (0x100000UL) /*!< ER_CL20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL21_Pos (21UL) /*!< ER_CL21 (Bit 21) */ + #define R_ICU_PERIERR_CLR0_ER_CL21_Msk (0x200000UL) /*!< ER_CL21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL22_Pos (22UL) /*!< ER_CL22 (Bit 22) */ + #define R_ICU_PERIERR_CLR0_ER_CL22_Msk (0x400000UL) /*!< ER_CL22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL23_Pos (23UL) /*!< ER_CL23 (Bit 23) */ + #define R_ICU_PERIERR_CLR0_ER_CL23_Msk (0x800000UL) /*!< ER_CL23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL24_Pos (24UL) /*!< ER_CL24 (Bit 24) */ + #define R_ICU_PERIERR_CLR0_ER_CL24_Msk (0x1000000UL) /*!< ER_CL24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL25_Pos (25UL) /*!< ER_CL25 (Bit 25) */ + #define R_ICU_PERIERR_CLR0_ER_CL25_Msk (0x2000000UL) /*!< ER_CL25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL26_Pos (26UL) /*!< ER_CL26 (Bit 26) */ + #define R_ICU_PERIERR_CLR0_ER_CL26_Msk (0x4000000UL) /*!< ER_CL26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL27_Pos (27UL) /*!< ER_CL27 (Bit 27) */ + #define R_ICU_PERIERR_CLR0_ER_CL27_Msk (0x8000000UL) /*!< ER_CL27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL28_Pos (28UL) /*!< ER_CL28 (Bit 28) */ + #define R_ICU_PERIERR_CLR0_ER_CL28_Msk (0x10000000UL) /*!< ER_CL28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL29_Pos (29UL) /*!< ER_CL29 (Bit 29) */ + #define R_ICU_PERIERR_CLR0_ER_CL29_Msk (0x20000000UL) /*!< ER_CL29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL30_Pos (30UL) /*!< ER_CL30 (Bit 30) */ + #define R_ICU_PERIERR_CLR0_ER_CL30_Msk (0x40000000UL) /*!< ER_CL30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL31_Pos (31UL) /*!< ER_CL31 (Bit 31) */ + #define R_ICU_PERIERR_CLR0_ER_CL31_Msk (0x80000000UL) /*!< ER_CL31 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_CLR1 ====================================================== */ + #define R_ICU_PERIERR_CLR1_ER_CL0_Pos (0UL) /*!< ER_CL0 (Bit 0) */ + #define R_ICU_PERIERR_CLR1_ER_CL0_Msk (0x1UL) /*!< ER_CL0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL1_Pos (1UL) /*!< ER_CL1 (Bit 1) */ + #define R_ICU_PERIERR_CLR1_ER_CL1_Msk (0x2UL) /*!< ER_CL1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL2_Pos (2UL) /*!< ER_CL2 (Bit 2) */ + #define R_ICU_PERIERR_CLR1_ER_CL2_Msk (0x4UL) /*!< ER_CL2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL3_Pos (3UL) /*!< ER_CL3 (Bit 3) */ + #define R_ICU_PERIERR_CLR1_ER_CL3_Msk (0x8UL) /*!< ER_CL3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL4_Pos (4UL) /*!< ER_CL4 (Bit 4) */ + #define R_ICU_PERIERR_CLR1_ER_CL4_Msk (0x10UL) /*!< ER_CL4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL5_Pos (5UL) /*!< ER_CL5 (Bit 5) */ + #define R_ICU_PERIERR_CLR1_ER_CL5_Msk (0x20UL) /*!< ER_CL5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL6_Pos (6UL) /*!< ER_CL6 (Bit 6) */ + #define R_ICU_PERIERR_CLR1_ER_CL6_Msk (0x40UL) /*!< ER_CL6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL7_Pos (7UL) /*!< ER_CL7 (Bit 7) */ + #define R_ICU_PERIERR_CLR1_ER_CL7_Msk (0x80UL) /*!< ER_CL7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL8_Pos (8UL) /*!< ER_CL8 (Bit 8) */ + #define R_ICU_PERIERR_CLR1_ER_CL8_Msk (0x100UL) /*!< ER_CL8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL9_Pos (9UL) /*!< ER_CL9 (Bit 9) */ + #define R_ICU_PERIERR_CLR1_ER_CL9_Msk (0x200UL) /*!< ER_CL9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL10_Pos (10UL) /*!< ER_CL10 (Bit 10) */ + #define R_ICU_PERIERR_CLR1_ER_CL10_Msk (0x400UL) /*!< ER_CL10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL11_Pos (11UL) /*!< ER_CL11 (Bit 11) */ + #define R_ICU_PERIERR_CLR1_ER_CL11_Msk (0x800UL) /*!< ER_CL11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL12_Pos (12UL) /*!< ER_CL12 (Bit 12) */ + #define R_ICU_PERIERR_CLR1_ER_CL12_Msk (0x1000UL) /*!< ER_CL12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL13_Pos (13UL) /*!< ER_CL13 (Bit 13) */ + #define R_ICU_PERIERR_CLR1_ER_CL13_Msk (0x2000UL) /*!< ER_CL13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL14_Pos (14UL) /*!< ER_CL14 (Bit 14) */ + #define R_ICU_PERIERR_CLR1_ER_CL14_Msk (0x4000UL) /*!< ER_CL14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL15_Pos (15UL) /*!< ER_CL15 (Bit 15) */ + #define R_ICU_PERIERR_CLR1_ER_CL15_Msk (0x8000UL) /*!< ER_CL15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL16_Pos (16UL) /*!< ER_CL16 (Bit 16) */ + #define R_ICU_PERIERR_CLR1_ER_CL16_Msk (0x10000UL) /*!< ER_CL16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL17_Pos (17UL) /*!< ER_CL17 (Bit 17) */ + #define R_ICU_PERIERR_CLR1_ER_CL17_Msk (0x20000UL) /*!< ER_CL17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL18_Pos (18UL) /*!< ER_CL18 (Bit 18) */ + #define R_ICU_PERIERR_CLR1_ER_CL18_Msk (0x40000UL) /*!< ER_CL18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL19_Pos (19UL) /*!< ER_CL19 (Bit 19) */ + #define R_ICU_PERIERR_CLR1_ER_CL19_Msk (0x80000UL) /*!< ER_CL19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL20_Pos (20UL) /*!< ER_CL20 (Bit 20) */ + #define R_ICU_PERIERR_CLR1_ER_CL20_Msk (0x100000UL) /*!< ER_CL20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL21_Pos (21UL) /*!< ER_CL21 (Bit 21) */ + #define R_ICU_PERIERR_CLR1_ER_CL21_Msk (0x200000UL) /*!< ER_CL21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL22_Pos (22UL) /*!< ER_CL22 (Bit 22) */ + #define R_ICU_PERIERR_CLR1_ER_CL22_Msk (0x400000UL) /*!< ER_CL22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL23_Pos (23UL) /*!< ER_CL23 (Bit 23) */ + #define R_ICU_PERIERR_CLR1_ER_CL23_Msk (0x800000UL) /*!< ER_CL23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL24_Pos (24UL) /*!< ER_CL24 (Bit 24) */ + #define R_ICU_PERIERR_CLR1_ER_CL24_Msk (0x1000000UL) /*!< ER_CL24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL27_Pos (27UL) /*!< ER_CL27 (Bit 27) */ + #define R_ICU_PERIERR_CLR1_ER_CL27_Msk (0x8000000UL) /*!< ER_CL27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL28_Pos (28UL) /*!< ER_CL28 (Bit 28) */ + #define R_ICU_PERIERR_CLR1_ER_CL28_Msk (0x10000000UL) /*!< ER_CL28 (Bitfield-Mask: 0x01) */ +/* ==================================================== CPU0ERR_RSTMSK ===================================================== */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK0_Pos (0UL) /*!< RS_MK0 (Bit 0) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK0_Msk (0x1UL) /*!< RS_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK1_Pos (1UL) /*!< RS_MK1 (Bit 1) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK1_Msk (0x2UL) /*!< RS_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK2_Pos (2UL) /*!< RS_MK2 (Bit 2) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK2_Msk (0x4UL) /*!< RS_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK3_Pos (3UL) /*!< RS_MK3 (Bit 3) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK3_Msk (0x8UL) /*!< RS_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK4_Pos (4UL) /*!< RS_MK4 (Bit 4) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK4_Msk (0x10UL) /*!< RS_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK5_Pos (5UL) /*!< RS_MK5 (Bit 5) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK5_Msk (0x20UL) /*!< RS_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK6_Pos (6UL) /*!< RS_MK6 (Bit 6) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK6_Msk (0x40UL) /*!< RS_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK7_Pos (7UL) /*!< RS_MK7 (Bit 7) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK7_Msk (0x80UL) /*!< RS_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK8_Pos (8UL) /*!< RS_MK8 (Bit 8) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK8_Msk (0x100UL) /*!< RS_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK9_Pos (9UL) /*!< RS_MK9 (Bit 9) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK9_Msk (0x200UL) /*!< RS_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK10_Pos (10UL) /*!< RS_MK10 (Bit 10) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK10_Msk (0x400UL) /*!< RS_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK11_Pos (11UL) /*!< RS_MK11 (Bit 11) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK11_Msk (0x800UL) /*!< RS_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK12_Pos (12UL) /*!< RS_MK12 (Bit 12) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK12_Msk (0x1000UL) /*!< RS_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK13_Pos (13UL) /*!< RS_MK13 (Bit 13) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK13_Msk (0x2000UL) /*!< RS_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK14_Pos (14UL) /*!< RS_MK14 (Bit 14) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK14_Msk (0x4000UL) /*!< RS_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK15_Pos (15UL) /*!< RS_MK15 (Bit 15) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK15_Msk (0x8000UL) /*!< RS_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK16_Pos (16UL) /*!< RS_MK16 (Bit 16) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK16_Msk (0x10000UL) /*!< RS_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK17_Pos (17UL) /*!< RS_MK17 (Bit 17) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK17_Msk (0x20000UL) /*!< RS_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK18_Pos (18UL) /*!< RS_MK18 (Bit 18) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK18_Msk (0x40000UL) /*!< RS_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK19_Pos (19UL) /*!< RS_MK19 (Bit 19) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK19_Msk (0x80000UL) /*!< RS_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK20_Pos (20UL) /*!< RS_MK20 (Bit 20) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK20_Msk (0x100000UL) /*!< RS_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK21_Pos (21UL) /*!< RS_MK21 (Bit 21) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK21_Msk (0x200000UL) /*!< RS_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK22_Pos (22UL) /*!< RS_MK22 (Bit 22) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK22_Msk (0x400000UL) /*!< RS_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK23_Pos (23UL) /*!< RS_MK23 (Bit 23) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK23_Msk (0x800000UL) /*!< RS_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK24_Pos (24UL) /*!< RS_MK24 (Bit 24) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK24_Msk (0x1000000UL) /*!< RS_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK25_Pos (25UL) /*!< RS_MK25 (Bit 25) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK25_Msk (0x2000000UL) /*!< RS_MK25 (Bitfield-Mask: 0x01) */ +/* ==================================================== CPU1ERR_RSTMSK ===================================================== */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK0_Pos (0UL) /*!< RS_MK0 (Bit 0) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK0_Msk (0x1UL) /*!< RS_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK1_Pos (1UL) /*!< RS_MK1 (Bit 1) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK1_Msk (0x2UL) /*!< RS_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK2_Pos (2UL) /*!< RS_MK2 (Bit 2) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK2_Msk (0x4UL) /*!< RS_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK3_Pos (3UL) /*!< RS_MK3 (Bit 3) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK3_Msk (0x8UL) /*!< RS_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK4_Pos (4UL) /*!< RS_MK4 (Bit 4) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK4_Msk (0x10UL) /*!< RS_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK5_Pos (5UL) /*!< RS_MK5 (Bit 5) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK5_Msk (0x20UL) /*!< RS_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK6_Pos (6UL) /*!< RS_MK6 (Bit 6) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK6_Msk (0x40UL) /*!< RS_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK7_Pos (7UL) /*!< RS_MK7 (Bit 7) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK7_Msk (0x80UL) /*!< RS_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK8_Pos (8UL) /*!< RS_MK8 (Bit 8) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK8_Msk (0x100UL) /*!< RS_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK9_Pos (9UL) /*!< RS_MK9 (Bit 9) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK9_Msk (0x200UL) /*!< RS_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK10_Pos (10UL) /*!< RS_MK10 (Bit 10) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK10_Msk (0x400UL) /*!< RS_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK11_Pos (11UL) /*!< RS_MK11 (Bit 11) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK11_Msk (0x800UL) /*!< RS_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK12_Pos (12UL) /*!< RS_MK12 (Bit 12) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK12_Msk (0x1000UL) /*!< RS_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK13_Pos (13UL) /*!< RS_MK13 (Bit 13) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK13_Msk (0x2000UL) /*!< RS_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK14_Pos (14UL) /*!< RS_MK14 (Bit 14) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK14_Msk (0x4000UL) /*!< RS_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK15_Pos (15UL) /*!< RS_MK15 (Bit 15) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK15_Msk (0x8000UL) /*!< RS_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK16_Pos (16UL) /*!< RS_MK16 (Bit 16) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK16_Msk (0x10000UL) /*!< RS_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK17_Pos (17UL) /*!< RS_MK17 (Bit 17) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK17_Msk (0x20000UL) /*!< RS_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK18_Pos (18UL) /*!< RS_MK18 (Bit 18) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK18_Msk (0x40000UL) /*!< RS_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK19_Pos (19UL) /*!< RS_MK19 (Bit 19) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK19_Msk (0x80000UL) /*!< RS_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK20_Pos (20UL) /*!< RS_MK20 (Bit 20) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK20_Msk (0x100000UL) /*!< RS_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK21_Pos (21UL) /*!< RS_MK21 (Bit 21) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK21_Msk (0x200000UL) /*!< RS_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK22_Pos (22UL) /*!< RS_MK22 (Bit 22) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK22_Msk (0x400000UL) /*!< RS_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK23_Pos (23UL) /*!< RS_MK23 (Bit 23) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK23_Msk (0x800000UL) /*!< RS_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK24_Pos (24UL) /*!< RS_MK24 (Bit 24) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK24_Msk (0x1000000UL) /*!< RS_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK25_Pos (25UL) /*!< RS_MK25 (Bit 25) */ + #define R_ICU_CPU1ERR_RSTMSK_RS_MK25_Msk (0x2000000UL) /*!< RS_MK25 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_RSTMSK0 ==================================================== */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK0_Pos (0UL) /*!< RS_MK0 (Bit 0) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK0_Msk (0x1UL) /*!< RS_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK1_Pos (1UL) /*!< RS_MK1 (Bit 1) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK1_Msk (0x2UL) /*!< RS_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK2_Pos (2UL) /*!< RS_MK2 (Bit 2) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK2_Msk (0x4UL) /*!< RS_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK3_Pos (3UL) /*!< RS_MK3 (Bit 3) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK3_Msk (0x8UL) /*!< RS_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK4_Pos (4UL) /*!< RS_MK4 (Bit 4) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK4_Msk (0x10UL) /*!< RS_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK5_Pos (5UL) /*!< RS_MK5 (Bit 5) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK5_Msk (0x20UL) /*!< RS_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK6_Pos (6UL) /*!< RS_MK6 (Bit 6) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK6_Msk (0x40UL) /*!< RS_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK7_Pos (7UL) /*!< RS_MK7 (Bit 7) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK7_Msk (0x80UL) /*!< RS_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK8_Pos (8UL) /*!< RS_MK8 (Bit 8) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK8_Msk (0x100UL) /*!< RS_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK9_Pos (9UL) /*!< RS_MK9 (Bit 9) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK9_Msk (0x200UL) /*!< RS_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK10_Pos (10UL) /*!< RS_MK10 (Bit 10) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK10_Msk (0x400UL) /*!< RS_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK11_Pos (11UL) /*!< RS_MK11 (Bit 11) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK11_Msk (0x800UL) /*!< RS_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK12_Pos (12UL) /*!< RS_MK12 (Bit 12) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK12_Msk (0x1000UL) /*!< RS_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK13_Pos (13UL) /*!< RS_MK13 (Bit 13) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK13_Msk (0x2000UL) /*!< RS_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK14_Pos (14UL) /*!< RS_MK14 (Bit 14) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK14_Msk (0x4000UL) /*!< RS_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK15_Pos (15UL) /*!< RS_MK15 (Bit 15) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK15_Msk (0x8000UL) /*!< RS_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK16_Pos (16UL) /*!< RS_MK16 (Bit 16) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK16_Msk (0x10000UL) /*!< RS_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK17_Pos (17UL) /*!< RS_MK17 (Bit 17) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK17_Msk (0x20000UL) /*!< RS_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK18_Pos (18UL) /*!< RS_MK18 (Bit 18) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK18_Msk (0x40000UL) /*!< RS_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK19_Pos (19UL) /*!< RS_MK19 (Bit 19) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK19_Msk (0x80000UL) /*!< RS_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK20_Pos (20UL) /*!< RS_MK20 (Bit 20) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK20_Msk (0x100000UL) /*!< RS_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK21_Pos (21UL) /*!< RS_MK21 (Bit 21) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK21_Msk (0x200000UL) /*!< RS_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK22_Pos (22UL) /*!< RS_MK22 (Bit 22) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK22_Msk (0x400000UL) /*!< RS_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK23_Pos (23UL) /*!< RS_MK23 (Bit 23) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK23_Msk (0x800000UL) /*!< RS_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK24_Pos (24UL) /*!< RS_MK24 (Bit 24) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK24_Msk (0x1000000UL) /*!< RS_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK25_Pos (25UL) /*!< RS_MK25 (Bit 25) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK25_Msk (0x2000000UL) /*!< RS_MK25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK26_Pos (26UL) /*!< RS_MK26 (Bit 26) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK26_Msk (0x4000000UL) /*!< RS_MK26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK27_Pos (27UL) /*!< RS_MK27 (Bit 27) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK27_Msk (0x8000000UL) /*!< RS_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK28_Pos (28UL) /*!< RS_MK28 (Bit 28) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK28_Msk (0x10000000UL) /*!< RS_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK29_Pos (29UL) /*!< RS_MK29 (Bit 29) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK29_Msk (0x20000000UL) /*!< RS_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK30_Pos (30UL) /*!< RS_MK30 (Bit 30) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK30_Msk (0x40000000UL) /*!< RS_MK30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK31_Pos (31UL) /*!< RS_MK31 (Bit 31) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK31_Msk (0x80000000UL) /*!< RS_MK31 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_RSTMSK1 ==================================================== */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK0_Pos (0UL) /*!< RS_MK0 (Bit 0) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK0_Msk (0x1UL) /*!< RS_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK1_Pos (1UL) /*!< RS_MK1 (Bit 1) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK1_Msk (0x2UL) /*!< RS_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK2_Pos (2UL) /*!< RS_MK2 (Bit 2) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK2_Msk (0x4UL) /*!< RS_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK3_Pos (3UL) /*!< RS_MK3 (Bit 3) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK3_Msk (0x8UL) /*!< RS_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK4_Pos (4UL) /*!< RS_MK4 (Bit 4) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK4_Msk (0x10UL) /*!< RS_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK5_Pos (5UL) /*!< RS_MK5 (Bit 5) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK5_Msk (0x20UL) /*!< RS_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK6_Pos (6UL) /*!< RS_MK6 (Bit 6) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK6_Msk (0x40UL) /*!< RS_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK7_Pos (7UL) /*!< RS_MK7 (Bit 7) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK7_Msk (0x80UL) /*!< RS_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK8_Pos (8UL) /*!< RS_MK8 (Bit 8) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK8_Msk (0x100UL) /*!< RS_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK9_Pos (9UL) /*!< RS_MK9 (Bit 9) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK9_Msk (0x200UL) /*!< RS_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK10_Pos (10UL) /*!< RS_MK10 (Bit 10) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK10_Msk (0x400UL) /*!< RS_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK11_Pos (11UL) /*!< RS_MK11 (Bit 11) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK11_Msk (0x800UL) /*!< RS_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK12_Pos (12UL) /*!< RS_MK12 (Bit 12) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK12_Msk (0x1000UL) /*!< RS_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK13_Pos (13UL) /*!< RS_MK13 (Bit 13) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK13_Msk (0x2000UL) /*!< RS_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK14_Pos (14UL) /*!< RS_MK14 (Bit 14) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK14_Msk (0x4000UL) /*!< RS_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK15_Pos (15UL) /*!< RS_MK15 (Bit 15) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK15_Msk (0x8000UL) /*!< RS_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK16_Pos (16UL) /*!< RS_MK16 (Bit 16) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK16_Msk (0x10000UL) /*!< RS_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK17_Pos (17UL) /*!< RS_MK17 (Bit 17) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK17_Msk (0x20000UL) /*!< RS_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK18_Pos (18UL) /*!< RS_MK18 (Bit 18) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK18_Msk (0x40000UL) /*!< RS_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK19_Pos (19UL) /*!< RS_MK19 (Bit 19) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK19_Msk (0x80000UL) /*!< RS_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK20_Pos (20UL) /*!< RS_MK20 (Bit 20) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK20_Msk (0x100000UL) /*!< RS_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK21_Pos (21UL) /*!< RS_MK21 (Bit 21) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK21_Msk (0x200000UL) /*!< RS_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK22_Pos (22UL) /*!< RS_MK22 (Bit 22) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK22_Msk (0x400000UL) /*!< RS_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK23_Pos (23UL) /*!< RS_MK23 (Bit 23) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK23_Msk (0x800000UL) /*!< RS_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK24_Pos (24UL) /*!< RS_MK24 (Bit 24) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK24_Msk (0x1000000UL) /*!< RS_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK27_Pos (27UL) /*!< RS_MK27 (Bit 27) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK27_Msk (0x8000000UL) /*!< RS_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK28_Pos (28UL) /*!< RS_MK28 (Bit 28) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK28_Msk (0x10000000UL) /*!< RS_MK28 (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU0ERR_E0MSK ===================================================== */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK0_Pos (0UL) /*!< E0_MK0 (Bit 0) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK0_Msk (0x1UL) /*!< E0_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK1_Pos (1UL) /*!< E0_MK1 (Bit 1) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK1_Msk (0x2UL) /*!< E0_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK2_Pos (2UL) /*!< E0_MK2 (Bit 2) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK2_Msk (0x4UL) /*!< E0_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK3_Pos (3UL) /*!< E0_MK3 (Bit 3) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK3_Msk (0x8UL) /*!< E0_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK4_Pos (4UL) /*!< E0_MK4 (Bit 4) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK4_Msk (0x10UL) /*!< E0_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK5_Pos (5UL) /*!< E0_MK5 (Bit 5) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK5_Msk (0x20UL) /*!< E0_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK6_Pos (6UL) /*!< E0_MK6 (Bit 6) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK6_Msk (0x40UL) /*!< E0_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK7_Pos (7UL) /*!< E0_MK7 (Bit 7) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK7_Msk (0x80UL) /*!< E0_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK8_Pos (8UL) /*!< E0_MK8 (Bit 8) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK8_Msk (0x100UL) /*!< E0_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK9_Pos (9UL) /*!< E0_MK9 (Bit 9) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK9_Msk (0x200UL) /*!< E0_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK10_Pos (10UL) /*!< E0_MK10 (Bit 10) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK10_Msk (0x400UL) /*!< E0_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK11_Pos (11UL) /*!< E0_MK11 (Bit 11) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK11_Msk (0x800UL) /*!< E0_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK12_Pos (12UL) /*!< E0_MK12 (Bit 12) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK12_Msk (0x1000UL) /*!< E0_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK13_Pos (13UL) /*!< E0_MK13 (Bit 13) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK13_Msk (0x2000UL) /*!< E0_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK14_Pos (14UL) /*!< E0_MK14 (Bit 14) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK14_Msk (0x4000UL) /*!< E0_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK15_Pos (15UL) /*!< E0_MK15 (Bit 15) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK15_Msk (0x8000UL) /*!< E0_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK16_Pos (16UL) /*!< E0_MK16 (Bit 16) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK16_Msk (0x10000UL) /*!< E0_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK17_Pos (17UL) /*!< E0_MK17 (Bit 17) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK17_Msk (0x20000UL) /*!< E0_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK18_Pos (18UL) /*!< E0_MK18 (Bit 18) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK18_Msk (0x40000UL) /*!< E0_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK19_Pos (19UL) /*!< E0_MK19 (Bit 19) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK19_Msk (0x80000UL) /*!< E0_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK20_Pos (20UL) /*!< E0_MK20 (Bit 20) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK20_Msk (0x100000UL) /*!< E0_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK21_Pos (21UL) /*!< E0_MK21 (Bit 21) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK21_Msk (0x200000UL) /*!< E0_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK22_Pos (22UL) /*!< E0_MK22 (Bit 22) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK22_Msk (0x400000UL) /*!< E0_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK23_Pos (23UL) /*!< E0_MK23 (Bit 23) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK23_Msk (0x800000UL) /*!< E0_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK24_Pos (24UL) /*!< E0_MK24 (Bit 24) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK24_Msk (0x1000000UL) /*!< E0_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK25_Pos (25UL) /*!< E0_MK25 (Bit 25) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK25_Msk (0x2000000UL) /*!< E0_MK25 (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU1ERR_E0MSK ===================================================== */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK0_Pos (0UL) /*!< E0_MK0 (Bit 0) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK0_Msk (0x1UL) /*!< E0_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK1_Pos (1UL) /*!< E0_MK1 (Bit 1) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK1_Msk (0x2UL) /*!< E0_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK2_Pos (2UL) /*!< E0_MK2 (Bit 2) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK2_Msk (0x4UL) /*!< E0_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK3_Pos (3UL) /*!< E0_MK3 (Bit 3) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK3_Msk (0x8UL) /*!< E0_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK4_Pos (4UL) /*!< E0_MK4 (Bit 4) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK4_Msk (0x10UL) /*!< E0_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK5_Pos (5UL) /*!< E0_MK5 (Bit 5) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK5_Msk (0x20UL) /*!< E0_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK6_Pos (6UL) /*!< E0_MK6 (Bit 6) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK6_Msk (0x40UL) /*!< E0_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK7_Pos (7UL) /*!< E0_MK7 (Bit 7) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK7_Msk (0x80UL) /*!< E0_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK8_Pos (8UL) /*!< E0_MK8 (Bit 8) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK8_Msk (0x100UL) /*!< E0_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK9_Pos (9UL) /*!< E0_MK9 (Bit 9) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK9_Msk (0x200UL) /*!< E0_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK10_Pos (10UL) /*!< E0_MK10 (Bit 10) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK10_Msk (0x400UL) /*!< E0_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK11_Pos (11UL) /*!< E0_MK11 (Bit 11) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK11_Msk (0x800UL) /*!< E0_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK12_Pos (12UL) /*!< E0_MK12 (Bit 12) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK12_Msk (0x1000UL) /*!< E0_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK13_Pos (13UL) /*!< E0_MK13 (Bit 13) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK13_Msk (0x2000UL) /*!< E0_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK14_Pos (14UL) /*!< E0_MK14 (Bit 14) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK14_Msk (0x4000UL) /*!< E0_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK15_Pos (15UL) /*!< E0_MK15 (Bit 15) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK15_Msk (0x8000UL) /*!< E0_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK16_Pos (16UL) /*!< E0_MK16 (Bit 16) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK16_Msk (0x10000UL) /*!< E0_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK17_Pos (17UL) /*!< E0_MK17 (Bit 17) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK17_Msk (0x20000UL) /*!< E0_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK18_Pos (18UL) /*!< E0_MK18 (Bit 18) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK18_Msk (0x40000UL) /*!< E0_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK19_Pos (19UL) /*!< E0_MK19 (Bit 19) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK19_Msk (0x80000UL) /*!< E0_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK20_Pos (20UL) /*!< E0_MK20 (Bit 20) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK20_Msk (0x100000UL) /*!< E0_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK21_Pos (21UL) /*!< E0_MK21 (Bit 21) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK21_Msk (0x200000UL) /*!< E0_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK22_Pos (22UL) /*!< E0_MK22 (Bit 22) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK22_Msk (0x400000UL) /*!< E0_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK23_Pos (23UL) /*!< E0_MK23 (Bit 23) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK23_Msk (0x800000UL) /*!< E0_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK24_Pos (24UL) /*!< E0_MK24 (Bit 24) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK24_Msk (0x1000000UL) /*!< E0_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK25_Pos (25UL) /*!< E0_MK25 (Bit 25) */ + #define R_ICU_CPU1ERR_E0MSK_E0_MK25_Msk (0x2000000UL) /*!< E0_MK25 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E0MSK0 ===================================================== */ + #define R_ICU_PERIERR_E0MSK0_E0_MK0_Pos (0UL) /*!< E0_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK0_Msk (0x1UL) /*!< E0_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK1_Pos (1UL) /*!< E0_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK1_Msk (0x2UL) /*!< E0_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK2_Pos (2UL) /*!< E0_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK2_Msk (0x4UL) /*!< E0_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK3_Pos (3UL) /*!< E0_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK3_Msk (0x8UL) /*!< E0_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK4_Pos (4UL) /*!< E0_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK4_Msk (0x10UL) /*!< E0_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK5_Pos (5UL) /*!< E0_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK5_Msk (0x20UL) /*!< E0_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK6_Pos (6UL) /*!< E0_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK6_Msk (0x40UL) /*!< E0_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK7_Pos (7UL) /*!< E0_MK7 (Bit 7) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK7_Msk (0x80UL) /*!< E0_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK8_Pos (8UL) /*!< E0_MK8 (Bit 8) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK8_Msk (0x100UL) /*!< E0_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK9_Pos (9UL) /*!< E0_MK9 (Bit 9) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK9_Msk (0x200UL) /*!< E0_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK10_Pos (10UL) /*!< E0_MK10 (Bit 10) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK10_Msk (0x400UL) /*!< E0_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK11_Pos (11UL) /*!< E0_MK11 (Bit 11) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK11_Msk (0x800UL) /*!< E0_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK12_Pos (12UL) /*!< E0_MK12 (Bit 12) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK12_Msk (0x1000UL) /*!< E0_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK13_Pos (13UL) /*!< E0_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK13_Msk (0x2000UL) /*!< E0_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK14_Pos (14UL) /*!< E0_MK14 (Bit 14) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK14_Msk (0x4000UL) /*!< E0_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK15_Pos (15UL) /*!< E0_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK15_Msk (0x8000UL) /*!< E0_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK16_Pos (16UL) /*!< E0_MK16 (Bit 16) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK16_Msk (0x10000UL) /*!< E0_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK17_Pos (17UL) /*!< E0_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK17_Msk (0x20000UL) /*!< E0_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK18_Pos (18UL) /*!< E0_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK18_Msk (0x40000UL) /*!< E0_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK19_Pos (19UL) /*!< E0_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK19_Msk (0x80000UL) /*!< E0_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK20_Pos (20UL) /*!< E0_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK20_Msk (0x100000UL) /*!< E0_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK21_Pos (21UL) /*!< E0_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK21_Msk (0x200000UL) /*!< E0_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK22_Pos (22UL) /*!< E0_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK22_Msk (0x400000UL) /*!< E0_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK23_Pos (23UL) /*!< E0_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK23_Msk (0x800000UL) /*!< E0_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK24_Pos (24UL) /*!< E0_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK24_Msk (0x1000000UL) /*!< E0_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK25_Pos (25UL) /*!< E0_MK25 (Bit 25) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK25_Msk (0x2000000UL) /*!< E0_MK25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK26_Pos (26UL) /*!< E0_MK26 (Bit 26) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK26_Msk (0x4000000UL) /*!< E0_MK26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK27_Pos (27UL) /*!< E0_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK27_Msk (0x8000000UL) /*!< E0_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK28_Pos (28UL) /*!< E0_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK28_Msk (0x10000000UL) /*!< E0_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK29_Pos (29UL) /*!< E0_MK29 (Bit 29) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK29_Msk (0x20000000UL) /*!< E0_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK30_Pos (30UL) /*!< E0_MK30 (Bit 30) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK30_Msk (0x40000000UL) /*!< E0_MK30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK31_Pos (31UL) /*!< E0_MK31 (Bit 31) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK31_Msk (0x80000000UL) /*!< E0_MK31 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E0MSK1 ===================================================== */ + #define R_ICU_PERIERR_E0MSK1_E0_MK0_Pos (0UL) /*!< E0_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK0_Msk (0x1UL) /*!< E0_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK1_Pos (1UL) /*!< E0_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK1_Msk (0x2UL) /*!< E0_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK2_Pos (2UL) /*!< E0_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK2_Msk (0x4UL) /*!< E0_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK3_Pos (3UL) /*!< E0_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK3_Msk (0x8UL) /*!< E0_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK4_Pos (4UL) /*!< E0_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK4_Msk (0x10UL) /*!< E0_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK5_Pos (5UL) /*!< E0_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK5_Msk (0x20UL) /*!< E0_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK6_Pos (6UL) /*!< E0_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK6_Msk (0x40UL) /*!< E0_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK7_Pos (7UL) /*!< E0_MK7 (Bit 7) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK7_Msk (0x80UL) /*!< E0_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK8_Pos (8UL) /*!< E0_MK8 (Bit 8) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK8_Msk (0x100UL) /*!< E0_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK9_Pos (9UL) /*!< E0_MK9 (Bit 9) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK9_Msk (0x200UL) /*!< E0_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK10_Pos (10UL) /*!< E0_MK10 (Bit 10) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK10_Msk (0x400UL) /*!< E0_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK11_Pos (11UL) /*!< E0_MK11 (Bit 11) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK11_Msk (0x800UL) /*!< E0_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK12_Pos (12UL) /*!< E0_MK12 (Bit 12) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK12_Msk (0x1000UL) /*!< E0_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK13_Pos (13UL) /*!< E0_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK13_Msk (0x2000UL) /*!< E0_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK14_Pos (14UL) /*!< E0_MK14 (Bit 14) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK14_Msk (0x4000UL) /*!< E0_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK15_Pos (15UL) /*!< E0_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK15_Msk (0x8000UL) /*!< E0_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK16_Pos (16UL) /*!< E0_MK16 (Bit 16) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK16_Msk (0x10000UL) /*!< E0_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK17_Pos (17UL) /*!< E0_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK17_Msk (0x20000UL) /*!< E0_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK18_Pos (18UL) /*!< E0_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK18_Msk (0x40000UL) /*!< E0_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK19_Pos (19UL) /*!< E0_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK19_Msk (0x80000UL) /*!< E0_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK20_Pos (20UL) /*!< E0_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK20_Msk (0x100000UL) /*!< E0_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK21_Pos (21UL) /*!< E0_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK21_Msk (0x200000UL) /*!< E0_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK22_Pos (22UL) /*!< E0_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK22_Msk (0x400000UL) /*!< E0_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK23_Pos (23UL) /*!< E0_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK23_Msk (0x800000UL) /*!< E0_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK24_Pos (24UL) /*!< E0_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK24_Msk (0x1000000UL) /*!< E0_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK27_Pos (27UL) /*!< E0_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK27_Msk (0x8000000UL) /*!< E0_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK28_Pos (28UL) /*!< E0_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK28_Msk (0x10000000UL) /*!< E0_MK28 (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU0ERR_E1MSK ===================================================== */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK0_Pos (0UL) /*!< E1_MK0 (Bit 0) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK0_Msk (0x1UL) /*!< E1_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK1_Pos (1UL) /*!< E1_MK1 (Bit 1) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK1_Msk (0x2UL) /*!< E1_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK2_Pos (2UL) /*!< E1_MK2 (Bit 2) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK2_Msk (0x4UL) /*!< E1_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK3_Pos (3UL) /*!< E1_MK3 (Bit 3) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK3_Msk (0x8UL) /*!< E1_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK4_Pos (4UL) /*!< E1_MK4 (Bit 4) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK4_Msk (0x10UL) /*!< E1_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK5_Pos (5UL) /*!< E1_MK5 (Bit 5) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK5_Msk (0x20UL) /*!< E1_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK6_Pos (6UL) /*!< E1_MK6 (Bit 6) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK6_Msk (0x40UL) /*!< E1_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK7_Pos (7UL) /*!< E1_MK7 (Bit 7) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK7_Msk (0x80UL) /*!< E1_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK8_Pos (8UL) /*!< E1_MK8 (Bit 8) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK8_Msk (0x100UL) /*!< E1_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK9_Pos (9UL) /*!< E1_MK9 (Bit 9) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK9_Msk (0x200UL) /*!< E1_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK10_Pos (10UL) /*!< E1_MK10 (Bit 10) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK10_Msk (0x400UL) /*!< E1_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK11_Pos (11UL) /*!< E1_MK11 (Bit 11) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK11_Msk (0x800UL) /*!< E1_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK12_Pos (12UL) /*!< E1_MK12 (Bit 12) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK12_Msk (0x1000UL) /*!< E1_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK13_Pos (13UL) /*!< E1_MK13 (Bit 13) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK13_Msk (0x2000UL) /*!< E1_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK14_Pos (14UL) /*!< E1_MK14 (Bit 14) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK14_Msk (0x4000UL) /*!< E1_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK15_Pos (15UL) /*!< E1_MK15 (Bit 15) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK15_Msk (0x8000UL) /*!< E1_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK16_Pos (16UL) /*!< E1_MK16 (Bit 16) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK16_Msk (0x10000UL) /*!< E1_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK17_Pos (17UL) /*!< E1_MK17 (Bit 17) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK17_Msk (0x20000UL) /*!< E1_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK18_Pos (18UL) /*!< E1_MK18 (Bit 18) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK18_Msk (0x40000UL) /*!< E1_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK19_Pos (19UL) /*!< E1_MK19 (Bit 19) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK19_Msk (0x80000UL) /*!< E1_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK20_Pos (20UL) /*!< E1_MK20 (Bit 20) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK20_Msk (0x100000UL) /*!< E1_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK21_Pos (21UL) /*!< E1_MK21 (Bit 21) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK21_Msk (0x200000UL) /*!< E1_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK22_Pos (22UL) /*!< E1_MK22 (Bit 22) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK22_Msk (0x400000UL) /*!< E1_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK23_Pos (23UL) /*!< E1_MK23 (Bit 23) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK23_Msk (0x800000UL) /*!< E1_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK24_Pos (24UL) /*!< E1_MK24 (Bit 24) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK24_Msk (0x1000000UL) /*!< E1_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK25_Pos (25UL) /*!< E1_MK25 (Bit 25) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK25_Msk (0x2000000UL) /*!< E1_MK25 (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU1ERR_E1MSK ===================================================== */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK0_Pos (0UL) /*!< E1_MK0 (Bit 0) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK0_Msk (0x1UL) /*!< E1_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK1_Pos (1UL) /*!< E1_MK1 (Bit 1) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK1_Msk (0x2UL) /*!< E1_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK2_Pos (2UL) /*!< E1_MK2 (Bit 2) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK2_Msk (0x4UL) /*!< E1_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK3_Pos (3UL) /*!< E1_MK3 (Bit 3) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK3_Msk (0x8UL) /*!< E1_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK4_Pos (4UL) /*!< E1_MK4 (Bit 4) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK4_Msk (0x10UL) /*!< E1_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK5_Pos (5UL) /*!< E1_MK5 (Bit 5) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK5_Msk (0x20UL) /*!< E1_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK6_Pos (6UL) /*!< E1_MK6 (Bit 6) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK6_Msk (0x40UL) /*!< E1_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK7_Pos (7UL) /*!< E1_MK7 (Bit 7) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK7_Msk (0x80UL) /*!< E1_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK8_Pos (8UL) /*!< E1_MK8 (Bit 8) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK8_Msk (0x100UL) /*!< E1_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK9_Pos (9UL) /*!< E1_MK9 (Bit 9) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK9_Msk (0x200UL) /*!< E1_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK10_Pos (10UL) /*!< E1_MK10 (Bit 10) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK10_Msk (0x400UL) /*!< E1_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK11_Pos (11UL) /*!< E1_MK11 (Bit 11) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK11_Msk (0x800UL) /*!< E1_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK12_Pos (12UL) /*!< E1_MK12 (Bit 12) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK12_Msk (0x1000UL) /*!< E1_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK13_Pos (13UL) /*!< E1_MK13 (Bit 13) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK13_Msk (0x2000UL) /*!< E1_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK14_Pos (14UL) /*!< E1_MK14 (Bit 14) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK14_Msk (0x4000UL) /*!< E1_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK15_Pos (15UL) /*!< E1_MK15 (Bit 15) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK15_Msk (0x8000UL) /*!< E1_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK16_Pos (16UL) /*!< E1_MK16 (Bit 16) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK16_Msk (0x10000UL) /*!< E1_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK17_Pos (17UL) /*!< E1_MK17 (Bit 17) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK17_Msk (0x20000UL) /*!< E1_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK18_Pos (18UL) /*!< E1_MK18 (Bit 18) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK18_Msk (0x40000UL) /*!< E1_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK19_Pos (19UL) /*!< E1_MK19 (Bit 19) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK19_Msk (0x80000UL) /*!< E1_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK20_Pos (20UL) /*!< E1_MK20 (Bit 20) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK20_Msk (0x100000UL) /*!< E1_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK21_Pos (21UL) /*!< E1_MK21 (Bit 21) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK21_Msk (0x200000UL) /*!< E1_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK22_Pos (22UL) /*!< E1_MK22 (Bit 22) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK22_Msk (0x400000UL) /*!< E1_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK23_Pos (23UL) /*!< E1_MK23 (Bit 23) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK23_Msk (0x800000UL) /*!< E1_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK24_Pos (24UL) /*!< E1_MK24 (Bit 24) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK24_Msk (0x1000000UL) /*!< E1_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK25_Pos (25UL) /*!< E1_MK25 (Bit 25) */ + #define R_ICU_CPU1ERR_E1MSK_E1_MK25_Msk (0x2000000UL) /*!< E1_MK25 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E1MSK0 ===================================================== */ + #define R_ICU_PERIERR_E1MSK0_E1_MK0_Pos (0UL) /*!< E1_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK0_Msk (0x1UL) /*!< E1_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK1_Pos (1UL) /*!< E1_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK1_Msk (0x2UL) /*!< E1_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK2_Pos (2UL) /*!< E1_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK2_Msk (0x4UL) /*!< E1_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK3_Pos (3UL) /*!< E1_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK3_Msk (0x8UL) /*!< E1_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK4_Pos (4UL) /*!< E1_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK4_Msk (0x10UL) /*!< E1_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK5_Pos (5UL) /*!< E1_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK5_Msk (0x20UL) /*!< E1_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK6_Pos (6UL) /*!< E1_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK6_Msk (0x40UL) /*!< E1_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK7_Pos (7UL) /*!< E1_MK7 (Bit 7) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK7_Msk (0x80UL) /*!< E1_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK8_Pos (8UL) /*!< E1_MK8 (Bit 8) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK8_Msk (0x100UL) /*!< E1_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK9_Pos (9UL) /*!< E1_MK9 (Bit 9) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK9_Msk (0x200UL) /*!< E1_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK10_Pos (10UL) /*!< E1_MK10 (Bit 10) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK10_Msk (0x400UL) /*!< E1_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK11_Pos (11UL) /*!< E1_MK11 (Bit 11) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK11_Msk (0x800UL) /*!< E1_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK12_Pos (12UL) /*!< E1_MK12 (Bit 12) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK12_Msk (0x1000UL) /*!< E1_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK13_Pos (13UL) /*!< E1_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK13_Msk (0x2000UL) /*!< E1_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK14_Pos (14UL) /*!< E1_MK14 (Bit 14) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK14_Msk (0x4000UL) /*!< E1_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK15_Pos (15UL) /*!< E1_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK15_Msk (0x8000UL) /*!< E1_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK16_Pos (16UL) /*!< E1_MK16 (Bit 16) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK16_Msk (0x10000UL) /*!< E1_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK17_Pos (17UL) /*!< E1_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK17_Msk (0x20000UL) /*!< E1_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK18_Pos (18UL) /*!< E1_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK18_Msk (0x40000UL) /*!< E1_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK19_Pos (19UL) /*!< E1_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK19_Msk (0x80000UL) /*!< E1_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK20_Pos (20UL) /*!< E1_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK20_Msk (0x100000UL) /*!< E1_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK21_Pos (21UL) /*!< E1_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK21_Msk (0x200000UL) /*!< E1_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK22_Pos (22UL) /*!< E1_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK22_Msk (0x400000UL) /*!< E1_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK23_Pos (23UL) /*!< E1_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK23_Msk (0x800000UL) /*!< E1_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK24_Pos (24UL) /*!< E1_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK24_Msk (0x1000000UL) /*!< E1_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK25_Pos (25UL) /*!< E1_MK25 (Bit 25) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK25_Msk (0x2000000UL) /*!< E1_MK25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK26_Pos (26UL) /*!< E1_MK26 (Bit 26) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK26_Msk (0x4000000UL) /*!< E1_MK26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK27_Pos (27UL) /*!< E1_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK27_Msk (0x8000000UL) /*!< E1_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK28_Pos (28UL) /*!< E1_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK28_Msk (0x10000000UL) /*!< E1_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK29_Pos (29UL) /*!< E1_MK29 (Bit 29) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK29_Msk (0x20000000UL) /*!< E1_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK30_Pos (30UL) /*!< E1_MK30 (Bit 30) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK30_Msk (0x40000000UL) /*!< E1_MK30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK31_Pos (31UL) /*!< E1_MK31 (Bit 31) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK31_Msk (0x80000000UL) /*!< E1_MK31 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E1MSK1 ===================================================== */ + #define R_ICU_PERIERR_E1MSK1_E1_MK0_Pos (0UL) /*!< E1_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK0_Msk (0x1UL) /*!< E1_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK1_Pos (1UL) /*!< E1_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK1_Msk (0x2UL) /*!< E1_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK2_Pos (2UL) /*!< E1_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK2_Msk (0x4UL) /*!< E1_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK3_Pos (3UL) /*!< E1_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK3_Msk (0x8UL) /*!< E1_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK4_Pos (4UL) /*!< E1_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK4_Msk (0x10UL) /*!< E1_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK5_Pos (5UL) /*!< E1_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK5_Msk (0x20UL) /*!< E1_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK6_Pos (6UL) /*!< E1_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK6_Msk (0x40UL) /*!< E1_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK7_Pos (7UL) /*!< E1_MK7 (Bit 7) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK7_Msk (0x80UL) /*!< E1_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK8_Pos (8UL) /*!< E1_MK8 (Bit 8) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK8_Msk (0x100UL) /*!< E1_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK9_Pos (9UL) /*!< E1_MK9 (Bit 9) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK9_Msk (0x200UL) /*!< E1_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK10_Pos (10UL) /*!< E1_MK10 (Bit 10) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK10_Msk (0x400UL) /*!< E1_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK11_Pos (11UL) /*!< E1_MK11 (Bit 11) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK11_Msk (0x800UL) /*!< E1_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK12_Pos (12UL) /*!< E1_MK12 (Bit 12) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK12_Msk (0x1000UL) /*!< E1_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK13_Pos (13UL) /*!< E1_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK13_Msk (0x2000UL) /*!< E1_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK14_Pos (14UL) /*!< E1_MK14 (Bit 14) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK14_Msk (0x4000UL) /*!< E1_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK15_Pos (15UL) /*!< E1_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK15_Msk (0x8000UL) /*!< E1_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK16_Pos (16UL) /*!< E1_MK16 (Bit 16) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK16_Msk (0x10000UL) /*!< E1_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK17_Pos (17UL) /*!< E1_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK17_Msk (0x20000UL) /*!< E1_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK18_Pos (18UL) /*!< E1_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK18_Msk (0x40000UL) /*!< E1_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK19_Pos (19UL) /*!< E1_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK19_Msk (0x80000UL) /*!< E1_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK20_Pos (20UL) /*!< E1_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK20_Msk (0x100000UL) /*!< E1_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK21_Pos (21UL) /*!< E1_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK21_Msk (0x200000UL) /*!< E1_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK22_Pos (22UL) /*!< E1_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK22_Msk (0x400000UL) /*!< E1_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK23_Pos (23UL) /*!< E1_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK23_Msk (0x800000UL) /*!< E1_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK24_Pos (24UL) /*!< E1_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK24_Msk (0x1000000UL) /*!< E1_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK27_Pos (27UL) /*!< E1_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK27_Msk (0x8000000UL) /*!< E1_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK28_Pos (28UL) /*!< E1_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK28_Msk (0x10000000UL) /*!< E1_MK28 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSC_S ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SCKCR2 ========================================================= */ + #define R_SYSC_S_SCKCR2_FSELCPU0_Pos (0UL) /*!< FSELCPU0 (Bit 0) */ + #define R_SYSC_S_SCKCR2_FSELCPU0_Msk (0x3UL) /*!< FSELCPU0 (Bitfield-Mask: 0x03) */ + #define R_SYSC_S_SCKCR2_FSELCPU1_Pos (2UL) /*!< FSELCPU1 (Bit 2) */ + #define R_SYSC_S_SCKCR2_FSELCPU1_Msk (0xcUL) /*!< FSELCPU1 (Bitfield-Mask: 0x03) */ + #define R_SYSC_S_SCKCR2_DIVSELSUB_Pos (5UL) /*!< DIVSELSUB (Bit 5) */ + #define R_SYSC_S_SCKCR2_DIVSELSUB_Msk (0x20UL) /*!< DIVSELSUB (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_SCKCR2_SPI3ASYNCSEL_Pos (24UL) /*!< SPI3ASYNCSEL (Bit 24) */ + #define R_SYSC_S_SCKCR2_SPI3ASYNCSEL_Msk (0x1000000UL) /*!< SPI3ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_SCKCR2_SCI5ASYNCSEL_Pos (25UL) /*!< SCI5ASYNCSEL (Bit 25) */ + #define R_SYSC_S_SCKCR2_SCI5ASYNCSEL_Msk (0x2000000UL) /*!< SCI5ASYNCSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL0MON ======================================================== */ + #define R_SYSC_S_PLL0MON_PLL0MON_Pos (0UL) /*!< PLL0MON (Bit 0) */ + #define R_SYSC_S_PLL0MON_PLL0MON_Msk (0x1UL) /*!< PLL0MON (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL1MON ======================================================== */ + #define R_SYSC_S_PLL1MON_PLL1MON_Pos (0UL) /*!< PLL1MON (Bit 0) */ + #define R_SYSC_S_PLL1MON_PLL1MON_Msk (0x1UL) /*!< PLL1MON (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL1EN ========================================================= */ + #define R_SYSC_S_PLL1EN_PLL1EN_Pos (0UL) /*!< PLL1EN (Bit 0) */ + #define R_SYSC_S_PLL1EN_PLL1EN_Msk (0x1UL) /*!< PLL1EN (Bitfield-Mask: 0x01) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSC_S_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSC_S_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= HIZCTRLEN ======================================================= */ + #define R_SYSC_S_HIZCTRLEN_CLMA3MASK_Pos (0UL) /*!< CLMA3MASK (Bit 0) */ + #define R_SYSC_S_HIZCTRLEN_CLMA3MASK_Msk (0x1UL) /*!< CLMA3MASK (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_HIZCTRLEN_CLMA0MASK_Pos (1UL) /*!< CLMA0MASK (Bit 1) */ + #define R_SYSC_S_HIZCTRLEN_CLMA0MASK_Msk (0x2UL) /*!< CLMA0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_HIZCTRLEN_CLMA1MASK_Pos (2UL) /*!< CLMA1MASK (Bit 2) */ + #define R_SYSC_S_HIZCTRLEN_CLMA1MASK_Msk (0x4UL) /*!< CLMA1MASK (Bitfield-Mask: 0x01) */ +/* ======================================================== SWRSYS ========================================================= */ + #define R_SYSC_S_SWRSYS_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_SYSC_S_SWRSYS_SWR_Msk (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SWRCPU0 ======================================================== */ + #define R_SYSC_S_SWRCPU0_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_SYSC_S_SWRCPU0_SWR_Msk (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SWRCPU1 ======================================================== */ + #define R_SYSC_S_SWRCPU1_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_SYSC_S_SWRCPU1_SWR_Msk (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MSTPCRF ======================================================== */ + #define R_SYSC_S_MSTPCRF_MSTPCRF00_Pos (0UL) /*!< MSTPCRF00 (Bit 0) */ + #define R_SYSC_S_MSTPCRF_MSTPCRF00_Msk (0x1UL) /*!< MSTPCRF00 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRG ======================================================== */ + #define R_SYSC_S_MSTPCRG_MSTPCRG00_Pos (0UL) /*!< MSTPCRG00 (Bit 0) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG00_Msk (0x1UL) /*!< MSTPCRG00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG01_Pos (1UL) /*!< MSTPCRG01 (Bit 1) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG01_Msk (0x2UL) /*!< MSTPCRG01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG02_Pos (2UL) /*!< MSTPCRG02 (Bit 2) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG02_Msk (0x4UL) /*!< MSTPCRG02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG03_Pos (3UL) /*!< MSTPCRG03 (Bit 3) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG03_Msk (0x8UL) /*!< MSTPCRG03 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG04_Pos (4UL) /*!< MSTPCRG04 (Bit 4) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG04_Msk (0x10UL) /*!< MSTPCRG04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG05_Pos (5UL) /*!< MSTPCRG05 (Bit 5) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG05_Msk (0x20UL) /*!< MSTPCRG05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG08_Pos (8UL) /*!< MSTPCRG08 (Bit 8) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG08_Msk (0x100UL) /*!< MSTPCRG08 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG09_Pos (9UL) /*!< MSTPCRG09 (Bit 9) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG09_Msk (0x200UL) /*!< MSTPCRG09 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG10_Pos (10UL) /*!< MSTPCRG10 (Bit 10) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG10_Msk (0x400UL) /*!< MSTPCRG10 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG11_Pos (11UL) /*!< MSTPCRG11 (Bit 11) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG11_Msk (0x800UL) /*!< MSTPCRG11 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRH ======================================================== */ + #define R_SYSC_S_MSTPCRH_MSTPCRH01_Pos (1UL) /*!< MSTPCRH01 (Bit 1) */ + #define R_SYSC_S_MSTPCRH_MSTPCRH01_Msk (0x2UL) /*!< MSTPCRH01 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CLMA0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTL0 ========================================================== */ + #define R_CLMA0_CTL0_CLME_Pos (0UL) /*!< CLME (Bit 0) */ + #define R_CLMA0_CTL0_CLME_Msk (0x1UL) /*!< CLME (Bitfield-Mask: 0x01) */ +/* ========================================================= CMPL ========================================================== */ + #define R_CLMA0_CMPL_CMPL_Pos (0UL) /*!< CMPL (Bit 0) */ + #define R_CLMA0_CMPL_CMPL_Msk (0xfffUL) /*!< CMPL (Bitfield-Mask: 0xfff) */ +/* ========================================================= CMPH ========================================================== */ + #define R_CLMA0_CMPH_CMPH_Pos (0UL) /*!< CMPH (Bit 0) */ + #define R_CLMA0_CMPH_CMPH_Msk (0xfffUL) /*!< CMPH (Bitfield-Mask: 0xfff) */ +/* ========================================================= PCMD ========================================================== */ +/* ======================================================== PROTSR ========================================================= */ + #define R_CLMA0_PROTSR_PRERR_Pos (0UL) /*!< PRERR (Bit 0) */ + #define R_CLMA0_PROTSR_PRERR_Msk (0x1UL) /*!< PRERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= ERRINF_R ======================================================== */ + #define R_MPU0_ERRINF_R_VALID_Pos (0UL) /*!< VALID (Bit 0) */ + #define R_MPU0_ERRINF_R_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_MPU0_ERRINF_R_RW_Pos (1UL) /*!< RW (Bit 1) */ + #define R_MPU0_ERRINF_R_RW_Msk (0x2UL) /*!< RW (Bitfield-Mask: 0x01) */ + #define R_MPU0_ERRINF_R_ERRADDR_Pos (2UL) /*!< ERRADDR (Bit 2) */ + #define R_MPU0_ERRINF_R_ERRADDR_Msk (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================= ERRINF_W ======================================================== */ + #define R_MPU0_ERRINF_W_VALID_Pos (0UL) /*!< VALID (Bit 0) */ + #define R_MPU0_ERRINF_W_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_MPU0_ERRINF_W_RW_Pos (1UL) /*!< RW (Bit 1) */ + #define R_MPU0_ERRINF_W_RW_Msk (0x2UL) /*!< RW (Bitfield-Mask: 0x01) */ + #define R_MPU0_ERRINF_W_ERRADDR_Pos (2UL) /*!< ERRADDR (Bit 2) */ + #define R_MPU0_ERRINF_W_ERRADDR_Msk (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU3 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== ERRINF ========================================================= */ + #define R_MPU3_ERRINF_VALID_Pos (0UL) /*!< VALID (Bit 0) */ + #define R_MPU3_ERRINF_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_MPU3_ERRINF_RW_Pos (1UL) /*!< RW (Bit 1) */ + #define R_MPU3_ERRINF_RW_Msk (0x2UL) /*!< RW (Bitfield-Mask: 0x01) */ + #define R_MPU3_ERRINF_ERRADDR_Pos (2UL) /*!< ERRADDR (Bit 2) */ + #define R_MPU3_ERRINF_ERRADDR_Msk (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSRAM_CTL ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== SYSRAM_CTRL0 ====================================================== */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VECEN_Pos (0UL) /*!< VECEN (Bit 0) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VECEN_Msk (0x1UL) /*!< VECEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VRWEN_Pos (16UL) /*!< VRWEN (Bit 16) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VRWEN_Msk (0xf0000UL) /*!< VRWEN (Bitfield-Mask: 0x0f) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VCEN_Pos (20UL) /*!< VCEN (Bit 20) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VCEN_Msk (0x100000UL) /*!< VCEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VLWEN_Pos (21UL) /*!< VLWEN (Bit 21) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VLWEN_Msk (0x200000UL) /*!< VLWEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_MKICCAXIERR_Pos (24UL) /*!< MKICCAXIERR (Bit 24) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_MKICCAXIERR_Msk (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01) */ +/* ===================================================== SYSRAM_CTRL1 ====================================================== */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VECEN_Pos (0UL) /*!< VECEN (Bit 0) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VECEN_Msk (0x1UL) /*!< VECEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VRWEN_Pos (16UL) /*!< VRWEN (Bit 16) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VRWEN_Msk (0xf0000UL) /*!< VRWEN (Bitfield-Mask: 0x0f) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VCEN_Pos (20UL) /*!< VCEN (Bit 20) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VCEN_Msk (0x100000UL) /*!< VCEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VLWEN_Pos (21UL) /*!< VLWEN (Bit 21) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VLWEN_Msk (0x200000UL) /*!< VLWEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_MKICCAXIERR_Pos (24UL) /*!< MKICCAXIERR (Bit 24) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_MKICCAXIERR_Msk (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01) */ +/* ===================================================== SYSRAM_CTRL2 ====================================================== */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VECEN_Pos (0UL) /*!< VECEN (Bit 0) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VECEN_Msk (0x1UL) /*!< VECEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VRWEN_Pos (16UL) /*!< VRWEN (Bit 16) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VRWEN_Msk (0xf0000UL) /*!< VRWEN (Bitfield-Mask: 0x0f) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VCEN_Pos (20UL) /*!< VCEN (Bit 20) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VCEN_Msk (0x100000UL) /*!< VCEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VLWEN_Pos (21UL) /*!< VLWEN (Bit 21) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VLWEN_Msk (0x200000UL) /*!< VLWEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_MKICCAXIERR_Pos (24UL) /*!< MKICCAXIERR (Bit 24) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_MKICCAXIERR_Msk (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01) */ +/* ===================================================== SYSRAM_CTRL3 ====================================================== */ + #define R_SYSRAM_CTL_SYSRAM_CTRL3_VECEN_Pos (0UL) /*!< VECEN (Bit 0) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL3_VECEN_Msk (0x1UL) /*!< VECEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL3_VRWEN_Pos (16UL) /*!< VRWEN (Bit 16) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL3_VRWEN_Msk (0xf0000UL) /*!< VRWEN (Bitfield-Mask: 0x0f) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL3_VCEN_Pos (20UL) /*!< VCEN (Bit 20) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL3_VCEN_Msk (0x100000UL) /*!< VCEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL3_VLWEN_Pos (21UL) /*!< VLWEN (Bit 21) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL3_VLWEN_Msk (0x200000UL) /*!< VLWEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL3_MKICCAXIERR_Pos (24UL) /*!< MKICCAXIERR (Bit 24) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL3_MKICCAXIERR_Msk (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TCMAW ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= CPU0WAIT ======================================================== */ + #define R_TCMAW_CPU0WAIT_CPU0WAIT_Pos (0UL) /*!< CPU0WAIT (Bit 0) */ + #define R_TCMAW_CPU0WAIT_CPU0WAIT_Msk (0x1UL) /*!< CPU0WAIT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RWP_S ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRCRS ========================================================= */ + #define R_RWP_S_PRCRS_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_RWP_S_PRCRS_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_RWP_S_PRCRS_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_RWP_S_PRCRS_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_RWP_S_PRCRS_PRC2_Pos (2UL) /*!< PRC2 (Bit 2) */ + #define R_RWP_S_PRCRS_PRC2_Msk (0x4UL) /*!< PRC2 (Bitfield-Mask: 0x01) */ + #define R_RWP_S_PRCRS_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_RWP_S_PRCRS_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_RWP_S_PRCRS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_RWP_S_PRCRS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_AC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= CPU1_CTRL ======================================================= */ + #define R_MPU_AC_CPU1_CTRL_CPU1_CTRL_Pos (0UL) /*!< CPU1_CTRL (Bit 0) */ + #define R_MPU_AC_CPU1_CTRL_CPU1_CTRL_Msk (0x1UL) /*!< CPU1_CTRL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TOERA ========================================================= */ + #define R_MTU_TOERA_OE3B_Pos (0UL) /*!< OE3B (Bit 0) */ + #define R_MTU_TOERA_OE3B_Msk (0x1UL) /*!< OE3B (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERA_OE4A_Pos (1UL) /*!< OE4A (Bit 1) */ + #define R_MTU_TOERA_OE4A_Msk (0x2UL) /*!< OE4A (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERA_OE4B_Pos (2UL) /*!< OE4B (Bit 2) */ + #define R_MTU_TOERA_OE4B_Msk (0x4UL) /*!< OE4B (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERA_OE3D_Pos (3UL) /*!< OE3D (Bit 3) */ + #define R_MTU_TOERA_OE3D_Msk (0x8UL) /*!< OE3D (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERA_OE4C_Pos (4UL) /*!< OE4C (Bit 4) */ + #define R_MTU_TOERA_OE4C_Msk (0x10UL) /*!< OE4C (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERA_OE4D_Pos (5UL) /*!< OE4D (Bit 5) */ + #define R_MTU_TOERA_OE4D_Msk (0x20UL) /*!< OE4D (Bitfield-Mask: 0x01) */ +/* ========================================================= TGCRA ========================================================= */ + #define R_MTU_TGCRA_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_MTU_TGCRA_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_MTU_TGCRA_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_MTU_TGCRA_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_FB_Pos (3UL) /*!< FB (Bit 3) */ + #define R_MTU_TGCRA_FB_Msk (0x8UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_P_Pos (4UL) /*!< P (Bit 4) */ + #define R_MTU_TGCRA_P_Msk (0x10UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_N_Pos (5UL) /*!< N (Bit 5) */ + #define R_MTU_TGCRA_N_Msk (0x20UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_BDC_Pos (6UL) /*!< BDC (Bit 6) */ + #define R_MTU_TGCRA_BDC_Msk (0x40UL) /*!< BDC (Bitfield-Mask: 0x01) */ +/* ======================================================== TOCR1A ========================================================= */ + #define R_MTU_TOCR1A_OLSP_Pos (0UL) /*!< OLSP (Bit 0) */ + #define R_MTU_TOCR1A_OLSP_Msk (0x1UL) /*!< OLSP (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1A_OLSN_Pos (1UL) /*!< OLSN (Bit 1) */ + #define R_MTU_TOCR1A_OLSN_Msk (0x2UL) /*!< OLSN (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1A_TOCS_Pos (2UL) /*!< TOCS (Bit 2) */ + #define R_MTU_TOCR1A_TOCS_Msk (0x4UL) /*!< TOCS (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1A_TOCL_Pos (3UL) /*!< TOCL (Bit 3) */ + #define R_MTU_TOCR1A_TOCL_Msk (0x8UL) /*!< TOCL (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1A_PSYE_Pos (6UL) /*!< PSYE (Bit 6) */ + #define R_MTU_TOCR1A_PSYE_Msk (0x40UL) /*!< PSYE (Bitfield-Mask: 0x01) */ +/* ======================================================== TOCR2A ========================================================= */ + #define R_MTU_TOCR2A_OLS1P_Pos (0UL) /*!< OLS1P (Bit 0) */ + #define R_MTU_TOCR2A_OLS1P_Msk (0x1UL) /*!< OLS1P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_OLS1N_Pos (1UL) /*!< OLS1N (Bit 1) */ + #define R_MTU_TOCR2A_OLS1N_Msk (0x2UL) /*!< OLS1N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_OLS2P_Pos (2UL) /*!< OLS2P (Bit 2) */ + #define R_MTU_TOCR2A_OLS2P_Msk (0x4UL) /*!< OLS2P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_OLS2N_Pos (3UL) /*!< OLS2N (Bit 3) */ + #define R_MTU_TOCR2A_OLS2N_Msk (0x8UL) /*!< OLS2N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_OLS3P_Pos (4UL) /*!< OLS3P (Bit 4) */ + #define R_MTU_TOCR2A_OLS3P_Msk (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_OLS3N_Pos (5UL) /*!< OLS3N (Bit 5) */ + #define R_MTU_TOCR2A_OLS3N_Msk (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_BF_Pos (6UL) /*!< BF (Bit 6) */ + #define R_MTU_TOCR2A_BF_Msk (0xc0UL) /*!< BF (Bitfield-Mask: 0x03) */ +/* ========================================================= TCDRA ========================================================= */ +/* ========================================================= TDDRA ========================================================= */ +/* ======================================================== TCNTSA ========================================================= */ +/* ========================================================= TCBRA ========================================================= */ +/* ======================================================== TITCR1A ======================================================== */ + #define R_MTU_TITCR1A_T4VCOR_Pos (0UL) /*!< T4VCOR (Bit 0) */ + #define R_MTU_TITCR1A_T4VCOR_Msk (0x7UL) /*!< T4VCOR (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCR1A_T4VEN_Pos (3UL) /*!< T4VEN (Bit 3) */ + #define R_MTU_TITCR1A_T4VEN_Msk (0x8UL) /*!< T4VEN (Bitfield-Mask: 0x01) */ + #define R_MTU_TITCR1A_T3ACOR_Pos (4UL) /*!< T3ACOR (Bit 4) */ + #define R_MTU_TITCR1A_T3ACOR_Msk (0x70UL) /*!< T3ACOR (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCR1A_T3AEN_Pos (7UL) /*!< T3AEN (Bit 7) */ + #define R_MTU_TITCR1A_T3AEN_Msk (0x80UL) /*!< T3AEN (Bitfield-Mask: 0x01) */ +/* ======================================================= TITCNT1A ======================================================== */ + #define R_MTU_TITCNT1A_T4VCNT_Pos (0UL) /*!< T4VCNT (Bit 0) */ + #define R_MTU_TITCNT1A_T4VCNT_Msk (0x7UL) /*!< T4VCNT (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCNT1A_T3ACNT_Pos (4UL) /*!< T3ACNT (Bit 4) */ + #define R_MTU_TITCNT1A_T3ACNT_Msk (0x70UL) /*!< T3ACNT (Bitfield-Mask: 0x07) */ +/* ======================================================== TBTERA ========================================================= */ + #define R_MTU_TBTERA_BTE_Pos (0UL) /*!< BTE (Bit 0) */ + #define R_MTU_TBTERA_BTE_Msk (0x3UL) /*!< BTE (Bitfield-Mask: 0x03) */ +/* ========================================================= TDERA ========================================================= */ + #define R_MTU_TDERA_TDER_Pos (0UL) /*!< TDER (Bit 0) */ + #define R_MTU_TDERA_TDER_Msk (0x1UL) /*!< TDER (Bitfield-Mask: 0x01) */ +/* ======================================================== TOLBRA ========================================================= */ + #define R_MTU_TOLBRA_OLS1P_Pos (0UL) /*!< OLS1P (Bit 0) */ + #define R_MTU_TOLBRA_OLS1P_Msk (0x1UL) /*!< OLS1P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRA_OLS1N_Pos (1UL) /*!< OLS1N (Bit 1) */ + #define R_MTU_TOLBRA_OLS1N_Msk (0x2UL) /*!< OLS1N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRA_OLS2P_Pos (2UL) /*!< OLS2P (Bit 2) */ + #define R_MTU_TOLBRA_OLS2P_Msk (0x4UL) /*!< OLS2P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRA_OLS2N_Pos (3UL) /*!< OLS2N (Bit 3) */ + #define R_MTU_TOLBRA_OLS2N_Msk (0x8UL) /*!< OLS2N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRA_OLS3P_Pos (4UL) /*!< OLS3P (Bit 4) */ + #define R_MTU_TOLBRA_OLS3P_Msk (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRA_OLS3N_Pos (5UL) /*!< OLS3N (Bit 5) */ + #define R_MTU_TOLBRA_OLS3N_Msk (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01) */ +/* ======================================================== TITMRA ========================================================= */ + #define R_MTU_TITMRA_TITM_Pos (0UL) /*!< TITM (Bit 0) */ + #define R_MTU_TITMRA_TITM_Msk (0x1UL) /*!< TITM (Bitfield-Mask: 0x01) */ +/* ======================================================== TITCR2A ======================================================== */ + #define R_MTU_TITCR2A_TRG4COR_Pos (0UL) /*!< TRG4COR (Bit 0) */ + #define R_MTU_TITCR2A_TRG4COR_Msk (0x7UL) /*!< TRG4COR (Bitfield-Mask: 0x07) */ +/* ======================================================= TITCNT2A ======================================================== */ + #define R_MTU_TITCNT2A_TRG4CNT_Pos (0UL) /*!< TRG4CNT (Bit 0) */ + #define R_MTU_TITCNT2A_TRG4CNT_Msk (0x7UL) /*!< TRG4CNT (Bitfield-Mask: 0x07) */ +/* ========================================================= TWCRA ========================================================= */ + #define R_MTU_TWCRA_WRE_Pos (0UL) /*!< WRE (Bit 0) */ + #define R_MTU_TWCRA_WRE_Msk (0x1UL) /*!< WRE (Bitfield-Mask: 0x01) */ + #define R_MTU_TWCRA_SCC_Pos (1UL) /*!< SCC (Bit 1) */ + #define R_MTU_TWCRA_SCC_Msk (0x2UL) /*!< SCC (Bitfield-Mask: 0x01) */ + #define R_MTU_TWCRA_CCE_Pos (7UL) /*!< CCE (Bit 7) */ + #define R_MTU_TWCRA_CCE_Msk (0x80UL) /*!< CCE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMDR2A ========================================================= */ + #define R_MTU_TMDR2A_DRS_Pos (0UL) /*!< DRS (Bit 0) */ + #define R_MTU_TMDR2A_DRS_Msk (0x1UL) /*!< DRS (Bitfield-Mask: 0x01) */ +/* ========================================================= TSTRA ========================================================= */ + #define R_MTU_TSTRA_CST0_Pos (0UL) /*!< CST0 (Bit 0) */ + #define R_MTU_TSTRA_CST0_Msk (0x1UL) /*!< CST0 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRA_CST1_Pos (1UL) /*!< CST1 (Bit 1) */ + #define R_MTU_TSTRA_CST1_Msk (0x2UL) /*!< CST1 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRA_CST2_Pos (2UL) /*!< CST2 (Bit 2) */ + #define R_MTU_TSTRA_CST2_Msk (0x4UL) /*!< CST2 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRA_CST8_Pos (3UL) /*!< CST8 (Bit 3) */ + #define R_MTU_TSTRA_CST8_Msk (0x8UL) /*!< CST8 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRA_CST3_Pos (6UL) /*!< CST3 (Bit 6) */ + #define R_MTU_TSTRA_CST3_Msk (0x40UL) /*!< CST3 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRA_CST4_Pos (7UL) /*!< CST4 (Bit 7) */ + #define R_MTU_TSTRA_CST4_Msk (0x80UL) /*!< CST4 (Bitfield-Mask: 0x01) */ +/* ========================================================= TSYRA ========================================================= */ + #define R_MTU_TSYRA_SYNC0_Pos (0UL) /*!< SYNC0 (Bit 0) */ + #define R_MTU_TSYRA_SYNC0_Msk (0x1UL) /*!< SYNC0 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSYRA_SYNC1_Pos (1UL) /*!< SYNC1 (Bit 1) */ + #define R_MTU_TSYRA_SYNC1_Msk (0x2UL) /*!< SYNC1 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSYRA_SYNC2_Pos (2UL) /*!< SYNC2 (Bit 2) */ + #define R_MTU_TSYRA_SYNC2_Msk (0x4UL) /*!< SYNC2 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSYRA_SYNC3_Pos (6UL) /*!< SYNC3 (Bit 6) */ + #define R_MTU_TSYRA_SYNC3_Msk (0x40UL) /*!< SYNC3 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSYRA_SYNC4_Pos (7UL) /*!< SYNC4 (Bit 7) */ + #define R_MTU_TSYRA_SYNC4_Msk (0x80UL) /*!< SYNC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== TCSYSTR ======================================================== */ + #define R_MTU_TCSYSTR_SCH7_Pos (0UL) /*!< SCH7 (Bit 0) */ + #define R_MTU_TCSYSTR_SCH7_Msk (0x1UL) /*!< SCH7 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH6_Pos (1UL) /*!< SCH6 (Bit 1) */ + #define R_MTU_TCSYSTR_SCH6_Msk (0x2UL) /*!< SCH6 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH4_Pos (3UL) /*!< SCH4 (Bit 3) */ + #define R_MTU_TCSYSTR_SCH4_Msk (0x8UL) /*!< SCH4 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH3_Pos (4UL) /*!< SCH3 (Bit 4) */ + #define R_MTU_TCSYSTR_SCH3_Msk (0x10UL) /*!< SCH3 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH2_Pos (5UL) /*!< SCH2 (Bit 5) */ + #define R_MTU_TCSYSTR_SCH2_Msk (0x20UL) /*!< SCH2 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH1_Pos (6UL) /*!< SCH1 (Bit 6) */ + #define R_MTU_TCSYSTR_SCH1_Msk (0x40UL) /*!< SCH1 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH0_Pos (7UL) /*!< SCH0 (Bit 7) */ + #define R_MTU_TCSYSTR_SCH0_Msk (0x80UL) /*!< SCH0 (Bitfield-Mask: 0x01) */ +/* ======================================================== TRWERA ========================================================= */ + #define R_MTU_TRWERA_RWE_Pos (0UL) /*!< RWE (Bit 0) */ + #define R_MTU_TRWERA_RWE_Msk (0x1UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ========================================================= TOERB ========================================================= */ + #define R_MTU_TOERB_OE6B_Pos (0UL) /*!< OE6B (Bit 0) */ + #define R_MTU_TOERB_OE6B_Msk (0x1UL) /*!< OE6B (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERB_OE7A_Pos (1UL) /*!< OE7A (Bit 1) */ + #define R_MTU_TOERB_OE7A_Msk (0x2UL) /*!< OE7A (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERB_OE7B_Pos (2UL) /*!< OE7B (Bit 2) */ + #define R_MTU_TOERB_OE7B_Msk (0x4UL) /*!< OE7B (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERB_OE6D_Pos (3UL) /*!< OE6D (Bit 3) */ + #define R_MTU_TOERB_OE6D_Msk (0x8UL) /*!< OE6D (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERB_OE7C_Pos (4UL) /*!< OE7C (Bit 4) */ + #define R_MTU_TOERB_OE7C_Msk (0x10UL) /*!< OE7C (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERB_OE7D_Pos (5UL) /*!< OE7D (Bit 5) */ + #define R_MTU_TOERB_OE7D_Msk (0x20UL) /*!< OE7D (Bitfield-Mask: 0x01) */ +/* ======================================================== TOCR1B ========================================================= */ + #define R_MTU_TOCR1B_OLSP_Pos (0UL) /*!< OLSP (Bit 0) */ + #define R_MTU_TOCR1B_OLSP_Msk (0x1UL) /*!< OLSP (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1B_OLSN_Pos (1UL) /*!< OLSN (Bit 1) */ + #define R_MTU_TOCR1B_OLSN_Msk (0x2UL) /*!< OLSN (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1B_TOCS_Pos (2UL) /*!< TOCS (Bit 2) */ + #define R_MTU_TOCR1B_TOCS_Msk (0x4UL) /*!< TOCS (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1B_TOCL_Pos (3UL) /*!< TOCL (Bit 3) */ + #define R_MTU_TOCR1B_TOCL_Msk (0x8UL) /*!< TOCL (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1B_PSYE_Pos (6UL) /*!< PSYE (Bit 6) */ + #define R_MTU_TOCR1B_PSYE_Msk (0x40UL) /*!< PSYE (Bitfield-Mask: 0x01) */ +/* ======================================================== TOCR2B ========================================================= */ + #define R_MTU_TOCR2B_OLS1P_Pos (0UL) /*!< OLS1P (Bit 0) */ + #define R_MTU_TOCR2B_OLS1P_Msk (0x1UL) /*!< OLS1P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_OLS1N_Pos (1UL) /*!< OLS1N (Bit 1) */ + #define R_MTU_TOCR2B_OLS1N_Msk (0x2UL) /*!< OLS1N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_OLS2P_Pos (2UL) /*!< OLS2P (Bit 2) */ + #define R_MTU_TOCR2B_OLS2P_Msk (0x4UL) /*!< OLS2P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_OLS2N_Pos (3UL) /*!< OLS2N (Bit 3) */ + #define R_MTU_TOCR2B_OLS2N_Msk (0x8UL) /*!< OLS2N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_OLS3P_Pos (4UL) /*!< OLS3P (Bit 4) */ + #define R_MTU_TOCR2B_OLS3P_Msk (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_OLS3N_Pos (5UL) /*!< OLS3N (Bit 5) */ + #define R_MTU_TOCR2B_OLS3N_Msk (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_BF_Pos (6UL) /*!< BF (Bit 6) */ + #define R_MTU_TOCR2B_BF_Msk (0xc0UL) /*!< BF (Bitfield-Mask: 0x03) */ +/* ========================================================= TCDRB ========================================================= */ +/* ========================================================= TDDRB ========================================================= */ +/* ======================================================== TCNTSB ========================================================= */ +/* ========================================================= TCBRB ========================================================= */ +/* ======================================================== TITCR1B ======================================================== */ + #define R_MTU_TITCR1B_T7VCOR_Pos (0UL) /*!< T7VCOR (Bit 0) */ + #define R_MTU_TITCR1B_T7VCOR_Msk (0x7UL) /*!< T7VCOR (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCR1B_T7VEN_Pos (3UL) /*!< T7VEN (Bit 3) */ + #define R_MTU_TITCR1B_T7VEN_Msk (0x8UL) /*!< T7VEN (Bitfield-Mask: 0x01) */ + #define R_MTU_TITCR1B_T6ACOR_Pos (4UL) /*!< T6ACOR (Bit 4) */ + #define R_MTU_TITCR1B_T6ACOR_Msk (0x70UL) /*!< T6ACOR (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCR1B_T6AEN_Pos (7UL) /*!< T6AEN (Bit 7) */ + #define R_MTU_TITCR1B_T6AEN_Msk (0x80UL) /*!< T6AEN (Bitfield-Mask: 0x01) */ +/* ======================================================= TITCNT1B ======================================================== */ + #define R_MTU_TITCNT1B_T7VCNT_Pos (0UL) /*!< T7VCNT (Bit 0) */ + #define R_MTU_TITCNT1B_T7VCNT_Msk (0x7UL) /*!< T7VCNT (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCNT1B_T6ACNT_Pos (4UL) /*!< T6ACNT (Bit 4) */ + #define R_MTU_TITCNT1B_T6ACNT_Msk (0x70UL) /*!< T6ACNT (Bitfield-Mask: 0x07) */ +/* ======================================================== TBTERB ========================================================= */ + #define R_MTU_TBTERB_BTE_Pos (0UL) /*!< BTE (Bit 0) */ + #define R_MTU_TBTERB_BTE_Msk (0x3UL) /*!< BTE (Bitfield-Mask: 0x03) */ +/* ========================================================= TDERB ========================================================= */ + #define R_MTU_TDERB_TDER_Pos (0UL) /*!< TDER (Bit 0) */ + #define R_MTU_TDERB_TDER_Msk (0x1UL) /*!< TDER (Bitfield-Mask: 0x01) */ +/* ======================================================== TOLBRB ========================================================= */ + #define R_MTU_TOLBRB_OLS1P_Pos (0UL) /*!< OLS1P (Bit 0) */ + #define R_MTU_TOLBRB_OLS1P_Msk (0x1UL) /*!< OLS1P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRB_OLS1N_Pos (1UL) /*!< OLS1N (Bit 1) */ + #define R_MTU_TOLBRB_OLS1N_Msk (0x2UL) /*!< OLS1N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRB_OLS2P_Pos (2UL) /*!< OLS2P (Bit 2) */ + #define R_MTU_TOLBRB_OLS2P_Msk (0x4UL) /*!< OLS2P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRB_OLS2N_Pos (3UL) /*!< OLS2N (Bit 3) */ + #define R_MTU_TOLBRB_OLS2N_Msk (0x8UL) /*!< OLS2N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRB_OLS3P_Pos (4UL) /*!< OLS3P (Bit 4) */ + #define R_MTU_TOLBRB_OLS3P_Msk (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRB_OLS3N_Pos (5UL) /*!< OLS3N (Bit 5) */ + #define R_MTU_TOLBRB_OLS3N_Msk (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01) */ +/* ======================================================== TITMRB ========================================================= */ + #define R_MTU_TITMRB_TITM_Pos (0UL) /*!< TITM (Bit 0) */ + #define R_MTU_TITMRB_TITM_Msk (0x1UL) /*!< TITM (Bitfield-Mask: 0x01) */ +/* ======================================================== TITCR2B ======================================================== */ + #define R_MTU_TITCR2B_TRG7COR_Pos (0UL) /*!< TRG7COR (Bit 0) */ + #define R_MTU_TITCR2B_TRG7COR_Msk (0x7UL) /*!< TRG7COR (Bitfield-Mask: 0x07) */ +/* ======================================================= TITCNT2B ======================================================== */ + #define R_MTU_TITCNT2B_TRG7CNT_Pos (0UL) /*!< TRG7CNT (Bit 0) */ + #define R_MTU_TITCNT2B_TRG7CNT_Msk (0x7UL) /*!< TRG7CNT (Bitfield-Mask: 0x07) */ +/* ========================================================= TWCRB ========================================================= */ + #define R_MTU_TWCRB_WRE_Pos (0UL) /*!< WRE (Bit 0) */ + #define R_MTU_TWCRB_WRE_Msk (0x1UL) /*!< WRE (Bitfield-Mask: 0x01) */ + #define R_MTU_TWCRB_SCC_Pos (1UL) /*!< SCC (Bit 1) */ + #define R_MTU_TWCRB_SCC_Msk (0x2UL) /*!< SCC (Bitfield-Mask: 0x01) */ + #define R_MTU_TWCRB_CCE_Pos (7UL) /*!< CCE (Bit 7) */ + #define R_MTU_TWCRB_CCE_Msk (0x80UL) /*!< CCE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMDR2B ========================================================= */ + #define R_MTU_TMDR2B_DRS_Pos (0UL) /*!< DRS (Bit 0) */ + #define R_MTU_TMDR2B_DRS_Msk (0x1UL) /*!< DRS (Bitfield-Mask: 0x01) */ +/* ========================================================= TSTRB ========================================================= */ + #define R_MTU_TSTRB_CST6_Pos (6UL) /*!< CST6 (Bit 6) */ + #define R_MTU_TSTRB_CST6_Msk (0x40UL) /*!< CST6 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRB_CST7_Pos (7UL) /*!< CST7 (Bit 7) */ + #define R_MTU_TSTRB_CST7_Msk (0x80UL) /*!< CST7 (Bitfield-Mask: 0x01) */ +/* ========================================================= TSYRB ========================================================= */ + #define R_MTU_TSYRB_SYNC6_Pos (6UL) /*!< SYNC6 (Bit 6) */ + #define R_MTU_TSYRB_SYNC6_Msk (0x40UL) /*!< SYNC6 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSYRB_SYNC7_Pos (7UL) /*!< SYNC7 (Bit 7) */ + #define R_MTU_TSYRB_SYNC7_Msk (0x80UL) /*!< SYNC7 (Bitfield-Mask: 0x01) */ +/* ======================================================== TRWERB ========================================================= */ + #define R_MTU_TRWERB_RWE_Pos (0UL) /*!< RWE (Bit 0) */ + #define R_MTU_TRWERB_RWE_Msk (0x1UL) /*!< RWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU3 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU3_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU3_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU3_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU3_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU3_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU3_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU3_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU3_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU3_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU3_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU3_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU3_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU3_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU3_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU3_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU3_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU3_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU3_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU3_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU3_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU3_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU3_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU3_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU3_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU3_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU3_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU3_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU3_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU3_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU3_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU3_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU3_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU3_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU3_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU3_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU3_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU3_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU3_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU3_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU3_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TBTM ========================================================== */ + #define R_MTU3_TBTM_TTSA_Pos (0UL) /*!< TTSA (Bit 0) */ + #define R_MTU3_TBTM_TTSA_Msk (0x1UL) /*!< TTSA (Bitfield-Mask: 0x01) */ + #define R_MTU3_TBTM_TTSB_Pos (1UL) /*!< TTSB (Bit 1) */ + #define R_MTU3_TBTM_TTSB_Msk (0x2UL) /*!< TTSB (Bitfield-Mask: 0x01) */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU3_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU3_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ +/* ========================================================= TGRE ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MTU4 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU4_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU4_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU4_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU4_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU4_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU4_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU4_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU4_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU4_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU4_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU4_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU4_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU4_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU4_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU4_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU4_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU4_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU4_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU4_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU4_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU4_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU4_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU4_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU4_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU4_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU4_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TTGE2_Pos (6UL) /*!< TTGE2 (Bit 6) */ + #define R_MTU4_TIER_TTGE2_Msk (0x40UL) /*!< TTGE2 (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU4_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU4_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU4_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU4_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU4_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU4_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU4_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU4_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU4_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TBTM ========================================================== */ + #define R_MTU4_TBTM_TTSA_Pos (0UL) /*!< TTSA (Bit 0) */ + #define R_MTU4_TBTM_TTSA_Msk (0x1UL) /*!< TTSA (Bitfield-Mask: 0x01) */ + #define R_MTU4_TBTM_TTSB_Pos (1UL) /*!< TTSB (Bit 1) */ + #define R_MTU4_TBTM_TTSB_Msk (0x2UL) /*!< TTSB (Bitfield-Mask: 0x01) */ +/* ========================================================= TADCR ========================================================= */ + #define R_MTU4_TADCR_ITB4VE_Pos (0UL) /*!< ITB4VE (Bit 0) */ + #define R_MTU4_TADCR_ITB4VE_Msk (0x1UL) /*!< ITB4VE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_ITB3AE_Pos (1UL) /*!< ITB3AE (Bit 1) */ + #define R_MTU4_TADCR_ITB3AE_Msk (0x2UL) /*!< ITB3AE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_ITA4VE_Pos (2UL) /*!< ITA4VE (Bit 2) */ + #define R_MTU4_TADCR_ITA4VE_Msk (0x4UL) /*!< ITA4VE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_ITA3AE_Pos (3UL) /*!< ITA3AE (Bit 3) */ + #define R_MTU4_TADCR_ITA3AE_Msk (0x8UL) /*!< ITA3AE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_DT4BE_Pos (4UL) /*!< DT4BE (Bit 4) */ + #define R_MTU4_TADCR_DT4BE_Msk (0x10UL) /*!< DT4BE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_UT4BE_Pos (5UL) /*!< UT4BE (Bit 5) */ + #define R_MTU4_TADCR_UT4BE_Msk (0x20UL) /*!< UT4BE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_DT4AE_Pos (6UL) /*!< DT4AE (Bit 6) */ + #define R_MTU4_TADCR_DT4AE_Msk (0x40UL) /*!< DT4AE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_UT4AE_Pos (7UL) /*!< UT4AE (Bit 7) */ + #define R_MTU4_TADCR_UT4AE_Msk (0x80UL) /*!< UT4AE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_BF_Pos (14UL) /*!< BF (Bit 14) */ + #define R_MTU4_TADCR_BF_Msk (0xc000UL) /*!< BF (Bitfield-Mask: 0x03) */ +/* ======================================================== TADCORA ======================================================== */ +/* ======================================================== TADCORB ======================================================== */ +/* ======================================================= TADCOBRA ======================================================== */ +/* ======================================================= TADCOBRB ======================================================== */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU4_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU4_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ +/* ========================================================= TGRE ========================================================== */ +/* ========================================================= TGRF ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MTU_NF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NFCR0 ========================================================= */ + #define R_MTU_NF_NFCR0_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR0_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR0_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR0_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR0_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR0_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR0_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR0_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR0_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR0_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR1 ========================================================= */ + #define R_MTU_NF_NFCR1_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR1_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR1_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR1_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR1_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR1_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR2 ========================================================= */ + #define R_MTU_NF_NFCR2_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR2_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR2_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR2_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR2_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR2_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR3 ========================================================= */ + #define R_MTU_NF_NFCR3_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR3_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR3_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR3_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR3_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR3_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR3_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR3_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR3_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR3_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR4 ========================================================= */ + #define R_MTU_NF_NFCR4_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR4_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR4_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR4_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR4_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR4_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR4_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR4_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR4_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR4_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR8 ========================================================= */ + #define R_MTU_NF_NFCR8_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR8_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR8_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR8_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR8_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR8_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR8_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR8_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR8_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR8_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCRC ========================================================= */ + #define R_MTU_NF_NFCRC_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCRC_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCRC_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCRC_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCRC_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCRC_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCRC_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCRC_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCRC_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCRC_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR6 ========================================================= */ + #define R_MTU_NF_NFCR6_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR6_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR6_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR6_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR6_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR6_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR6_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR6_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR6_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR6_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR7 ========================================================= */ + #define R_MTU_NF_NFCR7_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR7_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR7_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR7_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR7_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR7_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR7_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR7_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR7_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR7_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR5 ========================================================= */ + #define R_MTU_NF_NFCR5_NFUEN_Pos (0UL) /*!< NFUEN (Bit 0) */ + #define R_MTU_NF_NFCR5_NFUEN_Msk (0x1UL) /*!< NFUEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR5_NFVEN_Pos (1UL) /*!< NFVEN (Bit 1) */ + #define R_MTU_NF_NFCR5_NFVEN_Msk (0x2UL) /*!< NFVEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR5_NFWEN_Pos (2UL) /*!< NFWEN (Bit 2) */ + #define R_MTU_NF_NFCR5_NFWEN_Msk (0x4UL) /*!< NFWEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR5_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR5_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU0_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU0_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU0_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU0_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU0_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU0_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU0_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU0_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU0_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU0_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU0_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU0_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ + #define R_MTU0_TMDR1_BFE_Pos (6UL) /*!< BFE (Bit 6) */ + #define R_MTU0_TMDR1_BFE_Msk (0x40UL) /*!< BFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU0_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU0_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU0_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU0_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU0_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU0_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU0_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU0_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU0_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU0_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU0_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU0_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU0_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU0_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU0_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ +/* ========================================================= TGRE ========================================================== */ +/* ========================================================= TGRF ========================================================== */ +/* ========================================================= TIER2 ========================================================= */ + #define R_MTU0_TIER2_TGIEE_Pos (0UL) /*!< TGIEE (Bit 0) */ + #define R_MTU0_TIER2_TGIEE_Msk (0x1UL) /*!< TGIEE (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER2_TGIEF_Pos (1UL) /*!< TGIEF (Bit 1) */ + #define R_MTU0_TIER2_TGIEF_Msk (0x2UL) /*!< TGIEF (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER2_TTGE2_Pos (7UL) /*!< TTGE2 (Bit 7) */ + #define R_MTU0_TIER2_TTGE2_Msk (0x80UL) /*!< TTGE2 (Bitfield-Mask: 0x01) */ +/* ========================================================= TBTM ========================================================== */ + #define R_MTU0_TBTM_TTSA_Pos (0UL) /*!< TTSA (Bit 0) */ + #define R_MTU0_TBTM_TTSA_Msk (0x1UL) /*!< TTSA (Bitfield-Mask: 0x01) */ + #define R_MTU0_TBTM_TTSB_Pos (1UL) /*!< TTSB (Bit 1) */ + #define R_MTU0_TBTM_TTSB_Msk (0x2UL) /*!< TTSB (Bitfield-Mask: 0x01) */ + #define R_MTU0_TBTM_TTSE_Pos (2UL) /*!< TTSE (Bit 2) */ + #define R_MTU0_TBTM_TTSE_Msk (0x4UL) /*!< TTSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU0_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU0_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU1_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU1_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU1_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU1_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU1_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU1_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU1_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU1_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIOR ========================================================== */ + #define R_MTU1_TIOR_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU1_TIOR_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU1_TIOR_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU1_TIOR_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU1_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU1_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU1_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU1_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU1_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU1_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU1_TIER_TCIEU_Pos (5UL) /*!< TCIEU (Bit 5) */ + #define R_MTU1_TIER_TCIEU_Msk (0x20UL) /*!< TCIEU (Bitfield-Mask: 0x01) */ + #define R_MTU1_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU1_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU1_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU1_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU1_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU1_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU1_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU1_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU1_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU1_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TICCR ========================================================= */ + #define R_MTU1_TICCR_I1AE_Pos (0UL) /*!< I1AE (Bit 0) */ + #define R_MTU1_TICCR_I1AE_Msk (0x1UL) /*!< I1AE (Bitfield-Mask: 0x01) */ + #define R_MTU1_TICCR_I1BE_Pos (1UL) /*!< I1BE (Bit 1) */ + #define R_MTU1_TICCR_I1BE_Msk (0x2UL) /*!< I1BE (Bitfield-Mask: 0x01) */ + #define R_MTU1_TICCR_I2AE_Pos (2UL) /*!< I2AE (Bit 2) */ + #define R_MTU1_TICCR_I2AE_Msk (0x4UL) /*!< I2AE (Bitfield-Mask: 0x01) */ + #define R_MTU1_TICCR_I2BE_Pos (3UL) /*!< I2BE (Bit 3) */ + #define R_MTU1_TICCR_I2BE_Msk (0x8UL) /*!< I2BE (Bitfield-Mask: 0x01) */ +/* ========================================================= TMDR3 ========================================================= */ + #define R_MTU1_TMDR3_LWA_Pos (0UL) /*!< LWA (Bit 0) */ + #define R_MTU1_TMDR3_LWA_Msk (0x1UL) /*!< LWA (Bitfield-Mask: 0x01) */ + #define R_MTU1_TMDR3_PHCKSEL_Pos (1UL) /*!< PHCKSEL (Bit 1) */ + #define R_MTU1_TMDR3_PHCKSEL_Msk (0x2UL) /*!< PHCKSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU1_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU1_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + #define R_MTU1_TCR2_PCB_Pos (3UL) /*!< PCB (Bit 3) */ + #define R_MTU1_TCR2_PCB_Msk (0x18UL) /*!< PCB (Bitfield-Mask: 0x03) */ +/* ======================================================== TCNTLW ========================================================= */ +/* ======================================================== TGRALW ========================================================= */ +/* ======================================================== TGRBLW ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_MTU2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU2_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU2_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU2_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU2_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU2_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU2_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU2_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU2_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIOR ========================================================== */ + #define R_MTU2_TIOR_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU2_TIOR_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU2_TIOR_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU2_TIOR_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU2_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU2_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU2_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU2_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU2_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU2_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU2_TIER_TCIEU_Pos (5UL) /*!< TCIEU (Bit 5) */ + #define R_MTU2_TIER_TCIEU_Msk (0x20UL) /*!< TCIEU (Bitfield-Mask: 0x01) */ + #define R_MTU2_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU2_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU2_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU2_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU2_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU2_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU2_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU2_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU2_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU2_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU2_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU2_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + #define R_MTU2_TCR2_PCB_Pos (3UL) /*!< PCB (Bit 3) */ + #define R_MTU2_TCR2_PCB_Msk (0x18UL) /*!< PCB (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU8 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU8_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU8_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU8_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU8_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU8_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU8_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU8_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU8_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU8_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU8_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU8_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU8_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU8_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU8_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU8_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU8_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU8_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU8_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU8_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU8_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU8_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU8_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU8_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU8_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU8_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU8_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU8_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU8_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU8_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU8_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU8_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU8_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MTU6 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU6_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU6_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU6_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU6_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU6_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU6_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU6_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU6_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU6_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU6_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU6_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU6_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU6_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU6_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU6_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU6_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU6_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU6_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU6_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU6_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU6_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU6_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU6_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU6_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU6_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU6_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU6_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU6_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU6_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU6_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU6_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU6_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU6_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU6_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU6_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU6_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU6_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU6_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU6_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU6_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TBTM ========================================================== */ + #define R_MTU6_TBTM_TTSA_Pos (0UL) /*!< TTSA (Bit 0) */ + #define R_MTU6_TBTM_TTSA_Msk (0x1UL) /*!< TTSA (Bitfield-Mask: 0x01) */ + #define R_MTU6_TBTM_TTSB_Pos (1UL) /*!< TTSB (Bit 1) */ + #define R_MTU6_TBTM_TTSB_Msk (0x2UL) /*!< TTSB (Bitfield-Mask: 0x01) */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU6_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU6_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ +/* ========================================================= TSYCR ========================================================= */ + #define R_MTU6_TSYCR_CE2B_Pos (0UL) /*!< CE2B (Bit 0) */ + #define R_MTU6_TSYCR_CE2B_Msk (0x1UL) /*!< CE2B (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE2A_Pos (1UL) /*!< CE2A (Bit 1) */ + #define R_MTU6_TSYCR_CE2A_Msk (0x2UL) /*!< CE2A (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE1B_Pos (2UL) /*!< CE1B (Bit 2) */ + #define R_MTU6_TSYCR_CE1B_Msk (0x4UL) /*!< CE1B (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE1A_Pos (3UL) /*!< CE1A (Bit 3) */ + #define R_MTU6_TSYCR_CE1A_Msk (0x8UL) /*!< CE1A (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE0D_Pos (4UL) /*!< CE0D (Bit 4) */ + #define R_MTU6_TSYCR_CE0D_Msk (0x10UL) /*!< CE0D (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE0C_Pos (5UL) /*!< CE0C (Bit 5) */ + #define R_MTU6_TSYCR_CE0C_Msk (0x20UL) /*!< CE0C (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE0B_Pos (6UL) /*!< CE0B (Bit 6) */ + #define R_MTU6_TSYCR_CE0B_Msk (0x40UL) /*!< CE0B (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE0A_Pos (7UL) /*!< CE0A (Bit 7) */ + #define R_MTU6_TSYCR_CE0A_Msk (0x80UL) /*!< CE0A (Bitfield-Mask: 0x01) */ +/* ========================================================= TGRE ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MTU7 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU7_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU7_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU7_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU7_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU7_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU7_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU7_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU7_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU7_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU7_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU7_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU7_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU7_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU7_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU7_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU7_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU7_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU7_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU7_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU7_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU7_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU7_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU7_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU7_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU7_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU7_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TTGE2_Pos (6UL) /*!< TTGE2 (Bit 6) */ + #define R_MTU7_TIER_TTGE2_Msk (0x40UL) /*!< TTGE2 (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU7_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU7_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU7_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU7_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU7_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU7_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU7_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU7_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU7_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TBTM ========================================================== */ + #define R_MTU7_TBTM_TTSA_Pos (0UL) /*!< TTSA (Bit 0) */ + #define R_MTU7_TBTM_TTSA_Msk (0x1UL) /*!< TTSA (Bitfield-Mask: 0x01) */ + #define R_MTU7_TBTM_TTSB_Pos (1UL) /*!< TTSB (Bit 1) */ + #define R_MTU7_TBTM_TTSB_Msk (0x2UL) /*!< TTSB (Bitfield-Mask: 0x01) */ +/* ========================================================= TADCR ========================================================= */ + #define R_MTU7_TADCR_ITB7VE_Pos (0UL) /*!< ITB7VE (Bit 0) */ + #define R_MTU7_TADCR_ITB7VE_Msk (0x1UL) /*!< ITB7VE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_ITB6AE_Pos (1UL) /*!< ITB6AE (Bit 1) */ + #define R_MTU7_TADCR_ITB6AE_Msk (0x2UL) /*!< ITB6AE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_ITA7VE_Pos (2UL) /*!< ITA7VE (Bit 2) */ + #define R_MTU7_TADCR_ITA7VE_Msk (0x4UL) /*!< ITA7VE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_ITA6AE_Pos (3UL) /*!< ITA6AE (Bit 3) */ + #define R_MTU7_TADCR_ITA6AE_Msk (0x8UL) /*!< ITA6AE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_DT7BE_Pos (4UL) /*!< DT7BE (Bit 4) */ + #define R_MTU7_TADCR_DT7BE_Msk (0x10UL) /*!< DT7BE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_UT7BE_Pos (5UL) /*!< UT7BE (Bit 5) */ + #define R_MTU7_TADCR_UT7BE_Msk (0x20UL) /*!< UT7BE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_DT7AE_Pos (6UL) /*!< DT7AE (Bit 6) */ + #define R_MTU7_TADCR_DT7AE_Msk (0x40UL) /*!< DT7AE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_UT7AE_Pos (7UL) /*!< UT7AE (Bit 7) */ + #define R_MTU7_TADCR_UT7AE_Msk (0x80UL) /*!< UT7AE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_BF_Pos (14UL) /*!< BF (Bit 14) */ + #define R_MTU7_TADCR_BF_Msk (0xc000UL) /*!< BF (Bitfield-Mask: 0x03) */ +/* ======================================================== TADCORA ======================================================== */ +/* ======================================================== TADCORB ======================================================== */ +/* ======================================================= TADCOBRA ======================================================== */ +/* ======================================================= TADCOBRB ======================================================== */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU7_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU7_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ +/* ========================================================= TGRE ========================================================== */ +/* ========================================================= TGRF ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MTU5 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TCNTU ========================================================= */ +/* ========================================================= TGRU ========================================================== */ +/* ========================================================= TCRU ========================================================== */ + #define R_MTU5_TCRU_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU5_TCRU_TPSC_Msk (0x3UL) /*!< TPSC (Bitfield-Mask: 0x03) */ +/* ========================================================= TCR2U ========================================================= */ + #define R_MTU5_TCR2U_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU5_TCR2U_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + #define R_MTU5_TCR2U_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU5_TCR2U_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ +/* ========================================================= TIORU ========================================================= */ + #define R_MTU5_TIORU_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU5_TIORU_IOC_Msk (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f) */ +/* ========================================================= TCNTV ========================================================= */ +/* ========================================================= TGRV ========================================================== */ +/* ========================================================= TCRV ========================================================== */ + #define R_MTU5_TCRV_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU5_TCRV_TPSC_Msk (0x3UL) /*!< TPSC (Bitfield-Mask: 0x03) */ +/* ========================================================= TCR2V ========================================================= */ + #define R_MTU5_TCR2V_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU5_TCR2V_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + #define R_MTU5_TCR2V_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU5_TCR2V_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ +/* ========================================================= TIORV ========================================================= */ + #define R_MTU5_TIORV_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU5_TIORV_IOC_Msk (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f) */ +/* ========================================================= TCNTW ========================================================= */ +/* ========================================================= TGRW ========================================================== */ +/* ========================================================= TCRW ========================================================== */ + #define R_MTU5_TCRW_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU5_TCRW_TPSC_Msk (0x3UL) /*!< TPSC (Bitfield-Mask: 0x03) */ +/* ========================================================= TCR2W ========================================================= */ + #define R_MTU5_TCR2W_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU5_TCR2W_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + #define R_MTU5_TCR2W_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU5_TCR2W_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ +/* ========================================================= TIORW ========================================================= */ + #define R_MTU5_TIORW_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU5_TIORW_IOC_Msk (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU5_TIER_TGIE5W_Pos (0UL) /*!< TGIE5W (Bit 0) */ + #define R_MTU5_TIER_TGIE5W_Msk (0x1UL) /*!< TGIE5W (Bitfield-Mask: 0x01) */ + #define R_MTU5_TIER_TGIE5V_Pos (1UL) /*!< TGIE5V (Bit 1) */ + #define R_MTU5_TIER_TGIE5V_Msk (0x2UL) /*!< TGIE5V (Bitfield-Mask: 0x01) */ + #define R_MTU5_TIER_TGIE5U_Pos (2UL) /*!< TGIE5U (Bit 2) */ + #define R_MTU5_TIER_TGIE5U_Msk (0x4UL) /*!< TGIE5U (Bitfield-Mask: 0x01) */ +/* ========================================================= TSTR ========================================================== */ + #define R_MTU5_TSTR_CSTW5_Pos (0UL) /*!< CSTW5 (Bit 0) */ + #define R_MTU5_TSTR_CSTW5_Msk (0x1UL) /*!< CSTW5 (Bitfield-Mask: 0x01) */ + #define R_MTU5_TSTR_CSTV5_Pos (1UL) /*!< CSTV5 (Bit 1) */ + #define R_MTU5_TSTR_CSTV5_Msk (0x2UL) /*!< CSTV5 (Bitfield-Mask: 0x01) */ + #define R_MTU5_TSTR_CSTU5_Pos (2UL) /*!< CSTU5 (Bit 2) */ + #define R_MTU5_TSTR_CSTU5_Msk (0x4UL) /*!< CSTU5 (Bitfield-Mask: 0x01) */ +/* ====================================================== TCNTCMPCLR ======================================================= */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5W_Pos (0UL) /*!< CMPCLR5W (Bit 0) */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5W_Msk (0x1UL) /*!< CMPCLR5W (Bitfield-Mask: 0x01) */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5V_Pos (1UL) /*!< CMPCLR5V (Bit 1) */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5V_Msk (0x2UL) /*!< CMPCLR5V (Bitfield-Mask: 0x01) */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5U_Pos (2UL) /*!< CMPCLR5U (Bit 2) */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5U_Msk (0x4UL) /*!< CMPCLR5U (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TFU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TRGSTS ========================================================= */ + #define R_TFU_TRGSTS_BSYF_Pos (0UL) /*!< BSYF (Bit 0) */ + #define R_TFU_TRGSTS_BSYF_Msk (0x1UL) /*!< BSYF (Bitfield-Mask: 0x01) */ + #define R_TFU_TRGSTS_ERRF_Pos (1UL) /*!< ERRF (Bit 1) */ + #define R_TFU_TRGSTS_ERRF_Msk (0x2UL) /*!< ERRF (Bitfield-Mask: 0x01) */ +/* ========================================================= SCDT0 ========================================================= */ + #define R_TFU_SCDT0_SCDT0_Pos (0UL) /*!< SCDT0 (Bit 0) */ + #define R_TFU_SCDT0_SCDT0_Msk (0xffffffffUL) /*!< SCDT0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SCDT1 ========================================================= */ + #define R_TFU_SCDT1_SCDT1_Pos (0UL) /*!< SCDT1 (Bit 0) */ + #define R_TFU_SCDT1_SCDT1_Msk (0xffffffffUL) /*!< SCDT1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ATDT0 ========================================================= */ + #define R_TFU_ATDT0_ATDT0_Pos (0UL) /*!< ATDT0 (Bit 0) */ + #define R_TFU_ATDT0_ATDT0_Msk (0xffffffffUL) /*!< ATDT0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ATDT1 ========================================================= */ + #define R_TFU_ATDT1_ATDT1_Pos (0UL) /*!< ATDT1 (Bit 0) */ + #define R_TFU_ATDT1_ATDT1_Msk (0xffffffffUL) /*!< ATDT1 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_POE3 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICSR1 ========================================================= */ + #define R_POE3_ICSR1_POE0M_Pos (0UL) /*!< POE0M (Bit 0) */ + #define R_POE3_ICSR1_POE0M_Msk (0x3UL) /*!< POE0M (Bitfield-Mask: 0x03) */ + #define R_POE3_ICSR1_PIE1_Pos (8UL) /*!< PIE1 (Bit 8) */ + #define R_POE3_ICSR1_PIE1_Msk (0x100UL) /*!< PIE1 (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR1_POE0F_Pos (12UL) /*!< POE0F (Bit 12) */ + #define R_POE3_ICSR1_POE0F_Msk (0x1000UL) /*!< POE0F (Bitfield-Mask: 0x01) */ +/* ========================================================= OCSR1 ========================================================= */ + #define R_POE3_OCSR1_OIE1_Pos (8UL) /*!< OIE1 (Bit 8) */ + #define R_POE3_OCSR1_OIE1_Msk (0x100UL) /*!< OIE1 (Bitfield-Mask: 0x01) */ + #define R_POE3_OCSR1_OCE1_Pos (9UL) /*!< OCE1 (Bit 9) */ + #define R_POE3_OCSR1_OCE1_Msk (0x200UL) /*!< OCE1 (Bitfield-Mask: 0x01) */ + #define R_POE3_OCSR1_OSF1_Pos (15UL) /*!< OSF1 (Bit 15) */ + #define R_POE3_OCSR1_OSF1_Msk (0x8000UL) /*!< OSF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_POE3_ICSR2_POE4M_Pos (0UL) /*!< POE4M (Bit 0) */ + #define R_POE3_ICSR2_POE4M_Msk (0x3UL) /*!< POE4M (Bitfield-Mask: 0x03) */ + #define R_POE3_ICSR2_PIE2_Pos (8UL) /*!< PIE2 (Bit 8) */ + #define R_POE3_ICSR2_PIE2_Msk (0x100UL) /*!< PIE2 (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR2_POE4F_Pos (12UL) /*!< POE4F (Bit 12) */ + #define R_POE3_ICSR2_POE4F_Msk (0x1000UL) /*!< POE4F (Bitfield-Mask: 0x01) */ +/* ========================================================= OCSR2 ========================================================= */ + #define R_POE3_OCSR2_OIE2_Pos (8UL) /*!< OIE2 (Bit 8) */ + #define R_POE3_OCSR2_OIE2_Msk (0x100UL) /*!< OIE2 (Bitfield-Mask: 0x01) */ + #define R_POE3_OCSR2_OCE2_Pos (9UL) /*!< OCE2 (Bit 9) */ + #define R_POE3_OCSR2_OCE2_Msk (0x200UL) /*!< OCE2 (Bitfield-Mask: 0x01) */ + #define R_POE3_OCSR2_OSF2_Pos (15UL) /*!< OSF2 (Bit 15) */ + #define R_POE3_OCSR2_OSF2_Msk (0x8000UL) /*!< OSF2 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR3 ========================================================= */ + #define R_POE3_ICSR3_POE8M_Pos (0UL) /*!< POE8M (Bit 0) */ + #define R_POE3_ICSR3_POE8M_Msk (0x3UL) /*!< POE8M (Bitfield-Mask: 0x03) */ + #define R_POE3_ICSR3_PIE3_Pos (8UL) /*!< PIE3 (Bit 8) */ + #define R_POE3_ICSR3_PIE3_Msk (0x100UL) /*!< PIE3 (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR3_POE8E_Pos (9UL) /*!< POE8E (Bit 9) */ + #define R_POE3_ICSR3_POE8E_Msk (0x200UL) /*!< POE8E (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR3_POE8F_Pos (12UL) /*!< POE8F (Bit 12) */ + #define R_POE3_ICSR3_POE8F_Msk (0x1000UL) /*!< POE8F (Bitfield-Mask: 0x01) */ +/* ========================================================= SPOER ========================================================= */ + #define R_POE3_SPOER_MTUCH34HIZ_Pos (0UL) /*!< MTUCH34HIZ (Bit 0) */ + #define R_POE3_SPOER_MTUCH34HIZ_Msk (0x1UL) /*!< MTUCH34HIZ (Bitfield-Mask: 0x01) */ + #define R_POE3_SPOER_MTUCH67HIZ_Pos (1UL) /*!< MTUCH67HIZ (Bit 1) */ + #define R_POE3_SPOER_MTUCH67HIZ_Msk (0x2UL) /*!< MTUCH67HIZ (Bitfield-Mask: 0x01) */ + #define R_POE3_SPOER_MTUCH0HIZ_Pos (2UL) /*!< MTUCH0HIZ (Bit 2) */ + #define R_POE3_SPOER_MTUCH0HIZ_Msk (0x4UL) /*!< MTUCH0HIZ (Bitfield-Mask: 0x01) */ +/* ======================================================== POECR1 ========================================================= */ + #define R_POE3_POECR1_MTU0AZE_Pos (0UL) /*!< MTU0AZE (Bit 0) */ + #define R_POE3_POECR1_MTU0AZE_Msk (0x1UL) /*!< MTU0AZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR1_MTU0BZE_Pos (1UL) /*!< MTU0BZE (Bit 1) */ + #define R_POE3_POECR1_MTU0BZE_Msk (0x2UL) /*!< MTU0BZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR1_MTU0CZE_Pos (2UL) /*!< MTU0CZE (Bit 2) */ + #define R_POE3_POECR1_MTU0CZE_Msk (0x4UL) /*!< MTU0CZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR1_MTU0DZE_Pos (3UL) /*!< MTU0DZE (Bit 3) */ + #define R_POE3_POECR1_MTU0DZE_Msk (0x8UL) /*!< MTU0DZE (Bitfield-Mask: 0x01) */ +/* ======================================================== POECR2 ========================================================= */ + #define R_POE3_POECR2_MTU7BDZE_Pos (0UL) /*!< MTU7BDZE (Bit 0) */ + #define R_POE3_POECR2_MTU7BDZE_Msk (0x1UL) /*!< MTU7BDZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR2_MTU7ACZE_Pos (1UL) /*!< MTU7ACZE (Bit 1) */ + #define R_POE3_POECR2_MTU7ACZE_Msk (0x2UL) /*!< MTU7ACZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR2_MTU6BDZE_Pos (2UL) /*!< MTU6BDZE (Bit 2) */ + #define R_POE3_POECR2_MTU6BDZE_Msk (0x4UL) /*!< MTU6BDZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR2_MTU4BDZE_Pos (8UL) /*!< MTU4BDZE (Bit 8) */ + #define R_POE3_POECR2_MTU4BDZE_Msk (0x100UL) /*!< MTU4BDZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR2_MTU4ACZE_Pos (9UL) /*!< MTU4ACZE (Bit 9) */ + #define R_POE3_POECR2_MTU4ACZE_Msk (0x200UL) /*!< MTU4ACZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR2_MTU3BDZE_Pos (10UL) /*!< MTU3BDZE (Bit 10) */ + #define R_POE3_POECR2_MTU3BDZE_Msk (0x400UL) /*!< MTU3BDZE (Bitfield-Mask: 0x01) */ +/* ======================================================== POECR4 ========================================================= */ + #define R_POE3_POECR4_IC2ADDMT34ZE_Pos (2UL) /*!< IC2ADDMT34ZE (Bit 2) */ + #define R_POE3_POECR4_IC2ADDMT34ZE_Msk (0x4UL) /*!< IC2ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC3ADDMT34ZE_Pos (3UL) /*!< IC3ADDMT34ZE (Bit 3) */ + #define R_POE3_POECR4_IC3ADDMT34ZE_Msk (0x8UL) /*!< IC3ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC4ADDMT34ZE_Pos (4UL) /*!< IC4ADDMT34ZE (Bit 4) */ + #define R_POE3_POECR4_IC4ADDMT34ZE_Msk (0x10UL) /*!< IC4ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC5ADDMT34ZE_Pos (5UL) /*!< IC5ADDMT34ZE (Bit 5) */ + #define R_POE3_POECR4_IC5ADDMT34ZE_Msk (0x20UL) /*!< IC5ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_DE0ADDMT34ZE_Pos (6UL) /*!< DE0ADDMT34ZE (Bit 6) */ + #define R_POE3_POECR4_DE0ADDMT34ZE_Msk (0x40UL) /*!< DE0ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_DE1ADDMT34ZE_Pos (7UL) /*!< DE1ADDMT34ZE (Bit 7) */ + #define R_POE3_POECR4_DE1ADDMT34ZE_Msk (0x80UL) /*!< DE1ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC1ADDMT67ZE_Pos (9UL) /*!< IC1ADDMT67ZE (Bit 9) */ + #define R_POE3_POECR4_IC1ADDMT67ZE_Msk (0x200UL) /*!< IC1ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC3ADDMT67ZE_Pos (11UL) /*!< IC3ADDMT67ZE (Bit 11) */ + #define R_POE3_POECR4_IC3ADDMT67ZE_Msk (0x800UL) /*!< IC3ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC4ADDMT67ZE_Pos (12UL) /*!< IC4ADDMT67ZE (Bit 12) */ + #define R_POE3_POECR4_IC4ADDMT67ZE_Msk (0x1000UL) /*!< IC4ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC5ADDMT67ZE_Pos (13UL) /*!< IC5ADDMT67ZE (Bit 13) */ + #define R_POE3_POECR4_IC5ADDMT67ZE_Msk (0x2000UL) /*!< IC5ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_DE0ADDMT67ZE_Pos (14UL) /*!< DE0ADDMT67ZE (Bit 14) */ + #define R_POE3_POECR4_DE0ADDMT67ZE_Msk (0x4000UL) /*!< DE0ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_DE1ADDMT67ZE_Pos (15UL) /*!< DE1ADDMT67ZE (Bit 15) */ + #define R_POE3_POECR4_DE1ADDMT67ZE_Msk (0x8000UL) /*!< DE1ADDMT67ZE (Bitfield-Mask: 0x01) */ +/* ======================================================== POECR5 ========================================================= */ + #define R_POE3_POECR5_IC1ADDMT0ZE_Pos (1UL) /*!< IC1ADDMT0ZE (Bit 1) */ + #define R_POE3_POECR5_IC1ADDMT0ZE_Msk (0x2UL) /*!< IC1ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_IC2ADDMT0ZE_Pos (2UL) /*!< IC2ADDMT0ZE (Bit 2) */ + #define R_POE3_POECR5_IC2ADDMT0ZE_Msk (0x4UL) /*!< IC2ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_IC4ADDMT0ZE_Pos (4UL) /*!< IC4ADDMT0ZE (Bit 4) */ + #define R_POE3_POECR5_IC4ADDMT0ZE_Msk (0x10UL) /*!< IC4ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_IC5ADDMT0ZE_Pos (5UL) /*!< IC5ADDMT0ZE (Bit 5) */ + #define R_POE3_POECR5_IC5ADDMT0ZE_Msk (0x20UL) /*!< IC5ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_DE0ADDMT0ZE_Pos (6UL) /*!< DE0ADDMT0ZE (Bit 6) */ + #define R_POE3_POECR5_DE0ADDMT0ZE_Msk (0x40UL) /*!< DE0ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_DE1ADDMT0ZE_Pos (7UL) /*!< DE1ADDMT0ZE (Bit 7) */ + #define R_POE3_POECR5_DE1ADDMT0ZE_Msk (0x80UL) /*!< DE1ADDMT0ZE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR4 ========================================================= */ + #define R_POE3_ICSR4_POE10M_Pos (0UL) /*!< POE10M (Bit 0) */ + #define R_POE3_ICSR4_POE10M_Msk (0x3UL) /*!< POE10M (Bitfield-Mask: 0x03) */ + #define R_POE3_ICSR4_PIE4_Pos (8UL) /*!< PIE4 (Bit 8) */ + #define R_POE3_ICSR4_PIE4_Msk (0x100UL) /*!< PIE4 (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR4_POE10E_Pos (9UL) /*!< POE10E (Bit 9) */ + #define R_POE3_ICSR4_POE10E_Msk (0x200UL) /*!< POE10E (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR4_POE10F_Pos (12UL) /*!< POE10F (Bit 12) */ + #define R_POE3_ICSR4_POE10F_Msk (0x1000UL) /*!< POE10F (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR5 ========================================================= */ + #define R_POE3_ICSR5_POE11M_Pos (0UL) /*!< POE11M (Bit 0) */ + #define R_POE3_ICSR5_POE11M_Msk (0x3UL) /*!< POE11M (Bitfield-Mask: 0x03) */ + #define R_POE3_ICSR5_PIE5_Pos (8UL) /*!< PIE5 (Bit 8) */ + #define R_POE3_ICSR5_PIE5_Msk (0x100UL) /*!< PIE5 (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR5_POE11E_Pos (9UL) /*!< POE11E (Bit 9) */ + #define R_POE3_ICSR5_POE11E_Msk (0x200UL) /*!< POE11E (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR5_POE11F_Pos (12UL) /*!< POE11F (Bit 12) */ + #define R_POE3_ICSR5_POE11F_Msk (0x1000UL) /*!< POE11F (Bitfield-Mask: 0x01) */ +/* ========================================================= ALR1 ========================================================== */ + #define R_POE3_ALR1_OLSG0A_Pos (0UL) /*!< OLSG0A (Bit 0) */ + #define R_POE3_ALR1_OLSG0A_Msk (0x1UL) /*!< OLSG0A (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSG0B_Pos (1UL) /*!< OLSG0B (Bit 1) */ + #define R_POE3_ALR1_OLSG0B_Msk (0x2UL) /*!< OLSG0B (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSG1A_Pos (2UL) /*!< OLSG1A (Bit 2) */ + #define R_POE3_ALR1_OLSG1A_Msk (0x4UL) /*!< OLSG1A (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSG1B_Pos (3UL) /*!< OLSG1B (Bit 3) */ + #define R_POE3_ALR1_OLSG1B_Msk (0x8UL) /*!< OLSG1B (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSG2A_Pos (4UL) /*!< OLSG2A (Bit 4) */ + #define R_POE3_ALR1_OLSG2A_Msk (0x10UL) /*!< OLSG2A (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSG2B_Pos (5UL) /*!< OLSG2B (Bit 5) */ + #define R_POE3_ALR1_OLSG2B_Msk (0x20UL) /*!< OLSG2B (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSEN_Pos (7UL) /*!< OLSEN (Bit 7) */ + #define R_POE3_ALR1_OLSEN_Msk (0x80UL) /*!< OLSEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR6 ========================================================= */ + #define R_POE3_ICSR6_OSTSTE_Pos (9UL) /*!< OSTSTE (Bit 9) */ + #define R_POE3_ICSR6_OSTSTE_Msk (0x200UL) /*!< OSTSTE (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR6_OSTSTF_Pos (12UL) /*!< OSTSTF (Bit 12) */ + #define R_POE3_ICSR6_OSTSTF_Msk (0x1000UL) /*!< OSTSTF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR7 ========================================================= */ + #define R_POE3_ICSR7_DERR0IE_Pos (6UL) /*!< DERR0IE (Bit 6) */ + #define R_POE3_ICSR7_DERR0IE_Msk (0x40UL) /*!< DERR0IE (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR7_DERR1IE_Pos (7UL) /*!< DERR1IE (Bit 7) */ + #define R_POE3_ICSR7_DERR1IE_Msk (0x80UL) /*!< DERR1IE (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR7_DERR0ST_Pos (13UL) /*!< DERR0ST (Bit 13) */ + #define R_POE3_ICSR7_DERR0ST_Msk (0x2000UL) /*!< DERR0ST (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR7_DERR1ST_Pos (14UL) /*!< DERR1ST (Bit 14) */ + #define R_POE3_ICSR7_DERR1ST_Msk (0x4000UL) /*!< DERR1ST (Bitfield-Mask: 0x01) */ +/* ======================================================== M0SELR1 ======================================================== */ + #define R_POE3_M0SELR1_M0ASEL_Pos (0UL) /*!< M0ASEL (Bit 0) */ + #define R_POE3_M0SELR1_M0ASEL_Msk (0xfUL) /*!< M0ASEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M0SELR1_M0BSEL_Pos (4UL) /*!< M0BSEL (Bit 4) */ + #define R_POE3_M0SELR1_M0BSEL_Msk (0xf0UL) /*!< M0BSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M0SELR2 ======================================================== */ + #define R_POE3_M0SELR2_M0CSEL_Pos (0UL) /*!< M0CSEL (Bit 0) */ + #define R_POE3_M0SELR2_M0CSEL_Msk (0xfUL) /*!< M0CSEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M0SELR2_M0DSEL_Pos (4UL) /*!< M0DSEL (Bit 4) */ + #define R_POE3_M0SELR2_M0DSEL_Msk (0xf0UL) /*!< M0DSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M3SELR ========================================================= */ + #define R_POE3_M3SELR_M3BSEL_Pos (0UL) /*!< M3BSEL (Bit 0) */ + #define R_POE3_M3SELR_M3BSEL_Msk (0xfUL) /*!< M3BSEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M3SELR_M3DSEL_Pos (4UL) /*!< M3DSEL (Bit 4) */ + #define R_POE3_M3SELR_M3DSEL_Msk (0xf0UL) /*!< M3DSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M4SELR1 ======================================================== */ + #define R_POE3_M4SELR1_M4ASEL_Pos (0UL) /*!< M4ASEL (Bit 0) */ + #define R_POE3_M4SELR1_M4ASEL_Msk (0xfUL) /*!< M4ASEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M4SELR1_M4CSEL_Pos (4UL) /*!< M4CSEL (Bit 4) */ + #define R_POE3_M4SELR1_M4CSEL_Msk (0xf0UL) /*!< M4CSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M4SELR2 ======================================================== */ + #define R_POE3_M4SELR2_M4BSEL_Pos (0UL) /*!< M4BSEL (Bit 0) */ + #define R_POE3_M4SELR2_M4BSEL_Msk (0xfUL) /*!< M4BSEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M4SELR2_M4DSEL_Pos (4UL) /*!< M4DSEL (Bit 4) */ + #define R_POE3_M4SELR2_M4DSEL_Msk (0xf0UL) /*!< M4DSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M6SELR ========================================================= */ + #define R_POE3_M6SELR_M6BSEL_Pos (0UL) /*!< M6BSEL (Bit 0) */ + #define R_POE3_M6SELR_M6BSEL_Msk (0xfUL) /*!< M6BSEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M6SELR_M6DSEL_Pos (4UL) /*!< M6DSEL (Bit 4) */ + #define R_POE3_M6SELR_M6DSEL_Msk (0xf0UL) /*!< M6DSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M7SELR1 ======================================================== */ + #define R_POE3_M7SELR1_M7ASEL_Pos (0UL) /*!< M7ASEL (Bit 0) */ + #define R_POE3_M7SELR1_M7ASEL_Msk (0xfUL) /*!< M7ASEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M7SELR1_M7CSEL_Pos (4UL) /*!< M7CSEL (Bit 4) */ + #define R_POE3_M7SELR1_M7CSEL_Msk (0xf0UL) /*!< M7CSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M7SELR2 ======================================================== */ + #define R_POE3_M7SELR2_M7BSEL_Pos (0UL) /*!< M7BSEL (Bit 0) */ + #define R_POE3_M7SELR2_M7BSEL_Msk (0xfUL) /*!< M7BSEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M7SELR2_M7DSEL_Pos (4UL) /*!< M7DSEL (Bit 4) */ + #define R_POE3_M7SELR2_M7DSEL_Msk (0xf0UL) /*!< M7DSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== POEG0GA ======================================================== */ + #define R_POEG0_POEG0GA_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG0_POEG0GA_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG0_POEG0GA_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG0_POEG0GA_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG0_POEG0GA_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG0_POEG0GA_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG0_POEG0GA_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG0_POEG0GA_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG0_POEG0GA_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_DERR0ST_Pos (24UL) /*!< DERR0ST (Bit 24) */ + #define R_POEG0_POEG0GA_DERR0ST_Msk (0x1000000UL) /*!< DERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_DERR1ST_Pos (25UL) /*!< DERR1ST (Bit 25) */ + #define R_POEG0_POEG0GA_DERR1ST_Msk (0x2000000UL) /*!< DERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_DERR0E_Pos (26UL) /*!< DERR0E (Bit 26) */ + #define R_POEG0_POEG0GA_DERR0E_Msk (0x4000000UL) /*!< DERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_DERR1E_Pos (27UL) /*!< DERR1E (Bit 27) */ + #define R_POEG0_POEG0GA_DERR1E_Msk (0x8000000UL) /*!< DERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG0_POEG0GA_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG0_POEG0GA_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG0_POEG0GA_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG0GB ======================================================== */ + #define R_POEG0_POEG0GB_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG0_POEG0GB_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG0_POEG0GB_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG0_POEG0GB_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG0_POEG0GB_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG0_POEG0GB_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG0_POEG0GB_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG0_POEG0GB_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG0_POEG0GB_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_DERR0ST_Pos (24UL) /*!< DERR0ST (Bit 24) */ + #define R_POEG0_POEG0GB_DERR0ST_Msk (0x1000000UL) /*!< DERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_DERR1ST_Pos (25UL) /*!< DERR1ST (Bit 25) */ + #define R_POEG0_POEG0GB_DERR1ST_Msk (0x2000000UL) /*!< DERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_DERR0E_Pos (26UL) /*!< DERR0E (Bit 26) */ + #define R_POEG0_POEG0GB_DERR0E_Msk (0x4000000UL) /*!< DERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_DERR1E_Pos (27UL) /*!< DERR1E (Bit 27) */ + #define R_POEG0_POEG0GB_DERR1E_Msk (0x8000000UL) /*!< DERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG0_POEG0GB_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG0_POEG0GB_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG0_POEG0GB_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG0GC ======================================================== */ + #define R_POEG0_POEG0GC_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG0_POEG0GC_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG0_POEG0GC_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG0_POEG0GC_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG0_POEG0GC_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG0_POEG0GC_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG0_POEG0GC_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG0_POEG0GC_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG0_POEG0GC_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_DERR0ST_Pos (24UL) /*!< DERR0ST (Bit 24) */ + #define R_POEG0_POEG0GC_DERR0ST_Msk (0x1000000UL) /*!< DERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_DERR1ST_Pos (25UL) /*!< DERR1ST (Bit 25) */ + #define R_POEG0_POEG0GC_DERR1ST_Msk (0x2000000UL) /*!< DERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_DERR0E_Pos (26UL) /*!< DERR0E (Bit 26) */ + #define R_POEG0_POEG0GC_DERR0E_Msk (0x4000000UL) /*!< DERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_DERR1E_Pos (27UL) /*!< DERR1E (Bit 27) */ + #define R_POEG0_POEG0GC_DERR1E_Msk (0x8000000UL) /*!< DERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG0_POEG0GC_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG0_POEG0GC_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG0_POEG0GC_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG0GD ======================================================== */ + #define R_POEG0_POEG0GD_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG0_POEG0GD_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG0_POEG0GD_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG0_POEG0GD_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG0_POEG0GD_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG0_POEG0GD_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG0_POEG0GD_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG0_POEG0GD_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG0_POEG0GD_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_DERR0ST_Pos (24UL) /*!< DERR0ST (Bit 24) */ + #define R_POEG0_POEG0GD_DERR0ST_Msk (0x1000000UL) /*!< DERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_DERR1ST_Pos (25UL) /*!< DERR1ST (Bit 25) */ + #define R_POEG0_POEG0GD_DERR1ST_Msk (0x2000000UL) /*!< DERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_DERR0E_Pos (26UL) /*!< DERR0E (Bit 26) */ + #define R_POEG0_POEG0GD_DERR0E_Msk (0x4000000UL) /*!< DERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_DERR1E_Pos (27UL) /*!< DERR1E (Bit 27) */ + #define R_POEG0_POEG0GD_DERR1E_Msk (0x8000000UL) /*!< DERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG0_POEG0GD_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG0_POEG0GD_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG0_POEG0GD_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_DSMIF0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DSSEICR ======================================================== */ + #define R_DSMIF0_DSSEICR_ISEL_Pos (0UL) /*!< ISEL (Bit 0) */ + #define R_DSMIF0_DSSEICR_ISEL_Msk (0x1UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSSEICR_ISEH_Pos (1UL) /*!< ISEH (Bit 1) */ + #define R_DSMIF0_DSSEICR_ISEH_Msk (0x2UL) /*!< ISEH (Bitfield-Mask: 0x01) */ +/* ======================================================== DSSECSR ======================================================== */ + #define R_DSMIF0_DSSECSR_SEDM_Pos (0UL) /*!< SEDM (Bit 0) */ + #define R_DSMIF0_DSSECSR_SEDM_Msk (0x7UL) /*!< SEDM (Bitfield-Mask: 0x07) */ +/* ======================================================== DSSELTR ======================================================== */ + #define R_DSMIF0_DSSELTR_SCMPTBL_Pos (0UL) /*!< SCMPTBL (Bit 0) */ + #define R_DSMIF0_DSSELTR_SCMPTBL_Msk (0x3ffffUL) /*!< SCMPTBL (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== DSSEHTR ======================================================== */ + #define R_DSMIF0_DSSEHTR_SCMPTBH_Pos (0UL) /*!< SCMPTBH (Bit 0) */ + #define R_DSMIF0_DSSEHTR_SCMPTBH_Msk (0x3ffffUL) /*!< SCMPTBH (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== DSSECR ========================================================= */ + #define R_DSMIF0_DSSECR_SEEL_Pos (0UL) /*!< SEEL (Bit 0) */ + #define R_DSMIF0_DSSECR_SEEL_Msk (0x1UL) /*!< SEEL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSSECR_SEEH_Pos (1UL) /*!< SEEH (Bit 1) */ + #define R_DSMIF0_DSSECR_SEEH_Msk (0x2UL) /*!< SEEH (Bitfield-Mask: 0x01) */ +/* ======================================================== DSSECDR ======================================================== */ + #define R_DSMIF0_DSSECDR_SECDR_Pos (0UL) /*!< SECDR (Bit 0) */ + #define R_DSMIF0_DSSECDR_SECDR_Msk (0xffffUL) /*!< SECDR (Bitfield-Mask: 0xffff) */ +/* ======================================================= DSCSTRTR ======================================================== */ + #define R_DSMIF0_DSCSTRTR_STRTRG0_Pos (0UL) /*!< STRTRG0 (Bit 0) */ + #define R_DSMIF0_DSCSTRTR_STRTRG0_Msk (0x1UL) /*!< STRTRG0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSTRTR_STRTRG1_Pos (1UL) /*!< STRTRG1 (Bit 1) */ + #define R_DSMIF0_DSCSTRTR_STRTRG1_Msk (0x2UL) /*!< STRTRG1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSTRTR_STRTRG2_Pos (2UL) /*!< STRTRG2 (Bit 2) */ + #define R_DSMIF0_DSCSTRTR_STRTRG2_Msk (0x4UL) /*!< STRTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSCSTPTR ======================================================== */ + #define R_DSMIF0_DSCSTPTR_STPTRG0_Pos (0UL) /*!< STPTRG0 (Bit 0) */ + #define R_DSMIF0_DSCSTPTR_STPTRG0_Msk (0x1UL) /*!< STPTRG0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSTPTR_STPTRG1_Pos (1UL) /*!< STPTRG1 (Bit 1) */ + #define R_DSMIF0_DSCSTPTR_STPTRG1_Msk (0x2UL) /*!< STPTRG1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSTPTR_STPTRG2_Pos (2UL) /*!< STPTRG2 (Bit 2) */ + #define R_DSMIF0_DSCSTPTR_STPTRG2_Msk (0x4UL) /*!< STPTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCESR ========================================================= */ + #define R_DSMIF0_DSCESR_OCFL0_Pos (0UL) /*!< OCFL0 (Bit 0) */ + #define R_DSMIF0_DSCESR_OCFL0_Msk (0x1UL) /*!< OCFL0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_OCFL1_Pos (1UL) /*!< OCFL1 (Bit 1) */ + #define R_DSMIF0_DSCESR_OCFL1_Msk (0x2UL) /*!< OCFL1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_OCFL2_Pos (2UL) /*!< OCFL2 (Bit 2) */ + #define R_DSMIF0_DSCESR_OCFL2_Msk (0x4UL) /*!< OCFL2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_OCFH0_Pos (4UL) /*!< OCFH0 (Bit 4) */ + #define R_DSMIF0_DSCESR_OCFH0_Msk (0x10UL) /*!< OCFH0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_OCFH1_Pos (5UL) /*!< OCFH1 (Bit 5) */ + #define R_DSMIF0_DSCESR_OCFH1_Msk (0x20UL) /*!< OCFH1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_OCFH2_Pos (6UL) /*!< OCFH2 (Bit 6) */ + #define R_DSMIF0_DSCESR_OCFH2_Msk (0x40UL) /*!< OCFH2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_SCF0_Pos (8UL) /*!< SCF0 (Bit 8) */ + #define R_DSMIF0_DSCESR_SCF0_Msk (0x100UL) /*!< SCF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_SCF1_Pos (9UL) /*!< SCF1 (Bit 9) */ + #define R_DSMIF0_DSCESR_SCF1_Msk (0x200UL) /*!< SCF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_SCF2_Pos (10UL) /*!< SCF2 (Bit 10) */ + #define R_DSMIF0_DSCESR_SCF2_Msk (0x400UL) /*!< SCF2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_SUMERRL_Pos (16UL) /*!< SUMERRL (Bit 16) */ + #define R_DSMIF0_DSCESR_SUMERRL_Msk (0x10000UL) /*!< SUMERRL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_SUMERRH_Pos (17UL) /*!< SUMERRH (Bit 17) */ + #define R_DSMIF0_DSCESR_SUMERRH_Msk (0x20000UL) /*!< SUMERRH (Bitfield-Mask: 0x01) */ +/* ========================================================= DSCSR ========================================================= */ + #define R_DSMIF0_DSCSR_DUF0_Pos (0UL) /*!< DUF0 (Bit 0) */ + #define R_DSMIF0_DSCSR_DUF0_Msk (0x1UL) /*!< DUF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSR_DUF1_Pos (1UL) /*!< DUF1 (Bit 1) */ + #define R_DSMIF0_DSCSR_DUF1_Msk (0x2UL) /*!< DUF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSR_DUF2_Pos (2UL) /*!< DUF2 (Bit 2) */ + #define R_DSMIF0_DSCSR_DUF2_Msk (0x4UL) /*!< DUF2 (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCSSR ========================================================= */ + #define R_DSMIF0_DSCSSR_CHSTATE0_Pos (0UL) /*!< CHSTATE0 (Bit 0) */ + #define R_DSMIF0_DSCSSR_CHSTATE0_Msk (0x1UL) /*!< CHSTATE0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSSR_CHSTATE1_Pos (4UL) /*!< CHSTATE1 (Bit 4) */ + #define R_DSMIF0_DSCSSR_CHSTATE1_Msk (0x10UL) /*!< CHSTATE1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSSR_CHSTATE2_Pos (8UL) /*!< CHSTATE2 (Bit 8) */ + #define R_DSMIF0_DSCSSR_CHSTATE2_Msk (0x100UL) /*!< CHSTATE2 (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCESCR ======================================================== */ + #define R_DSMIF0_DSCESCR_CLROCFL0_Pos (0UL) /*!< CLROCFL0 (Bit 0) */ + #define R_DSMIF0_DSCESCR_CLROCFL0_Msk (0x1UL) /*!< CLROCFL0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLROCFL1_Pos (1UL) /*!< CLROCFL1 (Bit 1) */ + #define R_DSMIF0_DSCESCR_CLROCFL1_Msk (0x2UL) /*!< CLROCFL1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLROCFL2_Pos (2UL) /*!< CLROCFL2 (Bit 2) */ + #define R_DSMIF0_DSCESCR_CLROCFL2_Msk (0x4UL) /*!< CLROCFL2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLROCFH0_Pos (4UL) /*!< CLROCFH0 (Bit 4) */ + #define R_DSMIF0_DSCESCR_CLROCFH0_Msk (0x10UL) /*!< CLROCFH0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLROCFH1_Pos (5UL) /*!< CLROCFH1 (Bit 5) */ + #define R_DSMIF0_DSCESCR_CLROCFH1_Msk (0x20UL) /*!< CLROCFH1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLROCFH2_Pos (6UL) /*!< CLROCFH2 (Bit 6) */ + #define R_DSMIF0_DSCESCR_CLROCFH2_Msk (0x40UL) /*!< CLROCFH2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLRSCF0_Pos (8UL) /*!< CLRSCF0 (Bit 8) */ + #define R_DSMIF0_DSCESCR_CLRSCF0_Msk (0x100UL) /*!< CLRSCF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLRSCF1_Pos (9UL) /*!< CLRSCF1 (Bit 9) */ + #define R_DSMIF0_DSCESCR_CLRSCF1_Msk (0x200UL) /*!< CLRSCF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLRSCF2_Pos (10UL) /*!< CLRSCF2 (Bit 10) */ + #define R_DSMIF0_DSCESCR_CLRSCF2_Msk (0x400UL) /*!< CLRSCF2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLRSUMERRL_Pos (16UL) /*!< CLRSUMERRL (Bit 16) */ + #define R_DSMIF0_DSCESCR_CLRSUMERRL_Msk (0x10000UL) /*!< CLRSUMERRL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLRSUMERRH_Pos (17UL) /*!< CLRSUMERRH (Bit 17) */ + #define R_DSMIF0_DSCESCR_CLRSUMERRH_Msk (0x20000UL) /*!< CLRSUMERRH (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCSCR ========================================================= */ + #define R_DSMIF0_DSCSCR_CLRDUF0_Pos (0UL) /*!< CLRDUF0 (Bit 0) */ + #define R_DSMIF0_DSCSCR_CLRDUF0_Msk (0x1UL) /*!< CLRDUF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSCR_CLRDUF1_Pos (1UL) /*!< CLRDUF1 (Bit 1) */ + #define R_DSMIF0_DSCSCR_CLRDUF1_Msk (0x2UL) /*!< CLRDUF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSCR_CLRDUF2_Pos (2UL) /*!< CLRDUF2 (Bit 2) */ + #define R_DSMIF0_DSCSCR_CLRDUF2_Msk (0x4UL) /*!< CLRDUF2 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GSC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CNTCR ========================================================= */ + #define R_GSC_CNTCR_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GSC_CNTCR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GSC_CNTCR_HDBG_Pos (1UL) /*!< HDBG (Bit 1) */ + #define R_GSC_CNTCR_HDBG_Msk (0x2UL) /*!< HDBG (Bitfield-Mask: 0x01) */ +/* ========================================================= CNTSR ========================================================= */ + #define R_GSC_CNTSR_DBGH_Pos (1UL) /*!< DBGH (Bit 1) */ + #define R_GSC_CNTSR_DBGH_Msk (0x2UL) /*!< DBGH (Bitfield-Mask: 0x01) */ +/* ======================================================== CNTCVL ========================================================= */ + #define R_GSC_CNTCVL_CNTCVL_L_32_Pos (0UL) /*!< CNTCVL_L_32 (Bit 0) */ + #define R_GSC_CNTCVL_CNTCVL_L_32_Msk (0xffffffffUL) /*!< CNTCVL_L_32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CNTCVU ========================================================= */ + #define R_GSC_CNTCVU_CNTCVU_U_32_Pos (0UL) /*!< CNTCVU_U_32 (Bit 0) */ + #define R_GSC_CNTCVU_CNTCVU_U_32_Msk (0xffffffffUL) /*!< CNTCVU_U_32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CNTFID0 ======================================================== */ + #define R_GSC_CNTFID0_FREQ_Pos (0UL) /*!< FREQ (Bit 0) */ + #define R_GSC_CNTFID0_FREQ_Msk (0xffffffffUL) /*!< FREQ (Bitfield-Mask: 0xffffffff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R9A07G075_H */ + +/** @} */ /* End of group R9A07G075 */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h new file mode 100644 index 00000000000..0acf27501a7 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h @@ -0,0 +1,133 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/* Ensure Renesas MCU variation definitions are included to ensure MCU + * specific register variations are handled correctly. */ +#ifndef BSP_FEATURE_H + #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h." +#endif + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup RZT2 + * @{ + */ + +#ifndef RZT2_H + #define RZT2_H + + #ifdef __cplusplus +extern "C" { + #endif + +/* Define compiler macros for CPU architecture, used in CMSIS 5. */ + #if defined(__ICCARM__) + #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ + +/* Macros already defined */ + #else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ + #endif + +/* Alternative core deduction for older ICCARM's */ + #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8R__) && (__CORE__ == __ARM8R__) + #define __ARM_ARCH_8R__ 1 + #else + #error "Unknown target." + #endif + #endif + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +/* IRQn_Type is generated as part of an FSP project. It can be found in vector_data.h. */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + + #if __ARM_ARCH_7EM__ + #define RENESAS_CORTEX_M4 + #elif __ARM_ARCH_6M__ + #define RENESAS_CORTEX_M0PLUS + #elif __ARM_ARCH_8M_BASE__ + #define RENESAS_CORTEX_M23 + #elif __ARM_ARCH_8M_MAIN__ + #define RENESAS_CORTEX_M33 + #elif __ARM_ARCH_8R__ + #define RENESAS_CORTEX_R52 + #else + #warning Unsupported Architecture + #endif + + #if BSP_MCU_GROUP_RZT2M + #include "R9A07G075.h" + #elif BSP_MCU_GROUP_RZT2L + #include "R9A07G074.h" + #else + #warning Unsupported MCU + #endif + + #ifdef __cplusplus +} + #endif + +#endif /* RZT2_H */ + +/** @} */ /* End of group RZT2 */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h new file mode 100644 index 00000000000..2fafe6c0f68 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef SYSTEM_RENESAS_ARM_H + #define SYSTEM_RENESAS_ARM_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include + +extern uint32_t SystemCoreClock; /** System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c new file mode 100644 index 00000000000..ab8fdf6c29d --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c @@ -0,0 +1,377 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_HACTLR_BIT_L (0xB783) /* HACTLR EL1 access enable(0b1011 0111 1000 0011) */ +#define BSP_HCR_HCD_DISABLE (0x20000000) /* HCR.HCD = 1 : HVC disable */ +#define BSP_MODE_MASK (0x1F) /* Bit mask for mode bits in CPSR */ +#define BSP_SVC_MODE (0x13) /* Supervisor mode */ + +#if defined(__ICCARM__) + #define BSP_IRQ_STACK_END_ADDRESS __section_end(".irq_stack") + #define BSP_FIQ_STACK_END_ADDRESS __section_end(".fiq_stack") + #define BSP_SVC_STACK_END_ADDRESS __section_end(".svc_stack") + #define BSP_ABORT_STACK_END_ADDRESS __section_end(".abt_stack") + #define BSP_UNDEFINED_STACK_END_ADDRESS __section_end(".und_stack") + #define BSP_SYSTEM_STACK_END_ADDRESS __section_end(".sys_stack") + +#elif defined(__GNUC__) + #define BSP_IRQ_STACK_END_ADDRESS &__IrqStackLimit + #define BSP_FIQ_STACK_END_ADDRESS &__FiqStackLimit + #define BSP_SVC_STACK_END_ADDRESS &__SvcStackLimit + #define BSP_ABORT_STACK_END_ADDRESS &__AbtStackLimit + #define BSP_UNDEFINED_STACK_END_ADDRESS &__UndStackLimit + #define BSP_SYSTEM_STACK_END_ADDRESS &__SysStackLimit + +#endif + +#if (0 == BSP_CFG_CORE_CR52) + #define BSP_IMP_BTCMREGIONR_MASK_L (0x1FFC) /* Masked out BASEADDRESS and ENABLEELx bits(L) */ + #define BSP_IMP_BTCMREGIONR_ENABLEEL_L (0x0003) /* Set base address and enable EL2, EL1, EL0 access(L) */ + #define BSP_IMP_BTCMREGIONR_ENABLEEL_H (0x0010) /* Set base address and enable EL2, EL1, EL0 access(H) */ + +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +#if defined(__ICCARM__) + #pragma section=".irq_stack" + #pragma section=".fiq_stack" + #pragma section=".svc_stack" + #pragma section=".abt_stack" + #pragma section=".und_stack" + #pragma section=".sys_stack" + +#elif defined(__GNUC__) +extern void * __IrqStackLimit; +extern void * __FiqStackLimit; +extern void * __SvcStackLimit; +extern void * __AbtStackLimit; +extern void * __UndStackLimit; +extern void * __SysStackLimit; + +#endif + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#if __FPU_USED +extern void bsp_fpu_advancedsimd_init(void); + +#endif + +#if (0 == BSP_CFG_CORE_CR52) +extern void bsp_slavetcm_enable(void); + +#endif + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +int32_t main(void); + +BSP_TARGET_ARM void system_init(void) BSP_PLACE_IN_SECTION(".loader_text"); +BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void stack_init(void); +BSP_TARGET_ARM void fpu_slavetcm_init(void); + +BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void __Vectors(void) BSP_PLACE_IN_SECTION(".intvec"); +__WEAK BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void IRQ_Handler(void); +__WEAK BSP_TARGET_ARM void Reset_Handler(void) BSP_PLACE_IN_SECTION(".reset_handler"); + +void Default_Handler(void); + +/* Stacks */ +BSP_DONT_REMOVE static uint8_t g_fiq_stack[BSP_CFG_STACK_FIQ_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) +BSP_PLACE_IN_SECTION(BSP_SECTION_FIQ_STACK); +BSP_DONT_REMOVE static uint8_t g_irq_stack[BSP_CFG_STACK_IRQ_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) +BSP_PLACE_IN_SECTION(BSP_SECTION_IRQ_STACK); +BSP_DONT_REMOVE static uint8_t g_abt_stack[BSP_CFG_STACK_ABT_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) +BSP_PLACE_IN_SECTION(BSP_SECTION_ABT_STACK); +BSP_DONT_REMOVE static uint8_t g_und_stack[BSP_CFG_STACK_UND_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) +BSP_PLACE_IN_SECTION(BSP_SECTION_UND_STACK); +BSP_DONT_REMOVE static uint8_t g_sys_stack[BSP_CFG_STACK_SYS_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) +BSP_PLACE_IN_SECTION(BSP_SECTION_SYS_STACK); +BSP_DONT_REMOVE static uint8_t g_svc_stack[BSP_CFG_STACK_SVC_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) +BSP_PLACE_IN_SECTION(BSP_SECTION_SVC_STACK); + +/* Heap */ +#if (BSP_CFG_HEAP_BYTES > 0) + +BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ + BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); +#endif + +#if defined(__GNUC__) +BSP_DONT_REMOVE static const void * g_bsp_dummy BSP_PLACE_IN_SECTION(".dummy"); + + #if BSP_CFG_RAM_EXECUTION +BSP_DONT_REMOVE static const void * g_bsp_loader_dummy BSP_PLACE_IN_SECTION(".loader_dummy"); + + #endif +#endif + +BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void __Vectors (void) +{ + __asm volatile (" ldr pc,=Reset_Handler \n" + " ldr pc,=Undefined_Handler \n" + " ldr pc,=SVC_Handler \n" + " ldr pc,=Prefetch_Handler \n" + " ldr pc,=Abort_Handler \n" + " ldr pc,=Reserved_Handler \n" + " ldr pc,=IRQ_Handler \n" + " ldr pc,=FIQ_Handler \n" + ::: "memory"); +} + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Default exception handler. + **********************************************************************************************************************/ +void Default_Handler (void) +{ + /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption + * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status + * registers for more information. + */ + BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0); +} + +/*******************************************************************************************************************//** + * After boot processing, LSI starts executing here. + **********************************************************************************************************************/ +BSP_TARGET_ARM void system_init (void) +{ + __asm volatile ( + "set_hactlr: \n" + " MOVW r0, %[bsp_hactlr_bit_l] \n" /* Set HACTLR bits(L) */ + " MOVT r0, #0 \n" + " MCR p15, #4, r0, c1, c0, #1 \n" /* Write r0 to HACTLR */ + ::[bsp_hactlr_bit_l] "i" (BSP_HACTLR_BIT_L) : "memory"); + + __asm volatile ( + "set_hcr: \n" + " MRC p15, #4, r1, c1, c1, #0 \n" /* Read Hyp Configuration Register */ + " ORR r1, r1, %[bsp_hcr_hcd_disable] \n" /* HVC instruction disable */ + " MCR p15, #4, r1, c1, c1, #0 \n" /* Write Hyp Configuration Register */ + ::[bsp_hcr_hcd_disable] "i" (BSP_HCR_HCD_DISABLE) : "memory"); + + __asm volatile ( + "set_vbar: \n" + " LDR r0, =__Vectors \n" + " MCR p15, #0, r0, c12, c0, #0 \n" /* Write r0 to VBAR */ + ::: "memory"); + +#if (0 == BSP_CFG_CORE_CR52) + __asm volatile ( + "LLPP_access_enable: \n" + + /* Enable PERIPHPREGIONR (LLPP) */ + " MRC p15, #0, r1, c15, c0,#0 \n" /* PERIPHPREGIONR */ + " ORR r1, r1, #(0x1 << 1) \n" /* Enable PERIPHPREGIONR EL2 */ + " ORR r1, r1, #(0x1) \n" /* Enable PERIPHPREGIONR EL1 and EL0 */ + " DSB \n" /* Ensuring memory access complete */ + " MCR p15, #0, r1, c15, c0,#0 \n" /* PERIPHREGIONR */ + " ISB \n" /* Ensuring Context-changing */ + ::: "memory"); +#endif + + __asm volatile ( + "cpsr_save: \n" + " MRS r0, CPSR \n" /* Original PSR value */ + " BIC r0, r0, %[bsp_mode_mask] \n" /* Clear the mode bits */ + " ORR r0, r0, %[bsp_svc_mode] \n" /* Set SVC mode bits */ + " MSR SPSR_hyp, r0 \n" + ::[bsp_mode_mask] "i" (BSP_MODE_MASK), [bsp_svc_mode] "i" (BSP_SVC_MODE) : "memory"); + + __asm volatile ( + "exception_return: \n" + " LDR r1, =stack_init \n" + " MSR ELR_hyp, r1 \n" + " ERET \n" /* Branch to stack_init and enter EL1 */ + ::: "memory"); +} + +/** @} (end addtogroup BSP_MCU) */ + +#if defined(__ICCARM__) + #define BSP_SYSTEMINIT_B_INSTRUCTION SystemInit(); + + #define WEAK_REF_ATTRIBUTE + + #pragma weak Undefined_Handler = Default_Handler + #pragma weak SVC_Handler = Default_Handler + #pragma weak Prefetch_Handler = Default_Handler + #pragma weak Abort_Handler = Default_Handler + #pragma weak Reserved_Handler = Default_Handler + #pragma weak FIQ_Handler = Default_Handler +#elif defined(__GNUC__) + + #define BSP_SYSTEMINIT_B_INSTRUCTION __asm volatile ("B SystemInit"); + + #define WEAK_REF_ATTRIBUTE __attribute__((weak, alias("Default_Handler"))) +#endif + +void Undefined_Handler(void) WEAK_REF_ATTRIBUTE; +void SVC_Handler(void) WEAK_REF_ATTRIBUTE; +void Prefetch_Handler(void) WEAK_REF_ATTRIBUTE; +void Abort_Handler(void) WEAK_REF_ATTRIBUTE; +void Reserved_Handler(void) WEAK_REF_ATTRIBUTE; +void FIQ_Handler(void) WEAK_REF_ATTRIBUTE; + +/*******************************************************************************************************************//** + * After system_init, EL1 settings start here. + **********************************************************************************************************************/ +BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void stack_init (void) +{ + __asm volatile ( + "stack_initialization: \n" + + /* Stack setting for EL1 */ + " CPS #17 \n" /* FIQ mode */ + " MOV sp, %[bsp_fiq_stack_end_address] \n" + " CPS #18 \n" /* IRQ mode */ + " MOV sp, %[bsp_irq_stack_end_address] \n" + " CPS #23 \n" /* Abort mode */ + " MOV sp, %[bsp_abort_stack_end_address] \n" + " CPS #27 \n" /* Undefined mode */ + " MOV sp, %[bsp_undefined_stack_end_address] \n" + " CPS #31 \n" /* System mode */ + " MOV sp, %[bsp_system_stack_end_address] \n" + " CPS #19 \n" /* SVC mode */ + " MOV sp, %[bsp_svc_stack_end_address] \n" + + " B fpu_slavetcm_init \n" /* Branch to fpu_slavetcm_init */ + ::[bsp_fiq_stack_end_address] "r" (BSP_FIQ_STACK_END_ADDRESS), + [bsp_irq_stack_end_address] "r" (BSP_IRQ_STACK_END_ADDRESS), + [bsp_abort_stack_end_address] "r" (BSP_ABORT_STACK_END_ADDRESS), + [bsp_undefined_stack_end_address] "r" (BSP_UNDEFINED_STACK_END_ADDRESS), + [bsp_system_stack_end_address] "r" (BSP_SYSTEM_STACK_END_ADDRESS), + [bsp_svc_stack_end_address] "r" (BSP_SVC_STACK_END_ADDRESS) : "memory"); +} + +/*******************************************************************************************************************//** + * Enable FPU and enable privileged/unprivileged access for TCM. + **********************************************************************************************************************/ +BSP_TARGET_ARM void fpu_slavetcm_init (void) +{ +#if __FPU_USED + + /* Initialize FPU and Advanced SIMD setting */ + bsp_fpu_advancedsimd_init(); +#endif + +#if (0 == BSP_CFG_CORE_CR52) + + /* Enable SLAVEPCTLR TCM access lvl slaves */ + bsp_slavetcm_enable(); +#endif + + BSP_SYSTEMINIT_B_INSTRUCTION +} + +__WEAK BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void IRQ_Handler (void) +{ + __asm volatile ( + "SUB lr, lr, #4 \n" + "SRSDB sp!, #31 \n" /* Store LR_irq and SPSR_irq in system mode stack. */ + "CPS #31 \n" /* Switch to system mode. */ + "PUSH {r0-r3, r12} \n" /* Store other AAPCS registers. */ + +#if __FPU_USED + "VMRS r0, FPSCR \n" + "STMDB sp!, {r0} \n" /* Store FPSCR register. */ + "SUB sp, sp, #4 \n" + "VPUSH {d0-d15} \n" /* Store FPU registers. */ + "VPUSH {d16-d31} \n" /* Store FPU registers. */ +#endif + + "MRC p15, #0, r3, c12, c12, #2 \n" /* Read HPPIR1 to r3. */ + "MRC p15, #0, r0, c12, c12, #0 \n" /* Read IAR1 to r0. */ + + "PUSH {r0} \n" /* Store the INTID. */ + "MOV r1, sp \n" /* Make alignment for stack. */ + "AND r1, r1, #4 \n" + "SUB sp, sp, r1 \n" + "PUSH {r1, lr} \n" + + "LDR r1,=bsp_common_interrupt_handler \n" + "BLX r1 \n" /* Jump to bsp_common_interrupt_handler, First argument (r0) = ICC_IAR1 read value. */ + + "POP {r1, lr} \n" + "ADD sp, sp, r1 \n" + "POP {r0} \n" /* Restore the INTID to r0. */ + + "MCR p15, #0, r0, c12, c12, #1 \n" /* Write INTID to EOIR. */ + +#if __FPU_USED + "VPOP {d16-d31} \n" /* Restore FPU registers. */ + "VPOP {d0-d15} \n" /* Restore FPU registers. */ + "ADD sp, sp, #4 \n" + "POP {r0} \n" + "VMSR FPSCR, r0 \n" /* Restore FPSCR register. */ +#endif + + "POP {r0-r3, r12} \n" /* Restore registers. */ + "RFEIA sp! \n" /* Return from system mode tack using RFE. */ + ::: "memory"); +} + +__WEAK BSP_TARGET_ARM void Reset_Handler (void) +{ +#if (0 == BSP_CFG_CORE_CR52) + + /* Enable access to BTCM */ + __asm volatile ( + "set_IMP_BTCMREGIONR: \n" + " MRC p15, #0, r0, c9, c1, #1 \n" /* Read IMP_BTCMREGIONR to r0 */ + " MOVW r1, %[bsp_imp_btcmregionr_mask_l] \n" + " MOVT r1, #0 \n" + " AND r0, r0, r1 \n" /* Masked out BASEADDRESS and ENABLEELx bits */ + " MOVW r1, %[bsp_imp_btcmregionr_enableel_l] \n" + " MOVT r1, %[bsp_imp_btcmregionr_enableel_h] \n" + " ORR r0, r0, r1 \n" /* Set base address and enable EL2, EL1, EL0 access */ + " DSB \n" /* Ensuring memory access complete */ + + " MCR p15, #0, r0, c9, c1, #1 \n" /* Write r0 to IMP_BTCMREGIONR */ + " ISB \n" /* Ensuring Context-changing */ + ::[bsp_imp_btcmregionr_mask_l] "i" (BSP_IMP_BTCMREGIONR_MASK_L), + [bsp_imp_btcmregionr_enableel_l] "i" (BSP_IMP_BTCMREGIONR_ENABLEEL_L), + [bsp_imp_btcmregionr_enableel_h] "i" (BSP_IMP_BTCMREGIONR_ENABLEEL_H) : "memory"); +#endif + + /* Branch to system_init */ + __asm volatile ("B system_init"); +} diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c new file mode 100644 index 00000000000..faa04d0d2bd --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c @@ -0,0 +1,625 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include +#include "bsp_api.h" + +#include "../../../../../mcu/all/bsp_clocks.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_CPCAR_CP_ENABLE (0x00F00000) +#define BSP_FPEXC_EN_ENABLE (0x40000000) +#define BSP_TCM_ALL_ACCESS_ENABLE (0x00000003) + +#define BSP_PRIORITY_MASK BSP_FEATURE_BSP_IRQ_PRIORITY_MASK /* Priority mask value for GIC */ +#define BSP_ENABLE_GROUP_INT (0x00000001) /* Enable Group1 interrupt value */ +#define BSP_ICC_CTLR (0x00000001) /* ICC_BPR0 is used for Group1 interrupt */ + +#define BSP_BG_REGION_ENABLE (0x00020000) /* Enable EL1 background region */ +#define BSP_BG_REGION_DISABLE (0x00000000) /* Disable EL1 background region */ +#define BSP_SCTLR_BR_BIT (BSP_CFG_SCTLR_BR_BIT) /* Enable EL1 background region */ + +#define BSP_ICACHE_ENABLE (0x00001000) +#define BSP_ICACHE_DISABLE (0x00000000) + +#define BSP_DATACACHE_ENABLE (0x00000004) +#define BSP_DATACACHE_DISABLE (0x00000000) + +#define BSP_WRITE_THROUGH_TRANSIENT (0x0003) /* Normal-Memory: Write-Through transient */ +#define BSP_NON_CACHEABLE (0x0004) /* Normal-Memory: Non-Cacheable */ +#define BSP_WRITE_BACK_TRANSIENT (0x0007) /* Normal-Memory: Write-Back transient */ +#define BSP_WRITE_NON_THROUGH (0x000B) /* Normal-Memory: Write-Through non-transient. */ +#define BSP_WRITE_BACK_NON_TRANSIENT (0x000F) /* Normal-Memory: Write-Back non-transient. */ + +#define BSP_TYPE_NORMAL_MEMORY (0) +#define BSP_TYPE_DEVICE_MEMORY (1) + +#define BSP_READ_ALLOCATE (0xFFFF) /* Read allocate (bit1=1, "1" mask except bit1) */ +#define BSP_READ_NOT_ALLOCATE (0xFFFD) /* Read not allocate (bit1=0, "1" mask except bit1) */ +#define BSP_WRITE_ALLOCATE (0xFFFF) /* Write allocate (bit0=1, "1" mask except bit0) */ +#define BSP_WRITE_NOT_ALLOCATE (0xFFFE) /* Write not allocate (bit0=0, "1" mask except bit0) */ + +#define BSP_DEVICE_NGNRNE (0x0000) /* Device-nGnRnE memory */ +#define BSP_DEVICE_NGNRE (0x0004) /* Device-nGnRE memory */ +#define BSP_DEVICE_NGRE (0x0008) /* Device-nGRE memory */ +#define BSP_DEVICE_GRE (0x000C) /* Device-GRE memory */ + +#define BSP_OFFSET_ATTR0_INNER (0) +#define BSP_OFFSET_ATTR0_OUTER (4) +#define BSP_OFFSET_ATTR0_DEVICE (0) +#define BSP_OFFSET_ATTR1_INNER (8) +#define BSP_OFFSET_ATTR1_OUTER (12) +#define BSP_OFFSET_ATTR1_DEVICE (8) + +#define BSP_OFFSET_ATTR2_INNER (16) +#define BSP_OFFSET_ATTR2_OUTER (20) +#define BSP_OFFSET_ATTR2_DEVICE (16) +#define BSP_OFFSET_ATTR3_INNER (24) +#define BSP_OFFSET_ATTR3_OUTER (28) +#define BSP_OFFSET_ATTR3_DEVICE (24) + +#define BSP_OFFSET_ATTR4_INNER (0) +#define BSP_OFFSET_ATTR4_OUTER (4) +#define BSP_OFFSET_ATTR4_DEVICE (0) +#define BSP_OFFSET_ATTR5_INNER (8) +#define BSP_OFFSET_ATTR5_OUTER (12) +#define BSP_OFFSET_ATTR5_DEVICE (8) + +#define BSP_OFFSET_ATTR6_INNER (16) +#define BSP_OFFSET_ATTR6_OUTER (20) +#define BSP_OFFSET_ATTR6_DEVICE (16) +#define BSP_OFFSET_ATTR7_INNER (24) +#define BSP_OFFSET_ATTR7_OUTER (28) +#define BSP_OFFSET_ATTR7_DEVICE (24) + +#define BSP_NON_SHAREABLE (0 << 3) +#define BSP_OUTER_SHAREABLE (2 << 3) +#define BSP_INNER_SHAREABLE (3 << 3) +#define BSP_EL1RW_EL0NO (0 << 1) +#define BSP_EL1RW_EL0RW (1 << 1) +#define BSP_EL1RO_EL0NO (2 << 1) +#define BSP_EL1RO_EL0RO (3 << 1) +#define BSP_EXECUTE_ENABLE (0) +#define BSP_EXECUTE_NEVER (1) +#define BSP_REGION_DISABLE (0) +#define BSP_REGION_ENABLE (1) +#define BSP_ATTRINDEX0 (0 << 1) +#define BSP_ATTRINDEX1 (1 << 1) +#define BSP_ATTRINDEX2 (2 << 1) +#define BSP_ATTRINDEX3 (3 << 1) +#define BSP_ATTRINDEX4 (4 << 1) +#define BSP_ATTRINDEX5 (5 << 1) +#define BSP_ATTRINDEX6 (6 << 1) +#define BSP_ATTRINDEX7 (7 << 1) + +/* Attr0 */ +#if BSP_CFG_CPU_MPU_ATTR0_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR0 (BSP_CFG_CPU_MPU_ATTR0_DEVICE_TYPE << BSP_OFFSET_ATTR0_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR0 (((BSP_CFG_CPU_MPU_ATTR0_INNER & \ + (BSP_CFG_CPU_MPU_ATTR0_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR0_INNER_WRITE)) << BSP_OFFSET_ATTR0_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR0_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR0_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR0_OUTER_WRITE)) << BSP_OFFSET_ATTR0_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR0_TYPE */ + +/* Attr1 */ +#if BSP_CFG_CPU_MPU_ATTR1_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR1 (BSP_CFG_CPU_MPU_ATTR1_DEVICE_TYPE << BSP_OFFSET_ATTR1_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR1 (((BSP_CFG_CPU_MPU_ATTR1_INNER & \ + (BSP_CFG_CPU_MPU_ATTR1_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR1_INNER_WRITE)) << BSP_OFFSET_ATTR1_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR1_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR1_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR1_OUTER_WRITE)) << BSP_OFFSET_ATTR1_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR1_TYPE */ + +/* Attr2 */ +#if BSP_CFG_CPU_MPU_ATTR2_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR2 (BSP_CFG_CPU_MPU_ATTR2_DEVICE_TYPE << BSP_OFFSET_ATTR2_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR2 (((BSP_CFG_CPU_MPU_ATTR2_INNER & \ + (BSP_CFG_CPU_MPU_ATTR2_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR2_INNER_WRITE)) << BSP_OFFSET_ATTR2_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR2_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR2_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR2_OUTER_WRITE)) << BSP_OFFSET_ATTR2_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR2_TYPE */ + +/* Attr3 */ +#if BSP_CFG_CPU_MPU_ATTR3_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR3 (BSP_CFG_CPU_MPU_ATTR3_DEVICE_TYPE << BSP_OFFSET_ATTR3_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR3 (((BSP_CFG_CPU_MPU_ATTR3_INNER & \ + (BSP_CFG_CPU_MPU_ATTR3_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR3_INNER_WRITE)) << BSP_OFFSET_ATTR3_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR3_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR3_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR3_OUTER_WRITE)) << BSP_OFFSET_ATTR3_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR3_TYPE */ + +/* Attr4 */ +#if BSP_CFG_CPU_MPU_ATTR4_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR4 (BSP_CFG_CPU_MPU_ATTR4_DEVICE_TYPE << BSP_OFFSET_ATTR4_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR4 (((BSP_CFG_CPU_MPU_ATTR4_INNER & \ + (BSP_CFG_CPU_MPU_ATTR4_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR4_INNER_WRITE)) << BSP_OFFSET_ATTR4_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR4_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR4_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR4_OUTER_WRITE)) << BSP_OFFSET_ATTR4_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR4_TYPE */ + +/* Attr5 */ +#if BSP_CFG_CPU_MPU_ATTR5_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR5 (BSP_CFG_CPU_MPU_ATTR5_DEVICE_TYPE << BSP_OFFSET_ATTR5_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR5 (((BSP_CFG_CPU_MPU_ATTR5_INNER & \ + (BSP_CFG_CPU_MPU_ATTR5_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR5_INNER_WRITE)) << BSP_OFFSET_ATTR5_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR5_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR5_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR5_OUTER_WRITE)) << BSP_OFFSET_ATTR5_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR5_TYPE */ + +/* Attr6 */ +#if BSP_CFG_CPU_MPU_ATTR6_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR6 (BSP_CFG_CPU_MPU_ATTR6_DEVICE_TYPE << BSP_OFFSET_ATTR6_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR6 (((BSP_CFG_CPU_MPU_ATTR6_INNER & \ + (BSP_CFG_CPU_MPU_ATTR6_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR6_INNER_WRITE)) << BSP_OFFSET_ATTR6_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR6_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR6_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR6_OUTER_WRITE)) << BSP_OFFSET_ATTR6_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR6_TYPE */ + +/* Attr7 */ +#if BSP_CFG_CPU_MPU_ATTR7_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR7 (BSP_CFG_CPU_MPU_ATTR7_DEVICE_TYPE << BSP_OFFSET_ATTR7_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR7 (((BSP_CFG_CPU_MPU_ATTR7_INNER & \ + (BSP_CFG_CPU_MPU_ATTR7_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR7_INNER_WRITE)) << BSP_OFFSET_ATTR7_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR7_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR7_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR7_OUTER_WRITE)) << BSP_OFFSET_ATTR7_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR7_TYPE */ + +#define ATTR_3_2_1_0 (BSP_CFG_CPU_MPU_ATTR3 | BSP_CFG_CPU_MPU_ATTR2 | BSP_CFG_CPU_MPU_ATTR1 | \ + BSP_CFG_CPU_MPU_ATTR0) +#define ATTR_7_6_5_4 (BSP_CFG_CPU_MPU_ATTR7 | BSP_CFG_CPU_MPU_ATTR6 | BSP_CFG_CPU_MPU_ATTR5 | \ + BSP_CFG_CPU_MPU_ATTR4) + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR0_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR0_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR0_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR1_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR1_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR1_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR2_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR2_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR2_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR3_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR3_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR3_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR4_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR4_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR4_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR5_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR5_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR5_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR6_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR6_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR6_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR7_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR7_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR7_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +/* Region template */ +#define EL1_MPU_REGION_COUNT (24) + +#define EL1_MPU_REGIONXX_BASE(n) ((BSP_CFG_EL1_MPU_REGION ## n ## _BASE & 0xFFFFFFC0) | \ + BSP_CFG_EL1_MPU_REGION ## n ## _SH | \ + BSP_CFG_EL1_MPU_REGION ## n ## _AP | \ + BSP_CFG_EL1_MPU_REGION ## n ## _XN) + +#define EL1_MPU_REGIONXX_LIMIT(n) ((BSP_CFG_EL1_MPU_REGION ## n ## _LIMIT & 0xFFFFFFC0) | \ + BSP_CFG_EL1_MPU_REGION ## n ## _ATTRINDEX | \ + BSP_CFG_EL1_MPU_REGION ## n ## _ENABLE) + +/* region 0 */ +#define EL1_MPU_REGION00_BASE EL1_MPU_REGIONXX_BASE(00) +#define EL1_MPU_REGION00_LIMIT EL1_MPU_REGIONXX_LIMIT(00) + +/* region 1 */ +#define EL1_MPU_REGION01_BASE EL1_MPU_REGIONXX_BASE(01) +#define EL1_MPU_REGION01_LIMIT EL1_MPU_REGIONXX_LIMIT(01) + +/* region 2 */ +#define EL1_MPU_REGION02_BASE EL1_MPU_REGIONXX_BASE(02) +#define EL1_MPU_REGION02_LIMIT EL1_MPU_REGIONXX_LIMIT(02) + +/* region 3 */ +#define EL1_MPU_REGION03_BASE EL1_MPU_REGIONXX_BASE(03) +#define EL1_MPU_REGION03_LIMIT EL1_MPU_REGIONXX_LIMIT(03) + +/* region 4 */ +#define EL1_MPU_REGION04_BASE EL1_MPU_REGIONXX_BASE(04) +#define EL1_MPU_REGION04_LIMIT EL1_MPU_REGIONXX_LIMIT(04) + +/* region 5 */ +#define EL1_MPU_REGION05_BASE EL1_MPU_REGIONXX_BASE(05) +#define EL1_MPU_REGION05_LIMIT EL1_MPU_REGIONXX_LIMIT(05) + +/* region 6 */ +#define EL1_MPU_REGION06_BASE EL1_MPU_REGIONXX_BASE(06) +#define EL1_MPU_REGION06_LIMIT EL1_MPU_REGIONXX_LIMIT(06) + +/* region 7 */ +#define EL1_MPU_REGION07_BASE EL1_MPU_REGIONXX_BASE(07) +#define EL1_MPU_REGION07_LIMIT EL1_MPU_REGIONXX_LIMIT(07) + +/* region 8 */ +#define EL1_MPU_REGION08_BASE EL1_MPU_REGIONXX_BASE(08) +#define EL1_MPU_REGION08_LIMIT EL1_MPU_REGIONXX_LIMIT(08) + +/* region 9 */ +#define EL1_MPU_REGION09_BASE EL1_MPU_REGIONXX_BASE(09) +#define EL1_MPU_REGION09_LIMIT EL1_MPU_REGIONXX_LIMIT(09) + +/* region 10 */ +#define EL1_MPU_REGION10_BASE EL1_MPU_REGIONXX_BASE(10) +#define EL1_MPU_REGION10_LIMIT EL1_MPU_REGIONXX_LIMIT(10) + +/* region 11 */ +#define EL1_MPU_REGION11_BASE EL1_MPU_REGIONXX_BASE(11) +#define EL1_MPU_REGION11_LIMIT EL1_MPU_REGIONXX_LIMIT(11) + +/* region 12 */ +#define EL1_MPU_REGION12_BASE EL1_MPU_REGIONXX_BASE(12) +#define EL1_MPU_REGION12_LIMIT EL1_MPU_REGIONXX_LIMIT(12) + +/* region 13 */ +#define EL1_MPU_REGION13_BASE EL1_MPU_REGIONXX_BASE(13) +#define EL1_MPU_REGION13_LIMIT EL1_MPU_REGIONXX_LIMIT(13) + +/* region 14 */ +#define EL1_MPU_REGION14_BASE EL1_MPU_REGIONXX_BASE(14) +#define EL1_MPU_REGION14_LIMIT EL1_MPU_REGIONXX_LIMIT(14) + +/* region 15 */ +#define EL1_MPU_REGION15_BASE EL1_MPU_REGIONXX_BASE(15) +#define EL1_MPU_REGION15_LIMIT EL1_MPU_REGIONXX_LIMIT(15) + +/* region 16 */ +#define EL1_MPU_REGION16_BASE EL1_MPU_REGIONXX_BASE(16) +#define EL1_MPU_REGION16_LIMIT EL1_MPU_REGIONXX_LIMIT(16) + +/* region 17 */ +#define EL1_MPU_REGION17_BASE EL1_MPU_REGIONXX_BASE(17) +#define EL1_MPU_REGION17_LIMIT EL1_MPU_REGIONXX_LIMIT(17) + +/* region 18 */ +#define EL1_MPU_REGION18_BASE EL1_MPU_REGIONXX_BASE(18) +#define EL1_MPU_REGION18_LIMIT EL1_MPU_REGIONXX_LIMIT(18) + +/* region 19 */ +#define EL1_MPU_REGION19_BASE EL1_MPU_REGIONXX_BASE(19) +#define EL1_MPU_REGION19_LIMIT EL1_MPU_REGIONXX_LIMIT(19) + +/* region 20 */ +#define EL1_MPU_REGION20_BASE EL1_MPU_REGIONXX_BASE(20) +#define EL1_MPU_REGION20_LIMIT EL1_MPU_REGIONXX_LIMIT(20) + +/* region 21 */ +#define EL1_MPU_REGION21_BASE EL1_MPU_REGIONXX_BASE(21) +#define EL1_MPU_REGION21_LIMIT EL1_MPU_REGIONXX_LIMIT(21) + +/* region 22 */ +#define EL1_MPU_REGION22_BASE EL1_MPU_REGIONXX_BASE(22) +#define EL1_MPU_REGION22_LIMIT EL1_MPU_REGIONXX_LIMIT(22) + +/* region 23 */ +#define EL1_MPU_REGION23_BASE EL1_MPU_REGIONXX_BASE(23) +#define EL1_MPU_REGION23_LIMIT EL1_MPU_REGIONXX_LIMIT(23) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct st_bsp_mpu_config +{ + uint32_t base; + uint32_t limit; +} bsp_mpu_config_t; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +static const bsp_mpu_config_t g_bsp_el1_mpu[EL1_MPU_REGION_COUNT] = +{ + {EL1_MPU_REGION00_BASE, EL1_MPU_REGION00_LIMIT}, + {EL1_MPU_REGION01_BASE, EL1_MPU_REGION01_LIMIT}, + {EL1_MPU_REGION02_BASE, EL1_MPU_REGION02_LIMIT}, + {EL1_MPU_REGION03_BASE, EL1_MPU_REGION03_LIMIT}, + {EL1_MPU_REGION04_BASE, EL1_MPU_REGION04_LIMIT}, + {EL1_MPU_REGION05_BASE, EL1_MPU_REGION05_LIMIT}, + {EL1_MPU_REGION06_BASE, EL1_MPU_REGION06_LIMIT}, + {EL1_MPU_REGION07_BASE, EL1_MPU_REGION07_LIMIT}, + {EL1_MPU_REGION08_BASE, EL1_MPU_REGION08_LIMIT}, + {EL1_MPU_REGION09_BASE, EL1_MPU_REGION09_LIMIT}, + {EL1_MPU_REGION10_BASE, EL1_MPU_REGION10_LIMIT}, + {EL1_MPU_REGION11_BASE, EL1_MPU_REGION11_LIMIT}, + {EL1_MPU_REGION12_BASE, EL1_MPU_REGION12_LIMIT}, + {EL1_MPU_REGION13_BASE, EL1_MPU_REGION13_LIMIT}, + {EL1_MPU_REGION14_BASE, EL1_MPU_REGION14_LIMIT}, + {EL1_MPU_REGION15_BASE, EL1_MPU_REGION15_LIMIT}, + {EL1_MPU_REGION16_BASE, EL1_MPU_REGION16_LIMIT}, + {EL1_MPU_REGION17_BASE, EL1_MPU_REGION17_LIMIT}, + {EL1_MPU_REGION18_BASE, EL1_MPU_REGION18_LIMIT}, + {EL1_MPU_REGION19_BASE, EL1_MPU_REGION19_LIMIT}, + {EL1_MPU_REGION20_BASE, EL1_MPU_REGION20_LIMIT}, + {EL1_MPU_REGION21_BASE, EL1_MPU_REGION21_LIMIT}, + {EL1_MPU_REGION22_BASE, EL1_MPU_REGION22_LIMIT}, + {EL1_MPU_REGION23_BASE, EL1_MPU_REGION23_LIMIT}, +}; + +#if __FPU_USED +void bsp_fpu_advancedsimd_init(void); + +#endif + +#if (0 == BSP_CFG_CORE_CR52) +void bsp_slavetcm_enable(void); + +#endif + +void bsp_memory_protect_setting(void); +void bsp_mpu_init(uint32_t region, uint32_t base, uint32_t limit); +void bsp_irq_cfg_common(void); + +#if __FPU_USED + +/*******************************************************************************************************************//** + * Initialize FPU and Advanced SIMD setting. + **********************************************************************************************************************/ +void bsp_fpu_advancedsimd_init (void) +{ + uint32_t apacr; + uint32_t fpexc; + + /* Enables cp10 and cp11 accessing */ + apacr = __get_CPACR(); + apacr |= BSP_CPCAR_CP_ENABLE; + __set_CPACR(apacr); + __ISB(); + + /* Enables the FPU */ + fpexc = __get_FPEXC(); + fpexc |= BSP_FPEXC_EN_ENABLE; + __set_FPEXC(fpexc); + __ISB(); +} + +#endif + +#if (0 == BSP_CFG_CORE_CR52) + +/*******************************************************************************************************************//** + * Settings the privilege level required for the AXIS to access the TCM. + **********************************************************************************************************************/ +void bsp_slavetcm_enable (void) +{ + uint32_t imp_slavepctlr; + + /* Enable TCM access privilege and non privilege */ + imp_slavepctlr = __get_IMP_SLAVEPCTLR(); + imp_slavepctlr |= BSP_TCM_ALL_ACCESS_ENABLE; + __DSB(); + + __set_IMP_SLAVEPCTLR(imp_slavepctlr); + __ISB(); +} + +#endif + +/*******************************************************************************************************************//** + * Initialize memory protection settings. + **********************************************************************************************************************/ +void bsp_memory_protect_setting (void) +{ + uint32_t sctlr; + uint32_t mair0; + uint32_t mair1; + uint32_t region; + + /* Adopt EL1 default memory map as background map */ + sctlr = __get_SCTLR(); + sctlr |= BSP_SCTLR_BR_BIT; + __DSB(); + __set_SCTLR(sctlr); + __ISB(); + + /* Configure Memory Attribute Indirection Registers */ + mair0 = ATTR_3_2_1_0; + mair1 = ATTR_7_6_5_4; + __set_MAIR0(mair0); + __set_MAIR1(mair1); + __DSB(); + + /* Setup region. */ + for (region = 0; region < EL1_MPU_REGION_COUNT; region++) + { + bsp_mpu_init(region, g_bsp_el1_mpu[region].base, g_bsp_el1_mpu[region].limit); + } + + R_BSP_CacheInvalidateAll(); + + R_BSP_CacheEnableMemoryProtect(); + +#if (BSP_ICACHE_ENABLE == BSP_CFG_SCTLR_I_BIT) + R_BSP_CacheEnableInst(); +#else + R_BSP_CacheDisableInst(); +#endif + +#if (BSP_DATACACHE_ENABLE == BSP_CFG_SCTLR_C_BIT) + R_BSP_CacheEnableData(); +#else + R_BSP_CacheDisableData(); +#endif +} + +/*******************************************************************************************************************//** + * Core MPU initialization block. + **********************************************************************************************************************/ +void bsp_mpu_init (uint32_t region, uint32_t base, uint32_t limit) +{ + /* Selects the current EL1-controlled MPU region registers, PRBAR, and PRLAR */ + __set_PRSELR(region); + __DSB(); + + /* Set the base address and attributes of the MPU region controlled by EL1 */ + __set_PRBAR(base); + __DSB(); + + /* Set the limit address and attributes of the MPU region controlled by EL1 */ + __set_PRLAR(limit); + __DSB(); +} + +/*******************************************************************************************************************//** + * Initialize common configuration settings for interrupts + **********************************************************************************************************************/ +void bsp_irq_cfg_common (void) +{ + uint32_t icc_pmr; + uint32_t icc_igrpen1; + uint32_t icc_ctlr; + + /* Set priority mask level for CPU interface */ + icc_pmr = BSP_PRIORITY_MASK; + __set_ICC_PMR(icc_pmr); + + /* Enable group 1 interrupts */ + icc_igrpen1 = BSP_ENABLE_GROUP_INT; + __set_ICC_IGRPEN1(icc_igrpen1); + + /* Use ICC_BPR0 for interrupt preemption for both group 0 and group 1 interrupts */ + icc_ctlr = __get_ICC_CTLR(); + icc_ctlr |= BSP_ICC_CTLR; + __set_ICC_CTLR(icc_ctlr); + + __ISB(); +} diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c new file mode 100644 index 00000000000..d07a7a294df --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c @@ -0,0 +1,230 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#if (1 == _RZT_ORDINAL) +extern void bsp_master_mpu_init(void); +extern void bsp_global_system_counter_init(void); + + #if BSP_FEATURE_TFU_SUPPORTED +extern void bsp_tfu_init(void); + + #endif +#endif + +#if BSP_CFG_C_RUNTIME_INIT + #if (1 == _RZT_ORDINAL) || BSP_CFG_RAM_EXECUTION +extern void bsp_loader_data_init(void); + + #endif + +extern void bsp_loader_bss_init(void); +extern void bsp_static_constructor_init(void); + +#endif + +#if !(BSP_CFG_RAM_EXECUTION) +extern void bsp_application_bss_init(void); + + #if (1 == _RZT_ORDINAL) +extern void bsp_copy_to_ram(void); +extern void bsp_cpu_reset_release(void); + + #endif +#endif + +#if !BSP_CFG_PORT_PROTECT +extern void bsp_release_port_protect(void); + +#endif + +extern void bsp_memory_protect_setting(void); +extern void bsp_irq_cfg_common(void); + +extern void R_BSP_WarmStart(bsp_warm_start_event_t event); + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +int32_t main(void); + +#if BSP_CFG_EARLY_INIT +static void bsp_init_uninitialized_vars(void); + +#endif + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initialize the MCU and the runtime environment. + **********************************************************************************************************************/ +void SystemInit (void) +{ +#if BSP_CFG_EARLY_INIT + + /* Initialize uninitialized BSP variables early for use in R_BSP_WarmStart. */ + bsp_init_uninitialized_vars(); +#endif + + /* Call before initializing clock and variables. */ + R_BSP_WarmStart(BSP_WARM_START_RESET); + +#if (1 == _RZT_ORDINAL) + + /* Configure system clocks. */ + bsp_clock_init(); +#endif + + /* Call post clock initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK); + +#if BSP_CFG_C_RUNTIME_INIT + #if (1 == _RZT_ORDINAL) || BSP_CFG_RAM_EXECUTION + + /* Copy the primary core loader data from external Flash to internal RAM. */ + bsp_loader_data_init(); + #endif + + /* Clear loader bss section in internal RAM. */ + bsp_loader_bss_init(); +#endif + + /* Initialize SystemCoreClock variable. */ + SystemCoreClockUpdate(); + + /* Set memory attributes, etc. */ + bsp_memory_protect_setting(); + +#if !(BSP_CFG_RAM_EXECUTION) + + /* Clear bss section in internal RAM. */ + bsp_application_bss_init(); + + #if (1 == _RZT_ORDINAL) + + /* Copy the application program from external Flash to internal RAM. + * In the case of multi-core operation, copies each section (vector, loader(program/data), user(program/data)) of + * the secondary core (or later). */ + bsp_copy_to_ram(); + + /* Release the reset state of the slave core */ + bsp_cpu_reset_release(); + #endif +#endif + +#if BSP_CFG_C_RUNTIME_INIT + + /* Initialize static constructors */ + bsp_static_constructor_init(); +#endif + +#if !BSP_CFG_PORT_PROTECT + + /* When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ + bsp_release_port_protect(); +#endif + + /* Call Post C runtime initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_POST_C); + +#if (1 == _RZT_ORDINAL) + #if BSP_CFG_SEMAPHORE_ENABLE + + /* Initialize semaphores required for synchronization and exclusive control between CPUs. */ + bsp_semaphore_init(); + #endif + + /* Initialize the Master-MPU settings. */ + bsp_master_mpu_init(); + + /* Initialize global system counter. The counter is enabled and is incrementing. */ + bsp_global_system_counter_init(); +#endif + + /* GIC initialization */ + bsp_irq_cfg_common(); + + /* Initialize GIC interrupts. */ + bsp_irq_cfg(); + +#if (1 == _RZT_ORDINAL) + #if BSP_FEATURE_TFU_SUPPORTED + + /* Initialize the TFU settings. */ + bsp_tfu_init(); + #endif +#endif + +#if defined(__GNUC__) + extern void entry(void); + entry(); +#elif defined(__ICCARM__) + extern void __low_level_init(void); + __low_level_init(); +#else + /* Jump to main. */ + main(); +#endif +} + +/** @} (end addtogroup BSP_MCU) */ + +#if BSP_CFG_EARLY_INIT + +/*******************************************************************************************************************//** + * Initialize BSP variables not handled by C runtime startup. + **********************************************************************************************************************/ +static void bsp_init_uninitialized_vars (void) +{ + g_protect_port_counter = 0; + + extern volatile uint16_t g_protect_counters[]; + for (uint32_t i = 0; i < 4; i++) + { + g_protect_counters[i] = 0; + } + + SystemCoreClockUpdate(); +} + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c new file mode 100644 index 00000000000..fc50099f451 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c @@ -0,0 +1,1162 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if (1 == _RZT_ORDINAL) + #define BSP_PRV_MASTER_MPU_REGION_NUM (8) + + #define BSP_PRV_MASTER_MPU_STADD(master, region) (BSP_CFG_MPU ## master ## _STADD ## region | \ + (BSP_CFG_MPU ## master ## _WRITE ## region << 1) | \ + BSP_CFG_MPU ## master ## _READ ## region) + + #define BSP_PRV_MASTER_MPU_ENDADD(master, region) (BSP_CFG_MPU ## master ## _ENDADD ## region) + +#endif + +#if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM) + #if !(BSP_CFG_RAM_EXECUTION) + + #define BSP_PRV_IMAGE_INFO_ARRAY_MAX (3) + + #define BSP_PRV_IMAGE_INFO_KEY (0xAC54E6B8) + + #if (0 == BSP_CFG_CORE_CR52) + #define BSP_PRV_IMAGE_INFO_CPU (BSP_PRIV_ASSIGNMENT_CPU_CR52_0) + + #elif (1 == BSP_CFG_CORE_CR52) + #define BSP_PRV_IMAGE_INFO_CPU (BSP_PRIV_ASSIGNMENT_CPU_CR52_1) + + #endif + #endif +#endif + +#if defined(__ICCARM__) + #if BSP_CFG_C_RUNTIME_INIT + #define BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS __section_begin("LDR_DATA_RBLOCK") + #define BSP_PRV_SECTION_LDR_DATA_RAM_START __section_begin("LDR_DATA_WBLOCK") + #define BSP_PRV_SECTION_LDR_DATA_RAM_END __section_end("LDR_DATA_WBLOCK") + + #define BSP_PRV_SECTION_LDR_DATA_BSS_START __section_begin("LDR_DATA_ZBLOCK") + #define BSP_PRV_SECTION_LDR_DATA_BSS_END __section_end("LDR_DATA_ZBLOCK") + + #endif + + #if !(BSP_CFG_RAM_EXECUTION) + #if BSP_CFG_XSPI0_X1_BOOT + #define BSP_PRV_SECTION_SLAVE_ROM_ADDRESS __section_begin("xSPI0_CS0_SPACE_ALIGNMENT_block") + + #elif BSP_CFG_XSPI1_X1_BOOT + #define BSP_PRV_SECTION_SLAVE_ROM_ADDRESS __section_begin("xSPI1_CS0_SPACE_ALIGNMENT_block") + + #elif BSP_CFG_16BIT_NOR_BOOT + #define BSP_PRV_SECTION_SLAVE_ROM_ADDRESS __section_begin("CS0_SPACE_ALIGNMENT_block") + + #endif + + #define BSP_PRV_SECTION_VECTOR_ROM_ADDRESS __section_begin("VECTOR_RBLOCK") + #define BSP_PRV_SECTION_VECTOR_RAM_START __section_begin("VECTOR_WBLOCK") + #define BSP_PRV_SECTION_VECTOR_RAM_END __section_end("VECTOR_WBLOCK") + + #define BSP_PRV_SECTION_USER_PRG_ROM_ADDRESS __section_begin("USER_PRG_RBLOCK") + #define BSP_PRV_SECTION_USER_PRG_RAM_START __section_begin("USER_PRG_WBLOCK") + #define BSP_PRV_SECTION_USER_PRG_RAM_END __section_end("USER_PRG_WBLOCK") + + #define BSP_PRV_SECTION_USER_DATA_ROM_ADDRESS __section_begin("USER_DATA_RBLOCK") + #define BSP_PRV_SECTION_USER_DATA_RAM_START __section_begin("USER_DATA_WBLOCK") + #define BSP_PRV_SECTION_USER_DATA_RAM_END __section_end("USER_DATA_WBLOCK") + + #define BSP_PRV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS __section_begin("USER_DATA_NONCACHE_RBLOCK") + #define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START __section_begin("USER_DATA_NONCACHE_WBLOCK") + #define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_END __section_end("USER_DATA_NONCACHE_WBLOCK") + + #define BSP_PRV_SECTION_USER_DATA_BSS_START __section_begin("USER_DATA_ZBLOCK") + #define BSP_PRV_SECTION_USER_DATA_BSS_END __section_end("USER_DATA_ZBLOCK") + + #define BSP_PRV_SECTION_LDR_PRG_ROM_ADDRESS __section_begin("LDR_PRG_RBLOCK") + #define BSP_PRV_SECTION_LDR_PRG_RAM_START __section_begin("LDR_PRG_WBLOCK") + #define BSP_PRV_SECTION_LDR_PRG_RAM_END __section_end("LDR_PRG_WBLOCK") + + #if !(BSP_CFG_C_RUNTIME_INIT) + #define BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS __section_begin("LDR_DATA_RBLOCK") + #define BSP_PRV_SECTION_LDR_DATA_RAM_START __section_begin("LDR_DATA_WBLOCK") + #define BSP_PRV_SECTION_LDR_DATA_RAM_END __section_end("LDR_DATA_WBLOCK") + + #endif + + #endif + + #if BSP_CFG_RAM_EXECUTION + #define BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_START __section_begin("NONCACHE_BUFFER_ZBLOCK") + #define BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_END __section_end("NONCACHE_BUFFER_ZBLOCK") + + #if (1 == _RZT_ORDINAL) + #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_START __section_begin("SHARED_NONCACHE_BUFFER_ZBLOCK") + #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_END __section_end("SHARED_NONCACHE_BUFFER_ZBLOCK") + + #endif + + #define BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_START __section_begin("DMAC_LINK_MODE_ZBLOCK") + #define BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_END __section_end("DMAC_LINK_MODE_ZBLOCK") + + #endif + +#elif defined(__GNUC__) + #if BSP_CFG_C_RUNTIME_INIT + #define BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS &_mloader_data + #define BSP_PRV_SECTION_LDR_DATA_RAM_START &__loader_data_start + #define BSP_PRV_SECTION_LDR_DATA_RAM_END &__loader_data_end + + #define BSP_PRV_SECTION_LDR_DATA_BSS_START &__loader_bss_start + #define BSP_PRV_SECTION_LDR_DATA_BSS_END &__loader_bss_end + + #endif + + #if !(BSP_CFG_RAM_EXECUTION) + #if BSP_CFG_XSPI0_X1_BOOT + #define BSP_PRV_SECTION_SLAVE_ROM_ADDRESS &__ddsc_xSPI0_CS0_SPACE_ALIGNMENT + + #elif BSP_CFG_XSPI1_X1_BOOT + #define BSP_PRV_SECTION_SLAVE_ROM_ADDRESS &__ddsc_xSPI1_CS0_SPACE_ALIGNMENT + + #elif BSP_CFG_16BIT_NOR_BOOT + #define BSP_PRV_SECTION_SLAVE_ROM_ADDRESS &__ddsc_CS0_SPACE_ALIGNMENT + + #endif + + #define BSP_PRV_SECTION_VECTOR_ROM_ADDRESS &_mfvector + #define BSP_PRV_SECTION_VECTOR_RAM_START &_fvector_start + #define BSP_PRV_SECTION_VECTOR_RAM_END &_fvector_end + + #define BSP_PRV_SECTION_USER_PRG_ROM_ADDRESS &_mtext + #define BSP_PRV_SECTION_USER_PRG_RAM_START &_text_start + #define BSP_PRV_SECTION_USER_PRG_RAM_END &_text_end + + #define BSP_PRV_SECTION_USER_DATA_ROM_ADDRESS &_mdata + #define BSP_PRV_SECTION_USER_DATA_RAM_START &_data_start + #define BSP_PRV_SECTION_USER_DATA_RAM_END &_data_end + + #define BSP_PRV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS &_mdata_noncache + #define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START &_data_noncache_start + #define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_END &_data_noncache_end + + #define BSP_PRV_SECTION_LDR_PRG_ROM_ADDRESS &_mloader_text + #define BSP_PRV_SECTION_LDR_PRG_RAM_START &_loader_text_start + #define BSP_PRV_SECTION_LDR_PRG_RAM_END &_loader_text_end + + #if !(BSP_CFG_C_RUNTIME_INIT) + #define BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS &_mloader_data + #define BSP_PRV_SECTION_LDR_DATA_RAM_START &__loader_data_start + #define BSP_PRV_SECTION_LDR_DATA_RAM_END &__loader_data_end + + #endif + #endif + + #define BSP_PRV_SECTION_USER_DATA_BSS_START &__bss_start__ + #define BSP_PRV_SECTION_USER_DATA_BSS_END &__bss_end__ + + #if BSP_CFG_RAM_EXECUTION + #define BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_START &_ncbuffer_start + #define BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_END &_ncbuffer_end + + #if (1 == _RZT_ORDINAL) + #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_START &_sncbuffer_start + #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_END &_sncbuffer_end + + #endif + + #define BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_START &_DmacLinkMode_start + #define BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_END &_DmacLinkMode_end + + #endif +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM) + #if !(BSP_CFG_RAM_EXECUTION) + #if (1 == _RZT_ORDINAL) +typedef enum e_bsp_image_info +{ + BSP_PRIV_IMAGE_INFO_KEY = 0, + + BSP_PRIV_IMAGE_INFO_CPU = 1, + + BSP_PRIV_IMAGE_INFO_SECTION_ADDRESS = 2, +} bsp_image_info_t; + +typedef enum e_bsp_section +{ + BSP_PRIV_SECTION_SLAVE_ROM_ADDRESS = 0, + + BSP_PRIV_SECTION_VECTOR_ROM_ADDRESS = 1, + BSP_PRIV_SECTION_VECTOR_RAM_START = 2, + BSP_PRIV_SECTION_VECTOR_RAM_END = 3, + + BSP_PRIV_SECTION_LDR_PRG_ROM_ADDRESS = 4, + BSP_PRIV_SECTION_LDR_PRG_RAM_START = 5, + BSP_PRIV_SECTION_LDR_PRG_RAM_END = 6, + + BSP_PRIV_SECTION_LDR_DATA_ROM_ADDRESS = 7, + BSP_PRIV_SECTION_LDR_DATA_RAM_START = 8, + BSP_PRIV_SECTION_LDR_DATA_RAM_END = 9, + + BSP_PRIV_SECTION_USER_PRG_ROM_ADDRESS = 10, + BSP_PRIV_SECTION_USER_PRG_RAM_START = 11, + BSP_PRIV_SECTION_USER_PRG_RAM_END = 12, + + BSP_PRIV_SECTION_USER_DATA_ROM_ADDRESS = 13, + BSP_PRIV_SECTION_USER_DATA_RAM_START = 14, + BSP_PRIV_SECTION_USER_DATA_RAM_END = 15, + + BSP_PRIV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS = 16, + BSP_PRIV_SECTION_USER_DATA_NONCACHE_RAM_START = 17, + BSP_PRIV_SECTION_USER_DATA_NONCACHE_RAM_END = 18, +} bsp_section_t; + + #endif + +typedef enum e_bsp_assignment_cpu +{ + BSP_PRIV_ASSIGNMENT_CPU_CR52_0 = 0xAC54E000, + BSP_PRIV_ASSIGNMENT_CPU_CR52_1 = 0xAC54E001, +} bsp_assignment_cpu_t; + + #endif +#endif + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClock = 0U; + +/** @} (end addtogroup BSP_MCU) */ + +#if defined(__ICCARM__) + #if BSP_CFG_C_RUNTIME_INIT + #pragma section="LDR_DATA_RBLOCK" + #pragma section="LDR_DATA_WBLOCK" + #pragma section="LDR_DATA_ZBLOCK" + + #endif + + #if !(BSP_CFG_RAM_EXECUTION) + #if BSP_CFG_XSPI0_X1_BOOT + #pragma section="xSPI0_CS0_SPACE_ALIGNMENT_block" + + #elif BSP_CFG_XSPI1_X1_BOOT + #pragma section="xSPI1_CS0_SPACE_ALIGNMENT_block" + + #elif BSP_CFG_16BIT_NOR_BOOT + #pragma section="CS0_SPACE_ALIGNMENT_block" + + #endif + + #pragma section="VECTOR_RBLOCK" + #pragma section="VECTOR_WBLOCK" + + #pragma section="USER_PRG_RBLOCK" + #pragma section="USER_PRG_WBLOCK" + + #pragma section="USER_DATA_RBLOCK" + #pragma section="USER_DATA_WBLOCK" + #pragma section="USER_DATA_ZBLOCK" + + #pragma section="USER_DATA_NONCACHE_RBLOCK" + #pragma section="USER_DATA_NONCACHE_WBLOCK" + + #pragma section="LDR_PRG_RBLOCK" + #pragma section="LDR_PRG_WBLOCK" + + #if !(BSP_CFG_C_RUNTIME_INIT) + #pragma section="LDR_DATA_RBLOCK" + #pragma section="LDR_DATA_WBLOCK" + + #endif + #endif + + #if BSP_CFG_RAM_EXECUTION + #pragma section="NONCACHE_BUFFER_ZBLOCK" + + #if (1 == _RZT_ORDINAL) + #pragma section="SHARED_NONCACHE_BUFFER_ZBLOCK" + + #endif + + #pragma section="DMAC_LINK_MODE_ZBLOCK" + + #endif + +#elif defined(__GNUC__) + #if BSP_CFG_C_RUNTIME_INIT +extern void * _mloader_data; +extern void * __loader_data_start; +extern void * __loader_data_end; + +extern void * __loader_bss_start; +extern void * __loader_bss_end; + +extern void (* __preinit_array_start[])(void); +extern void (* __preinit_array_end[])(void); +extern void (* __init_array_start[])(void); +extern void (* __init_array_end[])(void); + + #endif + + #if !(BSP_CFG_RAM_EXECUTION) + #if BSP_CFG_XSPI0_X1_BOOT +extern void * __ddsc_xSPI0_CS0_SPACE_ALIGNMENT; + + #elif BSP_CFG_XSPI1_X1_BOOT +extern void * __ddsc_xSPI1_CS0_SPACE_ALIGNMENT; + + #elif BSP_CFG_16BIT_NOR_BOOT +extern void * __ddsc_CS0_SPACE_ALIGNMENT; + + #endif + +extern void * _mfvector; +extern void * _fvector_start; +extern void * _fvector_end; + +extern void * _mtext; +extern void * _text_start; +extern void * _text_end; + +extern void * _mdata; +extern void * _data_start; +extern void * _data_end; + +extern void * _mdata_noncache; +extern void * _data_noncache_start; +extern void * _data_noncache_end; + +extern void * _mloader_text; +extern void * _loader_text_start; +extern void * _loader_text_end; + + #if !(BSP_CFG_C_RUNTIME_INIT) +extern void * _mloader_data; +extern void * __loader_data_start; +extern void * __loader_data_end; + + #endif + #endif + +extern void * __bss_start__; +extern void * __bss_end__; + + #if BSP_CFG_RAM_EXECUTION +extern void * _ncbuffer_start; +extern void * _ncbuffer_end; + + #if (1 == _RZT_ORDINAL) +extern void * _sncbuffer_start; +extern void * _sncbuffer_end; + + #endif + +extern void * _DmacLinkMode_start; +extern void * _DmacLinkMode_end; + + #endif +#endif + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#if defined(__ICCARM__) + #if BSP_CFG_C_RUNTIME_INIT +extern void __iar_data_init3(void); + + #endif +#endif + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +#if (1 == _RZT_ORDINAL) + #if (1 == BSP_FEATURE_BSP_MASTER_MPU0_SUPPORTED) +const uint32_t g_bsp_master_mpu0_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] = +{ + {BSP_PRV_MASTER_MPU_STADD(0, 0), BSP_PRV_MASTER_MPU_ENDADD(0, 0)}, + {BSP_PRV_MASTER_MPU_STADD(0, 1), BSP_PRV_MASTER_MPU_ENDADD(0, 1)}, + {BSP_PRV_MASTER_MPU_STADD(0, 2), BSP_PRV_MASTER_MPU_ENDADD(0, 2)}, + {BSP_PRV_MASTER_MPU_STADD(0, 3), BSP_PRV_MASTER_MPU_ENDADD(0, 3)}, + {BSP_PRV_MASTER_MPU_STADD(0, 4), BSP_PRV_MASTER_MPU_ENDADD(0, 4)}, + {BSP_PRV_MASTER_MPU_STADD(0, 5), BSP_PRV_MASTER_MPU_ENDADD(0, 5)}, + {BSP_PRV_MASTER_MPU_STADD(0, 6), BSP_PRV_MASTER_MPU_ENDADD(0, 6)}, + {BSP_PRV_MASTER_MPU_STADD(0, 7), BSP_PRV_MASTER_MPU_ENDADD(0, 7)} +}; + #endif + #if (1 == BSP_FEATURE_BSP_MASTER_MPU1_SUPPORTED) +const uint32_t g_bsp_master_mpu1_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] = +{ + {BSP_PRV_MASTER_MPU_STADD(1, 0), BSP_PRV_MASTER_MPU_ENDADD(1, 0)}, + {BSP_PRV_MASTER_MPU_STADD(1, 1), BSP_PRV_MASTER_MPU_ENDADD(1, 1)}, + {BSP_PRV_MASTER_MPU_STADD(1, 2), BSP_PRV_MASTER_MPU_ENDADD(1, 2)}, + {BSP_PRV_MASTER_MPU_STADD(1, 3), BSP_PRV_MASTER_MPU_ENDADD(1, 3)}, + {BSP_PRV_MASTER_MPU_STADD(1, 4), BSP_PRV_MASTER_MPU_ENDADD(1, 4)}, + {BSP_PRV_MASTER_MPU_STADD(1, 5), BSP_PRV_MASTER_MPU_ENDADD(1, 5)}, + {BSP_PRV_MASTER_MPU_STADD(1, 6), BSP_PRV_MASTER_MPU_ENDADD(1, 6)}, + {BSP_PRV_MASTER_MPU_STADD(1, 7), BSP_PRV_MASTER_MPU_ENDADD(1, 7)} +}; + #endif + #if (1 == BSP_FEATURE_BSP_MASTER_MPU2_SUPPORTED) +const uint32_t g_bsp_master_mpu2_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] = +{ + {BSP_PRV_MASTER_MPU_STADD(2, 0), BSP_PRV_MASTER_MPU_ENDADD(2, 0)}, + {BSP_PRV_MASTER_MPU_STADD(2, 1), BSP_PRV_MASTER_MPU_ENDADD(2, 1)}, + {BSP_PRV_MASTER_MPU_STADD(2, 2), BSP_PRV_MASTER_MPU_ENDADD(2, 2)}, + {BSP_PRV_MASTER_MPU_STADD(2, 3), BSP_PRV_MASTER_MPU_ENDADD(2, 3)}, + {BSP_PRV_MASTER_MPU_STADD(2, 4), BSP_PRV_MASTER_MPU_ENDADD(2, 4)}, + {BSP_PRV_MASTER_MPU_STADD(2, 5), BSP_PRV_MASTER_MPU_ENDADD(2, 5)}, + {BSP_PRV_MASTER_MPU_STADD(2, 6), BSP_PRV_MASTER_MPU_ENDADD(2, 6)}, + {BSP_PRV_MASTER_MPU_STADD(2, 7), BSP_PRV_MASTER_MPU_ENDADD(2, 7)} +}; + #endif + #if (1 == BSP_FEATURE_BSP_MASTER_MPU3_SUPPORTED) +const uint32_t g_bsp_master_mpu3_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] = +{ + {BSP_PRV_MASTER_MPU_STADD(3, 0), BSP_PRV_MASTER_MPU_ENDADD(3, 0)}, + {BSP_PRV_MASTER_MPU_STADD(3, 1), BSP_PRV_MASTER_MPU_ENDADD(3, 1)}, + {BSP_PRV_MASTER_MPU_STADD(3, 2), BSP_PRV_MASTER_MPU_ENDADD(3, 2)}, + {BSP_PRV_MASTER_MPU_STADD(3, 3), BSP_PRV_MASTER_MPU_ENDADD(3, 3)}, + {BSP_PRV_MASTER_MPU_STADD(3, 4), BSP_PRV_MASTER_MPU_ENDADD(3, 4)}, + {BSP_PRV_MASTER_MPU_STADD(3, 5), BSP_PRV_MASTER_MPU_ENDADD(3, 5)}, + {BSP_PRV_MASTER_MPU_STADD(3, 6), BSP_PRV_MASTER_MPU_ENDADD(3, 6)}, + {BSP_PRV_MASTER_MPU_STADD(3, 7), BSP_PRV_MASTER_MPU_ENDADD(3, 7)} +}; + #endif + #if (1 == BSP_FEATURE_BSP_MASTER_MPU4_SUPPORTED) +const uint32_t g_bsp_master_mpu4_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] = +{ + {BSP_PRV_MASTER_MPU_STADD(4, 0), BSP_PRV_MASTER_MPU_ENDADD(4, 0)}, + {BSP_PRV_MASTER_MPU_STADD(4, 1), BSP_PRV_MASTER_MPU_ENDADD(4, 1)}, + {BSP_PRV_MASTER_MPU_STADD(4, 2), BSP_PRV_MASTER_MPU_ENDADD(4, 2)}, + {BSP_PRV_MASTER_MPU_STADD(4, 3), BSP_PRV_MASTER_MPU_ENDADD(4, 3)}, + {BSP_PRV_MASTER_MPU_STADD(4, 4), BSP_PRV_MASTER_MPU_ENDADD(4, 4)}, + {BSP_PRV_MASTER_MPU_STADD(4, 5), BSP_PRV_MASTER_MPU_ENDADD(4, 5)}, + {BSP_PRV_MASTER_MPU_STADD(4, 6), BSP_PRV_MASTER_MPU_ENDADD(4, 6)}, + {BSP_PRV_MASTER_MPU_STADD(4, 7), BSP_PRV_MASTER_MPU_ENDADD(4, 7)} +}; + #endif + #if (1 == BSP_FEATURE_BSP_MASTER_MPU6_SUPPORTED) +const uint32_t g_bsp_master_mpu6_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] = +{ + {BSP_PRV_MASTER_MPU_STADD(6, 0), BSP_PRV_MASTER_MPU_ENDADD(6, 0)}, + {BSP_PRV_MASTER_MPU_STADD(6, 1), BSP_PRV_MASTER_MPU_ENDADD(6, 1)}, + {BSP_PRV_MASTER_MPU_STADD(6, 2), BSP_PRV_MASTER_MPU_ENDADD(6, 2)}, + {BSP_PRV_MASTER_MPU_STADD(6, 3), BSP_PRV_MASTER_MPU_ENDADD(6, 3)}, + {BSP_PRV_MASTER_MPU_STADD(6, 4), BSP_PRV_MASTER_MPU_ENDADD(6, 4)}, + {BSP_PRV_MASTER_MPU_STADD(6, 5), BSP_PRV_MASTER_MPU_ENDADD(6, 5)}, + {BSP_PRV_MASTER_MPU_STADD(6, 6), BSP_PRV_MASTER_MPU_ENDADD(6, 6)}, + {BSP_PRV_MASTER_MPU_STADD(6, 7), BSP_PRV_MASTER_MPU_ENDADD(6, 7)} +}; + #endif + #if (1 == BSP_FEATURE_BSP_MASTER_MPU7_SUPPORTED) +const uint32_t g_bsp_master_mpu7_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] = +{ + {BSP_PRV_MASTER_MPU_STADD(7, 0), BSP_PRV_MASTER_MPU_ENDADD(7, 0)}, + {BSP_PRV_MASTER_MPU_STADD(7, 1), BSP_PRV_MASTER_MPU_ENDADD(7, 1)}, + {BSP_PRV_MASTER_MPU_STADD(7, 2), BSP_PRV_MASTER_MPU_ENDADD(7, 2)}, + {BSP_PRV_MASTER_MPU_STADD(7, 3), BSP_PRV_MASTER_MPU_ENDADD(7, 3)}, + {BSP_PRV_MASTER_MPU_STADD(7, 4), BSP_PRV_MASTER_MPU_ENDADD(7, 4)}, + {BSP_PRV_MASTER_MPU_STADD(7, 5), BSP_PRV_MASTER_MPU_ENDADD(7, 5)}, + {BSP_PRV_MASTER_MPU_STADD(7, 6), BSP_PRV_MASTER_MPU_ENDADD(7, 6)}, + {BSP_PRV_MASTER_MPU_STADD(7, 7), BSP_PRV_MASTER_MPU_ENDADD(7, 7)} +}; + #endif +#endif + +#if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM) + #if !(BSP_CFG_RAM_EXECUTION) + #if (1 != _RZT_ORDINAL) + +const uint32_t g_bsp_image_info_section[] BSP_PLACE_IN_SECTION (".image_info") = +{ + (uint32_t) BSP_PRV_SECTION_SLAVE_ROM_ADDRESS, + + (uint32_t) BSP_PRV_SECTION_VECTOR_ROM_ADDRESS, + (uint32_t) BSP_PRV_SECTION_VECTOR_RAM_START, + (uint32_t) BSP_PRV_SECTION_VECTOR_RAM_END, + + (uint32_t) BSP_PRV_SECTION_LDR_PRG_ROM_ADDRESS, + (uint32_t) BSP_PRV_SECTION_LDR_PRG_RAM_START, + (uint32_t) BSP_PRV_SECTION_LDR_PRG_RAM_END, + + (uint32_t) BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS, + (uint32_t) BSP_PRV_SECTION_LDR_DATA_RAM_START, + (uint32_t) BSP_PRV_SECTION_LDR_DATA_RAM_END, + + (uint32_t) BSP_PRV_SECTION_USER_PRG_ROM_ADDRESS, + (uint32_t) BSP_PRV_SECTION_USER_PRG_RAM_START, + (uint32_t) BSP_PRV_SECTION_USER_PRG_RAM_END, + + (uint32_t) BSP_PRV_SECTION_USER_DATA_ROM_ADDRESS, + (uint32_t) BSP_PRV_SECTION_USER_DATA_RAM_START, + (uint32_t) BSP_PRV_SECTION_USER_DATA_RAM_END, + + (uint32_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS, + (uint32_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START, + (uint32_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_END, +}; + +const uint32_t g_bsp_image_info_array[BSP_PRV_IMAGE_INFO_ARRAY_MAX] BSP_PLACE_IN_SECTION(BSP_SECTION_LOADER_PARAM) = +{ + (uint32_t) BSP_PRV_IMAGE_INFO_KEY, + + (uint32_t) BSP_PRV_IMAGE_INFO_CPU, + + (uint32_t) g_bsp_image_info_section +}; + + #endif + #endif + + #if defined(__ICCARM__) + #if BSP_CFG_RAM_EXECUTION +BSP_DONT_REMOVE const void * const __ddsc_SYSTEM_RAM_END BSP_PLACE_IN_SECTION(".ddsc_system_ram_end") = 0; + + #elif BSP_CFG_XSPI0_X1_BOOT +BSP_DONT_REMOVE const void * const __ddsc_xSPI0_CS0_SPACE_END BSP_PLACE_IN_SECTION(".ddsc_xspi0_cs0_space_end") = 0; + + #elif BSP_CFG_16BIT_NOR_BOOT +BSP_DONT_REMOVE const void * const __ddsc_CS0_SPACE_END BSP_PLACE_IN_SECTION(".ddsc_cs0_space_end") = 0; + + #endif + #endif +#endif + +#if defined(__ICCARM__) + +void R_BSP_WarmStart(bsp_warm_start_event_t event); + + #pragma weak R_BSP_WarmStart + +#elif defined(__GNUC__) || defined(__ARMCC_VERSION) + +void R_BSP_WarmStart(bsp_warm_start_event_t event) __attribute__((weak)); + +#endif + +#if BSP_CFG_C_RUNTIME_INIT + #if (1 == _RZT_ORDINAL) || BSP_CFG_RAM_EXECUTION +void bsp_loader_data_init(void); + + #endif + +void bsp_loader_bss_init(void); +void bsp_static_constructor_init(void); + +#endif + +void bsp_copy_multibyte(uintptr_t * src, uintptr_t * dst, uintptr_t bytesize); +void bsp_bss_init_multibyte(uintptr_t * src, uintptr_t bytesize); + +#if !(BSP_CFG_RAM_EXECUTION) +void bsp_application_bss_init(void); + + #if (1 == _RZT_ORDINAL) +void bsp_copy_to_ram(void); +void bsp_cpu_reset_release(void); + + #endif +#endif + +#if (1 == _RZT_ORDINAL) +void bsp_master_mpu_init(void); +void bsp_global_system_counter_init(void); + + #if BSP_FEATURE_TFU_SUPPORTED +void bsp_tfu_init(void); + + #endif +#endif + +#if !BSP_CFG_PORT_PROTECT +void bsp_release_port_protect(void); + +#endif + +#if (1 == _RZT_ORDINAL) + +/*******************************************************************************************************************//** + * Initialize the Master-MPU settings. + **********************************************************************************************************************/ +void bsp_master_mpu_init (void) +{ + /* Disable register protection for Master-MPU related registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM); + + for (uint8_t region_num = 0; region_num < BSP_PRV_MASTER_MPU_REGION_NUM; region_num++) + { + #if (1 == BSP_FEATURE_BSP_MASTER_MPU0_SUPPORTED) + R_MPU0->RGN[region_num].STADD = g_bsp_master_mpu0_cfg[region_num][0]; + R_MPU0->RGN[region_num].ENDADD = g_bsp_master_mpu0_cfg[region_num][1]; + #endif + #if (1 == BSP_FEATURE_BSP_MASTER_MPU1_SUPPORTED) + R_MPU1->RGN[region_num].STADD = g_bsp_master_mpu1_cfg[region_num][0]; + R_MPU1->RGN[region_num].ENDADD = g_bsp_master_mpu1_cfg[region_num][1]; + #endif + #if (1 == BSP_FEATURE_BSP_MASTER_MPU2_SUPPORTED) + R_MPU2->RGN[region_num].STADD = g_bsp_master_mpu2_cfg[region_num][0]; + R_MPU2->RGN[region_num].ENDADD = g_bsp_master_mpu2_cfg[region_num][1]; + #endif + #if (1 == BSP_FEATURE_BSP_MASTER_MPU3_SUPPORTED) + R_MPU3->RGN[region_num].STADD = g_bsp_master_mpu3_cfg[region_num][0]; + R_MPU3->RGN[region_num].ENDADD = g_bsp_master_mpu3_cfg[region_num][1]; + #endif + #if (1 == BSP_FEATURE_BSP_MASTER_MPU4_SUPPORTED) + R_MPU4->RGN[region_num].STADD = g_bsp_master_mpu4_cfg[region_num][0]; + R_MPU4->RGN[region_num].ENDADD = g_bsp_master_mpu4_cfg[region_num][1]; + #endif + #if (1 == BSP_FEATURE_BSP_MASTER_MPU6_SUPPORTED) + R_MPU6->RGN[region_num].STADD = g_bsp_master_mpu6_cfg[region_num][0]; + R_MPU6->RGN[region_num].ENDADD = g_bsp_master_mpu6_cfg[region_num][1]; + #endif + #if (1 == BSP_FEATURE_BSP_MASTER_MPU7_SUPPORTED) + R_MPU7->RGN[region_num].STADD = g_bsp_master_mpu7_cfg[region_num][0]; + R_MPU7->RGN[region_num].ENDADD = g_bsp_master_mpu7_cfg[region_num][1]; + #endif + } + + /* Enable register protection for Master-MPU related registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM); +} + +/*******************************************************************************************************************//** + * Initialize global system counter. The counter is enabled and is incrementing. + **********************************************************************************************************************/ +void bsp_global_system_counter_init (void) +{ + /* Initialize registers related the global system counter. */ + R_GSC->CNTCR &= (uint32_t) (~R_GSC_CNTCR_EN_Msk); + R_GSC->CNTFID0 = BSP_GLOBAL_SYSTEM_COUNTER_CLOCK_HZ; + R_GSC->CNTCVL = 0; + R_GSC->CNTCVU = 0; + R_GSC->CNTCR |= R_GSC_CNTCR_EN_Msk; +} + +#endif + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This function is called at various points during the startup process. + * This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user + * implemented version. One of the main uses for this function is to call functional safety code during the startup + * process. To use this function just copy this function into your own code and modify it to meet your needs. + * + * @param[in] event Where the code currently is in the start up process + * + * + * @note All programs to be executed when BSP_WARM_START_RESET or BSP_WARM_START_POST_CLOCK event occurs should be + * placed in BTCM. These events occur before copying the application program in startup code is executed, and + * therefore the application program is located on ROM and cannot be executed at that time. + * Linker script for FSP specifies that .warm_start section is to be placed at BTCM. Adding the section + * designation to function or variable definition makes it easy to place at BTCM. + **********************************************************************************************************************/ +void R_BSP_WarmStart (bsp_warm_start_event_t event) +{ + if (BSP_WARM_START_RESET == event) + { + /* C runtime environment has not been setup so you cannot use globals. System clocks are not setup. */ + } + + if (BSP_WARM_START_POST_CLOCK == event) + { + /* C runtime environment has not been setup so you cannot use globals. Clocks have been initialized. */ + } + else if (BSP_WARM_START_POST_C == event) + { + /* C runtime environment, system clocks, and pins are all setup. */ + } + else + { + /* Do nothing */ + } +} + +/** @} (end addtogroup BSP_MCU) */ + +#if BSP_CFG_C_RUNTIME_INIT + #if (1 == _RZT_ORDINAL) || BSP_CFG_RAM_EXECUTION + +/*******************************************************************************************************************//** + * Copy the loader data block from external Flash to internal RAM. + **********************************************************************************************************************/ +void bsp_loader_data_init (void) +{ + #if (!defined(__GNUC__) || !(BSP_CFG_RAM_EXECUTION)) + + /* Define destination/source address pointer and block size */ + uintptr_t * src; + uintptr_t * dst; + uintptr_t size; + + /* Copy loader data block */ + src = (uintptr_t *) BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS; + dst = (uintptr_t *) BSP_PRV_SECTION_LDR_DATA_RAM_START; + size = (uintptr_t) BSP_PRV_SECTION_LDR_DATA_RAM_END - (uintptr_t) BSP_PRV_SECTION_LDR_DATA_RAM_START; + bsp_copy_multibyte(src, dst, size); + #endif +} + + #endif + +/*******************************************************************************************************************//** + * Clear the loader bss block in internal RAM. + **********************************************************************************************************************/ +void bsp_loader_bss_init (void) +{ + /* Define source address pointer and block size */ + uintptr_t * src; + uintptr_t size; + + /* Clear loader bss block. */ + src = (uintptr_t *) BSP_PRV_SECTION_LDR_DATA_BSS_START; + size = (uintptr_t) BSP_PRV_SECTION_LDR_DATA_BSS_END - (uintptr_t) BSP_PRV_SECTION_LDR_DATA_BSS_START; + bsp_bss_init_multibyte(src, size); + + #if BSP_CFG_RAM_EXECUTION + #if defined(__ICCARM__) + + /* Initialize the application data and clear the application bss. + * This code is for RAM Execution. If you want to boot with ROM, + * enable app_copy and app_bss_init, and disable this code. + * Also need to change icf file. */ + __iar_data_init3(); + #elif defined(__GNUC__) + + /* Clear application bss block. */ + src = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_BSS_START; + size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_END - (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_START; + bsp_bss_init_multibyte(src, size); + #endif + + /* Clear non-cache buffer block. */ + src = (uintptr_t *) BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_START; + size = (uintptr_t) BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_END - + (uintptr_t) BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_START; + bsp_bss_init_multibyte(src, size); + + #if (1 == _RZT_ORDINAL) + + /* Clear shared non-cache buffer block. */ + src = (uintptr_t *) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_START; + size = (uintptr_t) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_END - + (uintptr_t) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_START; + bsp_bss_init_multibyte(src, size); + #endif + + /* Clear DMAC link mode data block. */ + src = (uintptr_t *) BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_START; + size = (uintptr_t) BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_END - + (uintptr_t) BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_START; + bsp_bss_init_multibyte(src, size); + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Copy the memory block from Source address to Destination address by the multi byte unit. + **********************************************************************************************************************/ +void bsp_copy_multibyte (uintptr_t * src, uintptr_t * dst, uintptr_t bytesize) +{ + uintptr_t i; + uintptr_t cnt; + + uintptr_t src_mod; + uint8_t * src_single_byte; + uint8_t * dst_single_byte; + + if (0 != bytesize) + { + /* Copy Count in single byte unit */ + src_mod = (uintptr_t) src % sizeof(uintptr_t); + + if (0 != src_mod) + { + src_single_byte = (uint8_t *) src; + dst_single_byte = (uint8_t *) dst; + + for (i = 0; i < src_mod; i++) + { + *dst_single_byte++ = *src_single_byte++; + } + + dst = (uintptr_t *) dst_single_byte; + src = (uintptr_t *) src_single_byte; + bytesize -= src_mod; + } + else + { + /* Do nothing */ + } + + /* Copy Count in multi byte unit */ + cnt = (bytesize + (sizeof(uintptr_t) - 1)) / sizeof(uintptr_t); + + for (i = 0; i < cnt; i++) + { + *dst++ = *src++; + } + + /* Ensuring data-changing */ + __asm volatile ("DSB SY"); + } + else + { + /* Do nothing */ + } +} + +/*******************************************************************************************************************//** + * Clear the bss block by the multi byte unit. + **********************************************************************************************************************/ +void bsp_bss_init_multibyte (uintptr_t * src, uintptr_t bytesize) +{ + uintptr_t i; + uintptr_t cnt; + uintptr_t zero = 0; + + uintptr_t src_mod; + uint8_t * src_single_byte; + uint8_t zero_single_byte = 0; + + if (0 != bytesize) + { + /* Clear Count in single byte unit */ + src_mod = (uintptr_t) src % sizeof(uintptr_t); + + if (0 != src_mod) + { + src_single_byte = (uint8_t *) src; + + for (i = 0; i < src_mod; i++) + { + *src_single_byte++ = zero_single_byte; + } + + src = (uintptr_t *) src_single_byte; + bytesize -= src_mod; + } + else + { + /* Do nothing */ + } + + /* Clear Count in multi byte unit */ + cnt = (bytesize + (sizeof(uintptr_t) - 1)) / sizeof(uintptr_t); + + for (i = 0; i < cnt; i++) + { + *src++ = zero; + } + + /* Ensuring data-changing */ + __asm volatile ("DSB SY"); + } + else + { + /* Do nothing */ + } +} + +#if !(BSP_CFG_RAM_EXECUTION) + +/*******************************************************************************************************************//** + * Clear the application bss block in internal RAM. + **********************************************************************************************************************/ +void bsp_application_bss_init (void) +{ + /* Define source address pointer and block size */ + uintptr_t * src; + uintptr_t size; + + /* Clear application bss block. */ + src = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_BSS_START; + size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_END - (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_START; + bsp_bss_init_multibyte(src, size); +} + + #if (1 == _RZT_ORDINAL) + +/*******************************************************************************************************************//** + * Copy the application program block from external Flash to internal RAM. + * In the case of multi-core operation, copies each section (vector, loader(program/data), user(program/data)) of + * the secondary core (or later). + **********************************************************************************************************************/ +void bsp_copy_to_ram (void) +{ + /* Define destination/source address pointer and block size */ + uintptr_t * src; + uintptr_t * dst; + uintptr_t size; + + /* Copy exception vector block */ + src = (uintptr_t *) BSP_PRV_SECTION_VECTOR_ROM_ADDRESS; + dst = (uintptr_t *) BSP_PRV_SECTION_VECTOR_RAM_START; + size = (uintptr_t) BSP_PRV_SECTION_VECTOR_RAM_END - (uintptr_t) BSP_PRV_SECTION_VECTOR_RAM_START; + bsp_copy_multibyte(src, dst, size); + + /* Copy user program block */ + src = (uintptr_t *) BSP_PRV_SECTION_USER_PRG_ROM_ADDRESS; + dst = (uintptr_t *) BSP_PRV_SECTION_USER_PRG_RAM_START; + size = (uintptr_t) BSP_PRV_SECTION_USER_PRG_RAM_END - (uintptr_t) BSP_PRV_SECTION_USER_PRG_RAM_START; + bsp_copy_multibyte(src, dst, size); + + /* Copy user data block */ + src = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_ROM_ADDRESS; + dst = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_RAM_START; + size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_RAM_END - (uintptr_t) BSP_PRV_SECTION_USER_DATA_RAM_START; + bsp_copy_multibyte(src, dst, size); + + /* Copy user data_noncache block */ + src = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS; + dst = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START; + size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_END - + (uintptr_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START; + bsp_copy_multibyte(src, dst, size); + + #if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM) + + /* Define a pointer to refer to the address of each section of the secondary core (or later) */ + uint32_t * image_info = (uint32_t *) BSP_PRV_SECTION_SLAVE_ROM_ADDRESS; + + /* Determine whether the secondary core (or later) binary exists */ + while ((BSP_PRV_IMAGE_INFO_KEY == image_info[BSP_PRIV_IMAGE_INFO_KEY]) && + (BSP_PRIV_ASSIGNMENT_CPU_CR52_0 <= image_info[BSP_PRIV_IMAGE_INFO_CPU]) && + (BSP_PRIV_ASSIGNMENT_CPU_CR52_1 >= image_info[BSP_PRIV_IMAGE_INFO_CPU])) + { + /* Assign the address of the array that stores the address of each section of the secondary core (or later) */ + image_info = (uint32_t *) image_info[BSP_PRIV_IMAGE_INFO_SECTION_ADDRESS]; + + /* Copy exception vector block on the secondary core (or later) */ + src = (uintptr_t *) image_info[BSP_PRIV_SECTION_VECTOR_ROM_ADDRESS]; + dst = (uintptr_t *) image_info[BSP_PRIV_SECTION_VECTOR_RAM_START]; + size = (uintptr_t) image_info[BSP_PRIV_SECTION_VECTOR_RAM_END] - + (uintptr_t) image_info[BSP_PRIV_SECTION_VECTOR_RAM_START]; + bsp_copy_multibyte(src, dst, size); + + /* Copy loader program block on the secondary core (or later) */ + src = (uintptr_t *) image_info[BSP_PRIV_SECTION_LDR_PRG_ROM_ADDRESS]; + dst = (uintptr_t *) image_info[BSP_PRIV_SECTION_LDR_PRG_RAM_START]; + size = (uintptr_t) image_info[BSP_PRIV_SECTION_LDR_PRG_RAM_END] - + (uintptr_t) image_info[BSP_PRIV_SECTION_LDR_PRG_RAM_START]; + bsp_copy_multibyte(src, dst, size); + + /* Copy loader data block on the secondary core (or later) */ + src = (uintptr_t *) image_info[BSP_PRIV_SECTION_LDR_DATA_ROM_ADDRESS]; + dst = (uintptr_t *) image_info[BSP_PRIV_SECTION_LDR_DATA_RAM_START]; + size = (uintptr_t) image_info[BSP_PRIV_SECTION_LDR_DATA_RAM_END] - + (uintptr_t) image_info[BSP_PRIV_SECTION_LDR_DATA_RAM_START]; + bsp_copy_multibyte(src, dst, size); + + /* Copy user program block on the secondary core (or later) */ + src = (uintptr_t *) image_info[BSP_PRIV_SECTION_USER_PRG_ROM_ADDRESS]; + dst = (uintptr_t *) image_info[BSP_PRIV_SECTION_USER_PRG_RAM_START]; + size = (uintptr_t) image_info[BSP_PRIV_SECTION_USER_PRG_RAM_END] - + (uintptr_t) image_info[BSP_PRIV_SECTION_USER_PRG_RAM_START]; + bsp_copy_multibyte(src, dst, size); + + /* Copy user data block on the secondary core (or later) */ + src = (uintptr_t *) image_info[BSP_PRIV_SECTION_USER_DATA_ROM_ADDRESS]; + dst = (uintptr_t *) image_info[BSP_PRIV_SECTION_USER_DATA_RAM_START]; + size = (uintptr_t) image_info[BSP_PRIV_SECTION_USER_DATA_RAM_END] - + (uintptr_t) image_info[BSP_PRIV_SECTION_USER_DATA_RAM_START]; + bsp_copy_multibyte(src, dst, size); + + /* Copy user data_noncache block on the secondary core (or later) */ + src = (uintptr_t *) image_info[BSP_PRIV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS]; + dst = (uintptr_t *) image_info[BSP_PRIV_SECTION_USER_DATA_NONCACHE_RAM_START]; + size = (uintptr_t) image_info[BSP_PRIV_SECTION_USER_DATA_NONCACHE_RAM_END] - + (uintptr_t) image_info[BSP_PRIV_SECTION_USER_DATA_NONCACHE_RAM_START]; + bsp_copy_multibyte(src, dst, size); + + /* Refer to the address information of each section after the secondary core */ + image_info = (uint32_t *) image_info[BSP_PRIV_SECTION_SLAVE_ROM_ADDRESS]; + } + #endif +} + +/*******************************************************************************************************************//** + * Reset release each CPU + **********************************************************************************************************************/ +void bsp_cpu_reset_release (void) +{ + #if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM) + uint32_t * image_info = (uint32_t *) BSP_PRV_SECTION_SLAVE_ROM_ADDRESS; + + /* Determine whether the secondary core (or later) binary exists */ + if ((BSP_PRV_IMAGE_INFO_KEY == image_info[BSP_PRIV_IMAGE_INFO_KEY]) && + (BSP_PRIV_ASSIGNMENT_CPU_CR52_0 <= image_info[BSP_PRIV_IMAGE_INFO_CPU]) && + (BSP_PRIV_ASSIGNMENT_CPU_CR52_1 >= image_info[BSP_PRIV_IMAGE_INFO_CPU])) + { + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET); + + /* Determine whether the secondary core (or later) binary exists */ + while ((BSP_PRV_IMAGE_INFO_KEY == image_info[BSP_PRIV_IMAGE_INFO_KEY]) && + (BSP_PRIV_ASSIGNMENT_CPU_CR52_0 <= image_info[BSP_PRIV_IMAGE_INFO_CPU]) && + (BSP_PRIV_ASSIGNMENT_CPU_CR52_1 >= image_info[BSP_PRIV_IMAGE_INFO_CPU])) + { + switch (image_info[BSP_PRIV_IMAGE_INFO_CPU]) + { + case BSP_PRIV_ASSIGNMENT_CPU_CR52_0: + { + R_BSP_CPUResetRelease(BSP_RESET_CR52_0); + break; + } + + case BSP_PRIV_ASSIGNMENT_CPU_CR52_1: + { + R_BSP_CPUResetRelease(BSP_RESET_CR52_1); + break; + } + + default: + { + break; + } + } + + /* Refer to the address information of each section after the secondary core */ + image_info = (uint32_t *) image_info[BSP_PRIV_IMAGE_INFO_SECTION_ADDRESS]; + image_info = (uint32_t *) image_info[BSP_PRIV_SECTION_SLAVE_ROM_ADDRESS]; + } + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET); + } + #endif +} + + #endif +#endif + +#if (1 == _RZT_ORDINAL) + #if BSP_FEATURE_TFU_SUPPORTED +void bsp_tfu_init (void) +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET); + R_BSP_MODULE_START(FSP_IP_TFU, 0U); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET); +} + + #endif +#endif + +#if !BSP_CFG_PORT_PROTECT +void bsp_release_port_protect (void) +{ + /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ + R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO); + R_RWP_S->PRCRS = ((R_RWP_S->PRCRS | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO); +} + +#endif + +/*******************************************************************************************************************//** + * Initialize static constructors. + **********************************************************************************************************************/ +#if BSP_CFG_C_RUNTIME_INIT +void bsp_static_constructor_init (void) +{ + #if defined(__ICCARM__) + #if !(BSP_CFG_RAM_EXECUTION) + + /* In the case of ROM boot, initialization of static constructors is performed by __iar_data_init3(). */ + __iar_data_init3(); + #endif + #elif defined(__GNUC__) + intptr_t count; + intptr_t i; + + count = __preinit_array_end - __preinit_array_start; + for (i = 0; i < count; i++) + { + __preinit_array_start[i](); + } + + count = __init_array_end - __init_array_start; + for (i = 0; i < count; i++) + { + __init_array_start[i](); + } + #endif +} + +#endif + +/* This vector table is for SGI and PPI interrupts. */ +BSP_DONT_REMOVE fsp_vector_t g_sgi_ppi_vector_table[BSP_CORTEX_VECTOR_TABLE_ENTRIES] = +{ + NULL, /* INTID0 : SOFTWARE_GENERATE_INT0 */ + NULL, /* INTID1 : SOFTWARE_GENERATE_INT1 */ + NULL, /* INTID2 : SOFTWARE_GENERATE_INT2 */ + NULL, /* INTID3 : SOFTWARE_GENERATE_INT3 */ + NULL, /* INTID4 : SOFTWARE_GENERATE_INT4 */ + NULL, /* INTID5 : SOFTWARE_GENERATE_INT5 */ + NULL, /* INTID6 : SOFTWARE_GENERATE_INT6 */ + NULL, /* INTID7 : SOFTWARE_GENERATE_INT7 */ + NULL, /* INTID8 : SOFTWARE_GENERATE_INT8 */ + NULL, /* INTID9 : SOFTWARE_GENERATE_INT9 */ + NULL, /* INTID10 : SOFTWARE_GENERATE_INT10 */ + NULL, /* INTID11 : SOFTWARE_GENERATE_INT11 */ + NULL, /* INTID12 : SOFTWARE_GENERATE_INT12 */ + NULL, /* INTID13 : SOFTWARE_GENERATE_INT13 */ + NULL, /* INTID14 : SOFTWARE_GENERATE_INT14 */ + NULL, /* INTID15 : SOFTWARE_GENERATE_INT15 */ + NULL, /* INTID16 : RESERVED */ + NULL, /* INTID17 : RESERVED */ + NULL, /* INTID18 : RESERVED */ + NULL, /* INTID19 : RESERVED */ + NULL, /* INTID20 : RESERVED */ + NULL, /* INTID21 : RESERVED */ + NULL, /* INTID22 : DEBUG_COMMUNICATIONS_CHANNEL_INT */ + NULL, /* INTID23 : PERFORMANCE_MONITOR_COUNTER_OVERFLOW_INT */ + NULL, /* INTID24 : CROSS_TRIGGER_INTERFACE_INT */ + NULL, /* INTID25 : VIRTUAL_CPU_INTERFACE_MAINTENANCE_INT */ + NULL, /* INTID26 : HYPERVISOR_TIMER_INT */ + NULL, /* INTID27 : VIRTUAL_TIMER_INT */ + NULL, /* INTID28 : RESERVED */ + NULL, /* INTID29 : RESERVED */ + NULL, /* INTID30 : NON-SECURE_PHYSICAL_TIMER_INT */ + NULL, /* INTID31 : RESERVED */ +}; diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_cache.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_cache.c new file mode 100644 index 00000000000..4a42d4ca6c1 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_cache.c @@ -0,0 +1,752 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_PRV_SCTLR_ELX_BIT_I (0x1000U) +#define BSP_PRV_SCTLR_ELX_BIT_C (0x4U) +#define BSP_PRV_SCTLR_ELX_BIT_M (0x1U) + +#define BSP_PRV_CLIDR_CTYPE_OFFSET (3U) +#define BSP_PRV_CLIDR_CTYPE_MASK (7U) +#define BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE (2U) +#define BSP_PRV_CLIDR_LOC_OFFSET (24U) +#define BSP_PRV_CLIDR_LOC_MASK (7U) + +#define BSP_PRV_CCSIDR_LINESIZE_OFFSET (0U) +#define BSP_PRV_CCSIDR_LINESIZE_MASK (7U) +#define BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE (4U) +#define BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET (3U) +#define BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK (0x3FFU) +#define BSP_PRV_CCSIDR_NUMSETS_OFFSET (13U) +#define BSP_PRV_CCSIDR_NUMSETS_MASK (0x7FFFU) +#define BSP_PRV_CCSIDR_SHIFT_MAX (32U) + +#define BSP_PRV_CSSELR_LEVEL_OFFSET (1U) + +#define BSP_PRV_CTR_IMINLINE_OFFSET (0U) +#define BSP_PRV_CTR_IMINLINE_MASK (0xFU) +#define BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS (4U) +#define BSP_PRV_CTR_IMINLINE_ADDRESS_MASK (1U) +#define BSP_PRV_CTR_DMINLINE_OFFSET (16U) +#define BSP_PRV_CTR_DMINLINE_MASK (0xFU) +#define BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS (4U) +#define BSP_PRV_CTR_DMINLINE_ADDRESS_MASK (1U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enable instruction caching. + **********************************************************************************************************************/ +void R_BSP_CacheEnableInst (void) +{ + uintptr_t sctlr; + + sctlr = __get_SCTLR(); + sctlr |= BSP_PRV_SCTLR_ELX_BIT_I; + + __asm volatile ("DSB SY"); + + __set_SCTLR(sctlr); + + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Enable data caching. + **********************************************************************************************************************/ +void R_BSP_CacheEnableData (void) +{ + uintptr_t sctlr; + + sctlr = __get_SCTLR(); + sctlr |= BSP_PRV_SCTLR_ELX_BIT_C; + + __asm volatile ("DSB SY"); + + __set_SCTLR(sctlr); + + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Enable memory protect. + **********************************************************************************************************************/ +void R_BSP_CacheEnableMemoryProtect (void) +{ + uintptr_t sctlr; + + sctlr = __get_SCTLR(); + sctlr |= BSP_PRV_SCTLR_ELX_BIT_M; + + __asm volatile ("DSB SY"); + + __set_SCTLR(sctlr); + + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Disable instruction caching. + **********************************************************************************************************************/ +void R_BSP_CacheDisableInst (void) +{ + uintptr_t sctlr; + + sctlr = __get_SCTLR(); + sctlr &= ~(BSP_PRV_SCTLR_ELX_BIT_I); + + __asm volatile ("DSB SY"); + + __set_SCTLR(sctlr); + + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Disable data caching. + **********************************************************************************************************************/ +void R_BSP_CacheDisableData (void) +{ + uintptr_t sctlr; + + sctlr = __get_SCTLR(); + sctlr &= ~(BSP_PRV_SCTLR_ELX_BIT_C); + + __asm volatile ("DSB SY"); + + __set_SCTLR(sctlr); + + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Disable memory protect. + **********************************************************************************************************************/ +void R_BSP_CacheDisableMemoryProtect (void) +{ + uintptr_t sctlr; + + sctlr = __get_SCTLR(); + sctlr &= ~(BSP_PRV_SCTLR_ELX_BIT_M); + + __asm volatile ("DSB SY"); + + __set_SCTLR(sctlr); + + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Clean data cache by set/way. + * Clean means writing the cache data to memory and clear the dirty bits + * if there is a discrepancy between the cache and memory data. + **********************************************************************************************************************/ +void R_BSP_CacheCleanAll (void) +{ + uintptr_t clidr; + uintptr_t clidr_loc; + uintptr_t clidr_ctype; + uintptr_t clidr_ctype_shift; + + uintptr_t csselr; + uintptr_t csselr_level; + + uintptr_t ccsidr; + uintptr_t ccsidr_linesize; + uintptr_t ccsidr_associativity; + uintptr_t ccsidr_associativity_clz; + uintptr_t ccsidr_associativity_value; + uintptr_t ccsidr_associativity_msb; + uintptr_t ccsidr_numsets; + uintptr_t ccsidr_numsets_total; + + uintptr_t dccsw; + + __asm volatile ("DSB SY"); + + __set_ICIALLU(0); + + __asm volatile ("DMB SY"); + + /* Reads the maximum level of cache implemented */ + clidr = __get_CLIDR(); + clidr_loc = (clidr >> BSP_PRV_CLIDR_LOC_OFFSET) & BSP_PRV_CLIDR_LOC_MASK; + + /* If the cache does not exist, do not process */ + if (0 != clidr_loc) + { + /* Loop until all levels of cache are processed */ + for (csselr = 0; csselr < clidr_loc; csselr++) + { + /* Read the current level cache type */ + clidr_ctype_shift = csselr * BSP_PRV_CLIDR_CTYPE_OFFSET; + clidr_ctype = (clidr >> clidr_ctype_shift) & BSP_PRV_CLIDR_CTYPE_MASK; + + /* If no data cache exists in the current level of cache, do not process */ + if (BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE <= clidr_ctype) + { + /* Set the current level to Cache Size Selection Register */ + csselr_level = csselr << BSP_PRV_CSSELR_LEVEL_OFFSET; + __set_CSSELR(csselr_level); + + __asm volatile ("DSB SY"); + + /* Read the line size, number of ways, and number of sets for the current level of cache */ + ccsidr = __get_CCSIDR(); + ccsidr_linesize = ((ccsidr >> BSP_PRV_CCSIDR_LINESIZE_OFFSET) & BSP_PRV_CCSIDR_LINESIZE_MASK) + + BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE; + ccsidr_associativity = (ccsidr >> BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET) & + BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK; + ccsidr_numsets = (ccsidr >> BSP_PRV_CCSIDR_NUMSETS_OFFSET) & BSP_PRV_CCSIDR_NUMSETS_MASK; + + /* Count consecutive number of 0 starting from the most significant bit (CLZ = Count Leading Zeros) */ + ccsidr_associativity_clz = __CLZ((uint32_t) ccsidr_associativity); + if (BSP_PRV_CCSIDR_SHIFT_MAX == ccsidr_associativity_clz) + { + ccsidr_associativity_clz--; + } + else + { + /* Do Nothing */ + } + + /* Loop until all sets are processed */ + while (1) + { + /* Working copy of number of ways */ + ccsidr_associativity_value = ccsidr_associativity; + + /* Loop until all ways are processed */ + while (1) + { + ccsidr_associativity_msb = (ccsidr_associativity_value << ccsidr_associativity_clz) | + csselr_level; /* Left shift way */ + ccsidr_numsets_total = ccsidr_numsets << ccsidr_linesize; /* Left shift set */ + dccsw = ccsidr_associativity_msb | ccsidr_numsets_total; /* Combine set and way */ + + /* DCCSW - Data or unified Cache line Clean by Set/Way */ + __set_DCCSW(dccsw); + + if (0 != ccsidr_associativity_value) + { + ccsidr_associativity_value--; + } + else + { + break; + } + } + + if (0 != ccsidr_numsets) + { + ccsidr_numsets--; + } + else + { + break; + } + } + } + else + { + /* Do Nothing */ + } + } + + __asm volatile ("DSB SY"); + __asm volatile ("ISB SY"); + } + else + { + /* Do Nothing */ + } +} + +/*******************************************************************************************************************//** + * Invalidate data cache by set/way. + * Also Invalidate instruction cache. + * + * Invalidate means to delete cache data. + **********************************************************************************************************************/ +void R_BSP_CacheInvalidateAll (void) +{ + uintptr_t clidr; + uintptr_t clidr_loc; + uintptr_t clidr_ctype; + uintptr_t clidr_ctype_shift; + + uintptr_t csselr; + uintptr_t csselr_level; + + uintptr_t ccsidr; + uintptr_t ccsidr_linesize; + uintptr_t ccsidr_associativity; + uintptr_t ccsidr_associativity_clz; + uintptr_t ccsidr_associativity_value; + uintptr_t ccsidr_associativity_msb; + uintptr_t ccsidr_numsets; + uintptr_t ccsidr_numsets_total; + + uintptr_t dcisw; + + __asm volatile ("DSB SY"); + + __set_ICIALLU(0); + + __asm volatile ("DMB SY"); + + /* Reads the maximum level of cache implemented */ + clidr = __get_CLIDR(); + clidr_loc = (clidr >> BSP_PRV_CLIDR_LOC_OFFSET) & BSP_PRV_CLIDR_LOC_MASK; + + /* If the cache does not exist, do not process */ + if (0 != clidr_loc) + { + /* Loop until all levels of cache are processed */ + for (csselr = 0; csselr < clidr_loc; csselr++) + { + /* Read the current level cache type */ + clidr_ctype_shift = csselr * BSP_PRV_CLIDR_CTYPE_OFFSET; + clidr_ctype = (clidr >> clidr_ctype_shift) & BSP_PRV_CLIDR_CTYPE_MASK; + + /* If no data cache exists in the current level of cache, do not process */ + if (BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE <= clidr_ctype) + { + /* Set the current level to Cache Size Selection Register */ + csselr_level = csselr << BSP_PRV_CSSELR_LEVEL_OFFSET; + __set_CSSELR(csselr_level); + + __asm volatile ("DSB SY"); + + /* Read the line size, number of ways, and number of sets for the current level of cache */ + ccsidr = __get_CCSIDR(); + ccsidr_linesize = ((ccsidr >> BSP_PRV_CCSIDR_LINESIZE_OFFSET) & BSP_PRV_CCSIDR_LINESIZE_MASK) + + BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE; + ccsidr_associativity = (ccsidr >> BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET) & + BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK; + ccsidr_numsets = (ccsidr >> BSP_PRV_CCSIDR_NUMSETS_OFFSET) & BSP_PRV_CCSIDR_NUMSETS_MASK; + + /* Count consecutive number of 0 starting from the most significant bit (CLZ = Count Leading Zeros) */ + ccsidr_associativity_clz = __CLZ((uint32_t) ccsidr_associativity); + if (BSP_PRV_CCSIDR_SHIFT_MAX == ccsidr_associativity_clz) + { + ccsidr_associativity_clz--; + } + else + { + /* Do Nothing */ + } + + /* Loop until all sets are processed */ + while (1) + { + /* Working copy of number of ways */ + ccsidr_associativity_value = ccsidr_associativity; + + /* Loop until all ways are processed */ + while (1) + { + ccsidr_associativity_msb = (ccsidr_associativity_value << ccsidr_associativity_clz) | + csselr_level; /* Left shift way */ + ccsidr_numsets_total = ccsidr_numsets << ccsidr_linesize; /* Left shift set */ + dcisw = ccsidr_associativity_msb | ccsidr_numsets_total; /* Combine set and way */ + + /* DCISW - Data or unified Cache line Invalidate by Set/Way */ + __set_DCISW(dcisw); + + if (0 != ccsidr_associativity_value) + { + ccsidr_associativity_value--; + } + else + { + break; + } + } + + if (0 != ccsidr_numsets) + { + ccsidr_numsets--; + } + else + { + break; + } + } + } + else + { + /* Do Nothing */ + } + } + + __asm volatile ("DSB SY"); + __asm volatile ("ISB SY"); + } + else + { + /* Do Nothing */ + } +} + +/*******************************************************************************************************************//** + * Clean and Invalidate data cache by set/way. + * Also Invalidate instruction cache. + * + * Clean means writing the cache data to memory and clear the dirty bits + * if there is a discrepancy between the cache and memory data. + * + * Invalidate means to delete cache data. + **********************************************************************************************************************/ +void R_BSP_CacheCleanInvalidateAll (void) +{ + uintptr_t clidr; + uintptr_t clidr_loc; + uintptr_t clidr_ctype; + uintptr_t clidr_ctype_shift; + + uintptr_t csselr; + uintptr_t csselr_level; + + uintptr_t ccsidr; + uintptr_t ccsidr_linesize; + uintptr_t ccsidr_associativity; + uintptr_t ccsidr_associativity_clz; + uintptr_t ccsidr_associativity_value; + uintptr_t ccsidr_associativity_msb; + uintptr_t ccsidr_numsets; + uintptr_t ccsidr_numsets_total; + + uintptr_t dccisw; + + __asm volatile ("DSB SY"); + + __set_ICIALLU(0); + + __asm volatile ("DMB SY"); + + /* Reads the maximum level of cache implemented */ + clidr = __get_CLIDR(); + clidr_loc = (clidr >> BSP_PRV_CLIDR_LOC_OFFSET) & BSP_PRV_CLIDR_LOC_MASK; + + /* If the cache does not exist, do not process */ + if (0 != clidr_loc) + { + /* Loop until all levels of cache are processed */ + for (csselr = 0; csselr < clidr_loc; csselr++) + { + /* Read the current level cache type */ + clidr_ctype_shift = csselr * BSP_PRV_CLIDR_CTYPE_OFFSET; + clidr_ctype = (clidr >> clidr_ctype_shift) & BSP_PRV_CLIDR_CTYPE_MASK; + + /* If no data cache exists in the current level of cache, do not process */ + if (BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE <= clidr_ctype) + { + /* Set the current level to Cache Size Selection Register */ + csselr_level = csselr << BSP_PRV_CSSELR_LEVEL_OFFSET; + __set_CSSELR(csselr_level); + + __asm volatile ("DSB SY"); + + /* Read the line size, number of ways, and number of sets for the current level of cache */ + ccsidr = __get_CCSIDR(); + ccsidr_linesize = ((ccsidr >> BSP_PRV_CCSIDR_LINESIZE_OFFSET) & BSP_PRV_CCSIDR_LINESIZE_MASK) + + BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE; + ccsidr_associativity = (ccsidr >> BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET) & + BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK; + ccsidr_numsets = (ccsidr >> BSP_PRV_CCSIDR_NUMSETS_OFFSET) & BSP_PRV_CCSIDR_NUMSETS_MASK; + + /* Count consecutive number of 0 starting from the most significant bit (CLZ = Count Leading Zeros) */ + ccsidr_associativity_clz = __CLZ((uint32_t) ccsidr_associativity); + if (BSP_PRV_CCSIDR_SHIFT_MAX == ccsidr_associativity_clz) + { + ccsidr_associativity_clz--; + } + else + { + /* Do Nothing */ + } + + /* Loop until all sets are processed */ + while (1) + { + /* Working copy of number of ways */ + ccsidr_associativity_value = ccsidr_associativity; + + /* Loop until all ways are processed */ + while (1) + { + ccsidr_associativity_msb = (ccsidr_associativity_value << ccsidr_associativity_clz) | + csselr_level; /* Left shift way */ + ccsidr_numsets_total = ccsidr_numsets << ccsidr_linesize; /* Left shift set */ + dccisw = ccsidr_associativity_msb | ccsidr_numsets_total; /* Combine set and way */ + + /* DCCISW - Data or unified Cache line Clean and Invalidate by Set/Way */ + __set_DCCISW(dccisw); + + if (0 != ccsidr_associativity_value) + { + ccsidr_associativity_value--; + } + else + { + break; + } + } + + if (0 != ccsidr_numsets) + { + ccsidr_numsets--; + } + else + { + break; + } + } + } + else + { + /* Do Nothing */ + } + } + + __asm volatile ("DSB SY"); + __asm volatile ("ISB SY"); + } + else + { + /* Do Nothing */ + } +} + +/*******************************************************************************************************************//** + * Clean data cache and Invalidate instruction cache by address. + * + * Clean means writing the cache data to memory and clear the dirty bits + * if there is a discrepancy between the cache and memory data. + * + * Invalidate means to delete cache data. + * + * @param[in] base_address Start address of area you want to Clean. + * @param[in] length Size of area you want to Clean. + **********************************************************************************************************************/ +void R_BSP_CacheCleanRange (uintptr_t base_address, uintptr_t length) +{ + uintptr_t end_address; + uintptr_t ctr; + + uintptr_t dminline; + uintptr_t dminline_size; + uintptr_t dccvac; + + uintptr_t iminline; + uintptr_t iminline_size; + uintptr_t icivau; + + end_address = base_address + length; + + /* Calculate data cache line size */ + ctr = __get_CTR(); + dminline = (ctr >> BSP_PRV_CTR_DMINLINE_OFFSET) & BSP_PRV_CTR_DMINLINE_MASK; + dminline_size = (BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS << dminline); + + /* Align base address with cache line */ + dccvac = base_address & ~(dminline_size - BSP_PRV_CTR_DMINLINE_ADDRESS_MASK); + do + { + /* Data or unified Cache line Clean by VA to PoC */ + __set_DCCVAC(dccvac); + + dccvac += dminline_size; /* Next data line */ + } while (end_address > dccvac); + + __asm volatile ("DSB SY"); + + /* Calculate instruction cache line size */ + iminline = (ctr >> BSP_PRV_CTR_IMINLINE_OFFSET) & BSP_PRV_CTR_IMINLINE_MASK; + iminline_size = (BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS << iminline); + + /* Align base address with cache line */ + icivau = base_address & ~(iminline_size - BSP_PRV_CTR_IMINLINE_ADDRESS_MASK); + do + { + /* Instruction Cache line Invalidate by VA to PoU */ + __set_ICIVAU(icivau); + + icivau += iminline_size; /* Next data line */ + } while (end_address == icivau); + + __asm volatile ("DSB SY"); + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Invalidate instruction and data cache by address. + * + * Invalidate means to delete cache data. + * + * @param[in] base_address Start address of area you want to Invalidate. + * @param[in] length Size of area you want to Invalidate. + **********************************************************************************************************************/ +void R_BSP_CacheInvalidateRange (uintptr_t base_address, uintptr_t length) +{ + uintptr_t end_address; + uintptr_t ctr; + + uintptr_t dminline; + uintptr_t dminline_size; + uintptr_t dcivac; + + uintptr_t iminline; + uintptr_t iminline_size; + uintptr_t icivau; + + end_address = base_address + length; + + /* Calculate data cache line size */ + ctr = __get_CTR(); + dminline = (ctr >> BSP_PRV_CTR_DMINLINE_OFFSET) & BSP_PRV_CTR_DMINLINE_MASK; + dminline_size = (BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS << dminline); + + /* Align base address with cache line */ + dcivac = base_address & ~(dminline_size - BSP_PRV_CTR_DMINLINE_ADDRESS_MASK); + do + { + /* Data or unified Cache line Invalidate by VA to PoC */ + __set_DCIVAC(dcivac); + + dcivac += dminline_size; /* Next data line */ + } while (end_address > dcivac); + + __asm volatile ("DSB SY"); + + /* Calculate instruction cache line size */ + iminline = (ctr >> BSP_PRV_CTR_IMINLINE_OFFSET) & BSP_PRV_CTR_IMINLINE_MASK; + iminline_size = (BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS << iminline); + + /* Align base address with cache line */ + icivau = base_address & ~(iminline_size - BSP_PRV_CTR_IMINLINE_ADDRESS_MASK); + do + { + /* Instruction Cache line Invalidate by VA to PoU */ + __set_ICIVAU(icivau); + + icivau += iminline_size; /* Next data line */ + } while (end_address == icivau); + + __asm volatile ("DSB SY"); + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Clean and Invalidate data cache and Invalidate instruction cache by address. + * + * Clean means writing the cache data to memory and clear the dirty bits + * if there is a discrepancy between the cache and memory data. + * + * Invalidate means to delete cache data. + * + * @param[in] base_address Start address of area you want to Clean and Invalidate. + * @param[in] length Size of area you want to Clean and Invalidate. + **********************************************************************************************************************/ +void R_BSP_CacheCleanInvalidateRange (uintptr_t base_address, uintptr_t length) +{ + uintptr_t end_address; + uintptr_t ctr; + + uintptr_t dminline; + uintptr_t dminline_size; + uintptr_t dccivac; + + uintptr_t iminline; + uintptr_t iminline_size; + uintptr_t icivau; + + end_address = base_address + length; + + /* Calculate data cache line size */ + ctr = __get_CTR(); + dminline = (ctr >> BSP_PRV_CTR_DMINLINE_OFFSET) & BSP_PRV_CTR_DMINLINE_MASK; + dminline_size = (BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS << dminline); + + /* Align base address with cache line */ + dccivac = base_address & ~(dminline_size - BSP_PRV_CTR_DMINLINE_ADDRESS_MASK); + do + { + /* Data or unified Cache line Clean and Invalidate by VA to PoC */ + __set_DCCIVAC(dccivac); + + dccivac += dminline_size; /* Next data line */ + } while (end_address > dccivac); + + __asm volatile ("DSB SY"); + + /* Calculate instruction cache line size */ + iminline = (ctr >> BSP_PRV_CTR_IMINLINE_OFFSET) & BSP_PRV_CTR_IMINLINE_MASK; + iminline_size = (BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS << iminline); + + /* Align base address with cache line */ + icivau = base_address & ~(iminline_size - BSP_PRV_CTR_IMINLINE_ADDRESS_MASK); + do + { + /* Instruction Cache line Invalidate by VA to PoU */ + __set_ICIVAU(icivau); + + icivau += iminline_size; /* Next data line */ + } while (end_address == icivau); + + __asm volatile ("DSB SY"); + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Powers on and off the L3 cache way. + * CA55 only. + **********************************************************************************************************************/ +void R_BSP_CacheL3PowerCtrl (void) +{ + r_bsp_cache_l3_power_ctrl(); +} + +/*******************************************************************************************************************//** + * @} (end addtogroup BSP_MCU) + **********************************************************************************************************************/ diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_cache.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_cache.h new file mode 100644 index 00000000000..dd55ecebe98 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_cache.h @@ -0,0 +1,68 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_CACHE_H +#define BSP_CACHE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#if defined(BSP_CFG_CORE_CR52) + #include "cr/bsp_cache_core.h" +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void R_BSP_CacheEnableInst(void); +void R_BSP_CacheEnableData(void); +void R_BSP_CacheEnableMemoryProtect(void); +void R_BSP_CacheDisableInst(void); +void R_BSP_CacheDisableData(void); +void R_BSP_CacheDisableMemoryProtect(void); +void R_BSP_CacheCleanAll(void); +void R_BSP_CacheInvalidateAll(void); +void R_BSP_CacheCleanInvalidateAll(void); +void R_BSP_CacheCleanRange(uintptr_t base_address, uintptr_t length); +void R_BSP_CacheInvalidateRange(uintptr_t base_address, uintptr_t length); +void R_BSP_CacheCleanInvalidateRange(uintptr_t base_address, uintptr_t length); +void R_BSP_CacheL3PowerCtrl(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_clocks.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_clocks.c new file mode 100644 index 00000000000..02b2948e655 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_clocks.c @@ -0,0 +1,458 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_clocks.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_CGC_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x1U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) + +/* Key code for writing PCMD register. */ +#define BSP_PRV_PCMD_KEY (0xA5U) + +/* Calculate the value to write to SCKCR. */ +#define BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS (BSP_CFG_FSELXSPI0_DIVSELXSPI0 & 0x47U) +#define BSP_PRV_STARTUP_SCKCR_FSELXSPI1_DIVSELXSPI1_BITS ((BSP_CFG_FSELXSPI1_DIVSELXSPI1 & 0x47U) << 8U) +#define BSP_PRV_STARTUP_SCKCR_CKIO_BITS ((BSP_CFG_CKIO & 7U) << 16U) +#define BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS ((BSP_CFG_FSELCANFD & 1U) << 20U) +#define BSP_PRV_STARTUP_SCKCR_PHYSEL_BITS ((BSP_CFG_PHYSEL & 1U) << 21U) +#define BSP_PRV_STARTUP_SCKCR_CLMASEL_BITS ((BSP_CFG_CLMASEL & 1U) << 22U) +#define BSP_PRV_STARTUP_SCKCR_SPI0ASYNCSEL_BITS ((BSP_CFG_SPI0ASYNCCLK & 1U) << 24U) +#define BSP_PRV_STARTUP_SCKCR_SPI1ASYNCSEL_BITS ((BSP_CFG_SPI1ASYNCCLK & 1U) << 25U) +#define BSP_PRV_STARTUP_SCKCR_SPI2ASYNCSEL_BITS ((BSP_CFG_SPI2ASYNCCLK & 1U) << 26U) +#define BSP_PRV_STARTUP_SCKCR_SCI0ASYNCSEL_BITS ((BSP_CFG_SCI0ASYNCCLK & 1U) << 27U) +#define BSP_PRV_STARTUP_SCKCR_SCI1ASYNCSEL_BITS ((BSP_CFG_SCI1ASYNCCLK & 1U) << 28U) +#define BSP_PRV_STARTUP_SCKCR_SCI2ASYNCSEL_BITS ((BSP_CFG_SCI2ASYNCCLK & 1U) << 29U) +#define BSP_PRV_STARTUP_SCKCR_SCI3ASYNCSEL_BITS ((BSP_CFG_SCI3ASYNCCLK & 1U) << 30U) +#define BSP_PRV_STARTUP_SCKCR_SCI4ASYNCSEL_BITS ((BSP_CFG_SCI4ASYNCCLK & 1U) << 31U) + +/* Calculate the value to write to SCKCR2. */ +#define BSP_PRV_STARTUP_SCKCR2_FSELCPU0_BITS (BSP_CFG_FSELCPU0 & 3U) +#if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM) + #define BSP_PRV_STARTUP_SCKCR2_FSELCPU1_BITS ((BSP_CFG_FSELCPU1 & 3U) << 2U) +#else + #define BSP_PRV_STARTUP_SCKCR2_FSELCPU1_BITS (0U) +#endif +#define BSP_PRV_STARTUP_SCKCR2_RESERVED_BIT4_BITS (1U << 4U) // The write value should be 1. +#define BSP_PRV_STARTUP_SCKCR2_DIVSELSUB_BITS ((BSP_CFG_DIVSELSUB & 1U) << 5U) +#define BSP_PRV_STARTUP_SCKCR2_SPI3ASYNCSEL_BITS ((BSP_CFG_SPI3ASYNCCLK & 1U) << 24U) +#define BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS ((BSP_CFG_SCI5ASYNCCLK & 1U) << 25U) + +#define BSP_PRV_STARTUP_SCKCR (BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS | \ + BSP_PRV_STARTUP_SCKCR_FSELXSPI1_DIVSELXSPI1_BITS | \ + BSP_PRV_STARTUP_SCKCR_CKIO_BITS | \ + BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS | \ + BSP_PRV_STARTUP_SCKCR_PHYSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_CLMASEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SPI0ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SPI1ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SPI2ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SCI0ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SCI1ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SCI2ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SCI3ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SCI4ASYNCSEL_BITS) + +#define BSP_PRV_STARTUP_SCKCR2 (BSP_PRV_STARTUP_SCKCR2_FSELCPU0_BITS | \ + BSP_PRV_STARTUP_SCKCR2_FSELCPU1_BITS | \ + BSP_PRV_STARTUP_SCKCR2_RESERVED_BIT4_BITS | \ + BSP_PRV_STARTUP_SCKCR2_DIVSELSUB_BITS | \ + BSP_PRV_STARTUP_SCKCR2_SPI3ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS) + +#define BSP_PRV_STARTUP_SCKCR2_FSELCPU0_ICLK_MUL2 (BSP_CLOCKS_FSELCPU0_ICLK_MUL2 << \ + R_SYSC_S_SCKCR2_FSELCPU0_Pos) +#if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM) + #define BSP_PRV_STARTUP_SCKCR2_FSELCPU1_ICLK_MUL2 (BSP_CLOCKS_FSELCPU1_ICLK_MUL2 << \ + R_SYSC_S_SCKCR2_FSELCPU1_Pos) +#endif + +/* Calculate the value to write to HIZCTRLEN. */ +#define BSP_PRV_STARTUP_HIZCTRLEN ((BSP_CFG_CLMA1MASK << 2) | (BSP_CFG_CLMA0MASK << 1) | \ + BSP_CFG_CLMA3MASK) + +/* Frequencies of clocks. */ +#define BSP_PRV_CPU_FREQ_800_MHZ (800000000U) // CPU frequency is 800 MHz +#define BSP_PRV_CPU_FREQ_600_MHZ (600000000U) // CPU frequency is 600 MHz + +/* Command sequence for enabling CLMA. */ +#define BSP_PRV_CTL0_ENABLE_TARGET_CMD (0x01) +#define BSP_PRV_CTL0_ENABLE_REVERSED_CMD (0xFE) + +#define BSP_PRV_LOCO_STABILIZATION_COUNT (40000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +static void bsp_prv_clock_temporaliy_set_system_clock(uint32_t sckcr2); + +#if !BSP_CFG_SOFT_RESET_SUPPORTED +static void bsp_prv_clock_set_hard_reset(void); + +#endif + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Update SystemCoreClock variable based on current clock settings. + **********************************************************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t devselsub = R_SYSC_S->SCKCR2_b.DIVSELSUB; +#if (0 == BSP_CFG_CORE_CR52) + uint32_t fselcpu = R_SYSC_S->SCKCR2_b.FSELCPU0; +#elif (1 == BSP_CFG_CORE_CR52) + uint32_t fselcpu = R_SYSC_S->SCKCR2_b.FSELCPU1; +#endif + + if (0U == devselsub) + { + SystemCoreClock = BSP_PRV_CPU_FREQ_800_MHZ >> fselcpu; + } + else + { + SystemCoreClock = BSP_PRV_CPU_FREQ_600_MHZ >> fselcpu; + } +} + +/*******************************************************************************************************************//** + * Applies system core clock source and divider changes. The MCU is expected to be in high speed mode during this + * configuration and the CGC registers are expected to be unlocked in PRCR. + * + * @param[in] sckcr Value to set in SCKCR register + * @param[in] sckcr2 Value to set in SCKCR2 register + **********************************************************************************************************************/ +void bsp_prv_clock_set (uint32_t sckcr, uint32_t sckcr2) +{ + volatile uint32_t dummy; + sckcr = sckcr & BSP_PRV_SCKCR_MASK; + sckcr2 = sckcr2 & BSP_PRV_SCKCR2_MASK; + + /* Note that if switching CPU clock to 800MHz, switch to 400MHz and then to 800MHz. + * The same applies to changing the clock frequency when the bus reference clock is 150MHz. + * This is the case if FSELCPUn bit of sckcr2 variable is 00b(CPU clock is 800MHz or 600MHz). */ + if (!(BSP_PRV_SCKCR2_FSELCPU0_MASK & sckcr2) || !(BSP_PRV_SCKCR2_FSELCPU1_MASK & sckcr2)) + { + bsp_prv_clock_temporaliy_set_system_clock(sckcr2); + } + + /* Set the system source clock */ + R_SYSC_S->SCKCR2 = sckcr2; + + /** In order to secure processing after clock frequency is changed, + * dummy read the same register at least eight times. + * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */ + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + + R_SYSC_NS->SCKCR = sckcr; + + /** In order to secure processing after clock frequency is changed, + * dummy read the same register at least eight times. + * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */ + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + + FSP_PARAMETER_NOT_USED(dummy); + + /* Clock is now at requested frequency. */ + + /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ + SystemCoreClockUpdate(); +} + +#if !BSP_CFG_SOFT_RESET_SUPPORTED + +static void bsp_prv_clock_set_hard_reset (void) +{ + volatile uint32_t dummy; + uint32_t sckcr = BSP_PRV_STARTUP_SCKCR & BSP_PRV_SCKCR_MASK; + uint32_t sckcr2 = BSP_PRV_STARTUP_SCKCR2 & BSP_PRV_SCKCR2_MASK; + + /* Note that if switching CPU clock to 800MHz, switch to 400MHz and then to 800MHz. + * The same applies to changing the clock frequency when the bus reference clock is 150MHz. + * This is the case if FSELCPUn bit of sckcr2 variable is 00b(CPU clock is 800MHz or 600MHz). */ + if (!(BSP_PRV_SCKCR2_FSELCPU0_MASK & sckcr2) || !(BSP_PRV_SCKCR2_FSELCPU1_MASK & sckcr2)) + { + bsp_prv_clock_temporaliy_set_system_clock(sckcr2); + } + + /* Set the system source clock */ + R_SYSC_S->SCKCR2 = sckcr2; + + /** In order to secure processing after clock frequency is changed, + * dummy read the same register at least eight times. + * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */ + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + + R_SYSC_NS->SCKCR = sckcr; + + /** In order to secure processing after clock frequency is changed, + * dummy read the same register at least eight times. + * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */ + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + + FSP_PARAMETER_NOT_USED(dummy); + + /* Clock is now at requested frequency. */ + + /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ + SystemCoreClockUpdate(); +} + +#endif + +/*******************************************************************************************************************//** + * Initializes system clocks. Makes no assumptions about current register settings. + **********************************************************************************************************************/ +void bsp_clock_init (void) +{ + volatile uint32_t dummy = 0; + + /* Unlock CGC protection registers. */ + R_RWP_NS->PRCRN = (uint16_t) BSP_PRV_PRCR_CGC_UNLOCK; + R_RWP_S->PRCRS = (uint16_t) BSP_PRV_PRCR_CGC_UNLOCK; + + /* The SystemCoreClock needs to be updated before calling R_BSP_SoftwareDelay. */ + SystemCoreClockUpdate(); + + /* Set source clock and dividers. */ +#if BSP_CFG_SOFT_RESET_SUPPORTED + bsp_prv_clock_set(BSP_PRV_STARTUP_SCKCR, BSP_PRV_STARTUP_SCKCR2); +#else + bsp_prv_clock_set_hard_reset(); +#endif + +#if (BSP_CLOCKS_PLL1_INITIAL != BSP_CFG_PLL1) + R_SYSC_S->PLL1EN = BSP_CFG_PLL1; +#endif + +#if (BSP_CLOCKS_LOCO_ENABLE == BSP_CFG_LOCO_ENABLE) + R_SYSC_S->LOCOCR = BSP_CLOCKS_LOCO_ENABLE; + + /* Only start using the LOCO clock after + * the LOCO oscillation stabilization time (tLOCOWT) has elapsed. */ + for (uint16_t i = 0; i < BSP_PRV_LOCO_STABILIZATION_COUNT; i++) + { + __asm volatile ("nop"); + } +#endif + + R_SYSC_S->HIZCTRLEN = BSP_PRV_STARTUP_HIZCTRLEN; + +#if (BSP_CLOCKS_CLMA0_ENABLE == BSP_CFG_CLMA0_ENABLE) + + /* Set the lower and upper limit for comparing frequency domains. */ + R_CLMA0->CMPL = BSP_CFG_CLMA0_CMPL; + R_CLMA0->CMPH = BSP_CFG_CLMA0_CMPH; + + /* Enabling CLMA0 operation. */ + do + { + R_CLMA0->PCMD = BSP_PRV_PCMD_KEY; + + R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD; + R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + + if (1 != R_CLMA0->CTL0) + { + /* Check the value of PROTSR register. */ + dummy = R_CLMA0->PROTSR; + } + } while (1 == R_CLMA0->PROTSR_b.PRERR); +#endif + +#if (BSP_CLOCKS_CLMA1_ENABLE == BSP_CFG_CLMA1_ENABLE) + + /* Set the lower and upper limit for comparing frequency domains. */ + R_CLMA1->CMPL = BSP_CFG_CLMA1_CMPL; + R_CLMA1->CMPH = BSP_CFG_CLMA1_CMPH; + + /* Enabling CLMA1 operation. */ + do + { + R_CLMA1->PCMD = BSP_PRV_PCMD_KEY; + + R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD; + R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + + if (1 != R_CLMA1->CTL0) + { + /* Check the value of PROTSR register. */ + dummy = R_CLMA1->PROTSR; + } + } while (1 == R_CLMA1->PROTSR_b.PRERR); +#endif + +#if (BSP_CLOCKS_CLMA2_ENABLE == BSP_CFG_CLMA2_ENABLE) + + /* Set the lower and upper limit for comparing frequency domains. */ + R_CLMA2->CMPL = BSP_CFG_CLMA2_CMPL; + R_CLMA2->CMPH = BSP_CFG_CLMA2_CMPH; + + /* Enabling CLMA2 operation. */ + do + { + R_CLMA2->PCMD = BSP_PRV_PCMD_KEY; + + R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD; + R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + + if (1 != R_CLMA2->CTL0) + { + /* Check the value of PROTSR register. */ + dummy = R_CLMA2->PROTSR; + } + } while (1 == R_CLMA2->PROTSR_b.PRERR); +#endif + +#if (BSP_CLOCKS_CLMA3_ENABLE == BSP_CFG_CLMA3_ENABLE) + + /* Set the lower and upper limit for comparing frequency domains. */ + R_CLMA3->CMPL = BSP_CFG_CLMA3_CMPL; + R_CLMA3->CMPH = BSP_CFG_CLMA3_CMPH; + + /* Enabling CLMA3 operation. */ + do + { + R_CLMA3->PCMD = BSP_PRV_PCMD_KEY; + + R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD; + R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + + if (1 != R_CLMA3->CTL0) + { + /* Check the value of PROTSR register. */ + dummy = R_CLMA3->PROTSR; + } + } while (1 == R_CLMA3->PROTSR_b.PRERR); +#endif + + /* Lock CGC and LPM protection registers. */ + R_RWP_NS->PRCRN = (uint16_t) BSP_PRV_PRCR_LOCK; + R_RWP_S->PRCRS = (uint16_t) BSP_PRV_PRCR_LOCK; + + FSP_PARAMETER_NOT_USED(dummy); +} + +/*******************************************************************************************************************//** + * Temporarily set system clock. + * Note that if switching CPU clock to 800MHz, switch to 400MHz and then to 800MHz. + * The same applies to changing the clock frequency when the bus reference clock is 150MHz. + * + * @param[in] sckcr2 Value to set in SCKCR2 register + **********************************************************************************************************************/ +void bsp_prv_clock_temporaliy_set_system_clock (uint32_t sckcr2) +{ + volatile uint32_t dummy = 0; + uint32_t sckcr2_cpu_clock = R_SYSC_S->SCKCR2; + + /* Check if FSELCPU0 bit of sckcr2 variable is 00b and CPU0 clock is 800MHz. (Or 600MHz) */ + if (!(BSP_PRV_SCKCR2_FSELCPU0_MASK & sckcr2)) + { + /* Set FSELCPU0 bit to 01b and CPU0 clock is 400MHz. (Or 300MHz) */ + sckcr2_cpu_clock = + ((sckcr2_cpu_clock & ~R_SYSC_S_SCKCR2_FSELCPU0_Msk) | BSP_PRV_STARTUP_SCKCR2_FSELCPU0_ICLK_MUL2); + } + +#if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM) + + /* Check if FSELCPU1 bit of sckcr2 variable is 00b and CPU1 clock is 800MHz. (Or 600MHz) */ + if (!(BSP_PRV_SCKCR2_FSELCPU1_MASK & sckcr2)) + { + /* Set FSELCPU1 bit to 01b and CPU1 clock is 400MHz. (Or 300MHz) */ + sckcr2_cpu_clock = + ((sckcr2_cpu_clock & ~R_SYSC_S_SCKCR2_FSELCPU1_Msk) | BSP_PRV_STARTUP_SCKCR2_FSELCPU1_ICLK_MUL2); + } +#endif + + /* Temporarily set system clock. */ + if (R_SYSC_S->SCKCR2 != sckcr2_cpu_clock) + { + R_SYSC_S->SCKCR2 = sckcr2_cpu_clock; + + /** In order to secure processing after clock frequency is changed, + * dummy read the same register at least eight times. + * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */ + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + } + + FSP_PARAMETER_NOT_USED(dummy); +} + +/** @} (end addtogroup BSP_MCU_PRV) */ diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_clocks.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_clocks.h new file mode 100644 index 00000000000..4b4928389e1 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_clocks.h @@ -0,0 +1,233 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_CLOCKS_H +#define BSP_CLOCKS_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_clock_cfg.h" +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have + * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */ + +/* xSPI unit0 clock options. */ +#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_133_3_MHZ (0x02) // xSPI0 base clock 800MHz and xSPI0 clock 133.3MHz. +#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_100_0_MHZ (0x03) // xSPI0 base clock 800MHz and xSPI0 clock 100.0 MHz. +#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_50_0_MHZ (0x04) // xSPI0 base clock 800MHz and xSPI0 clock 50.0 MHz. +#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_25_0_MHZ (0x05) // xSPI0 base clock 800MHz and xSPI0 clock 25.0 MHz. +#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_12_5_MHZ (0x06) // xSPI0 base clock 800MHz and xSPI0 clock 12.5 MHz. +#define BSP_CLOCKS_XSPI0_CLOCK_DIV1_75_0_MHZ (0x43) // xSPI0 base clock 600MHz and xSPI0 clock 75.0 MHz. +#define BSP_CLOCKS_XSPI0_CLOCK_DIV1_37_5_MHZ (0x44) // xSPI0 base clock 600MHz and xSPI0 clock 37.5 MHz. + +/* xSPI unit1 clock options. */ +#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_133_3_MHZ (0x02) // xSPI1 base clock 800MHz and xSPI1 clock 133.3MHz. +#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_100_0_MHZ (0x03) // xSPI1 base clock 800MHz and xSPI1 clock 100.0 MHz. +#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_50_0_MHZ (0x04) // xSPI1 base clock 800MHz and xSPI1 clock 50.0 MHz. +#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_25_0_MHZ (0x05) // xSPI1 base clock 800MHz and xSPI1 clock 25.0 MHz. +#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_12_5_MHZ (0x06) // xSPI1 base clock 800MHz and xSPI1 clock 12.5 MHz. +#define BSP_CLOCKS_XSPI1_CLOCK_DIV1_75_0_MHZ (0x43) // xSPI1 base clock 600MHz and xSPI1 clock 75.0 MHz. +#define BSP_CLOCKS_XSPI1_CLOCK_DIV1_37_5_MHZ (0x44) // xSPI1 base clock 600MHz and xSPI1 clock 37.5 MHz. + +/* CKIO clock options. */ +#define BSP_CLOCKS_CKIO_ICLK_DIV2 (0) // CKIO clock 100.0 MHz (when SCKCR2.DIVSELSUB = 0), + // or 75.0 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_CKIO_ICLK_DIV3 (1) // CKIO clock 66.7 MHz (when SCKCR2.DIVSELSUB = 0), + // or 50.0 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_CKIO_ICLK_DIV4 (2) // CKIO clock 50.0 MHz (when SCKCR2.DIVSELSUB = 0), + // or 37.5 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_CKIO_ICLK_DIV5 (3) // CKIO clock 40.0 MHz (when SCKCR2.DIVSELSUB = 0), + // or 30.0 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_CKIO_ICLK_DIV6 (4) // CKIO clock 33.3 MHz (when SCKCR2.DIVSELSUB = 0), + // or 25.0 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_CKIO_ICLK_DIV7 (5) // CKIO clock 28.6 MHz (when SCKCR2.DIVSELSUB = 0), + // or 21.4 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_CKIO_ICLK_DIV8 (6) // CKIO clock 25.0 MHz (when SCKCR2.DIVSELSUB = 0), + // or 18.75 MHz (when SCKCR2.DIVSELSUB = 1). + +/* CANFD clock options. */ +#define BSP_CLOCKS_CANFD_CLOCK_80_MHZ (0) // CANFD clock 80 MHz. +#define BSP_CLOCKS_CANFD_CLOCK_40_MHZ (1) // CANFD clock 40 MHz. + +/* Ethernet PHY reference clock (ETHn_REFCLK : n = 0 to 2) options. */ +#define BSP_CLOCKS_PHYSEL_PLL1_DIV (0) // PLL1 devider clock. +#define BSP_CLOCKS_PHYSEL_MAINOSC_DIV (1) // Main clock oscillator. + +/* Alternative clock options when main clock abnormal oscillation is detected in CLMA3. */ +#define BSP_CLOCKS_CLMASEL_LOCO (0) // LOCO clock. +#define BSP_CLOCKS_CLMASEL_PLL (1) // PLL clock. + +/* SPI clock options. */ +#define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI0 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI0 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI1 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI1 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI2 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI2 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI3 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI3 asynchronous serial clock 96.0 MHz. + +/* SCI clock options. */ +#define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI0 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI0 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI1 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI1 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI2 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI2 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI3 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI3 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI4 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI4 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI5 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI5 asynchronous serial clock 96.0 MHz. + +/* CPU0 clock options. */ +#define BSP_CLOCKS_FSELCPU0_ICLK_MUL4 (0) // CPU0 clock 800 MHz (when SCKCR2.DIVSELSUB = 0), + // or 600 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_FSELCPU0_ICLK_MUL2 (1) // CPU0 clock 400 MHz (when SCKCR2.DIVSELSUB = 0), + // or 300 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_FSELCPU0_ICLK_MUL1 (2) // CPU0 clock 200 MHz (when SCKCR2.DIVSELSUB = 0), + // or 150 MHz (when SCKCR2.DIVSELSUB = 1). + +/* CPU1 clock options. */ +#define BSP_CLOCKS_FSELCPU1_ICLK_MUL4 (0) // CPU1 clock 800 MHz (when SCKCR2.DIVSELSUB = 0), + // or 600 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_FSELCPU1_ICLK_MUL2 (1) // CPU1 clock 400 MHz (when SCKCR2.DIVSELSUB = 0), + // or 300 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_FSELCPU1_ICLK_MUL1 (2) // CPU1 clock 200 MHz (when SCKCR2.DIVSELSUB = 0), + // or 150 MHz (when SCKCR2.DIVSELSUB = 1). + +/* Peripheral module base clock options. */ +#define BSP_CLOCKS_DIVSELSUB_0 (0) // ICLK:200MHz, PCLKH:200MHz, PCLKM:100MHz, + // PCLKL:50MHz, PCLKADC:25MHz, PCLKGPTL:400MHz. +#define BSP_CLOCKS_DIVSELSUB_1 (1) // ICLK:150MHz, PCLKH:150MHz, PCLKM:75 MHz, + // PCLKL:37.5MHz, PCLKADC:18.75MHz, PCLKGPTL:300MHz. + +/* LOCO enable options. */ +#define BSP_CLOCKS_LOCO_DISABLE (0) // LOCO Stop +#define BSP_CLOCKS_LOCO_ENABLE (1) // LOCO Run + +/* PLL1 enable options. */ +#define BSP_CLOCKS_PLL1_INITIAL (0xFF) // Initial (This value should not be reflected in the register) +#define BSP_CLOCKS_PLL1_STANDBY (0) // PLL1 is standby state. +#define BSP_CLOCKS_PLL1_NORMAL (1) // PLL1 is normal state. + +/* CLMA error mask options. */ +#define BSP_CLOCKS_CLMA0_ERROR_MASK (0) // CLMA0 error is not transferred to POE3 and POEG. +#define BSP_CLOCKS_CLMA0_ERROR_NOT_MASK (1) // CLMA0 error is transferred to POE3 and POEG. +#define BSP_CLOCKS_CLMA1_ERROR_MASK (0) // CLMA1 error is not transferred to POE3 and POEG. +#define BSP_CLOCKS_CLMA1_ERROR_NOT_MASK (1) // CLMA1 error is transferred to POE3 and POEG. +#define BSP_CLOCKS_CLMA3_ERROR_MASK (0) // CLMA3 error is not transferred to POE3 and POEG. +#define BSP_CLOCKS_CLMA3_ERROR_NOT_MASK (1) // CLMA3 error is transferred to POE3 and POEG. + +/* CLMA enable options. */ +#define BSP_CLOCKS_CLMA0_DISABLE (0) // Disable CLMA0 operation. +#define BSP_CLOCKS_CLMA0_ENABLE (1) // Enable CLMA0 operation. +#define BSP_CLOCKS_CLMA1_DISABLE (0) // Disable CLMA1 operation. +#define BSP_CLOCKS_CLMA1_ENABLE (1) // Enable CLMA1 operation. +#define BSP_CLOCKS_CLMA2_DISABLE (0) // Disable CLMA2 operation. +#define BSP_CLOCKS_CLMA2_ENABLE (1) // Enable CLMA2 operation. +#define BSP_CLOCKS_CLMA3_DISABLE (0) // Disable CLMA3 operation. +#define BSP_CLOCKS_CLMA3_ENABLE (1) // Enable CLMA3 operation. + +/* Create a mask of valid bits in SCKCR. */ +#define BSP_PRV_SCKCR_FSELXSPI0_MASK (7U << 0) +#define BSP_PRV_SCKCR_DIVSELXSPI0_MASK (1U << 6) +#define BSP_PRV_SCKCR_FSELXSPI1_MASK (7U << 8) +#define BSP_PRV_SCKCR_DIVSELXSPI1_MASK (1U << 14) +#define BSP_PRV_SCKCR_CKIO_MASK (7U << 16) +#define BSP_PRV_SCKCR_FSELCANFD_MASK (1U << 20) +#define BSP_PRV_SCKCR_PHYSEL_MASK (1U << 21) +#define BSP_PRV_SCKCR_CLMASEL_MASK (1U << 22) +#define BSP_PRV_SCKCR_SPI0ASYNCSEL_MASK (1U << 24) +#define BSP_PRV_SCKCR_SPI1ASYNCSEL_MASK (1U << 25) +#define BSP_PRV_SCKCR_SPI2ASYNCSEL_MASK (1U << 26) +#define BSP_PRV_SCKCR_SCI0ASYNCSEL_MASK (1U << 27) +#define BSP_PRV_SCKCR_SCI1ASYNCSEL_MASK (1U << 28) +#define BSP_PRV_SCKCR_SCI2ASYNCSEL_MASK (1U << 29) +#define BSP_PRV_SCKCR_SCI3ASYNCSEL_MASK (1U << 30) +#define BSP_PRV_SCKCR_SCI4ASYNCSEL_MASK (1U << 31) +#define BSP_PRV_SCKCR_MASK (((((((((((((((BSP_PRV_SCKCR_FSELXSPI0_MASK | \ + BSP_PRV_SCKCR_DIVSELXSPI0_MASK) | \ + BSP_PRV_SCKCR_FSELXSPI1_MASK) | \ + BSP_PRV_SCKCR_DIVSELXSPI1_MASK) | \ + BSP_PRV_SCKCR_CKIO_MASK) | \ + BSP_PRV_SCKCR_FSELCANFD_MASK) | \ + BSP_PRV_SCKCR_PHYSEL_MASK) | \ + BSP_PRV_SCKCR_CLMASEL_MASK) | \ + BSP_PRV_SCKCR_SPI0ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR_SPI1ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR_SPI2ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR_SCI0ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR_SCI1ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR_SCI2ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR_SCI3ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR_SCI4ASYNCSEL_MASK) +#define BSP_PRV_SCKCR_DIVSELXSPI_MASK (BSP_PRV_SCKCR_DIVSELXSPI0_MASK | \ + BSP_PRV_SCKCR_DIVSELXSPI1_MASK) + +/* Create a mask of valid bits in SCKCR2. */ +#define BSP_PRV_SCKCR2_FSELCPU0_MASK (3U << 0) +#define BSP_PRV_SCKCR2_FSELCPU1_MASK (3U << 2) +#define BSP_PRV_SCKCR2_RESERVED_BIT4_MASK (1U << 4) +#define BSP_PRV_SCKCR2_DIVSELSUB_MASK (1U << 5) +#define BSP_PRV_SCKCR2_SPI3ASYNCSEL_MASK (1U << 24) +#define BSP_PRV_SCKCR2_SCI5ASYNCSEL_MASK (1U << 25) +#define BSP_PRV_SCKCR2_MASK (((((BSP_PRV_SCKCR2_FSELCPU0_MASK | \ + BSP_PRV_SCKCR2_FSELCPU1_MASK) | \ + BSP_PRV_SCKCR2_RESERVED_BIT4_MASK) | \ + BSP_PRV_SCKCR2_DIVSELSUB_MASK) | \ + BSP_PRV_SCKCR2_SPI3ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR2_SCI5ASYNCSEL_MASK) + +#define BSP_PRV_FSELCPU0_INIT (0x02U) +#define BSP_PRV_FSELCPU1_INIT (0x20U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_clock_init(void); // Used internally by BSP + +/* Used internally by CGC */ +void bsp_prv_clock_set(uint32_t sckcr, uint32_t sckcr2); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_common.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_common.c new file mode 100644 index 00000000000..a34a04991e1 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_common.c @@ -0,0 +1,221 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if defined(__ICCARM__) + #define WEAK_ERROR_ATTRIBUTE + #define WEAK_INIT_ATTRIBUTE + #pragma weak fsp_error_log = fsp_error_log_internal + #pragma weak bsp_init = bsp_init_internal +#elif defined(__GNUC__) + + #define WEAK_ERROR_ATTRIBUTE __attribute__((weak, alias("fsp_error_log_internal"))) + + #define WEAK_INIT_ATTRIBUTE __attribute__((weak, alias("bsp_init_internal"))) +#endif + +#define FSP_SECTION_VERSION ".version" + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* System clock frequency information */ +const uint32_t g_bsp_system_clock_select[][2] = +{ + {BSP_PRV_CPU_FREQ_800_MHZ, BSP_PRV_CPU_FREQ_600_MHZ }, // FSP_PRIV_CLOCK_CPU0 + {BSP_PRV_CPU_FREQ_800_MHZ, BSP_PRV_CPU_FREQ_600_MHZ }, // FSP_PRIV_CLOCK_CPU1 + {BSP_PRV_ICLK_FREQ_200_MHZ, BSP_PRV_ICLK_FREQ_150_MHZ }, // FSP_PRIV_CLOCK_ICLK + {BSP_PRV_PCLKH_FREQ_200_MHZ, BSP_PRV_PCLKH_FREQ_150_MHZ }, // FSP_PRIV_CLOCK_PCLKH + {BSP_PRV_PCLKM_FREQ_100_MHZ, BSP_PRV_PCLKM_FREQ_75_MHZ }, // FSP_PRIV_CLOCK_PCLKM + {BSP_PRV_PCLKL_FREQ_50_MHZ, BSP_PRV_PCLKL_FREQ_37_5_MHZ }, // FSP_PRIV_CLOCK_PCLKL + {BSP_PRV_PCLKADC_FREQ_25_MHZ, BSP_PRV_PCLKADC_FREQ_18_75_MHZ}, // FSP_PRIV_CLOCK_PCLKADC + {BSP_PRV_PCLKGPTL_FREQ_400_MHZ, BSP_PRV_PCLKGPTL_FREQ_300_MHZ }, // FSP_PRIV_CLOCK_PCLKGPTL + {BSP_PRV_PCLKSPI_FREQ_75_MHZ, BSP_PRV_PCLKSPI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSPI0 + {BSP_PRV_PCLKSPI_FREQ_75_MHZ, BSP_PRV_PCLKSPI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSPI1 + {BSP_PRV_PCLKSPI_FREQ_75_MHZ, BSP_PRV_PCLKSPI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSPI2 + {BSP_PRV_PCLKSPI_FREQ_75_MHZ, BSP_PRV_PCLKSPI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSPI3 + {BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI0 + {BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI1 + {BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI2 + {BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI3 + {BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI4 + {BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI5 + {BSP_PRV_PCLKCAN_FREQ_80_MHZ, BSP_PRV_PCLKCAN_FREQ_40_MHZ }, // FSP_PRIV_CLOCK_PCLKCAN +}; + +/* System clock frequency information for CKIO */ +const uint32_t g_bsp_system_clock_select_ckio[][2] = +{ + {BSP_PRV_CKIO_FREQ_100_MHZ, BSP_PRV_CKIO_FREQ_75_MHZ }, // CKIO = 000b + {BSP_PRV_CKIO_FREQ_66_7_MHZ, BSP_PRV_CKIO_FREQ_50_MHZ }, // CKIO = 001b + {BSP_PRV_CKIO_FREQ_50_MHZ, BSP_PRV_CKIO_FREQ_37_5_MHZ }, // CKIO = 010b + {BSP_PRV_CKIO_FREQ_40_MHZ, BSP_PRV_CKIO_FREQ_30_MHZ }, // CKIO = 011b + {BSP_PRV_CKIO_FREQ_33_3_MHZ, BSP_PRV_CKIO_FREQ_25_MHZ }, // CKIO = 100b + {BSP_PRV_CKIO_FREQ_28_6_MHZ, BSP_PRV_CKIO_FREQ_21_4_MHZ }, // CKIO = 101b + {BSP_PRV_CKIO_FREQ_25_MHZ, BSP_PRV_CKIO_FREQ_18_75_MHZ }, // CKIO = 110b + {BSP_PRV_CKIO_FREQ_NOT_SUPPORTED, BSP_PRV_CKIO_FREQ_NOT_SUPPORTED}, // CKIO = 111b +}; + +/* System clock frequency information for XSPI_CLK */ +const uint32_t g_bsp_system_clock_select_xspi_clk[][2] = +{ + {BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 000b + {BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 001b + {BSP_PRV_XSPI_CLK_FREQ_133_3_MHZ, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 010b + {BSP_PRV_XSPI_CLK_FREQ_100_MHZ, BSP_PRV_XSPI_CLK_FREQ_75_MHZ }, // FSELXSPIn = 011b + {BSP_PRV_XSPI_CLK_FREQ_50_MHZ, BSP_PRV_XSPI_CLK_FREQ_37_5_MHZ }, // FSELXSPIn = 100b + {BSP_PRV_XSPI_CLK_FREQ_25_MHZ, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 101b + {BSP_PRV_XSPI_CLK_FREQ_12_5_MHZ, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 110b + {BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 111b +}; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/* FSP pack version structure. */ +static BSP_DONT_REMOVE const fsp_pack_version_t g_fsp_version BSP_PLACE_IN_SECTION (FSP_SECTION_VERSION) = +{ + .version_id_b = + { + .minor = FSP_VERSION_MINOR, + .major = FSP_VERSION_MAJOR, + .build = FSP_VERSION_BUILD, + .patch = FSP_VERSION_PATCH + } +}; + +/* Public FSP version name. */ +static BSP_DONT_REMOVE const uint8_t g_fsp_version_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) = + FSP_VERSION_STRING; + +/* Unique FSP version ID. */ +static BSP_DONT_REMOVE const uint8_t g_fsp_version_build_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) = + FSP_VERSION_BUILD_STRING; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/** Prototype of initialization function called before main. This prototype sets the weak association of this + * function to an internal example implementation. If this function is defined in the application code, the + * application code version is used. */ + +void bsp_init(void * p_args) WEAK_INIT_ATTRIBUTE; + +void bsp_init_internal(void * p_args); /// Default initialization function + +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/** Prototype of function called before errors are returned in FSP code if BSP_CFG_ERROR_LOG is set to 1. This + * prototype sets the weak association of this function to an internal example implementation. */ + +void fsp_error_log(fsp_err_t err, const char * file, int32_t line) WEAK_ERROR_ATTRIBUTE; + +void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); /// Default error logger function + +#endif + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Get the FSP version based on compile time macros. + * + * @param[out] p_version Memory address to return version information to. + * + * @retval FSP_SUCCESS Version information stored. + * @retval FSP_ERR_ASSERTION The parameter p_version is NULL. + **********************************************************************************************************************/ +fsp_err_t R_FSP_VersionGet (fsp_pack_version_t * const p_version) +{ +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /** Verify parameters are valid */ + FSP_ASSERT(NULL != p_version); +#endif + + *p_version = g_fsp_version; + + return FSP_SUCCESS; +} + +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/*******************************************************************************************************************//** + * Default error logger function, used only if fsp_error_log is not defined in the user application. + * + * @param[in] err The error code encountered. + * @param[in] file The file name in which the error code was encountered. + * @param[in] line The line number at which the error code was encountered. + **********************************************************************************************************************/ +void fsp_error_log_internal (fsp_err_t err, const char * file, int32_t line) +{ + /** Do nothing. Do not generate any 'unused' warnings. */ + FSP_PARAMETER_NOT_USED(err); + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); +} + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * Default initialization function, used only if bsp_init is not defined in the user application. + **********************************************************************************************************************/ +void bsp_init_internal (void * p_args) +{ + /* Do nothing. */ + FSP_PARAMETER_NOT_USED(p_args); +} + +#if defined(__ARMCC_VERSION) + +/*******************************************************************************************************************//** + * Default implementation of assert for AC6. + **********************************************************************************************************************/ +__attribute__((weak, noreturn)) +void __aeabi_assert (const char * expr, const char * file, int line) { + FSP_PARAMETER_NOT_USED(expr); + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); + __BKPT(0); + while (1) + { + /* Do nothing. */ + } +} + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_common.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_common.h new file mode 100644 index 00000000000..250a0bd9ad3 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_common.h @@ -0,0 +1,446 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_COMMON_H +#define BSP_COMMON_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include +#include + +/* Different compiler support. */ +#include "../../inc/fsp_common_api.h" +#include "bsp_compiler_support.h" +#include "bsp_cfg.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Used to signify that an ELC event is not able to be used as an interrupt. */ +#define BSP_IRQ_DISABLED (0xFFU) + +/* Vector Number offset */ +#define BSP_VECTOR_NUM_OFFSET (32) +#define BSP_INTERRUPT_TYPE_OFFSET (16U) + +#define FSP_CONTEXT_SAVE +#define FSP_CONTEXT_RESTORE + +#define BSP_PRV_CPU_FREQ_800_MHZ (800000000U) // CPU frequency is 800 MHz +#define BSP_PRV_CPU_FREQ_600_MHZ (600000000U) // CPU frequency is 600 MHz + +#define BSP_PRV_ICLK_FREQ_200_MHZ (200000000U) // ICLK frequency is 200 MHz +#define BSP_PRV_ICLK_FREQ_150_MHZ (150000000U) // ICLK frequency is 150 MHz + +#define BSP_PRV_PCLKH_FREQ_200_MHZ (200000000U) // PCLKH frequency is 200 MHz +#define BSP_PRV_PCLKH_FREQ_150_MHZ (150000000U) // PCLKH frequency is 150 MHz + +#define BSP_PRV_PCLKM_FREQ_100_MHZ (100000000U) // PCLKM frequency is 100 MHz +#define BSP_PRV_PCLKM_FREQ_75_MHZ (75000000U) // PCLKM frequency is 750 MHz + +#define BSP_PRV_PCLKL_FREQ_50_MHZ (50000000U) // PCLKL frequency is 50 MHz +#define BSP_PRV_PCLKL_FREQ_37_5_MHZ (37500000U) // PCLKL frequency is 37.5 MHz + +#define BSP_PRV_PCLKADC_FREQ_25_MHZ (25000000U) // PCLKADC frequency is 25 MHz +#define BSP_PRV_PCLKADC_FREQ_18_75_MHZ (18750000U) // PCLKADC frequency is 18.75 MHz + +#define BSP_PRV_PCLKGPTL_FREQ_400_MHZ (400000000U) // PCLKGPTL frequency is 400 MHz +#define BSP_PRV_PCLKGPTL_FREQ_300_MHZ (300000000U) // PCLKGPTL frequency is 300 MHz + +#define BSP_PRV_PCLKSCI_FREQ_75_MHZ (75000000U) // PCLKSCI frequency is 75 MHz +#define BSP_PRV_PCLKSCI_FREQ_96_MHZ (96000000U) // PCLKSCI frequency is 96 MHz + +#define BSP_PRV_PCLKSPI_FREQ_75_MHZ (75000000U) // PCLKSPI frequency is 75 MHz +#define BSP_PRV_PCLKSPI_FREQ_96_MHZ (96000000U) // PCLKSPI frequency is 96 MHz + +#define BSP_PRV_PCLKCAN_FREQ_80_MHZ (80000000U) // PCLKCAN frequency is 80 MHz +#define BSP_PRV_PCLKCAN_FREQ_40_MHZ (40000000U) // PCLKCAN frequency is 40 MHz + +#define BSP_PRV_CKIO_FREQ_100_MHZ (100000000U) // CKIO frequency is 100 MHz +#define BSP_PRV_CKIO_FREQ_75_MHZ (75000000U) // CKIO frequency is 75 MHz +#define BSP_PRV_CKIO_FREQ_66_7_MHZ (66666666U) // CKIO frequency is 66.7 MHz +#define BSP_PRV_CKIO_FREQ_50_MHZ (50000000U) // CKIO frequency is 50 MHz +#define BSP_PRV_CKIO_FREQ_40_MHZ (40000000U) // CKIO frequency is 40 MHz +#define BSP_PRV_CKIO_FREQ_37_5_MHZ (37500000U) // CKIO frequency is 37.5 MHz +#define BSP_PRV_CKIO_FREQ_33_3_MHZ (33333333U) // CKIO frequency is 33.3MHz +#define BSP_PRV_CKIO_FREQ_30_MHZ (30000000U) // CKIO frequency is 30 MHz +#define BSP_PRV_CKIO_FREQ_28_6_MHZ (28571428U) // CKIO frequency is 28.6 MHz +#define BSP_PRV_CKIO_FREQ_25_MHZ (25000000U) // CKIO frequency is 25 MHz +#define BSP_PRV_CKIO_FREQ_21_4_MHZ (21428571U) // CKIO frequency is 21.4 MHz +#define BSP_PRV_CKIO_FREQ_18_75_MHZ (18750000U) // CKIO frequency is 18.75 MHz +#define BSP_PRV_CKIO_FREQ_NOT_SUPPORTED (0xFFFFFFFFU) // CKIO frequency is not supported + +#define BSP_PRV_XSPI_CLK_FREQ_133_3_MHZ (133333333U) // XSPI_CLK frequency is 133.3 MHz +#define BSP_PRV_XSPI_CLK_FREQ_100_MHZ (100000000U) // XSPI_CLK frequency is 100.0 MHz +#define BSP_PRV_XSPI_CLK_FREQ_75_MHZ (75000000U) // XSPI_CLK frequency is 75.0 MHz +#define BSP_PRV_XSPI_CLK_FREQ_50_MHZ (50000000U) // XSPI_CLK frequency is 50.0 MHz +#define BSP_PRV_XSPI_CLK_FREQ_37_5_MHZ (37500000U) // XSPI_CLK frequency is 37.5 MHz +#define BSP_PRV_XSPI_CLK_FREQ_25_MHZ (25000000U) // XSPI_CLK frequency is 25.0 MHz +#define BSP_PRV_XSPI_CLK_FREQ_12_5_MHZ (12500000U) // XSPI_CLK frequency is 12.5 MHz +#define BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED (0xFFFFFFFFU) // XSPI_CLK frequency is not supported + +/** Macro to log and return error without an assertion. */ +#ifndef FSP_RETURN + + #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \ + return err; +#endif + +/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in + * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/ +#if (1 == BSP_CFG_ERROR_LOG) + + #ifndef FSP_ERROR_LOG + #define FSP_ERROR_LOG(err) \ + fsp_error_log((err), __FILE__, __LINE__); + #endif +#else + + #define FSP_ERROR_LOG(err) +#endif + +/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP + * functions. */ +#if (3 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) +#elif (2 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) {assert(a);} +#else + #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION) +#endif // ifndef FSP_ASSERT + +/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used + * to identify runtime errors in FSP functions. */ + +#define FSP_ERROR_RETURN(a, err) \ + { \ + if ((a)) \ + { \ + (void) 0; /* Do nothing */ \ + } \ + else \ + { \ + FSP_ERROR_LOG(err); \ + return err; \ + } \ + } + +/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates. + * This macro can be redefined to add a timeout if necessary. */ +#ifndef FSP_HARDWARE_REGISTER_WAIT + #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} +#endif + +/* Function-like macro used to wait for a condition to be met with timeout, + * most often used to wait for hardware register updates. */ +#define BSP_HARDWARE_REGISTER_WAIT_WTIH_TIMEOUT(reg, required_value, timeout) \ + while ((timeout)) \ + { \ + if ((required_value) == (reg)) \ + { \ + break; \ + } \ + (timeout)--; \ + } + +#ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) +#endif + +/* This macro defines a variable for saving previous mask value */ +#ifndef FSP_CRITICAL_SECTION_DEFINE + + #define FSP_CRITICAL_SECTION_DEFINE uintptr_t old_mask_level = 0U +#endif + +/* These macros abstract methods to save and restore the interrupt state. */ +#define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_ICC_PMR +#define FSP_CRITICAL_SECTION_SET_STATE __set_ICC_PMR +#define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \ + BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT)) + +/** This macro temporarily saves the current interrupt state and disables interrupts. */ +#ifndef FSP_CRITICAL_SECTION_ENTER + #define FSP_CRITICAL_SECTION_ENTER \ + old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \ + FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET) +#endif + +/** This macro restores the previously saved interrupt state, reenabling interrupts. */ +#ifndef FSP_CRITICAL_SECTION_EXIT + #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level) +#endif + +/* Number of Cortex processor exceptions. */ +#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (32U) + +/** Used to signify that the requested IRQ vector is not defined in this system. */ +#define FSP_INVALID_VECTOR ((IRQn_Type) - 33) + +/* This macro Enable or Disable interrupts. */ +#define BSP_INTERRUPT_ENABLE __asm volatile ("cpsie i"); \ + __asm volatile ("isb"); + +#define BSP_INTERRUPT_DISABLE __asm volatile ("cpsid i"); \ + __asm volatile ("isb"); + +/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will + * alert the user of the error. The user can override this default behavior by defining their own + * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro. + */ +#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR) + + #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x)) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Different warm start entry locations in the BSP. */ +typedef enum e_bsp_warm_start_event +{ + BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs. + BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs. + BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up +} bsp_warm_start_event_t; + +/* Private enum used in R_FSP_SystemClockHzGet. */ +typedef enum e_fsp_priv_clock +{ + FSP_PRIV_CLOCK_CPU0 = 0, + FSP_PRIV_CLOCK_CPU1 = 1, + FSP_PRIV_CLOCK_ICLK = 2, + FSP_PRIV_CLOCK_PCLKH = 3, + FSP_PRIV_CLOCK_PCLKM = 4, + FSP_PRIV_CLOCK_PCLKL = 5, + FSP_PRIV_CLOCK_PCLKADC = 6, + FSP_PRIV_CLOCK_PCLKGPTL = 7, + FSP_PRIV_CLOCK_PCLKSPI0 = 8, + FSP_PRIV_CLOCK_PCLKSPI1 = 9, + FSP_PRIV_CLOCK_PCLKSPI2 = 10, + FSP_PRIV_CLOCK_PCLKSPI3 = 11, + FSP_PRIV_CLOCK_PCLKSCI0 = 12, + FSP_PRIV_CLOCK_PCLKSCI1 = 13, + FSP_PRIV_CLOCK_PCLKSCI2 = 14, + FSP_PRIV_CLOCK_PCLKSCI3 = 15, + FSP_PRIV_CLOCK_PCLKSCI4 = 16, + FSP_PRIV_CLOCK_PCLKSCI5 = 17, + FSP_PRIV_CLOCK_PCLKCAN = 18, + FSP_PRIV_CLOCK_CKIO = 19, + FSP_PRIV_CLOCK_XSPI0_CLK = 20, + FSP_PRIV_CLOCK_XSPI1_CLK = 21, +} fsp_priv_clock_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +extern const uint32_t g_bsp_system_clock_select[][2]; +extern const uint32_t g_bsp_system_clock_select_ckio[][2]; +extern const uint32_t g_bsp_system_clock_select_xspi_clk[][2]; + +extern IRQn_Type g_current_interrupt_num[]; +extern uint8_t g_current_interrupt_pointer; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Return active interrupt vector number value + * + * @return Active interrupt vector number value + **********************************************************************************************************************/ +__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void) +{ + /* Return the current interrupt number. */ + return g_current_interrupt_num[(g_current_interrupt_pointer - 1U)]; +} + +/*******************************************************************************************************************//** + * Gets the frequency of a system clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) +{ + uint32_t clock_hz = 0; + uint32_t fselcpu0 = R_SYSC_S->SCKCR2_b.FSELCPU0; +#if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM) + uint32_t fselcpu1 = R_SYSC_S->SCKCR2_b.FSELCPU1; +#endif + switch (clock) + { + case FSP_PRIV_CLOCK_CPU0: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_S->SCKCR2_b.DIVSELSUB] >> fselcpu0; + break; + } + + case FSP_PRIV_CLOCK_CPU1: + { +#if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM) + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_S->SCKCR2_b.DIVSELSUB] >> fselcpu1; +#endif + break; + } + + /* These iclk and pclk cases are intentionally combined. */ + case FSP_PRIV_CLOCK_ICLK: + case FSP_PRIV_CLOCK_PCLKH: + case FSP_PRIV_CLOCK_PCLKM: + case FSP_PRIV_CLOCK_PCLKL: + case FSP_PRIV_CLOCK_PCLKADC: + case FSP_PRIV_CLOCK_PCLKGPTL: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_S->SCKCR2_b.DIVSELSUB]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSPI0: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SPI0ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSPI1: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SPI1ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSPI2: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SPI2ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSPI3: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_S->SCKCR2_b.SPI3ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSCI0: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SCI0ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSCI1: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SCI1ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSCI2: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SCI2ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSCI3: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SCI3ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSCI4: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SCI4ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSCI5: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_S->SCKCR2_b.SCI5ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKCAN: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.FSELCANFD]; + break; + } + + case FSP_PRIV_CLOCK_CKIO: + { + uint32_t ckio = R_SYSC_NS->SCKCR_b.CKIO; + clock_hz = g_bsp_system_clock_select_ckio[ckio][R_SYSC_S->SCKCR2_b.DIVSELSUB]; + break; + } + + case FSP_PRIV_CLOCK_XSPI0_CLK: + { + uint32_t fselxspi0 = R_SYSC_NS->SCKCR_b.FSELXSPI0; + clock_hz = g_bsp_system_clock_select_xspi_clk[fselxspi0][R_SYSC_NS->SCKCR_b.DIVSELXSPI0]; + break; + } + + case FSP_PRIV_CLOCK_XSPI1_CLK: + { + uint32_t fselxspi1 = R_SYSC_NS->SCKCR_b.FSELXSPI1; + clock_hz = g_bsp_system_clock_select_xspi_clk[fselxspi1][R_SYSC_NS->SCKCR_b.DIVSELXSPI1]; + break; + } + + default: + { + break; + } + } + + return clock_hz; +} + +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */ +void fsp_error_log(fsp_err_t err, const char * file, int32_t line); + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_compiler_support.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_compiler_support.h new file mode 100644 index 00000000000..d593dee9d60 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_compiler_support.h @@ -0,0 +1,110 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_COMPILER_SUPPORT_H +#define BSP_COMPILER_SUPPORT_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + #include +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) /* AC6 compiler */ + +/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load + * memory (ROM) is reserved unnecessarily. */ + #define BSP_UNINIT_SECTION_PREFIX ".bss" + #define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap" + #define BSP_DONT_REMOVE + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) + #define BSP_TARGET_ARM #pragma arm +#elif defined(__GNUC__) /* GCC compiler */ + #define BSP_UNINIT_SECTION_PREFIX + #define BSP_SECTION_HEAP ".heap" + #define BSP_DONT_REMOVE + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) + #define BSP_TARGET_ARM __attribute__((target("arm"))) +#elif defined(__ICCARM__) /* IAR compiler */ + #define BSP_UNINIT_SECTION_PREFIX + #define BSP_SECTION_HEAP "HEAP" + #define BSP_DONT_REMOVE __root + #define BSP_ATTRIBUTE_STACKLESS __stackless + #define BSP_FORCE_INLINE _Pragma("inline=forced") + #define BSP_TARGET_ARM __arm +#endif + +#define BSP_SECTION_FIQ_STACK BSP_UNINIT_SECTION_PREFIX ".fiq_stack" +#define BSP_SECTION_IRQ_STACK BSP_UNINIT_SECTION_PREFIX ".irq_stack" +#define BSP_SECTION_ABT_STACK BSP_UNINIT_SECTION_PREFIX ".abt_stack" +#define BSP_SECTION_UND_STACK BSP_UNINIT_SECTION_PREFIX ".und_stack" +#define BSP_SECTION_SYS_STACK BSP_UNINIT_SECTION_PREFIX ".sys_stack" +#define BSP_SECTION_SVC_STACK BSP_UNINIT_SECTION_PREFIX ".svc_stack" +#define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit" +#define BSP_SECTION_FIXED_VECTORS ".fixed_vectors" +#define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" +#define BSP_SECTION_ROM_REGISTERS ".rom_registers" +#define BSP_SECTION_ID_CODE ".id_code" +#define BSP_SECTION_LOADER_PARAM ".loader_param" + +/* Compiler neutral macros. */ +#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) + +#define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x))) + +#define BSP_PACKED __attribute__((aligned(1))) + +#define BSP_WEAK_REFERENCE __attribute__((weak)) + +/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */ +#define BSP_STACK_ALIGNMENT (8) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end of addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_delay.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_delay.c new file mode 100644 index 00000000000..1bf5382b0cf --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_delay.c @@ -0,0 +1,159 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "bsp_delay.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_DELAY_NS_PER_SECOND (1000000000) +#define BSP_DELAY_NS_PER_US (1000) +#define BSP_DELAY_SIGNIFICANT_DIGITS (10000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Delay for at least the specified duration in units and return. + * @param[in] delay The number of 'units' to delay. + * @param[in] units The 'base' (bsp_delay_units_t) for the units specified. Valid values are: + * BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS.@n + * For example:@n + * At 200 MHz one cycle takes 1/200 microsecond or 5 nanoseconds.@n + * At 800 MHz one cycle takes 1/800 microsecond or 1.25 nanoseconds.@n + * Therefore one run through bsp_prv_software_delay_loop() takes: + * ~ (1.25 * BSP_DELAY_LOOP_CYCLES) or 5 ns. + * A delay of 2 us therefore requires 2000ns/5ns or 400 loops. + * + * The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the system clock rate. + * @200MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 200000000) = 85 seconds. + * @800MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 800000000) = 21 seconds. + * + * Note that requests for very large delays will be affected by rounding in the calculations and the actual delay + * achieved may be slightly longer. @200 MHz, for example, a request for 85 seconds will be closer to 86 seconds. + * + * Note also that if the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() function is not called + * at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the + * overhead associated with executing the code to just get to this point has certainly satisfied the requested delay. + * + * + * @note R_BSP_SoftwareDelay() obtains the system clock value by reading the SystemCoreClock variable. + * Therefore, R_BSP_SoftwareDelay() cannot be used until after the SystemCoreClock has been updated. + * The SystemCoreClock is updated by executing SystemCoreClockUpdate() in startup; + * users cannot call R_BSP_SoftwareDelay() inside R_BSP_WarmStart(BSP_WARM_START_RESET) and + * R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK) since they are invoked before SystemCoreClockUpdate() in startup. + * + * @note This function will delay for **at least** the specified duration. Due to overhead in calculating the correct number + * of loops to delay, very small delay values (generally 1-5 microseconds) may be significantly longer than specified. + * Approximate overhead for this function is as follows: + * - CR52: 94-117 cycles + * + * @note If more accurate microsecond timing must be performed in software it is recommended to use + * bsp_prv_software_delay_loop() directly. In this case, use BSP_DELAY_LOOP_CYCLES or BSP_DELAY_LOOPS_CALCULATE() + * to convert a calculated delay cycle count to a number of software delay loops. + * + * @note Delays may be longer than expected when compiler optimization is turned off. + **********************************************************************************************************************/ + +void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units) +{ + uint32_t cpu_hz; + uint32_t cycles_requested; + uint32_t ns_per_cycle; + uint32_t loops_required = 0; + uint32_t total_us = (delay * units); /** Convert the requested time to microseconds. */ + uint64_t ns_64bits; + + cpu_hz = SystemCoreClock; /** Get the system clock frequency in Hz. */ + + /* BSP_DELAY_SIGNIFICANT_DIGITS to keep the decimal point. */ + ns_per_cycle = BSP_DELAY_NS_PER_SECOND / (cpu_hz / BSP_DELAY_SIGNIFICANT_DIGITS); /** Get the # of nanoseconds/cycle. */ + + /* We want to get the time in total nanoseconds but need to be conscious of overflowing 32 bits. We also do not want to do 64 bit */ + /* division as that pulls in a division library. */ + ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns. + + /* Have we overflowed 32 bits? */ + if (ns_64bits <= UINT32_MAX) + { + ns_64bits = ns_64bits * (uint64_t) BSP_DELAY_SIGNIFICANT_DIGITS; + + /* No, we will not overflow. + * Multiply the calculation result by BSP_DELAY_SIGNIFICANT_DIGITS to disable the retention of the decimal point.*/ + cycles_requested = (uint32_t) (ns_64bits / (uint64_t) ns_per_cycle); + loops_required = cycles_requested / BSP_DELAY_LOOP_CYCLES; + } + else + { + /* We did overflow. Try dividing down first. + * Multiply the calculation result by BSP_DELAY_SIGNIFICANT_DIGITS to disable the retention of the decimal point.*/ + total_us = (total_us / (ns_per_cycle * BSP_DELAY_LOOP_CYCLES)) * BSP_DELAY_SIGNIFICANT_DIGITS; + ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns. + + /* Have we overflowed 32 bits? */ + if (ns_64bits <= UINT32_MAX) + { + /* No, we will not overflow. */ + loops_required = (uint32_t) ns_64bits; + } + else + { + /* We still overflowed, use the max count for cycles */ + loops_required = UINT32_MAX; + } + } + + /** Only delay if the supplied parameters constitute a delay. */ + if (loops_required > (uint32_t) 0) + { + bsp_prv_software_delay_loop(loops_required); + } +} + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * This assembly language routine takes roughly 4 cycles per loop. 2 additional cycles + * occur when the loop exits. The 'naked' attribute indicates that the specified function does not need + * prologue/epilogue sequences generated by the compiler. + * @param[in] loop_cnt The number of loops to iterate. + **********************************************************************************************************************/ +void bsp_prv_software_delay_loop (uint32_t loop_cnt) +{ + r_bsp_software_delay_loop(loop_cnt); +} diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_delay.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_delay.h new file mode 100644 index 00000000000..82e69ab1188 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_delay.h @@ -0,0 +1,72 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_DELAY_H +#define BSP_DELAY_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#if defined(BSP_CFG_CORE_CR52) + #include "cr/bsp_delay_core.h" +#endif + +#include "bsp_compiler_support.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */ +typedef enum +{ + BSP_DELAY_UNITS_SECONDS = 1000000, ///< Requested delay amount is in seconds + BSP_DELAY_UNITS_MILLISECONDS = 1000, ///< Requested delay amount is in milliseconds + BSP_DELAY_UNITS_MICROSECONDS = 1 ///< Requested delay amount is in microseconds +} bsp_delay_units_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void bsp_prv_software_delay_loop(uint32_t loop_cnt); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_exceptions.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_exceptions.h new file mode 100644 index 00000000000..37b0468ac00 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_exceptions.h @@ -0,0 +1,50 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_EXCEPTIONS_H +#define BSP_EXCEPTIONS_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_io.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_io.c new file mode 100644 index 00000000000..4cf8a6285a6 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_io.c @@ -0,0 +1,41 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +volatile uint32_t g_protect_port_counter; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_io.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_io.h new file mode 100644 index 00000000000..0da51954ec8 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_io.h @@ -0,0 +1,544 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @defgroup BSP_IO BSP I/O access + * @ingroup RENESAS_COMMON + * @brief This module provides basic read/write/toggle access to port pins and read/write access to port. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_IO_H +#define BSP_IO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Private definition to set enumeration values. */ +#define BSP_IO_PRV_8BIT_MASK (0xFF) +#define BSP_IO_PM_OUTPUT (3U) + +/* Key code for writing PRCR register. */ +#define BSP_IO_PRV_PRCR_KEY (0xA500U) +#define BSP_IO_REG_PROTECT_GPIO (0x0004U) + +/* Difference between safety and non safety I/O port region addresses. */ +#define BSP_IO_REGION_ADDRESS_DIFF (R_PORT_SR_BASE - R_PORT_NSR_BASE) + +/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */ +#define BSP_IO_PRV_PORT_OFFSET (8U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Levels that can be set and read for individual pins */ +typedef enum e_bsp_io_level +{ + BSP_IO_LEVEL_LOW = 0, ///< Low + BSP_IO_LEVEL_HIGH ///< High +} bsp_io_level_t; + +/** Direction of individual pins */ +typedef enum e_bsp_io_dir +{ + BSP_IO_DIRECTION_INPUT = 0, ///< Input + BSP_IO_DIRECTION_OUTPUT ///< Output +} bsp_io_direction_t; + +/** Superset list of all possible IO ports. */ +typedef enum e_bsp_io_port +{ + BSP_IO_PORT_00 = 0x0000, ///< IO port 0 + BSP_IO_PORT_01 = 0x0100, ///< IO port 1 + BSP_IO_PORT_02 = 0x0200, ///< IO port 2 + BSP_IO_PORT_03 = 0x0300, ///< IO port 3 + BSP_IO_PORT_04 = 0x0400, ///< IO port 4 + BSP_IO_PORT_05 = 0x0500, ///< IO port 5 + BSP_IO_PORT_06 = 0x0600, ///< IO port 6 + BSP_IO_PORT_07 = 0x0700, ///< IO port 7 + BSP_IO_PORT_08 = 0x0800, ///< IO port 8 + BSP_IO_PORT_09 = 0x0900, ///< IO port 9 + BSP_IO_PORT_10 = 0x0A00, ///< IO port 10 + BSP_IO_PORT_11 = 0x0B00, ///< IO port 11 + BSP_IO_PORT_12 = 0x0C00, ///< IO port 12 + BSP_IO_PORT_13 = 0x0D00, ///< IO port 13 + BSP_IO_PORT_14 = 0x0E00, ///< IO port 14 + BSP_IO_PORT_15 = 0x0F00, ///< IO port 15 + BSP_IO_PORT_16 = 0x1000, ///< IO port 16 + BSP_IO_PORT_17 = 0x1100, ///< IO port 17 + BSP_IO_PORT_18 = 0x1200, ///< IO port 18 + BSP_IO_PORT_19 = 0x1300, ///< IO port 19 + BSP_IO_PORT_20 = 0x1400, ///< IO port 20 + BSP_IO_PORT_21 = 0x1500, ///< IO port 21 + BSP_IO_PORT_22 = 0x1600, ///< IO port 22 + BSP_IO_PORT_23 = 0x1700, ///< IO port 23 + BSP_IO_PORT_24 = 0x1800, ///< IO port 24 +} bsp_io_port_t; + +/** Superset list of all possible IO port pins. */ +typedef enum e_bsp_io_port_pin +{ + BSP_IO_PORT_00_PIN_0 = 0x0000, ///< IO port 0 pin 0 + BSP_IO_PORT_00_PIN_1 = 0x0001, ///< IO port 0 pin 1 + BSP_IO_PORT_00_PIN_2 = 0x0002, ///< IO port 0 pin 2 + BSP_IO_PORT_00_PIN_3 = 0x0003, ///< IO port 0 pin 3 + BSP_IO_PORT_00_PIN_4 = 0x0004, ///< IO port 0 pin 4 + BSP_IO_PORT_00_PIN_5 = 0x0005, ///< IO port 0 pin 5 + BSP_IO_PORT_00_PIN_6 = 0x0006, ///< IO port 0 pin 6 + BSP_IO_PORT_00_PIN_7 = 0x0007, ///< IO port 0 pin 7 + + BSP_IO_PORT_01_PIN_0 = 0x0100, ///< IO port 1 pin 0 + BSP_IO_PORT_01_PIN_1 = 0x0101, ///< IO port 1 pin 1 + BSP_IO_PORT_01_PIN_2 = 0x0102, ///< IO port 1 pin 2 + BSP_IO_PORT_01_PIN_3 = 0x0103, ///< IO port 1 pin 3 + BSP_IO_PORT_01_PIN_4 = 0x0104, ///< IO port 1 pin 4 + BSP_IO_PORT_01_PIN_5 = 0x0105, ///< IO port 1 pin 5 + BSP_IO_PORT_01_PIN_6 = 0x0106, ///< IO port 1 pin 6 + BSP_IO_PORT_01_PIN_7 = 0x0107, ///< IO port 1 pin 7 + + BSP_IO_PORT_02_PIN_0 = 0x0200, ///< IO port 2 pin 0 + BSP_IO_PORT_02_PIN_1 = 0x0201, ///< IO port 2 pin 1 + BSP_IO_PORT_02_PIN_2 = 0x0202, ///< IO port 2 pin 2 + BSP_IO_PORT_02_PIN_3 = 0x0203, ///< IO port 2 pin 3 + BSP_IO_PORT_02_PIN_4 = 0x0204, ///< IO port 2 pin 4 + BSP_IO_PORT_02_PIN_5 = 0x0205, ///< IO port 2 pin 5 + BSP_IO_PORT_02_PIN_6 = 0x0206, ///< IO port 2 pin 6 + BSP_IO_PORT_02_PIN_7 = 0x0207, ///< IO port 2 pin 7 + + BSP_IO_PORT_03_PIN_0 = 0x0300, ///< IO port 3 pin 0 + BSP_IO_PORT_03_PIN_1 = 0x0301, ///< IO port 3 pin 1 + BSP_IO_PORT_03_PIN_2 = 0x0302, ///< IO port 3 pin 2 + BSP_IO_PORT_03_PIN_3 = 0x0303, ///< IO port 3 pin 3 + BSP_IO_PORT_03_PIN_4 = 0x0304, ///< IO port 3 pin 4 + BSP_IO_PORT_03_PIN_5 = 0x0305, ///< IO port 3 pin 5 + BSP_IO_PORT_03_PIN_6 = 0x0306, ///< IO port 3 pin 6 + BSP_IO_PORT_03_PIN_7 = 0x0307, ///< IO port 3 pin 7 + + BSP_IO_PORT_04_PIN_0 = 0x0400, ///< IO port 4 pin 0 + BSP_IO_PORT_04_PIN_1 = 0x0401, ///< IO port 4 pin 1 + BSP_IO_PORT_04_PIN_2 = 0x0402, ///< IO port 4 pin 2 + BSP_IO_PORT_04_PIN_3 = 0x0403, ///< IO port 4 pin 3 + BSP_IO_PORT_04_PIN_4 = 0x0404, ///< IO port 4 pin 4 + BSP_IO_PORT_04_PIN_5 = 0x0405, ///< IO port 4 pin 5 + BSP_IO_PORT_04_PIN_6 = 0x0406, ///< IO port 4 pin 6 + BSP_IO_PORT_04_PIN_7 = 0x0407, ///< IO port 4 pin 7 + + BSP_IO_PORT_05_PIN_0 = 0x0500, ///< IO port 5 pin 0 + BSP_IO_PORT_05_PIN_1 = 0x0501, ///< IO port 5 pin 1 + BSP_IO_PORT_05_PIN_2 = 0x0502, ///< IO port 5 pin 2 + BSP_IO_PORT_05_PIN_3 = 0x0503, ///< IO port 5 pin 3 + BSP_IO_PORT_05_PIN_4 = 0x0504, ///< IO port 5 pin 4 + BSP_IO_PORT_05_PIN_5 = 0x0505, ///< IO port 5 pin 5 + BSP_IO_PORT_05_PIN_6 = 0x0506, ///< IO port 5 pin 6 + BSP_IO_PORT_05_PIN_7 = 0x0507, ///< IO port 5 pin 7 + + BSP_IO_PORT_06_PIN_0 = 0x0600, ///< IO port 6 pin 0 + BSP_IO_PORT_06_PIN_1 = 0x0601, ///< IO port 6 pin 1 + BSP_IO_PORT_06_PIN_2 = 0x0602, ///< IO port 6 pin 2 + BSP_IO_PORT_06_PIN_3 = 0x0603, ///< IO port 6 pin 3 + BSP_IO_PORT_06_PIN_4 = 0x0604, ///< IO port 6 pin 4 + BSP_IO_PORT_06_PIN_5 = 0x0605, ///< IO port 6 pin 5 + BSP_IO_PORT_06_PIN_6 = 0x0606, ///< IO port 6 pin 6 + BSP_IO_PORT_06_PIN_7 = 0x0607, ///< IO port 6 pin 7 + + BSP_IO_PORT_07_PIN_0 = 0x0700, ///< IO port 7 pin 0 + BSP_IO_PORT_07_PIN_1 = 0x0701, ///< IO port 7 pin 1 + BSP_IO_PORT_07_PIN_2 = 0x0702, ///< IO port 7 pin 2 + BSP_IO_PORT_07_PIN_3 = 0x0703, ///< IO port 7 pin 3 + BSP_IO_PORT_07_PIN_4 = 0x0704, ///< IO port 7 pin 4 + BSP_IO_PORT_07_PIN_5 = 0x0705, ///< IO port 7 pin 5 + BSP_IO_PORT_07_PIN_6 = 0x0706, ///< IO port 7 pin 6 + BSP_IO_PORT_07_PIN_7 = 0x0707, ///< IO port 7 pin 7 + + BSP_IO_PORT_08_PIN_0 = 0x0800, ///< IO port 8 pin 0 + BSP_IO_PORT_08_PIN_1 = 0x0801, ///< IO port 8 pin 1 + BSP_IO_PORT_08_PIN_2 = 0x0802, ///< IO port 8 pin 2 + BSP_IO_PORT_08_PIN_3 = 0x0803, ///< IO port 8 pin 3 + BSP_IO_PORT_08_PIN_4 = 0x0804, ///< IO port 8 pin 4 + BSP_IO_PORT_08_PIN_5 = 0x0805, ///< IO port 8 pin 5 + BSP_IO_PORT_08_PIN_6 = 0x0806, ///< IO port 8 pin 6 + BSP_IO_PORT_08_PIN_7 = 0x0807, ///< IO port 8 pin 7 + + BSP_IO_PORT_09_PIN_0 = 0x0900, ///< IO port 9 pin 0 + BSP_IO_PORT_09_PIN_1 = 0x0901, ///< IO port 9 pin 1 + BSP_IO_PORT_09_PIN_2 = 0x0902, ///< IO port 9 pin 2 + BSP_IO_PORT_09_PIN_3 = 0x0903, ///< IO port 9 pin 3 + BSP_IO_PORT_09_PIN_4 = 0x0904, ///< IO port 9 pin 4 + BSP_IO_PORT_09_PIN_5 = 0x0905, ///< IO port 9 pin 5 + BSP_IO_PORT_09_PIN_6 = 0x0906, ///< IO port 9 pin 6 + BSP_IO_PORT_09_PIN_7 = 0x0907, ///< IO port 9 pin 7 + + BSP_IO_PORT_10_PIN_0 = 0x0A00, ///< IO port 10 pin 0 + BSP_IO_PORT_10_PIN_1 = 0x0A01, ///< IO port 10 pin 1 + BSP_IO_PORT_10_PIN_2 = 0x0A02, ///< IO port 10 pin 2 + BSP_IO_PORT_10_PIN_3 = 0x0A03, ///< IO port 10 pin 3 + BSP_IO_PORT_10_PIN_4 = 0x0A04, ///< IO port 10 pin 4 + BSP_IO_PORT_10_PIN_5 = 0x0A05, ///< IO port 10 pin 5 + BSP_IO_PORT_10_PIN_6 = 0x0A06, ///< IO port 10 pin 6 + BSP_IO_PORT_10_PIN_7 = 0x0A07, ///< IO port 10 pin 7 + + BSP_IO_PORT_11_PIN_0 = 0x0B00, ///< IO port 11 pin 0 + BSP_IO_PORT_11_PIN_1 = 0x0B01, ///< IO port 11 pin 1 + BSP_IO_PORT_11_PIN_2 = 0x0B02, ///< IO port 11 pin 2 + BSP_IO_PORT_11_PIN_3 = 0x0B03, ///< IO port 11 pin 3 + BSP_IO_PORT_11_PIN_4 = 0x0B04, ///< IO port 11 pin 4 + BSP_IO_PORT_11_PIN_5 = 0x0B05, ///< IO port 11 pin 5 + BSP_IO_PORT_11_PIN_6 = 0x0B06, ///< IO port 11 pin 6 + BSP_IO_PORT_11_PIN_7 = 0x0B07, ///< IO port 11 pin 7 + + BSP_IO_PORT_12_PIN_0 = 0x0C00, ///< IO port 12 pin 0 + BSP_IO_PORT_12_PIN_1 = 0x0C01, ///< IO port 12 pin 1 + BSP_IO_PORT_12_PIN_2 = 0x0C02, ///< IO port 12 pin 2 + BSP_IO_PORT_12_PIN_3 = 0x0C03, ///< IO port 12 pin 3 + BSP_IO_PORT_12_PIN_4 = 0x0C04, ///< IO port 12 pin 4 + BSP_IO_PORT_12_PIN_5 = 0x0C05, ///< IO port 12 pin 5 + BSP_IO_PORT_12_PIN_6 = 0x0C06, ///< IO port 12 pin 6 + BSP_IO_PORT_12_PIN_7 = 0x0C07, ///< IO port 12 pin 7 + + BSP_IO_PORT_13_PIN_0 = 0x0D00, ///< IO port 13 pin 0 + BSP_IO_PORT_13_PIN_1 = 0x0D01, ///< IO port 13 pin 1 + BSP_IO_PORT_13_PIN_2 = 0x0D02, ///< IO port 13 pin 2 + BSP_IO_PORT_13_PIN_3 = 0x0D03, ///< IO port 13 pin 3 + BSP_IO_PORT_13_PIN_4 = 0x0D04, ///< IO port 13 pin 4 + BSP_IO_PORT_13_PIN_5 = 0x0D05, ///< IO port 13 pin 5 + BSP_IO_PORT_13_PIN_6 = 0x0D06, ///< IO port 13 pin 6 + BSP_IO_PORT_13_PIN_7 = 0x0D07, ///< IO port 13 pin 7 + + BSP_IO_PORT_14_PIN_0 = 0x0E00, ///< IO port 14 pin 0 + BSP_IO_PORT_14_PIN_1 = 0x0E01, ///< IO port 14 pin 1 + BSP_IO_PORT_14_PIN_2 = 0x0E02, ///< IO port 14 pin 2 + BSP_IO_PORT_14_PIN_3 = 0x0E03, ///< IO port 14 pin 3 + BSP_IO_PORT_14_PIN_4 = 0x0E04, ///< IO port 14 pin 4 + BSP_IO_PORT_14_PIN_5 = 0x0E05, ///< IO port 14 pin 5 + BSP_IO_PORT_14_PIN_6 = 0x0E06, ///< IO port 14 pin 6 + BSP_IO_PORT_14_PIN_7 = 0x0E07, ///< IO port 14 pin 7 + + BSP_IO_PORT_15_PIN_0 = 0x0F00, ///< IO port 15 pin 0 + BSP_IO_PORT_15_PIN_1 = 0x0F01, ///< IO port 15 pin 1 + BSP_IO_PORT_15_PIN_2 = 0x0F02, ///< IO port 15 pin 2 + BSP_IO_PORT_15_PIN_3 = 0x0F03, ///< IO port 15 pin 3 + BSP_IO_PORT_15_PIN_4 = 0x0F04, ///< IO port 15 pin 4 + BSP_IO_PORT_15_PIN_5 = 0x0F05, ///< IO port 15 pin 5 + BSP_IO_PORT_15_PIN_6 = 0x0F06, ///< IO port 15 pin 6 + BSP_IO_PORT_15_PIN_7 = 0x0F07, ///< IO port 15 pin 7 + + BSP_IO_PORT_16_PIN_0 = 0x1000, ///< IO port 16 pin 0 + BSP_IO_PORT_16_PIN_1 = 0x1001, ///< IO port 16 pin 1 + BSP_IO_PORT_16_PIN_2 = 0x1002, ///< IO port 16 pin 2 + BSP_IO_PORT_16_PIN_3 = 0x1003, ///< IO port 16 pin 3 + BSP_IO_PORT_16_PIN_4 = 0x1004, ///< IO port 16 pin 4 + BSP_IO_PORT_16_PIN_5 = 0x1005, ///< IO port 16 pin 5 + BSP_IO_PORT_16_PIN_6 = 0x1006, ///< IO port 16 pin 6 + BSP_IO_PORT_16_PIN_7 = 0x1007, ///< IO port 16 pin 7 + + BSP_IO_PORT_17_PIN_0 = 0x1100, ///< IO port 17 pin 0 + BSP_IO_PORT_17_PIN_1 = 0x1101, ///< IO port 17 pin 1 + BSP_IO_PORT_17_PIN_2 = 0x1102, ///< IO port 17 pin 2 + BSP_IO_PORT_17_PIN_3 = 0x1103, ///< IO port 17 pin 3 + BSP_IO_PORT_17_PIN_4 = 0x1104, ///< IO port 17 pin 4 + BSP_IO_PORT_17_PIN_5 = 0x1105, ///< IO port 17 pin 5 + BSP_IO_PORT_17_PIN_6 = 0x1106, ///< IO port 17 pin 6 + BSP_IO_PORT_17_PIN_7 = 0x1107, ///< IO port 17 pin 7 + + BSP_IO_PORT_18_PIN_0 = 0x1200, ///< IO port 18 pin 0 + BSP_IO_PORT_18_PIN_1 = 0x1201, ///< IO port 18 pin 1 + BSP_IO_PORT_18_PIN_2 = 0x1202, ///< IO port 18 pin 2 + BSP_IO_PORT_18_PIN_3 = 0x1203, ///< IO port 18 pin 3 + BSP_IO_PORT_18_PIN_4 = 0x1204, ///< IO port 18 pin 4 + BSP_IO_PORT_18_PIN_5 = 0x1205, ///< IO port 18 pin 5 + BSP_IO_PORT_18_PIN_6 = 0x1206, ///< IO port 18 pin 6 + BSP_IO_PORT_18_PIN_7 = 0x1207, ///< IO port 18 pin 7 + + BSP_IO_PORT_19_PIN_0 = 0x1300, ///< IO port 19 pin 0 + BSP_IO_PORT_19_PIN_1 = 0x1301, ///< IO port 19 pin 1 + BSP_IO_PORT_19_PIN_2 = 0x1302, ///< IO port 19 pin 2 + BSP_IO_PORT_19_PIN_3 = 0x1303, ///< IO port 19 pin 3 + BSP_IO_PORT_19_PIN_4 = 0x1304, ///< IO port 19 pin 4 + BSP_IO_PORT_19_PIN_5 = 0x1305, ///< IO port 19 pin 5 + BSP_IO_PORT_19_PIN_6 = 0x1306, ///< IO port 19 pin 6 + BSP_IO_PORT_19_PIN_7 = 0x1307, ///< IO port 19 pin 7 + + BSP_IO_PORT_20_PIN_0 = 0x1400, ///< IO port 20 pin 0 + BSP_IO_PORT_20_PIN_1 = 0x1401, ///< IO port 20 pin 1 + BSP_IO_PORT_20_PIN_2 = 0x1402, ///< IO port 20 pin 2 + BSP_IO_PORT_20_PIN_3 = 0x1403, ///< IO port 20 pin 3 + BSP_IO_PORT_20_PIN_4 = 0x1404, ///< IO port 20 pin 4 + BSP_IO_PORT_20_PIN_5 = 0x1405, ///< IO port 20 pin 5 + BSP_IO_PORT_20_PIN_6 = 0x1406, ///< IO port 20 pin 6 + BSP_IO_PORT_20_PIN_7 = 0x1407, ///< IO port 20 pin 7 + + BSP_IO_PORT_21_PIN_0 = 0x1500, ///< IO port 21 pin 0 + BSP_IO_PORT_21_PIN_1 = 0x1501, ///< IO port 21 pin 1 + BSP_IO_PORT_21_PIN_2 = 0x1502, ///< IO port 21 pin 2 + BSP_IO_PORT_21_PIN_3 = 0x1503, ///< IO port 21 pin 3 + BSP_IO_PORT_21_PIN_4 = 0x1504, ///< IO port 21 pin 4 + BSP_IO_PORT_21_PIN_5 = 0x1505, ///< IO port 21 pin 5 + BSP_IO_PORT_21_PIN_6 = 0x1506, ///< IO port 21 pin 6 + BSP_IO_PORT_21_PIN_7 = 0x1507, ///< IO port 21 pin 7 + + BSP_IO_PORT_22_PIN_0 = 0x1600, ///< IO port 22 pin 0 + BSP_IO_PORT_22_PIN_1 = 0x1601, ///< IO port 22 pin 1 + BSP_IO_PORT_22_PIN_2 = 0x1602, ///< IO port 22 pin 2 + BSP_IO_PORT_22_PIN_3 = 0x1603, ///< IO port 22 pin 3 + BSP_IO_PORT_22_PIN_4 = 0x1604, ///< IO port 22 pin 4 + BSP_IO_PORT_22_PIN_5 = 0x1605, ///< IO port 22 pin 5 + BSP_IO_PORT_22_PIN_6 = 0x1606, ///< IO port 22 pin 6 + BSP_IO_PORT_22_PIN_7 = 0x1607, ///< IO port 22 pin 7 + + BSP_IO_PORT_23_PIN_0 = 0x1700, ///< IO port 23 pin 0 + BSP_IO_PORT_23_PIN_1 = 0x1701, ///< IO port 23 pin 1 + BSP_IO_PORT_23_PIN_2 = 0x1702, ///< IO port 23 pin 2 + BSP_IO_PORT_23_PIN_3 = 0x1703, ///< IO port 23 pin 3 + BSP_IO_PORT_23_PIN_4 = 0x1704, ///< IO port 23 pin 4 + BSP_IO_PORT_23_PIN_5 = 0x1705, ///< IO port 23 pin 5 + BSP_IO_PORT_23_PIN_6 = 0x1706, ///< IO port 23 pin 6 + BSP_IO_PORT_23_PIN_7 = 0x1707, ///< IO port 23 pin 7 + + BSP_IO_PORT_24_PIN_0 = 0x1800, ///< IO port 24 pin 0 + BSP_IO_PORT_24_PIN_1 = 0x1801, ///< IO port 24 pin 1 + BSP_IO_PORT_24_PIN_2 = 0x1802, ///< IO port 24 pin 2 + BSP_IO_PORT_24_PIN_3 = 0x1803, ///< IO port 24 pin 3 + BSP_IO_PORT_24_PIN_4 = 0x1804, ///< IO port 24 pin 4 + BSP_IO_PORT_24_PIN_5 = 0x1805, ///< IO port 24 pin 5 + BSP_IO_PORT_24_PIN_6 = 0x1806, ///< IO port 24 pin 6 + BSP_IO_PORT_24_PIN_7 = 0x1807, ///< IO port 24 pin 7 +} bsp_io_port_pin_t; + +/** Offset for pin safety region access */ +typedef enum e_bsp_io_region +{ + BSP_IO_REGION_NOT_SAFE = 0, ///< Non safety region + BSP_IO_REGION_SAFE = BSP_IO_REGION_ADDRESS_DIFF, ///< Safety region +} bsp_io_region_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern volatile uint32_t g_protect_port_counter; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Set the output level of the pin in the specified region. + * + * @param[in] region The target IO region + * @param[in] pin The pin + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinSet (bsp_io_region_t region, bsp_io_port_pin_t pin) +{ + /* Casting to a uint8_t type is valid because only the lower 8 bits of pin(uint16_t) are extracted by masking on + * the right side. */ + ((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->P[pin >> + BSP_IO_PRV_PORT_OFFSET] |= + (uint8_t) (1UL << (pin & BSP_IO_PRV_8BIT_MASK)); +} + +/*******************************************************************************************************************//** + * Clear the output level of the pin in the specified region. + * + * @param[in] region The target IO region + * @param[in] pin The pin + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinClear (bsp_io_region_t region, bsp_io_port_pin_t pin) +{ + /* Casting to a uint8_t type is valid because only the lower 8 bits of pin(uint16_t) are extracted by masking on + * the right side. */ + ((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->P[pin >> BSP_IO_PRV_PORT_OFFSET] &= + (uint8_t) (~(1UL << (pin & BSP_IO_PRV_8BIT_MASK))); +} + +/*******************************************************************************************************************//** + * Toggle the output level of the pin in the specified region. + * + * @param[in] region The target IO region + * @param[in] pin The pin + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinToggle (bsp_io_region_t region, bsp_io_port_pin_t pin) +{ + /* Casting to a uint8_t type is valid because only the lower 8 bits of pin(uint16_t) are extracted by masking on + * the right side. */ + ((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->P[pin >> + BSP_IO_PRV_PORT_OFFSET] ^= + (uint8_t) (1UL << (pin & BSP_IO_PRV_8BIT_MASK)); +} + +/*******************************************************************************************************************//** + * Read the input level of the pin in the specified region. + * + * @param[in] region The target IO region + * @param[in] pin The pin + * + * @retval Current input level + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_FastPinRead (bsp_io_region_t region, bsp_io_port_pin_t pin) +{ + return (uint32_t) ((((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->PIN[pin >> BSP_IO_PRV_PORT_OFFSET]) >> + (pin & BSP_IO_PRV_8BIT_MASK)) & 0x00000001UL; +} + +/*******************************************************************************************************************//** + * Set the output value of the port in the specified region. All pins in the port must be set to the same IO region to + * use this function. + * + * @param[in] region The target IO region + * @param[in] port The port + * @param[in] set_value The setting value + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PortWrite (bsp_io_region_t region, bsp_io_port_t port, uint8_t set_value) +{ + ((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->P[port >> BSP_IO_PRV_PORT_OFFSET] = set_value; +} + +/*******************************************************************************************************************//** + * Read the input value of the port in the specified region. All pins in the port must be set to the same IO region to + * use this function. + * + * @param[in] region The target IO region + * @param[in] port The port + * + * @retval Current input value + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_PortRead (bsp_io_region_t region, bsp_io_port_t port) +{ + return (uint32_t) (((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->PIN[port >> BSP_IO_PRV_PORT_OFFSET]); +} + +/*******************************************************************************************************************//** + * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur + * via multiple threads or an ISR re-entering this code. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessEnable (void) +{ +#if BSP_CFG_PORT_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /** If this is first entry then allow writing of PFS. */ + if (0 == g_protect_port_counter) + { + /** Disable protection using PRCR register. */ + + /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ + R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO); + R_RWP_S->PRCRS = ((R_RWP_S->PRCRS | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO); + } + + /** Increment the protect counter */ + g_protect_port_counter++; + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +#endif +} + +/*******************************************************************************************************************//** + * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via + * multiple threads or an ISR re-entering this code. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessDisable (void) +{ +#if BSP_CFG_PORT_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /** Is it safe to disable PFS register? */ + if (0 != g_protect_port_counter) + { + /* Decrement the protect counter */ + g_protect_port_counter--; + } + + /** Is it safe to disable writing of PFS? */ + if (0 == g_protect_port_counter) + { + /** Enable protection using PRCR register. */ + + /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ + R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_IO_PRV_PRCR_KEY) & (uint16_t) (~BSP_IO_REG_PROTECT_GPIO)); + R_RWP_S->PRCRS = ((R_RWP_S->PRCRS | BSP_IO_PRV_PRCR_KEY) & (uint16_t) (~BSP_IO_REG_PROTECT_GPIO)); + } + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +#endif +} + +/*******************************************************************************************************************//** + * Read IO region of the pin. + * + * @param[in] pin The pin + * + * @retval BSP_IO_REGION_SAFE IO region of the pin is safety + * @retval BSP_IO_REGION_NOT_SAFE IO region of the pin is non-safety + * + * This function can be given as an argument to pin/port access functions described below. When used in a function + * starting with R_BSP_Port, any one pin in the port should be given as an argument to this function. + * R_BSP_PinSet(), R_BSP_PinClear(), R_BSP_PinToggle(), R_BSP_FastPinRead(), R_BSP_PortWrite(), R_BSP_PortRead() + * + * @note This function can be used to get the region of a specified pin, but the overhead should be considered if this + * function is executed each time the pin is accessed. When accessing the same pin repeatedly, it is recommended + * that the value obtained by this function be held in a variable beforehand, and the value of the variable be + * used as the region argument of the pin access function. + **********************************************************************************************************************/ +__STATIC_INLINE bsp_io_region_t R_BSP_IoRegionGet (bsp_io_port_pin_t pin) +{ + /* Casting to a uint32_t type is valid because the range of values represented by uint32_t is not over in the + * calculation process of the right-hand side. */ + uint32_t aselp = + ((uint32_t) ((R_PTADR->RSELP[pin >> BSP_IO_PRV_PORT_OFFSET]) >> (pin & BSP_IO_PRV_8BIT_MASK)) & 0x00000001UL); + + if (0U == aselp) + { + return BSP_IO_REGION_SAFE; + } + else + { + return BSP_IO_REGION_NOT_SAFE; + } +} + +/** @} (end addtogroup BSP_IO) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_irq.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_irq.c new file mode 100644 index 00000000000..3fe92cc3e2d --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_irq.c @@ -0,0 +1,50 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initialize interrupt controller. + * + * @retval None + **********************************************************************************************************************/ +void bsp_irq_cfg (void) +{ + bsp_irq_core_cfg(); +} diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_irq.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_irq.h new file mode 100644 index 00000000000..f8fa8e2d021 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_irq.h @@ -0,0 +1,236 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_IRQ_H +#define BSP_IRQ_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#if defined(BSP_CFG_CORE_CR52) + #include "cr/bsp_irq_core.h" +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Sets the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @param[in] p_context ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + r_fsp_irq_context_set(irq, p_context); +} + +/*******************************************************************************************************************//** + * Clear the GIC pending interrupt. + * + * @param[in] irq Interrupt for which to clear the Pending bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq) +{ + r_bsp_irq_clear_pending(irq); +} + +/*******************************************************************************************************************//** + * Get the GIC pending interrupt. + * + * @param[in] irq Interrupt that gets a pending bit.. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @return Value indicating the status of the level interrupt. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_IrqPendingGet (IRQn_Type irq) +{ + return r_bsp_irq_pending_get(irq); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context. + * + * @param[in] irq The IRQ number to configure. + * @param[in] priority GIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + r_bsp_irq_cfg(irq, priority); + + /* Store the context. The context is recovered in the ISR. */ + R_FSP_IsrContextSet(irq, p_context); +} + +/*******************************************************************************************************************//** + * Enable the IRQ in the GIC (Without clearing the pending bit). + * + * @param[in] irq The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the + * Cortex Processor Exceptions Numbers. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq) +{ + r_bsp_irq_enable_no_clear(irq); +} + +/*******************************************************************************************************************//** + * Enable the IRQ in the GIC (With clearing the pending bit). + * + * @param[in] irq The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the + * Cortex Processor Exceptions Numbers. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq) +{ + /* Clear pending interrupts in the GIC. */ + R_BSP_IrqClearPending(irq); + + /* Enable the interrupt in the GIC. */ + R_BSP_IrqEnableNoClear(irq); +} + +/*******************************************************************************************************************//** + * Disables interrupts in the GIC. + * + * @param[in] irq The IRQ number to disable in the GIC. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq) +{ + r_bsp_irq_disable(irq); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt. + * + * @param[in] irq Interrupt number. + * @param[in] priority GIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + R_BSP_IrqCfg(irq, priority, p_context); + R_BSP_IrqEnable(irq); +} + +/*******************************************************************************************************************//** + * @brief Finds the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @return ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + return gp_renesas_isr_context[irq + BSP_VECTOR_NUM_OFFSET]; +} + +/*******************************************************************************************************************//** + * Sets the interrupt detect type. + * + * @param[in] irq The IRQ number to configure. + * @param[in] detect_type GIC detect type of the interrupt (0 : active-HIGH level, 1 : rising edge-triggerd). + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqDetectTypeSet (IRQn_Type const irq, uint32_t detect_type) +{ + r_bsp_irq_detect_type_set(irq, detect_type); +} + +/*******************************************************************************************************************//** + * Sets the interrupt Group. + * + * @param[in] irq The IRQ number to configure. + * @param[in] interrupt_group GIC interrupt group number ( 0 : FIQ, 1 : IRQ ). + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqGroupSet (IRQn_Type const irq, uint32_t interrupt_group) +{ + r_bsp_irq_group_set(irq, interrupt_group); +} + +/*******************************************************************************************************************//** + * Sets the interrupt mask level. + * + * @param[in] mask_level The interrupt mask level + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqMaskLevelSet (uint32_t mask_level) +{ + FSP_CRITICAL_SECTION_SET_STATE(mask_level << BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT); +} + +/*******************************************************************************************************************//** + * Gets the interrupt mask level. + * + * @return Value indicating the interrupt mask level. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_IrqMaskLevelGet (void) +{ + return (uint32_t) ((FSP_CRITICAL_SECTION_GET_CURRENT_STATE() >> BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT) & + 0x0000001FUL); +} + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_irq_cfg(void); // Used internally by BSP + +/** @} (end addtogroup BSP_MCU_PRV) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_mcu_api.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_mcu_api.h new file mode 100644 index 00000000000..12eab87147f --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_mcu_api.h @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_MCU_API_H +#define BSP_MCU_API_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct st_bsp_event_info +{ + IRQn_Type irq; + elc_event_t event; +} bsp_event_info_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); +void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); +void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); +void R_BSP_SystemReset(void); +void R_BSP_CPUReset(bsp_reset_t cpu); +void R_BSP_CPUResetRelease(bsp_reset_t cpu); +void R_BSP_ModuleResetEnable(bsp_module_reset_t module_to_enable); +void R_BSP_ModuleResetDisable(bsp_module_reset_t module_to_disable); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_module_stop.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_module_stop.h new file mode 100644 index 00000000000..da3acc8066f --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_module_stop.h @@ -0,0 +1,261 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_MODULE_H +#define BSP_MODULE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Cancels the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped + * @param channel The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ + BSP_MSTP_REG_ ## ip(channel); \ + BSP_MSTP_DMY_ ## ip(channel); \ + BSP_MSTP_DMY_ ## ip(channel); \ + BSP_MSTP_DMY_ ## ip(channel); \ + BSP_MSTP_DMY_ ## ip(channel); \ + BSP_MSTP_DMY_ ## ip(channel); \ + FSP_CRITICAL_SECTION_EXIT;} + +/*******************************************************************************************************************//** + * Enables the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped + * @param channel The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ + BSP_MSTP_REG_ ## ip(channel); \ + FSP_CRITICAL_SECTION_EXIT;} + +/** @} (end addtogroup BSP_MCU) */ + +#define BSP_MSTP_REG_FSP_IP_BSC(channel) R_SYSC_NS->MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_BSC(channel) (1U); +#define BSP_MSTP_DMY_FSP_IP_BSC(channel) R_BSC->SDCR; + +#define BSP_MSTP_REG_FSP_IP_XSPI(channel) R_SYSC_NS->MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_XSPI(channel) (1U << (4U + channel)); +#define BSP_MSTP_DMY_FSP_IP_XSPI(channel) (0 >= channel) ? R_XSPI0->WRAPCFG : R_XSPI1->WRAPCFG + +#define BSP_MSTP_REG_FSP_IP_SCI(channel) *((4U >= channel) ? &R_SYSC_NS->MSTPCRA : &R_SYSC_S->MSTPCRG) +#define BSP_MSTP_BIT_FSP_IP_SCI(channel) ((4U >= channel) ? (1U << (8U + channel)) : (1U)); +#define BSP_MSTP_DMY_FSP_IP_SCI(channel) (0 >= channel) ? R_SCI0->RDR : ((1 >= channel) ? R_SCI1->RDR : \ + ((2 >= \ + channel) ? R_SCI2->RDR : ((3 >= \ + channel) \ + ? R_SCI3 \ + ->RDR : \ + ((4 \ + >= \ + channel) \ + ? R_SCI4 \ + ->RDR : \ + R_SCI5-> \ + RDR)))) + +#define BSP_MSTP_REG_FSP_IP_IIC(channel) *((1U >= channel) ? &R_SYSC_NS->MSTPCRB : &R_SYSC_S->MSTPCRG) +#define BSP_MSTP_BIT_FSP_IP_IIC(channel) ((1U >= channel) ? (1U << (0U + channel)) : (1U << (1U))); +#define BSP_MSTP_DMY_FSP_IP_IIC(channel) (0 >= channel) ? R_IIC0->ICCR1 : ((1 >= channel) ? R_IIC1->ICCR1 \ + : R_IIC2->ICCR1) + +#define BSP_MSTP_REG_FSP_IP_SPI(channel) *((2U >= channel) ? &R_SYSC_NS->MSTPCRB : &R_SYSC_S->MSTPCRG) +#define BSP_MSTP_BIT_FSP_IP_SPI(channel) ((2U >= channel) ? (1U << (4U + channel)) : (1U << (2U))); +#define BSP_MSTP_DMY_FSP_IP_SPI(channel) (0 >= channel) ? R_SPI0->SPCKD : ((1 >= channel) ? R_SPI1->SPCKD : \ + ((2 >= \ + channel) ? R_SPI2->SPCKD : R_SPI3 \ + ->SPCKD)) + +#define BSP_MSTP_REG_FSP_IP_MTU3(channel) R_SYSC_NS->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_MTU3(channel) (1U); +#define BSP_MSTP_DMY_FSP_IP_MTU3(channel) R_MTU0->TCR; + +#define BSP_MSTP_REG_FSP_IP_GPT(channel) *((13U >= channel) ? &R_SYSC_NS->MSTPCRC : &R_SYSC_S->MSTPCRG) +#define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((6U >= channel) ? (1U << (1U)) : ((13U >= channel) ? \ + (1U << (2U)) : (1U << (3U)))); +#define BSP_MSTP_DMY_FSP_IP_GPT(channel) (6 >= \ + channel) ? R_GPT0->GTSTR : ((13 >= \ + channel) ? R_GPT7->GTSTR : R_GPT14-> \ + GTSTR); +#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_SYSC_NS->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (5U)); +#define BSP_MSTP_DMY_FSP_IP_TFU(channel) R_TFU->TRGSTS; + +#define BSP_MSTP_REG_FSP_IP_ADC12(channel) R_SYSC_NS->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_ADC12(channel) (1U << (6U + channel)); +#define BSP_MSTP_DMY_FSP_IP_ADC12(channel) (0 >= channel) ? R_ADC120->ADCSR : R_ADC121->ADCSR; + +#define BSP_MSTP_REG_FSP_IP_DSMIF(channel) R_SYSC_NS->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_DSMIF(channel) (1U << (0U + channel)); +#define BSP_MSTP_DMY_FSP_IP_DSMIF(channel) (0 >= channel) ? R_DSMIF0->DSSEICR : R_DSMIF1->DSSEICR + +#define BSP_MSTP_REG_FSP_IP_CMT(channel) R_SYSC_NS->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_CMT(channel) (1U << (2U + channel)); +#define BSP_MSTP_DMY_FSP_IP_CMT(channel) (0 >= \ + channel) ? R_CMT->UNT[0].CMSTR0 : ((1 >= \ + channel) ? R_CMT->UNT[1].CMSTR0 \ + : R_CMT->UNT[2].CMSTR0) + +#define BSP_MSTP_REG_FSP_IP_CMTW(channel) R_SYSC_NS->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_CMTW(channel) (1U << (5U + channel)); +#define BSP_MSTP_DMY_FSP_IP_CMTW(channel) (0 >= channel) ? R_CMTW0->CMWSTR : R_CMTW1->CMWSTR + +#define BSP_MSTP_REG_FSP_IP_TSU(channel) R_SYSC_NS->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_TSU(channel) (1U << (7U)); +#define BSP_MSTP_DMY_FSP_IP_TSU(channel) R_TSU->TSUSM; + +#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_SYSC_NS->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (8U)); +#define BSP_MSTP_DMY_FSP_IP_DOC(channel) R_DOC->DOCR + +#define BSP_MSTP_REG_FSP_IP_CRC(channel) *((0U == channel) ? &R_SYSC_NS->MSTPCRD : &R_SYSC_S->MSTPCRG) +#define BSP_MSTP_BIT_FSP_IP_CRC(channel) ((0U == channel) ? (1U << (9U)) : (1U << (4U))); +#define BSP_MSTP_DMY_FSP_IP_CRC(channel) (0 >= channel) ? R_CRC0->CRCDIR : R_CRC1->CRCDIR; + +#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_SYSC_NS->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (10U)); +#define BSP_MSTP_DMY_FSP_IP_CANFD(channel) R_CANFD->CFDGIPV; + +#define BSP_MSTP_REG_FSP_IP_CKIO(channel) R_SYSC_NS->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_CKIO(channel) (1U << (11U)); +#define BSP_MSTP_DMY_FSP_IP_CKIO(channel) ; + +#define BSP_MSTP_REG_FSP_IP_GMAC(channel) R_SYSC_NS->MSTPCRE +#define BSP_MSTP_BIT_FSP_IP_GMAC(channel) (1U); +#define BSP_MSTP_DMY_FSP_IP_GMAC(channel) R_GMAC->MAC_Configuration + +#define BSP_MSTP_REG_FSP_IP_ETHSW(channel) R_SYSC_NS->MSTPCRE +#define BSP_MSTP_BIT_FSP_IP_ETHSW(channel) (1U << (1U)); +#define BSP_MSTP_DMY_FSP_IP_ETHSW(channel) R_ETHSW->REVISION + +#define BSP_MSTP_REG_FSP_IP_ESC(channel) R_SYSC_NS->MSTPCRE +#define BSP_MSTP_BIT_FSP_IP_ESC(channel) (1U << (2U)); +#define BSP_MSTP_DMY_FSP_IP_ESC(channel) R_ESC->TYPE; + +#define BSP_MSTP_REG_FSP_IP_ETHSS(channel) R_SYSC_NS->MSTPCRE +#define BSP_MSTP_BIT_FSP_IP_ETHSS(channel) (1U << (3U)); +#define BSP_MSTP_DMY_FSP_IP_ETHSS(channel) R_ETHSS->PRCMD + +#define BSP_MSTP_REG_FSP_IP_ENCIF(channel) R_SYSC_NS->MSTPCRE +#define BSP_MSTP_BIT_FSP_IP_ENCIF(channel) (1U << (4U)); +#define BSP_MSTP_DMY_FSP_IP_ENCIF(channel) ; + +#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_SYSC_NS->MSTPCRE +#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (8U)); +#define BSP_MSTP_DMY_FSP_IP_USBHS(channel) R_USBHC->HCREVISION; + +#define BSP_MSTP_REG_FSP_IP_TRACECLOCK(channel) R_SYSC_S->MSTPCRF +#define BSP_MSTP_BIT_FSP_IP_TRACECLOCK(channel) (1U << (0U)); +#define BSP_MSTP_DMY_FSP_IP_TRACECLOCK(channel) ; + +#define BSP_MSTP_REG_FSP_IP_RTC(channel) R_SYSC_S->MSTPCRG +#define BSP_MSTP_BIT_FSP_IP_RTC(channel) (1U << (5U)); +#define BSP_MSTP_DMY_FSP_IP_RTC(channel) R_RTC->RTCA0CTL0; + +#define BSP_MSTP_REG_FSP_IP_CLMA(channel) R_SYSC_S->MSTPCRG +#define BSP_MSTP_BIT_FSP_IP_CLMA(channel) ((2U >= channel) ? \ + (1U << (9U + channel)) : (1U << (8U))); +#define BSP_MSTP_DMY_FSP_IP_CLMA(channel) (0 >= \ + channel) ? R_CLMA0->CTL0 : ((1 >= \ + channel) ? R_CLMA1->CTL0 : ((2 >= \ + channel) ? \ + R_CLMA2-> \ + CTL0 : \ + R_CLMA3-> \ + CTL0)); +#if BSP_FEATURE_BSP_SHOSTIF_SUPPORTED + #define BSP_MSTP_REG_FSP_IP_SHOSTIF(channel) R_SYSC_S->MSTPCRI + #define BSP_MSTP_BIT_FSP_IP_SHOSTIF(channel) (1U << (1U)); + #define BSP_MSTP_DMY_FSP_IP_SHOSTIF(channel) R_SHOSTIF->CTRLR0; +#endif + +#if (2 == BSP_FEATURE_BSP_AFMT_UNIT) + #define BSP_MSTP_REG_FSP_IP_AFMT(channel) *((0U == channel) ? &R_SYSC_NS->MSTPCRJ : &R_SYSC_NS->MSTPCRK) + #define BSP_MSTP_BIT_FSP_IP_AFMT(channel) (1U << (0U)); + #define BSP_MSTP_DMY_FSP_IP_AFMT(channel) (0 == channel) ? R_AFMT0->COMMAND : R_AFMT1->COMMAND; +#endif + +#if (2 == BSP_FEATURE_BSP_HDSL_UNIT) + #define BSP_MSTP_REG_FSP_IP_HDSL(channel) *((0U == channel) ? &R_SYSC_NS->MSTPCRJ : &R_SYSC_NS->MSTPCRK) + #define BSP_MSTP_BIT_FSP_IP_HDSL(channel) (1U << (1U)); + #define BSP_MSTP_DMY_FSP_IP_HDSL(channel) (0 == channel) ? R_HDSLD0->SYS_CTRL : R_HDSLD1->SYS_CTRL; +#endif + +#if (2 == BSP_FEATURE_BSP_BISS_UNIT) + #define BSP_MSTP_REG_FSP_IP_BISS(channel) *((0U == channel) ? &R_SYSC_NS->MSTPCRJ : &R_SYSC_NS->MSTPCRK) + #define BSP_MSTP_BIT_FSP_IP_BISS(channel) (1U << (2U)); + #define BSP_MSTP_DMY_FSP_IP_BISS(channel) (0 == channel) ? R_BISS0->SCDATA[0].L : R_BISS1->SCDATA[0].L; +#endif + +#if (2 == BSP_FEATURE_BSP_ENDAT_UNIT) + #define BSP_MSTP_REG_FSP_IP_ENDAT(channel) *((0U == channel) ? &R_SYSC_NS->MSTPCRJ : &R_SYSC_NS->MSTPCRK) + #define BSP_MSTP_BIT_FSP_IP_ENDAT(channel) (1U << (3U)); + #define BSP_MSTP_DMY_FSP_IP_ENDAT(channel) (0 == channel) ? R_ENDAT0->SEND : R_ENDAT1->SEND; +#endif + +#if BSP_FEATURE_BSP_ENCOUT_SUPPORTED + #define BSP_MSTP_REG_FSP_IP_ENCOUT(channel) R_SYSC_NS->MSTPCRL + #define BSP_MSTP_BIT_FSP_IP_ENCOUT(channel) (1U << (0U)); + #define BSP_MSTP_DMY_FSP_IP_ENCOUT(channel) R_ENCOUT->CTL; +#endif + +#if BSP_FEATURE_BSP_MSTP_CR52_CPU1_HAS_MSTPCRH + #define BSP_MSTP_REG_FSP_IP_CPU1(channel) R_SYSC_S->MSTPCRH + #define BSP_MSTP_BIT_FSP_IP_CPU1(channel) (1U << (1U)); + #define BSP_MSTP_DMY_FSP_IP_CPU1(channel) ; +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_register_protection.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_register_protection.c new file mode 100644 index 00000000000..8db202648dc --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_register_protection.c @@ -0,0 +1,116 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Used for holding reference counters for protection bits. */ +volatile uint16_t g_protect_counters[] = +{ + 0U, 0U, 0U, 0U +}; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */ +static const uint16_t g_prcr_masks[] = +{ + 0x0001U, /* PRC0. */ + 0x0002U, /* PRC1. */ + 0x0004U, /* PRC2. */ + 0x0008U, /* PRC3. */ +}; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enable register protection. Registers that are protected cannot be written to. Register protection is + * enabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR). + * + * @param[in] regs_to_protect Registers which have write protection enabled. + **********************************************************************************************************************/ +void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect) +{ + /* Is it safe to disable write access? */ + if (0U != g_protect_counters[regs_to_protect]) + { + /* Decrement the protect counter */ + g_protect_counters[regs_to_protect]--; + } + + /* Is it safe to disable write access? */ + if (0U == g_protect_counters[regs_to_protect]) + { + /** Enable protection using PRCR register. */ + + /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ + R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect])); + R_RWP_S->PRCRS = ((R_RWP_S->PRCRS | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect])); + } +} + +/*******************************************************************************************************************//** + * Disable register protection. Registers that are protected cannot be written to. Register protection is + * disabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR). + * + * @param[in] regs_to_unprotect Registers which have write protection disabled. + **********************************************************************************************************************/ +void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect) +{ + /* If this is first entry then disable protection. */ + if (0U == g_protect_counters[regs_to_unprotect]) + { + /** Disable protection using PRCR register. */ + + /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ + R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]); + R_RWP_S->PRCRS = ((R_RWP_S->PRCRS | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]); + } + + /** Increment the protect counter */ + g_protect_counters[regs_to_unprotect]++; +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_register_protection.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_register_protection.h new file mode 100644 index 00000000000..63917ea4690 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_register_protection.h @@ -0,0 +1,76 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_REGISTER_PROTECTION_H +#define BSP_REGISTER_PROTECTION_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** The different types of registers that can be protected. */ +typedef enum e_bsp_reg_protect +{ + /** Enables writing to the registers related to the clock generation circuit. */ + BSP_REG_PROTECT_CGC = 0, + + /** Enables writing to the registers related to low power consumption and reset. */ + BSP_REG_PROTECT_LPC_RESET, + + /** Enables writing to the registers related to GPIO. */ + BSP_REG_PROTECT_GPIO, + + /** Enables writing to the registers related to Non-Safety reg. */ + BSP_REG_PROTECT_SYSTEM, +} bsp_reg_protect_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_register_protect_open(void); // Used internally by BSP + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_reset.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_reset.c new file mode 100644 index 00000000000..bc5669f72d1 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_reset.c @@ -0,0 +1,170 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_RESET_MRCTL_BIT_SHIFT_MASK (0x0000001FU) +#define BSP_RESET_MRCTL_SELECT_MASK (0x001F0000U) +#define BSP_RESET_MRCTL_REGION_SELECT_MASK (0x00400000U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Occur the system software reset. + **********************************************************************************************************************/ +void R_BSP_SystemReset (void) +{ + /* System software reset. */ + R_SYSC_S->SWRSYS = BSP_PRV_RESET_KEY; +} + +/*******************************************************************************************************************//** + * Occur the CPU software reset. + * + * @param[in] cpu to be reset state. + **********************************************************************************************************************/ +void R_BSP_CPUReset (bsp_reset_t cpu) +{ + if (BSP_RESET_CR52_0 == cpu) + { + /* CR52_0 software reset. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET); + R_SYSC_S->SWRCPU0 = BSP_PRV_RESET_KEY; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET); + __WFI(); + } + +#if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM) + else if (BSP_RESET_CR52_1 == cpu) + { + /* CR52_1 software reset. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET); + R_SYSC_S->SWRCPU1 = BSP_PRV_RESET_KEY; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET); + __WFI(); + } +#endif + else + { + /* Do Nothing. */ + } +} + +/*******************************************************************************************************************//** + * Release the CPU reset state. + * + * @param[in] cpu to be release reset state. + **********************************************************************************************************************/ +void R_BSP_CPUResetRelease (bsp_reset_t cpu) +{ + if (BSP_RESET_CR52_0 == cpu) + { + /* Release CR52_0 reset state. */ + R_SYSC_S->SWRCPU0 = BSP_PRV_RESET_RELEASE_KEY; + } + +#if (2 == BSP_FEATURE_BSP_CR52_CORE_NUM) + else if (BSP_RESET_CR52_1 == cpu) + { + /* Release CR52_1 reset state. */ + R_SYSC_S->SWRCPU1 = BSP_PRV_RESET_RELEASE_KEY; + } +#endif + else + { + /* Do Nothing. */ + } +} + +/*******************************************************************************************************************//** + * Enable module reset state. + * + * @param[in] module_to_enable Modules to enable module reset state. + **********************************************************************************************************************/ +void R_BSP_ModuleResetEnable (bsp_module_reset_t module_to_enable) +{ + volatile uint32_t mrctl; + uint32_t * p_reg; + + /** When MRCTLn register exists in the safety region, + * it is necessary to add an offset of safety region. */ + p_reg = (uint32_t *) &R_SYSC_NS->MRCTLA + + (((module_to_enable & BSP_RESET_MRCTL_SELECT_MASK) >> 16U) + + (module_to_enable & BSP_RESET_MRCTL_REGION_SELECT_MASK)); + mrctl = 1U << (module_to_enable & BSP_RESET_MRCTL_BIT_SHIFT_MASK); + + /** Enable module reset state using MRCTLE register. */ + *p_reg |= mrctl; + + /** To ensure processing after module reset. */ + mrctl = *(volatile uint32_t *) (p_reg); +} + +/*******************************************************************************************************************//** + * Disable module reset state. + * + * @param[in] module_to_disable Modules to disable module reset state. + **********************************************************************************************************************/ +void R_BSP_ModuleResetDisable (bsp_module_reset_t module_to_disable) +{ + volatile uint32_t mrctl; + uint32_t * p_reg; + + /** When MRCTLn register exists in the safety region, + * it is necessary to add an offset of safety region. */ + p_reg = (uint32_t *) &R_SYSC_NS->MRCTLA + + (((module_to_disable & BSP_RESET_MRCTL_SELECT_MASK) >> 16U) + + (module_to_disable & BSP_RESET_MRCTL_REGION_SELECT_MASK)); + mrctl = 1U << (module_to_disable & BSP_RESET_MRCTL_BIT_SHIFT_MASK); + + /** Disable module stop state using MRCTLn register. */ + *p_reg &= ~mrctl; + + /** In order to secure processing after release from module reset, + * dummy read the same register at least three times. + * Refer to "Notes on Module Reset Control Register Operation" of the RZ microprocessor manual. */ + mrctl = *(volatile uint32_t *) (p_reg); + mrctl = *(volatile uint32_t *) (p_reg); + mrctl = *(volatile uint32_t *) (p_reg); +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_reset.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_reset.h new file mode 100644 index 00000000000..c6a574057ab --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_reset.h @@ -0,0 +1,174 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_RESET_H +#define BSP_RESET_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Key code for writing reset register. */ +#define BSP_PRV_RESET_KEY (0x4321A501U) +#define BSP_PRV_RESET_RELEASE_KEY (0x00000000U) + +/* MRCTL register selection. Bits 16-20 assign values in order for the module control registers (A=0, E=4). + * Bit 24 indicates whether MRCTLn register is in the safety region. */ +#define BSP_RESET_MRCTLA_SELECT (0x00000000U) +#define BSP_RESET_MRCTLE_SELECT (0x00040000U) +#define BSP_RESET_MRCTLI_SELECT (0x00480000U) +#define BSP_RESET_MRCTLJ_SELECT (0x00090000U) +#define BSP_RESET_MRCTLK_SELECT (0x000A0000U) + +/* MRCTL register bit number. */ +#define BSP_RESET_MRCTL_BIT0_SHIFT (0x00000000U) +#define BSP_RESET_MRCTL_BIT1_SHIFT (0x00000001U) +#define BSP_RESET_MRCTL_BIT2_SHIFT (0x00000002U) +#define BSP_RESET_MRCTL_BIT3_SHIFT (0x00000003U) +#define BSP_RESET_MRCTL_BIT4_SHIFT (0x00000004U) +#define BSP_RESET_MRCTL_BIT5_SHIFT (0x00000005U) +#define BSP_RESET_MRCTL_BIT6_SHIFT (0x00000006U) +#define BSP_RESET_MRCTL_BIT7_SHIFT (0x00000007U) +#define BSP_RESET_MRCTL_BIT8_SHIFT (0x00000008U) +#define BSP_RESET_MRCTL_BIT9_SHIFT (0x00000009U) +#define BSP_RESET_MRCTL_BIT10_SHIFT (0x0000000AU) +#define BSP_RESET_MRCTL_BIT11_SHIFT (0x0000000BU) +#define BSP_RESET_MRCTL_BIT12_SHIFT (0x0000000CU) +#define BSP_RESET_MRCTL_BIT13_SHIFT (0x0000000DU) +#define BSP_RESET_MRCTL_BIT14_SHIFT (0x0000000EU) +#define BSP_RESET_MRCTL_BIT15_SHIFT (0x0000000FU) +#define BSP_RESET_MRCTL_BIT16_SHIFT (0x00000010U) +#define BSP_RESET_MRCTL_BIT17_SHIFT (0x00000011U) +#define BSP_RESET_MRCTL_BIT18_SHIFT (0x00000012U) +#define BSP_RESET_MRCTL_BIT19_SHIFT (0x00000013U) +#define BSP_RESET_MRCTL_BIT20_SHIFT (0x00000014U) +#define BSP_RESET_MRCTL_BIT21_SHIFT (0x00000015U) +#define BSP_RESET_MRCTL_BIT22_SHIFT (0x00000016U) +#define BSP_RESET_MRCTL_BIT23_SHIFT (0x00000017U) +#define BSP_RESET_MRCTL_BIT24_SHIFT (0x00000018U) +#define BSP_RESET_MRCTL_BIT25_SHIFT (0x00000019U) +#define BSP_RESET_MRCTL_BIT26_SHIFT (0x0000001AU) +#define BSP_RESET_MRCTL_BIT27_SHIFT (0x0000001BU) +#define BSP_RESET_MRCTL_BIT28_SHIFT (0x0000001CU) +#define BSP_RESET_MRCTL_BIT29_SHIFT (0x0000001DU) +#define BSP_RESET_MRCTL_BIT30_SHIFT (0x0000001EU) +#define BSP_RESET_MRCTL_BIT31_SHIFT (0x0000001FU) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** CPU to be reset target.*/ +typedef enum e_bsp_reset +{ + BSP_RESET_CR52_0 = 0, ///< Software reset for CR52_0 + BSP_RESET_CR52_1 = 1, ///< Software reset for CR52_1 +} bsp_reset_t; + +/** The different types of registers that can control the reset of peripheral modules related to Ethernet. */ +typedef enum e_bsp_module_reset +{ + /** Enables writing to the registers related to xSPI Unit 0 reset control. */ + BSP_MODULE_RESET_XSPI0 = (BSP_RESET_MRCTLA_SELECT | BSP_RESET_MRCTL_BIT4_SHIFT), + + /** Enables writing to the registers related to xSPI Unit 1 reset control. */ + BSP_MODULE_RESET_XSPI1 = (BSP_RESET_MRCTLA_SELECT | BSP_RESET_MRCTL_BIT5_SHIFT), + + /** Enables writing to the registers related to GMAC (PCLKH clock domain) reset control. */ + BSP_MODULE_RESET_GMAC0_PCLKH = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT0_SHIFT), + + /** Enables writing to the registers related to GMAC (PCLKM clock domain) reset control. */ + BSP_MODULE_RESET_GMAC0_PCLKM = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT1_SHIFT), + + /** Enables writing to the registers related to ETHSW reset control. */ + BSP_MODULE_RESET_ETHSW = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT2_SHIFT), + + /** Enables writing to the registers related to ESC (Bus clock domain) reset control. */ + BSP_MODULE_RESET_ESC_BUS = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT3_SHIFT), + + /** Enables writing to the registers related to ESC (IP clock domain) reset control. */ + BSP_MODULE_RESET_ESC_IP = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT4_SHIFT), + + /** Enables writing to the registers related to Ethernet subsystem register reset control. */ + BSP_MODULE_RESET_ESC_ETH_SUBSYSTEM = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT5_SHIFT), + + /** Enables writing to the registers related to MII converter reset control. */ + BSP_MODULE_RESET_MII = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT6_SHIFT), + + /** Enables writing to the registers related to SHOSTIF (Master bus clock domain) reset control. */ + BSP_MODULE_RESET_SHOSTIF_MASTER_BUS_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT1_SHIFT), + + /** Enables writing to the registers related to SHOSTIF (Slave bus clock domain) reset control. */ + BSP_MODULE_RESET_SHOSTIF_SLAVE_BUS_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT2_SHIFT), + + /** Enables writing to the registers related to SHOSTIF (IP clock domain) reset control. */ + BSP_MODULE_RESET_SHOSTIF_IP_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT3_SHIFT), + + /** Enables writing to the registers related to AFMT0 reset control. */ + BSP_MODULE_RESET_AFMT0 = (BSP_RESET_MRCTLJ_SELECT | BSP_RESET_MRCTL_BIT0_SHIFT), + + /** Enables writing to the registers related to HDSL0 reset control. */ + BSP_MODULE_RESET_HDSL0 = (BSP_RESET_MRCTLJ_SELECT | BSP_RESET_MRCTL_BIT1_SHIFT), + + /** Enables writing to the registers related to BISS0 reset control. */ + BSP_MODULE_RESET_BISS0 = (BSP_RESET_MRCTLJ_SELECT | BSP_RESET_MRCTL_BIT2_SHIFT), + + /** Enables writing to the registers related to ENDAT0 reset control. */ + BSP_MODULE_RESET_ENDAT0 = (BSP_RESET_MRCTLJ_SELECT | BSP_RESET_MRCTL_BIT3_SHIFT), + + /** Enables writing to the registers related to AFMT1 reset control. */ + BSP_MODULE_RESET_AFMT1 = (BSP_RESET_MRCTLK_SELECT | BSP_RESET_MRCTL_BIT0_SHIFT), + + /** Enables writing to the registers related to HDSL1 reset control. */ + BSP_MODULE_RESET_HDSL1 = (BSP_RESET_MRCTLK_SELECT | BSP_RESET_MRCTL_BIT1_SHIFT), + + /** Enables writing to the registers related to BISS1 reset control. */ + BSP_MODULE_RESET_BISS1 = (BSP_RESET_MRCTLK_SELECT | BSP_RESET_MRCTL_BIT2_SHIFT), + + /** Enables writing to the registers related to ENDAT1 reset control. */ + BSP_MODULE_RESET_ENDAT1 = (BSP_RESET_MRCTLK_SELECT | BSP_RESET_MRCTL_BIT3_SHIFT), +} bsp_module_reset_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_sbrk.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_sbrk.c new file mode 100644 index 00000000000..35759244d0e --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_sbrk.c @@ -0,0 +1,108 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#include +#include +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +caddr_t _sbrk(int incr); + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * FSP implementation of the standard library _sbrk() function. + * @param[in] inc The number of bytes being asked for by malloc(). + * + * @note This function overrides the _sbrk version that exists in the newlib library that is linked with. + * That version improperly relies on the SP as part of it's allocation strategy. This is bad in general and + * worse in an RTOS environment. This version insures that we allocate the byte pool requested by malloc() + * only from our allocated HEAP area. Also note that newlib is pre-built and forces the pagesize used by + * malloc() to be 4096. That requires that we have a HEAP of at least 4096 if we are to support malloc(). + * @retval Address of allocated area if successful, -1 otherwise. + **********************************************************************************************************************/ +caddr_t _sbrk (int incr) +{ + extern char _Heap_Begin __asm("__HeapBase"); ///< Defined by the linker. + + extern char _Heap_Limit __asm("__HeapLimit"); ///< Defined by the linker. + + uint32_t bytes = (uint32_t) incr; + static char * current_heap_end = 0; + char * current_block_address; + + if (current_heap_end == 0) + { + current_heap_end = &_Heap_Begin; + } + + current_block_address = current_heap_end; + + /* The returned address must be aligned to a word boundary to prevent hard faults on cores that do not support + * unaligned access. We assume the heap starts on a word boundary and make sure all allocations are a multiple + * of 4. */ + bytes = (bytes + 3U) & (~3U); + if (current_heap_end + bytes > &_Heap_Limit) + { + /** Heap has overflowed */ + errno = ENOMEM; + + return (caddr_t) -1; + } + + current_heap_end += bytes; + + return (caddr_t) current_block_address; +} + +#endif + +/******************************************************************************************************************//** + * @} (end addtogroup BSP_MCU) + *********************************************************************************************************************/ diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_semaphore.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_semaphore.c new file mode 100644 index 00000000000..600fb1f0ccb --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_semaphore.c @@ -0,0 +1,70 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Private definition to set enumeration values. */ +#define BSP_PRV_SYTSEMFEN_ENABLE (0x00000001U) +#define BSP_PRV_RESOURCE_NOT_USED (0x00000001U) +#define BSP_SEMAPHORE_RESOURCE_MAX (8U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Semaphore initialization. + **********************************************************************************************************************/ +void bsp_semaphore_init (void) +{ +#if BSP_FEATURE_SEM_SUPPORTED + uint32_t sem_num; + + /* Disable register protection for semaphore related registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM); + + /* Enable read clear function. */ + R_SEM->SYTSEMFEN = BSP_PRV_SYTSEMFEN_ENABLE; + + for (sem_num = 0; sem_num < BSP_SEMAPHORE_RESOURCE_MAX; sem_num++) + { + /* Set the semaphore state not being used. */ + R_SEM->SYTSEMF[sem_num] = BSP_PRV_RESOURCE_NOT_USED; + } + + /* Enable register protection for semaphore related registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM); +#endif +} diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_semaphore.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_semaphore.h new file mode 100644 index 00000000000..e36fb9a9c29 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_semaphore.h @@ -0,0 +1,100 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_SEMAPHORE_H +#define BSP_SEMAPHORE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** The semaphore resource state shared by CPU0 and CPU1 */ +typedef enum e_bsp_resource_state +{ + BSP_RESOURCE_STATE_BEING_USED = 0, ///< Semaphore resource being used. + BSP_RESOURCE_STATE_NOT_BEING_USED = 1, ///< Semaphore resource not being used. +} bsp_resource_state_t; + +/** The semaphore resource number shared by CPU0 and CPU1 */ +typedef enum e_bsp_resource_num +{ + BSP_RESOURCE_NUM_0 = 0, ///< Semaphore resource number 0 + BSP_RESOURCE_NUM_1 = 1, ///< Semaphore resource number 1 + BSP_RESOURCE_NUM_2 = 2, ///< Semaphore resource number 2 + BSP_RESOURCE_NUM_3 = 3, ///< Semaphore resource number 3 + BSP_RESOURCE_NUM_4 = 4, ///< Semaphore resource number 4 + BSP_RESOURCE_NUM_5 = 5, ///< Semaphore resource number 5 + BSP_RESOURCE_NUM_6 = 6, ///< Semaphore resource number 6 + BSP_RESOURCE_NUM_7 = 7, ///< Semaphore resource number 7 +} bsp_resource_num_t; + +#if BSP_FEATURE_SEM_SUPPORTED + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Read semaphore resource status. When SYTSEMFEN = 1, reading this status clear the resource status. + * + * @param[in] sem_num Semaphore number to read resource status. + * + * @retval Resource status. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_SemaphoreStateRead (bsp_resource_num_t sem_num) +{ + return R_SEM->SYTSEMF[sem_num]; +} + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/* Public functions defined in bsp.h */ +void bsp_semaphore_init(void); // Used internally by BSP + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_tfu.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_tfu.h new file mode 100644 index 00000000000..42304d7d02f --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/bsp_tfu.h @@ -0,0 +1,228 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef RENESAS_TFU +#define RENESAS_TFU + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* Mathematical Functions includes. */ +#ifdef __cplusplus + #include +#else + #include +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define R_TFU_HYPOT_SCALING_FACTOR 0.607252935F + +#ifdef __GNUC__ /* and (arm)clang */ + #if (__STDC_VERSION__ < 199901L) && defined(__STRICT_ANSI__) && !defined(__cplusplus) + +/* No form of inline is available, it happens only when -std=c89, gnu89 and + * above are OK */ + #warning \ + "-std=c89 doesn't support type checking on TFU. Please use -std=gnu89 or higher for example -std=c99" + #else + #ifdef __GNUC_GNU_INLINE__ + +/* gnu89 semantics of inline and extern inline are essentially the exact + * opposite of those in C99 */ + #define BSP_TFU_INLINE extern inline __attribute__((always_inline)) + #else /* __GNUC_STDC_INLINE__ */ + #define BSP_TFU_INLINE static inline __attribute__((always_inline)) + #endif + #endif +#elif __ICCARM__ + #define BSP_TFU_INLINE +#else + #error "Compiler not supported!" +#endif + +#if BSP_CFG_USE_TFU_MATHLIB + #define sinf(x) __sinf(x) + #define cosf(x) __cosf(x) + #define atan2f(y, x) __atan2f(y, x) + #define hypotf(x, y) __hypotf(x, y) + #define atan2hypotf(y, x, a, h) __atan2hypotf(y, x, a, h) + #define sincosf(a, s, c) __sincosf(a, s, c) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Calculates sine of the given angle. + * @param[in] angle The value of an angle in radian. + * + * @retval Sine value of an angle. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE float __sinf (float angle) +{ + /* Set the angle to R_TFU->SCDT1 */ + R_TFU->SCDT1 = angle; + + /* Read sin from R_TFU->SCDT1 */ + return R_TFU->SCDT1; +} + +/*******************************************************************************************************************//** + * Calculates cosine of the given angle. + * @param[in] angle The value of an angle in radian. + * + * @retval Cosine value of an angle. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE float __cosf (float angle) +{ + /* Set the angle to R_TFU->SCDT1 */ + R_TFU->SCDT1 = angle; + + /* Read cos from R_TFU->SCDT1 */ + return R_TFU->SCDT0; +} + +/*******************************************************************************************************************//** + * Calculates sine and cosine of the given angle. + * @param[in] angle The value of an angle in radian. + * @param[out] sin Sine value of an angle. + * @param[out] cos Cosine value of an angle. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos) +{ + /* Set the angle to R_TFU->SCDT1 */ + R_TFU->SCDT1 = angle; + + /* Read sin from R_TFU->SCDT1 */ + *sin = R_TFU->SCDT1; + + /* Read sin from R_TFU->SCDT1 */ + *cos = R_TFU->SCDT0; +} + +/*******************************************************************************************************************//** + * Calculates the arc tangent based on given X-cordinate and Y-cordinate values. + * @param[in] y_cord Y-Axis cordinate value. + * @param[in] x_cord X-Axis cordinate value. + * + * @retval Arc tangent for given values. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord) +{ + /* Set X-cordinate to R_TFU->ATDT0 */ + R_TFU->ATDT0 = x_cord; + + /* set Y-cordinate to R_TFU->ATDT1 */ + R_TFU->ATDT1 = y_cord; + + /* Read arctan(y/x) from R_TFU->ATDT1 */ + return R_TFU->ATDT1; +} + +/*******************************************************************************************************************//** + * Calculates the hypotenuse based on given X-cordinate and Y-cordinate values. + * @param[in] y_cord Y-cordinate value. + * @param[in] x_cord X-cordinate value. + * + * @retval Hypotenuse for given values. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord) +{ + /* Set X-coordinate to R_TFU->ATDT0 */ + R_TFU->ATDT0 = x_cord; + + /* set Y-coordinate to R_TFU->ATDT1 */ + R_TFU->ATDT1 = y_cord; + + /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ + return R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; +} + +/*******************************************************************************************************************//** + * Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values. + * @param[in] y_cord Y-cordinate value. + * @param[in] x_cord X-cordinate value. + * @param[out] atan2 Arc tangent for given values. + * @param[out] hypot Hypotenuse for given values. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, float * hypot) +{ + /* Set X-coordinate to R_TFU->ATDT0 */ + R_TFU->ATDT0 = x_cord; + + /* set Y-coordinate to R_TFU->ATDT1 */ + R_TFU->ATDT1 = y_cord; + + /* Read arctan(y/x) from R_TFU->ATDT1 */ + *atan2 = R_TFU->ATDT1; + + /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ + *hypot = R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; +} + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* RENESAS_TFU */ diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c new file mode 100644 index 00000000000..f85e3dbdae9 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c @@ -0,0 +1,48 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Powers on and off the L3 cache way. + **********************************************************************************************************************/ +void r_bsp_cache_l3_power_ctrl (void) +{ + /* Does nothing because CR52 does not have the CLUSTERPWRCTLR register. */ +} diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h new file mode 100644 index 00000000000..a0ca23c5e6b --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_CACHE_CORE_H +#define BSP_CACHE_CORE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void r_bsp_cache_l3_power_ctrl(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c new file mode 100644 index 00000000000..9eea2c8a1da --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c @@ -0,0 +1,63 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This assembly language routine takes roughly 4 cycles per loop. 2 additional cycles + * occur when the loop exits. The 'naked' attribute indicates that the specified function does not need + * prologue/epilogue sequences generated by the compiler. + * @param[in] loop_cnt The number of loops to iterate. + **********************************************************************************************************************/ +BSP_ATTRIBUTE_STACKLESS void r_bsp_software_delay_loop (__attribute__((unused)) uint32_t loop_cnt) +{ + __asm volatile ("sw_delay_loop: \n" + +#if defined(__ICCARM__) || defined(__ARMCC_VERSION) + " subs r0, #1 \n" ///< 1 cycle +#elif defined(__GNUC__) + " sub r0, r0, #1 \n" ///< 1 cycle +#endif + + " cmp r0, #0 \n" ///< 1 cycle + + " bne sw_delay_loop \n" ///< 2 cycles + + " bx lr \n"); ///< 2 cycles +} diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h new file mode 100644 index 00000000000..1e31cd2b4e1 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h @@ -0,0 +1,63 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_DELAY_CORE_H +#define BSP_DELAY_CORE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* The number of cycles required per software delay loop. */ +#ifndef BSP_DELAY_LOOP_CYCLES + #define BSP_DELAY_LOOP_CYCLES (4) +#endif + +/* Calculates the number of delay loops to pass to r_bsp_software_delay_loop to achieve at least the requested cycle + * count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures + * the requested number of loops is at least 1 since r_bsp_software_delay_loop cannot be called with a loop count + * of 0. */ +#define BSP_DELAY_LOOPS_CALCULATE(cycles) (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +BSP_ATTRIBUTE_STACKLESS void r_bsp_software_delay_loop(uint32_t loop_cnt); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c new file mode 100644 index 00000000000..d31ab2fb5b1 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c @@ -0,0 +1,146 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/** ELC event definitions. */ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_IRQ_UINT32_MAX (0xFFFFFFFFU) + +#define BSP_PRV_CLEAR_REG_MAX (13U) +#define BSP_PRV_ALL_BIT_CLEAR (0xFFFFFFFFU) + +#define BSP_PRV_ID_MASK (0x000003FFU) +#define BSP_PRV_INTERRUPTABLE_NUM (32U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +#if VECTOR_DATA_IRQ_COUNT > 0 +extern fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES]; +#endif +extern fsp_vector_t g_sgi_ppi_vector_table[BSP_CORTEX_VECTOR_TABLE_ENTRIES]; + +extern const uint32_t BSP_GICD_ICFGR_INIT[BSP_NON_SELECTABLE_ICFGR_MAX]; + +/* This table is used to store the context in the ISR. */ +void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES]; + +/* GIC current interrupt ID and variable. */ +IRQn_Type g_current_interrupt_num[BSP_PRV_INTERRUPTABLE_NUM]; +uint8_t g_current_interrupt_pointer = 0; + +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_WEAK_REFERENCE = +{ + (bsp_interrupt_event_t) 0 +}; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Using the vector table information section that has been built by the linker and placed into ROM in the + * .vector_info. section, this function will initialize the ICU so that configured ELC events will trigger interrupts + * in the NVIC. + * + **********************************************************************************************************************/ +void bsp_irq_core_cfg (void) +{ + uint32_t gicd_reg_num; + GICD_Type * GICD; + GICR_CONTROL_TARGET_Type * GICR_TARGET0_IFREG; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_IFREG = BSP_PRV_GICR_TARGET0_IFREG_ADDRESS; + + /* Enable Group1 interrupts from the GIC Distributor to the GIC CPU interface. */ + GICD->GICD_CTLR |= 0x00000002UL; + + /* Release Processor Sleep state of the target. */ + GICR_TARGET0_IFREG->GICR_WAKER = 0x00000000UL; + + /* Initialize GICD_ICFGR register for the edge-triggered interrupt. */ + for (gicd_reg_num = 0; gicd_reg_num < BSP_NON_SELECTABLE_ICFGR_MAX; gicd_reg_num++) + { + GICD->GICD_ICFGR[gicd_reg_num] = BSP_GICD_ICFGR_INIT[gicd_reg_num]; + } + + /* Clear the Pending and Active bit for the all interrupts. */ + for (gicd_reg_num = 0; gicd_reg_num < BSP_PRV_CLEAR_REG_MAX; gicd_reg_num++) + { + GICD->GICD_ICPENDR[gicd_reg_num] = BSP_PRV_ALL_BIT_CLEAR; + GICD->GICD_ICACTIVER[gicd_reg_num] = BSP_PRV_ALL_BIT_CLEAR; + } + + __asm volatile ("cpsie i \n" /* Enable IRQ Interrupts */ + "cpsie f \n" /* Enable FIQ Interrupts */ + "cpsie a \n" /* Enable SError Interrupts */ + "isb"); /* Ensuring Context-changing */ +} + +/*******************************************************************************************************************//** + * This function is called first when an interrupt is generated and branches to each interrupt isr function. + * + * @param[in] id GIC INTID used to identify the interrupt. + **********************************************************************************************************************/ +void bsp_common_interrupt_handler (uint32_t id) +{ + uint16_t gic_intid; + IRQn_Type irq; + + /* Get interrupt ID (GIC INTID). */ + gic_intid = (uint16_t) (id & BSP_PRV_ID_MASK); + + irq = (IRQn_Type) (gic_intid - BSP_CORTEX_VECTOR_TABLE_ENTRIES); + + /* Remain the interrupt number */ + g_current_interrupt_num[g_current_interrupt_pointer++] = irq; + __asm volatile ("dmb"); + + BSP_CFG_MULTIPLEX_INTERRUPT_ENABLE + +#if VECTOR_DATA_IRQ_COUNT > 0 + if (BSP_CORTEX_VECTOR_TABLE_ENTRIES <= gic_intid) + { + /* Branch to an interrupt handler. */ + g_vector_table[irq](); + } + else +#endif + { + /* Branch to an interrupt handler. */ + g_sgi_ppi_vector_table[gic_intid](); + } + + g_current_interrupt_pointer--; + + BSP_CFG_MULTIPLEX_INTERRUPT_DISABLE +} diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h new file mode 100644 index 00000000000..c527f9feea2 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h @@ -0,0 +1,355 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_IRQ_CORE_H +#define BSP_IRQ_CORE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES) + +#if (0 == BSP_CFG_CORE_CR52) + #define BSP_PRV_GICD_ADDRESS (GICD0) + #define BSP_PRV_GICR_TARGET0_INTREG_ADDRESS (GICR0_TARGET0_INTREG) + #define BSP_PRV_GICR_TARGET0_IFREG_ADDRESS (GICR0_TARGET0_IFREG) + +#elif (1 == BSP_CFG_CORE_CR52) + #define BSP_PRV_GICD_ADDRESS (GICD1) + #define BSP_PRV_GICR_TARGET0_INTREG_ADDRESS (GICR1_TARGET0_INTREG) + #define BSP_PRV_GICR_TARGET0_IFREG_ADDRESS (GICR1_TARGET0_IFREG) + +#endif + +#define BSP_EVENT_SGI_PPI_ARRAY_NUM (2U) +#define BSP_NON_SELECTABLE_ICFGR_MAX (BSP_VECTOR_TABLE_MAX_ENTRIES / BSP_INTERRUPT_TYPE_OFFSET) + +#define BSP_PRV_IRQ_CONFIG_MASK (0x000000FFU) +#define BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK (1UL << 1UL) + +#define BSP_PRV_GIC_REG_STRIDE04 (4U) +#define BSP_PRV_GIC_REG_STRIDE16 (16U) +#define BSP_PRV_GIC_REG_STRIDE32 (32U) + +#define BSP_PRV_GIC_REG_BITS1 (1U) +#define BSP_PRV_GIC_REG_BITS2 (2U) +#define BSP_PRV_GIC_REG_BITS8 (8U) + +#define BSP_PRV_GIC_REG_MASK_1BIT (1U) + +#define BSP_PRV_GIC_LOWEST_PPI_INTERRUPT_NUM (-17) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES]; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Sets the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @param[in] p_context ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void r_fsp_irq_context_set (IRQn_Type const irq, void * p_context) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + gp_renesas_isr_context[irq + BSP_VECTOR_NUM_OFFSET] = p_context; +} + +/*******************************************************************************************************************//** + * Clear the GIC pending interrupt. + * + * @param[in] irq Interrupt for which to clear the Pending bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + **********************************************************************************************************************/ +__STATIC_INLINE void r_bsp_irq_clear_pending (IRQn_Type irq) +{ + GICD_Type * GICD; + GICR_SGI_PPI_Type * GICR_TARGET0_INTREG; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS; + + if (irq >= 0) + { + uint32_t _irq = (uint32_t) irq; + GICD->GICD_ICPENDR[_irq / BSP_PRV_GIC_REG_STRIDE32] = + (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32)); + } + else + { + uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET); + GICR_TARGET0_INTREG->GICR_ICPENDR0 = (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq); + } +} + +/*******************************************************************************************************************//** + * Get the GIC pending interrupt. + * + * @param[in] irq Interrupt that gets a pending bit.. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @return Value indicating the status of the level interrupt. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t r_bsp_irq_pending_get (IRQn_Type irq) +{ + GICD_Type * GICD; + GICR_SGI_PPI_Type * GICR_TARGET0_INTREG; + uint32_t value = 0; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS; + + if (irq >= 0) + { + uint32_t _irq = (uint32_t) irq; + uint32_t shift = (_irq % BSP_PRV_GIC_REG_STRIDE32); + value = (GICD->GICD_ISPENDR[_irq / BSP_PRV_GIC_REG_STRIDE32] >> shift) & (uint32_t) (BSP_PRV_GIC_REG_MASK_1BIT); + } + else + { + uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET); + uint32_t shift = _irq; + value = (GICR_TARGET0_INTREG->GICR_ISPENDR0 >> shift) & (uint32_t) (BSP_PRV_GIC_REG_MASK_1BIT); + } + + return value; +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context. + * + * @param[in] irq The IRQ number to configure. + * @param[in] priority GIC priority of the interrupt + **********************************************************************************************************************/ +__STATIC_INLINE void r_bsp_irq_cfg (IRQn_Type const irq, uint32_t priority) +{ +#if (52U == __CORTEX_R) + GICD_Type * GICD; + GICR_SGI_PPI_Type * GICR_TARGET0_INTREG; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS; + + if (irq >= 0) + { + uint32_t _irq = (uint32_t) irq; + + /* Set the interrupt group to 1 (IRQ) */ + GICD->GICD_IGROUPR[_irq / BSP_PRV_GIC_REG_STRIDE32] |= + (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32)); + + /* Set the interrupt priority */ + GICD->GICD_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] &= + (uint32_t) (~(BSP_PRV_IRQ_CONFIG_MASK << (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04)))); + GICD->GICD_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] |= + (priority << + (BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT + (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04)))); + } + else + { + uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET); + + /* Set the interrupt group to 1 (IRQ) */ + GICR_TARGET0_INTREG->GICR_IGROUPR0 |= (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq); + + /* Set the interrupt priority */ + GICR_TARGET0_INTREG->GICR_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] &= + (uint32_t) (~(BSP_PRV_IRQ_CONFIG_MASK << (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04)))); + GICR_TARGET0_INTREG->GICR_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] |= + (priority << + (BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT + (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04)))); + } +#endif +} + +/*******************************************************************************************************************//** + * Enable the IRQ in the GIC (Without clearing the pending bit). + * + * @param[in] irq The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the + * Cortex Processor Exceptions Numbers. + **********************************************************************************************************************/ +__STATIC_INLINE void r_bsp_irq_enable_no_clear (IRQn_Type const irq) +{ + GICD_Type * GICD; + GICR_SGI_PPI_Type * GICR_TARGET0_INTREG; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS; + + if (irq >= 0) + { + uint32_t _irq = (uint32_t) irq; + GICD->GICD_ISENABLER[_irq / BSP_PRV_GIC_REG_STRIDE32] |= + (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32)); + } + else + { + uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET); + GICR_TARGET0_INTREG->GICR_ISENABLER0 |= (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq); + } +} + +/*******************************************************************************************************************//** + * Disables interrupts in the GIC. + * + * @param[in] irq The IRQ number to disable in the GIC. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + **********************************************************************************************************************/ +__STATIC_INLINE void r_bsp_irq_disable (IRQn_Type const irq) +{ + GICD_Type * GICD; + GICR_SGI_PPI_Type * GICR_TARGET0_INTREG; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS; + + if (irq >= 0) + { + uint32_t _irq = (uint32_t) irq; + GICD->GICD_ICENABLER[_irq / BSP_PRV_GIC_REG_STRIDE32] = + (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32)); + } + else + { + uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET); + GICR_TARGET0_INTREG->GICR_ICENABLER0 = (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq); + } + + __DSB(); + __ISB(); +} + +/*******************************************************************************************************************//** + * Sets the interrupt detect type. + * + * @param[in] irq The IRQ number to configure. + * @param[in] detect_type GIC detect type of the interrupt (0 : active-HIGH level, 1 : rising edge-triggerd). + **********************************************************************************************************************/ +__STATIC_INLINE void r_bsp_irq_detect_type_set (IRQn_Type const irq, uint32_t detect_type) +{ + GICD_Type * GICD; + GICR_SGI_PPI_Type * GICR_TARGET0_INTREG; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS; + + if (irq >= 0) + { + uint32_t _irq = (uint32_t) irq; + if (0 != detect_type) + { + GICD->GICD_ICFGR[_irq / BSP_PRV_GIC_REG_STRIDE16] |= + (uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK << + (BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16))); + } + else + { + GICD->GICD_ICFGR[_irq / BSP_PRV_GIC_REG_STRIDE16] &= + ~((uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK << + (BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16)))); + } + } + else if (irq >= BSP_PRV_GIC_LOWEST_PPI_INTERRUPT_NUM) + { + uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET); + if (0 != detect_type) + { + GICR_TARGET0_INTREG->GICR_ICFGR1 |= + (uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK << + (BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16))); + } + else + { + GICR_TARGET0_INTREG->GICR_ICFGR1 &= + ~((uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK << + (BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16)))); + } + } + else + { + /* The register that sets the SGI interrupt type (GICR_ICFGR0) is read-only, so do not set it. */ + } +} + +/*******************************************************************************************************************//** + * Sets the interrupt Group. + * + * @param[in] irq The IRQ number to configure. + * @param[in] interrupt_group GIC interrupt group number ( 0 : FIQ, 1 : IRQ ). + **********************************************************************************************************************/ +__STATIC_INLINE void r_bsp_irq_group_set (IRQn_Type const irq, uint32_t interrupt_group) +{ + GICD_Type * GICD; + GICR_SGI_PPI_Type * GICR_TARGET0_INTREG; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS; + + if (irq >= 0) + { + uint32_t _irq = (uint32_t) irq; + GICD->GICD_IGROUPR[_irq / BSP_PRV_GIC_REG_STRIDE32] |= (interrupt_group << (_irq % BSP_PRV_GIC_REG_STRIDE32)); + } + else + { + uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET); + GICR_TARGET0_INTREG->GICR_IGROUPR0 |= interrupt_group << _irq; + } +} + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_irq_core_cfg(void); // Used internally by BSP +void bsp_common_interrupt_handler(uint32_t id); + +/** @} (end addtogroup BSP_MCU_PRV) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_elc.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_elc.h new file mode 100644 index 00000000000..39993b238df --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_elc.h @@ -0,0 +1,543 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RZT2M + * @{ + **********************************************************************************************************************/ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list may change based on based on the device. + * */ +typedef enum e_elc_event_rzt2m +{ + ELC_EVENT_INTCPU0 = (0), // Software interrupt 0 + ELC_EVENT_INTCPU1 = (1), // Software interrupt 1 + ELC_EVENT_INTCPU2 = (2), // Software interrupt 2 + ELC_EVENT_INTCPU3 = (3), // Software interrupt 3 + ELC_EVENT_INTCPU4 = (4), // Software interrupt 4 + ELC_EVENT_INTCPU5 = (5), // Software interrupt 5 + ELC_EVENT_IRQ0 = (6), // External pin interrupt 0 + ELC_EVENT_IRQ1 = (7), // External pin interrupt 1 + ELC_EVENT_IRQ2 = (8), // External pin interrupt 2 + ELC_EVENT_IRQ3 = (9), // External pin interrupt 3 + ELC_EVENT_IRQ4 = (10), // External pin interrupt 4 + ELC_EVENT_IRQ5 = (11), // External pin interrupt 5 + ELC_EVENT_IRQ6 = (12), // External pin interrupt 6 + ELC_EVENT_IRQ7 = (13), // External pin interrupt 7 + ELC_EVENT_IRQ8 = (14), // External pin interrupt 8 + ELC_EVENT_IRQ9 = (15), // External pin interrupt 9 + ELC_EVENT_IRQ10 = (16), // External pin interrupt 10 + ELC_EVENT_IRQ11 = (17), // External pin interrupt 11 + ELC_EVENT_IRQ12 = (18), // External pin interrupt 12 + ELC_EVENT_IRQ13 = (19), // External pin interrupt 13 + ELC_EVENT_BSC_CMI = (20), // Refresh compare match interrupt + ELC_EVENT_DMAC0_INT0 = (21), // DMAC0 transfer completion 0 + ELC_EVENT_DMAC0_INT1 = (22), // DMAC0 transfer completion 1 + ELC_EVENT_DMAC0_INT2 = (23), // DMAC0 transfer completion 2 + ELC_EVENT_DMAC0_INT3 = (24), // DMAC0 transfer completion 3 + ELC_EVENT_DMAC0_INT4 = (25), // DMAC0 transfer completion 4 + ELC_EVENT_DMAC0_INT5 = (26), // DMAC0 transfer completion 5 + ELC_EVENT_DMAC0_INT6 = (27), // DMAC0 transfer completion 6 + ELC_EVENT_DMAC0_INT7 = (28), // DMAC0 transfer completion 7 + ELC_EVENT_DMAC0_INT8 = (29), // DMAC0 transfer completion 8 + ELC_EVENT_DMAC0_INT9 = (30), // DMAC0 transfer completion 9 + ELC_EVENT_DMAC0_INT10 = (31), // DMAC0 transfer completion 10 + ELC_EVENT_DMAC0_INT11 = (32), // DMAC0 transfer completion 11 + ELC_EVENT_DMAC0_INT12 = (33), // DMAC0 transfer completion 12 + ELC_EVENT_DMAC0_INT13 = (34), // DMAC0 transfer completion 13 + ELC_EVENT_DMAC0_INT14 = (35), // DMAC0 transfer completion 14 + ELC_EVENT_DMAC0_INT15 = (36), // DMAC0 transfer completion 15 + ELC_EVENT_DMAC1_INT0 = (37), // DMAC1 transfer completion 0 + ELC_EVENT_DMAC1_INT1 = (38), // DMAC1 transfer completion 1 + ELC_EVENT_DMAC1_INT2 = (39), // DMAC1 transfer completion 2 + ELC_EVENT_DMAC1_INT3 = (40), // DMAC1 transfer completion 3 + ELC_EVENT_DMAC1_INT4 = (41), // DMAC1 transfer completion 4 + ELC_EVENT_DMAC1_INT5 = (42), // DMAC1 transfer completion 5 + ELC_EVENT_DMAC1_INT6 = (43), // DMAC1 transfer completion 6 + ELC_EVENT_DMAC1_INT7 = (44), // DMAC1 transfer completion 7 + ELC_EVENT_DMAC1_INT8 = (45), // DMAC1 transfer completion 8 + ELC_EVENT_DMAC1_INT9 = (46), // DMAC1 transfer completion 9 + ELC_EVENT_DMAC1_INT10 = (47), // DMAC1 transfer completion 10 + ELC_EVENT_DMAC1_INT11 = (48), // DMAC1 transfer completion 11 + ELC_EVENT_DMAC1_INT12 = (49), // DMAC1 transfer completion 12 + ELC_EVENT_DMAC1_INT13 = (50), // DMAC1 transfer completion 13 + ELC_EVENT_DMAC1_INT14 = (51), // DMAC1 transfer completion 14 + ELC_EVENT_DMAC1_INT15 = (52), // DMAC1 transfer completion 15 + ELC_EVENT_CMT0_CMI = (53), // CMT0 Compare match + ELC_EVENT_CMT1_CMI = (54), // CMT1 Compare match + ELC_EVENT_CMT2_CMI = (55), // CMT2 Compare match + ELC_EVENT_CMT3_CMI = (56), // CMT3 Compare match + ELC_EVENT_CMT4_CMI = (57), // CMT4 Compare match + ELC_EVENT_CMT5_CMI = (58), // CMT5 Compare match + ELC_EVENT_CMTW0_CMWI = (59), // CMTW0 Compare match + ELC_EVENT_CMTW0_IC0I = (60), // CMTW0 Input capture of register 0 + ELC_EVENT_CMTW0_IC1I = (61), // CMTW0 Input capture of register 1 + ELC_EVENT_CMTW0_OC0I = (62), // CMTW0 Output compare of register 0 + ELC_EVENT_CMTW0_OC1I = (63), // CMTW0 Output compare of register 1 + ELC_EVENT_CMTW1_CMWI = (64), // CMTW1 Compare match + ELC_EVENT_CMTW1_IC0I = (65), // CMTW1 Input capture of register 0 + ELC_EVENT_CMTW1_IC1I = (66), // CMTW1 Input capture of register 1 + ELC_EVENT_CMTW1_OC0I = (67), // CMTW1 Output compare of register 0 + ELC_EVENT_CMTW1_OC1I = (68), // CMTW1 Output compare of register 1 + ELC_EVENT_TGIA0 = (69), // MTU0.TGRA input capture/compare match + ELC_EVENT_TGIB0 = (70), // MTU0.TGRB input capture/compare match + ELC_EVENT_TGIC0 = (71), // MTU0.TGRC input capture/compare match + ELC_EVENT_TGID0 = (72), // MTU0.TGRD input capture/compare match + ELC_EVENT_TCIV0 = (73), // MTU0.TCNT overflow + ELC_EVENT_TGIE0 = (74), // MTU0.TGRE compare match + ELC_EVENT_TGIF0 = (75), // MTU0.TGRF compare match + ELC_EVENT_TGIA1 = (76), // MTU1.TGRA input capture/compare match + ELC_EVENT_TGIB1 = (77), // MTU1.TGRB input capture/compare match + ELC_EVENT_TCIV1 = (78), // MTU1.TCNT overflow + ELC_EVENT_TCIU1 = (79), // MTU1.TCNT underflow + ELC_EVENT_TGIA2 = (80), // MTU2.TGRA input capture/compare match + ELC_EVENT_TGIB2 = (81), // MTU2.TGRB input capture/compare match + ELC_EVENT_TCIV2 = (82), // MTU2.TCNT overflow + ELC_EVENT_TCIU2 = (83), // MTU2.TCNT underflow + ELC_EVENT_TGIA3 = (84), // MTU3.TGRA input capture/compare match + ELC_EVENT_TGIB3 = (85), // MTU3.TGRB input capture/compare match + ELC_EVENT_TGIC3 = (86), // MTU3.TGRC input capture/compare match + ELC_EVENT_TGID3 = (87), // MTU3.TGRD input capture/compare match + ELC_EVENT_TCIV3 = (88), // MTU3.TCNT overflow + ELC_EVENT_TGIA4 = (89), // MTU4.TGRA input capture/compare match + ELC_EVENT_TGIB4 = (90), // MTU4.TGRB input capture/compare match + ELC_EVENT_TGIC4 = (91), // MTU4.TGRC input capture/compare match + ELC_EVENT_TGID4 = (92), // MTU4.TGRD input capture/compare match + ELC_EVENT_TCIV4 = (93), // MTU4.TCNT overflow/underflow + ELC_EVENT_TGIU5 = (94), // MTU5.TGRU input capture/compare match + ELC_EVENT_TGIV5 = (95), // MTU5.TGRV input capture/compare match + ELC_EVENT_TGIW5 = (96), // MTU5.TGRW input capture/compare match + ELC_EVENT_TGIA6 = (97), // MTU6.TGRA input capture/compare match + ELC_EVENT_TGIB6 = (98), // MTU6.TGRB input capture/compare match + ELC_EVENT_TGIC6 = (99), // MTU6.TGRC input capture/compare match + ELC_EVENT_TGID6 = (100), // MTU6.TGRD input capture/compare match + ELC_EVENT_TCIV6 = (101), // MTU6.TCNT overflow + ELC_EVENT_TGIA7 = (102), // MTU7.TGRA input capture/compare match + ELC_EVENT_TGIB7 = (103), // MTU7.TGRB input capture/compare match + ELC_EVENT_TGIC7 = (104), // MTU7.TGRC input capture/compare match + ELC_EVENT_TGID7 = (105), // MTU7.TGRD input capture/compare match + ELC_EVENT_TCIV7 = (106), // MTU7.TCNT overflow/underflow + ELC_EVENT_TGIA8 = (107), // MTU8.TGRA input capture/compare match + ELC_EVENT_TGIB8 = (108), // MTU8.TGRB input capture/compare match + ELC_EVENT_TGIC8 = (109), // MTU8.TGRC input capture/compare match + ELC_EVENT_TGID8 = (110), // MTU8.TGRD input capture/compare match + ELC_EVENT_TCIV8 = (111), // MTU8.TCNT overflow + ELC_EVENT_OEI1 = (112), // Output enable interrupt 1 + ELC_EVENT_OEI2 = (113), // Output enable interrupt 2 + ELC_EVENT_OEI3 = (114), // Output enable interrupt 3 + ELC_EVENT_OEI4 = (115), // Output enable interrupt 4 + ELC_EVENT_GPT0_CCMPA = (116), // GPT0 GTCCRA input capture/compare match + ELC_EVENT_GPT0_CCMPB = (117), // GPT0 GTCCRB input capture/compare match + ELC_EVENT_GPT0_CMPC = (118), // GPT0 GTCCRC compare match + ELC_EVENT_GPT0_CMPD = (119), // GPT0 GTCCRD compare match + ELC_EVENT_GPT0_CMPE = (120), // GPT0 GTCCRE compare match + ELC_EVENT_GPT0_CMPF = (121), // GPT0 GTCCRF compare match + ELC_EVENT_GPT0_OVF = (122), // GPT0 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT0_UDF = (123), // GPT0 GTCNT underflow + ELC_EVENT_GPT0_DTE = (124), // GPT0 Dead time error + ELC_EVENT_GPT1_CCMPA = (125), // GPT1 GTCCRA input capture/compare match + ELC_EVENT_GPT1_CCMPB = (126), // GPT1 GTCCRB input capture/compare match + ELC_EVENT_GPT1_CMPC = (127), // GPT1 GTCCRC compare match + ELC_EVENT_GPT1_CMPD = (128), // GPT1 GTCCRD compare match + ELC_EVENT_GPT1_CMPE = (129), // GPT1 GTCCRE compare match + ELC_EVENT_GPT1_CMPF = (130), // GPT1 GTCCRF compare match + ELC_EVENT_GPT1_OVF = (131), // GPT1 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT1_UDF = (132), // GPT1 GTCNT underflow + ELC_EVENT_GPT1_DTE = (133), // GPT1 Dead time error + ELC_EVENT_GPT2_CCMPA = (134), // GPT2 GTCCRA input capture/compare match + ELC_EVENT_GPT2_CCMPB = (135), // GPT2 GTCCRB input capture/compare match + ELC_EVENT_GPT2_CMPC = (136), // GPT2 GTCCRC compare match + ELC_EVENT_GPT2_CMPD = (137), // GPT2 GTCCRD compare match + ELC_EVENT_GPT2_CMPE = (138), // GPT2 GTCCRE compare match + ELC_EVENT_GPT2_CMPF = (139), // GPT2 GTCCRF compare match + ELC_EVENT_GPT2_OVF = (140), // GPT2 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT2_UDF = (141), // GPT2 GTCNT underflow + ELC_EVENT_GPT2_DTE = (142), // GPT2 Dead time error + ELC_EVENT_GPT3_CCMPA = (143), // GPT3 GTCCRA input capture/compare match + ELC_EVENT_GPT3_CCMPB = (144), // GPT3 GTCCRB input capture/compare match + ELC_EVENT_GPT3_CMPC = (145), // GPT3 GTCCRC compare match + ELC_EVENT_GPT3_CMPD = (146), // GPT3 GTCCRD compare match + ELC_EVENT_GPT3_CMPE = (147), // GPT3 GTCCRE compare match + ELC_EVENT_GPT3_CMPF = (148), // GPT3 GTCCRF compare match + ELC_EVENT_GPT3_OVF = (149), // GPT3 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT3_UDF = (150), // GPT3 GTCNT underflow + ELC_EVENT_GPT3_DTE = (151), // GPT3 Dead time error + ELC_EVENT_GPT4_CCMPA = (152), // GPT4 GTCCRA input capture/compare match + ELC_EVENT_GPT4_CCMPB = (153), // GPT4 GTCCRB input capture/compare match + ELC_EVENT_GPT4_CMPC = (154), // GPT4 GTCCRC compare match + ELC_EVENT_GPT4_CMPD = (155), // GPT4 GTCCRD compare match + ELC_EVENT_GPT4_CMPE = (156), // GPT4 GTCCRE compare match + ELC_EVENT_GPT4_CMPF = (157), // GPT4 GTCCRF compare match + ELC_EVENT_GPT4_OVF = (158), // GPT4 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT4_UDF = (159), // GPT4 GTCNT underflow + ELC_EVENT_GPT4_DTE = (160), // GPT4 Dead time error + ELC_EVENT_GPT5_CCMPA = (161), // GPT5 GTCCRA input capture/compare match + ELC_EVENT_GPT5_CCMPB = (162), // GPT5 GTCCRB input capture/compare match + ELC_EVENT_GPT5_CMPC = (163), // GPT5 GTCCRC compare match + ELC_EVENT_GPT5_CMPD = (164), // GPT5 GTCCRD compare match + ELC_EVENT_GPT5_CMPE = (165), // GPT5 GTCCRE compare match + ELC_EVENT_GPT5_CMPF = (166), // GPT5 GTCCRF compare match + ELC_EVENT_GPT5_OVF = (167), // GPT5 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT5_UDF = (168), // GPT5 GTCNT underflow + ELC_EVENT_GPT5_DTE = (169), // GPT5 Dead time error + ELC_EVENT_GPT6_CCMPA = (170), // GPT6 GTCCRA input capture/compare match + ELC_EVENT_GPT6_CCMPB = (171), // GPT6 GTCCRB input capture/compare match + ELC_EVENT_GPT6_CMPC = (172), // GPT6 GTCCRC compare match + ELC_EVENT_GPT6_CMPD = (173), // GPT6 GTCCRD compare match + ELC_EVENT_GPT6_CMPE = (174), // GPT6 GTCCRE compare match + ELC_EVENT_GPT6_CMPF = (175), // GPT6 GTCCRF compare match + ELC_EVENT_GPT6_OVF = (176), // GPT6 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT6_UDF = (177), // GPT6 GTCNT underflow + ELC_EVENT_GPT6_DTE = (178), // GPT6 Dead time error + ELC_EVENT_GPT7_CCMPA = (179), // GPT7 GTCCRA input capture/compare match + ELC_EVENT_GPT7_CCMPB = (180), // GPT7 GTCCRB input capture/compare match + ELC_EVENT_GPT7_CMPC = (181), // GPT7 GTCCRC compare match + ELC_EVENT_GPT7_CMPD = (182), // GPT7 GTCCRD compare match + ELC_EVENT_GPT7_CMPE = (183), // GPT7 GTCCRE compare match + ELC_EVENT_GPT7_CMPF = (184), // GPT7 GTCCRF compare match + ELC_EVENT_GPT7_OVF = (185), // GPT7 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT7_UDF = (186), // GPT7 GTCNT underflow + ELC_EVENT_GPT7_DTE = (187), // GPT7 Dead time error + ELC_EVENT_GPT8_CCMPA = (188), // GPT8 GTCCRA input capture/compare match + ELC_EVENT_GPT8_CCMPB = (189), // GPT8 GTCCRB input capture/compare match + ELC_EVENT_GPT8_CMPC = (190), // GPT8 GTCCRC compare match + ELC_EVENT_GPT8_CMPD = (191), // GPT8 GTCCRD compare match + ELC_EVENT_GPT8_CMPE = (192), // GPT8 GTCCRE compare match + ELC_EVENT_GPT8_CMPF = (193), // GPT8 GTCCRF compare match + ELC_EVENT_GPT8_OVF = (194), // GPT8 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT8_UDF = (195), // GPT8 GTCNT underflow + ELC_EVENT_GPT8_DTE = (196), // GPT8 Dead time error + ELC_EVENT_GPT9_CCMPA = (197), // GPT9 GTCCRA input capture/compare match + ELC_EVENT_GPT9_CCMPB = (198), // GPT9 GTCCRB input capture/compare match + ELC_EVENT_GPT9_CMPC = (199), // GPT9 GTCCRC compare match + ELC_EVENT_GPT9_CMPD = (200), // GPT9 GTCCRD compare match + ELC_EVENT_GPT9_CMPE = (201), // GPT9 GTCCRE compare match + ELC_EVENT_GPT9_CMPF = (202), // GPT9 GTCCRF compare match + ELC_EVENT_GPT9_OVF = (203), // GPT9 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT9_UDF = (204), // GPT9 GTCNT underflow + ELC_EVENT_GPT9_DTE = (205), // GPT9 Dead time error + ELC_EVENT_GPT10_CCMPA = (206), // GPT10 GTCCRA input capture/compare match + ELC_EVENT_GPT10_CCMPB = (207), // GPT10 GTCCRB input capture/compare match + ELC_EVENT_GPT10_CMPC = (208), // GPT10 GTCCRC compare match + ELC_EVENT_GPT10_CMPD = (209), // GPT10 GTCCRD compare match + ELC_EVENT_GPT10_CMPE = (210), // GPT10 GTCCRE compare match + ELC_EVENT_GPT10_CMPF = (211), // GPT10 GTCCRF compare match + ELC_EVENT_GPT10_OVF = (212), // GPT10 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT10_UDF = (213), // GPT10 GTCNT underflow + ELC_EVENT_GPT10_DTE = (214), // GPT10 Dead time error + ELC_EVENT_GPT11_CCMPA = (215), // GPT11 GTCCRA input capture/compare match + ELC_EVENT_GPT11_CCMPB = (216), // GPT11 GTCCRB input capture/compare match + ELC_EVENT_GPT11_CMPC = (217), // GPT11 GTCCRC compare match + ELC_EVENT_GPT11_CMPD = (218), // GPT11 GTCCRD compare match + ELC_EVENT_GPT11_CMPE = (219), // GPT11 GTCCRE compare match + ELC_EVENT_GPT11_CMPF = (220), // GPT11 GTCCRF compare match + ELC_EVENT_GPT11_OVF = (221), // GPT11 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT11_UDF = (222), // GPT11 GTCNT underflow + ELC_EVENT_GPT11_DTE = (223), // GPT11 Dead time error + ELC_EVENT_GPT12_CCMPA = (224), // GPT12 GTCCRA input capture/compare match + ELC_EVENT_GPT12_CCMPB = (225), // GPT12 GTCCRB input capture/compare match + ELC_EVENT_GPT12_CMPC = (226), // GPT12 GTCCRC compare match + ELC_EVENT_GPT12_CMPD = (227), // GPT12 GTCCRD compare match + ELC_EVENT_GPT12_CMPE = (228), // GPT12 GTCCRE compare match + ELC_EVENT_GPT12_CMPF = (229), // GPT12 GTCCRF compare match + ELC_EVENT_GPT12_OVF = (230), // GPT12 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT12_UDF = (231), // GPT12 GTCNT underflow + ELC_EVENT_GPT12_DTE = (232), // GPT12 Dead time error + ELC_EVENT_GPT13_CCMPA = (233), // GPT13 GTCCRA input capture/compare match + ELC_EVENT_GPT13_CCMPB = (234), // GPT13 GTCCRB input capture/compare match + ELC_EVENT_GPT13_CMPC = (235), // GPT13 GTCCRC compare match + ELC_EVENT_GPT13_CMPD = (236), // GPT13 GTCCRD compare match + ELC_EVENT_GPT13_CMPE = (237), // GPT13 GTCCRE compare match + ELC_EVENT_GPT13_CMPF = (238), // GPT13 GTCCRF compare match + ELC_EVENT_GPT13_OVF = (239), // GPT13 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT13_UDF = (240), // GPT13 GTCNT underflow + ELC_EVENT_GPT13_DTE = (241), // GPT13 Dead time error + ELC_EVENT_POEG0_GROUP0 = (242), // POEG group A interrupt for channels in LLPP + ELC_EVENT_POEG0_GROUP1 = (243), // POEG group B interrupt for channels in LLPP + ELC_EVENT_POEG0_GROUP2 = (244), // POEG group C interrupt for channels in LLPP + ELC_EVENT_POEG0_GROUP3 = (245), // POEG group D interrupt for channels in LLPP + ELC_EVENT_POEG1_GROUP0 = (246), // POEG group A interrupt for channels in NONSAFETY + ELC_EVENT_POEG1_GROUP1 = (247), // POEG group B interrupt for channels in NONSAFETY + ELC_EVENT_POEG1_GROUP2 = (248), // POEG group C interrupt for channels in NONSAFETY + ELC_EVENT_POEG1_GROUP3 = (249), // POEG group D interrupt for channels in NONSAFETY + ELC_EVENT_GMAC_LPI = (250), // GMAC1 energy efficient + ELC_EVENT_GMAC_PMT = (251), // GMAC1 power management + ELC_EVENT_GMAC_SBD = (252), // GMAC1 general interrupt + ELC_EVENT_ETHSW_INTR = (253), // Ethernet Switch interrupt + ELC_EVENT_ETHSW_DLR = (254), // Ethernet Switch DLR interrupt + ELC_EVENT_ETHSW_PRP = (255), // Ethernet Switch PRP interrupt + ELC_EVENT_ETHSW_IHUB = (256), // Ethernet Switch Integrated Hub interrupt + ELC_EVENT_ETHSW_PTRN0 = (257), // Ethernet Switch RX Pattern Matcher interrupt 0 + ELC_EVENT_ETHSW_PTRN1 = (258), // Ethernet Switch RX Pattern Matcher interrupt 1 + ELC_EVENT_ETHSW_PTRN2 = (259), // Ethernet Switch RX Pattern Matcher interrupt 2 + ELC_EVENT_ETHSW_PTRN3 = (260), // Ethernet Switch RX Pattern Matcher interrupt 3 + ELC_EVENT_ETHSW_PTRN4 = (261), // Ethernet Switch RX Pattern Matcher interrupt 4 + ELC_EVENT_ETHSW_PTRN5 = (262), // Ethernet Switch RX Pattern Matcher interrupt 5 + ELC_EVENT_ETHSW_PTRN6 = (263), // Ethernet Switch RX Pattern Matcher interrupt 6 + ELC_EVENT_ETHSW_PTRN7 = (264), // Ethernet Switch RX Pattern Matcher interrupt 7 + ELC_EVENT_ETHSW_PTRN8 = (265), // Ethernet Switch RX Pattern Matcher interrupt 8 + ELC_EVENT_ETHSW_PTRN9 = (266), // Ethernet Switch RX Pattern Matcher interrupt 9 + ELC_EVENT_ETHSW_PTRN10 = (267), // Ethernet Switch RX Pattern Matcher interrupt 10 + ELC_EVENT_ETHSW_PTRN11 = (268), // Ethernet Switch RX Pattern Matcher interrupt 11 + ELC_EVENT_ETHSW_PTPOUT0 = (269), // Ethernet switch timer pulse output 0 + ELC_EVENT_ETHSW_PTPOUT1 = (270), // Ethernet switch timer pulse output 1 + ELC_EVENT_ETHSW_PTPOUT2 = (271), // Ethernet switch timer pulse output 2 + ELC_EVENT_ETHSW_PTPOUT3 = (272), // Ethernet switch timer pulse output 3 + ELC_EVENT_ETHSW_TDMAOUT0 = (273), // Ethernet Switch TDMA timer output 0 + ELC_EVENT_ETHSW_TDMAOUT1 = (274), // Ethernet Switch TDMA timer output 1 + ELC_EVENT_ETHSW_TDMAOUT2 = (275), // Ethernet Switch TDMA timer output 2 + ELC_EVENT_ETHSW_TDMAOUT3 = (276), // Ethernet Switch TDMA timer output 3 + ELC_EVENT_ESC_SYNC0 = (277), // EtherCAT Sync0 interrupt + ELC_EVENT_ESC_SYNC1 = (278), // EtherCAT Sync1 interrupt + ELC_EVENT_ESC_CAT = (279), // EtherCAT interrupt + ELC_EVENT_ESC_SOF = (280), // EtherCAT SOF interrupt + ELC_EVENT_ESC_EOF = (281), // EtherCAT EOF interrupt + ELC_EVENT_ESC_WDT = (282), // EtherCAT WDT interrupt + ELC_EVENT_ESC_RST = (283), // EtherCAT RESET interrupt + ELC_EVENT_USB_HI = (284), // USB (Host) interrupt + ELC_EVENT_USB_FI = (285), // USB (Function) interrupt + ELC_EVENT_USB_FDMA0 = (286), // USB (Function) DMA 0 transmit completion + ELC_EVENT_USB_FDMA1 = (287), // USB (Function) DMA 1 transmit completion + ELC_EVENT_SCI0_ERI = (288), // SCI0 Receive error + ELC_EVENT_SCI0_RXI = (289), // SCI0 Receive data full + ELC_EVENT_SCI0_TXI = (290), // SCI0 Transmit data empty + ELC_EVENT_SCI0_TEI = (291), // SCI0 Transmit end + ELC_EVENT_SCI1_ERI = (292), // SCI1 Receive error + ELC_EVENT_SCI1_RXI = (293), // SCI1 Receive data full + ELC_EVENT_SCI1_TXI = (294), // SCI1 Transmit data empty + ELC_EVENT_SCI1_TEI = (295), // SCI1 Transmit end + ELC_EVENT_SCI2_ERI = (296), // SCI2 Receive error + ELC_EVENT_SCI2_RXI = (297), // SCI2 Receive data full + ELC_EVENT_SCI2_TXI = (298), // SCI2 Transmit data empty + ELC_EVENT_SCI2_TEI = (299), // SCI2 Transmit end + ELC_EVENT_SCI3_ERI = (300), // SCI3 Receive error + ELC_EVENT_SCI3_RXI = (301), // SCI3 Receive data full + ELC_EVENT_SCI3_TXI = (302), // SCI3 Transmit data empty + ELC_EVENT_SCI3_TEI = (303), // SCI3 Transmit end + ELC_EVENT_SCI4_ERI = (304), // SCI4 Receive error + ELC_EVENT_SCI4_RXI = (305), // SCI4 Receive data full + ELC_EVENT_SCI4_TXI = (306), // SCI4 Transmit data empty + ELC_EVENT_SCI4_TEI = (307), // SCI4 Transmit end + ELC_EVENT_IIC0_EEI = (308), // IIC0 Transfer error or event generation + ELC_EVENT_IIC0_RXI = (309), // IIC0 Receive data full + ELC_EVENT_IIC0_TXI = (310), // IIC0 Transmit data empty + ELC_EVENT_IIC0_TEI = (311), // IIC0 Transmit end + ELC_EVENT_IIC1_EEI = (312), // IIC1 Transfer error or event generation + ELC_EVENT_IIC1_RXI = (313), // IIC1 Receive data full + ELC_EVENT_IIC1_TXI = (314), // IIC1 Transmit data empty + ELC_EVENT_IIC1_TEI = (315), // IIC1 Transmit end + ELC_EVENT_CAN_RXF = (316), // CANFD RX FIFO interrupt + ELC_EVENT_CAN_GLERR = (317), // CANFD Global error interrupt + ELC_EVENT_CAN0_TX = (318), // CAFND0 Channel TX interrupt + ELC_EVENT_CAN0_CHERR = (319), // CAFND0 Channel CAN error interrupt + ELC_EVENT_CAN0_COMFRX = (320), // CAFND0 Common RX FIFO or TXQ interrupt + ELC_EVENT_CAN1_TX = (321), // CAFND1 Channel TX interrupt + ELC_EVENT_CAN1_CHERR = (322), // CAFND1 Channel CAN error interrupt + ELC_EVENT_CAN1_COMFRX = (323), // CAFND1 Common RX FIFO or TXQ interrupt + ELC_EVENT_SPI0_SPRI = (324), // SPI0 Reception buffer full + ELC_EVENT_SPI0_SPTI = (325), // SPI0 Transmit buffer empty + ELC_EVENT_SPI0_SPII = (326), // SPI0 SPI idle + ELC_EVENT_SPI0_SPEI = (327), // SPI0 errors + ELC_EVENT_SPI0_SPCEND = (328), // SPI0 Communication complete + ELC_EVENT_SPI1_SPRI = (329), // SPI1 Reception buffer full + ELC_EVENT_SPI1_SPTI = (330), // SPI1 Transmit buffer empty + ELC_EVENT_SPI1_SPII = (331), // SPI1 SPI idle + ELC_EVENT_SPI1_SPEI = (332), // SPI1 errors + ELC_EVENT_SPI1_SPCEND = (333), // SPI1 Communication complete + ELC_EVENT_SPI2_SPRI = (334), // SPI2 Reception buffer full + ELC_EVENT_SPI2_SPTI = (335), // SPI2 Transmit buffer empty + ELC_EVENT_SPI2_SPII = (336), // SPI2 SPI idle + ELC_EVENT_SPI2_SPEI = (337), // SPI2 errors + ELC_EVENT_SPI2_SPCEND = (338), // SPI2 Communication complete + ELC_EVENT_XSPI0_INT = (339), // xSPI0 Interrupt + ELC_EVENT_XSPI0_INTERR = (340), // xSPI0 Error interrupt + ELC_EVENT_XSPI1_INT = (341), // xSPI1 Interrupt + ELC_EVENT_XSPI1_INTERR = (342), // xSPI1 Error interrupt + ELC_EVENT_DSMIF0_CDRUI = (343), // DSMIF0 current data register update (ORed ch0 to ch2) + ELC_EVENT_DSMIF1_CDRUI = (344), // DSMIF1 current data register update (ORed ch3 to ch5) + ELC_EVENT_ADC0_ADI = (345), // ADC0 A/D scan end interrupt + ELC_EVENT_ADC0_GBADI = (346), // ADC0 A/D scan end interrupt for Group B + ELC_EVENT_ADC0_GCADI = (347), // ADC0 A/D scan end interrupt for Group C + ELC_EVENT_ADC0_CMPAI = (348), // ADC0 Window A compare match + ELC_EVENT_ADC0_CMPBI = (349), // ADC0 Window B compare match + ELC_EVENT_ADC1_ADI = (350), // ADC1 A/D scan end interrupt + ELC_EVENT_ADC1_GBADI = (351), // ADC1 A/D scan end interrupt for Group B + ELC_EVENT_ADC1_GCADI = (352), // ADC1 A/D scan end interrupt for Group C + ELC_EVENT_ADC1_CMPAI = (353), // ADC1 Window A compare match + ELC_EVENT_ADC1_CMPBI = (354), // ADC1 Window B compare match + ELC_EVENT_ENCIF_INT0 = (372), // ENCIF CH0 Interrupt A + ELC_EVENT_ENCIF_INT1 = (373), // ENCIF CH0 Interrupt B + ELC_EVENT_ENCIF_INT2 = (374), // ENCIF CH0 OUTPUT FIFO Interrupt + ELC_EVENT_ENCIF_INT3 = (375), // ENCIF CH0 INPUT FIFO Interrupt + ELC_EVENT_ENCIF_INT4 = (376), // ENCIF CH1 Interrupt A + ELC_EVENT_ENCIF_INT5 = (377), // ENCIF CH1 Interrupt B + ELC_EVENT_ENCIF_INT6 = (378), // ENCIF CH1 OUTPUT FIFO Interrupt + ELC_EVENT_ENCIF_INT7 = (379), // ENCIF CH1 INPUT FIFO Interrupt + ELC_EVENT_CPU0_ERR0 = (384), // Cortex-R52 CPU0 error event 0 + ELC_EVENT_CPU0_ERR1 = (385), // Cortex-R52 CPU0 error event 1 + ELC_EVENT_CPU1_ERR0 = (386), // Cortex-R52 CPU1 error event 0 + ELC_EVENT_CPU1_ERR1 = (387), // Cortex-R52 CPU1 error event 1 + ELC_EVENT_PERI_ERR0 = (388), // Peripherals error event 0 + ELC_EVENT_PERI_ERR1 = (389), // Peripherals error event 1 + ELC_EVENT_INTCPU6 = (392), // Software interrupt 6 + ELC_EVENT_INTCPU7 = (393), // Software interrupt 7 + ELC_EVENT_IRQ14 = (394), // External pin interrupt 14 + ELC_EVENT_IRQ15 = (395), // External pin interrupt 15 + ELC_EVENT_GPT14_CCMPA = (396), // GPT14 GTCCRA input capture/compare match + ELC_EVENT_GPT14_CCMPB = (397), // GPT14 GTCCRB input capture/compare match + ELC_EVENT_GPT14_CMPC = (398), // GPT14 GTCCRC compare match + ELC_EVENT_GPT14_CMPD = (399), // GPT14 GTCCRD compare match + ELC_EVENT_GPT14_CMPE = (400), // GPT14 GTCCRE compare match + ELC_EVENT_GPT14_CMPF = (401), // GPT14 GTCCRF compare match + ELC_EVENT_GPT14_OVF = (402), // GPT14 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT14_UDF = (403), // GPT14 GTCNT underflow + ELC_EVENT_GPT15_CCMPA = (404), // GPT15 GTCCRA input capture/compare match + ELC_EVENT_GPT15_CCMPB = (405), // GPT15 GTCCRB input capture/compare match + ELC_EVENT_GPT15_CMPC = (406), // GPT15 GTCCRC compare match + ELC_EVENT_GPT15_CMPD = (407), // GPT15 GTCCRD compare match + ELC_EVENT_GPT15_CMPE = (408), // GPT15 GTCCRE compare match + ELC_EVENT_GPT15_CMPF = (409), // GPT15 GTCCRF compare match + ELC_EVENT_GPT15_OVF = (410), // GPT15 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT15_UDF = (411), // GPT15 GTCNT underflow + ELC_EVENT_GPT16_CCMPA = (412), // GPT16 GTCCRA input capture/compare match + ELC_EVENT_GPT16_CCMPB = (413), // GPT16 GTCCRB input capture/compare match + ELC_EVENT_GPT16_CMPC = (414), // GPT16 GTCCRC compare match + ELC_EVENT_GPT16_CMPD = (415), // GPT16 GTCCRD compare match + ELC_EVENT_GPT16_CMPE = (416), // GPT16 GTCCRE compare match + ELC_EVENT_GPT16_CMPF = (417), // GPT16 GTCCRF compare match + ELC_EVENT_GPT16_OVF = (418), // GPT16 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT16_UDF = (419), // GPT16 GTCNT underflow + ELC_EVENT_GPT17_CCMPA = (420), // GPT17 GTCCRA input capture/compare match + ELC_EVENT_GPT17_CCMPB = (421), // GPT17 GTCCRB input capture/compare match + ELC_EVENT_GPT17_CMPC = (422), // GPT17 GTCCRC compare match + ELC_EVENT_GPT17_CMPD = (423), // GPT17 GTCCRD compare match + ELC_EVENT_GPT17_CMPE = (424), // GPT17 GTCCRE compare match + ELC_EVENT_GPT17_CMPF = (425), // GPT17 GTCCRF compare match + ELC_EVENT_GPT17_OVF = (426), // GPT17 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT17_UDF = (427), // GPT17 GTCNT underflow + ELC_EVENT_POEG2_GROUP0 = (428), // POEG group A interrupt for channels in SAFETY + ELC_EVENT_POEG2_GROUP1 = (429), // POEG group B interrupt for channels in SAFETY + ELC_EVENT_POEG2_GROUP2 = (430), // POEG group C interrupt for channels in SAFETY + ELC_EVENT_POEG2_GROUP3 = (431), // POEG group D interrupt for channels in SAFETY + ELC_EVENT_RTC_ALM = (432), // Alarm interrupt + ELC_EVENT_RTC_1S = (433), // 1 second interrupt + ELC_EVENT_RTC_PRD = (434), // Fixed interval interrupt + ELC_EVENT_SCI5_ERI = (435), // SCI5 Receive error + ELC_EVENT_SCI5_RXI = (436), // SCI5 Receive data full + ELC_EVENT_SCI5_TXI = (437), // SCI5 Transmit data empty + ELC_EVENT_SCI5_TEI = (438), // SCI5 Transmit end + ELC_EVENT_IIC2_EEI = (439), // IIC2 Transfer error or event generation + ELC_EVENT_IIC2_RXI = (440), // IIC2 Receive data full + ELC_EVENT_IIC2_TXI = (441), // IIC2 Transmit data empty + ELC_EVENT_IIC2_TEI = (442), // IIC2 Transmit end + ELC_EVENT_SPI3_SPRI = (443), // SPI3 Reception buffer full + ELC_EVENT_SPI3_SPTI = (444), // SPI3 Transmit buffer empty + ELC_EVENT_SPI3_SPII = (445), // SPI3 SPI idle + ELC_EVENT_SPI3_SPEI = (446), // SPI3 errors + ELC_EVENT_SPI3_SPCEND = (447), // SPI3 Communication complete + ELC_EVENT_DREQ = (448), // External DMA request + ELC_EVENT_CAN_RF_DMAREQ0 = (449), // CAFND RX FIFO 0 DMA request + ELC_EVENT_CAN_RF_DMAREQ1 = (450), // CAFND RX FIFO 1 DMA request + ELC_EVENT_CAN_RF_DMAREQ2 = (451), // CAFND RX FIFO 2 DMA request + ELC_EVENT_CAN_RF_DMAREQ3 = (452), // CAFND RX FIFO 3 DMA request + ELC_EVENT_CAN_RF_DMAREQ4 = (453), // CAFND RX FIFO 4 DMA request + ELC_EVENT_CAN_RF_DMAREQ5 = (454), // CAFND RX FIFO 5 DMA request + ELC_EVENT_CAN_RF_DMAREQ6 = (455), // CAFND RX FIFO 6 DMA request + ELC_EVENT_CAN_RF_DMAREQ7 = (456), // CAFND RX FIFO 7 DMA request + ELC_EVENT_CAN0_CF_DMAREQ = (457), // CAFND0 First common FIFO DMA request + ELC_EVENT_CAN1_CF_DMAREQ = (458), // CAFND1 First common FIFO DMA request + ELC_EVENT_ADC0_WCMPM = (459), // ADC0 compare match + ELC_EVENT_ADC0_WCMPUM = (460), // ADC0 compare mismatch + ELC_EVENT_ADC1_WCMPM = (461), // ADC1 compare match + ELC_EVENT_ADC1_WCMPUM = (462), // ADC1 compare mismatch + ELC_EVENT_TCIV4_OF = (463), // MTU4.TCNT overflow + ELC_EVENT_TCIV4_UF = (464), // MTU4.TCNT underflow + ELC_EVENT_TCIV7_OF = (465), // MTU7.TCNT overflow + ELC_EVENT_TCIV7_UF = (466), // MTU7.TCNT underflow + ELC_EVENT_IOPORT_GROUP1 = (467), // Input edge detection of input port group 1 + ELC_EVENT_IOPORT_GROUP2 = (468), // Input edge detection of input port group 2 + ELC_EVENT_IOPORT_SINGLE0 = (469), // Input edge detection of single input port 0 + ELC_EVENT_IOPORT_SINGLE1 = (470), // Input edge detection of single input port 1 + ELC_EVENT_IOPORT_SINGLE2 = (471), // Input edge detection of single input port 2 + ELC_EVENT_IOPORT_SINGLE3 = (472), // Input edge detection of single input port 3 + ELC_EVENT_GPT0_ADTRGA = (473), // GPT0 GTADTRA compare match + ELC_EVENT_GPT0_ADTRGB = (474), // GPT0 GTADTRB compare match + ELC_EVENT_GPT1_ADTRGA = (475), // GPT1 GTADTRA compare match + ELC_EVENT_GPT1_ADTRGB = (476), // GPT1 GTADTRB compare match + ELC_EVENT_GPT2_ADTRGA = (477), // GPT2 GTADTRA compare match + ELC_EVENT_GPT2_ADTRGB = (478), // GPT2 GTADTRB compare match + ELC_EVENT_GPT3_ADTRGA = (479), // GPT3 GTADTRA compare match + ELC_EVENT_GPT3_ADTRGB = (480), // GPT3 GTADTRB compare match + ELC_EVENT_GPT4_ADTRGA = (481), // GPT4 GTADTRA compare match + ELC_EVENT_GPT4_ADTRGB = (482), // GPT4 GTADTRB compare match + ELC_EVENT_GPT5_ADTRGA = (483), // GPT5 GTADTRA compare match + ELC_EVENT_GPT5_ADTRGB = (484), // GPT5 GTADTRB compare match + ELC_EVENT_GPT6_ADTRGA = (485), // GPT6 GTADTRA compare match + ELC_EVENT_GPT6_ADTRGB = (486), // GPT6 GTADTRB compare match + ELC_EVENT_GPT7_ADTRGA = (487), // GPT7 GTADTRA compare match + ELC_EVENT_GPT7_ADTRGB = (488), // GPT7 GTADTRB compare match + ELC_EVENT_GPT8_ADTRGA = (489), // GPT8 GTADTRA compare match + ELC_EVENT_GPT8_ADTRGB = (490), // GPT8 GTADTRB compare match + ELC_EVENT_GPT9_ADTRGA = (491), // GPT9 GTADTRA compare match + ELC_EVENT_GPT9_ADTRGB = (492), // GPT9 GTADTRB compare match + ELC_EVENT_GPT10_ADTRGA = (493), // GPT10 GTADTRA compare match + ELC_EVENT_GPT10_ADTRGB = (494), // GPT10 GTADTRB compare match + ELC_EVENT_GPT11_ADTRGA = (495), // GPT11 GTADTRA compare match + ELC_EVENT_GPT11_ADTRGB = (496), // GPT11 GTADTRB compare match + ELC_EVENT_GPT12_ADTRGA = (497), // GPT12 GTADTRA compare match + ELC_EVENT_GPT12_ADTRGB = (498), // GPT12 GTADTRB compare match + ELC_EVENT_GPT13_ADTRGA = (499), // GPT13 GTADTRA compare match + ELC_EVENT_GPT13_ADTRGB = (500), // GPT13 GTADTRB compare match + ELC_EVENT_NONE +} elc_event_t; + +/** @} (end addtogroup BSP_MCU_RZT2M) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_feature.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_feature.h new file mode 100644 index 00000000000..baa15b885bb --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_feature.h @@ -0,0 +1,264 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKADC) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) +#define BSP_FEATURE_ADC_HAS_PGA (1U) +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (1U) +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_UNIT_NUM (1U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) +#define BSP_FEATURE_ADC_REGISTER_MASK_TYPE (1U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x00000FFFU) +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_SLOPE (4000U) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x00FF) // 0 to 7 in unit 0 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0xFFFF) // 0 to 15 in unit 1 +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) + +#define BSP_FEATURE_BSC_32BIT_DATA_BUS_WIDTH_SUPPORTED (1U) + +#define BSP_FEATURE_BSP_AFMT_UNIT (0U) +#define BSP_FEATURE_BSP_BISS_UNIT (0U) +#define BSP_FEATURE_BSP_CR52_CORE_NUM (2U) +#define BSP_FEATURE_BSP_ENCOUT_SUPPORTED (0U) +#define BSP_FEATURE_BSP_ENDAT_UNIT (0U) +#define BSP_FEATURE_BSP_HDSL_UNIT (0U) +#define BSP_FEATURE_BSP_IRQ_PRIORITY_MASK (0xF8U) +#define BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT (3U) +#define BSP_FEATURE_BSP_MASTER_MPU0_SUPPORTED (1U) +#define BSP_FEATURE_BSP_MASTER_MPU1_SUPPORTED (1U) +#define BSP_FEATURE_BSP_MASTER_MPU2_SUPPORTED (1U) +#define BSP_FEATURE_BSP_MASTER_MPU3_SUPPORTED (1U) +#define BSP_FEATURE_BSP_MASTER_MPU4_SUPPORTED (1U) +#define BSP_FEATURE_BSP_MASTER_MPU6_SUPPORTED (1U) +#define BSP_FEATURE_BSP_MASTER_MPU7_SUPPORTED (0U) +#define BSP_FEATURE_BSP_MSTP_CR52_CPU1_HAS_MSTPCRH (1U) +#define BSP_FEATURE_BSP_SEMAPHORE_SUPPORTED (1U) +#define BSP_FEATURE_BSP_SHOSTIF_SUPPORTED (0U) + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) +#define BSP_FEATURE_CAN_CLOCK (0U) +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) +#define BSP_FEATURE_CAN_NUM_CHANNELS (2U) + +#define BSP_FEATURE_CANFD_NUM_CHANNELS (2U) + +#define BSP_FEATURE_CGC_HAS_BCLK (1U) +#define BSP_FEATURE_CGC_HAS_FCLK (1U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) +#define BSP_FEATURE_CGC_HAS_FLWT (1U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_PCLKA (1U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (1U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PLL (1U) +#define BSP_FEATURE_CGC_HAS_PLL2 (0U) +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) +#define BSP_FEATURE_CGC_LOCO_CONTROL_ADDRESS (0x81280070U) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) +#define BSP_FEATURE_CGC_MODRV_MASK (0x30U) +#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U) +#define BSP_FEATURE_CGC_PLL1_CONTROL_ADDRESS (0x81280050U) +#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP + +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) +#define BSP_FEATURE_CGC_SODRV_MASK (0x02U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0U) + +#define BSP_FEATURE_CMT_VALID_CHANNEL_MASK (0x3FU) + +#define BSP_FEATURE_CMTW_VALID_CHANNEL_MASK (0x3U) + +#define BSP_FEATURE_CRC_VALID_CHANNEL_MASK (0x3U) + +#define BSP_FEATURE_DMAC_MAX_CHANNEL (16U) +#define BSP_FEATURE_DMAC_MAX_UNIT (2U) +#define BSP_FEATURE_DMAC_UNIT0_ERROR_NUM (5U) + +#define BSP_FEATURE_DSMIF_CHANNEL_STATUS (1U) +#define BSP_FEATURE_DSMIF_DATA_FORMAT_SEL (0U) +#define BSP_FEATURE_DSMIF_ERROR_STATUS_CLR (5U) +#define BSP_FEATURE_DSMIF_OVERCURRENT_DETECT_CONTROL (1U) +#define BSP_FEATURE_DSMIF_OVERCURRENT_DETECT_ISR (1U) +#define BSP_FEATURE_DSMIF_OVERCURRENT_DETECT_NOTIFY (0U) +#define BSP_FEATURE_DSMIF_OVERCURRENT_ERROR_STATUS (1U) +#define BSP_FEATURE_DSMIF_OVERCURRENT_NOTIFY_STATUS (0U) +#define BSP_FEATURE_DSMIF_VERSION (1U) + +#define BSP_FEATURE_ELC_ELC_SSEL_NUM (19) +#define BSP_FEATURE_ELC_EVENT_MASK_NUM (4U) +#define BSP_FEATURE_ELC_PERIPHERAL_0_MASK (0xFFFFFFFFU) // ELC event source no.0 to 31 available on this MCU +#define BSP_FEATURE_ELC_PERIPHERAL_1_MASK (0x007FFFFFU) // ELC event source no.32 to 63 available on this MCU. +#define BSP_FEATURE_ELC_PERIPHERAL_2_MASK (0x00000000U) // ELC event source no.64 to 95 available on this MCU. +#define BSP_FEATURE_ELC_PERIPHERAL_3_MASK (0x00000000U) // ELC event source no.96 to 127 available on this MCU. +#define BSP_FEATURE_ELC_PERIPHERAL_TYPE (1U) + +#define BSP_FEATURE_ESC_MAX_PORTS (3U) +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) +#define BSP_FEATURE_ETHER_PHY_MAX_CHANNELS (3U) +#define BSP_FEATURE_ETHSS_SWITCH_MODE_BIT_MASK (3U) +#define BSP_FEATURE_ETHSS_MAX_PORTS (3U) +#define BSP_FEATURE_ETHSW_MAX_CHANNELS (1U) +#define BSP_FEATURE_ETHSW_SUPPORTED (1U) +#define BSP_FEATURE_GMAC_MAX_CHANNELS (1U) +#define BSP_FEATURE_GMAC_MAX_PORTS (3U) + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3FFFF) +#define BSP_FEATURE_GPT_LLPP_BASE_CHANNEL (0) // LLPP channel: ch0-6 +#define BSP_FEATURE_GPT_LLPP_CHANNEL_MASK (0x0007F) +#define BSP_FEATURE_GPT_NONSAFETY_BASE_CHANNEL (7) // Non-safety channel: ch7-13 +#define BSP_FEATURE_GPT_NONSAFETY_CHANNEL_MASK (0x0007F) +#define BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL (14) // safety channel: ch14-17 +#define BSP_FEATURE_GPT_SAFETY_CHANNEL_MASK (0x0000F) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFFF) +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0xF0) +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0xF) + +#define BSP_FEATURE_ICU_ERROR_CR52_CPU1_SUPPORTED (1U) +#define BSP_FEATURE_ICU_ERROR_PERI_ERR_REG_NUM (2U) +#define BSP_FEATURE_ICU_ERROR_PERI_ERR0_REG_MASK (0xFFFFFFFFU) +#define BSP_FEATURE_ICU_ERROR_PERI_ERR1_REG_MASK (0x19FFFFFFU) +#define BSP_FEATURE_ICU_ERROR_PERI_ERR2_REG_MASK (0x00000000U) +#define BSP_FEATURE_ICU_ERROR_PERI_ERR3_REG_MASK (0x00000000U) +#define BSP_FEATURE_ICU_ERROR_PERIPHERAL_TYPE (1U) +#define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) +#define BSP_FEATURE_ICU_INTER_CPU_IRQ_CHANNEL (1U) +#define BSP_FEATURE_ICU_INTER_CPU_IRQ_CHANNELS_MASK (0xFFU) +#define BSP_FEATURE_ICU_INTER_CPU_IRQ_NS_SWINT_MASK (0x0000003FU) // Non-safety channel: ch0-5 (bit0-5) +#define BSP_FEATURE_ICU_INTER_CPU_IRQ_S_SWINT_MASK (0x000000C0U) // Safety channel: ch6-7 (bit6-7) +#define BSP_FEATURE_ICU_INTER_CPU_IRQ_S_SWINT_SHIFT (6U) +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0xFF4FFFFFU) + +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) +#define BSP_FEATURE_IIC_SAFETY_CHANNEL (2U) +#define BSP_FEATURE_IIC_SAFETY_CHANNEL_BASE_ADDRESS (R_IIC2_BASE) +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07) + +#define BSP_FEATURE_IOPORT_ELC_PORTS (4U) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) +#define BSP_FEATURE_IOPORT_PIN_PFC_TYPE (1U) + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {{0, 15}, {0, 13}, {1, 31}, {1, 6}, {1, 5}, {1, 4}, {2, 5}} +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (1U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00137FFFU) +#define BSP_FEATURE_LPM_DPSIER_MASK (0x071F7FFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) +#define BSP_FEATURE_LPM_HAS_STCONR (1U) +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0U) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) + +#define BSP_FEATURE_MAILBOX_SEM_SUPPORTED (0U) + +#define BSP_FEATURE_MTU3_MAX_CHANNELS (9U) +#define BSP_FEATURE_MTU3_UVW_MAX_CHANNELS (3U) +#define BSP_FEATURE_MTU3_VALID_CHANNEL_MASK (0x01FF) + +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) + +#define BSP_FEATURE_POE3_ERROR_SIGNAL_TYPE (1U) +#define BSP_FEATURE_POE3_PIN_SELECT_TYPE (1U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) +#define BSP_FEATURE_POEG_ERROR_SIGNAL_TYPE (1U) +#define BSP_FEATURE_POEG_GROUP_OFSSET_ADDRESS (0x400) +#define BSP_FEATURE_POEG_LLPP_UNIT (0U) +#define BSP_FEATURE_POEG_MAX_UNIT (2U) +#define BSP_FEATURE_POEG_NONSAFETY_UNIT (1U) +#define BSP_FEATURE_POEG_SAFETY_UNIT (2U) + +#define BSP_FEATURE_SEM_SUPPORTED (1U) + +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) +#define BSP_FEATURE_SCI_CHANNELS (0x3FU) +#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03FU) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3FFU) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) +#define BSP_FEATURE_SCI_SAFETY_CHANNEL (5U) +#define BSP_FEATURE_SCI_SAFETY_CHANNEL_BASE_ADDRESS (R_SCI5_BASE) + +#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) +#define BSP_FEATURE_SPI_HAS_SPCR3 (0U) +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (4U) +#define BSP_FEATURE_SPI_SAFETY_CHANNEL (3U) +#define BSP_FEATURE_SPI_SAFETY_CHANNEL_BASE_ADDRESS (R_SPI3_BASE) + +#define BSP_FEATURE_TFU_SUPPORTED (1U) + +#define BSP_FEATURE_XSPI_CHANNELS (0x03U) +#define BSP_FEATURE_XSPI_NUM_CHIP_SELECT (2U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_irq_sense.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_irq_sense.c new file mode 100644 index 00000000000..312fe76d2ba --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_irq_sense.c @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RZT2M + * @{ + **********************************************************************************************************************/ + +/** Array of GICD_ICFGR initialization value. */ +const uint32_t BSP_GICD_ICFGR_INIT[BSP_NON_SELECTABLE_ICFGR_MAX] = +{ + 0xAAAAAAAAUL, /* Event No. 0 to 15 */ + 0x000000AAUL, /* Event No. 16 to 31 */ + 0x00000000UL, /* Event No. 32 to 47 */ + 0xAAAAA800UL, /* Event No. 48 to 63 */ + 0xAAAAAAAAUL, /* Event No. 64 to 79 */ + 0xAAAAAAAAUL, /* Event No. 80 to 95 */ + 0xAAAAAAAAUL, /* Event No. 96 to 111 */ + 0xAAAAAA00UL, /* Event No. 112 to 127 */ + 0xAAAAAAAAUL, /* Event No. 128 to 143 */ + 0xAAAAAAAAUL, /* Event No. 144 to 159 */ + 0xAAAAAAAAUL, /* Event No. 160 to 175 */ + 0xAAAAAAAAUL, /* Event No. 176 to 191 */ + 0xAAAAAAAAUL, /* Event No. 192 to 207 */ + 0xAAAAAAAAUL, /* Event No. 208 to 223 */ + 0xAAAAAAAAUL, /* Event No. 224 to 239 */ + 0x0000000AUL, /* Event No. 240 to 255 */ + 0xA8000000UL, /* Event No. 256 to 271 */ + 0xA82A2AAAUL, /* Event No. 272 to 287 */ + 0x28282828UL, /* Event No. 288 to 303 */ + 0x00282828UL, /* Event No. 304 to 319 */ + 0xA82A0A00UL, /* Event No. 320 to 335 */ + 0xA0AA8020UL, /* Event No. 336 to 351 */ + 0x00000002UL, /* Event No. 352 to 367 */ + 0x00000000UL, /* Event No. 368 to 383 */ + 0xAAAA0AAAUL, /* Event No. 384 to 399 */ + 0xAAAAAAAAUL, /* Event No. 400 to 415 */ + 0x00AAAAAAUL, /* Event No. 416 to 431 */ + 0x828A0A2AUL, /* Event No. 432 to 447 */ +}; + +const uint32_t BSP_GICR_SGI_PPI_ICFGR_INIT[BSP_EVENT_SGI_PPI_ARRAY_NUM] = +{ + 0xAAAAAAAAUL, /* event SGI */ + 0x00020000UL, /* event PPI */ +}; + +/** @} (end addtogroup BSP_MCU_RZT2M) */ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_loader_param.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_loader_param.c new file mode 100644 index 00000000000..e0600c134b2 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_loader_param.c @@ -0,0 +1,71 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if !(BSP_CFG_RAM_EXECUTION) + #if (1 == _RZT_ORDINAL) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + #define BSP_LOADER_PARAM_MAX (19) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* Parameter Information for the Loader. */ +BSP_DONT_REMOVE const uint32_t g_bsp_loader_param[BSP_LOADER_PARAM_MAX] BSP_PLACE_IN_SECTION(BSP_SECTION_LOADER_PARAM) = +{ + BSP_CFG_CACHE_FLG, + BSP_CFG_CS0BCR_V_WRAPCFG_V, + BSP_CFG_CS0WCR_V_COMCFG_V, + BSP_CFG_DUMMY0_BMCFG_V, + BSP_CFG_BSC_FLG_xSPI_FLG, + BSP_CFG_LDR_ADDR_NML, + BSP_CFG_LDR_SIZE_NML, + BSP_CFG_DEST_ADDR_NML, + BSP_CFG_DUMMY1, + BSP_CFG_DUMMY2, + BSP_CFG_DUMMY3_CSSCTL_V, + BSP_CFG_DUMMY4_LIOCFGCS0_V, + BSP_CFG_DUMMY5, + BSP_CFG_DUMMY6, + BSP_CFG_DUMMY7, + BSP_CFG_DUMMY8, + BSP_CFG_DUMMY9, + BSP_CFG_DUMMY10_ACCESS_SPEED, + BSP_CFG_CHECK_SUM +}; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + + #endif +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_mcu_info.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_mcu_info.h new file mode 100644 index 00000000000..f0669eb268a --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_mcu_info.h @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RZT2M RZT2M + * @includedoc config_bsp_rzt2m_fsp.html + * @{ + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_MCU_RZT2M) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_feature.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_override.h b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_override.h new file mode 100644 index 00000000000..3618e717fd6 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/mcu/rzt2m/bsp_override.h @@ -0,0 +1,1608 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RZT2M + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU_RZT2M) */ + +#ifndef BSP_OVERRIDE_H +#define BSP_OVERRIDE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Common Includes. */ +#include "../../src/bsp/mcu/all/bsp_common.h" + +/* BSP MPU Specific Includes. */ +#include "../../src/bsp/mcu/all/bsp_register_protection.h" +#include "../../src/bsp/mcu/all/bsp_irq.h" +#include "../../src/bsp/mcu/all/bsp_io.h" +#include "../../src/bsp/mcu/all/bsp_clocks.h" +#include "../../src/bsp/mcu/all/bsp_module_stop.h" +#include "../../src/bsp/mcu/all/bsp_semaphore.h" +#include "../../src/bsp/mcu/all/bsp_reset.h" +#include "../../src/bsp/mcu/all/bsp_cache.h" + +/* Factory MPU information. */ +#include "../../inc/fsp_features.h" + +/* BSP Common Includes (Other than bsp_common.h) */ +#include "../../src/bsp/mcu/all/bsp_delay.h" +#include "../../src/bsp/mcu/all/bsp_mcu_api.h" + +/* BSP TFU Includes. */ +#if BSP_FEATURE_TFU_SUPPORTED + #include "../../src/bsp/mcu/all/bsp_tfu.h" +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Define overrides required for this MPU. */ +#define BSP_OVERRIDE_ADC_MODE_T +#define BSP_OVERRIDE_ADC_CHANNEL_T +#define BSP_OVERRIDE_CGC_CLOCK_T +#define BSP_OVERRIDE_CGC_PLL_CFG_T +#define BSP_OVERRIDE_CGC_DIVIDER_CFG_T +#define BSP_OVERRIDE_CGC_CLOCK_CHANGE_T +#define BSP_OVERRIDE_CGC_CLOCKS_CFG_T +#define BSP_OVERRIDE_ELC_PERIPHERAL_T +#define BSP_OVERRIDE_ETHER_EVENT_T +#define BSP_OVERRIDE_ETHER_CALLBACK_ARGS_T +#define BSP_OVERRIDE_ETHER_PHY_LSI_TYPE_T +#define BSP_OVERRIDE_ETHER_SWITCH_CALLBACK_ARGS_T +#define BSP_OVERRIDE_POE3_STATE_T +#define BSP_OVERRIDE_POEG_STATE_T +#define BSP_OVERRIDE_POEG_TRIGGER_T +#define BSP_OVERRIDE_TRANSFER_MODE_T +#define BSP_OVERRIDE_TRANSFER_SIZE_T +#define BSP_OVERRIDE_TRANSFER_ADDR_MODE_T +#define BSP_OVERRIDE_TRANSFER_CALLBACK_ARGS_T +#define BSP_OVERRIDE_TRANSFER_INFO_T + +/* Override definitions. */ + +#define ELC_PERIPHERAL_NUM (55U) + +/* Private definition to set enumeration values. */ +#define IOPORT_P_OFFSET (0U) +#define IOPORT_PM_OFFSET (1U) +#define IOPORT_PMC_OFFSET (3U) +#define IOPORT_PFC_OFFSET (4U) +#define IOPORT_DRCTL_OFFSET (8U) +#define IOPORT_RSELP_OFFSET (14U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*============================================== + * ADC API Overrides + *==============================================*/ + +/** ADC operation mode definitions */ +typedef enum e_adc_mode +{ + ADC_MODE_SINGLE_SCAN = 0, ///< Single scan - one or more channels + ADC_MODE_GROUP_SCAN = 1, ///< Two trigger sources to trigger scan for two groups which contain one or more channels + ADC_MODE_CONTINUOUS_SCAN = 2, ///< Continuous scan - one or more channels + ADC_MODE_SYNCHRONIZE_SCAN = 3, ///< Channel synchronization control mode + ADC_MODE_INDIVIDUAL_SCAN = 4, ///< Channel individual control mode +} adc_mode_t; + +/** ADC channels */ +typedef enum e_adc_channel +{ + ADC_CHANNEL_0 = 0, ///< ADC channel 0 + ADC_CHANNEL_1 = 1, ///< ADC channel 1 + ADC_CHANNEL_2 = 2, ///< ADC channel 2 + ADC_CHANNEL_3 = 3, ///< ADC channel 3 + ADC_CHANNEL_4 = 4, ///< ADC channel 4 + ADC_CHANNEL_5 = 5, ///< ADC channel 5 + ADC_CHANNEL_6 = 6, ///< ADC channel 6 + ADC_CHANNEL_7 = 7, ///< ADC channel 7 + ADC_CHANNEL_8 = 8, ///< ADC channel 8 + ADC_CHANNEL_9 = 9, ///< ADC channel 9 + ADC_CHANNEL_10 = 10, ///< ADC channel 10 + ADC_CHANNEL_11 = 11, ///< ADC channel 11 + ADC_CHANNEL_12 = 12, ///< ADC channel 12 + ADC_CHANNEL_13 = 13, ///< ADC channel 13 + ADC_CHANNEL_14 = 14, ///< ADC channel 14 + ADC_CHANNEL_15 = 15, ///< ADC channel 15 + ADC_CHANNEL_16 = 16, ///< ADC channel 16 + ADC_CHANNEL_17 = 17, ///< ADC channel 17 + ADC_CHANNEL_18 = 18, ///< ADC channel 18 + ADC_CHANNEL_19 = 19, ///< ADC channel 19 + ADC_CHANNEL_20 = 20, ///< ADC channel 20 + ADC_CHANNEL_21 = 21, ///< ADC channel 21 + ADC_CHANNEL_22 = 22, ///< ADC channel 22 + ADC_CHANNEL_23 = 23, ///< ADC channel 23 + ADC_CHANNEL_24 = 24, ///< ADC channel 24 + ADC_CHANNEL_25 = 25, ///< ADC channel 25 + ADC_CHANNEL_26 = 26, ///< ADC channel 26 + ADC_CHANNEL_27 = 27, ///< ADC channel 27 + ADC_CHANNEL_28 = 28, ///< ADC channel 28 + ADC_CHANNEL_DUPLEX_A = 50, ///< Data duplexing register A + ADC_CHANNEL_DUPLEX_B = 51, ///< Data duplexing register B + ADC_CHANNEL_DUPLEX = -4, ///< Data duplexing register + ADC_CHANNEL_TEMPERATURE = -3, ///< Temperature sensor output + ADC_CHANNEL_VOLT = -2, ///< Internal reference voltage + ADC_CHANNEL_0_DSMIF_CAPTURE_A = 0x100, ///< ADC channel 0 Capture Current Data Register A + ADC_CHANNEL_0_DSMIF_CAPTURE_B = 0x200, ///< ADC channel 0 Capture Current Data Register B + ADC_CHANNEL_1_DSMIF_CAPTURE_A = 0x101, ///< ADC channel 1 Capture Current Data Register A + ADC_CHANNEL_1_DSMIF_CAPTURE_B = 0x201, ///< ADC channel 1 Capture Current Data Register B + ADC_CHANNEL_2_DSMIF_CAPTURE_A = 0x102, ///< ADC channel 2 Capture Current Data Register A + ADC_CHANNEL_2_DSMIF_CAPTURE_B = 0x202, ///< ADC channel 2 Capture Current Data Register B +} adc_channel_t; + +/*============================================== + * CGC API Overrides + *==============================================*/ + +/** Divider values of clock provided to xSPI */ +typedef enum e_cgc_fsel_xspi_clock_div +{ + CGC_FSEL_XSPI_CLOCK_DIV_6 = 0x02, ///< XSPI_CLKn 133.3MHz (XSPI base clock divided by 3) + CGC_FSEL_XSPI_CLOCK_DIV_8 = 0x03, ///< XSPI_CLKn 100.0MHz / 75.0MHz (XSPI base clock divided by 3 / divided by 4) + CGC_FSEL_XSPI_CLOCK_DIV_16 = 0x04, ///< XSPI_CLKn 50.0MHz / 37.5MHz (XSPI base clock divided by 3 / divided by 4) + CGC_FSEL_XSPI_CLOCK_DIV_32 = 0x05, ///< XSPI_CLKn 25.0MHz (XSPI base clock divided by 3) + CGC_FSEL_XSPI_CLOCK_DIV_64 = 0x06, ///< XSPI_CLKn 12.5MHz (XSPI base clock divided by 3) +} cgc_fsel_xspi_clock_div_t; + +/** Divider values of base clock generated for xSPI */ +typedef enum e_cgc_divsel_xspi_clock_div +{ + CGC_DIVSEL_XSPI_CLOCK_DIV_3 = 0x00, ///< XSPI base clock divided by 3 + CGC_DIVSEL_XSPI_CLOCK_DIV_4 = 0x01, ///< XSPI base clock divided by 4 +} cgc_divsel_xspi_clock_div_t; + +/** Clock output divider values */ +typedef enum e_cgc_clock_out_clock_div +{ + CGC_CLOCK_OUT_CLOCK_DIV_2 = 0, ///< CKIO 100.0MHz / 75.0MHz (Base clock divided by 3 / divided by 4) + CGC_CLOCK_OUT_CLOCK_DIV_3 = 1, ///< CKIO 66.7MHz / 50.0MHz (Base clock divided by 3 / divided by 4) + CGC_CLOCK_OUT_CLOCK_DIV_4 = 2, ///< CKIO 50.0MHz / 37.5MHz (Base clock divided by 3 / divided by 4) + CGC_CLOCK_OUT_CLOCK_DIV_5 = 3, ///< CKIO 40.0MHz / 30.0MHz (Base clock divided by 3 / divided by 4) + CGC_CLOCK_OUT_CLOCK_DIV_6 = 4, ///< CKIO 33.3MHz / 25.0MHz (Base clock divided by 3 / divided by 4) + CGC_CLOCK_OUT_CLOCK_DIV_7 = 5, ///< CKIO 28.6MHz / 21.4MHz (Base clock divided by 3 / divided by 4) + CGC_CLOCK_OUT_CLOCK_DIV_8 = 6, ///< CKIO 25.0MHz / 18.75MHz (Base clock divided by 3 / divided by 4) +} cgc_clock_out_clock_div_t; + +/** CANFD clock divider values */ +typedef enum e_cgc_canfd_clock_div +{ + CGC_CANFD_CLOCK_DIV_10 = 0, ///< CANFD clock 80.0MHz + CGC_CANFD_CLOCK_DIV_20 = 1, ///< CANFD clock 40.0MHz +} cgc_canfd_clock_div_t; + +/** PHY clock source identifiers */ +typedef enum e_cgc_phy_clock +{ + CGC_PHY_CLOCK_PLL1 = 0, ///< PLL1 divider clock + CGC_PHY_CLOCK_MAIN_OSC = 1, ///< Main clock oscillator +} cgc_phy_clock_t; + +/** SPI asynchronous serial clock frequency */ +typedef enum e_cgc_spi_async_clock +{ + CGC_SPI_ASYNC_CLOCK_75MHZ = 0, ///< SPI asynchronous serial clock 75MHz + CGC_SPI_ASYNC_CLOCK_96MHZ = 1, ///< SPI asynchronous serial clock 96MHz +} cgc_spi_async_clock_t; + +/** SCI asynchronous serial clock frequency */ +typedef enum e_cgc_sci_async_clock +{ + CGC_SCI_ASYNC_CLOCK_75MHZ = 0, ///< SCI asynchronous serial clock 75MHz + CGC_SCI_ASYNC_CLOCK_96MHZ = 1, ///< SCI asynchronous serial clock 96MHz +} cgc_sci_async_clock_t; + +/** CPU clock divider values */ +typedef enum e_cgc_cpu_clock_div +{ + CGC_CPU_CLOCK_DIV_1 = 0, ///< CPU 800.0MHz / 600.0MHz (Base clock divided by 3 / divided by 4) + CGC_CPU_CLOCK_DIV_2 = 1, ///< CPU 400.0MHz / 300.0MHz (Base clock divided by 3 / divided by 4) + CGC_CPU_CLOCK_DIV_4 = 2, ///< CPU 200.0MHz / 150.0MHz (Base clock divided by 3 / divided by 4) +} cgc_cpu_clock_div_t; + +/** Base clock divider values */ +typedef enum e_cgc_baseclock_div +{ + CGC_BASECLOCK_DIV_3 = 0, ///< Base clock divided by 3 (ICLK=200.0MHz etc.) + CGC_BASECLOCK_DIV_4 = 1, ///< Base clock divided by 4 (ICLK=150.0MHz etc.) +} cgc_baseclock_div_t; + +/** System clock source identifiers */ +typedef enum e_cgc_clock +{ + CGC_CLOCK_LOCO = 0, ///< The low speed on chip oscillator + CGC_CLOCK_PLL0 = 1, ///< The PLL0 oscillator + CGC_CLOCK_PLL1 = 2, ///< The PLL1 oscillator +} cgc_clock_t; + +/** Clock configuration structure - Dummy definition because it is not used in this MPU. + * Set NULL as an input parameter to the @ref cgc_api_t::clockStart function for the PLL clock. */ +typedef struct st_cgc_pll_cfg +{ + uint32_t dummy; /* Dummy. */ +} cgc_pll_cfg_t; + +/** Clock configuration structure */ +typedef struct st_cgc_divider_cfg +{ + union + { + uint32_t sckcr_w; ///< System Clock Control Register + + struct + { + cgc_fsel_xspi_clock_div_t fselxspi0 : 3; ///< Divider value for XSPI_CLK0 + uint32_t : 3; + cgc_divsel_xspi_clock_div_t divselxspi0 : 1; ///< Divider base value for XSPI_CLK0 + uint32_t : 1; + cgc_fsel_xspi_clock_div_t fselxspi1 : 3; ///< Divider value for XSPI_CLK1 + uint32_t : 3; + cgc_divsel_xspi_clock_div_t divselxspi1 : 1; ///< Divider base value for XSPI_CLK1 + uint32_t : 1; + cgc_clock_out_clock_div_t ckio_div : 3; ///< Divider value for CKIO + uint32_t : 1; + cgc_canfd_clock_div_t fselcanfd_div : 1; ///< Divider value for CANFD clock + cgc_phy_clock_t phy_sel : 1; ///< Ethernet PHY reference clock output + uint32_t : 2; + cgc_spi_async_clock_t spi0_async_sel : 1; ///< SPI0 asynchronous serial clock + cgc_spi_async_clock_t spi1_async_sel : 1; ///< SPI1 asynchronous serial clock + cgc_spi_async_clock_t spi2_async_sel : 1; ///< SPI2 asynchronous serial clock + cgc_sci_async_clock_t sci0_async_sel : 1; ///< SCI0 asynchronous serial clock + cgc_sci_async_clock_t sci1_async_sel : 1; ///< SCI1 asynchronous serial clock + cgc_sci_async_clock_t sci2_async_sel : 1; ///< SCI2 asynchronous serial clock + cgc_sci_async_clock_t sci3_async_sel : 1; ///< SCI3 asynchronous serial clock + cgc_sci_async_clock_t sci4_async_sel : 1; ///< SCI4 asynchronous serial clock + } sckcr_b; + }; + + union + { + uint32_t sckcr2_w; ///< System Clock Control Register 2 + + struct + { + cgc_cpu_clock_div_t fsel0cr52 : 2; ///< Divider value for Cortex-R52 CPU0 + cgc_cpu_clock_div_t fsel1cr52 : 2; ///< Divider value for Cortex-R52 CPU1 + uint32_t : 1; + cgc_baseclock_div_t div_sub_sel : 1; ///< Divider value for base clock + uint32_t : 18; + cgc_spi_async_clock_t spi3_async_sel : 1; ///< SPI3 asynchronous serial clock + cgc_sci_async_clock_t sci5_async_sel : 1; ///< SCI5 asynchronous serial clock + uint32_t : 6; + } sckcr2_b; + }; +} cgc_divider_cfg_t; + +/** Clock options */ +typedef enum e_cgc_clock_change +{ + CGC_CLOCK_CHANGE_START = 0, ///< Start the clock + CGC_CLOCK_CHANGE_STOP = 1, ///< Stop the clock + CGC_CLOCK_CHANGE_NONE = 2, ///< No change to the clock +} cgc_clock_change_t; + +/** Clock configuration */ +typedef struct st_cgc_clocks_cfg +{ + cgc_divider_cfg_t divider_cfg; ///< Clock dividers structure + cgc_clock_change_t loco_state; ///< State of LOCO + cgc_clock_change_t pll1_state; ///< State of PLL1 +} cgc_clocks_cfg_t; + +/*============================================== + * ELC API Overrides + *==============================================*/ + +/** Possible peripherals to be linked to event signals (not all available on all MPUs) */ +typedef enum e_elc_peripheral +{ + ELC_PERIPHERAL_MTU0 = (0), + ELC_PERIPHERAL_MTU3 = (1), + ELC_PERIPHERAL_MTU4 = (2), + ELC_PERIPHERAL_LLPPGPT_A = (3), + ELC_PERIPHERAL_LLPPGPT_B = (4), + ELC_PERIPHERAL_LLPPGPT_C = (5), + ELC_PERIPHERAL_LLPPGPT_D = (6), + ELC_PERIPHERAL_LLPPGPT_E = (7), + ELC_PERIPHERAL_LLPPGPT_F = (8), + ELC_PERIPHERAL_LLPPGPT_G = (9), + ELC_PERIPHERAL_LLPPGPT_H = (10), + ELC_PERIPHERAL_NONSAFTYGPT_A = (11), + ELC_PERIPHERAL_NONSAFTYGPT_B = (12), + ELC_PERIPHERAL_NONSAFTYGPT_C = (13), + ELC_PERIPHERAL_NONSAFTYGPT_D = (14), + ELC_PERIPHERAL_NONSAFTYGPT_E = (15), + ELC_PERIPHERAL_NONSAFTYGPT_F = (16), + ELC_PERIPHERAL_NONSAFTYGPT_G = (17), + ELC_PERIPHERAL_NONSAFTYGPT_H = (18), + ELC_PERIPHERAL_ADC0_A = (19), + ELC_PERIPHERAL_ADC0_B = (20), + ELC_PERIPHERAL_ADC1_A = (21), + ELC_PERIPHERAL_ADC1_B = (22), + ELC_PERIPHERAL_DSMIF0_CAP0 = (23), + ELC_PERIPHERAL_DSMIF0_CAP1 = (24), + ELC_PERIPHERAL_DSMIF0_CAP2 = (25), + ELC_PERIPHERAL_DSMIF0_CAP3 = (26), + ELC_PERIPHERAL_DSMIF0_CAP4 = (27), + ELC_PERIPHERAL_DSMIF0_CAP5 = (28), + ELC_PERIPHERAL_DSMIF0_CDCNT0 = (29), + ELC_PERIPHERAL_DSMIF0_CDCNT1 = (30), + ELC_PERIPHERAL_DSMIF0_CDCNT2 = (31), + ELC_PERIPHERAL_DSMIF1_CAP0 = (32), + ELC_PERIPHERAL_DSMIF1_CAP1 = (33), + ELC_PERIPHERAL_DSMIF1_CAP2 = (34), + ELC_PERIPHERAL_DSMIF1_CAP3 = (35), + ELC_PERIPHERAL_DSMIF1_CAP4 = (36), + ELC_PERIPHERAL_DSMIF1_CAP5 = (37), + ELC_PERIPHERAL_DSMIF1_CDCNT0 = (38), + ELC_PERIPHERAL_DSMIF1_CDCNT1 = (39), + ELC_PERIPHERAL_DSMIF1_CDCNT2 = (40), + ELC_PERIPHERAL_ENCIF_TRG0 = (41), + ELC_PERIPHERAL_ENCIF_TRG1 = (42), + ELC_PERIPHERAL_ESC0 = (43), + ELC_PERIPHERAL_ESC1 = (44), + ELC_PERIPHERAL_GMA0 = (45), + ELC_PERIPHERAL_GMA1 = (46), + ELC_PERIPHERAL_OUTPORTGR1 = (47), + ELC_PERIPHERAL_OUTPORTGR2 = (48), + ELC_PERIPHERAL_INPORTGR1 = (49), + ELC_PERIPHERAL_INPORTGR2 = (50), + ELC_PERIPHERAL_SINGLEPORT0 = (51), + ELC_PERIPHERAL_SINGLEPORT1 = (52), + ELC_PERIPHERAL_SINGLEPORT2 = (53), + ELC_PERIPHERAL_SINGLEPORT3 = (54), +} elc_peripheral_t; + +/*============================================== + * ETHER API Overrides + *==============================================*/ + +/** Event code of callback function */ +typedef enum e_ether_event +{ + ETHER_EVENT_WAKEON_LAN, ///< Magic packet detection event + ETHER_EVENT_LINK_ON, ///< Link up detection event + ETHER_EVENT_LINK_OFF, ///< Link down detection event + ETHER_EVENT_SBD_INTERRUPT, ///< SBD Interrupt event + ETHER_EVENT_PMT_INTERRUPT ///< PMT Interrupt event +} ether_event_t; + +/** Ether Callback function parameter data */ +typedef struct st_ether_callback_args +{ + uint32_t channel; ///< Device channel number + ether_event_t event; ///< Event code + + uint32_t status_ether; ///< Interrupt status of SDB or PMT + uint32_t status_link; ///< Link status + + void const * p_context; ///< Placeholder for user data. +} ether_callback_args_t; + +/*============================================== + * ETHER PHY API Overrides + *==============================================*/ + +/** Phy LSI */ +typedef enum e_ether_phy_lsi_type +{ + ETHER_PHY_LSI_TYPE_DEFAULT = 0, ///< Select default configuration. This type dose not change Phy LSI default setting by strapping option. + ETHER_PHY_LSI_TYPE_VSC8541 = 1, ///< Select configuration forVSC8541 + ETHER_PHY_LSI_TYPE_KSZ9131 = 2, ///< Select configuration forKSZ9131 + ETHER_PHY_LSI_TYPE_KSZ9031 = 3, ///< Select configuration forKSZ9031 + ETHER_PHY_LSI_TYPE_KSZ8081 = 4, ///< Select configuration forKSZ8081 + ETHER_PHY_LSI_TYPE_KSZ8041 = 5, ///< Select configuration forKSZ8041 + ETHER_PHY_LSI_TYPE_CUSTOM = 0xFFU, ///< Select configuration for User custom. +} ether_phy_lsi_type_t; + +/*============================================== + * ETHER SWITCH API Overrides + *==============================================*/ + +/** Ether Switch Event code of callback function */ +typedef enum e_ether_switch_event +{ + ETHER_SWITCH_EVENT_LINK_CHANGE ///< Change Link status +} ether_switch_event_t; + +/** Ether Switch Callback function parameter data */ +typedef struct st_ether_switch_callback_args +{ + uint32_t channel; ///< Device channel number + ether_switch_event_t event; ///< Event code + + uint32_t status_link; ///< Link status bit0:port0. bit1:port1. bit2:port2, bit3:port3 + + void const * p_context; ///< Placeholder for user data. +} ether_switch_callback_args_t; + +/*============================================== + * IOPORT API Overrides + *==============================================*/ + +/** Superset of all peripheral functions. */ +typedef enum e_ioport_pin_pfc +{ + IOPORT_PIN_P000_PFC_00_ETH2_RXD3 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_0 / ETHER_ETHn / ETH2_RXD3 + IOPORT_PIN_P000_PFC_01_D26 = (0x01U << IOPORT_PFC_OFFSET), ///< P00_0 / BSC / D26 + IOPORT_PIN_P000_PFC_02_D15 = (0x02U << IOPORT_PFC_OFFSET), ///< P00_0 / BSC / D15 + IOPORT_PIN_P000_PFC_03_SCK2 = (0x03U << IOPORT_PFC_OFFSET), ///< P00_0 / SCIn / SCK2 + IOPORT_PIN_P001_PFC_00_IRQ0 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_1 / IRQ / IRQ0 + IOPORT_PIN_P001_PFC_01_ETH2_RXDV = (0x01U << IOPORT_PFC_OFFSET), ///< P00_1 / ETHER_ETHn / ETH2_RXDV + IOPORT_PIN_P001_PFC_02_D27 = (0x02U << IOPORT_PFC_OFFSET), ///< P00_1 / BSC / D27 + IOPORT_PIN_P001_PFC_03_A13 = (0x03U << IOPORT_PFC_OFFSET), ///< P00_1 / BSC / A13 + IOPORT_PIN_P001_PFC_04_MTIC5U = (0x04U << IOPORT_PFC_OFFSET), ///< P00_1 / MTU3n / MTIC5U + IOPORT_PIN_P001_PFC_05_RXD2_SCL2_MISO2 = (0x05U << IOPORT_PFC_OFFSET), ///< P00_1 / SCIn / RXD2_SCL2_MISO2 + IOPORT_PIN_P002_PFC_00_ETH2_TXEN = (0x00U << IOPORT_PFC_OFFSET), ///< P00_2 / ETHER_ETHn / ETH2_TXEN + IOPORT_PIN_P002_PFC_01_D28 = (0x01U << IOPORT_PFC_OFFSET), ///< P00_2 / BSC / D28 + IOPORT_PIN_P002_PFC_02_RD = (0x02U << IOPORT_PFC_OFFSET), ///< P00_2 / BSC / RD + IOPORT_PIN_P002_PFC_03_MTIC5V = (0x03U << IOPORT_PFC_OFFSET), ///< P00_2 / MTU3n / MTIC5V + IOPORT_PIN_P002_PFC_04_TXD2_SDA2_MOSI2 = (0x04U << IOPORT_PFC_OFFSET), ///< P00_2 / SCIn / TXD2_SDA2_MOSI2 + IOPORT_PIN_P002_PFC_05_USB_OVRCUR = (0x05U << IOPORT_PFC_OFFSET), ///< P00_2 / USB_HS / USB_OVRCUR + IOPORT_PIN_P003_PFC_00_IRQ1 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_3 / IRQ / IRQ1 + IOPORT_PIN_P003_PFC_01_ETH2_REFCLK = (0x01U << IOPORT_PFC_OFFSET), ///< P00_3 / ETHER_ETHn / ETH2_REFCLK + IOPORT_PIN_P003_PFC_02_RMII2_REFCLK = (0x02U << IOPORT_PFC_OFFSET), ///< P00_3 / ETHER_ETHn / RMII2_REFCLK + IOPORT_PIN_P003_PFC_03_D29 = (0x03U << IOPORT_PFC_OFFSET), ///< P00_3 / BSC / D29 + IOPORT_PIN_P003_PFC_04_RD_WR = (0x04U << IOPORT_PFC_OFFSET), ///< P00_3 / BSC / RD_WR + IOPORT_PIN_P003_PFC_05_MTIC5W = (0x05U << IOPORT_PFC_OFFSET), ///< P00_3 / MTU3n / MTIC5W + IOPORT_PIN_P003_PFC_06_SS2_CTS2_RTS2 = (0x06U << IOPORT_PFC_OFFSET), ///< P00_3 / SCIn / SS2_CTS2_RTS2 + IOPORT_PIN_P004_PFC_00_IRQ13 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_4 / IRQ / IRQ13 + IOPORT_PIN_P004_PFC_01_ETH2_RXER = (0x01U << IOPORT_PFC_OFFSET), ///< P00_4 / ETHER_ETHn / ETH2_RXER + IOPORT_PIN_P004_PFC_02_D30 = (0x02U << IOPORT_PFC_OFFSET), ///< P00_4 / BSC / D30 + IOPORT_PIN_P004_PFC_03_WAIT = (0x03U << IOPORT_PFC_OFFSET), ///< P00_4 / BSC / WAIT + IOPORT_PIN_P004_PFC_04_MTIOC3A = (0x04U << IOPORT_PFC_OFFSET), ///< P00_4 / MTU3n / MTIOC3A + IOPORT_PIN_P004_PFC_05_GTIOC0A = (0x05U << IOPORT_PFC_OFFSET), ///< P00_4 / GPTn / GTIOC0A + IOPORT_PIN_P004_PFC_06_MCLK0 = (0x06U << IOPORT_PFC_OFFSET), ///< P00_4 / DSMIFn / MCLK0 + IOPORT_PIN_P005_PFC_00_ETHSW_PHYLINK2 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_5 / ETHER_ETHSW / ETHSW_PHYLINK2 + IOPORT_PIN_P005_PFC_01_D31 = (0x01U << IOPORT_PFC_OFFSET), ///< P00_5 / BSC / D31 + IOPORT_PIN_P005_PFC_02_CS0 = (0x02U << IOPORT_PFC_OFFSET), ///< P00_5 / BSC / CS0 + IOPORT_PIN_P005_PFC_03_ESC_PHYLINK2 = (0x03U << IOPORT_PFC_OFFSET), ///< P00_5 / ETHER_ESC / ESC_PHYLINK2 + IOPORT_PIN_P005_PFC_04_MTIOC3C = (0x04U << IOPORT_PFC_OFFSET), ///< P00_5 / MTU3n / MTIOC3C + IOPORT_PIN_P005_PFC_05_GTIOC0B = (0x05U << IOPORT_PFC_OFFSET), ///< P00_5 / GPTn / GTIOC0B + IOPORT_PIN_P005_PFC_06_MDAT0 = (0x06U << IOPORT_PFC_OFFSET), ///< P00_5 / DSMIFn / MDAT0 + IOPORT_PIN_P006_PFC_00_ETH2_TXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P00_6 / ETHER_ETHn / ETH2_TXCLK + IOPORT_PIN_P006_PFC_01_CS5 = (0x01U << IOPORT_PFC_OFFSET), ///< P00_6 / BSC / CS5 + IOPORT_PIN_P006_PFC_02_MTIOC3B = (0x02U << IOPORT_PFC_OFFSET), ///< P00_6 / MTU3n / MTIOC3B + IOPORT_PIN_P006_PFC_03_GTIOC1A = (0x03U << IOPORT_PFC_OFFSET), ///< P00_6 / GPTn / GTIOC1A + IOPORT_PIN_P007_PFC_00_IRQ13 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_7 / IRQ / IRQ13 + IOPORT_PIN_P007_PFC_01_RAS = (0x01U << IOPORT_PFC_OFFSET), ///< P00_7 / BSC / RAS + IOPORT_PIN_P007_PFC_02_MTIOC4A = (0x02U << IOPORT_PFC_OFFSET), ///< P00_7 / MTU3n / MTIOC4A + IOPORT_PIN_P007_PFC_03_GTIOC2A = (0x03U << IOPORT_PFC_OFFSET), ///< P00_7 / GPTn / GTIOC2A + IOPORT_PIN_P010_PFC_00_GMAC_MDIO = (0x00U << IOPORT_PFC_OFFSET), ///< P01_0 / ETHER_GMAC / GMAC_MDIO + IOPORT_PIN_P010_PFC_01_ETHSW_MDIO = (0x01U << IOPORT_PFC_OFFSET), ///< P01_0 / ETHER_ETHSW / ETHSW_MDIO + IOPORT_PIN_P010_PFC_02_CAS = (0x02U << IOPORT_PFC_OFFSET), ///< P01_0 / BSC / CAS + IOPORT_PIN_P010_PFC_03_ESC_MDIO = (0x03U << IOPORT_PFC_OFFSET), ///< P01_0 / ETHER_ESC / ESC_MDIO + IOPORT_PIN_P010_PFC_04_MTIOC4C = (0x04U << IOPORT_PFC_OFFSET), ///< P01_0 / MTU3n / MTIOC4C + IOPORT_PIN_P010_PFC_05_GTIOC3A = (0x05U << IOPORT_PFC_OFFSET), ///< P01_0 / GPTn / GTIOC3A + IOPORT_PIN_P010_PFC_06_CTS2 = (0x06U << IOPORT_PFC_OFFSET), ///< P01_0 / SCIn / CTS2 + IOPORT_PIN_P010_PFC_07_MCLK1 = (0x07U << IOPORT_PFC_OFFSET), ///< P01_0 / DSMIFn / MCLK1 + IOPORT_PIN_P011_PFC_00_GMAC_MDC = (0x00U << IOPORT_PFC_OFFSET), ///< P01_1 / ETHER_GMAC / GMAC_MDC + IOPORT_PIN_P011_PFC_01_ETHSW_MDC = (0x01U << IOPORT_PFC_OFFSET), ///< P01_1 / ETHER_ETHSW / ETHSW_MDC + IOPORT_PIN_P011_PFC_02_CKE = (0x02U << IOPORT_PFC_OFFSET), ///< P01_1 / BSC / CKE + IOPORT_PIN_P011_PFC_03_ESC_MDC = (0x03U << IOPORT_PFC_OFFSET), ///< P01_1 / ETHER_ESC / ESC_MDC + IOPORT_PIN_P011_PFC_04_MTIOC3D = (0x04U << IOPORT_PFC_OFFSET), ///< P01_1 / MTU3n / MTIOC3D + IOPORT_PIN_P011_PFC_05_GTIOC1B = (0x05U << IOPORT_PFC_OFFSET), ///< P01_1 / GPTn / GTIOC1B + IOPORT_PIN_P011_PFC_06_DE2 = (0x06U << IOPORT_PFC_OFFSET), ///< P01_1 / SCIn / DE2 + IOPORT_PIN_P011_PFC_07_MDAT1 = (0x07U << IOPORT_PFC_OFFSET), ///< P01_1 / DSMIFn / MDAT1 + IOPORT_PIN_P012_PFC_00_IRQ2 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_2 / IRQ / IRQ2 + IOPORT_PIN_P012_PFC_01_ETH2_TXD3 = (0x01U << IOPORT_PFC_OFFSET), ///< P01_2 / ETHER_ETHn / ETH2_TXD3 + IOPORT_PIN_P012_PFC_02_CS2 = (0x02U << IOPORT_PFC_OFFSET), ///< P01_2 / BSC / CS2 + IOPORT_PIN_P012_PFC_03_MTIOC4B = (0x03U << IOPORT_PFC_OFFSET), ///< P01_2 / MTU3n / MTIOC4B + IOPORT_PIN_P012_PFC_04_GTIOC2B = (0x04U << IOPORT_PFC_OFFSET), ///< P01_2 / GPTn / GTIOC2B + IOPORT_PIN_P013_PFC_00_ETH2_TXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_3 / ETHER_ETHn / ETH2_TXD2 + IOPORT_PIN_P013_PFC_01_WE3_DQMUU_AH = (0x01U << IOPORT_PFC_OFFSET), ///< P01_3 / BSC / WE3_DQMUU_AH + IOPORT_PIN_P013_PFC_02_MTIOC4D = (0x02U << IOPORT_PFC_OFFSET), ///< P01_3 / MTU3n / MTIOC4D + IOPORT_PIN_P013_PFC_03_GTIOC3B = (0x03U << IOPORT_PFC_OFFSET), ///< P01_3 / GPTn / GTIOC3B + IOPORT_PIN_P014_PFC_00_IRQ3 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_4 / IRQ / IRQ3 + IOPORT_PIN_P014_PFC_01_ETH2_TXD1 = (0x01U << IOPORT_PFC_OFFSET), ///< P01_4 / ETHER_ETHn / ETH2_TXD1 + IOPORT_PIN_P014_PFC_02_WE1_DQMLU = (0x02U << IOPORT_PFC_OFFSET), ///< P01_4 / BSC / WE1_DQMLU + IOPORT_PIN_P014_PFC_03_POE0 = (0x03U << IOPORT_PFC_OFFSET), ///< P01_4 / MTU_POE3 / POE0 + IOPORT_PIN_P015_PFC_00_ETH2_TXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_5 / ETHER_ETHn / ETH2_TXD0 + IOPORT_PIN_P015_PFC_01_WE0_DQMLL = (0x01U << IOPORT_PFC_OFFSET), ///< P01_5 / BSC / WE0_DQMLL + IOPORT_PIN_P016_PFC_00_GMAC_PTPTRG1 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_6 / ETHER_GMAC / GMAC_PTPTRG1 + IOPORT_PIN_P016_PFC_01_TRACEDATA0 = (0x01U << IOPORT_PFC_OFFSET), ///< P01_6 / TRACE / TRACEDATA0 + IOPORT_PIN_P016_PFC_02_A20 = (0x02U << IOPORT_PFC_OFFSET), ///< P01_6 / BSC / A20 + IOPORT_PIN_P016_PFC_03_ESC_LATCH1 = (0x03U << IOPORT_PFC_OFFSET), ///< P01_6 / ETHER_ESC / ESC_LATCH1 + IOPORT_PIN_P016_PFC_04_ESC_LATCH0 = (0x04U << IOPORT_PFC_OFFSET), ///< P01_6 / ETHER_ESC / ESC_LATCH0 + IOPORT_PIN_P016_PFC_05_MTIOC1A = (0x05U << IOPORT_PFC_OFFSET), ///< P01_6 / MTU3n / MTIOC1A + IOPORT_PIN_P016_PFC_06_GTIOC9A = (0x06U << IOPORT_PFC_OFFSET), ///< P01_6 / GPTn / GTIOC9A + IOPORT_PIN_P016_PFC_07_CTS1 = (0x07U << IOPORT_PFC_OFFSET), ///< P01_6 / SCIn / CTS1 + IOPORT_PIN_P016_PFC_08_CANTXDP1 = (0x08U << IOPORT_PFC_OFFSET), ///< P01_6 / CANFDn / CANTXDP1 + IOPORT_PIN_P016_PFC_09_ENCIF0 = (0x09U << IOPORT_PFC_OFFSET), ///< P01_6 / ENCIF / ENCIF0 + IOPORT_PIN_P017_PFC_00_ETHSW_LPI1 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_7 / ETHER_ETHSW / ETHSW_LPI1 + IOPORT_PIN_P017_PFC_01_TRACEDATA1 = (0x01U << IOPORT_PFC_OFFSET), ///< P01_7 / TRACE / TRACEDATA1 + IOPORT_PIN_P017_PFC_02_A19 = (0x02U << IOPORT_PFC_OFFSET), ///< P01_7 / BSC / A19 + IOPORT_PIN_P017_PFC_03_MTIOC1B = (0x03U << IOPORT_PFC_OFFSET), ///< P01_7 / MTU3n / MTIOC1B + IOPORT_PIN_P017_PFC_04_GTIOC9B = (0x04U << IOPORT_PFC_OFFSET), ///< P01_7 / GPTn / GTIOC9B + IOPORT_PIN_P017_PFC_05_ADTRG0 = (0x05U << IOPORT_PFC_OFFSET), ///< P01_7 / ADCn / ADTRG0 + IOPORT_PIN_P017_PFC_06_SCK1 = (0x06U << IOPORT_PFC_OFFSET), ///< P01_7 / SCIn / SCK1 + IOPORT_PIN_P017_PFC_07_SPI_RSPCK3 = (0x07U << IOPORT_PFC_OFFSET), ///< P01_7 / SPIn / SPI_RSPCK3 + IOPORT_PIN_P017_PFC_08_CANRX0 = (0x08U << IOPORT_PFC_OFFSET), ///< P01_7 / CANFDn / CANRX0 + IOPORT_PIN_P017_PFC_09_ENCIF1 = (0x09U << IOPORT_PFC_OFFSET), ///< P01_7 / ENCIF / ENCIF1 + IOPORT_PIN_P020_PFC_00_IRQ4 = (0x00U << IOPORT_PFC_OFFSET), ///< P02_0 / IRQ / IRQ4 + IOPORT_PIN_P020_PFC_01_ETHSW_LPI2 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_0 / ETHER_ETHSW / ETHSW_LPI2 + IOPORT_PIN_P020_PFC_02_TRACEDATA2 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_0 / TRACE / TRACEDATA2 + IOPORT_PIN_P020_PFC_03_A18 = (0x03U << IOPORT_PFC_OFFSET), ///< P02_0 / BSC / A18 + IOPORT_PIN_P020_PFC_04_GTADSML0 = (0x04U << IOPORT_PFC_OFFSET), ///< P02_0 / GPT / GTADSML0 + IOPORT_PIN_P020_PFC_05_RXD1_SCL1_MISO1 = (0x05U << IOPORT_PFC_OFFSET), ///< P02_0 / SCIn / RXD1_SCL1_MISO1 + IOPORT_PIN_P020_PFC_06_SPI_MISO3 = (0x06U << IOPORT_PFC_OFFSET), ///< P02_0 / SPIn / SPI_MISO3 + IOPORT_PIN_P020_PFC_07_CANTX1 = (0x07U << IOPORT_PFC_OFFSET), ///< P02_0 / CANFDn / CANTX1 + IOPORT_PIN_P020_PFC_08_USB_OTGID = (0x08U << IOPORT_PFC_OFFSET), ///< P02_0 / USB_HS / USB_OTGID + IOPORT_PIN_P020_PFC_09_ENCIF2 = (0x09U << IOPORT_PFC_OFFSET), ///< P02_0 / ENCIF / ENCIF2 + IOPORT_PIN_P021_PFC_00_ETHSW_PTPOUT1 = (0x00U << IOPORT_PFC_OFFSET), ///< P02_1 / ETHER_ETHSW / ETHSW_PTPOUT1 + IOPORT_PIN_P021_PFC_01_A17 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_1 / BSC / A17 + IOPORT_PIN_P021_PFC_02_ESC_SYNC1 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_1 / ETHER_ESC / ESC_SYNC1 + IOPORT_PIN_P021_PFC_03_ESC_SYNC0 = (0x03U << IOPORT_PFC_OFFSET), ///< P02_1 / ETHER_ESC / ESC_SYNC0 + IOPORT_PIN_P022_PFC_00_IRQ14 = (0x00U << IOPORT_PFC_OFFSET), ///< P02_2 / IRQ / IRQ14 + IOPORT_PIN_P022_PFC_01_ETHSW_TDMAOUT0 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_2 / ETHER_ETHSW / ETHSW_TDMAOUT0 + IOPORT_PIN_P022_PFC_02_A16 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_2 / BSC / A16 + IOPORT_PIN_P022_PFC_03_MTIOC2A = (0x03U << IOPORT_PFC_OFFSET), ///< P02_2 / MTU3n / MTIOC2A + IOPORT_PIN_P022_PFC_04_GTIOC10A = (0x04U << IOPORT_PFC_OFFSET), ///< P02_2 / GPTn / GTIOC10A + IOPORT_PIN_P022_PFC_05_POE10 = (0x05U << IOPORT_PFC_OFFSET), ///< P02_2 / MTU_POE3 / POE10 + IOPORT_PIN_P022_PFC_06_TXD1_SDA1_MOSI1 = (0x06U << IOPORT_PFC_OFFSET), ///< P02_2 / SCIn / TXD1_SDA1_MOSI1 + IOPORT_PIN_P022_PFC_07_SPI_MOSI3 = (0x07U << IOPORT_PFC_OFFSET), ///< P02_2 / SPIn / SPI_MOSI3 + IOPORT_PIN_P022_PFC_08_CANTX0 = (0x08U << IOPORT_PFC_OFFSET), ///< P02_2 / CANFDn / CANTX0 + IOPORT_PIN_P022_PFC_09_ENCIF3 = (0x09U << IOPORT_PFC_OFFSET), ///< P02_2 / ENCIF / ENCIF3 + IOPORT_PIN_P022_PFC_0A_RTCAT1HZ = (0x0AU << IOPORT_PFC_OFFSET), ///< P02_2 / RTC / RTCAT1HZ + IOPORT_PIN_P023_PFC_00_IRQ15 = (0x00U << IOPORT_PFC_OFFSET), ///< P02_3 / IRQ / IRQ15 + IOPORT_PIN_P023_PFC_01_ETHSW_TDMAOUT1 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_3 / ETHER_ETHSW / ETHSW_TDMAOUT1 + IOPORT_PIN_P023_PFC_02_A15 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_3 / BSC / A15 + IOPORT_PIN_P023_PFC_03_WE3_DQMUU_AH = (0x03U << IOPORT_PFC_OFFSET), ///< P02_3 / BSC / WE3_DQMUU_AH + IOPORT_PIN_P023_PFC_04_MTIOC2B = (0x04U << IOPORT_PFC_OFFSET), ///< P02_3 / MTU3n / MTIOC2B + IOPORT_PIN_P023_PFC_05_GTIOC10B = (0x05U << IOPORT_PFC_OFFSET), ///< P02_3 / GPTn / GTIOC10B + IOPORT_PIN_P023_PFC_06_POE11 = (0x06U << IOPORT_PFC_OFFSET), ///< P02_3 / MTU_POE3 / POE11 + IOPORT_PIN_P023_PFC_07_SS1_CTS1_RTS1 = (0x07U << IOPORT_PFC_OFFSET), ///< P02_3 / SCIn / SS1_CTS1_RTS1 + IOPORT_PIN_P023_PFC_08_SPI_SSL30 = (0x08U << IOPORT_PFC_OFFSET), ///< P02_3 / SPIn / SPI_SSL30 + IOPORT_PIN_P023_PFC_09_CANRX1 = (0x09U << IOPORT_PFC_OFFSET), ///< P02_3 / CANFDn / CANRX1 + IOPORT_PIN_P023_PFC_0A_ENCIF4 = (0x0AU << IOPORT_PFC_OFFSET), ///< P02_3 / ENCIF / ENCIF4 + IOPORT_PIN_P024_PFC_00_TDO = (0x00U << IOPORT_PFC_OFFSET), ///< P02_4 / JTAG/SWD / TDO + IOPORT_PIN_P024_PFC_01_WE0_DQMLL = (0x01U << IOPORT_PFC_OFFSET), ///< P02_4 / BSC / WE0_DQMLL + IOPORT_PIN_P024_PFC_02_DE1 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_4 / SCIn / DE1 + IOPORT_PIN_P024_PFC_03_SPI_SSL33 = (0x03U << IOPORT_PFC_OFFSET), ///< P02_4 / SPIn / SPI_SSL33 + IOPORT_PIN_P025_PFC_00_ETHSW_TDMAOUT3 = (0x00U << IOPORT_PFC_OFFSET), ///< P02_5 / ETHER_ETHSW / ETHSW_TDMAOUT3 + IOPORT_PIN_P025_PFC_01_TDI = (0x01U << IOPORT_PFC_OFFSET), ///< P02_5 / JTAG/SWD / TDI + IOPORT_PIN_P025_PFC_02_WE1_DQMLU = (0x02U << IOPORT_PFC_OFFSET), ///< P02_5 / BSC / WE1_DQMLU + IOPORT_PIN_P025_PFC_03_SCK5 = (0x03U << IOPORT_PFC_OFFSET), ///< P02_5 / SCIn / SCK5 + IOPORT_PIN_P025_PFC_04_SPI_SSL31 = (0x04U << IOPORT_PFC_OFFSET), ///< P02_5 / SPIn / SPI_SSL31 + IOPORT_PIN_P025_PFC_05_ENCIF5 = (0x05U << IOPORT_PFC_OFFSET), ///< P02_5 / ENCIF / ENCIF5 + IOPORT_PIN_P026_PFC_00_TMS_SWDIO = (0x00U << IOPORT_PFC_OFFSET), ///< P02_6 / JTAG/SWD / TMS_SWDIO + IOPORT_PIN_P026_PFC_01_RXD5_SCL5_MISO5 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_6 / SCIn / RXD5_SCL5_MISO5 + IOPORT_PIN_P026_PFC_02_ENCIF6 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_6 / ENCIF / ENCIF6 + IOPORT_PIN_P027_PFC_00_TCK_SWCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P02_7 / JTAG/SWD / TCK_SWCLK + IOPORT_PIN_P027_PFC_01_TXD5_SDA5_MOSI5 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_7 / SCIn / TXD5_SDA5_MOSI5 + IOPORT_PIN_P027_PFC_02_ENCIF7 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_7 / ENCIF / ENCIF7 + IOPORT_PIN_P030_PFC_00_IRQ14 = (0x00U << IOPORT_PFC_OFFSET), ///< P03_0 / IRQ / IRQ14 + IOPORT_PIN_P030_PFC_01_TRACEDATA3 = (0x01U << IOPORT_PFC_OFFSET), ///< P03_0 / TRACE / TRACEDATA3 + IOPORT_PIN_P030_PFC_02_A14 = (0x02U << IOPORT_PFC_OFFSET), ///< P03_0 / BSC / A14 + IOPORT_PIN_P030_PFC_03_CS5 = (0x03U << IOPORT_PFC_OFFSET), ///< P03_0 / BSC / CS5 + IOPORT_PIN_P030_PFC_04_GTADSML1 = (0x04U << IOPORT_PFC_OFFSET), ///< P03_0 / GPT / GTADSML1 + IOPORT_PIN_P030_PFC_05_SCK2 = (0x05U << IOPORT_PFC_OFFSET), ///< P03_0 / SCIn / SCK2 + IOPORT_PIN_P030_PFC_06_SPI_SSL32 = (0x06U << IOPORT_PFC_OFFSET), ///< P03_0 / SPIn / SPI_SSL32 + IOPORT_PIN_P030_PFC_07_CANTXDP1 = (0x07U << IOPORT_PFC_OFFSET), ///< P03_0 / CANFDn / CANTXDP1 + IOPORT_PIN_P030_PFC_08_ENCIF8 = (0x08U << IOPORT_PFC_OFFSET), ///< P03_0 / ENCIF / ENCIF8 + IOPORT_PIN_P032_PFC_00_NMI = (0x00U << IOPORT_PFC_OFFSET), ///< P03_2 / IRQ / NMI + IOPORT_PIN_P032_PFC_01_ETHSW_TDMAOUT2 = (0x01U << IOPORT_PFC_OFFSET), ///< P03_2 / ETHER_ETHSW / ETHSW_TDMAOUT2 + IOPORT_PIN_P032_PFC_02_A13 = (0x02U << IOPORT_PFC_OFFSET), ///< P03_2 / BSC / A13 + IOPORT_PIN_P032_PFC_03_CTS2 = (0x03U << IOPORT_PFC_OFFSET), ///< P03_2 / SCIn / CTS2 + IOPORT_PIN_P032_PFC_04_CANRXDP0 = (0x04U << IOPORT_PFC_OFFSET), ///< P03_2 / CANFDn / CANRXDP0 + IOPORT_PIN_P033_PFC_00_IRQ11 = (0x00U << IOPORT_PFC_OFFSET), ///< P03_3 / IRQ / IRQ11 + IOPORT_PIN_P033_PFC_01_WAIT = (0x01U << IOPORT_PFC_OFFSET), ///< P03_3 / BSC / WAIT + IOPORT_PIN_P033_PFC_02_DE2 = (0x02U << IOPORT_PFC_OFFSET), ///< P03_3 / SCIn / DE2 + IOPORT_PIN_P033_PFC_03_TEND = (0x03U << IOPORT_PFC_OFFSET), ///< P03_3 / DMAC / TEND + IOPORT_PIN_P033_PFC_04_USB_OTGID = (0x04U << IOPORT_PFC_OFFSET), ///< P03_3 / USB_HS / USB_OTGID + IOPORT_PIN_P033_PFC_05_ENCIF9 = (0x05U << IOPORT_PFC_OFFSET), ///< P03_3 / ENCIF / ENCIF9 + IOPORT_PIN_P034_PFC_00_IRQ7 = (0x00U << IOPORT_PFC_OFFSET), ///< P03_4 / IRQ / IRQ7 + IOPORT_PIN_P034_PFC_01_RD_WR = (0x01U << IOPORT_PFC_OFFSET), ///< P03_4 / BSC / RD_WR + IOPORT_PIN_P034_PFC_02_SS2_CTS2_RTS2 = (0x02U << IOPORT_PFC_OFFSET), ///< P03_4 / SCIn / SS2_CTS2_RTS2 + IOPORT_PIN_P034_PFC_03_SPI_SSL03 = (0x03U << IOPORT_PFC_OFFSET), ///< P03_4 / SPIn / SPI_SSL03 + IOPORT_PIN_P035_PFC_00_IRQ5 = (0x00U << IOPORT_PFC_OFFSET), ///< P03_5 / IRQ / IRQ5 + IOPORT_PIN_P035_PFC_01_ETH2_CRS = (0x01U << IOPORT_PFC_OFFSET), ///< P03_5 / ETHER_ETHn / ETH2_CRS + IOPORT_PIN_P035_PFC_02_A12 = (0x02U << IOPORT_PFC_OFFSET), ///< P03_5 / BSC / A12 + IOPORT_PIN_P035_PFC_03_MTIOC3A = (0x03U << IOPORT_PFC_OFFSET), ///< P03_5 / MTU3n / MTIOC3A + IOPORT_PIN_P035_PFC_04_GTIOC4A = (0x04U << IOPORT_PFC_OFFSET), ///< P03_5 / GPTn / GTIOC4A + IOPORT_PIN_P035_PFC_05_RXD2_SCL2_MISO2 = (0x05U << IOPORT_PFC_OFFSET), ///< P03_5 / SCIn / RXD2_SCL2_MISO2 + IOPORT_PIN_P035_PFC_06_MCLK2 = (0x06U << IOPORT_PFC_OFFSET), ///< P03_5 / DSMIFn / MCLK2 + IOPORT_PIN_P036_PFC_00_IRQ8 = (0x00U << IOPORT_PFC_OFFSET), ///< P03_6 / IRQ / IRQ8 + IOPORT_PIN_P036_PFC_01_ETH2_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P03_6 / ETHER_ETHn / ETH2_COL + IOPORT_PIN_P036_PFC_02_TRACEDATA4 = (0x02U << IOPORT_PFC_OFFSET), ///< P03_6 / TRACE / TRACEDATA4 + IOPORT_PIN_P036_PFC_03_A11 = (0x03U << IOPORT_PFC_OFFSET), ///< P03_6 / BSC / A11 + IOPORT_PIN_P036_PFC_04_MTIOC3B = (0x04U << IOPORT_PFC_OFFSET), ///< P03_6 / MTU3n / MTIOC3B + IOPORT_PIN_P036_PFC_05_GTIOC4B = (0x05U << IOPORT_PFC_OFFSET), ///< P03_6 / GPTn / GTIOC4B + IOPORT_PIN_P036_PFC_06_TXD2_SDA2_MOSI2 = (0x06U << IOPORT_PFC_OFFSET), ///< P03_6 / SCIn / TXD2_SDA2_MOSI2 + IOPORT_PIN_P036_PFC_07_SPI_SSL13 = (0x07U << IOPORT_PFC_OFFSET), ///< P03_6 / SPIn / SPI_SSL13 + IOPORT_PIN_P036_PFC_08_MDAT2 = (0x08U << IOPORT_PFC_OFFSET), ///< P03_6 / DSMIFn / MDAT2 + IOPORT_PIN_P037_PFC_00_IRQ9 = (0x00U << IOPORT_PFC_OFFSET), ///< P03_7 / IRQ / IRQ9 + IOPORT_PIN_P037_PFC_01_ETH2_TXER = (0x01U << IOPORT_PFC_OFFSET), ///< P03_7 / ETHER_ETHn / ETH2_TXER + IOPORT_PIN_P037_PFC_02_TRACEDATA5 = (0x02U << IOPORT_PFC_OFFSET), ///< P03_7 / TRACE / TRACEDATA5 + IOPORT_PIN_P037_PFC_03_A10 = (0x03U << IOPORT_PFC_OFFSET), ///< P03_7 / BSC / A10 + IOPORT_PIN_P037_PFC_04_MTIOC3C = (0x04U << IOPORT_PFC_OFFSET), ///< P03_7 / MTU3n / MTIOC3C + IOPORT_PIN_P037_PFC_05_GTIOC5A = (0x05U << IOPORT_PFC_OFFSET), ///< P03_7 / GPTn / GTIOC5A + IOPORT_PIN_P037_PFC_06_SCK3 = (0x06U << IOPORT_PFC_OFFSET), ///< P03_7 / SCIn / SCK3 + IOPORT_PIN_P040_PFC_00_TRACEDATA6 = (0x00U << IOPORT_PFC_OFFSET), ///< P04_0 / TRACE / TRACEDATA6 + IOPORT_PIN_P040_PFC_01_A9 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_0 / BSC / A9 + IOPORT_PIN_P040_PFC_02_MTIOC3D = (0x02U << IOPORT_PFC_OFFSET), ///< P04_0 / MTU3n / MTIOC3D + IOPORT_PIN_P040_PFC_03_GTIOC5B = (0x03U << IOPORT_PFC_OFFSET), ///< P04_0 / GPTn / GTIOC5B + IOPORT_PIN_P040_PFC_04_RXD3_SCL3_MISO3 = (0x04U << IOPORT_PFC_OFFSET), ///< P04_0 / SCIn / RXD3_SCL3_MISO3 + IOPORT_PIN_P041_PFC_00_CKIO = (0x00U << IOPORT_PFC_OFFSET), ///< P04_1 / BSC / CKIO + IOPORT_PIN_P041_PFC_01_TXD3_SDA3_MOSI3 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_1 / SCIn / TXD3_SDA3_MOSI3 + IOPORT_PIN_P041_PFC_02_SPI_MOSI0 = (0x02U << IOPORT_PFC_OFFSET), ///< P04_1 / SPIn / SPI_MOSI0 + IOPORT_PIN_P041_PFC_03_IIC_SDA2 = (0x03U << IOPORT_PFC_OFFSET), ///< P04_1 / IICn / IIC_SDA2 + IOPORT_PIN_P042_PFC_00_CS0 = (0x00U << IOPORT_PFC_OFFSET), ///< P04_2 / BSC / CS0 + IOPORT_PIN_P043_PFC_00_RD = (0x00U << IOPORT_PFC_OFFSET), ///< P04_3 / BSC / RD + IOPORT_PIN_P043_PFC_01_SS3_CTS3_RTS3 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_3 / SCIn / SS3_CTS3_RTS3 + IOPORT_PIN_P043_PFC_02_SPI_RSPCK0 = (0x02U << IOPORT_PFC_OFFSET), ///< P04_3 / SPIn / SPI_RSPCK0 + IOPORT_PIN_P043_PFC_03_IIC_SCL2 = (0x03U << IOPORT_PFC_OFFSET), ///< P04_3 / IICn / IIC_SCL2 + IOPORT_PIN_P043_PFC_04_USB_OVRCUR = (0x04U << IOPORT_PFC_OFFSET), ///< P04_3 / USB_HS / USB_OVRCUR + IOPORT_PIN_P044_PFC_00_IRQ10 = (0x00U << IOPORT_PFC_OFFSET), ///< P04_4 / IRQ / IRQ10 + IOPORT_PIN_P044_PFC_01_TRACEDATA7 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_4 / TRACE / TRACEDATA7 + IOPORT_PIN_P044_PFC_02_A8 = (0x02U << IOPORT_PFC_OFFSET), ///< P04_4 / BSC / A8 + IOPORT_PIN_P044_PFC_03_GTADSMP0 = (0x03U << IOPORT_PFC_OFFSET), ///< P04_4 / GPT / GTADSMP0 + IOPORT_PIN_P044_PFC_04_POE10 = (0x04U << IOPORT_PFC_OFFSET), ///< P04_4 / MTU_POE3 / POE10 + IOPORT_PIN_P044_PFC_05_CTS3 = (0x05U << IOPORT_PFC_OFFSET), ///< P04_4 / SCIn / CTS3 + IOPORT_PIN_P044_PFC_06_SPI_RSPCK1 = (0x06U << IOPORT_PFC_OFFSET), ///< P04_4 / SPIn / SPI_RSPCK1 + IOPORT_PIN_P044_PFC_07_ENCIF10 = (0x07U << IOPORT_PFC_OFFSET), ///< P04_4 / ENCIF / ENCIF10 + IOPORT_PIN_P045_PFC_00_A7 = (0x00U << IOPORT_PFC_OFFSET), ///< P04_5 / BSC / A7 + IOPORT_PIN_P045_PFC_01_DE3 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_5 / SCIn / DE3 + IOPORT_PIN_P046_PFC_00_ETH1_TXER = (0x00U << IOPORT_PFC_OFFSET), ///< P04_6 / ETHER_ETHn / ETH1_TXER + IOPORT_PIN_P046_PFC_01_A6 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_6 / BSC / A6 + IOPORT_PIN_P046_PFC_02_DACK = (0x02U << IOPORT_PFC_OFFSET), ///< P04_6 / DMAC / DACK + IOPORT_PIN_P046_PFC_03_RTCAT1HZ = (0x03U << IOPORT_PFC_OFFSET), ///< P04_6 / RTC / RTCAT1HZ + IOPORT_PIN_P047_PFC_00_ETH0_TXER = (0x00U << IOPORT_PFC_OFFSET), ///< P04_7 / ETHER_ETHn / ETH0_TXER + IOPORT_PIN_P047_PFC_01_A5 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_7 / BSC / A5 + IOPORT_PIN_P047_PFC_02_SPI_SSL21 = (0x02U << IOPORT_PFC_OFFSET), ///< P04_7 / SPIn / SPI_SSL21 + IOPORT_PIN_P050_PFC_00_IRQ12 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_0 / IRQ / IRQ12 + IOPORT_PIN_P050_PFC_01_ETH1_CRS = (0x01U << IOPORT_PFC_OFFSET), ///< P05_0 / ETHER_ETHn / ETH1_CRS + IOPORT_PIN_P050_PFC_02_A4 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_0 / BSC / A4 + IOPORT_PIN_P050_PFC_03_MTIOC4A = (0x03U << IOPORT_PFC_OFFSET), ///< P05_0 / MTU3n / MTIOC4A + IOPORT_PIN_P050_PFC_04_GTIOC6A = (0x04U << IOPORT_PFC_OFFSET), ///< P05_0 / GPTn / GTIOC6A + IOPORT_PIN_P050_PFC_05_CMTW0_TOC0 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_0 / CMTWn / CMTW0_TOC0 + IOPORT_PIN_P050_PFC_06_SS5_CTS5_RTS5 = (0x06U << IOPORT_PFC_OFFSET), ///< P05_0 / SCIn / SS5_CTS5_RTS5 + IOPORT_PIN_P050_PFC_07_CANTXDP0 = (0x07U << IOPORT_PFC_OFFSET), ///< P05_0 / CANFDn / CANTXDP0 + IOPORT_PIN_P050_PFC_08_USB_VBUSEN = (0x08U << IOPORT_PFC_OFFSET), ///< P05_0 / USB_HS / USB_VBUSEN + IOPORT_PIN_P050_PFC_09_MCLK3 = (0x09U << IOPORT_PFC_OFFSET), ///< P05_0 / DSMIFn / MCLK3 + IOPORT_PIN_P050_PFC_0A_ENCIF11 = (0x0AU << IOPORT_PFC_OFFSET), ///< P05_0 / ENCIF / ENCIF11 + IOPORT_PIN_P051_PFC_00_IRQ13 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_1 / IRQ / IRQ13 + IOPORT_PIN_P051_PFC_01_ETH1_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P05_1 / ETHER_ETHn / ETH1_COL + IOPORT_PIN_P051_PFC_02_A3 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_1 / BSC / A3 + IOPORT_PIN_P051_PFC_03_MTIOC4B = (0x03U << IOPORT_PFC_OFFSET), ///< P05_1 / MTU3n / MTIOC4B + IOPORT_PIN_P051_PFC_04_GTIOC6B = (0x04U << IOPORT_PFC_OFFSET), ///< P05_1 / GPTn / GTIOC6B + IOPORT_PIN_P051_PFC_05_CMTW0_TIC1 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_1 / CMTWn / CMTW0_TIC1 + IOPORT_PIN_P051_PFC_06_CTS5 = (0x06U << IOPORT_PFC_OFFSET), ///< P05_1 / SCIn / CTS5 + IOPORT_PIN_P051_PFC_07_CANRXDP0 = (0x07U << IOPORT_PFC_OFFSET), ///< P05_1 / CANFDn / CANRXDP0 + IOPORT_PIN_P051_PFC_08_USB_EXICEN = (0x08U << IOPORT_PFC_OFFSET), ///< P05_1 / USB_HS / USB_EXICEN + IOPORT_PIN_P051_PFC_09_MDAT3 = (0x09U << IOPORT_PFC_OFFSET), ///< P05_1 / DSMIFn / MDAT3 + IOPORT_PIN_P051_PFC_0A_ENCIF12 = (0x0AU << IOPORT_PFC_OFFSET), ///< P05_1 / ENCIF / ENCIF12 + IOPORT_PIN_P052_PFC_00_IRQ14 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_2 / IRQ / IRQ14 + IOPORT_PIN_P052_PFC_01_ETH0_CRS = (0x01U << IOPORT_PFC_OFFSET), ///< P05_2 / ETHER_ETHn / ETH0_CRS + IOPORT_PIN_P052_PFC_02_A2 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_2 / BSC / A2 + IOPORT_PIN_P052_PFC_03_MTIOC4C = (0x03U << IOPORT_PFC_OFFSET), ///< P05_2 / MTU3n / MTIOC4C + IOPORT_PIN_P052_PFC_04_GTETRGSA = (0x04U << IOPORT_PFC_OFFSET), ///< P05_2 / GPT_POEG / GTETRGSA + IOPORT_PIN_P052_PFC_05_GTIOC7A = (0x05U << IOPORT_PFC_OFFSET), ///< P05_2 / GPTn / GTIOC7A + IOPORT_PIN_P052_PFC_06_CMTW0_TOC0 = (0x06U << IOPORT_PFC_OFFSET), ///< P05_2 / CMTWn / CMTW0_TOC0 + IOPORT_PIN_P052_PFC_07_DE5 = (0x07U << IOPORT_PFC_OFFSET), ///< P05_2 / SCIn / DE5 + IOPORT_PIN_P052_PFC_08_IIC_SCL1 = (0x08U << IOPORT_PFC_OFFSET), ///< P05_2 / IICn / IIC_SCL1 + IOPORT_PIN_P052_PFC_09_CANRX0 = (0x09U << IOPORT_PFC_OFFSET), ///< P05_2 / CANFDn / CANRX0 + IOPORT_PIN_P052_PFC_0A_DREQ = (0x0AU << IOPORT_PFC_OFFSET), ///< P05_2 / DMAC / DREQ + IOPORT_PIN_P052_PFC_0B_USB_VBUSEN = (0x0BU << IOPORT_PFC_OFFSET), ///< P05_2 / USB_HS / USB_VBUSEN + IOPORT_PIN_P052_PFC_0C_ENCIF13 = (0x0CU << IOPORT_PFC_OFFSET), ///< P05_2 / ENCIF / ENCIF13 + IOPORT_PIN_P053_PFC_00_IRQ15 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_3 / IRQ / IRQ15 + IOPORT_PIN_P053_PFC_01_ETH0_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P05_3 / ETHER_ETHn / ETH0_COL + IOPORT_PIN_P053_PFC_02_A1 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_3 / BSC / A1 + IOPORT_PIN_P053_PFC_03_MTIOC4D = (0x03U << IOPORT_PFC_OFFSET), ///< P05_3 / MTU3n / MTIOC4D + IOPORT_PIN_P053_PFC_04_GTETRGSB = (0x04U << IOPORT_PFC_OFFSET), ///< P05_3 / GPT_POEG / GTETRGSB + IOPORT_PIN_P053_PFC_05_GTIOC7B = (0x05U << IOPORT_PFC_OFFSET), ///< P05_3 / GPTn / GTIOC7B + IOPORT_PIN_P053_PFC_06_POE11 = (0x06U << IOPORT_PFC_OFFSET), ///< P05_3 / MTU_POE3 / POE11 + IOPORT_PIN_P053_PFC_07_CMTW0_TIC0 = (0x07U << IOPORT_PFC_OFFSET), ///< P05_3 / CMTWn / CMTW0_TIC0 + IOPORT_PIN_P053_PFC_08_SCK4 = (0x08U << IOPORT_PFC_OFFSET), ///< P05_3 / SCIn / SCK4 + IOPORT_PIN_P053_PFC_09_IIC_SDA1 = (0x09U << IOPORT_PFC_OFFSET), ///< P05_3 / IICn / IIC_SDA1 + IOPORT_PIN_P053_PFC_0A_CANTX0 = (0x0AU << IOPORT_PFC_OFFSET), ///< P05_3 / CANFDn / CANTX0 + IOPORT_PIN_P053_PFC_0B_USB_EXICEN = (0x0BU << IOPORT_PFC_OFFSET), ///< P05_3 / USB_HS / USB_EXICEN + IOPORT_PIN_P053_PFC_0C_ENCIF14 = (0x0CU << IOPORT_PFC_OFFSET), ///< P05_3 / ENCIF / ENCIF14 + IOPORT_PIN_P054_PFC_00_IRQ12 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_4 / IRQ / IRQ12 + IOPORT_PIN_P054_PFC_01_ETHSW_LPI0 = (0x01U << IOPORT_PFC_OFFSET), ///< P05_4 / ETHER_ETHSW / ETHSW_LPI0 + IOPORT_PIN_P054_PFC_02_A0 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_4 / BSC / A0 + IOPORT_PIN_P054_PFC_03_GTIOC14A = (0x03U << IOPORT_PFC_OFFSET), ///< P05_4 / GPTn / GTIOC14A + IOPORT_PIN_P054_PFC_04_RXD4_SCL4_MISO4 = (0x04U << IOPORT_PFC_OFFSET), ///< P05_4 / SCIn / RXD4_SCL4_MISO4 + IOPORT_PIN_P054_PFC_05_SPI_SSL00 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_4 / SPIn / SPI_SSL00 + IOPORT_PIN_P054_PFC_06_CANTXDP0 = (0x06U << IOPORT_PFC_OFFSET), ///< P05_4 / CANFDn / CANTXDP0 + IOPORT_PIN_P054_PFC_07_DACK = (0x07U << IOPORT_PFC_OFFSET), ///< P05_4 / DMAC / DACK + IOPORT_PIN_P054_PFC_08_USB_OVRCUR = (0x08U << IOPORT_PFC_OFFSET), ///< P05_4 / USB_HS / USB_OVRCUR + IOPORT_PIN_P054_PFC_09_ENCIF15 = (0x09U << IOPORT_PFC_OFFSET), ///< P05_4 / ENCIF / ENCIF15 + IOPORT_PIN_P055_PFC_00_ETHSW_PHYLINK1 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_5 / ETHER_ETHSW / ETHSW_PHYLINK1 + IOPORT_PIN_P055_PFC_01_D16 = (0x01U << IOPORT_PFC_OFFSET), ///< P05_5 / BSC / D16 + IOPORT_PIN_P055_PFC_02_ESC_PHYLINK1 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_5 / ETHER_ESC / ESC_PHYLINK1 + IOPORT_PIN_P055_PFC_03_GTIOC14B = (0x03U << IOPORT_PFC_OFFSET), ///< P05_5 / GPTn / GTIOC14B + IOPORT_PIN_P055_PFC_04_CMTW0_TOC1 = (0x04U << IOPORT_PFC_OFFSET), ///< P05_5 / CMTWn / CMTW0_TOC1 + IOPORT_PIN_P055_PFC_05_SPI_RSPCK2 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_5 / SPIn / SPI_RSPCK2 + IOPORT_PIN_P056_PFC_00_IRQ12 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_6 / IRQ / IRQ12 + IOPORT_PIN_P056_PFC_01_ETH1_RXER = (0x01U << IOPORT_PFC_OFFSET), ///< P05_6 / ETHER_ETHn / ETH1_RXER + IOPORT_PIN_P056_PFC_02_D17 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_6 / BSC / D17 + IOPORT_PIN_P056_PFC_03_GTIOC15A = (0x03U << IOPORT_PFC_OFFSET), ///< P05_6 / GPTn / GTIOC15A + IOPORT_PIN_P056_PFC_04_CMTW1_TIC0 = (0x04U << IOPORT_PFC_OFFSET), ///< P05_6 / CMTWn / CMTW1_TIC0 + IOPORT_PIN_P056_PFC_05_SPI_SSL22 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_6 / SPIn / SPI_SSL22 + IOPORT_PIN_P057_PFC_00_ETH1_TXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_7 / ETHER_ETHn / ETH1_TXD2 + IOPORT_PIN_P057_PFC_01_D18 = (0x01U << IOPORT_PFC_OFFSET), ///< P05_7 / BSC / D18 + IOPORT_PIN_P057_PFC_02_GTIOC15B = (0x02U << IOPORT_PFC_OFFSET), ///< P05_7 / GPTn / GTIOC15B + IOPORT_PIN_P057_PFC_03_CMTW1_TOC1 = (0x03U << IOPORT_PFC_OFFSET), ///< P05_7 / CMTWn / CMTW1_TOC1 + IOPORT_PIN_P057_PFC_04_TXD4_SDA4_MOSI4 = (0x04U << IOPORT_PFC_OFFSET), ///< P05_7 / SCIn / TXD4_SDA4_MOSI4 + IOPORT_PIN_P057_PFC_05_SPI_SSL23 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_7 / SPIn / SPI_SSL23 + IOPORT_PIN_P060_PFC_00_ETH1_TXD3 = (0x00U << IOPORT_PFC_OFFSET), ///< P06_0 / ETHER_ETHn / ETH1_TXD3 + IOPORT_PIN_P060_PFC_01_D19 = (0x01U << IOPORT_PFC_OFFSET), ///< P06_0 / BSC / D19 + IOPORT_PIN_P060_PFC_02_GTIOC16A = (0x02U << IOPORT_PFC_OFFSET), ///< P06_0 / GPTn / GTIOC16A + IOPORT_PIN_P060_PFC_03_CMTW1_TOC0 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_0 / CMTWn / CMTW1_TOC0 + IOPORT_PIN_P060_PFC_04_SS4_CTS4_RTS4 = (0x04U << IOPORT_PFC_OFFSET), ///< P06_0 / SCIn / SS4_CTS4_RTS4 + IOPORT_PIN_P060_PFC_05_SPI_SSL23 = (0x05U << IOPORT_PFC_OFFSET), ///< P06_0 / SPIn / SPI_SSL23 + IOPORT_PIN_P060_PFC_06_CANRX1 = (0x06U << IOPORT_PFC_OFFSET), ///< P06_0 / CANFDn / CANRX1 + IOPORT_PIN_P061_PFC_00_ETH1_REFCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P06_1 / ETHER_ETHn / ETH1_REFCLK + IOPORT_PIN_P061_PFC_01_RMII1_REFCLK = (0x01U << IOPORT_PFC_OFFSET), ///< P06_1 / ETHER_ETHn / RMII1_REFCLK + IOPORT_PIN_P061_PFC_02_D22 = (0x02U << IOPORT_PFC_OFFSET), ///< P06_1 / BSC / D22 + IOPORT_PIN_P061_PFC_03_GTIOC16B = (0x03U << IOPORT_PFC_OFFSET), ///< P06_1 / GPTn / GTIOC16B + IOPORT_PIN_P061_PFC_04_CTS4 = (0x04U << IOPORT_PFC_OFFSET), ///< P06_1 / SCIn / CTS4 + IOPORT_PIN_P061_PFC_05_SPI_SSL22 = (0x05U << IOPORT_PFC_OFFSET), ///< P06_1 / SPIn / SPI_SSL22 + IOPORT_PIN_P061_PFC_06_CANTX1 = (0x06U << IOPORT_PFC_OFFSET), ///< P06_1 / CANFDn / CANTX1 + IOPORT_PIN_P062_PFC_00_ETH1_TXD1 = (0x00U << IOPORT_PFC_OFFSET), ///< P06_2 / ETHER_ETHn / ETH1_TXD1 + IOPORT_PIN_P062_PFC_01_D20 = (0x01U << IOPORT_PFC_OFFSET), ///< P06_2 / BSC / D20 + IOPORT_PIN_P062_PFC_02_GTIOC17A = (0x02U << IOPORT_PFC_OFFSET), ///< P06_2 / GPTn / GTIOC17A + IOPORT_PIN_P062_PFC_03_CANRXDP1 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_2 / CANFDn / CANRXDP1 + IOPORT_PIN_P063_PFC_00_ETH1_TXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P06_3 / ETHER_ETHn / ETH1_TXD0 + IOPORT_PIN_P063_PFC_01_D23 = (0x01U << IOPORT_PFC_OFFSET), ///< P06_3 / BSC / D23 + IOPORT_PIN_P063_PFC_02_GTIOC17B = (0x02U << IOPORT_PFC_OFFSET), ///< P06_3 / GPTn / GTIOC17B + IOPORT_PIN_P063_PFC_03_CMTW1_TIC1 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_3 / CMTWn / CMTW1_TIC1 + IOPORT_PIN_P063_PFC_04_DE4 = (0x04U << IOPORT_PFC_OFFSET), ///< P06_3 / SCIn / DE4 + IOPORT_PIN_P063_PFC_05_SPI_MISO1 = (0x05U << IOPORT_PFC_OFFSET), ///< P06_3 / SPIn / SPI_MISO1 + IOPORT_PIN_P063_PFC_06_CANTXDP1 = (0x06U << IOPORT_PFC_OFFSET), ///< P06_3 / CANFDn / CANTXDP1 + IOPORT_PIN_P064_PFC_00_ETH1_TXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P06_4 / ETHER_ETHn / ETH1_TXCLK + IOPORT_PIN_P064_PFC_01_D24 = (0x01U << IOPORT_PFC_OFFSET), ///< P06_4 / BSC / D24 + IOPORT_PIN_P064_PFC_02_GTIOC11A = (0x02U << IOPORT_PFC_OFFSET), ///< P06_4 / GPTn / GTIOC11A + IOPORT_PIN_P064_PFC_03_SPI_MOSI1 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_4 / SPIn / SPI_MOSI1 + IOPORT_PIN_P065_PFC_00_ETH1_TXEN = (0x00U << IOPORT_PFC_OFFSET), ///< P06_5 / ETHER_ETHn / ETH1_TXEN + IOPORT_PIN_P065_PFC_01_D25 = (0x01U << IOPORT_PFC_OFFSET), ///< P06_5 / BSC / D25 + IOPORT_PIN_P065_PFC_02_GTIOC11B = (0x02U << IOPORT_PFC_OFFSET), ///< P06_5 / GPTn / GTIOC11B + IOPORT_PIN_P066_PFC_00_ETH1_RXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P06_6 / ETHER_ETHn / ETH1_RXD0 + IOPORT_PIN_P066_PFC_01_D21 = (0x01U << IOPORT_PFC_OFFSET), ///< P06_6 / BSC / D21 + IOPORT_PIN_P066_PFC_02_GTIOC12A = (0x02U << IOPORT_PFC_OFFSET), ///< P06_6 / GPTn / GTIOC12A + IOPORT_PIN_P066_PFC_03_SPI_SSL10 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_6 / SPIn / SPI_SSL10 + IOPORT_PIN_P067_PFC_00_ETH1_RXD1 = (0x00U << IOPORT_PFC_OFFSET), ///< P06_7 / ETHER_ETHn / ETH1_RXD1 + IOPORT_PIN_P067_PFC_01_D26 = (0x01U << IOPORT_PFC_OFFSET), ///< P06_7 / BSC / D26 + IOPORT_PIN_P067_PFC_02_GTIOC12B = (0x02U << IOPORT_PFC_OFFSET), ///< P06_7 / GPTn / GTIOC12B + IOPORT_PIN_P067_PFC_03_SPI_SSL11 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_7 / SPIn / SPI_SSL11 + IOPORT_PIN_P070_PFC_00_ETH1_RXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P07_0 / ETHER_ETHn / ETH1_RXD2 + IOPORT_PIN_P070_PFC_01_D27 = (0x01U << IOPORT_PFC_OFFSET), ///< P07_0 / BSC / D27 + IOPORT_PIN_P070_PFC_02_GTIOC13A = (0x02U << IOPORT_PFC_OFFSET), ///< P07_0 / GPTn / GTIOC13A + IOPORT_PIN_P071_PFC_00_ETH1_RXD3 = (0x00U << IOPORT_PFC_OFFSET), ///< P07_1 / ETHER_ETHn / ETH1_RXD3 + IOPORT_PIN_P071_PFC_01_D28 = (0x01U << IOPORT_PFC_OFFSET), ///< P07_1 / BSC / D28 + IOPORT_PIN_P071_PFC_02_GTIOC13B = (0x02U << IOPORT_PFC_OFFSET), ///< P07_1 / GPTn / GTIOC13B + IOPORT_PIN_P072_PFC_00_ETH1_RXDV = (0x00U << IOPORT_PFC_OFFSET), ///< P07_2 / ETHER_ETHn / ETH1_RXDV + IOPORT_PIN_P072_PFC_01_D29 = (0x01U << IOPORT_PFC_OFFSET), ///< P07_2 / BSC / D29 + IOPORT_PIN_P073_PFC_00_ETH1_RXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P07_3 / ETHER_ETHn / ETH1_RXCLK + IOPORT_PIN_P073_PFC_01_D30 = (0x01U << IOPORT_PFC_OFFSET), ///< P07_3 / BSC / D30 + IOPORT_PIN_P074_PFC_00_IRQ1 = (0x00U << IOPORT_PFC_OFFSET), ///< P07_4 / IRQ / IRQ1 + IOPORT_PIN_P074_PFC_01_ADTRG0 = (0x01U << IOPORT_PFC_OFFSET), ///< P07_4 / ADCn / ADTRG0 + IOPORT_PIN_P074_PFC_02_USB_VBUSIN = (0x02U << IOPORT_PFC_OFFSET), ///< P07_4 / USB_HS / USB_VBUSIN + IOPORT_PIN_P075_PFC_00_A21 = (0x00U << IOPORT_PFC_OFFSET), ///< P07_5 / BSC / A21 + IOPORT_PIN_P075_PFC_01_D22 = (0x01U << IOPORT_PFC_OFFSET), ///< P07_5 / BSC / D22 + IOPORT_PIN_P076_PFC_00_A22 = (0x00U << IOPORT_PFC_OFFSET), ///< P07_6 / BSC / A22 + IOPORT_PIN_P076_PFC_01_D23 = (0x01U << IOPORT_PFC_OFFSET), ///< P07_6 / BSC / D23 + IOPORT_PIN_P076_PFC_02_SPI_SSL21 = (0x02U << IOPORT_PFC_OFFSET), ///< P07_6 / SPIn / SPI_SSL21 + IOPORT_PIN_P077_PFC_00_ETHSW_LPI1 = (0x00U << IOPORT_PFC_OFFSET), ///< P07_7 / ETHER_ETHSW / ETHSW_LPI1 + IOPORT_PIN_P077_PFC_01_A23 = (0x01U << IOPORT_PFC_OFFSET), ///< P07_7 / BSC / A23 + IOPORT_PIN_P077_PFC_02_D24 = (0x02U << IOPORT_PFC_OFFSET), ///< P07_7 / BSC / D24 + IOPORT_PIN_P080_PFC_00_ETHSW_LPI0 = (0x00U << IOPORT_PFC_OFFSET), ///< P08_0 / ETHER_ETHSW / ETHSW_LPI0 + IOPORT_PIN_P080_PFC_01_A24 = (0x01U << IOPORT_PFC_OFFSET), ///< P08_0 / BSC / A24 + IOPORT_PIN_P080_PFC_02_D25 = (0x02U << IOPORT_PFC_OFFSET), ///< P08_0 / BSC / D25 + IOPORT_PIN_P081_PFC_00_ETHSW_LPI2 = (0x00U << IOPORT_PFC_OFFSET), ///< P08_1 / ETHER_ETHSW / ETHSW_LPI2 + IOPORT_PIN_P081_PFC_01_A25 = (0x01U << IOPORT_PFC_OFFSET), ///< P08_1 / BSC / A25 + IOPORT_PIN_P081_PFC_02_D26 = (0x02U << IOPORT_PFC_OFFSET), ///< P08_1 / BSC / D26 + IOPORT_PIN_P081_PFC_03_USB_VBUSEN = (0x03U << IOPORT_PFC_OFFSET), ///< P08_1 / USB_HS / USB_VBUSEN + IOPORT_PIN_P082_PFC_00_GMAC_PTPTRG0 = (0x00U << IOPORT_PFC_OFFSET), ///< P08_2 / ETHER_GMAC / GMAC_PTPTRG0 + IOPORT_PIN_P082_PFC_01_D27 = (0x01U << IOPORT_PFC_OFFSET), ///< P08_2 / BSC / D27 + IOPORT_PIN_P082_PFC_02_ESC_LATCH0 = (0x02U << IOPORT_PFC_OFFSET), ///< P08_2 / ETHER_ESC / ESC_LATCH0 + IOPORT_PIN_P082_PFC_03_ESC_LATCH1 = (0x03U << IOPORT_PFC_OFFSET), ///< P08_2 / ETHER_ESC / ESC_LATCH1 + IOPORT_PIN_P083_PFC_00_ETHSW_PTPOUT0 = (0x00U << IOPORT_PFC_OFFSET), ///< P08_3 / ETHER_ETHSW / ETHSW_PTPOUT0 + IOPORT_PIN_P083_PFC_01_D28 = (0x01U << IOPORT_PFC_OFFSET), ///< P08_3 / BSC / D28 + IOPORT_PIN_P083_PFC_02_ESC_SYNC0 = (0x02U << IOPORT_PFC_OFFSET), ///< P08_3 / ETHER_ESC / ESC_SYNC0 + IOPORT_PIN_P083_PFC_03_ESC_SYNC1 = (0x03U << IOPORT_PFC_OFFSET), ///< P08_3 / ETHER_ESC / ESC_SYNC1 + IOPORT_PIN_P084_PFC_00_ETH0_RXD3 = (0x00U << IOPORT_PFC_OFFSET), ///< P08_4 / ETHER_ETHn / ETH0_RXD3 + IOPORT_PIN_P084_PFC_01_D31 = (0x01U << IOPORT_PFC_OFFSET), ///< P08_4 / BSC / D31 + IOPORT_PIN_P084_PFC_02_MTIOC6A = (0x02U << IOPORT_PFC_OFFSET), ///< P08_4 / MTU3n / MTIOC6A + IOPORT_PIN_P085_PFC_00_ETH0_RXDV = (0x00U << IOPORT_PFC_OFFSET), ///< P08_5 / ETHER_ETHn / ETH0_RXDV + IOPORT_PIN_P085_PFC_01_MTIOC6B = (0x01U << IOPORT_PFC_OFFSET), ///< P08_5 / MTU3n / MTIOC6B + IOPORT_PIN_P086_PFC_00_ETH0_RXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P08_6 / ETHER_ETHn / ETH0_RXCLK + IOPORT_PIN_P086_PFC_01_MTIOC6C = (0x01U << IOPORT_PFC_OFFSET), ///< P08_6 / MTU3n / MTIOC6C + IOPORT_PIN_P087_PFC_00_GMAC_MDC = (0x00U << IOPORT_PFC_OFFSET), ///< P08_7 / ETHER_GMAC / GMAC_MDC + IOPORT_PIN_P087_PFC_01_ETHSW_MDC = (0x01U << IOPORT_PFC_OFFSET), ///< P08_7 / ETHER_ETHSW / ETHSW_MDC + IOPORT_PIN_P087_PFC_02_D29 = (0x02U << IOPORT_PFC_OFFSET), ///< P08_7 / BSC / D29 + IOPORT_PIN_P087_PFC_03_ESC_MDC = (0x03U << IOPORT_PFC_OFFSET), ///< P08_7 / ETHER_ESC / ESC_MDC + IOPORT_PIN_P087_PFC_04_MTIOC6D = (0x04U << IOPORT_PFC_OFFSET), ///< P08_7 / MTU3n / MTIOC6D + IOPORT_PIN_P090_PFC_00_GMAC_MDIO = (0x00U << IOPORT_PFC_OFFSET), ///< P09_0 / ETHER_GMAC / GMAC_MDIO + IOPORT_PIN_P090_PFC_01_ETHSW_MDIO = (0x01U << IOPORT_PFC_OFFSET), ///< P09_0 / ETHER_ETHSW / ETHSW_MDIO + IOPORT_PIN_P090_PFC_02_D30 = (0x02U << IOPORT_PFC_OFFSET), ///< P09_0 / BSC / D30 + IOPORT_PIN_P090_PFC_03_ESC_MDIO = (0x03U << IOPORT_PFC_OFFSET), ///< P09_0 / ETHER_ESC / ESC_MDIO + IOPORT_PIN_P090_PFC_04_MTIOC7A = (0x04U << IOPORT_PFC_OFFSET), ///< P09_0 / MTU3n / MTIOC7A + IOPORT_PIN_P091_PFC_00_ETH0_REFCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P09_1 / ETHER_ETHn / ETH0_REFCLK + IOPORT_PIN_P091_PFC_01_RMII0_REFCLK = (0x01U << IOPORT_PFC_OFFSET), ///< P09_1 / ETHER_ETHn / RMII0_REFCLK + IOPORT_PIN_P091_PFC_02_MTIOC7B = (0x02U << IOPORT_PFC_OFFSET), ///< P09_1 / MTU3n / MTIOC7B + IOPORT_PIN_P092_PFC_00_IRQ0 = (0x00U << IOPORT_PFC_OFFSET), ///< P09_2 / IRQ / IRQ0 + IOPORT_PIN_P092_PFC_01_ETH0_RXER = (0x01U << IOPORT_PFC_OFFSET), ///< P09_2 / ETHER_ETHn / ETH0_RXER + IOPORT_PIN_P092_PFC_02_D31 = (0x02U << IOPORT_PFC_OFFSET), ///< P09_2 / BSC / D31 + IOPORT_PIN_P092_PFC_03_MTIOC7C = (0x03U << IOPORT_PFC_OFFSET), ///< P09_2 / MTU3n / MTIOC7C + IOPORT_PIN_P093_PFC_00_ETH0_TXD3 = (0x00U << IOPORT_PFC_OFFSET), ///< P09_3 / ETHER_ETHn / ETH0_TXD3 + IOPORT_PIN_P093_PFC_01_MTIOC7D = (0x01U << IOPORT_PFC_OFFSET), ///< P09_3 / MTU3n / MTIOC7D + IOPORT_PIN_P094_PFC_00_ETH0_TXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P09_4 / ETHER_ETHn / ETH0_TXD2 + IOPORT_PIN_P095_PFC_00_ETH0_TXD1 = (0x00U << IOPORT_PFC_OFFSET), ///< P09_5 / ETHER_ETHn / ETH0_TXD1 + IOPORT_PIN_P096_PFC_00_ETH0_TXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P09_6 / ETHER_ETHn / ETH0_TXD0 + IOPORT_PIN_P097_PFC_00_ETH0_TXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P09_7 / ETHER_ETHn / ETH0_TXCLK + IOPORT_PIN_P100_PFC_00_ETH0_TXEN = (0x00U << IOPORT_PFC_OFFSET), ///< P10_0 / ETHER_ETHn / ETH0_TXEN + IOPORT_PIN_P101_PFC_00_ETH0_RXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P10_1 / ETHER_ETHn / ETH0_RXD0 + IOPORT_PIN_P102_PFC_00_ETH0_RXD1 = (0x00U << IOPORT_PFC_OFFSET), ///< P10_2 / ETHER_ETHn / ETH0_RXD1 + IOPORT_PIN_P103_PFC_00_ETH0_RXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P10_3 / ETHER_ETHn / ETH0_RXD2 + IOPORT_PIN_P103_PFC_01_RTCAT1HZ = (0x01U << IOPORT_PFC_OFFSET), ///< P10_3 / RTC / RTCAT1HZ + IOPORT_PIN_P104_PFC_00_IRQ11 = (0x00U << IOPORT_PFC_OFFSET), ///< P10_4 / IRQ / IRQ11 + IOPORT_PIN_P104_PFC_01_ETHSW_PHYLINK0 = (0x01U << IOPORT_PFC_OFFSET), ///< P10_4 / ETHER_ETHSW / ETHSW_PHYLINK0 + IOPORT_PIN_P104_PFC_02_WE2_DQMUL = (0x02U << IOPORT_PFC_OFFSET), ///< P10_4 / BSC / WE2_DQMUL + IOPORT_PIN_P104_PFC_03_ESC_PHYLINK0 = (0x03U << IOPORT_PFC_OFFSET), ///< P10_4 / ETHER_ESC / ESC_PHYLINK0 + IOPORT_PIN_P105_PFC_00_IRQ2 = (0x00U << IOPORT_PFC_OFFSET), ///< P10_5 / IRQ / IRQ2 + IOPORT_PIN_P105_PFC_01_ETH2_CRS = (0x01U << IOPORT_PFC_OFFSET), ///< P10_5 / ETHER_ETHn / ETH2_CRS + IOPORT_PIN_P106_PFC_00_XSPI1_INT1 = (0x00U << IOPORT_PFC_OFFSET), ///< P10_6 / XSPIn / XSPI1_INT1 + IOPORT_PIN_P106_PFC_01_ETH2_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P10_6 / ETHER_ETHn / ETH2_COL + IOPORT_PIN_P107_PFC_00_XSPI1_INT0 = (0x00U << IOPORT_PFC_OFFSET), ///< P10_7 / XSPIn / XSPI1_INT0 + IOPORT_PIN_P107_PFC_01_ETH2_TXER = (0x01U << IOPORT_PFC_OFFSET), ///< P10_7 / ETHER_ETHn / ETH2_TXER + IOPORT_PIN_P110_PFC_00_XSPI1_ECS1 = (0x00U << IOPORT_PFC_OFFSET), ///< P11_0 / XSPIn / XSPI1_ECS1 + IOPORT_PIN_P110_PFC_01_ETH1_CRS = (0x01U << IOPORT_PFC_OFFSET), ///< P11_0 / ETHER_ETHn / ETH1_CRS + IOPORT_PIN_P111_PFC_00_XSPI1_WP1 = (0x00U << IOPORT_PFC_OFFSET), ///< P11_1 / XSPIn / XSPI1_WP1 + IOPORT_PIN_P111_PFC_01_ETH1_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P11_1 / ETHER_ETHn / ETH1_COL + IOPORT_PIN_P111_PFC_02_MTIOC1A = (0x02U << IOPORT_PFC_OFFSET), ///< P11_1 / MTU3n / MTIOC1A + IOPORT_PIN_P111_PFC_03_GTIOC11A = (0x03U << IOPORT_PFC_OFFSET), ///< P11_1 / GPTn / GTIOC11A + IOPORT_PIN_P112_PFC_00_XSPI1_WP0 = (0x00U << IOPORT_PFC_OFFSET), ///< P11_2 / XSPIn / XSPI1_WP0 + IOPORT_PIN_P112_PFC_01_ETH1_TXER = (0x01U << IOPORT_PFC_OFFSET), ///< P11_2 / ETHER_ETHn / ETH1_TXER + IOPORT_PIN_P112_PFC_02_MTIOC1B = (0x02U << IOPORT_PFC_OFFSET), ///< P11_2 / MTU3n / MTIOC1B + IOPORT_PIN_P112_PFC_03_GTIOC11B = (0x03U << IOPORT_PFC_OFFSET), ///< P11_2 / GPTn / GTIOC11B + IOPORT_PIN_P113_PFC_00_XSPI1_ECS0 = (0x00U << IOPORT_PFC_OFFSET), ///< P11_3 / XSPIn / XSPI1_ECS0 + IOPORT_PIN_P113_PFC_01_ETH0_TXER = (0x01U << IOPORT_PFC_OFFSET), ///< P11_3 / ETHER_ETHn / ETH0_TXER + IOPORT_PIN_P113_PFC_02_MTIOC2A = (0x02U << IOPORT_PFC_OFFSET), ///< P11_3 / MTU3n / MTIOC2A + IOPORT_PIN_P113_PFC_03_GTIOC12A = (0x03U << IOPORT_PFC_OFFSET), ///< P11_3 / GPTn / GTIOC12A + IOPORT_PIN_P114_PFC_00_XSPI1_RSTO1 = (0x00U << IOPORT_PFC_OFFSET), ///< P11_4 / XSPIn / XSPI1_RSTO1 + IOPORT_PIN_P114_PFC_01_ETH0_CRS = (0x01U << IOPORT_PFC_OFFSET), ///< P11_4 / ETHER_ETHn / ETH0_CRS + IOPORT_PIN_P114_PFC_02_MTIOC2B = (0x02U << IOPORT_PFC_OFFSET), ///< P11_4 / MTU3n / MTIOC2B + IOPORT_PIN_P114_PFC_03_GTIOC12B = (0x03U << IOPORT_PFC_OFFSET), ///< P11_4 / GPTn / GTIOC12B + IOPORT_PIN_P115_PFC_00_XSPI1_RSTO0 = (0x00U << IOPORT_PFC_OFFSET), ///< P11_5 / XSPIn / XSPI1_RSTO0 + IOPORT_PIN_P115_PFC_01_MTIOC0B = (0x01U << IOPORT_PFC_OFFSET), ///< P11_5 / MTU3n / MTIOC0B + IOPORT_PIN_P115_PFC_02_ENCIF0 = (0x02U << IOPORT_PFC_OFFSET), ///< P11_5 / ENCIF / ENCIF0 + IOPORT_PIN_P116_PFC_00_XSPI1_RESET1 = (0x00U << IOPORT_PFC_OFFSET), ///< P11_6 / XSPIn / XSPI1_RESET1 + IOPORT_PIN_P116_PFC_01_ETH0_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P11_6 / ETHER_ETHn / ETH0_COL + IOPORT_PIN_P116_PFC_02_MTIOC8C = (0x02U << IOPORT_PFC_OFFSET), ///< P11_6 / MTU3n / MTIOC8C + IOPORT_PIN_P116_PFC_03_ENCIF1 = (0x03U << IOPORT_PFC_OFFSET), ///< P11_6 / ENCIF / ENCIF1 + IOPORT_PIN_P117_PFC_00_XSPI1_DS = (0x00U << IOPORT_PFC_OFFSET), ///< P11_7 / XSPIn / XSPI1_DS + IOPORT_PIN_P117_PFC_01_MTIOC8D = (0x01U << IOPORT_PFC_OFFSET), ///< P11_7 / MTU3n / MTIOC8D + IOPORT_PIN_P117_PFC_02_USB_OVRCUR = (0x02U << IOPORT_PFC_OFFSET), ///< P11_7 / USB_HS / USB_OVRCUR + IOPORT_PIN_P117_PFC_03_ENCIF2 = (0x03U << IOPORT_PFC_OFFSET), ///< P11_7 / ENCIF / ENCIF2 + IOPORT_PIN_P120_PFC_00_XSPI1_IO7 = (0x00U << IOPORT_PFC_OFFSET), ///< P12_0 / XSPIn / XSPI1_IO7 + IOPORT_PIN_P120_PFC_01_GTADSMP1 = (0x01U << IOPORT_PFC_OFFSET), ///< P12_0 / GPT / GTADSMP1 + IOPORT_PIN_P120_PFC_02_ENCIF3 = (0x02U << IOPORT_PFC_OFFSET), ///< P12_0 / ENCIF / ENCIF3 + IOPORT_PIN_P121_PFC_00_XSPI1_IO6 = (0x00U << IOPORT_PFC_OFFSET), ///< P12_1 / XSPIn / XSPI1_IO6 + IOPORT_PIN_P121_PFC_01_GTADSML0 = (0x01U << IOPORT_PFC_OFFSET), ///< P12_1 / GPT / GTADSML0 + IOPORT_PIN_P121_PFC_02_ENCIF4 = (0x02U << IOPORT_PFC_OFFSET), ///< P12_1 / ENCIF / ENCIF4 + IOPORT_PIN_P122_PFC_00_XSPI1_IO5 = (0x00U << IOPORT_PFC_OFFSET), ///< P12_2 / XSPIn / XSPI1_IO5 + IOPORT_PIN_P122_PFC_01_GTADSML1 = (0x01U << IOPORT_PFC_OFFSET), ///< P12_2 / GPT / GTADSML1 + IOPORT_PIN_P122_PFC_02_ENCIF5 = (0x02U << IOPORT_PFC_OFFSET), ///< P12_2 / ENCIF / ENCIF5 + IOPORT_PIN_P123_PFC_00_XSPI1_IO4 = (0x00U << IOPORT_PFC_OFFSET), ///< P12_3 / XSPIn / XSPI1_IO4 + IOPORT_PIN_P123_PFC_01_GTADSMP0 = (0x01U << IOPORT_PFC_OFFSET), ///< P12_3 / GPT / GTADSMP0 + IOPORT_PIN_P123_PFC_02_ENCIF6 = (0x02U << IOPORT_PFC_OFFSET), ///< P12_3 / ENCIF / ENCIF6 + IOPORT_PIN_P124_PFC_00_XSPI1_RESET0 = (0x00U << IOPORT_PFC_OFFSET), ///< P12_4 / XSPIn / XSPI1_RESET0 + IOPORT_PIN_P124_PFC_01_ETH1_CRS = (0x01U << IOPORT_PFC_OFFSET), ///< P12_4 / ETHER_ETHn / ETH1_CRS + IOPORT_PIN_P124_PFC_02_TRACEDATA0 = (0x02U << IOPORT_PFC_OFFSET), ///< P12_4 / TRACE / TRACEDATA0 + IOPORT_PIN_P124_PFC_03_D15 = (0x03U << IOPORT_PFC_OFFSET), ///< P12_4 / BSC / D15 + IOPORT_PIN_P124_PFC_04_MTIOC8B = (0x04U << IOPORT_PFC_OFFSET), ///< P12_4 / MTU3n / MTIOC8B + IOPORT_PIN_P124_PFC_05_GTIOC8B = (0x05U << IOPORT_PFC_OFFSET), ///< P12_4 / GPTn / GTIOC8B + IOPORT_PIN_P124_PFC_06_SPI_SSL01 = (0x06U << IOPORT_PFC_OFFSET), ///< P12_4 / SPIn / SPI_SSL01 + IOPORT_PIN_P124_PFC_07_ENCIF7 = (0x07U << IOPORT_PFC_OFFSET), ///< P12_4 / ENCIF / ENCIF7 + IOPORT_PIN_P125_PFC_00_XSPI1_IO3 = (0x00U << IOPORT_PFC_OFFSET), ///< P12_5 / XSPIn / XSPI1_IO3 + IOPORT_PIN_P125_PFC_01_TRACEDATA1 = (0x01U << IOPORT_PFC_OFFSET), ///< P12_5 / TRACE / TRACEDATA1 + IOPORT_PIN_P125_PFC_02_D14 = (0x02U << IOPORT_PFC_OFFSET), ///< P12_5 / BSC / D14 + IOPORT_PIN_P125_PFC_03_MTIOC8A = (0x03U << IOPORT_PFC_OFFSET), ///< P12_5 / MTU3n / MTIOC8A + IOPORT_PIN_P125_PFC_04_GTIOC8A = (0x04U << IOPORT_PFC_OFFSET), ///< P12_5 / GPTn / GTIOC8A + IOPORT_PIN_P125_PFC_05_SPI_SSL03 = (0x05U << IOPORT_PFC_OFFSET), ///< P12_5 / SPIn / SPI_SSL03 + IOPORT_PIN_P125_PFC_06_DACK = (0x06U << IOPORT_PFC_OFFSET), ///< P12_5 / DMAC / DACK + IOPORT_PIN_P125_PFC_07_ENCIF0 = (0x07U << IOPORT_PFC_OFFSET), ///< P12_5 / ENCIF / ENCIF0 + IOPORT_PIN_P126_PFC_00_IRQ3 = (0x00U << IOPORT_PFC_OFFSET), ///< P12_6 / IRQ / IRQ3 + IOPORT_PIN_P126_PFC_01_XSPI1_IO2 = (0x01U << IOPORT_PFC_OFFSET), ///< P12_6 / XSPIn / XSPI1_IO2 + IOPORT_PIN_P126_PFC_02_TRACEDATA2 = (0x02U << IOPORT_PFC_OFFSET), ///< P12_6 / TRACE / TRACEDATA2 + IOPORT_PIN_P126_PFC_03_D13 = (0x03U << IOPORT_PFC_OFFSET), ///< P12_6 / BSC / D13 + IOPORT_PIN_P126_PFC_04_MTCLKA = (0x04U << IOPORT_PFC_OFFSET), ///< P12_6 / MTU3 / MTCLKA + IOPORT_PIN_P126_PFC_05_DE1 = (0x05U << IOPORT_PFC_OFFSET), ///< P12_6 / SCIn / DE1 + IOPORT_PIN_P126_PFC_06_SPI_SSL02 = (0x06U << IOPORT_PFC_OFFSET), ///< P12_6 / SPIn / SPI_SSL02 + IOPORT_PIN_P126_PFC_07_MCLK5 = (0x07U << IOPORT_PFC_OFFSET), ///< P12_6 / DSMIFn / MCLK5 + IOPORT_PIN_P126_PFC_08_ENCIF1 = (0x08U << IOPORT_PFC_OFFSET), ///< P12_6 / ENCIF / ENCIF1 + IOPORT_PIN_P127_PFC_00_IRQ4 = (0x00U << IOPORT_PFC_OFFSET), ///< P12_7 / IRQ / IRQ4 + IOPORT_PIN_P127_PFC_01_XSPI1_IO1 = (0x01U << IOPORT_PFC_OFFSET), ///< P12_7 / XSPIn / XSPI1_IO1 + IOPORT_PIN_P127_PFC_02_TRACEDATA3 = (0x02U << IOPORT_PFC_OFFSET), ///< P12_7 / TRACE / TRACEDATA3 + IOPORT_PIN_P127_PFC_03_D12 = (0x03U << IOPORT_PFC_OFFSET), ///< P12_7 / BSC / D12 + IOPORT_PIN_P127_PFC_04_MTCLKB = (0x04U << IOPORT_PFC_OFFSET), ///< P12_7 / MTU3 / MTCLKB + IOPORT_PIN_P127_PFC_05_MTCLKC = (0x05U << IOPORT_PFC_OFFSET), ///< P12_7 / MTU3 / MTCLKC + IOPORT_PIN_P127_PFC_06_SCK1 = (0x06U << IOPORT_PFC_OFFSET), ///< P12_7 / SCIn / SCK1 + IOPORT_PIN_P127_PFC_07_SPI_SSL01 = (0x07U << IOPORT_PFC_OFFSET), ///< P12_7 / SPIn / SPI_SSL01 + IOPORT_PIN_P127_PFC_08_MDAT5 = (0x08U << IOPORT_PFC_OFFSET), ///< P12_7 / DSMIFn / MDAT5 + IOPORT_PIN_P127_PFC_09_ENCIF2 = (0x09U << IOPORT_PFC_OFFSET), ///< P12_7 / ENCIF / ENCIF2 + IOPORT_PIN_P130_PFC_00_XSPI1_IO0 = (0x00U << IOPORT_PFC_OFFSET), ///< P13_0 / XSPIn / XSPI1_IO0 + IOPORT_PIN_P130_PFC_01_TRACEDATA4 = (0x01U << IOPORT_PFC_OFFSET), ///< P13_0 / TRACE / TRACEDATA4 + IOPORT_PIN_P130_PFC_02_D11 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_0 / BSC / D11 + IOPORT_PIN_P130_PFC_03_MTCLKC = (0x03U << IOPORT_PFC_OFFSET), ///< P13_0 / MTU3 / MTCLKC + IOPORT_PIN_P130_PFC_04_MTCLKB = (0x04U << IOPORT_PFC_OFFSET), ///< P13_0 / MTU3 / MTCLKB + IOPORT_PIN_P130_PFC_05_GTIOC9A = (0x05U << IOPORT_PFC_OFFSET), ///< P13_0 / GPTn / GTIOC9A + IOPORT_PIN_P130_PFC_06_RXD1_SCL1_MISO1 = (0x06U << IOPORT_PFC_OFFSET), ///< P13_0 / SCIn / RXD1_SCL1_MISO1 + IOPORT_PIN_P130_PFC_07_SPI_SSL00 = (0x07U << IOPORT_PFC_OFFSET), ///< P13_0 / SPIn / SPI_SSL00 + IOPORT_PIN_P130_PFC_08_MCLK0 = (0x08U << IOPORT_PFC_OFFSET), ///< P13_0 / DSMIFn / MCLK0 + IOPORT_PIN_P130_PFC_09_ENCIF3 = (0x09U << IOPORT_PFC_OFFSET), ///< P13_0 / ENCIF / ENCIF3 + IOPORT_PIN_P131_PFC_00_XSPI1_CS0 = (0x00U << IOPORT_PFC_OFFSET), ///< P13_1 / XSPIn / XSPI1_CS0 + IOPORT_PIN_P131_PFC_01_TRACEDATA5 = (0x01U << IOPORT_PFC_OFFSET), ///< P13_1 / TRACE / TRACEDATA5 + IOPORT_PIN_P131_PFC_02_D10 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_1 / BSC / D10 + IOPORT_PIN_P131_PFC_03_MTCLKD = (0x03U << IOPORT_PFC_OFFSET), ///< P13_1 / MTU3 / MTCLKD + IOPORT_PIN_P131_PFC_04_GTIOC9B = (0x04U << IOPORT_PFC_OFFSET), ///< P13_1 / GPTn / GTIOC9B + IOPORT_PIN_P131_PFC_05_TXD1_SDA1_MOSI1 = (0x05U << IOPORT_PFC_OFFSET), ///< P13_1 / SCIn / TXD1_SDA1_MOSI1 + IOPORT_PIN_P131_PFC_06_SPI_MOSI0 = (0x06U << IOPORT_PFC_OFFSET), ///< P13_1 / SPIn / SPI_MOSI0 + IOPORT_PIN_P131_PFC_07_MDAT0 = (0x07U << IOPORT_PFC_OFFSET), ///< P13_1 / DSMIFn / MDAT0 + IOPORT_PIN_P131_PFC_08_ENCIF4 = (0x08U << IOPORT_PFC_OFFSET), ///< P13_1 / ENCIF / ENCIF4 + IOPORT_PIN_P132_PFC_00_IRQ5 = (0x00U << IOPORT_PFC_OFFSET), ///< P13_2 / IRQ / IRQ5 + IOPORT_PIN_P132_PFC_01_XSPI1_CS1 = (0x01U << IOPORT_PFC_OFFSET), ///< P13_2 / XSPIn / XSPI1_CS1 + IOPORT_PIN_P132_PFC_02_ETHSW_PTPOUT2 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_2 / ETHER_ETHSW / ETHSW_PTPOUT2 + IOPORT_PIN_P132_PFC_03_TRACEDATA6 = (0x03U << IOPORT_PFC_OFFSET), ///< P13_2 / TRACE / TRACEDATA6 + IOPORT_PIN_P132_PFC_04_D9 = (0x04U << IOPORT_PFC_OFFSET), ///< P13_2 / BSC / D9 + IOPORT_PIN_P132_PFC_05_ESC_I2CCLK = (0x05U << IOPORT_PFC_OFFSET), ///< P13_2 / ETHER_ESC / ESC_I2CCLK + IOPORT_PIN_P132_PFC_06_MTIOC0A = (0x06U << IOPORT_PFC_OFFSET), ///< P13_2 / MTU3n / MTIOC0A + IOPORT_PIN_P132_PFC_07_GTIOC10A = (0x07U << IOPORT_PFC_OFFSET), ///< P13_2 / GPTn / GTIOC10A + IOPORT_PIN_P132_PFC_08_POE8 = (0x08U << IOPORT_PFC_OFFSET), ///< P13_2 / MTU_POE3 / POE8 + IOPORT_PIN_P132_PFC_09_SS1_CTS1_RTS1 = (0x09U << IOPORT_PFC_OFFSET), ///< P13_2 / SCIn / SS1_CTS1_RTS1 + IOPORT_PIN_P132_PFC_0A_SPI_MISO0 = (0x0AU << IOPORT_PFC_OFFSET), ///< P13_2 / SPIn / SPI_MISO0 + IOPORT_PIN_P132_PFC_0B_IIC_SCL0 = (0x0BU << IOPORT_PFC_OFFSET), ///< P13_2 / IICn / IIC_SCL0 + IOPORT_PIN_P132_PFC_0C_MCLK4 = (0x0CU << IOPORT_PFC_OFFSET), ///< P13_2 / DSMIFn / MCLK4 + IOPORT_PIN_P132_PFC_0D_ENCIF8 = (0x0DU << IOPORT_PFC_OFFSET), ///< P13_2 / ENCIF / ENCIF8 + IOPORT_PIN_P133_PFC_00_XSPI1_CKP = (0x00U << IOPORT_PFC_OFFSET), ///< P13_3 / XSPIn / XSPI1_CKP + IOPORT_PIN_P133_PFC_01_ETHSW_PTPOUT3 = (0x01U << IOPORT_PFC_OFFSET), ///< P13_3 / ETHER_ETHSW / ETHSW_PTPOUT3 + IOPORT_PIN_P133_PFC_02_TRACEDATA7 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_3 / TRACE / TRACEDATA7 + IOPORT_PIN_P133_PFC_03_D8 = (0x03U << IOPORT_PFC_OFFSET), ///< P13_3 / BSC / D8 + IOPORT_PIN_P133_PFC_04_ESC_I2CDATA = (0x04U << IOPORT_PFC_OFFSET), ///< P13_3 / ETHER_ESC / ESC_I2CDATA + IOPORT_PIN_P133_PFC_05_MTIOC0C = (0x05U << IOPORT_PFC_OFFSET), ///< P13_3 / MTU3n / MTIOC0C + IOPORT_PIN_P133_PFC_06_MTIOC0B = (0x06U << IOPORT_PFC_OFFSET), ///< P13_3 / MTU3n / MTIOC0B + IOPORT_PIN_P133_PFC_07_GTIOC10B = (0x07U << IOPORT_PFC_OFFSET), ///< P13_3 / GPTn / GTIOC10B + IOPORT_PIN_P133_PFC_08_CMTW1_TOC0 = (0x08U << IOPORT_PFC_OFFSET), ///< P13_3 / CMTWn / CMTW1_TOC0 + IOPORT_PIN_P133_PFC_09_CTS1 = (0x09U << IOPORT_PFC_OFFSET), ///< P13_3 / SCIn / CTS1 + IOPORT_PIN_P133_PFC_0A_SPI_RSPCK0 = (0x0AU << IOPORT_PFC_OFFSET), ///< P13_3 / SPIn / SPI_RSPCK0 + IOPORT_PIN_P133_PFC_0B_IIC_SDA0 = (0x0BU << IOPORT_PFC_OFFSET), ///< P13_3 / IICn / IIC_SDA0 + IOPORT_PIN_P133_PFC_0C_MDAT4 = (0x0CU << IOPORT_PFC_OFFSET), ///< P13_3 / DSMIFn / MDAT4 + IOPORT_PIN_P133_PFC_0D_ENCIF9 = (0x0DU << IOPORT_PFC_OFFSET), ///< P13_3 / ENCIF / ENCIF9 + IOPORT_PIN_P134_PFC_00_XSPI1_CKN = (0x00U << IOPORT_PFC_OFFSET), ///< P13_4 / XSPIn / XSPI1_CKN + IOPORT_PIN_P134_PFC_01_ESC_RESETOUT = (0x01U << IOPORT_PFC_OFFSET), ///< P13_4 / ETHER_ESC / ESC_RESETOUT + IOPORT_PIN_P134_PFC_02_MTIOC0D = (0x02U << IOPORT_PFC_OFFSET), ///< P13_4 / MTU3n / MTIOC0D + IOPORT_PIN_P134_PFC_03_GTIOC8B = (0x03U << IOPORT_PFC_OFFSET), ///< P13_4 / GPTn / GTIOC8B + IOPORT_PIN_P134_PFC_04_ENCIF10 = (0x04U << IOPORT_PFC_OFFSET), ///< P13_4 / ENCIF / ENCIF10 + IOPORT_PIN_P135_PFC_00_XSPI0_WP1 = (0x00U << IOPORT_PFC_OFFSET), ///< P13_5 / XSPIn / XSPI0_WP1 + IOPORT_PIN_P135_PFC_01_GMAC_PTPTRG0 = (0x01U << IOPORT_PFC_OFFSET), ///< P13_5 / ETHER_GMAC / GMAC_PTPTRG0 + IOPORT_PIN_P135_PFC_02_ESC_LATCH0 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_5 / ETHER_ESC / ESC_LATCH0 + IOPORT_PIN_P135_PFC_03_ESC_LATCH1 = (0x03U << IOPORT_PFC_OFFSET), ///< P13_5 / ETHER_ESC / ESC_LATCH1 + IOPORT_PIN_P135_PFC_04_MTCLKA = (0x04U << IOPORT_PFC_OFFSET), ///< P13_5 / MTU3 / MTCLKA + IOPORT_PIN_P135_PFC_05_SPI_RSPCK1 = (0x05U << IOPORT_PFC_OFFSET), ///< P13_5 / SPIn / SPI_RSPCK1 + IOPORT_PIN_P136_PFC_00_XSPI0_WP0 = (0x00U << IOPORT_PFC_OFFSET), ///< P13_6 / XSPIn / XSPI0_WP0 + IOPORT_PIN_P136_PFC_01_ETHSW_PTPOUT0 = (0x01U << IOPORT_PFC_OFFSET), ///< P13_6 / ETHER_ETHSW / ETHSW_PTPOUT0 + IOPORT_PIN_P136_PFC_02_ESC_SYNC0 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_6 / ETHER_ESC / ESC_SYNC0 + IOPORT_PIN_P136_PFC_03_ESC_SYNC1 = (0x03U << IOPORT_PFC_OFFSET), ///< P13_6 / ETHER_ESC / ESC_SYNC1 + IOPORT_PIN_P136_PFC_04_MTCLKB = (0x04U << IOPORT_PFC_OFFSET), ///< P13_6 / MTU3 / MTCLKB + IOPORT_PIN_P137_PFC_00_XSPI0_ECS1 = (0x00U << IOPORT_PFC_OFFSET), ///< P13_7 / XSPIn / XSPI0_ECS1 + IOPORT_PIN_P137_PFC_01_GMAC_PTPTRG1 = (0x01U << IOPORT_PFC_OFFSET), ///< P13_7 / ETHER_GMAC / GMAC_PTPTRG1 + IOPORT_PIN_P137_PFC_02_ESC_LATCH1 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_7 / ETHER_ESC / ESC_LATCH1 + IOPORT_PIN_P137_PFC_03_ESC_LATCH0 = (0x03U << IOPORT_PFC_OFFSET), ///< P13_7 / ETHER_ESC / ESC_LATCH0 + IOPORT_PIN_P137_PFC_04_MTCLKC = (0x04U << IOPORT_PFC_OFFSET), ///< P13_7 / MTU3 / MTCLKC + IOPORT_PIN_P140_PFC_00_XSPI0_INT0 = (0x00U << IOPORT_PFC_OFFSET), ///< P14_0 / XSPIn / XSPI0_INT0 + IOPORT_PIN_P140_PFC_01_ETHSW_PTPOUT1 = (0x01U << IOPORT_PFC_OFFSET), ///< P14_0 / ETHER_ETHSW / ETHSW_PTPOUT1 + IOPORT_PIN_P140_PFC_02_ESC_SYNC1 = (0x02U << IOPORT_PFC_OFFSET), ///< P14_0 / ETHER_ESC / ESC_SYNC1 + IOPORT_PIN_P140_PFC_03_ESC_SYNC0 = (0x03U << IOPORT_PFC_OFFSET), ///< P14_0 / ETHER_ESC / ESC_SYNC0 + IOPORT_PIN_P140_PFC_04_MTCLKD = (0x04U << IOPORT_PFC_OFFSET), ///< P14_0 / MTU3 / MTCLKD + IOPORT_PIN_P141_PFC_00_XSPI0_INT1 = (0x00U << IOPORT_PFC_OFFSET), ///< P14_1 / XSPIn / XSPI0_INT1 + IOPORT_PIN_P141_PFC_01_ETH1_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P14_1 / ETHER_ETHn / ETH1_COL + IOPORT_PIN_P141_PFC_03_MTIOC8A = (0x03U << IOPORT_PFC_OFFSET), ///< P14_1 / MTU3n / MTIOC8A + IOPORT_PIN_P141_PFC_04_GTIOC8A = (0x04U << IOPORT_PFC_OFFSET), ///< P14_1 / GPTn / GTIOC8A + IOPORT_PIN_P141_PFC_05_ENCIF11 = (0x05U << IOPORT_PFC_OFFSET), ///< P14_1 / ENCIF / ENCIF11 + IOPORT_PIN_P142_PFC_00_IRQ6 = (0x00U << IOPORT_PFC_OFFSET), ///< P14_2 / IRQ / IRQ6 + IOPORT_PIN_P142_PFC_01_XSPI0_ECS0 = (0x01U << IOPORT_PFC_OFFSET), ///< P14_2 / XSPIn / XSPI0_ECS0 + IOPORT_PIN_P142_PFC_02_ETH0_CRS = (0x02U << IOPORT_PFC_OFFSET), ///< P14_2 / ETHER_ETHn / ETH0_CRS + IOPORT_PIN_P142_PFC_04_MTIOC8B = (0x04U << IOPORT_PFC_OFFSET), ///< P14_2 / MTU3n / MTIOC8B + IOPORT_PIN_P142_PFC_05_GTIOC8B = (0x05U << IOPORT_PFC_OFFSET), ///< P14_2 / GPTn / GTIOC8B + IOPORT_PIN_P142_PFC_06_ENCIF12 = (0x06U << IOPORT_PFC_OFFSET), ///< P14_2 / ENCIF / ENCIF12 + IOPORT_PIN_P143_PFC_00_XSPI0_RSTO1 = (0x00U << IOPORT_PFC_OFFSET), ///< P14_3 / XSPIn / XSPI0_RSTO1 + IOPORT_PIN_P143_PFC_01_ETH0_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P14_3 / ETHER_ETHn / ETH0_COL + IOPORT_PIN_P143_PFC_04_MTIOC0A = (0x04U << IOPORT_PFC_OFFSET), ///< P14_3 / MTU3n / MTIOC0A + IOPORT_PIN_P143_PFC_05_ENCIF13 = (0x05U << IOPORT_PFC_OFFSET), ///< P14_3 / ENCIF / ENCIF13 + IOPORT_PIN_P144_PFC_00_XSPI0_DS = (0x00U << IOPORT_PFC_OFFSET), ///< P14_4 / XSPIn / XSPI0_DS + IOPORT_PIN_P144_PFC_01_BS = (0x01U << IOPORT_PFC_OFFSET), ///< P14_4 / BSC / BS + IOPORT_PIN_P144_PFC_02_ESC_IRQ = (0x02U << IOPORT_PFC_OFFSET), ///< P14_4 / ETHER_ESC / ESC_IRQ + IOPORT_PIN_P144_PFC_03_MTIOC0B = (0x03U << IOPORT_PFC_OFFSET), ///< P14_4 / MTU3n / MTIOC0B + IOPORT_PIN_P145_PFC_00_XSPI0_CKN = (0x00U << IOPORT_PFC_OFFSET), ///< P14_5 / XSPIn / XSPI0_CKN + IOPORT_PIN_P145_PFC_01_CS3 = (0x01U << IOPORT_PFC_OFFSET), ///< P14_5 / BSC / CS3 + IOPORT_PIN_P145_PFC_02_POE8 = (0x02U << IOPORT_PFC_OFFSET), ///< P14_5 / MTU_POE3 / POE8 + IOPORT_PIN_P146_PFC_00_XSPI0_CKP = (0x00U << IOPORT_PFC_OFFSET), ///< P14_6 / XSPIn / XSPI0_CKP + IOPORT_PIN_P146_PFC_01_A21 = (0x01U << IOPORT_PFC_OFFSET), ///< P14_6 / BSC / A21 + IOPORT_PIN_P147_PFC_00_XSPI0_IO0 = (0x00U << IOPORT_PFC_OFFSET), ///< P14_7 / XSPIn / XSPI0_IO0 + IOPORT_PIN_P147_PFC_01_A22 = (0x01U << IOPORT_PFC_OFFSET), ///< P14_7 / BSC / A22 + IOPORT_PIN_P147_PFC_02_SCK5 = (0x02U << IOPORT_PFC_OFFSET), ///< P14_7 / SCIn / SCK5 + IOPORT_PIN_P147_PFC_03_SPI_MISO1 = (0x03U << IOPORT_PFC_OFFSET), ///< P14_7 / SPIn / SPI_MISO1 + IOPORT_PIN_P150_PFC_00_XSPI0_IO1 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_0 / XSPIn / XSPI0_IO1 + IOPORT_PIN_P150_PFC_01_A23 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_0 / BSC / A23 + IOPORT_PIN_P150_PFC_02_RXD5_SCL5_MISO5 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_0 / SCIn / RXD5_SCL5_MISO5 + IOPORT_PIN_P150_PFC_03_SPI_MOSI1 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_0 / SPIn / SPI_MOSI1 + IOPORT_PIN_P151_PFC_00_XSPI0_IO2 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_1 / XSPIn / XSPI0_IO2 + IOPORT_PIN_P151_PFC_01_A24 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_1 / BSC / A24 + IOPORT_PIN_P151_PFC_02_MTIOC0C = (0x02U << IOPORT_PFC_OFFSET), ///< P15_1 / MTU3n / MTIOC0C + IOPORT_PIN_P151_PFC_03_TXD5_SDA5_MOSI5 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_1 / SCIn / TXD5_SDA5_MOSI5 + IOPORT_PIN_P151_PFC_04_SPI_SSL10 = (0x04U << IOPORT_PFC_OFFSET), ///< P15_1 / SPIn / SPI_SSL10 + IOPORT_PIN_P152_PFC_00_XSPI0_IO3 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_2 / XSPIn / XSPI0_IO3 + IOPORT_PIN_P152_PFC_01_A25 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_2 / BSC / A25 + IOPORT_PIN_P152_PFC_02_MTIOC0D = (0x02U << IOPORT_PFC_OFFSET), ///< P15_2 / MTU3n / MTIOC0D + IOPORT_PIN_P152_PFC_03_SS5_CTS5_RTS5 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_2 / SCIn / SS5_CTS5_RTS5 + IOPORT_PIN_P152_PFC_04_SPI_SSL11 = (0x04U << IOPORT_PFC_OFFSET), ///< P15_2 / SPIn / SPI_SSL11 + IOPORT_PIN_P153_PFC_00_XSPI0_IO4 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_3 / XSPIn / XSPI0_IO4 + IOPORT_PIN_P153_PFC_01_MTIOC8C = (0x01U << IOPORT_PFC_OFFSET), ///< P15_3 / MTU3n / MTIOC8C + IOPORT_PIN_P153_PFC_02_MCLK1 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_3 / DSMIFn / MCLK1 + IOPORT_PIN_P154_PFC_00_XSPI0_IO5 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_4 / XSPIn / XSPI0_IO5 + IOPORT_PIN_P154_PFC_01_MTIOC8D = (0x01U << IOPORT_PFC_OFFSET), ///< P15_4 / MTU3n / MTIOC8D + IOPORT_PIN_P154_PFC_02_MDAT1 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_4 / DSMIFn / MDAT1 + IOPORT_PIN_P155_PFC_00_XSPI0_IO6 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_5 / XSPIn / XSPI0_IO6 + IOPORT_PIN_P155_PFC_01_MCLK2 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_5 / DSMIFn / MCLK2 + IOPORT_PIN_P156_PFC_00_XSPI0_IO7 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_6 / XSPIn / XSPI0_IO7 + IOPORT_PIN_P156_PFC_01_SPI_SSL12 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_6 / SPIn / SPI_SSL12 + IOPORT_PIN_P156_PFC_02_MDAT2 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_6 / DSMIFn / MDAT2 + IOPORT_PIN_P157_PFC_00_XSPI0_CS0 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_7 / XSPIn / XSPI0_CS0 + IOPORT_PIN_P157_PFC_01_CTS5 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_7 / SCIn / CTS5 + IOPORT_PIN_P157_PFC_02_SPI_SSL13 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_7 / SPIn / SPI_SSL13 + IOPORT_PIN_P157_PFC_03_TEND = (0x03U << IOPORT_PFC_OFFSET), ///< P15_7 / DMAC / TEND + IOPORT_PIN_P157_PFC_04_ENCIF1 = (0x04U << IOPORT_PFC_OFFSET), ///< P15_7 / ENCIF / ENCIF1 + IOPORT_PIN_P160_PFC_00_XSPI0_CS1 = (0x00U << IOPORT_PFC_OFFSET), ///< P16_0 / XSPIn / XSPI0_CS1 + IOPORT_PIN_P160_PFC_01_ETH0_TXER = (0x01U << IOPORT_PFC_OFFSET), ///< P16_0 / ETHER_ETHn / ETH0_TXER + IOPORT_PIN_P160_PFC_02_TXD0_SDA0_MOSI0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_0 / SCIn / TXD0_SDA0_MOSI0 + IOPORT_PIN_P160_PFC_03_SPI_MOSI3 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_0 / SPIn / SPI_MOSI3 + IOPORT_PIN_P160_PFC_04_MCLK3 = (0x04U << IOPORT_PFC_OFFSET), ///< P16_0 / DSMIFn / MCLK3 + IOPORT_PIN_P160_PFC_05_ENCIF0 = (0x05U << IOPORT_PFC_OFFSET), ///< P16_0 / ENCIF / ENCIF0 + IOPORT_PIN_P161_PFC_00_XSPI0_RESET0 = (0x00U << IOPORT_PFC_OFFSET), ///< P16_1 / XSPIn / XSPI0_RESET0 + IOPORT_PIN_P161_PFC_01_CMTW0_TOC1 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_1 / CMTWn / CMTW0_TOC1 + IOPORT_PIN_P161_PFC_02_ADTRG0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_1 / ADCn / ADTRG0 + IOPORT_PIN_P161_PFC_03_RXD0_SCL0_MISO0 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_1 / SCIn / RXD0_SCL0_MISO0 + IOPORT_PIN_P161_PFC_04_SPI_MISO3 = (0x04U << IOPORT_PFC_OFFSET), ///< P16_1 / SPIn / SPI_MISO3 + IOPORT_PIN_P161_PFC_05_MDAT3 = (0x05U << IOPORT_PFC_OFFSET), ///< P16_1 / DSMIFn / MDAT3 + IOPORT_PIN_P161_PFC_06_ENCIF2 = (0x06U << IOPORT_PFC_OFFSET), ///< P16_1 / ENCIF / ENCIF2 + IOPORT_PIN_P162_PFC_00_NMI = (0x00U << IOPORT_PFC_OFFSET), ///< P16_2 / IRQ / NMI + IOPORT_PIN_P162_PFC_01_XSPI0_RESET1 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_2 / XSPIn / XSPI0_RESET1 + IOPORT_PIN_P162_PFC_02_CTS0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_2 / SCIn / CTS0 + IOPORT_PIN_P162_PFC_03_SPI_RSPCK3 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_2 / SPIn / SPI_RSPCK3 + IOPORT_PIN_P162_PFC_04_USB_EXICEN = (0x04U << IOPORT_PFC_OFFSET), ///< P16_2 / USB_HS / USB_EXICEN + IOPORT_PIN_P162_PFC_05_ENCIF3 = (0x05U << IOPORT_PFC_OFFSET), ///< P16_2 / ENCIF / ENCIF3 + IOPORT_PIN_P163_PFC_00_IRQ7 = (0x00U << IOPORT_PFC_OFFSET), ///< P16_3 / IRQ / IRQ7 + IOPORT_PIN_P163_PFC_01_XSPI0_RSTO0 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_3 / XSPIn / XSPI0_RSTO0 + IOPORT_PIN_P163_PFC_02_ETH1_TXER = (0x02U << IOPORT_PFC_OFFSET), ///< P16_3 / ETHER_ETHn / ETH1_TXER + IOPORT_PIN_P163_PFC_03_GTADSMP1 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_3 / GPT / GTADSMP1 + IOPORT_PIN_P163_PFC_04_SCK0 = (0x04U << IOPORT_PFC_OFFSET), ///< P16_3 / SCIn / SCK0 + IOPORT_PIN_P163_PFC_05_SPI_SSL30 = (0x05U << IOPORT_PFC_OFFSET), ///< P16_3 / SPIn / SPI_SSL30 + IOPORT_PIN_P163_PFC_06_ENCIF4 = (0x06U << IOPORT_PFC_OFFSET), ///< P16_3 / ENCIF / ENCIF4 + IOPORT_PIN_P165_PFC_00_MTIC5U = (0x00U << IOPORT_PFC_OFFSET), ///< P16_5 / MTU3n / MTIC5U + IOPORT_PIN_P165_PFC_01_TXD0_SDA0_MOSI0 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_5 / SCIn / TXD0_SDA0_MOSI0 + IOPORT_PIN_P166_PFC_00_IRQ8 = (0x00U << IOPORT_PFC_OFFSET), ///< P16_6 / IRQ / IRQ8 + IOPORT_PIN_P166_PFC_01_MTIC5V = (0x01U << IOPORT_PFC_OFFSET), ///< P16_6 / MTU3n / MTIC5V + IOPORT_PIN_P166_PFC_02_RXD0_SCL0_MISO0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_6 / SCIn / RXD0_SCL0_MISO0 + IOPORT_PIN_P167_PFC_00_MTIC5W = (0x00U << IOPORT_PFC_OFFSET), ///< P16_7 / MTU3n / MTIC5W + IOPORT_PIN_P167_PFC_01_SCK0 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_7 / SCIn / SCK0 + IOPORT_PIN_P170_PFC_00_ESC_IRQ = (0x00U << IOPORT_PFC_OFFSET), ///< P17_0 / ETHER_ESC / ESC_IRQ + IOPORT_PIN_P170_PFC_01_SS0_CTS0_RTS0 = (0x01U << IOPORT_PFC_OFFSET), ///< P17_0 / SCIn / SS0_CTS0_RTS0 + IOPORT_PIN_P171_PFC_00_DE0 = (0x00U << IOPORT_PFC_OFFSET), ///< P17_1 / SCIn / DE0 + IOPORT_PIN_P172_PFC_00_IRQ9 = (0x00U << IOPORT_PFC_OFFSET), ///< P17_2 / IRQ / IRQ9 + IOPORT_PIN_P172_PFC_01_CMTW1_TIC0 = (0x01U << IOPORT_PFC_OFFSET), ///< P17_2 / CMTWn / CMTW1_TIC0 + IOPORT_PIN_P173_PFC_00_TRACECTL = (0x00U << IOPORT_PFC_OFFSET), ///< P17_3 / TRACE / TRACECTL + IOPORT_PIN_P173_PFC_01_GTETRGA = (0x01U << IOPORT_PFC_OFFSET), ///< P17_3 / GPT_POEG / GTETRGA + IOPORT_PIN_P173_PFC_02_POE0 = (0x02U << IOPORT_PFC_OFFSET), ///< P17_3 / MTU_POE3 / POE0 + IOPORT_PIN_P173_PFC_03_ADTRG1 = (0x03U << IOPORT_PFC_OFFSET), ///< P17_3 / ADCn / ADTRG1 + IOPORT_PIN_P173_PFC_04_SPI_SSL31 = (0x04U << IOPORT_PFC_OFFSET), ///< P17_3 / SPIn / SPI_SSL31 + IOPORT_PIN_P173_PFC_05_DREQ = (0x05U << IOPORT_PFC_OFFSET), ///< P17_3 / DMAC / DREQ + IOPORT_PIN_P173_PFC_06_ENCIF5 = (0x06U << IOPORT_PFC_OFFSET), ///< P17_3 / ENCIF / ENCIF5 + IOPORT_PIN_P174_PFC_00_TRACECLK = (0x00U << IOPORT_PFC_OFFSET), ///< P17_4 / TRACE / TRACECLK + IOPORT_PIN_P174_PFC_01_MTIOC3C = (0x01U << IOPORT_PFC_OFFSET), ///< P17_4 / MTU3n / MTIOC3C + IOPORT_PIN_P174_PFC_02_GTETRGB = (0x02U << IOPORT_PFC_OFFSET), ///< P17_4 / GPT_POEG / GTETRGB + IOPORT_PIN_P174_PFC_03_GTIOC0A = (0x03U << IOPORT_PFC_OFFSET), ///< P17_4 / GPTn / GTIOC0A + IOPORT_PIN_P174_PFC_04_CTS3 = (0x04U << IOPORT_PFC_OFFSET), ///< P17_4 / SCIn / CTS3 + IOPORT_PIN_P174_PFC_05_SPI_SSL32 = (0x05U << IOPORT_PFC_OFFSET), ///< P17_4 / SPIn / SPI_SSL32 + IOPORT_PIN_P174_PFC_06_ENCIF6 = (0x06U << IOPORT_PFC_OFFSET), ///< P17_4 / ENCIF / ENCIF6 + IOPORT_PIN_P175_PFC_01_MTIOC3A = (0x01U << IOPORT_PFC_OFFSET), ///< P17_5 / MTU3n / MTIOC3A + IOPORT_PIN_P175_PFC_02_GTETRGC = (0x02U << IOPORT_PFC_OFFSET), ///< P17_5 / GPT_POEG / GTETRGC + IOPORT_PIN_P175_PFC_03_GTIOC0B = (0x03U << IOPORT_PFC_OFFSET), ///< P17_5 / GPTn / GTIOC0B + IOPORT_PIN_P175_PFC_04_TEND = (0x04U << IOPORT_PFC_OFFSET), ///< P17_5 / DMAC / TEND + IOPORT_PIN_P175_PFC_05_USB_OVRCUR = (0x05U << IOPORT_PFC_OFFSET), ///< P17_5 / USB_HS / USB_OVRCUR + IOPORT_PIN_P175_PFC_06_ENCIF7 = (0x06U << IOPORT_PFC_OFFSET), ///< P17_5 / ENCIF / ENCIF7 + IOPORT_PIN_P176_PFC_00_MTIOC3B = (0x00U << IOPORT_PFC_OFFSET), ///< P17_6 / MTU3n / MTIOC3B + IOPORT_PIN_P176_PFC_01_GTIOC1A = (0x01U << IOPORT_PFC_OFFSET), ///< P17_6 / GPTn / GTIOC1A + IOPORT_PIN_P176_PFC_02_SCK3 = (0x02U << IOPORT_PFC_OFFSET), ///< P17_6 / SCIn / SCK3 + IOPORT_PIN_P176_PFC_03_ENCIF8 = (0x03U << IOPORT_PFC_OFFSET), ///< P17_6 / ENCIF / ENCIF8 + IOPORT_PIN_P177_PFC_00_MTIOC4A = (0x00U << IOPORT_PFC_OFFSET), ///< P17_7 / MTU3n / MTIOC4A + IOPORT_PIN_P177_PFC_01_MTIOC4C = (0x01U << IOPORT_PFC_OFFSET), ///< P17_7 / MTU3n / MTIOC4C + IOPORT_PIN_P177_PFC_02_GTIOC2A = (0x02U << IOPORT_PFC_OFFSET), ///< P17_7 / GPTn / GTIOC2A + IOPORT_PIN_P177_PFC_03_GTIOC3A = (0x03U << IOPORT_PFC_OFFSET), ///< P17_7 / GPTn / GTIOC3A + IOPORT_PIN_P177_PFC_04_RXD3_SCL3_MISO3 = (0x04U << IOPORT_PFC_OFFSET), ///< P17_7 / SCIn / RXD3_SCL3_MISO3 + IOPORT_PIN_P177_PFC_05_DACK = (0x05U << IOPORT_PFC_OFFSET), ///< P17_7 / DMAC / DACK + IOPORT_PIN_P177_PFC_06_ENCIF9 = (0x06U << IOPORT_PFC_OFFSET), ///< P17_7 / ENCIF / ENCIF9 + IOPORT_PIN_P180_PFC_00_MTIOC4C = (0x00U << IOPORT_PFC_OFFSET), ///< P18_0 / MTU3n / MTIOC4C + IOPORT_PIN_P180_PFC_01_MTIOC4A = (0x01U << IOPORT_PFC_OFFSET), ///< P18_0 / MTU3n / MTIOC4A + IOPORT_PIN_P180_PFC_02_GTIOC3A = (0x02U << IOPORT_PFC_OFFSET), ///< P18_0 / GPTn / GTIOC3A + IOPORT_PIN_P180_PFC_03_GTIOC2A = (0x03U << IOPORT_PFC_OFFSET), ///< P18_0 / GPTn / GTIOC2A + IOPORT_PIN_P180_PFC_04_TXD3_SDA3_MOSI3 = (0x04U << IOPORT_PFC_OFFSET), ///< P18_0 / SCIn / TXD3_SDA3_MOSI3 + IOPORT_PIN_P181_PFC_00_IRQ10 = (0x00U << IOPORT_PFC_OFFSET), ///< P18_1 / IRQ / IRQ10 + IOPORT_PIN_P181_PFC_01_MTIOC3D = (0x01U << IOPORT_PFC_OFFSET), ///< P18_1 / MTU3n / MTIOC3D + IOPORT_PIN_P181_PFC_02_GTIOC1B = (0x02U << IOPORT_PFC_OFFSET), ///< P18_1 / GPTn / GTIOC1B + IOPORT_PIN_P181_PFC_03_ADTRG1 = (0x03U << IOPORT_PFC_OFFSET), ///< P18_1 / ADCn / ADTRG1 + IOPORT_PIN_P181_PFC_04_SS3_CTS3_RTS3 = (0x04U << IOPORT_PFC_OFFSET), ///< P18_1 / SCIn / SS3_CTS3_RTS3 + IOPORT_PIN_P181_PFC_05_ENCIF10 = (0x05U << IOPORT_PFC_OFFSET), ///< P18_1 / ENCIF / ENCIF10 + IOPORT_PIN_P182_PFC_00_MTIOC4B = (0x00U << IOPORT_PFC_OFFSET), ///< P18_2 / MTU3n / MTIOC4B + IOPORT_PIN_P182_PFC_01_MTIOC4D = (0x01U << IOPORT_PFC_OFFSET), ///< P18_2 / MTU3n / MTIOC4D + IOPORT_PIN_P182_PFC_02_GTIOC2B = (0x02U << IOPORT_PFC_OFFSET), ///< P18_2 / GPTn / GTIOC2B + IOPORT_PIN_P182_PFC_03_GTIOC3B = (0x03U << IOPORT_PFC_OFFSET), ///< P18_2 / GPTn / GTIOC3B + IOPORT_PIN_P182_PFC_04_ENCIF11 = (0x04U << IOPORT_PFC_OFFSET), ///< P18_2 / ENCIF / ENCIF11 + IOPORT_PIN_P183_PFC_00_IRQ0 = (0x00U << IOPORT_PFC_OFFSET), ///< P18_3 / IRQ / IRQ0 + IOPORT_PIN_P183_PFC_01_MTIOC4D = (0x01U << IOPORT_PFC_OFFSET), ///< P18_3 / MTU3n / MTIOC4D + IOPORT_PIN_P183_PFC_02_MTIOC4B = (0x02U << IOPORT_PFC_OFFSET), ///< P18_3 / MTU3n / MTIOC4B + IOPORT_PIN_P183_PFC_03_GTIOC3B = (0x03U << IOPORT_PFC_OFFSET), ///< P18_3 / GPTn / GTIOC3B + IOPORT_PIN_P183_PFC_04_GTIOC2B = (0x04U << IOPORT_PFC_OFFSET), ///< P18_3 / GPTn / GTIOC2B + IOPORT_PIN_P183_PFC_05_CMTW1_TIC1 = (0x05U << IOPORT_PFC_OFFSET), ///< P18_3 / CMTWn / CMTW1_TIC1 + IOPORT_PIN_P183_PFC_06_CANRXDP1 = (0x06U << IOPORT_PFC_OFFSET), ///< P18_3 / CANFDn / CANRXDP1 + IOPORT_PIN_P183_PFC_07_ENCIF12 = (0x07U << IOPORT_PFC_OFFSET), ///< P18_3 / ENCIF / ENCIF12 + IOPORT_PIN_P184_PFC_00_IRQ1 = (0x00U << IOPORT_PFC_OFFSET), ///< P18_4 / IRQ / IRQ1 + IOPORT_PIN_P184_PFC_01_MTIC5U = (0x01U << IOPORT_PFC_OFFSET), ///< P18_4 / MTU3n / MTIC5U + IOPORT_PIN_P184_PFC_02_TXD4_SDA4_MOSI4 = (0x02U << IOPORT_PFC_OFFSET), ///< P18_4 / SCIn / TXD4_SDA4_MOSI4 + IOPORT_PIN_P184_PFC_03_SPI_RSPCK2 = (0x03U << IOPORT_PFC_OFFSET), ///< P18_4 / SPIn / SPI_RSPCK2 + IOPORT_PIN_P184_PFC_04_ENCIF13 = (0x04U << IOPORT_PFC_OFFSET), ///< P18_4 / ENCIF / ENCIF13 + IOPORT_PIN_P185_PFC_00_TRACECTL = (0x00U << IOPORT_PFC_OFFSET), ///< P18_5 / TRACE / TRACECTL + IOPORT_PIN_P185_PFC_01_MTIC5V = (0x01U << IOPORT_PFC_OFFSET), ///< P18_5 / MTU3n / MTIC5V + IOPORT_PIN_P185_PFC_02_RXD4_SCL4_MISO4 = (0x02U << IOPORT_PFC_OFFSET), ///< P18_5 / SCIn / RXD4_SCL4_MISO4 + IOPORT_PIN_P185_PFC_03_SPI_MOSI2 = (0x03U << IOPORT_PFC_OFFSET), ///< P18_5 / SPIn / SPI_MOSI2 + IOPORT_PIN_P185_PFC_04_ENCIF14 = (0x04U << IOPORT_PFC_OFFSET), ///< P18_5 / ENCIF / ENCIF14 + IOPORT_PIN_P186_PFC_00_IRQ11 = (0x00U << IOPORT_PFC_OFFSET), ///< P18_6 / IRQ / IRQ11 + IOPORT_PIN_P186_PFC_01_TRACECLK = (0x01U << IOPORT_PFC_OFFSET), ///< P18_6 / TRACE / TRACECLK + IOPORT_PIN_P186_PFC_02_MTIC5W = (0x02U << IOPORT_PFC_OFFSET), ///< P18_6 / MTU3n / MTIC5W + IOPORT_PIN_P186_PFC_03_ADTRG0 = (0x03U << IOPORT_PFC_OFFSET), ///< P18_6 / ADCn / ADTRG0 + IOPORT_PIN_P186_PFC_04_SCK4 = (0x04U << IOPORT_PFC_OFFSET), ///< P18_6 / SCIn / SCK4 + IOPORT_PIN_P186_PFC_05_SPI_MISO2 = (0x05U << IOPORT_PFC_OFFSET), ///< P18_6 / SPIn / SPI_MISO2 + IOPORT_PIN_P186_PFC_06_IIC_SCL2 = (0x06U << IOPORT_PFC_OFFSET), ///< P18_6 / IICn / IIC_SCL2 + IOPORT_PIN_P186_PFC_07_ENCIF15 = (0x07U << IOPORT_PFC_OFFSET), ///< P18_6 / ENCIF / ENCIF15 + IOPORT_PIN_P187_PFC_00_IRQ2 = (0x00U << IOPORT_PFC_OFFSET), ///< P18_7 / IRQ / IRQ2 + IOPORT_PIN_P187_PFC_01_GTETRGD = (0x01U << IOPORT_PFC_OFFSET), ///< P18_7 / GPT_POEG / GTETRGD + IOPORT_PIN_P187_PFC_02_POE4 = (0x02U << IOPORT_PFC_OFFSET), ///< P18_7 / MTU_POE3 / POE4 + IOPORT_PIN_P187_PFC_03_SPI_SSL20 = (0x03U << IOPORT_PFC_OFFSET), ///< P18_7 / SPIn / SPI_SSL20 + IOPORT_PIN_P187_PFC_04_IIC_SDA2 = (0x04U << IOPORT_PFC_OFFSET), ///< P18_7 / IICn / IIC_SDA2 + IOPORT_PIN_P187_PFC_05_USB_VBUSEN = (0x05U << IOPORT_PFC_OFFSET), ///< P18_7 / USB_HS / USB_VBUSEN + IOPORT_PIN_P190_PFC_00_USB_VBUSEN = (0x00U << IOPORT_PFC_OFFSET), ///< P19_0 / USB_HS / USB_VBUSEN + IOPORT_PIN_P191_PFC_00_MTIOC6A = (0x00U << IOPORT_PFC_OFFSET), ///< P19_1 / MTU3n / MTIOC6A + IOPORT_PIN_P191_PFC_01_GTIOC4A = (0x01U << IOPORT_PFC_OFFSET), ///< P19_1 / GPTn / GTIOC4A + IOPORT_PIN_P192_PFC_00_IRQ3 = (0x00U << IOPORT_PFC_OFFSET), ///< P19_2 / IRQ / IRQ3 + IOPORT_PIN_P192_PFC_01_MTIOC6C = (0x01U << IOPORT_PFC_OFFSET), ///< P19_2 / MTU3n / MTIOC6C + IOPORT_PIN_P192_PFC_02_GTIOC4B = (0x02U << IOPORT_PFC_OFFSET), ///< P19_2 / GPTn / GTIOC4B + IOPORT_PIN_P193_PFC_00_MTIOC6B = (0x00U << IOPORT_PFC_OFFSET), ///< P19_3 / MTU3n / MTIOC6B + IOPORT_PIN_P193_PFC_01_GTIOC5A = (0x01U << IOPORT_PFC_OFFSET), ///< P19_3 / GPTn / GTIOC5A + IOPORT_PIN_P194_PFC_00_MTIOC7A = (0x00U << IOPORT_PFC_OFFSET), ///< P19_4 / MTU3n / MTIOC7A + IOPORT_PIN_P194_PFC_01_GTIOC6A = (0x01U << IOPORT_PFC_OFFSET), ///< P19_4 / GPTn / GTIOC6A + IOPORT_PIN_P195_PFC_00_MTIOC7C = (0x00U << IOPORT_PFC_OFFSET), ///< P19_5 / MTU3n / MTIOC7C + IOPORT_PIN_P195_PFC_01_GTIOC7A = (0x01U << IOPORT_PFC_OFFSET), ///< P19_5 / GPTn / GTIOC7A + IOPORT_PIN_P196_PFC_00_MTIOC6D = (0x00U << IOPORT_PFC_OFFSET), ///< P19_6 / MTU3n / MTIOC6D + IOPORT_PIN_P196_PFC_01_GTIOC5B = (0x01U << IOPORT_PFC_OFFSET), ///< P19_6 / GPTn / GTIOC5B + IOPORT_PIN_P197_PFC_00_MTIOC7B = (0x00U << IOPORT_PFC_OFFSET), ///< P19_7 / MTU3n / MTIOC7B + IOPORT_PIN_P197_PFC_01_GTIOC6B = (0x01U << IOPORT_PFC_OFFSET), ///< P19_7 / GPTn / GTIOC6B + IOPORT_PIN_P200_PFC_00_MTIOC7D = (0x00U << IOPORT_PFC_OFFSET), ///< P20_0 / MTU3n / MTIOC7D + IOPORT_PIN_P200_PFC_01_GTIOC7B = (0x01U << IOPORT_PFC_OFFSET), ///< P20_0 / GPTn / GTIOC7B + IOPORT_PIN_P201_PFC_00_ETHSW_TDMAOUT0 = (0x00U << IOPORT_PFC_OFFSET), ///< P20_1 / ETHER_ETHSW / ETHSW_TDMAOUT0 + IOPORT_PIN_P201_PFC_01_ESC_LINKACT0 = (0x01U << IOPORT_PFC_OFFSET), ///< P20_1 / ETHER_ESC / ESC_LINKACT0 + IOPORT_PIN_P202_PFC_00_ETHSW_TDMAOUT1 = (0x00U << IOPORT_PFC_OFFSET), ///< P20_2 / ETHER_ETHSW / ETHSW_TDMAOUT1 + IOPORT_PIN_P202_PFC_01_ESC_LEDRUN = (0x01U << IOPORT_PFC_OFFSET), ///< P20_2 / ETHER_ESC / ESC_LEDRUN + IOPORT_PIN_P202_PFC_02_ESC_LEDSTER = (0x02U << IOPORT_PFC_OFFSET), ///< P20_2 / ETHER_ESC / ESC_LEDSTER + IOPORT_PIN_P202_PFC_03_DE3 = (0x03U << IOPORT_PFC_OFFSET), ///< P20_2 / SCIn / DE3 + IOPORT_PIN_P203_PFC_00_ETHSW_TDMAOUT2 = (0x00U << IOPORT_PFC_OFFSET), ///< P20_3 / ETHER_ETHSW / ETHSW_TDMAOUT2 + IOPORT_PIN_P203_PFC_01_ESC_LEDERR = (0x01U << IOPORT_PFC_OFFSET), ///< P20_3 / ETHER_ESC / ESC_LEDERR + IOPORT_PIN_P204_PFC_00_ETHSW_TDMAOUT3 = (0x00U << IOPORT_PFC_OFFSET), ///< P20_4 / ETHER_ETHSW / ETHSW_TDMAOUT3 + IOPORT_PIN_P204_PFC_01_ESC_LINKACT1 = (0x01U << IOPORT_PFC_OFFSET), ///< P20_4 / ETHER_ESC / ESC_LINKACT1 + IOPORT_PIN_P205_PFC_00_ESC_I2CCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P20_5 / ETHER_ESC / ESC_I2CCLK + IOPORT_PIN_P205_PFC_01_MTIOC1A = (0x01U << IOPORT_PFC_OFFSET), ///< P20_5 / MTU3n / MTIOC1A + IOPORT_PIN_P205_PFC_02_IIC_SCL0 = (0x02U << IOPORT_PFC_OFFSET), ///< P20_5 / IICn / IIC_SCL0 + IOPORT_PIN_P205_PFC_03_MCLK4 = (0x03U << IOPORT_PFC_OFFSET), ///< P20_5 / DSMIFn / MCLK4 + IOPORT_PIN_P206_PFC_00_ESC_I2CDATA = (0x00U << IOPORT_PFC_OFFSET), ///< P20_6 / ETHER_ESC / ESC_I2CDATA + IOPORT_PIN_P206_PFC_01_MTIOC1B = (0x01U << IOPORT_PFC_OFFSET), ///< P20_6 / MTU3n / MTIOC1B + IOPORT_PIN_P206_PFC_02_IIC_SDA0 = (0x02U << IOPORT_PFC_OFFSET), ///< P20_6 / IICn / IIC_SDA0 + IOPORT_PIN_P206_PFC_03_MDAT4 = (0x03U << IOPORT_PFC_OFFSET), ///< P20_6 / DSMIFn / MDAT4 + IOPORT_PIN_P207_PFC_00_ETHSW_PTPOUT2 = (0x00U << IOPORT_PFC_OFFSET), ///< P20_7 / ETHER_ETHSW / ETHSW_PTPOUT2 + IOPORT_PIN_P207_PFC_01_ESC_RESETOUT = (0x01U << IOPORT_PFC_OFFSET), ///< P20_7 / ETHER_ESC / ESC_RESETOUT + IOPORT_PIN_P207_PFC_02_MTIOC2A = (0x02U << IOPORT_PFC_OFFSET), ///< P20_7 / MTU3n / MTIOC2A + IOPORT_PIN_P207_PFC_03_GTIOC13A = (0x03U << IOPORT_PFC_OFFSET), ///< P20_7 / GPTn / GTIOC13A + IOPORT_PIN_P207_PFC_04_MCLK5 = (0x04U << IOPORT_PFC_OFFSET), ///< P20_7 / DSMIFn / MCLK5 + IOPORT_PIN_P210_PFC_00_ETHSW_PTPOUT3 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_0 / ETHER_ETHSW / ETHSW_PTPOUT3 + IOPORT_PIN_P210_PFC_01_WE2_DQMUL = (0x01U << IOPORT_PFC_OFFSET), ///< P21_0 / BSC / WE2_DQMUL + IOPORT_PIN_P210_PFC_02_ESC_LINKACT2 = (0x02U << IOPORT_PFC_OFFSET), ///< P21_0 / ETHER_ESC / ESC_LINKACT2 + IOPORT_PIN_P210_PFC_03_MTIOC2B = (0x03U << IOPORT_PFC_OFFSET), ///< P21_0 / MTU3n / MTIOC2B + IOPORT_PIN_P210_PFC_04_GTIOC13B = (0x04U << IOPORT_PFC_OFFSET), ///< P21_0 / GPTn / GTIOC13B + IOPORT_PIN_P210_PFC_05_MDAT5 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_0 / DSMIFn / MDAT5 + IOPORT_PIN_P211_PFC_00_TRACEDATA0 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_1 / TRACE / TRACEDATA0 + IOPORT_PIN_P211_PFC_01_D0 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_1 / BSC / D0 + IOPORT_PIN_P211_PFC_02_MTIOC6A = (0x02U << IOPORT_PFC_OFFSET), ///< P21_1 / MTU3n / MTIOC6A + IOPORT_PIN_P211_PFC_03_GTIOC14A = (0x03U << IOPORT_PFC_OFFSET), ///< P21_1 / GPTn / GTIOC14A + IOPORT_PIN_P211_PFC_04_CMTW0_TIC0 = (0x04U << IOPORT_PFC_OFFSET), ///< P21_1 / CMTWn / CMTW0_TIC0 + IOPORT_PIN_P211_PFC_05_SCK5 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_1 / SCIn / SCK5 + IOPORT_PIN_P211_PFC_06_SPI_SSL20 = (0x06U << IOPORT_PFC_OFFSET), ///< P21_1 / SPIn / SPI_SSL20 + IOPORT_PIN_P211_PFC_07_IIC_SCL1 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_1 / IICn / IIC_SCL1 + IOPORT_PIN_P211_PFC_08_MCLK0 = (0x08U << IOPORT_PFC_OFFSET), ///< P21_1 / DSMIFn / MCLK0 + IOPORT_PIN_P211_PFC_09_ENCIF5 = (0x09U << IOPORT_PFC_OFFSET), ///< P21_1 / ENCIF / ENCIF5 + IOPORT_PIN_P212_PFC_00_TRACEDATA1 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_2 / TRACE / TRACEDATA1 + IOPORT_PIN_P212_PFC_01_D1 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_2 / BSC / D1 + IOPORT_PIN_P212_PFC_02_MTIOC6B = (0x02U << IOPORT_PFC_OFFSET), ///< P21_2 / MTU3n / MTIOC6B + IOPORT_PIN_P212_PFC_03_GTIOC14B = (0x03U << IOPORT_PFC_OFFSET), ///< P21_2 / GPTn / GTIOC14B + IOPORT_PIN_P212_PFC_04_CMTW0_TIC1 = (0x04U << IOPORT_PFC_OFFSET), ///< P21_2 / CMTWn / CMTW0_TIC1 + IOPORT_PIN_P212_PFC_05_RXD5_SCL5_MISO5 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_2 / SCIn / RXD5_SCL5_MISO5 + IOPORT_PIN_P212_PFC_06_SPI_MISO2 = (0x06U << IOPORT_PFC_OFFSET), ///< P21_2 / SPIn / SPI_MISO2 + IOPORT_PIN_P212_PFC_07_IIC_SDA1 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_2 / IICn / IIC_SDA1 + IOPORT_PIN_P212_PFC_08_MDAT0 = (0x08U << IOPORT_PFC_OFFSET), ///< P21_2 / DSMIFn / MDAT0 + IOPORT_PIN_P212_PFC_09_ENCIF6 = (0x09U << IOPORT_PFC_OFFSET), ///< P21_2 / ENCIF / ENCIF6 + IOPORT_PIN_P213_PFC_00_TRACEDATA2 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_3 / TRACE / TRACEDATA2 + IOPORT_PIN_P213_PFC_01_D2 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_3 / BSC / D2 + IOPORT_PIN_P213_PFC_02_MTIOC6C = (0x02U << IOPORT_PFC_OFFSET), ///< P21_3 / MTU3n / MTIOC6C + IOPORT_PIN_P213_PFC_03_GTIOC15A = (0x03U << IOPORT_PFC_OFFSET), ///< P21_3 / GPTn / GTIOC15A + IOPORT_PIN_P213_PFC_04_TXD5_SDA5_MOSI5 = (0x04U << IOPORT_PFC_OFFSET), ///< P21_3 / SCIn / TXD5_SDA5_MOSI5 + IOPORT_PIN_P213_PFC_05_SPI_SSL33 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_3 / SPIn / SPI_SSL33 + IOPORT_PIN_P213_PFC_06_MCLK1 = (0x06U << IOPORT_PFC_OFFSET), ///< P21_3 / DSMIFn / MCLK1 + IOPORT_PIN_P213_PFC_07_ENCIF7 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_3 / ENCIF / ENCIF7 + IOPORT_PIN_P214_PFC_00_TRACEDATA3 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_4 / TRACE / TRACEDATA3 + IOPORT_PIN_P214_PFC_01_D3 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_4 / BSC / D3 + IOPORT_PIN_P214_PFC_02_MTIOC6D = (0x02U << IOPORT_PFC_OFFSET), ///< P21_4 / MTU3n / MTIOC6D + IOPORT_PIN_P214_PFC_03_GTIOC15B = (0x03U << IOPORT_PFC_OFFSET), ///< P21_4 / GPTn / GTIOC15B + IOPORT_PIN_P214_PFC_04_SS5_CTS5_RTS5 = (0x04U << IOPORT_PFC_OFFSET), ///< P21_4 / SCIn / SS5_CTS5_RTS5 + IOPORT_PIN_P214_PFC_05_SPI_SSL02 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_4 / SPIn / SPI_SSL02 + IOPORT_PIN_P214_PFC_06_MDAT1 = (0x06U << IOPORT_PFC_OFFSET), ///< P21_4 / DSMIFn / MDAT1 + IOPORT_PIN_P214_PFC_07_ENCIF8 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_4 / ENCIF / ENCIF8 + IOPORT_PIN_P215_PFC_00_IRQ6 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_5 / IRQ / IRQ6 + IOPORT_PIN_P215_PFC_01_TRACEDATA4 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_5 / TRACE / TRACEDATA4 + IOPORT_PIN_P215_PFC_02_D4 = (0x02U << IOPORT_PFC_OFFSET), ///< P21_5 / BSC / D4 + IOPORT_PIN_P215_PFC_03_MTIOC7A = (0x03U << IOPORT_PFC_OFFSET), ///< P21_5 / MTU3n / MTIOC7A + IOPORT_PIN_P215_PFC_04_GTIOC16A = (0x04U << IOPORT_PFC_OFFSET), ///< P21_5 / GPTn / GTIOC16A + IOPORT_PIN_P215_PFC_05_CMTW1_TOC1 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_5 / CMTWn / CMTW1_TOC1 + IOPORT_PIN_P215_PFC_06_ADTRG1 = (0x06U << IOPORT_PFC_OFFSET), ///< P21_5 / ADCn / ADTRG1 + IOPORT_PIN_P215_PFC_07_CTS5 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_5 / SCIn / CTS5 + IOPORT_PIN_P215_PFC_08_SPI_MISO0 = (0x08U << IOPORT_PFC_OFFSET), ///< P21_5 / SPIn / SPI_MISO0 + IOPORT_PIN_P215_PFC_09_MCLK2 = (0x09U << IOPORT_PFC_OFFSET), ///< P21_5 / DSMIFn / MCLK2 + IOPORT_PIN_P215_PFC_0A_ENCIF9 = (0x0AU << IOPORT_PFC_OFFSET), ///< P21_5 / ENCIF / ENCIF9 + IOPORT_PIN_P216_PFC_00_IRQ9 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_6 / IRQ / IRQ9 + IOPORT_PIN_P216_PFC_01_TRACEDATA5 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_6 / TRACE / TRACEDATA5 + IOPORT_PIN_P216_PFC_02_D5 = (0x02U << IOPORT_PFC_OFFSET), ///< P21_6 / BSC / D5 + IOPORT_PIN_P216_PFC_03_MTIOC7B = (0x03U << IOPORT_PFC_OFFSET), ///< P21_6 / MTU3n / MTIOC7B + IOPORT_PIN_P216_PFC_04_GTIOC16B = (0x04U << IOPORT_PFC_OFFSET), ///< P21_6 / GPTn / GTIOC16B + IOPORT_PIN_P216_PFC_05_CTS0 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_6 / SCIn / CTS0 + IOPORT_PIN_P216_PFC_06_TEND = (0x06U << IOPORT_PFC_OFFSET), ///< P21_6 / DMAC / TEND + IOPORT_PIN_P216_PFC_07_MDAT2 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_6 / DSMIFn / MDAT2 + IOPORT_PIN_P217_PFC_00_IRQ10 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_7 / IRQ / IRQ10 + IOPORT_PIN_P217_PFC_01_TRACEDATA6 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_7 / TRACE / TRACEDATA6 + IOPORT_PIN_P217_PFC_02_D6 = (0x02U << IOPORT_PFC_OFFSET), ///< P21_7 / BSC / D6 + IOPORT_PIN_P217_PFC_03_MTIOC7C = (0x03U << IOPORT_PFC_OFFSET), ///< P21_7 / MTU3n / MTIOC7C + IOPORT_PIN_P217_PFC_04_GTIOC17A = (0x04U << IOPORT_PFC_OFFSET), ///< P21_7 / GPTn / GTIOC17A + IOPORT_PIN_P217_PFC_05_DE0 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_7 / SCIn / DE0 + IOPORT_PIN_P217_PFC_06_DREQ = (0x06U << IOPORT_PFC_OFFSET), ///< P21_7 / DMAC / DREQ + IOPORT_PIN_P217_PFC_07_MCLK3 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_7 / DSMIFn / MCLK3 + IOPORT_PIN_P220_PFC_00_IRQ15 = (0x00U << IOPORT_PFC_OFFSET), ///< P22_0 / IRQ / IRQ15 + IOPORT_PIN_P220_PFC_01_TRACEDATA7 = (0x01U << IOPORT_PFC_OFFSET), ///< P22_0 / TRACE / TRACEDATA7 + IOPORT_PIN_P220_PFC_02_D7 = (0x02U << IOPORT_PFC_OFFSET), ///< P22_0 / BSC / D7 + IOPORT_PIN_P220_PFC_03_MTIOC7D = (0x03U << IOPORT_PFC_OFFSET), ///< P22_0 / MTU3n / MTIOC7D + IOPORT_PIN_P220_PFC_04_GTIOC17B = (0x04U << IOPORT_PFC_OFFSET), ///< P22_0 / GPTn / GTIOC17B + IOPORT_PIN_P220_PFC_05_DE5 = (0x05U << IOPORT_PFC_OFFSET), ///< P22_0 / SCIn / DE5 + IOPORT_PIN_P220_PFC_06_MDAT3 = (0x06U << IOPORT_PFC_OFFSET), ///< P22_0 / DSMIFn / MDAT3 + IOPORT_PIN_P221_PFC_00_TRACECTL = (0x00U << IOPORT_PFC_OFFSET), ///< P22_1 / TRACE / TRACECTL + IOPORT_PIN_P221_PFC_01_D8 = (0x01U << IOPORT_PFC_OFFSET), ///< P22_1 / BSC / D8 + IOPORT_PIN_P221_PFC_02_ESC_LINKACT2 = (0x02U << IOPORT_PFC_OFFSET), ///< P22_1 / ETHER_ESC / ESC_LINKACT2 + IOPORT_PIN_P221_PFC_03_POE4 = (0x03U << IOPORT_PFC_OFFSET), ///< P22_1 / MTU_POE3 / POE4 + IOPORT_PIN_P221_PFC_04_SS4_CTS4_RTS4 = (0x04U << IOPORT_PFC_OFFSET), ///< P22_1 / SCIn / SS4_CTS4_RTS4 + IOPORT_PIN_P222_PFC_00_IRQ4 = (0x00U << IOPORT_PFC_OFFSET), ///< P22_2 / IRQ / IRQ4 + IOPORT_PIN_P222_PFC_01_TRACECLK = (0x01U << IOPORT_PFC_OFFSET), ///< P22_2 / TRACE / TRACECLK + IOPORT_PIN_P222_PFC_02_D9 = (0x02U << IOPORT_PFC_OFFSET), ///< P22_2 / BSC / D9 + IOPORT_PIN_P222_PFC_03_MTIOC8C = (0x03U << IOPORT_PFC_OFFSET), ///< P22_2 / MTU3n / MTIOC8C + IOPORT_PIN_P222_PFC_04_GTETRGSA = (0x04U << IOPORT_PFC_OFFSET), ///< P22_2 / GPT_POEG / GTETRGSA + IOPORT_PIN_P222_PFC_05_SPI_SSL12 = (0x05U << IOPORT_PFC_OFFSET), ///< P22_2 / SPIn / SPI_SSL12 + IOPORT_PIN_P222_PFC_06_ENCIF10 = (0x06U << IOPORT_PFC_OFFSET), ///< P22_2 / ENCIF / ENCIF10 + IOPORT_PIN_P223_PFC_00_D10 = (0x00U << IOPORT_PFC_OFFSET), ///< P22_3 / BSC / D10 + IOPORT_PIN_P223_PFC_01_MTIOC8D = (0x01U << IOPORT_PFC_OFFSET), ///< P22_3 / MTU3n / MTIOC8D + IOPORT_PIN_P223_PFC_02_GTETRGSB = (0x02U << IOPORT_PFC_OFFSET), ///< P22_3 / GPT_POEG / GTETRGSB + IOPORT_PIN_P223_PFC_03_ENCIF11 = (0x03U << IOPORT_PFC_OFFSET), ///< P22_3 / ENCIF / ENCIF11 + IOPORT_PIN_P224_PFC_00_D11 = (0x00U << IOPORT_PFC_OFFSET), ///< P22_4 / BSC / D11 + IOPORT_PIN_P225_PFC_00_D12 = (0x00U << IOPORT_PFC_OFFSET), ///< P22_5 / BSC / D12 + IOPORT_PIN_P225_PFC_01_CTS4 = (0x01U << IOPORT_PFC_OFFSET), ///< P22_5 / SCIn / CTS4 + IOPORT_PIN_P226_PFC_00_D13 = (0x00U << IOPORT_PFC_OFFSET), ///< P22_6 / BSC / D13 + IOPORT_PIN_P226_PFC_01_DE4 = (0x01U << IOPORT_PFC_OFFSET), ///< P22_6 / SCIn / DE4 + IOPORT_PIN_P226_PFC_02_IIC_SCL1 = (0x02U << IOPORT_PFC_OFFSET), ///< P22_6 / IICn / IIC_SCL1 + IOPORT_PIN_P227_PFC_00_D14 = (0x00U << IOPORT_PFC_OFFSET), ///< P22_7 / BSC / D14 + IOPORT_PIN_P227_PFC_01_SCK0 = (0x01U << IOPORT_PFC_OFFSET), ///< P22_7 / SCIn / SCK0 + IOPORT_PIN_P227_PFC_02_IIC_SDA1 = (0x02U << IOPORT_PFC_OFFSET), ///< P22_7 / IICn / IIC_SDA1 + IOPORT_PIN_P230_PFC_00_IRQ5 = (0x00U << IOPORT_PFC_OFFSET), ///< P23_0 / IRQ / IRQ5 + IOPORT_PIN_P230_PFC_01_D15 = (0x01U << IOPORT_PFC_OFFSET), ///< P23_0 / BSC / D15 + IOPORT_PIN_P230_PFC_02_SPI_MOSI2 = (0x02U << IOPORT_PFC_OFFSET), ///< P23_0 / SPIn / SPI_MOSI2 + IOPORT_PIN_P231_PFC_00_NMI = (0x00U << IOPORT_PFC_OFFSET), ///< P23_1 / IRQ / NMI + IOPORT_PIN_P231_PFC_01_D16 = (0x01U << IOPORT_PFC_OFFSET), ///< P23_1 / BSC / D16 + IOPORT_PIN_P231_PFC_02_WE0_DQMLL = (0x02U << IOPORT_PFC_OFFSET), ///< P23_1 / BSC / WE0_DQMLL + IOPORT_PIN_P231_PFC_03_MTCLKA = (0x03U << IOPORT_PFC_OFFSET), ///< P23_1 / MTU3 / MTCLKA + IOPORT_PIN_P232_PFC_00_IRQ8 = (0x00U << IOPORT_PFC_OFFSET), ///< P23_2 / IRQ / IRQ8 + IOPORT_PIN_P232_PFC_01_D17 = (0x01U << IOPORT_PFC_OFFSET), ///< P23_2 / BSC / D17 + IOPORT_PIN_P232_PFC_02_WE1_DQMLU = (0x02U << IOPORT_PFC_OFFSET), ///< P23_2 / BSC / WE1_DQMLU + IOPORT_PIN_P232_PFC_03_MTCLKB = (0x03U << IOPORT_PFC_OFFSET), ///< P23_2 / MTU3 / MTCLKB + IOPORT_PIN_P233_PFC_00_D18 = (0x00U << IOPORT_PFC_OFFSET), ///< P23_3 / BSC / D18 + IOPORT_PIN_P233_PFC_01_WE3_DQMUU_AH = (0x01U << IOPORT_PFC_OFFSET), ///< P23_3 / BSC / WE3_DQMUU_AH + IOPORT_PIN_P233_PFC_02_MTCLKC = (0x02U << IOPORT_PFC_OFFSET), ///< P23_3 / MTU3 / MTCLKC + IOPORT_PIN_P233_PFC_03_RXD0_SCL0_MISO0 = (0x03U << IOPORT_PFC_OFFSET), ///< P23_3 / SCIn / RXD0_SCL0_MISO0 + IOPORT_PIN_P234_PFC_00_D19 = (0x00U << IOPORT_PFC_OFFSET), ///< P23_4 / BSC / D19 + IOPORT_PIN_P234_PFC_01_CS5 = (0x01U << IOPORT_PFC_OFFSET), ///< P23_4 / BSC / CS5 + IOPORT_PIN_P234_PFC_02_MTCLKD = (0x02U << IOPORT_PFC_OFFSET), ///< P23_4 / MTU3 / MTCLKD + IOPORT_PIN_P235_PFC_00_D20 = (0x00U << IOPORT_PFC_OFFSET), ///< P23_5 / BSC / D20 + IOPORT_PIN_P235_PFC_01_CS2 = (0x01U << IOPORT_PFC_OFFSET), ///< P23_5 / BSC / CS2 + IOPORT_PIN_P235_PFC_02_MTIOC8A = (0x02U << IOPORT_PFC_OFFSET), ///< P23_5 / MTU3n / MTIOC8A + IOPORT_PIN_P235_PFC_03_TXD0_SDA0_MOSI0 = (0x03U << IOPORT_PFC_OFFSET), ///< P23_5 / SCIn / TXD0_SDA0_MOSI0 + IOPORT_PIN_P236_PFC_00_D21 = (0x00U << IOPORT_PFC_OFFSET), ///< P23_6 / BSC / D21 + IOPORT_PIN_P236_PFC_01_MTIOC8B = (0x01U << IOPORT_PFC_OFFSET), ///< P23_6 / MTU3n / MTIOC8B + IOPORT_PIN_P236_PFC_02_SS0_CTS0_RTS0 = (0x02U << IOPORT_PFC_OFFSET), ///< P23_6 / SCIn / SS0_CTS0_RTS0 + IOPORT_PIN_P237_PFC_00_ETH2_RXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P23_7 / ETHER_ETHn / ETH2_RXD0 + IOPORT_PIN_P237_PFC_01_D22 = (0x01U << IOPORT_PFC_OFFSET), ///< P23_7 / BSC / D22 + IOPORT_PIN_P237_PFC_02_D11 = (0x02U << IOPORT_PFC_OFFSET), ///< P23_7 / BSC / D11 + IOPORT_PIN_P237_PFC_03_BS = (0x03U << IOPORT_PFC_OFFSET), ///< P23_7 / BSC / BS + IOPORT_PIN_P237_PFC_04_MTIOC0A = (0x04U << IOPORT_PFC_OFFSET), ///< P23_7 / MTU3n / MTIOC0A + IOPORT_PIN_P237_PFC_05_GTETRGA = (0x05U << IOPORT_PFC_OFFSET), ///< P23_7 / GPT_POEG / GTETRGA + IOPORT_PIN_P237_PFC_06_SCK1 = (0x06U << IOPORT_PFC_OFFSET), ///< P23_7 / SCIn / SCK1 + IOPORT_PIN_P237_PFC_07_MCLK4 = (0x07U << IOPORT_PFC_OFFSET), ///< P23_7 / DSMIFn / MCLK4 + IOPORT_PIN_P237_PFC_08_ENCIF12 = (0x08U << IOPORT_PFC_OFFSET), ///< P23_7 / ENCIF / ENCIF12 + IOPORT_PIN_P240_PFC_00_ETH2_RXD1 = (0x00U << IOPORT_PFC_OFFSET), ///< P24_0 / ETHER_ETHn / ETH2_RXD1 + IOPORT_PIN_P240_PFC_01_D23 = (0x01U << IOPORT_PFC_OFFSET), ///< P24_0 / BSC / D23 + IOPORT_PIN_P240_PFC_02_D12 = (0x02U << IOPORT_PFC_OFFSET), ///< P24_0 / BSC / D12 + IOPORT_PIN_P240_PFC_03_CKE = (0x03U << IOPORT_PFC_OFFSET), ///< P24_0 / BSC / CKE + IOPORT_PIN_P240_PFC_04_MTIOC0B = (0x04U << IOPORT_PFC_OFFSET), ///< P24_0 / MTU3n / MTIOC0B + IOPORT_PIN_P240_PFC_05_GTETRGB = (0x05U << IOPORT_PFC_OFFSET), ///< P24_0 / GPT_POEG / GTETRGB + IOPORT_PIN_P240_PFC_06_RXD1_SCL1_MISO1 = (0x06U << IOPORT_PFC_OFFSET), ///< P24_0 / SCIn / RXD1_SCL1_MISO1 + IOPORT_PIN_P240_PFC_07_DREQ = (0x07U << IOPORT_PFC_OFFSET), ///< P24_0 / DMAC / DREQ + IOPORT_PIN_P240_PFC_08_MDAT4 = (0x08U << IOPORT_PFC_OFFSET), ///< P24_0 / DSMIFn / MDAT4 + IOPORT_PIN_P240_PFC_09_ENCIF13 = (0x09U << IOPORT_PFC_OFFSET), ///< P24_0 / ENCIF / ENCIF13 + IOPORT_PIN_P241_PFC_00_ETH2_RXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P24_1 / ETHER_ETHn / ETH2_RXCLK + IOPORT_PIN_P241_PFC_01_D24 = (0x01U << IOPORT_PFC_OFFSET), ///< P24_1 / BSC / D24 + IOPORT_PIN_P241_PFC_02_D13 = (0x02U << IOPORT_PFC_OFFSET), ///< P24_1 / BSC / D13 + IOPORT_PIN_P241_PFC_03_CAS = (0x03U << IOPORT_PFC_OFFSET), ///< P24_1 / BSC / CAS + IOPORT_PIN_P241_PFC_04_MTIOC0C = (0x04U << IOPORT_PFC_OFFSET), ///< P24_1 / MTU3n / MTIOC0C + IOPORT_PIN_P241_PFC_05_GTETRGC = (0x05U << IOPORT_PFC_OFFSET), ///< P24_1 / GPT_POEG / GTETRGC + IOPORT_PIN_P241_PFC_06_POE8 = (0x06U << IOPORT_PFC_OFFSET), ///< P24_1 / MTU_POE3 / POE8 + IOPORT_PIN_P241_PFC_07_MCLK5 = (0x07U << IOPORT_PFC_OFFSET), ///< P24_1 / DSMIFn / MCLK5 + IOPORT_PIN_P241_PFC_08_ENCIF14 = (0x08U << IOPORT_PFC_OFFSET), ///< P24_1 / ENCIF / ENCIF14 + IOPORT_PIN_P242_PFC_00_ETH2_RXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P24_2 / ETHER_ETHn / ETH2_RXD2 + IOPORT_PIN_P242_PFC_01_D25 = (0x01U << IOPORT_PFC_OFFSET), ///< P24_2 / BSC / D25 + IOPORT_PIN_P242_PFC_02_D14 = (0x02U << IOPORT_PFC_OFFSET), ///< P24_2 / BSC / D14 + IOPORT_PIN_P242_PFC_03_RAS = (0x03U << IOPORT_PFC_OFFSET), ///< P24_2 / BSC / RAS + IOPORT_PIN_P242_PFC_04_MTIOC0D = (0x04U << IOPORT_PFC_OFFSET), ///< P24_2 / MTU3n / MTIOC0D + IOPORT_PIN_P242_PFC_05_GTETRGD = (0x05U << IOPORT_PFC_OFFSET), ///< P24_2 / GPT_POEG / GTETRGD + IOPORT_PIN_P242_PFC_06_TXD1_SDA1_MOSI1 = (0x06U << IOPORT_PFC_OFFSET), ///< P24_2 / SCIn / TXD1_SDA1_MOSI1 + IOPORT_PIN_P242_PFC_07_MDAT5 = (0x07U << IOPORT_PFC_OFFSET), ///< P24_2 / DSMIFn / MDAT5 + IOPORT_PIN_P242_PFC_08_ENCIF15 = (0x08U << IOPORT_PFC_OFFSET), ///< P24_2 / ENCIF / ENCIF15 + + /** Marks end of enum - used by parameter checking */ + IOPORT_PERIPHERAL_END +} ioport_pin_pfc_t; + +/** Options to configure pin functions */ +typedef enum e_ioport_cfg_options +{ + IOPORT_CFG_PORT_DIRECTION_HIZ = 0x00000000 << IOPORT_PM_OFFSET, ///< Sets the pin direction to Hi-Z + IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000001 << IOPORT_PM_OFFSET, ///< Sets the pin direction to input (default) + IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000002 << IOPORT_PM_OFFSET, ///< Sets the pin direction to output + IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT = 0x00000003 << IOPORT_PM_OFFSET, ///< Sets the pin direction to output (data is input to input buffer) + IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000 << IOPORT_P_OFFSET, ///< Sets the pin level to low + IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001 << IOPORT_P_OFFSET, ///< Sets the pin level to high + IOPORT_CFG_PORT_GPIO = 0x00000000 << IOPORT_PMC_OFFSET, ///< Enables pin to operate as an GPIO pin + IOPORT_CFG_PORT_PERI = 0x00000001 << IOPORT_PMC_OFFSET, ///< Enables pin to operate as a peripheral pin + IOPORT_CFG_DRIVE_LOW = 0x00000000 << IOPORT_DRCTL_OFFSET, ///< Sets pin drive output to low + IOPORT_CFG_DRIVE_MID = 0x00000001 << IOPORT_DRCTL_OFFSET, ///< Sets pin drive output to medium + IOPORT_CFG_DRIVE_HIGH = 0x00000002 << IOPORT_DRCTL_OFFSET, ///< Sets pin drive output to high + IOPORT_CFG_DRIVE_UHIGH = 0x00000003 << IOPORT_DRCTL_OFFSET, ///< Sets pin drive output to ultra high + IOPORT_CFG_PULLUP_DOWN_DISABLE = 0x00000000 << IOPORT_DRCTL_OFFSET, ///< Disables the pin's pull-up / pull-down + IOPORT_CFG_PULLUP_ENABLE = 0x00000004 << IOPORT_DRCTL_OFFSET, ///< Enables the pin's internal pull-up + IOPORT_CFG_PULLDOWN_ENABLE = 0x00000008 << IOPORT_DRCTL_OFFSET, ///< Enables the pin's pull-down + IOPORT_CFG_SCHMITT_TRIGGER_DISABLE = 0x00000000 << IOPORT_DRCTL_OFFSET, ///< Disables schmitt trigger input + IOPORT_CFG_SCHMITT_TRIGGER_ENABLE = 0x00000010 << IOPORT_DRCTL_OFFSET, ///< Enables schmitt trigger input + IOPORT_CFG_SLEW_RATE_SLOW = 0x00000000 << IOPORT_DRCTL_OFFSET, ///< Sets the slew rate to slow + IOPORT_CFG_SLEW_RATE_FAST = 0x00000020 << IOPORT_DRCTL_OFFSET, ///< Sets the slew rate to fast + IOPORT_CFG_REGION_SAFETY = 0x00000000 << IOPORT_RSELP_OFFSET, ///< Selects safety region + IOPORT_CFG_REGION_NSAFETY = 0x00000001 << IOPORT_RSELP_OFFSET, ///< Selects non safety region + IOPORT_CFG_PIM_TTL = 0x00000020, ///< This macro has been unsupported + IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< This macro has been unsupported + IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< This macro has been unsupported + IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< This macro has been unsupported + IOPORT_CFG_DRIVE_MID_IIC = 0x00000C00, ///< This macro has been unsupported + IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< This macro has been unsupported + IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< This macro has been unsupported + IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< This macro has been unsupported + IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< This macro has been unsupported + IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< This macro has been unsupported + IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< This macro has been unsupported +} ioport_cfg_options_t; + +/*============================================== + * POE3 API Overrides + *==============================================*/ + +/** POE3 states. */ +typedef enum e_poe3_state +{ + POE3_STATE_NO_DISABLE_REQUEST = 0, ///< Timer output is not disabled by POE3 + POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST = 1U, ///< Timer output disabled due to POE0# pin + POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST = 1U << 1, ///< Timer output disabled due to POE4# pin + POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST = 1U << 2, ///< Timer output disabled due to POE8# pin + POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST = 1U << 3, ///< Timer output disabled due to POE10# pin + POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST = 1U << 4, ///< Timer output disabled due to POE11# pin + + POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST = 1U << 5, ///< Timer output disabled due to poe3_api_t::outputDisable() + POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST = 1U << 6, ///< Timer output disabled due to main oscillator stop + + POE3_STATE_DSMIF0_ERROR_REQUEST = 1U << 7, ///< Timer output disabled due to DSMIF0 error + POE3_STATE_DSMIF1_ERROR_REQUEST = 1U << 8, ///< Timer output disabled due to DSMIF1 error + + POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST = 1U << 9, ///< Timer output disabled due to output short circuit 1 + POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST = 1U << 10, ///< Timer output disabled due to output short circuit 2 +} poe3_state_t; + +/*============================================== + * POEG API Overrides + *==============================================*/ + +/** POEG states. */ +typedef enum e_poeg_state +{ + POEG_STATE_NO_DISABLE_REQUEST = 0, ///< GPT output is not disabled by POEG + POEG_STATE_PIN_DISABLE_REQUEST = 1U << 0, ///< GPT output disabled due to GTETRG pin level + POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST = 1U << 1, ///< GPT output disabled due to high speed analog comparator or GPT + POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST = 1U << 2, ///< GPT output disabled due to main oscillator stop + POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST = 1U << 3, ///< GPT output disabled due to poeg_api_t::outputDisable() + + /** GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of + * the filtered input. */ + POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE = 1U << 16, + POEG_STATE_DSMIF0_DISABLE_REQUEST = 1U << 24, ///< GPT output disabled due to DSMIF0 error 0 + POEG_STATE_DSMIF1_DISABLE_REQUEST = 1U << 25, ///< GPT output disabled due to DSMIF1 error 0 +} poeg_state_t; + +/** Triggers that will disable GPT output pins. */ +typedef enum e_poeg_trigger +{ + /** Software disable is always supported with POEG. Select this option if no other triggers are used. */ + POEG_TRIGGER_SOFTWARE = 0U, + POEG_TRIGGER_PIN = 1U << 0, ///< Disable GPT output based on GTETRG input level + POEG_TRIGGER_GPT_OUTPUT_LEVEL = 1U << 1, ///< Disable GPT output based on GPT output pin levels + POEG_TRIGGER_OSCILLATION_STOP = 1U << 2, ///< Disable GPT output based on main oscillator stop + POEG_TRIGGER_ACMPHS0 = 1U << 4, ///< Disable GPT output based on ACMPHS0 comparator result + POEG_TRIGGER_ACMPHS1 = 1U << 5, ///< Disable GPT output based on ACMPHS1 comparator result + POEG_TRIGGER_ACMPHS2 = 1U << 6, ///< Disable GPT output based on ACMPHS2 comparator result + POEG_TRIGGER_ACMPHS3 = 1U << 7, ///< Disable GPT output based on ACMPHS3 comparator result + POEG_TRIGGER_ACMPHS4 = 1U << 8, ///< Disable GPT output based on ACMPHS4 comparator result + POEG_TRIGGER_ACMPHS5 = 1U << 9, ///< Disable GPT output based on ACMPHS5 comparator result + + /** The GPT output pins can be disabled when DSMIF error occurs (LLPP only). */ + POEG_TRIGGER_DERR0E = 1U << 22, ///< Permit output disabled by DSMIF0 error detection + POEG_TRIGGER_DERR1E = 1U << 23, ///< Permit output disabled by DSMIF1 error detection +} poeg_trigger_t; + +/*============================================== + * Transfer API Overrides + *==============================================*/ + +/** Events that can trigger a callback function. */ +typedef enum e_transfer_event +{ + TRANSFER_EVENT_TRANSFER_END = 0, ///< Transfer has completed. + TRANSFER_EVENT_TRANSFER_ERROR = 1, ///< Transfer error has occurred. +} transfer_event_t; + +/** Transfer mode describes what will happen when a transfer request occurs. */ +typedef enum e_transfer_mode +{ + /** Normal mode. */ + TRANSFER_MODE_NORMAL = 0, + + /** Block mode. */ + TRANSFER_MODE_BLOCK = 1 +} transfer_mode_t; + +/** Transfer size specifies the size of each individual transfer. */ +typedef enum e_transfer_size +{ + TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value + TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value + TRANSFER_SIZE_4_BYTE = 2, ///< Each transfer transfers a 32-bit value + TRANSFER_SIZE_8_BYTE = 3, ///< Each transfer transfers a 64-bit value + TRANSFER_SIZE_16_BYTE = 4, ///< Each transfer transfers a 128-bit value + TRANSFER_SIZE_32_BYTE = 5, ///< Each transfer transfers a 256-bit value + TRANSFER_SIZE_64_BYTE = 6 ///< Each transfer transfers a 512-bit value +} transfer_size_t; + +/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */ +typedef enum e_transfer_addr_mode +{ + /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_INCREMENTED = 0, + + /** Address pointer remains fixed after each transfer. */ + TRANSFER_ADDR_MODE_FIXED = 1 +} transfer_addr_mode_t; + +/** Callback function parameter data. */ +typedef struct st_transfer_callback_args_t +{ + transfer_event_t event; ///< Event code + void const * p_context; ///< Placeholder for user data. Set in transfer_api_t::open function in ::transfer_cfg_t. +} transfer_callback_args_t; + +/** This structure specifies the properties of the transfer. */ +typedef struct st_transfer_info +{ + /** Select what happens to destination pointer after each transfer. */ + transfer_addr_mode_t dest_addr_mode; + + /** Select what happens to source pointer after each transfer. */ + transfer_addr_mode_t src_addr_mode; + + /** Select mode from @ref transfer_mode_t. */ + transfer_mode_t mode; + + /** Source pointer. */ + void const * volatile p_src; + + /** Destination pointer. */ + void * volatile p_dest; + + /** Length of each transfer. */ + volatile uint32_t length; + + /** Select number of source bytes to transfer at once. */ + transfer_size_t src_size; + + /** Select number of destination bytes to transfer at once. */ + transfer_size_t dest_size; + + /** Next1 Register set settings */ + void const * p_next1_src; + void * p_next1_dest; + uint32_t next1_length; +} transfer_info_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/r_ioport/r_ioport.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/r_ioport/r_ioport.c new file mode 100644 index 00000000000..b8d65aa3968 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/r_ioport/r_ioport.c @@ -0,0 +1,957 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "r_ioport_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "PORT" in ASCII, used to determine if the module is open */ +#define IOPORT_OPEN (0x504F5254U) +#define IOPORT_CLOSED (0x00000000U) + +/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */ +#define IOPORT_PRV_PORT_OFFSET (8U) + +#define IOPORT_PRV_PORT_BITS (0xFF00U) +#define IOPORT_PRV_PIN_BITS (0x00FFU) + +#define IOPORT_PRV_8BIT_MASK (0x00FFU) + +/* Added definitions */ +#define IOPORT_PIN_NUM_MUX (8U) +#define IOPORT_REGION_SEL_SAFE (0U) +#define IOPORT_REGION_SEL_NSAFE (1U) +#define IOPORT_RSEL_MASK (0x01U) +#define IOPORT_PM_BIT_MASK (0x0003U) +#define IOPORT_PFC_BIT_MASK (0x0000000FU) +#define IOPORT_DRTCL_BIT_MASK (0x000000FFU) +#define IOPORT_ELC_PEL_MASK (0x80) +#define IOOPRT_ELC_PGC_MASK (0x88) +#define IOPORT_ELC_PEL_PSM_HIGH (0x20) + +/* Switch IOPORT register region either safety or non safety */ +#define IOPORT_PRV_PORT_ADDRESS(region_sel) (region_sel == 1 ? (R_PORT_NSR) : (R_PORT_SR)) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct st_ioport_cfg_data +{ + uint32_t p_reg : 1; + uint32_t pm_reg : 2; + uint32_t pmc_reg : 1; + uint32_t pfc_reg : 4; + uint32_t drct_reg : 6; + uint32_t rsel_reg : 1; + uint32_t reserved : 17; +} ioport_cfg_data_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_ioport_pins_config(const ioport_cfg_t * p_cfg); +static void r_ioport_pin_set(bsp_io_port_pin_t pin, ioport_cfg_data_t * p_cfg_data); +static void r_ioport_event_config(const ioport_extend_cfg_t * p_extend_cfg_data); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* IOPort Implementation of IOPort Driver */ +const ioport_api_t g_ioport_on_ioport = +{ + .open = R_IOPORT_Open, + .close = R_IOPORT_Close, + .pinsCfg = R_IOPORT_PinsCfg, + .pinCfg = R_IOPORT_PinCfg, + .pinEventInputRead = R_IOPORT_PinEventInputRead, + .pinEventOutputWrite = R_IOPORT_PinEventOutputWrite, + .pinRead = R_IOPORT_PinRead, + .pinWrite = R_IOPORT_PinWrite, + .portDirectionSet = R_IOPORT_PortDirectionSet, + .portEventInputRead = R_IOPORT_PortEventInputRead, + .portEventOutputWrite = R_IOPORT_PortEventOutputWrite, + .portRead = R_IOPORT_PortRead, + .portWrite = R_IOPORT_PortWrite, +}; + +/*******************************************************************************************************************//** + * @addtogroup IOPORT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes internal driver data, then calls pin configuration function to configure pins. + * + * @retval FSP_SUCCESS Pin configuration data written to the multiple registers + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_Open (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg) +{ + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data); + FSP_ERROR_RETURN(IOPORT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + /* Set driver status to open */ + p_instance_ctrl->open = IOPORT_OPEN; + + p_instance_ctrl->p_cfg = p_cfg; + + r_ioport_pins_config(p_cfg); + + r_ioport_event_config(p_cfg->p_extend); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets IOPORT registers. Implements @ref ioport_api_t::close + * + * @retval FSP_SUCCESS The IOPORT was successfully uninitialized + * @retval FSP_ERR_ASSERTION p_ctrl was NULL + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_Close (ioport_ctrl_t * const p_ctrl) +{ + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Set state to closed */ + p_instance_ctrl->open = IOPORT_CLOSED; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the functions of multiple pins by loading configuration data into the multiple registers. + * Implements @ref ioport_api_t::pinsCfg. + * + * This function initializes the supplied list of the multiple registers with the supplied values. This data can be generated + * by the Pins tab of the RZ/T2M Configuration editor or manually by the developer. Different pin configurations can be + * loaded for different situations such as low power modes and testing. + * + * @retval FSP_SUCCESS Pin configuration data written to the multiple registers + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinsCfg (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + r_ioport_pins_config(p_cfg); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the settings of a pin. Implements @ref ioport_api_t::pinCfg. + * + * @retval FSP_SUCCESS Pin configured + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different pins. + * This function will change the configuration of the pin with the new configuration. For example it is not possible + * with this function to change the drive strength of a pin while leaving all the other pin settings unchanged. To + * achieve this the original settings with the required change will need to be written using this function. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinCfg (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + R_BSP_PinAccessEnable(); + + r_ioport_pin_set(pin, (ioport_cfg_data_t *) &cfg); + + R_BSP_PinAccessDisable(); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the level on a pin. Implements @ref ioport_api_t::pinRead. + * + * The level for the specifed pin will be reterned by PINm register. + * + * @retval FSP_SUCCESS Pin read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + * @note This function is re-entrant for different pins. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_pin_value); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + *p_pin_value = (bsp_io_level_t) R_BSP_FastPinRead(R_BSP_IoRegionGet(pin), pin); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value on an IO port. Implements @ref ioport_api_t::portRead. + * + * The specified port will be read, and the levels for all the pins will be returned by PINm register. + * Each bit in the returned value corresponds to a pin on the port. For example, bit 7 corresponds + * to pin 7, bit 6 to pin 6, and so on. + * + * @retval FSP_SUCCESS Port read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_port_value); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + R_PORT_COMMON_Type * p_ioport_regs; + ioport_size_t safe_value; + ioport_size_t nsafe_value; + + /* Get port number */ + uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) port) >> IOPORT_PRV_PORT_OFFSET; + + /* Get the RSELP register value */ + ioport_size_t rselp_value = (ioport_size_t) R_PTADR->RSELP[port_num]; + + /* Get the port register address in non safety region */ + p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + + /* Read the specified port states in non safety region */ + nsafe_value = (ioport_size_t) (p_ioport_regs->PIN[port_num] & rselp_value); + + /* Get the port register address in safety region */ + p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_SAFE); + + /* Read the specified port states in safety region */ + safe_value = (ioport_size_t) (p_ioport_regs->PIN[port_num] & ~(rselp_value)); + + /* Read the specified port states */ + *p_port_value = nsafe_value | safe_value; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Writes to multiple pins on a port. Implements @ref ioport_api_t::portWrite. + * + * The output value will be written to the specified port. Each bit in the value parameter corresponds to a bit + * on the port. For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on. + * Each bit in the mask parameter corresponds to a pin on the port. + * + * Only the bits with the corresponding bit in the mask value set will be updated. + * For example, value = 0x00FF, mask = 0x0003 results in only bits 0 and 1 being updated. + * + * @retval FSP_SUCCESS Port written to + * @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointerd + * + * @note This function is re-entrant for different ports. This function makes use of the Pm register to atomically + * modify the levels on the specified pins on a port. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + R_PORT_COMMON_Type * p_ioport_regs; + ioport_size_t temp_value; + ioport_size_t write_mask; + + /* mask value: lower word is valid, upper word is invalid */ + mask &= IOPORT_PRV_8BIT_MASK; + + /* Get port number */ + uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) port) >> IOPORT_PRV_PORT_OFFSET; + + /* Get the RSELP register value */ + ioport_size_t rselp_value = R_PTADR->RSELP[port_num]; + + /* Set value to non safety region register */ + write_mask = rselp_value & mask; + if (write_mask) + { + /* Get the port register address */ + p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + + /* Output data store of the specified pins sets to low output */ + temp_value = (ioport_size_t) (p_ioport_regs->P[port_num] & (~write_mask)); + + /* Write output data to P register of the specified pins */ + p_ioport_regs->P[port_num] = (uint8_t) (temp_value | (value & write_mask)); + } + + /* Set value to safety region register */ + write_mask = (ioport_size_t) ((~rselp_value) & mask); + if (write_mask) + { + /* Get the port register address */ + p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_SAFE); + + /* Output data store of the specified pins sets to low output */ + temp_value = (ioport_size_t) (p_ioport_regs->P[port_num] & (~write_mask)); + + /* Write output data to P register of the specified pins */ + p_ioport_regs->P[port_num] = (uint8_t) (temp_value | (value & write_mask)); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets a pin's output either high or low. Implements @ref ioport_api_t::pinWrite. + * + * @retval FSP_SUCCESS Pin written to + * @retval FSP_ERR_INVALID_ARGUMENT The pin and/or level not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opene + * @retval FSP_ERR_ASSERTION NULL pointerd + * + * @note This function is re-entrant for different pins. This function makes use of the Pm register to atomically + * modify the level on the specified pin on a port. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(level <= BSP_IO_LEVEL_HIGH, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + R_PORT_COMMON_Type * p_ioport_regs; + + /* Get port and pin number */ + uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin) >> IOPORT_PRV_PORT_OFFSET; + uint32_t pin_num = (IOPORT_PRV_PIN_BITS & (ioport_size_t) pin); + + /* Get the port register address */ + p_ioport_regs = (IOPORT_PRV_PORT_ADDRESS(((uint16_t) (R_PTADR->RSELP[port_num] >> pin_num) & + IOPORT_RSEL_MASK))); + + /* Set output level to P register of the specified pin */ + if (BSP_IO_LEVEL_LOW == level) + { + p_ioport_regs->P[port_num] &= (uint8_t) (~(1U << pin_num)); + } + else + { + p_ioport_regs->P[port_num] |= (uint8_t) (1U << pin_num); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets the direction of individual pins on a port. Implements @ref ioport_api_t::portDirectionSet(). + * + * Multiple pins on a port can be set to inputs or outputs at once. + * Each bit in the mask parameter corresponds to a pin on the port. For example, bit 7 corresponds to + * pin 7, bit 6 to pin 6, and so on. If a mask bit is set to 1 then the corresponding pin will be changed to + * an input or an output as specified by the direction values. If a mask bit is set to 0 then the direction of + * the pin will not be changed. + * + * @retval FSP_SUCCESS Port direction updated + * @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortDirectionSet (ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t direction_values, + ioport_size_t mask) +{ + uint32_t pin_num; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask > (uint16_t) 0, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* mask value: lower word is valid, upper word is invalid */ + mask &= IOPORT_PRV_8BIT_MASK; + + for (pin_num = 0U; pin_num < IOPORT_PIN_NUM_MUX; pin_num++) + { + if (mask & (1U << pin_num)) + { + /* Get port number */ + uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) port) >> IOPORT_PRV_PORT_OFFSET; + + /* Get the port register address */ + R_PORT_COMMON_Type * p_ioport_regs = + IOPORT_PRV_PORT_ADDRESS(((uint16_t) (R_PTADR->RSELP[port_num] >> pin_num) & + IOPORT_RSEL_MASK)); + + /* Set */ + uint16_t set_bits = (uint16_t) (direction_values & (IOPORT_PM_BIT_MASK << (pin_num * 2U))); + + /* Set the direction value */ + uint16_t temp_value = (uint16_t) (p_ioport_regs->PM[port_num] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U))); + p_ioport_regs->PM[port_num] = temp_value | set_bits; + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value of the event input data. Implements @ref ioport_api_t::portEventInputRead(). + * + * The event input data for the port will be read. Each bit in the returned value corresponds to a pin on the port. + * For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on. + * + * The port event data is captured in response to a trigger from the ELC. This function enables this data to be read. + * Using the event system allows the captured data to be stored when it occurs and then read back at a later time. + * + * @retval FSP_SUCCESS Port read + * @retval FSP_ERR_INVALID_ARGUMENT Port not a valid ELC port + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data) +{ + uint8_t portgroup = 0U; + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_event_data); + FSP_ERROR_RETURN((port == BSP_IO_PORT_16) || (port == BSP_IO_PORT_18), FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + const ioport_extend_cfg_t * elc_cfg = p_instance_ctrl->p_cfg->p_extend; + + /* Get register address */ + R_PORT_COMMON_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + + /* Get port group number for the specified port */ + if (BSP_IO_PORT_16 == port) + { + portgroup = 0U; + } + else if (BSP_IO_PORT_18 == port) + { + portgroup = 1U; + } + else + { + /* Do Nothing */ + } + + /* Read current value of buffer value from ELC_PDBF register for the specified port group */ + *p_event_data = + (uint16_t) (p_ioport_regs->ELC_PDBF[portgroup].BY & elc_cfg->port_group_input_cfg[portgroup].pin_select); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value of the event input data of a specific pin. Implements @ref ioport_api_t::pinEventInputRead. + * + * The pin event data is captured in response to a trigger from the ELC. This function enables this data to be read. + * Using the event system allows the captured data to be stored when it occurs and then read back at a later time. + * + * @retval FSP_SUCCESS Pin read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_INVALID_ARGUMENT Port is not valid ELC PORT. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event) +{ + uint8_t portgroup = 0U; + uint8_t portvalue; + uint8_t mask; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_pin_event); + uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((port_number == BSP_IO_PORT_16 >> IOPORT_PRV_PORT_OFFSET) || + (port_number == BSP_IO_PORT_18 >> IOPORT_PRV_PORT_OFFSET), + FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Get port and pin number */ + uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin); + uint32_t pin_num = (IOPORT_PRV_PIN_BITS & (ioport_size_t) pin); + + /* Get register address */ + R_PORT_COMMON_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + + /* Get port group number for the specified port */ + if (BSP_IO_PORT_16 == port_num) + { + portgroup = 0U; + } + else if (BSP_IO_PORT_18 == port_num) + { + portgroup = 1U; + } + else + { + /* Do Nothing */ + } + + /* Read current value of buffer value from ELC_PDBF register for the specified port group */ + portvalue = p_ioport_regs->ELC_PDBF[portgroup].BY; + mask = (uint8_t) (1U << pin_num); + + if ((portvalue & mask) == mask) + { + *p_pin_event = BSP_IO_LEVEL_HIGH; + } + else + { + *p_pin_event = BSP_IO_LEVEL_LOW; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function writes the set and reset event output data for a port. Implements + * @ref ioport_api_t::portEventOutputWrite. + * + * Using the event system enables a port state to be stored by this function in advance of being output on the port. + * The output to the port will occur when the ELC event occurs. + * + * The input value will be written to the specified port when an ELC event configured for that port occurs. + * Each bit in the value parameter corresponds to a bit on the port. For example, bit 7 corresponds to pin 7, + * bit 6 to pin 6, and so on. Each bit in the mask parameter corresponds to a pin on the port. + * + * @retval FSP_SUCCESS Port event data written + * @retval FSP_ERR_INVALID_ARGUMENT Port or Mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortEventOutputWrite (ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t event_data, + ioport_size_t mask_value) +{ + uint8_t portgroup = 0U; + ioport_size_t temp_value; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask_value > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((port == BSP_IO_PORT_16) || (port == BSP_IO_PORT_18), FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + R_BSP_PinAccessEnable(); // Unlock Register Write Protection + + /* Get register address */ + R_PORT_COMMON_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + + /* Get port group number for the specified port */ + if (BSP_IO_PORT_16 == port) + { + portgroup = 0U; + } + else if (BSP_IO_PORT_18 == port) + { + portgroup = 1U; + } + else + { + /* Do Nothing */ + } + + temp_value = p_ioport_regs->ELC_PDBF[portgroup].BY; + temp_value &= (ioport_size_t) (~mask_value); + + p_ioport_regs->ELC_PDBF[portgroup].BY = (uint8_t) (temp_value | event_data); + + R_BSP_PinAccessDisable(); // Lock Register Write Protection + + return FSP_SUCCESS; +} + +/**********************************************************************************************************************//** + * This function writes the event output data value to a pin. Implements @ref ioport_api_t::pinEventOutputWrite. + * + * Using the event system enables a pin state to be stored by this function in advance of being output on the pin. + * The output to the pin will occur when the ELC event occurs. + * + * @retval FSP_SUCCESS Pin event data written + * @retval FSP_ERR_INVALID_ARGUMENT Port or Pin or value not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value) +{ + uint8_t singleport = 0U; + uint8_t cnt; + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN((pin_value == BSP_IO_LEVEL_HIGH) || (pin_value == BSP_IO_LEVEL_LOW), FSP_ERR_INVALID_ARGUMENT); + uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((port_number == BSP_IO_PORT_16 >> IOPORT_PRV_PORT_OFFSET) || + (port_number == BSP_IO_PORT_18 >> IOPORT_PRV_PORT_OFFSET), + FSP_ERR_INVALID_ARGUMENT); +#endif + + const ioport_extend_cfg_t * elc_cfg = p_instance_ctrl->p_cfg->p_extend; + + R_BSP_PinAccessEnable(); // Unlock Register Write Protection + + /* Get register address */ + R_PORT_COMMON_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + + for (cnt = 0; cnt < IOPORT_SINGLE_PORT_NUM; cnt++) + { + if ((bsp_io_port_pin_t) elc_cfg->single_port_cfg[cnt].port_num == pin) + { + singleport = cnt; + } + } + + if (BSP_IO_LEVEL_HIGH == pin_value) + { + p_ioport_regs->ELC_PEL[singleport] |= (uint8_t) IOPORT_ELC_PEL_PSM_HIGH; + } + else + { + p_ioport_regs->ELC_PEL[singleport] &= (uint8_t) (~IOPORT_ELC_PEL_PSM_HIGH); + } + + R_BSP_PinAccessDisable(); // Lock Register Write Protection + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup IOPORT) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures pins. + * + * @param[in] p_cfg Pin configuration data + **********************************************************************************************************************/ +void r_ioport_pins_config (const ioport_cfg_t * p_cfg) +{ + uint16_t pin_count; + ioport_cfg_t * p_pin_data; + + p_pin_data = (ioport_cfg_t *) p_cfg; + + R_BSP_PinAccessEnable(); // Unlock Register Write Protection + + for (pin_count = 0U; pin_count < p_pin_data->number_of_pins; pin_count++) + { + r_ioport_pin_set(p_pin_data->p_pin_cfg_data[pin_count].pin, + (ioport_cfg_data_t *) &p_pin_data->p_pin_cfg_data[pin_count].pin_cfg); + } + + R_BSP_PinAccessDisable(); // Lock Register Write Protection +} + +/*******************************************************************************************************************//** + * Writes to the specified pin's multiple registers + * + * @param[in] pin Pin to write parameter data for + * @param[in] p_cfg_data Value to be written to the multiple registers + * + **********************************************************************************************************************/ +static void r_ioport_pin_set (bsp_io_port_pin_t pin, ioport_cfg_data_t * p_cfg_data) +{ + R_PORT_COMMON_Type * p_ioport_regs; + uint32_t temp_value; + + /* Get port and pin number */ + uint32_t port = (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin) >> IOPORT_PRV_PORT_OFFSET; + uint32_t pin_num = (IOPORT_PRV_PIN_BITS & (ioport_size_t) pin); + + /* Setting for Safety region or Non safety region */ + if (p_cfg_data->rsel_reg == 1U) // Setting for Non safety region + { + R_PTADR->RSELP[port] |= (uint8_t) (1U << pin_num); + p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + } + else // Setting for Safety region + { + R_PTADR->RSELP[port] &= (uint8_t) (~(1U << pin_num)); + p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_SAFE); + } + + /* Setting DRCTL register */ + if (3U >= pin_num) + { + temp_value = p_ioport_regs->DRCTL[port].L & ~(IOPORT_DRTCL_BIT_MASK << (pin_num * 8U)); + p_ioport_regs->DRCTL[port].L = temp_value | (uint32_t) (p_cfg_data->drct_reg << (pin_num * 8U)); + } + else if (3U < pin_num) + { + temp_value = p_ioport_regs->DRCTL[port].H & ~(IOPORT_DRTCL_BIT_MASK << ((pin_num - 4U) * 8U)); + p_ioport_regs->DRCTL[port].H = temp_value | (uint32_t) (p_cfg_data->drct_reg << ((pin_num - 4U) * 8U)); + } + else + { + /* Do Nothing */ + } + + /* Setting for GPIO or peripheral */ + if (1U == p_cfg_data->pmc_reg) // Setting for peripheral + { + temp_value = p_ioport_regs->PFC[port] & ~(IOPORT_PFC_BIT_MASK << (pin_num * 4U)); + p_ioport_regs->PFC[port] = temp_value | (uint32_t) (p_cfg_data->pfc_reg << (pin_num * 4U)); // Setting PFC register + + /* Setting peripheral for port mode */ + p_ioport_regs->PMC[port] |= (uint8_t) (p_cfg_data->pmc_reg << pin_num); // Setting PMC register + } + else // Setting for GPIO + { + /* Setting GPIO for port mode */ + p_ioport_regs->PMC[port] &= (uint8_t) (~(1U << pin_num)); // Setting PMC register + + /* Setting for input or output */ + if (1U == p_cfg_data->pm_reg) // Setting for input + { + /* Setting PM register. */ + /* 01b: Input */ + temp_value = (uint32_t) (p_ioport_regs->PM[port] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U))); + p_ioport_regs->PM[port] = (uint16_t) (temp_value | (uint32_t) (1U << (pin_num * 2U))); + } + else if (1U < p_cfg_data->pm_reg) // Setting for two kinds of Output + { + /* Setting P register */ + if (0U == p_cfg_data->p_reg) // Low output setting + { + p_ioport_regs->P[port] &= (uint8_t) (~(1U << pin_num)); + } + else if (1U == p_cfg_data->p_reg) // High output setting + { + p_ioport_regs->P[port] |= (uint8_t) (1U << pin_num); + } + else + { + /* Do Nothing */ + } + + /* Setting PM register. */ + /* 10b: Output */ + /* 11b: Output(output data is input to input buffer) */ + temp_value = (uint32_t) (p_ioport_regs->PM[port] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U))); + p_ioport_regs->PM[port] = (uint16_t) (temp_value | (uint32_t) (p_cfg_data->pm_reg << (pin_num * 2U))); + } + else + { + /* Do Nothing */ + } + } +} + +/*******************************************************************************************************************//** + * Writes to the specified pin's multiple registers to generate event link function + * + * @param[in] p_extend_cfg_data Value to be written to the multiple registers + * + **********************************************************************************************************************/ +static void r_ioport_event_config (const ioport_extend_cfg_t * p_extend_cfg_data) +{ + uint8_t event_num; + uint8_t temp_value = 0x00; + uint8_t single_enable = 0x00; + uint8_t group_enable = 0x00; + R_PORT_COMMON_Type * p_ioport_regs; + ioport_extend_cfg_t * ex_cfg; + + ex_cfg = (ioport_extend_cfg_t *) p_extend_cfg_data; + + R_BSP_PinAccessEnable(); // Unlock Register Write Protection + + /* Get register address */ + p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + + /* Single port configuration */ + for (event_num = 0U; event_num < IOPORT_SINGLE_PORT_NUM; event_num++) + { + uint8_t port = + (uint8_t) ((ex_cfg->single_port_cfg[event_num].port_num & IOPORT_PRV_PORT_BITS) >> IOPORT_PRV_PORT_OFFSET); + uint8_t pin_num = (uint8_t) ex_cfg->single_port_cfg[event_num].port_num & IOPORT_PRV_PIN_BITS; + + temp_value = p_ioport_regs->ELC_PEL[event_num] & IOPORT_ELC_PEL_MASK; + + /* Port selection */ + if ((BSP_IO_PORT_16 >> IOPORT_PRV_PORT_OFFSET) == port) + { + temp_value |= 1U << 3; + } + else if ((BSP_IO_PORT_18 >> IOPORT_PRV_PORT_OFFSET) == port) + { + temp_value |= 1U << 4; + } + else + { + /* Do Nothing */ + } + + temp_value |= pin_num; // Pin number setting + + /* When the pin specified as single input port, Set edge detection */ + /* When the pin specified as single output port, Set output operation */ + if (IOPORT_EVENT_DIRECTION_INPUT == ex_cfg->single_port_cfg[event_num].direction) + { + temp_value |= (uint8_t) (ex_cfg->single_port_cfg[event_num].edge_detection << 5); // Edge detection + + /* Edge detection enable */ + p_ioport_regs->ELC_DPTC |= (uint8_t) (1U << event_num); + } + else + { + temp_value |= (uint8_t) (ex_cfg->single_port_cfg[event_num].operation << 5); // Output operation + } + + /* Set to ELC port setting register */ + p_ioport_regs->ELC_PEL[event_num] = temp_value; + + /* Single port event link function enable */ + if (IOPORT_EVENT_CONTROL_ENABLE == ex_cfg->single_port_cfg[event_num].event_control) + { + single_enable |= (uint8_t) (1U << event_num); + } + } + + /* Port group configuration */ + for (event_num = 0U; event_num < IOPORT_PORT_GROUP_NUM; event_num++) + { + /* Pin selection */ + uint8_t group_pin = ex_cfg->port_group_input_cfg[event_num].pin_select | + ex_cfg->port_group_output_cfg[event_num].pin_select; + p_ioport_regs->ELC_PGR[event_num] = group_pin; + + if (IOPORT_EVENT_CONTROL_ENABLE == ex_cfg->port_group_input_cfg[event_num].event_control) + { + /* Input port group control */ + temp_value = p_ioport_regs->ELC_PGC[event_num] & IOOPRT_ELC_PGC_MASK; + temp_value |= ex_cfg->port_group_input_cfg[event_num].edge_detection; // Edge detection + temp_value |= (uint8_t) (ex_cfg->port_group_input_cfg[event_num].overwrite_control << 2U); // Overwrite setting + + /* Buffer register initialization */ + p_ioport_regs->ELC_PDBF[event_num].BY = ex_cfg->port_group_input_cfg[event_num].buffer_init_value; + + /* Input port group event link function enable */ + group_enable |= (uint8_t) (1U << event_num); + } + + /* Output port group operation */ + temp_value |= (uint8_t) (ex_cfg->port_group_output_cfg[event_num].operation << 4); + + /* Set to port group control register */ + p_ioport_regs->ELC_PGC[event_num] = temp_value; + } + + /* Set to ELC port event control register */ + p_ioport_regs->ELC_ELSR2 = (uint8_t) ((single_enable << 4) | (group_enable << 2)); + + R_BSP_PinAccessDisable(); // Lock Register Write Protection +} diff --git a/bsp/renesas/rzt2m_rsk/rzt/fsp/src/r_sci_uart/r_sci_uart.c b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/r_sci_uart/r_sci_uart.c new file mode 100644 index 00000000000..dff83ec6b74 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt/fsp/src/r_sci_uart/r_sci_uart.c @@ -0,0 +1,1934 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_sci_uart.h" +#include + +#if SCI_UART_CFG_DMAC_SUPPORTED + #include "r_dmac.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#ifndef SCI_UART_CFG_RX_ENABLE + #define SCI_UART_CFG_RX_ENABLE 1 +#endif +#ifndef SCI_UART_CFG_TX_ENABLE + #define SCI_UART_CFG_TX_ENABLE 1 +#endif + +/** Number of divisors in the data table used for baud rate calculation. */ +#define SCI_UART_NUM_DIVISORS_ASYNC (13U) + +/** Valid range of values for the modulation duty register is 128 - 256 (256 = modulation disabled). */ +#define SCI_UART_MDDR_MIN (128U) +#define SCI_UART_MDDR_MAX (256U) + +/** The bit rate register is 8-bits, so the maximum value is 255. */ +#define SCI_UART_BRR_MAX (255U) + +/** No limit to the number of bytes to read or write if DMAC is not used. */ +#define SCI_UART_MAX_READ_WRITE_NO_DMAC (0xFFFFFFFFU) + +/** Mask of invalid data bits in 9-bit mode. */ +#define SCI_UART_ALIGN_2_BYTES (0x1U) + +/** Clock frequency 96MHz. */ +#define SCI_UART_CLOCK_96MHZ (96000000) + +/** "SCIU" in ASCII. Used to determine if the control block is open. */ +#define SCI_UART_OPEN (0x53434955U) + +#define SCI_UART_BRR_DEFAULT_VALUE (0xFFU) +#define SCI_UART_MDDR_DEFAULT_VALUE (0xFFU) +#define SCI_UART_FCR_DEFAULT_VALUE (0x1F1F0000) + +#define SCI_UART_CCR0_DEFAULT_VALUE (0x00000000) +#define SCI_UART_CCR1_DEFAULT_VALUE (0x00000010) +#define SCI_UART_CCR2_DEFAULT_VALUE (0xFF00FF04) +#define SCI_UART_CCR3_DEFAULT_VALUE (0x00001203) +#define SCI_UART_CCR4_DEFAULT_VALUE (0x00000000) + +#define SCI_UART_CFCLR_ALL_FLAG_CLEAR (0xBD070010) +#define SCI_UART_FFCLR_ALL_FLAG_CLEAR (0x00000001) + +/** SCI CCR0 register bit masks */ +#define SCI_UART_CCR0_IDSEL_MASK (0x00000400) +#define SCI_UART_CCR0_TEIE_MASK (0x00200000) +#define SCI_UART_CCR0_RE_MASK (0x00000001) +#define SCI_UART_CCR0_TE_MASK (0x00000010) +#define SCI_UART_CCR0_RIE_MASK (0x00010000) +#define SCI_UART_CCR0_TIE_MASK (0x00100000) + +/** SCI CCR1 register bit offsets */ +#define SCI_UART_CCR1_CTSE_OFFSET (0U) +#define SCI_UART_CCR1_SPB2DT_BIT (4U) +#define SCI_UART_CCR1_OUTPUT_ENABLE_MASK (0x00000020) +#define SCI_UART_CCR1_PARITY_OFFSET (8U) +#define SCI_UART_CCR1_PARITY_MASK (0x00000300U) +#define SCI_UART_CCR1_FLOW_CTSRTS_MASK (0x00000003U) +#define SCI_UART_CCR1_NFCS_OFFSET (24U) +#define SCI_UART_CCR1_NFCS_VALUE_MASK (0x07U) +#define SCI_UART_CCR1_NFEN_OFFSET (28U) + +/** SCI CCR2 register bit offsets */ +#define SCI_UART_CCR2_BRME_OFFSET (16U) +#define SCI_UART_CCR2_ABCSE_OFFSET (6U) +#define SCI_UART_CCR2_ABCS_OFFSET (5U) +#define SCI_UART_CCR2_BDGM_OFFSET (4U) +#define SCI_UART_CCR2_CKS_OFFSET (20U) +#define SCI_UART_CCR2_CKS_VALUE_MASK (0x03U) ///< CKS: 2 bits +#define SCI_UART_CCR2_BRR_OFFSET (8U) +#define SCI_UART_CCR2_BRR_VALUE_MASK (0xFFU) ///< BRR: 8bits +#define SCI_UART_CCR2_MDDR_OFFSET (24U) +#define SCI_UART_CCR2_MDDR_VALUE_MASK (0xFFU) ///< MDDR: 8bits + +#define SCI_UART_CCR2_BAUD_SETTING_MASK ((1U << SCI_UART_CCR2_BRME_OFFSET) | \ + (1U << SCI_UART_CCR2_ABCSE_OFFSET) | \ + (1U << SCI_UART_CCR2_ABCS_OFFSET) | \ + (1U << SCI_UART_CCR2_BDGM_OFFSET) | \ + (SCI_UART_CCR2_CKS_VALUE_MASK << SCI_UART_CCR2_CKS_OFFSET) | \ + (SCI_UART_CCR2_BRR_VALUE_MASK << SCI_UART_CCR2_BRR_OFFSET) | \ + (SCI_UART_CCR2_MDDR_VALUE_MASK << SCI_UART_CCR2_MDDR_OFFSET)) + +/** SCI CCR3 register bit masks */ +#define SCI_UART_CCR3_BPEN_OFFSET (7U) +#define SCI_UART_CCR3_CHR_OFFSET (8U) +#define SCI_UART_CCR3_STP_OFFSET (14U) +#define SCI_UART_CCR3_RxDSEL_OFFSET (15U) +#define SCI_UART_CCR3_FM_OFFSET (20U) +#define SCI_UART_CCR3_CKE_OFFSET (24U) +#define SCI_UART_CCR3_CKE_MASK (0x03000000U) +#define SCI_UART_CCR3_CKE_VALUE_MASK (0x03U) + +/** SCI CSR register receiver error bit masks */ +#define SCI_UART_CSR_ORER_MASK (0x01000000) +#define SCI_UART_CSR_FER_MASK (0x10000000) +#define SCI_UART_CSR_PER_MASK (0x08000000) +#define SCI_UART_RCVR_ERR_MASK (SCI_UART_CSR_ORER_MASK | SCI_UART_CSR_FER_MASK | SCI_UART_CSR_PER_MASK) + +/** SCI CFCLR register receiver clear error bit masks */ +#define SCI_UART_CFCLR_ORERC_MASK (0x01000000) +#define SCI_UART_CFCLR_FERC_MASK (0x10000000) +#define SCI_UART_CFCLE_PERC_MASK (0x08000000) +#define SCI_UART_RCVR_ERRCLR_MASK (SCI_UART_CFCLR_ORERC_MASK | SCI_UART_CFCLR_FERC_MASK | \ + SCI_UART_CFCLE_PERC_MASK) + +#define SCI_REG_SIZE (R_SCI1_BASE - R_SCI0_BASE) + +#define SCI_UART_INVALID_8BIT_PARAM (0xFFU) +#define SCI_UART_INVALID_16BIT_PARAM (0xFFFFU) + +#define SCI_UART_TDR_9BIT_MASK (0x1FFU) + +#define SCI_UART_FCR_TRIGGER_MASK (0xF) +#define SCI_UART_FCR_RSTRG_OFFSET (24U) +#define SCI_UART_FCR_RTRG_OFFSET (16U) +#define SCI_UART_FCR_TTRG_OFFSET (8U) +#define SCI_UART_FCR_TTRG_DMAC_VALUE (0x0F) +#define SCI_UART_FCR_RESET_TX_RX (0x00808000) + +#define SCI_UART_DMAC_MAX_TRANSFER (0xFFFFFFFFU) + +/*********************************************************************************************************************** + * Private constants + **********************************************************************************************************************/ +static const int32_t SCI_UART_100_PERCENT_X_1000 = 100000; +static const int32_t SCI_UART_MDDR_DIVISOR = 256; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) +static const uint32_t SCI_UART_MAX_BAUD_RATE_ERROR_X_1000 = 15000; +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct st_baud_setting_const_t +{ + uint8_t bgdm : 1; /**< BGDM value to get divisor */ + uint8_t abcs : 1; /**< ABCS value to get divisor */ + uint8_t abcse : 1; /**< ABCSE value to get divisor */ + uint8_t cks : 2; /**< CKS value to get divisor (CKS = N) */ +} baud_setting_const_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + +static fsp_err_t r_sci_read_write_param_check(sci_uart_instance_ctrl_t const * const p_instance_ctrl, + uint8_t const * const addr, + uint32_t const bytes); + +#endif + +static void r_sci_uart_config_set(sci_uart_instance_ctrl_t * const p_instance_ctrl, uart_cfg_t const * const p_cfg); + +#if SCI_UART_CFG_DMAC_SUPPORTED +static fsp_err_t r_sci_uart_transfer_configure(sci_uart_instance_ctrl_t * const p_instance_ctrl, + transfer_instance_t const * p_transfer, + uint32_t * p_transfer_reg, + uint32_t address); + +static fsp_err_t r_sci_uart_transfer_open(sci_uart_instance_ctrl_t * const p_instance_ctrl, + uart_cfg_t const * const p_cfg); + +static void r_sci_uart_transfer_close(sci_uart_instance_ctrl_t * p_instance_ctrl); + +#endif + +static void r_sci_uart_baud_set(R_SCI0_Type * p_sci_reg, sci_baud_setting_t const * const p_baud_setting); +static void r_sci_uart_call_callback(sci_uart_instance_ctrl_t * p_instance_ctrl, uint32_t data, uart_event_t event); + +#if SCI_UART_CFG_FIFO_SUPPORT +static void r_sci_uart_fifo_cfg(sci_uart_instance_ctrl_t * const p_instance_ctrl); + +#endif + +static void r_sci_irq_cfg(sci_uart_instance_ctrl_t * const p_instance_ctrl, uint8_t const ipl, IRQn_Type const p_irq); + +static void r_sci_irqs_cfg(sci_uart_instance_ctrl_t * const p_instance_ctrl, uart_cfg_t const * const p_cfg); + +#if (SCI_UART_CFG_TX_ENABLE) +void r_sci_uart_write_no_transfer(sci_uart_instance_ctrl_t * const p_instance_ctrl); + +#endif + +#if (SCI_UART_CFG_RX_ENABLE) +void r_sci_uart_rxi_read_no_transfer(sci_uart_instance_ctrl_t * const p_instance_ctrl); + +static void sci_uart_rxi_common(sci_uart_instance_ctrl_t * p_instance_ctrl); + +void sci_uart_rxi_isr(void); + +void sci_uart_rx_dmac_callback(sci_uart_instance_ctrl_t * p_instance_ctrl); + +void r_sci_uart_read_data(sci_uart_instance_ctrl_t * const p_instance_ctrl, uint32_t * const p_data); + +void sci_uart_eri_isr(void); + +#endif + +#if (SCI_UART_CFG_TX_ENABLE) +static void sci_uart_txi_common(sci_uart_instance_ctrl_t * p_instance_ctrl); + +void sci_uart_txi_isr(void); + +void sci_uart_tx_dmac_callback(sci_uart_instance_ctrl_t * p_instance_ctrl); + +void sci_uart_tei_isr(void); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/** Name of module used by error logger macro */ +#if BSP_CFG_ERROR_LOG != 0 +static const char g_module_name[] = "sci_uart"; +#endif + +/** Baud rate divisor information (UART mode) */ +static const baud_setting_const_t g_async_baud[SCI_UART_NUM_DIVISORS_ASYNC] = +{ + {0U, 0U, 1U, 0U}, /* BGDM, ABCS, ABCSE, n */ + {1U, 1U, 0U, 0U}, + {1U, 0U, 0U, 0U}, + {0U, 0U, 1U, 1U}, + {0U, 0U, 0U, 0U}, + {1U, 0U, 0U, 1U}, + {0U, 0U, 1U, 2U}, + {0U, 0U, 0U, 1U}, + {1U, 0U, 0U, 2U}, + {0U, 0U, 1U, 3U}, + {0U, 0U, 0U, 2U}, + {1U, 0U, 0U, 3U}, + {0U, 0U, 0U, 3U} +}; + +static const uint16_t g_div_coefficient[SCI_UART_NUM_DIVISORS_ASYNC] = +{ + 6U, + 8U, + 16U, + 24U, + 32U, + 64U, + 96U, + 128U, + 256U, + 384U, + 512U, + 1024U, + 2048U, +}; + +/** UART on SCI HAL API mapping for UART interface */ +const uart_api_t g_uart_on_sci = +{ + .open = R_SCI_UART_Open, + .close = R_SCI_UART_Close, + .write = R_SCI_UART_Write, + .read = R_SCI_UART_Read, + .infoGet = R_SCI_UART_InfoGet, + .baudSet = R_SCI_UART_BaudSet, + .communicationAbort = R_SCI_UART_Abort, + .callbackSet = R_SCI_UART_CallbackSet, + .readStop = R_SCI_UART_ReadStop, +}; + +/*******************************************************************************************************************//** + * @addtogroup SCI_UART + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures the UART driver based on the input configurations. If reception is enabled at compile time, reception is + * enabled at the end of this function. Implements @ref uart_api_t::open + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested channel does not exist on this MCU. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid input parameter. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check parameters. */ + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_cfg); + FSP_ASSERT(p_cfg->p_callback); + FSP_ASSERT(p_cfg->p_extend); + FSP_ASSERT(((sci_uart_extended_cfg_t *) p_cfg->p_extend)->p_baud_setting); + FSP_ERROR_RETURN(SCI_UART_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Make sure this channel exists. */ + FSP_ERROR_RETURN(BSP_FEATURE_SCI_CHANNELS & (1U << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + #if SCI_UART_CFG_DMAC_SUPPORTED + #if (SCI_UART_CFG_RX_ENABLE) + if (NULL != p_cfg->p_transfer_rx) + { + /* DMAC activation is not available for safety channel. */ + FSP_ERROR_RETURN(BSP_FEATURE_SCI_SAFETY_CHANNEL != p_cfg->channel, FSP_ERR_INVALID_ARGUMENT); + } + #endif + #if (SCI_UART_CFG_TX_ENABLE) + if (NULL != p_cfg->p_transfer_tx) + { + /* DMAC activation is not available for safety channel. */ + FSP_ERROR_RETURN(BSP_FEATURE_SCI_SAFETY_CHANNEL != p_cfg->channel, FSP_ERR_INVALID_ARGUMENT); + } + #endif + #endif + + if (SCI_UART_FLOW_CONTROL_CTSRTS == ((sci_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control) + { + FSP_ERROR_RETURN( + ((sci_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control_pin != (bsp_io_port_pin_t) SCI_UART_INVALID_16BIT_PARAM, + FSP_ERR_INVALID_ARGUMENT); + } + + if (SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS == ((sci_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control) + { + FSP_ERROR_RETURN((0U != (((1U << (p_cfg->channel)) & BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS))), + FSP_ERR_INVALID_ARGUMENT); + } + + FSP_ASSERT(UART_PARITY_ZERO != p_cfg->parity); + FSP_ASSERT(p_cfg->rxi_irq >= 0); + FSP_ASSERT(p_cfg->txi_irq >= 0); + FSP_ASSERT(p_cfg->tei_irq >= 0); + FSP_ASSERT(p_cfg->eri_irq >= 0); +#endif + + p_instance_ctrl->fifo_depth = 0U; +#if SCI_UART_CFG_FIFO_SUPPORT + + /* Check if the channel supports fifo */ + if (BSP_FEATURE_SCI_UART_FIFO_CHANNELS & (1U << p_cfg->channel)) + { + p_instance_ctrl->fifo_depth = BSP_FEATURE_SCI_UART_FIFO_DEPTH; + } +#endif + + p_instance_ctrl->p_cfg = p_cfg; + + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + sci_uart_extended_cfg_t * p_extend = (sci_uart_extended_cfg_t *) p_cfg->p_extend; + + p_instance_ctrl->data_bytes = 1U; + if (UART_DATA_BITS_9 == p_cfg->data_bits) + { + p_instance_ctrl->data_bytes = 2U; + } + + /* Configure the interrupts. */ + r_sci_irqs_cfg(p_instance_ctrl, p_cfg); + + /* Enable the SCI channel and reset the registers to their initial state. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET); + R_BSP_MODULE_START(FSP_IP_SCI, p_cfg->channel); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET); + + if (p_cfg->channel != BSP_FEATURE_SCI_SAFETY_CHANNEL) + { + /* Non-Safety Peripheral */ + p_instance_ctrl->p_reg = + (R_SCI0_Type *) ((uint32_t) R_SCI0 + (p_cfg->channel * ((uint32_t) R_SCI1 - (uint32_t) R_SCI0))); + } + else + { + /* Safety Peripheral */ + p_instance_ctrl->p_reg = (R_SCI0_Type *) BSP_FEATURE_SCI_SAFETY_CHANNEL_BASE_ADDRESS; + } + +#if SCI_UART_CFG_DMAC_SUPPORTED + + /* Configure the transfer interface for transmission and reception if provided. */ + fsp_err_t err = r_sci_uart_transfer_open(p_instance_ctrl, p_cfg); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + p_instance_ctrl->p_reg->CCR0 = SCI_UART_CCR0_DEFAULT_VALUE; + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.RE, 0); + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.TE, 0); + p_instance_ctrl->p_reg->CCR1 = SCI_UART_CCR1_DEFAULT_VALUE; + p_instance_ctrl->p_reg->CCR2 = SCI_UART_CCR2_DEFAULT_VALUE; + p_instance_ctrl->p_reg->CCR3 = SCI_UART_CCR3_DEFAULT_VALUE; + p_instance_ctrl->p_reg->CCR4 = SCI_UART_CCR4_DEFAULT_VALUE; + + /* Set the UART configuration settings provided in ::uart_cfg_t and ::sci_uart_extended_cfg_t. */ + r_sci_uart_config_set(p_instance_ctrl, p_cfg); + + p_instance_ctrl->p_reg->CFCLR = SCI_UART_CFCLR_ALL_FLAG_CLEAR; + +#if SCI_UART_CFG_FIFO_SUPPORT + p_instance_ctrl->p_reg->FFCLR = SCI_UART_FFCLR_ALL_FLAG_CLEAR; +#endif + + p_instance_ctrl->p_tx_src = NULL; + p_instance_ctrl->tx_src_bytes = 0U; + p_instance_ctrl->p_rx_dest = NULL; + p_instance_ctrl->rx_dest_bytes = 0; + + uint32_t ccr0 = SCI_UART_CCR0_IDSEL_MASK; +#if (SCI_UART_CFG_RX_ENABLE) + + /* If reception is enabled at build time, enable reception. */ + /* NOTE: Transmitter and its interrupt are enabled in R_SCI_UART_Write(). */ + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->rxi_irq); + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->eri_irq); + + ccr0 |= (SCI_UART_CCR0_RIE_MASK | SCI_UART_CCR0_RE_MASK); +#endif + +#if (SCI_UART_CFG_TX_ENABLE) + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->txi_irq); + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->tei_irq); + + ccr0 |= SCI_UART_CCR0_TE_MASK; +#endif + p_instance_ctrl->p_reg->CCR0 = ccr0; + + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.RE, 1); + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.TE, 1); + + /* Set flow control pins. */ + p_instance_ctrl->flow_pin = p_extend->flow_control_pin; + +#if SCI_UART_CFG_FLOW_CONTROL_SUPPORT + if (p_instance_ctrl->flow_pin != (bsp_io_port_pin_t) SCI_UART_INVALID_16BIT_PARAM) + { + R_BSP_PinAccessEnable(); + R_BSP_PinClear(R_BSP_IoRegionGet(p_instance_ctrl->flow_pin), p_instance_ctrl->flow_pin); + R_BSP_PinAccessDisable(); + } +#endif + + p_instance_ctrl->open = SCI_UART_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Aborts any in progress transfers. Disables interrupts, receiver, and transmitter. Closes lower level transfer + * drivers if used. Removes power. Implements @ref uart_api_t::close + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_Close (uart_ctrl_t * const p_ctrl) +{ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Mark the channel not open so other APIs cannot use it. */ + p_instance_ctrl->open = 0U; + + /* Disable interrupts, receiver, and transmitter. Disable baud clock output.*/ + p_instance_ctrl->p_reg->CCR0 = SCI_UART_CCR0_DEFAULT_VALUE; + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.RE, 0); + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.TE, 0); + p_instance_ctrl->p_reg->CCR3 &= ~(SCI_UART_CCR3_CKE_MASK); + +#if (SCI_UART_CFG_RX_ENABLE) + + /* If reception is enabled at build time, disable reception irqs. */ + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->rxi_irq); + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->eri_irq); +#endif +#if (SCI_UART_CFG_TX_ENABLE) + + /* If transmission is enabled at build time, disable transmission irqs. */ + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->txi_irq); + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->tei_irq); +#endif +#if SCI_UART_CFG_DMAC_SUPPORTED + + /* Close the lower level transfer instances. */ + r_sci_uart_transfer_close(p_instance_ctrl); +#endif + + /* Remove power to the channel. */ + /* Disable the clock to the SCI channel. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET); + R_BSP_MODULE_STOP(FSP_IP_SCI, p_instance_ctrl->p_cfg->channel); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Receives user specified number of bytes into destination buffer pointer. Implements @ref uart_api_t::read + * + * @retval FSP_SUCCESS Data reception successfully ends. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Destination address or data size is not valid for 9-bit mode. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A previous read operation is still in progress. + * @retval FSP_ERR_UNSUPPORTED SCI_UART_CFG_RX_ENABLE is set to 0 + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reconfigure + * + * @note If 9-bit data length is specified at R_SCI_UART_Open call, p_dest must be aligned 16-bit boundary. + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_Read (uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ +#if (SCI_UART_CFG_RX_ENABLE) + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + + #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + err = r_sci_read_write_param_check(p_instance_ctrl, p_dest, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_instance_ctrl->rx_dest_bytes, FSP_ERR_IN_USE); + #endif + + #if SCI_UART_CFG_DMAC_SUPPORTED + + /* Configure transfer instance to receive the requested number of bytes if transfer is used for reception. */ + if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx) + { + p_instance_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_dest = (void *) p_dest; + p_instance_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->length = bytes; + + /* Disable the corresponding IRQ when transferring using DMAC. */ + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->rxi_irq); + + err = p_instance_ctrl->p_cfg->p_transfer_rx->p_api->reconfigure(p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl, + p_instance_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + /* Save the destination address and size for use in rxi_isr. */ + p_instance_ctrl->p_rx_dest = p_dest; + p_instance_ctrl->rx_dest_bytes = bytes; + + return err; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Transmits user specified number of bytes from the source buffer pointer. Implements @ref uart_api_t::write + * + * @retval FSP_SUCCESS Data transmission finished successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Source address or data size is not valid for 9-bit mode. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A UART transmission is in progress + * @retval FSP_ERR_UNSUPPORTED SCI_UART_CFG_TX_ENABLE is set to 0 + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reconfigure + * + * @note If 9-bit data length is specified at R_SCI_UART_Open call, p_src must be aligned on a 16-bit boundary. + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_Write (uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes) +{ +#if (SCI_UART_CFG_TX_ENABLE) + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; + #if SCI_UART_CFG_PARAM_CHECKING_ENABLE || SCI_UART_CFG_DMAC_SUPPORTED + fsp_err_t err = FSP_SUCCESS; + #endif + + #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + err = r_sci_read_write_param_check(p_instance_ctrl, p_src, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_instance_ctrl->tx_src_bytes, FSP_ERR_IN_USE); + #endif + + /* Transmit interrupts must be disabled to start with. */ + p_instance_ctrl->p_reg->CCR0 &= (uint32_t) ~(SCI_UART_CCR0_TIE_MASK | SCI_UART_CCR0_TEIE_MASK); + + p_instance_ctrl->tx_src_bytes = bytes - p_instance_ctrl->data_bytes; + p_instance_ctrl->p_tx_src = p_src + p_instance_ctrl->data_bytes; + + #if SCI_UART_CFG_DMAC_SUPPORTED + + /* If a transfer instance is used for transmission, reset the transfer instance to transmit the requested + * data. */ + if ((NULL != p_instance_ctrl->p_cfg->p_transfer_tx) && p_instance_ctrl->tx_src_bytes) + { + uint32_t num_transfers = p_instance_ctrl->tx_src_bytes; + p_instance_ctrl->tx_src_bytes = 0U; + + p_instance_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src = (void const *) p_instance_ctrl->p_tx_src; + p_instance_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->length = num_transfers; + + /* Disable the corresponding IRQ when transferring using DMAC. */ + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->txi_irq); + + err = p_instance_ctrl->p_cfg->p_transfer_tx->p_api->reconfigure(p_instance_ctrl->p_cfg->p_transfer_tx->p_ctrl, + p_instance_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + /* Trigger a TXI interrupt. This triggers the transfer instance or a TXI interrupt if the transfer instance is + * not used. */ + p_instance_ctrl->p_reg->CCR0 |= SCI_UART_CCR0_TIE_MASK; + + /* The first byte is sent from this function to trigger the first TXI event. This + * method is used instead of setting TE and TIE at the same time as recommended in the hardware manual to avoid + * the one frame delay that occurs when the TE bit is set. */ + if (2U == p_instance_ctrl->data_bytes) + { + p_instance_ctrl->p_reg->TDR_b.TDAT = (*(uint16_t *) (p_src)) & SCI_UART_TDR_9BIT_MASK; + } + else + { + p_instance_ctrl->p_reg->TDR_b.TDAT = *(p_src); + } + + #if SCI_UART_CFG_FIFO_SUPPORT + + /* The behavior of the TDRE flag differs between when FIFO is used and not used. + * When using FIFO, clear the flag manually to detect the interrupt at the edge. */ + p_instance_ctrl->p_reg->CFCLR_b.TDREC = 1; + #endif + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements uart_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_CallbackSet (uart_ctrl_t * const p_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void const * const p_context, + uart_callback_args_t * const p_callback_memory) +{ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + p_instance_ctrl->p_callback = p_callback; + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the baud rate using the clock selected in Open. p_baud_setting is a pointer to a sci_baud_setting_t structure. + * Implements @ref uart_api_t::baudSet + * + * @warning This terminates any in-progress transmission. + * + * @retval FSP_SUCCESS Baud rate was successfully changed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL or the UART is not configured to use the + * internal clock. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_BaudSet (uart_ctrl_t * const p_ctrl, void const * const p_baud_setting) +{ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Verify that the On-Chip baud rate generator is currently selected. */ + FSP_ASSERT((p_instance_ctrl->p_reg->CCR3_b.CKE & 0x2) == 0U); +#endif + + /* Save CCR0 configurations except transmit interrupts. Resuming transmission after reconfiguring baud settings is + * not supported. */ + uint32_t preserved_ccr0 = p_instance_ctrl->p_reg->CCR0 & (uint32_t) ~(R_SCI0_CCR0_TIE_Msk | R_SCI0_CCR0_TEIE_Msk); + + /* Disables transmitter and receiver. This terminates any in-progress transmission. */ + p_instance_ctrl->p_reg->CCR0 = preserved_ccr0 & + (uint32_t) ~(R_SCI0_CCR0_TE_Msk | R_SCI0_CCR0_RE_Msk | R_SCI0_CCR0_RIE_Msk); + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.RE, 0); + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.TE, 0); + p_instance_ctrl->p_tx_src = NULL; + + /* Apply new baud rate register settings. */ + r_sci_uart_baud_set(p_instance_ctrl->p_reg, p_baud_setting); + + /* Restore all settings except transmit interrupts. */ + p_instance_ctrl->p_reg->CCR0 = preserved_ccr0; + FSP_HARDWARE_REGISTER_WAIT((p_instance_ctrl->p_reg->CCR0 & R_SCI0_CCR0_RE_Msk), + (preserved_ccr0 & R_SCI0_CCR0_RE_Msk)); + FSP_HARDWARE_REGISTER_WAIT((p_instance_ctrl->p_reg->CCR0 & R_SCI0_CCR0_TE_Msk), + (preserved_ccr0 & R_SCI0_CCR0_TE_Msk)); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the driver information, including the maximum number of bytes that can be received or transmitted at a time. + * Implements @ref uart_api_t::infoGet + * + * @retval FSP_SUCCESS Information stored in provided p_info. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_InfoGet (uart_ctrl_t * const p_ctrl, uart_info_t * const p_info) +{ +#if SCI_UART_CFG_PARAM_CHECKING_ENABLE || SCI_UART_CFG_DMAC_SUPPORTED + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_info); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_info->read_bytes_max = SCI_UART_MAX_READ_WRITE_NO_DMAC; + p_info->write_bytes_max = SCI_UART_MAX_READ_WRITE_NO_DMAC; + +#if (SCI_UART_CFG_RX_ENABLE) + + /* Store number of bytes that can be read at a time. */ + #if SCI_UART_CFG_DMAC_SUPPORTED + if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx) + { + p_info->read_bytes_max = SCI_UART_DMAC_MAX_TRANSFER; + } + #endif +#endif + +#if (SCI_UART_CFG_TX_ENABLE) + + /* Store number of bytes that can be written at a time. */ + #if SCI_UART_CFG_DMAC_SUPPORTED + if (NULL != p_instance_ctrl->p_cfg->p_transfer_tx) + { + p_info->write_bytes_max = SCI_UART_DMAC_MAX_TRANSFER; + } + #endif +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing transfer. Transmission is aborted after the current character is transmitted. + * Reception is still enabled after abort(). Any characters received after abort() and before the transfer + * is reset in the next call to read(), will arrive via the callback function with event UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::communicationAbort + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_Abort (uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort) +{ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_ERR_UNSUPPORTED; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if (SCI_UART_CFG_TX_ENABLE) + if (UART_DIR_TX & communication_to_abort) + { + err = FSP_SUCCESS; + p_instance_ctrl->p_reg->CCR0 &= (uint32_t) ~(SCI_UART_CCR0_TIE_MASK | SCI_UART_CCR0_TEIE_MASK); + + /* Make sure no transmission is in progress. */ + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CSR_b.TEND, 1U); + + #if SCI_UART_CFG_DMAC_SUPPORTED + if (NULL != p_instance_ctrl->p_cfg->p_transfer_tx) + { + err = p_instance_ctrl->p_cfg->p_transfer_tx->p_api->disable(p_instance_ctrl->p_cfg->p_transfer_tx->p_ctrl); + + /* Now that the transfer using DMAC is finished, enable the corresponding IRQ. */ + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->txi_irq); + } + #endif + + #if SCI_UART_CFG_FIFO_SUPPORT + if (0U != p_instance_ctrl->fifo_depth) + { + /* Reset the transmit fifo */ + p_instance_ctrl->p_reg->FCR_b.TFRST = 1U; + } + #endif + p_instance_ctrl->tx_src_bytes = 0U; + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } +#endif +#if (SCI_UART_CFG_RX_ENABLE) + if (UART_DIR_RX & communication_to_abort) + { + err = FSP_SUCCESS; + + p_instance_ctrl->rx_dest_bytes = 0U; + + #if SCI_UART_CFG_DMAC_SUPPORTED + if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx) + { + err = p_instance_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl); + + /* Now that the transfer using DMAC is finished, enable the corresponding IRQ. */ + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->rxi_irq); + } + #endif + + #if SCI_UART_CFG_FIFO_SUPPORT + if (0U != p_instance_ctrl->fifo_depth) + { + /* Reset the receive fifo */ + p_instance_ctrl->p_reg->FCR_b.RFRST = 1U; + } + #endif + } +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing read. Reception is still enabled after abort(). Any characters received after abort() + * and before the transfer is reset in the next call to read(), will arrive via the callback function with event + * UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::readStop + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block or remaining_bytes is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_ReadStop (uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes) +{ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(remaining_bytes); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if (SCI_UART_CFG_RX_ENABLE) + *remaining_bytes = p_instance_ctrl->rx_dest_bytes; + p_instance_ctrl->rx_dest_bytes = 0U; + #if SCI_UART_CFG_DMAC_SUPPORTED + if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx) + { + fsp_err_t err = p_instance_ctrl->p_cfg->p_transfer_rx->p_api->disable( + p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Now that the transfer using DMAC is finished, enable the corresponding IRQ. */ + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->rxi_irq); + + transfer_properties_t transfer_info; + err = p_instance_ctrl->p_cfg->p_transfer_rx->p_api->infoGet(p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl, + &transfer_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + *remaining_bytes = transfer_info.transfer_length_remaining; + } + #endif + #if SCI_UART_CFG_FIFO_SUPPORT + if (0U != p_instance_ctrl->fifo_depth) + { + /* Reset the receive fifo */ + p_instance_ctrl->p_reg->FCR_b.RFRST = 1U; + } + #endif +#else + + return FSP_ERR_UNSUPPORTED; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Calculates baud rate register settings. Evaluates and determines the best possible settings set to the baud rate + * related registers. + * + * @param[in] p_baud_target Baudrate calculation configuration. + * @param[in] clock_source Clock source (PCLKM or SCInASYNCCLK) used for baudrate calculation. + * @param[out] p_baud_setting Baud setting information stored here if successful + * + * @retval FSP_SUCCESS Baud rate is set successfully + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_INVALID_ARGUMENT Baud rate is '0', error in calculated baud rate is larger than requested + * max error, or requested max error in baud rate is larger than 15%. + * Clock source frequency could not be get. + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_BaudCalculate (sci_uart_baud_calculation_t const * const p_baud_target, + sci_uart_clock_source_t clock_source, + sci_baud_setting_t * const p_baud_setting) +{ +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_baud_target); + FSP_ASSERT(p_baud_setting); + FSP_ERROR_RETURN(SCI_UART_MAX_BAUD_RATE_ERROR_X_1000 >= p_baud_target->baud_rate_error_x_1000, + FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((0U != p_baud_target->baudrate), FSP_ERR_INVALID_ARGUMENT); +#endif + + p_baud_setting->baudrate_bits_b.brr = SCI_UART_BRR_MAX; + p_baud_setting->baudrate_bits_b.brme = 0U; + p_baud_setting->baudrate_bits_b.mddr = SCI_UART_MDDR_MIN; + + /* Find the best BRR (bit rate register) value. + * In table g_async_baud, divisor values are stored for BGDM, ABCS, ABCSE and N values. Each set of divisors + * is tried, and the settings with the lowest bit rate error are stored. The formula to calculate BRR is as + * follows and it must be 255 or less: + * BRR = (PCLK / (div_coefficient * baud)) - 1 + */ + int32_t hit_bit_err = SCI_UART_100_PERCENT_X_1000; + uint32_t hit_mddr = 0U; + uint32_t divisor = 0U; + + uint32_t freq_hz = 0U; + if (SCI_UART_CLOCK_SOURCE_PCLKM == clock_source) + { + freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKM); + } + else + { + freq_hz = + R_FSP_SystemClockHzGet((fsp_priv_clock_t) ((uint8_t) FSP_PRIV_CLOCK_PCLKSCI0 + (uint8_t) clock_source)); + } + + FSP_ERROR_RETURN(0U != freq_hz, FSP_ERR_INVALID_ARGUMENT); + + for (uint32_t select_16_base_clk_cycles = 0U; + select_16_base_clk_cycles <= 1U && (hit_bit_err > ((int32_t) p_baud_target->baud_rate_error_x_1000)); + select_16_base_clk_cycles++) + { + for (uint32_t i = 0U; i < SCI_UART_NUM_DIVISORS_ASYNC; i++) + { + /* if select_16_base_clk_cycles == true: Skip this calculation for divisors that are not acheivable with 16 base clk cycles per bit. + * if select_16_base_clk_cycles == false: Skip this calculation for divisors that are only acheivable without 16 base clk cycles per bit. + */ + if (((uint8_t) select_16_base_clk_cycles) ^ (g_async_baud[i].abcs | g_async_baud[i].abcse)) + { + continue; + } + + divisor = (uint32_t) g_div_coefficient[i] * p_baud_target->baudrate; + uint32_t temp_brr = freq_hz / divisor; + + if (temp_brr <= (SCI_UART_BRR_MAX + 1U)) + { + while (temp_brr > 0U) + { + temp_brr -= 1U; + + /* Calculate the bit rate error. The formula is as follows: + * bit rate error[%] = {(PCLK / (baud * div_coefficient * (BRR + 1)) - 1} x 100 + * calculates bit rate error[%] to three decimal places + */ + int32_t err_divisor = (int32_t) (divisor * (temp_brr + 1U)); + + /* Promoting to 64 bits for calculation, but the final value can never be more than 32 bits, as + * described below, so this cast is safe. + * 1. (temp_brr + 1) can be off by an upper limit of 1 due to rounding from the calculation: + * freq_hz / divisor, or: + * freq_hz / divisor <= (temp_brr + 1) < (freq_hz / divisor) + 1 + * 2. Solving for err_divisor: + * freq_hz <= err_divisor < freq_hz + divisor + * 3. Solving for bit_err: + * 0 >= bit_err >= (freq_hz * 100000 / (freq_hz + divisor)) - 100000 + * 4. freq_hz >= divisor (or temp_brr would be -1 and we would never enter this while loop), so: + * 0 >= bit_err >= 100000 / freq_hz - 100000 + * 5. Larger frequencies yield larger bit errors (absolute value). As the frequency grows, + * the bit_err approaches -100000, so: + * 0 >= bit_err >= -100000 + * 6. bit_err is between -100000 and 0. This entire range fits in an int32_t type, so the cast + * to (int32_t) is safe. + */ + int32_t bit_err = (int32_t) (((((int64_t) freq_hz) * SCI_UART_100_PERCENT_X_1000) / + err_divisor) - SCI_UART_100_PERCENT_X_1000); + + uint32_t mddr = 0U; + if (p_baud_target->bitrate_modulation) + { + /* Calculate the MDDR (M) value if bit rate modulation is enabled, + * The formula to calculate MBBR (from the M and N relationship given in the hardware manual) is as follows + * and it must be between 128 and 256. + * MDDR = ((div_coefficient * baud * 256) * (BRR + 1)) / PCLK */ + mddr = (uint32_t) err_divisor / (freq_hz / SCI_UART_MDDR_MAX); + + /* The maximum value that could result from the calculation above is 256, which is a valid MDDR + * value, so only the lower bound is checked. */ + if (mddr < SCI_UART_MDDR_MIN) + { + break; + } + + /* Adjust bit rate error for bit rate modulation. The following formula is used: + * bit rate error [%] = ((bit rate error [%, no modulation] + 100) * MDDR / 256) - 100 + */ + bit_err = (((bit_err + SCI_UART_100_PERCENT_X_1000) * (int32_t) mddr) / + SCI_UART_MDDR_DIVISOR) - SCI_UART_100_PERCENT_X_1000; + } + + /* Take the absolute value of the bit rate error. */ + if (bit_err < 0) + { + bit_err = -bit_err; + } + + /* If the absolute value of the bit rate error is less than the previous lowest absolute value of + * bit rate error, then store these settings as the best value. + */ + if (bit_err < hit_bit_err) + { + p_baud_setting->baudrate_bits_b.bgdm = g_async_baud[i].bgdm; + p_baud_setting->baudrate_bits_b.abcs = g_async_baud[i].abcs; + p_baud_setting->baudrate_bits_b.abcse = g_async_baud[i].abcse; + p_baud_setting->baudrate_bits_b.cks = g_async_baud[i].cks; + p_baud_setting->baudrate_bits_b.brr = (uint8_t) temp_brr; + hit_bit_err = bit_err; + hit_mddr = mddr; + } + + if (p_baud_target->bitrate_modulation) + { + p_baud_setting->baudrate_bits_b.brme = 1U; + p_baud_setting->baudrate_bits_b.mddr = (uint8_t) hit_mddr; + } + else + { + break; + } + } + } + } + } + + /* Return an error if the percent error is larger than the maximum percent error allowed for this instance */ + FSP_ERROR_RETURN((hit_bit_err <= (int32_t) p_baud_target->baud_rate_error_x_1000), FSP_ERR_INVALID_ARGUMENT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SCI_UART) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * Parameter error check function for read/write. + * + * @param[in] p_instance_ctrl Pointer to the control block for the channel + * @param[in] addr Pointer to the buffer + * @param[in] bytes Number of bytes to read or write + * + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL + * @retval FSP_ERR_INVALID_ARGUMENT Address is not aligned to 2-byte boundary or size is the odd number when the data + * length is 9-bit + **********************************************************************************************************************/ +static fsp_err_t r_sci_read_write_param_check (sci_uart_instance_ctrl_t const * const p_instance_ctrl, + uint8_t const * const addr, + uint32_t const bytes) +{ + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(addr); + FSP_ASSERT(0U != bytes); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + if (2U == p_instance_ctrl->data_bytes) + { + /* Do not allow odd buffer address if data length is 9 bits. */ + FSP_ERROR_RETURN((0U == ((uint32_t) addr & SCI_UART_ALIGN_2_BYTES)), FSP_ERR_INVALID_ARGUMENT); + + /* Do not allow odd number of data bytes if data length is 9 bits. */ + FSP_ERROR_RETURN(0U == (bytes % 2U), FSP_ERR_INVALID_ARGUMENT); + } + + return FSP_SUCCESS; +} + +#endif + +#if SCI_UART_CFG_DMAC_SUPPORTED + +/*******************************************************************************************************************//** + * Subroutine to apply common UART transfer settings. + * + * @param[in] p_cfg Pointer to UART specific configuration structure + * @param[in] p_transfer Pointer to transfer instance to configure + * + * @retval FSP_SUCCESS UART transfer drivers successfully configured + * @retval FSP_ERR_ASSERTION Invalid pointer + **********************************************************************************************************************/ +static fsp_err_t r_sci_uart_transfer_configure (sci_uart_instance_ctrl_t * const p_instance_ctrl, + transfer_instance_t const * p_transfer, + uint32_t * p_transfer_reg, + uint32_t sci_buffer_address) +{ + /* Configure the transfer instance, if enabled. */ + #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_transfer->p_api); + FSP_ASSERT(NULL != p_transfer->p_ctrl); + FSP_ASSERT(NULL != p_transfer->p_cfg); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_info); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_extend); + #endif + + /* Casting for compatibility with 7 or 8 bit mode. */ + *p_transfer_reg = sci_buffer_address; + + transfer_info_t * p_info = p_transfer->p_cfg->p_info; + if (UART_DATA_BITS_9 == p_instance_ctrl->p_cfg->data_bits) + { + p_info->src_size = TRANSFER_SIZE_2_BYTE; + p_info->dest_size = TRANSFER_SIZE_2_BYTE; + } + else + { + p_info->src_size = TRANSFER_SIZE_1_BYTE; + p_info->dest_size = TRANSFER_SIZE_1_BYTE; + } + + fsp_err_t err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +#endif + +#if SCI_UART_CFG_DMAC_SUPPORTED + +/*******************************************************************************************************************//** + * Configures UART related transfer drivers (if enabled). + * + * @param[in] p_instance_ctrl Pointer to UART control structure + * @param[in] p_cfg Pointer to UART specific configuration structure + * + * @retval FSP_SUCCESS UART transfer drivers successfully configured + * @retval FSP_ERR_ASSERTION Invalid pointer or required interrupt not enabled in vector table + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +static fsp_err_t r_sci_uart_transfer_open (sci_uart_instance_ctrl_t * const p_instance_ctrl, + uart_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + #if (SCI_UART_CFG_RX_ENABLE) + + /* If a transfer instance is used for reception, apply UART specific settings and open the transfer instance. */ + if (NULL != p_cfg->p_transfer_rx) + { + transfer_info_t * p_info = p_cfg->p_transfer_rx->p_cfg->p_info; + + p_info->mode = TRANSFER_MODE_NORMAL; + p_info->src_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_info->dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + + err = + r_sci_uart_transfer_configure(p_instance_ctrl, + p_cfg->p_transfer_rx, + (uint32_t *) &p_info->p_src, + (uint32_t) &(p_instance_ctrl->p_reg->RDR)); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + #if (SCI_UART_CFG_TX_ENABLE) + + /* If a transfer instance is used for transmission, apply UART specific settings and open the transfer instance. */ + if (NULL != p_cfg->p_transfer_tx) + { + transfer_info_t * p_info = p_cfg->p_transfer_tx->p_cfg->p_info; + + p_info->mode = TRANSFER_MODE_NORMAL; + p_info->src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + p_info->dest_addr_mode = TRANSFER_ADDR_MODE_FIXED; + + err = + r_sci_uart_transfer_configure(p_instance_ctrl, + p_cfg->p_transfer_tx, + (uint32_t *) &p_info->p_dest, + (uint32_t) &p_instance_ctrl->p_reg->TDR); + + #if (SCI_UART_CFG_RX_ENABLE) + if ((err != FSP_SUCCESS) && (NULL != p_cfg->p_transfer_rx)) + { + p_cfg->p_transfer_rx->p_api->close(p_cfg->p_transfer_rx->p_ctrl); + } + #endif + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + return err; +} + +#endif + +/*******************************************************************************************************************//** + * Configures UART related registers based on user configurations. + * + * @param[in] p_instance_ctrl Pointer to UART control structure + * @param[in] p_cfg Pointer to UART specific configuration structure + **********************************************************************************************************************/ +static void r_sci_uart_config_set (sci_uart_instance_ctrl_t * const p_instance_ctrl, uart_cfg_t const * const p_cfg) +{ + /* CCR3 register setting. */ + uint32_t ccr3 = SCI_UART_CCR3_DEFAULT_VALUE; + +#if SCI_UART_CFG_FIFO_SUPPORT + ccr3 |= (1U << SCI_UART_CCR3_FM_OFFSET); + + /* Configure FIFO related registers. */ + r_sci_uart_fifo_cfg(p_instance_ctrl); +#else + + /* If fifo support is disabled and the current channel supports fifo make sure it's disabled. */ + if (BSP_FEATURE_SCI_UART_FIFO_CHANNELS & (1U << p_cfg->channel)) + { + p_instance_ctrl->p_reg->FCR = SCI_UART_FCR_DEFAULT_VALUE; + } +#endif + + /* Configure data size. */ + if (UART_DATA_BITS_7 == p_cfg->data_bits) + { + ccr3 |= (1U << SCI_UART_CCR3_CHR_OFFSET); + } + else if (UART_DATA_BITS_9 == p_cfg->data_bits) + { + ccr3 &= ~(1U << (SCI_UART_CCR3_CHR_OFFSET + 1)); + } + else + { + /* Do nothing. Default is 8-bit mode. */ + } + + /* Configure stop bits. */ + ccr3 |= (uint32_t) p_cfg->stop_bits << SCI_UART_CCR3_STP_OFFSET; + + /* Configure CKE bits. */ + sci_uart_extended_cfg_t * p_extend = (sci_uart_extended_cfg_t *) p_cfg->p_extend; + ccr3 |= (p_extend->clock & SCI_UART_CCR3_CKE_VALUE_MASK) << SCI_UART_CCR3_CKE_OFFSET; + + /* Starts reception on falling edge of RXD if enabled in extension (otherwise reception starts at low level + * of RXD). */ + ccr3 |= (p_extend->rx_edge_start & 1U) << SCI_UART_CCR3_RxDSEL_OFFSET; + + ccr3 |= ((uint32_t) p_extend->rs485_setting.enable << R_SCI0_CCR3_DEN_Pos) & R_SCI0_CCR3_DEN_Msk; + + /* Configure SPEN bit. */ + if (SCI_UART_CLOCK_SOURCE_PCLKM == p_extend->clock_source) + { + ccr3 |= 1U << SCI_UART_CCR3_BPEN_OFFSET; + } + + /* Write to the CCR3 register. */ + p_instance_ctrl->p_reg->CCR3 = ccr3; + + /* CCR1 register setting. */ + uint32_t ccr1 = SCI_UART_CCR1_DEFAULT_VALUE; + + /* Configure flow control pin. */ + ccr1 |= ((uint32_t) (p_extend->flow_control << R_SCI0_CCR1_CTSE_Pos) & SCI_UART_CCR1_FLOW_CTSRTS_MASK); + + /* Set the default level of the TX pin to 1. */ + ccr1 |= (uint32_t) (1U << SCI_UART_CCR1_SPB2DT_BIT | SCI_UART_CCR1_OUTPUT_ENABLE_MASK); + + /* Configure parity bits. */ + if (0 != p_cfg->parity) + { + ccr1 |= + (((UART_PARITY_EVEN == + p_cfg->parity) ? 1U : 3U) << SCI_UART_CCR1_PARITY_OFFSET) & SCI_UART_CCR1_PARITY_MASK; + } + + if (SCI_UART_NOISE_CANCELLATION_DISABLE != p_extend->noise_cancel) + { + /* Select noise filter clock */ + ccr1 |= (uint32_t) (((p_extend->noise_cancel & 0x07U) - 1) & SCI_UART_CCR1_NFCS_VALUE_MASK) << + SCI_UART_CCR1_NFCS_OFFSET; + + /* Enables the noise cancellation */ + ccr1 |= (uint32_t) 1 << SCI_UART_CCR1_NFEN_OFFSET; + } + + p_instance_ctrl->p_reg->CCR1 = ccr1; + + if ((SCI_UART_CLOCK_EXT8X == p_extend->clock) || (SCI_UART_CLOCK_EXT16X == p_extend->clock)) + { + /* Use external clock for baud rate */ + p_instance_ctrl->p_reg->CCR2_b.BRR = SCI_UART_BRR_DEFAULT_VALUE; + + if (SCI_UART_CLOCK_EXT8X == p_extend->clock) + { + /* Set baud rate as (external clock / 8) */ + p_instance_ctrl->p_reg->CCR2 |= 1U << SCI_UART_CCR2_ABCS_OFFSET; + } + } + else + { + /* Set the baud rate settings for the internal baud rate generator. */ + r_sci_uart_baud_set(p_instance_ctrl->p_reg, p_extend->p_baud_setting); + } + + /* Configure RS-485 DE assertion settings. */ + uint32_t dcr = ((uint32_t) (p_extend->rs485_setting.polarity << R_SCI0_DCR_DEPOL_Pos)) & R_SCI0_DCR_DEPOL_Msk; + dcr |= ((uint32_t) p_extend->rs485_setting.assertion_time << R_SCI0_DCR_DEAST_Pos) & + R_SCI0_DCR_DEAST_Msk; + dcr |= ((uint32_t) p_extend->rs485_setting.negation_time << R_SCI0_DCR_DENGT_Pos) & + R_SCI0_DCR_DENGT_Msk; + p_instance_ctrl->p_reg->DCR = dcr; +} + +#if SCI_UART_CFG_FIFO_SUPPORT + +/*******************************************************************************************************************//** + * Resets FIFO related registers. + * + * @param[in] p_instance_ctrl Pointer to UART instance control + * @param[in] p_cfg Pointer to UART configuration structure + **********************************************************************************************************************/ +static void r_sci_uart_fifo_cfg (sci_uart_instance_ctrl_t * const p_instance_ctrl) +{ + if (0U != p_instance_ctrl->fifo_depth) + { + /* Set the tx and rx reset bits */ + uint32_t fcr = 0U; + + #if (SCI_UART_CFG_TX_ENABLE) + #if SCI_UART_CFG_DMAC_SUPPORTED + if (NULL != p_instance_ctrl->p_cfg->p_transfer_tx) + { + /* When DMAC transfer is used, set TTRG[4:0] = 0x0F. */ + fcr |= SCI_UART_FCR_TTRG_DMAC_VALUE << SCI_UART_FCR_TTRG_OFFSET; + } + #endif + #endif + + #if (SCI_UART_CFG_RX_ENABLE) + #if SCI_UART_CFG_DMAC_SUPPORTED + + /* If DMAC is used keep the receive trigger at the default level of 0. */ + if (NULL == p_instance_ctrl->p_cfg->p_transfer_rx) + #endif + { + /* Otherwise, set receive trigger number as configured by the user. */ + sci_uart_extended_cfg_t const * p_extend = p_instance_ctrl->p_cfg->p_extend; + + /* RTRG(Receive FIFO Data Trigger Number) controls when the RXI interrupt will be generated. If data is + * received but the trigger number is not met the RXI interrupt will be generated after 15 ETUs from + * the last stop bit in asynchronous mode. */ + fcr |= (((p_instance_ctrl->fifo_depth - 1U) & p_extend->rx_fifo_trigger) & SCI_UART_FCR_TRIGGER_MASK) << + SCI_UART_FCR_RTRG_OFFSET; + } + + /* RTS asserts when the amount of received data stored in the fifo is equal or less than this value. */ + fcr |= ((p_instance_ctrl->fifo_depth - 1U) & SCI_UART_FCR_TRIGGER_MASK) << SCI_UART_FCR_RSTRG_OFFSET; + #endif + + /* Set the FCR and reset the fifos. */ + p_instance_ctrl->p_reg->FCR = (uint32_t) (fcr | SCI_UART_FCR_RESET_TX_RX); + } +} + +#endif + +/*******************************************************************************************************************//** + * Sets interrupt priority and initializes vector info. + * + * @param[in] p_instance_ctrl Pointer to driver control block + * @param[in] ipl Interrupt priority level + * @param[in] irq IRQ number for this interrupt + **********************************************************************************************************************/ +static void r_sci_irq_cfg (sci_uart_instance_ctrl_t * const p_instance_ctrl, uint8_t const ipl, IRQn_Type const irq) +{ + /* Disable interrupts, set priority, and store control block in the vector information so it can be accessed + * from the callback. */ + R_BSP_IrqDisable(irq); + + R_BSP_IrqCfg(irq, ipl, p_instance_ctrl); +} + +/*******************************************************************************************************************//** + * Sets interrupt priority and initializes vector info for all interrupts. + * + * @param[in] p_instance_ctrl Pointer to UART instance control block + * @param[in] p_cfg Pointer to UART specific configuration structure + **********************************************************************************************************************/ +static void r_sci_irqs_cfg (sci_uart_instance_ctrl_t * const p_instance_ctrl, uart_cfg_t const * const p_cfg) +{ +#if (SCI_UART_CFG_RX_ENABLE) + + /* ERI is optional. */ + r_sci_irq_cfg(p_instance_ctrl, p_cfg->eri_ipl, p_cfg->eri_irq); + r_sci_irq_cfg(p_instance_ctrl, p_cfg->rxi_ipl, p_cfg->rxi_irq); +#endif +#if (SCI_UART_CFG_TX_ENABLE) + r_sci_irq_cfg(p_instance_ctrl, p_cfg->txi_ipl, p_cfg->txi_irq); + + r_sci_irq_cfg(p_instance_ctrl, p_cfg->tei_ipl, p_cfg->tei_irq); +#endif +} + +#if SCI_UART_CFG_DMAC_SUPPORTED + +/*******************************************************************************************************************//** + * Closes transfer interfaces. + * + * @param[in] p_instance_ctrl Pointer to UART instance control block + **********************************************************************************************************************/ +static void r_sci_uart_transfer_close (sci_uart_instance_ctrl_t * p_instance_ctrl) +{ + #if (SCI_UART_CFG_RX_ENABLE) + if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx) + { + p_instance_ctrl->p_cfg->p_transfer_rx->p_api->close(p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + #endif + #if (SCI_UART_CFG_TX_ENABLE) + if (NULL != p_instance_ctrl->p_cfg->p_transfer_tx) + { + p_instance_ctrl->p_cfg->p_transfer_tx->p_api->close(p_instance_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Changes baud rate based on predetermined register settings. + * + * @param[in] p_sci_reg Base pointer for SCI registers + * @param[in] p_baud_setting Pointer to other divisor related settings + * + * @note The transmitter and receiver (TE and RE bits in SCR) must be disabled prior to calling this function. + **********************************************************************************************************************/ +static void r_sci_uart_baud_set (R_SCI0_Type * p_sci_reg, sci_baud_setting_t const * const p_baud_setting) +{ + p_sci_reg->CCR2 = (uint32_t) ((p_sci_reg->CCR2 & ~(SCI_UART_CCR2_BAUD_SETTING_MASK)) | + (p_baud_setting->baudrate_bits & SCI_UART_CCR2_BAUD_SETTING_MASK)); +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_instance_ctrl Pointer to UART instance control block + * @param[in] data See uart_callback_args_t in r_uart_api.h + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_sci_uart_call_callback (sci_uart_instance_ctrl_t * p_instance_ctrl, uint32_t data, uart_event_t event) +{ + uart_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. */ + uart_callback_args_t * p_args = p_instance_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_instance_ctrl->p_cfg->channel; + p_args->data = data; + p_args->event = event; + p_args->p_context = p_instance_ctrl->p_context; + + p_instance_ctrl->p_callback(p_args); + + if (NULL != p_instance_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = args; + } +} + +#if (SCI_UART_CFG_TX_ENABLE) + +/*******************************************************************************************************************//** + * Common processing for TXI interrupt and DMA transfer completion interrupt in UART write mode. This function writes + * the next data. After the last data byte is written, this function disables the TXI interrupt and enables the TEI + * (transmit end) interrupt. + **********************************************************************************************************************/ +static void sci_uart_txi_common (sci_uart_instance_ctrl_t * p_instance_ctrl) +{ + if ((NULL == p_instance_ctrl->p_cfg->p_transfer_tx) && (0U != p_instance_ctrl->tx_src_bytes)) + { + if (2U == p_instance_ctrl->data_bytes) + { + p_instance_ctrl->p_reg->TDR_b.TDAT = (*(uint16_t *) (p_instance_ctrl->p_tx_src)) & SCI_UART_TDR_9BIT_MASK; + } + else + { + p_instance_ctrl->p_reg->TDR_b.TDAT = *(p_instance_ctrl->p_tx_src); + } + + /* Update pointer to the next data and number of remaining bytes in the control block. */ + p_instance_ctrl->tx_src_bytes -= p_instance_ctrl->data_bytes; + p_instance_ctrl->p_tx_src += p_instance_ctrl->data_bytes; + + /* If transfer is not used, write data until FIFO is full. */ + #if SCI_UART_CFG_FIFO_SUPPORT + if (0U != p_instance_ctrl->fifo_depth) + { + uint32_t fifo_count = p_instance_ctrl->p_reg->FTSR_b.T; + for (uint32_t cnt = fifo_count; (cnt < p_instance_ctrl->fifo_depth) && p_instance_ctrl->tx_src_bytes; cnt++) + { + if (2U == p_instance_ctrl->data_bytes) + { + p_instance_ctrl->p_reg->TDR_b.TDAT = (*(uint16_t *) (p_instance_ctrl->p_tx_src)) & + SCI_UART_TDR_9BIT_MASK; + } + else + { + p_instance_ctrl->p_reg->TDR_b.TDAT = *(p_instance_ctrl->p_tx_src); + } + + p_instance_ctrl->tx_src_bytes -= p_instance_ctrl->data_bytes; + p_instance_ctrl->p_tx_src += p_instance_ctrl->data_bytes; + } + + /* Clear TDRE flag */ + p_instance_ctrl->p_reg->CFCLR_b.TDREC = 1; + } + #endif + } + + if (0U == p_instance_ctrl->tx_src_bytes) + { + /* After all data has been transmitted, disable transmit interrupts and enable the transmit end interrupt. */ + uint32_t ccr0_temp = p_instance_ctrl->p_reg->CCR0; + ccr0_temp |= SCI_UART_CCR0_TEIE_MASK; + ccr0_temp &= (uint32_t) ~SCI_UART_CCR0_TIE_MASK; + p_instance_ctrl->p_reg->CCR0 = ccr0_temp; + + p_instance_ctrl->p_tx_src = NULL; + r_sci_uart_call_callback(p_instance_ctrl, 0U, UART_EVENT_TX_DATA_EMPTY); + } +} + +/*******************************************************************************************************************//** + * TXI interrupt handler for UART mode. TXI interrupt fires when the data in the data register or FIFO register has been + * transferred to the data shift register, and the next data can be written. This function calls sci_uart_txi_common(). + **********************************************************************************************************************/ +void sci_uart_txi_isr (void) +{ + SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE; + + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + sci_uart_txi_common(p_instance_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; + + SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE; +} + +/*******************************************************************************************************************//** + * Callback that must be called after a TX DMAC transfer completes. + * + * @param[in] p_instance_ctrl Pointer to SCI_UART instance control block + **********************************************************************************************************************/ +void sci_uart_tx_dmac_callback (sci_uart_instance_ctrl_t * p_instance_ctrl) +{ + SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE; + + /* Now that the transfer using DMAC is finished, enable the corresponding IRQ. */ + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->txi_irq); + + sci_uart_txi_common(p_instance_ctrl); + + SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE; +} + +#endif + +#if (SCI_UART_CFG_RX_ENABLE) + +/*******************************************************************************************************************//** + * Common processing for RXI interrupt and DMA transfer completion interrupt in UART read mode. This function calls + * callback function when it meets conditions below. + * - UART_EVENT_RX_COMPLETE: The number of data which has been read reaches to the number specified in R_SCI_UART_Read() + * if a transfer instance is used for reception. + * - UART_EVENT_RX_CHAR: Data is received asynchronously (read has not been called) + * + * This function also calls the callback function for RTS pin control if it is registered in R_SCI_UART_Open(). This is + * special functionality to expand SCI hardware capability and make RTS/CTS hardware flow control possible. If macro + * 'SCI_UART_CFG_FLOW_CONTROL_SUPPORT' is set, it is called at the beginning in this function to set the RTS pin high, + * then it is called again just before leaving this function to set the RTS pin low. + * @retval none + **********************************************************************************************************************/ +static void sci_uart_rxi_common (sci_uart_instance_ctrl_t * p_instance_ctrl) +{ + #if SCI_UART_CFG_DMAC_SUPPORTED + if ((p_instance_ctrl->p_cfg->p_transfer_rx == NULL) || (0 == p_instance_ctrl->rx_dest_bytes)) + #endif + { + #if (SCI_UART_CFG_FLOW_CONTROL_SUPPORT) + if (p_instance_ctrl->flow_pin != (bsp_io_port_pin_t) SCI_UART_INVALID_16BIT_PARAM) + { + R_BSP_PinAccessEnable(); + + /* Pause the transmission of data from the other device. */ + R_BSP_PinSet(R_BSP_IoRegionGet(p_instance_ctrl->flow_pin), p_instance_ctrl->flow_pin); + } + #endif + + uint32_t data; + #if SCI_UART_CFG_FIFO_SUPPORT + do + { + if ((p_instance_ctrl->fifo_depth > 0U)) + { + if (p_instance_ctrl->p_reg->FRSR_b.R > 0U) + { + data = p_instance_ctrl->p_reg->RDR_b.RDAT; + } + else + { + break; + } + } + else + { + data = p_instance_ctrl->p_reg->RDR_b.RDAT; + } + + #else + { + data = p_instance_ctrl->p_reg->RDR_b.RDAT; + #endif + if (0 == p_instance_ctrl->rx_dest_bytes) + { + /* Call user callback with the data. */ + r_sci_uart_call_callback(p_instance_ctrl, data, UART_EVENT_RX_CHAR); + } + else + { + memcpy((void *) p_instance_ctrl->p_rx_dest, &data, p_instance_ctrl->data_bytes); + p_instance_ctrl->p_rx_dest += p_instance_ctrl->data_bytes; + p_instance_ctrl->rx_dest_bytes -= p_instance_ctrl->data_bytes; + + if (0 == p_instance_ctrl->rx_dest_bytes) + { + r_sci_uart_call_callback(p_instance_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + } + + #if SCI_UART_CFG_FIFO_SUPPORT + } while ((p_instance_ctrl->fifo_depth > 0U) && ((p_instance_ctrl->p_reg->FRSR_b.R) > 0U)); + + if (p_instance_ctrl->fifo_depth > 0U) + { + p_instance_ctrl->p_reg->CFCLR_b.RDRFC = 1; + } + + #else + } + #endif + #if (SCI_UART_CFG_FLOW_CONTROL_SUPPORT) + if (p_instance_ctrl->flow_pin != (bsp_io_port_pin_t) SCI_UART_INVALID_16BIT_PARAM) + { + /* Resume the transmission of data from the other device. */ + R_BSP_PinClear(R_BSP_IoRegionGet(p_instance_ctrl->flow_pin), p_instance_ctrl->flow_pin); + R_BSP_PinAccessDisable(); + } + #endif + } + + #if SCI_UART_CFG_DMAC_SUPPORTED + else + { + p_instance_ctrl->rx_dest_bytes = 0; + p_instance_ctrl->p_rx_dest = NULL; + + /* Call callback */ + r_sci_uart_call_callback(p_instance_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + #endif +} + +/*******************************************************************************************************************//** + * RXI interrupt handler for UART mode. RXI interrupt happens when data arrives to the data register or the FIFO + * register. This function calls sci_uart_rxi_common(). + **********************************************************************************************************************/ +void sci_uart_rxi_isr (void) +{ + SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE; + + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + sci_uart_rxi_common(p_instance_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; + + SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE; +} + +/*******************************************************************************************************************//** + * Callback that must be called after a RX DMAC transfer completes. + * + * @param[in] p_instance_ctrl Pointer to SCI_UART instance control block + **********************************************************************************************************************/ +void sci_uart_rx_dmac_callback (sci_uart_instance_ctrl_t * p_instance_ctrl) +{ + SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE; + + /* Now that the transfer using DMAC is finished, enable the corresponding IRQ. */ + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->rxi_irq); + + sci_uart_rxi_common(p_instance_ctrl); + + SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE; +} + +#endif + +#if (SCI_UART_CFG_TX_ENABLE) + +/*******************************************************************************************************************//** + * TEI interrupt processing for UART mode. The TEI interrupt fires after the last byte is transmitted on the TX pin. + * The user callback function is called with the UART_EVENT_TX_COMPLETE event code (if it is registered in + * R_SCI_UART_Open()). + **********************************************************************************************************************/ +void sci_uart_tei_isr (void) +{ + SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE; + + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Receiving TEI(transmit end interrupt) means the completion of transmission, so call callback function here. */ + p_instance_ctrl->p_reg->CCR0 &= (uint32_t) ~(SCI_UART_CCR0_TIE_MASK | SCI_UART_CCR0_TEIE_MASK); + + /* Dummy read to ensure that interrupts are disabled. */ + volatile uint32_t dummy = p_instance_ctrl->p_reg->CCR0; + FSP_PARAMETER_NOT_USED(dummy); + + r_sci_uart_call_callback(p_instance_ctrl, 0U, UART_EVENT_TX_COMPLETE); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; + + SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE; +} + +#endif + +#if (SCI_UART_CFG_RX_ENABLE) + +/*******************************************************************************************************************//** + * ERI interrupt processing for UART mode. When an ERI interrupt fires, the user callback function is called if it is + * registered in R_SCI_UART_Open() with the event code that triggered the interrupt. + **********************************************************************************************************************/ +void sci_uart_eri_isr (void) +{ + SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE; + + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + uint32_t data = 0U; + uart_event_t event = (uart_event_t) 0U; + + /* Read data. */ + data = p_instance_ctrl->p_reg->RDR_b.RDAT; + + /* Determine cause of error. */ + uint32_t csr = p_instance_ctrl->p_reg->CSR & SCI_UART_RCVR_ERR_MASK; + + if (csr & SCI_UART_CSR_ORER_MASK) + { + event |= UART_EVENT_ERR_OVERFLOW; + } + + if (csr & SCI_UART_CSR_FER_MASK) + { + event |= UART_EVENT_ERR_FRAMING; + } + + if (csr & SCI_UART_CSR_PER_MASK) + { + event |= UART_EVENT_ERR_PARITY; + } + + /* Check if there is a break detected. */ + if ((UART_EVENT_ERR_FRAMING == (event & UART_EVENT_ERR_FRAMING)) && (0U == p_instance_ctrl->p_reg->CSR_b.RXDMON)) + { + event |= UART_EVENT_BREAK_DETECT; + } + + /* Clear error condition. */ + p_instance_ctrl->p_reg->CFCLR |= (uint32_t) (SCI_UART_RCVR_ERRCLR_MASK); + + /* Dummy read to ensure that interrupt event is cleared. */ + volatile uint32_t dummy = p_instance_ctrl->p_reg->CSR; + FSP_PARAMETER_NOT_USED(dummy); + + /* Call callback. */ + r_sci_uart_call_callback(p_instance_ctrl, data, event); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; + + SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE; +} + +#endif diff --git a/bsp/renesas/rzt2m_rsk/rzt_cfg/SConscript b/bsp/renesas/rzt2m_rsk/rzt_cfg/SConscript new file mode 100644 index 00000000000..8d63460c645 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_cfg/SConscript @@ -0,0 +1,19 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +from gcc import * + +cwd = GetCurrentDir() +src = [] +group = [] +CPPPATH = [] + +if rtconfig.PLATFORM in ['iccarm']: + Return('group') +elif rtconfig.PLATFORM in GetGCCLikePLATFORM(): + if GetOption('target') != 'mdk5': + src = Glob('*.c') + CPPPATH = [cwd+'/fsp_cfg', cwd + '/fsp_cfg/bsp'] + +group += DefineGroup('rz_cfg', src, depend = [''], CPPPATH = CPPPATH) +Return('group') diff --git a/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/board_cfg.h b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/board_cfg.h new file mode 100644 index 00000000000..2844e2c4849 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/board_cfg.h @@ -0,0 +1,25 @@ +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#include "../../../rzt/board/rzt2m_rsk/board.h" + #define BSP_CFG_XSPI0_X1_BOOT (1) + #define BSP_CFG_CACHE_FLG (0x00000000) + #define BSP_CFG_CS0BCR_V_WRAPCFG_V (0x00000000) + #define BSP_CFG_CS0WCR_V_COMCFG_V (0x00000000) + #define BSP_CFG_DUMMY0_BMCFG_V (0x00000000) + #define BSP_CFG_BSC_FLG_xSPI_FLG (0x00000000) + #define BSP_CFG_LDR_ADDR_NML (0x6000004C) + #define BSP_CFG_LDR_SIZE_NML (0x00006000) + #define BSP_CFG_DEST_ADDR_NML (0x00102000) + #define BSP_CFG_DUMMY1 (0x00000000) + #define BSP_CFG_DUMMY2 (0x00000000) + #define BSP_CFG_DUMMY3_CSSCTL_V (0x0000003F) + #define BSP_CFG_DUMMY4_LIOCFGCS0_V (0x00070000) + #define BSP_CFG_DUMMY5 (0x00000000) + #define BSP_CFG_DUMMY6 (0x00000000) + #define BSP_CFG_DUMMY7 (0x00000000) + #define BSP_CFG_DUMMY8 (0x00000000) + #define BSP_CFG_DUMMY9 (0x00000000) + #define BSP_CFG_DUMMY10_ACCESS_SPEED (0x00000006) + #define BSP_CFG_CHECK_SUM (0xE0A8) +#endif /* BOARD_CFG_H_ */ diff --git a/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_cfg.h b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 00000000000..989932e34d3 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,37 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define FSP_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #undef FSP_NOT_DEFINED + #define BSP_CFG_MCU_VCC_MV (3300) + + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PORT_PROTECT (1) + + #define BSP_CFG_SOFT_RESET_SUPPORTED (0) + #define BSP_CFG_EARLY_INIT (0) + + #define BSP_CFG_MULTIPLEX_INTERRUPT_SUPPORTED (0) + #if BSP_CFG_MULTIPLEX_INTERRUPT_SUPPORTED + #define BSP_CFG_MULTIPLEX_INTERRUPT_ENABLE BSP_INTERRUPT_ENABLE + #define BSP_CFG_MULTIPLEX_INTERRUPT_DISABLE BSP_INTERRUPT_DISABLE + #else + #define BSP_CFG_MULTIPLEX_INTERRUPT_ENABLE + #define BSP_CFG_MULTIPLEX_INTERRUPT_DISABLE + #endif +#endif /* BSP_CFG_H_ */ diff --git a/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 00000000000..8a578b1be21 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_STACK_FIQ_BYTES (0x1000) + #define BSP_CFG_STACK_IRQ_BYTES (0x1000) + #define BSP_CFG_STACK_ABT_BYTES (0x1000) + #define BSP_CFG_STACK_UND_BYTES (0x1000) + #define BSP_CFG_STACK_SYS_BYTES (0x1000) + #define BSP_CFG_STACK_SVC_BYTES (0x1000) + #define BSP_CFG_HEAP_BYTES (0x8000) + + #define BSP_CFG_C_RUNTIME_INIT (1) + #define BSP_CFG_USE_TFU_MATHLIB ((1)) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h new file mode 100644 index 00000000000..dc3faf2be56 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h @@ -0,0 +1,488 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_MEMORY_CFG_H_ +#define BSP_MCU_DEVICE_MEMORY_CFG_H_ +#define BSP_CFG_MPU0_READ0 (0) + #define BSP_CFG_MPU0_WRITE0 (0) + #define BSP_CFG_MPU0_STADD0 (0x00000000) + #define BSP_CFG_MPU0_ENDADD0 (0x00000C00) + #define BSP_CFG_MPU0_READ1 (0) + #define BSP_CFG_MPU0_WRITE1 (0) + #define BSP_CFG_MPU0_STADD1 (0x00000000) + #define BSP_CFG_MPU0_ENDADD1 (0x00000C00) + #define BSP_CFG_MPU0_READ2 (0) + #define BSP_CFG_MPU0_WRITE2 (0) + #define BSP_CFG_MPU0_STADD2 (0x00000000) + #define BSP_CFG_MPU0_ENDADD2 (0x00000C00) + #define BSP_CFG_MPU0_READ3 (0) + #define BSP_CFG_MPU0_WRITE3 (0) + #define BSP_CFG_MPU0_STADD3 (0x00000000) + #define BSP_CFG_MPU0_ENDADD3 (0x00000C00) + #define BSP_CFG_MPU0_READ4 (0) + #define BSP_CFG_MPU0_WRITE4 (0) + #define BSP_CFG_MPU0_STADD4 (0x00000000) + #define BSP_CFG_MPU0_ENDADD4 (0x00000C00) + #define BSP_CFG_MPU0_READ5 (0) + #define BSP_CFG_MPU0_WRITE5 (0) + #define BSP_CFG_MPU0_STADD5 (0x00000000) + #define BSP_CFG_MPU0_ENDADD5 (0x00000C00) + #define BSP_CFG_MPU0_READ6 (0) + #define BSP_CFG_MPU0_WRITE6 (0) + #define BSP_CFG_MPU0_STADD6 (0x00000000) + #define BSP_CFG_MPU0_ENDADD6 (0x00000C00) + #define BSP_CFG_MPU0_READ7 (0) + #define BSP_CFG_MPU0_WRITE7 (0) + #define BSP_CFG_MPU0_STADD7 (0x00000000) + #define BSP_CFG_MPU0_ENDADD7 (0x00000C00) + #define BSP_CFG_MPU1_READ0 (0) + #define BSP_CFG_MPU1_WRITE0 (0) + #define BSP_CFG_MPU1_STADD0 (0x00000000) + #define BSP_CFG_MPU1_ENDADD0 (0x00000C00) + #define BSP_CFG_MPU1_READ1 (0) + #define BSP_CFG_MPU1_WRITE1 (0) + #define BSP_CFG_MPU1_STADD1 (0x00000000) + #define BSP_CFG_MPU1_ENDADD1 (0x00000C00) + #define BSP_CFG_MPU1_READ2 (0) + #define BSP_CFG_MPU1_WRITE2 (0) + #define BSP_CFG_MPU1_STADD2 (0x00000000) + #define BSP_CFG_MPU1_ENDADD2 (0x00000C00) + #define BSP_CFG_MPU1_READ3 (0) + #define BSP_CFG_MPU1_WRITE3 (0) + #define BSP_CFG_MPU1_STADD3 (0x00000000) + #define BSP_CFG_MPU1_ENDADD3 (0x00000C00) + #define BSP_CFG_MPU1_READ4 (0) + #define BSP_CFG_MPU1_WRITE4 (0) + #define BSP_CFG_MPU1_STADD4 (0x00000000) + #define BSP_CFG_MPU1_ENDADD4 (0x00000C00) + #define BSP_CFG_MPU1_READ5 (0) + #define BSP_CFG_MPU1_WRITE5 (0) + #define BSP_CFG_MPU1_STADD5 (0x00000000) + #define BSP_CFG_MPU1_ENDADD5 (0x00000C00) + #define BSP_CFG_MPU1_READ6 (0) + #define BSP_CFG_MPU1_WRITE6 (0) + #define BSP_CFG_MPU1_STADD6 (0x00000000) + #define BSP_CFG_MPU1_ENDADD6 (0x00000C00) + #define BSP_CFG_MPU1_READ7 (0) + #define BSP_CFG_MPU1_WRITE7 (0) + #define BSP_CFG_MPU1_STADD7 (0x00000000) + #define BSP_CFG_MPU1_ENDADD7 (0x00000C00) + #define BSP_CFG_MPU2_READ0 (0) + #define BSP_CFG_MPU2_WRITE0 (0) + #define BSP_CFG_MPU2_STADD0 (0x00000000) + #define BSP_CFG_MPU2_ENDADD0 (0x00000C00) + #define BSP_CFG_MPU2_READ1 (0) + #define BSP_CFG_MPU2_WRITE1 (0) + #define BSP_CFG_MPU2_STADD1 (0x00000000) + #define BSP_CFG_MPU2_ENDADD1 (0x00000C00) + #define BSP_CFG_MPU2_READ2 (0) + #define BSP_CFG_MPU2_WRITE2 (0) + #define BSP_CFG_MPU2_STADD2 (0x00000000) + #define BSP_CFG_MPU2_ENDADD2 (0x00000C00) + #define BSP_CFG_MPU2_READ3 (0) + #define BSP_CFG_MPU2_WRITE3 (0) + #define BSP_CFG_MPU2_STADD3 (0x00000000) + #define BSP_CFG_MPU2_ENDADD3 (0x00000C00) + #define BSP_CFG_MPU2_READ4 (0) + #define BSP_CFG_MPU2_WRITE4 (0) + #define BSP_CFG_MPU2_STADD4 (0x00000000) + #define BSP_CFG_MPU2_ENDADD4 (0x00000C00) + #define BSP_CFG_MPU2_READ5 (0) + #define BSP_CFG_MPU2_WRITE5 (0) + #define BSP_CFG_MPU2_STADD5 (0x00000000) + #define BSP_CFG_MPU2_ENDADD5 (0x00000C00) + #define BSP_CFG_MPU2_READ6 (0) + #define BSP_CFG_MPU2_WRITE6 (0) + #define BSP_CFG_MPU2_STADD6 (0x00000000) + #define BSP_CFG_MPU2_ENDADD6 (0x00000C00) + #define BSP_CFG_MPU2_READ7 (0) + #define BSP_CFG_MPU2_WRITE7 (0) + #define BSP_CFG_MPU2_STADD7 (0x00000000) + #define BSP_CFG_MPU2_ENDADD7 (0x00000C00) + #define BSP_CFG_MPU3_READ0 (0) + #define BSP_CFG_MPU3_WRITE0 (0) + #define BSP_CFG_MPU3_STADD0 (0x00000000) + #define BSP_CFG_MPU3_ENDADD0 (0x00000000) + #define BSP_CFG_MPU3_READ1 (0) + #define BSP_CFG_MPU3_WRITE1 (0) + #define BSP_CFG_MPU3_STADD1 (0x00000000) + #define BSP_CFG_MPU3_ENDADD1 (0x00000000) + #define BSP_CFG_MPU3_READ2 (0) + #define BSP_CFG_MPU3_WRITE2 (0) + #define BSP_CFG_MPU3_STADD2 (0x00000000) + #define BSP_CFG_MPU3_ENDADD2 (0x00000000) + #define BSP_CFG_MPU3_READ3 (0) + #define BSP_CFG_MPU3_WRITE3 (0) + #define BSP_CFG_MPU3_STADD3 (0x00000000) + #define BSP_CFG_MPU3_ENDADD3 (0x00000000) + #define BSP_CFG_MPU3_READ4 (0) + #define BSP_CFG_MPU3_WRITE4 (0) + #define BSP_CFG_MPU3_STADD4 (0x00000000) + #define BSP_CFG_MPU3_ENDADD4 (0x00000000) + #define BSP_CFG_MPU3_READ5 (0) + #define BSP_CFG_MPU3_WRITE5 (0) + #define BSP_CFG_MPU3_STADD5 (0x00000000) + #define BSP_CFG_MPU3_ENDADD5 (0x00000000) + #define BSP_CFG_MPU3_READ6 (0) + #define BSP_CFG_MPU3_WRITE6 (0) + #define BSP_CFG_MPU3_STADD6 (0x00000000) + #define BSP_CFG_MPU3_ENDADD6 (0x00000000) + #define BSP_CFG_MPU3_READ7 (0) + #define BSP_CFG_MPU3_WRITE7 (0) + #define BSP_CFG_MPU3_STADD7 (0x00000000) + #define BSP_CFG_MPU3_ENDADD7 (0x00000000) + #define BSP_CFG_MPU4_READ0 (0) + #define BSP_CFG_MPU4_WRITE0 (0) + #define BSP_CFG_MPU4_STADD0 (0x00000000) + #define BSP_CFG_MPU4_ENDADD0 (0x00000000) + #define BSP_CFG_MPU4_READ1 (0) + #define BSP_CFG_MPU4_WRITE1 (0) + #define BSP_CFG_MPU4_STADD1 (0x00000000) + #define BSP_CFG_MPU4_ENDADD1 (0x00000000) + #define BSP_CFG_MPU4_READ2 (0) + #define BSP_CFG_MPU4_WRITE2 (0) + #define BSP_CFG_MPU4_STADD2 (0x00000000) + #define BSP_CFG_MPU4_ENDADD2 (0x00000000) + #define BSP_CFG_MPU4_READ3 (0) + #define BSP_CFG_MPU4_WRITE3 (0) + #define BSP_CFG_MPU4_STADD3 (0x00000000) + #define BSP_CFG_MPU4_ENDADD3 (0x00000000) + #define BSP_CFG_MPU4_READ4 (0) + #define BSP_CFG_MPU4_WRITE4 (0) + #define BSP_CFG_MPU4_STADD4 (0x00000000) + #define BSP_CFG_MPU4_ENDADD4 (0x00000000) + #define BSP_CFG_MPU4_READ5 (0) + #define BSP_CFG_MPU4_WRITE5 (0) + #define BSP_CFG_MPU4_STADD5 (0x00000000) + #define BSP_CFG_MPU4_ENDADD5 (0x00000000) + #define BSP_CFG_MPU4_READ6 (0) + #define BSP_CFG_MPU4_WRITE6 (0) + #define BSP_CFG_MPU4_STADD6 (0x00000000) + #define BSP_CFG_MPU4_ENDADD6 (0x00000000) + #define BSP_CFG_MPU4_READ7 (0) + #define BSP_CFG_MPU4_WRITE7 (0) + #define BSP_CFG_MPU4_STADD7 (0x00000000) + #define BSP_CFG_MPU4_ENDADD7 (0x00000000) + #define BSP_CFG_MPU6_READ0 (0) + #define BSP_CFG_MPU6_WRITE0 (0) + #define BSP_CFG_MPU6_STADD0 (0x00000000) + #define BSP_CFG_MPU6_ENDADD0 (0x00000C00) + #define BSP_CFG_MPU6_READ1 (0) + #define BSP_CFG_MPU6_WRITE1 (0) + #define BSP_CFG_MPU6_STADD1 (0x00000000) + #define BSP_CFG_MPU6_ENDADD1 (0x00000C00) + #define BSP_CFG_MPU6_READ2 (0) + #define BSP_CFG_MPU6_WRITE2 (0) + #define BSP_CFG_MPU6_STADD2 (0x00000000) + #define BSP_CFG_MPU6_ENDADD2 (0x00000C00) + #define BSP_CFG_MPU6_READ3 (0) + #define BSP_CFG_MPU6_WRITE3 (0) + #define BSP_CFG_MPU6_STADD3 (0x00000000) + #define BSP_CFG_MPU6_ENDADD3 (0x00000C00) + #define BSP_CFG_MPU6_READ4 (0) + #define BSP_CFG_MPU6_WRITE4 (0) + #define BSP_CFG_MPU6_STADD4 (0x00000000) + #define BSP_CFG_MPU6_ENDADD4 (0x00000C00) + #define BSP_CFG_MPU6_READ5 (0) + #define BSP_CFG_MPU6_WRITE5 (0) + #define BSP_CFG_MPU6_STADD5 (0x00000000) + #define BSP_CFG_MPU6_ENDADD5 (0x00000C00) + #define BSP_CFG_MPU6_READ6 (0) + #define BSP_CFG_MPU6_WRITE6 (0) + #define BSP_CFG_MPU6_STADD6 (0x00000000) + #define BSP_CFG_MPU6_ENDADD6 (0x00000C00) + #define BSP_CFG_MPU6_READ7 (0) + #define BSP_CFG_MPU6_WRITE7 (0) + #define BSP_CFG_MPU6_STADD7 (0x00000000) + #define BSP_CFG_MPU6_ENDADD7 (0x00000C00) + + #define BSP_CFG_CPU_MPU_ATTR0_TYPE (BSP_TYPE_NORMAL_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR0_INNER (BSP_WRITE_BACK_NON_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR0_INNER_READ (BSP_READ_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR0_INNER_WRITE (BSP_WRITE_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR0_OUTER (BSP_WRITE_BACK_NON_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR0_OUTER_READ (BSP_READ_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR0_OUTER_WRITE (BSP_WRITE_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR0_DEVICE_TYPE (BSP_DEVICE_NGNRNE) + + #define BSP_CFG_CPU_MPU_ATTR1_TYPE (BSP_TYPE_NORMAL_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR1_INNER (BSP_WRITE_NON_THROUGH) + #define BSP_CFG_CPU_MPU_ATTR1_INNER_READ (BSP_READ_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR1_INNER_WRITE (BSP_WRITE_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR1_OUTER (BSP_WRITE_NON_THROUGH) + #define BSP_CFG_CPU_MPU_ATTR1_OUTER_READ (BSP_READ_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR1_OUTER_WRITE (BSP_WRITE_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR1_DEVICE_TYPE (BSP_DEVICE_NGNRNE) + + #define BSP_CFG_CPU_MPU_ATTR2_TYPE (BSP_TYPE_NORMAL_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR2_INNER (BSP_WRITE_NON_THROUGH) + #define BSP_CFG_CPU_MPU_ATTR2_INNER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR2_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR2_OUTER (BSP_WRITE_NON_THROUGH) + #define BSP_CFG_CPU_MPU_ATTR2_OUTER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR2_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR2_DEVICE_TYPE (BSP_DEVICE_NGNRNE) + + #define BSP_CFG_CPU_MPU_ATTR3_TYPE (BSP_TYPE_NORMAL_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR3_INNER (BSP_NON_CACHEABLE) + #define BSP_CFG_CPU_MPU_ATTR3_INNER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR3_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR3_OUTER (BSP_NON_CACHEABLE) + #define BSP_CFG_CPU_MPU_ATTR3_OUTER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR3_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR3_DEVICE_TYPE (BSP_DEVICE_NGNRNE) + + #define BSP_CFG_CPU_MPU_ATTR4_TYPE (BSP_TYPE_DEVICE_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR4_INNER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR4_INNER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR4_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR4_OUTER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR4_OUTER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR4_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR4_DEVICE_TYPE (BSP_DEVICE_NGNRNE) + + #define BSP_CFG_CPU_MPU_ATTR5_TYPE (BSP_TYPE_DEVICE_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR5_INNER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR5_INNER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR5_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR5_OUTER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR5_OUTER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR5_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR5_DEVICE_TYPE (BSP_DEVICE_NGNRE) + + #define BSP_CFG_CPU_MPU_ATTR6_TYPE (BSP_TYPE_DEVICE_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR6_INNER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR6_INNER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR6_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR6_OUTER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR6_OUTER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR6_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR6_DEVICE_TYPE (BSP_DEVICE_NGRE) + + #define BSP_CFG_CPU_MPU_ATTR7_TYPE (BSP_TYPE_DEVICE_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR7_INNER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR7_INNER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR7_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR7_OUTER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR7_OUTER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR7_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR7_DEVICE_TYPE (BSP_DEVICE_GRE) + + /* Region00 : ATCM */ + #define BSP_CFG_EL1_MPU_REGION00_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION00_LIMIT (0x0007FFFF) + #define BSP_CFG_EL1_MPU_REGION00_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION00_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION00_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION00_ATTRINDEX (BSP_ATTRINDEX3) + #define BSP_CFG_EL1_MPU_REGION00_ENABLE (BSP_REGION_ENABLE) + + /* Region01 : BTCM */ + #define BSP_CFG_EL1_MPU_REGION01_BASE (0x00100000) + #define BSP_CFG_EL1_MPU_REGION01_LIMIT (0x0010FFFF) + #define BSP_CFG_EL1_MPU_REGION01_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION01_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION01_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION01_ATTRINDEX (BSP_ATTRINDEX3) + #define BSP_CFG_EL1_MPU_REGION01_ENABLE (BSP_REGION_ENABLE) + + /* Region02 : System RAM */ + #define BSP_CFG_EL1_MPU_REGION02_BASE (0x10000000) + #define BSP_CFG_EL1_MPU_REGION02_LIMIT (0x101FFFFF) + #define BSP_CFG_EL1_MPU_REGION02_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION02_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION02_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION02_ATTRINDEX (BSP_ATTRINDEX1) + #define BSP_CFG_EL1_MPU_REGION02_ENABLE (BSP_REGION_ENABLE) + + /* Region03 : Mirror area of System RAM */ + #define BSP_CFG_EL1_MPU_REGION03_BASE (0x30000000) + #define BSP_CFG_EL1_MPU_REGION03_LIMIT (0x301FFFFF) + #define BSP_CFG_EL1_MPU_REGION03_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION03_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION03_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION03_ATTRINDEX (BSP_ATTRINDEX3) + #define BSP_CFG_EL1_MPU_REGION03_ENABLE (BSP_REGION_ENABLE) + + /* Region04 : Mirror area of external address space */ + #define BSP_CFG_EL1_MPU_REGION04_BASE (0x40000000) + #define BSP_CFG_EL1_MPU_REGION04_LIMIT (0x5FFFFFFF) + #define BSP_CFG_EL1_MPU_REGION04_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION04_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION04_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION04_ATTRINDEX (BSP_ATTRINDEX3) + #define BSP_CFG_EL1_MPU_REGION04_ENABLE (BSP_REGION_ENABLE) + + /* Region05 : External address space */ + #define BSP_CFG_EL1_MPU_REGION05_BASE (0x60000000) + #define BSP_CFG_EL1_MPU_REGION05_LIMIT (0x7FFFFFFF) + #define BSP_CFG_EL1_MPU_REGION05_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION05_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION05_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION05_ATTRINDEX (BSP_ATTRINDEX1) + #define BSP_CFG_EL1_MPU_REGION05_ENABLE (BSP_REGION_ENABLE) + + /* Region06 : Non-Safety Peripheral */ + #define BSP_CFG_EL1_MPU_REGION06_BASE (0x80000000) + #define BSP_CFG_EL1_MPU_REGION06_LIMIT (0x80FFFFFF) + #define BSP_CFG_EL1_MPU_REGION06_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION06_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION06_XN (BSP_EXECUTE_NEVER) + #define BSP_CFG_EL1_MPU_REGION06_ATTRINDEX (BSP_ATTRINDEX5) + #define BSP_CFG_EL1_MPU_REGION06_ENABLE (BSP_REGION_ENABLE) + + /* Region07 : Safety Peripheral */ + #define BSP_CFG_EL1_MPU_REGION07_BASE (0x81000000) + #define BSP_CFG_EL1_MPU_REGION07_LIMIT (0x81FFFFFF) + #define BSP_CFG_EL1_MPU_REGION07_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION07_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION07_XN (BSP_EXECUTE_NEVER) + #define BSP_CFG_EL1_MPU_REGION07_ATTRINDEX (BSP_ATTRINDEX5) + #define BSP_CFG_EL1_MPU_REGION07_ENABLE (BSP_REGION_ENABLE) + + /* Region08 : LLPP Peripheral */ + #define BSP_CFG_EL1_MPU_REGION08_BASE (0x90000000) + #define BSP_CFG_EL1_MPU_REGION08_LIMIT (0x901FFFFF) + #define BSP_CFG_EL1_MPU_REGION08_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION08_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION08_XN (BSP_EXECUTE_NEVER) + #define BSP_CFG_EL1_MPU_REGION08_ATTRINDEX (BSP_ATTRINDEX5) + #define BSP_CFG_EL1_MPU_REGION08_ENABLE (BSP_REGION_ENABLE) + + /* Region09 : GIC0 */ + #define BSP_CFG_EL1_MPU_REGION09_BASE (0x94000000) + #define BSP_CFG_EL1_MPU_REGION09_LIMIT (0x941FFFFF) + #define BSP_CFG_EL1_MPU_REGION09_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION09_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION09_XN (BSP_EXECUTE_NEVER) + #define BSP_CFG_EL1_MPU_REGION09_ATTRINDEX (BSP_ATTRINDEX4) + #define BSP_CFG_EL1_MPU_REGION09_ENABLE (BSP_REGION_ENABLE) + + /* Region10 : Encoder IF area */ + #define BSP_CFG_EL1_MPU_REGION10_BASE (0xA0000000) + #define BSP_CFG_EL1_MPU_REGION10_LIMIT (0xA0FFFFFF) + #define BSP_CFG_EL1_MPU_REGION10_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION10_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION10_XN (BSP_EXECUTE_NEVER) + #define BSP_CFG_EL1_MPU_REGION10_ATTRINDEX (BSP_ATTRINDEX5) + #define BSP_CFG_EL1_MPU_REGION10_ENABLE (BSP_REGION_ENABLE) + + /* Region11 : Debug Private */ + #define BSP_CFG_EL1_MPU_REGION11_BASE (0xC0000000) + #define BSP_CFG_EL1_MPU_REGION11_LIMIT (0xC0FFFFFF) + #define BSP_CFG_EL1_MPU_REGION11_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION11_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION11_XN (BSP_EXECUTE_NEVER) + #define BSP_CFG_EL1_MPU_REGION11_ATTRINDEX (BSP_ATTRINDEX4) + #define BSP_CFG_EL1_MPU_REGION11_ENABLE (BSP_REGION_ENABLE) + + /* Region12 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION12_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION12_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION12_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION12_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION12_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION12_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION12_ENABLE (BSP_REGION_DISABLE) + + /* Region13 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION13_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION13_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION13_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION13_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION13_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION13_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION13_ENABLE (BSP_REGION_DISABLE) + + /* Region14 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION14_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION14_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION14_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION14_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION14_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION14_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION14_ENABLE (BSP_REGION_DISABLE) + + /* Region15 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION15_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION15_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION15_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION15_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION15_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION15_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION15_ENABLE (BSP_REGION_DISABLE) + + /* Region16 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION16_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION16_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION16_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION16_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION16_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION16_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION16_ENABLE (BSP_REGION_DISABLE) + + /* Region17 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION17_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION17_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION17_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION17_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION17_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION17_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION17_ENABLE (BSP_REGION_DISABLE) + + /* Region18 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION18_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION18_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION18_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION18_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION18_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION18_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION18_ENABLE (BSP_REGION_DISABLE) + + /* Region19 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION19_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION19_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION19_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION19_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION19_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION19_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION19_ENABLE (BSP_REGION_DISABLE) + + /* Region20 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION20_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION20_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION20_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION20_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION20_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION20_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION20_ENABLE (BSP_REGION_DISABLE) + + /* Region21 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION21_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION21_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION21_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION21_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION21_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION21_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION21_ENABLE (BSP_REGION_DISABLE) + + /* Region22 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION22_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION22_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION22_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION22_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION22_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION22_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION22_ENABLE (BSP_REGION_DISABLE) + + /* Region23 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION23_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION23_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION23_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION23_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION23_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION23_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION23_ENABLE (BSP_REGION_DISABLE) + + #define BSP_CFG_SCTLR_BR_BIT (BSP_BG_REGION_DISABLE) + #define BSP_CFG_SCTLR_I_BIT (BSP_ICACHE_ENABLE) + #define BSP_CFG_SCTLR_C_BIT (BSP_DATACACHE_ENABLE) +#endif /* BSP_MCU_DEVICE_MEMORY_CFG_H_ */ diff --git a/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 00000000000..c04349819e1 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R9A07G075M24GBG + #define BSP_ATCM_SIZE_BYTES (524288) + #define BSP_BTCM_SIZE_BYTES (65536) + #define BSP_SYSTEM_RAM_SIZE_BYTES (2097152) + #define BSP_PACKAGE_BGA + #define BSP_PACKAGE_PINS (320) + + #define BSP_CFG_CORE_CR52 (0) + #define BSP_CFG_SEMAPHORE_ENABLE (1) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 00000000000..e8b58e50b23 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,15 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "bsp_mcu_device_memory_cfg.h" + #include "../../../rzt/fsp/src/bsp/mcu/rzt2m/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_API_OVERRIDE "../../src/bsp/mcu/rzt2m/bsp_override.h" + #define BSP_MCU_GROUP_RZT2M (1) + #define BSP_LOCO_HZ (240000) + #define BSP_GLOBAL_SYSTEM_COUNTER_CLOCK_HZ (25000000) + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (32) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (448) +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_memory_cfg.h b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_memory_cfg.h new file mode 100644 index 00000000000..baaa5be87a3 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_memory_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MEMORY_CFG_H_ +#define BSP_MEMORY_CFG_H_ +#define BSP_MPU_SUPPORT +#endif /* BSP_MEMORY_CFG_H_ */ diff --git a/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 00000000000..8b423fba1aa --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,132 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" +#define ETH2_RXD3 (BSP_IO_PORT_00_PIN_0) +#define ETH2_RXDV (BSP_IO_PORT_00_PIN_1) +#define ETH2_TXEN (BSP_IO_PORT_00_PIN_2) +#define ETH2_REFCLK (BSP_IO_PORT_00_PIN_3) +#define ETH2_LINK (BSP_IO_PORT_00_PIN_5) +#define ETH2_TXCLK (BSP_IO_PORT_00_PIN_6) +#define ETH2_TXD3 (BSP_IO_PORT_01_PIN_2) +#define ETH2_TXD2 (BSP_IO_PORT_01_PIN_3) +#define ETH2_TXD1 (BSP_IO_PORT_01_PIN_4) +#define ETH2_TXD0 (BSP_IO_PORT_01_PIN_5) +#define TDO (BSP_IO_PORT_02_PIN_4) +#define TDI (BSP_IO_PORT_02_PIN_5) +#define TMS (BSP_IO_PORT_02_PIN_6) +#define TCK (BSP_IO_PORT_02_PIN_7) +#define TRACE_D5 (BSP_IO_PORT_03_PIN_7) +#define BSC_CS0 (BSP_IO_PORT_04_PIN_2) +#define CAN_RX (BSP_IO_PORT_05_PIN_2) +#define CAN_TX (BSP_IO_PORT_05_PIN_3) +#define ETH1_LINK (BSP_IO_PORT_05_PIN_5) +#define ETH1_TXD2 (BSP_IO_PORT_05_PIN_7) +#define ETH1_TXD3 (BSP_IO_PORT_06_PIN_0) +#define ETH1_REFCLK (BSP_IO_PORT_06_PIN_1) +#define ETH1_TXD1 (BSP_IO_PORT_06_PIN_2) +#define ETH1_TXD0 (BSP_IO_PORT_06_PIN_3) +#define ETH1_TXCLK (BSP_IO_PORT_06_PIN_4) +#define ETH1_TXEN (BSP_IO_PORT_06_PIN_5) +#define ETH1_RXD0 (BSP_IO_PORT_06_PIN_6) +#define ETH1_RXD1 (BSP_IO_PORT_06_PIN_7) +#define ETH1_RXD2 (BSP_IO_PORT_07_PIN_0) +#define ETH1_RXD3 (BSP_IO_PORT_07_PIN_1) +#define ETH1_RXDV (BSP_IO_PORT_07_PIN_2) +#define ETH1_RXCLK (BSP_IO_PORT_07_PIN_3) +#define USB_VBUSIN (BSP_IO_PORT_07_PIN_4) +#define ETH_LED6 (BSP_IO_PORT_08_PIN_2) +#define ETH0_RXD3 (BSP_IO_PORT_08_PIN_4) +#define ETH0_RXDV (BSP_IO_PORT_08_PIN_5) +#define ETH0_RXCLK (BSP_IO_PORT_08_PIN_6) +#define ETH_MDC (BSP_IO_PORT_08_PIN_7) +#define ETH_MDIO (BSP_IO_PORT_09_PIN_0) +#define ETH0_REFCLK (BSP_IO_PORT_09_PIN_1) +#define ETH0_TXD3 (BSP_IO_PORT_09_PIN_3) +#define ETH0_TXD2 (BSP_IO_PORT_09_PIN_4) +#define ETH0_TXD1 (BSP_IO_PORT_09_PIN_5) +#define ETH0_TXD0 (BSP_IO_PORT_09_PIN_6) +#define ETH0_TXCLK (BSP_IO_PORT_09_PIN_7) +#define ETH0_TXEN (BSP_IO_PORT_10_PIN_0) +#define ETH0_RXD0 (BSP_IO_PORT_10_PIN_1) +#define ETH0_RXD1 (BSP_IO_PORT_10_PIN_2) +#define ETH0_RXD2 (BSP_IO_PORT_10_PIN_3) +#define ETH0_LINK (BSP_IO_PORT_10_PIN_4) +#define SW1 (BSP_IO_PORT_10_PIN_5) +#define SW3_Pin5 (BSP_IO_PORT_10_PIN_6) +#define SW3_Pin1 (BSP_IO_PORT_11_PIN_0) +#define SW3_Pin2 (BSP_IO_PORT_11_PIN_3) +#define SW3_Pin3 (BSP_IO_PORT_11_PIN_4) +#define SW3_Pin4 (BSP_IO_PORT_11_PIN_6) +#define HYPER_DS (BSP_IO_PORT_11_PIN_7) +#define HYRAM_IO7 (BSP_IO_PORT_12_PIN_0) +#define HYRAM_IO6 (BSP_IO_PORT_12_PIN_1) +#define HYRAM_IO5 (BSP_IO_PORT_12_PIN_2) +#define HYRAM_IO4 (BSP_IO_PORT_12_PIN_3) +#define HYRAM_RESET0 (BSP_IO_PORT_12_PIN_4) +#define HYRAM_IO3 (BSP_IO_PORT_12_PIN_5) +#define HYRAM_IO2 (BSP_IO_PORT_12_PIN_6) +#define HYRAM_IO1 (BSP_IO_PORT_12_PIN_7) +#define HYRAM_IO0 (BSP_IO_PORT_13_PIN_0) +#define HYRAM_CS0 (BSP_IO_PORT_13_PIN_1) +#define SW3_Pin6 (BSP_IO_PORT_13_PIN_2) +#define HYRAM_CKP (BSP_IO_PORT_13_PIN_3) +#define HYRAM_CKN (BSP_IO_PORT_13_PIN_4) +#define SW3_Pin7 (BSP_IO_PORT_13_PIN_7) +#define SW3_Pin8 (BSP_IO_PORT_14_PIN_1) +#define XSPI0_ECS (BSP_IO_PORT_14_PIN_2) +#define XSPI0_DS (BSP_IO_PORT_14_PIN_4) +#define BSC_CS3 (BSP_IO_PORT_14_PIN_5) +#define XSPI0_CKP (BSP_IO_PORT_14_PIN_6) +#define XSPI0_IO0 (BSP_IO_PORT_14_PIN_7) +#define XSPI0_IO1 (BSP_IO_PORT_15_PIN_0) +#define XSPI0_IO2 (BSP_IO_PORT_15_PIN_1) +#define XSPI0_IO3 (BSP_IO_PORT_15_PIN_2) +#define XSPI0_IO4 (BSP_IO_PORT_15_PIN_3) +#define XSPI0_IO5 (BSP_IO_PORT_15_PIN_4) +#define XSPI0_IO6 (BSP_IO_PORT_15_PIN_5) +#define XSPI0_IO7 (BSP_IO_PORT_15_PIN_6) +#define XSPI0_CS0 (BSP_IO_PORT_15_PIN_7) +#define XSPI0_RESET0 (BSP_IO_PORT_16_PIN_1) +#define SW2 (BSP_IO_PORT_16_PIN_3) +#define UART_USB_TX (BSP_IO_PORT_16_PIN_5) +#define UART_USB_RX (BSP_IO_PORT_16_PIN_6) +#define USB_OVRCUR (BSP_IO_PORT_17_PIN_5) +#define RS485_RXD (BSP_IO_PORT_17_PIN_7) +#define SCI_TXD (BSP_IO_PORT_18_PIN_0) +#define RSPCK2 (BSP_IO_PORT_18_PIN_4) +#define MOSI2 (BSP_IO_PORT_18_PIN_5) +#define MISO2 (BSP_IO_PORT_18_PIN_6) +#define SSL20 (BSP_IO_PORT_18_PIN_7) +#define USB_VBUSEN_MDV4 (BSP_IO_PORT_19_PIN_0) +#define ETH_LED7 (BSP_IO_PORT_19_PIN_3) +#define RLED1 (BSP_IO_PORT_19_PIN_4) +#define RLED0 (BSP_IO_PORT_19_PIN_6) +#define ETH_LED4 (BSP_IO_PORT_19_PIN_7) +#define RLED2 (BSP_IO_PORT_20_PIN_0) +#define ETH_LED2_MDV0 (BSP_IO_PORT_20_PIN_1) +#define ETH_LED0_MDV1 (BSP_IO_PORT_20_PIN_2) +#define ETH_LED1_MDV2 (BSP_IO_PORT_20_PIN_3) +#define ETH_LED3_MDV3 (BSP_IO_PORT_20_PIN_4) +#define EEPROM_SCL (BSP_IO_PORT_20_PIN_5) +#define EEPROM_SDA (BSP_IO_PORT_20_PIN_6) +#define ETH_RESET (BSP_IO_PORT_20_PIN_7) +#define ETH_LED5 (BSP_IO_PORT_21_PIN_0) +#define TRACE_D0 (BSP_IO_PORT_21_PIN_1) +#define TRACE_D1 (BSP_IO_PORT_21_PIN_2) +#define TRACE_D2 (BSP_IO_PORT_21_PIN_3) +#define TRACE_D3 (BSP_IO_PORT_21_PIN_4) +#define TRACE_D4 (BSP_IO_PORT_21_PIN_5) +#define TRACE_D6 (BSP_IO_PORT_21_PIN_7) +#define TRACE_D7 (BSP_IO_PORT_22_PIN_0) +#define TRACE_CTL (BSP_IO_PORT_22_PIN_1) +#define TRACE_CLK (BSP_IO_PORT_22_PIN_2) +#define I2C_SCL_A (BSP_IO_PORT_22_PIN_6) +#define I2C_SDA_A (BSP_IO_PORT_22_PIN_7) +#define RLED3 (BSP_IO_PORT_23_PIN_4) +#define ETH2_RXD0 (BSP_IO_PORT_23_PIN_7) +#define ETH2_RXD1 (BSP_IO_PORT_24_PIN_0) +#define ETH2_RXCLK (BSP_IO_PORT_24_PIN_1) +#define ETH2_RXD2 (BSP_IO_PORT_24_PIN_2) +extern const ioport_cfg_t g_bsp_pin_cfg; /* RSK+RZT2M */ +#endif /* BSP_PIN_CFG_H_ */ diff --git a/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/r_ioport_cfg.h b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 00000000000..d2688bf5ba3 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/r_sci_uart_cfg.h b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/r_sci_uart_cfg.h new file mode 100644 index 00000000000..fe4cc09bf17 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_cfg/fsp_cfg/r_sci_uart_cfg.h @@ -0,0 +1,16 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SCI_UART_CFG_H_ +#define R_SCI_UART_CFG_H_ +#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SCI_UART_CFG_FIFO_SUPPORT (1) +#define SCI_UART_CFG_DMAC_SUPPORTED (0) +#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) +#define SCI_UART_CFG_MULTIPLEX_INTERRUPT_SUPPORTED (0) +#if SCI_UART_CFG_MULTIPLEX_INTERRUPT_SUPPORTED + #define SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE BSP_INTERRUPT_ENABLE + #define SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE BSP_INTERRUPT_DISABLE +#else + #define SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE + #define SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE +#endif +#endif /* R_SCI_UART_CFG_H_ */ diff --git a/bsp/renesas/rzt2m_rsk/rzt_gen/SConscript b/bsp/renesas/rzt2m_rsk/rzt_gen/SConscript new file mode 100644 index 00000000000..33e4f94e073 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_gen/SConscript @@ -0,0 +1,19 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +from gcc import * + +cwd = GetCurrentDir() +src = [] +group = [] +CPPPATH = [] + +if rtconfig.PLATFORM in ['iccarm']: + Return('group') +elif rtconfig.PLATFORM in GetGCCLikePLATFORM(): + if GetOption('target') != 'mdk5': + src = Glob('*.c') + CPPPATH = [cwd, ] + +group = DefineGroup('rz_gen', src, depend = [''], CPPPATH = CPPPATH) +Return('group') diff --git a/bsp/renesas/rzt2m_rsk/rzt_gen/bsp_clock_cfg.h b/bsp/renesas/rzt2m_rsk/rzt_gen/bsp_clock_cfg.h new file mode 100644 index 00000000000..9d26263b6ad --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_gen/bsp_clock_cfg.h @@ -0,0 +1,43 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_MAIN_CLOCK_HZ (25000000) /* Main Clock: 25MHz */ +#define BSP_CFG_LOCO_ENABLE (BSP_CLOCKS_LOCO_ENABLE) /* LOCO Enabled */ +#define BSP_CFG_PLL1 (BSP_CLOCKS_PLL1_INITIAL) /* PLL1 is initial state */ +#define BSP_CFG_PHYSEL (BSP_CLOCKS_PHYSEL_PLL1_DIV) /* Ethernet Clock src: PLL1 divider clock */ +#define BSP_CFG_CLMA0_ENABLE (BSP_CLOCKS_CLMA0_ENABLE) /* CLMA0 Enabled */ +#define BSP_CFG_CLMA0MASK (BSP_CLOCKS_CLMA0_ERROR_NOT_MASK) /* CLMA0 error not mask */ +#define BSP_CFG_CLMA3MASK (BSP_CLOCKS_CLMA3_ERROR_NOT_MASK) /* CLMA3 error not mask */ +#define BSP_CFG_CLMA1MASK (BSP_CLOCKS_CLMA1_ERROR_MASK) /* CLMA1 error mask */ +#define BSP_CFG_CLMA3_ENABLE (BSP_CLOCKS_CLMA3_ENABLE) /* CLMA3 Enabled */ +#define BSP_CFG_CLMA1_ENABLE (BSP_CLOCKS_CLMA1_ENABLE) /* CLMA1 Enabled */ +#define BSP_CFG_CLMA2_ENABLE (BSP_CLOCKS_CLMA2_ENABLE) /* CLMA2 Enabled */ +#define BSP_CFG_CLMA0_CMPL (1) /* CLMA0 CMPL 1 */ +#define BSP_CFG_CLMA1_CMPL (1) /* CLMA1 CMPL 1 */ +#define BSP_CFG_CLMA2_CMPL (1) /* CLMA2 CMPL 1 */ +#define BSP_CFG_CLMA3_CMPL (1) /* CLMA3 CMPL 1 */ +#define BSP_CFG_CLMASEL (BSP_CLOCKS_CLMASEL_LOCO) /* Alternative clock: LOCO */ +#define BSP_CFG_CLMA0_CMPH (1023) /* CLMA0 CMPH 1023 */ +#define BSP_CFG_CLMA1_CMPH (1023) /* CLMA1 CMPH 1023 */ +#define BSP_CFG_CLMA2_CMPH (1023) /* CLMA2 CMPH 1023 */ +#define BSP_CFG_CLMA3_CMPH (1023) /* CLMA3 CMPH 1023 */ +#define BSP_CFG_DIVSELSUB (BSP_CLOCKS_DIVSELSUB_0) /* ICLK 200MHz */ +#define BSP_CFG_SCI0ASYNCCLK (BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI0ASYNCCLK: 96MHz */ +#define BSP_CFG_SCI1ASYNCCLK (BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI1ASYNCCLK: 96MHz */ +#define BSP_CFG_SCI2ASYNCCLK (BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI2ASYNCCLK: 96MHz */ +#define BSP_CFG_SCI3ASYNCCLK (BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI3ASYNCCLK: 96MHz */ +#define BSP_CFG_SCI4ASYNCCLK (BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI4ASYNCCLK: 96MHz */ +#define BSP_CFG_SCI5ASYNCCLK (BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI5ASYNCCLK: 96MHz */ +#define BSP_CFG_SPI0ASYNCCLK (BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI0ASYNCCLK: 96MHz */ +#define BSP_CFG_SPI1ASYNCCLK (BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI1ASYNCCLK: 96MHz */ +#define BSP_CFG_SPI2ASYNCCLK (BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI2ASYNCCLK: 96MHz */ +#define BSP_CFG_SPI3ASYNCCLK (BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI3ASYNCCLK: 96MHz */ +#define BSP_CFG_FSELCPU0 (BSP_CLOCKS_FSELCPU0_ICLK_MUL1) /* CPU0CLK Mul x1 */ +#define BSP_CFG_FSELCPU1 (BSP_CLOCKS_FSELCPU1_ICLK_MUL1) /* CPU1CLK Mul x1 */ +#define BSP_CFG_CKIO (BSP_CLOCKS_CKIO_ICLK_DIV4) /* CKIO Div /4 */ +#define BSP_CFG_FSELCANFD (BSP_CLOCKS_CANFD_CLOCK_40_MHZ) /* PCLKCAN 40MHz */ +#define BSP_CFG_FSELXSPI0_DIVSELXSPI0 (BSP_CLOCKS_XSPI0_CLOCK_DIV0_12_5_MHZ) /* XSPI_CLK0 12.5MHz */ +#define BSP_CFG_FSELXSPI1_DIVSELXSPI1 (BSP_CLOCKS_XSPI1_CLOCK_DIV0_12_5_MHZ) /* XSPI_CLK1 12.5MHz */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/bsp/renesas/rzt2m_rsk/rzt_gen/common_data.c b/bsp/renesas/rzt2m_rsk/rzt_gen/common_data.c new file mode 100644 index 00000000000..2c7f165bf0f --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_gen/common_data.c @@ -0,0 +1,75 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +/** IOPORT interface configuration for event link **/ + const ioport_extend_cfg_t g_ioport_cfg_extend = + { + .port_group_output_cfg[IOPORT_PORT_GROUP_1] = + { + .pin_select = (uint8_t)( IOPORT_EVENT_PIN_SELECTION_NONE), + .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW + }, + .port_group_output_cfg[IOPORT_PORT_GROUP_2] = + { + .pin_select = (uint8_t)( IOPORT_EVENT_PIN_SELECTION_NONE), + .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW + }, + .port_group_input_cfg[IOPORT_PORT_GROUP_1] = + { + .event_control = IOPORT_EVENT_CONTROL_DISABLE, + .pin_select = (uint8_t)( IOPORT_EVENT_PIN_SELECTION_NONE), + .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE, + .overwrite_control = IOPORT_EVENT_CONTROL_DISABLE, + .buffer_init_value = IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 7U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 6U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 5U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 4U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 3U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 2U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 1U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW + }, + .port_group_input_cfg[IOPORT_PORT_GROUP_2] = + { + .event_control = IOPORT_EVENT_CONTROL_DISABLE, + .pin_select = (uint8_t)( IOPORT_EVENT_PIN_SELECTION_NONE), + .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE, + .overwrite_control = IOPORT_EVENT_CONTROL_DISABLE, + .buffer_init_value = IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 7U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 6U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 5U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 4U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 3U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 2U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 1U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW + }, + .single_port_cfg[IOPORT_SINGLE_PORT_0] = + { + .event_control = IOPORT_EVENT_CONTROL_DISABLE, + .direction = IOPORT_EVENT_DIRECTION_OUTPUT, + .port_num = (uint16_t)BSP_IO_PORT_16_PIN_0, + .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW, + .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE + }, + .single_port_cfg[IOPORT_SINGLE_PORT_1] = + { + .event_control = IOPORT_EVENT_CONTROL_DISABLE, + .direction = IOPORT_EVENT_DIRECTION_OUTPUT, + .port_num = (uint16_t)BSP_IO_PORT_16_PIN_0, + .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW, + .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE + }, + .single_port_cfg[IOPORT_SINGLE_PORT_2] = + { + .event_control = IOPORT_EVENT_CONTROL_DISABLE, + .direction = IOPORT_EVENT_DIRECTION_OUTPUT, + .port_num = (uint16_t)BSP_IO_PORT_16_PIN_0, + .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW, + .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE + }, + .single_port_cfg[IOPORT_SINGLE_PORT_3] = + { + .event_control = IOPORT_EVENT_CONTROL_DISABLE, + .direction = IOPORT_EVENT_DIRECTION_OUTPUT, + .port_num = (uint16_t)BSP_IO_PORT_16_PIN_0, + .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW, + .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE + } + }; + +ioport_instance_ctrl_t g_ioport_ctrl; + +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg + }; +void g_common_init(void) { +} diff --git a/bsp/renesas/rzt2m_rsk/rzt_gen/common_data.h b/bsp/renesas/rzt2m_rsk/rzt_gen/common_data.h new file mode 100644 index 00000000000..e2eb70836ba --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_gen/common_data.h @@ -0,0 +1,16 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/bsp/renesas/rzt2m_rsk/rzt_gen/hal_data.c b/bsp/renesas/rzt2m_rsk/rzt_gen/hal_data.c new file mode 100644 index 00000000000..2ddb428c13d --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_gen/hal_data.c @@ -0,0 +1,110 @@ +/* generated HAL source file - do not edit */ +#include "hal_data.h" +sci_uart_instance_ctrl_t g_uart0_ctrl; + + #define FSP_NOT_DEFINED (1) + #if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED) + + /* If the transfer module is DMAC, define a DMAC transfer callback. */ + extern void sci_uart_tx_dmac_callback(sci_uart_instance_ctrl_t * p_instance_ctrl); + + void g_uart0_tx_transfer_callback (transfer_callback_args_t * p_args) + { + FSP_PARAMETER_NOT_USED(p_args); + sci_uart_tx_dmac_callback(&g_uart0_ctrl); + } + #endif + + #if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED) + + /* If the transfer module is DMAC, define a DMAC transfer callback. */ + extern void sci_uart_rx_dmac_callback(sci_uart_instance_ctrl_t * p_instance_ctrl); + + void g_uart0_rx_transfer_callback (transfer_callback_args_t * p_args) + { + FSP_PARAMETER_NOT_USED(p_args); + sci_uart_rx_dmac_callback(&g_uart0_ctrl); + } + #endif + #undef FSP_NOT_DEFINED + + sci_baud_setting_t g_uart0_baud_setting = + { + /* Baud rate calculated with 0.160% error. */ .baudrate_bits_b.abcse = 0, .baudrate_bits_b.abcs = 0, .baudrate_bits_b.bgdm = 1, .baudrate_bits_b.cks = 0, .baudrate_bits_b.brr = 51, .baudrate_bits_b.mddr = (uint8_t) 256, .baudrate_bits_b.brme = false + }; + + /** UART extended configuration for UARTonSCI HAL driver */ + const sci_uart_extended_cfg_t g_uart0_cfg_extend = + { + .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart0_baud_setting, +#if 1 + .clock_source = SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK, +#else + .clock_source = SCI_UART_CLOCK_SOURCE_PCLKM, +#endif + .flow_control = SCI_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + .rs485_setting = { + .enable = SCI_UART_RS485_DISABLE, + .polarity = SCI_UART_RS485_DE_POLARITY_HIGH, + .assertion_time = 1, + .negation_time = 1, + }, + }; + + /** UART interface configuration */ + const uart_cfg_t g_uart0_cfg = + { + .channel = 0, + .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .p_callback = user_uart0_callback, + .p_context = NULL, + .p_extend = &g_uart0_cfg_extend, + .p_transfer_tx = g_uart0_P_TRANSFER_TX, + .p_transfer_rx = g_uart0_P_TRANSFER_RX, + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI0_RXI) + .rxi_irq = VECTOR_NUMBER_SCI0_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI0_TXI) + .txi_irq = VECTOR_NUMBER_SCI0_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI0_TEI) + .tei_irq = VECTOR_NUMBER_SCI0_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI0_ERI) + .eri_irq = VECTOR_NUMBER_SCI0_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart0 = +{ + .p_ctrl = &g_uart0_ctrl, + .p_cfg = &g_uart0_cfg, + .p_api = &g_uart_on_sci +}; +void g_hal_init(void) { +g_common_init(); +} diff --git a/bsp/renesas/rzt2m_rsk/rzt_gen/hal_data.h b/bsp/renesas/rzt2m_rsk/rzt_gen/hal_data.h new file mode 100644 index 00000000000..983bc881f4a --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_gen/hal_data.h @@ -0,0 +1,37 @@ +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include +#include "bsp_api.h" +#include "common_data.h" +#include "r_sci_uart.h" + #include "r_uart_api.h" +FSP_HEADER +/** UART on SCI Instance. */ + extern const uart_instance_t g_uart0; + + /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ + extern sci_uart_instance_ctrl_t g_uart0_ctrl; + extern const uart_cfg_t g_uart0_cfg; + extern const sci_uart_extended_cfg_t g_uart0_cfg_extend; + + #ifndef user_uart0_callback + void user_uart0_callback(uart_callback_args_t * p_args); + #endif + + #define FSP_NOT_DEFINED (1) + #if (FSP_NOT_DEFINED == FSP_NOT_DEFINED) + #define g_uart0_P_TRANSFER_TX (NULL) + #else + #define g_uart0_P_TRANSFER_TX (&FSP_NOT_DEFINED) + #endif + #if (FSP_NOT_DEFINED == FSP_NOT_DEFINED) + #define g_uart0_P_TRANSFER_RX (NULL) + #else + #define g_uart0_P_TRANSFER_RX (&FSP_NOT_DEFINED) + #endif + #undef FSP_NOT_DEFINED +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/bsp/renesas/rzt2m_rsk/rzt_gen/main.c b/bsp/renesas/rzt2m_rsk/rzt_gen/main.c new file mode 100644 index 00000000000..42c5904834c --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_gen/main.c @@ -0,0 +1,6 @@ +/* generated main source file - do not edit */ +#include "hal_data.h" + int main(void) { + hal_entry(); + return 0; + } diff --git a/bsp/renesas/rzt2m_rsk/rzt_gen/pin_data.c b/bsp/renesas/rzt2m_rsk/rzt_gen/pin_data.c new file mode 100644 index 00000000000..b790a04a0f3 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_gen/pin_data.c @@ -0,0 +1,528 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport_api.h" +#include "r_ioport.h" + +extern const ioport_extend_cfg_t g_ioport_cfg_extend; + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P000_PFC_00_ETH2_RXD3) + }, + { + .pin = BSP_IO_PORT_00_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P001_PFC_01_ETH2_RXDV) + }, + { + .pin = BSP_IO_PORT_00_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P002_PFC_00_ETH2_TXEN) + }, + { + .pin = BSP_IO_PORT_00_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P003_PFC_01_ETH2_REFCLK) + }, + { + .pin = BSP_IO_PORT_00_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P005_PFC_00_ETHSW_PHYLINK2) + }, + { + .pin = BSP_IO_PORT_00_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P006_PFC_00_ETH2_TXCLK) + }, + { + .pin = BSP_IO_PORT_01_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P012_PFC_01_ETH2_TXD3) + }, + { + .pin = BSP_IO_PORT_01_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P013_PFC_00_ETH2_TXD2) + }, + { + .pin = BSP_IO_PORT_01_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P014_PFC_01_ETH2_TXD1) + }, + { + .pin = BSP_IO_PORT_01_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P015_PFC_00_ETH2_TXD0) + }, + { + .pin = BSP_IO_PORT_02_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P024_PFC_00_TDO) + }, + { + .pin = BSP_IO_PORT_02_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P025_PFC_01_TDI) + }, + { + .pin = BSP_IO_PORT_02_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P026_PFC_00_TMS_SWDIO) + }, + { + .pin = BSP_IO_PORT_02_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P027_PFC_00_TCK_SWCLK) + }, + { + .pin = BSP_IO_PORT_03_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P037_PFC_02_TRACEDATA5) + }, + { + .pin = BSP_IO_PORT_04_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_05_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P052_PFC_09_CANRX0) + }, + { + .pin = BSP_IO_PORT_05_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P053_PFC_0A_CANTX0) + }, + { + .pin = BSP_IO_PORT_05_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P055_PFC_00_ETHSW_PHYLINK1) + }, + { + .pin = BSP_IO_PORT_05_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P057_PFC_00_ETH1_TXD2) + }, + { + .pin = BSP_IO_PORT_06_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P060_PFC_00_ETH1_TXD3) + }, + { + .pin = BSP_IO_PORT_06_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P061_PFC_00_ETH1_REFCLK) + }, + { + .pin = BSP_IO_PORT_06_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P062_PFC_00_ETH1_TXD1) + }, + { + .pin = BSP_IO_PORT_06_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P063_PFC_00_ETH1_TXD0) + }, + { + .pin = BSP_IO_PORT_06_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P064_PFC_00_ETH1_TXCLK) + }, + { + .pin = BSP_IO_PORT_06_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P065_PFC_00_ETH1_TXEN) + }, + { + .pin = BSP_IO_PORT_06_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P066_PFC_00_ETH1_RXD0) + }, + { + .pin = BSP_IO_PORT_06_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P067_PFC_00_ETH1_RXD1) + }, + { + .pin = BSP_IO_PORT_07_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P070_PFC_00_ETH1_RXD2) + }, + { + .pin = BSP_IO_PORT_07_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P071_PFC_00_ETH1_RXD3) + }, + { + .pin = BSP_IO_PORT_07_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P072_PFC_00_ETH1_RXDV) + }, + { + .pin = BSP_IO_PORT_07_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P073_PFC_00_ETH1_RXCLK) + }, + { + .pin = BSP_IO_PORT_07_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P074_PFC_02_USB_VBUSIN) + }, + { + .pin = BSP_IO_PORT_08_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_08_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P084_PFC_00_ETH0_RXD3) + }, + { + .pin = BSP_IO_PORT_08_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P085_PFC_00_ETH0_RXDV) + }, + { + .pin = BSP_IO_PORT_08_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P086_PFC_00_ETH0_RXCLK) + }, + { + .pin = BSP_IO_PORT_08_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P087_PFC_00_GMAC_MDC) + }, + { + .pin = BSP_IO_PORT_09_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P090_PFC_00_GMAC_MDIO) + }, + { + .pin = BSP_IO_PORT_09_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P091_PFC_00_ETH0_REFCLK) + }, + { + .pin = BSP_IO_PORT_09_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P093_PFC_00_ETH0_TXD3) + }, + { + .pin = BSP_IO_PORT_09_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P094_PFC_00_ETH0_TXD2) + }, + { + .pin = BSP_IO_PORT_09_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P095_PFC_00_ETH0_TXD1) + }, + { + .pin = BSP_IO_PORT_09_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P096_PFC_00_ETH0_TXD0) + }, + { + .pin = BSP_IO_PORT_09_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P097_PFC_00_ETH0_TXCLK) + }, + { + .pin = BSP_IO_PORT_10_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P100_PFC_00_ETH0_TXEN) + }, + { + .pin = BSP_IO_PORT_10_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P101_PFC_00_ETH0_RXD0) + }, + { + .pin = BSP_IO_PORT_10_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P102_PFC_00_ETH0_RXD1) + }, + { + .pin = BSP_IO_PORT_10_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P103_PFC_00_ETH0_RXD2) + }, + { + .pin = BSP_IO_PORT_10_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P104_PFC_01_ETHSW_PHYLINK0) + }, + { + .pin = BSP_IO_PORT_10_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_10_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_11_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_11_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_11_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_11_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_11_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P117_PFC_00_XSPI1_DS) + }, + { + .pin = BSP_IO_PORT_12_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P120_PFC_00_XSPI1_IO7) + }, + { + .pin = BSP_IO_PORT_12_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P121_PFC_00_XSPI1_IO6) + }, + { + .pin = BSP_IO_PORT_12_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P122_PFC_00_XSPI1_IO5) + }, + { + .pin = BSP_IO_PORT_12_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P123_PFC_00_XSPI1_IO4) + }, + { + .pin = BSP_IO_PORT_12_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P124_PFC_00_XSPI1_RESET0) + }, + { + .pin = BSP_IO_PORT_12_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P125_PFC_00_XSPI1_IO3) + }, + { + .pin = BSP_IO_PORT_12_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P126_PFC_01_XSPI1_IO2) + }, + { + .pin = BSP_IO_PORT_12_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P127_PFC_01_XSPI1_IO1) + }, + { + .pin = BSP_IO_PORT_13_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P130_PFC_00_XSPI1_IO0) + }, + { + .pin = BSP_IO_PORT_13_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P131_PFC_00_XSPI1_CS0) + }, + { + .pin = BSP_IO_PORT_13_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_13_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P133_PFC_00_XSPI1_CKP) + }, + { + .pin = BSP_IO_PORT_13_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P134_PFC_00_XSPI1_CKN) + }, + { + .pin = BSP_IO_PORT_13_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_14_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_14_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P142_PFC_01_XSPI0_ECS0) + }, + { + .pin = BSP_IO_PORT_14_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P144_PFC_00_XSPI0_DS) + }, + { + .pin = BSP_IO_PORT_14_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_14_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P146_PFC_00_XSPI0_CKP) + }, + { + .pin = BSP_IO_PORT_14_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P147_PFC_00_XSPI0_IO0) + }, + { + .pin = BSP_IO_PORT_15_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P150_PFC_00_XSPI0_IO1) + }, + { + .pin = BSP_IO_PORT_15_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P151_PFC_00_XSPI0_IO2) + }, + { + .pin = BSP_IO_PORT_15_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P152_PFC_00_XSPI0_IO3) + }, + { + .pin = BSP_IO_PORT_15_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P153_PFC_00_XSPI0_IO4) + }, + { + .pin = BSP_IO_PORT_15_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P154_PFC_00_XSPI0_IO5) + }, + { + .pin = BSP_IO_PORT_15_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P155_PFC_00_XSPI0_IO6) + }, + { + .pin = BSP_IO_PORT_15_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P156_PFC_00_XSPI0_IO7) + }, + { + .pin = BSP_IO_PORT_15_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P157_PFC_00_XSPI0_CS0) + }, + { + .pin = BSP_IO_PORT_16_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P161_PFC_00_XSPI0_RESET0) + }, + { + .pin = BSP_IO_PORT_16_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_16_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P165_PFC_01_TXD0_SDA0_MOSI0) + }, + { + .pin = BSP_IO_PORT_16_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P166_PFC_02_RXD0_SCL0_MISO0) + }, + { + .pin = BSP_IO_PORT_17_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P172_PFC_00_IRQ9) + }, + { + .pin = BSP_IO_PORT_17_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P175_PFC_05_USB_OVRCUR) + }, + { + .pin = BSP_IO_PORT_17_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P177_PFC_04_RXD3_SCL3_MISO3) + }, + { + .pin = BSP_IO_PORT_18_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P180_PFC_04_TXD3_SDA3_MOSI3) + }, + { + .pin = BSP_IO_PORT_18_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P184_PFC_03_SPI_RSPCK2) + }, + { + .pin = BSP_IO_PORT_18_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P185_PFC_03_SPI_MOSI2) + }, + { + .pin = BSP_IO_PORT_18_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P186_PFC_05_SPI_MISO2) + }, + { + .pin = BSP_IO_PORT_18_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_19_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P190_PFC_00_USB_VBUSEN) + }, + { + .pin = BSP_IO_PORT_19_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_19_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_19_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_19_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_20_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_20_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_20_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_20_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_20_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_20_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P205_PFC_02_IIC_SCL0) + }, + { + .pin = BSP_IO_PORT_20_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P206_PFC_02_IIC_SDA0) + }, + { + .pin = BSP_IO_PORT_20_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_21_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_21_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P211_PFC_00_TRACEDATA0) + }, + { + .pin = BSP_IO_PORT_21_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P212_PFC_00_TRACEDATA1) + }, + { + .pin = BSP_IO_PORT_21_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P213_PFC_00_TRACEDATA2) + }, + { + .pin = BSP_IO_PORT_21_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P214_PFC_00_TRACEDATA3) + }, + { + .pin = BSP_IO_PORT_21_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P215_PFC_01_TRACEDATA4) + }, + { + .pin = BSP_IO_PORT_21_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P217_PFC_01_TRACEDATA6) + }, + { + .pin = BSP_IO_PORT_22_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P220_PFC_01_TRACEDATA7) + }, + { + .pin = BSP_IO_PORT_22_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P221_PFC_00_TRACECTL) + }, + { + .pin = BSP_IO_PORT_22_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P222_PFC_01_TRACECLK) + }, + { + .pin = BSP_IO_PORT_22_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P226_PFC_02_IIC_SCL1) + }, + { + .pin = BSP_IO_PORT_22_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P227_PFC_02_IIC_SDA1) + }, + { + .pin = BSP_IO_PORT_23_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_23_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_HIGH) + }, + { + .pin = BSP_IO_PORT_23_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P237_PFC_00_ETH2_RXD0) + }, + { + .pin = BSP_IO_PORT_24_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P240_PFC_00_ETH2_RXD1) + }, + { + .pin = BSP_IO_PORT_24_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P241_PFC_00_ETH2_RXCLK) + }, + { + .pin = BSP_IO_PORT_24_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P242_PFC_00_ETH2_RXD2) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], + .p_extend = &g_ioport_cfg_extend, +}; diff --git a/bsp/renesas/rzt2m_rsk/rzt_gen/vector_data.c b/bsp/renesas/rzt2m_rsk/rzt_gen/vector_data.c new file mode 100644 index 00000000000..c02f2f69daf --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_gen/vector_data.c @@ -0,0 +1,12 @@ +/* generated vector source file - do not edit */ + #include "bsp_api.h" + /* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ + #if VECTOR_DATA_IRQ_COUNT > 0 + BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] = + { + [288] = sci_uart_eri_isr, /* SCI0_ERI (SCI0 Receive error) */ + [289] = sci_uart_rxi_isr, /* SCI0_RXI (SCI0 Receive data full) */ + [290] = sci_uart_txi_isr, /* SCI0_TXI (SCI0 Transmit data empty) */ + [291] = sci_uart_tei_isr, /* SCI0_TEI (SCI0 Transmit end) */ + }; + #endif \ No newline at end of file diff --git a/bsp/renesas/rzt2m_rsk/rzt_gen/vector_data.h b/bsp/renesas/rzt2m_rsk/rzt_gen/vector_data.h new file mode 100644 index 00000000000..852c5ecf779 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/rzt_gen/vector_data.h @@ -0,0 +1,50 @@ +/* generated vector header file - do not edit */ + #ifndef VECTOR_DATA_H + #define VECTOR_DATA_H + #include "bsp_api.h" + /* Number of interrupts allocated */ + #ifndef VECTOR_DATA_IRQ_COUNT + #define VECTOR_DATA_IRQ_COUNT (4) + #endif + /* ISR prototypes */ + void sci_uart_eri_isr(void); + void sci_uart_rxi_isr(void); + void sci_uart_txi_isr(void); + void sci_uart_tei_isr(void); + + /* Vector table allocations */ + #define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type) 288) /* SCI0_ERI (SCI0 Receive error) */ + #define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type) 289) /* SCI0_RXI (SCI0 Receive data full) */ + #define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type) 290) /* SCI0_TXI (SCI0 Transmit data empty) */ + #define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type) 291) /* SCI0_TEI (SCI0 Transmit end) */ + typedef enum IRQn { + SoftwareGeneratedInt0 = -32, + SoftwareGeneratedInt1 = -31, + SoftwareGeneratedInt2 = -30, + SoftwareGeneratedInt3 = -29, + SoftwareGeneratedInt4 = -28, + SoftwareGeneratedInt5 = -27, + SoftwareGeneratedInt6 = -26, + SoftwareGeneratedInt7 = -25, + SoftwareGeneratedInt8 = -24, + SoftwareGeneratedInt9 = -23, + SoftwareGeneratedInt10 = -22, + SoftwareGeneratedInt11 = -21, + SoftwareGeneratedInt12 = -20, + SoftwareGeneratedInt13 = -19, + SoftwareGeneratedInt14 = -18, + SoftwareGeneratedInt15 = -17, + DebugCommunicationsChannelInt = -10, + PerformanceMonitorCounterOverflowInt = -9, + CrossTriggerInterfaceInt = -8, + VritualCPUInterfaceMaintenanceInt = -7, + HypervisorTimerInt = -6, + VirtualTimerInt = -5, + NonSecurePhysicalTimerInt = -2, + SCI0_ERI_IRQn = 288, /* SCI0_ERI (SCI0 Receive error) */ + SCI0_RXI_IRQn = 289, /* SCI0_RXI (SCI0 Receive data full) */ + SCI0_TXI_IRQn = 290, /* SCI0_TXI (SCI0 Transmit data empty) */ + SCI0_TEI_IRQn = 291, /* SCI0_TEI (SCI0 Transmit end) */ + SHARED_PERIPHERAL_INTERRUPTS_MAX_ENTRIES = BSP_VECTOR_TABLE_MAX_ENTRIES + } IRQn_Type; + #endif /* VECTOR_DATA_H */ \ No newline at end of file diff --git a/bsp/renesas/rzt2m_rsk/script/fsp_xspi0_boot.icf b/bsp/renesas/rzt2m_rsk/script/fsp_xspi0_boot.icf new file mode 100644 index 00000000000..a3b329021e8 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/script/fsp_xspi0_boot.icf @@ -0,0 +1,726 @@ +include "memory_regions.icf"; + +/* The memory information for each device is done in memory regions file. + * The starting address and length of memory not defined in memory regions file are defined as 0. */ + +if (isdefinedsymbol(ATCM_START)) +{ + define symbol ATCM_PRV_START = ATCM_START; +} +else +{ + define symbol ATCM_PRV_START = 0; +} + +if (isdefinedsymbol(ATCM_LENGTH)) +{ + define symbol ATCM_PRV_LENGTH = ATCM_LENGTH; +} +else +{ + define symbol ATCM_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(BTCM_START)) +{ + define symbol BTCM_PRV_START = BTCM_START; +} +else +{ + define symbol BTCM_PRV_START = 0; +} + +if (isdefinedsymbol(BTCM_LENGTH)) +{ + define symbol BTCM_PRV_LENGTH = BTCM_LENGTH; +} +else +{ + define symbol BTCM_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_START)) +{ + define symbol SYSTEM_RAM_PRV_START = SYSTEM_RAM_START; +} +else +{ + define symbol SYSTEM_RAM_PRV_START = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_LENGTH)) +{ + define symbol SYSTEM_RAM_PRV_LENGTH = SYSTEM_RAM_LENGTH; +} +else +{ + define symbol SYSTEM_RAM_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_MIRROR_START)) +{ + define symbol SYSTEM_RAM_MIRROR_PRV_START = SYSTEM_RAM_MIRROR_START; +} +else +{ + define symbol SYSTEM_RAM_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_MIRROR_LENGTH)) +{ + define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = SYSTEM_RAM_MIRROR_LENGTH; +} +else +{ + define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_START)) +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = xSPI0_CS0_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS0_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_START)) +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = xSPI0_CS1_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS1_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_START)) +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = xSPI1_CS0_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS0_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_START)) +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = xSPI1_CS1_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS1_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS0_SPACE_MIRROR_START)) +{ + define symbol CS0_SPACE_MIRROR_PRV_START = CS0_SPACE_MIRROR_START; +} +else +{ + define symbol CS0_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS0_SPACE_MIRROR_LENGTH)) +{ + define symbol CS0_SPACE_MIRROR_PRV_LENGTH = CS0_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS0_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS2_SPACE_MIRROR_START)) +{ + define symbol CS2_SPACE_MIRROR_PRV_START = CS2_SPACE_MIRROR_START; +} +else +{ + define symbol CS2_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS2_SPACE_MIRROR_LENGTH)) +{ + define symbol CS2_SPACE_MIRROR_PRV_LENGTH = CS2_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS2_SPACE_MIRROR_PRV_LENGTH = 0; +} + + +if (isdefinedsymbol(CS3_SPACE_MIRROR_START)) +{ + define symbol CS3_SPACE_MIRROR_PRV_START = CS3_SPACE_MIRROR_START; +} +else +{ + define symbol CS3_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS3_SPACE_MIRROR_LENGTH)) +{ + define symbol CS3_SPACE_MIRROR_PRV_LENGTH = CS3_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS3_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS5_SPACE_MIRROR_START)) +{ + define symbol CS5_SPACE_MIRROR_PRV_START = CS5_SPACE_MIRROR_START; +} +else +{ + define symbol CS5_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS5_SPACE_MIRROR_LENGTH)) +{ + define symbol CS5_SPACE_MIRROR_PRV_LENGTH = CS5_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS5_SPACE_MIRROR_PRV_LENGTH = 0; +} + + +if (isdefinedsymbol(xSPI0_CS0_SPACE_START)) +{ + define symbol xSPI0_CS0_SPACE_PRV_START = xSPI0_CS0_SPACE_START; +} +else +{ + define symbol xSPI0_CS0_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS0_SPACE_LENGTH)) +{ + define symbol xSPI0_CS0_SPACE_PRV_LENGTH = xSPI0_CS0_SPACE_LENGTH; +} +else +{ + define symbol xSPI0_CS0_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_START)) +{ + define symbol xSPI0_CS1_SPACE_PRV_START = xSPI0_CS1_SPACE_START; +} +else +{ + define symbol xSPI0_CS1_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_LENGTH)) +{ + define symbol xSPI0_CS1_SPACE_PRV_LENGTH = xSPI0_CS1_SPACE_LENGTH; +} +else +{ + define symbol xSPI0_CS1_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_START)) +{ + define symbol xSPI1_CS0_SPACE_PRV_START = xSPI1_CS0_SPACE_START; +} +else +{ + define symbol xSPI1_CS0_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_LENGTH)) +{ + define symbol xSPI1_CS0_SPACE_PRV_LENGTH = xSPI1_CS0_SPACE_LENGTH; +} +else +{ + define symbol xSPI1_CS0_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_START)) +{ + define symbol xSPI1_CS1_SPACE_PRV_START = xSPI1_CS1_SPACE_START; +} +else +{ + define symbol xSPI1_CS1_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_LENGTH)) +{ + define symbol xSPI1_CS1_SPACE_PRV_LENGTH = xSPI1_CS1_SPACE_LENGTH; +} +else +{ + define symbol xSPI1_CS1_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS0_SPACE_START)) +{ + define symbol CS0_SPACE_PRV_START = CS0_SPACE_START; +} +else +{ + define symbol CS0_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS0_SPACE_LENGTH)) +{ + define symbol CS0_SPACE_PRV_LENGTH = CS0_SPACE_LENGTH; +} +else +{ + define symbol CS0_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS2_SPACE_START)) +{ + define symbol CS2_SPACE_PRV_START = CS2_SPACE_START; +} +else +{ + define symbol CS2_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS2_SPACE_LENGTH)) +{ + define symbol CS2_SPACE_PRV_LENGTH = CS2_SPACE_LENGTH; +} +else +{ + define symbol CS2_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS3_SPACE_START)) +{ + define symbol CS3_SPACE_PRV_START = CS3_SPACE_START; +} +else +{ + define symbol CS3_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS3_SPACE_LENGTH)) +{ + define symbol CS3_SPACE_PRV_LENGTH = CS3_SPACE_LENGTH; +} +else +{ + define symbol CS3_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS5_SPACE_START)) +{ + define symbol CS5_SPACE_PRV_START = CS5_SPACE_START; +} +else +{ + define symbol CS5_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS5_SPACE_LENGTH)) +{ + define symbol CS5_SPACE_PRV_LENGTH = CS5_SPACE_LENGTH; +} +else +{ + define symbol CS5_SPACE_PRV_LENGTH = 0; +} + +define symbol SYSTEM_RAM_END_OFFSET = 0x00070000; +define symbol tmp_flash_address = xSPI0_CS0_SPACE_PRV_START % 0x80000; +define symbol FLASH_ADDRESS = (0 == tmp_flash_address) ? xSPI0_CS0_SPACE_PRV_START : xSPI0_CS0_SPACE_PRV_START + (0x80000 - tmp_flash_address); + +if (isdefinedsymbol(CR52_0)) +{ + define symbol INTVEC_ADDRESS = ATCM_PRV_START; + define symbol RAM_ADDRESS = (ATCM_PRV_START + 0x100); + define symbol RAM_END_ADDRESS = (ATCM_PRV_START + ATCM_PRV_LENGTH - 1); + define symbol LOADER_STACK_ADDRESS = (BTCM_PRV_START + 0x2000); + define symbol LOADER_STACK_END_ADDRESS = (BTCM_PRV_START + BTCM_PRV_LENGTH - 1); + define symbol DATA_NONCACHE_OFFSET = 0x00070000; + define symbol DATA_NONCACHE_END_OFFSET = 0x0006C000; + define symbol DMAC_LINK_MODE_OFFSET = 0x00068000; + define symbol DMAC_LINK_MODE_END_OFFSET = 0x00064000; + define symbol NONCACHE_BUFFER_OFFSET = 0x00040000; + define symbol NONCACHE_BUFFER_END_OFFSET = 0x00020000; +} +else +{ + + define symbol INTVEC_ADDRESS = SYSTEM_RAM_PRV_START; + define symbol LOADER_STACK_ADDRESS = (SYSTEM_RAM_PRV_START + 0x10000); + define symbol LOADER_STACK_END_ADDRESS = (SYSTEM_RAM_PRV_START + SYSTEM_RAM_PRV_LENGTH - 1); + define symbol RAM_ADDRESS = (SYSTEM_RAM_PRV_START + 0x20000); + define symbol RAM_END_ADDRESS = (SYSTEM_RAM_PRV_START + SYSTEM_RAM_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1); + define symbol DATA_NONCACHE_OFFSET = 0x0006C000; + define symbol DATA_NONCACHE_END_OFFSET = 0x00068000; + define symbol DMAC_LINK_MODE_OFFSET = 0x00064000; + define symbol DMAC_LINK_MODE_END_OFFSET = 0x00060000; + define symbol NONCACHE_BUFFER_OFFSET = 0x00020000; + define symbol NONCACHE_BUFFER_END_OFFSET = 0; +} + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = INTVEC_ADDRESS; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = FLASH_ADDRESS + 0x20100; +define symbol __ICFEDIT_region_ROM_end__ = FLASH_ADDRESS + 0x6FFFF; +define symbol __ICFEDIT_region_RAM_start__ = RAM_ADDRESS; +define symbol __ICFEDIT_region_RAM_end__ = RAM_END_ADDRESS; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define symbol __region_D_LOADER_STACK_start__ = LOADER_STACK_ADDRESS; +define symbol __region_D_LOADER_STACK_end__ = LOADER_STACK_END_ADDRESS; + +define symbol __region_DATA_NONCACHE_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_OFFSET; +define symbol __region_DATA_NONCACHE_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_END_OFFSET - 1; +define symbol __region_DMAC_LINK_MODE_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_OFFSET; +define symbol __region_DMAC_LINK_MODE_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_END_OFFSET - 1; +define symbol __region_SHARED_NONCACHE_BUFFER_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00060000; +define symbol __region_SHARED_NONCACHE_BUFFER_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00040000 - 1; +define symbol __region_NONCACHE_BUFFER_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_OFFSET; +define symbol __region_NONCACHE_BUFFER_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_END_OFFSET - 1; + +define symbol __region_ATCM_start__ = ATCM_PRV_START; +define symbol __region_ATCM_end__ = ATCM_PRV_START + ATCM_PRV_LENGTH - 1; +define symbol __region_BTCM_start__ = BTCM_PRV_START; +define symbol __region_BTCM_end__ = BTCM_PRV_START + BTCM_PRV_LENGTH - 1; +define symbol __region_SYSTEM_RAM_start__ = SYSTEM_RAM_PRV_START; +define symbol __region_SYSTEM_RAM_end__ = SYSTEM_RAM_PRV_START + SYSTEM_RAM_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1; +define symbol __region_SYSTEM_RAM_MIRROR_start__ = SYSTEM_RAM_MIRROR_PRV_START; +define symbol __region_SYSTEM_RAM_MIRROR_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1; + +define symbol __region_XSPI0_CS0_MIRROR_start__ = xSPI0_CS0_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI0_CS0_MIRROR_end__ = xSPI0_CS0_SPACE_MIRROR_PRV_START + xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI0_CS1_MIRROR_start__ = xSPI0_CS1_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI0_CS1_MIRROR_end__ = xSPI0_CS1_SPACE_MIRROR_PRV_START + xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS0_MIRROR_start__ = xSPI1_CS0_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI1_CS0_MIRROR_end__ = xSPI1_CS0_SPACE_MIRROR_PRV_START + xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS1_MIRROR_start__ = xSPI1_CS1_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI1_CS1_MIRROR_end__ = xSPI1_CS1_SPACE_MIRROR_PRV_START + xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS0_MIRROR_start__ = CS0_SPACE_MIRROR_PRV_START; +define symbol __region_CS0_MIRROR_end__ = CS0_SPACE_MIRROR_PRV_START + CS0_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS2_MIRROR_start__ = CS2_SPACE_MIRROR_PRV_START; +define symbol __region_CS2_MIRROR_end__ = CS2_SPACE_MIRROR_PRV_START + CS2_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS3_MIRROR_start__ = CS3_SPACE_MIRROR_PRV_START; +define symbol __region_CS3_MIRROR_end__ = CS3_SPACE_MIRROR_PRV_START + CS3_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS5_MIRROR_start__ = CS5_SPACE_MIRROR_PRV_START; +define symbol __region_CS5_MIRROR_end__ = CS5_SPACE_MIRROR_PRV_START + CS5_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI0_CS0_start__ = xSPI0_CS0_SPACE_PRV_START; +define symbol __region_XSPI0_CS0_end__ = xSPI0_CS0_SPACE_PRV_START + xSPI0_CS0_SPACE_PRV_LENGTH - 1; +define symbol __region_XSPI0_CS1_start__ = xSPI0_CS1_SPACE_PRV_START; +define symbol __region_XSPI0_CS1_end__ = xSPI0_CS1_SPACE_PRV_START + xSPI0_CS1_SPACE_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS0_start__ = xSPI1_CS0_SPACE_PRV_START; +define symbol __region_XSPI1_CS0_end__ = xSPI1_CS0_SPACE_PRV_START + xSPI1_CS0_SPACE_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS1_start__ = xSPI1_CS1_SPACE_PRV_START; +define symbol __region_XSPI1_CS1_end__ = xSPI1_CS1_SPACE_PRV_START + xSPI1_CS1_SPACE_PRV_LENGTH - 1; +define symbol __region_CS0_start__ = CS0_SPACE_PRV_START; +define symbol __region_CS0_end__ = CS0_SPACE_PRV_START + CS0_SPACE_PRV_LENGTH - 1; +define symbol __region_CS2_start__ = CS2_SPACE_PRV_START; +define symbol __region_CS2_end__ = CS2_SPACE_PRV_START + CS2_SPACE_PRV_LENGTH - 1; +define symbol __region_CS3_start__ = CS3_SPACE_PRV_START; +define symbol __region_CS3_end__ = CS3_SPACE_PRV_START + CS3_SPACE_PRV_LENGTH - 1; +define symbol __region_CS5_start__ = CS5_SPACE_PRV_START; +define symbol __region_CS5_end__ = CS5_SPACE_PRV_START + CS5_SPACE_PRV_LENGTH - 1; + +/************** SPI boot mode setting **************/ +define symbol __region_LDR_PARAM_start__ = FLASH_ADDRESS; +define symbol __region_LDR_PARAM_end__ = FLASH_ADDRESS + 0x0000004B; +define symbol __region_S_LOADER_STACK_start__ = FLASH_ADDRESS + 0x0000004C; +define symbol __region_S_LOADER_STACK_end__ = FLASH_ADDRESS + 0x0000804B; + +define symbol __region_S_intvec_start__ = FLASH_ADDRESS + 0x20000; +define symbol __region_S_intvec_end__ = FLASH_ADDRESS + 0x200FF; +define symbol __region_S_RAM_start__ = FLASH_ADDRESS + 0x70000; +define symbol __region_S_RAM_end__ = FLASH_ADDRESS + 0x7FFFF; + +define symbol __region_SECONDARY_start__ = FLASH_ADDRESS + 0x80000; +define symbol __region_SECONDARY_end__ = FLASH_ADDRESS + 0xFFFFF; +/****************************************************/ + +define exported symbol __ddsc_xSPI0_CS0_SPACE_START = FLASH_ADDRESS; + +define region SECONDARY_region = mem:[from __region_SECONDARY_start__ to __region_SECONDARY_end__]; + +define region D_LOADER_STACK_region = mem:[from __region_D_LOADER_STACK_start__ to __region_D_LOADER_STACK_end__]; + +define region LDR_PARAM_region = mem:[from __region_LDR_PARAM_start__ to __region_LDR_PARAM_end__]; +define region S_LOADER_STACK_region = mem:[from __region_S_LOADER_STACK_start__ to __region_S_LOADER_STACK_end__]; + +define region S_intvec_region = mem:[from __region_S_intvec_start__ to __region_S_intvec_end__]; +define region S_RAM_region = mem:[from __region_S_RAM_start__ to __region_S_RAM_end__]; + +define region DATA_NONCACHE_region = mem:[from __region_DATA_NONCACHE_start__ to __region_DATA_NONCACHE_end__]; +define region DMAC_LINK_MODE_region = mem:[from __region_DMAC_LINK_MODE_start__ to __region_DMAC_LINK_MODE_end__]; +define region SHARED_NONCACHE_BUFFER_region = mem:[from __region_SHARED_NONCACHE_BUFFER_start__ to __region_SHARED_NONCACHE_BUFFER_end__]; +define region NONCACHE_BUFFER_region = mem:[from __region_NONCACHE_BUFFER_start__ to __region_NONCACHE_BUFFER_end__]; + +define region ATCM_region = mem:[from __region_ATCM_start__ to __region_ATCM_end__ ]; +define region BTCM_region = mem:[from __region_BTCM_start__ to __region_BTCM_end__ ]; +define region SYSTEM_RAM_region = mem:[from __region_SYSTEM_RAM_start__ to __region_SYSTEM_RAM_end__ ]; +define region SYSTEM_RAM_MIRROR_region = mem:[from __region_SYSTEM_RAM_MIRROR_start__ to __region_SYSTEM_RAM_MIRROR_end__ ]; +define region XSPI0_CS0_MIRROR_region = mem:[from __region_XSPI0_CS0_MIRROR_start__ to __region_XSPI0_CS0_MIRROR_end__ ]; +define region XSPI0_CS1_MIRROR_region = mem:[from __region_XSPI0_CS1_MIRROR_start__ to __region_XSPI0_CS1_MIRROR_end__ ]; +define region XSPI1_CS0_MIRROR_region = mem:[from __region_XSPI1_CS0_MIRROR_start__ to __region_XSPI1_CS0_MIRROR_end__ ]; +define region XSPI1_CS1_MIRROR_region = mem:[from __region_XSPI1_CS1_MIRROR_start__ to __region_XSPI1_CS1_MIRROR_end__ ]; +define region CS0_MIRROR_region = mem:[from __region_CS0_MIRROR_start__ to __region_CS0_MIRROR_end__ ]; +define region CS2_MIRROR_region = mem:[from __region_CS2_MIRROR_start__ to __region_CS2_MIRROR_end__ ]; +define region CS3_MIRROR_region = mem:[from __region_CS3_MIRROR_start__ to __region_CS3_MIRROR_end__ ]; +define region CS5_MIRROR_region = mem:[from __region_CS5_MIRROR_start__ to __region_CS5_MIRROR_end__ ]; +define region XSPI0_CS0_region = mem:[from __region_XSPI0_CS0_start__ to __region_XSPI0_CS0_end__ ]; +define region XSPI0_CS1_region = mem:[from __region_XSPI0_CS1_start__ to __region_XSPI0_CS1_end__ ]; +define region XSPI1_CS0_region = mem:[from __region_XSPI1_CS0_start__ to __region_XSPI1_CS0_end__ ]; +define region XSPI1_CS1_region = mem:[from __region_XSPI1_CS1_start__ to __region_XSPI1_CS1_end__ ]; +define region CS0_region = mem:[from __region_CS0_start__ to __region_CS0_end__ ]; +define region CS2_region = mem:[from __region_CS2_start__ to __region_CS2_end__ ]; +define region CS3_region = mem:[from __region_CS3_start__ to __region_CS3_end__ ]; +define region CS5_region = mem:[from __region_CS5_start__ to __region_CS5_end__ ]; + +/**************** RT-THREAD CINFIG *******************/ +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +/****************************************************/ + +define block LDR_PRG_RBLOCK with fixed order + { ro code section .loader_text_init object startup_core.o, + ro code object startup_core.o, + ro code object system_core.o, + ro code object startup.o, + ro code object system.o, + ro code object bsp_clocks.o, + ro code object bsp_irq_core.o, + ro code object bsp_irq.o, + ro code object bsp_semaphore.o, + ro code object bsp_register_protection.o, + ro code object r_ioport.o, + ro code object bsp_cache.o, + ro code section .warm_start_init } + except { ro code section .intvec_init, + ro code section .reset_handler_init }; +define block LDR_PRG_WBLOCK with fixed order + { rw code section .loader_text object startup_core.o, + rw code object startup_core.o, + rw code object system_core.o, + rw code object startup.o, + rw code object system.o, + rw code object bsp_clocks.o, + rw code object bsp_irq_core.o, + rw code object bsp_irq.o, + rw code object bsp_semaphore.o, + rw code object bsp_register_protection.o, + rw code object r_ioport.o, + rw code object bsp_cache.o, + rw code section .warm_start } + except { rw code section .intvec, + rw code section .reset_handler }; +define block LDR_DATA_ZBLOCK with alignment = 4 + { section .bss object startup_core.o, + section .bss object system_core.o, + section .bss object startup.o, + section .bss object system.o, + section .bss object bsp_clocks.o, + section .bss object bsp_irq_core.o, + section .bss object bsp_irq.o, + section .bss object bsp_semaphore.o, + section .bss object bsp_register_protection.o, + section .bss object r_ioport.o, + section .bss object bsp_cache.o, + section .bss object bsp_io.o }; +define block LDR_DATA_RBLOCK with fixed order, alignment = 4 + { section .data_init object startup_core.o, + section .data_init object system_core.o, + section .data_init object startup.o, + section .data_init object system.o, + section .data_init object bsp_clocks.o, + section .data_init object bsp_irq_core.o, + section .data_init object bsp_irq.o, + section .data_init object bsp_semaphore.o, + section .data_init object bsp_register_protection.o, + section .data_init object r_ioport.o, + section .data_init object bsp_cache.o, + section .rodata_init object system_core.o }; +define block LDR_DATA_WBLOCK with fixed order, alignment = 4 + { section .data object startup_core.o, + section .data object system_core.o, + section .data object startup.o, + section .data object system.o, + section .data object bsp_clocks.o, + section .data object bsp_irq_core.o, + section .data object bsp_irq.o, + section .data object bsp_semaphore.o, + section .data object bsp_register_protection.o, + section .data object r_ioport.o, + section .data object bsp_cache.o, + section .rodata object system_core.o }; + +define block HEAP_BLOCK with alignment = 8 { rw section HEAP }; +define block THREAD_STACK with alignment = 8 { rw section .stack* }; +define block SYS_STACK with alignment = 8 { rw section .sys_stack }; +define block SVC_STACK with alignment = 8 { rw section .svc_stack }; +define block IRQ_STACK with alignment = 8 { rw section .irq_stack }; +define block FIQ_STACK with alignment = 8 { rw section .fiq_stack }; +define block UND_STACK with alignment = 8 { rw section .und_stack }; +define block ABT_STACK with alignment = 8 { rw section .abt_stack }; + +define block VECTOR_RBLOCK with alignment = 32 { ro code section .intvec_init}; +define block VECTOR_WBLOCK with alignment = 32 { rw code section .intvec}; +define block USER_PRG_RBLOCK with alignment = 4 { ro code }; +define block USER_PRG_WBLOCK with alignment = 4 { rw code }; +define block USER_DATA_ZBLOCK with alignment = 4 { section .bss }; +define block USER_DATA_RBLOCK with fixed order, alignment = 4 + { section .data_init, + section __DLIB_PERTHREAD_init, + section .rodata_init, + section .version_init }; +define block USER_DATA_WBLOCK with fixed order, alignment = 4 + { section .data, + section __DLIB_PERTHREAD, + section .rodata, + section .version }; +define block USER_DATA_NONCACHE_RBLOCK with alignment = 4 { section .data_noncache_init }; +define block USER_DATA_NONCACHE_WBLOCK with alignment = 4 { section .data_noncache }; +define block DMAC_LINK_MODE_ZBLOCK with alignment = 4 { section .dmac_link_mode* }; +define block SHARED_NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .shared_noncache_buffer* }; +define block NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .noncache_buffer* }; + +define block xSPI0_CS0_SPACE_END_block { section .ddsc_xspi0_cs0_space_end }; +define block xSPI0_CS0_SPACE_ALIGNMENT_block with alignment = 0x20000 {}; + +define block SECONDARY_RBLOCK { section SECONDARY }; + +initialize manually { ro code object startup_core.o, + ro code object system_core.o, + ro code object startup.o, + ro code object system.o, + ro code object bsp_clocks.o, + ro code object bsp_irq_core.o, + ro code object bsp_irq.o, + ro code object bsp_semaphore.o, + ro code object bsp_register_protection.o, + ro code object r_ioport.o, + ro code object bsp_cache.o, + ro code section .intvec, + ro code section .reset_handler, + ro code section .warm_start, + ro code, + section .data, + section __DLIB_PERTHREAD, + section .rodata, + section .version, + section .data_noncache }; + +do not initialize { section .noinit, + section .bss, + section .dmac_link_mode*, + section .shared_noncache_buffer*, + section .noncache_buffer*, + rw section HEAP, + rw section .stack*, + rw section .sys_stack, + rw section .svc_stack, + rw section .irq_stack, + rw section .fiq_stack, + rw section .und_stack, + rw section .abt_stack }; + +place at address mem: __ICFEDIT_intvec_start__ { block VECTOR_WBLOCK }; + +place in LDR_PARAM_region { readonly section .loader_param }; +place at start of S_LOADER_STACK_region { block LDR_PRG_RBLOCK }; +place in S_LOADER_STACK_region { section LDR_DATA_RBLOCK, block LDR_DATA_RBLOCK }; +place in S_intvec_region { block VECTOR_RBLOCK }; +place in ROM_region { block USER_PRG_RBLOCK, readonly }; +place in S_RAM_region { readonly section .image_info }; +place in S_RAM_region { block USER_DATA_RBLOCK, block USER_DATA_NONCACHE_RBLOCK, block xSPI0_CS0_SPACE_END_block, last block xSPI0_CS0_SPACE_ALIGNMENT_block }; + +place at start of D_LOADER_STACK_region { block LDR_PRG_WBLOCK }; +place in D_LOADER_STACK_region { section LDR_DATA_WBLOCK, block LDR_DATA_WBLOCK, + section LDR_DATA_ZBLOCK, block LDR_DATA_ZBLOCK }; +place in D_LOADER_STACK_region { section SYS_STACK, block SYS_STACK, + section SVC_STACK, block SVC_STACK, + section IRQ_STACK, block IRQ_STACK, + section FIQ_STACK, block FIQ_STACK, + section UND_STACK, block UND_STACK, + section ABT_STACK, block ABT_STACK }; +place in RAM_region { block USER_PRG_WBLOCK }; +place in RAM_region { readwrite }; +place in RAM_region { block USER_DATA_WBLOCK, + block USER_DATA_ZBLOCK, + block CSTACK }; +place in RAM_region { section HEAP_BLOCK, block HEAP_BLOCK, + section THREAD_STACK, block THREAD_STACK }; + +place in DATA_NONCACHE_region { block USER_DATA_NONCACHE_WBLOCK }; +place in DMAC_LINK_MODE_region { block DMAC_LINK_MODE_ZBLOCK }; +place in SHARED_NONCACHE_BUFFER_region { block SHARED_NONCACHE_BUFFER_ZBLOCK }; +place in NONCACHE_BUFFER_region { block NONCACHE_BUFFER_ZBLOCK }; +place in ATCM_region { }; +place in BTCM_region { }; +place in SYSTEM_RAM_region { }; +place in SYSTEM_RAM_MIRROR_region { }; +place in XSPI0_CS0_MIRROR_region { }; +place in XSPI0_CS1_MIRROR_region { }; +place in XSPI1_CS0_MIRROR_region { }; +place in XSPI1_CS1_MIRROR_region { }; +place in CS0_MIRROR_region { }; +place in CS2_MIRROR_region { }; +place in CS3_MIRROR_region { }; +place in CS5_MIRROR_region { }; +place in XSPI0_CS0_region { }; +place in XSPI0_CS1_region { }; +place in XSPI1_CS0_region { }; +place in XSPI1_CS1_region { }; +place in CS0_region { }; +place in CS2_region { }; +place in CS3_region { }; +place in CS5_region { }; +place in SECONDARY_region { block SECONDARY_RBLOCK }; \ No newline at end of file diff --git a/bsp/renesas/rzt2m_rsk/script/fsp_xspi0_boot.ld b/bsp/renesas/rzt2m_rsk/script/fsp_xspi0_boot.ld new file mode 100644 index 00000000000..84b90b766c6 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/script/fsp_xspi0_boot.ld @@ -0,0 +1,435 @@ +/* + Linker File for Renesas RZ/T2 FSP +*/ + +INCLUDE memory_regions.ld + +/* The memory information for each device is done in memory regions file. + * The starting address and length of memory not defined in memory regions file are defined as 0. */ + +ATCM_PRV_START = DEFINED(ATCM_START) ? ATCM_START : 0; +ATCM_PRV_LENGTH = DEFINED(ATCM_LENGTH) ? ATCM_LENGTH : 0; +BTCM_PRV_START = DEFINED(BTCM_START) ? BTCM_START : 0; +BTCM_PRV_LENGTH = DEFINED(BTCM_LENGTH) ? BTCM_LENGTH : 0; +SYSTEM_RAM_PRV_START = DEFINED(SYSTEM_RAM_START) ? SYSTEM_RAM_START : 0; +SYSTEM_RAM_PRV_LENGTH = DEFINED(SYSTEM_RAM_LENGTH) ? SYSTEM_RAM_LENGTH : 0; +SYSTEM_RAM_MIRROR_PRV_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START : 0; +SYSTEM_RAM_MIRROR_PRV_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? SYSTEM_RAM_MIRROR_LENGTH : 0; +xSPI0_CS0_SPACE_MIRROR_PRV_START = DEFINED(xSPI0_CS0_SPACE_MIRROR_START) ? xSPI0_CS0_SPACE_MIRROR_START : 0; +xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI0_CS0_SPACE_MIRROR_LENGTH) ? xSPI0_CS0_SPACE_MIRROR_LENGTH : 0; +xSPI0_CS1_SPACE_MIRROR_PRV_START = DEFINED(xSPI0_CS1_SPACE_MIRROR_START) ? xSPI0_CS1_SPACE_MIRROR_START : 0; +xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI0_CS1_SPACE_MIRROR_LENGTH) ? xSPI0_CS1_SPACE_MIRROR_LENGTH : 0; +xSPI1_CS0_SPACE_MIRROR_PRV_START = DEFINED(xSPI1_CS0_SPACE_MIRROR_START) ? xSPI1_CS0_SPACE_MIRROR_START : 0; +xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI1_CS0_SPACE_MIRROR_LENGTH) ? xSPI1_CS0_SPACE_MIRROR_LENGTH : 0; +xSPI1_CS1_SPACE_MIRROR_PRV_START = DEFINED(xSPI1_CS1_SPACE_MIRROR_START) ? xSPI1_CS1_SPACE_MIRROR_START : 0; +xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI1_CS1_SPACE_MIRROR_LENGTH) ? xSPI1_CS1_SPACE_MIRROR_LENGTH : 0; +CS0_SPACE_MIRROR_PRV_START = DEFINED(CS0_SPACE_MIRROR_START) ? CS0_SPACE_MIRROR_START : 0; +CS0_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS0_SPACE_MIRROR_LENGTH) ? CS0_SPACE_MIRROR_LENGTH : 0; +CS2_SPACE_MIRROR_PRV_START = DEFINED(CS2_SPACE_MIRROR_START) ? CS2_SPACE_MIRROR_START : 0; +CS2_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS2_SPACE_MIRROR_LENGTH) ? CS2_SPACE_MIRROR_LENGTH : 0; +CS3_SPACE_MIRROR_PRV_START = DEFINED(CS3_SPACE_MIRROR_START) ? CS3_SPACE_MIRROR_START : 0; +CS3_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS3_SPACE_MIRROR_LENGTH) ? CS3_SPACE_MIRROR_LENGTH : 0; +CS5_SPACE_MIRROR_PRV_START = DEFINED(CS5_SPACE_MIRROR_START) ? CS5_SPACE_MIRROR_START : 0; +CS5_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS5_SPACE_MIRROR_LENGTH) ? CS5_SPACE_MIRROR_LENGTH : 0; +xSPI0_CS0_SPACE_PRV_START = DEFINED(xSPI0_CS0_SPACE_START) ? xSPI0_CS0_SPACE_START : 0; +xSPI0_CS0_SPACE_PRV_LENGTH = DEFINED(xSPI0_CS0_SPACE_LENGTH) ? xSPI0_CS0_SPACE_LENGTH : 0; +xSPI0_CS1_SPACE_PRV_START = DEFINED(xSPI0_CS1_SPACE_START) ? xSPI0_CS1_SPACE_START : 0; +xSPI0_CS1_SPACE_PRV_LENGTH = DEFINED(xSPI0_CS1_SPACE_LENGTH) ? xSPI0_CS1_SPACE_LENGTH : 0; +xSPI1_CS0_SPACE_PRV_START = DEFINED(xSPI1_CS0_SPACE_START) ? xSPI1_CS0_SPACE_START : 0; +xSPI1_CS0_SPACE_PRV_LENGTH = DEFINED(xSPI1_CS0_SPACE_LENGTH) ? xSPI1_CS0_SPACE_LENGTH : 0; +xSPI1_CS1_SPACE_PRV_START = DEFINED(xSPI1_CS1_SPACE_START) ? xSPI1_CS1_SPACE_START : 0; +xSPI1_CS1_SPACE_PRV_LENGTH = DEFINED(xSPI1_CS1_SPACE_LENGTH) ? xSPI1_CS1_SPACE_LENGTH : 0; +CS0_SPACE_PRV_START = DEFINED(CS0_SPACE_START) ? CS0_SPACE_START : 0; +CS0_SPACE_PRV_LENGTH = DEFINED(CS0_SPACE_LENGTH) ? CS0_SPACE_LENGTH : 0; +CS2_SPACE_PRV_START = DEFINED(CS2_SPACE_START) ? CS2_SPACE_START : 0; +CS2_SPACE_PRV_LENGTH = DEFINED(CS2_SPACE_LENGTH) ? CS2_SPACE_LENGTH : 0; +CS3_SPACE_PRV_START = DEFINED(CS3_SPACE_START) ? CS3_SPACE_START : 0; +CS3_SPACE_PRV_LENGTH = DEFINED(CS3_SPACE_LENGTH) ? CS3_SPACE_LENGTH : 0; +CS5_SPACE_PRV_START = DEFINED(CS5_SPACE_START) ? CS5_SPACE_START : 0; +CS5_SPACE_PRV_LENGTH = DEFINED(CS5_SPACE_LENGTH) ? CS5_SPACE_LENGTH : 0; + +LOADER_PARAM_ADDRESS = ALIGN(xSPI0_CS0_SPACE_PRV_START, 0x00020000); +FLASH_CONTENTS_ADDRESS = LOADER_PARAM_ADDRESS + 0x0000004C; +LOADER_TEXT_ADDRESS = DEFINED(CR52_0) ? 0x00102000 : 0x10010000; +INTVEC_ADDRESS = DEFINED(CR52_0) ? 0x00000000 : 0x10000000; +TEXT_ADDRESS = DEFINED(CR52_0) ? 0x00000100 : 0x10020000; +NONCACHE_BUFFER_OFFSET = DEFINED(CR52_0) ? 0x00040000 : 0x00020000; +DMAC_LINK_MODE_OFFSET = DEFINED(CR52_0) ? 0x00068000 : 0x00064000; +DATA_NONCACHE_OFFSET = DEFINED(CR52_0) ? 0x00070000 : 0x0006C000; +RAM_START = DEFINED(CR52_0) ? ATCM_PRV_START : SYSTEM_RAM_PRV_START; +RAM_LENGTH = DEFINED(CR52_0) ? ATCM_PRV_LENGTH : SYSTEM_RAM_PRV_LENGTH; +LOADER_START = DEFINED(CR52_0) ? BTCM_PRV_START : SYSTEM_RAM_PRV_START; +LOADER_LENGTH = DEFINED(CR52_0) ? BTCM_PRV_LENGTH : SYSTEM_RAM_PRV_LENGTH; + +/* Define starting addresses and length for data_noncache, DMAC link mode data, CPU-shared non-cache, and CPU-specific non-cache areas. */ +DATA_NONCACHE_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START + SYSTEM_RAM_MIRROR_LENGTH - DATA_NONCACHE_OFFSET : 0; +DATA_NONCACHE_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? 0x00004000 : 0; +DMAC_LINK_MODE_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START + SYSTEM_RAM_MIRROR_LENGTH - DMAC_LINK_MODE_OFFSET : 0; +DMAC_LINK_MODE_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? 0x00004000 : 0; +SHARED_NONCACHE_BUFFER_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START + SYSTEM_RAM_MIRROR_LENGTH - 0x00060000 : 0; +SHARED_NONCACHE_BUFFER_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? 0x00020000 : 0; +NONCACHE_BUFFER_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START + SYSTEM_RAM_MIRROR_LENGTH - NONCACHE_BUFFER_OFFSET : 0; +NONCACHE_BUFFER_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? 0x00020000 : 0; + +MEMORY +{ + ATCM : ORIGIN = ATCM_PRV_START, LENGTH = ATCM_PRV_LENGTH + BTCM : ORIGIN = BTCM_PRV_START, LENGTH = BTCM_PRV_LENGTH + SYSTEM_RAM : ORIGIN = SYSTEM_RAM_PRV_START, LENGTH = SYSTEM_RAM_PRV_LENGTH + SYSTEM_RAM_MIRROR : ORIGIN = SYSTEM_RAM_MIRROR_PRV_START, LENGTH = SYSTEM_RAM_MIRROR_PRV_LENGTH + xSPI0_CS0_SPACE_MIRROR : ORIGIN = xSPI0_CS0_SPACE_MIRROR_PRV_START, LENGTH = xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH + xSPI0_CS1_SPACE_MIRROR : ORIGIN = xSPI0_CS1_SPACE_MIRROR_PRV_START, LENGTH = xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH + xSPI1_CS0_SPACE_MIRROR : ORIGIN = xSPI1_CS0_SPACE_MIRROR_PRV_START, LENGTH = xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH + xSPI1_CS1_SPACE_MIRROR : ORIGIN = xSPI1_CS1_SPACE_MIRROR_PRV_START, LENGTH = xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH + CS0_SPACE_MIRROR : ORIGIN = CS0_SPACE_MIRROR_PRV_START, LENGTH = CS0_SPACE_MIRROR_PRV_LENGTH + CS2_SPACE_MIRROR : ORIGIN = CS2_SPACE_MIRROR_PRV_START, LENGTH = CS2_SPACE_MIRROR_PRV_LENGTH + CS3_SPACE_MIRROR : ORIGIN = CS3_SPACE_MIRROR_PRV_START, LENGTH = CS3_SPACE_MIRROR_PRV_LENGTH + CS5_SPACE_MIRROR : ORIGIN = CS5_SPACE_MIRROR_PRV_START, LENGTH = CS5_SPACE_MIRROR_PRV_LENGTH + xSPI0_CS0_SPACE : ORIGIN = xSPI0_CS0_SPACE_PRV_START, LENGTH = xSPI0_CS0_SPACE_PRV_LENGTH + xSPI0_CS1_SPACE : ORIGIN = xSPI0_CS1_SPACE_PRV_START, LENGTH = xSPI0_CS1_SPACE_PRV_LENGTH + xSPI1_CS0_SPACE : ORIGIN = xSPI1_CS0_SPACE_PRV_START, LENGTH = xSPI1_CS0_SPACE_PRV_LENGTH + xSPI1_CS1_SPACE : ORIGIN = xSPI1_CS1_SPACE_PRV_START, LENGTH = xSPI1_CS1_SPACE_PRV_LENGTH + CS0_SPACE : ORIGIN = CS0_SPACE_PRV_START, LENGTH = CS0_SPACE_PRV_LENGTH + CS2_SPACE : ORIGIN = CS2_SPACE_PRV_START, LENGTH = CS2_SPACE_PRV_LENGTH + CS3_SPACE : ORIGIN = CS3_SPACE_PRV_START, LENGTH = CS3_SPACE_PRV_LENGTH + CS5_SPACE : ORIGIN = CS5_SPACE_PRV_START, LENGTH = CS5_SPACE_PRV_LENGTH + RAM : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + LOADER_STACK : ORIGIN = LOADER_START, LENGTH = LOADER_LENGTH + DUMMY : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_NONCACHE : ORIGIN = DATA_NONCACHE_START, LENGTH = DATA_NONCACHE_LENGTH + DMAC_LINK_MODE : ORIGIN = DMAC_LINK_MODE_START, LENGTH = DMAC_LINK_MODE_LENGTH + SHARED_NONCACHE_BUFFER : ORIGIN = SHARED_NONCACHE_BUFFER_START, LENGTH = SHARED_NONCACHE_BUFFER_LENGTH + NONCACHE_BUFFER : ORIGIN = NONCACHE_BUFFER_START, LENGTH = NONCACHE_BUFFER_LENGTH +} + +SECTIONS +{ + .loader_param LOADER_PARAM_ADDRESS : AT (LOADER_PARAM_ADDRESS) + { + KEEP(*(.loader_param)) + } > xSPI0_CS0_SPACE + .flash_contents FLASH_CONTENTS_ADDRESS : AT (FLASH_CONTENTS_ADDRESS) + { + _mloader_text = .; + . = . + (_loader_text_end - _loader_text_start); + _mloader_data = .; + . = . + (_loader_data_end - _loader_data_start); + _mfvector = .; + . = . + (_fvector_end - _fvector_start); + _mtext = .; + . = . + (_text_end - _text_start); + _mdummy = .; + . = . + (_dummy_end - _dummy_start); + _mdata = .; + . = . + (_data_end - _data_start); + _mdata_noncache = .; + . = . + (_data_noncache_end - _data_noncache_start); + flash_contents_end = .; + } > xSPI0_CS0_SPACE + .image_info : + { + _image_info_start = .; + KEEP(*(.image_info)) + _image_info_end = .; + } > xSPI0_CS0_SPACE + SECONDARY_START = ALIGN(_image_info_end, 0x20000); + .secondary SECONDARY_START : AT (SECONDARY_START) + { + _secondary_start = .; + KEEP(*(.secondary)) + _secondary_end = .; + } > xSPI0_CS0_SPACE + .loader_text LOADER_TEXT_ADDRESS : AT (_mloader_text) + { + _loader_text_start = .; + *(.loader_text) + */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(.text*) + */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(.text*) + */fsp/src/bsp/mcu/all/bsp_clocks.o(.text*) + */fsp/src/bsp/mcu/all/bsp_irq.o(.text*) + */fsp/src/bsp/mcu/all/bsp_semaphore.o(.text*) + */fsp/src/bsp/mcu/all/bsp_register_protection.o(.text*) + */fsp/src/bsp/mcu/all/bsp_cache.o(.text*) + */fsp/src/r_ioport/r_ioport.o(.text*) + KEEP(*(.warm_start)) + . = . + (512 - ((. - _loader_text_start) % 512)); + _loader_text_end = .; + } > LOADER_STACK + .loader_data : AT (_mloader_data) + { + _loader_data_start = .; + __loader_data_start = .; + */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(.data*) + */fsp/src/bsp/cmsis/Device/RENESAS/Source/*/system_core.o(.rodata*) + */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(.data*) + */fsp/src/bsp/mcu/all/bsp_clocks.o(.data*) + */fsp/src/bsp/mcu/all/bsp_irq.o(.data*) + */fsp/src/bsp/mcu/all/bsp_semaphore.o(.data*) + */fsp/src/bsp/mcu/all/bsp_register_protection.o(.data*) + */fsp/src/bsp/mcu/all/bsp_cache.o(.data*) + */fsp/src/r_ioport/r_ioport.o(.data*) + . = ALIGN(4); + __loader_data_end = .; + __loader_bss_start = .; + */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(.bss*) + */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(.bss*) + */fsp/src/bsp/mcu/all/bsp_clocks.o(.bss*) + */fsp/src/bsp/mcu/all/bsp_irq.o(.bss*) + */fsp/src/bsp/mcu/all/bsp_semaphore.o(.bss*) + */fsp/src/bsp/mcu/all/bsp_register_protection.o(.bss*) + */fsp/src/bsp/mcu/all/bsp_cache.o(.bss*) + */fsp/src/r_ioport/r_ioport.o(.bss*) + */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(COMMON) + */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(COMMON) + */fsp/src/bsp/mcu/all/bsp_clocks.o(COMMON) + */fsp/src/bsp/mcu/all/bsp_irq.o(COMMON) + */fsp/src/bsp/mcu/all/bsp_semaphore.o(COMMON) + */fsp/src/bsp/mcu/all/bsp_register_protection.o(.COMMON) + */fsp/src/bsp/mcu/all/bsp_cache.o(COMMON) + */fsp/src/r_ioport/r_ioport.o(.COMMON) + . = ALIGN(4); + __loader_bss_end = . ; + _loader_data_end = .; + } > LOADER_STACK + .intvec INTVEC_ADDRESS : AT (_mfvector) + { + _fvector_start = .; + KEEP(*(.intvec)) + _fvector_end = .; + } > RAM + .text TEXT_ADDRESS : AT (_mtext) + { + _text_start = .; + *(.text*) + + KEEP(*(.reset_handler)) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + _ctor_end = .; + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + _dtor_end = .; + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + /* new GCC version uses .init_array */ + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + KEEP(*(FalPartTable)) + + KEEP(*(.eh_frame*)) + } > RAM + .rvectors : + { + _rvectors_start = .; + KEEP(*(.rvectors)) + _rvectors_end = .; + } > RAM + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > RAM + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > RAM + __exidx_end = .; + .got : + { + *(.got) + *(.got.plt) + . = ALIGN(4); + _text_end = .; + } > RAM + .dummy _fvector_end : AT (_mdummy) + { + _dummy_start = .; + KEEP(*(.dummy)); + _dummy_end = .; + } > DUMMY + .data : AT (_mdata) + { + _data_start = .; + + *(vtable) + *(.data.*) + *(.data) + + *(.rodata*) + _erodata = .; + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + _data_end = .; + } > RAM + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _bss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + _end = .; + } > RAM + .heap (NOLOAD) : + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + .thread_stack (NOLOAD): + { + . = ALIGN(8); + __ThreadStackBase = .; + /* Place the Thread stacks here. */ + KEEP(*(.stack*)) + __ThreadStackLimit = .; + } > RAM + .sys_stack (NOLOAD) : + { + . = ALIGN(8); + __SysStackBase = .; + /* Place the sys_stack here. */ + KEEP(*(.sys_stack)) + __SysStackLimit = .; + } > LOADER_STACK + .svc_stack (NOLOAD) : + { + . = ALIGN(8); + __SvcStackBase = .; + /* Place the svc_stack here. */ + KEEP(*(.svc_stack)) + __SvcStackLimit = .; + } > LOADER_STACK + .irq_stack (NOLOAD) : + { + . = ALIGN(8); + __IrqStackBase = .; + /* Place the irq_stack here. */ + KEEP(*(.irq_stack)) + __IrqStackLimit = .; + } > LOADER_STACK + .fiq_stack (NOLOAD) : + { + . = ALIGN(8); + __FiqStackBase = .; + /* Place the fiq_stack here. */ + KEEP(*(.fiq_stack)) + __FiqStackLimit = .; + } > LOADER_STACK + .und_stack (NOLOAD) : + { + . = ALIGN(8); + __UndStackBase = .; + /* Place the und_stack here. */ + KEEP(*(.und_stack)) + __UndStackLimit = .; + } > LOADER_STACK + .abt_stack (NOLOAD) : + { + . = ALIGN(8); + __AbtStackBase = .; + /* Place the abt_stack here. */ + KEEP(*(.abt_stack)) + __AbtStackLimit = .; + } > LOADER_STACK + .data_noncache DATA_NONCACHE_START : AT (_mdata_noncache) + { + . = ALIGN(4); + _data_noncache_start = .; + KEEP(*(.data_noncache*)) + _data_noncache_end = .; + } > DATA_NONCACHE + .dmac_link_mode DMAC_LINK_MODE_START : AT (DMAC_LINK_MODE_START) + { + . = ALIGN(4); + _DmacLinkMode_start = .; + KEEP(*(.dmac_link_mode*)) + _DmacLinkMode_end = .; + } > DMAC_LINK_MODE + .shared_noncache_buffer SHARED_NONCACHE_BUFFER_START (NOLOAD) : AT (SHARED_NONCACHE_BUFFER_START) + { + . = ALIGN(32); + _sncbuffer_start = .; + KEEP(*(.shared_noncache_buffer*)) + _sncbuffer_end = .; + } > SHARED_NONCACHE_BUFFER + .noncache_buffer NONCACHE_BUFFER_START (NOLOAD) : AT (NONCACHE_BUFFER_START) + { + . = ALIGN(32); + _ncbuffer_start = .; + KEEP(*(.noncache_buffer*)) + _ncbuffer_end = .; + } > NONCACHE_BUFFER +} + +__ddsc_xSPI0_CS0_SPACE_START = LOADER_PARAM_ADDRESS; +__ddsc_xSPI0_CS0_SPACE_END = _image_info_end; +__ddsc_xSPI0_CS0_SPACE_ALIGNMENT = ALIGN(_image_info_end, 0x20000); \ No newline at end of file diff --git a/bsp/renesas/rzt2m_rsk/script/memory_regions.ld b/bsp/renesas/rzt2m_rsk/script/memory_regions.ld new file mode 100644 index 00000000000..42b822acd19 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/script/memory_regions.ld @@ -0,0 +1,42 @@ +/* generated memory regions file - do not edit */ +ATCM_START = 0x00000000; +ATCM_LENGTH = 0x80000; +BTCM_START = 0x00100000; +BTCM_LENGTH = 0x10000; +SYSTEM_RAM_START = 0x10000000; +SYSTEM_RAM_LENGTH = 0x200000; +SYSTEM_RAM_MIRROR_START = 0x30000000; +SYSTEM_RAM_MIRROR_LENGTH = 0x200000; +xSPI0_CS0_SPACE_MIRROR_START = 0x40000000; +xSPI0_CS0_SPACE_MIRROR_LENGTH = 0x4000000; +xSPI0_CS1_SPACE_MIRROR_START = 0x44000000; +xSPI0_CS1_SPACE_MIRROR_LENGTH = 0x4000000; +xSPI1_CS0_SPACE_MIRROR_START = 0x48000000; +xSPI1_CS0_SPACE_MIRROR_LENGTH = 0x4000000; +xSPI1_CS1_SPACE_MIRROR_START = 0x4C000000; +xSPI1_CS1_SPACE_MIRROR_LENGTH = 0x4000000; +CS0_SPACE_MIRROR_START = 0x50000000; +CS0_SPACE_MIRROR_LENGTH = 0x4000000; +CS2_SPACE_MIRROR_START = 0x54000000; +CS2_SPACE_MIRROR_LENGTH = 0x4000000; +CS3_SPACE_MIRROR_START = 0x58000000; +CS3_SPACE_MIRROR_LENGTH = 0x4000000; +CS5_SPACE_MIRROR_START = 0x5C000000; +CS5_SPACE_MIRROR_LENGTH = 0x4000000; +xSPI0_CS0_SPACE_START = 0x60000000; +xSPI0_CS0_SPACE_LENGTH = 0x4000000; +xSPI0_CS1_SPACE_START = 0x64000000; +xSPI0_CS1_SPACE_LENGTH = 0x4000000; +xSPI1_CS0_SPACE_START = 0x68000000; +xSPI1_CS0_SPACE_LENGTH = 0x4000000; +xSPI1_CS1_SPACE_START = 0x6C000000; +xSPI1_CS1_SPACE_LENGTH = 0x4000000; +CS0_SPACE_START = 0x70000000; +CS0_SPACE_LENGTH = 0x4000000; +CS2_SPACE_START = 0x74000000; +CS2_SPACE_LENGTH = 0x4000000; +CS3_SPACE_START = 0x78000000; +CS3_SPACE_LENGTH = 0x4000000; +CS5_SPACE_START = 0x7C000000; +CS5_SPACE_LENGTH = 0x4000000; +CR52_0 = 1; diff --git a/bsp/renesas/rzt2m_rsk/src/hal_entry.c b/bsp/renesas/rzt2m_rsk/src/hal_entry.c new file mode 100644 index 00000000000..ffb1dc07ab3 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/src/hal_entry.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-11 Wangyuqiang first version + */ + +#include +#include "hal_data.h" +#include +#include + +#define LED_PIN BSP_IO_PORT_19_PIN_6 /* Onboard LED pins */ + +void hal_entry(void) +{ + rt_kprintf("\nHello RT-Thread!\n"); + rt_kprintf("==================================================\n"); + rt_kprintf("This is a iar project which mode is xspi0 execution!\n"); + rt_kprintf("==================================================\n"); + + while (1) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} diff --git a/bsp/renesas/rzt2m_rsk/template.ewd b/bsp/renesas/rzt2m_rsk/template.ewd new file mode 100644 index 00000000000..05f6295a7d7 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/template.ewd @@ -0,0 +1,3276 @@ + + + 4 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + GPLINK_ID + 2 + + 0 + 1 + 1 + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 33 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + GPLINK_ID + 2 + + 0 + 1 + 0 + + + + + + + IJET_ID + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 0 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/renesas/rzt2m_rsk/template.ewp b/bsp/renesas/rzt2m_rsk/template.ewp new file mode 100644 index 00000000000..25576aee9d9 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/template.ewp @@ -0,0 +1,2546 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 38 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + ILINK + 0 + + 27 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + cmd /c ""$RASC_EXE_PATH$" -nosplash --launcher.suppressErrors --generate --compiler IAR --devicefamily rzt "$PROJ_DIR$\configuration.xml" 2> "%TEMP%\rasc_stderr.out"" + $PROJ_DIR$ + preCompile + + + $BUILD_FILES_DIR$/.prebuild + + + + + cmd /c ""$RASC_EXE_PATH$" -nosplash --launcher.suppressErrors --gensmartbundle --compiler IAR --devicefamily rzt "$PROJ_DIR$\configuration.xml" "$TARGET_PATH$" 2> "%TEMP%\rasc_stderr.out"" && echo > "$BUILD_FILES_DIR$/.postbuild" + $PROJ_DIR$ + postLink + + + $BUILD_FILES_DIR$/.postbuild + + + + + + + + + Release + + ARM + + 0 + + General + 3 + + 36 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 38 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + ILINK + 0 + + 27 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + cmd /c ""$RASC_EXE_PATH$" -nosplash --launcher.suppressErrors --generate --compiler IAR --devicefamily rzt "$PROJ_DIR$\configuration.xml" 2> "%TEMP%\rasc_stderr.out"" + $PROJ_DIR$ + preCompile + + + $BUILD_FILES_DIR$/.prebuild + + + + + cmd /c ""$RASC_EXE_PATH$" -nosplash --launcher.suppressErrors --gensmartbundle --compiler IAR --devicefamily rzt "$PROJ_DIR$\configuration.xml" "$TARGET_PATH$" 2> "%TEMP%\rasc_stderr.out"" && echo > "$BUILD_FILES_DIR$/.postbuild" + $PROJ_DIR$ + postLink + + + $BUILD_FILES_DIR$/.postbuild + + + + + + + + + Flex Software + + Build Configuration + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\board_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\bsp_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\bsp_mcu_device_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\bsp_mcu_device_memory_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\bsp_mcu_device_pn_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\bsp_mcu_family_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\bsp_memory_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\bsp\bsp_pin_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\r_ioport_cfg.h + + + $PROJ_DIR$\rzt_cfg\fsp_cfg\r_sci_uart_cfg.h + + + + Components + + $PROJ_DIR$\rzt\board\rzt2m_rsk\board.h + + + $PROJ_DIR$\rzt\board\rzt2m_rsk\board_ethernet_phy.h + + + $PROJ_DIR$\rzt\board\rzt2m_rsk\board_init.c + + + $PROJ_DIR$\rzt\board\rzt2m_rsk\board_init.h + + + $PROJ_DIR$\rzt\board\rzt2m_rsk\board_leds.c + + + $PROJ_DIR$\rzt\board\rzt2m_rsk\board_leds.h + + + $PROJ_DIR$\rzt\fsp\inc\api\bsp_api.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_cache.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_cache.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\cr\bsp_cache_core.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\cr\bsp_cache_core.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_clocks.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_clocks.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_common.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_common.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_compiler_support.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_delay.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_delay.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\cr\bsp_delay_core.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\cr\bsp_delay_core.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\rzt2m\bsp_elc.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_exceptions.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\rzt2m\bsp_feature.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_io.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_io.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_irq.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_irq.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\cr\bsp_irq_core.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\cr\bsp_irq_core.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\rzt2m\bsp_irq_sense.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\rzt2m\bsp_loader_param.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_mcu_api.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\rzt2m\bsp_mcu_info.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_module_stop.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\rzt2m\bsp_override.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_register_protection.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_register_protection.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_reset.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_reset.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_sbrk.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_semaphore.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_semaphore.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\mcu\all\bsp_tfu.h + + + $PROJ_DIR$\rzt\arm\CMSIS_5\CMSIS\Core_R\Include\cmsis_compiler.h + + + $PROJ_DIR$\rzt\arm\CMSIS_5\CMSIS\Core_R\Include\cmsis_cp15.h + + + $PROJ_DIR$\rzt\arm\CMSIS_5\CMSIS\Core_R\Include\cmsis_gcc.h + + + $PROJ_DIR$\rzt\arm\CMSIS_5\CMSIS\Core_R\Include\cmsis_iccarm.h + + + $PROJ_DIR$\rzt\arm\CMSIS_5\CMSIS\Core_R\Include\cmsis_version.h + + + $PROJ_DIR$\rzt\arm\CMSIS_5\CMSIS\Core_R\Include\core_cr52.h + + + $PROJ_DIR$\rzt\fsp\inc\fsp_common_api.h + + + $PROJ_DIR$\rzt\fsp\inc\fsp_features.h + + + $PROJ_DIR$\rzt\fsp\inc\fsp_version.h + + + $PROJ_DIR$\rzt\arm\CMSIS_5\LICENSE.txt + + + $PROJ_DIR$\rzt\fsp\src\bsp\cmsis\Device\RENESAS\Include\R9A07G074.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\cmsis\Device\RENESAS\Include\R9A07G075.h + + + $PROJ_DIR$\rzt\fsp\src\r_ioport\r_ioport.c + + + $PROJ_DIR$\rzt\fsp\inc\instances\r_ioport.h + + + $PROJ_DIR$\rzt\fsp\inc\api\r_ioport_api.h + + + $PROJ_DIR$\rzt\fsp\src\r_sci_uart\r_sci_uart.c + + + $PROJ_DIR$\rzt\fsp\inc\instances\r_sci_uart.h + + + $PROJ_DIR$\rzt\fsp\inc\api\r_transfer_api.h + + + $PROJ_DIR$\rzt\fsp\inc\api\r_uart_api.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\cmsis\Device\RENESAS\Include\renesas.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\cmsis\Device\RENESAS\Source\startup.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\cmsis\Device\RENESAS\Source\cr\startup_core.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\cmsis\Device\RENESAS\Source\system.c + + + $PROJ_DIR$\rzt\fsp\src\bsp\cmsis\Device\RENESAS\Include\system.h + + + $PROJ_DIR$\rzt\fsp\src\bsp\cmsis\Device\RENESAS\Source\cr\system_core.c + + + + Generated Data + + $PROJ_DIR$\rzt_gen\bsp_clock_cfg.h + + + $PROJ_DIR$\rzt_gen\common_data.c + + + $PROJ_DIR$\rzt_gen\common_data.h + + + $PROJ_DIR$\rzt_gen\hal_data.c + + + $PROJ_DIR$\rzt_gen\hal_data.h + + + $PROJ_DIR$\rzt_gen\main.c + + + $PROJ_DIR$\rzt_gen\pin_data.c + + + $PROJ_DIR$\rzt_gen\vector_data.c + + + $PROJ_DIR$\rzt_gen\vector_data.h + + + + Program Entry + + $PROJ_DIR$\src\hal_entry.c + + + + + $PROJ_DIR$\buildinfo.ipcf + IAR.ControlFile + + diff --git a/bsp/renesas/rzt2m_rsk/template.eww b/bsp/renesas/rzt2m_rsk/template.eww new file mode 100644 index 00000000000..53e2ec6f096 --- /dev/null +++ b/bsp/renesas/rzt2m_rsk/template.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\template.ewp + + + diff --git a/bsp/rm48x50/drivers/drv_uart.c b/bsp/rm48x50/drivers/drv_uart.c index d42a52bc6b6..2ebea5ad4fc 100644 --- a/bsp/rm48x50/drivers/drv_uart.c +++ b/bsp/rm48x50/drivers/drv_uart.c @@ -194,7 +194,7 @@ void rt_hw_uart_init(void) config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.bufsz = RT_SERIAL_RB_BUFSZ; _sci2_serial.ops = &_sci_ops; _sci2_serial.config = config; diff --git a/bsp/rockchip/common/drivers/drv_gpio.c b/bsp/rockchip/common/drivers/drv_gpio.c index 1505d004485..f343ea0bb73 100644 --- a/bsp/rockchip/common/drivers/drv_gpio.c +++ b/bsp/rockchip/common/drivers/drv_gpio.c @@ -248,7 +248,7 @@ static void pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t value) HAL_GPIO_SetPinLevel(get_st_gpio(pin), get_st_pin(pin), value); } -static rt_int8_t pin_read(struct rt_device *dev, rt_base_t pin) +static rt_ssize_t pin_read(struct rt_device *dev, rt_base_t pin) { RT_ASSERT(PIN_BANK(pin) < GPIO_BANK_NUM); return HAL_GPIO_GetPinLevel(get_st_gpio(pin), get_st_pin(pin));; diff --git a/bsp/rv32m1_vega/ri5cy/driver/drv_gpio.c b/bsp/rv32m1_vega/ri5cy/driver/drv_gpio.c index 46bc77afdf8..fb1daa4d110 100644 --- a/bsp/rv32m1_vega/ri5cy/driver/drv_gpio.c +++ b/bsp/rv32m1_vega/ri5cy/driver/drv_gpio.c @@ -355,7 +355,7 @@ static void vega_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) GPIO_PinInit(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin, &gpio); } -static rt_int8_t vega_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t vega_pin_read(rt_device_t dev, rt_base_t pin) { uint32_t value; diff --git a/bsp/rv32m1_vega/ri5cy/driver/drv_uart.c b/bsp/rv32m1_vega/ri5cy/driver/drv_uart.c index db526556e01..7097980397f 100644 --- a/bsp/rv32m1_vega/ri5cy/driver/drv_uart.c +++ b/bsp/rv32m1_vega/ri5cy/driver/drv_uart.c @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes * 2018/10/28 Bernard Unify UART driver for FSL library. - * 2019/09/07 niannianyouyu Add the driver of UART1 + * 2019/09/07 niannianyouyu Add the driver of UART1 */ #include @@ -126,7 +126,7 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co switch (cfg->data_bits) { -#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT case DATA_BITS_7: config.dataBitsCount = kLPUART_SevenDataBits; break; @@ -168,7 +168,7 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co uint32_t uartClkSrcFreq0 = CLOCK_GetIpFreq(kCLOCK_Lpuart0); LPUART_Init(uart->uart_base, &config, uartClkSrcFreq0); LPUART_EnableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable); - + CLOCK_SetIpSrc(kCLOCK_Lpuart1, kCLOCK_IpSrcFircAsync); uint32_t uartClkSrcFreq1 = CLOCK_GetIpFreq(kCLOCK_Lpuart1); diff --git a/bsp/sam7x/project.uvproj b/bsp/sam7x/project.uvproj index 2c04776ecdd..4038dfff855 100644 --- a/bsp/sam7x/project.uvproj +++ b/bsp/sam7x/project.uvproj @@ -384,16 +384,16 @@ Applications - application.c + startup.c 1 - applications\application.c + applications\startup.c - startup.c + application.c 1 - applications\startup.c + applications\application.c @@ -496,6 +496,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/smartfusion2/drivers/drv_gpio.c b/bsp/smartfusion2/drivers/drv_gpio.c index 0016717cd78..8c2ec2910f5 100644 --- a/bsp/smartfusion2/drivers/drv_gpio.c +++ b/bsp/smartfusion2/drivers/drv_gpio.c @@ -71,7 +71,7 @@ static void sf2_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) MSS_GPIO_config((mss_gpio_id_t )pin, config); } -static rt_int8_t sf2_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t sf2_pin_read(rt_device_t dev, rt_base_t pin) { uint32_t value; value = MSS_GPIO_get_inputs() & (1<parent.user_data; - + switch(cfg->data_bits) { case DATA_BITS_5: datBits = MSS_UART_DATA_5_BITS; break; @@ -71,7 +71,7 @@ static rt_err_t sf2_uart_configure(struct rt_serial_device *serial, case DATA_BITS_7: datBits = MSS_UART_DATA_7_BITS; break; case DATA_BITS_8: datBits = MSS_UART_DATA_8_BITS; break; default: datBits = MSS_UART_DATA_8_BITS; break; - } + } switch(cfg->parity) { case PARITY_NONE: parity = MSS_UART_NO_PARITY; break; @@ -84,26 +84,26 @@ static rt_err_t sf2_uart_configure(struct rt_serial_device *serial, case STOP_BITS_1: stopBits = MSS_UART_ONE_STOP_BIT; break; case STOP_BITS_2: stopBits = MSS_UART_TWO_STOP_BITS; break; case STOP_BITS_3: stopBits = MSS_UART_ONEHALF_STOP_BIT; break; - default : stopBits = MSS_UART_ONE_STOP_BIT; + default : stopBits = MSS_UART_ONE_STOP_BIT; } - + baudRate = cfg->baud_rate; config = datBits | parity | stopBits; - + MSS_UART_init(uart->uart, baudRate, config); if(uart->uart == &g_mss_uart0) MSS_UART_set_rx_handler(uart->uart, uart0_rx_handler, MSS_UART_FIFO_SINGLE_BYTE); - else + else MSS_UART_set_rx_handler(uart->uart, uart1_rx_handler, MSS_UART_FIFO_SINGLE_BYTE); - return RT_EOK; + return RT_EOK; } -static rt_err_t sf2_uart_control(struct rt_serial_device *serial, - int cmd, void *arg) +static rt_err_t sf2_uart_control(struct rt_serial_device *serial, + int cmd, void *arg) { struct sf2_uart* uart; - + RT_ASSERT(serial != RT_NULL); uart = (struct sf2_uart*)serial->parent.user_data; @@ -124,11 +124,11 @@ static int sf2_uart_putc(struct rt_serial_device *serial, char c) { struct sf2_uart* uart; uint32_t tx_ready; - + RT_ASSERT(serial != RT_NULL); uart = (struct sf2_uart*)serial->parent.user_data; - + do { tx_ready = uart->uart->hw_reg->LSR & 0x20u; } while(!tx_ready); @@ -142,14 +142,14 @@ static int sf2_uart_getc(struct rt_serial_device *serial) int ch = -1; uint8_t err_status; struct sf2_uart* uart; - + RT_ASSERT(serial != RT_NULL); uart = (struct sf2_uart*)serial->parent.user_data; err_status = MSS_UART_get_rx_status(uart->uart); if(MSS_UART_NO_ERROR == err_status) MSS_UART_get_rx(uart->uart, (uint8_t *)&ch, 1); - + return ch; } @@ -172,7 +172,7 @@ int rt_hw_uart_init(void) serial0.ops = &sf2_uart_ops; /* default config: 115200, 8, no, 1 */ serial0.config = config; - result = rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); + result = rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); RT_ASSERT(result == RT_EOK); #endif @@ -181,7 +181,7 @@ int rt_hw_uart_init(void) serial1.ops = &sf2_uart_ops; /* default config: 115200, 8, no, 1 */ serial1.config = config; - result = rt_hw_serial_register(&serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); + result = rt_hw_serial_register(&serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); RT_ASSERT(result == RT_EOK); #endif return result; diff --git a/bsp/smartfusion2/project.uvproj b/bsp/smartfusion2/project.uvproj index 2b351ead718..5bc7df8b1e2 100644 --- a/bsp/smartfusion2/project.uvproj +++ b/bsp/smartfusion2/project.uvproj @@ -425,13 +425,6 @@ CMSIS - - - system_m2sxxx.c - 1 - CMSIS\system_m2sxxx.c - - startup_m2sxxx.s @@ -446,6 +439,13 @@ CMSIS\core_cm3.c + + + system_m2sxxx.c + 1 + CMSIS\system_m2sxxx.c + + Compiler @@ -546,6 +546,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/smartfusion2/project.uvprojx b/bsp/smartfusion2/project.uvprojx index c4fd778e985..93b43fe5a73 100644 --- a/bsp/smartfusion2/project.uvprojx +++ b/bsp/smartfusion2/project.uvprojx @@ -524,6 +524,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/README.md b/bsp/stm32/README.md index e7c9d57f74d..9ba2e08d522 100644 --- a/bsp/stm32/README.md +++ b/bsp/stm32/README.md @@ -30,6 +30,7 @@ STM32 系列 BSP 目前支持情况如下表所示： | [stm32f407-rt-spark](stm32f407-rt-spark) | 睿赛德官方 F407 星火一号开发板 | | [stm32f401-st-nucleo](stm32f401-st-nucleo) | ST 官方 STM32F401 Nucleo-64 开发板 | | [stm32f405-smdz-breadfruit](stm32f405-smdz-breadfruit) | 三木电子 SM1432F405 开发板 | +| [stm32f407-lckfb-skystar](stm32f407-lckfb-skystar) | 立创开发板 天空星STM32F407开发板 | | [stm32f407-atk-explorer](stm32f407-atk-explorer) | 正点原子 F407 探索者开发板 | | [stm32f407-robomaster-c](stm32f407-robomaster-c) | 大疆公司 RoboMaster C型开发板 | | [stm32f407-st-discovery](stm32f407-st-discovery) | ST 官方 STM32F407-discovery 开发板 | diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h index 2c7d3775eb1..fdb6eef2532 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h @@ -125,6 +125,17 @@ extern "C" { #include "h7/sdio_config.h" #include "h7/pwm_config.h" #include "h7/usbd_config.h" + +#elif defined(SOC_SERIES_STM32H7RS) +#include "h7/dma_config.h" +#include "h7/uart_config.h" +#include "h7/spi_config.h" +#include "h7/adc_config.h" +#include "h7/dac_config.h" +#include "h7/tim_config.h" +#include "h7/pwm_config.h" +#include "h7/usbd_config.h" + #elif defined(SOC_SERIES_STM32U5) #include "u5/dma_config.h" #include "u5/uart_config.h" diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h index 6000a4119b2..3fe4ff8978d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h @@ -22,7 +22,7 @@ extern "C" { #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32L5)\ || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) \ || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \ - || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) + || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) #define DMA_INSTANCE_TYPE DMA_Channel_TypeDef #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\ || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_gpio.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_gpio.c index efadb5870dd..3ff92b1341b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_gpio.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_gpio.c @@ -35,6 +35,14 @@ #define PIN_STPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) #if defined(GPIOZ) +#define __STM32_PORT_MAX 16u +#elif defined(GPIOP) +#define __STM32_PORT_MAX 15u +#elif defined(GPIOO) +#define __STM32_PORT_MAX 14u +#elif defined(GPION) +#define __STM32_PORT_MAX 13u +#elif defined(GPIOM) #define __STM32_PORT_MAX 12u #elif defined(GPIOK) #define __STM32_PORT_MAX 11u @@ -84,7 +92,8 @@ static const struct pin_irq_map pin_irq_map[] = {GPIO_PIN_13, EXTI4_15_IRQn}, {GPIO_PIN_14, EXTI4_15_IRQn}, {GPIO_PIN_15, EXTI4_15_IRQn}, -#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) +#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32U5) \ + || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) {GPIO_PIN_0, EXTI0_IRQn}, {GPIO_PIN_1, EXTI1_IRQn}, {GPIO_PIN_2, EXTI2_IRQn}, @@ -217,7 +226,7 @@ static void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t stm32_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t stm32_pin_read(rt_device_t dev, rt_base_t pin) { GPIO_TypeDef *gpio_port; uint16_t gpio_pin; @@ -229,6 +238,10 @@ static rt_int8_t stm32_pin_read(rt_device_t dev, rt_base_t pin) gpio_pin = PIN_STPIN(pin); state = HAL_GPIO_ReadPin(gpio_port, gpio_pin); } + else + { + return -RT_EINVAL; + } return (state == GPIO_PIN_RESET) ? PIN_LOW : PIN_HIGH; } @@ -503,13 +516,13 @@ static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, } static const struct rt_pin_ops _stm32_pin_ops = { - stm32_pin_mode, - stm32_pin_write, - stm32_pin_read, - stm32_pin_attach_irq, - stm32_pin_dettach_irq, - stm32_pin_irq_enable, - stm32_pin_get, + stm32_pin_mode, + stm32_pin_write, + stm32_pin_read, + stm32_pin_attach_irq, + stm32_pin_dettach_irq, + stm32_pin_irq_enable, + stm32_pin_get, }; rt_inline void pin_irq_hdr(int irqno) @@ -571,7 +584,7 @@ void EXTI4_15_IRQHandler(void) rt_interrupt_leave(); } -#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32U5) +#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H7RS) void EXTI0_IRQHandler(void) { rt_interrupt_enter(); @@ -794,6 +807,22 @@ int rt_hw_pin_init(void) __HAL_RCC_GPIOK_CLK_ENABLE(); #endif +#if defined(__HAL_RCC_GPIOM_CLK_ENABLE) + __HAL_RCC_GPIOM_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPION_CLK_ENABLE) + __HAL_RCC_GPION_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPIOO_CLK_ENABLE) + __HAL_RCC_GPIOO_CLK_ENABLE(); +#endif + +#if defined(__HAL_RCC_GPIOP_CLK_ENABLE) + __HAL_RCC_GPIOP_CLK_ENABLE(); +#endif + return rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL); } diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c index e28fa5db4ef..bc616b04717 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c @@ -59,10 +59,18 @@ static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv) rt_memset(i2c_handle, 0, sizeof(I2C_HandleTypeDef)); struct stm32_i2c_config *cfg = i2c_drv->config; i2c_handle->Instance = cfg->Instance; +#if defined(SOC_SERIES_STM32H7) i2c_handle->Init.Timing = cfg->timing; +#endif /* defined(SOC_SERIES_STM32H7) */ +#if defined(SOC_SERIES_STM32F4) + hi2c1.Init.ClockSpeed = 100000; + hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; +#endif /* defined(SOC_SERIES_STM32F4) */ i2c_handle->Init.OwnAddress1 = 0; i2c_handle->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; +#if defined(SOC_SERIES_STM32H7) i2c_handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; +#endif /* defined(SOC_SERIES_STM32H7) */ i2c_handle->Init.OwnAddress2 = 0; i2c_handle->Init.OwnAddress2Masks = I2C_OA2_NOMASK; i2c_handle->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; @@ -76,7 +84,7 @@ static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv) { return -RT_EFAULT; } - +#if defined(SOC_SERIES_STM32H7) /* Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(i2c_handle, I2C_ANALOGFILTER_ENABLE) != HAL_OK) { @@ -88,7 +96,7 @@ static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv) { return -RT_EFAULT; } - +#endif /* defined(SOC_SERIES_STM32H7) */ /* I2C2 DMA Init */ if (i2c_drv->i2c_dma_flag & I2C_USING_RX_DMA_FLAG) { @@ -123,7 +131,6 @@ static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv) static rt_err_t stm32_i2c_configure(struct rt_i2c_bus_device *bus) { - int ret = -RT_ERROR; RT_ASSERT(RT_NULL != bus); struct stm32_i2c *i2c_drv = rt_container_of(bus, struct stm32_i2c, i2c_bus); @@ -307,7 +314,9 @@ static rt_ssize_t stm32_i2c_master_xfer(struct rt_i2c_bus_device *bus, { LOG_D("I2C NACK Error now stoped"); /* Send stop signal to prevent bus lock-up */ +#if defined(SOC_SERIES_STM32H7) handle->Instance->CR1 |= I2C_IT_STOPI; +#endif /* defined(SOC_SERIES_STM32H7) */ } if (handle->ErrorCode == HAL_I2C_ERROR_BERR) { @@ -459,6 +468,7 @@ void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) } void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) { +#if defined(SOC_SERIES_STM32H7) /* Send stop signal to prevent bus lock-up */ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -470,6 +480,8 @@ void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) LOG_D("I2C BUS Error now stoped"); hi2c->Instance->CR1 |= I2C_IT_STOPI; } +#endif /* defined(SOC_SERIES_STM32H7) */ + } #ifdef BSP_USING_HARD_I2C1 /** diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.h index 2d9d425cd80..5e91a26471f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.h @@ -18,7 +18,7 @@ #include #include "drv_dma.h" #include -#ifdef (RT_USING_I2C && BSP_USING_I2C) +#if defined(RT_USING_I2C) && defined(BSP_USING_I2C) /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus @@ -26,7 +26,6 @@ extern "C" { #endif - struct stm32_i2c_config { const char *name; diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lcd.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lcd.c index 8f9167465ea..31ca4fa5dfc 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lcd.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lcd.c @@ -181,10 +181,6 @@ rt_err_t stm32_lcd_init(struct drv_lcd_device *lcd) { pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB888; } - else if (lcd->lcd_info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_RGB888) - { - pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB888; - } else { LOG_E("unsupported pixel format"); diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c index 4f530a12e69..d5bc35057ba 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c @@ -14,6 +14,7 @@ #include "board.h" #include #include +#include #ifdef BSP_USING_ONCHIP_RTC diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_soft_i2c.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_soft_i2c.c index 3838b740493..5592e6c738e 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_soft_i2c.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_soft_i2c.c @@ -12,7 +12,8 @@ #include "drv_soft_i2c.h" #include "drv_config.h" -#if defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) || defined(BSP_USING_I2C4) +#if defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) || defined(BSP_USING_I2C4) || defined(BSP_USING_I2C5) + //#define DRV_DEBUG #define LOG_TAG "drv.i2c.sw" @@ -32,6 +33,9 @@ static const struct stm32_soft_i2c_config soft_i2c_config[] = #ifdef BSP_USING_I2C4 I2C4_BUS_CONFIG, #endif +#ifdef BSP_USING_I2C5 + I2C5_BUS_CONFIG, +#endif }; static struct stm32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])]; diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_soft_i2c.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_soft_i2c.h index e5f8695b7a2..40c77f566dd 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_soft_i2c.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_soft_i2c.h @@ -64,6 +64,15 @@ struct stm32_i2c .bus_name = "i2c4", \ } #endif + +#ifdef BSP_USING_I2C5 +#define I2C5_BUS_CONFIG \ + { \ + .scl = BSP_I2C5_SCL_PIN, \ + .sda = BSP_I2C5_SDA_PIN, \ + .bus_name = "i2c5", \ + } +#endif int rt_hw_i2c_init(void); #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_soft_spi.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_soft_spi.c index ad186e3bcd1..6f36d5ad8e1 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_soft_spi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_soft_spi.c @@ -28,6 +28,8 @@ static struct stm32_soft_spi_config soft_spi_config[] = #endif }; +static struct stm32_soft_spi spi_obj[sizeof(soft_spi_config) / sizeof(soft_spi_config[0])]; + /** * Attach the spi device to soft SPI bus, this function must be used after initialization. */ @@ -184,9 +186,20 @@ static void stm32_udelay(rt_uint32_t us) } } +static void stm32_pin_init(void) +{ + rt_size_t obj_num = sizeof(spi_obj) / sizeof(struct stm32_soft_spi); + + for(rt_size_t i; i < obj_num; i++) + { + stm32_spi_gpio_init(&spi_obj[i]); + } +} + static struct rt_spi_bit_ops stm32_soft_spi_ops = { .data = RT_NULL, + .pin_init = stm32_pin_init, .tog_sclk = stm32_tog_sclk, .set_sclk = stm32_set_sclk, .set_mosi = stm32_set_mosi, @@ -200,21 +213,18 @@ static struct rt_spi_bit_ops stm32_soft_spi_ops = .delay_us = 1, }; -static struct stm32_soft_spi spi_obj[sizeof(soft_spi_config) / sizeof(soft_spi_config[0])]; - /* Soft SPI initialization function */ int rt_hw_softspi_init(void) { rt_size_t obj_num = sizeof(spi_obj) / sizeof(struct stm32_soft_spi); rt_err_t result; - for (int i = 0; i < obj_num; i++) + for (rt_size_t i = 0; i < obj_num; i++) { memcpy(&spi_obj[i].ops, &stm32_soft_spi_ops, sizeof(struct rt_spi_bit_ops)); spi_obj[i].ops.data = (void *)&soft_spi_config[i]; spi_obj[i].spi.ops = &stm32_soft_spi_ops; spi_obj[i].cfg = (void *)&soft_spi_config[i]; - stm32_spi_gpio_init(&spi_obj[i]); result = rt_spi_bit_add_bus(&spi_obj[i].spi, soft_spi_config[i].bus_name, &spi_obj[i].ops); RT_ASSERT(result == RT_EOK); } diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c index ebfebbba42f..8424bbf781c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c @@ -298,9 +298,13 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE)) { if (device->config.mode & RT_SPI_CS_HIGH) + { rt_pin_write(device->cs_pin, PIN_HIGH); + } else + { rt_pin_write(device->cs_pin, PIN_LOW); + } } LOG_D("%s transfer prepare and start", spi_drv->config->bus_name); @@ -344,7 +348,7 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (send_length >= DMA_TRANS_MIN_LEN)) { #if defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) - if (RT_IS_ALIGN((rt_uint32_t)send_buf, 32)) /* aligned with 32 bytes? */ + if (RT_IS_ALIGN((rt_uint32_t)send_buf, 32) && send_buf != RT_NULL) /* aligned with 32 bytes? */ { p_txrx_buffer = (rt_uint32_t *)send_buf; /* send_buf aligns with 32 bytes, no more operations */ } @@ -357,7 +361,7 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m } rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, dma_aligned_buffer, send_length); #else - if (RT_IS_ALIGN((rt_uint32_t)send_buf, 4)) /* aligned with 4 bytes? */ + if (RT_IS_ALIGN((rt_uint32_t)send_buf, 4) && send_buf != RT_NULL) /* aligned with 4 bytes? */ { p_txrx_buffer = (rt_uint32_t *)send_buf; /* send_buf aligns with 4 bytes, no more operations */ } diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c index 7e73a5739f8..081c0ae8ac5 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c @@ -317,7 +317,7 @@ static int stm32_putc(struct rt_serial_device *serial, char c) #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \ || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \ || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3) \ - || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) + || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) uart->handle.Instance->TDR = c; #else uart->handle.Instance->DR = c; @@ -339,7 +339,7 @@ static int stm32_getc(struct rt_serial_device *serial) #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \ || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \ || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \ - || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) + || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) ch = uart->handle.Instance->RDR & uart->DR_mask; #else ch = uart->handle.Instance->DR & uart->DR_mask; @@ -477,7 +477,7 @@ static void uart_isr(struct rt_serial_device *serial) #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \ && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \ && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB) \ - && !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5) && !defined(SOC_SERIES_STM32H5) + && !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5) && !defined(SOC_SERIES_STM32H5) && !defined(SOC_SERIES_STM32H7RS) #ifdef SOC_SERIES_STM32F3 if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET) { diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h index 7f0b0731550..1885d164b58 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h @@ -32,7 +32,7 @@ int rt_hw_usart_init(void); #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32WL) \ || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \ || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32U5) \ - || defined(SOC_SERIES_STM32H5) + || defined(SOC_SERIES_STM32H5) || defined(SOC_SERIES_STM32H7RS) #define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG #elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \ || defined(SOC_SERIES_STM32MP1) diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_common.c b/bsp/stm32/libraries/HAL_Drivers/drv_common.c index fa5b806250c..62a1b35e078 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_common.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_common.c @@ -23,8 +23,8 @@ #endif /* RT_USING_SERIAL */ #endif /* RT_USING_SERIAL_V2 */ -#define DBG_TAG "drv_common" -#define DBG_LVL DBG_INFO +#define DBG_TAG "drv_common" +#define DBG_LVL DBG_INFO #include #ifdef RT_USING_FINSH @@ -42,12 +42,15 @@ static uint32_t _systick_ms = 1; /* SysTick configuration */ void rt_hw_systick_init(void) { + // Updates the variable SystemCoreClock + SystemCoreClockUpdate(); + HAL_SYSTICK_Config(SystemCoreClock / RT_TICK_PER_SECOND); NVIC_SetPriority(SysTick_IRQn, 0xFF); _systick_ms = 1000u / RT_TICK_PER_SECOND; - if(_systick_ms == 0) + if (_systick_ms == 0) _systick_ms = 1; } @@ -60,7 +63,7 @@ void SysTick_Handler(void) /* enter interrupt */ rt_interrupt_enter(); - if(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) + if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) HAL_IncTick(); rt_tick_increase(); @@ -71,7 +74,7 @@ void SysTick_Handler(void) uint32_t HAL_GetTick(void) { - if(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) + if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) HAL_IncTick(); return uwTick; @@ -115,10 +118,10 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) } /** - * @brief This function is executed in case of error occurrence. - * @param None - * @retval None - */ + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ void _Error_Handler(char *s, int num) { /* USER CODE BEGIN Error_Handler */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Include/stm32h7r3xx.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Include/stm32h7r3xx.h new file mode 100644 index 00000000000..12f0579e41f --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Include/stm32h7r3xx.h @@ -0,0 +1,23356 @@ +/** + ****************************************************************************** + * @file stm32h7r3xx.h + * @author MCD Application Team + * @brief CMSIS STM32H7R3xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32H7R3xx_H +#define STM32H7R3xx_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32H7R3xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M7 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32H7R3xx Specific Interrupt Numbers ====================================== */ + PVD_PVM_IRQn = 0, /*!< PVD/PVM through EXTI Line detection */ + DTS_IRQn = 2, /*!< Digital Temperature Sensor interrupt */ + IWDG_IRQn = 3, /*!< Internal Watchdog interrupt */ + WWDG_IRQn = 4, /*!< Window Watchdog interrupt */ + RCC_IRQn = 5, /*!< RCC global interrupts through EXTI Line detection */ + FLASH_IRQn = 8, /*!< FLASH interrupts */ + RAMECC_IRQn = 9, /*!< RAMECC interrupts */ + FPU_IRQn = 10, /*!< FPU interrupt */ + TAMP_IRQn = 13, /*!< Tamper and TimeStamp interrupts through EXTI Line detection */ + EXTI0_IRQn = 16, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 17, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 18, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 19, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 20, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 21, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 22, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 23, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 24, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 25, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 26, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 27, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 28, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 29, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 30, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 31, /*!< EXTI Line15 interrupt */ + RTC_IRQn = 32, /*!< RTC Wakeup and Alarm interrupts through EXTI Line detection */ + PKA_IRQn = 35, /*!< PKA interrupt */ + HASH_IRQn = 36, /*!< HASH interrupt */ + RNG_IRQn = 37, /*!< RNG global interrupt */ + ADC1_2_IRQn = 38, /*!< ADC1 & ADC2 interrupt */ + GPDMA1_Channel0_IRQn = 39, /*!< GPDMA1 Channel 0 interrupt */ + GPDMA1_Channel1_IRQn = 40, /*!< GPDMA1 Channel 1 interrupt */ + GPDMA1_Channel2_IRQn = 41, /*!< GPDMA1 Channel 2 interrupt */ + GPDMA1_Channel3_IRQn = 42, /*!< GPDMA1 Channel 3 interrupt */ + GPDMA1_Channel4_IRQn = 43, /*!< GPDMA1 Channel 4 interrupt */ + GPDMA1_Channel5_IRQn = 44, /*!< GPDMA1 Channel 5 interrupt */ + GPDMA1_Channel6_IRQn = 45, /*!< GPDMA1 Channel 6 interrupt */ + GPDMA1_Channel7_IRQn = 46, /*!< GPDMA1 Channel 7 interrupt */ + TIM1_BRK_IRQn = 47, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 48, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 49, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 50, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 51, /*!< TIM2 global interrupt */ + TIM3_IRQn = 52, /*!< TIM3 global interrupt */ + TIM4_IRQn = 53, /*!< TIM4 global interrupt */ + TIM5_IRQn = 54, /*!< TIM5 global interrupt */ + TIM6_IRQn = 55, /*!< TIM6 global interrupt */ + TIM7_IRQn = 56, /*!< TIM7 global interrupt */ + TIM9_IRQn = 57, /*!< TIM9 global interrupt */ + SPI1_IRQn = 58, /*!< SPI1 global interrupt */ + SPI2_IRQn = 59, /*!< SPI2 global interrupt */ + SPI3_IRQn = 60, /*!< SPI3 global interrupt */ + SPI4_IRQn = 61, /*!< SPI4 global interrupt */ + SPI5_IRQn = 62, /*!< SPI5 global interrupt */ + SPI6_IRQn = 63, /*!< SPI6 global interrupt */ + HPDMA1_Channel0_IRQn = 64, /*!< HPDMA1 Channel 0 global interrupt */ + HPDMA1_Channel1_IRQn = 65, /*!< HPDMA1 Channel 1 global interrupt */ + HPDMA1_Channel2_IRQn = 66, /*!< HPDMA1 Channel 2 global interrupt */ + HPDMA1_Channel3_IRQn = 67, /*!< HPDMA1 Channel 3 global interrupt */ + HPDMA1_Channel4_IRQn = 68, /*!< HPDMA1 Channel 4 global interrupt */ + HPDMA1_Channel5_IRQn = 69, /*!< HPDMA1 Channel 5 global interrupt */ + HPDMA1_Channel6_IRQn = 70, /*!< HPDMA1 Channel 6 global interrupt */ + HPDMA1_Channel7_IRQn = 71, /*!< HPDMA1 Channel 7 global interrupt */ + SAI1_A_IRQn = 72, /*!< Serial Audio Interface 1 block A interrupt */ + SAI1_B_IRQn = 73, /*!< Serial Audio Interface 1 block B interrupt */ + SAI2_A_IRQn = 74, /*!< Serial Audio Interface 2 block A interrupt */ + SAI2_B_IRQn = 75, /*!< Serial Audio Interface 2 block B interrupt */ + I2C1_EV_IRQn = 76, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 77, /*!< I2C1 error interrupt */ + I2C2_EV_IRQn = 78, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 79, /*!< I2C2 error interrupt */ + I2C3_EV_IRQn = 80, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 81, /*!< I2C3 error interrupt */ + USART1_IRQn = 82, /*!< USART1 global interrupt */ + USART2_IRQn = 83, /*!< USART2 global interrupt */ + USART3_IRQn = 84, /*!< USART3 global interrupt */ + UART4_IRQn = 85, /*!< UART4 global interrupt */ + UART5_IRQn = 86, /*!< UART5 global interrupt */ + UART7_IRQn = 87, /*!< UART7 global interrupt */ + UART8_IRQn = 88, /*!< UART8 global interrupt */ + I3C1_EV_IRQn = 89, /*!< I3C1 event interrupt */ + I3C1_ER_IRQn = 90, /*!< I3C1 error interrupt */ + OTG_HS_IRQn = 91, /*!< USB OTG HS interrupt */ + ETH_IRQn = 92, /*!< Ethernet global interrupt */ + CORDIC_IRQn = 93, /*!< CORDIC global interrupt */ + GFXTIM_IRQn = 94, /*!< GFXTIM global interrupt */ + DCMIPP_IRQn = 95, /*!< DCMIPP global interrupt */ + DMA2D_IRQn = 98, /*!< DMA2D global interrupt */ + JPEG_IRQn = 99, /*!< JPEG global interrupt */ + GFXMMU_IRQn = 100, /*!< GFXMMU global interrupt */ + I3C1_WKUP_IRQn = 101, /*!< I3C1 wakeup global interrupt */ + XSPI1_IRQn = 105, /*!< XSPI1 global interrupt */ + XSPI2_IRQn = 106, /*!< XSPI2 global interrupt */ + FMC_IRQn = 107, /*!< FMC global interrupt */ + SDMMC1_IRQn = 108, /*!< SDMMC1 global interrupt */ + SDMMC2_IRQn = 109, /*!< SDMMC2 global interrupt */ + OTG_FS_IRQn = 112, /*!< USB OTG FS interrupt */ + TIM12_IRQn = 113, /*!< TIM12 global interrupt */ + TIM13_IRQn = 114, /*!< TIM13 global interrupt */ + TIM14_IRQn = 115, /*!< TIM14 global interrupt */ + TIM15_IRQn = 116, /*!< TIM15 global interrupt */ + TIM16_IRQn = 117, /*!< TIM16 global interrupt */ + TIM17_IRQn = 118, /*!< TIM17 global interrupt */ + LPTIM1_IRQn = 119, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 120, /*!< LPTIM2 global interrupt */ + LPTIM3_IRQn = 121, /*!< LPTIM3 global interrupt */ + LPTIM4_IRQn = 122, /*!< LPTIM4 global interrupt */ + LPTIM5_IRQn = 123, /*!< LPTIM5 global interrupt */ + SPDIF_RX_IRQn = 124, /*!< SPDIF_RX global interrupt */ + MDIOS_IRQn = 125, /*!< MDIOS global interrupt */ + ADF1_FLT0_IRQn = 126, /*!< ADF1 Filter 0 global Interrupt */ + CRS_IRQn = 127, /*!< CRS global interrupt */ + UCPD1_IRQn = 128, /*!< UCPD1 global interrupt */ + CEC_IRQn = 129, /*!< HDMI_CEC global Interrupt */ + PSSI_IRQn = 130, /*!< PSSI global interrupt */ + LPUART1_IRQn = 131, /*!< LPUART1 global interrupt */ + WAKEUP_PIN_IRQn = 132, /*!< Wake-up pins interrupt */ + GPDMA1_Channel8_IRQn = 133, /*!< GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQn = 134, /*!< GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQn = 135, /*!< GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQn = 136, /*!< GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQn = 137, /*!< GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQn = 138, /*!< GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQn = 139, /*!< GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQn = 140, /*!< GPDMA1 Channel 15 global interrupt */ + HPDMA1_Channel8_IRQn = 141, /*!< HPDMA1 Channel 8 global interrupt */ + HPDMA1_Channel9_IRQn = 142, /*!< HPDMA1 Channel 9 global interrupt */ + HPDMA1_Channel10_IRQn = 143, /*!< HPDMA1 Channel 10 global interrupt */ + HPDMA1_Channel11_IRQn = 144, /*!< HPDMA1 Channel 11 global interrupt */ + HPDMA1_Channel12_IRQn = 145, /*!< HPDMA1 Channel 12 global interrupt */ + HPDMA1_Channel13_IRQn = 146, /*!< HPDMA1 Channel 13 global interrupt */ + HPDMA1_Channel14_IRQn = 147, /*!< HPDMA1 Channel 14 global interrupt */ + HPDMA1_Channel15_IRQn = 148, /*!< HPDMA1 Channel 15 global interrupt */ + FDCAN1_IT0_IRQn = 152, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 153, /*!< FDCAN1 interrupt 1 */ + FDCAN2_IT0_IRQn = 154, /*!< FDCAN2 interrupt 0 */ + FDCAN2_IT1_IRQn = 155 /*!< FDCAN2 interrupt 1 */ +} IRQn_Type; + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ +#define __CM7_REV 0x0102U /*!< Cortex-M7 revision r1p2 */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __MPU_REGIONCOUNT 16U /*!< CM7 provides MPU region number */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + +#include /*!< ARM Cortex-M7 processor and core peripherals */ +#include "system_stm32h7rsxx.h" /*!< STM32H7RSxx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H7RSxx_peripherals + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[4];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t OR; /*!< ADC option register, Address offset: 0xC8 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief AXIM ASIB + */ +typedef struct +{ + uint32_t RESERVED1[9]; /*!< Reserved, Address offset: 0x00-0x20 */ + __IO uint32_t FNMOD2; /*!< AXIM ASIB fn_mod2 register Address offset: 0x24 */ + uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x28-0xFC */ + __IO uint32_t READQOS; /*!< AXIM ASIB read_qos register Address offset: 0x100 */ + __IO uint32_t WRITEQOS; /*!< AXIM ASIB write_qos register Address offset: 0x104 */ + __IO uint32_t FNMOD; /*!< AXIM ASIB fn_mod register Address offset: 0x108 */ +} AXIM_ASIB_TypeDef; + +typedef struct +{ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x00-0x04 */ + __IO uint32_t FNMODBMISS; /*!< AXIM AMIB fn_mod_bm_iss register Address offset: 0x08 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x0C-0x20 */ + __IO uint32_t FNMOD2; /*!< AXIM AMIB fn_mod2 register Address offset: 0x24 */ + uint32_t RESERVED3[1]; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t FNMODLB; /*!< AXIM AMIB fn_mod_lb register Address offset: 0x2C */ + uint32_t RESERVED5[54]; /*!< Reserved, Address offset: 0x30-0x104 */ + __IO uint32_t FNMOD; /*!< AXIM AMIB fn_mod register Address offset: 0x108 */ +} AXIM_AMIB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +} CEC_TypeDef; + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC Control and Status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief GFXTIM + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXTIM configuration register, Address offset: 0x00 */ + __IO uint32_t CGCR; /*!< GFXTIM clock generator configuration register, Address offset: 0x04 */ + __IO uint32_t TCR; /*!< GFXTIM timers configuration register, Address offset: 0x08 */ + __IO uint32_t TDR; /*!< GFXTIM timers disable register, Address offset: 0x0C */ + __IO uint32_t EVCR; /*!< GFXTIM events control register, Address offset: 0x10 */ + __IO uint32_t EVSR; /*!< GFXTIM events selection register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WDGTCR; /*!< GFXTIM watchdog timer configuration register, Address offset: 0x20 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t ISR; /*!< GFXTIM interrupt status register, Address offset: 0x30 */ + __IO uint32_t ICR; /*!< GFXTIM interrupt clear register, Address offset: 0x34 */ + __IO uint32_t IER; /*!< GFXTIM interrupt enable register, Address offset: 0x38 */ + __IO uint32_t TSR; /*!< GFXTIM timers status register, Address offset: 0x3C */ + __IO uint32_t LCCRR; /*!< GFXTIM line clock counter reload register, Address offset: 0x40 */ + __IO uint32_t FCCRR; /*!< GFXTIM frame clock counter reload register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48-0x4C */ + __IO uint32_t ATR; /*!< GFXTIM absolute time register, Address offset: 0x50 */ + __IO uint32_t AFCR; /*!< GFXTIM absolute frame counter register, Address offset: 0x54 */ + __IO uint32_t ALCR; /*!< GFXTIM absolute line counter register, Address offset: 0x58 */ + uint32_t RESERVED4[1]; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t AFCC1R; /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */ + uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x64-0X6C */ + __IO uint32_t ALCC1R; /*!< GFXTIM absolute line counter compare 1 register, Address offset: 0x70 */ + __IO uint32_t ALCC2R; /*!< GFXTIM absolute line counter compare 2 register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x78-0X7C */ + __IO uint32_t RFC1R; /*!< GFXTIM relative frame counter 1 register, Address offset: 0x80 */ + __IO uint32_t RFC1RR; /*!< GFXTIM relative frame counter 1 reload register, Address offset: 0x84 */ + __IO uint32_t RFC2R; /*!< GFXTIM relative frame counter 2 register, Address offset: 0x88 */ + __IO uint32_t RFC2RR; /*!< GFXTIM relative frame counter 2 reload register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x90-0X9C */ + __IO uint32_t WDGCR; /*!< GFXTIM watchdog counter register, Address offset: 0xA0 */ + __IO uint32_t WDGRR; /*!< GFXTIM watchdog reload register, Address offset: 0xA4 */ + __IO uint32_t WDGPAR; /*!< GFXTIM watchdog pre-alarm register, Address offset: 0xA8 */ + uint32_t RESERVED8[209]; /*!< Reserved, Address offset: 0xAC-0X3EC */ + __IO uint32_t HWCFGR; /*!< GFXTIM HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GFXTIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GFXTIM identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GFXTIM size identification register, Address offset: 0x3FC */ +} GFXTIM_TypeDef; + + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t AHB5FZR; /*!< Debug MCU AHB5FZR freeze register, Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1FZR freeze register, Address offset: 0x24 */ + uint32_t RESERVED3[5]; /*!< Reserved, Address offset: 0x28-0x38 */ + __IO uint32_t APB1FZR; /*!< Debug MCU APB1FZR freeze register, Address offset: 0x3C */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x40-0x48 */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2FZR freeze register, Address offset: 0x4C */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZR; /*!< Debug MCU APB4FZR freeze register, Address offset: 0x54 */ + uint32_t RESERVED6[41]; /*!< Reserved, Address offset: 0x58-0xF8 */ + __IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU Authentication Host register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug MCU Authentication Device register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug MCU Authentication Ack register, Address offset: 0x108 */ + uint32_t RESERVED7[945]; /*!< Reserved, Address offset: 0x10C-0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU peripheral identity register 4, Address offset: 0xFD0 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0xFD4-0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMIPP + */ +typedef struct +{ + __IO uint32_t IPGR1; /*!< IP-Plug global register 1 Address offset: 0x00 */ + __IO uint32_t IPGR2; /*!< IP-Plug global register 2 Address offset: 0x04 */ + __IO uint32_t IPGR3; /*!< IP-Plug global register 3 Address offset: 0x08 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x0C-0x18 */ + __IO uint32_t IPGR8; /*!< IP-Plug global register 8 Address offset: 0x1C */ + __IO uint32_t IPC1R1; /*!< IP-Plug client 1 register 1 Address offset: 0x20 */ + __IO uint32_t IPC1R2; /*!< IP-Plug client 1 register 2 Address offset: 0x24 */ + __IO uint32_t IPC1R3; /*!< IP-Plug client 1 register 3 Address offset: 0x28 */ + __IO uint32_t RESERVED2[54]; /*!< Reserved, Address offset: 0x2C-0x100 */ + __IO uint32_t PRCR; /*!< Parallel interface control register Address offset: 0x104 */ + __IO uint32_t PRESCR; /*!< Parallel interface embedded sync code register Address offset: 0x108 */ + __IO uint32_t PRESUR; /*!< Parallel interface embedded sync unmask register Address offset: 0x10C */ + __IO uint32_t RESERVED3[57]; /*!< Reserved, Address offset: 0x110-0x1F0 */ + __IO uint32_t PRIER; /*!< Parallel interface interrupt enable register Address offset: 0x1F4 */ + __IO uint32_t PRSR; /*!< Parallel interface status register Address offset: 0x1F8 */ + __IO uint32_t PRFCR; /*!< Parallel interface interrupt clear register Address offset: 0x1FC */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x200 */ + __IO uint32_t CMCR; /*!< Common configuration register Address offset: 0x204 */ + __IO uint32_t CMFRCR; /*!< Common frame counter register Address offset: 0x208 */ + __IO uint32_t RESERVED5[121]; /*!< Reserved, Address offset: 0x20C-0x3EC */ + __IO uint32_t CMIER; /*!< Common interrupt enable register Address offset: 0x3F0 */ + __IO uint32_t CMSR1; /*!< Common status register 1 Address offset: 0x3F4 */ + __IO uint32_t CMSR2; /*!< Common status register 2 Address offset: 0x3F8 */ + __IO uint32_t CMFCR; /*!< Common interrupt clear register Address offset: 0x3FC */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x400 */ + __IO uint32_t P0FSCR; /*!< Pipe0 flow selection configuration register Address offset: 0x404 */ + __IO uint32_t RESERVED7[62]; /*!< Reserved, Address offset: 0x408-0x4FC */ + __IO uint32_t P0FCTCR; /*!< Pipe0 flow control configuration register Address offset: 0x500 */ + __IO uint32_t P0SCSTR; /*!< Pipe0 stat/crop start register Address offset: 0x504 */ + __IO uint32_t P0SCSZR; /*!< Pipe0 stat/crop size register Address offset: 0x508 */ + __IO uint32_t RESERVED8[41]; /*!< Reserved, Address offset: 0x50C-0x5AC */ + __IO uint32_t P0DCCNTR; /*!< Pipe0 dump counter register Address offset: 0x5B0 */ + __IO uint32_t P0DCLMTR; /*!< Pipe0 dump limit register Address offset: 0x5B4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x5B8-0x5BC */ + __IO uint32_t P0PPCR; /*!< Pipe0 pixel packer configuration register Address offset: 0x5C0 */ + __IO uint32_t P0PPM0AR1; /*!< Pipe0 pixel packer memory0 address register 1 Address offset: 0x5C4 */ + __IO uint32_t P0PPM0AR2; /*!< Pipe0 pixel packer memory0 address register 2 Address offset: 0x5C8 */ + __IO uint32_t RESERVED10[10]; /*!< Reserved, Address offset: 0x5CC-0x5F0 */ + __IO uint32_t P0IER; /*!< Pipe0 interrupt enable register Address offset: 0x5F4 */ + __IO uint32_t P0SR; /*!< Pipe0 status register Address offset: 0x5F8 */ + __IO uint32_t P0FCR; /*!< Pipe0 interrupt clear register Address offset: 0x5FC */ + __IO uint32_t RESERVED11[64]; /*!< Reserved, Address offset: 0x600-0x6FC */ + __IO uint32_t P0CFCTCR; /*!< Pipe0 current flow control configuration register Address offset: 0x700 */ + __IO uint32_t P0CSCSTR; /*!< Pipe0 current stat/crop start register Address offset: 0x704 */ + __IO uint32_t P0CSCSZR; /*!< Pipe0 current stat/crop size register Address offset: 0x708 */ + __IO uint32_t RESERVED12[45]; /*!< Reserved, Address offset: 0x70C-0x7BC */ + __IO uint32_t P0CPPCR; /*!< Pipe0 current pixel packer configuration register Address offset: 0x700 */ + __IO uint32_t P0CPPM0AR1; /*!< Pipe0 current pixel packer memory0 address register 1 Address offset: 0x7C4 */ + __IO uint32_t P0CPPM0AR2; /*!< Pipe0 current pixel packer memory0 address register 2 Address offset: 0x7C8 */ +} DCMIPP_TypeDef; + +/** + * @ brief Delay Block + */ +typedef struct +{ + __IO uint32_t CR; /*!< Delay Block Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA masked interrupt status register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */ +} DMA2D_TypeDef; + +/** + * @brief DTS + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */ + __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */ + __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */ + __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */ + __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */ +} DTS_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x08 */ + uint32_t RESERVED1[5]; /*!< Reserved 1, Address offset: 0x0C-0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x28 */ + uint32_t RESERVED2[21]; /*!< Reserved 2, Address offset: 0x2C-0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x84 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x88 */ + uint32_t RESERVED3; /*!< Reserved 3, Address offset: 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x94 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x98 */ + uint32_t RESERVED4; /*!< Reserved 4, Address offset: 0x9C */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register 3, Address offset: 0xA0 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register 3, Address offset: 0xA4 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x000 */ + __IO uint32_t KEYR; /*!< FLASH control key register, Address offset: 0x004 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x008 - 0x00C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x010 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t IER; /*!< FLASH interrupt enable register, Address offset: 0x020 */ + __IO uint32_t ISR; /*!< FLASH interrupt status register, Address offset: 0x024 */ + __IO uint32_t ICR; /*!< FLASH interrupt clear register, Address offset: 0x028 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t CRCCR; /*!< FLASH CRC control register, Address offset: 0x030 */ + __IO uint32_t CRCSADDR; /*!< FLASH CRC start address register, Address offset: 0x034 */ + __IO uint32_t CRCEADDR; /*!< FLASH CRC end address register, Address offset: 0x038 */ + __IO uint32_t CRCDATAR; /*!< FLASH CRC data register, Address offset: 0x03C */ + __IO uint32_t ECCSFADDR; /*!< FLASH ECC single fail address register, Address offset: 0x040 */ + __IO uint32_t ECCDFADDR; /*!< FLASH ECC double fail address register, Address offset: 0x044 */ + uint32_t RESERVED4[46]; /*!< Reserved, Address offset: 0x048 - 0x0FC */ + __IO uint32_t OPTKEYR; /*!< FLASH options key register, Address offset: 0x100 */ + __IO uint32_t OPTCR; /*!< FLASH options control register, Address offset: 0x104 */ + __IO uint32_t OPTISR; /*!< FLASH options interrupt status register, Address offset: 0x108 */ + __IO uint32_t OPTICR; /*!< FLASH options interrupt clear register, Address offset: 0x10C */ + __IO uint32_t OBKCR; /*!< FLASH option byte key control register, Address offset: 0x110 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x114 */ + __IO uint32_t OBKDR[8]; /*!< FLASH option bytes key data register, Address offset: 0x118 - 0x134 */ + uint32_t RESERVED6[50]; /*!< Reserved, Address offset: 0x138 - 0x1FC */ + __IO uint32_t NVSR; /*!< FLASH non-volatile status register, Address offset: 0x200 */ + __IO uint32_t NVSRP; /*!< FLASH security status register programming, Address offset: 0x204 */ + __IO uint32_t ROTSR; /*!< FLASH RoT status register, Address offset: 0x208 */ + __IO uint32_t ROTSRP; /*!< FLASH RoT status register programming, Address offset: 0x20C */ + __IO uint32_t OTPLSR; /*!< FLASH OTP lock status register, Address offset: 0x210 */ + __IO uint32_t OTPLSRP; /*!< FLASH OTP lock status programming register, Address offset: 0x214 */ + __IO uint32_t WRPSR; /*!< FLASH write protection status register, Address offset: 0x218 */ + __IO uint32_t WRPSRP; /*!< FLASH write protection status register programming, Address offset: 0x21C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x220 - 0x22C */ + __IO uint32_t HDPSR; /*!< FLASH hide protection status register, Address offset: 0x230 */ + __IO uint32_t HDPSRP; /*!< FLASH hide protection status register programming, Address offset: 0x234 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0x238 - 0x24C */ + __IO uint32_t EPOCHSR; /*!< FLASH epoch status register, Address offset: 0x250 */ + __IO uint32_t EPOCHSRP; /*!< FLASH epoch status register programming, Address offset: 0x254 */ + uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x258 - 0x25C */ + __IO uint32_t OBW1SR; /*!< FLASH option byte word 1 status register, Address offset: 0x260 */ + __IO uint32_t OBW1SRP; /*!< FLASH option byte word 1 status register programming, Address offset: 0x264 */ + __IO uint32_t OBW2SR; /*!< FLASH option byte word 2 status register, Address offset: 0x268 */ + __IO uint32_t OBW2SRP; /*!< FLASH option byte word 2 status register programming, Address offset: 0x26C */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1 + */ +typedef struct { + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1 Extended + */ +typedef struct { + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct { + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 & 6 + */ +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140 - 0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148 - 0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief GFXMMU + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved0, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + __IO uint32_t DAR; /*!< GFXMMU default alpha register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved1, Address offset: 0x18 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 0x00 */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 0x04 */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 0x08 */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0x0C */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 0x10 */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 0x14 */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 0x18 */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 0x1C */ + uint32_t RESERVED0[4]; /* Reserved Address offset: 0x20-0x2C */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 0x30 */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 0x34 */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 0x38 */ + uint32_t RESERVED1; /* Reserved Address offset: 0x3C */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 0x40 */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 0x44 */ + uint32_t RESERVED2[2]; /* Reserved Address offset: 0x48-0x4C */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 0x50-0x8C */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 0x90-0xCC */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: 0xD0-0x10C */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 0x110-0x14C */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 0x150-0x18C */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 0x190-0x20C */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 0x210-0x35C */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 0x360-0x4F8 */ + uint32_t RESERVED3; /* Reserved Address offset: 0x4FC */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 0x500-0x65C */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 0x660-0x7BC */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 0x7C0-0x7DC */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 0x7E0-0x7FC */ +} JPEG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + +/** + * @brief ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ +} MDF_TypeDef; + +/** + * @brief ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x94-0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + uint32_t RESERVED1[1]; /*!< Reserved, 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED3[10]; /*!< Reserved, 0xC8-0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief XSPI + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control Register, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration Register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration Register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration Register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration Register 4, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t SR; /*!< XSPI Status Register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear Register, Address offset: 0x024 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x028 - 0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length Register, Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address Register, Address offset: 0x048 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data Register, Address offset: 0x050 */ + uint32_t RESERVED6[11]; /*!< Reserved, Address offset: 0x054 - 0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask Register, Address offset: 0x080 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match Register, Address offset: 0x088 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval Register, Address offset: 0x090 */ + uint32_t RESERVED9[27]; /*!< Reserved, Address offset: 0x094 - 0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration Register, Address offset: 0x100 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration Register, Address offset: 0x108 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction Register, Address offset: 0x110 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x114 - 0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes Register, Address offset: 0x120 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x124 - 0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low-Power Timeout Register, Address offset: 0x130 */ + uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x134 - 0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration Register, Address offset: 0x140 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration Register, Address offset: 0x148 */ + uint32_t RESERVED16; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction Register, Address offset: 0x150 */ + uint32_t RESERVED17[3]; /*!< Reserved, Address offset: 0x154 - 0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes Register, Address offset: 0x160 */ + uint32_t RESERVED18[7]; /*!< Reserved, Address offset: 0x164 - 0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration Register, Address offset: 0x180 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration Register, Address offset: 0x188 */ + uint32_t RESERVED20; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction Register, Address offset: 0x190 */ + uint32_t RESERVED21[3]; /*!< Reserved, Address offset: 0x194 - 0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes Register, Address offset: 0x1A0 */ + uint32_t RESERVED22[23]; /*!< Reserved, Address offset: 0x1A4 - 0x1FC */ + __IO uint32_t HLCR; /*!< XSPI HyperBus Latency Configuration Register, Address offset: 0x200 */ + uint32_t RESERVED23[3]; /*!< Reserved, Address offset: 0x204 - 0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-Cycle Calibration Configuration Register, Address offset: 0x210 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL Master Calibration Configuration Register, Address offset: 0x218 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220 */ + uint32_t RESERVED26; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI Slave Input Calibration Configuration Register, Address offset: 0x228 */ +} XSPI_TypeDef; + +/** + * @brief XSPI IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPIM IO Manager Control Register, Address offset: 0x00 */ +} XSPIM_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x04 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x08 */ + __IO uint32_t CSR2; /*!< PWR power control status register 2, Address offset: 0x0C */ + __IO uint32_t CSR3; /*!< PWR power control status register 3, Address offset: 0x10 */ + __IO uint32_t CSR4; /*!< PWR power control status register 4, Address offset: 0x14 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< PWR USB Type-C and power delivery register, Address offset: 0x2C */ + __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x30 */ + __IO uint32_t PUCRN; /*!< PWR port N pull-up control register, Address offset: 0x34 */ + __IO uint32_t PDCRN; /*!< PWR port N pull-down control register, Address offset: 0x38 */ + __IO uint32_t PUCRO; /*!< PWR port O pull-up control register, Address offset: 0x3C */ + __IO uint32_t PDCRO; /*!< PWR port O pull-down control register, Address offset: 0x40 */ + __IO uint32_t PDCRP; /*!< PWR port P pull-down control register, Address offset: 0x44 */ + uint32_t RESERVED2[2]; /*!< Reserved */ + __IO uint32_t PDR1; /*!< PWR debug register 1, Address offset: 0x50 */ +} PWR_TypeDef; + +/** + * @brief Public Key Accelerator (PKA) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved1[253]; /*!< Reserved, Address offset: 0x000C-0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x0400-0x18D8 */ +} PKA_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI clock calibration register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock recovery RC register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI clock calibration register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CDCFGR; /*!< RCC CPU domain configuration register, Address offset: 0x18 */ + __IO uint32_t BMCFGR; /*!< RCC Bus matrix configuration register, Address offset: 0x1C */ + __IO uint32_t APBCFGR; /*!< RCC APB clock configuration register, Address offset: 0x20 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs clock source selection register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs configuration register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR1; /*!< RCC PLL1 dividers configuration register 1, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 fractional divider configuration register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR1; /*!< RCC PLL2 dividers configuration register 1, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 fractional divider configuration register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR1; /*!< RCC PLL3 dividers configuration register 1, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 fractional divider configuration register, Address offset: 0x44 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t CCIPR1; /*!< RCC AHB peripherals kernel clock configuration register Address offset: 0x4C */ + __IO uint32_t CCIPR2; /*!< RCC APB1 peripherals kernel clock configuration register Address offset: 0x50 */ + __IO uint32_t CCIPR3; /*!< RCC APB2 peripherals kernel clock configuration register Address offset: 0x54 */ + __IO uint32_t CCIPR4; /*!< RCC APB4/APB5 peripherals kernel clock configuration register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x68 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB5RSTR; /*!< RCC AHB5 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB5RSTR; /*!< RCC APB5 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x90 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0xA0 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0xA4 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0xA8-0xAC */ + __IO uint32_t CKGDISR ; /*!< RCC AXI clocks gating disable register, Address offset: 0xB0 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0xB4-0xBC */ + __IO uint32_t PLL1DIVR2; /*!< RCC PLL1 dividers configuration register 2, Address offset: 0xC0 */ + __IO uint32_t PLL2DIVR2; /*!< RCC PLL2 dividers configuration register 2, Address offset: 0xC4 */ + __IO uint32_t PLL3DIVR2; /*!< RCC PLL3 dividers configuration register 2, Address offset: 0xC8 */ + __IO uint32_t PLL1SSCGR; /*!< RCC PLL1 spread spectrum clock generator register, Address offset: 0xCC */ + __IO uint32_t PLL2SSCGR; /*!< RCC PLL2 spread spectrum clock generator register, Address offset: 0xD0 */ + __IO uint32_t PLL3SSCGR; /*!< RCC PLL3 spread spectrum clock generator register, Address offset: 0xD4 */ + uint32_t RESERVED9[10]; /*!< Reserved, Address offset: 0xD8-0xFC */ + __IO uint32_t CKPROTR; /*!< RCC clock protection register, Address offset: 0x100 */ + uint32_t RESERVED10[11]; /*!< Reserved, Address offset: 0x104-0x12C */ + __IO uint32_t RSR; /*!< RCC reset status register, Address offset: 0x130 */ + __IO uint32_t AHB5ENR; /*!< RCC AHB5 peripheral clocks enable register, Address offset: 0x134 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x138 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x13C */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clocks enable register, Address offset: 0x140 */ + __IO uint32_t APB5ENR; /*!< RCC APB5 peripheral clocks enable register, Address offset: 0x144 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x148 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x14C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x150 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clocks enable register, Address offset: 0x154 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x158 */ + __IO uint32_t AHB5LPENR; /*!< RCC AHB5 peripheral sleep clocks enable register, Address offset: 0x15C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clocks enable register, Address offset: 0x160 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clocks enable register, Address offset: 0x164 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clocks enable register, Address offset: 0x168 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clocks enable register, Address offset: 0x16C */ + __IO uint32_t APB1LPENR1; /*!< RCC APB1 peripheral sleep clocks enable register 1, Address offset: 0x170 */ + __IO uint32_t APB1LPENR2; /*!< RCC APB1 peripheral sleep clocks enable register 2, Address offset: 0x174 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clocks enable register, Address offset: 0x178 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clocks enable register, Address offset: 0x17C */ + __IO uint32_t APB5LPENR; /*!< RCC APB5 peripheral sleep clocks enable register, Address offset: 0x180 */ +} RCC_TypeDef; + +/** + * @brief Random Number Generator + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration, boot and security controller + */ +typedef struct +{ + __IO uint32_t BOOTSR; /*!< SBS Boot Status register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04-0x0C */ + __IO uint32_t HDPLCR; /*!< SBS Hide Protection Control register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS Hide Protection Status register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x28-0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command register, Address offset: 0x34 */ + uint32_t RESERVED4[50]; /*!< Reserved, Address offset: 0x38-0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status register, Address offset: 0x108 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS IO Compensation Cell Control and Status register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS IO Compensation Cell Value register, Address offset: 0x114 */ + __IO uint32_t CCSWVALR; /*!< SBS IO Compensation Cell Software Value register, Address offset: 0x118 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x11C */ + __IO uint32_t BKLOCKR; /*!< SBS Break Lockup register, Address offset: 0x120 */ + uint32_t RESERVED7[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t EXTICR[4]; /*!< SBS External Interrupt Configuration registers, Address offset: 0x130-0x13C */ +} SBS_TypeDef; + +/** + * @brief Secure Digital Card/IO Embedded MultiMediaCard Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC Power control register, Address offset : 0x000 */ + __IO uint32_t CLKCR; /*!< SDMMC Clock control register, Address offset : 0x004 */ + __IO uint32_t ARG; /*!< SDMMC Argument register, Address offset : 0x008 */ + __IO uint32_t CMD; /*!< SDMMC Command register, Address offset : 0x00C */ + __IO uint32_t RESPCMD; /*!< SDMMC Command response register, Address offset : 0x010 */ + __IO uint32_t RESP1; /*!< SDMMC Response 1 register, Address offset : 0x014 */ + __IO uint32_t RESP2; /*!< SDMMC Response 2 register, Address offset : 0x018 */ + __IO uint32_t RESP3; /*!< SDMMC Response 3 register, Address offset : 0x01C */ + __IO uint32_t RESP4; /*!< SDMMC Response 4 register, Address offset : 0x020 */ + __IO uint32_t DTIMER; /*!< SDMMC Data timer register, Address offset : 0x024 */ + __IO uint32_t DLEN; /*!< SDMMC Data length register, Address offset : 0x028 */ + __IO uint32_t DCTRL; /*!< SDMMC Data control register, Address offset : 0x02C */ + __IO uint32_t DCOUNT; /*!< SDMMC Data counter register, Address offset : 0x030 */ + __IO uint32_t STA; /*!< SDMMC Status register, Address offset : 0x034 */ + __IO uint32_t ICR; /*!< SDMMC Interrupt clear register, Address offset : 0x038 */ + __IO uint32_t MASK; /*!< SDMMC Mask register, Address offset : 0x03C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset : 0x040 */ + uint32_t RESERVED0[3]; /*!< Reserved, Address offset : 0x044 - 0x04C */ + __IO uint32_t IDMACTRL; /*!< SDMMC IDMA control register, Address offset : 0x050 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC IDMA buffer size register, Address offset : 0x054 */ + __IO uint32_t IDMABASER; /*!< SDMMC IDMA buffer base address register, Address offset : 0x058 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset : 0x05C - 0x060 */ + __IO uint32_t IDMALAR; /*!< SDMMC IDMA linked list address register, Address offset : 0x064 */ + __IO uint32_t IDMABAR; /*!< SDMMC IDMA linked list memory base register, Address offset : 0x068 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset : 0x06C - 0x07C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset : 0x080 */ +} SDMMC_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t CFGR; /*!< TAMP configuration control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter 1 register, Address offset: 0x40 */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED5[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + uint32_t RESERVED0[221]; /*!< Reserved, Address offset: 0x68 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Window Watchdog + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32H7RSxx_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup STM32H7RSxx_Peripheral_peripheralAddr + * @{ + */ +#define ITCM_BASE 0x00000000UL /*!< ITCM base address */ +#define FLASH_BASE 0x08000000UL /*!< User Flash address */ +#define OTP_AREA_BASE 0x08FFF000UL /*!< OTP Area base address */ +#define ENGI_BYTES_BASE 0x52002800UL /*!< Engi Bytes */ +#define SYSTEM_FLASH_BASE 0x1FF00000UL /*!< System Flash base address */ +#define DTCM_BASE 0x20000000UL /*!< DTCM base address */ +#define SRAM1_AXI_BASE 0x24000000UL /*!< SRAM1 base address - accessible over AXI */ +#define SRAM2_AXI_BASE 0x24020000UL /*!< SRAM2 base address - accessible over AXI */ +#define SRAM3_AXI_BASE 0x24040000UL /*!< SRAM3 base address - accessible over AXI */ +#define SRAM4_AXI_BASE 0x24060000UL /*!< SRAM4 base address - accessible over AXI */ + +#define GFXMMU_VIRTUAL_BUFFER0_BASE 0x25000000UL /*!< GFXMMU virtual buffer 0 base address */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE 0x25400000UL /*!< GFXMMU virtual buffer 1 base address */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE 0x25800000UL /*!< GFXMMU virtual buffer 2 base address */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE 0x25C00000UL /*!< GFXMMU virtual buffer 3 base address */ + +#define SRAM1_AHB_BASE 0x30000000UL /*!< SRAM1 base address */ +#define SRAM2_AHB_BASE 0x30004000UL /*!< SRAM2 base address */ +#define BKPSRAM_BASE 0x38800000UL /*!< Backup SRAM */ + +#define PERIPH_BASE 0x40000000UL /*!< AHB and APB Peripherals base address */ +#define XSPI2_BASE 0x70000000UL /*!< XSPI2 base address */ +#define XSPI1_BASE 0x90000000UL /*!< XSPI1 base address */ + +/*!< Internal memory size */ +#define ITCM_SIZE 0x00010000UL /*!< 64 KB default, can be increased up to 192 KB */ +#define DTCM_SIZE 0x00010000UL /*!< 64 KB default, can be increased up to 192 KB */ +#define FLASH_SIZE 0x00010000UL /*!< 64 KB */ +#define SRAM1_AXI_SIZE 0x00020000UL /*!< 128 KB default, can be decreased down to 0 KB to increase ITCM */ +#define SRAM2_AXI_SIZE 0x00020000UL /*!< 128 KB */ +#define SRAM3_AXI_SIZE 0x00020000UL /*!< 128 KB default, can be decreased down to 0 KB to increase DTCM */ +#define SRAM4_AXI_SIZE 0x00012000UL /*!< 72 KB default, can be decreased to 0 KB when RAM ECC is disable */ +#define SRAM_AHB_SIZE 0x00004000UL /*!< Both AHB SRAMs are 16 KB */ +#define BKPSRAM_SIZE 0x00001000UL /*!< 4 KB */ + +/*!< OTP Area size */ +#define OTP_SIZE 0x400U /* 1 KB */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x02000000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x08020000UL) +#define APB5PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define AHB5PERIPH_BASE (PERIPH_BASE + 0x12000000UL) +#define APB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define AHB4PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I3C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x8400UL) +#define MDIOS_BASE (APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0xA100UL) /*!< FDCAN configuration registers base address */ +#define FDCAN2_BASE (APB1PERIPH_BASE + 0xA400UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xAC00UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xEC00UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00UL) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define GPDMA1_Channel0_BASE (GPDMA1_BASE + 0x0050UL) +#define GPDMA1_Channel1_BASE (GPDMA1_BASE + 0x00D0UL) +#define GPDMA1_Channel2_BASE (GPDMA1_BASE + 0x0150UL) +#define GPDMA1_Channel3_BASE (GPDMA1_BASE + 0x01D0UL) +#define GPDMA1_Channel4_BASE (GPDMA1_BASE + 0x0250UL) +#define GPDMA1_Channel5_BASE (GPDMA1_BASE + 0x02D0UL) +#define GPDMA1_Channel6_BASE (GPDMA1_BASE + 0x0350UL) +#define GPDMA1_Channel7_BASE (GPDMA1_BASE + 0x03D0UL) +#define GPDMA1_Channel8_BASE (GPDMA1_BASE + 0x0450UL) +#define GPDMA1_Channel9_BASE (GPDMA1_BASE + 0x04D0UL) +#define GPDMA1_Channel10_BASE (GPDMA1_BASE + 0x0550UL) +#define GPDMA1_Channel11_BASE (GPDMA1_BASE + 0x05D0UL) +#define GPDMA1_Channel12_BASE (GPDMA1_BASE + 0x0650UL) +#define GPDMA1_Channel13_BASE (GPDMA1_BASE + 0x06D0UL) +#define GPDMA1_Channel14_BASE (GPDMA1_BASE + 0x0750UL) +#define GPDMA1_Channel15_BASE (GPDMA1_BASE + 0x07D0UL) +#define ADC1_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) +#define ADF1_BASE (AHB1PERIPH_BASE + 0xF000UL) +#define ADF1_Filter0_BASE (ADF1_BASE + 0x0080UL) +#define USB_OTG_HS_PERIPH_BASE (AHB1PERIPH_BASE + 0x20000UL) +#define USB_OTG_FS_PERIPH_BASE (AHB1PERIPH_BASE + 0x60000UL) + +/*!< AHB2 peripherals */ +#define PSSI_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define SDMMC2_BASE (AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (AHB2PERIPH_BASE + 0x2800UL) +#define CORDIC_BASE (AHB2PERIPH_BASE + 0x4400UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE AHB3PERIPH_BASE +#define HASH_BASE (AHB3PERIPH_BASE + 0x0400UL) +#define HASH_DIGEST_BASE (AHB3PERIPH_BASE + 0x0710UL) +#define PKA_BASE (AHB3PERIPH_BASE + 0x2000UL) + +/*!< APB5 peripherals */ +#define DCMIPP_BASE (APB5PERIPH_BASE + 0x2000UL) +#define GFXTIM_BASE (APB5PERIPH_BASE + 0x4000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE AHB5PERIPH_BASE +#define HPDMA1_Channel0_BASE (HPDMA1_BASE + 0x0050UL) +#define HPDMA1_Channel1_BASE (HPDMA1_BASE + 0x00D0UL) +#define HPDMA1_Channel2_BASE (HPDMA1_BASE + 0x0150UL) +#define HPDMA1_Channel3_BASE (HPDMA1_BASE + 0x01D0UL) +#define HPDMA1_Channel4_BASE (HPDMA1_BASE + 0x0250UL) +#define HPDMA1_Channel5_BASE (HPDMA1_BASE + 0x02D0UL) +#define HPDMA1_Channel6_BASE (HPDMA1_BASE + 0x0350UL) +#define HPDMA1_Channel7_BASE (HPDMA1_BASE + 0x03D0UL) +#define HPDMA1_Channel8_BASE (HPDMA1_BASE + 0x0450UL) +#define HPDMA1_Channel9_BASE (HPDMA1_BASE + 0x04D0UL) +#define HPDMA1_Channel10_BASE (HPDMA1_BASE + 0x0550UL) +#define HPDMA1_Channel11_BASE (HPDMA1_BASE + 0x05D0UL) +#define HPDMA1_Channel12_BASE (HPDMA1_BASE + 0x0650UL) +#define HPDMA1_Channel13_BASE (HPDMA1_BASE + 0x06D0UL) +#define HPDMA1_Channel14_BASE (HPDMA1_BASE + 0x0750UL) +#define HPDMA1_Channel15_BASE (HPDMA1_BASE + 0x07D0UL) +#define DMA2D_BASE (AHB5PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB5PERIPH_BASE + 0x2000UL) +#define JPEG_BASE (AHB5PERIPH_BASE + 0x3000UL) +#define FMC_R_BASE (AHB5PERIPH_BASE + 0x4000UL) +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) +#define XSPI1_R_BASE (AHB5PERIPH_BASE + 0x5000UL) +#define SDMMC1_BASE (AHB5PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (AHB5PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (AHB5PERIPH_BASE + 0x9000UL) +#define RAMECC1_Monitor0_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0xA0UL) +#define XSPI2_R_BASE (AHB5PERIPH_BASE + 0xA000UL) +#define XSPIM_BASE (AHB5PERIPH_BASE + 0xB400UL) +#define GFXMMU_BASE (AHB5PERIPH_BASE + 0x010000UL) + +/*!< APB4 peripherals */ +#define EXTI_BASE APB4PERIPH_BASE +#define SBS_BASE (APB4PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (APB4PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (APB4PERIPH_BASE + 0x1400UL) +#define LPTIM2_BASE (APB4PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (APB4PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (APB4PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (APB4PERIPH_BASE + 0x3000UL) +#define VREFBUF_BASE (APB4PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (APB4PERIPH_BASE + 0x4000UL) +#define TAMP_BASE (APB4PERIPH_BASE + 0x4400UL) +#define IWDG_BASE (APB4PERIPH_BASE + 0x4800UL) +#define DTS_BASE (APB4PERIPH_BASE + 0x6800UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE AHB4PERIPH_BASE +#define GPIOB_BASE (AHB4PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB4PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB4PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB4PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB4PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB4PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB4PERIPH_BASE + 0x1C00UL) +#define GPIOM_BASE (AHB4PERIPH_BASE + 0x3000UL) +#define GPION_BASE (AHB4PERIPH_BASE + 0x3400UL) +#define GPIOO_BASE (AHB4PERIPH_BASE + 0x3800UL) +#define GPIOP_BASE (AHB4PERIPH_BASE + 0x3C00UL) +#define RCC_BASE (AHB4PERIPH_BASE + 0x4400UL) +#define PWR_BASE (AHB4PERIPH_BASE + 0x4800UL) +#define CRC_BASE (AHB4PERIPH_BASE + 0x4C00UL) +#define RAMECC2_BASE (AHB4PERIPH_BASE + 0x7000UL) +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x40UL) + +/*!< Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +/*!< AXIM registers base address */ +#define AXIM_BASE (0xBFF00000UL) +#define AXIM_ASIB1_BASE (AXIM_BASE + 0x42000UL) +#define AXIM_ASIB2_BASE (AXIM_BASE + 0x43000UL) +#define AXIM_ASIB3_BASE (AXIM_BASE + 0x44000UL) +#define AXIM_ASIB4_BASE (AXIM_BASE + 0x45000UL) +#define AXIM_ASIB5_BASE (AXIM_BASE + 0x46000UL) +#define AXIM_ASIB6_BASE (AXIM_BASE + 0x47000UL) +#define AXIM_ASIB7_BASE (AXIM_BASE + 0x48000UL) +#define AXIM_ASIB8_BASE (AXIM_BASE + 0x49000UL) +#define AXIM_ASIB9_BASE (AXIM_BASE + 0x4A000UL) +#define AXIM_ASIB10_BASE (AXIM_BASE + 0x4B000UL) +#define AXIM_ASIB11_BASE (AXIM_BASE + 0x4C000UL) +#define AXIM_AMIB1_BASE (AXIM_BASE + 0x02000UL) +#define AXIM_AMIB2_BASE (AXIM_BASE + 0x03000UL) +#define AXIM_AMIB3_BASE (AXIM_BASE + 0x04000UL) +#define AXIM_AMIB4_BASE (AXIM_BASE + 0x05000UL) +#define AXIM_AMIB5_BASE (AXIM_BASE + 0x06000UL) +#define AXIM_AMIB6_BASE (AXIM_BASE + 0x07000UL) +#define AXIM_AMIB7_BASE (AXIM_BASE + 0x08000UL) +#define AXIM_AMIB8_BASE (AXIM_BASE + 0x09000UL) +#define AXIM_AMIB9_BASE (AXIM_BASE + 0x0A000UL) +#define AXIM_AMIB10_BASE (AXIM_BASE + 0x0B000UL) + +/*!< Unique device ID register base address */ +#define UID_BASE (0x08FFF800UL) + +/*!< Flash size data register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) + +/*!< Package data register base address */ +#define PACKAGE_BASE (0x08FFF80CUL) + +/* USB OTG registers base addresses */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_PFUNC_START (0x1FF1FD4CUL) +#define RSSLIB_SYS_FLASH_PFUNC_END (0x1FF1FD78UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0x1FF1FD4CUL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t Destination; /*!< OBKeys destination information where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + +/** + * @brief Prototype of RSSLIB Set Secure OB Function + * @detail This function configure a secure OB. + * @param OB address among following values: + * &(FLASH->WRPSRP), &(FLASH->HDPSRP) or &(FLASH->ROTSRP) + * @param OB mask (example 0x000000FF for updating WRP OB). + * @param OB value + * @param OB Pos: bit position of OB value. + * ObValue << ObPos must be aligned on ObMask. + * @retval RSSLIB_RSS_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_SetSecOB_TypeDef)(uint32_t ObAddr, uint32_t ObMask, uint32_t ObValue, uint32_t ObPos); + +/** + * @brief Prototype of RSSLIB Get RSS Status Function + * @detail This function return RSS Status. + * Calling GetRssStatus is only relevant after calling + * SetSecOB or DataProvisioning. + * @param none. + * @retval RSSLIB_SUCCESS on success, otherwise return an error 0xF5F5xxxx. + */ +typedef uint32_t (*RSSLIB_GetRssStatus_TypeDef)(void); + +/** + * @brief Prototype of RSSLIB Set Product State Function + * @detail This function change Product State. + * @param Requested Product State among following values: + * 0x17 : Provisioning + * 0x72 : Closed + * 0x5C : Locked + * @retval RSSLIB_RSS_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_SetProductState_TypeDef)(uint32_t ProductState); + +/** + * @brief Prototype of RSSLIB Get Product State Function + * @detail This function return current Product State. + * @param none. + * @retval RSSLIB_RSS_ERROR on error, + * otherwise return product state among following values: + * 0x39 : Open + * 0x17 : Provisioning + * 0x72 : Closed + * 0x5C : Locked + */ +typedef uint32_t (*RSSLIB_GetProductState_TypeDef)(void); + + +/** + * @brief RSSLib callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_SetSecOB_TypeDef SetSecOB; + uint32_t RESERVED1[4]; + __IM RSSLIB_GetRssStatus_TypeDef GetRssStatus; + __IM RSSLIB_SetProductState_TypeDef SetProductState; + __IM RSSLIB_DataProvisioning_TypeDef DataProvisioning; + __IM RSSLIB_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_GetProductState_TypeDef GetProductState; +} RSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32H7RSxx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H7RSxx_Peripheral_declaration + * @{ + */ + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADF1 ((MDF_TypeDef *) ADF1_BASE) +#define ADF1_Filter0 ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE) +#define AXIM_AMIB_1 ((AXIM_AMIB_TypeDef *) AXIM_AMIB1_BASE ) +#define AXIM_AMIB_2 ((AXIM_AMIB_TypeDef *) AXIM_AMIB2_BASE ) +#define AXIM_AMIB_3 ((AXIM_AMIB_TypeDef *) AXIM_AMIB3_BASE ) +#define AXIM_AMIB_4 ((AXIM_AMIB_TypeDef *) AXIM_AMIB4_BASE ) +#define AXIM_AMIB_5 ((AXIM_AMIB_TypeDef *) AXIM_AMIB5_BASE ) +#define AXIM_AMIB_6 ((AXIM_AMIB_TypeDef *) AXIM_AMIB6_BASE ) +#define AXIM_AMIB_7 ((AXIM_AMIB_TypeDef *) AXIM_AMIB7_BASE ) +#define AXIM_AMIB_8 ((AXIM_AMIB_TypeDef *) AXIM_AMIB8_BASE ) +#define AXIM_AMIB_9 ((AXIM_AMIB_TypeDef *) AXIM_AMIB9_BASE ) +#define AXIM_AMIB_10 ((AXIM_AMIB_TypeDef *) AXIM_AMIB10_BASE) +#define AXIM_ASIB_1 ((AXIM_ASIB_TypeDef *) AXIM_ASIB1_BASE ) +#define AXIM_ASIB_2 ((AXIM_ASIB_TypeDef *) AXIM_ASIB2_BASE ) +#define AXIM_ASIB_3 ((AXIM_ASIB_TypeDef *) AXIM_ASIB3_BASE ) +#define AXIM_ASIB_4 ((AXIM_ASIB_TypeDef *) AXIM_ASIB4_BASE ) +#define AXIM_ASIB_5 ((AXIM_ASIB_TypeDef *) AXIM_ASIB5_BASE ) +#define AXIM_ASIB_6 ((AXIM_ASIB_TypeDef *) AXIM_ASIB6_BASE ) +#define AXIM_ASIB_7 ((AXIM_ASIB_TypeDef *) AXIM_ASIB7_BASE ) +#define AXIM_ASIB_8 ((AXIM_ASIB_TypeDef *) AXIM_ASIB8_BASE ) +#define AXIM_ASIB_9 ((AXIM_ASIB_TypeDef *) AXIM_ASIB9_BASE ) +#define AXIM_ASIB_10 ((AXIM_ASIB_TypeDef *) AXIM_ASIB10_BASE) +#define AXIM_ASIB_11 ((AXIM_ASIB_TypeDef *) AXIM_ASIB11_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define DCMIPP ((DCMIPP_TypeDef *) DCMIPP_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DTS ((DTS_TypeDef *) DTS_BASE) +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define GFXTIM ((GFXTIM_TypeDef *) GFXTIM_BASE) +#define GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE) +#define GPDMA1 ((DMA_TypeDef *) GPDMA1_BASE) +#define GPDMA1_Channel0 ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE) +#define GPDMA1_Channel1 ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE) +#define GPDMA1_Channel2 ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE) +#define GPDMA1_Channel3 ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE) +#define GPDMA1_Channel4 ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE) +#define GPDMA1_Channel5 ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE) +#define GPDMA1_Channel6 ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE) +#define GPDMA1_Channel7 ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE) +#define GPDMA1_Channel8 ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE) +#define GPDMA1_Channel9 ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE) +#define GPDMA1_Channel10 ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE) +#define GPDMA1_Channel11 ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE) +#define GPDMA1_Channel12 ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE) +#define GPDMA1_Channel13 ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE) +#define GPDMA1_Channel14 ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE) +#define GPDMA1_Channel15 ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOM ((GPIO_TypeDef *) GPIOM_BASE) +#define GPION ((GPIO_TypeDef *) GPION_BASE) +#define GPIOO ((GPIO_TypeDef *) GPIOO_BASE) +#define GPIOP ((GPIO_TypeDef *) GPIOP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define HPDMA1 ((DMA_TypeDef *) HPDMA1_BASE) +#define HPDMA1_Channel0 ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE) +#define HPDMA1_Channel1 ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE) +#define HPDMA1_Channel2 ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE) +#define HPDMA1_Channel3 ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE) +#define HPDMA1_Channel4 ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE) +#define HPDMA1_Channel5 ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE) +#define HPDMA1_Channel6 ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE) +#define HPDMA1_Channel7 ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE) +#define HPDMA1_Channel8 ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE) +#define HPDMA1_Channel9 ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE) +#define HPDMA1_Channel10 ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE) +#define HPDMA1_Channel11 ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE) +#define HPDMA1_Channel12 ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE) +#define HPDMA1_Channel13 ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE) +#define HPDMA1_Channel14 ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE) +#define HPDMA1_Channel15 ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE) +#define JPEG ((JPEG_TypeDef *) JPEG_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I3C1 ((I3C_TypeDef *) I3C1_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) +#define PKA ((PKA_TypeDef *) PKA_BASE) +#define PSSI ((PSSI_TypeDef *) PSSI_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC1_Monitor0 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor0_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *) SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *) SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *) SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *) SAI2_Block_B_BASE) +#define SBS ((SBS_TypeDef *) SBS_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define XSPI1 ((XSPI_TypeDef *) XSPI1_R_BASE) +#define XSPI2 ((XSPI_TypeDef *) XSPI2_R_BASE) +#define XSPIM ((XSPIM_TypeDef *) XSPIM_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) + +/** @} */ /* End of group STM32H7RSxx_Peripheral_declaration */ + +/** @addtogroup STM32H7RSxx_Peripheral_Exported_constants + * @{ + */ + +/** @addtogroup STM32H7RSxx_Peripheral_Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_Peripheral_Registers_Bits_Definition + * @{ + */ +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_ADFCFG_Pos (2U) +#define ADC_CFGR_ADFCFG_Msk (0x1UL << ADC_CFGR_ADFCFG_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_ADFCFG ADC_CFGR_ADFCFG_Msk /*!< ADC ADF transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register ***************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x1UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC internal path to VDDCORE */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ + +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************************************************************************/ +/* */ +/* AXIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AXIM_ASIB_FNMOD2 register **********/ +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE_Pos (0U) +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE_Msk (0x1UL << AXIM_ASIB_FNMOD2_BYPASS_MERGE_Pos) /*!< 0x00000001 */ +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE AXIM_ASIB_FNMOD2_BYPASS_MERGE_Msk /*!< Bypass Merge enable */ + +/******************* Bit definition for AXIM_ASIB_READQOS register ********/ +#define AXIM_ASIB_READQOS_AR_QOS_Pos (0U) +#define AXIM_ASIB_READQOS_AR_QOS_Msk (0xFUL << AXIM_ASIB_READQOS_AR_QOS_Pos) /*!< 0x0000000F */ +#define AXIM_ASIB_READQOS_AR_QOS AXIM_ASIB_READQOS_AR_QOS_Msk /*!< Read channel QoS setting */ + +/******************* Bit definition for AXIM_ASIB_WRITEQOS register *******/ +#define AXIM_ASIB_WRITEQOS_AW_QOS_Pos (0U) +#define AXIM_ASIB_WRITEQOS_AW_QOS_Msk (0xFUL << AXIM_ASIB_WRITEQOS_AW_QOS_Pos) /*!< 0x0000000F */ +#define AXIM_ASIB_WRITEQOS_AW_QOS AXIM_ASIB_WRITEQOS_AW_QOS_Msk /*!< Write channel QoS setting */ + +/******************* Bit definition for AXIM_ASIB_FNMOD register **********/ +#define AXIM_ASIB_FNMOD_READ_ISS_Pos (0U) +#define AXIM_ASIB_FNMOD_READ_ISS_Msk (0x1UL << AXIM_ASIB_FNMOD_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_ASIB_FNMOD_READ_ISS AXIM_ASIB_FNMOD_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_ASIB_FNMOD_WRITE_ISS_Pos (1U) +#define AXIM_ASIB_FNMOD_WRITE_ISS_Msk (0x1UL << AXIM_ASIB_FNMOD_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_ASIB_FNMOD_WRITE_ISS AXIM_ASIB_FNMOD_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************* Bit definition for AXIM_AMIB_FNMODBMISS register **********/ +#define AXIM_AMIB_FNMODBMISS_READ_ISS_Pos (0U) +#define AXIM_AMIB_FNMODBMISS_READ_ISS_Msk (0x1UL << AXIM_AMIB_FNMODBMISS_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMODBMISS_READ_ISS AXIM_AMIB_FNMODBMISS_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS_Pos (1U) +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS_Msk (0x1UL << AXIM_AMIB_FNMODBMISS_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS AXIM_AMIB_FNMODBMISS_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************* Bit definition for AXIM_AMIB_FNMOD2 register **********/ +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE_Pos (0U) +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE_Msk (0x1UL << AXIM_AMIB_FNMOD2_BYPASS_MERGE_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE AXIM_AMIB_FNMOD2_BYPASS_MERGE_Msk /*!< Bypass Merge enable */ + +/******************* Bit definition for AXIM_AMIB_FNMODLB register **********/ +#define AXIM_AMIB_FNMODLB_LONG_BURST_Pos (0U) +#define AXIM_AMIB_FNMODLB_LONG_BURST_Msk (0x1UL << AXIM_AMIB_FNMODLB_LONG_BURST_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMODLB_LONG_BURST AXIM_AMIB_FNMODLB_LONG_BURST_Msk /*!< Long bursts can be generated */ + +/******************* Bit definition for AXIM_AMIB_FNMOD register **********/ +#define AXIM_AMIB_FNMOD_READ_ISS_Pos (0U) +#define AXIM_AMIB_FNMOD_READ_ISS_Msk (0x1UL << AXIM_AMIB_FNMOD_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMOD_READ_ISS AXIM_AMIB_FNMOD_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_AMIB_FNMOD_WRITE_ISS_Pos (1U) +#define AXIM_AMIB_FNMOD_WRITE_ISS_Msk (0x1UL << AXIM_AMIB_FNMOD_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_AMIB_FNMOD_WRITE_ISS AXIM_AMIB_FNMOD_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* Parallel Synchronous Slave Interface (PSSI ) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PSSI_CR register *******************/ +#define PSSI_CR_CKPOL_Pos (5U) +#define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) /*!< 0x00000020 */ +#define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk /*!< Parallel data clock polarity */ +#define PSSI_CR_DEPOL_Pos (6U) +#define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) /*!< 0x00000040 */ +#define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk /*!< Data enable polarity */ +#define PSSI_CR_RDYPOL_Pos (8U) +#define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) /*!< 0x00000100 */ +#define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk /*!< Ready polarity */ +#define PSSI_CR_EDM_Pos (10U) +#define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define PSSI_CR_EDM PSSI_CR_EDM_Msk /*!< Extended data mode */ +#define PSSI_CR_ENABLE_Pos (14U) +#define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk /*!< PSSI enable */ +#define PSSI_CR_DERDYCFG_Pos (18U) +#define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< 0x001C0000 */ +#define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk /*!< Data enable and ready configuration */ +#define PSSI_CR_CKSRC_Pos (29U) +#define PSSI_CR_CKSRC_Msk (0x1UL << PSSI_CR_CKSRC_Pos) /*!< 0x20000000 */ +#define PSSI_CR_CKSRC PSSI_CR_CKSRC_Msk /*!< Clock source */ +#define PSSI_CR_DMAEN_Pos (30U) +#define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) /*!< 0x40000000 */ +#define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk /*!< DMA enable */ +#define PSSI_CR_OUTEN_Pos (31U) +#define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) /*!< 0x80000000 */ +#define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk /*!< Data direction selection */ + +/******************** Bit definition for PSSI_SR register *******************/ +#define PSSI_SR_RTT4B_Pos (2U) +#define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) /*!< 0x00000004 */ +#define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk /*!< Ready to transfer four bytes */ +#define PSSI_SR_RTT1B_Pos (3U) +#define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) /*!< 0x00000008 */ +#define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk /*!< Ready to transfer one byte */ + +/******************** Bit definition for PSSI_RIS register ******************/ +#define PSSI_RIS_OVR_RIS_Pos (1U) +#define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk /*!< Data buffer overrun/underrun raw interrupt status */ + +/******************** Bit definition for PSSI_IER register ******************/ +#define PSSI_IER_OVR_IE_Pos (1U) +#define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk /*!< Data buffer overrun/underrun interrupt enable */ + +/******************** Bit definition for PSSI_MIS register ******************/ +#define PSSI_MIS_OVR_MIS_Pos (1U) +#define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk /*!< Data buffer overrun/underrun masked interrupt status */ + +/******************** Bit definition for PSSI_ICR register ******************/ +#define PSSI_ICR_OVR_ISC_Pos (1U) +#define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk /*!< Data buffer overrun/underrun interrupt status clear */ + +/******************** Bit definition for PSSI_DR register *******************/ +#define PSSI_DR_DR_Pos (0U) +#define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) /*!< 0xFFFFFFF */ +#define PSSI_DR_DR PSSI_DR_DR_Msk /*!< Data register */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CR1 register *******************/ +#define PWR_CR1_SVOS_Pos (0U) +#define PWR_CR1_SVOS_Msk (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00000001 */ +#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection. */ + +#define PWR_CR1_PVDE_Pos (4U) +#define PWR_CR1_PVDE_Msk (0x1UL << PWR_CR1_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR1_PVDE PWR_CR1_PVDE_Msk /*!< Programmable Voltage detector enable. */ + +#define PWR_CR1_PLS_Pos (5U) +#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */ +#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */ + +#define PWR_CR1_DBP_Pos (8U) +#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */ + +#define PWR_CR1_FLPS_Pos (9U) +#define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) /*!< 0x00000200 */ +#define PWR_CR1_FLPS PWR_CR1_FLPS_Msk /*!< Flash low power mode in STOP */ + +#define PWR_CR1_BOOSTE_Pos (11U) +#define PWR_CR1_BOOSTE_Msk (0x1UL << PWR_CR1_BOOSTE_Pos) /*!< 0x00000800 */ +#define PWR_CR1_BOOSTE PWR_CR1_BOOSTE_Msk /*!< Analog Switch VBoost control. */ + +#define PWR_CR1_AVDREADY_Pos (12) +#define PWR_CR1_AVDREADY_Msk (0x1UL << PWR_CR1_AVDREADY_Pos) /*!< 0x00001000 */ +#define PWR_CR1_AVDREADY PWR_CR1_AVDREADY_Msk /*!< Analog Voltage Ready. */ + +#define PWR_CR1_AVDEN_Pos (13U) +#define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) /*!< 0x00002000 */ +#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */ + +#define PWR_CR1_ALS_Pos (14U) +#define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x0000A000 */ +#define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */ +#define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) /*!< 0x00004000 */ +#define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for PWR_SR1 register ********************/ +#define PWR_SR1_ACTVOS_Pos (0U) +#define PWR_SR1_ACTVOS_Msk (0x1UL << PWR_SR1_ACTVOS_Pos) /*!< 0x00000001 */ +#define PWR_SR1_ACTVOS PWR_SR1_ACTVOS_Msk /*!< VOS currently applied for VCORE voltage scaling selection */ + +#define PWR_SR1_ACTVOSRDY_Pos (1U) +#define PWR_SR1_ACTVOSRDY_Msk (0x1UL << PWR_SR1_ACTVOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_SR1_ACTVOSRDY PWR_SR1_ACTVOSRDY_Msk /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling */ + +#define PWR_SR1_PVDO_Pos (4U) +#define PWR_SR1_PVDO_Msk (0x1UL << PWR_SR1_PVDO_Pos) /*!< 0x00000010 */ +#define PWR_SR1_PVDO PWR_SR1_PVDO_Msk /*!< Programmable Voltage Detect Output */ + +#define PWR_SR1_AVDO_Pos (13U) +#define PWR_SR1_AVDO_Msk (0x1UL << PWR_SR1_AVDO_Pos) /*!< 0x00002000 */ +#define PWR_SR1_AVDO PWR_SR1_AVDO_Msk /*!< Analog Voltage Detect Output on VDDA */ + +/******************** Bit definition for PWR_CSR1 register ********************/ +#define PWR_CSR1_BREN_Pos (0U) +#define PWR_CSR1_BREN_Msk (0x1UL << PWR_CSR1_BREN_Pos) /*!< 0x00000001 */ +#define PWR_CSR1_BREN PWR_CSR1_BREN_Msk /*!< Backup regulator enable */ + +#define PWR_CSR1_MONEN_Pos (4U) +#define PWR_CSR1_MONEN_Msk (0x1UL << PWR_CSR1_MONEN_Pos) /*!< 0x00000010 */ +#define PWR_CSR1_MONEN PWR_CSR1_MONEN_Msk /*!< VBAT and temperature monitoring enable */ + +#define PWR_CSR1_BRRDY_Pos (16U) +#define PWR_CSR1_BRRDY_Msk (0x1UL << PWR_CSR1_BRRDY_Pos) /*!< 0x00010000 */ +#define PWR_CSR1_BRRDY PWR_CSR1_BRRDY_Msk /*!< Backup regulator ready */ + +#define PWR_CSR1_VBATL_Pos (20U) +#define PWR_CSR1_VBATL_Msk (0x1UL << PWR_CSR1_VBATL_Pos) /*!< 0x00100000 */ +#define PWR_CSR1_VBATL PWR_CSR1_VBATL_Msk /*!< Monitored VBAT level above low threshold */ + +#define PWR_CSR1_VBATH_Pos (21U) +#define PWR_CSR1_VBATH_Msk (0x1UL << PWR_CSR1_VBATH_Pos) /*!< 0x00200000 */ +#define PWR_CSR1_VBATH PWR_CSR1_VBATH_Msk /*!< Monitored VBAT level above high threshold */ + +#define PWR_CSR1_TEMPL_Pos (22U) +#define PWR_CSR1_TEMPL_Msk (0x1UL << PWR_CSR1_TEMPL_Pos) /*!< 0x00400000 */ +#define PWR_CSR1_TEMPL PWR_CSR1_TEMPL_Msk /*!< Monitored temperature level above low threshold */ + +#define PWR_CSR1_TEMPH_Pos (23U) +#define PWR_CSR1_TEMPH_Msk (0x1UL << PWR_CSR1_TEMPH_Pos) /*!< 0x00800000 */ +#define PWR_CSR1_TEMPH PWR_CSR1_TEMPH_Msk /*!< Monitored temperature level above high threshold */ + +/******************** Bit definition for PWR_CSR2 register ********************/ +#define PWR_CSR2_BYPASS_Pos (0U) +#define PWR_CSR2_BYPASS_Msk (0x1UL << PWR_CSR2_BYPASS_Pos) /*!< 0x00000001 */ +#define PWR_CSR2_BYPASS PWR_CSR2_BYPASS_Msk /*!< Power Management Unit bypass */ + +#define PWR_CSR2_LDOEN_Pos (1U) +#define PWR_CSR2_LDOEN_Msk (0x1UL << PWR_CSR2_LDOEN_Pos) /*!< 0x00000002 */ +#define PWR_CSR2_LDOEN PWR_CSR2_LDOEN_Msk /*!< Low Drop-Out regulator enable */ + +#define PWR_CSR2_SDEN_Pos (2U) +#define PWR_CSR2_SDEN_Msk (0x1UL << PWR_CSR2_SDEN_Pos) /*!< 0x00000004 */ +#define PWR_CSR2_SDEN PWR_CSR2_SDEN_Msk /*!< SMPS Step-down converter enable */ + +#define PWR_CSR2_SMPSEXTHP_Pos (3U) +#define PWR_CSR2_SMPSEXTHP_Msk (0x1UL << PWR_CSR2_SMPSEXTHP_Pos) /*!< 0x00000008 */ +#define PWR_CSR2_SMPSEXTHP PWR_CSR2_SMPSEXTHP_Msk /*!< SMPS external power delivery selection */ + +#define PWR_CSR2_SDHILEVEL_Pos (4U) +#define PWR_CSR2_SDHILEVEL_Msk (0x1UL << PWR_CSR2_SDHILEVEL_Pos) /*!< 0x00000030 */ +#define PWR_CSR2_SDHILEVEL PWR_CSR2_SDHILEVEL_Msk /*!< SMPS step-down converter voltage output for LDO or external supply */ + +#define PWR_CSR2_VBE_Pos (8U) +#define PWR_CSR2_VBE_Msk (0x1UL << PWR_CSR2_VBE_Pos) /*!< 0x00000100 */ +#define PWR_CSR2_VBE PWR_CSR2_VBE_Msk /*!< VBAT charging enable */ + +#define PWR_CSR2_VBRS_Pos (9U) +#define PWR_CSR2_VBRS_Msk (0x1UL << PWR_CSR2_VBRS_Pos) /*!< 0x00000200 */ +#define PWR_CSR2_VBRS PWR_CSR2_VBRS_Msk /*!< VBAT charging resistor selection */ + +#define PWR_CSR2_XSPICAP1_Pos (10U) +#define PWR_CSR2_XSPICAP1_Msk (0x3UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000C00 */ +#define PWR_CSR2_XSPICAP1 PWR_CSR2_XSPICAP1_Msk /*!< XSPI port 1 capacitor control bits */ +#define PWR_CSR2_XSPICAP1_0 (0x1UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000400 */ +#define PWR_CSR2_XSPICAP1_1 (0x2UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000800 */ + +#define PWR_CSR2_XSPICAP2_Pos (12U) +#define PWR_CSR2_XSPICAP2_Msk (0x3UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00003000 */ +#define PWR_CSR2_XSPICAP2 PWR_CSR2_XSPICAP2_Msk /*!< XSPI port 2 capacitor control bits */ +#define PWR_CSR2_XSPICAP2_0 (0x1UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00001000 */ +#define PWR_CSR2_XSPICAP2_1 (0x2UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00002000 */ + +#define PWR_CSR2_EN_XSPIM1_Pos (14U) +#define PWR_CSR2_EN_XSPIM1_Msk (0x1UL << PWR_CSR2_EN_XSPIM1_Pos) /*!< 0x00004000 */ +#define PWR_CSR2_EN_XSPIM1 PWR_CSR2_EN_XSPIM1_Msk /*!< XSPIM1 external supply enable */ + +#define PWR_CSR2_EN_XSPIM2_Pos (15U) +#define PWR_CSR2_EN_XSPIM2_Msk (0x1UL << PWR_CSR2_EN_XSPIM2_Pos) /*!< 0x00008000 */ +#define PWR_CSR2_EN_XSPIM2 PWR_CSR2_EN_XSPIM2_Msk /*!< XSPIM2 external supply enable */ + +#define PWR_CSR2_SDEXTRDY_Pos (16U) +#define PWR_CSR2_SDEXTRDY_Msk (0x1UL << PWR_CSR2_SDEXTRDY_Pos) /*!< 0x00010000 */ +#define PWR_CSR2_SDEXTRDY PWR_CSR2_SDEXTRDY_Msk /*!< SMPS External supply ready */ + +#define PWR_CSR2_USB33DEN_Pos (24U) +#define PWR_CSR2_USB33DEN_Msk (0x1UL << PWR_CSR2_USB33DEN_Pos) /*!< 0x01000000 */ +#define PWR_CSR2_USB33DEN PWR_CSR2_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */ + +#define PWR_CSR2_USBREGEN_Pos (25U) +#define PWR_CSR2_USBREGEN_Msk (0x1UL << PWR_CSR2_USBREGEN_Pos) /*!< 0x02000000 */ +#define PWR_CSR2_USBREGEN PWR_CSR2_USBREGEN_Msk /*!< USB regulator enable */ + +#define PWR_CSR2_USB33RDY_Pos (26U) +#define PWR_CSR2_USB33RDY_Msk (0x1UL << PWR_CSR2_USB33RDY_Pos) /*!< 0x04000000 */ +#define PWR_CSR2_USB33RDY PWR_CSR2_USB33RDY_Msk /*!< USB supply ready */ + +#define PWR_CSR2_USBHSREGEN_Pos (27U) +#define PWR_CSR2_USBHSREGEN_Msk (0x1UL << PWR_CSR2_USBHSREGEN_Pos) /*!< 0x08000000 */ +#define PWR_CSR2_USBHSREGEN PWR_CSR2_USBHSREGEN_Msk /*!< USB HS regulator enable */ + +/******************** Bit definition for PWR_CSR3 register ********************/ +#define PWR_CSR3_PDDS_Pos (0U) +#define PWR_CSR3_PDDS_Msk (0x1UL << PWR_CSR3_PDDS_Pos) /*!< 0x00000001 */ +#define PWR_CSR3_PDDS PWR_CSR3_PDDS_Msk /*!< D1 domain Power Down Deepsleep */ + +#define PWR_CSR3_CSSF_Pos (1U) +#define PWR_CSR3_CSSF_Msk (0x1UL << PWR_CSR3_CSSF_Pos) /*!< 0x00000002 */ +#define PWR_CSR3_CSSF PWR_CSR3_CSSF_Msk /*!< Clear Standby and Stop flag */ + +#define PWR_CSR3_STOPF_Pos (8U) +#define PWR_CSR3_STOPF_Msk (0x1UL << PWR_CSR3_STOPF_Pos) /*!< 0x00000080 */ +#define PWR_CSR3_STOPF PWR_CSR3_STOPF_Msk /*!< STOP Flag */ + +#define PWR_CSR3_SBF_Pos (9U) +#define PWR_CSR3_SBF_Msk (0x1UL << PWR_CSR3_SBF_Pos) /*!< 0x00000100 */ +#define PWR_CSR3_SBF PWR_CSR3_SBF_Msk /*!< System STANDBY Flag */ + +/******************** Bit definition for PWR_CSR4 register ********************/ +#define PWR_CSR4_VOS_Pos (0U) +#define PWR_CSR4_VOS_Msk (0x1UL << PWR_CSR4_VOS_Pos) /*!< 0x00000001 */ +#define PWR_CSR4_VOS PWR_CSR4_VOS_Msk /*!< Voltage Scaling selection according performance */ + +#define PWR_CSR4_VOSRDY_Pos (1U) +#define PWR_CSR4_VOSRDY_Msk (0x1UL << PWR_CSR4_VOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_CSR4_VOSRDY PWR_CSR4_VOSRDY_Msk /*!< VOSRDY: VOS Ready bit for VCORE voltage scaling output selection. */ + +/******************** Bit definition for PWR_WKUPCR register ********************/ +#define PWR_WKUPCR_WKUPC_Pos (0U) +#define PWR_WKUPCR_WKUPC_Msk (0xFUL << PWR_WKUPCR_WKUPC_Pos) /*!< 0x0000000F */ +#define PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC_Msk /*!< Clear Wakeup Pin Flag 1 to 4 */ +#define PWR_WKUPCR_WKUPC1_Pos (0U) +#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */ +#define PWR_WKUPCR_WKUPC2_Pos (1U) +#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */ +#define PWR_WKUPCR_WKUPC3_Pos (2U) +#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */ +#define PWR_WKUPCR_WKUPC4_Pos (3U) +#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */ + +/******************** Bit definition for PWR_WKUPFR register ********************/ +#define PWR_WKUPFR_WKUPF1_Pos (0U) +#define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */ +#define PWR_WKUPFR_WKUPF2_Pos (1U) +#define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */ +#define PWR_WKUPFR_WKUPF3_Pos (2U) +#define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */ +#define PWR_WKUPFR_WKUPF4_Pos (3U) +#define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */ + +/******************** Bit definition for PWR_WKUPEPR register ********************/ +#define PWR_WKUPEPR_WKUPEN_Pos (0U) +#define PWR_WKUPEPR_WKUPEN_Msk (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000000F */ +#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */ +#define PWR_WKUPEPR_WKUPEN1_Pos (0U) +#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup Pin WKUP1 */ +#define PWR_WKUPEPR_WKUPEN2_Pos (1U) +#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup Pin WKUP2 */ +#define PWR_WKUPEPR_WKUPEN3_Pos (2U) +#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup Pin WKUP3 */ +#define PWR_WKUPEPR_WKUPEN4_Pos (3U) +#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup Pin WKUP4 */ + +#define PWR_WKUPEPR_WKUPP_Pos (8U) +#define PWR_WKUPEPR_WKUPP_Msk (0x0FUL << PWR_WKUPEPR_WKUPP_Pos) /*!< 0x0000F00 */ +#define PWR_WKUPEPR_WKUPP PWR_WKUPEPR_WKUPP_Msk /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */ +#define PWR_WKUPEPR_WKUPP1_Pos (8U) +#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Pin Polarity for WKUP1 */ +#define PWR_WKUPEPR_WKUPP2_Pos (9U) +#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Pin Polarity for WKUP2 */ +#define PWR_WKUPEPR_WKUPP3_Pos (10U) +#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Pin Polarity for WKUP3 */ +#define PWR_WKUPEPR_WKUPP4_Pos (11U) +#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Pin Polarity for WKUP4 */ + +#define PWR_WKUPEPR_WKUPPUPD1_Pos (16U) +#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */ +#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WKUPEPR_WKUPPUPD2_Pos (18U) +#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */ +#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WKUPEPR_WKUPPUPD3_Pos (20U) +#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */ +#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WKUPEPR_WKUPPUPD4_Pos (22U) +#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */ +#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for PWR_UCPDRR register ********************/ +#define PWR_UCPDR_UCPD_DBDIS_Pos (0U) +#define PWR_UCPDR_UCPD_DBDIS_Msk (0x1UL << PWR_UCPDR_UCPD_DBDIS_Pos) /*!< 0x00000001 */ +#define PWR_UCPDR_UCPD_DBDIS PWR_UCPDR_UCPD_DBDIS_Msk /*!< UCPD dead battery disable */ + +#define PWR_UCPDR_UCPD_STBY_Pos (1U) +#define PWR_UCPDR_UCPD_STBY_Msk (0x1UL << PWR_UCPDR_UCPD_STBY_Pos) /*!< 0x00000002 */ +#define PWR_UCPDR_UCPD_STBY PWR_UCPDR_UCPD_STBY_Msk /*!< UCPD Standby mode */ + +/******************** Bit definition for PWR_APCR register ********************/ +#define PWR_APCR_APC_Pos (0U) +#define PWR_APCR_APC_Msk (0x1UL << PWR_APCR_APC_Pos) /*!< 0x00000001 */ +#define PWR_APCR_APC PWR_APCR_APC_Msk /*!< Apply pull configuration register */ + +#define PWR_APCR_PN7_PUPD_Pos (16U) +#define PWR_APCR_PN7_PUPD_Msk (0x1UL << PWR_APCR_PN7_PUPD_Pos) /*!< 0x00010000 */ +#define PWR_APCR_PN7_PUPD PWR_APCR_PN7_PUPD_Msk /*!< Port N bit 7 pull-up/down configuration */ + +#define PWR_APCR_PO5_PUPD_Pos (17) +#define PWR_APCR_PO5_PUPD_Msk (0x1UL << PWR_APCR_PO5_PUPD_Pos) /*!< 0x00020000 */ +#define PWR_APCR_PO5_PUPD PWR_APCR_PO5_PUPD_Msk /*!< Port O bit 5 pull-up/down configuration */ + +#define PWR_APCR_I3CPB6_PU_Pos (28U) +#define PWR_APCR_I3CPB6_PU_Msk (0x1UL << PWR_APCR_I3CPB6_PU_Pos) /*!< 0x10000000 */ +#define PWR_APCR_I3CPB6_PU PWR_APCR_I3CPB6_PU_Msk /*!< Port PB6 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB7_PU_Pos (29U) +#define PWR_APCR_I3CPB7_PU_Msk (0x1UL << PWR_APCR_I3CPB7_PU_Pos) /*!< 0x20000000 */ +#define PWR_APCR_I3CPB7_PU PWR_APCR_I3CPB7_PU_Msk /*!< Port PB7 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB8_PU_Pos (30U) +#define PWR_APCR_I3CPB8_PU_Msk (0x1UL << PWR_APCR_I3CPB8_PU_Pos) /*!< 0x40000000 */ +#define PWR_APCR_I3CPB8_PU PWR_APCR_I3CPB8_PU_Msk /*!< Port PB8 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB9_PU_Pos (31U) +#define PWR_APCR_I3CPB9_PU_Msk (0x1UL << PWR_APCR_I3CPB9_PU_Pos) /*!< 0x80000000 */ +#define PWR_APCR_I3CPB9_PU PWR_APCR_I3CPB9_PU_Msk /*!< Port PB9 I3C pull-up bit configuration */ + +/******************** Bit definition for PWR_PUCRN register ********************/ +#define PWR_PUCRN_PUN1_Pos (1U) +#define PWR_PUCRN_PUN1_Msk (0x1UL << PWR_PUCRN_PUN1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRN_PUN1 PWR_PUCRN_PUN1_Msk /*!< PUN1: Port N pull-up */ + +#define PWR_PUCRN_PUN6_Pos (6U) +#define PWR_PUCRN_PUN6_Msk (0x1UL << PWR_PUCRN_PUN6_Pos) /*!< 0x00000040 */ +#define PWR_PUCRN_PUN6 PWR_PUCRN_PUN6_Msk /*!< PUN6: Port N pull-up */ + +#define PWR_PUCRN_PUN12_Pos (12U) +#define PWR_PUCRN_PUN12_Msk (0x1UL << PWR_PUCRN_PUN12_Pos) /*!< 0x00001000 */ +#define PWR_PUCRN_PUN12 PWR_PUCRN_PUN12_Msk /*!< PUN12: Port N pull-up */ + +/******************** Bit definition for PWR_PDCRN register ********************/ +#define PWR_PDCRN_PDN0_Pos (0U) +#define PWR_PDCRN_PDN0_Msk (0x1UL << PWR_PDCRN_PDN0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRN_PDN0 PWR_PDCRN_PDN0_Msk /*!< PDN0: Port N pull-down */ + +#define PWR_PDCRN_PDN1_Pos (1U) +#define PWR_PDCRN_PDN1_Msk (0x1UL << PWR_PDCRN_PDN1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRN_PDN1 PWR_PDCRN_PDN1_Msk /*!< PDN1: Port N pull-down */ + +#define PWR_PDCRN_PDN2N5_Pos (2U) +#define PWR_PDCRN_PDN2N5_Msk (0x1UL << PWR_PDCRN_PDN2N5_Pos) /*!< 0x00000004 */ +#define PWR_PDCRN_PDN2N5 PWR_PDCRN_PDN2N5_Msk /*!< PDN2 to PDN5: Port N pull-down */ + +#define PWR_PDCRN_PDN6_Pos (6U) +#define PWR_PDCRN_PDN6_Msk (0x1UL << PWR_PDCRN_PDN6_Pos) /*!< 0x00000040 */ +#define PWR_PDCRN_PDN6 PWR_PDCRN_PDN6_Msk /*!< PDN6: Port N pull-down */ + +#define PWR_PDCRN_PDN8N11_Pos (8U) +#define PWR_PDCRN_PDN8N11_Msk (0x1UL << PWR_PDCRN_PDN8N11_Pos) /*!< 0x00000100 */ +#define PWR_PDCRN_PDN8N11 PWR_PDCRN_PDN8N11_Msk /*!< PDN8 to PDN11: Port N pull-down */ + +#define PWR_PDCRN_PDN12_Pos (12U) +#define PWR_PDCRN_PDN12_Msk (0x1UL << PWR_PDCRN_PDN12_Pos) /*!< 0x00001000 */ +#define PWR_PDCRN_PDN12 PWR_PDCRN_PDN12_Msk /*!< PDN12: Port N pull-down */ + +/******************** Bit definition for PWR_PUCRO register ********************/ +#define PWR_PUCRO_PUO0_Pos (0U) +#define PWR_PUCRO_PUO0_Msk (0x1UL << PWR_PUCRO_PUO0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRO_PUO0 PWR_PUCRO_PUO0_Msk /*!< PUO0: Port O pull-up */ + +#define PWR_PUCRO_PUO1_Pos (1U) +#define PWR_PUCRO_PUO1_Msk (0x1UL << PWR_PUCRO_PUO1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRO_PUO1 PWR_PUCRO_PUO1_Msk /*!< PUO1: Port O pull-up */ + +#define PWR_PUCRO_PUO4_Pos (4U) +#define PWR_PUCRO_PUO4_Msk (0x1UL << PWR_PUCRO_PUO4_Pos) /*!< 0x00000010 */ +#define PWR_PUCRO_PUO4 PWR_PUCRO_PUO4_Msk /*!< PUO4: Port O pull-up */ + +/******************** Bit definition for PWR_PDCRO register ********************/ +#define PWR_PDCRO_PDO0_Pos (0U) +#define PWR_PDCRO_PDO0_Msk (0x1UL << PWR_PDCRO_PDO0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRO_PDO0 PWR_PDCRO_PDO0_Msk /*!< PDO0: Port O pull-down */ + +#define PWR_PDCRO_PDO1_Pos (1U) +#define PWR_PDCRO_PDO1_Msk (0x1UL << PWR_PDCRO_PDO1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRO_PDO1 PWR_PDCRO_PDO1_Msk /*!< PDO1: Port O pull-down */ + +#define PWR_PDCRO_PDO2_Pos (2U) +#define PWR_PDCRO_PDO2_Msk (0x1UL << PWR_PDCRO_PDO2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRO_PDO2 PWR_PDCRO_PDO2_Msk /*!< PDO2: Port O pull-down */ + +#define PWR_PDCRO_PDO3_Pos (3U) +#define PWR_PDCRO_PDO3_Msk (0x1UL << PWR_PDCRO_PDO3_Pos) /*!< 0x00000008 */ +#define PWR_PDCRO_PDO3 PWR_PDCRO_PDO3_Msk /*!< PDO3: Port O pull-down */ + +#define PWR_PDCRO_PDO4_Pos (4U) +#define PWR_PDCRO_PDO4_Msk (0x1UL << PWR_PDCRO_PDO4_Pos) /*!< 0x00000010 */ +#define PWR_PDCRO_PDO4 PWR_PDCRO_PDO4_Msk /*!< PDO4: Port O pull-down */ + +/******************** Bit definition for PWR_PDCRP register ********************/ +#define PWR_PDCRP_PDP0P3_Pos (0U) +#define PWR_PDCRP_PDP0P3_Msk (0x1UL << PWR_PDCRP_PDP0P3_Pos) /*!< 0x00000001 */ +#define PWR_PDCRP_PDP0P3 PWR_PDCRP_PDP0P3_Msk /*!< PPO0 to PP03 : Port P pull-down */ + +#define PWR_PDCRP_PDP4P7_Pos (4U) +#define PWR_PDCRP_PDP4P7_Msk (0x1UL << PWR_PDCRP_PDP4P7_Pos) /*!< 0x00000010 */ +#define PWR_PDCRP_PDP4P7 PWR_PDCRP_PDP4P7_Msk /*!< PPO4 to PP07 : Port P pull-down */ + +#define PWR_PDCRP_PDP8P11_Pos (8U) +#define PWR_PDCRP_PDP8P11_Msk (0x1UL << PWR_PDCRP_PDP8P11_Pos) /*!< 0x00000100 */ +#define PWR_PDCRP_PDP8P11 PWR_PDCRP_PDP8P11_Msk /*!< PPO8 to PP11 : Port P pull-down */ + +#define PWR_PDCRP_PDP12P15_Pos (12U) +#define PWR_PDCRP_PDP12P15_Msk (0x1UL << PWR_PDCRP_PDP12P15_Pos) /*!< 0x00001000 */ +#define PWR_PDCRP_PDP12P15 PWR_PDCRP_PDP12P15_Msk /*!< PP12 to PP15 : Port P pull-down */ + + +/******************************************************************************/ +/* */ +/* RAM ECC monitoring */ +/* */ +/******************************************************************************/ +/****************** Bit definition for RAMECC_IER register ******************/ +#define RAMECC_IER_GIE_Pos (0U) +#define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) /*!< 0x00000001 */ +#define RAMECC_IER_GIE RAMECC_IER_GIE_Msk /*!< Global interrupt enable */ +#define RAMECC_IER_GECCSEIE_Pos (1U) +#define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) /*!< 0x00000002 */ +#define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk /*!< Global ECC single error interrupt enable */ +#define RAMECC_IER_GECCDEIE_Pos (2U) +#define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) /*!< 0x00000004 */ +#define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk /*!< Global ECC double error interrupt enable */ +#define RAMECC_IER_GECCDEBWIE_Pos (3U) +#define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) /*!< 0x00000008 */ +#define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk /*!< Global ECC double error on byte write (BW) interrupt enable */ + +/******************* Bit definition for RAMECC_CR register ******************/ +#define RAMECC_CR_ECCSEIE_Pos (2U) +#define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) /*!< 0x00000004 */ +#define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk /*!< ECC single error interrupt enable */ +#define RAMECC_CR_ECCDEIE_Pos (3U) +#define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) /*!< 0x00000008 */ +#define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk /*!< ECC double error interrupt enable */ +#define RAMECC_CR_ECCDEBWIE_Pos (4U) +#define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) /*!< 0x00000010 */ +#define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk /*!< ECC double error on byte write (BW) interrupt enable */ +#define RAMECC_CR_ECCELEN_Pos (5U) +#define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) /*!< 0x00000020 */ +#define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk /*!< ECC error latching enable */ + +/******************* Bit definition for RAMECC_SR register ******************/ +#define RAMECC_SR_SEDCF_Pos (0U) +#define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) /*!< 0x00000001 */ +#define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk /*!< ECC single error detected and corrected flag */ +#define RAMECC_SR_DEDF_Pos (1U) +#define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) /*!< 0x00000002 */ +#define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk /*!< ECC double error detected flag */ +#define RAMECC_SR_DEBWDF_Pos (2U) +#define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) /*!< 0x00000004 */ +#define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk /*!< ECC double error on byte write (BW) detected flag */ + +/****************** Bit definition for RAMECC_FAR register ******************/ +#define RAMECC_FAR_FADD_Pos (0U) +#define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk /*!< ECC error failing address */ + +/****************** Bit definition for RAMECC_FDRL register *****************/ +#define RAMECC_FDRL_FDATAL_Pos (0U) +#define RAMECC_FDRL_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FDRL_FDATAL_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FDRL_FDATAL RAMECC_FDRL_FDATAL_Msk /*!< Failing data low */ + +/****************** Bit definition for RAMECC_FDRH register *****************/ +#define RAMECC_FDRH_FDATAH_Pos (0U) +#define RAMECC_FDRH_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FDRH_FDATAH_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FDRH_FDATAH RAMECC_FDRH_FDATAH_Msk /* Failing data high (64-bit memory) */ + +/***************** Bit definition for RAMECC_FECR register ******************/ +#define RAMECC_FECR_FEC_Pos (0U) +#define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk /*!< Failing error code */ + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIKERON_Pos (1U) +#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable in Stop mode */ +#define RCC_CR_HSIRDY_Pos (2U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIV_Pos (3U) +#define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */ +#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< Internal High Speed clock divider selection */ +#define RCC_CR_HSIDIV_0 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSIDIV_1 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000010 */ + +#define RCC_CR_HSIDIVF_Pos (5U) +#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000020 */ +#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< HSI Divider flag */ +#define RCC_CR_CSION_Pos (7U) +#define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) /*!< 0x00000080 */ +#define RCC_CR_CSION RCC_CR_CSION_Msk /*!< The Internal RC 4MHz oscillator clock enable */ +#define RCC_CR_CSIRDY_Pos (8U) +#define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) /*!< 0x00000100 */ +#define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk /*!< The Internal RC 4MHz oscillator clock ready */ +#define RCC_CR_CSIKERON_Pos (9U) +#define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) /*!< 0x00000200 */ +#define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk /*!< Internal RC 4MHz oscillator clock enable in Stop mode */ +#define RCC_CR_HSI48ON_Pos (12U) +#define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) /*!< 0x00001000 */ +#define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk /*!< HSI48 clock enable clock enable */ +#define RCC_CR_HSI48RDY_Pos (13U) +#define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) /*!< 0x00002000 */ +#define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk /*!< HSI48 clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock bypass */ +#define RCC_CR_HSEEXT_Pos (19U) +#define RCC_CR_HSEEXT_Msk (0x1UL << RCC_CR_HSEEXT_Pos) /*!< 0x00100000 */ +#define RCC_CR_HSEEXT RCC_CR_HSEEXT_Msk /*!< External High Speed clock type in bypass mode */ +#define RCC_CR_HSECSSON_Pos (20U) +#define RCC_CR_HSECSSON_Msk (0x1UL << RCC_CR_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSECSSON RCC_CR_HSECSSON_Msk /*!< HSE Clock security System enable */ +#define RCC_CR_PLL1ON_Pos (24U) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */ +#define RCC_CR_PLL1RDY_Pos (25U) +#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready flag */ +#define RCC_CR_PLL2ON_Pos (26U) +#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */ +#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< System PLL2 clock enable */ +#define RCC_CR_PLL2RDY_Pos (27U) +#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */ +#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< System PLL2 clock ready flag */ +#define RCC_CR_PLL3ON_Pos (28U) +#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */ +#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< System PLL3 clock enable */ +#define RCC_CR_PLL3RDY_Pos (29U) +#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */ +#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< System PLL3 clock ready flag */ + +/******************** Bit definition for RCC_HSICFGR register ***************/ +/*!< HSICAL configuration */ +#define RCC_HSICFGR_HSICAL_Pos (0U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSICAL[11:0] bits */ +#define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */ +#define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */ +#define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */ +#define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */ +#define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */ +#define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */ +#define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */ + +/*!< HSITRIM configuration */ +#define RCC_HSICFGR_HSITRIM_Pos (24U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ +#define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CRRCR register *****************/ +/*!< HSI48CAL configuration */ +#define RCC_CRRCR_HSI48CAL_Pos (0U) +#define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */ +#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[9:0] bits */ +#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */ +#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */ +#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */ +#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */ +#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */ +#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */ +#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */ +#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */ +#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */ +#define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */ + +/******************** Bit definition for RCC_CSICFGR register ***************/ +/*!< CSICAL configuration */ +#define RCC_CSICFGR_CSICAL_Pos (0U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSICAL[7:0] bits */ +#define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */ +#define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */ +#define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */ +#define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */ +#define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */ +#define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */ +#define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */ +#define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */ + +/*!< CSITRIM configuration */ +#define RCC_CSICFGR_CSITRIM_Pos (24U) +#define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSITRIM[5:0] bits */ +#define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */ +#define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */ +#define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */ +#define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for RCC_CFGR register ******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock switch) */ +#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_Pos (3U) +#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System clock switch status) */ +#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ + +#define RCC_CFGR_STOPWUCK_Pos (6U) +#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */ +#define RCC_CFGR_STOPKERWUCK_Pos (7U) +#define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) /*!< 0x00000080 */ +#define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk /*!< Kernel Clock Selection after a Wake Up from Stop */ + +/*!< RTCPRE configuration */ +#define RCC_CFGR_RTCPRE_Pos (8U) +#define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00003F00 */ +#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk /*!< RTCPRE[5:0] bits (HSE division factor for RTC clock) */ +#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00002000 */ + +#define RCC_CFGR_TIMPRE_Pos (15U) +#define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos) /*!< 0x00008000 */ +#define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk /*!< TIMPRE configuration */ + +#define RCC_CFGR_MCO1PRE_Pos (18U) +#define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk /*!< MCO1 configuration */ +#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00200000 */ + +#define RCC_CFGR_MCO1SEL_Pos (22U) +#define RCC_CFGR_MCO1SEL_Msk (0x7UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x01C00000 */ +#define RCC_CFGR_MCO1SEL RCC_CFGR_MCO1SEL_Msk /*!< MCO1SEL [2:0] bits (MCO1 clock output selection) */ +#define RCC_CFGR_MCO1SEL_0 (0x1UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_MCO1SEL_1 (0x2UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x00800000 */ +#define RCC_CFGR_MCO1SEL_2 (0x4UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x01000000 */ + +#define RCC_CFGR_MCO2PRE_Pos (25U) +#define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x1E000000 */ +#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< MCO2 configuration */ +#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */ + +#define RCC_CFGR_MCO2SEL_Pos (29U) +#define RCC_CFGR_MCO2SEL_Msk (0x7UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0xE0000000 */ +#define RCC_CFGR_MCO2SEL RCC_CFGR_MCO2SEL_Msk /*!< MCO2SEL [2:0] bits (MCO2 clock output selection) */ +#define RCC_CFGR_MCO2SEL_0 (0x1UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x20000000 */ +#define RCC_CFGR_MCO2SEL_1 (0x2UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x40000000 */ +#define RCC_CFGR_MCO2SEL_2 (0x4UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for RCC_CDCFGR register ****************/ +/*!< CPRE configuration */ +#define RCC_CDCFGR_CPRE_Pos (0U) +#define RCC_CDCFGR_CPRE_Msk (0xFUL << RCC_CDCFGR_CPRE_Pos) /*!< 0x0000000F */ +#define RCC_CDCFGR_CPRE RCC_CDCFGR_CPRE_Msk /*!< CPRE[3:0] bits */ +#define RCC_CDCFGR_CPRE_0 (0x1UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000001 */ +#define RCC_CDCFGR_CPRE_1 (0x2UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000002 */ +#define RCC_CDCFGR_CPRE_2 (0x4UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000004 */ +#define RCC_CDCFGR_CPRE_3 (0x8UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for RCC_BMCFGR register ****************/ +/*!< BMPRE configuration */ +#define RCC_BMCFGR_BMPRE_Pos (0U) +#define RCC_BMCFGR_BMPRE_Msk (0xFUL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x0000000F */ +#define RCC_BMCFGR_BMPRE RCC_BMCFGR_BMPRE_Msk /*!< BMPRE[3:0] bits */ +#define RCC_BMCFGR_BMPRE_0 (0x1UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000001 */ +#define RCC_BMCFGR_BMPRE_1 (0x2UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000002 */ +#define RCC_BMCFGR_BMPRE_2 (0x4UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000004 */ +#define RCC_BMCFGR_BMPRE_3 (0x8UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for RCC_APBCFGR register ***************/ +/*!< APB1 prescaler configuration */ +#define RCC_APBCFGR_PPRE1_Pos (0U) +#define RCC_APBCFGR_PPRE1_Msk (0x7UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000007 */ +#define RCC_APBCFGR_PPRE1 RCC_APBCFGR_PPRE1_Msk /*!< PPRE1[2:0] bits */ +#define RCC_APBCFGR_PPRE1_0 (0x1UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000001 */ +#define RCC_APBCFGR_PPRE1_1 (0x2UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000002 */ +#define RCC_APBCFGR_PPRE1_2 (0x4UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000004 */ + +/*!< APB2 prescaler configuration */ +#define RCC_APBCFGR_PPRE2_Pos (4U) +#define RCC_APBCFGR_PPRE2_Msk (0x7UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000070 */ +#define RCC_APBCFGR_PPRE2 RCC_APBCFGR_PPRE2_Msk /*!< PPRE2[2:0] bits */ +#define RCC_APBCFGR_PPRE2_0 (0x1UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000010 */ +#define RCC_APBCFGR_PPRE2_1 (0x2UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000020 */ +#define RCC_APBCFGR_PPRE2_2 (0x4UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000040 */ + +/*!< APB4 prescaler configuration */ +#define RCC_APBCFGR_PPRE4_Pos (8U) +#define RCC_APBCFGR_PPRE4_Msk (0x7UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000700 */ +#define RCC_APBCFGR_PPRE4 RCC_APBCFGR_PPRE4_Msk /*!< PPRE4[2:0] bits */ +#define RCC_APBCFGR_PPRE4_0 (0x1UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000100 */ +#define RCC_APBCFGR_PPRE4_1 (0x2UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000200 */ +#define RCC_APBCFGR_PPRE4_2 (0x4UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000400 */ + +/*!< APB5 prescaler configuration */ +#define RCC_APBCFGR_PPRE5_Pos (12U) +#define RCC_APBCFGR_PPRE5_Msk (0x7UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00007000 */ +#define RCC_APBCFGR_PPRE5 RCC_APBCFGR_PPRE5_Msk /*!< PPRE5[2:0] bits */ +#define RCC_APBCFGR_PPRE5_0 (0x1UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00001000 */ +#define RCC_APBCFGR_PPRE5_1 (0x2UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00002000 */ +#define RCC_APBCFGR_PPRE5_2 (0x4UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_PLLCKSELR register *************/ +#define RCC_PLLCKSELR_PLLSRC_Pos (0U) +#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ +#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk /*!< DIVMx and PLLs clock source selection */ +#define RCC_PLLCKSELR_PLLSRC_0 (0x01UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000010 */ +#define RCC_PLLCKSELR_PLLSRC_1 (0x02UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000020 */ + +#define RCC_PLLCKSELR_DIVM1_Pos (4U) +#define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */ +#define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk /*!< DIVM1[5:0] bits */ +#define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */ +#define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */ +#define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */ +#define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */ +#define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */ +#define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */ + +#define RCC_PLLCKSELR_DIVM2_Pos (12U) +#define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */ +#define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk /*!< DIVM2[5:0] bits */ +#define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */ +#define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */ +#define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */ +#define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */ +#define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */ + +#define RCC_PLLCKSELR_DIVM3_Pos (20U) +#define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */ +#define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk /*!< DIVM3[5:0] bits */ +#define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */ +#define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */ +#define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */ +#define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for RCC_PLLCFGR register ***************/ +#define RCC_PLLCFGR_PLL1FRACEN_Pos (0U) +#define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */ +#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk /*!< PLL1 fractional latch enable */ +#define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U) +#define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */ +#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk /*!< PLL1 VCO selection */ +#define RCC_PLLCFGR_PLL1SSCGEN_Pos (2U) +#define RCC_PLLCFGR_PLL1SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL1SSCGEN_Pos) /*!< 0x00000004 */ +#define RCC_PLLCFGR_PLL1SSCGEN RCC_PLLCFGR_PLL1SSCGEN_Msk /*!< PLL1 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL1RGE_Pos (3U) +#define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000018 */ +#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk /*!< PLL1RGE[1:0] bits: PLL1 input frequency range */ +#define RCC_PLLCFGR_PLL1RGE_0 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */ +#define RCC_PLLCFGR_PLL1RGE_1 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000010 */ + +#define RCC_PLLCFGR_PLL1PEN_Pos (5U) +#define RCC_PLLCFGR_PLL1PEN_Msk (0x1UL << RCC_PLLCFGR_PLL1PEN_Pos) /*!< 0x00000020 */ +#define RCC_PLLCFGR_PLL1PEN RCC_PLLCFGR_PLL1PEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL1QEN_Pos (6U) +#define RCC_PLLCFGR_PLL1QEN_Msk (0x1UL << RCC_PLLCFGR_PLL1QEN_Pos) /*!< 0x00000040 */ +#define RCC_PLLCFGR_PLL1QEN RCC_PLLCFGR_PLL1QEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL1REN_Pos (7U) +#define RCC_PLLCFGR_PLL1REN_Msk (0x1UL << RCC_PLLCFGR_PLL1REN_Pos) /*!< 0x00000080 */ +#define RCC_PLLCFGR_PLL1REN RCC_PLLCFGR_PLL1REN_Msk /*!< PLL1 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL1SEN_Pos (8U) +#define RCC_PLLCFGR_PLL1SEN_Msk (0x1UL << RCC_PLLCFGR_PLL1SEN_Pos) /*!< 0x00000100 */ +#define RCC_PLLCFGR_PLL1SEN RCC_PLLCFGR_PLL1SEN_Msk /*!< PLL1 DIVS divider output enable */ + +#define RCC_PLLCFGR_PLL2FRACEN_Pos (11U) +#define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000800 */ +#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk /*!< PLL2 fractional latch enable */ +#define RCC_PLLCFGR_PLL2VCOSEL_Pos (12U) +#define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00001000 */ +#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk /*!< PLL2 VCO selection */ +#define RCC_PLLCFGR_PLL2SSCGEN_Pos (13U) +#define RCC_PLLCFGR_PLL2SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL2SSCGEN_Pos) /*!< 0x00002000 */ +#define RCC_PLLCFGR_PLL2SSCGEN RCC_PLLCFGR_PLL2SSCGEN_Msk /*!< PLL2 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL2RGE_Pos (14U) +#define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x0000C000 */ +#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk /*!< PLL2RGE[1:0] bits: PLL2 input frequency range */ +#define RCC_PLLCFGR_PLL2RGE_0 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00004000 */ +#define RCC_PLLCFGR_PLL2RGE_1 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00008000 */ + +#define RCC_PLLCFGR_PLL2PEN_Pos (16U) +#define RCC_PLLCFGR_PLL2PEN_Msk (0x1UL << RCC_PLLCFGR_PLL2PEN_Pos) /*!< 0x00010000 */ +#define RCC_PLLCFGR_PLL2PEN RCC_PLLCFGR_PLL2PEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL2QEN_Pos (17U) +#define RCC_PLLCFGR_PLL2QEN_Msk (0x1UL << RCC_PLLCFGR_PLL2QEN_Pos) /*!< 0x00020000 */ +#define RCC_PLLCFGR_PLL2QEN RCC_PLLCFGR_PLL2QEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL2REN_Pos (18U) +#define RCC_PLLCFGR_PLL2REN_Msk (0x1UL << RCC_PLLCFGR_PLL2REN_Pos) /*!< 0x00040000 */ +#define RCC_PLLCFGR_PLL2REN RCC_PLLCFGR_PLL2REN_Msk /*!< PLL2 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL2SEN_Pos (19U) +#define RCC_PLLCFGR_PLL2SEN_Msk (0x1UL << RCC_PLLCFGR_PLL2SEN_Pos) /*!< 0x00080000 */ +#define RCC_PLLCFGR_PLL2SEN RCC_PLLCFGR_PLL2SEN_Msk /*!< PLL2 DIVS divider output enable */ +#define RCC_PLLCFGR_PLL2TEN_Pos (20U) +#define RCC_PLLCFGR_PLL2TEN_Msk (0x1UL << RCC_PLLCFGR_PLL2TEN_Pos) /*!< 0x00100000 */ +#define RCC_PLLCFGR_PLL2TEN RCC_PLLCFGR_PLL2TEN_Msk /*!< PLL2 DIVT divider output enable */ + +#define RCC_PLLCFGR_PLL3FRACEN_Pos (22U) +#define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00400000 */ +#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk /*!< PLL3 fractional latch enable */ +#define RCC_PLLCFGR_PLL3VCOSEL_Pos (23U) +#define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00800000 */ +#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk /*!< PLL3 VCO selection */ +#define RCC_PLLCFGR_PLL3SSCGEN_Pos (24U) +#define RCC_PLLCFGR_PLL3SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL3SSCGEN_Pos) /*!< 0x01000000 */ +#define RCC_PLLCFGR_PLL3SSCGEN RCC_PLLCFGR_PLL3SSCGEN_Msk /*!< PLL3 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL3RGE_Pos (25U) +#define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x06000000 */ +#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk /*!< PLL3RGE[1:0] bits: PLL3 input frequency range */ +#define RCC_PLLCFGR_PLL3RGE_0 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x02000000 */ +#define RCC_PLLCFGR_PLL3RGE_1 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x04000000 */ + +#define RCC_PLLCFGR_PLL3PEN_Pos (27U) +#define RCC_PLLCFGR_PLL3PEN_Msk (0x1UL << RCC_PLLCFGR_PLL3PEN_Pos) /*!< 0x08000000 */ +#define RCC_PLLCFGR_PLL3PEN RCC_PLLCFGR_PLL3PEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL3QEN_Pos (28U) +#define RCC_PLLCFGR_PLL3QEN_Msk (0x1UL << RCC_PLLCFGR_PLL3QEN_Pos) /*!< 0x10000000 */ +#define RCC_PLLCFGR_PLL3QEN RCC_PLLCFGR_PLL3QEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL3REN_Pos (29U) +#define RCC_PLLCFGR_PLL3REN_Msk (0x1UL << RCC_PLLCFGR_PLL3REN_Pos) /*!< 0x20000000 */ +#define RCC_PLLCFGR_PLL3REN RCC_PLLCFGR_PLL3REN_Msk /*!< PLL3 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL3SEN_Pos (30U) +#define RCC_PLLCFGR_PLL3SEN_Msk (0x1UL << RCC_PLLCFGR_PLL3SEN_Pos) /*!< 0x40000000 */ +#define RCC_PLLCFGR_PLL3SEN RCC_PLLCFGR_PLL3SEN_Msk /*!< PLL3 DIVS divider output enable */ + +/******************** Bit definition for RCC_PLL1DIVR1 register *************/ +#define RCC_PLL1DIVR1_DIVN_Pos (0U) +#define RCC_PLL1DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1DIVR1_DIVN RCC_PLL1DIVR1_DIVN_Msk /*!< DIVN1[8:0] bits: PLL1 DIVN division factor */ +#define RCC_PLL1DIVR1_DIVN_0 (0x001UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR1_DIVN_1 (0x002UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR1_DIVN_2 (0x004UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1DIVR1_DIVN_3 (0x008UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1DIVR1_DIVN_4 (0x010UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1DIVR1_DIVN_5 (0x020UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1DIVR1_DIVN_6 (0x040UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1DIVR1_DIVN_7 (0x080UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1DIVR1_DIVN_8 (0x100UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL1DIVR1_DIVP_Pos (9U) +#define RCC_PLL1DIVR1_DIVP_Msk (0x7FUL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL1DIVR1_DIVP RCC_PLL1DIVR1_DIVP_Msk /*!< DIVP1[6:0] bits: PLL1 DIVP division factor */ +#define RCC_PLL1DIVR1_DIVP_0 (0x001UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL1DIVR1_DIVP_1 (0x002UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL1DIVR1_DIVP_2 (0x004UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL1DIVR1_DIVP_3 (0x008UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL1DIVR1_DIVP_4 (0x010UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL1DIVR1_DIVP_5 (0x020UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL1DIVR1_DIVP_6 (0x040UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL1DIVR1_DIVQ_Pos (16U) +#define RCC_PLL1DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1DIVR1_DIVQ RCC_PLL1DIVR1_DIVQ_Msk /*!< DIVQ1[6:0] bits: PLL1 DIVQ division factor */ +#define RCC_PLL1DIVR1_DIVQ_0 (0x001UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL1DIVR1_DIVQ_1 (0x002UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL1DIVR1_DIVQ_2 (0x004UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL1DIVR1_DIVQ_3 (0x008UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL1DIVR1_DIVQ_4 (0x010UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL1DIVR1_DIVQ_5 (0x020UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL1DIVR1_DIVQ_6 (0x040UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL1DIVR1_DIVR_Pos (24U) +#define RCC_PLL1DIVR1_DIVR_Msk (0x7FUL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL1DIVR1_DIVR RCC_PLL1DIVR1_DIVR_Msk /*!< DIVR1[6:0] bits: PLL1 DIVR division factor */ +#define RCC_PLL1DIVR1_DIVR_0 (0x001UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL1DIVR1_DIVR_1 (0x002UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL1DIVR1_DIVR_2 (0x004UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL1DIVR1_DIVR_3 (0x008UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL1DIVR1_DIVR_4 (0x010UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL1DIVR1_DIVR_5 (0x020UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL1DIVR1_DIVR_6 (0x040UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL1FRACR register *************/ +#define RCC_PLL1FRACR_FRACN_Pos (3U) +#define RCC_PLL1FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACN RCC_PLL1FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_PLL2DIVR1 register *************/ +#define RCC_PLL2DIVR1_DIVN_Pos (0U) +#define RCC_PLL2DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2DIVR1_DIVN RCC_PLL2DIVR1_DIVN_Msk /*!< DIVN2[8:0] bits: PLL2 DIVN division factor */ +#define RCC_PLL2DIVR1_DIVN_0 (0x001UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2DIVR1_DIVN_1 (0x002UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2DIVR1_DIVN_2 (0x004UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2DIVR1_DIVN_3 (0x008UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2DIVR1_DIVN_4 (0x010UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2DIVR1_DIVN_5 (0x020UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2DIVR1_DIVN_6 (0x040UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2DIVR1_DIVN_7 (0x080UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2DIVR1_DIVN_8 (0x100UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL2DIVR1_DIVP_Pos (9U) +#define RCC_PLL2DIVR1_DIVP_Msk (0x7FUL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL2DIVR1_DIVP RCC_PLL2DIVR1_DIVP_Msk /*!< DIVP2[6:0] bits: PLL2 DIVP division factor */ +#define RCC_PLL2DIVR1_DIVP_0 (0x001UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL2DIVR1_DIVP_1 (0x002UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL2DIVR1_DIVP_2 (0x004UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL2DIVR1_DIVP_3 (0x008UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL2DIVR1_DIVP_4 (0x010UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL2DIVR1_DIVP_5 (0x020UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL2DIVR1_DIVP_6 (0x040UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL2DIVR1_DIVQ_Pos (16U) +#define RCC_PLL2DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2DIVR1_DIVQ RCC_PLL2DIVR1_DIVQ_Msk /*!< DIVQ2[6:0] bits: PLL2 DIVQ division factor */ +#define RCC_PLL2DIVR1_DIVQ_0 (0x001UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL2DIVR1_DIVQ_1 (0x002UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL2DIVR1_DIVQ_2 (0x004UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL2DIVR1_DIVQ_3 (0x008UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL2DIVR1_DIVQ_4 (0x010UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL2DIVR1_DIVQ_5 (0x020UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL2DIVR1_DIVQ_6 (0x040UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL2DIVR1_DIVR_Pos (24U) +#define RCC_PLL2DIVR1_DIVR_Msk (0x7FUL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL2DIVR1_DIVR RCC_PLL2DIVR1_DIVR_Msk /*!< DIVR2[6:0] bits: PLL2 DIVR division factor */ +#define RCC_PLL2DIVR1_DIVR_0 (0x001UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL2DIVR1_DIVR_1 (0x002UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL2DIVR1_DIVR_2 (0x004UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL2DIVR1_DIVR_3 (0x008UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL2DIVR1_DIVR_4 (0x010UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL2DIVR1_DIVR_5 (0x020UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL2DIVR1_DIVR_6 (0x040UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL2FRACR register *************/ +#define RCC_PLL2FRACR_FRACN_Pos (3U) +#define RCC_PLL2FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACN RCC_PLL2FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_PLL3DIVR1 register *************/ +#define RCC_PLL3DIVR1_DIVN_Pos (0U) +#define RCC_PLL3DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3DIVR1_DIVN RCC_PLL3DIVR1_DIVN_Msk /*!< DIVN3[8:0] bits: PLL3 DIVN division factor */ +#define RCC_PLL3DIVR1_DIVN_0 (0x001UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3DIVR1_DIVN_1 (0x002UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3DIVR1_DIVN_2 (0x004UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3DIVR1_DIVN_3 (0x008UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3DIVR1_DIVN_4 (0x010UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3DIVR1_DIVN_5 (0x020UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3DIVR1_DIVN_6 (0x040UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3DIVR1_DIVN_7 (0x080UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3DIVR1_DIVN_8 (0x100UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL3DIVR1_DIVP_Pos (9U) +#define RCC_PLL3DIVR1_DIVP_Msk (0x7FUL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL3DIVR1_DIVP RCC_PLL3DIVR1_DIVP_Msk /*!< DIVP3[6:0] bits: PLL3 DIVP division factor */ +#define RCC_PLL3DIVR1_DIVP_0 (0x001UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL3DIVR1_DIVP_1 (0x002UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL3DIVR1_DIVP_2 (0x004UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL3DIVR1_DIVP_3 (0x008UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL3DIVR1_DIVP_4 (0x010UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL3DIVR1_DIVP_5 (0x020UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL3DIVR1_DIVP_6 (0x040UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL3DIVR1_DIVQ_Pos (16U) +#define RCC_PLL3DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3DIVR1_DIVQ RCC_PLL3DIVR1_DIVQ_Msk /*!< DIVQ3[6:0] bits: PLL3 DIVQ division factor */ +#define RCC_PLL3DIVR1_DIVQ_0 (0x001UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL3DIVR1_DIVQ_1 (0x002UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL3DIVR1_DIVQ_2 (0x004UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL3DIVR1_DIVQ_3 (0x008UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL3DIVR1_DIVQ_4 (0x010UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL3DIVR1_DIVQ_5 (0x020UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL3DIVR1_DIVQ_6 (0x040UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL3DIVR1_DIVR_Pos (24U) +#define RCC_PLL3DIVR1_DIVR_Msk (0x7FUL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL3DIVR1_DIVR RCC_PLL3DIVR1_DIVR_Msk /*!< DIVR3[6:0] bits: PLL3 DIVR division factor */ +#define RCC_PLL3DIVR1_DIVR_0 (0x001UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL3DIVR1_DIVR_1 (0x002UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL3DIVR1_DIVR_2 (0x004UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL3DIVR1_DIVR_3 (0x008UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL3DIVR1_DIVR_4 (0x010UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL3DIVR1_DIVR_5 (0x020UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL3DIVR1_DIVR_6 (0x040UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL3FRACR register *************/ +#define RCC_PLL3FRACR_FRACN_Pos (3U) +#define RCC_PLL3FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACN RCC_PLL3FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_CCIPR1 register **************/ +#define RCC_CCIPR1_FMCSEL_Pos (0U) +#define RCC_CCIPR1_FMCSEL_Msk (0x3UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_FMCSEL RCC_CCIPR1_FMCSEL_Msk +#define RCC_CCIPR1_FMCSEL_0 (0x1UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_FMCSEL_1 (0x2UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000002 */ + +#define RCC_CCIPR1_SDMMC12SEL_Pos (2U) +#define RCC_CCIPR1_SDMMC12SEL_Msk (0x1UL << RCC_CCIPR1_SDMMC12SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_SDMMC12SEL RCC_CCIPR1_SDMMC12SEL_Msk + +#define RCC_CCIPR1_XSPI1SEL_Pos (4U) +#define RCC_CCIPR1_XSPI1SEL_Msk (0x3UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR1_XSPI1SEL RCC_CCIPR1_XSPI1SEL_Msk +#define RCC_CCIPR1_XSPI1SEL_0 (0x1UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_XSPI1SEL_1 (0x2UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000020 */ + +#define RCC_CCIPR1_XSPI2SEL_Pos (6U) +#define RCC_CCIPR1_XSPI2SEL_Msk (0x3UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR1_XSPI2SEL RCC_CCIPR1_XSPI2SEL_Msk +#define RCC_CCIPR1_XSPI2SEL_0 (0x1UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_XSPI2SEL_1 (0x2UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x00000080 */ + +#define RCC_CCIPR1_USBREFCKSEL_Pos (8U) +#define RCC_CCIPR1_USBREFCKSEL_Msk (0xFUL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000F00 */ +#define RCC_CCIPR1_USBREFCKSEL RCC_CCIPR1_USBREFCKSEL_Msk +#define RCC_CCIPR1_USBREFCKSEL_0 (0x1UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_USBREFCKSEL_1 (0x2UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_USBREFCKSEL_2 (0x4UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_USBREFCKSEL_3 (0x8UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000800 */ + +#define RCC_CCIPR1_USBPHYCSEL_Pos (12U) +#define RCC_CCIPR1_USBPHYCSEL_Msk (0x3UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR1_USBPHYCSEL RCC_CCIPR1_USBPHYCSEL_Msk +#define RCC_CCIPR1_USBPHYCSEL_0 (0x1UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR1_USBPHYCSEL_1 (0x2UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00002000 */ + +#define RCC_CCIPR1_OTGFSSEL_Pos (14U) +#define RCC_CCIPR1_OTGFSSEL_Msk (0x3UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_OTGFSSEL RCC_CCIPR1_OTGFSSEL_Msk +#define RCC_CCIPR1_OTGFSSEL_0 (0x1UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_OTGFSSEL_1 (0x2UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x00008000 */ + +#define RCC_CCIPR1_ETH1REFCKSEL_Pos (16U) +#define RCC_CCIPR1_ETH1REFCKSEL_Msk (0x3UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_ETH1REFCKSEL RCC_CCIPR1_ETH1REFCKSEL_Msk +#define RCC_CCIPR1_ETH1REFCKSEL_0 (0x1UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_ETH1REFCKSEL_1 (0x2UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00020000 */ + +#define RCC_CCIPR1_ETH1PHYCKSEL_Pos (18U) +#define RCC_CCIPR1_ETH1PHYCKSEL_Msk (0x1UL << RCC_CCIPR1_ETH1PHYCKSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_ETH1PHYCKSEL RCC_CCIPR1_ETH1PHYCKSEL_Msk + +#define RCC_CCIPR1_ADF1SEL_Pos (20U) +#define RCC_CCIPR1_ADF1SEL_Msk (0x7UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR1_ADF1SEL RCC_CCIPR1_ADF1SEL_Msk +#define RCC_CCIPR1_ADF1SEL_0 (0x1UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_ADF1SEL_1 (0x2UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR1_ADF1SEL_2 (0x4UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00400000 */ + +#define RCC_CCIPR1_ADCSEL_Pos (24U) +#define RCC_CCIPR1_ADCSEL_Msk (0x3UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR1_ADCSEL RCC_CCIPR1_ADCSEL_Msk +#define RCC_CCIPR1_ADCSEL_0 (0x1UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR1_ADCSEL_1 (0x2UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x02000000 */ + +#define RCC_CCIPR1_PSSISEL_Pos (27U) +#define RCC_CCIPR1_PSSISEL_Msk (0x1UL << RCC_CCIPR1_PSSISEL_Pos) /*!< 0x08000000 */ +#define RCC_CCIPR1_PSSISEL RCC_CCIPR1_PSSISEL_Msk + +#define RCC_CCIPR1_CKPERSEL_Pos (28U) +#define RCC_CCIPR1_CKPERSEL_Msk (0x3UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x30000000 */ +#define RCC_CCIPR1_CKPERSEL RCC_CCIPR1_CKPERSEL_Msk +#define RCC_CCIPR1_CKPERSEL_0 (0x1UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR1_CKPERSEL_1 (0x2UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for RCC_CCIPR2 register *************/ +#define RCC_CCIPR2_UART234578SEL_Pos (0U) +#define RCC_CCIPR2_UART234578SEL_Msk (0x7UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR2_UART234578SEL RCC_CCIPR2_UART234578SEL_Msk +#define RCC_CCIPR2_UART234578SEL_0 (0x1UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_UART234578SEL_1 (0x2UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_UART234578SEL_2 (0x4UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR2_SPI23SEL_Pos (4U) +#define RCC_CCIPR2_SPI23SEL_Msk (0x7UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR2_SPI23SEL RCC_CCIPR2_SPI23SEL_Msk +#define RCC_CCIPR2_SPI23SEL_0 (0x1UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR2_SPI23SEL_1 (0x2UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR2_SPI23SEL_2 (0x4UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR2_I2C23SEL_Pos (8U) +#define RCC_CCIPR2_I2C23SEL_Msk (0x3UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR2_I2C23SEL RCC_CCIPR2_I2C23SEL_Msk +#define RCC_CCIPR2_I2C23SEL_0 (0x1UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR2_I2C23SEL_1 (0x2UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000200 */ + +#define RCC_CCIPR2_I2C1_I3C1SEL_Pos (12U) +#define RCC_CCIPR2_I2C1_I3C1SEL_Msk (0x3UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR2_I2C1_I3C1SEL RCC_CCIPR2_I2C1_I3C1SEL_Msk +#define RCC_CCIPR2_I2C1_I3C1SEL_0 (0x1UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_I2C1_I3C1SEL_1 (0x2UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00002000 */ + +#define RCC_CCIPR2_LPTIM1SEL_Pos (16U) +#define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR2_LPTIM1SEL RCC_CCIPR2_LPTIM1SEL_Msk +#define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00040000 */ + +#define RCC_CCIPR2_FDCANSEL_Pos (22U) +#define RCC_CCIPR2_FDCANSEL_Msk (0x3UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00C00000 */ +#define RCC_CCIPR2_FDCANSEL RCC_CCIPR2_FDCANSEL_Msk +#define RCC_CCIPR2_FDCANSEL_0 (0x1UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR2_FDCANSEL_1 (0x2UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00800000 */ + +#define RCC_CCIPR2_SPDIFRXSEL_Pos (24U) +#define RCC_CCIPR2_SPDIFRXSEL_Msk (0x3UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_SPDIFRXSEL RCC_CCIPR2_SPDIFRXSEL_Msk +#define RCC_CCIPR2_SPDIFRXSEL_0 (0x1UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_SPDIFRXSEL_1 (0x2UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x02000000 */ + +#define RCC_CCIPR2_CECSEL_Pos (28U) +#define RCC_CCIPR2_CECSEL_Msk (0x3UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_CECSEL RCC_CCIPR2_CECSEL_Msk +#define RCC_CCIPR2_CECSEL_0 (0x1UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_CECSEL_1 (0x2UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for RCC_CCIPR3 register *************/ +#define RCC_CCIPR3_USART1SEL_Pos (0U) +#define RCC_CCIPR3_USART1SEL_Msk (0x7UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR3_USART1SEL RCC_CCIPR3_USART1SEL_Msk +#define RCC_CCIPR3_USART1SEL_0 (0x1UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_USART1SEL_1 (0x2UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_USART1SEL_2 (0x4UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR3_SPI45SEL_Pos (4U) +#define RCC_CCIPR3_SPI45SEL_Msk (0x7UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR3_SPI45SEL RCC_CCIPR3_SPI45SEL_Msk +#define RCC_CCIPR3_SPI45SEL_0 (0x1UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_SPI45SEL_1 (0x2UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR3_SPI45SEL_2 (0x4UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR3_SPI1SEL_Pos (8U) +#define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR3_SPI1SEL RCC_CCIPR3_SPI1SEL_Msk +#define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000400 */ + +#define RCC_CCIPR3_SAI1SEL_Pos (16U) +#define RCC_CCIPR3_SAI1SEL_Msk (0x7UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR3_SAI1SEL RCC_CCIPR3_SAI1SEL_Msk +#define RCC_CCIPR3_SAI1SEL_0 (0x1UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR3_SAI1SEL_1 (0x2UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR3_SAI1SEL_2 (0x4UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00040000 */ + +#define RCC_CCIPR3_SAI2SEL_Pos (20U) +#define RCC_CCIPR3_SAI2SEL_Msk (0x7UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR3_SAI2SEL RCC_CCIPR3_SAI2SEL_Msk +#define RCC_CCIPR3_SAI2SEL_0 (0x1UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR3_SAI2SEL_1 (0x2UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR3_SAI2SEL_2 (0x4UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for RCC_CCIPR4 register ************/ +#define RCC_CCIPR4_LPUART1SEL_Pos (0U) +#define RCC_CCIPR4_LPUART1SEL_Msk (0x7UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR4_LPUART1SEL RCC_CCIPR4_LPUART1SEL_Msk +#define RCC_CCIPR4_LPUART1SEL_0 (0x1UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR4_LPUART1SEL_1 (0x2UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR4_LPUART1SEL_2 (0x4UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR4_SPI6SEL_Pos (4U) +#define RCC_CCIPR4_SPI6SEL_Msk (0x7UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR4_SPI6SEL RCC_CCIPR4_SPI6SEL_Msk +#define RCC_CCIPR4_SPI6SEL_0 (0x1UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR4_SPI6SEL_1 (0x2UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR4_SPI6SEL_2 (0x4UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR4_LPTIM23SEL_Pos (8U) +#define RCC_CCIPR4_LPTIM23SEL_Msk (0x7UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR4_LPTIM23SEL RCC_CCIPR4_LPTIM23SEL_Msk +#define RCC_CCIPR4_LPTIM23SEL_0 (0x1UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR4_LPTIM23SEL_1 (0x2UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR4_LPTIM23SEL_2 (0x4UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000400 */ + +#define RCC_CCIPR4_LPTIM45SEL_Pos (12U) +#define RCC_CCIPR4_LPTIM45SEL_Msk (0x7UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR4_LPTIM45SEL RCC_CCIPR4_LPTIM45SEL_Msk +#define RCC_CCIPR4_LPTIM45SEL_0 (0x1UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR4_LPTIM45SEL_1 (0x2UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR4_LPTIM45SEL_2 (0x4UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_CIER register ******************/ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk +#define RCC_CIER_HSIRDYIE_Pos (2U) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk +#define RCC_CIER_HSERDYIE_Pos (3U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk +#define RCC_CIER_CSIRDYIE_Pos (4U) +#define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk +#define RCC_CIER_HSI48RDYIE_Pos (5U) +#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk +#define RCC_CIER_PLL1RDYIE_Pos (6U) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk +#define RCC_CIER_PLL2RDYIE_Pos (7U) +#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk +#define RCC_CIER_PLL3RDYIE_Pos (8U) +#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk +#define RCC_CIER_LSECSSIE_Pos (9U) +#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */ +#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk + +/******************** Bit definition for RCC_CIFR register ******************/ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk +#define RCC_CIFR_HSIRDYF_Pos (2U) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk +#define RCC_CIFR_HSERDYF_Pos (3U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk +#define RCC_CIFR_CSIRDYF_Pos (4U) +#define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk +#define RCC_CIFR_HSI48RDYF_Pos (5U) +#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk +#define RCC_CIFR_PLL1RDYF_Pos (6U) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk +#define RCC_CIFR_PLL2RDYF_Pos (7U) +#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk +#define RCC_CIFR_PLL3RDYF_Pos (8U) +#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk +#define RCC_CIFR_LSECSSF_Pos (9U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk + +/******************** Bit definition for RCC_CICR register ******************/ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk +#define RCC_CICR_HSIRDYC_Pos (2U) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk +#define RCC_CICR_HSERDYC_Pos (3U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk +#define RCC_CICR_CSIRDYC_Pos (4U) +#define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk +#define RCC_CICR_HSI48RDYC_Pos (5U) +#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk +#define RCC_CICR_PLL1RDYC_Pos (6U) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk +#define RCC_CICR_PLL2RDYC_Pos (7U) +#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk +#define RCC_CICR_PLL3RDYC_Pos (8U) +#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk +#define RCC_CICR_LSECSSC_Pos (9U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk + +/******************** Bit definition for RCC_BDCR register ******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk +#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk +#define RCC_BDCR_LSEDRV_Pos (3U) +#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk +#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ + +#define RCC_BDCR_LSECSSON_Pos (5U) +#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk +#define RCC_BDCR_LSECSSD_Pos (6U) +#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk +#define RCC_BDCR_LSEEXT_Pos (7U) +#define RCC_BDCR_LSEEXT_Msk (0x1UL << RCC_BDCR_LSEEXT_Pos) /*!< 0x00000080 */ +#define RCC_BDCR_LSEEXT RCC_BDCR_LSEEXT_Msk +#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk +#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSRA_Pos (12U) +#define RCC_BDCR_LSECSSRA_Msk (0x1UL << RCC_BDCR_LSECSSRA_Pos) /*!< 0x00001000 */ +#define RCC_BDCR_LSECSSRA RCC_BDCR_LSECSSRA_Msk + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk +#define RCC_BDCR_VSWRST_Pos (16U) +#define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk + +/******************** Bit definition for RCC_AHB1RSTR register **************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (4U) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk +#define RCC_AHB1RSTR_ADC12RST_Pos (5U) +#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk +#define RCC_AHB1RSTR_ETH1RST_Pos (15U) +#define RCC_AHB1RSTR_ETH1RST_Msk (0x1UL << RCC_AHB1RSTR_ETH1RST_Pos) /*!< 0x00008000 */ +#define RCC_AHB1RSTR_ETH1RST RCC_AHB1RSTR_ETH1RST_Msk +#define RCC_AHB1RSTR_OTGHSRST_Pos (25U) +#define RCC_AHB1RSTR_OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHSRST_Pos) /*!< 0x02000000 */ +#define RCC_AHB1RSTR_OTGHSRST RCC_AHB1RSTR_OTGHSRST_Msk +#define RCC_AHB1RSTR_USBPHYCRST_Pos (26U) +#define RCC_AHB1RSTR_USBPHYCRST_Msk (0x1UL << RCC_AHB1RSTR_USBPHYCRST_Pos) /*!< 0x04000000 */ +#define RCC_AHB1RSTR_USBPHYCRST RCC_AHB1RSTR_USBPHYCRST_Msk +#define RCC_AHB1RSTR_OTGFSRST_Pos (27U) +#define RCC_AHB1RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_OTGFSRST_Pos) /*!< 0x08000000 */ +#define RCC_AHB1RSTR_OTGFSRST RCC_AHB1RSTR_OTGFSRST_Msk +#define RCC_AHB1RSTR_ADF1RST_Pos (31U) +#define RCC_AHB1RSTR_ADF1RST_Msk (0x1UL << RCC_AHB1RSTR_ADF1RST_Pos) /*!< 0x80000000 */ +#define RCC_AHB1RSTR_ADF1RST RCC_AHB1RSTR_ADF1RST_Msk + +/******************** Bit definition for RCC_AHB2RSTR register **************/ +#define RCC_AHB2RSTR_PSSIRST_Pos (1U) +#define RCC_AHB2RSTR_PSSIRST_Msk (0x1UL << RCC_AHB2RSTR_PSSIRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_PSSIRST RCC_AHB2RSTR_PSSIRST_Msk +#define RCC_AHB2RSTR_SDMMC2RST_Pos (9U) +#define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) /*!< 0x00000200 */ +#define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk +#define RCC_AHB2RSTR_CORDICRST_Pos (14U) +#define RCC_AHB2RSTR_CORDICRST_Msk (0x1UL << RCC_AHB2RSTR_CORDICRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB2RSTR_CORDICRST RCC_AHB2RSTR_CORDICRST_Msk + +/******************** Bit definition for RCC_AHB3RSTR register **************/ +#define RCC_AHB3RSTR_RNGRST_Pos (0U) +#define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk +#define RCC_AHB3RSTR_HASHRST_Pos (1U) +#define RCC_AHB3RSTR_HASHRST_Msk (0x1UL << RCC_AHB3RSTR_HASHRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTR_HASHRST RCC_AHB3RSTR_HASHRST_Msk +#define RCC_AHB3RSTR_PKARST_Pos (6U) +#define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk + +/******************** Bit definition for RCC_AHB4RSTR register **************/ +#define RCC_AHB4RSTR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk +#define RCC_AHB4RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk +#define RCC_AHB4RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk +#define RCC_AHB4RSTR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk +#define RCC_AHB4RSTR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk +#define RCC_AHB4RSTR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk +#define RCC_AHB4RSTR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk +#define RCC_AHB4RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk +#define RCC_AHB4RSTR_GPIOMRST_Pos (12U) +#define RCC_AHB4RSTR_GPIOMRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOMRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB4RSTR_GPIOMRST RCC_AHB4RSTR_GPIOMRST_Msk +#define RCC_AHB4RSTR_GPIONRST_Pos (13U) +#define RCC_AHB4RSTR_GPIONRST_Msk (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB4RSTR_GPIONRST RCC_AHB4RSTR_GPIONRST_Msk +#define RCC_AHB4RSTR_GPIOORST_Pos (14U) +#define RCC_AHB4RSTR_GPIOORST_Msk (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos) /*!< 0x00004000 */ +#define RCC_AHB4RSTR_GPIOORST RCC_AHB4RSTR_GPIOORST_Msk +#define RCC_AHB4RSTR_GPIOPRST_Pos (15U) +#define RCC_AHB4RSTR_GPIOPRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos) /*!< 0x00008000 */ +#define RCC_AHB4RSTR_GPIOPRST RCC_AHB4RSTR_GPIOPRST_Msk +#define RCC_AHB4RSTR_CRCRST_Pos (19U) +#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk + +/******************** Bit definition for RCC_AHB5RSTR register **************/ +#define RCC_AHB5RSTR_HPDMA1RST_Pos (0U) +#define RCC_AHB5RSTR_HPDMA1RST_Msk (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_HPDMA1RST RCC_AHB5RSTR_HPDMA1RST_Msk +#define RCC_AHB5RSTR_DMA2DRST_Pos (1U) +#define RCC_AHB5RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB5RSTR_DMA2DRST RCC_AHB5RSTR_DMA2DRST_Msk +#define RCC_AHB5RSTR_JPEGRST_Pos (3U) +#define RCC_AHB5RSTR_JPEGRST_Msk (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTR_JPEGRST RCC_AHB5RSTR_JPEGRST_Msk +#define RCC_AHB5RSTR_FMCRST_Pos (4U) +#define RCC_AHB5RSTR_FMCRST_Msk (0x1UL << RCC_AHB5RSTR_FMCRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTR_FMCRST RCC_AHB5RSTR_FMCRST_Msk +#define RCC_AHB5RSTR_XSPI1RST_Pos (5U) +#define RCC_AHB5RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTR_XSPI1RST RCC_AHB5RSTR_XSPI1RST_Msk +#define RCC_AHB5RSTR_SDMMC1RST_Pos (8U) +#define RCC_AHB5RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTR_SDMMC1RST RCC_AHB5RSTR_SDMMC1RST_Msk +#define RCC_AHB5RSTR_XSPI2RST_Pos (12U) +#define RCC_AHB5RSTR_XSPI2RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos) /*!< 0x00001000 */ +#define RCC_AHB5RSTR_XSPI2RST RCC_AHB5RSTR_XSPI2RST_Msk +#define RCC_AHB5RSTR_XSPIMRST_Pos (14U) +#define RCC_AHB5RSTR_XSPIMRST_Msk (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB5RSTR_XSPIMRST RCC_AHB5RSTR_XSPIMRST_Msk +#define RCC_AHB5RSTR_GFXMMURST_Pos (19U) +#define RCC_AHB5RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTR_GFXMMURST RCC_AHB5RSTR_GFXMMURST_Msk + +/******************** Bit definition for RCC_APB1RSTR1 register *************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0U) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk +#define RCC_APB1RSTR1_TIM3RST_Pos (1U) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk +#define RCC_APB1RSTR1_TIM4RST_Pos (2U) +#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk +#define RCC_APB1RSTR1_TIM5RST_Pos (3U) +#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk +#define RCC_APB1RSTR1_TIM6RST_Pos (4U) +#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk +#define RCC_APB1RSTR1_TIM7RST_Pos (5U) +#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk +#define RCC_APB1RSTR1_TIM12RST_Pos (6U) +#define RCC_APB1RSTR1_TIM12RST_Msk (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTR1_TIM12RST RCC_APB1RSTR1_TIM12RST_Msk +#define RCC_APB1RSTR1_TIM13RST_Pos (7U) +#define RCC_APB1RSTR1_TIM13RST_Msk (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTR1_TIM13RST RCC_APB1RSTR1_TIM13RST_Msk +#define RCC_APB1RSTR1_TIM14RST_Pos (8U) +#define RCC_APB1RSTR1_TIM14RST_Msk (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR1_TIM14RST RCC_APB1RSTR1_TIM14RST_Msk +#define RCC_APB1RSTR1_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk +#define RCC_APB1RSTR1_SPI2RST_Pos (14U) +#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk +#define RCC_APB1RSTR1_SPI3RST_Pos (15U) +#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk +#define RCC_APB1RSTR1_SPDIFRXRST_Pos (16U) +#define RCC_APB1RSTR1_SPDIFRXRST_Msk (0x1UL << RCC_APB1RSTR1_SPDIFRXRST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTR1_SPDIFRXRST RCC_APB1RSTR1_SPDIFRXRST_Msk +#define RCC_APB1RSTR1_USART2RST_Pos (17U) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk +#define RCC_APB1RSTR1_USART3RST_Pos (18U) +#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk +#define RCC_APB1RSTR1_UART4RST_Pos (19U) +#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk +#define RCC_APB1RSTR1_UART5RST_Pos (20U) +#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk +#define RCC_APB1RSTR1_I2C1_I3C1RST_Pos (21U) +#define RCC_APB1RSTR1_I2C1_I3C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1_I3C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1_I3C1RST RCC_APB1RSTR1_I2C1_I3C1RST_Msk +#define RCC_APB1RSTR1_I2C2RST_Pos (22U) +#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk +#define RCC_APB1RSTR1_I2C3RST_Pos (23U) +#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk +#define RCC_APB1RSTR1_CECRST_Pos (27U) +#define RCC_APB1RSTR1_CECRST_Msk (0x1UL << RCC_APB1RSTR1_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR1_CECRST RCC_APB1RSTR1_CECRST_Msk +#define RCC_APB1RSTR1_UART7RST_Pos (30U) +#define RCC_APB1RSTR1_UART7RST_Msk (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTR1_UART7RST RCC_APB1RSTR1_UART7RST_Msk +#define RCC_APB1RSTR1_UART8RST_Pos (31U) +#define RCC_APB1RSTR1_UART8RST_Msk (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR1_UART8RST RCC_APB1RSTR1_UART8RST_Msk + +/******************** Bit definition for RCC_APB1RSTR2 register *************/ +#define RCC_APB1RSTR2_CRSRST_Pos (1U) +#define RCC_APB1RSTR2_CRSRST_Msk (0x1UL << RCC_APB1RSTR2_CRSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR2_CRSRST RCC_APB1RSTR2_CRSRST_Msk +#define RCC_APB1RSTR2_MDIOSRST_Pos (5U) +#define RCC_APB1RSTR2_MDIOSRST_Msk (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_MDIOSRST RCC_APB1RSTR2_MDIOSRST_Msk +#define RCC_APB1RSTR2_FDCANRST_Pos (8U) +#define RCC_APB1RSTR2_FDCANRST_Msk (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR2_FDCANRST RCC_APB1RSTR2_FDCANRST_Msk +#define RCC_APB1RSTR2_UCPD1RST_Pos (27U) +#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk + +/******************** Bit definition for RCC_APB2RSTR register **************/ +#define RCC_APB2RSTR_TIM1RST_Pos (0U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk +#define RCC_APB2RSTR_USART1RST_Pos (4U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk +#define RCC_APB2RSTR_SPI4RST_Pos (13U) +#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk +#define RCC_APB2RSTR_TIM9RST_Pos (19U) +#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk +#define RCC_APB2RSTR_SPI5RST_Pos (20U) +#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk +#define RCC_APB2RSTR_SAI1RST_Pos (22U) +#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk +#define RCC_APB2RSTR_SAI2RST_Pos (23U) +#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */ +#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk + +/******************** Bit definition for RCC_APB4RSTR register **************/ +#define RCC_APB4RSTR_SBSRST_Pos (1U) +#define RCC_APB4RSTR_SBSRST_Msk (0x1UL << RCC_APB4RSTR_SBSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB4RSTR_SBSRST RCC_APB4RSTR_SBSRST_Msk +#define RCC_APB4RSTR_LPUART1RST_Pos (3U) +#define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk +#define RCC_APB4RSTR_SPI6RST_Pos (5U) +#define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk +#define RCC_APB4RSTR_LPTIM2RST_Pos (9U) +#define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk +#define RCC_APB4RSTR_LPTIM3RST_Pos (10U) +#define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk +#define RCC_APB4RSTR_LPTIM4RST_Pos (11U) +#define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk +#define RCC_APB4RSTR_LPTIM5RST_Pos (12U) +#define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk +#define RCC_APB4RSTR_VREFRST_Pos (15U) +#define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk +#define RCC_APB4RSTR_DTSRST_Pos (26U) +#define RCC_APB4RSTR_DTSRST_Msk (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */ +#define RCC_APB4RSTR_DTSRST RCC_APB4RSTR_DTSRST_Msk + +/******************** Bit definition for RCC_APB5RSTR register **************/ +#define RCC_APB5RSTR_DCMIPPRST_Pos (2U) +#define RCC_APB5RSTR_DCMIPPRST_Msk (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTR_DCMIPPRST RCC_APB5RSTR_DCMIPPRST_Msk +#define RCC_APB5RSTR_GFXTIMRST_Pos (4U) +#define RCC_APB5RSTR_GFXTIMRST_Msk (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTR_GFXTIMRST RCC_APB5RSTR_GFXTIMRST_Msk + +/******************** Bit definition for RCC_CKGDISR register ***************/ +#define RCC_CKGDISR_AXICKG_Pos (0U) +#define RCC_CKGDISR_AXICKG_Msk (0x1UL << RCC_CKGDISR_AXICKG_Pos) /*!< 0x00000001 */ +#define RCC_CKGDISR_AXICKG RCC_CKGDISR_AXICKG_Msk +#define RCC_CKGDISR_AHBMCKG_Pos (1U) +#define RCC_CKGDISR_AHBMCKG_Msk (0x1UL << RCC_CKGDISR_AHBMCKG_Pos) /*!< 0x00000002 */ +#define RCC_CKGDISR_AHBMCKG RCC_CKGDISR_AHBMCKG_Msk +#define RCC_CKGDISR_SDMMC1CKG_Pos (2U) +#define RCC_CKGDISR_SDMMC1CKG_Msk (0x1UL << RCC_CKGDISR_SDMMC1CKG_Pos) /*!< 0x00000004 */ +#define RCC_CKGDISR_SDMMC1CKG RCC_CKGDISR_SDMMC1CKG_Msk +#define RCC_CKGDISR_HPDMA1CKG_Pos (3U) +#define RCC_CKGDISR_HPDMA1CKG_Msk (0x1UL << RCC_CKGDISR_HPDMA1CKG_Pos) /*!< 0x00000008 */ +#define RCC_CKGDISR_HPDMA1CKG RCC_CKGDISR_HPDMA1CKG_Msk +#define RCC_CKGDISR_CPUCKG_Pos (4U) +#define RCC_CKGDISR_CPUCKG_Msk (0x1UL << RCC_CKGDISR_CPUCKG_Pos) /*!< 0x00000010 */ +#define RCC_CKGDISR_CPUCKG RCC_CKGDISR_CPUCKG_Msk +#define RCC_CKGDISR_DCMIPPCKG_Pos (8U) +#define RCC_CKGDISR_DCMIPPCKG_Msk (0x1UL << RCC_CKGDISR_DCMIPPCKG_Pos) /*!< 0x00000100 */ +#define RCC_CKGDISR_DCMIPPCKG RCC_CKGDISR_DCMIPPCKG_Msk +#define RCC_CKGDISR_DMA2DCKG_Pos (9U) +#define RCC_CKGDISR_DMA2DCKG_Msk (0x1UL << RCC_CKGDISR_DMA2DCKG_Pos) /*!< 0x00000200 */ +#define RCC_CKGDISR_DMA2DCKG RCC_CKGDISR_DMA2DCKG_Msk +#define RCC_CKGDISR_GFXMMUSCKG_Pos (10U) +#define RCC_CKGDISR_GFXMMUSCKG_Msk (0x1UL << RCC_CKGDISR_GFXMMUSCKG_Pos) /*!< 0x00000400 */ +#define RCC_CKGDISR_GFXMMUSCKG RCC_CKGDISR_GFXMMUSCKG_Msk +#define RCC_CKGDISR_GFXMMUMCKG_Pos (12U) +#define RCC_CKGDISR_GFXMMUMCKG_Msk (0x1UL << RCC_CKGDISR_GFXMMUMCKG_Pos) /*!< 0x00001000 */ +#define RCC_CKGDISR_GFXMMUMCKG RCC_CKGDISR_GFXMMUMCKG_Msk +#define RCC_CKGDISR_AHBSCKG_Pos (13U) +#define RCC_CKGDISR_AHBSCKG_Msk (0x1UL << RCC_CKGDISR_AHBSCKG_Pos) /*!< 0x00002000 */ +#define RCC_CKGDISR_AHBSCKG RCC_CKGDISR_AHBSCKG_Msk +#define RCC_CKGDISR_FMCCKG_Pos (14U) +#define RCC_CKGDISR_FMCCKG_Msk (0x1UL << RCC_CKGDISR_FMCCKG_Pos) /*!< 0x00004000 */ +#define RCC_CKGDISR_FMCCKG RCC_CKGDISR_FMCCKG_Msk +#define RCC_CKGDISR_XSPI1CKG_Pos (15U) +#define RCC_CKGDISR_XSPI1CKG_Msk (0x1UL << RCC_CKGDISR_XSPI1CKG_Pos) /*!< 0x00008000 */ +#define RCC_CKGDISR_XSPI1CKG RCC_CKGDISR_XSPI1CKG_Msk +#define RCC_CKGDISR_XSPI2CKG_Pos (16U) +#define RCC_CKGDISR_XSPI2CKG_Msk (0x1UL << RCC_CKGDISR_XSPI2CKG_Pos) /*!< 0x00010000 */ +#define RCC_CKGDISR_XSPI2CKG RCC_CKGDISR_XSPI2CKG_Msk +#define RCC_CKGDISR_AXISRAM4CKG_Pos (17U) +#define RCC_CKGDISR_AXISRAM4CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM4CKG_Pos) /*!< 0x00020000 */ +#define RCC_CKGDISR_AXISRAM4CKG RCC_CKGDISR_AXISRAM4CKG_Msk +#define RCC_CKGDISR_AXISRAM3CKG_Pos (18U) +#define RCC_CKGDISR_AXISRAM3CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM3CKG_Pos) /*!< 0x00040000 */ +#define RCC_CKGDISR_AXISRAM3CKG RCC_CKGDISR_AXISRAM3CKG_Msk +#define RCC_CKGDISR_AXISRAM2CKG_Pos (19U) +#define RCC_CKGDISR_AXISRAM2CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM2CKG_Pos) /*!< 0x00080000 */ +#define RCC_CKGDISR_AXISRAM2CKG RCC_CKGDISR_AXISRAM2CKG_Msk +#define RCC_CKGDISR_AXISRAM1CKG_Pos (20U) +#define RCC_CKGDISR_AXISRAM1CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM1CKG_Pos) /*!< 0x00100000 */ +#define RCC_CKGDISR_AXISRAM1CKG RCC_CKGDISR_AXISRAM1CKG_Msk +#define RCC_CKGDISR_FLASHCKG_Pos (21U) +#define RCC_CKGDISR_FLASHCKG_Msk (0x1UL << RCC_CKGDISR_FLASHCKG_Pos) /*!< 0x00200000 */ +#define RCC_CKGDISR_FLASHCKG RCC_CKGDISR_FLASHCKG_Msk +#define RCC_CKGDISR_EXTICKG_Pos (30U) +#define RCC_CKGDISR_EXTICKG_Msk (0x1UL << RCC_CKGDISR_EXTICKG_Pos) /*!< 0x40000000 */ +#define RCC_CKGDISR_EXTICKG RCC_CKGDISR_EXTICKG_Msk +#define RCC_CKGDISR_JTAGCKG_Pos (31U) +#define RCC_CKGDISR_JTAGCKG_Msk (0x1UL << RCC_CKGDISR_JTAGCKG_Pos) /*!< 0x80000000 */ +#define RCC_CKGDISR_JTAGCKG RCC_CKGDISR_JTAGCKG_Msk + +/******************** Bit definition for RCC_PLL1DIVR2 register *************/ +#define RCC_PLL1DIVR2_DIVS_Pos (0U) +#define RCC_PLL1DIVR2_DIVS_Msk (0x7UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL1DIVR2_DIVS RCC_PLL1DIVR2_DIVS_Msk /*!< DIVS1[2:0] bits: PLL1 DIVS division factor */ +#define RCC_PLL1DIVR2_DIVS_0 (0x1UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR2_DIVS_1 (0x2UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR2_DIVS_2 (0x4UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for RCC_PLL2DIVR2 register *************/ +#define RCC_PLL2DIVR2_DIVS_Pos (0U) +#define RCC_PLL2DIVR2_DIVS_Msk (0x7UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL2DIVR2_DIVS RCC_PLL2DIVR2_DIVS_Msk /*!< DIVS2[2:0] bits: PLL2 DIVS division factor */ +#define RCC_PLL2DIVR2_DIVS_0 (0x1UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL2DIVR2_DIVS_1 (0x2UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL2DIVR2_DIVS_2 (0x4UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +#define RCC_PLL2DIVR2_DIVT_Pos (8U) +#define RCC_PLL2DIVR2_DIVT_Msk (0x7UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000700 */ +#define RCC_PLL2DIVR2_DIVT RCC_PLL2DIVR2_DIVT_Msk /*!< DIVT2[2:0] bits: PLL2 DIVT division factor */ +#define RCC_PLL2DIVR2_DIVT_0 (0x1UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000100 */ +#define RCC_PLL2DIVR2_DIVT_1 (0x2UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000200 */ +#define RCC_PLL2DIVR2_DIVT_2 (0x4UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for RCC_PLL3DIVR2 register *************/ +#define RCC_PLL3DIVR2_DIVS_Pos (0U) +#define RCC_PLL3DIVR2_DIVS_Msk (0x7UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL3DIVR2_DIVS RCC_PLL3DIVR2_DIVS_Msk /*!< DIVS3[2:0] bits: PLL3 DIVS division factor */ +#define RCC_PLL3DIVR2_DIVS_0 (0x1UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL3DIVR2_DIVS_1 (0x2UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL3DIVR2_DIVS_2 (0x4UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for RCC_PLL1SSCGR register *************/ +#define RCC_PLL1SSCGR_MODPER_Pos (0U) +#define RCC_PLL1SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1SSCGR_MODPER RCC_PLL1SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL1SSCGR_MODPER_0 (0x0001UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1SSCGR_MODPER_1 (0x0002UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1SSCGR_MODPER_2 (0x0004UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1SSCGR_MODPER_3 (0x0008UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1SSCGR_MODPER_4 (0x0010UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1SSCGR_MODPER_5 (0x0020UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1SSCGR_MODPER_6 (0x0040UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1SSCGR_MODPER_7 (0x0080UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1SSCGR_MODPER_8 (0x0100UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1SSCGR_MODPER_9 (0x0200UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1SSCGR_MODPER_10 (0x0400UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1SSCGR_MODPER_11 (0x0800UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1SSCGR_MODPER_12 (0x1000UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL1SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL1SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1SSCGR_TPDFNDIS RCC_PLL1SSCGR_TPDFNDIS_Msk +#define RCC_PLL1SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL1SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL1SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1SSCGR_RPDFNDIS RCC_PLL1SSCGR_RPDFNDIS_Msk +#define RCC_PLL1SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL1SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL1SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL1SSCGR_SPREADSEL RCC_PLL1SSCGR_SPREADSEL_Msk +#define RCC_PLL1SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL1SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1SSCGR_INCSTEP RCC_PLL1SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL1SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL2SSCGR register *************/ +#define RCC_PLL2SSCGR_MODPER_Pos (0U) +#define RCC_PLL2SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2SSCGR_MODPER RCC_PLL2SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL2SSCGR_MODPER_0 (0x0001UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2SSCGR_MODPER_1 (0x0002UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2SSCGR_MODPER_2 (0x0004UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2SSCGR_MODPER_3 (0x0008UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2SSCGR_MODPER_4 (0x0010UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2SSCGR_MODPER_5 (0x0020UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2SSCGR_MODPER_6 (0x0040UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2SSCGR_MODPER_7 (0x0080UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2SSCGR_MODPER_8 (0x0100UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2SSCGR_MODPER_9 (0x0200UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2SSCGR_MODPER_10 (0x0400UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2SSCGR_MODPER_11 (0x0800UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2SSCGR_MODPER_12 (0x1000UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL2SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL2SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2SSCGR_TPDFNDIS RCC_PLL2SSCGR_TPDFNDIS_Msk +#define RCC_PLL2SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL2SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL2SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2SSCGR_RPDFNDIS RCC_PLL2SSCGR_RPDFNDIS_Msk +#define RCC_PLL2SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL2SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL2SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL2SSCGR_SPREADSEL RCC_PLL2SSCGR_SPREADSEL_Msk +#define RCC_PLL2SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL2SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2SSCGR_INCSTEP RCC_PLL2SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL2SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL3SSCGR register *************/ +#define RCC_PLL3SSCGR_MODPER_Pos (0U) +#define RCC_PLL3SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL3SSCGR_MODPER RCC_PLL3SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL3SSCGR_MODPER_0 (0x0001UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL3SSCGR_MODPER_1 (0x0002UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL3SSCGR_MODPER_2 (0x0004UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL3SSCGR_MODPER_3 (0x0008UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL3SSCGR_MODPER_4 (0x0010UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL3SSCGR_MODPER_5 (0x0020UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL3SSCGR_MODPER_6 (0x0040UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL3SSCGR_MODPER_7 (0x0080UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL3SSCGR_MODPER_8 (0x0100UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL3SSCGR_MODPER_9 (0x0200UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL3SSCGR_MODPER_10 (0x0400UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL3SSCGR_MODPER_11 (0x0800UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL3SSCGR_MODPER_12 (0x1000UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL3SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL3SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL3SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL3SSCGR_TPDFNDIS RCC_PLL3SSCGR_TPDFNDIS_Msk +#define RCC_PLL3SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL3SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL3SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL3SSCGR_RPDFNDIS RCC_PLL3SSCGR_RPDFNDIS_Msk +#define RCC_PLL3SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL3SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL3SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL3SSCGR_SPREADSEL RCC_PLL3SSCGR_SPREADSEL_Msk +#define RCC_PLL3SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL3SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3SSCGR_INCSTEP RCC_PLL3SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL3SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL3SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL3SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL3SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL3SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL3SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL3SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL3SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL3SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL3SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL3SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL3SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL3SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL3SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL3SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CKPROTR register ***************/ +#define RCC_CKPROTR_XSPICKP_Pos (0U) +#define RCC_CKPROTR_XSPICKP_Msk (0x1UL << RCC_CKPROTR_XSPICKP_Pos) /*!< 0x00000001 */ +#define RCC_CKPROTR_XSPICKP RCC_CKPROTR_XSPICKP_Msk +#define RCC_CKPROTR_FMCCKP_Pos (1U) +#define RCC_CKPROTR_FMCCKP_Msk (0x1UL << RCC_CKPROTR_FMCCKP_Pos) /*!< 0x00000002 */ +#define RCC_CKPROTR_FMCCKP RCC_CKPROTR_FMCCKP_Msk +#define RCC_CKPROTR_XSPI1SWP_Pos (4U) +#define RCC_CKPROTR_XSPI1SWP_Msk (0x7UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000070 */ +#define RCC_CKPROTR_XSPI1SWP RCC_CKPROTR_XSPI1SWP_Msk +#define RCC_CKPROTR_XSPI1SWP_0 (0x1UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000010 */ +#define RCC_CKPROTR_XSPI1SWP_1 (0x2UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000020 */ +#define RCC_CKPROTR_XSPI1SWP_2 (0x4UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000040 */ +#define RCC_CKPROTR_XSPI2SWP_Pos (8U) +#define RCC_CKPROTR_XSPI2SWP_Msk (0x7UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000700 */ +#define RCC_CKPROTR_XSPI2SWP RCC_CKPROTR_XSPI2SWP_Msk +#define RCC_CKPROTR_XSPI2SWP_0 (0x1UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000100 */ +#define RCC_CKPROTR_XSPI2SWP_1 (0x2UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000200 */ +#define RCC_CKPROTR_XSPI2SWP_2 (0x4UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000400 */ +#define RCC_CKPROTR_FMCSWP_Pos (12U) +#define RCC_CKPROTR_FMCSWP_Msk (0x7UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00007000 */ +#define RCC_CKPROTR_FMCSWP RCC_CKPROTR_FMCSWP_Msk +#define RCC_CKPROTR_FMCSWP_0 (0x1UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00001000 */ +#define RCC_CKPROTR_FMCSWP_1 (0x2UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00002000 */ +#define RCC_CKPROTR_FMCSWP_2 (0x4UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_RSR register *******************/ +#define RCC_RSR_RMVF_Pos (16U) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk +#define RCC_RSR_OBLRSTF_Pos (17U) +#define RCC_RSR_OBLRSTF_Msk (0x1UL << RCC_RSR_OBLRSTF_Pos) /*!< 0x00020000 */ +#define RCC_RSR_OBLRSTF RCC_RSR_OBLRSTF_Msk +#define RCC_RSR_BORRSTF_Pos (21U) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk +#define RCC_RSR_PINRSTF_Pos (22U) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk +#define RCC_RSR_PORRSTF_Pos (23U) +#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk +#define RCC_RSR_SFTRSTF_Pos (24U) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk +#define RCC_RSR_IWDGRSTF_Pos (26U) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk +#define RCC_RSR_WWDGRSTF_Pos (28U) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk +#define RCC_RSR_LPWRRSTF_Pos (30U) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk + +/******************** Bit definition for RCC_AHB1ENR register ***************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (4U) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk +#define RCC_AHB1ENR_ADC12EN_Pos (5U) +#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk +#define RCC_AHB1ENR_ETH1MACEN_Pos (15U) +#define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk +#define RCC_AHB1ENR_ETH1TXEN_Pos (16U) +#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk +#define RCC_AHB1ENR_ETH1RXEN_Pos (17U) +#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk +#define RCC_AHB1ENR_OTGHSEN_Pos (25U) +#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk +#define RCC_AHB1ENR_USBPHYCEN_Pos (26U) +#define RCC_AHB1ENR_USBPHYCEN_Msk (0x1UL << RCC_AHB1ENR_USBPHYCEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB1ENR_USBPHYCEN RCC_AHB1ENR_USBPHYCEN_Msk +#define RCC_AHB1ENR_OTGFSEN_Pos (27U) +#define RCC_AHB1ENR_OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_OTGFSEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB1ENR_OTGFSEN RCC_AHB1ENR_OTGFSEN_Msk +#define RCC_AHB1ENR_ADF1EN_Pos (31U) +#define RCC_AHB1ENR_ADF1EN_Msk (0x1UL << RCC_AHB1ENR_ADF1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_ADF1EN RCC_AHB1ENR_ADF1EN_Msk + +/******************** Bit definition for RCC_AHB2ENR register ***************/ +#define RCC_AHB2ENR_PSSIEN_Pos (1U) +#define RCC_AHB2ENR_PSSIEN_Msk (0x1UL << RCC_AHB2ENR_PSSIEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_PSSIEN RCC_AHB2ENR_PSSIEN_Msk +#define RCC_AHB2ENR_SDMMC2EN_Pos (9U) +#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */ +#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk +#define RCC_AHB2ENR_CORDICEN_Pos (14U) +#define RCC_AHB2ENR_CORDICEN_Msk (0x1UL << RCC_AHB2ENR_CORDICEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB2ENR_CORDICEN RCC_AHB2ENR_CORDICEN_Msk +#define RCC_AHB2ENR_SRAM1EN_Pos (29U) +#define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos) /*!< 0x20000000 */ +#define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk +#define RCC_AHB2ENR_SRAM2EN_Pos (30U) +#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk + +/******************** Bit definition for RCC_AHB3ENR register ***************/ +#define RCC_AHB3ENR_RNGEN_Pos (0U) +#define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk +#define RCC_AHB3ENR_HASHEN_Pos (1U) +#define RCC_AHB3ENR_HASHEN_Msk (0x1UL << RCC_AHB3ENR_HASHEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENR_HASHEN RCC_AHB3ENR_HASHEN_Msk +#define RCC_AHB3ENR_PKAEN_Pos (6U) +#define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk + +/******************** Bit definition for RCC_AHB4ENR register ***************/ +#define RCC_AHB4ENR_GPIOAEN_Pos (0U) +#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk +#define RCC_AHB4ENR_GPIOBEN_Pos (1U) +#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk +#define RCC_AHB4ENR_GPIOCEN_Pos (2U) +#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk +#define RCC_AHB4ENR_GPIODEN_Pos (3U) +#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk +#define RCC_AHB4ENR_GPIOEEN_Pos (4U) +#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk +#define RCC_AHB4ENR_GPIOFEN_Pos (5U) +#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk +#define RCC_AHB4ENR_GPIOGEN_Pos (6U) +#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk +#define RCC_AHB4ENR_GPIOHEN_Pos (7U) +#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk +#define RCC_AHB4ENR_GPIOMEN_Pos (12U) +#define RCC_AHB4ENR_GPIOMEN_Msk (0x1UL << RCC_AHB4ENR_GPIOMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB4ENR_GPIOMEN RCC_AHB4ENR_GPIOMEN_Msk +#define RCC_AHB4ENR_GPIONEN_Pos (13U) +#define RCC_AHB4ENR_GPIONEN_Msk (0x1UL << RCC_AHB4ENR_GPIONEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENR_GPIONEN RCC_AHB4ENR_GPIONEN_Msk +#define RCC_AHB4ENR_GPIOOEN_Pos (14U) +#define RCC_AHB4ENR_GPIOOEN_Msk (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENR_GPIOOEN RCC_AHB4ENR_GPIOOEN_Msk +#define RCC_AHB4ENR_GPIOPEN_Pos (15U) +#define RCC_AHB4ENR_GPIOPEN_Msk (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENR_GPIOPEN RCC_AHB4ENR_GPIOPEN_Msk +#define RCC_AHB4ENR_CRCEN_Pos (19U) +#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk +#define RCC_AHB4ENR_BKPRAMEN_Pos (28U) +#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk + +/******************** Bit definition for RCC_AHB5ENR register ***************/ +#define RCC_AHB5ENR_HPDMA1EN_Pos (0U) +#define RCC_AHB5ENR_HPDMA1EN_Msk (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_HPDMA1EN RCC_AHB5ENR_HPDMA1EN_Msk +#define RCC_AHB5ENR_DMA2DEN_Pos (1U) +#define RCC_AHB5ENR_DMA2DEN_Msk (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENR_DMA2DEN RCC_AHB5ENR_DMA2DEN_Msk +#define RCC_AHB5ENR_JPEGEN_Pos (3U) +#define RCC_AHB5ENR_JPEGEN_Msk (0x1UL << RCC_AHB5ENR_JPEGEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENR_JPEGEN RCC_AHB5ENR_JPEGEN_Msk +#define RCC_AHB5ENR_FMCEN_Pos (4U) +#define RCC_AHB5ENR_FMCEN_Msk (0x1UL << RCC_AHB5ENR_FMCEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENR_FMCEN RCC_AHB5ENR_FMCEN_Msk +#define RCC_AHB5ENR_XSPI1EN_Pos (5U) +#define RCC_AHB5ENR_XSPI1EN_Msk (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENR_XSPI1EN RCC_AHB5ENR_XSPI1EN_Msk +#define RCC_AHB5ENR_SDMMC1EN_Pos (8U) +#define RCC_AHB5ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENR_SDMMC1EN RCC_AHB5ENR_SDMMC1EN_Msk +#define RCC_AHB5ENR_XSPI2EN_Pos (12U) +#define RCC_AHB5ENR_XSPI2EN_Msk (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENR_XSPI2EN RCC_AHB5ENR_XSPI2EN_Msk +#define RCC_AHB5ENR_XSPIMEN_Pos (14U) +#define RCC_AHB5ENR_XSPIMEN_Msk (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5ENR_XSPIMEN RCC_AHB5ENR_XSPIMEN_Msk +#define RCC_AHB5ENR_GFXMMUEN_Pos (19U) +#define RCC_AHB5ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENR_GFXMMUEN RCC_AHB5ENR_GFXMMUEN_Msk + +/******************** Bit definition for RCC_APB1ENR1 register **************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0U) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk +#define RCC_APB1ENR1_TIM3EN_Pos (1U) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk +#define RCC_APB1ENR1_TIM4EN_Pos (2U) +#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk +#define RCC_APB1ENR1_TIM5EN_Pos (3U) +#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk +#define RCC_APB1ENR1_TIM6EN_Pos (4U) +#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk +#define RCC_APB1ENR1_TIM7EN_Pos (5U) +#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk +#define RCC_APB1ENR1_TIM12EN_Pos (6U) +#define RCC_APB1ENR1_TIM12EN_Msk (0x1UL << RCC_APB1ENR1_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENR1_TIM12EN RCC_APB1ENR1_TIM12EN_Msk +#define RCC_APB1ENR1_TIM13EN_Pos (7U) +#define RCC_APB1ENR1_TIM13EN_Msk (0x1UL << RCC_APB1ENR1_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENR1_TIM13EN RCC_APB1ENR1_TIM13EN_Msk +#define RCC_APB1ENR1_TIM14EN_Pos (8U) +#define RCC_APB1ENR1_TIM14EN_Msk (0x1UL << RCC_APB1ENR1_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR1_TIM14EN RCC_APB1ENR1_TIM14EN_Msk +#define RCC_APB1ENR1_LPTIM1EN_Pos (9U) +#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk +#define RCC_APB1ENR1_WWDGEN_Pos (11U) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk +#define RCC_APB1ENR1_SPI2EN_Pos (14U) +#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk +#define RCC_APB1ENR1_SPI3EN_Pos (15U) +#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk +#define RCC_APB1ENR1_SPDIFRXEN_Pos (16U) +#define RCC_APB1ENR1_SPDIFRXEN_Msk (0x1UL << RCC_APB1ENR1_SPDIFRXEN_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENR1_SPDIFRXEN RCC_APB1ENR1_SPDIFRXEN_Msk +#define RCC_APB1ENR1_USART2EN_Pos (17U) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk +#define RCC_APB1ENR1_USART3EN_Pos (18U) +#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk +#define RCC_APB1ENR1_UART4EN_Pos (19U) +#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk +#define RCC_APB1ENR1_UART5EN_Pos (20U) +#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk +#define RCC_APB1ENR1_I2C1_I3C1EN_Pos (21U) +#define RCC_APB1ENR1_I2C1_I3C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1_I3C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1_I3C1EN RCC_APB1ENR1_I2C1_I3C1EN_Msk +#define RCC_APB1ENR1_I2C2EN_Pos (22U) +#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk +#define RCC_APB1ENR1_I2C3EN_Pos (23U) +#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk +#define RCC_APB1ENR1_CECEN_Pos (27U) +#define RCC_APB1ENR1_CECEN_Msk (0x1UL << RCC_APB1ENR1_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR1_CECEN RCC_APB1ENR1_CECEN_Msk +#define RCC_APB1ENR1_UART7EN_Pos (30U) +#define RCC_APB1ENR1_UART7EN_Msk (0x1UL << RCC_APB1ENR1_UART7EN_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENR1_UART7EN RCC_APB1ENR1_UART7EN_Msk +#define RCC_APB1ENR1_UART8EN_Pos (31U) +#define RCC_APB1ENR1_UART8EN_Msk (0x1UL << RCC_APB1ENR1_UART8EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR1_UART8EN RCC_APB1ENR1_UART8EN_Msk + +/******************** Bit definition for RCC_APB1ENR2 register **************/ +#define RCC_APB1ENR2_CRSEN_Pos (1U) +#define RCC_APB1ENR2_CRSEN_Msk (0x1UL << RCC_APB1ENR2_CRSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR2_CRSEN RCC_APB1ENR2_CRSEN_Msk +#define RCC_APB1ENR2_MDIOSEN_Pos (5U) +#define RCC_APB1ENR2_MDIOSEN_Msk (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_MDIOSEN RCC_APB1ENR2_MDIOSEN_Msk +#define RCC_APB1ENR2_FDCANEN_Pos (8U) +#define RCC_APB1ENR2_FDCANEN_Msk (0x1UL << RCC_APB1ENR2_FDCANEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR2_FDCANEN RCC_APB1ENR2_FDCANEN_Msk +#define RCC_APB1ENR2_UCPD1EN_Pos (27U) +#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk + +/******************** Bit definition for RCC_APB2ENR register ***************/ +#define RCC_APB2ENR_TIM1EN_Pos (0U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk +#define RCC_APB2ENR_USART1EN_Pos (4U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk +#define RCC_APB2ENR_SPI4EN_Pos (13U) +#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk +#define RCC_APB2ENR_TIM9EN_Pos (19U) +#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk +#define RCC_APB2ENR_SPI5EN_Pos (20U) +#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk +#define RCC_APB2ENR_SAI1EN_Pos (22U) +#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk +#define RCC_APB2ENR_SAI2EN_Pos (23U) +#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */ +#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk + +/******************** Bit definition for RCC_APB4ENR register ***************/ +#define RCC_APB4ENR_SBSEN_Pos (1U) +#define RCC_APB4ENR_SBSEN_Msk (0x1UL << RCC_APB4ENR_SBSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENR_SBSEN RCC_APB4ENR_SBSEN_Msk +#define RCC_APB4ENR_LPUART1EN_Pos (3U) +#define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk +#define RCC_APB4ENR_SPI6EN_Pos (5U) +#define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk +#define RCC_APB4ENR_LPTIM2EN_Pos (9U) +#define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */ +#define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk +#define RCC_APB4ENR_LPTIM3EN_Pos (10U) +#define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */ +#define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk +#define RCC_APB4ENR_LPTIM4EN_Pos (11U) +#define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */ +#define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk +#define RCC_APB4ENR_LPTIM5EN_Pos (12U) +#define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */ +#define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk +#define RCC_APB4ENR_VREFEN_Pos (15U) +#define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk +#define RCC_APB4ENR_RTCAPBEN_Pos (16U) +#define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk +#define RCC_APB4ENR_DTSEN_Pos (26U) +#define RCC_APB4ENR_DTSEN_Msk (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */ +#define RCC_APB4ENR_DTSEN RCC_APB4ENR_DTSEN_Msk + +/******************** Bit definition for RCC_APB5ENR register ***************/ +#define RCC_APB5ENR_DCMIPPEN_Pos (2U) +#define RCC_APB5ENR_DCMIPPEN_Msk (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENR_DCMIPPEN RCC_APB5ENR_DCMIPPEN_Msk +#define RCC_APB5ENR_GFXTIMEN_Pos (4U) +#define RCC_APB5ENR_GFXTIMEN_Msk (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENR_GFXTIMEN RCC_APB5ENR_GFXTIMEN_Msk + +/******************** Bit definition for RCC_AHB1LPENR register *************/ +#define RCC_AHB1LPENR_GPDMA1LPEN_Pos (4U) +#define RCC_AHB1LPENR_GPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENR_GPDMA1LPEN RCC_AHB1LPENR_GPDMA1LPEN_Msk +#define RCC_AHB1LPENR_ADC12LPEN_Pos (5U) +#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk +#define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U) +#define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk +#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U) +#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk +#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U) +#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk +#define RCC_AHB1LPENR_UCPDCTRL_Pos (24U) +#define RCC_AHB1LPENR_UCPDCTRL_Msk (0x1UL << RCC_AHB1LPENR_UCPDCTRL_Pos) /*!< 0x01000000 */ +#define RCC_AHB1LPENR_UCPDCTRL RCC_AHB1LPENR_UCPDCTRL_Msk +#define RCC_AHB1LPENR_OTGHSLPEN_Pos (25U) +#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk +#define RCC_AHB1LPENR_USBPHYCLPEN_Pos (26U) +#define RCC_AHB1LPENR_USBPHYCLPEN_Msk (0x1UL << RCC_AHB1LPENR_USBPHYCLPEN_Pos)/*!< 0x04000000 */ +#define RCC_AHB1LPENR_USBPHYCLPEN RCC_AHB1LPENR_USBPHYCLPEN_Msk +#define RCC_AHB1LPENR_OTGFSLPEN_Pos (27U) +#define RCC_AHB1LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGFSLPEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB1LPENR_OTGFSLPEN RCC_AHB1LPENR_OTGFSLPEN_Msk +#define RCC_AHB1LPENR_ADF1LPEN_Pos (31U) +#define RCC_AHB1LPENR_ADF1LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADF1LPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1LPENR_ADF1LPEN RCC_AHB1LPENR_ADF1LPEN_Msk + +/******************** Bit definition for RCC_AHB2LPENR register *************/ +#define RCC_AHB2LPENR_PSSILPEN_Pos (1U) +#define RCC_AHB2LPENR_PSSILPEN_Msk (0x1UL << RCC_AHB2LPENR_PSSILPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2LPENR_PSSILPEN RCC_AHB2LPENR_PSSILPEN_Msk +#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U) +#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk +#define RCC_AHB2LPENR_CORDICLPEN_Pos (14U) +#define RCC_AHB2LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB2LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB2LPENR_CORDICLPEN RCC_AHB2LPENR_CORDICLPEN_Msk +#define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U) +#define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk +#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U) +#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk + +/******************** Bit definition for RCC_AHB3LPENR register *************/ +#define RCC_AHB3LPENR_RNGLPEN_Pos (0U) +#define RCC_AHB3LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3LPENR_RNGLPEN RCC_AHB3LPENR_RNGLPEN_Msk +#define RCC_AHB3LPENR_HASHLPEN_Pos (1U) +#define RCC_AHB3LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENR_HASHLPEN RCC_AHB3LPENR_HASHLPEN_Msk +#define RCC_AHB3LPENR_PKALPEN_Pos (6U) +#define RCC_AHB3LPENR_PKALPEN_Msk (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB3LPENR_PKALPEN RCC_AHB3LPENR_PKALPEN_Msk + +/******************** Bit definition for RCC_AHB4LPENR register *************/ +#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk +#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk +#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk +#define RCC_AHB4LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk +#define RCC_AHB4LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk +#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U) +#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk +#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U) +#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk +#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk +#define RCC_AHB4LPENR_GPIOMLPEN_Pos (12U) +#define RCC_AHB4LPENR_GPIOMLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOMLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB4LPENR_GPIOMLPEN RCC_AHB4LPENR_GPIOMLPEN_Msk +#define RCC_AHB4LPENR_GPIONLPEN_Pos (13U) +#define RCC_AHB4LPENR_GPIONLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENR_GPIONLPEN RCC_AHB4LPENR_GPIONLPEN_Msk +#define RCC_AHB4LPENR_GPIOOLPEN_Pos (14U) +#define RCC_AHB4LPENR_GPIOOLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENR_GPIOOLPEN RCC_AHB4LPENR_GPIOOLPEN_Msk +#define RCC_AHB4LPENR_GPIOPLPEN_Pos (15U) +#define RCC_AHB4LPENR_GPIOPLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENR_GPIOPLPEN RCC_AHB4LPENR_GPIOPLPEN_Msk +#define RCC_AHB4LPENR_CRCLPEN_Pos (19U) +#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk +#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U) +#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk + +/******************** Bit definition for RCC_AHB5LPENR register *************/ +#define RCC_AHB5LPENR_HPDMA1LPEN_Pos (0U) +#define RCC_AHB5LPENR_HPDMA1LPEN_Msk (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENR_HPDMA1LPEN RCC_AHB5LPENR_HPDMA1LPEN_Msk +#define RCC_AHB5LPENR_DMA2DLPEN_Pos (1U) +#define RCC_AHB5LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENR_DMA2DLPEN RCC_AHB5LPENR_DMA2DLPEN_Msk +#define RCC_AHB5LPENR_FLASHLPEN_Pos (2U) +#define RCC_AHB5LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB5LPENR_FLASHLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB5LPENR_FLASHLPEN RCC_AHB5LPENR_FLASHLPEN_Msk +#define RCC_AHB5LPENR_JPEGLPEN_Pos (3U) +#define RCC_AHB5LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENR_JPEGLPEN RCC_AHB5LPENR_JPEGLPEN_Msk +#define RCC_AHB5LPENR_FMCLPEN_Pos (4U) +#define RCC_AHB5LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5LPENR_FMCLPEN RCC_AHB5LPENR_FMCLPEN_Msk +#define RCC_AHB5LPENR_XSPI1LPEN_Pos (5U) +#define RCC_AHB5LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENR_XSPI1LPEN RCC_AHB5LPENR_XSPI1LPEN_Msk +#define RCC_AHB5LPENR_SDMMC1LPEN_Pos (8U) +#define RCC_AHB5LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENR_SDMMC1LPEN RCC_AHB5LPENR_SDMMC1LPEN_Msk +#define RCC_AHB5LPENR_XSPI2LPEN_Pos (12U) +#define RCC_AHB5LPENR_XSPI2LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENR_XSPI2LPEN RCC_AHB5LPENR_XSPI2LPEN_Msk +#define RCC_AHB5LPENR_XSPIMLPEN_Pos (14U) +#define RCC_AHB5LPENR_XSPIMLPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5LPENR_XSPIMLPEN RCC_AHB5LPENR_XSPIMLPEN_Msk +#define RCC_AHB5LPENR_GFXMMULPEN_Pos (19U) +#define RCC_AHB5LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENR_GFXMMULPEN RCC_AHB5LPENR_GFXMMULPEN_Msk +#define RCC_AHB5LPENR_DTCM1LPEN_Pos (28U) +#define RCC_AHB5LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB5LPENR_DTCM1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENR_DTCM1LPEN RCC_AHB5LPENR_DTCM1LPEN_Msk +#define RCC_AHB5LPENR_DTCM2LPEN_Pos (29U) +#define RCC_AHB5LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB5LPENR_DTCM2LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENR_DTCM2LPEN RCC_AHB5LPENR_DTCM2LPEN_Msk +#define RCC_AHB5LPENR_ITCMLPEN_Pos (30U) +#define RCC_AHB5LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB5LPENR_ITCMLPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB5LPENR_ITCMLPEN RCC_AHB5LPENR_ITCMLPEN_Msk +#define RCC_AHB5LPENR_AXISRAMLPEN_Pos (31U) +#define RCC_AHB5LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB5LPENR_AXISRAMLPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB5LPENR_AXISRAMLPEN RCC_AHB5LPENR_AXISRAMLPEN_Msk + +/******************** Bit definition for RCC_APB1LPENR1 register ************/ +#define RCC_APB1LPENR1_TIM2LPEN_Pos (0U) +#define RCC_APB1LPENR1_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENR1_TIM2LPEN RCC_APB1LPENR1_TIM2LPEN_Msk +#define RCC_APB1LPENR1_TIM3LPEN_Pos (1U) +#define RCC_APB1LPENR1_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENR1_TIM3LPEN RCC_APB1LPENR1_TIM3LPEN_Msk +#define RCC_APB1LPENR1_TIM4LPEN_Pos (2U) +#define RCC_APB1LPENR1_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENR1_TIM4LPEN RCC_APB1LPENR1_TIM4LPEN_Msk +#define RCC_APB1LPENR1_TIM5LPEN_Pos (3U) +#define RCC_APB1LPENR1_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENR1_TIM5LPEN RCC_APB1LPENR1_TIM5LPEN_Msk +#define RCC_APB1LPENR1_TIM6LPEN_Pos (4U) +#define RCC_APB1LPENR1_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENR1_TIM6LPEN RCC_APB1LPENR1_TIM6LPEN_Msk +#define RCC_APB1LPENR1_TIM7LPEN_Pos (5U) +#define RCC_APB1LPENR1_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR1_TIM7LPEN RCC_APB1LPENR1_TIM7LPEN_Msk +#define RCC_APB1LPENR1_TIM12LPEN_Pos (6U) +#define RCC_APB1LPENR1_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENR1_TIM12LPEN RCC_APB1LPENR1_TIM12LPEN_Msk +#define RCC_APB1LPENR1_TIM13LPEN_Pos (7U) +#define RCC_APB1LPENR1_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENR1_TIM13LPEN RCC_APB1LPENR1_TIM13LPEN_Msk +#define RCC_APB1LPENR1_TIM14LPEN_Pos (8U) +#define RCC_APB1LPENR1_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR1_TIM14LPEN RCC_APB1LPENR1_TIM14LPEN_Msk +#define RCC_APB1LPENR1_LPTIM1LPEN_Pos (9U) +#define RCC_APB1LPENR1_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos)/*!< 0x00000200 */ +#define RCC_APB1LPENR1_LPTIM1LPEN RCC_APB1LPENR1_LPTIM1LPEN_Msk +#define RCC_APB1LPENR1_WWDGLPEN_Pos (11U) +#define RCC_APB1LPENR1_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENR1_WWDGLPEN RCC_APB1LPENR1_WWDGLPEN_Msk +#define RCC_APB1LPENR1_SPI2LPEN_Pos (14U) +#define RCC_APB1LPENR1_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENR1_SPI2LPEN RCC_APB1LPENR1_SPI2LPEN_Msk +#define RCC_APB1LPENR1_SPI3LPEN_Pos (15U) +#define RCC_APB1LPENR1_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENR1_SPI3LPEN RCC_APB1LPENR1_SPI3LPEN_Msk +#define RCC_APB1LPENR1_SPDIFRXLPEN_Pos (16U) +#define RCC_APB1LPENR1_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LPENR1_SPDIFRXLPEN_Pos)/*!< 0x00010000 */ +#define RCC_APB1LPENR1_SPDIFRXLPEN RCC_APB1LPENR1_SPDIFRXLPEN_Msk +#define RCC_APB1LPENR1_USART2LPEN_Pos (17U) +#define RCC_APB1LPENR1_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos)/*!< 0x00020000 */ +#define RCC_APB1LPENR1_USART2LPEN RCC_APB1LPENR1_USART2LPEN_Msk +#define RCC_APB1LPENR1_USART3LPEN_Pos (18U) +#define RCC_APB1LPENR1_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos)/*!< 0x00040000 */ +#define RCC_APB1LPENR1_USART3LPEN RCC_APB1LPENR1_USART3LPEN_Msk +#define RCC_APB1LPENR1_UART4LPEN_Pos (19U) +#define RCC_APB1LPENR1_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENR1_UART4LPEN RCC_APB1LPENR1_UART4LPEN_Msk +#define RCC_APB1LPENR1_UART5LPEN_Pos (20U) +#define RCC_APB1LPENR1_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENR1_UART5LPEN RCC_APB1LPENR1_UART5LPEN_Msk +#define RCC_APB1LPENR1_I2C1_I3C1LPEN_Pos (21U) +#define RCC_APB1LPENR1_I2C1_I3C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C1_I3C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENR1_I2C1_I3C1LPEN RCC_APB1LPENR1_I2C1_I3C1LPEN_Msk +#define RCC_APB1LPENR1_I2C2LPEN_Pos (22U) +#define RCC_APB1LPENR1_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENR1_I2C2LPEN RCC_APB1LPENR1_I2C2LPEN_Msk +#define RCC_APB1LPENR1_I2C3LPEN_Pos (23U) +#define RCC_APB1LPENR1_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENR1_I2C3LPEN RCC_APB1LPENR1_I2C3LPEN_Msk +#define RCC_APB1LPENR1_CECLPEN_Pos (27U) +#define RCC_APB1LPENR1_CECLPEN_Msk (0x1UL << RCC_APB1LPENR1_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1LPENR1_CECLPEN RCC_APB1LPENR1_CECLPEN_Msk +#define RCC_APB1LPENR1_UART7LPEN_Pos (30U) +#define RCC_APB1LPENR1_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENR1_UART7LPEN RCC_APB1LPENR1_UART7LPEN_Msk +#define RCC_APB1LPENR1_UART8LPEN_Pos (31U) +#define RCC_APB1LPENR1_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENR1_UART8LPEN RCC_APB1LPENR1_UART8LPEN_Msk + +/******************** Bit definition for RCC_PB1LPENR2 register ************/ +#define RCC_APB1LPENR2_CRSLPEN_Pos (1U) +#define RCC_APB1LPENR2_CRSLPEN_Msk (0x1UL << RCC_APB1LPENR2_CRSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENR2_CRSLPEN RCC_APB1LPENR2_CRSLPEN_Msk +#define RCC_APB1LPENR2_MDIOSLPEN_Pos (5U) +#define RCC_APB1LPENR2_MDIOSLPEN_Msk (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR2_MDIOSLPEN RCC_APB1LPENR2_MDIOSLPEN_Msk +#define RCC_APB1LPENR2_FDCANLPEN_Pos (8U) +#define RCC_APB1LPENR2_FDCANLPEN_Msk (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR2_FDCANLPEN RCC_APB1LPENR2_FDCANLPEN_Msk +#define RCC_APB1LPENR2_UCPD1LPEN_Pos (27U) +#define RCC_APB1LPENR2_UCPD1LPEN_Msk (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1LPENR2_UCPD1LPEN RCC_APB1LPENR2_UCPD1LPEN_Msk + +/******************** Bit definition for RCC_APB2LPENR register *************/ +#define RCC_APB2LPENR_TIM1LPEN_Pos (0U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk +#define RCC_APB2LPENR_USART1LPEN_Pos (4U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk +#define RCC_APB2LPENR_SPI4LPEN_Pos (13U) +#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk +#define RCC_APB2LPENR_TIM15LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk +#define RCC_APB2LPENR_TIM16LPEN_Pos (17U) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk +#define RCC_APB2LPENR_TIM17LPEN_Pos (18U) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk +#define RCC_APB2LPENR_TIM9LPEN_Pos (19U) +#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk +#define RCC_APB2LPENR_SPI5LPEN_Pos (20U) +#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk +#define RCC_APB2LPENR_SAI1LPEN_Pos (22U) +#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk +#define RCC_APB2LPENR_SAI2LPEN_Pos (23U) +#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk + +/******************** Bit definition for RCC_APB4LPENR register *************/ +#define RCC_APB4LPENR_SBSLPEN_Pos (1U) +#define RCC_APB4LPENR_SBSLPEN_Msk (0x1UL << RCC_APB4LPENR_SBSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENR_SBSLPEN RCC_APB4LPENR_SBSLPEN_Msk +#define RCC_APB4LPENR_LPUART1LPEN_Pos (3U) +#define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos)/*!< 0x00000008 */ +#define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk +#define RCC_APB4LPENR_SPI6LPEN_Pos (5U) +#define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk +#define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U) +#define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk +#define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U) +#define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk +#define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U) +#define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk +#define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U) +#define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk +#define RCC_APB4LPENR_VREFLPEN_Pos (15U) +#define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk +#define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U) +#define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk +#define RCC_APB4LPENR_DTSLPEN_Pos (26U) +#define RCC_APB4LPENR_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */ +#define RCC_APB4LPENR_DTSLPEN RCC_APB4LPENR_DTSLPEN_Msk + +/******************** Bit definition for RCC_APB5LPENR register *************/ +#define RCC_APB5LPENR_DCMIPPLPEN_Pos (2U) +#define RCC_APB5LPENR_DCMIPPLPEN_Msk (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENR_DCMIPPLPEN RCC_APB5LPENR_DCMIPPLPEN_Msk +#define RCC_APB5LPENR_GFXTIMLPEN_Pos (4U) +#define RCC_APB5LPENR_GFXTIMLPEN_Msk (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENR_GFXTIMLPEN RCC_APB5LPENR_GFXTIMLPEN_Msk + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! /*!< ARM Cortex-M7 processor and core peripherals */ +#include "system_stm32h7rsxx.h" /*!< STM32H7RSxx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H7RSxx_peripherals + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[4];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t OR; /*!< ADC option register, Address offset: 0xC8 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief AXIM ASIB + */ +typedef struct +{ + uint32_t RESERVED1[9]; /*!< Reserved, Address offset: 0x00-0x20 */ + __IO uint32_t FNMOD2; /*!< AXIM ASIB fn_mod2 register Address offset: 0x24 */ + uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x28-0xFC */ + __IO uint32_t READQOS; /*!< AXIM ASIB read_qos register Address offset: 0x100 */ + __IO uint32_t WRITEQOS; /*!< AXIM ASIB write_qos register Address offset: 0x104 */ + __IO uint32_t FNMOD; /*!< AXIM ASIB fn_mod register Address offset: 0x108 */ +} AXIM_ASIB_TypeDef; + +typedef struct +{ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x00-0x04 */ + __IO uint32_t FNMODBMISS; /*!< AXIM AMIB fn_mod_bm_iss register Address offset: 0x08 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x0C-0x20 */ + __IO uint32_t FNMOD2; /*!< AXIM AMIB fn_mod2 register Address offset: 0x24 */ + uint32_t RESERVED3[1]; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t FNMODLB; /*!< AXIM AMIB fn_mod_lb register Address offset: 0x2C */ + uint32_t RESERVED5[54]; /*!< Reserved, Address offset: 0x30-0x104 */ + __IO uint32_t FNMOD; /*!< AXIM AMIB fn_mod register Address offset: 0x108 */ +} AXIM_AMIB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +} CEC_TypeDef; + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC Control and Status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief GFXTIM + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXTIM configuration register, Address offset: 0x00 */ + __IO uint32_t CGCR; /*!< GFXTIM clock generator configuration register, Address offset: 0x04 */ + __IO uint32_t TCR; /*!< GFXTIM timers configuration register, Address offset: 0x08 */ + __IO uint32_t TDR; /*!< GFXTIM timers disable register, Address offset: 0x0C */ + __IO uint32_t EVCR; /*!< GFXTIM events control register, Address offset: 0x10 */ + __IO uint32_t EVSR; /*!< GFXTIM events selection register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WDGTCR; /*!< GFXTIM watchdog timer configuration register, Address offset: 0x20 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t ISR; /*!< GFXTIM interrupt status register, Address offset: 0x30 */ + __IO uint32_t ICR; /*!< GFXTIM interrupt clear register, Address offset: 0x34 */ + __IO uint32_t IER; /*!< GFXTIM interrupt enable register, Address offset: 0x38 */ + __IO uint32_t TSR; /*!< GFXTIM timers status register, Address offset: 0x3C */ + __IO uint32_t LCCRR; /*!< GFXTIM line clock counter reload register, Address offset: 0x40 */ + __IO uint32_t FCCRR; /*!< GFXTIM frame clock counter reload register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48-0x4C */ + __IO uint32_t ATR; /*!< GFXTIM absolute time register, Address offset: 0x50 */ + __IO uint32_t AFCR; /*!< GFXTIM absolute frame counter register, Address offset: 0x54 */ + __IO uint32_t ALCR; /*!< GFXTIM absolute line counter register, Address offset: 0x58 */ + uint32_t RESERVED4[1]; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t AFCC1R; /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */ + uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x64-0X6C */ + __IO uint32_t ALCC1R; /*!< GFXTIM absolute line counter compare 1 register, Address offset: 0x70 */ + __IO uint32_t ALCC2R; /*!< GFXTIM absolute line counter compare 2 register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x78-0X7C */ + __IO uint32_t RFC1R; /*!< GFXTIM relative frame counter 1 register, Address offset: 0x80 */ + __IO uint32_t RFC1RR; /*!< GFXTIM relative frame counter 1 reload register, Address offset: 0x84 */ + __IO uint32_t RFC2R; /*!< GFXTIM relative frame counter 2 register, Address offset: 0x88 */ + __IO uint32_t RFC2RR; /*!< GFXTIM relative frame counter 2 reload register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x90-0X9C */ + __IO uint32_t WDGCR; /*!< GFXTIM watchdog counter register, Address offset: 0xA0 */ + __IO uint32_t WDGRR; /*!< GFXTIM watchdog reload register, Address offset: 0xA4 */ + __IO uint32_t WDGPAR; /*!< GFXTIM watchdog pre-alarm register, Address offset: 0xA8 */ + uint32_t RESERVED8[209]; /*!< Reserved, Address offset: 0xAC-0X3EC */ + __IO uint32_t HWCFGR; /*!< GFXTIM HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GFXTIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GFXTIM identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GFXTIM size identification register, Address offset: 0x3FC */ +} GFXTIM_TypeDef; + + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t AHB5FZR; /*!< Debug MCU AHB5FZR freeze register, Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1FZR freeze register, Address offset: 0x24 */ + uint32_t RESERVED3[5]; /*!< Reserved, Address offset: 0x28-0x38 */ + __IO uint32_t APB1FZR; /*!< Debug MCU APB1FZR freeze register, Address offset: 0x3C */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x40-0x48 */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2FZR freeze register, Address offset: 0x4C */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZR; /*!< Debug MCU APB4FZR freeze register, Address offset: 0x54 */ + uint32_t RESERVED6[41]; /*!< Reserved, Address offset: 0x58-0xF8 */ + __IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU Authentication Host register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug MCU Authentication Device register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug MCU Authentication Ack register, Address offset: 0x108 */ + uint32_t RESERVED7[945]; /*!< Reserved, Address offset: 0x10C-0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU peripheral identity register 4, Address offset: 0xFD0 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0xFD4-0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMIPP + */ +typedef struct +{ + __IO uint32_t IPGR1; /*!< IP-Plug global register 1 Address offset: 0x00 */ + __IO uint32_t IPGR2; /*!< IP-Plug global register 2 Address offset: 0x04 */ + __IO uint32_t IPGR3; /*!< IP-Plug global register 3 Address offset: 0x08 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x0C-0x18 */ + __IO uint32_t IPGR8; /*!< IP-Plug global register 8 Address offset: 0x1C */ + __IO uint32_t IPC1R1; /*!< IP-Plug client 1 register 1 Address offset: 0x20 */ + __IO uint32_t IPC1R2; /*!< IP-Plug client 1 register 2 Address offset: 0x24 */ + __IO uint32_t IPC1R3; /*!< IP-Plug client 1 register 3 Address offset: 0x28 */ + __IO uint32_t RESERVED2[54]; /*!< Reserved, Address offset: 0x2C-0x100 */ + __IO uint32_t PRCR; /*!< Parallel interface control register Address offset: 0x104 */ + __IO uint32_t PRESCR; /*!< Parallel interface embedded sync code register Address offset: 0x108 */ + __IO uint32_t PRESUR; /*!< Parallel interface embedded sync unmask register Address offset: 0x10C */ + __IO uint32_t RESERVED3[57]; /*!< Reserved, Address offset: 0x110-0x1F0 */ + __IO uint32_t PRIER; /*!< Parallel interface interrupt enable register Address offset: 0x1F4 */ + __IO uint32_t PRSR; /*!< Parallel interface status register Address offset: 0x1F8 */ + __IO uint32_t PRFCR; /*!< Parallel interface interrupt clear register Address offset: 0x1FC */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x200 */ + __IO uint32_t CMCR; /*!< Common configuration register Address offset: 0x204 */ + __IO uint32_t CMFRCR; /*!< Common frame counter register Address offset: 0x208 */ + __IO uint32_t RESERVED5[121]; /*!< Reserved, Address offset: 0x20C-0x3EC */ + __IO uint32_t CMIER; /*!< Common interrupt enable register Address offset: 0x3F0 */ + __IO uint32_t CMSR1; /*!< Common status register 1 Address offset: 0x3F4 */ + __IO uint32_t CMSR2; /*!< Common status register 2 Address offset: 0x3F8 */ + __IO uint32_t CMFCR; /*!< Common interrupt clear register Address offset: 0x3FC */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x400 */ + __IO uint32_t P0FSCR; /*!< Pipe0 flow selection configuration register Address offset: 0x404 */ + __IO uint32_t RESERVED7[62]; /*!< Reserved, Address offset: 0x408-0x4FC */ + __IO uint32_t P0FCTCR; /*!< Pipe0 flow control configuration register Address offset: 0x500 */ + __IO uint32_t P0SCSTR; /*!< Pipe0 stat/crop start register Address offset: 0x504 */ + __IO uint32_t P0SCSZR; /*!< Pipe0 stat/crop size register Address offset: 0x508 */ + __IO uint32_t RESERVED8[41]; /*!< Reserved, Address offset: 0x50C-0x5AC */ + __IO uint32_t P0DCCNTR; /*!< Pipe0 dump counter register Address offset: 0x5B0 */ + __IO uint32_t P0DCLMTR; /*!< Pipe0 dump limit register Address offset: 0x5B4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x5B8-0x5BC */ + __IO uint32_t P0PPCR; /*!< Pipe0 pixel packer configuration register Address offset: 0x5C0 */ + __IO uint32_t P0PPM0AR1; /*!< Pipe0 pixel packer memory0 address register 1 Address offset: 0x5C4 */ + __IO uint32_t P0PPM0AR2; /*!< Pipe0 pixel packer memory0 address register 2 Address offset: 0x5C8 */ + __IO uint32_t RESERVED10[10]; /*!< Reserved, Address offset: 0x5CC-0x5F0 */ + __IO uint32_t P0IER; /*!< Pipe0 interrupt enable register Address offset: 0x5F4 */ + __IO uint32_t P0SR; /*!< Pipe0 status register Address offset: 0x5F8 */ + __IO uint32_t P0FCR; /*!< Pipe0 interrupt clear register Address offset: 0x5FC */ + __IO uint32_t RESERVED11[64]; /*!< Reserved, Address offset: 0x600-0x6FC */ + __IO uint32_t P0CFCTCR; /*!< Pipe0 current flow control configuration register Address offset: 0x700 */ + __IO uint32_t P0CSCSTR; /*!< Pipe0 current stat/crop start register Address offset: 0x704 */ + __IO uint32_t P0CSCSZR; /*!< Pipe0 current stat/crop size register Address offset: 0x708 */ + __IO uint32_t RESERVED12[45]; /*!< Reserved, Address offset: 0x70C-0x7BC */ + __IO uint32_t P0CPPCR; /*!< Pipe0 current pixel packer configuration register Address offset: 0x700 */ + __IO uint32_t P0CPPM0AR1; /*!< Pipe0 current pixel packer memory0 address register 1 Address offset: 0x7C4 */ + __IO uint32_t P0CPPM0AR2; /*!< Pipe0 current pixel packer memory0 address register 2 Address offset: 0x7C8 */ +} DCMIPP_TypeDef; + +/** + * @ brief Delay Block + */ +typedef struct +{ + __IO uint32_t CR; /*!< Delay Block Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA masked interrupt status register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */ +} DMA2D_TypeDef; + +/** + * @brief DTS + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */ + __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */ + __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */ + __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */ + __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */ +} DTS_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x08 */ + uint32_t RESERVED1[5]; /*!< Reserved 1, Address offset: 0x0C-0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x28 */ + uint32_t RESERVED2[21]; /*!< Reserved 2, Address offset: 0x2C-0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x84 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x88 */ + uint32_t RESERVED3; /*!< Reserved 3, Address offset: 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x94 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x98 */ + uint32_t RESERVED4; /*!< Reserved 4, Address offset: 0x9C */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register 3, Address offset: 0xA0 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register 3, Address offset: 0xA4 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x000 */ + __IO uint32_t KEYR; /*!< FLASH control key register, Address offset: 0x004 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x008 - 0x00C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x010 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t IER; /*!< FLASH interrupt enable register, Address offset: 0x020 */ + __IO uint32_t ISR; /*!< FLASH interrupt status register, Address offset: 0x024 */ + __IO uint32_t ICR; /*!< FLASH interrupt clear register, Address offset: 0x028 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t CRCCR; /*!< FLASH CRC control register, Address offset: 0x030 */ + __IO uint32_t CRCSADDR; /*!< FLASH CRC start address register, Address offset: 0x034 */ + __IO uint32_t CRCEADDR; /*!< FLASH CRC end address register, Address offset: 0x038 */ + __IO uint32_t CRCDATAR; /*!< FLASH CRC data register, Address offset: 0x03C */ + __IO uint32_t ECCSFADDR; /*!< FLASH ECC single fail address register, Address offset: 0x040 */ + __IO uint32_t ECCDFADDR; /*!< FLASH ECC double fail address register, Address offset: 0x044 */ + uint32_t RESERVED4[46]; /*!< Reserved, Address offset: 0x048 - 0x0FC */ + __IO uint32_t OPTKEYR; /*!< FLASH options key register, Address offset: 0x100 */ + __IO uint32_t OPTCR; /*!< FLASH options control register, Address offset: 0x104 */ + __IO uint32_t OPTISR; /*!< FLASH options interrupt status register, Address offset: 0x108 */ + __IO uint32_t OPTICR; /*!< FLASH options interrupt clear register, Address offset: 0x10C */ + __IO uint32_t OBKCR; /*!< FLASH option byte key control register, Address offset: 0x110 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x114 */ + __IO uint32_t OBKDR[8]; /*!< FLASH option bytes key data register, Address offset: 0x118 - 0x134 */ + uint32_t RESERVED6[50]; /*!< Reserved, Address offset: 0x138 - 0x1FC */ + __IO uint32_t NVSR; /*!< FLASH non-volatile status register, Address offset: 0x200 */ + __IO uint32_t NVSRP; /*!< FLASH security status register programming, Address offset: 0x204 */ + __IO uint32_t ROTSR; /*!< FLASH RoT status register, Address offset: 0x208 */ + __IO uint32_t ROTSRP; /*!< FLASH RoT status register programming, Address offset: 0x20C */ + __IO uint32_t OTPLSR; /*!< FLASH OTP lock status register, Address offset: 0x210 */ + __IO uint32_t OTPLSRP; /*!< FLASH OTP lock status programming register, Address offset: 0x214 */ + __IO uint32_t WRPSR; /*!< FLASH write protection status register, Address offset: 0x218 */ + __IO uint32_t WRPSRP; /*!< FLASH write protection status register programming, Address offset: 0x21C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x220 - 0x22C */ + __IO uint32_t HDPSR; /*!< FLASH hide protection status register, Address offset: 0x230 */ + __IO uint32_t HDPSRP; /*!< FLASH hide protection status register programming, Address offset: 0x234 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0x238 - 0x24C */ + __IO uint32_t EPOCHSR; /*!< FLASH epoch status register, Address offset: 0x250 */ + __IO uint32_t EPOCHSRP; /*!< FLASH epoch status register programming, Address offset: 0x254 */ + uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x258 - 0x25C */ + __IO uint32_t OBW1SR; /*!< FLASH option byte word 1 status register, Address offset: 0x260 */ + __IO uint32_t OBW1SRP; /*!< FLASH option byte word 1 status register programming, Address offset: 0x264 */ + __IO uint32_t OBW2SR; /*!< FLASH option byte word 2 status register, Address offset: 0x268 */ + __IO uint32_t OBW2SRP; /*!< FLASH option byte word 2 status register programming, Address offset: 0x26C */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1 + */ +typedef struct { + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1 Extended + */ +typedef struct { + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct { + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 & 6 + */ +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140 - 0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148 - 0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief GFXMMU + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved0, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + __IO uint32_t DAR; /*!< GFXMMU default alpha register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved1, Address offset: 0x18 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + + +/** + * @brief Instruction Cache + */ + +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ +} ICACHE_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 0x00 */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 0x04 */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 0x08 */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0x0C */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 0x10 */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 0x14 */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 0x18 */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 0x1C */ + uint32_t RESERVED0[4]; /* Reserved Address offset: 0x20-0x2C */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 0x30 */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 0x34 */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 0x38 */ + uint32_t RESERVED1; /* Reserved Address offset: 0x3C */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 0x40 */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 0x44 */ + uint32_t RESERVED2[2]; /* Reserved Address offset: 0x48-0x4C */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 0x50-0x8C */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 0x90-0xCC */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: 0xD0-0x10C */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 0x110-0x14C */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 0x150-0x18C */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 0x190-0x20C */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 0x210-0x35C */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 0x360-0x4F8 */ + uint32_t RESERVED3; /* Reserved Address offset: 0x4FC */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 0x500-0x65C */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 0x660-0x7BC */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 0x7C0-0x7DC */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 0x7E0-0x7FC */ +} JPEG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + +/** + * @brief ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ +} MDF_TypeDef; + +/** + * @brief ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x94-0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + uint32_t RESERVED1[1]; /*!< Reserved, 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED3[10]; /*!< Reserved, 0xC8-0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0xA4-0xA8 */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0xB8-0xC0 */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0xC4 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief XSPI + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control Register, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration Register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration Register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration Register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration Register 4, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t SR; /*!< XSPI Status Register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear Register, Address offset: 0x024 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x028 - 0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length Register, Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address Register, Address offset: 0x048 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data Register, Address offset: 0x050 */ + uint32_t RESERVED6[11]; /*!< Reserved, Address offset: 0x054 - 0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask Register, Address offset: 0x080 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match Register, Address offset: 0x088 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval Register, Address offset: 0x090 */ + uint32_t RESERVED9[27]; /*!< Reserved, Address offset: 0x094 - 0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration Register, Address offset: 0x100 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration Register, Address offset: 0x108 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction Register, Address offset: 0x110 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x114 - 0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes Register, Address offset: 0x120 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x124 - 0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low-Power Timeout Register, Address offset: 0x130 */ + uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x134 - 0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration Register, Address offset: 0x140 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration Register, Address offset: 0x148 */ + uint32_t RESERVED16; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction Register, Address offset: 0x150 */ + uint32_t RESERVED17[3]; /*!< Reserved, Address offset: 0x154 - 0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes Register, Address offset: 0x160 */ + uint32_t RESERVED18[7]; /*!< Reserved, Address offset: 0x164 - 0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration Register, Address offset: 0x180 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration Register, Address offset: 0x188 */ + uint32_t RESERVED20; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction Register, Address offset: 0x190 */ + uint32_t RESERVED21[3]; /*!< Reserved, Address offset: 0x194 - 0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes Register, Address offset: 0x1A0 */ + uint32_t RESERVED22[23]; /*!< Reserved, Address offset: 0x1A4 - 0x1FC */ + __IO uint32_t HLCR; /*!< XSPI HyperBus Latency Configuration Register, Address offset: 0x200 */ + uint32_t RESERVED23[3]; /*!< Reserved, Address offset: 0x204 - 0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-Cycle Calibration Configuration Register, Address offset: 0x210 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL Master Calibration Configuration Register, Address offset: 0x218 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220 */ + uint32_t RESERVED26; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI Slave Input Calibration Configuration Register, Address offset: 0x228 */ +} XSPI_TypeDef; + +/** + * @brief XSPI IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPIM IO Manager Control Register, Address offset: 0x00 */ +} XSPIM_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x04 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x08 */ + __IO uint32_t CSR2; /*!< PWR power control status register 2, Address offset: 0x0C */ + __IO uint32_t CSR3; /*!< PWR power control status register 3, Address offset: 0x10 */ + __IO uint32_t CSR4; /*!< PWR power control status register 4, Address offset: 0x14 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< PWR USB Type-C and power delivery register, Address offset: 0x2C */ + __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x30 */ + __IO uint32_t PUCRN; /*!< PWR port N pull-up control register, Address offset: 0x34 */ + __IO uint32_t PDCRN; /*!< PWR port N pull-down control register, Address offset: 0x38 */ + __IO uint32_t PUCRO; /*!< PWR port O pull-up control register, Address offset: 0x3C */ + __IO uint32_t PDCRO; /*!< PWR port O pull-down control register, Address offset: 0x40 */ + __IO uint32_t PDCRP; /*!< PWR port P pull-down control register, Address offset: 0x44 */ + uint32_t RESERVED2[2]; /*!< Reserved */ + __IO uint32_t PDR1; /*!< PWR debug register 1, Address offset: 0x50 */ +} PWR_TypeDef; + +/** + * @brief Public Key Accelerator (PKA) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved1[253]; /*!< Reserved, Address offset: 0x000C-0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x0400-0x18D8 */ +} PKA_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI clock calibration register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock recovery RC register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI clock calibration register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CDCFGR; /*!< RCC CPU domain configuration register, Address offset: 0x18 */ + __IO uint32_t BMCFGR; /*!< RCC Bus matrix configuration register, Address offset: 0x1C */ + __IO uint32_t APBCFGR; /*!< RCC APB clock configuration register, Address offset: 0x20 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs clock source selection register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs configuration register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR1; /*!< RCC PLL1 dividers configuration register 1, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 fractional divider configuration register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR1; /*!< RCC PLL2 dividers configuration register 1, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 fractional divider configuration register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR1; /*!< RCC PLL3 dividers configuration register 1, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 fractional divider configuration register, Address offset: 0x44 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t CCIPR1; /*!< RCC AHB peripherals kernel clock configuration register Address offset: 0x4C */ + __IO uint32_t CCIPR2; /*!< RCC APB1 peripherals kernel clock configuration register Address offset: 0x50 */ + __IO uint32_t CCIPR3; /*!< RCC APB2 peripherals kernel clock configuration register Address offset: 0x54 */ + __IO uint32_t CCIPR4; /*!< RCC APB4/APB5 peripherals kernel clock configuration register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x68 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB5RSTR; /*!< RCC AHB5 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB5RSTR; /*!< RCC APB5 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x90 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0xA0 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0xA4 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0xA8-0xAC */ + __IO uint32_t CKGDISR ; /*!< RCC AXI clocks gating disable register, Address offset: 0xB0 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0xB4-0xBC */ + __IO uint32_t PLL1DIVR2; /*!< RCC PLL1 dividers configuration register 2, Address offset: 0xC0 */ + __IO uint32_t PLL2DIVR2; /*!< RCC PLL2 dividers configuration register 2, Address offset: 0xC4 */ + __IO uint32_t PLL3DIVR2; /*!< RCC PLL3 dividers configuration register 2, Address offset: 0xC8 */ + __IO uint32_t PLL1SSCGR; /*!< RCC PLL1 spread spectrum clock generator register, Address offset: 0xCC */ + __IO uint32_t PLL2SSCGR; /*!< RCC PLL2 spread spectrum clock generator register, Address offset: 0xD0 */ + __IO uint32_t PLL3SSCGR; /*!< RCC PLL3 spread spectrum clock generator register, Address offset: 0xD4 */ + uint32_t RESERVED9[10]; /*!< Reserved, Address offset: 0xD8-0xFC */ + __IO uint32_t CKPROTR; /*!< RCC clock protection register, Address offset: 0x100 */ + uint32_t RESERVED10[11]; /*!< Reserved, Address offset: 0x104-0x12C */ + __IO uint32_t RSR; /*!< RCC reset status register, Address offset: 0x130 */ + __IO uint32_t AHB5ENR; /*!< RCC AHB5 peripheral clocks enable register, Address offset: 0x134 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x138 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x13C */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clocks enable register, Address offset: 0x140 */ + __IO uint32_t APB5ENR; /*!< RCC APB5 peripheral clocks enable register, Address offset: 0x144 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x148 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x14C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x150 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clocks enable register, Address offset: 0x154 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x158 */ + __IO uint32_t AHB5LPENR; /*!< RCC AHB5 peripheral sleep clocks enable register, Address offset: 0x15C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clocks enable register, Address offset: 0x160 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clocks enable register, Address offset: 0x164 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clocks enable register, Address offset: 0x168 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clocks enable register, Address offset: 0x16C */ + __IO uint32_t APB1LPENR1; /*!< RCC APB1 peripheral sleep clocks enable register 1, Address offset: 0x170 */ + __IO uint32_t APB1LPENR2; /*!< RCC APB1 peripheral sleep clocks enable register 2, Address offset: 0x174 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clocks enable register, Address offset: 0x178 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clocks enable register, Address offset: 0x17C */ + __IO uint32_t APB5LPENR; /*!< RCC APB5 peripheral sleep clocks enable register, Address offset: 0x180 */ +} RCC_TypeDef; + +/** + * @brief Random Number Generator + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration, boot and security controller + */ +typedef struct +{ + __IO uint32_t BOOTSR; /*!< SBS Boot Status register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04-0x0C */ + __IO uint32_t HDPLCR; /*!< SBS Hide Protection Control register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS Hide Protection Status register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x28-0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command register, Address offset: 0x34 */ + uint32_t RESERVED4[50]; /*!< Reserved, Address offset: 0x38-0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status register, Address offset: 0x108 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS IO Compensation Cell Control and Status register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS IO Compensation Cell Value register, Address offset: 0x114 */ + __IO uint32_t CCSWVALR; /*!< SBS IO Compensation Cell Software Value register, Address offset: 0x118 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x11C */ + __IO uint32_t BKLOCKR; /*!< SBS Break Lockup register, Address offset: 0x120 */ + uint32_t RESERVED7[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t EXTICR[4]; /*!< SBS External Interrupt Configuration registers, Address offset: 0x130-0x13C */ +} SBS_TypeDef; + +/** + * @brief Secure Digital Card/IO Embedded MultiMediaCard Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC Power control register, Address offset : 0x000 */ + __IO uint32_t CLKCR; /*!< SDMMC Clock control register, Address offset : 0x004 */ + __IO uint32_t ARG; /*!< SDMMC Argument register, Address offset : 0x008 */ + __IO uint32_t CMD; /*!< SDMMC Command register, Address offset : 0x00C */ + __IO uint32_t RESPCMD; /*!< SDMMC Command response register, Address offset : 0x010 */ + __IO uint32_t RESP1; /*!< SDMMC Response 1 register, Address offset : 0x014 */ + __IO uint32_t RESP2; /*!< SDMMC Response 2 register, Address offset : 0x018 */ + __IO uint32_t RESP3; /*!< SDMMC Response 3 register, Address offset : 0x01C */ + __IO uint32_t RESP4; /*!< SDMMC Response 4 register, Address offset : 0x020 */ + __IO uint32_t DTIMER; /*!< SDMMC Data timer register, Address offset : 0x024 */ + __IO uint32_t DLEN; /*!< SDMMC Data length register, Address offset : 0x028 */ + __IO uint32_t DCTRL; /*!< SDMMC Data control register, Address offset : 0x02C */ + __IO uint32_t DCOUNT; /*!< SDMMC Data counter register, Address offset : 0x030 */ + __IO uint32_t STA; /*!< SDMMC Status register, Address offset : 0x034 */ + __IO uint32_t ICR; /*!< SDMMC Interrupt clear register, Address offset : 0x038 */ + __IO uint32_t MASK; /*!< SDMMC Mask register, Address offset : 0x03C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset : 0x040 */ + uint32_t RESERVED0[3]; /*!< Reserved, Address offset : 0x044 - 0x04C */ + __IO uint32_t IDMACTRL; /*!< SDMMC IDMA control register, Address offset : 0x050 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC IDMA buffer size register, Address offset : 0x054 */ + __IO uint32_t IDMABASER; /*!< SDMMC IDMA buffer base address register, Address offset : 0x058 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset : 0x05C - 0x060 */ + __IO uint32_t IDMALAR; /*!< SDMMC IDMA linked list address register, Address offset : 0x064 */ + __IO uint32_t IDMABAR; /*!< SDMMC IDMA linked list memory base register, Address offset : 0x068 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset : 0x06C - 0x07C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset : 0x080 */ +} SDMMC_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t CFGR; /*!< TAMP configuration control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter 1 register, Address offset: 0x40 */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED5[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + uint32_t RESERVED0[221]; /*!< Reserved, Address offset: 0x68 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Window Watchdog + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32H7RSxx_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup STM32H7RSxx_Peripheral_peripheralAddr + * @{ + */ +#define ITCM_BASE 0x00000000UL /*!< ITCM base address */ +#define FLASH_BASE 0x08000000UL /*!< User Flash address */ +#define OTP_AREA_BASE 0x08FFF000UL /*!< OTP Area base address */ +#define ENGI_BYTES_BASE 0x52002800UL /*!< Engi Bytes */ +#define SYSTEM_FLASH_BASE 0x1FF00000UL /*!< System Flash base address */ +#define DTCM_BASE 0x20000000UL /*!< DTCM base address */ +#define SRAM1_AXI_BASE 0x24000000UL /*!< SRAM1 base address - accessible over AXI */ +#define SRAM2_AXI_BASE 0x24020000UL /*!< SRAM2 base address - accessible over AXI */ +#define SRAM3_AXI_BASE 0x24040000UL /*!< SRAM3 base address - accessible over AXI */ +#define SRAM4_AXI_BASE 0x24060000UL /*!< SRAM4 base address - accessible over AXI */ + +#define GFXMMU_VIRTUAL_BUFFER0_BASE 0x25000000UL /*!< GFXMMU virtual buffer 0 base address */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE 0x25400000UL /*!< GFXMMU virtual buffer 1 base address */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE 0x25800000UL /*!< GFXMMU virtual buffer 2 base address */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE 0x25C00000UL /*!< GFXMMU virtual buffer 3 base address */ + +#define SRAM1_AHB_BASE 0x30000000UL /*!< SRAM1 base address */ +#define SRAM2_AHB_BASE 0x30004000UL /*!< SRAM2 base address */ +#define BKPSRAM_BASE 0x38800000UL /*!< Backup SRAM */ + +#define PERIPH_BASE 0x40000000UL /*!< AHB and APB Peripherals base address */ +#define XSPI2_BASE 0x70000000UL /*!< XSPI2 base address */ +#define XSPI1_BASE 0x90000000UL /*!< XSPI1 base address */ + +/*!< Internal memory size */ +#define ITCM_SIZE 0x00010000UL /*!< 64 KB default, can be increased up to 192 KB */ +#define DTCM_SIZE 0x00010000UL /*!< 64 KB default, can be increased up to 192 KB */ +#define FLASH_SIZE 0x00010000UL /*!< 64 KB */ +#define SRAM1_AXI_SIZE 0x00020000UL /*!< 128 KB default, can be decreased down to 0 KB to increase ITCM */ +#define SRAM2_AXI_SIZE 0x00020000UL /*!< 128 KB */ +#define SRAM3_AXI_SIZE 0x00020000UL /*!< 128 KB default, can be decreased down to 0 KB to increase DTCM */ +#define SRAM4_AXI_SIZE 0x00012000UL /*!< 72 KB default, can be decreased to 0 KB when RAM ECC is disable */ +#define SRAM_AHB_SIZE 0x00004000UL /*!< Both AHB SRAMs are 16 KB */ +#define BKPSRAM_SIZE 0x00001000UL /*!< 4 KB */ + +/*!< OTP Area size */ +#define OTP_SIZE 0x400U /* 1 KB */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x02000000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x08020000UL) +#define APB5PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define AHB5PERIPH_BASE (PERIPH_BASE + 0x12000000UL) +#define APB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define AHB4PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I3C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x8400UL) +#define MDIOS_BASE (APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0xA100UL) /*!< FDCAN configuration registers base address */ +#define FDCAN2_BASE (APB1PERIPH_BASE + 0xA400UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xAC00UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xEC00UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00UL) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define GPDMA1_Channel0_BASE (GPDMA1_BASE + 0x0050UL) +#define GPDMA1_Channel1_BASE (GPDMA1_BASE + 0x00D0UL) +#define GPDMA1_Channel2_BASE (GPDMA1_BASE + 0x0150UL) +#define GPDMA1_Channel3_BASE (GPDMA1_BASE + 0x01D0UL) +#define GPDMA1_Channel4_BASE (GPDMA1_BASE + 0x0250UL) +#define GPDMA1_Channel5_BASE (GPDMA1_BASE + 0x02D0UL) +#define GPDMA1_Channel6_BASE (GPDMA1_BASE + 0x0350UL) +#define GPDMA1_Channel7_BASE (GPDMA1_BASE + 0x03D0UL) +#define GPDMA1_Channel8_BASE (GPDMA1_BASE + 0x0450UL) +#define GPDMA1_Channel9_BASE (GPDMA1_BASE + 0x04D0UL) +#define GPDMA1_Channel10_BASE (GPDMA1_BASE + 0x0550UL) +#define GPDMA1_Channel11_BASE (GPDMA1_BASE + 0x05D0UL) +#define GPDMA1_Channel12_BASE (GPDMA1_BASE + 0x0650UL) +#define GPDMA1_Channel13_BASE (GPDMA1_BASE + 0x06D0UL) +#define GPDMA1_Channel14_BASE (GPDMA1_BASE + 0x0750UL) +#define GPDMA1_Channel15_BASE (GPDMA1_BASE + 0x07D0UL) +#define ADC1_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) +#define ADF1_BASE (AHB1PERIPH_BASE + 0xF000UL) +#define ADF1_Filter0_BASE (ADF1_BASE + 0x0080UL) +#define USB_OTG_HS_PERIPH_BASE (AHB1PERIPH_BASE + 0x20000UL) +#define USB_OTG_FS_PERIPH_BASE (AHB1PERIPH_BASE + 0x60000UL) + +/*!< AHB2 peripherals */ +#define PSSI_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define SDMMC2_BASE (AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (AHB2PERIPH_BASE + 0x2800UL) +#define CORDIC_BASE (AHB2PERIPH_BASE + 0x4400UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE AHB3PERIPH_BASE +#define HASH_BASE (AHB3PERIPH_BASE + 0x0400UL) +#define HASH_DIGEST_BASE (AHB3PERIPH_BASE + 0x0710UL) +#define PKA_BASE (AHB3PERIPH_BASE + 0x2000UL) + +/*!< APB5 peripherals */ +#define LTDC_BASE (APB5PERIPH_BASE + 0x1000UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x0084UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x0104UL) +#define DCMIPP_BASE (APB5PERIPH_BASE + 0x2000UL) +#define GFXTIM_BASE (APB5PERIPH_BASE + 0x4000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE AHB5PERIPH_BASE +#define HPDMA1_Channel0_BASE (HPDMA1_BASE + 0x0050UL) +#define HPDMA1_Channel1_BASE (HPDMA1_BASE + 0x00D0UL) +#define HPDMA1_Channel2_BASE (HPDMA1_BASE + 0x0150UL) +#define HPDMA1_Channel3_BASE (HPDMA1_BASE + 0x01D0UL) +#define HPDMA1_Channel4_BASE (HPDMA1_BASE + 0x0250UL) +#define HPDMA1_Channel5_BASE (HPDMA1_BASE + 0x02D0UL) +#define HPDMA1_Channel6_BASE (HPDMA1_BASE + 0x0350UL) +#define HPDMA1_Channel7_BASE (HPDMA1_BASE + 0x03D0UL) +#define HPDMA1_Channel8_BASE (HPDMA1_BASE + 0x0450UL) +#define HPDMA1_Channel9_BASE (HPDMA1_BASE + 0x04D0UL) +#define HPDMA1_Channel10_BASE (HPDMA1_BASE + 0x0550UL) +#define HPDMA1_Channel11_BASE (HPDMA1_BASE + 0x05D0UL) +#define HPDMA1_Channel12_BASE (HPDMA1_BASE + 0x0650UL) +#define HPDMA1_Channel13_BASE (HPDMA1_BASE + 0x06D0UL) +#define HPDMA1_Channel14_BASE (HPDMA1_BASE + 0x0750UL) +#define HPDMA1_Channel15_BASE (HPDMA1_BASE + 0x07D0UL) +#define DMA2D_BASE (AHB5PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB5PERIPH_BASE + 0x2000UL) +#define JPEG_BASE (AHB5PERIPH_BASE + 0x3000UL) +#define FMC_R_BASE (AHB5PERIPH_BASE + 0x4000UL) +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) +#define XSPI1_R_BASE (AHB5PERIPH_BASE + 0x5000UL) +#define SDMMC1_BASE (AHB5PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (AHB5PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (AHB5PERIPH_BASE + 0x9000UL) +#define RAMECC1_Monitor0_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0xA0UL) +#define XSPI2_R_BASE (AHB5PERIPH_BASE + 0xA000UL) +#define XSPIM_BASE (AHB5PERIPH_BASE + 0xB400UL) +#define GFXMMU_BASE (AHB5PERIPH_BASE + 0x010000UL) +#define GPU2D_BASE (AHB5PERIPH_BASE + 0x014000UL) +#define ICACHE_BASE (AHB5PERIPH_BASE + 0x015000UL) + +/*!< APB4 peripherals */ +#define EXTI_BASE APB4PERIPH_BASE +#define SBS_BASE (APB4PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (APB4PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (APB4PERIPH_BASE + 0x1400UL) +#define LPTIM2_BASE (APB4PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (APB4PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (APB4PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (APB4PERIPH_BASE + 0x3000UL) +#define VREFBUF_BASE (APB4PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (APB4PERIPH_BASE + 0x4000UL) +#define TAMP_BASE (APB4PERIPH_BASE + 0x4400UL) +#define IWDG_BASE (APB4PERIPH_BASE + 0x4800UL) +#define DTS_BASE (APB4PERIPH_BASE + 0x6800UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE AHB4PERIPH_BASE +#define GPIOB_BASE (AHB4PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB4PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB4PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB4PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB4PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB4PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB4PERIPH_BASE + 0x1C00UL) +#define GPIOM_BASE (AHB4PERIPH_BASE + 0x3000UL) +#define GPION_BASE (AHB4PERIPH_BASE + 0x3400UL) +#define GPIOO_BASE (AHB4PERIPH_BASE + 0x3800UL) +#define GPIOP_BASE (AHB4PERIPH_BASE + 0x3C00UL) +#define RCC_BASE (AHB4PERIPH_BASE + 0x4400UL) +#define PWR_BASE (AHB4PERIPH_BASE + 0x4800UL) +#define CRC_BASE (AHB4PERIPH_BASE + 0x4C00UL) +#define RAMECC2_BASE (AHB4PERIPH_BASE + 0x7000UL) +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x40UL) + +/*!< Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +/*!< AXIM registers base address */ +#define AXIM_BASE (0xBFF00000UL) +#define AXIM_ASIB1_BASE (AXIM_BASE + 0x42000UL) +#define AXIM_ASIB2_BASE (AXIM_BASE + 0x43000UL) +#define AXIM_ASIB3_BASE (AXIM_BASE + 0x44000UL) +#define AXIM_ASIB4_BASE (AXIM_BASE + 0x45000UL) +#define AXIM_ASIB5_BASE (AXIM_BASE + 0x46000UL) +#define AXIM_ASIB6_BASE (AXIM_BASE + 0x47000UL) +#define AXIM_ASIB7_BASE (AXIM_BASE + 0x48000UL) +#define AXIM_ASIB8_BASE (AXIM_BASE + 0x49000UL) +#define AXIM_ASIB9_BASE (AXIM_BASE + 0x4A000UL) +#define AXIM_ASIB10_BASE (AXIM_BASE + 0x4B000UL) +#define AXIM_ASIB11_BASE (AXIM_BASE + 0x4C000UL) +#define AXIM_AMIB1_BASE (AXIM_BASE + 0x02000UL) +#define AXIM_AMIB2_BASE (AXIM_BASE + 0x03000UL) +#define AXIM_AMIB3_BASE (AXIM_BASE + 0x04000UL) +#define AXIM_AMIB4_BASE (AXIM_BASE + 0x05000UL) +#define AXIM_AMIB5_BASE (AXIM_BASE + 0x06000UL) +#define AXIM_AMIB6_BASE (AXIM_BASE + 0x07000UL) +#define AXIM_AMIB7_BASE (AXIM_BASE + 0x08000UL) +#define AXIM_AMIB8_BASE (AXIM_BASE + 0x09000UL) +#define AXIM_AMIB9_BASE (AXIM_BASE + 0x0A000UL) +#define AXIM_AMIB10_BASE (AXIM_BASE + 0x0B000UL) + +/*!< Unique device ID register base address */ +#define UID_BASE (0x08FFF800UL) + +/*!< Flash size data register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) + +/*!< Package data register base address */ +#define PACKAGE_BASE (0x08FFF80CUL) + +/* USB OTG registers base addresses */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_PFUNC_START (0x1FF1FD4CUL) +#define RSSLIB_SYS_FLASH_PFUNC_END (0x1FF1FD78UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0x1FF1FD4CUL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t Destination; /*!< OBKeys destination information where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + +/** + * @brief Prototype of RSSLIB Set Secure OB Function + * @detail This function configure a secure OB. + * @param OB address among following values: + * &(FLASH->WRPSRP), &(FLASH->HDPSRP) or &(FLASH->ROTSRP) + * @param OB mask (example 0x000000FF for updating WRP OB). + * @param OB value + * @param OB Pos: bit position of OB value. + * ObValue << ObPos must be aligned on ObMask. + * @retval RSSLIB_RSS_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_SetSecOB_TypeDef)(uint32_t ObAddr, uint32_t ObMask, uint32_t ObValue, uint32_t ObPos); + +/** + * @brief Prototype of RSSLIB Get RSS Status Function + * @detail This function return RSS Status. + * Calling GetRssStatus is only relevant after calling + * SetSecOB or DataProvisioning. + * @param none. + * @retval RSSLIB_SUCCESS on success, otherwise return an error 0xF5F5xxxx. + */ +typedef uint32_t (*RSSLIB_GetRssStatus_TypeDef)(void); + +/** + * @brief Prototype of RSSLIB Set Product State Function + * @detail This function change Product State. + * @param Requested Product State among following values: + * 0x17 : Provisioning + * 0x72 : Closed + * 0x5C : Locked + * @retval RSSLIB_RSS_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_SetProductState_TypeDef)(uint32_t ProductState); + +/** + * @brief Prototype of RSSLIB Get Product State Function + * @detail This function return current Product State. + * @param none. + * @retval RSSLIB_RSS_ERROR on error, + * otherwise return product state among following values: + * 0x39 : Open + * 0x17 : Provisioning + * 0x72 : Closed + * 0x5C : Locked + */ +typedef uint32_t (*RSSLIB_GetProductState_TypeDef)(void); + + +/** + * @brief RSSLib callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_SetSecOB_TypeDef SetSecOB; + uint32_t RESERVED1[4]; + __IM RSSLIB_GetRssStatus_TypeDef GetRssStatus; + __IM RSSLIB_SetProductState_TypeDef SetProductState; + __IM RSSLIB_DataProvisioning_TypeDef DataProvisioning; + __IM RSSLIB_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_GetProductState_TypeDef GetProductState; +} RSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32H7RSxx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H7RSxx_Peripheral_declaration + * @{ + */ + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADF1 ((MDF_TypeDef *) ADF1_BASE) +#define ADF1_Filter0 ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE) +#define AXIM_AMIB_1 ((AXIM_AMIB_TypeDef *) AXIM_AMIB1_BASE ) +#define AXIM_AMIB_2 ((AXIM_AMIB_TypeDef *) AXIM_AMIB2_BASE ) +#define AXIM_AMIB_3 ((AXIM_AMIB_TypeDef *) AXIM_AMIB3_BASE ) +#define AXIM_AMIB_4 ((AXIM_AMIB_TypeDef *) AXIM_AMIB4_BASE ) +#define AXIM_AMIB_5 ((AXIM_AMIB_TypeDef *) AXIM_AMIB5_BASE ) +#define AXIM_AMIB_6 ((AXIM_AMIB_TypeDef *) AXIM_AMIB6_BASE ) +#define AXIM_AMIB_7 ((AXIM_AMIB_TypeDef *) AXIM_AMIB7_BASE ) +#define AXIM_AMIB_8 ((AXIM_AMIB_TypeDef *) AXIM_AMIB8_BASE ) +#define AXIM_AMIB_9 ((AXIM_AMIB_TypeDef *) AXIM_AMIB9_BASE ) +#define AXIM_AMIB_10 ((AXIM_AMIB_TypeDef *) AXIM_AMIB10_BASE) +#define AXIM_ASIB_1 ((AXIM_ASIB_TypeDef *) AXIM_ASIB1_BASE ) +#define AXIM_ASIB_2 ((AXIM_ASIB_TypeDef *) AXIM_ASIB2_BASE ) +#define AXIM_ASIB_3 ((AXIM_ASIB_TypeDef *) AXIM_ASIB3_BASE ) +#define AXIM_ASIB_4 ((AXIM_ASIB_TypeDef *) AXIM_ASIB4_BASE ) +#define AXIM_ASIB_5 ((AXIM_ASIB_TypeDef *) AXIM_ASIB5_BASE ) +#define AXIM_ASIB_6 ((AXIM_ASIB_TypeDef *) AXIM_ASIB6_BASE ) +#define AXIM_ASIB_7 ((AXIM_ASIB_TypeDef *) AXIM_ASIB7_BASE ) +#define AXIM_ASIB_8 ((AXIM_ASIB_TypeDef *) AXIM_ASIB8_BASE ) +#define AXIM_ASIB_9 ((AXIM_ASIB_TypeDef *) AXIM_ASIB9_BASE ) +#define AXIM_ASIB_10 ((AXIM_ASIB_TypeDef *) AXIM_ASIB10_BASE) +#define AXIM_ASIB_11 ((AXIM_ASIB_TypeDef *) AXIM_ASIB11_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define DCMIPP ((DCMIPP_TypeDef *) DCMIPP_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DTS ((DTS_TypeDef *) DTS_BASE) +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define GFXTIM ((GFXTIM_TypeDef *) GFXTIM_BASE) +#define GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE) +#define GPU2D GPU2D_BASE +#define GPDMA1 ((DMA_TypeDef *) GPDMA1_BASE) +#define GPDMA1_Channel0 ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE) +#define GPDMA1_Channel1 ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE) +#define GPDMA1_Channel2 ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE) +#define GPDMA1_Channel3 ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE) +#define GPDMA1_Channel4 ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE) +#define GPDMA1_Channel5 ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE) +#define GPDMA1_Channel6 ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE) +#define GPDMA1_Channel7 ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE) +#define GPDMA1_Channel8 ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE) +#define GPDMA1_Channel9 ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE) +#define GPDMA1_Channel10 ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE) +#define GPDMA1_Channel11 ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE) +#define GPDMA1_Channel12 ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE) +#define GPDMA1_Channel13 ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE) +#define GPDMA1_Channel14 ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE) +#define GPDMA1_Channel15 ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOM ((GPIO_TypeDef *) GPIOM_BASE) +#define GPION ((GPIO_TypeDef *) GPION_BASE) +#define GPIOO ((GPIO_TypeDef *) GPIOO_BASE) +#define GPIOP ((GPIO_TypeDef *) GPIOP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define HPDMA1 ((DMA_TypeDef *) HPDMA1_BASE) +#define HPDMA1_Channel0 ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE) +#define HPDMA1_Channel1 ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE) +#define HPDMA1_Channel2 ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE) +#define HPDMA1_Channel3 ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE) +#define HPDMA1_Channel4 ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE) +#define HPDMA1_Channel5 ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE) +#define HPDMA1_Channel6 ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE) +#define HPDMA1_Channel7 ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE) +#define HPDMA1_Channel8 ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE) +#define HPDMA1_Channel9 ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE) +#define HPDMA1_Channel10 ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE) +#define HPDMA1_Channel11 ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE) +#define HPDMA1_Channel12 ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE) +#define HPDMA1_Channel13 ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE) +#define HPDMA1_Channel14 ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE) +#define HPDMA1_Channel15 ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE) +#define ICACHE ((ICACHE_TypeDef *) ICACHE_BASE) +#define JPEG ((JPEG_TypeDef *) JPEG_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I3C1 ((I3C_TypeDef *) I3C1_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) +#define PKA ((PKA_TypeDef *) PKA_BASE) +#define PSSI ((PSSI_TypeDef *) PSSI_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC1_Monitor0 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor0_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *) SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *) SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *) SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *) SAI2_Block_B_BASE) +#define SBS ((SBS_TypeDef *) SBS_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define XSPI1 ((XSPI_TypeDef *) XSPI1_R_BASE) +#define XSPI2 ((XSPI_TypeDef *) XSPI2_R_BASE) +#define XSPIM ((XSPIM_TypeDef *) XSPIM_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) + +/** @} */ /* End of group STM32H7RSxx_Peripheral_declaration */ + +/** @addtogroup STM32H7RSxx_Peripheral_Exported_constants + * @{ + */ + +/** @addtogroup STM32H7RSxx_Peripheral_Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_Peripheral_Registers_Bits_Definition + * @{ + */ +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_ADFCFG_Pos (2U) +#define ADC_CFGR_ADFCFG_Msk (0x1UL << ADC_CFGR_ADFCFG_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_ADFCFG ADC_CFGR_ADFCFG_Msk /*!< ADC ADF transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register ***************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x1UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC internal path to VDDCORE */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ + +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************************************************************************/ +/* */ +/* AXIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AXIM_ASIB_FNMOD2 register **********/ +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE_Pos (0U) +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE_Msk (0x1UL << AXIM_ASIB_FNMOD2_BYPASS_MERGE_Pos) /*!< 0x00000001 */ +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE AXIM_ASIB_FNMOD2_BYPASS_MERGE_Msk /*!< Bypass Merge enable */ + +/******************* Bit definition for AXIM_ASIB_READQOS register ********/ +#define AXIM_ASIB_READQOS_AR_QOS_Pos (0U) +#define AXIM_ASIB_READQOS_AR_QOS_Msk (0xFUL << AXIM_ASIB_READQOS_AR_QOS_Pos) /*!< 0x0000000F */ +#define AXIM_ASIB_READQOS_AR_QOS AXIM_ASIB_READQOS_AR_QOS_Msk /*!< Read channel QoS setting */ + +/******************* Bit definition for AXIM_ASIB_WRITEQOS register *******/ +#define AXIM_ASIB_WRITEQOS_AW_QOS_Pos (0U) +#define AXIM_ASIB_WRITEQOS_AW_QOS_Msk (0xFUL << AXIM_ASIB_WRITEQOS_AW_QOS_Pos) /*!< 0x0000000F */ +#define AXIM_ASIB_WRITEQOS_AW_QOS AXIM_ASIB_WRITEQOS_AW_QOS_Msk /*!< Write channel QoS setting */ + +/******************* Bit definition for AXIM_ASIB_FNMOD register **********/ +#define AXIM_ASIB_FNMOD_READ_ISS_Pos (0U) +#define AXIM_ASIB_FNMOD_READ_ISS_Msk (0x1UL << AXIM_ASIB_FNMOD_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_ASIB_FNMOD_READ_ISS AXIM_ASIB_FNMOD_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_ASIB_FNMOD_WRITE_ISS_Pos (1U) +#define AXIM_ASIB_FNMOD_WRITE_ISS_Msk (0x1UL << AXIM_ASIB_FNMOD_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_ASIB_FNMOD_WRITE_ISS AXIM_ASIB_FNMOD_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************* Bit definition for AXIM_AMIB_FNMODBMISS register **********/ +#define AXIM_AMIB_FNMODBMISS_READ_ISS_Pos (0U) +#define AXIM_AMIB_FNMODBMISS_READ_ISS_Msk (0x1UL << AXIM_AMIB_FNMODBMISS_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMODBMISS_READ_ISS AXIM_AMIB_FNMODBMISS_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS_Pos (1U) +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS_Msk (0x1UL << AXIM_AMIB_FNMODBMISS_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS AXIM_AMIB_FNMODBMISS_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************* Bit definition for AXIM_AMIB_FNMOD2 register **********/ +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE_Pos (0U) +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE_Msk (0x1UL << AXIM_AMIB_FNMOD2_BYPASS_MERGE_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE AXIM_AMIB_FNMOD2_BYPASS_MERGE_Msk /*!< Bypass Merge enable */ + +/******************* Bit definition for AXIM_AMIB_FNMODLB register **********/ +#define AXIM_AMIB_FNMODLB_LONG_BURST_Pos (0U) +#define AXIM_AMIB_FNMODLB_LONG_BURST_Msk (0x1UL << AXIM_AMIB_FNMODLB_LONG_BURST_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMODLB_LONG_BURST AXIM_AMIB_FNMODLB_LONG_BURST_Msk /*!< Long bursts can be generated */ + +/******************* Bit definition for AXIM_AMIB_FNMOD register **********/ +#define AXIM_AMIB_FNMOD_READ_ISS_Pos (0U) +#define AXIM_AMIB_FNMOD_READ_ISS_Msk (0x1UL << AXIM_AMIB_FNMOD_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMOD_READ_ISS AXIM_AMIB_FNMOD_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_AMIB_FNMOD_WRITE_ISS_Pos (1U) +#define AXIM_AMIB_FNMOD_WRITE_ISS_Msk (0x1UL << AXIM_AMIB_FNMOD_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_AMIB_FNMOD_WRITE_ISS AXIM_AMIB_FNMOD_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* Parallel Synchronous Slave Interface (PSSI ) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PSSI_CR register *******************/ +#define PSSI_CR_CKPOL_Pos (5U) +#define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) /*!< 0x00000020 */ +#define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk /*!< Parallel data clock polarity */ +#define PSSI_CR_DEPOL_Pos (6U) +#define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) /*!< 0x00000040 */ +#define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk /*!< Data enable polarity */ +#define PSSI_CR_RDYPOL_Pos (8U) +#define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) /*!< 0x00000100 */ +#define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk /*!< Ready polarity */ +#define PSSI_CR_EDM_Pos (10U) +#define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define PSSI_CR_EDM PSSI_CR_EDM_Msk /*!< Extended data mode */ +#define PSSI_CR_ENABLE_Pos (14U) +#define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk /*!< PSSI enable */ +#define PSSI_CR_DERDYCFG_Pos (18U) +#define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< 0x001C0000 */ +#define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk /*!< Data enable and ready configuration */ +#define PSSI_CR_CKSRC_Pos (29U) +#define PSSI_CR_CKSRC_Msk (0x1UL << PSSI_CR_CKSRC_Pos) /*!< 0x20000000 */ +#define PSSI_CR_CKSRC PSSI_CR_CKSRC_Msk /*!< Clock source */ +#define PSSI_CR_DMAEN_Pos (30U) +#define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) /*!< 0x40000000 */ +#define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk /*!< DMA enable */ +#define PSSI_CR_OUTEN_Pos (31U) +#define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) /*!< 0x80000000 */ +#define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk /*!< Data direction selection */ + +/******************** Bit definition for PSSI_SR register *******************/ +#define PSSI_SR_RTT4B_Pos (2U) +#define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) /*!< 0x00000004 */ +#define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk /*!< Ready to transfer four bytes */ +#define PSSI_SR_RTT1B_Pos (3U) +#define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) /*!< 0x00000008 */ +#define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk /*!< Ready to transfer one byte */ + +/******************** Bit definition for PSSI_RIS register ******************/ +#define PSSI_RIS_OVR_RIS_Pos (1U) +#define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk /*!< Data buffer overrun/underrun raw interrupt status */ + +/******************** Bit definition for PSSI_IER register ******************/ +#define PSSI_IER_OVR_IE_Pos (1U) +#define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk /*!< Data buffer overrun/underrun interrupt enable */ + +/******************** Bit definition for PSSI_MIS register ******************/ +#define PSSI_MIS_OVR_MIS_Pos (1U) +#define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk /*!< Data buffer overrun/underrun masked interrupt status */ + +/******************** Bit definition for PSSI_ICR register ******************/ +#define PSSI_ICR_OVR_ISC_Pos (1U) +#define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk /*!< Data buffer overrun/underrun interrupt status clear */ + +/******************** Bit definition for PSSI_DR register *******************/ +#define PSSI_DR_DR_Pos (0U) +#define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) /*!< 0xFFFFFFF */ +#define PSSI_DR_DR PSSI_DR_DR_Msk /*!< Data register */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CR1 register *******************/ +#define PWR_CR1_SVOS_Pos (0U) +#define PWR_CR1_SVOS_Msk (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00000001 */ +#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection. */ + +#define PWR_CR1_PVDE_Pos (4U) +#define PWR_CR1_PVDE_Msk (0x1UL << PWR_CR1_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR1_PVDE PWR_CR1_PVDE_Msk /*!< Programmable Voltage detector enable. */ + +#define PWR_CR1_PLS_Pos (5U) +#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */ +#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */ + +#define PWR_CR1_DBP_Pos (8U) +#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */ + +#define PWR_CR1_FLPS_Pos (9U) +#define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) /*!< 0x00000200 */ +#define PWR_CR1_FLPS PWR_CR1_FLPS_Msk /*!< Flash low power mode in STOP */ + +#define PWR_CR1_BOOSTE_Pos (11U) +#define PWR_CR1_BOOSTE_Msk (0x1UL << PWR_CR1_BOOSTE_Pos) /*!< 0x00000800 */ +#define PWR_CR1_BOOSTE PWR_CR1_BOOSTE_Msk /*!< Analog Switch VBoost control. */ + +#define PWR_CR1_AVDREADY_Pos (12) +#define PWR_CR1_AVDREADY_Msk (0x1UL << PWR_CR1_AVDREADY_Pos) /*!< 0x00001000 */ +#define PWR_CR1_AVDREADY PWR_CR1_AVDREADY_Msk /*!< Analog Voltage Ready. */ + +#define PWR_CR1_AVDEN_Pos (13U) +#define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) /*!< 0x00002000 */ +#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */ + +#define PWR_CR1_ALS_Pos (14U) +#define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x0000A000 */ +#define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */ +#define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) /*!< 0x00004000 */ +#define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for PWR_SR1 register ********************/ +#define PWR_SR1_ACTVOS_Pos (0U) +#define PWR_SR1_ACTVOS_Msk (0x1UL << PWR_SR1_ACTVOS_Pos) /*!< 0x00000001 */ +#define PWR_SR1_ACTVOS PWR_SR1_ACTVOS_Msk /*!< VOS currently applied for VCORE voltage scaling selection */ + +#define PWR_SR1_ACTVOSRDY_Pos (1U) +#define PWR_SR1_ACTVOSRDY_Msk (0x1UL << PWR_SR1_ACTVOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_SR1_ACTVOSRDY PWR_SR1_ACTVOSRDY_Msk /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling */ + +#define PWR_SR1_PVDO_Pos (4U) +#define PWR_SR1_PVDO_Msk (0x1UL << PWR_SR1_PVDO_Pos) /*!< 0x00000010 */ +#define PWR_SR1_PVDO PWR_SR1_PVDO_Msk /*!< Programmable Voltage Detect Output */ + +#define PWR_SR1_AVDO_Pos (13U) +#define PWR_SR1_AVDO_Msk (0x1UL << PWR_SR1_AVDO_Pos) /*!< 0x00002000 */ +#define PWR_SR1_AVDO PWR_SR1_AVDO_Msk /*!< Analog Voltage Detect Output on VDDA */ + +/******************** Bit definition for PWR_CSR1 register ********************/ +#define PWR_CSR1_BREN_Pos (0U) +#define PWR_CSR1_BREN_Msk (0x1UL << PWR_CSR1_BREN_Pos) /*!< 0x00000001 */ +#define PWR_CSR1_BREN PWR_CSR1_BREN_Msk /*!< Backup regulator enable */ + +#define PWR_CSR1_MONEN_Pos (4U) +#define PWR_CSR1_MONEN_Msk (0x1UL << PWR_CSR1_MONEN_Pos) /*!< 0x00000010 */ +#define PWR_CSR1_MONEN PWR_CSR1_MONEN_Msk /*!< VBAT and temperature monitoring enable */ + +#define PWR_CSR1_BRRDY_Pos (16U) +#define PWR_CSR1_BRRDY_Msk (0x1UL << PWR_CSR1_BRRDY_Pos) /*!< 0x00010000 */ +#define PWR_CSR1_BRRDY PWR_CSR1_BRRDY_Msk /*!< Backup regulator ready */ + +#define PWR_CSR1_VBATL_Pos (20U) +#define PWR_CSR1_VBATL_Msk (0x1UL << PWR_CSR1_VBATL_Pos) /*!< 0x00100000 */ +#define PWR_CSR1_VBATL PWR_CSR1_VBATL_Msk /*!< Monitored VBAT level above low threshold */ + +#define PWR_CSR1_VBATH_Pos (21U) +#define PWR_CSR1_VBATH_Msk (0x1UL << PWR_CSR1_VBATH_Pos) /*!< 0x00200000 */ +#define PWR_CSR1_VBATH PWR_CSR1_VBATH_Msk /*!< Monitored VBAT level above high threshold */ + +#define PWR_CSR1_TEMPL_Pos (22U) +#define PWR_CSR1_TEMPL_Msk (0x1UL << PWR_CSR1_TEMPL_Pos) /*!< 0x00400000 */ +#define PWR_CSR1_TEMPL PWR_CSR1_TEMPL_Msk /*!< Monitored temperature level above low threshold */ + +#define PWR_CSR1_TEMPH_Pos (23U) +#define PWR_CSR1_TEMPH_Msk (0x1UL << PWR_CSR1_TEMPH_Pos) /*!< 0x00800000 */ +#define PWR_CSR1_TEMPH PWR_CSR1_TEMPH_Msk /*!< Monitored temperature level above high threshold */ + +/******************** Bit definition for PWR_CSR2 register ********************/ +#define PWR_CSR2_BYPASS_Pos (0U) +#define PWR_CSR2_BYPASS_Msk (0x1UL << PWR_CSR2_BYPASS_Pos) /*!< 0x00000001 */ +#define PWR_CSR2_BYPASS PWR_CSR2_BYPASS_Msk /*!< Power Management Unit bypass */ + +#define PWR_CSR2_LDOEN_Pos (1U) +#define PWR_CSR2_LDOEN_Msk (0x1UL << PWR_CSR2_LDOEN_Pos) /*!< 0x00000002 */ +#define PWR_CSR2_LDOEN PWR_CSR2_LDOEN_Msk /*!< Low Drop-Out regulator enable */ + +#define PWR_CSR2_SDEN_Pos (2U) +#define PWR_CSR2_SDEN_Msk (0x1UL << PWR_CSR2_SDEN_Pos) /*!< 0x00000004 */ +#define PWR_CSR2_SDEN PWR_CSR2_SDEN_Msk /*!< SMPS Step-down converter enable */ + +#define PWR_CSR2_SMPSEXTHP_Pos (3U) +#define PWR_CSR2_SMPSEXTHP_Msk (0x1UL << PWR_CSR2_SMPSEXTHP_Pos) /*!< 0x00000008 */ +#define PWR_CSR2_SMPSEXTHP PWR_CSR2_SMPSEXTHP_Msk /*!< SMPS external power delivery selection */ + +#define PWR_CSR2_SDHILEVEL_Pos (4U) +#define PWR_CSR2_SDHILEVEL_Msk (0x1UL << PWR_CSR2_SDHILEVEL_Pos) /*!< 0x00000030 */ +#define PWR_CSR2_SDHILEVEL PWR_CSR2_SDHILEVEL_Msk /*!< SMPS step-down converter voltage output for LDO or external supply */ + +#define PWR_CSR2_VBE_Pos (8U) +#define PWR_CSR2_VBE_Msk (0x1UL << PWR_CSR2_VBE_Pos) /*!< 0x00000100 */ +#define PWR_CSR2_VBE PWR_CSR2_VBE_Msk /*!< VBAT charging enable */ + +#define PWR_CSR2_VBRS_Pos (9U) +#define PWR_CSR2_VBRS_Msk (0x1UL << PWR_CSR2_VBRS_Pos) /*!< 0x00000200 */ +#define PWR_CSR2_VBRS PWR_CSR2_VBRS_Msk /*!< VBAT charging resistor selection */ + +#define PWR_CSR2_XSPICAP1_Pos (10U) +#define PWR_CSR2_XSPICAP1_Msk (0x3UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000C00 */ +#define PWR_CSR2_XSPICAP1 PWR_CSR2_XSPICAP1_Msk /*!< XSPI port 1 capacitor control bits */ +#define PWR_CSR2_XSPICAP1_0 (0x1UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000400 */ +#define PWR_CSR2_XSPICAP1_1 (0x2UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000800 */ + +#define PWR_CSR2_XSPICAP2_Pos (12U) +#define PWR_CSR2_XSPICAP2_Msk (0x3UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00003000 */ +#define PWR_CSR2_XSPICAP2 PWR_CSR2_XSPICAP2_Msk /*!< XSPI port 2 capacitor control bits */ +#define PWR_CSR2_XSPICAP2_0 (0x1UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00001000 */ +#define PWR_CSR2_XSPICAP2_1 (0x2UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00002000 */ + +#define PWR_CSR2_EN_XSPIM1_Pos (14U) +#define PWR_CSR2_EN_XSPIM1_Msk (0x1UL << PWR_CSR2_EN_XSPIM1_Pos) /*!< 0x00004000 */ +#define PWR_CSR2_EN_XSPIM1 PWR_CSR2_EN_XSPIM1_Msk /*!< XSPIM1 external supply enable */ + +#define PWR_CSR2_EN_XSPIM2_Pos (15U) +#define PWR_CSR2_EN_XSPIM2_Msk (0x1UL << PWR_CSR2_EN_XSPIM2_Pos) /*!< 0x00008000 */ +#define PWR_CSR2_EN_XSPIM2 PWR_CSR2_EN_XSPIM2_Msk /*!< XSPIM2 external supply enable */ + +#define PWR_CSR2_SDEXTRDY_Pos (16U) +#define PWR_CSR2_SDEXTRDY_Msk (0x1UL << PWR_CSR2_SDEXTRDY_Pos) /*!< 0x00010000 */ +#define PWR_CSR2_SDEXTRDY PWR_CSR2_SDEXTRDY_Msk /*!< SMPS External supply ready */ + +#define PWR_CSR2_USB33DEN_Pos (24U) +#define PWR_CSR2_USB33DEN_Msk (0x1UL << PWR_CSR2_USB33DEN_Pos) /*!< 0x01000000 */ +#define PWR_CSR2_USB33DEN PWR_CSR2_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */ + +#define PWR_CSR2_USBREGEN_Pos (25U) +#define PWR_CSR2_USBREGEN_Msk (0x1UL << PWR_CSR2_USBREGEN_Pos) /*!< 0x02000000 */ +#define PWR_CSR2_USBREGEN PWR_CSR2_USBREGEN_Msk /*!< USB regulator enable */ + +#define PWR_CSR2_USB33RDY_Pos (26U) +#define PWR_CSR2_USB33RDY_Msk (0x1UL << PWR_CSR2_USB33RDY_Pos) /*!< 0x04000000 */ +#define PWR_CSR2_USB33RDY PWR_CSR2_USB33RDY_Msk /*!< USB supply ready */ + +#define PWR_CSR2_USBHSREGEN_Pos (27U) +#define PWR_CSR2_USBHSREGEN_Msk (0x1UL << PWR_CSR2_USBHSREGEN_Pos) /*!< 0x08000000 */ +#define PWR_CSR2_USBHSREGEN PWR_CSR2_USBHSREGEN_Msk /*!< USB HS regulator enable */ + +/******************** Bit definition for PWR_CSR3 register ********************/ +#define PWR_CSR3_PDDS_Pos (0U) +#define PWR_CSR3_PDDS_Msk (0x1UL << PWR_CSR3_PDDS_Pos) /*!< 0x00000001 */ +#define PWR_CSR3_PDDS PWR_CSR3_PDDS_Msk /*!< D1 domain Power Down Deepsleep */ + +#define PWR_CSR3_CSSF_Pos (1U) +#define PWR_CSR3_CSSF_Msk (0x1UL << PWR_CSR3_CSSF_Pos) /*!< 0x00000002 */ +#define PWR_CSR3_CSSF PWR_CSR3_CSSF_Msk /*!< Clear Standby and Stop flag */ + +#define PWR_CSR3_STOPF_Pos (8U) +#define PWR_CSR3_STOPF_Msk (0x1UL << PWR_CSR3_STOPF_Pos) /*!< 0x00000080 */ +#define PWR_CSR3_STOPF PWR_CSR3_STOPF_Msk /*!< STOP Flag */ + +#define PWR_CSR3_SBF_Pos (9U) +#define PWR_CSR3_SBF_Msk (0x1UL << PWR_CSR3_SBF_Pos) /*!< 0x00000100 */ +#define PWR_CSR3_SBF PWR_CSR3_SBF_Msk /*!< System STANDBY Flag */ + +/******************** Bit definition for PWR_CSR4 register ********************/ +#define PWR_CSR4_VOS_Pos (0U) +#define PWR_CSR4_VOS_Msk (0x1UL << PWR_CSR4_VOS_Pos) /*!< 0x00000001 */ +#define PWR_CSR4_VOS PWR_CSR4_VOS_Msk /*!< Voltage Scaling selection according performance */ + +#define PWR_CSR4_VOSRDY_Pos (1U) +#define PWR_CSR4_VOSRDY_Msk (0x1UL << PWR_CSR4_VOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_CSR4_VOSRDY PWR_CSR4_VOSRDY_Msk /*!< VOSRDY: VOS Ready bit for VCORE voltage scaling output selection. */ + +/******************** Bit definition for PWR_WKUPCR register ********************/ +#define PWR_WKUPCR_WKUPC_Pos (0U) +#define PWR_WKUPCR_WKUPC_Msk (0xFUL << PWR_WKUPCR_WKUPC_Pos) /*!< 0x0000000F */ +#define PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC_Msk /*!< Clear Wakeup Pin Flag 1 to 4 */ +#define PWR_WKUPCR_WKUPC1_Pos (0U) +#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */ +#define PWR_WKUPCR_WKUPC2_Pos (1U) +#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */ +#define PWR_WKUPCR_WKUPC3_Pos (2U) +#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */ +#define PWR_WKUPCR_WKUPC4_Pos (3U) +#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */ + +/******************** Bit definition for PWR_WKUPFR register ********************/ +#define PWR_WKUPFR_WKUPF1_Pos (0U) +#define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */ +#define PWR_WKUPFR_WKUPF2_Pos (1U) +#define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */ +#define PWR_WKUPFR_WKUPF3_Pos (2U) +#define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */ +#define PWR_WKUPFR_WKUPF4_Pos (3U) +#define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */ + +/******************** Bit definition for PWR_WKUPEPR register ********************/ +#define PWR_WKUPEPR_WKUPEN_Pos (0U) +#define PWR_WKUPEPR_WKUPEN_Msk (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000000F */ +#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */ +#define PWR_WKUPEPR_WKUPEN1_Pos (0U) +#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup Pin WKUP1 */ +#define PWR_WKUPEPR_WKUPEN2_Pos (1U) +#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup Pin WKUP2 */ +#define PWR_WKUPEPR_WKUPEN3_Pos (2U) +#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup Pin WKUP3 */ +#define PWR_WKUPEPR_WKUPEN4_Pos (3U) +#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup Pin WKUP4 */ + +#define PWR_WKUPEPR_WKUPP_Pos (8U) +#define PWR_WKUPEPR_WKUPP_Msk (0x0FUL << PWR_WKUPEPR_WKUPP_Pos) /*!< 0x0000F00 */ +#define PWR_WKUPEPR_WKUPP PWR_WKUPEPR_WKUPP_Msk /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */ +#define PWR_WKUPEPR_WKUPP1_Pos (8U) +#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Pin Polarity for WKUP1 */ +#define PWR_WKUPEPR_WKUPP2_Pos (9U) +#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Pin Polarity for WKUP2 */ +#define PWR_WKUPEPR_WKUPP3_Pos (10U) +#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Pin Polarity for WKUP3 */ +#define PWR_WKUPEPR_WKUPP4_Pos (11U) +#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Pin Polarity for WKUP4 */ + +#define PWR_WKUPEPR_WKUPPUPD1_Pos (16U) +#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */ +#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WKUPEPR_WKUPPUPD2_Pos (18U) +#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */ +#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WKUPEPR_WKUPPUPD3_Pos (20U) +#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */ +#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WKUPEPR_WKUPPUPD4_Pos (22U) +#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */ +#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for PWR_UCPDRR register ********************/ +#define PWR_UCPDR_UCPD_DBDIS_Pos (0U) +#define PWR_UCPDR_UCPD_DBDIS_Msk (0x1UL << PWR_UCPDR_UCPD_DBDIS_Pos) /*!< 0x00000001 */ +#define PWR_UCPDR_UCPD_DBDIS PWR_UCPDR_UCPD_DBDIS_Msk /*!< UCPD dead battery disable */ + +#define PWR_UCPDR_UCPD_STBY_Pos (1U) +#define PWR_UCPDR_UCPD_STBY_Msk (0x1UL << PWR_UCPDR_UCPD_STBY_Pos) /*!< 0x00000002 */ +#define PWR_UCPDR_UCPD_STBY PWR_UCPDR_UCPD_STBY_Msk /*!< UCPD Standby mode */ + +/******************** Bit definition for PWR_APCR register ********************/ +#define PWR_APCR_APC_Pos (0U) +#define PWR_APCR_APC_Msk (0x1UL << PWR_APCR_APC_Pos) /*!< 0x00000001 */ +#define PWR_APCR_APC PWR_APCR_APC_Msk /*!< Apply pull configuration register */ + +#define PWR_APCR_PN7_PUPD_Pos (16U) +#define PWR_APCR_PN7_PUPD_Msk (0x1UL << PWR_APCR_PN7_PUPD_Pos) /*!< 0x00010000 */ +#define PWR_APCR_PN7_PUPD PWR_APCR_PN7_PUPD_Msk /*!< Port N bit 7 pull-up/down configuration */ + +#define PWR_APCR_PO5_PUPD_Pos (17) +#define PWR_APCR_PO5_PUPD_Msk (0x1UL << PWR_APCR_PO5_PUPD_Pos) /*!< 0x00020000 */ +#define PWR_APCR_PO5_PUPD PWR_APCR_PO5_PUPD_Msk /*!< Port O bit 5 pull-up/down configuration */ + +#define PWR_APCR_I3CPB6_PU_Pos (28U) +#define PWR_APCR_I3CPB6_PU_Msk (0x1UL << PWR_APCR_I3CPB6_PU_Pos) /*!< 0x10000000 */ +#define PWR_APCR_I3CPB6_PU PWR_APCR_I3CPB6_PU_Msk /*!< Port PB6 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB7_PU_Pos (29U) +#define PWR_APCR_I3CPB7_PU_Msk (0x1UL << PWR_APCR_I3CPB7_PU_Pos) /*!< 0x20000000 */ +#define PWR_APCR_I3CPB7_PU PWR_APCR_I3CPB7_PU_Msk /*!< Port PB7 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB8_PU_Pos (30U) +#define PWR_APCR_I3CPB8_PU_Msk (0x1UL << PWR_APCR_I3CPB8_PU_Pos) /*!< 0x40000000 */ +#define PWR_APCR_I3CPB8_PU PWR_APCR_I3CPB8_PU_Msk /*!< Port PB8 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB9_PU_Pos (31U) +#define PWR_APCR_I3CPB9_PU_Msk (0x1UL << PWR_APCR_I3CPB9_PU_Pos) /*!< 0x80000000 */ +#define PWR_APCR_I3CPB9_PU PWR_APCR_I3CPB9_PU_Msk /*!< Port PB9 I3C pull-up bit configuration */ + +/******************** Bit definition for PWR_PUCRN register ********************/ +#define PWR_PUCRN_PUN1_Pos (1U) +#define PWR_PUCRN_PUN1_Msk (0x1UL << PWR_PUCRN_PUN1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRN_PUN1 PWR_PUCRN_PUN1_Msk /*!< PUN1: Port N pull-up */ + +#define PWR_PUCRN_PUN6_Pos (6U) +#define PWR_PUCRN_PUN6_Msk (0x1UL << PWR_PUCRN_PUN6_Pos) /*!< 0x00000040 */ +#define PWR_PUCRN_PUN6 PWR_PUCRN_PUN6_Msk /*!< PUN6: Port N pull-up */ + +#define PWR_PUCRN_PUN12_Pos (12U) +#define PWR_PUCRN_PUN12_Msk (0x1UL << PWR_PUCRN_PUN12_Pos) /*!< 0x00001000 */ +#define PWR_PUCRN_PUN12 PWR_PUCRN_PUN12_Msk /*!< PUN12: Port N pull-up */ + +/******************** Bit definition for PWR_PDCRN register ********************/ +#define PWR_PDCRN_PDN0_Pos (0U) +#define PWR_PDCRN_PDN0_Msk (0x1UL << PWR_PDCRN_PDN0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRN_PDN0 PWR_PDCRN_PDN0_Msk /*!< PDN0: Port N pull-down */ + +#define PWR_PDCRN_PDN1_Pos (1U) +#define PWR_PDCRN_PDN1_Msk (0x1UL << PWR_PDCRN_PDN1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRN_PDN1 PWR_PDCRN_PDN1_Msk /*!< PDN1: Port N pull-down */ + +#define PWR_PDCRN_PDN2N5_Pos (2U) +#define PWR_PDCRN_PDN2N5_Msk (0x1UL << PWR_PDCRN_PDN2N5_Pos) /*!< 0x00000004 */ +#define PWR_PDCRN_PDN2N5 PWR_PDCRN_PDN2N5_Msk /*!< PDN2 to PDN5: Port N pull-down */ + +#define PWR_PDCRN_PDN6_Pos (6U) +#define PWR_PDCRN_PDN6_Msk (0x1UL << PWR_PDCRN_PDN6_Pos) /*!< 0x00000040 */ +#define PWR_PDCRN_PDN6 PWR_PDCRN_PDN6_Msk /*!< PDN6: Port N pull-down */ + +#define PWR_PDCRN_PDN8N11_Pos (8U) +#define PWR_PDCRN_PDN8N11_Msk (0x1UL << PWR_PDCRN_PDN8N11_Pos) /*!< 0x00000100 */ +#define PWR_PDCRN_PDN8N11 PWR_PDCRN_PDN8N11_Msk /*!< PDN8 to PDN11: Port N pull-down */ + +#define PWR_PDCRN_PDN12_Pos (12U) +#define PWR_PDCRN_PDN12_Msk (0x1UL << PWR_PDCRN_PDN12_Pos) /*!< 0x00001000 */ +#define PWR_PDCRN_PDN12 PWR_PDCRN_PDN12_Msk /*!< PDN12: Port N pull-down */ + +/******************** Bit definition for PWR_PUCRO register ********************/ +#define PWR_PUCRO_PUO0_Pos (0U) +#define PWR_PUCRO_PUO0_Msk (0x1UL << PWR_PUCRO_PUO0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRO_PUO0 PWR_PUCRO_PUO0_Msk /*!< PUO0: Port O pull-up */ + +#define PWR_PUCRO_PUO1_Pos (1U) +#define PWR_PUCRO_PUO1_Msk (0x1UL << PWR_PUCRO_PUO1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRO_PUO1 PWR_PUCRO_PUO1_Msk /*!< PUO1: Port O pull-up */ + +#define PWR_PUCRO_PUO4_Pos (4U) +#define PWR_PUCRO_PUO4_Msk (0x1UL << PWR_PUCRO_PUO4_Pos) /*!< 0x00000010 */ +#define PWR_PUCRO_PUO4 PWR_PUCRO_PUO4_Msk /*!< PUO4: Port O pull-up */ + +/******************** Bit definition for PWR_PDCRO register ********************/ +#define PWR_PDCRO_PDO0_Pos (0U) +#define PWR_PDCRO_PDO0_Msk (0x1UL << PWR_PDCRO_PDO0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRO_PDO0 PWR_PDCRO_PDO0_Msk /*!< PDO0: Port O pull-down */ + +#define PWR_PDCRO_PDO1_Pos (1U) +#define PWR_PDCRO_PDO1_Msk (0x1UL << PWR_PDCRO_PDO1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRO_PDO1 PWR_PDCRO_PDO1_Msk /*!< PDO1: Port O pull-down */ + +#define PWR_PDCRO_PDO2_Pos (2U) +#define PWR_PDCRO_PDO2_Msk (0x1UL << PWR_PDCRO_PDO2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRO_PDO2 PWR_PDCRO_PDO2_Msk /*!< PDO2: Port O pull-down */ + +#define PWR_PDCRO_PDO3_Pos (3U) +#define PWR_PDCRO_PDO3_Msk (0x1UL << PWR_PDCRO_PDO3_Pos) /*!< 0x00000008 */ +#define PWR_PDCRO_PDO3 PWR_PDCRO_PDO3_Msk /*!< PDO3: Port O pull-down */ + +#define PWR_PDCRO_PDO4_Pos (4U) +#define PWR_PDCRO_PDO4_Msk (0x1UL << PWR_PDCRO_PDO4_Pos) /*!< 0x00000010 */ +#define PWR_PDCRO_PDO4 PWR_PDCRO_PDO4_Msk /*!< PDO4: Port O pull-down */ + +/******************** Bit definition for PWR_PDCRP register ********************/ +#define PWR_PDCRP_PDP0P3_Pos (0U) +#define PWR_PDCRP_PDP0P3_Msk (0x1UL << PWR_PDCRP_PDP0P3_Pos) /*!< 0x00000001 */ +#define PWR_PDCRP_PDP0P3 PWR_PDCRP_PDP0P3_Msk /*!< PPO0 to PP03 : Port P pull-down */ + +#define PWR_PDCRP_PDP4P7_Pos (4U) +#define PWR_PDCRP_PDP4P7_Msk (0x1UL << PWR_PDCRP_PDP4P7_Pos) /*!< 0x00000010 */ +#define PWR_PDCRP_PDP4P7 PWR_PDCRP_PDP4P7_Msk /*!< PPO4 to PP07 : Port P pull-down */ + +#define PWR_PDCRP_PDP8P11_Pos (8U) +#define PWR_PDCRP_PDP8P11_Msk (0x1UL << PWR_PDCRP_PDP8P11_Pos) /*!< 0x00000100 */ +#define PWR_PDCRP_PDP8P11 PWR_PDCRP_PDP8P11_Msk /*!< PPO8 to PP11 : Port P pull-down */ + +#define PWR_PDCRP_PDP12P15_Pos (12U) +#define PWR_PDCRP_PDP12P15_Msk (0x1UL << PWR_PDCRP_PDP12P15_Pos) /*!< 0x00001000 */ +#define PWR_PDCRP_PDP12P15 PWR_PDCRP_PDP12P15_Msk /*!< PP12 to PP15 : Port P pull-down */ + + +/******************************************************************************/ +/* */ +/* RAM ECC monitoring */ +/* */ +/******************************************************************************/ +/****************** Bit definition for RAMECC_IER register ******************/ +#define RAMECC_IER_GIE_Pos (0U) +#define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) /*!< 0x00000001 */ +#define RAMECC_IER_GIE RAMECC_IER_GIE_Msk /*!< Global interrupt enable */ +#define RAMECC_IER_GECCSEIE_Pos (1U) +#define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) /*!< 0x00000002 */ +#define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk /*!< Global ECC single error interrupt enable */ +#define RAMECC_IER_GECCDEIE_Pos (2U) +#define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) /*!< 0x00000004 */ +#define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk /*!< Global ECC double error interrupt enable */ +#define RAMECC_IER_GECCDEBWIE_Pos (3U) +#define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) /*!< 0x00000008 */ +#define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk /*!< Global ECC double error on byte write (BW) interrupt enable */ + +/******************* Bit definition for RAMECC_CR register ******************/ +#define RAMECC_CR_ECCSEIE_Pos (2U) +#define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) /*!< 0x00000004 */ +#define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk /*!< ECC single error interrupt enable */ +#define RAMECC_CR_ECCDEIE_Pos (3U) +#define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) /*!< 0x00000008 */ +#define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk /*!< ECC double error interrupt enable */ +#define RAMECC_CR_ECCDEBWIE_Pos (4U) +#define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) /*!< 0x00000010 */ +#define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk /*!< ECC double error on byte write (BW) interrupt enable */ +#define RAMECC_CR_ECCELEN_Pos (5U) +#define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) /*!< 0x00000020 */ +#define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk /*!< ECC error latching enable */ + +/******************* Bit definition for RAMECC_SR register ******************/ +#define RAMECC_SR_SEDCF_Pos (0U) +#define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) /*!< 0x00000001 */ +#define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk /*!< ECC single error detected and corrected flag */ +#define RAMECC_SR_DEDF_Pos (1U) +#define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) /*!< 0x00000002 */ +#define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk /*!< ECC double error detected flag */ +#define RAMECC_SR_DEBWDF_Pos (2U) +#define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) /*!< 0x00000004 */ +#define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk /*!< ECC double error on byte write (BW) detected flag */ + +/****************** Bit definition for RAMECC_FAR register ******************/ +#define RAMECC_FAR_FADD_Pos (0U) +#define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk /*!< ECC error failing address */ + +/****************** Bit definition for RAMECC_FDRL register *****************/ +#define RAMECC_FDRL_FDATAL_Pos (0U) +#define RAMECC_FDRL_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FDRL_FDATAL_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FDRL_FDATAL RAMECC_FDRL_FDATAL_Msk /*!< Failing data low */ + +/****************** Bit definition for RAMECC_FDRH register *****************/ +#define RAMECC_FDRH_FDATAH_Pos (0U) +#define RAMECC_FDRH_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FDRH_FDATAH_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FDRH_FDATAH RAMECC_FDRH_FDATAH_Msk /* Failing data high (64-bit memory) */ + +/***************** Bit definition for RAMECC_FECR register ******************/ +#define RAMECC_FECR_FEC_Pos (0U) +#define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk /*!< Failing error code */ + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIKERON_Pos (1U) +#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable in Stop mode */ +#define RCC_CR_HSIRDY_Pos (2U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIV_Pos (3U) +#define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */ +#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< Internal High Speed clock divider selection */ +#define RCC_CR_HSIDIV_0 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSIDIV_1 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000010 */ + +#define RCC_CR_HSIDIVF_Pos (5U) +#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000020 */ +#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< HSI Divider flag */ +#define RCC_CR_CSION_Pos (7U) +#define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) /*!< 0x00000080 */ +#define RCC_CR_CSION RCC_CR_CSION_Msk /*!< The Internal RC 4MHz oscillator clock enable */ +#define RCC_CR_CSIRDY_Pos (8U) +#define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) /*!< 0x00000100 */ +#define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk /*!< The Internal RC 4MHz oscillator clock ready */ +#define RCC_CR_CSIKERON_Pos (9U) +#define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) /*!< 0x00000200 */ +#define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk /*!< Internal RC 4MHz oscillator clock enable in Stop mode */ +#define RCC_CR_HSI48ON_Pos (12U) +#define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) /*!< 0x00001000 */ +#define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk /*!< HSI48 clock enable clock enable */ +#define RCC_CR_HSI48RDY_Pos (13U) +#define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) /*!< 0x00002000 */ +#define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk /*!< HSI48 clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock bypass */ +#define RCC_CR_HSEEXT_Pos (19U) +#define RCC_CR_HSEEXT_Msk (0x1UL << RCC_CR_HSEEXT_Pos) /*!< 0x00100000 */ +#define RCC_CR_HSEEXT RCC_CR_HSEEXT_Msk /*!< External High Speed clock type in bypass mode */ +#define RCC_CR_HSECSSON_Pos (20U) +#define RCC_CR_HSECSSON_Msk (0x1UL << RCC_CR_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSECSSON RCC_CR_HSECSSON_Msk /*!< HSE Clock security System enable */ +#define RCC_CR_PLL1ON_Pos (24U) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */ +#define RCC_CR_PLL1RDY_Pos (25U) +#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready flag */ +#define RCC_CR_PLL2ON_Pos (26U) +#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */ +#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< System PLL2 clock enable */ +#define RCC_CR_PLL2RDY_Pos (27U) +#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */ +#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< System PLL2 clock ready flag */ +#define RCC_CR_PLL3ON_Pos (28U) +#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */ +#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< System PLL3 clock enable */ +#define RCC_CR_PLL3RDY_Pos (29U) +#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */ +#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< System PLL3 clock ready flag */ + +/******************** Bit definition for RCC_HSICFGR register ***************/ +/*!< HSICAL configuration */ +#define RCC_HSICFGR_HSICAL_Pos (0U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSICAL[11:0] bits */ +#define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */ +#define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */ +#define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */ +#define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */ +#define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */ +#define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */ +#define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */ + +/*!< HSITRIM configuration */ +#define RCC_HSICFGR_HSITRIM_Pos (24U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ +#define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CRRCR register *****************/ +/*!< HSI48CAL configuration */ +#define RCC_CRRCR_HSI48CAL_Pos (0U) +#define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */ +#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[9:0] bits */ +#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */ +#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */ +#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */ +#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */ +#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */ +#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */ +#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */ +#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */ +#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */ +#define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */ + +/******************** Bit definition for RCC_CSICFGR register ***************/ +/*!< CSICAL configuration */ +#define RCC_CSICFGR_CSICAL_Pos (0U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSICAL[7:0] bits */ +#define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */ +#define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */ +#define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */ +#define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */ +#define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */ +#define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */ +#define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */ +#define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */ + +/*!< CSITRIM configuration */ +#define RCC_CSICFGR_CSITRIM_Pos (24U) +#define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSITRIM[5:0] bits */ +#define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */ +#define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */ +#define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */ +#define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for RCC_CFGR register ******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock switch) */ +#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_Pos (3U) +#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System clock switch status) */ +#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ + +#define RCC_CFGR_STOPWUCK_Pos (6U) +#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */ +#define RCC_CFGR_STOPKERWUCK_Pos (7U) +#define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) /*!< 0x00000080 */ +#define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk /*!< Kernel Clock Selection after a Wake Up from Stop */ + +/*!< RTCPRE configuration */ +#define RCC_CFGR_RTCPRE_Pos (8U) +#define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00003F00 */ +#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk /*!< RTCPRE[5:0] bits (HSE division factor for RTC clock) */ +#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00002000 */ + +#define RCC_CFGR_TIMPRE_Pos (15U) +#define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos) /*!< 0x00008000 */ +#define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk /*!< TIMPRE configuration */ + +#define RCC_CFGR_MCO1PRE_Pos (18U) +#define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk /*!< MCO1 configuration */ +#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00200000 */ + +#define RCC_CFGR_MCO1SEL_Pos (22U) +#define RCC_CFGR_MCO1SEL_Msk (0x7UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x01C00000 */ +#define RCC_CFGR_MCO1SEL RCC_CFGR_MCO1SEL_Msk /*!< MCO1SEL [2:0] bits (MCO1 clock output selection) */ +#define RCC_CFGR_MCO1SEL_0 (0x1UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_MCO1SEL_1 (0x2UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x00800000 */ +#define RCC_CFGR_MCO1SEL_2 (0x4UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x01000000 */ + +#define RCC_CFGR_MCO2PRE_Pos (25U) +#define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x1E000000 */ +#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< MCO2 configuration */ +#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */ + +#define RCC_CFGR_MCO2SEL_Pos (29U) +#define RCC_CFGR_MCO2SEL_Msk (0x7UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0xE0000000 */ +#define RCC_CFGR_MCO2SEL RCC_CFGR_MCO2SEL_Msk /*!< MCO2SEL [2:0] bits (MCO2 clock output selection) */ +#define RCC_CFGR_MCO2SEL_0 (0x1UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x20000000 */ +#define RCC_CFGR_MCO2SEL_1 (0x2UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x40000000 */ +#define RCC_CFGR_MCO2SEL_2 (0x4UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for RCC_CDCFGR register ****************/ +/*!< CPRE configuration */ +#define RCC_CDCFGR_CPRE_Pos (0U) +#define RCC_CDCFGR_CPRE_Msk (0xFUL << RCC_CDCFGR_CPRE_Pos) /*!< 0x0000000F */ +#define RCC_CDCFGR_CPRE RCC_CDCFGR_CPRE_Msk /*!< CPRE[3:0] bits */ +#define RCC_CDCFGR_CPRE_0 (0x1UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000001 */ +#define RCC_CDCFGR_CPRE_1 (0x2UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000002 */ +#define RCC_CDCFGR_CPRE_2 (0x4UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000004 */ +#define RCC_CDCFGR_CPRE_3 (0x8UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for RCC_BMCFGR register ****************/ +/*!< BMPRE configuration */ +#define RCC_BMCFGR_BMPRE_Pos (0U) +#define RCC_BMCFGR_BMPRE_Msk (0xFUL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x0000000F */ +#define RCC_BMCFGR_BMPRE RCC_BMCFGR_BMPRE_Msk /*!< BMPRE[3:0] bits */ +#define RCC_BMCFGR_BMPRE_0 (0x1UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000001 */ +#define RCC_BMCFGR_BMPRE_1 (0x2UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000002 */ +#define RCC_BMCFGR_BMPRE_2 (0x4UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000004 */ +#define RCC_BMCFGR_BMPRE_3 (0x8UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for RCC_APBCFGR register ***************/ +/*!< APB1 prescaler configuration */ +#define RCC_APBCFGR_PPRE1_Pos (0U) +#define RCC_APBCFGR_PPRE1_Msk (0x7UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000007 */ +#define RCC_APBCFGR_PPRE1 RCC_APBCFGR_PPRE1_Msk /*!< PPRE1[2:0] bits */ +#define RCC_APBCFGR_PPRE1_0 (0x1UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000001 */ +#define RCC_APBCFGR_PPRE1_1 (0x2UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000002 */ +#define RCC_APBCFGR_PPRE1_2 (0x4UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000004 */ + +/*!< APB2 prescaler configuration */ +#define RCC_APBCFGR_PPRE2_Pos (4U) +#define RCC_APBCFGR_PPRE2_Msk (0x7UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000070 */ +#define RCC_APBCFGR_PPRE2 RCC_APBCFGR_PPRE2_Msk /*!< PPRE2[2:0] bits */ +#define RCC_APBCFGR_PPRE2_0 (0x1UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000010 */ +#define RCC_APBCFGR_PPRE2_1 (0x2UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000020 */ +#define RCC_APBCFGR_PPRE2_2 (0x4UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000040 */ + +/*!< APB4 prescaler configuration */ +#define RCC_APBCFGR_PPRE4_Pos (8U) +#define RCC_APBCFGR_PPRE4_Msk (0x7UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000700 */ +#define RCC_APBCFGR_PPRE4 RCC_APBCFGR_PPRE4_Msk /*!< PPRE4[2:0] bits */ +#define RCC_APBCFGR_PPRE4_0 (0x1UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000100 */ +#define RCC_APBCFGR_PPRE4_1 (0x2UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000200 */ +#define RCC_APBCFGR_PPRE4_2 (0x4UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000400 */ + +/*!< APB5 prescaler configuration */ +#define RCC_APBCFGR_PPRE5_Pos (12U) +#define RCC_APBCFGR_PPRE5_Msk (0x7UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00007000 */ +#define RCC_APBCFGR_PPRE5 RCC_APBCFGR_PPRE5_Msk /*!< PPRE5[2:0] bits */ +#define RCC_APBCFGR_PPRE5_0 (0x1UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00001000 */ +#define RCC_APBCFGR_PPRE5_1 (0x2UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00002000 */ +#define RCC_APBCFGR_PPRE5_2 (0x4UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_PLLCKSELR register *************/ +#define RCC_PLLCKSELR_PLLSRC_Pos (0U) +#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ +#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk /*!< DIVMx and PLLs clock source selection */ +#define RCC_PLLCKSELR_PLLSRC_0 (0x01UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000010 */ +#define RCC_PLLCKSELR_PLLSRC_1 (0x02UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000020 */ + +#define RCC_PLLCKSELR_DIVM1_Pos (4U) +#define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */ +#define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk /*!< DIVM1[5:0] bits */ +#define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */ +#define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */ +#define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */ +#define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */ +#define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */ +#define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */ + +#define RCC_PLLCKSELR_DIVM2_Pos (12U) +#define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */ +#define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk /*!< DIVM2[5:0] bits */ +#define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */ +#define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */ +#define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */ +#define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */ +#define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */ + +#define RCC_PLLCKSELR_DIVM3_Pos (20U) +#define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */ +#define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk /*!< DIVM3[5:0] bits */ +#define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */ +#define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */ +#define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */ +#define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for RCC_PLLCFGR register ***************/ +#define RCC_PLLCFGR_PLL1FRACEN_Pos (0U) +#define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */ +#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk /*!< PLL1 fractional latch enable */ +#define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U) +#define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */ +#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk /*!< PLL1 VCO selection */ +#define RCC_PLLCFGR_PLL1SSCGEN_Pos (2U) +#define RCC_PLLCFGR_PLL1SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL1SSCGEN_Pos) /*!< 0x00000004 */ +#define RCC_PLLCFGR_PLL1SSCGEN RCC_PLLCFGR_PLL1SSCGEN_Msk /*!< PLL1 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL1RGE_Pos (3U) +#define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000018 */ +#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk /*!< PLL1RGE[1:0] bits: PLL1 input frequency range */ +#define RCC_PLLCFGR_PLL1RGE_0 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */ +#define RCC_PLLCFGR_PLL1RGE_1 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000010 */ + +#define RCC_PLLCFGR_PLL1PEN_Pos (5U) +#define RCC_PLLCFGR_PLL1PEN_Msk (0x1UL << RCC_PLLCFGR_PLL1PEN_Pos) /*!< 0x00000020 */ +#define RCC_PLLCFGR_PLL1PEN RCC_PLLCFGR_PLL1PEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL1QEN_Pos (6U) +#define RCC_PLLCFGR_PLL1QEN_Msk (0x1UL << RCC_PLLCFGR_PLL1QEN_Pos) /*!< 0x00000040 */ +#define RCC_PLLCFGR_PLL1QEN RCC_PLLCFGR_PLL1QEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL1REN_Pos (7U) +#define RCC_PLLCFGR_PLL1REN_Msk (0x1UL << RCC_PLLCFGR_PLL1REN_Pos) /*!< 0x00000080 */ +#define RCC_PLLCFGR_PLL1REN RCC_PLLCFGR_PLL1REN_Msk /*!< PLL1 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL1SEN_Pos (8U) +#define RCC_PLLCFGR_PLL1SEN_Msk (0x1UL << RCC_PLLCFGR_PLL1SEN_Pos) /*!< 0x00000100 */ +#define RCC_PLLCFGR_PLL1SEN RCC_PLLCFGR_PLL1SEN_Msk /*!< PLL1 DIVS divider output enable */ + +#define RCC_PLLCFGR_PLL2FRACEN_Pos (11U) +#define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000800 */ +#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk /*!< PLL2 fractional latch enable */ +#define RCC_PLLCFGR_PLL2VCOSEL_Pos (12U) +#define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00001000 */ +#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk /*!< PLL2 VCO selection */ +#define RCC_PLLCFGR_PLL2SSCGEN_Pos (13U) +#define RCC_PLLCFGR_PLL2SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL2SSCGEN_Pos) /*!< 0x00002000 */ +#define RCC_PLLCFGR_PLL2SSCGEN RCC_PLLCFGR_PLL2SSCGEN_Msk /*!< PLL2 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL2RGE_Pos (14U) +#define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x0000C000 */ +#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk /*!< PLL2RGE[1:0] bits: PLL2 input frequency range */ +#define RCC_PLLCFGR_PLL2RGE_0 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00004000 */ +#define RCC_PLLCFGR_PLL2RGE_1 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00008000 */ + +#define RCC_PLLCFGR_PLL2PEN_Pos (16U) +#define RCC_PLLCFGR_PLL2PEN_Msk (0x1UL << RCC_PLLCFGR_PLL2PEN_Pos) /*!< 0x00010000 */ +#define RCC_PLLCFGR_PLL2PEN RCC_PLLCFGR_PLL2PEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL2QEN_Pos (17U) +#define RCC_PLLCFGR_PLL2QEN_Msk (0x1UL << RCC_PLLCFGR_PLL2QEN_Pos) /*!< 0x00020000 */ +#define RCC_PLLCFGR_PLL2QEN RCC_PLLCFGR_PLL2QEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL2REN_Pos (18U) +#define RCC_PLLCFGR_PLL2REN_Msk (0x1UL << RCC_PLLCFGR_PLL2REN_Pos) /*!< 0x00040000 */ +#define RCC_PLLCFGR_PLL2REN RCC_PLLCFGR_PLL2REN_Msk /*!< PLL2 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL2SEN_Pos (19U) +#define RCC_PLLCFGR_PLL2SEN_Msk (0x1UL << RCC_PLLCFGR_PLL2SEN_Pos) /*!< 0x00080000 */ +#define RCC_PLLCFGR_PLL2SEN RCC_PLLCFGR_PLL2SEN_Msk /*!< PLL2 DIVS divider output enable */ +#define RCC_PLLCFGR_PLL2TEN_Pos (20U) +#define RCC_PLLCFGR_PLL2TEN_Msk (0x1UL << RCC_PLLCFGR_PLL2TEN_Pos) /*!< 0x00100000 */ +#define RCC_PLLCFGR_PLL2TEN RCC_PLLCFGR_PLL2TEN_Msk /*!< PLL2 DIVT divider output enable */ + +#define RCC_PLLCFGR_PLL3FRACEN_Pos (22U) +#define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00400000 */ +#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk /*!< PLL3 fractional latch enable */ +#define RCC_PLLCFGR_PLL3VCOSEL_Pos (23U) +#define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00800000 */ +#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk /*!< PLL3 VCO selection */ +#define RCC_PLLCFGR_PLL3SSCGEN_Pos (24U) +#define RCC_PLLCFGR_PLL3SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL3SSCGEN_Pos) /*!< 0x01000000 */ +#define RCC_PLLCFGR_PLL3SSCGEN RCC_PLLCFGR_PLL3SSCGEN_Msk /*!< PLL3 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL3RGE_Pos (25U) +#define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x06000000 */ +#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk /*!< PLL3RGE[1:0] bits: PLL3 input frequency range */ +#define RCC_PLLCFGR_PLL3RGE_0 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x02000000 */ +#define RCC_PLLCFGR_PLL3RGE_1 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x04000000 */ + +#define RCC_PLLCFGR_PLL3PEN_Pos (27U) +#define RCC_PLLCFGR_PLL3PEN_Msk (0x1UL << RCC_PLLCFGR_PLL3PEN_Pos) /*!< 0x08000000 */ +#define RCC_PLLCFGR_PLL3PEN RCC_PLLCFGR_PLL3PEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL3QEN_Pos (28U) +#define RCC_PLLCFGR_PLL3QEN_Msk (0x1UL << RCC_PLLCFGR_PLL3QEN_Pos) /*!< 0x10000000 */ +#define RCC_PLLCFGR_PLL3QEN RCC_PLLCFGR_PLL3QEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL3REN_Pos (29U) +#define RCC_PLLCFGR_PLL3REN_Msk (0x1UL << RCC_PLLCFGR_PLL3REN_Pos) /*!< 0x20000000 */ +#define RCC_PLLCFGR_PLL3REN RCC_PLLCFGR_PLL3REN_Msk /*!< PLL3 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL3SEN_Pos (30U) +#define RCC_PLLCFGR_PLL3SEN_Msk (0x1UL << RCC_PLLCFGR_PLL3SEN_Pos) /*!< 0x40000000 */ +#define RCC_PLLCFGR_PLL3SEN RCC_PLLCFGR_PLL3SEN_Msk /*!< PLL3 DIVS divider output enable */ + +/******************** Bit definition for RCC_PLL1DIVR1 register *************/ +#define RCC_PLL1DIVR1_DIVN_Pos (0U) +#define RCC_PLL1DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1DIVR1_DIVN RCC_PLL1DIVR1_DIVN_Msk /*!< DIVN1[8:0] bits: PLL1 DIVN division factor */ +#define RCC_PLL1DIVR1_DIVN_0 (0x001UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR1_DIVN_1 (0x002UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR1_DIVN_2 (0x004UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1DIVR1_DIVN_3 (0x008UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1DIVR1_DIVN_4 (0x010UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1DIVR1_DIVN_5 (0x020UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1DIVR1_DIVN_6 (0x040UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1DIVR1_DIVN_7 (0x080UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1DIVR1_DIVN_8 (0x100UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL1DIVR1_DIVP_Pos (9U) +#define RCC_PLL1DIVR1_DIVP_Msk (0x7FUL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL1DIVR1_DIVP RCC_PLL1DIVR1_DIVP_Msk /*!< DIVP1[6:0] bits: PLL1 DIVP division factor */ +#define RCC_PLL1DIVR1_DIVP_0 (0x001UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL1DIVR1_DIVP_1 (0x002UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL1DIVR1_DIVP_2 (0x004UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL1DIVR1_DIVP_3 (0x008UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL1DIVR1_DIVP_4 (0x010UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL1DIVR1_DIVP_5 (0x020UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL1DIVR1_DIVP_6 (0x040UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL1DIVR1_DIVQ_Pos (16U) +#define RCC_PLL1DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1DIVR1_DIVQ RCC_PLL1DIVR1_DIVQ_Msk /*!< DIVQ1[6:0] bits: PLL1 DIVQ division factor */ +#define RCC_PLL1DIVR1_DIVQ_0 (0x001UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL1DIVR1_DIVQ_1 (0x002UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL1DIVR1_DIVQ_2 (0x004UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL1DIVR1_DIVQ_3 (0x008UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL1DIVR1_DIVQ_4 (0x010UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL1DIVR1_DIVQ_5 (0x020UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL1DIVR1_DIVQ_6 (0x040UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL1DIVR1_DIVR_Pos (24U) +#define RCC_PLL1DIVR1_DIVR_Msk (0x7FUL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL1DIVR1_DIVR RCC_PLL1DIVR1_DIVR_Msk /*!< DIVR1[6:0] bits: PLL1 DIVR division factor */ +#define RCC_PLL1DIVR1_DIVR_0 (0x001UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL1DIVR1_DIVR_1 (0x002UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL1DIVR1_DIVR_2 (0x004UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL1DIVR1_DIVR_3 (0x008UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL1DIVR1_DIVR_4 (0x010UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL1DIVR1_DIVR_5 (0x020UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL1DIVR1_DIVR_6 (0x040UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL1FRACR register *************/ +#define RCC_PLL1FRACR_FRACN_Pos (3U) +#define RCC_PLL1FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACN RCC_PLL1FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_PLL2DIVR1 register *************/ +#define RCC_PLL2DIVR1_DIVN_Pos (0U) +#define RCC_PLL2DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2DIVR1_DIVN RCC_PLL2DIVR1_DIVN_Msk /*!< DIVN2[8:0] bits: PLL2 DIVN division factor */ +#define RCC_PLL2DIVR1_DIVN_0 (0x001UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2DIVR1_DIVN_1 (0x002UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2DIVR1_DIVN_2 (0x004UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2DIVR1_DIVN_3 (0x008UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2DIVR1_DIVN_4 (0x010UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2DIVR1_DIVN_5 (0x020UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2DIVR1_DIVN_6 (0x040UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2DIVR1_DIVN_7 (0x080UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2DIVR1_DIVN_8 (0x100UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL2DIVR1_DIVP_Pos (9U) +#define RCC_PLL2DIVR1_DIVP_Msk (0x7FUL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL2DIVR1_DIVP RCC_PLL2DIVR1_DIVP_Msk /*!< DIVP2[6:0] bits: PLL2 DIVP division factor */ +#define RCC_PLL2DIVR1_DIVP_0 (0x001UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL2DIVR1_DIVP_1 (0x002UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL2DIVR1_DIVP_2 (0x004UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL2DIVR1_DIVP_3 (0x008UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL2DIVR1_DIVP_4 (0x010UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL2DIVR1_DIVP_5 (0x020UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL2DIVR1_DIVP_6 (0x040UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL2DIVR1_DIVQ_Pos (16U) +#define RCC_PLL2DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2DIVR1_DIVQ RCC_PLL2DIVR1_DIVQ_Msk /*!< DIVQ2[6:0] bits: PLL2 DIVQ division factor */ +#define RCC_PLL2DIVR1_DIVQ_0 (0x001UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL2DIVR1_DIVQ_1 (0x002UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL2DIVR1_DIVQ_2 (0x004UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL2DIVR1_DIVQ_3 (0x008UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL2DIVR1_DIVQ_4 (0x010UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL2DIVR1_DIVQ_5 (0x020UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL2DIVR1_DIVQ_6 (0x040UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL2DIVR1_DIVR_Pos (24U) +#define RCC_PLL2DIVR1_DIVR_Msk (0x7FUL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL2DIVR1_DIVR RCC_PLL2DIVR1_DIVR_Msk /*!< DIVR2[6:0] bits: PLL2 DIVR division factor */ +#define RCC_PLL2DIVR1_DIVR_0 (0x001UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL2DIVR1_DIVR_1 (0x002UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL2DIVR1_DIVR_2 (0x004UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL2DIVR1_DIVR_3 (0x008UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL2DIVR1_DIVR_4 (0x010UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL2DIVR1_DIVR_5 (0x020UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL2DIVR1_DIVR_6 (0x040UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL2FRACR register *************/ +#define RCC_PLL2FRACR_FRACN_Pos (3U) +#define RCC_PLL2FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACN RCC_PLL2FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_PLL3DIVR1 register *************/ +#define RCC_PLL3DIVR1_DIVN_Pos (0U) +#define RCC_PLL3DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3DIVR1_DIVN RCC_PLL3DIVR1_DIVN_Msk /*!< DIVN3[8:0] bits: PLL3 DIVN division factor */ +#define RCC_PLL3DIVR1_DIVN_0 (0x001UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3DIVR1_DIVN_1 (0x002UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3DIVR1_DIVN_2 (0x004UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3DIVR1_DIVN_3 (0x008UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3DIVR1_DIVN_4 (0x010UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3DIVR1_DIVN_5 (0x020UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3DIVR1_DIVN_6 (0x040UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3DIVR1_DIVN_7 (0x080UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3DIVR1_DIVN_8 (0x100UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL3DIVR1_DIVP_Pos (9U) +#define RCC_PLL3DIVR1_DIVP_Msk (0x7FUL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL3DIVR1_DIVP RCC_PLL3DIVR1_DIVP_Msk /*!< DIVP3[6:0] bits: PLL3 DIVP division factor */ +#define RCC_PLL3DIVR1_DIVP_0 (0x001UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL3DIVR1_DIVP_1 (0x002UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL3DIVR1_DIVP_2 (0x004UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL3DIVR1_DIVP_3 (0x008UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL3DIVR1_DIVP_4 (0x010UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL3DIVR1_DIVP_5 (0x020UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL3DIVR1_DIVP_6 (0x040UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL3DIVR1_DIVQ_Pos (16U) +#define RCC_PLL3DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3DIVR1_DIVQ RCC_PLL3DIVR1_DIVQ_Msk /*!< DIVQ3[6:0] bits: PLL3 DIVQ division factor */ +#define RCC_PLL3DIVR1_DIVQ_0 (0x001UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL3DIVR1_DIVQ_1 (0x002UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL3DIVR1_DIVQ_2 (0x004UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL3DIVR1_DIVQ_3 (0x008UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL3DIVR1_DIVQ_4 (0x010UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL3DIVR1_DIVQ_5 (0x020UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL3DIVR1_DIVQ_6 (0x040UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL3DIVR1_DIVR_Pos (24U) +#define RCC_PLL3DIVR1_DIVR_Msk (0x7FUL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL3DIVR1_DIVR RCC_PLL3DIVR1_DIVR_Msk /*!< DIVR3[6:0] bits: PLL3 DIVR division factor */ +#define RCC_PLL3DIVR1_DIVR_0 (0x001UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL3DIVR1_DIVR_1 (0x002UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL3DIVR1_DIVR_2 (0x004UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL3DIVR1_DIVR_3 (0x008UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL3DIVR1_DIVR_4 (0x010UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL3DIVR1_DIVR_5 (0x020UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL3DIVR1_DIVR_6 (0x040UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL3FRACR register *************/ +#define RCC_PLL3FRACR_FRACN_Pos (3U) +#define RCC_PLL3FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACN RCC_PLL3FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_CCIPR1 register **************/ +#define RCC_CCIPR1_FMCSEL_Pos (0U) +#define RCC_CCIPR1_FMCSEL_Msk (0x3UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_FMCSEL RCC_CCIPR1_FMCSEL_Msk +#define RCC_CCIPR1_FMCSEL_0 (0x1UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_FMCSEL_1 (0x2UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000002 */ + +#define RCC_CCIPR1_SDMMC12SEL_Pos (2U) +#define RCC_CCIPR1_SDMMC12SEL_Msk (0x1UL << RCC_CCIPR1_SDMMC12SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_SDMMC12SEL RCC_CCIPR1_SDMMC12SEL_Msk + +#define RCC_CCIPR1_XSPI1SEL_Pos (4U) +#define RCC_CCIPR1_XSPI1SEL_Msk (0x3UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR1_XSPI1SEL RCC_CCIPR1_XSPI1SEL_Msk +#define RCC_CCIPR1_XSPI1SEL_0 (0x1UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_XSPI1SEL_1 (0x2UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000020 */ + +#define RCC_CCIPR1_XSPI2SEL_Pos (6U) +#define RCC_CCIPR1_XSPI2SEL_Msk (0x3UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR1_XSPI2SEL RCC_CCIPR1_XSPI2SEL_Msk +#define RCC_CCIPR1_XSPI2SEL_0 (0x1UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_XSPI2SEL_1 (0x2UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x00000080 */ + +#define RCC_CCIPR1_USBREFCKSEL_Pos (8U) +#define RCC_CCIPR1_USBREFCKSEL_Msk (0xFUL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000F00 */ +#define RCC_CCIPR1_USBREFCKSEL RCC_CCIPR1_USBREFCKSEL_Msk +#define RCC_CCIPR1_USBREFCKSEL_0 (0x1UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_USBREFCKSEL_1 (0x2UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_USBREFCKSEL_2 (0x4UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_USBREFCKSEL_3 (0x8UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000800 */ + +#define RCC_CCIPR1_USBPHYCSEL_Pos (12U) +#define RCC_CCIPR1_USBPHYCSEL_Msk (0x3UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR1_USBPHYCSEL RCC_CCIPR1_USBPHYCSEL_Msk +#define RCC_CCIPR1_USBPHYCSEL_0 (0x1UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR1_USBPHYCSEL_1 (0x2UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00002000 */ + +#define RCC_CCIPR1_OTGFSSEL_Pos (14U) +#define RCC_CCIPR1_OTGFSSEL_Msk (0x3UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_OTGFSSEL RCC_CCIPR1_OTGFSSEL_Msk +#define RCC_CCIPR1_OTGFSSEL_0 (0x1UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_OTGFSSEL_1 (0x2UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x00008000 */ + +#define RCC_CCIPR1_ETH1REFCKSEL_Pos (16U) +#define RCC_CCIPR1_ETH1REFCKSEL_Msk (0x3UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_ETH1REFCKSEL RCC_CCIPR1_ETH1REFCKSEL_Msk +#define RCC_CCIPR1_ETH1REFCKSEL_0 (0x1UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_ETH1REFCKSEL_1 (0x2UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00020000 */ + +#define RCC_CCIPR1_ETH1PHYCKSEL_Pos (18U) +#define RCC_CCIPR1_ETH1PHYCKSEL_Msk (0x1UL << RCC_CCIPR1_ETH1PHYCKSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_ETH1PHYCKSEL RCC_CCIPR1_ETH1PHYCKSEL_Msk + +#define RCC_CCIPR1_ADF1SEL_Pos (20U) +#define RCC_CCIPR1_ADF1SEL_Msk (0x7UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR1_ADF1SEL RCC_CCIPR1_ADF1SEL_Msk +#define RCC_CCIPR1_ADF1SEL_0 (0x1UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_ADF1SEL_1 (0x2UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR1_ADF1SEL_2 (0x4UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00400000 */ + +#define RCC_CCIPR1_ADCSEL_Pos (24U) +#define RCC_CCIPR1_ADCSEL_Msk (0x3UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR1_ADCSEL RCC_CCIPR1_ADCSEL_Msk +#define RCC_CCIPR1_ADCSEL_0 (0x1UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR1_ADCSEL_1 (0x2UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x02000000 */ + +#define RCC_CCIPR1_PSSISEL_Pos (27U) +#define RCC_CCIPR1_PSSISEL_Msk (0x1UL << RCC_CCIPR1_PSSISEL_Pos) /*!< 0x08000000 */ +#define RCC_CCIPR1_PSSISEL RCC_CCIPR1_PSSISEL_Msk + +#define RCC_CCIPR1_CKPERSEL_Pos (28U) +#define RCC_CCIPR1_CKPERSEL_Msk (0x3UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x30000000 */ +#define RCC_CCIPR1_CKPERSEL RCC_CCIPR1_CKPERSEL_Msk +#define RCC_CCIPR1_CKPERSEL_0 (0x1UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR1_CKPERSEL_1 (0x2UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for RCC_CCIPR2 register *************/ +#define RCC_CCIPR2_UART234578SEL_Pos (0U) +#define RCC_CCIPR2_UART234578SEL_Msk (0x7UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR2_UART234578SEL RCC_CCIPR2_UART234578SEL_Msk +#define RCC_CCIPR2_UART234578SEL_0 (0x1UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_UART234578SEL_1 (0x2UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_UART234578SEL_2 (0x4UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR2_SPI23SEL_Pos (4U) +#define RCC_CCIPR2_SPI23SEL_Msk (0x7UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR2_SPI23SEL RCC_CCIPR2_SPI23SEL_Msk +#define RCC_CCIPR2_SPI23SEL_0 (0x1UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR2_SPI23SEL_1 (0x2UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR2_SPI23SEL_2 (0x4UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR2_I2C23SEL_Pos (8U) +#define RCC_CCIPR2_I2C23SEL_Msk (0x3UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR2_I2C23SEL RCC_CCIPR2_I2C23SEL_Msk +#define RCC_CCIPR2_I2C23SEL_0 (0x1UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR2_I2C23SEL_1 (0x2UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000200 */ + +#define RCC_CCIPR2_I2C1_I3C1SEL_Pos (12U) +#define RCC_CCIPR2_I2C1_I3C1SEL_Msk (0x3UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR2_I2C1_I3C1SEL RCC_CCIPR2_I2C1_I3C1SEL_Msk +#define RCC_CCIPR2_I2C1_I3C1SEL_0 (0x1UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_I2C1_I3C1SEL_1 (0x2UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00002000 */ + +#define RCC_CCIPR2_LPTIM1SEL_Pos (16U) +#define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR2_LPTIM1SEL RCC_CCIPR2_LPTIM1SEL_Msk +#define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00040000 */ + +#define RCC_CCIPR2_FDCANSEL_Pos (22U) +#define RCC_CCIPR2_FDCANSEL_Msk (0x3UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00C00000 */ +#define RCC_CCIPR2_FDCANSEL RCC_CCIPR2_FDCANSEL_Msk +#define RCC_CCIPR2_FDCANSEL_0 (0x1UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR2_FDCANSEL_1 (0x2UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00800000 */ + +#define RCC_CCIPR2_SPDIFRXSEL_Pos (24U) +#define RCC_CCIPR2_SPDIFRXSEL_Msk (0x3UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_SPDIFRXSEL RCC_CCIPR2_SPDIFRXSEL_Msk +#define RCC_CCIPR2_SPDIFRXSEL_0 (0x1UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_SPDIFRXSEL_1 (0x2UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x02000000 */ + +#define RCC_CCIPR2_CECSEL_Pos (28U) +#define RCC_CCIPR2_CECSEL_Msk (0x3UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_CECSEL RCC_CCIPR2_CECSEL_Msk +#define RCC_CCIPR2_CECSEL_0 (0x1UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_CECSEL_1 (0x2UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for RCC_CCIPR3 register *************/ +#define RCC_CCIPR3_USART1SEL_Pos (0U) +#define RCC_CCIPR3_USART1SEL_Msk (0x7UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR3_USART1SEL RCC_CCIPR3_USART1SEL_Msk +#define RCC_CCIPR3_USART1SEL_0 (0x1UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_USART1SEL_1 (0x2UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_USART1SEL_2 (0x4UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR3_SPI45SEL_Pos (4U) +#define RCC_CCIPR3_SPI45SEL_Msk (0x7UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR3_SPI45SEL RCC_CCIPR3_SPI45SEL_Msk +#define RCC_CCIPR3_SPI45SEL_0 (0x1UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_SPI45SEL_1 (0x2UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR3_SPI45SEL_2 (0x4UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR3_SPI1SEL_Pos (8U) +#define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR3_SPI1SEL RCC_CCIPR3_SPI1SEL_Msk +#define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000400 */ + +#define RCC_CCIPR3_SAI1SEL_Pos (16U) +#define RCC_CCIPR3_SAI1SEL_Msk (0x7UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR3_SAI1SEL RCC_CCIPR3_SAI1SEL_Msk +#define RCC_CCIPR3_SAI1SEL_0 (0x1UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR3_SAI1SEL_1 (0x2UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR3_SAI1SEL_2 (0x4UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00040000 */ + +#define RCC_CCIPR3_SAI2SEL_Pos (20U) +#define RCC_CCIPR3_SAI2SEL_Msk (0x7UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR3_SAI2SEL RCC_CCIPR3_SAI2SEL_Msk +#define RCC_CCIPR3_SAI2SEL_0 (0x1UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR3_SAI2SEL_1 (0x2UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR3_SAI2SEL_2 (0x4UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for RCC_CCIPR4 register ************/ +#define RCC_CCIPR4_LPUART1SEL_Pos (0U) +#define RCC_CCIPR4_LPUART1SEL_Msk (0x7UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR4_LPUART1SEL RCC_CCIPR4_LPUART1SEL_Msk +#define RCC_CCIPR4_LPUART1SEL_0 (0x1UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR4_LPUART1SEL_1 (0x2UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR4_LPUART1SEL_2 (0x4UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR4_SPI6SEL_Pos (4U) +#define RCC_CCIPR4_SPI6SEL_Msk (0x7UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR4_SPI6SEL RCC_CCIPR4_SPI6SEL_Msk +#define RCC_CCIPR4_SPI6SEL_0 (0x1UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR4_SPI6SEL_1 (0x2UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR4_SPI6SEL_2 (0x4UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR4_LPTIM23SEL_Pos (8U) +#define RCC_CCIPR4_LPTIM23SEL_Msk (0x7UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR4_LPTIM23SEL RCC_CCIPR4_LPTIM23SEL_Msk +#define RCC_CCIPR4_LPTIM23SEL_0 (0x1UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR4_LPTIM23SEL_1 (0x2UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR4_LPTIM23SEL_2 (0x4UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000400 */ + +#define RCC_CCIPR4_LPTIM45SEL_Pos (12U) +#define RCC_CCIPR4_LPTIM45SEL_Msk (0x7UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR4_LPTIM45SEL RCC_CCIPR4_LPTIM45SEL_Msk +#define RCC_CCIPR4_LPTIM45SEL_0 (0x1UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR4_LPTIM45SEL_1 (0x2UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR4_LPTIM45SEL_2 (0x4UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_CIER register ******************/ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk +#define RCC_CIER_HSIRDYIE_Pos (2U) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk +#define RCC_CIER_HSERDYIE_Pos (3U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk +#define RCC_CIER_CSIRDYIE_Pos (4U) +#define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk +#define RCC_CIER_HSI48RDYIE_Pos (5U) +#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk +#define RCC_CIER_PLL1RDYIE_Pos (6U) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk +#define RCC_CIER_PLL2RDYIE_Pos (7U) +#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk +#define RCC_CIER_PLL3RDYIE_Pos (8U) +#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk +#define RCC_CIER_LSECSSIE_Pos (9U) +#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */ +#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk + +/******************** Bit definition for RCC_CIFR register ******************/ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk +#define RCC_CIFR_HSIRDYF_Pos (2U) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk +#define RCC_CIFR_HSERDYF_Pos (3U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk +#define RCC_CIFR_CSIRDYF_Pos (4U) +#define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk +#define RCC_CIFR_HSI48RDYF_Pos (5U) +#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk +#define RCC_CIFR_PLL1RDYF_Pos (6U) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk +#define RCC_CIFR_PLL2RDYF_Pos (7U) +#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk +#define RCC_CIFR_PLL3RDYF_Pos (8U) +#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk +#define RCC_CIFR_LSECSSF_Pos (9U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk + +/******************** Bit definition for RCC_CICR register ******************/ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk +#define RCC_CICR_HSIRDYC_Pos (2U) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk +#define RCC_CICR_HSERDYC_Pos (3U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk +#define RCC_CICR_CSIRDYC_Pos (4U) +#define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk +#define RCC_CICR_HSI48RDYC_Pos (5U) +#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk +#define RCC_CICR_PLL1RDYC_Pos (6U) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk +#define RCC_CICR_PLL2RDYC_Pos (7U) +#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk +#define RCC_CICR_PLL3RDYC_Pos (8U) +#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk +#define RCC_CICR_LSECSSC_Pos (9U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk + +/******************** Bit definition for RCC_BDCR register ******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk +#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk +#define RCC_BDCR_LSEDRV_Pos (3U) +#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk +#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ + +#define RCC_BDCR_LSECSSON_Pos (5U) +#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk +#define RCC_BDCR_LSECSSD_Pos (6U) +#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk +#define RCC_BDCR_LSEEXT_Pos (7U) +#define RCC_BDCR_LSEEXT_Msk (0x1UL << RCC_BDCR_LSEEXT_Pos) /*!< 0x00000080 */ +#define RCC_BDCR_LSEEXT RCC_BDCR_LSEEXT_Msk +#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk +#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSRA_Pos (12U) +#define RCC_BDCR_LSECSSRA_Msk (0x1UL << RCC_BDCR_LSECSSRA_Pos) /*!< 0x00001000 */ +#define RCC_BDCR_LSECSSRA RCC_BDCR_LSECSSRA_Msk + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk +#define RCC_BDCR_VSWRST_Pos (16U) +#define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk + +/******************** Bit definition for RCC_AHB1RSTR register **************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (4U) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk +#define RCC_AHB1RSTR_ADC12RST_Pos (5U) +#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk +#define RCC_AHB1RSTR_ETH1RST_Pos (15U) +#define RCC_AHB1RSTR_ETH1RST_Msk (0x1UL << RCC_AHB1RSTR_ETH1RST_Pos) /*!< 0x00008000 */ +#define RCC_AHB1RSTR_ETH1RST RCC_AHB1RSTR_ETH1RST_Msk +#define RCC_AHB1RSTR_OTGHSRST_Pos (25U) +#define RCC_AHB1RSTR_OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHSRST_Pos) /*!< 0x02000000 */ +#define RCC_AHB1RSTR_OTGHSRST RCC_AHB1RSTR_OTGHSRST_Msk +#define RCC_AHB1RSTR_USBPHYCRST_Pos (26U) +#define RCC_AHB1RSTR_USBPHYCRST_Msk (0x1UL << RCC_AHB1RSTR_USBPHYCRST_Pos) /*!< 0x04000000 */ +#define RCC_AHB1RSTR_USBPHYCRST RCC_AHB1RSTR_USBPHYCRST_Msk +#define RCC_AHB1RSTR_OTGFSRST_Pos (27U) +#define RCC_AHB1RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_OTGFSRST_Pos) /*!< 0x08000000 */ +#define RCC_AHB1RSTR_OTGFSRST RCC_AHB1RSTR_OTGFSRST_Msk +#define RCC_AHB1RSTR_ADF1RST_Pos (31U) +#define RCC_AHB1RSTR_ADF1RST_Msk (0x1UL << RCC_AHB1RSTR_ADF1RST_Pos) /*!< 0x80000000 */ +#define RCC_AHB1RSTR_ADF1RST RCC_AHB1RSTR_ADF1RST_Msk + +/******************** Bit definition for RCC_AHB2RSTR register **************/ +#define RCC_AHB2RSTR_PSSIRST_Pos (1U) +#define RCC_AHB2RSTR_PSSIRST_Msk (0x1UL << RCC_AHB2RSTR_PSSIRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_PSSIRST RCC_AHB2RSTR_PSSIRST_Msk +#define RCC_AHB2RSTR_SDMMC2RST_Pos (9U) +#define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) /*!< 0x00000200 */ +#define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk +#define RCC_AHB2RSTR_CORDICRST_Pos (14U) +#define RCC_AHB2RSTR_CORDICRST_Msk (0x1UL << RCC_AHB2RSTR_CORDICRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB2RSTR_CORDICRST RCC_AHB2RSTR_CORDICRST_Msk + +/******************** Bit definition for RCC_AHB3RSTR register **************/ +#define RCC_AHB3RSTR_RNGRST_Pos (0U) +#define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk +#define RCC_AHB3RSTR_HASHRST_Pos (1U) +#define RCC_AHB3RSTR_HASHRST_Msk (0x1UL << RCC_AHB3RSTR_HASHRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTR_HASHRST RCC_AHB3RSTR_HASHRST_Msk +#define RCC_AHB3RSTR_PKARST_Pos (6U) +#define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk + +/******************** Bit definition for RCC_AHB4RSTR register **************/ +#define RCC_AHB4RSTR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk +#define RCC_AHB4RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk +#define RCC_AHB4RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk +#define RCC_AHB4RSTR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk +#define RCC_AHB4RSTR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk +#define RCC_AHB4RSTR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk +#define RCC_AHB4RSTR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk +#define RCC_AHB4RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk +#define RCC_AHB4RSTR_GPIOMRST_Pos (12U) +#define RCC_AHB4RSTR_GPIOMRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOMRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB4RSTR_GPIOMRST RCC_AHB4RSTR_GPIOMRST_Msk +#define RCC_AHB4RSTR_GPIONRST_Pos (13U) +#define RCC_AHB4RSTR_GPIONRST_Msk (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB4RSTR_GPIONRST RCC_AHB4RSTR_GPIONRST_Msk +#define RCC_AHB4RSTR_GPIOORST_Pos (14U) +#define RCC_AHB4RSTR_GPIOORST_Msk (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos) /*!< 0x00004000 */ +#define RCC_AHB4RSTR_GPIOORST RCC_AHB4RSTR_GPIOORST_Msk +#define RCC_AHB4RSTR_GPIOPRST_Pos (15U) +#define RCC_AHB4RSTR_GPIOPRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos) /*!< 0x00008000 */ +#define RCC_AHB4RSTR_GPIOPRST RCC_AHB4RSTR_GPIOPRST_Msk +#define RCC_AHB4RSTR_CRCRST_Pos (19U) +#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk + +/******************** Bit definition for RCC_AHB5RSTR register **************/ +#define RCC_AHB5RSTR_HPDMA1RST_Pos (0U) +#define RCC_AHB5RSTR_HPDMA1RST_Msk (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_HPDMA1RST RCC_AHB5RSTR_HPDMA1RST_Msk +#define RCC_AHB5RSTR_DMA2DRST_Pos (1U) +#define RCC_AHB5RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB5RSTR_DMA2DRST RCC_AHB5RSTR_DMA2DRST_Msk +#define RCC_AHB5RSTR_JPEGRST_Pos (3U) +#define RCC_AHB5RSTR_JPEGRST_Msk (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTR_JPEGRST RCC_AHB5RSTR_JPEGRST_Msk +#define RCC_AHB5RSTR_FMCRST_Pos (4U) +#define RCC_AHB5RSTR_FMCRST_Msk (0x1UL << RCC_AHB5RSTR_FMCRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTR_FMCRST RCC_AHB5RSTR_FMCRST_Msk +#define RCC_AHB5RSTR_XSPI1RST_Pos (5U) +#define RCC_AHB5RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTR_XSPI1RST RCC_AHB5RSTR_XSPI1RST_Msk +#define RCC_AHB5RSTR_SDMMC1RST_Pos (8U) +#define RCC_AHB5RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTR_SDMMC1RST RCC_AHB5RSTR_SDMMC1RST_Msk +#define RCC_AHB5RSTR_XSPI2RST_Pos (12U) +#define RCC_AHB5RSTR_XSPI2RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos) /*!< 0x00001000 */ +#define RCC_AHB5RSTR_XSPI2RST RCC_AHB5RSTR_XSPI2RST_Msk +#define RCC_AHB5RSTR_XSPIMRST_Pos (14U) +#define RCC_AHB5RSTR_XSPIMRST_Msk (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB5RSTR_XSPIMRST RCC_AHB5RSTR_XSPIMRST_Msk +#define RCC_AHB5RSTR_GFXMMURST_Pos (19U) +#define RCC_AHB5RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTR_GFXMMURST RCC_AHB5RSTR_GFXMMURST_Msk +#define RCC_AHB5RSTR_GPU2DRST_Pos (20U) +#define RCC_AHB5RSTR_GPU2DRST_Msk (0x1UL << RCC_AHB5RSTR_GPU2DRST_Pos) /*!< 0x00100000 */ +#define RCC_AHB5RSTR_GPU2DRST RCC_AHB5RSTR_GPU2DRST_Msk + +/******************** Bit definition for RCC_APB1RSTR1 register *************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0U) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk +#define RCC_APB1RSTR1_TIM3RST_Pos (1U) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk +#define RCC_APB1RSTR1_TIM4RST_Pos (2U) +#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk +#define RCC_APB1RSTR1_TIM5RST_Pos (3U) +#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk +#define RCC_APB1RSTR1_TIM6RST_Pos (4U) +#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk +#define RCC_APB1RSTR1_TIM7RST_Pos (5U) +#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk +#define RCC_APB1RSTR1_TIM12RST_Pos (6U) +#define RCC_APB1RSTR1_TIM12RST_Msk (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTR1_TIM12RST RCC_APB1RSTR1_TIM12RST_Msk +#define RCC_APB1RSTR1_TIM13RST_Pos (7U) +#define RCC_APB1RSTR1_TIM13RST_Msk (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTR1_TIM13RST RCC_APB1RSTR1_TIM13RST_Msk +#define RCC_APB1RSTR1_TIM14RST_Pos (8U) +#define RCC_APB1RSTR1_TIM14RST_Msk (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR1_TIM14RST RCC_APB1RSTR1_TIM14RST_Msk +#define RCC_APB1RSTR1_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk +#define RCC_APB1RSTR1_SPI2RST_Pos (14U) +#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk +#define RCC_APB1RSTR1_SPI3RST_Pos (15U) +#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk +#define RCC_APB1RSTR1_SPDIFRXRST_Pos (16U) +#define RCC_APB1RSTR1_SPDIFRXRST_Msk (0x1UL << RCC_APB1RSTR1_SPDIFRXRST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTR1_SPDIFRXRST RCC_APB1RSTR1_SPDIFRXRST_Msk +#define RCC_APB1RSTR1_USART2RST_Pos (17U) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk +#define RCC_APB1RSTR1_USART3RST_Pos (18U) +#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk +#define RCC_APB1RSTR1_UART4RST_Pos (19U) +#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk +#define RCC_APB1RSTR1_UART5RST_Pos (20U) +#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk +#define RCC_APB1RSTR1_I2C1_I3C1RST_Pos (21U) +#define RCC_APB1RSTR1_I2C1_I3C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1_I3C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1_I3C1RST RCC_APB1RSTR1_I2C1_I3C1RST_Msk +#define RCC_APB1RSTR1_I2C2RST_Pos (22U) +#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk +#define RCC_APB1RSTR1_I2C3RST_Pos (23U) +#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk +#define RCC_APB1RSTR1_CECRST_Pos (27U) +#define RCC_APB1RSTR1_CECRST_Msk (0x1UL << RCC_APB1RSTR1_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR1_CECRST RCC_APB1RSTR1_CECRST_Msk +#define RCC_APB1RSTR1_UART7RST_Pos (30U) +#define RCC_APB1RSTR1_UART7RST_Msk (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTR1_UART7RST RCC_APB1RSTR1_UART7RST_Msk +#define RCC_APB1RSTR1_UART8RST_Pos (31U) +#define RCC_APB1RSTR1_UART8RST_Msk (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR1_UART8RST RCC_APB1RSTR1_UART8RST_Msk + +/******************** Bit definition for RCC_APB1RSTR2 register *************/ +#define RCC_APB1RSTR2_CRSRST_Pos (1U) +#define RCC_APB1RSTR2_CRSRST_Msk (0x1UL << RCC_APB1RSTR2_CRSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR2_CRSRST RCC_APB1RSTR2_CRSRST_Msk +#define RCC_APB1RSTR2_MDIOSRST_Pos (5U) +#define RCC_APB1RSTR2_MDIOSRST_Msk (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_MDIOSRST RCC_APB1RSTR2_MDIOSRST_Msk +#define RCC_APB1RSTR2_FDCANRST_Pos (8U) +#define RCC_APB1RSTR2_FDCANRST_Msk (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR2_FDCANRST RCC_APB1RSTR2_FDCANRST_Msk +#define RCC_APB1RSTR2_UCPD1RST_Pos (27U) +#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk + +/******************** Bit definition for RCC_APB2RSTR register **************/ +#define RCC_APB2RSTR_TIM1RST_Pos (0U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk +#define RCC_APB2RSTR_USART1RST_Pos (4U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk +#define RCC_APB2RSTR_SPI4RST_Pos (13U) +#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk +#define RCC_APB2RSTR_TIM9RST_Pos (19U) +#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk +#define RCC_APB2RSTR_SPI5RST_Pos (20U) +#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk +#define RCC_APB2RSTR_SAI1RST_Pos (22U) +#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk +#define RCC_APB2RSTR_SAI2RST_Pos (23U) +#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */ +#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk + +/******************** Bit definition for RCC_APB4RSTR register **************/ +#define RCC_APB4RSTR_SBSRST_Pos (1U) +#define RCC_APB4RSTR_SBSRST_Msk (0x1UL << RCC_APB4RSTR_SBSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB4RSTR_SBSRST RCC_APB4RSTR_SBSRST_Msk +#define RCC_APB4RSTR_LPUART1RST_Pos (3U) +#define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk +#define RCC_APB4RSTR_SPI6RST_Pos (5U) +#define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk +#define RCC_APB4RSTR_LPTIM2RST_Pos (9U) +#define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk +#define RCC_APB4RSTR_LPTIM3RST_Pos (10U) +#define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk +#define RCC_APB4RSTR_LPTIM4RST_Pos (11U) +#define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk +#define RCC_APB4RSTR_LPTIM5RST_Pos (12U) +#define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk +#define RCC_APB4RSTR_VREFRST_Pos (15U) +#define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk +#define RCC_APB4RSTR_DTSRST_Pos (26U) +#define RCC_APB4RSTR_DTSRST_Msk (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */ +#define RCC_APB4RSTR_DTSRST RCC_APB4RSTR_DTSRST_Msk + +/******************** Bit definition for RCC_APB5RSTR register **************/ +#define RCC_APB5RSTR_LTDCRST_Pos (1U) +#define RCC_APB5RSTR_LTDCRST_Msk (0x1UL << RCC_APB5RSTR_LTDCRST_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTR_LTDCRST RCC_APB5RSTR_LTDCRST_Msk +#define RCC_APB5RSTR_DCMIPPRST_Pos (2U) +#define RCC_APB5RSTR_DCMIPPRST_Msk (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTR_DCMIPPRST RCC_APB5RSTR_DCMIPPRST_Msk +#define RCC_APB5RSTR_GFXTIMRST_Pos (4U) +#define RCC_APB5RSTR_GFXTIMRST_Msk (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTR_GFXTIMRST RCC_APB5RSTR_GFXTIMRST_Msk + +/******************** Bit definition for RCC_CKGDISR register ***************/ +#define RCC_CKGDISR_AXICKG_Pos (0U) +#define RCC_CKGDISR_AXICKG_Msk (0x1UL << RCC_CKGDISR_AXICKG_Pos) /*!< 0x00000001 */ +#define RCC_CKGDISR_AXICKG RCC_CKGDISR_AXICKG_Msk +#define RCC_CKGDISR_AHBMCKG_Pos (1U) +#define RCC_CKGDISR_AHBMCKG_Msk (0x1UL << RCC_CKGDISR_AHBMCKG_Pos) /*!< 0x00000002 */ +#define RCC_CKGDISR_AHBMCKG RCC_CKGDISR_AHBMCKG_Msk +#define RCC_CKGDISR_SDMMC1CKG_Pos (2U) +#define RCC_CKGDISR_SDMMC1CKG_Msk (0x1UL << RCC_CKGDISR_SDMMC1CKG_Pos) /*!< 0x00000004 */ +#define RCC_CKGDISR_SDMMC1CKG RCC_CKGDISR_SDMMC1CKG_Msk +#define RCC_CKGDISR_HPDMA1CKG_Pos (3U) +#define RCC_CKGDISR_HPDMA1CKG_Msk (0x1UL << RCC_CKGDISR_HPDMA1CKG_Pos) /*!< 0x00000008 */ +#define RCC_CKGDISR_HPDMA1CKG RCC_CKGDISR_HPDMA1CKG_Msk +#define RCC_CKGDISR_CPUCKG_Pos (4U) +#define RCC_CKGDISR_CPUCKG_Msk (0x1UL << RCC_CKGDISR_CPUCKG_Pos) /*!< 0x00000010 */ +#define RCC_CKGDISR_CPUCKG RCC_CKGDISR_CPUCKG_Msk +#define RCC_CKGDISR_GPU2DS0CKG_Pos (5U) +#define RCC_CKGDISR_GPU2DS0CKG_Msk (0x1UL << RCC_CKGDISR_GPU2DS0CKG_Pos) /*!< 0x00000020 */ +#define RCC_CKGDISR_GPU2DS0CKG RCC_CKGDISR_GPU2DS0CKG_Msk +#define RCC_CKGDISR_GPU2DS1CKG_Pos (6U) +#define RCC_CKGDISR_GPU2DS1CKG_Msk (0x1UL << RCC_CKGDISR_GPU2DS1CKG_Pos) /*!< 0x00000040 */ +#define RCC_CKGDISR_GPU2DS1CKG RCC_CKGDISR_GPU2DS1CKG_Msk +#define RCC_CKGDISR_GPU2DCLCKG_Pos (7U) +#define RCC_CKGDISR_GPU2DCLCKG_Msk (0x1UL << RCC_CKGDISR_GPU2DCLCKG_Pos) /*!< 0x00000080 */ +#define RCC_CKGDISR_GPU2DCLCKG RCC_CKGDISR_GPU2DCLCKG_Msk +#define RCC_CKGDISR_DCMIPPCKG_Pos (8U) +#define RCC_CKGDISR_DCMIPPCKG_Msk (0x1UL << RCC_CKGDISR_DCMIPPCKG_Pos) /*!< 0x00000100 */ +#define RCC_CKGDISR_DCMIPPCKG RCC_CKGDISR_DCMIPPCKG_Msk +#define RCC_CKGDISR_DMA2DCKG_Pos (9U) +#define RCC_CKGDISR_DMA2DCKG_Msk (0x1UL << RCC_CKGDISR_DMA2DCKG_Pos) /*!< 0x00000200 */ +#define RCC_CKGDISR_DMA2DCKG RCC_CKGDISR_DMA2DCKG_Msk +#define RCC_CKGDISR_GFXMMUSCKG_Pos (10U) +#define RCC_CKGDISR_GFXMMUSCKG_Msk (0x1UL << RCC_CKGDISR_GFXMMUSCKG_Pos) /*!< 0x00000400 */ +#define RCC_CKGDISR_GFXMMUSCKG RCC_CKGDISR_GFXMMUSCKG_Msk +#define RCC_CKGDISR_LTDCCKG_Pos (11U) +#define RCC_CKGDISR_LTDCCKG_Msk (0x1UL << RCC_CKGDISR_LTDCCKG_Pos) /*!< 0x00000800 */ +#define RCC_CKGDISR_LTDCCKG RCC_CKGDISR_LTDCCKG_Msk +#define RCC_CKGDISR_GFXMMUMCKG_Pos (12U) +#define RCC_CKGDISR_GFXMMUMCKG_Msk (0x1UL << RCC_CKGDISR_GFXMMUMCKG_Pos) /*!< 0x00001000 */ +#define RCC_CKGDISR_GFXMMUMCKG RCC_CKGDISR_GFXMMUMCKG_Msk +#define RCC_CKGDISR_AHBSCKG_Pos (13U) +#define RCC_CKGDISR_AHBSCKG_Msk (0x1UL << RCC_CKGDISR_AHBSCKG_Pos) /*!< 0x00002000 */ +#define RCC_CKGDISR_AHBSCKG RCC_CKGDISR_AHBSCKG_Msk +#define RCC_CKGDISR_FMCCKG_Pos (14U) +#define RCC_CKGDISR_FMCCKG_Msk (0x1UL << RCC_CKGDISR_FMCCKG_Pos) /*!< 0x00004000 */ +#define RCC_CKGDISR_FMCCKG RCC_CKGDISR_FMCCKG_Msk +#define RCC_CKGDISR_XSPI1CKG_Pos (15U) +#define RCC_CKGDISR_XSPI1CKG_Msk (0x1UL << RCC_CKGDISR_XSPI1CKG_Pos) /*!< 0x00008000 */ +#define RCC_CKGDISR_XSPI1CKG RCC_CKGDISR_XSPI1CKG_Msk +#define RCC_CKGDISR_XSPI2CKG_Pos (16U) +#define RCC_CKGDISR_XSPI2CKG_Msk (0x1UL << RCC_CKGDISR_XSPI2CKG_Pos) /*!< 0x00010000 */ +#define RCC_CKGDISR_XSPI2CKG RCC_CKGDISR_XSPI2CKG_Msk +#define RCC_CKGDISR_AXISRAM4CKG_Pos (17U) +#define RCC_CKGDISR_AXISRAM4CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM4CKG_Pos) /*!< 0x00020000 */ +#define RCC_CKGDISR_AXISRAM4CKG RCC_CKGDISR_AXISRAM4CKG_Msk +#define RCC_CKGDISR_AXISRAM3CKG_Pos (18U) +#define RCC_CKGDISR_AXISRAM3CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM3CKG_Pos) /*!< 0x00040000 */ +#define RCC_CKGDISR_AXISRAM3CKG RCC_CKGDISR_AXISRAM3CKG_Msk +#define RCC_CKGDISR_AXISRAM2CKG_Pos (19U) +#define RCC_CKGDISR_AXISRAM2CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM2CKG_Pos) /*!< 0x00080000 */ +#define RCC_CKGDISR_AXISRAM2CKG RCC_CKGDISR_AXISRAM2CKG_Msk +#define RCC_CKGDISR_AXISRAM1CKG_Pos (20U) +#define RCC_CKGDISR_AXISRAM1CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM1CKG_Pos) /*!< 0x00100000 */ +#define RCC_CKGDISR_AXISRAM1CKG RCC_CKGDISR_AXISRAM1CKG_Msk +#define RCC_CKGDISR_FLASHCKG_Pos (21U) +#define RCC_CKGDISR_FLASHCKG_Msk (0x1UL << RCC_CKGDISR_FLASHCKG_Pos) /*!< 0x00200000 */ +#define RCC_CKGDISR_FLASHCKG RCC_CKGDISR_FLASHCKG_Msk +#define RCC_CKGDISR_EXTICKG_Pos (30U) +#define RCC_CKGDISR_EXTICKG_Msk (0x1UL << RCC_CKGDISR_EXTICKG_Pos) /*!< 0x40000000 */ +#define RCC_CKGDISR_EXTICKG RCC_CKGDISR_EXTICKG_Msk +#define RCC_CKGDISR_JTAGCKG_Pos (31U) +#define RCC_CKGDISR_JTAGCKG_Msk (0x1UL << RCC_CKGDISR_JTAGCKG_Pos) /*!< 0x80000000 */ +#define RCC_CKGDISR_JTAGCKG RCC_CKGDISR_JTAGCKG_Msk + +/******************** Bit definition for RCC_PLL1DIVR2 register *************/ +#define RCC_PLL1DIVR2_DIVS_Pos (0U) +#define RCC_PLL1DIVR2_DIVS_Msk (0x7UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL1DIVR2_DIVS RCC_PLL1DIVR2_DIVS_Msk /*!< DIVS1[2:0] bits: PLL1 DIVS division factor */ +#define RCC_PLL1DIVR2_DIVS_0 (0x1UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR2_DIVS_1 (0x2UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR2_DIVS_2 (0x4UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for RCC_PLL2DIVR2 register *************/ +#define RCC_PLL2DIVR2_DIVS_Pos (0U) +#define RCC_PLL2DIVR2_DIVS_Msk (0x7UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL2DIVR2_DIVS RCC_PLL2DIVR2_DIVS_Msk /*!< DIVS2[2:0] bits: PLL2 DIVS division factor */ +#define RCC_PLL2DIVR2_DIVS_0 (0x1UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL2DIVR2_DIVS_1 (0x2UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL2DIVR2_DIVS_2 (0x4UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +#define RCC_PLL2DIVR2_DIVT_Pos (8U) +#define RCC_PLL2DIVR2_DIVT_Msk (0x7UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000700 */ +#define RCC_PLL2DIVR2_DIVT RCC_PLL2DIVR2_DIVT_Msk /*!< DIVT2[2:0] bits: PLL2 DIVT division factor */ +#define RCC_PLL2DIVR2_DIVT_0 (0x1UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000100 */ +#define RCC_PLL2DIVR2_DIVT_1 (0x2UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000200 */ +#define RCC_PLL2DIVR2_DIVT_2 (0x4UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for RCC_PLL3DIVR2 register *************/ +#define RCC_PLL3DIVR2_DIVS_Pos (0U) +#define RCC_PLL3DIVR2_DIVS_Msk (0x7UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL3DIVR2_DIVS RCC_PLL3DIVR2_DIVS_Msk /*!< DIVS3[2:0] bits: PLL3 DIVS division factor */ +#define RCC_PLL3DIVR2_DIVS_0 (0x1UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL3DIVR2_DIVS_1 (0x2UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL3DIVR2_DIVS_2 (0x4UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for RCC_PLL1SSCGR register *************/ +#define RCC_PLL1SSCGR_MODPER_Pos (0U) +#define RCC_PLL1SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1SSCGR_MODPER RCC_PLL1SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL1SSCGR_MODPER_0 (0x0001UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1SSCGR_MODPER_1 (0x0002UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1SSCGR_MODPER_2 (0x0004UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1SSCGR_MODPER_3 (0x0008UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1SSCGR_MODPER_4 (0x0010UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1SSCGR_MODPER_5 (0x0020UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1SSCGR_MODPER_6 (0x0040UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1SSCGR_MODPER_7 (0x0080UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1SSCGR_MODPER_8 (0x0100UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1SSCGR_MODPER_9 (0x0200UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1SSCGR_MODPER_10 (0x0400UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1SSCGR_MODPER_11 (0x0800UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1SSCGR_MODPER_12 (0x1000UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL1SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL1SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1SSCGR_TPDFNDIS RCC_PLL1SSCGR_TPDFNDIS_Msk +#define RCC_PLL1SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL1SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL1SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1SSCGR_RPDFNDIS RCC_PLL1SSCGR_RPDFNDIS_Msk +#define RCC_PLL1SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL1SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL1SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL1SSCGR_SPREADSEL RCC_PLL1SSCGR_SPREADSEL_Msk +#define RCC_PLL1SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL1SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1SSCGR_INCSTEP RCC_PLL1SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL1SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL2SSCGR register *************/ +#define RCC_PLL2SSCGR_MODPER_Pos (0U) +#define RCC_PLL2SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2SSCGR_MODPER RCC_PLL2SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL2SSCGR_MODPER_0 (0x0001UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2SSCGR_MODPER_1 (0x0002UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2SSCGR_MODPER_2 (0x0004UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2SSCGR_MODPER_3 (0x0008UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2SSCGR_MODPER_4 (0x0010UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2SSCGR_MODPER_5 (0x0020UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2SSCGR_MODPER_6 (0x0040UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2SSCGR_MODPER_7 (0x0080UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2SSCGR_MODPER_8 (0x0100UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2SSCGR_MODPER_9 (0x0200UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2SSCGR_MODPER_10 (0x0400UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2SSCGR_MODPER_11 (0x0800UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2SSCGR_MODPER_12 (0x1000UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL2SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL2SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2SSCGR_TPDFNDIS RCC_PLL2SSCGR_TPDFNDIS_Msk +#define RCC_PLL2SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL2SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL2SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2SSCGR_RPDFNDIS RCC_PLL2SSCGR_RPDFNDIS_Msk +#define RCC_PLL2SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL2SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL2SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL2SSCGR_SPREADSEL RCC_PLL2SSCGR_SPREADSEL_Msk +#define RCC_PLL2SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL2SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2SSCGR_INCSTEP RCC_PLL2SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL2SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL3SSCGR register *************/ +#define RCC_PLL3SSCGR_MODPER_Pos (0U) +#define RCC_PLL3SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL3SSCGR_MODPER RCC_PLL3SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL3SSCGR_MODPER_0 (0x0001UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL3SSCGR_MODPER_1 (0x0002UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL3SSCGR_MODPER_2 (0x0004UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL3SSCGR_MODPER_3 (0x0008UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL3SSCGR_MODPER_4 (0x0010UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL3SSCGR_MODPER_5 (0x0020UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL3SSCGR_MODPER_6 (0x0040UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL3SSCGR_MODPER_7 (0x0080UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL3SSCGR_MODPER_8 (0x0100UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL3SSCGR_MODPER_9 (0x0200UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL3SSCGR_MODPER_10 (0x0400UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL3SSCGR_MODPER_11 (0x0800UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL3SSCGR_MODPER_12 (0x1000UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL3SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL3SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL3SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL3SSCGR_TPDFNDIS RCC_PLL3SSCGR_TPDFNDIS_Msk +#define RCC_PLL3SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL3SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL3SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL3SSCGR_RPDFNDIS RCC_PLL3SSCGR_RPDFNDIS_Msk +#define RCC_PLL3SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL3SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL3SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL3SSCGR_SPREADSEL RCC_PLL3SSCGR_SPREADSEL_Msk +#define RCC_PLL3SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL3SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3SSCGR_INCSTEP RCC_PLL3SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL3SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL3SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL3SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL3SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL3SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL3SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL3SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL3SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL3SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL3SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL3SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL3SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL3SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL3SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL3SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CKPROTR register ***************/ +#define RCC_CKPROTR_XSPICKP_Pos (0U) +#define RCC_CKPROTR_XSPICKP_Msk (0x1UL << RCC_CKPROTR_XSPICKP_Pos) /*!< 0x00000001 */ +#define RCC_CKPROTR_XSPICKP RCC_CKPROTR_XSPICKP_Msk +#define RCC_CKPROTR_FMCCKP_Pos (1U) +#define RCC_CKPROTR_FMCCKP_Msk (0x1UL << RCC_CKPROTR_FMCCKP_Pos) /*!< 0x00000002 */ +#define RCC_CKPROTR_FMCCKP RCC_CKPROTR_FMCCKP_Msk +#define RCC_CKPROTR_XSPI1SWP_Pos (4U) +#define RCC_CKPROTR_XSPI1SWP_Msk (0x7UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000070 */ +#define RCC_CKPROTR_XSPI1SWP RCC_CKPROTR_XSPI1SWP_Msk +#define RCC_CKPROTR_XSPI1SWP_0 (0x1UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000010 */ +#define RCC_CKPROTR_XSPI1SWP_1 (0x2UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000020 */ +#define RCC_CKPROTR_XSPI1SWP_2 (0x4UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000040 */ +#define RCC_CKPROTR_XSPI2SWP_Pos (8U) +#define RCC_CKPROTR_XSPI2SWP_Msk (0x7UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000700 */ +#define RCC_CKPROTR_XSPI2SWP RCC_CKPROTR_XSPI2SWP_Msk +#define RCC_CKPROTR_XSPI2SWP_0 (0x1UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000100 */ +#define RCC_CKPROTR_XSPI2SWP_1 (0x2UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000200 */ +#define RCC_CKPROTR_XSPI2SWP_2 (0x4UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000400 */ +#define RCC_CKPROTR_FMCSWP_Pos (12U) +#define RCC_CKPROTR_FMCSWP_Msk (0x7UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00007000 */ +#define RCC_CKPROTR_FMCSWP RCC_CKPROTR_FMCSWP_Msk +#define RCC_CKPROTR_FMCSWP_0 (0x1UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00001000 */ +#define RCC_CKPROTR_FMCSWP_1 (0x2UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00002000 */ +#define RCC_CKPROTR_FMCSWP_2 (0x4UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_RSR register *******************/ +#define RCC_RSR_RMVF_Pos (16U) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk +#define RCC_RSR_OBLRSTF_Pos (17U) +#define RCC_RSR_OBLRSTF_Msk (0x1UL << RCC_RSR_OBLRSTF_Pos) /*!< 0x00020000 */ +#define RCC_RSR_OBLRSTF RCC_RSR_OBLRSTF_Msk +#define RCC_RSR_BORRSTF_Pos (21U) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk +#define RCC_RSR_PINRSTF_Pos (22U) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk +#define RCC_RSR_PORRSTF_Pos (23U) +#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk +#define RCC_RSR_SFTRSTF_Pos (24U) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk +#define RCC_RSR_IWDGRSTF_Pos (26U) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk +#define RCC_RSR_WWDGRSTF_Pos (28U) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk +#define RCC_RSR_LPWRRSTF_Pos (30U) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk + +/******************** Bit definition for RCC_AHB1ENR register ***************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (4U) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk +#define RCC_AHB1ENR_ADC12EN_Pos (5U) +#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk +#define RCC_AHB1ENR_ETH1MACEN_Pos (15U) +#define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk +#define RCC_AHB1ENR_ETH1TXEN_Pos (16U) +#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk +#define RCC_AHB1ENR_ETH1RXEN_Pos (17U) +#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk +#define RCC_AHB1ENR_OTGHSEN_Pos (25U) +#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk +#define RCC_AHB1ENR_USBPHYCEN_Pos (26U) +#define RCC_AHB1ENR_USBPHYCEN_Msk (0x1UL << RCC_AHB1ENR_USBPHYCEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB1ENR_USBPHYCEN RCC_AHB1ENR_USBPHYCEN_Msk +#define RCC_AHB1ENR_OTGFSEN_Pos (27U) +#define RCC_AHB1ENR_OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_OTGFSEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB1ENR_OTGFSEN RCC_AHB1ENR_OTGFSEN_Msk +#define RCC_AHB1ENR_ADF1EN_Pos (31U) +#define RCC_AHB1ENR_ADF1EN_Msk (0x1UL << RCC_AHB1ENR_ADF1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_ADF1EN RCC_AHB1ENR_ADF1EN_Msk + +/******************** Bit definition for RCC_AHB2ENR register ***************/ +#define RCC_AHB2ENR_PSSIEN_Pos (1U) +#define RCC_AHB2ENR_PSSIEN_Msk (0x1UL << RCC_AHB2ENR_PSSIEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_PSSIEN RCC_AHB2ENR_PSSIEN_Msk +#define RCC_AHB2ENR_SDMMC2EN_Pos (9U) +#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */ +#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk +#define RCC_AHB2ENR_CORDICEN_Pos (14U) +#define RCC_AHB2ENR_CORDICEN_Msk (0x1UL << RCC_AHB2ENR_CORDICEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB2ENR_CORDICEN RCC_AHB2ENR_CORDICEN_Msk +#define RCC_AHB2ENR_SRAM1EN_Pos (29U) +#define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos) /*!< 0x20000000 */ +#define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk +#define RCC_AHB2ENR_SRAM2EN_Pos (30U) +#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk + +/******************** Bit definition for RCC_AHB3ENR register ***************/ +#define RCC_AHB3ENR_RNGEN_Pos (0U) +#define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk +#define RCC_AHB3ENR_HASHEN_Pos (1U) +#define RCC_AHB3ENR_HASHEN_Msk (0x1UL << RCC_AHB3ENR_HASHEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENR_HASHEN RCC_AHB3ENR_HASHEN_Msk +#define RCC_AHB3ENR_PKAEN_Pos (6U) +#define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk + +/******************** Bit definition for RCC_AHB4ENR register ***************/ +#define RCC_AHB4ENR_GPIOAEN_Pos (0U) +#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk +#define RCC_AHB4ENR_GPIOBEN_Pos (1U) +#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk +#define RCC_AHB4ENR_GPIOCEN_Pos (2U) +#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk +#define RCC_AHB4ENR_GPIODEN_Pos (3U) +#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk +#define RCC_AHB4ENR_GPIOEEN_Pos (4U) +#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk +#define RCC_AHB4ENR_GPIOFEN_Pos (5U) +#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk +#define RCC_AHB4ENR_GPIOGEN_Pos (6U) +#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk +#define RCC_AHB4ENR_GPIOHEN_Pos (7U) +#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk +#define RCC_AHB4ENR_GPIOMEN_Pos (12U) +#define RCC_AHB4ENR_GPIOMEN_Msk (0x1UL << RCC_AHB4ENR_GPIOMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB4ENR_GPIOMEN RCC_AHB4ENR_GPIOMEN_Msk +#define RCC_AHB4ENR_GPIONEN_Pos (13U) +#define RCC_AHB4ENR_GPIONEN_Msk (0x1UL << RCC_AHB4ENR_GPIONEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENR_GPIONEN RCC_AHB4ENR_GPIONEN_Msk +#define RCC_AHB4ENR_GPIOOEN_Pos (14U) +#define RCC_AHB4ENR_GPIOOEN_Msk (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENR_GPIOOEN RCC_AHB4ENR_GPIOOEN_Msk +#define RCC_AHB4ENR_GPIOPEN_Pos (15U) +#define RCC_AHB4ENR_GPIOPEN_Msk (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENR_GPIOPEN RCC_AHB4ENR_GPIOPEN_Msk +#define RCC_AHB4ENR_CRCEN_Pos (19U) +#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk +#define RCC_AHB4ENR_BKPRAMEN_Pos (28U) +#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk + +/******************** Bit definition for RCC_AHB5ENR register ***************/ +#define RCC_AHB5ENR_HPDMA1EN_Pos (0U) +#define RCC_AHB5ENR_HPDMA1EN_Msk (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_HPDMA1EN RCC_AHB5ENR_HPDMA1EN_Msk +#define RCC_AHB5ENR_DMA2DEN_Pos (1U) +#define RCC_AHB5ENR_DMA2DEN_Msk (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENR_DMA2DEN RCC_AHB5ENR_DMA2DEN_Msk +#define RCC_AHB5ENR_JPEGEN_Pos (3U) +#define RCC_AHB5ENR_JPEGEN_Msk (0x1UL << RCC_AHB5ENR_JPEGEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENR_JPEGEN RCC_AHB5ENR_JPEGEN_Msk +#define RCC_AHB5ENR_FMCEN_Pos (4U) +#define RCC_AHB5ENR_FMCEN_Msk (0x1UL << RCC_AHB5ENR_FMCEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENR_FMCEN RCC_AHB5ENR_FMCEN_Msk +#define RCC_AHB5ENR_XSPI1EN_Pos (5U) +#define RCC_AHB5ENR_XSPI1EN_Msk (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENR_XSPI1EN RCC_AHB5ENR_XSPI1EN_Msk +#define RCC_AHB5ENR_SDMMC1EN_Pos (8U) +#define RCC_AHB5ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENR_SDMMC1EN RCC_AHB5ENR_SDMMC1EN_Msk +#define RCC_AHB5ENR_XSPI2EN_Pos (12U) +#define RCC_AHB5ENR_XSPI2EN_Msk (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENR_XSPI2EN RCC_AHB5ENR_XSPI2EN_Msk +#define RCC_AHB5ENR_XSPIMEN_Pos (14U) +#define RCC_AHB5ENR_XSPIMEN_Msk (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5ENR_XSPIMEN RCC_AHB5ENR_XSPIMEN_Msk +#define RCC_AHB5ENR_GFXMMUEN_Pos (19U) +#define RCC_AHB5ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENR_GFXMMUEN RCC_AHB5ENR_GFXMMUEN_Msk +#define RCC_AHB5ENR_GPU2DEN_Pos (20U) +#define RCC_AHB5ENR_GPU2DEN_Msk (0x1UL << RCC_AHB5ENR_GPU2DEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENR_GPU2DEN RCC_AHB5ENR_GPU2DEN_Msk + +/******************** Bit definition for RCC_APB1ENR1 register **************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0U) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk +#define RCC_APB1ENR1_TIM3EN_Pos (1U) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk +#define RCC_APB1ENR1_TIM4EN_Pos (2U) +#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk +#define RCC_APB1ENR1_TIM5EN_Pos (3U) +#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk +#define RCC_APB1ENR1_TIM6EN_Pos (4U) +#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk +#define RCC_APB1ENR1_TIM7EN_Pos (5U) +#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk +#define RCC_APB1ENR1_TIM12EN_Pos (6U) +#define RCC_APB1ENR1_TIM12EN_Msk (0x1UL << RCC_APB1ENR1_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENR1_TIM12EN RCC_APB1ENR1_TIM12EN_Msk +#define RCC_APB1ENR1_TIM13EN_Pos (7U) +#define RCC_APB1ENR1_TIM13EN_Msk (0x1UL << RCC_APB1ENR1_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENR1_TIM13EN RCC_APB1ENR1_TIM13EN_Msk +#define RCC_APB1ENR1_TIM14EN_Pos (8U) +#define RCC_APB1ENR1_TIM14EN_Msk (0x1UL << RCC_APB1ENR1_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR1_TIM14EN RCC_APB1ENR1_TIM14EN_Msk +#define RCC_APB1ENR1_LPTIM1EN_Pos (9U) +#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk +#define RCC_APB1ENR1_WWDGEN_Pos (11U) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk +#define RCC_APB1ENR1_SPI2EN_Pos (14U) +#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk +#define RCC_APB1ENR1_SPI3EN_Pos (15U) +#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk +#define RCC_APB1ENR1_SPDIFRXEN_Pos (16U) +#define RCC_APB1ENR1_SPDIFRXEN_Msk (0x1UL << RCC_APB1ENR1_SPDIFRXEN_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENR1_SPDIFRXEN RCC_APB1ENR1_SPDIFRXEN_Msk +#define RCC_APB1ENR1_USART2EN_Pos (17U) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk +#define RCC_APB1ENR1_USART3EN_Pos (18U) +#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk +#define RCC_APB1ENR1_UART4EN_Pos (19U) +#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk +#define RCC_APB1ENR1_UART5EN_Pos (20U) +#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk +#define RCC_APB1ENR1_I2C1_I3C1EN_Pos (21U) +#define RCC_APB1ENR1_I2C1_I3C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1_I3C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1_I3C1EN RCC_APB1ENR1_I2C1_I3C1EN_Msk +#define RCC_APB1ENR1_I2C2EN_Pos (22U) +#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk +#define RCC_APB1ENR1_I2C3EN_Pos (23U) +#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk +#define RCC_APB1ENR1_CECEN_Pos (27U) +#define RCC_APB1ENR1_CECEN_Msk (0x1UL << RCC_APB1ENR1_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR1_CECEN RCC_APB1ENR1_CECEN_Msk +#define RCC_APB1ENR1_UART7EN_Pos (30U) +#define RCC_APB1ENR1_UART7EN_Msk (0x1UL << RCC_APB1ENR1_UART7EN_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENR1_UART7EN RCC_APB1ENR1_UART7EN_Msk +#define RCC_APB1ENR1_UART8EN_Pos (31U) +#define RCC_APB1ENR1_UART8EN_Msk (0x1UL << RCC_APB1ENR1_UART8EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR1_UART8EN RCC_APB1ENR1_UART8EN_Msk + +/******************** Bit definition for RCC_APB1ENR2 register **************/ +#define RCC_APB1ENR2_CRSEN_Pos (1U) +#define RCC_APB1ENR2_CRSEN_Msk (0x1UL << RCC_APB1ENR2_CRSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR2_CRSEN RCC_APB1ENR2_CRSEN_Msk +#define RCC_APB1ENR2_MDIOSEN_Pos (5U) +#define RCC_APB1ENR2_MDIOSEN_Msk (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_MDIOSEN RCC_APB1ENR2_MDIOSEN_Msk +#define RCC_APB1ENR2_FDCANEN_Pos (8U) +#define RCC_APB1ENR2_FDCANEN_Msk (0x1UL << RCC_APB1ENR2_FDCANEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR2_FDCANEN RCC_APB1ENR2_FDCANEN_Msk +#define RCC_APB1ENR2_UCPD1EN_Pos (27U) +#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk + +/******************** Bit definition for RCC_APB2ENR register ***************/ +#define RCC_APB2ENR_TIM1EN_Pos (0U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk +#define RCC_APB2ENR_USART1EN_Pos (4U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk +#define RCC_APB2ENR_SPI4EN_Pos (13U) +#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk +#define RCC_APB2ENR_TIM9EN_Pos (19U) +#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk +#define RCC_APB2ENR_SPI5EN_Pos (20U) +#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk +#define RCC_APB2ENR_SAI1EN_Pos (22U) +#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk +#define RCC_APB2ENR_SAI2EN_Pos (23U) +#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */ +#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk + +/******************** Bit definition for RCC_APB4ENR register ***************/ +#define RCC_APB4ENR_SBSEN_Pos (1U) +#define RCC_APB4ENR_SBSEN_Msk (0x1UL << RCC_APB4ENR_SBSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENR_SBSEN RCC_APB4ENR_SBSEN_Msk +#define RCC_APB4ENR_LPUART1EN_Pos (3U) +#define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk +#define RCC_APB4ENR_SPI6EN_Pos (5U) +#define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk +#define RCC_APB4ENR_LPTIM2EN_Pos (9U) +#define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */ +#define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk +#define RCC_APB4ENR_LPTIM3EN_Pos (10U) +#define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */ +#define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk +#define RCC_APB4ENR_LPTIM4EN_Pos (11U) +#define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */ +#define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk +#define RCC_APB4ENR_LPTIM5EN_Pos (12U) +#define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */ +#define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk +#define RCC_APB4ENR_VREFEN_Pos (15U) +#define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk +#define RCC_APB4ENR_RTCAPBEN_Pos (16U) +#define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk +#define RCC_APB4ENR_DTSEN_Pos (26U) +#define RCC_APB4ENR_DTSEN_Msk (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */ +#define RCC_APB4ENR_DTSEN RCC_APB4ENR_DTSEN_Msk + +/******************** Bit definition for RCC_APB5ENR register ***************/ +#define RCC_APB5ENR_LTDCEN_Pos (1U) +#define RCC_APB5ENR_LTDCEN_Msk (0x1UL << RCC_APB5ENR_LTDCEN_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENR_LTDCEN RCC_APB5ENR_LTDCEN_Msk +#define RCC_APB5ENR_DCMIPPEN_Pos (2U) +#define RCC_APB5ENR_DCMIPPEN_Msk (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENR_DCMIPPEN RCC_APB5ENR_DCMIPPEN_Msk +#define RCC_APB5ENR_GFXTIMEN_Pos (4U) +#define RCC_APB5ENR_GFXTIMEN_Msk (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENR_GFXTIMEN RCC_APB5ENR_GFXTIMEN_Msk + +/******************** Bit definition for RCC_AHB1LPENR register *************/ +#define RCC_AHB1LPENR_GPDMA1LPEN_Pos (4U) +#define RCC_AHB1LPENR_GPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENR_GPDMA1LPEN RCC_AHB1LPENR_GPDMA1LPEN_Msk +#define RCC_AHB1LPENR_ADC12LPEN_Pos (5U) +#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk +#define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U) +#define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk +#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U) +#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk +#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U) +#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk +#define RCC_AHB1LPENR_UCPDCTRL_Pos (24U) +#define RCC_AHB1LPENR_UCPDCTRL_Msk (0x1UL << RCC_AHB1LPENR_UCPDCTRL_Pos) /*!< 0x01000000 */ +#define RCC_AHB1LPENR_UCPDCTRL RCC_AHB1LPENR_UCPDCTRL_Msk +#define RCC_AHB1LPENR_OTGHSLPEN_Pos (25U) +#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk +#define RCC_AHB1LPENR_USBPHYCLPEN_Pos (26U) +#define RCC_AHB1LPENR_USBPHYCLPEN_Msk (0x1UL << RCC_AHB1LPENR_USBPHYCLPEN_Pos)/*!< 0x04000000 */ +#define RCC_AHB1LPENR_USBPHYCLPEN RCC_AHB1LPENR_USBPHYCLPEN_Msk +#define RCC_AHB1LPENR_OTGFSLPEN_Pos (27U) +#define RCC_AHB1LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGFSLPEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB1LPENR_OTGFSLPEN RCC_AHB1LPENR_OTGFSLPEN_Msk +#define RCC_AHB1LPENR_ADF1LPEN_Pos (31U) +#define RCC_AHB1LPENR_ADF1LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADF1LPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1LPENR_ADF1LPEN RCC_AHB1LPENR_ADF1LPEN_Msk + +/******************** Bit definition for RCC_AHB2LPENR register *************/ +#define RCC_AHB2LPENR_PSSILPEN_Pos (1U) +#define RCC_AHB2LPENR_PSSILPEN_Msk (0x1UL << RCC_AHB2LPENR_PSSILPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2LPENR_PSSILPEN RCC_AHB2LPENR_PSSILPEN_Msk +#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U) +#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk +#define RCC_AHB2LPENR_CORDICLPEN_Pos (14U) +#define RCC_AHB2LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB2LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB2LPENR_CORDICLPEN RCC_AHB2LPENR_CORDICLPEN_Msk +#define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U) +#define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk +#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U) +#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk + +/******************** Bit definition for RCC_AHB3LPENR register *************/ +#define RCC_AHB3LPENR_RNGLPEN_Pos (0U) +#define RCC_AHB3LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3LPENR_RNGLPEN RCC_AHB3LPENR_RNGLPEN_Msk +#define RCC_AHB3LPENR_HASHLPEN_Pos (1U) +#define RCC_AHB3LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENR_HASHLPEN RCC_AHB3LPENR_HASHLPEN_Msk +#define RCC_AHB3LPENR_PKALPEN_Pos (6U) +#define RCC_AHB3LPENR_PKALPEN_Msk (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB3LPENR_PKALPEN RCC_AHB3LPENR_PKALPEN_Msk + +/******************** Bit definition for RCC_AHB4LPENR register *************/ +#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk +#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk +#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk +#define RCC_AHB4LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk +#define RCC_AHB4LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk +#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U) +#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk +#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U) +#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk +#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk +#define RCC_AHB4LPENR_GPIOMLPEN_Pos (12U) +#define RCC_AHB4LPENR_GPIOMLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOMLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB4LPENR_GPIOMLPEN RCC_AHB4LPENR_GPIOMLPEN_Msk +#define RCC_AHB4LPENR_GPIONLPEN_Pos (13U) +#define RCC_AHB4LPENR_GPIONLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENR_GPIONLPEN RCC_AHB4LPENR_GPIONLPEN_Msk +#define RCC_AHB4LPENR_GPIOOLPEN_Pos (14U) +#define RCC_AHB4LPENR_GPIOOLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENR_GPIOOLPEN RCC_AHB4LPENR_GPIOOLPEN_Msk +#define RCC_AHB4LPENR_GPIOPLPEN_Pos (15U) +#define RCC_AHB4LPENR_GPIOPLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENR_GPIOPLPEN RCC_AHB4LPENR_GPIOPLPEN_Msk +#define RCC_AHB4LPENR_CRCLPEN_Pos (19U) +#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk +#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U) +#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk + +/******************** Bit definition for RCC_AHB5LPENR register *************/ +#define RCC_AHB5LPENR_HPDMA1LPEN_Pos (0U) +#define RCC_AHB5LPENR_HPDMA1LPEN_Msk (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENR_HPDMA1LPEN RCC_AHB5LPENR_HPDMA1LPEN_Msk +#define RCC_AHB5LPENR_DMA2DLPEN_Pos (1U) +#define RCC_AHB5LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENR_DMA2DLPEN RCC_AHB5LPENR_DMA2DLPEN_Msk +#define RCC_AHB5LPENR_FLASHLPEN_Pos (2U) +#define RCC_AHB5LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB5LPENR_FLASHLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB5LPENR_FLASHLPEN RCC_AHB5LPENR_FLASHLPEN_Msk +#define RCC_AHB5LPENR_JPEGLPEN_Pos (3U) +#define RCC_AHB5LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENR_JPEGLPEN RCC_AHB5LPENR_JPEGLPEN_Msk +#define RCC_AHB5LPENR_FMCLPEN_Pos (4U) +#define RCC_AHB5LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5LPENR_FMCLPEN RCC_AHB5LPENR_FMCLPEN_Msk +#define RCC_AHB5LPENR_XSPI1LPEN_Pos (5U) +#define RCC_AHB5LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENR_XSPI1LPEN RCC_AHB5LPENR_XSPI1LPEN_Msk +#define RCC_AHB5LPENR_SDMMC1LPEN_Pos (8U) +#define RCC_AHB5LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENR_SDMMC1LPEN RCC_AHB5LPENR_SDMMC1LPEN_Msk +#define RCC_AHB5LPENR_XSPI2LPEN_Pos (12U) +#define RCC_AHB5LPENR_XSPI2LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENR_XSPI2LPEN RCC_AHB5LPENR_XSPI2LPEN_Msk +#define RCC_AHB5LPENR_XSPIMLPEN_Pos (14U) +#define RCC_AHB5LPENR_XSPIMLPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5LPENR_XSPIMLPEN RCC_AHB5LPENR_XSPIMLPEN_Msk +#define RCC_AHB5LPENR_GFXMMULPEN_Pos (19U) +#define RCC_AHB5LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENR_GFXMMULPEN RCC_AHB5LPENR_GFXMMULPEN_Msk +#define RCC_AHB5LPENR_GPU2DLPEN_Pos (20U) +#define RCC_AHB5LPENR_GPU2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_GPU2DLPEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB5LPENR_GPU2DLPEN RCC_AHB5LPENR_GPU2DLPEN_Msk +#define RCC_AHB5LPENR_DTCM1LPEN_Pos (28U) +#define RCC_AHB5LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB5LPENR_DTCM1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENR_DTCM1LPEN RCC_AHB5LPENR_DTCM1LPEN_Msk +#define RCC_AHB5LPENR_DTCM2LPEN_Pos (29U) +#define RCC_AHB5LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB5LPENR_DTCM2LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENR_DTCM2LPEN RCC_AHB5LPENR_DTCM2LPEN_Msk +#define RCC_AHB5LPENR_ITCMLPEN_Pos (30U) +#define RCC_AHB5LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB5LPENR_ITCMLPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB5LPENR_ITCMLPEN RCC_AHB5LPENR_ITCMLPEN_Msk +#define RCC_AHB5LPENR_AXISRAMLPEN_Pos (31U) +#define RCC_AHB5LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB5LPENR_AXISRAMLPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB5LPENR_AXISRAMLPEN RCC_AHB5LPENR_AXISRAMLPEN_Msk + +/******************** Bit definition for RCC_APB1LPENR1 register ************/ +#define RCC_APB1LPENR1_TIM2LPEN_Pos (0U) +#define RCC_APB1LPENR1_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENR1_TIM2LPEN RCC_APB1LPENR1_TIM2LPEN_Msk +#define RCC_APB1LPENR1_TIM3LPEN_Pos (1U) +#define RCC_APB1LPENR1_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENR1_TIM3LPEN RCC_APB1LPENR1_TIM3LPEN_Msk +#define RCC_APB1LPENR1_TIM4LPEN_Pos (2U) +#define RCC_APB1LPENR1_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENR1_TIM4LPEN RCC_APB1LPENR1_TIM4LPEN_Msk +#define RCC_APB1LPENR1_TIM5LPEN_Pos (3U) +#define RCC_APB1LPENR1_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENR1_TIM5LPEN RCC_APB1LPENR1_TIM5LPEN_Msk +#define RCC_APB1LPENR1_TIM6LPEN_Pos (4U) +#define RCC_APB1LPENR1_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENR1_TIM6LPEN RCC_APB1LPENR1_TIM6LPEN_Msk +#define RCC_APB1LPENR1_TIM7LPEN_Pos (5U) +#define RCC_APB1LPENR1_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR1_TIM7LPEN RCC_APB1LPENR1_TIM7LPEN_Msk +#define RCC_APB1LPENR1_TIM12LPEN_Pos (6U) +#define RCC_APB1LPENR1_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENR1_TIM12LPEN RCC_APB1LPENR1_TIM12LPEN_Msk +#define RCC_APB1LPENR1_TIM13LPEN_Pos (7U) +#define RCC_APB1LPENR1_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENR1_TIM13LPEN RCC_APB1LPENR1_TIM13LPEN_Msk +#define RCC_APB1LPENR1_TIM14LPEN_Pos (8U) +#define RCC_APB1LPENR1_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR1_TIM14LPEN RCC_APB1LPENR1_TIM14LPEN_Msk +#define RCC_APB1LPENR1_LPTIM1LPEN_Pos (9U) +#define RCC_APB1LPENR1_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos)/*!< 0x00000200 */ +#define RCC_APB1LPENR1_LPTIM1LPEN RCC_APB1LPENR1_LPTIM1LPEN_Msk +#define RCC_APB1LPENR1_WWDGLPEN_Pos (11U) +#define RCC_APB1LPENR1_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENR1_WWDGLPEN RCC_APB1LPENR1_WWDGLPEN_Msk +#define RCC_APB1LPENR1_SPI2LPEN_Pos (14U) +#define RCC_APB1LPENR1_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENR1_SPI2LPEN RCC_APB1LPENR1_SPI2LPEN_Msk +#define RCC_APB1LPENR1_SPI3LPEN_Pos (15U) +#define RCC_APB1LPENR1_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENR1_SPI3LPEN RCC_APB1LPENR1_SPI3LPEN_Msk +#define RCC_APB1LPENR1_SPDIFRXLPEN_Pos (16U) +#define RCC_APB1LPENR1_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LPENR1_SPDIFRXLPEN_Pos)/*!< 0x00010000 */ +#define RCC_APB1LPENR1_SPDIFRXLPEN RCC_APB1LPENR1_SPDIFRXLPEN_Msk +#define RCC_APB1LPENR1_USART2LPEN_Pos (17U) +#define RCC_APB1LPENR1_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos)/*!< 0x00020000 */ +#define RCC_APB1LPENR1_USART2LPEN RCC_APB1LPENR1_USART2LPEN_Msk +#define RCC_APB1LPENR1_USART3LPEN_Pos (18U) +#define RCC_APB1LPENR1_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos)/*!< 0x00040000 */ +#define RCC_APB1LPENR1_USART3LPEN RCC_APB1LPENR1_USART3LPEN_Msk +#define RCC_APB1LPENR1_UART4LPEN_Pos (19U) +#define RCC_APB1LPENR1_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENR1_UART4LPEN RCC_APB1LPENR1_UART4LPEN_Msk +#define RCC_APB1LPENR1_UART5LPEN_Pos (20U) +#define RCC_APB1LPENR1_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENR1_UART5LPEN RCC_APB1LPENR1_UART5LPEN_Msk +#define RCC_APB1LPENR1_I2C1_I3C1LPEN_Pos (21U) +#define RCC_APB1LPENR1_I2C1_I3C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C1_I3C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENR1_I2C1_I3C1LPEN RCC_APB1LPENR1_I2C1_I3C1LPEN_Msk +#define RCC_APB1LPENR1_I2C2LPEN_Pos (22U) +#define RCC_APB1LPENR1_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENR1_I2C2LPEN RCC_APB1LPENR1_I2C2LPEN_Msk +#define RCC_APB1LPENR1_I2C3LPEN_Pos (23U) +#define RCC_APB1LPENR1_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENR1_I2C3LPEN RCC_APB1LPENR1_I2C3LPEN_Msk +#define RCC_APB1LPENR1_CECLPEN_Pos (27U) +#define RCC_APB1LPENR1_CECLPEN_Msk (0x1UL << RCC_APB1LPENR1_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1LPENR1_CECLPEN RCC_APB1LPENR1_CECLPEN_Msk +#define RCC_APB1LPENR1_UART7LPEN_Pos (30U) +#define RCC_APB1LPENR1_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENR1_UART7LPEN RCC_APB1LPENR1_UART7LPEN_Msk +#define RCC_APB1LPENR1_UART8LPEN_Pos (31U) +#define RCC_APB1LPENR1_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENR1_UART8LPEN RCC_APB1LPENR1_UART8LPEN_Msk + +/******************** Bit definition for RCC_PB1LPENR2 register ************/ +#define RCC_APB1LPENR2_CRSLPEN_Pos (1U) +#define RCC_APB1LPENR2_CRSLPEN_Msk (0x1UL << RCC_APB1LPENR2_CRSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENR2_CRSLPEN RCC_APB1LPENR2_CRSLPEN_Msk +#define RCC_APB1LPENR2_MDIOSLPEN_Pos (5U) +#define RCC_APB1LPENR2_MDIOSLPEN_Msk (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR2_MDIOSLPEN RCC_APB1LPENR2_MDIOSLPEN_Msk +#define RCC_APB1LPENR2_FDCANLPEN_Pos (8U) +#define RCC_APB1LPENR2_FDCANLPEN_Msk (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR2_FDCANLPEN RCC_APB1LPENR2_FDCANLPEN_Msk +#define RCC_APB1LPENR2_UCPD1LPEN_Pos (27U) +#define RCC_APB1LPENR2_UCPD1LPEN_Msk (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1LPENR2_UCPD1LPEN RCC_APB1LPENR2_UCPD1LPEN_Msk + +/******************** Bit definition for RCC_APB2LPENR register *************/ +#define RCC_APB2LPENR_TIM1LPEN_Pos (0U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk +#define RCC_APB2LPENR_USART1LPEN_Pos (4U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk +#define RCC_APB2LPENR_SPI4LPEN_Pos (13U) +#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk +#define RCC_APB2LPENR_TIM15LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk +#define RCC_APB2LPENR_TIM16LPEN_Pos (17U) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk +#define RCC_APB2LPENR_TIM17LPEN_Pos (18U) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk +#define RCC_APB2LPENR_TIM9LPEN_Pos (19U) +#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk +#define RCC_APB2LPENR_SPI5LPEN_Pos (20U) +#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk +#define RCC_APB2LPENR_SAI1LPEN_Pos (22U) +#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk +#define RCC_APB2LPENR_SAI2LPEN_Pos (23U) +#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk + +/******************** Bit definition for RCC_APB4LPENR register *************/ +#define RCC_APB4LPENR_SBSLPEN_Pos (1U) +#define RCC_APB4LPENR_SBSLPEN_Msk (0x1UL << RCC_APB4LPENR_SBSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENR_SBSLPEN RCC_APB4LPENR_SBSLPEN_Msk +#define RCC_APB4LPENR_LPUART1LPEN_Pos (3U) +#define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos)/*!< 0x00000008 */ +#define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk +#define RCC_APB4LPENR_SPI6LPEN_Pos (5U) +#define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk +#define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U) +#define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk +#define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U) +#define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk +#define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U) +#define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk +#define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U) +#define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk +#define RCC_APB4LPENR_VREFLPEN_Pos (15U) +#define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk +#define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U) +#define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk +#define RCC_APB4LPENR_DTSLPEN_Pos (26U) +#define RCC_APB4LPENR_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */ +#define RCC_APB4LPENR_DTSLPEN RCC_APB4LPENR_DTSLPEN_Msk + +/******************** Bit definition for RCC_APB5LPENR register *************/ +#define RCC_APB5LPENR_LTDCLPEN_Pos (1U) +#define RCC_APB5LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB5LPENR_LTDCLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENR_LTDCLPEN RCC_APB5LPENR_LTDCLPEN_Msk +#define RCC_APB5LPENR_DCMIPPLPEN_Pos (2U) +#define RCC_APB5LPENR_DCMIPPLPEN_Msk (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENR_DCMIPPLPEN RCC_APB5LPENR_DCMIPPLPEN_Msk +#define RCC_APB5LPENR_GFXTIMLPEN_Pos (4U) +#define RCC_APB5LPENR_GFXTIMLPEN_Msk (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENR_GFXTIMLPEN RCC_APB5LPENR_GFXTIMLPEN_Msk + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! /*!< ARM Cortex-M7 processor and core peripherals */ +#include "system_stm32h7rsxx.h" /*!< STM32H7RSxx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H7RSxx_peripherals + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[4];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t OR; /*!< ADC option register, Address offset: 0xC8 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief AXIM ASIB + */ +typedef struct +{ + uint32_t RESERVED1[9]; /*!< Reserved, Address offset: 0x00-0x20 */ + __IO uint32_t FNMOD2; /*!< AXIM ASIB fn_mod2 register Address offset: 0x24 */ + uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x28-0xFC */ + __IO uint32_t READQOS; /*!< AXIM ASIB read_qos register Address offset: 0x100 */ + __IO uint32_t WRITEQOS; /*!< AXIM ASIB write_qos register Address offset: 0x104 */ + __IO uint32_t FNMOD; /*!< AXIM ASIB fn_mod register Address offset: 0x108 */ +} AXIM_ASIB_TypeDef; + +typedef struct +{ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x00-0x04 */ + __IO uint32_t FNMODBMISS; /*!< AXIM AMIB fn_mod_bm_iss register Address offset: 0x08 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x0C-0x20 */ + __IO uint32_t FNMOD2; /*!< AXIM AMIB fn_mod2 register Address offset: 0x24 */ + uint32_t RESERVED3[1]; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t FNMODLB; /*!< AXIM AMIB fn_mod_lb register Address offset: 0x2C */ + uint32_t RESERVED5[54]; /*!< Reserved, Address offset: 0x30-0x104 */ + __IO uint32_t FNMOD; /*!< AXIM AMIB fn_mod register Address offset: 0x108 */ +} AXIM_AMIB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +} CEC_TypeDef; + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC Control and Status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief GFXTIM + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXTIM configuration register, Address offset: 0x00 */ + __IO uint32_t CGCR; /*!< GFXTIM clock generator configuration register, Address offset: 0x04 */ + __IO uint32_t TCR; /*!< GFXTIM timers configuration register, Address offset: 0x08 */ + __IO uint32_t TDR; /*!< GFXTIM timers disable register, Address offset: 0x0C */ + __IO uint32_t EVCR; /*!< GFXTIM events control register, Address offset: 0x10 */ + __IO uint32_t EVSR; /*!< GFXTIM events selection register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WDGTCR; /*!< GFXTIM watchdog timer configuration register, Address offset: 0x20 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t ISR; /*!< GFXTIM interrupt status register, Address offset: 0x30 */ + __IO uint32_t ICR; /*!< GFXTIM interrupt clear register, Address offset: 0x34 */ + __IO uint32_t IER; /*!< GFXTIM interrupt enable register, Address offset: 0x38 */ + __IO uint32_t TSR; /*!< GFXTIM timers status register, Address offset: 0x3C */ + __IO uint32_t LCCRR; /*!< GFXTIM line clock counter reload register, Address offset: 0x40 */ + __IO uint32_t FCCRR; /*!< GFXTIM frame clock counter reload register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48-0x4C */ + __IO uint32_t ATR; /*!< GFXTIM absolute time register, Address offset: 0x50 */ + __IO uint32_t AFCR; /*!< GFXTIM absolute frame counter register, Address offset: 0x54 */ + __IO uint32_t ALCR; /*!< GFXTIM absolute line counter register, Address offset: 0x58 */ + uint32_t RESERVED4[1]; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t AFCC1R; /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */ + uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x64-0X6C */ + __IO uint32_t ALCC1R; /*!< GFXTIM absolute line counter compare 1 register, Address offset: 0x70 */ + __IO uint32_t ALCC2R; /*!< GFXTIM absolute line counter compare 2 register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x78-0X7C */ + __IO uint32_t RFC1R; /*!< GFXTIM relative frame counter 1 register, Address offset: 0x80 */ + __IO uint32_t RFC1RR; /*!< GFXTIM relative frame counter 1 reload register, Address offset: 0x84 */ + __IO uint32_t RFC2R; /*!< GFXTIM relative frame counter 2 register, Address offset: 0x88 */ + __IO uint32_t RFC2RR; /*!< GFXTIM relative frame counter 2 reload register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x90-0X9C */ + __IO uint32_t WDGCR; /*!< GFXTIM watchdog counter register, Address offset: 0xA0 */ + __IO uint32_t WDGRR; /*!< GFXTIM watchdog reload register, Address offset: 0xA4 */ + __IO uint32_t WDGPAR; /*!< GFXTIM watchdog pre-alarm register, Address offset: 0xA8 */ + uint32_t RESERVED8[209]; /*!< Reserved, Address offset: 0xAC-0X3EC */ + __IO uint32_t HWCFGR; /*!< GFXTIM HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GFXTIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GFXTIM identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GFXTIM size identification register, Address offset: 0x3FC */ +} GFXTIM_TypeDef; + + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Cryp Processor + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ +} CRYP_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t AHB5FZR; /*!< Debug MCU AHB5FZR freeze register, Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1FZR freeze register, Address offset: 0x24 */ + uint32_t RESERVED3[5]; /*!< Reserved, Address offset: 0x28-0x38 */ + __IO uint32_t APB1FZR; /*!< Debug MCU APB1FZR freeze register, Address offset: 0x3C */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x40-0x48 */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2FZR freeze register, Address offset: 0x4C */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZR; /*!< Debug MCU APB4FZR freeze register, Address offset: 0x54 */ + uint32_t RESERVED6[41]; /*!< Reserved, Address offset: 0x58-0xF8 */ + __IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU Authentication Host register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug MCU Authentication Device register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug MCU Authentication Ack register, Address offset: 0x108 */ + uint32_t RESERVED7[945]; /*!< Reserved, Address offset: 0x10C-0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU peripheral identity register 4, Address offset: 0xFD0 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0xFD4-0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMIPP + */ +typedef struct +{ + __IO uint32_t IPGR1; /*!< IP-Plug global register 1 Address offset: 0x00 */ + __IO uint32_t IPGR2; /*!< IP-Plug global register 2 Address offset: 0x04 */ + __IO uint32_t IPGR3; /*!< IP-Plug global register 3 Address offset: 0x08 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x0C-0x18 */ + __IO uint32_t IPGR8; /*!< IP-Plug global register 8 Address offset: 0x1C */ + __IO uint32_t IPC1R1; /*!< IP-Plug client 1 register 1 Address offset: 0x20 */ + __IO uint32_t IPC1R2; /*!< IP-Plug client 1 register 2 Address offset: 0x24 */ + __IO uint32_t IPC1R3; /*!< IP-Plug client 1 register 3 Address offset: 0x28 */ + __IO uint32_t RESERVED2[54]; /*!< Reserved, Address offset: 0x2C-0x100 */ + __IO uint32_t PRCR; /*!< Parallel interface control register Address offset: 0x104 */ + __IO uint32_t PRESCR; /*!< Parallel interface embedded sync code register Address offset: 0x108 */ + __IO uint32_t PRESUR; /*!< Parallel interface embedded sync unmask register Address offset: 0x10C */ + __IO uint32_t RESERVED3[57]; /*!< Reserved, Address offset: 0x110-0x1F0 */ + __IO uint32_t PRIER; /*!< Parallel interface interrupt enable register Address offset: 0x1F4 */ + __IO uint32_t PRSR; /*!< Parallel interface status register Address offset: 0x1F8 */ + __IO uint32_t PRFCR; /*!< Parallel interface interrupt clear register Address offset: 0x1FC */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x200 */ + __IO uint32_t CMCR; /*!< Common configuration register Address offset: 0x204 */ + __IO uint32_t CMFRCR; /*!< Common frame counter register Address offset: 0x208 */ + __IO uint32_t RESERVED5[121]; /*!< Reserved, Address offset: 0x20C-0x3EC */ + __IO uint32_t CMIER; /*!< Common interrupt enable register Address offset: 0x3F0 */ + __IO uint32_t CMSR1; /*!< Common status register 1 Address offset: 0x3F4 */ + __IO uint32_t CMSR2; /*!< Common status register 2 Address offset: 0x3F8 */ + __IO uint32_t CMFCR; /*!< Common interrupt clear register Address offset: 0x3FC */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x400 */ + __IO uint32_t P0FSCR; /*!< Pipe0 flow selection configuration register Address offset: 0x404 */ + __IO uint32_t RESERVED7[62]; /*!< Reserved, Address offset: 0x408-0x4FC */ + __IO uint32_t P0FCTCR; /*!< Pipe0 flow control configuration register Address offset: 0x500 */ + __IO uint32_t P0SCSTR; /*!< Pipe0 stat/crop start register Address offset: 0x504 */ + __IO uint32_t P0SCSZR; /*!< Pipe0 stat/crop size register Address offset: 0x508 */ + __IO uint32_t RESERVED8[41]; /*!< Reserved, Address offset: 0x50C-0x5AC */ + __IO uint32_t P0DCCNTR; /*!< Pipe0 dump counter register Address offset: 0x5B0 */ + __IO uint32_t P0DCLMTR; /*!< Pipe0 dump limit register Address offset: 0x5B4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x5B8-0x5BC */ + __IO uint32_t P0PPCR; /*!< Pipe0 pixel packer configuration register Address offset: 0x5C0 */ + __IO uint32_t P0PPM0AR1; /*!< Pipe0 pixel packer memory0 address register 1 Address offset: 0x5C4 */ + __IO uint32_t P0PPM0AR2; /*!< Pipe0 pixel packer memory0 address register 2 Address offset: 0x5C8 */ + __IO uint32_t RESERVED10[10]; /*!< Reserved, Address offset: 0x5CC-0x5F0 */ + __IO uint32_t P0IER; /*!< Pipe0 interrupt enable register Address offset: 0x5F4 */ + __IO uint32_t P0SR; /*!< Pipe0 status register Address offset: 0x5F8 */ + __IO uint32_t P0FCR; /*!< Pipe0 interrupt clear register Address offset: 0x5FC */ + __IO uint32_t RESERVED11[64]; /*!< Reserved, Address offset: 0x600-0x6FC */ + __IO uint32_t P0CFCTCR; /*!< Pipe0 current flow control configuration register Address offset: 0x700 */ + __IO uint32_t P0CSCSTR; /*!< Pipe0 current stat/crop start register Address offset: 0x704 */ + __IO uint32_t P0CSCSZR; /*!< Pipe0 current stat/crop size register Address offset: 0x708 */ + __IO uint32_t RESERVED12[45]; /*!< Reserved, Address offset: 0x70C-0x7BC */ + __IO uint32_t P0CPPCR; /*!< Pipe0 current pixel packer configuration register Address offset: 0x700 */ + __IO uint32_t P0CPPM0AR1; /*!< Pipe0 current pixel packer memory0 address register 1 Address offset: 0x7C4 */ + __IO uint32_t P0CPPM0AR2; /*!< Pipe0 current pixel packer memory0 address register 2 Address offset: 0x7C8 */ +} DCMIPP_TypeDef; + +/** + * @ brief Delay Block + */ +typedef struct +{ + __IO uint32_t CR; /*!< Delay Block Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA masked interrupt status register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */ +} DMA2D_TypeDef; + +/** + * @brief DTS + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */ + __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */ + __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */ + __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */ + __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */ +} DTS_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x08 */ + uint32_t RESERVED1[5]; /*!< Reserved 1, Address offset: 0x0C-0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x28 */ + uint32_t RESERVED2[21]; /*!< Reserved 2, Address offset: 0x2C-0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x84 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x88 */ + uint32_t RESERVED3; /*!< Reserved 3, Address offset: 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x94 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x98 */ + uint32_t RESERVED4; /*!< Reserved 4, Address offset: 0x9C */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register 3, Address offset: 0xA0 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register 3, Address offset: 0xA4 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x000 */ + __IO uint32_t KEYR; /*!< FLASH control key register, Address offset: 0x004 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x008 - 0x00C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x010 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t IER; /*!< FLASH interrupt enable register, Address offset: 0x020 */ + __IO uint32_t ISR; /*!< FLASH interrupt status register, Address offset: 0x024 */ + __IO uint32_t ICR; /*!< FLASH interrupt clear register, Address offset: 0x028 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t CRCCR; /*!< FLASH CRC control register, Address offset: 0x030 */ + __IO uint32_t CRCSADDR; /*!< FLASH CRC start address register, Address offset: 0x034 */ + __IO uint32_t CRCEADDR; /*!< FLASH CRC end address register, Address offset: 0x038 */ + __IO uint32_t CRCDATAR; /*!< FLASH CRC data register, Address offset: 0x03C */ + __IO uint32_t ECCSFADDR; /*!< FLASH ECC single fail address register, Address offset: 0x040 */ + __IO uint32_t ECCDFADDR; /*!< FLASH ECC double fail address register, Address offset: 0x044 */ + uint32_t RESERVED4[46]; /*!< Reserved, Address offset: 0x048 - 0x0FC */ + __IO uint32_t OPTKEYR; /*!< FLASH options key register, Address offset: 0x100 */ + __IO uint32_t OPTCR; /*!< FLASH options control register, Address offset: 0x104 */ + __IO uint32_t OPTISR; /*!< FLASH options interrupt status register, Address offset: 0x108 */ + __IO uint32_t OPTICR; /*!< FLASH options interrupt clear register, Address offset: 0x10C */ + __IO uint32_t OBKCR; /*!< FLASH option byte key control register, Address offset: 0x110 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x114 */ + __IO uint32_t OBKDR[8]; /*!< FLASH option bytes key data register, Address offset: 0x118 - 0x134 */ + uint32_t RESERVED6[50]; /*!< Reserved, Address offset: 0x138 - 0x1FC */ + __IO uint32_t NVSR; /*!< FLASH non-volatile status register, Address offset: 0x200 */ + __IO uint32_t NVSRP; /*!< FLASH security status register programming, Address offset: 0x204 */ + __IO uint32_t ROTSR; /*!< FLASH RoT status register, Address offset: 0x208 */ + __IO uint32_t ROTSRP; /*!< FLASH RoT status register programming, Address offset: 0x20C */ + __IO uint32_t OTPLSR; /*!< FLASH OTP lock status register, Address offset: 0x210 */ + __IO uint32_t OTPLSRP; /*!< FLASH OTP lock status programming register, Address offset: 0x214 */ + __IO uint32_t WRPSR; /*!< FLASH write protection status register, Address offset: 0x218 */ + __IO uint32_t WRPSRP; /*!< FLASH write protection status register programming, Address offset: 0x21C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x220 - 0x22C */ + __IO uint32_t HDPSR; /*!< FLASH hide protection status register, Address offset: 0x230 */ + __IO uint32_t HDPSRP; /*!< FLASH hide protection status register programming, Address offset: 0x234 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0x238 - 0x24C */ + __IO uint32_t EPOCHSR; /*!< FLASH epoch status register, Address offset: 0x250 */ + __IO uint32_t EPOCHSRP; /*!< FLASH epoch status register programming, Address offset: 0x254 */ + uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x258 - 0x25C */ + __IO uint32_t OBW1SR; /*!< FLASH option byte word 1 status register, Address offset: 0x260 */ + __IO uint32_t OBW1SRP; /*!< FLASH option byte word 1 status register programming, Address offset: 0x264 */ + __IO uint32_t OBW2SR; /*!< FLASH option byte word 2 status register, Address offset: 0x268 */ + __IO uint32_t OBW2SRP; /*!< FLASH option byte word 2 status register programming, Address offset: 0x26C */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1 + */ +typedef struct { + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1 Extended + */ +typedef struct { + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct { + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 & 6 + */ +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140 - 0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148 - 0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief GFXMMU + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved0, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + __IO uint32_t DAR; /*!< GFXMMU default alpha register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved1, Address offset: 0x18 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 0x00 */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 0x04 */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 0x08 */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0x0C */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 0x10 */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 0x14 */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 0x18 */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 0x1C */ + uint32_t RESERVED0[4]; /* Reserved Address offset: 0x20-0x2C */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 0x30 */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 0x34 */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 0x38 */ + uint32_t RESERVED1; /* Reserved Address offset: 0x3C */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 0x40 */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 0x44 */ + uint32_t RESERVED2[2]; /* Reserved Address offset: 0x48-0x4C */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 0x50-0x8C */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 0x90-0xCC */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: 0xD0-0x10C */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 0x110-0x14C */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 0x150-0x18C */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 0x190-0x20C */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 0x210-0x35C */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 0x360-0x4F8 */ + uint32_t RESERVED3; /* Reserved Address offset: 0x4FC */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 0x500-0x65C */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 0x660-0x7BC */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 0x7C0-0x7DC */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 0x7E0-0x7FC */ +} JPEG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Memory Cipher Engine (MCE) + */ +typedef struct +{ + __IO uint32_t REGCR; /*!< MCE region configuration register, Address offset: 0x040 + 0x10 * (x-1) (x = 1 to 4) */ + __IO uint32_t SADDR; /*!< MCE region start address register, Address offset: 0x044 + 0x10 * (x-1) (x = 1 to 4) */ + __IO uint32_t EADDR; /*!< MCE region end address register, Address offset: 0x048 + 0x10 * (x-1) (x = 1 to 4) */ + __IO uint32_t ATTR; /*!< MCE region attribute register, Address offset: 0x04C + 0x10 * (x-1) (x = 1 to 4) */ +} MCE_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CCCFGR; /*!< MCE cipher context configuration register, Address offset: 0x240 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCNR0; /*!< MCE cipher context nonce register 0, Address offset: 0x244 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCNR1; /*!< MCE cipher context nonce register 1, Address offset: 0x248 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR0; /*!< MCE cipher context key register 0, Address offset: 0x24C + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR1; /*!< MCE cipher context key register 1, Address offset: 0x250 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR2; /*!< MCE cipher context key register 2, Address offset: 0x254 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR3; /*!< MCE cipher context key register 3, Address offset: 0x258 + 0x30 * (x-1) (x = 1 to 2) */ +} MCE_Context_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MCE configuration register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< MCE status register, Address offset: 0x004 */ + __IO uint32_t IASR; /*!< MCE illegal access status register, Address offset: 0x008 */ + __IO uint32_t IACR; /*!< MCE illegal access clear register, Address offset: 0x00C */ + __IO uint32_t IAIER; /*!< MCE illegal access interrupt enable register, Address offset: 0x010 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x014-0x018 */ + __IO uint32_t PRIVCFGR; /*!< MCE privileged configuration register, Address offset: 0x01C */ + __IO uint32_t IAESR; /*!< MCE illegal access error status register, Address offset: 0x020 */ + __IO uint32_t IADDR; /*!< MCE illegal address register, Address offset: 0x024 */ + uint32_t RESERVED2[118]; /*!< Reserved, Address offset: 0x028-0x1FC */ + __IO uint32_t MKEYR0; /*!< MCE master key register 0, Address offset: 0x200 */ + __IO uint32_t MKEYR1; /*!< MCE master key register 1, Address offset: 0x204 */ + __IO uint32_t MKEYR2; /*!< MCE master key register 2, Address offset: 0x208 */ + __IO uint32_t MKEYR3; /*!< MCE master key register 3, Address offset: 0x20C */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x210-0x21C */ + __IO uint32_t FMKEYR0; /*!< MCE fast master key register 0, Address offset: 0x220 */ + __IO uint32_t FMKEYR1; /*!< MCE fast master key register 1, Address offset: 0x224 */ + __IO uint32_t FMKEYR2; /*!< MCE fast master key register 2, Address offset: 0x228 */ + __IO uint32_t FMKEYR3; /*!< MCE fast master key register 3, Address offset: 0x22C */ +} MCE_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + +/** + * @brief ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ +} MDF_TypeDef; + +/** + * @brief ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x94-0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + uint32_t RESERVED1[1]; /*!< Reserved, 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED3[10]; /*!< Reserved, 0xC8-0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief XSPI + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control Register, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration Register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration Register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration Register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration Register 4, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t SR; /*!< XSPI Status Register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear Register, Address offset: 0x024 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x028 - 0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length Register, Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address Register, Address offset: 0x048 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data Register, Address offset: 0x050 */ + uint32_t RESERVED6[11]; /*!< Reserved, Address offset: 0x054 - 0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask Register, Address offset: 0x080 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match Register, Address offset: 0x088 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval Register, Address offset: 0x090 */ + uint32_t RESERVED9[27]; /*!< Reserved, Address offset: 0x094 - 0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration Register, Address offset: 0x100 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration Register, Address offset: 0x108 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction Register, Address offset: 0x110 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x114 - 0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes Register, Address offset: 0x120 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x124 - 0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low-Power Timeout Register, Address offset: 0x130 */ + uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x134 - 0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration Register, Address offset: 0x140 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration Register, Address offset: 0x148 */ + uint32_t RESERVED16; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction Register, Address offset: 0x150 */ + uint32_t RESERVED17[3]; /*!< Reserved, Address offset: 0x154 - 0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes Register, Address offset: 0x160 */ + uint32_t RESERVED18[7]; /*!< Reserved, Address offset: 0x164 - 0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration Register, Address offset: 0x180 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration Register, Address offset: 0x188 */ + uint32_t RESERVED20; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction Register, Address offset: 0x190 */ + uint32_t RESERVED21[3]; /*!< Reserved, Address offset: 0x194 - 0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes Register, Address offset: 0x1A0 */ + uint32_t RESERVED22[23]; /*!< Reserved, Address offset: 0x1A4 - 0x1FC */ + __IO uint32_t HLCR; /*!< XSPI HyperBus Latency Configuration Register, Address offset: 0x200 */ + uint32_t RESERVED23[3]; /*!< Reserved, Address offset: 0x204 - 0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-Cycle Calibration Configuration Register, Address offset: 0x210 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL Master Calibration Configuration Register, Address offset: 0x218 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220 */ + uint32_t RESERVED26; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI Slave Input Calibration Configuration Register, Address offset: 0x228 */ +} XSPI_TypeDef; + +/** + * @brief XSPI IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPIM IO Manager Control Register, Address offset: 0x00 */ +} XSPIM_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x04 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x08 */ + __IO uint32_t CSR2; /*!< PWR power control status register 2, Address offset: 0x0C */ + __IO uint32_t CSR3; /*!< PWR power control status register 3, Address offset: 0x10 */ + __IO uint32_t CSR4; /*!< PWR power control status register 4, Address offset: 0x14 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< PWR USB Type-C and power delivery register, Address offset: 0x2C */ + __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x30 */ + __IO uint32_t PUCRN; /*!< PWR port N pull-up control register, Address offset: 0x34 */ + __IO uint32_t PDCRN; /*!< PWR port N pull-down control register, Address offset: 0x38 */ + __IO uint32_t PUCRO; /*!< PWR port O pull-up control register, Address offset: 0x3C */ + __IO uint32_t PDCRO; /*!< PWR port O pull-down control register, Address offset: 0x40 */ + __IO uint32_t PDCRP; /*!< PWR port P pull-down control register, Address offset: 0x44 */ + uint32_t RESERVED2[2]; /*!< Reserved */ + __IO uint32_t PDR1; /*!< PWR debug register 1, Address offset: 0x50 */ +} PWR_TypeDef; + +/** + * @brief Public Key Accelerator (PKA) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved1[253]; /*!< Reserved, Address offset: 0x000C-0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x0400-0x18D8 */ +} PKA_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI clock calibration register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock recovery RC register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI clock calibration register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CDCFGR; /*!< RCC CPU domain configuration register, Address offset: 0x18 */ + __IO uint32_t BMCFGR; /*!< RCC Bus matrix configuration register, Address offset: 0x1C */ + __IO uint32_t APBCFGR; /*!< RCC APB clock configuration register, Address offset: 0x20 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs clock source selection register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs configuration register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR1; /*!< RCC PLL1 dividers configuration register 1, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 fractional divider configuration register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR1; /*!< RCC PLL2 dividers configuration register 1, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 fractional divider configuration register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR1; /*!< RCC PLL3 dividers configuration register 1, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 fractional divider configuration register, Address offset: 0x44 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t CCIPR1; /*!< RCC AHB peripherals kernel clock configuration register Address offset: 0x4C */ + __IO uint32_t CCIPR2; /*!< RCC APB1 peripherals kernel clock configuration register Address offset: 0x50 */ + __IO uint32_t CCIPR3; /*!< RCC APB2 peripherals kernel clock configuration register Address offset: 0x54 */ + __IO uint32_t CCIPR4; /*!< RCC APB4/APB5 peripherals kernel clock configuration register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x68 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB5RSTR; /*!< RCC AHB5 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB5RSTR; /*!< RCC APB5 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x90 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0xA0 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0xA4 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0xA8-0xAC */ + __IO uint32_t CKGDISR ; /*!< RCC AXI clocks gating disable register, Address offset: 0xB0 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0xB4-0xBC */ + __IO uint32_t PLL1DIVR2; /*!< RCC PLL1 dividers configuration register 2, Address offset: 0xC0 */ + __IO uint32_t PLL2DIVR2; /*!< RCC PLL2 dividers configuration register 2, Address offset: 0xC4 */ + __IO uint32_t PLL3DIVR2; /*!< RCC PLL3 dividers configuration register 2, Address offset: 0xC8 */ + __IO uint32_t PLL1SSCGR; /*!< RCC PLL1 spread spectrum clock generator register, Address offset: 0xCC */ + __IO uint32_t PLL2SSCGR; /*!< RCC PLL2 spread spectrum clock generator register, Address offset: 0xD0 */ + __IO uint32_t PLL3SSCGR; /*!< RCC PLL3 spread spectrum clock generator register, Address offset: 0xD4 */ + uint32_t RESERVED9[10]; /*!< Reserved, Address offset: 0xD8-0xFC */ + __IO uint32_t CKPROTR; /*!< RCC clock protection register, Address offset: 0x100 */ + uint32_t RESERVED10[11]; /*!< Reserved, Address offset: 0x104-0x12C */ + __IO uint32_t RSR; /*!< RCC reset status register, Address offset: 0x130 */ + __IO uint32_t AHB5ENR; /*!< RCC AHB5 peripheral clocks enable register, Address offset: 0x134 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x138 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x13C */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clocks enable register, Address offset: 0x140 */ + __IO uint32_t APB5ENR; /*!< RCC APB5 peripheral clocks enable register, Address offset: 0x144 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x148 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x14C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x150 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clocks enable register, Address offset: 0x154 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x158 */ + __IO uint32_t AHB5LPENR; /*!< RCC AHB5 peripheral sleep clocks enable register, Address offset: 0x15C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clocks enable register, Address offset: 0x160 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clocks enable register, Address offset: 0x164 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clocks enable register, Address offset: 0x168 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clocks enable register, Address offset: 0x16C */ + __IO uint32_t APB1LPENR1; /*!< RCC APB1 peripheral sleep clocks enable register 1, Address offset: 0x170 */ + __IO uint32_t APB1LPENR2; /*!< RCC APB1 peripheral sleep clocks enable register 2, Address offset: 0x174 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clocks enable register, Address offset: 0x178 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clocks enable register, Address offset: 0x17C */ + __IO uint32_t APB5LPENR; /*!< RCC APB5 peripheral sleep clocks enable register, Address offset: 0x180 */ +} RCC_TypeDef; + +/** + * @brief Random Number Generator + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief SAES Processor + */ +typedef struct +{ + __IO uint32_t CR; /*!< SAES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< SAES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< SAES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< SAES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< SAES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< SAES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< SAES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< SAES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< SAES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< SAES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< SAES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< SAES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< SAES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< SAES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< SAES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< SAES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< SAES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< SAES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< SAES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< SAES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< SAES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< SAES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< SAES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< SAES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168]; /*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< SAES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< SAES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< SAES Interrupt Clear Register, Address offset: 0x308 */ +} SAES_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration, boot and security controller + */ +typedef struct +{ + __IO uint32_t BOOTSR; /*!< SBS Boot Status register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04-0x0C */ + __IO uint32_t HDPLCR; /*!< SBS Hide Protection Control register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS Hide Protection Status register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x28-0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command register, Address offset: 0x34 */ + uint32_t RESERVED4[50]; /*!< Reserved, Address offset: 0x38-0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status register, Address offset: 0x108 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS IO Compensation Cell Control and Status register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS IO Compensation Cell Value register, Address offset: 0x114 */ + __IO uint32_t CCSWVALR; /*!< SBS IO Compensation Cell Software Value register, Address offset: 0x118 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x11C */ + __IO uint32_t BKLOCKR; /*!< SBS Break Lockup register, Address offset: 0x120 */ + uint32_t RESERVED7[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t EXTICR[4]; /*!< SBS External Interrupt Configuration registers, Address offset: 0x130-0x13C */ +} SBS_TypeDef; + +/** + * @brief Secure Digital Card/IO Embedded MultiMediaCard Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC Power control register, Address offset : 0x000 */ + __IO uint32_t CLKCR; /*!< SDMMC Clock control register, Address offset : 0x004 */ + __IO uint32_t ARG; /*!< SDMMC Argument register, Address offset : 0x008 */ + __IO uint32_t CMD; /*!< SDMMC Command register, Address offset : 0x00C */ + __IO uint32_t RESPCMD; /*!< SDMMC Command response register, Address offset : 0x010 */ + __IO uint32_t RESP1; /*!< SDMMC Response 1 register, Address offset : 0x014 */ + __IO uint32_t RESP2; /*!< SDMMC Response 2 register, Address offset : 0x018 */ + __IO uint32_t RESP3; /*!< SDMMC Response 3 register, Address offset : 0x01C */ + __IO uint32_t RESP4; /*!< SDMMC Response 4 register, Address offset : 0x020 */ + __IO uint32_t DTIMER; /*!< SDMMC Data timer register, Address offset : 0x024 */ + __IO uint32_t DLEN; /*!< SDMMC Data length register, Address offset : 0x028 */ + __IO uint32_t DCTRL; /*!< SDMMC Data control register, Address offset : 0x02C */ + __IO uint32_t DCOUNT; /*!< SDMMC Data counter register, Address offset : 0x030 */ + __IO uint32_t STA; /*!< SDMMC Status register, Address offset : 0x034 */ + __IO uint32_t ICR; /*!< SDMMC Interrupt clear register, Address offset : 0x038 */ + __IO uint32_t MASK; /*!< SDMMC Mask register, Address offset : 0x03C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset : 0x040 */ + uint32_t RESERVED0[3]; /*!< Reserved, Address offset : 0x044 - 0x04C */ + __IO uint32_t IDMACTRL; /*!< SDMMC IDMA control register, Address offset : 0x050 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC IDMA buffer size register, Address offset : 0x054 */ + __IO uint32_t IDMABASER; /*!< SDMMC IDMA buffer base address register, Address offset : 0x058 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset : 0x05C - 0x060 */ + __IO uint32_t IDMALAR; /*!< SDMMC IDMA linked list address register, Address offset : 0x064 */ + __IO uint32_t IDMABAR; /*!< SDMMC IDMA linked list memory base register, Address offset : 0x068 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset : 0x06C - 0x07C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset : 0x080 */ +} SDMMC_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t CFGR; /*!< TAMP configuration control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter 1 register, Address offset: 0x40 */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED5[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + uint32_t RESERVED0[221]; /*!< Reserved, Address offset: 0x68 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Window Watchdog + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32H7RSxx_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup STM32H7RSxx_Peripheral_peripheralAddr + * @{ + */ +#define ITCM_BASE 0x00000000UL /*!< ITCM base address */ +#define FLASH_BASE 0x08000000UL /*!< User Flash address */ +#define OTP_AREA_BASE 0x08FFF000UL /*!< OTP Area base address */ +#define ENGI_BYTES_BASE 0x52002800UL /*!< Engi Bytes */ +#define SYSTEM_FLASH_BASE 0x1FF00000UL /*!< System Flash base address */ +#define DTCM_BASE 0x20000000UL /*!< DTCM base address */ +#define SRAM1_AXI_BASE 0x24000000UL /*!< SRAM1 base address - accessible over AXI */ +#define SRAM2_AXI_BASE 0x24020000UL /*!< SRAM2 base address - accessible over AXI */ +#define SRAM3_AXI_BASE 0x24040000UL /*!< SRAM3 base address - accessible over AXI */ +#define SRAM4_AXI_BASE 0x24060000UL /*!< SRAM4 base address - accessible over AXI */ + +#define GFXMMU_VIRTUAL_BUFFER0_BASE 0x25000000UL /*!< GFXMMU virtual buffer 0 base address */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE 0x25400000UL /*!< GFXMMU virtual buffer 1 base address */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE 0x25800000UL /*!< GFXMMU virtual buffer 2 base address */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE 0x25C00000UL /*!< GFXMMU virtual buffer 3 base address */ + +#define SRAM1_AHB_BASE 0x30000000UL /*!< SRAM1 base address */ +#define SRAM2_AHB_BASE 0x30004000UL /*!< SRAM2 base address */ +#define BKPSRAM_BASE 0x38800000UL /*!< Backup SRAM */ + +#define PERIPH_BASE 0x40000000UL /*!< AHB and APB Peripherals base address */ +#define XSPI2_BASE 0x70000000UL /*!< XSPI2 base address */ +#define XSPI1_BASE 0x90000000UL /*!< XSPI1 base address */ + +/*!< Internal memory size */ +#define ITCM_SIZE 0x00010000UL /*!< 64 KB default, can be increased up to 192 KB */ +#define DTCM_SIZE 0x00010000UL /*!< 64 KB default, can be increased up to 192 KB */ +#define FLASH_SIZE 0x00010000UL /*!< 64 KB */ +#define SRAM1_AXI_SIZE 0x00020000UL /*!< 128 KB default, can be decreased down to 0 KB to increase ITCM */ +#define SRAM2_AXI_SIZE 0x00020000UL /*!< 128 KB */ +#define SRAM3_AXI_SIZE 0x00020000UL /*!< 128 KB default, can be decreased down to 0 KB to increase DTCM */ +#define SRAM4_AXI_SIZE 0x00012000UL /*!< 72 KB default, can be decreased to 0 KB when RAM ECC is disable */ +#define SRAM_AHB_SIZE 0x00004000UL /*!< Both AHB SRAMs are 16 KB */ +#define BKPSRAM_SIZE 0x00001000UL /*!< 4 KB */ + +/*!< OTP Area size */ +#define OTP_SIZE 0x400U /* 1 KB */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x02000000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x08020000UL) +#define APB5PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define AHB5PERIPH_BASE (PERIPH_BASE + 0x12000000UL) +#define APB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define AHB4PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I3C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x8400UL) +#define MDIOS_BASE (APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0xA100UL) /*!< FDCAN configuration registers base address */ +#define FDCAN2_BASE (APB1PERIPH_BASE + 0xA400UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xAC00UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xEC00UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00UL) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define GPDMA1_Channel0_BASE (GPDMA1_BASE + 0x0050UL) +#define GPDMA1_Channel1_BASE (GPDMA1_BASE + 0x00D0UL) +#define GPDMA1_Channel2_BASE (GPDMA1_BASE + 0x0150UL) +#define GPDMA1_Channel3_BASE (GPDMA1_BASE + 0x01D0UL) +#define GPDMA1_Channel4_BASE (GPDMA1_BASE + 0x0250UL) +#define GPDMA1_Channel5_BASE (GPDMA1_BASE + 0x02D0UL) +#define GPDMA1_Channel6_BASE (GPDMA1_BASE + 0x0350UL) +#define GPDMA1_Channel7_BASE (GPDMA1_BASE + 0x03D0UL) +#define GPDMA1_Channel8_BASE (GPDMA1_BASE + 0x0450UL) +#define GPDMA1_Channel9_BASE (GPDMA1_BASE + 0x04D0UL) +#define GPDMA1_Channel10_BASE (GPDMA1_BASE + 0x0550UL) +#define GPDMA1_Channel11_BASE (GPDMA1_BASE + 0x05D0UL) +#define GPDMA1_Channel12_BASE (GPDMA1_BASE + 0x0650UL) +#define GPDMA1_Channel13_BASE (GPDMA1_BASE + 0x06D0UL) +#define GPDMA1_Channel14_BASE (GPDMA1_BASE + 0x0750UL) +#define GPDMA1_Channel15_BASE (GPDMA1_BASE + 0x07D0UL) +#define ADC1_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) +#define ADF1_BASE (AHB1PERIPH_BASE + 0xF000UL) +#define ADF1_Filter0_BASE (ADF1_BASE + 0x0080UL) +#define USB_OTG_HS_PERIPH_BASE (AHB1PERIPH_BASE + 0x20000UL) +#define USB_OTG_FS_PERIPH_BASE (AHB1PERIPH_BASE + 0x60000UL) + +/*!< AHB2 peripherals */ +#define PSSI_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define SDMMC2_BASE (AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (AHB2PERIPH_BASE + 0x2800UL) +#define CORDIC_BASE (AHB2PERIPH_BASE + 0x4400UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE AHB3PERIPH_BASE +#define HASH_BASE (AHB3PERIPH_BASE + 0x0400UL) +#define HASH_DIGEST_BASE (AHB3PERIPH_BASE + 0x0710UL) +#define CRYP_BASE (AHB3PERIPH_BASE + 0x0800UL) +#define SAES_BASE (AHB3PERIPH_BASE + 0x1000UL) +#define PKA_BASE (AHB3PERIPH_BASE + 0x2000UL) + +/*!< APB5 peripherals */ +#define DCMIPP_BASE (APB5PERIPH_BASE + 0x2000UL) +#define GFXTIM_BASE (APB5PERIPH_BASE + 0x4000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE AHB5PERIPH_BASE +#define HPDMA1_Channel0_BASE (HPDMA1_BASE + 0x0050UL) +#define HPDMA1_Channel1_BASE (HPDMA1_BASE + 0x00D0UL) +#define HPDMA1_Channel2_BASE (HPDMA1_BASE + 0x0150UL) +#define HPDMA1_Channel3_BASE (HPDMA1_BASE + 0x01D0UL) +#define HPDMA1_Channel4_BASE (HPDMA1_BASE + 0x0250UL) +#define HPDMA1_Channel5_BASE (HPDMA1_BASE + 0x02D0UL) +#define HPDMA1_Channel6_BASE (HPDMA1_BASE + 0x0350UL) +#define HPDMA1_Channel7_BASE (HPDMA1_BASE + 0x03D0UL) +#define HPDMA1_Channel8_BASE (HPDMA1_BASE + 0x0450UL) +#define HPDMA1_Channel9_BASE (HPDMA1_BASE + 0x04D0UL) +#define HPDMA1_Channel10_BASE (HPDMA1_BASE + 0x0550UL) +#define HPDMA1_Channel11_BASE (HPDMA1_BASE + 0x05D0UL) +#define HPDMA1_Channel12_BASE (HPDMA1_BASE + 0x0650UL) +#define HPDMA1_Channel13_BASE (HPDMA1_BASE + 0x06D0UL) +#define HPDMA1_Channel14_BASE (HPDMA1_BASE + 0x0750UL) +#define HPDMA1_Channel15_BASE (HPDMA1_BASE + 0x07D0UL) +#define DMA2D_BASE (AHB5PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB5PERIPH_BASE + 0x2000UL) +#define JPEG_BASE (AHB5PERIPH_BASE + 0x3000UL) +#define FMC_R_BASE (AHB5PERIPH_BASE + 0x4000UL) +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) +#define XSPI1_R_BASE (AHB5PERIPH_BASE + 0x5000UL) +#define SDMMC1_BASE (AHB5PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (AHB5PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (AHB5PERIPH_BASE + 0x9000UL) +#define RAMECC1_Monitor0_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0xA0UL) +#define XSPI2_R_BASE (AHB5PERIPH_BASE + 0xA000UL) +#define XSPIM_BASE (AHB5PERIPH_BASE + 0xB400UL) +#define MCE1_BASE (AHB5PERIPH_BASE + 0xB800UL) +#define MCE1_REGION1_BASE (MCE1_BASE + 0x040UL) +#define MCE1_REGION2_BASE (MCE1_BASE + 0x050UL) +#define MCE1_REGION3_BASE (MCE1_BASE + 0x060UL) +#define MCE1_REGION4_BASE (MCE1_BASE + 0x070UL) +#define MCE1_CONTEXT1_BASE (MCE1_BASE + 0x240UL) +#define MCE1_CONTEXT2_BASE (MCE1_BASE + 0x270UL) +#define MCE2_BASE (AHB5PERIPH_BASE + 0xBC00UL) +#define MCE2_REGION1_BASE (MCE2_BASE + 0x040UL) +#define MCE2_REGION2_BASE (MCE2_BASE + 0x050UL) +#define MCE2_REGION3_BASE (MCE2_BASE + 0x060UL) +#define MCE2_REGION4_BASE (MCE2_BASE + 0x070UL) +#define MCE3_BASE (AHB5PERIPH_BASE + 0xC000UL) +#define MCE3_REGION1_BASE (MCE3_BASE + 0x040UL) +#define MCE3_REGION2_BASE (MCE3_BASE + 0x050UL) +#define MCE3_REGION3_BASE (MCE3_BASE + 0x060UL) +#define MCE3_REGION4_BASE (MCE3_BASE + 0x070UL) +#define GFXMMU_BASE (AHB5PERIPH_BASE + 0x010000UL) + +/*!< APB4 peripherals */ +#define EXTI_BASE APB4PERIPH_BASE +#define SBS_BASE (APB4PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (APB4PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (APB4PERIPH_BASE + 0x1400UL) +#define LPTIM2_BASE (APB4PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (APB4PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (APB4PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (APB4PERIPH_BASE + 0x3000UL) +#define VREFBUF_BASE (APB4PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (APB4PERIPH_BASE + 0x4000UL) +#define TAMP_BASE (APB4PERIPH_BASE + 0x4400UL) +#define IWDG_BASE (APB4PERIPH_BASE + 0x4800UL) +#define DTS_BASE (APB4PERIPH_BASE + 0x6800UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE AHB4PERIPH_BASE +#define GPIOB_BASE (AHB4PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB4PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB4PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB4PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB4PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB4PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB4PERIPH_BASE + 0x1C00UL) +#define GPIOM_BASE (AHB4PERIPH_BASE + 0x3000UL) +#define GPION_BASE (AHB4PERIPH_BASE + 0x3400UL) +#define GPIOO_BASE (AHB4PERIPH_BASE + 0x3800UL) +#define GPIOP_BASE (AHB4PERIPH_BASE + 0x3C00UL) +#define RCC_BASE (AHB4PERIPH_BASE + 0x4400UL) +#define PWR_BASE (AHB4PERIPH_BASE + 0x4800UL) +#define CRC_BASE (AHB4PERIPH_BASE + 0x4C00UL) +#define RAMECC2_BASE (AHB4PERIPH_BASE + 0x7000UL) +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x40UL) + +/*!< Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +/*!< AXIM registers base address */ +#define AXIM_BASE (0xBFF00000UL) +#define AXIM_ASIB1_BASE (AXIM_BASE + 0x42000UL) +#define AXIM_ASIB2_BASE (AXIM_BASE + 0x43000UL) +#define AXIM_ASIB3_BASE (AXIM_BASE + 0x44000UL) +#define AXIM_ASIB4_BASE (AXIM_BASE + 0x45000UL) +#define AXIM_ASIB5_BASE (AXIM_BASE + 0x46000UL) +#define AXIM_ASIB6_BASE (AXIM_BASE + 0x47000UL) +#define AXIM_ASIB7_BASE (AXIM_BASE + 0x48000UL) +#define AXIM_ASIB8_BASE (AXIM_BASE + 0x49000UL) +#define AXIM_ASIB9_BASE (AXIM_BASE + 0x4A000UL) +#define AXIM_ASIB10_BASE (AXIM_BASE + 0x4B000UL) +#define AXIM_ASIB11_BASE (AXIM_BASE + 0x4C000UL) +#define AXIM_AMIB1_BASE (AXIM_BASE + 0x02000UL) +#define AXIM_AMIB2_BASE (AXIM_BASE + 0x03000UL) +#define AXIM_AMIB3_BASE (AXIM_BASE + 0x04000UL) +#define AXIM_AMIB4_BASE (AXIM_BASE + 0x05000UL) +#define AXIM_AMIB5_BASE (AXIM_BASE + 0x06000UL) +#define AXIM_AMIB6_BASE (AXIM_BASE + 0x07000UL) +#define AXIM_AMIB7_BASE (AXIM_BASE + 0x08000UL) +#define AXIM_AMIB8_BASE (AXIM_BASE + 0x09000UL) +#define AXIM_AMIB9_BASE (AXIM_BASE + 0x0A000UL) +#define AXIM_AMIB10_BASE (AXIM_BASE + 0x0B000UL) + +/*!< Unique device ID register base address */ +#define UID_BASE (0x08FFF800UL) + +/*!< Flash size data register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) + +/*!< Package data register base address */ +#define PACKAGE_BASE (0x08FFF80CUL) + +/* USB OTG registers base addresses */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_PFUNC_START (0x1FF1FD4CUL) +#define RSSLIB_SYS_FLASH_PFUNC_END (0x1FF1FD78UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0x1FF1FD4CUL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t Destination; /*!< OBKeys destination information where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + +/** + * @brief Prototype of RSSLIB Set Secure OB Function + * @detail This function configure a secure OB. + * @param OB address among following values: + * &(FLASH->WRPSRP), &(FLASH->HDPSRP) or &(FLASH->ROTSRP) + * @param OB mask (example 0x000000FF for updating WRP OB). + * @param OB value + * @param OB Pos: bit position of OB value. + * ObValue << ObPos must be aligned on ObMask. + * @retval RSSLIB_RSS_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_SetSecOB_TypeDef)(uint32_t ObAddr, uint32_t ObMask, uint32_t ObValue, uint32_t ObPos); + +/** + * @brief Prototype of RSSLIB Get RSS Status Function + * @detail This function return RSS Status. + * Calling GetRssStatus is only relevant after calling + * SetSecOB or DataProvisioning. + * @param none. + * @retval RSSLIB_SUCCESS on success, otherwise return an error 0xF5F5xxxx. + */ +typedef uint32_t (*RSSLIB_GetRssStatus_TypeDef)(void); + +/** + * @brief Prototype of RSSLIB Set Product State Function + * @detail This function change Product State. + * @param Requested Product State among following values: + * 0x17 : Provisioning + * 0x72 : Closed + * 0x5C : Locked + * @retval RSSLIB_RSS_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_SetProductState_TypeDef)(uint32_t ProductState); + +/** + * @brief Prototype of RSSLIB Get Product State Function + * @detail This function return current Product State. + * @param none. + * @retval RSSLIB_RSS_ERROR on error, + * otherwise return product state among following values: + * 0x39 : Open + * 0x17 : Provisioning + * 0x72 : Closed + * 0x5C : Locked + */ +typedef uint32_t (*RSSLIB_GetProductState_TypeDef)(void); + + +/** + * @brief RSSLib callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_SetSecOB_TypeDef SetSecOB; + uint32_t RESERVED1[4]; + __IM RSSLIB_GetRssStatus_TypeDef GetRssStatus; + __IM RSSLIB_SetProductState_TypeDef SetProductState; + __IM RSSLIB_DataProvisioning_TypeDef DataProvisioning; + __IM RSSLIB_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_GetProductState_TypeDef GetProductState; +} RSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32H7RSxx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H7RSxx_Peripheral_declaration + * @{ + */ + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADF1 ((MDF_TypeDef *) ADF1_BASE) +#define ADF1_Filter0 ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE) +#define AXIM_AMIB_1 ((AXIM_AMIB_TypeDef *) AXIM_AMIB1_BASE ) +#define AXIM_AMIB_2 ((AXIM_AMIB_TypeDef *) AXIM_AMIB2_BASE ) +#define AXIM_AMIB_3 ((AXIM_AMIB_TypeDef *) AXIM_AMIB3_BASE ) +#define AXIM_AMIB_4 ((AXIM_AMIB_TypeDef *) AXIM_AMIB4_BASE ) +#define AXIM_AMIB_5 ((AXIM_AMIB_TypeDef *) AXIM_AMIB5_BASE ) +#define AXIM_AMIB_6 ((AXIM_AMIB_TypeDef *) AXIM_AMIB6_BASE ) +#define AXIM_AMIB_7 ((AXIM_AMIB_TypeDef *) AXIM_AMIB7_BASE ) +#define AXIM_AMIB_8 ((AXIM_AMIB_TypeDef *) AXIM_AMIB8_BASE ) +#define AXIM_AMIB_9 ((AXIM_AMIB_TypeDef *) AXIM_AMIB9_BASE ) +#define AXIM_AMIB_10 ((AXIM_AMIB_TypeDef *) AXIM_AMIB10_BASE) +#define AXIM_ASIB_1 ((AXIM_ASIB_TypeDef *) AXIM_ASIB1_BASE ) +#define AXIM_ASIB_2 ((AXIM_ASIB_TypeDef *) AXIM_ASIB2_BASE ) +#define AXIM_ASIB_3 ((AXIM_ASIB_TypeDef *) AXIM_ASIB3_BASE ) +#define AXIM_ASIB_4 ((AXIM_ASIB_TypeDef *) AXIM_ASIB4_BASE ) +#define AXIM_ASIB_5 ((AXIM_ASIB_TypeDef *) AXIM_ASIB5_BASE ) +#define AXIM_ASIB_6 ((AXIM_ASIB_TypeDef *) AXIM_ASIB6_BASE ) +#define AXIM_ASIB_7 ((AXIM_ASIB_TypeDef *) AXIM_ASIB7_BASE ) +#define AXIM_ASIB_8 ((AXIM_ASIB_TypeDef *) AXIM_ASIB8_BASE ) +#define AXIM_ASIB_9 ((AXIM_ASIB_TypeDef *) AXIM_ASIB9_BASE ) +#define AXIM_ASIB_10 ((AXIM_ASIB_TypeDef *) AXIM_ASIB10_BASE) +#define AXIM_ASIB_11 ((AXIM_ASIB_TypeDef *) AXIM_ASIB11_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define DCMIPP ((DCMIPP_TypeDef *) DCMIPP_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DTS ((DTS_TypeDef *) DTS_BASE) +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define GFXTIM ((GFXTIM_TypeDef *) GFXTIM_BASE) +#define GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE) +#define GPDMA1 ((DMA_TypeDef *) GPDMA1_BASE) +#define GPDMA1_Channel0 ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE) +#define GPDMA1_Channel1 ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE) +#define GPDMA1_Channel2 ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE) +#define GPDMA1_Channel3 ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE) +#define GPDMA1_Channel4 ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE) +#define GPDMA1_Channel5 ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE) +#define GPDMA1_Channel6 ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE) +#define GPDMA1_Channel7 ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE) +#define GPDMA1_Channel8 ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE) +#define GPDMA1_Channel9 ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE) +#define GPDMA1_Channel10 ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE) +#define GPDMA1_Channel11 ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE) +#define GPDMA1_Channel12 ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE) +#define GPDMA1_Channel13 ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE) +#define GPDMA1_Channel14 ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE) +#define GPDMA1_Channel15 ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOM ((GPIO_TypeDef *) GPIOM_BASE) +#define GPION ((GPIO_TypeDef *) GPION_BASE) +#define GPIOO ((GPIO_TypeDef *) GPIOO_BASE) +#define GPIOP ((GPIO_TypeDef *) GPIOP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define HPDMA1 ((DMA_TypeDef *) HPDMA1_BASE) +#define HPDMA1_Channel0 ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE) +#define HPDMA1_Channel1 ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE) +#define HPDMA1_Channel2 ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE) +#define HPDMA1_Channel3 ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE) +#define HPDMA1_Channel4 ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE) +#define HPDMA1_Channel5 ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE) +#define HPDMA1_Channel6 ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE) +#define HPDMA1_Channel7 ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE) +#define HPDMA1_Channel8 ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE) +#define HPDMA1_Channel9 ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE) +#define HPDMA1_Channel10 ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE) +#define HPDMA1_Channel11 ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE) +#define HPDMA1_Channel12 ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE) +#define HPDMA1_Channel13 ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE) +#define HPDMA1_Channel14 ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE) +#define HPDMA1_Channel15 ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE) +#define JPEG ((JPEG_TypeDef *) JPEG_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I3C1 ((I3C_TypeDef *) I3C1_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define MCE1 ((MCE_TypeDef *) MCE1_BASE) +#define MCE1_REGION1 ((MCE_Region_TypeDef *) MCE1_REGION1_BASE) +#define MCE1_REGION2 ((MCE_Region_TypeDef *) MCE1_REGION2_BASE) +#define MCE1_REGION3 ((MCE_Region_TypeDef *) MCE1_REGION3_BASE) +#define MCE1_REGION4 ((MCE_Region_TypeDef *) MCE1_REGION4_BASE) +#define MCE1_CONTEXT1 ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE) +#define MCE1_CONTEXT2 ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE) +#define MCE2 ((MCE_TypeDef *) MCE2_BASE) +#define MCE2_REGION1 ((MCE_Region_TypeDef *) MCE2_REGION1_BASE) +#define MCE2_REGION2 ((MCE_Region_TypeDef *) MCE2_REGION2_BASE) +#define MCE2_REGION3 ((MCE_Region_TypeDef *) MCE2_REGION3_BASE) +#define MCE2_REGION4 ((MCE_Region_TypeDef *) MCE2_REGION4_BASE) +#define MCE3 ((MCE_TypeDef *) MCE3_BASE) +#define MCE3_REGION1 ((MCE_Region_TypeDef *) MCE3_REGION1_BASE) +#define MCE3_REGION2 ((MCE_Region_TypeDef *) MCE3_REGION2_BASE) +#define MCE3_REGION3 ((MCE_Region_TypeDef *) MCE3_REGION3_BASE) +#define MCE3_REGION4 ((MCE_Region_TypeDef *) MCE3_REGION4_BASE) +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) +#define PKA ((PKA_TypeDef *) PKA_BASE) +#define PSSI ((PSSI_TypeDef *) PSSI_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC1_Monitor0 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor0_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SAES ((SAES_TypeDef *) SAES_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *) SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *) SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *) SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *) SAI2_Block_B_BASE) +#define SBS ((SBS_TypeDef *) SBS_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define XSPI1 ((XSPI_TypeDef *) XSPI1_R_BASE) +#define XSPI2 ((XSPI_TypeDef *) XSPI2_R_BASE) +#define XSPIM ((XSPIM_TypeDef *) XSPIM_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) + +/** @} */ /* End of group STM32H7RSxx_Peripheral_declaration */ + +/** @addtogroup STM32H7RSxx_Peripheral_Exported_constants + * @{ + */ + +/** @addtogroup STM32H7RSxx_Peripheral_Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_Peripheral_Registers_Bits_Definition + * @{ + */ +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_ADFCFG_Pos (2U) +#define ADC_CFGR_ADFCFG_Msk (0x1UL << ADC_CFGR_ADFCFG_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_ADFCFG ADC_CFGR_ADFCFG_Msk /*!< ADC ADF transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register ***************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x1UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC internal path to VDDCORE */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ + +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************************************************************************/ +/* */ +/* AXIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AXIM_ASIB_FNMOD2 register **********/ +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE_Pos (0U) +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE_Msk (0x1UL << AXIM_ASIB_FNMOD2_BYPASS_MERGE_Pos) /*!< 0x00000001 */ +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE AXIM_ASIB_FNMOD2_BYPASS_MERGE_Msk /*!< Bypass Merge enable */ + +/******************* Bit definition for AXIM_ASIB_READQOS register ********/ +#define AXIM_ASIB_READQOS_AR_QOS_Pos (0U) +#define AXIM_ASIB_READQOS_AR_QOS_Msk (0xFUL << AXIM_ASIB_READQOS_AR_QOS_Pos) /*!< 0x0000000F */ +#define AXIM_ASIB_READQOS_AR_QOS AXIM_ASIB_READQOS_AR_QOS_Msk /*!< Read channel QoS setting */ + +/******************* Bit definition for AXIM_ASIB_WRITEQOS register *******/ +#define AXIM_ASIB_WRITEQOS_AW_QOS_Pos (0U) +#define AXIM_ASIB_WRITEQOS_AW_QOS_Msk (0xFUL << AXIM_ASIB_WRITEQOS_AW_QOS_Pos) /*!< 0x0000000F */ +#define AXIM_ASIB_WRITEQOS_AW_QOS AXIM_ASIB_WRITEQOS_AW_QOS_Msk /*!< Write channel QoS setting */ + +/******************* Bit definition for AXIM_ASIB_FNMOD register **********/ +#define AXIM_ASIB_FNMOD_READ_ISS_Pos (0U) +#define AXIM_ASIB_FNMOD_READ_ISS_Msk (0x1UL << AXIM_ASIB_FNMOD_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_ASIB_FNMOD_READ_ISS AXIM_ASIB_FNMOD_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_ASIB_FNMOD_WRITE_ISS_Pos (1U) +#define AXIM_ASIB_FNMOD_WRITE_ISS_Msk (0x1UL << AXIM_ASIB_FNMOD_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_ASIB_FNMOD_WRITE_ISS AXIM_ASIB_FNMOD_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************* Bit definition for AXIM_AMIB_FNMODBMISS register **********/ +#define AXIM_AMIB_FNMODBMISS_READ_ISS_Pos (0U) +#define AXIM_AMIB_FNMODBMISS_READ_ISS_Msk (0x1UL << AXIM_AMIB_FNMODBMISS_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMODBMISS_READ_ISS AXIM_AMIB_FNMODBMISS_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS_Pos (1U) +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS_Msk (0x1UL << AXIM_AMIB_FNMODBMISS_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS AXIM_AMIB_FNMODBMISS_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************* Bit definition for AXIM_AMIB_FNMOD2 register **********/ +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE_Pos (0U) +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE_Msk (0x1UL << AXIM_AMIB_FNMOD2_BYPASS_MERGE_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE AXIM_AMIB_FNMOD2_BYPASS_MERGE_Msk /*!< Bypass Merge enable */ + +/******************* Bit definition for AXIM_AMIB_FNMODLB register **********/ +#define AXIM_AMIB_FNMODLB_LONG_BURST_Pos (0U) +#define AXIM_AMIB_FNMODLB_LONG_BURST_Msk (0x1UL << AXIM_AMIB_FNMODLB_LONG_BURST_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMODLB_LONG_BURST AXIM_AMIB_FNMODLB_LONG_BURST_Msk /*!< Long bursts can be generated */ + +/******************* Bit definition for AXIM_AMIB_FNMOD register **********/ +#define AXIM_AMIB_FNMOD_READ_ISS_Pos (0U) +#define AXIM_AMIB_FNMOD_READ_ISS_Msk (0x1UL << AXIM_AMIB_FNMOD_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMOD_READ_ISS AXIM_AMIB_FNMOD_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_AMIB_FNMOD_WRITE_ISS_Pos (1U) +#define AXIM_AMIB_FNMOD_WRITE_ISS_Msk (0x1UL << AXIM_AMIB_FNMOD_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_AMIB_FNMOD_WRITE_ISS AXIM_AMIB_FNMOD_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* Parallel Synchronous Slave Interface (PSSI ) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PSSI_CR register *******************/ +#define PSSI_CR_CKPOL_Pos (5U) +#define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) /*!< 0x00000020 */ +#define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk /*!< Parallel data clock polarity */ +#define PSSI_CR_DEPOL_Pos (6U) +#define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) /*!< 0x00000040 */ +#define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk /*!< Data enable polarity */ +#define PSSI_CR_RDYPOL_Pos (8U) +#define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) /*!< 0x00000100 */ +#define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk /*!< Ready polarity */ +#define PSSI_CR_EDM_Pos (10U) +#define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define PSSI_CR_EDM PSSI_CR_EDM_Msk /*!< Extended data mode */ +#define PSSI_CR_ENABLE_Pos (14U) +#define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk /*!< PSSI enable */ +#define PSSI_CR_DERDYCFG_Pos (18U) +#define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< 0x001C0000 */ +#define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk /*!< Data enable and ready configuration */ +#define PSSI_CR_CKSRC_Pos (29U) +#define PSSI_CR_CKSRC_Msk (0x1UL << PSSI_CR_CKSRC_Pos) /*!< 0x20000000 */ +#define PSSI_CR_CKSRC PSSI_CR_CKSRC_Msk /*!< Clock source */ +#define PSSI_CR_DMAEN_Pos (30U) +#define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) /*!< 0x40000000 */ +#define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk /*!< DMA enable */ +#define PSSI_CR_OUTEN_Pos (31U) +#define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) /*!< 0x80000000 */ +#define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk /*!< Data direction selection */ + +/******************** Bit definition for PSSI_SR register *******************/ +#define PSSI_SR_RTT4B_Pos (2U) +#define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) /*!< 0x00000004 */ +#define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk /*!< Ready to transfer four bytes */ +#define PSSI_SR_RTT1B_Pos (3U) +#define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) /*!< 0x00000008 */ +#define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk /*!< Ready to transfer one byte */ + +/******************** Bit definition for PSSI_RIS register ******************/ +#define PSSI_RIS_OVR_RIS_Pos (1U) +#define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk /*!< Data buffer overrun/underrun raw interrupt status */ + +/******************** Bit definition for PSSI_IER register ******************/ +#define PSSI_IER_OVR_IE_Pos (1U) +#define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk /*!< Data buffer overrun/underrun interrupt enable */ + +/******************** Bit definition for PSSI_MIS register ******************/ +#define PSSI_MIS_OVR_MIS_Pos (1U) +#define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk /*!< Data buffer overrun/underrun masked interrupt status */ + +/******************** Bit definition for PSSI_ICR register ******************/ +#define PSSI_ICR_OVR_ISC_Pos (1U) +#define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk /*!< Data buffer overrun/underrun interrupt status clear */ + +/******************** Bit definition for PSSI_DR register *******************/ +#define PSSI_DR_DR_Pos (0U) +#define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) /*!< 0xFFFFFFF */ +#define PSSI_DR_DR PSSI_DR_DR_Msk /*!< Data register */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CR1 register *******************/ +#define PWR_CR1_SVOS_Pos (0U) +#define PWR_CR1_SVOS_Msk (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00000001 */ +#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection. */ + +#define PWR_CR1_PVDE_Pos (4U) +#define PWR_CR1_PVDE_Msk (0x1UL << PWR_CR1_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR1_PVDE PWR_CR1_PVDE_Msk /*!< Programmable Voltage detector enable. */ + +#define PWR_CR1_PLS_Pos (5U) +#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */ +#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */ + +#define PWR_CR1_DBP_Pos (8U) +#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */ + +#define PWR_CR1_FLPS_Pos (9U) +#define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) /*!< 0x00000200 */ +#define PWR_CR1_FLPS PWR_CR1_FLPS_Msk /*!< Flash low power mode in STOP */ + +#define PWR_CR1_BOOSTE_Pos (11U) +#define PWR_CR1_BOOSTE_Msk (0x1UL << PWR_CR1_BOOSTE_Pos) /*!< 0x00000800 */ +#define PWR_CR1_BOOSTE PWR_CR1_BOOSTE_Msk /*!< Analog Switch VBoost control. */ + +#define PWR_CR1_AVDREADY_Pos (12) +#define PWR_CR1_AVDREADY_Msk (0x1UL << PWR_CR1_AVDREADY_Pos) /*!< 0x00001000 */ +#define PWR_CR1_AVDREADY PWR_CR1_AVDREADY_Msk /*!< Analog Voltage Ready. */ + +#define PWR_CR1_AVDEN_Pos (13U) +#define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) /*!< 0x00002000 */ +#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */ + +#define PWR_CR1_ALS_Pos (14U) +#define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x0000A000 */ +#define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */ +#define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) /*!< 0x00004000 */ +#define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for PWR_SR1 register ********************/ +#define PWR_SR1_ACTVOS_Pos (0U) +#define PWR_SR1_ACTVOS_Msk (0x1UL << PWR_SR1_ACTVOS_Pos) /*!< 0x00000001 */ +#define PWR_SR1_ACTVOS PWR_SR1_ACTVOS_Msk /*!< VOS currently applied for VCORE voltage scaling selection */ + +#define PWR_SR1_ACTVOSRDY_Pos (1U) +#define PWR_SR1_ACTVOSRDY_Msk (0x1UL << PWR_SR1_ACTVOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_SR1_ACTVOSRDY PWR_SR1_ACTVOSRDY_Msk /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling */ + +#define PWR_SR1_PVDO_Pos (4U) +#define PWR_SR1_PVDO_Msk (0x1UL << PWR_SR1_PVDO_Pos) /*!< 0x00000010 */ +#define PWR_SR1_PVDO PWR_SR1_PVDO_Msk /*!< Programmable Voltage Detect Output */ + +#define PWR_SR1_AVDO_Pos (13U) +#define PWR_SR1_AVDO_Msk (0x1UL << PWR_SR1_AVDO_Pos) /*!< 0x00002000 */ +#define PWR_SR1_AVDO PWR_SR1_AVDO_Msk /*!< Analog Voltage Detect Output on VDDA */ + +/******************** Bit definition for PWR_CSR1 register ********************/ +#define PWR_CSR1_BREN_Pos (0U) +#define PWR_CSR1_BREN_Msk (0x1UL << PWR_CSR1_BREN_Pos) /*!< 0x00000001 */ +#define PWR_CSR1_BREN PWR_CSR1_BREN_Msk /*!< Backup regulator enable */ + +#define PWR_CSR1_MONEN_Pos (4U) +#define PWR_CSR1_MONEN_Msk (0x1UL << PWR_CSR1_MONEN_Pos) /*!< 0x00000010 */ +#define PWR_CSR1_MONEN PWR_CSR1_MONEN_Msk /*!< VBAT and temperature monitoring enable */ + +#define PWR_CSR1_BRRDY_Pos (16U) +#define PWR_CSR1_BRRDY_Msk (0x1UL << PWR_CSR1_BRRDY_Pos) /*!< 0x00010000 */ +#define PWR_CSR1_BRRDY PWR_CSR1_BRRDY_Msk /*!< Backup regulator ready */ + +#define PWR_CSR1_VBATL_Pos (20U) +#define PWR_CSR1_VBATL_Msk (0x1UL << PWR_CSR1_VBATL_Pos) /*!< 0x00100000 */ +#define PWR_CSR1_VBATL PWR_CSR1_VBATL_Msk /*!< Monitored VBAT level above low threshold */ + +#define PWR_CSR1_VBATH_Pos (21U) +#define PWR_CSR1_VBATH_Msk (0x1UL << PWR_CSR1_VBATH_Pos) /*!< 0x00200000 */ +#define PWR_CSR1_VBATH PWR_CSR1_VBATH_Msk /*!< Monitored VBAT level above high threshold */ + +#define PWR_CSR1_TEMPL_Pos (22U) +#define PWR_CSR1_TEMPL_Msk (0x1UL << PWR_CSR1_TEMPL_Pos) /*!< 0x00400000 */ +#define PWR_CSR1_TEMPL PWR_CSR1_TEMPL_Msk /*!< Monitored temperature level above low threshold */ + +#define PWR_CSR1_TEMPH_Pos (23U) +#define PWR_CSR1_TEMPH_Msk (0x1UL << PWR_CSR1_TEMPH_Pos) /*!< 0x00800000 */ +#define PWR_CSR1_TEMPH PWR_CSR1_TEMPH_Msk /*!< Monitored temperature level above high threshold */ + +/******************** Bit definition for PWR_CSR2 register ********************/ +#define PWR_CSR2_BYPASS_Pos (0U) +#define PWR_CSR2_BYPASS_Msk (0x1UL << PWR_CSR2_BYPASS_Pos) /*!< 0x00000001 */ +#define PWR_CSR2_BYPASS PWR_CSR2_BYPASS_Msk /*!< Power Management Unit bypass */ + +#define PWR_CSR2_LDOEN_Pos (1U) +#define PWR_CSR2_LDOEN_Msk (0x1UL << PWR_CSR2_LDOEN_Pos) /*!< 0x00000002 */ +#define PWR_CSR2_LDOEN PWR_CSR2_LDOEN_Msk /*!< Low Drop-Out regulator enable */ + +#define PWR_CSR2_SDEN_Pos (2U) +#define PWR_CSR2_SDEN_Msk (0x1UL << PWR_CSR2_SDEN_Pos) /*!< 0x00000004 */ +#define PWR_CSR2_SDEN PWR_CSR2_SDEN_Msk /*!< SMPS Step-down converter enable */ + +#define PWR_CSR2_SMPSEXTHP_Pos (3U) +#define PWR_CSR2_SMPSEXTHP_Msk (0x1UL << PWR_CSR2_SMPSEXTHP_Pos) /*!< 0x00000008 */ +#define PWR_CSR2_SMPSEXTHP PWR_CSR2_SMPSEXTHP_Msk /*!< SMPS external power delivery selection */ + +#define PWR_CSR2_SDHILEVEL_Pos (4U) +#define PWR_CSR2_SDHILEVEL_Msk (0x1UL << PWR_CSR2_SDHILEVEL_Pos) /*!< 0x00000030 */ +#define PWR_CSR2_SDHILEVEL PWR_CSR2_SDHILEVEL_Msk /*!< SMPS step-down converter voltage output for LDO or external supply */ + +#define PWR_CSR2_VBE_Pos (8U) +#define PWR_CSR2_VBE_Msk (0x1UL << PWR_CSR2_VBE_Pos) /*!< 0x00000100 */ +#define PWR_CSR2_VBE PWR_CSR2_VBE_Msk /*!< VBAT charging enable */ + +#define PWR_CSR2_VBRS_Pos (9U) +#define PWR_CSR2_VBRS_Msk (0x1UL << PWR_CSR2_VBRS_Pos) /*!< 0x00000200 */ +#define PWR_CSR2_VBRS PWR_CSR2_VBRS_Msk /*!< VBAT charging resistor selection */ + +#define PWR_CSR2_XSPICAP1_Pos (10U) +#define PWR_CSR2_XSPICAP1_Msk (0x3UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000C00 */ +#define PWR_CSR2_XSPICAP1 PWR_CSR2_XSPICAP1_Msk /*!< XSPI port 1 capacitor control bits */ +#define PWR_CSR2_XSPICAP1_0 (0x1UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000400 */ +#define PWR_CSR2_XSPICAP1_1 (0x2UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000800 */ + +#define PWR_CSR2_XSPICAP2_Pos (12U) +#define PWR_CSR2_XSPICAP2_Msk (0x3UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00003000 */ +#define PWR_CSR2_XSPICAP2 PWR_CSR2_XSPICAP2_Msk /*!< XSPI port 2 capacitor control bits */ +#define PWR_CSR2_XSPICAP2_0 (0x1UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00001000 */ +#define PWR_CSR2_XSPICAP2_1 (0x2UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00002000 */ + +#define PWR_CSR2_EN_XSPIM1_Pos (14U) +#define PWR_CSR2_EN_XSPIM1_Msk (0x1UL << PWR_CSR2_EN_XSPIM1_Pos) /*!< 0x00004000 */ +#define PWR_CSR2_EN_XSPIM1 PWR_CSR2_EN_XSPIM1_Msk /*!< XSPIM1 external supply enable */ + +#define PWR_CSR2_EN_XSPIM2_Pos (15U) +#define PWR_CSR2_EN_XSPIM2_Msk (0x1UL << PWR_CSR2_EN_XSPIM2_Pos) /*!< 0x00008000 */ +#define PWR_CSR2_EN_XSPIM2 PWR_CSR2_EN_XSPIM2_Msk /*!< XSPIM2 external supply enable */ + +#define PWR_CSR2_SDEXTRDY_Pos (16U) +#define PWR_CSR2_SDEXTRDY_Msk (0x1UL << PWR_CSR2_SDEXTRDY_Pos) /*!< 0x00010000 */ +#define PWR_CSR2_SDEXTRDY PWR_CSR2_SDEXTRDY_Msk /*!< SMPS External supply ready */ + +#define PWR_CSR2_USB33DEN_Pos (24U) +#define PWR_CSR2_USB33DEN_Msk (0x1UL << PWR_CSR2_USB33DEN_Pos) /*!< 0x01000000 */ +#define PWR_CSR2_USB33DEN PWR_CSR2_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */ + +#define PWR_CSR2_USBREGEN_Pos (25U) +#define PWR_CSR2_USBREGEN_Msk (0x1UL << PWR_CSR2_USBREGEN_Pos) /*!< 0x02000000 */ +#define PWR_CSR2_USBREGEN PWR_CSR2_USBREGEN_Msk /*!< USB regulator enable */ + +#define PWR_CSR2_USB33RDY_Pos (26U) +#define PWR_CSR2_USB33RDY_Msk (0x1UL << PWR_CSR2_USB33RDY_Pos) /*!< 0x04000000 */ +#define PWR_CSR2_USB33RDY PWR_CSR2_USB33RDY_Msk /*!< USB supply ready */ + +#define PWR_CSR2_USBHSREGEN_Pos (27U) +#define PWR_CSR2_USBHSREGEN_Msk (0x1UL << PWR_CSR2_USBHSREGEN_Pos) /*!< 0x08000000 */ +#define PWR_CSR2_USBHSREGEN PWR_CSR2_USBHSREGEN_Msk /*!< USB HS regulator enable */ + +/******************** Bit definition for PWR_CSR3 register ********************/ +#define PWR_CSR3_PDDS_Pos (0U) +#define PWR_CSR3_PDDS_Msk (0x1UL << PWR_CSR3_PDDS_Pos) /*!< 0x00000001 */ +#define PWR_CSR3_PDDS PWR_CSR3_PDDS_Msk /*!< D1 domain Power Down Deepsleep */ + +#define PWR_CSR3_CSSF_Pos (1U) +#define PWR_CSR3_CSSF_Msk (0x1UL << PWR_CSR3_CSSF_Pos) /*!< 0x00000002 */ +#define PWR_CSR3_CSSF PWR_CSR3_CSSF_Msk /*!< Clear Standby and Stop flag */ + +#define PWR_CSR3_STOPF_Pos (8U) +#define PWR_CSR3_STOPF_Msk (0x1UL << PWR_CSR3_STOPF_Pos) /*!< 0x00000080 */ +#define PWR_CSR3_STOPF PWR_CSR3_STOPF_Msk /*!< STOP Flag */ + +#define PWR_CSR3_SBF_Pos (9U) +#define PWR_CSR3_SBF_Msk (0x1UL << PWR_CSR3_SBF_Pos) /*!< 0x00000100 */ +#define PWR_CSR3_SBF PWR_CSR3_SBF_Msk /*!< System STANDBY Flag */ + +/******************** Bit definition for PWR_CSR4 register ********************/ +#define PWR_CSR4_VOS_Pos (0U) +#define PWR_CSR4_VOS_Msk (0x1UL << PWR_CSR4_VOS_Pos) /*!< 0x00000001 */ +#define PWR_CSR4_VOS PWR_CSR4_VOS_Msk /*!< Voltage Scaling selection according performance */ + +#define PWR_CSR4_VOSRDY_Pos (1U) +#define PWR_CSR4_VOSRDY_Msk (0x1UL << PWR_CSR4_VOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_CSR4_VOSRDY PWR_CSR4_VOSRDY_Msk /*!< VOSRDY: VOS Ready bit for VCORE voltage scaling output selection. */ + +/******************** Bit definition for PWR_WKUPCR register ********************/ +#define PWR_WKUPCR_WKUPC_Pos (0U) +#define PWR_WKUPCR_WKUPC_Msk (0xFUL << PWR_WKUPCR_WKUPC_Pos) /*!< 0x0000000F */ +#define PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC_Msk /*!< Clear Wakeup Pin Flag 1 to 4 */ +#define PWR_WKUPCR_WKUPC1_Pos (0U) +#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */ +#define PWR_WKUPCR_WKUPC2_Pos (1U) +#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */ +#define PWR_WKUPCR_WKUPC3_Pos (2U) +#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */ +#define PWR_WKUPCR_WKUPC4_Pos (3U) +#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */ + +/******************** Bit definition for PWR_WKUPFR register ********************/ +#define PWR_WKUPFR_WKUPF1_Pos (0U) +#define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */ +#define PWR_WKUPFR_WKUPF2_Pos (1U) +#define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */ +#define PWR_WKUPFR_WKUPF3_Pos (2U) +#define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */ +#define PWR_WKUPFR_WKUPF4_Pos (3U) +#define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */ + +/******************** Bit definition for PWR_WKUPEPR register ********************/ +#define PWR_WKUPEPR_WKUPEN_Pos (0U) +#define PWR_WKUPEPR_WKUPEN_Msk (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000000F */ +#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */ +#define PWR_WKUPEPR_WKUPEN1_Pos (0U) +#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup Pin WKUP1 */ +#define PWR_WKUPEPR_WKUPEN2_Pos (1U) +#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup Pin WKUP2 */ +#define PWR_WKUPEPR_WKUPEN3_Pos (2U) +#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup Pin WKUP3 */ +#define PWR_WKUPEPR_WKUPEN4_Pos (3U) +#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup Pin WKUP4 */ + +#define PWR_WKUPEPR_WKUPP_Pos (8U) +#define PWR_WKUPEPR_WKUPP_Msk (0x0FUL << PWR_WKUPEPR_WKUPP_Pos) /*!< 0x0000F00 */ +#define PWR_WKUPEPR_WKUPP PWR_WKUPEPR_WKUPP_Msk /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */ +#define PWR_WKUPEPR_WKUPP1_Pos (8U) +#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Pin Polarity for WKUP1 */ +#define PWR_WKUPEPR_WKUPP2_Pos (9U) +#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Pin Polarity for WKUP2 */ +#define PWR_WKUPEPR_WKUPP3_Pos (10U) +#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Pin Polarity for WKUP3 */ +#define PWR_WKUPEPR_WKUPP4_Pos (11U) +#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Pin Polarity for WKUP4 */ + +#define PWR_WKUPEPR_WKUPPUPD1_Pos (16U) +#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */ +#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WKUPEPR_WKUPPUPD2_Pos (18U) +#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */ +#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WKUPEPR_WKUPPUPD3_Pos (20U) +#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */ +#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WKUPEPR_WKUPPUPD4_Pos (22U) +#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */ +#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for PWR_UCPDRR register ********************/ +#define PWR_UCPDR_UCPD_DBDIS_Pos (0U) +#define PWR_UCPDR_UCPD_DBDIS_Msk (0x1UL << PWR_UCPDR_UCPD_DBDIS_Pos) /*!< 0x00000001 */ +#define PWR_UCPDR_UCPD_DBDIS PWR_UCPDR_UCPD_DBDIS_Msk /*!< UCPD dead battery disable */ + +#define PWR_UCPDR_UCPD_STBY_Pos (1U) +#define PWR_UCPDR_UCPD_STBY_Msk (0x1UL << PWR_UCPDR_UCPD_STBY_Pos) /*!< 0x00000002 */ +#define PWR_UCPDR_UCPD_STBY PWR_UCPDR_UCPD_STBY_Msk /*!< UCPD Standby mode */ + +/******************** Bit definition for PWR_APCR register ********************/ +#define PWR_APCR_APC_Pos (0U) +#define PWR_APCR_APC_Msk (0x1UL << PWR_APCR_APC_Pos) /*!< 0x00000001 */ +#define PWR_APCR_APC PWR_APCR_APC_Msk /*!< Apply pull configuration register */ + +#define PWR_APCR_PN7_PUPD_Pos (16U) +#define PWR_APCR_PN7_PUPD_Msk (0x1UL << PWR_APCR_PN7_PUPD_Pos) /*!< 0x00010000 */ +#define PWR_APCR_PN7_PUPD PWR_APCR_PN7_PUPD_Msk /*!< Port N bit 7 pull-up/down configuration */ + +#define PWR_APCR_PO5_PUPD_Pos (17) +#define PWR_APCR_PO5_PUPD_Msk (0x1UL << PWR_APCR_PO5_PUPD_Pos) /*!< 0x00020000 */ +#define PWR_APCR_PO5_PUPD PWR_APCR_PO5_PUPD_Msk /*!< Port O bit 5 pull-up/down configuration */ + +#define PWR_APCR_I3CPB6_PU_Pos (28U) +#define PWR_APCR_I3CPB6_PU_Msk (0x1UL << PWR_APCR_I3CPB6_PU_Pos) /*!< 0x10000000 */ +#define PWR_APCR_I3CPB6_PU PWR_APCR_I3CPB6_PU_Msk /*!< Port PB6 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB7_PU_Pos (29U) +#define PWR_APCR_I3CPB7_PU_Msk (0x1UL << PWR_APCR_I3CPB7_PU_Pos) /*!< 0x20000000 */ +#define PWR_APCR_I3CPB7_PU PWR_APCR_I3CPB7_PU_Msk /*!< Port PB7 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB8_PU_Pos (30U) +#define PWR_APCR_I3CPB8_PU_Msk (0x1UL << PWR_APCR_I3CPB8_PU_Pos) /*!< 0x40000000 */ +#define PWR_APCR_I3CPB8_PU PWR_APCR_I3CPB8_PU_Msk /*!< Port PB8 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB9_PU_Pos (31U) +#define PWR_APCR_I3CPB9_PU_Msk (0x1UL << PWR_APCR_I3CPB9_PU_Pos) /*!< 0x80000000 */ +#define PWR_APCR_I3CPB9_PU PWR_APCR_I3CPB9_PU_Msk /*!< Port PB9 I3C pull-up bit configuration */ + +/******************** Bit definition for PWR_PUCRN register ********************/ +#define PWR_PUCRN_PUN1_Pos (1U) +#define PWR_PUCRN_PUN1_Msk (0x1UL << PWR_PUCRN_PUN1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRN_PUN1 PWR_PUCRN_PUN1_Msk /*!< PUN1: Port N pull-up */ + +#define PWR_PUCRN_PUN6_Pos (6U) +#define PWR_PUCRN_PUN6_Msk (0x1UL << PWR_PUCRN_PUN6_Pos) /*!< 0x00000040 */ +#define PWR_PUCRN_PUN6 PWR_PUCRN_PUN6_Msk /*!< PUN6: Port N pull-up */ + +#define PWR_PUCRN_PUN12_Pos (12U) +#define PWR_PUCRN_PUN12_Msk (0x1UL << PWR_PUCRN_PUN12_Pos) /*!< 0x00001000 */ +#define PWR_PUCRN_PUN12 PWR_PUCRN_PUN12_Msk /*!< PUN12: Port N pull-up */ + +/******************** Bit definition for PWR_PDCRN register ********************/ +#define PWR_PDCRN_PDN0_Pos (0U) +#define PWR_PDCRN_PDN0_Msk (0x1UL << PWR_PDCRN_PDN0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRN_PDN0 PWR_PDCRN_PDN0_Msk /*!< PDN0: Port N pull-down */ + +#define PWR_PDCRN_PDN1_Pos (1U) +#define PWR_PDCRN_PDN1_Msk (0x1UL << PWR_PDCRN_PDN1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRN_PDN1 PWR_PDCRN_PDN1_Msk /*!< PDN1: Port N pull-down */ + +#define PWR_PDCRN_PDN2N5_Pos (2U) +#define PWR_PDCRN_PDN2N5_Msk (0x1UL << PWR_PDCRN_PDN2N5_Pos) /*!< 0x00000004 */ +#define PWR_PDCRN_PDN2N5 PWR_PDCRN_PDN2N5_Msk /*!< PDN2 to PDN5: Port N pull-down */ + +#define PWR_PDCRN_PDN6_Pos (6U) +#define PWR_PDCRN_PDN6_Msk (0x1UL << PWR_PDCRN_PDN6_Pos) /*!< 0x00000040 */ +#define PWR_PDCRN_PDN6 PWR_PDCRN_PDN6_Msk /*!< PDN6: Port N pull-down */ + +#define PWR_PDCRN_PDN8N11_Pos (8U) +#define PWR_PDCRN_PDN8N11_Msk (0x1UL << PWR_PDCRN_PDN8N11_Pos) /*!< 0x00000100 */ +#define PWR_PDCRN_PDN8N11 PWR_PDCRN_PDN8N11_Msk /*!< PDN8 to PDN11: Port N pull-down */ + +#define PWR_PDCRN_PDN12_Pos (12U) +#define PWR_PDCRN_PDN12_Msk (0x1UL << PWR_PDCRN_PDN12_Pos) /*!< 0x00001000 */ +#define PWR_PDCRN_PDN12 PWR_PDCRN_PDN12_Msk /*!< PDN12: Port N pull-down */ + +/******************** Bit definition for PWR_PUCRO register ********************/ +#define PWR_PUCRO_PUO0_Pos (0U) +#define PWR_PUCRO_PUO0_Msk (0x1UL << PWR_PUCRO_PUO0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRO_PUO0 PWR_PUCRO_PUO0_Msk /*!< PUO0: Port O pull-up */ + +#define PWR_PUCRO_PUO1_Pos (1U) +#define PWR_PUCRO_PUO1_Msk (0x1UL << PWR_PUCRO_PUO1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRO_PUO1 PWR_PUCRO_PUO1_Msk /*!< PUO1: Port O pull-up */ + +#define PWR_PUCRO_PUO4_Pos (4U) +#define PWR_PUCRO_PUO4_Msk (0x1UL << PWR_PUCRO_PUO4_Pos) /*!< 0x00000010 */ +#define PWR_PUCRO_PUO4 PWR_PUCRO_PUO4_Msk /*!< PUO4: Port O pull-up */ + +/******************** Bit definition for PWR_PDCRO register ********************/ +#define PWR_PDCRO_PDO0_Pos (0U) +#define PWR_PDCRO_PDO0_Msk (0x1UL << PWR_PDCRO_PDO0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRO_PDO0 PWR_PDCRO_PDO0_Msk /*!< PDO0: Port O pull-down */ + +#define PWR_PDCRO_PDO1_Pos (1U) +#define PWR_PDCRO_PDO1_Msk (0x1UL << PWR_PDCRO_PDO1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRO_PDO1 PWR_PDCRO_PDO1_Msk /*!< PDO1: Port O pull-down */ + +#define PWR_PDCRO_PDO2_Pos (2U) +#define PWR_PDCRO_PDO2_Msk (0x1UL << PWR_PDCRO_PDO2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRO_PDO2 PWR_PDCRO_PDO2_Msk /*!< PDO2: Port O pull-down */ + +#define PWR_PDCRO_PDO3_Pos (3U) +#define PWR_PDCRO_PDO3_Msk (0x1UL << PWR_PDCRO_PDO3_Pos) /*!< 0x00000008 */ +#define PWR_PDCRO_PDO3 PWR_PDCRO_PDO3_Msk /*!< PDO3: Port O pull-down */ + +#define PWR_PDCRO_PDO4_Pos (4U) +#define PWR_PDCRO_PDO4_Msk (0x1UL << PWR_PDCRO_PDO4_Pos) /*!< 0x00000010 */ +#define PWR_PDCRO_PDO4 PWR_PDCRO_PDO4_Msk /*!< PDO4: Port O pull-down */ + +/******************** Bit definition for PWR_PDCRP register ********************/ +#define PWR_PDCRP_PDP0P3_Pos (0U) +#define PWR_PDCRP_PDP0P3_Msk (0x1UL << PWR_PDCRP_PDP0P3_Pos) /*!< 0x00000001 */ +#define PWR_PDCRP_PDP0P3 PWR_PDCRP_PDP0P3_Msk /*!< PPO0 to PP03 : Port P pull-down */ + +#define PWR_PDCRP_PDP4P7_Pos (4U) +#define PWR_PDCRP_PDP4P7_Msk (0x1UL << PWR_PDCRP_PDP4P7_Pos) /*!< 0x00000010 */ +#define PWR_PDCRP_PDP4P7 PWR_PDCRP_PDP4P7_Msk /*!< PPO4 to PP07 : Port P pull-down */ + +#define PWR_PDCRP_PDP8P11_Pos (8U) +#define PWR_PDCRP_PDP8P11_Msk (0x1UL << PWR_PDCRP_PDP8P11_Pos) /*!< 0x00000100 */ +#define PWR_PDCRP_PDP8P11 PWR_PDCRP_PDP8P11_Msk /*!< PPO8 to PP11 : Port P pull-down */ + +#define PWR_PDCRP_PDP12P15_Pos (12U) +#define PWR_PDCRP_PDP12P15_Msk (0x1UL << PWR_PDCRP_PDP12P15_Pos) /*!< 0x00001000 */ +#define PWR_PDCRP_PDP12P15 PWR_PDCRP_PDP12P15_Msk /*!< PP12 to PP15 : Port P pull-down */ + + +/******************************************************************************/ +/* */ +/* RAM ECC monitoring */ +/* */ +/******************************************************************************/ +/****************** Bit definition for RAMECC_IER register ******************/ +#define RAMECC_IER_GIE_Pos (0U) +#define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) /*!< 0x00000001 */ +#define RAMECC_IER_GIE RAMECC_IER_GIE_Msk /*!< Global interrupt enable */ +#define RAMECC_IER_GECCSEIE_Pos (1U) +#define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) /*!< 0x00000002 */ +#define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk /*!< Global ECC single error interrupt enable */ +#define RAMECC_IER_GECCDEIE_Pos (2U) +#define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) /*!< 0x00000004 */ +#define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk /*!< Global ECC double error interrupt enable */ +#define RAMECC_IER_GECCDEBWIE_Pos (3U) +#define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) /*!< 0x00000008 */ +#define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk /*!< Global ECC double error on byte write (BW) interrupt enable */ + +/******************* Bit definition for RAMECC_CR register ******************/ +#define RAMECC_CR_ECCSEIE_Pos (2U) +#define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) /*!< 0x00000004 */ +#define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk /*!< ECC single error interrupt enable */ +#define RAMECC_CR_ECCDEIE_Pos (3U) +#define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) /*!< 0x00000008 */ +#define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk /*!< ECC double error interrupt enable */ +#define RAMECC_CR_ECCDEBWIE_Pos (4U) +#define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) /*!< 0x00000010 */ +#define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk /*!< ECC double error on byte write (BW) interrupt enable */ +#define RAMECC_CR_ECCELEN_Pos (5U) +#define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) /*!< 0x00000020 */ +#define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk /*!< ECC error latching enable */ + +/******************* Bit definition for RAMECC_SR register ******************/ +#define RAMECC_SR_SEDCF_Pos (0U) +#define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) /*!< 0x00000001 */ +#define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk /*!< ECC single error detected and corrected flag */ +#define RAMECC_SR_DEDF_Pos (1U) +#define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) /*!< 0x00000002 */ +#define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk /*!< ECC double error detected flag */ +#define RAMECC_SR_DEBWDF_Pos (2U) +#define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) /*!< 0x00000004 */ +#define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk /*!< ECC double error on byte write (BW) detected flag */ + +/****************** Bit definition for RAMECC_FAR register ******************/ +#define RAMECC_FAR_FADD_Pos (0U) +#define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk /*!< ECC error failing address */ + +/****************** Bit definition for RAMECC_FDRL register *****************/ +#define RAMECC_FDRL_FDATAL_Pos (0U) +#define RAMECC_FDRL_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FDRL_FDATAL_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FDRL_FDATAL RAMECC_FDRL_FDATAL_Msk /*!< Failing data low */ + +/****************** Bit definition for RAMECC_FDRH register *****************/ +#define RAMECC_FDRH_FDATAH_Pos (0U) +#define RAMECC_FDRH_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FDRH_FDATAH_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FDRH_FDATAH RAMECC_FDRH_FDATAH_Msk /* Failing data high (64-bit memory) */ + +/***************** Bit definition for RAMECC_FECR register ******************/ +#define RAMECC_FECR_FEC_Pos (0U) +#define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk /*!< Failing error code */ + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIKERON_Pos (1U) +#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable in Stop mode */ +#define RCC_CR_HSIRDY_Pos (2U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIV_Pos (3U) +#define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */ +#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< Internal High Speed clock divider selection */ +#define RCC_CR_HSIDIV_0 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSIDIV_1 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000010 */ + +#define RCC_CR_HSIDIVF_Pos (5U) +#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000020 */ +#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< HSI Divider flag */ +#define RCC_CR_CSION_Pos (7U) +#define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) /*!< 0x00000080 */ +#define RCC_CR_CSION RCC_CR_CSION_Msk /*!< The Internal RC 4MHz oscillator clock enable */ +#define RCC_CR_CSIRDY_Pos (8U) +#define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) /*!< 0x00000100 */ +#define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk /*!< The Internal RC 4MHz oscillator clock ready */ +#define RCC_CR_CSIKERON_Pos (9U) +#define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) /*!< 0x00000200 */ +#define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk /*!< Internal RC 4MHz oscillator clock enable in Stop mode */ +#define RCC_CR_HSI48ON_Pos (12U) +#define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) /*!< 0x00001000 */ +#define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk /*!< HSI48 clock enable clock enable */ +#define RCC_CR_HSI48RDY_Pos (13U) +#define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) /*!< 0x00002000 */ +#define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk /*!< HSI48 clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock bypass */ +#define RCC_CR_HSEEXT_Pos (19U) +#define RCC_CR_HSEEXT_Msk (0x1UL << RCC_CR_HSEEXT_Pos) /*!< 0x00100000 */ +#define RCC_CR_HSEEXT RCC_CR_HSEEXT_Msk /*!< External High Speed clock type in bypass mode */ +#define RCC_CR_HSECSSON_Pos (20U) +#define RCC_CR_HSECSSON_Msk (0x1UL << RCC_CR_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSECSSON RCC_CR_HSECSSON_Msk /*!< HSE Clock security System enable */ +#define RCC_CR_PLL1ON_Pos (24U) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */ +#define RCC_CR_PLL1RDY_Pos (25U) +#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready flag */ +#define RCC_CR_PLL2ON_Pos (26U) +#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */ +#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< System PLL2 clock enable */ +#define RCC_CR_PLL2RDY_Pos (27U) +#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */ +#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< System PLL2 clock ready flag */ +#define RCC_CR_PLL3ON_Pos (28U) +#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */ +#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< System PLL3 clock enable */ +#define RCC_CR_PLL3RDY_Pos (29U) +#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */ +#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< System PLL3 clock ready flag */ + +/******************** Bit definition for RCC_HSICFGR register ***************/ +/*!< HSICAL configuration */ +#define RCC_HSICFGR_HSICAL_Pos (0U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSICAL[11:0] bits */ +#define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */ +#define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */ +#define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */ +#define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */ +#define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */ +#define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */ +#define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */ + +/*!< HSITRIM configuration */ +#define RCC_HSICFGR_HSITRIM_Pos (24U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ +#define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CRRCR register *****************/ +/*!< HSI48CAL configuration */ +#define RCC_CRRCR_HSI48CAL_Pos (0U) +#define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */ +#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[9:0] bits */ +#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */ +#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */ +#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */ +#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */ +#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */ +#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */ +#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */ +#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */ +#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */ +#define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */ + +/******************** Bit definition for RCC_CSICFGR register ***************/ +/*!< CSICAL configuration */ +#define RCC_CSICFGR_CSICAL_Pos (0U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSICAL[7:0] bits */ +#define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */ +#define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */ +#define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */ +#define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */ +#define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */ +#define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */ +#define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */ +#define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */ + +/*!< CSITRIM configuration */ +#define RCC_CSICFGR_CSITRIM_Pos (24U) +#define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSITRIM[5:0] bits */ +#define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */ +#define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */ +#define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */ +#define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for RCC_CFGR register ******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock switch) */ +#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_Pos (3U) +#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System clock switch status) */ +#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ + +#define RCC_CFGR_STOPWUCK_Pos (6U) +#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */ +#define RCC_CFGR_STOPKERWUCK_Pos (7U) +#define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) /*!< 0x00000080 */ +#define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk /*!< Kernel Clock Selection after a Wake Up from Stop */ + +/*!< RTCPRE configuration */ +#define RCC_CFGR_RTCPRE_Pos (8U) +#define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00003F00 */ +#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk /*!< RTCPRE[5:0] bits (HSE division factor for RTC clock) */ +#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00002000 */ + +#define RCC_CFGR_TIMPRE_Pos (15U) +#define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos) /*!< 0x00008000 */ +#define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk /*!< TIMPRE configuration */ + +#define RCC_CFGR_MCO1PRE_Pos (18U) +#define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk /*!< MCO1 configuration */ +#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00200000 */ + +#define RCC_CFGR_MCO1SEL_Pos (22U) +#define RCC_CFGR_MCO1SEL_Msk (0x7UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x01C00000 */ +#define RCC_CFGR_MCO1SEL RCC_CFGR_MCO1SEL_Msk /*!< MCO1SEL [2:0] bits (MCO1 clock output selection) */ +#define RCC_CFGR_MCO1SEL_0 (0x1UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_MCO1SEL_1 (0x2UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x00800000 */ +#define RCC_CFGR_MCO1SEL_2 (0x4UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x01000000 */ + +#define RCC_CFGR_MCO2PRE_Pos (25U) +#define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x1E000000 */ +#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< MCO2 configuration */ +#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */ + +#define RCC_CFGR_MCO2SEL_Pos (29U) +#define RCC_CFGR_MCO2SEL_Msk (0x7UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0xE0000000 */ +#define RCC_CFGR_MCO2SEL RCC_CFGR_MCO2SEL_Msk /*!< MCO2SEL [2:0] bits (MCO2 clock output selection) */ +#define RCC_CFGR_MCO2SEL_0 (0x1UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x20000000 */ +#define RCC_CFGR_MCO2SEL_1 (0x2UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x40000000 */ +#define RCC_CFGR_MCO2SEL_2 (0x4UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for RCC_CDCFGR register ****************/ +/*!< CPRE configuration */ +#define RCC_CDCFGR_CPRE_Pos (0U) +#define RCC_CDCFGR_CPRE_Msk (0xFUL << RCC_CDCFGR_CPRE_Pos) /*!< 0x0000000F */ +#define RCC_CDCFGR_CPRE RCC_CDCFGR_CPRE_Msk /*!< CPRE[3:0] bits */ +#define RCC_CDCFGR_CPRE_0 (0x1UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000001 */ +#define RCC_CDCFGR_CPRE_1 (0x2UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000002 */ +#define RCC_CDCFGR_CPRE_2 (0x4UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000004 */ +#define RCC_CDCFGR_CPRE_3 (0x8UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for RCC_BMCFGR register ****************/ +/*!< BMPRE configuration */ +#define RCC_BMCFGR_BMPRE_Pos (0U) +#define RCC_BMCFGR_BMPRE_Msk (0xFUL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x0000000F */ +#define RCC_BMCFGR_BMPRE RCC_BMCFGR_BMPRE_Msk /*!< BMPRE[3:0] bits */ +#define RCC_BMCFGR_BMPRE_0 (0x1UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000001 */ +#define RCC_BMCFGR_BMPRE_1 (0x2UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000002 */ +#define RCC_BMCFGR_BMPRE_2 (0x4UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000004 */ +#define RCC_BMCFGR_BMPRE_3 (0x8UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for RCC_APBCFGR register ***************/ +/*!< APB1 prescaler configuration */ +#define RCC_APBCFGR_PPRE1_Pos (0U) +#define RCC_APBCFGR_PPRE1_Msk (0x7UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000007 */ +#define RCC_APBCFGR_PPRE1 RCC_APBCFGR_PPRE1_Msk /*!< PPRE1[2:0] bits */ +#define RCC_APBCFGR_PPRE1_0 (0x1UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000001 */ +#define RCC_APBCFGR_PPRE1_1 (0x2UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000002 */ +#define RCC_APBCFGR_PPRE1_2 (0x4UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000004 */ + +/*!< APB2 prescaler configuration */ +#define RCC_APBCFGR_PPRE2_Pos (4U) +#define RCC_APBCFGR_PPRE2_Msk (0x7UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000070 */ +#define RCC_APBCFGR_PPRE2 RCC_APBCFGR_PPRE2_Msk /*!< PPRE2[2:0] bits */ +#define RCC_APBCFGR_PPRE2_0 (0x1UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000010 */ +#define RCC_APBCFGR_PPRE2_1 (0x2UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000020 */ +#define RCC_APBCFGR_PPRE2_2 (0x4UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000040 */ + +/*!< APB4 prescaler configuration */ +#define RCC_APBCFGR_PPRE4_Pos (8U) +#define RCC_APBCFGR_PPRE4_Msk (0x7UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000700 */ +#define RCC_APBCFGR_PPRE4 RCC_APBCFGR_PPRE4_Msk /*!< PPRE4[2:0] bits */ +#define RCC_APBCFGR_PPRE4_0 (0x1UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000100 */ +#define RCC_APBCFGR_PPRE4_1 (0x2UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000200 */ +#define RCC_APBCFGR_PPRE4_2 (0x4UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000400 */ + +/*!< APB5 prescaler configuration */ +#define RCC_APBCFGR_PPRE5_Pos (12U) +#define RCC_APBCFGR_PPRE5_Msk (0x7UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00007000 */ +#define RCC_APBCFGR_PPRE5 RCC_APBCFGR_PPRE5_Msk /*!< PPRE5[2:0] bits */ +#define RCC_APBCFGR_PPRE5_0 (0x1UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00001000 */ +#define RCC_APBCFGR_PPRE5_1 (0x2UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00002000 */ +#define RCC_APBCFGR_PPRE5_2 (0x4UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_PLLCKSELR register *************/ +#define RCC_PLLCKSELR_PLLSRC_Pos (0U) +#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ +#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk /*!< DIVMx and PLLs clock source selection */ +#define RCC_PLLCKSELR_PLLSRC_0 (0x01UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000010 */ +#define RCC_PLLCKSELR_PLLSRC_1 (0x02UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000020 */ + +#define RCC_PLLCKSELR_DIVM1_Pos (4U) +#define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */ +#define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk /*!< DIVM1[5:0] bits */ +#define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */ +#define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */ +#define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */ +#define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */ +#define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */ +#define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */ + +#define RCC_PLLCKSELR_DIVM2_Pos (12U) +#define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */ +#define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk /*!< DIVM2[5:0] bits */ +#define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */ +#define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */ +#define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */ +#define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */ +#define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */ + +#define RCC_PLLCKSELR_DIVM3_Pos (20U) +#define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */ +#define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk /*!< DIVM3[5:0] bits */ +#define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */ +#define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */ +#define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */ +#define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for RCC_PLLCFGR register ***************/ +#define RCC_PLLCFGR_PLL1FRACEN_Pos (0U) +#define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */ +#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk /*!< PLL1 fractional latch enable */ +#define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U) +#define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */ +#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk /*!< PLL1 VCO selection */ +#define RCC_PLLCFGR_PLL1SSCGEN_Pos (2U) +#define RCC_PLLCFGR_PLL1SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL1SSCGEN_Pos) /*!< 0x00000004 */ +#define RCC_PLLCFGR_PLL1SSCGEN RCC_PLLCFGR_PLL1SSCGEN_Msk /*!< PLL1 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL1RGE_Pos (3U) +#define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000018 */ +#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk /*!< PLL1RGE[1:0] bits: PLL1 input frequency range */ +#define RCC_PLLCFGR_PLL1RGE_0 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */ +#define RCC_PLLCFGR_PLL1RGE_1 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000010 */ + +#define RCC_PLLCFGR_PLL1PEN_Pos (5U) +#define RCC_PLLCFGR_PLL1PEN_Msk (0x1UL << RCC_PLLCFGR_PLL1PEN_Pos) /*!< 0x00000020 */ +#define RCC_PLLCFGR_PLL1PEN RCC_PLLCFGR_PLL1PEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL1QEN_Pos (6U) +#define RCC_PLLCFGR_PLL1QEN_Msk (0x1UL << RCC_PLLCFGR_PLL1QEN_Pos) /*!< 0x00000040 */ +#define RCC_PLLCFGR_PLL1QEN RCC_PLLCFGR_PLL1QEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL1REN_Pos (7U) +#define RCC_PLLCFGR_PLL1REN_Msk (0x1UL << RCC_PLLCFGR_PLL1REN_Pos) /*!< 0x00000080 */ +#define RCC_PLLCFGR_PLL1REN RCC_PLLCFGR_PLL1REN_Msk /*!< PLL1 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL1SEN_Pos (8U) +#define RCC_PLLCFGR_PLL1SEN_Msk (0x1UL << RCC_PLLCFGR_PLL1SEN_Pos) /*!< 0x00000100 */ +#define RCC_PLLCFGR_PLL1SEN RCC_PLLCFGR_PLL1SEN_Msk /*!< PLL1 DIVS divider output enable */ + +#define RCC_PLLCFGR_PLL2FRACEN_Pos (11U) +#define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000800 */ +#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk /*!< PLL2 fractional latch enable */ +#define RCC_PLLCFGR_PLL2VCOSEL_Pos (12U) +#define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00001000 */ +#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk /*!< PLL2 VCO selection */ +#define RCC_PLLCFGR_PLL2SSCGEN_Pos (13U) +#define RCC_PLLCFGR_PLL2SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL2SSCGEN_Pos) /*!< 0x00002000 */ +#define RCC_PLLCFGR_PLL2SSCGEN RCC_PLLCFGR_PLL2SSCGEN_Msk /*!< PLL2 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL2RGE_Pos (14U) +#define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x0000C000 */ +#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk /*!< PLL2RGE[1:0] bits: PLL2 input frequency range */ +#define RCC_PLLCFGR_PLL2RGE_0 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00004000 */ +#define RCC_PLLCFGR_PLL2RGE_1 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00008000 */ + +#define RCC_PLLCFGR_PLL2PEN_Pos (16U) +#define RCC_PLLCFGR_PLL2PEN_Msk (0x1UL << RCC_PLLCFGR_PLL2PEN_Pos) /*!< 0x00010000 */ +#define RCC_PLLCFGR_PLL2PEN RCC_PLLCFGR_PLL2PEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL2QEN_Pos (17U) +#define RCC_PLLCFGR_PLL2QEN_Msk (0x1UL << RCC_PLLCFGR_PLL2QEN_Pos) /*!< 0x00020000 */ +#define RCC_PLLCFGR_PLL2QEN RCC_PLLCFGR_PLL2QEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL2REN_Pos (18U) +#define RCC_PLLCFGR_PLL2REN_Msk (0x1UL << RCC_PLLCFGR_PLL2REN_Pos) /*!< 0x00040000 */ +#define RCC_PLLCFGR_PLL2REN RCC_PLLCFGR_PLL2REN_Msk /*!< PLL2 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL2SEN_Pos (19U) +#define RCC_PLLCFGR_PLL2SEN_Msk (0x1UL << RCC_PLLCFGR_PLL2SEN_Pos) /*!< 0x00080000 */ +#define RCC_PLLCFGR_PLL2SEN RCC_PLLCFGR_PLL2SEN_Msk /*!< PLL2 DIVS divider output enable */ +#define RCC_PLLCFGR_PLL2TEN_Pos (20U) +#define RCC_PLLCFGR_PLL2TEN_Msk (0x1UL << RCC_PLLCFGR_PLL2TEN_Pos) /*!< 0x00100000 */ +#define RCC_PLLCFGR_PLL2TEN RCC_PLLCFGR_PLL2TEN_Msk /*!< PLL2 DIVT divider output enable */ + +#define RCC_PLLCFGR_PLL3FRACEN_Pos (22U) +#define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00400000 */ +#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk /*!< PLL3 fractional latch enable */ +#define RCC_PLLCFGR_PLL3VCOSEL_Pos (23U) +#define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00800000 */ +#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk /*!< PLL3 VCO selection */ +#define RCC_PLLCFGR_PLL3SSCGEN_Pos (24U) +#define RCC_PLLCFGR_PLL3SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL3SSCGEN_Pos) /*!< 0x01000000 */ +#define RCC_PLLCFGR_PLL3SSCGEN RCC_PLLCFGR_PLL3SSCGEN_Msk /*!< PLL3 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL3RGE_Pos (25U) +#define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x06000000 */ +#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk /*!< PLL3RGE[1:0] bits: PLL3 input frequency range */ +#define RCC_PLLCFGR_PLL3RGE_0 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x02000000 */ +#define RCC_PLLCFGR_PLL3RGE_1 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x04000000 */ + +#define RCC_PLLCFGR_PLL3PEN_Pos (27U) +#define RCC_PLLCFGR_PLL3PEN_Msk (0x1UL << RCC_PLLCFGR_PLL3PEN_Pos) /*!< 0x08000000 */ +#define RCC_PLLCFGR_PLL3PEN RCC_PLLCFGR_PLL3PEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL3QEN_Pos (28U) +#define RCC_PLLCFGR_PLL3QEN_Msk (0x1UL << RCC_PLLCFGR_PLL3QEN_Pos) /*!< 0x10000000 */ +#define RCC_PLLCFGR_PLL3QEN RCC_PLLCFGR_PLL3QEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL3REN_Pos (29U) +#define RCC_PLLCFGR_PLL3REN_Msk (0x1UL << RCC_PLLCFGR_PLL3REN_Pos) /*!< 0x20000000 */ +#define RCC_PLLCFGR_PLL3REN RCC_PLLCFGR_PLL3REN_Msk /*!< PLL3 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL3SEN_Pos (30U) +#define RCC_PLLCFGR_PLL3SEN_Msk (0x1UL << RCC_PLLCFGR_PLL3SEN_Pos) /*!< 0x40000000 */ +#define RCC_PLLCFGR_PLL3SEN RCC_PLLCFGR_PLL3SEN_Msk /*!< PLL3 DIVS divider output enable */ + +/******************** Bit definition for RCC_PLL1DIVR1 register *************/ +#define RCC_PLL1DIVR1_DIVN_Pos (0U) +#define RCC_PLL1DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1DIVR1_DIVN RCC_PLL1DIVR1_DIVN_Msk /*!< DIVN1[8:0] bits: PLL1 DIVN division factor */ +#define RCC_PLL1DIVR1_DIVN_0 (0x001UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR1_DIVN_1 (0x002UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR1_DIVN_2 (0x004UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1DIVR1_DIVN_3 (0x008UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1DIVR1_DIVN_4 (0x010UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1DIVR1_DIVN_5 (0x020UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1DIVR1_DIVN_6 (0x040UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1DIVR1_DIVN_7 (0x080UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1DIVR1_DIVN_8 (0x100UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL1DIVR1_DIVP_Pos (9U) +#define RCC_PLL1DIVR1_DIVP_Msk (0x7FUL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL1DIVR1_DIVP RCC_PLL1DIVR1_DIVP_Msk /*!< DIVP1[6:0] bits: PLL1 DIVP division factor */ +#define RCC_PLL1DIVR1_DIVP_0 (0x001UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL1DIVR1_DIVP_1 (0x002UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL1DIVR1_DIVP_2 (0x004UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL1DIVR1_DIVP_3 (0x008UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL1DIVR1_DIVP_4 (0x010UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL1DIVR1_DIVP_5 (0x020UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL1DIVR1_DIVP_6 (0x040UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL1DIVR1_DIVQ_Pos (16U) +#define RCC_PLL1DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1DIVR1_DIVQ RCC_PLL1DIVR1_DIVQ_Msk /*!< DIVQ1[6:0] bits: PLL1 DIVQ division factor */ +#define RCC_PLL1DIVR1_DIVQ_0 (0x001UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL1DIVR1_DIVQ_1 (0x002UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL1DIVR1_DIVQ_2 (0x004UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL1DIVR1_DIVQ_3 (0x008UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL1DIVR1_DIVQ_4 (0x010UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL1DIVR1_DIVQ_5 (0x020UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL1DIVR1_DIVQ_6 (0x040UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL1DIVR1_DIVR_Pos (24U) +#define RCC_PLL1DIVR1_DIVR_Msk (0x7FUL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL1DIVR1_DIVR RCC_PLL1DIVR1_DIVR_Msk /*!< DIVR1[6:0] bits: PLL1 DIVR division factor */ +#define RCC_PLL1DIVR1_DIVR_0 (0x001UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL1DIVR1_DIVR_1 (0x002UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL1DIVR1_DIVR_2 (0x004UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL1DIVR1_DIVR_3 (0x008UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL1DIVR1_DIVR_4 (0x010UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL1DIVR1_DIVR_5 (0x020UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL1DIVR1_DIVR_6 (0x040UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL1FRACR register *************/ +#define RCC_PLL1FRACR_FRACN_Pos (3U) +#define RCC_PLL1FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACN RCC_PLL1FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_PLL2DIVR1 register *************/ +#define RCC_PLL2DIVR1_DIVN_Pos (0U) +#define RCC_PLL2DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2DIVR1_DIVN RCC_PLL2DIVR1_DIVN_Msk /*!< DIVN2[8:0] bits: PLL2 DIVN division factor */ +#define RCC_PLL2DIVR1_DIVN_0 (0x001UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2DIVR1_DIVN_1 (0x002UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2DIVR1_DIVN_2 (0x004UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2DIVR1_DIVN_3 (0x008UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2DIVR1_DIVN_4 (0x010UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2DIVR1_DIVN_5 (0x020UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2DIVR1_DIVN_6 (0x040UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2DIVR1_DIVN_7 (0x080UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2DIVR1_DIVN_8 (0x100UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL2DIVR1_DIVP_Pos (9U) +#define RCC_PLL2DIVR1_DIVP_Msk (0x7FUL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL2DIVR1_DIVP RCC_PLL2DIVR1_DIVP_Msk /*!< DIVP2[6:0] bits: PLL2 DIVP division factor */ +#define RCC_PLL2DIVR1_DIVP_0 (0x001UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL2DIVR1_DIVP_1 (0x002UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL2DIVR1_DIVP_2 (0x004UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL2DIVR1_DIVP_3 (0x008UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL2DIVR1_DIVP_4 (0x010UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL2DIVR1_DIVP_5 (0x020UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL2DIVR1_DIVP_6 (0x040UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL2DIVR1_DIVQ_Pos (16U) +#define RCC_PLL2DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2DIVR1_DIVQ RCC_PLL2DIVR1_DIVQ_Msk /*!< DIVQ2[6:0] bits: PLL2 DIVQ division factor */ +#define RCC_PLL2DIVR1_DIVQ_0 (0x001UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL2DIVR1_DIVQ_1 (0x002UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL2DIVR1_DIVQ_2 (0x004UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL2DIVR1_DIVQ_3 (0x008UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL2DIVR1_DIVQ_4 (0x010UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL2DIVR1_DIVQ_5 (0x020UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL2DIVR1_DIVQ_6 (0x040UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL2DIVR1_DIVR_Pos (24U) +#define RCC_PLL2DIVR1_DIVR_Msk (0x7FUL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL2DIVR1_DIVR RCC_PLL2DIVR1_DIVR_Msk /*!< DIVR2[6:0] bits: PLL2 DIVR division factor */ +#define RCC_PLL2DIVR1_DIVR_0 (0x001UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL2DIVR1_DIVR_1 (0x002UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL2DIVR1_DIVR_2 (0x004UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL2DIVR1_DIVR_3 (0x008UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL2DIVR1_DIVR_4 (0x010UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL2DIVR1_DIVR_5 (0x020UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL2DIVR1_DIVR_6 (0x040UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL2FRACR register *************/ +#define RCC_PLL2FRACR_FRACN_Pos (3U) +#define RCC_PLL2FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACN RCC_PLL2FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_PLL3DIVR1 register *************/ +#define RCC_PLL3DIVR1_DIVN_Pos (0U) +#define RCC_PLL3DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3DIVR1_DIVN RCC_PLL3DIVR1_DIVN_Msk /*!< DIVN3[8:0] bits: PLL3 DIVN division factor */ +#define RCC_PLL3DIVR1_DIVN_0 (0x001UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3DIVR1_DIVN_1 (0x002UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3DIVR1_DIVN_2 (0x004UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3DIVR1_DIVN_3 (0x008UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3DIVR1_DIVN_4 (0x010UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3DIVR1_DIVN_5 (0x020UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3DIVR1_DIVN_6 (0x040UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3DIVR1_DIVN_7 (0x080UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3DIVR1_DIVN_8 (0x100UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL3DIVR1_DIVP_Pos (9U) +#define RCC_PLL3DIVR1_DIVP_Msk (0x7FUL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL3DIVR1_DIVP RCC_PLL3DIVR1_DIVP_Msk /*!< DIVP3[6:0] bits: PLL3 DIVP division factor */ +#define RCC_PLL3DIVR1_DIVP_0 (0x001UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL3DIVR1_DIVP_1 (0x002UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL3DIVR1_DIVP_2 (0x004UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL3DIVR1_DIVP_3 (0x008UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL3DIVR1_DIVP_4 (0x010UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL3DIVR1_DIVP_5 (0x020UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL3DIVR1_DIVP_6 (0x040UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL3DIVR1_DIVQ_Pos (16U) +#define RCC_PLL3DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3DIVR1_DIVQ RCC_PLL3DIVR1_DIVQ_Msk /*!< DIVQ3[6:0] bits: PLL3 DIVQ division factor */ +#define RCC_PLL3DIVR1_DIVQ_0 (0x001UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL3DIVR1_DIVQ_1 (0x002UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL3DIVR1_DIVQ_2 (0x004UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL3DIVR1_DIVQ_3 (0x008UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL3DIVR1_DIVQ_4 (0x010UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL3DIVR1_DIVQ_5 (0x020UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL3DIVR1_DIVQ_6 (0x040UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL3DIVR1_DIVR_Pos (24U) +#define RCC_PLL3DIVR1_DIVR_Msk (0x7FUL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL3DIVR1_DIVR RCC_PLL3DIVR1_DIVR_Msk /*!< DIVR3[6:0] bits: PLL3 DIVR division factor */ +#define RCC_PLL3DIVR1_DIVR_0 (0x001UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL3DIVR1_DIVR_1 (0x002UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL3DIVR1_DIVR_2 (0x004UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL3DIVR1_DIVR_3 (0x008UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL3DIVR1_DIVR_4 (0x010UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL3DIVR1_DIVR_5 (0x020UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL3DIVR1_DIVR_6 (0x040UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL3FRACR register *************/ +#define RCC_PLL3FRACR_FRACN_Pos (3U) +#define RCC_PLL3FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACN RCC_PLL3FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_CCIPR1 register **************/ +#define RCC_CCIPR1_FMCSEL_Pos (0U) +#define RCC_CCIPR1_FMCSEL_Msk (0x3UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_FMCSEL RCC_CCIPR1_FMCSEL_Msk +#define RCC_CCIPR1_FMCSEL_0 (0x1UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_FMCSEL_1 (0x2UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000002 */ + +#define RCC_CCIPR1_SDMMC12SEL_Pos (2U) +#define RCC_CCIPR1_SDMMC12SEL_Msk (0x1UL << RCC_CCIPR1_SDMMC12SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_SDMMC12SEL RCC_CCIPR1_SDMMC12SEL_Msk + +#define RCC_CCIPR1_XSPI1SEL_Pos (4U) +#define RCC_CCIPR1_XSPI1SEL_Msk (0x3UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR1_XSPI1SEL RCC_CCIPR1_XSPI1SEL_Msk +#define RCC_CCIPR1_XSPI1SEL_0 (0x1UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_XSPI1SEL_1 (0x2UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000020 */ + +#define RCC_CCIPR1_XSPI2SEL_Pos (6U) +#define RCC_CCIPR1_XSPI2SEL_Msk (0x3UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR1_XSPI2SEL RCC_CCIPR1_XSPI2SEL_Msk +#define RCC_CCIPR1_XSPI2SEL_0 (0x1UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_XSPI2SEL_1 (0x2UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x00000080 */ + +#define RCC_CCIPR1_USBREFCKSEL_Pos (8U) +#define RCC_CCIPR1_USBREFCKSEL_Msk (0xFUL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000F00 */ +#define RCC_CCIPR1_USBREFCKSEL RCC_CCIPR1_USBREFCKSEL_Msk +#define RCC_CCIPR1_USBREFCKSEL_0 (0x1UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_USBREFCKSEL_1 (0x2UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_USBREFCKSEL_2 (0x4UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_USBREFCKSEL_3 (0x8UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000800 */ + +#define RCC_CCIPR1_USBPHYCSEL_Pos (12U) +#define RCC_CCIPR1_USBPHYCSEL_Msk (0x3UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR1_USBPHYCSEL RCC_CCIPR1_USBPHYCSEL_Msk +#define RCC_CCIPR1_USBPHYCSEL_0 (0x1UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR1_USBPHYCSEL_1 (0x2UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00002000 */ + +#define RCC_CCIPR1_OTGFSSEL_Pos (14U) +#define RCC_CCIPR1_OTGFSSEL_Msk (0x3UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_OTGFSSEL RCC_CCIPR1_OTGFSSEL_Msk +#define RCC_CCIPR1_OTGFSSEL_0 (0x1UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_OTGFSSEL_1 (0x2UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x00008000 */ + +#define RCC_CCIPR1_ETH1REFCKSEL_Pos (16U) +#define RCC_CCIPR1_ETH1REFCKSEL_Msk (0x3UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_ETH1REFCKSEL RCC_CCIPR1_ETH1REFCKSEL_Msk +#define RCC_CCIPR1_ETH1REFCKSEL_0 (0x1UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_ETH1REFCKSEL_1 (0x2UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00020000 */ + +#define RCC_CCIPR1_ETH1PHYCKSEL_Pos (18U) +#define RCC_CCIPR1_ETH1PHYCKSEL_Msk (0x1UL << RCC_CCIPR1_ETH1PHYCKSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_ETH1PHYCKSEL RCC_CCIPR1_ETH1PHYCKSEL_Msk + +#define RCC_CCIPR1_ADF1SEL_Pos (20U) +#define RCC_CCIPR1_ADF1SEL_Msk (0x7UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR1_ADF1SEL RCC_CCIPR1_ADF1SEL_Msk +#define RCC_CCIPR1_ADF1SEL_0 (0x1UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_ADF1SEL_1 (0x2UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR1_ADF1SEL_2 (0x4UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00400000 */ + +#define RCC_CCIPR1_ADCSEL_Pos (24U) +#define RCC_CCIPR1_ADCSEL_Msk (0x3UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR1_ADCSEL RCC_CCIPR1_ADCSEL_Msk +#define RCC_CCIPR1_ADCSEL_0 (0x1UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR1_ADCSEL_1 (0x2UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x02000000 */ + +#define RCC_CCIPR1_PSSISEL_Pos (27U) +#define RCC_CCIPR1_PSSISEL_Msk (0x1UL << RCC_CCIPR1_PSSISEL_Pos) /*!< 0x08000000 */ +#define RCC_CCIPR1_PSSISEL RCC_CCIPR1_PSSISEL_Msk + +#define RCC_CCIPR1_CKPERSEL_Pos (28U) +#define RCC_CCIPR1_CKPERSEL_Msk (0x3UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x30000000 */ +#define RCC_CCIPR1_CKPERSEL RCC_CCIPR1_CKPERSEL_Msk +#define RCC_CCIPR1_CKPERSEL_0 (0x1UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR1_CKPERSEL_1 (0x2UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for RCC_CCIPR2 register *************/ +#define RCC_CCIPR2_UART234578SEL_Pos (0U) +#define RCC_CCIPR2_UART234578SEL_Msk (0x7UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR2_UART234578SEL RCC_CCIPR2_UART234578SEL_Msk +#define RCC_CCIPR2_UART234578SEL_0 (0x1UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_UART234578SEL_1 (0x2UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_UART234578SEL_2 (0x4UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR2_SPI23SEL_Pos (4U) +#define RCC_CCIPR2_SPI23SEL_Msk (0x7UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR2_SPI23SEL RCC_CCIPR2_SPI23SEL_Msk +#define RCC_CCIPR2_SPI23SEL_0 (0x1UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR2_SPI23SEL_1 (0x2UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR2_SPI23SEL_2 (0x4UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR2_I2C23SEL_Pos (8U) +#define RCC_CCIPR2_I2C23SEL_Msk (0x3UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR2_I2C23SEL RCC_CCIPR2_I2C23SEL_Msk +#define RCC_CCIPR2_I2C23SEL_0 (0x1UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR2_I2C23SEL_1 (0x2UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000200 */ + +#define RCC_CCIPR2_I2C1_I3C1SEL_Pos (12U) +#define RCC_CCIPR2_I2C1_I3C1SEL_Msk (0x3UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR2_I2C1_I3C1SEL RCC_CCIPR2_I2C1_I3C1SEL_Msk +#define RCC_CCIPR2_I2C1_I3C1SEL_0 (0x1UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_I2C1_I3C1SEL_1 (0x2UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00002000 */ + +#define RCC_CCIPR2_LPTIM1SEL_Pos (16U) +#define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR2_LPTIM1SEL RCC_CCIPR2_LPTIM1SEL_Msk +#define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00040000 */ + +#define RCC_CCIPR2_FDCANSEL_Pos (22U) +#define RCC_CCIPR2_FDCANSEL_Msk (0x3UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00C00000 */ +#define RCC_CCIPR2_FDCANSEL RCC_CCIPR2_FDCANSEL_Msk +#define RCC_CCIPR2_FDCANSEL_0 (0x1UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR2_FDCANSEL_1 (0x2UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00800000 */ + +#define RCC_CCIPR2_SPDIFRXSEL_Pos (24U) +#define RCC_CCIPR2_SPDIFRXSEL_Msk (0x3UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_SPDIFRXSEL RCC_CCIPR2_SPDIFRXSEL_Msk +#define RCC_CCIPR2_SPDIFRXSEL_0 (0x1UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_SPDIFRXSEL_1 (0x2UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x02000000 */ + +#define RCC_CCIPR2_CECSEL_Pos (28U) +#define RCC_CCIPR2_CECSEL_Msk (0x3UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_CECSEL RCC_CCIPR2_CECSEL_Msk +#define RCC_CCIPR2_CECSEL_0 (0x1UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_CECSEL_1 (0x2UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for RCC_CCIPR3 register *************/ +#define RCC_CCIPR3_USART1SEL_Pos (0U) +#define RCC_CCIPR3_USART1SEL_Msk (0x7UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR3_USART1SEL RCC_CCIPR3_USART1SEL_Msk +#define RCC_CCIPR3_USART1SEL_0 (0x1UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_USART1SEL_1 (0x2UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_USART1SEL_2 (0x4UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR3_SPI45SEL_Pos (4U) +#define RCC_CCIPR3_SPI45SEL_Msk (0x7UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR3_SPI45SEL RCC_CCIPR3_SPI45SEL_Msk +#define RCC_CCIPR3_SPI45SEL_0 (0x1UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_SPI45SEL_1 (0x2UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR3_SPI45SEL_2 (0x4UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR3_SPI1SEL_Pos (8U) +#define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR3_SPI1SEL RCC_CCIPR3_SPI1SEL_Msk +#define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000400 */ + +#define RCC_CCIPR3_SAI1SEL_Pos (16U) +#define RCC_CCIPR3_SAI1SEL_Msk (0x7UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR3_SAI1SEL RCC_CCIPR3_SAI1SEL_Msk +#define RCC_CCIPR3_SAI1SEL_0 (0x1UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR3_SAI1SEL_1 (0x2UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR3_SAI1SEL_2 (0x4UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00040000 */ + +#define RCC_CCIPR3_SAI2SEL_Pos (20U) +#define RCC_CCIPR3_SAI2SEL_Msk (0x7UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR3_SAI2SEL RCC_CCIPR3_SAI2SEL_Msk +#define RCC_CCIPR3_SAI2SEL_0 (0x1UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR3_SAI2SEL_1 (0x2UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR3_SAI2SEL_2 (0x4UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for RCC_CCIPR4 register ************/ +#define RCC_CCIPR4_LPUART1SEL_Pos (0U) +#define RCC_CCIPR4_LPUART1SEL_Msk (0x7UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR4_LPUART1SEL RCC_CCIPR4_LPUART1SEL_Msk +#define RCC_CCIPR4_LPUART1SEL_0 (0x1UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR4_LPUART1SEL_1 (0x2UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR4_LPUART1SEL_2 (0x4UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR4_SPI6SEL_Pos (4U) +#define RCC_CCIPR4_SPI6SEL_Msk (0x7UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR4_SPI6SEL RCC_CCIPR4_SPI6SEL_Msk +#define RCC_CCIPR4_SPI6SEL_0 (0x1UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR4_SPI6SEL_1 (0x2UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR4_SPI6SEL_2 (0x4UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR4_LPTIM23SEL_Pos (8U) +#define RCC_CCIPR4_LPTIM23SEL_Msk (0x7UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR4_LPTIM23SEL RCC_CCIPR4_LPTIM23SEL_Msk +#define RCC_CCIPR4_LPTIM23SEL_0 (0x1UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR4_LPTIM23SEL_1 (0x2UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR4_LPTIM23SEL_2 (0x4UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000400 */ + +#define RCC_CCIPR4_LPTIM45SEL_Pos (12U) +#define RCC_CCIPR4_LPTIM45SEL_Msk (0x7UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR4_LPTIM45SEL RCC_CCIPR4_LPTIM45SEL_Msk +#define RCC_CCIPR4_LPTIM45SEL_0 (0x1UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR4_LPTIM45SEL_1 (0x2UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR4_LPTIM45SEL_2 (0x4UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_CIER register ******************/ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk +#define RCC_CIER_HSIRDYIE_Pos (2U) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk +#define RCC_CIER_HSERDYIE_Pos (3U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk +#define RCC_CIER_CSIRDYIE_Pos (4U) +#define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk +#define RCC_CIER_HSI48RDYIE_Pos (5U) +#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk +#define RCC_CIER_PLL1RDYIE_Pos (6U) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk +#define RCC_CIER_PLL2RDYIE_Pos (7U) +#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk +#define RCC_CIER_PLL3RDYIE_Pos (8U) +#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk +#define RCC_CIER_LSECSSIE_Pos (9U) +#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */ +#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk + +/******************** Bit definition for RCC_CIFR register ******************/ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk +#define RCC_CIFR_HSIRDYF_Pos (2U) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk +#define RCC_CIFR_HSERDYF_Pos (3U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk +#define RCC_CIFR_CSIRDYF_Pos (4U) +#define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk +#define RCC_CIFR_HSI48RDYF_Pos (5U) +#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk +#define RCC_CIFR_PLL1RDYF_Pos (6U) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk +#define RCC_CIFR_PLL2RDYF_Pos (7U) +#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk +#define RCC_CIFR_PLL3RDYF_Pos (8U) +#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk +#define RCC_CIFR_LSECSSF_Pos (9U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk + +/******************** Bit definition for RCC_CICR register ******************/ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk +#define RCC_CICR_HSIRDYC_Pos (2U) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk +#define RCC_CICR_HSERDYC_Pos (3U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk +#define RCC_CICR_CSIRDYC_Pos (4U) +#define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk +#define RCC_CICR_HSI48RDYC_Pos (5U) +#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk +#define RCC_CICR_PLL1RDYC_Pos (6U) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk +#define RCC_CICR_PLL2RDYC_Pos (7U) +#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk +#define RCC_CICR_PLL3RDYC_Pos (8U) +#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk +#define RCC_CICR_LSECSSC_Pos (9U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk + +/******************** Bit definition for RCC_BDCR register ******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk +#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk +#define RCC_BDCR_LSEDRV_Pos (3U) +#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk +#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ + +#define RCC_BDCR_LSECSSON_Pos (5U) +#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk +#define RCC_BDCR_LSECSSD_Pos (6U) +#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk +#define RCC_BDCR_LSEEXT_Pos (7U) +#define RCC_BDCR_LSEEXT_Msk (0x1UL << RCC_BDCR_LSEEXT_Pos) /*!< 0x00000080 */ +#define RCC_BDCR_LSEEXT RCC_BDCR_LSEEXT_Msk +#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk +#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSRA_Pos (12U) +#define RCC_BDCR_LSECSSRA_Msk (0x1UL << RCC_BDCR_LSECSSRA_Pos) /*!< 0x00001000 */ +#define RCC_BDCR_LSECSSRA RCC_BDCR_LSECSSRA_Msk + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk +#define RCC_BDCR_VSWRST_Pos (16U) +#define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk + +/******************** Bit definition for RCC_AHB1RSTR register **************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (4U) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk +#define RCC_AHB1RSTR_ADC12RST_Pos (5U) +#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk +#define RCC_AHB1RSTR_ETH1RST_Pos (15U) +#define RCC_AHB1RSTR_ETH1RST_Msk (0x1UL << RCC_AHB1RSTR_ETH1RST_Pos) /*!< 0x00008000 */ +#define RCC_AHB1RSTR_ETH1RST RCC_AHB1RSTR_ETH1RST_Msk +#define RCC_AHB1RSTR_OTGHSRST_Pos (25U) +#define RCC_AHB1RSTR_OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHSRST_Pos) /*!< 0x02000000 */ +#define RCC_AHB1RSTR_OTGHSRST RCC_AHB1RSTR_OTGHSRST_Msk +#define RCC_AHB1RSTR_USBPHYCRST_Pos (26U) +#define RCC_AHB1RSTR_USBPHYCRST_Msk (0x1UL << RCC_AHB1RSTR_USBPHYCRST_Pos) /*!< 0x04000000 */ +#define RCC_AHB1RSTR_USBPHYCRST RCC_AHB1RSTR_USBPHYCRST_Msk +#define RCC_AHB1RSTR_OTGFSRST_Pos (27U) +#define RCC_AHB1RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_OTGFSRST_Pos) /*!< 0x08000000 */ +#define RCC_AHB1RSTR_OTGFSRST RCC_AHB1RSTR_OTGFSRST_Msk +#define RCC_AHB1RSTR_ADF1RST_Pos (31U) +#define RCC_AHB1RSTR_ADF1RST_Msk (0x1UL << RCC_AHB1RSTR_ADF1RST_Pos) /*!< 0x80000000 */ +#define RCC_AHB1RSTR_ADF1RST RCC_AHB1RSTR_ADF1RST_Msk + +/******************** Bit definition for RCC_AHB2RSTR register **************/ +#define RCC_AHB2RSTR_PSSIRST_Pos (1U) +#define RCC_AHB2RSTR_PSSIRST_Msk (0x1UL << RCC_AHB2RSTR_PSSIRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_PSSIRST RCC_AHB2RSTR_PSSIRST_Msk +#define RCC_AHB2RSTR_SDMMC2RST_Pos (9U) +#define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) /*!< 0x00000200 */ +#define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk +#define RCC_AHB2RSTR_CORDICRST_Pos (14U) +#define RCC_AHB2RSTR_CORDICRST_Msk (0x1UL << RCC_AHB2RSTR_CORDICRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB2RSTR_CORDICRST RCC_AHB2RSTR_CORDICRST_Msk + +/******************** Bit definition for RCC_AHB3RSTR register **************/ +#define RCC_AHB3RSTR_RNGRST_Pos (0U) +#define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk +#define RCC_AHB3RSTR_HASHRST_Pos (1U) +#define RCC_AHB3RSTR_HASHRST_Msk (0x1UL << RCC_AHB3RSTR_HASHRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTR_HASHRST RCC_AHB3RSTR_HASHRST_Msk +#define RCC_AHB3RSTR_CRYPRST_Pos (2U) +#define RCC_AHB3RSTR_CRYPRST_Msk (0x1UL << RCC_AHB3RSTR_CRYPRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB3RSTR_CRYPRST RCC_AHB3RSTR_CRYPRST_Msk +#define RCC_AHB3RSTR_SAESRST_Pos (4U) +#define RCC_AHB3RSTR_SAESRST_Msk (0x1UL << RCC_AHB3RSTR_SAESRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTR_SAESRST RCC_AHB3RSTR_SAESRST_Msk +#define RCC_AHB3RSTR_PKARST_Pos (6U) +#define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk + +/******************** Bit definition for RCC_AHB4RSTR register **************/ +#define RCC_AHB4RSTR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk +#define RCC_AHB4RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk +#define RCC_AHB4RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk +#define RCC_AHB4RSTR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk +#define RCC_AHB4RSTR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk +#define RCC_AHB4RSTR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk +#define RCC_AHB4RSTR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk +#define RCC_AHB4RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk +#define RCC_AHB4RSTR_GPIOMRST_Pos (12U) +#define RCC_AHB4RSTR_GPIOMRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOMRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB4RSTR_GPIOMRST RCC_AHB4RSTR_GPIOMRST_Msk +#define RCC_AHB4RSTR_GPIONRST_Pos (13U) +#define RCC_AHB4RSTR_GPIONRST_Msk (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB4RSTR_GPIONRST RCC_AHB4RSTR_GPIONRST_Msk +#define RCC_AHB4RSTR_GPIOORST_Pos (14U) +#define RCC_AHB4RSTR_GPIOORST_Msk (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos) /*!< 0x00004000 */ +#define RCC_AHB4RSTR_GPIOORST RCC_AHB4RSTR_GPIOORST_Msk +#define RCC_AHB4RSTR_GPIOPRST_Pos (15U) +#define RCC_AHB4RSTR_GPIOPRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos) /*!< 0x00008000 */ +#define RCC_AHB4RSTR_GPIOPRST RCC_AHB4RSTR_GPIOPRST_Msk +#define RCC_AHB4RSTR_CRCRST_Pos (19U) +#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk + +/******************** Bit definition for RCC_AHB5RSTR register **************/ +#define RCC_AHB5RSTR_HPDMA1RST_Pos (0U) +#define RCC_AHB5RSTR_HPDMA1RST_Msk (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_HPDMA1RST RCC_AHB5RSTR_HPDMA1RST_Msk +#define RCC_AHB5RSTR_DMA2DRST_Pos (1U) +#define RCC_AHB5RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB5RSTR_DMA2DRST RCC_AHB5RSTR_DMA2DRST_Msk +#define RCC_AHB5RSTR_JPEGRST_Pos (3U) +#define RCC_AHB5RSTR_JPEGRST_Msk (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTR_JPEGRST RCC_AHB5RSTR_JPEGRST_Msk +#define RCC_AHB5RSTR_FMCRST_Pos (4U) +#define RCC_AHB5RSTR_FMCRST_Msk (0x1UL << RCC_AHB5RSTR_FMCRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTR_FMCRST RCC_AHB5RSTR_FMCRST_Msk +#define RCC_AHB5RSTR_XSPI1RST_Pos (5U) +#define RCC_AHB5RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTR_XSPI1RST RCC_AHB5RSTR_XSPI1RST_Msk +#define RCC_AHB5RSTR_SDMMC1RST_Pos (8U) +#define RCC_AHB5RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTR_SDMMC1RST RCC_AHB5RSTR_SDMMC1RST_Msk +#define RCC_AHB5RSTR_XSPI2RST_Pos (12U) +#define RCC_AHB5RSTR_XSPI2RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos) /*!< 0x00001000 */ +#define RCC_AHB5RSTR_XSPI2RST RCC_AHB5RSTR_XSPI2RST_Msk +#define RCC_AHB5RSTR_XSPIMRST_Pos (14U) +#define RCC_AHB5RSTR_XSPIMRST_Msk (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB5RSTR_XSPIMRST RCC_AHB5RSTR_XSPIMRST_Msk +#define RCC_AHB5RSTR_GFXMMURST_Pos (19U) +#define RCC_AHB5RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTR_GFXMMURST RCC_AHB5RSTR_GFXMMURST_Msk + +/******************** Bit definition for RCC_APB1RSTR1 register *************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0U) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk +#define RCC_APB1RSTR1_TIM3RST_Pos (1U) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk +#define RCC_APB1RSTR1_TIM4RST_Pos (2U) +#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk +#define RCC_APB1RSTR1_TIM5RST_Pos (3U) +#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk +#define RCC_APB1RSTR1_TIM6RST_Pos (4U) +#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk +#define RCC_APB1RSTR1_TIM7RST_Pos (5U) +#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk +#define RCC_APB1RSTR1_TIM12RST_Pos (6U) +#define RCC_APB1RSTR1_TIM12RST_Msk (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTR1_TIM12RST RCC_APB1RSTR1_TIM12RST_Msk +#define RCC_APB1RSTR1_TIM13RST_Pos (7U) +#define RCC_APB1RSTR1_TIM13RST_Msk (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTR1_TIM13RST RCC_APB1RSTR1_TIM13RST_Msk +#define RCC_APB1RSTR1_TIM14RST_Pos (8U) +#define RCC_APB1RSTR1_TIM14RST_Msk (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR1_TIM14RST RCC_APB1RSTR1_TIM14RST_Msk +#define RCC_APB1RSTR1_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk +#define RCC_APB1RSTR1_SPI2RST_Pos (14U) +#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk +#define RCC_APB1RSTR1_SPI3RST_Pos (15U) +#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk +#define RCC_APB1RSTR1_SPDIFRXRST_Pos (16U) +#define RCC_APB1RSTR1_SPDIFRXRST_Msk (0x1UL << RCC_APB1RSTR1_SPDIFRXRST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTR1_SPDIFRXRST RCC_APB1RSTR1_SPDIFRXRST_Msk +#define RCC_APB1RSTR1_USART2RST_Pos (17U) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk +#define RCC_APB1RSTR1_USART3RST_Pos (18U) +#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk +#define RCC_APB1RSTR1_UART4RST_Pos (19U) +#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk +#define RCC_APB1RSTR1_UART5RST_Pos (20U) +#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk +#define RCC_APB1RSTR1_I2C1_I3C1RST_Pos (21U) +#define RCC_APB1RSTR1_I2C1_I3C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1_I3C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1_I3C1RST RCC_APB1RSTR1_I2C1_I3C1RST_Msk +#define RCC_APB1RSTR1_I2C2RST_Pos (22U) +#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk +#define RCC_APB1RSTR1_I2C3RST_Pos (23U) +#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk +#define RCC_APB1RSTR1_CECRST_Pos (27U) +#define RCC_APB1RSTR1_CECRST_Msk (0x1UL << RCC_APB1RSTR1_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR1_CECRST RCC_APB1RSTR1_CECRST_Msk +#define RCC_APB1RSTR1_UART7RST_Pos (30U) +#define RCC_APB1RSTR1_UART7RST_Msk (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTR1_UART7RST RCC_APB1RSTR1_UART7RST_Msk +#define RCC_APB1RSTR1_UART8RST_Pos (31U) +#define RCC_APB1RSTR1_UART8RST_Msk (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR1_UART8RST RCC_APB1RSTR1_UART8RST_Msk + +/******************** Bit definition for RCC_APB1RSTR2 register *************/ +#define RCC_APB1RSTR2_CRSRST_Pos (1U) +#define RCC_APB1RSTR2_CRSRST_Msk (0x1UL << RCC_APB1RSTR2_CRSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR2_CRSRST RCC_APB1RSTR2_CRSRST_Msk +#define RCC_APB1RSTR2_MDIOSRST_Pos (5U) +#define RCC_APB1RSTR2_MDIOSRST_Msk (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_MDIOSRST RCC_APB1RSTR2_MDIOSRST_Msk +#define RCC_APB1RSTR2_FDCANRST_Pos (8U) +#define RCC_APB1RSTR2_FDCANRST_Msk (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR2_FDCANRST RCC_APB1RSTR2_FDCANRST_Msk +#define RCC_APB1RSTR2_UCPD1RST_Pos (27U) +#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk + +/******************** Bit definition for RCC_APB2RSTR register **************/ +#define RCC_APB2RSTR_TIM1RST_Pos (0U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk +#define RCC_APB2RSTR_USART1RST_Pos (4U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk +#define RCC_APB2RSTR_SPI4RST_Pos (13U) +#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk +#define RCC_APB2RSTR_TIM9RST_Pos (19U) +#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk +#define RCC_APB2RSTR_SPI5RST_Pos (20U) +#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk +#define RCC_APB2RSTR_SAI1RST_Pos (22U) +#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk +#define RCC_APB2RSTR_SAI2RST_Pos (23U) +#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */ +#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk + +/******************** Bit definition for RCC_APB4RSTR register **************/ +#define RCC_APB4RSTR_SBSRST_Pos (1U) +#define RCC_APB4RSTR_SBSRST_Msk (0x1UL << RCC_APB4RSTR_SBSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB4RSTR_SBSRST RCC_APB4RSTR_SBSRST_Msk +#define RCC_APB4RSTR_LPUART1RST_Pos (3U) +#define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk +#define RCC_APB4RSTR_SPI6RST_Pos (5U) +#define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk +#define RCC_APB4RSTR_LPTIM2RST_Pos (9U) +#define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk +#define RCC_APB4RSTR_LPTIM3RST_Pos (10U) +#define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk +#define RCC_APB4RSTR_LPTIM4RST_Pos (11U) +#define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk +#define RCC_APB4RSTR_LPTIM5RST_Pos (12U) +#define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk +#define RCC_APB4RSTR_VREFRST_Pos (15U) +#define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk +#define RCC_APB4RSTR_DTSRST_Pos (26U) +#define RCC_APB4RSTR_DTSRST_Msk (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */ +#define RCC_APB4RSTR_DTSRST RCC_APB4RSTR_DTSRST_Msk + +/******************** Bit definition for RCC_APB5RSTR register **************/ +#define RCC_APB5RSTR_DCMIPPRST_Pos (2U) +#define RCC_APB5RSTR_DCMIPPRST_Msk (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTR_DCMIPPRST RCC_APB5RSTR_DCMIPPRST_Msk +#define RCC_APB5RSTR_GFXTIMRST_Pos (4U) +#define RCC_APB5RSTR_GFXTIMRST_Msk (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTR_GFXTIMRST RCC_APB5RSTR_GFXTIMRST_Msk + +/******************** Bit definition for RCC_CKGDISR register ***************/ +#define RCC_CKGDISR_AXICKG_Pos (0U) +#define RCC_CKGDISR_AXICKG_Msk (0x1UL << RCC_CKGDISR_AXICKG_Pos) /*!< 0x00000001 */ +#define RCC_CKGDISR_AXICKG RCC_CKGDISR_AXICKG_Msk +#define RCC_CKGDISR_AHBMCKG_Pos (1U) +#define RCC_CKGDISR_AHBMCKG_Msk (0x1UL << RCC_CKGDISR_AHBMCKG_Pos) /*!< 0x00000002 */ +#define RCC_CKGDISR_AHBMCKG RCC_CKGDISR_AHBMCKG_Msk +#define RCC_CKGDISR_SDMMC1CKG_Pos (2U) +#define RCC_CKGDISR_SDMMC1CKG_Msk (0x1UL << RCC_CKGDISR_SDMMC1CKG_Pos) /*!< 0x00000004 */ +#define RCC_CKGDISR_SDMMC1CKG RCC_CKGDISR_SDMMC1CKG_Msk +#define RCC_CKGDISR_HPDMA1CKG_Pos (3U) +#define RCC_CKGDISR_HPDMA1CKG_Msk (0x1UL << RCC_CKGDISR_HPDMA1CKG_Pos) /*!< 0x00000008 */ +#define RCC_CKGDISR_HPDMA1CKG RCC_CKGDISR_HPDMA1CKG_Msk +#define RCC_CKGDISR_CPUCKG_Pos (4U) +#define RCC_CKGDISR_CPUCKG_Msk (0x1UL << RCC_CKGDISR_CPUCKG_Pos) /*!< 0x00000010 */ +#define RCC_CKGDISR_CPUCKG RCC_CKGDISR_CPUCKG_Msk +#define RCC_CKGDISR_DCMIPPCKG_Pos (8U) +#define RCC_CKGDISR_DCMIPPCKG_Msk (0x1UL << RCC_CKGDISR_DCMIPPCKG_Pos) /*!< 0x00000100 */ +#define RCC_CKGDISR_DCMIPPCKG RCC_CKGDISR_DCMIPPCKG_Msk +#define RCC_CKGDISR_DMA2DCKG_Pos (9U) +#define RCC_CKGDISR_DMA2DCKG_Msk (0x1UL << RCC_CKGDISR_DMA2DCKG_Pos) /*!< 0x00000200 */ +#define RCC_CKGDISR_DMA2DCKG RCC_CKGDISR_DMA2DCKG_Msk +#define RCC_CKGDISR_GFXMMUSCKG_Pos (10U) +#define RCC_CKGDISR_GFXMMUSCKG_Msk (0x1UL << RCC_CKGDISR_GFXMMUSCKG_Pos) /*!< 0x00000400 */ +#define RCC_CKGDISR_GFXMMUSCKG RCC_CKGDISR_GFXMMUSCKG_Msk +#define RCC_CKGDISR_GFXMMUMCKG_Pos (12U) +#define RCC_CKGDISR_GFXMMUMCKG_Msk (0x1UL << RCC_CKGDISR_GFXMMUMCKG_Pos) /*!< 0x00001000 */ +#define RCC_CKGDISR_GFXMMUMCKG RCC_CKGDISR_GFXMMUMCKG_Msk +#define RCC_CKGDISR_AHBSCKG_Pos (13U) +#define RCC_CKGDISR_AHBSCKG_Msk (0x1UL << RCC_CKGDISR_AHBSCKG_Pos) /*!< 0x00002000 */ +#define RCC_CKGDISR_AHBSCKG RCC_CKGDISR_AHBSCKG_Msk +#define RCC_CKGDISR_FMCCKG_Pos (14U) +#define RCC_CKGDISR_FMCCKG_Msk (0x1UL << RCC_CKGDISR_FMCCKG_Pos) /*!< 0x00004000 */ +#define RCC_CKGDISR_FMCCKG RCC_CKGDISR_FMCCKG_Msk +#define RCC_CKGDISR_XSPI1CKG_Pos (15U) +#define RCC_CKGDISR_XSPI1CKG_Msk (0x1UL << RCC_CKGDISR_XSPI1CKG_Pos) /*!< 0x00008000 */ +#define RCC_CKGDISR_XSPI1CKG RCC_CKGDISR_XSPI1CKG_Msk +#define RCC_CKGDISR_XSPI2CKG_Pos (16U) +#define RCC_CKGDISR_XSPI2CKG_Msk (0x1UL << RCC_CKGDISR_XSPI2CKG_Pos) /*!< 0x00010000 */ +#define RCC_CKGDISR_XSPI2CKG RCC_CKGDISR_XSPI2CKG_Msk +#define RCC_CKGDISR_AXISRAM4CKG_Pos (17U) +#define RCC_CKGDISR_AXISRAM4CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM4CKG_Pos) /*!< 0x00020000 */ +#define RCC_CKGDISR_AXISRAM4CKG RCC_CKGDISR_AXISRAM4CKG_Msk +#define RCC_CKGDISR_AXISRAM3CKG_Pos (18U) +#define RCC_CKGDISR_AXISRAM3CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM3CKG_Pos) /*!< 0x00040000 */ +#define RCC_CKGDISR_AXISRAM3CKG RCC_CKGDISR_AXISRAM3CKG_Msk +#define RCC_CKGDISR_AXISRAM2CKG_Pos (19U) +#define RCC_CKGDISR_AXISRAM2CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM2CKG_Pos) /*!< 0x00080000 */ +#define RCC_CKGDISR_AXISRAM2CKG RCC_CKGDISR_AXISRAM2CKG_Msk +#define RCC_CKGDISR_AXISRAM1CKG_Pos (20U) +#define RCC_CKGDISR_AXISRAM1CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM1CKG_Pos) /*!< 0x00100000 */ +#define RCC_CKGDISR_AXISRAM1CKG RCC_CKGDISR_AXISRAM1CKG_Msk +#define RCC_CKGDISR_FLASHCKG_Pos (21U) +#define RCC_CKGDISR_FLASHCKG_Msk (0x1UL << RCC_CKGDISR_FLASHCKG_Pos) /*!< 0x00200000 */ +#define RCC_CKGDISR_FLASHCKG RCC_CKGDISR_FLASHCKG_Msk +#define RCC_CKGDISR_EXTICKG_Pos (30U) +#define RCC_CKGDISR_EXTICKG_Msk (0x1UL << RCC_CKGDISR_EXTICKG_Pos) /*!< 0x40000000 */ +#define RCC_CKGDISR_EXTICKG RCC_CKGDISR_EXTICKG_Msk +#define RCC_CKGDISR_JTAGCKG_Pos (31U) +#define RCC_CKGDISR_JTAGCKG_Msk (0x1UL << RCC_CKGDISR_JTAGCKG_Pos) /*!< 0x80000000 */ +#define RCC_CKGDISR_JTAGCKG RCC_CKGDISR_JTAGCKG_Msk + +/******************** Bit definition for RCC_PLL1DIVR2 register *************/ +#define RCC_PLL1DIVR2_DIVS_Pos (0U) +#define RCC_PLL1DIVR2_DIVS_Msk (0x7UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL1DIVR2_DIVS RCC_PLL1DIVR2_DIVS_Msk /*!< DIVS1[2:0] bits: PLL1 DIVS division factor */ +#define RCC_PLL1DIVR2_DIVS_0 (0x1UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR2_DIVS_1 (0x2UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR2_DIVS_2 (0x4UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for RCC_PLL2DIVR2 register *************/ +#define RCC_PLL2DIVR2_DIVS_Pos (0U) +#define RCC_PLL2DIVR2_DIVS_Msk (0x7UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL2DIVR2_DIVS RCC_PLL2DIVR2_DIVS_Msk /*!< DIVS2[2:0] bits: PLL2 DIVS division factor */ +#define RCC_PLL2DIVR2_DIVS_0 (0x1UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL2DIVR2_DIVS_1 (0x2UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL2DIVR2_DIVS_2 (0x4UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +#define RCC_PLL2DIVR2_DIVT_Pos (8U) +#define RCC_PLL2DIVR2_DIVT_Msk (0x7UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000700 */ +#define RCC_PLL2DIVR2_DIVT RCC_PLL2DIVR2_DIVT_Msk /*!< DIVT2[2:0] bits: PLL2 DIVT division factor */ +#define RCC_PLL2DIVR2_DIVT_0 (0x1UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000100 */ +#define RCC_PLL2DIVR2_DIVT_1 (0x2UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000200 */ +#define RCC_PLL2DIVR2_DIVT_2 (0x4UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for RCC_PLL3DIVR2 register *************/ +#define RCC_PLL3DIVR2_DIVS_Pos (0U) +#define RCC_PLL3DIVR2_DIVS_Msk (0x7UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL3DIVR2_DIVS RCC_PLL3DIVR2_DIVS_Msk /*!< DIVS3[2:0] bits: PLL3 DIVS division factor */ +#define RCC_PLL3DIVR2_DIVS_0 (0x1UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL3DIVR2_DIVS_1 (0x2UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL3DIVR2_DIVS_2 (0x4UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for RCC_PLL1SSCGR register *************/ +#define RCC_PLL1SSCGR_MODPER_Pos (0U) +#define RCC_PLL1SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1SSCGR_MODPER RCC_PLL1SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL1SSCGR_MODPER_0 (0x0001UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1SSCGR_MODPER_1 (0x0002UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1SSCGR_MODPER_2 (0x0004UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1SSCGR_MODPER_3 (0x0008UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1SSCGR_MODPER_4 (0x0010UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1SSCGR_MODPER_5 (0x0020UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1SSCGR_MODPER_6 (0x0040UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1SSCGR_MODPER_7 (0x0080UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1SSCGR_MODPER_8 (0x0100UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1SSCGR_MODPER_9 (0x0200UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1SSCGR_MODPER_10 (0x0400UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1SSCGR_MODPER_11 (0x0800UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1SSCGR_MODPER_12 (0x1000UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL1SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL1SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1SSCGR_TPDFNDIS RCC_PLL1SSCGR_TPDFNDIS_Msk +#define RCC_PLL1SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL1SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL1SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1SSCGR_RPDFNDIS RCC_PLL1SSCGR_RPDFNDIS_Msk +#define RCC_PLL1SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL1SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL1SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL1SSCGR_SPREADSEL RCC_PLL1SSCGR_SPREADSEL_Msk +#define RCC_PLL1SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL1SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1SSCGR_INCSTEP RCC_PLL1SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL1SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL2SSCGR register *************/ +#define RCC_PLL2SSCGR_MODPER_Pos (0U) +#define RCC_PLL2SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2SSCGR_MODPER RCC_PLL2SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL2SSCGR_MODPER_0 (0x0001UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2SSCGR_MODPER_1 (0x0002UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2SSCGR_MODPER_2 (0x0004UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2SSCGR_MODPER_3 (0x0008UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2SSCGR_MODPER_4 (0x0010UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2SSCGR_MODPER_5 (0x0020UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2SSCGR_MODPER_6 (0x0040UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2SSCGR_MODPER_7 (0x0080UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2SSCGR_MODPER_8 (0x0100UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2SSCGR_MODPER_9 (0x0200UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2SSCGR_MODPER_10 (0x0400UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2SSCGR_MODPER_11 (0x0800UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2SSCGR_MODPER_12 (0x1000UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL2SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL2SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2SSCGR_TPDFNDIS RCC_PLL2SSCGR_TPDFNDIS_Msk +#define RCC_PLL2SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL2SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL2SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2SSCGR_RPDFNDIS RCC_PLL2SSCGR_RPDFNDIS_Msk +#define RCC_PLL2SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL2SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL2SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL2SSCGR_SPREADSEL RCC_PLL2SSCGR_SPREADSEL_Msk +#define RCC_PLL2SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL2SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2SSCGR_INCSTEP RCC_PLL2SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL2SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL3SSCGR register *************/ +#define RCC_PLL3SSCGR_MODPER_Pos (0U) +#define RCC_PLL3SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL3SSCGR_MODPER RCC_PLL3SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL3SSCGR_MODPER_0 (0x0001UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL3SSCGR_MODPER_1 (0x0002UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL3SSCGR_MODPER_2 (0x0004UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL3SSCGR_MODPER_3 (0x0008UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL3SSCGR_MODPER_4 (0x0010UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL3SSCGR_MODPER_5 (0x0020UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL3SSCGR_MODPER_6 (0x0040UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL3SSCGR_MODPER_7 (0x0080UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL3SSCGR_MODPER_8 (0x0100UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL3SSCGR_MODPER_9 (0x0200UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL3SSCGR_MODPER_10 (0x0400UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL3SSCGR_MODPER_11 (0x0800UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL3SSCGR_MODPER_12 (0x1000UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL3SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL3SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL3SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL3SSCGR_TPDFNDIS RCC_PLL3SSCGR_TPDFNDIS_Msk +#define RCC_PLL3SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL3SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL3SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL3SSCGR_RPDFNDIS RCC_PLL3SSCGR_RPDFNDIS_Msk +#define RCC_PLL3SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL3SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL3SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL3SSCGR_SPREADSEL RCC_PLL3SSCGR_SPREADSEL_Msk +#define RCC_PLL3SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL3SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3SSCGR_INCSTEP RCC_PLL3SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL3SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL3SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL3SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL3SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL3SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL3SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL3SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL3SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL3SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL3SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL3SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL3SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL3SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL3SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL3SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CKPROTR register ***************/ +#define RCC_CKPROTR_XSPICKP_Pos (0U) +#define RCC_CKPROTR_XSPICKP_Msk (0x1UL << RCC_CKPROTR_XSPICKP_Pos) /*!< 0x00000001 */ +#define RCC_CKPROTR_XSPICKP RCC_CKPROTR_XSPICKP_Msk +#define RCC_CKPROTR_FMCCKP_Pos (1U) +#define RCC_CKPROTR_FMCCKP_Msk (0x1UL << RCC_CKPROTR_FMCCKP_Pos) /*!< 0x00000002 */ +#define RCC_CKPROTR_FMCCKP RCC_CKPROTR_FMCCKP_Msk +#define RCC_CKPROTR_XSPI1SWP_Pos (4U) +#define RCC_CKPROTR_XSPI1SWP_Msk (0x7UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000070 */ +#define RCC_CKPROTR_XSPI1SWP RCC_CKPROTR_XSPI1SWP_Msk +#define RCC_CKPROTR_XSPI1SWP_0 (0x1UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000010 */ +#define RCC_CKPROTR_XSPI1SWP_1 (0x2UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000020 */ +#define RCC_CKPROTR_XSPI1SWP_2 (0x4UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000040 */ +#define RCC_CKPROTR_XSPI2SWP_Pos (8U) +#define RCC_CKPROTR_XSPI2SWP_Msk (0x7UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000700 */ +#define RCC_CKPROTR_XSPI2SWP RCC_CKPROTR_XSPI2SWP_Msk +#define RCC_CKPROTR_XSPI2SWP_0 (0x1UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000100 */ +#define RCC_CKPROTR_XSPI2SWP_1 (0x2UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000200 */ +#define RCC_CKPROTR_XSPI2SWP_2 (0x4UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000400 */ +#define RCC_CKPROTR_FMCSWP_Pos (12U) +#define RCC_CKPROTR_FMCSWP_Msk (0x7UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00007000 */ +#define RCC_CKPROTR_FMCSWP RCC_CKPROTR_FMCSWP_Msk +#define RCC_CKPROTR_FMCSWP_0 (0x1UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00001000 */ +#define RCC_CKPROTR_FMCSWP_1 (0x2UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00002000 */ +#define RCC_CKPROTR_FMCSWP_2 (0x4UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_RSR register *******************/ +#define RCC_RSR_RMVF_Pos (16U) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk +#define RCC_RSR_OBLRSTF_Pos (17U) +#define RCC_RSR_OBLRSTF_Msk (0x1UL << RCC_RSR_OBLRSTF_Pos) /*!< 0x00020000 */ +#define RCC_RSR_OBLRSTF RCC_RSR_OBLRSTF_Msk +#define RCC_RSR_BORRSTF_Pos (21U) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk +#define RCC_RSR_PINRSTF_Pos (22U) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk +#define RCC_RSR_PORRSTF_Pos (23U) +#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk +#define RCC_RSR_SFTRSTF_Pos (24U) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk +#define RCC_RSR_IWDGRSTF_Pos (26U) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk +#define RCC_RSR_WWDGRSTF_Pos (28U) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk +#define RCC_RSR_LPWRRSTF_Pos (30U) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk + +/******************** Bit definition for RCC_AHB1ENR register ***************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (4U) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk +#define RCC_AHB1ENR_ADC12EN_Pos (5U) +#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk +#define RCC_AHB1ENR_ETH1MACEN_Pos (15U) +#define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk +#define RCC_AHB1ENR_ETH1TXEN_Pos (16U) +#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk +#define RCC_AHB1ENR_ETH1RXEN_Pos (17U) +#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk +#define RCC_AHB1ENR_OTGHSEN_Pos (25U) +#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk +#define RCC_AHB1ENR_USBPHYCEN_Pos (26U) +#define RCC_AHB1ENR_USBPHYCEN_Msk (0x1UL << RCC_AHB1ENR_USBPHYCEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB1ENR_USBPHYCEN RCC_AHB1ENR_USBPHYCEN_Msk +#define RCC_AHB1ENR_OTGFSEN_Pos (27U) +#define RCC_AHB1ENR_OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_OTGFSEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB1ENR_OTGFSEN RCC_AHB1ENR_OTGFSEN_Msk +#define RCC_AHB1ENR_ADF1EN_Pos (31U) +#define RCC_AHB1ENR_ADF1EN_Msk (0x1UL << RCC_AHB1ENR_ADF1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_ADF1EN RCC_AHB1ENR_ADF1EN_Msk + +/******************** Bit definition for RCC_AHB2ENR register ***************/ +#define RCC_AHB2ENR_PSSIEN_Pos (1U) +#define RCC_AHB2ENR_PSSIEN_Msk (0x1UL << RCC_AHB2ENR_PSSIEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_PSSIEN RCC_AHB2ENR_PSSIEN_Msk +#define RCC_AHB2ENR_SDMMC2EN_Pos (9U) +#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */ +#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk +#define RCC_AHB2ENR_CORDICEN_Pos (14U) +#define RCC_AHB2ENR_CORDICEN_Msk (0x1UL << RCC_AHB2ENR_CORDICEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB2ENR_CORDICEN RCC_AHB2ENR_CORDICEN_Msk +#define RCC_AHB2ENR_SRAM1EN_Pos (29U) +#define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos) /*!< 0x20000000 */ +#define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk +#define RCC_AHB2ENR_SRAM2EN_Pos (30U) +#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk + +/******************** Bit definition for RCC_AHB3ENR register ***************/ +#define RCC_AHB3ENR_RNGEN_Pos (0U) +#define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk +#define RCC_AHB3ENR_HASHEN_Pos (1U) +#define RCC_AHB3ENR_HASHEN_Msk (0x1UL << RCC_AHB3ENR_HASHEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENR_HASHEN RCC_AHB3ENR_HASHEN_Msk +#define RCC_AHB3ENR_CRYPEN_Pos (2U) +#define RCC_AHB3ENR_CRYPEN_Msk (0x1UL << RCC_AHB3ENR_CRYPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB3ENR_CRYPEN RCC_AHB3ENR_CRYPEN_Msk +#define RCC_AHB3ENR_SAESEN_Pos (4U) +#define RCC_AHB3ENR_SAESEN_Msk (0x1UL << RCC_AHB3ENR_SAESEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB3ENR_SAESEN RCC_AHB3ENR_SAESEN_Msk +#define RCC_AHB3ENR_PKAEN_Pos (6U) +#define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk + +/******************** Bit definition for RCC_AHB4ENR register ***************/ +#define RCC_AHB4ENR_GPIOAEN_Pos (0U) +#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk +#define RCC_AHB4ENR_GPIOBEN_Pos (1U) +#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk +#define RCC_AHB4ENR_GPIOCEN_Pos (2U) +#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk +#define RCC_AHB4ENR_GPIODEN_Pos (3U) +#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk +#define RCC_AHB4ENR_GPIOEEN_Pos (4U) +#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk +#define RCC_AHB4ENR_GPIOFEN_Pos (5U) +#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk +#define RCC_AHB4ENR_GPIOGEN_Pos (6U) +#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk +#define RCC_AHB4ENR_GPIOHEN_Pos (7U) +#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk +#define RCC_AHB4ENR_GPIOMEN_Pos (12U) +#define RCC_AHB4ENR_GPIOMEN_Msk (0x1UL << RCC_AHB4ENR_GPIOMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB4ENR_GPIOMEN RCC_AHB4ENR_GPIOMEN_Msk +#define RCC_AHB4ENR_GPIONEN_Pos (13U) +#define RCC_AHB4ENR_GPIONEN_Msk (0x1UL << RCC_AHB4ENR_GPIONEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENR_GPIONEN RCC_AHB4ENR_GPIONEN_Msk +#define RCC_AHB4ENR_GPIOOEN_Pos (14U) +#define RCC_AHB4ENR_GPIOOEN_Msk (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENR_GPIOOEN RCC_AHB4ENR_GPIOOEN_Msk +#define RCC_AHB4ENR_GPIOPEN_Pos (15U) +#define RCC_AHB4ENR_GPIOPEN_Msk (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENR_GPIOPEN RCC_AHB4ENR_GPIOPEN_Msk +#define RCC_AHB4ENR_CRCEN_Pos (19U) +#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk +#define RCC_AHB4ENR_BKPRAMEN_Pos (28U) +#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk + +/******************** Bit definition for RCC_AHB5ENR register ***************/ +#define RCC_AHB5ENR_HPDMA1EN_Pos (0U) +#define RCC_AHB5ENR_HPDMA1EN_Msk (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_HPDMA1EN RCC_AHB5ENR_HPDMA1EN_Msk +#define RCC_AHB5ENR_DMA2DEN_Pos (1U) +#define RCC_AHB5ENR_DMA2DEN_Msk (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENR_DMA2DEN RCC_AHB5ENR_DMA2DEN_Msk +#define RCC_AHB5ENR_JPEGEN_Pos (3U) +#define RCC_AHB5ENR_JPEGEN_Msk (0x1UL << RCC_AHB5ENR_JPEGEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENR_JPEGEN RCC_AHB5ENR_JPEGEN_Msk +#define RCC_AHB5ENR_FMCEN_Pos (4U) +#define RCC_AHB5ENR_FMCEN_Msk (0x1UL << RCC_AHB5ENR_FMCEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENR_FMCEN RCC_AHB5ENR_FMCEN_Msk +#define RCC_AHB5ENR_XSPI1EN_Pos (5U) +#define RCC_AHB5ENR_XSPI1EN_Msk (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENR_XSPI1EN RCC_AHB5ENR_XSPI1EN_Msk +#define RCC_AHB5ENR_SDMMC1EN_Pos (8U) +#define RCC_AHB5ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENR_SDMMC1EN RCC_AHB5ENR_SDMMC1EN_Msk +#define RCC_AHB5ENR_XSPI2EN_Pos (12U) +#define RCC_AHB5ENR_XSPI2EN_Msk (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENR_XSPI2EN RCC_AHB5ENR_XSPI2EN_Msk +#define RCC_AHB5ENR_XSPIMEN_Pos (14U) +#define RCC_AHB5ENR_XSPIMEN_Msk (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5ENR_XSPIMEN RCC_AHB5ENR_XSPIMEN_Msk +#define RCC_AHB5ENR_GFXMMUEN_Pos (19U) +#define RCC_AHB5ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENR_GFXMMUEN RCC_AHB5ENR_GFXMMUEN_Msk + +/******************** Bit definition for RCC_APB1ENR1 register **************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0U) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk +#define RCC_APB1ENR1_TIM3EN_Pos (1U) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk +#define RCC_APB1ENR1_TIM4EN_Pos (2U) +#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk +#define RCC_APB1ENR1_TIM5EN_Pos (3U) +#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk +#define RCC_APB1ENR1_TIM6EN_Pos (4U) +#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk +#define RCC_APB1ENR1_TIM7EN_Pos (5U) +#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk +#define RCC_APB1ENR1_TIM12EN_Pos (6U) +#define RCC_APB1ENR1_TIM12EN_Msk (0x1UL << RCC_APB1ENR1_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENR1_TIM12EN RCC_APB1ENR1_TIM12EN_Msk +#define RCC_APB1ENR1_TIM13EN_Pos (7U) +#define RCC_APB1ENR1_TIM13EN_Msk (0x1UL << RCC_APB1ENR1_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENR1_TIM13EN RCC_APB1ENR1_TIM13EN_Msk +#define RCC_APB1ENR1_TIM14EN_Pos (8U) +#define RCC_APB1ENR1_TIM14EN_Msk (0x1UL << RCC_APB1ENR1_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR1_TIM14EN RCC_APB1ENR1_TIM14EN_Msk +#define RCC_APB1ENR1_LPTIM1EN_Pos (9U) +#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk +#define RCC_APB1ENR1_WWDGEN_Pos (11U) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk +#define RCC_APB1ENR1_SPI2EN_Pos (14U) +#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk +#define RCC_APB1ENR1_SPI3EN_Pos (15U) +#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk +#define RCC_APB1ENR1_SPDIFRXEN_Pos (16U) +#define RCC_APB1ENR1_SPDIFRXEN_Msk (0x1UL << RCC_APB1ENR1_SPDIFRXEN_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENR1_SPDIFRXEN RCC_APB1ENR1_SPDIFRXEN_Msk +#define RCC_APB1ENR1_USART2EN_Pos (17U) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk +#define RCC_APB1ENR1_USART3EN_Pos (18U) +#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk +#define RCC_APB1ENR1_UART4EN_Pos (19U) +#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk +#define RCC_APB1ENR1_UART5EN_Pos (20U) +#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk +#define RCC_APB1ENR1_I2C1_I3C1EN_Pos (21U) +#define RCC_APB1ENR1_I2C1_I3C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1_I3C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1_I3C1EN RCC_APB1ENR1_I2C1_I3C1EN_Msk +#define RCC_APB1ENR1_I2C2EN_Pos (22U) +#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk +#define RCC_APB1ENR1_I2C3EN_Pos (23U) +#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk +#define RCC_APB1ENR1_CECEN_Pos (27U) +#define RCC_APB1ENR1_CECEN_Msk (0x1UL << RCC_APB1ENR1_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR1_CECEN RCC_APB1ENR1_CECEN_Msk +#define RCC_APB1ENR1_UART7EN_Pos (30U) +#define RCC_APB1ENR1_UART7EN_Msk (0x1UL << RCC_APB1ENR1_UART7EN_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENR1_UART7EN RCC_APB1ENR1_UART7EN_Msk +#define RCC_APB1ENR1_UART8EN_Pos (31U) +#define RCC_APB1ENR1_UART8EN_Msk (0x1UL << RCC_APB1ENR1_UART8EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR1_UART8EN RCC_APB1ENR1_UART8EN_Msk + +/******************** Bit definition for RCC_APB1ENR2 register **************/ +#define RCC_APB1ENR2_CRSEN_Pos (1U) +#define RCC_APB1ENR2_CRSEN_Msk (0x1UL << RCC_APB1ENR2_CRSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR2_CRSEN RCC_APB1ENR2_CRSEN_Msk +#define RCC_APB1ENR2_MDIOSEN_Pos (5U) +#define RCC_APB1ENR2_MDIOSEN_Msk (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_MDIOSEN RCC_APB1ENR2_MDIOSEN_Msk +#define RCC_APB1ENR2_FDCANEN_Pos (8U) +#define RCC_APB1ENR2_FDCANEN_Msk (0x1UL << RCC_APB1ENR2_FDCANEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR2_FDCANEN RCC_APB1ENR2_FDCANEN_Msk +#define RCC_APB1ENR2_UCPD1EN_Pos (27U) +#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk + +/******************** Bit definition for RCC_APB2ENR register ***************/ +#define RCC_APB2ENR_TIM1EN_Pos (0U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk +#define RCC_APB2ENR_USART1EN_Pos (4U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk +#define RCC_APB2ENR_SPI4EN_Pos (13U) +#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk +#define RCC_APB2ENR_TIM9EN_Pos (19U) +#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk +#define RCC_APB2ENR_SPI5EN_Pos (20U) +#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk +#define RCC_APB2ENR_SAI1EN_Pos (22U) +#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk +#define RCC_APB2ENR_SAI2EN_Pos (23U) +#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */ +#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk + +/******************** Bit definition for RCC_APB4ENR register ***************/ +#define RCC_APB4ENR_SBSEN_Pos (1U) +#define RCC_APB4ENR_SBSEN_Msk (0x1UL << RCC_APB4ENR_SBSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENR_SBSEN RCC_APB4ENR_SBSEN_Msk +#define RCC_APB4ENR_LPUART1EN_Pos (3U) +#define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk +#define RCC_APB4ENR_SPI6EN_Pos (5U) +#define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk +#define RCC_APB4ENR_LPTIM2EN_Pos (9U) +#define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */ +#define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk +#define RCC_APB4ENR_LPTIM3EN_Pos (10U) +#define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */ +#define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk +#define RCC_APB4ENR_LPTIM4EN_Pos (11U) +#define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */ +#define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk +#define RCC_APB4ENR_LPTIM5EN_Pos (12U) +#define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */ +#define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk +#define RCC_APB4ENR_VREFEN_Pos (15U) +#define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk +#define RCC_APB4ENR_RTCAPBEN_Pos (16U) +#define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk +#define RCC_APB4ENR_DTSEN_Pos (26U) +#define RCC_APB4ENR_DTSEN_Msk (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */ +#define RCC_APB4ENR_DTSEN RCC_APB4ENR_DTSEN_Msk + +/******************** Bit definition for RCC_APB5ENR register ***************/ +#define RCC_APB5ENR_DCMIPPEN_Pos (2U) +#define RCC_APB5ENR_DCMIPPEN_Msk (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENR_DCMIPPEN RCC_APB5ENR_DCMIPPEN_Msk +#define RCC_APB5ENR_GFXTIMEN_Pos (4U) +#define RCC_APB5ENR_GFXTIMEN_Msk (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENR_GFXTIMEN RCC_APB5ENR_GFXTIMEN_Msk + +/******************** Bit definition for RCC_AHB1LPENR register *************/ +#define RCC_AHB1LPENR_GPDMA1LPEN_Pos (4U) +#define RCC_AHB1LPENR_GPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENR_GPDMA1LPEN RCC_AHB1LPENR_GPDMA1LPEN_Msk +#define RCC_AHB1LPENR_ADC12LPEN_Pos (5U) +#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk +#define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U) +#define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk +#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U) +#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk +#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U) +#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk +#define RCC_AHB1LPENR_UCPDCTRL_Pos (24U) +#define RCC_AHB1LPENR_UCPDCTRL_Msk (0x1UL << RCC_AHB1LPENR_UCPDCTRL_Pos) /*!< 0x01000000 */ +#define RCC_AHB1LPENR_UCPDCTRL RCC_AHB1LPENR_UCPDCTRL_Msk +#define RCC_AHB1LPENR_OTGHSLPEN_Pos (25U) +#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk +#define RCC_AHB1LPENR_USBPHYCLPEN_Pos (26U) +#define RCC_AHB1LPENR_USBPHYCLPEN_Msk (0x1UL << RCC_AHB1LPENR_USBPHYCLPEN_Pos)/*!< 0x04000000 */ +#define RCC_AHB1LPENR_USBPHYCLPEN RCC_AHB1LPENR_USBPHYCLPEN_Msk +#define RCC_AHB1LPENR_OTGFSLPEN_Pos (27U) +#define RCC_AHB1LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGFSLPEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB1LPENR_OTGFSLPEN RCC_AHB1LPENR_OTGFSLPEN_Msk +#define RCC_AHB1LPENR_ADF1LPEN_Pos (31U) +#define RCC_AHB1LPENR_ADF1LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADF1LPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1LPENR_ADF1LPEN RCC_AHB1LPENR_ADF1LPEN_Msk + +/******************** Bit definition for RCC_AHB2LPENR register *************/ +#define RCC_AHB2LPENR_PSSILPEN_Pos (1U) +#define RCC_AHB2LPENR_PSSILPEN_Msk (0x1UL << RCC_AHB2LPENR_PSSILPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2LPENR_PSSILPEN RCC_AHB2LPENR_PSSILPEN_Msk +#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U) +#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk +#define RCC_AHB2LPENR_CORDICLPEN_Pos (14U) +#define RCC_AHB2LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB2LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB2LPENR_CORDICLPEN RCC_AHB2LPENR_CORDICLPEN_Msk +#define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U) +#define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk +#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U) +#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk + +/******************** Bit definition for RCC_AHB3LPENR register *************/ +#define RCC_AHB3LPENR_RNGLPEN_Pos (0U) +#define RCC_AHB3LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3LPENR_RNGLPEN RCC_AHB3LPENR_RNGLPEN_Msk +#define RCC_AHB3LPENR_HASHLPEN_Pos (1U) +#define RCC_AHB3LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENR_HASHLPEN RCC_AHB3LPENR_HASHLPEN_Msk +#define RCC_AHB3LPENR_CRYPLPEN_Pos (2U) +#define RCC_AHB3LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB3LPENR_CRYPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB3LPENR_CRYPLPEN RCC_AHB3LPENR_CRYPLPEN_Msk +#define RCC_AHB3LPENR_SAESLPEN_Pos (4U) +#define RCC_AHB3LPENR_SAESLPEN_Msk (0x1UL << RCC_AHB3LPENR_SAESLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB3LPENR_SAESLPEN RCC_AHB3LPENR_SAESLPEN_Msk +#define RCC_AHB3LPENR_PKALPEN_Pos (6U) +#define RCC_AHB3LPENR_PKALPEN_Msk (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB3LPENR_PKALPEN RCC_AHB3LPENR_PKALPEN_Msk + +/******************** Bit definition for RCC_AHB4LPENR register *************/ +#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk +#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk +#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk +#define RCC_AHB4LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk +#define RCC_AHB4LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk +#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U) +#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk +#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U) +#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk +#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk +#define RCC_AHB4LPENR_GPIOMLPEN_Pos (12U) +#define RCC_AHB4LPENR_GPIOMLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOMLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB4LPENR_GPIOMLPEN RCC_AHB4LPENR_GPIOMLPEN_Msk +#define RCC_AHB4LPENR_GPIONLPEN_Pos (13U) +#define RCC_AHB4LPENR_GPIONLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENR_GPIONLPEN RCC_AHB4LPENR_GPIONLPEN_Msk +#define RCC_AHB4LPENR_GPIOOLPEN_Pos (14U) +#define RCC_AHB4LPENR_GPIOOLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENR_GPIOOLPEN RCC_AHB4LPENR_GPIOOLPEN_Msk +#define RCC_AHB4LPENR_GPIOPLPEN_Pos (15U) +#define RCC_AHB4LPENR_GPIOPLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENR_GPIOPLPEN RCC_AHB4LPENR_GPIOPLPEN_Msk +#define RCC_AHB4LPENR_CRCLPEN_Pos (19U) +#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk +#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U) +#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk + +/******************** Bit definition for RCC_AHB5LPENR register *************/ +#define RCC_AHB5LPENR_HPDMA1LPEN_Pos (0U) +#define RCC_AHB5LPENR_HPDMA1LPEN_Msk (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENR_HPDMA1LPEN RCC_AHB5LPENR_HPDMA1LPEN_Msk +#define RCC_AHB5LPENR_DMA2DLPEN_Pos (1U) +#define RCC_AHB5LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENR_DMA2DLPEN RCC_AHB5LPENR_DMA2DLPEN_Msk +#define RCC_AHB5LPENR_FLASHLPEN_Pos (2U) +#define RCC_AHB5LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB5LPENR_FLASHLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB5LPENR_FLASHLPEN RCC_AHB5LPENR_FLASHLPEN_Msk +#define RCC_AHB5LPENR_JPEGLPEN_Pos (3U) +#define RCC_AHB5LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENR_JPEGLPEN RCC_AHB5LPENR_JPEGLPEN_Msk +#define RCC_AHB5LPENR_FMCLPEN_Pos (4U) +#define RCC_AHB5LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5LPENR_FMCLPEN RCC_AHB5LPENR_FMCLPEN_Msk +#define RCC_AHB5LPENR_XSPI1LPEN_Pos (5U) +#define RCC_AHB5LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENR_XSPI1LPEN RCC_AHB5LPENR_XSPI1LPEN_Msk +#define RCC_AHB5LPENR_SDMMC1LPEN_Pos (8U) +#define RCC_AHB5LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENR_SDMMC1LPEN RCC_AHB5LPENR_SDMMC1LPEN_Msk +#define RCC_AHB5LPENR_XSPI2LPEN_Pos (12U) +#define RCC_AHB5LPENR_XSPI2LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENR_XSPI2LPEN RCC_AHB5LPENR_XSPI2LPEN_Msk +#define RCC_AHB5LPENR_XSPIMLPEN_Pos (14U) +#define RCC_AHB5LPENR_XSPIMLPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5LPENR_XSPIMLPEN RCC_AHB5LPENR_XSPIMLPEN_Msk +#define RCC_AHB5LPENR_GFXMMULPEN_Pos (19U) +#define RCC_AHB5LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENR_GFXMMULPEN RCC_AHB5LPENR_GFXMMULPEN_Msk +#define RCC_AHB5LPENR_DTCM1LPEN_Pos (28U) +#define RCC_AHB5LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB5LPENR_DTCM1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENR_DTCM1LPEN RCC_AHB5LPENR_DTCM1LPEN_Msk +#define RCC_AHB5LPENR_DTCM2LPEN_Pos (29U) +#define RCC_AHB5LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB5LPENR_DTCM2LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENR_DTCM2LPEN RCC_AHB5LPENR_DTCM2LPEN_Msk +#define RCC_AHB5LPENR_ITCMLPEN_Pos (30U) +#define RCC_AHB5LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB5LPENR_ITCMLPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB5LPENR_ITCMLPEN RCC_AHB5LPENR_ITCMLPEN_Msk +#define RCC_AHB5LPENR_AXISRAMLPEN_Pos (31U) +#define RCC_AHB5LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB5LPENR_AXISRAMLPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB5LPENR_AXISRAMLPEN RCC_AHB5LPENR_AXISRAMLPEN_Msk + +/******************** Bit definition for RCC_APB1LPENR1 register ************/ +#define RCC_APB1LPENR1_TIM2LPEN_Pos (0U) +#define RCC_APB1LPENR1_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENR1_TIM2LPEN RCC_APB1LPENR1_TIM2LPEN_Msk +#define RCC_APB1LPENR1_TIM3LPEN_Pos (1U) +#define RCC_APB1LPENR1_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENR1_TIM3LPEN RCC_APB1LPENR1_TIM3LPEN_Msk +#define RCC_APB1LPENR1_TIM4LPEN_Pos (2U) +#define RCC_APB1LPENR1_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENR1_TIM4LPEN RCC_APB1LPENR1_TIM4LPEN_Msk +#define RCC_APB1LPENR1_TIM5LPEN_Pos (3U) +#define RCC_APB1LPENR1_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENR1_TIM5LPEN RCC_APB1LPENR1_TIM5LPEN_Msk +#define RCC_APB1LPENR1_TIM6LPEN_Pos (4U) +#define RCC_APB1LPENR1_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENR1_TIM6LPEN RCC_APB1LPENR1_TIM6LPEN_Msk +#define RCC_APB1LPENR1_TIM7LPEN_Pos (5U) +#define RCC_APB1LPENR1_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR1_TIM7LPEN RCC_APB1LPENR1_TIM7LPEN_Msk +#define RCC_APB1LPENR1_TIM12LPEN_Pos (6U) +#define RCC_APB1LPENR1_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENR1_TIM12LPEN RCC_APB1LPENR1_TIM12LPEN_Msk +#define RCC_APB1LPENR1_TIM13LPEN_Pos (7U) +#define RCC_APB1LPENR1_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENR1_TIM13LPEN RCC_APB1LPENR1_TIM13LPEN_Msk +#define RCC_APB1LPENR1_TIM14LPEN_Pos (8U) +#define RCC_APB1LPENR1_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR1_TIM14LPEN RCC_APB1LPENR1_TIM14LPEN_Msk +#define RCC_APB1LPENR1_LPTIM1LPEN_Pos (9U) +#define RCC_APB1LPENR1_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos)/*!< 0x00000200 */ +#define RCC_APB1LPENR1_LPTIM1LPEN RCC_APB1LPENR1_LPTIM1LPEN_Msk +#define RCC_APB1LPENR1_WWDGLPEN_Pos (11U) +#define RCC_APB1LPENR1_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENR1_WWDGLPEN RCC_APB1LPENR1_WWDGLPEN_Msk +#define RCC_APB1LPENR1_SPI2LPEN_Pos (14U) +#define RCC_APB1LPENR1_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENR1_SPI2LPEN RCC_APB1LPENR1_SPI2LPEN_Msk +#define RCC_APB1LPENR1_SPI3LPEN_Pos (15U) +#define RCC_APB1LPENR1_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENR1_SPI3LPEN RCC_APB1LPENR1_SPI3LPEN_Msk +#define RCC_APB1LPENR1_SPDIFRXLPEN_Pos (16U) +#define RCC_APB1LPENR1_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LPENR1_SPDIFRXLPEN_Pos)/*!< 0x00010000 */ +#define RCC_APB1LPENR1_SPDIFRXLPEN RCC_APB1LPENR1_SPDIFRXLPEN_Msk +#define RCC_APB1LPENR1_USART2LPEN_Pos (17U) +#define RCC_APB1LPENR1_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos)/*!< 0x00020000 */ +#define RCC_APB1LPENR1_USART2LPEN RCC_APB1LPENR1_USART2LPEN_Msk +#define RCC_APB1LPENR1_USART3LPEN_Pos (18U) +#define RCC_APB1LPENR1_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos)/*!< 0x00040000 */ +#define RCC_APB1LPENR1_USART3LPEN RCC_APB1LPENR1_USART3LPEN_Msk +#define RCC_APB1LPENR1_UART4LPEN_Pos (19U) +#define RCC_APB1LPENR1_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENR1_UART4LPEN RCC_APB1LPENR1_UART4LPEN_Msk +#define RCC_APB1LPENR1_UART5LPEN_Pos (20U) +#define RCC_APB1LPENR1_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENR1_UART5LPEN RCC_APB1LPENR1_UART5LPEN_Msk +#define RCC_APB1LPENR1_I2C1_I3C1LPEN_Pos (21U) +#define RCC_APB1LPENR1_I2C1_I3C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C1_I3C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENR1_I2C1_I3C1LPEN RCC_APB1LPENR1_I2C1_I3C1LPEN_Msk +#define RCC_APB1LPENR1_I2C2LPEN_Pos (22U) +#define RCC_APB1LPENR1_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENR1_I2C2LPEN RCC_APB1LPENR1_I2C2LPEN_Msk +#define RCC_APB1LPENR1_I2C3LPEN_Pos (23U) +#define RCC_APB1LPENR1_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENR1_I2C3LPEN RCC_APB1LPENR1_I2C3LPEN_Msk +#define RCC_APB1LPENR1_CECLPEN_Pos (27U) +#define RCC_APB1LPENR1_CECLPEN_Msk (0x1UL << RCC_APB1LPENR1_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1LPENR1_CECLPEN RCC_APB1LPENR1_CECLPEN_Msk +#define RCC_APB1LPENR1_UART7LPEN_Pos (30U) +#define RCC_APB1LPENR1_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENR1_UART7LPEN RCC_APB1LPENR1_UART7LPEN_Msk +#define RCC_APB1LPENR1_UART8LPEN_Pos (31U) +#define RCC_APB1LPENR1_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENR1_UART8LPEN RCC_APB1LPENR1_UART8LPEN_Msk + +/******************** Bit definition for RCC_PB1LPENR2 register ************/ +#define RCC_APB1LPENR2_CRSLPEN_Pos (1U) +#define RCC_APB1LPENR2_CRSLPEN_Msk (0x1UL << RCC_APB1LPENR2_CRSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENR2_CRSLPEN RCC_APB1LPENR2_CRSLPEN_Msk +#define RCC_APB1LPENR2_MDIOSLPEN_Pos (5U) +#define RCC_APB1LPENR2_MDIOSLPEN_Msk (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR2_MDIOSLPEN RCC_APB1LPENR2_MDIOSLPEN_Msk +#define RCC_APB1LPENR2_FDCANLPEN_Pos (8U) +#define RCC_APB1LPENR2_FDCANLPEN_Msk (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR2_FDCANLPEN RCC_APB1LPENR2_FDCANLPEN_Msk +#define RCC_APB1LPENR2_UCPD1LPEN_Pos (27U) +#define RCC_APB1LPENR2_UCPD1LPEN_Msk (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1LPENR2_UCPD1LPEN RCC_APB1LPENR2_UCPD1LPEN_Msk + +/******************** Bit definition for RCC_APB2LPENR register *************/ +#define RCC_APB2LPENR_TIM1LPEN_Pos (0U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk +#define RCC_APB2LPENR_USART1LPEN_Pos (4U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk +#define RCC_APB2LPENR_SPI4LPEN_Pos (13U) +#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk +#define RCC_APB2LPENR_TIM15LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk +#define RCC_APB2LPENR_TIM16LPEN_Pos (17U) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk +#define RCC_APB2LPENR_TIM17LPEN_Pos (18U) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk +#define RCC_APB2LPENR_TIM9LPEN_Pos (19U) +#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk +#define RCC_APB2LPENR_SPI5LPEN_Pos (20U) +#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk +#define RCC_APB2LPENR_SAI1LPEN_Pos (22U) +#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk +#define RCC_APB2LPENR_SAI2LPEN_Pos (23U) +#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk + +/******************** Bit definition for RCC_APB4LPENR register *************/ +#define RCC_APB4LPENR_SBSLPEN_Pos (1U) +#define RCC_APB4LPENR_SBSLPEN_Msk (0x1UL << RCC_APB4LPENR_SBSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENR_SBSLPEN RCC_APB4LPENR_SBSLPEN_Msk +#define RCC_APB4LPENR_LPUART1LPEN_Pos (3U) +#define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos)/*!< 0x00000008 */ +#define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk +#define RCC_APB4LPENR_SPI6LPEN_Pos (5U) +#define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk +#define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U) +#define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk +#define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U) +#define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk +#define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U) +#define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk +#define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U) +#define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk +#define RCC_APB4LPENR_VREFLPEN_Pos (15U) +#define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk +#define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U) +#define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk +#define RCC_APB4LPENR_DTSLPEN_Pos (26U) +#define RCC_APB4LPENR_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */ +#define RCC_APB4LPENR_DTSLPEN RCC_APB4LPENR_DTSLPEN_Msk + +/******************** Bit definition for RCC_APB5LPENR register *************/ +#define RCC_APB5LPENR_DCMIPPLPEN_Pos (2U) +#define RCC_APB5LPENR_DCMIPPLPEN_Msk (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENR_DCMIPPLPEN RCC_APB5LPENR_DCMIPPLPEN_Msk +#define RCC_APB5LPENR_GFXTIMLPEN_Pos (4U) +#define RCC_APB5LPENR_GFXTIMLPEN_Msk (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENR_GFXTIMLPEN RCC_APB5LPENR_GFXTIMLPEN_Msk + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Secure Advanced Encryption Standard (SAES) */ +/* */ +/******************************************************************************/ +/******************* Bits definition for SAES_CR register *********************/ +#define SAES_CR_EN_Pos (0U) +#define SAES_CR_EN_Msk (0x1UL << SAES_CR_EN_Pos) /*!< 0x00000001 */ +#define SAES_CR_EN SAES_CR_EN_Msk /*!< SAES Enable */ +#define SAES_CR_DATATYPE_Pos (1U) +#define SAES_CR_DATATYPE_Msk (0x3UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define SAES_CR_DATATYPE SAES_CR_DATATYPE_Msk /*!< Data type selection */ +#define SAES_CR_DATATYPE_0 (0x1UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define SAES_CR_DATATYPE_1 (0x2UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define SAES_CR_MODE_Pos (3U) +#define SAES_CR_MODE_Msk (0x3UL << SAES_CR_MODE_Pos) /*!< 0x00000018 */ +#define SAES_CR_MODE SAES_CR_MODE_Msk /*!< SAES Mode Of Operation */ +#define SAES_CR_MODE_0 (0x1UL << SAES_CR_MODE_Pos) /*!< 0x00000008 */ +#define SAES_CR_MODE_1 (0x2UL << SAES_CR_MODE_Pos) /*!< 0x00000010 */ +#define SAES_CR_CHMOD_Pos (5U) +#define SAES_CR_CHMOD_Msk (0x803UL << SAES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define SAES_CR_CHMOD SAES_CR_CHMOD_Msk /*!< SAES Chaining Mode */ +#define SAES_CR_CHMOD_0 (0x001UL << SAES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define SAES_CR_CHMOD_1 (0x002UL << SAES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define SAES_CR_CHMOD_2 (0x800UL << SAES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define SAES_CR_DMAINEN_Pos (11U) +#define SAES_CR_DMAINEN_Msk (0x1UL << SAES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define SAES_CR_DMAINEN SAES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define SAES_CR_DMAOUTEN_Pos (12U) +#define SAES_CR_DMAOUTEN_Msk (0x1UL << SAES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define SAES_CR_DMAOUTEN SAES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ +#define SAES_CR_GCMPH_Pos (13U) +#define SAES_CR_GCMPH_Msk (0x3UL << SAES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define SAES_CR_GCMPH SAES_CR_GCMPH_Msk /*!< GCM Phase */ +#define SAES_CR_GCMPH_0 (0x1UL << SAES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define SAES_CR_GCMPH_1 (0x2UL << SAES_CR_GCMPH_Pos) /*!< 0x00004000 */ +#define SAES_CR_KEYSIZE_Pos (18U) +#define SAES_CR_KEYSIZE_Msk (0x1UL << SAES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define SAES_CR_KEYSIZE SAES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define SAES_CR_NPBLB_Pos (20U) +#define SAES_CR_NPBLB_Msk (0xFUL << SAES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define SAES_CR_NPBLB SAES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define SAES_CR_NPBLB_0 (0x1UL << SAES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define SAES_CR_NPBLB_1 (0x2UL << SAES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define SAES_CR_NPBLB_2 (0x4UL << SAES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define SAES_CR_NPBLB_3 (0x8UL << SAES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define SAES_CR_KMOD_Pos (24U) +#define SAES_CR_KMOD_Msk (0x3UL << SAES_CR_KMOD_Pos) /*!< 0x00000006 */ +#define SAES_CR_KMOD SAES_CR_KMOD_Msk /*!< Key mode selection */ +#define SAES_CR_KMOD_0 (0x1UL << SAES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define SAES_CR_KMOD_1 (0x2UL << SAES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define SAES_CR_KSHAREID_Pos (26U) +#define SAES_CR_KSHAREID_Msk (0x3UL << SAES_CR_KSHAREID_Pos) /*!< 0x00000006 */ +#define SAES_CR_KSHAREID SAES_CR_KSHAREID_Msk /*!< Key Shared ID */ +#define SAES_CR_KEYSEL_Pos (28U) +#define SAES_CR_KEYSEL_Msk (0x7UL << SAES_CR_KEYSEL_Pos) /*!< 0x00000006 */ +#define SAES_CR_KEYSEL SAES_CR_KEYSEL_Msk /*!< Key Selection */ +#define SAES_CR_KEYSEL_0 (0x1UL << SAES_CR_KEYSEL_Pos) /*!< 0x02000000 */ +#define SAES_CR_KEYSEL_1 (0x2UL << SAES_CR_KEYSEL_Pos) /*!< 0x02000000 */ +#define SAES_CR_KEYSEL_2 (0x4UL << SAES_CR_KEYSEL_Pos) /*!< 0x02000000 */ +#define SAES_CR_IPRST_Pos (31U) +#define SAES_CR_IPRST_Msk (0x1UL << SAES_CR_IPRST_Pos) /*!< 0x80000001 */ +#define SAES_CR_IPRST SAES_CR_IPRST_Msk /*!< SAES IP software reset */ + +/******************* Bits definition for SAES_SR register *********************/ +#define SAES_SR_CCF_Pos (0U) +#define SAES_SR_CCF_Msk (0x1UL << SAES_SR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_SR_CCF SAES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define SAES_SR_RDERR_Pos (1U) +#define SAES_SR_RDERR_Msk (0x1UL << SAES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define SAES_SR_RDERR SAES_SR_RDERR_Msk /*!< Read Error Flag */ +#define SAES_SR_WRERR_Pos (2U) +#define SAES_SR_WRERR_Msk (0x1UL << SAES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define SAES_SR_WRERR SAES_SR_WRERR_Msk /*!< Write Error Flag */ +#define SAES_SR_BUSY_Pos (3U) +#define SAES_SR_BUSY_Msk (0x1UL << SAES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define SAES_SR_BUSY SAES_SR_BUSY_Msk /*!< Busy Flag */ +#define SAES_SR_KEYVALID_Pos (7U) +#define SAES_SR_KEYVALID_Msk (0x1UL << SAES_SR_KEYVALID_Pos) /*!< 0x00000008 */ +#define SAES_SR_KEYVALID SAES_SR_KEYVALID_Msk /*!< KEYVALID Flag */ + +/******************* Bits definition for SAES_DINR register *******************/ +#define SAES_DINR_Pos (0U) +#define SAES_DINR_Msk (0xFFFFFFFFUL << SAES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define SAES_DINR SAES_DINR_Msk /*!< SAES Data Input Register */ + +/******************* Bits definition for SAES_DOUTR register ******************/ +#define SAES_DOUTR_Pos (0U) +#define SAES_DOUTR_Msk (0xFFFFFFFFUL << SAES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define SAES_DOUTR SAES_DOUTR_Msk /*!< SAES Data Output Register */ + +/******************* Bits definition for SAES_KEYR0 register ******************/ +#define SAES_KEYR0_Pos (0U) +#define SAES_KEYR0_Msk (0xFFFFFFFFUL << SAES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR0 SAES_KEYR0_Msk /*!< SAES Key Register 0 */ + +/******************* Bits definition for SAES_KEYR1 register ******************/ +#define SAES_KEYR1_Pos (0U) +#define SAES_KEYR1_Msk (0xFFFFFFFFUL << SAES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR1 SAES_KEYR1_Msk /*!< SAES Key Register 1 */ + +/******************* Bits definition for SAES_KEYR2 register ******************/ +#define SAES_KEYR2_Pos (0U) +#define SAES_KEYR2_Msk (0xFFFFFFFFUL << SAES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR2 SAES_KEYR2_Msk /*!< SAES Key Register 2 */ + +/******************* Bits definition for SAES_KEYR3 register ******************/ +#define SAES_KEYR3_Pos (0U) +#define SAES_KEYR3_Msk (0xFFFFFFFFUL << SAES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR3 SAES_KEYR3_Msk /*!< SAES Key Register 3 */ + +/******************* Bits definition for SAES_KEYR4 register ******************/ +#define SAES_KEYR4_Pos (0U) +#define SAES_KEYR4_Msk (0xFFFFFFFFUL << SAES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR4 SAES_KEYR4_Msk /*!< SAES Key Register 4 */ + +/******************* Bits definition for SAES_KEYR5 register ******************/ +#define SAES_KEYR5_Pos (0U) +#define SAES_KEYR5_Msk (0xFFFFFFFFUL << SAES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR5 SAES_KEYR5_Msk /*!< SAES Key Register 5 */ + +/******************* Bits definition for SAES_KEYR6 register ******************/ +#define SAES_KEYR6_Pos (0U) +#define SAES_KEYR6_Msk (0xFFFFFFFFUL << SAES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR6 SAES_KEYR6_Msk /*!< SAES Key Register 6 */ + +/******************* Bits definition for SAES_KEYR7 register ******************/ +#define SAES_KEYR7_Pos (0U) +#define SAES_KEYR7_Msk (0xFFFFFFFFUL << SAES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR7 SAES_KEYR7_Msk /*!< SAES Key Register 7 */ + +/******************* Bits definition for SAES_IVR0 register ******************/ +#define SAES_IVR0_Pos (0U) +#define SAES_IVR0_Msk (0xFFFFFFFFUL << SAES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR0 SAES_IVR0_Msk /*!< SAES Initialization Vector Register 0 */ + +/******************* Bits definition for SAES_IVR1 register ******************/ +#define SAES_IVR1_Pos (0U) +#define SAES_IVR1_Msk (0xFFFFFFFFUL << SAES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR1 SAES_IVR1_Msk /*!< SAES Initialization Vector Register 1 */ + +/******************* Bits definition for SAES_IVR2 register ******************/ +#define SAES_IVR2_Pos (0U) +#define SAES_IVR2_Msk (0xFFFFFFFFUL << SAES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR2 SAES_IVR2_Msk /*!< SAES Initialization Vector Register 2 */ + +/******************* Bits definition for SAES_IVR3 register ******************/ +#define SAES_IVR3_Pos (0U) +#define SAES_IVR3_Msk (0xFFFFFFFFUL << SAES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR3 SAES_IVR3_Msk /*!< SAES Initialization Vector Register 3 */ + +/******************* Bit definition for SAES_SUSP0R register ******************/ +#define SAES_SUSP0R_Pos (0U) +#define SAES_SUSP0R_Msk (0xFFFFFFFFUL << SAES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP0R SAES_SUSP0R_Msk /*!< SAES Suspend registers 0 */ + +/******************* Bit definition for SAES_SUSP1R register ******************/ +#define SAES_SUSP1R_Pos (0U) +#define SAES_SUSP1R_Msk (0xFFFFFFFFUL << SAES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP1R SAES_SUSP1R_Msk /*!< SAES Suspend registers 1 */ + +/******************* Bit definition for SAES_SUSP2R register ******************/ +#define SAES_SUSP2R_Pos (0U) +#define SAES_SUSP2R_Msk (0xFFFFFFFFUL << SAES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP2R SAES_SUSP2R_Msk /*!< SAES Suspend registers 2 */ + +/******************* Bit definition for SAES_SUSP3R register ******************/ +#define SAES_SUSP3R_Pos (0U) +#define SAES_SUSP3R_Msk (0xFFFFFFFFUL << SAES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP3R SAES_SUSP3R_Msk /*!< SAES Suspend registers 3 */ + +/******************* Bit definition for SAES_SUSP4R register ******************/ +#define SAES_SUSP4R_Pos (0U) +#define SAES_SUSP4R_Msk (0xFFFFFFFFUL << SAES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP4R SAES_SUSP4R_Msk /*!< SAES Suspend registers 4 */ + +/******************* Bit definition for SAES_SUSP5R register ******************/ +#define SAES_SUSP5R_Pos (0U) +#define SAES_SUSP5R_Msk (0xFFFFFFFFUL << SAES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP5R SAES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for SAES_SUSP6R register ******************/ +#define SAES_SUSP6R_Pos (0U) +#define SAES_SUSP6R_Msk (0xFFFFFFFFUL << SAES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP6R SAES_SUSP6R_Msk /*!< SAES Suspend registers 6 */ + +/******************* Bit definition for SAES_SUSP7R register ******************/ +#define SAES_SUSP7R_Pos (0U) +#define SAES_SUSP7R_Msk (0xFFFFFFFFUL << SAES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP7R SAES_SUSP7R_Msk /*!< SAES Suspend registers 7 */ + +/******************* Bits definition for SAES_IER register ******************/ +#define SAES_IER_CCFIE_Pos (0U) +#define SAES_IER_CCFIE_Msk (0x1UL << SAES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define SAES_IER_CCFIE SAES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ +#define SAES_IER_RWEIE_Pos (1U) +#define SAES_IER_RWEIE_Msk (0x1UL << SAES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define SAES_IER_RWEIE SAES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ +#define SAES_IER_KEIE_Pos (2U) +#define SAES_IER_KEIE_Msk (0x1UL << SAES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define SAES_IER_KEIE SAES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define SAES_IER_RNGEIE_Pos (3U) +#define SAES_IER_RNGEIE_Msk (0x1UL << SAES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define SAES_IER_RNGEIE SAES_IER_RNGEIE_Msk /*!< Rng error interrupt enable */ + +/******************* Bits definition for SAES_ISR register ******************/ +#define SAES_ISR_CCF_Pos (0U) +#define SAES_ISR_CCF_Msk (0x1UL << SAES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_ISR_CCF SAES_ISR_CCF_Msk /*!< Computation complete flag */ +#define SAES_ISR_RWEIF_Pos (1U) +#define SAES_ISR_RWEIF_Msk (0x1UL << SAES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define SAES_ISR_RWEIF SAES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ +#define SAES_ISR_KEIF_Pos (2U) +#define SAES_ISR_KEIF_Msk (0x1UL << SAES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define SAES_ISR_KEIF SAES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define SAES_ISR_RNGEIF_Pos (3U) +#define SAES_ISR_RNGEIF_Msk (0x1UL << SAES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define SAES_ISR_RNGEIF SAES_ISR_RNGEIF_Msk /*!< Rng error interrupt flag */ + +/******************* Bits definition for SAES_ICR register ******************/ +#define SAES_ICR_CCF_Pos (0U) +#define SAES_ICR_CCF_Msk (0x1UL << SAES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_ICR_CCF SAES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define SAES_ICR_RWEIF_Pos (1U) +#define SAES_ICR_RWEIF_Msk (0x1UL << SAES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define SAES_ICR_RWEIF SAES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ +#define SAES_ICR_KEIF_Pos (2U) +#define SAES_ICR_KEIF_Msk (0x1UL << SAES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define SAES_ICR_KEIF SAES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define SAES_ICR_RNGEIF_Pos (3U) +#define SAES_ICR_RNGEIF_Msk (0x1UL << SAES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define SAES_ICR_RNGEIF SAES_ICR_RNGEIF_Msk /*!< Rng error interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! /*!< ARM Cortex-M7 processor and core peripherals */ +#include "system_stm32h7rsxx.h" /*!< STM32H7RSxx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H7RSxx_peripherals + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[4];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t OR; /*!< ADC option register, Address offset: 0xC8 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief AXIM ASIB + */ +typedef struct +{ + uint32_t RESERVED1[9]; /*!< Reserved, Address offset: 0x00-0x20 */ + __IO uint32_t FNMOD2; /*!< AXIM ASIB fn_mod2 register Address offset: 0x24 */ + uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x28-0xFC */ + __IO uint32_t READQOS; /*!< AXIM ASIB read_qos register Address offset: 0x100 */ + __IO uint32_t WRITEQOS; /*!< AXIM ASIB write_qos register Address offset: 0x104 */ + __IO uint32_t FNMOD; /*!< AXIM ASIB fn_mod register Address offset: 0x108 */ +} AXIM_ASIB_TypeDef; + +typedef struct +{ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x00-0x04 */ + __IO uint32_t FNMODBMISS; /*!< AXIM AMIB fn_mod_bm_iss register Address offset: 0x08 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x0C-0x20 */ + __IO uint32_t FNMOD2; /*!< AXIM AMIB fn_mod2 register Address offset: 0x24 */ + uint32_t RESERVED3[1]; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t FNMODLB; /*!< AXIM AMIB fn_mod_lb register Address offset: 0x2C */ + uint32_t RESERVED5[54]; /*!< Reserved, Address offset: 0x30-0x104 */ + __IO uint32_t FNMOD; /*!< AXIM AMIB fn_mod register Address offset: 0x108 */ +} AXIM_AMIB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +} CEC_TypeDef; + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC Control and Status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief GFXTIM + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXTIM configuration register, Address offset: 0x00 */ + __IO uint32_t CGCR; /*!< GFXTIM clock generator configuration register, Address offset: 0x04 */ + __IO uint32_t TCR; /*!< GFXTIM timers configuration register, Address offset: 0x08 */ + __IO uint32_t TDR; /*!< GFXTIM timers disable register, Address offset: 0x0C */ + __IO uint32_t EVCR; /*!< GFXTIM events control register, Address offset: 0x10 */ + __IO uint32_t EVSR; /*!< GFXTIM events selection register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WDGTCR; /*!< GFXTIM watchdog timer configuration register, Address offset: 0x20 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t ISR; /*!< GFXTIM interrupt status register, Address offset: 0x30 */ + __IO uint32_t ICR; /*!< GFXTIM interrupt clear register, Address offset: 0x34 */ + __IO uint32_t IER; /*!< GFXTIM interrupt enable register, Address offset: 0x38 */ + __IO uint32_t TSR; /*!< GFXTIM timers status register, Address offset: 0x3C */ + __IO uint32_t LCCRR; /*!< GFXTIM line clock counter reload register, Address offset: 0x40 */ + __IO uint32_t FCCRR; /*!< GFXTIM frame clock counter reload register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48-0x4C */ + __IO uint32_t ATR; /*!< GFXTIM absolute time register, Address offset: 0x50 */ + __IO uint32_t AFCR; /*!< GFXTIM absolute frame counter register, Address offset: 0x54 */ + __IO uint32_t ALCR; /*!< GFXTIM absolute line counter register, Address offset: 0x58 */ + uint32_t RESERVED4[1]; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t AFCC1R; /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */ + uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x64-0X6C */ + __IO uint32_t ALCC1R; /*!< GFXTIM absolute line counter compare 1 register, Address offset: 0x70 */ + __IO uint32_t ALCC2R; /*!< GFXTIM absolute line counter compare 2 register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x78-0X7C */ + __IO uint32_t RFC1R; /*!< GFXTIM relative frame counter 1 register, Address offset: 0x80 */ + __IO uint32_t RFC1RR; /*!< GFXTIM relative frame counter 1 reload register, Address offset: 0x84 */ + __IO uint32_t RFC2R; /*!< GFXTIM relative frame counter 2 register, Address offset: 0x88 */ + __IO uint32_t RFC2RR; /*!< GFXTIM relative frame counter 2 reload register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x90-0X9C */ + __IO uint32_t WDGCR; /*!< GFXTIM watchdog counter register, Address offset: 0xA0 */ + __IO uint32_t WDGRR; /*!< GFXTIM watchdog reload register, Address offset: 0xA4 */ + __IO uint32_t WDGPAR; /*!< GFXTIM watchdog pre-alarm register, Address offset: 0xA8 */ + uint32_t RESERVED8[209]; /*!< Reserved, Address offset: 0xAC-0X3EC */ + __IO uint32_t HWCFGR; /*!< GFXTIM HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GFXTIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GFXTIM identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GFXTIM size identification register, Address offset: 0x3FC */ +} GFXTIM_TypeDef; + + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Cryp Processor + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ +} CRYP_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t AHB5FZR; /*!< Debug MCU AHB5FZR freeze register, Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1FZR freeze register, Address offset: 0x24 */ + uint32_t RESERVED3[5]; /*!< Reserved, Address offset: 0x28-0x38 */ + __IO uint32_t APB1FZR; /*!< Debug MCU APB1FZR freeze register, Address offset: 0x3C */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x40-0x48 */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2FZR freeze register, Address offset: 0x4C */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZR; /*!< Debug MCU APB4FZR freeze register, Address offset: 0x54 */ + uint32_t RESERVED6[41]; /*!< Reserved, Address offset: 0x58-0xF8 */ + __IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU Authentication Host register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug MCU Authentication Device register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug MCU Authentication Ack register, Address offset: 0x108 */ + uint32_t RESERVED7[945]; /*!< Reserved, Address offset: 0x10C-0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU peripheral identity register 4, Address offset: 0xFD0 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0xFD4-0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMIPP + */ +typedef struct +{ + __IO uint32_t IPGR1; /*!< IP-Plug global register 1 Address offset: 0x00 */ + __IO uint32_t IPGR2; /*!< IP-Plug global register 2 Address offset: 0x04 */ + __IO uint32_t IPGR3; /*!< IP-Plug global register 3 Address offset: 0x08 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x0C-0x18 */ + __IO uint32_t IPGR8; /*!< IP-Plug global register 8 Address offset: 0x1C */ + __IO uint32_t IPC1R1; /*!< IP-Plug client 1 register 1 Address offset: 0x20 */ + __IO uint32_t IPC1R2; /*!< IP-Plug client 1 register 2 Address offset: 0x24 */ + __IO uint32_t IPC1R3; /*!< IP-Plug client 1 register 3 Address offset: 0x28 */ + __IO uint32_t RESERVED2[54]; /*!< Reserved, Address offset: 0x2C-0x100 */ + __IO uint32_t PRCR; /*!< Parallel interface control register Address offset: 0x104 */ + __IO uint32_t PRESCR; /*!< Parallel interface embedded sync code register Address offset: 0x108 */ + __IO uint32_t PRESUR; /*!< Parallel interface embedded sync unmask register Address offset: 0x10C */ + __IO uint32_t RESERVED3[57]; /*!< Reserved, Address offset: 0x110-0x1F0 */ + __IO uint32_t PRIER; /*!< Parallel interface interrupt enable register Address offset: 0x1F4 */ + __IO uint32_t PRSR; /*!< Parallel interface status register Address offset: 0x1F8 */ + __IO uint32_t PRFCR; /*!< Parallel interface interrupt clear register Address offset: 0x1FC */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x200 */ + __IO uint32_t CMCR; /*!< Common configuration register Address offset: 0x204 */ + __IO uint32_t CMFRCR; /*!< Common frame counter register Address offset: 0x208 */ + __IO uint32_t RESERVED5[121]; /*!< Reserved, Address offset: 0x20C-0x3EC */ + __IO uint32_t CMIER; /*!< Common interrupt enable register Address offset: 0x3F0 */ + __IO uint32_t CMSR1; /*!< Common status register 1 Address offset: 0x3F4 */ + __IO uint32_t CMSR2; /*!< Common status register 2 Address offset: 0x3F8 */ + __IO uint32_t CMFCR; /*!< Common interrupt clear register Address offset: 0x3FC */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x400 */ + __IO uint32_t P0FSCR; /*!< Pipe0 flow selection configuration register Address offset: 0x404 */ + __IO uint32_t RESERVED7[62]; /*!< Reserved, Address offset: 0x408-0x4FC */ + __IO uint32_t P0FCTCR; /*!< Pipe0 flow control configuration register Address offset: 0x500 */ + __IO uint32_t P0SCSTR; /*!< Pipe0 stat/crop start register Address offset: 0x504 */ + __IO uint32_t P0SCSZR; /*!< Pipe0 stat/crop size register Address offset: 0x508 */ + __IO uint32_t RESERVED8[41]; /*!< Reserved, Address offset: 0x50C-0x5AC */ + __IO uint32_t P0DCCNTR; /*!< Pipe0 dump counter register Address offset: 0x5B0 */ + __IO uint32_t P0DCLMTR; /*!< Pipe0 dump limit register Address offset: 0x5B4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x5B8-0x5BC */ + __IO uint32_t P0PPCR; /*!< Pipe0 pixel packer configuration register Address offset: 0x5C0 */ + __IO uint32_t P0PPM0AR1; /*!< Pipe0 pixel packer memory0 address register 1 Address offset: 0x5C4 */ + __IO uint32_t P0PPM0AR2; /*!< Pipe0 pixel packer memory0 address register 2 Address offset: 0x5C8 */ + __IO uint32_t RESERVED10[10]; /*!< Reserved, Address offset: 0x5CC-0x5F0 */ + __IO uint32_t P0IER; /*!< Pipe0 interrupt enable register Address offset: 0x5F4 */ + __IO uint32_t P0SR; /*!< Pipe0 status register Address offset: 0x5F8 */ + __IO uint32_t P0FCR; /*!< Pipe0 interrupt clear register Address offset: 0x5FC */ + __IO uint32_t RESERVED11[64]; /*!< Reserved, Address offset: 0x600-0x6FC */ + __IO uint32_t P0CFCTCR; /*!< Pipe0 current flow control configuration register Address offset: 0x700 */ + __IO uint32_t P0CSCSTR; /*!< Pipe0 current stat/crop start register Address offset: 0x704 */ + __IO uint32_t P0CSCSZR; /*!< Pipe0 current stat/crop size register Address offset: 0x708 */ + __IO uint32_t RESERVED12[45]; /*!< Reserved, Address offset: 0x70C-0x7BC */ + __IO uint32_t P0CPPCR; /*!< Pipe0 current pixel packer configuration register Address offset: 0x700 */ + __IO uint32_t P0CPPM0AR1; /*!< Pipe0 current pixel packer memory0 address register 1 Address offset: 0x7C4 */ + __IO uint32_t P0CPPM0AR2; /*!< Pipe0 current pixel packer memory0 address register 2 Address offset: 0x7C8 */ +} DCMIPP_TypeDef; + +/** + * @ brief Delay Block + */ +typedef struct +{ + __IO uint32_t CR; /*!< Delay Block Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA masked interrupt status register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */ +} DMA2D_TypeDef; + +/** + * @brief DTS + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */ + __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */ + __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */ + __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */ + __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */ +} DTS_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x08 */ + uint32_t RESERVED1[5]; /*!< Reserved 1, Address offset: 0x0C-0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x28 */ + uint32_t RESERVED2[21]; /*!< Reserved 2, Address offset: 0x2C-0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x84 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x88 */ + uint32_t RESERVED3; /*!< Reserved 3, Address offset: 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x94 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x98 */ + uint32_t RESERVED4; /*!< Reserved 4, Address offset: 0x9C */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register 3, Address offset: 0xA0 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register 3, Address offset: 0xA4 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x000 */ + __IO uint32_t KEYR; /*!< FLASH control key register, Address offset: 0x004 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x008 - 0x00C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x010 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t IER; /*!< FLASH interrupt enable register, Address offset: 0x020 */ + __IO uint32_t ISR; /*!< FLASH interrupt status register, Address offset: 0x024 */ + __IO uint32_t ICR; /*!< FLASH interrupt clear register, Address offset: 0x028 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t CRCCR; /*!< FLASH CRC control register, Address offset: 0x030 */ + __IO uint32_t CRCSADDR; /*!< FLASH CRC start address register, Address offset: 0x034 */ + __IO uint32_t CRCEADDR; /*!< FLASH CRC end address register, Address offset: 0x038 */ + __IO uint32_t CRCDATAR; /*!< FLASH CRC data register, Address offset: 0x03C */ + __IO uint32_t ECCSFADDR; /*!< FLASH ECC single fail address register, Address offset: 0x040 */ + __IO uint32_t ECCDFADDR; /*!< FLASH ECC double fail address register, Address offset: 0x044 */ + uint32_t RESERVED4[46]; /*!< Reserved, Address offset: 0x048 - 0x0FC */ + __IO uint32_t OPTKEYR; /*!< FLASH options key register, Address offset: 0x100 */ + __IO uint32_t OPTCR; /*!< FLASH options control register, Address offset: 0x104 */ + __IO uint32_t OPTISR; /*!< FLASH options interrupt status register, Address offset: 0x108 */ + __IO uint32_t OPTICR; /*!< FLASH options interrupt clear register, Address offset: 0x10C */ + __IO uint32_t OBKCR; /*!< FLASH option byte key control register, Address offset: 0x110 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x114 */ + __IO uint32_t OBKDR[8]; /*!< FLASH option bytes key data register, Address offset: 0x118 - 0x134 */ + uint32_t RESERVED6[50]; /*!< Reserved, Address offset: 0x138 - 0x1FC */ + __IO uint32_t NVSR; /*!< FLASH non-volatile status register, Address offset: 0x200 */ + __IO uint32_t NVSRP; /*!< FLASH security status register programming, Address offset: 0x204 */ + __IO uint32_t ROTSR; /*!< FLASH RoT status register, Address offset: 0x208 */ + __IO uint32_t ROTSRP; /*!< FLASH RoT status register programming, Address offset: 0x20C */ + __IO uint32_t OTPLSR; /*!< FLASH OTP lock status register, Address offset: 0x210 */ + __IO uint32_t OTPLSRP; /*!< FLASH OTP lock status programming register, Address offset: 0x214 */ + __IO uint32_t WRPSR; /*!< FLASH write protection status register, Address offset: 0x218 */ + __IO uint32_t WRPSRP; /*!< FLASH write protection status register programming, Address offset: 0x21C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x220 - 0x22C */ + __IO uint32_t HDPSR; /*!< FLASH hide protection status register, Address offset: 0x230 */ + __IO uint32_t HDPSRP; /*!< FLASH hide protection status register programming, Address offset: 0x234 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0x238 - 0x24C */ + __IO uint32_t EPOCHSR; /*!< FLASH epoch status register, Address offset: 0x250 */ + __IO uint32_t EPOCHSRP; /*!< FLASH epoch status register programming, Address offset: 0x254 */ + uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x258 - 0x25C */ + __IO uint32_t OBW1SR; /*!< FLASH option byte word 1 status register, Address offset: 0x260 */ + __IO uint32_t OBW1SRP; /*!< FLASH option byte word 1 status register programming, Address offset: 0x264 */ + __IO uint32_t OBW2SR; /*!< FLASH option byte word 2 status register, Address offset: 0x268 */ + __IO uint32_t OBW2SRP; /*!< FLASH option byte word 2 status register programming, Address offset: 0x26C */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1 + */ +typedef struct { + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1 Extended + */ +typedef struct { + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct { + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 & 6 + */ +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140 - 0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148 - 0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief GFXMMU + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved0, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + __IO uint32_t DAR; /*!< GFXMMU default alpha register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved1, Address offset: 0x18 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + + +/** + * @brief Instruction Cache + */ + +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ +} ICACHE_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 0x00 */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 0x04 */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 0x08 */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0x0C */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 0x10 */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 0x14 */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 0x18 */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 0x1C */ + uint32_t RESERVED0[4]; /* Reserved Address offset: 0x20-0x2C */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 0x30 */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 0x34 */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 0x38 */ + uint32_t RESERVED1; /* Reserved Address offset: 0x3C */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 0x40 */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 0x44 */ + uint32_t RESERVED2[2]; /* Reserved Address offset: 0x48-0x4C */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 0x50-0x8C */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 0x90-0xCC */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: 0xD0-0x10C */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 0x110-0x14C */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 0x150-0x18C */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 0x190-0x20C */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 0x210-0x35C */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 0x360-0x4F8 */ + uint32_t RESERVED3; /* Reserved Address offset: 0x4FC */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 0x500-0x65C */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 0x660-0x7BC */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 0x7C0-0x7DC */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 0x7E0-0x7FC */ +} JPEG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Memory Cipher Engine (MCE) + */ +typedef struct +{ + __IO uint32_t REGCR; /*!< MCE region configuration register, Address offset: 0x040 + 0x10 * (x-1) (x = 1 to 4) */ + __IO uint32_t SADDR; /*!< MCE region start address register, Address offset: 0x044 + 0x10 * (x-1) (x = 1 to 4) */ + __IO uint32_t EADDR; /*!< MCE region end address register, Address offset: 0x048 + 0x10 * (x-1) (x = 1 to 4) */ + __IO uint32_t ATTR; /*!< MCE region attribute register, Address offset: 0x04C + 0x10 * (x-1) (x = 1 to 4) */ +} MCE_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CCCFGR; /*!< MCE cipher context configuration register, Address offset: 0x240 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCNR0; /*!< MCE cipher context nonce register 0, Address offset: 0x244 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCNR1; /*!< MCE cipher context nonce register 1, Address offset: 0x248 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR0; /*!< MCE cipher context key register 0, Address offset: 0x24C + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR1; /*!< MCE cipher context key register 1, Address offset: 0x250 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR2; /*!< MCE cipher context key register 2, Address offset: 0x254 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR3; /*!< MCE cipher context key register 3, Address offset: 0x258 + 0x30 * (x-1) (x = 1 to 2) */ +} MCE_Context_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MCE configuration register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< MCE status register, Address offset: 0x004 */ + __IO uint32_t IASR; /*!< MCE illegal access status register, Address offset: 0x008 */ + __IO uint32_t IACR; /*!< MCE illegal access clear register, Address offset: 0x00C */ + __IO uint32_t IAIER; /*!< MCE illegal access interrupt enable register, Address offset: 0x010 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x014-0x018 */ + __IO uint32_t PRIVCFGR; /*!< MCE privileged configuration register, Address offset: 0x01C */ + __IO uint32_t IAESR; /*!< MCE illegal access error status register, Address offset: 0x020 */ + __IO uint32_t IADDR; /*!< MCE illegal address register, Address offset: 0x024 */ + uint32_t RESERVED2[118]; /*!< Reserved, Address offset: 0x028-0x1FC */ + __IO uint32_t MKEYR0; /*!< MCE master key register 0, Address offset: 0x200 */ + __IO uint32_t MKEYR1; /*!< MCE master key register 1, Address offset: 0x204 */ + __IO uint32_t MKEYR2; /*!< MCE master key register 2, Address offset: 0x208 */ + __IO uint32_t MKEYR3; /*!< MCE master key register 3, Address offset: 0x20C */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x210-0x21C */ + __IO uint32_t FMKEYR0; /*!< MCE fast master key register 0, Address offset: 0x220 */ + __IO uint32_t FMKEYR1; /*!< MCE fast master key register 1, Address offset: 0x224 */ + __IO uint32_t FMKEYR2; /*!< MCE fast master key register 2, Address offset: 0x228 */ + __IO uint32_t FMKEYR3; /*!< MCE fast master key register 3, Address offset: 0x22C */ +} MCE_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + +/** + * @brief ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ +} MDF_TypeDef; + +/** + * @brief ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x94-0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + uint32_t RESERVED1[1]; /*!< Reserved, 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED3[10]; /*!< Reserved, 0xC8-0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0xA4-0xA8 */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0xB8-0xC0 */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0xC4 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief XSPI + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control Register, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration Register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration Register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration Register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration Register 4, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t SR; /*!< XSPI Status Register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear Register, Address offset: 0x024 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x028 - 0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length Register, Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address Register, Address offset: 0x048 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data Register, Address offset: 0x050 */ + uint32_t RESERVED6[11]; /*!< Reserved, Address offset: 0x054 - 0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask Register, Address offset: 0x080 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match Register, Address offset: 0x088 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval Register, Address offset: 0x090 */ + uint32_t RESERVED9[27]; /*!< Reserved, Address offset: 0x094 - 0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration Register, Address offset: 0x100 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration Register, Address offset: 0x108 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction Register, Address offset: 0x110 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x114 - 0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes Register, Address offset: 0x120 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x124 - 0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low-Power Timeout Register, Address offset: 0x130 */ + uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x134 - 0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration Register, Address offset: 0x140 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration Register, Address offset: 0x148 */ + uint32_t RESERVED16; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction Register, Address offset: 0x150 */ + uint32_t RESERVED17[3]; /*!< Reserved, Address offset: 0x154 - 0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes Register, Address offset: 0x160 */ + uint32_t RESERVED18[7]; /*!< Reserved, Address offset: 0x164 - 0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration Register, Address offset: 0x180 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration Register, Address offset: 0x188 */ + uint32_t RESERVED20; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction Register, Address offset: 0x190 */ + uint32_t RESERVED21[3]; /*!< Reserved, Address offset: 0x194 - 0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes Register, Address offset: 0x1A0 */ + uint32_t RESERVED22[23]; /*!< Reserved, Address offset: 0x1A4 - 0x1FC */ + __IO uint32_t HLCR; /*!< XSPI HyperBus Latency Configuration Register, Address offset: 0x200 */ + uint32_t RESERVED23[3]; /*!< Reserved, Address offset: 0x204 - 0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-Cycle Calibration Configuration Register, Address offset: 0x210 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL Master Calibration Configuration Register, Address offset: 0x218 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220 */ + uint32_t RESERVED26; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI Slave Input Calibration Configuration Register, Address offset: 0x228 */ +} XSPI_TypeDef; + +/** + * @brief XSPI IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPIM IO Manager Control Register, Address offset: 0x00 */ +} XSPIM_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x04 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x08 */ + __IO uint32_t CSR2; /*!< PWR power control status register 2, Address offset: 0x0C */ + __IO uint32_t CSR3; /*!< PWR power control status register 3, Address offset: 0x10 */ + __IO uint32_t CSR4; /*!< PWR power control status register 4, Address offset: 0x14 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< PWR USB Type-C and power delivery register, Address offset: 0x2C */ + __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x30 */ + __IO uint32_t PUCRN; /*!< PWR port N pull-up control register, Address offset: 0x34 */ + __IO uint32_t PDCRN; /*!< PWR port N pull-down control register, Address offset: 0x38 */ + __IO uint32_t PUCRO; /*!< PWR port O pull-up control register, Address offset: 0x3C */ + __IO uint32_t PDCRO; /*!< PWR port O pull-down control register, Address offset: 0x40 */ + __IO uint32_t PDCRP; /*!< PWR port P pull-down control register, Address offset: 0x44 */ + uint32_t RESERVED2[2]; /*!< Reserved */ + __IO uint32_t PDR1; /*!< PWR debug register 1, Address offset: 0x50 */ +} PWR_TypeDef; + +/** + * @brief Public Key Accelerator (PKA) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved1[253]; /*!< Reserved, Address offset: 0x000C-0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x0400-0x18D8 */ +} PKA_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI clock calibration register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock recovery RC register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI clock calibration register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CDCFGR; /*!< RCC CPU domain configuration register, Address offset: 0x18 */ + __IO uint32_t BMCFGR; /*!< RCC Bus matrix configuration register, Address offset: 0x1C */ + __IO uint32_t APBCFGR; /*!< RCC APB clock configuration register, Address offset: 0x20 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs clock source selection register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs configuration register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR1; /*!< RCC PLL1 dividers configuration register 1, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 fractional divider configuration register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR1; /*!< RCC PLL2 dividers configuration register 1, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 fractional divider configuration register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR1; /*!< RCC PLL3 dividers configuration register 1, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 fractional divider configuration register, Address offset: 0x44 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t CCIPR1; /*!< RCC AHB peripherals kernel clock configuration register Address offset: 0x4C */ + __IO uint32_t CCIPR2; /*!< RCC APB1 peripherals kernel clock configuration register Address offset: 0x50 */ + __IO uint32_t CCIPR3; /*!< RCC APB2 peripherals kernel clock configuration register Address offset: 0x54 */ + __IO uint32_t CCIPR4; /*!< RCC APB4/APB5 peripherals kernel clock configuration register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x68 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB5RSTR; /*!< RCC AHB5 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB5RSTR; /*!< RCC APB5 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x90 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0xA0 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0xA4 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0xA8-0xAC */ + __IO uint32_t CKGDISR ; /*!< RCC AXI clocks gating disable register, Address offset: 0xB0 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0xB4-0xBC */ + __IO uint32_t PLL1DIVR2; /*!< RCC PLL1 dividers configuration register 2, Address offset: 0xC0 */ + __IO uint32_t PLL2DIVR2; /*!< RCC PLL2 dividers configuration register 2, Address offset: 0xC4 */ + __IO uint32_t PLL3DIVR2; /*!< RCC PLL3 dividers configuration register 2, Address offset: 0xC8 */ + __IO uint32_t PLL1SSCGR; /*!< RCC PLL1 spread spectrum clock generator register, Address offset: 0xCC */ + __IO uint32_t PLL2SSCGR; /*!< RCC PLL2 spread spectrum clock generator register, Address offset: 0xD0 */ + __IO uint32_t PLL3SSCGR; /*!< RCC PLL3 spread spectrum clock generator register, Address offset: 0xD4 */ + uint32_t RESERVED9[10]; /*!< Reserved, Address offset: 0xD8-0xFC */ + __IO uint32_t CKPROTR; /*!< RCC clock protection register, Address offset: 0x100 */ + uint32_t RESERVED10[11]; /*!< Reserved, Address offset: 0x104-0x12C */ + __IO uint32_t RSR; /*!< RCC reset status register, Address offset: 0x130 */ + __IO uint32_t AHB5ENR; /*!< RCC AHB5 peripheral clocks enable register, Address offset: 0x134 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x138 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x13C */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clocks enable register, Address offset: 0x140 */ + __IO uint32_t APB5ENR; /*!< RCC APB5 peripheral clocks enable register, Address offset: 0x144 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x148 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x14C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x150 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clocks enable register, Address offset: 0x154 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x158 */ + __IO uint32_t AHB5LPENR; /*!< RCC AHB5 peripheral sleep clocks enable register, Address offset: 0x15C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clocks enable register, Address offset: 0x160 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clocks enable register, Address offset: 0x164 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clocks enable register, Address offset: 0x168 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clocks enable register, Address offset: 0x16C */ + __IO uint32_t APB1LPENR1; /*!< RCC APB1 peripheral sleep clocks enable register 1, Address offset: 0x170 */ + __IO uint32_t APB1LPENR2; /*!< RCC APB1 peripheral sleep clocks enable register 2, Address offset: 0x174 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clocks enable register, Address offset: 0x178 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clocks enable register, Address offset: 0x17C */ + __IO uint32_t APB5LPENR; /*!< RCC APB5 peripheral sleep clocks enable register, Address offset: 0x180 */ +} RCC_TypeDef; + +/** + * @brief Random Number Generator + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief SAES Processor + */ +typedef struct +{ + __IO uint32_t CR; /*!< SAES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< SAES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< SAES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< SAES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< SAES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< SAES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< SAES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< SAES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< SAES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< SAES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< SAES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< SAES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< SAES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< SAES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< SAES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< SAES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< SAES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< SAES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< SAES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< SAES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< SAES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< SAES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< SAES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< SAES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168]; /*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< SAES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< SAES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< SAES Interrupt Clear Register, Address offset: 0x308 */ +} SAES_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration, boot and security controller + */ +typedef struct +{ + __IO uint32_t BOOTSR; /*!< SBS Boot Status register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04-0x0C */ + __IO uint32_t HDPLCR; /*!< SBS Hide Protection Control register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS Hide Protection Status register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x28-0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command register, Address offset: 0x34 */ + uint32_t RESERVED4[50]; /*!< Reserved, Address offset: 0x38-0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status register, Address offset: 0x108 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS IO Compensation Cell Control and Status register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS IO Compensation Cell Value register, Address offset: 0x114 */ + __IO uint32_t CCSWVALR; /*!< SBS IO Compensation Cell Software Value register, Address offset: 0x118 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x11C */ + __IO uint32_t BKLOCKR; /*!< SBS Break Lockup register, Address offset: 0x120 */ + uint32_t RESERVED7[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t EXTICR[4]; /*!< SBS External Interrupt Configuration registers, Address offset: 0x130-0x13C */ +} SBS_TypeDef; + +/** + * @brief Secure Digital Card/IO Embedded MultiMediaCard Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC Power control register, Address offset : 0x000 */ + __IO uint32_t CLKCR; /*!< SDMMC Clock control register, Address offset : 0x004 */ + __IO uint32_t ARG; /*!< SDMMC Argument register, Address offset : 0x008 */ + __IO uint32_t CMD; /*!< SDMMC Command register, Address offset : 0x00C */ + __IO uint32_t RESPCMD; /*!< SDMMC Command response register, Address offset : 0x010 */ + __IO uint32_t RESP1; /*!< SDMMC Response 1 register, Address offset : 0x014 */ + __IO uint32_t RESP2; /*!< SDMMC Response 2 register, Address offset : 0x018 */ + __IO uint32_t RESP3; /*!< SDMMC Response 3 register, Address offset : 0x01C */ + __IO uint32_t RESP4; /*!< SDMMC Response 4 register, Address offset : 0x020 */ + __IO uint32_t DTIMER; /*!< SDMMC Data timer register, Address offset : 0x024 */ + __IO uint32_t DLEN; /*!< SDMMC Data length register, Address offset : 0x028 */ + __IO uint32_t DCTRL; /*!< SDMMC Data control register, Address offset : 0x02C */ + __IO uint32_t DCOUNT; /*!< SDMMC Data counter register, Address offset : 0x030 */ + __IO uint32_t STA; /*!< SDMMC Status register, Address offset : 0x034 */ + __IO uint32_t ICR; /*!< SDMMC Interrupt clear register, Address offset : 0x038 */ + __IO uint32_t MASK; /*!< SDMMC Mask register, Address offset : 0x03C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset : 0x040 */ + uint32_t RESERVED0[3]; /*!< Reserved, Address offset : 0x044 - 0x04C */ + __IO uint32_t IDMACTRL; /*!< SDMMC IDMA control register, Address offset : 0x050 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC IDMA buffer size register, Address offset : 0x054 */ + __IO uint32_t IDMABASER; /*!< SDMMC IDMA buffer base address register, Address offset : 0x058 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset : 0x05C - 0x060 */ + __IO uint32_t IDMALAR; /*!< SDMMC IDMA linked list address register, Address offset : 0x064 */ + __IO uint32_t IDMABAR; /*!< SDMMC IDMA linked list memory base register, Address offset : 0x068 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset : 0x06C - 0x07C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset : 0x080 */ +} SDMMC_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t CFGR; /*!< TAMP configuration control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter 1 register, Address offset: 0x40 */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED5[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + uint32_t RESERVED0[221]; /*!< Reserved, Address offset: 0x68 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Window Watchdog + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32H7RSxx_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup STM32H7RSxx_Peripheral_peripheralAddr + * @{ + */ +#define ITCM_BASE 0x00000000UL /*!< ITCM base address */ +#define FLASH_BASE 0x08000000UL /*!< User Flash address */ +#define OTP_AREA_BASE 0x08FFF000UL /*!< OTP Area base address */ +#define ENGI_BYTES_BASE 0x52002800UL /*!< Engi Bytes */ +#define SYSTEM_FLASH_BASE 0x1FF00000UL /*!< System Flash base address */ +#define DTCM_BASE 0x20000000UL /*!< DTCM base address */ +#define SRAM1_AXI_BASE 0x24000000UL /*!< SRAM1 base address - accessible over AXI */ +#define SRAM2_AXI_BASE 0x24020000UL /*!< SRAM2 base address - accessible over AXI */ +#define SRAM3_AXI_BASE 0x24040000UL /*!< SRAM3 base address - accessible over AXI */ +#define SRAM4_AXI_BASE 0x24060000UL /*!< SRAM4 base address - accessible over AXI */ + +#define GFXMMU_VIRTUAL_BUFFER0_BASE 0x25000000UL /*!< GFXMMU virtual buffer 0 base address */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE 0x25400000UL /*!< GFXMMU virtual buffer 1 base address */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE 0x25800000UL /*!< GFXMMU virtual buffer 2 base address */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE 0x25C00000UL /*!< GFXMMU virtual buffer 3 base address */ + +#define SRAM1_AHB_BASE 0x30000000UL /*!< SRAM1 base address */ +#define SRAM2_AHB_BASE 0x30004000UL /*!< SRAM2 base address */ +#define BKPSRAM_BASE 0x38800000UL /*!< Backup SRAM */ + +#define PERIPH_BASE 0x40000000UL /*!< AHB and APB Peripherals base address */ +#define XSPI2_BASE 0x70000000UL /*!< XSPI2 base address */ +#define XSPI1_BASE 0x90000000UL /*!< XSPI1 base address */ + +/*!< Internal memory size */ +#define ITCM_SIZE 0x00010000UL /*!< 64 KB default, can be increased up to 192 KB */ +#define DTCM_SIZE 0x00010000UL /*!< 64 KB default, can be increased up to 192 KB */ +#define FLASH_SIZE 0x00010000UL /*!< 64 KB */ +#define SRAM1_AXI_SIZE 0x00020000UL /*!< 128 KB default, can be decreased down to 0 KB to increase ITCM */ +#define SRAM2_AXI_SIZE 0x00020000UL /*!< 128 KB */ +#define SRAM3_AXI_SIZE 0x00020000UL /*!< 128 KB default, can be decreased down to 0 KB to increase DTCM */ +#define SRAM4_AXI_SIZE 0x00012000UL /*!< 72 KB default, can be decreased to 0 KB when RAM ECC is disable */ +#define SRAM_AHB_SIZE 0x00004000UL /*!< Both AHB SRAMs are 16 KB */ +#define BKPSRAM_SIZE 0x00001000UL /*!< 4 KB */ + +/*!< OTP Area size */ +#define OTP_SIZE 0x400U /* 1 KB */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x02000000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x08020000UL) +#define APB5PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define AHB5PERIPH_BASE (PERIPH_BASE + 0x12000000UL) +#define APB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define AHB4PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I3C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x8400UL) +#define MDIOS_BASE (APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0xA100UL) /*!< FDCAN configuration registers base address */ +#define FDCAN2_BASE (APB1PERIPH_BASE + 0xA400UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xAC00UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xEC00UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00UL) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define GPDMA1_Channel0_BASE (GPDMA1_BASE + 0x0050UL) +#define GPDMA1_Channel1_BASE (GPDMA1_BASE + 0x00D0UL) +#define GPDMA1_Channel2_BASE (GPDMA1_BASE + 0x0150UL) +#define GPDMA1_Channel3_BASE (GPDMA1_BASE + 0x01D0UL) +#define GPDMA1_Channel4_BASE (GPDMA1_BASE + 0x0250UL) +#define GPDMA1_Channel5_BASE (GPDMA1_BASE + 0x02D0UL) +#define GPDMA1_Channel6_BASE (GPDMA1_BASE + 0x0350UL) +#define GPDMA1_Channel7_BASE (GPDMA1_BASE + 0x03D0UL) +#define GPDMA1_Channel8_BASE (GPDMA1_BASE + 0x0450UL) +#define GPDMA1_Channel9_BASE (GPDMA1_BASE + 0x04D0UL) +#define GPDMA1_Channel10_BASE (GPDMA1_BASE + 0x0550UL) +#define GPDMA1_Channel11_BASE (GPDMA1_BASE + 0x05D0UL) +#define GPDMA1_Channel12_BASE (GPDMA1_BASE + 0x0650UL) +#define GPDMA1_Channel13_BASE (GPDMA1_BASE + 0x06D0UL) +#define GPDMA1_Channel14_BASE (GPDMA1_BASE + 0x0750UL) +#define GPDMA1_Channel15_BASE (GPDMA1_BASE + 0x07D0UL) +#define ADC1_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) +#define ADF1_BASE (AHB1PERIPH_BASE + 0xF000UL) +#define ADF1_Filter0_BASE (ADF1_BASE + 0x0080UL) +#define USB_OTG_HS_PERIPH_BASE (AHB1PERIPH_BASE + 0x20000UL) +#define USB_OTG_FS_PERIPH_BASE (AHB1PERIPH_BASE + 0x60000UL) + +/*!< AHB2 peripherals */ +#define PSSI_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define SDMMC2_BASE (AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (AHB2PERIPH_BASE + 0x2800UL) +#define CORDIC_BASE (AHB2PERIPH_BASE + 0x4400UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE AHB3PERIPH_BASE +#define HASH_BASE (AHB3PERIPH_BASE + 0x0400UL) +#define HASH_DIGEST_BASE (AHB3PERIPH_BASE + 0x0710UL) +#define CRYP_BASE (AHB3PERIPH_BASE + 0x0800UL) +#define SAES_BASE (AHB3PERIPH_BASE + 0x1000UL) +#define PKA_BASE (AHB3PERIPH_BASE + 0x2000UL) + +/*!< APB5 peripherals */ +#define LTDC_BASE (APB5PERIPH_BASE + 0x1000UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x0084UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x0104UL) +#define DCMIPP_BASE (APB5PERIPH_BASE + 0x2000UL) +#define GFXTIM_BASE (APB5PERIPH_BASE + 0x4000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE AHB5PERIPH_BASE +#define HPDMA1_Channel0_BASE (HPDMA1_BASE + 0x0050UL) +#define HPDMA1_Channel1_BASE (HPDMA1_BASE + 0x00D0UL) +#define HPDMA1_Channel2_BASE (HPDMA1_BASE + 0x0150UL) +#define HPDMA1_Channel3_BASE (HPDMA1_BASE + 0x01D0UL) +#define HPDMA1_Channel4_BASE (HPDMA1_BASE + 0x0250UL) +#define HPDMA1_Channel5_BASE (HPDMA1_BASE + 0x02D0UL) +#define HPDMA1_Channel6_BASE (HPDMA1_BASE + 0x0350UL) +#define HPDMA1_Channel7_BASE (HPDMA1_BASE + 0x03D0UL) +#define HPDMA1_Channel8_BASE (HPDMA1_BASE + 0x0450UL) +#define HPDMA1_Channel9_BASE (HPDMA1_BASE + 0x04D0UL) +#define HPDMA1_Channel10_BASE (HPDMA1_BASE + 0x0550UL) +#define HPDMA1_Channel11_BASE (HPDMA1_BASE + 0x05D0UL) +#define HPDMA1_Channel12_BASE (HPDMA1_BASE + 0x0650UL) +#define HPDMA1_Channel13_BASE (HPDMA1_BASE + 0x06D0UL) +#define HPDMA1_Channel14_BASE (HPDMA1_BASE + 0x0750UL) +#define HPDMA1_Channel15_BASE (HPDMA1_BASE + 0x07D0UL) +#define DMA2D_BASE (AHB5PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB5PERIPH_BASE + 0x2000UL) +#define JPEG_BASE (AHB5PERIPH_BASE + 0x3000UL) +#define FMC_R_BASE (AHB5PERIPH_BASE + 0x4000UL) +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) +#define XSPI1_R_BASE (AHB5PERIPH_BASE + 0x5000UL) +#define SDMMC1_BASE (AHB5PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (AHB5PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (AHB5PERIPH_BASE + 0x9000UL) +#define RAMECC1_Monitor0_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0xA0UL) +#define XSPI2_R_BASE (AHB5PERIPH_BASE + 0xA000UL) +#define XSPIM_BASE (AHB5PERIPH_BASE + 0xB400UL) +#define MCE1_BASE (AHB5PERIPH_BASE + 0xB800UL) +#define MCE1_REGION1_BASE (MCE1_BASE + 0x040UL) +#define MCE1_REGION2_BASE (MCE1_BASE + 0x050UL) +#define MCE1_REGION3_BASE (MCE1_BASE + 0x060UL) +#define MCE1_REGION4_BASE (MCE1_BASE + 0x070UL) +#define MCE1_CONTEXT1_BASE (MCE1_BASE + 0x240UL) +#define MCE1_CONTEXT2_BASE (MCE1_BASE + 0x270UL) +#define MCE2_BASE (AHB5PERIPH_BASE + 0xBC00UL) +#define MCE2_REGION1_BASE (MCE2_BASE + 0x040UL) +#define MCE2_REGION2_BASE (MCE2_BASE + 0x050UL) +#define MCE2_REGION3_BASE (MCE2_BASE + 0x060UL) +#define MCE2_REGION4_BASE (MCE2_BASE + 0x070UL) +#define MCE3_BASE (AHB5PERIPH_BASE + 0xC000UL) +#define MCE3_REGION1_BASE (MCE3_BASE + 0x040UL) +#define MCE3_REGION2_BASE (MCE3_BASE + 0x050UL) +#define MCE3_REGION3_BASE (MCE3_BASE + 0x060UL) +#define MCE3_REGION4_BASE (MCE3_BASE + 0x070UL) +#define GFXMMU_BASE (AHB5PERIPH_BASE + 0x010000UL) +#define GPU2D_BASE (AHB5PERIPH_BASE + 0x014000UL) +#define ICACHE_BASE (AHB5PERIPH_BASE + 0x015000UL) + +/*!< APB4 peripherals */ +#define EXTI_BASE APB4PERIPH_BASE +#define SBS_BASE (APB4PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (APB4PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (APB4PERIPH_BASE + 0x1400UL) +#define LPTIM2_BASE (APB4PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (APB4PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (APB4PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (APB4PERIPH_BASE + 0x3000UL) +#define VREFBUF_BASE (APB4PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (APB4PERIPH_BASE + 0x4000UL) +#define TAMP_BASE (APB4PERIPH_BASE + 0x4400UL) +#define IWDG_BASE (APB4PERIPH_BASE + 0x4800UL) +#define DTS_BASE (APB4PERIPH_BASE + 0x6800UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE AHB4PERIPH_BASE +#define GPIOB_BASE (AHB4PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB4PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB4PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB4PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB4PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB4PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB4PERIPH_BASE + 0x1C00UL) +#define GPIOM_BASE (AHB4PERIPH_BASE + 0x3000UL) +#define GPION_BASE (AHB4PERIPH_BASE + 0x3400UL) +#define GPIOO_BASE (AHB4PERIPH_BASE + 0x3800UL) +#define GPIOP_BASE (AHB4PERIPH_BASE + 0x3C00UL) +#define RCC_BASE (AHB4PERIPH_BASE + 0x4400UL) +#define PWR_BASE (AHB4PERIPH_BASE + 0x4800UL) +#define CRC_BASE (AHB4PERIPH_BASE + 0x4C00UL) +#define RAMECC2_BASE (AHB4PERIPH_BASE + 0x7000UL) +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x40UL) + +/*!< Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +/*!< AXIM registers base address */ +#define AXIM_BASE (0xBFF00000UL) +#define AXIM_ASIB1_BASE (AXIM_BASE + 0x42000UL) +#define AXIM_ASIB2_BASE (AXIM_BASE + 0x43000UL) +#define AXIM_ASIB3_BASE (AXIM_BASE + 0x44000UL) +#define AXIM_ASIB4_BASE (AXIM_BASE + 0x45000UL) +#define AXIM_ASIB5_BASE (AXIM_BASE + 0x46000UL) +#define AXIM_ASIB6_BASE (AXIM_BASE + 0x47000UL) +#define AXIM_ASIB7_BASE (AXIM_BASE + 0x48000UL) +#define AXIM_ASIB8_BASE (AXIM_BASE + 0x49000UL) +#define AXIM_ASIB9_BASE (AXIM_BASE + 0x4A000UL) +#define AXIM_ASIB10_BASE (AXIM_BASE + 0x4B000UL) +#define AXIM_ASIB11_BASE (AXIM_BASE + 0x4C000UL) +#define AXIM_AMIB1_BASE (AXIM_BASE + 0x02000UL) +#define AXIM_AMIB2_BASE (AXIM_BASE + 0x03000UL) +#define AXIM_AMIB3_BASE (AXIM_BASE + 0x04000UL) +#define AXIM_AMIB4_BASE (AXIM_BASE + 0x05000UL) +#define AXIM_AMIB5_BASE (AXIM_BASE + 0x06000UL) +#define AXIM_AMIB6_BASE (AXIM_BASE + 0x07000UL) +#define AXIM_AMIB7_BASE (AXIM_BASE + 0x08000UL) +#define AXIM_AMIB8_BASE (AXIM_BASE + 0x09000UL) +#define AXIM_AMIB9_BASE (AXIM_BASE + 0x0A000UL) +#define AXIM_AMIB10_BASE (AXIM_BASE + 0x0B000UL) + +/*!< Unique device ID register base address */ +#define UID_BASE (0x08FFF800UL) + +/*!< Flash size data register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) + +/*!< Package data register base address */ +#define PACKAGE_BASE (0x08FFF80CUL) + +/* USB OTG registers base addresses */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_PFUNC_START (0x1FF1FD4CUL) +#define RSSLIB_SYS_FLASH_PFUNC_END (0x1FF1FD78UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0x1FF1FD4CUL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t Destination; /*!< OBKeys destination information where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + +/** + * @brief Prototype of RSSLIB Set Secure OB Function + * @detail This function configure a secure OB. + * @param OB address among following values: + * &(FLASH->WRPSRP), &(FLASH->HDPSRP) or &(FLASH->ROTSRP) + * @param OB mask (example 0x000000FF for updating WRP OB). + * @param OB value + * @param OB Pos: bit position of OB value. + * ObValue << ObPos must be aligned on ObMask. + * @retval RSSLIB_RSS_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_SetSecOB_TypeDef)(uint32_t ObAddr, uint32_t ObMask, uint32_t ObValue, uint32_t ObPos); + +/** + * @brief Prototype of RSSLIB Get RSS Status Function + * @detail This function return RSS Status. + * Calling GetRssStatus is only relevant after calling + * SetSecOB or DataProvisioning. + * @param none. + * @retval RSSLIB_SUCCESS on success, otherwise return an error 0xF5F5xxxx. + */ +typedef uint32_t (*RSSLIB_GetRssStatus_TypeDef)(void); + +/** + * @brief Prototype of RSSLIB Set Product State Function + * @detail This function change Product State. + * @param Requested Product State among following values: + * 0x17 : Provisioning + * 0x72 : Closed + * 0x5C : Locked + * @retval RSSLIB_RSS_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_SetProductState_TypeDef)(uint32_t ProductState); + +/** + * @brief Prototype of RSSLIB Get Product State Function + * @detail This function return current Product State. + * @param none. + * @retval RSSLIB_RSS_ERROR on error, + * otherwise return product state among following values: + * 0x39 : Open + * 0x17 : Provisioning + * 0x72 : Closed + * 0x5C : Locked + */ +typedef uint32_t (*RSSLIB_GetProductState_TypeDef)(void); + + +/** + * @brief RSSLib callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_SetSecOB_TypeDef SetSecOB; + uint32_t RESERVED1[4]; + __IM RSSLIB_GetRssStatus_TypeDef GetRssStatus; + __IM RSSLIB_SetProductState_TypeDef SetProductState; + __IM RSSLIB_DataProvisioning_TypeDef DataProvisioning; + __IM RSSLIB_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_GetProductState_TypeDef GetProductState; +} RSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32H7RSxx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H7RSxx_Peripheral_declaration + * @{ + */ + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADF1 ((MDF_TypeDef *) ADF1_BASE) +#define ADF1_Filter0 ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE) +#define AXIM_AMIB_1 ((AXIM_AMIB_TypeDef *) AXIM_AMIB1_BASE ) +#define AXIM_AMIB_2 ((AXIM_AMIB_TypeDef *) AXIM_AMIB2_BASE ) +#define AXIM_AMIB_3 ((AXIM_AMIB_TypeDef *) AXIM_AMIB3_BASE ) +#define AXIM_AMIB_4 ((AXIM_AMIB_TypeDef *) AXIM_AMIB4_BASE ) +#define AXIM_AMIB_5 ((AXIM_AMIB_TypeDef *) AXIM_AMIB5_BASE ) +#define AXIM_AMIB_6 ((AXIM_AMIB_TypeDef *) AXIM_AMIB6_BASE ) +#define AXIM_AMIB_7 ((AXIM_AMIB_TypeDef *) AXIM_AMIB7_BASE ) +#define AXIM_AMIB_8 ((AXIM_AMIB_TypeDef *) AXIM_AMIB8_BASE ) +#define AXIM_AMIB_9 ((AXIM_AMIB_TypeDef *) AXIM_AMIB9_BASE ) +#define AXIM_AMIB_10 ((AXIM_AMIB_TypeDef *) AXIM_AMIB10_BASE) +#define AXIM_ASIB_1 ((AXIM_ASIB_TypeDef *) AXIM_ASIB1_BASE ) +#define AXIM_ASIB_2 ((AXIM_ASIB_TypeDef *) AXIM_ASIB2_BASE ) +#define AXIM_ASIB_3 ((AXIM_ASIB_TypeDef *) AXIM_ASIB3_BASE ) +#define AXIM_ASIB_4 ((AXIM_ASIB_TypeDef *) AXIM_ASIB4_BASE ) +#define AXIM_ASIB_5 ((AXIM_ASIB_TypeDef *) AXIM_ASIB5_BASE ) +#define AXIM_ASIB_6 ((AXIM_ASIB_TypeDef *) AXIM_ASIB6_BASE ) +#define AXIM_ASIB_7 ((AXIM_ASIB_TypeDef *) AXIM_ASIB7_BASE ) +#define AXIM_ASIB_8 ((AXIM_ASIB_TypeDef *) AXIM_ASIB8_BASE ) +#define AXIM_ASIB_9 ((AXIM_ASIB_TypeDef *) AXIM_ASIB9_BASE ) +#define AXIM_ASIB_10 ((AXIM_ASIB_TypeDef *) AXIM_ASIB10_BASE) +#define AXIM_ASIB_11 ((AXIM_ASIB_TypeDef *) AXIM_ASIB11_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define DCMIPP ((DCMIPP_TypeDef *) DCMIPP_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DTS ((DTS_TypeDef *) DTS_BASE) +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define GFXTIM ((GFXTIM_TypeDef *) GFXTIM_BASE) +#define GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE) +#define GPU2D GPU2D_BASE +#define GPDMA1 ((DMA_TypeDef *) GPDMA1_BASE) +#define GPDMA1_Channel0 ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE) +#define GPDMA1_Channel1 ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE) +#define GPDMA1_Channel2 ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE) +#define GPDMA1_Channel3 ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE) +#define GPDMA1_Channel4 ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE) +#define GPDMA1_Channel5 ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE) +#define GPDMA1_Channel6 ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE) +#define GPDMA1_Channel7 ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE) +#define GPDMA1_Channel8 ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE) +#define GPDMA1_Channel9 ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE) +#define GPDMA1_Channel10 ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE) +#define GPDMA1_Channel11 ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE) +#define GPDMA1_Channel12 ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE) +#define GPDMA1_Channel13 ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE) +#define GPDMA1_Channel14 ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE) +#define GPDMA1_Channel15 ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOM ((GPIO_TypeDef *) GPIOM_BASE) +#define GPION ((GPIO_TypeDef *) GPION_BASE) +#define GPIOO ((GPIO_TypeDef *) GPIOO_BASE) +#define GPIOP ((GPIO_TypeDef *) GPIOP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define HPDMA1 ((DMA_TypeDef *) HPDMA1_BASE) +#define HPDMA1_Channel0 ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE) +#define HPDMA1_Channel1 ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE) +#define HPDMA1_Channel2 ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE) +#define HPDMA1_Channel3 ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE) +#define HPDMA1_Channel4 ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE) +#define HPDMA1_Channel5 ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE) +#define HPDMA1_Channel6 ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE) +#define HPDMA1_Channel7 ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE) +#define HPDMA1_Channel8 ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE) +#define HPDMA1_Channel9 ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE) +#define HPDMA1_Channel10 ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE) +#define HPDMA1_Channel11 ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE) +#define HPDMA1_Channel12 ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE) +#define HPDMA1_Channel13 ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE) +#define HPDMA1_Channel14 ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE) +#define HPDMA1_Channel15 ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE) +#define ICACHE ((ICACHE_TypeDef *) ICACHE_BASE) +#define JPEG ((JPEG_TypeDef *) JPEG_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I3C1 ((I3C_TypeDef *) I3C1_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) +#define MCE1 ((MCE_TypeDef *) MCE1_BASE) +#define MCE1_REGION1 ((MCE_Region_TypeDef *) MCE1_REGION1_BASE) +#define MCE1_REGION2 ((MCE_Region_TypeDef *) MCE1_REGION2_BASE) +#define MCE1_REGION3 ((MCE_Region_TypeDef *) MCE1_REGION3_BASE) +#define MCE1_REGION4 ((MCE_Region_TypeDef *) MCE1_REGION4_BASE) +#define MCE1_CONTEXT1 ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE) +#define MCE1_CONTEXT2 ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE) +#define MCE2 ((MCE_TypeDef *) MCE2_BASE) +#define MCE2_REGION1 ((MCE_Region_TypeDef *) MCE2_REGION1_BASE) +#define MCE2_REGION2 ((MCE_Region_TypeDef *) MCE2_REGION2_BASE) +#define MCE2_REGION3 ((MCE_Region_TypeDef *) MCE2_REGION3_BASE) +#define MCE2_REGION4 ((MCE_Region_TypeDef *) MCE2_REGION4_BASE) +#define MCE3 ((MCE_TypeDef *) MCE3_BASE) +#define MCE3_REGION1 ((MCE_Region_TypeDef *) MCE3_REGION1_BASE) +#define MCE3_REGION2 ((MCE_Region_TypeDef *) MCE3_REGION2_BASE) +#define MCE3_REGION3 ((MCE_Region_TypeDef *) MCE3_REGION3_BASE) +#define MCE3_REGION4 ((MCE_Region_TypeDef *) MCE3_REGION4_BASE) +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) +#define PKA ((PKA_TypeDef *) PKA_BASE) +#define PSSI ((PSSI_TypeDef *) PSSI_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC1_Monitor0 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor0_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SAES ((SAES_TypeDef *) SAES_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *) SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *) SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *) SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *) SAI2_Block_B_BASE) +#define SBS ((SBS_TypeDef *) SBS_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define XSPI1 ((XSPI_TypeDef *) XSPI1_R_BASE) +#define XSPI2 ((XSPI_TypeDef *) XSPI2_R_BASE) +#define XSPIM ((XSPIM_TypeDef *) XSPIM_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) + +/** @} */ /* End of group STM32H7RSxx_Peripheral_declaration */ + +/** @addtogroup STM32H7RSxx_Peripheral_Exported_constants + * @{ + */ + +/** @addtogroup STM32H7RSxx_Peripheral_Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_Peripheral_Registers_Bits_Definition + * @{ + */ +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_ADFCFG_Pos (2U) +#define ADC_CFGR_ADFCFG_Msk (0x1UL << ADC_CFGR_ADFCFG_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_ADFCFG ADC_CFGR_ADFCFG_Msk /*!< ADC ADF transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register ***************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x1UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC internal path to VDDCORE */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ + +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************************************************************************/ +/* */ +/* AXIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AXIM_ASIB_FNMOD2 register **********/ +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE_Pos (0U) +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE_Msk (0x1UL << AXIM_ASIB_FNMOD2_BYPASS_MERGE_Pos) /*!< 0x00000001 */ +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE AXIM_ASIB_FNMOD2_BYPASS_MERGE_Msk /*!< Bypass Merge enable */ + +/******************* Bit definition for AXIM_ASIB_READQOS register ********/ +#define AXIM_ASIB_READQOS_AR_QOS_Pos (0U) +#define AXIM_ASIB_READQOS_AR_QOS_Msk (0xFUL << AXIM_ASIB_READQOS_AR_QOS_Pos) /*!< 0x0000000F */ +#define AXIM_ASIB_READQOS_AR_QOS AXIM_ASIB_READQOS_AR_QOS_Msk /*!< Read channel QoS setting */ + +/******************* Bit definition for AXIM_ASIB_WRITEQOS register *******/ +#define AXIM_ASIB_WRITEQOS_AW_QOS_Pos (0U) +#define AXIM_ASIB_WRITEQOS_AW_QOS_Msk (0xFUL << AXIM_ASIB_WRITEQOS_AW_QOS_Pos) /*!< 0x0000000F */ +#define AXIM_ASIB_WRITEQOS_AW_QOS AXIM_ASIB_WRITEQOS_AW_QOS_Msk /*!< Write channel QoS setting */ + +/******************* Bit definition for AXIM_ASIB_FNMOD register **********/ +#define AXIM_ASIB_FNMOD_READ_ISS_Pos (0U) +#define AXIM_ASIB_FNMOD_READ_ISS_Msk (0x1UL << AXIM_ASIB_FNMOD_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_ASIB_FNMOD_READ_ISS AXIM_ASIB_FNMOD_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_ASIB_FNMOD_WRITE_ISS_Pos (1U) +#define AXIM_ASIB_FNMOD_WRITE_ISS_Msk (0x1UL << AXIM_ASIB_FNMOD_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_ASIB_FNMOD_WRITE_ISS AXIM_ASIB_FNMOD_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************* Bit definition for AXIM_AMIB_FNMODBMISS register **********/ +#define AXIM_AMIB_FNMODBMISS_READ_ISS_Pos (0U) +#define AXIM_AMIB_FNMODBMISS_READ_ISS_Msk (0x1UL << AXIM_AMIB_FNMODBMISS_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMODBMISS_READ_ISS AXIM_AMIB_FNMODBMISS_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS_Pos (1U) +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS_Msk (0x1UL << AXIM_AMIB_FNMODBMISS_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS AXIM_AMIB_FNMODBMISS_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************* Bit definition for AXIM_AMIB_FNMOD2 register **********/ +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE_Pos (0U) +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE_Msk (0x1UL << AXIM_AMIB_FNMOD2_BYPASS_MERGE_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE AXIM_AMIB_FNMOD2_BYPASS_MERGE_Msk /*!< Bypass Merge enable */ + +/******************* Bit definition for AXIM_AMIB_FNMODLB register **********/ +#define AXIM_AMIB_FNMODLB_LONG_BURST_Pos (0U) +#define AXIM_AMIB_FNMODLB_LONG_BURST_Msk (0x1UL << AXIM_AMIB_FNMODLB_LONG_BURST_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMODLB_LONG_BURST AXIM_AMIB_FNMODLB_LONG_BURST_Msk /*!< Long bursts can be generated */ + +/******************* Bit definition for AXIM_AMIB_FNMOD register **********/ +#define AXIM_AMIB_FNMOD_READ_ISS_Pos (0U) +#define AXIM_AMIB_FNMOD_READ_ISS_Msk (0x1UL << AXIM_AMIB_FNMOD_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMOD_READ_ISS AXIM_AMIB_FNMOD_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_AMIB_FNMOD_WRITE_ISS_Pos (1U) +#define AXIM_AMIB_FNMOD_WRITE_ISS_Msk (0x1UL << AXIM_AMIB_FNMOD_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_AMIB_FNMOD_WRITE_ISS AXIM_AMIB_FNMOD_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* Parallel Synchronous Slave Interface (PSSI ) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PSSI_CR register *******************/ +#define PSSI_CR_CKPOL_Pos (5U) +#define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) /*!< 0x00000020 */ +#define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk /*!< Parallel data clock polarity */ +#define PSSI_CR_DEPOL_Pos (6U) +#define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) /*!< 0x00000040 */ +#define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk /*!< Data enable polarity */ +#define PSSI_CR_RDYPOL_Pos (8U) +#define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) /*!< 0x00000100 */ +#define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk /*!< Ready polarity */ +#define PSSI_CR_EDM_Pos (10U) +#define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define PSSI_CR_EDM PSSI_CR_EDM_Msk /*!< Extended data mode */ +#define PSSI_CR_ENABLE_Pos (14U) +#define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk /*!< PSSI enable */ +#define PSSI_CR_DERDYCFG_Pos (18U) +#define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< 0x001C0000 */ +#define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk /*!< Data enable and ready configuration */ +#define PSSI_CR_CKSRC_Pos (29U) +#define PSSI_CR_CKSRC_Msk (0x1UL << PSSI_CR_CKSRC_Pos) /*!< 0x20000000 */ +#define PSSI_CR_CKSRC PSSI_CR_CKSRC_Msk /*!< Clock source */ +#define PSSI_CR_DMAEN_Pos (30U) +#define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) /*!< 0x40000000 */ +#define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk /*!< DMA enable */ +#define PSSI_CR_OUTEN_Pos (31U) +#define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) /*!< 0x80000000 */ +#define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk /*!< Data direction selection */ + +/******************** Bit definition for PSSI_SR register *******************/ +#define PSSI_SR_RTT4B_Pos (2U) +#define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) /*!< 0x00000004 */ +#define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk /*!< Ready to transfer four bytes */ +#define PSSI_SR_RTT1B_Pos (3U) +#define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) /*!< 0x00000008 */ +#define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk /*!< Ready to transfer one byte */ + +/******************** Bit definition for PSSI_RIS register ******************/ +#define PSSI_RIS_OVR_RIS_Pos (1U) +#define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk /*!< Data buffer overrun/underrun raw interrupt status */ + +/******************** Bit definition for PSSI_IER register ******************/ +#define PSSI_IER_OVR_IE_Pos (1U) +#define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk /*!< Data buffer overrun/underrun interrupt enable */ + +/******************** Bit definition for PSSI_MIS register ******************/ +#define PSSI_MIS_OVR_MIS_Pos (1U) +#define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk /*!< Data buffer overrun/underrun masked interrupt status */ + +/******************** Bit definition for PSSI_ICR register ******************/ +#define PSSI_ICR_OVR_ISC_Pos (1U) +#define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk /*!< Data buffer overrun/underrun interrupt status clear */ + +/******************** Bit definition for PSSI_DR register *******************/ +#define PSSI_DR_DR_Pos (0U) +#define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) /*!< 0xFFFFFFF */ +#define PSSI_DR_DR PSSI_DR_DR_Msk /*!< Data register */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CR1 register *******************/ +#define PWR_CR1_SVOS_Pos (0U) +#define PWR_CR1_SVOS_Msk (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00000001 */ +#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection. */ + +#define PWR_CR1_PVDE_Pos (4U) +#define PWR_CR1_PVDE_Msk (0x1UL << PWR_CR1_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR1_PVDE PWR_CR1_PVDE_Msk /*!< Programmable Voltage detector enable. */ + +#define PWR_CR1_PLS_Pos (5U) +#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */ +#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */ + +#define PWR_CR1_DBP_Pos (8U) +#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */ + +#define PWR_CR1_FLPS_Pos (9U) +#define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) /*!< 0x00000200 */ +#define PWR_CR1_FLPS PWR_CR1_FLPS_Msk /*!< Flash low power mode in STOP */ + +#define PWR_CR1_BOOSTE_Pos (11U) +#define PWR_CR1_BOOSTE_Msk (0x1UL << PWR_CR1_BOOSTE_Pos) /*!< 0x00000800 */ +#define PWR_CR1_BOOSTE PWR_CR1_BOOSTE_Msk /*!< Analog Switch VBoost control. */ + +#define PWR_CR1_AVDREADY_Pos (12) +#define PWR_CR1_AVDREADY_Msk (0x1UL << PWR_CR1_AVDREADY_Pos) /*!< 0x00001000 */ +#define PWR_CR1_AVDREADY PWR_CR1_AVDREADY_Msk /*!< Analog Voltage Ready. */ + +#define PWR_CR1_AVDEN_Pos (13U) +#define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) /*!< 0x00002000 */ +#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */ + +#define PWR_CR1_ALS_Pos (14U) +#define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x0000A000 */ +#define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */ +#define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) /*!< 0x00004000 */ +#define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for PWR_SR1 register ********************/ +#define PWR_SR1_ACTVOS_Pos (0U) +#define PWR_SR1_ACTVOS_Msk (0x1UL << PWR_SR1_ACTVOS_Pos) /*!< 0x00000001 */ +#define PWR_SR1_ACTVOS PWR_SR1_ACTVOS_Msk /*!< VOS currently applied for VCORE voltage scaling selection */ + +#define PWR_SR1_ACTVOSRDY_Pos (1U) +#define PWR_SR1_ACTVOSRDY_Msk (0x1UL << PWR_SR1_ACTVOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_SR1_ACTVOSRDY PWR_SR1_ACTVOSRDY_Msk /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling */ + +#define PWR_SR1_PVDO_Pos (4U) +#define PWR_SR1_PVDO_Msk (0x1UL << PWR_SR1_PVDO_Pos) /*!< 0x00000010 */ +#define PWR_SR1_PVDO PWR_SR1_PVDO_Msk /*!< Programmable Voltage Detect Output */ + +#define PWR_SR1_AVDO_Pos (13U) +#define PWR_SR1_AVDO_Msk (0x1UL << PWR_SR1_AVDO_Pos) /*!< 0x00002000 */ +#define PWR_SR1_AVDO PWR_SR1_AVDO_Msk /*!< Analog Voltage Detect Output on VDDA */ + +/******************** Bit definition for PWR_CSR1 register ********************/ +#define PWR_CSR1_BREN_Pos (0U) +#define PWR_CSR1_BREN_Msk (0x1UL << PWR_CSR1_BREN_Pos) /*!< 0x00000001 */ +#define PWR_CSR1_BREN PWR_CSR1_BREN_Msk /*!< Backup regulator enable */ + +#define PWR_CSR1_MONEN_Pos (4U) +#define PWR_CSR1_MONEN_Msk (0x1UL << PWR_CSR1_MONEN_Pos) /*!< 0x00000010 */ +#define PWR_CSR1_MONEN PWR_CSR1_MONEN_Msk /*!< VBAT and temperature monitoring enable */ + +#define PWR_CSR1_BRRDY_Pos (16U) +#define PWR_CSR1_BRRDY_Msk (0x1UL << PWR_CSR1_BRRDY_Pos) /*!< 0x00010000 */ +#define PWR_CSR1_BRRDY PWR_CSR1_BRRDY_Msk /*!< Backup regulator ready */ + +#define PWR_CSR1_VBATL_Pos (20U) +#define PWR_CSR1_VBATL_Msk (0x1UL << PWR_CSR1_VBATL_Pos) /*!< 0x00100000 */ +#define PWR_CSR1_VBATL PWR_CSR1_VBATL_Msk /*!< Monitored VBAT level above low threshold */ + +#define PWR_CSR1_VBATH_Pos (21U) +#define PWR_CSR1_VBATH_Msk (0x1UL << PWR_CSR1_VBATH_Pos) /*!< 0x00200000 */ +#define PWR_CSR1_VBATH PWR_CSR1_VBATH_Msk /*!< Monitored VBAT level above high threshold */ + +#define PWR_CSR1_TEMPL_Pos (22U) +#define PWR_CSR1_TEMPL_Msk (0x1UL << PWR_CSR1_TEMPL_Pos) /*!< 0x00400000 */ +#define PWR_CSR1_TEMPL PWR_CSR1_TEMPL_Msk /*!< Monitored temperature level above low threshold */ + +#define PWR_CSR1_TEMPH_Pos (23U) +#define PWR_CSR1_TEMPH_Msk (0x1UL << PWR_CSR1_TEMPH_Pos) /*!< 0x00800000 */ +#define PWR_CSR1_TEMPH PWR_CSR1_TEMPH_Msk /*!< Monitored temperature level above high threshold */ + +/******************** Bit definition for PWR_CSR2 register ********************/ +#define PWR_CSR2_BYPASS_Pos (0U) +#define PWR_CSR2_BYPASS_Msk (0x1UL << PWR_CSR2_BYPASS_Pos) /*!< 0x00000001 */ +#define PWR_CSR2_BYPASS PWR_CSR2_BYPASS_Msk /*!< Power Management Unit bypass */ + +#define PWR_CSR2_LDOEN_Pos (1U) +#define PWR_CSR2_LDOEN_Msk (0x1UL << PWR_CSR2_LDOEN_Pos) /*!< 0x00000002 */ +#define PWR_CSR2_LDOEN PWR_CSR2_LDOEN_Msk /*!< Low Drop-Out regulator enable */ + +#define PWR_CSR2_SDEN_Pos (2U) +#define PWR_CSR2_SDEN_Msk (0x1UL << PWR_CSR2_SDEN_Pos) /*!< 0x00000004 */ +#define PWR_CSR2_SDEN PWR_CSR2_SDEN_Msk /*!< SMPS Step-down converter enable */ + +#define PWR_CSR2_SMPSEXTHP_Pos (3U) +#define PWR_CSR2_SMPSEXTHP_Msk (0x1UL << PWR_CSR2_SMPSEXTHP_Pos) /*!< 0x00000008 */ +#define PWR_CSR2_SMPSEXTHP PWR_CSR2_SMPSEXTHP_Msk /*!< SMPS external power delivery selection */ + +#define PWR_CSR2_SDHILEVEL_Pos (4U) +#define PWR_CSR2_SDHILEVEL_Msk (0x1UL << PWR_CSR2_SDHILEVEL_Pos) /*!< 0x00000030 */ +#define PWR_CSR2_SDHILEVEL PWR_CSR2_SDHILEVEL_Msk /*!< SMPS step-down converter voltage output for LDO or external supply */ + +#define PWR_CSR2_VBE_Pos (8U) +#define PWR_CSR2_VBE_Msk (0x1UL << PWR_CSR2_VBE_Pos) /*!< 0x00000100 */ +#define PWR_CSR2_VBE PWR_CSR2_VBE_Msk /*!< VBAT charging enable */ + +#define PWR_CSR2_VBRS_Pos (9U) +#define PWR_CSR2_VBRS_Msk (0x1UL << PWR_CSR2_VBRS_Pos) /*!< 0x00000200 */ +#define PWR_CSR2_VBRS PWR_CSR2_VBRS_Msk /*!< VBAT charging resistor selection */ + +#define PWR_CSR2_XSPICAP1_Pos (10U) +#define PWR_CSR2_XSPICAP1_Msk (0x3UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000C00 */ +#define PWR_CSR2_XSPICAP1 PWR_CSR2_XSPICAP1_Msk /*!< XSPI port 1 capacitor control bits */ +#define PWR_CSR2_XSPICAP1_0 (0x1UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000400 */ +#define PWR_CSR2_XSPICAP1_1 (0x2UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000800 */ + +#define PWR_CSR2_XSPICAP2_Pos (12U) +#define PWR_CSR2_XSPICAP2_Msk (0x3UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00003000 */ +#define PWR_CSR2_XSPICAP2 PWR_CSR2_XSPICAP2_Msk /*!< XSPI port 2 capacitor control bits */ +#define PWR_CSR2_XSPICAP2_0 (0x1UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00001000 */ +#define PWR_CSR2_XSPICAP2_1 (0x2UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00002000 */ + +#define PWR_CSR2_EN_XSPIM1_Pos (14U) +#define PWR_CSR2_EN_XSPIM1_Msk (0x1UL << PWR_CSR2_EN_XSPIM1_Pos) /*!< 0x00004000 */ +#define PWR_CSR2_EN_XSPIM1 PWR_CSR2_EN_XSPIM1_Msk /*!< XSPIM1 external supply enable */ + +#define PWR_CSR2_EN_XSPIM2_Pos (15U) +#define PWR_CSR2_EN_XSPIM2_Msk (0x1UL << PWR_CSR2_EN_XSPIM2_Pos) /*!< 0x00008000 */ +#define PWR_CSR2_EN_XSPIM2 PWR_CSR2_EN_XSPIM2_Msk /*!< XSPIM2 external supply enable */ + +#define PWR_CSR2_SDEXTRDY_Pos (16U) +#define PWR_CSR2_SDEXTRDY_Msk (0x1UL << PWR_CSR2_SDEXTRDY_Pos) /*!< 0x00010000 */ +#define PWR_CSR2_SDEXTRDY PWR_CSR2_SDEXTRDY_Msk /*!< SMPS External supply ready */ + +#define PWR_CSR2_USB33DEN_Pos (24U) +#define PWR_CSR2_USB33DEN_Msk (0x1UL << PWR_CSR2_USB33DEN_Pos) /*!< 0x01000000 */ +#define PWR_CSR2_USB33DEN PWR_CSR2_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */ + +#define PWR_CSR2_USBREGEN_Pos (25U) +#define PWR_CSR2_USBREGEN_Msk (0x1UL << PWR_CSR2_USBREGEN_Pos) /*!< 0x02000000 */ +#define PWR_CSR2_USBREGEN PWR_CSR2_USBREGEN_Msk /*!< USB regulator enable */ + +#define PWR_CSR2_USB33RDY_Pos (26U) +#define PWR_CSR2_USB33RDY_Msk (0x1UL << PWR_CSR2_USB33RDY_Pos) /*!< 0x04000000 */ +#define PWR_CSR2_USB33RDY PWR_CSR2_USB33RDY_Msk /*!< USB supply ready */ + +#define PWR_CSR2_USBHSREGEN_Pos (27U) +#define PWR_CSR2_USBHSREGEN_Msk (0x1UL << PWR_CSR2_USBHSREGEN_Pos) /*!< 0x08000000 */ +#define PWR_CSR2_USBHSREGEN PWR_CSR2_USBHSREGEN_Msk /*!< USB HS regulator enable */ + +/******************** Bit definition for PWR_CSR3 register ********************/ +#define PWR_CSR3_PDDS_Pos (0U) +#define PWR_CSR3_PDDS_Msk (0x1UL << PWR_CSR3_PDDS_Pos) /*!< 0x00000001 */ +#define PWR_CSR3_PDDS PWR_CSR3_PDDS_Msk /*!< D1 domain Power Down Deepsleep */ + +#define PWR_CSR3_CSSF_Pos (1U) +#define PWR_CSR3_CSSF_Msk (0x1UL << PWR_CSR3_CSSF_Pos) /*!< 0x00000002 */ +#define PWR_CSR3_CSSF PWR_CSR3_CSSF_Msk /*!< Clear Standby and Stop flag */ + +#define PWR_CSR3_STOPF_Pos (8U) +#define PWR_CSR3_STOPF_Msk (0x1UL << PWR_CSR3_STOPF_Pos) /*!< 0x00000080 */ +#define PWR_CSR3_STOPF PWR_CSR3_STOPF_Msk /*!< STOP Flag */ + +#define PWR_CSR3_SBF_Pos (9U) +#define PWR_CSR3_SBF_Msk (0x1UL << PWR_CSR3_SBF_Pos) /*!< 0x00000100 */ +#define PWR_CSR3_SBF PWR_CSR3_SBF_Msk /*!< System STANDBY Flag */ + +/******************** Bit definition for PWR_CSR4 register ********************/ +#define PWR_CSR4_VOS_Pos (0U) +#define PWR_CSR4_VOS_Msk (0x1UL << PWR_CSR4_VOS_Pos) /*!< 0x00000001 */ +#define PWR_CSR4_VOS PWR_CSR4_VOS_Msk /*!< Voltage Scaling selection according performance */ + +#define PWR_CSR4_VOSRDY_Pos (1U) +#define PWR_CSR4_VOSRDY_Msk (0x1UL << PWR_CSR4_VOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_CSR4_VOSRDY PWR_CSR4_VOSRDY_Msk /*!< VOSRDY: VOS Ready bit for VCORE voltage scaling output selection. */ + +/******************** Bit definition for PWR_WKUPCR register ********************/ +#define PWR_WKUPCR_WKUPC_Pos (0U) +#define PWR_WKUPCR_WKUPC_Msk (0xFUL << PWR_WKUPCR_WKUPC_Pos) /*!< 0x0000000F */ +#define PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC_Msk /*!< Clear Wakeup Pin Flag 1 to 4 */ +#define PWR_WKUPCR_WKUPC1_Pos (0U) +#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */ +#define PWR_WKUPCR_WKUPC2_Pos (1U) +#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */ +#define PWR_WKUPCR_WKUPC3_Pos (2U) +#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */ +#define PWR_WKUPCR_WKUPC4_Pos (3U) +#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */ + +/******************** Bit definition for PWR_WKUPFR register ********************/ +#define PWR_WKUPFR_WKUPF1_Pos (0U) +#define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */ +#define PWR_WKUPFR_WKUPF2_Pos (1U) +#define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */ +#define PWR_WKUPFR_WKUPF3_Pos (2U) +#define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */ +#define PWR_WKUPFR_WKUPF4_Pos (3U) +#define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */ + +/******************** Bit definition for PWR_WKUPEPR register ********************/ +#define PWR_WKUPEPR_WKUPEN_Pos (0U) +#define PWR_WKUPEPR_WKUPEN_Msk (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000000F */ +#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */ +#define PWR_WKUPEPR_WKUPEN1_Pos (0U) +#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup Pin WKUP1 */ +#define PWR_WKUPEPR_WKUPEN2_Pos (1U) +#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup Pin WKUP2 */ +#define PWR_WKUPEPR_WKUPEN3_Pos (2U) +#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup Pin WKUP3 */ +#define PWR_WKUPEPR_WKUPEN4_Pos (3U) +#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup Pin WKUP4 */ + +#define PWR_WKUPEPR_WKUPP_Pos (8U) +#define PWR_WKUPEPR_WKUPP_Msk (0x0FUL << PWR_WKUPEPR_WKUPP_Pos) /*!< 0x0000F00 */ +#define PWR_WKUPEPR_WKUPP PWR_WKUPEPR_WKUPP_Msk /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */ +#define PWR_WKUPEPR_WKUPP1_Pos (8U) +#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Pin Polarity for WKUP1 */ +#define PWR_WKUPEPR_WKUPP2_Pos (9U) +#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Pin Polarity for WKUP2 */ +#define PWR_WKUPEPR_WKUPP3_Pos (10U) +#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Pin Polarity for WKUP3 */ +#define PWR_WKUPEPR_WKUPP4_Pos (11U) +#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Pin Polarity for WKUP4 */ + +#define PWR_WKUPEPR_WKUPPUPD1_Pos (16U) +#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */ +#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WKUPEPR_WKUPPUPD2_Pos (18U) +#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */ +#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WKUPEPR_WKUPPUPD3_Pos (20U) +#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */ +#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WKUPEPR_WKUPPUPD4_Pos (22U) +#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */ +#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for PWR_UCPDRR register ********************/ +#define PWR_UCPDR_UCPD_DBDIS_Pos (0U) +#define PWR_UCPDR_UCPD_DBDIS_Msk (0x1UL << PWR_UCPDR_UCPD_DBDIS_Pos) /*!< 0x00000001 */ +#define PWR_UCPDR_UCPD_DBDIS PWR_UCPDR_UCPD_DBDIS_Msk /*!< UCPD dead battery disable */ + +#define PWR_UCPDR_UCPD_STBY_Pos (1U) +#define PWR_UCPDR_UCPD_STBY_Msk (0x1UL << PWR_UCPDR_UCPD_STBY_Pos) /*!< 0x00000002 */ +#define PWR_UCPDR_UCPD_STBY PWR_UCPDR_UCPD_STBY_Msk /*!< UCPD Standby mode */ + +/******************** Bit definition for PWR_APCR register ********************/ +#define PWR_APCR_APC_Pos (0U) +#define PWR_APCR_APC_Msk (0x1UL << PWR_APCR_APC_Pos) /*!< 0x00000001 */ +#define PWR_APCR_APC PWR_APCR_APC_Msk /*!< Apply pull configuration register */ + +#define PWR_APCR_PN7_PUPD_Pos (16U) +#define PWR_APCR_PN7_PUPD_Msk (0x1UL << PWR_APCR_PN7_PUPD_Pos) /*!< 0x00010000 */ +#define PWR_APCR_PN7_PUPD PWR_APCR_PN7_PUPD_Msk /*!< Port N bit 7 pull-up/down configuration */ + +#define PWR_APCR_PO5_PUPD_Pos (17) +#define PWR_APCR_PO5_PUPD_Msk (0x1UL << PWR_APCR_PO5_PUPD_Pos) /*!< 0x00020000 */ +#define PWR_APCR_PO5_PUPD PWR_APCR_PO5_PUPD_Msk /*!< Port O bit 5 pull-up/down configuration */ + +#define PWR_APCR_I3CPB6_PU_Pos (28U) +#define PWR_APCR_I3CPB6_PU_Msk (0x1UL << PWR_APCR_I3CPB6_PU_Pos) /*!< 0x10000000 */ +#define PWR_APCR_I3CPB6_PU PWR_APCR_I3CPB6_PU_Msk /*!< Port PB6 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB7_PU_Pos (29U) +#define PWR_APCR_I3CPB7_PU_Msk (0x1UL << PWR_APCR_I3CPB7_PU_Pos) /*!< 0x20000000 */ +#define PWR_APCR_I3CPB7_PU PWR_APCR_I3CPB7_PU_Msk /*!< Port PB7 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB8_PU_Pos (30U) +#define PWR_APCR_I3CPB8_PU_Msk (0x1UL << PWR_APCR_I3CPB8_PU_Pos) /*!< 0x40000000 */ +#define PWR_APCR_I3CPB8_PU PWR_APCR_I3CPB8_PU_Msk /*!< Port PB8 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB9_PU_Pos (31U) +#define PWR_APCR_I3CPB9_PU_Msk (0x1UL << PWR_APCR_I3CPB9_PU_Pos) /*!< 0x80000000 */ +#define PWR_APCR_I3CPB9_PU PWR_APCR_I3CPB9_PU_Msk /*!< Port PB9 I3C pull-up bit configuration */ + +/******************** Bit definition for PWR_PUCRN register ********************/ +#define PWR_PUCRN_PUN1_Pos (1U) +#define PWR_PUCRN_PUN1_Msk (0x1UL << PWR_PUCRN_PUN1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRN_PUN1 PWR_PUCRN_PUN1_Msk /*!< PUN1: Port N pull-up */ + +#define PWR_PUCRN_PUN6_Pos (6U) +#define PWR_PUCRN_PUN6_Msk (0x1UL << PWR_PUCRN_PUN6_Pos) /*!< 0x00000040 */ +#define PWR_PUCRN_PUN6 PWR_PUCRN_PUN6_Msk /*!< PUN6: Port N pull-up */ + +#define PWR_PUCRN_PUN12_Pos (12U) +#define PWR_PUCRN_PUN12_Msk (0x1UL << PWR_PUCRN_PUN12_Pos) /*!< 0x00001000 */ +#define PWR_PUCRN_PUN12 PWR_PUCRN_PUN12_Msk /*!< PUN12: Port N pull-up */ + +/******************** Bit definition for PWR_PDCRN register ********************/ +#define PWR_PDCRN_PDN0_Pos (0U) +#define PWR_PDCRN_PDN0_Msk (0x1UL << PWR_PDCRN_PDN0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRN_PDN0 PWR_PDCRN_PDN0_Msk /*!< PDN0: Port N pull-down */ + +#define PWR_PDCRN_PDN1_Pos (1U) +#define PWR_PDCRN_PDN1_Msk (0x1UL << PWR_PDCRN_PDN1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRN_PDN1 PWR_PDCRN_PDN1_Msk /*!< PDN1: Port N pull-down */ + +#define PWR_PDCRN_PDN2N5_Pos (2U) +#define PWR_PDCRN_PDN2N5_Msk (0x1UL << PWR_PDCRN_PDN2N5_Pos) /*!< 0x00000004 */ +#define PWR_PDCRN_PDN2N5 PWR_PDCRN_PDN2N5_Msk /*!< PDN2 to PDN5: Port N pull-down */ + +#define PWR_PDCRN_PDN6_Pos (6U) +#define PWR_PDCRN_PDN6_Msk (0x1UL << PWR_PDCRN_PDN6_Pos) /*!< 0x00000040 */ +#define PWR_PDCRN_PDN6 PWR_PDCRN_PDN6_Msk /*!< PDN6: Port N pull-down */ + +#define PWR_PDCRN_PDN8N11_Pos (8U) +#define PWR_PDCRN_PDN8N11_Msk (0x1UL << PWR_PDCRN_PDN8N11_Pos) /*!< 0x00000100 */ +#define PWR_PDCRN_PDN8N11 PWR_PDCRN_PDN8N11_Msk /*!< PDN8 to PDN11: Port N pull-down */ + +#define PWR_PDCRN_PDN12_Pos (12U) +#define PWR_PDCRN_PDN12_Msk (0x1UL << PWR_PDCRN_PDN12_Pos) /*!< 0x00001000 */ +#define PWR_PDCRN_PDN12 PWR_PDCRN_PDN12_Msk /*!< PDN12: Port N pull-down */ + +/******************** Bit definition for PWR_PUCRO register ********************/ +#define PWR_PUCRO_PUO0_Pos (0U) +#define PWR_PUCRO_PUO0_Msk (0x1UL << PWR_PUCRO_PUO0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRO_PUO0 PWR_PUCRO_PUO0_Msk /*!< PUO0: Port O pull-up */ + +#define PWR_PUCRO_PUO1_Pos (1U) +#define PWR_PUCRO_PUO1_Msk (0x1UL << PWR_PUCRO_PUO1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRO_PUO1 PWR_PUCRO_PUO1_Msk /*!< PUO1: Port O pull-up */ + +#define PWR_PUCRO_PUO4_Pos (4U) +#define PWR_PUCRO_PUO4_Msk (0x1UL << PWR_PUCRO_PUO4_Pos) /*!< 0x00000010 */ +#define PWR_PUCRO_PUO4 PWR_PUCRO_PUO4_Msk /*!< PUO4: Port O pull-up */ + +/******************** Bit definition for PWR_PDCRO register ********************/ +#define PWR_PDCRO_PDO0_Pos (0U) +#define PWR_PDCRO_PDO0_Msk (0x1UL << PWR_PDCRO_PDO0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRO_PDO0 PWR_PDCRO_PDO0_Msk /*!< PDO0: Port O pull-down */ + +#define PWR_PDCRO_PDO1_Pos (1U) +#define PWR_PDCRO_PDO1_Msk (0x1UL << PWR_PDCRO_PDO1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRO_PDO1 PWR_PDCRO_PDO1_Msk /*!< PDO1: Port O pull-down */ + +#define PWR_PDCRO_PDO2_Pos (2U) +#define PWR_PDCRO_PDO2_Msk (0x1UL << PWR_PDCRO_PDO2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRO_PDO2 PWR_PDCRO_PDO2_Msk /*!< PDO2: Port O pull-down */ + +#define PWR_PDCRO_PDO3_Pos (3U) +#define PWR_PDCRO_PDO3_Msk (0x1UL << PWR_PDCRO_PDO3_Pos) /*!< 0x00000008 */ +#define PWR_PDCRO_PDO3 PWR_PDCRO_PDO3_Msk /*!< PDO3: Port O pull-down */ + +#define PWR_PDCRO_PDO4_Pos (4U) +#define PWR_PDCRO_PDO4_Msk (0x1UL << PWR_PDCRO_PDO4_Pos) /*!< 0x00000010 */ +#define PWR_PDCRO_PDO4 PWR_PDCRO_PDO4_Msk /*!< PDO4: Port O pull-down */ + +/******************** Bit definition for PWR_PDCRP register ********************/ +#define PWR_PDCRP_PDP0P3_Pos (0U) +#define PWR_PDCRP_PDP0P3_Msk (0x1UL << PWR_PDCRP_PDP0P3_Pos) /*!< 0x00000001 */ +#define PWR_PDCRP_PDP0P3 PWR_PDCRP_PDP0P3_Msk /*!< PPO0 to PP03 : Port P pull-down */ + +#define PWR_PDCRP_PDP4P7_Pos (4U) +#define PWR_PDCRP_PDP4P7_Msk (0x1UL << PWR_PDCRP_PDP4P7_Pos) /*!< 0x00000010 */ +#define PWR_PDCRP_PDP4P7 PWR_PDCRP_PDP4P7_Msk /*!< PPO4 to PP07 : Port P pull-down */ + +#define PWR_PDCRP_PDP8P11_Pos (8U) +#define PWR_PDCRP_PDP8P11_Msk (0x1UL << PWR_PDCRP_PDP8P11_Pos) /*!< 0x00000100 */ +#define PWR_PDCRP_PDP8P11 PWR_PDCRP_PDP8P11_Msk /*!< PPO8 to PP11 : Port P pull-down */ + +#define PWR_PDCRP_PDP12P15_Pos (12U) +#define PWR_PDCRP_PDP12P15_Msk (0x1UL << PWR_PDCRP_PDP12P15_Pos) /*!< 0x00001000 */ +#define PWR_PDCRP_PDP12P15 PWR_PDCRP_PDP12P15_Msk /*!< PP12 to PP15 : Port P pull-down */ + + +/******************************************************************************/ +/* */ +/* RAM ECC monitoring */ +/* */ +/******************************************************************************/ +/****************** Bit definition for RAMECC_IER register ******************/ +#define RAMECC_IER_GIE_Pos (0U) +#define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) /*!< 0x00000001 */ +#define RAMECC_IER_GIE RAMECC_IER_GIE_Msk /*!< Global interrupt enable */ +#define RAMECC_IER_GECCSEIE_Pos (1U) +#define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) /*!< 0x00000002 */ +#define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk /*!< Global ECC single error interrupt enable */ +#define RAMECC_IER_GECCDEIE_Pos (2U) +#define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) /*!< 0x00000004 */ +#define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk /*!< Global ECC double error interrupt enable */ +#define RAMECC_IER_GECCDEBWIE_Pos (3U) +#define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) /*!< 0x00000008 */ +#define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk /*!< Global ECC double error on byte write (BW) interrupt enable */ + +/******************* Bit definition for RAMECC_CR register ******************/ +#define RAMECC_CR_ECCSEIE_Pos (2U) +#define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) /*!< 0x00000004 */ +#define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk /*!< ECC single error interrupt enable */ +#define RAMECC_CR_ECCDEIE_Pos (3U) +#define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) /*!< 0x00000008 */ +#define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk /*!< ECC double error interrupt enable */ +#define RAMECC_CR_ECCDEBWIE_Pos (4U) +#define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) /*!< 0x00000010 */ +#define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk /*!< ECC double error on byte write (BW) interrupt enable */ +#define RAMECC_CR_ECCELEN_Pos (5U) +#define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) /*!< 0x00000020 */ +#define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk /*!< ECC error latching enable */ + +/******************* Bit definition for RAMECC_SR register ******************/ +#define RAMECC_SR_SEDCF_Pos (0U) +#define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) /*!< 0x00000001 */ +#define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk /*!< ECC single error detected and corrected flag */ +#define RAMECC_SR_DEDF_Pos (1U) +#define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) /*!< 0x00000002 */ +#define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk /*!< ECC double error detected flag */ +#define RAMECC_SR_DEBWDF_Pos (2U) +#define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) /*!< 0x00000004 */ +#define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk /*!< ECC double error on byte write (BW) detected flag */ + +/****************** Bit definition for RAMECC_FAR register ******************/ +#define RAMECC_FAR_FADD_Pos (0U) +#define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk /*!< ECC error failing address */ + +/****************** Bit definition for RAMECC_FDRL register *****************/ +#define RAMECC_FDRL_FDATAL_Pos (0U) +#define RAMECC_FDRL_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FDRL_FDATAL_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FDRL_FDATAL RAMECC_FDRL_FDATAL_Msk /*!< Failing data low */ + +/****************** Bit definition for RAMECC_FDRH register *****************/ +#define RAMECC_FDRH_FDATAH_Pos (0U) +#define RAMECC_FDRH_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FDRH_FDATAH_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FDRH_FDATAH RAMECC_FDRH_FDATAH_Msk /* Failing data high (64-bit memory) */ + +/***************** Bit definition for RAMECC_FECR register ******************/ +#define RAMECC_FECR_FEC_Pos (0U) +#define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk /*!< Failing error code */ + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIKERON_Pos (1U) +#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable in Stop mode */ +#define RCC_CR_HSIRDY_Pos (2U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIV_Pos (3U) +#define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */ +#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< Internal High Speed clock divider selection */ +#define RCC_CR_HSIDIV_0 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSIDIV_1 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000010 */ + +#define RCC_CR_HSIDIVF_Pos (5U) +#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000020 */ +#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< HSI Divider flag */ +#define RCC_CR_CSION_Pos (7U) +#define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) /*!< 0x00000080 */ +#define RCC_CR_CSION RCC_CR_CSION_Msk /*!< The Internal RC 4MHz oscillator clock enable */ +#define RCC_CR_CSIRDY_Pos (8U) +#define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) /*!< 0x00000100 */ +#define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk /*!< The Internal RC 4MHz oscillator clock ready */ +#define RCC_CR_CSIKERON_Pos (9U) +#define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) /*!< 0x00000200 */ +#define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk /*!< Internal RC 4MHz oscillator clock enable in Stop mode */ +#define RCC_CR_HSI48ON_Pos (12U) +#define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) /*!< 0x00001000 */ +#define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk /*!< HSI48 clock enable clock enable */ +#define RCC_CR_HSI48RDY_Pos (13U) +#define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) /*!< 0x00002000 */ +#define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk /*!< HSI48 clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock bypass */ +#define RCC_CR_HSEEXT_Pos (19U) +#define RCC_CR_HSEEXT_Msk (0x1UL << RCC_CR_HSEEXT_Pos) /*!< 0x00100000 */ +#define RCC_CR_HSEEXT RCC_CR_HSEEXT_Msk /*!< External High Speed clock type in bypass mode */ +#define RCC_CR_HSECSSON_Pos (20U) +#define RCC_CR_HSECSSON_Msk (0x1UL << RCC_CR_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSECSSON RCC_CR_HSECSSON_Msk /*!< HSE Clock security System enable */ +#define RCC_CR_PLL1ON_Pos (24U) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */ +#define RCC_CR_PLL1RDY_Pos (25U) +#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready flag */ +#define RCC_CR_PLL2ON_Pos (26U) +#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */ +#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< System PLL2 clock enable */ +#define RCC_CR_PLL2RDY_Pos (27U) +#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */ +#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< System PLL2 clock ready flag */ +#define RCC_CR_PLL3ON_Pos (28U) +#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */ +#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< System PLL3 clock enable */ +#define RCC_CR_PLL3RDY_Pos (29U) +#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */ +#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< System PLL3 clock ready flag */ + +/******************** Bit definition for RCC_HSICFGR register ***************/ +/*!< HSICAL configuration */ +#define RCC_HSICFGR_HSICAL_Pos (0U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSICAL[11:0] bits */ +#define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */ +#define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */ +#define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */ +#define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */ +#define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */ +#define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */ +#define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */ + +/*!< HSITRIM configuration */ +#define RCC_HSICFGR_HSITRIM_Pos (24U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ +#define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CRRCR register *****************/ +/*!< HSI48CAL configuration */ +#define RCC_CRRCR_HSI48CAL_Pos (0U) +#define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */ +#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[9:0] bits */ +#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */ +#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */ +#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */ +#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */ +#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */ +#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */ +#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */ +#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */ +#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */ +#define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */ + +/******************** Bit definition for RCC_CSICFGR register ***************/ +/*!< CSICAL configuration */ +#define RCC_CSICFGR_CSICAL_Pos (0U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSICAL[7:0] bits */ +#define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */ +#define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */ +#define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */ +#define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */ +#define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */ +#define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */ +#define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */ +#define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */ + +/*!< CSITRIM configuration */ +#define RCC_CSICFGR_CSITRIM_Pos (24U) +#define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSITRIM[5:0] bits */ +#define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */ +#define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */ +#define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */ +#define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for RCC_CFGR register ******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock switch) */ +#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_Pos (3U) +#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System clock switch status) */ +#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ + +#define RCC_CFGR_STOPWUCK_Pos (6U) +#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */ +#define RCC_CFGR_STOPKERWUCK_Pos (7U) +#define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) /*!< 0x00000080 */ +#define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk /*!< Kernel Clock Selection after a Wake Up from Stop */ + +/*!< RTCPRE configuration */ +#define RCC_CFGR_RTCPRE_Pos (8U) +#define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00003F00 */ +#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk /*!< RTCPRE[5:0] bits (HSE division factor for RTC clock) */ +#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00002000 */ + +#define RCC_CFGR_TIMPRE_Pos (15U) +#define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos) /*!< 0x00008000 */ +#define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk /*!< TIMPRE configuration */ + +#define RCC_CFGR_MCO1PRE_Pos (18U) +#define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk /*!< MCO1 configuration */ +#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00200000 */ + +#define RCC_CFGR_MCO1SEL_Pos (22U) +#define RCC_CFGR_MCO1SEL_Msk (0x7UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x01C00000 */ +#define RCC_CFGR_MCO1SEL RCC_CFGR_MCO1SEL_Msk /*!< MCO1SEL [2:0] bits (MCO1 clock output selection) */ +#define RCC_CFGR_MCO1SEL_0 (0x1UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_MCO1SEL_1 (0x2UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x00800000 */ +#define RCC_CFGR_MCO1SEL_2 (0x4UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x01000000 */ + +#define RCC_CFGR_MCO2PRE_Pos (25U) +#define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x1E000000 */ +#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< MCO2 configuration */ +#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */ + +#define RCC_CFGR_MCO2SEL_Pos (29U) +#define RCC_CFGR_MCO2SEL_Msk (0x7UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0xE0000000 */ +#define RCC_CFGR_MCO2SEL RCC_CFGR_MCO2SEL_Msk /*!< MCO2SEL [2:0] bits (MCO2 clock output selection) */ +#define RCC_CFGR_MCO2SEL_0 (0x1UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x20000000 */ +#define RCC_CFGR_MCO2SEL_1 (0x2UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x40000000 */ +#define RCC_CFGR_MCO2SEL_2 (0x4UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for RCC_CDCFGR register ****************/ +/*!< CPRE configuration */ +#define RCC_CDCFGR_CPRE_Pos (0U) +#define RCC_CDCFGR_CPRE_Msk (0xFUL << RCC_CDCFGR_CPRE_Pos) /*!< 0x0000000F */ +#define RCC_CDCFGR_CPRE RCC_CDCFGR_CPRE_Msk /*!< CPRE[3:0] bits */ +#define RCC_CDCFGR_CPRE_0 (0x1UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000001 */ +#define RCC_CDCFGR_CPRE_1 (0x2UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000002 */ +#define RCC_CDCFGR_CPRE_2 (0x4UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000004 */ +#define RCC_CDCFGR_CPRE_3 (0x8UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for RCC_BMCFGR register ****************/ +/*!< BMPRE configuration */ +#define RCC_BMCFGR_BMPRE_Pos (0U) +#define RCC_BMCFGR_BMPRE_Msk (0xFUL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x0000000F */ +#define RCC_BMCFGR_BMPRE RCC_BMCFGR_BMPRE_Msk /*!< BMPRE[3:0] bits */ +#define RCC_BMCFGR_BMPRE_0 (0x1UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000001 */ +#define RCC_BMCFGR_BMPRE_1 (0x2UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000002 */ +#define RCC_BMCFGR_BMPRE_2 (0x4UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000004 */ +#define RCC_BMCFGR_BMPRE_3 (0x8UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for RCC_APBCFGR register ***************/ +/*!< APB1 prescaler configuration */ +#define RCC_APBCFGR_PPRE1_Pos (0U) +#define RCC_APBCFGR_PPRE1_Msk (0x7UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000007 */ +#define RCC_APBCFGR_PPRE1 RCC_APBCFGR_PPRE1_Msk /*!< PPRE1[2:0] bits */ +#define RCC_APBCFGR_PPRE1_0 (0x1UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000001 */ +#define RCC_APBCFGR_PPRE1_1 (0x2UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000002 */ +#define RCC_APBCFGR_PPRE1_2 (0x4UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000004 */ + +/*!< APB2 prescaler configuration */ +#define RCC_APBCFGR_PPRE2_Pos (4U) +#define RCC_APBCFGR_PPRE2_Msk (0x7UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000070 */ +#define RCC_APBCFGR_PPRE2 RCC_APBCFGR_PPRE2_Msk /*!< PPRE2[2:0] bits */ +#define RCC_APBCFGR_PPRE2_0 (0x1UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000010 */ +#define RCC_APBCFGR_PPRE2_1 (0x2UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000020 */ +#define RCC_APBCFGR_PPRE2_2 (0x4UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000040 */ + +/*!< APB4 prescaler configuration */ +#define RCC_APBCFGR_PPRE4_Pos (8U) +#define RCC_APBCFGR_PPRE4_Msk (0x7UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000700 */ +#define RCC_APBCFGR_PPRE4 RCC_APBCFGR_PPRE4_Msk /*!< PPRE4[2:0] bits */ +#define RCC_APBCFGR_PPRE4_0 (0x1UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000100 */ +#define RCC_APBCFGR_PPRE4_1 (0x2UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000200 */ +#define RCC_APBCFGR_PPRE4_2 (0x4UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000400 */ + +/*!< APB5 prescaler configuration */ +#define RCC_APBCFGR_PPRE5_Pos (12U) +#define RCC_APBCFGR_PPRE5_Msk (0x7UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00007000 */ +#define RCC_APBCFGR_PPRE5 RCC_APBCFGR_PPRE5_Msk /*!< PPRE5[2:0] bits */ +#define RCC_APBCFGR_PPRE5_0 (0x1UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00001000 */ +#define RCC_APBCFGR_PPRE5_1 (0x2UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00002000 */ +#define RCC_APBCFGR_PPRE5_2 (0x4UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_PLLCKSELR register *************/ +#define RCC_PLLCKSELR_PLLSRC_Pos (0U) +#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ +#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk /*!< DIVMx and PLLs clock source selection */ +#define RCC_PLLCKSELR_PLLSRC_0 (0x01UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000010 */ +#define RCC_PLLCKSELR_PLLSRC_1 (0x02UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000020 */ + +#define RCC_PLLCKSELR_DIVM1_Pos (4U) +#define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */ +#define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk /*!< DIVM1[5:0] bits */ +#define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */ +#define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */ +#define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */ +#define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */ +#define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */ +#define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */ + +#define RCC_PLLCKSELR_DIVM2_Pos (12U) +#define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */ +#define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk /*!< DIVM2[5:0] bits */ +#define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */ +#define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */ +#define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */ +#define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */ +#define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */ + +#define RCC_PLLCKSELR_DIVM3_Pos (20U) +#define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */ +#define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk /*!< DIVM3[5:0] bits */ +#define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */ +#define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */ +#define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */ +#define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for RCC_PLLCFGR register ***************/ +#define RCC_PLLCFGR_PLL1FRACEN_Pos (0U) +#define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */ +#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk /*!< PLL1 fractional latch enable */ +#define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U) +#define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */ +#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk /*!< PLL1 VCO selection */ +#define RCC_PLLCFGR_PLL1SSCGEN_Pos (2U) +#define RCC_PLLCFGR_PLL1SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL1SSCGEN_Pos) /*!< 0x00000004 */ +#define RCC_PLLCFGR_PLL1SSCGEN RCC_PLLCFGR_PLL1SSCGEN_Msk /*!< PLL1 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL1RGE_Pos (3U) +#define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000018 */ +#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk /*!< PLL1RGE[1:0] bits: PLL1 input frequency range */ +#define RCC_PLLCFGR_PLL1RGE_0 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */ +#define RCC_PLLCFGR_PLL1RGE_1 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000010 */ + +#define RCC_PLLCFGR_PLL1PEN_Pos (5U) +#define RCC_PLLCFGR_PLL1PEN_Msk (0x1UL << RCC_PLLCFGR_PLL1PEN_Pos) /*!< 0x00000020 */ +#define RCC_PLLCFGR_PLL1PEN RCC_PLLCFGR_PLL1PEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL1QEN_Pos (6U) +#define RCC_PLLCFGR_PLL1QEN_Msk (0x1UL << RCC_PLLCFGR_PLL1QEN_Pos) /*!< 0x00000040 */ +#define RCC_PLLCFGR_PLL1QEN RCC_PLLCFGR_PLL1QEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL1REN_Pos (7U) +#define RCC_PLLCFGR_PLL1REN_Msk (0x1UL << RCC_PLLCFGR_PLL1REN_Pos) /*!< 0x00000080 */ +#define RCC_PLLCFGR_PLL1REN RCC_PLLCFGR_PLL1REN_Msk /*!< PLL1 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL1SEN_Pos (8U) +#define RCC_PLLCFGR_PLL1SEN_Msk (0x1UL << RCC_PLLCFGR_PLL1SEN_Pos) /*!< 0x00000100 */ +#define RCC_PLLCFGR_PLL1SEN RCC_PLLCFGR_PLL1SEN_Msk /*!< PLL1 DIVS divider output enable */ + +#define RCC_PLLCFGR_PLL2FRACEN_Pos (11U) +#define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000800 */ +#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk /*!< PLL2 fractional latch enable */ +#define RCC_PLLCFGR_PLL2VCOSEL_Pos (12U) +#define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00001000 */ +#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk /*!< PLL2 VCO selection */ +#define RCC_PLLCFGR_PLL2SSCGEN_Pos (13U) +#define RCC_PLLCFGR_PLL2SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL2SSCGEN_Pos) /*!< 0x00002000 */ +#define RCC_PLLCFGR_PLL2SSCGEN RCC_PLLCFGR_PLL2SSCGEN_Msk /*!< PLL2 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL2RGE_Pos (14U) +#define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x0000C000 */ +#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk /*!< PLL2RGE[1:0] bits: PLL2 input frequency range */ +#define RCC_PLLCFGR_PLL2RGE_0 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00004000 */ +#define RCC_PLLCFGR_PLL2RGE_1 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00008000 */ + +#define RCC_PLLCFGR_PLL2PEN_Pos (16U) +#define RCC_PLLCFGR_PLL2PEN_Msk (0x1UL << RCC_PLLCFGR_PLL2PEN_Pos) /*!< 0x00010000 */ +#define RCC_PLLCFGR_PLL2PEN RCC_PLLCFGR_PLL2PEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL2QEN_Pos (17U) +#define RCC_PLLCFGR_PLL2QEN_Msk (0x1UL << RCC_PLLCFGR_PLL2QEN_Pos) /*!< 0x00020000 */ +#define RCC_PLLCFGR_PLL2QEN RCC_PLLCFGR_PLL2QEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL2REN_Pos (18U) +#define RCC_PLLCFGR_PLL2REN_Msk (0x1UL << RCC_PLLCFGR_PLL2REN_Pos) /*!< 0x00040000 */ +#define RCC_PLLCFGR_PLL2REN RCC_PLLCFGR_PLL2REN_Msk /*!< PLL2 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL2SEN_Pos (19U) +#define RCC_PLLCFGR_PLL2SEN_Msk (0x1UL << RCC_PLLCFGR_PLL2SEN_Pos) /*!< 0x00080000 */ +#define RCC_PLLCFGR_PLL2SEN RCC_PLLCFGR_PLL2SEN_Msk /*!< PLL2 DIVS divider output enable */ +#define RCC_PLLCFGR_PLL2TEN_Pos (20U) +#define RCC_PLLCFGR_PLL2TEN_Msk (0x1UL << RCC_PLLCFGR_PLL2TEN_Pos) /*!< 0x00100000 */ +#define RCC_PLLCFGR_PLL2TEN RCC_PLLCFGR_PLL2TEN_Msk /*!< PLL2 DIVT divider output enable */ + +#define RCC_PLLCFGR_PLL3FRACEN_Pos (22U) +#define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00400000 */ +#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk /*!< PLL3 fractional latch enable */ +#define RCC_PLLCFGR_PLL3VCOSEL_Pos (23U) +#define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00800000 */ +#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk /*!< PLL3 VCO selection */ +#define RCC_PLLCFGR_PLL3SSCGEN_Pos (24U) +#define RCC_PLLCFGR_PLL3SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL3SSCGEN_Pos) /*!< 0x01000000 */ +#define RCC_PLLCFGR_PLL3SSCGEN RCC_PLLCFGR_PLL3SSCGEN_Msk /*!< PLL3 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL3RGE_Pos (25U) +#define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x06000000 */ +#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk /*!< PLL3RGE[1:0] bits: PLL3 input frequency range */ +#define RCC_PLLCFGR_PLL3RGE_0 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x02000000 */ +#define RCC_PLLCFGR_PLL3RGE_1 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x04000000 */ + +#define RCC_PLLCFGR_PLL3PEN_Pos (27U) +#define RCC_PLLCFGR_PLL3PEN_Msk (0x1UL << RCC_PLLCFGR_PLL3PEN_Pos) /*!< 0x08000000 */ +#define RCC_PLLCFGR_PLL3PEN RCC_PLLCFGR_PLL3PEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL3QEN_Pos (28U) +#define RCC_PLLCFGR_PLL3QEN_Msk (0x1UL << RCC_PLLCFGR_PLL3QEN_Pos) /*!< 0x10000000 */ +#define RCC_PLLCFGR_PLL3QEN RCC_PLLCFGR_PLL3QEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL3REN_Pos (29U) +#define RCC_PLLCFGR_PLL3REN_Msk (0x1UL << RCC_PLLCFGR_PLL3REN_Pos) /*!< 0x20000000 */ +#define RCC_PLLCFGR_PLL3REN RCC_PLLCFGR_PLL3REN_Msk /*!< PLL3 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL3SEN_Pos (30U) +#define RCC_PLLCFGR_PLL3SEN_Msk (0x1UL << RCC_PLLCFGR_PLL3SEN_Pos) /*!< 0x40000000 */ +#define RCC_PLLCFGR_PLL3SEN RCC_PLLCFGR_PLL3SEN_Msk /*!< PLL3 DIVS divider output enable */ + +/******************** Bit definition for RCC_PLL1DIVR1 register *************/ +#define RCC_PLL1DIVR1_DIVN_Pos (0U) +#define RCC_PLL1DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1DIVR1_DIVN RCC_PLL1DIVR1_DIVN_Msk /*!< DIVN1[8:0] bits: PLL1 DIVN division factor */ +#define RCC_PLL1DIVR1_DIVN_0 (0x001UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR1_DIVN_1 (0x002UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR1_DIVN_2 (0x004UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1DIVR1_DIVN_3 (0x008UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1DIVR1_DIVN_4 (0x010UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1DIVR1_DIVN_5 (0x020UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1DIVR1_DIVN_6 (0x040UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1DIVR1_DIVN_7 (0x080UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1DIVR1_DIVN_8 (0x100UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL1DIVR1_DIVP_Pos (9U) +#define RCC_PLL1DIVR1_DIVP_Msk (0x7FUL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL1DIVR1_DIVP RCC_PLL1DIVR1_DIVP_Msk /*!< DIVP1[6:0] bits: PLL1 DIVP division factor */ +#define RCC_PLL1DIVR1_DIVP_0 (0x001UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL1DIVR1_DIVP_1 (0x002UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL1DIVR1_DIVP_2 (0x004UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL1DIVR1_DIVP_3 (0x008UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL1DIVR1_DIVP_4 (0x010UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL1DIVR1_DIVP_5 (0x020UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL1DIVR1_DIVP_6 (0x040UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL1DIVR1_DIVQ_Pos (16U) +#define RCC_PLL1DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1DIVR1_DIVQ RCC_PLL1DIVR1_DIVQ_Msk /*!< DIVQ1[6:0] bits: PLL1 DIVQ division factor */ +#define RCC_PLL1DIVR1_DIVQ_0 (0x001UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL1DIVR1_DIVQ_1 (0x002UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL1DIVR1_DIVQ_2 (0x004UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL1DIVR1_DIVQ_3 (0x008UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL1DIVR1_DIVQ_4 (0x010UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL1DIVR1_DIVQ_5 (0x020UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL1DIVR1_DIVQ_6 (0x040UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL1DIVR1_DIVR_Pos (24U) +#define RCC_PLL1DIVR1_DIVR_Msk (0x7FUL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL1DIVR1_DIVR RCC_PLL1DIVR1_DIVR_Msk /*!< DIVR1[6:0] bits: PLL1 DIVR division factor */ +#define RCC_PLL1DIVR1_DIVR_0 (0x001UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL1DIVR1_DIVR_1 (0x002UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL1DIVR1_DIVR_2 (0x004UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL1DIVR1_DIVR_3 (0x008UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL1DIVR1_DIVR_4 (0x010UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL1DIVR1_DIVR_5 (0x020UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL1DIVR1_DIVR_6 (0x040UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL1FRACR register *************/ +#define RCC_PLL1FRACR_FRACN_Pos (3U) +#define RCC_PLL1FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACN RCC_PLL1FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_PLL2DIVR1 register *************/ +#define RCC_PLL2DIVR1_DIVN_Pos (0U) +#define RCC_PLL2DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2DIVR1_DIVN RCC_PLL2DIVR1_DIVN_Msk /*!< DIVN2[8:0] bits: PLL2 DIVN division factor */ +#define RCC_PLL2DIVR1_DIVN_0 (0x001UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2DIVR1_DIVN_1 (0x002UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2DIVR1_DIVN_2 (0x004UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2DIVR1_DIVN_3 (0x008UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2DIVR1_DIVN_4 (0x010UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2DIVR1_DIVN_5 (0x020UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2DIVR1_DIVN_6 (0x040UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2DIVR1_DIVN_7 (0x080UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2DIVR1_DIVN_8 (0x100UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL2DIVR1_DIVP_Pos (9U) +#define RCC_PLL2DIVR1_DIVP_Msk (0x7FUL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL2DIVR1_DIVP RCC_PLL2DIVR1_DIVP_Msk /*!< DIVP2[6:0] bits: PLL2 DIVP division factor */ +#define RCC_PLL2DIVR1_DIVP_0 (0x001UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL2DIVR1_DIVP_1 (0x002UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL2DIVR1_DIVP_2 (0x004UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL2DIVR1_DIVP_3 (0x008UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL2DIVR1_DIVP_4 (0x010UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL2DIVR1_DIVP_5 (0x020UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL2DIVR1_DIVP_6 (0x040UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL2DIVR1_DIVQ_Pos (16U) +#define RCC_PLL2DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2DIVR1_DIVQ RCC_PLL2DIVR1_DIVQ_Msk /*!< DIVQ2[6:0] bits: PLL2 DIVQ division factor */ +#define RCC_PLL2DIVR1_DIVQ_0 (0x001UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL2DIVR1_DIVQ_1 (0x002UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL2DIVR1_DIVQ_2 (0x004UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL2DIVR1_DIVQ_3 (0x008UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL2DIVR1_DIVQ_4 (0x010UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL2DIVR1_DIVQ_5 (0x020UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL2DIVR1_DIVQ_6 (0x040UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL2DIVR1_DIVR_Pos (24U) +#define RCC_PLL2DIVR1_DIVR_Msk (0x7FUL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL2DIVR1_DIVR RCC_PLL2DIVR1_DIVR_Msk /*!< DIVR2[6:0] bits: PLL2 DIVR division factor */ +#define RCC_PLL2DIVR1_DIVR_0 (0x001UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL2DIVR1_DIVR_1 (0x002UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL2DIVR1_DIVR_2 (0x004UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL2DIVR1_DIVR_3 (0x008UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL2DIVR1_DIVR_4 (0x010UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL2DIVR1_DIVR_5 (0x020UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL2DIVR1_DIVR_6 (0x040UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL2FRACR register *************/ +#define RCC_PLL2FRACR_FRACN_Pos (3U) +#define RCC_PLL2FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACN RCC_PLL2FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_PLL3DIVR1 register *************/ +#define RCC_PLL3DIVR1_DIVN_Pos (0U) +#define RCC_PLL3DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3DIVR1_DIVN RCC_PLL3DIVR1_DIVN_Msk /*!< DIVN3[8:0] bits: PLL3 DIVN division factor */ +#define RCC_PLL3DIVR1_DIVN_0 (0x001UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3DIVR1_DIVN_1 (0x002UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3DIVR1_DIVN_2 (0x004UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3DIVR1_DIVN_3 (0x008UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3DIVR1_DIVN_4 (0x010UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3DIVR1_DIVN_5 (0x020UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3DIVR1_DIVN_6 (0x040UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3DIVR1_DIVN_7 (0x080UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3DIVR1_DIVN_8 (0x100UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL3DIVR1_DIVP_Pos (9U) +#define RCC_PLL3DIVR1_DIVP_Msk (0x7FUL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL3DIVR1_DIVP RCC_PLL3DIVR1_DIVP_Msk /*!< DIVP3[6:0] bits: PLL3 DIVP division factor */ +#define RCC_PLL3DIVR1_DIVP_0 (0x001UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL3DIVR1_DIVP_1 (0x002UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL3DIVR1_DIVP_2 (0x004UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL3DIVR1_DIVP_3 (0x008UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL3DIVR1_DIVP_4 (0x010UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL3DIVR1_DIVP_5 (0x020UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL3DIVR1_DIVP_6 (0x040UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL3DIVR1_DIVQ_Pos (16U) +#define RCC_PLL3DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3DIVR1_DIVQ RCC_PLL3DIVR1_DIVQ_Msk /*!< DIVQ3[6:0] bits: PLL3 DIVQ division factor */ +#define RCC_PLL3DIVR1_DIVQ_0 (0x001UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL3DIVR1_DIVQ_1 (0x002UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL3DIVR1_DIVQ_2 (0x004UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL3DIVR1_DIVQ_3 (0x008UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL3DIVR1_DIVQ_4 (0x010UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL3DIVR1_DIVQ_5 (0x020UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL3DIVR1_DIVQ_6 (0x040UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL3DIVR1_DIVR_Pos (24U) +#define RCC_PLL3DIVR1_DIVR_Msk (0x7FUL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL3DIVR1_DIVR RCC_PLL3DIVR1_DIVR_Msk /*!< DIVR3[6:0] bits: PLL3 DIVR division factor */ +#define RCC_PLL3DIVR1_DIVR_0 (0x001UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL3DIVR1_DIVR_1 (0x002UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL3DIVR1_DIVR_2 (0x004UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL3DIVR1_DIVR_3 (0x008UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL3DIVR1_DIVR_4 (0x010UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL3DIVR1_DIVR_5 (0x020UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL3DIVR1_DIVR_6 (0x040UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL3FRACR register *************/ +#define RCC_PLL3FRACR_FRACN_Pos (3U) +#define RCC_PLL3FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACN RCC_PLL3FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_CCIPR1 register **************/ +#define RCC_CCIPR1_FMCSEL_Pos (0U) +#define RCC_CCIPR1_FMCSEL_Msk (0x3UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_FMCSEL RCC_CCIPR1_FMCSEL_Msk +#define RCC_CCIPR1_FMCSEL_0 (0x1UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_FMCSEL_1 (0x2UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000002 */ + +#define RCC_CCIPR1_SDMMC12SEL_Pos (2U) +#define RCC_CCIPR1_SDMMC12SEL_Msk (0x1UL << RCC_CCIPR1_SDMMC12SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_SDMMC12SEL RCC_CCIPR1_SDMMC12SEL_Msk + +#define RCC_CCIPR1_XSPI1SEL_Pos (4U) +#define RCC_CCIPR1_XSPI1SEL_Msk (0x3UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR1_XSPI1SEL RCC_CCIPR1_XSPI1SEL_Msk +#define RCC_CCIPR1_XSPI1SEL_0 (0x1UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_XSPI1SEL_1 (0x2UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000020 */ + +#define RCC_CCIPR1_XSPI2SEL_Pos (6U) +#define RCC_CCIPR1_XSPI2SEL_Msk (0x3UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR1_XSPI2SEL RCC_CCIPR1_XSPI2SEL_Msk +#define RCC_CCIPR1_XSPI2SEL_0 (0x1UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_XSPI2SEL_1 (0x2UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x00000080 */ + +#define RCC_CCIPR1_USBREFCKSEL_Pos (8U) +#define RCC_CCIPR1_USBREFCKSEL_Msk (0xFUL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000F00 */ +#define RCC_CCIPR1_USBREFCKSEL RCC_CCIPR1_USBREFCKSEL_Msk +#define RCC_CCIPR1_USBREFCKSEL_0 (0x1UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_USBREFCKSEL_1 (0x2UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_USBREFCKSEL_2 (0x4UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_USBREFCKSEL_3 (0x8UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000800 */ + +#define RCC_CCIPR1_USBPHYCSEL_Pos (12U) +#define RCC_CCIPR1_USBPHYCSEL_Msk (0x3UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR1_USBPHYCSEL RCC_CCIPR1_USBPHYCSEL_Msk +#define RCC_CCIPR1_USBPHYCSEL_0 (0x1UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR1_USBPHYCSEL_1 (0x2UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00002000 */ + +#define RCC_CCIPR1_OTGFSSEL_Pos (14U) +#define RCC_CCIPR1_OTGFSSEL_Msk (0x3UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_OTGFSSEL RCC_CCIPR1_OTGFSSEL_Msk +#define RCC_CCIPR1_OTGFSSEL_0 (0x1UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_OTGFSSEL_1 (0x2UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x00008000 */ + +#define RCC_CCIPR1_ETH1REFCKSEL_Pos (16U) +#define RCC_CCIPR1_ETH1REFCKSEL_Msk (0x3UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_ETH1REFCKSEL RCC_CCIPR1_ETH1REFCKSEL_Msk +#define RCC_CCIPR1_ETH1REFCKSEL_0 (0x1UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_ETH1REFCKSEL_1 (0x2UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00020000 */ + +#define RCC_CCIPR1_ETH1PHYCKSEL_Pos (18U) +#define RCC_CCIPR1_ETH1PHYCKSEL_Msk (0x1UL << RCC_CCIPR1_ETH1PHYCKSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_ETH1PHYCKSEL RCC_CCIPR1_ETH1PHYCKSEL_Msk + +#define RCC_CCIPR1_ADF1SEL_Pos (20U) +#define RCC_CCIPR1_ADF1SEL_Msk (0x7UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR1_ADF1SEL RCC_CCIPR1_ADF1SEL_Msk +#define RCC_CCIPR1_ADF1SEL_0 (0x1UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_ADF1SEL_1 (0x2UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR1_ADF1SEL_2 (0x4UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00400000 */ + +#define RCC_CCIPR1_ADCSEL_Pos (24U) +#define RCC_CCIPR1_ADCSEL_Msk (0x3UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR1_ADCSEL RCC_CCIPR1_ADCSEL_Msk +#define RCC_CCIPR1_ADCSEL_0 (0x1UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR1_ADCSEL_1 (0x2UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x02000000 */ + +#define RCC_CCIPR1_PSSISEL_Pos (27U) +#define RCC_CCIPR1_PSSISEL_Msk (0x1UL << RCC_CCIPR1_PSSISEL_Pos) /*!< 0x08000000 */ +#define RCC_CCIPR1_PSSISEL RCC_CCIPR1_PSSISEL_Msk + +#define RCC_CCIPR1_CKPERSEL_Pos (28U) +#define RCC_CCIPR1_CKPERSEL_Msk (0x3UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x30000000 */ +#define RCC_CCIPR1_CKPERSEL RCC_CCIPR1_CKPERSEL_Msk +#define RCC_CCIPR1_CKPERSEL_0 (0x1UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR1_CKPERSEL_1 (0x2UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for RCC_CCIPR2 register *************/ +#define RCC_CCIPR2_UART234578SEL_Pos (0U) +#define RCC_CCIPR2_UART234578SEL_Msk (0x7UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR2_UART234578SEL RCC_CCIPR2_UART234578SEL_Msk +#define RCC_CCIPR2_UART234578SEL_0 (0x1UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_UART234578SEL_1 (0x2UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_UART234578SEL_2 (0x4UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR2_SPI23SEL_Pos (4U) +#define RCC_CCIPR2_SPI23SEL_Msk (0x7UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR2_SPI23SEL RCC_CCIPR2_SPI23SEL_Msk +#define RCC_CCIPR2_SPI23SEL_0 (0x1UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR2_SPI23SEL_1 (0x2UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR2_SPI23SEL_2 (0x4UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR2_I2C23SEL_Pos (8U) +#define RCC_CCIPR2_I2C23SEL_Msk (0x3UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR2_I2C23SEL RCC_CCIPR2_I2C23SEL_Msk +#define RCC_CCIPR2_I2C23SEL_0 (0x1UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR2_I2C23SEL_1 (0x2UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000200 */ + +#define RCC_CCIPR2_I2C1_I3C1SEL_Pos (12U) +#define RCC_CCIPR2_I2C1_I3C1SEL_Msk (0x3UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR2_I2C1_I3C1SEL RCC_CCIPR2_I2C1_I3C1SEL_Msk +#define RCC_CCIPR2_I2C1_I3C1SEL_0 (0x1UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_I2C1_I3C1SEL_1 (0x2UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00002000 */ + +#define RCC_CCIPR2_LPTIM1SEL_Pos (16U) +#define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR2_LPTIM1SEL RCC_CCIPR2_LPTIM1SEL_Msk +#define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00040000 */ + +#define RCC_CCIPR2_FDCANSEL_Pos (22U) +#define RCC_CCIPR2_FDCANSEL_Msk (0x3UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00C00000 */ +#define RCC_CCIPR2_FDCANSEL RCC_CCIPR2_FDCANSEL_Msk +#define RCC_CCIPR2_FDCANSEL_0 (0x1UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR2_FDCANSEL_1 (0x2UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00800000 */ + +#define RCC_CCIPR2_SPDIFRXSEL_Pos (24U) +#define RCC_CCIPR2_SPDIFRXSEL_Msk (0x3UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_SPDIFRXSEL RCC_CCIPR2_SPDIFRXSEL_Msk +#define RCC_CCIPR2_SPDIFRXSEL_0 (0x1UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_SPDIFRXSEL_1 (0x2UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x02000000 */ + +#define RCC_CCIPR2_CECSEL_Pos (28U) +#define RCC_CCIPR2_CECSEL_Msk (0x3UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_CECSEL RCC_CCIPR2_CECSEL_Msk +#define RCC_CCIPR2_CECSEL_0 (0x1UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_CECSEL_1 (0x2UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for RCC_CCIPR3 register *************/ +#define RCC_CCIPR3_USART1SEL_Pos (0U) +#define RCC_CCIPR3_USART1SEL_Msk (0x7UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR3_USART1SEL RCC_CCIPR3_USART1SEL_Msk +#define RCC_CCIPR3_USART1SEL_0 (0x1UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_USART1SEL_1 (0x2UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_USART1SEL_2 (0x4UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR3_SPI45SEL_Pos (4U) +#define RCC_CCIPR3_SPI45SEL_Msk (0x7UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR3_SPI45SEL RCC_CCIPR3_SPI45SEL_Msk +#define RCC_CCIPR3_SPI45SEL_0 (0x1UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_SPI45SEL_1 (0x2UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR3_SPI45SEL_2 (0x4UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR3_SPI1SEL_Pos (8U) +#define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR3_SPI1SEL RCC_CCIPR3_SPI1SEL_Msk +#define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000400 */ + +#define RCC_CCIPR3_SAI1SEL_Pos (16U) +#define RCC_CCIPR3_SAI1SEL_Msk (0x7UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR3_SAI1SEL RCC_CCIPR3_SAI1SEL_Msk +#define RCC_CCIPR3_SAI1SEL_0 (0x1UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR3_SAI1SEL_1 (0x2UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR3_SAI1SEL_2 (0x4UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00040000 */ + +#define RCC_CCIPR3_SAI2SEL_Pos (20U) +#define RCC_CCIPR3_SAI2SEL_Msk (0x7UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR3_SAI2SEL RCC_CCIPR3_SAI2SEL_Msk +#define RCC_CCIPR3_SAI2SEL_0 (0x1UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR3_SAI2SEL_1 (0x2UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR3_SAI2SEL_2 (0x4UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for RCC_CCIPR4 register ************/ +#define RCC_CCIPR4_LPUART1SEL_Pos (0U) +#define RCC_CCIPR4_LPUART1SEL_Msk (0x7UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR4_LPUART1SEL RCC_CCIPR4_LPUART1SEL_Msk +#define RCC_CCIPR4_LPUART1SEL_0 (0x1UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR4_LPUART1SEL_1 (0x2UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR4_LPUART1SEL_2 (0x4UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR4_SPI6SEL_Pos (4U) +#define RCC_CCIPR4_SPI6SEL_Msk (0x7UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR4_SPI6SEL RCC_CCIPR4_SPI6SEL_Msk +#define RCC_CCIPR4_SPI6SEL_0 (0x1UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR4_SPI6SEL_1 (0x2UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR4_SPI6SEL_2 (0x4UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR4_LPTIM23SEL_Pos (8U) +#define RCC_CCIPR4_LPTIM23SEL_Msk (0x7UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR4_LPTIM23SEL RCC_CCIPR4_LPTIM23SEL_Msk +#define RCC_CCIPR4_LPTIM23SEL_0 (0x1UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR4_LPTIM23SEL_1 (0x2UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR4_LPTIM23SEL_2 (0x4UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000400 */ + +#define RCC_CCIPR4_LPTIM45SEL_Pos (12U) +#define RCC_CCIPR4_LPTIM45SEL_Msk (0x7UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR4_LPTIM45SEL RCC_CCIPR4_LPTIM45SEL_Msk +#define RCC_CCIPR4_LPTIM45SEL_0 (0x1UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR4_LPTIM45SEL_1 (0x2UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR4_LPTIM45SEL_2 (0x4UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_CIER register ******************/ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk +#define RCC_CIER_HSIRDYIE_Pos (2U) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk +#define RCC_CIER_HSERDYIE_Pos (3U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk +#define RCC_CIER_CSIRDYIE_Pos (4U) +#define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk +#define RCC_CIER_HSI48RDYIE_Pos (5U) +#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk +#define RCC_CIER_PLL1RDYIE_Pos (6U) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk +#define RCC_CIER_PLL2RDYIE_Pos (7U) +#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk +#define RCC_CIER_PLL3RDYIE_Pos (8U) +#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk +#define RCC_CIER_LSECSSIE_Pos (9U) +#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */ +#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk + +/******************** Bit definition for RCC_CIFR register ******************/ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk +#define RCC_CIFR_HSIRDYF_Pos (2U) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk +#define RCC_CIFR_HSERDYF_Pos (3U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk +#define RCC_CIFR_CSIRDYF_Pos (4U) +#define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk +#define RCC_CIFR_HSI48RDYF_Pos (5U) +#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk +#define RCC_CIFR_PLL1RDYF_Pos (6U) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk +#define RCC_CIFR_PLL2RDYF_Pos (7U) +#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk +#define RCC_CIFR_PLL3RDYF_Pos (8U) +#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk +#define RCC_CIFR_LSECSSF_Pos (9U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk + +/******************** Bit definition for RCC_CICR register ******************/ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk +#define RCC_CICR_HSIRDYC_Pos (2U) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk +#define RCC_CICR_HSERDYC_Pos (3U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk +#define RCC_CICR_CSIRDYC_Pos (4U) +#define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk +#define RCC_CICR_HSI48RDYC_Pos (5U) +#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk +#define RCC_CICR_PLL1RDYC_Pos (6U) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk +#define RCC_CICR_PLL2RDYC_Pos (7U) +#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk +#define RCC_CICR_PLL3RDYC_Pos (8U) +#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk +#define RCC_CICR_LSECSSC_Pos (9U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk + +/******************** Bit definition for RCC_BDCR register ******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk +#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk +#define RCC_BDCR_LSEDRV_Pos (3U) +#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk +#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ + +#define RCC_BDCR_LSECSSON_Pos (5U) +#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk +#define RCC_BDCR_LSECSSD_Pos (6U) +#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk +#define RCC_BDCR_LSEEXT_Pos (7U) +#define RCC_BDCR_LSEEXT_Msk (0x1UL << RCC_BDCR_LSEEXT_Pos) /*!< 0x00000080 */ +#define RCC_BDCR_LSEEXT RCC_BDCR_LSEEXT_Msk +#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk +#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSRA_Pos (12U) +#define RCC_BDCR_LSECSSRA_Msk (0x1UL << RCC_BDCR_LSECSSRA_Pos) /*!< 0x00001000 */ +#define RCC_BDCR_LSECSSRA RCC_BDCR_LSECSSRA_Msk + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk +#define RCC_BDCR_VSWRST_Pos (16U) +#define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk + +/******************** Bit definition for RCC_AHB1RSTR register **************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (4U) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk +#define RCC_AHB1RSTR_ADC12RST_Pos (5U) +#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk +#define RCC_AHB1RSTR_ETH1RST_Pos (15U) +#define RCC_AHB1RSTR_ETH1RST_Msk (0x1UL << RCC_AHB1RSTR_ETH1RST_Pos) /*!< 0x00008000 */ +#define RCC_AHB1RSTR_ETH1RST RCC_AHB1RSTR_ETH1RST_Msk +#define RCC_AHB1RSTR_OTGHSRST_Pos (25U) +#define RCC_AHB1RSTR_OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHSRST_Pos) /*!< 0x02000000 */ +#define RCC_AHB1RSTR_OTGHSRST RCC_AHB1RSTR_OTGHSRST_Msk +#define RCC_AHB1RSTR_USBPHYCRST_Pos (26U) +#define RCC_AHB1RSTR_USBPHYCRST_Msk (0x1UL << RCC_AHB1RSTR_USBPHYCRST_Pos) /*!< 0x04000000 */ +#define RCC_AHB1RSTR_USBPHYCRST RCC_AHB1RSTR_USBPHYCRST_Msk +#define RCC_AHB1RSTR_OTGFSRST_Pos (27U) +#define RCC_AHB1RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_OTGFSRST_Pos) /*!< 0x08000000 */ +#define RCC_AHB1RSTR_OTGFSRST RCC_AHB1RSTR_OTGFSRST_Msk +#define RCC_AHB1RSTR_ADF1RST_Pos (31U) +#define RCC_AHB1RSTR_ADF1RST_Msk (0x1UL << RCC_AHB1RSTR_ADF1RST_Pos) /*!< 0x80000000 */ +#define RCC_AHB1RSTR_ADF1RST RCC_AHB1RSTR_ADF1RST_Msk + +/******************** Bit definition for RCC_AHB2RSTR register **************/ +#define RCC_AHB2RSTR_PSSIRST_Pos (1U) +#define RCC_AHB2RSTR_PSSIRST_Msk (0x1UL << RCC_AHB2RSTR_PSSIRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_PSSIRST RCC_AHB2RSTR_PSSIRST_Msk +#define RCC_AHB2RSTR_SDMMC2RST_Pos (9U) +#define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) /*!< 0x00000200 */ +#define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk +#define RCC_AHB2RSTR_CORDICRST_Pos (14U) +#define RCC_AHB2RSTR_CORDICRST_Msk (0x1UL << RCC_AHB2RSTR_CORDICRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB2RSTR_CORDICRST RCC_AHB2RSTR_CORDICRST_Msk + +/******************** Bit definition for RCC_AHB3RSTR register **************/ +#define RCC_AHB3RSTR_RNGRST_Pos (0U) +#define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk +#define RCC_AHB3RSTR_HASHRST_Pos (1U) +#define RCC_AHB3RSTR_HASHRST_Msk (0x1UL << RCC_AHB3RSTR_HASHRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTR_HASHRST RCC_AHB3RSTR_HASHRST_Msk +#define RCC_AHB3RSTR_CRYPRST_Pos (2U) +#define RCC_AHB3RSTR_CRYPRST_Msk (0x1UL << RCC_AHB3RSTR_CRYPRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB3RSTR_CRYPRST RCC_AHB3RSTR_CRYPRST_Msk +#define RCC_AHB3RSTR_SAESRST_Pos (4U) +#define RCC_AHB3RSTR_SAESRST_Msk (0x1UL << RCC_AHB3RSTR_SAESRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTR_SAESRST RCC_AHB3RSTR_SAESRST_Msk +#define RCC_AHB3RSTR_PKARST_Pos (6U) +#define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk + +/******************** Bit definition for RCC_AHB4RSTR register **************/ +#define RCC_AHB4RSTR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk +#define RCC_AHB4RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk +#define RCC_AHB4RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk +#define RCC_AHB4RSTR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk +#define RCC_AHB4RSTR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk +#define RCC_AHB4RSTR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk +#define RCC_AHB4RSTR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk +#define RCC_AHB4RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk +#define RCC_AHB4RSTR_GPIOMRST_Pos (12U) +#define RCC_AHB4RSTR_GPIOMRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOMRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB4RSTR_GPIOMRST RCC_AHB4RSTR_GPIOMRST_Msk +#define RCC_AHB4RSTR_GPIONRST_Pos (13U) +#define RCC_AHB4RSTR_GPIONRST_Msk (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB4RSTR_GPIONRST RCC_AHB4RSTR_GPIONRST_Msk +#define RCC_AHB4RSTR_GPIOORST_Pos (14U) +#define RCC_AHB4RSTR_GPIOORST_Msk (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos) /*!< 0x00004000 */ +#define RCC_AHB4RSTR_GPIOORST RCC_AHB4RSTR_GPIOORST_Msk +#define RCC_AHB4RSTR_GPIOPRST_Pos (15U) +#define RCC_AHB4RSTR_GPIOPRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos) /*!< 0x00008000 */ +#define RCC_AHB4RSTR_GPIOPRST RCC_AHB4RSTR_GPIOPRST_Msk +#define RCC_AHB4RSTR_CRCRST_Pos (19U) +#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk + +/******************** Bit definition for RCC_AHB5RSTR register **************/ +#define RCC_AHB5RSTR_HPDMA1RST_Pos (0U) +#define RCC_AHB5RSTR_HPDMA1RST_Msk (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_HPDMA1RST RCC_AHB5RSTR_HPDMA1RST_Msk +#define RCC_AHB5RSTR_DMA2DRST_Pos (1U) +#define RCC_AHB5RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB5RSTR_DMA2DRST RCC_AHB5RSTR_DMA2DRST_Msk +#define RCC_AHB5RSTR_JPEGRST_Pos (3U) +#define RCC_AHB5RSTR_JPEGRST_Msk (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTR_JPEGRST RCC_AHB5RSTR_JPEGRST_Msk +#define RCC_AHB5RSTR_FMCRST_Pos (4U) +#define RCC_AHB5RSTR_FMCRST_Msk (0x1UL << RCC_AHB5RSTR_FMCRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTR_FMCRST RCC_AHB5RSTR_FMCRST_Msk +#define RCC_AHB5RSTR_XSPI1RST_Pos (5U) +#define RCC_AHB5RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTR_XSPI1RST RCC_AHB5RSTR_XSPI1RST_Msk +#define RCC_AHB5RSTR_SDMMC1RST_Pos (8U) +#define RCC_AHB5RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTR_SDMMC1RST RCC_AHB5RSTR_SDMMC1RST_Msk +#define RCC_AHB5RSTR_XSPI2RST_Pos (12U) +#define RCC_AHB5RSTR_XSPI2RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos) /*!< 0x00001000 */ +#define RCC_AHB5RSTR_XSPI2RST RCC_AHB5RSTR_XSPI2RST_Msk +#define RCC_AHB5RSTR_XSPIMRST_Pos (14U) +#define RCC_AHB5RSTR_XSPIMRST_Msk (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB5RSTR_XSPIMRST RCC_AHB5RSTR_XSPIMRST_Msk +#define RCC_AHB5RSTR_GFXMMURST_Pos (19U) +#define RCC_AHB5RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTR_GFXMMURST RCC_AHB5RSTR_GFXMMURST_Msk +#define RCC_AHB5RSTR_GPU2DRST_Pos (20U) +#define RCC_AHB5RSTR_GPU2DRST_Msk (0x1UL << RCC_AHB5RSTR_GPU2DRST_Pos) /*!< 0x00100000 */ +#define RCC_AHB5RSTR_GPU2DRST RCC_AHB5RSTR_GPU2DRST_Msk + +/******************** Bit definition for RCC_APB1RSTR1 register *************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0U) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk +#define RCC_APB1RSTR1_TIM3RST_Pos (1U) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk +#define RCC_APB1RSTR1_TIM4RST_Pos (2U) +#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk +#define RCC_APB1RSTR1_TIM5RST_Pos (3U) +#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk +#define RCC_APB1RSTR1_TIM6RST_Pos (4U) +#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk +#define RCC_APB1RSTR1_TIM7RST_Pos (5U) +#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk +#define RCC_APB1RSTR1_TIM12RST_Pos (6U) +#define RCC_APB1RSTR1_TIM12RST_Msk (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTR1_TIM12RST RCC_APB1RSTR1_TIM12RST_Msk +#define RCC_APB1RSTR1_TIM13RST_Pos (7U) +#define RCC_APB1RSTR1_TIM13RST_Msk (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTR1_TIM13RST RCC_APB1RSTR1_TIM13RST_Msk +#define RCC_APB1RSTR1_TIM14RST_Pos (8U) +#define RCC_APB1RSTR1_TIM14RST_Msk (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR1_TIM14RST RCC_APB1RSTR1_TIM14RST_Msk +#define RCC_APB1RSTR1_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk +#define RCC_APB1RSTR1_SPI2RST_Pos (14U) +#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk +#define RCC_APB1RSTR1_SPI3RST_Pos (15U) +#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk +#define RCC_APB1RSTR1_SPDIFRXRST_Pos (16U) +#define RCC_APB1RSTR1_SPDIFRXRST_Msk (0x1UL << RCC_APB1RSTR1_SPDIFRXRST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTR1_SPDIFRXRST RCC_APB1RSTR1_SPDIFRXRST_Msk +#define RCC_APB1RSTR1_USART2RST_Pos (17U) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk +#define RCC_APB1RSTR1_USART3RST_Pos (18U) +#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk +#define RCC_APB1RSTR1_UART4RST_Pos (19U) +#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk +#define RCC_APB1RSTR1_UART5RST_Pos (20U) +#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk +#define RCC_APB1RSTR1_I2C1_I3C1RST_Pos (21U) +#define RCC_APB1RSTR1_I2C1_I3C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1_I3C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1_I3C1RST RCC_APB1RSTR1_I2C1_I3C1RST_Msk +#define RCC_APB1RSTR1_I2C2RST_Pos (22U) +#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk +#define RCC_APB1RSTR1_I2C3RST_Pos (23U) +#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk +#define RCC_APB1RSTR1_CECRST_Pos (27U) +#define RCC_APB1RSTR1_CECRST_Msk (0x1UL << RCC_APB1RSTR1_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR1_CECRST RCC_APB1RSTR1_CECRST_Msk +#define RCC_APB1RSTR1_UART7RST_Pos (30U) +#define RCC_APB1RSTR1_UART7RST_Msk (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTR1_UART7RST RCC_APB1RSTR1_UART7RST_Msk +#define RCC_APB1RSTR1_UART8RST_Pos (31U) +#define RCC_APB1RSTR1_UART8RST_Msk (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR1_UART8RST RCC_APB1RSTR1_UART8RST_Msk + +/******************** Bit definition for RCC_APB1RSTR2 register *************/ +#define RCC_APB1RSTR2_CRSRST_Pos (1U) +#define RCC_APB1RSTR2_CRSRST_Msk (0x1UL << RCC_APB1RSTR2_CRSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR2_CRSRST RCC_APB1RSTR2_CRSRST_Msk +#define RCC_APB1RSTR2_MDIOSRST_Pos (5U) +#define RCC_APB1RSTR2_MDIOSRST_Msk (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_MDIOSRST RCC_APB1RSTR2_MDIOSRST_Msk +#define RCC_APB1RSTR2_FDCANRST_Pos (8U) +#define RCC_APB1RSTR2_FDCANRST_Msk (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR2_FDCANRST RCC_APB1RSTR2_FDCANRST_Msk +#define RCC_APB1RSTR2_UCPD1RST_Pos (27U) +#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk + +/******************** Bit definition for RCC_APB2RSTR register **************/ +#define RCC_APB2RSTR_TIM1RST_Pos (0U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk +#define RCC_APB2RSTR_USART1RST_Pos (4U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk +#define RCC_APB2RSTR_SPI4RST_Pos (13U) +#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk +#define RCC_APB2RSTR_TIM9RST_Pos (19U) +#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk +#define RCC_APB2RSTR_SPI5RST_Pos (20U) +#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk +#define RCC_APB2RSTR_SAI1RST_Pos (22U) +#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk +#define RCC_APB2RSTR_SAI2RST_Pos (23U) +#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */ +#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk + +/******************** Bit definition for RCC_APB4RSTR register **************/ +#define RCC_APB4RSTR_SBSRST_Pos (1U) +#define RCC_APB4RSTR_SBSRST_Msk (0x1UL << RCC_APB4RSTR_SBSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB4RSTR_SBSRST RCC_APB4RSTR_SBSRST_Msk +#define RCC_APB4RSTR_LPUART1RST_Pos (3U) +#define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk +#define RCC_APB4RSTR_SPI6RST_Pos (5U) +#define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk +#define RCC_APB4RSTR_LPTIM2RST_Pos (9U) +#define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk +#define RCC_APB4RSTR_LPTIM3RST_Pos (10U) +#define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk +#define RCC_APB4RSTR_LPTIM4RST_Pos (11U) +#define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk +#define RCC_APB4RSTR_LPTIM5RST_Pos (12U) +#define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk +#define RCC_APB4RSTR_VREFRST_Pos (15U) +#define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk +#define RCC_APB4RSTR_DTSRST_Pos (26U) +#define RCC_APB4RSTR_DTSRST_Msk (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */ +#define RCC_APB4RSTR_DTSRST RCC_APB4RSTR_DTSRST_Msk + +/******************** Bit definition for RCC_APB5RSTR register **************/ +#define RCC_APB5RSTR_LTDCRST_Pos (1U) +#define RCC_APB5RSTR_LTDCRST_Msk (0x1UL << RCC_APB5RSTR_LTDCRST_Pos) /*!< 0x00000002 */ +#define RCC_APB5RSTR_LTDCRST RCC_APB5RSTR_LTDCRST_Msk +#define RCC_APB5RSTR_DCMIPPRST_Pos (2U) +#define RCC_APB5RSTR_DCMIPPRST_Msk (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTR_DCMIPPRST RCC_APB5RSTR_DCMIPPRST_Msk +#define RCC_APB5RSTR_GFXTIMRST_Pos (4U) +#define RCC_APB5RSTR_GFXTIMRST_Msk (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTR_GFXTIMRST RCC_APB5RSTR_GFXTIMRST_Msk + +/******************** Bit definition for RCC_CKGDISR register ***************/ +#define RCC_CKGDISR_AXICKG_Pos (0U) +#define RCC_CKGDISR_AXICKG_Msk (0x1UL << RCC_CKGDISR_AXICKG_Pos) /*!< 0x00000001 */ +#define RCC_CKGDISR_AXICKG RCC_CKGDISR_AXICKG_Msk +#define RCC_CKGDISR_AHBMCKG_Pos (1U) +#define RCC_CKGDISR_AHBMCKG_Msk (0x1UL << RCC_CKGDISR_AHBMCKG_Pos) /*!< 0x00000002 */ +#define RCC_CKGDISR_AHBMCKG RCC_CKGDISR_AHBMCKG_Msk +#define RCC_CKGDISR_SDMMC1CKG_Pos (2U) +#define RCC_CKGDISR_SDMMC1CKG_Msk (0x1UL << RCC_CKGDISR_SDMMC1CKG_Pos) /*!< 0x00000004 */ +#define RCC_CKGDISR_SDMMC1CKG RCC_CKGDISR_SDMMC1CKG_Msk +#define RCC_CKGDISR_HPDMA1CKG_Pos (3U) +#define RCC_CKGDISR_HPDMA1CKG_Msk (0x1UL << RCC_CKGDISR_HPDMA1CKG_Pos) /*!< 0x00000008 */ +#define RCC_CKGDISR_HPDMA1CKG RCC_CKGDISR_HPDMA1CKG_Msk +#define RCC_CKGDISR_CPUCKG_Pos (4U) +#define RCC_CKGDISR_CPUCKG_Msk (0x1UL << RCC_CKGDISR_CPUCKG_Pos) /*!< 0x00000010 */ +#define RCC_CKGDISR_CPUCKG RCC_CKGDISR_CPUCKG_Msk +#define RCC_CKGDISR_GPU2DS0CKG_Pos (5U) +#define RCC_CKGDISR_GPU2DS0CKG_Msk (0x1UL << RCC_CKGDISR_GPU2DS0CKG_Pos) /*!< 0x00000020 */ +#define RCC_CKGDISR_GPU2DS0CKG RCC_CKGDISR_GPU2DS0CKG_Msk +#define RCC_CKGDISR_GPU2DS1CKG_Pos (6U) +#define RCC_CKGDISR_GPU2DS1CKG_Msk (0x1UL << RCC_CKGDISR_GPU2DS1CKG_Pos) /*!< 0x00000040 */ +#define RCC_CKGDISR_GPU2DS1CKG RCC_CKGDISR_GPU2DS1CKG_Msk +#define RCC_CKGDISR_GPU2DCLCKG_Pos (7U) +#define RCC_CKGDISR_GPU2DCLCKG_Msk (0x1UL << RCC_CKGDISR_GPU2DCLCKG_Pos) /*!< 0x00000080 */ +#define RCC_CKGDISR_GPU2DCLCKG RCC_CKGDISR_GPU2DCLCKG_Msk +#define RCC_CKGDISR_DCMIPPCKG_Pos (8U) +#define RCC_CKGDISR_DCMIPPCKG_Msk (0x1UL << RCC_CKGDISR_DCMIPPCKG_Pos) /*!< 0x00000100 */ +#define RCC_CKGDISR_DCMIPPCKG RCC_CKGDISR_DCMIPPCKG_Msk +#define RCC_CKGDISR_DMA2DCKG_Pos (9U) +#define RCC_CKGDISR_DMA2DCKG_Msk (0x1UL << RCC_CKGDISR_DMA2DCKG_Pos) /*!< 0x00000200 */ +#define RCC_CKGDISR_DMA2DCKG RCC_CKGDISR_DMA2DCKG_Msk +#define RCC_CKGDISR_GFXMMUSCKG_Pos (10U) +#define RCC_CKGDISR_GFXMMUSCKG_Msk (0x1UL << RCC_CKGDISR_GFXMMUSCKG_Pos) /*!< 0x00000400 */ +#define RCC_CKGDISR_GFXMMUSCKG RCC_CKGDISR_GFXMMUSCKG_Msk +#define RCC_CKGDISR_LTDCCKG_Pos (11U) +#define RCC_CKGDISR_LTDCCKG_Msk (0x1UL << RCC_CKGDISR_LTDCCKG_Pos) /*!< 0x00000800 */ +#define RCC_CKGDISR_LTDCCKG RCC_CKGDISR_LTDCCKG_Msk +#define RCC_CKGDISR_GFXMMUMCKG_Pos (12U) +#define RCC_CKGDISR_GFXMMUMCKG_Msk (0x1UL << RCC_CKGDISR_GFXMMUMCKG_Pos) /*!< 0x00001000 */ +#define RCC_CKGDISR_GFXMMUMCKG RCC_CKGDISR_GFXMMUMCKG_Msk +#define RCC_CKGDISR_AHBSCKG_Pos (13U) +#define RCC_CKGDISR_AHBSCKG_Msk (0x1UL << RCC_CKGDISR_AHBSCKG_Pos) /*!< 0x00002000 */ +#define RCC_CKGDISR_AHBSCKG RCC_CKGDISR_AHBSCKG_Msk +#define RCC_CKGDISR_FMCCKG_Pos (14U) +#define RCC_CKGDISR_FMCCKG_Msk (0x1UL << RCC_CKGDISR_FMCCKG_Pos) /*!< 0x00004000 */ +#define RCC_CKGDISR_FMCCKG RCC_CKGDISR_FMCCKG_Msk +#define RCC_CKGDISR_XSPI1CKG_Pos (15U) +#define RCC_CKGDISR_XSPI1CKG_Msk (0x1UL << RCC_CKGDISR_XSPI1CKG_Pos) /*!< 0x00008000 */ +#define RCC_CKGDISR_XSPI1CKG RCC_CKGDISR_XSPI1CKG_Msk +#define RCC_CKGDISR_XSPI2CKG_Pos (16U) +#define RCC_CKGDISR_XSPI2CKG_Msk (0x1UL << RCC_CKGDISR_XSPI2CKG_Pos) /*!< 0x00010000 */ +#define RCC_CKGDISR_XSPI2CKG RCC_CKGDISR_XSPI2CKG_Msk +#define RCC_CKGDISR_AXISRAM4CKG_Pos (17U) +#define RCC_CKGDISR_AXISRAM4CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM4CKG_Pos) /*!< 0x00020000 */ +#define RCC_CKGDISR_AXISRAM4CKG RCC_CKGDISR_AXISRAM4CKG_Msk +#define RCC_CKGDISR_AXISRAM3CKG_Pos (18U) +#define RCC_CKGDISR_AXISRAM3CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM3CKG_Pos) /*!< 0x00040000 */ +#define RCC_CKGDISR_AXISRAM3CKG RCC_CKGDISR_AXISRAM3CKG_Msk +#define RCC_CKGDISR_AXISRAM2CKG_Pos (19U) +#define RCC_CKGDISR_AXISRAM2CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM2CKG_Pos) /*!< 0x00080000 */ +#define RCC_CKGDISR_AXISRAM2CKG RCC_CKGDISR_AXISRAM2CKG_Msk +#define RCC_CKGDISR_AXISRAM1CKG_Pos (20U) +#define RCC_CKGDISR_AXISRAM1CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM1CKG_Pos) /*!< 0x00100000 */ +#define RCC_CKGDISR_AXISRAM1CKG RCC_CKGDISR_AXISRAM1CKG_Msk +#define RCC_CKGDISR_FLASHCKG_Pos (21U) +#define RCC_CKGDISR_FLASHCKG_Msk (0x1UL << RCC_CKGDISR_FLASHCKG_Pos) /*!< 0x00200000 */ +#define RCC_CKGDISR_FLASHCKG RCC_CKGDISR_FLASHCKG_Msk +#define RCC_CKGDISR_EXTICKG_Pos (30U) +#define RCC_CKGDISR_EXTICKG_Msk (0x1UL << RCC_CKGDISR_EXTICKG_Pos) /*!< 0x40000000 */ +#define RCC_CKGDISR_EXTICKG RCC_CKGDISR_EXTICKG_Msk +#define RCC_CKGDISR_JTAGCKG_Pos (31U) +#define RCC_CKGDISR_JTAGCKG_Msk (0x1UL << RCC_CKGDISR_JTAGCKG_Pos) /*!< 0x80000000 */ +#define RCC_CKGDISR_JTAGCKG RCC_CKGDISR_JTAGCKG_Msk + +/******************** Bit definition for RCC_PLL1DIVR2 register *************/ +#define RCC_PLL1DIVR2_DIVS_Pos (0U) +#define RCC_PLL1DIVR2_DIVS_Msk (0x7UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL1DIVR2_DIVS RCC_PLL1DIVR2_DIVS_Msk /*!< DIVS1[2:0] bits: PLL1 DIVS division factor */ +#define RCC_PLL1DIVR2_DIVS_0 (0x1UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR2_DIVS_1 (0x2UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR2_DIVS_2 (0x4UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for RCC_PLL2DIVR2 register *************/ +#define RCC_PLL2DIVR2_DIVS_Pos (0U) +#define RCC_PLL2DIVR2_DIVS_Msk (0x7UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL2DIVR2_DIVS RCC_PLL2DIVR2_DIVS_Msk /*!< DIVS2[2:0] bits: PLL2 DIVS division factor */ +#define RCC_PLL2DIVR2_DIVS_0 (0x1UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL2DIVR2_DIVS_1 (0x2UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL2DIVR2_DIVS_2 (0x4UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +#define RCC_PLL2DIVR2_DIVT_Pos (8U) +#define RCC_PLL2DIVR2_DIVT_Msk (0x7UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000700 */ +#define RCC_PLL2DIVR2_DIVT RCC_PLL2DIVR2_DIVT_Msk /*!< DIVT2[2:0] bits: PLL2 DIVT division factor */ +#define RCC_PLL2DIVR2_DIVT_0 (0x1UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000100 */ +#define RCC_PLL2DIVR2_DIVT_1 (0x2UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000200 */ +#define RCC_PLL2DIVR2_DIVT_2 (0x4UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for RCC_PLL3DIVR2 register *************/ +#define RCC_PLL3DIVR2_DIVS_Pos (0U) +#define RCC_PLL3DIVR2_DIVS_Msk (0x7UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL3DIVR2_DIVS RCC_PLL3DIVR2_DIVS_Msk /*!< DIVS3[2:0] bits: PLL3 DIVS division factor */ +#define RCC_PLL3DIVR2_DIVS_0 (0x1UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL3DIVR2_DIVS_1 (0x2UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL3DIVR2_DIVS_2 (0x4UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for RCC_PLL1SSCGR register *************/ +#define RCC_PLL1SSCGR_MODPER_Pos (0U) +#define RCC_PLL1SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1SSCGR_MODPER RCC_PLL1SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL1SSCGR_MODPER_0 (0x0001UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1SSCGR_MODPER_1 (0x0002UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1SSCGR_MODPER_2 (0x0004UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1SSCGR_MODPER_3 (0x0008UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1SSCGR_MODPER_4 (0x0010UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1SSCGR_MODPER_5 (0x0020UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1SSCGR_MODPER_6 (0x0040UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1SSCGR_MODPER_7 (0x0080UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1SSCGR_MODPER_8 (0x0100UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1SSCGR_MODPER_9 (0x0200UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1SSCGR_MODPER_10 (0x0400UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1SSCGR_MODPER_11 (0x0800UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1SSCGR_MODPER_12 (0x1000UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL1SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL1SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1SSCGR_TPDFNDIS RCC_PLL1SSCGR_TPDFNDIS_Msk +#define RCC_PLL1SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL1SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL1SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1SSCGR_RPDFNDIS RCC_PLL1SSCGR_RPDFNDIS_Msk +#define RCC_PLL1SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL1SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL1SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL1SSCGR_SPREADSEL RCC_PLL1SSCGR_SPREADSEL_Msk +#define RCC_PLL1SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL1SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1SSCGR_INCSTEP RCC_PLL1SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL1SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL2SSCGR register *************/ +#define RCC_PLL2SSCGR_MODPER_Pos (0U) +#define RCC_PLL2SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2SSCGR_MODPER RCC_PLL2SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL2SSCGR_MODPER_0 (0x0001UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2SSCGR_MODPER_1 (0x0002UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2SSCGR_MODPER_2 (0x0004UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2SSCGR_MODPER_3 (0x0008UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2SSCGR_MODPER_4 (0x0010UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2SSCGR_MODPER_5 (0x0020UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2SSCGR_MODPER_6 (0x0040UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2SSCGR_MODPER_7 (0x0080UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2SSCGR_MODPER_8 (0x0100UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2SSCGR_MODPER_9 (0x0200UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2SSCGR_MODPER_10 (0x0400UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2SSCGR_MODPER_11 (0x0800UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2SSCGR_MODPER_12 (0x1000UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL2SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL2SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2SSCGR_TPDFNDIS RCC_PLL2SSCGR_TPDFNDIS_Msk +#define RCC_PLL2SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL2SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL2SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2SSCGR_RPDFNDIS RCC_PLL2SSCGR_RPDFNDIS_Msk +#define RCC_PLL2SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL2SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL2SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL2SSCGR_SPREADSEL RCC_PLL2SSCGR_SPREADSEL_Msk +#define RCC_PLL2SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL2SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2SSCGR_INCSTEP RCC_PLL2SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL2SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL3SSCGR register *************/ +#define RCC_PLL3SSCGR_MODPER_Pos (0U) +#define RCC_PLL3SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL3SSCGR_MODPER RCC_PLL3SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL3SSCGR_MODPER_0 (0x0001UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL3SSCGR_MODPER_1 (0x0002UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL3SSCGR_MODPER_2 (0x0004UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL3SSCGR_MODPER_3 (0x0008UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL3SSCGR_MODPER_4 (0x0010UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL3SSCGR_MODPER_5 (0x0020UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL3SSCGR_MODPER_6 (0x0040UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL3SSCGR_MODPER_7 (0x0080UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL3SSCGR_MODPER_8 (0x0100UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL3SSCGR_MODPER_9 (0x0200UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL3SSCGR_MODPER_10 (0x0400UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL3SSCGR_MODPER_11 (0x0800UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL3SSCGR_MODPER_12 (0x1000UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL3SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL3SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL3SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL3SSCGR_TPDFNDIS RCC_PLL3SSCGR_TPDFNDIS_Msk +#define RCC_PLL3SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL3SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL3SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL3SSCGR_RPDFNDIS RCC_PLL3SSCGR_RPDFNDIS_Msk +#define RCC_PLL3SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL3SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL3SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL3SSCGR_SPREADSEL RCC_PLL3SSCGR_SPREADSEL_Msk +#define RCC_PLL3SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL3SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3SSCGR_INCSTEP RCC_PLL3SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL3SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL3SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL3SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL3SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL3SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL3SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL3SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL3SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL3SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL3SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL3SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL3SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL3SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL3SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL3SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CKPROTR register ***************/ +#define RCC_CKPROTR_XSPICKP_Pos (0U) +#define RCC_CKPROTR_XSPICKP_Msk (0x1UL << RCC_CKPROTR_XSPICKP_Pos) /*!< 0x00000001 */ +#define RCC_CKPROTR_XSPICKP RCC_CKPROTR_XSPICKP_Msk +#define RCC_CKPROTR_FMCCKP_Pos (1U) +#define RCC_CKPROTR_FMCCKP_Msk (0x1UL << RCC_CKPROTR_FMCCKP_Pos) /*!< 0x00000002 */ +#define RCC_CKPROTR_FMCCKP RCC_CKPROTR_FMCCKP_Msk +#define RCC_CKPROTR_XSPI1SWP_Pos (4U) +#define RCC_CKPROTR_XSPI1SWP_Msk (0x7UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000070 */ +#define RCC_CKPROTR_XSPI1SWP RCC_CKPROTR_XSPI1SWP_Msk +#define RCC_CKPROTR_XSPI1SWP_0 (0x1UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000010 */ +#define RCC_CKPROTR_XSPI1SWP_1 (0x2UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000020 */ +#define RCC_CKPROTR_XSPI1SWP_2 (0x4UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000040 */ +#define RCC_CKPROTR_XSPI2SWP_Pos (8U) +#define RCC_CKPROTR_XSPI2SWP_Msk (0x7UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000700 */ +#define RCC_CKPROTR_XSPI2SWP RCC_CKPROTR_XSPI2SWP_Msk +#define RCC_CKPROTR_XSPI2SWP_0 (0x1UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000100 */ +#define RCC_CKPROTR_XSPI2SWP_1 (0x2UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000200 */ +#define RCC_CKPROTR_XSPI2SWP_2 (0x4UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000400 */ +#define RCC_CKPROTR_FMCSWP_Pos (12U) +#define RCC_CKPROTR_FMCSWP_Msk (0x7UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00007000 */ +#define RCC_CKPROTR_FMCSWP RCC_CKPROTR_FMCSWP_Msk +#define RCC_CKPROTR_FMCSWP_0 (0x1UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00001000 */ +#define RCC_CKPROTR_FMCSWP_1 (0x2UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00002000 */ +#define RCC_CKPROTR_FMCSWP_2 (0x4UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_RSR register *******************/ +#define RCC_RSR_RMVF_Pos (16U) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk +#define RCC_RSR_OBLRSTF_Pos (17U) +#define RCC_RSR_OBLRSTF_Msk (0x1UL << RCC_RSR_OBLRSTF_Pos) /*!< 0x00020000 */ +#define RCC_RSR_OBLRSTF RCC_RSR_OBLRSTF_Msk +#define RCC_RSR_BORRSTF_Pos (21U) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk +#define RCC_RSR_PINRSTF_Pos (22U) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk +#define RCC_RSR_PORRSTF_Pos (23U) +#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk +#define RCC_RSR_SFTRSTF_Pos (24U) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk +#define RCC_RSR_IWDGRSTF_Pos (26U) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk +#define RCC_RSR_WWDGRSTF_Pos (28U) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk +#define RCC_RSR_LPWRRSTF_Pos (30U) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk + +/******************** Bit definition for RCC_AHB1ENR register ***************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (4U) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk +#define RCC_AHB1ENR_ADC12EN_Pos (5U) +#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk +#define RCC_AHB1ENR_ETH1MACEN_Pos (15U) +#define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk +#define RCC_AHB1ENR_ETH1TXEN_Pos (16U) +#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk +#define RCC_AHB1ENR_ETH1RXEN_Pos (17U) +#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk +#define RCC_AHB1ENR_OTGHSEN_Pos (25U) +#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk +#define RCC_AHB1ENR_USBPHYCEN_Pos (26U) +#define RCC_AHB1ENR_USBPHYCEN_Msk (0x1UL << RCC_AHB1ENR_USBPHYCEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB1ENR_USBPHYCEN RCC_AHB1ENR_USBPHYCEN_Msk +#define RCC_AHB1ENR_OTGFSEN_Pos (27U) +#define RCC_AHB1ENR_OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_OTGFSEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB1ENR_OTGFSEN RCC_AHB1ENR_OTGFSEN_Msk +#define RCC_AHB1ENR_ADF1EN_Pos (31U) +#define RCC_AHB1ENR_ADF1EN_Msk (0x1UL << RCC_AHB1ENR_ADF1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_ADF1EN RCC_AHB1ENR_ADF1EN_Msk + +/******************** Bit definition for RCC_AHB2ENR register ***************/ +#define RCC_AHB2ENR_PSSIEN_Pos (1U) +#define RCC_AHB2ENR_PSSIEN_Msk (0x1UL << RCC_AHB2ENR_PSSIEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_PSSIEN RCC_AHB2ENR_PSSIEN_Msk +#define RCC_AHB2ENR_SDMMC2EN_Pos (9U) +#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */ +#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk +#define RCC_AHB2ENR_CORDICEN_Pos (14U) +#define RCC_AHB2ENR_CORDICEN_Msk (0x1UL << RCC_AHB2ENR_CORDICEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB2ENR_CORDICEN RCC_AHB2ENR_CORDICEN_Msk +#define RCC_AHB2ENR_SRAM1EN_Pos (29U) +#define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos) /*!< 0x20000000 */ +#define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk +#define RCC_AHB2ENR_SRAM2EN_Pos (30U) +#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk + +/******************** Bit definition for RCC_AHB3ENR register ***************/ +#define RCC_AHB3ENR_RNGEN_Pos (0U) +#define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk +#define RCC_AHB3ENR_HASHEN_Pos (1U) +#define RCC_AHB3ENR_HASHEN_Msk (0x1UL << RCC_AHB3ENR_HASHEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENR_HASHEN RCC_AHB3ENR_HASHEN_Msk +#define RCC_AHB3ENR_CRYPEN_Pos (2U) +#define RCC_AHB3ENR_CRYPEN_Msk (0x1UL << RCC_AHB3ENR_CRYPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB3ENR_CRYPEN RCC_AHB3ENR_CRYPEN_Msk +#define RCC_AHB3ENR_SAESEN_Pos (4U) +#define RCC_AHB3ENR_SAESEN_Msk (0x1UL << RCC_AHB3ENR_SAESEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB3ENR_SAESEN RCC_AHB3ENR_SAESEN_Msk +#define RCC_AHB3ENR_PKAEN_Pos (6U) +#define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk + +/******************** Bit definition for RCC_AHB4ENR register ***************/ +#define RCC_AHB4ENR_GPIOAEN_Pos (0U) +#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk +#define RCC_AHB4ENR_GPIOBEN_Pos (1U) +#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk +#define RCC_AHB4ENR_GPIOCEN_Pos (2U) +#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk +#define RCC_AHB4ENR_GPIODEN_Pos (3U) +#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk +#define RCC_AHB4ENR_GPIOEEN_Pos (4U) +#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk +#define RCC_AHB4ENR_GPIOFEN_Pos (5U) +#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk +#define RCC_AHB4ENR_GPIOGEN_Pos (6U) +#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk +#define RCC_AHB4ENR_GPIOHEN_Pos (7U) +#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk +#define RCC_AHB4ENR_GPIOMEN_Pos (12U) +#define RCC_AHB4ENR_GPIOMEN_Msk (0x1UL << RCC_AHB4ENR_GPIOMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB4ENR_GPIOMEN RCC_AHB4ENR_GPIOMEN_Msk +#define RCC_AHB4ENR_GPIONEN_Pos (13U) +#define RCC_AHB4ENR_GPIONEN_Msk (0x1UL << RCC_AHB4ENR_GPIONEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENR_GPIONEN RCC_AHB4ENR_GPIONEN_Msk +#define RCC_AHB4ENR_GPIOOEN_Pos (14U) +#define RCC_AHB4ENR_GPIOOEN_Msk (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENR_GPIOOEN RCC_AHB4ENR_GPIOOEN_Msk +#define RCC_AHB4ENR_GPIOPEN_Pos (15U) +#define RCC_AHB4ENR_GPIOPEN_Msk (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENR_GPIOPEN RCC_AHB4ENR_GPIOPEN_Msk +#define RCC_AHB4ENR_CRCEN_Pos (19U) +#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk +#define RCC_AHB4ENR_BKPRAMEN_Pos (28U) +#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk + +/******************** Bit definition for RCC_AHB5ENR register ***************/ +#define RCC_AHB5ENR_HPDMA1EN_Pos (0U) +#define RCC_AHB5ENR_HPDMA1EN_Msk (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_HPDMA1EN RCC_AHB5ENR_HPDMA1EN_Msk +#define RCC_AHB5ENR_DMA2DEN_Pos (1U) +#define RCC_AHB5ENR_DMA2DEN_Msk (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENR_DMA2DEN RCC_AHB5ENR_DMA2DEN_Msk +#define RCC_AHB5ENR_JPEGEN_Pos (3U) +#define RCC_AHB5ENR_JPEGEN_Msk (0x1UL << RCC_AHB5ENR_JPEGEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENR_JPEGEN RCC_AHB5ENR_JPEGEN_Msk +#define RCC_AHB5ENR_FMCEN_Pos (4U) +#define RCC_AHB5ENR_FMCEN_Msk (0x1UL << RCC_AHB5ENR_FMCEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENR_FMCEN RCC_AHB5ENR_FMCEN_Msk +#define RCC_AHB5ENR_XSPI1EN_Pos (5U) +#define RCC_AHB5ENR_XSPI1EN_Msk (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENR_XSPI1EN RCC_AHB5ENR_XSPI1EN_Msk +#define RCC_AHB5ENR_SDMMC1EN_Pos (8U) +#define RCC_AHB5ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENR_SDMMC1EN RCC_AHB5ENR_SDMMC1EN_Msk +#define RCC_AHB5ENR_XSPI2EN_Pos (12U) +#define RCC_AHB5ENR_XSPI2EN_Msk (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENR_XSPI2EN RCC_AHB5ENR_XSPI2EN_Msk +#define RCC_AHB5ENR_XSPIMEN_Pos (14U) +#define RCC_AHB5ENR_XSPIMEN_Msk (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5ENR_XSPIMEN RCC_AHB5ENR_XSPIMEN_Msk +#define RCC_AHB5ENR_GFXMMUEN_Pos (19U) +#define RCC_AHB5ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENR_GFXMMUEN RCC_AHB5ENR_GFXMMUEN_Msk +#define RCC_AHB5ENR_GPU2DEN_Pos (20U) +#define RCC_AHB5ENR_GPU2DEN_Msk (0x1UL << RCC_AHB5ENR_GPU2DEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB5ENR_GPU2DEN RCC_AHB5ENR_GPU2DEN_Msk + +/******************** Bit definition for RCC_APB1ENR1 register **************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0U) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk +#define RCC_APB1ENR1_TIM3EN_Pos (1U) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk +#define RCC_APB1ENR1_TIM4EN_Pos (2U) +#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk +#define RCC_APB1ENR1_TIM5EN_Pos (3U) +#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk +#define RCC_APB1ENR1_TIM6EN_Pos (4U) +#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk +#define RCC_APB1ENR1_TIM7EN_Pos (5U) +#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk +#define RCC_APB1ENR1_TIM12EN_Pos (6U) +#define RCC_APB1ENR1_TIM12EN_Msk (0x1UL << RCC_APB1ENR1_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENR1_TIM12EN RCC_APB1ENR1_TIM12EN_Msk +#define RCC_APB1ENR1_TIM13EN_Pos (7U) +#define RCC_APB1ENR1_TIM13EN_Msk (0x1UL << RCC_APB1ENR1_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENR1_TIM13EN RCC_APB1ENR1_TIM13EN_Msk +#define RCC_APB1ENR1_TIM14EN_Pos (8U) +#define RCC_APB1ENR1_TIM14EN_Msk (0x1UL << RCC_APB1ENR1_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR1_TIM14EN RCC_APB1ENR1_TIM14EN_Msk +#define RCC_APB1ENR1_LPTIM1EN_Pos (9U) +#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk +#define RCC_APB1ENR1_WWDGEN_Pos (11U) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk +#define RCC_APB1ENR1_SPI2EN_Pos (14U) +#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk +#define RCC_APB1ENR1_SPI3EN_Pos (15U) +#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk +#define RCC_APB1ENR1_SPDIFRXEN_Pos (16U) +#define RCC_APB1ENR1_SPDIFRXEN_Msk (0x1UL << RCC_APB1ENR1_SPDIFRXEN_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENR1_SPDIFRXEN RCC_APB1ENR1_SPDIFRXEN_Msk +#define RCC_APB1ENR1_USART2EN_Pos (17U) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk +#define RCC_APB1ENR1_USART3EN_Pos (18U) +#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk +#define RCC_APB1ENR1_UART4EN_Pos (19U) +#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk +#define RCC_APB1ENR1_UART5EN_Pos (20U) +#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk +#define RCC_APB1ENR1_I2C1_I3C1EN_Pos (21U) +#define RCC_APB1ENR1_I2C1_I3C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1_I3C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1_I3C1EN RCC_APB1ENR1_I2C1_I3C1EN_Msk +#define RCC_APB1ENR1_I2C2EN_Pos (22U) +#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk +#define RCC_APB1ENR1_I2C3EN_Pos (23U) +#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk +#define RCC_APB1ENR1_CECEN_Pos (27U) +#define RCC_APB1ENR1_CECEN_Msk (0x1UL << RCC_APB1ENR1_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR1_CECEN RCC_APB1ENR1_CECEN_Msk +#define RCC_APB1ENR1_UART7EN_Pos (30U) +#define RCC_APB1ENR1_UART7EN_Msk (0x1UL << RCC_APB1ENR1_UART7EN_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENR1_UART7EN RCC_APB1ENR1_UART7EN_Msk +#define RCC_APB1ENR1_UART8EN_Pos (31U) +#define RCC_APB1ENR1_UART8EN_Msk (0x1UL << RCC_APB1ENR1_UART8EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR1_UART8EN RCC_APB1ENR1_UART8EN_Msk + +/******************** Bit definition for RCC_APB1ENR2 register **************/ +#define RCC_APB1ENR2_CRSEN_Pos (1U) +#define RCC_APB1ENR2_CRSEN_Msk (0x1UL << RCC_APB1ENR2_CRSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR2_CRSEN RCC_APB1ENR2_CRSEN_Msk +#define RCC_APB1ENR2_MDIOSEN_Pos (5U) +#define RCC_APB1ENR2_MDIOSEN_Msk (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_MDIOSEN RCC_APB1ENR2_MDIOSEN_Msk +#define RCC_APB1ENR2_FDCANEN_Pos (8U) +#define RCC_APB1ENR2_FDCANEN_Msk (0x1UL << RCC_APB1ENR2_FDCANEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR2_FDCANEN RCC_APB1ENR2_FDCANEN_Msk +#define RCC_APB1ENR2_UCPD1EN_Pos (27U) +#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk + +/******************** Bit definition for RCC_APB2ENR register ***************/ +#define RCC_APB2ENR_TIM1EN_Pos (0U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk +#define RCC_APB2ENR_USART1EN_Pos (4U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk +#define RCC_APB2ENR_SPI4EN_Pos (13U) +#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk +#define RCC_APB2ENR_TIM9EN_Pos (19U) +#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk +#define RCC_APB2ENR_SPI5EN_Pos (20U) +#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk +#define RCC_APB2ENR_SAI1EN_Pos (22U) +#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk +#define RCC_APB2ENR_SAI2EN_Pos (23U) +#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */ +#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk + +/******************** Bit definition for RCC_APB4ENR register ***************/ +#define RCC_APB4ENR_SBSEN_Pos (1U) +#define RCC_APB4ENR_SBSEN_Msk (0x1UL << RCC_APB4ENR_SBSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENR_SBSEN RCC_APB4ENR_SBSEN_Msk +#define RCC_APB4ENR_LPUART1EN_Pos (3U) +#define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk +#define RCC_APB4ENR_SPI6EN_Pos (5U) +#define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk +#define RCC_APB4ENR_LPTIM2EN_Pos (9U) +#define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */ +#define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk +#define RCC_APB4ENR_LPTIM3EN_Pos (10U) +#define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */ +#define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk +#define RCC_APB4ENR_LPTIM4EN_Pos (11U) +#define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */ +#define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk +#define RCC_APB4ENR_LPTIM5EN_Pos (12U) +#define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */ +#define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk +#define RCC_APB4ENR_VREFEN_Pos (15U) +#define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk +#define RCC_APB4ENR_RTCAPBEN_Pos (16U) +#define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk +#define RCC_APB4ENR_DTSEN_Pos (26U) +#define RCC_APB4ENR_DTSEN_Msk (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */ +#define RCC_APB4ENR_DTSEN RCC_APB4ENR_DTSEN_Msk + +/******************** Bit definition for RCC_APB5ENR register ***************/ +#define RCC_APB5ENR_LTDCEN_Pos (1U) +#define RCC_APB5ENR_LTDCEN_Msk (0x1UL << RCC_APB5ENR_LTDCEN_Pos) /*!< 0x00000002 */ +#define RCC_APB5ENR_LTDCEN RCC_APB5ENR_LTDCEN_Msk +#define RCC_APB5ENR_DCMIPPEN_Pos (2U) +#define RCC_APB5ENR_DCMIPPEN_Msk (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENR_DCMIPPEN RCC_APB5ENR_DCMIPPEN_Msk +#define RCC_APB5ENR_GFXTIMEN_Pos (4U) +#define RCC_APB5ENR_GFXTIMEN_Msk (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENR_GFXTIMEN RCC_APB5ENR_GFXTIMEN_Msk + +/******************** Bit definition for RCC_AHB1LPENR register *************/ +#define RCC_AHB1LPENR_GPDMA1LPEN_Pos (4U) +#define RCC_AHB1LPENR_GPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENR_GPDMA1LPEN RCC_AHB1LPENR_GPDMA1LPEN_Msk +#define RCC_AHB1LPENR_ADC12LPEN_Pos (5U) +#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk +#define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U) +#define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk +#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U) +#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk +#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U) +#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk +#define RCC_AHB1LPENR_UCPDCTRL_Pos (24U) +#define RCC_AHB1LPENR_UCPDCTRL_Msk (0x1UL << RCC_AHB1LPENR_UCPDCTRL_Pos) /*!< 0x01000000 */ +#define RCC_AHB1LPENR_UCPDCTRL RCC_AHB1LPENR_UCPDCTRL_Msk +#define RCC_AHB1LPENR_OTGHSLPEN_Pos (25U) +#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk +#define RCC_AHB1LPENR_USBPHYCLPEN_Pos (26U) +#define RCC_AHB1LPENR_USBPHYCLPEN_Msk (0x1UL << RCC_AHB1LPENR_USBPHYCLPEN_Pos)/*!< 0x04000000 */ +#define RCC_AHB1LPENR_USBPHYCLPEN RCC_AHB1LPENR_USBPHYCLPEN_Msk +#define RCC_AHB1LPENR_OTGFSLPEN_Pos (27U) +#define RCC_AHB1LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGFSLPEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB1LPENR_OTGFSLPEN RCC_AHB1LPENR_OTGFSLPEN_Msk +#define RCC_AHB1LPENR_ADF1LPEN_Pos (31U) +#define RCC_AHB1LPENR_ADF1LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADF1LPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1LPENR_ADF1LPEN RCC_AHB1LPENR_ADF1LPEN_Msk + +/******************** Bit definition for RCC_AHB2LPENR register *************/ +#define RCC_AHB2LPENR_PSSILPEN_Pos (1U) +#define RCC_AHB2LPENR_PSSILPEN_Msk (0x1UL << RCC_AHB2LPENR_PSSILPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2LPENR_PSSILPEN RCC_AHB2LPENR_PSSILPEN_Msk +#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U) +#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk +#define RCC_AHB2LPENR_CORDICLPEN_Pos (14U) +#define RCC_AHB2LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB2LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB2LPENR_CORDICLPEN RCC_AHB2LPENR_CORDICLPEN_Msk +#define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U) +#define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk +#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U) +#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk + +/******************** Bit definition for RCC_AHB3LPENR register *************/ +#define RCC_AHB3LPENR_RNGLPEN_Pos (0U) +#define RCC_AHB3LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3LPENR_RNGLPEN RCC_AHB3LPENR_RNGLPEN_Msk +#define RCC_AHB3LPENR_HASHLPEN_Pos (1U) +#define RCC_AHB3LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENR_HASHLPEN RCC_AHB3LPENR_HASHLPEN_Msk +#define RCC_AHB3LPENR_CRYPLPEN_Pos (2U) +#define RCC_AHB3LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB3LPENR_CRYPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB3LPENR_CRYPLPEN RCC_AHB3LPENR_CRYPLPEN_Msk +#define RCC_AHB3LPENR_SAESLPEN_Pos (4U) +#define RCC_AHB3LPENR_SAESLPEN_Msk (0x1UL << RCC_AHB3LPENR_SAESLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB3LPENR_SAESLPEN RCC_AHB3LPENR_SAESLPEN_Msk +#define RCC_AHB3LPENR_PKALPEN_Pos (6U) +#define RCC_AHB3LPENR_PKALPEN_Msk (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB3LPENR_PKALPEN RCC_AHB3LPENR_PKALPEN_Msk + +/******************** Bit definition for RCC_AHB4LPENR register *************/ +#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk +#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk +#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk +#define RCC_AHB4LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk +#define RCC_AHB4LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk +#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U) +#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk +#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U) +#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk +#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk +#define RCC_AHB4LPENR_GPIOMLPEN_Pos (12U) +#define RCC_AHB4LPENR_GPIOMLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOMLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB4LPENR_GPIOMLPEN RCC_AHB4LPENR_GPIOMLPEN_Msk +#define RCC_AHB4LPENR_GPIONLPEN_Pos (13U) +#define RCC_AHB4LPENR_GPIONLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENR_GPIONLPEN RCC_AHB4LPENR_GPIONLPEN_Msk +#define RCC_AHB4LPENR_GPIOOLPEN_Pos (14U) +#define RCC_AHB4LPENR_GPIOOLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENR_GPIOOLPEN RCC_AHB4LPENR_GPIOOLPEN_Msk +#define RCC_AHB4LPENR_GPIOPLPEN_Pos (15U) +#define RCC_AHB4LPENR_GPIOPLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENR_GPIOPLPEN RCC_AHB4LPENR_GPIOPLPEN_Msk +#define RCC_AHB4LPENR_CRCLPEN_Pos (19U) +#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk +#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U) +#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk + +/******************** Bit definition for RCC_AHB5LPENR register *************/ +#define RCC_AHB5LPENR_HPDMA1LPEN_Pos (0U) +#define RCC_AHB5LPENR_HPDMA1LPEN_Msk (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENR_HPDMA1LPEN RCC_AHB5LPENR_HPDMA1LPEN_Msk +#define RCC_AHB5LPENR_DMA2DLPEN_Pos (1U) +#define RCC_AHB5LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENR_DMA2DLPEN RCC_AHB5LPENR_DMA2DLPEN_Msk +#define RCC_AHB5LPENR_FLASHLPEN_Pos (2U) +#define RCC_AHB5LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB5LPENR_FLASHLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB5LPENR_FLASHLPEN RCC_AHB5LPENR_FLASHLPEN_Msk +#define RCC_AHB5LPENR_JPEGLPEN_Pos (3U) +#define RCC_AHB5LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENR_JPEGLPEN RCC_AHB5LPENR_JPEGLPEN_Msk +#define RCC_AHB5LPENR_FMCLPEN_Pos (4U) +#define RCC_AHB5LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5LPENR_FMCLPEN RCC_AHB5LPENR_FMCLPEN_Msk +#define RCC_AHB5LPENR_XSPI1LPEN_Pos (5U) +#define RCC_AHB5LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENR_XSPI1LPEN RCC_AHB5LPENR_XSPI1LPEN_Msk +#define RCC_AHB5LPENR_SDMMC1LPEN_Pos (8U) +#define RCC_AHB5LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENR_SDMMC1LPEN RCC_AHB5LPENR_SDMMC1LPEN_Msk +#define RCC_AHB5LPENR_XSPI2LPEN_Pos (12U) +#define RCC_AHB5LPENR_XSPI2LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENR_XSPI2LPEN RCC_AHB5LPENR_XSPI2LPEN_Msk +#define RCC_AHB5LPENR_XSPIMLPEN_Pos (14U) +#define RCC_AHB5LPENR_XSPIMLPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5LPENR_XSPIMLPEN RCC_AHB5LPENR_XSPIMLPEN_Msk +#define RCC_AHB5LPENR_GFXMMULPEN_Pos (19U) +#define RCC_AHB5LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENR_GFXMMULPEN RCC_AHB5LPENR_GFXMMULPEN_Msk +#define RCC_AHB5LPENR_GPU2DLPEN_Pos (20U) +#define RCC_AHB5LPENR_GPU2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_GPU2DLPEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB5LPENR_GPU2DLPEN RCC_AHB5LPENR_GPU2DLPEN_Msk +#define RCC_AHB5LPENR_DTCM1LPEN_Pos (28U) +#define RCC_AHB5LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB5LPENR_DTCM1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENR_DTCM1LPEN RCC_AHB5LPENR_DTCM1LPEN_Msk +#define RCC_AHB5LPENR_DTCM2LPEN_Pos (29U) +#define RCC_AHB5LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB5LPENR_DTCM2LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENR_DTCM2LPEN RCC_AHB5LPENR_DTCM2LPEN_Msk +#define RCC_AHB5LPENR_ITCMLPEN_Pos (30U) +#define RCC_AHB5LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB5LPENR_ITCMLPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB5LPENR_ITCMLPEN RCC_AHB5LPENR_ITCMLPEN_Msk +#define RCC_AHB5LPENR_AXISRAMLPEN_Pos (31U) +#define RCC_AHB5LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB5LPENR_AXISRAMLPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB5LPENR_AXISRAMLPEN RCC_AHB5LPENR_AXISRAMLPEN_Msk + +/******************** Bit definition for RCC_APB1LPENR1 register ************/ +#define RCC_APB1LPENR1_TIM2LPEN_Pos (0U) +#define RCC_APB1LPENR1_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENR1_TIM2LPEN RCC_APB1LPENR1_TIM2LPEN_Msk +#define RCC_APB1LPENR1_TIM3LPEN_Pos (1U) +#define RCC_APB1LPENR1_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENR1_TIM3LPEN RCC_APB1LPENR1_TIM3LPEN_Msk +#define RCC_APB1LPENR1_TIM4LPEN_Pos (2U) +#define RCC_APB1LPENR1_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENR1_TIM4LPEN RCC_APB1LPENR1_TIM4LPEN_Msk +#define RCC_APB1LPENR1_TIM5LPEN_Pos (3U) +#define RCC_APB1LPENR1_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENR1_TIM5LPEN RCC_APB1LPENR1_TIM5LPEN_Msk +#define RCC_APB1LPENR1_TIM6LPEN_Pos (4U) +#define RCC_APB1LPENR1_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENR1_TIM6LPEN RCC_APB1LPENR1_TIM6LPEN_Msk +#define RCC_APB1LPENR1_TIM7LPEN_Pos (5U) +#define RCC_APB1LPENR1_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR1_TIM7LPEN RCC_APB1LPENR1_TIM7LPEN_Msk +#define RCC_APB1LPENR1_TIM12LPEN_Pos (6U) +#define RCC_APB1LPENR1_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENR1_TIM12LPEN RCC_APB1LPENR1_TIM12LPEN_Msk +#define RCC_APB1LPENR1_TIM13LPEN_Pos (7U) +#define RCC_APB1LPENR1_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENR1_TIM13LPEN RCC_APB1LPENR1_TIM13LPEN_Msk +#define RCC_APB1LPENR1_TIM14LPEN_Pos (8U) +#define RCC_APB1LPENR1_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR1_TIM14LPEN RCC_APB1LPENR1_TIM14LPEN_Msk +#define RCC_APB1LPENR1_LPTIM1LPEN_Pos (9U) +#define RCC_APB1LPENR1_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos)/*!< 0x00000200 */ +#define RCC_APB1LPENR1_LPTIM1LPEN RCC_APB1LPENR1_LPTIM1LPEN_Msk +#define RCC_APB1LPENR1_WWDGLPEN_Pos (11U) +#define RCC_APB1LPENR1_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENR1_WWDGLPEN RCC_APB1LPENR1_WWDGLPEN_Msk +#define RCC_APB1LPENR1_SPI2LPEN_Pos (14U) +#define RCC_APB1LPENR1_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENR1_SPI2LPEN RCC_APB1LPENR1_SPI2LPEN_Msk +#define RCC_APB1LPENR1_SPI3LPEN_Pos (15U) +#define RCC_APB1LPENR1_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENR1_SPI3LPEN RCC_APB1LPENR1_SPI3LPEN_Msk +#define RCC_APB1LPENR1_SPDIFRXLPEN_Pos (16U) +#define RCC_APB1LPENR1_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LPENR1_SPDIFRXLPEN_Pos)/*!< 0x00010000 */ +#define RCC_APB1LPENR1_SPDIFRXLPEN RCC_APB1LPENR1_SPDIFRXLPEN_Msk +#define RCC_APB1LPENR1_USART2LPEN_Pos (17U) +#define RCC_APB1LPENR1_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos)/*!< 0x00020000 */ +#define RCC_APB1LPENR1_USART2LPEN RCC_APB1LPENR1_USART2LPEN_Msk +#define RCC_APB1LPENR1_USART3LPEN_Pos (18U) +#define RCC_APB1LPENR1_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos)/*!< 0x00040000 */ +#define RCC_APB1LPENR1_USART3LPEN RCC_APB1LPENR1_USART3LPEN_Msk +#define RCC_APB1LPENR1_UART4LPEN_Pos (19U) +#define RCC_APB1LPENR1_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENR1_UART4LPEN RCC_APB1LPENR1_UART4LPEN_Msk +#define RCC_APB1LPENR1_UART5LPEN_Pos (20U) +#define RCC_APB1LPENR1_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENR1_UART5LPEN RCC_APB1LPENR1_UART5LPEN_Msk +#define RCC_APB1LPENR1_I2C1_I3C1LPEN_Pos (21U) +#define RCC_APB1LPENR1_I2C1_I3C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C1_I3C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENR1_I2C1_I3C1LPEN RCC_APB1LPENR1_I2C1_I3C1LPEN_Msk +#define RCC_APB1LPENR1_I2C2LPEN_Pos (22U) +#define RCC_APB1LPENR1_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENR1_I2C2LPEN RCC_APB1LPENR1_I2C2LPEN_Msk +#define RCC_APB1LPENR1_I2C3LPEN_Pos (23U) +#define RCC_APB1LPENR1_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENR1_I2C3LPEN RCC_APB1LPENR1_I2C3LPEN_Msk +#define RCC_APB1LPENR1_CECLPEN_Pos (27U) +#define RCC_APB1LPENR1_CECLPEN_Msk (0x1UL << RCC_APB1LPENR1_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1LPENR1_CECLPEN RCC_APB1LPENR1_CECLPEN_Msk +#define RCC_APB1LPENR1_UART7LPEN_Pos (30U) +#define RCC_APB1LPENR1_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENR1_UART7LPEN RCC_APB1LPENR1_UART7LPEN_Msk +#define RCC_APB1LPENR1_UART8LPEN_Pos (31U) +#define RCC_APB1LPENR1_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENR1_UART8LPEN RCC_APB1LPENR1_UART8LPEN_Msk + +/******************** Bit definition for RCC_PB1LPENR2 register ************/ +#define RCC_APB1LPENR2_CRSLPEN_Pos (1U) +#define RCC_APB1LPENR2_CRSLPEN_Msk (0x1UL << RCC_APB1LPENR2_CRSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENR2_CRSLPEN RCC_APB1LPENR2_CRSLPEN_Msk +#define RCC_APB1LPENR2_MDIOSLPEN_Pos (5U) +#define RCC_APB1LPENR2_MDIOSLPEN_Msk (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR2_MDIOSLPEN RCC_APB1LPENR2_MDIOSLPEN_Msk +#define RCC_APB1LPENR2_FDCANLPEN_Pos (8U) +#define RCC_APB1LPENR2_FDCANLPEN_Msk (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR2_FDCANLPEN RCC_APB1LPENR2_FDCANLPEN_Msk +#define RCC_APB1LPENR2_UCPD1LPEN_Pos (27U) +#define RCC_APB1LPENR2_UCPD1LPEN_Msk (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1LPENR2_UCPD1LPEN RCC_APB1LPENR2_UCPD1LPEN_Msk + +/******************** Bit definition for RCC_APB2LPENR register *************/ +#define RCC_APB2LPENR_TIM1LPEN_Pos (0U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk +#define RCC_APB2LPENR_USART1LPEN_Pos (4U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk +#define RCC_APB2LPENR_SPI4LPEN_Pos (13U) +#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk +#define RCC_APB2LPENR_TIM15LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk +#define RCC_APB2LPENR_TIM16LPEN_Pos (17U) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk +#define RCC_APB2LPENR_TIM17LPEN_Pos (18U) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk +#define RCC_APB2LPENR_TIM9LPEN_Pos (19U) +#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk +#define RCC_APB2LPENR_SPI5LPEN_Pos (20U) +#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk +#define RCC_APB2LPENR_SAI1LPEN_Pos (22U) +#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk +#define RCC_APB2LPENR_SAI2LPEN_Pos (23U) +#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk + +/******************** Bit definition for RCC_APB4LPENR register *************/ +#define RCC_APB4LPENR_SBSLPEN_Pos (1U) +#define RCC_APB4LPENR_SBSLPEN_Msk (0x1UL << RCC_APB4LPENR_SBSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENR_SBSLPEN RCC_APB4LPENR_SBSLPEN_Msk +#define RCC_APB4LPENR_LPUART1LPEN_Pos (3U) +#define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos)/*!< 0x00000008 */ +#define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk +#define RCC_APB4LPENR_SPI6LPEN_Pos (5U) +#define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk +#define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U) +#define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk +#define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U) +#define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk +#define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U) +#define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk +#define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U) +#define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk +#define RCC_APB4LPENR_VREFLPEN_Pos (15U) +#define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk +#define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U) +#define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk +#define RCC_APB4LPENR_DTSLPEN_Pos (26U) +#define RCC_APB4LPENR_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */ +#define RCC_APB4LPENR_DTSLPEN RCC_APB4LPENR_DTSLPEN_Msk + +/******************** Bit definition for RCC_APB5LPENR register *************/ +#define RCC_APB5LPENR_LTDCLPEN_Pos (1U) +#define RCC_APB5LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB5LPENR_LTDCLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB5LPENR_LTDCLPEN RCC_APB5LPENR_LTDCLPEN_Msk +#define RCC_APB5LPENR_DCMIPPLPEN_Pos (2U) +#define RCC_APB5LPENR_DCMIPPLPEN_Msk (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENR_DCMIPPLPEN RCC_APB5LPENR_DCMIPPLPEN_Msk +#define RCC_APB5LPENR_GFXTIMLPEN_Pos (4U) +#define RCC_APB5LPENR_GFXTIMLPEN_Msk (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENR_GFXTIMLPEN RCC_APB5LPENR_GFXTIMLPEN_Msk + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Secure Advanced Encryption Standard (SAES) */ +/* */ +/******************************************************************************/ +/******************* Bits definition for SAES_CR register *********************/ +#define SAES_CR_EN_Pos (0U) +#define SAES_CR_EN_Msk (0x1UL << SAES_CR_EN_Pos) /*!< 0x00000001 */ +#define SAES_CR_EN SAES_CR_EN_Msk /*!< SAES Enable */ +#define SAES_CR_DATATYPE_Pos (1U) +#define SAES_CR_DATATYPE_Msk (0x3UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define SAES_CR_DATATYPE SAES_CR_DATATYPE_Msk /*!< Data type selection */ +#define SAES_CR_DATATYPE_0 (0x1UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define SAES_CR_DATATYPE_1 (0x2UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define SAES_CR_MODE_Pos (3U) +#define SAES_CR_MODE_Msk (0x3UL << SAES_CR_MODE_Pos) /*!< 0x00000018 */ +#define SAES_CR_MODE SAES_CR_MODE_Msk /*!< SAES Mode Of Operation */ +#define SAES_CR_MODE_0 (0x1UL << SAES_CR_MODE_Pos) /*!< 0x00000008 */ +#define SAES_CR_MODE_1 (0x2UL << SAES_CR_MODE_Pos) /*!< 0x00000010 */ +#define SAES_CR_CHMOD_Pos (5U) +#define SAES_CR_CHMOD_Msk (0x803UL << SAES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define SAES_CR_CHMOD SAES_CR_CHMOD_Msk /*!< SAES Chaining Mode */ +#define SAES_CR_CHMOD_0 (0x001UL << SAES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define SAES_CR_CHMOD_1 (0x002UL << SAES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define SAES_CR_CHMOD_2 (0x800UL << SAES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define SAES_CR_DMAINEN_Pos (11U) +#define SAES_CR_DMAINEN_Msk (0x1UL << SAES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define SAES_CR_DMAINEN SAES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define SAES_CR_DMAOUTEN_Pos (12U) +#define SAES_CR_DMAOUTEN_Msk (0x1UL << SAES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define SAES_CR_DMAOUTEN SAES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ +#define SAES_CR_GCMPH_Pos (13U) +#define SAES_CR_GCMPH_Msk (0x3UL << SAES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define SAES_CR_GCMPH SAES_CR_GCMPH_Msk /*!< GCM Phase */ +#define SAES_CR_GCMPH_0 (0x1UL << SAES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define SAES_CR_GCMPH_1 (0x2UL << SAES_CR_GCMPH_Pos) /*!< 0x00004000 */ +#define SAES_CR_KEYSIZE_Pos (18U) +#define SAES_CR_KEYSIZE_Msk (0x1UL << SAES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define SAES_CR_KEYSIZE SAES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define SAES_CR_NPBLB_Pos (20U) +#define SAES_CR_NPBLB_Msk (0xFUL << SAES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define SAES_CR_NPBLB SAES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define SAES_CR_NPBLB_0 (0x1UL << SAES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define SAES_CR_NPBLB_1 (0x2UL << SAES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define SAES_CR_NPBLB_2 (0x4UL << SAES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define SAES_CR_NPBLB_3 (0x8UL << SAES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define SAES_CR_KMOD_Pos (24U) +#define SAES_CR_KMOD_Msk (0x3UL << SAES_CR_KMOD_Pos) /*!< 0x00000006 */ +#define SAES_CR_KMOD SAES_CR_KMOD_Msk /*!< Key mode selection */ +#define SAES_CR_KMOD_0 (0x1UL << SAES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define SAES_CR_KMOD_1 (0x2UL << SAES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define SAES_CR_KSHAREID_Pos (26U) +#define SAES_CR_KSHAREID_Msk (0x3UL << SAES_CR_KSHAREID_Pos) /*!< 0x00000006 */ +#define SAES_CR_KSHAREID SAES_CR_KSHAREID_Msk /*!< Key Shared ID */ +#define SAES_CR_KEYSEL_Pos (28U) +#define SAES_CR_KEYSEL_Msk (0x7UL << SAES_CR_KEYSEL_Pos) /*!< 0x00000006 */ +#define SAES_CR_KEYSEL SAES_CR_KEYSEL_Msk /*!< Key Selection */ +#define SAES_CR_KEYSEL_0 (0x1UL << SAES_CR_KEYSEL_Pos) /*!< 0x02000000 */ +#define SAES_CR_KEYSEL_1 (0x2UL << SAES_CR_KEYSEL_Pos) /*!< 0x02000000 */ +#define SAES_CR_KEYSEL_2 (0x4UL << SAES_CR_KEYSEL_Pos) /*!< 0x02000000 */ +#define SAES_CR_IPRST_Pos (31U) +#define SAES_CR_IPRST_Msk (0x1UL << SAES_CR_IPRST_Pos) /*!< 0x80000001 */ +#define SAES_CR_IPRST SAES_CR_IPRST_Msk /*!< SAES IP software reset */ + +/******************* Bits definition for SAES_SR register *********************/ +#define SAES_SR_CCF_Pos (0U) +#define SAES_SR_CCF_Msk (0x1UL << SAES_SR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_SR_CCF SAES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define SAES_SR_RDERR_Pos (1U) +#define SAES_SR_RDERR_Msk (0x1UL << SAES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define SAES_SR_RDERR SAES_SR_RDERR_Msk /*!< Read Error Flag */ +#define SAES_SR_WRERR_Pos (2U) +#define SAES_SR_WRERR_Msk (0x1UL << SAES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define SAES_SR_WRERR SAES_SR_WRERR_Msk /*!< Write Error Flag */ +#define SAES_SR_BUSY_Pos (3U) +#define SAES_SR_BUSY_Msk (0x1UL << SAES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define SAES_SR_BUSY SAES_SR_BUSY_Msk /*!< Busy Flag */ +#define SAES_SR_KEYVALID_Pos (7U) +#define SAES_SR_KEYVALID_Msk (0x1UL << SAES_SR_KEYVALID_Pos) /*!< 0x00000008 */ +#define SAES_SR_KEYVALID SAES_SR_KEYVALID_Msk /*!< KEYVALID Flag */ + +/******************* Bits definition for SAES_DINR register *******************/ +#define SAES_DINR_Pos (0U) +#define SAES_DINR_Msk (0xFFFFFFFFUL << SAES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define SAES_DINR SAES_DINR_Msk /*!< SAES Data Input Register */ + +/******************* Bits definition for SAES_DOUTR register ******************/ +#define SAES_DOUTR_Pos (0U) +#define SAES_DOUTR_Msk (0xFFFFFFFFUL << SAES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define SAES_DOUTR SAES_DOUTR_Msk /*!< SAES Data Output Register */ + +/******************* Bits definition for SAES_KEYR0 register ******************/ +#define SAES_KEYR0_Pos (0U) +#define SAES_KEYR0_Msk (0xFFFFFFFFUL << SAES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR0 SAES_KEYR0_Msk /*!< SAES Key Register 0 */ + +/******************* Bits definition for SAES_KEYR1 register ******************/ +#define SAES_KEYR1_Pos (0U) +#define SAES_KEYR1_Msk (0xFFFFFFFFUL << SAES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR1 SAES_KEYR1_Msk /*!< SAES Key Register 1 */ + +/******************* Bits definition for SAES_KEYR2 register ******************/ +#define SAES_KEYR2_Pos (0U) +#define SAES_KEYR2_Msk (0xFFFFFFFFUL << SAES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR2 SAES_KEYR2_Msk /*!< SAES Key Register 2 */ + +/******************* Bits definition for SAES_KEYR3 register ******************/ +#define SAES_KEYR3_Pos (0U) +#define SAES_KEYR3_Msk (0xFFFFFFFFUL << SAES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR3 SAES_KEYR3_Msk /*!< SAES Key Register 3 */ + +/******************* Bits definition for SAES_KEYR4 register ******************/ +#define SAES_KEYR4_Pos (0U) +#define SAES_KEYR4_Msk (0xFFFFFFFFUL << SAES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR4 SAES_KEYR4_Msk /*!< SAES Key Register 4 */ + +/******************* Bits definition for SAES_KEYR5 register ******************/ +#define SAES_KEYR5_Pos (0U) +#define SAES_KEYR5_Msk (0xFFFFFFFFUL << SAES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR5 SAES_KEYR5_Msk /*!< SAES Key Register 5 */ + +/******************* Bits definition for SAES_KEYR6 register ******************/ +#define SAES_KEYR6_Pos (0U) +#define SAES_KEYR6_Msk (0xFFFFFFFFUL << SAES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR6 SAES_KEYR6_Msk /*!< SAES Key Register 6 */ + +/******************* Bits definition for SAES_KEYR7 register ******************/ +#define SAES_KEYR7_Pos (0U) +#define SAES_KEYR7_Msk (0xFFFFFFFFUL << SAES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR7 SAES_KEYR7_Msk /*!< SAES Key Register 7 */ + +/******************* Bits definition for SAES_IVR0 register ******************/ +#define SAES_IVR0_Pos (0U) +#define SAES_IVR0_Msk (0xFFFFFFFFUL << SAES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR0 SAES_IVR0_Msk /*!< SAES Initialization Vector Register 0 */ + +/******************* Bits definition for SAES_IVR1 register ******************/ +#define SAES_IVR1_Pos (0U) +#define SAES_IVR1_Msk (0xFFFFFFFFUL << SAES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR1 SAES_IVR1_Msk /*!< SAES Initialization Vector Register 1 */ + +/******************* Bits definition for SAES_IVR2 register ******************/ +#define SAES_IVR2_Pos (0U) +#define SAES_IVR2_Msk (0xFFFFFFFFUL << SAES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR2 SAES_IVR2_Msk /*!< SAES Initialization Vector Register 2 */ + +/******************* Bits definition for SAES_IVR3 register ******************/ +#define SAES_IVR3_Pos (0U) +#define SAES_IVR3_Msk (0xFFFFFFFFUL << SAES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR3 SAES_IVR3_Msk /*!< SAES Initialization Vector Register 3 */ + +/******************* Bit definition for SAES_SUSP0R register ******************/ +#define SAES_SUSP0R_Pos (0U) +#define SAES_SUSP0R_Msk (0xFFFFFFFFUL << SAES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP0R SAES_SUSP0R_Msk /*!< SAES Suspend registers 0 */ + +/******************* Bit definition for SAES_SUSP1R register ******************/ +#define SAES_SUSP1R_Pos (0U) +#define SAES_SUSP1R_Msk (0xFFFFFFFFUL << SAES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP1R SAES_SUSP1R_Msk /*!< SAES Suspend registers 1 */ + +/******************* Bit definition for SAES_SUSP2R register ******************/ +#define SAES_SUSP2R_Pos (0U) +#define SAES_SUSP2R_Msk (0xFFFFFFFFUL << SAES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP2R SAES_SUSP2R_Msk /*!< SAES Suspend registers 2 */ + +/******************* Bit definition for SAES_SUSP3R register ******************/ +#define SAES_SUSP3R_Pos (0U) +#define SAES_SUSP3R_Msk (0xFFFFFFFFUL << SAES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP3R SAES_SUSP3R_Msk /*!< SAES Suspend registers 3 */ + +/******************* Bit definition for SAES_SUSP4R register ******************/ +#define SAES_SUSP4R_Pos (0U) +#define SAES_SUSP4R_Msk (0xFFFFFFFFUL << SAES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP4R SAES_SUSP4R_Msk /*!< SAES Suspend registers 4 */ + +/******************* Bit definition for SAES_SUSP5R register ******************/ +#define SAES_SUSP5R_Pos (0U) +#define SAES_SUSP5R_Msk (0xFFFFFFFFUL << SAES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP5R SAES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for SAES_SUSP6R register ******************/ +#define SAES_SUSP6R_Pos (0U) +#define SAES_SUSP6R_Msk (0xFFFFFFFFUL << SAES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP6R SAES_SUSP6R_Msk /*!< SAES Suspend registers 6 */ + +/******************* Bit definition for SAES_SUSP7R register ******************/ +#define SAES_SUSP7R_Pos (0U) +#define SAES_SUSP7R_Msk (0xFFFFFFFFUL << SAES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP7R SAES_SUSP7R_Msk /*!< SAES Suspend registers 7 */ + +/******************* Bits definition for SAES_IER register ******************/ +#define SAES_IER_CCFIE_Pos (0U) +#define SAES_IER_CCFIE_Msk (0x1UL << SAES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define SAES_IER_CCFIE SAES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ +#define SAES_IER_RWEIE_Pos (1U) +#define SAES_IER_RWEIE_Msk (0x1UL << SAES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define SAES_IER_RWEIE SAES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ +#define SAES_IER_KEIE_Pos (2U) +#define SAES_IER_KEIE_Msk (0x1UL << SAES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define SAES_IER_KEIE SAES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define SAES_IER_RNGEIE_Pos (3U) +#define SAES_IER_RNGEIE_Msk (0x1UL << SAES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define SAES_IER_RNGEIE SAES_IER_RNGEIE_Msk /*!< Rng error interrupt enable */ + +/******************* Bits definition for SAES_ISR register ******************/ +#define SAES_ISR_CCF_Pos (0U) +#define SAES_ISR_CCF_Msk (0x1UL << SAES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_ISR_CCF SAES_ISR_CCF_Msk /*!< Computation complete flag */ +#define SAES_ISR_RWEIF_Pos (1U) +#define SAES_ISR_RWEIF_Msk (0x1UL << SAES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define SAES_ISR_RWEIF SAES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ +#define SAES_ISR_KEIF_Pos (2U) +#define SAES_ISR_KEIF_Msk (0x1UL << SAES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define SAES_ISR_KEIF SAES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define SAES_ISR_RNGEIF_Pos (3U) +#define SAES_ISR_RNGEIF_Msk (0x1UL << SAES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define SAES_ISR_RNGEIF SAES_ISR_RNGEIF_Msk /*!< Rng error interrupt flag */ + +/******************* Bits definition for SAES_ICR register ******************/ +#define SAES_ICR_CCF_Pos (0U) +#define SAES_ICR_CCF_Msk (0x1UL << SAES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_ICR_CCF SAES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define SAES_ICR_RWEIF_Pos (1U) +#define SAES_ICR_RWEIF_Msk (0x1UL << SAES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define SAES_ICR_RWEIF SAES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ +#define SAES_ICR_KEIF_Pos (2U) +#define SAES_ICR_KEIF_Msk (0x1UL << SAES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define SAES_ICR_KEIF SAES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define SAES_ICR_RNGEIF_Pos (3U) +#define SAES_ICR_RNGEIF_Msk (0x1UL << SAES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define SAES_ICR_RNGEIF SAES_ICR_RNGEIF_Msk /*!< Rng error interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Exported_Functions + * @{ + */ + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_STM32H7RSXX_H */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Release_Notes.html b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Release_Notes.html new file mode 100644 index 00000000000..66888846e0a --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Release_Notes.html @@ -0,0 +1,126 @@ + + + + + + + Release Notes for STM32H7RSxx CMSIS + + + + + + +
+
+
+

Release Notes for

+

STM32H7RSxx CMSIS

+

Copyright © 2024 STMicroelectronics
+

+ +
+

Purpose

+

This driver provides the CMSIS device for the stm32H7RSxx products. This covers

+
    +
  • STM32H7S7xx devices
    • +
  • STM32H7S3xx devices
    • +
  • STM32H7R7xx devices
    • +
  • STM32H7R3xx devices
    • +
+

This driver is composed of the description of the registers under “Include” directory.

+

Various template files are provided to easily build an application. They can be adapted to fit applications requirements.

+
    +
  • Templates/system_stm32h7rsxx.c contains the initialization code referred as SystemInit.
    • +
  • Startup files are provided as example for EWARM©, MDK-ARM©, STM32CubeIDE©.
    • +
  • Linker files are provided as example for EWARM©, MDK-ARM©, STM32CubeIDE©.
    • +
+
+
+

Update History

+
+ +
+

First release

+

First official Release of STM32H7RSxx Firmware package supporting STM32H7RSxx devices

+

Contents

+
    +
  • Support of STM32H7Rx/Sx devices
    • +
+


+

+

Notes: linker file mapping vs HW boards

+ + + + + + + + + + + + + + + + + + + + +
BoardInternal Flash (boot)External memories (Appli)
STM32H7S78-DKstm32h7s7xx_flash.*stm32h7rsxx_RAMxspi1_ROMxspi2.*
NUCLEO-H7S3L8stm32h7s3xx_flash.*stm32h7rsxx_ROMxspi2.*
+


+

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V9.20.1
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.38a
    • +
  • STM32CubeIDE V1.15.0 (GCC12)
    • +
+


+

+

Supported Devices and boards

+
    +
  • STM32H7R3xx/STM32H7R7xx/STM32H7S3xx/STM32H7S7xx devices
    • +
+


+

+

Known Limitations

+
    +
  • None
    • +
+

Dependencies

+
    +
  • None
    • +
+

Notes

+
    +
  • None
    • +
+
+
+
+
+
+
+
+

For complete documentation on STM32H7Rx/Sx,

+

visit: stm32h7-series/stm32h7r3-7s3

+

visit: stm32h7-series/stm32h7r7-7s7

+

This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.

+
+

Info

+
+
+
+ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7r3xx_flash.sct b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7r3xx_flash.sct new file mode 100644 index 00000000000..d6063e6a1fb --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7r3xx_flash.sct @@ -0,0 +1,34 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LOAD_FLASH 0x08000000 0x08010000 { ; load region size_region + ER_ROM 0x08000000 0x08010000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + ER_ITCM 0x00000000 0x00010000 { ; + } + + RW_DTCM 0x20000000 0x00010000 { ; RW data + *(STACK) + *(HEAP) + } + + RW_SRAMAHB 0x30000000 0x8000 { + } + + RW_BKPSRAM 0x38800000 0x1000 { + } + + RW_RAM 0x24000000 0x00072000-0x400 { + .ANY (+RW +ZI) + } + + RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 { + *(noncacheable_buffer) + } +} \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7r3xx_sram.sct b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7r3xx_sram.sct new file mode 100644 index 00000000000..b21e20c90f7 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7r3xx_sram.sct @@ -0,0 +1,34 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LOAD_FLASH 0x24050000 0x00022000 { ; load region size_region + ER_ROM 0x24050000 0x00022000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + ER_ITCM 0x00000000 0x00010000 { ; + } + + RW_DTCM 0x20000000 0x00010000 { ; RW data + *(STACK) + *(HEAP) + } + + RW_SRAMAHB 0x30000000 0x8000 { + } + + RW_BKPSRAM 0x38800000 0x1000 { + } + + RW_RAM 0x24000000 0x00050000-0x400 { + .ANY (+RW +ZI) + } + + RW_NONCACHEABLEBUFFER 0x24050000-0x400 0x400 { + *(noncacheable_buffer) + } +} \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7r7xx_flash.sct b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7r7xx_flash.sct new file mode 100644 index 00000000000..d6063e6a1fb --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7r7xx_flash.sct @@ -0,0 +1,34 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LOAD_FLASH 0x08000000 0x08010000 { ; load region size_region + ER_ROM 0x08000000 0x08010000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + ER_ITCM 0x00000000 0x00010000 { ; + } + + RW_DTCM 0x20000000 0x00010000 { ; RW data + *(STACK) + *(HEAP) + } + + RW_SRAMAHB 0x30000000 0x8000 { + } + + RW_BKPSRAM 0x38800000 0x1000 { + } + + RW_RAM 0x24000000 0x00072000-0x400 { + .ANY (+RW +ZI) + } + + RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 { + *(noncacheable_buffer) + } +} \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7r7xx_sram.sct b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7r7xx_sram.sct new file mode 100644 index 00000000000..b21e20c90f7 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7r7xx_sram.sct @@ -0,0 +1,34 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LOAD_FLASH 0x24050000 0x00022000 { ; load region size_region + ER_ROM 0x24050000 0x00022000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + ER_ITCM 0x00000000 0x00010000 { ; + } + + RW_DTCM 0x20000000 0x00010000 { ; RW data + *(STACK) + *(HEAP) + } + + RW_SRAMAHB 0x30000000 0x8000 { + } + + RW_BKPSRAM 0x38800000 0x1000 { + } + + RW_RAM 0x24000000 0x00050000-0x400 { + .ANY (+RW +ZI) + } + + RW_NONCACHEABLEBUFFER 0x24050000-0x400 0x400 { + *(noncacheable_buffer) + } +} \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_RAMxspi1_ROMxspi2.sct b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_RAMxspi1_ROMxspi2.sct new file mode 100644 index 00000000000..54bb443dd6c --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_RAMxspi1_ROMxspi2.sct @@ -0,0 +1,37 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LOAD_FLASH 0x70000000 0x08000000 { ; load region size_region + ER_ROM 0x70000000 0x08000000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + ER_ITCM 0x00000000 0x00010000 { ; + } + + RW_DTCM 0x20000000 0x00010000 { ; RW data + *(STACK) + *(HEAP) + } + + RW_SRAMAHB 0x30000000 0x8000 { + } + + RW_BKPSRAM 0x38800000 0x1000 { + } + + RW_EXTRAM 0x90000000 0x2000000 { + } + + RW_RAM 0x24000000 0x00072000-0x400 { + .ANY (+RW +ZI) + } + + RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 { + *(noncacheable_buffer) + } +} \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_ROMxspi1.sct b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_ROMxspi1.sct new file mode 100644 index 00000000000..d9c96319b80 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_ROMxspi1.sct @@ -0,0 +1,34 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LOAD_FLASH 0x90000000 0x08000000 { ; load region size_region + ER_ROM 0x90000000 0x08000000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + ER_ITCM 0x00000000 0x00010000 { ; + } + + RW_DTCM 0x20000000 0x00010000 { ; RW data + *(STACK) + *(HEAP) + } + + RW_SRAMAHB 0x30000000 0x8000 { + } + + RW_BKPSRAM 0x38800000 0x1000 { + } + + RW_RAM 0x24000000 0x00072000-0x400 { + .ANY (+RW +ZI) + } + + RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 { + *(noncacheable_buffer) + } +} \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_ROMxspi1_RAMxspi2.sct b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_ROMxspi1_RAMxspi2.sct new file mode 100644 index 00000000000..977f5bd85cc --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_ROMxspi1_RAMxspi2.sct @@ -0,0 +1,37 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LOAD_FLASH 0x90000000 0x08000000 { ; load region size_region + ER_ROM 0x90000000 0x08000000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + ER_ITCM 0x00000000 0x00010000 { ; + } + + RW_DTCM 0x20000000 0x00010000 { ; RW data + *(STACK) + *(HEAP) + } + + RW_SRAMAHB 0x30000000 0x8000 { + } + + RW_BKPSRAM 0x38800000 0x1000 { + } + + RW_EXTRAM 0x70000000 0x2000000 { + } + + RW_RAM 0x24000000 0x00072000-0x400 { + .ANY (+RW +ZI) + } + + RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 { + *(noncacheable_buffer) + } +} \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_ROMxspi2.sct b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_ROMxspi2.sct new file mode 100644 index 00000000000..eb7894987f0 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_ROMxspi2.sct @@ -0,0 +1,34 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LOAD_FLASH 0x70000000 0x08000000 { ; load region size_region + ER_ROM 0x70000000 0x08000000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + ER_ITCM 0x00000000 0x00010000 { ; + } + + RW_DTCM 0x20000000 0x00010000 { ; RW data + *(STACK) + *(HEAP) + } + + RW_SRAMAHB 0x30000000 0x8000 { + } + + RW_BKPSRAM 0x38800000 0x1000 { + } + + RW_RAM 0x24000000 0x00072000-0x400 { + .ANY (+RW +ZI) + } + + RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 { + *(noncacheable_buffer) + } +} \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_extmemloader_mdkarm.sct b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_extmemloader_mdkarm.sct new file mode 100644 index 00000000000..b286900b16e --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_extmemloader_mdkarm.sct @@ -0,0 +1,23 @@ +; ************************************************************* +; MDK-ARM ExtFlashLoader Linker Control File (scatter-loading) +; ************************************************************* +PRG 0 PI ; Programming Functions +{ + PrgCode +0 ; Code + { + * (+RO) + } + PrgData +0 ; Data + { + * (+ZI,+RW) + } + +} + +DSCR +0x1000 +{ + DevDscr +0 + { + FlashDev.o + } +} diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_extmemloader_stm32cube.sct b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_extmemloader_stm32cube.sct new file mode 100644 index 00000000000..a8cca1c221b --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7rsxx_extmemloader_stm32cube.sct @@ -0,0 +1,26 @@ +; ************************************************************* +; STM32CubeProgrammer ExtFlashLoader Linker Control File (scatter-loading) +; ************************************************************* + +;0x20000004 is the address where the flashloader is loaded +FLASH_LOADER 0x20000004 PI ; FlashLoader Functions +{ + PrgCode +0 ; Code + { + * (+RO) + } +; 0x0401FFFC+0x20000004=0x24020000 where data and bss is loaded + PrgData +0x0401FFFC ; Data + { + * (+RW,+ZI) + } +} + +;reserved for device information +DEVICE_INFO 0 ; Device Info +{ + DevInfo 0 ; Info structure + { + stm32_device_info.o + } +} diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7s3xx_flash.sct b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7s3xx_flash.sct new file mode 100644 index 00000000000..d6063e6a1fb --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7s3xx_flash.sct @@ -0,0 +1,34 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LOAD_FLASH 0x08000000 0x08010000 { ; load region size_region + ER_ROM 0x08000000 0x08010000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + ER_ITCM 0x00000000 0x00010000 { ; + } + + RW_DTCM 0x20000000 0x00010000 { ; RW data + *(STACK) + *(HEAP) + } + + RW_SRAMAHB 0x30000000 0x8000 { + } + + RW_BKPSRAM 0x38800000 0x1000 { + } + + RW_RAM 0x24000000 0x00072000-0x400 { + .ANY (+RW +ZI) + } + + RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 { + *(noncacheable_buffer) + } +} \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7s3xx_sram.sct b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7s3xx_sram.sct new file mode 100644 index 00000000000..b21e20c90f7 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7s3xx_sram.sct @@ -0,0 +1,34 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LOAD_FLASH 0x24050000 0x00022000 { ; load region size_region + ER_ROM 0x24050000 0x00022000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + ER_ITCM 0x00000000 0x00010000 { ; + } + + RW_DTCM 0x20000000 0x00010000 { ; RW data + *(STACK) + *(HEAP) + } + + RW_SRAMAHB 0x30000000 0x8000 { + } + + RW_BKPSRAM 0x38800000 0x1000 { + } + + RW_RAM 0x24000000 0x00050000-0x400 { + .ANY (+RW +ZI) + } + + RW_NONCACHEABLEBUFFER 0x24050000-0x400 0x400 { + *(noncacheable_buffer) + } +} \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7s7xx_flash.sct b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7s7xx_flash.sct new file mode 100644 index 00000000000..d6063e6a1fb --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7s7xx_flash.sct @@ -0,0 +1,34 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LOAD_FLASH 0x08000000 0x08010000 { ; load region size_region + ER_ROM 0x08000000 0x08010000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + ER_ITCM 0x00000000 0x00010000 { ; + } + + RW_DTCM 0x20000000 0x00010000 { ; RW data + *(STACK) + *(HEAP) + } + + RW_SRAMAHB 0x30000000 0x8000 { + } + + RW_BKPSRAM 0x38800000 0x1000 { + } + + RW_RAM 0x24000000 0x00072000-0x400 { + .ANY (+RW +ZI) + } + + RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 { + *(noncacheable_buffer) + } +} \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7s7xx_sram.sct b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7s7xx_sram.sct new file mode 100644 index 00000000000..b21e20c90f7 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/linker/stm32h7s7xx_sram.sct @@ -0,0 +1,34 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LOAD_FLASH 0x24050000 0x00022000 { ; load region size_region + ER_ROM 0x24050000 0x00022000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + ER_ITCM 0x00000000 0x00010000 { ; + } + + RW_DTCM 0x20000000 0x00010000 { ; RW data + *(STACK) + *(HEAP) + } + + RW_SRAMAHB 0x30000000 0x8000 { + } + + RW_BKPSRAM 0x38800000 0x1000 { + } + + RW_RAM 0x24000000 0x00050000-0x400 { + .ANY (+RW +ZI) + } + + RW_NONCACHEABLEBUFFER 0x24050000-0x400 0x400 { + *(noncacheable_buffer) + } +} \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/startup_stm32h7r3xx.s b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/startup_stm32h7r3xx.s new file mode 100644 index 00000000000..105df6fd08b --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/startup_stm32h7r3xx.s @@ -0,0 +1,613 @@ +;******************************************************************************* +;* File Name : startup_stm32h7r3xx.s +;* Author : MCD Application Team +;* Description : STM32H7R3xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;* Copyright (c) 2023 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + ; External Interrupts + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection + DCD 0 ; Reserved + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD IWDG_IRQHandler ; Internal Watchdog + DCD WWDG_IRQHandler ; Window Watchdog + DCD RCC_IRQHandler ; RCC global interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FLASH_IRQHandler ; FLASH interrupts + DCD RAMECC_IRQHandler ; RAMECC interrupts + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TAMP_IRQHandler ; Tamper and TimeStamp interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD EXTI5_IRQHandler ; EXTI Line5 + DCD EXTI6_IRQHandler ; EXTI Line6 + DCD EXTI7_IRQHandler ; EXTI Line7 + DCD EXTI8_IRQHandler ; EXTI Line8 + DCD EXTI9_IRQHandler ; EXTI Line9 + DCD EXTI10_IRQHandler ; EXTI Line10 + DCD EXTI11_IRQHandler ; EXTI Line11 + DCD EXTI12_IRQHandler ; EXTI Line12 + DCD EXTI13_IRQHandler ; EXTI Line13 + DCD EXTI14_IRQHandler ; EXTI Line14 + DCD EXTI15_IRQHandler ; EXTI Line15 + DCD RTC_IRQHandler ; RTC wakeup and alarm interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PKA_IRQHandler ; PKA + DCD HASH_IRQHandler ; HASH + DCD RNG_IRQHandler ; RNG + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 + DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 + DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 + DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 + DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 + DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 + DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 + DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD TIM9_IRQHandler ; TIM9 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD SPI3_IRQHandler ; SPI3 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD HPDMA1_Channel0_IRQHandler ; HPDMA1 Channel 0 + DCD HPDMA1_Channel1_IRQHandler ; HPDMA1 Channel 1 + DCD HPDMA1_Channel2_IRQHandler ; HPDMA1 Channel 2 + DCD HPDMA1_Channel3_IRQHandler ; HPDMA1 Channel 3 + DCD HPDMA1_Channel4_IRQHandler ; HPDMA1 Channel 4 + DCD HPDMA1_Channel5_IRQHandler ; HPDMA1 Channel 5 + DCD HPDMA1_Channel6_IRQHandler ; HPDMA1 Channel 6 + DCD HPDMA1_Channel7_IRQHandler ; HPDMA1 Channel 7 + DCD SAI1_A_IRQHandler ; Serial Audio Interface 1 block A + DCD SAI1_B_IRQHandler ; Serial Audio Interface 1 block B + DCD SAI2_A_IRQHandler ; Serial Audio Interface 2 block A + DCD SAI2_B_IRQHandler ; Serial Audio Interface 2 block B + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD I3C1_EV_IRQHandler ; I3C1 Event + DCD I3C1_ER_IRQHandler ; I3C1 Error + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD ETH_IRQHandler ; Ethernet + DCD CORDIC_IRQHandler ; CORDIC + DCD GFXTIM_IRQHandler ; GFXTIM + DCD DCMIPP_IRQHandler ; DCMIPP + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2D_IRQHandler ; DMA2D + DCD JPEG_IRQHandler ; JPEG + DCD GFXMMU_IRQHandler ; GFXMMU + DCD I3C1_WKUP_IRQHandler ; I3C1 wakeup + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD XSPI1_IRQHandler ; XSPI1 + DCD XSPI2_IRQHandler ; XSPI2 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD LPTIM1_IRQHandler ; LP TIM1 + DCD LPTIM2_IRQHandler ; LP TIM2 + DCD LPTIM3_IRQHandler ; LP TIM3 + DCD LPTIM4_IRQHandler ; LP TIM4 + DCD LPTIM5_IRQHandler ; LP TIM5 + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD MDIOS_IRQHandler ; MDIOS + DCD ADF1_FLT0_IRQHandler ; ADF1 Filter 0 + DCD CRS_IRQHandler ; CRS + DCD UCPD1_IRQHandler ; UCPD1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD PSSI_IRQHandler ; PSSI + DCD LPUART1_IRQHandler ; LP UART1 + DCD WAKEUP_PIN_IRQHandler ; Wake-up pins interrupt + DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8 + DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9 + DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10 + DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11 + DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12 + DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13 + DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14 + DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15 + DCD HPDMA1_Channel8_IRQHandler ; HPDMA1 Channel 8 + DCD HPDMA1_Channel9_IRQHandler ; HPDMA1 Channel 9 + DCD HPDMA1_Channel10_IRQHandler ; HPDMA1 Channel 10 + DCD HPDMA1_Channel11_IRQHandler ; HPDMA1 Channel 11 + DCD HPDMA1_Channel12_IRQHandler ; HPDMA1 Channel 12 + DCD HPDMA1_Channel13_IRQHandler ; HPDMA1 Channel 13 + DCD HPDMA1_Channel14_IRQHandler ; HPDMA1 Channel 14 + DCD HPDMA1_Channel15_IRQHandler ; HPDMA1 Channel 15 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt 1 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt 1 + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT DTS_IRQHandler [WEAK] + EXPORT IWDG_IRQHandler [WEAK] + EXPORT WWDG_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RAMECC_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT TAMP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT PKA_IRQHandler [WEAK] + EXPORT HASH_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT GPDMA1_Channel0_IRQHandler [WEAK] + EXPORT GPDMA1_Channel1_IRQHandler [WEAK] + EXPORT GPDMA1_Channel2_IRQHandler [WEAK] + EXPORT GPDMA1_Channel3_IRQHandler [WEAK] + EXPORT GPDMA1_Channel4_IRQHandler [WEAK] + EXPORT GPDMA1_Channel5_IRQHandler [WEAK] + EXPORT GPDMA1_Channel6_IRQHandler [WEAK] + EXPORT GPDMA1_Channel7_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT HPDMA1_Channel0_IRQHandler [WEAK] + EXPORT HPDMA1_Channel1_IRQHandler [WEAK] + EXPORT HPDMA1_Channel2_IRQHandler [WEAK] + EXPORT HPDMA1_Channel3_IRQHandler [WEAK] + EXPORT HPDMA1_Channel4_IRQHandler [WEAK] + EXPORT HPDMA1_Channel5_IRQHandler [WEAK] + EXPORT HPDMA1_Channel6_IRQHandler [WEAK] + EXPORT HPDMA1_Channel7_IRQHandler [WEAK] + EXPORT SAI1_A_IRQHandler [WEAK] + EXPORT SAI1_B_IRQHandler [WEAK] + EXPORT SAI2_A_IRQHandler [WEAK] + EXPORT SAI2_B_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT I3C1_EV_IRQHandler [WEAK] + EXPORT I3C1_ER_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT GFXTIM_IRQHandler [WEAK] + EXPORT DCMIPP_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT GFXMMU_IRQHandler [WEAK] + EXPORT I3C1_WKUP_IRQHandler [WEAK] + EXPORT XSPI1_IRQHandler [WEAK] + EXPORT XSPI2_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT TIM12_IRQHandler [WEAK] + EXPORT TIM13_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT ADF1_FLT0_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT UCPD1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT PSSI_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + EXPORT GPDMA1_Channel8_IRQHandler [WEAK] + EXPORT GPDMA1_Channel9_IRQHandler [WEAK] + EXPORT GPDMA1_Channel10_IRQHandler [WEAK] + EXPORT GPDMA1_Channel11_IRQHandler [WEAK] + EXPORT GPDMA1_Channel12_IRQHandler [WEAK] + EXPORT GPDMA1_Channel13_IRQHandler [WEAK] + EXPORT GPDMA1_Channel14_IRQHandler [WEAK] + EXPORT GPDMA1_Channel15_IRQHandler [WEAK] + EXPORT HPDMA1_Channel8_IRQHandler [WEAK] + EXPORT HPDMA1_Channel9_IRQHandler [WEAK] + EXPORT HPDMA1_Channel10_IRQHandler [WEAK] + EXPORT HPDMA1_Channel11_IRQHandler [WEAK] + EXPORT HPDMA1_Channel12_IRQHandler [WEAK] + EXPORT HPDMA1_Channel13_IRQHandler [WEAK] + EXPORT HPDMA1_Channel14_IRQHandler [WEAK] + EXPORT HPDMA1_Channel15_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + +PVD_PVM_IRQHandler +DTS_IRQHandler +IWDG_IRQHandler +WWDG_IRQHandler +RCC_IRQHandler +FLASH_IRQHandler +RAMECC_IRQHandler +FPU_IRQHandler +TAMP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +RTC_IRQHandler +PKA_IRQHandler +HASH_IRQHandler +RNG_IRQHandler +ADC1_2_IRQHandler +GPDMA1_Channel0_IRQHandler +GPDMA1_Channel1_IRQHandler +GPDMA1_Channel2_IRQHandler +GPDMA1_Channel3_IRQHandler +GPDMA1_Channel4_IRQHandler +GPDMA1_Channel5_IRQHandler +GPDMA1_Channel6_IRQHandler +GPDMA1_Channel7_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +TIM5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +TIM9_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +HPDMA1_Channel0_IRQHandler +HPDMA1_Channel1_IRQHandler +HPDMA1_Channel2_IRQHandler +HPDMA1_Channel3_IRQHandler +HPDMA1_Channel4_IRQHandler +HPDMA1_Channel5_IRQHandler +HPDMA1_Channel6_IRQHandler +HPDMA1_Channel7_IRQHandler +SAI1_A_IRQHandler +SAI1_B_IRQHandler +SAI2_A_IRQHandler +SAI2_B_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +I3C1_EV_IRQHandler +I3C1_ER_IRQHandler +OTG_HS_IRQHandler +ETH_IRQHandler +CORDIC_IRQHandler +GFXTIM_IRQHandler +DCMIPP_IRQHandler +DMA2D_IRQHandler +JPEG_IRQHandler +GFXMMU_IRQHandler +I3C1_WKUP_IRQHandler +XSPI1_IRQHandler +XSPI2_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +SDMMC2_IRQHandler +OTG_FS_IRQHandler +TIM12_IRQHandler +TIM13_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +SPDIF_RX_IRQHandler +MDIOS_IRQHandler +ADF1_FLT0_IRQHandler +CRS_IRQHandler +UCPD1_IRQHandler +CEC_IRQHandler +PSSI_IRQHandler +LPUART1_IRQHandler +WAKEUP_PIN_IRQHandler +GPDMA1_Channel8_IRQHandler +GPDMA1_Channel9_IRQHandler +GPDMA1_Channel10_IRQHandler +GPDMA1_Channel11_IRQHandler +GPDMA1_Channel12_IRQHandler +GPDMA1_Channel13_IRQHandler +GPDMA1_Channel14_IRQHandler +GPDMA1_Channel15_IRQHandler +HPDMA1_Channel8_IRQHandler +HPDMA1_Channel9_IRQHandler +HPDMA1_Channel10_IRQHandler +HPDMA1_Channel11_IRQHandler +HPDMA1_Channel12_IRQHandler +HPDMA1_Channel13_IRQHandler +HPDMA1_Channel14_IRQHandler +HPDMA1_Channel15_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN2_IT1_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/startup_stm32h7r7xx.s b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/startup_stm32h7r7xx.s new file mode 100644 index 00000000000..b00611f1e3d --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/startup_stm32h7r7xx.s @@ -0,0 +1,623 @@ +;******************************************************************************* +;* File Name : startup_stm32h7r7xx.s +;* Author : MCD Application Team +;* Description : STM32H7R7xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;* Copyright (c) 2023 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + ; External Interrupts + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection + DCD 0 ; Reserved + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD IWDG_IRQHandler ; Internal Watchdog + DCD WWDG_IRQHandler ; Window Watchdog + DCD RCC_IRQHandler ; RCC global interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FLASH_IRQHandler ; FLASH interrupts + DCD RAMECC_IRQHandler ; RAMECC interrupts + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TAMP_IRQHandler ; Tamper and TimeStamp interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD EXTI5_IRQHandler ; EXTI Line5 + DCD EXTI6_IRQHandler ; EXTI Line6 + DCD EXTI7_IRQHandler ; EXTI Line7 + DCD EXTI8_IRQHandler ; EXTI Line8 + DCD EXTI9_IRQHandler ; EXTI Line9 + DCD EXTI10_IRQHandler ; EXTI Line10 + DCD EXTI11_IRQHandler ; EXTI Line11 + DCD EXTI12_IRQHandler ; EXTI Line12 + DCD EXTI13_IRQHandler ; EXTI Line13 + DCD EXTI14_IRQHandler ; EXTI Line14 + DCD EXTI15_IRQHandler ; EXTI Line15 + DCD RTC_IRQHandler ; RTC wakeup and alarm interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PKA_IRQHandler ; PKA + DCD HASH_IRQHandler ; HASH + DCD RNG_IRQHandler ; RNG + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 + DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 + DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 + DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 + DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 + DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 + DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 + DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD TIM9_IRQHandler ; TIM9 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD SPI3_IRQHandler ; SPI3 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD HPDMA1_Channel0_IRQHandler ; HPDMA1 Channel 0 + DCD HPDMA1_Channel1_IRQHandler ; HPDMA1 Channel 1 + DCD HPDMA1_Channel2_IRQHandler ; HPDMA1 Channel 2 + DCD HPDMA1_Channel3_IRQHandler ; HPDMA1 Channel 3 + DCD HPDMA1_Channel4_IRQHandler ; HPDMA1 Channel 4 + DCD HPDMA1_Channel5_IRQHandler ; HPDMA1 Channel 5 + DCD HPDMA1_Channel6_IRQHandler ; HPDMA1 Channel 6 + DCD HPDMA1_Channel7_IRQHandler ; HPDMA1 Channel 7 + DCD SAI1_A_IRQHandler ; Serial Audio Interface 1 block A + DCD SAI1_B_IRQHandler ; Serial Audio Interface 1 block B + DCD SAI2_A_IRQHandler ; Serial Audio Interface 2 block A + DCD SAI2_B_IRQHandler ; Serial Audio Interface 2 block B + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD I3C1_EV_IRQHandler ; I3C1 Event + DCD I3C1_ER_IRQHandler ; I3C1 Error + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD ETH_IRQHandler ; Ethernet + DCD CORDIC_IRQHandler ; CORDIC + DCD GFXTIM_IRQHandler ; GFXTIM + DCD DCMIPP_IRQHandler ; DCMIPP + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD JPEG_IRQHandler ; JPEG + DCD GFXMMU_IRQHandler ; GFXMMU + DCD I3C1_WKUP_IRQHandler ; I3C1 wakeup + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD XSPI1_IRQHandler ; XSPI1 + DCD XSPI2_IRQHandler ; XSPI2 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD LPTIM1_IRQHandler ; LP TIM1 + DCD LPTIM2_IRQHandler ; LP TIM2 + DCD LPTIM3_IRQHandler ; LP TIM3 + DCD LPTIM4_IRQHandler ; LP TIM4 + DCD LPTIM5_IRQHandler ; LP TIM5 + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD MDIOS_IRQHandler ; MDIOS + DCD ADF1_FLT0_IRQHandler ; ADF1 Filter 0 + DCD CRS_IRQHandler ; CRS + DCD UCPD1_IRQHandler ; UCPD1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD PSSI_IRQHandler ; PSSI + DCD LPUART1_IRQHandler ; LP UART1 + DCD WAKEUP_PIN_IRQHandler ; Wake-up pins interrupt + DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8 + DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9 + DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10 + DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11 + DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12 + DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13 + DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14 + DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15 + DCD HPDMA1_Channel8_IRQHandler ; HPDMA1 Channel 8 + DCD HPDMA1_Channel9_IRQHandler ; HPDMA1 Channel 9 + DCD HPDMA1_Channel10_IRQHandler ; HPDMA1 Channel 10 + DCD HPDMA1_Channel11_IRQHandler ; HPDMA1 Channel 11 + DCD HPDMA1_Channel12_IRQHandler ; HPDMA1 Channel 12 + DCD HPDMA1_Channel13_IRQHandler ; HPDMA1 Channel 13 + DCD HPDMA1_Channel14_IRQHandler ; HPDMA1 Channel 14 + DCD HPDMA1_Channel15_IRQHandler ; HPDMA1 Channel 15 + DCD GPU2D_IRQHandler ; GPU2D + DCD GPU2D_ER_IRQHandler ; GPU2D error + DCD ICACHE_IRQHandler ; ICACHE + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt 1 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt 1 + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT DTS_IRQHandler [WEAK] + EXPORT IWDG_IRQHandler [WEAK] + EXPORT WWDG_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RAMECC_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT TAMP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT PKA_IRQHandler [WEAK] + EXPORT HASH_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT GPDMA1_Channel0_IRQHandler [WEAK] + EXPORT GPDMA1_Channel1_IRQHandler [WEAK] + EXPORT GPDMA1_Channel2_IRQHandler [WEAK] + EXPORT GPDMA1_Channel3_IRQHandler [WEAK] + EXPORT GPDMA1_Channel4_IRQHandler [WEAK] + EXPORT GPDMA1_Channel5_IRQHandler [WEAK] + EXPORT GPDMA1_Channel6_IRQHandler [WEAK] + EXPORT GPDMA1_Channel7_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT HPDMA1_Channel0_IRQHandler [WEAK] + EXPORT HPDMA1_Channel1_IRQHandler [WEAK] + EXPORT HPDMA1_Channel2_IRQHandler [WEAK] + EXPORT HPDMA1_Channel3_IRQHandler [WEAK] + EXPORT HPDMA1_Channel4_IRQHandler [WEAK] + EXPORT HPDMA1_Channel5_IRQHandler [WEAK] + EXPORT HPDMA1_Channel6_IRQHandler [WEAK] + EXPORT HPDMA1_Channel7_IRQHandler [WEAK] + EXPORT SAI1_A_IRQHandler [WEAK] + EXPORT SAI1_B_IRQHandler [WEAK] + EXPORT SAI2_A_IRQHandler [WEAK] + EXPORT SAI2_B_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT I3C1_EV_IRQHandler [WEAK] + EXPORT I3C1_ER_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT GFXTIM_IRQHandler [WEAK] + EXPORT DCMIPP_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT GFXMMU_IRQHandler [WEAK] + EXPORT I3C1_WKUP_IRQHandler [WEAK] + EXPORT XSPI1_IRQHandler [WEAK] + EXPORT XSPI2_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT TIM12_IRQHandler [WEAK] + EXPORT TIM13_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT ADF1_FLT0_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT UCPD1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT PSSI_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + EXPORT GPDMA1_Channel8_IRQHandler [WEAK] + EXPORT GPDMA1_Channel9_IRQHandler [WEAK] + EXPORT GPDMA1_Channel10_IRQHandler [WEAK] + EXPORT GPDMA1_Channel11_IRQHandler [WEAK] + EXPORT GPDMA1_Channel12_IRQHandler [WEAK] + EXPORT GPDMA1_Channel13_IRQHandler [WEAK] + EXPORT GPDMA1_Channel14_IRQHandler [WEAK] + EXPORT GPDMA1_Channel15_IRQHandler [WEAK] + EXPORT HPDMA1_Channel8_IRQHandler [WEAK] + EXPORT HPDMA1_Channel9_IRQHandler [WEAK] + EXPORT HPDMA1_Channel10_IRQHandler [WEAK] + EXPORT HPDMA1_Channel11_IRQHandler [WEAK] + EXPORT HPDMA1_Channel12_IRQHandler [WEAK] + EXPORT HPDMA1_Channel13_IRQHandler [WEAK] + EXPORT HPDMA1_Channel14_IRQHandler [WEAK] + EXPORT HPDMA1_Channel15_IRQHandler [WEAK] + EXPORT GPU2D_IRQHandler [WEAK] + EXPORT GPU2D_ER_IRQHandler [WEAK] + EXPORT ICACHE_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + +PVD_PVM_IRQHandler +DTS_IRQHandler +IWDG_IRQHandler +WWDG_IRQHandler +RCC_IRQHandler +FLASH_IRQHandler +RAMECC_IRQHandler +FPU_IRQHandler +TAMP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +RTC_IRQHandler +PKA_IRQHandler +HASH_IRQHandler +RNG_IRQHandler +ADC1_2_IRQHandler +GPDMA1_Channel0_IRQHandler +GPDMA1_Channel1_IRQHandler +GPDMA1_Channel2_IRQHandler +GPDMA1_Channel3_IRQHandler +GPDMA1_Channel4_IRQHandler +GPDMA1_Channel5_IRQHandler +GPDMA1_Channel6_IRQHandler +GPDMA1_Channel7_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +TIM5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +TIM9_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +HPDMA1_Channel0_IRQHandler +HPDMA1_Channel1_IRQHandler +HPDMA1_Channel2_IRQHandler +HPDMA1_Channel3_IRQHandler +HPDMA1_Channel4_IRQHandler +HPDMA1_Channel5_IRQHandler +HPDMA1_Channel6_IRQHandler +HPDMA1_Channel7_IRQHandler +SAI1_A_IRQHandler +SAI1_B_IRQHandler +SAI2_A_IRQHandler +SAI2_B_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +I3C1_EV_IRQHandler +I3C1_ER_IRQHandler +OTG_HS_IRQHandler +ETH_IRQHandler +CORDIC_IRQHandler +GFXTIM_IRQHandler +DCMIPP_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +JPEG_IRQHandler +GFXMMU_IRQHandler +I3C1_WKUP_IRQHandler +XSPI1_IRQHandler +XSPI2_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +SDMMC2_IRQHandler +OTG_FS_IRQHandler +TIM12_IRQHandler +TIM13_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +SPDIF_RX_IRQHandler +MDIOS_IRQHandler +ADF1_FLT0_IRQHandler +CRS_IRQHandler +UCPD1_IRQHandler +CEC_IRQHandler +PSSI_IRQHandler +LPUART1_IRQHandler +WAKEUP_PIN_IRQHandler +GPDMA1_Channel8_IRQHandler +GPDMA1_Channel9_IRQHandler +GPDMA1_Channel10_IRQHandler +GPDMA1_Channel11_IRQHandler +GPDMA1_Channel12_IRQHandler +GPDMA1_Channel13_IRQHandler +GPDMA1_Channel14_IRQHandler +GPDMA1_Channel15_IRQHandler +HPDMA1_Channel8_IRQHandler +HPDMA1_Channel9_IRQHandler +HPDMA1_Channel10_IRQHandler +HPDMA1_Channel11_IRQHandler +HPDMA1_Channel12_IRQHandler +HPDMA1_Channel13_IRQHandler +HPDMA1_Channel14_IRQHandler +HPDMA1_Channel15_IRQHandler +GPU2D_IRQHandler +GPU2D_ER_IRQHandler +ICACHE_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN2_IT1_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/startup_stm32h7s3xx.s b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/startup_stm32h7s3xx.s new file mode 100644 index 00000000000..a9f96f9fa27 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/startup_stm32h7s3xx.s @@ -0,0 +1,623 @@ +;******************************************************************************* +;* File Name : startup_stm32h7s3xx.s +;* Author : MCD Application Team +;* Description : STM32H7S3xx Crypto devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;* Copyright (c) 2023 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + ; External Interrupts + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection + DCD 0 ; Reserved + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD IWDG_IRQHandler ; Internal Watchdog + DCD WWDG_IRQHandler ; Window Watchdog + DCD RCC_IRQHandler ; RCC global interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FLASH_IRQHandler ; FLASH interrupts + DCD RAMECC_IRQHandler ; RAMECC interrupts + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TAMP_IRQHandler ; Tamper and TimeStamp interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD EXTI5_IRQHandler ; EXTI Line5 + DCD EXTI6_IRQHandler ; EXTI Line6 + DCD EXTI7_IRQHandler ; EXTI Line7 + DCD EXTI8_IRQHandler ; EXTI Line8 + DCD EXTI9_IRQHandler ; EXTI Line9 + DCD EXTI10_IRQHandler ; EXTI Line10 + DCD EXTI11_IRQHandler ; EXTI Line11 + DCD EXTI12_IRQHandler ; EXTI Line12 + DCD EXTI13_IRQHandler ; EXTI Line13 + DCD EXTI14_IRQHandler ; EXTI Line14 + DCD EXTI15_IRQHandler ; EXTI Line15 + DCD RTC_IRQHandler ; RTC wakeup and alarm interrupts through EXTI Line detection + DCD SAES_IRQHandler ; SAES + DCD CRYP_IRQHandler ; CRYP + DCD PKA_IRQHandler ; PKA + DCD HASH_IRQHandler ; HASH + DCD RNG_IRQHandler ; RNG + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 + DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 + DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 + DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 + DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 + DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 + DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 + DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD TIM9_IRQHandler ; TIM9 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD SPI3_IRQHandler ; SPI3 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD HPDMA1_Channel0_IRQHandler ; HPDMA1 Channel 0 + DCD HPDMA1_Channel1_IRQHandler ; HPDMA1 Channel 1 + DCD HPDMA1_Channel2_IRQHandler ; HPDMA1 Channel 2 + DCD HPDMA1_Channel3_IRQHandler ; HPDMA1 Channel 3 + DCD HPDMA1_Channel4_IRQHandler ; HPDMA1 Channel 4 + DCD HPDMA1_Channel5_IRQHandler ; HPDMA1 Channel 5 + DCD HPDMA1_Channel6_IRQHandler ; HPDMA1 Channel 6 + DCD HPDMA1_Channel7_IRQHandler ; HPDMA1 Channel 7 + DCD SAI1_A_IRQHandler ; Serial Audio Interface 1 block A + DCD SAI1_B_IRQHandler ; Serial Audio Interface 1 block B + DCD SAI2_A_IRQHandler ; Serial Audio Interface 2 block A + DCD SAI2_B_IRQHandler ; Serial Audio Interface 2 block B + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD I3C1_EV_IRQHandler ; I3C1 Event + DCD I3C1_ER_IRQHandler ; I3C1 Error + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD ETH_IRQHandler ; Ethernet + DCD CORDIC_IRQHandler ; CORDIC + DCD GFXTIM_IRQHandler ; GFXTIM + DCD DCMIPP_IRQHandler ; DCMIPP + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2D_IRQHandler ; DMA2D + DCD JPEG_IRQHandler ; JPEG + DCD GFXMMU_IRQHandler ; GFXMMU + DCD I3C1_WKUP_IRQHandler ; I3C1 wakeup + DCD MCE1_IRQHandler ; MCE1 + DCD MCE2_IRQHandler ; MCE2 + DCD MCE3_IRQHandler ; MCE3 + DCD XSPI1_IRQHandler ; XSPI1 + DCD XSPI2_IRQHandler ; XSPI2 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD LPTIM1_IRQHandler ; LP TIM1 + DCD LPTIM2_IRQHandler ; LP TIM2 + DCD LPTIM3_IRQHandler ; LP TIM3 + DCD LPTIM4_IRQHandler ; LP TIM4 + DCD LPTIM5_IRQHandler ; LP TIM5 + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD MDIOS_IRQHandler ; MDIOS + DCD ADF1_FLT0_IRQHandler ; ADF1 Filter 0 + DCD CRS_IRQHandler ; CRS + DCD UCPD1_IRQHandler ; UCPD1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD PSSI_IRQHandler ; PSSI + DCD LPUART1_IRQHandler ; LP UART1 + DCD WAKEUP_PIN_IRQHandler ; Wake-up pins interrupt + DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8 + DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9 + DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10 + DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11 + DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12 + DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13 + DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14 + DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15 + DCD HPDMA1_Channel8_IRQHandler ; HPDMA1 Channel 8 + DCD HPDMA1_Channel9_IRQHandler ; HPDMA1 Channel 9 + DCD HPDMA1_Channel10_IRQHandler ; HPDMA1 Channel 10 + DCD HPDMA1_Channel11_IRQHandler ; HPDMA1 Channel 11 + DCD HPDMA1_Channel12_IRQHandler ; HPDMA1 Channel 12 + DCD HPDMA1_Channel13_IRQHandler ; HPDMA1 Channel 13 + DCD HPDMA1_Channel14_IRQHandler ; HPDMA1 Channel 14 + DCD HPDMA1_Channel15_IRQHandler ; HPDMA1 Channel 15 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt 1 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt 1 + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT DTS_IRQHandler [WEAK] + EXPORT IWDG_IRQHandler [WEAK] + EXPORT WWDG_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RAMECC_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT TAMP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT SAES_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT PKA_IRQHandler [WEAK] + EXPORT HASH_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT GPDMA1_Channel0_IRQHandler [WEAK] + EXPORT GPDMA1_Channel1_IRQHandler [WEAK] + EXPORT GPDMA1_Channel2_IRQHandler [WEAK] + EXPORT GPDMA1_Channel3_IRQHandler [WEAK] + EXPORT GPDMA1_Channel4_IRQHandler [WEAK] + EXPORT GPDMA1_Channel5_IRQHandler [WEAK] + EXPORT GPDMA1_Channel6_IRQHandler [WEAK] + EXPORT GPDMA1_Channel7_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT HPDMA1_Channel0_IRQHandler [WEAK] + EXPORT HPDMA1_Channel1_IRQHandler [WEAK] + EXPORT HPDMA1_Channel2_IRQHandler [WEAK] + EXPORT HPDMA1_Channel3_IRQHandler [WEAK] + EXPORT HPDMA1_Channel4_IRQHandler [WEAK] + EXPORT HPDMA1_Channel5_IRQHandler [WEAK] + EXPORT HPDMA1_Channel6_IRQHandler [WEAK] + EXPORT HPDMA1_Channel7_IRQHandler [WEAK] + EXPORT SAI1_A_IRQHandler [WEAK] + EXPORT SAI1_B_IRQHandler [WEAK] + EXPORT SAI2_A_IRQHandler [WEAK] + EXPORT SAI2_B_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT I3C1_EV_IRQHandler [WEAK] + EXPORT I3C1_ER_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT GFXTIM_IRQHandler [WEAK] + EXPORT DCMIPP_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT GFXMMU_IRQHandler [WEAK] + EXPORT I3C1_WKUP_IRQHandler [WEAK] + EXPORT MCE1_IRQHandler [WEAK] + EXPORT MCE2_IRQHandler [WEAK] + EXPORT MCE3_IRQHandler [WEAK] + EXPORT XSPI1_IRQHandler [WEAK] + EXPORT XSPI2_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT TIM12_IRQHandler [WEAK] + EXPORT TIM13_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT ADF1_FLT0_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT UCPD1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT PSSI_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + EXPORT GPDMA1_Channel8_IRQHandler [WEAK] + EXPORT GPDMA1_Channel9_IRQHandler [WEAK] + EXPORT GPDMA1_Channel10_IRQHandler [WEAK] + EXPORT GPDMA1_Channel11_IRQHandler [WEAK] + EXPORT GPDMA1_Channel12_IRQHandler [WEAK] + EXPORT GPDMA1_Channel13_IRQHandler [WEAK] + EXPORT GPDMA1_Channel14_IRQHandler [WEAK] + EXPORT GPDMA1_Channel15_IRQHandler [WEAK] + EXPORT HPDMA1_Channel8_IRQHandler [WEAK] + EXPORT HPDMA1_Channel9_IRQHandler [WEAK] + EXPORT HPDMA1_Channel10_IRQHandler [WEAK] + EXPORT HPDMA1_Channel11_IRQHandler [WEAK] + EXPORT HPDMA1_Channel12_IRQHandler [WEAK] + EXPORT HPDMA1_Channel13_IRQHandler [WEAK] + EXPORT HPDMA1_Channel14_IRQHandler [WEAK] + EXPORT HPDMA1_Channel15_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + +PVD_PVM_IRQHandler +DTS_IRQHandler +IWDG_IRQHandler +WWDG_IRQHandler +RCC_IRQHandler +FLASH_IRQHandler +RAMECC_IRQHandler +FPU_IRQHandler +TAMP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +RTC_IRQHandler +SAES_IRQHandler +CRYP_IRQHandler +PKA_IRQHandler +HASH_IRQHandler +RNG_IRQHandler +ADC1_2_IRQHandler +GPDMA1_Channel0_IRQHandler +GPDMA1_Channel1_IRQHandler +GPDMA1_Channel2_IRQHandler +GPDMA1_Channel3_IRQHandler +GPDMA1_Channel4_IRQHandler +GPDMA1_Channel5_IRQHandler +GPDMA1_Channel6_IRQHandler +GPDMA1_Channel7_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +TIM5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +TIM9_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +HPDMA1_Channel0_IRQHandler +HPDMA1_Channel1_IRQHandler +HPDMA1_Channel2_IRQHandler +HPDMA1_Channel3_IRQHandler +HPDMA1_Channel4_IRQHandler +HPDMA1_Channel5_IRQHandler +HPDMA1_Channel6_IRQHandler +HPDMA1_Channel7_IRQHandler +SAI1_A_IRQHandler +SAI1_B_IRQHandler +SAI2_A_IRQHandler +SAI2_B_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +I3C1_EV_IRQHandler +I3C1_ER_IRQHandler +OTG_HS_IRQHandler +ETH_IRQHandler +CORDIC_IRQHandler +GFXTIM_IRQHandler +DCMIPP_IRQHandler +DMA2D_IRQHandler +JPEG_IRQHandler +GFXMMU_IRQHandler +I3C1_WKUP_IRQHandler +MCE1_IRQHandler +MCE2_IRQHandler +MCE3_IRQHandler +XSPI1_IRQHandler +XSPI2_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +SDMMC2_IRQHandler +OTG_FS_IRQHandler +TIM12_IRQHandler +TIM13_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +SPDIF_RX_IRQHandler +MDIOS_IRQHandler +ADF1_FLT0_IRQHandler +CRS_IRQHandler +UCPD1_IRQHandler +CEC_IRQHandler +PSSI_IRQHandler +LPUART1_IRQHandler +WAKEUP_PIN_IRQHandler +GPDMA1_Channel8_IRQHandler +GPDMA1_Channel9_IRQHandler +GPDMA1_Channel10_IRQHandler +GPDMA1_Channel11_IRQHandler +GPDMA1_Channel12_IRQHandler +GPDMA1_Channel13_IRQHandler +GPDMA1_Channel14_IRQHandler +GPDMA1_Channel15_IRQHandler +HPDMA1_Channel8_IRQHandler +HPDMA1_Channel9_IRQHandler +HPDMA1_Channel10_IRQHandler +HPDMA1_Channel11_IRQHandler +HPDMA1_Channel12_IRQHandler +HPDMA1_Channel13_IRQHandler +HPDMA1_Channel14_IRQHandler +HPDMA1_Channel15_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN2_IT1_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/startup_stm32h7s7xx.s b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/startup_stm32h7s7xx.s new file mode 100644 index 00000000000..1fed8690404 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/startup_stm32h7s7xx.s @@ -0,0 +1,633 @@ +;******************************************************************************* +;* File Name : startup_stm32h7s7xx.s +;* Author : MCD Application Team +;* Description : STM32H7S7xx Crypto devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;* Copyright (c) 2023 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + ; External Interrupts + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection + DCD 0 ; Reserved + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD IWDG_IRQHandler ; Internal Watchdog + DCD WWDG_IRQHandler ; Window Watchdog + DCD RCC_IRQHandler ; RCC global interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FLASH_IRQHandler ; FLASH interrupts + DCD RAMECC_IRQHandler ; RAMECC interrupts + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TAMP_IRQHandler ; Tamper and TimeStamp interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD EXTI5_IRQHandler ; EXTI Line5 + DCD EXTI6_IRQHandler ; EXTI Line6 + DCD EXTI7_IRQHandler ; EXTI Line7 + DCD EXTI8_IRQHandler ; EXTI Line8 + DCD EXTI9_IRQHandler ; EXTI Line9 + DCD EXTI10_IRQHandler ; EXTI Line10 + DCD EXTI11_IRQHandler ; EXTI Line11 + DCD EXTI12_IRQHandler ; EXTI Line12 + DCD EXTI13_IRQHandler ; EXTI Line13 + DCD EXTI14_IRQHandler ; EXTI Line14 + DCD EXTI15_IRQHandler ; EXTI Line15 + DCD RTC_IRQHandler ; RTC wakeup and alarm interrupts through EXTI Line detection + DCD SAES_IRQHandler ; SAES + DCD CRYP_IRQHandler ; CRYP + DCD PKA_IRQHandler ; PKA + DCD HASH_IRQHandler ; HASH + DCD RNG_IRQHandler ; RNG + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 + DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 + DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 + DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 + DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 + DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 + DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 + DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD TIM9_IRQHandler ; TIM9 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD SPI3_IRQHandler ; SPI3 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD HPDMA1_Channel0_IRQHandler ; HPDMA1 Channel 0 + DCD HPDMA1_Channel1_IRQHandler ; HPDMA1 Channel 1 + DCD HPDMA1_Channel2_IRQHandler ; HPDMA1 Channel 2 + DCD HPDMA1_Channel3_IRQHandler ; HPDMA1 Channel 3 + DCD HPDMA1_Channel4_IRQHandler ; HPDMA1 Channel 4 + DCD HPDMA1_Channel5_IRQHandler ; HPDMA1 Channel 5 + DCD HPDMA1_Channel6_IRQHandler ; HPDMA1 Channel 6 + DCD HPDMA1_Channel7_IRQHandler ; HPDMA1 Channel 7 + DCD SAI1_A_IRQHandler ; Serial Audio Interface 1 block A + DCD SAI1_B_IRQHandler ; Serial Audio Interface 1 block B + DCD SAI2_A_IRQHandler ; Serial Audio Interface 2 block A + DCD SAI2_B_IRQHandler ; Serial Audio Interface 2 block B + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD I3C1_EV_IRQHandler ; I3C1 Event + DCD I3C1_ER_IRQHandler ; I3C1 Error + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD ETH_IRQHandler ; Ethernet + DCD CORDIC_IRQHandler ; CORDIC + DCD GFXTIM_IRQHandler ; GFXTIM + DCD DCMIPP_IRQHandler ; DCMIPP + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD JPEG_IRQHandler ; JPEG + DCD GFXMMU_IRQHandler ; GFXMMU + DCD I3C1_WKUP_IRQHandler ; I3C1 wakeup + DCD MCE1_IRQHandler ; MCE1 + DCD MCE2_IRQHandler ; MCE2 + DCD MCE3_IRQHandler ; MCE3 + DCD XSPI1_IRQHandler ; XSPI1 + DCD XSPI2_IRQHandler ; XSPI2 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD LPTIM1_IRQHandler ; LP TIM1 + DCD LPTIM2_IRQHandler ; LP TIM2 + DCD LPTIM3_IRQHandler ; LP TIM3 + DCD LPTIM4_IRQHandler ; LP TIM4 + DCD LPTIM5_IRQHandler ; LP TIM5 + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD MDIOS_IRQHandler ; MDIOS + DCD ADF1_FLT0_IRQHandler ; ADF1 Filter 0 + DCD CRS_IRQHandler ; CRS + DCD UCPD1_IRQHandler ; UCPD1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD PSSI_IRQHandler ; PSSI + DCD LPUART1_IRQHandler ; LP UART1 + DCD WAKEUP_PIN_IRQHandler ; Wake-up pins interrupt + DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8 + DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9 + DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10 + DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11 + DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12 + DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13 + DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14 + DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15 + DCD HPDMA1_Channel8_IRQHandler ; HPDMA1 Channel 8 + DCD HPDMA1_Channel9_IRQHandler ; HPDMA1 Channel 9 + DCD HPDMA1_Channel10_IRQHandler ; HPDMA1 Channel 10 + DCD HPDMA1_Channel11_IRQHandler ; HPDMA1 Channel 11 + DCD HPDMA1_Channel12_IRQHandler ; HPDMA1 Channel 12 + DCD HPDMA1_Channel13_IRQHandler ; HPDMA1 Channel 13 + DCD HPDMA1_Channel14_IRQHandler ; HPDMA1 Channel 14 + DCD HPDMA1_Channel15_IRQHandler ; HPDMA1 Channel 15 + DCD GPU2D_IRQHandler ; GPU2D + DCD GPU2D_ER_IRQHandler ; GPU2D error + DCD ICACHE_IRQHandler ; ICACHE + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt 1 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt 1 + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT DTS_IRQHandler [WEAK] + EXPORT IWDG_IRQHandler [WEAK] + EXPORT WWDG_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RAMECC_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT TAMP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT SAES_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT PKA_IRQHandler [WEAK] + EXPORT HASH_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT GPDMA1_Channel0_IRQHandler [WEAK] + EXPORT GPDMA1_Channel1_IRQHandler [WEAK] + EXPORT GPDMA1_Channel2_IRQHandler [WEAK] + EXPORT GPDMA1_Channel3_IRQHandler [WEAK] + EXPORT GPDMA1_Channel4_IRQHandler [WEAK] + EXPORT GPDMA1_Channel5_IRQHandler [WEAK] + EXPORT GPDMA1_Channel6_IRQHandler [WEAK] + EXPORT GPDMA1_Channel7_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT HPDMA1_Channel0_IRQHandler [WEAK] + EXPORT HPDMA1_Channel1_IRQHandler [WEAK] + EXPORT HPDMA1_Channel2_IRQHandler [WEAK] + EXPORT HPDMA1_Channel3_IRQHandler [WEAK] + EXPORT HPDMA1_Channel4_IRQHandler [WEAK] + EXPORT HPDMA1_Channel5_IRQHandler [WEAK] + EXPORT HPDMA1_Channel6_IRQHandler [WEAK] + EXPORT HPDMA1_Channel7_IRQHandler [WEAK] + EXPORT SAI1_A_IRQHandler [WEAK] + EXPORT SAI1_B_IRQHandler [WEAK] + EXPORT SAI2_A_IRQHandler [WEAK] + EXPORT SAI2_B_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT I3C1_EV_IRQHandler [WEAK] + EXPORT I3C1_ER_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT GFXTIM_IRQHandler [WEAK] + EXPORT DCMIPP_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT GFXMMU_IRQHandler [WEAK] + EXPORT I3C1_WKUP_IRQHandler [WEAK] + EXPORT MCE1_IRQHandler [WEAK] + EXPORT MCE2_IRQHandler [WEAK] + EXPORT MCE3_IRQHandler [WEAK] + EXPORT XSPI1_IRQHandler [WEAK] + EXPORT XSPI2_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT TIM12_IRQHandler [WEAK] + EXPORT TIM13_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT ADF1_FLT0_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT UCPD1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT PSSI_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + EXPORT GPDMA1_Channel8_IRQHandler [WEAK] + EXPORT GPDMA1_Channel9_IRQHandler [WEAK] + EXPORT GPDMA1_Channel10_IRQHandler [WEAK] + EXPORT GPDMA1_Channel11_IRQHandler [WEAK] + EXPORT GPDMA1_Channel12_IRQHandler [WEAK] + EXPORT GPDMA1_Channel13_IRQHandler [WEAK] + EXPORT GPDMA1_Channel14_IRQHandler [WEAK] + EXPORT GPDMA1_Channel15_IRQHandler [WEAK] + EXPORT HPDMA1_Channel8_IRQHandler [WEAK] + EXPORT HPDMA1_Channel9_IRQHandler [WEAK] + EXPORT HPDMA1_Channel10_IRQHandler [WEAK] + EXPORT HPDMA1_Channel11_IRQHandler [WEAK] + EXPORT HPDMA1_Channel12_IRQHandler [WEAK] + EXPORT HPDMA1_Channel13_IRQHandler [WEAK] + EXPORT HPDMA1_Channel14_IRQHandler [WEAK] + EXPORT HPDMA1_Channel15_IRQHandler [WEAK] + EXPORT GPU2D_IRQHandler [WEAK] + EXPORT GPU2D_ER_IRQHandler [WEAK] + EXPORT ICACHE_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + +PVD_PVM_IRQHandler +DTS_IRQHandler +IWDG_IRQHandler +WWDG_IRQHandler +RCC_IRQHandler +FLASH_IRQHandler +RAMECC_IRQHandler +FPU_IRQHandler +TAMP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +RTC_IRQHandler +SAES_IRQHandler +CRYP_IRQHandler +PKA_IRQHandler +HASH_IRQHandler +RNG_IRQHandler +ADC1_2_IRQHandler +GPDMA1_Channel0_IRQHandler +GPDMA1_Channel1_IRQHandler +GPDMA1_Channel2_IRQHandler +GPDMA1_Channel3_IRQHandler +GPDMA1_Channel4_IRQHandler +GPDMA1_Channel5_IRQHandler +GPDMA1_Channel6_IRQHandler +GPDMA1_Channel7_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +TIM5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +TIM9_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +HPDMA1_Channel0_IRQHandler +HPDMA1_Channel1_IRQHandler +HPDMA1_Channel2_IRQHandler +HPDMA1_Channel3_IRQHandler +HPDMA1_Channel4_IRQHandler +HPDMA1_Channel5_IRQHandler +HPDMA1_Channel6_IRQHandler +HPDMA1_Channel7_IRQHandler +SAI1_A_IRQHandler +SAI1_B_IRQHandler +SAI2_A_IRQHandler +SAI2_B_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +I3C1_EV_IRQHandler +I3C1_ER_IRQHandler +OTG_HS_IRQHandler +ETH_IRQHandler +CORDIC_IRQHandler +GFXTIM_IRQHandler +DCMIPP_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +JPEG_IRQHandler +GFXMMU_IRQHandler +I3C1_WKUP_IRQHandler +MCE1_IRQHandler +MCE2_IRQHandler +MCE3_IRQHandler +XSPI1_IRQHandler +XSPI2_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +SDMMC2_IRQHandler +OTG_FS_IRQHandler +TIM12_IRQHandler +TIM13_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +SPDIF_RX_IRQHandler +MDIOS_IRQHandler +ADF1_FLT0_IRQHandler +CRS_IRQHandler +UCPD1_IRQHandler +CEC_IRQHandler +PSSI_IRQHandler +LPUART1_IRQHandler +WAKEUP_PIN_IRQHandler +GPDMA1_Channel8_IRQHandler +GPDMA1_Channel9_IRQHandler +GPDMA1_Channel10_IRQHandler +GPDMA1_Channel11_IRQHandler +GPDMA1_Channel12_IRQHandler +GPDMA1_Channel13_IRQHandler +GPDMA1_Channel14_IRQHandler +GPDMA1_Channel15_IRQHandler +HPDMA1_Channel8_IRQHandler +HPDMA1_Channel9_IRQHandler +HPDMA1_Channel10_IRQHandler +HPDMA1_Channel11_IRQHandler +HPDMA1_Channel12_IRQHandler +HPDMA1_Channel13_IRQHandler +HPDMA1_Channel14_IRQHandler +HPDMA1_Channel15_IRQHandler +GPU2D_IRQHandler +GPU2D_ER_IRQHandler +ICACHE_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN2_IT1_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7r3xx_flash.ld b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7r3xx_flash.ld new file mode 100644 index 00000000000..7834ce06500 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7r3xx_flash.ld @@ -0,0 +1,209 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H7R3xx Device from STM32H7RS series +** 64Kbytes FLASH +** 456Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +__FLASH_BEGIN = 0x08000000; +__FLASH_SIZE = 0x00010000; + + +__RAM_BEGIN = 0x24000000; +__RAM_SIZE = 0x71C00; +__RAM_NONCACHEABLEBUFFER_SIZE = 0x400; + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE + RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE + + ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x00010000 + DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000 + BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000 + + FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + RW_NONCACHEABLE : + { + __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + __NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */ + } > RAM_NONCACHEABLEBUFFER + + /* User_heap_stack section, used to check that there is enough "DTCM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7r3xx_sram.ld b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7r3xx_sram.ld new file mode 100644 index 00000000000..d19ae182df6 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7r3xx_sram.ld @@ -0,0 +1,206 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld (debug in RAM dedicated) +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H7R3xx Device from STM32H7RS series +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +__FLASH_BEGIN = 0x24050000; +__FLASH_SIZE = 0x00022000; + +__RAM_BEGIN = 0x24000000; +__RAM_SIZE = 0x50000; +__RAM_NONCACHEABLEBUFFER_SIZE = 0x400; + +/* Highest address of the user mode stack */ +_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM(xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE + RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE + + ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 64K + SRAMAHB(rw) : ORIGIN = 0x30000000, LENGTH = 32 + BKPSRAM(rw) : ORIGIN = 0x38800000, LENGTH = 4K + + FLASH(xrw) : ORIGIN = __FLASH_BEGIN,LENGTH = __FLASH_SIZE +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + RW_NONCACHEABLE : + { + __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + __NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */ + } >RAM_NONCACHEABLEBUFFER + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7r7xx_flash.ld b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7r7xx_flash.ld new file mode 100644 index 00000000000..33b2d23d443 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7r7xx_flash.ld @@ -0,0 +1,209 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H7R7xx Device from STM32H7RS series +** 64Kbytes FLASH +** 456Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +__FLASH_BEGIN = 0x08000000; +__FLASH_SIZE = 0x00010000; + + +__RAM_BEGIN = 0x24000000; +__RAM_SIZE = 0x71C00; +__RAM_NONCACHEABLEBUFFER_SIZE = 0x400; + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE + RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE + + ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x00010000 + DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000 + BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000 + + FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + RW_NONCACHEABLE : + { + __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + __NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */ + } > RAM_NONCACHEABLEBUFFER + + /* User_heap_stack section, used to check that there is enough "DTCM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7r7xx_sram.ld b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7r7xx_sram.ld new file mode 100644 index 00000000000..f926bd790ca --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7r7xx_sram.ld @@ -0,0 +1,206 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld (debug in RAM dedicated) +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H7R7xx Device from STM32H7RS series +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +__FLASH_BEGIN = 0x24050000; +__FLASH_SIZE = 0x00022000; + +__RAM_BEGIN = 0x24000000; +__RAM_SIZE = 0x50000; +__RAM_NONCACHEABLEBUFFER_SIZE = 0x400; + +/* Highest address of the user mode stack */ +_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM(xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE + RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE + + ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 64K + SRAMAHB(rw) : ORIGIN = 0x30000000, LENGTH = 32 + BKPSRAM(rw) : ORIGIN = 0x38800000, LENGTH = 4K + + FLASH(xrw) : ORIGIN = __FLASH_BEGIN,LENGTH = __FLASH_SIZE +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + RW_NONCACHEABLE : + { + __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + __NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */ + } >RAM_NONCACHEABLEBUFFER + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7rsxx_RAMxspi1_ROMxspi2.ld b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7rsxx_RAMxspi1_ROMxspi2.ld new file mode 100644 index 00000000000..cb2335a0c8e --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7rsxx_RAMxspi1_ROMxspi2.ld @@ -0,0 +1,210 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : STM32CubeIDE +** +** Abstract : Linker script for STM32H7Rxx8 Device +** 64Kbytes FLASH +** 456Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +__FLASH_BEGIN = 0x70000000; +__FLASH_SIZE = 0x08000000; +__EXTRAM_BEGIN = 0x90000000; +__EXTRAM_SIZE = 0x02000000; + + +__RAM = 0x24000000; +__RAM_SIZE = 0x72000; +__RAM_NONCACHEABLEBUFFER_SIZE = 0x400; + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = __RAM, LENGTH = __RAM_SIZE -__RAM_NONCACHEABLEBUFFER_SIZE + RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM + __RAM_SIZE - __RAM_NONCACHEABLEBUFFER_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE + ITCM (rw) : ORIGIN = 0x00000000, LENGTH = 0x00010000 + DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000 + BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000 + FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE + EXTRAM (rw) : ORIGIN = __EXTRAM_BEGIN,LENGTH = __EXTRAM_SIZE +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + RW_NONCACHEABLE : + { + __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + __NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */ + } > RAM_NONCACHEABLEBUFFER + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7rsxx_ROMxspi1.ld b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7rsxx_ROMxspi1.ld new file mode 100644 index 00000000000..3533caa9a64 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7rsxx_ROMxspi1.ld @@ -0,0 +1,206 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : STM32CubeIDE +** +** Abstract : Linker script for STM32H7Rxx8 Device +** 64Kbytes FLASH +** 456Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +__FLASH_BEGIN = 0x90000000; +__FLASH_SIZE = 0x08000000; + +__RAM = 0x24000000; +__RAM_SIZE = 0x72000; +__RAM_NONCACHEABLEBUFFER_SIZE = 0x400; + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = __RAM, LENGTH = __RAM_SIZE -__RAM_NONCACHEABLEBUFFER_SIZE + RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM + __RAM_SIZE - __RAM_NONCACHEABLEBUFFER_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE + ITCM (rw) : ORIGIN = 0x00000000, LENGTH = 0x00010000 + DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000 + BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000 + FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + RW_NONCACHEABLE : + { + __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + __NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */ + } > RAM_NONCACHEABLEBUFFER + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7rsxx_ROMxspi1_RAMxspi2.ld b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7rsxx_ROMxspi1_RAMxspi2.ld new file mode 100644 index 00000000000..6d648882a80 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7rsxx_ROMxspi1_RAMxspi2.ld @@ -0,0 +1,210 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : STM32CubeIDE +** +** Abstract : Linker script for STM32H7Rxx8 Device +** 64Kbytes FLASH +** 456Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +__FLASH_BEGIN = 0x90000000; +__FLASH_SIZE = 0x08000000; +__EXTRAM_BEGIN = 0x70000000; +__EXTRAM_SIZE = 0x02000000; + + +__RAM = 0x24000000; +__RAM_SIZE = 0x72000; +__RAM_NONCACHEABLEBUFFER_SIZE = 0x400; + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = __RAM, LENGTH = __RAM_SIZE -__RAM_NONCACHEABLEBUFFER_SIZE + RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM + __RAM_SIZE - __RAM_NONCACHEABLEBUFFER_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE + ITCM (rw) : ORIGIN = 0x00000000, LENGTH = 0x00010000 + DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000 + BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000 + FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE + EXTRAM (rw) : ORIGIN = __EXTRAM_BEGIN,LENGTH = __EXTRAM_SIZE +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + RW_NONCACHEABLE : + { + __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + __NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */ + } > RAM_NONCACHEABLEBUFFER + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7rsxx_ROMxspi2.ld b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7rsxx_ROMxspi2.ld new file mode 100644 index 00000000000..d285d38fda7 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7rsxx_ROMxspi2.ld @@ -0,0 +1,206 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : STM32CubeIDE +** +** Abstract : Linker script for STM32H7Rxx8 Device +** 64Kbytes FLASH +** 456Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +__FLASH_BEGIN = 0x70000000; +__FLASH_SIZE = 0x08000000; + +__RAM = 0x24000000; +__RAM_SIZE = 0x72000; +__RAM_NONCACHEABLEBUFFER_SIZE = 0x400; + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = __RAM, LENGTH = __RAM_SIZE -__RAM_NONCACHEABLEBUFFER_SIZE + RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM + __RAM_SIZE - __RAM_NONCACHEABLEBUFFER_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE + ITCM (rw) : ORIGIN = 0x00000000, LENGTH = 0x00010000 + DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000 + BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000 + FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + RW_NONCACHEABLE : + { + __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + __NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */ + } > RAM_NONCACHEABLEBUFFER + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7rsxx_extmemloader_stm32cube.ld b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7rsxx_extmemloader_stm32cube.ld new file mode 100644 index 00000000000..961701e1c3c --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7rsxx_extmemloader_stm32cube.ld @@ -0,0 +1,159 @@ +/* +***************************************************************************** +** File : linker.ld +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Generate 2 segment for Loader code and device info */ +PHDRS {Loader PT_LOAD FLAGS(5) ; SgInfo PT_LOAD ; } + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1)-1; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + RAM_D1 (xrw) : ORIGIN = 0x20000004, LENGTH = 64K-4 + RAM_D2 (xrw) : ORIGIN = 0x24020000, LENGTH = 128K +} + +/* Define output sections */ + +SECTIONS +{ + + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = . + 0x1FC; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >RAM_D1 :Loader + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_D1 + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >RAM_D1 :Loader + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >RAM_D1 :Loader + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >RAM_D1 :Loader + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >RAM_D1 :Loader + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM_D1 :Loader + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM_D2 :Loader + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >RAM_D1 :Loader + + .stm32_device_info : + { + KEEP(*stm32_device_info.o ( .rodata* )) + + } :SgInfo + + + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >RAM_D1 :Loader + + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM_D1 :Loader + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7s3xx_flash.ld b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7s3xx_flash.ld new file mode 100644 index 00000000000..08a0df539ef --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7s3xx_flash.ld @@ -0,0 +1,209 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H7S3xx Device from STM32H7RS series +** 64Kbytes FLASH +** 456Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +__FLASH_BEGIN = 0x08000000; +__FLASH_SIZE = 0x00010000; + + +__RAM_BEGIN = 0x24000000; +__RAM_SIZE = 0x71C00; +__RAM_NONCACHEABLEBUFFER_SIZE = 0x400; + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE + RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE + + ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x00010000 + DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000 + BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000 + + FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + RW_NONCACHEABLE : + { + __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + __NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */ + } > RAM_NONCACHEABLEBUFFER + + /* User_heap_stack section, used to check that there is enough "DTCM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7s3xx_sram.ld b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7s3xx_sram.ld new file mode 100644 index 00000000000..7957ecf6935 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7s3xx_sram.ld @@ -0,0 +1,206 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld (debug in RAM dedicated) +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H7S3xx Device from STM32H7RS series +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +__FLASH_BEGIN = 0x24050000; +__FLASH_SIZE = 0x00022000; + +__RAM_BEGIN = 0x24000000; +__RAM_SIZE = 0x50000; +__RAM_NONCACHEABLEBUFFER_SIZE = 0x400; + +/* Highest address of the user mode stack */ +_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM(xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE + RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE + + ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 64K + SRAMAHB(rw) : ORIGIN = 0x30000000, LENGTH = 32 + BKPSRAM(rw) : ORIGIN = 0x38800000, LENGTH = 4K + + FLASH(xrw) : ORIGIN = __FLASH_BEGIN,LENGTH = __FLASH_SIZE +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + RW_NONCACHEABLE : + { + __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + __NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */ + } >RAM_NONCACHEABLEBUFFER + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7s7xx_flash.ld b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7s7xx_flash.ld new file mode 100644 index 00000000000..bc856f65e85 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7s7xx_flash.ld @@ -0,0 +1,209 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H7S7xx Device from STM32H7RS series +** 64Kbytes FLASH +** 456Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +__FLASH_BEGIN = 0x08000000; +__FLASH_SIZE = 0x00010000; + + +__RAM_BEGIN = 0x24000000; +__RAM_SIZE = 0x71C00; +__RAM_NONCACHEABLEBUFFER_SIZE = 0x400; + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE + RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE + + ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x00010000 + DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000 + BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000 + + FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + RW_NONCACHEABLE : + { + __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + __NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */ + } > RAM_NONCACHEABLEBUFFER + + /* User_heap_stack section, used to check that there is enough "DTCM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7s7xx_sram.ld b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7s7xx_sram.ld new file mode 100644 index 00000000000..3a9767cfe11 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/linker/stm32h7s7xx_sram.ld @@ -0,0 +1,206 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld (debug in RAM dedicated) +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H7S7xx Device from STM32H7RS series +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +__FLASH_BEGIN = 0x24050000; +__FLASH_SIZE = 0x00022000; + +__RAM_BEGIN = 0x24000000; +__RAM_SIZE = 0x50000; +__RAM_NONCACHEABLEBUFFER_SIZE = 0x400; + +/* Highest address of the user mode stack */ +_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM(xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE + RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE + + ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 64K + SRAMAHB(rw) : ORIGIN = 0x30000000, LENGTH = 32 + BKPSRAM(rw) : ORIGIN = 0x38800000, LENGTH = 4K + + FLASH(xrw) : ORIGIN = __FLASH_BEGIN,LENGTH = __FLASH_SIZE +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + RW_NONCACHEABLE : + { + __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + __NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */ + } >RAM_NONCACHEABLEBUFFER + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/startup_stm32h7r3xx.s b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/startup_stm32h7r3xx.s new file mode 100644 index 00000000000..ea3e43be827 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/startup_stm32h7r3xx.s @@ -0,0 +1,750 @@ +/** + ****************************************************************************** + * @file startup_stm32h7s7xx.s + * @author MCD Application Team + * @brief STM32H7R3xx Devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl entry + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32H7R3xx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + /* External Interrupts */ + .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */ + .word 0 /* Reserved */ + .word DTS_IRQHandler /* Digital Temperature Sensor */ + .word IWDG_IRQHandler /* Internal Watchdog */ + .word WWDG_IRQHandler /* Window Watchdog */ + .word RCC_IRQHandler /* RCC global interrupts through EXTI Line detection */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FLASH_IRQHandler /* FLASH interrupts */ + .word RAMECC_IRQHandler /* RAMECC interruptsflags */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TAMP_IRQHandler /* Tamper and TimeStamp interrupts */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word EXTI5_IRQHandler /* EXTI Line5 */ + .word EXTI6_IRQHandler /* EXTI Line6 */ + .word EXTI7_IRQHandler /* EXTI Line7 */ + .word EXTI8_IRQHandler /* EXTI Line8 */ + .word EXTI9_IRQHandler /* EXTI Line9 */ + .word EXTI10_IRQHandler /* EXTI Line10 */ + .word EXTI11_IRQHandler /* EXTI Line11 */ + .word EXTI12_IRQHandler /* EXTI Line12 */ + .word EXTI13_IRQHandler /* EXTI Line13 */ + .word EXTI14_IRQHandler /* EXTI Line14 */ + .word EXTI15_IRQHandler /* EXTI Line15 */ + .word RTC_IRQHandler /* RTC wakeup and alarm interrupts */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word PKA_IRQHandler /* PKA */ + .word HASH_IRQHandler /* HASH */ + .word RNG_IRQHandler /* RNG */ + .word ADC1_2_IRQHandler /* ADC1 & ADC2 */ + .word GPDMA1_Channel0_IRQHandler /* GPDMA1 Channel 0 */ + .word GPDMA1_Channel1_IRQHandler /* GPDMA1 Channel 1 */ + .word GPDMA1_Channel2_IRQHandler /* GPDMA1 Channel 2 */ + .word GPDMA1_Channel3_IRQHandler /* GPDMA1 Channel 3 */ + .word GPDMA1_Channel4_IRQHandler /* GPDMA1 Channel 4 */ + .word GPDMA1_Channel5_IRQHandler /* GPDMA1 Channel 5 */ + .word GPDMA1_Channel6_IRQHandler /* GPDMA1 Channel 6 */ + .word GPDMA1_Channel7_IRQHandler /* GPDMA1 Channel 7 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word TIM5_IRQHandler /* TIM5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word TIM9_IRQHandler /* TIM9 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word SPI3_IRQHandler /* SPI3 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word HPDMA1_Channel0_IRQHandler /* HPDMA1 Channel 0 */ + .word HPDMA1_Channel1_IRQHandler /* HPDMA1 Channel 1 */ + .word HPDMA1_Channel2_IRQHandler /* HPDMA1 Channel 2 */ + .word HPDMA1_Channel3_IRQHandler /* HPDMA1 Channel 3 */ + .word HPDMA1_Channel4_IRQHandler /* HPDMA1 Channel 4 */ + .word HPDMA1_Channel5_IRQHandler /* HPDMA1 Channel 5 */ + .word HPDMA1_Channel6_IRQHandler /* HPDMA1 Channel 6 */ + .word HPDMA1_Channel7_IRQHandler /* HPDMA1 Channel 7 */ + .word SAI1_A_IRQHandler /* Serial Audio Interface 1 block A */ + .word SAI1_B_IRQHandler /* Serial Audio Interface 1 block B */ + .word SAI2_A_IRQHandler /* Serial Audio Interface 2 block A */ + .word SAI2_B_IRQHandler /* Serial Audio Interface 2 block B */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word I2C3_EV_IRQHandler /* I2C3 Event */ + .word I2C3_ER_IRQHandler /* I2C3 Error */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word I3C1_EV_IRQHandler /* I3C1 Event */ + .word I3C1_ER_IRQHandler /* I3C1 Error */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word ETH_IRQHandler /* Ethernet */ + .word CORDIC_IRQHandler /* CORDIC */ + .word GFXTIM_IRQHandler /* GFXTIM */ + .word DCMIPP_IRQHandler /* DCMIPP */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2D_IRQHandler /* DMA2D */ + .word JPEG_IRQHandler /* JPEG */ + .word GFXMMU_IRQHandler /* GFXMMU */ + .word I3C1_WKUP_IRQHandler /* I3C1 wakeup */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word XSPI1_IRQHandler /* XSPI1 */ + .word XSPI2_IRQHandler /* XSPI2 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word SDMMC2_IRQHandler /* SDMMC2 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word TIM12_IRQHandler /* TIM12 */ + .word TIM13_IRQHandler /* TIM13 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word LPTIM1_IRQHandler /* LP TIM1 */ + .word LPTIM2_IRQHandler /* LP TIM2 */ + .word LPTIM3_IRQHandler /* LP TIM3 */ + .word LPTIM4_IRQHandler /* LP TIM4 */ + .word LPTIM5_IRQHandler /* LP TIM5 */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word MDIOS_IRQHandler /* MDIOS */ + .word ADF1_FLT0_IRQHandler /* ADF1 Filter 0 */ + .word CRS_IRQHandler /* CRS */ + .word UCPD1_IRQHandler /* UCPD1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word PSSI_IRQHandler /* PSSI */ + .word LPUART1_IRQHandler /* LP UART1 */ + .word WAKEUP_PIN_IRQHandler /* Wake-up pins interrupt */ + .word GPDMA1_Channel8_IRQHandler /* GPDMA1 Channel 8 */ + .word GPDMA1_Channel9_IRQHandler /* GPDMA1 Channel 9 */ + .word GPDMA1_Channel10_IRQHandler /* GPDMA1 Channel 10 */ + .word GPDMA1_Channel11_IRQHandler /* GPDMA1 Channel 11 */ + .word GPDMA1_Channel12_IRQHandler /* GPDMA1 Channel 12 */ + .word GPDMA1_Channel13_IRQHandler /* GPDMA1 Channel 13 */ + .word GPDMA1_Channel14_IRQHandler /* GPDMA1 Channel 14 */ + .word GPDMA1_Channel15_IRQHandler /* GPDMA1 Channel 15 */ + .word HPDMA1_Channel8_IRQHandler /* HPDMA1 Channel 8 */ + .word HPDMA1_Channel9_IRQHandler /* HPDMA1 Channel 9 */ + .word HPDMA1_Channel10_IRQHandler /* HPDMA1 Channel 10 */ + .word HPDMA1_Channel11_IRQHandler /* HPDMA1 Channel 11 */ + .word HPDMA1_Channel12_IRQHandler /* HPDMA1 Channel 12 */ + .word HPDMA1_Channel13_IRQHandler /* HPDMA1 Channel 13 */ + .word HPDMA1_Channel14_IRQHandler /* HPDMA1 Channel 14 */ + .word HPDMA1_Channel15_IRQHandler /* HPDMA1 Channel 15 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 Interrupt 0 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 Interrupt 1 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RAMECC_IRQHandler + .thumb_set RAMECC_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak HPDMA1_Channel0_IRQHandler + .thumb_set HPDMA1_Channel0_IRQHandler,Default_Handler + + .weak HPDMA1_Channel1_IRQHandler + .thumb_set HPDMA1_Channel1_IRQHandler,Default_Handler + + .weak HPDMA1_Channel2_IRQHandler + .thumb_set HPDMA1_Channel2_IRQHandler,Default_Handler + + .weak HPDMA1_Channel3_IRQHandler + .thumb_set HPDMA1_Channel3_IRQHandler,Default_Handler + + .weak HPDMA1_Channel4_IRQHandler + .thumb_set HPDMA1_Channel4_IRQHandler,Default_Handler + + .weak HPDMA1_Channel5_IRQHandler + .thumb_set HPDMA1_Channel5_IRQHandler,Default_Handler + + .weak HPDMA1_Channel6_IRQHandler + .thumb_set HPDMA1_Channel6_IRQHandler,Default_Handler + + .weak HPDMA1_Channel7_IRQHandler + .thumb_set HPDMA1_Channel7_IRQHandler,Default_Handler + + .weak SAI1_A_IRQHandler + .thumb_set SAI1_A_IRQHandler,Default_Handler + + .weak SAI1_B_IRQHandler + .thumb_set SAI1_B_IRQHandler,Default_Handler + + .weak SAI2_A_IRQHandler + .thumb_set SAI2_A_IRQHandler,Default_Handler + + .weak SAI2_B_IRQHandler + .thumb_set SAI2_B_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak GFXTIM_IRQHandler + .thumb_set GFXTIM_IRQHandler,Default_Handler + + .weak DCMIPP_IRQHandler + .thumb_set DCMIPP_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak GFXMMU_IRQHandler + .thumb_set GFXMMU_IRQHandler,Default_Handler + + .weak I3C1_WKUP_IRQHandler + .thumb_set I3C1_WKUP_IRQHandler,Default_Handler + + .weak XSPI1_IRQHandler + .thumb_set XSPI1_IRQHandler,Default_Handler + + .weak XSPI2_IRQHandler + .thumb_set XSPI2_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak ADF1_FLT0_IRQHandler + .thumb_set ADF1_FLT0_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak PSSI_IRQHandler + .thumb_set PSSI_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + .weak GPDMA1_Channel8_IRQHandler + .thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler + + .weak GPDMA1_Channel9_IRQHandler + .thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler + + .weak GPDMA1_Channel10_IRQHandler + .thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler + + .weak GPDMA1_Channel11_IRQHandler + .thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler + + .weak GPDMA1_Channel12_IRQHandler + .thumb_set GPDMA1_Channel12_IRQHandler,Default_Handler + + .weak GPDMA1_Channel13_IRQHandler + .thumb_set GPDMA1_Channel13_IRQHandler,Default_Handler + + .weak GPDMA1_Channel14_IRQHandler + .thumb_set GPDMA1_Channel14_IRQHandler,Default_Handler + + .weak GPDMA1_Channel15_IRQHandler + .thumb_set GPDMA1_Channel15_IRQHandler,Default_Handler + + .weak HPDMA1_Channel8_IRQHandler + .thumb_set HPDMA1_Channel8_IRQHandler,Default_Handler + + .weak HPDMA1_Channel9_IRQHandler + .thumb_set HPDMA1_Channel9_IRQHandler,Default_Handler + + .weak HPDMA1_Channel10_IRQHandler + .thumb_set HPDMA1_Channel10_IRQHandler,Default_Handler + + .weak HPDMA1_Channel11_IRQHandler + .thumb_set HPDMA1_Channel11_IRQHandler,Default_Handler + + .weak HPDMA1_Channel12_IRQHandler + .thumb_set HPDMA1_Channel12_IRQHandler,Default_Handler + + .weak HPDMA1_Channel13_IRQHandler + .thumb_set HPDMA1_Channel13_IRQHandler,Default_Handler + + .weak HPDMA1_Channel14_IRQHandler + .thumb_set HPDMA1_Channel14_IRQHandler,Default_Handler + + .weak HPDMA1_Channel15_IRQHandler + .thumb_set HPDMA1_Channel15_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak SystemInit \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/startup_stm32h7r7xx.s b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/startup_stm32h7r7xx.s new file mode 100644 index 00000000000..b6a68eeb23c --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/startup_stm32h7r7xx.s @@ -0,0 +1,765 @@ +/** + ****************************************************************************** + * @file startup_stm32h7s7xx.s + * @author MCD Application Team + * @brief STM32H7R7xx Devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl entry + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32H7R7xx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + /* External Interrupts */ + .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */ + .word 0 /* Reserved */ + .word DTS_IRQHandler /* Digital Temperature Sensor */ + .word IWDG_IRQHandler /* Internal Watchdog */ + .word WWDG_IRQHandler /* Window Watchdog */ + .word RCC_IRQHandler /* RCC global interrupts through EXTI Line detection */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FLASH_IRQHandler /* FLASH interrupts */ + .word RAMECC_IRQHandler /* RAMECC interrupts */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TAMP_IRQHandler /* Tamper and TimeStamp interrupts */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word EXTI5_IRQHandler /* EXTI Line5 */ + .word EXTI6_IRQHandler /* EXTI Line6 */ + .word EXTI7_IRQHandler /* EXTI Line7 */ + .word EXTI8_IRQHandler /* EXTI Line8 */ + .word EXTI9_IRQHandler /* EXTI Line9 */ + .word EXTI10_IRQHandler /* EXTI Line10 */ + .word EXTI11_IRQHandler /* EXTI Line11 */ + .word EXTI12_IRQHandler /* EXTI Line12 */ + .word EXTI13_IRQHandler /* EXTI Line13 */ + .word EXTI14_IRQHandler /* EXTI Line14 */ + .word EXTI15_IRQHandler /* EXTI Line15 */ + .word RTC_IRQHandler /* RTC wakeup and alarm interrupts */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word PKA_IRQHandler /* PKA */ + .word HASH_IRQHandler /* HASH */ + .word RNG_IRQHandler /* RNG */ + .word ADC1_2_IRQHandler /* ADC1 & ADC2 */ + .word GPDMA1_Channel0_IRQHandler /* GPDMA1 Channel 0 */ + .word GPDMA1_Channel1_IRQHandler /* GPDMA1 Channel 1 */ + .word GPDMA1_Channel2_IRQHandler /* GPDMA1 Channel 2 */ + .word GPDMA1_Channel3_IRQHandler /* GPDMA1 Channel 3 */ + .word GPDMA1_Channel4_IRQHandler /* GPDMA1 Channel 4 */ + .word GPDMA1_Channel5_IRQHandler /* GPDMA1 Channel 5 */ + .word GPDMA1_Channel6_IRQHandler /* GPDMA1 Channel 6 */ + .word GPDMA1_Channel7_IRQHandler /* GPDMA1 Channel 7 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word TIM5_IRQHandler /* TIM5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word TIM9_IRQHandler /* TIM9 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word SPI3_IRQHandler /* SPI3 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word HPDMA1_Channel0_IRQHandler /* HPDMA1 Channel 0 */ + .word HPDMA1_Channel1_IRQHandler /* HPDMA1 Channel 1 */ + .word HPDMA1_Channel2_IRQHandler /* HPDMA1 Channel 2 */ + .word HPDMA1_Channel3_IRQHandler /* HPDMA1 Channel 3 */ + .word HPDMA1_Channel4_IRQHandler /* HPDMA1 Channel 4 */ + .word HPDMA1_Channel5_IRQHandler /* HPDMA1 Channel 5 */ + .word HPDMA1_Channel6_IRQHandler /* HPDMA1 Channel 6 */ + .word HPDMA1_Channel7_IRQHandler /* HPDMA1 Channel 7 */ + .word SAI1_A_IRQHandler /* Serial Audio Interface 1 block A */ + .word SAI1_B_IRQHandler /* Serial Audio Interface 1 block B */ + .word SAI2_A_IRQHandler /* Serial Audio Interface 2 block A */ + .word SAI2_B_IRQHandler /* Serial Audio Interface 2 block B */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word I2C3_EV_IRQHandler /* I2C3 Event */ + .word I2C3_ER_IRQHandler /* I2C3 Error */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word I3C1_EV_IRQHandler /* I3C1 Event */ + .word I3C1_ER_IRQHandler /* I3C1 Error */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word ETH_IRQHandler /* Ethernet */ + .word CORDIC_IRQHandler /* CORDIC */ + .word GFXTIM_IRQHandler /* GFXTIM */ + .word DCMIPP_IRQHandler /* DCMIPP */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word JPEG_IRQHandler /* JPEG */ + .word GFXMMU_IRQHandler /* GFXMMU */ + .word I3C1_WKUP_IRQHandler /* I3C1 wakeup */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word XSPI1_IRQHandler /* XSPI1 */ + .word XSPI2_IRQHandler /* XSPI2 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word SDMMC2_IRQHandler /* SDMMC2 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word TIM12_IRQHandler /* TIM12 */ + .word TIM13_IRQHandler /* TIM13 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word LPTIM1_IRQHandler /* LP TIM1 */ + .word LPTIM2_IRQHandler /* LP TIM2 */ + .word LPTIM3_IRQHandler /* LP TIM3 */ + .word LPTIM4_IRQHandler /* LP TIM4 */ + .word LPTIM5_IRQHandler /* LP TIM5 */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word MDIOS_IRQHandler /* MDIOS */ + .word ADF1_FLT0_IRQHandler /* ADF1 Filter 0 */ + .word CRS_IRQHandler /* CRS */ + .word UCPD1_IRQHandler /* UCPD1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word PSSI_IRQHandler /* PSSI */ + .word LPUART1_IRQHandler /* LP UART1 */ + .word WAKEUP_PIN_IRQHandler /* Wake-up pins interrupt */ + .word GPDMA1_Channel8_IRQHandler /* GPDMA1 Channel 8 */ + .word GPDMA1_Channel9_IRQHandler /* GPDMA1 Channel 9 */ + .word GPDMA1_Channel10_IRQHandler /* GPDMA1 Channel 10 */ + .word GPDMA1_Channel11_IRQHandler /* GPDMA1 Channel 11 */ + .word GPDMA1_Channel12_IRQHandler /* GPDMA1 Channel 12 */ + .word GPDMA1_Channel13_IRQHandler /* GPDMA1 Channel 13 */ + .word GPDMA1_Channel14_IRQHandler /* GPDMA1 Channel 14 */ + .word GPDMA1_Channel15_IRQHandler /* GPDMA1 Channel 15 */ + .word HPDMA1_Channel8_IRQHandler /* HPDMA1 Channel 8 */ + .word HPDMA1_Channel9_IRQHandler /* HPDMA1 Channel 9 */ + .word HPDMA1_Channel10_IRQHandler /* HPDMA1 Channel 10 */ + .word HPDMA1_Channel11_IRQHandler /* HPDMA1 Channel 11 */ + .word HPDMA1_Channel12_IRQHandler /* HPDMA1 Channel 12 */ + .word HPDMA1_Channel13_IRQHandler /* HPDMA1 Channel 13 */ + .word HPDMA1_Channel14_IRQHandler /* HPDMA1 Channel 14 */ + .word HPDMA1_Channel15_IRQHandler /* HPDMA1 Channel 15 */ + .word GPU2D_IRQHandler /* GPU2D */ + .word GPU2D_ER_IRQHandler /* GPU2D error */ + .word ICACHE_IRQHandler /* ICACHE */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 Interrupt 0 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 Interrupt 1 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RAMECC_IRQHandler + .thumb_set RAMECC_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak HPDMA1_Channel0_IRQHandler + .thumb_set HPDMA1_Channel0_IRQHandler,Default_Handler + + .weak HPDMA1_Channel1_IRQHandler + .thumb_set HPDMA1_Channel1_IRQHandler,Default_Handler + + .weak HPDMA1_Channel2_IRQHandler + .thumb_set HPDMA1_Channel2_IRQHandler,Default_Handler + + .weak HPDMA1_Channel3_IRQHandler + .thumb_set HPDMA1_Channel3_IRQHandler,Default_Handler + + .weak HPDMA1_Channel4_IRQHandler + .thumb_set HPDMA1_Channel4_IRQHandler,Default_Handler + + .weak HPDMA1_Channel5_IRQHandler + .thumb_set HPDMA1_Channel5_IRQHandler,Default_Handler + + .weak HPDMA1_Channel6_IRQHandler + .thumb_set HPDMA1_Channel6_IRQHandler,Default_Handler + + .weak HPDMA1_Channel7_IRQHandler + .thumb_set HPDMA1_Channel7_IRQHandler,Default_Handler + + .weak SAI1_A_IRQHandler + .thumb_set SAI1_A_IRQHandler,Default_Handler + + .weak SAI1_B_IRQHandler + .thumb_set SAI1_B_IRQHandler,Default_Handler + + .weak SAI2_A_IRQHandler + .thumb_set SAI2_A_IRQHandler,Default_Handler + + .weak SAI2_B_IRQHandler + .thumb_set SAI2_B_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak GFXTIM_IRQHandler + .thumb_set GFXTIM_IRQHandler,Default_Handler + + .weak DCMIPP_IRQHandler + .thumb_set DCMIPP_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak GFXMMU_IRQHandler + .thumb_set GFXMMU_IRQHandler,Default_Handler + + .weak I3C1_WKUP_IRQHandler + .thumb_set I3C1_WKUP_IRQHandler,Default_Handler + + .weak XSPI1_IRQHandler + .thumb_set XSPI1_IRQHandler,Default_Handler + + .weak XSPI2_IRQHandler + .thumb_set XSPI2_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak ADF1_FLT0_IRQHandler + .thumb_set ADF1_FLT0_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak PSSI_IRQHandler + .thumb_set PSSI_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + .weak GPDMA1_Channel8_IRQHandler + .thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler + + .weak GPDMA1_Channel9_IRQHandler + .thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler + + .weak GPDMA1_Channel10_IRQHandler + .thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler + + .weak GPDMA1_Channel11_IRQHandler + .thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler + + .weak GPDMA1_Channel12_IRQHandler + .thumb_set GPDMA1_Channel12_IRQHandler,Default_Handler + + .weak GPDMA1_Channel13_IRQHandler + .thumb_set GPDMA1_Channel13_IRQHandler,Default_Handler + + .weak GPDMA1_Channel14_IRQHandler + .thumb_set GPDMA1_Channel14_IRQHandler,Default_Handler + + .weak GPDMA1_Channel15_IRQHandler + .thumb_set GPDMA1_Channel15_IRQHandler,Default_Handler + + .weak HPDMA1_Channel8_IRQHandler + .thumb_set HPDMA1_Channel8_IRQHandler,Default_Handler + + .weak HPDMA1_Channel9_IRQHandler + .thumb_set HPDMA1_Channel9_IRQHandler,Default_Handler + + .weak HPDMA1_Channel10_IRQHandler + .thumb_set HPDMA1_Channel10_IRQHandler,Default_Handler + + .weak HPDMA1_Channel11_IRQHandler + .thumb_set HPDMA1_Channel11_IRQHandler,Default_Handler + + .weak HPDMA1_Channel12_IRQHandler + .thumb_set HPDMA1_Channel12_IRQHandler,Default_Handler + + .weak HPDMA1_Channel13_IRQHandler + .thumb_set HPDMA1_Channel13_IRQHandler,Default_Handler + + .weak HPDMA1_Channel14_IRQHandler + .thumb_set HPDMA1_Channel14_IRQHandler,Default_Handler + + .weak HPDMA1_Channel15_IRQHandler + .thumb_set HPDMA1_Channel15_IRQHandler,Default_Handler + + .weak GPU2D_IRQHandler + .thumb_set GPU2D_IRQHandler,Default_Handler + + .weak GPU2D_ER_IRQHandler + .thumb_set GPU2D_ER_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak SystemInit \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/startup_stm32h7s3xx.s b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/startup_stm32h7s3xx.s new file mode 100644 index 00000000000..e2a4cdfa20a --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/startup_stm32h7s3xx.s @@ -0,0 +1,765 @@ +/** + ****************************************************************************** + * @file startup_stm32h7s3xx.s + * @author MCD Application Team + * @brief STM32H7S3xx Devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl entry + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32H7S3xx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + /* External Interrupts */ + .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */ + .word 0 /* Reserved */ + .word DTS_IRQHandler /* Digital Temperature Sensor */ + .word IWDG_IRQHandler /* Internal Watchdog */ + .word WWDG_IRQHandler /* Window Watchdog */ + .word RCC_IRQHandler /* RCC global interrupts through EXTI Line detection */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FLASH_IRQHandler /* FLASH interrupts */ + .word RAMECC_IRQHandler /* RAMECC interrupts */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TAMP_IRQHandler /* Tamper and TimeStamp interrupts */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word EXTI5_IRQHandler /* EXTI Line5 */ + .word EXTI6_IRQHandler /* EXTI Line6 */ + .word EXTI7_IRQHandler /* EXTI Line7 */ + .word EXTI8_IRQHandler /* EXTI Line8 */ + .word EXTI9_IRQHandler /* EXTI Line9 */ + .word EXTI10_IRQHandler /* EXTI Line10 */ + .word EXTI11_IRQHandler /* EXTI Line11 */ + .word EXTI12_IRQHandler /* EXTI Line12 */ + .word EXTI13_IRQHandler /* EXTI Line13 */ + .word EXTI14_IRQHandler /* EXTI Line14 */ + .word EXTI15_IRQHandler /* EXTI Line15 */ + .word RTC_IRQHandler /* RTC wakeup and alarm interrupts */ + .word SAES_IRQHandler /* SAES */ + .word CRYP_IRQHandler /* CRYP */ + .word PKA_IRQHandler /* PKA */ + .word HASH_IRQHandler /* HASH */ + .word RNG_IRQHandler /* RNG */ + .word ADC1_2_IRQHandler /* ADC1 & ADC2 */ + .word GPDMA1_Channel0_IRQHandler /* GPDMA1 Channel 0 */ + .word GPDMA1_Channel1_IRQHandler /* GPDMA1 Channel 1 */ + .word GPDMA1_Channel2_IRQHandler /* GPDMA1 Channel 2 */ + .word GPDMA1_Channel3_IRQHandler /* GPDMA1 Channel 3 */ + .word GPDMA1_Channel4_IRQHandler /* GPDMA1 Channel 4 */ + .word GPDMA1_Channel5_IRQHandler /* GPDMA1 Channel 5 */ + .word GPDMA1_Channel6_IRQHandler /* GPDMA1 Channel 6 */ + .word GPDMA1_Channel7_IRQHandler /* GPDMA1 Channel 7 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word TIM5_IRQHandler /* TIM5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word TIM9_IRQHandler /* TIM9 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word SPI3_IRQHandler /* SPI3 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word HPDMA1_Channel0_IRQHandler /* HPDMA1 Channel 0 */ + .word HPDMA1_Channel1_IRQHandler /* HPDMA1 Channel 1 */ + .word HPDMA1_Channel2_IRQHandler /* HPDMA1 Channel 2 */ + .word HPDMA1_Channel3_IRQHandler /* HPDMA1 Channel 3 */ + .word HPDMA1_Channel4_IRQHandler /* HPDMA1 Channel 4 */ + .word HPDMA1_Channel5_IRQHandler /* HPDMA1 Channel 5 */ + .word HPDMA1_Channel6_IRQHandler /* HPDMA1 Channel 6 */ + .word HPDMA1_Channel7_IRQHandler /* HPDMA1 Channel 7 */ + .word SAI1_A_IRQHandler /* Serial Audio Interface 1 block A */ + .word SAI1_B_IRQHandler /* Serial Audio Interface 1 block B */ + .word SAI2_A_IRQHandler /* Serial Audio Interface 2 block A */ + .word SAI2_B_IRQHandler /* Serial Audio Interface 2 block B */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word I2C3_EV_IRQHandler /* I2C3 Event */ + .word I2C3_ER_IRQHandler /* I2C3 Error */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word I3C1_EV_IRQHandler /* I3C1 Event */ + .word I3C1_ER_IRQHandler /* I3C1 Error */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word ETH_IRQHandler /* Ethernet */ + .word CORDIC_IRQHandler /* CORDIC */ + .word GFXTIM_IRQHandler /* GFXTIM */ + .word DCMIPP_IRQHandler /* DCMIPP */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2D_IRQHandler /* DMA2D */ + .word JPEG_IRQHandler /* JPEG */ + .word GFXMMU_IRQHandler /* GFXMMU */ + .word I3C1_WKUP_IRQHandler /* I3C1 wakeup */ + .word MCE1_IRQHandler /* MCE1 */ + .word MCE2_IRQHandler /* MCE2 */ + .word MCE3_IRQHandler /* MCE3 */ + .word XSPI1_IRQHandler /* XSPI1 */ + .word XSPI2_IRQHandler /* XSPI2 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word SDMMC2_IRQHandler /* SDMMC2 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word TIM12_IRQHandler /* TIM12 */ + .word TIM13_IRQHandler /* TIM13 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word LPTIM1_IRQHandler /* LP TIM1 */ + .word LPTIM2_IRQHandler /* LP TIM2 */ + .word LPTIM3_IRQHandler /* LP TIM3 */ + .word LPTIM4_IRQHandler /* LP TIM4 */ + .word LPTIM5_IRQHandler /* LP TIM5 */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word MDIOS_IRQHandler /* MDIOS */ + .word ADF1_FLT0_IRQHandler /* ADF1 Filter 0 */ + .word CRS_IRQHandler /* CRS */ + .word UCPD1_IRQHandler /* UCPD1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word PSSI_IRQHandler /* PSSI */ + .word LPUART1_IRQHandler /* LP UART1 */ + .word WAKEUP_PIN_IRQHandler /* Wake-up pins interrupt */ + .word GPDMA1_Channel8_IRQHandler /* GPDMA1 Channel 8 */ + .word GPDMA1_Channel9_IRQHandler /* GPDMA1 Channel 9 */ + .word GPDMA1_Channel10_IRQHandler /* GPDMA1 Channel 10 */ + .word GPDMA1_Channel11_IRQHandler /* GPDMA1 Channel 11 */ + .word GPDMA1_Channel12_IRQHandler /* GPDMA1 Channel 12 */ + .word GPDMA1_Channel13_IRQHandler /* GPDMA1 Channel 13 */ + .word GPDMA1_Channel14_IRQHandler /* GPDMA1 Channel 14 */ + .word GPDMA1_Channel15_IRQHandler /* GPDMA1 Channel 15 */ + .word HPDMA1_Channel8_IRQHandler /* HPDMA1 Channel 8 */ + .word HPDMA1_Channel9_IRQHandler /* HPDMA1 Channel 9 */ + .word HPDMA1_Channel10_IRQHandler /* HPDMA1 Channel 10 */ + .word HPDMA1_Channel11_IRQHandler /* HPDMA1 Channel 11 */ + .word HPDMA1_Channel12_IRQHandler /* HPDMA1 Channel 12 */ + .word HPDMA1_Channel13_IRQHandler /* HPDMA1 Channel 13 */ + .word HPDMA1_Channel14_IRQHandler /* HPDMA1 Channel 14 */ + .word HPDMA1_Channel15_IRQHandler /* HPDMA1 Channel 15 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 Interrupt 0 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 Interrupt 1 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RAMECC_IRQHandler + .thumb_set RAMECC_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak SAES_IRQHandler + .thumb_set SAES_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak HPDMA1_Channel0_IRQHandler + .thumb_set HPDMA1_Channel0_IRQHandler,Default_Handler + + .weak HPDMA1_Channel1_IRQHandler + .thumb_set HPDMA1_Channel1_IRQHandler,Default_Handler + + .weak HPDMA1_Channel2_IRQHandler + .thumb_set HPDMA1_Channel2_IRQHandler,Default_Handler + + .weak HPDMA1_Channel3_IRQHandler + .thumb_set HPDMA1_Channel3_IRQHandler,Default_Handler + + .weak HPDMA1_Channel4_IRQHandler + .thumb_set HPDMA1_Channel4_IRQHandler,Default_Handler + + .weak HPDMA1_Channel5_IRQHandler + .thumb_set HPDMA1_Channel5_IRQHandler,Default_Handler + + .weak HPDMA1_Channel6_IRQHandler + .thumb_set HPDMA1_Channel6_IRQHandler,Default_Handler + + .weak HPDMA1_Channel7_IRQHandler + .thumb_set HPDMA1_Channel7_IRQHandler,Default_Handler + + .weak SAI1_A_IRQHandler + .thumb_set SAI1_A_IRQHandler,Default_Handler + + .weak SAI1_B_IRQHandler + .thumb_set SAI1_B_IRQHandler,Default_Handler + + .weak SAI2_A_IRQHandler + .thumb_set SAI2_A_IRQHandler,Default_Handler + + .weak SAI2_B_IRQHandler + .thumb_set SAI2_B_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak GFXTIM_IRQHandler + .thumb_set GFXTIM_IRQHandler,Default_Handler + + .weak DCMIPP_IRQHandler + .thumb_set DCMIPP_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak GFXMMU_IRQHandler + .thumb_set GFXMMU_IRQHandler,Default_Handler + + .weak I3C1_WKUP_IRQHandler + .thumb_set I3C1_WKUP_IRQHandler,Default_Handler + + .weak MCE1_IRQHandler + .thumb_set MCE1_IRQHandler,Default_Handler + + .weak MCE2_IRQHandler + .thumb_set MCE2_IRQHandler,Default_Handler + + .weak MCE3_IRQHandler + .thumb_set MCE3_IRQHandler,Default_Handler + + .weak XSPI1_IRQHandler + .thumb_set XSPI1_IRQHandler,Default_Handler + + .weak XSPI2_IRQHandler + .thumb_set XSPI2_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak ADF1_FLT0_IRQHandler + .thumb_set ADF1_FLT0_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak PSSI_IRQHandler + .thumb_set PSSI_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + .weak GPDMA1_Channel8_IRQHandler + .thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler + + .weak GPDMA1_Channel9_IRQHandler + .thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler + + .weak GPDMA1_Channel10_IRQHandler + .thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler + + .weak GPDMA1_Channel11_IRQHandler + .thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler + + .weak GPDMA1_Channel12_IRQHandler + .thumb_set GPDMA1_Channel12_IRQHandler,Default_Handler + + .weak GPDMA1_Channel13_IRQHandler + .thumb_set GPDMA1_Channel13_IRQHandler,Default_Handler + + .weak GPDMA1_Channel14_IRQHandler + .thumb_set GPDMA1_Channel14_IRQHandler,Default_Handler + + .weak GPDMA1_Channel15_IRQHandler + .thumb_set GPDMA1_Channel15_IRQHandler,Default_Handler + + .weak HPDMA1_Channel8_IRQHandler + .thumb_set HPDMA1_Channel8_IRQHandler,Default_Handler + + .weak HPDMA1_Channel9_IRQHandler + .thumb_set HPDMA1_Channel9_IRQHandler,Default_Handler + + .weak HPDMA1_Channel10_IRQHandler + .thumb_set HPDMA1_Channel10_IRQHandler,Default_Handler + + .weak HPDMA1_Channel11_IRQHandler + .thumb_set HPDMA1_Channel11_IRQHandler,Default_Handler + + .weak HPDMA1_Channel12_IRQHandler + .thumb_set HPDMA1_Channel12_IRQHandler,Default_Handler + + .weak HPDMA1_Channel13_IRQHandler + .thumb_set HPDMA1_Channel13_IRQHandler,Default_Handler + + .weak HPDMA1_Channel14_IRQHandler + .thumb_set HPDMA1_Channel14_IRQHandler,Default_Handler + + .weak HPDMA1_Channel15_IRQHandler + .thumb_set HPDMA1_Channel15_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak SystemInit \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/startup_stm32h7s7xx.s b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/startup_stm32h7s7xx.s new file mode 100644 index 00000000000..816e67b4b7e --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/startup_stm32h7s7xx.s @@ -0,0 +1,780 @@ +/** + ****************************************************************************** + * @file startup_stm32h7s7xx.s + * @author MCD Application Team + * @brief STM32H7S7xx Devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl entry + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32H7S7xx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + /* External Interrupts */ + .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */ + .word 0 /* Reserved */ + .word DTS_IRQHandler /* Digital Temperature Sensor */ + .word IWDG_IRQHandler /* Internal Watchdog */ + .word WWDG_IRQHandler /* Window Watchdog */ + .word RCC_IRQHandler /* RCC global interrupts through EXTI Line detection */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FLASH_IRQHandler /* FLASH interrupts */ + .word RAMECC_IRQHandler /* RAMECC interrupts */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TAMP_IRQHandler /* Tamper and TimeStamp interrupts */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word EXTI5_IRQHandler /* EXTI Line5 */ + .word EXTI6_IRQHandler /* EXTI Line6 */ + .word EXTI7_IRQHandler /* EXTI Line7 */ + .word EXTI8_IRQHandler /* EXTI Line8 */ + .word EXTI9_IRQHandler /* EXTI Line9 */ + .word EXTI10_IRQHandler /* EXTI Line10 */ + .word EXTI11_IRQHandler /* EXTI Line11 */ + .word EXTI12_IRQHandler /* EXTI Line12 */ + .word EXTI13_IRQHandler /* EXTI Line13 */ + .word EXTI14_IRQHandler /* EXTI Line14 */ + .word EXTI15_IRQHandler /* EXTI Line15 */ + .word RTC_IRQHandler /* RTC wakeup and alarm interrupts */ + .word SAES_IRQHandler /* SAES */ + .word CRYP_IRQHandler /* CRYP */ + .word PKA_IRQHandler /* PKA */ + .word HASH_IRQHandler /* HASH */ + .word RNG_IRQHandler /* RNG */ + .word ADC1_2_IRQHandler /* ADC1 & ADC2 */ + .word GPDMA1_Channel0_IRQHandler /* GPDMA1 Channel 0 */ + .word GPDMA1_Channel1_IRQHandler /* GPDMA1 Channel 1 */ + .word GPDMA1_Channel2_IRQHandler /* GPDMA1 Channel 2 */ + .word GPDMA1_Channel3_IRQHandler /* GPDMA1 Channel 3 */ + .word GPDMA1_Channel4_IRQHandler /* GPDMA1 Channel 4 */ + .word GPDMA1_Channel5_IRQHandler /* GPDMA1 Channel 5 */ + .word GPDMA1_Channel6_IRQHandler /* GPDMA1 Channel 6 */ + .word GPDMA1_Channel7_IRQHandler /* GPDMA1 Channel 7 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word TIM5_IRQHandler /* TIM5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word TIM9_IRQHandler /* TIM9 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word SPI3_IRQHandler /* SPI3 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word HPDMA1_Channel0_IRQHandler /* HPDMA1 Channel 0 */ + .word HPDMA1_Channel1_IRQHandler /* HPDMA1 Channel 1 */ + .word HPDMA1_Channel2_IRQHandler /* HPDMA1 Channel 2 */ + .word HPDMA1_Channel3_IRQHandler /* HPDMA1 Channel 3 */ + .word HPDMA1_Channel4_IRQHandler /* HPDMA1 Channel 4 */ + .word HPDMA1_Channel5_IRQHandler /* HPDMA1 Channel 5 */ + .word HPDMA1_Channel6_IRQHandler /* HPDMA1 Channel 6 */ + .word HPDMA1_Channel7_IRQHandler /* HPDMA1 Channel 7 */ + .word SAI1_A_IRQHandler /* Serial Audio Interface 1 block A */ + .word SAI1_B_IRQHandler /* Serial Audio Interface 1 block B */ + .word SAI2_A_IRQHandler /* Serial Audio Interface 2 block A */ + .word SAI2_B_IRQHandler /* Serial Audio Interface 2 block B */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word I2C3_EV_IRQHandler /* I2C3 Event */ + .word I2C3_ER_IRQHandler /* I2C3 Error */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word I3C1_EV_IRQHandler /* I3C1 Event */ + .word I3C1_ER_IRQHandler /* I3C1 Error */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word ETH_IRQHandler /* Ethernet */ + .word CORDIC_IRQHandler /* CORDIC */ + .word GFXTIM_IRQHandler /* GFXTIM */ + .word DCMIPP_IRQHandler /* DCMIPP */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word JPEG_IRQHandler /* JPEG */ + .word GFXMMU_IRQHandler /* GFXMMU */ + .word I3C1_WKUP_IRQHandler /* I3C1 wakeup */ + .word MCE1_IRQHandler /* MCE1 */ + .word MCE2_IRQHandler /* MCE2 */ + .word MCE3_IRQHandler /* MCE3 */ + .word XSPI1_IRQHandler /* XSPI1 */ + .word XSPI2_IRQHandler /* XSPI2 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word SDMMC2_IRQHandler /* SDMMC2 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word TIM12_IRQHandler /* TIM12 */ + .word TIM13_IRQHandler /* TIM13 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word LPTIM1_IRQHandler /* LP TIM1 */ + .word LPTIM2_IRQHandler /* LP TIM2 */ + .word LPTIM3_IRQHandler /* LP TIM3 */ + .word LPTIM4_IRQHandler /* LP TIM4 */ + .word LPTIM5_IRQHandler /* LP TIM5 */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word MDIOS_IRQHandler /* MDIOS */ + .word ADF1_FLT0_IRQHandler /* ADF1 Filter 0 */ + .word CRS_IRQHandler /* CRS */ + .word UCPD1_IRQHandler /* UCPD1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word PSSI_IRQHandler /* PSSI */ + .word LPUART1_IRQHandler /* LP UART1 */ + .word WAKEUP_PIN_IRQHandler /* Wake-up pins interrupt */ + .word GPDMA1_Channel8_IRQHandler /* GPDMA1 Channel 8 */ + .word GPDMA1_Channel9_IRQHandler /* GPDMA1 Channel 9 */ + .word GPDMA1_Channel10_IRQHandler /* GPDMA1 Channel 10 */ + .word GPDMA1_Channel11_IRQHandler /* GPDMA1 Channel 11 */ + .word GPDMA1_Channel12_IRQHandler /* GPDMA1 Channel 12 */ + .word GPDMA1_Channel13_IRQHandler /* GPDMA1 Channel 13 */ + .word GPDMA1_Channel14_IRQHandler /* GPDMA1 Channel 14 */ + .word GPDMA1_Channel15_IRQHandler /* GPDMA1 Channel 15 */ + .word HPDMA1_Channel8_IRQHandler /* HPDMA1 Channel 8 */ + .word HPDMA1_Channel9_IRQHandler /* HPDMA1 Channel 9 */ + .word HPDMA1_Channel10_IRQHandler /* HPDMA1 Channel 10 */ + .word HPDMA1_Channel11_IRQHandler /* HPDMA1 Channel 11 */ + .word HPDMA1_Channel12_IRQHandler /* HPDMA1 Channel 12 */ + .word HPDMA1_Channel13_IRQHandler /* HPDMA1 Channel 13 */ + .word HPDMA1_Channel14_IRQHandler /* HPDMA1 Channel 14 */ + .word HPDMA1_Channel15_IRQHandler /* HPDMA1 Channel 15 */ + .word GPU2D_IRQHandler /* GPU2D */ + .word GPU2D_ER_IRQHandler /* GPU2D error */ + .word ICACHE_IRQHandler /* ICACHE */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 Interrupt 0 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 Interrupt 1 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RAMECC_IRQHandler + .thumb_set RAMECC_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak SAES_IRQHandler + .thumb_set SAES_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak HPDMA1_Channel0_IRQHandler + .thumb_set HPDMA1_Channel0_IRQHandler,Default_Handler + + .weak HPDMA1_Channel1_IRQHandler + .thumb_set HPDMA1_Channel1_IRQHandler,Default_Handler + + .weak HPDMA1_Channel2_IRQHandler + .thumb_set HPDMA1_Channel2_IRQHandler,Default_Handler + + .weak HPDMA1_Channel3_IRQHandler + .thumb_set HPDMA1_Channel3_IRQHandler,Default_Handler + + .weak HPDMA1_Channel4_IRQHandler + .thumb_set HPDMA1_Channel4_IRQHandler,Default_Handler + + .weak HPDMA1_Channel5_IRQHandler + .thumb_set HPDMA1_Channel5_IRQHandler,Default_Handler + + .weak HPDMA1_Channel6_IRQHandler + .thumb_set HPDMA1_Channel6_IRQHandler,Default_Handler + + .weak HPDMA1_Channel7_IRQHandler + .thumb_set HPDMA1_Channel7_IRQHandler,Default_Handler + + .weak SAI1_A_IRQHandler + .thumb_set SAI1_A_IRQHandler,Default_Handler + + .weak SAI1_B_IRQHandler + .thumb_set SAI1_B_IRQHandler,Default_Handler + + .weak SAI2_A_IRQHandler + .thumb_set SAI2_A_IRQHandler,Default_Handler + + .weak SAI2_B_IRQHandler + .thumb_set SAI2_B_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak GFXTIM_IRQHandler + .thumb_set GFXTIM_IRQHandler,Default_Handler + + .weak DCMIPP_IRQHandler + .thumb_set DCMIPP_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak GFXMMU_IRQHandler + .thumb_set GFXMMU_IRQHandler,Default_Handler + + .weak I3C1_WKUP_IRQHandler + .thumb_set I3C1_WKUP_IRQHandler,Default_Handler + + .weak MCE1_IRQHandler + .thumb_set MCE1_IRQHandler,Default_Handler + + .weak MCE2_IRQHandler + .thumb_set MCE2_IRQHandler,Default_Handler + + .weak MCE3_IRQHandler + .thumb_set MCE3_IRQHandler,Default_Handler + + .weak XSPI1_IRQHandler + .thumb_set XSPI1_IRQHandler,Default_Handler + + .weak XSPI2_IRQHandler + .thumb_set XSPI2_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak ADF1_FLT0_IRQHandler + .thumb_set ADF1_FLT0_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak PSSI_IRQHandler + .thumb_set PSSI_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + .weak GPDMA1_Channel8_IRQHandler + .thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler + + .weak GPDMA1_Channel9_IRQHandler + .thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler + + .weak GPDMA1_Channel10_IRQHandler + .thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler + + .weak GPDMA1_Channel11_IRQHandler + .thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler + + .weak GPDMA1_Channel12_IRQHandler + .thumb_set GPDMA1_Channel12_IRQHandler,Default_Handler + + .weak GPDMA1_Channel13_IRQHandler + .thumb_set GPDMA1_Channel13_IRQHandler,Default_Handler + + .weak GPDMA1_Channel14_IRQHandler + .thumb_set GPDMA1_Channel14_IRQHandler,Default_Handler + + .weak GPDMA1_Channel15_IRQHandler + .thumb_set GPDMA1_Channel15_IRQHandler,Default_Handler + + .weak HPDMA1_Channel8_IRQHandler + .thumb_set HPDMA1_Channel8_IRQHandler,Default_Handler + + .weak HPDMA1_Channel9_IRQHandler + .thumb_set HPDMA1_Channel9_IRQHandler,Default_Handler + + .weak HPDMA1_Channel10_IRQHandler + .thumb_set HPDMA1_Channel10_IRQHandler,Default_Handler + + .weak HPDMA1_Channel11_IRQHandler + .thumb_set HPDMA1_Channel11_IRQHandler,Default_Handler + + .weak HPDMA1_Channel12_IRQHandler + .thumb_set HPDMA1_Channel12_IRQHandler,Default_Handler + + .weak HPDMA1_Channel13_IRQHandler + .thumb_set HPDMA1_Channel13_IRQHandler,Default_Handler + + .weak HPDMA1_Channel14_IRQHandler + .thumb_set HPDMA1_Channel14_IRQHandler,Default_Handler + + .weak HPDMA1_Channel15_IRQHandler + .thumb_set HPDMA1_Channel15_IRQHandler,Default_Handler + + .weak GPU2D_IRQHandler + .thumb_set GPU2D_IRQHandler,Default_Handler + + .weak GPU2D_ER_IRQHandler + .thumb_set GPU2D_ER_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak SystemInit \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7r3xx_flash.icf b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7r3xx_flash.icf new file mode 100644 index 00000000000..1382cdf2392 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7r3xx_flash.icf @@ -0,0 +1,55 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol NONCACHEABLEBUFFER_size = 0x400; +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size; +define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; +define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_ITCM_start__ = 0x00000000; +define symbol __region_ITCM_end__ = 0x0000FFFF; +define symbol __region_DTCM_start__ = 0x20000000; +define symbol __region_DTCM_end__ = 0x2000FFFF; +define symbol __region_SRAMAHB_start__ = 0x30000000; +define symbol __region_SRAMAHB_end__ = 0x30007FFF; +define symbol __region_BKPSRAM_start__ = 0x38800000; +define symbol __region_BKPSRAM_end__ = 0x38800FFF; + +export symbol NONCACHEABLEBUFFER_start; +export symbol NONCACHEABLEBUFFER_size; + +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; +define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; +define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; +define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; +define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place in NONCACHEABLE_region { section noncacheable_buffer }; +place in DTCM_region { block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7r3xx_sram.icf b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7r3xx_sram.icf new file mode 100644 index 00000000000..3b784f1ec79 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7r3xx_sram.icf @@ -0,0 +1,55 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x24050000; +/*-Memory Regions-*/ +define symbol NONCACHEABLEBUFFER_size = 0x400; +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size; +define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; +define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; +define symbol __ICFEDIT_region_ROM_start__ = 0x24050000; +define symbol __ICFEDIT_region_ROM_end__ = 0x24071FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_ITCM_start__ = 0x00000000; +define symbol __region_ITCM_end__ = 0x0000FFFF; +define symbol __region_DTCM_start__ = 0x20000000; +define symbol __region_DTCM_end__ = 0x2000FFFF; +define symbol __region_SRAMAHB_start__ = 0x30000000; +define symbol __region_SRAMAHB_end__ = 0x30007FFF; +define symbol __region_BKPSRAM_start__ = 0x38800000; +define symbol __region_BKPSRAM_end__ = 0x38800FFF; + +export symbol NONCACHEABLEBUFFER_start; +export symbol NONCACHEABLEBUFFER_size; + +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; +define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; +define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; +define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; +define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec}; + +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place in NONCACHEABLE_region { section noncacheable_buffer }; +place in DTCM_region { block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7r7xx_flash.icf b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7r7xx_flash.icf new file mode 100644 index 00000000000..1382cdf2392 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7r7xx_flash.icf @@ -0,0 +1,55 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol NONCACHEABLEBUFFER_size = 0x400; +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size; +define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; +define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_ITCM_start__ = 0x00000000; +define symbol __region_ITCM_end__ = 0x0000FFFF; +define symbol __region_DTCM_start__ = 0x20000000; +define symbol __region_DTCM_end__ = 0x2000FFFF; +define symbol __region_SRAMAHB_start__ = 0x30000000; +define symbol __region_SRAMAHB_end__ = 0x30007FFF; +define symbol __region_BKPSRAM_start__ = 0x38800000; +define symbol __region_BKPSRAM_end__ = 0x38800FFF; + +export symbol NONCACHEABLEBUFFER_start; +export symbol NONCACHEABLEBUFFER_size; + +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; +define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; +define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; +define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; +define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place in NONCACHEABLE_region { section noncacheable_buffer }; +place in DTCM_region { block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7r7xx_sram.icf b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7r7xx_sram.icf new file mode 100644 index 00000000000..3b784f1ec79 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7r7xx_sram.icf @@ -0,0 +1,55 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x24050000; +/*-Memory Regions-*/ +define symbol NONCACHEABLEBUFFER_size = 0x400; +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size; +define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; +define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; +define symbol __ICFEDIT_region_ROM_start__ = 0x24050000; +define symbol __ICFEDIT_region_ROM_end__ = 0x24071FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_ITCM_start__ = 0x00000000; +define symbol __region_ITCM_end__ = 0x0000FFFF; +define symbol __region_DTCM_start__ = 0x20000000; +define symbol __region_DTCM_end__ = 0x2000FFFF; +define symbol __region_SRAMAHB_start__ = 0x30000000; +define symbol __region_SRAMAHB_end__ = 0x30007FFF; +define symbol __region_BKPSRAM_start__ = 0x38800000; +define symbol __region_BKPSRAM_end__ = 0x38800FFF; + +export symbol NONCACHEABLEBUFFER_start; +export symbol NONCACHEABLEBUFFER_size; + +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; +define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; +define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; +define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; +define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec}; + +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place in NONCACHEABLE_region { section noncacheable_buffer }; +place in DTCM_region { block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_RAMxspi1_ROMxspi2.icf b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_RAMxspi1_ROMxspi2.icf new file mode 100644 index 00000000000..2f0fbe000f6 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_RAMxspi1_ROMxspi2.icf @@ -0,0 +1,61 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x70000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x70000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x77FFFFFF; +define symbol NONCACHEABLEBUFFER_size = 0x400; +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size; +define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; +define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_ITCM_start__ = 0x00000000; +define symbol __region_ITCM_end__ = 0x0000FFFF; +define symbol __region_DTCM_start__ = 0x20000000; +define symbol __region_DTCM_end__ = 0x2000FFFF; +define symbol __region_SRAMAHB_start__ = 0x30000000; +define symbol __region_SRAMAHB_end__ = 0x30007FFF; +define symbol __region_BKPSRAM_start__ = 0x38800000; +define symbol __region_BKPSRAM_end__ = 0x38800FFF; +define symbol __region_EXTRAM_start__ = 0x90000000; +define symbol __region_EXTRAM_end__ = 0x91FFFFFF; + +export symbol NONCACHEABLEBUFFER_start; +export symbol NONCACHEABLEBUFFER_size; + +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; + +export symbol __region_EXTRAM_start__; +export symbol __region_EXTRAM_end__; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region EXTRAM_region = mem:[from __region_EXTRAM_start__ to __region_EXTRAM_end__]; +define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; +define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; +define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; +define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; +define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place in NONCACHEABLE_region { section noncacheable_buffer }; +place in DTCM_region { block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_ROMxspi1.icf b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_ROMxspi1.icf new file mode 100644 index 00000000000..df317ef5c81 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_ROMxspi1.icf @@ -0,0 +1,55 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x90000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x90000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x97FFFFFF; +define symbol NONCACHEABLEBUFFER_size = 0x400; +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size; +define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; +define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_ITCM_start__ = 0x00000000; +define symbol __region_ITCM_end__ = 0x0000FFFF; +define symbol __region_DTCM_start__ = 0x20000000; +define symbol __region_DTCM_end__ = 0x2000FFFF; +define symbol __region_SRAMAHB_start__ = 0x30000000; +define symbol __region_SRAMAHB_end__ = 0x30007FFF; +define symbol __region_BKPSRAM_start__ = 0x38800000; +define symbol __region_BKPSRAM_end__ = 0x38800FFF; + +export symbol NONCACHEABLEBUFFER_start; +export symbol NONCACHEABLEBUFFER_size; + +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; +define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; +define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; +define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; +define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place in NONCACHEABLE_region { section noncacheable_buffer }; +place in DTCM_region { block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_ROMxspi1_RAMxspi2.icf b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_ROMxspi1_RAMxspi2.icf new file mode 100644 index 00000000000..7519a0bbeaa --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_ROMxspi1_RAMxspi2.icf @@ -0,0 +1,62 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x90000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x90000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x97FFFFFF; +define symbol NONCACHEABLEBUFFER_size = 0x400; +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size; +define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; +define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_ITCM_start__ = 0x00000000; +define symbol __region_ITCM_end__ = 0x0000FFFF; +define symbol __region_DTCM_start__ = 0x20000000; +define symbol __region_DTCM_end__ = 0x2000FFFF; +define symbol __region_SRAMAHB_start__ = 0x30000000; +define symbol __region_SRAMAHB_end__ = 0x30007FFF; +define symbol __region_BKPSRAM_start__ = 0x38800000; +define symbol __region_BKPSRAM_end__ = 0x38800FFF; +define symbol __region_EXTRAM_start__ = 0x70000000; +define symbol __region_EXTRAM_end__ = 0x71FFFFFF; + +export symbol NONCACHEABLEBUFFER_start; +export symbol NONCACHEABLEBUFFER_size; + +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; + +export symbol __region_EXTRAM_start__; +export symbol __region_EXTRAM_end__; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region EXTRAM_region = mem:[from __region_EXTRAM_start__ to __region_EXTRAM_end__]; +define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; +define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; +define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; +define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; +define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place in NONCACHEABLE_region { section noncacheable_buffer }; +place in DTCM_region { block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_ROMxspi2.icf b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_ROMxspi2.icf new file mode 100644 index 00000000000..fd3eaefc8ab --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_ROMxspi2.icf @@ -0,0 +1,56 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x70000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x70000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x77FFFFFF; +define symbol NONCACHEABLEBUFFER_size = 0x400; +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size; +define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; +define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_ITCM_start__ = 0x00000000; +define symbol __region_ITCM_end__ = 0x0000FFFF; +define symbol __region_DTCM_start__ = 0x20000000; +define symbol __region_DTCM_end__ = 0x2000FFFF; +define symbol __region_SRAMAHB_start__ = 0x30000000; +define symbol __region_SRAMAHB_end__ = 0x30007FFF; +define symbol __region_BKPSRAM_start__ = 0x38800000; +define symbol __region_BKPSRAM_end__ = 0x38800FFF; + +export symbol NONCACHEABLEBUFFER_start; +export symbol NONCACHEABLEBUFFER_size; + +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; +define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; +define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; +define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; +define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place in NONCACHEABLE_region { section noncacheable_buffer }; +place in DTCM_region { block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_extmemloader_ewarm.icf b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_extmemloader_ewarm.icf new file mode 100644 index 00000000000..aaa1cadce52 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_extmemloader_ewarm.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_1.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x00000040; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x0000EFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0000F000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0000FFFF; +define symbol __ICFEDIT_region_DTCM_start__ = 0x20000000; +define symbol __ICFEDIT_region_DTCM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; /* not used defined the min size */ +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; +define region IRAM_region_2 = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; +define region DTCM_region = mem:[from __ICFEDIT_region_DTCM_start__ to __ICFEDIT_region_DTCM_end__]; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +do not initialize { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { section .intvec }; +place at start of IRAM_region { readonly }; +place in IRAM_region { block RamTop with fixed order { readwrite, block CSTACK, block HEAP }}; +place in IRAM_region_2 { zi}; +place at start of DTCM_region { section RAMBUFFER_END }; +place at end of DTCM_region { section RAMBUFFER_START }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_extmemloader_stm32cube.icf b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_extmemloader_stm32cube.icf new file mode 100644 index 00000000000..7323f1b3f23 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_extmemloader_stm32cube.icf @@ -0,0 +1,22 @@ + +define symbol __ICFEDIT_region_RAM_start__ = 0x20000004; +define symbol __ICFEDIT_region_RAM_end__ = 0x20010000; + +define symbol __ICFEDIT_region_RAM2_start__ = 0x24020000; +define symbol __ICFEDIT_region_RAM2_end__ = 0x24040000; + +export symbol __ICFEDIT_region_RAM_end__; + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]; +define region Info_region = mem:[from 0 to 0x3000]; + +define block RAM_BLOCK with fixed order {readonly code, readonly data, readwrite }; +define block StorageInfo_BLOCK with fixed order { readonly data object stm32_device_Info.o}; + +place in RAM_region { block RAM_BLOCK}; +place in RAM2_region { zi }; +place in Info_region { block StorageInfo_BLOCK }; + +do not initialize { section .info, readwrite }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_sram.icf b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_sram.icf new file mode 100644 index 00000000000..3b784f1ec79 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7rsxx_sram.icf @@ -0,0 +1,55 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x24050000; +/*-Memory Regions-*/ +define symbol NONCACHEABLEBUFFER_size = 0x400; +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size; +define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; +define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; +define symbol __ICFEDIT_region_ROM_start__ = 0x24050000; +define symbol __ICFEDIT_region_ROM_end__ = 0x24071FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_ITCM_start__ = 0x00000000; +define symbol __region_ITCM_end__ = 0x0000FFFF; +define symbol __region_DTCM_start__ = 0x20000000; +define symbol __region_DTCM_end__ = 0x2000FFFF; +define symbol __region_SRAMAHB_start__ = 0x30000000; +define symbol __region_SRAMAHB_end__ = 0x30007FFF; +define symbol __region_BKPSRAM_start__ = 0x38800000; +define symbol __region_BKPSRAM_end__ = 0x38800FFF; + +export symbol NONCACHEABLEBUFFER_start; +export symbol NONCACHEABLEBUFFER_size; + +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; +define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; +define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; +define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; +define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec}; + +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place in NONCACHEABLE_region { section noncacheable_buffer }; +place in DTCM_region { block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7s3xx_flash.icf b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7s3xx_flash.icf new file mode 100644 index 00000000000..1382cdf2392 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7s3xx_flash.icf @@ -0,0 +1,55 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol NONCACHEABLEBUFFER_size = 0x400; +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size; +define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; +define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_ITCM_start__ = 0x00000000; +define symbol __region_ITCM_end__ = 0x0000FFFF; +define symbol __region_DTCM_start__ = 0x20000000; +define symbol __region_DTCM_end__ = 0x2000FFFF; +define symbol __region_SRAMAHB_start__ = 0x30000000; +define symbol __region_SRAMAHB_end__ = 0x30007FFF; +define symbol __region_BKPSRAM_start__ = 0x38800000; +define symbol __region_BKPSRAM_end__ = 0x38800FFF; + +export symbol NONCACHEABLEBUFFER_start; +export symbol NONCACHEABLEBUFFER_size; + +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; +define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; +define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; +define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; +define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place in NONCACHEABLE_region { section noncacheable_buffer }; +place in DTCM_region { block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7s3xx_sram.icf b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7s3xx_sram.icf new file mode 100644 index 00000000000..3b784f1ec79 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7s3xx_sram.icf @@ -0,0 +1,55 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x24050000; +/*-Memory Regions-*/ +define symbol NONCACHEABLEBUFFER_size = 0x400; +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size; +define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; +define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; +define symbol __ICFEDIT_region_ROM_start__ = 0x24050000; +define symbol __ICFEDIT_region_ROM_end__ = 0x24071FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_ITCM_start__ = 0x00000000; +define symbol __region_ITCM_end__ = 0x0000FFFF; +define symbol __region_DTCM_start__ = 0x20000000; +define symbol __region_DTCM_end__ = 0x2000FFFF; +define symbol __region_SRAMAHB_start__ = 0x30000000; +define symbol __region_SRAMAHB_end__ = 0x30007FFF; +define symbol __region_BKPSRAM_start__ = 0x38800000; +define symbol __region_BKPSRAM_end__ = 0x38800FFF; + +export symbol NONCACHEABLEBUFFER_start; +export symbol NONCACHEABLEBUFFER_size; + +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; +define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; +define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; +define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; +define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec}; + +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place in NONCACHEABLE_region { section noncacheable_buffer }; +place in DTCM_region { block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7s7xx_flash.icf b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7s7xx_flash.icf new file mode 100644 index 00000000000..1382cdf2392 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7s7xx_flash.icf @@ -0,0 +1,55 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol NONCACHEABLEBUFFER_size = 0x400; +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size; +define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; +define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_ITCM_start__ = 0x00000000; +define symbol __region_ITCM_end__ = 0x0000FFFF; +define symbol __region_DTCM_start__ = 0x20000000; +define symbol __region_DTCM_end__ = 0x2000FFFF; +define symbol __region_SRAMAHB_start__ = 0x30000000; +define symbol __region_SRAMAHB_end__ = 0x30007FFF; +define symbol __region_BKPSRAM_start__ = 0x38800000; +define symbol __region_BKPSRAM_end__ = 0x38800FFF; + +export symbol NONCACHEABLEBUFFER_start; +export symbol NONCACHEABLEBUFFER_size; + +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; +define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; +define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; +define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; +define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place in NONCACHEABLE_region { section noncacheable_buffer }; +place in DTCM_region { block CSTACK, block HEAP }; diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7s7xx_sram.icf b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7s7xx_sram.icf new file mode 100644 index 00000000000..3b784f1ec79 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/linker/stm32h7s7xx_sram.icf @@ -0,0 +1,55 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x24050000; +/*-Memory Regions-*/ +define symbol NONCACHEABLEBUFFER_size = 0x400; +define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size; +define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; +define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; +define symbol __ICFEDIT_region_ROM_start__ = 0x24050000; +define symbol __ICFEDIT_region_ROM_end__ = 0x24071FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_ITCM_start__ = 0x00000000; +define symbol __region_ITCM_end__ = 0x0000FFFF; +define symbol __region_DTCM_start__ = 0x20000000; +define symbol __region_DTCM_end__ = 0x2000FFFF; +define symbol __region_SRAMAHB_start__ = 0x30000000; +define symbol __region_SRAMAHB_end__ = 0x30007FFF; +define symbol __region_BKPSRAM_start__ = 0x38800000; +define symbol __region_BKPSRAM_end__ = 0x38800FFF; + +export symbol NONCACHEABLEBUFFER_start; +export symbol NONCACHEABLEBUFFER_size; + +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; +define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; +define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; +define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; +define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec}; + +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place in NONCACHEABLE_region { section noncacheable_buffer }; +place in DTCM_region { block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/startup_stm32h7r3xx.s b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/startup_stm32h7r3xx.s new file mode 100644 index 00000000000..b6bb0d131c4 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/startup_stm32h7r3xx.s @@ -0,0 +1,981 @@ +;******************************************************************************** +;* File Name : startup_stm32h7r3xx.s +;* Author : MCD Application Team +;* Description : STM32H7R3xx Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2022 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection + DCD 0 ; Reserved + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD IWDG_IRQHandler ; Internal Watchdog + DCD WWDG_IRQHandler ; Window Watchdog + DCD RCC_IRQHandler ; RCC global interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FLASH_IRQHandler ; FLASH interrupts + DCD RAMECC_IRQHandler ; RAMECC interrupts + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TAMP_IRQHandler ; Tamper and TimeStamp interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD EXTI5_IRQHandler ; EXTI Line5 + DCD EXTI6_IRQHandler ; EXTI Line6 + DCD EXTI7_IRQHandler ; EXTI Line7 + DCD EXTI8_IRQHandler ; EXTI Line8 + DCD EXTI9_IRQHandler ; EXTI Line9 + DCD EXTI10_IRQHandler ; EXTI Line10 + DCD EXTI11_IRQHandler ; EXTI Line11 + DCD EXTI12_IRQHandler ; EXTI Line12 + DCD EXTI13_IRQHandler ; EXTI Line13 + DCD EXTI14_IRQHandler ; EXTI Line14 + DCD EXTI15_IRQHandler ; EXTI Line15 + DCD RTC_IRQHandler ; RTC wakeup and alarm interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PKA_IRQHandler ; PKA + DCD HASH_IRQHandler ; HASH + DCD RNG_IRQHandler ; RNG + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 + DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 + DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 + DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 + DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 + DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 + DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 + DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD TIM9_IRQHandler ; TIM9 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD SPI3_IRQHandler ; SPI3 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD HPDMA1_Channel0_IRQHandler ; HPDMA1 Channel 0 + DCD HPDMA1_Channel1_IRQHandler ; HPDMA1 Channel 1 + DCD HPDMA1_Channel2_IRQHandler ; HPDMA1 Channel 2 + DCD HPDMA1_Channel3_IRQHandler ; HPDMA1 Channel 3 + DCD HPDMA1_Channel4_IRQHandler ; HPDMA1 Channel 4 + DCD HPDMA1_Channel5_IRQHandler ; HPDMA1 Channel 5 + DCD HPDMA1_Channel6_IRQHandler ; HPDMA1 Channel 6 + DCD HPDMA1_Channel7_IRQHandler ; HPDMA1 Channel 7 + DCD SAI1_A_IRQHandler ; Serial Audio Interface 1 block A + DCD SAI1_B_IRQHandler ; Serial Audio Interface 1 block B + DCD SAI2_A_IRQHandler ; Serial Audio Interface 2 block A + DCD SAI2_B_IRQHandler ; Serial Audio Interface 2 block B + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD I3C1_EV_IRQHandler ; I3C1 Event + DCD I3C1_ER_IRQHandler ; I3C1 Error + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD ETH_IRQHandler ; Ethernet + DCD CORDIC_IRQHandler ; CORDIC + DCD GFXTIM_IRQHandler ; GFXTIM + DCD DCMIPP_IRQHandler ; DCMIPP + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2D_IRQHandler ; DMA2D + DCD JPEG_IRQHandler ; JPEG + DCD GFXMMU_IRQHandler ; GFXMMU + DCD I3C1_WKUP_IRQHandler ; I3C1 wakeup + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD XSPI1_IRQHandler ; XSPI1 + DCD XSPI2_IRQHandler ; XSPI2 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD LPTIM1_IRQHandler ; LP TIM1 + DCD LPTIM2_IRQHandler ; LP TIM2 + DCD LPTIM3_IRQHandler ; LP TIM3 + DCD LPTIM4_IRQHandler ; LP TIM4 + DCD LPTIM5_IRQHandler ; LP TIM5 + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD MDIOS_IRQHandler ; MDIOS + DCD ADF1_FLT0_IRQHandler ; ADF1 Filter 0 + DCD CRS_IRQHandler ; CRS + DCD UCPD1_IRQHandler ; UCPD1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD PSSI_IRQHandler ; PSSI + DCD LPUART1_IRQHandler ; LP UART1 + DCD WAKEUP_PIN_IRQHandler ; Wake-up pins interrupt + DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8 + DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9 + DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10 + DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11 + DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12 + DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13 + DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14 + DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15 + DCD HPDMA1_Channel8_IRQHandler ; HPDMA1 Channel 8 + DCD HPDMA1_Channel9_IRQHandler ; HPDMA1 Channel 9 + DCD HPDMA1_Channel10_IRQHandler ; HPDMA1 Channel 10 + DCD HPDMA1_Channel11_IRQHandler ; HPDMA1 Channel 11 + DCD HPDMA1_Channel12_IRQHandler ; HPDMA1 Channel 12 + DCD HPDMA1_Channel13_IRQHandler ; HPDMA1 Channel 13 + DCD HPDMA1_Channel14_IRQHandler ; HPDMA1 Channel 14 + DCD HPDMA1_Channel15_IRQHandler ; HPDMA1 Channel 15 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt 1 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt 1 +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK DTS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DTS_IRQHandler + B DTS_IRQHandler + + PUBWEAK IWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +IWDG_IRQHandler + B IWDG_IRQHandler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RAMECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RAMECC_IRQHandler + B RAMECC_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK TAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_IRQHandler + B TAMP_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK EXTI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_IRQHandler + B EXTI5_IRQHandler + + PUBWEAK EXTI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI6_IRQHandler + B EXTI6_IRQHandler + + PUBWEAK EXTI7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI7_IRQHandler + B EXTI7_IRQHandler + + PUBWEAK EXTI8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI8_IRQHandler + B EXTI8_IRQHandler + + PUBWEAK EXTI9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_IRQHandler + B EXTI9_IRQHandler + + PUBWEAK EXTI10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_IRQHandler + B EXTI10_IRQHandler + + PUBWEAK EXTI11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI11_IRQHandler + B EXTI11_IRQHandler + + PUBWEAK EXTI12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI12_IRQHandler + B EXTI12_IRQHandler + + PUBWEAK EXTI13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI13_IRQHandler + B EXTI13_IRQHandler + + PUBWEAK EXTI14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI14_IRQHandler + B EXTI14_IRQHandler + + PUBWEAK EXTI15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_IRQHandler + B EXTI15_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK PKA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PKA_IRQHandler + B PKA_IRQHandler + + PUBWEAK HASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_IRQHandler + B HASH_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK GPDMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel0_IRQHandler + B GPDMA1_Channel0_IRQHandler + + PUBWEAK GPDMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel1_IRQHandler + B GPDMA1_Channel1_IRQHandler + + PUBWEAK GPDMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel2_IRQHandler + B GPDMA1_Channel2_IRQHandler + + PUBWEAK GPDMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel3_IRQHandler + B GPDMA1_Channel3_IRQHandler + + PUBWEAK GPDMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel4_IRQHandler + B GPDMA1_Channel4_IRQHandler + + PUBWEAK GPDMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel5_IRQHandler + B GPDMA1_Channel5_IRQHandler + + PUBWEAK GPDMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel6_IRQHandler + B GPDMA1_Channel6_IRQHandler + + PUBWEAK GPDMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel7_IRQHandler + B GPDMA1_Channel7_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK TIM9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM9_IRQHandler + B TIM9_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK HPDMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel0_IRQHandler + B HPDMA1_Channel0_IRQHandler + + PUBWEAK HPDMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel1_IRQHandler + B HPDMA1_Channel1_IRQHandler + + PUBWEAK HPDMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel2_IRQHandler + B HPDMA1_Channel2_IRQHandler + + PUBWEAK HPDMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel3_IRQHandler + B HPDMA1_Channel3_IRQHandler + + PUBWEAK HPDMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel4_IRQHandler + B HPDMA1_Channel4_IRQHandler + + PUBWEAK HPDMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel5_IRQHandler + B HPDMA1_Channel5_IRQHandler + + PUBWEAK HPDMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel6_IRQHandler + B HPDMA1_Channel6_IRQHandler + + PUBWEAK HPDMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel7_IRQHandler + B HPDMA1_Channel7_IRQHandler + + PUBWEAK SAI1_A_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_A_IRQHandler + B SAI1_A_IRQHandler + + PUBWEAK SAI1_B_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_B_IRQHandler + B SAI1_A_IRQHandler + + PUBWEAK SAI2_A_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_A_IRQHandler + B SAI2_A_IRQHandler + + PUBWEAK SAI2_B_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_B_IRQHandler + B SAI2_B_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK I3C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I3C1_EV_IRQHandler + B I3C1_EV_IRQHandler + + PUBWEAK I3C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I3C1_ER_IRQHandler + B I3C1_ER_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + PUBWEAK GFXTIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GFXTIM_IRQHandler + B GFXTIM_IRQHandler + + PUBWEAK DCMIPP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMIPP_IRQHandler + B DCMIPP_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler + B JPEG_IRQHandler + + PUBWEAK GFXMMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GFXMMU_IRQHandler + B GFXMMU_IRQHandler + + PUBWEAK I3C1_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I3C1_WKUP_IRQHandler + B I3C1_WKUP_IRQHandler + + PUBWEAK XSPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +XSPI1_IRQHandler + B XSPI1_IRQHandler + + PUBWEAK XSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +XSPI2_IRQHandler + B XSPI2_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM12_IRQHandler + B TIM12_IRQHandler + + PUBWEAK TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM13_IRQHandler + B TIM13_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler + B LPTIM3_IRQHandler + + PUBWEAK LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler + B LPTIM4_IRQHandler + + PUBWEAK LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler + B MDIOS_IRQHandler + + PUBWEAK ADF1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADF1_FLT0_IRQHandler + B ADF1_FLT0_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK UCPD1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UCPD1_IRQHandler + B UCPD1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK PSSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PSSI_IRQHandler + B PSSI_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler + + PUBWEAK GPDMA1_Channel8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel8_IRQHandler + B GPDMA1_Channel8_IRQHandler + + PUBWEAK GPDMA1_Channel9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel9_IRQHandler + B GPDMA1_Channel9_IRQHandler + + PUBWEAK GPDMA1_Channel10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel10_IRQHandler + B GPDMA1_Channel10_IRQHandler + + PUBWEAK GPDMA1_Channel11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel11_IRQHandler + B GPDMA1_Channel11_IRQHandler + + PUBWEAK GPDMA1_Channel12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel12_IRQHandler + B GPDMA1_Channel12_IRQHandler + + PUBWEAK GPDMA1_Channel13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel13_IRQHandler + B GPDMA1_Channel13_IRQHandler + + PUBWEAK GPDMA1_Channel14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel14_IRQHandler + B GPDMA1_Channel14_IRQHandler + + PUBWEAK GPDMA1_Channel15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel15_IRQHandler + B GPDMA1_Channel15_IRQHandler + + PUBWEAK HPDMA1_Channel8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel8_IRQHandler + B HPDMA1_Channel8_IRQHandler + + PUBWEAK HPDMA1_Channel9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel9_IRQHandler + B HPDMA1_Channel9_IRQHandler + + PUBWEAK HPDMA1_Channel10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel10_IRQHandler + B HPDMA1_Channel10_IRQHandler + + PUBWEAK HPDMA1_Channel11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel11_IRQHandler + B HPDMA1_Channel11_IRQHandler + + PUBWEAK HPDMA1_Channel12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel12_IRQHandler + B HPDMA1_Channel12_IRQHandler + + PUBWEAK HPDMA1_Channel13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel13_IRQHandler + B HPDMA1_Channel13_IRQHandler + + PUBWEAK HPDMA1_Channel14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel14_IRQHandler + B HPDMA1_Channel14_IRQHandler + + PUBWEAK HPDMA1_Channel15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel15_IRQHandler + B HPDMA1_Channel15_IRQHandler + + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + END diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/startup_stm32h7r7xx.s b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/startup_stm32h7r7xx.s new file mode 100644 index 00000000000..fb0b9171550 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/startup_stm32h7r7xx.s @@ -0,0 +1,1006 @@ +;******************************************************************************** +;* File Name : startup_stm32h7r7xx.s +;* Author : MCD Application Team +;* Description : STM32H7R7xx Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2022 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection + DCD 0 ; Reserved + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD IWDG_IRQHandler ; Internal Watchdog + DCD WWDG_IRQHandler ; Window Watchdog + DCD RCC_IRQHandler ; RCC global interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FLASH_IRQHandler ; FLASH interrupts + DCD RAMECC_IRQHandler ; RAMECC interrupts + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TAMP_IRQHandler ; Tamper and TimeStamp interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD EXTI5_IRQHandler ; EXTI Line5 + DCD EXTI6_IRQHandler ; EXTI Line6 + DCD EXTI7_IRQHandler ; EXTI Line7 + DCD EXTI8_IRQHandler ; EXTI Line8 + DCD EXTI9_IRQHandler ; EXTI Line9 + DCD EXTI10_IRQHandler ; EXTI Line10 + DCD EXTI11_IRQHandler ; EXTI Line11 + DCD EXTI12_IRQHandler ; EXTI Line12 + DCD EXTI13_IRQHandler ; EXTI Line13 + DCD EXTI14_IRQHandler ; EXTI Line14 + DCD EXTI15_IRQHandler ; EXTI Line15 + DCD RTC_IRQHandler ; RTC wakeup and alarm interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PKA_IRQHandler ; PKA + DCD HASH_IRQHandler ; HASH + DCD RNG_IRQHandler ; RNG + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 + DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 + DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 + DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 + DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 + DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 + DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 + DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD TIM9_IRQHandler ; TIM9 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD SPI3_IRQHandler ; SPI3 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD HPDMA1_Channel0_IRQHandler ; HPDMA1 Channel 0 + DCD HPDMA1_Channel1_IRQHandler ; HPDMA1 Channel 1 + DCD HPDMA1_Channel2_IRQHandler ; HPDMA1 Channel 2 + DCD HPDMA1_Channel3_IRQHandler ; HPDMA1 Channel 3 + DCD HPDMA1_Channel4_IRQHandler ; HPDMA1 Channel 4 + DCD HPDMA1_Channel5_IRQHandler ; HPDMA1 Channel 5 + DCD HPDMA1_Channel6_IRQHandler ; HPDMA1 Channel 6 + DCD HPDMA1_Channel7_IRQHandler ; HPDMA1 Channel 7 + DCD SAI1_A_IRQHandler ; Serial Audio Interface 1 block A + DCD SAI1_B_IRQHandler ; Serial Audio Interface 1 block B + DCD SAI2_A_IRQHandler ; Serial Audio Interface 2 block A + DCD SAI2_B_IRQHandler ; Serial Audio Interface 2 block B + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD I3C1_EV_IRQHandler ; I3C1 Event + DCD I3C1_ER_IRQHandler ; I3C1 Error + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD ETH_IRQHandler ; Ethernet + DCD CORDIC_IRQHandler ; CORDIC + DCD GFXTIM_IRQHandler ; GFXTIM + DCD DCMIPP_IRQHandler ; DCMIPP + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD JPEG_IRQHandler ; JPEG + DCD GFXMMU_IRQHandler ; GFXMMU + DCD I3C1_WKUP_IRQHandler ; I3C1 wakeup + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD XSPI1_IRQHandler ; XSPI1 + DCD XSPI2_IRQHandler ; XSPI2 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD LPTIM1_IRQHandler ; LP TIM1 + DCD LPTIM2_IRQHandler ; LP TIM2 + DCD LPTIM3_IRQHandler ; LP TIM3 + DCD LPTIM4_IRQHandler ; LP TIM4 + DCD LPTIM5_IRQHandler ; LP TIM5 + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD MDIOS_IRQHandler ; MDIOS + DCD ADF1_FLT0_IRQHandler ; ADF1 Filter 0 + DCD CRS_IRQHandler ; CRS + DCD UCPD1_IRQHandler ; UCPD1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD PSSI_IRQHandler ; PSSI + DCD LPUART1_IRQHandler ; LP UART1 + DCD WAKEUP_PIN_IRQHandler ; Wake-up pins interrupt + DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8 + DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9 + DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10 + DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11 + DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12 + DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13 + DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14 + DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15 + DCD HPDMA1_Channel8_IRQHandler ; HPDMA1 Channel 8 + DCD HPDMA1_Channel9_IRQHandler ; HPDMA1 Channel 9 + DCD HPDMA1_Channel10_IRQHandler ; HPDMA1 Channel 10 + DCD HPDMA1_Channel11_IRQHandler ; HPDMA1 Channel 11 + DCD HPDMA1_Channel12_IRQHandler ; HPDMA1 Channel 12 + DCD HPDMA1_Channel13_IRQHandler ; HPDMA1 Channel 13 + DCD HPDMA1_Channel14_IRQHandler ; HPDMA1 Channel 14 + DCD HPDMA1_Channel15_IRQHandler ; HPDMA1 Channel 15 + DCD GPU2D_IRQHandler ; GPU2D + DCD GPU2D_ER_IRQHandler ; GPU2D error + DCD ICACHE_IRQHandler ; ICACHE + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt 1 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt 1 +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK DTS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DTS_IRQHandler + B DTS_IRQHandler + + PUBWEAK IWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +IWDG_IRQHandler + B IWDG_IRQHandler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RAMECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RAMECC_IRQHandler + B RAMECC_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK TAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_IRQHandler + B TAMP_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK EXTI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_IRQHandler + B EXTI5_IRQHandler + + PUBWEAK EXTI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI6_IRQHandler + B EXTI6_IRQHandler + + PUBWEAK EXTI7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI7_IRQHandler + B EXTI7_IRQHandler + + PUBWEAK EXTI8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI8_IRQHandler + B EXTI8_IRQHandler + + PUBWEAK EXTI9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_IRQHandler + B EXTI9_IRQHandler + + PUBWEAK EXTI10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_IRQHandler + B EXTI10_IRQHandler + + PUBWEAK EXTI11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI11_IRQHandler + B EXTI11_IRQHandler + + PUBWEAK EXTI12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI12_IRQHandler + B EXTI12_IRQHandler + + PUBWEAK EXTI13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI13_IRQHandler + B EXTI13_IRQHandler + + PUBWEAK EXTI14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI14_IRQHandler + B EXTI14_IRQHandler + + PUBWEAK EXTI15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_IRQHandler + B EXTI15_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK PKA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PKA_IRQHandler + B PKA_IRQHandler + + PUBWEAK HASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_IRQHandler + B HASH_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK GPDMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel0_IRQHandler + B GPDMA1_Channel0_IRQHandler + + PUBWEAK GPDMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel1_IRQHandler + B GPDMA1_Channel1_IRQHandler + + PUBWEAK GPDMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel2_IRQHandler + B GPDMA1_Channel2_IRQHandler + + PUBWEAK GPDMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel3_IRQHandler + B GPDMA1_Channel3_IRQHandler + + PUBWEAK GPDMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel4_IRQHandler + B GPDMA1_Channel4_IRQHandler + + PUBWEAK GPDMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel5_IRQHandler + B GPDMA1_Channel5_IRQHandler + + PUBWEAK GPDMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel6_IRQHandler + B GPDMA1_Channel6_IRQHandler + + PUBWEAK GPDMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel7_IRQHandler + B GPDMA1_Channel7_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK TIM9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM9_IRQHandler + B TIM9_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK HPDMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel0_IRQHandler + B HPDMA1_Channel0_IRQHandler + + PUBWEAK HPDMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel1_IRQHandler + B HPDMA1_Channel1_IRQHandler + + PUBWEAK HPDMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel2_IRQHandler + B HPDMA1_Channel2_IRQHandler + + PUBWEAK HPDMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel3_IRQHandler + B HPDMA1_Channel3_IRQHandler + + PUBWEAK HPDMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel4_IRQHandler + B HPDMA1_Channel4_IRQHandler + + PUBWEAK HPDMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel5_IRQHandler + B HPDMA1_Channel5_IRQHandler + + PUBWEAK HPDMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel6_IRQHandler + B HPDMA1_Channel6_IRQHandler + + PUBWEAK HPDMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel7_IRQHandler + B HPDMA1_Channel7_IRQHandler + + PUBWEAK SAI1_A_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_A_IRQHandler + B SAI1_A_IRQHandler + + PUBWEAK SAI1_B_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_B_IRQHandler + B SAI1_A_IRQHandler + + PUBWEAK SAI2_A_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_A_IRQHandler + B SAI2_A_IRQHandler + + PUBWEAK SAI2_B_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_B_IRQHandler + B SAI2_B_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK I3C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I3C1_EV_IRQHandler + B I3C1_EV_IRQHandler + + PUBWEAK I3C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I3C1_ER_IRQHandler + B I3C1_ER_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + PUBWEAK GFXTIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GFXTIM_IRQHandler + B GFXTIM_IRQHandler + + PUBWEAK DCMIPP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMIPP_IRQHandler + B DCMIPP_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler + B JPEG_IRQHandler + + PUBWEAK GFXMMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GFXMMU_IRQHandler + B GFXMMU_IRQHandler + + PUBWEAK I3C1_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I3C1_WKUP_IRQHandler + B I3C1_WKUP_IRQHandler + + PUBWEAK XSPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +XSPI1_IRQHandler + B XSPI1_IRQHandler + + PUBWEAK XSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +XSPI2_IRQHandler + B XSPI2_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM12_IRQHandler + B TIM12_IRQHandler + + PUBWEAK TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM13_IRQHandler + B TIM13_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler + B LPTIM3_IRQHandler + + PUBWEAK LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler + B LPTIM4_IRQHandler + + PUBWEAK LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler + B MDIOS_IRQHandler + + PUBWEAK ADF1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADF1_FLT0_IRQHandler + B ADF1_FLT0_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK UCPD1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UCPD1_IRQHandler + B UCPD1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK PSSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PSSI_IRQHandler + B PSSI_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler + + PUBWEAK GPDMA1_Channel8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel8_IRQHandler + B GPDMA1_Channel8_IRQHandler + + PUBWEAK GPDMA1_Channel9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel9_IRQHandler + B GPDMA1_Channel9_IRQHandler + + PUBWEAK GPDMA1_Channel10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel10_IRQHandler + B GPDMA1_Channel10_IRQHandler + + PUBWEAK GPDMA1_Channel11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel11_IRQHandler + B GPDMA1_Channel11_IRQHandler + + PUBWEAK GPDMA1_Channel12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel12_IRQHandler + B GPDMA1_Channel12_IRQHandler + + PUBWEAK GPDMA1_Channel13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel13_IRQHandler + B GPDMA1_Channel13_IRQHandler + + PUBWEAK GPDMA1_Channel14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel14_IRQHandler + B GPDMA1_Channel14_IRQHandler + + PUBWEAK GPDMA1_Channel15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel15_IRQHandler + B GPDMA1_Channel15_IRQHandler + + PUBWEAK HPDMA1_Channel8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel8_IRQHandler + B HPDMA1_Channel8_IRQHandler + + PUBWEAK HPDMA1_Channel9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel9_IRQHandler + B HPDMA1_Channel9_IRQHandler + + PUBWEAK HPDMA1_Channel10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel10_IRQHandler + B HPDMA1_Channel10_IRQHandler + + PUBWEAK HPDMA1_Channel11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel11_IRQHandler + B HPDMA1_Channel11_IRQHandler + + PUBWEAK HPDMA1_Channel12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel12_IRQHandler + B HPDMA1_Channel12_IRQHandler + + PUBWEAK HPDMA1_Channel13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel13_IRQHandler + B HPDMA1_Channel13_IRQHandler + + PUBWEAK HPDMA1_Channel14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel14_IRQHandler + B HPDMA1_Channel14_IRQHandler + + PUBWEAK HPDMA1_Channel15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel15_IRQHandler + B HPDMA1_Channel15_IRQHandler + + PUBWEAK GPU2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPU2D_IRQHandler + B GPU2D_IRQHandler + + PUBWEAK GPU2D_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPU2D_ER_IRQHandler + B GPU2D_ER_IRQHandler + + PUBWEAK ICACHE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ICACHE_IRQHandler + B ICACHE_IRQHandler + + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + END diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/startup_stm32h7s3xx.s b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/startup_stm32h7s3xx.s new file mode 100644 index 00000000000..2a23ce2b533 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/startup_stm32h7s3xx.s @@ -0,0 +1,1006 @@ +;******************************************************************************** +;* File Name : startup_stm32h7s3xx.s +;* Author : MCD Application Team +;* Description : STM32H7S3xx Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2022 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection + DCD 0 ; Reserved + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD IWDG_IRQHandler ; Internal Watchdog + DCD WWDG_IRQHandler ; Window Watchdog + DCD RCC_IRQHandler ; RCC global interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FLASH_IRQHandler ; FLASH interrupts + DCD RAMECC_IRQHandler ; RAMECC interrupts + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TAMP_IRQHandler ; Tamper and TimeStamp interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD EXTI5_IRQHandler ; EXTI Line5 + DCD EXTI6_IRQHandler ; EXTI Line6 + DCD EXTI7_IRQHandler ; EXTI Line7 + DCD EXTI8_IRQHandler ; EXTI Line8 + DCD EXTI9_IRQHandler ; EXTI Line9 + DCD EXTI10_IRQHandler ; EXTI Line10 + DCD EXTI11_IRQHandler ; EXTI Line11 + DCD EXTI12_IRQHandler ; EXTI Line12 + DCD EXTI13_IRQHandler ; EXTI Line13 + DCD EXTI14_IRQHandler ; EXTI Line14 + DCD EXTI15_IRQHandler ; EXTI Line15 + DCD RTC_IRQHandler ; RTC wakeup and alarm interrupts through EXTI Line detection + DCD SAES_IRQHandler ; SAES + DCD CRYP_IRQHandler ; CRYP + DCD PKA_IRQHandler ; PKA + DCD HASH_IRQHandler ; HASH + DCD RNG_IRQHandler ; RNG + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 + DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 + DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 + DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 + DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 + DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 + DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 + DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD TIM9_IRQHandler ; TIM9 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD SPI3_IRQHandler ; SPI3 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD HPDMA1_Channel0_IRQHandler ; HPDMA1 Channel 0 + DCD HPDMA1_Channel1_IRQHandler ; HPDMA1 Channel 1 + DCD HPDMA1_Channel2_IRQHandler ; HPDMA1 Channel 2 + DCD HPDMA1_Channel3_IRQHandler ; HPDMA1 Channel 3 + DCD HPDMA1_Channel4_IRQHandler ; HPDMA1 Channel 4 + DCD HPDMA1_Channel5_IRQHandler ; HPDMA1 Channel 5 + DCD HPDMA1_Channel6_IRQHandler ; HPDMA1 Channel 6 + DCD HPDMA1_Channel7_IRQHandler ; HPDMA1 Channel 7 + DCD SAI1_A_IRQHandler ; Serial Audio Interface 1 block A + DCD SAI1_B_IRQHandler ; Serial Audio Interface 1 block B + DCD SAI2_A_IRQHandler ; Serial Audio Interface 2 block A + DCD SAI2_B_IRQHandler ; Serial Audio Interface 2 block B + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD I3C1_EV_IRQHandler ; I3C1 Event + DCD I3C1_ER_IRQHandler ; I3C1 Error + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD ETH_IRQHandler ; Ethernet + DCD CORDIC_IRQHandler ; CORDIC + DCD GFXTIM_IRQHandler ; GFXTIM + DCD DCMIPP_IRQHandler ; DCMIPP + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2D_IRQHandler ; DMA2D + DCD JPEG_IRQHandler ; JPEG + DCD GFXMMU_IRQHandler ; GFXMMU + DCD I3C1_WKUP_IRQHandler ; I3C1 wakeup + DCD MCE1_IRQHandler ; MCE1 + DCD MCE2_IRQHandler ; MCE2 + DCD MCE3_IRQHandler ; MCE3 + DCD XSPI1_IRQHandler ; XSPI1 + DCD XSPI2_IRQHandler ; XSPI2 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD LPTIM1_IRQHandler ; LP TIM1 + DCD LPTIM2_IRQHandler ; LP TIM2 + DCD LPTIM3_IRQHandler ; LP TIM3 + DCD LPTIM4_IRQHandler ; LP TIM4 + DCD LPTIM5_IRQHandler ; LP TIM5 + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD MDIOS_IRQHandler ; MDIOS + DCD ADF1_FLT0_IRQHandler ; ADF1 Filter 0 + DCD CRS_IRQHandler ; CRS + DCD UCPD1_IRQHandler ; UCPD1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD PSSI_IRQHandler ; PSSI + DCD LPUART1_IRQHandler ; LP UART1 + DCD WAKEUP_PIN_IRQHandler ; Wake-up pins interrupt + DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8 + DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9 + DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10 + DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11 + DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12 + DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13 + DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14 + DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15 + DCD HPDMA1_Channel8_IRQHandler ; HPDMA1 Channel 8 + DCD HPDMA1_Channel9_IRQHandler ; HPDMA1 Channel 9 + DCD HPDMA1_Channel10_IRQHandler ; HPDMA1 Channel 10 + DCD HPDMA1_Channel11_IRQHandler ; HPDMA1 Channel 11 + DCD HPDMA1_Channel12_IRQHandler ; HPDMA1 Channel 12 + DCD HPDMA1_Channel13_IRQHandler ; HPDMA1 Channel 13 + DCD HPDMA1_Channel14_IRQHandler ; HPDMA1 Channel 14 + DCD HPDMA1_Channel15_IRQHandler ; HPDMA1 Channel 15 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt 1 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt 1 +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK DTS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DTS_IRQHandler + B DTS_IRQHandler + + PUBWEAK IWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +IWDG_IRQHandler + B IWDG_IRQHandler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RAMECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RAMECC_IRQHandler + B RAMECC_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK TAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_IRQHandler + B TAMP_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK EXTI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_IRQHandler + B EXTI5_IRQHandler + + PUBWEAK EXTI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI6_IRQHandler + B EXTI6_IRQHandler + + PUBWEAK EXTI7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI7_IRQHandler + B EXTI7_IRQHandler + + PUBWEAK EXTI8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI8_IRQHandler + B EXTI8_IRQHandler + + PUBWEAK EXTI9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_IRQHandler + B EXTI9_IRQHandler + + PUBWEAK EXTI10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_IRQHandler + B EXTI10_IRQHandler + + PUBWEAK EXTI11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI11_IRQHandler + B EXTI11_IRQHandler + + PUBWEAK EXTI12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI12_IRQHandler + B EXTI12_IRQHandler + + PUBWEAK EXTI13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI13_IRQHandler + B EXTI13_IRQHandler + + PUBWEAK EXTI14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI14_IRQHandler + B EXTI14_IRQHandler + + PUBWEAK EXTI15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_IRQHandler + B EXTI15_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK SAES_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAES_IRQHandler + B SAES_IRQHandler + + PUBWEAK CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYP_IRQHandler + B CRYP_IRQHandler + + PUBWEAK PKA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PKA_IRQHandler + B PKA_IRQHandler + + PUBWEAK HASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_IRQHandler + B HASH_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK GPDMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel0_IRQHandler + B GPDMA1_Channel0_IRQHandler + + PUBWEAK GPDMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel1_IRQHandler + B GPDMA1_Channel1_IRQHandler + + PUBWEAK GPDMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel2_IRQHandler + B GPDMA1_Channel2_IRQHandler + + PUBWEAK GPDMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel3_IRQHandler + B GPDMA1_Channel3_IRQHandler + + PUBWEAK GPDMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel4_IRQHandler + B GPDMA1_Channel4_IRQHandler + + PUBWEAK GPDMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel5_IRQHandler + B GPDMA1_Channel5_IRQHandler + + PUBWEAK GPDMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel6_IRQHandler + B GPDMA1_Channel6_IRQHandler + + PUBWEAK GPDMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel7_IRQHandler + B GPDMA1_Channel7_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK TIM9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM9_IRQHandler + B TIM9_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK HPDMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel0_IRQHandler + B HPDMA1_Channel0_IRQHandler + + PUBWEAK HPDMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel1_IRQHandler + B HPDMA1_Channel1_IRQHandler + + PUBWEAK HPDMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel2_IRQHandler + B HPDMA1_Channel2_IRQHandler + + PUBWEAK HPDMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel3_IRQHandler + B HPDMA1_Channel3_IRQHandler + + PUBWEAK HPDMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel4_IRQHandler + B HPDMA1_Channel4_IRQHandler + + PUBWEAK HPDMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel5_IRQHandler + B HPDMA1_Channel5_IRQHandler + + PUBWEAK HPDMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel6_IRQHandler + B HPDMA1_Channel6_IRQHandler + + PUBWEAK HPDMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel7_IRQHandler + B HPDMA1_Channel7_IRQHandler + + PUBWEAK SAI1_A_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_A_IRQHandler + B SAI1_A_IRQHandler + + PUBWEAK SAI1_B_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_B_IRQHandler + B SAI1_A_IRQHandler + + PUBWEAK SAI2_A_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_A_IRQHandler + B SAI2_A_IRQHandler + + PUBWEAK SAI2_B_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_B_IRQHandler + B SAI2_B_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK I3C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I3C1_EV_IRQHandler + B I3C1_EV_IRQHandler + + PUBWEAK I3C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I3C1_ER_IRQHandler + B I3C1_ER_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + PUBWEAK GFXTIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GFXTIM_IRQHandler + B GFXTIM_IRQHandler + + PUBWEAK DCMIPP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMIPP_IRQHandler + B DCMIPP_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler + B JPEG_IRQHandler + + PUBWEAK GFXMMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GFXMMU_IRQHandler + B GFXMMU_IRQHandler + + PUBWEAK I3C1_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I3C1_WKUP_IRQHandler + B I3C1_WKUP_IRQHandler + + PUBWEAK MCE1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MCE1_IRQHandler + B MCE1_IRQHandler + + PUBWEAK MCE2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MCE2_IRQHandler + B MCE2_IRQHandler + + PUBWEAK MCE3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MCE3_IRQHandler + B MCE3_IRQHandler + + PUBWEAK XSPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +XSPI1_IRQHandler + B XSPI1_IRQHandler + + PUBWEAK XSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +XSPI2_IRQHandler + B XSPI2_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM12_IRQHandler + B TIM12_IRQHandler + + PUBWEAK TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM13_IRQHandler + B TIM13_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler + B LPTIM3_IRQHandler + + PUBWEAK LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler + B LPTIM4_IRQHandler + + PUBWEAK LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler + B MDIOS_IRQHandler + + PUBWEAK ADF1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADF1_FLT0_IRQHandler + B ADF1_FLT0_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK UCPD1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UCPD1_IRQHandler + B UCPD1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK PSSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PSSI_IRQHandler + B PSSI_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler + + PUBWEAK GPDMA1_Channel8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel8_IRQHandler + B GPDMA1_Channel8_IRQHandler + + PUBWEAK GPDMA1_Channel9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel9_IRQHandler + B GPDMA1_Channel9_IRQHandler + + PUBWEAK GPDMA1_Channel10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel10_IRQHandler + B GPDMA1_Channel10_IRQHandler + + PUBWEAK GPDMA1_Channel11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel11_IRQHandler + B GPDMA1_Channel11_IRQHandler + + PUBWEAK GPDMA1_Channel12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel12_IRQHandler + B GPDMA1_Channel12_IRQHandler + + PUBWEAK GPDMA1_Channel13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel13_IRQHandler + B GPDMA1_Channel13_IRQHandler + + PUBWEAK GPDMA1_Channel14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel14_IRQHandler + B GPDMA1_Channel14_IRQHandler + + PUBWEAK GPDMA1_Channel15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel15_IRQHandler + B GPDMA1_Channel15_IRQHandler + + PUBWEAK HPDMA1_Channel8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel8_IRQHandler + B HPDMA1_Channel8_IRQHandler + + PUBWEAK HPDMA1_Channel9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel9_IRQHandler + B HPDMA1_Channel9_IRQHandler + + PUBWEAK HPDMA1_Channel10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel10_IRQHandler + B HPDMA1_Channel10_IRQHandler + + PUBWEAK HPDMA1_Channel11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel11_IRQHandler + B HPDMA1_Channel11_IRQHandler + + PUBWEAK HPDMA1_Channel12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel12_IRQHandler + B HPDMA1_Channel12_IRQHandler + + PUBWEAK HPDMA1_Channel13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel13_IRQHandler + B HPDMA1_Channel13_IRQHandler + + PUBWEAK HPDMA1_Channel14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel14_IRQHandler + B HPDMA1_Channel14_IRQHandler + + PUBWEAK HPDMA1_Channel15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel15_IRQHandler + B HPDMA1_Channel15_IRQHandler + + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + END diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/startup_stm32h7s7xx.s b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/startup_stm32h7s7xx.s new file mode 100644 index 00000000000..32bad2067fe --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/startup_stm32h7s7xx.s @@ -0,0 +1,1031 @@ +;******************************************************************************** +;* File Name : startup_stm32h7s7xx.s +;* Author : MCD Application Team +;* Description : STM32H7S7xx Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2022 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection + DCD 0 ; Reserved + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD IWDG_IRQHandler ; Internal Watchdog + DCD WWDG_IRQHandler ; Window Watchdog + DCD RCC_IRQHandler ; RCC global interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FLASH_IRQHandler ; FLASH interrupts + DCD RAMECC_IRQHandler ; RAMECC interrupts + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TAMP_IRQHandler ; Tamper and TimeStamp interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD EXTI5_IRQHandler ; EXTI Line5 + DCD EXTI6_IRQHandler ; EXTI Line6 + DCD EXTI7_IRQHandler ; EXTI Line7 + DCD EXTI8_IRQHandler ; EXTI Line8 + DCD EXTI9_IRQHandler ; EXTI Line9 + DCD EXTI10_IRQHandler ; EXTI Line10 + DCD EXTI11_IRQHandler ; EXTI Line11 + DCD EXTI12_IRQHandler ; EXTI Line12 + DCD EXTI13_IRQHandler ; EXTI Line13 + DCD EXTI14_IRQHandler ; EXTI Line14 + DCD EXTI15_IRQHandler ; EXTI Line15 + DCD RTC_IRQHandler ; RTC wakeup and alarm interrupts through EXTI Line detection + DCD SAES_IRQHandler ; SAES + DCD CRYP_IRQHandler ; CRYP + DCD PKA_IRQHandler ; PKA + DCD HASH_IRQHandler ; HASH + DCD RNG_IRQHandler ; RNG + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 + DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 + DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 + DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 + DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 + DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 + DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 + DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD TIM9_IRQHandler ; TIM9 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD SPI3_IRQHandler ; SPI3 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD HPDMA1_Channel0_IRQHandler ; HPDMA1 Channel 0 + DCD HPDMA1_Channel1_IRQHandler ; HPDMA1 Channel 1 + DCD HPDMA1_Channel2_IRQHandler ; HPDMA1 Channel 2 + DCD HPDMA1_Channel3_IRQHandler ; HPDMA1 Channel 3 + DCD HPDMA1_Channel4_IRQHandler ; HPDMA1 Channel 4 + DCD HPDMA1_Channel5_IRQHandler ; HPDMA1 Channel 5 + DCD HPDMA1_Channel6_IRQHandler ; HPDMA1 Channel 6 + DCD HPDMA1_Channel7_IRQHandler ; HPDMA1 Channel 7 + DCD SAI1_A_IRQHandler ; Serial Audio Interface 1 block A + DCD SAI1_B_IRQHandler ; Serial Audio Interface 1 block B + DCD SAI2_A_IRQHandler ; Serial Audio Interface 2 block A + DCD SAI2_B_IRQHandler ; Serial Audio Interface 2 block B + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD I3C1_EV_IRQHandler ; I3C1 Event + DCD I3C1_ER_IRQHandler ; I3C1 Error + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD ETH_IRQHandler ; Ethernet + DCD CORDIC_IRQHandler ; CORDIC + DCD GFXTIM_IRQHandler ; GFXTIM + DCD DCMIPP_IRQHandler ; DCMIPP + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD JPEG_IRQHandler ; JPEG + DCD GFXMMU_IRQHandler ; GFXMMU + DCD I3C1_WKUP_IRQHandler ; I3C1 wakeup + DCD MCE1_IRQHandler ; MCE1 + DCD MCE2_IRQHandler ; MCE2 + DCD MCE3_IRQHandler ; MCE3 + DCD XSPI1_IRQHandler ; XSPI1 + DCD XSPI2_IRQHandler ; XSPI2 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD LPTIM1_IRQHandler ; LP TIM1 + DCD LPTIM2_IRQHandler ; LP TIM2 + DCD LPTIM3_IRQHandler ; LP TIM3 + DCD LPTIM4_IRQHandler ; LP TIM4 + DCD LPTIM5_IRQHandler ; LP TIM5 + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD MDIOS_IRQHandler ; MDIOS + DCD ADF1_FLT0_IRQHandler ; ADF1 Filter 0 + DCD CRS_IRQHandler ; CRS + DCD UCPD1_IRQHandler ; UCPD1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD PSSI_IRQHandler ; PSSI + DCD LPUART1_IRQHandler ; LP UART1 + DCD WAKEUP_PIN_IRQHandler ; Wake-up pins interrupt + DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8 + DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9 + DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10 + DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11 + DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12 + DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13 + DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14 + DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15 + DCD HPDMA1_Channel8_IRQHandler ; HPDMA1 Channel 8 + DCD HPDMA1_Channel9_IRQHandler ; HPDMA1 Channel 9 + DCD HPDMA1_Channel10_IRQHandler ; HPDMA1 Channel 10 + DCD HPDMA1_Channel11_IRQHandler ; HPDMA1 Channel 11 + DCD HPDMA1_Channel12_IRQHandler ; HPDMA1 Channel 12 + DCD HPDMA1_Channel13_IRQHandler ; HPDMA1 Channel 13 + DCD HPDMA1_Channel14_IRQHandler ; HPDMA1 Channel 14 + DCD HPDMA1_Channel15_IRQHandler ; HPDMA1 Channel 15 + DCD GPU2D_IRQHandler ; GPU2D + DCD GPU2D_ER_IRQHandler ; GPU2D error + DCD ICACHE_IRQHandler ; ICACHE + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt 1 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt 1 +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK DTS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DTS_IRQHandler + B DTS_IRQHandler + + PUBWEAK IWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +IWDG_IRQHandler + B IWDG_IRQHandler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RAMECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RAMECC_IRQHandler + B RAMECC_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK TAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_IRQHandler + B TAMP_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK EXTI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_IRQHandler + B EXTI5_IRQHandler + + PUBWEAK EXTI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI6_IRQHandler + B EXTI6_IRQHandler + + PUBWEAK EXTI7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI7_IRQHandler + B EXTI7_IRQHandler + + PUBWEAK EXTI8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI8_IRQHandler + B EXTI8_IRQHandler + + PUBWEAK EXTI9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_IRQHandler + B EXTI9_IRQHandler + + PUBWEAK EXTI10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_IRQHandler + B EXTI10_IRQHandler + + PUBWEAK EXTI11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI11_IRQHandler + B EXTI11_IRQHandler + + PUBWEAK EXTI12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI12_IRQHandler + B EXTI12_IRQHandler + + PUBWEAK EXTI13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI13_IRQHandler + B EXTI13_IRQHandler + + PUBWEAK EXTI14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI14_IRQHandler + B EXTI14_IRQHandler + + PUBWEAK EXTI15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_IRQHandler + B EXTI15_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK SAES_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAES_IRQHandler + B SAES_IRQHandler + + PUBWEAK CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYP_IRQHandler + B CRYP_IRQHandler + + PUBWEAK PKA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PKA_IRQHandler + B PKA_IRQHandler + + PUBWEAK HASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_IRQHandler + B HASH_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK GPDMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel0_IRQHandler + B GPDMA1_Channel0_IRQHandler + + PUBWEAK GPDMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel1_IRQHandler + B GPDMA1_Channel1_IRQHandler + + PUBWEAK GPDMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel2_IRQHandler + B GPDMA1_Channel2_IRQHandler + + PUBWEAK GPDMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel3_IRQHandler + B GPDMA1_Channel3_IRQHandler + + PUBWEAK GPDMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel4_IRQHandler + B GPDMA1_Channel4_IRQHandler + + PUBWEAK GPDMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel5_IRQHandler + B GPDMA1_Channel5_IRQHandler + + PUBWEAK GPDMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel6_IRQHandler + B GPDMA1_Channel6_IRQHandler + + PUBWEAK GPDMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel7_IRQHandler + B GPDMA1_Channel7_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK TIM9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM9_IRQHandler + B TIM9_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK HPDMA1_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel0_IRQHandler + B HPDMA1_Channel0_IRQHandler + + PUBWEAK HPDMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel1_IRQHandler + B HPDMA1_Channel1_IRQHandler + + PUBWEAK HPDMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel2_IRQHandler + B HPDMA1_Channel2_IRQHandler + + PUBWEAK HPDMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel3_IRQHandler + B HPDMA1_Channel3_IRQHandler + + PUBWEAK HPDMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel4_IRQHandler + B HPDMA1_Channel4_IRQHandler + + PUBWEAK HPDMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel5_IRQHandler + B HPDMA1_Channel5_IRQHandler + + PUBWEAK HPDMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel6_IRQHandler + B HPDMA1_Channel6_IRQHandler + + PUBWEAK HPDMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel7_IRQHandler + B HPDMA1_Channel7_IRQHandler + + PUBWEAK SAI1_A_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_A_IRQHandler + B SAI1_A_IRQHandler + + PUBWEAK SAI1_B_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_B_IRQHandler + B SAI1_A_IRQHandler + + PUBWEAK SAI2_A_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_A_IRQHandler + B SAI2_A_IRQHandler + + PUBWEAK SAI2_B_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_B_IRQHandler + B SAI2_B_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK I3C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I3C1_EV_IRQHandler + B I3C1_EV_IRQHandler + + PUBWEAK I3C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I3C1_ER_IRQHandler + B I3C1_ER_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + PUBWEAK GFXTIM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GFXTIM_IRQHandler + B GFXTIM_IRQHandler + + PUBWEAK DCMIPP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMIPP_IRQHandler + B DCMIPP_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler + B JPEG_IRQHandler + + PUBWEAK GFXMMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GFXMMU_IRQHandler + B GFXMMU_IRQHandler + + PUBWEAK I3C1_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I3C1_WKUP_IRQHandler + B I3C1_WKUP_IRQHandler + + PUBWEAK MCE1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MCE1_IRQHandler + B MCE1_IRQHandler + + PUBWEAK MCE2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MCE2_IRQHandler + B MCE2_IRQHandler + + PUBWEAK MCE3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MCE3_IRQHandler + B MCE3_IRQHandler + + PUBWEAK XSPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +XSPI1_IRQHandler + B XSPI1_IRQHandler + + PUBWEAK XSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +XSPI2_IRQHandler + B XSPI2_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM12_IRQHandler + B TIM12_IRQHandler + + PUBWEAK TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM13_IRQHandler + B TIM13_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler + B LPTIM3_IRQHandler + + PUBWEAK LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler + B LPTIM4_IRQHandler + + PUBWEAK LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler + B MDIOS_IRQHandler + + PUBWEAK ADF1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADF1_FLT0_IRQHandler + B ADF1_FLT0_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK UCPD1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UCPD1_IRQHandler + B UCPD1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK PSSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PSSI_IRQHandler + B PSSI_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler + + PUBWEAK GPDMA1_Channel8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel8_IRQHandler + B GPDMA1_Channel8_IRQHandler + + PUBWEAK GPDMA1_Channel9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel9_IRQHandler + B GPDMA1_Channel9_IRQHandler + + PUBWEAK GPDMA1_Channel10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel10_IRQHandler + B GPDMA1_Channel10_IRQHandler + + PUBWEAK GPDMA1_Channel11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel11_IRQHandler + B GPDMA1_Channel11_IRQHandler + + PUBWEAK GPDMA1_Channel12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel12_IRQHandler + B GPDMA1_Channel12_IRQHandler + + PUBWEAK GPDMA1_Channel13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel13_IRQHandler + B GPDMA1_Channel13_IRQHandler + + PUBWEAK GPDMA1_Channel14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel14_IRQHandler + B GPDMA1_Channel14_IRQHandler + + PUBWEAK GPDMA1_Channel15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPDMA1_Channel15_IRQHandler + B GPDMA1_Channel15_IRQHandler + + PUBWEAK HPDMA1_Channel8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel8_IRQHandler + B HPDMA1_Channel8_IRQHandler + + PUBWEAK HPDMA1_Channel9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel9_IRQHandler + B HPDMA1_Channel9_IRQHandler + + PUBWEAK HPDMA1_Channel10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel10_IRQHandler + B HPDMA1_Channel10_IRQHandler + + PUBWEAK HPDMA1_Channel11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel11_IRQHandler + B HPDMA1_Channel11_IRQHandler + + PUBWEAK HPDMA1_Channel12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel12_IRQHandler + B HPDMA1_Channel12_IRQHandler + + PUBWEAK HPDMA1_Channel13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel13_IRQHandler + B HPDMA1_Channel13_IRQHandler + + PUBWEAK HPDMA1_Channel14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel14_IRQHandler + B HPDMA1_Channel14_IRQHandler + + PUBWEAK HPDMA1_Channel15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HPDMA1_Channel15_IRQHandler + B HPDMA1_Channel15_IRQHandler + + PUBWEAK GPU2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPU2D_IRQHandler + B GPU2D_IRQHandler + + PUBWEAK GPU2D_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPU2D_ER_IRQHandler + B GPU2D_ER_IRQHandler + + PUBWEAK ICACHE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ICACHE_IRQHandler + B ICACHE_IRQHandler + + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + END diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/system_stm32h7rsxx.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/system_stm32h7rsxx.c new file mode 100644 index 00000000000..97d821bcb7c --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/system_stm32h7rsxx.c @@ -0,0 +1,285 @@ +/** + ****************************************************************************** + * @file system_stm32h7rsxx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h7rsxx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (sys_cpu_ck), it can + * be used by the user application to setup the + * SysTick timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (64 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32h7rsxx.s" file, to + * optionally configure the system clock before to branch to main program. + * + *============================================================================= + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32H7RSxx_System + * @{ + */ + +/** @addtogroup STM32H7RSxx_System_Private_Includes + * @{ + */ + +#include "stm32h7rsxx.h" +#include + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 24000000UL /*!< Value of the High-Speed External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 64000000UL /*!< Value of the High-Speed Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE 4000000UL /*!< Value of the Low-power Internal oscillator in Hz */ +#endif /* CSI_VALUE */ + +/*!< The VTOR location information is based on information from the linker with a dependency + on the IDE, the cortex register is updated using the INTVECT_START. +*/ +#if defined(__ICCARM__) +extern uint32_t __vector_table; +#define INTVECT_START ((uint32_t)& __vector_table) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void * __Vectors; +#define INTVECT_START ((uint32_t) & __Vectors) +#elif defined(__GNUC__) +extern void * g_pfnVectors; +#define INTVECT_START ((uint32_t)& g_pfnVectors) +#endif /* __ICCARM__*/ + + + +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in two ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the first function listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = HSI_VALUE; + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @retval None + */ + +void SystemInit(void) +{ + /* Configure the Vector Table location -------------------------------------*/ + SCB->VTOR = INTVECT_START; + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to RCC registers values. + * The SystemCoreClock variable contains the core clock (sys_cpu_ck), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSI_VALUE(*) + * or CSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) CSI_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value + * 24 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t sysclk, hsivalue, pllsource, pllm, pllp, core_presc; + float_t pllfracn, pllvco; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x00: /* HSI used as system clock source (default after reset) */ + sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos)); + break; + + case 0x08: /* CSI used as system clock source */ + sysclk = CSI_VALUE; + break; + + case 0x10: /* HSE used as system clock source */ + sysclk = HSE_VALUE; + break; + + case 0x18: /* PLL1 used as system clock source */ + /* PLL1_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL1_VCO / PLL1R + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) ; + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) != 0U) + { + pllfracn = (float_t)(uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN)>> RCC_PLL1FRACR_FRACN_Pos)); + } + else + { + pllfracn = (float_t)0U; + } + + if (pllm != 0U) + { + switch (pllsource) + { + case 0x02: /* HSE used as PLL1 clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 ); + break; + + case 0x01: /* CSI used as PLL1 clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 ); + break; + + case 0x00: /* HSI used as PLL1 clock source */ + default: + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos)); + pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 ); + break; + } + pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U ) ; + sysclk = (uint32_t)(float_t)(pllvco/(float_t)pllp); + } + else + { + sysclk = 0U; + } + break; + + default: /* Unexpected, default to HSI used as system clock source (default after reset) */ + sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos)); + break; + } + + /* system clock frequency : CM7 CPU frequency */ + core_presc = (RCC->CDCFGR & RCC_CDCFGR_CPRE); + if (core_presc >= 8U) + { + SystemCoreClock = (sysclk >> (core_presc - RCC_CDCFGR_CPRE_3 + 1U)); + } + else + { + SystemCoreClock = sysclk; + } +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/SConscript b/bsp/stm32/libraries/STM32H7RSxx_HAL/SConscript new file mode 100644 index 00000000000..695d52521cb --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/SConscript @@ -0,0 +1,47 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. + +src = Split(''' +CMSIS/Device/ST/STM32H7RSxx/Source/Templates/system_stm32h7rsxx.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cec.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cortex.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_crc.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_crc_ex.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cryp.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cryp_ex.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma_ex.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pwr.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pwr_ex.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rcc.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rcc_ex.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rng.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sram.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gpio.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_adc.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_adc_ex.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_xspi.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_flash.c +STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_flash_ex.c +''') + +if GetDepend(['RT_USING_SERIAL']) or GetDepend(['RT_USING_NANO', 'RT_USING_CONSOLE']): + src += ['STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_uart.c'] + src += ['STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_usart.c'] + src += ['STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_uart_ex.c'] + + +path = [cwd + '/STM32H7RSxx_HAL_Driver/Inc', + cwd + '/CMSIS/Device/ST/STM32H7RSxx/Include'] + +CPPDEFINES = ['USE_HAL_DRIVER'] +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h new file mode 100644 index 00000000000..f76653ed7bd --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,4354 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32H7) || defined(STM32MP1) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#endif /* STM32H7 || STM32MP1 */ +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32H5) || defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ +#endif +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) || defined(STM32C0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ + +#if defined(STM32L1) +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) || defined(STM32H5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP + +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H5) || defined(STM32H7RS) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 || STM32H7RS */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA || STM32H7RS */ + +#if defined(STM32F7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 */ + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 || STM32L0 */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP + +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP + +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +#if defined(STM32U5) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ +/** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA || STM32H7RS */ + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || \ + defined(STM32U0) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32_assert_template.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32_assert_template.h new file mode 100644 index 00000000000..07e99b9fe52 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32_assert_template.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file stm32_assert.h + * @author MCD Application Team + * @brief STM32 assert template file. + * This file should be copied to the application folder and renamed + * to stm32_assert.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_ASSERT_H +#define STM32_ASSERT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_ASSERT_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal.h new file mode 100644 index 00000000000..68393d6d5c3 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal.h @@ -0,0 +1,767 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_H +#define STM32H7RSxx_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_conf.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +/** + * @brief HAL Tick frequency + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup REV_ID device revision ID + * @{ + */ +#define REV_ID_A 0x1003U /*!< STM32H7Rx/Sx rev.A */ +/** + * @} + */ + +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ +/** + * @brief STM32H7RSxx HAL Driver version number + */ +#define STM32H7RSXX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define STM32H7RSXX_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ +#define STM32H7RSXX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define STM32H7RSXX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define STM32H7RSXX_HAL_VERSION ((STM32H7RSXX_HAL_VERSION_MAIN << 24U)\ + |(STM32H7RSXX_HAL_VERSION_SUB1 << 16U)\ + |(STM32H7RSXX_HAL_VERSION_SUB2 << 8U )\ + |(STM32H7RSXX_HAL_VERSION_RC)) +/** + * @} + */ + +/** @defgroup SBS_Exported_Constants SBS Exported Constants + * @{ + */ + +/** @defgroup SBS_HDPL_Value HDPL Value + * @{ + */ +#define SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */ +#define SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 1 */ +#define SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 2 */ +#define SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 3 */ +/** + * @} + */ + +/** @defgroup SBS_Timer_Break_Inputs Timer Break Inputs + * @{ + */ +#define SBS_TIMER_BREAK_LOCK_PVD SBS_BKLOCKR_PVD_BL /*!< PVD break lock */ +#define SBS_TIMER_BREAK_LOCK_FLASH SBS_BKLOCKR_FLASHECC_BL /*!< FLASH ECC error break lock */ +#define SBS_TIMER_BREAK_LOCK_CORE SBS_BKLOCKR_CM7LCKUP_BL /*!< Cortex-M7 lockup break lock */ +#define SBS_TIMER_BREAK_LOCK_BKPRAM SBS_BKLOCKR_BKRAMECC_BL /*!< Backup RAM ECC error break lock */ +#define SBS_TIMER_BREAK_LOCK_DTCM SBS_BKLOCKR_DTCMECC_BL /*!< DTCM ECC error break lock */ +#define SBS_TIMER_BREAK_LOCK_ITCM SBS_BKLOCKR_ITCMECC_BL /*!< ITCM ECC error break lock */ +#define SBS_TIMER_BREAK_LOCK_AXISRAM3 SBS_BKLOCKR_ARAM3ECC_BL /*!< AXISRAM3 ECC error break lock */ +#define SBS_TIMER_BREAK_LOCK_AXISRAM1 SBS_BKLOCKR_ARAM1ECC_BL /*!< AXISRAM1 ECC error break lock */ +/** + * @} + */ + +/** @defgroup SBS_FPU_Interrupts FPU Interrupts + * @{ + */ +#define SBS_IT_FPU_IOC SBS_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ +#define SBS_IT_FPU_DZC SBS_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ +#define SBS_IT_FPU_UFC SBS_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ +#define SBS_IT_FPU_OFC SBS_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ +#define SBS_IT_FPU_IDC SBS_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ +#define SBS_IT_FPU_IXC SBS_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ +/** + * @} + */ + +/** @defgroup SBS_Compensation_Cell_Selection Compensation Cell Selection + * @{ + */ +#define SBS_IO_ANALOG_CELL SBS_CCCSR_COMP_EN /*!< Compensation cell for the I/O analog switches */ +#define SBS_IO_XSPI1_CELL SBS_CCCSR_XSPI1_COMP_EN /*!< Compensation cell for the I/O of the XSPI1 */ +#define SBS_IO_XSPI2_CELL SBS_CCCSR_XSPI2_COMP_EN /*!< Compensation cell for the I/O of the XSPI2 */ +/** + * @} + */ + +/** @defgroup SBS_Compensation_Cell_Ready_Selection Compensation Cell Ready Selection + * @{ + */ +#define SBS_IO_ANALOG_CELL_READY SBS_CCCSR_COMP_RDY /*!< Ready flag of compensation cell for the I/O analog switches */ +#define SBS_IO_XSPI1_CELL_READY SBS_CCCSR_XSPI1_COMP_RDY /*!< Ready flag of compensation cell for the I/O of the XSPI1 */ +#define SBS_IO_XSPI2_CELL_READY SBS_CCCSR_XSPI2_COMP_RDY /*!< Ready flag of compensation cell for the I/O of the XSPI2 */ +/** + * @} + */ + +/** @defgroup SBS_IO_Compensation_Code_Config IO Compensation Code config + * @{ + */ +#define SBS_IO_CELL_CODE 0UL /*!< Code from the cell */ +#define SBS_IO_REGISTER_CODE 1UL /*!< Code from the values in the cell code register */ +/** + * @} + */ + +/** @defgroup SBS_IO_HSLV_Selection IO High Speed at Low Voltage Selection + * @{ + */ +#define SBS_IO_ANALOG_HSLV SBS_CCCSR_IOHSLV /*!< High speed at low voltage for the I/O analog switches */ +#define SBS_IO_XSPI1_HSLV SBS_CCCSR_XSPI1_IOHSLV /*!< High speed at low voltage for the I/O of the XSPI1 */ +#define SBS_IO_XSPI2_HSLV SBS_CCCSR_XSPI2_IOHSLV /*!< High speed at low voltage for the I/O of the XSPI2 */ +/** + * @} + */ + +/** @defgroup SBS_Ethernet_PHY_Config Ethernet PHY config + * @{ + */ +#define SBS_ETHERNET_PHY_GMII_OR_MII 0U /*!< GMII or MII */ +#define SBS_ETHERNET_PHY_RMII SBS_PMCR_ETH_PHYSEL_2 /*!< RMII */ +/** + * @} + */ + +/** @defgroup SBS_ECC_AXISRAM_WS_Config ECC AXISRAMs Wait State when ECC=0 config + * @{ + */ +#define SBS_AXISRAM_WS_0 0U /*!< 0 Wait state */ +#define SBS_AXISRAM_WS_1 SBS_PMCR_AXISRAM_WS /*!< 1 Wait state */ +/** + * @} + */ + +/** @defgroup SBS_EXTI_Port EXTI Port configuration + * @{ + */ +#define SBS_EXTI_PIN_PORTA 0x00UL /*!< Port A pin input of EXTI event detection */ +#define SBS_EXTI_PIN_PORTB 0x01UL /*!< Port B pin input of EXTI event detection */ +#define SBS_EXTI_PIN_PORTC 0x02UL /*!< Port C pin input of EXTI event detection */ +#define SBS_EXTI_PIN_PORTD 0x03UL /*!< Port D pin input of EXTI event detection */ +#define SBS_EXTI_PIN_PORTE 0x04UL /*!< Port E pin input of EXTI event detection */ +#define SBS_EXTI_PIN_PORTF 0x05UL /*!< Port F pin input of EXTI event detection */ +#define SBS_EXTI_PIN_PORTG 0x06UL /*!< Port G pin input of EXTI event detection */ +#define SBS_EXTI_PIN_PORTH 0x07UL /*!< Port H pin input of EXTI event detection */ +#define SBS_EXTI_PIN_PORTM 0x0CUL /*!< Port M pin input of EXTI event detection */ +#define SBS_EXTI_PIN_PORTN 0x0DUL /*!< Port N pin input of EXTI event detection */ +#define SBS_EXTI_PIN_PORTO 0x0EUL /*!< Port O pin input of EXTI event detection */ +#define SBS_EXTI_PIN_PORTP 0x0FUL /*!< Port P pin input of EXTI event detection */ +/** + * @} + */ + +/** @defgroup AXIM_Exported_Constants AXIM Exported Constants + * @{ + */ + +/** @defgroup AXIM_ASIB_READ_ISSUING_CAP AXIM ASIBs Read Issuing Capability + * @{ + */ +#define AXIM_ASIB_READ_ISS_NORMAL 0U /*!< Normal issuing capability */ +#define AXIM_ASIB_READ_ISS_FORCE_TO_1 AXIM_ASIB_FNMOD_READ_ISS /*!< Force issuing capability to 1 */ +/** + * @} + */ + +/** @defgroup AXIM_ASIB_WRITE_ISSUING_CAP AXIM ASIBs Write Issuing Capability + * @{ + */ +#define AXIM_ASIB_WRITE_ISS_NORMAL 0U /*!< Normal issuing capability */ +#define AXIM_ASIB_WRITE_ISS_FORCE_TO_1 AXIM_ASIB_FNMOD_WRITE_ISS /*!< Force issuing capability to 1 */ +/** + * @} + */ + +/** @defgroup AXIM_AMIB_READ_ISSUING_CAP AXIM AMIBs Read Issuing Capability + * @{ + */ +#define AXIM_AMIB_READ_ISS_NORMAL 0U /*!< Normal issuing capability */ +#define AXIM_AMIB_READ_ISS_FORCE_TO_1 AXIM_AMIB_FNMOD_READ_ISS /*!< Force issuing capability to 1 */ +/** + * @} + */ + +/** @defgroup AXIM_AMIB_WRITE_ISSUING_CAP AXIM AMIBs Write Issuing Capability + * @{ + */ +#define AXIM_AMIB_WRITE_ISS_NORMAL 0U /*!< Normal issuing capability */ +#define AXIM_AMIB_WRITE_ISS_FORCE_TO_1 AXIM_AMIB_FNMOD_WRITE_ISS /*!< Force issuing capability to 1 */ +/** + * @} + */ + +/** @defgroup AXIM_AMIB_READ_ISSUING_BM_CAP AXIM AMIBs Read Issuing Bus Matrix Capability + * @{ + */ +#define AXIM_AMIB_READ_ISS_BM_NORMAL 0U /*!< Normal issuing capability */ +#define AXIM_AMIB_READ_ISS_BM_FORCE_TO_1 AXIM_AMIB_FNMOD_READ_ISS /*!< Force issuing capability to 1 */ +/** + * @} + */ + +/** @defgroup AXIM_AMIB_WRITE_ISSUING_BM_CAP AXIM AMIBs Write Issuing Bus Matrix Capability + * @{ + */ +#define AXIM_AMIB_WRITE_ISS_BM_NORMAL 0U /*!< Normal issuing capability */ +#define AXIM_AMIB_WRITE_ISS_BM_FORCE_TO_1 AXIM_AMIB_FNMOD_WRITE_ISS /*!< Force issuing capability to 1 */ +/** + * @} + */ +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros + * @{ + */ + +/** @brief Freeze/Unfreeze Peripherals in Debug mode + */ +#define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_0) +#define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_0) + +#define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_1) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_1) + +#define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_2) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_2) + +#define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_3) +#define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_3) + +#define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_4) +#define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_4) + +#define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_5) +#define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_5) + +#define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_6) +#define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_6) + +#define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_7) +#define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_7) + +#define __HAL_DBGMCU_FREEZE_GPDMA8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_8) +#define __HAL_DBGMCU_UNFREEZE_GPDMA8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_8) + +#define __HAL_DBGMCU_FREEZE_GPDMA9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_9) +#define __HAL_DBGMCU_UNFREEZE_GPDMA9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_9) + +#define __HAL_DBGMCU_FREEZE_GPDMA10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_10) +#define __HAL_DBGMCU_UNFREEZE_GPDMA10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_10) + +#define __HAL_DBGMCU_FREEZE_GPDMA11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_11) +#define __HAL_DBGMCU_UNFREEZE_GPDMA11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_11) + +#define __HAL_DBGMCU_FREEZE_GPDMA12() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_12) +#define __HAL_DBGMCU_UNFREEZE_GPDMA12() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_12) + +#define __HAL_DBGMCU_FREEZE_GPDMA13() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_13) +#define __HAL_DBGMCU_UNFREEZE_GPDMA13() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_13) + +#define __HAL_DBGMCU_FREEZE_GPDMA14() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_14) +#define __HAL_DBGMCU_UNFREEZE_GPDMA14() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_14) + +#define __HAL_DBGMCU_FREEZE_GPDMA15() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_15) +#define __HAL_DBGMCU_UNFREEZE_GPDMA15() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_15) + +#define __HAL_DBGMCU_FREEZE_HPDMA0() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_0) +#define __HAL_DBGMCU_UNFREEZE_HPDMA0() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_0) + +#define __HAL_DBGMCU_FREEZE_HPDMA1() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_1) +#define __HAL_DBGMCU_UNFREEZE_HPDMA1() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_1) + +#define __HAL_DBGMCU_FREEZE_HPDMA2() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_2) +#define __HAL_DBGMCU_UNFREEZE_HPDMA2() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_2) + +#define __HAL_DBGMCU_FREEZE_HPDMA3() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_3) +#define __HAL_DBGMCU_UNFREEZE_HPDMA3() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_3) + +#define __HAL_DBGMCU_FREEZE_HPDMA4() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_4) +#define __HAL_DBGMCU_UNFREEZE_HPDMA4() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_4) + +#define __HAL_DBGMCU_FREEZE_HPDMA5() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_5) +#define __HAL_DBGMCU_UNFREEZE_HPDMA5() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_5) + +#define __HAL_DBGMCU_FREEZE_HPDMA6() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_6) +#define __HAL_DBGMCU_UNFREEZE_HPDMA6() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_6) + +#define __HAL_DBGMCU_FREEZE_HPDMA7() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_7) +#define __HAL_DBGMCU_UNFREEZE_HPDMA7() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_7) + +#define __HAL_DBGMCU_FREEZE_HPDMA8() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_8) +#define __HAL_DBGMCU_UNFREEZE_HPDMA8() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_8) + +#define __HAL_DBGMCU_FREEZE_HPDMA9() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_9) +#define __HAL_DBGMCU_UNFREEZE_HPDMA9() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_9) + +#define __HAL_DBGMCU_FREEZE_HPDMA10() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_10) +#define __HAL_DBGMCU_UNFREEZE_HPDMA10() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_10) + +#define __HAL_DBGMCU_FREEZE_HPDMA11() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_11) +#define __HAL_DBGMCU_UNFREEZE_HPDMA11() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_11) + +#define __HAL_DBGMCU_FREEZE_HPDMA12() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_12) +#define __HAL_DBGMCU_UNFREEZE_HPDMA12() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_12) + +#define __HAL_DBGMCU_FREEZE_HPDMA13() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_13) +#define __HAL_DBGMCU_UNFREEZE_HPDMA13() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_13) + +#define __HAL_DBGMCU_FREEZE_HPDMA14() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_14) +#define __HAL_DBGMCU_UNFREEZE_HPDMA14() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_14) + +#define __HAL_DBGMCU_FREEZE_HPDMA15() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_15) +#define __HAL_DBGMCU_UNFREEZE_HPDMA15() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_15) + +#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C1) +#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C1) + +#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C2) +#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C2) + +#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C3) +#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C3) + +#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM2) +#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM2) + +#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM3) +#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM3) + +#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM4) +#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM4) + +#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM5) +#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM5) + +#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM6) +#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM6) + +#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM7) +#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM7) + +#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM9) +#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM9) + +#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM12) +#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM12) + +#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM13) +#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM13) + +#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM14) +#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM14) + +#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM1) +#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM1) + +#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM15) +#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM15) + +#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM16) +#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM16) + +#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM17) +#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM17) + +#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_LPTIM1) +#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_LPTIM1) + +#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM2) +#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM2) + +#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM3) +#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM3) + +#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM4) +#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM4) + +#define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM5) +#define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM5) + +#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_IWDG) +#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_IWDG) + +#define __HAL_DBGMCU_FREEZE_PWM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_PWM1) +#define __HAL_DBGMCU_UNFREEZE_PWM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_PWM1) + +#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_RTC) +#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_RTC) + +#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_WWDG) +#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_WWDG) + +/** + * @} + */ + +/** @defgroup SBS_Exported_Macros SBS Exported Macros + * @{ + */ + +/** @brief Floating Point Unit interrupt enable/disable macros + * @param __INTERRUPT__ This parameter can be a value of @ref SBS_FPU_Interrupts + */ +#define __HAL_SBS_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do { \ + assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__))); \ + SET_BIT(SBS->FPUIMR, (__INTERRUPT__)); \ + } while(0) + +#define __HAL_SBS_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do { \ + assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__))); \ + CLEAR_BIT(SBS->FPUIMR, (__INTERRUPT__)); \ + } while(0) + +/** @brief Check SBS Memories Erase Status Flags. + * @retval The state of memory erase. + */ +#define __HAL_SBS_GET_MEMORIES_ERASE_STATUS() ((SBS->MESR) & (SBS_MESR_MEF)) + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup VREFBUF_VoltageScale VREFBUF Voltage Scale + * @{ + */ +#define VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 2 (VREF_OUT3) */ +#define VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 3 (VREF_OUT4) */ + + +#define IS_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == VREFBUF_VOLTAGE_SCALE0) || \ + ((__SCALE__) == VREFBUF_VOLTAGE_SCALE1) || \ + ((__SCALE__) == VREFBUF_VOLTAGE_SCALE2) || \ + ((__SCALE__) == VREFBUF_VOLTAGE_SCALE3)) + + +/** + * @} + */ + +/** @defgroup VREFBUF_HighImpedance VREFBUF High Impedance + * @{ + */ +#define VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ +#define VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ + +#define IS_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ + ((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_ENABLE)) + +#define IS_VREFBUF_TRIMMING(__VALUE__) ((__VALUE__) <= VREFBUF_CCR_TRIM) + +/** + * @} + */ + +/** @addtogroup SBS_Private_Macros + * @{ + */ +#define IS_SBS_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SBS_IT_FPU_IOC) == SBS_IT_FPU_IOC) || \ + (((__INTERRUPT__) & SBS_IT_FPU_DZC) == SBS_IT_FPU_DZC) || \ + (((__INTERRUPT__) & SBS_IT_FPU_UFC) == SBS_IT_FPU_UFC) || \ + (((__INTERRUPT__) & SBS_IT_FPU_OFC) == SBS_IT_FPU_OFC) || \ + (((__INTERRUPT__) & SBS_IT_FPU_IDC) == SBS_IT_FPU_IDC) || \ + (((__INTERRUPT__) & SBS_IT_FPU_IXC) == SBS_IT_FPU_IXC)) + +#define IS_SBS_HDPL(__LEVEL__) (((__LEVEL__) == SBS_HDPL_VALUE_0) || \ + ((__LEVEL__) == SBS_HDPL_VALUE_1) || \ + ((__LEVEL__) == SBS_HDPL_VALUE_2) || \ + ((__LEVEL__) == SBS_HDPL_VALUE_3)) + +#define IS_SBS_COMPENSATION_CELL(__CELL__) (((__CELL__) == SBS_IO_ANALOG_CELL) || \ + ((__CELL__) == SBS_IO_XSPI1_CELL) || \ + ((__CELL__) == SBS_IO_XSPI2_CELL)) + +#define IS_SBS_COMPENSATION_CELL_READY(__CELL__) (((__CELL__) == SBS_IO_ANALOG_CELL_READY) || \ + ((__CELL__) == SBS_IO_XSPI1_CELL_READY) || \ + ((__CELL__) == SBS_IO_XSPI2_CELL_READY)) + +#define IS_SBS_IOHSLV(__HSLV__) (((__HSLV__) == SBS_IO_ANALOG_HSLV) || \ + ((__HSLV__) == SBS_IO_XSPI1_HSLV) || \ + ((__HSLV__) == SBS_IO_XSPI2_HSLV)) + +#define IS_SBS_EXTI_INPUT(__INPUT__) ((__INPUT__) < 16U) + +#define IS_SBS_EXTI_PIN(__PIN__) (((__PIN__) == SBS_EXTI_PIN_PORTA) || \ + ((__PIN__) == SBS_EXTI_PIN_PORTB) || \ + ((__PIN__) == SBS_EXTI_PIN_PORTC) || \ + ((__PIN__) == SBS_EXTI_PIN_PORTD) || \ + ((__PIN__) == SBS_EXTI_PIN_PORTE) || \ + ((__PIN__) == SBS_EXTI_PIN_PORTF) || \ + ((__PIN__) == SBS_EXTI_PIN_PORTG) || \ + ((__PIN__) == SBS_EXTI_PIN_PORTH) || \ + ((__PIN__) == SBS_EXTI_PIN_PORTM) || \ + ((__PIN__) == SBS_EXTI_PIN_PORTN) || \ + ((__PIN__) == SBS_EXTI_PIN_PORTO) || \ + ((__PIN__) == SBS_EXTI_PIN_PORTP)) +/** + * @} + */ + +/** @addtogroup AXIM_Private_Macros + * @{ + */ +#define IS_AXIM_ASIB_READ_ISS(__ISS__) (((__ISS__) == AXIM_ASIB_READ_ISS_NORMAL) || \ + ((__ISS__) == AXIM_ASIB_READ_ISS_FORCE_TO_1)) + +#define IS_AXIM_ASIB_WRITE_ISS(__ISS__) (((__ISS__) == AXIM_ASIB_WRITE_ISS_NORMAL) || \ + ((__ISS__) == AXIM_ASIB_WRITE_ISS_FORCE_TO_1)) + +#define IS_AXIM_QOS(__QOS__) ((__QOS__) <= AXIM_ASIB_READQOS_AR_QOS) + +#define IS_AXIM_AMIB_READ_ISS(__ISS__) (((__ISS__) == AXIM_AMIB_READ_ISS_NORMAL) || \ + ((__ISS__) == AXIM_AMIB_READ_ISS_FORCE_TO_1)) + +#define IS_AXIM_AMIB_WRITE_ISS(__ISS__) (((__ISS__) == AXIM_AMIB_WRITE_ISS_NORMAL) || \ + ((__ISS__) == AXIM_AMIB_WRITE_ISS_FORCE_TO_1)) + +#define IS_AXIM_AMIB_READ_ISS_BM(__ISS__) (((__ISS__) == AXIM_AMIB_READ_ISS_NORMAL) || \ + ((__ISS__) == AXIM_AMIB_READ_ISS_FORCE_TO_1)) + +#define IS_AXIM_AMIB_WRITE_ISS_BM(__ISS__) (((__ISS__) == AXIM_AMIB_WRITE_ISS_BM_NORMAL) || \ + ((__ISS__) == AXIM_AMIB_WRITE_ISS_BM_FORCE_TO_1)) + +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group3 + * @{ + */ + +/* DBGMCU Peripheral Control functions ***************************************/ +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group4 + * @{ + */ + +/* SBS Control functions *****************************************************/ +uint32_t HAL_SBS_GetBootAddress(void); + +void HAL_SBS_IncrementHDPLValue(void); +uint32_t HAL_SBS_GetHDPLValue(void); + +void HAL_SBS_OpenAccessPort(void); +void HAL_SBS_OpenDebug(void); +HAL_StatusTypeDef HAL_SBS_ConfigDebugLevel(uint32_t Level); +uint32_t HAL_SBS_GetDebugLevel(void); +void HAL_SBS_UnlockDebugConfig(void); +void HAL_SBS_LockDebugConfig(void); + +void HAL_SBS_ConfigRSSCommand(uint32_t Cmd); +uint32_t HAL_SBS_GetRSSCommand(void); + +void HAL_SBS_EnableIOAnalogBooster(void); +void HAL_SBS_DisableIOAnalogBooster(void); +void HAL_SBS_EnableIOAnalogSwitchVdd(void); +void HAL_SBS_DisableIOAnalogSwitchVdd(void); +void HAL_SBS_ConfigEthernetPHY(uint32_t Config); +void HAL_SBS_ConfigAXISRAMWaitState(uint32_t Config); + +void HAL_SBS_EnableCompensationCell(uint32_t Selection); +void HAL_SBS_DisableCompensationCell(uint32_t Selection); +uint32_t HAL_SBS_GetCompensationCellReadyStatus(uint32_t Selection); +void HAL_SBS_ConfigCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue, + uint32_t PmosValue); +HAL_StatusTypeDef HAL_SBS_GetCompensationCell(uint32_t Selection, uint32_t *pCode, uint32_t *pNmosValue, + uint32_t *pPmosValue); + +void HAL_SBS_EnableIOSpeedOptimize(uint32_t Selection); +void HAL_SBS_DisableIOSpeedOptimize(uint32_t Selection); + +void HAL_SBS_ConfigTimerBreakInput(uint32_t Input); +uint32_t HAL_SBS_GetTimerBreakInputConfig(void); + +void HAL_SBS_EXTIConfig(uint32_t Exti, uint32_t Port); +uint32_t HAL_SBS_GetEXTIConfig(uint32_t Exti); +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group5 + * @{ + */ + +/* VREFBUF Control functions *************************************************/ +void HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); +void HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode); +void HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); +HAL_StatusTypeDef HAL_VREFBUF_Enable(void); +void HAL_VREFBUF_Disable(void); + + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group6 + * @{ + */ + +/* AXIM Configuration functions *************************************************/ +void HAL_AXIM_ASIB_EnablePacking(AXIM_ASIB_TypeDef *AsibInstance); +void HAL_AXIM_ASIB_DisablePacking(AXIM_ASIB_TypeDef *AsibInstance); +void HAL_AXIM_ASIB_IssuingConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t ReadIssuing, + uint32_t WriteIssuing); +void HAL_AXIM_ASIB_ReadQoSConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t QosPriority); +void HAL_AXIM_ASIB_WriteQoSConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t QosPriority); + + +void HAL_AXIM_AMIB_EnablePacking(AXIM_AMIB_TypeDef *AmibInstance); +void HAL_AXIM_AMIB_DisablePacking(AXIM_AMIB_TypeDef *AmibInstance); +void HAL_AXIM_AMIB_IssuingConfig(AXIM_AMIB_TypeDef *AmibInstance, uint32_t ReadIssuing, + uint32_t WriteIssuing); +void HAL_AXIM_AMIB_IssuingConfigBusMatrix(AXIM_AMIB_TypeDef *AmibInstance, uint32_t ReadIssuing, + uint32_t WriteIssuing); +void HAL_AXIM_AMIB_EnableLongBurst(AXIM_AMIB_TypeDef *AmibInstance); +void HAL_AXIM_AMIB_DisableLongBurst(AXIM_AMIB_TypeDef *AmibInstance); +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_adc.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_adc.h new file mode 100644 index 00000000000..7c180e7c6a8 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_adc.h @@ -0,0 +1,2028 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_adc.h + * @author MCD Application Team + * @brief Header file of ADC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_ADC_H +#define STM32H7RSxx_HAL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/* Include low level driver */ +#include "stm32h7rsxx_ll_adc.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Types ADC Exported Types + * @{ + */ + +/** + * @brief ADC group regular oversampling structure definition + */ +typedef struct +{ + uint32_t Ratio; /*!< Configures the oversampling ratio. + This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ + + uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. + This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ + + uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. + This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ + + uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. + The oversampling is either temporary stopped or reset upon an injected + sequence interruption. + If oversampling is enabled on both regular and injected groups, this + parameter is discarded and forced to setting + "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed + during injection sequence). + This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ + +} ADC_OversamplingTypeDef; + +/** + * @brief Structure definition of ADC instance and ADC group regular. + * @note Parameters of this structure are shared within 2 scopes: + * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, + * ScanConvMode, EOCSelection, LowPowerAutoWait. + * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, + * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling, + * SamplingMode. + * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled + * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled + * without conversion on going on group regular. + * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going + * on groups regular and injected. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behavior in case of intended action to update another + * parameter (which fulfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous + clock derived from system clock or PLL (Refer to reference manual for list of + clocks available)) and clock prescaler. + This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. + Note: The ADC clock configuration is common to all ADC instances. + Note: In case of usage of channels on injected group, ADC frequency should be + lower than AHB clock frequency /4 for resolution 12 or 10 bits, + AHB clock frequency /3 for resolution 8 bits, + AHB clock frequency /2 for resolution 6 bits. + Note: In case of synchronous clock mode based on HCLK/1, the configuration must + be enabled only if the system clock has a 50% duty clock cycle (APB + prescaler configured inside RCC must be bypassed and PCLK clock must have + 50% duty cycle). Refer to reference manual for details. + Note: In case of usage of asynchronous clock, the selected clock must be + preliminarily enabled at RCC top level. + Note: This parameter can be modified only if all ADC instances are disabled. */ + + uint32_t Resolution; /*!< Configure the ADC resolution. + This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ + + uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). + Refer to reference manual for alignments formats versus resolutions. + This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ + + uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. + This parameter can be associated to parameter 'DiscontinuousConvMode' to have + main sequence subdivided in successive parts. + If disabled: Conversion is performed in single mode (one channel converted, the + one defined in rank 1). Parameters 'NbrOfConversion' and + 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). + If enabled: Conversions are performed in sequence mode (multiple ranks defined + by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each + channel in sequencer). Scan direction is upward: from rank 1 to + rank 'n'. + This parameter can be a value of @ref ADC_Scan_mode */ + + uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and + interruption: end of unitary conversion or end of sequence conversions. + This parameter can be a value of @ref ADC_EOCSelection. */ + + FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the + previous conversion (for ADC group regular) or previous sequence (for ADC group + injected) has been retrieved by user software, using function HAL_ADC_GetValue() + or HAL_ADCEx_InjectedGetValue(). + This feature automatically adapts the frequency of ADC conversions triggers to + the speed of the system that reads the data. Moreover, this avoids risk of + overrun for low frequency applications. + This parameter can be set to ENABLE or DISABLE. + Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), + HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC + flag (by CPU to free the IRQ pending event or by DMA). + Auto wait will work but fort a very short time, discarding its intended + benefit (except specific case of high load of CPU or DMA transfers which + can justify usage of auto wait). + Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, + when ADC conversion data is needed: + use HAL_ADC_PollForConversion() to ensure that conversion is completed and + HAL_ADC_GetValue() to retrieve conversion result and trig another + conversion start. (in case of usage of ADC group injected, use the + equivalent functions HAL_ADCExInjected_Start(), + HAL_ADCEx_InjectedGetValue(), ...). */ + + FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) + or continuous mode for ADC group regular, after the first ADC conversion + start trigger occurred (software start or external trigger). This parameter + can be set to ENABLE or DISABLE. */ + + uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group + sequencer. + This parameter is dependent on ScanConvMode: + - sequencer configured to fully configurable: + Number of ranks in the scan sequence is configurable using this parameter. + Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to + parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. + Afterwards, when all needed sequencer ranks are set, parameter + 'NbrOfConversion' can be updated without modifying configuration of + sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded). + - sequencer configured to not fully configurable: + Number of ranks in the scan sequence is defined by number of channels set in + the sequence. This parameter is discarded. + This parameter must be a number between Min_Data = 1 and Max_Data = 8. + Note: This parameter must be modified when no conversion is on going on regular + group (ADC disabled, or ADC enabled without continuous mode or external + trigger that could launch a conversion). */ + + FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed + in Complete-sequence/Discontinuous-sequence (main sequence subdivided in + successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter + 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. + If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. + Note: On this STM32 series, ADC group regular number of discontinuous + ranks increment is fixed to one-by-one. */ + + uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence + of ADC group regular (parameter NbrOfConversion) will be subdivided. + If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. + This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ + + uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion + start. + If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger + is used instead. + This parameter can be a value of @ref ADC_regular_external_trigger_source. + Caution: external trigger source is common to all ADC instances. */ + + uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start + If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. + This parameter can be a value of @ref ADC_regular_external_trigger_edge */ + + uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion. + This parameter can be a value of @ref ADC_regular_sampling_mode */ + + uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (one shot + or circular), or stored in the DR register or transferred to ADF register. + Note: In continuous mode, DMA must be configured in circular mode. Otherwise + an overrun will be triggered when DMA buffer maximum pointer is reached. + This parameter can be a value of @ref ADC_ConversionDataManagement. + Note: This parameter must be modified when no conversion is on going on both + regular and injected groups (ADC disabled, or ADC enabled without continuous mode + or external trigger that could launch a conversion). */ + + uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). + This parameter applies to ADC group regular only. + This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. + Note: In case of overrun set to data preserved and usage with programming model + with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of + conversion flags, this induces the release of the preserved data. If + needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), + placed in user program code (called before end of conversion flags clear) + Note: Error reporting with respect to the conversion mode: + - Usage with ADC conversion by polling for event or interruption: Error is + reported only if overrun is set to data preserved. If overrun is set to + data overwritten, user can willingly not read all the converted data, + this is not considered as an erroneous case. + - Usage with ADC conversion by DMA: Error is reported whatever overrun + setting (DMA is expected to process all data from data register). */ + + FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. + This parameter can be set to ENABLE or DISABLE. + Note: This parameter can be modified only if there is no conversion is + ongoing on ADC groups regular and injected */ + + ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. + Caution: this setting overwrites the previous oversampling configuration + if oversampling is already enabled. */ + +} ADC_InitTypeDef; + +/** + * @brief Structure definition of ADC channel for regular group + * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') + * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion + * on going on regular group. + * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on + * regular and injected groups. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behavior in case of intended action to update another + * parameter (which fulfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL + Note: Depending on devices and ADC instances, some channels may not be available + on device package pins. Refer to device datasheet for channels + availability. */ + + uint32_t Rank; /*!< Specify the rank in the regular group sequencer. + This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS + Note: to disable a channel or change order of conversion sequencer, rank + containing a previous channel setting can be overwritten by the new channel + setting (or parameter number of conversions adjusted) */ + + uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time + (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, + 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME + Caution: This parameter applies to a channel that can be used into regular + and/or injected group. It overwrites the last setting. + Note: In case of usage of internal measurement channels (VrefInt, Vbat, ...), + sampling time constraints must be respected (sampling time can be adjusted + in function of ADC clock frequency and sampling time setting). + Refer to device datasheet for timings values. */ + + uint32_t SingleDiff; /*!< Select single-ended or differential input. + In differential mode: Differential measurement is carried out between the + selected channel 'i' (positive input) and channel 'i+1' (negative input). + Only channel 'i' has to be configured, channel 'i+1' is configured automatically + This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING + Caution: This parameter applies to a channel that can be used in a regular + and/or injected group. + It overwrites the last setting. + Note: Refer to Reference Manual to ensure the selected channel is available in + differential mode. + Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is + not usable separately. + Note: This parameter must be modified when ADC is disabled (before ADC start + conversion or after ADC stop conversion). + If ADC is enabled, this parameter setting is bypassed without error + reporting (as it can be the expected behavior in case of another parameter + update on the fly) */ + + uint32_t OffsetNumber; /*!< Select the offset number + This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB + Caution: Only one offset is allowed per channel. This parameter overwrites the + last setting. */ + + uint32_t Offset; /*!< Define the offset to be applied on the raw converted data. + Offset value must be a positive number. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter + must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, + 0x3FF, 0xFF or 0x3F respectively. + Note: This parameter must be modified when no conversion is on going on both + regular and injected groups (ADC disabled, or ADC enabled without + continuous mode or external trigger that could launch a conversion). */ + + uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive + sign) from or to the raw converted data. + This parameter can be a value of @ref ADCEx_OffsetSign. + Note: This parameter must be modified when no conversion is on going on both + regular and injected groups (ADC disabled, or ADC enabled without + continuous mode or external trigger that could launch a conversion).*/ + FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. + This parameter value can be ENABLE or DISABLE. + Note: This parameter must be modified when no conversion is on going on both + regular and injected groups (ADC disabled, or ADC enabled without + continuous mode or external trigger that could launch a conversion). */ + +} ADC_ChannelConfTypeDef; + +/** + * @brief Structure definition of ADC analog watchdog + * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion + on going on ADC groups regular and injected. + * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and + injected groups. + */ +typedef struct +{ + uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. + For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels + by setting parameter 'WatchdogMode') + For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls + of 'HAL_ADC_AnalogWDGConfig()' for each channel) + This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ + + uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. + For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all + channels, ADC groups regular and-or injected. + For Analog Watchdog 2 and 3: Several channels can be monitored by applying + successively the AWD init structure. Channels on ADC + group regular and injected are not differentiated: Set + value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 + channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor + all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no + channel. + This parameter can be a value of @ref ADC_analog_watchdog_mode. */ + + uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. + For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' + is configured on single channel (only 1 channel can be + monitored). + For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, + call successively the function HAL_ADC_AnalogWDGConfig() + for each channel to be added (or removed with value + 'ADC_ANALOGWATCHDOG_NONE'). + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ + + FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a + number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F + respectively. + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC + resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 + LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + impacted: the comparison of analog watchdog thresholds is done on + oversampling final computation (after ratio and shift application): + ADC data register bitfield [15:4] (12 most significant bits). */ + + uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a + number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F + respectively. + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC + resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 + LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + impacted: the comparison of analog watchdog thresholds is done on + oversampling final computation (after ratio and shift application): + ADC data register bitfield [15:4] (12 most significant bits).*/ + + uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider. + Before setting flag or raising interrupt, analog watchdog can wait to have several + consecutive out-of-window samples. This parameter allows to configure this number. + This parameter only applies to Analog watchdog 1. For others, use value + ADC_AWD_FILTERING_NONE. + This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */ +} ADC_AnalogWDGConfTypeDef; + +/** + * @brief ADC group injected contexts queue configuration + * @note Structure intended to be used only through structure "ADC_HandleTypeDef" + */ +typedef struct +{ + uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each + HAL_ADCEx_InjectedConfigChannel() call to finally initialize + JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ + + uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ +} ADC_InjectionConfigTypeDef; + +/** @defgroup ADC_States ADC States + * @{ + */ + +/** + * @brief HAL ADC state machine: ADC states definition (bitfields) + * @note ADC state machine is managed by bitfields, state must be compared + * with bit by bit. + * For example: + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " + */ +/* States of ADC global scope */ +#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, + calibration, ...) */ +#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ + +/* States of ADC errors */ +#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ + +/* States of ADC group regular */ +#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur + (either by continuous mode, external trigger, low power + auto power-on (if feature available), multimode ADC master + control (if feature available)) */ +#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag + raised */ + +/* States of ADC group injected */ +#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur + (either by auto-injection mode, external trigger, low + power auto power-on (if feature available), multimode + ADC master control (if feature available)) */ +#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ + +/* States of ADC analog watchdogs */ +#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ + +/* States of ADC multi-mode */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC + master (when feature available) */ + +/** + * @} + */ + +/** + * @brief ADC handle Structure definition + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +typedef struct __ADC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +{ + ADC_TypeDef *Instance; /*!< Register base address */ + ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular + conversions setting */ + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + HAL_LockTypeDef Lock; /*!< ADC locking object */ + __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ + __IO uint32_t ErrorCode; /*!< ADC Error code */ + ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up + structure */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ + void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer + callback */ + void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ + void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ + void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete + callback */ + void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue + overflow callback */ + void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ + void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ + void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ + void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ + void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} ADC_HandleTypeDef; + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL ADC Callback ID enumeration definition + */ +typedef enum +{ + HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ + HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ + HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ + HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ + HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ + HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ + HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ + HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ +} HAL_ADC_CallbackIDTypeDef; + +/** + * @brief HAL ADC Callback pointer definition + */ +typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_Error_Code ADC Error Code + * @{ + */ +#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, + enable/disable, erroneous state, ...) */ +#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ +#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source + * @{ + */ + +#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock + without prescaler */ +#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock + with prescaler division by 2 */ +#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock + with prescaler division by 4 */ +#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without + prescaler */ +#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler + division by 2 */ +#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler + division by 4 */ +#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler + division by 6 */ +#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler + division by 8 */ +#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler + division by 10 */ +#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler + division by 12 */ +#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler + division by 16 */ +#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler + division by 32 */ +#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler + division by 64 */ +#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler + division by 128 */ +#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler + division by 256 */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution + * @{ + */ +#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ +#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ +#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ +#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment + * @{ + */ +#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned + (alignment on data register LSB bit 0)*/ +#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned + (alignment on data register MSB bit 15)*/ +/** + * @} + */ + +/** @defgroup ADC_Scan_mode ADC sequencer scan mode + * @{ + */ +#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ +#define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ +/** + * @} + */ + +/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source + * @{ + */ +/* ADC group regular trigger sources for all ADC instances */ +#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion + trigger software start */ +#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 channel 1 event (capture compare). */ +#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 channel 2 event (capture compare). */ +#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 channel 3 event (capture compare). */ +#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion + trigger from external peripheral: TIM2 channel 2 event (capture compare). */ +#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM3 TRGO event. */ +#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion + trigger from external peripheral: TIM4 channel 4 event (capture compare). */ +#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion + trigger from external peripheral: external interrupt line 11 event. */ +#define ADC_EXTERNALTRIG_T12_TRGO (LL_ADC_REG_TRIG_EXT_TIM12_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM12 TRGO event. */ +#define ADC_EXTERNALTRIG_T9_TRGO (LL_ADC_REG_TRIG_EXT_TIM9_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM9 TRGO event. */ +#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 TRGO event. */ +#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 TRGO2 event. */ +#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM2 TRGO event. */ +#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM4 TRGO event. */ +#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM6 TRGO event. */ +#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM15 TRGO event. */ +#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion + trigger from external peripheral: TIM3 channel 4 event (capture compare). */ +#define ADC_EXTERNALTRIG_LPTIM1_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) /*!< ADC group regular conversion + trigger from external peripheral: LPTIM1 channel 1 event (capture compare). */ +#define ADC_EXTERNALTRIG_LPTIM2_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) /*!< ADC group regular conversion + trigger from external peripheral: LPTIM2 channel 1 event (capture compare). */ +#define ADC_EXTERNALTRIG_LPTIM3_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM3_CH1) /*!< ADC group regular conversion + trigger from external peripheral: LPTIM3 channel 1 event (capture compare). */ +/** + * @} + */ + +/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) + * @{ + */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger + disabled (SW start)*/ +#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion + trigger polarity set to rising edge */ +#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion + trigger polarity set to falling edge */ +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion + trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode + * @{ + */ +#define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is + defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */ +#define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts + immediately after end of conversion, and stops upon trigger event. + Note: First conversion is using minimal sampling time + (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */ +#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled + by trigger events: + Trigger rising edge = start sampling + Trigger falling edge = stop sampling and start conversion */ +/** + * @} + */ + +/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions + * @{ + */ +#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ +#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data + * @{ + */ +#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case + of overrun: data preserved */ +#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case + of overrun: data overwritten */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks + * @{ + */ +#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ +#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ +#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ +#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ +#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ +#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ +#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ +#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ +#define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ +#define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ +#define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ +#define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ +#define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ +#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ +#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ +#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @{ + */ +#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ +#define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ +#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ +#define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ +#define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ +#define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ +#define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ +#define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ +#define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 + ADC clock cycles. If selected, this sampling time replaces sampling time + 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ +/* all ADC instances (refer to Reference Manual). */ +#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ +#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ +#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ +#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ +#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ +#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ +#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ +#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ +#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ +#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ +#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ +#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ +#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ +#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ +#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */ +#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */ +#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */ +#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */ +#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */ +#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal + voltage reference, channel specific to ADC1. */ +#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor, + channel specific to ADC1. */ +#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/4: Vbat voltage + through a divider ladder of factor 1/4 to have channel voltage always below + Vdda, channel specific to ADC2. */ +#define ADC_CHANNEL_VDDCORE (LL_ADC_CHANNEL_VDDCORE) /*!< Internal channel Vddcore, channel + specific to ADC2. */ +/** + * @} + */ + +/** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management + * @{ + */ +#define ADC_CONVERSIONDATA_DR (0x00000000UL) /*!< Regular Conversion data stored in DR register + only */ +#define ADC_CONVERSIONDATA_DMA_ONESHOT (0x00000000UL) /*!< DMA one shot mode selected. + Note: DMA access is enabled in function HAL_ADC_Start_DMA. */ +#define ADC_CONVERSIONDATA_DMA_CIRCULAR (ADC_CFGR_DMACFG) /*!< DMA circular mode selected. + Note: DMA access is enabled in function HAL_ADC_Start_DMA. */ +#define ADC_CONVERSIONDATA_MDF (ADC_CFGR_ADFCFG) /*!< MDF (ADF) mode selected */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number + * @{ + */ +#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ +#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ +#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_filtering_config ADC analog watchdog (AWD) filtering configuration + * @{ + */ +#define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC AWD no filtering, one +out-of-window sample to raise flag or interrupt */ +#define ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0)) /*!< ADC AWD 2 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1)) /*!< ADC AWD 3 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 4 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2)) /*!< ADC AWD 5 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 6 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC AWD 7 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_8SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \ + | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 8 consecutives + out-of-window samples to raise flag or interrupt */ +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode + * @{ + */ +#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */ +#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< ADC AWD applied to a regular + group single channel */ +#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to an + injected group single channel */ +#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN\ + | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to a regular + and injected groups single channel */ +#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< ADC AWD applied to regular + group all channels */ +#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to injected + group all channels */ +#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to regular + and injected groups all channels */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio + * @{ + */ +/** + * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed + * to result as the ADC oversampling conversion data (before potential shift) + */ +#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */ +#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */ +#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */ +#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */ +#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */ +#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */ +#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */ +#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift + * @{ + */ +/** + * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling + * conversion data) + */ +#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ +#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */ +#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */ +#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */ +#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */ +#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */ +#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */ +#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */ +#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode + * @{ + */ +#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: + continuous mode (all conversions of OVS ratio are done from 1 trigger) */ +#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: + discontinuous mode (each conversion of OVS ratio needs a trigger) */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular + * @{ + */ +#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained + during injection sequence */ +#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during + injection sequence */ +/** + * @} + */ + +/** @defgroup ADC_Event_type ADC Event type + * @{ + */ +/** + * @note Analog watchdog 1 is available on all stm32 series + * Analog watchdog 2 and 3 are not available on all series + */ +#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ +#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ +#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */ +#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */ +#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ +#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ +/** + * @} + */ +#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility + with other STM32 devices having only one analog watchdog */ + +/** @defgroup ADC_interrupts_definition ADC interrupts definition + * @{ + */ +#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ +#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ +#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ +#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ +#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ +#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ +#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ +#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ +#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog + watchdog) */ +#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog + watchdog) */ +#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ + +/** + * @} + */ + +/** @defgroup ADC_flags_definition ADC flags definition + * @{ + */ +#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ +#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ +#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ +#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ +#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ +#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ +#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ +#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ +#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + +/** + * @brief Verify the ADC data conversion setting. + * @param DATA : programmed DATA conversion mode. + * @retval SET (DATA is a valid value) or RESET (DATA is invalid) + */ +#define IS_ADC_CONVERSIONDATAMGT(DATA) \ + ((((DATA) == ADC_CONVERSIONDATA_DR)) || \ + (((DATA) == ADC_CONVERSIONDATA_MDF)) || \ + (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \ + (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR))) + +/** + * @brief Return resolution bits in CFGR register RES[1:0] field. + * @param __HANDLE__ ADC handle + * @retval Value of bitfield RES in CFGR register. + */ +#define ADC_GET_RESOLUTION(__HANDLE__) \ + (LL_ADC_GetResolution((__HANDLE__)->Instance)) + +/** + * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). + * @param __HANDLE__ ADC handle + * @retval None + */ +#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) + +/** + * @brief Simultaneously clear and set specific bits of the handle State. + * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), + * the first parameter is the ADC handle State, the second parameter is the + * bit field to clear, the third and last parameter is the bit field to set. + * @retval None + */ +#define ADC_STATE_CLR_SET MODIFY_REG + +/** + * @brief Verify that a given value is aligned with the ADC resolution range. + * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). + * @param __ADC_VALUE__ value checked against the resolution. + * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) + */ +#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ + ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) + +/** + * @brief Verify the length of the scheduled regular conversions group. + * @param __LENGTH__ number of programmed conversions. + * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) + * or RESET (__LENGTH__ is null or too large) + */ +#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) + + +/** + * @brief Verify the number of scheduled regular conversions in discontinuous mode. + * @param NUMBER number of scheduled regular conversions in discontinuous mode. + * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) + * or RESET (NUMBER is null or too large) + */ +#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) + + +/** + * @brief Verify the ADC clock setting. + * @param __ADC_CLOCK__ programmed ADC clock. + * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) + */ +#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) + +/** + * @brief Verify the ADC resolution setting. + * @param __RESOLUTION__ programmed ADC resolution. + * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) + */ +#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ + ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ + ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ + ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) + +/** + * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. + * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. + * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) + */ +#define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ + ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) + +/** + * @brief Verify the ADC converted data alignment. + * @param __ALIGN__ programmed ADC converted data alignment. + * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) + */ +#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ + ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) + +/** + * @brief Verify the ADC scan mode. + * @param __SCAN_MODE__ programmed ADC scan mode. + * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) + */ +#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ + ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) + +/** + * @brief Verify the ADC edge trigger setting for regular group. + * @param __EDGE__ programmed ADC edge trigger setting. + * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) + */ +#define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ + ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) + +/** + * @brief Verify the ADC regular conversions external trigger. + * @param __REGTRIG__ programmed ADC regular conversions external trigger. + * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) + */ +#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T12_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T9_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_CH1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_CH1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_CH1) || \ + ((__REGTRIG__) == ADC_SOFTWARE_START) ) + +/** + * @brief Verify the ADC regular conversions external trigger. + * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger. + * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid) + */ +#define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \ + ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \ + ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) ) + +/** + * @brief Verify the ADC regular conversions check for converted data availability. + * @param __EOC_SELECTION__ converted data availability check. + * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) + */ +#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ + ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) + +/** + * @brief Verify the ADC regular conversions overrun handling. + * @param __OVR__ ADC regular conversions overrun handling. + * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) + */ +#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ + ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) + +/** + * @brief Verify the ADC conversions sampling time. + * @param __TIME__ ADC conversions sampling time. + * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) + */ +#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ + ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ + ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ + ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ + ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ + ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ + ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ + ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ + ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) + +/** + * @brief Verify the ADC regular channel setting. + * @param __CHANNEL__ programmed ADC regular channel. + * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) + */ +#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ + ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ + ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ + ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ + ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ + ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ + ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ + ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ + ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ + ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ + ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ + ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ + ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ + ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ + ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ + ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) + +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ + +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ + +/* Fixed timeout values for ADC conversion (including sampling time) */ +/* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ +/* Maximum conversion time is 12.5 + Maximum sampling time */ +/* or 12.5 + 640.5 = 653 ADC clock cycles */ +/* Minimum ADC Clock frequency is 0.14 MHz */ +/* Maximum conversion time is */ +/* 653 / 0.14 MHz = 4.66 ms */ +#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ + +/* Delay for temperature sensor stabilization time. */ +/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ +/* Unit: us */ +#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ +/* Macro for internal HAL driver usage, and possibly can be used into code of */ +/* final user. */ + +/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. + * @{ + */ + +/** @brief Reset ADC handle state. + * @param __HANDLE__ ADC handle + * @retval None + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_ADC_STATE_RESET) +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @brief Enable ADC interrupt. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source + * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @retval None + */ +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable ADC interrupt. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source + * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @retval None + */ +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** @brief Checks if the specified ADC interrupt source is enabled or disabled. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC interrupt source to check + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source + * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @retval State of interruption (SET or RESET) + */ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Check whether the specified ADC flag is set or not. + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag + * This parameter can be one of the following values: + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag + * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag + * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) + * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. + * @retval State of flag (TRUE or FALSE). + */ +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the specified ADC flag. + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag + * This parameter can be one of the following values: + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag + * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag + * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) + * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. + * @retval None + */ +/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + (((__HANDLE__)->Instance->ISR) = (__FLAG__)) + +/** + * @} + */ + +/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals ADC_CHANNEL_x. + * @note Example: + * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 (3) + * @arg @ref ADC_CHANNEL_1 (3) + * @arg @ref ADC_CHANNEL_2 (3) + * @arg @ref ADC_CHANNEL_3 (3) + * @arg @ref ADC_CHANNEL_4 (3) + * @arg @ref ADC_CHANNEL_5 (3) + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC3.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * @retval Value between Min_Data=0 and Max_Data=18 + */ +#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) + +/** + * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "ADC_CHANNEL_4". + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 + * @retval Returned value can be one of the following values: + * @arg @ref ADC_CHANNEL_0 (3) + * @arg @ref ADC_CHANNEL_1 (3) + * @arg @ref ADC_CHANNEL_2 (3) + * @arg @ref ADC_CHANNEL_3 (3) + * @arg @ref ADC_CHANNEL_4 (3) + * @arg @ref ADC_CHANNEL_5 (3) + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * (1, 3) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * ADC_CHANNEL_1, ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 (3) + * @arg @ref ADC_CHANNEL_1 (3) + * @arg @ref ADC_CHANNEL_2 (3) + * @arg @ref ADC_CHANNEL_3 (3) + * @arg @ref ADC_CHANNEL_4 (3) + * @arg @ref ADC_CHANNEL_5 (3) + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC3.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel + * connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 (3) + * @arg @ref ADC_CHANNEL_1 (3) + * @arg @ref ADC_CHANNEL_2 (3) + * @arg @ref ADC_CHANNEL_3 (3) + * @arg @ref ADC_CHANNEL_4 (3) + * @arg @ref ADC_CHANNEL_5 (3) + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC3.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * @retval Returned value can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + */ +#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1. + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ +#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Helper macro to get the ADC multimode conversion data of ADC master + * or ADC slave from raw value with both ADC conversion data concatenated. + * @note This macro is intended to be used when multimode transfer by DMA + * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). + * In this case the transferred data need to processed with this macro + * to separate the conversion data of ADC master and ADC slave. + * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ + __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ + __LL_ADC_COMMON_INSTANCE((__ADCx__)) + +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data full-scale digital value + */ +#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param __DATA__ ADC conversion data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data to the requested resolution + */ +#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ + __ADC_RESOLUTION_CURRENT__,\ + __ADC_RESOLUTION_TARGET__) \ +__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ + (__ADC_RESOLUTION_CURRENT__),\ + (__ADC_RESOLUTION_TARGET__)) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ + (__ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value) + * in differential ended mode. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ + (__ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @note On this STM32 series, calibration data of internal voltage reference + * VrefInt corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * internal voltage reference VrefInt. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) + * of internal voltage reference VrefInt (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Analog reference voltage (unit: mV) + */ +#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor calibration values + * stored in system memory for each device during production. + * @note Calculation formula: + * Temperature = ((TS_ADC_DATA - TS_CAL1) + * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) + * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * Avg_Slope = (TS_CAL2 - TS_CAL1) + * / (TS_CAL2_TEMP - TS_CAL1_TEMP) + * TS_CAL1 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL1 (calibrated in factory) + * TS_CAL2 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL2 (calibrated in factory) + * Caution: Calculation relevancy under reserve that calibration + * parameters are correct (address and data). + * To calculate temperature using temperature sensor + * datasheet typical values (generic values less, therefore + * less accurate than calibrated values), + * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note On this STM32 series, calibration data of temperature sensor + * corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * temperature sensor. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal + * temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature + * sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * If temperature sensor calibration values are available on + * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), + * temperature calculation will be more accurate using + * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note ADC measurement data must correspond to a resolution of 12bits + * (full scale digital value 4095). If not the case, the data must be + * preliminarily rescaled to an equivalent resolution of 12 bits. + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value + (unit: uV/DegCelsius). + * On this STM32 series, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at + temperature and Vref+ defined in parameters below) (unit: mV). + * On this STM32 series, refer to device datasheet parameter "V30" + * (corresponding to TS_CAL1). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see + parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ + (__TEMPSENSOR_TYP_CALX_V__),\ + (__TEMPSENSOR_CALX_TEMP__),\ + (__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Include ADC HAL Extended module */ +#include "stm32h7rsxx_hal_adc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, + pADC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group2 + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); + +/* Non-blocking mode: Interruption */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); + +/* Non-blocking mode: DMA */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); + +/* ADC retrieve conversion value intended to be used with polling or interruption */ +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); + +/* ADC sampling control */ +HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc); + +/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, + const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); + +/** + * @} + */ + +/* Peripheral State functions *************************************************/ +/** @addtogroup ADC_Exported_Functions_Group4 + * @{ + */ +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup ADC_Private_Functions ADC Private Functions + * @{ + */ +HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); +void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); +void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); +void ADC_DMAError(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7RSxx_HAL_ADC_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_adc_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_adc_ex.h new file mode 100644 index 00000000000..6860507e543 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_adc_ex.h @@ -0,0 +1,1152 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_adc_ex.h + * @author MCD Application Team + * @brief Header file of ADC HAL extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_ADC_EX_H +#define STM32H7RSxx_HAL_ADC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup ADCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types + * @{ + */ + +/** + * @brief ADC Injected Conversion Oversampling structure definition + */ +typedef struct +{ + uint32_t Ratio; /*!< Configures the oversampling ratio. + This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ + + uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. + This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ +} ADC_InjOversamplingTypeDef; + +/** + * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected + * @note Parameters of this structure are shared within 2 scopes: + * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, + * InjectedOffsetNumber, InjectedOffset, InjectedOffsetSign, InjectedOffsetSaturation + * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, + * InjectedDiscontinuousConvMode, + * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, + * InjecOversamplingMode, InjecOversampling. + * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter + * 'InjectedSingleDiff') + * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled + * without conversion on going on injected group. + * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'InjectedOffsetSign', + * 'InjectedOffsetSaturation', 'AutoInjectedConv': ADC enabled without conversion on going on regular and + * injected groups. + * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', + * 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going + * on ADC groups regular and injected. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behavior in case of intended action to update another + * parameter (which fulfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL + Note: Depending on devices and ADC instances, some channels may not be + available on device package pins. Refer to device datasheet for + channels availability. */ + + uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. + This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. + Note: to disable a channel or change order of conversion sequencer, + rank containing a previous channel setting can be overwritten by + the new channel setting (or parameter number of conversions + adjusted) */ + + uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles. + Conversion time is the addition of sampling time and processing time + (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, + 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. + Caution: This parameter applies to a channel that can be used in a + regular and/or injected group. It overwrites the last setting. + Note: In case of usage of internal measurement channels (VrefInt, ...), + sampling time constraints must be respected (sampling time can be + adjusted in function of ADC clock frequency and sampling time + setting). Refer to device datasheet for timings values. */ + + uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. + In differential mode: Differential measurement is between the selected + channel 'i' (positive input) and channel 'i+1' (negative input). + Only channel 'i' has to be configured, channel 'i+1' is configured + automatically. + This parameter must be a value of + @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. + Caution: This parameter applies to a channel that can be used in a + regular and/or injected group. It overwrites the last setting. + Note: Refer to Reference Manual to ensure the selected channel is + available in differential mode. + Note: When configuring a channel 'i' in differential mode, the channel + 'i+1' is not usable separately. + Note: This parameter must be modified when ADC is disabled (before ADC + start conversion or after ADC stop conversion). + If ADC is enabled, this parameter setting is bypassed without error + reporting (as it can be the expected behavior in case of another + parameter update on the fly) */ + + uint32_t InjectedOffsetNumber; /*!< Selects the offset number. + This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. + Caution: Only one offset is allowed per channel. This parameter + overwrites the last setting. */ + + uint32_t InjectedOffset; /*!< Defines the offset to be applied on the raw converted data. + Offset value must be a positive number. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this + parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, + 0x3FF, 0xFF or 0x3F respectively. + Note: This parameter must be modified when no conversion is on going + on both regular and injected groups (ADC disabled, or ADC enabled + without continuous mode or external trigger that could launch a + conversion). */ + + uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added + (positive sign) from or to the raw converted data. + This parameter can be a value of @ref ADCEx_OffsetSign. + Note: This parameter must be modified when no conversion is on going + on both regular and injected groups (ADC disabled, or ADC + enabled without continuous mode or external trigger that could + launch a conversion). */ + FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. + This parameter value can be ENABLE or DISABLE. + Note: This parameter must be modified when no conversion is on going + on both regular and injected groups (ADC disabled, or ADC enabled + without continuous mode or external trigger that could launch a + conversion). */ + + uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group + injected sequencer. + To use the injected group sequencer and convert several ranks, parameter + 'ScanConvMode' must be enabled. + This parameter must be a number between Min_Data = 1 and Max_Data = 4. + Caution: this setting impacts the entire injected group. Therefore, + call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on + injected group can impact the configuration of other channels previously + set. */ + + FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected + is performed in Complete-sequence/Discontinuous-sequence + (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter + 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. + This parameter can be set to ENABLE or DISABLE. + Note: This parameter must be modified when ADC is disabled (before ADC + start conversion or after ADC stop conversion). + Note: For injected group, discontinuous mode converts the sequence + channel by channel (discontinuous length fixed to 1 rank). + Caution: this setting impacts the entire injected group. Therefore, + call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the + configuration of other channels previously set. */ + + FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion + after regular one + This parameter can be set to ENABLE or DISABLE. + Note: To use Automatic injected conversion, discontinuous mode must + be disabled ('DiscontinuousConvMode' and + 'InjectedDiscontinuousConvMode' set to DISABLE) + Note: To use Automatic injected conversion, injected group external + triggers must be disabled ('ExternalTrigInjecConv' set to + ADC_INJECTED_SOFTWARE_START) + Note: In case of DMA used with regular group: if DMA configured in + normal mode (single shot) JAUTO will be stopped upon DMA transfer + complete. + To maintain JAUTO always enabled, DMA must be configured in + circular mode. + Caution: this setting impacts the entire injected group. Therefore, + call of HAL_ADCEx_InjectedConfigChannel() to configure a channel + on injected group can impact the configuration of other channels + previously set. */ + + FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. + This parameter can be set to ENABLE or DISABLE. + If context queue is enabled, injected sequencer&channels configurations + are queued on up to 2 contexts. If a + new injected context is set when queue is full, error is triggered by + interruption and through function + 'HAL_ADCEx_InjectedQueueOverflowCallback'. + Caution: This feature request that the sequence is fully configured + before injected conversion start. + Therefore, configure channels with as many calls to + HAL_ADCEx_InjectedConfigChannel() as the + 'InjectedNbrOfConversion' parameter. + Caution: this setting impacts the entire injected group. Therefore, + call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the + configuration of other channels previously set. + Note: This parameter must be modified when ADC is disabled (before ADC + start conversion or after ADC stop conversion). */ + + uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of + injected group. + If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled + and software trigger is used instead. + This parameter can be a value of + @ref ADC_injected_external_trigger_source. + Caution: this setting impacts the entire injected group. Therefore, + call of HAL_ADCEx_InjectedConfigChannel() to configure a channel + on injected group can impact the configuration of other channels + previously set. */ + + uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. + This parameter can be a value of @ref ADC_injected_external_trigger_edge. + If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter + is discarded. + Caution: this setting impacts the entire injected group. Therefore, + call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the + configuration of other channels previously set. */ + + FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. + This parameter can be set to ENABLE or DISABLE. + Note: This parameter can be modified only if there is no + conversion is ongoing (both ADSTART and JADSTART cleared). */ + + ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. + Caution: this setting overwrites the previous oversampling + configuration if oversampling already enabled. + Note: This parameter can be modified only if there is no + conversion is ongoing (both ADSTART and JADSTART cleared).*/ +} ADC_InjectionConfTypeDef; + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Structure definition of ADC multimode + * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state + * (both Master and Slave ADCs). + * Both Master and Slave ADCs must be disabled. + */ +typedef struct +{ + uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. + This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ + + uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: + selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel + (one DMA channel for both ADC, DMA of ADC master). + This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */ + + uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. + This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. + Delay range depends on selected resolution: + from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, + from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ +} ADC_MultiModeTypeDef; +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants + * @{ + */ + +/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source + * @{ + */ +/* ADC group regular trigger sources for all ADC instances */ +#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< ADC group injected conversion + trigger software start */ +#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM1 TRGO event. */ +#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion + trigger from external peripheral: TIM1 channel 4 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM2 TRGO event. */ +#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion + trigger from external peripheral: TIM2 channel 1 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion + trigger from external peripheral: TIM3 channel 4 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM4 TRGO event. */ +#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion + trigger from external peripheral: external interrupt line 15. */ +#define ADC_EXTERNALTRIGINJEC_T9_CC1 (LL_ADC_INJ_TRIG_EXT_TIM9_CH1) /*!< ADC group injected conversion + trigger from external peripheral: TIM9 channel 1 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion + trigger from external peripheral: TIM1 TRGO2 event. */ +#define ADC_EXTERNALTRIGINJEC_T12_TRGO (LL_ADC_INJ_TRIG_EXT_TIM12_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM12 TRGO event. */ +#define ADC_EXTERNALTRIGINJEC_T9_TRGO (LL_ADC_INJ_TRIG_EXT_TIM9_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM9 TRGO event. */ +#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion + trigger from external peripheral: TIM3 channel 3 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM3 TRGO event. */ +#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion + trigger from external peripheral: TIM3 channel 1 event (capture compare). */ +#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM6 TRGO event. */ +#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion + trigger from external peripheral: TIM15 TRGO event. */ +#define ADC_EXTERNALTRIGINJEC_LPTIM1_CH2 (LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2) /*!< ADC group injected conversion + trigger from external peripheral: LPTIM1 channel 2 event (capture compare).*/ +#define ADC_EXTERNALTRIGINJEC_LPTIM2_CH2 (LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2) /*!< ADC group injected conversion + trigger from external peripheral: LPTIM2 channel 2 event (capture compare).*/ +#define ADC_EXTERNALTRIGINJEC_LPTIM3_CH1 (LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1) /*!< ADC group injected conversion + trigger from external peripheral: LPTIM3 channel 1 event (capture compare).*/ +/** + * @} + */ + +/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) + * @{ + */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions trigger + disabled (SW start)*/ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions trigger + polarity set to rising edge */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions trigger + polarity set to falling edge */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions trigger + polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending + * @{ + */ +#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended */ +#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number + * @{ + */ +#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected + ADC channel */ +#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which + the offset programmed will be applied (independently of channel mapped + on ADC group regular or group injected) */ +#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which + the offset programmed will be applied (independently of channel mapped + on ADC group regular or group injected) */ +#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which + the offset programmed will be applied (independently of channel mapped + on ADC group regular or group injected) */ +#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which + the offset programmed will be applied (independently of channel mapped + on ADC group regular or group injected) */ +/** + * @} + */ + +/** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign + * @{ + */ +#define ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */ +#define ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */ +/** + * @} + */ + +/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks + * @{ + */ +#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ +#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ +#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ +#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ +/** + * @} + */ + +#if defined(ADC_MULTIMODE_SUPPORT) +/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode + * @{ + */ +#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled + (ADC independent mode) */ +#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular + simultaneous */ +#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined + group regular interleaved */ +#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group + injected simultaneous */ +#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group + injected alternate trigger. Works only with external triggers (not internal + SW start) */ +#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined + group regular simultaneous + group injected simultaneous */ +#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined + group regular simultaneous + group injected alternate trigger */ +#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined + group regular interleaved + group injected simultaneous */ + +/** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution + * @{ + */ +#define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own + DMA channel */ +#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, + DMA of ADC master) for 12 and 10 bits resolution */ +#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, + DMA of ADC master) for 8 and 6 bits resolution */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases + * @{ + */ +#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two + sampling phases: 1 ADC clock cycle */ +#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two + sampling phases: 2 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two + sampling phases: 3 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two + sampling phases: 4 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two + sampling phases: 5 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two + sampling phases: 6 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two + sampling phases: 7 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two + sampling phases: 8 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two + sampling phases: 9 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two + sampling phases: 10 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two + sampling phases: 11 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two + sampling phases: 12 ADC clock cycles */ +/** + * @} + */ + +/** + * @} + */ +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups + * @{ + */ +#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on + all STM32 devices) */ +#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on + all STM32 devices) */ +#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ +/** + * @} + */ + +/** @defgroup ADC_CFGR_fields ADCx CFGR fields + * @{ + */ +#define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ + ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ + ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ + ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ + ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ + ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) +/** + * @} + */ + +/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields + * @{ + */ +#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ + ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ + ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ + ADC_SMPR1_SMP0) +/** + * @} + */ + +/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields + * @{ + */ +/* ADC_CFGR fields of parameters that can be updated when no conversion + (neither regular nor injected) is on-going */ +#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_ADFCFG | ADC_CFGR_AUTDLY)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +#if defined(ADC_MULTIMODE_SUPPORT) +/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros + * @{ + */ + +/** @brief Force ADC instance in multimode mode independent (multimode disable). + * @note This macro must be used only in case of transition from multimode + * to mode independent and in case of unknown previous state, + * to ensure ADC configuration is in mode independent. + * @note Standard way of multimode configuration change is done from + * HAL ADC handle of ADC master using function + * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". + * Usage of this macro is not the Standard way of multimode + * configuration and can lead to have HAL ADC handles status + * misaligned. Usage of this macro must be limited to cases + * mentioned above. + * @param __HANDLE__ ADC handle. + * @retval None + */ +#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ + LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) + +/** + * @} + */ +#endif /* ADC_MULTIMODE_SUPPORT */ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + +/** + * @brief Test if conversion trigger of injected group is software start + * or external trigger. + * @param __HANDLE__ ADC handle. + * @retval SET (software start) or RESET (external trigger). + */ +#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ + (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) + +/** + * @brief Check whether or not ADC is independent. + * @param __HANDLE__ ADC handle. + * @note When multimode feature is not available, the macro always returns SET. + * @retval SET (ADC is independent) or RESET (ADC is not). + */ +#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) + +/** + * @brief Set the selected injected Channel rank. + * @param __CHANNELNB__ Channel number. + * @param __RANKNB__ Rank number. + * @retval None + */ +#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) \ + ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \ + << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) + +/** + * @brief Configure ADC injected context queue + * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. + * @retval None + */ +#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) \ + ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) + +/** + * @brief Configure ADC discontinuous conversion mode for injected group + * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. + * @retval None + */ +#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) \ + ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) + +/** + * @brief Configure ADC discontinuous conversion mode for regular group + * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. + * @retval None + */ +#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) \ + ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) + +/** + * @brief Configure the number of discontinuous conversions for regular group. + * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. + * @retval None + */ +#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) \ + (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) + +/** + * @brief Configure the ADC auto delay mode. + * @param __AUTOWAIT__ Auto delay bit enable or disable. + * @retval None + */ +#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) + +/** + * @brief Configure ADC continuous conversion mode. + * @param __CONTINUOUS_MODE__ Continuous mode. + * @retval None + */ +#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) + + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Configure the ADC DMA continuous request for ADC multimode. + * @param __DMACONTREQ_MODE__ DMA continuous request mode. + * @retval None + */ +#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @brief Shift the offset with respect to the selected ADC resolution. + * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. + * If resolution 12 bits, no shift. + * If resolution 10 bits, shift of 2 ranks on the left. + * If resolution 8 bits, shift of 4 ranks on the left. + * If resolution 6 bits, shift of 6 ranks on the left. + * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). + * @param __HANDLE__ ADC handle + * @param __OFFSET__ Value to be shifted + * @retval None + */ +#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ + ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) + +/** + * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. + * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. + * If resolution 12 bits, no shift. + * If resolution 10 bits, shift of 2 ranks on the left. + * If resolution 8 bits, shift of 4 ranks on the left. + * If resolution 6 bits, shift of 6 ranks on the left. + * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). + * @param __HANDLE__ ADC handle + * @param __THRESHOLD__ Value to be shifted + * @retval None + */ +#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ + ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) + +/** + * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. + * @note Thresholds have to be left-aligned on bit 7. + * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). + * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). + * If resolution 8 bits, no shift. + * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). + * @param __HANDLE__ ADC handle + * @param __THRESHOLD__ Value to be shifted + * @retval None + */ +#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ + ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ + ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ + ((__THRESHOLD__) << 2UL) \ + ) + +/** + * @brief Clear Common Control Register. + * @param __HANDLE__ ADC handle. + * @retval None + */ +#if defined(ADC_MULTIMODE_SUPPORT) +#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ + ADC_CCR_CKMODE | \ + ADC_CCR_PRESC | \ + ADC_CCR_VBATEN | \ + ADC_CCR_TSEN | \ + ADC_CCR_VREFEN | \ + ADC_CCR_MDMA | \ + ADC_CCR_DMACFG | \ + ADC_CCR_DELAY | \ + ADC_CCR_DUAL) +#else +#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ + ADC_CCR_CKMODE | \ + ADC_CCR_PRESC | \ + ADC_CCR_VBATEN | \ + ADC_CCR_TSEN | \ + ADC_CCR_VREFEN) + +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @brief Set handle instance of the ADC slave associated to the ADC master. + * @param __HANDLE_MASTER__ ADC master handle. + * @param __HANDLE_SLAVE__ ADC slave handle. + * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC, __HANDLE_SLAVE__ instance is + * set to NULL. + * @retval None + */ +#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ + ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? \ + ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) + + +/** + * @brief Verify the ADC instance connected to the temperature sensor. + * @param __HANDLE__ ADC handle. + * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) + */ +#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) + +/** + * @brief Verify the ADC instance connected to the battery voltage VBAT. + * @param __HANDLE__ ADC handle. + * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) + */ +#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) + +/** + * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. + * @param __HANDLE__ ADC handle. + * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) + */ +#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) + +/** + * @brief Verify the ADC instance connected to the internal voltage reference VDDCORE. + * @param __HANDLE__ ADC handle. + * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) + */ +/* The internal voltage reference VDDCORE measurement path (channel 0) is available on ADC2 */ +#define ADC_VDDCORE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) + +/** + * @brief Verify the length of scheduled injected conversions group. + * @param __LENGTH__ number of programmed conversions. + * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) + * or RESET (__LENGTH__ is null or too large) + */ +#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) + +/** + * @brief Calibration factor size verification (7 bits maximum). + * @param __CALIBRATION_FACTOR__ Calibration factor value. + * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) + */ +#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) + + +/** + * @brief Verify the ADC channel setting. + * @param __HANDLE__ ADC handle. + * @param __CHANNEL__ programmed ADC channel. + * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) + */ +#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \ + ((__CHANNEL__) == ADC_CHANNEL_1) || \ + ((__CHANNEL__) == ADC_CHANNEL_2) || \ + ((__CHANNEL__) == ADC_CHANNEL_3) || \ + ((__CHANNEL__) == ADC_CHANNEL_4) || \ + ((__CHANNEL__) == ADC_CHANNEL_5) || \ + ((__CHANNEL__) == ADC_CHANNEL_6) || \ + ((__CHANNEL__) == ADC_CHANNEL_7) || \ + ((__CHANNEL__) == ADC_CHANNEL_8) || \ + ((__CHANNEL__) == ADC_CHANNEL_9) || \ + ((__CHANNEL__) == ADC_CHANNEL_10) || \ + ((__CHANNEL__) == ADC_CHANNEL_11) || \ + ((__CHANNEL__) == ADC_CHANNEL_12) || \ + ((__CHANNEL__) == ADC_CHANNEL_13) || \ + ((__CHANNEL__) == ADC_CHANNEL_14) || \ + ((__CHANNEL__) == ADC_CHANNEL_15) || \ + ((__CHANNEL__) == ADC_CHANNEL_16) || \ + ((__CHANNEL__) == ADC_CHANNEL_17) || \ + ((__CHANNEL__) == ADC_CHANNEL_18) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ + ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == ADC_CHANNEL_VDDCORE) ) + +/** + * @brief Verify the ADC channel setting in differential mode. + * @param __HANDLE__ ADC handle. + * @param __CHANNEL__ programmed ADC channel. + * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) + */ +#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ + ((__CHANNEL__) == ADC_CHANNEL_2) || \ + ((__CHANNEL__) == ADC_CHANNEL_3) || \ + ((__CHANNEL__) == ADC_CHANNEL_4) || \ + ((__CHANNEL__) == ADC_CHANNEL_8) || \ + ((__CHANNEL__) == ADC_CHANNEL_10) || \ + ((__CHANNEL__) == ADC_CHANNEL_11) || \ + ((__CHANNEL__) == ADC_CHANNEL_12) ) + +/** + * @brief Verify the ADC single-ended input or differential mode setting. + * @param __SING_DIFF__ programmed channel setting. + * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) + */ +#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ + ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) + +/** + * @brief Verify the ADC offset management setting. + * @param __OFFSET_NUMBER__ ADC offset management. + * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) + */ +#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ + ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ + ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ + ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ + ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) + +/** + * @brief Verify the ADC offset sign setting. + * @param __OFFSET_SIGN__ ADC offset sign. + * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid) + */ +#define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \ + ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE) ) + +/** + * @brief Verify the ADC injected channel setting. + * @param __CHANNEL__ programmed ADC injected channel. + * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) + */ +#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ + ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ + ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ + ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) + +/** + * @brief Verify the ADC injected conversions external trigger. + * @param __INJTRIG__ programmed ADC injected conversions external trigger. + * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) + */ +#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T9_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T12_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T9_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_CH2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_CH2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_CH1) || \ + ((__INJTRIG__) == ADC_SOFTWARE_START) ) + +/** + * @brief Verify the ADC edge trigger setting for injected group. + * @param __EDGE__ programmed ADC edge trigger setting. + * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) + */ +#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Verify the ADC multimode setting. + * @param __MODE__ programmed ADC multimode setting. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ + ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ + ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_INTERL) || \ + ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) + +/** + * @brief Verify the ADC multimode DMA access setting. + * @param __MODE__ programmed ADC multimode DMA access setting. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ + ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \ + ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) ) + +/** + * @brief Verify the ADC multimode delay setting. + * @param __DELAY__ programmed ADC multimode delay setting. + * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) + */ +#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @brief Verify the ADC analog watchdog setting. + * @param __WATCHDOG__ programmed ADC analog watchdog setting. + * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) + */ +#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) + +/** + * @brief Verify the ADC analog watchdog mode setting. + * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. + * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) + */ +#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) + +/** + * @brief Verify the ADC analog watchdog filtering setting. + * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting. + * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid) + */ +#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) \ + (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \ + ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \ + ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \ + ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \ + ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \ + ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \ + ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \ + ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES) ) + + +/** + * @brief Verify the ADC conversion (regular or injected or both). + * @param __CONVERSION__ ADC conversion group. + * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) + */ +#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ + ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ + ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) + +/** + * @brief Verify the ADC event type. + * @param __EVENT__ ADC event. + * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) + */ +#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ + ((__EVENT__) == ADC_AWD_EVENT) || \ + ((__EVENT__) == ADC_AWD2_EVENT) || \ + ((__EVENT__) == ADC_AWD3_EVENT) || \ + ((__EVENT__) == ADC_OVR_EVENT) || \ + ((__EVENT__) == ADC_JQOVF_EVENT) ) + +/** + * @brief Verify the ADC oversampling ratio. + * @param __RATIO__ programmed ADC oversampling ratio. + * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) + */ +#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) + +/** + * @brief Verify the ADC oversampling shift. + * @param __SHIFT__ programmed ADC oversampling shift. + * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) + */ +#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) + +/** + * @brief Verify the ADC oversampling triggered mode. + * @param __MODE__ programmed ADC oversampling triggered mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ + ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) + +/** + * @brief Verify the ADC oversampling regular conversion resumed or continued mode. + * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ + ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) + +/** + * @brief Verify the DFSDM mode configuration. + * @param __HANDLE__ ADC handle. + * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For + * this reason, the input parameter is the ADC handle and not the configuration parameter + * directly. + * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) + */ +#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) + +/** + * @brief Return the DFSDM configuration mode. + * @param __HANDLE__ ADC handle. + * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). + * For this reason, the input parameter is the ADC handle and not the configuration parameter + * directly. + * @retval DFSDM configuration mode + */ +#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADCEx_Exported_Functions + * @{ + */ + +/** @addtogroup ADCEx_Exported_Functions_Group1 + * @{ + */ +/* IO operation functions *****************************************************/ + +/* ADC calibration */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff); +HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, + uint32_t CalibrationFactor); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); + +/* Non-blocking mode: Interruption */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); + +#if defined(ADC_MULTIMODE_SUPPORT) +/* ADC multimode */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc); +#endif /* ADC_MULTIMODE_SUPPORT */ + +/* ADC retrieve conversion value intended to be used with polling or interruption */ +uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank); + +/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ +void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); + +/* ADC group regular conversions stop */ +HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); +#if defined(ADC_MULTIMODE_SUPPORT) +HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @addtogroup ADCEx_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, + const ADC_InjectionConfTypeDef *pConfigInjected); +#if defined(ADC_MULTIMODE_SUPPORT) +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, + const ADC_MultiModeTypeDef *pMultimode); +#endif /* ADC_MULTIMODE_SUPPORT */ + +HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_ADC_EX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cec.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cec.h new file mode 100644 index 00000000000..3ea75de16eb --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cec.h @@ -0,0 +1,804 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_cec.h + * @author MCD Application Team + * @brief Header file of CEC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_CEC_H +#define STM32H7RSxx_HAL_CEC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +#if defined (CEC) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup CEC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CEC_Exported_Types CEC Exported Types + * @{ + */ + +/** + * @brief CEC Init Structure definition + */ +typedef struct +{ + uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time. + It can be one of CEC_Signal_Free_Time + and belongs to the set {0,...,7} where + 0x0 is the default configuration + else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */ + + uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms, + it can be a value of CEC_Tolerance : + it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */ + + uint32_t BRERxStop; /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising + Error stops the reception. + CEC_NO_RX_STOP_ON_BRE: reception is not stopped. + CEC_RX_STOP_ON_BRE: reception is stopped. */ + + uint32_t BREErrorBitGen; /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an + Error-Bit is generated on the + CEC line upon Bit Rising Error detection. + CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. + CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */ + + uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an + Error-Bit is generated on the + CEC line upon Long Bit Period Error detection. + CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. + CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */ + + uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an + Error-Bit generation on the CEC line + upon an error detected on a broadcast message. + + It supersedes BREGEN and LBPEGEN bits for a broadcast message error + handling. It can take two values: + + 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. + a) BRE detection: error-bit generation on the CEC line if + BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. + b) LBPE detection: error-bit generation on the CEC line + if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION. + + 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. + no error-bit generation in case neither a) nor b) are satisfied. + Additionally, there is no error-bit generation in case of Short Bit + Period Error detection in a broadcast message while LSTN bit is set. */ + + uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts. + CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. + CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end + of message transmission/reception. */ + + uint32_t ListenMode; /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode. + It can take two values: + + CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed + to its own address (OAR). Messages addressed to different destination + are ignored. + Broadcast messages are always received. + + CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its + own address (OAR) with positive acknowledge. Messages addressed to + different destination are received, but without interfering with the + CEC bus: no acknowledge sent. */ + + uint16_t OwnAddress; /*!< Own addresses configuration + This parameter can be a value of CEC_OWN_ADDRESS */ + + uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */ + + +} CEC_InitTypeDef; + +/** + * @brief HAL CEC State definition + * @note HAL CEC State value is a combination of 2 different substates: gState and RxState + (see CEC_State_Definition). + * - gState contains CEC state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7 (not used) + * x : Should be set to 0 + * b6 Error information + * 0 : No Error + * 1 : Error + * b5 CEC peripheral initialization status + * 0 : Reset (peripheral not initialized) + * 1 : Init done (peripheral initialized. HAL CEC Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 CEC peripheral initialization status + * 0 : Reset (peripheral not initialized) + * 1 : Init done (peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_CEC_StateTypeDef; + +/** + * @brief CEC handle Structure definition + */ +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) +typedef struct __CEC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ +{ + CEC_TypeDef *Instance; /*!< CEC registers base address */ + + CEC_InitTypeDef Init; /*!< CEC communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ + + uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ + + uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of HAL_CEC_StateTypeDef */ + + HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations. + This parameter can be a value of HAL_CEC_StateTypeDef */ + + uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register + in case error is reported */ + +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) + void (* TxCpltCallback)(struct __CEC_HandleTypeDef + *hcec); /*!< CEC Tx Transfer completed callback */ + void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec, + uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */ + void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */ + + void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */ + void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */ + +#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */ +} CEC_HandleTypeDef; + +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL CEC Callback ID enumeration definition + */ +typedef enum +{ + HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */ + HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */ + HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */ + HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */ + HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */ +} HAL_CEC_CallbackIDTypeDef; + +/** + * @brief HAL CEC Callback pointer definition + */ +typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */ +typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, + uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed + callback function */ +#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CEC_Exported_Constants CEC Exported Constants + * @{ + */ +/** @defgroup CEC_State_Definition CEC State Code Definition + * @{ + */ +#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ +#define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */ +/** + * @} + */ +/** @defgroup CEC_Error_Code CEC Error Code + * @{ + */ +#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */ +#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */ +#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */ +#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */ +#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */ +#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */ +#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */ +#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */ +#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */ +#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */ +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) +#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error */ +#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter + * @{ + */ +#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U) +#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U) +#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U) +#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U) +#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U) +#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U) +#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U) +#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U) +/** + * @} + */ + +/** @defgroup CEC_Tolerance CEC Receiver Tolerance + * @{ + */ +#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U) +#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) +/** + * @} + */ + +/** @defgroup CEC_BRERxStop CEC Reception Stop on Error + * @{ + */ +#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U) +#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) +/** + * @} + */ + +/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported + * @{ + */ +#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) +#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) +/** + * @} + */ + +/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported + * @{ + */ +#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) +#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) +/** + * @} + */ + +/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message + * @{ + */ +#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U) +#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) +/** + * @} + */ + +/** @defgroup CEC_SFT_Option CEC Signal Free Time start option + * @{ + */ +#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U) +#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) +/** + * @} + */ + +/** @defgroup CEC_Listening_Mode CEC Listening mode option + * @{ + */ +#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U) +#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) +/** + * @} + */ + +/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register + * @{ + */ +#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U) +/** + * @} + */ + +/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header + * @{ + */ +#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U) +/** + * @} + */ + +/** @defgroup CEC_OWN_ADDRESS CEC Own Address + * @{ + */ +#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */ +#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */ +#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */ +#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */ +#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */ +#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */ +#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */ +#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */ +#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */ +#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */ +#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */ +#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */ +#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */ +#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */ +#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */ +#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */ +/** + * @} + */ + +/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition + * @{ + */ +#define CEC_IT_TXACKE CEC_IER_TXACKEIE +#define CEC_IT_TXERR CEC_IER_TXERRIE +#define CEC_IT_TXUDR CEC_IER_TXUDRIE +#define CEC_IT_TXEND CEC_IER_TXENDIE +#define CEC_IT_TXBR CEC_IER_TXBRIE +#define CEC_IT_ARBLST CEC_IER_ARBLSTIE +#define CEC_IT_RXACKE CEC_IER_RXACKEIE +#define CEC_IT_LBPE CEC_IER_LBPEIE +#define CEC_IT_SBPE CEC_IER_SBPEIE +#define CEC_IT_BRE CEC_IER_BREIE +#define CEC_IT_RXOVR CEC_IER_RXOVRIE +#define CEC_IT_RXEND CEC_IER_RXENDIE +#define CEC_IT_RXBR CEC_IER_RXBRIE +/** + * @} + */ + +/** @defgroup CEC_Flags_Definitions CEC Flags definition + * @{ + */ +#define CEC_FLAG_TXACKE CEC_ISR_TXACKE +#define CEC_FLAG_TXERR CEC_ISR_TXERR +#define CEC_FLAG_TXUDR CEC_ISR_TXUDR +#define CEC_FLAG_TXEND CEC_ISR_TXEND +#define CEC_FLAG_TXBR CEC_ISR_TXBR +#define CEC_FLAG_ARBLST CEC_ISR_ARBLST +#define CEC_FLAG_RXACKE CEC_ISR_RXACKE +#define CEC_FLAG_LBPE CEC_ISR_LBPE +#define CEC_FLAG_SBPE CEC_ISR_SBPE +#define CEC_FLAG_BRE CEC_ISR_BRE +#define CEC_FLAG_RXOVR CEC_ISR_RXOVR +#define CEC_FLAG_RXEND CEC_ISR_RXEND +#define CEC_FLAG_RXBR CEC_ISR_RXBR +/** + * @} + */ + +/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags + * @{ + */ +#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ + CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) +/** + * @} + */ + +/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag + * @{ + */ +#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) +/** + * @} + */ + +/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag + * @{ + */ +#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CEC_Exported_Macros CEC Exported Macros + * @{ + */ + +/** @brief Reset CEC handle gstate & RxState + * @param __HANDLE__ CEC handle. + * @retval None + */ +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) +#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ +/** @brief Checks whether or not the specified CEC interrupt flag is set. + * @param __HANDLE__ specifies the CEC Handle. + * @param __FLAG__ specifies the flag to check. + * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error + * @arg CEC_FLAG_TXERR: Tx Error. + * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. + * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). + * @arg CEC_FLAG_TXBR: Tx-Byte Request. + * @arg CEC_FLAG_ARBLST: Arbitration Lost + * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge + * @arg CEC_FLAG_LBPE: Rx Long period Error + * @arg CEC_FLAG_SBPE: Rx Short period Error + * @arg CEC_FLAG_BRE: Rx Bit Rising Error + * @arg CEC_FLAG_RXOVR: Rx Overrun. + * @arg CEC_FLAG_RXEND: End Of Reception. + * @arg CEC_FLAG_RXBR: Rx-Byte Received. + * @retval ITStatus + */ +#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) + +/** @brief Clears the interrupt or status flag when raised (write at 1) + * @param __HANDLE__ specifies the CEC Handle. + * @param __FLAG__ specifies the interrupt/status flag to clear. + * This parameter can be one of the following values: + * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error + * @arg CEC_FLAG_TXERR: Tx Error. + * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. + * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). + * @arg CEC_FLAG_TXBR: Tx-Byte Request. + * @arg CEC_FLAG_ARBLST: Arbitration Lost + * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge + * @arg CEC_FLAG_LBPE: Rx Long period Error + * @arg CEC_FLAG_SBPE: Rx Short period Error + * @arg CEC_FLAG_BRE: Rx Bit Rising Error + * @arg CEC_FLAG_RXOVR: Rx Overrun. + * @arg CEC_FLAG_RXEND: End Of Reception. + * @arg CEC_FLAG_RXBR: Rx-Byte Received. + * @retval none + */ +#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) + +/** @brief Enables the specified CEC interrupt. + * @param __HANDLE__ specifies the CEC Handle. + * @param __INTERRUPT__ specifies the CEC interrupt to enable. + * This parameter can be one of the following values: + * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable + * @arg CEC_IT_TXERR: Tx Error IT Enable + * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable + * @arg CEC_IT_TXEND: End of transmission IT Enable + * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable + * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable + * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable + * @arg CEC_IT_LBPE: Rx Long period Error IT Enable + * @arg CEC_IT_SBPE: Rx Short period Error IT Enable + * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable + * @arg CEC_IT_RXOVR: Rx Overrun IT Enable + * @arg CEC_IT_RXEND: End Of Reception IT Enable + * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable + * @retval none + */ +#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** @brief Disables the specified CEC interrupt. + * @param __HANDLE__ specifies the CEC Handle. + * @param __INTERRUPT__ specifies the CEC interrupt to disable. + * This parameter can be one of the following values: + * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable + * @arg CEC_IT_TXERR: Tx Error IT Enable + * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable + * @arg CEC_IT_TXEND: End of transmission IT Enable + * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable + * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable + * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable + * @arg CEC_IT_LBPE: Rx Long period Error IT Enable + * @arg CEC_IT_SBPE: Rx Short period Error IT Enable + * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable + * @arg CEC_IT_RXOVR: Rx Overrun IT Enable + * @arg CEC_IT_RXEND: End Of Reception IT Enable + * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable + * @retval none + */ +#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) + +/** @brief Checks whether or not the specified CEC interrupt is enabled. + * @param __HANDLE__ specifies the CEC Handle. + * @param __INTERRUPT__ specifies the CEC interrupt to check. + * This parameter can be one of the following values: + * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable + * @arg CEC_IT_TXERR: Tx Error IT Enable + * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable + * @arg CEC_IT_TXEND: End of transmission IT Enable + * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable + * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable + * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable + * @arg CEC_IT_LBPE: Rx Long period Error IT Enable + * @arg CEC_IT_SBPE: Rx Short period Error IT Enable + * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable + * @arg CEC_IT_RXOVR: Rx Overrun IT Enable + * @arg CEC_IT_RXEND: End Of Reception IT Enable + * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable + * @retval FlagStatus + */ +#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) + +/** @brief Enables the CEC device + * @param __HANDLE__ specifies the CEC Handle. + * @retval none + */ +#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) + +/** @brief Disables the CEC device + * @param __HANDLE__ specifies the CEC Handle. + * @retval none + */ +#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) + +/** @brief Set Transmission Start flag + * @param __HANDLE__ specifies the CEC Handle. + * @retval none + */ +#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) + +/** @brief Set Transmission End flag + * @param __HANDLE__ specifies the CEC Handle. + * @retval none + * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. + */ +#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) + +/** @brief Get Transmission Start flag + * @param __HANDLE__ specifies the CEC Handle. + * @retval FlagStatus + */ +#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) + +/** @brief Get Transmission End flag + * @param __HANDLE__ specifies the CEC Handle. + * @retval FlagStatus + */ +#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) + +/** @brief Clear OAR register + * @param __HANDLE__ specifies the CEC Handle. + * @retval none + */ +#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) + +/** @brief Set OAR register (without resetting previously set address in case of multi-address mode) + * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand + * @param __HANDLE__ specifies the CEC Handle. + * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position) + * @retval none + */ +#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \ + (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CEC_Exported_Functions + * @{ + */ + +/** @addtogroup CEC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec); +HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec); +HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress); +void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); +void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); + +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, + pCEC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec); +#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup CEC_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, + const uint8_t *pData, uint32_t Size); +uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec); +void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer); +void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); +void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); +void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); +void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); +/** + * @} + */ + +/** @addtogroup CEC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec); +uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup CEC_Private_Types CEC Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CEC_Private_Variables CEC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CEC_Private_Constants CEC Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CEC_Private_Macros CEC Private Macros + * @{ + */ + +#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT) + +#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \ + ((__RXTOL__) == CEC_EXTENDED_TOLERANCE)) + +#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \ + ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE)) + +#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \ + ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION)) + +#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \ + ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION)) + +#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \ + (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ + ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) + +#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \ + ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END)) + +#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \ + ((__MODE__) == CEC_FULL_LISTENING_MODE)) + +/** @brief Check CEC message size. + * The message size is the payload size: without counting the header, + * it varies from 0 byte (ping operation, one header only, no payload) to + * 15 bytes (1 opcode and up to 14 operands following the header). + * @param __SIZE__ CEC message size. + * @retval Test result (TRUE or FALSE). + */ +#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U) + +/** @brief Check CEC device Own Address Register (OAR) setting. + * OAR address is written in a 15-bit field within CEC_CFGR register. + * @param __ADDRESS__ CEC own address. + * @retval Test result (TRUE or FALSE). + */ +#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU) + +/** @brief Check CEC initiator or destination logical address setting. + * Initiator and destination addresses are coded over 4 bits. + * @param __ADDRESS__ CEC initiator or logical address. + * @retval Test result (TRUE or FALSE). + */ +#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU) +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CEC_Private_Functions CEC Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* CEC */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxxHAL_CEC_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_conf_template.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_conf_template.h new file mode 100644 index 00000000000..9895a378988 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_conf_template.h @@ -0,0 +1,507 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32h7rsxx_hal_conf.h. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_CONF_H +#define STM32H7RSxx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_CEC_MODULE_ENABLED +#define HAL_CORDIC_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED +#define HAL_DCMIPP_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_DMA2D_MODULE_ENABLED +#define HAL_DTS_MODULE_ENABLED +#define HAL_ETH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_FDCAN_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GFXMMU_MODULE_ENABLED +#define HAL_GFXTIM_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_GPU2D_MODULE_ENABLED +#define HAL_HASH_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_I3C_MODULE_ENABLED +#define HAL_ICACHE_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_JPEG_MODULE_ENABLED +#define HAL_LPTIM_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED +#define HAL_MCE_MODULE_ENABLED +#define HAL_MDF_MODULE_ENABLED +#define HAL_MMC_MODULE_ENABLED +#define HAL_NAND_MODULE_ENABLED +#define HAL_NOR_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_PKA_MODULE_ENABLED +#define HAL_PSSI_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RAMECC_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SAI_MODULE_ENABLED +#define HAL_SD_MODULE_ENABLED +#define HAL_SDRAM_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_SMBUS_MODULE_ENABLED +#define HAL_SPDIFRX_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED +#define HAL_XSPI_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 24000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up (in ms) */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low-power oscillator (CSI) default value. + * This value is the default CSI range value after Reset. + */ +#if !defined (CSI_VALUE) +#define CSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* CSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB OTG FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB OTG FS/RNG in Hz. + The real value my vary depending on manufacturing process variations. */ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz. + Value of the Internal Low Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* LSI_VALUE */ + +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up (in ms) */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for digital audio interfaces: SPI/I2S, SAI and ADF + * This value is used by the RCC HAL module to provide the digital audio interfaces + * frequency. This clock source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 48000UL /*!< Value of the external clock source in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32h7rsxx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_MDF_REGISTER_CALLBACKS 0U +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U +#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ + +#define USE_SPI_CRC 1U + +/* ################## CRYP peripheral configuration ########################## */ + +/** + * @brief For code optimization purpose, uncomment and set to "1U" the USE_HAL_CRYP_ONLY or USE_HAL_SAES_ONLY, + * to use only one peripheral. Both defines cannot be set to "1U" at the same time. + */ + + +/* #define USE_HAL_CRYP_ONLY 1U */ +/* #define USE_HAL_SAES_ONLY 0U */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 0U + +/* ################## HASH peripheral configuration ########################## */ + +#define USE_HAL_HASH_SUSPEND_RESUME 0U + +/* ################## SDMMC peripheral configuration ######################### */ + +#define USE_SD_TRANSCEIVER 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32h7rsxx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32h7rsxx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32h7rsxx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32h7rsxx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32h7rsxx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED +#include "stm32h7rsxx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED +#include "stm32h7rsxx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32h7rsxx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32h7rsxx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DCMIPP_MODULE_ENABLED +#include "stm32h7rsxx_hal_dcmipp.h" +#endif /* HAL_DCMIPP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED +#include "stm32h7rsxx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED +#include "stm32h7rsxx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED +#include "stm32h7rsxx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32h7rsxx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32h7rsxx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32h7rsxx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED +#include "stm32h7rsxx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_GFXTIM_MODULE_ENABLED +#include "stm32h7rsxx_hal_gfxtim.h" +#endif /* HAL_GFXTIM_MODULE_ENABLED */ + +#ifdef HAL_GPU2D_MODULE_ENABLED +#include "stm32h7rsxx_hal_gpu2d.h" +#endif /* HAL_GPU2D_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED +#include "stm32h7rsxx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32h7rsxx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32h7rsxx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED +#include "stm32h7rsxx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_I3C_MODULE_ENABLED +#include "stm32h7rsxx_hal_i3c.h" +#endif /* HAL_I3C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED +#include "stm32h7rsxx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32h7rsxx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32h7rsxx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED +#include "stm32h7rsxx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32h7rsxx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32h7rsxx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MCE_MODULE_ENABLED +#include "stm32h7rsxx_hal_mce.h" +#endif /* HAL_MCE_MODULE_ENABLED */ + +#ifdef HAL_MDF_MODULE_ENABLED +#include "stm32h7rsxx_hal_mdf.h" +#endif /* HAL_MDF_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED +#include "stm32h7rsxx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32h7rsxx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32h7rsxx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32h7rsxx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED +#include "stm32h7rsxx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED +#include "stm32h7rsxx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32h7rsxx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMECC_MODULE_ENABLED +#include "stm32h7rsxx_hal_ramecc.h" +#endif /* HAL_RAMECC_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32h7rsxx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32h7rsxx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32h7rsxx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED +#include "stm32h7rsxx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED +#include "stm32h7rsxx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32h7rsxx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32h7rsxx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED +#include "stm32h7rsxx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32h7rsxx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32h7rsxx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32h7rsxx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32h7rsxx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32h7rsxx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32h7rsxx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED +#include "stm32h7rsxx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_CONF_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cordic.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cordic.h new file mode 100644 index 00000000000..2a9b4933dbf --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cordic.h @@ -0,0 +1,609 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_cordic.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the CORDIC firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_CORDIC_H +#define STM32H7RSxx_HAL_CORDIC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +#if defined(CORDIC) +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup CORDIC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORDIC_Exported_Types CORDIC Exported Types + * @{ + */ + +/** + * @brief CORDIC HAL State Structure definition + */ +typedef enum +{ + HAL_CORDIC_STATE_RESET = 0x00U, /*!< CORDIC not yet initialized or disabled */ + HAL_CORDIC_STATE_READY = 0x01U, /*!< CORDIC initialized and ready for use */ + HAL_CORDIC_STATE_BUSY = 0x02U, /*!< CORDIC internal process is ongoing */ + HAL_CORDIC_STATE_ERROR = 0x03U /*!< CORDIC error state */ +} HAL_CORDIC_StateTypeDef; + +/** + * @brief CORDIC Handle Structure definition + */ +#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 +typedef struct __CORDIC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ +{ + CORDIC_TypeDef *Instance; /*!< Register base address */ + + const int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */ + + int32_t *pOutBuff; /*!< Pointer to CORDIC output data buffer */ + + uint32_t NbCalcToOrder; /*!< Remaining number of calculation to order */ + + uint32_t NbCalcToGet; /*!< Remaining number of calculation result to get */ + + uint32_t DMADirection; /*!< Direction of CORDIC DMA transfers */ + + DMA_HandleTypeDef *hdmaIn; /*!< CORDIC peripheral input data DMA handle parameters */ + + DMA_HandleTypeDef *hdmaOut; /*!< CORDIC peripheral output data DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< CORDIC locking object */ + + __IO HAL_CORDIC_StateTypeDef State; /*!< CORDIC state */ + + __IO uint32_t ErrorCode; /*!< CORDIC peripheral error code + This parameter can be a value of @ref CORDIC_Error_Code */ + +#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 + void (* ErrorCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC error callback */ + void (* CalculateCpltCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC calculate complete callback */ + + void (* MspInitCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC Msp Init callback */ + void (* MspDeInitCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC Msp DeInit callback */ + +#endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */ + +} CORDIC_HandleTypeDef; + +/** + * @brief CORDIC Config Structure definition + */ +typedef struct +{ + uint32_t Function; /*!< Function + This parameter can be a value of @ref CORDIC_Function */ + + uint32_t Scale; /*!< Scaling factor + This parameter can be a value of @ref CORDIC_Scale */ + + uint32_t InSize; /*!< Width of input data + This parameter can be a value of @ref CORDIC_In_Size */ + + uint32_t OutSize; /*!< Width of output data + This parameter can be a value of @ref CORDIC_Out_Size */ + + uint32_t NbWrite; /*!< Number of 32-bit write expected for one calculation + This parameter can be a value of @ref CORDIC_Nb_Write */ + + uint32_t NbRead; /*!< Number of 32-bit read expected after one calculation + This parameter can be a value of @ref CORDIC_Nb_Read */ + + uint32_t Precision; /*!< Number of cycles for calculation + This parameter can be a value of @ref CORDIC_Precision_In_Cycles_Number */ + +} CORDIC_ConfigTypeDef; + +#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 +/** + * @brief HAL CORDIC Callback ID enumeration definition + */ +typedef enum +{ + HAL_CORDIC_ERROR_CB_ID = 0x00U, /*!< CORDIC error callback ID */ + HAL_CORDIC_CALCULATE_CPLT_CB_ID = 0x01U, /*!< CORDIC calculate complete callback ID */ + + HAL_CORDIC_MSPINIT_CB_ID = 0x02U, /*!< CORDIC MspInit callback ID */ + HAL_CORDIC_MSPDEINIT_CB_ID = 0x03U, /*!< CORDIC MspDeInit callback ID */ + +} HAL_CORDIC_CallbackIDTypeDef; + +/** + * @brief HAL CORDIC Callback pointer definition + */ +typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< pointer to a CORDIC callback function */ + +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants + * @{ + */ + +/** @defgroup CORDIC_Error_Code CORDIC Error code + * @{ + */ +#define HAL_CORDIC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_CORDIC_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Wrong parameter error */ +#define HAL_CORDIC_ERROR_NOT_READY ((uint32_t)0x00000002U) /*!< Peripheral not ready */ +#define HAL_CORDIC_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */ +#define HAL_CORDIC_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA error */ +#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 +#define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup CORDIC_Function CORDIC Function + * @{ + */ +#define CORDIC_FUNCTION_COSINE (0x00000000U) /*!< Cosine */ +#define CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0)) /*!< Sine */ +#define CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1)) /*!< Phase */ +#define CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0)) /*!< Modulus */ +#define CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2)) /*!< Arctangent */ +#define CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0)) /*!< Hyperbolic Cosine */ +#define CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1)) /*!< Hyperbolic Sine */ +#define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */ +#define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */ +#define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */ +/** + * @} + */ + +/** @defgroup CORDIC_Precision_In_Cycles_Number CORDIC Precision in Cycles Number + * @{ + */ +/* Note: 1 cycle corresponds to 4 algorithm iterations */ +#define CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1)) +#define CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2)) +#define CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) +#define CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\ + | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3)) +#define CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1)) +#define CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2)) +#define CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) +#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\ + |CORDIC_CSR_PRECISION_0)) +/** + * @} + */ + +/** @defgroup CORDIC_Scale CORDIC Scaling factor + * @{ + */ +/* Scale factor value 'n' implies that the input data have been multiplied + by a factor 2exp(-n), and/or the output data need to be multiplied by 2exp(n). */ +#define CORDIC_SCALE_0 (0x00000000U) +#define CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0)) +#define CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1)) +#define CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0)) +#define CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2)) +#define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0)) +#define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1)) +#define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0)) +/** + * @} + */ + +/** @defgroup CORDIC_Interrupts_Enable CORDIC Interrupts Enable bit + * @{ + */ +#define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */ +/** + * @} + */ + +/** @defgroup CORDIC_DMAR DMA Read Request Enable bit + * @{ + */ +#define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */ +/** + * @} + */ + +/** @defgroup CORDIC_DMAW DMA Write Request Enable bit + * @{ + */ +#define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */ +/** + * @} + */ + +/** @defgroup CORDIC_Nb_Write CORDIC Number of 32-bit write required for one calculation + * @{ + */ +#define CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one + 32-bit data input (Q1.31 format), or two 16-bit + data input (Q1.15 format) packed in one 32 bits + Data */ +#define CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input + (Q1.31 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_Nb_Read CORDIC Number of 32-bit read required after one calculation + * @{ + */ +#define CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one + 32-bit data output (Q1.31 format), or two 16-bit + data output (Q1.15 format) packed in one 32 bits + Data */ +#define CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output + (Q1.31 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_In_Size CORDIC input data size + * @{ + */ +#define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */ +#define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_Out_Size CORDIC Results Size + * @{ + */ +#define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */ +#define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_Flags CORDIC status flags + * @{ + */ +#define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */ +/** + * @} + */ + +/** @defgroup CORDIC_DMA_Direction CORDIC DMA direction + * @{ + */ +#define CORDIC_DMA_DIR_NONE ((uint32_t)0x00000000U) /*!< DMA direction : none */ +#define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */ +#define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */ +#define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */ +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CORDIC_Exported_Macros CORDIC Exported Macros + * @{ + */ + +/** @brief Reset CORDIC handle state. + * @param __HANDLE__ CORDIC handle + * @retval None + */ +#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 +#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET) +#endif /*USE_HAL_CORDIC_REGISTER_CALLBACKS */ + +/** + * @brief Enable the CORDIC interrupt when result is ready + * @param __HANDLE__ CORDIC handle. + * @param __INTERRUPT__ CORDIC Interrupt. + * This parameter can be one of the following values: + * @arg @ref CORDIC_IT_IEN Enable Interrupt + * @retval None + */ +#define __HAL_CORDIC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__)) + +/** + * @brief Disable the CORDIC interrupt + * @param __HANDLE__ CORDIC handle. + * @param __INTERRUPT__ CORDIC Interrupt. + * This parameter can be one of the following values: + * @arg @ref CORDIC_IT_IEN Enable Interrupt + * @retval None + */ +#define __HAL_CORDIC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__)) + +/** @brief Check whether the specified CORDIC interrupt occurred or not. + Dummy macro as no interrupt status flag. + * @param __HANDLE__ CORDIC handle. + * @param __INTERRUPT__ CORDIC interrupt to check + * @retval SET (interrupt occurred) or RESET (interrupt did not occurred) + */ +#define __HAL_CORDIC_GET_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */ + +/** @brief Clear specified CORDIC interrupt status. Dummy macro as no + interrupt status flag. + * @param __HANDLE__ CORDIC handle. + * @param __INTERRUPT__ CORDIC interrupt to clear + * @retval None + */ +#define __HAL_CORDIC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */ + +/** @brief Check whether the specified CORDIC status flag is set or not. + * @param __HANDLE__ CORDIC handle. + * @param __FLAG__ CORDIC flag to check + * This parameter can be one of the following values: + * @arg @ref CORDIC_FLAG_RRDY Result Ready Flag + * @retval SET (flag is set) or RESET (flag is reset) + */ +#define __HAL_CORDIC_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear specified CORDIC status flag. Dummy macro as no + flag can be cleared. + * @param __HANDLE__ CORDIC handle. + * @param __FLAG__ CORDIC flag to clear + * This parameter can be one of the following values: + * @arg @ref CORDIC_FLAG_RRDY Result Ready Flag + * @retval None + */ +#define __HAL_CORDIC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */ + +/** @brief Check whether the specified CORDIC interrupt is enabled or not. + * @param __HANDLE__ CORDIC handle. + * @param __INTERRUPT__ CORDIC interrupt to check + * This parameter can be one of the following values: + * @arg @ref CORDIC_IT_IEN Enable Interrupt + * @retval FlagStatus + */ +#define __HAL_CORDIC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->CSR) & (__INTERRUPT__)) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup CORDIC_Private_Macros CORDIC Private Macros + * @{ + */ + +/** + * @brief Verify the CORDIC function. + * @param __FUNCTION__ Name of the function. + * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid) + */ +#define IS_CORDIC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == CORDIC_FUNCTION_COSINE) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_SINE) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_PHASE) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_MODULUS) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_ARCTANGENT) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_HCOSINE) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_HSINE) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_HARCTANGENT) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_NATURALLOG) || \ + ((__FUNCTION__) == CORDIC_FUNCTION_SQUAREROOT)) + + +/** + * @brief Verify the CORDIC precision. + * @param __PRECISION__ CORDIC Precision in Cycles Number. + * @retval SET (__PRECISION__ is a valid value) or RESET (__PRECISION__ is invalid) + */ +#define IS_CORDIC_PRECISION(__PRECISION__) (((__PRECISION__) == CORDIC_PRECISION_1CYCLE) || \ + ((__PRECISION__) == CORDIC_PRECISION_2CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_3CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_4CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_5CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_6CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_7CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_8CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_9CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_10CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_11CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_12CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_13CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_14CYCLES) || \ + ((__PRECISION__) == CORDIC_PRECISION_15CYCLES)) + +/** + * @brief Verify the CORDIC scaling factor. + * @param __SCALE__ Number of cycles for calculation, 1 cycle corresponding to 4 algorithm iterations. + * @retval SET (__SCALE__ is a valid value) or RESET (__SCALE__ is invalid) + */ +#define IS_CORDIC_SCALE(__SCALE__) (((__SCALE__) == CORDIC_SCALE_0) || \ + ((__SCALE__) == CORDIC_SCALE_1) || \ + ((__SCALE__) == CORDIC_SCALE_2) || \ + ((__SCALE__) == CORDIC_SCALE_3) || \ + ((__SCALE__) == CORDIC_SCALE_4) || \ + ((__SCALE__) == CORDIC_SCALE_5) || \ + ((__SCALE__) == CORDIC_SCALE_6) || \ + ((__SCALE__) == CORDIC_SCALE_7)) + +/** + * @brief Verify the CORDIC number of 32-bits write expected for one calculation. + * @param __NBWRITE__ Number of 32-bits write expected for one calculation. + * @retval SET (__NBWRITE__ is a valid value) or RESET (__NBWRITE__ is invalid) + */ +#define IS_CORDIC_NBWRITE(__NBWRITE__) (((__NBWRITE__) == CORDIC_NBWRITE_1) || \ + ((__NBWRITE__) == CORDIC_NBWRITE_2)) + +/** + * @brief Verify the CORDIC number of 32-bits read expected after one calculation. + * @param __NBREAD__ Number of 32-bits read expected after one calculation. + * @retval SET (__NBREAD__ is a valid value) or RESET (__NBREAD__ is invalid) + */ +#define IS_CORDIC_NBREAD(__NBREAD__) (((__NBREAD__) == CORDIC_NBREAD_1) || \ + ((__NBREAD__) == CORDIC_NBREAD_2)) + +/** + * @brief Verify the CORDIC input data size for one calculation. + * @param __INSIZE__ input data size for one calculation. + * @retval SET (__INSIZE__ is a valid value) or RESET (__INSIZE__ is invalid) + */ +#define IS_CORDIC_INSIZE(__INSIZE__) (((__INSIZE__) == CORDIC_INSIZE_32BITS) || \ + ((__INSIZE__) == CORDIC_INSIZE_16BITS)) + +/** + * @brief Verify the CORDIC output data size for one calculation. + * @param __OUTSIZE__ output data size for one calculation. + * @retval SET (__OUTSIZE__ is a valid value) or RESET (__OUTSIZE__ is invalid) + */ +#define IS_CORDIC_OUTSIZE(__OUTSIZE__) (((__OUTSIZE__) == CORDIC_OUTSIZE_32BITS) || \ + ((__OUTSIZE__) == CORDIC_OUTSIZE_16BITS)) + +/** + * @brief Verify the CORDIC DMA transfer Direction. + * @param __DMADIR__ DMA transfer direction. + * @retval SET (__DMADIR__ is a valid value) or RESET (__DMADIR__ is invalid) + */ +#define IS_CORDIC_DMA_DIRECTION(__DMADIR__) (((__DMADIR__) == CORDIC_DMA_DIR_IN) || \ + ((__DMADIR__) == CORDIC_DMA_DIR_OUT) || \ + ((__DMADIR__) == CORDIC_DMA_DIR_IN_OUT)) + +/** + * @} + */ + +/** @addtogroup CORDIC_Exported_Functions + * @{ + */ +/* Exported functions ------------------------------------------------------- */ + +/** @addtogroup CORDIC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_CORDIC_Init(CORDIC_HandleTypeDef *hcordic); +HAL_StatusTypeDef HAL_CORDIC_DeInit(CORDIC_HandleTypeDef *hcordic); +void HAL_CORDIC_MspInit(CORDIC_HandleTypeDef *hcordic); +void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic); + +#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, + pCORDIC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID); +/** + * @} + */ + +/** @addtogroup CORDIC_Exported_Functions_Group2 + * @{ + */ +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig); +HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t Timeout); +HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t Timeout); +HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc); +HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t DMADirection); +/** + * @} + */ + +/** @addtogroup CORDIC_Exported_Functions_Group3 + * @{ + */ +/* Callback functions *********************************************************/ +void HAL_CORDIC_ErrorCallback(CORDIC_HandleTypeDef *hcordic); +void HAL_CORDIC_CalculateCpltCallback(CORDIC_HandleTypeDef *hcordic); +/** + * @} + */ + +/** @addtogroup CORDIC_Exported_Functions_Group4 + * @{ + */ +/* IRQ handler management *****************************************************/ +void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic); +/** + * @} + */ + +/** @addtogroup CORDIC_Exported_Functions_Group5 + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic); +uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* CORDIC */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_CORDIC_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cortex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cortex.h new file mode 100644 index 00000000000..6dee7e4d952 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cortex.h @@ -0,0 +1,409 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_CORTEX_H +#define STM32H7RSxx_HAL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types CORTEX Exported Types + * @{ + */ + +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. + */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +} MPU_Region_InitTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 7U /*!< 0 bit for pre-emption priority, + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 6U /*!< 1 bit for pre-emption priority, + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 5U /*!< 2 bits for pre-emption priority, + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 4U /*!< 3 bits for pre-emption priority, + 1 bit for subpriority */ +#define NVIC_PRIORITYGROUP_4 3U /*!< 4 bits for pre-emption priority, + 0 bit for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0U +#define SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk + +/** + * @} + */ + +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0U +#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk +#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk +#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE 1U +#define MPU_REGION_DISABLE 0U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE 0U +#define MPU_INSTRUCTION_ACCESS_DISABLE 1U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_NOT_SHAREABLE 0U +#define MPU_ACCESS_SHAREABLE 1U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE 1U +#define MPU_ACCESS_NOT_CACHEABLE 0U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE 1U +#define MPU_ACCESS_NOT_BUFFERABLE 0U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 0U +#define MPU_TEX_LEVEL1 1U +#define MPU_TEX_LEVEL2 2U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B 0x04U +#define MPU_REGION_SIZE_64B 0x05U +#define MPU_REGION_SIZE_128B 0x06U +#define MPU_REGION_SIZE_256B 0x07U +#define MPU_REGION_SIZE_512B 0x08U +#define MPU_REGION_SIZE_1KB 0x09U +#define MPU_REGION_SIZE_2KB 0x0AU +#define MPU_REGION_SIZE_4KB 0x0BU +#define MPU_REGION_SIZE_8KB 0x0CU +#define MPU_REGION_SIZE_16KB 0x0DU +#define MPU_REGION_SIZE_32KB 0x0EU +#define MPU_REGION_SIZE_64KB 0x0FU +#define MPU_REGION_SIZE_128KB 0x10U +#define MPU_REGION_SIZE_256KB 0x11U +#define MPU_REGION_SIZE_512KB 0x12U +#define MPU_REGION_SIZE_1MB 0x13U +#define MPU_REGION_SIZE_2MB 0x14U +#define MPU_REGION_SIZE_4MB 0x15U +#define MPU_REGION_SIZE_8MB 0x16U +#define MPU_REGION_SIZE_16MB 0x17U +#define MPU_REGION_SIZE_32MB 0x18U +#define MPU_REGION_SIZE_64MB 0x19U +#define MPU_REGION_SIZE_128MB 0x1AU +#define MPU_REGION_SIZE_256MB 0x1BU +#define MPU_REGION_SIZE_512MB 0x1CU +#define MPU_REGION_SIZE_1GB 0x1DU +#define MPU_REGION_SIZE_2GB 0x1EU +#define MPU_REGION_SIZE_4GB 0x1FU +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS 0U +#define MPU_REGION_PRIV_RW 1U +#define MPU_REGION_PRIV_RW_URO 2U +#define MPU_REGION_FULL_ACCESS 3U +#define MPU_REGION_PRIV_RO 5U +#define MPU_REGION_PRIV_RO_URO 6U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 0U +#define MPU_REGION_NUMBER1 1U +#define MPU_REGION_NUMBER2 2U +#define MPU_REGION_NUMBER3 3U +#define MPU_REGION_NUMBER4 4U +#define MPU_REGION_NUMBER5 5U +#define MPU_REGION_NUMBER6 6U +#define MPU_REGION_NUMBER7 7U +#define MPU_REGION_NUMBER8 8U +#define MPU_REGION_NUMBER9 9U +#define MPU_REGION_NUMBER10 10U +#define MPU_REGION_NUMBER11 11U +#define MPU_REGION_NUMBER12 12U +#define MPU_REGION_NUMBER13 13U +#define MPU_REGION_NUMBER14 14U +#define MPU_REGION_NUMBER15 15U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and Configuration functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *pMPU_RegionInit); +void HAL_CORTEX_ClearEvent(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(__GROUP__) (((__GROUP__) == NVIC_PRIORITYGROUP_0) || \ + ((__GROUP__) == NVIC_PRIORITYGROUP_1) || \ + ((__GROUP__) == NVIC_PRIORITYGROUP_2) || \ + ((__GROUP__) == NVIC_PRIORITYGROUP_3) || \ + ((__GROUP__) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(__PRIO__, __PRIOGRP__) (((__PRIO__) < (1uL << __NVIC_PRIO_BITS)) && \ + ((__PRIO__) < (0x1uL << (0x07u - __PRIOGRP__)))) + +#define IS_NVIC_SUB_PRIORITY(__PRIO__, __PRIOGRP__) \ + ((__PRIOGRP__ < (0x07u - __NVIC_PRIO_BITS)) ?\ + ((__PRIO__) < (1u)): \ + ((__PRIO__) < (0x1uL << (__PRIOGRP__ - (0x07u - __NVIC_PRIO_BITS))))) + +#define IS_NVIC_DEVICE_IRQ(__IRQ__) ((__IRQ__) > SysTick_IRQn) + +#define IS_NVIC_PRIO_INTERRUPT(__IT__) (((__IT__) > HardFault_IRQn) && ((__IT__) != DebugMonitor_IRQn)) + +#define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \ + ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#define IS_MPU_REGION_ENABLE(__STATE__) (((__STATE__) == MPU_REGION_ENABLE) || \ + ((__STATE__) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(__STATE__) (((__STATE__) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((__STATE__) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(__STATE__) (((__STATE__) == MPU_ACCESS_SHAREABLE) || \ + ((__STATE__) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(__STATE__) (((__STATE__) == MPU_ACCESS_CACHEABLE) || \ + ((__STATE__) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(__STATE__) (((__STATE__) == MPU_ACCESS_BUFFERABLE) || \ + ((__STATE__) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(__TYPE__) (((__TYPE__) == MPU_TEX_LEVEL0) || \ + ((__TYPE__) == MPU_TEX_LEVEL1) || \ + ((__TYPE__) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(__TYPE__) (((__TYPE__) == MPU_REGION_NO_ACCESS) || \ + ((__TYPE__) == MPU_REGION_PRIV_RW) || \ + ((__TYPE__) == MPU_REGION_PRIV_RW_URO) || \ + ((__TYPE__) == MPU_REGION_FULL_ACCESS) || \ + ((__TYPE__) == MPU_REGION_PRIV_RO) || \ + ((__TYPE__) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(__NUMBER__) ((__NUMBER__) <= MPU_REGION_NUMBER15) + +#define IS_MPU_REGION_SIZE(__SIZE__) (((__SIZE__) == MPU_REGION_SIZE_32B) || \ + ((__SIZE__) == MPU_REGION_SIZE_64B) || \ + ((__SIZE__) == MPU_REGION_SIZE_128B) || \ + ((__SIZE__) == MPU_REGION_SIZE_256B) || \ + ((__SIZE__) == MPU_REGION_SIZE_512B) || \ + ((__SIZE__) == MPU_REGION_SIZE_1KB) || \ + ((__SIZE__) == MPU_REGION_SIZE_2KB) || \ + ((__SIZE__) == MPU_REGION_SIZE_4KB) || \ + ((__SIZE__) == MPU_REGION_SIZE_8KB) || \ + ((__SIZE__) == MPU_REGION_SIZE_16KB) || \ + ((__SIZE__) == MPU_REGION_SIZE_32KB) || \ + ((__SIZE__) == MPU_REGION_SIZE_64KB) || \ + ((__SIZE__) == MPU_REGION_SIZE_128KB) || \ + ((__SIZE__) == MPU_REGION_SIZE_256KB) || \ + ((__SIZE__) == MPU_REGION_SIZE_512KB) || \ + ((__SIZE__) == MPU_REGION_SIZE_1MB) || \ + ((__SIZE__) == MPU_REGION_SIZE_2MB) || \ + ((__SIZE__) == MPU_REGION_SIZE_4MB) || \ + ((__SIZE__) == MPU_REGION_SIZE_8MB) || \ + ((__SIZE__) == MPU_REGION_SIZE_16MB) || \ + ((__SIZE__) == MPU_REGION_SIZE_32MB) || \ + ((__SIZE__) == MPU_REGION_SIZE_64MB) || \ + ((__SIZE__) == MPU_REGION_SIZE_128MB) || \ + ((__SIZE__) == MPU_REGION_SIZE_256MB) || \ + ((__SIZE__) == MPU_REGION_SIZE_512MB) || \ + ((__SIZE__) == MPU_REGION_SIZE_1GB) || \ + ((__SIZE__) == MPU_REGION_SIZE_2GB) || \ + ((__SIZE__) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(__SUBREGION__) ((__SUBREGION__) < (uint16_t)0x00FFU) + +#define IS_MPU_ADDRESS_MULTIPLE_SIZE(__ADDRESS__, __SIZE__) (((__ADDRESS__) & ((1<<(__SIZE__+1U))- 1U)) == 0U) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_CORTEX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_crc.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_crc.h new file mode 100644 index 00000000000..dfce8c08553 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_crc.h @@ -0,0 +1,342 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_crc.h + * @author MCD Application Team + * @brief Header file of CRC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_CRC_H +#define STM32H7RSxx_HAL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Types CRC Exported Types + * @{ + */ + +/** + * @brief CRC HAL State Structure definition + */ +typedef enum +{ + HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */ + HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */ + HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */ + HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */ + HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */ +} HAL_CRC_StateTypeDef; + +/** + * @brief CRC Init Structure definition + */ +typedef struct +{ + uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. + If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default + X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + + X^4 + X^2+ X +1. + In that case, there is no need to set GeneratingPolynomial field. + If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and + CRCLength fields must be set. */ + + uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. + If set to DEFAULT_INIT_VALUE_ENABLE, resort to default + 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If + otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ + + uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree + respectively equal to 7, 8, 16 or 32. This field is written in normal, + representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 + is written 0x65. No need to specify it if DefaultPolynomialUse is set to + DEFAULT_POLYNOMIAL_ENABLE. */ + + uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length. + Value can be either one of + @arg @ref CRC_POLYLENGTH_32B (32-bit CRC), + @arg @ref CRC_POLYLENGTH_16B (16-bit CRC), + @arg @ref CRC_POLYLENGTH_8B (8-bit CRC), + @arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */ + + uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse + is set to DEFAULT_INIT_VALUE_ENABLE. */ + + uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. + Can be either one of the following values + @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion + @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D + becomes 0x58D43CB2 + @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, + 0x1A2B3C4D becomes 0xD458B23C + @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D + becomes 0xB23CD458 */ + + uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. + Can be either + @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, + @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted + into 0x22CC4488 */ +} CRC_InitTypeDef; + +/** + * @brief CRC Handle Structure definition + */ +typedef struct +{ + CRC_TypeDef *Instance; /*!< Register base address */ + + CRC_InitTypeDef Init; /*!< CRC configuration parameters */ + + HAL_LockTypeDef Lock; /*!< CRC Locking object */ + + __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */ + + uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. + Can be either + @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes + (8-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of + half-words (16-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words + (32-bit data) + + Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization + error must occur if InputBufferFormat is not one of the three values listed + above */ +} CRC_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Constants CRC Exported Constants + * @{ + */ + +/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial + * @{ + */ +#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */ +/** + * @} + */ + +/** @defgroup CRC_Default_InitValue Default CRC computation initialization value + * @{ + */ +#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */ +/** + * @} + */ + +/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used + * @{ + */ +#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */ +#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */ +/** + * @} + */ + +/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used + * @{ + */ +#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */ +#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */ +/** + * @} + */ + +/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral + * @{ + */ +#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */ +#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */ +#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */ +#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */ +/** + * @} + */ + +/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions + * @{ + */ +#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */ +#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */ +#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */ +#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */ +/** + * @} + */ + +/** @defgroup CRC_Input_Buffer_Format Input Buffer Format + * @{ + */ +/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but + * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set + * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for + * the CRC APIs to provide a correct result */ +#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */ +#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */ +#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */ +#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CRC_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @brief Reset CRC handle state. + * @param __HANDLE__ CRC handle. + * @retval None + */ +#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) + +/** + * @brief Reset CRC Data Register. + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) + +/** + * @brief Set CRC INIT non-default value + * @param __HANDLE__ CRC handle + * @param __INIT__ 32-bit initial value + * @retval None + */ +#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) + +/** + * @brief Store data in the Independent Data (ID) register. + * @param __HANDLE__ CRC handle + * @param __VALUE__ Value to be stored in the ID register + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits + * @retval None + */ +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) + +/** + * @brief Return the data stored in the Independent Data (ID) register. + * @param __HANDLE__ CRC handle + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits + * @retval Value of the ID register + */ +#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) +/** + * @} + */ + + +/* Private macros --------------------------------------------------------*/ +/** @defgroup CRC_Private_Macros CRC Private Macros + * @{ + */ + +#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \ + ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE)) + +#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \ + ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) + +#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \ + ((LENGTH) == CRC_POLYLENGTH_16B) || \ + ((LENGTH) == CRC_POLYLENGTH_8B) || \ + ((LENGTH) == CRC_POLYLENGTH_7B)) + +#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \ + ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \ + ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS)) + +/** + * @} + */ + +/* Include CRC HAL Extended module */ +#include "stm32h7rsxx_hal_crc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc); +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/* Peripheral Control functions ***********************************************/ +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +/** + * @} + */ + +/* Peripheral State and Error functions ***************************************/ +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @{ + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_CRC_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_crc_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_crc_ex.h new file mode 100644 index 00000000000..3602d570516 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_crc_ex.h @@ -0,0 +1,150 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_crc_ex.h + * @author MCD Application Team + * @brief Header file of CRC HAL extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_CRC_EX_H +#define STM32H7RSxx_HAL_CRC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup CRCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants + * @{ + */ + +/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes + * @{ + */ +#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */ +#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */ +/** + * @} + */ + +/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes + * @{ + */ +#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */ +#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros + * @{ + */ + +/** + * @brief Set CRC output reversal + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) + +/** + * @brief Unset CRC output reversal + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) + +/** + * @brief Set CRC non-default polynomial + * @param __HANDLE__ CRC handle + * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial + * @retval None + */ +#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros + * @{ + */ + +#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_WORD)) + +#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \ + ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CRCEx_Exported_Functions + * @{ + */ + +/** @addtogroup CRCEx_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength); +HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode); +HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_CRC_EX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cryp.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cryp.h new file mode 100644 index 00000000000..c2520692125 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cryp.h @@ -0,0 +1,944 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_cryp.h + * @author MCD Application Team + * @brief Header file of CRYP HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_CRYP_H +#define STM32H7RSxx_HAL_CRYP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(USE_HAL_SAES_ONLY) && (USE_HAL_SAES_ONLY == 1U) +#if !defined(USE_HAL_CRYP_ONLY) +#define USE_HAL_CRYP_ONLY 0U +#elif (USE_HAL_CRYP_ONLY == 1U) +#error ' USE_HAL_CRYP_ONLY and USE_HAL_SAES_ONLY cannot be set both to 1U ' +#endif /* defined (USE_HAL_CRYP_ONLY) */ +#endif /* defined (USE_HAL_SAES_ONLY) */ + +#if defined(USE_HAL_CRYP_ONLY) && (USE_HAL_CRYP_ONLY == 1U) +#if !defined(USE_HAL_SAES_ONLY) +#define USE_HAL_SAES_ONLY 0U +#elif (USE_HAL_SAES_ONLY == 1U) +#error ' USE_HAL_CRYP_ONLY and USE_HAL_SAES_ONLY cannot be set both to 1U ' +#endif /* defined (USE_HAL_SAES_ONLY) */ +#endif /* defined (USE_HAL_CRYP_ONLY) */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#if defined (CRYP) +/** @addtogroup CRYP + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CRYP_Exported_Types CRYP Exported Types + * @{ + */ + +/** + * @brief CRYP Init Structure definition + */ + +typedef struct +{ + uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string. + This parameter can be a value of @ref CRYP_Data_Type */ + uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1. + This parameter can be a value of @ref CRYP_Key_Size */ + uint32_t *pKey; /*!< The key used for encryption/decryption */ + uint32_t *pInitVect; /*!< The initialization vector used also as initialization + counter in CTR mode */ + uint32_t Algorithm; /*!< AES Algorithm ECB/CBC/CTR/GCM or CCM + This parameter can be a value of @ref CRYP_CR_ALGOMODE */ + uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication, + GCM : also known as Additional Authentication Data + CCM : named B1 composed of the associated data length and Associated Data. */ + uint32_t HeaderSize; /*!< The size of header buffer in word */ + uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */ + uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ + uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value + of @ref CRYP_Header_Width_Unit */ + uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, + to configure Key and Initialization + Vector only once and to skip configuration for consecutive processing. + This parameter can be a value of @ref CRYP_Configuration_Skip */ + uint32_t KeyMode; /*!< Key mode selection, this parameter can be a value of @ref CRYP_Key_Mode */ + uint32_t KeySelect; /*!< Only for SAES : Key selection, this parameter can be a value + of @ref CRYP_Key_Select */ + +} CRYP_ConfigTypeDef; + + +/** + * @brief CRYP State Structure definition + */ + +typedef enum +{ + HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */ + HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */ + HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP BUSY, internal processing is ongoing */ +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + HAL_CRYP_STATE_SUSPENDED = 0x03U, /*!< CRYP suspended */ +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ +} HAL_CRYP_STATETypeDef; + + +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) +/** + * @brief HAL CRYP mode suspend definitions + */ + +typedef enum +{ + HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP processing suspension not requested */ + HAL_CRYP_SUSPEND = 0x01U /*!< CRYP processing suspension requested */ +} HAL_SuspendTypeDef; +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + +/** + * @brief CRYP handle Structure definition + */ + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) +typedef struct __CRYP_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ +{ + void *Instance; /*!< CRYP or SAES registers base address */ + + CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */ + + uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) + buffer */ + + uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) + buffer */ + + __IO uint16_t CrypHeaderCount; /*!< Counter of header data */ + + __IO uint16_t CrypInCount; /*!< Counter of input data */ + + __IO uint16_t CrypOutCount; /*!< Counter of output data */ + + uint16_t Size; /*!< length of input data in word or in byte, + according to DataWidthUnit */ + + uint32_t Phase; /*!< CRYP peripheral phase */ + + DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */ + + DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< CRYP locking object */ + + __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ + + __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */ + + uint32_t Version; /*!< CRYP1 IP version*/ + + uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when + configuration can be skipped */ + + uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored + for a single signature computation after several + messages processing */ + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */ + void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */ + void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */ + + void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */ + void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */ + +#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ + +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + + __IO HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */ + + CRYP_ConfigTypeDef Init_saved; /*!< copy of CRYP required parameters when processing + is suspended */ + + uint32_t *pCrypInBuffPtr_saved; /*!< copy of CRYP input pointer when processing + is suspended */ + + uint32_t *pCrypOutBuffPtr_saved; /*!< copy of CRYP output pointer when processing + is suspended */ + + uint32_t CrypInCount_saved; /*!< copy of CRYP input data counter when processing + is suspended */ + + uint32_t CrypOutCount_saved; /*!< copy of CRYP output data counter when processing + is suspended */ + + uint32_t Phase_saved; /*!< copy of CRYP authentication phase when processing + is suspended */ + + __IO HAL_CRYP_STATETypeDef State_saved; /*!< copy of CRYP peripheral state when processing + is suspended */ + + uint32_t IV_saved[4]; /*!< copy of Initialisation Vector registers */ + + uint32_t SUSPxR_saved[16]; /*!< copy of suspension registers */ + + uint32_t CR_saved; /*!< copy of CRYP control register when processing + is suspended*/ + + uint32_t Key_saved[8]; /*!< copy of key registers */ + + uint16_t Size_saved; /*!< copy of input buffer size */ + + uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing + is suspended */ + + uint32_t SizesSum_saved; /*!< copy of SizesSum when processing is suspended */ + + uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */ + + uint32_t SuspendedProcessing; /*< Report whether interruption or DMA-mode processing + was suspended */ +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + +} CRYP_HandleTypeDef; + + +/** + * @} + */ + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition + * @brief HAL CRYP Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x01U, /*!< CRYP Input FIFO transfer completed callback ID */ + HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Output FIFO transfer completed callback ID */ + HAL_CRYP_ERROR_CB_ID = 0x03U, /*!< CRYP Error callback ID */ + HAL_CRYP_MSPINIT_CB_ID = 0x04U, /*!< CRYP MspInit callback ID */ + HAL_CRYP_MSPDEINIT_CB_ID = 0x05U /*!< CRYP MspDeInit callback ID */ + +} HAL_CRYP_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition + * @brief HAL CRYP Callback pointer definition + * @{ + */ + +typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */ + +/** + * @} + */ + +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRYP_Exported_Constants CRYP Exported Constants + * @{ + */ + +/** @defgroup CRYP_Error_Definition CRYP Error Definition + * @{ + */ +#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */ +#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */ +#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */ +#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */ +#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */ +#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */ +#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) +#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */ +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +#define HAL_CRYP_ERROR_KEY 0x00000100U /*!< Key error */ +#define HAL_CRYP_ERROR_RNG 0x00000200U /*!< RNG error */ + +/** + * @} + */ + + +/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit + * @{ + */ + +#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */ +#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */ + +/** + * @} + */ + +/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit + * @{ + */ + +#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */ +#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */ + +/** + * @} + */ + +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +/** @defgroup SAES_CR_CHMOD SAES CHMOD Selection + * @{ + */ + +#define SAES_CR_CHMOD_AES_ECB ((uint32_t)0x00000000) +#define SAES_CR_CHMOD_AES_CBC (SAES_CR_CHMOD_0) +#define SAES_CR_CHMOD_AES_CTR (SAES_CR_CHMOD_1) +#define SAES_CR_CHMOD_AES_GCM (SAES_CR_CHMOD_0 | SAES_CR_CHMOD_1) +#define SAES_CR_CHMOD_AES_CCM (SAES_CR_CHMOD_2) + +/** + * @} + */ +#endif /* USE_HAL_SAES_ONLY */ + +/** @defgroup CRYP_CR_ALGOMODE CRYP Algorithm Mode + * @{ + */ + +#define CRYP_AES_ECB (CRYP_CR_ALGOMODE_2) +#define CRYP_AES_CBC (CRYP_CR_ALGOMODE_0 | CRYP_CR_ALGOMODE_2) +#define CRYP_AES_CTR (CRYP_CR_ALGOMODE_1 | CRYP_CR_ALGOMODE_2) +#define CRYP_AES_KEY (CRYP_CR_ALGOMODE_0 | CRYP_CR_ALGOMODE_1 | CRYP_CR_ALGOMODE_2) +#define CRYP_AES_GCM (CRYP_CR_ALGOMODE_3) +#define CRYP_AES_CCM (CRYP_CR_ALGOMODE_0 | CRYP_CR_ALGOMODE_3) + +/** + * @} + */ + +/** @defgroup CRYP_Key_Size CRYP Key Size + * @{ + */ + +#define CRYP_KEYSIZE_128B 0x00000000U +#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0 +#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1 + +/** + * @} + */ + +/** @defgroup CRYP_Data_Type CRYP Data Type + * @{ + */ + +#define CRYP_DATATYPE_32B 0x00000000U +#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0 +#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1 +#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE + +#define CRYP_NO_SWAP CRYP_DATATYPE_32B /*!< 32-bit data type (no swapping) */ +#define CRYP_HALFWORD_SWAP CRYP_DATATYPE_16B /*!< 16-bit data type (half-word swapping) */ +#define CRYP_BYTE_SWAP CRYP_DATATYPE_8B /*!< 8-bit data type (byte swapping) */ +#define CRYP_BIT_SWAP CRYP_DATATYPE_1B /*!< 1-bit data type (bit swapping) */ +/** + * @} + */ + +/** @defgroup CRYP_Interrupt CRYP and SAES peripherals interrupts + * @{ + */ + +#define CRYP_IT_INI CRYP_IMSCR_INIM /*!< CRYP peripheral input FIFO Interrupt */ +#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM /*!< CRYP peripheral output FIFO Interrupt */ + +#define CRYP_IT_CCFIE SAES_IER_CCFIE /*!< SAES peripheral computation Complete interrupt enable */ +#define CRYP_IT_RWEIE SAES_IER_RWEIE /*!< SAES peripheral read or write Error interrupt enable */ +#define CRYP_IT_KEIE SAES_IER_KEIE /*!< SAES peripheral key error interrupt enable */ +#define CRYP_IT_RNGEIE SAES_IER_RNGEIE /*!< SAES peripheral RNG error interrupt enable */ + +/** + * @} + */ + +/** @defgroup CRYP_Flags CRYP & SAES Flags + * @{ + */ + +/* Flags in the SR register */ +#define CRYP_FLAG_IFEM CRYP_SR_IFEM /*!< CRYP peripheral Input FIFO is empty */ +#define CRYP_FLAG_IFNF CRYP_SR_IFNF /*!< CRYP peripheral Input FIFO is not Full */ +#define CRYP_FLAG_OFNE CRYP_SR_OFNE /*!< CRYP peripheral Output FIFO is not empty */ +#define CRYP_FLAG_OFFU CRYP_SR_OFFU /*!< CRYP peripheral Output FIFO is Full */ +#define CRYP_FLAG_KERF CRYP_SR_KERF /*!< CRYP peripheral Key error flag */ +/* Flags in the RISR register */ +#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw interrupt status */ +#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/ + +#define CRYP_FLAG_BUSY CRYP_SR_BUSY /*!< The CRYP peripheral is currently processing a block of data + or a key preparation (for AES decryption). */ + + +#define CRYP_FLAG_KEYVALID CRYP_SR_KEYVALID /*!< CRYP or SAES peripheral Key valid flag */ + +#define SAES_FLAG_BUSY SAES_SR_BUSY /*!< The SAES peripheral is currently processing a block of data + or a key preparation (for AES decryption). */ + +#define CRYP_FLAG_WRERR (SAES_SR_WRERR | 0x80000000U) /*!< SAES peripheral Write Error flag */ +#define CRYP_FLAG_RDERR (SAES_SR_RDERR | 0x80000000U) /*!< SAES peripheral Read error flag */ +#define CRYP_FLAG_CCF SAES_SR_CCF /*!< SAES peripheral Computation completed flag + as AES_ISR_CCF */ +#define CRYP_FLAG_KEIF SAES_ISR_KEIF /*!< SAES peripheral Key error interrupt flag */ +#define CRYP_FLAG_RWEIF SAES_ISR_RWEIF /*!< SAES peripheral Read or Write error Interrupt flag */ +#define CRYP_FLAG_RNGEIF SAES_ISR_RNGEIF /*!< SAES peripheral RNG error Interrupt flag */ +/** + * @} + */ + +/** @defgroup CRYP_CLEAR_Flags SAES peripheral Clear Flags + * @{ + */ +#define CRYP_CLEAR_CCF SAES_ICR_CCF /*!< SAES peripheral clear Computation Complete Flag */ +#define CRYP_CLEAR_RWEIF SAES_ICR_RWEIF /*!< SAES peripheral clear Error Flag : RWEIF in SAES_ISR and + both RDERR and WRERR flags in SAES_SR */ +#define CRYP_CLEAR_KEIF SAES_ICR_KEIF /*!< SAES peripheral clear Key Error Flag: KEIF in SAES_ISR */ +#define CRYP_CLEAR_RNGEIF SAES_ICR_RNGEIF /*!< SAES peripheral clear RNG error Flag */ + +/** + * @} + */ + + +/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode + * @{ + */ + +#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration + to do systematically */ +#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration + to do only once */ +#define CRYP_KEYNOCONFIG 0x00000002U /*!< Peripheral Key configuration to not do */ + +/** + * @} + */ + +/** @defgroup CRYP_Key_Mode CRYP or SAES Key Mode + * @{ + */ + +#define CRYP_KEYMODE_NORMAL 0x00000000U /*!< Normal key usage, Key registers are freely usable */ +#define CRYP_KEYMODE_WRAPPED SAES_CR_KMOD_0 /*!< Only for SAES, Wrapped key: to encrypt + or decrypt AES keys */ +#define CRYP_KEYMODE_SHARED SAES_CR_KMOD_1 /*!< Key shared by SAES peripheral */ +/** + * @} + */ + +/** @defgroup CRYP_Key_Select SAES Key Select + * @{ + */ + +#define CRYP_KEYSEL_NORMAL 0x00000000U /*!< Normal key, key registers SAES_KEYx or CRYP_KEYx */ +#define CRYP_KEYSEL_HW SAES_CR_KEYSEL_0 /*!< Only for SAES, Hardware key : derived hardware + unique key (DHUK 256-bit) */ +#define CRYP_KEYSEL_SW SAES_CR_KEYSEL_1 /*!< Only for SAES, Software key : boot hardware + key BHK (256-bit) */ +#define CRYP_KEYSEL_HSW SAES_CR_KEYSEL_2 /*!< Only for SAES, DHUK XOR BHK Hardware unique + key XOR software key */ +#define CRYP_KEYSEL_AHK (SAES_CR_KEYSEL_1|SAES_CR_KEYSEL_0) /*!< Only for SAES, Software key : + application hardware key AHK (128- or 256-bit) */ +#define CRYP_KEYSEL_DUK_AHK (SAES_CR_KEYSEL_2|SAES_CR_KEYSEL_0) /*!< Only for SAES, DHUK XOR AHK */ +#define CRYP_KEYSEL_TEST_KEY (SAES_CR_KEYSEL_2|SAES_CR_KEYSEL_1|SAES_CR_KEYSEL_0) /*!< Test mode key (256-bit + hardware constant key 0xA5A5...A5A5) */ +/** + * @} + */ + +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +/** + * @} + */ + +/** @defgroup CRYP_Key_Shared SAES Key Shared with Peripheral + * @{ + */ + +#define CRYP_KEYSHARED_CRYP 0x00000000U /*!< Only for SAES, key is shared with CRYP peripheral */ + +/** + * @} + */ + +/** @defgroup CRYP_Mode SAES processing mode + * @{ + */ + +#define CRYP_MODE_ENCRYPT 0x00000000U /*!< SAES peripheral encryption mode */ +#define CRYP_MODE_KEY_DERIVATION SAES_CR_MODE_0 /*!< SAES peripheral key derivation */ +#define CRYP_MODE_DECRYPT SAES_CR_MODE_1 /*!< SAES peripheral decryption mode */ + +/** + * @} + */ +#endif /* USE_HAL_SAES_ONLY */ + +/** @defgroup CRYP_Mode SAES processing mode + * @{ + */ + +#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< CRYP peripheral encryption mode */ +#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /*!< CRYP peripheral decryption mode */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CRYP_Exported_Macros CRYP Exported Macros + * @{ + */ + +/** + * @brief Inform about which IP is the current INSTANCE: CRYP or SAES. + * @param INSTANCE: specifies the HW instance. + * @retval None + */ +#define IS_CRYP_INSTANCE(INSTANCE) ((INSTANCE) == CRYP) +#define IS_SAES_INSTANCE(INSTANCE) ((INSTANCE) == SAES) + +/** @brief Reset CRYP handle state + * @param __HANDLE__ specifies the CRYP handle. + * @retval None + */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) +#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0) +#else +#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET) +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + +/** + * @brief Enable/Disable the CRYP or SAES peripheral. + * @param __HANDLE__: specifies the CRYP handle. + * @retval None + */ + +#define __HAL_CRYP_ENABLE(__HANDLE__) ((IS_CRYP_INSTANCE((__HANDLE__)->Instance)) ? \ + (((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR |= CRYP_CR_CRYPEN) :\ + (((SAES_TypeDef *)((__HANDLE__)->Instance))->CR |= SAES_CR_EN)) + +#define __HAL_CRYP_DISABLE(__HANDLE__) ((IS_CRYP_INSTANCE((__HANDLE__)->Instance)) ? \ + (((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR &= ~CRYP_CR_CRYPEN) :\ + (((SAES_TypeDef *)((__HANDLE__)->Instance))->CR &= ~SAES_CR_EN)) + +/** @brief Check whether the specified CRYP or SAES peripheral status flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data + * or a key preparation (for AES decryption) + * @arg @ref CRYP_FLAG_KEYVALID Key valid flag + * @arg @ref CRYP_FLAG_KEIF Key error flag + * @arg CRYP_FLAG_IFEM: Input FIFO is empty (CRYP peripheral only) + * @arg CRYP_FLAG_IFNF: Input FIFO is not full (CRYP peripheral only) + * @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending (CRYP peripheral only) + * @arg CRYP_FLAG_OFNE: Output FIFO is not empty (CRYP peripheral only) + * @arg CRYP_FLAG_OFFU: Output FIFO is full (CRYP peripheral only) + * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending (CRYP peripheral only) + * @arg @ref CRYP_FLAG_WRERR Write Error flag (SAES peripheral only) + * @arg @ref CRYP_FLAG_RDERR Read Error flag (SAES peripheral only) + * @arg @ref CRYP_FLAG_CCF Computation Complete flag (SAES peripheral only) + * @arg @ref CRYP_FLAG_RWEIF Read/write Error flag (SAES peripheral only) + * @arg @ref CRYP_FLAG_RNGEIF RNG Error flag (SAES peripheral only) + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#define CRYP_FLAG_MASK 0x0000001FU + +#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((IS_CRYP_INSTANCE((__HANDLE__)->Instance)) ?\ + ((__FLAG__) == CRYP_FLAG_KEYVALID )?((((((CRYP_TypeDef *) \ + ((__HANDLE__)->Instance))))->SR \ + & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \ + ((__FLAG__) == CRYP_FLAG_BUSY )?((((((CRYP_TypeDef *) \ + ((__HANDLE__)->Instance))))->SR \ + & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \ + ((__FLAG__) == CRYP_FLAG_KEIF )?((((((CRYP_TypeDef *) \ + ((__HANDLE__)->Instance))))->SR \ + & (CRYP_FLAG_KERF)) == (CRYP_FLAG_KERF)) : \ + ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?(((((CRYP_TypeDef *) \ + ((__HANDLE__)->Instance))->RISR) & ((__FLAG__) & \ + CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \ + (((((CRYP_TypeDef *)((__HANDLE__)->Instance))->RISR) & ((__FLAG__)\ + & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK))) :\ + (\ + ((__FLAG__) == CRYP_FLAG_KEYVALID )?((((SAES_TypeDef *)\ + (((SAES_TypeDef *)((__HANDLE__)->Instance))))->SR \ + & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \ + ((__FLAG__) == CRYP_FLAG_BUSY )?((((SAES_TypeDef *) \ + ((__HANDLE__)->Instance))->SR \ + & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \ + ((__FLAG__) == CRYP_FLAG_WRERR )?((((SAES_TypeDef *) \ + ((__HANDLE__)->Instance))->SR \ + & (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) == \ + (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) : \ + ((__FLAG__) == CRYP_FLAG_RDERR )?((((SAES_TypeDef *) \ + ((__HANDLE__)->Instance))->SR \ + & (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) == \ + (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) : \ + ((__FLAG__) == CRYP_FLAG_RNGEIF )?((((SAES_TypeDef *) \ + ((__HANDLE__)->Instance))->ISR \ + & (CRYP_FLAG_RNGEIF)) == (CRYP_FLAG_RNGEIF)) : \ + ((__FLAG__) == CRYP_FLAG_KEIF )?((((SAES_TypeDef *) \ + ((__HANDLE__)->Instance))->ISR \ + & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF)) : \ + ((__FLAG__) == CRYP_FLAG_RWEIF )?((((SAES_TypeDef *) \ + ((__HANDLE__)->Instance))->ISR \ + & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF)) : \ + ((((SAES_TypeDef *)((__HANDLE__)->Instance))->ISR & \ + (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF)))) + +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +/** @brief Clear the SAES peripheral pending status flag. + * @param __HANDLE__ specifies the SAES handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref CRYP_CLEAR_RWEIF Read (RDERR), Write (WRERR) or Read/write (RWEIF) Error Flag Clear + * @arg @ref CRYP_CLEAR_CCF Computation Complete Flag (CCF) Clear + * @arg @ref CRYP_CLEAR_KEIF Key error interrupt flag clear + * @arg @ref CRYP_CLEAR_RNGEIF RNG error interrupt flag clear + * @retval None + */ +#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG(((SAES_TypeDef *)((__HANDLE__)->Instance))->ICR,\ + (__FLAG__)) +#endif /* USE_HAL_SAES_ONLY */ + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) +/** @brief Check whether the specified CRYP peripheral interrupt is set or not. + * @param __HANDLE__: specifies the CRYP handle. + * @param __INTERRUPT__: specifies the interrupt to check. + * This parameter can be one of the following values: + * @arg CRYP_IT_INI: Input FIFO service masked interrupt status + * @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status + * @retval The state of __INTERRUPT__ (TRUE or FALSE). + */ + +#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) ((((CRYP_TypeDef *)((__HANDLE__)->Instance))->MISR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) +#endif /* USE_HAL_CRYP_ONLY */ + +/** + * @brief Enable the CRYP or SAES peripheral interrupt. + * @param __HANDLE__: specifies the CRYP handle. + * @param __INTERRUPT__: Interrupt. + * This parameter can be one of the following values: + * @arg @ref CRYP_IT_INI Input FIFO service interrupt mask (CRYP peripheral only) + * @arg @ref CRYP_IT_OUTI Output FIFO service interrupt mask (CRYP peripheral only) + * @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR) (SAES peripheral only) + * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt (SAES peripheral only) + * @arg @ref CRYP_IT_KEIE Key error interrupt (SAES peripheral only) + * @arg @ref CRYP_IT_RNGEIE RNG interrupt (SAES peripheral only) + * @retval None + */ + +#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_CRYP_INSTANCE((__HANDLE__)->Instance)) ?\ + ((((CRYP_TypeDef *)((__HANDLE__)->Instance))->IMSCR) |= \ + (__INTERRUPT__)) : ((((SAES_TypeDef *) \ + ((__HANDLE__)->Instance))->IER) |= (__INTERRUPT__))) + +/** + * @brief Disable the CRYP or SAES peripheral interrupt. + * @param __HANDLE__: specifies the CRYP handle. + * @param __INTERRUPT__: Interrupt. + * This parameter can be one of the following values: + * @arg @ref CRYP_IT_INI Input FIFO service interrupt mask (CRYP peripheral only) + * @arg @ref CRYP_IT_OUTI Output FIFO service interrupt mask (CRYP peripheral only) + * @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR) (SAES peripheral only) + * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt (SAES peripheral only) + * @arg @ref CRYP_IT_KEIE Key error interrupt (SAES peripheral only) + * @arg @ref CRYP_IT_RNGEIE RNG interrupt (SAES peripheral only) + * @retval None + */ + +#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_CRYP_INSTANCE((__HANDLE__)->Instance)) ?\ + ((((CRYP_TypeDef *)((__HANDLE__)->Instance))->IMSCR) &= \ + ~(__INTERRUPT__)) : ((((SAES_TypeDef *) \ + ((__HANDLE__)->Instance))->IER) &= ~(__INTERRUPT__))) + +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +/** @brief Check whether the specified SAES peripheral interrupt source is enabled or not. + * @param __HANDLE__ specifies the CRYP handle. + * @param __INTERRUPT__ interrupt source to check + * This parameter can be one of the following values for TinyAES: + * @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR) + * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt + * @arg @ref CRYP_IT_KEIE Key error interrupt + * @arg @ref CRYP_IT_RNGEIE RNG error interrupt + * @retval State of interruption (TRUE or FALSE). + */ + +#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((SAES_TypeDef *)((__HANDLE__)->Instance))->IER\ + & (__INTERRUPT__)) == (__INTERRUPT__)) +#endif /* USE_HAL_SAES_ONLY */ +/** + * @} + */ + +/* Include CRYP HAL Extended module */ +#include "stm32h7rsxx_hal_cryp_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRYP_Exported_Functions CRYP Exported Functions + * @{ + */ + +/** @addtogroup CRYP_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp); +HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); +HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, + pCRYP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) +void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp); +HAL_StatusTypeDef HAL_CRYP_DMAProcessSuspend(CRYP_HandleTypeDef *hcryp); +HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp); +HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp); +#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */ +/** + * @} + */ + +/** @addtogroup CRYP_Exported_Functions_Group2 + * @{ + */ + +/* encryption/decryption ***********************************/ +HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); +HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); +HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); +HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); + +/** + * @} + */ + + +/** @addtogroup CRYP_Exported_Functions_Group3 + * @{ + */ +/* Interrupt Handler functions **********************************************/ +void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); +uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup CRYP_Private_Macros CRYP Private Macros + * @{ + */ + +/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters + * @{ + */ + +#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \ + ((ALGORITHM) == CRYP_AES_CBC) || \ + ((ALGORITHM) == CRYP_AES_CTR) || \ + ((ALGORITHM) == CRYP_AES_GCM) || \ + ((ALGORITHM) == CRYP_AES_CCM)) + +#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KEYSIZE_128B) || \ + ((KEYSIZE) == CRYP_KEYSIZE_192B) || \ + ((KEYSIZE) == CRYP_KEYSIZE_256B)) + +#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DATATYPE_32B) || \ + ((DATATYPE) == CRYP_DATATYPE_16B) || \ + ((DATATYPE) == CRYP_DATATYPE_8B) || \ + ((DATATYPE) == CRYP_DATATYPE_1B)) + +#define IS_CRYP_INIT(CONFIG) (((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \ + ((CONFIG) == CRYP_KEYIVCONFIG_ONCE) || \ + ((CONFIG) == CRYP_KEYNOCONFIG)) + +#define IS_CRYP_KEYIVCONFIG(CONFIG) (((KEYSIZE) == CRYP_KEYSIZE_128B) || \ + ((KEYSIZE) == CRYP_KEYSIZE_192B) || \ + ((KEYSIZE) == CRYP_KEYSIZE_256B)) + +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +#define IS_CRYP_KEYMODE(MODE) (((MODE) == CRYP_KEYMODE_NORMAL) || \ + ((MODE) == CRYP_KEYMODE_SHARED)) + +#define IS_SAES_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \ + ((ALGORITHM) == CRYP_AES_CBC) || \ + ((ALGORITHM) == CRYP_AES_CTR) || \ + ((ALGORITHM) == CRYP_AES_GCM) || \ + ((ALGORITHM) == CRYP_AES_CCM)) + +#define IS_SAES_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KEYSIZE_128B) || \ + ((KEYSIZE) == CRYP_KEYSIZE_256B)) + +#define IS_SAES_DATATYPE(DATATYPE) (((DATATYPE) == SAES_DATATYPE_32B) || \ + ((DATATYPE) == SAES_DATATYPE_16B) || \ + ((DATATYPE) == SAES_DATATYPE_8B) || \ + ((DATATYPE) == SAES_DATATYPE_1B)) + +#define IS_SAES_KEYMODE(MODE) (((MODE) == CRYP_KEYMODE_NORMAL) || \ + ((MODE) == CRYP_KEYMODE_WRAPPED) || \ + ((MODE) == CRYP_KEYMODE_SHARED)) + +#define IS_SAES_KEYPROT(PROTECTION) (((PROTECTION) == CRYP_KEYPROT_ENABLE) || \ + ((PROTECTION) == CRYP_KEYPROT_DISABLE)) + +#define IS_SAES_KEYSEL(SELECTION) (((SELECTION) == CRYP_KEYSEL_NORMAL) || \ + ((SELECTION) == CRYP_KEYSEL_HW) || \ + ((SELECTION) == CRYP_KEYSEL_SW) || \ + ((SELECTION) == CRYP_KEYSEL_HSW) || \ + ((SELECTION) == CRYP_KEYSEL_AHK) || \ + ((SELECTION) == CRYP_KEYSEL_DUK_AHK) || \ + ((SELECTION) == CRYP_KEYSEL_TEST_KEY)) + +#define IS_SAES_KEYSHARED(PERIPHERAL) ((PERIPHERAL) == CRYP_KEYSHARED_CRYP) +/** + * @} + */ +#endif /* USE_HAL_SAES_ONLY */ + +/** @defgroup SAES_CONV_Definitions SAES Private macros to convert input parameters from CRYP peripheral to + SAES peripheral format + * @{ + */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +#define SAES_CONV_DATATYPE(__DATATYPE__) ((__DATATYPE__) >> (CRYP_CR_DATATYPE_Pos - SAES_CR_DATATYPE_Pos)) + +#define SAES_CONV_KEYSIZE(__KEY__) (((__KEY__)\ + & CRYP_CR_KEYSIZE_1) << (SAES_CR_KEYSIZE_Pos - (CRYP_CR_KEYSIZE_Pos + 1U))) + +#define SAES_CONV_ALGO(__ALGO__) (((__ALGO__)\ + & (CRYP_CR_ALGOMODE_1 | CRYP_CR_ALGOMODE_0)) << (SAES_CR_CHMOD_Pos - \ + CRYP_CR_ALGOMODE_Pos)) +#endif /* USE_HAL_SAES_ONLY */ +#define CRYP_CONV_ALGODIR(__ALGODIR__) (((__ALGODIR__)\ + & SAES_CR_MODE_1) >> ((SAES_CR_MODE_Pos + 1U) - CRYP_CR_ALGODIR_Pos)) + +/** + * @} + */ + + +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CRYP_Private_Constants CRYP Private Constants + * @{ + */ + +/** + * @} + */ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup CRYP_Private_Defines CRYP Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CRYP_Private_Variables CRYP Private Variables + * @{ + */ + +/** + * @} + */ +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CRYP_Private_Functions CRYP Private Functions + * @{ + */ + +/** + * @} + */ + + +/** + * @} + */ + + +#endif /* CRYP */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* STM32H7RSxx_HAL_CRYP_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cryp_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cryp_ex.h new file mode 100644 index 00000000000..3453457a7db --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_cryp_ex.h @@ -0,0 +1,129 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_cryp_ex.h + * @author MCD Application Team + * @brief Header file of CRYP HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_CRYP_EX_H +#define STM32H7RSxx_HAL_CRYP_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#if defined (CRYP) +/** @addtogroup CRYPEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup CRYPEx_Private_Types CRYPEx Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions + * @{ + */ + +/** @addtogroup CRYPEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag, + uint32_t Timeout); +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t *Output, + uint32_t ID, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t ID, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t *Output, uint32_t Timeout); +#endif /* USE_HAL_SAES_ONLY */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ +#endif /* CRYP */ +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_CRYP_EX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dcmipp.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dcmipp.h new file mode 100644 index 00000000000..18fcfe42f18 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dcmipp.h @@ -0,0 +1,948 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_dcmipp.h + * @author MCD Application Team + * @brief Header file of DCMIPP HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7RSxx_HAL_DCMIPP_H +#define __STM32H7RSxx_HAL_DCMIPP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#if defined (DCMIPP) + +/** @addtogroup DCMIPP DCMIPP + * @brief DCMIPP HAL module driver + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DCMIPP_Exported_Types DCMIPP Exported Types + * @brief DCMIPP Exported Types + * @{ + */ +/** + * @brief DCMIPP Embedded Synchronisation Unmask codes structure definition + */ +typedef struct +{ + uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */ + uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */ + uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */ + uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */ +} DCMIPP_EmbeddedSyncUnmaskTypeDef; + +/** + * @brief DCMIPP Embedded Synchronisation codes structure definition (CCIR656) + */ +typedef struct +{ + uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ + uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */ + uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */ + uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ +} DCMIPP_EmbeddedSyncCodesTypeDef; + + +/** + * @brief HAL DCMIPP Parallel configuration structure definition + */ +typedef struct +{ + uint32_t Format; /*!< Configures the DCMIPP Format + This parameter can be one value of @ref DCMIPP_Format */ + uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. + This parameter can be a value of @ref DCMIPP_VSYNC_Polarity */ + uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. + This parameter can be a value of @ref DCMIPP_HSYNC_Polarity */ + uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. + This parameter can be a value of @ref DCMIPP_PIXCK_Polarity */ + uint32_t ExtendedDataMode ; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit 14-bit or 16-bits. + This parameter can be a value of @ref DCMIPP_Extended_Data_Mode */ + uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. + This parameter can be a value of @ref DCMIPP_Synchronization_Mode */ + DCMIPP_EmbeddedSyncCodesTypeDef SynchroCodes; /*!< Specifies the code of the line/frame start delimiter and the + line/frame end delimiter */ + uint32_t SwapBits; /*!< Enable or Disable the Swap Bits. + This parameter can be a value of @ref DCMIPP_SWAP_BITS */ + uint32_t SwapCycles; /*!< Enable or Disable the Swap Cycles. + This parameter can be a value of @ref DCMIPP_SWAP_CYCLES */ +} DCMIPP_ParallelConfTypeDef; + +/** + * @brief HAL DCMIPP Pipe configuration structure definition + */ +typedef struct +{ + uint32_t FrameRate; /*!< Configures the DCMIPP Pipe Frame Rate + This parameter can be one value of @ref DCMIPP_Frame_Rates */ +} DCMIPP_PipeConfTypeDef; + +/** + * @brief HAL DCMIPP IPPLUG configuration structure definition + */ +typedef struct +{ + uint32_t Client; /*!< Configures the DCMIPP IPPLUG Client + This parameter can be a value from @ref DCMIPP_IPPLUG_Client */ + uint32_t MemoryPageSize; /*!< Configures the DCMIPP IPPLUG Memory page size + This parameter can be a value from @ref DCMIPP_Memory_Page_Size */ + uint32_t Traffic; /*!< Configures the DCMIPP IPPLUG Traffic + This parameter can be a value from @ref DCMIPP_Traffic_Burst_Size */ + uint32_t MaxOutstandingTransactions ; /*!< Configures the DCMIPP IPPLUG Maximum outstanding transactions + This parameter can be a value from + DCMIPP_Maximum_Outstanding_Transactions */ + uint32_t DPREGStart; /*!< Configures the End word of the FIFO of Clientx + This parameter can be a value between 0 and 0x3FF */ + uint32_t DPREGEnd; /*!< Configures the Start word of the FIFO of Clientx + This parameter can be a value between 0 and 0x3FF */ + uint32_t WLRURatio; /*!< Configures the DCMIPP Ratio for WLRU arbitration + This parameter can be a value between 0 and 15 */ +} DCMIPP_IPPlugConfTypeDef; + +/** + * @brief HAL DCMIPP Crop configuration structure definition + */ +typedef struct +{ + uint32_t VStart; /*!< Configures the DCMIPP Crop Vertical Start + This parameter can be one value between 0 and 4095 */ + uint32_t HStart; /*!< Configures the DCMIPP Crop Horizontal Start + This parameter can be one value between 0 and 4095 */ + uint32_t VSize; /*!< Configures the DCMIPP Crop Vertical Size + This parameter can be one value between 0 and 4095 */ + uint32_t HSize; /*!< Configures the DCMIPP Crop Horizontal Size + This parameter can be one value between 1 and 4095 */ + uint32_t PipeArea; /*!< Configures the DCMIPP Crop Area for the pipe0 + This parameter can be one value of @ref DCMIPP_Crop_Area */ +} DCMIPP_CropConfTypeDef; + + +/** + * @brief HAL DCMIPP State enumeration definition + */ +typedef enum +{ + HAL_DCMIPP_STATE_RESET = 0x00U, /*!< DCMIPP not yet initialized or disabled */ + HAL_DCMIPP_STATE_INIT = 0x01U, /*!< DCMIPP initialized */ + HAL_DCMIPP_STATE_READY = 0x02U, /*!< DCMIPP configured and ready for use */ + HAL_DCMIPP_STATE_BUSY = 0x03U, /*!< DCMIPP internal processing is ongoing */ + HAL_DCMIPP_STATE_ERROR = 0x04U, /*!< DCMIPP state error */ +} HAL_DCMIPP_StateTypeDef; + +/** + * @brief HAL DCMIPP Pipe State enumeration definition + */ + +typedef enum +{ + HAL_DCMIPP_PIPE_STATE_RESET = 0x00U, /*!< DCMIPP Pipe not yet initialized or disabled */ + HAL_DCMIPP_PIPE_STATE_READY = 0x01U, /*!< DCMIPP Pipe initialized and ready for use */ + HAL_DCMIPP_PIPE_STATE_BUSY = 0x02U, /*!< DCMIPP internal processing is ongoing */ + HAL_DCMIPP_PIPE_STATE_SUSPEND = 0x03U, /*!< DCMIPP pipe process is suspended */ + HAL_DCMIPP_PIPE_STATE_ERROR = 0x04U, /*!< DCMIPP pipe error state */ +} HAL_DCMIPP_PipeStateTypeDef; + +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DCMIPP common Callback ID enumeration definition + */ +typedef enum +{ + HAL_DCMIPP_MSPINIT_CB_ID = 0x00U, /*!< DCMIPP MspInit callback ID */ + HAL_DCMIPP_MSPDEINIT_CB_ID = 0x01U, /*!< DCMIPP MspDeInit callback ID */ + HAL_DCMIPP_ERROR_CB_ID = 0x02U, /*!< DCMIPP Error callback ID */ +} HAL_DCMIPP_CallbackIDTypeDef; + +/** + * @brief HAL DCMIPP pipe Callback ID enumeration definition + */ +typedef enum +{ + HAL_DCMIPP_PIPE_LIMIT_EVENT_CB_ID = 0x01U, /*!< DCMIPP Pipe Limit event callback ID */ + HAL_DCMIPP_PIPE_LINE_EVENT_CB_ID = 0x02U, /*!< DCMIPP Pipe Line event callback ID */ + HAL_DCMIPP_PIPE_FRAME_EVENT_CB_ID = 0x03U, /*!< DCMIPP Pipe Frame event callback ID */ + HAL_DCMIPP_PIPE_VSYNC_EVENT_CB_ID = 0x04U, /*!< DCMIPP Pipe Vsync event callback ID */ + HAL_DCMIPP_PIPE_ERROR_CB_ID = 0x05U, /*!< DCMIPP Pipe Error callback ID */ +} HAL_DCMIPP_PIPE_CallbackIDTypeDef; +#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */ + +/** + * @brief HAL DCMIPP handle structures definition + */ +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) +typedef struct __DCMIPP_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */ +{ + DCMIPP_TypeDef *Instance; /*!< Register the DCMIPP base + address */ + __IO HAL_DCMIPP_StateTypeDef State; /*!< DCMIPP state */ + __IO HAL_DCMIPP_PipeStateTypeDef PipeState[DCMIPP_NUM_OF_PIPES]; /*!< DCMIPP Pipes state */ + __IO uint32_t ErrorCode; /*!< DCMIPP Error code */ +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) + void (* PIPE_FrameEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< DCMIPP Pipe Frame Event + Callback */ + void (* PIPE_VsyncEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< DCMIPP Pipe Vsync Event + Callback */ + void (* PIPE_LineEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< DCMIPP Pipe Line Event + Callback */ + void (* PIPE_LimitEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< DCMIPP Pipe Limit Event + Callback */ + void (* PIPE_ErrorCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< DCMIPP Pipe Error + Callback */ + void (* ErrorCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp); /*!< DCMIPP Error Callback */ + void (* MspInitCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp); /*!< DCMIPP Msp Init + Callback */ + void (* MspDeInitCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp); /*!< DCMIPP Msp DeInit + Callback */ +#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */ +} DCMIPP_HandleTypeDef; + +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DCMIPP Callback pointer definition + */ +typedef void (*pDCMIPP_CallbackTypeDef)(DCMIPP_HandleTypeDef *hdcmipp); /*!< Pointer to a DCMIPP common callback + function */ +typedef void (*pDCMIPP_PIPE_CallbackTypeDef)(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< Pointer to a DCMIPP + Pipe callback function */ +#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DCMIPP_Exported_Constants DCMIPP Exported Constants + * @brief DCMIPP Exported constants + * @{ + */ + +/** @defgroup DCMIPP_Pipes DCMIPP Pipes + * @{ + */ +#define DCMIPP_PIPE0 0U /*!< DCMIPP Pipe0 (Dump pipe) */ +/** + * @} + */ + +/** @defgroup DCMIPP_Error_Codes DCMIPP Error Codes + * @{ + */ +#define HAL_DCMIPP_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_DCMIPP_ERROR_AXI_TRANSFER (0x00000001U) /*!< IPPLUG AXI Transfer error */ +#define HAL_DCMIPP_ERROR_PARALLEL_SYNC (0x00000002U) /*!< Synchronization error */ +#define HAL_DCMIPP_ERROR_PIPE0_LIMIT (0x00000004U) /*!< Limit error on pipe0 */ +#define HAL_DCMIPP_ERROR_PIPE0_OVR (0x00000008U) /*!< Overrun error on pipe0 */ + +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) +#define HAL_DCMIPP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup DCMIPP_Capture_Mode DCMIPP Capture Mode + * @{ + */ +#define DCMIPP_MODE_CONTINUOUS 0U /*!< DCMIPP continuous mode (preview) */ +#define DCMIPP_MODE_SNAPSHOT DCMIPP_P0FCTCR_CPTMODE /*!< DCMIPP snapshot mode */ +/** + * @} + */ + + +/** @defgroup DCMIPP_IPPLUG_Client DCMIPP IPPLUG Client + * @{ + */ +#define DCMIPP_CLIENT1 1U /*!< Client 1 identifier */ +/** + * @} + */ + +/** @defgroup DCMIPP_Traffic_Burst_Size DCMIPP Traffic Burst Size + * @{ + */ +#define DCMIPP_TRAFFIC_BURST_SIZE_8BYTES 0U /*!< Traffic Burst size 8 Bytes */ +#define DCMIPP_TRAFFIC_BURST_SIZE_16BYTES (0x01U << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< Traffic Burst size 16 Bytes */ +#define DCMIPP_TRAFFIC_BURST_SIZE_32BYTES (0x02U << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< Traffic Burst size 32 Bytes */ +#define DCMIPP_TRAFFIC_BURST_SIZE_64BYTES (0x03U << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< Traffic Burst size 64 Bytes */ +#define DCMIPP_TRAFFIC_BURST_SIZE_128BYTES (0x04U << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< Traffic Burst size 128 Bytes */ +/** + * @} + */ + +/** @defgroup DCMIPP_Memory_Page_Size DCMIPP Memory Page Size + * @{ + */ +#define DCMIPP_MEMORY_PAGE_SIZE_64BYTES 0U /*!< Memory Page size 64 Bytes */ +#define DCMIPP_MEMORY_PAGE_SIZE_128BYTES (0x01U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 128 Bytes */ +#define DCMIPP_MEMORY_PAGE_SIZE_256BYTES (0x02U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 256 Bytes */ +#define DCMIPP_MEMORY_PAGE_SIZE_512BYTES (0x03U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 512 Bytes */ +#define DCMIPP_MEMORY_PAGE_SIZE_1KBYTES (0x04U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 1 Bytes */ +#define DCMIPP_MEMORY_PAGE_SIZE_2KBYTES (0x05U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 2 Bytes */ +#define DCMIPP_MEMORY_PAGE_SIZE_4KBYTES (0x06U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 4 Bytes */ +#define DCMIPP_MEMORY_PAGE_SIZE_8KBYTES (0x07U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 8 Bytes */ +/** + * @} + */ +/** @defgroup DCMIPP_Maximum_Outstanding_Transactions DCMIPP Maximum Outstanding Transactions + * @{ + */ +#define DCMIPP_OUTSTANDING_TRANSACTION_NONE 0U /*!< Nooutstanding transaction limitation*/ +#define DCMIPP_OUTSTANDING_TRANSACTION_2 (0x01U << DCMIPP_IPC1R1_OTR_Pos) /*!< Two outstanding transactions */ +#define DCMIPP_OUTSTANDING_TRANSACTION_3 (0x02U << DCMIPP_IPC1R1_OTR_Pos) /*!< Three outstanding transactions */ +#define DCMIPP_OUTSTANDING_TRANSACTION_4 (0x03U << DCMIPP_IPC1R1_OTR_Pos) /*!< Four outstanding transactions */ +/** + * @} + */ + +/** @defgroup DCMIPP_Frame_Rates DCMIPP Frame Rates + * @{ + */ +#define DCMIPP_FRAME_RATE_ALL 0U /*!< All frames captured */ +#define DCMIPP_FRAME_RATE_1_OVER_2 (1U << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 1 frame over 2 captured */ +#define DCMIPP_FRAME_RATE_1_OVER_4 (2U << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 1 frame over 4 captured */ +#define DCMIPP_FRAME_RATE_1_OVER_8 (3U << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 1 frame over 8 captured */ +/** + * @} + */ + +/** @defgroup DCMIPP_Crop_Area DCMIPP Crop Area + * @{ + */ +#define DCMIPP_POSITIVE_AREA 0U /*!< Positive Area chosen for crop */ +#define DCMIPP_NEGATIVE_AREA DCMIPP_P0SCSZR_POSNEG /*!< Negative Area chosen for crop */ +/** + * @} + */ + + + +/** @defgroup DCMIPP_Format DCMIPP Format + * @{ + */ +#define DCMIPP_FORMAT_BYTE 0U /*!< DCMIPP Format BYTE */ +#define DCMIPP_FORMAT_YUV422 (0x1EU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format YUV422 */ +#define DCMIPP_FORMAT_RGB565 (0x22U << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RGB565 */ +#define DCMIPP_FORMAT_RGB666 (0x23U << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RGB666 */ +#define DCMIPP_FORMAT_RGB888 (0x24U << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RGB888 */ +#define DCMIPP_FORMAT_RAW8 (0x2AU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW8 */ +#define DCMIPP_FORMAT_RAW10 (0x2BU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW10 */ +#define DCMIPP_FORMAT_RAW12 (0x2CU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW12 */ +#define DCMIPP_FORMAT_RAW14 (0x2DU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW14 */ +#define DCMIPP_FORMAT_MONOCHROME_8B (0x4AU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 8-bits */ +#define DCMIPP_FORMAT_MONOCHROME_10B (0x4BU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 10-bits */ +#define DCMIPP_FORMAT_MONOCHROME_12B (0x4CU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 12-bits */ +#define DCMIPP_FORMAT_MONOCHROME_14B (0x4DU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 14-bits */ +/** + * @} + */ + +/** @defgroup DCMIPP_Extended_Data_Mode DCMIPP Extended Data Mode + * @{ + */ +#define DCMIPP_INTERFACE_8BITS 0U /*!< Interface captures 8bits on every pixel clock */ +#define DCMIPP_INTERFACE_10BITS (1U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 10bits on every pixel clock */ +#define DCMIPP_INTERFACE_12BITS (2U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 12bits on every pixel clock */ +#define DCMIPP_INTERFACE_14BITS (3U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 14bits on every pixel clock */ +#define DCMIPP_INTERFACE_16BITS (4U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 16bits on every pixel clock */ +/** + * @} + */ + +/** @defgroup DCMIPP_HSYNC_Polarity DCMIPP HSYNC Polarity + * @{ + */ +#define DCMIPP_HSPOLARITY_LOW 0U /*!< Horizontal synchronization active Low */ +#define DCMIPP_HSPOLARITY_HIGH DCMIPP_PRCR_HSPOL /*!< Horizontal synchronization active High */ +/** + * @} + */ +/** @defgroup DCMIPP_VSYNC_Polarity DCMIPP VSYNC Polarity + * @{ + */ +#define DCMIPP_VSPOLARITY_LOW 0U /*!< Vertical synchronization active Low */ +#define DCMIPP_VSPOLARITY_HIGH DCMIPP_PRCR_VSPOL /*!< Vertical synchronization active High */ +/** + * @} + */ +/** @defgroup DCMIPP_PIXCK_Polarity DCMIPP PIXCK Polarity + * @{ + */ +#define DCMIPP_PCKPOLARITY_FALLING 0U /*!< Pixel clock active on Falling edge */ +#define DCMIPP_PCKPOLARITY_RISING DCMIPP_PRCR_PCKPOL /*!< Pixel clock active on Rising edge */ +/** + * @} + */ + +/** @defgroup DCMIPP_Synchronization_Mode DCMIPP Synchronization Mode + * @{ + */ +#define DCMIPP_SYNCHRO_HARDWARE 0U /*!< Hardware Synchronization */ +#define DCMIPP_SYNCHRO_EMBEDDED DCMIPP_PRCR_ESS /*!< Embedded Synchronization */ +/** + * @} + */ + +/** @defgroup DCMIPP_SWAP_CYCLES DCMIPP Swap Cycles + * @{ + */ +#define DCMIPP_SWAPCYCLES_DISABLE 0U /*!< swap data from cycle 0 vs cycle 1 */ +#define DCMIPP_SWAPCYCLES_ENABLE (DCMIPP_PRCR_SWAPCYCLES) /*!< swap data from cycle 0 vs cycle 1 */ +/** + * @} + */ + +/** @defgroup DCMIPP_SWAP_BITS DCMIPP Swap Bits + * @{ + */ +#define DCMIPP_SWAPBITS_DISABLE 0U /*!< swap lsb vs msb within each received component */ +#define DCMIPP_SWAPBITS_ENABLE (DCMIPP_PRCR_SWAPBITS) /*!< swap lsb vs msb within each received component */ +/** + * @} + */ + +/** @defgroup DCMIPP_Pipe_Line_Decimation DCMIPP Pipe Line Decimation + * @{ + */ +/** @defgroup DCMIPP_Line_Select_Mode DCMIPP Line Select Mode + * @{ + */ +#define DCMIPP_LSM_ALL 0U /*!< Interface captures all received lines */ +#define DCMIPP_LSM_ALTERNATE_2 (1U << DCMIPP_P0PPCR_LSM_Pos ) /*!< Interface captures one line out of two */ +/** + * @} + */ +/** @defgroup DCMIPP_Line_Start_Mode DCMIPP Line Start Mode + * @{ + */ +#define DCMIPP_OELS_ODD 0U /*!< Interface captures first line from the frame start, + second one is dropped */ +#define DCMIPP_OELS_EVEN (1U << DCMIPP_P0PPCR_OELS_Pos) /*!< Interface captures second line from the frame + start, first one is dropped */ +/** + * @} + */ +/** + * @} + */ + +/** @defgroup DCMIPP_Pipe_Byte_Decimation DCMIPP Pipe Byte Decimation + * @{ + */ +/** @defgroup DCMIPP_Byte_Select_Mode DCMIPP Byte Select Mode + * @{ + */ +#define DCMIPP_BSM_ALL 0U /*!< Interface captures all received data */ +#define DCMIPP_BSM_DATA_OUT_2 (1U << DCMIPP_P0PPCR_BSM_Pos) /*!< Interface captures 1 data out of 2 */ +#define DCMIPP_BSM_BYTE_OUT_4 (2U << DCMIPP_P0PPCR_BSM_Pos) /*!< Interface captures 1 byte out of 4 */ +#define DCMIPP_BSM_2BYTE_OUT_4 (3U << DCMIPP_P0PPCR_BSM_Pos) /*!< Interface captures 2 byte out of 4 */ +/** + * @} + */ +/** @defgroup DCMIPP_Byte_Start_Mode DCMIPP Byte Start Mode + * @{ + */ +#define DCMIPP_OEBS_ODD 0U /*!< Interface captures first data (byte or double byte) + from the frame/line start,second one being dropped */ +#define DCMIPP_OEBS_EVEN (1U << DCMIPP_P0PPCR_OEBS_Pos) /*!< Interface captures second data (byte or double byte) + from the frame/line start, first one is dropped */ +/** + * @} + */ +/** + * @} + */ + +/** @defgroup DCMIPP_Memory DCMIPP Memory + * @{ + */ +#define DCMIPP_MEMORY_ADDRESS_0 0U /*!< Base destination address */ +#define DCMIPP_MEMORY_ADDRESS_1 1U /*!< Second destination address */ +/** + * @} + */ +/** @defgroup DCMIPP_LineMult DCMIPP Line Mult + * @{ + */ +#define DCMIPP_MULTILINE_1_LINE 0U /*!< Event after every 1 line */ +#define DCMIPP_MULTILINE_2_LINES (1U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 2 lines */ +#define DCMIPP_MULTILINE_4_LINES (2U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 4 lines */ +#define DCMIPP_MULTILINE_8_LINES (3U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 8 lines */ +#define DCMIPP_MULTILINE_16_LINES (4U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 16 lines */ +#define DCMIPP_MULTILINE_32_LINES (5U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 32 lines */ +#define DCMIPP_MULTILINE_64_LINES (6U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 64 lines */ +#define DCMIPP_MULTILINE_128_LINES (7U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 128 lines */ +/** + * @} + */ +/** @defgroup DCMIPP_Interrupt_Sources DCMIPP Interrupt sources + * @{ + */ +#define DCMIPP_IT_AXI_TRANSFER_ERROR DCMIPP_CMIER_ATXERRIE /*!< IPPLUG AXI Transfer error interrupt */ +#define DCMIPP_IT_PARALLEL_SYNC_ERROR DCMIPP_CMIER_PRERRIE /*!< Sync error interrupt on parallel interface */ +#define DCMIPP_IT_PIPE0_FRAME DCMIPP_CMIER_P0FRAMEIE /*!< Frame capture interrupt complete for pipe0 */ +#define DCMIPP_IT_PIPE0_VSYNC DCMIPP_CMIER_P0VSYNCIE /*!< Vertical sync interrupt for pipe0 */ +#define DCMIPP_IT_PIPE0_LINE DCMIPP_CMIER_P0LINEIE /*!< Multiline interrupt for pipe0 */ +#define DCMIPP_IT_PIPE0_LIMIT DCMIPP_CMIER_P0LIMITIE /*!< Limit interrupt for pipe0 */ +#define DCMIPP_IT_PIPE0_OVR DCMIPP_CMIER_P0OVRIE /*!< Overrun interrupt for pipe0 */ +/** + * @} + */ + +/** @defgroup DCMIPP_Interrupt_Flags DCMIPP Interrupt Flags + * @{ + */ +#define DCMIPP_FLAG_AXI_TRANSFER_ERROR DCMIPP_CMSR2_ATXERRF /*!< IPPLUG AXI Transfer error interrupt flag */ +#define DCMIPP_FLAG_PARALLEL_SYNC_ERROR DCMIPP_CMSR2_PRERRF /*!< Synchronization error interrupt on parallel interface + flag */ +#define DCMIPP_FLAG_PIPE0_FRAME DCMIPP_CMSR2_P0FRAMEF /*!< Frame capture interrupt complete for pipe0 flag */ +#define DCMIPP_FLAG_PIPE0_VSYNC DCMIPP_CMSR2_P0VSYNCF /*!< Vertical synch interrupt for pipe0 flag */ +#define DCMIPP_FLAG_PIPE0_LINE DCMIPP_CMSR2_P0LINEF /*!< Multiline interrupt for pipe0 flag */ +#define DCMIPP_FLAG_PIPE0_LIMIT DCMIPP_CMSR2_P0LIMITF /*!< Limit interrupt for pipe0 flag */ +#define DCMIPP_FLAG_PIPE0_OVR DCMIPP_CMSR2_P0OVRF /*!< Overrun interrupt for pipe0 flag */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DCMIPP_Exported_Macros DCMIPP Exported Macros + * @brief DCMIPP Exported Macros + * @{ + */ +/** + * @brief Enable the specified DCMIPP interrupts. + * @param __HANDLE__ DCMIPP handle + * @param __INTERRUPT__ specifies the DCMIPP interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DCMIPP_IT_AXI_TRANSFER_ERR IPPLUG AXI Transfer error interrupt + * @arg DCMIPP_IT_PARALLEL_SYNC_ERR Synchronization error interrupt on parallel interface + * @arg DCMIPP_IT_PIPE0_FRAME Frame capture complete interrupt for the pipe0 + * @arg DCMIPP_IT_PIPE0_VSYNC Vertical sync interrupt for the pipe0 + * @arg DCMIPP_IT_PIPE0_LINE Multi-line capture complete interrupt for the pipe0 + * @arg DCMIPP_IT_PIPE0_LIMIT Limit interrupt for the pipe0 + * @arg DCMIPP_IT_PIPE0_OVR Overrun interrupt for the pipe0 + * @retval None + */ +#define __HAL_DCMIPP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CMIER |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DCMIPP interrupts. + * @param __HANDLE__ DCMIPP handle + * @param __INTERRUPT__ specifies the DCMIPP interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg DCMIPP_IT_AXI_TRANSFER_ERR IPPLUG AXI Transfer error interrupt + * @arg DCMIPP_IT_PARALLEL_SYNC_ERR Synchronization error interrupt on parallel interface + * @arg DCMIPP_IT_PIPE0_FRAME Frame capture complete interrupt for the pipe0 + * @arg DCMIPP_IT_PIPE0_VSYNC Vertical sync interrupt for the pipe0 + * @arg DCMIPP_IT_PIPE0_LINE Multi-line capture complete interrupt for the pipe0 + * @arg DCMIPP_IT_PIPE0_LIMIT Limit interrupt for the pipe0 + * @arg DCMIPP_IT_PIPE0_OVR Overrun interrupt for the pipe0 + * @retval None + */ +#define __HAL_DCMIPP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CMIER &= ~(__INTERRUPT__)) + +/** + * @brief Get the DCMIPP pending interrupt flags. + * @param __HANDLE__ DCMIPP handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DCMIPP_FLAG_AXI_TRANSFER_ERR IPPLUG AXI Transfer error interrupt flag + * @arg DCMIPP_FLAG_PARALLEL_SYNC_ERR Synchronization error interrupt flag on parallel interface + * @arg DCMIPP_FLAG_PIPE0_FRAME Frame capture complete interrupt flag for the pipe0 + * @arg DCMIPP_FLAG_PIPE0_VSYNC Vertical sync interrupt flag for the pipe0 + * @arg DCMIPP_FLAG_PIPE0_LINE Multi-line capture complete interrupt flag for the pipe0 + * @arg DCMIPP_FLAG_PIPE0_LIMIT Limit interrupt flag for the pipe0 + * @arg DCMIPP_FLAG_PIPE0_OVR Overrun interrupt flag for the pipe0 + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DCMIPP_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CMSR2 & (__FLAG__)) + +/** + * @brief Clear the DCMIPP pending interrupt flags. + * @param __HANDLE__ DCMIPP handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DCMIPP_FLAG_AXI_TRANSFER_ERR IPPLUG AXI Transfer error interrupt + * @arg DCMIPP_FLAG_PARALLEL_SYNC_ERR Synchronization error interrupt on parallel interface + * @arg DCMIPP_FLAG_PIPE0_FRAME Frame capture complete interrupt for the pipe0 + * @arg DCMIPP_FLAG_PIPE0_VSYNC Vertical sync interrupt for the pipe0 + * @arg DCMIPP_FLAG_PIPE0_LINE Multi-line capture complete interrupt for the pipe0 + * @arg DCMIPP_FLAG_PIPE0_LIMIT Limit interrupt for the pipe0 + * @arg DCMIPP_FLAG_PIPE0_OVR Overrun interrupt for the pipe0 + * @retval None + */ +#define __HAL_DCMIPP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CMFCR = (__FLAG__)) + +/** + * @brief Checks whether the specified DCMIPP interrupt is enabled or not. + * @param __HANDLE__ DCMIPP handle + * @param __INTERRUPT__ specifies the DCMIPP interrupt sources to be checked. + * This parameter can be any combination of the following values: + * @arg DCMIPP_IT_AXI_TRANSFER_ERR IPPLUG AXI Transfer error interrupt + * @arg DCMIPP_IT_PARALLEL_SYNC_ERR Synchronization error interrupt on parallel interface + * @arg DCMIPP_IT_PIPE0_FRAME Frame capture complete interrupt for the pipe0 + * @arg DCMIPP_IT_PIPE0_VSYNC Vertical sync interrupt for the pipe0 + * @arg DCMIPP_IT_PIPE0_LINE Multi-line capture complete interrupt for the pipe0 + * @arg DCMIPP_IT_PIPE0_LIMIT Limit interrupt for the pipe0 + * @arg DCMIPP_IT_PIPE0_OVR Overrun interrupt for the pipe0 + * @retval The state of DCMIPP interrupt (SET or RESET). + */ +#define __HAL_DCMIPP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CMIER & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DCMIPP_Exported_Functions + * @{ + */ + +/** @addtogroup DCMIPP_Initialization_De-Initialization_Functions DCMIPP Initialization De-Initialization Functions + * @brief Initialization and De-Initialization Functions + * @{ + */ +HAL_StatusTypeDef HAL_DCMIPP_Init(DCMIPP_HandleTypeDef *hdcmipp); +HAL_StatusTypeDef HAL_DCMIPP_DeInit(DCMIPP_HandleTypeDef *hdcmipp); +void HAL_DCMIPP_MspInit(DCMIPP_HandleTypeDef *hdcmipp); +void HAL_DCMIPP_MspDeInit(DCMIPP_HandleTypeDef *hdcmipp); +/** + * @} + */ + +/** @defgroup DCMIPP_Configuration_Functions DCMIPP Configuration Functions + * @brief Configuration Functions + * @{ + */ + +HAL_StatusTypeDef HAL_DCMIPP_PARALLEL_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, + const DCMIPP_ParallelConfTypeDef *pParallelConfig); + +HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, + const DCMIPP_PipeConfTypeDef *pPipeConfig); +HAL_StatusTypeDef HAL_DCMIPP_SetIPPlugConfig(DCMIPP_HandleTypeDef *hdcmipp, + const DCMIPP_IPPlugConfTypeDef *pIPPlugConfig); +/** + * @} + */ + +/** @addtogroup DCMIPP_IO_operation_Functions DCMIPP IO operation Functions + * @brief IO Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_Start(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress, + uint32_t CaptureMode); +HAL_StatusTypeDef HAL_DCMIPP_PIPE_DoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress0, + uint32_t DstAddress1, uint32_t CaptureMode); +HAL_StatusTypeDef HAL_DCMIPP_PIPE_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); +HAL_StatusTypeDef HAL_DCMIPP_PIPE_Suspend(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); +HAL_StatusTypeDef HAL_DCMIPP_PIPE_Resume(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); + +/** + * @} + */ + +/** @addtogroup DCMIPP_IRQ_and_Callbacks_Functions DCMIPP IRQ and Callbacks Functions + * @brief IRQ and Callbacks functions + * @{ + */ +/** @addtogroup DCMIPP_IRQHandler_Functions IRQHandler Functions + * @{ + */ +void HAL_DCMIPP_IRQHandler(DCMIPP_HandleTypeDef *hdcmipp); +/** + * @} + */ +/** @addtogroup DCMIPP_Callback_Functions Callback Functions + * @{ + */ +void HAL_DCMIPP_PIPE_FrameEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); +void HAL_DCMIPP_PIPE_VsyncEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); +void HAL_DCMIPP_PIPE_LineEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); +void HAL_DCMIPP_PIPE_LimitEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); +void HAL_DCMIPP_PIPE_ErrorCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); +void HAL_DCMIPP_ErrorCallback(DCMIPP_HandleTypeDef *hdcmipp); +/** + * @} + */ + +/** @addtogroup DCMIPP_RegisterCallback_Functions Register Callback Functions + * @{ + */ +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_DCMIPP_RegisterCallback(DCMIPP_HandleTypeDef *hdcmipp, HAL_DCMIPP_CallbackIDTypeDef CallbackID, + pDCMIPP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DCMIPP_UnRegisterCallback(DCMIPP_HandleTypeDef *hdcmipp, + HAL_DCMIPP_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_DCMIPP_PIPE_RegisterCallback(DCMIPP_HandleTypeDef *hdcmipp, + HAL_DCMIPP_PIPE_CallbackIDTypeDef CallbackID, + pDCMIPP_PIPE_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DCMIPP_PIPE_UnRegisterCallback(DCMIPP_HandleTypeDef *hdcmipp, + HAL_DCMIPP_PIPE_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup DCMIPP_Decimation_Functions DCMIPP Decimation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetBytesDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, + uint32_t SelectStart, uint32_t SelectMode); +HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetLinesDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, + uint32_t SelectStart, uint32_t SelectMode); +/** + * @} + */ +/** @defgroup DCMIPP_Crop_Functions DCMIPP Crop Functions + * @{ + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetCropConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, + const DCMIPP_CropConfTypeDef *pCropConfig); +HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableCrop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); +HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableCrop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); +/** + * @} + */ +/** @defgroup DCMIPP_Line_Event_Functions DCMIPP Line Event Functions + * @{ + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableLineEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Line); +HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableLineEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); +/** + * @} + */ +/** @defgroup DCMIPP_LimitEvent_Functions DCMIPP Limit Event Functions + * @{ + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableLimitEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Limit); +HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableLimitEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); +/** + * @} + */ + +/** @defgroup DCMIPP_PeripheralControl_Functions DCMIPP Peripheral Control Functions + * @{ + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetFrameRate(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t FrameRate); +HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetCaptureMode(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t CaptureMode); +HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableCapture(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); +HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetMemoryAddress(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Memory, + uint32_t DstAddress); +HAL_StatusTypeDef HAL_DCMIPP_PIPE_PARALLEL_SetInputPixelFormat(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, + uint32_t InputPixelFormat); +HAL_StatusTypeDef HAL_DCMIPP_PARALLEL_SetSyncUnmask(DCMIPP_HandleTypeDef *hdcmipp, + const DCMIPP_EmbeddedSyncUnmaskTypeDef *SyncUnmask); +/** + * @} + */ + +/** @defgroup DCMIPP_Frame_Counter_Functions DCMIPP Frame Counter Functions + * @{ + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_ResetFrameCounter(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); +HAL_StatusTypeDef HAL_DCMIPP_PIPE_ReadFrameCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, + uint32_t *pCounter); +/** + * @} + */ +/** @defgroup DCMIPP_Data_Counter_Functions DCMIPP Data Counter Functions + * @{ + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_GetDataCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, + uint32_t *pCounter); +/** + * @} + */ + +/** @addtogroup DCMIPP_State_and_Error_Functions DCMIPP State and Error Functions + * @{ + */ +HAL_DCMIPP_StateTypeDef HAL_DCMIPP_GetState(const DCMIPP_HandleTypeDef *hdcmipp); +HAL_DCMIPP_PipeStateTypeDef HAL_DCMIPP_PIPE_GetState(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); +uint32_t HAL_DCMIPP_GetError(const DCMIPP_HandleTypeDef *hdcmipp); + +/** + * @} + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DCMIPP_Private_Macros DCMIPP Private Macros + * @{ + */ +#define IS_DCMIPP_PIPE(PIPE) ((PIPE) == DCMIPP_PIPE0) +#define IS_DCMIPP_FORMAT(FORMAT) (((FORMAT) == DCMIPP_FORMAT_BYTE) ||\ + ((FORMAT) == DCMIPP_FORMAT_YUV422) ||\ + ((FORMAT) == DCMIPP_FORMAT_RGB565) ||\ + ((FORMAT) == DCMIPP_FORMAT_RGB666) ||\ + ((FORMAT) == DCMIPP_FORMAT_RGB888) ||\ + ((FORMAT) == DCMIPP_FORMAT_RAW8 ) ||\ + ((FORMAT) == DCMIPP_FORMAT_RAW10 ) ||\ + ((FORMAT) == DCMIPP_FORMAT_RAW12 ) ||\ + ((FORMAT) == DCMIPP_FORMAT_RAW14 ) ||\ + ((FORMAT) == DCMIPP_FORMAT_MONOCHROME_8B) ||\ + ((FORMAT) == DCMIPP_FORMAT_MONOCHROME_10B) ||\ + ((FORMAT) == DCMIPP_FORMAT_MONOCHROME_12B) ||\ + ((FORMAT) == DCMIPP_FORMAT_MONOCHROME_14B)) + + +#define IS_DCMIPP_PCKPOLARITY(POLARITY)(((POLARITY) == DCMIPP_PCKPOLARITY_FALLING) || \ + ((POLARITY) == DCMIPP_PCKPOLARITY_RISING)) + +#define IS_DCMIPP_VSPOLARITY(POLARITY)(((POLARITY) == DCMIPP_VSPOLARITY_LOW) || \ + ((POLARITY) == DCMIPP_VSPOLARITY_HIGH)) + +#define IS_DCMIPP_HSPOLARITY(POLARITY)(((POLARITY) == DCMIPP_HSPOLARITY_LOW) || \ + ((POLARITY) == DCMIPP_HSPOLARITY_HIGH)) + + +#define IS_DCMIPP_EXTENDED_DATA_MODE(INTERFACE)(((INTERFACE) == DCMIPP_INTERFACE_8BITS ) ||\ + ((INTERFACE) == DCMIPP_INTERFACE_10BITS) ||\ + ((INTERFACE) == DCMIPP_INTERFACE_12BITS) ||\ + ((INTERFACE) == DCMIPP_INTERFACE_14BITS) ||\ + ((INTERFACE) == DCMIPP_INTERFACE_16BITS)) + + +#define IS_DCMIPP_SYNC_MODE(SYNC_MODE) (((SYNC_MODE) == DCMIPP_SYNCHRO_HARDWARE) ||\ + ((SYNC_MODE) == DCMIPP_SYNCHRO_EMBEDDED)) + +#define IS_DCMIPP_SWAP_BITS(SWAP_BITS) (((SWAP_BITS) == DCMIPP_SWAPBITS_ENABLE) ||\ + ((SWAP_BITS) == DCMIPP_SWAPBITS_DISABLE)) + +#define IS_DCMIPP_SWAP_CYCLES(SWAP_CYCLES) (((SWAP_CYCLES) == DCMIPP_SWAPCYCLES_ENABLE) ||\ + ((SWAP_CYCLES) == DCMIPP_SWAPCYCLES_DISABLE)) + + + +#define IS_DCMIPP_FRAME_RATE(FRAME_RATE) (((FRAME_RATE) == DCMIPP_FRAME_RATE_ALL) ||\ + ((FRAME_RATE) == DCMIPP_FRAME_RATE_1_OVER_2) ||\ + ((FRAME_RATE) == DCMIPP_FRAME_RATE_1_OVER_4) ||\ + ((FRAME_RATE) == DCMIPP_FRAME_RATE_1_OVER_8)) + + +#define IS_DCMIPP_CLIENT(CLIENT) (((CLIENT) == DCMIPP_CLIENT1)) + +#define IS_DCMIPP_DPREG_END(DPREG_END) ((DPREG_END) <= 0x1FU) +#define IS_DCMIPP_DPREG_START(DPREG_START) ((DPREG_START) <= 0x1FU) + +#define IS_DCMIPP_MAX_OUTSTANDING_TRANSACTIONS(OUTS_TRANS) (((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_NONE )||\ + ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_2 )||\ + ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_3 )||\ + ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_4 )) +#define IS_DCMIPP_MEMORY_PAGE_SIZE(MEMORY_PAGE_SIZE) (((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_64BYTES) ||\ + ((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_128BYTES) ||\ + ((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_256BYTES) ||\ + ((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_512BYTES) ||\ + ((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_1KBYTES) ||\ + ((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_2KBYTES) ||\ + ((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_4KBYTES) ||\ + ((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_8KBYTES)) +#define IS_DCMIPP_TRAFFIC(TRAFFIC) (((TRAFFIC) == DCMIPP_TRAFFIC_BURST_SIZE_8BYTES ) ||\ + ((TRAFFIC) == DCMIPP_TRAFFIC_BURST_SIZE_16BYTES) ||\ + ((TRAFFIC) == DCMIPP_TRAFFIC_BURST_SIZE_32BYTES) ||\ + ((TRAFFIC) == DCMIPP_TRAFFIC_BURST_SIZE_64BYTES) ||\ + ((TRAFFIC) == DCMIPP_TRAFFIC_BURST_SIZE_128BYTES)) +#define IS_DCMIPP_WLRU_RATIO(WLRU_RATIO) ((WLRU_RATIO)<= 0xFU) + +#define IS_DCMIPP_CAPTURE_MODE(CAPTURE_MODE) (((CAPTURE_MODE) == DCMIPP_MODE_CONTINUOUS)||\ + ((CAPTURE_MODE) == DCMIPP_MODE_SNAPSHOT)) + +#define IS_DCMIPP_PIPE_CROP_AREA(CROP_AREA)(((CROP_AREA) == DCMIPP_POSITIVE_AREA) ||\ + ((CROP_AREA) == DCMIPP_NEGATIVE_AREA)) + +#define IS_DCMIPP_PIPE_CROP_HSIZE(CROP_HSIZE) (((CROP_HSIZE) >= 0x1U) && ((CROP_HSIZE) <= 0xFFFU)) +#define IS_DCMIPP_PIPE_CROP_VSIZE(CROP_VSIZE) (((CROP_VSIZE) >= 0x1U) && ((CROP_VSIZE) <= 0xFFFU)) +#define IS_DCMIPP_PIPE_CROP_VSTART(CROP_VSTART) ((CROP_VSTART) <= 0xFFFU) +#define IS_DCMIPP_PIPE_CROP_HSTART(CROP_HSTART) ((CROP_HSTART) <= 0xFFFU) + +#define IS_DCMIPP_BYTE_SELECT_MODE(BYTE_SELECT) (((BYTE_SELECT) == DCMIPP_BSM_ALL) ||\ + ((BYTE_SELECT) == DCMIPP_BSM_DATA_OUT_2) ||\ + ((BYTE_SELECT) == DCMIPP_BSM_BYTE_OUT_4) ||\ + ((BYTE_SELECT) == DCMIPP_BSM_2BYTE_OUT_4)) + +#define IS_DCMIPP_BYTE_SELECT_START(BYTE_START)(((BYTE_START) == DCMIPP_OEBS_ODD) ||\ + ((BYTE_START) == DCMIPP_OEBS_EVEN)) + +#define IS_DCMIPP_LINE_SELECT_MODE(LINE_SELECT) (((LINE_SELECT) == DCMIPP_LSM_ALL) ||\ + ((LINE_SELECT) == DCMIPP_LSM_ALTERNATE_2)) + +#define IS_DCMIPP_LINE_SELECT_START(LINE__START)(((LINE__START) == DCMIPP_OELS_ODD) ||\ + ((LINE__START) == DCMIPP_OELS_EVEN)) + + +#define IS_DCMIPP_MEMORY_ADDRESS(MEMORY_ADDRESS) (((MEMORY_ADDRESS) == DCMIPP_MEMORY_ADDRESS_0) ||\ + ((MEMORY_ADDRESS) == DCMIPP_MEMORY_ADDRESS_1)) + +#define IS_DCMIPP_DATA_LIMIT(DATA_LIMIT) (((DATA_LIMIT) >=1U ) && ((DATA_LIMIT) <= 0xFFFFFFU)) + + +#define IS_DCMIPP_PIPE_MULTILINE(MULTILINE) (((MULTILINE) == DCMIPP_MULTILINE_1_LINE ) ||\ + ((MULTILINE) == DCMIPP_MULTILINE_2_LINES) ||\ + ((MULTILINE) == DCMIPP_MULTILINE_4_LINES) ||\ + ((MULTILINE) == DCMIPP_MULTILINE_8_LINES) ||\ + ((MULTILINE) == DCMIPP_MULTILINE_16_LINES) ||\ + ((MULTILINE) == DCMIPP_MULTILINE_32_LINES) ||\ + ((MULTILINE) == DCMIPP_MULTILINE_64_LINES) ||\ + ((MULTILINE) == DCMIPP_MULTILINE_128_LINES)) + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DCMIPP */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7RSxx_HAL_DCMIPP_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_def.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_def.h new file mode 100644 index 00000000000..1adf214e039 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_def.h @@ -0,0 +1,199 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_DEF_H +#define STM32H7RSxx_HAL_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" +#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ +#include +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00, + HAL_LOCKED = 0x01 +} HAL_LockTypeDef; + +/* Exported macros -----------------------------------------------------------*/ + +#if !defined(UNUSED) +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) + +#if (USE_RTOS == 1) +/* Reserved for future use */ +#error " USE_RTOS should be 0 in the current HAL release " +#else +#define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0) + +#define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) +#endif /* USE_RTOS */ + + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((packed)) +#endif /* packed */ +#elif defined (__GNUC__) /* GNU Compiler */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + +/* Macro to get buffer 32-bytes aligned (aligned to cache line width) */ +#define ALIGN_32BYTES(buf) buf __attribute__((aligned(32))) + +/* Macro to get buffer 8-bytes aligned (aligned to double-word width) */ +/* This alignment is required for double-word DMA transfers */ +#define ALIGN_8BYTES(buf) buf __attribute__((aligned(8))) + +/* Legacy macros to get variable 4-bytes aligned */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__((aligned(4))) +#endif /* __ALIGN_END */ + +/** + * @brief __RAM_FUNC definition + */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +/* ARM Compiler V6 + --------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined (__ICCARM__) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined (__GNUC__) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif /* __ARMCC_VERSION */ + +/** + * @brief __NOINLINE definition + */ +#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined (__GNUC__) +/* ARM V6 & GNU Compiler + --------------------- +*/ +#define __NOINLINE __attribute__((noinline)) + +#elif defined (__ICCARM__) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif /* __ARMCC_VERSION || __GNUC__ */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_DEF_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dma.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dma.h new file mode 100644 index 00000000000..8d517a2b78d --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dma.h @@ -0,0 +1,875 @@ +/** + ********************************************************************************************************************** + * @file stm32h7rsxx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32H7RSxx_HAL_DMA_H +#define STM32H7RSxx_HAL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + + +/* Exported types ----------------------------------------------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @brief DMA Exported Types + * @{ + */ + +/** + * @brief DMA Transfer Configuration Structure definition. + */ +typedef struct +{ + uint32_t Request; /*!< Specifies the DMA channel request. + This parameter can be a value of @ref DMA_Request_Selection */ + + uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel. + Block Hardware request feature can be used only with dedicated peripherals. + This parameter can be a value of @ref DMA_Block_Request */ + + uint32_t Direction; /*!< Specifies the transfer direction for DMA channel. + This parameter can be a value of @ref DMA_Transfer_Direction */ + + uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel. + This parameter can be a value of @ref DMA_Source_Increment_Mode */ + + uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel. + This parameter can be a value of @ref DMA_Destination_Increment_Mode */ + + uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel. + This parameter can be a value of @ref DMA_Source_Data_Width */ + + uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel. + This parameter can be a value of @ref DMA_Destination_Data_Width */ + + uint32_t Priority; /*!< Specifies the priority level for the DMA channel. + This parameter can be a value of @ref DMA_Priority_Level */ + + uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA + channel. + This parameter can be a value between 1 and 64 */ + + uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the + DMA channel. + This parameter can be a value between 1 and 64 */ + + uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports. + This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */ + + uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. + This parameter can be a value of @ref DMA_Transfer_Event_Mode */ + + uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel. + This parameter can be a value of @ref DMA_Transfer_Mode */ + +} DMA_InitTypeDef; + +/** + * @brief DMA Linked-List Configuration Structure Definition. + */ +typedef struct +{ + uint32_t Priority; /*!< Specifies the priority level for the DMA channel. + This parameter can be a value of @ref DMA_Priority_Level */ + + uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel. + This parameter can be a value of @ref DMAEx_Link_Step_Mode */ + + uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel. + This parameter can be a value of @ref DMAEx_Link_Allocated_Port */ + + uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. + This parameter can be a value of @ref DMA_Transfer_Event_Mode */ + + uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel. + This parameter can be a value of @ref DMAEx_LinkedList_Mode */ + +} DMA_InitLinkedListTypeDef; + +/** + * @brief HAL DMA State Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ + HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */ + +} HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Level Complete Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */ + +} HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callbacks IDs Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */ + HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */ + HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */ + +} HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */ + + DMA_InitTypeDef Init; /*!< DMA channel init parameters */ + + DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + uint32_t Mode; /*!< DMA transfer mode */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + __IO uint32_t ErrorCode; /*!< DMA error code */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */ + + void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */ + + void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */ + + struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */ + +} DMA_HandleTypeDef; +/** + * @} + */ + + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMA_Error_Codes DMA Error Codes + * @brief DMA Error Codes + * @{ + */ +#define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */ +#define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */ +#define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */ +#define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */ +#define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */ +#define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */ +#define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */ +#define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */ +#define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition + * @brief DMA Interrupt Enable Definition + * @{ + */ +#define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */ +#define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */ +#define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */ +#define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */ +#define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */ +#define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */ +/** + * @} + */ + +/** @defgroup DMA_Flag_Definition DMA Flag Definition + * @brief DMA Flag Definition + * @{ + */ +#define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */ +#define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */ +#define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */ +#define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */ +#define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */ +#define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */ +#define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */ +#define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */ +/** + * @} + */ + +/** @defgroup DMA_Request_Selection DMA Request Selection + * @brief DMA Request Selection + * @{ + */ +/* HPDMA1 requests */ +#define HPDMA1_REQUEST_JPEG_RX 0U /*!< HPDMA1 HW request is JPEG_DMA_RX */ +#define HPDMA1_REQUEST_JPEG_TX 1U /*!< HPDMA1 HW request is JPEG_DMA_TX */ +#define HPDMA1_REQUEST_XSPI1 2U /*!< HPDMA1 HW request is XSPI1 */ +#define HPDMA1_REQUEST_XSPI2 3U /*!< HPDMA1 HW request is XSPI2 */ +#define HPDMA1_REQUEST_SPI3_RX 4U /*!< HPDMA1 HW request is SPI3_RX */ +#define HPDMA1_REQUEST_SPI3_TX 5U /*!< HPDMA1 HW request is SPI3_TX */ +#define HPDMA1_REQUEST_SPI4_RX 6U /*!< HPDMA1 HW request is SPI4_RX */ +#define HPDMA1_REQUEST_SPI4_TX 7U /*!< HPDMA1 HW request is SPI4_TX */ +#define HPDMA1_REQUEST_ADC1 8U /*!< HPDMA1 HW request is ADC1 */ +#define HPDMA1_REQUEST_ADC2 9U /*!< HPDMA1 HW request is ADC2 */ +#define HPDMA1_REQUEST_ADF1_FLT0 10U /*!< HPDMA1 HW request is ADF1_FLT0 */ +#define HPDMA1_REQUEST_UART4_RX 11U /*!< HPDMA1 HW request is UART4_RX */ +#define HPDMA1_REQUEST_UART4_TX 12U /*!< HPDMA1 HW request is UART4_TX */ +#define HPDMA1_REQUEST_UART5_RX 13U /*!< HPDMA1 HW request is UART5_RX */ +#define HPDMA1_REQUEST_UART5_TX 14U /*!< HPDMA1 HW request is UART5_TX */ +#define HPDMA1_REQUEST_UART7_RX 15U /*!< HPDMA1 HW request is UART7_RX */ +#define HPDMA1_REQUEST_UART7_TX 16U /*!< HPDMA1 HW request is UART7_TX */ +#define HPDMA1_REQUEST_LPTIM2_IC1 17U /*!< HPDMA1 HW request is LPTIM2_IC1 */ +#define HPDMA1_REQUEST_LPTIM2_IC2 18U /*!< HPDMA1 HW request is LPTIM2_IC2 */ +#define HPDMA1_REQUEST_LPTIM2_UE 19U /*!< HPDMA1 HW request is LPTIM2_UE */ + +/* GPDMA1 requests */ +#define GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */ +#define GPDMA1_REQUEST_ADC2 1U /*!< GPDMA1 HW request is ADC2 */ +#define GPDMA1_REQUEST_CRYP_IN 2U /*!< GPDMA1 HW request is CRYP_IN */ +#define GPDMA1_REQUEST_CRYP_OUT 3U /*!< GPDMA1 HW request is CRYP_OUT */ +#define GPDMA1_REQUEST_SAES_IN 4U /*!< GPDMA1 HW request is SAES_IN */ +#define GPDMA1_REQUEST_SAES_OUT 5U /*!< GPDMA1 HW request is SAES_OUT */ +#define GPDMA1_REQUEST_HASH_IN 6U /*!< GPDMA1 HW request is HASH_IN */ +#define GPDMA1_REQUEST_TIM1_CH1 7U /*!< GPDMA1 HW request is TIM1_CH1 */ +#define GPDMA1_REQUEST_TIM1_CH2 8U /*!< GPDMA1 HW request is TIM1_CH2 */ +#define GPDMA1_REQUEST_TIM1_CH3 9U /*!< GPDMA1 HW request is TIM1_CH3 */ +#define GPDMA1_REQUEST_TIM1_CH4 10U /*!< GPDMA1 HW request is TIM1_CH4 */ +#define GPDMA1_REQUEST_TIM1_UP 11U /*!< GPDMA1 HW request is TIM1_UP */ +#define GPDMA1_REQUEST_TIM1_TRIG 12U /*!< GPDMA1 HW request is TIM1_TRIG */ +#define GPDMA1_REQUEST_TIM1_COM 13U /*!< GPDMA1 HW request is TIM1_COM */ +#define GPDMA1_REQUEST_TIM2_CH1 14U /*!< GPDMA1 HW request is TIM2_CH1 */ +#define GPDMA1_REQUEST_TIM2_CH2 15U /*!< GPDMA1 HW request is TIM2_CH2 */ +#define GPDMA1_REQUEST_TIM2_CH3 16U /*!< GPDMA1 HW request is TIM2_CH3 */ +#define GPDMA1_REQUEST_TIM2_CH4 17U /*!< GPDMA1 HW request is TIM2_CH4 */ +#define GPDMA1_REQUEST_TIM2_UP 18U /*!< GPDMA1 HW request is TIM2_UP */ +#define GPDMA1_REQUEST_TIM2_TRIG 19U /*!< GPDMA1 HW request is TIM2_TRIG */ +#define GPDMA1_REQUEST_TIM3_CH1 20U /*!< GPDMA1 HW request is TIM3_CH1 */ +#define GPDMA1_REQUEST_TIM3_CH2 21U /*!< GPDMA1 HW request is TIM3_CH2 */ +#define GPDMA1_REQUEST_TIM3_CH3 22U /*!< GPDMA1 HW request is TIM3_CH3 */ +#define GPDMA1_REQUEST_TIM3_CH4 23U /*!< GPDMA1 HW request is TIM3_CH4 */ +#define GPDMA1_REQUEST_TIM3_UP 24U /*!< GPDMA1 HW request is TIM3_UP */ +#define GPDMA1_REQUEST_TIM3_TRIG 25U /*!< GPDMA1 HW request is TIM3_TRIG */ +#define GPDMA1_REQUEST_TIM4_CH1 26U /*!< GPDMA1 HW request is TIM4_CH1 */ +#define GPDMA1_REQUEST_TIM4_CH2 27U /*!< GPDMA1 HW request is TIM4_CH2 */ +#define GPDMA1_REQUEST_TIM4_CH3 28U /*!< GPDMA1 HW request is TIM4_CH3 */ +#define GPDMA1_REQUEST_TIM4_CH4 29U /*!< GPDMA1 HW request is TIM4_CH4 */ +#define GPDMA1_REQUEST_TIM4_UP 30U /*!< GPDMA1 HW request is TIM4_UP */ +#define GPDMA1_REQUEST_TIM4_TRIG 31U /*!< GPDMA1 HW request is TIM4_TRIG */ +#define GPDMA1_REQUEST_TIM5_CH1 32U /*!< GPDMA1 HW request is TIM5_CH1 */ +#define GPDMA1_REQUEST_TIM5_CH2 33U /*!< GPDMA1 HW request is TIM5_CH2 */ +#define GPDMA1_REQUEST_TIM5_CH3 34U /*!< GPDMA1 HW request is TIM5_CH3 */ +#define GPDMA1_REQUEST_TIM5_CH4 35U /*!< GPDMA1 HW request is TIM5_CH4 */ +#define GPDMA1_REQUEST_TIM5_UP 36U /*!< GPDMA1 HW request is TIM5_UP */ +#define GPDMA1_REQUEST_TIM5_TRIG 37U /*!< GPDMA1 HW request is TIM5_TRIG */ +#define GPDMA1_REQUEST_TIM6_UP 38U /*!< GPDMA1 HW request is TIM6_UP */ +#define GPDMA1_REQUEST_TIM7_UP 39U /*!< GPDMA1 HW request is TIM7_UP */ +#define GPDMA1_REQUEST_TIM15_CH1 40U /*!< GPDMA1 HW request is TIM15_CH1 */ +#define GPDMA1_REQUEST_TIM15_CH2 41U /*!< GPDMA1 HW request is TIM15_CH2 */ +#define GPDMA1_REQUEST_TIM15_UP 42U /*!< GPDMA1 HW request is TIM15_UP */ +#define GPDMA1_REQUEST_TIM15_TRIG 43U /*!< GPDMA1 HW request is TIM15_TRIG */ +#define GPDMA1_REQUEST_TIM15_COM 44U /*!< GPDMA1 HW request is TIM15_COM */ +#define GPDMA1_REQUEST_TIM16_CH1 45U /*!< GPDMA1 HW request is TIM16_CH1 */ +#define GPDMA1_REQUEST_TIM16_UP 46U /*!< GPDMA1 HW request is TIM16_UP */ +#define GPDMA1_REQUEST_TIM16_COM 47U /*!< GPDMA1 HW request is TIM16_COM */ +#define GPDMA1_REQUEST_TIM17_CH1 48U /*!< GPDMA1 HW request is TIM17_CH1 */ +#define GPDMA1_REQUEST_TIM17_UP 49U /*!< GPDMA1 HW request is TIM17_UP */ +#define GPDMA1_REQUEST_TIM17_COM 50U /*!< GPDMA1 HW request is TIM17_COM */ +#define GPDMA1_REQUEST_SPI1_RX 51U /*!< GPDMA1 HW request is SPI1_RX */ +#define GPDMA1_REQUEST_SPI1_TX 52U /*!< GPDMA1 HW request is SPI1_TX */ +#define GPDMA1_REQUEST_SPI2_RX 53U /*!< GPDMA1 HW request is SPI2_RX */ +#define GPDMA1_REQUEST_SPI2_TX 54U /*!< GPDMA1 HW request is SPI2_TX */ +#define GPDMA1_REQUEST_SPI3_RX 55U /*!< GPDMA1 HW request is SPI3_RX */ +#define GPDMA1_REQUEST_SPI3_TX 56U /*!< GPDMA1 HW request is SPI3_TX */ +#define GPDMA1_REQUEST_SPI4_RX 57U /*!< GPDMA1 HW request is SPI4_RX */ +#define GPDMA1_REQUEST_SPI4_TX 58U /*!< GPDMA1 HW request is SPI4_TX */ +#define GPDMA1_REQUEST_SPI5_RX 59U /*!< GPDMA1 HW request is SPI5_RX */ +#define GPDMA1_REQUEST_SPI5_TX 60U /*!< GPDMA1 HW request is SPI5_TX */ +#define GPDMA1_REQUEST_SPI6_RX 61U /*!< GPDMA1 HW request is SPI6_RX */ +#define GPDMA1_REQUEST_SPI6_TX 62U /*!< GPDMA1 HW request is SPI6_TX */ +#define GPDMA1_REQUEST_SAI1_A 63U /*!< GPDMA1 HW request is SAI1_A */ +#define GPDMA1_REQUEST_SAI1_B 64U /*!< GPDMA1 HW request is SAI1_B */ +#define GPDMA1_REQUEST_SAI2_A 65U /*!< GPDMA1 HW request is SAI2_A */ +#define GPDMA1_REQUEST_SAI2_B 66U /*!< GPDMA1 HW request is SAI2_B */ +#define GPDMA1_REQUEST_I2C1_RX 67U /*!< GPDMA1 HW request is I2C1_RX */ +#define GPDMA1_REQUEST_I2C1_TX 68U /*!< GPDMA1 HW request is I2C1_TX */ +#define GPDMA1_REQUEST_I2C2_RX 69U /*!< GPDMA1 HW request is I2C2_RX */ +#define GPDMA1_REQUEST_I2C2_TX 70U /*!< GPDMA1 HW request is I2C2_TX */ +#define GPDMA1_REQUEST_I2C3_RX 71U /*!< GPDMA1 HW request is I2C3_RX */ +#define GPDMA1_REQUEST_I2C3_TX 72U /*!< GPDMA1 HW request is I2C3_TX */ +#define GPDMA1_REQUEST_USART1_RX 73U /*!< GPDMA1 HW request is USART1_RX */ +#define GPDMA1_REQUEST_USART1_TX 74U /*!< GPDMA1 HW request is USART1_TX */ +#define GPDMA1_REQUEST_USART2_RX 75U /*!< GPDMA1 HW request is USART2_RX */ +#define GPDMA1_REQUEST_USART2_TX 76U /*!< GPDMA1 HW request is USART2_TX */ +#define GPDMA1_REQUEST_USART3_RX 77U /*!< GPDMA1 HW request is USART3_RX */ +#define GPDMA1_REQUEST_USART3_TX 78U /*!< GPDMA1 HW request is USART3_TX */ +#define GPDMA1_REQUEST_UART4_RX 79U /*!< GPDMA1 HW request is UART4_RX */ +#define GPDMA1_REQUEST_UART4_TX 80U /*!< GPDMA1 HW request is UART4_TX */ +#define GPDMA1_REQUEST_UART5_RX 81U /*!< GPDMA1 HW request is UART5_RX */ +#define GPDMA1_REQUEST_UART5_TX 82U /*!< GPDMA1 HW request is UART5_TX */ +#define GPDMA1_REQUEST_UART7_RX 83U /*!< GPDMA1 HW request is UART7_RX */ +#define GPDMA1_REQUEST_UART7_TX 84U /*!< GPDMA1 HW request is UART7_TX */ +#define GPDMA1_REQUEST_UART8_RX 85U /*!< GPDMA1 HW request is UART8_RX */ +#define GPDMA1_REQUEST_UART8_TX 86U /*!< GPDMA1 HW request is UART8_TX */ +#define GPDMA1_REQUEST_CORDIC_READ 87U /*!< GPDMA1 HW request is CORDIC_READ */ +#define GPDMA1_REQUEST_CORDIC_WRITE 88U /*!< GPDMA1 HW request is CORDIC_WRITE */ +#define GPDMA1_REQUEST_LPTIM1_IC1 89U /*!< GPDMA1 HW request is LPTIM1_IC1 */ +#define GPDMA1_REQUEST_LPTIM1_IC2 90U /*!< GPDMA1 HW request is LPTIM1_IC2 */ +#define GPDMA1_REQUEST_LPTIM1_UE 91U /*!< GPDMA1 HW request is LPTIM1_UE */ +#define GPDMA1_REQUEST_LPTIM2_IC1 92U /*!< GPDMA1 HW request is LPTIM2_IC1 */ +#define GPDMA1_REQUEST_LPTIM2_IC2 93U /*!< GPDMA1 HW request is LPTIM2_IC2 */ +#define GPDMA1_REQUEST_LPTIM2_UE 94U /*!< GPDMA1 HW request is LPTIM2_UE */ +#define GPDMA1_REQUEST_SPDIF_RX_DT 95U /*!< GPDMA1 HW request is SPDIF_RX_DT */ +#define GPDMA1_REQUEST_SPDIF_RX_CS 96U /*!< GPDMA1 HW request is SPDIF_RX_CS */ +#define GPDMA1_REQUEST_ADF1_FLT0 97U /*!< GPDMA1 HW request is ADF1_FLT0 */ +#define GPDMA1_REQUEST_UCPD1_TX 98U /*!< GPDMA1 HW request is UCPD1_TX */ +#define GPDMA1_REQUEST_UCPD1_RX 99U /*!< GPDMA1 HW request is UCPD1_RX */ +#define GPDMA1_REQUEST_PSSI 100U /*!< GPDMA1 HW request is PSSI */ +#define GPDMA1_REQUEST_LPUART1_RX 101U /*!< GPDMA1 HW request is LPUART1_RX */ +#define GPDMA1_REQUEST_LPUART1_TX 102U /*!< GPDMA1 HW request is LPUART1_TX */ +#define GPDMA1_REQUEST_LPTIM3_IC1 103U /*!< GPDMA1 HW request is LPTIM3_IC1 */ +#define GPDMA1_REQUEST_LPTIM3_IC2 104U /*!< GPDMA1 HW request is LPTIM3_IC2 */ +#define GPDMA1_REQUEST_LPTIM3_UE 105U /*!< GPDMA1 HW request is LPTIM3_UE */ +#define GPDMA1_REQUEST_I3C1_RX 106U /*!< GPDMA1 HW request is I3C1_RX */ +#define GPDMA1_REQUEST_I3C1_TX 107U /*!< GPDMA1 HW request is I3C1_TX */ +#define GPDMA1_REQUEST_I3C1_TC 108U /*!< GPDMA1 HW request is I3C1_TC */ +#define GPDMA1_REQUEST_I3C1_RS 109U /*!< GPDMA1 HW request is I3C1_RS */ + +#define GPDMA1_MAX_REQUEST 109U + +/* Software request */ +#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ +/** + * @} + */ + +/** @defgroup DMA_Block_Request DMA Block Request + * @brief DMA Block Request + * @{ + */ +#define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */ +#define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Direction DMA Transfer Direction + * @brief DMA transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode + * @brief DMA Source Increment Mode + * @{ + */ +#define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */ +#define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */ +/** + * @} + */ + +/** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode + * @brief DMA Destination Increment Mode + * @{ + */ +#define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */ +#define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */ +/** + * @} + */ + +/** @defgroup DMA_Source_Data_Width DMA Source Data Width + * @brief DMA Source Data Width + * @{ + */ +#define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */ +#define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */ +#define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */ +#define DMA_SRC_DATAWIDTH_DOUBLEWORD DMA_CTR1_SDW_LOG2 /*!< Source data width : DoubleWord */ +/** + * @} + */ + +/** @defgroup DMA_Destination_Data_Width DMA destination Data Width + * @brief DMA destination Data Width + * @{ + */ +#define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */ +#define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */ +#define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */ +#define DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2 /*!< Destination data width : DoubleWord */ + +/** + * @} + */ + +/** @defgroup DMA_Priority_Level DMA Priority Level + * @brief DMA Priority Level + * @{ + */ +#define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */ +#define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */ +#define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */ +#define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port + * @brief DMA Transfer Allocated Port + * @{ + */ +#define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */ +#define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */ +#define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */ +#define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode + * @brief DMA Transfer Event Mode + * @{ + */ +#define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the + HT event is generated at the half of each block */ +#define DMA_TCEM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC event is generated at the end of the repeated block + and the HT event is generated at the half of the repeated + block */ +#define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list + item and the HT event is generated at the half of each + linked-list item */ +#define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last + linked-list item and the HT event is generated at the half + of the last linked-list item */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Mode DMA Transfer Mode + * @brief DMA Transfer Mode + * @{ + */ +#define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */ +#define DMA_PFCTRL DMA_CTR2_PFREQ /*!< HW request peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_Channel_Attributes DMA Channel Attributes + * @brief DMA Channel Privilege Attribute + * @{ + */ + + +#define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | (1U<State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__ : DMA handle. + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__ : DMA handle. + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET)) + +/** + * @brief Get the DMA channel pending flags. + * @param __HANDLE__ : DMA handle. + * @param __FLAG__ : Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TC : Transfer Complete flag. + * @arg DMA_FLAG_HT : Half Transfer Complete flag. + * @arg DMA_FLAG_DTE : Data Transfer Error flag. + * @arg DMA_FLAG_ULE : Update linked-list Error flag. + * @arg DMA_FLAG_USE : User Setting Error flag. + * @arg DMA_FLAG_TO : Trigger Overrun flag. + * @arg DMA_FLAG_SUSP : Completed Suspension flag. + * @arg DMA_FLAG_IDLEF : Idle flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \ + ((__HANDLE__)->Instance->CSR & (__FLAG__)) + +/** + * @brief Clear the DMA Channel pending flags. + * @param __HANDLE__ : DMA handle. + * @param __FLAG__ : Specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TC : Transfer Complete flag. + * @arg DMA_FLAG_HT : Half Transfer Complete flag. + * @arg DMA_FLAG_DTE : Data Transfer Error flag. + * @arg DMA_FLAG_ULE : Update Linked-List Error flag. + * @arg DMA_FLAG_USE : User Setting Error flag. + * @arg DMA_FLAG_TO : Trigger Overrun flag. + * @arg DMA_FLAG_SUSP : Completed Suspension flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + ((__HANDLE__)->Instance->CFCR = (__FLAG__)) + +/** + * @brief Enable the specified DMA Channel interrupts. + * @param __HANDLE__ : DMA handle. + * @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC : Transfer Complete interrupt. + * @arg DMA_IT_HT : Half Transfer Complete interrupt. + * @arg DMA_IT_DTE : Data Transfer Error interrupt. + * @arg DMA_IT_ULE : Update Linked-List Error interrupt. + * @arg DMA_IT_USE : User Setting Error interrupt. + * @arg DMA_IT_TO : Trigger Overrun interrupt. + * @arg DMA_IT_SUSP : Completed Suspension interrupt. + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DMA Channel interrupts. + * @param __HANDLE__ : DMA handle. + * @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC : Transfer Complete interrupt. + * @arg DMA_IT_HT : Half Transfer Complete interrupt. + * @arg DMA_IT_DTE : Data Transfer Error interrupt. + * @arg DMA_IT_ULE : Update Linked-List Error interrupt. + * @arg DMA_IT_USE : User Setting Error interrupt. + * @arg DMA_IT_TO : Trigger Overrun interrupt. + * @arg DMA_IT_SUSP : Completed Suspension interrupt. + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified DMA Channel interrupt is enabled or not. + * @param __HANDLE__ : DMA handle. + * @param __INTERRUPT__ : specifies the DMA interrupt source to check. + * @arg DMA_IT_TC : Transfer Complete interrupt. + * @arg DMA_IT_HT : Half Transfer Complete interrupt. + * @arg DMA_IT_DTE : Data Transfer Error interrupt. + * @arg DMA_IT_ULE : Update Linked-List Error interrupt. + * @arg DMA_IT_USE : User Setting Error interrupt. + * @arg DMA_IT_TO : Trigger Overrun interrupt. + * @arg DMA_IT_SUSP : Completed Suspension interrupt. + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Writes the block number of bytes to be transferred from the source on the DMA Channel. + * @param __HANDLE__ : DMA handle. + * @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535). + */ +#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \ + MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__)) + +/** + * @brief Returns the number of remaining data bytes in the current DMA Channel transfer. + * @param __HANDLE__ : DMA handle. + * @retval The number of remaining data units in the current DMA Stream transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) \ + (((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT) +/** + * @} + */ + + +/* Include DMA HAL Extension module */ +#include "stm32h7rsxx_hal_dma_ex.h" + + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @brief DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and De-Initialization Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions + * @brief I/O Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, + HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID, + void (*const pCallback)(DMA_HandleTypeDef *const _hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 State and Error Functions + * @brief State and Error Functions + * @{ + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions + * @brief DMA Attributes Functions + * @{ + */ + +HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, + uint32_t ChannelAttributes); +HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, + uint32_t *const pChannelAttributes); + +HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); +HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, + uint32_t *const pLockState); + + +/** + * @} + */ + +/** + * @} + */ + + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @brief DMA Private Constants + * @{ + */ +#define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */ +#define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */ +#define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */ +#define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */ +#define DMA_CHANNEL_ATTR_PRIV_MASK (0x01000000U) /* DMA channel privilege */ +#define DMA_CHANNEL_PRIV_VAL_POS 0U +#define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */ +#define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */ +/** + * @} + */ + + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @brief DMA Private Macros + * @{ + */ +#define GET_DMA_INSTANCE(__HANDLE__) \ + ((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK))) + +#define GET_DMA_CHANNEL(__HANDLE__) \ + ((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE) + +#define IS_DMA_MODE(MODE) \ + (((MODE) == DMA_NORMAL) || \ + ((MODE) == DMA_PFCTRL)) + +#define IS_DMA_DIRECTION(DIRECTION) \ + (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_LEVEL_COMPLETE(LEVEL) \ + (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \ + ((LEVEL) == HAL_DMA_HALF_TRANSFER)) + +#define IS_DMA_SOURCE_INC(INC) \ + (((INC) == DMA_SINC_FIXED) || \ + ((INC) == DMA_SINC_INCREMENTED)) + +#define IS_DMA_DESTINATION_INC(INC) \ + (((INC) == DMA_DINC_FIXED) || \ + ((INC) == DMA_DINC_INCREMENTED)) + +#define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \ + (((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \ + ((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \ + ((WIDTH) == DMA_SRC_DATAWIDTH_WORD) || \ + ((WIDTH) == DMA_SRC_DATAWIDTH_DOUBLEWORD)) + +#define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \ + (((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \ + ((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \ + ((WIDTH) == DMA_DEST_DATAWIDTH_WORD) || \ + ((WIDTH) == DMA_DEST_DATAWIDTH_DOUBLEWORD)) + +#define IS_DMA_BURST_LENGTH(LENGTH) \ + (((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \ + ((LENGTH) <= DMA_CHANNEL_BURST_MAX)) + +#define IS_DMA_PRIORITY(PRIORITY) \ + (((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \ + ((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \ + ((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \ + ((PRIORITY) == DMA_HIGH_PRIORITY)) + +#define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \ + (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U) + +#define IS_DMA_REQUEST(REQUEST) \ + (((REQUEST) == DMA_REQUEST_SW) || \ + ((REQUEST) <= GPDMA1_REQUEST_I3C1_RS)) + +#define IS_DMA_BLOCK_HW_REQUEST(MODE) \ + (((MODE) == DMA_BREQ_SINGLE_BURST) || \ + ((MODE) == DMA_BREQ_BLOCK)) + +#define IS_DMA_TCEM_EVENT_MODE(MODE) \ + (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ + ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) + +#define IS_DMA_BLOCK_SIZE(SIZE) \ + (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT)) + +#define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \ + (((INSTANCE)->MISR & (GLOBAL_FLAG))) +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ + (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ + ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) + +/** + * @} + */ + + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_DMA_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dma2d.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dma2d.h new file mode 100644 index 00000000000..86559f0055d --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dma2d.h @@ -0,0 +1,715 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_dma2d.h + * @author MCD Application Team + * @brief Header file of DMA2D HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_DMA2D_H +#define STM32H7RSxx_HAL_DMA2D_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#if defined (DMA2D) + +/** @addtogroup DMA2D DMA2D + * @brief DMA2D HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMA2D_Exported_Types DMA2D Exported Types + * @{ + */ +#define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ + +/** + * @brief DMA2D CLUT Structure definition + */ +typedef struct +{ + uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ + + uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. + This parameter can be one value of @ref DMA2D_CLUT_CM. */ + + uint32_t Size; /*!< Configures the DMA2D CLUT size. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ +} DMA2D_CLUTCfgTypeDef; + +/** + * @brief DMA2D Init structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Configures the DMA2D transfer mode. + This parameter can be one value of @ref DMA2D_Mode. */ + + uint32_t ColorMode; /*!< Configures the color format of the output image. + This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ + + uint32_t OutputOffset; /*!< Specifies the Offset value. + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x3FFF. */ + uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. + This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ + + uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) + for the output pixel format converter. + This parameter can be one value of @ref DMA2D_RB_Swap. */ + + + uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). + This parameter can be one value of @ref DMA2D_Bytes_Swap. */ + + uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. + This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ + +} DMA2D_InitTypeDef; + + +/** + * @brief DMA2D Layer structure definition + */ +typedef struct +{ + uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x3FFF. */ + + uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. + This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ + + uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. + This parameter can be one value of @ref DMA2D_Alpha_Mode. */ + + uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value + in case of A8 or A4 color mode. + This parameter must be a number between Min_Data = 0x00 + and Max_Data = 0xFF except for the color modes detailed below. + @note In case of A8 or A4 color mode (ARGB), + this parameter must be a number between + Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where + - InputAlpha[24:31] is the alpha value ALPHA[0:7] + - InputAlpha[16:23] is the red value RED[0:7] + - InputAlpha[8:15] is the green value GREEN[0:7] + - InputAlpha[0:7] is the blue value BLUE[0:7]. */ + uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. + This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ + + uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). + This parameter can be one value of @ref DMA2D_RB_Swap. */ + + uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode + This parameter can be one value of @ref DMA2D_Chroma_Sub_Sampling */ + +} DMA2D_LayerCfgTypeDef; + +/** + * @brief HAL DMA2D State structures definition + */ +typedef enum +{ + HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ + HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ + HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ +} HAL_DMA2D_StateTypeDef; + +/** + * @brief DMA2D handle Structure definition + */ +typedef struct __DMA2D_HandleTypeDef +{ + DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ + + DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ + + void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */ + + void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */ + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */ + + void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */ + + void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */ + + void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */ + +#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ + + DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ + + HAL_LockTypeDef Lock; /*!< DMA2D lock. */ + + __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ + + __IO uint32_t ErrorCode; /*!< DMA2D error code. */ +} DMA2D_HandleTypeDef; + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DMA2D Callback pointer definition + */ +typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */ +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants + * @{ + */ + +/** @defgroup DMA2D_Error_Code DMA2D Error Code + * @{ + */ +#define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ +#define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ +#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup DMA2D_Mode DMA2D Mode + * @{ + */ +#define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ +#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ +#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ +#define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ +#define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ +#define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ +/** + * @} + */ + +/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode + * @{ + */ +#define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ +#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ +#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ +#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ +#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ +/** + * @} + */ + +/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode + * @{ + */ +#define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ +#define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ +#define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ +#define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ +#define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ +#define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ +#define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ +#define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ +#define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ +#define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ +#define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ +#define DMA2D_INPUT_YCBCR 0x0000000BU /*!< YCbCr color mode */ +/** + * @} + */ + +/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode + * @{ + */ +#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ +#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ +#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value + with original alpha channel value */ +/** + * @} + */ + +/** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion + * @{ + */ +#define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ +#define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */ +/** + * @} + */ + +/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap + * @{ + */ +#define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */ +#define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */ +/** + * @} + */ + + + +/** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode + * @{ + */ +#define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */ +#define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ +/** + * @} + */ + +/** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap + * @{ + */ +#define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */ +#define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ +/** + * @} + */ + +/** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling + * @{ + */ +#define DMA2D_NO_CSS 0x00000000U /*!< No chroma sub-sampling 4:4:4 */ +#define DMA2D_CSS_422 0x00000001U /*!< chroma sub-sampling 4:2:2 */ +#define DMA2D_CSS_420 0x00000002U /*!< chroma sub-sampling 4:2:0 */ +/** + * @} + */ + +/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode + * @{ + */ +#define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ +#define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ +/** + * @} + */ + +/** @defgroup DMA2D_Interrupts DMA2D Interrupts + * @{ + */ +#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ +#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ +#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ +#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ +#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ +#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ +/** + * @} + */ + +/** @defgroup DMA2D_Flags DMA2D Flags + * @{ + */ +#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ +#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ +#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ +#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ +#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ +#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ +/** + * @} + */ + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DMA2D common Callback ID enumeration definition + */ +typedef enum +{ + HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ + HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ + HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ + HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ + HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ + HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ +} HAL_DMA2D_CallbackIDTypeDef; +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + + +/** + * @} + */ +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros + * @{ + */ + +/** @brief Reset DMA2D handle state + * @param __HANDLE__ specifies the DMA2D handle. + * @retval None + */ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + }while(0) +#else +#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + + +/** + * @brief Enable the DMA2D. + * @param __HANDLE__ DMA2D handle + * @retval None. + */ +#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) + + +/* Interrupt & Flag management */ +/** + * @brief Get the DMA2D pending flags. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ flag to check. + * This parameter can be any combination of the following values: + * @arg DMA2D_FLAG_CE: Configuration error flag + * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag + * @arg DMA2D_FLAG_CAE: CLUT access error flag + * @arg DMA2D_FLAG_TW: Transfer Watermark flag + * @arg DMA2D_FLAG_TC: Transfer complete flag + * @arg DMA2D_FLAG_TE: Transfer error flag + * @retval The state of FLAG. + */ +#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) + +/** + * @brief Clear the DMA2D pending flags. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA2D_FLAG_CE: Configuration error flag + * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag + * @arg DMA2D_FLAG_CAE: CLUT access error flag + * @arg DMA2D_FLAG_TW: Transfer Watermark flag + * @arg DMA2D_FLAG_TC: Transfer complete flag + * @arg DMA2D_FLAG_TE: Transfer error flag + * @retval None + */ +#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) + +/** + * @brief Enable the specified DMA2D interrupts. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DMA2D_IT_CE: Configuration error interrupt mask + * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask + * @arg DMA2D_IT_CAE: CLUT access error interrupt mask + * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask + * @arg DMA2D_IT_TC: Transfer complete interrupt mask + * @arg DMA2D_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DMA2D interrupts. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg DMA2D_IT_CE: Configuration error interrupt mask + * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask + * @arg DMA2D_IT_CAE: CLUT access error interrupt mask + * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask + * @arg DMA2D_IT_TC: Transfer complete interrupt mask + * @arg DMA2D_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified DMA2D interrupt source is enabled or not. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA2D_IT_CE: Configuration error interrupt mask + * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask + * @arg DMA2D_IT_CAE: CLUT access error interrupt mask + * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask + * @arg DMA2D_IT_TC: Transfer complete interrupt mask + * @arg DMA2D_IT_TE: Transfer error interrupt mask + * @retval The state of INTERRUPT source. + */ +#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions + * @{ + */ + +/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, + pDMA2D_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + +/** + * @} + */ + + +/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, + uint32_t DstAddress, uint32_t Width, uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, + uint32_t DstAddress, uint32_t Width, uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); +void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); + +/** + * @} + */ + +/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions *************************************************/ +HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); +HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); + +/** + * @} + */ + +/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State functions ***************************************************/ +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d); +uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants + * @{ + */ + +/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark + * @{ + */ +#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ +/** + * @} + */ + +/** @defgroup DMA2D_Color_Value DMA2D Color Value + * @{ + */ +#define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ +/** + * @} + */ + +/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers + * @{ + */ +#define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ +/** + * @} + */ + +/** @defgroup DMA2D_Layers DMA2D Layers + * @{ + */ +#define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ +#define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ +/** + * @} + */ + +/** @defgroup DMA2D_Offset DMA2D Offset + * @{ + */ +#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ +/** + * @} + */ + +/** @defgroup DMA2D_Size DMA2D Size + * @{ + */ +#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ +#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ +/** + * @} + */ + +/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size + * @{ + */ +#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ +/** + * @} + */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA2D_Private_Macros DMA2D Private Macros + * @{ + */ +#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\ + || ((LAYER) == DMA2D_FOREGROUND_LAYER)) + +#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ + ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ + ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) + +#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) + +#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) +#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) +#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) +#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) + +#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ + ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ + ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ + ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ + ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ + ((INPUT_CM) == DMA2D_INPUT_L8) || \ + ((INPUT_CM) == DMA2D_INPUT_AL44) || \ + ((INPUT_CM) == DMA2D_INPUT_AL88) || \ + ((INPUT_CM) == DMA2D_INPUT_L4) || \ + ((INPUT_CM) == DMA2D_INPUT_A8) || \ + ((INPUT_CM) == DMA2D_INPUT_A4) || \ + ((INPUT_CM) == DMA2D_INPUT_YCBCR)) + +#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ + ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ + ((AlphaMode) == DMA2D_COMBINE_ALPHA)) + +#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ + ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) + +#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ + ((RB_Swap) == DMA2D_RB_SWAP)) + +#define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ + ((LOM) == DMA2D_LOM_BYTES)) + +#define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ + ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) + +#define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS) || \ + ((CSS) == DMA2D_CSS_422) || \ + ((CSS) == DMA2D_CSS_420)) + +#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) +#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) +#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) +#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ + ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ + ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) +#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ + ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ + ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (DMA2D) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_DMA2D_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dma_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dma_ex.h new file mode 100644 index 00000000000..2bcae71eb57 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dma_ex.h @@ -0,0 +1,719 @@ +/** + ********************************************************************************************************************** + * @file stm32h7rsxx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32H7RSxx_HAL_DMA_EX_H +#define STM32H7RSxx_HAL_DMA_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @brief DMAEx Exported types + * @{ + */ + +/** + * @brief DMAEx Data Handling Configuration Structure Definition. + */ +typedef struct +{ + uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode. + This parameter can be a value of @ref DMAEx_Data_Exchange */ + + uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode + This parameter can be a value of @ref DMAEx_Data_Alignment */ + +} DMA_DataHandlingConfTypeDef; + +/** + * @brief DMAEx Trigger Configuration Structure Definition. + */ +typedef struct +{ + uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode. + This parameter can be a value of @ref DMAEx_Trigger_Mode */ + + uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity. + This parameter can be a value of @ref DMAEx_Trigger_Polarity */ + + uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection. + This parameter can be a value of @ref DMAEx_Trigger_Selection */ + +} DMA_TriggerConfTypeDef; + +/** + * @brief DMAEx Repeated Block Configuration Structure Definition. + */ +typedef struct +{ + uint32_t RepeatCount; /*!< Specifies the DMA channel repeat count (the number of repetitions of block). + This parameter can be a value between 1 and 2048 */ + + int32_t SrcAddrOffset; /*!< Specifies the DMA channel single/burst source address offset : + This parameter can be a value between -8191 and 8191. + * If source address offset > 0 => Increment the source address by offset from where + the last single/burst transfer ends. + * If source address offset < 0 => Decrement the source address by offset from where + the last single/burst transfer ends. + * If source address offset == 0 => The next single/burst source address starts from + where the last transfer ends */ + + int32_t DestAddrOffset; /*!< Specifies the DMA channel single/burst destination address offset signed value : + This parameter can be a value between -8191 and 8191. + * If destination address offset > 0 => Increment the destination address by offset + from where the last single/burst transfer ends. + * If destination address offset < 0 => Decrement the destination address by offset + from where the last single/burst transfer ends. + * If destination address offset == 0 => The next single/burst destination address + starts from where the last transfer ends. */ + + int32_t BlkSrcAddrOffset; /*!< Specifies the DMA channel block source address offset signed value : + This parameter can be a value between -65535 and 65535. + * If block source address offset > 0 => Increment the block source address by offset + from where the last block ends. + * If block source address offset < 0 => Decrement the next block source address by + offset from where the last block ends. + * If block source address offset == 0 => the next block source address starts from + where the last block ends */ + + int32_t BlkDestAddrOffset; /*!< Specifies the DMA channel block destination address offset signed value : + This parameter can be a value between -65535 and 65535. + * If block destination address offset > 0 => Increment the block destination address + by offset from where the last block ends. + * If block destination address offset < 0 => Decrement the next block destination + address by offset from where the last block ends. + * If block destination address offset == 0 => the next block destination address + starts from where the last block ends */ + +} DMA_RepeatBlockConfTypeDef; + +/** + * @brief DMAEx Queue State Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */ + HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */ + HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */ + +} HAL_DMA_QStateTypeDef; + +/** + * @brief DMAEx Linked-List Node Configuration Structure Definition. + */ +typedef struct +{ + uint32_t NodeType; /*!< Specifies the DMA channel node type. + This parameter can be a value of @ref DMAEx_Node_Type */ + + DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */ + + DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */ + + DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */ + + DMA_RepeatBlockConfTypeDef RepeatBlockConfig; /*!< Specifies the DMA channel repeated block configuration */ + + uint32_t SrcAddress; /*!< Specifies the source memory address */ + uint32_t DstAddress; /*!< Specifies the destination memory address */ + uint32_t DataSize; /*!< Specifies the source data size in bytes */ + +} DMA_NodeConfTypeDef; + +/** + * @brief DMAEx Linked-List Node Structure Definition. + */ +typedef struct +{ + uint32_t LinkRegisters[8U]; /*!< Physical Node register description */ + uint32_t NodeInfo; /*!< Node information */ + +} DMA_NodeTypeDef; + +/** + * @brief DMAEx Linked-List Queue Structure Definition. + */ +typedef struct __DMA_QListTypeDef +{ + DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */ + + DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */ + + uint32_t NodeNumber; /*!< Specifies the queue node number */ + + __IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */ + + __IO uint32_t ErrorCode; /*!< Specifies the queue error code */ + + __IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */ + +} DMA_QListTypeDef; +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @brief DMAEx Exported Constants + * @{ + */ + +/** @defgroup Queue_Error_Codes Queue Error Codes + * @brief Queue Error Codes + * @{ + */ +#define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */ +#define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */ +#define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */ +#define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization + and queue circular types are incompatible */ +#define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */ +#define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */ +/** + * @} + */ + +/** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode + * @brief DMAEx LinkedList Mode + * @{ + */ +#define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */ +#define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */ +/** + * @} + */ + +/** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment + * @brief DMAEx Data Alignment + * @{ + */ +#define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width + => Right aligned padded with 0 up to destination data + width */ +#define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width + => Right aligned left Truncated down to destination + data width */ +#define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width + => Right Aligned padded with sign extended up to + destination data width */ +#define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width + => Left Aligned Right Truncated down to the + destination data width */ +#define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width + => Packed at the destination data width */ +#define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width + => Unpacked at the destination data width */ +/** + * @} + */ + +/** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange + * @brief DMAEx Data Exchange + * @{ + */ +#define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */ +#define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */ +#define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */ +#define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */ +#define DMA_EXCHANGE_DEST_WORD DMA_CTR1_DWX /*!< Destination Word exchange when destination data width is > Word */ +/** + * @} + */ + +/** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity + * @brief DMAEx Trigger Polarity + * @{ + */ +#define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */ +#define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */ +#define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */ +/** + * @} + */ + +/** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode + * @brief DMAEx Trigger Mode + * @{ + */ +#define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */ +#define DMA_TRIGM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) one hit trigger */ +#define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */ +#define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */ +/** + * @} + */ + +/** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection + * @brief DMAEx Trigger Selection + * @{ + */ +/* HPDMA1 triggers */ +#define HPDMA1_TRIGGER_DCMIPP_EVT_FRAMEEND 0U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_FRAMEEND */ +#define HPDMA1_TRIGGER_DCMIPP_EVT_HSYNC 1U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_HSYNC */ +#define HPDMA1_TRIGGER_DCMIPP_EVT_LINEEND 2U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_LINEEND */ +#define HPDMA1_TRIGGER_DCMIPP_EVT_VSYNC 3U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_VSYNC */ +#define HPDMA1_TRIGGER_DMA2D_CTC_FLAG 4U /*!< HPDMA1 HW Trigger signal is DMA2D_CTC_FLAG */ +#define HPDMA1_TRIGGER_DMA2D_TC_FLAG 5U /*!< HPDMA1 HW Trigger signal is DMA2D_TC_FLAG */ +#define HPDMA1_TRIGGER_DMA2D_TW_FLAG 6U /*!< HPDMA1 HW Trigger signal is DMA2D_TW_FLAG */ +#define HPDMA1_TRIGGER_JPEG_EOC_FLAG 7U /*!< HPDMA1 HW Trigger signal is JPEG_EOC_FLAG */ +#define HPDMA1_TRIGGER_JPEG_IFNF_FLAG 8U /*!< HPDMA1 HW Trigger signal is JPEG_IFNF_FLAG */ +#define HPDMA1_TRIGGER_JPEG_IFT_FLAG 9U /*!< HPDMA1 HW Trigger signal is JPEG_IFT_FLAG */ +#define HPDMA1_TRIGGER_JPEG_OFNE_FLAG 10U /*!< HPDMA1 HW Trigger signal is JPEG_OFNE_FLAG */ +#define HPDMA1_TRIGGER_JPEG_OFT_FLAG 11U /*!< HPDMA1 HW Trigger signal is JPEG_OFT_FLAG */ +#define HPDMA1_TRIGGER_LCD 12U /*!< HPDMA1 HW Trigger signal is LCD */ +#define HPDMA1_TRIGGER_GPU2D1_GP_FLAG0 13U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG0 */ +#define HPDMA1_TRIGGER_GPU2D1_GP_FLAG1 14U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG1 */ +#define HPDMA1_TRIGGER_GPU2D1_GP_FLAG2 15U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG2 */ +#define HPDMA1_TRIGGER_GPU2D1_GP_FLAG3 16U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG3 */ +#define HPDMA1_TRIGGER_GFXTIM_0_EVT_4 17U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_4 */ +#define HPDMA1_TRIGGER_GFXTIM_0_EVT_3 18U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_3 */ +#define HPDMA1_TRIGGER_GFXTIM_0_EVT_2 19U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_2 */ +#define HPDMA1_TRIGGER_GFXTIM_0_EVT_1 20U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_1 */ +#define HPDMA1_TRIGGER_GPDMA1_CH0_TCF 21U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH1_TCF 22U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH2_TCF 23U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH3_TCF 24U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH4_TCF 25U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH5_TCF 26U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH6_TCF 27U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH7_TCF 28U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH8_TCF 29U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH9_TCF 30U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH10_TCF 31U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH11_TCF 32U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH12_TCF 33U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH13_TCF 34U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH14_TCF 35U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ +#define HPDMA1_TRIGGER_GPDMA1_CH15_TCF 36U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH0_TCF 37U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH1_TCF 38U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH2_TCF 39U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH3_TCF 40U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH4_TCF 41U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH5_TCF 42U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH6_TCF 43U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH7_TCF 44U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH8_TCF 45U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH9_TCF 46U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH10_TCF 47U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH11_TCF 48U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH12_TCF 49U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH13_TCF 50U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH14_TCF 51U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */ +#define HPDMA1_TRIGGER_HPDMA1_CH15_TCF 52U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */ + +/* GPDMA1 triggers */ +#define GPDMA1_TRIGGER_HPDMA1_CH0_TCF 0U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH1_TCF 1U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH2_TCF 2U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH3_TCF 3U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH4_TCF 4U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH5_TCF 5U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH6_TCF 6U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH7_TCF 7U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH8_TCF 8U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH9_TCF 9U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH10_TCF 10U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH11_TCF 11U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH12_TCF 12U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH13_TCF 13U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH14_TCF 14U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */ +#define GPDMA1_TRIGGER_HPDMA1_CH15_TCF 15U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */ +#define GPDMA1_TRIGGER_LPTIM1_CH1 16U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define GPDMA1_TRIGGER_LPTIM1_CH2 17U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define GPDMA1_TRIGGER_LPTIM2_CH1 18U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ +#define GPDMA1_TRIGGER_LPTIM2_CH2 19U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ +#define GPDMA1_TRIGGER_LPTIM3_CH1 20U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */ +#define GPDMA1_TRIGGER_LPTIM3_CH2 21U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */ +#define GPDMA1_TRIGGER_LPTIM4_OUT 22U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */ +#define GPDMA1_TRIGGER_LPTIM5_OUT 23U /*!< GPDMA1 HW Trigger signal is LPTIM5_OUT */ +#define GPDMA1_TRIGGER_EXTIT0_SYNC 24U /*!< GPDMA1 HW Trigger signal is EXTIT0_SYNC */ +#define GPDMA1_TRIGGER_RTC_WKUP 25U /*!< GPDMA1 HW Trigger signal is RTC_WKUP */ +#define GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC 26U /*!< GPDMA1 HW Trigger signal is R_WUP_ASYNC */ +#define GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC 27U /*!< GPDMA1 HW Trigger signal is T_WUP_ASYNC */ +#define GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 28U /*!< GPDMA1 HW Trigger signal is SPI6_OR_SPI6_AIT_SYNC */ +#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 34U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 35U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 36U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH8_TCF 37U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH9_TCF 38U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH10_TCF 39U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH11_TCF 40U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH12_TCF 41U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH13_TCF 42U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH14_TCF 43U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH15_TCF 44U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ +#define GPDMA1_TRIGGER_TIM1_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO */ +#define GPDMA1_TRIGGER_TIM1_TRGO2 46U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO2 */ +#define GPDMA1_TRIGGER_TIM2_TRGO 47U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ +#define GPDMA1_TRIGGER_TIM3_TRGO 48U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ +#define GPDMA1_TRIGGER_TIM4_TRGO 49U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ +#define GPDMA1_TRIGGER_TIM5_TRGO 50U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ +#define GPDMA1_TRIGGER_TIM6_TRGO 51U /*!< GPDMA1 HW Trigger signal is TIM6_TRGO */ +#define GPDMA1_TRIGGER_TIM7_TRGO 52U /*!< GPDMA1 HW Trigger signal is TIM7_TRGO */ +#define GPDMA1_TRIGGER_TIM9_TRGO 53U /*!< GPDMA1 HW Trigger signal is TIM9_TRGO */ +#define GPDMA1_TRIGGER_TIM12_TRGO 54U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */ +#define GPDMA1_TRIGGER_TIM15_TRGO 55U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ + +#define GPDMA1_MAX_TRIGGER 55U +/** + * @} + */ + +/** @defgroup DMAEx_Node_Type DMAEx Node Type + * @brief DMAEx Node Type + * @{ + */ +#define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */ +#define DMA_GPDMA_2D_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the GPDMA 2 dimension addressing node type */ +#define DMA_HPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_HPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the HPDMA linear addressing node type */ +#define DMA_HPDMA_2D_NODE (DMA_CHANNEL_TYPE_HPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the HPDMA 2 dimension addressing node type */ +/** + * @} + */ + +/** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port + * @brief DMAEx Linked-List Allocated Port + * @{ + */ +#define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */ +#define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */ +/** + * @} + */ + +/** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode + * @brief DMAEx Link Step Mode + * @{ + */ +#define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */ +#define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @brief DMAEx Exported functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions + * @brief Linked-List Initialization and De-Initialization Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions + * @brief Linked-List IO Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions + * @brief Linked-List Management Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode); +HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode); + +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pPrevNode, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); + +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNode); +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pOldNode, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); + +HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, + DMA_NodeTypeDef const *const pPrevNode, + DMA_QListTypeDef *const pDestQList); +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList); +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList); + +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pFirstCircularNode); +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, + DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions + * @brief Data Handling, Repeated Block and Trigger Configuration Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, + DMA_DataHandlingConfTypeDef const *const pConfigDataHandling); +HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, + DMA_TriggerConfTypeDef const *const pConfigTrigger); +HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, + DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions + * @brief Suspend and Resume Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function + * @brief FIFO Status Function + * @{ + */ +uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Types DMAEx Private Types + * @brief DMAEx Private Types + * @{ + */ + +/** + * @brief DMA Node in Queue Information Structure Definition. + */ +typedef struct +{ + uint32_t cllr_offset; /* CLLR register offset */ + + uint32_t previousnode_addr; /* Previous node address */ + + uint32_t currentnode_pos; /* Current node position */ + + uint32_t currentnode_addr; /* Current node address */ + + uint32_t nextnode_addr; /* Next node address */ + +} DMA_NodeInQInfoTypeDef; +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Constants DMAEx Private Constants + * @brief DMAEx Private Constants + * @{ + */ +#define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */ + +#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */ +#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */ +#define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */ +#define DMA_CHANNEL_TYPE_HPDMA (0x0040U) /* HPDMA channel node */ + +#define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */ +#define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */ +#define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */ + +#define NODE_MAXIMUM_SIZE (0x0008U) /* Amount of registers of the node */ + +#define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */ +#define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */ + +#define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */ +#define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */ + +#define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */ +#define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */ + +#define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */ +#define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */ + +#define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ +#define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */ +#define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */ +#define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */ +#define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */ +#define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */ +#define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */ +#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007U) /* CLLR 2D addressing default offset */ +#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */ + +#define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */ +#define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */ +#define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */ +#define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */ +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMAEx Private Macros + * @brief DMAEx Private Macros + * @{ + */ +#define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \ + (((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \ + ((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \ + ((ALIGNMENT) == DMA_DATA_PACK)) + +#define IS_DMA_DATA_EXCHANGE(EXCHANGE) \ + (((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD | \ + DMA_EXCHANGE_DEST_WORD))) == 0U) + +#define IS_DMA_REPEAT_COUNT(COUNT) \ + (((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos))) + +#define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \ + (((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \ + ((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX)) + +#define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \ + (((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \ + ((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX)) + +#define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \ + (((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U) + +#define IS_DMA_LINK_STEP_MODE(MODE) \ + (((MODE) == DMA_LSM_FULL_EXECUTION) || \ + ((MODE) == DMA_LSM_1LINK_EXECUTION)) + +#define IS_DMA_TRIGGER_MODE(MODE) \ + (((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TRIGM_REPEATED_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \ + ((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER)) + +#define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \ + (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ + ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) + +#define IS_DMA_LINKEDLIST_MODE(MODE) \ + (((MODE) == DMA_LINKEDLIST_NORMAL) || \ + ((MODE) == DMA_LINKEDLIST_CIRCULAR)) + +#define IS_DMA_TRIGGER_POLARITY(POLARITY) \ + (((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \ + ((POLARITY) == DMA_TRIG_POLARITY_RISING) || \ + ((POLARITY) == DMA_TRIG_POLARITY_FALLING)) + +#define IS_DMA_TRIGGER_SELECTION(TRIGGER) \ + ((TRIGGER) <= GPDMA1_TRIGGER_TIM15_TRGO) + +#define IS_DMA_NODE_TYPE(TYPE) \ + (((TYPE) == DMA_GPDMA_LINEAR_NODE) || \ + ((TYPE) == DMA_GPDMA_2D_NODE) || \ + ((TYPE) == DMA_HPDMA_LINEAR_NODE) || \ + ((TYPE) == DMA_HPDMA_2D_NODE)) +/** + * @} + */ + + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32H7RSxx_HAL_DMA_EX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dts.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dts.h new file mode 100644 index 00000000000..da7e8134446 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_dts.h @@ -0,0 +1,546 @@ +/** + ********************************************************************************************************************** + * @file stm32h7rsxx_hal_dts.h + * @author MCD Application Team + * @brief Header file of DTS HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32H7RSxx_HAL_DTS_H +#define STM32H7RSxx_HAL_DTS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup DTS + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DTS_Exported_Types DTS Exported Types + * @{ + */ + +/** + * @brief DTS Init structure definition + */ +typedef struct +{ + uint32_t QuickMeasure; /*!< Specifies the quick measure option selection of the DTS sensor. + This parameter can be a value of @ref DTS_Quick_Measurement */ + + uint32_t RefClock; /*!< Specifies the reference clock selection of the DTS sensor. + This parameter can be a value of @ref DTS_Reference_Clock_Selection */ + + uint32_t TriggerInput; /*!< Specifies the trigger input of the DTS sensor. + This parameter can be a value of @ref DTS_TriggerConfig */ + + uint32_t SamplingTime; /*!< Specifies the sampling time configuration. + This parameter can be a value of @ref DTS_Sampling_Time */ + + uint32_t Divider; /*!< Specifies the high speed clock divider ratio. + This parameter can be a value from 0 to 127 */ + + uint32_t HighThreshold; /*!< Specifies the high threshold of the DTS sensor */ + + uint32_t LowThreshold; /*!< Specifies the low threshold of the DTS sensor */ + +} DTS_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_DTS_STATE_RESET = 0x00UL, /*!< DTS not yet initialized or disabled */ + HAL_DTS_STATE_READY = 0x01UL, /*!< DTS initialized and ready for use */ + HAL_DTS_STATE_BUSY = 0x02UL, /*!< DTS is running */ + HAL_DTS_STATE_TIMEOUT = 0x03UL, /*!< Timeout state */ + HAL_DTS_STATE_ERROR = 0x04UL /*!< Internal Process error */ + +} HAL_DTS_StateTypeDef; + +/** + * @brief DTS Handle Structure definition + */ +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U) +typedef struct __DTS_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ +{ + DTS_TypeDef *Instance; /*!< Register base address */ + DTS_InitTypeDef Init; /*!< DTS required parameters */ + HAL_LockTypeDef Lock; /*!< DTS Locking object */ + __IO HAL_DTS_StateTypeDef State; /*!< DTS peripheral state */ + +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U) + void (* MspInitCallback)(struct __DTS_HandleTypeDef *hdts); /*!< DTS Base Msp Init Callback */ + void (* MspDeInitCallback)(struct __DTS_HandleTypeDef *hdts); /*!< DTS Base Msp DeInit Callback */ + void (* EndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< End measure Callback */ + void (* LowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< low threshold Callback */ + void (* HighCallback)(struct __DTS_HandleTypeDef *hdts); /*!< high threshold Callback */ + void (* AsyncEndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous end of measure Callback */ + void (* AsyncLowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous low threshold Callback */ + void (* AsyncHighCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous high threshold Callback */ +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ +} DTS_HandleTypeDef; + +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U) +/** + * @brief DTS callback ID enumeration definition + */ +typedef enum +{ + HAL_DTS_MEAS_COMPLETE_CB_ID = 0x00U, /*!< Measure complete callback ID */ + HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID = 0x01U, /*!< Asynchronous measure complete callback ID */ + HAL_DTS_LOW_THRESHOLD_CB_ID = 0x02U, /*!< Low threshold detection callback ID */ + HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID = 0x03U, /*!< Asynchronous low threshold detection callback ID */ + HAL_DTS_HIGH_THRESHOLD_CB_ID = 0x04U, /*!< High threshold detection callback ID */ + HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID = 0x05U, /*!< Asynchronous high threshold detection callback ID */ + HAL_DTS_MSPINIT_CB_ID = 0x06U, /*!< MSP init callback ID */ + HAL_DTS_MSPDEINIT_CB_ID = 0x07U /*!< MSP de-init callback ID */ +} HAL_DTS_CallbackIDTypeDef; + +/** + * @brief DTS callback pointers definition + */ +typedef void (*pDTS_CallbackTypeDef)(DTS_HandleTypeDef *hdts); +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup DTS_Exported_Constants DTS Exported Constants + * @{ + */ + +/** @defgroup DTS_TriggerConfig DTS Trigger Configuration + * @{ + */ +/* @brief No Hardware trigger detection */ +#define DTS_TRIGGER_HW_NONE (0UL) + +/* @brief External Interrupt Mode with LPTIMER1 trigger detection */ +#define DTS_TRIGGER_LPTIMER4 DTS_CFGR1_TS1_INTRIG_SEL_0 + +/* @brief External Interrupt Mode with LPTIMER2 trigger detection */ +#define DTS_TRIGGER_LPTIMER2 DTS_CFGR1_TS1_INTRIG_SEL_1 + +/* @brief External Interrupt Mode with LPTIMER3 trigger detection */ +#define DTS_TRIGGER_LPTIMER3 (DTS_CFGR1_TS1_INTRIG_SEL_0 | DTS_CFGR1_TS1_INTRIG_SEL_1) + +/* @brief External Interrupt Mode with EXTI13 trigger detection */ +#define DTS_TRIGGER_EXTI13 DTS_CFGR1_TS1_INTRIG_SEL_2 +/** + * @} + */ + +/** @defgroup DTS_Quick_Measurement DTS Quick Measurement + * @{ + */ +#define DTS_QUICKMEAS_ENABLE DTS_CFGR1_Q_MEAS_OPT /*!< Enable the Quick Measure (Measure without calibration) */ +#define DTS_QUICKMEAS_DISABLE (0x0UL) /*!< Disable the Quick Measure (Measure with calibration) */ +/** + * @} + */ + +/** @defgroup DTS_Reference_Clock_Selection DTS Reference Clock Selection + * @{ + */ +#define DTS_REFCLKSEL_LSE DTS_CFGR1_REFCLK_SEL /*!< Low speed REF clock (LSE) */ +#define DTS_REFCLKSEL_PCLK (0UL) /*!< High speed REF clock (PCLK) */ +/** + * @} + */ + +/** @defgroup DTS_Sampling_Time DTS Sampling Time + * @{ + */ +#define DTS_SMP_TIME_1_CYCLE DTS_CFGR1_TS1_SMP_TIME_0 /*!< 1 clock cycle for the sampling time */ +#define DTS_SMP_TIME_2_CYCLE DTS_CFGR1_TS1_SMP_TIME_1 /*!< 2 clock cycle for the sampling time */ +#define DTS_SMP_TIME_3_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\ + DTS_CFGR1_TS1_SMP_TIME_1) /*!< 3 clock cycle for the sampling time */ +#define DTS_SMP_TIME_4_CYCLE (DTS_CFGR1_TS1_SMP_TIME_2) /*!< 4 clock cycle for the sampling time */ +#define DTS_SMP_TIME_5_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\ + DTS_CFGR1_TS1_SMP_TIME_2) /*!< 5 clock cycle for the sampling time */ +#define DTS_SMP_TIME_6_CYCLE (DTS_CFGR1_TS1_SMP_TIME_1 |\ + DTS_CFGR1_TS1_SMP_TIME_2) /*!< 6 clock cycle for the sampling time */ +#define DTS_SMP_TIME_7_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\ + DTS_CFGR1_TS1_SMP_TIME_1 |\ + DTS_CFGR1_TS1_SMP_TIME_2) /*!< 7 clock cycle for the sampling time */ +#define DTS_SMP_TIME_8_CYCLE (DTS_CFGR1_TS1_SMP_TIME_3) /*!< 8 clock cycle for the sampling time */ +#define DTS_SMP_TIME_9_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\ + DTS_CFGR1_TS1_SMP_TIME_3) /*!< 9 clock cycle for the sampling time */ +#define DTS_SMP_TIME_10_CYCLE (DTS_CFGR1_TS1_SMP_TIME_1 |\ + DTS_CFGR1_TS1_SMP_TIME_3) /*!< 10 clock cycle for the sampling time */ +#define DTS_SMP_TIME_11_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\ + DTS_CFGR1_TS1_SMP_TIME_1 |\ + DTS_CFGR1_TS1_SMP_TIME_3) /*!< 11 clock cycle for the sampling time */ +#define DTS_SMP_TIME_12_CYCLE (DTS_CFGR1_TS1_SMP_TIME_2 |\ + DTS_CFGR1_TS1_SMP_TIME_3) /*!< 12 clock cycle for the sampling time */ +#define DTS_SMP_TIME_13_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\ + DTS_CFGR1_TS1_SMP_TIME_2 |\ + DTS_CFGR1_TS1_SMP_TIME_3) /*!< 13 clock cycle for the sampling time */ +#define DTS_SMP_TIME_14_CYCLE (DTS_CFGR1_TS1_SMP_TIME_1 |\ + DTS_CFGR1_TS1_SMP_TIME_2 |\ + DTS_CFGR1_TS1_SMP_TIME_3) /*!< 14 clock cycle for the sampling time */ +#define DTS_SMP_TIME_15_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\ + DTS_CFGR1_TS1_SMP_TIME_1 |\ + DTS_CFGR1_TS1_SMP_TIME_2 |\ + DTS_CFGR1_TS1_SMP_TIME_3) /*!< 15 clock cycle for the sampling time */ +/** + * @} + */ + +/** @defgroup DTS_Flag_Definitions DTS Flag Definitions + * @{ + */ +#define DTS_FLAG_TS1_ITE DTS_SR_TS1_ITEF /*!< Interrupt flag for end of measure for DTS1 */ +#define DTS_FLAG_TS1_ITL DTS_SR_TS1_ITLF /*!< Interrupt flag for low threshold for DTS1 */ +#define DTS_FLAG_TS1_ITH DTS_SR_TS1_ITHF /*!< Interrupt flag for high threshold for DTS1 */ +#define DTS_FLAG_TS1_AITE DTS_SR_TS1_AITEF /*!< Asynchronous Interrupt flag for end of measure for DTS1 */ +#define DTS_FLAG_TS1_AITL DTS_SR_TS1_AITLF /*!< Asynchronous Interrupt flag for low threshold for DTS1 */ +#define DTS_FLAG_TS1_AITH DTS_SR_TS1_AITHF /*!< Asynchronous Interrupt flag for high threshold for DTS1 */ +#define DTS_FLAG_TS1_RDY DTS_SR_TS1_RDY /*!< Ready flag for DTS1 */ +/** + * @} + */ + +/** @defgroup DTS_Interrupts_Definitions DTS Interrupts Definitions + * @{ + */ +#define DTS_IT_TS1_ITE DTS_ITENR_TS1_ITEEN /*!< Enable interrupt flag for end of measure for DTS1 */ +#define DTS_IT_TS1_ITL DTS_ITENR_TS1_ITLEN /*!< Enable interrupt flag for low threshold for DTS1 */ +#define DTS_IT_TS1_ITH DTS_ITENR_TS1_ITHEN /*!< Enable interrupt flag for high threshold for DTS1 */ +#define DTS_IT_TS1_AITE DTS_ITENR_TS1_AITEEN /*!< Enable asynchronous interrupt flag for end of measure for DTS1 */ +#define DTS_IT_TS1_AITL DTS_ITENR_TS1_AITLEN /*!< Enable asynchronous interrupt flag for low threshold for DTS1 */ +#define DTS_IT_TS1_AITH DTS_ITENR_TS1_AITHEN /*!< Enable asynchronous interrupt flag for high threshold for DTS1 */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macros ---------------------------------------------------------------------------------------------------*/ +/** @defgroup DTS_Exported_Macros DTS Exported Macros + * @{ + */ + +/** @brief Reset DTS handle state + * @param __HANDLE__ DTS handle. + * @retval None + */ +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U) +#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DTS_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else /* USE_HAL_DTS_REGISTER_CALLBACKS */ +#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DTS_STATE_RESET) +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ + +/** + * @brief Enable the specified DTS sensor + * @param __HANDLE__ DTS handle. + * @retval None + */ +#define __HAL_DTS_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN) + +/** + * @brief Disable the specified DTS sensor + * @param __HANDLE__ DTS handle. + * @retval None + */ +#define __HAL_DTS_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN) + +/** + * @brief Enable the DTS EXTI line in interrupt mode + * @retval None + */ +#define __HAL_DTS_EXTI_WAKEUP_ENABLE_IT() SET_BIT(EXTI->IMR2, DTS_EXTI_LINE_DTS1) + +/** + * @brief Disable the DTS EXTI line in interrupt mode + * @retval None + */ +#define __HAL_DTS_EXTI_WAKEUP_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, DTS_EXTI_LINE_DTS1) + +/** + * @brief Enable the DTS EXTI Line in event mode + * @retval None + */ +#define __HAL_DTS_EXTI_WAKEUP_ENABLE_EVENT() SET_BIT(EXTI->EMR2, DTS_EXTI_LINE_DTS1) + +/** + * @brief Disable the DTS EXTI Line in event mode + * @retval None + */ +#define __HAL_DTS_EXTI_WAKEUP_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, DTS_EXTI_LINE_DTS1) + +/** @brief Checks whether the specified DTS flag is set or not. + * @param __HANDLE__ specifies the DTS Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg DTS_FLAG_TS1_ITE : interrupt flag for end of measure for DTS1 + * @arg DTS_FLAG_TS1_ITL : interrupt flag for low threshold for DTS1 + * @arg DTS_FLAG_TS1_ITH : interrupt flag for high threshold for DTS1 + * @arg DTS_FLAG_TS1_AITE: asynchronous interrupt flag for end of measure for DTS1 + * @arg DTS_FLAG_TS1_AITL: asynchronous interrupt flag for low threshold for DTS1 + * @arg DTS_FLAG_TS1_AITH: asynchronous interrupt flag for high threshold for DTS1 + * @arg DTS_FLAG_TS1_RDY : Ready flag for DTS1 + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_DTS_GET_FLAG(__HANDLE__, __FLAG__) \ + (((((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)))? SET : RESET) + + +/** @brief Clears the specified DTS pending flag. + * @param __HANDLE__ specifies the DTS Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg DTS_FLAG_TS1_ITE : interrupt flag for end of measure for DTS1 + * @arg DTS_FLAG_TS1_ITL : interrupt flag for low threshold for DTS1 + * @arg DTS_FLAG_TS1_ITH : interrupt flag for high threshold for DTS1 + * @arg DTS_FLAG_TS1_AITE: asynchronous interrupt flag for end of measure for DTS1 + * @arg DTS_FLAG_TS1_AITL: asynchronous interrupt flag for low threshold for DTS1 + * @arg DTS_FLAG_TS1_AITH: asynchronous interrupt flag for high threshold for DTS1 + * @retval None + */ +#define __HAL_DTS_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + ((__HANDLE__)->Instance->ICIFR = (__FLAG__)) + + +/** @brief Enable the specified DTS interrupt. + * @param __HANDLE__ specifies the DTS Handle. + * @param __INTERRUPT__ specifies the DTS interrupt source to enable. + * This parameter can be one of the following values: + * @arg DTS_IT_TS1_ITE : interrupt flag for end of measure for DTS1 + * @arg DTS_IT_TS1_ITL : interrupt flag for low of measure for DTS1 + * @arg DTS_IT_TS1_ITH : interrupt flag for high of measure for DTS1 + * @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1 + * @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1 + * @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1 + * @retval None + */ +#define __HAL_DTS_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + SET_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__) + + +/** @brief Disable the specified DTS interrupt. + * @param __HANDLE__ specifies the DTS Handle. + * @param __INTERRUPT__ specifies the DTS interrupt source to enable. + * This parameter can be one of the following values: + * @arg DTS_IT_TS1_ITE : interrupt flag for end of measure for DTS1 + * @arg DTS_IT_TS1_ITL : interrupt flag for low of measure for DTS1 + * @arg DTS_IT_TS1_ITH : interrupt flag for high of measure for DTS1 + * @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1 + * @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1 + * @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1 + * @retval None + */ +#define __HAL_DTS_DISABLE_IT(__HANDLE__,__INTERRUPT__) \ + CLEAR_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__) + + +/** @brief Check whether the specified DTS interrupt source is enabled or not. + * @param __HANDLE__ DTS handle. + * @param __INTERRUPT__ DTS interrupt source to check + * This parameter can be one of the following values: + * @arg DTS_IT_TS1_ITE : interrupt flag for end of measure for DTS1 + * @arg DTS_IT_TS1_ITL : interrupt flag for low of measure for DTS1 + * @arg DTS_IT_TS1_ITH : interrupt flag for high of measure for DTS1 + * @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1 + * @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1 + * @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1 + * @retval State of interruption (SET or RESET) + */ +#define __HAL_DTS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (( ((__HANDLE__)->Instance->ITENR & (__INTERRUPT__)) == (__INTERRUPT__))? SET : RESET) + + +/** @brief Check whether the specified DTS REFCLK is selected + * @param __HANDLE__ DTS handle. + * @param __REFCLK__ DTS reference clock to check + * This parameter can be one of the following values: + * @arg DTS_REFCLKSEL_LSE: Low speed REF clock + * @arg DTS_REFCLKSEL_PCLK: High speed REF clock + * @retval State of the REF clock tested (SET or RESET) + */ +#define __HAL_DTS_GET_REFCLK(__HANDLE__, __REFCLK__) \ + ((((__HANDLE__)->Instance->CFGR1 & (__REFCLK__)) == (__REFCLK__))? SET : RESET) + +/** @brief Get Trigger + * @param __HANDLE__ DTS handle. + * @retval One of the following trigger + * DTS_TRIGGER_HW_NONE : No HW trigger (SW trigger) + * DTS_TRIGGER_LPTIMER1: LPTIMER1 trigger + * DTS_TRIGGER_LPTIMER2: LPTIMER2 trigger + * DTS_TRIGGER_LPTIMER3: LPTIMER3 trigger + * DTS_TRIGGER_EXTI13 : EXTI13 trigger + */ +#define __HAL_DTS_GET_TRIGGER(__HANDLE__) ((__HANDLE__)->Instance->CFGR1 & (DTS_CFGR1_TS1_INTRIG_SEL)) +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup DTS_Exported_Functions + * @{ + */ + +/** @addtogroup DTS_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions */ +HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts); +HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts); +void HAL_DTS_MspInit(DTS_HandleTypeDef *hdts); +void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts); +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_DTS_RegisterCallback(DTS_HandleTypeDef *hdts, + HAL_DTS_CallbackIDTypeDef CallbackID, + pDTS_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DTS_UnRegisterCallback(DTS_HandleTypeDef *hdts, + HAL_DTS_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ +/** + * @} + */ + + +/** @addtogroup DTS_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions */ +HAL_StatusTypeDef HAL_DTS_Start(DTS_HandleTypeDef *hdts); +HAL_StatusTypeDef HAL_DTS_Stop(DTS_HandleTypeDef *hdts); +HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Temperature); +HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts); +HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts); +void HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts); + +/* Callback in Interrupt mode */ +void HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts); +void HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts); +void HAL_DTS_HighCallback(DTS_HandleTypeDef *hdts); +void HAL_DTS_AsyncEndCallback(DTS_HandleTypeDef *hdts); +void HAL_DTS_AsyncLowCallback(DTS_HandleTypeDef *hdts); +void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts); +/** + * @} + */ + +/** @addtogroup DTS_Exported_Functions_Group3 + * @{ + */ +HAL_DTS_StateTypeDef HAL_DTS_GetState(const DTS_HandleTypeDef *hdts); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup DTS_Private_Constants DTS Private Constants + * @{ + */ +/** @defgroup DTS_ExtiLine DTS EXTI Lines + * @{ + */ +#define DTS_EXTI_LINE_DTS1 (EXTI_IMR3_IM77) /*!< EXTI line 77 connected to DTS1 output */ +/** + * @} + */ +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DTS_Private_Macros DTS Private Macros + * @{ + */ + +/** @defgroup DTS_IS_DTS_Definitions DTS Private macros to check input parameters + * @{ + */ +#define IS_DTS_QUICKMEAS(__SEL__) (((__SEL__) == DTS_QUICKMEAS_DISABLE) || \ + ((__SEL__) == DTS_QUICKMEAS_ENABLE)) + +#define IS_DTS_REFCLK(__SEL__) (((__SEL__) == DTS_REFCLKSEL_LSE) || \ + ((__SEL__) == DTS_REFCLKSEL_PCLK)) +#define IS_DTS_TRIGGERINPUT(__INPUT__) (((__INPUT__) == DTS_TRIGGER_HW_NONE) || \ + ((__INPUT__) == DTS_TRIGGER_LPTIMER4) || \ + ((__INPUT__) == DTS_TRIGGER_LPTIMER2) || \ + ((__INPUT__) == DTS_TRIGGER_LPTIMER3) || \ + ((__INPUT__) == DTS_TRIGGER_EXTI13)) + +#define IS_DTS_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= 0xFFFFUL) + +#define IS_DTS_DIVIDER_RATIO_NUMBER(__NUMBER__) ((__NUMBER__) <= 127UL) + +#define IS_DTS_SAMPLINGTIME(__CYCLE__) (((__CYCLE__) == DTS_SMP_TIME_1_CYCLE) || \ + ((__CYCLE__) == DTS_SMP_TIME_2_CYCLE) || \ + ((__CYCLE__) == DTS_SMP_TIME_3_CYCLE) || \ + ((__CYCLE__) == DTS_SMP_TIME_4_CYCLE) || \ + ((__CYCLE__) == DTS_SMP_TIME_5_CYCLE) || \ + ((__CYCLE__) == DTS_SMP_TIME_6_CYCLE) || \ + ((__CYCLE__) == DTS_SMP_TIME_7_CYCLE) || \ + ((__CYCLE__) == DTS_SMP_TIME_8_CYCLE) || \ + ((__CYCLE__) == DTS_SMP_TIME_9_CYCLE) || \ + ((__CYCLE__) == DTS_SMP_TIME_10_CYCLE) || \ + ((__CYCLE__) == DTS_SMP_TIME_11_CYCLE) || \ + ((__CYCLE__) == DTS_SMP_TIME_12_CYCLE) || \ + ((__CYCLE__) == DTS_SMP_TIME_13_CYCLE) || \ + ((__CYCLE__) == DTS_SMP_TIME_14_CYCLE) || \ + ((__CYCLE__) == DTS_SMP_TIME_15_CYCLE)) + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_DTS_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_eth.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_eth.h new file mode 100644 index 00000000000..f5afd734db5 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_eth.h @@ -0,0 +1,1823 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_eth.h + * @author MCD Application Team + * @brief Header file of ETH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_ETH_H +#define STM32H7RSxx_HAL_ETH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +#if defined(ETH) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup ETH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +#ifndef ETH_TX_DESC_CNT +#define ETH_TX_DESC_CNT 4U +#endif /* ETH_TX_DESC_CNT */ + +#ifndef ETH_RX_DESC_CNT +#define ETH_RX_DESC_CNT 4U +#endif /* ETH_RX_DESC_CNT */ + +#ifndef ETH_SWRESET_TIMEOUT +#define ETH_SWRESET_TIMEOUT 500U +#endif /* ETH_SWRESET_TIMEOUT */ + +#ifndef ETH_MDIO_BUS_TIMEOUT +#define ETH_MDIO_BUS_TIMEOUT 1000U +#endif /* ETH_MDIO_BUS_TIMEOUT */ + +#ifndef ETH_MAC_US_TICK +#define ETH_MAC_US_TICK 1000000U +#endif /* ETH_MAC_US_TICK */ + +/*********************** Descriptors struct def section ************************/ +/** @defgroup ETH_Exported_Types ETH Exported Types + * @{ + */ + +/** + * @brief ETH DMA Descriptor structure definition + */ +typedef struct +{ + __IO uint32_t DESC0; + __IO uint32_t DESC1; + __IO uint32_t DESC2; + __IO uint32_t DESC3; + uint32_t BackupAddr0; /* used to store rx buffer 1 address */ + uint32_t BackupAddr1; /* used to store rx buffer 2 address */ +} ETH_DMADescTypeDef; +/** + * + */ + +/** + * @brief ETH Buffers List structure definition + */ +typedef struct __ETH_BufferTypeDef +{ + uint8_t *buffer; /*gState = HAL_ETH_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ + } while(0) +#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @brief Enables the specified ETHERNET DMA interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be + * enabled @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET DMA interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be + * disabled. @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__)) + +/** + * @brief Gets the ETHERNET DMA IT source enabled or disabled. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts + * @retval The ETH DMA IT Source enabled or disabled + */ +#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Gets the ETHERNET DMA IT pending bit. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts + * @retval The state of ETH DMA IT (SET or RESET) + */ +#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clears the ETHERNET DMA IT pending bit. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__)) + +/** + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * @param __HANDLE__: ETH Handle + * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags + * @retval The state of ETH DMA FLAG (SET or RESET). + */ +#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__)) + +/** + * @brief Clears the specified ETHERNET DMA flag. + * @param __HANDLE__: ETH Handle + * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags + * @retval The state of ETH DMA FLAG (SET or RESET). + */ +#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__)) + +/** + * @brief Enables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * enabled @ref ETH_MAC_Interrupts + * @retval None + */ + +#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * enabled @ref ETH_MAC_Interrupts + * @retval None + */ +#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * @param __HANDLE__: ETH Handle + * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts + * @retval The state of ETH MAC IT (SET or RESET). + */ +#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &\ + ( __INTERRUPT__)) == ( __INTERRUPT__)) + +/*!< External interrupt line 46 Connected to the ETH wakeup EXTI Line */ +#define ETH_WAKEUP_EXTI_LINE 0x00004000U /* !< 46 - 32 = 14 */ + +/** + * @brief Enable the ETH WAKEUP Exti Line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI->IMR2 |= (__EXTI_LINE__)) + +/** + * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval EXTI ETH WAKEUP Line Status. + */ +#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR2 & (__EXTI_LINE__)) + +/** + * @brief Clear the ETH WAKEUP Exti flag. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR2 = (__EXTI_LINE__)) + +/** + * @brief enable rising edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR2 &= ~(__EXTI_LINE__)); \ + (EXTI->RTSR2 |= (__EXTI_LINE__)) + +/** + * @brief enable falling edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 &= ~(__EXTI_LINE__));\ + (EXTI->FTSR2 |= (__EXTI_LINE__)) + +/** + * @brief enable falling edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 |= (__EXTI_LINE__));\ + (EXTI->FTSR2 |= (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER2 |= (__EXTI_LINE__)) +#define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->MACTSCR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) +#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->MACTSCR |= (__FLAG__)) + +/** + * @} + */ + +/* Include ETH HAL Extension module */ +#include "stm32h7rsxx_hal_eth_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup ETH_Exported_Functions + * @{ + */ + +/** @addtogroup ETH_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de initialization functions **********************************/ +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, + pETH_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff); +HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, + pETH_rxAllocateCallbackTypeDef rxAllocateCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode); +HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth); + +#ifdef HAL_ETH_USE_PTP +HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); +HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); +HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); +HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); +HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, + ETH_TimeTypeDef *timeoffset); +HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth); +#endif /* HAL_ETH_USE_PTP */ + +HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout); +HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig); + +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t RegValue); +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t *pRegValue); + +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); +void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth); +void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_RxAllocateCallback(uint8_t **buff); +void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length); +void HAL_ETH_TxFreeCallback(uint32_t *buff); +void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp); +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions **********************************************/ +/* MAC & DMA Configuration APIs **********************************************/ +HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth); + +/* MAC VLAN Processing APIs ************************************************/ +void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, + uint32_t VLANIdentifier); + +/* MAC L2 Packet Filtering APIs **********************************************/ +HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable); +HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr, + const uint8_t *pMACAddr); + +/* MAC Power Down APIs *****************************************************/ +void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, + const ETH_PowerDownConfigTypeDef *pPowerDownConfig); +void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count); + +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ETH */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_ETH_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_eth_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_eth_ex.h new file mode 100644 index 00000000000..e640e3711fa --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_eth_ex.h @@ -0,0 +1,366 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_eth_ex.h + * @author MCD Application Team + * @brief Header file of ETH HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_ETH_EX_H +#define STM32H7RSxx_HAL_ETH_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(ETH) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup ETHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ETHEx_Exported_Types ETHEx Exported Types + * @{ + */ + +/** + * @brief ETH RX VLAN structure definition + */ +typedef struct +{ + FunctionalState InnerVLANTagInStatus; /*!< Enables or disables Inner VLAN Tag in Rx Status */ + + uint32_t StripInnerVLANTag; /*!< Sets the Inner VLAN Tag Stripping on Receive + This parameter can be a value of + @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */ + + FunctionalState InnerVLANTag; /*!< Enables or disables Inner VLAN Tag */ + + FunctionalState DoubleVLANProcessing; /*!< Enable or Disable double VLAN processing */ + + FunctionalState VLANTagHashTableMatch; /*!< Enable or Disable VLAN Tag Hash Table Match */ + + FunctionalState VLANTagInStatus; /*!< Enable or Disable VLAN Tag in Rx status */ + + uint32_t StripVLANTag; /*!< Set the VLAN Tag Stripping on Receive + This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */ + + uint32_t VLANTypeCheck; /*!< Enable or Disable VLAN Type Check + This parameter can be a value of @ref ETHEx_VLAN_Type_Check */ + + FunctionalState VLANTagInverceMatch; /*!< Enable or disable VLAN Tag Inverse Match */ +} ETH_RxVLANConfigTypeDef; +/** + * + */ + +/** + * @brief ETH TX VLAN structure definition + */ +typedef struct +{ + FunctionalState SourceTxDesc; /*!< Enable or Disable VLAN tag source from DMA tx descriptors */ + + FunctionalState SVLANType; /*!< Enable or Disable insertion of SVLAN type */ + + uint32_t VLANTagControl; /*!< Sets the VLAN tag control in tx packets + This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */ +} ETH_TxVLANConfigTypeDef; +/** + * + */ + +/** + * @brief ETH L3 filter structure definition + */ +typedef struct +{ + uint32_t Protocol; /*!< Sets the L3 filter protocol to IPv4 or IPv6 + This parameter can be a value of @ref ETHEx_L3_Protocol */ + + uint32_t SrcAddrFilterMatch; /*!< Sets the L3 filter source address match + This parameter can be a value of @ref ETHEx_L3_Source_Match */ + + uint32_t DestAddrFilterMatch; /*!< Sets the L3 filter destination address match + This parameter can be a value of @ref ETHEx_L3_Destination_Match */ + + uint32_t SrcAddrHigherBitsMatch; /*!< Sets the L3 filter source address higher bits match + This parameter can be a value from 0 to 31 */ + + uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match + This parameter can be a value from 0 to 31 */ + + uint32_t Ip4SrcAddr; /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used + This parameter can be a value from 0x0 to 0xFFFFFFFF */ + + uint32_t Ip4DestAddr; /*!< Sets the L3 filter IPv4 destination address if IPv4 protocol is used + This parameter can be a value from 0 to 0xFFFFFFFF */ + + uint32_t Ip6Addr[4]; /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used + This parameter must be a table of 4 words (4* 32 bits) */ +} ETH_L3FilterConfigTypeDef; +/** + * + */ + +/** + * @brief ETH L4 filter structure definition + */ +typedef struct +{ + uint32_t Protocol; /*!< Sets the L4 filter protocol to TCP or UDP + This parameter can be a value of @ref ETHEx_L4_Protocol */ + + uint32_t SrcPortFilterMatch; /*!< Sets the L4 filter source port match + This parameter can be a value of @ref ETHEx_L4_Source_Match */ + + uint32_t DestPortFilterMatch; /*!< Sets the L4 filter destination port match + This parameter can be a value of @ref ETHEx_L4_Destination_Match */ + + uint32_t SourcePort; /*!< Sets the L4 filter source port + This parameter must be a value from 0x0 to 0xFFFF */ + + uint32_t DestinationPort; /*!< Sets the L4 filter destination port + This parameter must be a value from 0x0 to 0xFFFF */ +} ETH_L4FilterConfigTypeDef; +/** + * + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants + * @{ + */ + +/** @defgroup ETHEx_LPI_Event ETHEx LPI Event + * @{ + */ +#define ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN +#define ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX +#define ETH_RX_LPI_ENTRY ETH_MACLCSR_RLPIEN +#define ETH_RX_LPI_EXIT ETH_MACLCSR_RLPIEX +/** + * @} + */ + +/** @defgroup ETHEx_L3_Filter ETHEx L3 Filter + * @{ + */ +#define ETH_L3_FILTER_0 0x00000000U +#define ETH_L3_FILTER_1 0x0000000CU +/** + * @} + */ + +/** @defgroup ETHEx_L4_Filter ETHEx L4 Filter + * @{ + */ +#define ETH_L4_FILTER_0 0x00000000U +#define ETH_L4_FILTER_1 0x0000000CU +/** + * @} + */ + +/** @defgroup ETHEx_L3_Protocol ETHEx L3 Protocol + * @{ + */ +#define ETH_L3_IPV6_MATCH ETH_MACL3L4CR_L3PEN +#define ETH_L3_IPV4_MATCH 0x00000000U +/** + * @} + */ + +/** @defgroup ETHEx_L3_Source_Match ETHEx L3 Source Match + * @{ + */ +#define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3SAM +#define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM) +#define ETH_L3_SRC_ADDR_MATCH_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match + * @{ + */ +#define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3DAM +#define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM) +#define ETH_L3_DEST_ADDR_MATCH_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol + * @{ + */ +#define ETH_L4_UDP_MATCH ETH_MACL3L4CR_L4PEN +#define ETH_L4_TCP_MATCH 0x00000000U +/** + * @} + */ + +/** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match + * @{ + */ +#define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4SPM +#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM) +#define ETH_L4_SRC_PORT_MATCH_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match + * @{ + */ +#define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4DPM +#define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM) +#define ETH_L4_DEST_PORT_MATCH_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping + * @{ + */ +#define ETH_INNERVLANTAGRXSTRIPPING_NONE ETH_MACVTR_EIVLS_DONOTSTRIP +#define ETH_INNERVLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EIVLS_STRIPIFPASS +#define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS +#define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EIVLS_ALWAYSSTRIP +/** + * @} + */ + +/** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping + * @{ + */ +#define ETH_VLANTAGRXSTRIPPING_NONE ETH_MACVTR_EVLS_DONOTSTRIP +#define ETH_VLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EVLS_STRIPIFPASS +#define ETH_VLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS +#define ETH_VLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EVLS_ALWAYSSTRIP +/** + * @} + */ + +/** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check + * @{ + */ +#define ETH_VLANTYPECHECK_DISABLE ETH_MACVTR_DOVLTC +#define ETH_VLANTYPECHECK_SVLAN (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL) +#define ETH_VLANTYPECHECK_CVLAN 0x00000000U +/** + * @} + */ + +/** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control + * @{ + */ +#define ETH_VLANTAGCONTROL_NONE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG) +#define ETH_VLANTAGCONTROL_DELETE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE) +#define ETH_VLANTAGCONTROL_INSERT (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT) +#define ETH_VLANTAGCONTROL_REPLACE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE) +/** + * @} + */ + +/** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag + * @{ + */ +#define ETH_INNER_TX_VLANTAG 0x00000001U +#define ETH_OUTER_TX_VLANTAG 0x00000000U +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ETHEx_Exported_Functions + * @{ + */ + +/** @addtogroup ETHEx_Exported_Functions_Group1 + * @{ + */ +/* MAC ARP Offloading APIs ***************************************************/ +void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth); +void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth); +void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress); + +/* MAC L3 L4 Filtering APIs ***************************************************/ +void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth); +void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L3FilterConfigTypeDef *pL3FilterConfig); +HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L4FilterConfigTypeDef *pL4FilterConfig); +HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + const ETH_L3FilterConfigTypeDef *pL3FilterConfig); +HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + const ETH_L4FilterConfigTypeDef *pL4FilterConfig); + +/* MAC VLAN Processing APIs ************************************************/ +void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth); +void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig); +HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig); +void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable); +HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag, + ETH_TxVLANConfigTypeDef *pVlanConfig); +HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag, + const ETH_TxVLANConfigTypeDef *pVlanConfig); +void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier); + +/* Energy Efficient Ethernet APIs *********************************************/ +void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, + FunctionalState TxClockStop); +void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth); +uint32_t HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ETH */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_ETH_EX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_exti.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_exti.h new file mode 100644 index 00000000000..8c5960513e6 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_exti.h @@ -0,0 +1,347 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_EXTI_H +#define STM32H7RSxx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U, +} EXTI_CallbackIDTypeDef; + + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu) +#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u) +#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u) +#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x03u) +#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x04u) +#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x05u) +#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x06u) +#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u) +#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u) +#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x09u) +#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0Au) +#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0Bu) +#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0Cu) +#define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0Du) +#define EXTI_LINE_46 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x0Eu) +#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0Fu) +#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x10u) +#define EXTI_LINE_49 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x11u) +#define EXTI_LINE_50 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x12u) +#define EXTI_LINE_51 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x13u) +#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x14u) +#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x15u) +#define EXTI_LINE_54 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x16u) +#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x17u) +#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x18u) +#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x19u) +#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x1Au) +#define EXTI_LINE_59 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x1Bu) +#define EXTI_LINE_77 (EXTI_DIRECT | EXTI_REG3 | EXTI_EVENT | 0x0Du) +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#define EXTI_GPIOD 0x00000003u +#define EXTI_GPIOE 0x00000004u +#define EXTI_GPIOF 0x00000005u +#define EXTI_GPIOG 0x00000006u +#define EXTI_GPIOH 0x00000007u +#define EXTI_GPIOM 0x0000000Cu +#define EXTI_GPION 0x0000000Du +#define EXTI_GPIOO 0x0000000Eu +#define EXTI_GPIOP 0x0000000Fu +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI Event presence definition + */ +#define EXTI_EVENT_PRESENCE_SHIFT 28u +#define EXTI_EVENT (0x01uL << EXTI_EVENT_PRESENCE_SHIFT) +#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT) + +/** + * @brief EXTI Register and bit usage + */ +#define EXTI_REG_SHIFT 16u +#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT) +#define EXTI_REG3 (0x02uL << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3) +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#define EXTI_LINE_NB 78u + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + ((((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))) || \ + (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x0002000DUL))) + +#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) + +#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOM) || \ + ((__PORT__) == EXTI_GPION) || \ + ((__PORT__) == EXTI_GPIOO) || \ + ((__PORT__) == EXTI_GPIOP)) + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_EXTI_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_fdcan.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_fdcan.h new file mode 100644 index 00000000000..757a01f8ab7 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_fdcan.h @@ -0,0 +1,1442 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_fdcan.h + * @author MCD Application Team + * @brief Header file of FDCAN HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_FDCAN_H +#define STM32H7RSxx_HAL_FDCAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +#if defined(FDCAN1) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup FDCAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Types FDCAN Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */ + HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */ + HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */ + HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */ +} HAL_FDCAN_StateTypeDef; + +/** + * @brief FDCAN Init structure definition + */ +typedef struct +{ + uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider. + The clock is common to all FDCAN instances. + This parameter is applied only at initialisation of + first FDCAN instance. + This parameter can be a value of @ref FDCAN_clock_divider. */ + + uint32_t FrameFormat; /*!< Specifies the FDCAN frame format. + This parameter can be a value of @ref FDCAN_frame_format */ + + uint32_t Mode; /*!< Specifies the FDCAN mode. + This parameter can be a value of @ref FDCAN_operating_mode */ + + FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is + divided for generating the nominal bit time quanta. + This parameter must be a number between 1 and 512 */ + + uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN + hardware is allowed to lengthen or shorten a bit to perform + resynchronization. + This parameter must be a number between 1 and 128 */ + + uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter must be a number between 2 and 256 */ + + uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter must be a number between 2 and 128 */ + + uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is + divided for generating the data bit time quanta. + This parameter must be a number between 1 and 32 */ + + uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN + hardware is allowed to lengthen or shorten a data bit to + perform resynchronization. + This parameter must be a number between 1 and 16 */ + + uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1. + This parameter must be a number between 1 and 32 */ + + uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2. + This parameter must be a number between 1 and 16 */ + + uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters. + This parameter must be a number between 0 and 28 */ + + uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters. + This parameter must be a number between 0 and 8 */ + + uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection. + This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */ + +} FDCAN_InitTypeDef; + +/** + * @brief FDCAN filter structure definition + */ +typedef struct +{ + uint32_t IdType; /*!< Specifies the identifier type. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t FilterIndex; /*!< Specifies the filter which will be initialized. + This parameter must be a number between: + - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID + - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */ + + uint32_t FilterType; /*!< Specifies the filter type. + This parameter can be a value of @ref FDCAN_filter_type. + The value FDCAN_FILTER_RANGE_NO_EIDM is permitted + only when IdType is FDCAN_EXTENDED_ID. */ + + uint32_t FilterConfig; /*!< Specifies the filter configuration. + This parameter can be a value of @ref FDCAN_filter_config */ + + uint32_t FilterID1; /*!< Specifies the filter identification 1. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t FilterID2; /*!< Specifies the filter identification 2. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + +} FDCAN_FilterTypeDef; + +/** + * @brief FDCAN Tx header structure definition + */ +typedef struct +{ + uint32_t Identifier; /*!< Specifies the identifier. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t IdType; /*!< Specifies the identifier type for the message that will be + transmitted. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted. + This parameter can be a value of @ref FDCAN_frame_type */ + + uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted. + This parameter can be a value of @ref FDCAN_data_length_code */ + + uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. + This parameter can be a value of @ref FDCAN_error_state_indicator */ + + uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without + bit rate switching. + This parameter can be a value of @ref FDCAN_bit_rate_switching */ + + uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or + FD format. + This parameter can be a value of @ref FDCAN_format */ + + uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control. + This parameter can be a value of @ref FDCAN_EFC */ + + uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO + element for identification of Tx message status. + This parameter must be a number between 0 and 0xFF */ + +} FDCAN_TxHeaderTypeDef; + +/** + * @brief FDCAN Rx header structure definition + */ +typedef struct +{ + uint32_t Identifier; /*!< Specifies the identifier. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t IdType; /*!< Specifies the identifier type of the received message. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t RxFrameType; /*!< Specifies the the received message frame type. + This parameter can be a value of @ref FDCAN_frame_type */ + + uint32_t DataLength; /*!< Specifies the received frame length. + This parameter can be a value of @ref FDCAN_data_length_code */ + + uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. + This parameter can be a value of @ref FDCAN_error_state_indicator */ + + uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit + rate switching. + This parameter can be a value of @ref FDCAN_bit_rate_switching */ + + uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD + format. + This parameter can be a value of @ref FDCAN_format */ + + uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame + reception. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element. + This parameter must be a number between: + - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID + - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID + When the frame is a Non-Filter matching frame, this parameter + is unused. */ + + uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter. + Acceptance of non-matching frames may be enabled via + HAL_FDCAN_ConfigGlobalFilter(). + This parameter takes 0 if the frame matched an Rx filter or + 1 if it did not match any Rx filter */ + +} FDCAN_RxHeaderTypeDef; + +/** + * @brief FDCAN Tx event FIFO structure definition + */ +typedef struct +{ + uint32_t Identifier; /*!< Specifies the identifier. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t IdType; /*!< Specifies the identifier type for the transmitted message. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message. + This parameter can be a value of @ref FDCAN_frame_type */ + + uint32_t DataLength; /*!< Specifies the length of the transmitted frame. + This parameter can be a value of @ref FDCAN_data_length_code */ + + uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. + This parameter can be a value of @ref FDCAN_error_state_indicator */ + + uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit + rate switching. + This parameter can be a value of @ref FDCAN_bit_rate_switching */ + + uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD + format. + This parameter can be a value of @ref FDCAN_format */ + + uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame + transmission. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element + for identification of Tx message status. + This parameter must be a number between 0 and 0xFF */ + + uint32_t EventType; /*!< Specifies the event type. + This parameter can be a value of @ref FDCAN_event_type */ + +} FDCAN_TxEventFifoTypeDef; + +/** + * @brief FDCAN High Priority Message Status structure definition + */ +typedef struct +{ + uint32_t FilterList; /*!< Specifies the filter list of the matching filter element. + This parameter can be: + - 0 : Standard Filter List + - 1 : Extended Filter List */ + + uint32_t FilterIndex; /*!< Specifies the index of matching filter element. + This parameter can be a number between: + - 0 and (SRAMCAN_FLS_NBR-1), if FilterList is 0 (Standard) + - 0 and (SRAMCAN_FLE_NBR-1), if FilterList is 1 (Extended) */ + + uint32_t MessageStorage; /*!< Specifies the HP Message Storage. + This parameter can be a value of @ref FDCAN_hp_msg_storage */ + + uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the + message was stored. + This parameter is valid only when MessageStorage is: + FDCAN_HP_STORAGE_RXFIFO0 + or + FDCAN_HP_STORAGE_RXFIFO1 */ + +} FDCAN_HpMsgStatusTypeDef; + +/** + * @brief FDCAN Protocol Status structure definition + */ +typedef struct +{ + uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus. + This parameter can be a value of @ref FDCAN_protocol_error_code */ + + uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase + of a CAN FD format frame with its BRS flag set. + This parameter can be a value of @ref FDCAN_protocol_error_code */ + + uint32_t Activity; /*!< Specifies the FDCAN module communication state. + This parameter can be a value of @ref FDCAN_communication_state */ + + uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status. + This parameter can be: + - 0 : The FDCAN is in Error_Active state + - 1 : The FDCAN is in Error_Passive state */ + + uint32_t Warning; /*!< Specifies the FDCAN module warning status. + This parameter can be: + - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the + Error_Warning limit of 96 + - 1 : at least one of error counters has reached the Error_Warning + limit of 96 */ + + uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status. + This parameter can be: + - 0 : The FDCAN is not in Bus_Off state + - 1 : The FDCAN is in Bus_Off state */ + + uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message. + This parameter can be: + - 0 : Last received CAN FD message did not have its ESI flag set + - 1 : Last received CAN FD message had its ESI flag set */ + + uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message. + This parameter can be: + - 0 : Last received CAN FD message did not have its BRS flag set + - 1 : Last received CAN FD message had its BRS flag set */ + + uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received + since last protocol status. + This parameter can be: + - 0 : No CAN FD message received + - 1 : CAN FD message received */ + + uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status. + This parameter can be: + - 0 : No protocol exception event occurred since last read access + - 1 : Protocol exception event occurred */ + + uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value. + This parameter can be a number between 0 and 127 */ + +} FDCAN_ProtocolStatusTypeDef; + +/** + * @brief FDCAN Error Counters structure definition + */ +typedef struct +{ + uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. + This parameter can be a number between 0 and 255 */ + + uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. + This parameter can be a number between 0 and 127 */ + + uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status. + This parameter can be: + - 0 : The Receive Error Counter (RxErrorCnt) is below the error + passive level of 128 + - 1 : The Receive Error Counter (RxErrorCnt) has reached the error + passive level of 128 */ + + uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. + This parameter can be a number between 0 and 255. + This counter is incremented each time when a FDCAN protocol error causes + the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255; + the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag + FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ + +} FDCAN_ErrorCountersTypeDef; + +/** + * @brief FDCAN Message RAM blocks + */ +typedef struct +{ + uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address. + This parameter must be a 32-bit word address */ + + uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address. + This parameter must be a 32-bit word address */ + + uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address. + This parameter must be a 32-bit word address */ + + uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address. + This parameter must be a 32-bit word address */ + + uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address. + This parameter must be a 32-bit word address */ + + uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address. + This parameter must be a 32-bit word address */ + +} FDCAN_MsgRamAddressTypeDef; + +/** + * @brief FDCAN handle structure definition + */ +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +typedef struct __FDCAN_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ +{ + FDCAN_GlobalTypeDef *Instance; /*!< Register base address */ + + FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */ + + FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */ + + uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index + of latest Tx FIFO/Queue request */ + + __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */ + + HAL_LockTypeDef Lock; /*!< FDCAN locking object */ + + __IO uint32_t ErrorCode; /*!< FDCAN Error code */ + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */ + void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */ + void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */ + void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Tx Fifo Empty callback */ + void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */ + void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */ + void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN High priority message callback */ + void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timestamp wraparound callback */ + void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timeout occurred callback */ + void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */ + void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */ + + void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */ + void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */ + +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +} FDCAN_HandleTypeDef; + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +/** + * @brief HAL FDCAN common Callback ID enumeration definition + */ +typedef enum +{ + HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */ + HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x01U, /*!< FDCAN High priority message callback ID */ + HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x02U, /*!< FDCAN Timestamp wraparound callback ID */ + HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x03U, /*!< FDCAN Timeout occurred callback ID */ + HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x04U, /*!< FDCAN Error callback ID */ + + HAL_FDCAN_MSPINIT_CB_ID = 0x05U, /*!< FDCAN MspInit callback ID */ + HAL_FDCAN_MSPDEINIT_CB_ID = 0x06U, /*!< FDCAN MspDeInit callback ID */ + +} HAL_FDCAN_CallbackIDTypeDef; + +/** + * @brief HAL FDCAN Callback pointer definition + */ +typedef void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan); /*!< pointer to a common FDCAN callback function */ +typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback function */ +typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */ +typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */ +typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */ +typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback function */ +typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */ + +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants + * @{ + */ + +/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code + * @{ + */ +#define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ +#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */ +#define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */ +#define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */ +#define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */ +#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ +#define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ +#define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ +#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ +#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ +#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ +#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ +#define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */ +#define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */ + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup FDCAN_frame_format FDCAN Frame Format + * @{ + */ +#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */ +#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */ +#define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */ +/** + * @} + */ + +/** @defgroup FDCAN_operating_mode FDCAN Operating Mode + * @{ + */ +#define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ +#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */ +#define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */ +#define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */ +#define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */ +/** + * @} + */ + +/** @defgroup FDCAN_clock_divider FDCAN Clock Divider + * @{ + */ +#define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */ +#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2 */ +#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4 */ +#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6 */ +#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8 */ +#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */ +#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */ +#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */ +#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */ +#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */ +#define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */ +#define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */ +#define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */ +#define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */ +#define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */ +#define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */ +/** + * @} + */ + +/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode + * @{ + */ +#define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */ +#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */ +/** + * @} + */ + +/** @defgroup FDCAN_id_type FDCAN ID Type + * @{ + */ +#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */ +#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */ +/** + * @} + */ + +/** @defgroup FDCAN_frame_type FDCAN Frame Type + * @{ + */ +#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */ +#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup FDCAN_data_length_code FDCAN Data Length Code + * @{ + */ +#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */ +#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U) /*!< 1 bytes data field */ +#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U) /*!< 2 bytes data field */ +#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U) /*!< 3 bytes data field */ +#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U) /*!< 4 bytes data field */ +#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U) /*!< 5 bytes data field */ +#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U) /*!< 6 bytes data field */ +#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U) /*!< 7 bytes data field */ +#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U) /*!< 8 bytes data field */ +#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */ +#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */ +#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */ +#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */ +#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */ +#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */ +#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */ +/** + * @} + */ + +/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator + * @{ + */ +#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */ +#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */ +/** + * @} + */ + +/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching + * @{ + */ +#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */ +#define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */ +/** + * @} + */ + +/** @defgroup FDCAN_format FDCAN format + * @{ + */ +#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */ +#define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */ +/** + * @} + */ + +/** @defgroup FDCAN_EFC FDCAN Event FIFO control + * @{ + */ +#define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */ +#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */ +/** + * @} + */ + +/** @defgroup FDCAN_filter_type FDCAN Filter Type + * @{ + */ +#define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */ +#define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */ +#define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */ +#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */ +/** + * @} + */ + +/** @defgroup FDCAN_filter_config FDCAN Filter Configuration + * @{ + */ +#define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */ +#define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */ +#define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */ +#define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */ +#define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */ +#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */ +#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */ +/** + * @} + */ + +/** @defgroup FDCAN_Tx_location FDCAN Tx Location + * @{ + */ +#define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */ +#define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */ +#define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_location FDCAN Rx Location + * @{ + */ +#define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */ +#define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_event_type FDCAN Event Type + * @{ + */ +#define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */ +#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */ +/** + * @} + */ + +/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage + * @{ + */ +#define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */ +#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */ +#define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */ +#define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code + * @{ + */ +#define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */ +#define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */ +#define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */ +#define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */ +#define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */ +#define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */ +#define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */ +#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */ +/** + * @} + */ + +/** @defgroup FDCAN_communication_state FDCAN communication state + * @{ + */ +#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */ +#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */ +#define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */ +#define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode + * @{ + */ +#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */ +#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */ +/** + * @} + */ + +/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames + * @{ + */ +#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */ +#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */ +#define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */ +/** + * @} + */ + +/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames + * @{ + */ +#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */ +#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */ +/** + * @} + */ + +/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line + * @{ + */ +#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */ +#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_Timestamp FDCAN timestamp + * @{ + */ +#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */ +#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */ +/** + * @} + */ + +/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler + * @{ + */ +#define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */ +#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2 */ +#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3 */ +#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4 */ +#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5 */ +#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6 */ +#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7 */ +#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8 */ +#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9 */ +#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */ +#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */ +#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */ +#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */ +#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */ +#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */ +#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */ +/** + * @} + */ + +/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation + * @{ + */ +#define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */ +#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */ +#define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */ +#define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */ +/** + * @} + */ + +/** @defgroup Interrupt_Masks Interrupt masks + * @{ + */ +#define FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU) /*!< FDCAN interrupts mask */ +#define FDCAN_ILS_MASK ((uint32_t)0x0000007FU) /*!< FDCAN interrupts group mask */ +/** + * @} + */ + +/** @defgroup FDCAN_flags FDCAN Flags + * @{ + */ +#define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */ +#define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */ +#define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */ +#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */ +#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */ +#define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */ +#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */ +#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */ +#define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */ +#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */ +#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */ +#define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */ +#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */ +#define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */ +#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */ +#define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */ +#define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */ +#define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */ +#define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */ +#define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */ +#define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */ +#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */ +#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */ +#define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */ +/** + * @} + */ + +/** @defgroup FDCAN_Interrupts FDCAN Interrupts + * @{ + */ + +/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts + * @{ + */ +#define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */ +#define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */ +#define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts + * @{ + */ +#define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */ +/** + * @} + */ + +/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts + * @{ + */ +#define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */ +#define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */ +/** + * @} + */ + +/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts + * @{ + */ +#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */ +#define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */ +#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts + * @{ + */ +#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */ +#define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */ +#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts + * @{ + */ +#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */ +#define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */ +#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts + * @{ + */ +#define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */ +#define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */ +#define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */ +#define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */ +#define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */ +#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */ +/** + * @} + */ + +/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts + * @{ + */ +#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */ +#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */ +#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */ +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FDCAN_Interrupts_List FDCAN Interrupts List + * @{ + */ +#define FDCAN_IT_LIST_RX_FIFO0 (FDCAN_IT_RX_FIFO0_MESSAGE_LOST | \ + FDCAN_IT_RX_FIFO0_FULL | \ + FDCAN_IT_RX_FIFO0_NEW_MESSAGE) /*!< RX FIFO 0 Interrupts List */ +#define FDCAN_IT_LIST_RX_FIFO1 (FDCAN_IT_RX_FIFO1_MESSAGE_LOST | \ + FDCAN_IT_RX_FIFO1_FULL | \ + FDCAN_IT_RX_FIFO1_NEW_MESSAGE) /*!< RX FIFO 1 Interrupts List */ +#define FDCAN_IT_LIST_SMSG (FDCAN_IT_TX_ABORT_COMPLETE | \ + FDCAN_IT_TX_COMPLETE | \ + FDCAN_IT_RX_HIGH_PRIORITY_MSG) /*!< Status Message Interrupts List */ +#define FDCAN_IT_LIST_TX_FIFO_ERROR (FDCAN_IT_TX_EVT_FIFO_ELT_LOST | \ + FDCAN_IT_TX_EVT_FIFO_FULL | \ + FDCAN_IT_TX_EVT_FIFO_NEW_DATA | \ + FDCAN_IT_TX_FIFO_EMPTY) /*!< TX FIFO Error Interrupts List */ +#define FDCAN_IT_LIST_MISC (FDCAN_IT_TIMEOUT_OCCURRED | \ + FDCAN_IT_RAM_ACCESS_FAILURE | \ + FDCAN_IT_TIMESTAMP_WRAPAROUND) /*!< Misc. Interrupts List */ +#define FDCAN_IT_LIST_BIT_LINE_ERROR (FDCAN_IT_ERROR_PASSIVE | \ + FDCAN_IT_ERROR_LOGGING_OVERFLOW) /*!< Bit and Line Error Interrupts List */ +#define FDCAN_IT_LIST_PROTOCOL_ERROR (FDCAN_IT_RESERVED_ADDRESS_ACCESS | \ + FDCAN_IT_DATA_PROTOCOL_ERROR | \ + FDCAN_IT_ARB_PROTOCOL_ERROR | \ + FDCAN_IT_RAM_WATCHDOG | \ + FDCAN_IT_BUS_OFF | \ + FDCAN_IT_ERROR_WARNING) /*!< Protocol Error Interrupts List */ +/** + * @} + */ + +/** @defgroup FDCAN_Interrupts_Group FDCAN Interrupts Group + * @{ + */ +#define FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RXFIFO0 /*!< RX FIFO 0 Interrupts Group: + RF0LL: Rx FIFO 0 Message Lost + RF0FL: Rx FIFO 0 is Full + RF0NL: Rx FIFO 0 Has New Message */ +#define FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RXFIFO1 /*!< RX FIFO 1 Interrupts Group: + RF1LL: Rx FIFO 1 Message Lost + RF1FL: Rx FIFO 1 is Full + RF1NL: Rx FIFO 1 Has New Message */ +#define FDCAN_IT_GROUP_SMSG FDCAN_ILS_SMSG /*!< Status Message Interrupts Group: + TCFL: Transmission Cancellation Finished + TCL: Transmission Completed + HPML: High Priority Message */ +#define FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFERR /*!< TX FIFO Error Interrupts Group: + TEFLL: Tx Event FIFO Element Lost + TEFFL: Tx Event FIFO Full + TEFNL: Tx Event FIFO New Entry + TFEL: Tx FIFO Empty Interrupt Line */ +#define FDCAN_IT_GROUP_MISC FDCAN_ILS_MISC /*!< Misc. Interrupts Group: + TOOL: Timeout Occurred + MRAFL: Message RAM Access Failure + TSWL: Timestamp Wraparound */ +#define FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_BERR /*!< Bit and Line Error Interrupts Group: + EPL: Error Passive + ELOL: Error Logging Overflow */ +#define FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_PERR /*!< Protocol Error Group: + ARAL: Access to Reserved Address Line + PEDL: Protocol Error in Data Phase Line + PEAL: Protocol Error in Arbitration Phase Line + WDIL: Watchdog Interrupt Line + BOL: Bus_Off Status + EWL: Warning Status */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros + * @{ + */ + +/** @brief Reset FDCAN handle state. + * @param __HANDLE__ FDCAN handle. + * @retval None + */ +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET) +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** + * @brief Enable the specified FDCAN interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN interrupt. + * This parameter can be any combination of @arg FDCAN_Interrupts + * @retval None + */ +#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + (__HANDLE__)->Instance->IE |= (__INTERRUPT__) + +/** + * @brief Disable the specified FDCAN interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN interrupt. + * This parameter can be any combination of @arg FDCAN_Interrupts + * @retval None + */ +#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__) + +/** + * @brief Check whether the specified FDCAN interrupt is set or not. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN interrupt. + * This parameter can be one of @arg FDCAN_Interrupts + * @retval ITStatus + */ +#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) + +/** + * @brief Clear the specified FDCAN interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ specifies the interrupts to clear. + * This parameter can be any combination of @arg FDCAN_Interrupts + * @retval None + */ +#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \ + ((__HANDLE__)->Instance->IR) = (__INTERRUPT__) + +/** + * @brief Check whether the specified FDCAN flag is set or not. + * @param __HANDLE__ FDCAN handle. + * @param __FLAG__ FDCAN flag. + * This parameter can be one of @arg FDCAN_flags + * @retval FlagStatus + */ +#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR & (__FLAG__)) + +/** + * @brief Clear the specified FDCAN flags. + * @param __HANDLE__ FDCAN handle. + * @param __FLAG__ specifies the flags to clear. + * This parameter can be any combination of @arg FDCAN_flags + * @retval None + */ +#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + ((__HANDLE__)->Instance->IR) = (__FLAG__) + +/** @brief Check if the specified FDCAN interrupt source is enabled or disabled. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ specifies the FDCAN interrupt source to check. + * This parameter can be a value of @arg FDCAN_Interrupts + * @retval ITStatus + */ +#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FDCAN_Exported_Functions + * @{ + */ + +/** @addtogroup FDCAN_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, + pFDCAN_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxEventFifoCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo0CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo1CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferCompleteCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferAbortCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_ErrorStatusCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group2 + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig); +HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, + uint32_t NonMatchingExt, uint32_t RejectRemoteStd, + uint32_t RejectRemoteExt); +HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask); +HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode); +HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue); +HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler); +HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation); +HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan); +uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, + uint32_t TimeoutPeriod); +HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, + uint32_t TdcFilter); +HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group3 + * @{ + */ +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData); +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); +HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, + FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); +HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent); +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_HpMsgStatusTypeDef *HpMsgStatus); +HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ProtocolStatusTypeDef *ProtocolStatus); +HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ErrorCountersTypeDef *ErrorCounters); +uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); +uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); +uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan); +uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group4 + * @{ + */ +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine); +HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, + uint32_t BufferIndexes); +HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs); +void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group5 + * @{ + */ +/* Callback functions *********************************************************/ +void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); +void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); +void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); +void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); +void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); +void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group6 + * @{ + */ +/* Peripheral State functions *************************************************/ +uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan); +HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Variables FDCAN Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Constants FDCAN Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Macros FDCAN Private Macros + * @{ + */ +#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \ + ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \ + ((FORMAT) == FDCAN_FRAME_FD_BRS )) +#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \ + ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \ + ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \ + ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \ + ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK )) +#define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV10) || \ + ((CKDIV) == FDCAN_CLOCK_DIV12) || \ + ((CKDIV) == FDCAN_CLOCK_DIV14) || \ + ((CKDIV) == FDCAN_CLOCK_DIV16) || \ + ((CKDIV) == FDCAN_CLOCK_DIV18) || \ + ((CKDIV) == FDCAN_CLOCK_DIV20) || \ + ((CKDIV) == FDCAN_CLOCK_DIV22) || \ + ((CKDIV) == FDCAN_CLOCK_DIV24) || \ + ((CKDIV) == FDCAN_CLOCK_DIV26) || \ + ((CKDIV) == FDCAN_CLOCK_DIV28) || \ + ((CKDIV) == FDCAN_CLOCK_DIV30)) +#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U)) +#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U)) +#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U)) +#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U)) +#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U)) +#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U)) +#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U)) +#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U)) +#define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_)) +#define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_)) +#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \ + ((MODE) == FDCAN_TX_QUEUE_OPERATION)) +#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \ + ((ID_TYPE) == FDCAN_EXTENDED_ID)) +#define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \ + ((CONFIG) == FDCAN_FILTER_REJECT ) || \ + ((CONFIG) == FDCAN_FILTER_HP ) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP)) +#define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \ + ((LOCATION) == FDCAN_TX_BUFFER2 )) +#define IS_FDCAN_TX_LOCATION_LIST(LOCATION) (((LOCATION) >= FDCAN_TX_BUFFER0) && \ + ((LOCATION) <= (FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2))) +#define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \ + ((FIFO) == FDCAN_RX_FIFO1)) +#define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \ + ((MODE) == FDCAN_RX_FIFO_OVERWRITE)) +#define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \ + ((TYPE) == FDCAN_FILTER_DUAL ) || \ + ((TYPE) == FDCAN_FILTER_MASK )) +#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \ + ((TYPE) == FDCAN_FILTER_DUAL ) || \ + ((TYPE) == FDCAN_FILTER_MASK ) || \ + ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM)) +#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \ + ((TYPE) == FDCAN_REMOTE_FRAME)) +#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \ + ((DLC) == FDCAN_DLC_BYTES_1 ) || \ + ((DLC) == FDCAN_DLC_BYTES_2 ) || \ + ((DLC) == FDCAN_DLC_BYTES_3 ) || \ + ((DLC) == FDCAN_DLC_BYTES_4 ) || \ + ((DLC) == FDCAN_DLC_BYTES_5 ) || \ + ((DLC) == FDCAN_DLC_BYTES_6 ) || \ + ((DLC) == FDCAN_DLC_BYTES_7 ) || \ + ((DLC) == FDCAN_DLC_BYTES_8 ) || \ + ((DLC) == FDCAN_DLC_BYTES_12) || \ + ((DLC) == FDCAN_DLC_BYTES_16) || \ + ((DLC) == FDCAN_DLC_BYTES_20) || \ + ((DLC) == FDCAN_DLC_BYTES_24) || \ + ((DLC) == FDCAN_DLC_BYTES_32) || \ + ((DLC) == FDCAN_DLC_BYTES_48) || \ + ((DLC) == FDCAN_DLC_BYTES_64)) +#define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \ + ((ESI) == FDCAN_ESI_PASSIVE)) +#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \ + ((BRS) == FDCAN_BRS_ON )) +#define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \ + ((FDF) == FDCAN_FD_CAN )) +#define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \ + ((EFC) == FDCAN_STORE_TX_EVENTS)) +#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U) +#define IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U) +#define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \ + ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \ + ((DESTINATION) == FDCAN_REJECT )) +#define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \ + ((DESTINATION) == FDCAN_REJECT_REMOTE)) +#define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \ + ((IT_LINE) == FDCAN_INTERRUPT_LINE1)) +#define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \ + ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL)) +#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16)) +#define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \ + ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \ + ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \ + ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 )) + +#define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET) + +#define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ +#endif /* FDCAN1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_FDCAN_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_flash.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_flash.h new file mode 100644 index 00000000000..aba89c27034 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_flash.h @@ -0,0 +1,831 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_FLASH_H +#define STM32H7RSxx_HAL_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or page erase. + This parameter can be a value of @ref FLASH_Type_Erase */ + uint32_t Sector; /*!< Initial Flash sector to erase when sector erase is enabled + This parameter must be a value between 0 and (max number of sector - 1) + (eg : 15 for 128KB single bank) */ + uint32_t NbSectors; /*!< Number of sectors to be erased. + This parameter must be a value between 1 and + (max number of sectors - value of initial page)*/ +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes Program structure definition + */ +#define FLASH_KEY_DATA_NB_REG (8U) /*!< 8 Key data registers */ + +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a combination of the values of @ref FLASH_OB_TYPE */ + uint32_t WRPState; /*!< Write protection activation or deactivation (used for OPTIONBYTE_WRP). + This parameter can be value of @ref FLASH_OB_WRP_STATE */ + uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected (used for OPTIONBYTE_WRP). + The value of this parameter depend on device used within the same series */ + uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_TYPE */ + uint32_t USERConfig1; /*!< Value of the user option byte (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEV, + @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_nRST_STOP, + @ref FLASH_OB_USER_nRST_STDBY, @ref FLASH_OB_USER_XSPI1_HSLV, + @ref FLASH_OB_USER_XSPI2_HSLV, @ref FLASH_OB_USER_IWDG_STOP, + @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_VDDIO_HSLV */ + uint32_t USERConfig2; /*!< Value of the user option byte (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_ITCM_AXI_SHARE, + @ref FLASH_OB_USER_DTCM_AXI_SHARE, @ref FLASH_OB_USER_ECC_ON_SRAM, + @ref FLASH_OB_USER_I2C_NI3C */ + uint32_t HDPStartPage; /*!< Start address that contains the first 256-byte block of HDP area (used for OPTIONBYTE_HDP). + This parameter must be a value between 0 or 0xFFF */ + uint32_t HDPEndPage; /*!< End address that contains the last 256-byte block of HDP area (used for OPTIONBYTE_HDP). + This parameter must be a value between 0 or 0xFFF */ + uint32_t NVState; /*!< Value of the non-volatile state (used for OPTIONBYTE_NV). + This parameter must be a value of @ref FLASH_OB_NVSTATE */ + uint32_t ROTConfig; /*!< Value of the RoT status (only used for read configuration). + This parameter can be a combination of @ref FLASH_OB_ROT_OEM_PROVD, + @ref FLASH_OB_ROT_DBG_AUTH, @ref FLASH_OB_ROT_IROT_SELECT */ + uint32_t EPOCH; /*!< Value of the epoch (only used for read configuration). + This parameter must be a value between 0x0 and 0xFFFFFF */ +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + HAL_LockTypeDef Lock; /* FLASH locking object */ + uint32_t ErrorCode; /* FLASH error code */ + uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT + context */ + uint32_t Address; /* Internal variable to save address selected for program in IT context */ + uint32_t Sector; /* Internal variable to define the current sector which is being erased in + IT context */ + uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */ +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Flags FLASH Flags Definition + * @{ + */ +#define FLASH_FLAG_EOP FLASH_ISR_EOPF /*!< FLASH End of program flag */ +#define FLASH_FLAG_WRPERR FLASH_ISR_WRPERRF /*!< FLASH Write protection error flag */ +#define FLASH_FLAG_PGSERR FLASH_ISR_PGSERRF /*!< FLASH Programming sequence error flag */ +#define FLASH_FLAG_STRBERR FLASH_ISR_STRBERRF /*!< FLASH Strobe error flag */ +#define FLASH_FLAG_OBLERR FLASH_ISR_OBLERRF /*!< FLASH Option byte loading error flag */ +#define FLASH_FLAG_INCERR FLASH_ISR_INCERRF /*!< FLASH Inconsistency error flag */ +#define FLASH_FLAG_RDSERR FLASH_ISR_RDSERRF /*!< FLASH Read security error flag */ +#define FLASH_FLAG_SNECCERR FLASH_ISR_SNECCERRF /*!< FLASH ECC single error flag */ +#define FLASH_FLAG_DBECCERR FLASH_ISR_DBECCERRF /*!< FLASH ECC double error flag */ +#define FLASH_FLAG_CRCEND FLASH_ISR_CRCENDF /*!< FLASH CRC end of calculation flag */ +#define FLASH_FLAG_CRCERR FLASH_ISR_CRCRDERRF /*!< FLASH CRC error flag */ +#define FLASH_FLAG_KVERR FLASH_OPTISR_KVEF /*!< FLASH Key valid error flag */ +#define FLASH_FLAG_KTERR FLASH_OPTISR_KTEF /*!< FLASH Key transfer error flag */ +#define FLASH_FLAG_OPTERR FLASH_OPTISR_OPTERRF /*!< FLASH Options byte change error flag */ + +#define FLASH_FLAG_ISR_ERRORS (FLASH_FLAG_WRPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_STRBERR | \ + FLASH_FLAG_OBLERR | FLASH_FLAG_INCERR | FLASH_FLAG_RDSERR | \ + FLASH_FLAG_CRCERR) +#define FLASH_FLAG_ECC_ERRORS (FLASH_FLAG_SNECCERR | FLASH_FLAG_DBECCERR) +#define FLASH_FLAG_OPTISR_ERRORS (FLASH_FLAG_KVERR | FLASH_FLAG_KTERR | FLASH_FLAG_OPTERR) +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_ISR_ERRORS | FLASH_FLAG_ECC_ERRORS | FLASH_FLAG_OPTISR_ERRORS) + +#define FLASH_FLAG_ISR_FLAGS (FLASH_FLAG_ISR_ERRORS | FLASH_FLAG_ECC_ERRORS | FLASH_FLAG_EOP) +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition + * @brief FLASH Interrupt definition + * @{ + */ +#define FLASH_IT_EOP FLASH_IER_EOPIE /*!< End of program interrupt source */ +#define FLASH_IT_WRPERR FLASH_IER_WRPERRIE /*!< FLASH Write protection error interrupt source */ +#define FLASH_IT_PGSERR FLASH_IER_PGSERRIE /*!< FLASH Programming sequence error interrupt source */ +#define FLASH_IT_STRBERR FLASH_IER_STRBERRIE /*!< FLASH Strobe error interrupt source */ +#define FLASH_IT_OBLERR FLASH_IER_OBLERRIE /*!< FLASH Option byte loading error interrupt source */ +#define FLASH_IT_INCERR FLASH_IER_INCERRIE /*!< FLASH Inconsistency error interrupt source */ +#define FLASH_IT_RDSERR FLASH_IER_RDSERRIE /*!< FLASH Read security error interrupt source */ +#define FLASH_IT_SNECCERR FLASH_IER_SNECCERRIE /*!< FLASH ECC single error interrupt source */ +#define FLASH_IT_DBECCERR FLASH_IER_DBECCERRIE /*!< FLASH ECC double error interrupt source */ +#define FLASH_IT_CRCEND FLASH_IER_CRCENDIE /*!< FLASH CRC end of calculation interrupt source */ +#define FLASH_IT_CRCERR FLASH_IER_CRCRDERRIE /*!< FLASH CRC error interrupt source */ +#define FLASH_IT_KVERR FLASH_OPTCR_KVEIE /*!< FLASH Key valid error interrupt source */ +#define FLASH_IT_KTERR FLASH_OPTCR_KTEIE /*!< FLASH Key transfer error interrupt source */ +#define FLASH_IT_OPTERR FLASH_OPTCR_OPTERRIE /*!< FLASH Options byte change error interrupt source */ + +#define FLASH_IT_IER (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | FLASH_IT_STRBERR | \ + FLASH_IT_OBLERR | FLASH_IT_INCERR | FLASH_IT_RDSERR | FLASH_IT_SNECCERR | \ + FLASH_IT_DBECCERR | FLASH_IT_CRCEND | FLASH_IT_CRCERR) +#define FLASH_IT_OPTCR (FLASH_IT_KVERR | FLASH_IT_KTERR | FLASH_IT_OPTERR) +/** + * @} + */ + +/** @defgroup FLASH_Error FLASH Error + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U +#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR +#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR +#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR +#define HAL_FLASH_ERROR_OBL FLASH_FLAG_OBLERR +#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR +#define HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR +#define HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR +#define HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR +#define HAL_FLASH_ERROR_CRC FLASH_FLAG_CRCERR +#define HAL_FLASH_ERROR_KV FLASH_FLAG_KVERR +#define HAL_FLASH_ERROR_KT FLASH_FLAG_KTERR +#define HAL_FLASH_ERROR_OPT FLASH_FLAG_OPTERR +/** + * @} + */ + +/** @defgroup FLASH_Type_Erase FLASH Erase Type + * @{ + */ +#define FLASH_TYPEERASE_SECTORS FLASH_CR_SER /*!< Sectors erase activation */ +#define FLASH_TYPEERASE_MASSERASE FLASH_CR_BER /*!< Flash mass erase activation */ +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Program Type + * @{ + */ +#define FLASH_TYPEPROGRAM_BYTE (FLASH_CR_PG | FLASH_CR_FW) /*!< Program a byte (8-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_HALFWORD (FLASH_HALFWORD_MASK | FLASH_CR_PG | FLASH_CR_FW) /*!< Program a half-word (16-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_WORD (FLASH_WORD_MASK | FLASH_CR_PG | FLASH_CR_FW) /*!< Program a word (32-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_DOUBLEWORD (FLASH_DOUBLEWORD_MASK | FLASH_CR_PG | FLASH_CR_FW) /*!< Program a double-word (64-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_QUADWORD (FLASH_CR_PG) /*!< Program a quad-word (128-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_OTP_HALFWORD (FLASH_HALFWORD_MASK | FLASH_CR_PG_OTP | FLASH_CR_FW) /*!< Program a half-word (16-bit) at a OTP address */ +#define FLASH_TYPEPROGRAM_OTP_WORD (FLASH_WORD_MASK | FLASH_CR_PG_OTP | FLASH_CR_FW) /*!< Program a word (32-bit) at a OTP address */ +/** + * @} + */ + +/** @defgroup FLASH_OB_TYPE FLASH Option Bytes Type + * @{ + */ +#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ +#define OPTIONBYTE_USER 0x00000002U /*!< User option byte configuration */ +#define OPTIONBYTE_HDP 0x00000004U /*!< HDP option byte configuration */ +#define OPTIONBYTE_NV 0x00000008U /*!< Non-Volatile State option byte configuration */ +/** + * @} + */ + +/** @defgroup FLASH_OB_WRP_STATE FLASH Option Bytes WRP State + * @{ + */ +#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired sectors */ +#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired sectors */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_TYPE FLASH Option Bytes User Type + * @{ + */ +#define OB_USER_BOR_LEV 0x00000001U /*!< Brownout level */ +#define OB_USER_IWDG_SW 0x00000002U /*!< IWDG control mode */ +#define OB_USER_NRST_STOP 0x00000004U /*!< Stop entry reset */ +#define OB_USER_NRST_STDBY 0x00000008U /*!< Standby entry reset */ +#define OB_USER_XSPI1_HSLV 0x00000010U /*!< XSPI1 High-speed at low voltage */ +#define OB_USER_XSPI2_HSLV 0x00000020U /*!< XSPI2 High-speed at low voltage */ +#define OB_USER_IWDG_STOP 0x00000040U /*!< IWDG Stop mode freeze */ +#define OB_USER_IWDG_STDBY 0x00000080U /*!< IWDG Standby mode freeze */ +#define OB_USER_VDDIO_HSLV 0x00000100U /*!< I/O High-speed at low voltage */ +#define OB_USER_ITCM_AXI_SHARE 0x00000200U /*!< ITCM AXI share */ +#define OB_USER_DTCM_AXI_SHARE 0x00000400U /*!< DTCM AXI share */ +#define OB_USER_SRAM_ECC 0x00000800U /*!< ECC on SRAM */ +#define OB_USER_I2C_NI3C 0x00001000U /*!< I2C Not I3C */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_BOR_LEV FLASH Option Bytes User BOR Level + * @{ + */ +#define OB_BOR_LEVEL_0 0x00000000U /*!< BOR OFF, POR/PDR reset threshold level is applied */ +#define OB_BOR_LEVEL_1 FLASH_OBW1SRP_BOR_LEVEL_0 /*!< BOR Level 1, the threshold level is low (around 2.1 V) */ +#define OB_BOR_LEVEL_2 FLASH_OBW1SRP_BOR_LEVEL_1 /*!< BOR Level 2, the threshold level is medium (around 2.4 V) */ +#define OB_BOR_LEVEL_3 FLASH_OBW1SRP_BOR_LEVEL /*!< BOR Level 3, the threshold level is high (around 2.7 V) */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG control mode + * @{ + */ +#define OB_IWDG_HW 0x00000000U /*!< IWDG watchdog is controlled by hardware */ +#define OB_IWDG_SW FLASH_OBW1SRP_IWDG_HW /*!< IWDG watchdog is controlled by software */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User stop entry reset + * @{ + */ +#define OB_STOP_RST 0x00000000U /*!< Reset generated when entering stop mode */ +#define OB_STOP_NORST FLASH_OBW1SRP_NRST_STOP /*!< No reset generated when entering stop mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nRST_STDBY FLASH Option Bytes User standby entry reset + * @{ + */ +#define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering standby mode */ +#define OB_STANDBY_NORST FLASH_OBW1SRP_NRST_STBY /*!< No reset generated when entering standby mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_XSPI1_HSLV FLASH Option Bytes User XSPI 1 High-Speed at Low-Voltage + * @{ + */ +#define OB_XSPI1_HSLV_DISABLE 0x00000000U /*!< I/O speed optimization at low-voltage disabled */ +#define OB_XSPI1_HSLV_ENABLE FLASH_OBW1SRP_XSPI1_HSLV /*!< I/O speed optimization at low-voltage feature allowed */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_XSPI2_HSLV FLASH Option Bytes User XSPI 2 High-Speed at Low-Voltage + * @{ + */ +#define OB_XSPI2_HSLV_DISABLE 0x00000000U /*!< I/O speed optimization at low-voltage disabled */ +#define OB_XSPI2_HSLV_ENABLE FLASH_OBW1SRP_XSPI2_HSLV /*!< I/O speed optimization at low-voltage feature allowed */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Stop Mode Freeze + * @{ + */ +#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog frozen in Stop mode */ +#define OB_IWDG_STOP_RUN FLASH_OBW1SRP_IWDG_FZ_STOP /*!< Independent watchdog running in Stop mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Standby Mode Freeze + * @{ + */ +#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog frozen in Standby mode */ +#define OB_IWDG_STDBY_RUN FLASH_OBW1SRP_IWDG_FZ_STBY /*!< Independent watchdog running in Standby mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_VDDIO_HSLV FLASH Option Bytes User I/O High-Speed at Low-Voltage + * @{ + */ +#define OB_VDDIO_HSLV_DISABLE 0x00000000U /*!< I/O speed optimization at low-voltage disabled */ +#define OB_VDDIO_HSLV_ENABLE FLASH_OBW1SRP_VDDIO_HSLV /*!< I/O speed optimization at low-voltage feature allowed */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_ITCM_AXI_SHARE FLASH Option Bytes User ITCM AXI share + * @{ + */ +#define OB_ITCM_AXI_SHARE_0 0x00000000U +#define OB_ITCM_AXI_SHARE_1 FLASH_OBW2SRP_ITCM_AXI_SHARE_0 +#define OB_ITCM_AXI_SHARE_2 FLASH_OBW2SRP_ITCM_AXI_SHARE_1 +#define OB_ITCM_AXI_SHARE_3 (FLASH_OBW2SRP_ITCM_AXI_SHARE_0 | FLASH_OBW2SRP_ITCM_AXI_SHARE_1) +#define OB_ITCM_AXI_SHARE_4 FLASH_OBW2SRP_ITCM_AXI_SHARE_2 +#define OB_ITCM_AXI_SHARE_5 (FLASH_OBW2SRP_ITCM_AXI_SHARE_2 | FLASH_OBW2SRP_ITCM_AXI_SHARE_0) +#define OB_ITCM_AXI_SHARE_6 (FLASH_OBW2SRP_ITCM_AXI_SHARE_2 | FLASH_OBW2SRP_ITCM_AXI_SHARE_1) +#define OB_ITCM_AXI_SHARE_7 FLASH_OBW2SRP_ITCM_AXI_SHARE +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_DTCM_AXI_SHARE FLASH Option Bytes User DTCM AXI share + * @{ + */ +#define OB_DTCM_AXI_SHARE_0 0x00000000U +#define OB_DTCM_AXI_SHARE_1 FLASH_OBW2SRP_DTCM_AXI_SHARE_0 +#define OB_DTCM_AXI_SHARE_2 FLASH_OBW2SRP_DTCM_AXI_SHARE_1 +#define OB_DTCM_AXI_SHARE_3 (FLASH_OBW2SRP_DTCM_AXI_SHARE_0 | FLASH_OBW2SRP_DTCM_AXI_SHARE_1) +#define OB_DTCM_AXI_SHARE_4 FLASH_OBW2SRP_DTCM_AXI_SHARE_2 +#define OB_DTCM_AXI_SHARE_5 (FLASH_OBW2SRP_DTCM_AXI_SHARE_2 | FLASH_OBW2SRP_DTCM_AXI_SHARE_0) +#define OB_DTCM_AXI_SHARE_6 (FLASH_OBW2SRP_DTCM_AXI_SHARE_2 | FLASH_OBW2SRP_DTCM_AXI_SHARE_1) +#define OB_DTCM_AXI_SHARE_7 FLASH_OBW2SRP_DTCM_AXI_SHARE +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_ECC_ON_SRAM FLASH Option Bytes User ECC on sRAM + * @{ + */ +#define OB_AXISRAM_ECC_DISABLE 0x00000000U /*!< AXISRAM ECC check disable */ +#define OB_AXISRAM_ECC_ENABLE FLASH_OBW2SRP_ECC_ON_SRAM /*!< AXISRAM ECC check enable */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_I2C_NI3C FLASH Option Bytes User I2C Not I3C + * @{ + */ +#define OB_I2C_NI3C_I2C FLASH_OBW2SRP_I2C_NI3C +#define OB_I2C_NI3C_I3C 0x00000000U +/** + * @} + */ + +/** @defgroup FLASH_OB_NVSTATE FLASH Option Bytes Non-volatile state + * @{ + */ +#define OB_NVSTATE_OPEN (uint8_t)0xB4 +#define OB_NVSTATE_CLOSE (uint8_t)0x51 +/** + * @} + */ + +/** @defgroup FLASH_OB_ROT_OEM_PROVD FLASH Option Bytes Root-Of-Trust OEM Provisioned state + * @{ + */ +#define OB_OEM_PROVD_ENABLE (0xB4UL << FLASH_ROTSR_OEM_PROVD_Pos) /*!< Device is in OEM provisioned state */ +#define OB_OEM_PROVD_DEFAULT (0x6AUL << FLASH_ROTSR_OEM_PROVD_Pos) /*!< Device is not in OEM provisioned state (default value)*/ +/** + * @} + */ + +/** @defgroup FLASH_OB_ROT_DBG_AUTH FLASH Option Bytes Root-Of-Trust Debug authentication method + * @{ + */ +#define OB_DBG_AUTH_LOCKED (0xB4UL << FLASH_ROTSR_DBG_AUTH_Pos) /*!< Locked device (no debug allowed) */ +#define OB_DBG_AUTH_ECDSA_SIGN (0x51UL << FLASH_ROTSR_DBG_AUTH_Pos) /*!< Authentication method using ECDSA signature (NISTP256) */ +#define OB_DBG_AUTH_PASSWORD (0x8AUL << FLASH_ROTSR_DBG_AUTH_Pos) /*!< Authentication method using password */ +#define OB_DBG_AUTH_DEFAULT (0xFFUL << FLASH_ROTSR_DBG_AUTH_Pos) /*!< No authentication method selected (default value) */ +/** + * @} + */ + +/** @defgroup FLASH_OB_ROT_IROT_SELECT FLASH Option Bytes iRoT selection + * @{ + */ +#define OB_IROT_SELECTION_ST (0xB4UL << FLASH_ROTSR_IROT_SELECT_Pos) /*!< ST iRoT is selected at boot */ +#define OB_IROT_SELECTION_OEM (0x6AUL << FLASH_ROTSR_IROT_SELECT_Pos) /*!< OEM iRoT is selected at boot */ +/** + * @} + */ + +/** @defgroup FLASH_Latency FLASH Latency + * @{ + */ +#define FLASH_LATENCY_0 0U /*!< FLASH Zero wait state */ +#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */ +#define FLASH_LATENCY_2 (FLASH_ACR_LATENCY_1 | FLASH_ACR_WRHIGHFREQ_0) /*!< FLASH Two wait states */ +#define FLASH_LATENCY_3 (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0 | FLASH_ACR_WRHIGHFREQ_0) /*!< FLASH Three wait states */ +#define FLASH_LATENCY_4 (FLASH_ACR_LATENCY_2 | FLASH_ACR_WRHIGHFREQ_1) /*!< FLASH Four wait states */ +#define FLASH_LATENCY_5 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0 | FLASH_ACR_WRHIGHFREQ_1) /*!< FLASH Five wait states */ +#define FLASH_LATENCY_6 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Six wait state */ +#define FLASH_LATENCY_7 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Seven wait states */ +#define FLASH_LATENCY_8 (FLASH_ACR_LATENCY_3 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Eight wait states */ +#define FLASH_LATENCY_9 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_0 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Nine wait states */ +#define FLASH_LATENCY_10 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_1 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Ten wait states */ +#define FLASH_LATENCY_11 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Eleven wait states */ +#define FLASH_LATENCY_12 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Twelve wait states */ +#define FLASH_LATENCY_13 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Thirteen wait states */ +#define FLASH_LATENCY_14 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Fourteen wait states */ +#define FLASH_LATENCY_15 (FLASH_ACR_LATENCY | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Fifteen wait states */ +/** + * @} + */ + +/** @defgroup FLASH_Keys FLASH Keys + * @{ + */ +#define FLASH_KEY1 0x45670123U /*!< Flash key1 */ +#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 + to unlock the FLASH registers access */ + +#define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ +#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 + to allow option bytes operations */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @brief macros to control FLASH features + * @{ + */ + +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency + * This parameter can be one of the following values : + * @arg FLASH_LATENCY_0: FLASH Zero wait state + * @arg FLASH_LATENCY_1: FLASH One wait state + * @arg FLASH_LATENCY_2: FLASH Two wait states + * @arg FLASH_LATENCY_3: FLASH Three wait states + * @arg FLASH_LATENCY_4: FLASH Four wait states + * @arg FLASH_LATENCY_5: FLASH Five wait states + * @arg FLASH_LATENCY_6: FLASH Six wait states + * @arg FLASH_LATENCY_7: FLASH Seven wait states + * @arg FLASH_LATENCY_8: FLASH Eight wait states + * @arg FLASH_LATENCY_9: FLASH Nine wait states + * @arg FLASH_LATENCY_10: FLASH Ten wait states + * @arg FLASH_LATENCY_11: FLASH Eleven wait states + * @arg FLASH_LATENCY_12: FLASH Twelve wait states + * @arg FLASH_LATENCY_13: FLASH Thirteen wait states + * @arg FLASH_LATENCY_14: FLASH Fourteen wait states + * @arg FLASH_LATENCY_15: FLASH Fifteen wait states + * @retval None + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, (FLASH_ACR_LATENCY |\ + FLASH_ACR_WRHIGHFREQ), (__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * This return value can be one of the following values : + * @arg FLASH_LATENCY_0: FLASH Zero wait state + * @arg FLASH_LATENCY_1: FLASH One wait state + * @arg FLASH_LATENCY_2: FLASH Two wait states + * @arg FLASH_LATENCY_3: FLASH Three wait states + * @arg FLASH_LATENCY_4: FLASH Four wait states + * @arg FLASH_LATENCY_5: FLASH Five wait states + * @arg FLASH_LATENCY_6: FLASH Six wait states + * @arg FLASH_LATENCY_7: FLASH Seven wait states + * @arg FLASH_LATENCY_8: FLASH Eight wait states + * @arg FLASH_LATENCY_9: FLASH Nine wait states + * @arg FLASH_LATENCY_10: FLASH Ten wait states + * @arg FLASH_LATENCY_11: FLASH Eleven wait states + * @arg FLASH_LATENCY_12: FLASH Twelve wait states + * @arg FLASH_LATENCY_13: FLASH Thirteen wait states + * @arg FLASH_LATENCY_14: FLASH Fourteen wait states + * @arg FLASH_LATENCY_15: FLASH Fifteen wait states + */ +#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, (FLASH_ACR_LATENCY | FLASH_ACR_WRHIGHFREQ)) + +/** + * @} + */ + +/** @defgroup FLASH_Interrupt FLASH Interrupts Macros + * @brief macros to handle FLASH interrupts + * @{ + */ + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of program interrupt + * @arg FLASH_IT_WRPERR: Write protection error interrupt + * @arg FLASH_IT_PGSERR: Programming sequence error interrupt + * @arg FLASH_IT_STRBERR: Strobe error interrupt + * @arg FLASH_IT_OBLERR: Option byte loading error interrupt + * @arg FLASH_IT_INCERR: Inconsistency error interrupt + * @arg FLASH_IT_RDSERR: Read security error interrupt + * @arg FLASH_IT_SNECCERR: ECC single error interrupt + * @arg FLASH_IT_DBECCERR: ECC double error interrupt + * @arg FLASH_IT_CRCEND: CRC end of calculation interrupt + * @arg FLASH_IT_CRCERR: CRC error interrupt + * @arg FLASH_IT_KVERR: Key valid error interrupt + * @arg FLASH_IT_KTERR: Key transfer error interrupt + * @arg FLASH_IT_OPTERR: Options byte change error interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_IER) != 0U)\ + { SET_BIT(FLASH->IER, ((__INTERRUPT__) & FLASH_IT_IER)); }\ + if(((__INTERRUPT__) & FLASH_IT_OPTCR) != 0U)\ + { SET_BIT(FLASH->OPTCR, ((__INTERRUPT__) & FLASH_IT_OPTCR)); }\ + } while(0) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of program interrupt + * @arg FLASH_IT_WRPERR: Write protection error interrupt + * @arg FLASH_IT_PGSERR: Programming sequence error interrupt + * @arg FLASH_IT_STRBERR: Strobe error interrupt + * @arg FLASH_IT_OBLERR: Option byte loading error interrupt + * @arg FLASH_IT_INCERR: Inconsistency error interrupt + * @arg FLASH_IT_RDSERR: Read security error interrupt + * @arg FLASH_IT_SNECCERR: ECC single error interrupt + * @arg FLASH_IT_DBECCERR: ECC double error interrupt + * @arg FLASH_IT_CRCEND: CRC end of calculation interrupt + * @arg FLASH_IT_CRCERR: CRC error interrupt + * @arg FLASH_IT_KVERR: Key valid error interrupt + * @arg FLASH_IT_KTERR: Key transfer error interrupt + * @arg FLASH_IT_OPTERR: Options byte change error interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_IER) != 0U)\ + { CLEAR_BIT(FLASH->IER, ((__INTERRUPT__) & FLASH_IT_IER)); }\ + if(((__INTERRUPT__) & FLASH_IT_OPTCR) != 0U)\ + { CLEAR_BIT(FLASH->OPTCR, ((__INTERRUPT__) & FLASH_IT_OPTCR)); }\ + } while(0) + +/** + * @brief Check whether the specified FLASH flag is set or not. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_EOP: FLASH End of program flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag + * @arg FLASH_FLAG_STRBERR: FLASH Strobe error flag + * @arg FLASH_FLAG_OBLERR: FLASH Option byte loading error flag + * @arg FLASH_FLAG_INCERR: FLASH Inconsistency error flag + * @arg FLASH_FLAG_RDSERR: FLASH Read security error flag + * @arg FLASH_FLAG_SNECCERR: FLASH ECC single error flag + * @arg FLASH_FLAG_DBECCERR: FLASH ECC double error flag + * @arg FLASH_FLAG_CRCEND: FLASH CRC end of calculation flag + * @arg FLASH_FLAG_CRCERR: FLASH CRC error flag + * @arg FLASH_FLAG_KVERR: FLASH Key valid error flag + * @arg FLASH_FLAG_KTERR: FLASH Key transfer error flag + * @arg FLASH_FLAG_OPTERR: FLASH Options byte change error flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_OPTISR_ERRORS) != 0U) ? \ + (READ_BIT(FLASH->OPTISR, (__FLAG__)) == (__FLAG__)) : \ + (READ_BIT(FLASH->ISR, (__FLAG__)) == (__FLAG__))) + +/** + * @brief Clear the FLASH's pending flags. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP: FLASH End of program flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag + * @arg FLASH_FLAG_STRBERR: FLASH Strobe error flag + * @arg FLASH_FLAG_OBLERR: FLASH Option byte loading error flag + * @arg FLASH_FLAG_INCERR: FLASH Inconsistency error flag + * @arg FLASH_FLAG_RDSERR: FLASH Read security error flag + * @arg FLASH_FLAG_SNECCERR: FLASH ECC single error flag + * @arg FLASH_FLAG_DBECCERR: FLASH ECC double error flag + * @arg FLASH_FLAG_CRCEND: FLASH CRC end of calculation flag + * @arg FLASH_FLAG_CRCERR: FLASH CRC error flag + * @arg FLASH_FLAG_KVERR: FLASH Key valid error flag + * @arg FLASH_FLAG_KTERR: FLASH Key transfer error flag + * @arg FLASH_FLAG_OPTERR: FLASH Options byte change error flag + * @retval None + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_OPTISR_ERRORS) != 0U)\ + { WRITE_REG(FLASH->OPTICR, ((__FLAG__) & FLASH_FLAG_OPTISR_ERRORS)); }\ + if(((__FLAG__) & FLASH_FLAG_ISR_FLAGS) != 0U)\ + { WRITE_REG(FLASH->ICR, ((__FLAG__) & FLASH_FLAG_ISR_FLAGS)); }\ + } while(0) +/** + * @} + */ + +/* Include FLASH HAL Extended module */ +#include "stm32h7rsxx_hal_flash_ex.h" + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/* Program operation functions ***********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +uint32_t HAL_FLASH_GetError(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +#define FLASH_BANK_SIZE FLASH_SIZE + +#define FLASH_SECTOR_NB 8U + +#define FLASH_SECTOR_SIZE 0x2000UL /* 8 KB */ + +#define FLASH_HDP_BLOCK_NB 0x100U + +#define FLASH_TIMEOUT_VALUE 1000U /* 1 s */ + +#define FLASH_BYTE_MASK 0x00000000U +#define FLASH_HALFWORD_MASK 0x40000000U +#define FLASH_WORD_MASK 0x80000000U +#define FLASH_DOUBLEWORD_MASK 0xC0000000U +#define FLASH_WORD_SIZE_MASK FLASH_DOUBLEWORD_MASK +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) ||\ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_BYTE) ||\ + ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) ||\ + ((VALUE) == FLASH_TYPEPROGRAM_WORD) ||\ + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) ||\ + ((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) ||\ + ((VALUE) == FLASH_TYPEPROGRAM_OTP_HALFWORD) ||\ + ((VALUE) == FLASH_TYPEPROGRAM_OTP_WORD)) + +#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) + +#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= OTP_AREA_BASE) && ((ADDRESS) < (OTP_AREA_BASE + OTP_SIZE))) + +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) + +#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_NB) + +#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP |\ + OPTIONBYTE_USER | OPTIONBYTE_HDP | OPTIONBYTE_NV))) + +#define IS_OB_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) + +#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFU) && ((TYPE) != 0U)) + +#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ + ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3)) + +#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) + +#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) + +#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) + +#define IS_OB_USER_XSPI1_HSLV(VALUE) (((VALUE) == OB_XSPI1_HSLV_DISABLE) || ((VALUE) == OB_XSPI1_HSLV_ENABLE)) + +#define IS_OB_USER_XSPI2_HSLV(VALUE) (((VALUE) == OB_XSPI2_HSLV_DISABLE) || ((VALUE) == OB_XSPI2_HSLV_ENABLE)) + +#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) + +#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) + +#define IS_OB_USER_VDDIO_HSLV(VALUE) (((VALUE) == OB_VDDIO_HSLV_DISABLE) || ((VALUE) == OB_VDDIO_HSLV_ENABLE)) + +#define IS_OB_USER_ITCM_AXI_SHARE(VALUE) (((VALUE) == OB_ITCM_AXI_SHARE_0) || ((VALUE) == OB_ITCM_AXI_SHARE_1) || \ + ((VALUE) == OB_ITCM_AXI_SHARE_2) || ((VALUE) == OB_ITCM_AXI_SHARE_3) || \ + ((VALUE) == OB_ITCM_AXI_SHARE_4) || ((VALUE) == OB_ITCM_AXI_SHARE_5) || \ + ((VALUE) == OB_ITCM_AXI_SHARE_6) || ((VALUE) == OB_ITCM_AXI_SHARE_7)) + +#define IS_OB_USER_DTCM_AXI_SHARE(VALUE) (((VALUE) == OB_DTCM_AXI_SHARE_0) || ((VALUE) == OB_DTCM_AXI_SHARE_1) || \ + ((VALUE) == OB_DTCM_AXI_SHARE_2) || ((VALUE) == OB_DTCM_AXI_SHARE_3) || \ + ((VALUE) == OB_DTCM_AXI_SHARE_4) || ((VALUE) == OB_DTCM_AXI_SHARE_5) || \ + ((VALUE) == OB_DTCM_AXI_SHARE_6) || ((VALUE) == OB_DTCM_AXI_SHARE_7)) + +#define IS_OB_USER_AXISRAM_ECC(VALUE) (((VALUE) == OB_AXISRAM_ECC_ENABLE) || ((VALUE) == OB_AXISRAM_ECC_DISABLE)) + +#define IS_OB_USER_I2C_NI3C(VALUE) (((VALUE) == OB_I2C_NI3C_I2C) || ((VALUE) == OB_I2C_NI3C_I3C)) + +#define IS_OB_HDP_PAGE(PAGE) ((PAGE) < FLASH_HDP_BLOCK_NB) + +#define IS_OB_NVSTATE(VALUE) (((VALUE) == OB_NVSTATE_OPEN) || ((VALUE) ==OB_NVSTATE_CLOSE)) + +#define IS_OB_ROT_TYPE(VALUE) ((VALUE) <= 0x7U) + +#define IS_OB_OEM_PROVD(VALUE) ((VALUE) <= 0x000000FFU) + +#define IS_OB_DBG_AUTH(VALUE) ((VALUE) <= 0x0000FF00U) + +#define IS_OB_IROT_SELECT(VALUE) ((VALUE) <= 0xFF000000U) + +#define IS_OB_EPOCH(VALUE) ((VALUE) <= 0xFFFFFFU) + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ + ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ + ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ + ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ + ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ + ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ + ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ + ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_FLASH_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_flash_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_flash_ex.h new file mode 100644 index 00000000000..c74a492107c --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_flash_ex.h @@ -0,0 +1,262 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_FLASH_EX_H +#define STM32H7RSxx_HAL_FLASH_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t Index; /*!< Index of the key. + This parameter can be a value between 0 and 31 */ + uint32_t Size; /*!< Size of the key. + This parameter must be a value of @ref FLASH_Key_Size */ + uint32_t HDPLLevel; /*!< HDPL level of the key. + This parameter must be a value of @ref FLASH_KEY_Level */ +} FLASH_KeyConfigTypeDef; + +/** + * @brief FLASH CRC configuration structure definition + */ +typedef struct +{ + uint32_t TypeCRC; /*!< CRC Selection Type. + This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */ + + uint32_t BurstSize; /*!< CRC Burst Size. + This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */ + + uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation + This parameter must be a value between 0 and (max number of sector - 1)*/ + + uint32_t NbSectors; /*!< Number of sectors to be computed. + This parameter must be a value between 1 and + (max number of sectors - value of Initial sector)*/ + + uint32_t CRCStartAddr; /*!< CRC Start address. + This parameter must be a value between begin address and end address of a bank */ + + uint32_t CRCEndAddr; /*!< CRC End address. + This parameter must be a value between CRC Start address and end address of a bank */ + +} FLASH_CRCInitTypeDef; + +/** + * @brief FLASH ECC information structure definition + */ +typedef struct +{ + uint32_t Area; /*!< Area from which an ECC was detected. + This parameter can be a value of @ref FLASHEx_ECC_Area */ + uint32_t Address; /*!< Flash address from which en ECC error was detected. + This parameter must be a value between begin address and end address of the Flash */ + uint32_t MasterID; /*!< Master that initiated transfer on which error was detected + This parameter can be a value of @ref FLASHEx_ECC_Master */ +} FLASH_EccInfoTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Constants + * @{ + */ +/** @defgroup FLASH_Key_Size FLASH Option Bytes Key Size + * @{ + */ +#define FLASH_KEY_32_BITS 0x0000000U /*!< Key size is 32 bits */ +#define FLASH_KEY_64_BITS FLASH_OBKCR_OBKSIZE_0 /*!< Key size is 64 bits */ +#define FLASH_KEY_128_BITS FLASH_OBKCR_OBKSIZE_1 /*!< Key size is 128 bits */ +#define FLASH_KEY_256_BITS FLASH_OBKCR_OBKSIZE /*!< Key size is 256 bits */ +/** + * @} + */ + +/** @defgroup FLASH_KEY_Level FLASH Option Bytes Key HDPL level + * @{ + */ +#define FLASH_KEY_LEVEL_CURRENT 0x00000000U /*!< Key stored for the HDPL indicated in SBS_HDPLSR */ +#define FLASH_KEY_LEVEL_NEXT FLASH_OBKCR_NEXTKL_0 /*!< Key stored for the HDPL indicated in SBS_HDPLSR + 1 */ +#define FLASH_KEY_LEVEL_PLUS_TWO FLASH_OBKCR_NEXTKL_1 /*!< Key stored for the HDPL indicated in SBS_HDPLSR + 2 */ +/** + * @} + */ + +/** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type + * @{ + */ +#define FLASH_CRC_ADDR 0x00000000U /*!< CRC selection type by address */ +#define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT /*!< CRC selection type by sectors */ +#define FLASH_CRC_BANK (FLASH_CRCCR_ALL_SECT | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type all bank */ +/** + * @} + */ + +/** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size + * @{ + */ +#define FLASH_CRC_BURST_SIZE_4 0x00000000U /*!< Every burst has a size of 4 Flash words (64 Bytes) */ +#define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0 /*!< Every burst has a size of 16 Flash words (256 Bytes) */ +#define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1 /*!< Every burst has a size of 64 Flash words (1 kByte) */ +#define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST /*!< Every burst has a size of 256 Flash words (4 kBytes) */ +/** + * @} + */ + +/** @defgroup FLASHEx_ECC_Area FLASH ECC Area + * @{ + */ +#define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */ +#define FLASH_ECC_AREA_SYSTEM 0x00000001U /*!< System FLASH area */ +#define FLASH_ECC_AREA_OTP 0x00000002U /*!< FLASH OTP area */ +#define FLASH_ECC_AREA_READ_ONLY 0x00000004U /*!< FLASH Read-only area */ +/** + * @} + */ + +/** @defgroup FLASHEx_ECC_Master FLASH ECC Master + * @{ + */ +#define FLASH_ECC_MASTER_CPU1 0x00000000U /*!< ECC error occurs on a CPU1 transaction */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/* Extended Program operation functions *************************************/ +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(const FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(const FLASH_EraseInitTypeDef *pEraseInit); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(const FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_FLASHEx_OTPLockConfig(uint32_t OTPLBlock); +uint32_t HAL_FLASHEx_GetOTPLock(void); +HAL_StatusTypeDef HAL_FLASHEx_KeyConfig(const FLASH_KeyConfigTypeDef *pKeyConfig, const uint32_t *pKey); +HAL_StatusTypeDef HAL_FLASHEx_GetKey(const FLASH_KeyConfigTypeDef *pKeyConfig, uint32_t *pKey); +HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(const FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result); +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group3 + * @{ + */ +void HAL_FLASHEx_EnableEccCorrectionInterrupt(void); +void HAL_FLASHEx_DisableEccCorrectionInterrupt(void); +void HAL_FLASHEx_EnableEccDetectionInterrupt(void); +void HAL_FLASHEx_DisableEccDetectionInterrupt(void); +void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData); +void HAL_FLASHEx_ECCD_IRQHandler(void); +void HAL_FLASHEx_EccDetectionCallback(void); +void HAL_FLASHEx_EccCorrectionCallback(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +void FLASH_SectorErase(uint32_t Sector); +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASH Private Macros + * @{ + */ +#define IS_KEY_INDEX(VALUE) ((VALUE) < 0x20U) + +#define IS_KEY_SIZE(VALUE) (((VALUE) == FLASH_KEY_32_BITS) || ((VALUE) == FLASH_KEY_64_BITS) || \ + ((VALUE) == FLASH_KEY_128_BITS) || ((VALUE) == FLASH_KEY_256_BITS)) + +#define IS_KEY_HDPL_LEVEL(VALUE) (((VALUE) == FLASH_KEY_LEVEL_CURRENT) || \ + ((VALUE) == FLASH_KEY_LEVEL_NEXT) || \ + ((VALUE) == FLASH_KEY_LEVEL_PLUS_TWO)) + +#define IS_OB_OTP_BLOCK(VALUE) ((VALUE) <= 0xFFFFU) + +#define IS_FLASH_TYPE_CRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || ((VALUE) == FLASH_CRC_SECTORS) ||\ + ((VALUE) == FLASH_CRC_BANK)) + +#define IS_FLASH_BURST_SIZE_CRC(VALUE) (((VALUE) == FLASH_CRC_BURST_SIZE_4) || ((VALUE) == FLASH_CRC_BURST_SIZE_16) ||\ + ((VALUE) == FLASH_CRC_BURST_SIZE_64) || ((VALUE) == FLASH_CRC_BURST_SIZE_256)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_FLASH_EX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gfxmmu.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gfxmmu.h new file mode 100644 index 00000000000..f3cd13852fa --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gfxmmu.h @@ -0,0 +1,370 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_gfxmmu.h + * @author MCD Application Team + * @brief Header file of GFXMMU HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_GFXMMU_H +#define STM32H7RSxx_HAL_GFXMMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +#if defined(GFXMMU) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup GFXMMU + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Types GFXMMU Exported Types + * @{ + */ + +/** + * @brief HAL GFXMMU states definition + */ +typedef enum +{ + HAL_GFXMMU_STATE_RESET = 0x00U, /*!< GFXMMU not initialized. */ + HAL_GFXMMU_STATE_READY = 0x01U, /*!< GFXMMU initialized and ready for use. */ +} HAL_GFXMMU_StateTypeDef; + +/** + * @brief GFXMMU buffers structure definition + */ +typedef struct +{ + uint32_t Buf0Address; /*!< Physical address of buffer 0. */ + uint32_t Buf1Address; /*!< Physical address of buffer 1. */ + uint32_t Buf2Address; /*!< Physical address of buffer 2. */ + uint32_t Buf3Address; /*!< Physical address of buffer 3. */ +} GFXMMU_BuffersTypeDef; + +/** + * @brief GFXMMU interrupts structure definition + */ +typedef struct +{ + FunctionalState Activation; /*!< Interrupts enable/disable. */ + uint32_t UsedInterrupts; /*!< Interrupts used. + This parameter can be a values combination of @ref GFXMMU_Interrupts. + @note: Useful only when interrupts are enabled. */ +} GFXMMU_InterruptsTypeDef; + +/** + * @brief GFXMMU init structure definition + */ +typedef struct +{ + uint32_t BlockSize; /*!< Size of virtual memory block. + This parameter can be a value of @ref GFXMMU_BlockSize. */ + uint32_t DefaultValue; /*!< Value returned when virtual memory location not physically mapped. */ + /* @note: Useful only when address translation is enabled. */ + FunctionalState AddressTranslation; /*!< Address translation enable/disable. */ + GFXMMU_BuffersTypeDef Buffers; /*!< Physical buffers addresses. */ + GFXMMU_InterruptsTypeDef Interrupts; /*!< Interrupts parameters. */ +} GFXMMU_InitTypeDef; + +/** + * @brief GFXMMU handle structure definition + */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +typedef struct __GFXMMU_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */ +{ + GFXMMU_TypeDef *Instance; /*!< GFXMMU instance. */ + GFXMMU_InitTypeDef Init; /*!< GFXMMU init parameters. */ + HAL_GFXMMU_StateTypeDef State; /*!< GFXMMU state. */ + __IO uint32_t ErrorCode; /*!< GFXMMU error code. */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + void (*ErrorCallback)(struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU error callback. */ + void (*MspInitCallback)(struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP init callback. */ + void (*MspDeInitCallback)(struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP de-init callback. */ +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */ +} GFXMMU_HandleTypeDef; + +/** + * @brief GFXMMU LUT line structure definition + */ +typedef struct +{ + uint32_t LineNumber; /*!< LUT line number. + This parameter must be a number between Min_Data = 0 and Max_Data = 1023. */ + uint32_t LineStatus; /*!< LUT line enable/disable. + This parameter can be a value of @ref GFXMMU_LutLineStatus. */ + uint32_t FirstVisibleBlock; /*!< First visible block on this line. + This parameter must be a number between Min_Data = 0 and Max_Data = 255. */ + uint32_t LastVisibleBlock; /*!< Last visible block on this line. + This parameter must be a number between Min_Data = 0 and Max_Data = 255. */ + int32_t LineOffset; /*!< Offset of block 0 of the current line in physical buffer. + This parameter must be a number between Min_Data = -255 and Max_Data = 261888. + @note: Line offset has to be computed with the following formula: + LineOffset = [(Blocks already used) - (1st visible block)]. */ +} GFXMMU_LutLineTypeDef; + +/** + * @brief GFXMMU packing structure definition + */ +typedef struct +{ + FunctionalState Buffer0Activation; /*!< Packing on buffer 0 enable/disable. */ + uint32_t Buffer0Mode; /*!< Buffer 0 packing mode. + This parameter can be a value of @ref GFXMMU_PackingModes. */ + FunctionalState Buffer1Activation; /*!< Packing on buffer 1 enable/disable. */ + uint32_t Buffer1Mode; /*!< Buffer 1 packing mode. + This parameter can be a value of @ref GFXMMU_PackingModes. */ + FunctionalState Buffer2Activation; /*!< Packing on buffer 2 enable/disable. */ + uint32_t Buffer2Mode; /*!< Buffer 2 packing mode. + This parameter can be a value of @ref GFXMMU_PackingModes. */ + FunctionalState Buffer3Activation; /*!< Packing on buffer 3 enable/disable. */ + uint32_t Buffer3Mode; /*!< Buffer 3 packing mode. + This parameter can be a value of @ref GFXMMU_PackingModes. */ + uint32_t DefaultAlpha; /*!< Default alpha value. + This parameter must be a number between Min_Data = 0 and Max_Data = 255. */ +} GFXMMU_PackingTypeDef; + +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +/** + * @brief GFXMMU callback ID enumeration definition + */ +typedef enum +{ + HAL_GFXMMU_ERROR_CB_ID = 0x00U, /*!< GFXMMU error callback ID. */ + HAL_GFXMMU_MSPINIT_CB_ID = 0x01U, /*!< GFXMMU MSP init callback ID. */ + HAL_GFXMMU_MSPDEINIT_CB_ID = 0x02U /*!< GFXMMU MSP de-init callback ID. */ +} HAL_GFXMMU_CallbackIDTypeDef; + +/** + * @brief GFXMMU callback pointer definition + */ +typedef void (*pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu); +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Constants GFXMMU Exported Constants + * @{ + */ + +/** @defgroup GFXMMU_BlockSize GFXMMU block size + * @{ + */ +#define GFXMMU_12BYTE_BLOCKS GFXMMU_CR_BS /*!< Blocks of 12-byte. */ +#define GFXMMU_16BYTE_BLOCKS 0x00000000U /*!< Blocks of 16-byte. */ +/** + * @} + */ + +/** @defgroup GFXMMU_Interrupts GFXMMU interrupts + * @{ + */ +#define GFXMMU_BUS_MASTER_ERROR_IT GFXMMU_CR_AMEIE /*!< Bus master error interrupt. */ +#define GFXMMU_BUFFER0_OVERFLOW_IT GFXMMU_CR_B0OIE /*!< Buffer 0 overflow interrupt. */ +#define GFXMMU_BUFFER1_OVERFLOW_IT GFXMMU_CR_B1OIE /*!< Buffer 1 overflow interrupt. */ +#define GFXMMU_BUFFER2_OVERFLOW_IT GFXMMU_CR_B2OIE /*!< Buffer 2 overflow interrupt. */ +#define GFXMMU_BUFFER3_OVERFLOW_IT GFXMMU_CR_B3OIE /*!< Buffer 3 overflow interrupt. */ +/** + * @} + */ + +/** @defgroup GFXMMU_Error_Code GFXMMU Error Code + * @{ + */ +#define GFXMMU_ERROR_NONE 0x00000000U /*!< No error. */ +#define GFXMMU_ERROR_BUFFER0_OVERFLOW GFXMMU_SR_B0OF /*!< Buffer 0 overflow. */ +#define GFXMMU_ERROR_BUFFER1_OVERFLOW GFXMMU_SR_B1OF /*!< Buffer 1 overflow. */ +#define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow. */ +#define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow. */ +#define GFXMMU_ERROR_BUS_MASTER GFXMMU_SR_AMEF /*!< Bus master error. */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +#define GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error. */ +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup GFXMMU_LutLineStatus GFXMMU LUT line status + * @{ + */ +#define GFXMMU_LUT_LINE_DISABLE 0x00000000U /*!< LUT line disabled. */ +#define GFXMMU_LUT_LINE_ENABLE GFXMMU_LUTxL_EN /*!< LUT line enabled. */ +/** + * @} + */ + +/** @defgroup GFXMMU_PackingModes GFXMMU packing modes + * @{ + */ +#define GFXMMU_PACKING_MSB_REMOVE 0x00000000U /*!< Remove MSB during packing operation. */ +#define GFXMMU_PACKING_LSB_REMOVE 0x00000001U /*!< Remove LSB during packing operation. */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Macros GFXMMU Exported Macros + * @{ + */ + +/** @brief Reset GFXMMU handle state. + * @param __HANDLE__ GFXMMU handle. + * @retval None + */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_GFXMMU_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET) +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GFXMMU_Exported_Functions GFXMMU Exported Functions + * @{ + */ + +/** @addtogroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu); +HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu); +void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu); +void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu); +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +/* GFXMMU callbacks register/unregister functions *****************************/ +HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID, + pGFXMMU_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup GFXMMU_Exported_Functions_Group2 Operations functions + * @{ + */ +/* Operation functions ********************************************************/ +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber, + uint32_t Address); + +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber); + +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_LutLineTypeDef *lutLine); + +HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_BuffersTypeDef *Buffers); + +HAL_StatusTypeDef HAL_GFXMMU_ConfigPacking(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_PackingTypeDef *pPacking); + +void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu); + +void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu); +/** + * @} + */ + +/** @defgroup GFXMMU_Exported_Functions_Group3 State functions + * @{ + */ +/* State function *************************************************************/ +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu); + +uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GFXMMU_Private_Macros GFXMMU Private Macros + * @{ + */ +#define IS_GFXMMU_BLOCK_SIZE(VALUE) (((VALUE) == GFXMMU_12BYTE_BLOCKS) || \ + ((VALUE) == GFXMMU_16BYTE_BLOCKS)) +#define IS_GFXMMU_LUT_LINE_OFFSET(VALUE) (((VALUE) >= -255) && ((VALUE) <= 261888)) + +#define IS_GFXMMU_BUFFER_ADDRESS(VALUE) (((VALUE) & 0xFU) == 0U) + +#define IS_GFXMMU_INTERRUPTS(VALUE) (((VALUE) & 0x1FU) != 0U) + +#define IS_GFXMMU_LUT_LINE(VALUE) ((VALUE) < 1024U) + +#define IS_GFXMMU_LUT_LINES_NUMBER(VALUE) (((VALUE) > 0U) && ((VALUE) <= 1024U)) + +#define IS_GFXMMU_LUT_LINE_STATUS(VALUE) (((VALUE) == GFXMMU_LUT_LINE_DISABLE) || \ + ((VALUE) == GFXMMU_LUT_LINE_ENABLE)) + +#define IS_GFXMMU_LUT_BLOCK(VALUE) ((VALUE) < 256U) + +#define IS_GFXMMU_PACKING_MODE(VALUE) (((VALUE) == GFXMMU_PACKING_MSB_REMOVE) || \ + ((VALUE) == GFXMMU_PACKING_LSB_REMOVE)) + +#define IS_GFXMMU_DEFAULT_ALPHA_VALUE(VALUE) ((VALUE) < 256U) +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ +#endif /* GFXMMU */ +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_GFXMMU_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gfxtim.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gfxtim.h new file mode 100644 index 00000000000..f83ad3b7a73 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gfxtim.h @@ -0,0 +1,929 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_gfxtim.h + * @author MCD Application Team + * @brief Header file of GFXTIM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_GFXTIM_H +#define STM32H7RSxx_HAL_GFXTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +#if defined (GFXTIM) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup GFXTIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GFXTIM_Exported_Types GFXTIM Exported Types + * @{ + */ + +/** + * @brief HAL GFXTIM states definition + */ +typedef enum +{ + HAL_GFXTIM_STATE_RESET = 0x00U, /*!< GFXTIM not initialized */ + HAL_GFXTIM_STATE_READY = 0x01U, /*!< GFXTIM initialized and ready for use */ + HAL_GFXTIM_STATE_ERROR = 0xFFU /*!< GFXTIM state error */ +} HAL_GFXTIM_StateTypeDef; + +/** + * @brief GFXTIM initialization structure definition + */ +typedef struct +{ + uint32_t SynchroSrc; /*!< Synchronization signals (HSYNC and VSYNC) sources. + This parameter can be a value of @ref GFXTIM_SynchroSrc */ + uint32_t TearingEffectSrc; /*!< Tearing effect source + This parameter can be a value of @ref GFXTIM_TearingEffectSrc */ + uint32_t TearingEffectPolarity; /*!< Tearing effect source + This parameter can be a value of @ref GFXTIM_TearingEffectPolarity */ + uint32_t TearingEffectInterrupt; /*!< Tearing effect interrupt Enable or Disable + This parameter can be a value of @ref GFXTIM_Interrupt */ +} GFXTIM_InitTypeDef; + +/** + * @brief GFXTIM handle structure definition + */ +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1) +typedef struct __GFXTIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ +{ + GFXTIM_TypeDef *Instance; /*!< GFXTIM instance */ + __IO HAL_GFXTIM_StateTypeDef State; /*!< GFXTIM state */ + __IO uint32_t ErrorCode; /*!< GFXTIM error code */ + GFXTIM_InitTypeDef Init; /*!< GFXTIM initialization */ +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1) + void (*HAL_GFXTIM_AbsoluteTimer_AFCC1Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Absolute frame counter compare 1 callback */ + void (*HAL_GFXTIM_AbsoluteTimer_AFCOFCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Absolute frame counter overflow callback */ + void (*HAL_GFXTIM_AbsoluteTimer_ALCC1Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Absolute line counter compare 1 callback */ + void (*HAL_GFXTIM_AbsoluteTimer_ALCC2Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Absolute line counter compare 2 callback */ + void (*HAL_GFXTIM_AbsoluteTimer_ALCOFCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Absolute line counter overflow callback */ + void (*HAL_GFXTIM_RelativeTimer_RFC1RCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Relative frame counter 1 reload callback */ + void (*HAL_GFXTIM_RelativeTimer_RFC2RCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Relative frame counter 2 reload callback */ + void (*HAL_GFXTIM_TECallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Tearing effect callback */ + void (*HAL_GFXTIM_EventGenerator_EV1Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Event events 1 callback */ + void (*HAL_GFXTIM_EventGenerator_EV2Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Event events 2 callback */ + void (*HAL_GFXTIM_EventGenerator_EV3Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Event events 3 callback */ + void (*HAL_GFXTIM_EventGenerator_EV4Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Event events 4 callback */ + void (*HAL_GFXTIM_WatchdogTimer_AlarmCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Watchdog alarm callback */ + void (*HAL_GFXTIM_WatchdogTimer_PreAlarmCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Watchdog pre alarm callback */ + void (*ErrorCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM error callback */ + void (*MspInitCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM MSP initialization user callback */ + void (*MspDeInitCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM MSP de-initialization user callback */ +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ +} GFXTIM_HandleTypeDef; + + +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1) +/** + * @brief GFXTIM callback ID enumeration definition + */ +typedef enum +{ + HAL_GFXTIM_AFC_COMPARE1_CB_ID = 1U, /*!< GFXTIM Absolute frame counter compare 1 callback ID */ + HAL_GFXTIM_AFC_OVERFLOW_CB_ID = 2U, /*!< GFXTIM Absolute frame counter overflow callback ID */ + HAL_GFXTIM_ALC_COMPARE1_CB_ID = 3U, /*!< GFXTIM Absolute line counter compare 1 callback ID */ + HAL_GFXTIM_ALC_COMPARE2_CB_ID = 4U, /*!< GFXTIM Absolute line counter compare 2 callback ID */ + HAL_GFXTIM_ALC_OVERFLOW_CB_ID = 5U, /*!< GFXTIM Absolute line counter overflow callback ID */ + HAL_GFXTIM_RFC1_RELOAD_CB_ID = 6U, /*!< GFXTIM Relative frame counter 1 reload callback ID */ + HAL_GFXTIM_RFC2_RELOAD_CB_ID = 7U, /*!< GFXTIM Relative frame counter 2 reload callback ID */ + HAL_GFXTIM_TE_CB_ID = 8U, /*!< GFXTIM External tearing effect callback ID */ + HAL_GFXTIM_EVENT1_CB_ID = 9U, /*!< GFXTIM Event events 1 callback ID */ + HAL_GFXTIM_EVENT2_CB_ID = 10U, /*!< GFXTIM Event events 2 callback ID */ + HAL_GFXTIM_EVENT3_CB_ID = 11U, /*!< GFXTIM Event events 3 callback ID */ + HAL_GFXTIM_EVENT4_CB_ID = 12U, /*!< GFXTIM Event events 4 callback ID */ + HAL_GFXTIM_WDG_ALARM_CB_ID = 13U, /*!< GFXTIM Watchdog alarm callback ID */ + HAL_GFXTIM_WDG_PREALARM_CB_ID = 14U, /*!< GFXTIM Watchdog pre alarm callback ID */ + HAL_GFXTIM_ERROR_CB_ID = 15U, /*!< GFXTIM error callback ID */ + HAL_GFXTIM_MSP_INIT_CB_ID = 16U, /*!< GFXTIM MSP initialization user callback ID */ + HAL_GFXTIM_MSP_DEINIT_CB_ID = 17U, /*!< GFXTIM MSP de-initialization user callback ID */ +} HAL_GFXTIM_CallbackIDTypeDef; + +/** + * @brief GFXTIM callback pointers definition + */ +typedef void (*pGFXTIM_CallbackTypeDef)(GFXTIM_HandleTypeDef *hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + + + + +/** + * @brief GFXTIM clock generator structure definition + */ +typedef struct +{ + uint32_t LCCHwReloadSrc; /*!< Line Clock Counter hardware reload source + This parameter can be a value of @ref GFXTIM_LCCHwReloadSrc */ + + uint32_t LCCReloadValue; /*!< Line Clock Counter reload value (22 bits) + This parameter must be a number between Min_Data = 1 and Max_Data = 4194303 */ + + uint32_t LCCClockSrc; /*!< Line Clock Counter Clock Source + This parameter can be a value of @ref GFXTIM_LCCClockSrc */ + + uint32_t LineClockSrc; /*!< Line Clock Source + This parameter can be a value of @ref GFXTIM_LineClockSrc */ + + uint32_t FCCHwReloadSrc; /*!< Frame Clock Counter hardware reload source + This parameter can be a value of @ref GFXTIM_FCCHwReloadSrc */ + + uint32_t FCCReloadValue; /*!< Frame Clock Counter reload value (12 bits) + This parameter must be a number between Min_Data = 1 and Max_Data = 4095 */ + + uint32_t FCCClockSrc; /*!< Frame Clock Counter Clock Source + This parameter can be a value of @ref GFXTIM_FCCClockSrc */ + + uint32_t FrameClockSrc; /*!< Frame Clock Source + This parameter can be a value of @ref GFXTIM_FrameClockSrc */ + + uint32_t LineClockCalib; /*!< Debug purpose + This parameter can be a value of @ref GFXTIM_LineClockCalib */ + + uint32_t FrameClockCalib; /*!< Debug purpose + This parameter can be a value of @ref GFXTIM_FrameClockCalib */ +} GFXTIM_ClockGeneratorConfigTypeDef; + +/** + * @brief GFXTIM absolute timer configuration structure + */ +typedef struct +{ + uint32_t FrameCompare1Value; /*!< Absolute Frame Compare 1 value (20 bits) + This parameter must be a number between 1 and 1048575 */ + + uint32_t FrameCounterValue; /*!< Absolute Frame Counter initial value (20 bits) + This parameter must be a number between 1 and 1048575 */ + + uint32_t FrameOverflowInterrupt; /*!< Absolute Frame Counter Overflow Interrupt Enable or Disable + This parameter can be a value of @ref GFXTIM_Interrupt */ + + uint32_t FrameCompare1Interrupt; /*!< Absolute Frame Compare 1 Interrupt Enable or Disable + This parameter can be a value of @ref GFXTIM_Interrupt */ + + uint32_t LineCompare1Value; /*!< Absolute Line Compare 1 value (12 bits) + This parameter must be a number between 1 and 4095 */ + + uint32_t LineCompare2Value; /*!< Absolute Line Compare 2 value (12 bits) + This parameter must be a number between 1 and 4095 */ + + uint32_t LineCounterValue; /*!< Absolute Line Counter value (12 bits) + This parameter must be a number between 1 and 4095 */ + + uint32_t LineOverflowInterrupt; /*!< Absolute Line Counter Overflow Interrupt Enable or Disable + This parameter can be a value of @ref GFXTIM_Interrupt */ + + uint32_t LineCompare1Interrupt; /*!< Absolute Line Compare 1 Interrupt Enable or Disable + This parameter can be a value of @ref GFXTIM_Interrupt */ + + uint32_t LineCompare2Interrupt; /*!< Absolute Line Compare 2 Interrupt Enable or Disable + This parameter can be a value of @ref GFXTIM_Interrupt */ +} GFXTIM_AbsoluteTimerConfigTypeDef; + + +/** + * @brief GFXTIM relative timer configuration structure + */ +typedef struct +{ + uint32_t AutoReloadValue; /*!< Auto reload value (12 bits) + This parameter must be a number between 1 and 4095 */ + + uint32_t CounterMode; /*!< Counter Mode + This parameter can be a value of GFXTIM_RelativeCounterMode */ + uint32_t ReloadInterrupt; /*!< Relative Frame Counter Reload Interrupt Enable or Disable + This parameter can be a value of @ref GFXTIM_Interrupt */ +} GFXTIM_RelativeTimerConfigTypeDef; + + +/** + * @brief GFXTIM event generator configuration structure + */ +typedef struct +{ + uint32_t LineEvent; /*!< Line event selection + This parameter can be a value of GFXTIM_EventLine */ + + uint32_t FrameEvent; /*!< Frmae event selection + This parameter can be a value of GFXTIM_EventFrame */ + + uint32_t EventInterrupt; /*!< Event interrupt Enable or Disable + This parameter can be a value of @ref GFXTIM_Interrupt */ +} GFXTIM_EventGeneratorConfigTypeDef; + +/** + * @brief GFXTIM watchdog configuration structure + */ +typedef struct +{ + uint32_t ClockSrc; /*!< Clock source + This parameter can be a value of GFXTIM_WatchdogClockSrc */ + + uint32_t AutoReloadValue; /*!< Reload value (16 bits) + This parameter must be a number between 1 and 65535 */ + + uint32_t HwReloadConfig; /*!< Hardware reload configuration + This parameter can be a value of GFXTIM_WatchdogHwReloadConfig */ + + uint32_t PreAlarmValue; /*!< Pre-alarm value (16 bits) + This parameter must be a number between 1 and 65535 */ + + uint32_t AlarmInterrupt; /*!< Interrupt Enable or Disable when watchdog counter reaches 0 + This parameter can be a value of @ref GFXTIM_Interrupt */ + + uint32_t PreAlarmInterrupt; /*!< Interrupt Enable or Disable when watchdog counter reaches pre-alarm value + This parameter can be a value of @ref GFXTIM_Interrupt */ +} GFXTIM_WatchdogConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GFXTIM_Exported_Constants GFXTIM Exported Constants + * @{ + */ + +/** @defgroup GFXTIM_ErrorCode GFXTIM Error Code + * @{ + */ +#define GFXTIM_ERROR_NONE 0U /*!< No error */ +#define GFXTIM_ERROR_STATE 1U /*!< State error */ +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1) +#define GFXTIM_ERROR_INVALID_CALLBACK 2U /*!< Invalid callback error occurs */ +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup GFXTIM_Interrupt GFXTIM Interrupt + * @{ + */ +#define GFXTIM_IT_DISABLE 0U /*!< gfxtim_interrupt disable */ +#define GFXTIM_IT_ENABLE 1U /*!< gfxtim_interrupt enable */ + +/** + * @} + */ + +/** @defgroup GFXTIM_SynchroSrc GFXTIM Synchronization Source + * @{ + */ +#define GFXTIM_SYNC_SRC_HSYNC_VSYNC_0 0U /*!< gfxtim_hsync[0] and gfxtim_vsync[0] are used as synchronization source */ +#define GFXTIM_SYNC_SRC_HSYNC_VSYNC_1 GFXTIM_CR_SYNCS_0 /*!< gfxtim_hsync[1] and gfxtim_vsync[1] are used as synchronization source */ +#define GFXTIM_SYNC_SRC_HSYNC_VSYNC_2 GFXTIM_CR_SYNCS_1 /*!< gfxtim_hsync[2] and gfxtim_vsync[2] are used as synchronization source */ +#define GFXTIM_SYNC_SRC_HSYNC_VSYNC_3 (GFXTIM_CR_SYNCS_0 | GFXTIM_CR_SYNCS_1) /*!< gfxtim_hsync[3] and gfxtim_vsync[3] are used as synchronization source */ +/** + * @} + */ + +/** @defgroup GFXTIM_TearingEffectSrc GFXTIM Tearing Effect Source + * @{ + */ +#define GFXTIM_TE_SRC_GPIO 0U /*!< Input pad rising */ +#define GFXTIM_TE_SRC_ITE GFXTIM_CR_TES_0 /*!< gfxtim_ite rising */ +#define GFXTIM_TE_SRC_HSYNC GFXTIM_CR_TES_1 /*!< HSYNC (see SynchroSrc) rising */ +#define GFXTIM_TE_SRC_VSYNC (GFXTIM_CR_TES_0 | GFXTIM_CR_TES_1) /*!< VSYNC (see SynchroSrc) rising */ +/** + * @} + */ + +/** @defgroup GFXTIM_TearingEffectPolarity GFXTIM Tearing Effect Polarity + * @{ + */ +#define GFXTIM_TE_RISING_EDGE 0U /*!< Tearing Effect active on rizing edge */ +#define GFXTIM_TE_FALLING_EDGE GFXTIM_CR_TEPOL /*!< Tearing Effect active on falling edge */ +/** + * @} + */ + +/** @defgroup GFXTIM_LCCHwReloadSrc GFXTIM Line Clock Counter Hardware Reload Source + * @{ + */ +#define GFXTIM_LCC_HW_RELOAD_SRC_NONE 0U /*!< No hardware reload */ +#define GFXTIM_LCC_HW_RELOAD_SRC_FCC_UNDERFLOW GFXTIM_CGCR_LCCHRS_0 /*!< FCC underflow */ +#define GFXTIM_LCC_HW_RELOAD_SRC_HSYNC_RISING GFXTIM_CGCR_LCCHRS_1 /*!< HSYNC rising */ +#define GFXTIM_LCC_HW_RELOAD_SRC_HSYNC_FALLING (GFXTIM_CGCR_LCCHRS_0 | GFXTIM_CGCR_LCCHRS_1) /*!< HSYNC falling */ +#define GFXTIM_LCC_HW_RELOAD_SRC_VSYNC_RISING GFXTIM_CGCR_LCCHRS_2 /*!< VSYNC rising */ +#define GFXTIM_LCC_HW_RELOAD_SRC_VSYNC_FALLING (GFXTIM_CGCR_LCCHRS_2 | GFXTIM_CGCR_LCCHRS_0) /*!< VSYNC falling */ +#define GFXTIM_LCC_HW_RELOAD_SRC_TE_RISING (GFXTIM_CGCR_LCCHRS_2 | GFXTIM_CGCR_LCCHRS_1) /*!< TE rising */ +#define GFXTIM_LCC_HW_RELOAD_SRC_TE_FALLING (GFXTIM_CGCR_LCCHRS_2 | GFXTIM_CGCR_LCCHRS_1 | GFXTIM_CGCR_LCCHRS_0) /*!< TE falling */ +/** + * @} + */ + +/** @defgroup GFXTIM_LCCClockSrc GFXTIM Line Clock Counter Clock Source + * @{ + */ +#define GFXTIM_LCC_CLK_SRC_DISABLE 0U /*!< Disable line clock counter */ +#define GFXTIM_LCC_CLK_SRC_SYSCLOCK GFXTIM_CGCR_LCCCS /*!< System clock as line clock counter source*/ +/** + * @} + */ + +/** @defgroup GFXTIM_LineClockSrc GFXTIM Line Clock Source + * @{ + */ +#define GFXTIM_LINE_CLK_SRC_LCC_UNDERFLOW 0U /*!< Line Clock Counter underflow */ +#define GFXTIM_LINE_CLK_SRC_FCC_UNDERFLOW GFXTIM_CGCR_LCS_0 /*!< Frame Clock Counter underflow */ +#define GFXTIM_LINE_CLK_SRC_HSYNC_RISING GFXTIM_CGCR_LCS_1 /*!< HSYNC rising edge */ +#define GFXTIM_LINE_CLK_SRC_HSYNC_FALLING (GFXTIM_CGCR_LCS_0 | GFXTIM_CGCR_LCS_1) /*!< HSYNC falling edge*/ +#define GFXTIM_LINE_CLK_SRC_VSYNC_RISING GFXTIM_CGCR_LCS_2 /*!< VSYNC rising edge*/ +#define GFXTIM_LINE_CLK_SRC_VSYNC_FALLING (GFXTIM_CGCR_LCS_2 | GFXTIM_CGCR_LCS_0) /*!< VSYNC falling edge*/ +#define GFXTIM_LINE_CLK_SRC_TE_RISING (GFXTIM_CGCR_LCS_2 | GFXTIM_CGCR_LCS_1) /*!< TE rising edge*/ +#define GFXTIM_LINE_CLK_SRC_TE_FALLING (GFXTIM_CGCR_LCS_2 | GFXTIM_CGCR_LCS_1 | GFXTIM_CGCR_LCS_0) /*!< TE falling edge*/ +/** + * @} + */ + +/** @defgroup GFXTIM_FCCHwReloadSrc GFXTIM Frame Clock Counter Hardware Reload source + * @{ + */ +#define GFXTIM_FCC_HW_RELOAD_SRC_NONE 0U /*!< No hardware reload */ +#define GFXTIM_FCC_HW_RELOAD_SRC_LCC_UNDERFLOW GFXTIM_CGCR_FCCHRS_0 /*!< Line Clock Counter underflow */ +#define GFXTIM_FCC_HW_RELOAD_SRC_HSYNC_RISING GFXTIM_CGCR_FCCHRS_1 /*!< HSYNC rising edge */ +#define GFXTIM_FCC_HW_RELOAD_SRC_HSYNC_FALLING (GFXTIM_CGCR_FCCHRS_0 | GFXTIM_CGCR_FCCHRS_1) /*!< HSYNC falling edge */ +#define GFXTIM_FCC_HW_RELOAD_SRC_VSYNC_RISING GFXTIM_CGCR_FCCHRS_2 /*!< VSYNC rising edge */ +#define GFXTIM_FCC_HW_RELOAD_SRC_VSYNC_FALLING (GFXTIM_CGCR_FCCHRS_2 | GFXTIM_CGCR_FCCHRS_0) /*!< VSYNC falling edge */ +#define GFXTIM_FCC_HW_RELOAD_SRC_TE_RISING (GFXTIM_CGCR_FCCHRS_2 | GFXTIM_CGCR_FCCHRS_1) /*!< TE rising edge */ +#define GFXTIM_FCC_HW_RELOAD_SRC_TE_FALLING (GFXTIM_CGCR_FCCHRS_2 | GFXTIM_CGCR_FCCHRS_1 | GFXTIM_CGCR_FCCHRS_0) /*!< TE falling edge */ +/** + * @} + */ + +/** @defgroup GFXTIM_FCCClockSrc GFXTIM Frame CLock Counter Clock Source + * @{ + */ +#define GFXTIM_FCC_CLK_SRC_DISABLE 0U /*!< Disable */ +#define GFXTIM_FCC_CLK_SRC_LCC_UNDERFLOW GFXTIM_CGCR_FCCCS_0 /*!< Line Clock Counter underflow */ +#define GFXTIM_FCC_CLK_SRC_HSYNC_RISING GFXTIM_CGCR_FCCCS_1 /*!< HSYNC rising edge */ +#define GFXTIM_FCC_CLK_SRC_HSYNC_FALLING (GFXTIM_CGCR_FCCCS_0 | GFXTIM_CGCR_FCCCS_1) /*!< HSYNC falling edge */ +#define GFXTIM_FCC_CLK_SRC_VSYNC_RISING GFXTIM_CGCR_FCCCS_2 /*!< VSYNC rising edge */ +#define GFXTIM_FCC_CLK_SRC_VSYNC_FALLING (GFXTIM_CGCR_FCCCS_2 | GFXTIM_CGCR_FCCCS_0) /*!< VSYNC falling edge */ +#define GFXTIM_FCC_CLK_SRC_TE_RISING (GFXTIM_CGCR_FCCCS_2 | GFXTIM_CGCR_FCCCS_1) /*!< TE rising edge */ +#define GFXTIM_FCC_CLK_SRC_TE_FALLING (GFXTIM_CGCR_FCCCS_2 | GFXTIM_CGCR_FCCCS_1 | GFXTIM_CGCR_FCCCS_0) /*!< TE falling edge */ +/** + * @} + */ + +/** @defgroup GFXTIM_FrameClockSrc GFXTIM GFXTIM Frame Clock Source + * @{ + */ +#define GFXTIM_FRAME_CLK_SRC_LCC_UNDERFLOW 0U /*!< Line Clock Counter underflow */ +#define GFXTIM_FRAME_CLK_SRC_FCC_UNDERFLOW GFXTIM_CGCR_FCS_0 /*!< Frame Clock Counter underflow */ +#define GFXTIM_FRAME_CLK_SRC_HSYNC_RISING GFXTIM_CGCR_FCS_1 /*!< HSYNC rising edge */ +#define GFXTIM_FRAME_CLK_SRC_HSYNC_FALLING (GFXTIM_CGCR_FCS_0 | GFXTIM_CGCR_FCS_1) /*!< HSYNC falling edge */ +#define GFXTIM_FRAME_CLK_SRC_VSYNC_RISING GFXTIM_CGCR_FCS_2 /*!< VSYNC rising edge */ +#define GFXTIM_FRAME_CLK_SRC_VSYNC_FALLING (GFXTIM_CGCR_FCS_2 | GFXTIM_CGCR_FCS_0) /*!< VSYNC falling edge */ +#define GFXTIM_FRAME_CLK_SRC_TE_RISING (GFXTIM_CGCR_FCS_2 | GFXTIM_CGCR_FCS_1) /*!< TE rising edge */ +#define GFXTIM_FRAME_CLK_SRC_TE_FALLING (GFXTIM_CGCR_FCS_2 | GFXTIM_CGCR_FCS_1 | GFXTIM_CGCR_FCS_0) /*!< TE falling edge */ +/** + * @} + */ + +/** @defgroup GFXTIM_LineClockCalib GFXTIM Line Clock Calibration Output + * @{ + */ +#define GFXTIM_LINE_CLK_CALIB_DISABLE 0U /*!< Disable Line clock calibration */ +#define GFXTIM_LINE_CLK_CALIB_ENABLE GFXTIM_CR_LCCOE /*!< Enable Line clock calibration */ +/** + * @} + */ + +/** @defgroup GFXTIM_FrameClockCalib GFXTIM Frame Clock Calibration Output (for debug purpose) + * @{ + */ +#define GFXTIM_FRAME_CLK_CALIB_DISABLE 0U /*!< Frame clock output calibration Disable */ +#define GFXTIM_FRAME_CLK_CALIB_ENABLE GFXTIM_CR_FCCOE /*!< Frame clock output calibration Enable */ +/** + * @} + */ + +/** @defgroup GFXTIM_ClockGeneratorCounter GFXTIM Clock Generator Counter + * @{ + */ +#define GFXTIM_LINE_CLK_COUNTER GFXTIM_CGCR_LCCFR /*!< Line clock counter */ +#define GFXTIM_FRAME_CLK_COUNTER GFXTIM_CGCR_FCCFR /*!< Frame clock counter */ +/** + * @} + */ + +/** @defgroup GFXTIM_AbsoluteTime GFXTIM Absolute Time + * @{ + */ +#define GFXTIM_ABSOLUTE_GLOBAL_TIME 0x00000014U /*!< Absolute global time (frame and line) counters ATR*/ +#define GFXTIM_ABSOLUTE_FRAME_TIME 0x00000015U /*!< Absolute frame counter AFCR */ +#define GFXTIM_ABSOLUTE_LINE_TIME 0x00000016U /*!< Absolute line counter ALCR */ +/** + * @} + */ + +/** @defgroup GFXTIM_AbsoluteLineComparator GFXTIM Absolute Line Comparator + * @{ + */ +#define GFXTIM_ABSOLUTE_LINE_COMPARE1 0x1CU /*!< Absolute line compare 1 */ +#define GFXTIM_ABSOLUTE_LINE_COMPARE2 0x1DU /*!< Absolute line compare 2 */ +/** + * @} + */ + + +/** @defgroup GFXTIM_RelativeCounterMode GFXTIM Relative Frame Counter Mode + * @{ + */ +#define GFXTIM_MODE_ONE_SHOT 0U /*!< Relative Frame Counter One Shot Mode*/ +#define GFXTIM_MODE_CONTINUOUS 1U /*!< Relative Frame Counter Continuous Mode */ +/** + * @} + */ + +/** @defgroup GFXTIM_RelativeTimer GFXTIM Relative Timer + * @{ + */ +#define GFXTIM_RELATIVE_TIMER1 0U /*!< Relative Timer 1*/ +#define GFXTIM_RELATIVE_TIMER2 1U /*!< Relative Timer 2 */ +/** + * @} + */ + +/** @defgroup GFXTIM_EventLineSrc GFXTIM Event generator Line source selection + * @{ + */ +#define GFXTIM_LINE_EVENT_NONE (0U << GFXTIM_EVSR_LES1_Pos) /*!< None */ +#define GFXTIM_LINE_EVENT_ALC_OVERFLOW (1U << GFXTIM_EVSR_LES1_Pos) /*!< Absolute line counter overflow */ +#define GFXTIM_LINE_EVENT_TE (2U << GFXTIM_EVSR_LES1_Pos) /*!< Tearing effect */ +#define GFXTIM_LINE_EVENT_ALC1_COMPARE (4U << GFXTIM_EVSR_LES1_Pos) /*!< Absolute line counter 1 compare */ +#define GFXTIM_LINE_EVENT_ALC2_COMPARE (5U << GFXTIM_EVSR_LES1_Pos) /*!< Absolute line counter 2 compare */ +/** + * @} + */ + +/** @defgroup GFXTIM_EventFrameSrc GFXTIM Event generator Frame Source selection + * @{ + */ +#define GFXTIM_FRAME_EVENT_NONE (0U << GFXTIM_EVSR_FES1_Pos ) /*!< None */ +#define GFXTIM_FRAME_EVENT_AFC_OVERFLOW (1U << GFXTIM_EVSR_FES1_Pos ) /*!< Absolute frame counter overflow */ +#define GFXTIM_FRAME_EVENT_AFC_COMPARE (2U << GFXTIM_EVSR_FES1_Pos ) /*!< Absolute frame counter compare */ +#define GFXTIM_FRAME_EVENT_RFC1_RELOAD (4U << GFXTIM_EVSR_FES1_Pos ) /*!< Relative frame counter 1 reload */ +#define GFXTIM_FRAME_EVENT_RFC2_RELOAD (5U << GFXTIM_EVSR_FES1_Pos ) /*!< Relative frame counter 1 reload */ +/** + * @} + */ + +/** @defgroup GFXTIM_EventGenerator GFXTIM Event Generator ID + * @{ + */ +#define GFXTIM_EVENT_GENERATOR_1 0U /*!< Event Generator 1 */ +#define GFXTIM_EVENT_GENERATOR_2 1U /*!< Event Generator 2 */ +#define GFXTIM_EVENT_GENERATOR_3 2U /*!< Event Generator 3 */ +#define GFXTIM_EVENT_GENERATOR_4 3U /*!< Event Generator 4 */ +/** + * @} + */ + + +/** @defgroup GFXTIM_WatchdogHwReloadConfig GFXTIM Watchdog hardware reload configuration + * @{ + */ +#define GFXTIM_WATCHDOG_HW_RELOAD_DISABLE (0U << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdog hardware reload is disable */ +#define GFXTIM_WATCHDOG_HW_RELOAD_RISING_EDGE (1U << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdog is reload on rising edge of gfxtim_wrld */ +#define GFXTIM_WATCHDOG_HW_RELOAD_FALLING_EDGE (2U << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdog is reload on falling edge of gfxtim_wrld */ +/** + * @} + */ + +/** @defgroup GFXTIM_WatchdogClockSrc GFXTIM Watchdog clock source + * @{ + */ +#define GFXTIM_WATCHDOG_CLK_SRC_LINE_CLK (0U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Line Clock */ +#define GFXTIM_WATCHDOG_CLK_SRC_FRAME_CLK (1U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Frame Clock */ +#define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_RISING (2U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC rising edge */ +#define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_FALLING (3U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC falling edge */ +#define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_RISING (4U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC rising edge */ +#define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_FALLING (5U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC falling edge */ +#define GFXTIM_WATCHDOG_CLK_SRC_TE_RISING (6U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effect rising edge */ +#define GFXTIM_WATCHDOG_CLK_SRC_TE_FALLING (7U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effect falling edge */ +#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_1 (8U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 1 output */ +#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_2 (9U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 2 output */ +#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_3 (10U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 3 output */ +#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_4 (11U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 4 output */ +/** + * @} + */ + +/** @defgroup GFXTIM_Flag GFXTIM flags + * @{ + */ +#define GFXTIM_FLAG_AFCO GFXTIM_ISR_AFCOF /* Absolute Frame Counter Overflow Flag */ +#define GFXTIM_FLAG_ALCO GFXTIM_ISR_ALCOF /* Absolute Line Counter Overflow Flag */ +#define GFXTIM_FLAG_TE GFXTIM_ISR_TEF /* Tearing Effect Flag */ +#define GFXTIM_FLAG_AFCC1 GFXTIM_ISR_AFCC1F /* Absolute Frame Counter Compare 1 Flag */ +#define GFXTIM_FLAG_ALCC1 GFXTIM_ISR_ALCC1F /* Absolute Line Counter Compare 1 Flag */ +#define GFXTIM_FLAG_ALCC2 GFXTIM_ISR_ALCC2F /* Absolute Line Counter Compare 2 Flag */ +#define GFXTIM_FLAG_RFC1R GFXTIM_ISR_RFC1RF /* Relative Frame Counter 1 Reload Flag */ +#define GFXTIM_FLAG_RFC2R GFXTIM_ISR_RFC2RF /* Relative Frame Counter 2 Reload Flag */ +#define GFXTIM_FLAG_EV1 GFXTIM_ISR_EV1F /* Event 1 Flag */ +#define GFXTIM_FLAG_EV2 GFXTIM_ISR_EV2F /* Event 2 Flag */ +#define GFXTIM_FLAG_EV3 GFXTIM_ISR_EV3F /* Event 3 Flag */ +#define GFXTIM_FLAG_EV4 GFXTIM_ISR_EV4F /* Event 4 Flag */ +#define GFXTIM_FLAG_WDGA GFXTIM_ISR_WDGAF /* Watchdog Alarm Flag */ +#define GFXTIM_FLAG_WDGP GFXTIM_ISR_WDGPF /* Watchdog Pre-alarm Flag */ +/** + * @} + */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GFXTIM_Private_Macros GFXTIM Private Macros + * @{ + */ +#define IS_GFXTIM_INTERRUPT(PARAM) (((PARAM) == GFXTIM_IT_ENABLE ) || \ + ((PARAM) == GFXTIM_IT_DISABLE )) + +#define IS_GFXTIM_SYNC_SRC(PARAM) (((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_0) || \ + ((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_1) || \ + ((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_2) || \ + ((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_3)) + +#define IS_GFXTIM_TE_SRC(PARAM) (((PARAM) == GFXTIM_TE_SRC_GPIO ) || \ + ((PARAM) == GFXTIM_TE_SRC_ITE ) || \ + ((PARAM) == GFXTIM_TE_SRC_HSYNC ) || \ + ((PARAM) == GFXTIM_TE_SRC_VSYNC )) + +#define IS_GFXTIM_TE_POLARITY(PARAM) (((PARAM) == GFXTIM_TE_RISING_EDGE ) || \ + ((PARAM) == GFXTIM_TE_FALLING_EDGE )) + +#define IS_GFXTIM_LCC_HW_RELOAD_SRC(PARAM) (((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_NONE ) || \ + ((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_FCC_UNDERFLOW) || \ + ((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_HSYNC_RISING ) || \ + ((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_HSYNC_FALLING) || \ + ((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_VSYNC_RISING ) || \ + ((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_VSYNC_FALLING) || \ + ((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_TE_RISING ) || \ + ((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_TE_FALLING )) + +#define IS_GFXTIM_LCC_CLK_SRC(PARAM) (((PARAM) == GFXTIM_LCC_CLK_SRC_DISABLE) || \ + ((PARAM) == GFXTIM_LCC_CLK_SRC_SYSCLOCK)) + +#define IS_GFXTIM_LINE_CLK_SRC(PARAM) (((PARAM) == GFXTIM_LINE_CLK_SRC_LCC_UNDERFLOW) || \ + ((PARAM) == GFXTIM_LINE_CLK_SRC_FCC_UNDERFLOW) || \ + ((PARAM) == GFXTIM_LINE_CLK_SRC_HSYNC_RISING ) || \ + ((PARAM) == GFXTIM_LINE_CLK_SRC_HSYNC_FALLING) || \ + ((PARAM) == GFXTIM_LINE_CLK_SRC_VSYNC_RISING ) || \ + ((PARAM) == GFXTIM_LINE_CLK_SRC_VSYNC_FALLING) || \ + ((PARAM) == GFXTIM_LINE_CLK_SRC_TE_RISING) || \ + ((PARAM) == GFXTIM_LINE_CLK_SRC_TE_FALLING)) + +#define IS_GFXTIM_FCC_HW_RELOAD_SRC(PARAM) (((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_NONE) || \ + ((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_LCC_UNDERFLOW) || \ + ((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_HSYNC_RISING ) || \ + ((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_HSYNC_FALLING) || \ + ((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_VSYNC_RISING ) || \ + ((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_VSYNC_FALLING) || \ + ((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_TE_RISING) || \ + ((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_TE_FALLING)) + +#define IS_GFXTIM_FCC_CLK_SRC(PARAM) (((PARAM) == GFXTIM_FCC_CLK_SRC_DISABLE) || \ + ((PARAM) == GFXTIM_FCC_CLK_SRC_LCC_UNDERFLOW) || \ + ((PARAM) == GFXTIM_FCC_CLK_SRC_HSYNC_RISING ) || \ + ((PARAM) == GFXTIM_FCC_CLK_SRC_HSYNC_FALLING) || \ + ((PARAM) == GFXTIM_FCC_CLK_SRC_VSYNC_RISING ) || \ + ((PARAM) == GFXTIM_FCC_CLK_SRC_VSYNC_FALLING) || \ + ((PARAM) == GFXTIM_FCC_CLK_SRC_TE_RISING) || \ + ((PARAM) == GFXTIM_FCC_CLK_SRC_TE_FALLING)) + +#define IS_GFXTIM_FRAME_CLK_SRC(PARAM) (((PARAM) == GFXTIM_FRAME_CLK_SRC_LCC_UNDERFLOW) || \ + ((PARAM) == GFXTIM_FRAME_CLK_SRC_FCC_UNDERFLOW) || \ + ((PARAM) == GFXTIM_FRAME_CLK_SRC_HSYNC_RISING ) || \ + ((PARAM) == GFXTIM_FRAME_CLK_SRC_HSYNC_FALLING) || \ + ((PARAM) == GFXTIM_FRAME_CLK_SRC_VSYNC_RISING ) || \ + ((PARAM) == GFXTIM_FRAME_CLK_SRC_VSYNC_FALLING) || \ + ((PARAM) == GFXTIM_FRAME_CLK_SRC_TE_RISING) || \ + ((PARAM) == GFXTIM_FRAME_CLK_SRC_TE_FALLING)) + +#define IS_GFXTIM_LINE_CLK_CALIB(PARAM) (((PARAM) == GFXTIM_LINE_CLK_CALIB_DISABLE) || \ + ((PARAM) == GFXTIM_LINE_CLK_CALIB_ENABLE)) + +#define IS_GFXTIM_FRAME_CLK_CALIB(PARAM) (((PARAM) == GFXTIM_FRAME_CLK_CALIB_DISABLE) || \ + ((PARAM) == GFXTIM_FRAME_CLK_CALIB_ENABLE)) + +#define IS_GFXTIM_CLOCK_GENERATOR_COUNTER(PARAM) (((PARAM) == GFXTIM_LINE_CLK_COUNTER) || \ + ((PARAM) == GFXTIM_FRAME_CLK_COUNTER) || \ + ((PARAM) == (GFXTIM_LINE_CLK_COUNTER | \ + GFXTIM_FRAME_CLK_COUNTER))) + +#define IS_GFXTIM_ABSOLUTE_TIME(PARAM) (((PARAM) == GFXTIM_ABSOLUTE_GLOBAL_TIME) || \ + ((PARAM) == GFXTIM_ABSOLUTE_FRAME_TIME) || \ + ((PARAM) == GFXTIM_ABSOLUTE_LINE_TIME)) + +#define IS_GFXTIM_ABSOLUTE_LINE_COMPARATOR(PARAM) (((PARAM) == GFXTIM_ABSOLUTE_LINE_COMPARE1) || \ + ((PARAM) == GFXTIM_ABSOLUTE_LINE_COMPARE2)) + +#define IS_GFXTIM_RELATIVE_TIMER(PARAM) (((PARAM) == GFXTIM_RELATIVE_TIMER1) || \ + ((PARAM) == GFXTIM_RELATIVE_TIMER2)) + +#define IS_GFXTIM_RELATIVE_COUNTER_MODE(PARAM) (((PARAM) == GFXTIM_MODE_ONE_SHOT) || \ + ((PARAM) == GFXTIM_MODE_CONTINUOUS)) + +#define IS_GFXTIM_EVENT_LINE(PARAM) (((PARAM) == GFXTIM_LINE_EVENT_NONE) || \ + ((PARAM) == GFXTIM_LINE_EVENT_ALC_OVERFLOW) || \ + ((PARAM) == GFXTIM_LINE_EVENT_TE) || \ + ((PARAM) == GFXTIM_LINE_EVENT_ALC1_COMPARE) || \ + ((PARAM) == GFXTIM_LINE_EVENT_ALC2_COMPARE)) + +#define IS_GFXTIM_EVENT_FRAME(PARAM) (((PARAM) == GFXTIM_FRAME_EVENT_NONE) || \ + ((PARAM) == GFXTIM_FRAME_EVENT_AFC_OVERFLOW) || \ + ((PARAM) == GFXTIM_FRAME_EVENT_AFC_COMPARE) || \ + ((PARAM) == GFXTIM_FRAME_EVENT_RFC1_RELOAD) || \ + ((PARAM) == GFXTIM_FRAME_EVENT_RFC2_RELOAD)) + +#define IS_GFXTIM_EVENT_GENERATOR(PARAM) (((PARAM) == GFXTIM_EVENT_GENERATOR_1) || \ + ((PARAM) == GFXTIM_EVENT_GENERATOR_2) || \ + ((PARAM) == GFXTIM_EVENT_GENERATOR_3) || \ + ((PARAM) == GFXTIM_EVENT_GENERATOR_4)) + + +#define IS_GFXTIM_CLOCK_GENERATOR_COUNTER_FORCE_RELOAD(PARAM) (((PARAM) == GFXTIM_LINE_CLK_COUNTER) || \ + ((PARAM) == GFXTIM_FRAME_CLK_COUNTER) || \ + ((PARAM) == (GFXTIM_LINE_CLK_COUNTER | \ + GFXTIM_FRAME_CLK_COUNTER))) + + +#define IS_GFXTIM_WATCHDOG_HW_RELOAD_CONFIG(PARAM) (((PARAM) == GFXTIM_WATCHDOG_HW_RELOAD_DISABLE) || \ + ((PARAM) == GFXTIM_WATCHDOG_HW_RELOAD_RISING_EDGE) || \ + ((PARAM) == GFXTIM_WATCHDOG_HW_RELOAD_FALLING_EDGE)) + +#define IS_GFXTIM_WATCHDOG_CLOCK_SRC(PARAM) (((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_LINE_CLK) || \ + ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_FRAME_CLK) || \ + ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_HSYNC_RISING) || \ + ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_HSYNC_FALLING) || \ + ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_VSYNC_RISING) || \ + ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_VSYNC_FALLING) || \ + ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_TE_RISING) || \ + ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_TE_FALLING) || \ + ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_EVENT_1) || \ + ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_EVENT_2) || \ + ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_EVENT_3) || \ + ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_EVENT_4)) +#define IS_GFXTIM_WATCHDOG_VALUE(PARAM) ((PARAM) <= 65535U) +#define IS_GFXTIM_RELATIVE_FRAME_VALUE(PARAM) ((PARAM) <= 4095U) +#define IS_GFXTIM_ABSOLUTE_FRAME_VALUE(PARAM) ((PARAM) <= 1048575U) +#define IS_GFXTIM_ABSOLUTE_LINE_VALUE(PARAM) ((PARAM) <= 4095U) +#define IS_GFXTIM_LCC_RELOAD_VALUE(PARAM) ((PARAM) <= 4194303U) +#define IS_GFXTIM_FCC_RELOAD_VALUE(PARAM) ((PARAM) <= 4095U) + + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GFXTIM_Exported_Macros GFXTIM Exported Macros + * @{ + */ + +/** @brief Reset GFXTIM handle state. + * @param __HANDLE__ GFXTIM handle. + * @retval None + */ +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1) +#define __HAL_GFXTIM_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_GFXTIM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ +#define __HAL_GFXTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXTIM_STATE_RESET) +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + + + +/** + * @brief Check whether the specified GFXTIM flag is set or not. + * @param __HANDLE__ GFXTIM handle + * @param __FLAG__ GFXTIM flag + * This parameter can be one or a combination of the following values: + * @arg @ref GFXTIM_FLAG_AFCO Absolute Frame Counter Overflow Flag + * @arg @ref GFXTIM_FLAG_ALCO Absolute Line Counter Overflow Flag + * @arg @ref GFXTIM_FLAG_TE Tearing Effect Flag + * @arg @ref GFXTIM_FLAG_AFCC1 Absolute Frame Counter Compare 1 Flag + * @arg @ref GFXTIM_FLAG_ALCC1 Absolute Line Counter Compare 1 Flag + * @arg @ref GFXTIM_FLAG_ALCC2 Absolute Line Counter Compare 2 Flag + * @arg @ref GFXTIM_FLAG_RFC1R Relative Frame Counter 1 Reload Flag + * @arg @ref GFXTIM_FLAG_RFC2R Relative Frame Counter 2 Reload Flag + * @arg @ref GFXTIM_FLAG_EV1 Event 1 Flag + * @arg @ref GFXTIM_FLAG_EV2 Event 2 Flag + * @arg @ref GFXTIM_FLAG_EV3 Event 3 Flag + * @arg @ref GFXTIM_FLAG_EV4 Event 4 Flag + * @arg @ref GFXTIM_FLAG_WDGA Watchdog Alarm Flag + * @arg @ref GFXTIM_FLAG_WDGP Watchdog Pre-alarm Flag + * @retval State of flag (TRUE or FALSE). + */ +#define __HAL_GFXTIM_GET_FLAG(__HANDLE__, __FLAG__)\ + ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the specified GFXTIM flag. + * @param __HANDLE__ GFXTIM handle + * @param __FLAG__ GFXTIM flag + * This parameter can be one or a combination of the following values: + * @arg @ref GFXTIM_FLAG_AFCO Absolute Frame Counter Overflow Flag + * @arg @ref GFXTIM_FLAG_ALCO Absolute Line Counter Overflow Flag + * @arg @ref GFXTIM_FLAG_TE Tearing Effect Flag + * @arg @ref GFXTIM_FLAG_AFCC1 Absolute Frame Counter Compare 1 Flag + * @arg @ref GFXTIM_FLAG_ALCC1 Absolute Line Counter Compare 1 Flag + * @arg @ref GFXTIM_FLAG_ALCC2 Absolute Line Counter Compare 2 Flag + * @arg @ref GFXTIM_FLAG_RFC1R Relative Frame Counter 1 Reload Flag + * @arg @ref GFXTIM_FLAG_RFC2R Relative Frame Counter 2 Reload Flag + * @arg @ref GFXTIM_FLAG_EV1 Event 1 Flag + * @arg @ref GFXTIM_FLAG_EV2 Event 2 Flag + * @arg @ref GFXTIM_FLAG_EV3 Event 3 Flag + * @arg @ref GFXTIM_FLAG_EV4 Event 4 Flag + * @arg @ref GFXTIM_FLAG_WDGA Watchdog Alarm Flag + * @arg @ref GFXTIM_FLAG_WDGP Watchdog Pre-alarm Flag + * @retval None + */ +#define __HAL_GFXTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)\ + (((__HANDLE__)->Instance->ICR) = (__FLAG__)) + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GFXTIM_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/** @addtogroup GFXTIM_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_GFXTIM_Init(GFXTIM_HandleTypeDef *hgfxtim); +HAL_StatusTypeDef HAL_GFXTIM_DeInit(GFXTIM_HandleTypeDef *hgfxtim); +void HAL_GFXTIM_MspInit(GFXTIM_HandleTypeDef *hgfxtim); +void HAL_GFXTIM_MspDeInit(GFXTIM_HandleTypeDef *hgfxtim); +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_GFXTIM_RegisterCallback(GFXTIM_HandleTypeDef *hgfxtim, + HAL_GFXTIM_CallbackIDTypeDef CallbackID, + pGFXTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_GFXTIM_UnRegisterCallback(GFXTIM_HandleTypeDef *hgfxtim, + HAL_GFXTIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ +void HAL_GFXTIM_TECallback(GFXTIM_HandleTypeDef *hgfxtim); +/** + * @} + */ + +/* Clock Generator functions *****************************************************/ +/** @addtogroup GFXTIM_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_GFXTIM_ClockGenerator_Config(GFXTIM_HandleTypeDef *hgfxtim, + const GFXTIM_ClockGeneratorConfigTypeDef *pClockGeneratorConfig); +HAL_StatusTypeDef HAL_GFXTIM_ClockGenerator_Reload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t ClockGeneratorCounter); +/** + * @} + */ + +/* Absolute Timer functions *****************************************/ +/** @addtogroup GFXTIM_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Config(GFXTIM_HandleTypeDef *hgfxtim, + const GFXTIM_AbsoluteTimerConfigTypeDef *pAbsoluteTimerConfig); +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Start(GFXTIM_HandleTypeDef *hgfxtim); +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Stop(GFXTIM_HandleTypeDef *hgfxtim); +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Reset(GFXTIM_HandleTypeDef *hgfxtim); +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_GetCounter(const GFXTIM_HandleTypeDef *hgfxtim, uint32_t AbsoluteTime, + uint32_t *pValue); +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_SetFrameCompare(GFXTIM_HandleTypeDef *hgfxtim, uint32_t Value); +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_SetLineCompare(GFXTIM_HandleTypeDef *hgfxtim, + uint32_t AbsoluteLineComparator, + uint32_t Value); +void HAL_GFXTIM_AbsoluteTimer_AFCC1Callback(GFXTIM_HandleTypeDef *hgfxtim); +void HAL_GFXTIM_AbsoluteTimer_AFCOFCallback(GFXTIM_HandleTypeDef *hgfxtim); +void HAL_GFXTIM_AbsoluteTimer_ALCC1Callback(GFXTIM_HandleTypeDef *hgfxtim); +void HAL_GFXTIM_AbsoluteTimer_ALCC2Callback(GFXTIM_HandleTypeDef *hgfxtim); +void HAL_GFXTIM_AbsoluteTimer_ALCOFCallback(GFXTIM_HandleTypeDef *hgfxtim); +/** + * @} + */ + +/* Relative Timer functions *****************************************/ +/** @addtogroup GFXTIM_Exported_Functions_Group4 + * @{ + */ +HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Config(GFXTIM_HandleTypeDef *hgfxtim, + const GFXTIM_RelativeTimerConfigTypeDef *pRelativeTimerConfig, + uint32_t RelativeTimer); +HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Start(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer); +HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Stop(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer); +HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_ForceReload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer); +HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_SetReload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer, + uint32_t Value); +HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_GetCounter(const GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer, + uint32_t *pValue); +void HAL_GFXTIM_RelativeTimer_RFC1RCallback(GFXTIM_HandleTypeDef *hgfxtim); +void HAL_GFXTIM_RelativeTimer_RFC2RCallback(GFXTIM_HandleTypeDef *hgfxtim); +/** + * @} + */ + +/* Event Generator functions *****************************************/ +/** @addtogroup GFXTIM_Exported_Functions_Group5 + * @{ + */ +HAL_StatusTypeDef HAL_GFXTIM_EventGenerator_Config(GFXTIM_HandleTypeDef *hgfxtim, uint32_t EventGenerator, + const GFXTIM_EventGeneratorConfigTypeDef *pEventGeneratorConfig); +HAL_StatusTypeDef HAL_GFXTIM_EventGenerator_Enable(GFXTIM_HandleTypeDef *hgfxtim, uint32_t EventGenerator); +HAL_StatusTypeDef HAL_GFXTIM_EventGenerator_Disable(GFXTIM_HandleTypeDef *hgfxtim, uint32_t EventGenerator); +void HAL_GFXTIM_EventGenerator_EV1Callback(GFXTIM_HandleTypeDef *hgfxtim); +void HAL_GFXTIM_EventGenerator_EV2Callback(GFXTIM_HandleTypeDef *hgfxtim); +void HAL_GFXTIM_EventGenerator_EV3Callback(GFXTIM_HandleTypeDef *hgfxtim); +void HAL_GFXTIM_EventGenerator_EV4Callback(GFXTIM_HandleTypeDef *hgfxtim); +/** + * @} + */ + +/* Watchdog functions *****************************************/ +/** @addtogroup GFXTIM_Exported_Functions_Group6 + * @{ + */ +HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Config(GFXTIM_HandleTypeDef *hgfxtim, + const GFXTIM_WatchdogConfigTypeDef *pWatchdogConfig); +HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Enable(GFXTIM_HandleTypeDef *hgfxtim); +HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Disable(GFXTIM_HandleTypeDef *hgfxtim); +HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Refresh(GFXTIM_HandleTypeDef *hgfxtim); +void HAL_GFXTIM_WatchdogTimer_AlarmCallback(GFXTIM_HandleTypeDef *hgfxtim); +void HAL_GFXTIM_WatchdogTimer_PreAlarmCallback(GFXTIM_HandleTypeDef *hgfxtim); +/** + * @} + */ + +/* Generic functions *********************************************************/ +/** @addtogroup GFXTIM_Exported_Functions_Group7 + * @{ + */ +void HAL_GFXTIM_IRQHandler(GFXTIM_HandleTypeDef *hgfxtim); +void HAL_GFXTIM_ErrorCallback(GFXTIM_HandleTypeDef *hgfxtim); +uint32_t HAL_GFXTIM_GetError(const GFXTIM_HandleTypeDef *hgfxtim); +HAL_GFXTIM_StateTypeDef HAL_GFXTIM_GetState(const GFXTIM_HandleTypeDef *hgfxtim); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* GFXTIM */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_GFXTIM_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gpio.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gpio.h new file mode 100644 index 00000000000..67f0ed5628a --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gpio.h @@ -0,0 +1,326 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_GPIO_H +#define STM32H7RSxx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits + * @{ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u /*!< Very high speed */ +/** + * @} + */ + +/** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ +#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Check whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) + +/** + * @brief Generate a Software interrupt on selected EXTI line(s). + * @param __EXTI_LINE__ specifies the EXTI line to be set. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 = (__EXTI_LINE__)) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0u +#define GPIO_MODE (0x3uL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0uL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) +#define MODE_AF (0x2uL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4u +#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16u +#define EXTI_MODE (0x3uL << EXTI_MODE_Pos) +#define EXTI_IT (0x1uL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2uL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20u +#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos) +/** + * @} + */ + +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u)) + +#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ + (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Include GPIO HAL Extended module */ +#include "stm32h7rsxx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @brief GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_GPIO_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gpio_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gpio_ex.h new file mode 100644 index 00000000000..5095b5c5f8e --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gpio_ex.h @@ -0,0 +1,266 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_GPIO_EX_H +#define STM32H7RSxx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @brief GPIO Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ + +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ + +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_JTAG ((uint8_t)0x00) /*!< JTAG Alternate Function mapping */ +#define GPIO_AF0_SWD ((uint8_t)0x00) /*!< SWD Alternate Function mapping */ +#define GPIO_AF0_RTC ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */ +#define GPIO_AF0_PWR ((uint8_t)0x00) /*!< PWR Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_ADF1 ((uint8_t)0x01) /*!< ADF1 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_GFXTIM ((uint8_t)0x02) /*!< GFXTIM Alternate Function mapping */ +#define GPIO_AF2_SAI1 ((uint8_t)0x02) /*!< SAI1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /*!< TIM5 Alternate Function mapping */ +#define GPIO_AF2_TIM12 ((uint8_t)0x02) /*!< TIM12 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_ADF1 ((uint8_t)0x03) /*!< ADF1 Alternate Function mapping */ +#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /*!< LPTIM3 Alternate Function mapping */ +#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /*!< LPTIM4 Alternate Function mapping */ +#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /*!< LPTIM5 Alternate Function mapping */ +#define GPIO_AF3_LPUART1 ((uint8_t)0x03) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */ +#define GPIO_AF3_USART3 ((uint8_t)0x03) /*!< USART3 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_CEC ((uint8_t)0x04) /*!< CEC Alternate Function mapping */ +#define GPIO_AF4_DCMIPP ((uint8_t)0x04) /*!< DCMIPP Alternate Function mapping */ +#define GPIO_AF4_ETH ((uint8_t)0x04) /*!< ETH Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF4_I3C1 ((uint8_t)0x04) /*!< I3C1 Alternate Function mapping */ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_CEC ((uint8_t)0x05) /*!< CEC Alternate Function mapping */ +#define GPIO_AF5_DCMIPP ((uint8_t)0x05) /*!< DCMIPP Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /*!< SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /*!< SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /*!< SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /*!< SPI6/I2S6 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_PSSI ((uint8_t)0x06) /*!< PSSI Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /*!< SAI1 Alternate Function mapping */ +#define GPIO_AF6_SDMMC1 ((uint8_t)0x06) /*!< SDMMC1 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /*!< SPI4 Alternate Function mapping */ +#define GPIO_AF6_UART4 ((uint8_t)0x06) /*!< UART4 Alternate Function mapping */ +#define GPIO_AF6_UCPD ((uint8_t)0x06) /*!< UCPD Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_FMC ((uint8_t)0x07) /*!< FMC Alternate Function mapping */ +#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /*!< SDMMC1 Alternate Function mapping */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07) /*!< SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /*!< SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF7_SPI6 ((uint8_t)0x07) /*!< SPI6/I2S6 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF7_UART7 ((uint8_t)0x07) /*!< UART7 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_GFXTIM ((uint8_t)0x08) /*!< GFXTIM Alternate Function mapping */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF8_PSSI ((uint8_t)0x08) /*!< PSSI Alternate Function mapping */ +#define GPIO_AF8_SAI2 ((uint8_t)0x08) /*!< SAI2 Alternate Function mapping */ +#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /*!< SDMMC1 Alternate Function mapping */ +#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /*!< SPDIFRX Alternate Function mapping */ +#define GPIO_AF8_SPI6 ((uint8_t)0x08) /*!< SPI6/I2S6 Alternate Function mapping */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /*!< UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /*!< UART5 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /*!< UART8 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /*!< FDCAN1 Alternate Function mapping */ +#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /*!< FDCAN2 Alternate Function mapping */ +#define GPIO_AF9_FMC ((uint8_t)0x09) /*!< FMC Alternate Function mapping */ +#define GPIO_AF9_XSPIM_P1 ((uint8_t)0x09) /*!< XSPIM Manager Port 1 Alternate Function mapping */ +#define GPIO_AF9_XSPIM_P2 ((uint8_t)0x09) /*!< XSPIM Manager Port 2 Alternate Function mapping */ +#define GPIO_AF9_PSSI ((uint8_t)0x09) /*!< PSSI Alternate Function mapping */ +#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /*!< SDMMC2 Alternate Function mapping */ +#define GPIO_AF9_SPDIFRX ((uint8_t)0x09) /*!< SPDIFRX Alternate Function mapping */ +#define GPIO_AF9_SPI5 ((uint8_t)0x09) /*!< SPI5 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /*!< TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /*!< TIM14 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_CRS ((uint8_t)0x0A) /*!< CRS Alternate Function mapping */ +#define GPIO_AF10_FMC ((uint8_t)0x0A) /*!< FMC Alternate Function mapping */ +#define GPIO_AF10_LTDC ((uint8_t)0x0A) /*!< LTDC Alternate Function mapping */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /*!< OTG FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /*!< OTG HS Alternate Function mapping */ +#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /*!< SAI2 Alternate Function mapping */ +#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /*!< SDMMC2 Alternate Function mapping */ +#define GPIO_AF10_SPI1 ((uint8_t)0x0A) /*!< SPI1/I2S1 Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /*!< ETH Alternate Function mapping */ +#define GPIO_AF11_LTDC ((uint8_t)0x0B) /*!< LTDC Alternate Function mapping */ +#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /*!< MDIOS Alternate Function mapping */ +#define GPIO_AF11_SDMMC1 ((uint8_t)0x0B) /*!< SDMMC1 Alternate Function mapping */ +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /*!< SDMMC2 Alternate Function mapping */ +#define GPIO_AF11_UART7 ((uint8_t)0x0B) /*!< UART7 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /*!< FMC Alternate Function mapping */ +#define GPIO_AF12_GFXTIM ((uint8_t)0x0C) /*!< GFXTIM Alternate Function mapping */ +#define GPIO_AF12_LTDC ((uint8_t)0x0C) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /*!< SDMMC1 Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMIPP ((uint8_t)0x0D) /*!< DCMIPP Alternate Function mapping */ +#define GPIO_AF13_GFXTIM ((uint8_t)0x0D) /*!< GFXTIM Alternate Function mapping */ +#define GPIO_AF13_LTDC ((uint8_t)0x0D) /*!< TIM1 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_FMC ((uint8_t)0x0E) /*!< FMC Alternate Function mapping */ +#define GPIO_AF14_LTDC ((uint8_t)0x0E) /*!< LTDC Alternate Function mapping */ +#define GPIO_AF14_MDIOS ((uint8_t)0x0E) /*!< MDIOS Alternate Function mapping */ +#define GPIO_AF14_PSSI ((uint8_t)0x0E) /*!< PSSI Alternate Function mapping */ +#define GPIO_AF14_TIM1 ((uint8_t)0x0E) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF14_UART5 ((uint8_t)0x0E) /*!< UART5 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros + * @{ + */ + +/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index + * @{ + */ +#define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_GPIO_EX_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gpu2d.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gpu2d.h new file mode 100644 index 00000000000..3adc486da88 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_gpu2d.h @@ -0,0 +1,321 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_gpu2d.h + * @author MCD Application Team + * @brief Header file of GPU2D HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_GPU2D_H +#define STM32H7RSxx_HAL_GPU2D_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +#if defined (GPU2D) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup GPU2D GPU2D + * @brief GPU2D HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GPU2D_Exported_Types GPU2D Exported Types + * @{ + */ +/** + * @brief HAL GPU2D State enumeration definition + */ +typedef enum +{ + HAL_GPU2D_STATE_RESET = 0x00U, /*!< GPU2D not yet initialized or disabled */ + HAL_GPU2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_GPU2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_GPU2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_GPU2D_STATE_ERROR = 0x04U +} HAL_GPU2D_StateTypeDef; + +/** + * @brief GPU2D_TypeDef definition + */ +typedef uint32_t GPU2D_TypeDef; + +/** + * @brief GPU2D handle Structure definition + */ +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) +typedef struct __GPU2D_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ +{ + GPU2D_TypeDef Instance; /*!< GPU2D register base address. */ + + HAL_LockTypeDef Lock; /*!< GPU2D lock. */ + + __IO HAL_GPU2D_StateTypeDef State; /*!< GPU2D transfer state. */ + + __IO uint32_t ErrorCode; /*!< GPU2D error code. */ + +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) + void (* CommandListCpltCallback)(struct __GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID); /*!< GPU2D Command Complete Callback */ + + void (* MspInitCallback)(struct __GPU2D_HandleTypeDef *hgpu2d); /*!< GPU2D Msp Init callback */ + + void (* MspDeInitCallback)(struct __GPU2D_HandleTypeDef *hgpu2d); /*!< GPU2D Msp DeInit callback */ +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ +} GPU2D_HandleTypeDef; + +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) +/** + * @brief HAL GPU2D Callback ID enumeration definition + */ +typedef enum +{ + HAL_GPU2D_MSPINIT_CB_ID = 0x00U, /*!< GPU2D MspInit callback ID */ + HAL_GPU2D_MSPDEINIT_CB_ID = 0x01U, /*!< GPU2D MspDeInit callback ID */ +} HAL_GPU2D_CallbackIDTypeDef; + +/** @defgroup HAL_GPU2D_Callback_pointer_definition HAL GPU2D Callback pointer definition + * @brief HAL GPU2D Callback pointer definition + * @{ + */ +typedef void (*pGPU2D_CallbackTypeDef)(GPU2D_HandleTypeDef *hgpu2d); /*!< pointer to an GPU2D Callback function */ +typedef void (*pGPU2D_CommandListCpltCallbackTypeDef)(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdID); /*!< pointer to an GPU2D Command List Complete Callback function */ +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPU2D_Exported_Constants GPU2D Exported Constants + * @{ + */ + +/** @defgroup GPU2D_Error_Code_definition GPU2D Error Code definition + * @brief GPU2D Error Code definition + * @{ + */ +#define HAL_GPU2D_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_GPU2D_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) +#define HAL_GPU2D_ERROR_INVALID_CALLBACK (0x00000002U) /*!< Invalid callback error */ +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ +/** + * @} + */ + +/** @defgroup GPU2D_Interrupt_configuration_definition GPU2D Interrupt configuration definition + * @brief GPU2D Interrupt definition + * @{ + */ +#define GPU2D_IT_CLC 0x00000001U /*!< Command List Complete Interrupt */ +/** + * @} + */ + +/** @defgroup GPU2D_Flag_definition GPU2D Flag definition + * @brief GPU2D Flags definition + * @{ + */ +#define GPU2D_FLAG_CLC 0x00000001U /*!< Command List Complete Interrupt Flag */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup GPU2D_Exported_Macros GPU2D Exported Macros + * @{ + */ + +/** @brief Reset GPU2D handle state + * @param __HANDLE__: specifies the GPU2D handle. + * @retval None + */ +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) +#define __HAL_GPU2D_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_GPU2D_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->CommandListCpltCallback = NULL; \ + } while(0) +#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */ +#define __HAL_GPU2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GPU2D_STATE_RESET) +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + +/* Interrupt & Flag management */ +/** + * @brief Get the GPU2D pending flags. + * @param __HANDLE__: GPU2D handle + * @param __FLAG__: flag to check. + * This parameter can be one of the following values: + * @arg GPU2D_FLAG_CLC: Command List Complete interrupt mask + * @retval The state of FLAG. + */ +#define __HAL_GPU2D_GET_FLAG(__HANDLE__, __FLAG__) (READ_REG(*(__IO uint32_t *)((uint32_t)(__HANDLE__)->Instance\ + + GPU2D_ITCTRL)) & (__FLAG__)) + +/** + * @brief Clear the GPU2D pending flags. + * @param __HANDLE__: GPU2D handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg GPU2D_FLAG_CLC: Command List Complete interrupt mask + * @retval None + */ +#define __HAL_GPU2D_CLEAR_FLAG(__HANDLE__, __FLAG__) do { \ + __IO uint32_t *tmpreg = \ + (__IO uint32_t *)((uint32_t)(__HANDLE__)->Instance\ + + GPU2D_ITCTRL); \ + CLEAR_BIT(*tmpreg, __FLAG__); \ + } while(0U) + +/** + * @brief Check whether the specified GPU2D interrupt source is enabled or not. + * @param __HANDLE__: GPU2D handle + * @param __INTERRUPT__: specifies the GPU2D interrupt source to check. + * This parameter can be one of the following values: + * @arg GPU2D_IT_CLC: Command List Complete interrupt mask + * @retval The state of INTERRUPT source. + */ +#define __HAL_GPU2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_REG(*(__IO uint32_t *)\ + ((uint32_t)(__HANDLE__)->Instance\ + + GPU2D_ITCTRL)) & (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPU2D_Exported_Functions GPU2D Exported Functions + * @{ + */ + +/** @addtogroup GPU2D_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +HAL_StatusTypeDef HAL_GPU2D_Init(GPU2D_HandleTypeDef *hgpu2d); +HAL_StatusTypeDef HAL_GPU2D_DeInit(GPU2D_HandleTypeDef *hgpu2d); +void HAL_GPU2D_MspInit(GPU2D_HandleTypeDef *hgpu2d); +void HAL_GPU2D_MspDeInit(GPU2D_HandleTypeDef *hgpu2d); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_GPU2D_RegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID, + pGPU2D_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_GPU2D_UnRegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_GPU2D_RegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, + pGPU2D_CommandListCpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_GPU2D_UnRegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d); +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + +/** + * @} + */ + + +/** @addtogroup GPU2D_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *******************************************************/ +uint32_t HAL_GPU2D_ReadRegister(const GPU2D_HandleTypeDef *hgpu2d, uint32_t offset); +HAL_StatusTypeDef HAL_GPU2D_WriteRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset, uint32_t value); +void HAL_GPU2D_IRQHandler(GPU2D_HandleTypeDef *hgpu2d); +void HAL_GPU2D_ER_IRQHandler(GPU2D_HandleTypeDef *hgpu2d); +void HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID); +void HAL_GPU2D_ErrorCallback(GPU2D_HandleTypeDef *hgpu2d); + +/** + * @} + */ + +/** @addtogroup GPU2D_Exported_Functions_Group3 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State functions ***************************************************/ +HAL_GPU2D_StateTypeDef HAL_GPU2D_GetState(GPU2D_HandleTypeDef const *const hgpu2d); +uint32_t HAL_GPU2D_GetError(GPU2D_HandleTypeDef const *const hgpu2d); + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup GPU2D_Private_Constants GPU2D Private Constants + * @{ + */ + +#define GPU2D_ITCTRL (0x0F8U) /*!< GPU2D Interrupt Control Register Offset */ +#define GPU2D_CLID (0x148U) /*!< GPU2D Last Command List Identifier Register Offset */ +#define GPU2D_BREAKPOINT (0x080U) /*!< GPU2D Breakpoint Register Offset */ +#define GPU2D_SYS_INTERRUPT (0xff8U) /*!< GPU2D System Interrupt Register Offset */ + +/** @defgroup GPU2D_Offset GPU2D Last Register Offset + * @{ + */ +#define GPU2D_OFFSET 0x1000U /*!< Last GPU2D Register Offset */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPU2D_Private_Macros GPU2D Private Macros + * @{ + */ +#define IS_GPU2D_OFFSET(OFFSET) ((OFFSET) < GPU2D_OFFSET) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPU2D) */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_GPU2D_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_hash.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_hash.h new file mode 100644 index 00000000000..0ee8a98eae4 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_hash.h @@ -0,0 +1,579 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_hash.h + * @author MCD Application Team + * @brief Header file of HASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_HASH_H +#define STM32H7RSxx_HAL_HASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#if defined (HASH) +/** @defgroup HASH HASH + * @brief HASH HAL module driver. + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HASH_Exported_Types HASH Exported Types + * @{ + */ + +/** + * @brief HASH Configuration Structure definition + */ +typedef struct +{ + uint32_t DataType; /*!< no swap (32-bit data), half word swap (16-bit data), byte swap (8-bit data) or bit swap + (1-bit data). This parameter can be a value of @ref HASH_Data_Type. */ + + uint32_t KeySize; /*!< The key size is used only in HMAC operation. */ + + uint8_t *pKey; /*!< The key is used only in HMAC operation. */ + + uint32_t Algorithm; /*!< HASH algorithm MD5, SHA1 or SHA2. + This parameter can be a value of @ref HASH_Algorithm_Selection */ + + +} HASH_ConfigTypeDef; + +/** + * @brief HAL State structure definition + */ +typedef enum +{ + HAL_HASH_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ + HAL_HASH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_HASH_STATE_BUSY = 0x02U, /*!< Processing (hashing) is ongoing */ + HAL_HASH_STATE_SUSPENDED = 0x03U /*!< Suspended state */ +} HAL_HASH_StateTypeDef; + +/** + * @brief HAL phase structure definition + */ +typedef enum +{ + HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready to start */ + HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in HASH processing phase */ + HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, /*!< HASH peripheral is in HMAC step 1 processing phase + (step 1 consists in entering the inner hash function key)*/ + HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U, /*!< HASH peripheral is in HMAC step 2 processing phase + (step 2 consists in entering the message text) */ + HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase + (step 3 consists in entering the outer hash function key)*/ + +} HAL_HASH_PhaseTypeDef; + +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) +/** + * @brief HAL HASH mode suspend definitions + */ +typedef enum +{ + HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */ + HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */ +} HAL_HASH_SuspendTypeDef; +#endif /* USE_HAL_HASH_SUSPEND_RESUME */ + + +/** + * @brief HASH Handle Structure definition + */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +typedef struct __HASH_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ +{ + HASH_TypeDef *Instance; /*!< HASH Register base address */ + + HASH_ConfigTypeDef Init; /*!< HASH required parameters */ + + uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */ + + uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ + + __IO uint32_t HashInCount; /*!< Counter of inputted data */ + + uint32_t Size; /*!< Size of buffer to be processed in bytes */ + + uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ + + HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */ + + DMA_HandleTypeDef *hdmain; /*!< HASH In DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO uint32_t ErrorCode; /*!< HASH Error code */ + + __IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */ + + __IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */ + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */ + + void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation complete callback */ + + void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */ + + void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */ + + void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */ + +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) + __IO HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */ + + HASH_ConfigTypeDef Init_saved; /*!< Saved HASH required parameters */ + + uint8_t const *pHashInBuffPtr_saved; /*!< Saved pointer to input buffer */ + + uint8_t *pHashOutBuffPtr_saved; /*!< Saved pointer to output buffer (digest) */ + + __IO uint32_t HashInCount_saved; /*!< Saved counter of inputted data */ + + uint32_t Size_saved; /*!< Saved size of buffer to be processed */ + + uint8_t *pHashKeyBuffPtr_saved; /*!< Saved pointer to key buffer (HMAC only) */ + + HAL_HASH_PhaseTypeDef Phase_saved; /*!< Saved HASH peripheral phase */ +#endif /* USE_HAL_HASH_SUSPEND_RESUME */ + +} HASH_HandleTypeDef; + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL HASH common Callback ID enumeration definition + */ +typedef enum +{ + HAL_HASH_MSPINIT_CB_ID = 0x00U, /*!< HASH MspInit callback ID */ + HAL_HASH_MSPDEINIT_CB_ID = 0x01U, /*!< HASH MspDeInit callback ID */ + HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */ + HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */ + HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */ +} HAL_HASH_CallbackIDTypeDef; + +/** + * @brief HAL HASH Callback pointer definition + */ +typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */ + +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HASH_Exported_Constants HASH Exported Constants + * @{ + */ + +/** @defgroup HASH_Error_Definition HASH Error Definition + * @{ + */ +#define HAL_HASH_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_HASH_ERROR_BUSY 0x00000001U /*!< Busy flag error */ +#define HAL_HASH_ERROR_DMA 0x00000002U /*!< DMA-based process error */ +#define HAL_HASH_ERROR_TIMEOUT 0x00000004U /*!< Timeout error */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) +#define HAL_HASH_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid Callback error */ +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup HASH_Algorithm_Selection HASH algorithm selection + * @{ + */ +#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */ +#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */ +#define HASH_ALGOSELECTION_SHA256 (HASH_CR_ALGO_0 | HASH_CR_ALGO_1) /*!< HASH function is SHA256 */ +#define HASH_ALGOSELECTION_SHA384 (HASH_CR_ALGO_2 | HASH_CR_ALGO_3) /*!< HASH function is SHA384 */ +#define HASH_ALGOSELECTION_SHA512_224 (HASH_CR_ALGO_0 | HASH_CR_ALGO_2 | HASH_CR_ALGO_3) +/*!< HASH function is SHA512_224 */ +#define HASH_ALGOSELECTION_SHA512_256 (HASH_CR_ALGO_1 | HASH_CR_ALGO_2 | HASH_CR_ALGO_3) +/*!< HASH function is SHA512_256 */ +#define HASH_ALGOSELECTION_SHA512 HASH_CR_ALGO /*!< HASH function is SHA512 */ +/** + * @} + */ + +/** @defgroup HASH_Mode HASH Mode + * @{ + */ +#define HASH_ALGOMODE_HASH 0x00000000U /*!< HASH mode */ +#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< HMAC mode */ +/** + * @} + */ + +/** @defgroup HASH_Data_Type HASH Data Type + * @{ + */ +#define HASH_NO_SWAP 0x00000000U /*!< 32-bit data. No swapping */ +#define HASH_HALFWORD_SWAP HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ +#define HASH_BYTE_SWAP HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ +#define HASH_BIT_SWAP HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */ +/** + * @} + */ + +/** @defgroup HASH_HMAC_KEY key length only for HMAC mode + * @{ + */ +#define HASH_SHORTKEY 0x00000000U /*!< HMAC Key size is <= block size (64 or 128 bytes) */ +#define HASH_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > block size (64 or 128 bytes) */ +/** + * @} + */ + +/** @defgroup HASH_flags_definition HASH flags definitions + * @{ + */ +#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : new block can be entered + in the Peripheral */ +#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ +#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ +#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */ +#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : input buffer contains at least one word of data*/ +/** + * @} + */ + +/** @defgroup HASH_interrupts_definition HASH interrupts definitions + * @{ + */ +#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */ +#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup HASH_Exported_Macros HASH Exported Macros + * @{ + */ + +/** @brief Check whether or not the specified HASH flag is set. + * @param __HANDLE__ specifies the HASH handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. + * @arg @ref HASH_FLAG_DCIS Digest calculation complete. + * @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing. + * @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data. + * @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_HASH_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) > 8U) ? \ + (((__HANDLE__)->Instance->CR & (__FLAG__)) == (__FLAG__)) :\ + (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) ) + +/** @brief Clear the specified HASH flag. + * @param __HANDLE__ specifies the HASH handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. + * @arg @ref HASH_FLAG_DCIS Digest calculation complete + * @retval None + */ +#define __HAL_HASH_CLEAR_FLAG(__HANDLE__, __FLAG__) CLEAR_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) + +/** @brief Check whether the specified HASH interrupt source is enabled or not. + * @param __HANDLE__ specifies the HASH handle. + * @param __INTERRUPT__ HASH interrupt source to check + * This parameter can be one of the following values : + * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN) + * @arg @ref HASH_IT_DCI Digest calculation complete + * @retval State of interruption (TRUE or FALSE). + */ +#define __HAL_HASH_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Enable the specified HASH interrupt. + * @param __HANDLE__ specifies the HASH handle. + * @param __INTERRUPT__ specifies the HASH interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN) + * @arg @ref HASH_IT_DCI Digest calculation complete + * @retval None + */ +#define __HAL_HASH_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IMR, (__INTERRUPT__)) + +/** @brief Disable the specified HASH interrupt. + * @param __HANDLE__ specifies the HASH handle. + * @param __INTERRUPT__ specifies the HASH interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN) + * @arg @ref HASH_IT_DCI Digest calculation complete + * @retval None + */ +#define __HAL_HASH_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IMR, (__INTERRUPT__)) + +/** @brief Reset HASH handle state. + * @param __HANDLE__ HASH handle. + * @retval None + */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_HASH_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + }while(0) +#else +#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET) +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + +/** + * @brief Enable the multi-buffer DMA transfer mode. + * @note This bit is set when hashing large files when multiple DMA transfers are needed. + * @retval None + */ +#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT) + +/** + * @brief Disable the multi-buffer DMA transfer mode. + * @retval None + */ +#define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT) + +/** + * @brief HAL HASH driver version. + * @retval None + */ +#define HAL_HASH_VERSION 200 /*!< HAL HASH driver version 2.0.0*/ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HASH_Exported_Functions HASH Exported Functions + * @{ + */ + +/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash); +HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash); +void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash); +void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash); +HAL_StatusTypeDef HAL_HASH_GetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, + pHASH_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + +HAL_StatusTypeDef HAL_HASH_ProcessSuspend(HASH_HandleTypeDef *hhash); +void HAL_HASH_Resume(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); +void HAL_HASH_Suspend(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); +/** + * @} + */ + +/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions + * @{ + */ + +HAL_StatusTypeDef HAL_HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, + uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer); +HAL_StatusTypeDef HAL_HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer); + +HAL_StatusTypeDef HAL_HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, + uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer); +HAL_StatusTypeDef HAL_HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); + +/** + * @} + */ + +/** @addtogroup HASH_Exported_Functions_Group3 HMAC processing functions + * @{ + */ +HAL_StatusTypeDef HAL_HASH_HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, + uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer); +HAL_StatusTypeDef HAL_HASH_HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer); + +HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *const pOutBuffer); + +/** + * @} + */ + +/** @addtogroup HASH_Exported_Functions_Group4 HASH IRQ handler management + * @{ + */ +void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); +void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash); +void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash); +void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash); +HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash); +uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup HASH_Private_Macros HASH Private Macros + * @{ + */ + +/** + * @brief Return digest length in bytes. + * @retval Digest length + */ +#define HASH_DIGEST_LENGTH(__HANDLE__) (((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \ + == HASH_ALGOSELECTION_SHA1) ? 20U : \ + ((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \ + == HASH_ALGOSELECTION_SHA224) ? 28U : \ + ((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \ + == HASH_ALGOSELECTION_SHA256) ? 32U : \ + ((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \ + == HASH_ALGOSELECTION_SHA384) ? 48U : \ + ((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \ + == HASH_ALGOSELECTION_SHA512_224) ? 28U : \ + ((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \ + == HASH_ALGOSELECTION_SHA512_256) ? 32U : \ + ((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \ + == HASH_ALGOSELECTION_SHA512) ? 64U : 20U ) ) )))))) + +/** + * @brief Ensure that HASH input data type is valid. + * @param __DATATYPE__ HASH input data type. + * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid) + */ +#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_NO_SWAP)|| \ + ((__DATATYPE__) == HASH_HALFWORD_SWAP)|| \ + ((__DATATYPE__) == HASH_BYTE_SWAP) || \ + ((__DATATYPE__) == HASH_BIT_SWAP)) + +/** + * @brief Ensure that HASH input algorithm is valid. + * @param __ALGORITHM__ HASH algorithm. + * @retval SET (__ALGORITHM__ is valid) or RESET (__ALGORITHM__ is invalid) + */ +#define IS_HASH_ALGORITHM(__ALGORITHM__) (((__ALGORITHM__) == HASH_ALGOSELECTION_SHA1)|| \ + ((__ALGORITHM__) == HASH_ALGOSELECTION_SHA224)|| \ + ((__ALGORITHM__) == HASH_ALGOSELECTION_SHA256)|| \ + ((__ALGORITHM__) == HASH_ALGOSELECTION_SHA384)|| \ + ((__ALGORITHM__) == HASH_ALGOSELECTION_SHA512_224)|| \ + ((__ALGORITHM__) == HASH_ALGOSELECTION_SHA512_256)|| \ + ((__ALGORITHM__) == HASH_ALGOSELECTION_SHA512)) + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup HASH_Private_Constants HASH Private Constants + * @{ + */ + +/** + * @} + */ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup HASH_Private_Defines HASH Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup HASH_Private_Variables HASH Private Variables + * @{ + */ + +/** + * @} + */ +/* Private functions -----------------------------------------------------------*/ + +/** @addtogroup HASH_Private_Functions HASH Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* HASH*/ +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7RSxx_HAL_HASH_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_hcd.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_hcd.h new file mode 100644 index 00000000000..1fb1a1d18f3 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_hcd.h @@ -0,0 +1,327 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_hcd.h + * @author MCD Application Team + * @brief Header file of HCD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_HCD_H +#define STM32H7RSxx_HAL_HCD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_usb.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup HCD HCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HCD_Exported_Types HCD Exported Types + * @{ + */ + +/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition + * @{ + */ +typedef enum +{ + HAL_HCD_STATE_RESET = 0x00, + HAL_HCD_STATE_READY = 0x01, + HAL_HCD_STATE_ERROR = 0x02, + HAL_HCD_STATE_BUSY = 0x03, + HAL_HCD_STATE_TIMEOUT = 0x04 +} HCD_StateTypeDef; + +typedef USB_OTG_GlobalTypeDef HCD_TypeDef; +typedef USB_OTG_CfgTypeDef HCD_InitTypeDef; +typedef USB_OTG_HCTypeDef HCD_HCTypeDef; +typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef; +typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef; +/** + * @} + */ + +/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition + * @{ + */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +typedef struct __HCD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +{ + HCD_TypeDef *Instance; /*!< Register base address */ + HCD_InitTypeDef Init; /*!< HCD required parameters */ + HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ + HAL_LockTypeDef Lock; /*!< HCD peripheral status */ + __IO HCD_StateTypeDef State; /*!< HCD communication state */ + __IO uint32_t ErrorCode; /*!< HCD Error code */ + void *pData; /*!< Pointer Stack Handler */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */ + void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */ + void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */ + void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */ + void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */ + void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum, + HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */ + + void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */ + void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */ +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +} HCD_HandleTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HCD_Exported_Constants HCD Exported Constants + * @{ + */ + +/** @defgroup HCD_Speed HCD Speed + * @{ + */ +#define HCD_SPEED_HIGH USBH_HS_SPEED +#define HCD_SPEED_FULL USBH_FSLS_SPEED +#define HCD_SPEED_LOW USBH_FSLS_SPEED +/** + * @} + */ + +/** @defgroup HCD_Device_Speed HCD Device Speed + * @{ + */ +#define HCD_DEVICE_SPEED_HIGH 0U +#define HCD_DEVICE_SPEED_FULL 1U +#define HCD_DEVICE_SPEED_LOW 2U +/** + * @} + */ + +/** @defgroup HCD_PHY_Module HCD PHY Module + * @{ + */ +#define HCD_PHY_ULPI 1U +#define HCD_PHY_EMBEDDED 2U +/** + * @} + */ + +/** @defgroup HCD_Error_Code_definition HCD Error Code definition + * @brief HCD Error Code definition + * @{ + */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HCD_Exported_Macros HCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + +#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) + +#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \ + ((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__)) + +#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) +#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) + +#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) +#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT) +#define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT) +#define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HCD_Exported_Functions HCD Exported Functions + * @{ + */ + +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, + uint8_t speed, uint8_t ep_type, uint16_t mps); + +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); +void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition + * @brief HAL USB OTG HCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */ + HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */ + HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */ + HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */ + HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */ + + HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */ + HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */ + +} HAL_HCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition + * @brief HAL USB OTG HCD Callback pointer definition + * @{ + */ + +typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */ +typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd, + uint8_t epnum, + HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */ +/** + * @} + */ + +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t direction, uint8_t ep_type, + uint8_t token, uint8_t *pbuff, + uint16_t length, uint8_t do_ping); + +HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr); + +HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num); + +/* Non-Blocking mode: Interrupt */ +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); +void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, + HCD_URBStateTypeDef urb_state); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd); +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum); +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum); +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum); +uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); +uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup HCD_Private_Macros HCD Private Macros + * @{ + */ +/** + * @} + */ +/* Private functions prototypes ----------------------------------------------*/ + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_HCD_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2c.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2c.h new file mode 100644 index 00000000000..3c4d4b0702f --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2c.h @@ -0,0 +1,842 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_I2C_H +#define STM32H7RSxx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization section + in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 Peripheral initialization status\n + * 0 : Reset (peripheral not initialized)\n + * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (peripheral in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (peripheral busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ + + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< I2C transfer IRQ handler function pointer */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + +#endif /*HAL_DMA_MODULE_ENABLED*/ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); +/*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x000000AAU) +#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks + * @{ + */ +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode + * @{ + */ +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode + * @{ + */ +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define I2C_FLAG_MASK (0x0001FFFFU) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32h7rsxx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +#if defined(HAL_DMA_MODULE_ENABLED) +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +#endif /*HAL_DMA_MODULE_ENABLED*/ +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ + >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ + >> 16U)) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_ADD10) | (I2C_CR2_START) | \ + (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32h7rsxx_hal_i2c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7RSxx_HAL_I2C_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2c_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2c_ex.h new file mode 100644 index 00000000000..ca69f5a4c21 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2c_ex.h @@ -0,0 +1,156 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_I2C_EX_H +#define STM32H7RSxx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#define I2C_FASTMODEPLUS_ENABLE 0x00000000U /*!< Enable Fast Mode Plus */ +#define I2C_FASTMODEPLUS_DISABLE 0x00000001U /*!< Disable Fast Mode Plus */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_I2C_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (I2C_FASTMODEPLUS_ENABLE)) || \ + ((__CONFIG__) == (I2C_FASTMODEPLUS_DISABLE))) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32h7rsxx_hal_i2c_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_I2C_EX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2s.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2s.h new file mode 100644 index 00000000000..42d77d49d0d --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2s.h @@ -0,0 +1,663 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_i2s.h + * @author MCD Application Team + * @brief Header file of I2S HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_I2S_H +#define STM32H7RSxx_HAL_I2S_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Types I2S Exported Types + * @{ + */ + +/** + * @brief I2S Init structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref I2S_MSB_LSB_Transmission */ + + uint32_t WSInversion; /*!< Control the Word Select Inversion. + This parameter can be a value of @ref I2S_WSInversion */ + + uint32_t Data24BitAlignment; /*!< Specifies the Data Padding for 24 bits data length + This parameter can be a value of @ref I2S_Data_24Bit_Alignment */ + + uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state + This parameter can be a value of @ref I2S_Master_Keep_IO_State */ + +} I2S_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_I2S_STATE_RESET = 0x00UL, /*!< I2S not yet initialized or disabled */ + HAL_I2S_STATE_READY = 0x01UL, /*!< I2S initialized and ready for use */ + HAL_I2S_STATE_BUSY = 0x02UL, /*!< I2S internal process is ongoing */ + HAL_I2S_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */ + HAL_I2S_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */ + HAL_I2S_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */ + HAL_I2S_STATE_TIMEOUT = 0x06UL, /*!< I2S timeout state */ + HAL_I2S_STATE_ERROR = 0x07UL /*!< I2S error state */ +} HAL_I2S_StateTypeDef; + +/** + * @brief I2S handle Structure definition + */ +typedef struct __I2S_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< I2S registers base address */ + + I2S_InitTypeDef Init; /*!< I2S communication parameters */ + + const uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */ + + __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */ + + __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */ + + uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */ + + __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */ + + __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter + (This field is initialized at the + same value as transfer size at the + beginning of the transfer and + decremented when a sample is received + NbSamplesReceived = RxBufferSize-RxBufferCount) */ + + void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */ + + DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */ + + __IO HAL_LockTypeDef Lock; /*!< I2S locking object */ + + __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */ + + __IO uint32_t ErrorCode; /*!< I2S Error code + This parameter can be a value of @ref I2S_Error */ + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */ + void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */ + void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Completed callback */ + void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */ + void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Half Completed callback */ + void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */ + void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */ + void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */ + +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} I2S_HandleTypeDef; + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) +/** + + * @brief HAL I2S Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2S_TX_COMPLETE_CB_ID = 0x00UL, /*!< I2S Tx Completed callback ID */ + HAL_I2S_RX_COMPLETE_CB_ID = 0x01UL, /*!< I2S Rx Completed callback ID */ + HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< I2S TxRx Completed callback ID */ + HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< I2S Tx Half Completed callback ID */ + HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< I2S Rx Half Completed callback ID */ + HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< I2S TxRx Half Completed callback ID */ + HAL_I2S_ERROR_CB_ID = 0x06UL, /*!< I2S Error callback ID */ + HAL_I2S_MSPINIT_CB_ID = 0x07UL, /*!< I2S Msp Init callback ID */ + HAL_I2S_MSPDEINIT_CB_ID = 0x08UL /*!< I2S Msp DeInit callback ID */ + +} HAL_I2S_CallbackIDTypeDef; + +/** + * @brief HAL I2S Callback pointer definition + */ +typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */ + +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_Exported_Constants I2S Exported Constants + * @{ + */ +/** @defgroup I2S_Error I2S Error + * @{ + */ +#define HAL_I2S_ERROR_NONE (0x00000000UL) /*!< No error */ +#define HAL_I2S_ERROR_TIMEOUT (0x00000001UL) /*!< Timeout error */ +#define HAL_I2S_ERROR_OVR (0x00000002UL) /*!< OVR error */ +#define HAL_I2S_ERROR_UDR (0x00000004UL) /*!< UDR error */ +#define HAL_I2S_ERROR_DMA (0x00000008UL) /*!< DMA transfer error */ +#define HAL_I2S_ERROR_PRESCALER (0x00000010UL) /*!< Prescaler Calculation error */ +#define HAL_I2S_ERROR_FRE (0x00000020UL) /*!< FRE error */ +#define HAL_I2S_ERROR_NO_OGT (0x00000040UL) /*!< No On Going Transfer error */ +#define HAL_I2S_ERROR_NOT_SUPPORTED (0x00000080UL) /*!< Requested operation not supported */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) +#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000100UL) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup I2S_Mode I2S Mode + * @{ + */ +#define I2S_MODE_SLAVE_TX (0x00000000UL) +#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) +#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) +#define I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) +#define I2S_MODE_SLAVE_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2) +#define I2S_MODE_MASTER_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0) +/** + * @} + */ + +/** @defgroup I2S_Standard I2S Standard + * @{ + */ +#define I2S_STANDARD_PHILIPS (0x00000000UL) +#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) +#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) +#define I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) +#define I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) +/** + * @} + */ + +/** @defgroup I2S_Data_Format I2S Data Format + * @{ + */ +#define I2S_DATAFORMAT_16B (0x00000000UL) +#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) +#define I2S_DATAFORMAT_24B (SPI_I2SCFGR_DATLEN_0) +#define I2S_DATAFORMAT_32B (SPI_I2SCFGR_DATLEN_1) +/** + * @} + */ + +/** @defgroup I2S_MCLK_Output I2S MCLK Output + * @{ + */ +#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SCFGR_MCKOE) +#define I2S_MCLKOUTPUT_DISABLE (0x00000000UL) +/** + * @} + */ + +/** @defgroup I2S_Audio_Frequency I2S Audio Frequency + * @{ + */ +#define I2S_AUDIOFREQ_192K (192000UL) +#define I2S_AUDIOFREQ_96K (96000UL) +#define I2S_AUDIOFREQ_48K (48000UL) +#define I2S_AUDIOFREQ_44K (44100UL) +#define I2S_AUDIOFREQ_32K (32000UL) +#define I2S_AUDIOFREQ_22K (22050UL) +#define I2S_AUDIOFREQ_16K (16000UL) +#define I2S_AUDIOFREQ_11K (11025UL) +#define I2S_AUDIOFREQ_8K (8000UL) +#define I2S_AUDIOFREQ_DEFAULT (2UL) +/** + * @} + */ + +/** @defgroup I2S_Clock_Polarity I2S FullDuplex Mode + * @{ + */ +#define I2S_CPOL_LOW (0x00000000UL) +#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL) +/** + * @} + */ + +/** @defgroup I2S_MSB_LSB_Transmission I2S MSB LSB Transmission + * @{ + */ +#define I2S_FIRSTBIT_MSB (0x00000000UL) +#define I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST +/** + * @} + */ + +/** @defgroup I2S_WSInversion I2S Word Select Inversion + * @{ + */ +#define I2S_WS_INVERSION_DISABLE (0x00000000UL) +#define I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV +/** + * @} + */ + +/** @defgroup I2S_Data_24Bit_Alignment Data Padding 24Bit + * @{ + */ +#define I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000UL) +#define I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT +/** + * @} + */ + +/** @defgroup I2S_Master_Keep_IO_State Keep IO State + * @{ + */ +#define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U) +#define I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR +/** + * @} + */ + +/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition + * @{ + */ +#define I2S_IT_RXP SPI_IER_RXPIE +#define I2S_IT_TXP SPI_IER_TXPIE +#define I2S_IT_DXP SPI_IER_DXPIE +#define I2S_IT_UDR SPI_IER_UDRIE +#define I2S_IT_OVR SPI_IER_OVRIE +#define I2S_IT_FRE SPI_IER_TIFREIE +#define I2S_IT_ERR (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE) +/** + * @} + */ + +/** @defgroup I2S_Flags_Definition I2S Flags Definition + * @{ + */ +#define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */ +#define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */ +#define I2S_FLAG_DXP SPI_SR_DXP /* I2S status flag : Dx-Packet space available flag */ +#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */ +#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */ +#define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */ + +#define I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_DXP |SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup I2S_Exported_macros I2S Exported Macros + * @{ + */ + +/** @brief Reset I2S handle state + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) +#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2S_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SPI peripheral (in I2S mode). + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)) + +/** @brief Disable the specified SPI peripheral (in I2S mode). + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)) + +/** @brief Enable the specified I2S interrupts. + * @param __HANDLE__ specifies the I2S Handle. + * This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2S_IT_RXP : Rx-Packet available interrupt + * @arg I2S_IT_TXP : Tx-Packet space available interrupt + * @arg I2S_IT_UDR : Underrun interrupt + * @arg I2S_IT_OVR : Overrun interrupt + * @arg I2S_IT_FRE : TI mode frame format error interrupt + * @arg I2S_IT_ERR : Error interrupt enable + * @retval None + */ +#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** @brief Disable the specified I2S interrupts. + * @param __HANDLE__ specifies the I2S Handle. + * This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2S_IT_RXP : Rx-Packet available interrupt + * @arg I2S_IT_TXP : Tx-Packet space available interrupt + * @arg I2S_IT_UDR : Underrun interrupt + * @arg I2S_IT_OVR : Overrun interrupt + * @arg I2S_IT_FRE : TI mode frame format error interrupt + * @arg I2S_IT_ERR : Error interrupt enable + * @retval None + */ +#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) + +/** @brief Check if the specified I2S interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the I2S Handle. + * This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral. + * @param __INTERRUPT__ specifies the I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg I2S_IT_RXP : Rx-Packet available interrupt + * @arg I2S_IT_TXP : Tx-Packet space available interrupt + * @arg I2S_IT_DXP : Tx-Packet space available interrupt + * @arg I2S_IT_UDR : Underrun interrupt + * @arg I2S_IT_OVR : Overrun interrupt + * @arg I2S_IT_FRE : TI mode frame format error interrupt + * @arg I2S_IT_ERR : Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2S flag is set or not. + * @param __HANDLE__ specifies the I2S Handle. + * This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_RXP : Rx-Packet available flag + * @arg I2S_FLAG_TXP : Tx-Packet space available flag + * @arg I2S_FLAG_UDR : Underrun flag + * @arg I2S_FLAG_OVR : Overrun flag + * @arg I2S_FLAG_FRE : TI mode frame format error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the I2S OVR pending flag. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC) + +/** @brief Clear the I2S UDR pending flag. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC) + +/** @brief Clear the I2S FRE pending flag. + * @param __HANDLE__: specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_CLEAR_TIFREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2S_Exported_Functions + * @{ + */ + +/** @addtogroup I2S_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s); +void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); +void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) +HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, + pI2S_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData, + uint16_t Size, uint32_t Timeout); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData, + uint16_t Size); + +void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData, + uint16_t Size); + +HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); + +/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ +void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); +/** + * @} + */ + +/** @addtogroup I2S_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control and State functions ************************************/ +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2S_Private_Constants I2S Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2S_Private_Functions I2S Private Functions + * @{ + */ +/* Private functions are defined in stm32h7xx_hal_i2S.c file */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2S_Private_Macros I2S Private Macros + * @{ + */ + +/** @brief Check whether the specified SPI flag is set or not. + * @param __SR__ copy of I2S SR register. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2S_FLAG_RXP : Rx-Packet available flag + * @arg I2S_FLAG_TXP : Tx-Packet space available flag + * @arg I2S_FLAG_UDR : Underrun flag + * @arg I2S_FLAG_OVR : Overrun flag + * @arg I2S_FLAG_FRE : TI mode frame format error flag + * @retval SET or RESET. + */ +#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\ + & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK))\ + ? SET : RESET) + +/** @brief Check whether the specified SPI Interrupt is set or not. + * @param __IER__ copy of I2S IER register. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg I2S_IT_RXP : Rx-Packet available interrupt + * @arg I2S_IT_TXP : Tx-Packet space available interrupt + * @arg I2S_IT_UDR : Underrun interrupt + * @arg I2S_IT_OVR : Overrun interrupt + * @arg I2S_IT_FRE : TI mode frame format error interrupt + * @arg I2S_IT_ERR : Error interrupt enable + * @retval SET or RESET. + */ +#define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__) ((((__IER__)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks if I2S Mode parameter is in allowed range. + * @param __MODE__ specifies the I2S Mode. + * This parameter can be a value of @ref I2S_Mode + * @retval None + */ +#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ + ((__MODE__) == I2S_MODE_SLAVE_RX) || \ + ((__MODE__) == I2S_MODE_MASTER_TX) || \ + ((__MODE__) == I2S_MODE_MASTER_RX) || \ + ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX) || \ + ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX)) + +#define IS_I2S_MASTER(__MODE__) (((__MODE__) == I2S_MODE_MASTER_TX) || \ + ((__MODE__) == I2S_MODE_MASTER_RX) || \ + ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX)) + +#define IS_I2S_SLAVE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ + ((__MODE__) == I2S_MODE_SLAVE_RX) || \ + ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX)) + +#define IS_I2S_FULLDUPLEX(__MODE__) (((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX) || \ + ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX)) + +#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ + ((__STANDARD__) == I2S_STANDARD_MSB) || \ + ((__STANDARD__) == I2S_STANDARD_LSB) || \ + ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ + ((__STANDARD__) == I2S_STANDARD_PCM_LONG)) + +#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \ + ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \ + ((__FORMAT__) == I2S_DATAFORMAT_24B) || \ + ((__FORMAT__) == I2S_DATAFORMAT_32B)) + +#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \ + ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE)) + +#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \ + ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \ + ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) + +#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ + ((__CPOL__) == I2S_CPOL_HIGH)) + +#define IS_I2S_FIRST_BIT(__BIT__) (((__BIT__) == I2S_FIRSTBIT_MSB) || \ + ((__BIT__) == I2S_FIRSTBIT_LSB)) + +#define IS_I2S_WS_INVERSION(__WSINV__) (((__WSINV__) == I2S_WS_INVERSION_DISABLE) || \ + ((__WSINV__) == I2S_WS_INVERSION_ENABLE)) + +#define IS_I2S_DATA_24BIT_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \ + ((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_LEFT)) + +#define IS_I2S_MASTER_KEEP_IO_STATE(__AFCNTR__) (((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_DISABLE) || \ + ((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_ENABLE)) + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_I2S_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2s_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2s_ex.h new file mode 100644 index 00000000000..ff4eb9bfd18 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i2s_ex.h @@ -0,0 +1,26 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_i2s_ex.h + * @author MCD Application Team + * @brief Header file of I2S HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** + ****************************************************************************** + ===== I2S FULL DUPLEX FEATURE ===== + I2S Full Duplex APIs are available in stm32h7rsxx_hal_i2s.c/.h + ****************************************************************************** + */ + + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i3c.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i3c.h new file mode 100644 index 00000000000..5c107544d81 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_i3c.h @@ -0,0 +1,1371 @@ +/** + ********************************************************************************************************************** + * @file stm32h7rsxx_hal_i3c.h + * @author MCD Application Team + * @brief Header file of I3C HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32H7RSxx_HAL_I3C_H +#define STM32H7RSxx_HAL_I3C_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" +#include "stm32h7rsxx_ll_i3c.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup I3C + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_Exported_Types I3C Exported Types + * @{ + */ +/** @defgroup I3C_Init_Structure_definition I3C Init Structure definition + * @brief I3C Init Structure definition + * @{ + */ +typedef struct +{ + LL_I3C_CtrlBusConfTypeDef CtrlBusCharacteristic; /*!< Specifies the I3C controller bus characteristic configuration + when Controller mode */ + + LL_I3C_TgtBusConfTypeDef TgtBusCharacteristic; /*!< Specifies the I3C target bus characteristic configuration + when Target mode */ + +} I3C_InitTypeDef; +/** + * @} + */ + +/** @defgroup I3C_FIFO_Config_Structure_definition I3C FIFO Configuration Structure definition + * @brief I3C FIFO configuration structure definition + * @{ + */ +typedef struct +{ + uint32_t RxFifoThreshold; /*!< Specifies the I3C Rx FIFO threshold level. + This parameter must be a value of @ref I3C_RX_FIFO_THRESHOLD */ + + uint32_t TxFifoThreshold; /*!< Specifies the I3C Tx FIFO threshold level. + This parameter must be a value of @ref I3C_TX_FIFO_THRESHOLD */ + + uint32_t ControlFifo; /*!< Specifies the I3C control FIFO enable/disable state. + This parameter is configured only with controller mode and it + must be a value of @ref I3C_CONTROL_FIFO_STATE */ + + uint32_t StatusFifo; /*!< Specifies the I3C status FIFO enable/disable state. + This parameter is configured only with controller mode and it + must be a value of @ref I3C_STATUS_FIFO_STATE */ +} I3C_FifoConfTypeDef; +/** + * @} + */ + +/** @defgroup I3C_Controller_Config_Structure_definition I3C Controller Configuration Structure definition + * @brief I3C controller configuration structure definition + * @{ + */ +typedef struct +{ + uint8_t DynamicAddr; /*!< Specifies the dynamic address of the controller when goes in target mode. + This parameter must be a number between Min_Data=0x00 and Max_Data=0x7F */ + + uint8_t StallTime; /*!< Specifies the controller clock stall time in number of kernel clock cycles. + This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF */ + + FunctionalState HotJoinAllowed; /*!< Specifies the Enable/Disable state of the controller Hot Join acknowledgement + when receiving a hot join request from target. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ACKStallState; /*!< Specifies the Enable/Disable state of the controller clock stall + on the ACK phase. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState CCCStallState; /*!< Specifies the Enable/Disable state of the controller clock stall on the + T bit phase of a CCC communication to allow the target to decode command. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState TxStallState; /*!< Specifies the Enable/Disable state of the controller clock stall on + parity phase of data to allow the target to read received data. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState RxStallState; /*!< Specifies the Enable/Disable state of the controller clock stall on the T bit + phase of data enable to allow the target to prepare data to be sent. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState HighKeeperSDA; /*!< Specifies the Enable/Disable state of the controller SDA high keeper. + This parameter can be set to ENABLE or DISABLE */ +} I3C_CtrlConfTypeDef; +/** + * @} + */ + +/** @defgroup I3C_Target_Config_Structure_definition I3C Target Configuration Structure definition + * @brief I3C target configuration structure definition + * @{ + */ +typedef struct +{ + uint8_t Identifier; /*!< Specifies the target characteristic ID (MIPI named reference DCR). + This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF */ + + uint8_t MIPIIdentifier; /*!< Specifies the bits [12-15] of the 48-provisioned ID + (MIPI named reference PID), other 48-provisioned ID are hardcoded. + This parameter must be a number between Min_Data=0x00 and Max_Data=0x0F */ + + FunctionalState CtrlRoleRequest; /*!< Specifies the Enable/Disable state of the target authorization request + for a second master Chip. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState HotJoinRequest; /*!< Specifies the Enable/Disable state of the target hot join + authorization request. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState IBIRequest; /*!< Specifies the Enable/Disable state of the target in Band Interrupt + authorization request. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState IBIPayload; /*!< Specifies the Enable/Disable state of sending data payload after + an accepted IBI. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t IBIPayloadSize; /*!< Specifies the I3C target payload data size. + This parameter must be a value of @ref I3C_PAYLOAD_SIZE */ + + uint16_t MaxReadDataSize; /*!< Specifies the numbers of data bytes that the target can read at maximum. + This parameter must be a number between Min_Data=0x00 and Max_Data=0xFFFF */ + + uint16_t MaxWriteDataSize; /*!< Specifies the numbers of data bytes that the target can write at maximum. + This parameter must be a number between Min_Data=0x00 and Max_Data=0xFFFF */ + + FunctionalState CtrlCapability; /*!< Specifies the Enable/Disable state of the target controller capability. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState GroupAddrCapability; /*!< Specifies the Enable/Disable state of the target support of group address + after a controller role hand-off. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t DataTurnAroundDuration; /*!< Specifies the I3C target clock-to-data turnaround time. + This parameter must be a value of @ref I3C_TURNAROUND_TIME_TSCO */ + + uint8_t MaxReadTurnAround; /*!< Specifies the target maximum read turnaround byte. + This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF */ + + uint32_t MaxDataSpeed; /*!< Specifies the I3C target returned GETMXDS CCC format. + This parameter must be a value of @ref I3C_GETMXDS_FORMAT */ + + FunctionalState MaxSpeedLimitation; /*!< Specifies the Enable/Disable state of the target max data speed limitation. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t HandOffActivityState; /*!< Specifies the I3C target activity state when becoming controller. + This parameter must be a value of @ref I3C_HANDOFF_ACTIVITY_STATE */ + + FunctionalState HandOffDelay; /*!< Specifies the Enable/Disable state of the target need of delay to process + the controller role hand-off. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState PendingReadMDB; /*!< Specifies the Enable/Disable state of the transmission of a mandatory + data bytes indicating a pending read notification for GETCAPR CCC command. + This parameter can be set to ENABLE or DISABLE */ +} I3C_TgtConfTypeDef; +/** + * @} + */ + +/** @defgroup I3C_Device_Config_Structure_definition I3C Device Configuration Structure definition + * @brief I3C device configuration structure definition + * @{ + */ +typedef struct +{ + uint8_t DeviceIndex; /*!< Specifies the index value of the device in the DEVRx register. + This parameter must be a number between Min_Data=1 and Max_Data=4 */ + + uint8_t TargetDynamicAddr; /*!< Specifies the dynamic address of the target x (1 to 4) connected on the bus. + This parameter must be a number between Min_Data=0x00 and Max_Data=0x7F */ + + FunctionalState IBIAck; /*!< Specifies the Enable/Disable state of the controller's ACK when receiving + an IBI from a target x (1 to 4) connected on the bus. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState IBIPayload; /*!< Specifies the Enable/Disable state of the controller's receiving IBI payload + after acknowledging an IBI requested from a target x (1 to 4) connected + on the bus. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState CtrlRoleReqAck; /*!< Specifies the Enable/Disable state of the controller's ACK when receiving + a control request from a target x (1 to 4) connected on the bus. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState CtrlStopTransfer; /*!< Specifies the Enable/Disable state of the controller's stop transfer after + receiving an IBI request from a target x (1 to 4) connected on the bus. + This parameter can be set to ENABLE or DISABLE */ + +} I3C_DeviceConfTypeDef; +/** + * @} + */ + +/** @defgroup I3C_mode_structure_definition I3C mode structure definition + * @brief I3C Mode structure definition + * @{ + */ +typedef enum +{ + HAL_I3C_MODE_NONE = 0x00U, /*!< No I3C communication on going */ + HAL_I3C_MODE_CONTROLLER = 0x01U, /*!< I3C communication is in controller Mode */ + HAL_I3C_MODE_TARGET = 0x02U, /*!< I3C communication is in target Mode */ + +} HAL_I3C_ModeTypeDef; +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @{ + */ +typedef enum +{ + HAL_I3C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I3C_STATE_READY = 0x10U, /*!< Peripheral Initialized and ready for use */ + HAL_I3C_STATE_BUSY = 0x20U, /*!< An internal process is ongoing */ + HAL_I3C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I3C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I3C_STATE_BUSY_TX_RX = 0x23U, /*!< Data Multiple Transfer process is ongoing */ + HAL_I3C_STATE_BUSY_DAA = 0x24U, /*!< Dynamic address assignment process is ongoing */ + HAL_I3C_STATE_LISTEN = 0x30U, /*!< Listen process is ongoing */ + HAL_I3C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I3C_STATE_ERROR = 0xE0U, /*!< Error */ + +} HAL_I3C_StateTypeDef; +/** + * @} + */ + +/** @defgroup I3C_CCCInfoTypeDef_Structure_definition I3C CCCInfoTypeDef Structure definition + * @brief I3C CCCInfoTypeDef Structure definition + * @{ + */ +typedef struct +{ + uint32_t DynamicAddrValid; /*!< I3C target Dynamic Address Valid (updated during ENTDAA/RSTDAA/SETNEWDA CCC) + This parameter can be Valid=1U or Not Valid=0U */ + uint32_t DynamicAddr; /*!< I3C target Dynamic Address (updated during ENTDAA/RSTDAA/SETNEWDA CCC) */ + uint32_t MaxWriteLength; /*!< I3C target Maximum Write Length (updated during SETMWL CCC) */ + uint32_t MaxReadLength; /*!< I3C target Maximum Read Length (updated during SETMRL CCC) */ + uint32_t ResetAction; /*!< I3C target Reset Action level (updated during RSTACT CCC) */ + uint32_t ActivityState; /*!< I3C target Activity State (updated during ENTASx CCC) */ + uint32_t HotJoinAllowed; /*!< I3C target Hot Join (updated during ENEC/DISEC CCC) + This parameter can be Allowed=1U or Not Allowed=0U */ + uint32_t InBandAllowed; /*!< I3C target In Band Interrupt (updated during ENEC/DISEC CCC) + This parameter can be Allowed=1U or Not Allowed=0U */ + uint32_t CtrlRoleAllowed; /*!< I3C target Controller Role Request (updated during ENEC/DISEC CCC) + This parameter can be Allowed=1U or Not Allowed=0U */ + uint32_t IBICRTgtAddr; /*!< I3C controller receive Target Address during IBI or Controller Role Request event*/ + uint32_t IBITgtNbPayload; /*!< I3C controller get Number of Data Payload after an IBI event */ + uint32_t IBITgtPayload; /*!< I3C controller receive IBI Payload after an IBI event */ + +} I3C_CCCInfoTypeDef; +/** + * @} + */ + +/** @defgroup I3C_ControlTypeDef_Structure_definition I3C ControlTypeDef Structure definition + * @brief I3C ControlTypeDef Structure definition + * @{ + */ +typedef struct +{ + uint32_t *pBuffer; /*!< Pointer to the buffer containing the control or status register values */ + uint32_t Size; /*!< The size of pBuffer in words */ + +} I3C_ControlTypeDef; +/** + * @} + */ + +/** @defgroup I3C_DataTypeDef_Structure_definition I3C DataTypeDef Structure definition + * @brief I3C DataTypeDef Structure definition + * @{ + */ +typedef struct +{ + uint8_t *pBuffer; /*!< Pointer to the buffer containing all data values to transfer */ + uint32_t Size; /*!< The size of pBuffer in bytes */ + +} I3C_DataTypeDef; + +/** + * @} + */ + +/** @defgroup I3C_CCCTypeDef_Structure_definition I3C CCCTypeDef Structure definition + * @brief I3C CCCTypeDef Structure definition + * @{ + */ +typedef struct +{ + uint8_t TargetAddr; /*!< Dynamic or Static target Address */ + uint8_t CCC; /*!< CCC value code */ + I3C_DataTypeDef CCCBuf; /*!< Contain size of associated data and size of defining byte if any. + Contain pointer to CCC associated data */ + uint32_t Direction; /*!< CCC read and/or write direction message */ + +} I3C_CCCTypeDef; +/** + * @} + */ + +/** @defgroup I3C_BCRTypeDef_Structure_definition I3C BCRTypeDef Structure definition + * @brief I3C BCRTypeDef Structure definition + * @{ + */ +typedef struct +{ + FunctionalState MaxDataSpeedLimitation; /*!< Max data speed limitation */ + FunctionalState IBIRequestCapable; /*!< IBI request capable */ + FunctionalState IBIPayload; /*!< IBI payload data */ + FunctionalState OfflineCapable; /*!< Offline capable */ + FunctionalState VirtualTargetSupport; /*!< Virtual target support */ + FunctionalState AdvancedCapabilities; /*!< Advanced capabilities */ + FunctionalState DeviceRole; /*!< Device role */ + +} I3C_BCRTypeDef; +/** + * @} + */ + +/** @defgroup I3C_PIDTypeDef_Structure_definition I3C PIDTypeDef Structure definition + * @brief I3C_PIDTypeDef Structure definition + * @{ + */ +typedef struct +{ + uint16_t MIPIMID; /*!< MIPI Manufacturer ID */ + uint8_t IDTSEL; /*!< Provisioned ID Type Selector */ + uint16_t PartID; /*!< Part ID device vendor to define */ + uint8_t MIPIID; /*!< Instance ID */ + +} I3C_PIDTypeDef; +/** + * @} + */ + +/** @defgroup I3C_ENTDAAPayloadTypeDef_Structure_definition I3C ENTDAAPayloadTypeDef Structure definition + * @brief I3C ENTDAAPayloadTypeDef Structure definition + * @{ + */ +typedef struct +{ + I3C_BCRTypeDef BCR; /*!< Bus Characteristics Register */ + uint32_t DCR; /*!< Device Characteristics Register */ + I3C_PIDTypeDef PID; /*!< Provisioned ID */ + +} I3C_ENTDAAPayloadTypeDef; +/** + * @} + */ + +/** @defgroup I3C_PrivateTypeDef_Structure_definition I3C PrivateTypeDef Structure definition + * @brief I3C PrivateTypeDef Structure definition + * @{ + */ +typedef struct +{ + uint8_t TargetAddr; /*!< Dynamic or Static target Address */ + I3C_DataTypeDef TxBuf; /*!< Buffer structure containing the data to transmit (little endian) */ + I3C_DataTypeDef RxBuf; /*!< Buffer structure containing the data to receive (little endian) */ + uint32_t Direction; /*!< Read and/or write message */ + +} I3C_PrivateTypeDef; +/** + * @} + */ + +/** @defgroup I3C_XferTypeDef_Structure_definition I3C XferTypeDef Structure definition + * @brief I3C XferTypeDef Structure definition + * @{ + */ +typedef struct +{ + I3C_ControlTypeDef CtrlBuf; /*!< Buffer structure containing the control register values */ + I3C_ControlTypeDef StatusBuf; /*!< Buffer structure containing the status register values */ + I3C_DataTypeDef TxBuf; /*!< Buffer structure containing the data to transmit */ + I3C_DataTypeDef RxBuf; /*!< Buffer structure containing the data to receive */ + +} I3C_XferTypeDef; +/** + * @} + */ + +/** @defgroup I3C_handle_Structure_definition I3C handle Structure definition + * @brief I3C handle Structure definition + * @{ + */ +typedef struct __I3C_HandleTypeDef +{ + I3C_TypeDef *Instance; /*!< I3C registers base address */ + + I3C_InitTypeDef Init; /*!< I3C communication parameters */ + + HAL_I3C_ModeTypeDef Mode; /*!< I3C communication mode. + This parameter must be a value of + @ref I3C_mode_structure_definition */ + + I3C_XferTypeDef *pXferData; /*!< I3C transfer buffers pointer */ + + const I3C_CCCTypeDef *pCCCDesc; /*!< I3C CCC descriptor pointer */ + + const I3C_PrivateTypeDef *pPrivateDesc; /*!< I3C private transfer descriptor pointer */ + + uint32_t ControlXferCount; /*!< I3C counter indicating the remaining + control data bytes to write in + the control register */ + + uint32_t RxXferCount; /*!< I3C counter indicating the remaining + data bytes to receive */ + + uint32_t TxXferCount; /*!< I3C counter indicating the remaining + data bytes to transmit */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmacr; /*!< I3C control DMA handle parameters */ + + DMA_HandleTypeDef *hdmatx; /*!< I3C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I3C Rx DMA handle parameters */ + + DMA_HandleTypeDef *hdmasr; /*!< I3C status DMA handle parameters */ +#endif /* HAL_DMA_MODULE_ENABLED */ + + HAL_LockTypeDef Lock; /*!< I3C locking object */ + + __IO HAL_I3C_StateTypeDef State; /*!< I3C communication state */ + + __IO HAL_I3C_StateTypeDef PreviousState; /*!< I3C communication previous state */ + + __IO uint32_t ErrorCode; /*!< I3C Error code */ + + HAL_StatusTypeDef(*XferISR)(struct __I3C_HandleTypeDef *hi3c, + uint32_t itMasks); /*!< I3C transfer IRQ handler function pointer */ + + void(*ptrTxFunc)(struct __I3C_HandleTypeDef *hi3c); /*!< I3C transmit function pointer */ + + void(*ptrRxFunc)(struct __I3C_HandleTypeDef *hi3c); /*!< I3C receive function pointer */ + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + + void (* CtrlTxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); + /*!< I3C Controller private data and CCC Tx Transfer complete callback */ + + void (* CtrlRxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); + /*!< I3C Controller private data and CCC Rx Transfer completed callback */ + + void (* CtrlMultipleXferCpltCallback)(struct __I3C_HandleTypeDef *hi3c); + /*!< I3C Controller multiple Direct CCC, I3C private or I2C Transfer completed callback */ + + void (* CtrlDAACpltCallback)(struct __I3C_HandleTypeDef *hi3c); + /*!< I3C Controller Dynamic Address Assignment completed callback */ + + void (* TgtReqDynamicAddrCallback)(struct __I3C_HandleTypeDef *hi3c, uint64_t targetPayload); + /*!< I3C Controller request dynamic address callback during Dynamic Address Assignment processus */ + + void (* TgtTxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); + /*!< I3C Target private data Tx Transfer completed callback */ + + void (* TgtRxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); + /*!< I3C Target private data Rx Transfer completed callback */ + + void (* TgtHotJoinCallback)(struct __I3C_HandleTypeDef *hi3c, uint8_t dynamicAddress); + /*!< I3C Target Hot-Join callback */ + + void (* NotifyCallback)(struct __I3C_HandleTypeDef *hi3c, uint32_t eventId); + /*!< I3C Target or Controller asynchronous events callback */ + + void (* ErrorCallback)(struct __I3C_HandleTypeDef *hi3c); + /*!< I3C Error callback */ + + void (* AbortCpltCallback)(struct __I3C_HandleTypeDef *hi3c); + /*!< I3C Abort complete callback */ + + void (* MspInitCallback)(struct __I3C_HandleTypeDef *hi3c); + /*!< I3C Msp Init callback */ + + void (* MspDeInitCallback)(struct __I3C_HandleTypeDef *hi3c); + /*!< I3C Msp DeInit callback */ + +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + +} I3C_HandleTypeDef; +/** + * @} + */ + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_I3C_Callback_ID_definition I3C callback ID definition + * @brief HAL I3C callback ID definition + * @{ + */ +typedef enum +{ + /*!< I3C Controller Tx Transfer completed callback ID */ + HAL_I3C_CTRL_TX_COMPLETE_CB_ID = 0x00U, + /*!< I3C Controller Rx Transfer completed callback ID */ + HAL_I3C_CTRL_RX_COMPLETE_CB_ID = 0x01U, + /*!< I3C Controller Multiple Transfer completed callback ID */ + HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID = 0x02U, + /*!< I3C Controller Dynamic Address Assignment completed callback ID */ + HAL_I3C_CTRL_DAA_COMPLETE_CB_ID = 0x03U, + /*!< I3C Controller request dynamic address completed callback ID */ + HAL_I3C_TGT_REQ_DYNAMIC_ADDR_CB_ID = 0x04U, + /*!< I3C Target Tx Transfer completed callback ID */ + HAL_I3C_TGT_TX_COMPLETE_CB_ID = 0x05U, + /*!< I3C Target Rx Transfer completed callback ID */ + HAL_I3C_TGT_RX_COMPLETE_CB_ID = 0x06U, + /*!< I3C Target Hot-join notification callback ID */ + HAL_I3C_TGT_HOTJOIN_CB_ID = 0x07U, + /*!< I3C Target or Controller receive notification callback ID */ + HAL_I3C_NOTIFY_CB_ID = 0x08U, + /*!< I3C Error callback ID */ + HAL_I3C_ERROR_CB_ID = 0x09U, + /*!< I3C Abort callback ID */ + HAL_I3C_ABORT_CB_ID = 0x0AU, + /*!< I3C Msp Init callback ID */ + HAL_I3C_MSPINIT_CB_ID = 0x0BU, + /*!< I3C Msp DeInit callback ID */ + HAL_I3C_MSPDEINIT_CB_ID = 0x0CU + +} HAL_I3C_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_I3C_Callback_Pointer_definition I3C callback Pointer definition + * @brief HAL I3C callback pointer definition + * @{ + */ +typedef void (*pI3C_CallbackTypeDef)(I3C_HandleTypeDef *hi3c); +typedef void (*pI3C_NotifyCallbackTypeDef)(I3C_HandleTypeDef *hi3c, uint32_t notifyId); +typedef void (*pI3C_TgtHotJoinCallbackTypeDef)(I3C_HandleTypeDef *hi3c, uint8_t dynamicAddress); +typedef void (*pI3C_TgtReqDynamicAddrCallbackTypeDef)(I3C_HandleTypeDef *hi3c, uint64_t targetPayload); +/** + * @} + */ +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_Exported_Constants I3C Exported Constants + * @{ + */ + +/** @defgroup HAL_I3C_Notification_ID_definition I3C Notification ID definition + * @brief HAL I3C Notification ID definition + * @{ + */ + +#define EVENT_ID_GETACCCR (0x00000001U) +/*!< I3C target complete controller-role hand-off (direct GETACCR CCC) event */ +#define EVENT_ID_IBIEND (0x00000002U) +/*!< I3C target IBI end process event */ +#define EVENT_ID_DAU (0x00000004U) +/*!< I3C target receive a dynamic address update (ENTDAA/RSTDAA/SETNEWDA CCC) event */ +#define EVENT_ID_GETx (0x00000008U) +/*!< I3C target receive any direct GETxxx CCC event */ +#define EVENT_ID_GETSTATUS (0x00000010U) +/*!< I3C target receive get status command (direct GETSTATUS CCC) event */ +#define EVENT_ID_SETMWL (0x00000020U) +/*!< I3C target receive maximum write length update (direct SETMWL CCC) event */ +#define EVENT_ID_SETMRL (0x00000040U) +/*!< I3C target receive maximum read length update(direct SETMRL CCC) event */ +#define EVENT_ID_RSTACT (0x00000080U) +/*!< I3C target detect reset pattern (broadcast or direct RSTACT CCC) event */ +#define EVENT_ID_ENTASx (0x00000100U) +/*!< I3C target receive activity state update (direct or broadcast ENTASx) event */ +#define EVENT_ID_ENEC_DISEC (0x00000200U) +/*!< I3C target receive a direct or broadcast ENEC/DISEC CCC event */ +#define EVENT_ID_DEFTGTS (0x00000400U) +/*!< I3C target receive a broadcast DEFTGTS CCC event */ +#define EVENT_ID_DEFGRPA (0x00000800U) +/*!< I3C target receive a group addressing (broadcast DEFGRPA CCC) event */ +#define EVENT_ID_WKP (0x00001000U) +/*!< I3C target wakeup event */ +#define EVENT_ID_IBI (0x00002000U) +/*!< I3C controller receive IBI event */ +#define EVENT_ID_CR (0x00004000U) +/*!< I3C controller controller-role request event */ +#define EVENT_ID_HJ (0x00008000U) +/*!< I3C controller hot-join event */ +/** + * @} + */ + +/** @defgroup I3C_OPTION_DEFINITION OPTION DEFINITION + * @note HAL I3C option value coding follow below described bitmap: + * b31 + * 0 : message end type restart + * 1 : message end type stop + * b30-b29-b28-b27 + * 0010 : I3C private message + * 0011 : direct CCC message + * 0110 : broadcast CCC message + * 0100 : I2C private message + * b4 + * 0 : message without arbitration header + * 1 : message with arbitration header + * b0 + * 0 : message without defining byte + * 1 : message with defining byte + * + * other bits (not used) + * @{ + */ +#define I3C_DIRECT_WITH_DEFBYTE_RESTART (0x18000001U) /*!< Restart between each Direct Command then Stop + request for last command. + Each Command have an associated defining byte */ +#define I3C_DIRECT_WITH_DEFBYTE_STOP (0x98000001U) /*!< Stop between each Direct Command. + Each Command have an associated defining byte */ +#define I3C_DIRECT_WITHOUT_DEFBYTE_RESTART (0x18000000U) /*!< Restart between each Direct Command then Stop + request for last command. + Each Command have not an associated defining byte */ +#define I3C_DIRECT_WITHOUT_DEFBYTE_STOP (0x98000000U) /*!< Stop between each Direct Command. + Each Command have not an associated defining byte */ +#define I3C_BROADCAST_WITH_DEFBYTE_RESTART (0x30000001U) /*!< Restart between each Broadcast Command then Stop + request for last command. + Each Command have an associated defining byte */ +#define I3C_BROADCAST_WITH_DEFBYTE_STOP (0xB0000001U) /*!< Stop between each Broadcast Command. + Each Command have an associated defining byte */ +#define I3C_BROADCAST_WITHOUT_DEFBYTE_RESTART (0x30000000U) /*!< Restart between each Broadcast Command then Stop + request for last command. + Each Command have not an associated defining byte */ +#define I3C_BROADCAST_WITHOUT_DEFBYTE_STOP (0xB0000000U) /*!< Stop between each Broadcast Command. + Each Command have not an associated defining byte */ +#define I3C_PRIVATE_WITH_ARB_RESTART (0x10000000U) /*!< Restart between each I3C Private message then Stop + request for last message. + Each Message start with an arbitration header after + start bit condition */ +#define I3C_PRIVATE_WITH_ARB_STOP (0x90000000U) /*!< Stop between each I3C Private message. + Each Message start with an arbitration header after + start bit condition */ +#define I3C_PRIVATE_WITHOUT_ARB_RESTART (0x10000004U) /*!< Restart between each I3C message then Stop request + for last message. + Each Message start with Target address after start + bit condition */ +#define I3C_PRIVATE_WITHOUT_ARB_STOP (0x90000004U) /*!< Stop between each I3C Private message. + Each Message start with Target address after + start bit condition */ +#define I2C_PRIVATE_WITH_ARB_RESTART (0x20000000U) /*!< Restart between each I2C Private message then Stop + request for last message. + Each Message start with an arbitration header after + start bit condition */ +#define I2C_PRIVATE_WITH_ARB_STOP (0xA0000000U) /*!< Stop between each I2C Private message. + Each Message start with an arbitration header after + start bit condition */ +#define I2C_PRIVATE_WITHOUT_ARB_RESTART (0x20000004U) /*!< Restart between each I2C message then Stop request + for last message. + Each Message start with Target address after start + bit condition */ +#define I2C_PRIVATE_WITHOUT_ARB_STOP (0xA0000004U) /*!< Stop between each I2C Private message. + Each Message start with Target address after start + bit condition */ +/** + * @} + */ + +/** @defgroup I3C_DYNAMIC_ADDRESS_OPTION_DEFINITION I3C DYNAMIC ADDRESS OPTION DEFINITION + * @{ + */ +#define I3C_RSTDAA_THEN_ENTDAA (0x00000001U) /*!< Initiate a RSTDAA before a ENTDAA procedure */ +#define I3C_ONLY_ENTDAA (0x00000002U) /*!< Initiate a ENTDAA without RSTDAA */ +/** + * @} + */ + +/** @defgroup I3C_ERROR_CODE_DEFINITION ERROR CODE DEFINITION + * @{ + */ +#define HAL_I3C_ERROR_NONE (0x00000000U) /*!< No error */ + +#define HAL_I3C_ERROR_CE0 (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE0) /*!< Controller detected an illegally + formatted CCC */ +#define HAL_I3C_ERROR_CE1 (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE1) /*!< Controller detected that transmitted data + on the bus is different than expected */ +#define HAL_I3C_ERROR_CE2 (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE2) /*!< Controller detected that broadcast address + 7'h7E has been nacked */ +#define HAL_I3C_ERROR_CE3 (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE3) /*!< Controller detected that new Controller + did not drive the bus after + Controller-role handoff */ +#define HAL_I3C_ERROR_TE0 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE0) /*!< Target detected an invalid broadcast + address */ +#define HAL_I3C_ERROR_TE1 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE1) /*!< Target detected an invalid CCC Code */ +#define HAL_I3C_ERROR_TE2 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE2) /*!< Target detected a parity error during + a write data */ +#define HAL_I3C_ERROR_TE3 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE3) /*!< Target detected a parity error on assigned + address during dynamic address + arbitration */ +#define HAL_I3C_ERROR_TE4 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE4) /*!< Target detected 7'h7E missing after Restart + during Dynamic Address Assignment + procedure */ +#define HAL_I3C_ERROR_TE5 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE5) /*!< Target detected an illegally + formatted CCC */ +#define HAL_I3C_ERROR_TE6 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE6) /*!< Target detected that transmitted data on + the bus is different than expected */ +#define HAL_I3C_ERROR_DATA_HAND_OFF (I3C_SER_DERR) /*!< I3C data error during controller-role hand-off process */ +#define HAL_I3C_ERROR_DATA_NACK (I3C_SER_DNACK) /*!< I3C data not acknowledged error */ +#define HAL_I3C_ERROR_ADDRESS_NACK (I3C_SER_ANACK) /*!< I3C address not acknowledged error */ +#define HAL_I3C_ERROR_COVR (I3C_SER_COVR) /*!< I3C S FIFO Over-Run or C FIFO Under-Run error */ +#define HAL_I3C_ERROR_DOVR (I3C_SER_DOVR) /*!< I3C Rx FIFO Over-Run or Tx FIFO Under-Run error */ +#define HAL_I3C_ERROR_STALL (I3C_SER_STALL) /*!< I3C SCL stall error */ +#define HAL_I3C_ERROR_DMA (0x00010000U) /*!< DMA transfer error */ +#define HAL_I3C_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ +#define HAL_I3C_ERROR_DMA_PARAM (0x00040000U) /*!< DMA Parameter Error */ +#define HAL_I3C_ERROR_INVALID_PARAM (0x00080000U) /*!< Invalid Parameters error */ +#define HAL_I3C_ERROR_SIZE (0x00100000U) /*!< I3C size management error */ +#define HAL_I3C_ERROR_NOT_ALLOWED (0x00200000U) /*!< I3C operation is not allowed */ +#define HAL_I3C_ERROR_DYNAMIC_ADDR (0x00400000U) /*!< I3C dynamic address error */ + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) +#define HAL_I3C_ERROR_INVALID_CALLBACK (0x00800000U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ +/** + * @} + */ + +/** @defgroup I3C_SDA_HOLD_TIME SDA HOLD TIME + * @{ + */ +#define HAL_I3C_SDA_HOLD_TIME_0_5 LL_I3C_SDA_HOLD_TIME_0_5 /*!< SDA hold time equal to 0.5 x ti3cclk */ +#define HAL_I3C_SDA_HOLD_TIME_1_5 LL_I3C_SDA_HOLD_TIME_1_5 /*!< SDA hold time equal to 1.5 x ti3cclk */ +/** + * @} + */ + +/** @defgroup I3C_OWN_ACTIVITY_STATE OWN ACTIVITY STATE + * @{ + */ +#define HAL_I3C_OWN_ACTIVITY_STATE_0 LL_I3C_OWN_ACTIVITY_STATE_0 /*!< Own Controller Activity state 0 */ +#define HAL_I3C_OWN_ACTIVITY_STATE_1 LL_I3C_OWN_ACTIVITY_STATE_1 /*!< Own Controller Activity state 1 */ +#define HAL_I3C_OWN_ACTIVITY_STATE_2 LL_I3C_OWN_ACTIVITY_STATE_2 /*!< Own Controller Activity state 2 */ +#define HAL_I3C_OWN_ACTIVITY_STATE_3 LL_I3C_OWN_ACTIVITY_STATE_3 /*!< Own Controller Activity state 3 */ +/** + * @} + */ + +/** @defgroup I3C_RX_FIFO_THRESHOLD RX FIFO THRESHOLD + * @{ + */ +#define HAL_I3C_RXFIFO_THRESHOLD_1_4 LL_I3C_RXFIFO_THRESHOLD_1_4 /*!< Rx Fifo Threshold is 1 byte */ +#define HAL_I3C_RXFIFO_THRESHOLD_4_4 LL_I3C_RXFIFO_THRESHOLD_4_4 /*!< Rx Fifo Threshold is 4 bytes */ +/** + * @} + */ + +/** @defgroup I3C_TX_FIFO_THRESHOLD TX FIFO THRESHOLD + * @{ + */ +#define HAL_I3C_TXFIFO_THRESHOLD_1_4 LL_I3C_TXFIFO_THRESHOLD_1_4 /*!< Tx Fifo Threshold is 1 byte */ +#define HAL_I3C_TXFIFO_THRESHOLD_4_4 LL_I3C_TXFIFO_THRESHOLD_4_4 /*!< Tx Fifo Threshold is 4 bytes */ +/** + * @} + */ + +/** @defgroup I3C_CONTROL_FIFO_STATE CONTROL FIFO STATE + * @{ + */ +#define HAL_I3C_CONTROLFIFO_DISABLE 0x00000000U /*!< Control FIFO mode disable */ +#define HAL_I3C_CONTROLFIFO_ENABLE I3C_CFGR_TMODE /*!< Control FIFO mode enable */ +/** + * @} + */ + +/** @defgroup I3C_STATUS_FIFO_STATE STATUS FIFO STATE + * @{ + */ +#define HAL_I3C_STATUSFIFO_DISABLE 0x00000000U /*!< Status FIFO mode disable */ +#define HAL_I3C_STATUSFIFO_ENABLE I3C_CFGR_SMODE /*!< Status FIFO mode enable */ +/** + * @} + */ + +/** @defgroup I3C_DIRECTION DIRECTION + * @{ + */ +#define HAL_I3C_DIRECTION_WRITE LL_I3C_DIRECTION_WRITE /*!< Write transfer */ +#define HAL_I3C_DIRECTION_READ LL_I3C_DIRECTION_READ /*!< Read transfer */ +#define HAL_I3C_DIRECTION_BOTH (LL_I3C_DIRECTION_READ | 1U) /*!< Read and Write transfer */ +/** + * @} + */ + +/** @defgroup I3C_PAYLOAD_SIZE PAYLOAD SIZE + * @{ + */ +#define HAL_I3C_PAYLOAD_EMPTY LL_I3C_PAYLOAD_EMPTY /*!< Empty payload, no additional data after IBI acknowledge */ +#define HAL_I3C_PAYLOAD_1_BYTE LL_I3C_PAYLOAD_1_BYTE /*!< One additional data byte after IBI acknowledge */ +#define HAL_I3C_PAYLOAD_2_BYTES LL_I3C_PAYLOAD_2_BYTES /*!< Two additional data bytes after IBI acknowledge */ +#define HAL_I3C_PAYLOAD_3_BYTES LL_I3C_PAYLOAD_3_BYTES /*!< Three additional data bytes after IBI acknowledge */ +#define HAL_I3C_PAYLOAD_4_BYTES LL_I3C_PAYLOAD_4_BYTES /*!< Four additional data bytes after IBI acknowledge */ +/** + * @} + */ + +/** @defgroup I3C_HANDOFF_ACTIVITY_STATE HANDOFF ACTIVITY STATE + * @{ + */ +#define HAL_I3C_HANDOFF_ACTIVITY_STATE_0 LL_I3C_HANDOFF_ACTIVITY_STATE_0 /*!< Activity state 0 after handoff */ +#define HAL_I3C_HANDOFF_ACTIVITY_STATE_1 LL_I3C_HANDOFF_ACTIVITY_STATE_1 /*!< Activity state 1 after handoff */ +#define HAL_I3C_HANDOFF_ACTIVITY_STATE_2 LL_I3C_HANDOFF_ACTIVITY_STATE_2 /*!< Activity state 2 after handoff */ +#define HAL_I3C_HANDOFF_ACTIVITY_STATE_3 LL_I3C_HANDOFF_ACTIVITY_STATE_3 /*!< Activity state 3 after handoff */ +/** + * @} + */ + +/** @defgroup I3C_GETMXDS_FORMAT GETMXDS FORMAT + * @{ + */ +#define HAL_I3C_GETMXDS_FORMAT_1 LL_I3C_GETMXDS_FORMAT_1 /*!< GETMXDS CCC Format 1 is used, no MaxRdTurn + field in response */ +#define HAL_I3C_GETMXDS_FORMAT_2_LSB LL_I3C_GETMXDS_FORMAT_2_LSB /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field + in response, LSB = RDTURN[7:0] */ +#define HAL_I3C_GETMXDS_FORMAT_2_MID LL_I3C_GETMXDS_FORMAT_2_MID /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field + in response, Middle byte = RDTURN[7:0] */ +#define HAL_I3C_GETMXDS_FORMAT_2_MSB LL_I3C_GETMXDS_FORMAT_2_MSB /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field + in response, MSB = RDTURN[7:0] */ +/** + * @} + */ + +/** @defgroup I3C_TURNAROUND_TIME_TSCO TURNAROUND TIME TSCO + * @{ + */ +#define HAL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS +/*!< clock-to-data turnaround time tSCO <= 12ns */ +#define HAL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS +/*!< clock-to-data turnaround time tSCO > 12ns */ +/** + * @} + */ + +/** @defgroup I3C_COMMON_INTERRUPT I3C COMMON INTERRUPT + * @{ + */ +#define HAL_I3C_IT_TXFNFIE LL_I3C_IER_TXFNFIE /*!< Tx FIFO not full interrupt enable */ +#define HAL_I3C_IT_RXFNEIE LL_I3C_IER_RXFNEIE /*!< Rx FIFO not empty interrupt enable */ +#define HAL_I3C_IT_FCIE LL_I3C_IER_FCIE /*!< Frame complete interrupt enable */ +#define HAL_I3C_IT_ERRIE LL_I3C_IER_ERRIE /*!< Error interrupt enable */ +#define HAL_I3C_ALL_COMMON_ITS (uint32_t)(LL_I3C_IER_TXFNFIE | LL_I3C_IER_RXFNEIE | \ + LL_I3C_IER_FCIE | LL_I3C_IER_ERRIE) +/** + * @} + */ + +/** @defgroup I3C_TARGET_INTERRUPT I3C TARGET INTERRUPT + * @{ + */ +#define HAL_I3C_IT_IBIENDIE LL_I3C_IER_IBIENDIE /*!< IBI end interrupt enable */ +#define HAL_I3C_IT_CRUPDIE LL_I3C_IER_CRUPDIE /*!< controller-role update interrupt enable */ +#define HAL_I3C_IT_WKPIE LL_I3C_IER_WKPIE /*!< wakeup interrupt enable */ +#define HAL_I3C_IT_GETIE LL_I3C_IER_GETIE /*!< GETxxx CCC interrupt enable */ +#define HAL_I3C_IT_STAIE LL_I3C_IER_STAIE /*!< GETSTATUS CCC interrupt enable */ +#define HAL_I3C_IT_DAUPDIE LL_I3C_IER_DAUPDIE /*!< ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable */ +#define HAL_I3C_IT_MWLUPDIE LL_I3C_IER_MWLUPDIE /*!< SETMWL CCC interrupt enable */ +#define HAL_I3C_IT_MRLUPDIE LL_I3C_IER_MRLUPDIE /*!< SETMRL CCC interrupt enable */ +#define HAL_I3C_IT_RSTIE LL_I3C_IER_RSTIE /*!< reset pattern interrupt enable */ +#define HAL_I3C_IT_ASUPDIE LL_I3C_IER_ASUPDIE /*!< ENTASx CCC interrupt enable */ +#define HAL_I3C_IT_INTUPDIE LL_I3C_IER_INTUPDIE /*!< ENEC/DISEC CCC interrupt enable */ +#define HAL_I3C_IT_DEFIE (LL_I3C_IER_DEFIE | LL_I3C_IER_RXFNEIE) +/*!< DEFTGTS CCC interrupt enable */ +#define HAL_I3C_IT_GRPIE (LL_I3C_IER_GRPIE | LL_I3C_IER_RXFNEIE) +/*!< DEFGRPA CCC interrupt enable */ +#define HAL_I3C_ALL_TGT_ITS (uint32_t)(LL_I3C_IER_IBIENDIE | LL_I3C_IER_CRUPDIE | LL_I3C_IER_WKPIE | \ + LL_I3C_IER_GETIE | LL_I3C_IER_STAIE | LL_I3C_IER_DAUPDIE | \ + LL_I3C_IER_MWLUPDIE | LL_I3C_IER_MRLUPDIE | LL_I3C_IER_RSTIE | \ + LL_I3C_IER_ASUPDIE | LL_I3C_IER_INTUPDIE | LL_I3C_IER_DEFIE | \ + LL_I3C_IER_GRPIE) +/** + * @} + */ + +/** @defgroup I3C_CONTROLLER_INTERRUPT I3C CONTROLLER INTERRUPT + * @{ + */ +#define HAL_I3C_IT_CFNFIE LL_I3C_IER_CFNFIE /*!< Control FIFO not full interrupt enable */ +#define HAL_I3C_IT_SFNEIE LL_I3C_IER_SFNEIE /*!< Status FIFO not empty interrupt enable */ +#define HAL_I3C_IT_HJIE LL_I3C_IER_HJIE /*!< Hot-join interrupt enable */ +#define HAL_I3C_IT_CRIE LL_I3C_IER_CRIE /*!< Controller-role request interrupt enable */ +#define HAL_I3C_IT_IBIIE LL_I3C_IER_IBIIE /*!< IBI request interrupt enable */ +#define HAL_I3C_IT_RXTGTENDIE LL_I3C_IER_RXTGTENDIE /*!< Target-initiated read end interrupt enable */ +#define HAL_I3C_ALL_CTRL_ITS (uint32_t)(LL_I3C_IER_CFNFIE | LL_I3C_IER_SFNEIE | LL_I3C_IER_HJIE | \ + LL_I3C_IER_CRIE | LL_I3C_IER_IBIIE | LL_I3C_IER_RXTGTENDIE) +/** + * @} + */ + +/** @defgroup I3C_FLAGS I3C FLAGS + * @{ + */ +#define HAL_I3C_FLAG_CFEF LL_I3C_EVR_CFEF /*!< Control FIFO not empty flag */ +#define HAL_I3C_FLAG_TXFEF LL_I3C_EVR_TXFEF /*!< Tx FIFO empty flag */ +#define HAL_I3C_FLAG_CFNFF LL_I3C_EVR_CFNFF /*!< Control FIFO not full flag */ +#define HAL_I3C_FLAG_SFNEF LL_I3C_EVR_SFNEF /*!< Status FIFO not empty flag */ +#define HAL_I3C_FLAG_TXFNFF LL_I3C_EVR_TXFNFF /*!< Tx FIFO not full flag */ +#define HAL_I3C_FLAG_RXFNEF LL_I3C_EVR_RXFNEF /*!< Rx FIFO not empty flag */ +#define HAL_I3C_FLAG_RXLASTF LL_I3C_EVR_RXLASTF /*!< Last read data byte/word flag */ +#define HAL_I3C_FLAG_TXLASTF LL_I3C_EVR_TXLASTF /*!< Last written data byte/word flag */ +#define HAL_I3C_FLAG_FCF LL_I3C_EVR_FCF /*!< Frame complete flag */ +#define HAL_I3C_FLAG_RXTGTENDF LL_I3C_EVR_RXTGTENDF /*!< Target-initiated read end flag */ +#define HAL_I3C_FLAG_ERRF LL_I3C_EVR_ERRF /*!< Error flag */ +#define HAL_I3C_FLAG_IBIF LL_I3C_EVR_IBIF /*!< IBI request flag */ +#define HAL_I3C_FLAG_IBIENDF LL_I3C_EVR_IBIENDF /*!< IBI end flag */ +#define HAL_I3C_FLAG_CRF LL_I3C_EVR_CRF /*!< Controller-role request flag */ +#define HAL_I3C_FLAG_CRUPDF LL_I3C_EVR_CRUPDF /*!< Controller-role update flag */ +#define HAL_I3C_FLAG_HJF LL_I3C_EVR_HJF /*!< Hot-join flag */ +#define HAL_I3C_FLAG_WKPF LL_I3C_EVR_WKPF /*!< Wakeup flag */ +#define HAL_I3C_FLAG_GETF LL_I3C_EVR_GETF /*!< GETxxx CCC flag */ +#define HAL_I3C_FLAG_STAF LL_I3C_EVR_STAF /*!< Format 1 GETSTATUS CCC flag */ +#define HAL_I3C_FLAG_DAUPDF LL_I3C_EVR_DAUPDF /*!< ENTDAA/RSTDAA/SETNEWDA CCC flag */ +#define HAL_I3C_FLAG_MWLUPDF LL_I3C_EVR_MWLUPDF /*!< SETMWL CCC flag */ +#define HAL_I3C_FLAG_MRLUPDF LL_I3C_EVR_MRLUPDF /*!< SETMRL CCC flag */ +#define HAL_I3C_FLAG_RSTF LL_I3C_EVR_RSTF /*!< Reset pattern flag */ +#define HAL_I3C_FLAG_ASUPDF LL_I3C_EVR_ASUPDF /*!< ENTASx CCC flag */ +#define HAL_I3C_FLAG_INTUPDF LL_I3C_EVR_INTUPDF /*!< ENEC/DISEC CCC flag */ +#define HAL_I3C_FLAG_DEFF LL_I3C_EVR_DEFF /*!< DEFTGTS CCC flag */ +#define HAL_I3C_FLAG_GRPF LL_I3C_EVR_GRPF /*!< DEFGRPA CCC flag */ +/** + * @} + */ + +/** @defgroup I3C_BCR_IN_PAYLOAD I3C BCR IN PAYLOAD + * @{ + */ +#define HAL_I3C_BCR_IN_PAYLOAD_SHIFT 48 /*!< BCR field in target payload */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ---------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_Exported_Macros I3C Exported Macros + * @{ + */ + +/** @brief Reset I3C handle state. + * @param __HANDLE__ specifies the I3C Handle. + * @retval None + */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1) +#define __HAL_I3C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I3C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I3C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I3C_STATE_RESET) +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + +/** @brief Enable the specified I3C interrupt. + * @param __HANDLE__ specifies the I3C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one value or a combination of the following group's values: + * @arg @ref I3C_CONTROLLER_INTERRUPT + * @arg @ref I3C_TARGET_INTERRUPT + * @arg @ref I3C_COMMON_INTERRUPT + * @retval None + */ +#define __HAL_I3C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** @brief Disable the specified I3C interrupt. + * @param __HANDLE__ specifies the I3C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one value or a combination of the following group's values: + * @arg @ref I3C_CONTROLLER_INTERRUPT + * @arg @ref I3C_TARGET_INTERRUPT + * @arg @ref I3C_COMMON_INTERRUPT + * @retval None + */ +#define __HAL_I3C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I3C flag is set or not. + * @param __HANDLE__ specifies the I3C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one value of the group @arg @ref I3C_FLAGS values. + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_I3C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->EVR) &\ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Get Bus Characterics in payload (64bits) receive during ENTDAA procedure. + * @param __PAYLOAD__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFFFFFFFF. + * @retval The value of BCR Return value between Min_Data=0x00 and Max_Data=0xFF. + */ +#define __HAL_I3C_GET_BCR(__PAYLOAD__) (((uint32_t)((uint64_t)(__PAYLOAD__) >> HAL_I3C_BCR_IN_PAYLOAD_SHIFT)) & \ + I3C_BCR_BCR) + +/** @brief Check IBI request capabilities. + * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval The state of IBI request capabilities (ENABLE or DISABLE). + */ +#define __HAL_I3C_GET_IBI_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR1_Msk) >> I3C_BCR_BCR1_Pos) == 1U) \ + ? ENABLE : DISABLE) + +/** @brief Check IBI additional data byte capabilities. + * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval The state of IBI additional data byte capabilities (ENABLE or DISABLE). + */ +#define __HAL_I3C_GET_IBI_PAYLOAD(__BCR__) (((((__BCR__) & I3C_BCR_BCR2_Msk) >> I3C_BCR_BCR2_Pos) == 1U) \ + ? ENABLE : DISABLE) + +/** @brief Check Controller role request capabilities. + * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval The state of Controller role request capabilities (ENABLE or DISABLE). + */ +#define __HAL_I3C_GET_CR_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR6_Msk) >> I3C_BCR_BCR6_Pos) == 1U) \ + ? ENABLE : DISABLE) + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup I3C_Exported_Functions + * @{ + */ + +/** @addtogroup I3C_Exported_Functions_Group1 Initialization and de-initialization functions. + * @{ + */ +HAL_StatusTypeDef HAL_I3C_Init(I3C_HandleTypeDef *hi3c); +HAL_StatusTypeDef HAL_I3C_DeInit(I3C_HandleTypeDef *hi3c); +void HAL_I3C_MspInit(I3C_HandleTypeDef *hi3c); +void HAL_I3C_MspDeInit(I3C_HandleTypeDef *hi3c); +/** + * @} + */ + +/** @addtogroup I3C_Exported_Functions_Group2 Interrupt and callback functions. + * @{ + */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_I3C_RegisterCallback(I3C_HandleTypeDef *hi3c, + HAL_I3C_CallbackIDTypeDef callbackID, + pI3C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I3C_RegisterNotifyCallback(I3C_HandleTypeDef *hi3c, + pI3C_NotifyCallbackTypeDef pNotifyCallback); +HAL_StatusTypeDef HAL_I3C_RegisterTgtReqDynamicAddrCallback(I3C_HandleTypeDef *hi3c, + pI3C_TgtReqDynamicAddrCallbackTypeDef pTgtReqAddrCallback); +HAL_StatusTypeDef HAL_I3C_RegisterTgtHotJoinCallback(I3C_HandleTypeDef *hi3c, + pI3C_TgtHotJoinCallbackTypeDef pTgtHotJoinCallback); +HAL_StatusTypeDef HAL_I3C_UnRegisterCallback(I3C_HandleTypeDef *hi3c, HAL_I3C_CallbackIDTypeDef callbackID); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + +HAL_StatusTypeDef HAL_I3C_ActivateNotification(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, + uint32_t interruptMask); +HAL_StatusTypeDef HAL_I3C_DeactivateNotification(I3C_HandleTypeDef *hi3c, uint32_t interruptMask); +void HAL_I3C_CtrlTxCpltCallback(I3C_HandleTypeDef *hi3c); +void HAL_I3C_CtrlRxCpltCallback(I3C_HandleTypeDef *hi3c); +void HAL_I3C_CtrlMultipleXferCpltCallback(I3C_HandleTypeDef *hi3c); +void HAL_I3C_CtrlDAACpltCallback(I3C_HandleTypeDef *hi3c); +void HAL_I3C_TgtReqDynamicAddrCallback(I3C_HandleTypeDef *hi3c, uint64_t targetPayload); +void HAL_I3C_TgtTxCpltCallback(I3C_HandleTypeDef *hi3c); +void HAL_I3C_TgtRxCpltCallback(I3C_HandleTypeDef *hi3c); +void HAL_I3C_TgtHotJoinCallback(I3C_HandleTypeDef *hi3c, uint8_t dynamicAddress); +void HAL_I3C_NotifyCallback(I3C_HandleTypeDef *hi3c, uint32_t eventId); +void HAL_I3C_AbortCpltCallback(I3C_HandleTypeDef *hi3c); +void HAL_I3C_ErrorCallback(I3C_HandleTypeDef *hi3c); +void HAL_I3C_ER_IRQHandler(I3C_HandleTypeDef *hi3c); +void HAL_I3C_EV_IRQHandler(I3C_HandleTypeDef *hi3c); +/** + * @} + */ + +/** @addtogroup I3C_Exported_Functions_Group3 Configuration functions. + * @{ + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_BusCharacteristicConfig(I3C_HandleTypeDef *hi3c, + const LL_I3C_CtrlBusConfTypeDef *pConfig); +HAL_StatusTypeDef HAL_I3C_Tgt_BusCharacteristicConfig(I3C_HandleTypeDef *hi3c, + const LL_I3C_TgtBusConfTypeDef *pConfig); +HAL_StatusTypeDef HAL_I3C_SetConfigFifo(I3C_HandleTypeDef *hi3c, const I3C_FifoConfTypeDef *pConfig); +HAL_StatusTypeDef HAL_I3C_Ctrl_Config(I3C_HandleTypeDef *hi3c, const I3C_CtrlConfTypeDef *pConfig); +HAL_StatusTypeDef HAL_I3C_Tgt_Config(I3C_HandleTypeDef *hi3c, const I3C_TgtConfTypeDef *pConfig); +HAL_StatusTypeDef HAL_I3C_Ctrl_ConfigBusDevices(I3C_HandleTypeDef *hi3c, + const I3C_DeviceConfTypeDef *pDesc, + uint8_t nbDevice); +HAL_StatusTypeDef HAL_I3C_AddDescToFrame(I3C_HandleTypeDef *hi3c, + const I3C_CCCTypeDef *pCCCDesc, + const I3C_PrivateTypeDef *pPrivateDesc, + I3C_XferTypeDef *pXferData, + uint8_t nbFrame, + uint32_t option); +/** + * @} + */ + +/** @addtogroup I3C_Exported_Functions_Group4 FIFO Management functions. + * @{ + */ +HAL_StatusTypeDef HAL_I3C_FlushAllFifo(I3C_HandleTypeDef *hi3c); +HAL_StatusTypeDef HAL_I3C_FlushTxFifo(I3C_HandleTypeDef *hi3c); +HAL_StatusTypeDef HAL_I3C_FlushRxFifo(I3C_HandleTypeDef *hi3c); +HAL_StatusTypeDef HAL_I3C_FlushControlFifo(I3C_HandleTypeDef *hi3c); +HAL_StatusTypeDef HAL_I3C_FlushStatusFifo(I3C_HandleTypeDef *hi3c); +HAL_StatusTypeDef HAL_I3C_ClearConfigFifo(I3C_HandleTypeDef *hi3c); +HAL_StatusTypeDef HAL_I3C_GetConfigFifo(I3C_HandleTypeDef *hi3c, I3C_FifoConfTypeDef *pConfig); +/** + * @} + */ + +/** @addtogroup I3C_Exported_Functions_Group5 Controller operational functions. + * @{ + */ +/* Controller transmit direct write or a broadcast CCC command APIs */ +HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData, + uint32_t timeout); +HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_IT(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData); +HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_DMA(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData); + +/* Controller transmit direct read CCC command APIs */ +HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData, + uint32_t timeout); +HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_IT(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData); +HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_DMA(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData); + +/* Controller private write APIs */ +HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData, + uint32_t timeout); +HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_IT(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData); +HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_DMA(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData); + +/* Controller private read APIs */ +HAL_StatusTypeDef HAL_I3C_Ctrl_Receive(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData, + uint32_t timeout); +HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_IT(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData); +HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_DMA(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData); + +/* Controller multiple Direct CCC Command, I3C private or I2C transfer APIs */ +HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_IT(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData); +HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_DMA(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData); + +/* Controller assign dynamic address APIs */ +HAL_StatusTypeDef HAL_I3C_Ctrl_SetDynAddr(I3C_HandleTypeDef *hi3c, uint8_t devAddress); +HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign_IT(I3C_HandleTypeDef *hi3c, uint32_t dynOption); +HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign(I3C_HandleTypeDef *hi3c, + uint64_t *target_payload, + uint32_t dynOption, + uint32_t timeout); +/* Controller check device ready APIs */ +HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI3C_Ready(I3C_HandleTypeDef *hi3c, + uint8_t devAddress, + uint32_t trials, + uint32_t timeout); +HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI2C_Ready(I3C_HandleTypeDef *hi3c, + uint8_t devAddress, + uint32_t trials, + uint32_t timeout); +/** + * @} + */ + +/** @addtogroup I3C_Exported_Functions_Group6 Target operational functions. + * @{ + */ +HAL_StatusTypeDef HAL_I3C_Tgt_Transmit(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, uint32_t timeout); +HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData); +HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData); +HAL_StatusTypeDef HAL_I3C_Tgt_Receive(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, uint32_t timeout); +HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData); +HAL_StatusTypeDef HAL_I3C_Tgt_Receive_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData); +HAL_StatusTypeDef HAL_I3C_Tgt_ControlRoleReq(I3C_HandleTypeDef *hi3c, uint32_t timeout); +HAL_StatusTypeDef HAL_I3C_Tgt_ControlRoleReq_IT(I3C_HandleTypeDef *hi3c); +HAL_StatusTypeDef HAL_I3C_Tgt_HotJoinReq(I3C_HandleTypeDef *hi3c, uint8_t *pAddress, uint32_t timeout); +HAL_StatusTypeDef HAL_I3C_Tgt_HotJoinReq_IT(I3C_HandleTypeDef *hi3c); +HAL_StatusTypeDef HAL_I3C_Tgt_IBIReq(I3C_HandleTypeDef *hi3c, const uint8_t *pPayload, + uint8_t payloadSize, uint32_t timeout); +HAL_StatusTypeDef HAL_I3C_Tgt_IBIReq_IT(I3C_HandleTypeDef *hi3c, const uint8_t *pPayload, uint8_t payloadSize); +/** + * @} + */ + +/** @addtogroup I3C_Exported_Functions_Group7 Generic and Common functions. + * @{ + */ +HAL_StatusTypeDef HAL_I3C_Abort_IT(I3C_HandleTypeDef *hi3c); +HAL_I3C_StateTypeDef HAL_I3C_GetState(const I3C_HandleTypeDef *hi3c); +HAL_I3C_ModeTypeDef HAL_I3C_GetMode(const I3C_HandleTypeDef *hi3c); +uint32_t HAL_I3C_GetError(const I3C_HandleTypeDef *hi3c); +HAL_StatusTypeDef HAL_I3C_GetCCCInfo(I3C_HandleTypeDef *hi3c, + uint32_t notifyId, + I3C_CCCInfoTypeDef *pCCCInfo); +HAL_StatusTypeDef HAL_I3C_Get_ENTDAA_Payload_Info(I3C_HandleTypeDef *hi3c, + uint64_t ENTDAA_payload, + I3C_ENTDAAPayloadTypeDef *pENTDAA_payload); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_Private_Constants I3C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_Private_Macro I3C Private Macros + * @{ + */ +#define IS_I3C_MODE(__MODE__) (((__MODE__) == HAL_I3C_MODE_NONE) || \ + ((__MODE__) == HAL_I3C_MODE_CONTROLLER) || \ + ((__MODE__) == HAL_I3C_MODE_TARGET)) + +#define IS_I3C_INTERRUPTMASK(__MODE__, __ITMASK__) (((__MODE__) == HAL_I3C_MODE_CONTROLLER) ? \ + ((((__ITMASK__) & HAL_I3C_ALL_CTRL_ITS) != 0x0U) || \ + (((__ITMASK__) & HAL_I3C_ALL_COMMON_ITS) != 0x0U)) : \ + ((((__ITMASK__) & HAL_I3C_ALL_TGT_ITS) != 0x0U) || \ + (((__ITMASK__) & HAL_I3C_ALL_COMMON_ITS) != 0x0U))) + +#define IS_I3C_ENTDAA_OPTION(__OPTION__) (((__OPTION__) == I3C_RSTDAA_THEN_ENTDAA) || \ + ((__OPTION__) == I3C_ONLY_ENTDAA)) + +#define IS_I3C_SDAHOLDTIME_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_SDA_HOLD_TIME_0_5) || \ + ((__VALUE__) == HAL_I3C_SDA_HOLD_TIME_1_5)) + +#define IS_I3C_WAITTIME_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_0) || \ + ((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_1) || \ + ((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_2) || \ + ((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_3)) + +#define IS_I3C_TXFIFOTHRESHOLD_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_TXFIFO_THRESHOLD_1_4) || \ + ((__VALUE__) == HAL_I3C_TXFIFO_THRESHOLD_4_4)) + +#define IS_I3C_RXFIFOTHRESHOLD_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_RXFIFO_THRESHOLD_1_4) || \ + ((__VALUE__) == HAL_I3C_RXFIFO_THRESHOLD_4_4)) + +#define IS_I3C_CONTROLFIFOSTATE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_CONTROLFIFO_DISABLE) || \ + ((__VALUE__) == HAL_I3C_CONTROLFIFO_ENABLE)) + +#define IS_I3C_STATUSFIFOSTATE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_STATUSFIFO_DISABLE) || \ + ((__VALUE__) == HAL_I3C_STATUSFIFO_ENABLE)) + +#define IS_I3C_DEVICE_VALUE(__VALUE__) (((__VALUE__) >= 1U) && ((__VALUE__) <= 4U)) + +#define IS_I3C_DYNAMICADDRESS_VALUE(__VALUE__) ((__VALUE__) <= 0x7FU) + +#define IS_I3C_FUNCTIONALSTATE_VALUE(__VALUE__) (((__VALUE__) == DISABLE) || \ + ((__VALUE__) == ENABLE)) + +#define IS_I3C_HANDOFFACTIVITYSTATE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_0) || \ + ((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_1) || \ + ((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_2) || \ + ((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_3)) + +#define IS_I3C_TSCOTIME_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS) || \ + ((__VALUE__) == HAL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS)) + +#define IS_I3C_MAXSPEEDDATA_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_1 ) || \ + ((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_2_LSB) || \ + ((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_2_MID) || \ + ((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_2_MSB)) + +#define IS_I3C_IBIPAYLOADSIZE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_PAYLOAD_EMPTY ) || \ + ((__VALUE__) == HAL_I3C_PAYLOAD_1_BYTE ) || \ + ((__VALUE__) == HAL_I3C_PAYLOAD_2_BYTES) || \ + ((__VALUE__) == HAL_I3C_PAYLOAD_3_BYTES) || \ + ((__VALUE__) == HAL_I3C_PAYLOAD_4_BYTES)) + +#define IS_I3C_MIPIIDENTIFIER_VALUE(__VALUE__) ((__VALUE__) <= 0x0FU) + +#define IS_I3C_MAXREADTURNARROUND_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU) + +#define I3C_CHECK_IT_SOURCE(__IER__, __IT__) ((((__IER__) & (__IT__)) == (__IT__)) ? SET : RESET) + +#define I3C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +#define IS_I3C_DMASOURCEBYTE_VALUE(__VALUE__) ((__VALUE__) == DMA_SRC_DATAWIDTH_BYTE) + +#define IS_I3C_DMASOURCEWORD_VALUE(__VALUE__) ((__VALUE__) == DMA_SRC_DATAWIDTH_WORD) + +#define IS_I3C_DMADESTINATIONBYTE_VALUE(__VALUE__) ((__VALUE__) == DMA_DEST_DATAWIDTH_BYTE) + +#define IS_I3C_DMADESTINATIONWORD_VALUE(__VALUE__) ((__VALUE__) == DMA_DEST_DATAWIDTH_WORD) + +#define I3C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__)) + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_Private_Functions I3C Private Functions + * @{ + */ +/* Private functions are defined in stm32h7rsxx_hal_i3c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_I3C_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_icache.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_icache.h new file mode 100644 index 00000000000..810c8592a0c --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_icache.h @@ -0,0 +1,216 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_icache.h + * @author MCD Application Team + * @brief Header file of ICACHE HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion ------------------------------------*/ +#ifndef STM32H7RSxx_HAL_ICACHE_H +#define STM32H7RSxx_HAL_ICACHE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -----------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +#if defined(ICACHE) +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup ICACHE + * @{ + */ + +/* Exported types -----------------------------------------------------------*/ + +/* Exported constants -------------------------------------------------------*/ +/** @defgroup ICACHE_Exported_Constants ICACHE Exported Constants + * @{ + */ + +/** @defgroup ICACHE_WaysSelection Ways selection + * @{ + */ +#define ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ +#define ICACHE_4WAYS ICACHE_CR_WAYSEL /*!< 4-ways set associative cache (default) */ +/** + * @} + */ + +/** @defgroup ICACHE_Monitor_Type Monitor type + * @{ + */ +#define ICACHE_MONITOR_HIT_MISS (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< Hit & Miss monitoring */ +#define ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitoring */ +#define ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitoring */ +/** + * @} + */ + + +/** @defgroup ICACHE_Interrupts Interrupts + * @{ + */ +#define ICACHE_IT_BUSYEND ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ +#define ICACHE_IT_ERROR ICACHE_IER_ERRIE /*!< Cache error interrupt */ +/** + * @} + */ + +/** @defgroup ICACHE_Flags Flags + * @{ + */ +#define ICACHE_FLAG_BUSY ICACHE_SR_BUSYF /*!< Busy flag */ +#define ICACHE_FLAG_BUSYEND ICACHE_SR_BSYENDF /*!< Busy end flag */ +#define ICACHE_FLAG_ERROR ICACHE_SR_ERRF /*!< Cache error flag */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ----------------------------------------------------------*/ +/** @defgroup ICACHE_Exported_Macros ICACHE Exported Macros + * @{ + */ + +/** @defgroup ICACHE_Flags_Interrupts_Management Flags and Interrupts Management + * @brief macros to manage the specified ICACHE flags and interrupts. + * @{ + */ + +/** @brief Enable ICACHE interrupts. + * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt + * @arg @ref ICACHE_IT_ERROR Cache error interrupt + */ +#define __HAL_ICACHE_ENABLE_IT(__INTERRUPT__) SET_BIT(ICACHE->IER, (__INTERRUPT__)) + +/** @brief Disable ICACHE interrupts. + * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt + * @arg @ref ICACHE_IT_ERROR Cache error interrupt + */ +#define __HAL_ICACHE_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(ICACHE->IER, (__INTERRUPT__)) + +/** @brief Check whether the specified ICACHE interrupt source is enabled or not. + * @param __INTERRUPT__ specifies the ICACHE interrupt source to check. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt + * @arg @ref ICACHE_IT_ERROR Cache error interrupt + * @retval The state of __INTERRUPT__ (0 or 1). + */ +#define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__) \ + ((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U) + +/** @brief Check whether the selected ICACHE flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref ICACHE_FLAG_BUSY Busy flag + * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag + * @arg @ref ICACHE_FLAG_ERROR Cache error flag + * @retval The state of __FLAG__ (0 or 1). + */ +#define __HAL_ICACHE_GET_FLAG(__FLAG__) ((READ_BIT(ICACHE->SR, (__FLAG__)) != 0U) ? 1U : 0U) + +/** @brief Clear the selected ICACHE flags. + * @param __FLAG__ specifies the ICACHE flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag + * @arg @ref ICACHE_FLAG_ERROR Cache error flag + */ +#define __HAL_ICACHE_CLEAR_FLAG(__FLAG__) WRITE_REG(ICACHE->FCR, (__FLAG__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions -------------------------------------------------------*/ +/** @addtogroup ICACHE_Exported_Functions + * @{ + */ + +/** @addtogroup ICACHE_Exported_Functions_Group1 + * @brief Initialization and control functions + * @{ + */ +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_ICACHE_Enable(void); +HAL_StatusTypeDef HAL_ICACHE_Disable(void); +uint32_t HAL_ICACHE_IsEnabled(void); +HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode); +HAL_StatusTypeDef HAL_ICACHE_DeInit(void); + +/******* Invalidate in blocking mode (Polling) */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate(void); +/******* Invalidate in non-blocking mode (Interrupt) */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void); +/******* Wait for Invalidate complete in blocking mode (Polling) */ +HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void); + +/******* Performance instruction cache monitoring functions */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType); +HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType); +HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType); +uint32_t HAL_ICACHE_Monitor_GetHitValue(void); +uint32_t HAL_ICACHE_Monitor_GetMissValue(void); + +/** + * @} + */ + +/** @addtogroup ICACHE_Exported_Functions_Group2 + * @brief IRQ and callback functions + * @{ + */ +/******* IRQHandler and Callbacks used in non-blocking mode (Interrupt) */ +void HAL_ICACHE_IRQHandler(void); +void HAL_ICACHE_InvalidateCompleteCallback(void); +void HAL_ICACHE_ErrorCallback(void); + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* ICACHE */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_ICACHE_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_irda.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_irda.h new file mode 100644 index 00000000000..37625f8258c --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_irda.h @@ -0,0 +1,900 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_irda.h + * @author MCD Application Team + * @brief Header file of IRDA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_IRDA_H +#define STM32H7RSxx_HAL_IRDA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup IRDA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup IRDA_Exported_Types IRDA Exported Types + * @{ + */ + +/** + * @brief IRDA Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate. + The baud rate register is computed using the following formula: + Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate))) + where usart_ker_ckpres is the IRDA input clock divided by a prescaler */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref IRDAEx_Word_Length */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref IRDA_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref IRDA_Transfer_Mode */ + + uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock + to achieve low-power frequency. + @note Prescaler value 0 is forbidden */ + + uint16_t PowerMode; /*!< Specifies the IRDA power mode. + This parameter can be a value of @ref IRDA_Low_Power */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the IRDA clock source. + This parameter can be a value of @ref IRDA_ClockPrescaler. */ + +} IRDA_InitTypeDef; + +/** + * @brief HAL IRDA State definition + * @note HAL IRDA State value is a combination of 2 different substates: + * gState and RxState (see @ref IRDA_State_Definition). + * - gState contains IRDA state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL IRDA Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_IRDA_StateTypeDef; + +/** + * @brief IRDA clock sources definition + */ +typedef enum +{ + IRDA_CLOCKSOURCE_PLL2Q = 0x14U, /*!< PLL2Q clock source */ + IRDA_CLOCKSOURCE_PLL3Q = 0x18U, /*!< PLL3Q clock source */ + IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + IRDA_CLOCKSOURCE_CSI = 0x08U, /*!< CSI clock source */ + IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */ + IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */ +} IRDA_ClockSourceTypeDef; + +/** + * @brief IRDA handle Structure definition + */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +typedef struct __IRDA_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ +{ + USART_TypeDef *Instance; /*!< USART registers base address */ + + IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< IRDA Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */ + + uint16_t Mask; /*!< USART RX RDR register mask */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ + + __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations. + This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< IRDA Error code */ + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */ + + void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */ + + void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */ + + void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */ + + void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */ + + void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */ + + void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */ + + void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */ + + + void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */ + + void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */ +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + +} IRDA_HandleTypeDef; + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +/** + * @brief HAL IRDA Callback ID enumeration definition + */ +typedef enum +{ + HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */ + HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */ + HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */ + HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */ + HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */ + HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */ + HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */ + HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */ + + HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */ + HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */ + +} HAL_IRDA_CallbackIDTypeDef; + +/** + * @brief HAL IRDA Callback pointer definition + */ +typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */ + +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IRDA_Exported_Constants IRDA Exported Constants + * @{ + */ + +/** @defgroup IRDA_State_Definition IRDA State Code Definition + * @{ + */ +#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing + Value is allowed for gState only */ +#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between + gState and RxState values */ +#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup IRDA_Error_Definition IRDA Error Code Definition + * @{ + */ +#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup IRDA_Parity IRDA Parity + * @{ + */ +#define IRDA_PARITY_NONE 0x00000000U /*!< No parity */ +#define IRDA_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode + * @{ + */ +#define IRDA_MODE_RX USART_CR1_RE /*!< RX mode */ +#define IRDA_MODE_TX USART_CR1_TE /*!< TX mode */ +#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup IRDA_Low_Power IRDA Low Power + * @{ + */ +#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */ +#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */ +/** + * @} + */ + +/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler + * @{ + */ +#define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define IRDA_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define IRDA_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define IRDA_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define IRDA_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define IRDA_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define IRDA_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define IRDA_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define IRDA_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define IRDA_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define IRDA_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define IRDA_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ +/** + * @} + */ + +/** @defgroup IRDA_State IRDA State + * @{ + */ +#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */ +#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */ +/** + * @} + */ + +/** @defgroup IRDA_Mode IRDA Mode + * @{ + */ +#define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */ +#define IRDA_MODE_ENABLE USART_CR3_IREN /*!< Associated UART enabled in IRDA mode */ +/** + * @} + */ + +/** @defgroup IRDA_One_Bit IRDA One Bit Sampling + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */ +#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enabled */ +/** + * @} + */ + +/** @defgroup IRDA_DMA_Tx IRDA DMA Tx + * @{ + */ +#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */ +#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */ +/** + * @} + */ + +/** @defgroup IRDA_DMA_Rx IRDA DMA Rx + * @{ + */ +#define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */ +#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR /*!< IRDA DMA RX enabled */ +/** + * @} + */ + +/** @defgroup IRDA_Request_Parameters IRDA Request Parameters + * @{ + */ +#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup IRDA_Flags IRDA Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define IRDA_FLAG_REACK USART_ISR_REACK /*!< IRDA receive enable acknowledge flag */ +#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< IRDA transmit enable acknowledge flag */ +#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< IRDA busy flag */ +#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< IRDA auto Baud rate flag */ +#define IRDA_FLAG_ABRE USART_ISR_ABRE /*!< IRDA auto Baud rate error */ +#define IRDA_FLAG_TXE USART_ISR_TXE_TXFNF /*!< IRDA transmit data register empty */ +#define IRDA_FLAG_TC USART_ISR_TC /*!< IRDA transmission complete */ +#define IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< IRDA read data register not empty */ +#define IRDA_FLAG_ORE USART_ISR_ORE /*!< IRDA overrun error */ +#define IRDA_FLAG_NE USART_ISR_NE /*!< IRDA noise error */ +#define IRDA_FLAG_FE USART_ISR_FE /*!< IRDA frame error */ +#define IRDA_FLAG_PE USART_ISR_PE /*!< IRDA parity error */ +/** + * @} + */ + +/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition + * Elements values convention: 0000ZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define IRDA_IT_PE 0x0028U /*!< IRDA Parity error interruption */ +#define IRDA_IT_TXE 0x0727U /*!< IRDA Transmit data register empty interruption */ +#define IRDA_IT_TC 0x0626U /*!< IRDA Transmission complete interruption */ +#define IRDA_IT_RXNE 0x0525U /*!< IRDA Read data register not empty interruption */ +#define IRDA_IT_IDLE 0x0424U /*!< IRDA Idle interruption */ + +/* Elements values convention: 000000000XXYYYYYb + - YYYYY : Interrupt source position in the XX register (5bits) + - XX : Interrupt source register (2bits) + - 01: CR1 register + - 10: CR2 register + - 11: CR3 register */ +#define IRDA_IT_ERR 0x0060U /*!< IRDA Error interruption */ + +/* Elements values convention: 0000ZZZZ00000000b + - ZZZZ : Flag position in the ISR register(4bits) */ +#define IRDA_IT_ORE 0x0300U /*!< IRDA Overrun error interruption */ +#define IRDA_IT_NE 0x0200U /*!< IRDA Noise error interruption */ +#define IRDA_IT_FE 0x0100U /*!< IRDA Frame error interruption */ +/** + * @} + */ + +/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags + * @{ + */ +#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define IRDA_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ +#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +/** + * @} + */ + +/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask + * @{ + */ +#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */ +#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */ +#define IRDA_CR_POS 5U /*!< IRDA control register position */ +#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */ +#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup IRDA_Exported_Macros IRDA Exported Macros + * @{ + */ + +/** @brief Reset IRDA handle state. + * @param __HANDLE__ IRDA handle. + * @retval None + */ +#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 +#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */ + +/** @brief Flush the IRDA DR register. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified IRDA pending flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref IRDA_CLEAR_PEF + * @arg @ref IRDA_CLEAR_FEF + * @arg @ref IRDA_CLEAR_NEF + * @arg @ref IRDA_CLEAR_OREF + * @arg @ref IRDA_CLEAR_TCF + * @arg @ref IRDA_CLEAR_IDLEF + * @retval None + */ +#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the IRDA PE pending flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF) + + +/** @brief Clear the IRDA FE pending flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF) + +/** @brief Clear the IRDA NE pending flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF) + +/** @brief Clear the IRDA ORE pending flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF) + +/** @brief Clear the IRDA IDLE pending flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF) + +/** @brief Check whether the specified IRDA flag is set or not. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag + * @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref IRDA_FLAG_BUSY Busy flag + * @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref IRDA_FLAG_TXE Transmit data register empty flag + * @arg @ref IRDA_FLAG_TC Transmission Complete flag + * @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag + * @arg @ref IRDA_FLAG_ORE OverRun Error flag + * @arg @ref IRDA_FLAG_NE Noise Error flag + * @arg @ref IRDA_FLAG_FE Framing Error flag + * @arg @ref IRDA_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + + +/** @brief Enable the specified IRDA interrupt. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt + * @arg @ref IRDA_IT_TC Transmission complete interrupt + * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt + * @arg @ref IRDA_IT_IDLE Idle line detection interrupt + * @arg @ref IRDA_IT_PE Parity Error interrupt + * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((__HANDLE__)->Instance->CR3 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) + +/** @brief Disable the specified IRDA interrupt. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt + * @arg @ref IRDA_IT_TC Transmission complete interrupt + * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt + * @arg @ref IRDA_IT_IDLE Idle line detection interrupt + * @arg @ref IRDA_IT_PE Parity Error interrupt + * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) + +/** @brief Check whether the specified IRDA interrupt has occurred or not. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt + * @arg @ref IRDA_IT_TC Transmission complete interrupt + * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt + * @arg @ref IRDA_IT_IDLE Idle line detection interrupt + * @arg @ref IRDA_IT_ORE OverRun Error interrupt + * @arg @ref IRDA_IT_NE Noise Error interrupt + * @arg @ref IRDA_IT_FE Framing Error interrupt + * @arg @ref IRDA_IT_PE Parity Error interrupt + * @retval The new state of __IT__ (SET or RESET). + */ +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET) + +/** @brief Check whether the specified IRDA interrupt source is enabled or not. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt + * @arg @ref IRDA_IT_TC Transmission complete interrupt + * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt + * @arg @ref IRDA_IT_IDLE Idle line detection interrupt + * @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt + * @arg @ref IRDA_IT_PE Parity Error interrupt + * @retval The new state of __IT__ (SET or RESET). + */ +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \ + & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \ + & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) + +/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag + * @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag + * @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag + * @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag + * @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag + * @retval None + */ +#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + + +/** @brief Set a specific IRDA request flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the IRDA one bit sample method. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the IRDA one bit sample method. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) + +/** @brief Enable UART/USART associated to IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART/USART associated to IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @addtogroup IRDA_Private_Macros + * @{ + */ + +/** @brief Ensure that IRDA Baud rate is less or equal to maximum value. + * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user. + * @retval True or False + */ +#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U) + +/** @brief Ensure that IRDA prescaler value is strictly larger than 0. + * @param __PRESCALER__ specifies the IRDA prescaler value set by the user. + * @retval True or False + */ +#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U) + +/** @brief Ensure that IRDA frame parity is valid. + * @param __PARITY__ IRDA frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \ + ((__PARITY__) == IRDA_PARITY_EVEN) || \ + ((__PARITY__) == IRDA_PARITY_ODD)) + +/** @brief Ensure that IRDA communication mode is valid. + * @param __MODE__ IRDA communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\ + & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) + +/** @brief Ensure that IRDA power mode is valid. + * @param __MODE__ IRDA power mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \ + ((__MODE__) == IRDA_POWERMODE_NORMAL)) + +/** @brief Ensure that IRDA clock Prescaler is valid. + * @param __CLOCKPRESCALER__ IRDA clock Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256)) + +/** @brief Ensure that IRDA state is valid. + * @param __STATE__ IRDA state mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \ + ((__STATE__) == IRDA_STATE_ENABLE)) + +/** @brief Ensure that IRDA associated UART/USART mode is valid. + * @param __MODE__ IRDA associated UART/USART mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \ + ((__MODE__) == IRDA_MODE_ENABLE)) + +/** @brief Ensure that IRDA sampling rate is valid. + * @param __ONEBIT__ IRDA sampling rate. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE)) + +/** @brief Ensure that IRDA DMA TX mode is valid. + * @param __DMATX__ IRDA DMA TX mode. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \ + ((__DMATX__) == IRDA_DMA_TX_ENABLE)) + +/** @brief Ensure that IRDA DMA RX mode is valid. + * @param __DMARX__ IRDA DMA RX mode. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \ + ((__DMARX__) == IRDA_DMA_RX_ENABLE)) + +/** @brief Ensure that IRDA request is valid. + * @param __PARAM__ IRDA request. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST)) +/** + * @} + */ + +/* Include IRDA HAL Extended module */ +#include "stm32h7rsxx_hal_irda_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions + * @{ + */ + +/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, + pIRDA_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); +#endif /* HAL_DMA_MODULE_ENABLED */ +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda); + +void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda); + +/** + * @} + */ + +/* Peripheral Control functions ************************************************/ + +/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda); +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_IRDA_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_irda_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_irda_ex.h new file mode 100644 index 00000000000..b41989a560a --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_irda_ex.h @@ -0,0 +1,216 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_irda_ex.h + * @author MCD Application Team + * @brief Header file of IRDA HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_IRDA_EX_H +#define STM32H7RSxx_HAL_IRDA_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup IRDAEx IRDAEx + * @brief IRDA Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants + * @{ + */ + +/** @defgroup IRDAEx_Word_Length IRDAEx Word Length + * @{ + */ +#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */ +#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */ +#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros + * @{ + */ + +/** @brief Report the IRDA clock source. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval IRDA clocking source, written in __CLOCKSOURCE__. + */ +/** @brief Return clock source used for USART instance used for IRDA. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval USART clocking source, written in __CLOCKSOURCE__. + */ +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART1CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if(((__HANDLE__)->Instance == USART2) || \ + ((__HANDLE__)->Instance == USART3) || \ + ((__HANDLE__)->Instance == UART4) || \ + ((__HANDLE__)->Instance == UART5) || \ + ((__HANDLE__)->Instance == UART7) || \ + ((__HANDLE__)->Instance == UART8)) \ + { \ + switch(__HAL_RCC_GET_USART234578_SOURCE()) \ + { \ + case RCC_USART234578CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART234578CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART234578CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART234578CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART234578CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART234578CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) + +/** @brief Compute the mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define IRDA_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** @brief Ensure that IRDA frame length is valid. + * @param __LENGTH__ IRDA frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \ + ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \ + ((__LENGTH__) == IRDA_WORDLENGTH_9B)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_IRDA_EX_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_iwdg.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_iwdg.h new file mode 100644 index 00000000000..beeb3a0edb7 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_iwdg.h @@ -0,0 +1,302 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_iwdg.h + * @author MCD Application Team + * @brief Header file of IWDG HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_IWDG_H +#define STM32H7RSxx_HAL_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup IWDG IWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Types IWDG Exported Types + * @{ + */ + +/** + * @brief IWDG Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Select the prescaler of the IWDG. + This parameter can be a value of @ref IWDG_Prescaler */ + + uint32_t Reload; /*!< Specifies the IWDG down-counter reload value. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + + uint32_t Window; /*!< Specifies the window value to be compared to the down-counter. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + + uint32_t EWI; /*!< Specifies if IWDG Early Wakeup Interrupt is enable or not and the comparator value. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF + value 0 means that EWI is disabled */ +} IWDG_InitTypeDef; + +/** + * @brief IWDG Handle Structure definition + */ +#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1) +typedef struct __IWDG_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ +{ + IWDG_TypeDef *Instance; /*!< Register base address */ + + IWDG_InitTypeDef Init; /*!< IWDG required parameters */ + +#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1) + void (* EwiCallback)(struct __IWDG_HandleTypeDef *hiwdg); /*!< IWDG Early WakeUp Interrupt callback */ + void (* MspInitCallback)(struct __IWDG_HandleTypeDef *hiwdg); /*!< IWDG Msp Init callback */ +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ +} IWDG_HandleTypeDef; + +#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1) +/** + * @brief HAL IWDG common Callback ID enumeration definition + */ +typedef enum +{ + HAL_IWDG_EWI_CB_ID = 0x00U, /*!< IWDG EWI callback ID */ + HAL_IWDG_MSPINIT_CB_ID = 0x01U, /*!< IWDG MspInit callback ID */ +} HAL_IWDG_CallbackIDTypeDef; + +/** + * @brief HAL IWDG Callback pointer definition + */ +typedef void (*pIWDG_CallbackTypeDef)(IWDG_HandleTypeDef *hppp); /*!< pointer to a IWDG common callback functions */ +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ + + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Constants IWDG Exported Constants + * @{ + */ + +/** @defgroup IWDG_Prescaler IWDG Prescaler + * @{ + */ +#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */ +#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ +#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ +#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ +#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ +#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ +#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ +#define IWDG_PRESCALER_512 (IWDG_PR_PR_2 | IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 512 */ +#define IWDG_PRESCALER_1024 IWDG_PR_PR_3 /*!< IWDG prescaler set to 1024 */ +/** + * @} + */ + +/** @defgroup IWDG_Window_option IWDG Window option + * @{ + */ +#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN +/** + * @} + */ + +/** @defgroup IWDG_EWI_Mode IWDG Early Wakeup Interrupt Mode + * @{ + */ +#define IWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */ +/** + * @} + */ + +/** @defgroup IWDG_Active_Status IWDG Active Status + * @{ + */ +#define IWDG_STATUS_DISABLE 0x00000000u +#define IWDG_STATUS_ENABLE IWDG_SR_ONF +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Macros IWDG Exported Macros + * @{ + */ + +/** + * @brief Enable the IWDG peripheral. + * @param __HANDLE__ IWDG handle + * @retval None + */ +#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) + +/** + * @brief Reload IWDG counter with value defined in the reload register + * (write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers disabled). + * @param __HANDLE__ IWDG handle + * @retval None + */ +#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Functions IWDG Exported Functions + * @{ + */ + +/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions + * @{ + */ +/* Initialization/Start functions ********************************************/ +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); +void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_IWDG_RegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID, + pIWDG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_IWDG_UnRegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions + * @{ + */ +/* I/O operation functions ****************************************************/ +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); +uint32_t HAL_IWDG_GetActiveStatus(const IWDG_HandleTypeDef *hiwdg); +void HAL_IWDG_IRQHandler(IWDG_HandleTypeDef *hiwdg); +void HAL_IWDG_EarlyWakeupCallback(IWDG_HandleTypeDef *hiwdg); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup IWDG_Private_Constants IWDG Private Constants + * @{ + */ + +/** + * @brief IWDG Key Register BitMask + */ +#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */ +#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */ +#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */ +#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup IWDG_Private_Macros IWDG Private Macros + * @{ + */ + +/** + * @brief Enable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers. + * @param __HANDLE__ IWDG handle + * @retval None + */ +#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) + +/** + * @brief Disable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers. + * @param __HANDLE__ IWDG handle + * @retval None + */ +#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) + +/** + * @brief Check IWDG prescaler value. + * @param __PRESCALER__ IWDG prescaler value + * @retval None + */ +#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ + ((__PRESCALER__) == IWDG_PRESCALER_8) || \ + ((__PRESCALER__) == IWDG_PRESCALER_16) || \ + ((__PRESCALER__) == IWDG_PRESCALER_32) || \ + ((__PRESCALER__) == IWDG_PRESCALER_64) || \ + ((__PRESCALER__) == IWDG_PRESCALER_128)|| \ + ((__PRESCALER__) == IWDG_PRESCALER_256)|| \ + ((__PRESCALER__) == IWDG_PRESCALER_512)|| \ + ((__PRESCALER__) == IWDG_PRESCALER_1024)) + +/** + * @brief Check IWDG reload value. + * @param __RELOAD__ IWDG reload value + * @retval None + */ +#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) + +/** + * @brief Check IWDG window value. + * @param __WINDOW__ IWDG window value + * @retval None + */ +#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN) + +/** + * @brief Check IWDG ewi value. + * @param __EWI__ IWDG ewi value + * @retval None + */ +#define IS_IWDG_EWI(__EWI__) ((__EWI__) <= IWDG_EWCR_EWIT) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_IWDG_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_jpeg.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_jpeg.h new file mode 100644 index 00000000000..b5a40afcecc --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_jpeg.h @@ -0,0 +1,654 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_jpeg.h + * @author MCD Application Team + * @brief Header file of JPEG HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_JPEG_H +#define STM32H7RSxx_HAL_JPEG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +#if defined (JPEG) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup JPEG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup JPEG_Exported_Types JPEG Exported Types + * @{ + */ + +/** @defgroup JPEG_Configuration_Structure_definition JPEG Configuration for encoding Structure definition + * @brief JPEG encoding configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t ColorSpace; /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK + This parameter can be a value of @ref JPEG_ColorSpace */ + + uint32_t ChromaSubsampling; /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0 + This parameter can be a value of @ref JPEG_ChromaSubsampling */ + + uint32_t ImageHeight; /*!< Image height : number of lines */ + + uint32_t ImageWidth; /*!< Image width : number of pixels per line */ + + uint32_t ImageQuality; /*!< Quality of the JPEG encoding : from 1 to 100 */ + +} JPEG_ConfTypeDef; +/** + * @} + */ + +/** @defgroup HAL_JPEG_state_structure_definition HAL JPEG state structure definition + * @brief HAL JPEG State structure definition + * @{ + */ +typedef enum +{ + HAL_JPEG_STATE_RESET = 0x00U, /*!< JPEG not yet initialized or disabled */ + HAL_JPEG_STATE_READY = 0x01U, /*!< JPEG initialized and ready for use */ + HAL_JPEG_STATE_BUSY = 0x02U, /*!< JPEG internal processing is ongoing */ + HAL_JPEG_STATE_BUSY_ENCODING = 0x03U, /*!< JPEG encoding processing is ongoing */ + HAL_JPEG_STATE_BUSY_DECODING = 0x04U, /*!< JPEG decoding processing is ongoing */ + HAL_JPEG_STATE_TIMEOUT = 0x05U, /*!< JPEG timeout state */ + HAL_JPEG_STATE_ERROR = 0x06U /*!< JPEG error state */ +} HAL_JPEG_STATETypeDef; + +/** + * @} + */ + + +/** @defgroup JPEG_handle_Structure_definition JPEG handle Structure definition + * @brief JPEG handle Structure definition + * @{ + */ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) +typedef struct __JPEG_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */ +{ + JPEG_TypeDef *Instance; /*!< JPEG peripheral register base address */ + + JPEG_ConfTypeDef Conf; /*!< Current JPEG encoding/decoding parameters */ + + uint8_t *pJpegInBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) input buffer */ + + uint8_t *pJpegOutBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) output buffer */ + + __IO uint32_t JpegInCount; /*!< Internal Counter of input data */ + + __IO uint32_t JpegOutCount; /*!< Internal Counter of output data */ + + uint32_t InDataLength; /*!< Input Buffer Length in Bytes */ + + uint32_t OutDataLength; /*!< Output Buffer Length in Bytes */ + + DMA_HandleTypeDef *hdmain; /*!< JPEG In DMA handle parameters */ + + DMA_HandleTypeDef *hdmaout; /*!< JPEG Out DMA handle parameters */ + + uint8_t CustomQuanTable; /*!< If set to 1 specify that user customized quantization tables are used */ + + uint8_t *QuantTable0; /*!< Basic Quantization Table for component 0 */ + + uint8_t *QuantTable1; /*!< Basic Quantization Table for component 1 */ + + uint8_t *QuantTable2; /*!< Basic Quantization Table for component 2 */ + + uint8_t *QuantTable3; /*!< Basic Quantization Table for component 3 */ + + HAL_LockTypeDef Lock; /*!< JPEG locking object */ + + __IO HAL_JPEG_STATETypeDef State; /*!< JPEG peripheral state */ + + __IO uint32_t ErrorCode; /*!< JPEG Error code */ + + __IO uint32_t Context; /*!< JPEG Internal context */ + +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + void (*InfoReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg, + JPEG_ConfTypeDef *pInfo); /*!< JPEG Info ready callback */ + void (*EncodeCpltCallback)(struct __JPEG_HandleTypeDef + *hjpeg); /*!< JPEG Encode complete callback */ + void (*DecodeCpltCallback)(struct __JPEG_HandleTypeDef + *hjpeg); /*!< JPEG Decode complete callback */ + void (*ErrorCallback)(struct __JPEG_HandleTypeDef + *hjpeg); /*!< JPEG Error callback */ + void (*GetDataCallback)(struct __JPEG_HandleTypeDef *hjpeg, + uint32_t NbDecodedData); /*!< JPEG Get Data callback */ + void (*DataReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, + uint32_t OutDataLength); /*!< JPEG Data ready callback */ + + void (* MspInitCallback)(struct __JPEG_HandleTypeDef *hjpeg); /*!< JPEG Msp Init callback */ + void (* MspDeInitCallback)(struct __JPEG_HandleTypeDef + *hjpeg); /*!< JPEG Msp DeInit callback */ + + +#endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */ + + +} JPEG_HandleTypeDef; +/** + * @} + */ + + +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) +/** @defgroup HAL_JPEG_Callback_ID_enumeration_definition HAL JPEG Callback ID enumeration definition + * @brief HAL JPEG Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_JPEG_ENCODE_CPLT_CB_ID = 0x01U, /*!< JPEG Encode Complete callback ID */ + HAL_JPEG_DECODE_CPLT_CB_ID = 0x02U, /*!< JPEG Decode Complete callback ID */ + HAL_JPEG_ERROR_CB_ID = 0x03U, /*!< JPEG Error callback ID */ + + HAL_JPEG_MSPINIT_CB_ID = 0x04U, /*!< JPEG MspInit callback ID */ + HAL_JPEG_MSPDEINIT_CB_ID = 0x05U /*!< JPEG MspDeInit callback ID */ + +} HAL_JPEG_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_JPEG_Callback_pointer_definition HAL JPEG Callback pointer definition + * @brief HAL JPEG Callback pointer definition + * @{ + */ +typedef void (*pJPEG_CallbackTypeDef)(JPEG_HandleTypeDef *hjpeg); /*!< pointer to a common JPEG callback function */ +typedef void (*pJPEG_InfoReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, + JPEG_ConfTypeDef *pInfo); /*!< pointer to an Info ready JPEG callback function */ +typedef void (*pJPEG_GetDataCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, + uint32_t NbDecodedData); /*!< pointer to a Get data JPEG callback function */ +typedef void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, + uint32_t OutDataLength); /*!< pointer to a Data ready JPEG callback function */ +/** + * @} + */ + +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup JPEG_Exported_Constants JPEG Exported Constants + * @{ + */ + +/** @defgroup JPEG_Error_Code_definition JPEG Error Code definition + * @brief JPEG Error Code definition + * @{ + */ + +#define HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U) /*!< HUffman Table programming error */ +#define HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U) /*!< Quantization Table programming error */ +#define HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ +#define HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U) /*!< Timeout error */ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) +#define HAL_JPEG_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup JPEG_Quantization_Table_Size JPEG Quantization Table Size + * @brief JPEG Quantization Table Size + * @{ + */ +#define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U) /*!< JPEG Quantization Table Size in bytes */ +/** + * @} + */ + + +/** @defgroup JPEG_ColorSpace JPEG ColorSpace + * @brief JPEG Color Space + * @{ + */ +#define JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U) +#define JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0 +#define JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE + + +/** + * @} + */ + + +/** @defgroup JPEG_ChromaSubsampling JPEG Chrominance Sampling + * @brief JPEG Chrominance Sampling + * @{ + */ +#define JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U) /*!< Chroma Subsampling 4:4:4 */ +#define JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U) /*!< Chroma Subsampling 4:2:0 */ +#define JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U) /*!< Chroma Subsampling 4:2:2 */ + +/** + * @} + */ + +/** @defgroup JPEG_ImageQuality JPEG Image Quality + * @brief JPEG Min and Max Image Quality + * @{ + */ +#define JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U) /*!< Minimum JPEG quality */ +#define JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U) /*!< Maximum JPEG quality */ + +/** + * @} + */ + +/** @defgroup JPEG_Interrupt_configuration_definition JPEG Interrupt configuration definition + * @brief JPEG Interrupt definition + * @{ + */ +#define JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE) /*!< Input FIFO Threshold Interrupt */ +#define JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE) /*!< Input FIFO Not Full Interrupt */ +#define JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Threshold Interrupt */ +#define JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Not Empty Interrupt */ +#define JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE) /*!< End of Conversion Interrupt */ +#define JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE) /*!< Header Parsing Done Interrupt */ +/** + * @} + */ + +/** @defgroup JPEG_Flag_definition JPEG Flag definition + * @brief JPEG Flags definition + * @{ + */ +#define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF) /*!< Input FIFO is not full and is below its threshold flag */ +#define JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF) /*!< Input FIFO Not Full Flag, a data can be written */ +#define JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF) /*!< Output FIFO is not empty and has reach its threshold */ +#define JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF) /*!< Output FIFO is not empty, a data is available */ +#define JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF) /*!< JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */ +#define JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF) /*!< JPEG Codec has finished the parsing of the headers and the internal registers have been updated */ +#define JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF) /*!< JPEG Codec operation on going flag*/ + +#define JPEG_FLAG_ALL ((uint32_t)0x000000FEU) /*!< JPEG Codec All previous flag*/ +/** + * @} + */ + +/** @defgroup JPEG_PROCESS_PAUSE_RESUME_definition JPEG Process Pause Resume definition + * @brief JPEG process pause, resume definition + * @{ + */ +#define JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U) /*!< Pause/Resume Input FIFO Xfer*/ +#define JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U) /*!< Pause/Resume Output FIFO Xfer*/ +#define JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U) /*!< Pause/Resume Input and Output FIFO Xfer*/ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup JPEG_Exported_Macros JPEG Exported Macros + * @{ + */ + +/** @brief Reset JPEG handle state + * @param __HANDLE__ specifies the JPEG handle. + * @retval None + */ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) +#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_JPEG_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0) +#else +#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET) +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + +/** + * @brief Enable the JPEG peripheral. + * @param __HANDLE__ specifies the JPEG handle. + * @retval None + */ +#define __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN) + +/** + * @brief Disable the JPEG peripheral. + * @param __HANDLE__ specifies the JPEG handle. + * @retval None + */ +#define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN) + + +/** + * @brief Check the specified JPEG status flag. + * @param __HANDLE__ specifies the JPEG handle. + * @param __FLAG__ specifies the flag to check + * This parameter can be one of the following values: + * @arg JPEG_FLAG_IFTF : The input FIFO is not full and is below its threshold flag + * @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written + * @arg JPEG_FLAG_OFTF : The output FIFO is not empty and has reach its threshold + * @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available + * @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process + * and than last data has been sent to the output FIFO + * @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers + * and the internal registers have been updated + * @arg JPEG_FLAG_COF : JPEG Codec operation on going flag + * + * @retval __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE) + */ + +#define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__))) + +/** + * @brief Clear the specified JPEG status flag. + * @param __HANDLE__ specifies the JPEG handle. + * @param __FLAG__ specifies the flag to clear + * This parameter can be one of the following values: + * @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process + * and than last data has been sent to the output FIFO + * @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers + * @retval None + */ + +#define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->CFR |= ((__FLAG__) &\ + (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF)))) + + +/** + * @brief Enable Interrupt. + * @param __HANDLE__ specifies the JPEG handle. + * @param __INTERRUPT__ specifies the interrupt to enable + * This parameter can be one of the following values: + * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt + * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt + * @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt + * @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt + * @arg JPEG_IT_EOC : End of Conversion Interrupt + * @arg JPEG_IT_HPD : Header Parsing Done Interrupt + * + * @retval No return + */ +#define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) ) + +/** + * @brief Disable Interrupt. + * @param __HANDLE__ specifies the JPEG handle. + * @param __INTERRUPT__ specifies the interrupt to disable + * This parameter can be one of the following values: + * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt + * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt + * @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt + * @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt + * @arg JPEG_IT_EOC : End of Conversion Interrupt + * @arg JPEG_IT_HPD : Header Parsing Done Interrupt + * + * @note To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits + * located in the same IT enable register (CR register). + * @retval No return + */ +#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0UL) + + +/** + * @brief Get Interrupt state. + * @param __HANDLE__ specifies the JPEG handle. + * @param __INTERRUPT__ specifies the interrupt to check + * This parameter can be one of the following values: + * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt + * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt + * @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt + * @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt + * @arg JPEG_IT_EOC : End of Conversion Interrupt + * @arg JPEG_IT_HPD : Header Parsing Done Interrupt + * + * @retval returns The new state of __INTERRUPT__ (Enabled or disabled) + */ +#define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup JPEG_Exported_Functions + * @{ + */ + +/** @addtogroup JPEG_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg); +HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg); +void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg); +void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg); + +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_JPEG_RegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID, + pJPEG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_JPEG_UnRegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_JPEG_RegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg, + pJPEG_InfoReadyCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_JPEG_UnRegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg); + +HAL_StatusTypeDef HAL_JPEG_RegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_JPEG_UnRegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg); + +HAL_StatusTypeDef HAL_JPEG_RegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg, + pJPEG_DataReadyCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg); + +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup JPEG_Exported_Functions_Group2 + * @{ + */ +/* Encoding/Decoding Configuration functions ********************************/ +HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, const JPEG_ConfTypeDef *pConf); +HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo); +HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg); +HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg); +HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, + uint8_t *QTable2, uint8_t *QTable3); + +/** + * @} + */ + +/** @addtogroup JPEG_Exported_Functions_Group3 + * @{ + */ +/* JPEG processing functions **************************************/ +HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, + uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout); +HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, + uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout); +HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, + uint8_t *pDataOut, uint32_t OutDataLength); +HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, + uint8_t *pDataOutMCU, uint32_t OutDataLength); +HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, + uint8_t *pDataOut, uint32_t OutDataLength); +HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, + uint8_t *pDataOutMCU, uint32_t OutDataLength); +HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection); +HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection); +void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength); +void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength); +HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg); + +/** + * @} + */ + +/** @addtogroup JPEG_Exported_Functions_Group4 + * @{ + */ +/* JPEG Decode/Encode callback functions ********************************************************/ +void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo); +void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg); +void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg); +void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg); +void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData); +void HAL_JPEG_DataReadyCallback(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength); + +/** + * @} + */ + +/** @addtogroup JPEG_Exported_Functions_Group5 + * @{ + */ +/* JPEG IRQ handler management ******************************************************/ +void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg); + +/** + * @} + */ + +/** @addtogroup JPEG_Exported_Functions_Group6 + * @{ + */ +/* Peripheral State and Error functions ************************************************/ +HAL_JPEG_STATETypeDef HAL_JPEG_GetState(const JPEG_HandleTypeDef *hjpeg); +uint32_t HAL_JPEG_GetError(const JPEG_HandleTypeDef *hjpeg); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup JPEG_Private_Types JPEG Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup JPEG_Private_Defines JPEG Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup JPEG_Private_Variables JPEG Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup JPEG_Private_Constants JPEG Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup JPEG_Private_Macros JPEG Private Macros + * @{ + */ + +#define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \ + ((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \ + ((SUBSAMPLING) == JPEG_422_SUBSAMPLING)) + +#define IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX)) + +#define IS_JPEG_COLORSPACE(COLORSPACE) (((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \ + ((COLORSPACE) == JPEG_YCBCR_COLORSPACE) || \ + ((COLORSPACE) == JPEG_CMYK_COLORSPACE)) + +#define IS_JPEG_PAUSE_RESUME_STATE(VALUE) (((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \ + ((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \ + ((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT)) + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup JPEG_Private_Functions_Prototypes JPEG Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup JPEG_Private_Functions JPEG Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* JPEG */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_JPEG_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_lptim.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_lptim.h new file mode 100644 index 00000000000..a230e748502 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_lptim.h @@ -0,0 +1,1259 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_lptim.h + * @author MCD Application Team + * @brief Header file of LPTIM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_LPTIM_H +#define STM32H7RSxx_HAL_LPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/* Include low level driver */ +#include "stm32h7rsxx_ll_lptim.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5) + +/** @addtogroup LPTIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Types LPTIM Exported Types + * @{ + */ +#define LPTIM_EXTI_LINE_LPTIM1 EXTI_IMR2_IM47 /*!< External interrupt line 47 Connected to the LPTIM1 EXTI Line */ +#define LPTIM_EXTI_LINE_LPTIM2 EXTI_IMR2_IM48 /*!< External interrupt line 48 Connected to the LPTIM2 EXTI Line */ +#define LPTIM_EXTI_LINE_LPTIM3 EXTI_IMR2_IM50 /*!< External interrupt line 50 Connected to the LPTIM3 EXTI Line */ +#define LPTIM_EXTI_LINE_LPTIM4 EXTI_IMR2_IM52 /*!< External interrupt line 52 Connected to the LPTIM4 EXTI Line */ +#define LPTIM_EXTI_LINE_LPTIM5 EXTI_IMR2_IM53 /*!< External interrupt line 53 Connected to the LPTIM5 EXTI Line */ + +/** + * @brief LPTIM Clock configuration definition + */ +typedef struct +{ + uint32_t Source; /*!< Selects the clock source. + This parameter can be a value of @ref LPTIM_Clock_Source */ + + uint32_t Prescaler; /*!< Specifies the counter clock Prescaler. + This parameter can be a value of @ref LPTIM_Clock_Prescaler */ + +} LPTIM_ClockConfigTypeDef; + +/** + * @brief LPTIM Clock configuration definition + */ +typedef struct +{ + uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit + if the ULPTIM input is selected. + Note: This parameter is used only when Ultra low power clock source is used. + Note: If the polarity is configured on 'both edges', an auxiliary clock + (one of the Low power oscillator) must be active. + This parameter can be a value of @ref LPTIM_Clock_Polarity */ + + uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter. + Note: This parameter is used only when Ultra low power clock source is used. + This parameter can be a value of @ref LPTIM_Clock_Sample_Time */ + +} LPTIM_ULPClockConfigTypeDef; + +/** + * @brief LPTIM Trigger configuration definition + */ +typedef struct +{ + uint32_t Source; /*!< Selects the Trigger source. + This parameter can be a value of @ref LPTIM_Trigger_Source */ + + uint32_t ActiveEdge; /*!< Selects the Trigger active edge. + Note: This parameter is used only when an external trigger is used. + This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */ + + uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter. + Note: This parameter is used only when an external trigger is used. + This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */ +} LPTIM_TriggerConfigTypeDef; + +/** + * @brief LPTIM Initialization Structure definition + */ +typedef struct +{ + LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ + + LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */ + + LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between + Min_Data = 0x0001 and Max_Data = 0xFFFF. */ + + uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare + values is done immediately or after the end of current period. + This parameter can be a value of @ref LPTIM_Updating_Mode */ + + uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event + or each external event. + This parameter can be a value of @ref LPTIM_Counter_Source */ + + uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output). + This parameter can be a value of @ref LPTIM_Input1_Source */ + + uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output). + Note: This parameter is used only for encoder feature so is used only + for LPTIM1 instance. + This parameter can be a value of @ref LPTIM_Input2_Source */ + + uint32_t RepetitionCounter;/*!< Specifies the repetition counter value. + Each time the RCR downcounter reaches zero, an update event is + generated and counting restarts from the RCR value (N). + Note: When using repetition counter the UpdateMode field must be + set to LPTIM_UPDATE_ENDOFPERIOD otherwise unpredictable + behavior may occur. + This parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. */ +} LPTIM_InitTypeDef; + +/** + * @brief LPTIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref LPTIM_Output_Compare_Polarity */ +} LPTIM_OC_ConfigTypeDef; + +/** + * @brief LPTIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICInputSource; /*!< Specifies source selected for IC channel. + This parameter can be a value of @ref LPTIM_Input_Capture_Source */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref LPTIM_Input_Capture_Prescaler */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref LPTIM_Input_Capture_Polarity */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a value of @ref LPTIM_Input_Capture_Filter */ +} LPTIM_IC_ConfigTypeDef; + +/** + * @brief HAL LPTIM State structure definition + */ +typedef enum +{ + HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */ +} HAL_LPTIM_StateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_LPTIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_LPTIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_LPTIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_LPTIM_ActiveChannel; + +/** + * @brief LPTIM Channel States definition + */ +typedef enum +{ + HAL_LPTIM_CHANNEL_STATE_RESET = 0x00U, /*!< LPTIM Channel initial state */ + HAL_LPTIM_CHANNEL_STATE_READY = 0x01U, /*!< LPTIM Channel ready for use */ + HAL_LPTIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the LPTIM channel */ +} HAL_LPTIM_ChannelStateTypeDef; + +/** + * @brief LPTIM handle Structure definition + */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +typedef struct __LPTIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +{ + LPTIM_TypeDef *Instance; /*!< Register base address */ + + LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */ + + HAL_LPTIM_ActiveChannel Channel; /*!< Active channel */ + + DMA_HandleTypeDef *hdma[3]; /*!< DMA Handlers array, This array is accessed by a @ref LPTIM_DMA_Handle_index */ + + HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */ + + HAL_LockTypeDef Lock; /*!< LPTIM locking object */ + + __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ + + __IO HAL_LPTIM_ChannelStateTypeDef ChannelState[2]; /*!< LPTIM channel operation state */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */ + void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */ + void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */ + void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */ + void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */ + void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */ + void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */ + void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */ + void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */ + void (* UpdateEventCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Update event detection Callback */ + void (* RepCounterWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Repetition counter register write complete Callback */ + void (* UpdateEventHalfCpltCallback)(struct __LPTIM_HandleTypeDef *hlptim);/*!< Update event half complete detection Callback */ + void (* ErrorCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Error Callback */ + void (* IC_CaptureCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Input capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __LPTIM_HandleTypeDef *htim); /*!< Input Capture half complete Callback */ + void (* IC_OverCaptureCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Over capture Callback */ +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +} LPTIM_HandleTypeDef; + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL LPTIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */ + HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */ + HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */ + HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */ + HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */ + HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */ + HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */ + HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */ + HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */ + HAL_LPTIM_UPDATE_EVENT_CB_ID = 0x09U, /*!< Update event detection Callback ID */ + HAL_LPTIM_REP_COUNTER_WRITE_CB_ID = 0x0AU, /*!< Repetition counter register write complete Callback ID */ + HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID = 0x0BU, /*!< Update event half complete detection Callback ID */ + HAL_LPTIM_ERROR_CB_ID = 0x0CU, /*!< LPTIM Error Callback ID */ + HAL_LPTIM_IC_CAPTURE_CB_ID = 0x0DU, /*!< Input capture Callback ID */ + HAL_LPTIM_IC_CAPTURE_HALF_CB_ID = 0x0EU, /*!< Input capture half complete Callback ID */ + HAL_LPTIM_OVER_CAPTURE_CB_ID = 0x0FU, /*!< Over capture Callback ID */ +} HAL_LPTIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */ + +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants + * @{ + */ + +/** @defgroup LPTIM_Clock_Source LPTIM Clock Source + * @{ + */ +#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U +#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL +/** + * @} + */ + +/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler + * @{ + */ +#define LPTIM_PRESCALER_DIV1 0x00000000U +#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 +#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 +#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1) +#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 +#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2) +#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2) +#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC +/** + * @} + */ + +/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time + * @{ + */ +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U +#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0 +#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1 +#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT +/** + * @} + */ + +/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity + * @{ + */ +#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U +#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0 +#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 +/** + * @} + */ + +/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source + * @{ + */ +#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU +#define LPTIM_TRIGSOURCE_0 0x00000000U +#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0 +#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1 +#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1) +#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2 +#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2) +#define LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2) +#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL +/** + * @} + */ + +/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity + * @{ + */ +#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0 +#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1 +#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN +/** + * @} + */ + +/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time + * @{ + */ +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U +#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0 +#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1 +#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT +/** + * @} + */ + +/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode + * @{ + */ + +#define LPTIM_UPDATE_IMMEDIATE 0x00000000U +#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD +/** + * @} + */ + +/** @defgroup LPTIM_Counter_Source LPTIM Counter Source + * @{ + */ + +#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U +#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE +/** + * @} + */ + +/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source + * @{ + */ + +#define LPTIM_INPUT1SOURCE_GPIO 0x00000000UL /*!< For LPTIM1 and LPTIM2 */ +/** + * @} + */ + +/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source + * @{ + */ + +#define LPTIM_INPUT2SOURCE_GPIO 0x00000000UL /*!< For LPTIM1 and LPTIM2 */ +/** + * @} + */ + +/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition + * @{ + */ + +#define LPTIM_FLAG_CC1O LPTIM_ISR_CC1OF +#define LPTIM_FLAG_CC2O LPTIM_ISR_CC2OF +#define LPTIM_FLAG_CC1 LPTIM_ISR_CC1IF +#define LPTIM_FLAG_CC2 LPTIM_ISR_CC2IF +#define LPTIM_FLAG_CMP1OK LPTIM_ISR_CMP1OK +#define LPTIM_FLAG_CMP2OK LPTIM_ISR_CMP2OK +#define LPTIM_FLAG_DIEROK LPTIM_ISR_DIEROK +#define LPTIM_FLAG_REPOK LPTIM_ISR_REPOK +#define LPTIM_FLAG_UPDATE LPTIM_ISR_UE +#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN +#define LPTIM_FLAG_UP LPTIM_ISR_UP +#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK +#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG +#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM +/** + * @} + */ + +/** @defgroup LPTIM_DMA_sources LPTIM DMA Sources + * @{ + */ +#define LPTIM_DMA_UPDATE LPTIM_DIER_UEDE /*!< DMA request is triggered by the update event */ +#define LPTIM_DMA_CC1 LPTIM_DIER_CC1DE /*!< DMA request is triggered by the capture 1 event */ +#define LPTIM_DMA_CC2 LPTIM_DIER_CC2DE /*!< DMA request is triggered by the capture 2 event */ + +/** + * @} + */ + +/** @defgroup LPTIM_DMA_Handle_index LPTIM DMA Handle Index + * @{ + */ +#define LPTIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define LPTIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Update event 1 DMA request */ +#define LPTIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Update event 2 DMA request */ +/** + * @} + */ + +/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition + * @{ + */ +#define LPTIM_IT_CC1O LPTIM_DIER_CC1OIE +#define LPTIM_IT_CC2O LPTIM_DIER_CC2OIE +#define LPTIM_IT_CC1 LPTIM_DIER_CC1IE +#define LPTIM_IT_CC2 LPTIM_DIER_CC2IE +#define LPTIM_IT_CMP1OK LPTIM_DIER_CMP1OKIE +#define LPTIM_IT_CMP2OK LPTIM_DIER_CMP2OKIE +#define LPTIM_IT_REPOK LPTIM_DIER_REPOKIE +#define LPTIM_IT_UPDATE LPTIM_DIER_UEIE +#define LPTIM_IT_DOWN LPTIM_DIER_DOWNIE +#define LPTIM_IT_UP LPTIM_DIER_UPIE +#define LPTIM_IT_ARROK LPTIM_DIER_ARROKIE +#define LPTIM_IT_EXTTRIG LPTIM_DIER_EXTTRIGIE +#define LPTIM_IT_ARRM LPTIM_DIER_ARRMIE +/** + * @} + */ + +/** @defgroup LPTIM_Channel LPTIM Channel + * @{ + */ +#define LPTIM_CHANNEL_1 LL_LPTIM_CHANNEL_CH1 /*!< Capture/compare channel 1 identifier */ +#define LPTIM_CHANNEL_2 LL_LPTIM_CHANNEL_CH2 /*!< Capture/compare channel 2 identifier */ +/** + * @} + */ + +/** @defgroup LPTIM_Output_Compare_Polarity LPTIM Output Compare Polarity + * @{ + */ +#define LPTIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define LPTIM_OCPOLARITY_LOW 0x00000001U /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup LPTIM_Input_Capture_Prescaler LPTIM Input Capture Prescaler + * @{ + */ +#define LPTIM_ICPSC_DIV1 0x00000000UL /*!< Capture performed each time an edge is detected on the capture input */ +#define LPTIM_ICPSC_DIV2 LPTIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define LPTIM_ICPSC_DIV4 LPTIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define LPTIM_ICPSC_DIV8 (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup LPTIM_Input_Capture_Polarity LPTIM Input Capture Polarity + * @{ + */ +#define LPTIM_ICPOLARITY_RISING 0x00000000UL /*!< Capture/Compare input rising polarity */ +#define LPTIM_ICPOLARITY_FALLING LPTIM_CCMR1_CC1P_0 /*!< Capture/Compare input falling polarity */ +#define LPTIM_ICPOLARITY_RISING_FALLING (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1) /*!< Capture/Compare input rising and falling polarities */ +/** + * @} + */ + +/** @defgroup LPTIM_Input_Capture_Filter LPTIM Input Capture Filter + * @{ + */ +#define LPTIM_ICFLT_CLOCK_DIV1 0x00000000UL /*!< any external input capture signal level change is considered as a valid transition */ +#define LPTIM_ICFLT_CLOCK_DIV2 LPTIM_CCMR1_IC1F_0 /*!< external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition */ +#define LPTIM_ICFLT_CLOCK_DIV4 LPTIM_CCMR1_IC1F_1 /*!< external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition */ +#define LPTIM_ICFLT_CLOCK_DIV8 (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1) /*!< external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition */ +/** + * @} + */ + +/** @defgroup LPTIM_Input_Capture_Source LPTIM Input Capture Source + * @{ + */ +#define LPTIM_IC1SOURCE_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2 and LPTIM3 */ +#define LPTIM_IC2SOURCE_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2 and LPTIM3 */ +#define LPTIM_IC2SOURCE_LSI LPTIM_CFGR2_IC2SEL_0 /*!< For LPTIM1 */ +#define LPTIM_IC2SOURCE_LSE LPTIM_CFGR2_IC2SEL_1 /*!< For LPTIM1 */ +#define LPTIM_IC2SOURCE_HSI_1024 LPTIM_CFGR2_IC2SEL_0 /*!< For LPTIM2 */ +#define LPTIM_IC2SOURCE_CSI_128 LPTIM_CFGR2_IC2SEL_1 /*!< For LPTIM2 */ +/** + * @} + */ +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros + * @{ + */ + +/** @brief Reset LPTIM handle state. + * @param __HANDLE__ LPTIM handle + * @retval None + */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_LPTIM_CHANNEL_STATE_RESET;\ + (__HANDLE__)->ChannelState[1] = HAL_LPTIM_CHANNEL_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_LPTIM_CHANNEL_STATE_RESET;\ + (__HANDLE__)->ChannelState[1] = HAL_LPTIM_CHANNEL_STATE_RESET;\ + } while(0) +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the LPTIM peripheral. + * @param __HANDLE__ LPTIM handle + * @retval None + */ +#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE)) + +/** + * @brief Disable the LPTIM peripheral. + * @param __HANDLE__ LPTIM handle + * @retval None + */ +#define __HAL_LPTIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCMR1 & LPTIM_CCMR1_CC1E) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCMR1 & LPTIM_CCMR1_CC2E) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE); \ + } \ + } \ + } while(0) + +/** + * @brief Start the LPTIM peripheral in Continuous mode. + * @param __HANDLE__ LPTIM handle + * @retval None + */ +#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT) +/** + * @brief Start the LPTIM peripheral in single mode. + * @param __HANDLE__ LPTIM handle + * @retval None + */ +#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT) + +/** + * @brief Reset the LPTIM Counter register in synchronous mode. + * @param __HANDLE__ LPTIM handle + * @retval None + */ +#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST) + +/** + * @brief Reset after read of the LPTIM Counter register in asynchronous mode. + * @param __HANDLE__ LPTIM handle + * @retval None + */ +#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE) + +/** + * @brief Write the passed parameter in the Autoreload register. + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Autoreload value + * @retval None + * @note The ARR register can only be modified when the LPTIM instance is enabled. + */ +#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__)) + +/** + * @brief Write the passed parameter in the Compare register. + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Compare value + * @param __CHANNEL__ TIM Channel to be configured + * @retval None + * @note The CCRx registers can only be modified when the LPTIM instance is enabled. + */ +#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __CHANNEL__, __VALUE__) \ + (((__CHANNEL__) == LPTIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__VALUE__)) :\ + ((__CHANNEL__) == LPTIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__VALUE__)) : 0U) + +/** + * @brief Write the passed parameter in the Repetition register. + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Repetition value + * @retval None + */ +#define __HAL_LPTIM_REPETITIONCOUNTER_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->RCR = (__VALUE__)) + +/** + * @brief Return the current Repetition value. + * @param __HANDLE__ LPTIM handle + * @retval Repetition register value + * @note The RCR register can only be modified when the LPTIM instance is enabled. + */ +#define __HAL_LPTIM_REPETITIONCOUNTER_GET(__HANDLE__) ((__HANDLE__)->Instance->RCR) + +/** + * @brief Enable the LPTIM signal input/output on the corresponding pin. + * @param __HANDLE__ LPTIM handle + * @param __CHANNEL__ LPTIM Channels to be enabled. + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval None + */ +#define __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(__HANDLE__, __CHANNEL__) \ + do { \ + switch (__CHANNEL__) \ + { \ + case LPTIM_CHANNEL_1: \ + ((__HANDLE__)->Instance->CCMR1 |= LPTIM_CCMR1_CC1E); \ + break; \ + case LPTIM_CHANNEL_2: \ + ((__HANDLE__)->Instance->CCMR1 |= LPTIM_CCMR1_CC2E); \ + break; \ + default: \ + break; \ + } \ + } \ + while(0) + +/** + * @brief Disable the LPTIM signal input/output on the corresponding pin. + * @param __HANDLE__ LPTIM handle + * @param __CHANNEL__ LPTIM Channels to be disabled. + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval None + */ +#define __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(__HANDLE__, __CHANNEL__) \ + do { \ + switch (__CHANNEL__) \ + { \ + case LPTIM_CHANNEL_1: \ + ((__HANDLE__)->Instance->CCMR1 &= ~LPTIM_CCMR1_CC1E); \ + break; \ + case LPTIM_CHANNEL_2: \ + ((__HANDLE__)->Instance->CCMR1 &= ~LPTIM_CCMR1_CC2E); \ + break; \ + default: \ + break; \ + } \ + } \ + while(0) + +/** + * @brief Check whether the specified LPTIM flag is set or not. + * @param __HANDLE__ LPTIM handle + * @param __FLAG__ LPTIM flag to check + * This parameter can be a value of: + * @arg LPTIM_FLAG_REPOK : Repetition register update OK Flag. + * @arg LPTIM_FLAG_UPDATE : Update event Flag. + * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. + * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. + * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. + * @arg LPTIM_FLAG_CMP1OK : Compare register 1 update OK Flag. + * @arg LPTIM_FLAG_CMP2OK : Compare register 2 update OK Flag. + * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag. + * @arg LPTIM_FLAG_ARRM : Autoreload match Flag. + * @arg LPTIM_FLAG_CC1 : Capture/Compare 1 interrupt flag. + * @arg LPTIM_FLAG_CC2 : Capture/Compare 2 interrupt flag. + * @arg LPTIM_FLAG_CC1O : Capture/Compare 1 over-capture flag. + * @arg LPTIM_FLAG_CC2O : Capture/Compare 2 over-capture flag. + * @arg LPTIM_FLAG_DIEROK : DMA & interrupt enable update OK flag. + * @retval The state of the specified flag (SET or RESET). + */ +#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the specified LPTIM flag. + * @param __HANDLE__ LPTIM handle. + * @param __FLAG__ LPTIM flag to clear. + * This parameter can be a value of: + * @arg LPTIM_FLAG_REPOK : Repetition register update OK Flag. + * @arg LPTIM_FLAG_UPDATE : Update event Flag. + * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. + * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. + * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. + * @arg LPTIM_FLAG_CMP1OK : Compare register 1 update OK Flag. + * @arg LPTIM_FLAG_CMP2OK : Compare register 2 update OK Flag. + * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag. + * @arg LPTIM_FLAG_ARRM : Autoreload match Flag. + * @arg LPTIM_FLAG_CC1 : Capture/Compare 1 interrupt flag. + * @arg LPTIM_FLAG_CC2 : Capture/Compare 2 interrupt flag. + * @arg LPTIM_FLAG_CC1O : Capture/Compare 1 over-capture flag. + * @arg LPTIM_FLAG_CC2O : Capture/Compare 2 over-capture flag. + * @arg LPTIM_FLAG_DIEROK : DMA & interrupt enable update OK flag. + * @retval None. + */ +#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** + * @brief Enable the specified LPTIM interrupt. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to set. + * This parameter can be a value of: + * @arg LPTIM_IT_REPOK : Repetition register update OK Interrupt. + * @arg LPTIM_IT_UPDATE : Update event register Interrupt. + * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. + * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. + * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. + * @arg LPTIM_IT_CMP1OK : Compare register 1 update OK Interrupt. + * @arg LPTIM_IT_CMP2OK : Compare register 2 update OK Interrupt. + * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. + * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. + * @arg LPTIM_IT_CC1 : Capture/Compare 1 interrupt Interrupt. + * @arg LPTIM_IT_CC2 : Capture/Compare 2 interrupt Interrupt. + * @arg LPTIM_IT_CC1O : Capture/Compare 1 over-capture Interrupt. + * @arg LPTIM_IT_CC2O : Capture/Compare 2 over-capture Interrupt. + * @retval None. + * @note The LPTIM interrupts can only be enabled when the LPTIM instance is enabled. + */ +#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** + * @brief Disable the specified LPTIM interrupt. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to set. + * This parameter can be a value of: + * @arg LPTIM_IT_REPOK : Repetition register update OK Interrupt. + * @arg LPTIM_IT_UPDATE : Update event register Interrupt. + * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. + * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. + * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. + * @arg LPTIM_IT_CMP1OK : Compare register 1 update OK Interrupt. + * @arg LPTIM_IT_CMP2OK : Compare register 2 update OK Interrupt. + * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. + * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. + * @arg LPTIM_IT_CC1 : Capture/Compare 1 interrupt Interrupt. + * @arg LPTIM_IT_CC2 : Capture/Compare 2 interrupt Interrupt. + * @arg LPTIM_IT_CC1O : Capture/Compare 1 over-capture Interrupt. + * @arg LPTIM_IT_CC2O : Capture/Compare 2 over-capture Interrupt. + * @retval None. + * @note The LPTIM interrupts can only be disabled when the LPTIM instance is enabled. + */ +#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= (~(__INTERRUPT__))) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the LPTIM DMA request to enable. + * This parameter can be one of the following values: + * @arg LPTIM_DMA_UPDATE: Update DMA request + * @arg LPTIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg LPTIM_DMA_CC2: Capture/Compare 2 DMA request + * @retval None + */ +#define __HAL_LPTIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the LPTIM Handle. + * @param __DMA__ specifies the LPTIM DMA request to disable. + * This parameter can be one of the following values: + * @arg LPTIM_DMA_UPDATE: Update DMA request + * @arg LPTIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg LPTIM_DMA_CC2: Capture/Compare 2 DMA request + * @retval None + */ +#define __HAL_LPTIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** + * @brief Check whether the specified LPTIM interrupt source is enabled or not. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to check. + * This parameter can be a value of: + * @arg LPTIM_IT_REPOK : Repetition register update OK Interrupt. + * @arg LPTIM_IT_UPDATE : Update event register Interrupt. + * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. + * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. + * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. + * @arg LPTIM_IT_CMP1OK : Compare register 1 update OK Interrupt. + * @arg LPTIM_IT_CMP2OK : Compare register 2 update OK Interrupt. + * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. + * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. + * @arg LPTIM_IT_CC1 : Capture/Compare 1 interrupt Interrupt. + * @arg LPTIM_IT_CC2 : Capture/Compare 2 interrupt Interrupt. + * @arg LPTIM_IT_CC1O : Capture/Compare 1 over-capture Interrupt. + * @arg LPTIM_IT_CC2O : Capture/Compare 2 over-capture Interrupt. + * @retval Interrupt status. + */ + +#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Enable the LPTIM1 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->IMR2 |= LPTIM_EXTI_LINE_LPTIM1) + +/** + * @brief Disable the LPTIM1 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR2\ + &= ~(LPTIM_EXTI_LINE_LPTIM1)) + +/** + * @brief Enable the LPTIM2 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->IMR2 |= LPTIM_EXTI_LINE_LPTIM2) + +/** + * @brief Disable the LPTIM2 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR2\ + &= ~(LPTIM_EXTI_LINE_LPTIM2)) + +/** + * @brief Enable the LPTIM3 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT() (EXTI->IMR2 |= LPTIM_EXTI_LINE_LPTIM3) + +/** + * @brief Disable the LPTIM3 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT() (EXTI->IMR2\ + &= ~(LPTIM_EXTI_LINE_LPTIM3)) + +/** + * @brief Enable the LPTIM4 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM4_EXTI_ENABLE_IT() (EXTI->IMR2 |= LPTIM_EXTI_LINE_LPTIM4) + +/** + * @brief Disable the LPTIM4 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM4_EXTI_DISABLE_IT() (EXTI->IMR2\ + &= ~(LPTIM_EXTI_LINE_LPTIM4)) + +/** + * @brief Enable the LPTIM5 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM5_EXTI_ENABLE_IT() (EXTI->IMR2 |= LPTIM_EXTI_LINE_LPTIM5) + +/** + * @brief Disable the LPTIM5 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_LPTIM_LPTIM5_EXTI_DISABLE_IT() (EXTI->IMR2\ + &= ~(LPTIM_EXTI_LINE_LPTIM5)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions + * @{ + */ + +/** @addtogroup LPTIM_Exported_Functions_Group1 + * @brief Initialization and Configuration functions. + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); + +/* MSP functions *************************************************************/ +void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); +/** + * @} + */ + +/** @addtogroup LPTIM_Exported_Functions_Group2 + * @brief Start-Stop operation functions. + * @{ + */ +/* Config functions **********************************************************/ +HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig, + uint32_t Channel); + +/* Start/Stop operation functions *********************************************/ +/* ################################# PWM Mode ################################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, const uint32_t *pData, + uint32_t Length); +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); + +/* ############################# One Pulse Mode ##############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); + +/* ############################## Set once Mode ##############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); + +/* ############################### Encoder Mode ##############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim); + +/* ############################# Time out Mode ##############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout); +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout); +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim); + +/* ############################## Counter Mode ###############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); + +/* ############################## Input Capture Mode ###############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData, + uint32_t Length); +HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup LPTIM_Exported_Functions_Group3 + * @brief Read operation functions. + * @{ + */ +/* Reading operation functions ************************************************/ +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +uint8_t HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup LPTIM_Exported_Functions_Group4 + * @brief LPTIM IRQ handler and callback functions. + * @{ + */ +/* LPTIM IRQ functions *******************************************************/ +void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim); + +/* CallBack functions ********************************************************/ +void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef *hlptim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, + pLPTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup LPTIM_Group5 + * @brief Peripheral State functions. + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Types LPTIM Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Variables LPTIM Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Constants LPTIM Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Macros LPTIM Private Macros + * @{ + */ + +#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \ + ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)) + + +#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV128)) + +#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1) +#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \ + ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \ + ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \ + ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS)) + +#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING)) + +#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_7)) + +#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \ + ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \ + ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING )) + +#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \ + ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \ + ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \ + ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS )) + +#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \ + ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD)) + +#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ + ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) + +#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\ + ((__AUTORELOAD__) <= 0x0000FFFFUL)) + +#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) + +#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ + ((__PERIOD__) <= 0x0000FFFFUL)) + +#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL) + +#define IS_LPTIM_OC_POLARITY(__OCPOLARITY__) (((__OCPOLARITY__) == LPTIM_OCPOLARITY_LOW) || \ + ((__OCPOLARITY__) == LPTIM_OCPOLARITY_HIGH)) +#define IS_LPTIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_ICPSC_DIV1) ||\ + ((__PRESCALER__) == LPTIM_ICPSC_DIV2) ||\ + ((__PRESCALER__) == LPTIM_ICPSC_DIV4) ||\ + ((__PRESCALER__) == LPTIM_ICPSC_DIV8)) + +#define IS_LPTIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == LPTIM_ICPOLARITY_FALLING) ||\ + ((__POLARITY__) == LPTIM_ICPOLARITY_RISING_FALLING)) + +#define IS_LPTIM_IC_FILTER(__FILTER__) (((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV1) ||\ + ((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV2) ||\ + ((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV4) ||\ + ((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV8)) + +#define IS_LPTIM_REPETITION(__REPETITION__) ((__REPETITION__) <= 0x000000FFUL) + +#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) || \ + ((__INSTANCE__) == LPTIM2) || \ + ((__INSTANCE__) == LPTIM3)) && \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO)) + +#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) || \ + ((__INSTANCE__) == LPTIM2) || \ + ((__INSTANCE__) == LPTIM3)) && \ + ((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO)) + +#define IS_LPTIM_IC1_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) || \ + ((__INSTANCE__) == LPTIM2)|| \ + ((__INSTANCE__) == LPTIM3)) && \ + ((__SOURCE__) == LPTIM_IC1SOURCE_GPIO)) + +#define IS_LPTIM_IC2_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_IC2SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_IC2SOURCE_LSI) || \ + ((__SOURCE__) == LPTIM_IC2SOURCE_LSE))) \ + || \ + (((__INSTANCE__) == LPTIM2) && \ + (((__SOURCE__) == LPTIM_IC2SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_IC2SOURCE_HSI_1024) || \ + ((__SOURCE__) == LPTIM_IC2SOURCE_CSI_128))) \ + || \ + (((__INSTANCE__) == LPTIM3) && \ + ((__SOURCE__) == LPTIM_IC2SOURCE_GPIO))) + +#define LPTIM_CHANNEL_STATE_GET(__INSTANCE__, __CHANNEL__)\ + (((__CHANNEL__) == LPTIM_CHANNEL_1) ? (__INSTANCE__)->ChannelState[0] :\ + (__INSTANCE__)->ChannelState[1]) + +#define LPTIM_CHANNEL_STATE_SET(__INSTANCE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == LPTIM_CHANNEL_1) ? ((__INSTANCE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__INSTANCE__)->ChannelState[1] = (__CHANNEL_STATE__))) + +#define LPTIM_CHANNEL_STATE_SET_ALL(__INSTANCE__, __CHANNEL_STATE__) do { \ + (__INSTANCE__)->ChannelState[0] =\ + (__CHANNEL_STATE__); \ + (__INSTANCE__)->ChannelState[1] =\ + (__CHANNEL_STATE__); \ + } while(0) + +#define IS_LPTIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \ + ((((__INSTANCE__) == LPTIM1) && \ + (((__CHANNEL__) == LPTIM_CHANNEL_1) || \ + ((__CHANNEL__) == LPTIM_CHANNEL_2))) \ + || \ + (((__INSTANCE__) == LPTIM2) && \ + (((__CHANNEL__) == LPTIM_CHANNEL_1) || \ + ((__CHANNEL__) == LPTIM_CHANNEL_2))) \ + || \ + (((__INSTANCE__) == LPTIM3) && \ + (((__CHANNEL__) == LPTIM_CHANNEL_1) || \ + ((__CHANNEL__) == LPTIM_CHANNEL_2))) \ + || \ + (((__INSTANCE__) == LPTIM4) && \ + ((__CHANNEL__) == LPTIM_CHANNEL_1)) \ + || \ + (((__INSTANCE__) == LPTIM5) && \ + ((__CHANNEL__) == LPTIM_CHANNEL_1))) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_LPTIM_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_ltdc.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_ltdc.h new file mode 100644 index 00000000000..14cdcac20f0 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_ltdc.h @@ -0,0 +1,720 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_ltdc.h + * @author MCD Application Team + * @brief Header file of LTDC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_LTDC_H +#define STM32H7RSxx_HAL_LTDC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +#if defined (LTDC) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup LTDC LTDC + * @brief LTDC HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Types LTDC Exported Types + * @{ + */ +#define MAX_LAYER 2U + +/** + * @brief LTDC color structure definition + */ +typedef struct +{ + uint8_t Blue; /*!< Configures the blue value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Green; /*!< Configures the green value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Red; /*!< Configures the red value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Reserved; /*!< Reserved 0xFF */ +} LTDC_ColorTypeDef; + +/** + * @brief LTDC Init structure definition + */ +typedef struct +{ + uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity. + This parameter can be one value of @ref LTDC_HS_POLARITY */ + + uint32_t VSPolarity; /*!< configures the vertical synchronization polarity. + This parameter can be one value of @ref LTDC_VS_POLARITY */ + + uint32_t DEPolarity; /*!< configures the data enable polarity. + This parameter can be one of value of @ref LTDC_DE_POLARITY */ + + uint32_t PCPolarity; /*!< configures the pixel clock polarity. + This parameter can be one of value of @ref LTDC_PC_POLARITY */ + + uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ + + uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. + This parameter must be a number between + Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ + + uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height. + This parameter must be a number between + Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ + + uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. + This parameter must be a number between + Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ + + uint32_t AccumulatedActiveH; /*!< configures the accumulated active height. + This parameter must be a number between + Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ + + uint32_t TotalWidth; /*!< configures the total width. + This parameter must be a number between + Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ + + uint32_t TotalHeigh; /*!< configures the total height. + This parameter must be a number between + Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ + + LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ +} LTDC_InitTypeDef; + +/** + * @brief LTDC Layer structure definition + */ +typedef struct +{ + uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t WindowY0; /*!< Configures the Window vertical Start Position. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ + + uint32_t WindowY1; /*!< Configures the Window vertical Stop Position. + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x7FF. */ + + uint32_t PixelFormat; /*!< Specifies the pixel format. + This parameter can be one of value of @ref LTDC_Pixelformat */ + + uint32_t Alpha; /*!< Specifies the constant alpha used for blending. + This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint32_t Alpha0; /*!< Configures the default alpha value. + This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint32_t BlendingFactor1; /*!< Select the blending factor 1. + This parameter can be one of value of @ref LTDC_BlendingFactor1 */ + + uint32_t BlendingFactor2; /*!< Select the blending factor 2. + This parameter can be one of value of @ref LTDC_BlendingFactor2 */ + + uint32_t FBStartAdress; /*!< Configures the color frame buffer address */ + + uint32_t ImageWidth; /*!< Configures the color frame buffer line length. + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x1FFF. */ + + uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ + + LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */ +} LTDC_LayerCfgTypeDef; + +/** + * @brief HAL LTDC State structures definition + */ +typedef enum +{ + HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */ + HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */ + HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */ + HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */ + HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */ +} HAL_LTDC_StateTypeDef; + +/** + * @brief LTDC handle Structure definition + */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +typedef struct __LTDC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ +{ + LTDC_TypeDef *Instance; /*!< LTDC Register base address */ + + LTDC_InitTypeDef Init; /*!< LTDC parameters */ + + LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */ + + HAL_LockTypeDef Lock; /*!< LTDC Lock */ + + __IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */ + + __IO uint32_t ErrorCode; /*!< LTDC Error code */ + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Line Event Callback */ + void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Reload Event Callback */ + void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Error Callback */ + + void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp Init callback */ + void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp DeInit callback */ + +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + +} LTDC_HandleTypeDef; + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL LTDC Callback ID enumeration definition + */ +typedef enum +{ + HAL_LTDC_MSPINIT_CB_ID = 0x00U, /*!< LTDC MspInit callback ID */ + HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, /*!< LTDC MspDeInit callback ID */ + + HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, /*!< LTDC Line Event Callback ID */ + HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U, /*!< LTDC Reload Callback ID */ + HAL_LTDC_ERROR_CB_ID = 0x04U /*!< LTDC Error Callback ID */ + +} HAL_LTDC_CallbackIDTypeDef; + +/** + * @brief HAL LTDC Callback pointer definition + */ +typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer to an LTDC callback function */ + +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Constants LTDC Exported Constants + * @{ + */ + +/** @defgroup LTDC_Error_Code LTDC Error Code + * @{ + */ +#define HAL_LTDC_ERROR_NONE 0x00000000U /*!< LTDC No error */ +#define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */ +#define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */ +#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U /*!< LTDC Invalid Callback error */ +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup LTDC_Layer LTDC Layer + * @{ + */ +#define LTDC_LAYER_1 0x00000000U /*!< LTDC Layer 1 */ +#define LTDC_LAYER_2 0x00000001U /*!< LTDC Layer 2 */ +/** + * @} + */ + +/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY + * @{ + */ +#define LTDC_HSPOLARITY_AL 0x00000000U /*!< Horizontal Synchronization is active low. */ +#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY + * @{ + */ +#define LTDC_VSPOLARITY_AL 0x00000000U /*!< Vertical Synchronization is active low. */ +#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY + * @{ + */ +#define LTDC_DEPOLARITY_AL 0x00000000U /*!< Data Enable, is active low. */ +#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY + * @{ + */ +#define LTDC_PCPOLARITY_IPC 0x00000000U /*!< input pixel clock. */ +#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ +/** + * @} + */ + +/** @defgroup LTDC_SYNC LTDC SYNC + * @{ + */ +#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */ +#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */ +/** + * @} + */ + +/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR + * @{ + */ +#define LTDC_COLOR 0x000000FFU /*!< Color mask */ +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1 + * @{ + */ +#define LTDC_BLENDING_FACTOR1_CA 0x00000400U /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2 + * @{ + */ +#define LTDC_BLENDING_FACTOR2_CA 0x00000005U /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +/** + * @} + */ + +/** @defgroup LTDC_Pixelformat LTDC Pixel format + * @{ + */ +#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */ +/** + * @} + */ + +/** @defgroup LTDC_Alpha LTDC Alpha + * @{ + */ +#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Constant Alpha mask */ +/** + * @} + */ + +/** @defgroup LTDC_LAYER_Config LTDC LAYER Config + * @{ + */ +#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */ +#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */ + +#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */ +#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */ +/** + * @} + */ + +/** @defgroup LTDC_Interrupts LTDC Interrupts + * @{ + */ +#define LTDC_IT_LI LTDC_IER_LIE /*!< LTDC Line Interrupt */ +#define LTDC_IT_FU LTDC_IER_FUIE /*!< LTDC FIFO Underrun Interrupt */ +#define LTDC_IT_TE LTDC_IER_TERRIE /*!< LTDC Transfer Error Interrupt */ +#define LTDC_IT_RR LTDC_IER_RRIE /*!< LTDC Register Reload Interrupt */ +/** + * @} + */ + +/** @defgroup LTDC_Flags LTDC Flags + * @{ + */ +#define LTDC_FLAG_LI LTDC_ISR_LIF /*!< LTDC Line Interrupt Flag */ +#define LTDC_FLAG_FU LTDC_ISR_FUIF /*!< LTDC FIFO Underrun interrupt Flag */ +#define LTDC_FLAG_TE LTDC_ISR_TERRIF /*!< LTDC Transfer Error interrupt Flag */ +#define LTDC_FLAG_RR LTDC_ISR_RRIF /*!< LTDC Register Reload interrupt Flag */ +/** + * @} + */ + +/** @defgroup LTDC_Reload_Type LTDC Reload Type + * @{ + */ +#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */ +#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Macros LTDC Exported Macros + * @{ + */ + +/** @brief Reset LTDC handle state. + * @param __HANDLE__ LTDC handle + * @retval None + */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_LTDC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) +#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @brief Enable the LTDC. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN) + +/** + * @brief Disable the LTDC. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN)) + +/** + * @brief Enable the LTDC Layer. + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be enabled. + * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval None. + */ +#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ + |= (uint32_t)LTDC_LxCR_LEN) + +/** + * @brief Disable the LTDC Layer. + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be disabled. + * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval None. + */ +#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ + &= ~(uint32_t)LTDC_LxCR_LEN) + +/** + * @brief Reload immediately all LTDC Layers. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR) + +/** + * @brief Reload during vertical blanking period all LTDC Layers. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR) + +/* Interrupt & Flag management */ +/** + * @brief Get the LTDC pending flags. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag + * @arg LTDC_FLAG_TE: Transfer Error interrupt flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) + +/** + * @brief Clears the LTDC pending flags. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ Specify the flag to clear. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag + * @arg LTDC_FLAG_TE: Transfer Error interrupt flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** + * @brief Enables the specified LTDC interrupts. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified LTDC interrupts. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified LTDC interrupt has occurred or not. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt source to check. + * This parameter can be one of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval The state of INTERRUPT (SET or RESET). + */ +#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) +/** + * @} + */ + +/* Include LTDC HAL Extension module */ +#include "stm32h7rsxx_hal_ltdc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LTDC_Exported_Functions + * @{ + */ +/** @addtogroup LTDC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, + pLTDC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line); +HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType); +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); + +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc); +uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup LTDC_Private_Macros LTDC Private Macros + * @{ + */ +#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(\ + ((uint32_t)((__HANDLE__)->Instance))\ + + 0x84U + (0x80U*(__LAYER__))))) +#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER) +#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL)\ + || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) +#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL)\ + || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) +#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL)\ + || ((__DEPOL__) == LTDC_DEPOLARITY_AH)) +#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\ + || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC)) +#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR) +#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR) +#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR) +#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \ + ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA)) +#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \ + ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA)) +#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88)) +#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA) +#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION) +#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION) +#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION) +#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION) +#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER) +#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER) +#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER) +#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU) +#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \ + ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LTDC_Private_Functions LTDC Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LTDC */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_LTDC_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_ltdc_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_ltdc_ex.h new file mode 100644 index 00000000000..cbf412e880f --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_ltdc_ex.h @@ -0,0 +1,83 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_ltdc_ex.h + * @author MCD Application Team + * @brief Header file of LTDC HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_LTDC_EX_H +#define STM32H7RSxx_HAL_LTDC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +#if defined (LTDC) && defined (DSI) + +#include "stm32h7rsxx_hal_dsi.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup LTDCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LTDCEx_Exported_Functions + * @{ + */ + +/** @addtogroup LTDCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg); +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LTDC && DSI */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_LTDC_EX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mce.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mce.h new file mode 100644 index 00000000000..e39843f39cb --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mce.h @@ -0,0 +1,479 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_mce.h + * @author MCD Application Team + * @brief Header file of MCE HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_MCE_H +#define STM32H7RSxx_HAL_MCE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#if defined(MCE1) +/** @addtogroup MCE + * @{ + */ +typedef struct +{ + uint32_t ContextID; /*!< MCE region context ID (can be null) */ + /*!< This parameter is a value of @ref MCE_Context_Index. */ + + uint32_t StartAddress; /*!< MCE region start address */ + + uint32_t EndAddress; /*!< MCE region end address */ + + uint32_t Mode; /*!< Indicates the chaining mode used for encryption. */ + /*!< This parameter is a value of @defgroup MCE_Ciphering_Algorithm */ + uint32_t AccessMode; /*!< MCE region writes enabled or not */ + /*!< This parameter is a value of @ref MCE_Region_Privilege. */ + + uint32_t PrivilegedAccess; /*!< MCE region privileged access or not */ + /*!< This parameter is a value of @ref MCE_Region_Privilege. */ + +} MCE_RegionConfigTypeDef; + +typedef struct +{ + uint32_t Nonce[2]; /*!< MCE context nonce */ + + uint32_t Version; /*!< 16-bit long MCE context version */ + + uint32_t *pKey; /*!< Pointer at the key used for encryption/decryption */ + +} MCE_AESConfigTypeDef; + +typedef struct +{ + uint32_t KeyType; /*!< This parameter is a value of @ref MCE_KeyType. */ + + uint32_t *pKey; /*!< Pointer at the key used for encryption/decryption .*/ + +} MCE_NoekeonConfigTypeDef; + + +/** + * @brief MCE states structure definition + */ +typedef enum +{ + HAL_MCE_STATE_RESET = 0x00U, /*!< MCE not yet initialized or disabled */ + HAL_MCE_STATE_READY = 0x01U, /*!< MCE initialized and ready for use */ + HAL_MCE_STATE_BUSY = 0x02U, /*!< MCE internal processing is ongoing */ +} HAL_MCE_StateTypeDef; + +#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1) +typedef struct __MCE_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */ +{ + MCE_TypeDef *Instance; /*!< MCE registers base address */ + + HAL_MCE_StateTypeDef State; /*!< MCE state */ + + HAL_LockTypeDef Lock; /*!< MCE Locking object */ + + __IO uint32_t ErrorCode; /*!< MCE error code */ + +#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1) + void (* ErrorCallback)(struct __MCE_HandleTypeDef *hmce); /*!< MCE error callback */ + + void (* MspInitCallback)(struct __MCE_HandleTypeDef *hmce); /*!< MCE Msp Init callback */ + + void (* MspDeInitCallback)(struct __MCE_HandleTypeDef *hmce); /*!< MCE Msp DeInit callback */ +#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */ + +} MCE_HandleTypeDef; + +#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1) +/** + * @brief HAL MCE Callback ID enumeration definition + */ +typedef enum +{ + HAL_MCE_ERROR_CB_ID = 0x00U, /*!< MCE error callback ID */ + HAL_MCE_MSPINIT_CB_ID = 0x01U, /*!< MCE Msp DeInit callback ID */ + HAL_MCE_MSPDEINIT_CB_ID = 0x02U /*!< MCE Msp DeInit callback ID */ +} HAL_MCE_CallbackIDTypeDef; + +/** + * @brief HAL MCE Callback pointer definition + */ +typedef void (*pMCE_CallbackTypeDef)(MCE_HandleTypeDef *hmce); /*!< pointer to a MCE callback function */ + +#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup MCE_Exported_Constants MCE Exported Constants + * @{ + */ + +/** @defgroup MCE_Error_Definition MCE Error Definition + * @{ + */ +#define HAL_MCE_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_MCE_CONFIGURATION_ACCESS_ERROR ((uint32_t)0x00000001U) /*!< Configuration access error */ +#define HAL_MCE_ILLEGAL_ACCESS_READ_PRIV_ERROR ((uint32_t)0x00000002U) /*!< Illegal privileged data read or instruction fetch access error */ +#define HAL_MCE_ILLEGAL_ACCESS_READ_NPRIV_ERROR ((uint32_t)0x00000004U) /*!< Illegal unprivileged data read or instruction fetch access error */ +#define HAL_MCE_ILLEGAL_ACCESS_WRITE_PRIV_ERROR ((uint32_t)0x00000008U) /*!< Illegal privileged data write access error */ +#define HAL_MCE_ILLEGAL_ACCESS_WRITE_NPRIV_ERROR ((uint32_t)0x00000010U) /*!< Illegal un privileged data write access error */ +#define HAL_MCE_MASTER_KEY_ERROR ((uint32_t)0x00000020U) /*!< Master key error */ +#define HAL_MCE_FASTMASTER_KEY_ERROR ((uint32_t)0x00000040U) /*!< Fast master key error */ +#define HAL_MCE_CONTEXT_KEY_ERROR ((uint32_t)0x00000080U) /*!< Context key error */ +#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1) +#define HAL_MCE_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup MCE_Interrupts MCE Interrupts + * @{ + */ +#define MCE_IT_ILLEGAL_ACCESS_ERROR MCE_IAIER_IAEIE /*!< Illegal access error interrupt */ +#define MCE_IT_CONFIGURATION_ACCESS_ERROR MCE_IAIER_CAEIE /*!< Configuration access error interrupt */ +#define MCE_IT_ALL (MCE_IAIER_IAEIE|MCE_IAIER_CAEIE) /*!< All interrupts */ +/** + * @} + */ + +/** @defgroup MCE_Illegal_Access_Flags MCE Illegal Access Flags + * @{ + */ +#define MCE_CONFIGURATION_ACCESS_ERROR MCE_IASR_CAEF /*!< Configuration access error */ +#define MCE_ILLEGAL_ACCESS_READ_NPRIV MCE_IASR_IAEF /*!< Illegal unprivileged data read/instruction fetch access flag */ +#define MCE_ILLEGAL_ACCESS_READ_PRIV (MCE_IASR_IAEF | MCE_IAESR_IAPRIV) /*!< Illegal privileged data read/instruction fetch access flag */ +#define MCE_ILLEGAL_ACCESS_WRITE_NPRIV (MCE_IASR_IAEF | MCE_IAESR_IANRW) /*!< Illegal unprivileged write access access flag */ +#define MCE_ILLEGAL_ACCESS_WRITE_PRIV (MCE_IASR_IAEF | MCE_IAESR_IANRW | MCE_IAESR_IAPRIV) /*!< Illegal privileged write access access flag */ +/** + * @} + */ + + +/** @defgroup MCE_Regions_Index MCE Regions Index + * @{ + */ +#define MCE_REGION1 0U /*!< MCE region 1 */ +#define MCE_REGION2 1U /*!< MCE region 2 */ +#define MCE_REGION3 2U /*!< MCE region 3 */ +#define MCE_REGION4 3U /*!< MCE region 4 */ +/** + * @} + */ + +/** @defgroup MCE_Context_Index MCE Context Index + * @{ + */ +#define MCE_NO_CONTEXT 0U /*!< MCE no context */ +#define MCE_CONTEXT1 MCE_REGCR_CTXID_0 /*!< MCE context 1 */ +#define MCE_CONTEXT2 MCE_REGCR_CTXID_1 /*!< MCE context 2 */ +/** + * @} + */ + +/** @defgroup MCE_Ciphering_Algorithm MCE Ciphering Algorithm + * @{ + */ +#define MCE_NO_CIPHER 0U /*!< MCE no cipher */ +#define MCE_STREAM_CIPHER MCE_REGCR_ENC_0 /*!< MCE stream cipher */ +#define MCE_BLOCK_CIPHER MCE_REGCR_ENC_1 /*!< MCE block cipher */ +#define MCE_FASTBLOCK_CIPHER MCE_REGCR_ENC /*!< MCE fast block cipher */ +/** + * @} + */ + + +/** @defgroup MCE_Region_Privilege MCE Region Privilege + * @{ + */ +#define MCE_REGION_NPRIV 0U /*!< Region non-privileged and privileged access */ +#define MCE_REGION_PRIV MCE_REGCR_PRIV /*!< Region privileged access only */ +/** + * @} + */ + + +/** @defgroup MCE_Region_Privilege MCE Region Privilege + * @{ + */ +#define MCE_REGION_READONLY 0U /*!< Writes to region are ignored, reads are allowed */ +#define MCE_REGION_READWRITE MCE_ATTR_WREN /*!< Region can be read and written */ +/** + * @} + */ + +/** @defgroup MCE_Configuration_Attributes MCE Configuration Attributes + * @{ + */ +#define MCE_ATTRIBUTE_NPRIV 0U /*!< Non-privileged access protection */ +#define MCE_ATTRIBUTE_PRIV MCE_PRIVCFGR_PRIV /*!< Privileged access protection */ +/** + * @} + */ + +/** @defgroup MCE_Lock MCE Lock values + * @{ + */ +#define MCE_LOCK_OFF 0U /*!< No global lock set */ +#define MCE_LOCK_ON MCE_CR_GLOCK /*!< Global lock set */ +/** + * @} + */ + +/** @defgroup MCE_Lock MCE Lock values + * @{ + */ +#define MCE_MASTERKEYS_LOCK_OFF 0U /*!< No master keys lock set */ +#define MCE_MASTERKEYS_LOCK_ON MCE_CR_MKLOCK /*!< Master keys lock set */ +/** + * @} + */ + +/** @defgroup MCE_KeyType key type used for encryption, Master key or Fast Master key + * @{ + */ +#define MCE_USE_MASTERKEYS 0U /*!< Master keys used for encryption */ +#define MCE_USE_FASTMASTERKEYS 1U /*!< Fast Master keys used for encryption */ +/** + * @} + */ + + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup MCE_Exported_Macros MCE Exported Macros + * @{ + */ + +/** @brief Reset MCE handle state. + * @param __HANDLE__ pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @retval None + */ +#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1) +#define __HAL_MCE_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_MCE_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_MCE_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_MCE_STATE_RESET) +#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */ + +/** + * @brief Enable MCE peripheral interrupts combination + * @param __HANDLE__ pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @param __INTERRUPT__ mask on enabled interrupts + * This parameter can be one of the following values: + * @arg @ref MCE_IT_ILLEGAL_ACCESS_ERROR MCE illegal access error interrupt + * @arg @ref MCE_IT_CONFIGURATION_ACCESS_ERROR MCE configuration access error interrupt + * @arg @ref MCE_IT_ALL MCE all interrupts + * @retval None + */ +#define __HAL_MCE_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(((__HANDLE__)->Instance->IAIER), (__INTERRUPT__)) + +/** + * @brief Disable MCE peripheral interrupts combination + * @param __HANDLE__ pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @param __INTERRUPT__ mask on disabled interrupts + * This parameter can be one of the following values: + * @arg @ref MCE_IT_ILLEGAL_ACCESS_ERROR MCE illegal access error interrupt + * @arg @ref MCE_IT_CONFIGURATION_ACCESS_ERROR MCE configuration access error interrupt + * @arg @ref MCE_IT_ALL MCE all interrupts + * @retval None + */ +#define __HAL_MCE_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(((__HANDLE__)->Instance->IAIER), (__INTERRUPT__)) + + +/** + * @brief Get MCE peripheral access error flag + * @param __HANDLE__ pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @param __FLAG__ access error flag to check + * This parameter can be one of the following values: + * @arg @ref MCE_CONFIGURATION_ACCESS_ERROR MCE configuration access error flag + * @arg @ref MCE_ILLEGAL_ACCESS_READ_NPRIV MCE illegal unprivileged data read/instruction fetch access flag + * @arg @ref MCE_ILLEGAL_ACCESS_READ_PRIV MCE illegal privileged data read/instruction fetch access flag + * @arg @ref MCE_ILLEGAL_ACCESS_WRITE_NPRIV MCE illegal unprivileged write access access flag + * @arg @ref MCE_ILLEGAL_ACCESS_WRITE_PRIV MCE illegal privileged write access access flag + * @retval 0 (not set) or 1 (set) + */ +#define __HAL_MCE_GET_FLAG(__HANDLE__, __FLAG__) \ + (((__FLAG__) == MCE_CONFIGURATION_ACCESS_ERROR) ? \ + (READ_BIT((__HANDLE__)->Instance->IASR, MCE_IASR_CAEF) == MCE_IASR_CAEF) : \ + ((READ_BIT((__HANDLE__)->Instance->IASR, MCE_IASR_IAEF) == MCE_IASR_IAEF) && \ + (READ_BIT((__HANDLE__)->Instance->IAESR, ((__FLAG__) & ~MCE_IASR_IAEF)) == ((__FLAG__) & ~MCE_IASR_IAEF)))) + + + +/** + * @brief Clear MCE peripheral illegal/configuration access flag + * @param __HANDLE__ pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @param __FLAG__ illegal access flag to check + * This parameter can be one of the following values: + * @arg @ref MCE_CONFIGURATION_ACCESS_ERROR MCE configuration access error flag + * @arg @ref MCE_ILLEGAL_ACCESS_READ_NPRIV MCE illegal unprivileged data read/instruction fetch access flag + * @arg @ref MCE_ILLEGAL_ACCESS_READ_PRIV MCE illegal privileged data read/instruction fetch access flag + * @arg @ref MCE_ILLEGAL_ACCESS_WRITE_NPRIV MCE illegal unprivileged write access access flag + * @arg @ref MCE_ILLEGAL_ACCESS_WRITE_PRIV MCE illegal privileged write access access flag + * @retval 0 (not set) or 1 (set) + */ +#define __HAL_MCE_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + (((__FLAG__) == MCE_CONFIGURATION_ACCESS_ERROR) ? WRITE_REG(((__HANDLE__)->Instance->IACR), MCE_IACR_CAEF) : \ + WRITE_REG(((__HANDLE__)->Instance->IACR), MCE_IACR_IAEF)) + + +/** + * @} + */ + + + + +/* Exported functions ---------------------------------------------------------*/ + + +HAL_StatusTypeDef HAL_MCE_Init(MCE_HandleTypeDef *hmce); +HAL_StatusTypeDef HAL_MCE_DeInit(MCE_HandleTypeDef *hmce); +void HAL_MCE_MspInit(MCE_HandleTypeDef *hmce); +void HAL_MCE_MspDeInit(MCE_HandleTypeDef *hmce); + + +HAL_StatusTypeDef HAL_MCE_ConfigNoekeon(MCE_HandleTypeDef *hmce, const MCE_NoekeonConfigTypeDef *pConfig); +HAL_StatusTypeDef HAL_MCE_ConfigAESContext(MCE_HandleTypeDef *hmce, const MCE_AESConfigTypeDef *AESConfig, + uint32_t ContextIndex); +HAL_StatusTypeDef HAL_MCE_ConfigRegion(MCE_HandleTypeDef *hmce, uint32_t RegionIndex, + const MCE_RegionConfigTypeDef *pConfig); +HAL_StatusTypeDef HAL_MCE_SetRegionAESContext(MCE_HandleTypeDef *hmce, uint32_t ContextIndex, uint32_t RegionIndex); +HAL_StatusTypeDef HAL_MCE_EnableAESContext(MCE_HandleTypeDef *hmce, uint32_t ContextIndex); +HAL_StatusTypeDef HAL_MCE_DisableAESContext(MCE_HandleTypeDef *hmce, uint32_t ContextIndex); +HAL_StatusTypeDef HAL_MCE_EnableRegion(MCE_HandleTypeDef *hmce, uint32_t RegionIndex); +HAL_StatusTypeDef HAL_MCE_DisableRegion(MCE_HandleTypeDef *hmce, uint32_t RegionIndex); +HAL_StatusTypeDef HAL_MCE_LockGlobalConfig(MCE_HandleTypeDef *hmce); +HAL_StatusTypeDef HAL_MCE_LockAESContextConfig(MCE_HandleTypeDef *hmce, uint32_t ContextIndex); +HAL_StatusTypeDef HAL_MCE_LockAESContextKey(MCE_HandleTypeDef *hmce, uint32_t ContextIndex); +HAL_StatusTypeDef HAL_MCE_LockNoekeonMasterKeys(MCE_HandleTypeDef *hmce); +HAL_StatusTypeDef HAL_MCE_LockNoekeonFastKeys(MCE_HandleTypeDef *hmce); +HAL_StatusTypeDef HAL_MCE_GetAESContextCRCKey(const MCE_HandleTypeDef *hmce, uint32_t *pCRCKey, uint32_t ContextIndex); + + +void HAL_MCE_IRQHandler(MCE_HandleTypeDef *hmce); +void HAL_MCE_ErrorCallback(MCE_HandleTypeDef *hmce); + +HAL_MCE_StateTypeDef HAL_MCE_GetState(MCE_HandleTypeDef const *hmce); +uint32_t HAL_MCE_GetError(MCE_HandleTypeDef const *hmce); +uint32_t HAL_MCE_KeyCRCComputation(const uint32_t *pKey); + +#define IS_MCE_INTERRUPT(__INTERRUPT__) (((__INTERRUPT__) == MCE_IT_ILLEGAL_ACCESS_ERROR) || \ + ((__INTERRUPT__) == MCE_IT_CONFIGURATION_ACCESS_ERROR) || \ + ((__INTERRUPT__) == MCE_IT_ALL) ) + +/** + * @brief Verify the MCE region index. + * @param __INDEX__ MCE region index + * @retval SET (__INDEX__ is valid) or RESET (__INDEX__ is invalid) + */ +#define IS_MCE_REGIONINDEX(__INDEX__) (((__INDEX__) == MCE_REGION1) || \ + ((__INDEX__) == MCE_REGION2) || \ + ((__INDEX__) == MCE_REGION3) || \ + ((__INDEX__) == MCE_REGION4)) + +/** + * @brief Verify the MCE configuration attributes. + * @param __ATTRIBUTE__ MCE region index + * @retval SET (__ATTRIBUTE__ is valid) or RESET (__ATTRIBUTE__ is invalid) + */ +#define IS_MCE_ATTRIBUTE(__ATTRIBUTE__) (((__ATTRIBUTE__) == MCE_ATTRIBUTE_PRIV) || \ + ((__ATTRIBUTE__) == MCE_ATTRIBUTE_NPRIV)) + +/** + * @brief Verify the MCE region privilege attribute. + * @param __PRIVILEGED__ MCE region privilege attribute + * @retval SET (__PRIVILEGED__ is valid) or RESET (__PRIVILEGED__ is invalid) + */ +#define IS_MCE_REGIONPRIVILEGED(__PRIVILEGED__) (((__PRIVILEGED__) == MCE_REGION_NPRIV) || \ + ((__PRIVILEGED__) == MCE_REGION_PRIV)) + +/** + * @brief Verify the MCE region write enable attribute. + * @param __WRITE__ MCE region write enable attribute + * @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid) + */ +#define IS_MCE_WRITE(__WRITE__) (((__WRITE__) == MCE_REGION_READONLY) || \ + ((__WRITE__) == MCE_REGION_READWRITE)) + +/** + * @brief Verify the MCE region context. + * @param __INSTANCE__ MCE instance + * @param __CONTEXT__ MCE region context + * @retval SET (__CONTEXT__ is valid) or RESET (__CONTEXT__ is invalid) + */ +#define IS_MCE_CONTEXT(__INSTANCE__, __CONTEXT__) (((__INSTANCE__) == (MCE1)) ? \ + (((__CONTEXT__) == MCE_NO_CONTEXT) || \ + ((__CONTEXT__) == MCE_CONTEXT1) || \ + ((__CONTEXT__) == MCE_CONTEXT2)) : \ + ((__CONTEXT__) == MCE_NO_CONTEXT)) + +/** + * @brief Verify the MCE region algorithm. + * @param __INSTANCE__ MCE instance + * @param __ALGO__ MCE region context + * @retval SET (__ALGO__ is valid) or RESET (__ALGO__ is invalid) + */ +#define IS_MCE_ALGORITHM(__INSTANCE__, __ALGO__) (((__INSTANCE__) == (MCE1)) ? \ + (((__ALGO__) == MCE_NO_CIPHER) || \ + ((__ALGO__) == MCE_STREAM_CIPHER) || \ + ((__ALGO__) == MCE_BLOCK_CIPHER) || \ + ((__ALGO__) == MCE_FASTBLOCK_CIPHER)) : \ + (((__ALGO__) == MCE_NO_CIPHER) || \ + ((__ALGO__) == MCE_BLOCK_CIPHER) || \ + ((__ALGO__) == MCE_FASTBLOCK_CIPHER))) + + + +#endif /* MCE1 */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_MCE_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mdf.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mdf.h new file mode 100644 index 00000000000..b741ae0ca98 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mdf.h @@ -0,0 +1,781 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_mdf.h + * @author MCD Application Team + * @brief Header file of MDF HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_MDF_H +#define STM32H7RSxx_HAL_MDF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup MDF + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup MDF_Exported_Types MDF Exported Types + * @{ + */ + +/** + * @brief HAL MDF states definition + */ +typedef enum +{ + HAL_MDF_STATE_RESET = 0x00U, /*!< MDF not initialized */ + HAL_MDF_STATE_READY = 0x01U, /*!< MDF initialized and ready for use */ + HAL_MDF_STATE_ACQUISITION = 0x02U, /*!< MDF acquisition in progress */ + HAL_MDF_STATE_ERROR = 0xFFU /*!< MDF state error */ +} HAL_MDF_StateTypeDef; + +/** + * @brief MDF clock trigger structure definition + */ +typedef struct +{ + FunctionalState Activation; /*!< Output clock trigger enable/disable */ + uint32_t Source; /*!< Output clock trigger source. + This parameter can be a value of @ref MDF_ClockTriggerSource */ + uint32_t Edge; /*!< Output clock trigger edge. + This parameter can be a value of @ref MDF_ClockTriggerEdge */ +} MDF_ClockTriggerTypeDef; + +/** + * @brief MDF output clock structure definition + */ +typedef struct +{ + FunctionalState Activation; /*!< Output clock enable/disable */ + uint32_t Pins; /*!< Output clock pins. + This parameter can be a value of @ref MDF_OuputClockPins */ + uint32_t Divider; /*!< Output clock divider. + This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ + MDF_ClockTriggerTypeDef Trigger; /*!< Output clock trigger parameters */ +} MDF_OutputClockTypeDef; + +/** + * @brief MDF common parameters structure definition + */ +typedef struct +{ + uint32_t ProcClockDivider; /*!< Processing clock divider. + This parameter must be a number between Min_Data = 1 + and Max_Data = 128 */ + MDF_OutputClockTypeDef OutputClock; /*!< Output clock parameters */ +} MDF_CommonParamTypeDef; + +/** + * @brief MDF serial interface structure definition + */ +typedef struct +{ + FunctionalState Activation; /*!< Serial interface enable/disable */ + uint32_t Mode; /*!< Serial interface mode. + This parameter can be a value of @ref MDF_SitfMode */ + uint32_t ClockSource; /*!< Serial interface clock source. + This parameter can be a value of @ref MDF_SitfClockSource */ + uint32_t Threshold; /*!< SPI threshold for clock absence detection or Manchester symbol threshold. + This parameter must be a number between Min_Data = 4 and Max_Data = 31 */ +} MDF_SerialInterfaceTypeDef; + +/** + * @brief MDF init structure definition + */ +typedef struct +{ + MDF_CommonParamTypeDef CommonParam; /*!< MDF common parameters */ + MDF_SerialInterfaceTypeDef SerialInterface; /*!< MDF serial interface parameters */ + uint32_t FilterBistream; /*!< MDF filter bitstream selection. + This parameter can be a value of @ref MDF_FilterBitstream */ +} MDF_InitTypeDef; + +/** + * @brief MDF handle structure definition + */ +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) +typedef struct __MDF_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ +{ + MDF_Filter_TypeDef *Instance; /*!< MDF instance */ + MDF_InitTypeDef Init; /*!< MDF init parameters */ + DMA_HandleTypeDef *hdma; /*!< Pointer on DMA handler for acquisitions */ + __IO HAL_MDF_StateTypeDef State; /*!< MDF state */ + __IO uint32_t ErrorCode; /*!< MDF error code */ +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) + void (*AcqCpltCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF acquisition complete callback */ + void (*AcqHalfCpltCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF acquisition half complete callback */ + void (*SndLvCallback)(struct __MDF_HandleTypeDef *hmdf, + uint32_t SoundLevel, + uint32_t AmbientNoise); /*!< MDF sound level callback */ + void (*SadCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF sound activity detector callback */ + void (*ErrorCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF error callback */ + void (*MspInitCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF MSP init callback */ + void (*MspDeInitCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF MSP de-init callback */ +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ +} MDF_HandleTypeDef; + +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) +/** + * @brief MDF callback ID enumeration definition + */ +typedef enum +{ + HAL_MDF_ACQ_COMPLETE_CB_ID = 0x01U, /*!< MDF acquisition complete callback ID */ + HAL_MDF_ACQ_HALFCOMPLETE_CB_ID = 0x02U, /*!< MDF acquisition half complete callback ID */ + HAL_MDF_SNDLVL_CB_ID = 0x03U, /*!< MDF sound level callback ID */ + HAL_MDF_SAD_CB_ID = 0x04U, /*!< MDF sound activity detector callback ID */ + HAL_MDF_ERROR_CB_ID = 0x05U, /*!< MDF error callback ID */ + HAL_MDF_MSPINIT_CB_ID = 0x06U, /*!< MDF MSP init callback ID */ + HAL_MDF_MSPDEINIT_CB_ID = 0x07U /*!< MDF MSP de-init callback ID */ +} HAL_MDF_CallbackIDTypeDef; + +/** + * @brief MDF callback pointers definition + */ +typedef void (*pMDF_CallbackTypeDef)(MDF_HandleTypeDef *hmdf); +typedef void (*pMDF_SndLvlCallbackTypeDef)(MDF_HandleTypeDef *hmdf, uint32_t SoundLevel, uint32_t AmbientNoise); +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ + +/** + * @brief MDF reshape filter structure definition + */ +typedef struct +{ + FunctionalState Activation; /*!< Reshape filter enable/disable */ + uint32_t DecimationRatio; /*!< Reshape filter decimation ratio. + This parameter can be a value of @ref MDF_ReshapeDecimationRatio */ +} MDF_ReshapeFilterTypeDef; + +/** + * @brief MDF high pass filter structure definition + */ +typedef struct +{ + FunctionalState Activation; /*!< High pass filter enable/disable */ + uint32_t CutOffFrequency; /*!< High pass filter cut-off frequency. + This parameter can be a value of @ref MDF_HighPassCutOffFreq */ +} MDF_HighPassFilterTypeDef; + +/** + * @brief MDF sound activity structure definition + */ +typedef struct +{ + FunctionalState Activation; /*!< Sound activity detector enable/disable */ + uint32_t Mode; /*!< Sound activity detector mode. + This parameter can be a value of @ref MDF_SadMode */ + uint32_t FrameSize; /*!< Size of one frame to compute short-term signal level. + This parameter can be a value of @ref MDF_SadFrameSize */ + FunctionalState Hysteresis; /*!< Hysteresis enable/disable. + @note This parameter is not used if Mode is set + to MDF_SAD_AMBIENT_NOISE_ESTIMATOR */ + uint32_t SoundTriggerEvent; /*!< Sound trigger event configuration. + This parameter can be a value of @ref MDF_SadSoundTriggerEvent */ + uint32_t DataMemoryTransfer; /*!< Data memory transfer mode. + This parameter can be a value of @ref MDF_SadDataMemoryTransfer */ + uint32_t MinNoiseLevel; /*!< Minimum noise level. + This parameter must be a number between Min_Data = 0 + and Max_Data = 8191 */ + uint32_t HangoverWindow; /*!< Hangover time window in frames. + This parameter can be a value of @ref MDF_SadHangoverWindow */ + uint32_t LearningFrames; /*!< Number of learning frames for the first estimation of noise level. + This parameter can be a value of @ref MDF_SadLearningFrames */ + uint32_t AmbientNoiseSlope; /*!< Ambient noise slope control. + This parameter must be a number between Min_Data = 0 and Max_Data = 7. + @note This parameter is not used if Mode is set + to MDF_SAD_SOUND_DETECTOR */ + uint32_t SignalNoiseThreshold; /*!< Signal to noise threshold. + This parameter can be a value of @ref MDF_SadSignalNoiseThreshold */ + FunctionalState SoundLevelInterrupt; /*!< Sound level interrupt enable/disable. + @note This interrupt is mainly used for debug purpose */ +} MDF_SoundActivityTypeDef; + +/** + * @brief MDF filter trigger structure definition + */ +typedef struct +{ + uint32_t Source; /*!< Filter trigger source. + This parameter can be a value of @ref MDF_FilterTriggerSource */ + uint32_t Edge; /*!< Filter trigger edge. + This parameter can be a value of @ref MDF_FilterTriggerEdge */ +} MDF_FilterTriggerTypeDef; + +/** + * @brief MDF filter configuration structure definition + */ +typedef struct +{ + uint32_t DataSource; /*!< Filter data source. + This parameter can be a value of @ref MDF_DataSource */ + uint32_t Delay; /*!< Delay to apply on data source in number of samples. + This parameter must be a number between Min_Data = 0 + and Max_Data = 127 */ + uint32_t CicMode; /*!< CIC filter mode. + This parameter can be a value of @ref MDF_CicMode */ + uint32_t DecimationRatio; /*!< Filter decimation ratio. + This parameter must be a number between Min_Data = 2 + and Max_Data = 512 */ + int32_t Gain; /*!< Filter gain in step of around 3db (from -48db to 72dB). + This parameter must be a number between Min_Data = -16 + and Max_Data = 24 */ + MDF_ReshapeFilterTypeDef ReshapeFilter; /*!< Reshape filter configuration */ + MDF_HighPassFilterTypeDef HighPassFilter; /*!< High pass filter configuration */ + MDF_SoundActivityTypeDef SoundActivity; /*!< Sound activity detector configuration */ + uint32_t AcquisitionMode; /*!< Filter acquisition mode. + This parameter can be a value of @ref MDF_AcquisitionMode */ + uint32_t FifoThreshold; /*!< Filter RXFIFO threshold. + This parameter can be a value of @ref MDF_FifoThreshold */ + uint32_t DiscardSamples; /*!< Number of samples to discard after filter enable. + This parameter must be a number between Min_Data = 0 + and Max_Data = 255 */ + MDF_FilterTriggerTypeDef Trigger; /*!< Filter trigger configuration. + @note This parameter is not used if AcquisitionMode is set + to MDF_MODE_ASYNC_CONT or MDF_MODE_ASYNC_SINGLE */ +} MDF_FilterConfigTypeDef; + +/** + * @brief MDF DMA configuration structure definition + */ +typedef struct +{ + uint32_t Address; /*!< DMA destination address */ + uint32_t DataLength; /*!< Length of data to transfer in bytes */ + FunctionalState MsbOnly; /*!< Transfer only the 16MSB of the acquistion data */ +} MDF_DmaConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup MDF_Exported_Constants MDF Exported Constants + * @{ + */ + +/** @defgroup MDF_ErrorCode MDF error code + * @{ + */ +#define MDF_ERROR_NONE 0x00000000U /*!< No error */ +#define MDF_ERROR_ACQUISITION_OVERFLOW 0x00000001U /*!< Overflow occurs during acquisition */ +#define MDF_ERROR_RSF_OVERRUN 0x00000002U /*!< Overrun occurs on reshape filter */ +#define MDF_ERROR_CLOCK_ABSENCE 0x00000004U /*!< Clock absence detection occurs */ +#define MDF_ERROR_SATURATION 0x00000010U /*!< Saturation detection occurs */ +#define MDF_ERROR_DMA 0x00000040U /*!< DMA error occurs */ +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) +#define MDF_ERROR_INVALID_CALLBACK 0x00000080U /*!< Invalid callback error occurs */ +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup MDF_ClockTriggerSource MDF output clock trigger source + * @{ + */ +#define MDF_CLOCK_TRIG_TRGO 0x00000000U +#define MDF_CLOCK_TRIG_EXTI15 MDF_CKGCR_TRGSRC_1 +/** + * @} + */ + +/** @defgroup MDF_ClockTriggerEdge MDF output clock trigger edge + * @{ + */ +#define MDF_CLOCK_TRIG_RISING_EDGE 0x00000000U /*!< Rising edge */ +#define MDF_CLOCK_TRIG_FALLING_EDGE MDF_CKGCR_TRGSENS /*!< Falling edge */ +/** + * @} + */ + +/** @defgroup MDF_OuputClockPins MDF output clock pins + * @{ + */ +#define MDF_OUTPUT_CLOCK_0 MDF_CKGCR_CCK0DIR /*!< MDF_CCK0 is used as output clock */ +#define MDF_OUTPUT_CLOCK_1 MDF_CKGCR_CCK1DIR /*!< MDF_CCK1 is used as output clock */ +#define MDF_OUTPUT_CLOCK_ALL (MDF_CKGCR_CCK0DIR | \ + MDF_CKGCR_CCK1DIR) /*!< MDF_CCK0 and MDF_CCK1 are used as output clock */ +/** + * @} + */ + +/** @defgroup MDF_SitfMode MDF serial interface mode + * @{ + */ +#define MDF_SITF_LF_MASTER_SPI_MODE 0x00000000U /*!< Low frequency master SPI mode */ +#define MDF_SITF_NORMAL_SPI_MODE MDF_SITFCR_SITFMOD_0 /*!< Normal SPI mode */ +#define MDF_SITF_MANCHESTER_FALLING_MODE MDF_SITFCR_SITFMOD_1 /*!< Manchester mode rising edge logic 0 + and falling edge logic 1 */ +#define MDF_SITF_MANCHESTER_RISING_MODE MDF_SITFCR_SITFMOD /*!< Manchester mode rising edge logic 1 + and falling edge logic 0 */ +/** + * @} + */ + +/** @defgroup MDF_SitfClockSource MDF serial interface clock source + * @{ + */ +#define MDF_SITF_CCK0_SOURCE 0x00000000U /*!< Common clock 0 source */ +#define MDF_SITF_CCK1_SOURCE MDF_SITFCR_SCKSRC_0 /*!< Common clock 1 source */ +/** + * @} + */ + +/** @defgroup MDF_FilterBitstream MDF filter bitstream + * @{ + */ +#define MDF_BITSTREAM0_RISING 0x00000000U +#define MDF_BITSTREAM0_FALLING MDF_BSMXCR_BSSEL_0 +/** + * @} + */ + +/** @defgroup MDF_ReshapeDecimationRatio MDF reshape filter decimation ratio + * @{ + */ +#define MDF_RSF_DECIMATION_RATIO_4 0x00000000U /*!< Reshape filter decimation ratio is 4 */ +#define MDF_RSF_DECIMATION_RATIO_1 MDF_DFLTRSFR_RSFLTD /*!< Reshape filter decimation ratio is 1 */ +/** + * @} + */ + +/** @defgroup MDF_HighPassCutOffFreq MDF high pass filter cut-off frequency + * @{ + */ +#define MDF_HPF_CUTOFF_0_000625FPCM 0x00000000U /*!< Cut-off frequency of 0.000625xFpcm */ +#define MDF_HPF_CUTOFF_0_00125FPCM MDF_DFLTRSFR_HPFC_0 /*!< Cut-off frequency of 0.00125xFpcm */ +#define MDF_HPF_CUTOFF_0_0025FPCM MDF_DFLTRSFR_HPFC_1 /*!< Cut-off frequency of 0.0025xFpcm */ +#define MDF_HPF_CUTOFF_0_0095FPCM MDF_DFLTRSFR_HPFC /*!< Cut-off frequency of 0.0095xFpcm */ +/** + * @} + */ + +/** @defgroup MDF_SadMode MDF sound activity detector mode + * @{ + */ +#define MDF_SAD_VOICE_ACTIVITY_DETECTOR 0x00000000U /*!< Voice activity detector */ +#define MDF_SAD_SOUND_DETECTOR MDF_SADCR_SADMOD_0 /*!< Sound detector */ +#define MDF_SAD_AMBIENT_NOISE_DETECTOR MDF_SADCR_SADMOD /*!< Ambient noise detector */ +/** + * @} + */ + +/** @defgroup MDF_SadFrameSize MDF sound activity detector frame size + * @{ + */ +#define MDF_SAD_8_PCM_SAMPLES 0x00000000U /*!< Frame size of 8 PCM samples */ +#define MDF_SAD_16_PCM_SAMPLES MDF_SADCR_FRSIZE_0 /*!< Frame size of 16 PCM samples */ +#define MDF_SAD_32_PCM_SAMPLES MDF_SADCR_FRSIZE_1 /*!< Frame size of 32 PCM samples */ +#define MDF_SAD_64_PCM_SAMPLES (MDF_SADCR_FRSIZE_0 | MDF_SADCR_FRSIZE_1) /*!< Frame size of 64 PCM samples */ +#define MDF_SAD_128_PCM_SAMPLES MDF_SADCR_FRSIZE_2 /*!< Frame size of 128 PCM samples */ +#define MDF_SAD_256_PCM_SAMPLES (MDF_SADCR_FRSIZE_0 | MDF_SADCR_FRSIZE_2) /*!< Frame size of 256 PCM samples */ +#define MDF_SAD_512_PCM_SAMPLES MDF_SADCR_FRSIZE /*!< Frame size of 512 PCM samples */ +/** + * @} + */ + +/** @defgroup MDF_SadSoundTriggerEvent MDF sound activity detector trigger event + * @{ + */ +#define MDF_SAD_ENTER_DETECT 0x00000000U /*!< Event when SAD enters in detect state */ +#define MDF_SAD_ENTER_EXIT_DETECT MDF_SADCR_DETCFG /*!< Event when SAD enters or exits from detect state */ +/** + * @} + */ + +/** @defgroup MDF_SadDataMemoryTransfer MDF sound activity detector data memory transfer mode + * @{ + */ +#define MDF_SAD_NO_MEMORY_TRANSFER 0x00000000U /*!< No memory transfer */ +#define MDF_SAD_MEMORY_TRANSFER_IN_DETECT MDF_SADCR_DATCAP_0 /*!< Memory transfer only in detect state */ +#define MDF_SAD_MEMORY_TRANSFER_ALWAYS MDF_SADCR_DATCAP /*!< Memory transfer always */ +/** + * @} + */ + +/** @defgroup MDF_SadHangoverWindow MDF sound activity detector data hangover time window + * @{ + */ +#define MDF_SAD_HANGOVER_4_FRAMES 0x00000000U /*!< Hangover window of 4 frames */ +#define MDF_SAD_HANGOVER_8_FRAMES MDF_SADCFGR_HGOVR_0 /*!< Hangover window of 8 frames */ +#define MDF_SAD_HANGOVER_16_FRAMES MDF_SADCFGR_HGOVR_1 /*!< Hangover window of 16 frames */ +#define MDF_SAD_HANGOVER_32_FRAMES (MDF_SADCFGR_HGOVR_0 | \ + MDF_SADCFGR_HGOVR_1) /*!< Hangover window of 32 frames */ +#define MDF_SAD_HANGOVER_64_FRAMES MDF_SADCFGR_HGOVR_2 /*!< Hangover window of 64 frames */ +#define MDF_SAD_HANGOVER_128_FRAMES (MDF_SADCFGR_HGOVR_0 | \ + MDF_SADCFGR_HGOVR_2) /*!< Hangover window of 128 frames */ +#define MDF_SAD_HANGOVER_256_FRAMES (MDF_SADCFGR_HGOVR_1 | \ + MDF_SADCFGR_HGOVR_2) /*!< Hangover window of 256 frames */ +#define MDF_SAD_HANGOVER_512_FRAMES (MDF_SADCFGR_HGOVR_0 | \ + MDF_SADCFGR_HGOVR_1 | \ + MDF_SADCFGR_HGOVR_2) /*!< Hangover window of 512 frames */ +/** + * @} + */ + +/** @defgroup MDF_SadLearningFrames MDF sound activity detector data learning frames + * @{ + */ +#define MDF_SAD_LEARNING_2_FRAMES 0x00000000U /*!< 2 learning frames */ +#define MDF_SAD_LEARNING_4_FRAMES MDF_SADCFGR_LFRNB_0 /*!< 4 learning frames */ +#define MDF_SAD_LEARNING_8_FRAMES MDF_SADCFGR_LFRNB_1 /*!< 8 learning frames */ +#define MDF_SAD_LEARNING_16_FRAMES (MDF_SADCFGR_LFRNB_0 | MDF_SADCFGR_LFRNB_1) /*!< 16 learning frames */ +#define MDF_SAD_LEARNING_32_FRAMES MDF_SADCFGR_LFRNB /*!< 32 learning frames */ +/** + * @} + */ + +/** @defgroup MDF_SadSignalNoiseThreshold MDF sound activity detector data signal to noise threshold + * @{ + */ +#define MDF_SAD_SIGNAL_NOISE_3_5DB 0x00000000U /*!< Signal to noise threshold is 3.5dB */ +#define MDF_SAD_SIGNAL_NOISE_6DB MDF_SADCFGR_SNTHR_0 /*!< Signal to noise threshold is 6dB */ +#define MDF_SAD_SIGNAL_NOISE_9_5DB MDF_SADCFGR_SNTHR_1 /*!< Signal to noise threshold is 9.5dB */ +#define MDF_SAD_SIGNAL_NOISE_12DB (MDF_SADCFGR_SNTHR_0 | \ + MDF_SADCFGR_SNTHR_1) /*!< Signal to noise threshold is 12dB */ +#define MDF_SAD_SIGNAL_NOISE_15_6DB MDF_SADCFGR_SNTHR_2 /*!< Signal to noise threshold is 15.6dB */ +#define MDF_SAD_SIGNAL_NOISE_18DB (MDF_SADCFGR_SNTHR_0 | \ + MDF_SADCFGR_SNTHR_2) /*!< Signal to noise threshold is 18dB */ +#define MDF_SAD_SIGNAL_NOISE_21_6DB (MDF_SADCFGR_SNTHR_1 | \ + MDF_SADCFGR_SNTHR_2) /*!< Signal to noise threshold is 21.6dB */ +#define MDF_SAD_SIGNAL_NOISE_24_1DB (MDF_SADCFGR_SNTHR_0 | \ + MDF_SADCFGR_SNTHR_1 | \ + MDF_SADCFGR_SNTHR_2) /*!< Signal to noise threshold is 24.1dB */ +#define MDF_SAD_SIGNAL_NOISE_27_6DB MDF_SADCFGR_SNTHR_3 /*!< Signal to noise threshold is 27.6dB */ +#define MDF_SAD_SIGNAL_NOISE_30_1DB (MDF_SADCFGR_SNTHR_0 | \ + MDF_SADCFGR_SNTHR_3) /*!< Signal to noise threshold is 30.1dB */ +/** + * @} + */ + +/** @defgroup MDF_FilterTriggerSource MDF filter trigger source + * @{ + */ +#define MDF_FILTER_TRIG_TRGO 0x00000000U +#define MDF_FILTER_TRIG_EXTI15 MDF_DFLTCR_TRGSRC_1 +/** + * @} + */ + +/** @defgroup MDF_FilterTriggerEdge MDF filter trigger edge + * @{ + */ +#define MDF_FILTER_TRIG_RISING_EDGE 0x00000000U /*!< Rising edge */ +#define MDF_FILTER_TRIG_FALLING_EDGE MDF_DFLTCR_TRGSENS /*!< Falling edge */ +/** + * @} + */ + +/** @defgroup MDF_DataSource MDF data source + * @{ + */ +#define MDF_DATA_SOURCE_BSMX 0x00000000U /*!< Data from bitstream matrix */ +#define MDF_DATA_SOURCE_ADCITF1 MDF_DFLTCICR_DATSRC_1 /*!< Data from ADC interface 1 */ +#define MDF_DATA_SOURCE_ADCITF2 MDF_DFLTCICR_DATSRC /*!< Data from ADC interface 2 */ +/** + * @} + */ + +/** @defgroup MDF_CicMode MDF CIC mode + * @{ + */ +#define MDF_ONE_FILTER_SINC4 MDF_DFLTCICR_CICMOD_2 /*!< One filter in Sinc4 order */ +#define MDF_ONE_FILTER_SINC5 (MDF_DFLTCICR_CICMOD_0 | \ + MDF_DFLTCICR_CICMOD_2) /*!< One filter in Sinc5 order */ +/** + * @} + */ + +/** @defgroup MDF_AcquisitionMode MDF acquisition mode + * @{ + */ +#define MDF_MODE_ASYNC_CONT 0x00000000U /*!< Asynchronous, continuous acquisition mode */ +#define MDF_MODE_ASYNC_SINGLE MDF_DFLTCR_ACQMOD_0 /*!< Asynchronous, single-shot acquisition mode. + @note Not available with SAD usage */ +#define MDF_MODE_SYNC_CONT MDF_DFLTCR_ACQMOD_1 /*!< Synchronous, continuous acquisition mode */ +#define MDF_MODE_SYNC_SINGLE (MDF_DFLTCR_ACQMOD_0 | \ + MDF_DFLTCR_ACQMOD_1) /*!< Synchronous, single-shot acquisition mode. + @note Not available with SAD usage */ +#define MDF_MODE_WINDOW_CONT MDF_DFLTCR_ACQMOD_2 /*!< Window, continuous acquisition mode. + @note Not available with SAD usage */ +/** + * @} + */ + +/** @defgroup MDF_FifoThreshold MDF RXFIFO threshold + * @{ + */ +#define MDF_FIFO_THRESHOLD_NOT_EMPTY 0x00000000U /*!< Event generated when RXFIFO is not empty */ +#define MDF_FIFO_THRESHOLD_HALF_FULL MDF_DFLTCR_FTH /*!< Event generated when RXFIFO is half_full */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup MDF_Exported_Macros MDF Exported Macros + * @{ + */ + +/** @brief Reset MDF handle state. + * @param __HANDLE__ MDF handle. + * @retval None + */ +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) +#define __HAL_MDF_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_MDF_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ +#define __HAL_MDF_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDF_STATE_RESET) +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup MDF_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/** @addtogroup MDF_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_MDF_Init(MDF_HandleTypeDef *hmdf); +HAL_StatusTypeDef HAL_MDF_DeInit(MDF_HandleTypeDef *hmdf); +void HAL_MDF_MspInit(MDF_HandleTypeDef *hmdf); +void HAL_MDF_MspDeInit(MDF_HandleTypeDef *hmdf); +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_MDF_RegisterCallback(MDF_HandleTypeDef *hmdf, + HAL_MDF_CallbackIDTypeDef CallbackID, + pMDF_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_MDF_UnRegisterCallback(MDF_HandleTypeDef *hmdf, + HAL_MDF_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_MDF_RegisterSndLvlCallback(MDF_HandleTypeDef *hmdf, + pMDF_SndLvlCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_MDF_UnRegisterSndLvlCallback(MDF_HandleTypeDef *hmdf); +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Acquisition functions *****************************************************/ +/** @addtogroup MDF_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_MDF_PollForAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout); +HAL_StatusTypeDef HAL_MDF_GetAcqValue(const MDF_HandleTypeDef *hmdf, int32_t *pValue); +HAL_StatusTypeDef HAL_MDF_AcqStop(MDF_HandleTypeDef *hmdf); +HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_MDF_AcqStop_IT(MDF_HandleTypeDef *hmdf); +HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig, + const MDF_DmaConfigTypeDef *pDmaConfig); +HAL_StatusTypeDef HAL_MDF_AcqStop_DMA(MDF_HandleTypeDef *hmdf); +HAL_StatusTypeDef HAL_MDF_GenerateTrgo(const MDF_HandleTypeDef *hmdf); +HAL_StatusTypeDef HAL_MDF_SetDelay(MDF_HandleTypeDef *hmdf, uint32_t Delay); +HAL_StatusTypeDef HAL_MDF_GetDelay(const MDF_HandleTypeDef *hmdf, uint32_t *pDelay); +HAL_StatusTypeDef HAL_MDF_SetGain(MDF_HandleTypeDef *hmdf, int32_t Gain); +HAL_StatusTypeDef HAL_MDF_GetGain(const MDF_HandleTypeDef *hmdf, int32_t *pGain); +HAL_StatusTypeDef HAL_MDF_PollForSndLvl(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pSoundLevel, + uint32_t *pAmbientNoise); +HAL_StatusTypeDef HAL_MDF_PollForSad(MDF_HandleTypeDef *hmdf, uint32_t Timeout); +void HAL_MDF_AcqCpltCallback(MDF_HandleTypeDef *hmdf); +void HAL_MDF_AcqHalfCpltCallback(MDF_HandleTypeDef *hmdf); +void HAL_MDF_SndLvlCallback(MDF_HandleTypeDef *hmdf, uint32_t SoundLevel, uint32_t AmbientNoise); +void HAL_MDF_SadCallback(MDF_HandleTypeDef *hmdf); +/** + * @} + */ + +/* Clock absence detection functions *****************************************/ +/** @addtogroup MDF_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_MDF_PollForCkab(MDF_HandleTypeDef *hmdf, uint32_t Timeout); +HAL_StatusTypeDef HAL_MDF_CkabStart_IT(MDF_HandleTypeDef *hmdf); +HAL_StatusTypeDef HAL_MDF_CkabStop_IT(MDF_HandleTypeDef *hmdf); +/** + * @} + */ + +/* Generic functions *********************************************************/ +/** @addtogroup MDF_Exported_Functions_Group4 + * @{ + */ +void HAL_MDF_IRQHandler(MDF_HandleTypeDef *hmdf); +void HAL_MDF_ErrorCallback(MDF_HandleTypeDef *hmdf); +HAL_MDF_StateTypeDef HAL_MDF_GetState(const MDF_HandleTypeDef *hmdf); +uint32_t HAL_MDF_GetError(const MDF_HandleTypeDef *hmdf); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup MDF_Private_Macros MDF Private Macros + * @{ + */ +#define IS_MDF_FILTER_BITSTREAM(PARAM) (((PARAM) == MDF_BITSTREAM0_RISING) || \ + ((PARAM) == MDF_BITSTREAM0_FALLING)) + +#define IS_MDF_PROC_CLOCK_DIVIDER(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 128U)) + +#define IS_MDF_OUTPUT_CLOCK_PINS(PARAM) (((PARAM) == MDF_OUTPUT_CLOCK_0) || \ + ((PARAM) == MDF_OUTPUT_CLOCK_1) || \ + ((PARAM) == MDF_OUTPUT_CLOCK_ALL)) + +#define IS_MDF_OUTPUT_CLOCK_DIVIDER(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 16U)) + +#define IS_MDF_OUTPUT_CLOCK_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_CLOCK_TRIG_TRGO) || \ + ((PARAM) == MDF_CLOCK_TRIG_EXTI15)) + +#define IS_MDF_OUTPUT_CLOCK_TRIGGER_EDGE(PARAM) (((PARAM) == MDF_CLOCK_TRIG_RISING_EDGE) || \ + ((PARAM) == MDF_CLOCK_TRIG_FALLING_EDGE)) + +#define IS_MDF_SITF_MODE(PARAM) (((PARAM) == MDF_SITF_LF_MASTER_SPI_MODE) || \ + ((PARAM) == MDF_SITF_NORMAL_SPI_MODE) || \ + ((PARAM) == MDF_SITF_MANCHESTER_FALLING_MODE) || \ + ((PARAM) == MDF_SITF_MANCHESTER_RISING_MODE)) + +#define IS_MDF_SITF_CLOCK_SOURCE(PARAM) (((PARAM) == MDF_SITF_CCK0_SOURCE) || \ + ((PARAM) == MDF_SITF_CCK1_SOURCE)) + +#define IS_MDF_SITF_THRESHOLD(PARAM) ((4U <= (PARAM)) && ((PARAM) <= 31U)) + +#define IS_MDF_CIC_MODE(PARAM) (((PARAM) == MDF_ONE_FILTER_SINC4) || \ + ((PARAM) == MDF_ONE_FILTER_SINC5)) + +#define IS_MDF_ACQUISITION_MODE(PARAM) (((PARAM) == MDF_MODE_ASYNC_CONT) || \ + ((PARAM) == MDF_MODE_ASYNC_SINGLE) || \ + ((PARAM) == MDF_MODE_SYNC_CONT) || \ + ((PARAM) == MDF_MODE_SYNC_SINGLE) || \ + ((PARAM) == MDF_MODE_WINDOW_CONT)) + +#define IS_MDF_DISCARD_SAMPLES(PARAM) ((PARAM) <= 255U) + +#define IS_MDF_FIFO_THRESHOLD(PARAM) (((PARAM) == MDF_FIFO_THRESHOLD_NOT_EMPTY) || \ + ((PARAM) == MDF_FIFO_THRESHOLD_HALF_FULL)) + +#define IS_MDF_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_FILTER_TRIG_TRGO) || \ + ((PARAM) == MDF_FILTER_TRIG_EXTI15)) + +#define IS_MDF_TRIGGER_EDGE(PARAM) (((PARAM) == MDF_FILTER_TRIG_RISING_EDGE) || \ + ((PARAM) == MDF_FILTER_TRIG_FALLING_EDGE)) + +#define IS_MDF_DATA_SOURCE(PARAM) (((PARAM) == MDF_DATA_SOURCE_BSMX) || \ + ((PARAM) == MDF_DATA_SOURCE_ADCITF1) || \ + ((PARAM) == MDF_DATA_SOURCE_ADCITF2)) + +#define IS_MDF_DECIMATION_RATIO(PARAM) ((2U <= (PARAM)) && ((PARAM) <= 512U)) + +#define IS_MDF_GAIN(PARAM) ((-16 <= (PARAM)) && ((PARAM) <= 24)) + +#define IS_MDF_DELAY(PARAM) ((PARAM) <= 127U) + +#define IS_MDF_RSF_DECIMATION_RATIO(PARAM) (((PARAM) == MDF_RSF_DECIMATION_RATIO_4) || \ + ((PARAM) == MDF_RSF_DECIMATION_RATIO_1)) + +#define IS_MDF_HPF_CUTOFF_FREQ(PARAM) (((PARAM) == MDF_HPF_CUTOFF_0_000625FPCM) || \ + ((PARAM) == MDF_HPF_CUTOFF_0_00125FPCM) || \ + ((PARAM) == MDF_HPF_CUTOFF_0_0025FPCM) || \ + ((PARAM) == MDF_HPF_CUTOFF_0_0095FPCM)) + +#define IS_MDF_SAD_MODE(PARAM) (((PARAM) == MDF_SAD_VOICE_ACTIVITY_DETECTOR) || \ + ((PARAM) == MDF_SAD_SOUND_DETECTOR) || \ + ((PARAM) == MDF_SAD_AMBIENT_NOISE_DETECTOR)) + +#define IS_MDF_SAD_FRAME_SIZE(PARAM) (((PARAM) == MDF_SAD_8_PCM_SAMPLES) || \ + ((PARAM) == MDF_SAD_16_PCM_SAMPLES) || \ + ((PARAM) == MDF_SAD_32_PCM_SAMPLES) || \ + ((PARAM) == MDF_SAD_64_PCM_SAMPLES) || \ + ((PARAM) == MDF_SAD_128_PCM_SAMPLES) || \ + ((PARAM) == MDF_SAD_256_PCM_SAMPLES) || \ + ((PARAM) == MDF_SAD_512_PCM_SAMPLES)) + +#define IS_MDF_SAD_SOUND_TRIGGER(PARAM) (((PARAM) == MDF_SAD_ENTER_DETECT) || \ + ((PARAM) == MDF_SAD_ENTER_EXIT_DETECT)) + +#define IS_MDF_SAD_DATA_MEMORY_TRANSFER(PARAM) (((PARAM) == MDF_SAD_NO_MEMORY_TRANSFER) || \ + ((PARAM) == MDF_SAD_MEMORY_TRANSFER_IN_DETECT) || \ + ((PARAM) == MDF_SAD_MEMORY_TRANSFER_ALWAYS)) + +#define IS_MDF_SAD_MIN_NOISE_LEVEL(PARAM) ((PARAM) <= 8191U) + +#define IS_MDF_SAD_HANGOVER_WINDOW(PARAM) (((PARAM) == MDF_SAD_HANGOVER_4_FRAMES) || \ + ((PARAM) == MDF_SAD_HANGOVER_8_FRAMES) || \ + ((PARAM) == MDF_SAD_HANGOVER_16_FRAMES) || \ + ((PARAM) == MDF_SAD_HANGOVER_32_FRAMES) || \ + ((PARAM) == MDF_SAD_HANGOVER_64_FRAMES) || \ + ((PARAM) == MDF_SAD_HANGOVER_128_FRAMES) || \ + ((PARAM) == MDF_SAD_HANGOVER_256_FRAMES) || \ + ((PARAM) == MDF_SAD_HANGOVER_512_FRAMES)) + +#define IS_MDF_SAD_LEARNING_FRAMES(PARAM) (((PARAM) == MDF_SAD_LEARNING_2_FRAMES) || \ + ((PARAM) == MDF_SAD_LEARNING_4_FRAMES) || \ + ((PARAM) == MDF_SAD_LEARNING_8_FRAMES) || \ + ((PARAM) == MDF_SAD_LEARNING_16_FRAMES) || \ + ((PARAM) == MDF_SAD_LEARNING_32_FRAMES)) + +#define IS_MDF_SAD_AMBIENT_NOISE_SLOPE(PARAM) ((PARAM) <= 7U) + +#define IS_MDF_SAD_SIGNAL_NOISE_THRESHOLD(PARAM) (((PARAM) == MDF_SAD_SIGNAL_NOISE_3_5DB) || \ + ((PARAM) == MDF_SAD_SIGNAL_NOISE_6DB) || \ + ((PARAM) == MDF_SAD_SIGNAL_NOISE_9_5DB) || \ + ((PARAM) == MDF_SAD_SIGNAL_NOISE_12DB) || \ + ((PARAM) == MDF_SAD_SIGNAL_NOISE_15_6DB) || \ + ((PARAM) == MDF_SAD_SIGNAL_NOISE_18DB) || \ + ((PARAM) == MDF_SAD_SIGNAL_NOISE_21_6DB) || \ + ((PARAM) == MDF_SAD_SIGNAL_NOISE_24_1DB) || \ + ((PARAM) == MDF_SAD_SIGNAL_NOISE_27_6DB) || \ + ((PARAM) == MDF_SAD_SIGNAL_NOISE_30_1DB)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_MDF_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mdios.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mdios.h new file mode 100644 index 00000000000..5120e1905a9 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mdios.h @@ -0,0 +1,576 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_mdios.h + * @author MCD Application Team + * @brief Header file of MDIOS HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_MDIOS_H +#define STM32H7RSxx_HAL_MDIOS_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +#if defined (MDIOS) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup MDIOS + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup MDIOS_Exported_Types MDIOS Exported Types + * @{ + */ + +/** @defgroup MDIOS_Exported_Types_Group1 MDIOS State structures definition + * @{ + */ + +typedef enum +{ + HAL_MDIOS_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ + HAL_MDIOS_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_MDIOS_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_MDIOS_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_MDIOS_StateTypeDef; + +/** + * @} + */ + +/** @defgroup MDIOS_Exported_Types_Group2 MDIOS Init Structure definition + * @{ + */ + +typedef struct +{ + uint32_t PortAddress; /*!< Specifies the MDIOS port address. + This parameter can be a value from 0 to 31 */ + uint32_t PreambleCheck; /*!< Specifies whether the preamble check is enabled or disabled. + This parameter can be a value of @ref MDIOS_Preamble_Check */ +} MDIOS_InitTypeDef; + +/** + * @} + */ + +/** @defgroup MDIOS_Exported_Types_Group4 MDIOS handle Structure definition + * @{ + */ + +#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) +typedef struct __MDIOS_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ +{ + MDIOS_TypeDef *Instance; /*!< Register base address */ + + MDIOS_InitTypeDef Init; /*!< MDIOS Init Structure */ + + __IO HAL_MDIOS_StateTypeDef State; /*!< MDIOS communication state + This parameter can be a value of of @ref HAL_MDIOS_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< Holds the global Error code of the MDIOS HAL status machine + This parameter can be a value of of @ref MDIOS_Error_Code */ + + HAL_LockTypeDef Lock; /*!< MDIOS Lock */ + +#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) + + void (* WriteCpltCallback)(struct __MDIOS_HandleTypeDef *hmdios); /*!< MDIOS Write Complete Callback */ + void (* ReadCpltCallback)(struct __MDIOS_HandleTypeDef *hmdios); /*!< MDIOS Read Complete Callback */ + void (* ErrorCallback)(struct __MDIOS_HandleTypeDef *hmdios); /*!< MDIOS Error Callback */ + void (* WakeUpCallback)(struct __MDIOS_HandleTypeDef *hmdios); /*!< MDIOS Wake UP Callback */ + + void (* MspInitCallback)(struct __MDIOS_HandleTypeDef *hmdios); /*!< MDIOS Msp Init callback */ + void (* MspDeInitCallback)(struct __MDIOS_HandleTypeDef *hmdios); /*!< MDIOS Msp DeInit callback */ + +#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ +} MDIOS_HandleTypeDef; + +/** + * @} + */ + +#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) +/** + * @brief HAL MDIOS Callback ID enumeration definition + */ +typedef enum +{ + HAL_MDIOS_MSPINIT_CB_ID = 0x00U, /*!< MDIOS MspInit callback ID */ + HAL_MDIOS_MSPDEINIT_CB_ID = 0x01U, /*!< MDIOS MspDeInit callback ID */ + + HAL_MDIOS_WRITE_COMPLETE_CB_ID = 0x02U, /*!< MDIOS Write Complete Callback ID */ + HAL_MDIOS_READ_COMPLETE_CB_ID = 0x03U, /*!< MDIOS Read Complete Callback ID */ + HAL_MDIOS_ERROR_CB_ID = 0x04U, /*!< MDIOS Error Callback ID */ + HAL_MDIOS_WAKEUP_CB_ID = 0x05U /*!< MDIOS Wake UP Callback ID */ +} HAL_MDIOS_CallbackIDTypeDef; + +/** + * @brief HAL MDIOS Callback pointer definition + */ +typedef void (*pMDIOS_CallbackTypeDef)(MDIOS_HandleTypeDef *hmdios); /*!< pointer to an MDIOS callback function */ + +#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup MDIOS_Exported_Constants MDIOS Exported Constants + * @{ + */ + +/** @defgroup MDIOS_Preamble_Check MDIOS Preamble Check + * @{ + */ +#define MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U) +#define MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC +/** + * @} + */ + +/** @defgroup MDIOS_Input_Output_Registers_Definitions MDIOS Input Output Registers Definitions + * @{ + */ +#define MDIOS_REG0 ((uint32_t)0x00000000U) +#define MDIOS_REG1 ((uint32_t)0x00000001U) +#define MDIOS_REG2 ((uint32_t)0x00000002U) +#define MDIOS_REG3 ((uint32_t)0x00000003U) +#define MDIOS_REG4 ((uint32_t)0x00000004U) +#define MDIOS_REG5 ((uint32_t)0x00000005U) +#define MDIOS_REG6 ((uint32_t)0x00000006U) +#define MDIOS_REG7 ((uint32_t)0x00000007U) +#define MDIOS_REG8 ((uint32_t)0x00000008U) +#define MDIOS_REG9 ((uint32_t)0x00000009U) +#define MDIOS_REG10 ((uint32_t)0x0000000AU) +#define MDIOS_REG11 ((uint32_t)0x0000000BU) +#define MDIOS_REG12 ((uint32_t)0x0000000CU) +#define MDIOS_REG13 ((uint32_t)0x0000000DU) +#define MDIOS_REG14 ((uint32_t)0x0000000EU) +#define MDIOS_REG15 ((uint32_t)0x0000000FU) +#define MDIOS_REG16 ((uint32_t)0x00000010U) +#define MDIOS_REG17 ((uint32_t)0x00000011U) +#define MDIOS_REG18 ((uint32_t)0x00000012U) +#define MDIOS_REG19 ((uint32_t)0x00000013U) +#define MDIOS_REG20 ((uint32_t)0x00000014U) +#define MDIOS_REG21 ((uint32_t)0x00000015U) +#define MDIOS_REG22 ((uint32_t)0x00000016U) +#define MDIOS_REG23 ((uint32_t)0x00000017U) +#define MDIOS_REG24 ((uint32_t)0x00000018U) +#define MDIOS_REG25 ((uint32_t)0x00000019U) +#define MDIOS_REG26 ((uint32_t)0x0000001AU) +#define MDIOS_REG27 ((uint32_t)0x0000001BU) +#define MDIOS_REG28 ((uint32_t)0x0000001CU) +#define MDIOS_REG29 ((uint32_t)0x0000001DU) +#define MDIOS_REG30 ((uint32_t)0x0000001EU) +#define MDIOS_REG31 ((uint32_t)0x0000001FU) +/** + * @} + */ + +/** @defgroup MDIOS_Registers_Flags MDIOS Registers Flags + * @{ + */ +#define MDIOS_REG0_FLAG ((uint32_t)0x00000001U) +#define MDIOS_REG1_FLAG ((uint32_t)0x00000002U) +#define MDIOS_REG2_FLAG ((uint32_t)0x00000004U) +#define MDIOS_REG3_FLAG ((uint32_t)0x00000008U) +#define MDIOS_REG4_FLAG ((uint32_t)0x00000010U) +#define MDIOS_REG5_FLAG ((uint32_t)0x00000020U) +#define MDIOS_REG6_FLAG ((uint32_t)0x00000040U) +#define MDIOS_REG7_FLAG ((uint32_t)0x00000080U) +#define MDIOS_REG8_FLAG ((uint32_t)0x00000100U) +#define MDIOS_REG9_FLAG ((uint32_t)0x00000200U) +#define MDIOS_REG10_FLAG ((uint32_t)0x00000400U) +#define MDIOS_REG11_FLAG ((uint32_t)0x00000800U) +#define MDIOS_REG12_FLAG ((uint32_t)0x00001000U) +#define MDIOS_REG13_FLAG ((uint32_t)0x00002000U) +#define MDIOS_REG14_FLAG ((uint32_t)0x00004000U) +#define MDIOS_REG15_FLAG ((uint32_t)0x00008000U) +#define MDIOS_REG16_FLAG ((uint32_t)0x00010000U) +#define MDIOS_REG17_FLAG ((uint32_t)0x00020000U) +#define MDIOS_REG18_FLAG ((uint32_t)0x00040000U) +#define MDIOS_REG19_FLAG ((uint32_t)0x00080000U) +#define MDIOS_REG20_FLAG ((uint32_t)0x00100000U) +#define MDIOS_REG21_FLAG ((uint32_t)0x00200000U) +#define MDIOS_REG22_FLAG ((uint32_t)0x00400000U) +#define MDIOS_REG23_FLAG ((uint32_t)0x00800000U) +#define MDIOS_REG24_FLAG ((uint32_t)0x01000000U) +#define MDIOS_REG25_FLAG ((uint32_t)0x02000000U) +#define MDIOS_REG26_FLAG ((uint32_t)0x04000000U) +#define MDIOS_REG27_FLAG ((uint32_t)0x08000000U) +#define MDIOS_REG28_FLAG ((uint32_t)0x10000000U) +#define MDIOS_REG29_FLAG ((uint32_t)0x20000000U) +#define MDIOS_REG30_FLAG ((uint32_t)0x40000000U) +#define MDIOS_REG31_FLAG ((uint32_t)0x80000000U) +#define MDIOS_ALLREG_FLAG ((uint32_t)0xFFFFFFFFU) +/** + * @} + */ + +/** @defgroup MDIOS_Interrupt_sources Interrupt Sources + * @{ + */ +#define MDIOS_IT_WRITE MDIOS_CR_WRIE +#define MDIOS_IT_READ MDIOS_CR_RDIE +#define MDIOS_IT_ERROR MDIOS_CR_EIE +/** + * @} + */ + +/** @defgroup MDIOS_Interrupt_Flags MDIOS Interrupt Flags + * @{ + */ +#define MDIOS_TURNAROUND_ERROR_FLAG MDIOS_SR_TERF +#define MDIOS_START_ERROR_FLAG MDIOS_SR_SERF +#define MDIOS_PREAMBLE_ERROR_FLAG MDIOS_SR_PERF +/** + * @} + */ + +/** @defgroup MDIOS_Error_Code MDIOS Error Code + * @{ + */ +#define HAL_MDIOS_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_MDIOS_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Busy error */ +#define HAL_MDIOS_ERROR_BUSY ((uint32_t)0x00000002U) /*!< Parameter error */ +#define HAL_MDIOS_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */ +#define HAL_MDIOS_ERROR_DATA ((uint32_t)0x00000010U) /*!< Data transfer error */ +#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) +#define HAL_MDIOS_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ +#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup MDIOS_Wakeup_Line MDIOS Wakeup Line + * @{ + */ +#define MDIOS_WAKEUP_EXTI_LINE ((uint32_t)0x00000400) /* !< 42 - 32 = 10 */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup MDIOS_Exported_Macros MDIOS Exported Macros + * @{ + */ + +/** @brief Reset MDIOS handle state + * @param __HANDLE__: MDIOS handle. + * @retval None + */ +#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) +#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_MDIOS_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET) +#endif /*USE_HAL_MDIOS_REGISTER_CALLBACKS */ + +/** + * @brief Enable/Disable the MDIOS peripheral. + * @param __HANDLE__: specifies the MDIOS handle. + * @retval None + */ +#define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN) +#define __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN) + + +/** + * @brief Enable the MDIOS device interrupt. + * @param __HANDLE__: specifies the MDIOS handle. + * @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg MDIOS_IT_WRITE: Register write interrupt + * @arg MDIOS_IT_READ: Register read interrupt + * @arg MDIOS_IT_ERROR: Error interrupt + * @retval None + */ +#define __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the MDIOS device interrupt. + * @param __HANDLE__: specifies the MDIOS handle. + * @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg MDIOS_IT_WRITE: Register write interrupt + * @arg MDIOS_IT_READ: Register read interrupt + * @arg MDIOS_IT_ERROR: Error interrupt + * @retval None + */ +#define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +/** @brief Set MDIOS slave get write register flag + * @param __HANDLE__: specifies the MDIOS handle. + * @param __FLAG__: specifies the write register flag + * @retval The state of write flag + */ +#define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WRFR & (__FLAG__)) + +/** @brief MDIOS slave get read register flag + * @param __HANDLE__: specifies the MDIOS handle. + * @param __FLAG__: specifies the read register flag + * @retval The state of read flag + */ +#define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RDFR & (__FLAG__)) + +/** @brief MDIOS slave get interrupt + * @param __HANDLE__: specifies the MDIOS handle. + * @param __FLAG__ : specifies the Error flag. + * This parameter can be one or a combination of the following values: + * @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt + * @arg MDIOS_START_ERROR_FLAG: Register read interrupt + * @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt + * @retval The state of the error flag + */ +#define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__)) + +/** @brief MDIOS slave clear interrupt + * @param __HANDLE__: specifies the MDIOS handle. + * @param __FLAG__ : specifies the Error flag. + * This parameter can be one or a combination of the following values: + * @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt + * @arg MDIOS_START_ERROR_FLAG: Register read interrupt + * @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt + * @retval none + */ +#define __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__) + +/** + * @brief Checks whether the specified MDIOS interrupt is set or not. + * @param __HANDLE__: specifies the MDIOS handle. + * @param __INTERRUPT__ : specifies the MDIOS interrupt sources + * This parameter can be one or a combination of the following values: + * @arg MDIOS_IT_WRITE: Register write interrupt + * @arg MDIOS_IT_READ: Register read interrupt + * @arg MDIOS_IT_ERROR: Error interrupt + * @retval The state of the interrupt source + */ +#define __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) + +/** + * @brief Enable the MDIOS WAKEUP Exti Line. + * @param __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be enabled. + * This parameter can be: + * @arg MDIOS_WAKEUP_EXTI_LINE + * @retval None. + */ +#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI->IMR2 |= (__EXTI_LINE__)) + +/** + * @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not. + * @param __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared. + * This parameter can be: + * @arg MDIOS_WAKEUP_EXTI_LINE + * @retval EXTI MDIOS WAKEUP Line Status. + */ +#define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR2 & (__EXTI_LINE__)) + +/** + * @brief Clear the MDIOS WAKEUP Exti flag. + * @param __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared. + * This parameter can be: + * @arg MDIOS_WAKEUP_EXTI_LINE + * @retval None. + */ +#define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR2 = (__EXTI_LINE__)) + +/** + * @brief enable rising edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled. + * This parameter can be: + * @arg MDIOS_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR2 &= ~(__EXTI_LINE__)); \ + (EXTI->RTSR2 |= (__EXTI_LINE__)) + +/** + * @brief enable falling edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled. + * This parameter can be: + * @arg MDIOS_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 &= ~(__EXTI_LINE__));\ + (EXTI->FTSR2 |= (__EXTI_LINE__)) + +/** + * @brief enable falling edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled. + * This parameter can be: + * @arg MDIOS_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 |= (__EXTI_LINE__));\ + (EXTI->FTSR2 |= (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled. + * This parameter can be: + * @arg MDIOS_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER2 |= (__EXTI_LINE__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions + * @{ + */ + +/** @addtogroup MDIOS_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios); +HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios); +void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios); +void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_MDIOS_RegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID, + pMDIOS_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup MDIOS_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data); +HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData); + +uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios); +uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios); +HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum); +HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum); + +HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios); +void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios); +void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios); +void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios); +void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios); +void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios); +/** + * @} + */ + +/** @addtogroup MDIOS_Exported_Functions_Group3 + * @{ + */ +uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios); +HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup MDIOS_Private_Types MDIOS Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup MDIOS_Private_Variables MDIOS Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup MDIOS_Private_Constants MDIOS Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup MDIOS_Private_Macros MDIOS Private Macros + * @{ + */ + +#define IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32U) + +#define IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32U) + +#define IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__) (((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || \ + ((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MDIOS_Private_Functions MDIOS Private Functions + * @{ + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* MDIOS */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_MDIOS_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mmc.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mmc.h new file mode 100644 index 00000000000..6f1497ca98e --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mmc.h @@ -0,0 +1,873 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_mmc.h + * @author MCD Application Team + * @brief Header file of MMC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_MMC_H +#define STM32H7RSxx_HAL_MMC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_sdmmc.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#if defined (SDMMC1) || defined (SDMMC2) + +/** @addtogroup MMC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup MMC_Exported_Types MMC Exported Types + * @{ + */ + +/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure + * @{ + */ +typedef enum +{ + HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), /*!< MMC not yet initialized or disabled */ + HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), /*!< MMC initialized and ready for use */ + HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< MMC Timeout state */ + HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */ + HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */ + HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */ + HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfer State */ + HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */ +} HAL_MMC_StateTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure + * @{ + */ +typedef uint32_t HAL_MMC_CardStateTypeDef; + +#define HAL_MMC_CARD_IDLE 0x00000000U /*!< Card is in idle state (can't be checked by CMD13) */ +#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready (can't be checked by CMD13) */ +#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state (can't be checked by CMD13) */ +#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ +#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ +#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ +#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ +#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ +#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ +#define HAL_MMC_CARD_BUSTEST 0x00000009U /*!< Card is in bus test state */ +#define HAL_MMC_CARD_SLEEP 0x0000000AU /*!< Card is in sleep state (can't be checked by CMD13) */ +#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error (can't be checked by CMD13) */ +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition + * @{ + */ +#define MMC_InitTypeDef SDMMC_InitTypeDef +#define MMC_TypeDef SDMMC_TypeDef + +/** + * @brief MMC Card Information Structure definition + */ +typedef struct +{ + uint32_t CardType; /*!< Specifies the card Type */ + + uint32_t Class; /*!< Specifies the class of the card class */ + + uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ + + uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ + + uint32_t BlockSize; /*!< Specifies one block size in bytes */ + + uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ + + uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ + +} HAL_MMC_CardInfoTypeDef; + +/** + * @brief MMC handle Structure definition + */ +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +typedef struct __MMC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ +{ + MMC_TypeDef *Instance; /*!< MMC registers base address */ + + MMC_InitTypeDef Init; /*!< MMC required parameters */ + + HAL_LockTypeDef Lock; /*!< MMC locking object */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ + + uint32_t TxXferSize; /*!< MMC Tx Transfer size */ + + uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */ + + uint32_t RxXferSize; /*!< MMC Rx Transfer size */ + + __IO uint32_t Context; /*!< MMC transfer context */ + + __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */ + + __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ + + __IO uint16_t RPMBErrorCode; /*!< MMC RPMB Area Error codes */ + + HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ + + uint32_t CSD[4U]; /*!< MMC card specific data table */ + + uint32_t CID[4U]; /*!< MMC card identification number table */ + + uint32_t Ext_CSD[128]; + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* RxCpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* ErrorCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* AbortCpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* Read_DMALnkLstBufCpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* Write_DMALnkLstBufCpltCallback)(struct __MMC_HandleTypeDef *hmmc); + + void (* MspInitCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* MspDeInitCallback)(struct __MMC_HandleTypeDef *hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ +} MMC_HandleTypeDef; + + +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register + * @{ + */ +typedef struct +{ + __IO uint8_t CSDStruct; /*!< CSD structure */ + __IO uint8_t SysSpecVersion; /*!< System specification version */ + __IO uint8_t Reserved1; /*!< Reserved */ + __IO uint8_t TAAC; /*!< Data read access time 1 */ + __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ + __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ + __IO uint16_t CardComdClasses; /*!< Card command classes */ + __IO uint8_t RdBlockLen; /*!< Max. read data block length */ + __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ + __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ + __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ + __IO uint8_t DSRImpl; /*!< DSR implemented */ + __IO uint8_t Reserved2; /*!< Reserved */ + __IO uint32_t DeviceSize; /*!< Device Size */ + __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ + __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ + __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ + __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ + __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ + __IO uint8_t EraseGrSize; /*!< Erase group size */ + __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ + __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ + __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ + __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ + __IO uint8_t WrSpeedFact; /*!< Write speed factor */ + __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ + __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ + __IO uint8_t Reserved3; /*!< Reserved */ + __IO uint8_t ContentProtectAppli; /*!< Content protection application */ + __IO uint8_t FileFormatGroup; /*!< File format group */ + __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ + __IO uint8_t PermWrProtect; /*!< Permanent write protection */ + __IO uint8_t TempWrProtect; /*!< Temporary write protection */ + __IO uint8_t FileFormat; /*!< File format */ + __IO uint8_t ECC; /*!< ECC code */ + __IO uint8_t CSD_CRC; /*!< CSD CRC */ + __IO uint8_t Reserved4; /*!< Always 1 */ + +} HAL_MMC_CardCSDTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register + * @{ + */ +typedef struct +{ + __IO uint8_t ManufacturerID; /*!< Manufacturer ID */ + __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ + __IO uint32_t ProdName1; /*!< Product Name part1 */ + __IO uint8_t ProdName2; /*!< Product Name part2 */ + __IO uint8_t ProdRev; /*!< Product Revision */ + __IO uint32_t ProdSN; /*!< Product Serial Number */ + __IO uint8_t Reserved1; /*!< Reserved1 */ + __IO uint16_t ManufactDate; /*!< Manufacturing Date */ + __IO uint8_t CID_CRC; /*!< CID CRC */ + __IO uint8_t Reserved2; /*!< Always 1 */ + +} HAL_MMC_CardCIDTypeDef; +/** + * @} + */ + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */ + HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */ + HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */ + HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */ + HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID = 0x04U, /*!< MMC DMA Rx Linked List Node buffer Callback ID */ + HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID = 0x05U, /*!< MMC DMA Tx Linked List Node buffer Callback ID */ + + HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */ + HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */ +} HAL_MMC_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition + * @{ + */ +typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc); +/** + * @} + */ +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup MMC_Exported_Constants Exported Constants + * @{ + */ + +#define MMC_BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */ + +/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition + * @{ + */ +#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ +/*!< number of transferred bytes does not match the block length */ +#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ +/*!< command or if there was an attempt to access a locked card */ +#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ +/*!< of erase sequence command was received */ +#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +/*!< response results after operating with RPMB partition */ +#define HAL_MMC_ERROR_RPMB_OPERATION_OK 0x0000U /*!< Operation OK */ +#define HAL_MMC_ERROR_RPMB_GENERAL_FAILURE 0x0001U /*!< General failure */ +#define HAL_MMC_ERROR_RPMB_AUTHENTICATION_FAILURE 0x0002U /*!< Authentication failure */ +#define HAL_MMC_ERROR_RPMB_COUNTER_FAILURE 0x0003U /*!< Counter failure */ +#define HAL_MMC_ERROR_RPMB_ADDRESS_FAILURE 0x0004U /*!< Address failure */ +#define HAL_MMC_ERROR_RPMB_WRITE_FAILURE 0x0005U /*!< Write failure */ +#define HAL_MMC_ERROR_RPMB_READ_FAILURE 0x0006U /*!< Read failure */ +#define HAL_MMC_ERROR_RPMB_KEY_NOT_YET_PROG 0x0007U /*!< Authentication Key not yet programmed */ +#define HAL_MMC_ERROR_RPMB_COUNTER_EXPIRED 0x0080U /*!< Write Counter has expired i.e. reached its max value */ + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration + * @{ + */ +#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */ +#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */ +#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */ +#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */ +#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */ +#define MMC_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */ +#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */ + +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode + * @{ + */ +/** + * @brief + */ +#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */ +#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */ +#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */ +#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */ +#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */ +#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */ +#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards + * @{ + */ +#define MMC_LOW_CAPACITY_CARD ((uint32_t)0x00000000U) /*!< MMC Card Capacity <=2Gbytes */ +#define MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U) /*!< MMC Card Capacity >2Gbytes and <2Tbytes */ + +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group5 MMC Erase Type + * @{ + */ +#define HAL_MMC_ERASE 0x00000000U /*!< Erase the erase groups identified by CMD35 & 36 */ +#define HAL_MMC_TRIM 0x00000001U /*!< Erase the write blocks identified by CMD35 & 36 */ +#define HAL_MMC_DISCARD 0x00000003U /*!< Discard the write blocks identified by CMD35 & 36 */ +#define HAL_MMC_SECURE_ERASE 0x80000000U /*!< Perform a secure purge according SRT on the erase groups identified by CMD35 & 36 */ +#define HAL_MMC_SECURE_TRIM_STEP1 0x80000001U /*!< Mark the write blocks identified by CMD35 & 36 for secure erase */ +#define HAL_MMC_SECURE_TRIM_STEP2 0x80008000U /*!< Perform a secure purge according SRT on the write blocks previously identified */ + +#define IS_MMC_ERASE_TYPE(TYPE) (((TYPE) == HAL_MMC_ERASE) || \ + ((TYPE) == HAL_MMC_TRIM) || \ + ((TYPE) == HAL_MMC_DISCARD) || \ + ((TYPE) == HAL_MMC_SECURE_ERASE) || \ + ((TYPE) == HAL_MMC_SECURE_TRIM_STEP1) || \ + ((TYPE) == HAL_MMC_SECURE_TRIM_STEP2)) +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group6 MMC Secure Removal Type + * @{ + */ +#define HAL_MMC_SRT_ERASE 0x00000001U /*!< Information removed by an erase */ +#define HAL_MMC_SRT_WRITE_CHAR_ERASE 0x00000002U /*!< Information removed by an overwriting with a character followed by an erase */ +#define HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM 0x00000004U /*!< Information removed by an overwriting with a character, its complement then a random character */ +#define HAL_MMC_SRT_VENDOR_DEFINED 0x00000008U /*!< Information removed using a vendor defined */ + + +#define IS_MMC_SRT_TYPE(TYPE) (((TYPE) == HAL_MMC_SRT_ERASE) || \ + ((TYPE) == HAL_MMC_SRT_WRITE_CHAR_ERASE) || \ + ((TYPE) == HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM) || \ + ((TYPE) == HAL_MMC_SRT_VENDOR_DEFINED)) +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group7 MMC Partitions types + * @{ + */ +typedef uint32_t HAL_MMC_PartitionTypeDef; + +#define HAL_MMC_USER_AREA_PARTITION 0x00000000U /*!< User area partition */ +#define HAL_MMC_BOOT_PARTITION1 0x00000100U /*!< Boot partition 1 */ +#define HAL_MMC_BOOT_PARTITION2 0x00000200U /*!< Boot partition 2 */ +#define HAL_MMC_RPMB_PARTITION 0x00000300U /*!< RPMB partition */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup MMC_Exported_macros MMC Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +/** @brief Reset MMC handle state. + * @param __HANDLE__ MMC Handle. + * @retval None + */ +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_MMC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET) +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + +/** + * @brief Enable the MMC device interrupt. + * @param __HANDLE__ MMC Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval None + */ +#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Disable the MMC device interrupt. + * @param __HANDLE__ MMC Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval None + */ +#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Check whether the specified MMC flag is set or not. + * @param __HANDLE__ MMC Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDMMC_FLAG_DHOLD: Data transfer Hold + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 + * @arg SDMMC_FLAG_DPSMACT: Data path state machine active + * @arg SDMMC_FLAG_CPSMACT: Command path state machine active + * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full + * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) + * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected + * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received + * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout + * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion + * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure + * @arg SDMMC_FLAG_IDMATE: IDMA transfer error + * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete + * @retval The new state of MMC FLAG (SET or RESET). + */ +#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Clear the MMC's pending flags. + * @param __HANDLE__ MMC Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDMMC_FLAG_DHOLD: Data transfer Hold + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 + * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected + * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received + * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout + * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion + * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure + * @arg SDMMC_FLAG_IDMATE: IDMA transfer error + * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete + * @retval None + */ +#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Check whether the specified MMC interrupt has occurred or not. + * @param __HANDLE__ MMC Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval The new state of MMC IT (SET or RESET). + */ +#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Clear the MMC's interrupt pending bits. + * @param __HANDLE__ MMC Handle. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval None + */ +#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @} + */ + +/* Include MMC HAL Extension module */ +#include "stm32h7rsxx_hal_mmc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MMC_Exported_Functions MMC Exported Functions + * @{ + */ + +/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc); +void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc); +void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); + +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, + uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +/* Non-Blocking mode: IT */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); + +void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc); + +/* Callback in non blocking modes (DMA) */ +void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc); + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +/* MMC callback registering/unregistering */ +HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, + pMMC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); +HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode); +HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions + * @{ + */ +HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions + * @{ + */ +HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetRPMBError(const MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group7 Peripheral Erase management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, + uint32_t BlockEndAdd); +HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode); +HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group8 Peripheral Sleep management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group9 Replay Protected Memory Block management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, + uint32_t Timeout); +uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout); +uint32_t HAL_MMC_RPMB_GetWriteCounter_IT(MMC_HandleTypeDef *hmmc, uint8_t *pNonce); +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC); +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC, + uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC); + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup MMC_Private_Types MMC Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup MMC_Private_Defines MMC Private Defines + * @{ + */ +#define MMC_EXT_CSD_DATA_SEC_SIZE_INDEX 61 +#define MMC_EXT_CSD_DATA_SEC_SIZE_POS 8 +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Variables MMC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Constants MMC Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup MMC_Private_Macros MMC Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Functions MMC Private Functions + * @{ + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ +#endif /* SDMMC1 || SDMMC2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7RSxx_HAL_MMC_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mmc_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mmc_ex.h new file mode 100644 index 00000000000..4615fb8c5ca --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_mmc_ex.h @@ -0,0 +1,122 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_mmc_ex.h + * @author MCD Application Team + * @brief Header file of SD HAL extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_MMC_EX_H +#define STM32H7RSxx_HAL_MMC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#if defined (SDMMC1) || defined (SDMMC2) +/** @addtogroup MMCEx + * @brief SD HAL extended module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup MMCEx_Exported_Types MMCEx Exported Types + * @{ + */ + +/** @defgroup MMCEx_Exported_Types_Group1 Linked List Wrapper + * @{ + */ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* -----------------Linked List Wrapper --------------------------------------*/ + +#define MMC_DMALinkNodeTypeDef SDMMC_DMALinkNodeTypeDef +#define MMC_DMALinkNodeConfTypeDef SDMMC_DMALinkNodeConfTypeDef +#define MMC_DMALinkedListTypeDef SDMMC_DMALinkedListTypeDef +/* ----------------- Linked Aliases ------------------------------------------*/ +#define HAL_MMCx_DMALinkedList_WriteCpltCallback HAL_MMC_TxCpltCallback +#define HAL_MMCx_DMALinkedList_ReadCpltCallback HAL_MMC_RxCpltCallback +/** + * @} + */ + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions + * @{ + */ + +/** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions + * @{ + */ +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, SDMMC_DMALinkedListTypeDef *pLinkedList, + uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, SDMMC_DMALinkedListTypeDef *pLinkedList, + uint32_t BlockAdd, uint32_t NumberOfBlocks); + +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_BuildNode(MMC_DMALinkNodeTypeDef *pNode, + MMC_DMALinkNodeConfTypeDef *pNodeConf); +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_InsertNode(MMC_DMALinkedListTypeDef *pLinkedList, + MMC_DMALinkNodeTypeDef *pPrevNode, + MMC_DMALinkNodeTypeDef *pNewNode); +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_RemoveNode(MMC_DMALinkedListTypeDef *pLinkedList, + MMC_DMALinkNodeTypeDef *pNode); +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_LockNode(MMC_DMALinkNodeTypeDef *pNode); +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_UnlockNode(MMC_DMALinkNodeTypeDef *pNode); +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_EnableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList); +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_DisableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList); + +void HAL_MMCEx_Read_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMCEx_Write_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions prototypes ----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ +#endif /* SDMMC1 || SDMMC2 */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7RSxx_HAL_MMCEx_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_nand.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_nand.h new file mode 100644 index 00000000000..9f6083bedcb --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_nand.h @@ -0,0 +1,376 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_nand.h + * @author MCD Application Team + * @brief Header file of NAND HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_NAND_H +#define STM32H7RSxx_HAL_NAND_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_fmc.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup NAND + * @{ + */ + +/* Exported typedef ----------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup NAND_Exported_Types NAND Exported Types + * @{ + */ + +/** + * @brief HAL NAND State structures definition + */ +typedef enum +{ + HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ + HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ + HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ + HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ +} HAL_NAND_StateTypeDef; + +/** + * @brief NAND Memory electronic signature Structure definition + */ +typedef struct +{ + /*State = HAL_NAND_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup NAND_Exported_Functions NAND Exported Functions + * @{ + */ + +/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, + FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); +HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); + +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); + +HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); + +void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); +void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); +void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); +void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); + +/** + * @} + */ + +/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions + * @{ + */ + +/* IO operation functions ****************************************************/ +HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); + +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress); + +uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); + +#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) +/* NAND callback registering/unregistering */ +HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, + pNAND_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* NAND Control functions ****************************************************/ +HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); +HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); +HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); + +/** + * @} + */ + +/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +/* NAND State functions *******************************************************/ +HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand); +uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup NAND_Private_Constants NAND Private Constants + * @{ + */ +#define NAND_DEVICE 0x80000000UL +#define NAND_WRITE_TIMEOUT 0x01000000UL + +#define CMD_AREA (1UL<<16U) /* A16 = CLE high */ +#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ + +#define NAND_CMD_AREA_A ((uint8_t)0x00) +#define NAND_CMD_AREA_B ((uint8_t)0x01) +#define NAND_CMD_AREA_C ((uint8_t)0x50) +#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) + +#define NAND_CMD_WRITE0 ((uint8_t)0x80) +#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) +#define NAND_CMD_ERASE0 ((uint8_t)0x60) +#define NAND_CMD_ERASE1 ((uint8_t)0xD0) +#define NAND_CMD_READID ((uint8_t)0x90) +#define NAND_CMD_STATUS ((uint8_t)0x70) +#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) +#define NAND_CMD_RESET ((uint8_t)0xFF) + +/* NAND memory status */ +#define NAND_VALID_ADDRESS 0x00000100UL +#define NAND_INVALID_ADDRESS 0x00000200UL +#define NAND_TIMEOUT_ERROR 0x00000400UL +#define NAND_BUSY 0x00000000UL +#define NAND_ERROR 0x00000001UL +#define NAND_READY 0x00000040UL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup NAND_Private_Macros NAND Private Macros + * @{ + */ + +/** + * @brief NAND memory address computation. + * @param __ADDRESS__ NAND memory address. + * @param __HANDLE__ NAND handle. + * @retval NAND Raw address value + */ +#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ + (((__ADDRESS__)->Block + \ + (((__ADDRESS__)->Plane) * \ + ((__HANDLE__)->Config.PlaneSize))) * \ + ((__HANDLE__)->Config.BlockSize))) + +/** + * @brief NAND memory Column address computation. + * @param __HANDLE__ NAND handle. + * @retval NAND Raw address value + */ +#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) + +/** + * @brief NAND memory address cycling. + * @param __ADDRESS__ NAND memory address. + * @retval NAND address cycling value. + */ +#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ +#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ +#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ +#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ + +/** + * @brief NAND memory Columns cycling. + * @param __ADDRESS__ NAND memory address. + * @retval NAND Column address cycling value. + */ +#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */ +#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_NAND_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_nor.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_nor.h new file mode 100644 index 00000000000..ab2d0796918 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_nor.h @@ -0,0 +1,324 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_nor.h + * @author MCD Application Team + * @brief Header file of NOR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_NOR_H +#define STM32H7RSxx_HAL_NOR_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_fmc.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup NOR + * @{ + */ + +/* Exported typedef ----------------------------------------------------------*/ +/** @defgroup NOR_Exported_Types NOR Exported Types + * @{ + */ + +/** + * @brief HAL SRAM State structures definition + */ +typedef enum +{ + HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */ + HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */ + HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */ + HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */ + HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */ +} HAL_NOR_StateTypeDef; + +/** + * @brief FMC NOR Status typedef + */ +typedef enum +{ + HAL_NOR_STATUS_SUCCESS = 0U, + HAL_NOR_STATUS_ONGOING, + HAL_NOR_STATUS_ERROR, + HAL_NOR_STATUS_TIMEOUT +} HAL_NOR_StatusTypeDef; + +/** + * @brief FMC NOR ID typedef + */ +typedef struct +{ + uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */ + + uint16_t Device_Code1; + + uint16_t Device_Code2; + + uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. + These codes can be accessed by performing read operations with specific + control signals and addresses set.They can also be accessed by issuing + an Auto Select command */ +} NOR_IDTypeDef; + +/** + * @brief FMC NOR CFI typedef + */ +typedef struct +{ + /*!< Defines the information stored in the memory's Common flash interface + which contains a description of various electrical and timing parameters, + density information and functions supported by the memory */ + + uint16_t CFI_1; + + uint16_t CFI_2; + + uint16_t CFI_3; + + uint16_t CFI_4; +} NOR_CFITypeDef; + +/** + * @brief NOR handle Structure definition + */ +#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) +typedef struct __NOR_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ + +{ + FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ + + FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ + + FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */ + + HAL_LockTypeDef Lock; /*!< NOR locking object */ + + __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ + + uint32_t CommandSet; /*!< NOR algorithm command set and control */ + +#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) + void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */ + void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */ +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ +} NOR_HandleTypeDef; + +#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) +/** + * @brief HAL NOR Callback ID enumeration definition + */ +typedef enum +{ + HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */ + HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */ +} HAL_NOR_CallbackIDTypeDef; + +/** + * @brief HAL NOR Callback pointer definition + */ +typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup NOR_Exported_Macros NOR Exported Macros + * @{ + */ +/** @brief Reset NOR handle state + * @param __HANDLE__ specifies the NOR handle. + * @retval None + */ +#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) +#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_NOR_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup NOR_Exported_Functions NOR Exported Functions + * @{ + */ + +/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); +void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); +void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); +void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); +/** + * @} + */ + +/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions + * @{ + */ + +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); +HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); +HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); +HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); + +HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize); +HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize); + +HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); +HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); +HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); + +#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) +/* NOR callback registering/unregistering */ +HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, + pNOR_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId); +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions + * @{ + */ + +/* NOR Control functions *****************************************************/ +HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); +HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); +/** + * @} + */ + +/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions + * @{ + */ + +/* NOR State functions ********************************************************/ +HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor); +HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup NOR_Private_Constants NOR Private Constants + * @{ + */ +/* NOR device IDs addresses */ +#define MC_ADDRESS ((uint16_t)0x0000) +#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) +#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) +#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) + +/* NOR CFI IDs addresses */ +#define CFI1_ADDRESS ((uint16_t)0x0061) +#define CFI2_ADDRESS ((uint16_t)0x0062) +#define CFI3_ADDRESS ((uint16_t)0x0063) +#define CFI4_ADDRESS ((uint16_t)0x0064) + +/* NOR operation wait timeout */ +#define NOR_TMEOUT ((uint16_t)0xFFFF) + +/* NOR memory data width */ +#define NOR_MEMORY_8B ((uint8_t)0x00) +#define NOR_MEMORY_16B ((uint8_t)0x01) + +/* NOR memory device read/write start address */ +#define NOR_MEMORY_ADRESS1 (0x60000000U) +#define NOR_MEMORY_ADRESS2 (0x64000000U) +#define NOR_MEMORY_ADRESS3 (0x68000000U) +#define NOR_MEMORY_ADRESS4 (0x6C000000U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup NOR_Private_Macros NOR Private Macros + * @{ + */ +/** + * @brief NOR memory address shifting. + * @param __NOR_ADDRESS NOR base address + * @param __NOR_MEMORY_WIDTH_ NOR memory width + * @param __ADDRESS__ NOR memory address + * @retval NOR shifted address value + */ +#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ + ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ + ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ + ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) + +/** + * @brief NOR memory write data to specified address. + * @param __ADDRESS__ NOR memory address + * @param __DATA__ Data to write + * @retval None + */ +#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \ + (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \ + __DSB(); \ + } while(0) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_NOR_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pcd.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pcd.h new file mode 100644 index 00000000000..78a357353a8 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pcd.h @@ -0,0 +1,427 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_pcd.h + * @author MCD Application Team + * @brief Header file of PCD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_PCD_H +#define STM32H7RSxx_HAL_PCD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_usb.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup PCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PCD_Exported_Types PCD Exported Types + * @{ + */ + +/** + * @brief PCD State structure definition + */ +typedef enum +{ + HAL_PCD_STATE_RESET = 0x00, + HAL_PCD_STATE_READY = 0x01, + HAL_PCD_STATE_ERROR = 0x02, + HAL_PCD_STATE_BUSY = 0x03, + HAL_PCD_STATE_TIMEOUT = 0x04 +} PCD_StateTypeDef; + +/* Device LPM suspend state */ +typedef enum +{ + LPM_L0 = 0x00, /* on */ + LPM_L1 = 0x01, /* LPM L1 sleep */ + LPM_L2 = 0x02, /* suspend */ + LPM_L3 = 0x03, /* off */ +} PCD_LPM_StateTypeDef; + +typedef enum +{ + PCD_LPM_L0_ACTIVE = 0x00, /* on */ + PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ +} PCD_LPM_MsgTypeDef; + +typedef enum +{ + PCD_BCD_ERROR = 0xFF, + PCD_BCD_CONTACT_DETECTION = 0xFE, + PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, + PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, + PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, + PCD_BCD_DISCOVERY_COMPLETED = 0x00, + +} PCD_BCD_MsgTypeDef; + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +typedef USB_OTG_GlobalTypeDef PCD_TypeDef; +typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; +typedef USB_OTG_EPTypeDef PCD_EPTypeDef; +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @brief PCD Handle Structure definition + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +typedef struct __PCD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + uint32_t BESL; + uint32_t FrameNumber; /*!< Store Current Frame number */ + + + uint32_t lpm_active; /*!< Enable or disable the Link Power Management . + This parameter can be set to ENABLE or DISABLE */ + + uint32_t battery_charging_active; /*!< Enable or disable Battery charging. + This parameter can be set to ENABLE or DISABLE */ + void *pData; /*!< Pointer to upper stack Handler */ + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */ + void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */ + void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */ + void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */ + void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */ + void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */ + void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */ + + void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */ + void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */ + void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */ + void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */ + void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */ + void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */ + + void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */ + void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +} PCD_HandleTypeDef; + +/** + * @} + */ + +/* Include PCD HAL Extended module */ +#include "stm32h7rsxx_hal_pcd_ex.h" + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +/** @defgroup PCD_Speed PCD Speed + * @{ + */ +#define PCD_SPEED_HIGH USBD_HS_SPEED +#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED +#define PCD_SPEED_FULL USBD_FS_SPEED +/** + * @} + */ + +/** @defgroup PCD_PHY_Module PCD PHY Module + * @{ + */ +#define PCD_PHY_ULPI 1U +#define PCD_PHY_EMBEDDED 2U +#define PCD_PHY_UTMI 3U +/** + * @} + */ + +/** @defgroup PCD_Error_Code_definition PCD Error Code definition + * @brief PCD Error Code definition + * @{ + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PCD_Exported_Macros PCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ + ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) +#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) + +#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) + +#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK + +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \ + ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition + * @brief HAL USB OTG PCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */ + HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */ + HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */ + HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ + HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ + HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ + HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ + + HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ + HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ + +} HAL_PCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition + * @brief HAL USB OTG PCD Callback pointer definition + * @{ + */ + +typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */ +typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */ +typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */ +typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */ +typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */ +typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */ +typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */ + +/** + * @} + */ + +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/* Non-Blocking mode: Interrupt */ +/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants PCD Private Constants + * @{ + */ +/** + * @} + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#ifndef USB_OTG_DOEPINT_OTEPSPR +#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_OTEPSPR */ + +#ifndef USB_OTG_DOEPMSK_OTEPSPRM +#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */ + +#ifndef USB_OTG_DOEPINT_NAK +#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ +#endif /* defined USB_OTG_DOEPINT_NAK */ + +#ifndef USB_OTG_DOEPMSK_NAKM +#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NAKM */ + +#ifndef USB_OTG_DOEPINT_STPKTRX +#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_STPKTRX */ + +#ifndef USB_OTG_DOEPMSK_NYETM +#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NYETM */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Macros + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_PCD_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pcd_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pcd_ex.h new file mode 100644 index 00000000000..3d337913819 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pcd_ex.h @@ -0,0 +1,88 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_pcd_ex.h + * @author MCD Application Team + * @brief Header file of PCD HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_PCD_EX_H +#define STM32H7RSxx_HAL_PCD_EX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup PCDEx + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ +/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @{ + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); + + +HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd); +void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd); + +void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); +void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32H7RSxx_HAL_PCD_EX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pka.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pka.h new file mode 100644 index 00000000000..9b1bea20a2e --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pka.h @@ -0,0 +1,670 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_pka.h + * @author MCD Application Team + * @brief Header file of PKA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_PKA_H +#define STM32H7RSxx_HAL_PKA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) + +/** @addtogroup PKA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PKA_Exported_Types PKA Exported Types + * @{ + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structures definition + * @{ + */ +typedef enum +{ + HAL_PKA_STATE_RESET = 0x00U, /*!< PKA not yet initialized or disabled */ + HAL_PKA_STATE_READY = 0x01U, /*!< PKA initialized and ready for use */ + HAL_PKA_STATE_BUSY = 0x02U, /*!< PKA internal processing is ongoing */ + HAL_PKA_STATE_ERROR = 0x03U, /*!< PKA error state */ +} +HAL_PKA_StateTypeDef; + +/** + * @} + */ + +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) +/** @defgroup HAL_callback_id HAL callback ID enumeration + * @{ + */ +typedef enum +{ + HAL_PKA_OPERATION_COMPLETE_CB_ID = 0x00U, /*!< PKA End of operation callback ID */ + HAL_PKA_ERROR_CB_ID = 0x01U, /*!< PKA Error callback ID */ + HAL_PKA_MSPINIT_CB_ID = 0x02U, /*!< PKA Msp Init callback ID */ + HAL_PKA_MSPDEINIT_CB_ID = 0x03U /*!< PKA Msp DeInit callback ID */ +} HAL_PKA_CallbackIDTypeDef; + +/** + * @} + */ + +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + +/** @defgroup PKA_Error_Code_definition PKA Error Code definition + * @brief PKA Error Code definition + * @{ + */ +#define HAL_PKA_ERROR_NONE (0x00000000U) +#define HAL_PKA_ERROR_ADDRERR (0x00000001U) +#define HAL_PKA_ERROR_RAMERR (0x00000002U) +#define HAL_PKA_ERROR_TIMEOUT (0x00000004U) +#define HAL_PKA_ERROR_OPERATION (0x00000008U) +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) +#define HAL_PKA_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup PKA_handle_Structure_definition PKA handle Structure definition + * @brief PKA handle Structure definition + * @{ + */ +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) +typedef struct __PKA_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ +{ + PKA_TypeDef *Instance; /*!< Register base address */ + __IO HAL_PKA_StateTypeDef State; /*!< PKA state */ + __IO uint32_t ErrorCode; /*!< PKA Error code */ +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) + void (* OperationCpltCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA End of operation callback */ + void (* ErrorCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Error callback */ + void (* MspInitCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Msp Init callback */ + void (* MspDeInitCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Msp DeInit callback */ +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ +} PKA_HandleTypeDef; +/** + * @} + */ + +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) +/** @defgroup PKA_Callback_definition PKA Callback pointer definition + * @brief PKA Callback pointer definition + * @{ + */ +typedef void (*pPKA_CallbackTypeDef)(PKA_HandleTypeDef *hpka); /*!< Pointer to a PKA callback function */ +/** + * @} + */ +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ +/** @defgroup PKA_Operation PKA operation structure definition + * @brief Input and output data definition + * @{ + */ + +typedef struct +{ + uint32_t scalarMulSize; /*!< Number of element in scalarMul array */ + uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */ + uint32_t coefSign; /*!< Curve coefficient a sign */ + const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */ + const uint8_t *coefB; /*!< pointer to curve coefficient b */ + const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */ + const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */ + const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */ + const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */ + const uint8_t *primeOrder; /*!< pointer to order of the curve */ +} PKA_ECCMulInTypeDef; + +typedef struct +{ + uint32_t primeOrderSize; /*!< Number of element in primeOrder array */ + uint32_t scalarMulSize; /*!< Number of element in scalarMul array */ + uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */ + uint32_t coefSign; /*!< Curve coefficient a sign */ + const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */ + const uint8_t *coefB; /*!< pointer to curve coefficient b */ + const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */ + const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */ + const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */ + const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */ + const uint8_t *primeOrder; /*!< pointer to order of the curve */ +} PKA_ECCMulExInTypeDef; + +typedef struct +{ + uint32_t modulusSize; /*!< Number of element in coefA, coefB, modulus, pointX and pointY arrays */ + uint32_t coefSign; /*!< Curve coefficient a sign */ + const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */ + const uint8_t *coefB; /*!< Pointer to curve coefficient b (Array of modulusSize elements) */ + const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */ + const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */ + const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */ + const uint32_t *pMontgomeryParam; /*!< pointer to montgomery param R2 (modulus N) */ +} PKA_PointCheckInTypeDef; + +typedef struct +{ + uint32_t size; /*!< Number of element in popA array */ + const uint8_t *pOpDp; /*!< Pointer to operand dP (Array of size/2 elements) */ + const uint8_t *pOpDq; /*!< Pointer to operand dQ (Array of size/2 elements) */ + const uint8_t *pOpQinv; /*!< Pointer to operand qinv (Array of size/2 elements) */ + const uint8_t *pPrimeP; /*!< Pointer to prime p (Array of size/2 elements) */ + const uint8_t *pPrimeQ; /*!< Pointer to prime Q (Array of size/2 elements) */ + const uint8_t *popA; /*!< Pointer to operand A (Array of size elements) */ +} PKA_RSACRTExpInTypeDef; + +typedef struct +{ + uint32_t primeOrderSize; /*!< Number of element in primeOrder array */ + uint32_t modulusSize; /*!< Number of element in modulus array */ + uint32_t coefSign; /*!< Curve coefficient a sign */ + const uint8_t *coef; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */ + const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */ + const uint8_t *basePointX; /*!< Pointer to curve base point xG (Array of modulusSize elements) */ + const uint8_t *basePointY; /*!< Pointer to curve base point yG (Array of modulusSize elements) */ + const uint8_t *pPubKeyCurvePtX; /*!< Pointer to public-key curve point xQ (Array of modulusSize elements) */ + const uint8_t *pPubKeyCurvePtY; /*!< Pointer to public-key curve point yQ (Array of modulusSize elements) */ + const uint8_t *RSign; /*!< Pointer to signature part r (Array of primeOrderSize elements) */ + const uint8_t *SSign; /*!< Pointer to signature part s (Array of primeOrderSize elements) */ + const uint8_t *hash; /*!< Pointer to hash of the message e (Array of primeOrderSize elements) */ + const uint8_t *primeOrder; /*!< Pointer to order of the curve n (Array of primeOrderSize elements) */ +} PKA_ECDSAVerifInTypeDef; + +typedef struct +{ + uint32_t primeOrderSize; /*!< Number of element in primeOrder array */ + uint32_t modulusSize; /*!< Number of element in modulus array */ + uint32_t coefSign; /*!< Curve coefficient a sign */ + const uint8_t *coef; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */ + const uint8_t *coefB; /*!< Pointer to B coefficient (Array of modulusSize elements) */ + const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */ + const uint8_t *integer; /*!< Pointer to random integer k (Array of primeOrderSize elements) */ + const uint8_t *basePointX; /*!< Pointer to curve base point xG (Array of modulusSize elements) */ + const uint8_t *basePointY; /*!< Pointer to curve base point yG (Array of modulusSize elements) */ + const uint8_t *hash; /*!< Pointer to hash of the message (Array of primeOrderSize elements) */ + const uint8_t *privateKey; /*!< Pointer to private key d (Array of primeOrderSize elements) */ + const uint8_t *primeOrder; /*!< Pointer to order of the curve n (Array of primeOrderSize elements) */ +} PKA_ECDSASignInTypeDef; + +typedef struct +{ + uint8_t *RSign; /*!< Pointer to signature part r (Array of modulusSize elements) */ + uint8_t *SSign; /*!< Pointer to signature part s (Array of modulusSize elements) */ +} PKA_ECDSASignOutTypeDef; + +typedef struct +{ + uint8_t *ptX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */ + uint8_t *ptY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */ +} PKA_ECDSASignOutExtParamTypeDef, PKA_ECCMulOutTypeDef, PKA_ECCProjective2AffineOutTypeDef, +PKA_ECCDoubleBaseLadderOutTypeDef; + +typedef struct +{ + uint8_t *ptX; /*!< pointer to point P coordinate xP */ + uint8_t *ptY; /*!< pointer to point P coordinate yP */ + uint8_t *ptZ; /*!< pointer to point P coordinate zP */ +} PKA_ECCCompleteAdditionOutTypeDef; + +typedef struct +{ + uint32_t expSize; /*!< Number of element in pExp array */ + uint32_t OpSize; /*!< Number of element in pOp1 and pMod arrays */ + const uint8_t *pExp; /*!< Pointer to Exponent (Array of expSize elements) */ + const uint8_t *pOp1; /*!< Pointer to Operand (Array of OpSize elements) */ + const uint8_t *pMod; /*!< Pointer to modulus (Array of OpSize elements) */ +} PKA_ModExpInTypeDef; + +typedef struct +{ + uint32_t expSize; /*!< Size of the operand in bytes */ + uint32_t OpSize; /*!< Size of the operand in bytes */ + const uint8_t *pOp1; /*!< Pointer to Operand 1 */ + const uint8_t *pExp; /*!< Pointer to Exponent */ + const uint8_t *pMod; /*!< Pointer to Operand 1 */ + const uint8_t *pPhi; /*!< Pointer to Phi value */ +} PKA_ModExpProtectModeInTypeDef; + +typedef struct +{ + uint32_t expSize; /*!< Number of element in pExp and pMontgomeryParam arrays */ + uint32_t OpSize; /*!< Number of element in pOp1 and pMod arrays */ + const uint8_t *pExp; /*!< Pointer to Exponent (Array of expSize elements) */ + const uint8_t *pOp1; /*!< Pointer to Operand (Array of OpSize elements) */ + const uint8_t *pMod; /*!< Pointer to modulus (Array of OpSize elements) */ + const uint32_t *pMontgomeryParam; /*!< Pointer to Montgomery parameter (Array of expSize/4 elements) */ +} PKA_ModExpFastModeInTypeDef; + +typedef struct +{ + uint32_t size; /*!< Number of element in pOp1 array */ + const uint8_t *pOp1; /*!< Pointer to Operand (Array of size elements) */ +} PKA_MontgomeryParamInTypeDef; + +typedef struct +{ + uint32_t size; /*!< Number of element in pOp1 and pOp2 arrays */ + const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */ + const uint32_t *pOp2; /*!< Pointer to Operand 2 (Array of size elements) */ +} PKA_AddInTypeDef, PKA_SubInTypeDef, PKA_MulInTypeDef, PKA_CmpInTypeDef; + +typedef struct +{ + uint32_t size; /*!< Number of element in pOp1 array */ + const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */ + const uint8_t *pMod; /*!< Pointer to modulus value n (Array of size*4 elements) */ +} PKA_ModInvInTypeDef; + +typedef struct +{ + uint32_t OpSize; /*!< Number of element in pOp1 array */ + uint32_t modSize; /*!< Number of element in pMod array */ + const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of OpSize elements) */ + const uint8_t *pMod; /*!< Pointer to modulus value n (Array of modSize elements) */ +} PKA_ModRedInTypeDef; + +typedef struct +{ + uint32_t size; /*!< Number of element in pOp1 and pOp2 arrays */ + const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */ + const uint32_t *pOp2; /*!< Pointer to Operand 2 (Array of size elements) */ + const uint8_t *pOp3; /*!< Pointer to Operand 3 (Array of size*4 elements) */ +} PKA_ModAddInTypeDef, PKA_ModSubInTypeDef, PKA_MontgomeryMulInTypeDef; + +typedef struct +{ + uint32_t primeOrderSize; /*!< curve prime order n length */ + uint32_t modulusSize; /*!< curve modulus p length */ + uint32_t coefSign; /*!< curve coefficient a sign */ + const uint8_t *coefA; /*!< pointer to curve coefficient |a| */ + const uint8_t *modulus; /*!< pointer to curve modulus value p */ + const uint8_t *integerK; /*!< pointer to cryptographically secure random integer k */ + const uint8_t *integerM; /*!< pointer to cryptographically secure random integer m */ + const uint8_t *basePointX1; /*!< pointer to curve base first point coordinate x */ + const uint8_t *basePointY1; /*!< pointer to curve base first point coordinate y */ + const uint8_t *basePointZ1; /*!< pointer to curve base first point coordinate z */ + const uint8_t *basePointX2; /*!< pointer to curve base second point coordinate x */ + const uint8_t *basePointY2; /*!< pointer to curve base second point coordinate y */ + const uint8_t *basePointZ2; /*!< pointer to curve base second point coordinate z */ +} PKA_ECCDoubleBaseLadderInTypeDef; + +typedef struct +{ + uint32_t modulusSize; /*!< curve modulus p length */ + const uint8_t *modulus; /*!< pointer to curve modulus value p */ + const uint8_t *basePointX; /*!< pointer to curve base point coordinate x */ + const uint8_t *basePointY; /*!< pointer to curve base point coordinate y */ + const uint8_t *basePointZ; /*!< pointer to curve base point coordinate z */ + const uint32_t *pMontgomeryParam; /*!< pointer to montgomery parameter R2 modulus n*/ +} PKA_ECCProjective2AffineInTypeDef; + +typedef struct +{ + uint32_t modulusSize; /*!< curve modulus p length */ + uint32_t coefSign; /*!< curve coefficient a sign */ + const uint8_t *modulus; /*!< pointer to curve modulus value p */ + const uint8_t *coefA; /*!< pointer to curve coefficient |a| */ + const uint8_t *basePointX1; /*!< pointer to curve base first point coordinate x */ + const uint8_t *basePointY1; /*!< pointer to curve base first point coordinate y */ + const uint8_t *basePointZ1; /*!< pointer to curve base first point coordinate z */ + const uint8_t *basePointX2; /*!< pointer to curve base second point coordinate x */ + const uint8_t *basePointY2; /*!< pointer to curve base second point coordinate y */ + const uint8_t *basePointZ2; /*!< pointer to curve base second point coordinate z */ +} PKA_ECCCompleteAdditionInTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PKA_Exported_Constants PKA Exported Constants + * @{ + */ + +/** @defgroup PKA_Mode PKA mode + * @{ + */ +#define PKA_MODE_MONTGOMERY_PARAM (0x00000001U) +#define PKA_MODE_MODULAR_EXP (0x00000000U) +#define PKA_MODE_MODULAR_EXP_FAST_MODE (0x00000002U) +#define PKA_MODE_ECC_MUL (0x00000020U) +#define PKA_MODE_ECDSA_SIGNATURE (0x00000024U) +#define PKA_MODE_ECDSA_VERIFICATION (0x00000026U) +#define PKA_MODE_POINT_CHECK (0x00000028U) +#define PKA_MODE_RSA_CRT_EXP (0x00000007U) +#define PKA_MODE_MODULAR_INV (0x00000008U) +#define PKA_MODE_ARITHMETIC_ADD (0x00000009U) +#define PKA_MODE_ARITHMETIC_SUB (0x0000000AU) +#define PKA_MODE_ARITHMETIC_MUL (0x0000000BU) +#define PKA_MODE_COMPARISON (0x0000000CU) +#define PKA_MODE_MODULAR_RED (0x0000000DU) +#define PKA_MODE_MODULAR_ADD (0x0000000EU) +#define PKA_MODE_MODULAR_SUB (0x0000000FU) +#define PKA_MODE_MONTGOMERY_MUL (0x00000010U) +#define PKA_MODE_ECC_PROJECTIVE_AFF (0x0000002FU) +#define PKA_MODE_DOUBLE_BASE_LADDER (0x00000027U) +#define PKA_MODE_ECC_COMPLETE_ADD (0x00000023U) +#define PKA_MODE_MODULAR_EXP_PROTECT (0x00000003U) +/** + * @} + */ + +/** @defgroup PKA_Interrupt_configuration_definition PKA Interrupt configuration definition + * @brief PKA Interrupt definition + * @{ + */ +#define PKA_IT_PROCEND PKA_CR_PROCENDIE +#define PKA_IT_ADDRERR PKA_CR_ADDRERRIE +#define PKA_IT_RAMERR PKA_CR_RAMERRIE +#define PKA_IT_OPERR PKA_CR_OPERRIE + +/** + * @} + */ + +/** @defgroup PKA_Flag_definition PKA Flag definition + * @{ + */ +#define PKA_FLAG_PROCEND PKA_SR_PROCENDF +#define PKA_FLAG_ADDRERR PKA_SR_ADDRERRF +#define PKA_FLAG_RAMERR PKA_SR_RAMERRF +#define PKA_FLAG_OPERR PKA_SR_OPERRF + +/** + * @} + */ + +/** @defgroup PKA_Operation_Status PKA Operation Status + * @{ + */ +#define PKA_NO_ERROR 0xD60DUL +#define PKA_FAILED_COMPUTATION 0xCBC9UL +#define PKA_RPART_SIGNATURE_NULL 0xA3B7UL +#define PKA_SPART_SIGNATURE_NULL 0xF946UL + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup PKA_Exported_Macros PKA Exported Macros + * @{ + */ + +/** @brief Reset PKA handle state. + * @param __HANDLE__ specifies the PKA Handle + * @retval None + */ +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) +#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_PKA_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PKA_STATE_RESET) +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + +/** @brief Enable the specified PKA interrupt. + * @param __HANDLE__ specifies the PKA Handle + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable + * @arg @ref PKA_IT_ADDRERR Address error interrupt enable + * @arg @ref PKA_IT_RAMERR RAM error interrupt enable + * @arg @ref PKA_IT_OPERR Operation error interrupt enable + * @retval None + */ +#define __HAL_PKA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** @brief Disable the specified PKA interrupt. + * @param __HANDLE__ specifies the PKA Handle + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable + * @arg @ref PKA_IT_ADDRERR Address error interrupt enable + * @arg @ref PKA_IT_RAMERR RAM error interrupt enable + * @arg @ref PKA_IT_OPERR Operation error interrupt enable + * @retval None + */ +#define __HAL_PKA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified PKA interrupt source is enabled or not. + * @param __HANDLE__ specifies the PKA Handle + * @param __INTERRUPT__ specifies the PKA interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable + * @arg @ref PKA_IT_ADDRERR Address error interrupt enable + * @arg @ref PKA_IT_RAMERR RAM error interrupt enable + * @arg @ref PKA_IT_OPERR Operation error interrupt enable + * @retval The new state of __INTERRUPT__ (SET or RESET) + */ +#define __HAL_PKA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified PKA flag is set or not. + * @param __HANDLE__ specifies the PKA Handle + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref PKA_FLAG_PROCEND End Of Operation + * @arg @ref PKA_FLAG_ADDRERR Address error + * @arg @ref PKA_FLAG_RAMERR RAM error + * @arg @ref PKA_FLAG_OPERR Operation error + * @retval The new state of __FLAG__ (SET or RESET) + */ +#define __HAL_PKA_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\ + & (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the PKA pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the PKA Handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref PKA_FLAG_PROCEND End Of Operation + * @arg @ref PKA_FLAG_ADDRERR Address error + * @arg @ref PKA_FLAG_RAMERR RAM error + * @arg @ref PKA_FLAG_OPERR Operation error + * @retval None + */ +#define __HAL_PKA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) + +/** @brief Enable the specified PKA peripheral. + * @param __HANDLE__ specifies the PKA Handle + * @retval None + */ +#define __HAL_PKA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN)) + +/** @brief Disable the specified PKA peripheral. + * @param __HANDLE__ specifies the PKA Handle + * @retval None + */ +#define __HAL_PKA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN)) + +/** @brief Start a PKA operation. + * @param __HANDLE__ specifies the PKA Handle + * @retval None + */ +#define __HAL_PKA_START(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_START)) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PKA_Exported_Functions + * @{ + */ + +/** @addtogroup PKA_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka); +HAL_StatusTypeDef HAL_PKA_DeInit(PKA_HandleTypeDef *hpka); +void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka); +void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka); + +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, + pPKA_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup PKA_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +/* High Level Functions *******************************************************/ +HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in, + uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in); +void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes); + +HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in); +void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, + PKA_ECDSASignOutExtParamTypeDef *outExt); + +HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in); +uint32_t HAL_PKA_ECDSAVerif_IsValidSignature(PKA_HandleTypeDef const *const hpka); + +HAL_StatusTypeDef HAL_PKA_RSACRTExp(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in); +void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes); + +HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in); +uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka); + +HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in); +void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out); + +HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_Add_IT(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_Sub(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_Sub_IT(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_Cmp(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_Cmp_IT(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_Mul(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_Mul_IT(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ModAdd(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ModAdd_IT(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ModSub(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ModSub_IT(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ModInv(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ModInv_IT(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ModRed(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ModRed_IT(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_MontgomeryMul(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in); +void HAL_PKA_Arithmetic_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes); + +HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in); +void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes); + +HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in, + uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder_IT(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in); +void HAL_PKA_ECCDoubleBaseLadder_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderOutTypeDef *out); + +HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in, + uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine_IT(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in); +void HAL_PKA_ECCProjective2Affine_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineOutTypeDef *out); + +HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in, + uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition_IT(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in); +void HAL_PKA_ECCCompleteAddition_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionOutTypeDef *out); + +HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka); +void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka); +void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka); +void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka); +void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka); +/** + * @} + */ + +/** @addtogroup PKA_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka); +uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_PKA_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pssi.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pssi.h new file mode 100644 index 00000000000..741a78fb07c --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pssi.h @@ -0,0 +1,568 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_pssi.h + * @author MCD Application Team + * @brief Header file of PSSI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_PSSI_H +#define STM32H7RSxx_HAL_PSSI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#if defined(PSSI) + +#ifndef USE_HAL_PSSI_REGISTER_CALLBACKS +/* For backward compatibility, if USE_HAL_PSSI_REGISTER_CALLBACKS not defined, define it to 1*/ +#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + +/** @addtogroup PSSI PSSI + * @brief PSSI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PSSI_Exported_Types PSSI Exported Types + * @{ + */ + + +/** + * @brief PSSI Init structure definition + */ +typedef struct +{ + uint32_t DataWidth; /* !< Configures the data width. + This parameter can be a value of @ref PSSI_DATA_WIDTH. */ + uint32_t BusWidth; /* !< Configures the parallel bus width. + This parameter can be a value of @ref PSSI_BUS_WIDTH. */ + uint32_t ControlSignal; /* !< Configures Data enable and Data ready. + This parameter can be a value of @ref ControlSignal_Configuration. */ + uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity. + This parameter can be a value of @ref Clock_Polarity. */ + uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity. + This parameter can be a value of @ref Data_Enable_Polarity. */ + uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity. + This parameter can be a value of @ref Ready_Polarity. */ + +} PSSI_InitTypeDef; + + +/** + * @brief HAL PSSI State structures definition + */ +typedef enum +{ + HAL_PSSI_STATE_RESET = 0x00U, /* !< PSSI not yet initialized or disabled */ + HAL_PSSI_STATE_READY = 0x01U, /* !< Peripheral initialized and ready for use */ + HAL_PSSI_STATE_BUSY = 0x02U, /* !< An internal process is ongoing */ + HAL_PSSI_STATE_BUSY_TX = 0x03U, /* !< Transmit process is ongoing */ + HAL_PSSI_STATE_BUSY_RX = 0x04U, /* !< Receive process is ongoing */ + HAL_PSSI_STATE_TIMEOUT = 0x05U, /* !< Timeout state */ + HAL_PSSI_STATE_ERROR = 0x06U, /* !< PSSI state error */ + HAL_PSSI_STATE_ABORT = 0x07U, /* !< PSSI process is aborted */ + +} HAL_PSSI_StateTypeDef; + +/** + * @brief PSSI handle Structure definition + */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) +typedef struct __PSSI_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ +{ + PSSI_TypeDef *Instance; /*!< PSSI register base address. */ + PSSI_InitTypeDef Init; /*!< PSSI Initialization Structure. */ + uint32_t *pBuffPtr; /*!< PSSI Data buffer. */ + uint32_t XferCount; /*!< PSSI transfer count */ + uint32_t XferSize; /*!< PSSI transfer size */ +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< PSSI Tx DMA Handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< PSSI Rx DMA Handle parameters */ +#endif /*HAL_DMA_MODULE_ENABLED*/ + +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) + void (* TxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */ + void (* RxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */ + void (* ErrorCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */ + void (* AbortCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer error callback. */ + + void (* MspInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp Init callback. */ + void (* MspDeInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp DeInit callback. */ +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + + HAL_LockTypeDef Lock; /*!< PSSI lock. */ + __IO HAL_PSSI_StateTypeDef State; /*!< PSSI transfer state. */ + __IO uint32_t ErrorCode; /*!< PSSI error code. */ + +} PSSI_HandleTypeDef; + +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) +/** + * @brief HAL PSSI Callback pointer definition + */ +typedef void (*pPSSI_CallbackTypeDef)(PSSI_HandleTypeDef *hpssi); /*!< Pointer to a PSSI common callback function */ + +/** + * @brief HAL PSSI Callback ID enumeration definition + */ +typedef enum +{ + HAL_PSSI_TX_COMPLETE_CB_ID = 0x00U, /*!< PSSI Tx Transfer completed callback ID */ + HAL_PSSI_RX_COMPLETE_CB_ID = 0x01U, /*!< PSSI Rx Transfer completed callback ID */ + HAL_PSSI_ERROR_CB_ID = 0x03U, /*!< PSSI Error callback ID */ + HAL_PSSI_ABORT_CB_ID = 0x04U, /*!< PSSI Abort callback ID */ + + HAL_PSSI_MSPINIT_CB_ID = 0x05U, /*!< PSSI Msp Init callback ID */ + HAL_PSSI_MSPDEINIT_CB_ID = 0x06U /*!< PSSI Msp DeInit callback ID */ + +} HAL_PSSI_CallbackIDTypeDef; +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PSSI_Exported_Constants PSSI Exported Constants + * @{ + */ + +/** @defgroup PSSI_Error_Code PSSI Error Code + * @{ + */ +#define HAL_PSSI_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_PSSI_ERROR_NOT_SUPPORTED 0x00000001U /*!< Not supported operation */ +#define HAL_PSSI_ERROR_UNDER_RUN 0x00000002U /*!< FIFO Under-run error */ +#define HAL_PSSI_ERROR_OVER_RUN 0x00000004U /*!< FIFO Over-run error */ +#define HAL_PSSI_ERROR_DMA 0x00000008U /*!< Dma error */ +#define HAL_PSSI_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) +#define HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error */ +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup PSSI_DATA_WIDTH PSSI Data Width + * @{ + */ + +#define HAL_PSSI_8BITS 0x00000000U /*!< 8 Bits */ +#define HAL_PSSI_16BITS 0x00000001U /*!< 16 Bits */ +#define HAL_PSSI_32BITS 0x00000002U /*!< 32 Bits */ +/** + * @} + */ + +/** @defgroup PSSI_BUS_WIDTH PSSI Bus Width + * @{ + */ + +#define HAL_PSSI_8LINES 0x00000000U /*!< 8 data lines */ +#define HAL_PSSI_16LINES PSSI_CR_EDM /*!< 16 data lines */ +/** + * @} + */ +/** @defgroup PSSI_MODE PSSI mode + * @{ + */ +#define HAL_PSSI_UNIDIRECTIONAL 0x00000000U /*!< Uni-directional mode */ +#define HAL_PSSI_BIDIRECTIONAL 0x00000001U /*!< Bi-directional mode */ +/** + * @} + */ + +/** @defgroup ControlSignal_Configuration ControlSignal Configuration + * @{ + */ +#define HAL_PSSI_DE_RDY_DISABLE (0x0U << PSSI_CR_DERDYCFG_Pos) /*!< Neither DE nor RDY are enabled */ +#define HAL_PSSI_RDY_ENABLE (0x1U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled */ +#define HAL_PSSI_DE_ENABLE (0x2U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled */ +#define HAL_PSSI_DE_RDY_ALT_ENABLE (0x3U << PSSI_CR_DERDYCFG_Pos) /*!< Both RDY and DE alternate functions enabled */ +#define HAL_PSSI_MAP_RDY_BIDIR_ENABLE (0x4U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on RDY pin */ +#define HAL_PSSI_RDY_MAP_ENABLE (0x5U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled, mapped to DE pin */ +#define HAL_PSSI_DE_MAP_ENABLE (0x6U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled, mapped to RDY pin */ +#define HAL_PSSI_MAP_DE_BIDIR_ENABLE (0x7U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on DE pin */ + +/** + * @} + */ + + +/** @defgroup Data_Enable_Polarity Data Enable Polarity + * @{ + */ +#define HAL_PSSI_DEPOL_ACTIVE_LOW 0x0U /*!< Active Low */ +#define HAL_PSSI_DEPOL_ACTIVE_HIGH PSSI_CR_DEPOL /*!< Active High */ +/** + * @} + */ +/** @defgroup Ready_Polarity Ready Polarity + * @{ + */ +#define HAL_PSSI_RDYPOL_ACTIVE_LOW 0x0U /*!< Active Low */ +#define HAL_PSSI_RDYPOL_ACTIVE_HIGH PSSI_CR_RDYPOL /*!< Active High */ +/** + * @} + */ + +/** @defgroup Clock_Polarity Clock Polarity + * @{ + */ +#define HAL_PSSI_FALLING_EDGE 0x0U /*!< Fallling Edge */ +#define HAL_PSSI_RISING_EDGE 0x1U /*!< Rising Edge */ +/** + * @} + */ + +/** @defgroup Clock_Source Clock Source + * @{ + */ +#define HAL_PSSI_CLOCK_EXT 0x0U /*!< External Clock */ +#define HAL_PSSI_CLOCK_INT PSSI_CR_CKSRC /*!< Internal Clock */ +/** + * @} + */ + + +/** @defgroup PSSI_DEFINITION PSSI definitions + * @{ + */ + +#define PSSI_MAX_NBYTE_SIZE 0x10000U /* 64 KB */ +#define PSSI_TIMEOUT_TRANSMIT 0x0000FFFFU /*!< Timeout Value */ + +#define PSSI_CR_OUTEN_INPUT 0x00000000U /*!< Input Mode */ +#define PSSI_CR_OUTEN_OUTPUT PSSI_CR_OUTEN /*!< Output Mode */ + +#define PSSI_CR_DMA_ENABLE PSSI_CR_DMAEN /*!< DMA Mode Enable */ +#define PSSI_CR_DMA_DISABLE (~PSSI_CR_DMAEN) /*!< DMA Mode Disable*/ + +#define PSSI_CR_16BITS PSSI_CR_EDM /*!< 16 Lines Mode */ +#define PSSI_CR_8BITS (~PSSI_CR_EDM) /*!< 8 Lines Mode */ + +#define PSSI_FLAG_RTT1B PSSI_SR_RTT1B /*!< 1 Byte Fifo Flag */ +#define PSSI_FLAG_RTT4B PSSI_SR_RTT4B /*!< 4 Bytes Fifo Flag*/ + + + +/** + * @} + */ + +/** @defgroup PSSI_Interrupts PSSI Interrupts + * @{ + */ + +#define PSSI_FLAG_OVR_RIS PSSI_RIS_OVR_RIS /*!< Overrun, Underrun errors flag */ +#define PSSI_FLAG_MASK PSSI_RIS_OVR_RIS_Msk /*!< Overrun, Underrun errors Mask */ +#define PSSI_FLAG_OVR_MIS PSSI_MIS_OVR_MIS /*!< Overrun, Underrun masked errors flag */ +/** + * @} + */ + + + +/** + * @} + */ +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup PSSI_Exported_Macros PSSI Exported Macros + * @{ + */ + +/** @brief Reset PSSI handle state + * @param __HANDLE__ specifies the PSSI handle. + * @retval None + */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) +#define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_PSSI_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + }while(0) +#else +#define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PSSI_STATE_RESET) +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + + +/** + * @brief Enable the PSSI. + * @param __HANDLE__ PSSI handle + * @retval None. + */ +#define HAL_PSSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= PSSI_CR_ENABLE) +/** + * @brief Disable the PSSI. + * @param __HANDLE__ PSSI handle + * @retval None. + */ +#define HAL_PSSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~PSSI_CR_ENABLE)) + +/* PSSI pripheral STATUS */ +/** + * @brief Get the PSSI pending flags. + * @param __HANDLE__ PSSI handle + * @param __FLAG__ flag to check. + * This parameter can be any combination of the following values: + * @arg PSSI_FLAG_RTT1B: FIFO is ready to transfer one byte + * @arg PSSI_FLAG_RTT4B: FIFO is ready to transfer four bytes + * @retval The state of FLAG. + */ + +#define HAL_PSSI_GET_STATUS(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__)) + + + +/* Interrupt & Flag management */ +/** + * @brief Get the PSSI pending flags. + * @param __HANDLE__ PSSI handle + * @param __FLAG__ flag to check. + * This parameter can be any combination of the following values: + * @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag + * @retval The state of FLAG. + */ +#define HAL_PSSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RIS & (__FLAG__)) + +/** + * @brief Clear the PSSI pending flags. + * @param __HANDLE__ PSSI handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag + * @retval None + */ +#define HAL_PSSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** + * @brief Enable the specified PSSI interrupts. + * @param __HANDLE__ PSSI handle + * @param __INTERRUPT__ specifies the PSSI interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg PSSI_FLAG_OVR_RIS: Configuration error mask + * @retval None + */ +#define HAL_PSSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** + * @brief Disable the specified PSSI interrupts. + * @param __HANDLE__ PSSI handle + * @param __INTERRUPT__ specifies the PSSI interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg PSSI_IT_OVR_IE: Configuration error mask + * @retval None + */ +#define HAL_PSSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified PSSI interrupt source is enabled or not. + * @param __HANDLE__ PSSI handle + * @param __INTERRUPT__ specifies the PSSI interrupt source to check. + * This parameter can be one of the following values: + * @arg PSSI_IT_OVR_IE: Data Buffer overrun/underrun error interrupt mask + * @retval The state of INTERRUPT source. + */ +#define HAL_PSSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) + + +/** + * @brief Check whether the PSSI Control signal is valid. + * @param __CONTROL__ Control signals configuration + * @retval Valid or not. + */ + +#define IS_PSSI_CONTROL_SIGNAL(__CONTROL__) (((__CONTROL__) == HAL_PSSI_DE_RDY_DISABLE ) || \ + ((__CONTROL__) == HAL_PSSI_RDY_ENABLE ) || \ + ((__CONTROL__) == HAL_PSSI_DE_ENABLE ) || \ + ((__CONTROL__) == HAL_PSSI_DE_RDY_ALT_ENABLE ) || \ + ((__CONTROL__) == HAL_PSSI_MAP_RDY_BIDIR_ENABLE ) || \ + ((__CONTROL__) == HAL_PSSI_RDY_MAP_ENABLE ) || \ + ((__CONTROL__) == HAL_PSSI_DE_MAP_ENABLE ) || \ + ((__CONTROL__) == HAL_PSSI_MAP_DE_BIDIR_ENABLE )) + + + +/** + * @brief Check whether the PSSI Bus Width is valid. + * @param __BUSWIDTH__ PSSI Bush width + * @retval Valid or not. + */ + +#define IS_PSSI_BUSWIDTH(__BUSWIDTH__) (((__BUSWIDTH__) == HAL_PSSI_8LINES ) || \ + ((__BUSWIDTH__) == HAL_PSSI_16LINES )) + +/** + + * @brief Check whether the PSSI Clock Polarity is valid. + * @param __CLOCKPOL__ PSSI Clock Polarity + * @retval Valid or not. + */ + +#define IS_PSSI_CLOCK_POLARITY(__CLOCKPOL__) (((__CLOCKPOL__) == HAL_PSSI_FALLING_EDGE ) || \ + ((__CLOCKPOL__) == HAL_PSSI_RISING_EDGE )) + + +/** + * @brief Check whether the PSSI Data Enable Polarity is valid. + * @param __DEPOL__ PSSI DE Polarity + * @retval Valid or not. + */ + +#define IS_PSSI_DE_POLARITY(__DEPOL__) (((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_LOW ) || \ + ((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_HIGH )) + +/** + * @brief Check whether the PSSI Ready Polarity is valid. + * @param __RDYPOL__ PSSI RDY Polarity + * @retval Valid or not. + */ + +#define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW ) || \ + ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH )) + +/** + * @brief Check whether the PSSI Clock source is valid. + * @param __CLOCKSRC__ PSSI Clock Source + * @retval Valid or not. + */ + +#define IS_PSSI_CLOCK_SOURCE(__CLOCKSRC__) (((__CLOCKSRC__) == HAL_PSSI_CLOCK_EXT ) || \ + ((__CLOCKSRC__) == HAL_PSSI_CLOCK_INT )) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PSSI_Exported_Functions PSSI Exported Functions + * @{ + */ + +/** @addtogroup PSSI_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi); +HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi); +void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi); +void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, + pPSSI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + +/** + * @} + */ + + +/** @addtogroup PSSI_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size); +HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size); +HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi); +#endif /*HAL_DMA_MODULE_ENABLED*/ + +/** + * @} + */ + +/** @addtogroup PSSI_Exported_Functions_Group3 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State functions ***************************************************/ +HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi); +uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi); + +/** + * @} + */ + +/** @addtogroup PSSI_Exported_Functions_Group4 Clock Source Selection function + * @{ + */ +/* Clock source selection function *******************************************/ +HAL_StatusTypeDef HAL_PSSI_ClockConfig(PSSI_HandleTypeDef *hpssi, uint32_t ClockSource); + +/** + * @} + */ + +/** @addtogroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi); +void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi); +void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi); +void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi); +void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi); + +/** + * @} + */ + + + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + + +/* Private macros ------------------------------------------------------------*/ + + +/** + * @} + */ +#endif /* PSSI */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_PSSI_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pwr.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pwr.h new file mode 100644 index 00000000000..31258205605 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pwr.h @@ -0,0 +1,589 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_PWR_H +#define STM32H7RSxx_HAL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< Specifies the PVD detection level. + This parameter can be a value of + @ref PWR_PVD_Detection_Level. */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode. */ +} PWR_PVDTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_WakeUp_Pins PWR Wake-Up Pins + * @{ + */ +/* High level and No pull (default configuration) */ +#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wakeup pin 4 (with high level polarity) */ +#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wakeup pin 3 (with high level polarity) */ +#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wakeup pin 2 (with high level polarity) */ +#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wakeup pin 1 (with high level polarity) */ + +/* High level and No pull */ +#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4 /*!< Wakeup pin 4 (with high level polarity) */ +#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3 /*!< Wakeup pin 3 (with high level polarity) */ +#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2 /*!< Wakeup pin 2 (with high level polarity) */ +#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1 /*!< Wakeup pin 1 (with high level polarity) */ + +/* Low level and No pull */ +#define PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4) /*!< Wakeup pin 4 (with low level polarity) */ +#define PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3) /*!< Wakeup pin 3 (with low level polarity) */ +#define PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2) /*!< Wakeup pin 2 (with low level polarity) */ +#define PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1) /*!< Wakeup pin 1 (with low level polarity) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Detection_Level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_1 (0x00000000U) /*!< Programmable voltage detector level 1 selection : 1V95 */ +#define PWR_PVDLEVEL_2 PWR_CR1_PLS_0 /*!< Programmable voltage detector level 2 selection : 2V1 */ +#define PWR_PVDLEVEL_3 PWR_CR1_PLS_1 /*!< Programmable voltage detector level 3 selection : 2V25 */ +#define PWR_PVDLEVEL_4 (PWR_CR1_PLS_1 | PWR_CR1_PLS_0) /*!< Programmable voltage detector level 4 selection : 2V4 */ +#define PWR_PVDLEVEL_5 PWR_CR1_PLS_2 /*!< Programmable voltage detector level 5 selection : 2V55 */ +#define PWR_PVDLEVEL_6 (PWR_CR1_PLS_2 | PWR_CR1_PLS_0) /*!< Programmable voltage detector level 6 selection : 2V7 */ +#define PWR_PVDLEVEL_7 (PWR_CR1_PLS_2 | PWR_CR1_PLS_1) /*!< Programmable voltage detector level 7 selection : 2V85 */ +#define PWR_PVDLEVEL_EXT_VOL (PWR_CR1_PLS_2 | PWR_CR1_PLS_1 | PWR_CR1_PLS_0) /*!< External input analog voltage (Compare internally to VREF) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_LP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +/* define for interface compatibility purpose */ +#define PWR_MAINREGULATOR_ON (0x0U) + +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI (0x01U) +#define PWR_SLEEPENTRY_WFE (0x02U) +#define PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR (0x03U) +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI (0x01U) +#define PWR_STOPENTRY_WFE (0x02U) +#define PWR_STOPENTRY_WFE_NO_EVT_CLEAR (0x03U) +/** + * @} + */ + +/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale + * @{ + */ +#define PWR_REGULATOR_VOLTAGE_SCALE0 PWR_CSR4_VOS /*!< Voltage scaling range 0 (highest frequency) */ +#define PWR_REGULATOR_VOLTAGE_SCALE1 (0U) /*!< Voltage scaling range 1 (lowest power) */ + +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Status Flags + * Elements values convention: 0000 0XXX XXXY YYYYb + * - Y YYYY : Flag position in the XXX register (5 bits) + * - XXX XXX : Status register (6 bits) + * - 000001: SR1 register + * - 000010: CSR1 register + * - 000100: CSR2 register + * - 001000: CSR3 register + * - 010000: CSR4 register + * - 100000: WKUPCR register + * The only exception is PWR_FLAG_WU, encompassing all + * wake-up flags and set to PWR_SR1_WUF. + * @{ + */ +/* SR1 */ +#define PWR_FLAG_AVDO (0x002DU) /*!< Analog voltage detector output on VDDA */ +#define PWR_FLAG_PVDO (0x0024U) /*!< Programmable voltage detect output */ +#define PWR_FLAG_ACTVOSRDY (0x0021U) /*!< Voltage levels ready bit for currently used ACTVOS and SDHILEVEL */ +#define PWR_FLAG_ACTVOS (0x0020U) /*!< Programmable voltage detect output */ + +/* CSR1 */ +#define PWR_FLAG_TEMPH (0x0057U) /*!< Temperature level monitoring versus high threshold */ +#define PWR_FLAG_TEMPL (0x0056U) /*!< Temperature level monitoring versus low threshold */ +#define PWR_FLAG_VBATH (0x0055U) /*!< VBAT level monitoring versus high threshold */ +#define PWR_FLAG_VBATL (0x0054U) /*!< VBAT level monitoring versus low threshold */ +#define PWR_FLAG_BRRDY (0x0050U) /*!< Backup regulator ready */ + +/* CSR2 */ +#define PWR_FLAG_USB33RDY (0x009AU) /*!< USB supply ready */ +#define PWR_FLAG_SDEXTRDY (0x0090U) /*!< SMPS step-down converter external supply ready */ + +/* CSR3 */ +#define PWR_FLAG_SBF (0x0109U) /*!< System Standby flag */ +#define PWR_FLAG_STOPF (0x0108U) /*!< System Stop flag */ + +/* CSR4 */ +#define PWR_FLAG_VOSRDY (0x0201U) /*!< VOS Ready bit for VCORE voltage scaling output selection */ + +/* WKUPCR & WKUPFR */ +#define PWR_FLAG_WUF1 (0x0400U) /*!< Wakeup event on wakeup pin 1 */ +#define PWR_FLAG_WUF2 (0x0401U) /*!< Wakeup event on wakeup pin 2 */ +#define PWR_FLAG_WUF3 (0x0402U) /*!< Wakeup event on wakeup pin 3 */ +#define PWR_FLAG_WUF4 (0x0403U) /*!< Wakeup event on wakeup pin 4 */ +#define PWR_FLAG_WUF_ALL (0x0404U) /*!< Wakeup flag all */ +/** + * @} + */ + +/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask + * @{ + */ +#define PWR_EWUP_MASK (0x00FF0F0FU) +/** + * @} + */ + +/** @defgroup PWR_Flag_WUP PWR Flag WakeUp + * @{ + */ +#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1 +#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2 +#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3 +#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4 +#define PWR_FLAG_WKUP PWR_WKUPCR_WKUPC +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief Check whether or not a specific PWR flag is set. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_ACTVOS: This flag indicates that the regulator voltage + * scaling output selection is ready. + * @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the regulator voltage + * scaling output selection is ready. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD + * is enabled by the HAL_PWR_EnablePVD()function. + * The PVD is stopped by STANDBY mode. For this reason, + * this bit is equal to 0 after STANDBY or reset until the + * PVDE bit is set. + * @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled + * by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode. + * For this reason, this bit is equal to 0 after Standby or reset + * until the AVDE bit is set. + * @arg PWR_FLAG_BRRDY : Backup regulator ready flag. This bit is not reset + * when the device wakes up from Standby mode or by a system reset + * or power reset. + * @arg PWR_FLAG_VBATL: This flag indicates if the VBAT level is above + * the low monitoring threshold. + * @arg PWR_FLAG_VBATH: This flag indicates if the VBAT level is above + * the high monitoring threshold. + * @arg PWR_FLAG_TEMPL This flag indicates if the temperature level is above + * the low monitoring threshold. + * @arg PWR_FLAG_TEMPH: This flag indicates if the temperature level is above + * the high monitoring threshold. + * @arg PWR_FLAG_SDEXTRDY: This flag indicates if the external supply + * from the SMPS step-down converter is ready. + * @arg PWR_FLAG_USB33RDY: This flag indicates if the USB supply is ready. + * @arg PWR_FLAG_STOPF: STOP mode flag + * @arg PWR_FLAG_SBF: Standby mode flag + * @arg PWR_FLAG_VOSRDY When an internal regulator is used, this bit indicates + * that all the features allowed by the selected VOS can be used. + * @arg PWR_FLAG_WUF1: This flag indicates a wakeup event was + * received from WKUP1 pin. + * @arg PWR_FLAG_WUF2: This flag indicates a wakeup event was + * received from WKUP2 pin. + * @arg PWR_FLAG_WUF3: This flag indicates a wakeup event was + * received from WKUP3 pin. + * @arg PWR_FLAG_WUF4: This flag indicates a wakeup event was + * received from WKUP4 pin. + * @retval The (__FLAG__) state (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ( \ + ((__FLAG__) == PWR_FLAG_ACTVOS) ? ((PWR->SR1 & PWR_SR1_ACTVOS) == PWR_SR1_ACTVOS) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY)? ((PWR->SR1 & PWR_SR1_ACTVOSRDY) == PWR_SR1_ACTVOSRDY) : \ + ((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->SR1 & PWR_SR1_PVDO) == PWR_SR1_PVDO) : \ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->SR1 & PWR_SR1_AVDO) == PWR_SR1_AVDO) : \ + ((__FLAG__) == PWR_FLAG_BRRDY) ? ((PWR->CSR1 & PWR_CSR1_BRRDY) == PWR_CSR1_BRRDY) : \ + ((__FLAG__) == PWR_FLAG_VBATL) ? ((PWR->CSR1 & PWR_CSR1_VBATL) == PWR_CSR1_VBATL) : \ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CSR1 & PWR_CSR1_VBATH) == PWR_CSR1_VBATH) : \ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CSR1 & PWR_CSR1_TEMPL) == PWR_CSR1_TEMPL) : \ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CSR1 & PWR_CSR1_TEMPH) == PWR_CSR1_TEMPH) : \ + ((__FLAG__) == PWR_FLAG_SDEXTRDY) ? ((PWR->CSR2 & PWR_CSR2_SDEXTRDY) == PWR_CSR2_SDEXTRDY) : \ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CSR2 & PWR_CSR2_USB33RDY) == PWR_CSR2_USB33RDY) : \ + ((__FLAG__) == PWR_FLAG_STOPF) ? ((PWR->CSR3 & PWR_CSR3_STOPF) == PWR_CSR3_STOPF) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? ((PWR->CSR3 & PWR_CSR3_SBF) == PWR_CSR3_SBF) : \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->CSR4 & PWR_CSR4_VOSRDY) == PWR_CSR4_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_WUF1) ? ((PWR->WKUPFR & PWR_WKUPFR_WKUPF1) == PWR_WKUPFR_WKUPF1) : \ + ((__FLAG__) == PWR_FLAG_WUF2) ? ((PWR->WKUPFR & PWR_WKUPFR_WKUPF2) == PWR_WKUPFR_WKUPF2) : \ + ((__FLAG__) == PWR_FLAG_WUF3) ? ((PWR->WKUPFR & PWR_WKUPFR_WKUPF3) == PWR_WKUPFR_WKUPF3) : \ + ((PWR->WKUPFR & PWR_WKUPFR_WKUPF4) == PWR_WKUPFR_WKUPF4)) + +/** @brief Clear PWR flags. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_STOPF : Stop flag. + * Indicates that the device was resumed from Stop mode. + * @arg PWR_FLAG_SBF : Standby flag. + * Indicates that the device was resumed from Standby mode. + * @arg PWR_FLAG_WUF1 : Wakeup flag 1. + * Indicates that a wakeup event was received from the WKUP line 1. + * @arg PWR_FLAG_WUF2 : Wakeup flag 2. + * Indicates that a wakeup event was received from the WKUP line 2. + * @arg PWR_FLAG_WUF3 : Wakeup flag 3. + * Indicates that a wakeup event was received from the WKUP line 3. + * @arg PWR_FLAG_WUF4 : Wakeup flag 4. + * Indicates that a wakeup event was received from the WKUP line 4. + * @arg PWR_FLAG_WUF_ALL: All Wakeup flags. + * @retval None. + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->CSR3, PWR_CSR3_CSSF)) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->CSR3, PWR_CSR3_CSSF)) : \ + ((__FLAG__) == PWR_FLAG_WUF1) ? (SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC1)) : \ + ((__FLAG__) == PWR_FLAG_WUF2) ? (SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC2)) : \ + ((__FLAG__) == PWR_FLAG_WUF3) ? (SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC3)) : \ + ((__FLAG__) == PWR_FLAG_WUF4) ? (SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC4)) : \ + (SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC))) + +/** @brief Check PWR wake up flags are set or not. + * @param __FLAG__: specifies the wake up flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WKUP1 : This parameter gets Wake up line 1 flag. + * @arg PWR_FLAG_WKUP2 : This parameter gets Wake up line 2 flag. + * @arg PWR_FLAG_WKUP3 : This parameter gets Wake up line 3 flag. + * @arg PWR_FLAG_WKUP4 : This parameter gets Wake up line 4 flag. + * @arg PWR_FLAG_WKUP : This parameter gets Wake up lines 1 to 4 flags. + * @retval The (__FLAG__) state (TRUE or FALSE). + */ +#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1) + +/** @brief Clear CPU PWR wake up flags. + * @param __FLAG__ : Specifies the wake up flag to be cleared. + * This parameter can be one of the following values : + * @arg PWR_FLAG_WKUP1 : This parameter clears Wake up line 1 flag. + * @arg PWR_FLAG_WKUP2 : This parameter clears Wake up line 2 flag. + * @arg PWR_FLAG_WKUP3 : This parameter clears Wake up line 3 flag. + * @arg PWR_FLAG_WKUP4 : This parameter clears Wake up line 4 flag. + * @arg PWR_FLAG_WKUP : This parameter clears Wake up lines 1 to 4 flags. + * @retval None. + */ +#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__)) + +/** + * @brief Enable the PVD Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Event Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Event Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0); + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0); + +/** + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) + +/** + * @brief Clear the PVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Generates a Software interrupt on PVD EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32h7rsxx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions + * @{ + */ +/* Peripheral Control Functions **********************************************/ +/* PVD configuration */ +void HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* WakeUp pins configuration */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes entry */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +/* Cortex System Control functions *******************************************/ +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line + * @{ + */ +#define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16 /*!< External interrupt line 16 connected to the PVD EXTI Line */ +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters + * @{ + */ +/* Check PVD level parameter */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_1) ||\ + ((LEVEL) == PWR_PVDLEVEL_2) ||\ + ((LEVEL) == PWR_PVDLEVEL_3) ||\ + ((LEVEL) == PWR_PVDLEVEL_4) ||\ + ((LEVEL) == PWR_PVDLEVEL_5) ||\ + ((LEVEL) == PWR_PVDLEVEL_6) ||\ + ((LEVEL) == PWR_PVDLEVEL_7) ||\ + ((LEVEL) == PWR_PVDLEVEL_EXT_VOL)) + +/* Check PVD mode parameter */ +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_NORMAL)) + +/* Check low power regulator parameter */ +#define IS_PWR_REGULATOR(REGULATOR) ((REGULATOR) == PWR_MAINREGULATOR_ON) + +/* Check low power mode entry parameter */ +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\ + ((ENTRY) == PWR_SLEEPENTRY_WFE) ||\ + ((ENTRY) == PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)) + +/* Check low power mode entry parameter */ +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\ + ((ENTRY) == PWR_STOPENTRY_WFE) ||\ + ((ENTRY) == PWR_STOPENTRY_WFE_NO_EVT_CLEAR)) + +/* Check voltage scale level parameter */ +#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1)) + + +/* Check wake up pin parameter */ +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ + ((PIN) == PWR_WAKEUP_PIN2) ||\ + ((PIN) == PWR_WAKEUP_PIN3) ||\ + ((PIN) == PWR_WAKEUP_PIN4) ||\ + ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN3_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32H7RSxx_HAL_PWR_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pwr_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pwr_ex.h new file mode 100644 index 00000000000..743652c2a95 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_pwr_ex.h @@ -0,0 +1,610 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_PWR_EX_H +#define STM32H7RSxx_HAL_PWR_EX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Types PWREx Exported Types + * @{ + */ +/** + * @brief PWREx AVD configuration structure definition + */ +typedef struct +{ + uint32_t AVDLevel; /*!< Specifies the AVD detection level. + This parameter can be a value of @ref PWREx_AVD_detection_level */ + + uint32_t Mode; /*!< Specifies the EXTI operating mode for the AVD event. + This parameter can be a value of @ref PWREx_AVD_Mode. */ +} PWREx_AVDTypeDef; + +/** + * @brief PWREx Wakeup pin configuration structure definition + */ +typedef struct +{ + uint32_t WakeUpPin; /*!< Specifies the Wake-Up pin to be enabled. + This parameter can be a value of @ref PWR_WakeUp_Pins */ + + uint32_t PinPolarity; /*!< Specifies the Wake-Up pin polarity. + This parameter can be a value of @ref PWREx_PIN_Polarity */ + + uint32_t PinPull; /*!< Specifies the Wake-Up pin pull. + This parameter can be a value of @ref PWREx_PIN_Pull */ +} PWREx_WakeupPinTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ + +/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration + * @{ + */ +#define PWR_PIN_POLARITY_HIGH (0x0U) +#define PWR_PIN_POLARITY_LOW (0x1U) +/** + * @} + */ + +/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration + * @{ + */ +#define PWR_PIN_NO_PULL (0x0U) +#define PWR_PIN_PULL_UP (0x1U) +#define PWR_PIN_PULL_DOWN (0x2U) +/** + * @} + */ + +/** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags. + * @{ + */ +#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */ +#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */ +#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PC13 */ +#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC1 */ + +#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\ + PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4) +/** + * @} + */ + +/** @defgroup PWREx_Supply_configuration PWREx Supply configuration + * @{ + */ +#define PWR_LDO_SUPPLY PWR_CSR2_LDOEN /*!< Core domains are supplied from the LDO */ +#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CSR2_BYPASS /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */ +#define PWR_DIRECT_SMPS_SUPPLY PWR_CSR2_SDEN /*!< Core domains are supplied from the SMPS only */ + +#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CSR2_SDHILEVEL | PWR_CSR2_SDEN | PWR_CSR2_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ +#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | PWR_CSR2_SDEN | PWR_CSR2_LDOEN) /*!< The SMPS 1.8V output supplies external circuits and the LDO. The Core domains are supplied from the LDO */ +#define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | PWR_CSR2_SDEN | PWR_CSR2_BYPASS) /*!< The SMPS 1.8V output supplies external source which supplies the Core domains */ + +#define PWR_SUPPLY_CONFIG_MASK (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | \ + PWR_CSR2_SDEN | PWR_CSR2_LDOEN | PWR_CSR2_BYPASS) + +/** + * @} + */ + + +/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level + * @{ + */ +#define PWR_AVDLEVEL_1 (0x0U) /*!< Analog voltage detector level 1 : 1V7 */ +#define PWR_AVDLEVEL_2 PWR_CR1_ALS_0 /*!< Analog voltage detector level 2 : 2V1 */ +#define PWR_AVDLEVEL_3 PWR_CR1_ALS_1 /*!< Analog voltage detector level 3 : 2V5 */ +#define PWR_AVDLEVEL_4 (PWR_CR1_ALS_1 | PWR_CR1_ALS_0) /*!< Analog voltage detector level 4 : 2V8 */ + +/** + * @} + */ + +/** @defgroup PWREx_AVD_Mode PWREx AVD Mode + * @{ + */ +#define PWR_AVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ +#define PWR_AVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_AVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_AVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_AVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale + * @{ + */ +#define PWR_REGULATOR_STOP_VOLTAGE_SCALE3 PWR_CR1_SVOS /*!< System Stop mode voltage scaling range 3 (highest frequency) */ +#define PWR_REGULATOR_STOP_VOLTAGE_SCALE5 (0x0U) /*!< System Stop mode voltage scaling range 5 (lowest power) */ + +/** + * @} + */ + +/** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection + * @{ + */ +#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x0U) /*!< VBAT charging through a 5 kOhms resistor */ +#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CSR2_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ +/** + * @} + */ + +/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds + * @{ + */ +#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0x0U) +#define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CSR1_VBATL +#define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CSR1_VBATH +/** + * @} + */ + +/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds + * @{ + */ +#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) +#define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CSR1_TEMPL +#define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CSR1_TEMPH +/** + * @} + */ + +/** @defgroup PWREx_CAPACITOR_Port PWREx Capacitor Port + * @{ + */ +#define PWR_CAPACITOR_PORT1 PWR_CSR2_XSPICAP1 +#define PWR_CAPACITOR_PORT2 PWR_CSR2_XSPICAP2 +/** + * @} + */ + +/** @defgroup PWREx_CAPACITOR_Value PWREx Capacitor Value + * @{ + */ +#define PWR_CAPACITOR_OFF (0x0U) +#define PWR_CAPACITOR_ONE_THIRD_CAPACITANCE PWR_CSR2_XSPICAP1_0 +#define PWR_CAPACITOR_TWO_THIRD_CAPACITANCE PWR_CSR2_XSPICAP1_1 +#define PWR_CAPACITOR_FULL_CAPACITANCE PWR_CSR2_XSPICAP1 +/** + * @} + */ + +/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16 + * @{ + */ +#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16 connected to the AVD EXTI Line */ +/** + * @} + */ + +/** @defgroup PWREx_GPIO_PullUp_Port PWR Extended GPIO Pull-Up Port + * @{ + */ +#define PWR_GPIO_PULLUP_PORT_N (0x00U) /*!< GPIO port N */ +#define PWR_GPIO_PULLUP_PORT_O (0x01U) /*!< GPIO port O */ +/** + * @} + */ + +/** @defgroup PWREx_GPIO_PullDown_Port PWR Extended GPIO Pull-Down Port + * @{ + */ +#define PWR_GPIO_PULLDOWN_PORT_N (0x00U) /*!< GPIO port N */ +#define PWR_GPIO_PULLDOWN_PORT_O (0x01U) /*!< GPIO port O */ +#define PWR_GPIO_PULLDOWN_PORT_P (0x02U) /*!< GPIO port P */ +/** + * @} + */ + +/** @defgroup PWREx_GPIO_PullUp_Pin_Mask PWR Extended GPIO Pull-Up Pin Mask + * @{ + */ +#define PWR_GPIO_N_PULLUP_PIN_1 (0x0002U) /*!< GPIO N pin 1 */ +#define PWR_GPIO_N_PULLUP_PIN_6 (0x0040U) /*!< GPIO N pin 6 */ +#define PWR_GPIO_N_PULLUP_PIN_12 (0x1000U) /*!< GPIO N pin 12 */ + +#define PWR_GPIO_O_PULLUP_PIN_0 (0x0001U) /*!< GPIO O pin 0 */ +#define PWR_GPIO_O_PULLUP_PIN_1 (0x0002U) /*!< GPIO O pin 1 */ +#define PWR_GPIO_O_PULLUP_PIN_4 (0x0010U) /*!< GPIO O pin 4 */ +/** + * @} + */ + +/** @defgroup PWREx_GPIO_PullDown_Pin_Mask PWR Extended GPIO Pull-Down Pin Mask + * @{ + */ +#define PWR_GPIO_N_PULLDOWN_PIN_0 (0x0001U) /*!< GPIO N pin 0 */ +#define PWR_GPIO_N_PULLDOWN_PIN_1 (0x0002U) /*!< GPIO N pin 1 */ +#define PWR_GPIO_N_PULLDOWN_PIN_2_5 (0x0004U) /*!< GPIO N pin 2 to 5 */ +#define PWR_GPIO_N_PULLDOWN_PIN_6 (0x0040U) /*!< GPIO N pin 6 */ +#define PWR_GPIO_N_PULLDOWN_PIN_8_11 (0x0100U) /*!< GPIO N pin 8 to 11 */ +#define PWR_GPIO_N_PULLDOWN_PIN_12 (0x1000U) /*!< GPIO N pin 12 */ + +#define PWR_GPIO_O_PULLDOWN_PIN_0 (0x0001U) /*!< GPIO O pin 0 */ +#define PWR_GPIO_O_PULLDOWN_PIN_1 (0x0002U) /*!< GPIO O pin 1 */ +#define PWR_GPIO_O_PULLDOWN_PIN_2 (0x0004U) /*!< GPIO O pin 2 */ +#define PWR_GPIO_O_PULLDOWN_PIN_3 (0x0008U) /*!< GPIO O pin 3 */ +#define PWR_GPIO_O_PULLDOWN_PIN_4 (0x0010U) /*!< GPIO O pin 4 */ + +#define PWR_GPIO_P_PULLDOWN_PIN_0_3 (0x0001U) /*!< GPIO P pin 0 to 3 */ +#define PWR_GPIO_P_PULLDOWN_PIN_4_7 (0x0010U) /*!< GPIO P pin 4 to 7 */ +#define PWR_GPIO_P_PULLDOWN_PIN_8_11 (0x0100U) /*!< GPIO P pin 8 to 11 */ +#define PWR_GPIO_P_PULLDOWN_PIN_12_15 (0x1000U) /*!< GPIO P pin 12 to 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Macro PWREx Exported Macro + * @{ + */ + +/** + * @brief Enable the AVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Disable the AVD EXTI Line 16 + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Enable event on AVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Disable event on AVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Enable the AVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Disable the AVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Enable the AVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Disable the AVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \ +} while(0); + +/** + * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \ +} while(0); + +/** + * @brief Check whether the specified AVD EXTI interrupt flag is set or not. + * @retval EXTI AVD Line Status. + */ +#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) + +/** + * @brief Clear the AVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Generates a Software interrupt on AVD EXTI line. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + * @{ + */ +/* Power supply control functions */ +HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource); +uint32_t HAL_PWREx_GetSupplyConfig(void); + +/* Power voltage scaling functions */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetVoltageRange(void); +HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetStopModeVoltageRange(void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions + * @{ + */ +/* Flash low power control functions */ +void HAL_PWREx_EnableFlashPowerDown(void); +void HAL_PWREx_DisableFlashPowerDown(void); + +/* Wakeup Pins control functions */ +void HAL_PWREx_EnableWakeUpPin(const PWREx_WakeupPinTypeDef *sPinParams); +void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin); +uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag); +HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag); + +/* Power Wakeup PIN IRQ Handler */ +void HAL_PWREx_WAKEUP_PIN_IRQHandler(void); +void HAL_PWREx_WKUP1_Callback(void); +void HAL_PWREx_WKUP2_Callback(void); +void HAL_PWREx_WKUP3_Callback(void); +void HAL_PWREx_WKUP4_Callback(void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals Control Functions + * @{ + */ +/* Backup regulator control functions */ +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void); +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); + +/* USB regulator control functions */ +void HAL_PWREx_EnableUSBReg(void); +void HAL_PWREx_DisableUSBReg(void); +HAL_StatusTypeDef HAL_PWREx_EnableUSBVoltageDetector(void); +HAL_StatusTypeDef HAL_PWREx_DisableUSBVoltageDetector(void); +void HAL_PWREx_EnableUSBHSregulator(void); +void HAL_PWREx_DisableUSBHSregulator(void); + +/* USB regulator control functions */ +void HAL_PWREx_EnableUCPDStandbyMode(void); +void HAL_PWREx_DisableUCPDStandbyMode(void); +void HAL_PWREx_EnableUCPDDeadBattery(void); +void HAL_PWREx_DisableUCPDDeadBattery(void); + +/* Battery control functions */ +void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue); +void HAL_PWREx_DisableBatteryCharging(void); + +/* Analog Booster functions */ +void HAL_PWREx_EnableAnalogBooster(void); +void HAL_PWREx_DisableAnalogBooster(void); + +/* XSPIM_P1 functions */ +void HAL_PWREx_EnableXSPIM1(void); +void HAL_PWREx_DisableXSPIM1(void); + +/* XSPIM_P2 functions */ +void HAL_PWREx_EnableXSPIM2(void); +void HAL_PWREx_DisableXSPIM2(void); + +/* PORT capacitor control functions */ +void HAL_PWREx_ConfigXSPIPortCap(uint32_t PortCapacitor, uint32_t PortCapacitorSetting); +uint32_t HAL_PWREx_GetConfigXSPIPortCap(uint32_t PortCapacitor); + +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions + * @{ + */ +/* Power VBAT/Temperature monitoring functions */ +void HAL_PWREx_EnableMonitoring(void); +void HAL_PWREx_DisableMonitoring(void); +uint32_t HAL_PWREx_GetTemperatureLevel(void); +uint32_t HAL_PWREx_GetVBATLevel(void); + +/* Power AVD configuration functions */ +void HAL_PWREx_ConfigAVD(const PWREx_AVDTypeDef *sConfigAVD); +void HAL_PWREx_EnableAVD(void); +void HAL_PWREx_DisableAVD(void); + +/* Power PVD/AVD IRQ Handler */ +void HAL_PWREx_PVD_AVD_IRQHandler(void); +void HAL_PWREx_PVD_AVD_Callback(void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions + * @{ + */ +/* GPIO Pull-up Pull-down configuration functions */ +void HAL_PWREx_EnablePullUpPullDownConfig(void); +void HAL_PWREx_DisablePullUpPullDownConfig(void); + +/* GPIO Pull control functions */ +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin); +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin); +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin); +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Macros PWREx Private Macros + * @{ + */ + +/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters + * @{ + */ +/* Check PWR regulator configuration parameter */ +#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) ||\ + ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) + +/* Check PWR regulator configuration in STOP mode parameter */ +#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_STOP_VOLTAGE_SCALE3) ||\ + ((VOLTAGE) == PWR_REGULATOR_STOP_VOLTAGE_SCALE5)) + +/* Check wake up pin polarity parameter */ +#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\ + ((POLARITY) == PWR_PIN_POLARITY_LOW)) + +/* Check wake up pin pull configuration parameter */ +#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\ + ((PULL) == PWR_PIN_PULL_UP) ||\ + ((PULL) == PWR_PIN_PULL_DOWN)) + +/* Check wake up flag parameter */ +#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ + ((FLAG) == PWR_WAKEUP_FLAG2) ||\ + ((FLAG) == PWR_WAKEUP_FLAG3) ||\ + ((FLAG) == PWR_WAKEUP_FLAG4) ||\ + ((FLAG) == PWR_WAKEUP_FLAG_ALL)) + +/* Check wake up flag parameter */ +#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_1) ||\ + ((LEVEL) == PWR_AVDLEVEL_2) ||\ + ((LEVEL) == PWR_AVDLEVEL_3) ||\ + ((LEVEL) == PWR_AVDLEVEL_4)) + +/* Check AVD mode parameter */ +#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING) ||\ + ((MODE) == PWR_AVD_MODE_IT_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_NORMAL) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING)) + +/* Check resistor battery parameter */ +#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ + ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) + +/* Check the capacitor port parameter */ +#define IS_PWR_CAPACITOR(PORT) (((PORT) == PWR_CAPACITOR_PORT1) || \ + ((PORT) == PWR_CAPACITOR_PORT2)) + +/* Check the capacitor port setting parameter */ +#define IS_PWR_CAPACITOR_SETTING(SETTING) (((SETTING) == PWR_CAPACITOR_OFF) || \ + ((SETTING) == PWR_CAPACITOR_ONE_THIRD_CAPACITANCE) || \ + ((SETTING) == PWR_CAPACITOR_TWO_THIRD_CAPACITANCE) || \ + ((SETTING) == PWR_CAPACITOR_FULL_CAPACITANCE)) + +/* Check GPIO Pull-Up Port parameter */ +#define IS_PWR_GPIO_PULLPUP_PORT(GPIO_PORT) (((GPIO_PORT) == PWR_GPIO_PULLUP_PORT_N) ||\ + ((GPIO_PORT) == PWR_GPIO_PULLUP_PORT_O)) + +/* Check GPIO Pull-Down Port parameter */ +#define IS_PWR_GPIO_PULLDOWN_PORT(GPIO_PORT) (((GPIO_PORT) == PWR_GPIO_PULLDOWN_PORT_N) ||\ + ((GPIO_PORT) == PWR_GPIO_PULLDOWN_PORT_O) ||\ + ((GPIO_PORT) == PWR_GPIO_PULLDOWN_PORT_P)) + +/* GPIO pin mask check macro */ +#define IS_PWR_GPIO_PIN_MASK(BIT_MASK) ((((BIT_MASK) & GPIO_PIN_MASK) != 0U) && ((BIT_MASK) <= GPIO_PIN_MASK)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32H7RSxx_HAL_PWR_EX_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_ramecc.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_ramecc.h new file mode 100644 index 00000000000..8d8ab844288 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_ramecc.h @@ -0,0 +1,394 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_ramecc.h + * @author MCD Application Team + * @brief Header file of RAMECC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_RAMECC_H +#define STM32H7RSxx_HAL_RAMECC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup RAMECC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RAMECC_Exported_Types RAMECC Exported Types + * @brief RAMECC Exported Types + * @{ + */ + +/** + * @brief HAL RAMECC State structures definition + */ +typedef enum +{ + HAL_RAMECC_STATE_RESET = 0x00U, /*!< RAMECC not yet initialized or disabled */ + HAL_RAMECC_STATE_READY = 0x01U, /*!< RAMECC initialized and ready for use */ + HAL_RAMECC_STATE_BUSY = 0x02U, /*!< RAMECC process is ongoing */ + HAL_RAMECC_STATE_ERROR = 0x03U, /*!< RAMECC error state */ +} HAL_RAMECC_StateTypeDef; + +#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL RAMECC Callbacks IDs Enumeration Definition + */ +typedef enum +{ + HAL_RAMECC_MSPINIT_CB_ID = 0x00U, /*!< RAMECC MSP Init Callback ID */ + HAL_RAMECC_MSPDEINIT_CB_ID = 0x01U, /*!< RAMECC MSP DeInit Callback ID */ + HAL_RAMECC_SE_DETECT_CB_ID = 0x02U, /*!< RAMECC Single Error Detect Callback ID */ + HAL_RAMECC_DE_DETECT_CB_ID = 0x03U, /*!< RAMECC Double Error Detect Callback ID */ + HAL_RAMECC_ALL_CB_ID = 0x04U, /*!< RAMECC All callback ID */ +} HAL_RAMECC_CallbackIDTypeDef; +#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */ + +/** + * @brief RAMECC handle Structure definition + */ + +#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1) +typedef struct __RAMECC_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_RAMECC_REGISTER_CALLBACKS) */ +{ + RAMECC_MonitorTypeDef *Instance; /*!< Register base address */ + __IO HAL_RAMECC_StateTypeDef State; /*!< RAMECC state */ + __IO uint32_t ErrorCode; /*!< RAMECC Error Code */ +#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1) + void (* MspInitCallback)(struct __RAMECC_HandleTypeDef *hramecc); /*!< RAMECC MSP Init Callback */ + void (* MspDeInitCallback)(struct __RAMECC_HandleTypeDef *hramecc); /*!< RAMECC MSP DeInit Callback */ + void (* DetectSingleErrorCallback)(struct __RAMECC_HandleTypeDef *hramecc); /*!< RAMECC Single Error Detect Callback */ + void (* DetectDoubleErrorCallback)(struct __RAMECC_HandleTypeDef *hramecc); /*!< RAMECC Double Error Detect Callback */ +#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */ +} RAMECC_HandleTypeDef; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RAMECC_Error_Codes RAMECC Error Codes + * @{ + */ +#define HAL_RAMECC_ERROR_NONE 0x00000000U /*!< RAMECC No Error */ +#define HAL_RAMECC_ERROR_TIMEOUT 0x00000001U /*!< RAMECC Timeout Error */ +#define HAL_RAMECC_ERROR_BUSY 0x00000002U /*!< RAMECC Busy Error */ +#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1) +#define HAL_RAMECC_ERROR_INVALID_CALLBACK 0x00000003U /*!< Invalid Callback error */ +#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup RAMECC_Interrupt RAMECC interrupts + * @{ + */ +#define RAMECC_IT_GLOBAL_ID 0x10000000UL +#define RAMECC_IT_MONITOR_ID 0x20000000UL + +#define RAMECC_IT_GLOBAL_ALL_ENABLE (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GIE) +#define RAMECC_IT_GLOBAL_SINGLEERR_R (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCSEIE) +#define RAMECC_IT_GLOBAL_DOUBLEERR_R (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCDEIE) +#define RAMECC_IT_GLOBAL_DOUBLEERR_W (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCDEBWIE) + +#define RAMECC_IT_MONITOR_SINGLEERR_R (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCSEIE) +#define RAMECC_IT_MONITOR_DOUBLEERR_R (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEIE) +#define RAMECC_IT_MONITOR_DOUBLEERR_W (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEBWIE) +#define RAMECC_IT_MONITOR_ALL (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEBWIE | RAMECC_CR_ECCDEIE | RAMECC_CR_ECCSEIE) +/** + * @} + */ + +/** @defgroup RAMECC_FLAG RAMECC Monitor flags + * @{ + */ +#define RAMECC_FLAG_SINGLEERR_R RAMECC_SR_SEDCF +#define RAMECC_FLAG_DOUBLEERR_R RAMECC_SR_DEDF +#define RAMECC_FLAG_DOUBLEERR_W RAMECC_SR_DEBWDF +#define RAMECC_FLAGS_ALL (RAMECC_SR_SEDCF | RAMECC_SR_DEDF | RAMECC_SR_DEBWDF) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RAMECC_Exported_Macros RAMECC Exported Macros + * @{ + */ + +#define __HAL_RAMECC_ENABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) |= ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) +#define __HAL_RAMECC_ENABLE_MONITOR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= ((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID)) + +/** + * @brief Enable the specified RAMECC interrupts. + * @param __HANDLE__ : RAMECC handle. + * @param __INTERRUPT__: specifies the RAMECC interrupt sources to be enabled. + * This parameter can be one of the following values: + * @arg RAMECC_IT_GLOBAL_ALL_ENABLE : All Global ECC interrupts enable. + * @arg RAMECC_IT_GLOBAL_SINGLEERR_R : Global ECC single error interrupt enable. + * @arg RAMECC_IT_GLOBAL_DOUBLEERR_R : Global ECC double error interrupt enable. + * @arg RAMECC_IT_GLOBAL_DOUBLEERR_W : Global ECC double error on byte write (BW) interrupt enable. + * @arg RAMECC_IT_MONITOR_SINGLEERR_R : Monitor ECC single error interrupt enable. + * @arg RAMECC_IT_MONITOR_DOUBLEERR_R : Monitor ECC double error interrupt enable. + * @arg RAMECC_IT_MONITOR_DOUBLEERR_W : Monitor ECC double error on byte write (BW) interrupt enable. + * @arg RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable. + * @retval None + */ +#define __HAL_RAMECC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ( \ +(IS_RAMECC_GLOBAL_INTERRUPT(__INTERRUPT__)) ? (__HAL_RAMECC_ENABLE_GLOBAL_IT((__HANDLE__), (__INTERRUPT__))) :\ +(__HAL_RAMECC_ENABLE_MONITOR_IT((__HANDLE__), (__INTERRUPT__)))) + + +#define __HAL_RAMECC_DISABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) &= ~((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) +#define __HAL_RAMECC_DISABLE_MONITOR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID)) + +/** + * @brief Disable the specified RAMECC interrupts. + * @param __HANDLE__ : RAMECC handle. + * @param __INTERRUPT__: specifies the RAMECC interrupt sources to be disabled. + * This parameter can be one of the following values: + * @arg RAMECC_IT_GLOBAL_ALL_ENABLE : All Global ECC interrupts disable. + * @arg RAMECC_IT_GLOBAL_SINGLEERR_R : Global ECC single error interrupt disable. + * @arg RAMECC_IT_GLOBAL_DOUBLEERR_R : Global ECC double error interrupt disable. + * @arg RAMECC_IT_GLOBAL_DOUBLEERR_W : Global ECC double error on byte write (BW) interrupt disable. + * @arg RAMECC_IT_MONITOR_SINGLEERR_R : Monitor ECC single error interrupt disable. + * @arg RAMECC_IT_MONITOR_DOUBLEERR_R : Monitor ECC double error interrupt disable. + * @arg RAMECC_IT_MONITOR_DOUBLEERR_W : Monitor ECC double error on byte write (BW) interrupt disable. + * @arg RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts disable. + * @retval None + */ +#define __HAL_RAMECC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ( \ +(IS_RAMECC_GLOBAL_INTERRUPT(__INTERRUPT__)) ? (__HAL_RAMECC_DISABLE_GLOBAL_IT((__HANDLE__), (__INTERRUPT__))) :\ +(__HAL_RAMECC_DISABLE_MONITOR_IT((__HANDLE__), (__INTERRUPT__)))) + + +#define __HAL_RAMECC_GET_GLOBAL_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) & ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) ? SET : RESET) +#define __HAL_RAMECC_GET_MONITOR_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR) & ((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID)) ? SET : RESET) + +/** + * @brief Check whether the specified RAMECC interrupt source is enabled or not. + * @param __HANDLE__ : Specifies the RAMECC Handle. + * @param __INTERRUPT__ : Specifies the RAMECC interrupt source to check. + * This parameter can be one of the following values: + * @arg RAMECC_IT_GLOBAL_ALL_ENABLE : All Global ECC interrupts enable. + * @arg RAMECC_IT_GLOBAL_SINGLEERR_R : Global ECC single error interrupt enable. + * @arg RAMECC_IT_GLOBAL_DOUBLEERR_R : Global ECC double error interrupt enable. + * @arg RAMECC_IT_GLOBAL_DOUBLEERR_W : Global ECC double error on byte write (BW) interrupt enable. + * @arg RAMECC_IT_MONITOR_SINGLEERR_R : Monitor ECC single error interrupt enable. + * @arg RAMECC_IT_MONITOR_DOUBLEERR_R : Monitor ECC double error interrupt enable. + * @arg RAMECC_IT_MONITOR_DOUBLEERR_W : Monitor ECC double error on byte write (BW) interrupt enable. + * @arg RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable. + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RAMECC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ( \ +(IS_RAMECC_GLOBAL_INTERRUPT(__INTERRUPT__)) ? (__HAL_RAMECC_GET_GLOBAL_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\ +(__HAL_RAMECC_GET_MONITOR_IT_SOURCE((__HANDLE__), (__INTERRUPT__)))) + + +/** + * @brief Get the RAMECC pending flags. + * @param __HANDLE__ : RAMECC handle. + * @param __FLAG__ : specifies the flag to get. + * This parameter can be any combination of the following values: + * @arg RAMECC_FLAG_SINGLEERR_R : RAMECC instance ECC single error detected and corrected flag. + * @arg RAMECC_FLAG_DOUBLEERR_R : RAMECC instance ECC double error detected flag. + * @arg RAMECC_FLAG_DOUBLEERR_W : RAMECC instance ECC double error on byte write (BW) detected flag. + * @arg RAMECC_FLAGS_ALL : RAMECC instance all flag. + * @retval The state of __FLAG__ (SET or RESET). + */ +#define __HAL_RAMECC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR & (__FLAG__)) != 0U) ? 1UL : 0UL) + +/** + * @brief Clear the RAMECC pending flags. + * @param __HANDLE__ : RAMECC handle. + * @param __FLAG__ : specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg RAMECC_FLAG_SINGLEERR_R : RAMECC instance ECC single error detected and corrected flag. + * @arg RAMECC_FLAG_DOUBLEERR_R : RAMECC instance ECC double error detected flag. + * @arg RAMECC_FLAG_DOUBLEERR_W : RAMECC instance ECC double error on byte write (BW) detected flag. + * @arg RAMECC_FLAGS_ALL : RAMECC instance all flag. + * @retval None. + */ +#define __HAL_RAMECC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__)) + +/** + * @brief Reset the RAMECC handle state. + * @param __HANDLE__ : Specifies the RAMECC Handle. + * @retval None. + */ +#define __HAL_RAMECC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RAMECC_STATE_RESET) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RAMECC_Exported_Functions RAMECC Exported Functions + * @brief RAMECC Exported functions + * @{ + */ + +/** @defgroup RAMECC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_RAMECC_Init(RAMECC_HandleTypeDef *hramecc); +HAL_StatusTypeDef HAL_RAMECC_DeInit(RAMECC_HandleTypeDef *hramecc); +void HAL_RAMECC_MspInit(RAMECC_HandleTypeDef *hramecc); +void HAL_RAMECC_MspDeInit(RAMECC_HandleTypeDef *hramecc); +/** + * @} + */ + +/** @defgroup RAMECC_Exported_Functions_Group2 Monitoring operation functions + * @brief Monitoring operation functions + * @{ + */ +HAL_StatusTypeDef HAL_RAMECC_StartMonitor(RAMECC_HandleTypeDef *hramecc); +HAL_StatusTypeDef HAL_RAMECC_StopMonitor(RAMECC_HandleTypeDef *hramecc); +HAL_StatusTypeDef HAL_RAMECC_EnableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications); +HAL_StatusTypeDef HAL_RAMECC_DisableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications); +/** + * @} + */ + +/** @defgroup RAMCECC_Exported_Functions_Group3 Handle Interrupt and Callbacks functions + * @brief Handle Interrupt and Callbacks functions + * @{ + */ +void HAL_RAMECC_IRQHandler(RAMECC_HandleTypeDef *hramecc); +void HAL_RAMECC_DetectSingleErrorCallback(RAMECC_HandleTypeDef *hramecc); +void HAL_RAMECC_DetectDoubleErrorCallback(RAMECC_HandleTypeDef *hramecc); +#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RAMECC_RegisterCallback(RAMECC_HandleTypeDef *hramecc, + HAL_RAMECC_CallbackIDTypeDef CallbackID, + void (* pCallback)(RAMECC_HandleTypeDef *_hramecc)); + +HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback(RAMECC_HandleTypeDef *hramecc, + HAL_RAMECC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */ + + +/** + * @} + */ + +/** @defgroup RAMECC_Exported_Functions_Group4 Error information functions + * @brief Error information functions + * @{ + */ +uint32_t HAL_RAMECC_GetFailingAddress(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetFailingDataLow(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetFailingDataHigh(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetHammingErrorCode(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_IsECCSingleErrorDetected(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(const RAMECC_HandleTypeDef *hramecc); +/** + * @} + */ + +/** @defgroup RAMECC_Exported_Functions_Group5 State and Error functions + * @brief State and Error functions + * @{ + */ +HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetError(const RAMECC_HandleTypeDef *hramecc); +/** + * @} + */ + +/** + * @} + */ +/* Private Constants -------------------------------------------------------------*/ +/** @defgroup RAMECC_Private_Constants RAMECC Private Constants + * @brief RAMECC private defines and constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RAMECC_Private_Macros RAMECC Private Macros + * @brief RAMECC private macros + * @{ + */ + +#define IS_RAMECC_GLOBAL_INTERRUPT(INTERRUPT) (((INTERRUPT) == RAMECC_IT_GLOBAL_ALL_ENABLE) || \ + ((INTERRUPT) == RAMECC_IT_GLOBAL_SINGLEERR_R) || \ + ((INTERRUPT) == RAMECC_IT_GLOBAL_DOUBLEERR_R) || \ + ((INTERRUPT) == RAMECC_IT_GLOBAL_DOUBLEERR_W)) + + +#define IS_RAMECC_MONITOR_INTERRUPT(INTERRUPT) (((INTERRUPT) == RAMECC_IT_MONITOR_SINGLEERR_R) || \ + ((INTERRUPT) == RAMECC_IT_MONITOR_DOUBLEERR_R) || \ + ((INTERRUPT) == RAMECC_IT_MONITOR_DOUBLEERR_W) || \ + ((INTERRUPT) == RAMECC_IT_MONITOR_ALL)) + +#define IS_RAMECC_INTERRUPT(INTERRUPT) ((IS_RAMECC_GLOBAL_INTERRUPT(INTERRUPT)) || \ + (IS_RAMECC_MONITOR_INTERRUPT(INTERRUPT))) + +/** + * @} + */ + +/** @defgroup RAMECC_FLAG RAMECC Monitor flags + * @{ + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RAMECC_Private_Functions RAMECC Private Functions + * @brief RAMECC private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_RAMECC_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rcc.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rcc.h new file mode 100644 index 00000000000..65858d372bb --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rcc.h @@ -0,0 +1,4814 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_RCC_H +#define STM32H7RSxx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" +#include "stm32h7rsxx_ll_rcc.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ + + uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 8 and Max_Data = 420 */ + + uint32_t PLLP; /*!< Division factor for system clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 + Odd division factors (except for 1) are not allowed */ + + uint32_t PLLQ; /*!< Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLLR; /*!< Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLLS; /*!< Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ + + uint32_t PLLT; /*!< Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ + + uint32_t PLLFractional; /*!< Fractional Part of the Multiplication Factor for PLL VCO. + This parameter must be a number between 0 and 8191 */ + +} RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSIDiv; /*!< The division factor of the HSI. + This parameter can be a value of @ref RCC_HSI_Divider */ + + uint32_t HSICalibrationValue; /*!< The calibration trimming value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + uint32_t HSI48State; /*!< The new state of the HSI48. + This parameter can be a value of @ref RCC_HSI48_Config */ + + uint32_t CSIState; /*!< The new state of the CSI. + This parameter can be a value of @ref RCC_CSI_Config */ + + RCC_PLLInitTypeDef PLL1; /*!< Main PLL1 structure parameters */ + + RCC_PLLInitTypeDef PLL2; /*!< PLL2 structure parameters */ + + RCC_PLLInitTypeDef PLL3; /*!< PLL3 structure parameters */ + +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t SYSCLKDivider; /*!< The system clock divider for CPU clock and all bus matrix clocks. + This parameter can be a value of @ref RCC_System_Clock_Divider */ + + uint32_t AHBCLKDivider; /*!< The AHB/AXI clock divider for HCLK. + This clock is derived from the system clock divided by the system clock divider. + This parameter can be a value of @ref RCC_HCLK_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock divider for PCLK1. + This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock divider for PCLK2. + This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB2_Clock_Source */ + + uint32_t APB4CLKDivider; /*!< The APB4 clock divider for PCLK4. + This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB4_Clock_Source */ + + uint32_t APB5CLKDivider; /*!< The APB5 clock divider for PCLK5. + This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB5_Clock_Source */ + +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ +#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE selected */ +#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI selected */ +#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE selected */ +#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI selected */ +#define RCC_OSCILLATORTYPE_CSI 0x00000010U /*!< CSI selected */ +#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 selected */ +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF 0U /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< HSE bypass analog clock activation */ +#define RCC_HSE_BYPASS_DIGITAL (RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< HSE bypass digital clock activation */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< LSE bypass analog clock activation */ +#define RCC_LSE_BYPASS_DIGITAL (RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< LSE bypass digital clock activation */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF 0U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation with divider 1 = 64MHz */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Calibration_Default HSI Calibration default + * @{ + */ +#define RCC_HSICALIBRATION_DEFAULT 0x40U /*!< Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Divider HSI Divider + * @{ + */ +#define RCC_HSI_DIV1 0U /*!< HSI clock activation with divider 1 = 64MHz */ +#define RCC_HSI_DIV2 RCC_CR_HSIDIV_0 /*!< HSI clock activation with divider 2 = 32MHz */ +#define RCC_HSI_DIV4 RCC_CR_HSIDIV_1 /*!< HSI clock activation with divider 4 = 16MHz */ +#define RCC_HSI_DIV8 RCC_CR_HSIDIV /*!< HSI clock activation with divider 8 = 8MHz */ +/** + * @} + */ + +/** @defgroup RCC_HSI48_Config HSI48 Config + * @{ + */ +#define RCC_HSI48_OFF 0U /*!< HSI48 clock deactivation */ +#define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF 0U /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ +/** + * @} + */ + +/** @defgroup RCC_CSI_Config CSI Config + * @{ + */ +#define RCC_CSI_OFF 0U /*!< CSI clock deactivation */ +#define RCC_CSI_ON RCC_CR_CSION /*!< CSI clock activation */ +/** + * @} + */ + +/** @defgroup RCC_CSI_Calibration_Default CSI Calibration default + * @{ + */ +#define RCC_CSICALIBRATION_DEFAULT 0x20U /*!< Default CSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE 0U /*!< PLL configuration unchanged */ +#define RCC_PLL_OFF 1U /*!< PLL deactivation */ +#define RCC_PLL_ON 2U /*!< PLL activation */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_HSI 0U /*!< HSI clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_0 /*!< CSI clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_1 /*!< HSE clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_NONE RCC_PLLCKSELR_PLLSRC /*!< No clock selected as PLL entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Output PLL Clock Output + * @{ + */ +#define RCC_PLL_PCLK RCC_PLLCFGR_PLL1PEN /*!< PLL DIVP divider output enable */ +#define RCC_PLL_QCLK RCC_PLLCFGR_PLL1QEN /*!< PLL DIVQ divider output enable */ +#define RCC_PLL_RCLK RCC_PLLCFGR_PLL1REN /*!< PLL DIVR divider output enable */ +#define RCC_PLL_SCLK RCC_PLLCFGR_PLL1SEN /*!< PLL DIVS divider output enable */ +#define RCC_PLL_TCLK 0x00000200U /*!< PLL DIVT divider output enable, hardcoded because no definition in CMSIS */ +/** + * @} + */ + +/** @defgroup RCC_PLL_VCI_Range PLL VCI Range + * @{ + */ +#define RCC_PLL_VCOINPUT_RANGE0 0U /*!< Clock range frequency for PLL between 1 and 2 MHz (reset) */ +#define RCC_PLL_VCOINPUT_RANGE1 RCC_PLLCFGR_PLL1RGE_0 /*!< Clock range frequency for PLL between 2 and 4 MHz */ +#define RCC_PLL_VCOINPUT_RANGE2 RCC_PLLCFGR_PLL1RGE_1 /*!< Clock range frequency for PLL between 4 and 8 MHz */ +#define RCC_PLL_VCOINPUT_RANGE3 RCC_PLLCFGR_PLL1RGE /*!< Clock range frequency for PLL between 8 and 16 MHz */ +/** + * @} + */ + +/** @defgroup RCC_PLL_VCO_Range PLL VCO Range + * @{ + */ +#define RCC_PLL_VCO_HIGH 0U /*!< Wide PLL VCO output range between 400 and 1600 MHz (reset) */ +#define RCC_PLL_VCO_LOW RCC_PLLCFGR_PLL1VCOSEL /*!< Low PLL VCO output range between 150 and 420 MHz */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ +#define RCC_CLOCKTYPE_PCLK4 0x00000010U /*!< PCLK4 to configure */ +#define RCC_CLOCKTYPE_PCLK5 0x00000020U /*!< PCLK5 to configure */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI 0U /*!< HSI selection as system clock */ +#define RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_0 /*!< CSI selection as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< PLL1 selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI 0U /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR_SWS_0 /*!< CSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< PLL1 used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Divider System Clock Divider + * @{ + */ +#define RCC_SYSCLK_DIV1 0U /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CDCFGR_CPRE_3 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_0) /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_1) /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_1 | RCC_CDCFGR_CPRE_0) /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV64 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_2) /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_2 | RCC_CDCFGR_CPRE_0) /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_2 | RCC_CDCFGR_CPRE_1) /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_2 | RCC_CDCFGR_CPRE_1 | RCC_CDCFGR_CPRE_0) /*!< SYSCLK divided by 512 */ +/** + * @} + */ + + +/** @defgroup RCC_HCLK_Clock_Source HCLK Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 0U /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_BMCFGR_BMPRE_3 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_0) /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_1) /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_1 | RCC_BMCFGR_BMPRE_0) /*!< HCLK divided by 16 */ +#define RCC_HCLK_DIV64 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_2) /*!< HCLK divided by 64 */ +#define RCC_HCLK_DIV128 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_2 | RCC_BMCFGR_BMPRE_0) /*!< HCLK divided by 128 */ +#define RCC_HCLK_DIV256 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_2 | RCC_BMCFGR_BMPRE_1) /*!< HCLK divided by 256 */ +#define RCC_HCLK_DIV512 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_2 | RCC_BMCFGR_BMPRE_1 | RCC_BMCFGR_BMPRE_0) /*!< HCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Source APB1 Clock Source + * @{ + */ +#define RCC_APB1_DIV1 0U /*!< APB1 not divided */ +#define RCC_APB1_DIV2 RCC_APBCFGR_PPRE1_2 /*!< APB1 divided by 2 */ +#define RCC_APB1_DIV4 (RCC_APBCFGR_PPRE1_2 | RCC_APBCFGR_PPRE1_0) /*!< APB1 divided by 4 */ +#define RCC_APB1_DIV8 (RCC_APBCFGR_PPRE1_2 | RCC_APBCFGR_PPRE1_1) /*!< APB1 divided by 8 */ +#define RCC_APB1_DIV16 RCC_APBCFGR_PPRE1 /*!< APB1 divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Source APB2 Clock Source + * @{ + */ +#define RCC_APB2_DIV1 0U /*!< APB2 not divided */ +#define RCC_APB2_DIV2 RCC_APBCFGR_PPRE2_2 /*!< APB2 divided by 2 */ +#define RCC_APB2_DIV4 (RCC_APBCFGR_PPRE2_2 | RCC_APBCFGR_PPRE2_0) /*!< APB2 divided by 4 */ +#define RCC_APB2_DIV8 (RCC_APBCFGR_PPRE2_2 | RCC_APBCFGR_PPRE2_1) /*!< APB2 divided by 8 */ +#define RCC_APB2_DIV16 RCC_APBCFGR_PPRE2 /*!< APB2 divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_APB4_Clock_Source APB4 Clock Source + * @{ + */ +#define RCC_APB4_DIV1 0U /*!< APB4 not divided */ +#define RCC_APB4_DIV2 RCC_APBCFGR_PPRE4_2 /*!< APB4 divided by 2 */ +#define RCC_APB4_DIV4 (RCC_APBCFGR_PPRE4_2 | RCC_APBCFGR_PPRE4_0) /*!< APB4 divided by 4 */ +#define RCC_APB4_DIV8 (RCC_APBCFGR_PPRE4_2 | RCC_APBCFGR_PPRE4_1) /*!< APB4 divided by 8 */ +#define RCC_APB4_DIV16 RCC_APBCFGR_PPRE4 /*!< APB4 divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_APB5_Clock_Source APB5 Clock Source + * @{ + */ +#define RCC_APB5_DIV1 0U /*!< APB5 not divided */ +#define RCC_APB5_DIV2 RCC_APBCFGR_PPRE5_2 /*!< APB5 divided by 2 */ +#define RCC_APB5_DIV4 (RCC_APBCFGR_PPRE5_2 | RCC_APBCFGR_PPRE5_0) /*!< APB5 divided by 4 */ +#define RCC_APB5_DIV8 (RCC_APBCFGR_PPRE5_2 | RCC_APBCFGR_PPRE5_1) /*!< APB5 divided by 8 */ +#define RCC_APB5_DIV16 RCC_APBCFGR_PPRE5 /*!< APB5 divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_DISABLE 0U /*!< RTC clock is disabled */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV2 ((0x02U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 2 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV3 ((0x03U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 3 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV4 ((0x04U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 4 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV5 ((0x05U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 5 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV6 ((0x06U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 6 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV7 ((0x07U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 7 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV8 ((0x08U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 8 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV9 ((0x09U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 9 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV10 ((0x0AU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 10 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV11 ((0x0BU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 11 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV12 ((0x0CU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 12 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV13 ((0x0DU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 13 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV14 ((0x0EU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 14 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV15 ((0x0FU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 15 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV16 ((0x10U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 16 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV17 ((0x11U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 17 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV18 ((0x12U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 18 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV19 ((0x13U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 19 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV20 ((0x14U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 20 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV21 ((0x15U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 21 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV22 ((0x16U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 22 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV23 ((0x17U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 23 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV24 ((0x18U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 24 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV25 ((0x19U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 25 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV26 ((0x1AU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 26 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV27 ((0x1BU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 27 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV28 ((0x1CU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 28 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV29 ((0x1DU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 29 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV30 ((0x1EU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 30 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV31 ((0x1FU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 31 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 ((0x20U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 32 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV33 ((0x21U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 33 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV34 ((0x22U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 34 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV35 ((0x23U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 35 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV36 ((0x24U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 36 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV37 ((0x25U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 37 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV38 ((0x26U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 38 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV39 ((0x27U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 39 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV40 ((0x28U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 40 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV41 ((0x29U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 41 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV42 ((0x2AU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 42 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV43 ((0x2BU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 43 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV44 ((0x2CU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 44 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV45 ((0x2DU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 45 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV46 ((0x2EU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 46 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV47 ((0x2FU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 47 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV48 ((0x30U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 48 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV49 ((0x31U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 49 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV50 ((0x32U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 50 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV51 ((0x33U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 51 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV52 ((0x34U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 52 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV53 ((0x35U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 53 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV54 ((0x36U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 54 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV55 ((0x37U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 55 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV56 ((0x38U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 56 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV57 ((0x39U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 57 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV58 ((0x3AU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 58 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV59 ((0x3BU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 59 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV60 ((0x3CU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 60 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV61 ((0x3DU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 61 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV62 ((0x3EU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 62 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV63 ((0x3FU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 63 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_MCOx_Index MCOx Index + * @{ + */ + +/* @cond */ +/* 32 28 20 16 0 + -------------------------------- + | MCO | GPIO | GPIO | GPIO | + | Index | AF | Port | Pin | + -------------------------------*/ + +#define RCC_MCO_GPIOPORT_POS 16U +#define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) +#define RCC_MCO_GPIOAF_POS 20U +#define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) +#define RCC_MCO_INDEX_POS 28U +#define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) + +#define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ +#define RCC_MCO2_INDEX (0x1UL << RCC_MCO_INDEX_POS) /*!< MCO2 index */ +/* @endcond */ + +#define RCC_MCO1_PA8 (RCC_MCO1_INDEX |\ + (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) +#define RCC_MCO1 RCC_MCO1_PA8 /*!< Alias for compatibility */ + +#define RCC_MCO2_PC9 (RCC_MCO2_INDEX |\ + (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOC) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_9) +#define RCC_MCO2 RCC_MCO2_PC9 /*!< Alias for compatibility */ + +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 1 MCO*/ +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_HSI 0U /*!< HSI clock selected as MCO1 source (reset) */ +#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1SEL_0 /*!< LSE clock selected as MCO1 source */ +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1SEL_1 /*!< HSE clock selected as MCO1 source */ +#define RCC_MCO1SOURCE_PLL1Q (RCC_CFGR_MCO1SEL_1 | RCC_CFGR_MCO1SEL_0) /*!< PLL1Q clock selected as MCO1 source */ +#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1SEL_2 /*!< HSI48 clock selected as MCO1 source */ +/** + * @} + */ + +/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_SYSCLK 0U /*!< System clock selected as MCO2 source (reset) */ +#define RCC_MCO2SOURCE_PLL2P RCC_CFGR_MCO2SEL_0 /*!< PLL2P clock selected as MCO2 source */ +#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_1 /*!< HSE clock selected as MCO2 source */ +#define RCC_MCO2SOURCE_PLL1P (RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< PLL1P clock selected as MCO2 source */ +#define RCC_MCO2SOURCE_CSI RCC_CFGR_MCO2SEL_2 /*!< CSI clock selected as MCO2 source */ +#define RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_0) /*!< LSI clock selected as MCO2 source */ +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler + * @{ + */ +#define RCC_MCODIV_NONE 0U /*!< No MCO prescaler (reset) */ +#define RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0 /*!< MCO divided by 1 */ +#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1 /*!< MCO divided by 2 */ +#define RCC_MCODIV_3 (RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 3 */ +#define RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2 /*!< MCO divided by 4 */ +#define RCC_MCODIV_5 (RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 5 */ +#define RCC_MCODIV_6 (RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_1) /*!< MCO divided by 6 */ +#define RCC_MCODIV_7 (RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 7 */ +#define RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3 /*!< MCO divided by 8 */ +#define RCC_MCODIV_9 (RCC_CFGR_MCO1PRE_3 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 9 */ +#define RCC_MCODIV_10 (RCC_CFGR_MCO1PRE_3 | RCC_CFGR_MCO1PRE_1) /*!< MCO divided by 10 */ +#define RCC_MCODIV_11 (RCC_CFGR_MCO1PRE_3 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 11 */ +#define RCC_MCODIV_12 (RCC_CFGR_MCO1PRE_3 | RCC_CFGR_MCO1PRE_2) /*!< MCO divided by 12 */ +#define RCC_MCODIV_13 (RCC_CFGR_MCO1PRE_3 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 13 */ +#define RCC_MCODIV_14 (RCC_CFGR_MCO1PRE_3 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_1) /*!< MCO divided by 14 */ +#define RCC_MCODIV_15 RCC_CFGR_MCO1PRE /*!< MCO divided by 15 */ +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupt + * @{ + */ +#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt */ +#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt */ +#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt */ +#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt */ +#define RCC_IT_CSIRDY RCC_CIFR_CSIRDYF /*!< CSI Ready Interrupt */ +#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt */ +#define RCC_IT_PLL1RDY RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt */ +#define RCC_IT_PLL2RDY RCC_CIFR_PLL2RDYF /*!< PLL2 Ready Interrupt */ +#define RCC_IT_PLL3RDY RCC_CIFR_PLL3RDYF /*!< PLL3 Ready Interrupt */ +#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt */ +#define RCC_IT_HSECSS RCC_CIFR_HSECSSF /*!< HSE Clock Security System Interrupt (flag only) */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flag + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: BDCR register + * - 011: CSR register + * - 100: RSR register + * @{ + */ +#define RCC_FLAG_HSIRDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ +#define RCC_FLAG_HSIDIV ((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSIDIVF_Pos) /*!< HSIDIV Ready flag */ +#define RCC_FLAG_CSIRDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_CSIRDY_Pos) /*!< CSI Ready flag */ +#define RCC_FLAG_HSI48RDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ +#define RCC_FLAG_HSERDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ +#define RCC_FLAG_PLL1RDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_PLL1RDY_Pos) /*!< PLL1 Ready flag */ +#define RCC_FLAG_PLL2RDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos) /*!< PLL2 Ready flag */ +#define RCC_FLAG_PLL3RDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos) /*!< PLL3 Ready flag */ + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((RCC_BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ +#define RCC_FLAG_LSECSSD ((RCC_BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System failure detection flag */ + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((RCC_CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ + +/* Flags in the RSR register */ +#define RCC_FLAG_BORRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_BORRSTF_Pos) /*!< BOR reset flag */ +#define RCC_FLAG_PINRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_PINRSTF_Pos) /*!< PIN reset flag */ +#define RCC_FLAG_PORRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_PORRSTF_Pos) /*!< Power-on reset flag */ +#define RCC_FLAG_SFTRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_SFTRSTF_Pos) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LSEDrive_Config LSE Drive Config + * @{ + */ +#define RCC_LSEDRIVE_LOW 0U /*!< LSE low drive capability */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ +/** + * @} + */ + +/** @defgroup RCC_Reset_Flag Reset Flag + * @{ + */ +#define RCC_RESET_FLAG_OBL RCC_RSR_OBLRSTF /*!< Option Byte Loader reset flag */ +#define RCC_RESET_FLAG_PIN RCC_RSR_PINRSTF /*!< PIN reset flag */ +#define RCC_RESET_FLAG_PWR RCC_RSR_BORRSTF /*!< BOR or POR/PDR reset flag */ +#define RCC_RESET_FLAG_SW RCC_RSR_SFTRSTF /*!< Software Reset flag */ +#define RCC_RESET_FLAG_IWDG RCC_RSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define RCC_RESET_FLAG_WWDG RCC_RSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define RCC_RESET_FLAG_LPWR RCC_RSR_LPWRRSTF /*!< Low power reset flag */ +#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ + RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ + RCC_RESET_FLAG_LPWR) +/** + * @} + */ + +/** @defgroup RCC_Stop_WakeUpClock Stop WakeUp Clock + * @{ + */ +#define RCC_STOP_WAKEUPCLOCK_HSI 0U /*!< HSI selected as wake up system clock from system Stop (default after reset) */ +#define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK /*!< CSI selected as wake up system clock from system Stop */ +/** + * @} + */ + +/** @defgroup RCC_Stop_KernelWakeUpClock Stop Kernel WakeUp Clock + * @{ + */ +#define RCC_STOP_KERWAKEUPCLOCK_HSI 0U /*!< HSI selected as wake up kernel clock from system Stop (default after reset) */ +#define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK /*!< CSI selected as wake up kernel clock from system Stop */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AXI_Clock_Gating_Enable_Disable AXI Interconnect, Master and Slave Clock Gating Enable Disable + * @brief Enable or disable the clock gating. + * @note The dynamic power consumption can be optimized by enabling the functional clock gating. + * After reset, the clock gating is enabled (except for JTAG if a JTAG connection has been detected). + * @{ + */ + +#define __HAL_RCC_AXI_INTERCONNECT_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXICKG) + +#define __HAL_RCC_AXI_MASTER_AHB_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AHBCKG) + +#define __HAL_RCC_AXI_MASTER_SDMMC1_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_SDMMCCKG) + +#define __HAL_RCC_AXI_MASTER_HPDMA1_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_HPDMA1CKG) + +#define __HAL_RCC_AXI_MASTER_CPU_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_CPUCKG) + +#define __HAL_RCC_AXI_MASTER_GPU2D_0_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2DS0CKG) + +#define __HAL_RCC_AXI_MASTER_GPU2D_1_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2DS1CKG) + +#define __HAL_RCC_AXI_MASTER_GPU2D_CACHE_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2DCKG) + +#define __HAL_RCC_AXI_MASTER_DCMIPP_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_DCMIPPCKG) + +#define __HAL_RCC_AXI_MASTER_DMA2D_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_DMA2DCKG) + +#define __HAL_RCC_AXI_MASTER_LTDC_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_LTDCCKG) + +#define __HAL_RCC_AXI_MASTER_GFXMMU_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GFXMMUMCKG) + +#define __HAL_RCC_AXI_SLAVE_GFXMMU_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GFXMMUSCKG) + +#define __HAL_RCC_AXI_SLAVE_AHB_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AHBSCKG) + +#define __HAL_RCC_AXI_SLAVE_FMC_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_FMCCKG) + +#define __HAL_RCC_AXI_SLAVE_XSPI1_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_XSPI1CKG) + +#define __HAL_RCC_AXI_SLAVE_XSPI2_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_XSPI2CKG) + +#define __HAL_RCC_AXI_SLAVE_SRAM0_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM0CKG) + +#define __HAL_RCC_AXI_SLAVE_SRAM1_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM1CKG) + +#define __HAL_RCC_AXI_SLAVE_SRAM2_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM2CKG) + +#define __HAL_RCC_AXI_SLAVE_SRAM3_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM3CKG) + +#define __HAL_RCC_AXI_SLAVE_FLASH_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_FLIFTCKG) + +#define __HAL_RCC_AXI_SLAVE_EXTI_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_EXTICKG) + +#define __HAL_RCC_AXI_SLAVE_JTAG_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_JTAGCKG) + + +#define __HAL_RCC_AXI_INTERCONNECT_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXICKG) + +#define __HAL_RCC_AXI_MASTER_AHB_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AHBCKG) + +#define __HAL_RCC_AXI_MASTER_SDMMC1_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_SDMMCCKG) + +#define __HAL_RCC_AXI_MASTER_HPDMA1_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_HPDMA1CKG) + +#define __HAL_RCC_AXI_MASTER_CPU_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_CPUCKG) + +#define __HAL_RCC_AXI_MASTER_GPU_0_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2DS0CKG) + +#define __HAL_RCC_AXI_MASTER_GPU_1_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2DS1CKG) + +#define __HAL_RCC_AXI_MASTER_GPU_CACHE_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2DCKG) + +#define __HAL_RCC_AXI_MASTER_DCMIPP_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_DCMIPPCKG) + +#define __HAL_RCC_AXI_MASTER_DMA2D_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_DMA2DCKG) + +#define __HAL_RCC_AXI_MASTER_LTDC_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_LTDCCKG) + +#define __HAL_RCC_AXI_MASTER_GFXMMU_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GFXMMUMCKG) + +#define __HAL_RCC_AXI_SLAVE_GFXMMU_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GFXMMUSCKG) + +#define __HAL_RCC_AXI_SLAVE_AHB_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AHBSCKG) + +#define __HAL_RCC_AXI_SLAVE_FMC_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_FMCCKG) + +#define __HAL_RCC_AXI_SLAVE_XSPI1_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_XSPI1CKG) + +#define __HAL_RCC_AXI_SLAVE_XSPI2_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_XSPI2CKG) + +#define __HAL_RCC_AXI_SLAVE_SRAM0_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM0CKG) + +#define __HAL_RCC_AXI_SLAVE_SRAM1_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM1CKG) + +#define __HAL_RCC_AXI_SLAVE_SRAM2_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM2CKG) + +#define __HAL_RCC_AXI_SLAVE_SRAM3_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM3CKG) + +#define __HAL_RCC_AXI_SLAVE_FLASH_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_FLIFTCKG) + +#define __HAL_RCC_AXI_SLAVE_EXTI_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_EXTICKG) + +#define __HAL_RCC_AXI_SLAVE_JTAG_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_JTAGCKG) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB1ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB1ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB1ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETH1TX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB1ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETH1RX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB1ENR);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* ETH */ + +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB1ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGFSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB1ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USBPHYC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USBPHYCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB1ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ADF1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADF1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB1ENR);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) + +#define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN) + +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN) + +#define __HAL_RCC_ETH1TX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN) + +#define __HAL_RCC_ETH1RX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN) +#endif /* ETH */ + +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGFSEN) + +#define __HAL_RCC_USBPHYC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USBPHYCEN) + +#define __HAL_RCC_ADF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADF1EN) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_PSSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PSSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PSSIEN) + +#define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) + +#define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN) + +#define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM1EN) + +#define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB3ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB3ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB3ENR);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* CRYP */ + +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SAESEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB3ENR);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* SAES */ + +#if defined(PKA) +#define __HAL_RCC_PKA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PKAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB3ENR);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* PKA */ + +#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_RNGEN) + +#define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_HASHEN) + +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_CRYPEN) +#endif /* CRYP */ + +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SAESEN) +#endif /* SAES */ + +#if defined(PKA) +#define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PKAEN) +#endif /* PKA */ + +/** + * @} + */ + +/** @defgroup RCC_AHB4_Peripheral_Clock_Enable_Disable AHB4 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPION_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIONEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN) + +#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN) + +#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN) + +#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN) + +#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN) + +#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN) + +#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN) + +#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN) + +#define __HAL_RCC_GPIOM_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOMEN) + +#define __HAL_RCC_GPION_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIONEN) + +#define __HAL_RCC_GPIOO_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOOEN) + +#define __HAL_RCC_GPIOP_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOPEN) + +#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN) + +#define __HAL_RCC_BKPRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB5_Peripheral_Clock_Enable_Disable AHB5 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB5 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_HPDMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_HPDMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB5ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB5ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_JPEGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB5ENR);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* JPEG */ + +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB5ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_XSPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB5ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_SDMMC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB5ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_XSPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB5ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_XSPIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPIMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB5ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GFXMMUEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB5ENR);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GPU2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->AHB5ENR);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPU2D */ + +#define __HAL_RCC_HPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_HPDMA1EN) + +#define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_DMA2DEN) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_JPEGEN) +#endif /* JPEG */ + +#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_FMCEN) + +#define __HAL_RCC_XSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI1EN) + +#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_SDMMC1EN) + +#define __HAL_RCC_XSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI2EN) + +#define __HAL_RCC_XSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPIMEN) + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GFXMMUEN) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GPU2DEN) +#endif /* GPU2D */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I3C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_CRSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_MDIOS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_MDIOSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCANEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB1ENR1);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) + +#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) + +#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) + +#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) + +#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) + +#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) + +#define __HAL_RCC_TIM12_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM12EN) + +#define __HAL_RCC_TIM13_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM13EN) + +#define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM14EN) + +#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) + +#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) + +#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) + +#define __HAL_RCC_SPDIFRX_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPDIFRXEN) + +#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) + +#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) + +#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) + +#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) + +#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN) + +#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) + +#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) + +#define __HAL_RCC_I3C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN) + +#define __HAL_RCC_CEC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CECEN) + +#define __HAL_RCC_UART7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART7EN) + +#define __HAL_RCC_UART8_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART8EN) + +#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_CRSEN) + +#define __HAL_RCC_MDIOS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_MDIOSEN) + +#define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCANEN) + +#define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB2ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) + +#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) + +#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) + +#define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) + +#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) + +#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) + +#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) + +#define __HAL_RCC_TIM9_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN) + +#define __HAL_RCC_SPI5_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN) + +#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) + +#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) + +/** + * @} + */ + +/** @defgroup RCC_APB4_Peripheral_Clock_Enable_Disable APB4 Peripheral Clock Enable Disable + * @brief Enable or disable the APB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_SBS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SBSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_VREF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DTS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB4ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SBS_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_SBSEN) + +#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN) + +#define __HAL_RCC_SPI6_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN) + +#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN) + +#define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN) + +#define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN) + +#define __HAL_RCC_LPTIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN) + +#define __HAL_RCC_VREF_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN) + +#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN) + +#define __HAL_RCC_DTS_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN) + +/** + * @} + */ + +/** @defgroup RCC_APB5_Peripheral_Clock_Enable_Disable APB5 Peripheral Clock Enable Disable + * @brief Enable or disable the APB5 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB5ENR, RCC_APB5ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB5ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DCMIPP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB5ENR, RCC_APB5ENR_DCMIPPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB5ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GFXTIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB5ENR, RCC_APB5ENR_GFXTIMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_REG(RCC->APB5ENR);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB5ENR, RCC_APB5ENR_LTDCEN) + +#define __HAL_RCC_DCMIPP_CLK_DISABLE() CLEAR_BIT(RCC->APB5ENR, RCC_APB5ENR_DCMIPPEN) + +#define __HAL_RCC_GFXTIM_CLK_DISABLE() CLEAR_BIT(RCC->APB5ENR, RCC_APB5ENR_GFXTIMEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) + +#define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN) != 0U) + +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN) != 0U) + +#define __HAL_RCC_ETH1TX_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN) != 0U) + +#define __HAL_RCC_ETH1RX_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN) != 0U) +#endif /* ETH */ + +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN) != 0U) + +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGFSEN) != 0U) + +#define __HAL_RCC_USBPHYC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USBPHYCEN) != 0U) + +#define __HAL_RCC_ADF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADF1EN) != 0U) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PSSIEN) != 0U) + +#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) != 0U) + +#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN) != 0U) + +#define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM1EN) != 0U) + +#define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) != 0U) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB3 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_RNGEN) != 0U) + +#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_HASHEN) != 0U) + +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_CRYPEN) != 0U) +#endif /* CRYP */ + +#if defined(SAES) +#define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SAESEN) != 0U) +#endif /* SAES */ + +#if defined(PKA) +#define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PKAEN) != 0U) +#endif /* PKA */ + +/** + * @} + */ + +/** @defgroup RCC_AHB4_Clock_Enable_Disable_Status AHB4 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB4 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN) != 0U) + +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN) != 0U) + +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN) != 0U) + +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN) != 0U) + +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN) != 0U) + +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN) != 0U) + +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN) != 0U) + +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN) != 0U) + +#define __HAL_RCC_GPIOM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOMEN) != 0U) + +#define __HAL_RCC_GPION_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIONEN) != 0U) + +#define __HAL_RCC_GPIOO_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOOEN) != 0U) + +#define __HAL_RCC_GPIOP_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOPEN) != 0U) + +#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN) != 0U) + +#define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN) != 0U) + +/** + * @} + */ + +/** @defgroup RCC_AHB5_Clock_Enable_Disable_Status AHB5 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB5 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_HPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_HPDMA1EN) != 0U) + +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_DMA2DEN) != 0U) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_JPEGEN) != 0U) +#endif /* JPEG */ + +#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_FMCEN) != 0U) + +#define __HAL_RCC_XSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI1EN) != 0U) + +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_SDMMC1EN) != 0U) + +#define __HAL_RCC_XSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI2EN) != 0U) + +#define __HAL_RCC_XSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPIMEN) != 0U) + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GFXMMUEN) != 0U) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GPU2DEN) != 0U) +#endif /* GPU2D */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) + +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) + +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) + +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) + +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) + +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) + +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM12EN) != 0U) + +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM13EN) != 0U) + +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM14EN) != 0U) + +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U) + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) + +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) + +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U) + +#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPDIFRXEN) != 0U) + +#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) + +#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) + +#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) + +#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) + +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN) != 0U) + +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) + +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U) + +#define __HAL_RCC_I3C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN) != 0U) + +#define __HAL_RCC_CEC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CECEN) != 0U) + +#define __HAL_RCC_UART7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART7EN) != 0U) + +#define __HAL_RCC_UART8_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART8EN) != 0U) + +#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_CRSEN) != 0U) + +#define __HAL_RCC_MDIOS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_MDIOSEN) != 0U) + +#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCANEN) != 0U) + +#define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) + +#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) + +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) + +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U) + +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) + +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) + +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) + +#define __HAL_RCC_TIM9_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN) != 0U) + +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN) != 0U) + +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) + +#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) + +/** + * @} + */ + +/** @defgroup RCC_APB4_Clock_Enable_Disable_Status APB4 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB4 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_SBS_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SBSEN) != 0U) + +#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN) != 0U) + +#define __HAL_RCC_SPI6_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN) != 0U) + +#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN) != 0U) + +#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN) != 0U) + +#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN) != 0U) + +#define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN) != 0U) + +#define __HAL_RCC_VREF_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN) != 0U) + +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN) != 0U) + +#define __HAL_RCC_DTS_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN) != 0U) + +/** + * @} + */ + +/** @defgroup RCC_APB5_Clock_Enable_Disable_Status APB5 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB5 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB5ENR, RCC_APB5ENR_LTDCEN) != 0U) + +#define __HAL_RCC_DCMIPP_IS_CLK_ENABLED() (READ_BIT(RCC->APB5ENR, RCC_APB5ENR_DCMIPPEN) != 0U) + +#define __HAL_RCC_GFXTIM_IS_CLK_ENABLED() (READ_BIT(RCC->APB5ENR, RCC_APB5ENR_GFXTIMEN) != 0U) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ + +#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x8E008030UL) +#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0UL) + +#define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) +#define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) + +#define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ADC12RST) +#define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ADC12RST) + +#if defined(ETH) +#define __HAL_RCC_ETH1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETH1RST) +#define __HAL_RCC_ETH1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETH1RST) +#endif /* ETH */ + +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_OTGHSRST) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_OTGHSRST) + +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_OTGFSRST) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_OTGFSRST) + +#define __HAL_RCC_USBPHYC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_USBPHYCRST) +#define __HAL_RCC_USBPHYC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_USBPHYCRST) + +#define __HAL_RCC_ADF1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ADF1RST) +#define __HAL_RCC_ADF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ADF1RST) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ + +#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00004202UL) +#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0UL) + +#define __HAL_RCC_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PSSIRST) +#define __HAL_RCC_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PSSIRST) + +#define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC2RST) +#define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC2RST) + +#define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_CORDICRST) +#define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_CORDICRST) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ + +#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000057UL) +#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0UL) + +#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_RNGRST) +#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_RNGRST) + +#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_HASHRST) +#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_HASHRST) + +#if defined(CRYP) +#define __HAL_RCC_CRYP_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_CRYPRST) +#define __HAL_RCC_CRYP_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_CRYPRST) +#endif /* CRYP */ + +#if defined(SAES) +#define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_SAESRST) +#define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_SAESRST) +#endif /* SAES */ + +#if defined(PKA) +#define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_PKARST) +#define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_PKARST) +#endif /* PKA */ + +/** + * @} + */ + +/** @defgroup RCC_AHB4_Force_Release_Reset AHB4 Peripheral Force Release Reset + * @brief Force or release AHB4 peripheral reset. + * @{ + */ + +#define __HAL_RCC_AHB4_FORCE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x0008B0FFUL) +#define __HAL_RCC_AHB4_RELEASE_RESET() WRITE_REG(RCC->AHB4RSTR, 0UL) + +#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOARST) +#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOARST) + +#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOBRST) +#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOBRST) + +#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOCRST) +#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOCRST) + +#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIODRST) +#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIODRST) + +#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOERST) +#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOERST) + +#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOFRST) +#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOFRST) + +#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOGRST) +#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOGRST) + +#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOHRST) +#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOHRST) + +#define __HAL_RCC_GPIOM_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOMRST) +#define __HAL_RCC_GPIOM_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOMRST) + +#define __HAL_RCC_GPION_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIONRST) +#define __HAL_RCC_GPION_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIONRST) + +#define __HAL_RCC_GPIOO_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOORST) +#define __HAL_RCC_GPIOO_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOORST) + +#define __HAL_RCC_GPIOP_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOPRST) +#define __HAL_RCC_GPIOP_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOPRST) + +#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_CRCRST) +#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_CRCRST) + +/** + * @} + */ + +/** @defgroup RCC_AHB5_Force_Release_Reset AHB5 Peripheral Force Release Reset + * @brief Force or release AHB5 peripheral reset. + * @{ + */ + +#define __HAL_RCC_AHB5_FORCE_RESET() WRITE_REG(RCC->AHB5RSTR, 0x0018513BUL) +#define __HAL_RCC_AHB5_RELEASE_RESET() WRITE_REG(RCC->AHB5RSTR, 0UL) + +#define __HAL_RCC_HPDMA1_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_HPDMA1RST) +#define __HAL_RCC_HPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_HPDMA1RST) + +#define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_DMA2DRST) +#define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_DMA2DRST) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_JPEGRST) +#define __HAL_RCC_JPEG_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_JPEGRST) +#endif /* JPEG */ + +#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_FMCRST) +#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_FMCRST) + +#define __HAL_RCC_XSPI1_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI1RST) +#define __HAL_RCC_XSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI1RST) + +#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_SDMMC1RST) +#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_SDMMC1RST) + +#define __HAL_RCC_XSPI2_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI2RST) +#define __HAL_RCC_XSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI2RST) + +#define __HAL_RCC_XSPIM_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPIMRST) +#define __HAL_RCC_XSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPIMRST) + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GFXMMURST) +#define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GFXMMURST) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GPU2DRST) +#define __HAL_RCC_GPU2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GPU2DRST) +#endif /* GPU2D */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ + +#define __HAL_RCC_APB1_FORCE_RESET() do { \ + WRITE_REG(RCC->APB1RSTR1, 0xC8FFC3FFUL); \ + WRITE_REG(RCC->APB1RSTR2, 0x08000122UL); \ + } while(0) +#define __HAL_RCC_APB1_RELEASE_RESET() do { \ + WRITE_REG(RCC->APB1RSTR1, 0UL); \ + WRITE_REG(RCC->APB1RSTR2, 0UL); \ + } while(0) + +#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) +#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) + +#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) +#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) + +#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) +#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) + +#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) +#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) + +#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) +#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) + +#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) +#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) + +#define __HAL_RCC_TIM12_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM12RST) +#define __HAL_RCC_TIM12_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM12RST) + +#define __HAL_RCC_TIM13_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM13RST) +#define __HAL_RCC_TIM13_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM13RST) + +#define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM14RST) +#define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM14RST) + +#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) + +#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) +#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) + +#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) +#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) + +#define __HAL_RCC_SPDIFRX_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPDIFRXRST) +#define __HAL_RCC_SPDIFRX_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPDIFRXRST) + +#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) +#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) + +#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) +#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) + +#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) +#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) + +#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) +#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) + +#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1_I3C1RST) +#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1_I3C1RST) + +#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) +#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) + +#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) +#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) + +#define __HAL_RCC_I3C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1_I3C1RST) +#define __HAL_RCC_I3C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1_I3C1RST) + +#define __HAL_RCC_CEC_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CECRST) +#define __HAL_RCC_CEC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CECRST) + +#define __HAL_RCC_UART7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART7RST) +#define __HAL_RCC_UART7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART7RST) + +#define __HAL_RCC_UART8_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART8RST) +#define __HAL_RCC_UART8_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART8RST) + +#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_CRSRST) +#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_CRSRST) + +#define __HAL_RCC_MDIOS_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_MDIOSRST) +#define __HAL_RCC_MDIOS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_MDIOSRST) + +#define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCANRST) +#define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCANRST) + +#define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) +#define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ + +#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xC8FFC3FFUL) +#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0UL) + +#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) +#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) + +#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) +#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) + +#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) +#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) + +#define __HAL_RCC_SPI4_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) +#define __HAL_RCC_SPI4_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) + +#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) +#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) + +#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) +#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) + +#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) +#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) + +#define __HAL_RCC_TIM9_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM9RST) +#define __HAL_RCC_TIM9_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM9RST) + +#define __HAL_RCC_SPI5_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI5RST) +#define __HAL_RCC_SPI5_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI5RST) + +#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) +#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) + +#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) +#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) + +/** + * @} + */ + +/** @defgroup RCC_APB4_Force_Release_Reset APB4 Peripheral Force Release Reset + * @brief Force or release APB4 peripheral reset. + * @{ + */ + +#define __HAL_RCC_APB4_FORCE_RESET() WRITE_REG(RCC->APB4RSTR, 0x04009E2AUL) +#define __HAL_RCC_APB4_RELEASE_RESET() WRITE_REG(RCC->APB4RSTR, 0UL) + +#define __HAL_RCC_SBS_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_SBSRST) +#define __HAL_RCC_SBS_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_SBSRST) + +#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPUART1RST) +#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPUART1RST) + +#define __HAL_RCC_SPI6_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_SPI6RST) +#define __HAL_RCC_SPI6_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_SPI6RST) + +#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM2RST) +#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM2RST) + +#define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM3RST) +#define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM3RST) + +#define __HAL_RCC_LPTIM4_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM4RST) +#define __HAL_RCC_LPTIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM4RST) + +#define __HAL_RCC_LPTIM5_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM5RST) +#define __HAL_RCC_LPTIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM5RST) + +#define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_VREFRST) +#define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_VREFRST) + +#define __HAL_RCC_DTS_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_DTSRST) +#define __HAL_RCC_DTS_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_DTSRST) + +/** + * @} + */ + +/** @defgroup RCC_APB5_Force_Release_Reset APB5 Peripheral Force Release Reset + * @brief Force or release APB5 peripheral reset. + * @{ + */ + +#define __HAL_RCC_APB5_FORCE_RESET() WRITE_REG(RCC->APB5RSTR, 0x00000016UL) +#define __HAL_RCC_APB5_RELEASE_RESET() WRITE_REG(RCC->APB5RSTR, 0UL) + +#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB5RSTR, RCC_APB5RSTR_LTDCRST) +#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB5RSTR, RCC_APB5RSTR_LTDCRST) + +#define __HAL_RCC_DCMIPP_FORCE_RESET() SET_BIT(RCC->APB5RSTR, RCC_APB5RSTR_DCMIPPRST) +#define __HAL_RCC_DCMIPP_RELEASE_RESET() CLEAR_BIT(RCC->APB5RSTR, RCC_APB5RSTR_DCMIPPRST) + +#define __HAL_RCC_GFXTIM_FORCE_RESET() SET_BIT(RCC->APB5RSTR, RCC_APB5RSTR_GFXTIMRST) +#define __HAL_RCC_GFXTIM_RELEASE_RESET() CLEAR_BIT(RCC->APB5RSTR, RCC_APB5RSTR_GFXTIMRST) + +/** + * @} + */ + + +/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN) + +#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADC12LPEN) +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1MACLPEN) + +#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1TXLPEN) + +#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1RXLPEN) +#endif /* ETH */ + +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGHSLPEN) + +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGFSLPEN) + +#define __HAL_RCC_USBPHYC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_USBPHYCLPEN) + +#define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADF1LPEN) + + +#define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN) + +#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADC12LPEN) + +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1MACLPEN) + +#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1TXLPEN) + +#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1RXLPEN) +#endif /* ETH */ + +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGHSLPEN) + +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGFSLPEN) + +#define __HAL_RCC_USBPHYC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_USBPHYCLPEN) + +#define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADF1LPEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PSSILPEN) + +#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SDMMC2LPEN) + +#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_CORDICLPEN) + +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM1LPEN) + +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN) + + +#define __HAL_RCC_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PSSILPEN) + +#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SDMMC2LPEN) + +#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_CORDICLPEN) + +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM1LPEN) + +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_RNGLPEN) + +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_HASHLPEN) + +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_CRYPLPEN) +#endif /* CRYP */ + +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_SAESLPEN) +#endif /* SAES */ + +#if defined(PKA) +#define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_PKALPEN) +#endif /* PKA */ + + +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_RNGLPEN) + +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_HASHLPEN) + +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_CRYPLPEN) +#endif /* CRYP */ + +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_SAESLPEN) +#endif /* SAES */ + +#if defined(PKA) +#define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_PKALPEN) +#endif /* PKA */ + +/** + * @} + */ + +/** @defgroup RCC_AHB4_Clock_Sleep_Enable_Disable AHB4 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOALPEN) + +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOBLPEN) + +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOCLPEN) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIODLPEN) + +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOELPEN) + +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOFLPEN) + +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOGLPEN) + +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOHLPEN) + +#define __HAL_RCC_GPIOM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOMLPEN) + +#define __HAL_RCC_GPION_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIONLPEN) + +#define __HAL_RCC_GPIOO_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOOLPEN) + +#define __HAL_RCC_GPIOP_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOPLPEN) + +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_CRCLPEN) + +#define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_BKPRAMLPEN) + + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOALPEN) + +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOBLPEN) + +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOCLPEN) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIODLPEN) + +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOELPEN) + +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOFLPEN) + +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOGLPEN) + +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOHLPEN) + +#define __HAL_RCC_GPIOM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOMLPEN) + +#define __HAL_RCC_GPION_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIONLPEN) + +#define __HAL_RCC_GPIOO_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOOLPEN) + +#define __HAL_RCC_GPIOP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOPLPEN) + +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_CRCLPEN) + +#define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_BKPRAMLPEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB5_Clock_Sleep_Enable_Disable AHB5 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_HPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_HPDMA1LPEN) + +#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DMA2DLPEN) + +#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FLASHLPEN) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_JPEGLPEN) +#endif /* JPEG */ + +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FMCLPEN) + +#define __HAL_RCC_XSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI1LPEN) + +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_SDMMC1LPEN) + +#define __HAL_RCC_XSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI2LPEN) + +#define __HAL_RCC_XSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPIMLPEN) + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GFXMMULPEN) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GPU2DLPEN) +#endif /* GPU2D */ + +#define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM1LPEN) + +#define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM2LPEN) + +#define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_ITCMLPEN) + +#define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_AXISRAMLPEN) + + +#define __HAL_RCC_HPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_HPDMA1LPEN) + +#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DMA2DLPEN) + +#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FLASHLPEN) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_JPEGLPEN) +#endif /* JPEG */ + +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FMCLPEN) + +#define __HAL_RCC_XSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI1LPEN) + +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_SDMMC1LPEN) + +#define __HAL_RCC_XSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI2LPEN) + +#define __HAL_RCC_XSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPIMLPEN) + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GFXMMULPEN) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GPU2DLPEN) +#endif /* GPU2D */ + +#define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM1LPEN) + +#define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM2LPEN) + +#define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_ITCMLPEN) + +#define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_AXISRAMLPEN) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM2LPEN) + +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM3LPEN) + +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM4LPEN) + +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM5LPEN) + +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM6LPEN) + +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM7LPEN) + +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM12LPEN) + +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM13LPEN) + +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM14LPEN) + +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_LPTIM1LPEN) + +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_WWDGLPEN) + +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI2LPEN) + +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI3LPEN) + +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPDIFRXLPEN) + +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART2LPEN) + +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART3LPEN) + +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART4LPEN) + +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART5LPEN) + +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPEN) + +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C2LPEN) + +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C3LPEN) + +#define __HAL_RCC_I3C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPEN) + +#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_CECLPEN) + +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART7LPEN) + +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART8LPEN) + +#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_CRSLPEN) + +#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_MDIOSLPEN) + +#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_FDCANLPEN) + +#define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_UCPD1LPEN) + + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM2LPEN) + +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM3LPEN) + +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM4LPEN) + +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM5LPEN) + +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM6LPEN) + +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM7LPEN) + +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM12LPEN) + +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM13LPEN) + +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM14LPEN) + +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_LPTIM1LPEN) + +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_WWDGLPEN) + +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI2LPEN) + +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI3LPEN) + +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPDIFRXLPEN) + +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART2LPEN) + +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART3LPEN) + +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART4LPEN) + +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART5LPEN) + +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPEN) + +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C2LPEN) + +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C3LPEN) + +#define __HAL_RCC_I3C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPEN) + +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_CECLPEN) + +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART7LPEN) + +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART8LPEN) + +#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_CRSLPEN) + +#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_MDIOSLPEN) + +#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_FDCANLPEN) + +#define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_UCPD1LPEN) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) + +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN) + +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN) + +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN) + +#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN) + +#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN) + +#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN) + +#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM9LPEN) + +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI5LPEN) + +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN) + +#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) + + +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) + +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN) + +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN) + +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN) + +#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN) + +#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN) + +#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN) + +#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM9LPEN) + +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI5LPEN) + +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN) + +#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) + +/** + * @} + */ + +/** @defgroup RCC_APB4_Clock_Sleep_Enable_Disable APB4 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_SBS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SBSLPEN) + +#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPUART1LPEN) + +#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SPI6LPEN) + +#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM2LPEN) + +#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM3LPEN) + +#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM4LPEN) + +#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM5LPEN) + +#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_VREFLPEN) + +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_RTCAPBLPEN) + +#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_DTSLPEN) + + +#define __HAL_RCC_SBS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SBSLPEN) + +#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPUART1LPEN) + +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SPI6LPEN) + +#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM2LPEN) + +#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM3LPEN) + +#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM4LPEN) + +#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM5LPEN) + +#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_VREFLPEN) + +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_RTCAPBLPEN) + +#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_DTSLPEN) + +/** + * @} + */ + +/** @defgroup RCC_APB5_Clock_Sleep_Enable_Disable APB5 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB5 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB5LPENR, RCC_APB5LPENR_LTDCLPEN) + +#define __HAL_RCC_DCMIPP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB5LPENR, RCC_APB5LPENR_DCMIPPLPEN) + +#define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB5LPENR, RCC_APB5LPENR_GFXTIMLPEN) + + +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB5LPENR, RCC_APB5LPENR_LTDCLPEN) + +#define __HAL_RCC_DCMIPP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB5LPENR, RCC_APB5LPENR_DCMIPPLPEN) + +#define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB5LPENR, RCC_APB5LPENR_GFXTIMLPEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_GPDMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN) != 0U) + +#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADC12LPEN) != 0U) +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1MACLPEN) != 0U) + +#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1TXLPEN) != 0U) + +#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1RXLPEN) != 0U) +#endif /* ETH */ + +#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGHSLPEN) != 0U) + +#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGFSLPEN) != 0U) + +#define __HAL_RCC_USBPHYC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_USBPHYCLPEN) != 0U) + +#define __HAL_RCC_ADF1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADF1LPEN) != 0U) +/** + * @} + */ + +/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_PSSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PSSILPEN) != 0U) + +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SDMMC2LPEN) != 0U) + +#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_CORDICLPEN) != 0U) + +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM1LPEN) != 0U) + +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN) != 0U) + +/** + * @} + */ + +/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_RNGLPEN) != 0U) + +#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_HASHLPEN) != 0U) + +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_CRYPLPEN) != 0U) +#endif /* CRYP */ + +#if defined(SAES) +#define __HAL_RCC_SAES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_SAESLPEN) != 0U) +#endif /* SAES */ + +#if defined(PKA) +#define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_PKALPEN) != 0U) +#endif /* PKA */ + +/** + * @} + */ + +/** @defgroup RCC_AHB4_Clock_Sleep_Enable_Disable_Status AHB4 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the AHB4 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOALPEN) != 0U) + +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOBLPEN) != 0U) + +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOCLPEN) != 0U) + +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIODLPEN) != 0U) + +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOELPEN) != 0U) + +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOFLPEN) != 0U) + +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOGLPEN) != 0U) + +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOHLPEN) != 0U) + +#define __HAL_RCC_GPIOM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOMLPEN) != 0U) + +#define __HAL_RCC_GPION_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIONLPEN) != 0U) + +#define __HAL_RCC_GPIOO_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOOLPEN) != 0U) + +#define __HAL_RCC_GPIOP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOPLPEN) != 0U) + +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_CRCLPEN) != 0U) + +#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_BKPRAMLPEN) != 0U) + +/** + * @} + */ + +/** @defgroup RCC_AHB5_Clock_Sleep_Enable_Disable_Status AHB5 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the AHB5 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_HPDMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_HPDMA1LPEN) != 0U) + +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DMA2DLPEN) != 0U) + +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FLASHLPEN) != 0U) + +#if defined(JPEG) +#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_JPEGLPEN) != 0U) +#endif /* JPEG */ + +#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FMCLPEN) != 0U) + +#define __HAL_RCC_XSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI1LPEN) != 0U) + +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_SDMMC1LPEN) != 0U) + +#define __HAL_RCC_XSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI2LPEN) != 0U) + +#define __HAL_RCC_XSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPIMLPEN) != 0U) + +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GFXMMULPEN) != 0U) +#endif /* GFXMMU */ + +#if defined(GPU2D) +#define __HAL_RCC_GPU2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GPU2DLPEN) != 0U) +#endif /* GPU2D */ + +#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM1LPEN) != 0U) + +#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM2LPEN) != 0U) + +#define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_ITCMLPEN) != 0U) + +#define __HAL_RCC_AXISRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_AXISRAMLPEN) != 0U) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM2LPEN) != 0U) + +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM3LPEN) != 0U) + +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM4LPEN) != 0U) + +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM5LPEN) != 0U) + +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM6LPEN) != 0U) + +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM7LPEN) != 0U) + +#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM12LPEN) != 0U) + +#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM13LPEN) != 0U) + +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM14LPEN) != 0U) + +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_LPTIM1LPEN) != 0U) + +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_WWDGLPEN) != 0U) + +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI2LPEN) != 0U) + +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI3LPEN) != 0U) + +#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPDIFRXLPEN) != 0U) + +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART2LPEN) != 0U) + +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART3LPEN) != 0U) + +#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART4LPEN) != 0U) + +#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART5LPEN) != 0U) + +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPEN) != 0U) + +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C2LPEN) != 0U) + +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C3LPEN) != 0U) + +#define __HAL_RCC_I3C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPEN) != 0U) + +#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_CECLPEN) != 0U) + +#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART7LPEN) != 0U) + +#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART8LPEN) != 0U) + +#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_CRSLPEN) != 0U) + +#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_MDIOSLPEN) != 0U) + +#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_FDCANLPEN) != 0U) + +#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_UCPD1LPEN) != 0U) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) != 0U) + +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN) != 0U) + +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN) != 0U) + +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN) != 0U) + +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN) != 0U) + +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN) != 0U) + +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN) != 0U) + +#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM9LPEN) != 0U) + +#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI5LPEN) != 0U) + +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN) != 0U) + +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) != 0U) + +/** + * @} + */ + +/** @defgroup RCC_APB4_Clock_Sleep_Enable_Disable_Status APB4 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the APB4 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_SBS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SBSLPEN) != 0U) + +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPUART1LPEN) != 0U) + +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SPI6LPEN) != 0U) + +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM2LPEN) != 0U) + +#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM3LPEN) != 0U) + +#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM4LPEN) != 0U) + +#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM5LPEN) != 0U) + +#define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_VREFLPEN) != 0U) + +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_RTCAPBLPEN) != 0U) + +#define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_DTSLPEN) != 0U) + +/** + * @} + */ + +/** @defgroup RCC_APB5_Clock_Sleep_Enable_Disable_Status APB5 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the APB5 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB5LPENR, RCC_APB5LPENR_LTDCLPEN) != 0U) + +#define __HAL_RCC_DCMIPP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB5LPENR, RCC_APB5LPENR_DCMIPPLPEN) != 0U) + +#define __HAL_RCC_GFXTIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB5LPENR, RCC_APB5LPENR_GFXTIMLPEN) != 0U) + +/** + * @} + */ + +/** @defgroup RCC_Osc_config Oscillators configuration + * @{ + */ + +/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI). + * @note After enabling the HSI, the application software should wait on + * HSIRDY and HSIDIVF flags to be set indicating that the HSI clock is + * stable and the divider ready and that HSI clock can be used to clock + * the PLL and/or system clock. + * @note HSI can not be stopped if it is used directly or through the PLL + * as system clock. In this case, you have to select another source + * of the system clock then stop the HSI. + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @param __STATE__ specifies the new state of the HSI. + * This parameter can be one of the following values: + * @arg @ref RCC_HSI_OFF turn OFF the HSI oscillator + * @arg @ref RCC_HSI_ON turn ON the HSI oscillator (divide it by 1 (default after reset)) + * @arg @ref RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2 + * @arg @ref RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4 + * @arg @ref RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8 + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_CONFIG(__STATE__) \ + MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__)) + +/** @brief Macro to get the HSI divider. + * @retval The HSI divider. The returned value can be one + * of the following: + * - RCC_CR_HSIDIV_1 HSI oscillator divided by 1 (default after reset) + * - RCC_CR_HSIDIV_2 HSI oscillator divided by 2 + * - RCC_CR_HSIDIV_4 HSI oscillator divided by 4 + * - RCC_CR_HSIDIV_8 HSI oscillator divided by 8 + */ +#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after start-up + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) + +#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) + +/** @brief Macro to adjust the Internal High Speed 64MHz oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x7F. + * @retval None + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_HSICFGR_HSITRIM_Pos); + +/** + * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) + * in STOP mode to be quickly available as kernel clock for some peripherals. + * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the HSI start-up time. + * @note The enable of this function has not effect on the HSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) + +#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) + +/** + * @brief Macros to enable or disable the Internal oscillator (CSI). + * @note The CSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after + * start-up from Reset, wakeup from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * @note CSI can not be stopped if it is used as system clock source. + * In this case, you have to select another source of the system + * clock then stop the CSI. + * @note After enabling the CSI, the application software should wait on + * CSIRDY flag to be set indicating that CSI clock is stable and can + * be used as system clock source. + * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator + * clock cycles. + */ +#define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION) + +#define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION) + +/** @brief Macro to adjust the Internal oscillator (CSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal CSI RC. + * @param __CSICALIBRATIONVALUE__ specifies the calibration trimming value + * (default is RCC_CSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x3F. + * @retval None + */ +#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICALIBRATIONVALUE__) \ + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICALIBRATIONVALUE__) << RCC_CSICFGR_CSITRIM_Pos); + +/** + * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI) + * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. + * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the CSI start-up time. + * @note The enable of this function has not effect on the CSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON) + +#define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON) + +/** + * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48). + * @note After enabling the HSI48, the application software should wait on + * HSI48RDY flag to be set indicating that HSI48 clock is stable and can + * be used to clock the USB. + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON); + +#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) + +#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) + +/** + * @brief Macro to configure the External High Speed oscillator (__HSE__). + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON turn ON the HSE oscillator. + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock (analog). + * @arg @ref RCC_HSE_BYPASS_DIGITAL HSE oscillator bypassed with external digital clock. + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + } \ + } while(0) + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * User should request a transition to LSE Off first and then LSE On or LSE Bypass. + * @note The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*). + A duty cycle close to 50% is recommended. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @note If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*) + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock (analog). + * @arg @ref RCC_LSE_BYPASS_DIGITAL LSE oscillator bypassed with external digital clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + } \ + } while(0) + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_config RCC_RTC_Clock_config + * @{ + */ + +/** @brief Macros to enable or disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it cannot be changed unless the + * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() and + * __HAL_RCC_BACKUPRESET_RELEASE() macros, or by a Power On Reset (POR). + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divide by 2 selected as RTC clock up to + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV63 for HSE divide by 63 + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) \ + ((((__RTC_CLKSOURCE__) & (0x3FU << 12U)) != 0U) ? \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTC_CLKSOURCE__) & (~RCC_BDCR_RTCSEL)) >> 4U)) : \ + CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)) + +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ + do { \ + __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \ + SET_BIT(RCC->BDCR, ((__RTC_CLKSOURCE__) & RCC_BDCR_RTCSEL)); \ + } while(0) + +#define __HAL_RCC_GET_RTC_SOURCE() \ + ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ + ((READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) << 4U) | RCC_BDCR_RTCSEL) : READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** @brief Macros to force or release the Vswitch backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + * @note The BKPSRAM is not affected by this reset. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST) + +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST) + +/** + * @} + */ + +/** @defgroup RCC_PLL_Clocks_config PLL Clocks configuration + * @{ + */ + +/** @brief Macro to configure the PLLs clock source. + * @note This function must be used only when all PLLs are disabled. + * @param __PLLSOURCE__ specifies the PLLs entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_CSI CSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_NONE No oscillator clock selected as PLL clock entry (consumption gain) + */ +#define __HAL_RCC_PLLSOURCE_CONFIG(__PLLSOURCE__) \ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__)) + +/** @brief Macro to get the oscillator used as PLL clock source. + * @retval The oscillator used as PLL clock source. + * The returned value can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_CSI CSI oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() \ + READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC) + +/** @brief Macros to enable or disable the PLL1. + * @note After enabling the main PLL, the application software should wait on + * PLL1RDY flag to be set indicating that PLL1 clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) + +#define __HAL_RCC_PLL1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) + +/** + * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK, PLL_S_CLK, PLL_T_CLK) + * @note PLL_P_CLK cannot be stopped if used as System Clock + * @param __PLL_CLOCKOUT__ specifies the PLL clock to be output + * This parameter can be one or a combination of the following values: + * @arg @ref RCC_PLL_PCLK This clock is used to generate system clock up to 500MHz + * @arg @ref RCC_PLL_QCLK This clock is used to generate peripherals clock up to 500MHz + * @arg @ref RCC_PLL_RCLK This clock is used to generate peripherals clock up to 500MHz + * @arg @ref RCC_PLL_SCLK This clock is used to generate peripherals clock up to 500MHz + * + * @retval None + */ +#define __HAL_RCC_PLL1CLKOUT_ENABLE(__PLL_CLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLL_CLOCKOUT__)) + +#define __HAL_RCC_PLL1CLKOUT_DISABLE(__PLL_CLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLL_CLOCKOUT__)) + +/** + * @brief Macro to get the PLL1 clock output enable status. + * @param __PLL_CLOCKOUT__ specifies the PLL1 clock to be output. + * This parameter can be one of the following values: + * @arg @ref RCC_PLL_PCLK This clock is used to generate system clock up to 500MHz + * @arg @ref RCC_PLL_QCLK This clock is used to generate peripherals clock up to 500MHz + * @arg @ref RCC_PLL_RCLK This clock is used to generate peripherals clock up to 500MHz + * @arg @ref RCC_PLL_SCLK This clock is used to generate peripherals clock up to 500MHz + * @retval SET / RESET + */ +#define __HAL_RCC_GET_PLL1CLKOUT_CONFIG(__PLL_CLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLL_CLOCKOUT__)) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 + * @retval None + */ +#define __HAL_RCC_PLL1_FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) + +#define __HAL_RCC_PLL1_FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) + +/** + * @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_CSI CSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_NONE No oscillator clock selected as PLL clock entry (consumption gain) + * @note This clock source is common for PLL1, PLL2 and PLL3. It cannot be + * change on any PLL if another PLL is already enabled. + * + * @param __PLL1M__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 16 MHz. + * + * @param __PLL1N__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between 8 and 420. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 150 and 420 MHz (when in medium VCO range) or + * between 128 and 560 MHZ (when in wide VCO range) + * + * @param __PLL1P__ specifies the division factor for system clock. + * This parameter must be a number between 1 and 128 (where odd numbers are not allowed) + * + * @param __PLL1Q__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @param __PLL1R__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @param __PLL1S__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 8 + * + * + * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ, + * DIVR, DIVS or DIVT) is not used, application shall clear the enable bit (PLL1yEN) + * and assign lowest possible value to __PLL1P__, __PLL1Q__, __PLL1R__, __PLL1S__ + * or __PLL1T__ parameters. + * @retval None + */ + +#define __HAL_RCC_PLL1_CONFIG(__PLLSOURCE__, __PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__, __PLL1S__) \ + do { \ + MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__PLLSOURCE__) | ( (__PLL1M__) << RCC_PLLCKSELR_DIVM1_Pos))); \ + WRITE_REG(RCC->PLL1DIVR1, ((((__PLL1N__) - 1U) & RCC_PLL1DIVR1_DIVN) | \ + ((((__PLL1P__) - 1U) << RCC_PLL1DIVR1_DIVP_Pos) & RCC_PLL1DIVR1_DIVP) | \ + ((((__PLL1Q__) - 1U) << RCC_PLL1DIVR1_DIVQ_Pos) & RCC_PLL1DIVR1_DIVQ) | \ + ((((__PLL1R__) - 1U) << RCC_PLL1DIVR1_DIVR_Pos) & RCC_PLL1DIVR1_DIVR))); \ + MODIFY_REG(RCC->PLL1DIVR2, RCC_PLL1DIVR2_DIVS, \ + (((__PLL1S__) - 1U) & RCC_PLL1DIVR2_DIVS)); \ + } while(0) + +/** + * @brief Macro to configures the PLL1 clock Fractional Part Of The Multiplication Factor + * + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO + * + * @param __PLL1FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL1 VCO. + * It should be a value between 0 and 8191 + * @note Warning: The software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 128 to 560 MHz if PLL1VCOSEL = 0 + * 150 to 420 MHz if PLL1VCOSEL = 1. + * + * @retval None + */ +#define __HAL_RCC_PLL1_FRACN_CONFIG(__PLL1FRACN__) \ + MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN, (uint32_t)(__PLL1FRACN__) << RCC_PLL1FRACR_FRACN_Pos) + +/** @brief Macro to select the PLL1 reference frequency range. + * @param __PLL_VCOINPUT_RANGE__ specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg @ref RCC_PLL_VCOINPUT_RANGE0 Range frequency is between 1 and 2 MHz + * @arg @ref RCC_PLL_VCOINPUT_RANGE1 Range frequency is between 2 and 4 MHz + * @arg @ref RCC_PLL_VCOINPUT_RANGE2 Range frequency is between 4 and 8 MHz + * @arg @ref RCC_PLL_VCOINPUT_RANGE3 Range frequency is between 8 and 16 MHz + * + * @retval None + */ +#define __HAL_RCC_PLL1_VCOINPUT_RANGE(__PLL_VCOINPUT_RANGE__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__PLL_VCOINPUT_RANGE__)) + +/** @brief Macro to select the PLL1 reference frequency range. + * @param __PLLVCORANGE__ specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg @ref RCC_PLL_VCO_HIGH Range frequency is between 128 to 560 MHz + * @arg @ref RCC_PLL_VCO_LOW Range frequency is between 150 and 420 MHz + * @retval None + */ +#define __HAL_RCC_PLL1_VCORANGE(__PLLVCORANGE__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__PLLVCORANGE__)) + +/** @brief Macros to enable or disable PLL2. + * @note After enabling PLL2, the application software should wait on + * PLL2RDY flag to be set indicating that PLL2 clock is stable and can + * be used as kernel clock source. + * @note PLL2 is disabled by hardware when entering Stop and Standby modes. + */ +#define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) +#define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) + +/** + * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK, PLL2_S_CLK, PLL2_T_CLK) + * @param __PLL_CLOCKOUT__ Specifies the PLL2 clock(s) to be output + * This parameter can be one or a combination of the following values: + * @arg @ref RCC_PLL_PCLK This clock is used to generate system clock up to 500MHz + * @arg @ref RCC_PLL_QCLK This clock is used to generate peripherals clock up to 500MHz + * @arg @ref RCC_PLL_RCLK This clock is used to generate peripherals clock up to 500MHz + * @arg @ref RCC_PLL_SCLK This clock is used to generate peripherals clock up to 500MHz + * @arg @ref RCC_PLL_TCLK This clock is used to generate peripherals clock up to 500MHz + * @retval None + */ +#define __HAL_RCC_PLL2CLKOUT_ENABLE(__PLL_CLOCKOUT__) SET_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__) << (RCC_PLLCFGR_PLL2PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos))) + +#define __HAL_RCC_PLL2CLKOUT_DISABLE(__PLL_CLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__) << (RCC_PLLCFGR_PLL2PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos))) + +/** + * @brief Macro to get the PLL2 clock output enable status. + * @param __PLL_CLOCKOUT__ specifies the PLL2 clock to be output. + * This parameter can be one of the following values: + * @arg @ref RCC_PLL_PCLK This clock is used to generate system clock up to 500MHz + * @arg @ref RCC_PLL_QCLK This clock is used to generate peripherals clock up to 500MHz + * @arg @ref RCC_PLL_RCLK This clock is used to generate peripherals clock up to 500MHz + * @arg @ref RCC_PLL_SCLK This clock is used to generate peripherals clock up to 500MHz + * @arg @ref RCC_PLL_TCLK This clock is used to generate peripherals clock up to 500MHz + * @retval SET / RESET + */ +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG(__PLL_CLOCKOUT__) (READ_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__) << (RCC_PLLCFGR_PLL2PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos))) \ + >> (RCC_PLLCFGR_PLL2PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos)) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2 + * @retval None + */ +#define __HAL_RCC_PLL2_FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) + +#define __HAL_RCC_PLL2_FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) + +/** + * @brief Macro to configures the PLL2 multiplication and division factors. + * @note This function must be used only when PLL2 is disabled. + * + * @param __PLLSOURCE__ specifies the PLL2 clock source + * This parameter must be a value of @ref RCC_PLL_Clock_Source + * @note PLL2 clock source is addressing a common clock source for all PLLs. + * + * @param __PLL2M__ specifies the division factor for PLL2 VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 16 MHz. + * + * @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock + * This parameter must be a number between 4 and 512 or between 8 and 420(*). + * @note You have to set the PLL2N parameter correctly to ensure that the VCO + * output frequency is between 150 and 420 MHz (when in medium VCO range) or + * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) + * + * @param __PLL2P__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128. + * + * @param __PLL2Q__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128. + * + * @param __PLL2R__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128. + * + * @param __PLL2S__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 8. + * + * @param __PLL2T__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 8. + * + * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ, + * DIVR, DIVS and DIVT) is not used, application shall clear the enable bit (PLL2yEN) + * and assign lowest possible value to __PLL2P__, __PLL2Q__, __PLL2R__, __PLL2S__ + * or __PLL2T__ parameters. + * @retval None + */ + +#define __HAL_RCC_PLL2_CONFIG(__PLLSOURCE__, __PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__, __PLL2S__, __PLL2T__) \ + do{ \ + MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_DIVM2 | RCC_PLLCKSELR_PLLSRC), \ + (((__PLL2M__) << RCC_PLLCKSELR_DIVM2_Pos) | (__PLLSOURCE__))); \ + WRITE_REG(RCC->PLL2DIVR1, ((((__PLL2N__) - 1U) & RCC_PLL2DIVR1_DIVN) | \ + ((((__PLL2P__) - 1U) << RCC_PLL2DIVR1_DIVP_Pos) & RCC_PLL2DIVR1_DIVP) | \ + ((((__PLL2Q__) - 1U) << RCC_PLL2DIVR1_DIVQ_Pos) & RCC_PLL2DIVR1_DIVQ) | \ + ((((__PLL2R__) - 1U) << RCC_PLL2DIVR1_DIVR_Pos) & RCC_PLL2DIVR1_DIVR))); \ + MODIFY_REG(RCC->PLL2DIVR2, (RCC_PLL2DIVR2_DIVS | RCC_PLL2DIVR2_DIVT) , \ + ((((__PLL2S__) - 1U) & RCC_PLL2DIVR2_DIVS) | \ + ((((__PLL2T__) - 1U) << RCC_PLL2DIVR2_DIVT_Pos) & RCC_PLL2DIVR2_DIVT))); \ + } while(0) + +/** + * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor + * + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO + * + * @param __PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO + * It should be a value between 0 and 8191 + * @note Warning: the software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 + * 150 to 420 MHz if PLL2VCOSEL = 1. + * + * + * @retval None + */ +#define __HAL_RCC_PLL2_FRACN_CONFIG(__PLL2FRACN__) \ + MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN,((uint32_t)(__PLL2FRACN__) << RCC_PLL2FRACR_FRACN_Pos)) + +/** @brief Macro to select the PLL2 reference frequency range. + * @param __PLL_VCOINPUT_RANGE__ specifies the PLL2 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL_VCOINPUT_RANGE0: Range frequency is between 1 and 2 MHz + * @arg RCC_PLL_VCOINPUT_RANGE1: Range frequency is between 2 and 4 MHz + * @arg RCC_PLL_VCOINPUT_RANGE2: Range frequency is between 4 and 8 MHz + * @arg RCC_PLL_VCOINPUT_RANGE3: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL2_VCOINPUT_RANGE(__PLL_VCOINPUT_RANGE__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, ((__PLL_VCOINPUT_RANGE__) << (RCC_PLLCFGR_PLL2RGE_Pos - RCC_PLLCFGR_PLL1RGE_Pos))) + + +/** @brief Macro to select the PLL2 reference frequency range. + * @param __PLLVCORANGE__ Specifies the PLL2 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL_VCO_HIGH: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) + * @arg RCC_PLL_VCO_LOW: Range frequency is between 150 and 420 MHz + * + * + * @retval None + */ +#define __HAL_RCC_PLL2_VCORANGE(__PLLVCORANGE__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, ((__PLLVCORANGE__) << (RCC_PLLCFGR_PLL2VCOSEL_Pos - RCC_PLLCFGR_PLL1VCOSEL_Pos))) + +/** @brief Macros to enable or disable the main PLL3. + * @note After enabling PLL3, the application software should wait on + * PLL3RDY flag to be set indicating that PLL3 clock is stable and can + * be used as kernel clock source. + * @note PLL3 is disabled by hardware when entering Stop and Standby modes. + */ +#define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) +#define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3 + * @retval None + */ +#define __HAL_RCC_PLL3_FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) + +#define __HAL_RCC_PLL3_FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) + +/** + * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK, PLL3_S_CLK, PLL3_T_CLK) + * @param __PLL_CLOCKOUT__ Specifies the PLL3 clock(s) to be output + * This parameter can be one or a combination of the following values: + * @arg RCC_PLL_PCLK + * @arg RCC_PLL_QCLK + * @arg RCC_PLL_RCLK + * @arg RCC_PLL_SCLK + * @retval SET / RESET + */ +#define __HAL_RCC_PLL3CLKOUT_ENABLE(__PLL_CLOCKOUT__) SET_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__) << (RCC_PLLCFGR_PLL3PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos))) + +#define __HAL_RCC_PLL3CLKOUT_DISABLE(__PLL_CLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__) << (RCC_PLLCFGR_PLL3PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos))) + +/** + * @brief Macro to get the PLL3 clock output enable status. + * @param __PLL_CLOCKOUT__ specifies the PLL3 clock(s) to be output. + * This parameter can be one of the following values: + * @arg RCC_PLL_PCLK + * @arg RCC_PLL_QCLK + * @arg RCC_PLL_RCLK + * @arg RCC_PLL_SCLK + * @retval SET / RESET + */ +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG(__PLL_CLOCKOUT__) (READ_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__) << (RCC_PLLCFGR_PLL3PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos))) \ + >> (RCC_PLLCFGR_PLL3PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos)) + +/** + * @brief Macro to configures the PLL3 multiplication and division factors. + * @note This function must be used only when PLL3 is disabled. + * + * @param __PLLSOURCE__ specifies the PLL3 clock source + * This parameter must be a value of @ref RCC_PLL_Clock_Source + * @note PLL3 clock source is addressing a common clock source for all PLLs. + * + * @param __PLL3M__ specifies the division factor for PLL3 VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 16 MHz. + * + * @param __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock + * This parameter must be a number between 4 and 512. + * @note You have to set the PLL3N parameter correctly to ensure that the VCO + * output frequency is between 150 and 420 MHz (when in medium VCO range) or + * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) + * + * @param __PLL3P__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 2 and 128 (where odd numbers not allowed) + * + * @param __PLL3Q__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @param __PLL3R__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @param __PLL3S__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 8. + * + * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ, + * DIVR, DIVS and DIVT) is not used, application shall clear the enable bit (PLL3yEN) + * and assign lowest possible value to __PLL3P__, __PLL3Q__, __PLL3R__, __PLL3S__ + * or __PLL3T__ parameters. + */ + +#define __HAL_RCC_PLL3_CONFIG(__PLLSOURCE__, __PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__, __PLL3S__) \ + do{ \ + MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_DIVM3 | RCC_PLLCKSELR_PLLSRC), \ + (((__PLL3M__) << RCC_PLLCKSELR_DIVM3_Pos) | (__PLLSOURCE__))); \ + WRITE_REG(RCC->PLL3DIVR1, ((((__PLL3N__) - 1U) & RCC_PLL3DIVR1_DIVN) | \ + ((((__PLL3P__) - 1U) << RCC_PLL3DIVR1_DIVP_Pos) & RCC_PLL3DIVR1_DIVP) | \ + ((((__PLL3Q__) - 1U) << RCC_PLL3DIVR1_DIVQ_Pos) & RCC_PLL3DIVR1_DIVQ) | \ + ((((__PLL3R__) - 1U) << RCC_PLL3DIVR1_DIVR_Pos) & RCC_PLL3DIVR1_DIVR))); \ + MODIFY_REG(RCC->PLL3DIVR2, RCC_PLL3DIVR2_DIVS, \ + (((__PLL3S__) - 1U) & RCC_PLL3DIVR2_DIVS)); \ + } while(0) + +/** + * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor + * + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO + * + * @param __PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO + * It should be a value between 0 and 8191 + * @note Warning: the software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 + * 150 to 420 MHz if PLL3VCOSEL = 1. + * + * + * @retval None + */ +#define __HAL_RCC_PLL3_FRACN_CONFIG(__PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN, (uint32_t)(__PLL3FRACN__) << RCC_PLL3FRACR_FRACN_Pos) + +/** @brief Macro to select the PLL3 reference frequency range. + * @param __PLL_VCOINPUT_RANGE__ specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL_VCOINPUT_RANGE0: Range frequency is between 1 and 2 MHz + * @arg RCC_PLL_VCOINPUT_RANGE1: Range frequency is between 2 and 4 MHz + * @arg RCC_PLL_VCOINPUT_RANGE2: Range frequency is between 4 and 8 MHz + * @arg RCC_PLL_VCOINPUT_RANGE3: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL3_VCOINPUT_RANGE(__PLL_VCOINPUT_RANGE__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, ((__PLL_VCOINPUT_RANGE__) << (RCC_PLLCFGR_PLL3RGE_Pos - RCC_PLLCFGR_PLL1RGE_Pos))) + +/** @brief Macro to select the PLL3 reference frequency range. + * @param __PLLVCORANGE__ specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL_VCO_HIGH: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) + * @arg RCC_PLL_VCO_HIGH: Range frequency is between 150 and 420 MHz + * + * + * @retval None + */ +#define __HAL_RCC_PLL3_VCORANGE(__PLLVCORANGE__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, ((__PLLVCORANGE__) << (RCC_PLLCFGR_PLL3VCOSEL_Pos - RCC_PLLCFGR_PLL1VCOSEL_Pos))) + +/** + * @} + */ + +/** @defgroup RCC_sysclk_config System clock source configuration + * @{ + */ + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_CSI CSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL1 output is used as system clock source. + * @retval None + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. + * The returned value can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_CSI CSI used as system clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL1 used as system clock. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() \ + READ_BIT(RCC->CFGR, RCC_CFGR_SWS) + +/** + * @} + */ + +/** @addtogroup RCC_Osc_config + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note This parameter cannot be updated while LSE is ON. + * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. + * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); +/** + * @} + */ + +/** @defgroup RCC_wkup_config Wakeup from stop configuration + * @{ + */ + +/** + * @brief Macro to configure the wake up from stop clock. + * @param __STOPWUCLK__ specifies the clock source used after wake up from stop + * This parameter can be one of the following values: + * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source + * @arg @ref RCC_STOP_WAKEUPCLOCK_CSI CSI selected as system clock source + * @retval None + */ +#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) + +/** + * @brief Macro to configure the Kernel wake up from stop clock. + * @param __STOPKERWUCLK__ specifies the Kernel clock source used after wake up from stop + * This parameter can be one of the following values: + * @arg @ref RCC_STOP_KERWAKEUPCLOCK_HSI HSI selected as Kernel clock source + * @arg @ref RCC_STOP_KERWAKEUPCLOCK_CSI CSI selected as Kernel clock source + * @retval None + */ +#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__STOPKERWUCLK__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__STOPKERWUCLK__)) +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Config RCC MCOx Clock Config + * @{ + */ + +/** @brief Macro to configure the MCO1 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO1 source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO1 source + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO1 source + * @arg @ref RCC_MCO1SOURCE_PLL1Q PLL1Q clock selected as MCO1 source + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO1 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO1 clock + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @brief Macro to configure the MCO2 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO2SOURCE_SYSCLK System clock (SYSCLK) selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_PLL2P PLL2P clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_PLL1P PLL1P clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_CSI CSI clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO2 clock + */ +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7U))); + +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_CSIRDY CSI ready interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt + * @arg @ref RCC_IT_LSECSS Clock security system interrupt + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Disable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_CSIRDY CSI ready interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt + * @arg @ref RCC_IT_LSECSS LSE clock security system interrupt + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Clear the RCC's interrupt pending bits + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_CSIRDY CSI ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt + * @arg @ref RCC_IT_LSECSS LSE clock security system interrupt + * @arg @ref RCC_IT_HSECSS HSE clock security interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) + +/** @brief Check whether the RCC interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_CSIRDY CSI ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt + * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt + * @arg @ref RCC_IT_LSECSS LSE clock security system interrupt + * @arg @ref RCC_IT_HSECSS HSE clock security interrupt + * @retval The pending state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are: RCC_FLAG_BORRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->RSR, RCC_RSR_RMVF) + +/** @brief Check whether the selected RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready + * @arg @ref RCC_FLAG_HSIDIV HSI divider ready + * @arg @ref RCC_FLAG_CSIRDY CSI oscillator clock ready + * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready + * @arg @ref RCC_FLAG_PLL1RDY PLL1 clock ready + * @arg @ref RCC_FLAG_PLL2RDY PLL2 clock ready + * @arg @ref RCC_FLAG_PLL3RDY PLL3 clock ready + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready + * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready + * @arg @ref RCC_FLAG_BORRST BOR reset + * @arg @ref RCC_FLAG_PINRST Pin reset + * @arg @ref RCC_FLAG_PORRST Power-on reset + * @arg @ref RCC_FLAG_SFTRST Software reset + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset + * @arg @ref RCC_FLAG_LPWRRST Low Power reset + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == RCC_CR_REG_INDEX) ? RCC->CR : \ + ((((__FLAG__) >> 5U) == RCC_BDCR_REG_INDEX) ? RCC->BDCR : \ + ((((__FLAG__) >> 5U) == RCC_CSR_REG_INDEX) ? RCC->CSR : \ + ((((__FLAG__) >> 5U) == RCC_RSR_REG_INDEX) ? RCC->RSR : RCC->CIFR)))) & \ + (1UL << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32h7rsxx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +uint32_t HAL_RCC_GetPCLK4Freq(void); +uint32_t HAL_RCC_GetPCLK5Freq(void); +uint32_t HAL_RCC_GetPLL1PFreq(void); +uint32_t HAL_RCC_GetPLL1QFreq(void); +uint32_t HAL_RCC_GetPLL1RFreq(void); +uint32_t HAL_RCC_GetPLL1SFreq(void); +uint32_t HAL_RCC_GetPLL2PFreq(void); +uint32_t HAL_RCC_GetPLL2QFreq(void); +uint32_t HAL_RCC_GetPLL2RFreq(void); +uint32_t HAL_RCC_GetPLL2SFreq(void); +uint32_t HAL_RCC_GetPLL2TFreq(void); +uint32_t HAL_RCC_GetPLL3PFreq(void); +uint32_t HAL_RCC_GetPLL3QFreq(void); +uint32_t HAL_RCC_GetPLL3RFreq(void); +uint32_t HAL_RCC_GetPLL3SFreq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User callbacks in non blocking mode (IT mode) */ +void HAL_RCC_HSECSSCallback(void); +void HAL_RCC_LSECSSCallback(void); +uint32_t HAL_RCC_GetResetSource(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +#define RCC_PLL_VCOINPUTFREQ_MAX 16000000U /* Maximum VCO input frequency is 16 MHz */ +#define RCC_PLL_VCOINPUTFREQ_MIN 1000000U /* Minimum VCO input frequency is 1 MHz */ + +#define RCC_PLL_TIMEOUT_VALUE (50U) /* 50 ms */ + +/* Defines used for Flags */ +#define RCC_CR_REG_INDEX 1U +#define RCC_BDCR_REG_INDEX 2U +#define RCC_CSR_REG_INDEX 3U +#define RCC_RSR_REG_INDEX 4U + +#define RCC_FLAG_MASK 0x0000001FU + +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros + * @{ + */ + +/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ + +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) + +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL)) + +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS) || ((__LSE__) == RCC_LSE_BYPASS_DIGITAL)) + +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) + +#define IS_RCC_HSIDIV(__HSIDIV__) (((__HSIDIV__) == RCC_HSI_DIV1) || ((__HSIDIV__) == RCC_HSI_DIV2) || \ + ((__HSIDIV__) == RCC_HSI_DIV4) || ((__HSIDIV__) == RCC_HSI_DIV8)) + +#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) \ + <= (uint32_t)( RCC_HSICFGR_HSITRIM >> RCC_HSICFGR_HSITRIM_Pos)) + +#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) + +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) + +#define IS_RCC_CSI(__CSI__) (((__CSI__) == RCC_CSI_OFF) || ((__CSI__) == RCC_CSI_ON)) + +#define IS_RCC_CSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) \ + <= (uint32_t)( RCC_CSICFGR_CSITRIM >> RCC_CSICFGR_CSITRIM_Pos)) + +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) + +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ + ((__SOURCE__) == RCC_PLLSOURCE_CSI) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U)) + +#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 420U)) + +#define IS_RCC_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U)) + +#define IS_RCC_PLLQ_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U)) + +#define IS_RCC_PLLR_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U)) + +#define IS_RCC_PLLS_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) + +#define IS_RCC_PLLT_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) + +#define IS_RCC_PLL_VCOINPUTFREQ(__VALUE__) ((RCC_PLL_VCOINPUTFREQ_MIN <= (__VALUE__)) &&\ + ((__VALUE__) <= RCC_PLL_VCOINPUTFREQ_MAX)) + +#define IS_RCC_PLLFRACN_VALUE(__VALUE__) ((__VALUE__) <= 8191U) + +#define IS_RCC_PLLCLOCKOUT_VALUE(__VALUE__) (((__VALUE__) == RCC_PLL_PCLK) || \ + ((__VALUE__) == RCC_PLL_QCLK) || \ + ((__VALUE__) == RCC_PLL_RCLK) || \ + ((__VALUE__) == RCC_PLL_SCLK)) + +#define IS_RCC_PLLRGE_VALUE(__VALUE__) (((__VALUE__) == RCC_PLL_VCOINPUT_RANGE0) || \ + ((__VALUE__) == RCC_PLL_VCOINPUT_RANGE1) || \ + ((__VALUE__) == RCC_PLL_VCOINPUT_RANGE2) || \ + ((__VALUE__) == RCC_PLL_VCOINPUT_RANGE3)) + +#define IS_RCC_PLLVCO_VALUE(__VALUE__) (((__VALUE__) == RCC_PLL_VCO_HIGH) || \ + ((__VALUE__) == RCC_PLL_VCO_LOW)) + +#define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 63U)) + +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_SYSCLK(__SYSCLK__) (((__SYSCLK__) == RCC_SYSCLK_DIV1) || ((__SYSCLK__) == RCC_SYSCLK_DIV2) || \ + ((__SYSCLK__) == RCC_SYSCLK_DIV4) || ((__SYSCLK__) == RCC_SYSCLK_DIV8) || \ + ((__SYSCLK__) == RCC_SYSCLK_DIV16) || ((__SYSCLK__) == RCC_SYSCLK_DIV64) || \ + ((__SYSCLK__) == RCC_SYSCLK_DIV128) || ((__SYSCLK__) == RCC_SYSCLK_DIV256) || \ + ((__SYSCLK__) == RCC_SYSCLK_DIV512)) + +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_HCLK_DIV1) || ((__HCLK__) == RCC_HCLK_DIV2) || \ + ((__HCLK__) == RCC_HCLK_DIV4) || ((__HCLK__) == RCC_HCLK_DIV8) || \ + ((__HCLK__) == RCC_HCLK_DIV16) || ((__HCLK__) == RCC_HCLK_DIV64) || \ + ((__HCLK__) == RCC_HCLK_DIV128) || ((__HCLK__) == RCC_HCLK_DIV256) || \ + ((__HCLK__) == RCC_HCLK_DIV512)) + +#define IS_RCC_PCLK1(__PCLK1__) (((__PCLK1__) == RCC_APB1_DIV1) || ((__PCLK1__) == RCC_APB1_DIV2) || \ + ((__PCLK1__) == RCC_APB1_DIV4) || ((__PCLK1__) == RCC_APB1_DIV8) || \ + ((__PCLK1__) == RCC_APB1_DIV16)) + +#define IS_RCC_PCLK2(__PCLK2__) (((__PCLK2__) == RCC_APB2_DIV1) || ((__PCLK2__) == RCC_APB2_DIV2) || \ + ((__PCLK2__) == RCC_APB2_DIV4) || ((__PCLK2__) == RCC_APB2_DIV8) || \ + ((__PCLK2__) == RCC_APB2_DIV16)) + +#define IS_RCC_PCLK4(__PCLK4__) (((__PCLK4__) == RCC_APB4_DIV1) || ((__PCLK4__) == RCC_APB4_DIV2) || \ + ((__PCLK4__) == RCC_APB4_DIV4) || ((__PCLK4__) == RCC_APB4_DIV8) || \ + ((__PCLK4__) == RCC_APB4_DIV16)) + +#define IS_RCC_PCLK5(__PCLK5__) (((__PCLK5__) == RCC_APB5_DIV1) || ((__PCLK5__) == RCC_APB5_DIV2) || \ + ((__PCLK5__) == RCC_APB5_DIV4) || ((__PCLK5__) == RCC_APB5_DIV8) || \ + ((__PCLK5__) == RCC_APB5_DIV16)) + +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV33) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV35) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV37) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV39) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV41) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV43) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV45) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV47) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV49) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV51) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV53) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV55) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV57) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV59) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV61) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV63) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_DISABLE)) + +#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1_PA8) || \ + ((__MCOX__) == RCC_MCO2_PC9)) + +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) + +#define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO2SOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || ((__SOURCE__) == RCC_MCO2SOURCE_PLL1P) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_CSI) || ((__SOURCE__) == RCC_MCO2SOURCE_LSI)) + +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_NONE) || ((__DIV__) == RCC_MCODIV_1) || \ + ((__DIV__) == RCC_MCODIV_2) || ((__DIV__) == RCC_MCODIV_3) || \ + ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_5) || \ + ((__DIV__) == RCC_MCODIV_6) || ((__DIV__) == RCC_MCODIV_7) || \ + ((__DIV__) == RCC_MCODIV_8) || ((__DIV__) == RCC_MCODIV_9) || \ + ((__DIV__) == RCC_MCODIV_10) || ((__DIV__) == RCC_MCODIV_11) || \ + ((__DIV__) == RCC_MCODIV_12) || ((__DIV__) == RCC_MCODIV_13) || \ + ((__DIV__) == RCC_MCODIV_14) || ((__DIV__) == RCC_MCODIV_15)) + +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) + +#define IS_RCC_FLAG(__FLAG__) (((__FLAG__) == RCC_FLAG_HSIRDY) || ((__FLAG__) == RCC_FLAG_HSIDIV ) || \ + ((__FLAG__) == RCC_FLAG_CSIRDY) || ((__FLAG__) == RCC_FLAG_HSI48RDY) || \ + ((__FLAG__) == RCC_FLAG_HSERDY) || ((__FLAG__) == RCC_FLAG_PLL1RDY) || \ + ((__FLAG__) == RCC_FLAG_PLL2RDY) || ((__FLAG__) == RCC_FLAG_PLL3RDY) || \ + ((__FLAG__) == RCC_FLAG_LSERDY) || ((__FLAG__) == RCC_FLAG_LSECSSD) || \ + ((__FLAG__) == RCC_FLAG_LSIRDY) || ((__FLAG__) == RCC_FLAG_BORRST) || \ + ((__FLAG__) == RCC_FLAG_PINRST) || ((__FLAG__) == RCC_FLAG_PORRST) || \ + ((__FLAG__) == RCC_FLAG_SFTRST) || ((__FLAG__) == RCC_FLAG_IWDGRST) || \ + ((__FLAG__) == RCC_FLAG_WWDGRST) || ((__FLAG__) == RCC_FLAG_LPWRRST)) + +#define IS_RCC_HSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x7FU) + +#define IS_RCC_CSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x3FU) + +#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_CSI) || \ + ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) + +#define IS_RCC_STOP_KERWAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \ + ((__SOURCE__) == RCC_STOP_KERWAKEUPCLOCK_HSI)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_RCC_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rcc_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rcc_ex.h new file mode 100644 index 00000000000..2523edda9ea --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rcc_ex.h @@ -0,0 +1,1996 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_RCC_EX_H +#define STM32H7RSxx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC PLL1 Clocks structure definition + */ + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t FmcClockSelection; /*!< Specifies FMC clock source + This parameter can be a value of @ref RCCEx_FMC_Clock_Source */ + + uint32_t Xspi1ClockSelection; /*!< Specifies XSPI1 clock source + This parameter can be a value of @ref RCCEx_XSPI1_Clock_Source */ + + uint32_t Xspi2ClockSelection; /*!< Specifies XSPI2 clock source + This parameter can be a value of @ref RCCEx_XSPI2_Clock_Source */ + + uint32_t CkperClockSelection; /*!< Specifies CKPER clock source + This parameter can be a value of @ref RCCEx_CLKP_Clock_Source */ + + uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source + This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ + + uint32_t Adf1ClockSelection; /*!< Specifies ADF1 Clock clock source + This parameter can be a value of @ref RCCEx_ADF1_Clock_Source */ + + uint32_t CecClockSelection; /*!< Specifies CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t Eth1RefClockSelection; /*!< Specifies ETH1 REF clock source + This parameter can be a value of @ref RCCEx_ETH1REF_Clock_Source */ + + uint32_t Eth1PhyClockSelection; /*!< Specifies ETH1 PHY clock source + This parameter can be a value of @ref RCCEx_ETH1PHY_Clock_Source */ + + uint32_t FdcanClockSelection; /*!< Specifies FDCAN kernel clock source + This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ + + uint32_t I2c1_I3c1ClockSelection; /*!< Specifies I2C1/I3C1 clock source + This parameter can be a value of @ref RCCEx_I2C1_I3C1_Clock_Source */ + + uint32_t I2c23ClockSelection; /*!< Specifies I2C2/I2C3 clock source + This parameter can be a value of @ref RCCEx_I2C23_Clock_Source */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t Lptim23ClockSelection; /*!< Specifies LPTIM2/LPTIM3 clock source + This parameter can be a value of @ref RCCEx_LPTIM23_Clock_Source */ + + uint32_t Lptim45ClockSelection; /*!< Specifies LPTIM4/LPTIM5 clock source + This parameter can be a value of @ref RCCEx_LPTIM45_Clock_Source */ + + uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source + This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ + + uint32_t LtdcClockSelection; /*!< Specifies LPUART1 clock source + This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ + + uint32_t PssiClockSelection; /*!< Specifies PSSI clock source + This parameter can be a value of @ref RCCEx_PSSI_Clock_Source */ + + uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source + This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ + + uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source + This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ + + uint32_t Sdmmc12ClockSelection; /*!< Specifies SDMMC clock source + This parameter can be a value of @ref RCCEx_SDMMC12_Clock_Source */ + + uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source + This parameter can be a value of @ref RCCEx_SPI1_Clock_Source */ + + uint32_t Spi23ClockSelection; /*!< Specifies SPI2/SPI3 clock source + This parameter can be a value of @ref RCCEx_SPI23_Clock_Source */ + + uint32_t Spi45ClockSelection; /*!< Specifies SPI4/SPI5 clock source + This parameter can be a value of @ref RCCEx_SPI45_Clock_Source */ + + uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source + This parameter can be a value of @ref RCCEx_SPI6_Clock_Source */ + + uint32_t SpdifrxClockSelection; /*!< Specifies SPDIFRX Clock clock source + This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t Usart234578ClockSelection; /*!< Specifies USART2/USART3/UART4/UART5/UART7/UART8 clock source + This parameter can be a value of @ref RCCEx_USART234578_Clock_Source */ + + uint32_t UsbPhycClockSelection; /*!< Specifies USB PHYC clock source + This parameter can be a value of @ref RCCEx_USB_PHYC_Clock_Source */ + + uint32_t UsbOtgFsClockSelection; /*!< Specifies USB OTG FS clock source + This parameter can be a value of @ref RCCEx_USB_OTGFS_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock clock source + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. + This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ +} RCC_PeriphCLKInitTypeDef; + +/** + * @brief RCC_CRS Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. + This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ + + uint32_t Source; /*!< Specifies the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ + + uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ + + uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. + It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) + This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ + + uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. + This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ + + uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. + This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ + +} RCC_CRSInitTypeDef; + +/** + * @brief RCC_CRS Synchronization structure definition + */ +typedef struct +{ + uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. + This parameter must be a number between 0 and 0x3F */ + + uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter + value latched in the time of the last SYNC event. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the + frequency error counter latched in the time of the last SYNC event. + It shows whether the actual frequency is below or above the target. + This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ + +} RCC_CRSSynchroInfoTypeDef; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_FMC (0x00000001U) +#define RCC_PERIPHCLK_XSPI1 (0x00000002U) +#define RCC_PERIPHCLK_XSPI2 (0x00000004U) +#define RCC_PERIPHCLK_CKPER (0x00000008U) +#define RCC_PERIPHCLK_ADC (0x00000010U) +#define RCC_PERIPHCLK_ADF1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000040U) +#define RCC_PERIPHCLK_ETH1REF (0x00000080U) +#define RCC_PERIPHCLK_ETH1PHY (0x00000100U) +#define RCC_PERIPHCLK_FDCAN (0x00000200U) +#define RCC_PERIPHCLK_I2C23 (0x00000400U) +#define RCC_PERIPHCLK_I2C1_I3C1 (0x00000800U) +#define RCC_PERIPHCLK_LPTIM1 (0x00001000U) +#define RCC_PERIPHCLK_LPTIM23 (0x00002000U) +#define RCC_PERIPHCLK_LPTIM45 (0x00004000U) +#define RCC_PERIPHCLK_LPUART1 (0x00008000U) +#define RCC_PERIPHCLK_LTDC (0x00010000U) +#define RCC_PERIPHCLK_PSSI (0x00020000U) +#define RCC_PERIPHCLK_RTC (0x00040000U) +#define RCC_PERIPHCLK_SAI1 (0x00080000U) +#define RCC_PERIPHCLK_SAI2 (0x00100000U) +#define RCC_PERIPHCLK_SDMMC12 (0x00200000U) +#define RCC_PERIPHCLK_SPDIFRX (0x00400000U) +#define RCC_PERIPHCLK_SPI1 (0x00800000U) +#define RCC_PERIPHCLK_SPI23 (0x01000000U) +#define RCC_PERIPHCLK_SPI45 (0x02000000U) +#define RCC_PERIPHCLK_SPI6 (0x04000000U) +#define RCC_PERIPHCLK_TIM (0x08000000U) +#define RCC_PERIPHCLK_USART1 (0x10000000U) +#define RCC_PERIPHCLK_USART234578 (0x20000000U) +#define RCC_PERIPHCLK_USBPHYC (0x40000000U) +#define RCC_PERIPHCLK_USBOTGFS (0x80000000U) +/** + * @} + */ + +/** @defgroup RCCEx_FMC_Clock_Source FMC Clock Source + * @{ + */ +#define RCC_FMCCLKSOURCE_HCLK 0U /*!< HCLK selection (default) */ +#define RCC_FMCCLKSOURCE_PLL1Q RCC_CCIPR1_FMCSEL_0 /*!< PLL 'Q' output selection */ +#define RCC_FMCCLKSOURCE_PLL2R RCC_CCIPR1_FMCSEL_1 /*!< PLL2 'R' output selection */ +#define RCC_FMCCLKSOURCE_HSI RCC_CCIPR1_FMCSEL /*!< HSI selection */ +#define RCC_FMCCLKSOURCE_HCLK_DIV4 (RCC_CKPROTR_FMCSWP_2 | RCC_CKPROTR_FMCSWP_0) /*!< HCLK/4 selection (recovery position) */ +/** + * @} + */ + +/** @defgroup RCCEx_XSPI1_Clock_Source XSPI1 Clock Source + * @{ + */ +#define RCC_XSPI1CLKSOURCE_HCLK 0U /*!< HCLK selection (default) */ +#define RCC_XSPI1CLKSOURCE_PLL2S RCC_CCIPR1_XSPI1SEL_0 /*!< PLL2 'S' output selection */ +#define RCC_XSPI1CLKSOURCE_PLL2T RCC_CCIPR1_XSPI1SEL_1 /*!< PLL2 'T' output selection */ +#define RCC_XSPI1CLKSOURCE_HCLK_DIV4 RCC_CKPROTR_XSPI1SWP_2 /*!< HCLK/4 selection (recovery position) */ +/** + * @} + */ + +/** @defgroup RCCEx_XSPI2_Clock_Source XSPI2 Clock Source + * @{ + */ +#define RCC_XSPI2CLKSOURCE_HCLK 0U /*!< HCLK selection (default) */ +#define RCC_XSPI2CLKSOURCE_PLL2S RCC_CCIPR1_XSPI2SEL_0 /*!< PLL2 'S' output selection */ +#define RCC_XSPI2CLKSOURCE_PLL2T RCC_CCIPR1_XSPI2SEL_1 /*!< PLL2 'T' output selection */ +#define RCC_XSPI2CLKSOURCE_HCLK_DIV4 RCC_CKPROTR_XSPI2SWP_2 /*!< HCLK/4 selection (recovery position) */ +/** + * @} + */ + +/** @defgroup RCCEx_CLKP_Clock_Source CLKP Clock Source + * @{ + */ +#define RCC_CLKPSOURCE_HSI 0U /*!< HSI selection (default) */ +#define RCC_CLKPSOURCE_CSI RCC_CCIPR1_CKPERSEL_0 /*!< CSI selection */ +#define RCC_CLKPSOURCE_HSE RCC_CCIPR1_CKPERSEL_1 /*!< HSE selection */ +/** + * @} + */ + +/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source + * @{ + */ +#define RCC_ADCCLKSOURCE_PLL2P 0U /*!< PLL2 'P' output selection (default) */ +#define RCC_ADCCLKSOURCE_PLL3R RCC_CCIPR1_ADCSEL_0 /*!< PLL3 'R' output selection */ +#define RCC_ADCCLKSOURCE_CLKP RCC_CCIPR1_ADCSEL_1 /*!< Clock peripheral output selection */ +/** + * @} + */ + +/** @defgroup RCCEx_ADF1_Clock_Source ADF1 Clock Source + * @{ + */ +#define RCC_ADF1CLKSOURCE_HCLK 0U /*!< HCLK selection (default) */ +#define RCC_ADF1CLKSOURCE_PLL2P RCC_CCIPR1_ADF1SEL_0 /*!< PLL2 'P' output selection */ +#define RCC_ADF1CLKSOURCE_PLL3P RCC_CCIPR1_ADF1SEL_1 /*!< PLL3 'P' output selection */ +#define RCC_ADF1CLKSOURCE_PIN (RCC_CCIPR1_ADF1SEL_1 | RCC_CCIPR1_ADF1SEL_0) /*!< External I2S_PIN selection */ +#define RCC_ADF1CLKSOURCE_CSI RCC_CCIPR1_ADF1SEL_2 /*!< CSI selection */ +#define RCC_ADF1CLKSOURCE_HSI (RCC_CCIPR1_ADF1SEL_2 | RCC_CCIPR1_ADF1SEL_0) /*!< HSI selection */ +/** + * @} + */ + +/** @defgroup RCCEx_CEC_Clock_Source CEC Clock Source + * @{ + */ +#define RCC_CECCLKSOURCE_LSE 0U /*!< LSE selection (default) */ +#define RCC_CECCLKSOURCE_LSI RCC_CCIPR2_CECSEL_0 /*!< LSI selection */ +#define RCC_CECCLKSOURCE_CSI RCC_CCIPR2_CECSEL_1 /*!< CSI divided by 122 selection */ +/** + * @} + */ + +/** @defgroup RCCEx_ETH1REF_Clock_Source ETH1 REF Clock Source + * @{ + */ +#define RCC_ETH1REFCLKSOURCE_PHY 0U /*!< ETH PHY selection (default) */ +#define RCC_ETH1REFCLKSOURCE_HSE RCC_CCIPR1_ETH1REFCKSEL_0 /*!< HSE selection */ +#define RCC_ETH1REFCLKSOURCE_ETH RCC_CCIPR1_ETH1REFCKSEL_1 /*!< ETH Feedback output selection */ +/** + * @} + */ + +/** @defgroup RCCEx_ETH1PHY_Clock_Source ETH1 PHY Clock Source + * @{ + */ +#define RCC_ETH1PHYCLKSOURCE_HSE 0U /*!< HSE selection (default) */ +#define RCC_ETH1PHYCLKSOURCE_PLL3S RCC_CCIPR1_ETH1PHYCKSEL /*!< PLL3 'S' output selection */ +/** + * @} + */ + +/** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Kernel Clock Source + * @{ + */ +#define RCC_FDCANCLKSOURCE_HSE 0U /*!< HSE selection (default) */ +#define RCC_FDCANCLKSOURCE_PLL1Q RCC_CCIPR2_FDCANSEL_0 /*!< PLL1 'Q' output selection */ +#define RCC_FDCANCLKSOURCE_PLL2P RCC_CCIPR2_FDCANSEL_1 /*!< PLL2 'P' output selection */ +/** + * @} + */ + +/** @defgroup RCCEx_I2C23_Clock_Source I2C2/I2C3 Clock Source + * @{ + */ +#define RCC_I2C23CLKSOURCE_PCLK1 0U /*!< PCLK1 selection (default) */ +#define RCC_I2C23CLKSOURCE_PLL3R RCC_CCIPR2_I2C23SEL_0 /*!< PLL3 'R' output selection */ +#define RCC_I2C23CLKSOURCE_HSI RCC_CCIPR2_I2C23SEL_1 /*!< HSI selection */ +#define RCC_I2C23CLKSOURCE_CSI (RCC_CCIPR2_I2C23SEL_1 | RCC_CCIPR2_I2C23SEL_0) /*!< CSI selection */ +/** + * @} + */ + +/** @defgroup RCCEx_I2C1_I3C1_Clock_Source I2C1/I3C1Clock Source + * @{ + */ +#define RCC_I2C1_I3C1CLKSOURCE_PCLK1 0U /*!< PCLK1 selection (default) */ +#define RCC_I2C1_I3C1CLKSOURCE_PLL3R RCC_CCIPR2_I2C1_I3C1SEL_0 /*!< PLL3 'R' output selection */ +#define RCC_I2C1_I3C1CLKSOURCE_HSI RCC_CCIPR2_I2C1_I3C1SEL_1 /*!< HSI selection */ +#define RCC_I2C1_I3C1CLKSOURCE_CSI (RCC_CCIPR2_I2C1_I3C1SEL_1 | RCC_CCIPR2_I2C1_I3C1SEL_0) /*!< CSI selection */ +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 0U /*!< PCLK1 selection (default) */ +#define RCC_LPTIM1CLKSOURCE_PLL2P RCC_CCIPR2_LPTIM1SEL_0 /*!< PLL2 'P' output selection */ +#define RCC_LPTIM1CLKSOURCE_PLL3R RCC_CCIPR2_LPTIM1SEL_1 /*!< PLL3 'R' output selection */ +#define RCC_LPTIM1CLKSOURCE_LSE (RCC_CCIPR2_LPTIM1SEL_1 | RCC_CCIPR2_LPTIM1SEL_0) /*!< LSE selection */ +#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR2_LPTIM1SEL_2 /*!< LSI selection */ +#define RCC_LPTIM1CLKSOURCE_CLKP (RCC_CCIPR2_LPTIM1SEL_2 | RCC_CCIPR2_LPTIM1SEL_0) /*!< Clock peripheral output selection */ +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM23_Clock_Source LPTIM2/LPTIM3 Clock Source + * @{ + */ +#define RCC_LPTIM23CLKSOURCE_PCLK4 0U /*!< PCLK4 selection (default) */ +#define RCC_LPTIM23CLKSOURCE_PLL2P RCC_CCIPR4_LPTIM23SEL_0 /*!< PLL2 'P' output selection */ +#define RCC_LPTIM23CLKSOURCE_PLL3R RCC_CCIPR4_LPTIM23SEL_1 /*!< PLL3 'R' output selection */ +#define RCC_LPTIM23CLKSOURCE_LSE (RCC_CCIPR4_LPTIM23SEL_1 | RCC_CCIPR4_LPTIM23SEL_0) /*!< LSE selection */ +#define RCC_LPTIM23CLKSOURCE_LSI RCC_CCIPR4_LPTIM23SEL_2 /*!< LSI selection */ +#define RCC_LPTIM23CLKSOURCE_CLKP (RCC_CCIPR4_LPTIM23SEL_2 | RCC_CCIPR4_LPTIM23SEL_0) /*!< Clock peripheral output selection */ +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM45_Clock_Source LPTIM4/LPTIM5 Clock Source + * @{ + */ +#define RCC_LPTIM45CLKSOURCE_PCLK4 0U /*!< PCLK4 selection (default) */ +#define RCC_LPTIM45CLKSOURCE_PLL2P RCC_CCIPR4_LPTIM45SEL_0 /*!< PLL2 'P' output selection */ +#define RCC_LPTIM45CLKSOURCE_PLL3R RCC_CCIPR4_LPTIM45SEL_1 /*!< PLL3 'R' output selection */ +#define RCC_LPTIM45CLKSOURCE_LSE (RCC_CCIPR4_LPTIM45SEL_1 | RCC_CCIPR4_LPTIM45SEL_0) /*!< LSE selection */ +#define RCC_LPTIM45CLKSOURCE_LSI RCC_CCIPR4_LPTIM45SEL_2 /*!< LSI selection */ +#define RCC_LPTIM45CLKSOURCE_CLKP (RCC_CCIPR4_LPTIM45SEL_2 | RCC_CCIPR4_LPTIM45SEL_0) /*!< Clock peripheral output selection */ +/** + * @} + */ + +/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source + * @{ + */ +#define RCC_LPUART1CLKSOURCE_PCLK4 0U /*!< PCLK4 selection (default) */ +#define RCC_LPUART1CLKSOURCE_PLL2Q RCC_CCIPR4_LPUART1SEL_0 /*!< PLL2 'Q' output selection */ +#define RCC_LPUART1CLKSOURCE_PLL3Q RCC_CCIPR4_LPUART1SEL_1 /*!< PLL2 'Q' output selection */ +#define RCC_LPUART1CLKSOURCE_HSI (RCC_CCIPR4_LPUART1SEL_1 | RCC_CCIPR4_LPUART1SEL_0) /*!< HSI selection */ +#define RCC_LPUART1CLKSOURCE_CSI RCC_CCIPR4_LPUART1SEL_2 /*!< CSI selection */ +#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR4_LPUART1SEL_2 | RCC_CCIPR4_LPUART1SEL_0) /*!< LSE selection */ +/** + * @} + */ + +/** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source + * @{ + */ +#define RCC_LTDCCLKSOURCE_PLL3R 0U /*!< PLL3 'R' output selection (unique) */ +/** + * @} + */ + +/** @defgroup RCCEx_PSSI_Clock_Source PSSI Clock Source + * @{ + */ +#define RCC_PSSICLKSOURCE_PLL3R 0U /*!< PLL3 'R' output selection (default) */ +#define RCC_PSSICLKSOURCE_CLKP RCC_CCIPR1_PSSISEL /*!< Clock peripheral output selection */ +/** + * @} + */ + +/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source + * @{ + */ +#define RCC_SAI1CLKSOURCE_PLL1Q 0U /*!< PLL1 'Q' output selection (default) */ +#define RCC_SAI1CLKSOURCE_PLL2P RCC_CCIPR3_SAI1SEL_0 /*!< PLL2 'P' output selection */ +#define RCC_SAI1CLKSOURCE_PLL3P RCC_CCIPR3_SAI1SEL_1 /*!< PLL3 'P' output selection */ +#define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR3_SAI1SEL_1 | RCC_CCIPR3_SAI1SEL_0) /*!< I2S_PIN selection */ +#define RCC_SAI1CLKSOURCE_CLKP RCC_CCIPR3_SAI1SEL_2 /*!< Clock peripheral output selection */ +/** + * @} + */ + +/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source + * @{ + */ +#define RCC_SAI2CLKSOURCE_PLL1Q 0U /*!< PLL1 'Q' output selection (default) */ +#define RCC_SAI2CLKSOURCE_PLL2P RCC_CCIPR3_SAI2SEL_0 /*!< PLL2 'P' output selection */ +#define RCC_SAI2CLKSOURCE_PLL3P RCC_CCIPR3_SAI2SEL_1 /*!< PLL3 'P' output selection */ +#define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR3_SAI2SEL_1 | RCC_CCIPR3_SAI2SEL_0) /*!< I2S_PIN selection */ +#define RCC_SAI2CLKSOURCE_CLKP RCC_CCIPR3_SAI2SEL_2 /*!< Clock peripheral output selection */ +#define RCC_SAI2CLKSOURCE_SPDIF (RCC_CCIPR3_SAI2SEL_2 | RCC_CCIPR3_SAI2SEL_0) /*!< SPDIF output selection */ +/** + * @} + */ + +/** @defgroup RCCEx_SDMMC12_Clock_Source SDMMC Clock Source + * @{ + */ +#define RCC_SDMMC12CLKSOURCE_PLL2S 0U /*!< PLL2 'S' output selection (default) */ +#define RCC_SDMMC12CLKSOURCE_PLL2T RCC_CCIPR1_SDMMC12SEL /*!< PLL2 'T' output selection */ +/** + * @} + */ + +/** @defgroup RCCEx_SPDIFRX_Clock_Source SPDIFRX Clock Source + * @{ + */ +#define RCC_SPDIFRXCLKSOURCE_PLL1Q 0U /*!< PLL1 'Q' output selection (default) */ +#define RCC_SPDIFRXCLKSOURCE_PLL2R RCC_CCIPR2_SPDIFRXSEL_0 /*!< PLL2 'R' output selection */ +#define RCC_SPDIFRXCLKSOURCE_PLL3R RCC_CCIPR2_SPDIFRXSEL_1 /*!< PLL3 'R' output selection */ +#define RCC_SPDIFRXCLKSOURCE_HSI RCC_CCIPR2_SPDIFRXSEL /*!< HSI selection */ +/** + * @} + */ + +/** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source + * @{ + */ +#define RCC_SPI1CLKSOURCE_PLL1Q 0U /*!< PLL1 'Q' output selection (default) */ +#define RCC_SPI1CLKSOURCE_PLL2P RCC_CCIPR3_SPI1SEL_0 /*!< PLL2 'P' output selection */ +#define RCC_SPI1CLKSOURCE_PLL3P RCC_CCIPR3_SPI1SEL_1 /*!< PLL3 'P' output selection */ +#define RCC_SPI1CLKSOURCE_PIN (RCC_CCIPR3_SPI1SEL_1 | RCC_CCIPR3_SPI1SEL_0) /*!< I2S_PIN selection */ +#define RCC_SPI1CLKSOURCE_CLKP RCC_CCIPR3_SPI1SEL_2 /*!< Clock peripheral output selection */ +/** + * @} + */ + +/** @defgroup RCCEx_SPI23_Clock_Source SPI2/SPI3 Clock Source + * @{ + */ +#define RCC_SPI23CLKSOURCE_PLL1Q 0U /*!< PLL1 'Q' output selection (default) */ +#define RCC_SPI23CLKSOURCE_PLL2P RCC_CCIPR2_SPI23SEL_0 /*!< PLL2 'P' output selection */ +#define RCC_SPI23CLKSOURCE_PLL3P RCC_CCIPR2_SPI23SEL_1 /*!< PLL3 'P' output selection */ +#define RCC_SPI23CLKSOURCE_PIN (RCC_CCIPR2_SPI23SEL_1 | RCC_CCIPR2_SPI23SEL_0) /*!< I2S_PIN selection */ +#define RCC_SPI23CLKSOURCE_CLKP RCC_CCIPR2_SPI23SEL_2 /*!< Clock peripheral output selection */ +/** + * @} + */ + +/** @defgroup RCCEx_SPI45_Clock_Source SPI4/SPI5 Clock Source + * @{ + */ +#define RCC_SPI45CLKSOURCE_PCLK2 0U /*!< PCLK2 selection (default) */ +#define RCC_SPI45CLKSOURCE_PLL2Q RCC_CCIPR3_SPI45SEL_0 /*!< PLL2 'Q' output selection */ +#define RCC_SPI45CLKSOURCE_PLL3Q RCC_CCIPR3_SPI45SEL_1 /*!< PLL3 'Q' output selection */ +#define RCC_SPI45CLKSOURCE_HSI (RCC_CCIPR3_SPI45SEL_1 | RCC_CCIPR3_SPI45SEL_0) /*!< HSI selection */ +#define RCC_SPI45CLKSOURCE_CSI RCC_CCIPR3_SPI45SEL_2 /*!< CSI selection */ +#define RCC_SPI45CLKSOURCE_HSE (RCC_CCIPR3_SPI45SEL_2 | RCC_CCIPR3_SPI45SEL_0) /*!< HSE selection */ +/** + * @} + */ + +/** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source + * @{ + */ +#define RCC_SPI6CLKSOURCE_PCLK4 0U /*!< PCLK4 selection (default) */ +#define RCC_SPI6CLKSOURCE_PLL2Q RCC_CCIPR4_SPI6SEL_0 /*!< PLL2 'Q' output selection */ +#define RCC_SPI6CLKSOURCE_PLL3Q RCC_CCIPR4_SPI6SEL_1 /*!< PLL3 'Q' output selection */ +#define RCC_SPI6CLKSOURCE_HSI (RCC_CCIPR4_SPI6SEL_1 | RCC_CCIPR4_SPI6SEL_0) /*!< HSI selection */ +#define RCC_SPI6CLKSOURCE_CSI RCC_CCIPR4_SPI6SEL_2 /*!< CSI selection */ +#define RCC_SPI6CLKSOURCE_HSE (RCC_CCIPR4_SPI6SEL_2 | RCC_CCIPR4_SPI6SEL_0) /*!< HSE selection */ +/** + * @} + */ + +/** @defgroup RCCEx_TIM_Prescaler_Selection TIM Prescaler Selection + * @{ + */ +#define RCC_TIMPRES_DISABLE 0U /*!< Timers clocks prescaler not set (default) */ +#define RCC_TIMPRES_ENABLE RCC_CFGR_TIMPRE /*!< Timers clocks prescaler set */ + +/** + * @} + */ + +/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK2 0U /*!< PCLK2 selection (default) */ +#define RCC_USART1CLKSOURCE_PLL2Q RCC_CCIPR3_USART1SEL_0 /*!< PLL2 'Q' output selection */ +#define RCC_USART1CLKSOURCE_PLL3Q RCC_CCIPR3_USART1SEL_1 /*!< PLL2 'Q' output selection */ +#define RCC_USART1CLKSOURCE_HSI (RCC_CCIPR3_USART1SEL_1 | RCC_CCIPR3_USART1SEL_0) /*!< HSI selection */ +#define RCC_USART1CLKSOURCE_CSI RCC_CCIPR3_USART1SEL_2 /*!< CSI selection */ +#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR3_USART1SEL_2 | RCC_CCIPR3_USART1SEL_0) /*!< LSE selection */ +/** + * @} + */ + +/** @defgroup RCCEx_USART234578_Clock_Source USART2/USART3/UART4/UART5/UART7/UART8 Clock Source + * @{ + */ +#define RCC_USART234578CLKSOURCE_PCLK1 0U /*!< PCLK1 selection (default) */ +#define RCC_USART234578CLKSOURCE_PLL2Q RCC_CCIPR2_UART234578SEL_0 /*!< PLL2 'Q' output selection */ +#define RCC_USART234578CLKSOURCE_PLL3Q RCC_CCIPR2_UART234578SEL_1 /*!< PLL3 'Q' output selection */ +#define RCC_USART234578CLKSOURCE_HSI (RCC_CCIPR2_UART234578SEL_1 | RCC_CCIPR2_UART234578SEL_0) /*!< HSI selection */ +#define RCC_USART234578CLKSOURCE_CSI RCC_CCIPR2_UART234578SEL_2 /*!< CSI selection */ +#define RCC_USART234578CLKSOURCE_LSE (RCC_CCIPR2_UART234578SEL_2 | RCC_CCIPR2_UART234578SEL_0) /*!< LSE selection */ +/** + * @} + */ + +/** @defgroup RCCEx_USB_PHYC_Clock_Source USB PHYC Clock Source + * @{ + */ +#define RCC_USBPHYCCLKSOURCE_HSE 0U /*!< HSE selection (default) */ +#define RCC_USBPHYCCLKSOURCE_HSE_DIV2 RCC_CCIPR1_USBPHYCSEL_0 /*!< HSE div 2 selection */ +#define RCC_USBPHYCCLKSOURCE_PLL3Q RCC_CCIPR1_USBPHYCSEL_1 /*!< PLL3 'Q' output selection */ +/** + * @} + */ + +/** @defgroup RCCEx_USB_OTGFS_Clock_Source USB OTG FS Clock Source + * @{ + */ +#define RCC_USBOTGFSCLKSOURCE_HSI48 0U /*!< HSI48 selection (default) */ +#define RCC_USBOTGFSCLKSOURCE_PLL3Q RCC_CCIPR1_OTGFSSEL_0 /*!< PLL3 'Q' output selection */ +#define RCC_USBOTGFSCLKSOURCE_HSE RCC_CCIPR1_OTGFSSEL_1 /*!< HSE selection */ +#define RCC_USBOTGFSCLKSOURCE_CLK48 RCC_CCIPR1_OTGFSSEL /*!< USBPHYC CLK48 output selection */ +/** + * @} + */ + +/** @defgroup RCCEx_Clock_Protection Clock Protection + * @{ + */ +#define RCC_CLOCKPROTECT_XSPI RCC_CKPROTR_XSPICKP /*!< XSPIs clock protection */ +#define RCC_CLOCKPROTECT_FMC RCC_CKPROTR_FMCCKP /*!< FMC clock protection */ +/** + * @} + */ + + +/** @defgroup RCCEx_EXTI_LINE_LSECSS LSE CSS external interrupt line + * @{ + */ +#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18 /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Status CRS Status + * @{ + */ +#define RCC_CRS_NONE 0x00000000U +#define RCC_CRS_TIMEOUT 0x00000001U +#define RCC_CRS_SYNCOK 0x00000002U +#define RCC_CRS_SYNCWARN 0x00000004U +#define RCC_CRS_SYNCERR 0x00000008U +#define RCC_CRS_SYNCMISS 0x00000010U +#define RCC_CRS_TRIMOVF 0x00000020U +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroSource CRS SynchroSource + * @{ + */ +#define RCC_CRS_SYNC_SOURCE_GPIO 0U /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define RCC_CRS_SYNC_SOURCE_USB_OTG_FS CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB OTG FS SOF (default) */ +#define RCC_CRS_SYNC_SOURCE_USB_OTG_HS (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0) /*!< Synchro Signal source USB OTG HS SOF */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroDivider CRS SynchroDivider + * @{ + */ +#define RCC_CRS_SYNC_DIV1 0U /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroPolarity CRS SynchroPolarity + * @{ + */ +#define RCC_CRS_SYNC_POLARITY_RISING 0U /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ReloadValueDefault CRS ReloadValueDefault + * @{ + */ +#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds + to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ErrorLimitDefault CRS ErrorLimitDefault + * @{ + */ +#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_HSI48CalibrationDefault CRS HSI48CalibrationDefault + * @{ + */ +#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. + The trimming step is specified in the product datasheet. A higher TRIM value corresponds + to a higher output frequency */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_FreqErrorDirection CRS FreqErrorDirection + * @{ + */ +#define RCC_CRS_FREQERRORDIR_UP 0U /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Interrupt_Sources CRS Interrupt Sources + * @{ + */ +#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ +#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ +#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ +#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ +#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ +#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ +#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Flags CRS Flags + * @{ + */ +#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ +#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ +#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ +#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ +#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ +#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ +#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + +/** @brief Macro to configure the ADC clock + * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. + * This parameter can be one of the following values: + * @arg RCC_ADCCLKSOURCE_PLL2P PLL2_P Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_PLL3R PLL3_R Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_CLKP CLKP Clock selected as ADC clock + */ +#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) + +/** @brief Macro to get the ADC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ADCCLKSOURCE_PLL2P PLL2_P Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_PLL3R PLL3_R Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_CLKP CLKP Clock selected as ADC clock + */ +#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADCSEL))) + +/** @brief Macro to configure the ADF1 clock + * @param __ADF1_CLKSOURCE__ specifies the ADF1 clock source. + * This parameter can be one of the following values: + * @arg RCC_ADF1CLKSOURCE_HCLK HCLK Clock selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_PLL2P PLL2_P Clock selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_PLL3P PLL3_P Clock selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_PIN External I2S_CKIN selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_CSI CSI selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_HSI HSI selected as ADF1 clock + */ +#define __HAL_RCC_ADF1_CONFIG(__ADF1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADF1SEL, (uint32_t)(__ADF1_CLKSOURCE__)) + +/** @brief Macro to get the ADF1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ADF1CLKSOURCE_HCLK HCLK Clock selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_PLL2P PLL2_P Clock selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_PLL3P PLL3_P Clock selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_PIN External I2S_CKIN selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_CSI CSI selected as ADF1 clock + * @arg RCC_ADF1CLKSOURCE_HSI HSI selected as ADF1 clock + */ +#define __HAL_RCC_GET_ADF1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADF1SEL))) + +/** @brief Macro to configure the HDMI-CEC clock source. + * @param __CEC_CLKSOURCE__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSI LSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_CSI CSI divided by 122 selected as CEC clock + */ +#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) + +/** @brief Macro to get the HDMI-CEC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSI LSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_CSI CSI divided by 122 selected as CEC clock + */ +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_CECSEL))) + +/** @brief Macro to configure the CLKP : Oscillator clock for peripheral + * @param __CLKP_CLKSOURCE__ specifies Oscillator clock for peripheral + * This parameter can be one of the following values: + * @arg RCC_CLKPSOURCE_HSI HSI selected as peripheral clock (default) + * @arg RCC_CLKPSOURCE_CSI CSI selected as peripheral clock + * @arg RCC_CLKPSOURCE_HSE HSE selected as peripheral clock + */ +#define __HAL_RCC_CLKP_CONFIG(__CLKP_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CKPERSEL, (uint32_t)(__CLKP_CLKSOURCE__)) + +/** @brief Macro to get the Oscillator clock for peripheral source. + * @retval The clock source can be one of the following values: + * @arg RCC_CLKPSOURCE_HSI HSI selected as peripheral clock (default) + * @arg RCC_CLKPSOURCE_CSI CSI selected as peripheral clock + * @arg RCC_CLKPSOURCE_HSE HSE selected as peripheral clock + */ +#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CKPERSEL))) + +/** @brief Macro to configure the ETH1 REF clock source. + * @param __ETH1REF_CLKSOURCE__ specifies clock source for ETH1 REF + * This parameter can be one of the following values: + * @arg RCC_ETH1REFCLKSOURCE_PHY ETH PHY selected as ETH1 REF clock (default) + * @arg RCC_ETH1REFCLKSOURCE_HSE HSE selected as ETH1 clock + * @arg RCC_ETH1REFCLKSOURCE_ETH ETH feedback selected as ETH1 REF clock + */ +#define __HAL_RCC_ETH1REF_CONFIG(__ETH1REF_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ETH1REFCKSEL, (uint32_t)(__ETH1REF_CLKSOURCE__)) + +/** @brief Macro to get the ETH1 REF clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ETH1REFCLKSOURCE_PHY ETH PHY selected as ETH1 clock (default) + * @arg RCC_ETH1REFCLKSOURCE_HSE HSE selected as ETH1 clock + * @arg RCC_ETH1REFCLKSOURCE_ETH ETH feedback selected as ETH1 clock + */ +#define __HAL_RCC_GET_ETH1REF_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ETH1REFCKSEL))) + +/** @brief Macro to configure the ETH1 PHY clock source. + * @param __ETH1PHY_CLKSOURCE__ specifies clock source for ETH PHY + * This parameter can be one of the following values: + * @arg RCC_ETH1PHYCLKSOURCE_HSE HSE selected as ETH PHY clock (default) + * @arg RCC_ETH1PHYCLKSOURCE_PLL3S PLL3_S selected as ETH PHY clock + */ +#define __HAL_RCC_ETH1PHY_CONFIG(__ETH1PHY_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ETH1PHYCKSEL, (uint32_t)(__ETH1PHY_CLKSOURCE__)) + +/** @brief Macro to get the ETH1 PHY clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ETH1PHYCLKSOURCE_HSE HSE selected as ETH PHY clock (default) + * @arg RCC_ETH1PHYCLKSOURCE_PLL3S PLL3_S selected as ETH PHY clock + */ +#define __HAL_RCC_GET_ETH1PHY_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ETH1PHYCKSEL))) + +/** @brief Macro to configure the FDCAN kernel clock source. + * @param __FDCAN_CLKSOURCE__ specifies clock source for FDCAN kernel + * This parameter can be one of the following values: + * @arg RCC_FDCANCLKSOURCE_HSE HSE selected as FDCAN kernel clock (default) + * @arg RCC_FDCANCLKSOURCE_PLL1Q PLL1_Q selected as FDCAN kernel clock + * @arg RCC_FDCANCLKSOURCE_PLL2P PLL2_P selected as FDCAN kernel clock + */ +#define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) + +/** @brief Macro to get the FDCAN kernel clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_FDCANCLKSOURCE_HSE HSE selected as FDCAN kernel clock (default) + * @arg RCC_FDCANCLKSOURCE_PLL1Q PLL1_Q selected as FDCAN kernel clock + * @arg RCC_FDCANCLKSOURCE_PLL2P PLL2_P selected as FDCAN kernel clock + */ +#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL))) + +/** @brief Macro to configure the FMC clock source. + * + * @param __FMC_CLKSOURCE__ specifies the FMC clock source. + * @arg RCC_FMCCLKSOURCE_HCLK HCLK Clock selected as FMC clock + * @arg RCC_FMCCLKSOURCE_PLL1Q PLL1_Q Clock selected as FMC clock + * @arg RCC_FMCCLKSOURCE_PLL2R PLL2_R Clock selected as FMC clock + * @arg RCC_FMCCLKSOURCE_HSI HSI selected as FMC clock + */ +#define __HAL_RCC_FMC_CONFIG(__FMC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FMCSEL, (uint32_t)(__FMC_CLKSOURCE__)) + +/** @brief Macro to get the FMC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_FMCCLKSOURCE_HCLK HCLK Clock selected as FMC clock + * @arg RCC_FMCCLKSOURCE_PLL1Q PLL1_Q Clock selected as FMC clock + * @arg RCC_FMCCLKSOURCE_PLL2R PLL2_R Clock selected as FMC clock + * @arg RCC_FMCCLKSOURCE_HSI HSI selected as FMC clock + * @arg RCC_FMCCLKSOURCE_HCLK_DIV4 Recovery Clock selected as FMC clock + */ +#define __HAL_RCC_GET_FMC_SOURCE() ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_FMCSWP) == RCC_FMCCLKSOURCE_HCLK_DIV4) ? \ + RCC_FMCCLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FMCSEL)))) + +/** @brief Macro to configure the I2C1/I3C1 clock source. + * @param __I2C1_I3C1_CLKSOURCE__ specifies the I2C1/I3C1clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C1_I3C1CLKSOURCE_PCLK1 APB1 selected as I2C1/I3C1clock + * @arg RCC_I2C1_I3C1CLKSOURCE_PLL3R PLL3_R selected as I2C1/I3C1clock + * @arg RCC_I2C1_I3C1CLKSOURCE_HSI HSI selected as I2C1/I3C1clock + * @arg RCC_I2C1_I3C1CLKSOURCE_CSI CSI selected as I2C1/I3C1clock + */ +#define __HAL_RCC_I2C1_I3C1_CONFIG(__I2C1_I3C1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C1_I3C1SEL, (uint32_t)(__I2C1_I3C1_CLKSOURCE__)) + +/** @brief Macro to get the I2C1/I3C1clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C1_I3C1CLKSOURCE_PCLK1 APB1 selected as I2C1/I3C1clock + * @arg RCC_I2C1_I3C1CLKSOURCE_PLL3R PLL3_R selected as I2C1/I3C1clock + * @arg RCC_I2C1_I3C1CLKSOURCE_HSI HSI selected as I2C1/I3C1clock + * @arg RCC_I2C1_I3C1CLKSOURCE_CSI CSI selected as I2C1/I3C1clock + */ +#define __HAL_RCC_GET_I2C1_I3C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C1_I3C1SEL))) + +/** @brief Macro to configure the I2C2/I2C3 clock source. + * @param __I2C23_CLKSOURCE__ specifies the I2C2/I2C3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C23CLKSOURCE_PCLK1 APB1 selected as I2C2/I2C3 clock + * @arg RCC_I2C23CLKSOURCE_PLL3R PLL3_R selected as I2C2/I2C3 clock + * @arg RCC_I2C23CLKSOURCE_HSI HSI selected as I2C2/I2C3 clock + * @arg RCC_I2C23CLKSOURCE_CSI CSI selected as I2C2/I2C3 clock + */ +#define __HAL_RCC_I2C23_CONFIG(__I2C23_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C23SEL, (uint32_t)(__I2C23_CLKSOURCE__)) + +/** @brief Macro to get the I2C2/I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C23CLKSOURCE_PCLK1 APB1 selected as I2C2/I2C3 clock + * @arg RCC_I2C23CLKSOURCE_PLL3R PLL3_R selected as I2C2/I2C3 clock + * @arg RCC_I2C23CLKSOURCE_HSI HSI selected as I2C2/I2C3 clock + * @arg RCC_I2C23CLKSOURCE_CSI CSI selected as I2C2/I2C3 clock + */ +#define __HAL_RCC_GET_I2C23_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C23SEL))) + +/** @brief Macro to configure the I3C1 clock source. + * @param __I3C1_CLKSOURCE__ specifies the I3C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I3C1CLKSOURCE_PCLK1 APB1 selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_PLL3R PLL3_R selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_CSI CSI selected as I3C1 clock + */ +#define __HAL_RCC_I3C1_CONFIG(__I3C1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C1_I3C1SEL, (uint32_t)(__I3C1_CLKSOURCE__)) + +/** @brief Macro to get the I3C1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I3C1CLKSOURCE_PCLK1 APB1 selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_PLL3R PLL3_R selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_HSI HSI selected as I3C1 clock + * @arg RCC_I3C1CLKSOURCE_CSI CSI selected as I3C1 clock + */ +#define __HAL_RCC_GET_I3C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C1_I3C1SEL))) + +/** @brief Macro to configure the LPTIM1 clock source. + * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1 APB1 clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL2P PLL2_P selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL3R PLL3_R selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI LSI Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_CLKP CLKP selected as LPTIM1 clock + */ +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1 APB1 clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL2P PLL2_P selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL3R PLL3_R selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI LSI Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_CLKP CLKP selected as LPTIM1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIM1SEL))) + +/** @brief Macro to configure the LPTIM2/LPTIM3 clock source. + * @param __LPTIM23_CLKSOURCE__ specifies the LPTIM2/LPTIM3 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM23CLKSOURCE_PCLK4 APB4 clock selected as LPTIM2/LPTIM3 clock + * @arg RCC_LPTIM23CLKSOURCE_PLL2P PLL2_P selected as LPTIM2/LPTIM3 clock + * @arg RCC_LPTIM23CLKSOURCE_PLL3R PLL3_R selected as LPTIM2/LPTIM3 clock + * @arg RCC_LPTIM23CLKSOURCE_LSE LSE selected as LPTIM2/LPTIM3 clock + * @arg RCC_LPTIM23CLKSOURCE_LSI LSI Clock selected as LPTIM2/LPTIM3 clock + * @arg RCC_LPTIM23CLKSOURCE_CLKP CLKP selected as LPTIM2/LPTIM3 clock + */ +#define __HAL_RCC_LPTIM23_CONFIG(__LPTIM23_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_LPTIM23SEL, (uint32_t)(__LPTIM23_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM2/LPTIM3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM23CLKSOURCE_PCLK4 APB4 clock selected as LPTIM2/LPTIM3 clock + * @arg RCC_LPTIM23CLKSOURCE_PLL2P PLL2_P selected as LPTIM2/LPTIM3 clock + * @arg RCC_LPTIM23CLKSOURCE_PLL3R PLL3_R selected as LPTIM2/LPTIM3 clock + * @arg RCC_LPTIM23CLKSOURCE_LSE LSE selected as LPTIM2/LPTIM3 clock + * @arg RCC_LPTIM23CLKSOURCE_LSI LSI Clock selected as LPTIM2/LPTIM3 clock + * @arg RCC_LPTIM23CLKSOURCE_CLKP CLKP selected as LPTIM2/LPTIM3 clock + */ +#define __HAL_RCC_GET_LPTIM23_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_LPTIM23SEL))) + +/** @brief Macro to configure the LPTIM4/LPTIM5 clock source. + * @param __LPTIM45_CLKSOURCE__ specifies the LPTIM4/LPTIM5 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM45CLKSOURCE_PCLK4 APB4 clock selected as LPTIM4/LPTIM5 clock + * @arg RCC_LPTIM45CLKSOURCE_PLL2P PLL2_P selected as LPTIM4/LPTIM5 clock + * @arg RCC_LPTIM45CLKSOURCE_PLL3R PLL3_R selected as LPTIM4/LPTIM5 clock + * @arg RCC_LPTIM45CLKSOURCE_LSE LSE selected as LPTIM4/LPTIM5 clock + * @arg RCC_LPTIM45CLKSOURCE_LSI LSI Clock selected as LPTIM4/LPTIM5 clock + * @arg RCC_LPTIM45CLKSOURCE_CLKP CLKP selected as LPTIM4/LPTIM5 clock + */ +#define __HAL_RCC_LPTIM45_CONFIG(__LPTIM45_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_LPTIM45SEL, (uint32_t)(__LPTIM45_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM4/LPTIM5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM45CLKSOURCE_PCLK4 APB4 clock selected as LPTIM4/LPTIM5 clock + * @arg RCC_LPTIM45CLKSOURCE_PLL2P PLL2_P selected as LPTIM4/LPTIM5 clock + * @arg RCC_LPTIM45CLKSOURCE_PLL3R PLL3_R selected as LPTIM4/LPTIM5 clock + * @arg RCC_LPTIM45CLKSOURCE_LSE LSE selected as LPTIM4/LPTIM5 clock + * @arg RCC_LPTIM45CLKSOURCE_LSI LSI Clock selected as LPTIM4/LPTIM5 clock + * @arg RCC_LPTIM45CLKSOURCE_CLKP CLKP selected as LPTIM4/LPTIM5 clock + */ +#define __HAL_RCC_GET_LPTIM45_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_LPTIM45SEL))) + +/** @brief Macro to configure the LPUART1 clock (LPUART1CLK). + * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPUART1CLKSOURCE_PCLK4 APB4 Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL2Q PLL2_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL3Q PLL3_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_CSI CSI Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + */ +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) + +/** @brief Macro to get the LPUART1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPUART1CLKSOURCE_PCLK4 APB4 Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL2Q PLL2_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL3Q PLL3_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_CSI CSI Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + */ +#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_LPUART1SEL))) + +/** @brief Macro to get the LTDC clock source. + * @retval The clock source is internally connected to: + * @arg RCC_LTDCCLKSOURCE_PLL3R PLL3_R Clock selected as LTDC clock + */ +#define __HAL_RCC_GET_LTDC_SOURCE() RCC_LTDCCLKSOURCE_PLL3R + +/** @brief Macro to configure the XSPI1 clock source. + * + * @param __XSPI1_CLKSOURCE__ specifies the XSPI1 clock source. + * @arg RCC_XSPI1CLKSOURCE_HCLK HCLK Clock selected as XSPI1 clock + * @arg RCC_XSPI1CLKSOURCE_PLL2S PLL2_S Clock selected as XSPI1 clock + * @arg RCC_XSPI1CLKSOURCE_PLL2T PLL2_T Clock selected as XSPI1 clock + */ +#define __HAL_RCC_XSPI1_CONFIG(__XSPI1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_XSPI1SEL, (uint32_t)(__XSPI1_CLKSOURCE__)) + +/** @brief Macro to get the XSPI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_XSPI1CLKSOURCE_HCLK HCLK Clock selected as XSPI1 clock + * @arg RCC_XSPI1CLKSOURCE_PLL2S PLL2_S Clock selected as XSPI1 clock + * @arg RCC_XSPI1CLKSOURCE_PLL2T PLL2_T Clock selected as XSPI1 clock + * @arg RCC_XSPI1CLKSOURCE_HCLK_DIV4 Recovery Clock selected as XSPI1 clock + */ +#define __HAL_RCC_GET_XSPI1_SOURCE() ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPI1SWP) == RCC_XSPI1CLKSOURCE_HCLK_DIV4) ? \ + RCC_XSPI1CLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_XSPI1SEL)))) + +/** @brief Macro to configure the XSPI2 clock source. + * + * @param __XSPI2_CLKSOURCE__ specifies the XSPI2 clock source. + * @arg RCC_XSPI2CLKSOURCE_HCLK HCLK Clock selected as XSPI2 clock + * @arg RCC_XSPI2CLKSOURCE_PLL2S PLL2_S Clock selected as XSPI2 clock + * @arg RCC_XSPI2CLKSOURCE_PLL2T PLL2_T Clock selected as XSPI2 clock + */ +#define __HAL_RCC_XSPI2_CONFIG(__XSPI2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_XSPI2SEL, (uint32_t)(__XSPI2_CLKSOURCE__)) + +/** @brief Macro to get the XSPI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_XSPI2CLKSOURCE_HCLK HCLK Clock selected as XSPI2 clock + * @arg RCC_XSPI2CLKSOURCE_PLL2S PLL2_S Clock selected as XSPI2 clock + * @arg RCC_XSPI2CLKSOURCE_PLL2T PLL2_T Clock selected as XSPI2 clock + * @arg RCC_XSPI2CLKSOURCE_HCLK_DIV4 Recovery Clock selected as XSPI2 clock + */ +#define __HAL_RCC_GET_XSPI2_SOURCE() ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPI2SWP) == RCC_XSPI2CLKSOURCE_HCLK_DIV4) ? \ + RCC_XSPI2CLKSOURCE_HCLK_DIV4 : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_XSPI2SEL)))) + +/** + * @brief Macro to configure the PSSI clock source. + * @param __PSSI_CLKSOURCE__ defines the PSSI clock source. + * This parameter can be one of the following values: + * @arg RCC_PSSICLKSOURCE_PLL3R PLL3_R selected as PSSI clock + * @arg RCC_PSSICLKSOURCE_CLKP Peripheral clock selected as PSSI clock + * @retval None + */ +#define __HAL_RCC_PSSI_CONFIG(__PSSI_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_PSSISEL, (__PSSI_CLKSOURCE__)) + +/** @brief Macro to get the PSSI clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_PSSICLKSOURCE_PLL3R PLL3_R selected as PSSI clock + * @arg RCC_PSSICLKSOURCE_CLKP Peripheral clock selected as PSSI clock + */ +#define __HAL_RCC_GET_PSSI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_PSSISEL))) + +/** + * @brief Macro to configure the SAI1 clock source. + * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLL1Q PLL1_Q selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_PLL2P PLL2_P selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_PLL3P PLL3_P selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_PIN External I2S_CKIN selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_CLKP Peripheral clock selected as SAI1 clock + * @retval None + */ +#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SAI1SEL, (__SAI1_CLKSOURCE__)) + +/** @brief Macro to get the SAI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLL1Q PLL1_Q selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_PLL2P PLL2_P selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_PLL3P PLL3_P selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_PIN External I2S_CKIN selected as SAI1 clock + * @arg RCC_SAI1CLKSOURCE_CLKP Peripheral clock selected as SAI1 clock + */ +#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SAI1SEL))) + +/** + * @brief Macro to configure the SAI2 clock source. + * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLL1Q PLL1_Q selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_PLL2P PLL2_P selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_PLL3P PLL3_P selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_PIN External I2S_CKIN selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_CLKP Peripheral clock selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_SPDIF SPDIF output clock selected as SAI2 clock + * @retval None + */ +#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SAI2SEL, (__SAI2_CLKSOURCE__)) + +/** @brief Macro to get the SAI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLL1Q PLL1_Q selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_PLL2P PLL2_P selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_PLL3P PLL3_P selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_PIN External I2S_CKIN selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_CLKP Peripheral clock selected as SAI2 clock + * @arg RCC_SAI2CLKSOURCE_SPDIF SPDIF output clock selected as SAI2 clock + */ +#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SAI2SEL))) + + +/** @brief Macro to configure the SDMMC kernel clock source. + * @param __SDMMC12_CLKSOURCE__ specifies clock source for SDMMC + * This parameter can be one of the following values: + * @arg RCC_SDMMC12CLKSOURCE_PLL2S PLL2_S selected as SDMMC kernel clock + * @arg RCC_SDMMC12CLKSOURCE_PLL2T PLL2_R selected as SDMMC kernel clock + */ +#define __HAL_RCC_SDMMC12_CONFIG(__SDMMC12_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SDMMC12SEL, (uint32_t)(__SDMMC12_CLKSOURCE__)) + +/** @brief Macro to get the SDMMC kernel clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SDMMC12CLKSOURCE_PLL2S PLL2_S selected as SDMMC12 kernel clock + * @arg RCC_SDMMC12CLKSOURCE_PLL2T PLL2_R selected as SDMMC12 kernel clock + */ +#define __HAL_RCC_GET_SDMMC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SDMMC12SEL))) + +/** + * @brief Macro to Configure the SPDIFRX clock source. + * @param __SPDIFRX_CLKSOURCE__ defines the SPDIFRX clock source. + * This parameter can be one of the following values: + * @arg RCC_SPDIFRXCLKSOURCE_PLL1Q PLL1_Q selected as SPDIFRX clock + * @arg RCC_SPDIFRXCLKSOURCE_PLL2R PLL2_R selected as SPDIFRX clock + * @arg RCC_SPDIFRXCLKSOURCE_PLL3R PLL3_R selected as SPDIFRX clock + * @arg RCC_SPDIFRXCLKSOURCE_HSI HSI selected as SPDIFRX clock + * @retval None + */ +#define __HAL_RCC_SPDIFRX_CONFIG(__SPDIFRX_CLKSOURCE__ ) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SPDIFRXSEL, (__SPDIFRX_CLKSOURCE__)) + +/** + * @brief Macro to get the SPDIFRX clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPDIFRXCLKSOURCE_PLL1Q PLL1_Q selected as SPDIFRX clock + * @arg RCC_SPDIFRXCLKSOURCE_PLL2R PLL2_R selected as SPDIFRX clock + * @arg RCC_SPDIFRXCLKSOURCE_PLL3R PLL3_R selected as SPDIFRX clock + * @arg RCC_SPDIFRXCLKSOURCE_HSI HSI selected as SPDIFRX clock + * @retval None + */ +#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SPDIFRXSEL))) + +/** + * @brief Macro to configure the SPI1 clock source. + * @param __SPI1_CLKSOURCE__ defines the SPI1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PLL1Q PLL1_Q selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_PLL2P PLL2_P selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_PLL3P PLL3_P selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_PIN External I2S_CKIN selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_CLKP Peripheral clock selected as SPI1 clock + * @retval None + */ +#define __HAL_RCC_SPI1_CONFIG(__SPI1_CLKSOURCE__ ) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI1SEL, (__SPI1_CLKSOURCE__)) + +/** @brief Macro to get the SPI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PLL1Q PLL1_Q selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_PLL2P PLL2_P selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_PLL3P PLL3_P selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_PIN External I2S_CKIN selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_CLKP Peripheral clock selected as SPI1 clock + */ +#define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI1SEL))) + +/** + * @brief Macro to configure the SPI2/SPI3 clock source. + * @param __SPI23_CLKSOURCE__ defines the SPI2/SPI3 clock source. + * This parameter can be one of the following values: + * @arg RCC_SPI23CLKSOURCE_PLL1Q PLL1_Q selected as SPI2/SPI3 clock + * @arg RCC_SPI23CLKSOURCE_PLL2P PLL2_P selected as SPI2/SPI3 clock + * @arg RCC_SPI23CLKSOURCE_PLL3P PLL3_P selected as SPI2/SPI3 clock + * @arg RCC_SPI23CLKSOURCE_PIN External I2S_CKIN selected as SPI2/SPI3 clock + * @arg RCC_SPI23CLKSOURCE_CLKP Peripheral clock selected as SPI2/SPI3 clock + * @retval None + */ +#define __HAL_RCC_SPI23_CONFIG(__SPI23_CLKSOURCE__ ) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SPI23SEL, (__SPI23_CLKSOURCE__)) + +/** @brief Macro to get the SPI2/SPI3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI23CLKSOURCE_PLL1Q PLL1_Q selected as SPI2/SPI3 clock + * @arg RCC_SPI23CLKSOURCE_PLL2P PLL2_P selected as SPI2/SPI3 clock + * @arg RCC_SPI23CLKSOURCE_PLL3P PLL3_P selected as SPI2/SPI3 clock + * @arg RCC_SPI23CLKSOURCE_PIN External I2S_CKIN selected as SPI2/SPI3 clock + * @arg RCC_SPI23CLKSOURCE_CLKP Peripheral clock selected as SPI2/SPI3 clock + */ +#define __HAL_RCC_GET_SPI23_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SPI23SEL))) + +/** + * @brief Macro to configure the SPI4/SPI5 clock source. + * @param __SPI45_CLKSOURCE__ defines the SPI4/SPI5 clock source. + * This parameter can be one of the following values: + * @arg RCC_SPI45CLKSOURCE_PCLK2 APB2 Clock selected as SPI4/SPI5 clock + * @arg RCC_SPI45CLKSOURCE_PLL2Q PLL2_Q selected as SPI4/SPI5 clock + * @arg RCC_SPI45CLKSOURCE_PLL3Q PLL3_Q selected as SPI4/SPI5 clock + * @arg RCC_SPI45CLKSOURCE_HSI HSI selected as SPI4/SPI5 clock + * @arg RCC_SPI45CLKSOURCE_CSI CSI selected as SPI4/SPI5 clock + * @arg RCC_SPI45CLKSOURCE_HSE HSE selected as SPI4/SPI5 clock + * @retval None + */ +#define __HAL_RCC_SPI45_CONFIG(__SPI45_CLKSOURCE__ ) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI45SEL, (__SPI45_CLKSOURCE__)) + +/** @brief Macro to get the SPI4/SPI5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI45CLKSOURCE_PCLK2 APB2 Clock selected as SPI4/SPI5 clock + * @arg RCC_SPI45CLKSOURCE_PLL2Q PLL2_Q selected as SPI4/SPI5 clock + * @arg RCC_SPI45CLKSOURCE_PLL3Q PLL3_Q selected as SPI4/SPI5 clock + * @arg RCC_SPI45CLKSOURCE_HSI HSI selected as SPI4/SPI5 clock + * @arg RCC_SPI45CLKSOURCE_CSI CSI selected as SPI4/SPI5 clock + * @arg RCC_SPI45CLKSOURCE_HSE HSE selected as SPI4/SPI5 clock + */ +#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI45SEL))) + +/** + * @brief Macro to configure the SPI6 clock source. + * @param __SPI6_CLKSOURCE__ defines the SPI6 clock source. + * This parameter can be one of the following values: + * @arg RCC_SPI6CLKSOURCE_PCLK4 APB4 Clock selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_PLL2Q PLL2_Q selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_PLL3Q PLL3_Q selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_HSI HSI selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_CSI CSI selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_HSE HSE selected as SPI6 clock + * @retval None + */ +#define __HAL_RCC_SPI6_CONFIG(__SPI6_CLKSOURCE__ ) \ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SPI6SEL, (__SPI6_CLKSOURCE__)) + +/** @brief Macro to get the SPI6 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI6CLKSOURCE_PCLK4 APB4 Clock selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_PLL2Q PLL2_Q selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_PLL3Q PLL3_Q selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_HSI HSI selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_CSI CSI selected as SPI6 clock + * @arg RCC_SPI6CLKSOURCE_HSE HSE selected as SPI6 clock + */ +#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SPI6SEL))) + +/** @brief Macro to configure the USART1 clock source. + * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART1CLKSOURCE_PCLK2 APB2 Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL2Q PLL2_Q selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL3Q PLL3_Q selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_CSI CSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) + +/** @brief Macro to get the USART1/6/9* /10* clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART1CLKSOURCE_PCLK2 APB2 Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL2Q PLL2_Q selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL3Q PLL3_Q selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_CSI CSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_USART1SEL))) + +/** @brief Macro to configure the USART2/USART3/UART4/UART5/UART7/UART8 clock source. + * @param __USART234578_CLKSOURCE__ specifies the USART2/UART3/UART4/UART5/UART7/UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART234578CLKSOURCE_PCLK1 APB1 Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock + * @arg RCC_USART234578CLKSOURCE_PLL2Q PLL2_Q Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock + * @arg RCC_USART234578CLKSOURCE_PLL3Q PLL3_Q Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock + * @arg RCC_USART234578CLKSOURCE_HSI HSI selected as USART2/USART3/UART4/UART5/UART7/UART8 clock + * @arg RCC_USART234578CLKSOURCE_CSI CSI Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock + * @arg RCC_USART234578CLKSOURCE_LSE LSE selected as USART2/USART3/UART4/UART5/UART7/UART8 clock + */ +#define __HAL_RCC_USART234578_CONFIG(__USART234578_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_UART234578SEL, (uint32_t)(__USART234578_CLKSOURCE__)) + +/** @brief Macro to get the USART2/USART3/UART4/UART5/UART7/UART8 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART234578CLKSOURCE_PCLK1 APB1 Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock + * @arg RCC_USART234578CLKSOURCE_PLL2Q PLL2_Q Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock + * @arg RCC_USART234578CLKSOURCE_PLL3Q PLL3_Q Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock + * @arg RCC_USART234578CLKSOURCE_HSI HSI selected as USART2/USART3/UART4/UART5/UART7/UART8 clock + * @arg RCC_USART234578CLKSOURCE_CSI CSI Clock selected as USART2/USART3/UART4/UART5/UART7/UART8 clock + * @arg RCC_USART234578CLKSOURCE_LSE LSE selected as USART2/USART3/UART4/UART5/UART7/UART8 clock + */ +#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_UART234578SEL))) + +/** @brief Macro to configure the Timers clocks prescalers + * @param __PRESC__ specifies the Timers clocks prescalers selection + * This parameter can be one of the following values: + * @arg RCC_TIMPRES_DISABLE + * The timers kernel clock is equal to: + * - PCLKx_freq, if PCLKx = RCC_APBx_DIV1 + * - 2*PCLKx_freq, otherwise (default after reset) + * @arg RCC_TIMPRES_ENABLE + * The timers kernel clock is equal to: + * - PCLKx_freq, if PCLKx = RCC_APBx_DIV1 + * - 2*PCLKx_freq, if PCLKx = RCC_APBx_DIV2 + * - 4*PCLKx_freq, otherwise + */ +#define __HAL_RCC_TIMCLKPRESCALER_CONFIG(__PRESC__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, (uint32_t)(__PRESC__)) + +/** @brief Macro to get the Timers clocks prescalers + * @retval The parameter can be one of the following values: + * @arg RCC_TIMPRES_DISABLE + * The timers kernel clock is equal to: + * - PCLKx_freq, if PCLKx = RCC_APBx_DIV1 + * - 2*PCLKx_freq, otherwise (default after reset) + * @arg RCC_TIMPRES_ENABLE + * The timers kernel clock is equal to: + * - PCLKx_freq, if PCLKx = RCC_APBx_DIV1 + * - 2*PCLKx_freq, if PCLKx = RCC_APBx_DIV2 + * - 4*PCLKx_freq, otherwise + */ +#define __HAL_RCC_GET_TIMCLKPRESCALER() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE))) + +/** @brief Macro to configure the USBPHYC clock. + * @param __USBPHYC_CLKSOURCE__ specifies the USBPHYC clock source. + * This parameter can be one of the following values: + * @arg RCC_USBPHYCCLKSOURCE_HSE HSE selected as USBPHYC clock + * @arg RCC_USBPHYCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as USBPHYC clock + * @arg RCC_USBPHYCCLKSOURCE_PLL3Q PLL3_Q Clock selected as USBPHYC clock + */ +#define __HAL_RCC_USBPHYC_CONFIG(__USBPHYC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USBPHYCSEL, (uint32_t)(__USBPHYC_CLKSOURCE__)) + +/** @brief Macro to get the USBPHYC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USBPHYCCLKSOURCE_HSE HSE selected as USBPHYC clock + * @arg RCC_USBPHYCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as USBPHYC clock + * @arg RCC_USBPHYCCLKSOURCE_PLL3Q PLL3_Q Clock selected as USBPHYC clock + */ +#define __HAL_RCC_GET_USBPHYC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USBPHYCSEL))) + +/** @brief Macro to configure the USB OTGFS clock. + * @param __USBOTGFS_CLKSOURCE__ specifies the USB OTGFS clock source. + * This parameter can be one of the following values: + * @arg RCC_USBOTGFSCLKSOURCE_HSI48 HSI48 selected as USB OTGFS clock + * @arg RCC_USBOTGFSCLKSOURCE_PLL3Q PLL3_Q Clock selected as USB OTGFS clock + * @arg RCC_USBOTGFSCLKSOURCE_HSE HSI48 selected as USB OTGFS clock + * @arg RCC_USBOTGFSCLKSOURCE_CLK48 USBPHYC CLK48 output selected as USB OTGFS clock + */ +#define __HAL_RCC_USBOTGFS_CONFIG(__USBOTGFS_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_OTGFSSEL, (uint32_t)(__USBOTGFS_CLKSOURCE__)) + +/** @brief Macro to get the USB OTGFS clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USBOTGFSCLKSOURCE_HSI48 HSI48 selected as USB OTGFS clock + * @arg RCC_USBOTGFSCLKSOURCE_PLL3Q PLL3_Q Clock selected as USB OTGFS clock + * @arg RCC_USBOTGFSCLKSOURCE_HSE HSI48 selected as USB OTGFS clock + * @arg RCC_USBOTGFSCLKSOURCE_CLK48 USBPHYC CLK48 output selected as USB OTGFS clock + */ +#define __HAL_RCC_GET_USBOTGFS_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_OTGFSSEL))) + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Line. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Line. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. + * @retval EXTI RCC LSE CSS Line Status. + */ +#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) + +/** + * @brief Clear the RCC LSE CSS EXTI flag. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) + +/** + * @brief Disable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) + +/** @brief Check whether the CRS interrupt has occurred or not. + * @param __INTERRUPT__ specifies the CRS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) + +/** @brief Clear the CRS interrupt pending bits + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt + * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt + * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt + */ +/* CRS IT Error Mask */ +#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF |\ + RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) + +#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ + } \ + } while(0) + +/** + * @brief Check whether the specified CRS flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @retval The new state of _FLAG_ (TRUE or FALSE). + */ +#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the CRS specified FLAG. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR + * @retval None + */ + +/* CRS Flag Error Mask */ +#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF |\ + RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) + +#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__FLAG__)); \ + } \ + } while(0) + +/** @defgroup RCCEx_CRS_Extended_Features CRS Extended Features + * @{ + */ +/** + * @brief Enable the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Disable the oscillator clock for frequency error counter. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Enable the automatic hardware adjustment of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Enable or disable the automatic hardware adjustment of TRIM bits. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after pre-scaling. It is then decreased by one in order to + * reach the expected synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval None + */ +#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); +void HAL_RCCEx_EnableClockProtection(uint32_t ProtectClk); +void HAL_RCCEx_DisableClockProtection(uint32_t ProtectClk); +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); +void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); +void HAL_RCCEx_EnableLSECSS(void); +void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_EnableLSECSS_IT(void); +void HAL_RCCEx_LSECSS_IRQHandler(void); +void HAL_RCCEx_LSECSS_Callback(void); +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +void HAL_RCCEx_CRS_IRQHandler(void); +void HAL_RCCEx_CRS_SyncOkCallback(void); +void HAL_RCCEx_CRS_SyncWarnCallback(void); +void HAL_RCCEx_CRS_ExpectedSyncCallback(void); +void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Macros + * @{ + */ + +/** @defgroup RCCEx_IS_RCC_Definitions Private macros to check input parameters + * @{ + */ + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_XSPI1) == RCC_PERIPHCLK_XSPI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_XSPI2) == RCC_PERIPHCLK_XSPI2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ETH1REF) == RCC_PERIPHCLK_ETH1REF) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ETH1PHY) == RCC_PERIPHCLK_ETH1PHY) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1_I3C1) == RCC_PERIPHCLK_I2C1_I3C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C23) == RCC_PERIPHCLK_I2C23) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM23) == RCC_PERIPHCLK_LPTIM23) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM45) == RCC_PERIPHCLK_LPTIM45) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_PSSI) == RCC_PERIPHCLK_PSSI) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SDMMC12) == RCC_PERIPHCLK_SDMMC12) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SPI23) == RCC_PERIPHCLK_SPI23) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USBPHYC) == RCC_PERIPHCLK_USBPHYC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USBOTGFS) == RCC_PERIPHCLK_USBOTGFS)) + +#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADCCLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_CLKP)) + +#define IS_RCC_ADF1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADF1CLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL3P) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_ADF1CLKSOURCE_HSI)) + +#define IS_RCC_CECCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_CECCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_CECCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_CECCLKSOURCE_CSI)) + +#define IS_RCC_CKPERCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_CLKPSOURCE_HSI) || \ + ((__SOURCE__) == RCC_CLKPSOURCE_CSI) || \ + ((__SOURCE__) == RCC_CLKPSOURCE_HSE)) + +#define IS_RCC_ETH1REFCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ETH1REFCLKSOURCE_PHY) || \ + ((__SOURCE__) == RCC_ETH1REFCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_ETH1REFCLKSOURCE_ETH)) + +#define IS_RCC_ETH1PHYCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ETH1PHYCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_ETH1PHYCLKSOURCE_PLL3S)) + +#define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2P)) + +#define IS_RCC_FMCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_FMCCLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2R) || \ + ((__SOURCE__) == RCC_FMCCLKSOURCE_HSI)) + +#define IS_RCC_I2C1_I3C1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C1_I3C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C1_I3C1CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_I2C1_I3C1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2C1_I3C1CLKSOURCE_CSI)) + +#define IS_RCC_I2C23CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C23CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C23CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_I2C23CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2C23CLKSOURCE_CSI)) + +#define IS_RCC_I3C1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I3C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I3C1CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_I3C1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I3C1CLKSOURCE_CSI)) + +#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_CLKP)) + +#define IS_RCC_LPTIM23CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM23CLKSOURCE_PCLK4) || \ + ((__SOURCE__) == RCC_LPTIM23CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_LPTIM23CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_LPTIM23CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM23CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM23CLKSOURCE_CLKP)) + +#define IS_RCC_LPTIM45CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM45CLKSOURCE_PCLK4) || \ + ((__SOURCE__) == RCC_LPTIM45CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_LPTIM45CLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_LPTIM45CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPTIM45CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM45CLKSOURCE_CLKP)) + +#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK4) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)) + +#define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ + ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL3R) + +#define IS_RCC_XSPI1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_XSPI1CLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_XSPI1CLKSOURCE_PLL2S) || \ + ((__SOURCE__) == RCC_XSPI1CLKSOURCE_PLL2T)) + +#define IS_RCC_XSPI2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_XSPI2CLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_XSPI2CLKSOURCE_PLL2S) || \ + ((__SOURCE__) == RCC_XSPI2CLKSOURCE_PLL2T)) + +#define IS_RCC_PSSICLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_PSSICLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_PSSICLKSOURCE_CLKP)) + +#define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3P) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) + +#define IS_RCC_SAI2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3P) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_SPDIF)) + +#define IS_RCC_SDMMC12CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SDMMC12CLKSOURCE_PLL2S) || \ + ((__SOURCE__) == RCC_SDMMC12CLKSOURCE_PLL2T)) + +#define IS_RCC_SPDIFRXCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPDIFRXCLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_SPDIFRXCLKSOURCE_PLL2R) || \ + ((__SOURCE__) == RCC_SPDIFRXCLKSOURCE_PLL3R) || \ + ((__SOURCE__) == RCC_SPDIFRXCLKSOURCE_HSI)) + +#define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3P) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP)) + +#define IS_RCC_SPI23CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL2P) || \ + ((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL3P) || \ + ((__SOURCE__) == RCC_SPI23CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SPI23CLKSOURCE_CLKP)) + +#define IS_RCC_SPI45CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI45CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE)) + +#define IS_RCC_SPI6CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI6CLKSOURCE_PCLK4) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) + +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) + +#define IS_RCC_USART234578CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART234578CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART234578CLKSOURCE_PLL2Q) || \ + ((__SOURCE__) == RCC_USART234578CLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_USART234578CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART234578CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART234578CLKSOURCE_CSI)) + +#define IS_RCC_USBPHYCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBPHYCCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_USBPHYCCLKSOURCE_HSE_DIV2) || \ + ((__SOURCE__) == RCC_USBPHYCCLKSOURCE_PLL3Q)) + +#define IS_RCC_USBOTGFSCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBOTGFSCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_USBOTGFSCLKSOURCE_PLL3Q) || \ + ((__SOURCE__) == RCC_USBOTGFSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_USBOTGFSCLKSOURCE_CLK48)) + +#define IS_RCC_TIMCLKPRESCALER(__VALUE__) \ + (((__VALUE__) == RCC_TIMPRES_DISABLE) || \ + ((__VALUE__) == RCC_TIMPRES_ENABLE)) + +#define IS_RCC_CLOCKPROTECTION(__CLOCK__) \ + ((((__CLOCK__) & RCC_CLOCKPROTECT_FMC) == RCC_CLOCKPROTECT_FMC) || \ + (((__CLOCK__) & RCC_CLOCKPROTECT_XSPI) == RCC_CLOCKPROTECT_XSPI) || \ + (((__CLOCK__) & ~(RCC_CLOCKPROTECT_FMC | RCC_CLOCKPROTECT_XSPI)) == 0U)) + + +#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB_OTG_FS) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB_OTG_HS) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO)) + +#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) + +#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) + +#define IS_RCC_CRS_RELOADVALUE(__VALUE__) ((__VALUE__) <= CRS_CFGR_RELOAD) + +#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) ((__VALUE__) <= (CRS_CFGR_FELIM >> CRS_CFGR_FELIM_Pos)) + +#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) ((__VALUE__) <= (CRS_CR_TRIM >> CRS_CR_TRIM_Pos)) + +#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ + ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_RCC_EX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rng.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rng.h new file mode 100644 index 00000000000..5f4430947e2 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rng.h @@ -0,0 +1,389 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_rng.h + * @author MCD Application Team + * @brief Header file of RNG HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_RNG_H +#define STM32H7RSxx_HAL_RNG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#if defined (RNG) + +/** @defgroup RNG RNG + * @brief RNG HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RNG_Exported_Types RNG Exported Types + * @{ + */ + +/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition + * @{ + */ +typedef struct +{ + uint32_t ClockErrorDetection; /*!< CED Clock error detection */ +} RNG_InitTypeDef; + +/** + * @} + */ + +/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition + * @{ + */ +typedef enum +{ + HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */ + HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */ + HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */ + HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */ + HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */ + +} HAL_RNG_StateTypeDef; + +/** + * @} + */ + +/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition + * @{ + */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +typedef struct __RNG_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ +{ + RNG_TypeDef *Instance; /*!< Register base address */ + + RNG_InitTypeDef Init; /*!< RNG configuration parameters */ + + HAL_LockTypeDef Lock; /*!< RNG locking object */ + + __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ + + __IO uint32_t ErrorCode; /*!< RNG Error code */ + + uint32_t RandomNumber; /*!< Last Generated RNG Data */ + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */ + void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */ + + void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */ + void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +} RNG_HandleTypeDef; + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +/** + * @brief HAL RNG Callback ID enumeration definition + */ +typedef enum +{ + HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */ + + HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */ + HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */ + +} HAL_RNG_CallbackIDTypeDef; + +/** + * @brief HAL RNG Callback pointer definition + */ +typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */ +typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */ + +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RNG_Exported_Constants RNG Exported Constants + * @{ + */ + +/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition + * @{ + */ +#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */ +#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */ +#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */ +/** + * @} + */ + +/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition + * @{ + */ +#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */ +#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */ +#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */ +/** + * @} + */ + +/** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection + * @{ + */ +#define RNG_CED_ENABLE 0x00000000U /*!< Clock error detection Enabled */ +#define RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection Disabled */ +/** + * @} + */ + +/** @defgroup RNG_Error_Definition RNG Error Definition + * @{ + */ +#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ +#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ +#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ +#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ +#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RNG_Exported_Macros RNG Exported Macros + * @{ + */ + +/** @brief Reset RNG handle state + * @param __HANDLE__ RNG Handle + * @retval None + */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_RNG_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +/** + * @brief Enables the RNG peripheral. + * @param __HANDLE__ RNG Handle + * @retval None + */ +#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN) + +/** + * @brief Disables the RNG peripheral. + * @param __HANDLE__ RNG Handle + * @retval None + */ +#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN) + +/** + * @brief Check the selected RNG flag status. + * @param __HANDLE__ RNG Handle + * @param __FLAG__ RNG flag + * This parameter can be one of the following values: + * @arg RNG_FLAG_DRDY: Data ready + * @arg RNG_FLAG_CECS: Clock error current status + * @arg RNG_FLAG_SECS: Seed error current status + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clears the selected RNG flag status. + * @param __HANDLE__ RNG handle + * @param __FLAG__ RNG flag to clear + * @note WARNING: This is a dummy macro for HAL code alignment, + * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only. + * @retval None + */ +#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */ + +/** + * @brief Enables the RNG interrupts. + * @param __HANDLE__ RNG Handle + * @retval None + */ +#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE) + +/** + * @brief Disables the RNG interrupts. + * @param __HANDLE__ RNG Handle + * @retval None + */ +#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE) + +/** + * @brief Checks whether the specified RNG interrupt has occurred or not. + * @param __HANDLE__ RNG Handle + * @param __INTERRUPT__ specifies the RNG interrupt status flag to check. + * This parameter can be one of the following values: + * @arg RNG_IT_DRDY: Data ready interrupt + * @arg RNG_IT_CEI: Clock error interrupt + * @arg RNG_IT_SEI: Seed error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clear the RNG interrupt status flags. + * @param __HANDLE__ RNG Handle + * @param __INTERRUPT__ specifies the RNG interrupt status flag to clear. + * This parameter can be one of the following values: + * @arg RNG_IT_CEI: Clock error interrupt + * @arg RNG_IT_SEI: Seed error interrupt + * @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY. + * @retval None + */ +#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__)) + +/** + * @} + */ + +/* Include RNG HAL Extended module */ +#include "stm32h7rsxx_hal_rng_ex.h" +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RNG_Exported_Functions RNG Exported Functions + * @{ + */ + +/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions + * @{ + */ +HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng); +HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng); +void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng); +void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng); + +void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); +void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); +void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit); + +/** + * @} + */ + +/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions + * @{ + */ +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RNG_Private_Macros RNG Private Macros + * @{ + */ +#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \ + ((IT) == RNG_IT_SEI)) + +#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \ + ((FLAG) == RNG_FLAG_CECS) || \ + ((FLAG) == RNG_FLAG_SECS)) + +/** + * @brief Verify the RNG Clock Error Detection mode. + * @param __MODE__ RNG Clock Error Detection mode + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_RNG_CED(__MODE__) (((__MODE__) == RNG_CED_ENABLE) || \ + ((__MODE__) == RNG_CED_DISABLE)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RNG_Private_Functions RNG Private functions + * @{ + */ +HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng); +/** + * @} + */ +/** + * @} + */ + +#endif /* RNG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7RSxx_HAL_RNG_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rng_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rng_ex.h new file mode 100644 index 00000000000..58aa18dd11e --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rng_ex.h @@ -0,0 +1,263 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_rng_ex.h + * @author MCD Application Team + * @brief Header file of RNG HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_RNG_EX_H +#define STM32H7RSxx_HAL_RNG_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#if defined(RNG) +#if defined(RNG_CR_CONDRST) + +/** @defgroup RNGEx RNGEx + * @brief RNG Extension HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types + * @{ + */ + +/** + * @brief RNGEx Configuration Structure definition + */ + +typedef struct +{ + uint32_t Config1; /*!< Config1 must be a value between 0 and 0x3F */ + uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ + uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ + uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can + be a value of @ref RNGEx_Clock_Divider_Factor */ + uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a + value of @ref RNGEx_NIST_Compliance */ + uint32_t AutoReset; /*!< automatic reset When a noise source error occurs + value of @ref RNGEx_Auto_Reset */ + uint32_t HealthTest; /*!< RNG health test control must be a value + between 0x0FFCABFF and 0x00005200 */ +} RNG_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants + * @{ + */ + +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal + * programmable divider acting on the incoming RNG clock + * @{ + */ +#define RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */ +#define RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) +/*!< 2 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) +/*!< 4 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) +/*!< 8 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) +/*!< 16 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) +/*!< 32 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) +/*!< 64 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) +/*!< 128 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) +/*!< 256 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) +/*!< 512 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) +/*!< 1024 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) +/*!< 2048 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) +/*!< 4096 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) +/*!< 8192 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) +/*!< 16384 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) +/*!< 32768 RNG clock cycles per internal RNG clock */ +/** + * @} + */ + +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration + * @{ + */ +#define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ +#define RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */ + +/** + * @} + */ +/** @defgroup RNGEx_Auto_Reset Auto Reset configuration + * @{ + */ +#define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/ +#define RNG_ARDIS_DISABLE (RNG_CR_ARDIS) /*!< Disable automatic reset after seed error */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup RNGEx_Private_Types RNGEx Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros + * @{ + */ + +#define IS_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) (((__CLOCK_DIV__) == RNG_CLKDIV_BY_1) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_64) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_128) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_256) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_512) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_1024) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2048) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4096) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8192) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16384) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32768)) + + +#define IS_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == RNG_NIST_COMPLIANT) || \ + ((__NIST_COMPLIANCE__) == RNG_CUSTOM_NIST)) + +#define IS_RNG_CONFIG1(__CONFIG1__) ((__CONFIG1__) <= 0x3FUL) + +#define IS_RNG_CONFIG2(__CONFIG2__) ((__CONFIG2__) <= 0x07UL) + +#define IS_RNG_CONFIG3(__CONFIG3__) ((__CONFIG3__) <= 0xFUL) +#define IS_RNG_ARDIS(__ARDIS__) (((__ARDIS__) == RNG_ARDIS_ENABLE) || \ + ((__ARDIS__) == RNG_ARDIS_DISABLE)) + + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RNGEx_Exported_Functions + * @{ + */ + +/** @addtogroup RNGEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); + +/** + * @} + */ + +/** @addtogroup RNGEx_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RNG_CR_CONDRST */ +#endif /* RNG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7RSxx_HAL_RNG_EX_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rtc.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rtc.h new file mode 100644 index 00000000000..ca63e994c24 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rtc.h @@ -0,0 +1,977 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_rtc.h + * @author MCD Application Team + * @brief Header file of RTC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_RTC_H +#define STM32H7RSxx_HAL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup RTC RTC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Types RTC Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ + +} HAL_RTCStateTypeDef; + +/** + * @brief RTC Configuration Structure definition + */ +typedef struct +{ + uint32_t HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ + + uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ + + uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. + This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ + + uint32_t OutPutRemap; /*!< Specifies the remap for RTC output. + This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */ + + uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. + This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ + + uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. + This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ + + uint32_t OutPutPullUp; /*!< Specifies the RTC Output Pull-Up mode. + This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */ + + uint32_t BinMode; /*!< Specifies the RTC binary mode. + This parameter can be a value of @ref RTCEx_Binary_Mode */ + + uint32_t BinMixBcdU; /*!< Specifies the BCD calendar update if and only if BinMode = RTC_BINARY_MIX. + This parameter can be a value of @ref RTCEx_Binary_mix_BCDU */ +} RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hour. + This parameter must be a number between: + Min_Data = 0 and Max_Data = 12 if the RTC_HOURFORMAT_12 is selected. + This parameter must be a number between: + Min_Data = 0 and Max_Data = 23 if the RTC_HOURFORMAT_24 is selected */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ + + uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. + This field is not used by HAL_RTC_SetTime. + If the free running 32 bit counter is not activated (mode binary none) + - This parameter corresponds to a time unit range + between [0-1] Second with [1 Sec / SecondFraction +1] granularity + else + - This parameter corresponds to the free running 32 bit counter. */ + + uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content + corresponding to Synchronous pre-scaler factor value (PREDIV_S) + This parameter corresponds to a time unit range between [0-1] Second + with [1 Sec / SecondFraction +1] granularity. + This field will be used only by HAL_RTC_GetTime function */ + + uint32_t DayLightSaving; /*!< This interface is deprecated. + To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ + + uint32_t StoreOperation; /*!< This interface is deprecated. + To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ +} RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t Date; /*!< Specifies the RTC Date. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ +} RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. + if Binary mode is RTC_BINARY_ONLY or is RTC_BINARY_MIX + This parameter can be a value of + @ref RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions + else if Binary mode is RTC_BINARY_NONE + This parameter can be a value of + @ref RTC_Alarm_Sub_Seconds_BCD_Masks_Definitions */ + + uint32_t BinaryAutoClr; /*!< Clear synchronously counter (RTC_SSR) on binary alarm. + RTC_ALARMSUBSECONDBIN_AUTOCLR_YES must only be used if Binary mode + is RTC_BINARY_ONLY + This parameter can be a value of + @ref RTCEx_Alarm_Sub_Seconds_binary_Clear_Definitions */ + + uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. + If the Alarm Date is selected, this parameter must be set to a value + in the 1-31 range. + If the Alarm WeekDay is selected, this parameter can be a value of + @ref RTC_WeekDay_Definitions */ + + uint32_t FlagAutoClr; /*!< Specifies the alarm trigger generation. This feature is meaningful + to avoid any RTC software execution after configuration. + This parameter can be a value of @ref RTC_ALARM_Flag_AutoClear_Definitions */ + + uint32_t Alarm; /*!< Specifies the alarm. + This parameter can be a value of @ref RTC_Alarms_Definitions */ +} RTC_AlarmTypeDef; + +/** + * @brief RTC Handle Structure definition + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +typedef struct __RTC_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ +{ + RTC_TypeDef *Instance; /*!< Legacy register base address. Not used anymore, the driver directly uses cmsis base address */ + + RTC_InitTypeDef Init; /*!< RTC required parameters */ + + HAL_LockTypeDef Lock; /*!< RTC locking object */ + + __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ + void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */ + void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */ + void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */ + void (* SSRUEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC SSRU Event callback */ + void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ + void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */ + void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */ + void (* Tamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 4 Event callback */ + void (* Tamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 5 Event callback */ + void (* Tamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 6 Event callback */ + void (* Tamper7EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 7 Event callback */ + void (* Tamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 8 Event callback */ + void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 1 Event callback */ + void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 2 Event callback */ + void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 3 Event callback */ + void (* InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 4 Event callback */ + void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 5 Event callback */ + void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 6 Event callback */ + void (* InternalTamper7EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 7 Event callback */ + void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 8 Event callback */ + void (* InternalTamper9EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 9 Event callback */ + void (* InternalTamper11EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 11 Event callback */ + void (* InternalTamper15EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 15 Event callback */ + void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ + void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ + +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + +} RTC_HandleTypeDef; + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL RTC Callback ID enumeration definition + */ +typedef enum +{ + HAL_RTC_ALARM_A_EVENT_CB_ID = 0U, /*!< RTC Alarm A Event Callback ID */ + HAL_RTC_ALARM_B_EVENT_CB_ID = 1U, /*!< RTC Alarm B Event Callback ID */ + HAL_RTC_TIMESTAMP_EVENT_CB_ID = 2U, /*!< RTC TimeStamp Event Callback ID */ + HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 3U, /*!< RTC WakeUp Timer Event Callback ID */ + HAL_RTC_SSRU_EVENT_CB_ID = 4U, /*!< RTC SSRU Event Callback ID */ + HAL_RTC_TAMPER1_EVENT_CB_ID = 5U, /*!< RTC Tamper 1 Callback ID */ + HAL_RTC_TAMPER2_EVENT_CB_ID = 6U, /*!< RTC Tamper 2 Callback ID */ + HAL_RTC_TAMPER3_EVENT_CB_ID = 7U, /*!< RTC Tamper 3 Callback ID */ + HAL_RTC_TAMPER4_EVENT_CB_ID = 8U, /*!< RTC Tamper 4 Callback ID */ + HAL_RTC_TAMPER5_EVENT_CB_ID = 9U, /*!< RTC Tamper 5 Callback ID */ + HAL_RTC_TAMPER6_EVENT_CB_ID = 10U, /*!< RTC Tamper 6 Callback ID */ + HAL_RTC_TAMPER7_EVENT_CB_ID = 11U, /*!< RTC Tamper 7 Callback ID */ + HAL_RTC_TAMPER8_EVENT_CB_ID = 12U, /*!< RTC Tamper 8 Callback ID */ + HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID = 13U, /*!< RTC Internal Tamper 1 Callback ID */ + HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID = 14U, /*!< RTC Internal Tamper 2 Callback ID */ + HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 15U, /*!< RTC Internal Tamper 3 Callback ID */ + HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID = 16U, /*!< RTC Internal Tamper 4 Callback ID */ + HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 17U, /*!< RTC Internal Tamper 5 Callback ID */ + HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID = 18U, /*!< RTC Internal Tamper 6 Callback ID */ + HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID = 19U, /*!< RTC Internal Tamper 7 Callback ID */ + HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID = 20U, /*!< RTC Internal Tamper 8 Callback ID */ + HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID = 21U, /*!< RTC Internal Tamper 9 Callback ID */ + HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID = 22U, /*!< RTC Internal Tamper 11 Callback ID */ + HAL_RTC_INTERNAL_TAMPER15_EVENT_CB_ID = 23U, /*!< RTC Internal Tamper 15 Callback ID */ + HAL_RTC_MSPINIT_CB_ID = 24U, /*!< RTC Msp Init callback ID */ + HAL_RTC_MSPDEINIT_CB_ID = 25U /*!< RTC Msp DeInit callback ID */ +} HAL_RTC_CallbackIDTypeDef; + +/** + * @brief HAL RTC Callback pointer definition + */ +typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_Exported_Constants RTC Exported Constants + * @{ + */ + +/** @defgroup RTC_Hour_Formats RTC Hour Formats + * @{ + */ +#define RTC_HOURFORMAT_24 0U +#define RTC_HOURFORMAT_12 RTC_CR_FMT +/** + * @} + */ + +/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition + * @{ + */ +#define RTC_OUTPUT_DISABLE 0U +#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0 +#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1 +#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL +#define RTC_OUTPUT_TAMPER RTC_CR_TAMPOE +/** + * @} + */ + +/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions + * @{ + */ +#define RTC_OUTPUT_POLARITY_HIGH 0U +#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL +/** + * @} + */ + +/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT + * @{ + */ +#define RTC_OUTPUT_TYPE_PUSHPULL 0U +#define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE +/** + * @} + */ + +/** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT + * @{ + */ +#define RTC_OUTPUT_PULLUP_NONE 0U +#define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU +/** + * @} + */ + +#if defined(RTC_CR_OUT2EN) +/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap + * @{ + */ +#define RTC_OUTPUT_REMAP_NONE 0U +#define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN +/** + * @} + */ +#endif /* RTC_CR_OUT2EN */ + +/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions + * @{ + */ +#define RTC_HOURFORMAT12_AM 0U +#define RTC_HOURFORMAT12_PM 1U +/** + * @} + */ + +/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions + * @{ + */ +#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H +#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H +#define RTC_DAYLIGHTSAVING_NONE 0U +/** + * @} + */ + +/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions + * @{ + */ +#define RTC_STOREOPERATION_RESET 0U +#define RTC_STOREOPERATION_SET RTC_CR_BKP +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions + * @{ + */ +#define RTC_FORMAT_BIN 0U +#define RTC_FORMAT_BCD 1U +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_MONTH_JANUARY ((uint8_t)0x01U) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U) +#define RTC_MONTH_MARCH ((uint8_t)0x03U) +#define RTC_MONTH_APRIL ((uint8_t)0x04U) +#define RTC_MONTH_MAY ((uint8_t)0x05U) +#define RTC_MONTH_JUNE ((uint8_t)0x06U) +#define RTC_MONTH_JULY ((uint8_t)0x07U) +#define RTC_MONTH_AUGUST ((uint8_t)0x08U) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10U) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12U) + +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions + * @{ + */ +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) + +/** + * @} + */ + +/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions + * @{ + */ +#define RTC_ALARMDATEWEEKDAYSEL_DATE 0U +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL + +/** + * @} + */ + +/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions + * @{ + */ +#define RTC_ALARMMASK_NONE 0U +#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 +#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 +#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 +#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 +#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | RTC_ALARMMASK_HOURS | \ + RTC_ALARMMASK_MINUTES | RTC_ALARMMASK_SECONDS) + +/** + * @} + */ + +/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions + * @{ + */ +#define RTC_ALARM_A RTC_CR_ALRAE +#define RTC_ALARM_B RTC_CR_ALRBE + +/** + * @} + */ +/** @defgroup RTC_ALARM_Flag_AutoClear_Definitions RTC Alarms Flag Auto Clear Definitions + * @{ + */ +#define ALARM_FLAG_AUTOCLR_ENABLE 1U +#define ALARM_FLAG_AUTOCLR_DISABLE 0U +/** + * @} + */ + +/** @defgroup RTC_Alarm_Sub_Seconds_BCD_Masks_Definitions RTC Alarm Sub Seconds BCD Masks Definitions + * In BCD mode (BIN=00) the overflow bits of the synchronous counter (bits 31:15) are never compared. + * @{ + */ +#define RTC_ALARMSUBSECONDMASK_ALL 0U /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ +#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] not used in Alarmcomparison. Only SS[0] is compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] not used in Alarm comparison. Only SS[1:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] not used in Alarm comparison. Only SS[2:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] not used in Alarm comparison. Only SS[3:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:5] not used in Alarm comparison. Only SS[4:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:6] not used in Alarm comparison. Only SS[5:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:7] not used in Alarm comparison. Only SS[6:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] not used in Alarm comparison. Only SS[7:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:9] not used in Alarm comparison. Only SS[8:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:10] not used in Alarm comparison. Only SS[9:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:11] not used in Alarm comparison. Only SS[10:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:12] not used in Alarm comparison.Only SS[11:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:13] not used in Alarm comparison. Only SS[12:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14] not used in Alarm comparison. Only SS[13:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match to activate alarm */ +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions + * @{ + */ +#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */ +#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */ +#define RTC_IT_SSRU RTC_CR_SSRUIE /*!< Enable SSR Underflow Interrupt */ +#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */ +#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */ +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions RTC Flags Definitions + * @{ + */ +#define RTC_FLAG_RECALPF (1U) /*!< Recalibration pending flag */ +#define RTC_FLAG_INITF (2U) /*!< Initialization flag */ +#define RTC_FLAG_RSF (3U) /*!< Registers synchronization flag */ +#define RTC_FLAG_INITS (4U) /*!< Initialization status flag */ +#define RTC_FLAG_SHPF (5U) /*!< Shift operation pending flag */ +#define RTC_FLAG_WUTWF (6U) /*!< Wakeup timer write flag */ +#define RTC_FLAG_SSRUF (7U) /*!< SSR underflow flag */ +#define RTC_FLAG_ITSF (8U) /*!< Internal Time-stamp flag */ +#define RTC_FLAG_TSOVF (9U) /*!< Time-stamp overflow flag */ +#define RTC_FLAG_TSF (10U) /*!< Time-stamp flag */ +#define RTC_FLAG_WUTF (11U) /*!< Wakeup timer flag */ +#define RTC_FLAG_ALRBF (12U) /*!< Alarm B flag */ +#define RTC_FLAG_ALRAF (13U) /*!< Alarm A flag */ +/** + * @} + */ + +/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions + * @{ + */ +#define RTC_CLEAR_SSRUF RTC_SCR_CSSRUF /*!< Clear SSR underflow flag */ +#define RTC_CLEAR_ITSF RTC_SCR_CITSF /*!< Clear Internal Time-stamp flag */ +#define RTC_CLEAR_TSOVF RTC_SCR_CTSOVF /*!< Clear Time-stamp overflow flag */ +#define RTC_CLEAR_TSF RTC_SCR_CTSF /*!< Clear Time-stamp flag */ +#define RTC_CLEAR_WUTF RTC_SCR_CWUTF /*!< Clear Wakeup timer flag */ +#define RTC_CLEAR_ALRBF RTC_SCR_CALRBF /*!< Clear Alarm B flag */ +#define RTC_CLEAR_ALRAF RTC_SCR_CALRAF /*!< Clear Alarm A flag */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RTC_Exported_Macros RTC Exported Macros + * @{ + */ + +/** @brief Reset RTC handle state + * @param __HANDLE__ RTC handle. + * @retval None + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_RTC_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0) +#else +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @brief Disable the write protection for RTC registers. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ + do{ \ + RTC->WPR = 0xCAU; \ + RTC->WPR = 0x53U; \ + } while(0U) + +/** + * @brief Enable the write protection for RTC registers. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ + do{ \ + RTC->WPR = 0xFFU; \ + } while(0U) + +/** + * @brief Add 1 hour (summer time change). + * @note This interface is deprecated. + * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions + * @param __HANDLE__ specifies the RTC handle. + * @param __BKP__ Backup + * This parameter can be: + * @arg @ref RTC_STOREOPERATION_RESET + * @arg @ref RTC_STOREOPERATION_SET + * @retval None + */ +#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__) \ + do { \ + __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ + SET_BIT(RTC->CR, RTC_CR_ADD1H); \ + MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \ + __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ + } while(0); + +/** + * @brief Subtract 1 hour (winter time change). + * @note This interface is deprecated. + * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions + * @param __HANDLE__ specifies the RTC handle. + * @param __BKP__ Backup + * This parameter can be: + * @arg @ref RTC_STOREOPERATION_RESET + * @arg @ref RTC_STOREOPERATION_SET + * @retval None + */ +#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__) \ + do { \ + __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ + SET_BIT(RTC->CR, RTC_CR_SUB1H); \ + MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \ + __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ + } while(0); + +/** + * @brief Enable the RTC ALARMA peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ALRAE)) + +/** + * @brief Disable the RTC ALARMA peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ALRAE)) + +/** + * @brief Enable the RTC ALARMB peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ALRBE)) + +/** + * @brief Disable the RTC ALARMB peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ALRBE)) + +/** + * @brief Enable the RTC Alarm interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ? (SET_BIT(RTC->CR, RTC_CR_ALRAIE)):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ? (SET_BIT(RTC->CR, RTC_CR_ALRBIE)):\ + (0U)) /* Dummy action because is an invalid parameter value */ + +/** + * @brief Disable the RTC Alarm interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ? (CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE)):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ? (CLEAR_BIT(RTC->CR, RTC_CR_ALRBIE)):\ + (0U)) /* Dummy action because is an invalid parameter value */ + +/** + * @brief Check whether the specified RTC Alarm interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ? (READ_BIT(RTC->MISR, RTC_MISR_ALRAMF) == RTC_MISR_ALRAMF):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ? (READ_BIT(RTC->MISR, RTC_MISR_ALRBMF) == RTC_MISR_ALRBMF):\ + (0U)) /* Return 0 because it is an invalid parameter value */ + +/** + * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ? (READ_BIT(RTC->CR, RTC_CR_ALRAIE) == RTC_CR_ALRAIE):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ? (READ_BIT(RTC->CR, RTC_CR_ALRBIE) == RTC_CR_ALRBIE):\ + (0U)) /* Return 0 because it is an invalid parameter value */ + +/** + * @brief Get the selected RTC Alarms flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to check. + * This parameter can be: + * @arg @ref RTC_FLAG_ALRAF + * @arg @ref RTC_FLAG_ALRBF + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_ALRAF) ? (READ_BIT(RTC->SR, RTC_SR_ALRAF) == RTC_SR_ALRAF):\ + ((__FLAG__) == RTC_FLAG_ALRBF) ? (READ_BIT(RTC->SR, RTC_SR_ALRBF) == RTC_SR_ALRBF):\ + (0U)) /* Return 0 because it is an invalid parameter value */ + +/** + * @brief Clear the RTC Alarms pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_ALRAF + * @arg @ref RTC_FLAG_ALRBF + * @retval None + */ +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_ALRAF) ? (WRITE_REG(RTC->SCR, RTC_SCR_CALRAF)):\ + ((__FLAG__) == RTC_FLAG_ALRBF) ? (WRITE_REG(RTC->SCR, RTC_SCR_CALRBF)):\ + (0U)) /* Dummy action because is an invalid parameter value */ + +/** + * @brief Check whether if the RTC Calendar is initialized. + * @param __HANDLE__ specifies the RTC handle. + * @retval The state of RTC Calendar initialization (TRUE or FALSE). + */ +#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS)) + +/** + * @} + */ + +/* Include RTC HAL Extended module */ +#include "stm32h7rsxx_hal_rtc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); + +void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, + pRTC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions + * @{ + */ +/* RTC Time and Date functions ************************************************/ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +void HAL_RTC_DST_Add1Hour(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_Sub1Hour(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTC_DST_ReadStoreOperation(const RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions + * @{ + */ +/* RTC Alarm functions ********************************************************/ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, + uint32_t Format); +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTC_Private_Constants RTC Private Constants + * @{ + */ +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \ + RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \ + RTC_TR_SU) +#define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \ + RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \ + RTC_DR_DU) +#define RTC_INIT_MASK 0xFFFFFFFFU +#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF)) + +#define RTC_TIMEOUT_VALUE 1000U + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RTC_Private_Macros RTC Private Macros + * @{ + */ + +/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters + * @{ + */ +#if defined(RTC_CR_OSEL) +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ + ((OUTPUT) == RTC_OUTPUT_WAKEUP) || \ + ((OUTPUT) == RTC_OUTPUT_TAMPER)) +#endif /* RTC_CR_OSEL */ + +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ + ((FORMAT) == RTC_HOURFORMAT_24)) + +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ + ((POL) == RTC_OUTPUT_POLARITY_LOW)) + +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ + ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) + +#define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \ + ((TYPE) == RTC_OUTPUT_PULLUP_ON)) + +#if defined(RTC_CR_OUT2EN) +#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \ + ((REMAP) == RTC_OUTPUT_REMAP_POS1)) +#endif /* RTC_CR_OUT2EN */ + +#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \ + ((PM) == RTC_HOURFORMAT12_PM)) + +#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ + ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ + ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) + +#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ + ((OPERATION) == RTC_STOREOPERATION_SET)) + +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \ + ((FORMAT) == RTC_FORMAT_BCD)) + +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U) + +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U)) + +#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U)) + +#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U)) + +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ + ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) + +#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0UL) + +#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || \ + ((ALARM) == RTC_ALARM_B)) + +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS) + +#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == 0UL) || \ + (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && \ + ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE))) + +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos)) + +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos)) + +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U)) + +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) + +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U) + +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U) + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------*/ +/** @defgroup RTC_Private_Functions RTC Private Functions + * @{ + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc); +uint8_t RTC_ByteToBcd2(uint8_t Value); +uint8_t RTC_Bcd2ToByte(uint8_t Value); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_RTC_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rtc_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rtc_ex.h new file mode 100644 index 00000000000..8422faeae37 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_rtc_ex.h @@ -0,0 +1,1783 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_rtc_ex.h + * @author MCD Application Team + * @brief Header file of RTC HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_RTC_EX_H +#define STM32H7RSxx_HAL_RTC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup RTCEx RTCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Types RTCEx Exported Types + * @{ + */ + +/** @defgroup RTCEx_Tamper_structure_definition RTCEx Tamper structure definition + * @{ + */ +typedef struct +{ + uint32_t Tamper; /*!< Specifies the Tamper Pin. + This parameter can be a value of @ref RTCEx_Tamper_Pins */ + + uint32_t Trigger; /*!< Specifies the Tamper Trigger. + This parameter can be a value of @ref RTCEx_Tamper_Trigger */ + + uint32_t NoErase; /*!< Specifies the Tamper no erase mode. + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */ + + uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. + This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */ + + uint32_t Filter; /*!< Specifies the TAMP Filter Tamper. + This parameter can be a value of @ref RTCEx_Tamper_Filter */ + + uint32_t SamplingFrequency; /*!< Specifies the sampling frequency. + This parameter can be a value of + @ref RTCEx_Tamper_Sampling_Frequencies */ + + uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration. + This parameter can be a value of + @ref RTCEx_Tamper_Pin_Precharge_Duration */ + + uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp. + This parameter can be a value of @ref RTCEx_Tamper_Pull_UP */ + + uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. + This parameter can be a value of + @ref RTCEx_Tamper_TimeStampOnTamperDetection */ +} RTC_TamperTypeDef; +/** + * @} + */ + + +/** @defgroup RTCEx_Active_Seed_Size Seed size Definitions + * @{ + */ +#define RTC_ATAMP_SEED_NB_UINT32 4U +/** + * @} + */ + + +/** @defgroup RTCEx_ActiveTamper_structures_definition RTCEx Active Tamper structures definitions + * @{ + */ +typedef struct +{ + uint32_t Enable; /*!< Specifies the Tamper input is active. + This parameter can be a value of @ref RTCEx_ActiveTamper_Enable */ + + uint32_t Interrupt; /*!< Specifies the interrupt mode. + This parameter can be a value of @ref RTCEx_ActiveTamper_Interrupt */ + + uint32_t Output; /*!< Specifies the TAMP output to be compared with. + The same output can be used for several tamper inputs. + This parameter can be a value of @ref RTCEx_ActiveTamper_Sel */ + + uint32_t NoErase; /*!< Specifies the Tamper no erase mode. + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */ + + uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. + This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */ + +} RTC_ATampInputTypeDef; + + +typedef struct +{ + uint32_t ActiveFilter; /*!< Specifies the Active tamper filter enable. + This parameter can be a value of @ref RTCEx_ActiveTamper_Filter */ + + uint32_t ActiveAsyncPrescaler; /*!< Specifies the Active Tamper asynchronous Prescaler clock. + This parameter can be a value of + @ref RTCEx_ActiveTamper_Async_prescaler */ + + uint32_t TimeStampOnTamperDetection; /*!< Specifies the timeStamp on tamper detection. + This parameter can be a value of + @ref RTCEx_Tamper_TimeStampOnTamperDetection */ + + uint32_t ActiveOutputChangePeriod; /*!< Specifies the Active Tamper output change period. + This parameter can be a value from 0 to 7 */ + + uint32_t Seed[RTC_ATAMP_SEED_NB_UINT32]; + /*!< Specifies the RNG Seed value. + This parameter is an array of value from 0 to 0xFFFFFFFF */ + + RTC_ATampInputTypeDef TampInput[RTC_TAMP_NB]; + /*!< Specifies configuration of all active tampers. + The index of TampInput[RTC_TAMP_NB] can be a value of RTCEx_ActiveTamper_Sel */ +} RTC_ActiveTampersTypeDef; +/** + * @} + */ + +/** @defgroup RTCEx_Internal_Tamper_structure_definition RTCEx Internal Tamper structure definition + * @{ + */ +typedef struct +{ + uint32_t IntTamper; /*!< Specifies the Internal Tamper Pin. + This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins */ + + uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. + This parameter can be a value of + @ref RTCEx_Tamper_TimeStampOnTamperDetection */ + + uint32_t NoErase; /*!< Specifies the internal Tamper no erase mode. + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */ + +} RTC_InternalTamperTypeDef; +/** + * @} + */ + +/** @defgroup RTCEx_Privilege_State_structure_definition RTCEx Privilege structure definition + * @{ + */ +typedef struct +{ + uint32_t rtcPrivilegeFull; /*!< Specifies If the RTC is fully privileged or not. + This parameter can be a value of @ref RTCEx_RTC_Privilege_Full */ + + uint32_t rtcPrivilegeFeatures; /*!< Specifies the privileged features. + This parameter is only relevant if RTC is not fully privileged + (rtcPrivilegeFull == RTC_PRIVILEGE_FULL_NO). + This parameter can be a combination of + @ref RTCEx_RTC_Privilege_Features */ + + uint32_t tampPrivilegeFull; /*!< Specifies If the TAMP is fully privileged or not execpt monotonic + counters and BackUp registers. + This parameter can be a value of @ref RTCEx_TAMP_Privilege_Full */ + + uint32_t backupRegisterPrivZone; /*!< Specifies backup register zone to be privileged. + This parameter can be a combination of + @ref RTCEx_Backup_Reg_Privilege_zone */ + + uint32_t backupRegisterStartZone2; /*!< Specifies the backup register start zone 2. + Zone 1 : read protection write protection. + Zone 2 : read non-protection write protection. + This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify + the register */ + + uint32_t backupRegisterStartZone3; /*!< Specifies the backup register start zone 3. + Zone 3 : read non-protection write non-protection. + This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify + the register */ + + uint32_t MonotonicCounterPrivilege; /*!< Specifies If the monotonic counter is privileged or not. + This parameter can be a value of + @ref RTCEx_TAMP_Monotonic_Counter_Privilege */ +} RTC_PrivilegeStateTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants + * @{ + */ + +#if defined(RTC_CR_TSEDGE) +/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition + * @{ + */ +#define RTC_TIMESTAMPEDGE_RISING 0U +#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE +/** + * @} + */ +#endif /* RTC_CR_TSEDGE */ + +/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection + * @{ + */ +#define RTC_TIMESTAMPPIN_DEFAULT 0U +/** + * @} + */ + +/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions + * @{ + */ +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0U +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2 +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2) +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions + * @{ + */ +#define RTC_SMOOTHCALIB_PERIOD_32SEC 0U /*!< If RTCCLK = 32768 Hz, Smooth calibration period + is 32s, else 2exp20 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibration period + is 16s, else 2exp19 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibration period + is 8s, else 2exp18 RTCCLK pulses */ +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions + * @{ + */ +#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0] + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0U /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0] */ +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_calib_low_power_Definitions RTCEx Smooth calib Low Power Definitions + * @{ + */ +#define RTC_LPCAL_SET RTC_CALR_LPCAL /*!< Calibration window is 2exp20 ck_apre, which is the required configuration for ultra-low consumption mode. */ +#define RTC_LPCAL_RESET 0U /*!< Calibration window is 2exp20 RTCCLK, which is a high-consumption mode. + This mode should be set only when less + than 32s calibration window is required. */ +/** + * @} + */ + +#if defined(RTC_CR_COSEL) +/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions + * @{ + */ +#define RTC_CALIBOUTPUT_512HZ 0U +#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL +/** + * @} + */ +#endif /* RTC_CR_COSEL */ + +/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions + * @{ + */ +#define RTC_SHIFTADD1S_RESET 0U +#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pins RTCEx Tamper Pins Definition + * @{ + */ +#define RTC_TAMPER_1 TAMP_CR1_TAMP1E +#define RTC_TAMPER_2 TAMP_CR1_TAMP2E +#if (RTC_TAMP_NB == 3U) +#define RTC_TAMPER_3 TAMP_CR1_TAMP3E +#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3 ) +#elif (RTC_TAMP_NB == 8U) +#define RTC_TAMPER_3 TAMP_CR1_TAMP3E +#define RTC_TAMPER_4 TAMP_CR1_TAMP4E +#define RTC_TAMPER_5 TAMP_CR1_TAMP5E +#define RTC_TAMPER_6 TAMP_CR1_TAMP6E +#define RTC_TAMPER_7 TAMP_CR1_TAMP7E +#define RTC_TAMPER_8 TAMP_CR1_TAMP8E +#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 |\ + RTC_TAMPER_3 | RTC_TAMPER_4 |\ + RTC_TAMPER_5 | RTC_TAMPER_6 |\ + RTC_TAMPER_7 | RTC_TAMPER_8 ) +#else +#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2) +#endif /* RTC_TAMP_NB */ +/** + * @} + */ + +/** @defgroup RTCEx_Internal_Tamper_Pins RTCEx Internal Tamper Pins Definition + * @{ + */ +#define RTC_INT_TAMPER_1 TAMP_CR1_ITAMP1E +#define RTC_INT_TAMPER_2 TAMP_CR1_ITAMP2E +#define RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E +#define RTC_INT_TAMPER_4 TAMP_CR1_ITAMP4E +#define RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E +#define RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E +#define RTC_INT_TAMPER_7 TAMP_CR1_ITAMP7E +#define RTC_INT_TAMPER_8 TAMP_CR1_ITAMP8E +#define RTC_INT_TAMPER_9 TAMP_CR1_ITAMP9E +#define RTC_INT_TAMPER_11 TAMP_CR1_ITAMP11E +#define RTC_INT_TAMPER_15 TAMP_CR1_ITAMP15E +#define RTC_INT_TAMPER_ALL (RTC_INT_TAMPER_1 | RTC_INT_TAMPER_2 |\ + RTC_INT_TAMPER_3 | RTC_INT_TAMPER_4 |\ + RTC_INT_TAMPER_5 | RTC_INT_TAMPER_6 |\ + RTC_INT_TAMPER_7 | RTC_INT_TAMPER_8 |\ + RTC_INT_TAMPER_9 | RTC_INT_TAMPER_11 |\ + RTC_INT_TAMPER_15) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Trigger RTCEx Tamper Trigger + * @{ + */ +#define RTC_TAMPERTRIGGER_RISINGEDGE 0U /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_FALLINGEDGE 1U /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_LOWLEVEL 2U /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_HIGHLEVEL 3U /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_MaskFlag RTCEx Tamper MaskFlag + * @{ + */ +#define RTC_TAMPERMASK_FLAG_DISABLE 0U +#define RTC_TAMPERMASK_FLAG_ENABLE 1U +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Maskable_nb RTCEx Tampers maskable number + * @{ + */ +#if (RTC_TAMP_NB == 2U) +#define RTC_TAMPER_MASKABLE_NB 2U +#else +#define RTC_TAMPER_MASKABLE_NB 3U +#endif /* (RTC_TAMP_NB == 2U) */ + +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_EraseBackUp RTCEx Tamper EraseBackUp + * @{ + */ +#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0U +#define RTC_TAMPER_ERASE_BACKUP_DISABLE 1U +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Filter RTCEx Tamper Filter + * @{ + */ +#define RTC_TAMPERFILTER_DISABLE 0U /*!< Tamper filter is disabled */ +#define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ +#define RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ +#define RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Sampling_Frequencies RTCEx Tamper Sampling Frequencies + * @{ + */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1 | \ + TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration RTCEx Tamper Pin Precharge Duration + * @{ + */ +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1) /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pull_UP RTCEx Tamper Pull UP + * @{ + */ +#define RTC_TAMPER_PULLUP_ENABLE 0U /*!< Tamper pins are pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection RTCEx Tamper TimeStamp On Tamper Detection Definitions + * @{ + */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0U /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Detection_Output RTCEx Tamper detection output Definitions + * @{ + */ +#if defined(RTC_CR_TAMPOE) +#define RTC_TAMPERDETECTIONOUTPUT_DISABLE 0U /*!< Tamper detection output disable on TAMPALRM */ +#define RTC_TAMPERDETECTIONOUTPUT_ENABLE RTC_CR_TAMPOE /*!< Tamper detection output enable on TAMPALRM */ +#endif /* RTC_CR_TAMPOE */ +/** + * @} + */ + + +/** @defgroup RTCEx_Tamper_Interrupt RTCEx Tamper Interrupt + * @{ + */ +#define RTC_IT_TAMP_1 TAMP_IER_TAMP1IE /*!< Tamper 1 Interrupt */ +#define RTC_IT_TAMP_2 TAMP_IER_TAMP2IE /*!< Tamper 2 Interrupt */ +#if (RTC_TAMP_NB == 3U) +#define RTC_IT_TAMP_3 TAMP_IER_TAMP3IE /*!< Tamper 3 Interrupt */ +#define RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 | RTC_IT_TAMP_3) +#elif (RTC_TAMP_NB == 8U) +#define RTC_IT_TAMP_3 TAMP_IER_TAMP3IE /*!< Tamper 3 Interrupt */ +#define RTC_IT_TAMP_4 TAMP_IER_TAMP4IE /*!< Tamper 4 Interrupt */ +#define RTC_IT_TAMP_5 TAMP_IER_TAMP5IE /*!< Tamper 5 Interrupt */ +#define RTC_IT_TAMP_6 TAMP_IER_TAMP6IE /*!< Tamper 6 Interrupt */ +#define RTC_IT_TAMP_7 TAMP_IER_TAMP7IE /*!< Tamper 7 Interrupt */ +#define RTC_IT_TAMP_8 TAMP_IER_TAMP8IE /*!< Tamper 8 Interrupt */ +#define RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 |\ + RTC_IT_TAMP_3 | RTC_IT_TAMP_4 |\ + RTC_IT_TAMP_5 | RTC_IT_TAMP_6 |\ + RTC_IT_TAMP_7 | RTC_IT_TAMP_8 ) +#else +#define RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2) +#endif /* RTC_TAMP_NB */ +/** + * @} + */ + +/** @defgroup RTCEx_Internal_Tamper_Interrupt RTCEx Internal Tamper Interrupt + * @{ + */ +#define RTC_IT_INT_TAMP_1 TAMP_IER_ITAMP1IE /*!< Tamper 1 internal Interrupt */ +#define RTC_IT_INT_TAMP_2 TAMP_IER_ITAMP2IE /*!< Tamper 2 internal Interrupt */ +#define RTC_IT_INT_TAMP_3 TAMP_IER_ITAMP3IE /*!< Tamper 3 internal Interrupt */ +#define RTC_IT_INT_TAMP_4 TAMP_IER_ITAMP4IE /*!< Tamper 4 internal Interrupt */ +#define RTC_IT_INT_TAMP_5 TAMP_IER_ITAMP5IE /*!< Tamper 5 internal Interrupt */ +#define RTC_IT_INT_TAMP_6 TAMP_IER_ITAMP6IE /*!< Tamper 6 internal Interrupt */ +#define RTC_IT_INT_TAMP_7 TAMP_IER_ITAMP7IE /*!< Tamper 7 internal Interrupt */ +#define RTC_IT_INT_TAMP_8 TAMP_IER_ITAMP8IE /*!< Tamper 8 internal Interrupt */ +#define RTC_IT_INT_TAMP_9 TAMP_IER_ITAMP9IE /*!< Tamper 9 internal Interrupt */ +#define RTC_IT_INT_TAMP_11 TAMP_IER_ITAMP11IE /*!< Tamper 11 internal Interrupt */ +#define RTC_IT_INT_TAMP_15 TAMP_IER_ITAMP15IE /*!< Tamper 15 internal Interrupt */ + +#define RTC_IT_INT_TAMP_ALL (RTC_IT_INT_TAMP_1 | RTC_IT_INT_TAMP_2 |\ + RTC_IT_INT_TAMP_3 | RTC_IT_INT_TAMP_4 |\ + RTC_IT_INT_TAMP_5 | RTC_IT_INT_TAMP_6 |\ + RTC_IT_INT_TAMP_7 | RTC_IT_INT_TAMP_8 |\ + RTC_IT_INT_TAMP_9 | RTC_IT_INT_TAMP_11 |\ + RTC_IT_INT_TAMP_15) +/** + * @} + */ + +/** @defgroup RTCEx_Flags RTCEx Flags + * @{ + */ +#define RTC_FLAG_TAMP_1 TAMP_SR_TAMP1F +#define RTC_FLAG_TAMP_2 TAMP_SR_TAMP2F +#if (RTC_TAMP_NB == 3U) +#define RTC_FLAG_TAMP_3 TAMP_SR_TAMP3F +#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3 ) +#elif (RTC_TAMP_NB == 8U) +#define RTC_FLAG_TAMP_3 TAMP_SR_TAMP3F +#define RTC_FLAG_TAMP_4 TAMP_SR_TAMP4F +#define RTC_FLAG_TAMP_5 TAMP_SR_TAMP5F +#define RTC_FLAG_TAMP_6 TAMP_SR_TAMP6F +#define RTC_FLAG_TAMP_7 TAMP_SR_TAMP7F +#define RTC_FLAG_TAMP_8 TAMP_SR_TAMP8F +#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3 |\ + RTC_FLAG_TAMP_4 | RTC_FLAG_TAMP_5 | RTC_FLAG_TAMP_6 |\ + RTC_FLAG_TAMP_7 | RTC_FLAG_TAMP_8) +#else +#define RTC_FLAG_TAMP_ALL (TAMP_SR_TAMP1F | TAMP_SR_TAMP2F) +#endif /* RTC_TAMP_NB */ + +#define RTC_FLAG_INT_TAMP_1 TAMP_SR_ITAMP1F +#define RTC_FLAG_INT_TAMP_2 TAMP_SR_ITAMP2F +#define RTC_FLAG_INT_TAMP_3 TAMP_SR_ITAMP3F +#define RTC_FLAG_INT_TAMP_4 TAMP_SR_ITAMP4F +#define RTC_FLAG_INT_TAMP_5 TAMP_SR_ITAMP5F +#define RTC_FLAG_INT_TAMP_6 TAMP_SR_ITAMP6F +#define RTC_FLAG_INT_TAMP_7 TAMP_SR_ITAMP7F +#define RTC_FLAG_INT_TAMP_8 TAMP_SR_ITAMP8F +#define RTC_FLAG_INT_TAMP_9 TAMP_SR_ITAMP9F +#define RTC_FLAG_INT_TAMP_11 TAMP_SR_ITAMP11F +#define RTC_FLAG_INT_TAMP_15 TAMP_SR_ITAMP15F +#define RTC_FLAG_INT_TAMP_ALL (RTC_FLAG_INT_TAMP_1 | RTC_FLAG_INT_TAMP_2 |\ + RTC_FLAG_INT_TAMP_3 | RTC_FLAG_INT_TAMP_4 |\ + RTC_FLAG_INT_TAMP_5 | RTC_FLAG_INT_TAMP_6 |\ + RTC_FLAG_INT_TAMP_7 | RTC_FLAG_INT_TAMP_8 |\ + RTC_FLAG_INT_TAMP_9 | RTC_FLAG_INT_TAMP_11 |\ + RTC_FLAG_INT_TAMP_15) +/** + * @} + */ + + +/** @defgroup RTCEx_ActiveTamper_Enable RTCEx_ActiveTamper_Enable Definitions + * @{ + */ +#define RTC_ATAMP_ENABLE 1U +#define RTC_ATAMP_DISABLE 0U +/** + * @} + */ + +/** @defgroup RTCEx_ActiveTamper_Interrupt RTCEx_ActiveTamper_Interrupt Definitions + * @{ + */ +#define RTC_ATAMP_INTERRUPT_ENABLE 1U +#define RTC_ATAMP_INTERRUPT_DISABLE 0U +/** + * @} + */ + +/** @defgroup RTCEx_ActiveTamper_Filter RTCEx_ActiveTamper_Filter Definitions + * @{ + */ +#define RTC_ATAMP_FILTER_ENABLE TAMP_ATCR1_FLTEN +#define RTC_ATAMP_FILTER_DISABLE 0U +/** + * @} + */ + +/** @defgroup RTCEx_ActiveTamper_Async_prescaler RTCEx Active_Tamper_Asynchronous_Prescaler clock Definitions + * @{ + */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK 0U /*!< RTCCLK */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_2048 (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/2048 */ +/** + * @} + */ + +/** @defgroup RTCEx_ActiveTamper_Sel RTCEx Active Tamper selection Definition + * @{ + */ +#define RTC_ATAMP_1 0U /*!< Tamper 1 */ +#define RTC_ATAMP_2 1U /*!< Tamper 2 */ +#define RTC_ATAMP_3 2U /*!< Tamper 3 */ +#define RTC_ATAMP_4 3U /*!< Tamper 4 */ +#define RTC_ATAMP_5 4U /*!< Tamper 5 */ +#define RTC_ATAMP_6 5U /*!< Tamper 6 */ +#define RTC_ATAMP_7 6U /*!< Tamper 7 */ +#define RTC_ATAMP_8 7U /*!< Tamper 8 */ +/** + * @} + */ + +/** @defgroup RTCEx_MonotonicCounter_Instance RTCEx Monotonic Counter Instance Definition + * @{ + */ +#define RTC_MONOTONIC_COUNTER_1 0U /*!< Monotonic counter 1 */ +/** + * @} + */ + +/** @defgroup RTCEx_Backup_Registers RTCEx Backup Registers Definition + * @{ + */ +#define RTC_BKP_NUMBER RTC_BKP_NB +#define RTC_BKP_DR0 0x00U +#define RTC_BKP_DR1 0x01U +#define RTC_BKP_DR2 0x02U +#define RTC_BKP_DR3 0x03U +#define RTC_BKP_DR4 0x04U +#define RTC_BKP_DR5 0x05U +#define RTC_BKP_DR6 0x06U +#define RTC_BKP_DR7 0x07U +#define RTC_BKP_DR8 0x08U +#define RTC_BKP_DR9 0x09U +#define RTC_BKP_DR10 0x0AU +#define RTC_BKP_DR11 0x0BU +#define RTC_BKP_DR12 0x0CU +#define RTC_BKP_DR13 0x0DU +#define RTC_BKP_DR14 0x0EU +#define RTC_BKP_DR15 0x0FU +#define RTC_BKP_DR16 0x10U +#define RTC_BKP_DR17 0x11U +#define RTC_BKP_DR18 0x12U +#define RTC_BKP_DR19 0x13U +#define RTC_BKP_DR20 0x14U +#define RTC_BKP_DR21 0x15U +#define RTC_BKP_DR22 0x16U +#define RTC_BKP_DR23 0x17U +#define RTC_BKP_DR24 0x18U +#define RTC_BKP_DR25 0x19U +#define RTC_BKP_DR26 0x1AU +#define RTC_BKP_DR27 0x1BU +#define RTC_BKP_DR28 0x1CU +#define RTC_BKP_DR29 0x1DU +#define RTC_BKP_DR30 0x1EU +#define RTC_BKP_DR31 0x1FU +/** + * @} + */ + +/** @defgroup RTCEx_Binary_Mode RTC Binary Mode (32-bit free-running counter configuration). + * Warning : It Should not be confused with the Binary format @ref RTC_Input_parameter_format_definitions. + * @{ + */ +#define RTC_BINARY_NONE 0U /*!< Free running BCD calendar mode (Binary mode disabled) */ +#define RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */ +#define RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary modes */ +/** + * @} + */ + +/** @defgroup RTCEx_Binary_mix_BCDU If Binary mode is RTC_BINARY_MIX, the BCD calendar second is incremented + * using the SSR Least Significant Bits. + * @{ + */ +#define RTC_BINARY_MIX_BCDU_0 0U /*!< The 1s BCD calendar increment is generated each time SS[7:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[8:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[9:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[10:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[11:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[12:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[13:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[14:0] = 0 */ +/** + * @} + */ + +/** @defgroup RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions RTC Alarm Sub Seconds with binary or mix mode + * Masks Definitions. + * @{ + */ +#define RTC_ALARMSUBSECONDBINMASK_ALL 0U /*!< All Alarm SS fields are masked.There is no comparison on sub seconds for Alarm */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_1 (1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:1] are don't care in Alarm comparison. Only SS[0] is compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_2 (2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:2] are don't care in Alarm comparison. Only SS[1:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_3 (3UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:3] are don't care in Alarm comparison. Only SS[2:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_4 (4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:4] are don't care in Alarm comparison. Only SS[3:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_5 (5UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:5] are don't care in Alarm comparison. Only SS[4:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_6 (6UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:6] are don't care in Alarm comparison. Only SS[5:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_7 (7UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:7] are don't care in Alarm comparison. Only SS[6:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_8 (8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:8] are don't care in Alarm comparison. Only SS[7:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_9 (9UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:9] are don't care in Alarm comparison. Only SS[8:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_10 (10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:10] are don't care in Alarm comparison. Only SS[9:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_11 (11UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:11] are don't care in Alarm comparison. Only SS[10:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_12 (12UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:12] are don't care in Alarm comparison.Only SS[11:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_13 (13UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:13] are don't care in Alarm comparison. Only SS[12:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_14 (14UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:14] are don't care in Alarm comparison. Only SS[13:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_15 (15UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:15] are don't care in Alarm comparison. Only SS[14:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_16 (16UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:16] are don't care in Alarm comparison. Only SS[15:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_17 (17UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:17] are don't care in Alarm comparison. Only SS[16:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_18 (18UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:18] are don't care in Alarm comparison. Only SS[17:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_19 (19UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:19] are don't care in Alarm comparison. Only SS[18:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_20 (20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:20] are don't care in Alarm comparison. Only SS[19:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_21 (21UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:21] are don't care in Alarm comparison. Only SS[20:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_22 (22UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:22] are don't care in Alarm comparison. Only SS[21:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_23 (23UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:23] are don't care in Alarm comparison. Only SS[22:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_24 (24UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:24] are don't care in Alarm comparison. Only SS[23:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_25 (25UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:25] are don't care in Alarm comparison. Only SS[24:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_26 (26UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:26] are don't care in Alarm comparison. Only SS[25:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_27 (27UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:27] are don't care in Alarm comparison. Only SS[26:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_28 (28UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:28] are don't care in Alarm comparison. Only SS[27:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_29 (29UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:29] are don't care in Alarm comparison. Only SS[28:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_30 (30UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:30] are don't care in Alarm comparison. Only SS[29:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31 (31UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31] is don't care in Alarm comparison. Only SS[30:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[31:0] are compared and must match to activate alarm */ +/** + * @} + */ + +/** @defgroup RTCEx_Alarm_Sub_Seconds_binary_Clear_Definitions RTC Alarm Sub Seconds + * with binary mode auto clear Definitions + * @{ + */ +#define RTC_ALARMSUBSECONDBIN_AUTOCLR_NO 0UL /*!< The synchronous Binary counter(SS[31:0] in RTC_SSR) is free-running */ +#define RTC_ALARMSUBSECONDBIN_AUTOCLR_YES RTC_ALRMASSR_SSCLR +/*!< The synchronous Binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR -> SS[31:0] + value and is automatically reloaded with 0xFFFF FFFF whenreaching RTC_ALRMABINR -> SS[31:0]. */ +/** + * @} + */ + +/** @defgroup RTCEx_RTC_Privilege_Full RTCEx Privilege Full Definition + * @{ + */ +#define RTC_PRIVILEGE_FULL_YES RTC_PRIVCFGR_PRIV +#define RTC_PRIVILEGE_FULL_NO 0U +/** + * @} + */ + +/** @defgroup RTCEx_RTC_Privilege_Features RTCEx Privilege Features Definition + * @{ + */ +#define RTC_PRIVILEGE_FEATURE_NONE 0U +#define RTC_PRIVILEGE_FEATURE_INIT RTC_PRIVCFGR_INITPRIV /*!< Initialization */ +#define RTC_PRIVILEGE_FEATURE_CAL RTC_PRIVCFGR_CALPRIV /*!< Calibration */ +#define RTC_PRIVILEGE_FEATURE_TS RTC_PRIVCFGR_TSPRIV /*!< Time stamp */ +#define RTC_PRIVILEGE_FEATURE_WUT RTC_PRIVCFGR_WUTPRIV /*!< Wake up timer */ +#define RTC_PRIVILEGE_FEATURE_ALRA RTC_PRIVCFGR_ALRAPRIV /*!< Alarm A */ +#define RTC_PRIVILEGE_FEATURE_ALRB RTC_PRIVCFGR_ALRBPRIV /*!< Alarm B */ + +#define RTC_PRIVILEGE_FEATURE_ALL (RTC_PRIVCFGR_INITPRIV | RTC_PRIVCFGR_CALPRIV | \ + RTC_PRIVCFGR_TSPRIV | RTC_PRIVCFGR_WUTPRIV | \ + RTC_PRIVCFGR_ALRAPRIV | RTC_PRIVCFGR_ALRBPRIV) +/** + * @} + */ + +/** @defgroup RTCEx_TAMP_Privilege_Full RTCEx TAMP security Definition + * @{ + */ +#define TAMP_PRIVILEGE_FULL_YES TAMP_PRIVCFGR_TAMPPRIV +#define TAMP_PRIVILEGE_FULL_NO 0U +/** + * @} + */ + +/** @defgroup RTCEx_TAMP_Device_Secrets_Erase_Conf RTCEx TAMP Device Secrets Erase Configuration Definition + * @{ + */ +#define TAMP_DEVICESECRETS_ERASE_NONE 0U /*!< No Erase */ +#define TAMP_DEVICESECRETS_ERASE_BKPSRAM TAMP_RPCFGR_RPCFG0 /*!< Backup SRAM */ +/** + * @} + */ + +/** @defgroup RTCEx_TAMP_Monotonic_Counter_Privilege RTCEx TAMP Monotonic Counter Privilege Definition + * @{ + */ +#define TAMP_MONOTONIC_CNT_PRIVILEGE_YES TAMP_PRIVCFGR_CNT1PRIV +#define TAMP_MONOTONIC_CNT_PRIVILEGE_NO 0U +/** + * @} + */ + +/** @defgroup RTCEx_Backup_Reg_Privilege_zone RTCEx Privilege Backup register privilege zone Definition + * @{ + */ +#define RTC_PRIVILEGE_BKUP_ZONE_NONE 0U +#define RTC_PRIVILEGE_BKUP_ZONE_1 TAMP_PRIVCFGR_BKPRWPRIV +#define RTC_PRIVILEGE_BKUP_ZONE_2 TAMP_PRIVCFGR_BKPWPRIV +#define RTC_PRIVILEGE_BKUP_ZONE_ALL (RTC_PRIVILEGE_BKUP_ZONE_1 | RTC_PRIVILEGE_BKUP_ZONE_2) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros + * @{ + */ + +/** @brief Clear the specified RTC pending flag. + * @param __HANDLE__ specifies the RTC Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref RTC_CLEAR_SSRUF Clear SSR underflow flag + * @arg @ref RTC_CLEAR_ITSF Clear Internal Time-stamp flag + * @arg @ref RTC_CLEAR_TSOVF Clear Time-stamp overflow flag + * @arg @ref RTC_CLEAR_TSF Clear Time-stamp flag + * @arg @ref RTC_CLEAR_WUTF Clear Wakeup timer flag + * @arg @ref RTC_CLEAR_ALRBF Clear Alarm B flag + * @arg @ref RTC_CLEAR_ALRAF Clear Alarm A flag + * @retval None + */ +#define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) (RTC->SCR = (__FLAG__)) + +/** @brief Check whether the specified RTC flag is set or not. + * @param __HANDLE__ specifies the RTC Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref RTC_FLAG_RECALPF Recalibration pending Flag + * @arg @ref RTC_FLAG_INITF Initialization flag + * @arg @ref RTC_FLAG_RSF Registers synchronization flag + * @arg @ref RTC_FLAG_INITS Initialization status flag + * @arg @ref RTC_FLAG_SHPF Shift operation pending flag + * @arg @ref RTC_FLAG_WUTWF Wakeup timer write flag + * @arg @ref RTC_FLAG_ITSF Internal Time-stamp flag + * @arg @ref RTC_FLAG_TSOVF Time-stamp overflow flag + * @arg @ref RTC_FLAG_TSF Time-stamp flag + * @arg @ref RTC_FLAG_WUTF Wakeup timer flag + * @arg @ref RTC_FLAG_ALRBF Alarm B flag + * @arg @ref RTC_FLAG_ALRAF Alarm A flag + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_RECALPF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) == \ + RTC_ICSR_RECALPF) : \ + ((__FLAG__) == RTC_FLAG_INITF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == \ + RTC_ICSR_INITF) : \ + ((__FLAG__) == RTC_FLAG_RSF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == \ + RTC_ICSR_RSF) : \ + ((__FLAG__) == RTC_FLAG_INITS) ? (READ_BIT(RTC->ICSR, RTC_ICSR_INITS) == \ + RTC_ICSR_INITS) : \ + ((__FLAG__) == RTC_FLAG_SHPF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) == \ + RTC_ICSR_SHPF) : \ + ((__FLAG__) == RTC_FLAG_WUTWF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == \ + RTC_ICSR_WUTWF) : \ + ((__FLAG__) == RTC_FLAG_SSRUF) ? (READ_BIT(RTC->SR, RTC_SR_SSRUF) == \ + RTC_SR_SSRUF) : \ + ((__FLAG__) == RTC_FLAG_ITSF) ? (READ_BIT(RTC->SR, RTC_SR_ITSF) == \ + RTC_SR_ITSF) : \ + ((__FLAG__) == RTC_FLAG_TSOVF) ? (READ_BIT(RTC->SR, RTC_SR_TSOVF) == \ + RTC_SR_TSOVF) : \ + ((__FLAG__) == RTC_FLAG_TSF) ? (READ_BIT(RTC->SR, RTC_SR_TSF) == \ + RTC_SR_TSF): \ + ((__FLAG__) == RTC_FLAG_WUTF) ? (READ_BIT(RTC->SR, RTC_SR_WUTF) == \ + RTC_SR_WUTF): \ + ((__FLAG__) == RTC_FLAG_ALRBF) ? (READ_BIT(RTC->SR, RTC_SR_ALRBF) == \ + RTC_SR_ALRBF) : \ + ((__FLAG__) == RTC_FLAG_ALRAF) ? (READ_BIT(RTC->SR, RTC_SR_ALRAF) == \ + RTC_SR_ALRAF) : \ + (0U)) /* Return 0 because it is an invalid parameter value */ + +/* ---------------------------------WAKEUPTIMER---------------------------------*/ +/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer + * @{ + */ + +/** + * @brief Enable the RTC WakeUp Timer peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_WUTE)) + +/** + * @brief Disable the RTC WakeUp Timer peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_WUTE)) + +/** + * @brief Enable the RTC WakeUpTimer interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_WUTIE)) + +/** + * @brief Disable the RTC WakeUpTimer interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_WUTIE)) + +/** + * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & (RTC_MISR_WUTMF)) != 0U) + +/** + * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((RTC->CR) & (RTC_CR_WUTIE)) != 0U) + +/** + * @brief Get the selected RTC WakeUpTimers flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_WUTF + * @arg @ref RTC_FLAG_WUTWF + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_WUTF) ? (READ_BIT(RTC->SR, RTC_SR_WUTF) == RTC_SR_WUTF):\ + ((__FLAG__) == RTC_FLAG_WUTWF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == RTC_ICSR_WUTWF):\ + (0U)) /* Return 0 because it is an invalid parameter value */ + +/** + * @brief Clear the RTC Wake Up timers pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_WUTF + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG(RTC->SCR, RTC_SCR_CWUTF)) + +/** + * @} + */ + +/* ---------------------------------TIMESTAMP---------------------------------*/ +/** @defgroup RTCEx_Timestamp RTC Timestamp + * @{ + */ + +/** + * @brief Enable the RTC TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TSE)) + +/** + * @brief Disable the RTC TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TSE)) + +/** + * @brief Enable the RTC TimeStamp interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_TSIE)) + +/** + * @brief Disable the RTC TimeStamp interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_TSIE)) + +/** + * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & (RTC_MISR_TSMF)) != 0U) + +/** + * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((RTC->CR) & (RTC_CR_TSIE)) != 0U) + +/** + * @brief Get the selected RTC TimeStamps flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_TSF + * @arg @ref RTC_FLAG_TSOVF + * @retval The state of __FLAG__ (TRUE or FALSE) or 255 if invalid parameter. + */ +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_TSF) ? (READ_BIT(RTC->SR, RTC_SR_TSF) == RTC_SR_TSF):\ + ((__FLAG__) == RTC_FLAG_TSOVF) ? (READ_BIT(RTC->SR, RTC_SR_TSOVF) == RTC_SR_TSOVF):\ + (0U)) /* Return 0 because it is an invalid parameter value */ + +/** + * @brief Clear the RTC Time Stamps pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_TSF + * @arg @ref RTC_FLAG_TSOVF + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_TSF) ? (WRITE_REG(RTC->SCR, RTC_SCR_CTSF)):\ + ((__FLAG__) == RTC_FLAG_TSOVF) ? (WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF)):\ + (0U)) /* Dummy action because is an invalid parameter value */ + +/** + * @brief Enable the RTC internal TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ITSE)) + +/** + * @brief Disable the RTC internal TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ITSE)) + +/** + * @brief Get the selected RTC Internal Time Stamps flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_ITSF + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->SR, RTC_SR_ITSF) == RTC_SR_ITSF)) + +/** + * @brief Clear the RTC Internal Time Stamps pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_ITSF + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG(RTC->SCR, RTC_SCR_CITSF)) + +/** + * @brief Enable the RTC TimeStamp on Tamper detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TAMPTS)) + +/** + * @brief Disable the RTC TimeStamp on Tamper detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TAMPTS)) + +#if defined(RTC_CR_TAMPOE) +/** + * @brief Enable the RTC Tamper detection output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TAMPOE)) + +/** + * @brief Disable the RTC Tamper detection output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TAMPOE)) + +#endif /* RTC_CR_TAMPOE */ +/** + * @} + */ + + +/* ------------------------------Calibration----------------------------------*/ +/** @defgroup RTCEx_Calibration RTC Calibration + * @{ + */ + +/** + * @brief Enable the RTC calibration output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_COE)) + +/** + * @brief Disable the calibration output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_COE)) + +/** + * @brief Enable the clock reference detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_REFCKON)) + +/** + * @brief Disable the clock reference detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_REFCKON)) + +/** + * @brief Get the selected RTC shift operations flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_SHPF + * @retval The state of __FLAG__ (TRUE or FALSE) + */ +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) == RTC_ICSR_SHPF)) +/** + * @} + */ + +/* ------------------------------Tamper----------------------------------*/ +/** @defgroup RTCEx_Tamper RTCEx tamper + * @{ + */ + +/** + * @brief Enable the TAMP Tamper input detection. + * @param __HANDLE__ specifies the RTC handle. + * @param __TAMPER__ specifies the RTC Tamper source to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_ALL: All tampers + * @arg RTC_TAMPER_1: Tamper1 + * @arg RTC_TAMPER_2: Tamper2 + * @arg RTC_TAMPER_3: Tamper3 + * @arg RTC_TAMPER_4: Tamper4 + * @arg RTC_TAMPER_5: Tamper5 + * @arg RTC_TAMPER_6: Tamper6 + * @arg RTC_TAMPER_7: Tamper7 + * @arg RTC_TAMPER_8: Tamper8 + * @retval None + */ +#define __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 |= (__TAMPER__)) + +/** + * @brief Disable the TAMP Tamper input detection. + * @param __HANDLE__ specifies the RTC handle. + * @param __TAMPER__ specifies the RTC Tamper sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_ALL: All tampers + * @arg RTC_TAMPER_1: Tamper1 + * @arg RTC_TAMPER_2: Tamper2 + * @arg RTC_TAMPER_3: Tamper3 + * @arg RTC_TAMPER_4: Tamper4 + * @arg RTC_TAMPER_5: Tamper5 + * @arg RTC_TAMPER_6: Tamper6 + * @arg RTC_TAMPER_7: Tamper7 + * @arg RTC_TAMPER_8: Tamper8 + */ +#define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 &= ~(__TAMPER__)) + + +/**************************************************************************************************/ +/** + * @brief Enable the TAMP Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @arg RTC_IT_TAMP_4: Tamper4 interrupt + * @arg RTC_IT_TAMP_5: Tamper5 interrupt + * @arg RTC_IT_TAMP_6: Tamper6 interrupt + * @arg RTC_IT_TAMP_7: Tamper7 interrupt + * @arg RTC_IT_TAMP_8: Tamper8 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER |= (__INTERRUPT__)) + +/** + * @brief Disable the TAMP Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @arg RTC_IT_TAMP_4: Tamper4 interrupt + * @arg RTC_IT_TAMP_5: Tamper5 interrupt + * @arg RTC_IT_TAMP_6: Tamper6 interrupt + * @arg RTC_IT_TAMP_7: Tamper7 interrupt + * @arg RTC_IT_TAMP_8: Tamper8 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER &= ~(__INTERRUPT__)) + + +/**************************************************************************************************/ +/** + * @brief Check whether the specified RTC Tamper interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. + * This parameter can be: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @arg RTC_IT_TAMP_4: Tamper4 interrupt + * @arg RTC_IT_TAMP_5: Tamper5 interrupt + * @arg RTC_IT_TAMP_6: Tamper6 interrupt + * @arg RTC_IT_TAMP_7: Tamper7 interrupt + * @arg RTC_IT_TAMP_8: Tamper8 interrupt + * @arg RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts + * @arg RTC_IT_INT_TAMP_1: Internal Tamper1 interrupt + * @arg RTC_IT_INT_TAMP_2: Internal Tamper2 interrupt + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_4: Internal Tamper4 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_7: Internal Tamper7 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt + * @arg RTC_IT_INT_TAMP_9: Internal Tamper9 interrupt + * @arg RTC_IT_INT_TAMP_11: Internal Tamper11 interrupt + * @arg RTC_IT_INT_TAMP_15: Internal Tamper15 interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE) + */ +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((TAMP->MISR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL) + +/** + * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. + * This parameter can be: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @arg RTC_IT_TAMP_4: Tamper4 interrupt + * @arg RTC_IT_TAMP_5: Tamper5 interrupt + * @arg RTC_IT_TAMP_6: Tamper6 interrupt + * @arg RTC_IT_TAMP_7: Tamper7 interrupt + * @arg RTC_IT_TAMP_8: Tamper8 interrupt + * @arg RTC_IT_INT_TAMP_ALL: All internal tampers interrupts + * @arg RTC_IT_INT_TAMP_1: Internal Tamper1 interrupt + * @arg RTC_IT_INT_TAMP_2: Internal Tamper2 interrupt + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_4: Internal Tamper4 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_7: Internal Tamper7 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt + * @arg RTC_IT_INT_TAMP_9: Internal Tamper9 interrupt + * @arg RTC_IT_INT_TAMP_11: Internal Tamper11 interrupt + * @arg RTC_IT_INT_TAMP_15: Internal Tamper15 interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE) + */ +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((TAMP->IER) & (__INTERRUPT__)) != \ + 0U) ? 1UL : 0UL) + +/** + * @brief Get the selected RTC Tampers flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_TAMP_ALL: All tampers flag + * @arg RTC_FLAG_TAMP_1: Tamper1 flag + * @arg RTC_FLAG_TAMP_2: Tamper2 flag + * @arg RTC_FLAG_TAMP_3: Tamper3 flag + * @arg RTC_FLAG_TAMP_4: Tamper4 flag + * @arg RTC_FLAG_TAMP_5: Tamper5 flag + * @arg RTC_FLAG_TAMP_6: Tamper6 flag + * @arg RTC_FLAG_TAMP_7: Tamper7 flag + * @arg RTC_FLAG_TAMP_8: Tamper8 flag + * @arg RTC_FLAG_INT_TAMP_1: Internal Tamper1 flag + * @arg RTC_FLAG_INT_TAMP_2: Internal Tamper2 flag + * @arg RTC_FLAG_INT_TAMP_3: Internal Tamper3 flag + * @arg RTC_FLAG_INT_TAMP_4: Internal Tamper4 flag + * @arg RTC_FLAG_INT_TAMP_5: Internal Tamper5 flag + * @arg RTC_FLAG_INT_TAMP_6: Internal Tamper6 flag + * @arg RTC_FLAG_INT_TAMP_7: Internal Tamper7 flag + * @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 flag + * @arg RTC_FLAG_INT_TAMP_9: Internal Tamper9 flag + * @arg RTC_FLAG_INT_TAMP_11: Internal Tamper11 flag + * @arg RTC_FLAG_INT_TAMP_15: Internal Tamper15 flag + * @retval The state of __FLAG__ (TRUE or FALSE) + */ +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((TAMP->SR) & (__FLAG__)) != 0U) + +/** + * @brief Clear the RTC Tamper's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag to clear. + * This parameter can be: + * @arg RTC_FLAG_TAMP_ALL: All tampers flag + * @arg RTC_FLAG_TAMP_1: Tamper1 flag + * @arg RTC_FLAG_TAMP_2: Tamper2 flag + * @arg RTC_FLAG_TAMP_3: Tamper3 flag + * @arg RTC_FLAG_TAMP_4: Tamper4 flag + * @arg RTC_FLAG_TAMP_5: Tamper5 flag + * @arg RTC_FLAG_TAMP_6: Tamper6 flag + * @arg RTC_FLAG_TAMP_7: Tamper7 flag + * @arg RTC_FLAG_TAMP_8: Tamper8 flag + * @arg RTC_FLAG_INT_TAMP_ALL: All Internal Tamper flags + * @arg RTC_FLAG_INT_TAMP_1: Internal Tamper1 flag + * @arg RTC_FLAG_INT_TAMP_2: Internal Tamper2 flag + * @arg RTC_FLAG_INT_TAMP_3: Internal Tamper3 flag + * @arg RTC_FLAG_INT_TAMP_4: Internal Tamper4 flag + * @arg RTC_FLAG_INT_TAMP_5: Internal Tamper5 flag + * @arg RTC_FLAG_INT_TAMP_6: Internal Tamper6 flag + * @arg RTC_FLAG_INT_TAMP_7: Internal Tamper7 flag + * @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 flag + * @arg RTC_FLAG_INT_TAMP_9: Internal Tamper9 flag + * @arg RTC_FLAG_INT_TAMP_11: Internal Tamper11 flag + * @arg RTC_FLAG_INT_TAMP_15: Internal Tamper15 flag + * @retval None + */ +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((TAMP->SCR) = (__FLAG__)) +/** + * @} + */ + +/* --------------------------------- SSR Underflow ---------------------------------*/ +/** @defgroup RTCEx_SSR_Underflow RTC SSR Underflow + * @{ + */ + +/** + * @brief Enable the RTC SSRU interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC SSRU interrupt sources to be enabled. + * This parameter can be: + * @arg @ref RTC_IT_SSRU SSRU interrupt + * @retval None + */ +#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_SSRUIE)) + +/** + * @brief Disable the RTC SSRU interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC SSRU interrupt sources to be disabled. + * This parameter can be: + * @arg @ref RTC_IT_SSRU SSRU interrupt + * @retval None + */ +#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_SSRUIE)) + + +/** + * @brief Check whether the specified RTC SSRU interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC SSRU interrupt to check. + * This parameter can be: + * @arg @ref RTC_IT_SSRU SSRU interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE) + */ +#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & (RTC_MISR_SSRUMF)) != 0U) ? 1U : 0U) +/** + * @brief Check whether the specified RTC SSRU interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC SSRU interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_SSRU SSRU interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE) + */ +#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (RTC_CR_SSRUIE)) != 0U) ? 1U : 0U) + +/** + * @brief Get the selected RTC SSRU's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC SSRU Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_SSRUF + * @retval The state of __FLAG__ (TRUE or FALSE) + */ +#define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->SR, RTC_SR_SSRUF) == RTC_SR_SSRUF)) + +/** + * @brief Clear the RTC SSRU's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC SSRU Flag to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_SSRUF + * @retval None + */ +#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG(RTC->SCR, RTC_SCR_CSSRUF)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions + * @{ + */ + +/* RTC TimeStamp functions *****************************************/ +/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp functions + * @{ + */ + +#ifdef RTC_CR_TSE +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); +#endif /* RTC_CR_TSE */ +HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, + RTC_DateTypeDef *sTimeStampDate, uint32_t Format); +void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + + +/* RTC Wake-up functions ******************************************************/ +/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions + * @{ + */ + +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, + uint32_t WakeUpAutoClr); +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTCEx_GetWakeUpTimer(const RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout); +/** + * @} + */ + +/* Extended Control functions ************************************************/ +/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions + * @{ + */ + +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, + uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue); +HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib); +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); +#if defined(RTC_CR_COSEL) +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); +#endif /* RTC_CR_COSEL */ +#if defined(RTC_CR_REFCKON) +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); +#endif /* RTC_CR_REFCKON */ +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(const RTC_HandleTypeDef *hrtc, uint32_t Instance); +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(const RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *pValue); +HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc); + +/** + * @} + */ + +/* Extended RTC features functions *******************************************/ +/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions + * @{ + */ + +void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout); +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(const RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, const RTC_ActiveTampersTypeDef *sAllTamper); +HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, const uint32_t *pSeed); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(const RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(const RTC_HandleTypeDef *hrtc, uint32_t Tamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(const RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(const RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(const RTC_HandleTypeDef *hrtc, + const RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(const RTC_HandleTypeDef *hrtc, + const RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(const RTC_HandleTypeDef *hrtc, uint32_t IntTamper); +HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(const RTC_HandleTypeDef *hrtc, uint32_t IntTamper, + uint32_t Timeout); +#if defined(TAMP_CFGR_BHKLOCK) +HAL_StatusTypeDef HAL_RTCEx_LockBootHardwareKey(const RTC_HandleTypeDef *hrtc); +#endif /* TAMP_CFGR_BHKLOCK */ +void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper4EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper5EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper6EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper7EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper8EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper7EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper9EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper11EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper15EventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions + * @{ + */ +void HAL_RTCEx_BKUPWrite(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +void HAL_RTCEx_BKUPErase(const RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_BKUPBlock(const RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_BKUPUnblock(const RTC_HandleTypeDef *hrtc); +#ifdef TAMP_RPCFGR_RPCFG0 +void HAL_RTCEx_ConfigEraseDeviceSecrets(const RTC_HandleTypeDef *hrtc, uint32_t DeviceSecretConf); +#endif /* TAMP_RPCFGR_RPCFG0 */ +/** + * @} + */ + +#if defined(TAMP_PRIVCFGR_TAMPPRIV) +/** @defgroup RTCEx_Exported_Functions_Group8 Extended RTC privilege functions + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(const RTC_HandleTypeDef *hrtc, + const RTC_PrivilegeStateTypeDef *privilegeState); +HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(const RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState); +/** + * @} + */ +#endif /* TAMP_PRIVCFGR_TAMPPRIV */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RTCEx_Private_Macros RTCEx Private Macros + * @{ + */ + +/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters + * @{ + */ +#if defined(RTC_CR_TSEDGE) +#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ + ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) +#endif /* RTC_CR_TSEDGE */ + +#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT)) + +#define IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) + +#if defined(RTC_CR_TAMPOE) +#define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(MODE) (((MODE) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \ + ((MODE) == RTC_TAMPERDETECTIONOUTPUT_DISABLE)) +#endif /* RTC_CR_TAMPOE */ + +#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) + +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT) + +#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ + ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ + ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) + +#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ + ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) + +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM) + +#define IS_RTC_LOW_POWER_CALIB(LPCAL) (((LPCAL) == RTC_LPCAL_SET) || \ + ((LPCAL) == RTC_LPCAL_RESET)) + + +#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0U) && \ + (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0U)) + +#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__) ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0U) && \ + (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0U)) + +#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL)) + +#define IS_RTC_TAMPER_ERASE_MODE(__MODE__) (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \ + ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE)) + +#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__) (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \ + ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE)) + +#define IS_RTC_TAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE)) + +#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) + +#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) + +#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \ + ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE)) + +#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) \ + (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) + +#define IS_RTC_ATAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_ATAMP_FILTER_ENABLE) || \ + ((__FILTER__) == RTC_ATAMP_FILTER_DISABLE)) + +#define IS_RTC_ATAMPER_OUTPUT_CHANGE_PERIOD(__PERIOD__) ((__PERIOD__) <= 7U) + +#define IS_RTC_ATAMPER_ASYNCPRES_RTCCLK(__PRESCALER__) (((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_2) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_4) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_8) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_16) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_32) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_64) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_128) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_2048)) + + +#define IS_RTC_BKP(__BKP__) ((__BKP__) < RTC_BKP_NUMBER) + +#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ + ((SEL) == RTC_SHIFTADD1S_SET)) + +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS) + +#if defined(RTC_CR_COSEL) +#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ + ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) +#endif /* RTC_CR_COSEL */ + +#define IS_RTC_PRIVILEGE_FULL(__STATE__) (((__STATE__) == RTC_PRIVILEGE_FULL_YES) || \ + ((__STATE__) == RTC_PRIVILEGE_FULL_NO)) + +#define IS_RTC_PRIVILEGE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_PRIVILEGE_FEATURE_ALL) == 0U) + +#define IS_TAMP_PRIVILEGE_FULL(__STATE__) (((__STATE__) == TAMP_PRIVILEGE_FULL_YES) || \ + ((__STATE__) == TAMP_PRIVILEGE_FULL_NO)) + +#define IS_TAMP_MONOTONIC_CNT_PRIVILEGE(__STATE__) (((__STATE__) == TAMP_MONOTONIC_CNT_PRIVILEGE_YES) || \ + ((__STATE__) == TAMP_MONOTONIC_CNT_PRIVILEGE_NO)) + +#define IS_RTC_PRIVILEGE_BKUP_ZONE(__ZONES__) (((__ZONES__) & ~RTC_PRIVILEGE_BKUP_ZONE_ALL) == 0U) + +#define IS_RTC_BINARY_MODE(MODE) (((MODE) == RTC_BINARY_NONE) || \ + ((MODE) == RTC_BINARY_ONLY) || \ + ((MODE) == RTC_BINARY_MIX )) + +#define IS_RTC_BINARY_MIX_BCDU(BDCU) (((BDCU) == RTC_BINARY_MIX_BCDU_0) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_1) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_2) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_3) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_4) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_5) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_6) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_7)) + +#define IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(MASK) (((MASK) == 0U) || \ + (((MASK) >= RTC_ALARMSUBSECONDBINMASK_SS31_1) &&\ + ((MASK) <= RTC_ALARMSUBSECONDBINMASK_NONE))) + +#define IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(SEL) (((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_NO) || \ + ((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_YES)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_RTC_EX_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sai.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sai.h new file mode 100644 index 00000000000..7ab2adc196d --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sai.h @@ -0,0 +1,968 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_sai.h + * @author MCD Application Team + * @brief Header file of SAI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_SAI_H +#define STM32H7RSxx_HAL_SAI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup SAI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SAI_Exported_Types SAI Exported Types + * @{ + */ + +/** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition + * @brief SAI PDM Init structure definition + * @{ + */ +typedef struct +{ + FunctionalState Activation; /*!< Enable/disable PDM interface */ + uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used. + This parameter must be a number between Min_Data = 1 and Max_Data = 3. */ + uint32_t ClockEnable; /*!< Specifies which clock must be enabled. + This parameter can be a values combination of @ref SAI_PDM_ClockEnable */ +} SAI_PdmInitTypeDef; +/** + * @} + */ + +/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition + * @brief SAI Init Structure definition + * @{ + */ +typedef struct +{ + uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode. + This parameter can be a value of @ref SAI_Block_Mode */ + + uint32_t Synchro; /*!< Specifies SAI Block synchronization + This parameter can be a value of @ref SAI_Block_Synchronization */ + + uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common + for BlockA and BlockB + This parameter can be a value of @ref SAI_Block_SyncExt + @note If both audio blocks of same SAI are used, this parameter has + to be set to the same value for each audio block */ + + uint32_t MckOutput; /*!< Specifies whether master clock output will be generated or not. + This parameter can be a value of @ref SAI_Block_MckOutput */ + + uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven. + This parameter can be a value of @ref SAI_Block_Output_Drive + @note This value has to be set before enabling the audio block + but after the audio block configuration. */ + + uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not. + This parameter can be a value of @ref SAI_Block_NoDivider + @note If bit NODIV in the SAI_xCR1 register is cleared, the frame length + should be aligned to a number equal to a power of 2, from 8 to 256. + If bit NODIV in the SAI_xCR1 register is set, the frame length can + take any of the values from 8 to 256. */ + + uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold. + This parameter can be a value of @ref SAI_Block_Fifo_Threshold */ + + uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling. + This parameter can be a value of @ref SAI_Audio_Frequency */ + + uint32_t Mckdiv; /*!< Specifies the master clock divider. + This parameter must be a number between Min_Data = 0 and Max_Data = 63. + @note This parameter is used only if AudioFrequency is set to + SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */ + + uint32_t MckOverSampling; /*!< Specifies the master clock oversampling. + This parameter can be a value of @ref SAI_Block_Mck_OverSampling */ + + uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected. + This parameter can be a value of @ref SAI_Mono_Stereo_Mode */ + + uint32_t CompandingMode; /*!< Specifies the companding mode type. + This parameter can be a value of @ref SAI_Block_Companding_Mode */ + + uint32_t TriState; /*!< Specifies the companding mode type. + This parameter can be a value of @ref SAI_TRIState_Management */ + + SAI_PdmInitTypeDef PdmInit; /*!< Specifies the PDM configuration. */ + + /* This part of the structure is automatically filled if your are using the high level initialisation + function HAL_SAI_InitProtocol */ + + uint32_t Protocol; /*!< Specifies the SAI Block protocol. + This parameter can be a value of @ref SAI_Block_Protocol */ + + uint32_t DataSize; /*!< Specifies the SAI Block data size. + This parameter can be a value of @ref SAI_Block_Data_Size */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */ + + uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity. + This parameter can be a value of @ref SAI_Block_Clock_Strobing */ +} SAI_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */ + HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */ + HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */ + HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */ + HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */ +} HAL_SAI_StateTypeDef; + +/** + * @brief SAI Callback prototype + */ +typedef void (*SAIcallback)(void); + +/** + * @} + */ + +/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition + * @brief SAI Frame Init structure definition + * @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware). + * @{ + */ +typedef struct +{ + + uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame. + This parameter must be a number between Min_Data = 8 and Max_Data = 256. + @note If master clock MCLK_x pin is declared as an output, the frame length + should be aligned to a number equal to power of 2 in order to keep + in an audio frame, an integer number of MCLK pulses by bit Clock. */ + + uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length. + This Parameter specifies the length in number of bit clock (SCK + 1) + of the active level of FS signal in audio frame. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition. + This parameter can be a value of @ref SAI_Block_FS_Definition */ + + uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity. + This parameter can be a value of @ref SAI_Block_FS_Polarity */ + + uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset. + This parameter can be a value of @ref SAI_Block_FS_Offset */ + +} SAI_FrameInitTypeDef; +/** + * @} + */ + +/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition + * @brief SAI Block Slot Init Structure definition + * @note For SPDIF protocol, these parameters are not used (set by hardware). + * @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware). + * @{ + */ +typedef struct +{ + uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot. + This parameter must be a number between Min_Data = 0 and Max_Data = 24 */ + + uint32_t SlotSize; /*!< Specifies the Slot Size. + This parameter can be a value of @ref SAI_Block_Slot_Size */ + + uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame. + This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ + + uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated. + This parameter can be a value of @ref SAI_Block_Slot_Active */ +} SAI_SlotInitTypeDef; +/** + * @} + */ + +/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition + * @brief SAI handle Structure definition + * @{ + */ +typedef struct __SAI_HandleTypeDef +{ + SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */ + + SAI_InitTypeDef Init; /*!< SAI communication parameters */ + + SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */ + + SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */ + + uint16_t XferSize; /*!< SAI transfer size */ + + uint16_t XferCount; /*!< SAI transfer counter */ + + DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */ + + SAIcallback mutecallback; /*!< SAI mute callback */ + + void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */ + + HAL_LockTypeDef Lock; /*!< SAI locking object */ + + __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */ + + __IO uint32_t ErrorCode; /*!< SAI Error code */ + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */ + void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */ + void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */ + void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */ + void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */ + void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */ + void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */ +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +} SAI_HandleTypeDef; + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +/** + * @brief SAI callback ID enumeration definition + */ +typedef enum +{ + HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */ + HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */ + HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */ + HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */ + HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */ + HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */ + HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */ +} HAL_SAI_CallbackIDTypeDef; + +/** + * @brief SAI callback pointer definition + */ +typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SAI_Exported_Constants SAI Exported Constants + * @{ + */ + +/** @defgroup SAI_Error_Code SAI Error Code + * @{ + */ +#define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */ +#define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */ +#define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */ +#define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */ +#define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */ +#define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */ +#define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */ +#define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */ +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SAI_Block_SyncExt SAI External synchronisation + * @{ + */ +#define SAI_SYNCEXT_DISABLE 0U +#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U +#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U +/** + * @} + */ + +/** @defgroup SAI_Block_MckOutput SAI Block Master Clock Output + * @{ + */ +#define SAI_MCK_OUTPUT_DISABLE 0x00000000U +#define SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN +/** + * @} + */ + +/** @defgroup SAI_Protocol SAI Supported protocol + * @{ + */ +#define SAI_I2S_STANDARD 0U +#define SAI_I2S_MSBJUSTIFIED 1U +#define SAI_I2S_LSBJUSTIFIED 2U +#define SAI_PCM_LONG 3U +#define SAI_PCM_SHORT 4U +/** + * @} + */ + +/** @defgroup SAI_Protocol_DataSize SAI protocol data size + * @{ + */ +#define SAI_PROTOCOL_DATASIZE_16BIT 0U +#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U +#define SAI_PROTOCOL_DATASIZE_24BIT 2U +#define SAI_PROTOCOL_DATASIZE_32BIT 3U +/** + * @} + */ + +/** @defgroup SAI_Audio_Frequency SAI Audio Frequency + * @{ + */ +#define SAI_AUDIO_FREQUENCY_192K 192000U +#define SAI_AUDIO_FREQUENCY_96K 96000U +#define SAI_AUDIO_FREQUENCY_48K 48000U +#define SAI_AUDIO_FREQUENCY_44K 44100U +#define SAI_AUDIO_FREQUENCY_32K 32000U +#define SAI_AUDIO_FREQUENCY_22K 22050U +#define SAI_AUDIO_FREQUENCY_16K 16000U +#define SAI_AUDIO_FREQUENCY_11K 11025U +#define SAI_AUDIO_FREQUENCY_8K 8000U +#define SAI_AUDIO_FREQUENCY_MCKDIV 0U +/** + * @} + */ + +/** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling + * @{ + */ +#define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U +#define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR +/** + * @} + */ + +/** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable + * @{ + */ +#define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1 +#define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2 +/** + * @} + */ + +/** @defgroup SAI_Block_Mode SAI Block Mode + * @{ + */ +#define SAI_MODEMASTER_TX 0x00000000U +#define SAI_MODEMASTER_RX SAI_xCR1_MODE_0 +#define SAI_MODESLAVE_TX SAI_xCR1_MODE_1 +#define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0) + +/** + * @} + */ + +/** @defgroup SAI_Block_Protocol SAI Block Protocol + * @{ + */ +#define SAI_FREE_PROTOCOL 0x00000000U +#define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0 +#define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1 +/** + * @} + */ + +/** @defgroup SAI_Block_Data_Size SAI Block Data Size + * @{ + */ +#define SAI_DATASIZE_8 SAI_xCR1_DS_1 +#define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0) +#define SAI_DATASIZE_16 SAI_xCR1_DS_2 +#define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0) +#define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1) +#define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0) +/** + * @} + */ + +/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission + * @{ + */ +#define SAI_FIRSTBIT_MSB 0x00000000U +#define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST +/** + * @} + */ + +/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing + * @{ + */ +#define SAI_CLOCKSTROBING_FALLINGEDGE 0U +#define SAI_CLOCKSTROBING_RISINGEDGE 1U +/** + * @} + */ + +/** @defgroup SAI_Block_Synchronization SAI Block Synchronization + * @{ + */ +#define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */ +#define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */ +#define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */ +#define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */ +/** + * @} + */ + +/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U +#define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV +/** + * @} + */ + +/** @defgroup SAI_Block_NoDivider SAI Block NoDivider + * @{ + */ +#define SAI_MASTERDIVIDER_ENABLE 0x00000000U +#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV +/** + * @} + */ + +/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition + * @{ + */ +#define SAI_FS_STARTFRAME 0x00000000U +#define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF +/** + * @} + */ + +/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity + * @{ + */ +#define SAI_FS_ACTIVE_LOW 0x00000000U +#define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL +/** + * @} + */ + +/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset + * @{ + */ +#define SAI_FS_FIRSTBIT 0x00000000U +#define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF +/** + * @} + */ + +/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size + * @{ + */ +#define SAI_SLOTSIZE_DATASIZE 0x00000000U +#define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0 +#define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1 +/** + * @} + */ + +/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active + * @{ + */ +#define SAI_SLOT_NOTACTIVE 0x00000000U +#define SAI_SLOTACTIVE_0 0x00000001U +#define SAI_SLOTACTIVE_1 0x00000002U +#define SAI_SLOTACTIVE_2 0x00000004U +#define SAI_SLOTACTIVE_3 0x00000008U +#define SAI_SLOTACTIVE_4 0x00000010U +#define SAI_SLOTACTIVE_5 0x00000020U +#define SAI_SLOTACTIVE_6 0x00000040U +#define SAI_SLOTACTIVE_7 0x00000080U +#define SAI_SLOTACTIVE_8 0x00000100U +#define SAI_SLOTACTIVE_9 0x00000200U +#define SAI_SLOTACTIVE_10 0x00000400U +#define SAI_SLOTACTIVE_11 0x00000800U +#define SAI_SLOTACTIVE_12 0x00001000U +#define SAI_SLOTACTIVE_13 0x00002000U +#define SAI_SLOTACTIVE_14 0x00004000U +#define SAI_SLOTACTIVE_15 0x00008000U +#define SAI_SLOTACTIVE_ALL 0x0000FFFFU +/** + * @} + */ + +/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode + * @{ + */ +#define SAI_STEREOMODE 0x00000000U +#define SAI_MONOMODE SAI_xCR1_MONO +/** + * @} + */ + +/** @defgroup SAI_TRIState_Management SAI TRIState Management + * @{ + */ +#define SAI_OUTPUT_NOTRELEASED 0x00000000U +#define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS +/** + * @} + */ + +/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold + * @{ + */ +#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U +#define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0 +#define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1 +#define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0) +#define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2 +/** + * @} + */ + +/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode + * @{ + */ +#define SAI_NOCOMPANDING 0x00000000U +#define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1 +#define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0) +#define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL) +#define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL) +/** + * @} + */ + +/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value + * @{ + */ +#define SAI_ZERO_VALUE 0x00000000U +#define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL +/** + * @} + */ + +/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition + * @{ + */ +#define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE +#define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE +#define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE +#define SAI_IT_FREQ SAI_xIMR_FREQIE +#define SAI_IT_CNRDY SAI_xIMR_CNRDYIE +#define SAI_IT_AFSDET SAI_xIMR_AFSDETIE +#define SAI_IT_LFSDET SAI_xIMR_LFSDETIE +/** + * @} + */ + +/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition + * @{ + */ +#define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR +#define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET +#define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG +#define SAI_FLAG_FREQ SAI_xSR_FREQ +#define SAI_FLAG_CNRDY SAI_xSR_CNRDY +#define SAI_FLAG_AFSDET SAI_xSR_AFSDET +#define SAI_FLAG_LFSDET SAI_xSR_LFSDET +/** + * @} + */ + +/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level + * @{ + */ +#define SAI_FIFOSTATUS_EMPTY 0x00000000U +#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U +#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U +#define SAI_FIFOSTATUS_HALFFULL 0x00030000U +#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U +#define SAI_FIFOSTATUS_FULL 0x00050000U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SAI_Exported_Macros SAI Exported Macros + * @brief macros to handle interrupts and specific configurations + * @{ + */ + +/** @brief Reset SAI handle state. + * @param __HANDLE__ specifies the SAI Handle. + * @retval None + */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SAI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SAI interrupts. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable + * @arg SAI_IT_MUTEDET: Mute detection interrupt enable + * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable + * @arg SAI_IT_FREQ: FIFO request interrupt enable + * @arg SAI_IT_CNRDY: Codec not ready interrupt enable + * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable + * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable + * @retval None + */ +#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) + +/** @brief Disable the specified SAI interrupts. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable + * @arg SAI_IT_MUTEDET: Mute detection interrupt enable + * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable + * @arg SAI_IT_FREQ: FIFO request interrupt enable + * @arg SAI_IT_CNRDY: Codec not ready interrupt enable + * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable + * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable + * @retval None + */ +#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified SAI interrupt source is enabled or not. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the SAI interrupt source to check. + * This parameter can be one of the following values: + * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable + * @arg SAI_IT_MUTEDET: Mute detection interrupt enable + * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable + * @arg SAI_IT_FREQ: FIFO request interrupt enable + * @arg SAI_IT_CNRDY: Codec not ready interrupt enable + * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable + * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SAI flag is set or not. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SAI_FLAG_OVRUDR: Overrun underrun flag. + * @arg SAI_FLAG_MUTEDET: Mute detection flag. + * @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag. + * @arg SAI_FLAG_FREQ: FIFO request flag. + * @arg SAI_FLAG_CNRDY: Codec not ready flag. + * @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag. + * @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified SAI pending flag. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun + * @arg SAI_FLAG_MUTEDET: Clear Mute detection + * @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration + * @arg SAI_FLAG_FREQ: Clear FIFO request + * @arg SAI_FLAG_CNRDY: Clear Codec not ready + * @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection + * @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection + * + * @retval None + */ +#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) + +/** @brief Enable SAI. + * @param __HANDLE__ specifies the SAI Handle. + * @retval None + */ +#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN) + +/** @brief Disable SAI. + * @param __HANDLE__ specifies the SAI Handle. + * @retval None + */ +#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN) + +/** + * @} + */ + +/* Include SAI HAL Extension module */ +#include "stm32h7rsxx_hal_sai_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SAI_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup SAI_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); +HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai); +HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai); +void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai); +void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai); + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +/* SAI callbacks register/unregister functions ********************************/ +HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID, + pSAI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/** @addtogroup SAI_Exported_Functions_Group2 + * @{ + */ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai); +HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai); +HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai); + +/* Abort function */ +HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai); + +/* Mute management */ +HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val); +HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai); +HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter); +HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai); + +/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai); +void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai); +void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai); +void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai); +void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai); +void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai); +/** + * @} + */ + +/** @addtogroup SAI_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai); +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SAI_Private_Macros SAI Private Macros + * @{ + */ +#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\ + ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\ + ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE)) + +#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\ + ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\ + ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\ + ((PROTOCOL) == SAI_PCM_LONG) ||\ + ((PROTOCOL) == SAI_PCM_SHORT)) + +#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\ + ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\ + ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\ + ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT)) + +#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV)) + +#define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \ + ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE)) + +#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U)) + +#define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \ + (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U)) + +#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \ + ((MODE) == SAI_MODEMASTER_RX) || \ + ((MODE) == SAI_MODESLAVE_TX) || \ + ((MODE) == SAI_MODESLAVE_RX)) + +#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \ + ((PROTOCOL) == SAI_AC97_PROTOCOL) || \ + ((PROTOCOL) == SAI_SPDIF_PROTOCOL)) + +#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \ + ((DATASIZE) == SAI_DATASIZE_10) || \ + ((DATASIZE) == SAI_DATASIZE_16) || \ + ((DATASIZE) == SAI_DATASIZE_20) || \ + ((DATASIZE) == SAI_DATASIZE_24) || \ + ((DATASIZE) == SAI_DATASIZE_32)) + +#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \ + ((BIT) == SAI_FIRSTBIT_LSB)) + +#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \ + ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE)) + +#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2)) + +#define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \ + ((VALUE) == SAI_MCK_OUTPUT_DISABLE)) + +#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \ + ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE)) + +#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \ + ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE)) + +#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U) + +#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \ + ((VALUE) == SAI_LAST_SENT_VALUE)) + +#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \ + ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \ + ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \ + ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \ + ((MODE) == SAI_ALAW_2CPL_COMPANDING)) + +#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \ + ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \ + ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \ + ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \ + ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL)) + +#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\ + ((STATE) == SAI_OUTPUT_RELEASED)) + +#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\ + ((MODE) == SAI_STEREOMODE)) + +#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL) + +#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U)) + +#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \ + ((SIZE) == SAI_SLOTSIZE_16B) || \ + ((SIZE) == SAI_SLOTSIZE_32B)) + +#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U) + +#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \ + ((OFFSET) == SAI_FS_BEFOREFIRSTBIT)) + +#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \ + ((POLARITY) == SAI_FS_ACTIVE_HIGH)) + +#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \ + ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION)) + +#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U) + +#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U)) + +#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SAI_Private_Functions SAI Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_SAI_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sai_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sai_ex.h new file mode 100644 index 00000000000..cbe0198fed8 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sai_ex.h @@ -0,0 +1,103 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_sai_ex.h + * @author MCD Application Team + * @brief Header file of SAI HAL extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_SAI_EX_H +#define STM32H7RSxx_HAL_SAI_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup SAIEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SAIEx_Exported_Types SAIEx Exported Types + * @{ + */ + +/** + * @brief PDM microphone delay structure definition + */ +typedef struct +{ + uint32_t MicPair; /*!< Specifies which pair of microphones is selected. + This parameter must be a number between Min_Data = 1 and Max_Data = 3. */ + + uint32_t LeftDelay; /*!< Specifies the delay in PDM clock unit to apply on left microphone. + This parameter must be a number between Min_Data = 0 and Max_Data = 7. */ + + uint32_t RightDelay; /*!< Specifies the delay in PDM clock unit to apply on right microphone. + This parameter must be a number between Min_Data = 0 and Max_Data = 7. */ +} SAIEx_PdmMicDelayParamTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions + * @{ + */ + +/** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai, + const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros + * @{ + */ +#define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_SAI_EX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sd.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sd.h new file mode 100644 index 00000000000..f215e991f34 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sd.h @@ -0,0 +1,798 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_sd.h + * @author MCD Application Team + * @brief Header file of SD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_SD_H +#define STM32H7RSxx_HAL_SD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_sdmmc.h" +#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_SDMMC3) +#include "stm32h7rsxx_ll_dlyb.h" +#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */ + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#if defined (SDMMC1) || defined (SDMMC2) + +/** @defgroup SD SD + * @brief SD HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SD_Exported_Types SD Exported Types + * @{ + */ + +/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure + * @{ + */ +typedef enum +{ + HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), /*!< SD not yet initialized or disabled */ + HAL_SD_STATE_READY = ((uint32_t)0x00000001U), /*!< SD initialized and ready for use */ + HAL_SD_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< SD Timeout state */ + HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U), /*!< SD process ongoing */ + HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< SD Programming State */ + HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receiving State */ + HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfer State */ + HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */ +} HAL_SD_StateTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure + * @{ + */ +typedef uint32_t HAL_SD_CardStateTypeDef; + +#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */ +#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ +#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ +#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ +#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ +#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ +#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ +#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ +#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */ +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition + * @{ + */ +#define SD_InitTypeDef SDMMC_InitTypeDef +#define SD_TypeDef SDMMC_TypeDef + +/** + * @brief SD Card Information Structure definition + */ +typedef struct +{ + uint32_t CardType; /*!< Specifies the card Type */ + + uint32_t CardVersion; /*!< Specifies the card version */ + + uint32_t Class; /*!< Specifies the class of the card class */ + + uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ + + uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ + + uint32_t BlockSize; /*!< Specifies one block size in bytes */ + + uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ + + uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ + + uint32_t CardSpeed; /*!< Specifies the card Speed */ + +} HAL_SD_CardInfoTypeDef; + +/** + * @brief SD handle Structure definition + */ +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +typedef struct __SD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +{ + SD_TypeDef *Instance; /*!< SD registers base address */ + + SD_InitTypeDef Init; /*!< SD required parameters */ + + HAL_LockTypeDef Lock; /*!< SD locking object */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ + + uint32_t TxXferSize; /*!< SD Tx Transfer size */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ + + uint32_t RxXferSize; /*!< SD Rx Transfer size */ + + __IO uint32_t Context; /*!< SD transfer context */ + + __IO HAL_SD_StateTypeDef State; /*!< SD card State */ + + __IO uint32_t ErrorCode; /*!< SD Card Error codes */ + + HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */ + + uint32_t CSD[4]; /*!< SD card specific data table */ + + uint32_t CID[4]; /*!< SD card identification number table */ + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* RxCpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* ErrorCallback)(struct __SD_HandleTypeDef *hsd); + void (* AbortCpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* Read_DMALnkLstBufCpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* Write_DMALnkLstBufCpltCallback)(struct __SD_HandleTypeDef *hsd); +#if (USE_SD_TRANSCEIVER != 0U) + void (* DriveTransceiver_1_8V_Callback)(FlagStatus status); +#endif /* USE_SD_TRANSCEIVER */ + + void (* MspInitCallback)(struct __SD_HandleTypeDef *hsd); + void (* MspDeInitCallback)(struct __SD_HandleTypeDef *hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +} SD_HandleTypeDef; + +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register + * @{ + */ +typedef struct +{ + __IO uint8_t CSDStruct; /*!< CSD structure */ + __IO uint8_t SysSpecVersion; /*!< System specification version */ + __IO uint8_t Reserved1; /*!< Reserved */ + __IO uint8_t TAAC; /*!< Data read access time 1 */ + __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ + __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ + __IO uint16_t CardComdClasses; /*!< Card command classes */ + __IO uint8_t RdBlockLen; /*!< Max. read data block length */ + __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ + __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ + __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ + __IO uint8_t DSRImpl; /*!< DSR implemented */ + __IO uint8_t Reserved2; /*!< Reserved */ + __IO uint32_t DeviceSize; /*!< Device Size */ + __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ + __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ + __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ + __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ + __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ + __IO uint8_t EraseGrSize; /*!< Erase group size */ + __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ + __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ + __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ + __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ + __IO uint8_t WrSpeedFact; /*!< Write speed factor */ + __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ + __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ + __IO uint8_t Reserved3; /*!< Reserved */ + __IO uint8_t ContentProtectAppli; /*!< Content protection application */ + __IO uint8_t FileFormatGroup; /*!< File format group */ + __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ + __IO uint8_t PermWrProtect; /*!< Permanent write protection */ + __IO uint8_t TempWrProtect; /*!< Temporary write protection */ + __IO uint8_t FileFormat; /*!< File format */ + __IO uint8_t ECC; /*!< ECC code */ + __IO uint8_t CSD_CRC; /*!< CSD CRC */ + __IO uint8_t Reserved4; /*!< Always 1 */ +} HAL_SD_CardCSDTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register + * @{ + */ +typedef struct +{ + __IO uint8_t ManufacturerID; /*!< Manufacturer ID */ + __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ + __IO uint32_t ProdName1; /*!< Product Name part1 */ + __IO uint8_t ProdName2; /*!< Product Name part2 */ + __IO uint8_t ProdRev; /*!< Product Revision */ + __IO uint32_t ProdSN; /*!< Product Serial Number */ + __IO uint8_t Reserved1; /*!< Reserved1 */ + __IO uint16_t ManufactDate; /*!< Manufacturing Date */ + __IO uint8_t CID_CRC; /*!< CID CRC */ + __IO uint8_t Reserved2; /*!< Always 1 */ + +} HAL_SD_CardCIDTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13 + * @{ + */ +typedef struct +{ + __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */ + __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */ + __IO uint16_t CardType; /*!< Carries information about card type */ + __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */ + __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */ + __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */ + __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */ + __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */ + __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */ + __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */ + __IO uint8_t UhsSpeedGrade; /*!< Carries information about the speed grade of UHS card */ + __IO uint8_t UhsAllocationUnitSize; /*!< Carries information about the UHS card's allocation unit size */ + __IO uint8_t VideoSpeedClass; /*!< Carries information about the Video Speed Class of UHS card */ +} HAL_SD_CardStatusTypeDef; +/** + * @} + */ + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_SD_TX_CPLT_CB_ID = 0x00U, /*!< SD Tx Complete Callback ID */ + HAL_SD_RX_CPLT_CB_ID = 0x01U, /*!< SD Rx Complete Callback ID */ + HAL_SD_ERROR_CB_ID = 0x02U, /*!< SD Error Callback ID */ + HAL_SD_ABORT_CB_ID = 0x03U, /*!< SD Abort Callback ID */ + HAL_SD_READ_DMA_LNKLST_BUF_CPLT_CB_ID = 0x04U, /*!< SD DMA Rx Linked List Node buffer Callback ID */ + HAL_SD_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID = 0x05U, /*!< SD DMA Tx Linked List Node buffer Callback ID */ + + HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */ + HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */ +} HAL_SD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition + * @{ + */ +typedef void (*pSD_CallbackTypeDef)(SD_HandleTypeDef *hsd); +#if (USE_SD_TRANSCEIVER != 0U) +typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); +#endif /* USE_SD_TRANSCEIVER */ +/** + * @} + */ +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SD_Exported_Constants SD Exported Constants + * @{ + */ + +#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */ + +/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition + * @{ + */ +#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ +/*!< number of transferred bytes does not match the block length */ +#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ +/*!< command or if there was an attempt to access a locked card */ +#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ +/*!< of erase sequence command was received */ +#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration + * @{ + */ +#define SD_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */ +#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */ +#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */ +#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */ +#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */ +#define SD_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */ +#define SD_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */ + +/** + * @} + */ + +/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards + * @{ + */ +#define CARD_NORMAL_SPEED ((uint32_t)0x00000000U) /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01 */ +#define CARD_HIGH_SPEED ((uint32_t)0x00000100U) /*!< High Speed Card <25Mo/s , Spec version 2.00 */ +#define CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U) /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards + and <104Mo/s for SDR104, Spec version 3.01 */ + +#define CARD_SDSC ((uint32_t)0x00000000U) /*!< SD Standard Capacity <2Go */ +#define CARD_SDHC_SDXC ((uint32_t)0x00000001U) /*!< SD High Capacity <32Go, SD Extended Capacity <2To */ +#define CARD_SECURED ((uint32_t)0x00000003U) + +/** + * @} + */ + +/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version + * @{ + */ +#define CARD_V1_X ((uint32_t)0x00000000U) +#define CARD_V2_X ((uint32_t)0x00000001U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SD_Exported_macros SD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +/** @brief Reset SD handle state. + * @param __HANDLE__ SD Handle. + * @retval None + */ +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_SD_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET) +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + +/** + * @brief Enable the SD device interrupt. + * @param __HANDLE__ SD Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval None + */ +#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Disable the SD device interrupt. + * @param __HANDLE__ SD Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval None + */ +#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Check whether the specified SD flag is set or not. + * @param __HANDLE__ SD Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDMMC_FLAG_DHOLD: Data transfer Hold + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 + * @arg SDMMC_FLAG_DPSMACT: Data path state machine active + * @arg SDMMC_FLAG_CPSMACT: Command path state machine active + * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full + * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) + * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received + * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received + * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout + * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion + * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure + * @arg SDMMC_FLAG_IDMATE: IDMA transfer error + * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete + * @retval The new state of SD FLAG (SET or RESET). + */ +#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Clear the SD's pending flags. + * @param __HANDLE__ SD Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDMMC_FLAG_DHOLD: Data transfer Hold + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 + * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received + * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received + * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout + * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion + * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure + * @arg SDMMC_FLAG_IDMATE: IDMA transfer error + * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete + * @retval None + */ +#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Check whether the specified SD interrupt has occurred or not. + * @param __HANDLE__ SD Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval The new state of SD IT (SET or RESET). + */ +#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Clear the SD's interrupt pending bits. + * @param __HANDLE__ SD Handle. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval None + */ +#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @} + */ + +/* Include SD HAL Extension module */ +#include "stm32h7rsxx_hal_sd_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SD_Exported_Functions SD Exported Functions + * @{ + */ + +/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd); +void HAL_SD_MspInit(SD_HandleTypeDef *hsd); +void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +/* Non-Blocking mode: IT */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); + +void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd); + +/* Callback in non blocking modes (DMA) */ +void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd); +void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd); + +#if (USE_SD_TRANSCEIVER != 0U) +/* Callback to switch in 1.8V mode */ +void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status); +#endif /* USE_SD_TRANSCEIVER */ + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +/* SD callback registering/unregistering */ +HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, + pSD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID); + +#if (USE_SD_TRANSCEIVER != 0U) +HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd); +#endif /* USE_SD_TRANSCEIVER */ +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode); +HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode); +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group4 SD card related functions + * @{ + */ +HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); +HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions + * @{ + */ +HAL_SD_StateTypeDef HAL_SD_GetState(const SD_HandleTypeDef *hsd); +uint32_t HAL_SD_GetError(const SD_HandleTypeDef *hsd); +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management + * @{ + */ +HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup SD_Private_Types SD Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SD_Private_Defines SD Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup SD_Private_Variables SD Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SD_Private_Constants SD Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SD_Private_Macros SD Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SD_Private_Functions SD Private Functions + * @{ + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ +#endif /* SDMMC1 || SDMMC2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7RSxx_HAL_SD_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sd_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sd_ex.h new file mode 100644 index 00000000000..c8b13b8b6b7 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sd_ex.h @@ -0,0 +1,119 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_sd_ex.h + * @author MCD Application Team + * @brief Header file of SD HAL extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_SD_EX_H +#define STM32H7RSxx_HAL_SD_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#if defined (SDMMC1) || defined (SDMMC2) + +/** @addtogroup SDEx + * @brief SD HAL extended module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SDEx_Exported_Types SDEx Exported Types + * @{ + */ + +/** @defgroup SDEx_Exported_Types_Group1 Linked List Wrapper + * @{ + */ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* -----------------Linked List Wrapper --------------------------------------*/ + +#define SD_DMALinkNodeTypeDef SDMMC_DMALinkNodeTypeDef +#define SD_DMALinkNodeConfTypeDef SDMMC_DMALinkNodeConfTypeDef +#define SD_DMALinkedListTypeDef SDMMC_DMALinkedListTypeDef +/* ----------------- Linked Aliases ------------------------------------------*/ +#define HAL_SDEx_DMALinkedList_WriteCpltCallback HAL_SD_TxCpltCallback +#define HAL_SDEx_DMALinkedList_ReadCpltCallback HAL_SD_RxCpltCallback +/** + * @} + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SDEx_Exported_Functions SDEx Exported Functions + * @{ + */ +/** @defgroup SDEx_Exported_Functions_Group1 Linked List functions + * @{ + */ +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SD_DMALinkedListTypeDef *pLinkedList, + uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, SD_DMALinkedListTypeDef *pLinkedList, + uint32_t BlockAdd, uint32_t NumberOfBlocks); + +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_BuildNode(SD_DMALinkNodeTypeDef *pNode, SD_DMALinkNodeConfTypeDef *pNodeConf); +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_InsertNode(SD_DMALinkedListTypeDef *pLinkedList, + SD_DMALinkNodeTypeDef *pPrevNode, SD_DMALinkNodeTypeDef *pNewNode); +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_RemoveNode(SD_DMALinkedListTypeDef *pLinkedList, SD_DMALinkNodeTypeDef *pNode); +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_LockNode(SD_DMALinkNodeTypeDef *pNode); +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_UnlockNode(SD_DMALinkNodeTypeDef *pNode); +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_EnableCircularMode(SD_DMALinkedListTypeDef *pLinkedList); +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_DisableCircularMode(SD_DMALinkedListTypeDef *pLinkedList); + +void HAL_SDEx_Read_DMALnkLstBufCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SDEx_Write_DMALnkLstBufCpltCallback(SD_HandleTypeDef *hsd); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions prototypes ----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ +#endif /* SDMMC1 || SDMMC2 */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + + +#endif /* stm32h7rsxx_HAL_SD_EX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sdram.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sdram.h new file mode 100644 index 00000000000..3f15255bb95 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sdram.h @@ -0,0 +1,236 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_sdram.h + * @author MCD Application Team + * @brief Header file of SDRAM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_SDRAM_H +#define STM32H7RSxx_HAL_SDRAM_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_fmc.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup SDRAM + * @{ + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup SDRAM_Exported_Types SDRAM Exported Types + * @{ + */ + +/** + * @brief HAL SDRAM State structure definition + */ +typedef enum +{ + HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */ + HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */ + HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */ + HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */ + HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */ + HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */ + +} HAL_SDRAM_StateTypeDef; + +/** + * @brief SDRAM handle Structure definition + */ +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +typedef struct __SDRAM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +{ + FMC_SDRAM_TypeDef *Instance; /*!< Register base address */ + + FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */ + + __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */ + + HAL_LockTypeDef Lock; /*!< SDRAM locking object */ + + DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + void (* MspInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp Init callback */ + void (* MspDeInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp DeInit callback */ + void (* RefreshErrorCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Refresh Error callback */ + void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Error callback */ +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} SDRAM_HandleTypeDef; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SDRAM Callback ID enumeration definition + */ +typedef enum +{ + HAL_SDRAM_MSP_INIT_CB_ID = 0x00U, /*!< SDRAM MspInit Callback ID */ + HAL_SDRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SDRAM MspDeInit Callback ID */ + HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, /*!< SDRAM Refresh Error Callback ID */ + HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U, /*!< SDRAM DMA Xfer Complete Callback ID */ + HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U /*!< SDRAM DMA Xfer Error Callback ID */ +} HAL_SDRAM_CallbackIDTypeDef; + +/** + * @brief HAL SDRAM Callback pointer definition + */ +typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram); +typedef void (*pSDRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros + * @{ + */ + +/** @brief Reset SDRAM handle state + * @param __HANDLE__ specifies the SDRAM handle. + * @retval None + */ +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_SDRAM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET) +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions + * @{ + */ + +/** @addtogroup SDRAM_Exported_Functions_Group1 + * @{ + */ + +/* Initialization/de-initialization functions *********************************/ +HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing); +HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram); + +void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/** @addtogroup SDRAM_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ****************************************************/ +HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); + +HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +/* SDRAM callback registering/unregistering */ +HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId); +HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_DmaCallbackTypeDef pCallback); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup SDRAM_Exported_Functions_Group3 + * @{ + */ +/* SDRAM Control functions *****************************************************/ +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram); +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram); +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate); +HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber); +uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); + +/** + * @} + */ + +/** @addtogroup SDRAM_Exported_Functions_Group4 + * @{ + */ +/* SDRAM State functions ********************************************************/ +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_SDRAM_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_smartcard.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_smartcard.h new file mode 100644 index 00000000000..7fec771050a --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_smartcard.h @@ -0,0 +1,1213 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_smartcard.h + * @author MCD Application Team + * @brief Header file of SMARTCARD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_SMARTCARD_H +#define STM32H7RSxx_HAL_SMARTCARD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup SMARTCARD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types + * @{ + */ + +/** + * @brief SMARTCARD Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate. + The baud rate register is computed using the following formula: + Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate))) + where usart_ker_ckpres is the USART input clock divided by a prescaler */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter @ref SMARTCARD_Word_Length can only be + set to 9 (8 data + 1 parity bits). */ + + uint32_t StopBits; /*!< Specifies the number of stop bits. + This parameter can be a value of @ref SMARTCARD_Stop_Bits. */ + + uint16_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref SMARTCARD_Parity + @note The parity is enabled by default (PCE is forced to 1). + Since the WordLength is forced to 8 bits + parity, M is + forced to 1 and the parity bit is the 9th bit. */ + + uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref SMARTCARD_Mode */ + + uint16_t CLKPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref SMARTCARD_Clock_Polarity */ + + uint16_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SMARTCARD_Clock_Phase */ + + uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref SMARTCARD_Last_Bit */ + + uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote + is selected. Selecting the single sample method increases + the receiver tolerance to clock deviations. This parameter can be a value + of @ref SMARTCARD_OneBit_Sampling. */ + + uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. + This parameter can be any value from 0x01 to 0x1F. Prescaler value is + multiplied by 2 to give the division factor of the source clock frequency */ + + uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ + + uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled + in case of parity error. + This parameter can be a value of @ref SMARTCARD_NACK_Enable */ + + uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled. + This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/ + + uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks: + it is used to implement the Character Wait Time (CWT) and + Block Wait Time (BWT). It is coded over 24 bits. */ + + uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode. + This parameter can be any value from 0x0 to 0xFF */ + + uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in + receive and transmit mode). When set to 0, retransmission is + disabled. Otherwise, its maximum value is 7 (before signalling + an error) */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source. + This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */ + +} SMARTCARD_InitTypeDef; + +/** + * @brief SMARTCARD advanced features initialization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several + advanced features may be initialized at the same time. This parameter + can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref SMARTCARD_Tx_Inv */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref SMARTCARD_Rx_Inv */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref SMARTCARD_Data_Inv */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref SMARTCARD_Overrun_Disable */ + + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref SMARTCARD_MSB_First */ + + uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when + relevant flag is available) or once guard time period has elapsed. + This parameter can be a value + of @ref SMARTCARDEx_Transmission_Completion_Indication. */ +} SMARTCARD_AdvFeatureInitTypeDef; + +/** + * @brief HAL SMARTCARD State definition + * @note HAL SMARTCARD State value is a combination of 2 different substates: + * gState and RxState (see @ref SMARTCARD_State_Definition). + * - gState contains SMARTCARD state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_SMARTCARD_StateTypeDef; + +/** + * @brief SMARTCARD handle Structure definition + */ +typedef struct __SMARTCARD_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< USART registers base address */ + + SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */ + + SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ + + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. + This parameter can be a value of + @ref SMARTCARDEx_FIFO_mode. */ + + void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global + Handle management and also related to Tx operations. + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ + + __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< SmartCard Error code */ + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Complete Callback */ + + void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Complete Callback */ + + void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Error Callback */ + + void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Complete Callback */ + + void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */ + + void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Receive Complete Callback */ + + void (* RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Fifo Full Callback */ + + void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Fifo Empty Callback */ + + void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp Init callback */ + + void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp DeInit callback */ +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +} SMARTCARD_HandleTypeDef; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SMARTCARD Callback ID enumeration definition + */ +typedef enum +{ + HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */ + HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */ + HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */ + HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */ + HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */ + HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */ + HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, /*!< SMARTCARD Rx Fifo Full Callback ID */ + HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U, /*!< SMARTCARD Tx Fifo Empty Callback ID */ + + HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */ + HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */ + +} HAL_SMARTCARD_CallbackIDTypeDef; + +/** + * @brief HAL SMARTCARD Callback pointer definition + */ +typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard); /*!< pointer to an SMARTCARD callback function */ + +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +/** + * @brief SMARTCARD clock sources + */ +typedef enum +{ + SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + SMARTCARD_CLOCKSOURCE_HSI = 0x04U, /*!< HSI clock source */ + SMARTCARD_CLOCKSOURCE_CSI = 0x08U, /*!< CSI clock source */ + SMARTCARD_CLOCKSOURCE_LSE = 0x20U, /*!< LSE clock source */ + SMARTCARD_CLOCKSOURCE_PLL2Q = 0x40U, /*!< PLL2Q clock source */ + SMARTCARD_CLOCKSOURCE_PLL3Q = 0x80U, /*!< PLL3Q clock source */ + SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U /*!< undefined clock source */ +} SMARTCARD_ClockSourceTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants + * @{ + */ + +/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition + * @{ + */ +#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value + is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for + use. Value is allowed for gState + and RxState */ +#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception + process is ongoing Not to be used for + neither gState nor RxState. + Value is result of combination (Or) + between gState and RxState values */ +#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition + * @{ + */ +#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length + * @{ + */ +#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0 /*!< SMARTCARD frame length */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits + * @{ + */ +#define SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0 /*!< SMARTCARD frame with 0.5 stop bit */ +#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Parity SMARTCARD Parity + * @{ + */ +#define SMARTCARD_PARITY_EVEN USART_CR1_PCE /*!< SMARTCARD frame even parity */ +#define SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< SMARTCARD frame odd parity */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode + * @{ + */ +#define SMARTCARD_MODE_RX USART_CR1_RE /*!< SMARTCARD RX mode */ +#define SMARTCARD_MODE_TX USART_CR1_TE /*!< SMARTCARD TX mode */ +#define SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< SMARTCARD RX and TX mode */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity + * @{ + */ +#define SMARTCARD_POLARITY_LOW 0x00000000U /*!< SMARTCARD frame low polarity */ +#define SMARTCARD_POLARITY_HIGH USART_CR2_CPOL /*!< SMARTCARD frame high polarity */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase + * @{ + */ +#define SMARTCARD_PHASE_1EDGE 0x00000000U /*!< SMARTCARD frame phase on first clock transition */ +#define SMARTCARD_PHASE_2EDGE USART_CR2_CPHA /*!< SMARTCARD frame phase on second clock transition */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit + * @{ + */ +#define SMARTCARD_LASTBIT_DISABLE 0x00000000U /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */ +#define SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */ +/** + * @} + */ + +/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method + * @{ + */ +#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< SMARTCARD frame one-bit sample disabled */ +#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< SMARTCARD frame one-bit sample enabled */ +/** + * @} + */ + +/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable + * @{ + */ +#define SMARTCARD_NACK_DISABLE 0x00000000U /*!< SMARTCARD NACK transmission disabled */ +#define SMARTCARD_NACK_ENABLE USART_CR3_NACK /*!< SMARTCARD NACK transmission enabled */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable + * @{ + */ +#define SMARTCARD_TIMEOUT_DISABLE 0x00000000U /*!< SMARTCARD receiver timeout disabled */ +#define SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< SMARTCARD receiver timeout enabled */ +/** + * @} + */ + +/** @defgroup SMARTCARD_ClockPrescaler SMARTCARD Clock Prescaler + * @{ + */ +#define SMARTCARD_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define SMARTCARD_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define SMARTCARD_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define SMARTCARD_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define SMARTCARD_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define SMARTCARD_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define SMARTCARD_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define SMARTCARD_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define SMARTCARD_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define SMARTCARD_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define SMARTCARD_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define SMARTCARD_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion + * @{ + */ +#define SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion + * @{ + */ +#define SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion + * @{ + */ +#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap + * @{ + */ +#define SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable + * @{ + */ +#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error + * @{ + */ +#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ +/** + * @} + */ + +/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first + * @{ + */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters + * @{ + */ +#define SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive data flush request */ +#define SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush request */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask + * @{ + */ +#define SMARTCARD_IT_MASK 0x001FU /*!< SMARTCARD interruptions flags mask */ +#define SMARTCARD_CR_MASK 0x00E0U /*!< SMARTCARD control register mask */ +#define SMARTCARD_CR_POS 5U /*!< SMARTCARD control register position */ +#define SMARTCARD_ISR_MASK 0x1F00U /*!< SMARTCARD ISR register mask */ +#define SMARTCARD_ISR_POS 8U /*!< SMARTCARD ISR register position */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros + * @{ + */ + +/** @brief Reset SMARTCARD handle states. + * @param __HANDLE__ SMARTCARD handle. + * @retval None + */ +#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 +#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +/** @brief Flush the Smartcard Data registers. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified SMARTCARD pending flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag + * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag + * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag + * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag + * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag + * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag + * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag + * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag + * @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the SMARTCARD PE pending flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF) + +/** @brief Clear the SMARTCARD FE pending flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF) + +/** @brief Clear the SMARTCARD NE pending flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF) + +/** @brief Clear the SMARTCARD ORE pending flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF) + +/** @brief Clear the SMARTCARD IDLE pending flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF) + +/** @brief Check whether the specified Smartcard flag is set or not. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available) + * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag + * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref SMARTCARD_FLAG_BUSY Busy flag + * @arg @ref SMARTCARD_FLAG_EOBF End of block flag + * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag + * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag + * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag + * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag + * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag + * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag + * @arg @ref SMARTCARD_FLAG_NE Noise error flag + * @arg @ref SMARTCARD_FLAG_FE Framing error flag + * @arg @ref SMARTCARD_FLAG_PE Parity error flag + * @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag + * @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag + * @arg @ref SMARTCARD_FLAG_TXFE TXFIFO Empty flag + * @arg @ref SMARTCARD_FLAG_RXFF RXFIFO Full flag + * @arg @ref SMARTCARD_FLAG_RXFT SMARTCARD RXFIFO threshold flag + * @arg @ref SMARTCARD_FLAG_TXFT SMARTCARD TXFIFO threshold flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enable the specified SmartCard interrupt. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before + * guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption + * @retval None + */ +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) + +/** @brief Disable the specified SmartCard interrupt. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard + * time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption + * @retval None + */ +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) + +/** @brief Check whether the specified SmartCard interrupt has occurred or not. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to check. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\ + (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\ + & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\ + ? SET : RESET) + +/** @brief Check whether the specified SmartCard interrupt source is enabled or not. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x01U)?\ + (__HANDLE__)->Instance->CR1 : \ + (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x02U)?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) &\ + (0x01UL << (((uint16_t)(__INTERRUPT__))\ + & SMARTCARD_IT_MASK))) != 0U)\ + ? SET : RESET) + +/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag + * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag + * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag + * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag + * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag + * @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag + * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag + * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available) + * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific SMARTCARD request flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request + * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the SMARTCARD one bit sample method. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the SMARTCARD one bit sample method. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) + +/** @brief Enable the USART associated to the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable the USART associated to the SMARTCARD Handle + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** + * @} + */ + +/* Private macros -------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros + * @{ + */ + +/** @brief Report the SMARTCARD clock source. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. + */ +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART1CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;\ + break; \ + } \ + } \ + else if(((__HANDLE__)->Instance == USART2) || \ + ((__HANDLE__)->Instance == USART3)) \ + { \ + switch(__HAL_RCC_GET_USART234578_SOURCE()) \ + { \ + case RCC_USART234578CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART234578CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART234578CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART234578CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART234578CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART234578CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;\ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) + + +/** @brief Check the Baud rate range. + * @note The maximum Baud Rate is derived from the maximum clock on H7RS (100 MHz) + * divided by the oversampling used on the SMARTCARD (i.e. 16). + * @param __BAUDRATE__ Baud rate set by the configuration function. + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6250001U) + +/** @brief Check the block length range. + * @note The maximum SMARTCARD block length is 0xFF. + * @param __LENGTH__ block length. + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU) + +/** @brief Check the receiver timeout value. + * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) + +/** @brief Check the SMARTCARD autoretry counter value. + * @note The maximum number of retransmissions is 0x7. + * @param __COUNT__ number of retransmissions. + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U) + +/** @brief Ensure that SMARTCARD frame length is valid. + * @param __LENGTH__ SMARTCARD frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) + +/** @brief Ensure that SMARTCARD frame number of stop bits is valid. + * @param __STOPBITS__ SMARTCARD frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\ + ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)) + +/** @brief Ensure that SMARTCARD frame parity is valid. + * @param __PARITY__ SMARTCARD frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \ + ((__PARITY__) == SMARTCARD_PARITY_ODD)) + +/** @brief Ensure that SMARTCARD communication mode is valid. + * @param __MODE__ SMARTCARD communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) + +/** @brief Ensure that SMARTCARD frame polarity is valid. + * @param __CPOL__ SMARTCARD frame polarity. + * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) + */ +#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\ + || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) + +/** @brief Ensure that SMARTCARD frame phase is valid. + * @param __CPHA__ SMARTCARD frame phase. + * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) + */ +#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE)) + +/** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid. + * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting. + * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) + */ +#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \ + ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE)) + +/** @brief Ensure that SMARTCARD frame sampling is valid. + * @param __ONEBIT__ SMARTCARD frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE)) + +/** @brief Ensure that SMARTCARD NACK transmission setting is valid. + * @param __NACK__ SMARTCARD NACK transmission setting. + * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid) + */ +#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \ + ((__NACK__) == SMARTCARD_NACK_DISABLE)) + +/** @brief Ensure that SMARTCARD receiver timeout setting is valid. + * @param __TIMEOUT__ SMARTCARD receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE)) + +/** @brief Ensure that SMARTCARD clock Prescaler is valid. + * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256)) + +/** @brief Ensure that SMARTCARD advanced features initialization is valid. + * @param __INIT__ SMARTCARD advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \ + SMARTCARD_ADVFEATURE_TXINVERT_INIT | \ + SMARTCARD_ADVFEATURE_RXINVERT_INIT | \ + SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \ + SMARTCARD_ADVFEATURE_SWAP_INIT | \ + SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \ + SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) + +/** @brief Ensure that SMARTCARD frame TX inversion setting is valid. + * @param __TXINV__ SMARTCARD frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE)) + +/** @brief Ensure that SMARTCARD frame RX inversion setting is valid. + * @param __RXINV__ SMARTCARD frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE)) + +/** @brief Ensure that SMARTCARD frame data inversion setting is valid. + * @param __DATAINV__ SMARTCARD frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE)) + +/** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid. + * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE)) + +/** @brief Ensure that SMARTCARD frame overrun setting is valid. + * @param __OVERRUN__ SMARTCARD frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE)) + +/** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid. + * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR)) + +/** @brief Ensure that SMARTCARD frame MSB first setting is valid. + * @param __MSBFIRST__ SMARTCARD frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE)) + +/** @brief Ensure that SMARTCARD request parameter is valid. + * @param __PARAM__ SMARTCARD request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST)) + +/** + * @} + */ + +/* Include SMARTCARD HAL Extended module */ +#include "stm32h7rsxx_hal_smartcard_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMARTCARD_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/** @addtogroup SMARTCARD_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup SMARTCARD_Exported_Functions_Group2 + * @{ + */ + +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard); + +void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); + +/** + * @} + */ + +/* Peripheral State and Error functions ***************************************/ +/** @addtogroup SMARTCARD_Exported_Functions_Group4 + * @{ + */ + +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard); +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_SMARTCARD_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_smartcard_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_smartcard_ex.h new file mode 100644 index 00000000000..bfcbe271774 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_smartcard_ex.h @@ -0,0 +1,336 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_smartcard_ex.h + * @author MCD Application Team + * @brief Header file of SMARTCARD HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_SMARTCARD_EX_H +#define STM32H7RSxx_HAL_SMARTCARD_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup SMARTCARDEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants + * @{ + */ + +/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication + * @{ + */ +#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */ +#define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type + * @{ + */ +#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ +#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U /*!< TX completion indication before of after guard time */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode + * @brief SMARTCARD FIFO mode + * @{ + */ +#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level + * @brief SMARTCARD TXFIFO level + * @{ + */ +#define SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level + * @brief SMARTCARD RXFIFO level + * @{ + */ +#define SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */ +#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */ +#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */ +#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */ +#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */ +#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */ +#define SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF /*!< SMARTCARD transmit data register empty */ +#define SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< SMARTCARD TXFIFO not full */ +#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */ +#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD read data register not empty */ +#define SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD RXFIFO not empty */ +#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */ +#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */ +#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */ +#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */ +#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */ +#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE /*!< SMARTCARD TXFIFO Empty flag */ +#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF /*!< SMARTCARD RXFIFO Full flag */ +#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT /*!< SMARTCARD RXFIFO threshold flag */ +#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT /*!< SMARTCARD TXFIFO threshold flag */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition + * Elements values convention: 000ZZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5 bits) + * - XX : Interrupt source register (2 bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZZ : Flag position in the ISR register(5 bits) + * @{ + */ +#define SMARTCARD_IT_PE 0x0028U /*!< SMARTCARD parity error interruption */ +#define SMARTCARD_IT_TXE 0x0727U /*!< SMARTCARD transmit data register empty interruption */ +#define SMARTCARD_IT_TXFNF 0x0727U /*!< SMARTCARD TX FIFO not full interruption */ +#define SMARTCARD_IT_TC 0x0626U /*!< SMARTCARD transmission complete interruption */ +#define SMARTCARD_IT_RXNE 0x0525U /*!< SMARTCARD read data register not empty interruption */ +#define SMARTCARD_IT_RXFNE 0x0525U /*!< SMARTCARD RXFIFO not empty interruption */ +#define SMARTCARD_IT_IDLE 0x0424U /*!< SMARTCARD idle line detection interruption */ + +#define SMARTCARD_IT_ERR 0x0060U /*!< SMARTCARD error interruption */ +#define SMARTCARD_IT_ORE 0x0300U /*!< SMARTCARD overrun error interruption */ +#define SMARTCARD_IT_NE 0x0200U /*!< SMARTCARD noise error interruption */ +#define SMARTCARD_IT_FE 0x0100U /*!< SMARTCARD frame error interruption */ + +#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */ +#define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */ +#define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */ + +#define SMARTCARD_IT_RXFF 0x183FU /*!< SMARTCARD RXFIFO full interruption */ +#define SMARTCARD_IT_TXFE 0x173EU /*!< SMARTCARD TXFIFO empty interruption */ +#define SMARTCARD_IT_RXFT 0x1A7CU /*!< SMARTCARD RXFIFO threshold reached interruption */ +#define SMARTCARD_IT_TXFT 0x1B77U /*!< SMARTCARD TXFIFO threshold reached interruption */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags + * @{ + */ +#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */ +#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */ +#define SMARTCARD_CLEAR_NEF USART_ICR_NECF /*!< SMARTCARD noise error detected clear flag */ +#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */ +#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */ +#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty Clear Flag */ +#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */ +#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */ +#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */ +#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macros -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros + * @{ + */ + +/** @brief Set the Transmission Completion flag + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if + * AdvancedInit.TxCompletionIndication is not already filled, the latter is forced + * to SMARTCARD_TC (transmission completion indication when guard time has elapsed). + * @retval None + */ +#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ + do { \ + if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ + { \ + (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ + } \ + else \ + { \ + assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \ + } \ + } while(0U) + +/** @brief Return the transmission completion flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag. + * When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is + * reported. + * @retval Transmission completion flag + */ +#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \ + (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT)) + + +/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid. + * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag. + * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid) + */ +#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \ + ((__TXCOMPLETE__) == SMARTCARD_TC)) + +/** @brief Ensure that SMARTCARD FIFO mode is valid. + * @param __STATE__ SMARTCARD FIFO mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \ + ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE)) + +/** @brief Ensure that SMARTCARD TXFIFO threshold level is valid. + * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8)) + +/** @brief Ensure that SMARTCARD RXFIFO threshold level is valid. + * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMARTCARDEx_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/* IO operation methods *******************************************************/ + +/** @addtogroup SMARTCARDEx_Exported_Functions_Group1 + * @{ + */ + +/* Peripheral Control functions ***********************************************/ +void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength); +void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue); +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMARTCARDEx_Exported_Functions_Group2 + * @{ + */ + +/* IO operation functions *****************************************************/ +void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard); + +/** + * @} + */ + +/** @addtogroup SMARTCARDEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold); +HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_SMARTCARD_EX_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_smbus.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_smbus.h new file mode 100644 index 00000000000..e3e7d959b39 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_smbus.h @@ -0,0 +1,787 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_smbus.h + * @author MCD Application Team + * @brief Header file of SMBUS HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_SMBUS_H +#define STM32H7RSxx_HAL_SMBUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup SMBUS + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SMBUS_Exported_Types SMBUS Exported Types + * @{ + */ + +/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition + * @brief SMBUS Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. + This parameter calculated by referring to SMBUS initialization section + in Reference manual */ + uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. + This parameter can be a value of @ref SMBUS_Analog_Filter */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit address. */ + + uint32_t AddressingMode; /*!< Specifies addressing mode selected. + This parameter can be a value of @ref SMBUS_addressing_mode */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref SMBUS_dual_addressing_mode */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address + if dual addressing mode is selected + This parameter can be a value of @ref SMBUS_own_address2_masks. */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref SMBUS_nostretch_mode */ + + uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. + This parameter can be a value of @ref SMBUS_packet_error_check_mode */ + + uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. + This parameter can be a value of @ref SMBUS_peripheral_mode */ + + uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. + (Enable bits and different timeout values) + This parameter calculated by referring to SMBUS initialization section + in Reference manual */ +} SMBUS_InitTypeDef; +/** + * @} + */ + +/** @defgroup HAL_state_definition HAL state definition + * @brief HAL State definition + * @{ + */ +#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ +#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ +#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ +#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ +/** + * @} + */ + +/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition + * @brief SMBUS Error Code definition + * @{ + */ +#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ +#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ +#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ +#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ +#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition + * @brief SMBUS handle Structure definition + * @{ + */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +typedef struct __SMBUS_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +{ + I2C_TypeDef *Instance; /*!< SMBUS registers base address */ + + SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ + + uint16_t XferSize; /*!< SMBUS transfer size */ + + __IO uint16_t XferCount; /*!< SMBUS transfer counter */ + + __IO uint32_t XferOptions; /*!< SMBUS transfer options */ + + __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ + + HAL_LockTypeDef Lock; /*!< SMBUS locking object */ + + __IO uint32_t State; /*!< SMBUS communication state */ + + __IO uint32_t ErrorCode; /*!< SMBUS Error code */ + +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Listen Complete callback */ + void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Error callback */ + + void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< SMBUS Slave Address Match callback */ + + void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Msp Init callback */ + void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Msp DeInit callback */ + +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +} SMBUS_HandleTypeDef; + +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SMBUS Callback ID enumeration definition + */ +typedef enum +{ + HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */ + HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */ + HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */ + HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */ + HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */ + HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */ + + HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */ + HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */ + +} HAL_SMBUS_CallbackIDTypeDef; + +/** + * @brief HAL SMBUS Callback pointer definition + */ +typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); +/*!< pointer to an SMBUS callback function */ +typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an SMBUS Address Match callback function */ + +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants + * @{ + */ + +/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter + * @{ + */ +#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U) +#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup SMBUS_addressing_mode SMBUS addressing mode + * @{ + */ +#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U) +/** + * @} + */ + +/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode + * @{ + */ + +#define SMBUS_DUALADDRESS_DISABLE (0x00000000U) +#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks + * @{ + */ + +#define SMBUS_OA2_NOMASK ((uint8_t)0x00U) +#define SMBUS_OA2_MASK01 ((uint8_t)0x01U) +#define SMBUS_OA2_MASK02 ((uint8_t)0x02U) +#define SMBUS_OA2_MASK03 ((uint8_t)0x03U) +#define SMBUS_OA2_MASK04 ((uint8_t)0x04U) +#define SMBUS_OA2_MASK05 ((uint8_t)0x05U) +#define SMBUS_OA2_MASK06 ((uint8_t)0x06U) +#define SMBUS_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + + +/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode + * @{ + */ +#define SMBUS_GENERALCALL_DISABLE (0x00000000U) +#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode + * @{ + */ +#define SMBUS_NOSTRETCH_DISABLE (0x00000000U) +#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode + * @{ + */ +#define SMBUS_PEC_DISABLE (0x00000000U) +#define SMBUS_PEC_ENABLE I2C_CR1_PECEN +/** + * @} + */ + +/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode + * @{ + */ +#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN +#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U) +#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN +/** + * @} + */ + +/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition + * @{ + */ + +#define SMBUS_SOFTEND_MODE (0x00000000U) +#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD +#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND +#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE +/** + * @} + */ + +/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition + * @{ + */ + +#define SMBUS_NO_STARTSTOP (0x00000000U) +#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/** + * @} + */ + +/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition + * @{ + */ + +/* List of XferOptions in usage of : + * 1- Restart condition when direction change + * 2- No Restart condition in other use cases + */ +#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE +#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) +#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE)) +#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) +#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) +#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) +#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) +#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) +/** + * @} + */ + +/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition + * @brief SMBUS Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define SMBUS_IT_ERRI I2C_CR1_ERRIE +#define SMBUS_IT_TCI I2C_CR1_TCIE +#define SMBUS_IT_STOPI I2C_CR1_STOPIE +#define SMBUS_IT_NACKI I2C_CR1_NACKIE +#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE +#define SMBUS_IT_RXI I2C_CR1_RXIE +#define SMBUS_IT_TXI I2C_CR1_TXIE +#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \ + SMBUS_IT_NACKI | SMBUS_IT_TXI) +#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \ + SMBUS_IT_RXI) +#define SMBUS_IT_ALERT (SMBUS_IT_ERRI) +#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) +/** + * @} + */ + +/** @defgroup SMBUS_Flag_definition SMBUS Flag definition + * @brief Flag definition + * Elements values convention: 0xXXXXYYYY + * - XXXXXXXX : Flag mask + * @{ + */ + +#define SMBUS_FLAG_TXE I2C_ISR_TXE +#define SMBUS_FLAG_TXIS I2C_ISR_TXIS +#define SMBUS_FLAG_RXNE I2C_ISR_RXNE +#define SMBUS_FLAG_ADDR I2C_ISR_ADDR +#define SMBUS_FLAG_AF I2C_ISR_NACKF +#define SMBUS_FLAG_STOPF I2C_ISR_STOPF +#define SMBUS_FLAG_TC I2C_ISR_TC +#define SMBUS_FLAG_TCR I2C_ISR_TCR +#define SMBUS_FLAG_BERR I2C_ISR_BERR +#define SMBUS_FLAG_ARLO I2C_ISR_ARLO +#define SMBUS_FLAG_OVR I2C_ISR_OVR +#define SMBUS_FLAG_PECERR I2C_ISR_PECERR +#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define SMBUS_FLAG_ALERT I2C_ISR_ALERT +#define SMBUS_FLAG_BUSY I2C_ISR_BUSY +#define SMBUS_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros + * @{ + */ + +/** @brief Reset SMBUS handle state. + * @param __HANDLE__ specifies the SMBUS Handle. + * @retval None + */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SMBUS interrupts. + * @param __HANDLE__ specifies the SMBUS Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref SMBUS_IT_ERRI Errors interrupt enable + * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable + * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable + * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable + * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable + * @arg @ref SMBUS_IT_RXI RX interrupt enable + * @arg @ref SMBUS_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified SMBUS interrupts. + * @param __HANDLE__ specifies the SMBUS Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref SMBUS_IT_ERRI Errors interrupt enable + * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable + * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable + * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable + * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable + * @arg @ref SMBUS_IT_RXI RX interrupt enable + * @arg @ref SMBUS_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified SMBUS interrupt source is enabled or not. + * @param __HANDLE__ specifies the SMBUS Handle. + * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref SMBUS_IT_ERRI Errors interrupt enable + * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable + * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable + * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable + * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable + * @arg @ref SMBUS_IT_RXI RX interrupt enable + * @arg @ref SMBUS_IT_TXI TX interrupt enable + * + * @retval The new state of __IT__ (SET or RESET). + */ +#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SMBUS flag is set or not. + * @param __HANDLE__ specifies the SMBUS Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref SMBUS_FLAG_TXE Transmit data register empty + * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status + * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty + * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) + * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_STOPF STOP detection flag + * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) + * @arg @ref SMBUS_FLAG_TCR Transfer complete reload + * @arg @ref SMBUS_FLAG_BERR Bus error + * @arg @ref SMBUS_FLAG_ARLO Arbitration lost + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_PECERR PEC error in reception + * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref SMBUS_FLAG_ALERT SMBus alert + * @arg @ref SMBUS_FLAG_BUSY Bus busy + * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define SMBUS_FLAG_MASK (0x0001FFFFU) +#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ + (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ + ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) + +/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the SMBUS Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref SMBUS_FLAG_TXE Transmit data register empty + * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) + * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_STOPF STOP detection flag + * @arg @ref SMBUS_FLAG_BERR Bus error + * @arg @ref SMBUS_FLAG_ARLO Arbitration lost + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_PECERR PEC error in reception + * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref SMBUS_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified SMBUS peripheral. + * @param __HANDLE__ specifies the SMBUS Handle. + * @retval None + */ +#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified SMBUS peripheral. + * @param __HANDLE__ specifies the SMBUS Handle. + * @retval None + */ +#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. + * @param __HANDLE__ specifies the SMBUS Handle. + * @retval None + */ +#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) + +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Macro SMBUS Private Macros + * @{ + */ + +#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ + ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) + +#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_SMBUS_ADDRESSING_MODE(MODE) ((MODE) == SMBUS_ADDRESSINGMODE_7BIT) + +#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) + +#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ + ((MASK) == SMBUS_OA2_MASK01) || \ + ((MASK) == SMBUS_OA2_MASK02) || \ + ((MASK) == SMBUS_OA2_MASK03) || \ + ((MASK) == SMBUS_OA2_MASK04) || \ + ((MASK) == SMBUS_OA2_MASK05) || \ + ((MASK) == SMBUS_OA2_MASK06) || \ + ((MASK) == SMBUS_OA2_MASK07)) + +#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ + ((CALL) == SMBUS_GENERALCALL_ENABLE)) + +#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ + ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) + +#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ + ((PEC) == SMBUS_PEC_ENABLE)) + +#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) + +#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ + ((MODE) == SMBUS_AUTOEND_MODE) || \ + ((MODE) == SMBUS_SOFTEND_MODE) || \ + ((MODE) == SMBUS_SENDPEC_MODE) || \ + ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \ + SMBUS_RELOAD_MODE ))) + + +#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ + ((REQUEST) == SMBUS_GENERATE_START_READ) || \ + ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == SMBUS_NO_STARTSTOP)) + + +#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ + ((REQUEST) == SMBUS_FIRST_FRAME) || \ + ((REQUEST) == SMBUS_NEXT_FRAME) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) + +#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) + +#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ + (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \ + I2C_CR1_PECEN))) +#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & \ + (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \ + (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + +#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) +#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) +#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) +#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) + +#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ + ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) +#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) + +#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +/** + * @} + */ + +/* Include SMBUS HAL Extended module */ +#include "stm32h7rsxx_hal_smbus_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions + * @{ + */ + +/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID, + pSMBUS_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, + pSMBUS_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup Blocking_mode_Polling Blocking mode Polling + * @{ + */ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); +/** + * @} + */ + +/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt + * @{ + */ +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); + +HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); +/** + * @} + */ + +/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ +void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); + +/** + * @} + */ + +/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus); + +/** + * @} + */ + +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Functions SMBUS Private Functions + * @{ + */ +/* Private functions are defined in stm32h7rsxx_hal_smbus.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7RSxx_HAL_SMBUS_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_smbus_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_smbus_ex.h new file mode 100644 index 00000000000..fb431e1be82 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_smbus_ex.h @@ -0,0 +1,133 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_smbus_ex.h + * @author MCD Application Team + * @brief Header file of SMBUS HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_SMBUS_EX_H +#define STM32H7RSxx_HAL_SMBUS_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup SMBUSEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants + * @{ + */ + +/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus + * @{ + */ +#define SMBUS_FASTMODEPLUS_ENABLE 0x00000000U /*!< Enable Fast Mode Plus */ +#define SMBUS_FASTMODEPLUS_DISABLE 0x00000001U /*!< Disable Fast Mode Plus */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @addtogroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus); +/** + * @} + */ + +/** @addtogroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ +HAL_StatusTypeDef HAL_SMBUSEx_ConfigFastModePlus(SMBUS_HandleTypeDef *hsmbus, uint32_t FastModePlus); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros + * @{ + */ +#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (SMBUS_FASTMODEPLUS_ENABLE)) || \ + ((__CONFIG__) == (SMBUS_FASTMODEPLUS_DISABLE))) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32h7rsxx_hal_smbus_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_SMBUS_EX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_spdifrx.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_spdifrx.h new file mode 100644 index 00000000000..59f72446698 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_spdifrx.h @@ -0,0 +1,622 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_spdifrx.h + * @author MCD Application Team + * @brief Header file of SPDIFRX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_SPDIFRX_H +#define STM32H7RSxx_HAL_SPDIFRX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#if defined (SPDIFRX) + +/** @addtogroup SPDIFRX + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types + * @{ + */ + +/** + * @brief SPDIFRX Init structure definition + */ +typedef struct +{ + uint32_t InputSelection; /*!< Specifies the SPDIF input selection. + This parameter can be a value of @ref SPDIFRX_Input_Selection */ + + uint32_t Retries; /*!< Specifies the Maximum allowed re-tries during synchronization phase. + This parameter can be a value of @ref SPDIFRX_Max_Retries */ + + uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input. + This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */ + + uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status + from channel A or B. + This parameter can be a value of @ref SPDIFRX_Channel_Selection */ + + uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...). + This parameter can be a value of @ref SPDIFRX_Data_Format */ + + uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode. + This parameter can be a value of @ref SPDIFRX_Stereo_Mode */ + + uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not + into the received frame. + This parameter can be a value of @ref SPDIFRX_PT_Mask */ + + uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not + into the received frame. + This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ + + uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame. + This parameter can be a value of @ref SPDIFRX_V_Mask */ + + uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not + into the received frame. + This parameter can be a value of @ref SPDIFRX_PE_Mask */ + FunctionalState SymbolClockGen; /*!< Enable/Disable the SPDIFRX Symbol Clock generation. + This parameter can be set to Enable or Disable */ + + FunctionalState BackupSymbolClockGen; /*!< Enable/Disable the SPDIFRX Backup Symbol Clock generation. + This parameter can be set to Enable or Disable */ +} SPDIFRX_InitTypeDef; + +/** + * @brief SPDIFRX SetDataFormat structure definition + */ +typedef struct +{ + uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...). + This parameter can be a value of @ref SPDIFRX_Data_Format */ + + uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode. + This parameter can be a value of @ref SPDIFRX_Stereo_Mode */ + + uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not + into the received frame. + This parameter can be a value of @ref SPDIFRX_PT_Mask */ + + uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not + into the received frame. + This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ + + uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame. + This parameter can be a value of @ref SPDIFRX_V_Mask */ + + uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not + into the received frame. + This parameter can be a value of @ref SPDIFRX_PE_Mask */ + +} SPDIFRX_SetDataFormatTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_SPDIFRX_STATE_RESET = 0x00U, /*!< SPDIFRX not yet initialized or disabled */ + HAL_SPDIFRX_STATE_READY = 0x01U, /*!< SPDIFRX initialized and ready for use */ + HAL_SPDIFRX_STATE_BUSY = 0x02U, /*!< SPDIFRX internal process is ongoing */ + HAL_SPDIFRX_STATE_BUSY_RX = 0x03U, /*!< SPDIFRX internal Data Flow RX process is ongoing */ + HAL_SPDIFRX_STATE_BUSY_CX = 0x04U, /*!< SPDIFRX internal Control Flow RX process is ongoing */ + HAL_SPDIFRX_STATE_ERROR = 0x07U /*!< SPDIFRX error state */ +} HAL_SPDIFRX_StateTypeDef; + +/** + * @brief SPDIFRX handle Structure definition + */ +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) +typedef struct __SPDIFRX_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ +{ + SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */ + + SPDIFRX_InitTypeDef Init; /* SPDIFRX communication parameters */ + + uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */ + + uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */ + + __IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */ + + __IO uint16_t RxXferCount; /* SPDIFRX Rx transfer counter + (This field is initialized at the + same value as transfer size at the + beginning of the transfer and + decremented when a sample is received. + NbSamplesReceived = RxBufferSize-RxBufferCount) */ + + __IO uint16_t CsXferSize; /* SPDIFRX Rx transfer size */ + + __IO uint16_t CsXferCount; /* SPDIFRX Rx transfer counter + (This field is initialized at the + same value as transfer size at the + beginning of the transfer and + decremented when a sample is received. + NbSamplesReceived = RxBufferSize-RxBufferCount) */ + + DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information + DMA handle parameters */ + + DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */ + + __IO HAL_LockTypeDef Lock; /* SPDIFRX locking object */ + + __IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */ + + __IO uint32_t ErrorCode; /* SPDIFRX Error code */ + +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) + void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed + callback */ + void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow completed callback */ + void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed + callback */ + void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow completed callback */ + void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX error callback */ + void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp Init callback */ + void (* MspDeInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp DeInit callback */ +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ + +} SPDIFRX_HandleTypeDef; + +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SPDIFRX Callback ID enumeration definition + */ +typedef enum +{ + HAL_SPDIFRX_RX_HALF_CB_ID = 0x00U, /*!< SPDIFRX Data flow half completed callback ID */ + HAL_SPDIFRX_RX_CPLT_CB_ID = 0x01U, /*!< SPDIFRX Data flow completed callback */ + HAL_SPDIFRX_CX_HALF_CB_ID = 0x02U, /*!< SPDIFRX Control flow half completed callback */ + HAL_SPDIFRX_CX_CPLT_CB_ID = 0x03U, /*!< SPDIFRX Control flow completed callback */ + HAL_SPDIFRX_ERROR_CB_ID = 0x04U, /*!< SPDIFRX error callback */ + HAL_SPDIFRX_MSPINIT_CB_ID = 0x05U, /*!< SPDIFRX Msp Init callback ID */ + HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U /*!< SPDIFRX Msp DeInit callback ID */ +} HAL_SPDIFRX_CallbackIDTypeDef; + +/** + * @brief HAL SPDIFRX Callback pointer definition + */ +typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback + function */ +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants + * @{ + */ +/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code + * @{ + */ +#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ +#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U) /*!< OVR error */ +#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U) /*!< Parity error */ +#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */ +#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U) /*!< Unknown Error error */ +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) +#define HAL_SPDIFRX_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection + * @{ + */ +#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U) +#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U) +#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U) +#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U) +/** + * @} + */ + +/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries + * @{ + */ +#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U) +#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U) +#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U) +#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U) +/** + * @} + */ + +/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity + * @{ + */ +#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U) +#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA) +/** + * @} + */ + +/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask + * @{ + */ +#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U) +#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK) +/** + * @} + */ + +/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask + * @{ + */ +#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied + into the SPDIF_DR */ +#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied + into the SPDIF_DR, zeros are written instead*/ +/** + * @} + */ + +/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask + * @{ + */ +#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U) +#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK) +/** + * @} + */ + +/** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask + * @{ + */ +#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U) +#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK) +/** + * @} + */ + +/** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection + * @{ + */ +#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U) +#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL) +/** + * @} + */ + +/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format + * @{ + */ +#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U) +#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U) +#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U) +/** + * @} + */ + +/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode + * @{ + */ +#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U) +#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO) +/** + * @} + */ + +/** @defgroup SPDIFRX_State SPDIFRX State + * @{ + */ + +#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU) +#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U) +#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFRXEN) +/** + * @} + */ + +/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition + * @{ + */ +#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE) +#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE) +#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE) +#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE) +#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE) +#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE) +#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE ) +/** + * @} + */ + +/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition + * @{ + */ +#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE) +#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE) +#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR) +#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR) +#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD) +#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD) +#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR) +#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR) +#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros + * @{ + */ + +/** @brief Reset SPDIFRX handle state + * @param __HANDLE__ SPDIFRX handle. + * @retval None + */ +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) +#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0) +#else +#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET) +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ + +/** @brief Disable the specified SPDIFRX peripheral (IDLE State). + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @retval None + */ +#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE) + +/** @brief Enable the specified SPDIFRX peripheral (SYNC State). + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @retval None + */ +#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC) + + +/** @brief Enable the specified SPDIFRX peripheral (RCV State). + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @retval None + */ +#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV) + + +/** @brief Enable or disable the specified SPDIFRX interrupts. + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SPDIFRX_IT_RXNE + * @arg SPDIFRX_IT_CSRNE + * @arg SPDIFRX_IT_PERRIE + * @arg SPDIFRX_IT_OVRIE + * @arg SPDIFRX_IT_SBLKIE + * @arg SPDIFRX_IT_SYNCDIE + * @arg SPDIFRX_IT_IFEIE + * @retval None + */ +#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) +#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR\ + &= (uint16_t)(~(__INTERRUPT__))) + +/** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @param __INTERRUPT__ specifies the SPDIFRX interrupt source to check. + * This parameter can be one of the following values: + * @arg SPDIFRX_IT_RXNE + * @arg SPDIFRX_IT_CSRNE + * @arg SPDIFRX_IT_PERRIE + * @arg SPDIFRX_IT_OVRIE + * @arg SPDIFRX_IT_SBLKIE + * @arg SPDIFRX_IT_SYNCDIE + * @arg SPDIFRX_IT_IFEIE + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified SPDIFRX flag is set or not. + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPDIFRX_FLAG_RXNE + * @arg SPDIFRX_FLAG_CSRNE + * @arg SPDIFRX_FLAG_PERR + * @arg SPDIFRX_FLAG_OVR + * @arg SPDIFRX_FLAG_SBD + * @arg SPDIFRX_FLAG_SYNCD + * @arg SPDIFRX_FLAG_FERR + * @arg SPDIFRX_FLAG_SERR + * @arg SPDIFRX_FLAG_TERR + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\ + & (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit. + * @param __HANDLE__ specifies the USART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg SPDIFRX_FLAG_PERR + * @arg SPDIFRX_FLAG_OVR + * @arg SPDIFRX_SR_SBD + * @arg SPDIFRX_SR_SYNCD + * @retval None + */ +#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPDIFRX_Exported_Functions + * @{ + */ + +/** @addtogroup SPDIFRX_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif); +HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif); +void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif); +void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif); +HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, + pSPDIFRX_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, + HAL_SPDIFRX_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SPDIFRX_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); +void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif); + +/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ +void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif); +void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif); +void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif); +void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif); +void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif); +/** + * @} + */ + +/** @addtogroup SPDIFRX_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control and State functions ************************************/ +HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif); +uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros + * @{ + */ +#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \ + ((INPUT) == SPDIFRX_INPUT_IN2) || \ + ((INPUT) == SPDIFRX_INPUT_IN3) || \ + ((INPUT) == SPDIFRX_INPUT_IN0)) + +#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \ + ((RET) == SPDIFRX_MAXRETRIES_3) || \ + ((RET) == SPDIFRX_MAXRETRIES_15) || \ + ((RET) == SPDIFRX_MAXRETRIES_63)) + +#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \ + ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF)) + +#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \ + ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF)) + +#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \ + ((VAL) == SPDIFRX_VALIDITYMASK_ON)) + +#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \ + ((VAL) == SPDIFRX_PARITYERRORMASK_ON)) + +#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \ + ((CHANNEL) == SPDIFRX_CHANNEL_B)) + +#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \ + ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \ + ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS)) + +#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \ + ((MODE) == SPDIFRX_STEREOMODE_ENABLE)) + +#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \ + ((VAL) == SPDIFRX_CHANNELSTATUS_OFF)) + +#define IS_SYMBOL_CLOCK_GEN(VAL) (((VAL) == ENABLE) || ((VAL) == DISABLE)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ +#endif /* SPDIFRX */ +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7RSxx_HAL_SPDIFRX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_spi.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_spi.h new file mode 100644 index 00000000000..5d284be5451 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_spi.h @@ -0,0 +1,1128 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_spi.h + * @author MCD Application Team + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_SPI_H +#define STM32H7RSxx_HAL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_Mode */ + + uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. + This parameter can be a value of @ref SPI_Direction */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_Data_Size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of + @ref SPI_Slave_Select_Management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_Transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_Mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be an odd number between + Min_Data = 0 and Max_Data = 65535 */ + + uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. + This parameter can be a value of @ref SPI_CRC_length */ + + uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . + This parameter can be a value of @ref SPI_NSSP_Mode + This mode is activated by the SSOM bit in the SPIx_CR2 register + and it takes effect only if the SPI interface is configured + as Motorola SPI master (FRF=0). */ + + uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal + (present on SS pin) is considered as active one. + This parameter can be a value of @ref SPI_NSS_Polarity */ + + uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref SPI_Fifo_Threshold */ + + uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for + the CRC calculation. This parameter can be a value of + @ref SPI_CRC_Calculation_Initialization_Pattern */ + + uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for + the CRC calculation. This parameter can be a value of + @ref SPI_CRC_Calculation_Initialization_Pattern */ + + uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle + periods, inserted additionally between active edge of SS + and first data transaction start in master mode. + This parameter can be a value of @ref SPI_Master_SS_Idleness */ + + uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) + inserted between two consecutive data frames in master mode. + This parameter can be a value of + @ref SPI_Master_InterData_Idleness */ + + uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode + and automatic management in order to avoid overrun condition. + This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/ + + uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state + This parameter can be a value of @ref SPI_Master_Keep_IO_State */ + + uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions + This parameter can be a value of @ref SPI_IO_Swap */ + + uint32_t ReadyMasterManagement; /*!< Specifies if RDY Signal is managed internally or not. + This parameter can be a value of @ref SPI_RDY_Master_Management */ + + uint32_t ReadyPolarity; /*!< Specifies which level of RDY Signal input (present on RDY pin) + is considered as active one. + This parameter can be a value of @ref SPI_RDY_Polarity */ +} SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00UL, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01UL, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02UL, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x06UL, /*!< SPI error state */ + HAL_SPI_STATE_ABORT = 0x07UL /*!< SPI abort is ongoing */ +} HAL_SPI_StateTypeDef; + + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< SPI registers base address */ + + SPI_InitTypeDef Init; /*!< SPI communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + + uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ + + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ + + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ + + __IO uint32_t ErrorCode; /*!< SPI Error code */ + + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ + void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ + void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ + void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ + void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ + void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ + void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* SuspendCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Suspend callback */ + void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ + void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} SPI_HandleTypeDef; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +/** + * @brief HAL SPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, /*!< SPI Tx Completed callback ID */ + HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, /*!< SPI Rx Completed callback ID */ + HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< SPI TxRx Completed callback ID */ + HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< SPI Tx Half Completed callback ID */ + HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< SPI Rx Half Completed callback ID */ + HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */ + HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */ + HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */ + HAL_SPI_SUSPEND_CB_ID = 0x08UL, /*!< SPI Suspend callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x09UL, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x0AUL /*!< SPI Msp DeInit callback ID */ + +} HAL_SPI_CallbackIDTypeDef; + +/** + * @brief HAL SPI Callback pointer definition + */ +typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_FIFO_Type SPI FIFO Type + * @{ + */ +#define SPI_LOWEND_FIFO_SIZE 8UL +#define SPI_HIGHEND_FIFO_SIZE 16UL +/** + * @} + */ + +/** @defgroup SPI_Error_Code SPI Error Codes + * @{ + */ +#define HAL_SPI_ERROR_NONE (0x00000000UL) /*!< No error */ +#define HAL_SPI_ERROR_MODF (0x00000001UL) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC (0x00000002UL) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXP/TXP/DXP/FTLVL/FRLVL Flag */ +#define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */ +#define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */ +#define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */ +#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */ +#define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00001000UL) /*!< Invalid Callback error */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Mode SPI Mode + * @{ + */ +#define SPI_MODE_SLAVE (0x00000000UL) +#define SPI_MODE_MASTER SPI_CFG2_MASTER +/** + * @} + */ + +/** @defgroup SPI_Direction SPI Direction Mode + * @{ + */ +#define SPI_DIRECTION_2LINES (0x00000000UL) +#define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0 +#define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1 +#define SPI_DIRECTION_1LINE SPI_CFG2_COMM +/** + * @} + */ + +/** @defgroup SPI_Data_Size SPI Data Size + * @{ + */ +#define SPI_DATASIZE_4BIT (0x00000003UL) +#define SPI_DATASIZE_5BIT (0x00000004UL) +#define SPI_DATASIZE_6BIT (0x00000005UL) +#define SPI_DATASIZE_7BIT (0x00000006UL) +#define SPI_DATASIZE_8BIT (0x00000007UL) +#define SPI_DATASIZE_9BIT (0x00000008UL) +#define SPI_DATASIZE_10BIT (0x00000009UL) +#define SPI_DATASIZE_11BIT (0x0000000AUL) +#define SPI_DATASIZE_12BIT (0x0000000BUL) +#define SPI_DATASIZE_13BIT (0x0000000CUL) +#define SPI_DATASIZE_14BIT (0x0000000DUL) +#define SPI_DATASIZE_15BIT (0x0000000EUL) +#define SPI_DATASIZE_16BIT (0x0000000FUL) +#define SPI_DATASIZE_17BIT (0x00000010UL) +#define SPI_DATASIZE_18BIT (0x00000011UL) +#define SPI_DATASIZE_19BIT (0x00000012UL) +#define SPI_DATASIZE_20BIT (0x00000013UL) +#define SPI_DATASIZE_21BIT (0x00000014UL) +#define SPI_DATASIZE_22BIT (0x00000015UL) +#define SPI_DATASIZE_23BIT (0x00000016UL) +#define SPI_DATASIZE_24BIT (0x00000017UL) +#define SPI_DATASIZE_25BIT (0x00000018UL) +#define SPI_DATASIZE_26BIT (0x00000019UL) +#define SPI_DATASIZE_27BIT (0x0000001AUL) +#define SPI_DATASIZE_28BIT (0x0000001BUL) +#define SPI_DATASIZE_29BIT (0x0000001CUL) +#define SPI_DATASIZE_30BIT (0x0000001DUL) +#define SPI_DATASIZE_31BIT (0x0000001EUL) +#define SPI_DATASIZE_32BIT (0x0000001FUL) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW (0x00000000UL) +#define SPI_POLARITY_HIGH SPI_CFG2_CPOL +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE (0x00000000UL) +#define SPI_PHASE_2EDGE SPI_CFG2_CPHA +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_Management SPI Slave Select Management + * @{ + */ +#define SPI_NSS_SOFT SPI_CFG2_SSM +#define SPI_NSS_HARD_INPUT (0x00000000UL) +#define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE +/** + * @} + */ + +/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode + * @{ + */ +#define SPI_NSS_PULSE_DISABLE (0x00000000UL) +#define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_BYPASS (0x80000000UL) +#define SPI_BAUDRATEPRESCALER_2 (0x00000000UL) +#define SPI_BAUDRATEPRESCALER_4 (0x10000000UL) +#define SPI_BAUDRATEPRESCALER_8 (0x20000000UL) +#define SPI_BAUDRATEPRESCALER_16 (0x30000000UL) +#define SPI_BAUDRATEPRESCALER_32 (0x40000000UL) +#define SPI_BAUDRATEPRESCALER_64 (0x50000000UL) +#define SPI_BAUDRATEPRESCALER_128 (0x60000000UL) +#define SPI_BAUDRATEPRESCALER_256 (0x70000000UL) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB (0x00000000UL) +#define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST +/** + * @} + */ + +/** @defgroup SPI_TI_Mode SPI TI Mode + * @{ + */ +#define SPI_TIMODE_DISABLE (0x00000000UL) +#define SPI_TIMODE_ENABLE SPI_CFG2_SP_0 +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE (0x00000000UL) +#define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN +/** + * @} + */ + +/** @defgroup SPI_CRC_length SPI CRC Length + * @{ + */ +#define SPI_CRC_LENGTH_DATASIZE (0x00000000UL) +#define SPI_CRC_LENGTH_4BIT (0x00030000UL) +#define SPI_CRC_LENGTH_5BIT (0x00040000UL) +#define SPI_CRC_LENGTH_6BIT (0x00050000UL) +#define SPI_CRC_LENGTH_7BIT (0x00060000UL) +#define SPI_CRC_LENGTH_8BIT (0x00070000UL) +#define SPI_CRC_LENGTH_9BIT (0x00080000UL) +#define SPI_CRC_LENGTH_10BIT (0x00090000UL) +#define SPI_CRC_LENGTH_11BIT (0x000A0000UL) +#define SPI_CRC_LENGTH_12BIT (0x000B0000UL) +#define SPI_CRC_LENGTH_13BIT (0x000C0000UL) +#define SPI_CRC_LENGTH_14BIT (0x000D0000UL) +#define SPI_CRC_LENGTH_15BIT (0x000E0000UL) +#define SPI_CRC_LENGTH_16BIT (0x000F0000UL) +#define SPI_CRC_LENGTH_17BIT (0x00100000UL) +#define SPI_CRC_LENGTH_18BIT (0x00110000UL) +#define SPI_CRC_LENGTH_19BIT (0x00120000UL) +#define SPI_CRC_LENGTH_20BIT (0x00130000UL) +#define SPI_CRC_LENGTH_21BIT (0x00140000UL) +#define SPI_CRC_LENGTH_22BIT (0x00150000UL) +#define SPI_CRC_LENGTH_23BIT (0x00160000UL) +#define SPI_CRC_LENGTH_24BIT (0x00170000UL) +#define SPI_CRC_LENGTH_25BIT (0x00180000UL) +#define SPI_CRC_LENGTH_26BIT (0x00190000UL) +#define SPI_CRC_LENGTH_27BIT (0x001A0000UL) +#define SPI_CRC_LENGTH_28BIT (0x001B0000UL) +#define SPI_CRC_LENGTH_29BIT (0x001C0000UL) +#define SPI_CRC_LENGTH_30BIT (0x001D0000UL) +#define SPI_CRC_LENGTH_31BIT (0x001E0000UL) +#define SPI_CRC_LENGTH_32BIT (0x001F0000UL) +/** + * @} + */ + +/** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold + * @{ + */ +#define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL) +#define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL) +#define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL) +#define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL) +#define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL) +#define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL) +#define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL) +#define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL) +#define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL) +#define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL) +#define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL) +#define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL) +#define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL) +#define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL) +#define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL) +#define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL) +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern + * @{ + */ +#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL) +#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL) +/** + * @} + */ + +/** @defgroup SPI_NSS_Polarity SPI NSS Polarity + * @{ + */ +#define SPI_NSS_POLARITY_LOW (0x00000000UL) +#define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP +/** + * @} + */ + +/** @defgroup SPI_Master_Keep_IO_State Keep IO State + * @{ + */ +#define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL) +#define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR +/** + * @} + */ + +/** @defgroup SPI_IO_Swap Control SPI IO Swap + * @{ + */ +#define SPI_IO_SWAP_DISABLE (0x00000000UL) +#define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP +/** + * @} + */ + +/** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness + * @{ + */ +#define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL) +#define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL) +#define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL) +#define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL) +#define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL) +#define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL) +#define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL) +#define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL) +#define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL) +#define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL) +#define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL) +#define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL) +#define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL) +#define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL) +#define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL) +#define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL) +/** + * @} + */ + +/** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness + * @{ + */ +#define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL) +#define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL) +#define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL) +#define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL) +#define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL) +#define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL) +#define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL) +#define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL) +#define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL) +#define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL) +#define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL) +/** + * @} + */ + +/** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend + * @{ + */ +#define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL) +#define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX +/** + * @} + */ + +/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior + * @{ + */ +#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL) +#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG +/** + * @} + */ + +/** @defgroup SPI_RDY_Master_Management SPI RDY Signal Input Master Management + * @{ + */ +#define SPI_RDY_MASTER_MANAGEMENT_INTERNALLY (0x00000000UL) +#define SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY SPI_CFG2_RDIOM +/** + * @} + */ + +/** @defgroup SPI_RDY_Polarity SPI RDY Signal Input/Output Polarity + * @{ + */ +#define SPI_RDY_POLARITY_HIGH (0x00000000UL) +#define SPI_RDY_POLARITY_LOW SPI_CFG2_RDIOP +/** + * @} + */ + +/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition + * @{ + */ +#define SPI_IT_RXP SPI_IER_RXPIE +#define SPI_IT_TXP SPI_IER_TXPIE +#define SPI_IT_DXP SPI_IER_DXPIE +#define SPI_IT_EOT SPI_IER_EOTIE +#define SPI_IT_TXTF SPI_IER_TXTFIE +#define SPI_IT_UDR SPI_IER_UDRIE +#define SPI_IT_OVR SPI_IER_OVRIE +#define SPI_IT_CRCERR SPI_IER_CRCEIE +#define SPI_IT_FRE SPI_IER_TIFREIE +#define SPI_IT_MODF SPI_IER_MODFIE +#define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR) +/** + * @} + */ + +/** @defgroup SPI_Flags_definition SPI Flags Definition + * @{ + */ +#define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */ +#define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */ +#define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */ +#define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */ +#define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */ +#define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */ +#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */ +#define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */ +#define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */ +#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */ +#define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */ +#define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */ +#define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */ +#define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */ +/** + * @} + */ + +/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level + * @{ + */ +#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */ +#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) +#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) +#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @retval None + */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SPI_IT_RXP : Rx-Packet available interrupt + * @arg SPI_IT_TXP : Tx-Packet space available interrupt + * @arg SPI_IT_DXP : Duplex Packet interrupt + * @arg SPI_IT_EOT : End of transfer interrupt + * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt + * @arg SPI_IT_UDR : Underrun interrupt + * @arg SPI_IT_OVR : Overrun interrupt + * @arg SPI_IT_CRCERR : CRC error interrupt + * @arg SPI_IT_FRE : TI mode frame format error interrupt + * @arg SPI_IT_MODF : Mode fault interrupt + * @arg SPI_IT_ERR : Error interrupt + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SPI_IT_RXP : Rx-Packet available interrupt + * @arg SPI_IT_TXP : Tx-Packet space available interrupt + * @arg SPI_IT_DXP : Duplex Packet interrupt + * @arg SPI_IT_EOT : End of transfer interrupt + * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt + * @arg SPI_IT_UDR : Underrun interrupt + * @arg SPI_IT_OVR : Overrun interrupt + * @arg SPI_IT_CRCERR : CRC error interrupt + * @arg SPI_IT_FRE : TI mode frame format error interrupt + * @arg SPI_IT_MODF : Mode fault interrupt + * @arg SPI_IT_ERR : Error interrupt + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified SPI interrupt source is enabled or not. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_RXP : Rx-Packet available interrupt + * @arg SPI_IT_TXP : Tx-Packet space available interrupt + * @arg SPI_IT_DXP : Duplex Packet interrupt + * @arg SPI_IT_EOT : End of transfer interrupt + * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt + * @arg SPI_IT_UDR : Underrun interrupt + * @arg SPI_IT_OVR : Overrun interrupt + * @arg SPI_IT_CRCERR : CRC error interrupt + * @arg SPI_IT_FRE : TI mode frame format error interrupt + * @arg SPI_IT_MODF : Mode fault interrupt + * @arg SPI_IT_ERR : Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXP : Rx-Packet available flag + * @arg SPI_FLAG_TXP : Tx-Packet space available flag + * @arg SPI_FLAG_DXP : Duplex Packet flag + * @arg SPI_FLAG_EOT : End of transfer flag + * @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag + * @arg SPI_FLAG_UDR : Underrun flag + * @arg SPI_FLAG_OVR : Overrun flag + * @arg SPI_FLAG_CRCERR : CRC error flag + * @arg SPI_FLAG_FRE : TI mode frame format error flag + * @arg SPI_FLAG_MODF : Mode fault flag + * @arg SPI_FLAG_SUSP : Transfer suspend complete flag + * @arg SPI_FLAG_TXC : TxFIFO transmission complete flag + * @arg SPI_FLAG_FRLVL : Fifo reception level flag + * @arg SPI_FLAG_RXWNE : RxFIFO word not empty flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC)); + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC) + +/** @brief Clear the SPI FRE pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC) + +/** @brief Clear the SPI UDR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC) + +/** @brief Clear the SPI EOT pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC) + +/** @brief Clear the SPI UDR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC) + +/** @brief Clear the SPI SUSP pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC) + +/** @brief Enable the SPI peripheral. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) + +/** @brief Disable the SPI peripheral. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) +/** + * @} + */ + + +/* Include SPI HAL Extension module */ +#include "stm32h7rsxx_hal_spi_ex.h" + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions + * @{ + */ +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); + +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); + + +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); + +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Set the SPI transmit-only mode in 1Line configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) + +/** @brief Set the SPI receive-only mode in 1Line configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) + +/** @brief Set the SPI transmit-only mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0) + +/** @brief Set the SPI receive-only mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1) + +/** @brief Set the SPI Transmit-Receive mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL) + +#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ + ((MODE) == SPI_MODE_MASTER)) + +#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) + +#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) + +#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) + +#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY)) + +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \ + ((DATASIZE) == SPI_DATASIZE_31BIT) || \ + ((DATASIZE) == SPI_DATASIZE_30BIT) || \ + ((DATASIZE) == SPI_DATASIZE_29BIT) || \ + ((DATASIZE) == SPI_DATASIZE_28BIT) || \ + ((DATASIZE) == SPI_DATASIZE_27BIT) || \ + ((DATASIZE) == SPI_DATASIZE_26BIT) || \ + ((DATASIZE) == SPI_DATASIZE_25BIT) || \ + ((DATASIZE) == SPI_DATASIZE_24BIT) || \ + ((DATASIZE) == SPI_DATASIZE_23BIT) || \ + ((DATASIZE) == SPI_DATASIZE_22BIT) || \ + ((DATASIZE) == SPI_DATASIZE_21BIT) || \ + ((DATASIZE) == SPI_DATASIZE_20BIT) || \ + ((DATASIZE) == SPI_DATASIZE_22BIT) || \ + ((DATASIZE) == SPI_DATASIZE_19BIT) || \ + ((DATASIZE) == SPI_DATASIZE_18BIT) || \ + ((DATASIZE) == SPI_DATASIZE_17BIT) || \ + ((DATASIZE) == SPI_DATASIZE_16BIT) || \ + ((DATASIZE) == SPI_DATASIZE_15BIT) || \ + ((DATASIZE) == SPI_DATASIZE_14BIT) || \ + ((DATASIZE) == SPI_DATASIZE_13BIT) || \ + ((DATASIZE) == SPI_DATASIZE_12BIT) || \ + ((DATASIZE) == SPI_DATASIZE_11BIT) || \ + ((DATASIZE) == SPI_DATASIZE_10BIT) || \ + ((DATASIZE) == SPI_DATASIZE_9BIT) || \ + ((DATASIZE) == SPI_DATASIZE_8BIT) || \ + ((DATASIZE) == SPI_DATASIZE_7BIT) || \ + ((DATASIZE) == SPI_DATASIZE_6BIT) || \ + ((DATASIZE) == SPI_DATASIZE_5BIT) || \ + ((DATASIZE) == SPI_DATASIZE_4BIT)) + +/** + * @brief DataSize for limited instance + */ +#define IS_SPI_LIMITED_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ + ((DATASIZE) == SPI_DATASIZE_8BIT)) + +#define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA)) + +/** + * @brief FifoThreshold for limited instance + */ +#define IS_SPI_LIMITED_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA)) + +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ + ((CPOL) == SPI_POLARITY_HIGH)) + +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ + ((CPHA) == SPI_PHASE_2EDGE)) + +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ + ((NSS) == SPI_NSS_HARD_INPUT) || \ + ((NSS) == SPI_NSS_HARD_OUTPUT)) + +#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ + ((NSSP) == SPI_NSS_PULSE_DISABLE)) + +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_BYPASS) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) + +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ + ((BIT) == SPI_FIRSTBIT_LSB)) + +#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ + ((MODE) == SPI_TIMODE_ENABLE)) + +#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ + ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) + +#define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \ + ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)) + +#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \ + ((LENGTH) == SPI_CRC_LENGTH_32BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_31BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_30BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_29BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_28BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_27BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_26BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_25BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_24BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_23BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_22BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_21BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_20BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_19BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_18BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_17BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_16BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_15BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_14BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_13BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_12BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_11BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_10BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_9BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_7BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_6BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_4BIT)) + +/** + * @brief CRC Length for limited instance + */ +#define IS_SPI_LIMITED_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_16BIT)) + + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) + + + +#define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ + ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED)) + +#define IS_SPI_RDY_MASTER_MANAGEMENT(MANAGEMENT) (((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_INTERNALLY) || \ + ((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY)) + +#define IS_SPI_RDY_POLARITY(POLARITY) (((POLARITY) == SPI_RDY_POLARITY_HIGH) || \ + ((POLARITY) == SPI_RDY_POLARITY_LOW)) + +#define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ + ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_SPI_H */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_spi_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_spi_ex.h new file mode 100644 index 00000000000..77d0102a5f1 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_spi_ex.h @@ -0,0 +1,99 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_spi_ex.h + * @author MCD Application Team + * @brief Header file of SPI HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_SPI_EX_H +#define STM32H7RSxx_HAL_SPI_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup SPIEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPIEx_Exported_Types SPIEx Exported Types + * @{ + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPIEx_Exported_Constants SPIEx Exported Constants + * @{ + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPIEx_Exported_Macros SPIEx Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPIEx_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/* IO operation functions *****************************************************/ +/** @addtogroup SPIEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, + uint32_t UnderrunBehaviour); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_SPI_EX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sram.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sram.h new file mode 100644 index 00000000000..1f98e3affdd --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_sram.h @@ -0,0 +1,230 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_sram.h + * @author MCD Application Team + * @brief Header file of SRAM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_SRAM_H +#define STM32H7RSxx_HAL_SRAM_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_fmc.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +/** @addtogroup SRAM + * @{ + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup SRAM_Exported_Types SRAM Exported Types + * @{ + */ +/** + * @brief HAL SRAM State structures definition + */ +typedef enum +{ + HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ + HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ + HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ + HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ + HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ + +} HAL_SRAM_StateTypeDef; + +/** + * @brief SRAM handle Structure definition + */ +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) +typedef struct __SRAM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +{ + FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ + + FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ + + FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ + + HAL_LockTypeDef Lock; /*!< SRAM locking object */ + + __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ + + DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ + void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ + void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +} SRAM_HandleTypeDef; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SRAM Callback ID enumeration definition + */ +typedef enum +{ + HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */ + HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ + HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ + HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ +} HAL_SRAM_CallbackIDTypeDef; + +/** + * @brief HAL SRAM Callback pointer definition + */ +typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); +typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup SRAM_Exported_Macros SRAM Exported Macros + * @{ + */ + +/** @brief Reset SRAM handle state + * @param __HANDLE__ SRAM handle + * @retval None + */ +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) +#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions + * @{ + */ + +/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); +void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); +void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); + +/** + * @} + */ + +/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions + * @{ + */ + +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); + +void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) +/* SRAM callback registering/unregistering */ +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_DmaCallbackTypeDef pCallback); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup SRAM_Exported_Functions_Group3 Control functions + * @{ + */ + +/* SRAM Control functions ****************************************************/ +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); + +/** + * @} + */ + +/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions + * @{ + */ + +/* SRAM State functions ******************************************************/ +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_SRAM_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_tim.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_tim.h new file mode 100644 index 00000000000..1645b54ea64 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_tim.h @@ -0,0 +1,2552 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_TIM_H +#define STM32H7RSxx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF + Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF + (or 0xFFEF if dithering is activated)Macros __HAL_TIM_CALC_PERIOD(), + __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(), + __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to calculate Period value */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF + (or 0xFFEF if dithering is activated) + Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate + Pulse value */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF + (or 0xFFEF if dithering is activated) + Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate + Pulse value */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + * @note Advanced timers provide TRGO2 internal line which is redirected + * to the ADC + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ + + uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + + uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ + + uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ + + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ + HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ + void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ + void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */ + void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */ + void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */ + void (* TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Transition Error Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ + , HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */ + , HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */ + , HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */ + , HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_CCR5 0x00000012U +#define TIM_DMABASE_CCR6 0x00000013U +#define TIM_DMABASE_CCMR3 0x00000014U +#define TIM_DMABASE_DTR2 0x00000015U +#define TIM_DMABASE_ECR 0x00000016U +#define TIM_DMABASE_TISEL 0x00000017U +#define TIM_DMABASE_AF1 0x00000018U +#define TIM_DMABASE_AF2 0x00000019U +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction, x2 mode */ +#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */ +#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */ +#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */ +#define TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */ +#define TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +#define TIM_IT_IDX TIM_DIER_IDXIE /*!< Index interrupt */ +#define TIM_IT_DIR TIM_DIER_DIRIE /*!< Direction change interrupt */ +#define TIM_IT_IERR TIM_DIER_IERRIE /*!< Index error interrupt */ +#define TIM_IT_TERR TIM_DIER_TERRIE /*!< Transition error interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +#define TIM_FLAG_IDX TIM_SR_IDXF /*!< Encoder index flag */ +#define TIM_FLAG_DIR TIM_SR_DIRF /*!< Direction change flag */ +#define TIM_FLAG_IERR TIM_SR_IERRF /*!< Index error flag */ +#define TIM_FLAG_TERR TIM_SR_TERRF /*!< Transition error flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ +#define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ +#define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ +#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ +#define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */ +#define TIM_CLOCKSOURCE_ITR9 TIM_TS_ITR9 /*!< External clock source mode 1 (ITR9) */ +#define TIM_CLOCKSOURCE_ITR10 TIM_TS_ITR10 /*!< External clock source mode 1 (ITR10) */ +#define TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11 /*!< External clock source mode 1 (ITR11) */ +#define TIM_CLOCKSOURCE_ITR13 TIM_TS_ITR13 /*!< External clock source mode 1 (ITR13) */ +#define TIM_CLOCKSOURCE_ITR14 TIM_TS_ITR14 /*!< External clock source mode 1 (ITR14) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ +#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable + * @{ + */ +#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ +#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity + * @{ + */ +#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ +#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ +#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 + * @{ + */ +#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_ENCODER_CLK TIM_CR2_MMS_3 /*!< Encoder clock is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) + * @{ + */ +#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ +#define TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ +#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ +#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ +#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ +#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +#define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */ +#define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) */ +#define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */ +#define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */ +#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ +#define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ +#define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */ +#define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */ +#define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ +#define TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) */ +#define TIM_TS_ITR14 (TIM_SMCR_TS_1 | TIM_SMCR_TS_4) /*!< Internal Trigger 14 (ITR14) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_System TIM Break System + * @{ + */ +#define TIM_BREAK_SYSTEM_ECC_AXISRAM1 SBS_BKLOCKR_ARAM1ECC_BL /*!< Enables and locks the AXIRAM1 ECC double error detection flag connection to TIM1/8/15/16/17/20 break inputs */ +#define TIM_BREAK_SYSTEM_ECC_AXISRAM3 SBS_BKLOCKR_ARAM3ECC_BL /*!< Enables and locks the AXIRAM3 ECC double error detection flag connection to TIM1/8/15/16/17/20 break inputs */ +#define TIM_BREAK_SYSTEM_ECC_ITCM SBS_BKLOCKR_ITCMECC_BL /*!< Enables and locks the ITCM ECC double error detection flag connection to TIM1/8/15/16/17/20 break inputs */ +#define TIM_BREAK_SYSTEM_ECC_DTCM SBS_BKLOCKR_DTCMECC_BL /*!< Enables and locks the DTCM ECC double error detection flag connection to TIM1/8/15/16/17/20 break inputs */ +#define TIM_BREAK_SYSTEM_ECC_BACKUP_RAM SBS_BKLOCKR_BKRAMECC_BL /*!< Enables and locks the Backup RAM ECC double error detection flag connection to TIM1/8/15/16/17/20 break inputs */ +#define TIM_BREAK_SYSTEM_ECC_FLASH SBS_BKLOCKR_FLASHECC_BL /*!< Enables and locks the FLASH ECC double error detection flag connection to TIM1/8/15/16/17/20 break inputs */ +#define TIM_BREAK_SYSTEM_PVD SBS_BKLOCKR_PVD_BL /*!< Enables and locks the PVD signal connection to TIM1/8/15/16/17/20 break inputs */ +#define TIM_BREAK_SYSTEM_LOCKUP SBS_BKLOCKR_CM7LCKUP_BL /*!< Enables and locks the Cortex-M7 lockup signal connection to TIM1/8/15/16/17/20 break inputs */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @arg TIM_IT_IDX: Index interrupt + * @arg TIM_IT_DIR: Direction change interrupt + * @arg TIM_IT_IERR: Index error interrupt + * @arg TIM_IT_TERR: Transition error interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @arg TIM_IT_IDX: Index interrupt + * @arg TIM_IT_DIR: Direction change interrupt + * @arg TIM_IT_IERR: Index error interrupt + * @arg TIM_IT_TERR: Transition error interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @arg TIM_FLAG_IDX: Index interrupt flag + * @arg TIM_FLAG_DIR: Direction change interrupt flag + * @arg TIM_FLAG_IERR: Index error interrupt flag + * @arg TIM_FLAG_TERR: Transition error interrupt flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @arg TIM_FLAG_IDX: Index interrupt flag + * @arg TIM_FLAG_DIR: Direction change interrupt flag + * @arg TIM_FLAG_IERR: Index error interrupt flag + * @arg TIM_FLAG_TERR: Transition error interrupt flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @arg TIM_IT_IDX: Index interrupt + * @arg TIM_IT_DIR: Direction change interrupt + * @arg TIM_IT_IERR: Index error interrupt + * @arg TIM_IT_TERR: Transition error interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @arg TIM_IT_IDX: Index interrupt + * @arg TIM_IT_DIR: Direction change interrupt + * @arg TIM_IT_IERR: Index error interrupt + * @arg TIM_IT_TERR: Transition error interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in + * case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @arg TIM_CHANNEL_5: get capture/compare 5 register value + * @arg TIM_CHANNEL_6: get capture/compare 6 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ + ((__HANDLE__)->Instance->CCR6)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) + +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ + ((__BASE__) == TIM_DMABASE_AF2) || \ + ((__BASE__) == TIM_DMABASE_TISEL) || \ + ((__BASE__) == TIM_DMABASE_DTR2) || \ + ((__BASE__) == TIM_DMABASE_ECR)) + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENABLE)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ + ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ + ((__CHANNEL__) != (TIM_CHANNEL_6))) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12) || \ + ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) || \ + ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) || \ + ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) || \ + ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \ + ((__MODE__) == TIM_ENCODERMODE_X1_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_X1_TI2)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_5) || \ + ((__CHANNEL__) == TIM_CHANNEL_6) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR13) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR14)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) + + +#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ + ((__STATE__) == TIM_BREAK2_DISABLE)) + +#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) + +#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) + + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF) || \ + ((__SOURCE__) == TIM_TRGO_ENCODER_CLK)) + +#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ + ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO2_OC1) || \ + ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ + ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \ + ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \ + ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9)|| \ + ((__SELECTION__) == TIM_TS_ITR10)|| \ + ((__SELECTION__) == TIM_TS_ITR11)|| \ + ((__SELECTION__) == TIM_TS_ITR13)|| \ + ((__SELECTION__) == TIM_TS_ITR14)|| \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC_AXISRAM1) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_ECC_AXISRAM3) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_ECC_ITCM) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_ECC_DTCM) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_ECC_BACKUP_RAM) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_ECC_FLASH) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = \ + (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32h7rsxx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); +HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst, + uint32_t length); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_TIM_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_tim_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_tim_ex.h new file mode 100644 index 00000000000..139f969f5ae --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_tim_ex.h @@ -0,0 +1,1124 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_TIM_EX_H +#define STM32H7RSxx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; + +/** + * @brief TIM Break/Break2 input configuration + */ +typedef struct +{ + uint32_t Source; /*!< Specifies the source of the timer break input. + This parameter can be a value of @ref TIMEx_Break_Input_Source */ + uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ + uint32_t Polarity; /*!< Specifies the break input source polarity. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */ +} TIMEx_BreakInputConfigTypeDef; + +/** + * @brief TIM Encoder index configuration + */ +typedef struct +{ + uint32_t Polarity; /*!< TIM Encoder index polarity.This parameter can be a value of @ref TIMEx_Encoder_Index_Polarity */ + + uint32_t Prescaler; /*!< TIM Encoder index prescaler.This parameter can be a value of @ref TIMEx_Encoder_Index_Prescaler */ + + uint32_t Filter; /*!< TIM Encoder index filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Blanking; /*!< Specifies whether or not the encoder index event is conditioned by TI3 or TI4 input.This parameter can be a value of @ref TIMEx_Encoder_Index_Blanking */ + + FunctionalState FirstIndexEnable; /*!< Specifies whether or not the encoder first index is enabled.This parameter value can be ENABLE or DISABLE. */ + + uint32_t Position; /*!< Specifies in which AB input configuration the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Position */ + + uint32_t Direction; /*!< Specifies in which counter direction the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Direction */ + +} TIMEx_EncoderIndexConfigTypeDef; + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#define TIM_TIM1_ETR_GPIO 0x00000000UL /*!< TIM1_ETR is not connected to I/O */ +#define TIM_TIM1_ETR_ADC1_AWD1 (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ETR_ADC1_AWD2 (TIM_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ETR_ADC1_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */ +#define TIM_TIM1_ETR_ADC2_AWD1 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM1_ETR_ADC2_AWD2 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM1_ETR_ADC2_AWD3 (TIM_AF1_ETRSEL_3) /*!< TIM1_ETR is connected to ADC2 AWD3 */ + +#define TIM_TIM2_ETR_GPIO 0x00000000UL /*!< TIM2_ETR is not connected to I/O */ +#define TIM_TIM2_ETR_DCMIPP_HSYNC (TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to DCMIPP HSYNC */ +#define TIM_TIM2_ETR_LTDC_HSYNC (TIM_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to LTDC HSYNC */ +#define TIM_TIM2_ETR_SAI1_FSA (TIM_AF1_ETRSEL_2) /*!< TIM2_ETR is connected to SAI1 FS_A */ +#define TIM_TIM2_ETR_SAI1_FSB (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 FS_B */ +#define TIM_TIM2_ETR_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to GFXTIM TE */ +#define TIM_TIM2_ETR_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to DCMIPP VSYNC */ +#define TIM_TIM2_ETR_LTDC_VSYNC (TIM_AF1_ETRSEL_3) /*!< TIM2_ETR is connected to LTDC VSYNC */ +#define TIM_TIM2_ETR_TIM3_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to TIM3 ETR */ +#define TIM_TIM2_ETR_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM4 ETR */ +#define TIM_TIM2_ETR_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM2_ETR is connected to TIM5 ETR */ +#define TIM_TIM2_ETR_ETH_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to ETH PPS */ + +#define TIM_TIM3_ETR_GPIO 0x00000000UL /*!< TIM3_ETR is not connected to I/O */ +#define TIM_TIM3_ETR_DCMIPP_HSYNC (TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to DCMIPP HSYNC */ +#define TIM_TIM3_ETR_LTDC_HSYNC (TIM_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to LTDC HSYNC */ +#define TIM_TIM3_ETR_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to GFXTIM TE */ +#define TIM_TIM3_ETR_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to DCMIPP VSYNC */ +#define TIM_TIM3_ETR_LTDC_VSYNC (TIM_AF1_ETRSEL_3) /*!< TIM3_ETR is connected to LTDC VSYNC */ +#define TIM_TIM3_ETR_TIM2_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to TIM2 ETR */ +#define TIM_TIM3_ETR_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to TIM4 ETR */ +#define TIM_TIM3_ETR_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM3_ETR is connected to TIM5 ETR */ +#define TIM_TIM3_ETR_ETH_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ETH PPS */ + +#define TIM_TIM4_ETR_GPIO 0x00000000UL /*!< TIM4_ETR is not connected to I/O */ +#define TIM_TIM4_ETR_DCMIPP_HSYNC (TIM_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to DCMIPP HSYNC */ +#define TIM_TIM4_ETR_LTDC_HSYNC (TIM_AF1_ETRSEL_1) /*!< TIM4_ETR is connected to LTDC HSYNC */ +#define TIM_TIM4_ETR_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM4_ETR is connected to GFXTIM TE */ +#define TIM_TIM4_ETR_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to DCMIPP VSYNC */ +#define TIM_TIM4_ETR_LTDC_VSYNC (TIM_AF1_ETRSEL_3) /*!< TIM4_ETR is connected to LTDC VSYNC */ +#define TIM_TIM4_ETR_TIM2_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to TIM2 ETR */ +#define TIM_TIM4_ETR_TIM3_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) /*!< TIM4_ETR is connected to TIM3 ETR */ +#define TIM_TIM4_ETR_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM4_ETR is connected to TIM5 ETR */ + +#define TIM_TIM5_ETR_GPIO 0x00000000UL /*!< TIM5_ETR is not connected to I/O */ +#define TIM_TIM5_ETR_SAI2_FSA (TIM_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to SAI2 FS_A */ +#define TIM_TIM5_ETR_SAI2_FSB (TIM_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to SAI2 FS_B */ +#define TIM_TIM5_ETR_DCMIPP_HSYNC (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to DCMIPP HSYNC */ +#define TIM_TIM5_ETR_LTDC_HSYNC (TIM_AF1_ETRSEL_2) /*!< TIM5_ETR is connected to LTDC HSYNC */ +#define TIM_TIM5_ETR_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to GFXTIM TE */ +#define TIM_TIM5_ETR_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to DCMIPP VSYNC */ +#define TIM_TIM5_ETR_LTDC_VSYNC (TIM_AF1_ETRSEL_3) /*!< TIM4_ETR is connected to LTDC VSYNC */ +#define TIM_TIM5_ETR_TIM2_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to TIM2 ETR */ +#define TIM_TIM5_ETR_TIM3_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to TIM3 ETR */ +#define TIM_TIM5_ETR_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to TIM4 ETR */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input TIM Extended Break input + * @{ + */ +#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source + * @{ + */ +#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling + * @{ + */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity + * @{ + */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ +/** + * @} + */ + +/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection + * @{ + */ +#define TIM_TIM2_TI1_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */ +#define TIM_TIM2_TI1_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM2 TI1 is connected to ETH1 PPS */ + +#define TIM_TIM3_TI1_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */ +#define TIM_TIM3_TI1_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM3 TI1 is connected to ETH1 PPS */ + +#define TIM_TIM9_TI1_GPIO 0x00000000UL /*!< TIM9_TI1 is connected to GPIO */ +#define TIM_TIM9_TI1_MCO1 (TIM_TISEL_TI1SEL_2) /*!< TIM9_TI1 is connected to MCO1 */ +#define TIM_TIM9_TI1_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM9_TI1 is connected to MCO2 */ + +#define TIM_TIM12_TI1_GPIO 0x00000000UL /*!< TIM12_TI1 is connected to GPIO */ +#define TIM_TIM12_TI1_SPDIF_FS (TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to SPDIFRX FS */ +#define TIM_TIM12_TI1_HSI_1024 (TIM_TISEL_TI1SEL_1) /*!< TIM12_TI1 is connected to HSI/1024 */ +#define TIM_TIM12_TI1_CSI_128 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to CSI/128 */ +#define TIM_TIM12_TI1_MCO1 (TIM_TISEL_TI1SEL_2) /*!< TIM12_TI1 is connected to MCO1 */ +#define TIM_TIM12_TI1_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to MCO2 */ +#define TIM_TIM12_TI2_GPIO 0x00000000UL /*!< TIM12_TI2 is connected to GPIO */ + +#define TIM_TIM15_TI1_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */ +#define TIM_TIM15_TI1_TIM2_CH1 (TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to TIM2 CH1 GPIO */ +#define TIM_TIM15_TI1_TIM3_CH1 (TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to TIM3 CH1 GPIO */ +#define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to TIM4 CH1 GPIO */ +#define TIM_TIM15_TI1_MCO1 (TIM_TISEL_TI1SEL_2) /*!< TIM15_TI1 is connected to MCO1 */ +#define TIM_TIM15_TI1_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to MCO2 */ +#define TIM_TIM15_TI2_GPIO 0x00000000UL /*!< TIM15_TI2 is connected to GPIO */ +#define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM2 CH2 GPIO */ +#define TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /*!< TIM15_TI2 is connected to TIM3 CH2 GPIO */ +#define TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM4 CH2 GPIO */ + +#define TIM_TIM16_TI1_GPIO 0x00000000UL /*!< TIM16_TI1 is connected to GPIO */ +#define TIM_TIM16_TI1_RTC_WKUP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to RTC Wakeup */ + +#define TIM_TIM17_TI1_GPIO 0x00000000UL /*!< TIM17_TI1 is connected to GPIO */ +#define TIM_TIM17_TI1_SPDIF_FS (TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to SPDIFRX FS */ +/** + * @} + */ + +/** @defgroup TIMEx_SMS_Preload_Enable TIM Extended Bitfield SMS preload enabling + * @{ + */ +#define TIM_SMS_PRELOAD_SOURCE_UPDATE 0x00000000U /*!< Prelaod of SMS bitfield is disabled */ +#define TIM_SMS_PRELOAD_SOURCE_INDEX TIM_SMCR_SMSPS /*!< Preload of SMS bitfield is enabled */ +/** + * @} + */ + +/** @defgroup TIMEx_Encoder_Index_Blanking TIM Extended Encoder index blanking + * @{ + */ +#define TIM_ENCODERINDEX_BLANKING_DISABLE 0x00000000U /*!< Encoder index blanking is disabled */ +#define TIM_ENCODERINDEX_BLANKING_TI3 TIM_ECR_IBLK_0 /*!< Encoder index blanking is enabled on TI3 */ +#define TIM_ENCODERINDEX_BLANKING_TI4 TIM_ECR_IBLK_1 /*!< Encoder index blanking is enabled on TI4 */ + +/** + * @} + */ + +/** @defgroup TIMEx_Encoder_Index_Position TIM Extended Encoder index position + * @{ + */ +#define TIM_ENCODERINDEX_POSITION_00 0x00000000U /*!< Encoder index position is AB=00 */ +#define TIM_ENCODERINDEX_POSITION_01 TIM_ECR_IPOS_0 /*!< Encoder index position is AB=01 */ +#define TIM_ENCODERINDEX_POSITION_10 TIM_ECR_IPOS_1 /*!< Encoder index position is AB=10 */ +#define TIM_ENCODERINDEX_POSITION_11 (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Encoder index position is AB=11 */ +#define TIM_ENCODERINDEX_POSITION_0 0x00000000U /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 0 */ +#define TIM_ENCODERINDEX_POSITION_1 TIM_ECR_IPOS_0 /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 1 */ +/** + * @} + */ + +/** @defgroup TIMEx_Encoder_Index_Direction TIM Extended Encoder index direction + * @{ + */ +#define TIM_ENCODERINDEX_DIRECTION_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */ +#define TIM_ENCODERINDEX_DIRECTION_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */ +#define TIM_ENCODERINDEX_DIRECTION_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */ +/** + * @} + */ + +/** @defgroup TIMEx_Encoder_Index_Polarity TIM Extended Encoder index polarity + * @{ + */ +#define TIM_ENCODERINDEX_POLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_ENCODERINDEX_POLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIMEx_Encoder_Index_Prescaler TIM Extended Encodder index prescaler + * @{ + */ +#define TIM_ENCODERINDEX_PRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_ENCODERINDEX_PRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_ENCODERINDEX_PRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_ENCODERINDEX_PRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @note ex: @ref __HAL_TIM_CALC_PSC(80000000, 1000000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CNTCLK__ counter clock frequency (in Hz) + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define __HAL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @note ex: @ref __HAL_TIM_CALC_PERIOD(1000000, 0, 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __HAL_TIM_CALC_PERIOD(__TIMCLK__, __PSC__, __FREQ__) \ + (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U + +/** + * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required + * output signal frequency. + * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000); + * @note This macro should be used only if dithering is already enabled + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519) + */ +#define __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__) \ + (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \ + (uint32_t)(((uint64_t)(__TIMCLK__)*16/((__FREQ__) * ((__PSC__) + 1U)) - 16U)) : 0U + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. + * @note ex: @ref __HAL_TIM_CALC_PULSE(1000000, 0, 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __HAL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer + * output compare active/inactive delay. + * @note ex: @ref __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10); + * @note This macro should be used only if dithering is already enabled + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65519) + */ +#define __HAL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). + * @note ex: @ref __HAL_TIM_CALC_PERIOD_BY_DELAY(1000000, 0, 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __HAL_TIM_CALC_PERIOD_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required + * pulse duration (when the timer operates in one pulse mode). + * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20); + * @note This macro should be used only if dithering is already enabled + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519) + */ +#define __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM1) && (((TIM_REMAP) == TIM_TIM1_ETR_GPIO) || \ + ((TIM_REMAP) == TIM_TIM1_ETR_ADC1_AWD1) || \ + ((TIM_REMAP) == TIM_TIM1_ETR_ADC1_AWD2) || \ + ((TIM_REMAP) == TIM_TIM1_ETR_ADC1_AWD3) || \ + ((TIM_REMAP) == TIM_TIM1_ETR_ADC2_AWD1) || \ + ((TIM_REMAP) == TIM_TIM1_ETR_ADC2_AWD2) || \ + ((TIM_REMAP) == TIM_TIM1_ETR_ADC2_AWD3))) || \ + (((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ETR_GPIO) || \ + ((TIM_REMAP) == TIM_TIM2_ETR_DCMIPP_HSYNC) || \ + ((TIM_REMAP) == TIM_TIM2_ETR_LTDC_HSYNC) || \ + ((TIM_REMAP) == TIM_TIM2_ETR_SAI1_FSA) || \ + ((TIM_REMAP) == TIM_TIM2_ETR_SAI1_FSB) || \ + ((TIM_REMAP) == TIM_TIM2_ETR_GFXTIM_TE) || \ + ((TIM_REMAP) == TIM_TIM2_ETR_DCMIPP_VSYNC) || \ + ((TIM_REMAP) == TIM_TIM2_ETR_LTDC_VSYNC) || \ + ((TIM_REMAP) == TIM_TIM2_ETR_TIM3_ETR) || \ + ((TIM_REMAP) == TIM_TIM2_ETR_TIM4_ETR) || \ + ((TIM_REMAP) == TIM_TIM2_ETR_TIM5_ETR) || \ + ((TIM_REMAP) == TIM_TIM2_ETR_ETH_PPS))) || \ + (((INSTANCE) == TIM3) && (((TIM_REMAP) == TIM_TIM3_ETR_GPIO) || \ + ((TIM_REMAP) == TIM_TIM3_ETR_DCMIPP_HSYNC) || \ + ((TIM_REMAP) == TIM_TIM3_ETR_LTDC_HSYNC) || \ + ((TIM_REMAP) == TIM_TIM3_ETR_GFXTIM_TE) || \ + ((TIM_REMAP) == TIM_TIM3_ETR_DCMIPP_VSYNC) || \ + ((TIM_REMAP) == TIM_TIM3_ETR_LTDC_VSYNC) || \ + ((TIM_REMAP) == TIM_TIM3_ETR_TIM2_ETR) || \ + ((TIM_REMAP) == TIM_TIM3_ETR_TIM4_ETR) || \ + ((TIM_REMAP) == TIM_TIM3_ETR_TIM5_ETR) || \ + ((TIM_REMAP) == TIM_TIM3_ETR_ETH_PPS))) || \ + (((INSTANCE) == TIM4) && (((TIM_REMAP) == TIM_TIM4_ETR_GPIO) || \ + ((TIM_REMAP) == TIM_TIM4_ETR_DCMIPP_HSYNC) || \ + ((TIM_REMAP) == TIM_TIM4_ETR_LTDC_HSYNC) || \ + ((TIM_REMAP) == TIM_TIM4_ETR_GFXTIM_TE) || \ + ((TIM_REMAP) == TIM_TIM4_ETR_DCMIPP_VSYNC) || \ + ((TIM_REMAP) == TIM_TIM4_ETR_LTDC_VSYNC) || \ + ((TIM_REMAP) == TIM_TIM4_ETR_TIM2_ETR) || \ + ((TIM_REMAP) == TIM_TIM4_ETR_TIM3_ETR) || \ + ((TIM_REMAP) == TIM_TIM4_ETR_TIM5_ETR))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_ETR_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_ETR_SAI2_FSA) || \ + ((TIM_REMAP) == TIM_TIM5_ETR_SAI2_FSB) || \ + ((TIM_REMAP) == TIM_TIM5_ETR_DCMIPP_HSYNC) || \ + ((TIM_REMAP) == TIM_TIM5_ETR_LTDC_HSYNC) || \ + ((TIM_REMAP) == TIM_TIM5_ETR_GFXTIM_TE) || \ + ((TIM_REMAP) == TIM_TIM5_ETR_DCMIPP_VSYNC) || \ + ((TIM_REMAP) == TIM_TIM5_ETR_LTDC_VSYNC) || \ + ((TIM_REMAP) == TIM_TIM5_ETR_TIM2_ETR) || \ + ((TIM_REMAP) == TIM_TIM5_ETR_TIM3_ETR) || \ + ((TIM_REMAP) == TIM_TIM5_ETR_TIM4_ETR)))) + +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ + ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) + +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) ((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) + +#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ + ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) + +#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) + +#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U)) + +#define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \ + (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5)) + +#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ + ((((INSTANCE) == TIM1) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR13) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR14))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ + || \ + (((INSTANCE) == TIM4) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ + || \ + (((INSTANCE) == TIM5) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR13))) \ + || \ + (((INSTANCE) == TIM9) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ + || \ + (((INSTANCE) == TIM12) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ + || \ + (((INSTANCE) == TIM15) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)))) + +#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ + ((((INSTANCE) == TIM1) && \ + (((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_ITR13) || \ + ((__SELECTION__) == TIM_TS_ITR14))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11))) \ + || \ + (((INSTANCE) == TIM4) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11))) \ + || \ + (((INSTANCE) == TIM5) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_ITR13) || \ + ((__SELECTION__) == TIM_TS_ITR14))) \ + || \ + (((INSTANCE) == TIM9) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11))) \ + || \ + (((INSTANCE) == TIM12) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11))) \ + || \ + (((INSTANCE) == TIM15) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11)))) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ + ((((INSTANCE) == TIM1) && \ + (((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_ITR13) || \ + ((__SELECTION__) == TIM_TS_ITR14) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM4) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM5) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_ITR13) || \ + ((__SELECTION__) == TIM_TS_ITR14) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM9) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM12) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM15) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR10) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_NONE)))) + +#define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \ + (IS_TIM_OC_MODE(__MODE__) \ + && ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \ + ? (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4)) : (1 == 1))) + +#define IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4)) + +#define IS_TIM_PULSEONCOMPARE_INSTANCE(INSTANCE) IS_TIM_CC3_INSTANCE(INSTANCE) + +#define IS_TIM_PULSEONCOMPARE_WIDTH(__WIDTH__) ((__WIDTH__) <= 0xFFU) + +#define IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0x7U) + +#define IS_TIM_SLAVE_PRELOAD_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_UPDATE) \ + || ((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_INDEX)) + +#define IS_TIM_ENCODERINDEX_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_NONINVERTED)) + +#define IS_TIM_ENCODERINDEX_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV8)) + +#define IS_TIM_ENCODERINDEX_FILTER(__FILTER__) ((__FILTER__) <= 0xFUL) + +#define IS_TIM_ENCODERINDEX_POSITION(__POSITION__) (((__POSITION__) == TIM_ENCODERINDEX_POSITION_00) || \ + ((__POSITION__) == TIM_ENCODERINDEX_POSITION_01) || \ + ((__POSITION__) == TIM_ENCODERINDEX_POSITION_10) || \ + ((__POSITION__) == TIM_ENCODERINDEX_POSITION_11) || \ + ((__POSITION__) == TIM_ENCODERINDEX_POSITION_0) || \ + ((__POSITION__) == TIM_ENCODERINDEX_POSITION_1)) + +#define IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__) (((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP_DOWN) || \ + ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP) || \ + ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_DOWN)) + +#define IS_TIM_ENCODERINDEX_BLANKING(__BLANKING__) (((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_DISABLE) || \ + ((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_TI3) || \ + ((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_TI4)) + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); + +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler, + uint32_t PulseWidth); +HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source); +HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime); +HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime); +HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim, + TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig); +HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7RSxx_HAL_TIM_EX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_uart.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_uart.h new file mode 100644 index 00000000000..89f0a91f4a1 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_uart.h @@ -0,0 +1,1780 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_UART_H +#define STM32H7RSxx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + LPUART: + ======= + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler + UART: + ===== + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ + + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ + +} UART_InitTypeDef; + +/** + * @brief UART Advanced Features initialization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several + Advanced Features may be initialized at the same time . + This parameter can be a value of + @ref UART_Advanced_Features_Initialization_Type. */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref UART_Tx_Inv. */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref UART_Rx_Inv. */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref UART_Data_Inv. */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref UART_Rx_Tx_Swap. */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref UART_Overrun_Disable. */ + +#if defined(HAL_DMA_MODULE_ENABLED) + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. + This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ + + uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate + detection is carried out. + This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref UART_MSB_First. */ +} UART_AdvFeatureInitTypeDef; + +/** + * @brief HAL UART State definition + * @note HAL UART State value is a combination of 2 different substates: + * gState and RxState (see @ref UART_State_Definition). + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_UART_StateTypeDef; + +/** + * @brief UART clock sources definition + */ +typedef enum +{ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + UART_CLOCKSOURCE_PCLK4 = 0x02U, /*!< PCLK4 clock source (only used by LPUART1) */ + UART_CLOCKSOURCE_PLL2Q = 0x04U, /*!< PLL2Q clock source */ + UART_CLOCKSOURCE_PLL3Q = 0x08U, /*!< PLL3Q clock source */ + UART_CLOCKSOURCE_HSI = 0x10U, /*!< HSI clock source */ + UART_CLOCKSOURCE_CSI = 0x20U, /*!< CSI clock source */ + UART_CLOCKSOURCE_LSE = 0x40U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x80U /*!< Undefined clock source */ +} UART_ClockSourceTypeDef; + +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * This parameter can be a value of @ref UART_Reception_Type_Values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + * HAL_UART_RECEPTION_TORTO = 0x02U, + * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + uint16_t Mask; /*!< UART Rx RDR register mask */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + This parameter can be a value of @ref UARTEx_FIFO_mode. */ + + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. This parameter + can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This + parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ + void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ + HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ + HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef) +(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_State_Definition UART State Code Definition + * @{ + */ +#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState.Value is result + of combination (Or) between gState and RxState values */ +#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup UART_Error_Definition UART Error Definition + * @{ + */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ +#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ +#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U /*!< No parity */ +#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ +#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ +#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ +#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ +#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method + * @{ + */ +#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ +/** + * @} + */ + +/** @defgroup UART_ClockPrescaler UART Clock Prescaler + * @{ + */ +#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ +/** + * @} + */ + +/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection + on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection + on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection + on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection + on 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout + * @{ + */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ +/** + * @} + */ + +/** @defgroup UART_LIN UART Local Interconnection Network mode + * @{ + */ +#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ +#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ +/** + * @} + */ + +#if defined(HAL_DMA_MODULE_ENABLED) +/** @defgroup UART_DMA_Tx UART DMA Tx + * @{ + */ +#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ +#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ +/** + * @} + */ + +/** @defgroup UART_DMA_Rx UART DMA Rx + * @{ + */ +#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ +#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection + * @{ + */ +#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_Methods UART WakeUp Methods + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ +/** + * @} + */ + +/** @defgroup UART_Request_Parameters UART Request Parameters + * @{ + */ +#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type + * @{ + */ +#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ +/** + * @} + */ + +/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion + * @{ + */ +#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap + * @{ + */ +#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ +/** + * @} + */ + +/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable + * @{ + */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ +/** + * @} + */ + +#if defined(HAL_DMA_MODULE_ENABLED) +/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error + * @{ + */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** @defgroup UART_MSB_First UART Advanced Feature MSB First + * @{ + */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received + first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received + first enable */ +/** + * @} + */ + +/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable + * @{ + */ +#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ +/** + * @} + */ + +/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable + * @{ + */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ +/** + * @} + */ + +/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register + * @{ + */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection + * @{ + */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ +/** + * @} + */ + +/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity + * @{ + */ +#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask + * @{ + */ +#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ +/** + * @} + */ + +/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value + * @{ + */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ +/** + * @} + */ + +/** @defgroup UART_Flags UART Status Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */ +#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */ +#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */ +#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */ +#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ +#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ +#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ +#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ +#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ +#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ +#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ +#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ +#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ +#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ +#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ +#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ +#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */ +#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */ +#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ +#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */ +#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */ +#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ +#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ +#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ +#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ +#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupts Definition + * Elements values convention: 000ZZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZZ : Flag position in the ISR register(5bits) + * Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ +#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ +#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ +#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ + +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +/** + * @} + */ + +/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags + * @{ + */ +#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ +#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ +#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */ +#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ +#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ +#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ +/** + * @} + */ + +/** @defgroup UART_Reception_Type_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ +#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ +/** + * @} + */ + +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle states. + * @param __HANDLE__ UART handle. + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flush the UART Data registers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) + +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) + +/** @brief Clear the UART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) + +/** @brief Check whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref UART_FLAG_RXFF RXFIFO Full flag + * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag + * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref UART_FLAG_WUF Wake up from stop mode flag + * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) + * @arg @ref UART_FLAG_SBKF Send Break flag + * @arg @ref UART_FLAG_CMF Character match flag + * @arg @ref UART_FLAG_BUSY Busy flag + * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref UART_FLAG_CTS CTS Change flag + * @arg @ref UART_FLAG_LBDF LIN Break detection flag + * @arg @ref UART_FLAG_TXE Transmit data register empty flag + * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag + * @arg @ref UART_FLAG_TC Transmission Complete flag + * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag + * @arg @ref UART_FLAG_IDLE Idle Line detection flag + * @arg @ref UART_FLAG_ORE Overrun Error flag + * @arg @ref UART_FLAG_NE Noise Error flag + * @arg @ref UART_FLAG_FE Framing Error flag + * @arg @ref UART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Check whether the specified UART interrupt has occurred or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) + +/** @brief Check whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + UART_IT_MASK))) != RESET) ? SET : RESET) + +/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific UART request flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref UART_SENDBREAK_REQUEST Send Break Request + * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request + * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** @brief Enable CTS flow control. + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control. + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control. + * @note This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control. + * @note This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +/** @brief Get UART clok division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval UART clock division factor + */ +#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + +/** @brief BRR division operation to set BRR register with LPUART. + * @param __PCLK__ LPUART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \ + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \ + ) + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief Check whether or not UART instance is Low Power UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) + */ +#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance)) + +/** @brief Check UART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on H7RS (i.e. 125 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) + */ +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 15625001U) + +/** @brief Check UART assertion time. + * @param __TIME__ 5-bit value assertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** @brief Check UART deassertion time. + * @param __TIME__ 5-bit value deassertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** + * @brief Ensure that UART frame number of stop bits is valid. + * @param __STOPBITS__ UART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ + ((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_1_5) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + +/** + * @brief Ensure that LPUART frame number of stop bits is valid. + * @param __STOPBITS__ LPUART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + +/** + * @brief Ensure that UART frame parity is valid. + * @param __PARITY__ UART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ + ((__PARITY__) == UART_PARITY_EVEN) || \ + ((__PARITY__) == UART_PARITY_ODD)) + +/** + * @brief Ensure that UART hardware flow control is valid. + * @param __CONTROL__ UART hardware flow control. + * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) + */ +#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + +/** + * @brief Ensure that UART communication mode is valid. + * @param __MODE__ UART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that UART state is valid. + * @param __STATE__ UART state. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ + ((__STATE__) == UART_STATE_ENABLE)) + +/** + * @brief Ensure that UART oversampling is valid. + * @param __SAMPLING__ UART oversampling. + * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) + */ +#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == UART_OVERSAMPLING_8)) + +/** + * @brief Ensure that UART frame sampling is valid. + * @param __ONEBIT__ UART frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that UART auto Baud rate detection mode is valid. + * @param __MODE__ UART auto Baud rate detection mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) + +/** + * @brief Ensure that UART receiver timeout setting is valid. + * @param __TIMEOUT__ UART receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) + +/** + * @brief Ensure that UART LIN state is valid. + * @param __LIN__ UART LIN state. + * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) + */ +#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ + ((__LIN__) == UART_LIN_ENABLE)) + +/** + * @brief Ensure that UART LIN break detection length is valid. + * @param __LENGTH__ UART LIN break detection length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Ensure that UART DMA TX state is valid. + * @param __DMATX__ UART DMA TX state. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ + ((__DMATX__) == UART_DMA_TX_ENABLE)) + +/** + * @brief Ensure that UART DMA RX state is valid. + * @param __DMARX__ UART DMA RX state. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ + ((__DMARX__) == UART_DMA_RX_ENABLE)) + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @brief Ensure that UART half-duplex state is valid. + * @param __HDSEL__ UART half-duplex state. + * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) + */ +#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ + ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) + +/** + * @brief Ensure that UART wake-up method is valid. + * @param __WAKEUP__ UART wake-up method . + * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) + */ +#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) + +/** + * @brief Ensure that UART request parameter is valid. + * @param __PARAM__ UART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ + ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ + ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that UART advanced features initialization is valid. + * @param __INIT__ UART advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) +#else +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Ensure that UART frame TX inversion setting is valid. + * @param __TXINV__ UART frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX inversion setting is valid. + * @param __RXINV__ UART frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) + +/** + * @brief Ensure that UART frame data inversion setting is valid. + * @param __DATAINV__ UART frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX/TX pins swap setting is valid. + * @param __SWAP__ UART frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) + +/** + * @brief Ensure that UART frame overrun setting is valid. + * @param __OVERRUN__ UART frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) + +/** + * @brief Ensure that UART auto Baud rate state is valid. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. + * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ + UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Ensure that UART DMA enabling or disabling on error setting is valid. + * @param __DMA__ UART DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Ensure that UART frame MSB first setting is valid. + * @param __MSBFIRST__ UART frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) + +/** + * @brief Ensure that UART stop mode state is valid. + * @param __STOPMODE__ UART stop mode state. + * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ + ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) + +/** + * @brief Ensure that UART mute mode state is valid. + * @param __MUTE__ UART mute mode state. + * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) + */ +#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ + ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) + +/** + * @brief Ensure that UART wake-up selection is valid. + * @param __WAKE__ UART wake-up selection. + * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) + */ +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ + ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) + +/** + * @brief Ensure that UART driver enable polarity is valid. + * @param __POLARITY__ UART driver enable polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ + ((__POLARITY__) == UART_DE_POLARITY_LOW)) + +/** + * @brief Ensure that UART Prescaler is valid. + * @param __CLOCKPRESCALER__ UART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) + +/** + * @} + */ + +/* Include UART HAL Extended module */ +#include "stm32h7rsxx_hal_uart_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +#endif /* HAL_DMA_MODULE_ENABLED */ +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -----------------------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + +/* Private variables -----------------------------------------------------------*/ +/** @defgroup UART_Private_variables UART Private variables + * @{ + */ +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ +extern const uint16_t UARTPrescTable[12]; +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_UART_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_uart_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_uart_ex.h new file mode 100644 index 00000000000..1dae3f822b5 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_uart_ex.h @@ -0,0 +1,409 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_uart_ex.h + * @author MCD Application Team + * @brief Header file of UART HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_UART_EX_H +#define STM32H7RSxx_HAL_UART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup UARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Types UARTEx Exported Types + * @{ + */ + +/** + * @brief UART wake up from stop mode parameters + */ +typedef struct +{ + uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). + This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. + If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must + be filled up. */ + + uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. + This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ + + uint8_t Address; /*!< UART/USART node address (7-bit long max). */ +} UART_WakeUpTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants + * @{ + */ + +/** @defgroup UARTEx_Word_Length UARTEx Word Length + * @{ + */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +/** + * @} + */ + +/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length + * @{ + */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +/** + * @} + */ + +/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode + * @brief UART FIFO mode + * @{ + */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level + * @brief UART TXFIFO threshold level + * @{ + */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ +/** + * @} + */ + +/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level + * @brief UART RXFIFO threshold level + * @{ + */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup UARTEx_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group2 + * @{ + */ + +void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); + +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ + +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UARTEx_Private_Macros UARTEx Private Macros + * @{ + */ + +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART1CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if(((__HANDLE__)->Instance == USART2) || \ + ((__HANDLE__)->Instance == USART3) || \ + ((__HANDLE__)->Instance == UART4) || \ + ((__HANDLE__)->Instance == UART5) || \ + ((__HANDLE__)->Instance == UART7) || \ + ((__HANDLE__)->Instance == UART8)) \ + { \ + switch(__HAL_RCC_GET_USART234578_SOURCE()) \ + { \ + case RCC_USART234578CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART234578CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART234578CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART234578CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART234578CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART234578CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ + case RCC_LPUART1CLKSOURCE_PCLK4: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK4; \ + break; \ + case RCC_LPUART1CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_LPUART1CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_LPUART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) + + +/** @brief Report the UART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define UART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** + * @brief Ensure that UART frame length is valid. + * @param __LENGTH__ UART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ + ((__LENGTH__) == UART_WORDLENGTH_8B) || \ + ((__LENGTH__) == UART_WORDLENGTH_9B)) + +/** + * @brief Ensure that UART wake-up address length is valid. + * @param __ADDRESS__ UART wake-up address length. + * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) + */ +#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ + ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) + +/** + * @brief Ensure that UART TXFIFO threshold level is valid. + * @param __THRESHOLD__ UART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that UART RXFIFO threshold level is valid. + * @param __THRESHOLD__ UART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_UART_EX_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_usart.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_usart.h new file mode 100644 index 00000000000..01000d53534 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_usart.h @@ -0,0 +1,986 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_usart.h + * @author MCD Application Team + * @brief Header file of USART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_USART_H +#define STM32H7RSxx_HAL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup USART_Exported_Types USART Exported Types + * @{ + */ + +/** + * @brief USART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. + The baud rate is computed using the following formula: + Baud Rate Register[15:4] = ((2 * fclk_pres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * fclk_pres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where fclk_pres is the USART input clock frequency (fclk) + divided by a prescaler. + @note Oversampling by 8 is systematically applied to + achieve high baud rates. */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode. */ + + uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity. */ + + uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase. */ + + uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit. */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source. + This parameter can be a value of @ref USART_ClockPrescaler. */ +} USART_InitTypeDef; + +/** + * @brief HAL USART State structures definition + */ +typedef enum +{ + HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ + HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */ + HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_USART_STATE_ERROR = 0x04U /*!< Error */ +} HAL_USART_StateTypeDef; + +/** + * @brief USART clock sources definitions + */ +typedef enum +{ + USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + USART_CLOCKSOURCE_PLL2Q = 0x02U, /*!< PLL2Q clock source */ + USART_CLOCKSOURCE_PLL3Q = 0x04U, /*!< PLL3Q clock source */ + USART_CLOCKSOURCE_HSI = 0x08U, /*!< HSI clock source */ + USART_CLOCKSOURCE_CSI = 0x10U, /*!< CSI clock source */ + USART_CLOCKSOURCE_LSE = 0x20U, /*!< LSE clock source */ + USART_CLOCKSOURCE_UNDEFINED = 0x80U /*!< Undefined clock source */ +} USART_ClockSourceTypeDef; + +/** + * @brief USART handle Structure definition + */ +typedef struct __USART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< USART registers base address */ + + USART_InitTypeDef Init; /*!< USART communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< USART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< USART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ + + uint16_t Mask; /*!< USART Rx RDR register mask */ + + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value + of @ref USARTEx_Slave_Mode */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value + of @ref USARTEx_FIFO_mode. */ + + void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ + + __IO uint32_t ErrorCode; /*!< USART Error code */ + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */ + void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */ + void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */ + void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */ + void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Fifo Empty Callback */ + + void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */ + void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +} USART_HandleTypeDef; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL USART Callback ID enumeration definition + */ +typedef enum +{ + HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */ + HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */ + HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */ + HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */ + HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */ + HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */ + HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */ + HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U, /*!< USART Rx Fifo Full Callback ID */ + HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, /*!< USART Tx Fifo Empty Callback ID */ + + HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */ + HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */ + +} HAL_USART_CallbackIDTypeDef; + +/** + * @brief HAL USART Callback pointer definition + */ +typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */ + +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_Error_Definition USART Error Definition + * @{ + */ +#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */ +/** + * @} + */ + +/** @defgroup USART_Stop_Bits USART Number of Stop Bits + * @{ + */ +#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */ +#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */ +#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ +#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_Parity USART Parity + * @{ + */ +#define USART_PARITY_NONE 0x00000000U /*!< No parity */ +#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup USART_Mode USART Mode + * @{ + */ +#define USART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define USART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup USART_Clock USART Clock + * @{ + */ +#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */ +#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */ +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity USART Clock Polarity + * @{ + */ +#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */ +#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup USART_Clock_Phase USART Clock Phase + * @{ + */ +#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */ +#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */ +/** + * @} + */ + +/** @defgroup USART_Last_Bit USART Last Bit + * @{ + */ +#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */ +#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_ClockPrescaler USART Clock Prescaler + * @{ + */ +#define USART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define USART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define USART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define USART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define USART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define USART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define USART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define USART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define USART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define USART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define USART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define USART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ + +/** + * @} + */ + +/** @defgroup USART_Request_Parameters USART Request Parameters + * @{ + */ +#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup USART_Flags USART Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define USART_FLAG_TXFT USART_ISR_TXFT /*!< USART TXFIFO threshold flag */ +#define USART_FLAG_RXFT USART_ISR_RXFT /*!< USART RXFIFO threshold flag */ +#define USART_FLAG_RXFF USART_ISR_RXFF /*!< USART RXFIFO Full flag */ +#define USART_FLAG_TXFE USART_ISR_TXFE /*!< USART TXFIFO Empty flag */ +#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */ +#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */ +#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */ +#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */ +#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */ +#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */ +#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */ +#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ +#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */ +#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */ +#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */ +#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */ +#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */ +#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */ +#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */ +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition USART Interrupts Definition + * Elements values convention: 0000ZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ + +#define USART_IT_PE 0x0028U /*!< USART parity error interruption */ +#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */ +#define USART_IT_TXFNF 0x0727U /*!< USART TX FIFO not full interruption */ +#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */ +#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */ +#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */ +#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */ +#define USART_IT_ERR 0x0060U /*!< USART error interruption */ +#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */ +#define USART_IT_NE 0x0200U /*!< USART noise error interruption */ +#define USART_IT_FE 0x0100U /*!< USART frame error interruption */ +#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */ +#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */ +#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */ +#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */ + +/** + * @} + */ + +/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags + * @{ + */ +#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ +#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */ +#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */ +#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */ +/** + * @} + */ + +/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask + * @{ + */ +#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */ +#define USART_CR_MASK 0x00E0U /*!< USART control register mask */ +#define USART_CR_POS 5U /*!< USART control register position */ +#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */ +#define USART_ISR_POS 8U /*!< USART ISR register position */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup USART_Exported_Macros USART Exported Macros + * @{ + */ + +/** @brief Reset USART handle state. + * @param __HANDLE__ USART handle. + * @retval None + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_USART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** @brief Check whether the specified USART flag is set or not. + * @param __HANDLE__ specifies the USART Handle + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref USART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref USART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref USART_FLAG_RXFF RXFIFO Full flag + * @arg @ref USART_FLAG_TXFE TXFIFO Empty flag + * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref USART_FLAG_BUSY Busy flag + * @arg @ref USART_FLAG_UDR SPI slave underrun error flag + * @arg @ref USART_FLAG_TXE Transmit data register empty flag + * @arg @ref USART_FLAG_TXFNF TXFIFO not full flag + * @arg @ref USART_FLAG_TC Transmission Complete flag + * @arg @ref USART_FLAG_RXNE Receive data register not empty flag + * @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag + * @arg @ref USART_FLAG_RTOF Receiver Timeout flag + * @arg @ref USART_FLAG_IDLE Idle Line detection flag + * @arg @ref USART_FLAG_ORE OverRun Error flag + * @arg @ref USART_FLAG_NE Noise Error flag + * @arg @ref USART_FLAG_FE Framing Error flag + * @arg @ref USART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified USART pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag + * @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag + * @retval None + */ +#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the USART PE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF) + +/** @brief Clear the USART FE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF) + +/** @brief Clear the USART NE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF) + +/** @brief Clear the USART ORE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF) + +/** @brief Clear the USART IDLE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF) + +/** @brief Clear the USART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF) + +/** @brief Clear SPI slave underrun error flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF) + +/** @brief Enable the specified USART interrupt. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + +/** @brief Disable the specified USART interrupt. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + +/** @brief Check whether the specified USART interrupt has occurred or not. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\ + USART_ISR_POS))) != 0U) ? SET : RESET) + +/** @brief Check whether the specified USART interrupt source is enabled or not. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + USART_IT_MASK))) != 0U) ? SET : RESET) + +/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the USART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt. + * This parameter can be one of the following values: + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @retval None + */ +#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific USART request flag. + * @param __HANDLE__ specifies the USART Handle. + * @param __REQ__ specifies the request flag to set. + * This parameter can be one of the following values: + * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * + * @retval None + */ +#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the USART one bit sample method. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the USART one bit sample method. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable USART. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable USART. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup USART_Private_Macros USART Private Macros + * @{ + */ + +/** @brief Get USART clock division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ USART prescaler value. + * @retval USART clock division factor + */ +#define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ USART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ USART prescaler value. + * @retval Division result + */ +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\ + (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief Report the USART clock source. + * @param __HANDLE__ specifies the USART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval the USART clocking source, written in __CLOCKSOURCE__. + */ +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART1CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if(((__HANDLE__)->Instance == USART2) || \ + ((__HANDLE__)->Instance == USART3)) \ + { \ + switch(__HAL_RCC_GET_USART234578_SOURCE()) \ + { \ + case RCC_USART234578CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART234578CLKSOURCE_PLL2Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART234578CLKSOURCE_PLL3Q: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART234578CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART234578CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART234578CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) + + +/** @brief Check USART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on H7RS (i.e. 100 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U) + +/** + * @brief Ensure that USART frame number of stop bits is valid. + * @param __STOPBITS__ USART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \ + ((__STOPBITS__) == USART_STOPBITS_1) || \ + ((__STOPBITS__) == USART_STOPBITS_1_5) || \ + ((__STOPBITS__) == USART_STOPBITS_2)) + +/** + * @brief Ensure that USART frame parity is valid. + * @param __PARITY__ USART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \ + ((__PARITY__) == USART_PARITY_EVEN) || \ + ((__PARITY__) == USART_PARITY_ODD)) + +/** + * @brief Ensure that USART communication mode is valid. + * @param __MODE__ USART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that USART clock state is valid. + * @param __CLOCK__ USART clock state. + * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid) + */ +#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \ + ((__CLOCK__) == USART_CLOCK_ENABLE)) + +/** + * @brief Ensure that USART frame polarity is valid. + * @param __CPOL__ USART frame polarity. + * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) + */ +#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH)) + +/** + * @brief Ensure that USART frame phase is valid. + * @param __CPHA__ USART frame phase. + * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) + */ +#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE)) + +/** + * @brief Ensure that USART frame last bit clock pulse setting is valid. + * @param __LASTBIT__ USART frame last bit clock pulse setting. + * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) + */ +#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \ + ((__LASTBIT__) == USART_LASTBIT_ENABLE)) + +/** + * @brief Ensure that USART request parameter is valid. + * @param __PARAM__ USART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that USART Prescaler is valid. + * @param __CLOCKPRESCALER__ USART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256)) + +/** + * @} + */ + +/* Include USART HAL Extended module */ +#include "stm32h7rsxx_hal_usart_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USART_Exported_Functions USART Exported Functions + * @{ + */ + +/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart); +void HAL_USART_MspInit(USART_HandleTypeDef *husart); +void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); +#endif /* HAL_DMA_MODULE_ENABLED */ +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart); + +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart); +void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); +void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart); +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_USART_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_usart_ex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_usart_ex.h new file mode 100644 index 00000000000..c6ad9501721 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_usart_ex.h @@ -0,0 +1,282 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_usart_ex.h + * @author MCD Application Team + * @brief Header file of USART HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_USART_EX_H +#define STM32H7RSxx_HAL_USART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup USARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants + * @{ + */ + +/** @defgroup USARTEx_Word_Length USARTEx Word Length + * @{ + */ +#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ +/** + * @} + */ + +/** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management + * @{ + */ +#define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ +#define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ +/** + * @} + */ + + +/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable + * @brief USART SLAVE mode + * @{ + */ +#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ +#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ +/** + * @} + */ + +/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode + * @brief USART FIFO mode + * @{ + */ +#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level + * @brief USART TXFIFO level + * @{ + */ +#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ +#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +/** + * @} + */ + +/** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level + * @brief USART RXFIFO level + * @{ + */ +#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ +#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ +#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ +#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ +#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ +#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup USARTEx_Private_Macros USARTEx Private Macros + * @{ + */ + +/** @brief Compute the USART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the USART Handle. + * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define USART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** + * @brief Ensure that USART frame length is valid. + * @param __LENGTH__ USART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \ + ((__LENGTH__) == USART_WORDLENGTH_8B) || \ + ((__LENGTH__) == USART_WORDLENGTH_9B)) + +/** + * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid. + * @param __NSS__ USART Negative Slave Select pin management. + * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid) + */ +#define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \ + ((__NSS__) == USART_NSS_SOFT)) + +/** + * @brief Ensure that USART Slave Mode is valid. + * @param __STATE__ USART Slave Mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_USART_SLAVEMODE(__STATE__) (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \ + ((__STATE__) == USART_SLAVEMODE_ENABLE)) + +/** + * @brief Ensure that USART FIFO mode is valid. + * @param __STATE__ USART FIFO mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \ + ((__STATE__) == USART_FIFOMODE_ENABLE)) + +/** + * @brief Ensure that USART TXFIFO threshold level is valid. + * @param __THRESHOLD__ USART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that USART RXFIFO threshold level is valid. + * @param __THRESHOLD__ USART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup USARTEx_Exported_Functions_Group1 + * @{ + */ + +/* IO operation functions *****************************************************/ +void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart); +void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** @addtogroup USARTEx_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig); +HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); +HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_USART_EX_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_wwdg.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_wwdg.h new file mode 100644 index 00000000000..c602a34b072 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_wwdg.h @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_wwdg.h + * @author MCD Application Team + * @brief Header file of WWDG HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_WWDG_H +#define STM32H7RSxx_HAL_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Types WWDG Exported Types + * @{ + */ + +/** + * @brief WWDG Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG. + This parameter can be a value of @ref WWDG_Prescaler */ + + uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter. + This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */ + + uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. + This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ + + uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not. + This parameter can be a value of @ref WWDG_EWI_Mode */ + +} WWDG_InitTypeDef; + +/** + * @brief WWDG handle Structure definition + */ +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +typedef struct __WWDG_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ +{ + WWDG_TypeDef *Instance; /*!< Register base address */ + + WWDG_InitTypeDef Init; /*!< WWDG required parameters */ + +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) + void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ + + void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ +} WWDG_HandleTypeDef; + +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +/** + * @brief HAL WWDG common Callback ID enumeration definition + */ +typedef enum +{ + HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */ + HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */ +} HAL_WWDG_CallbackIDTypeDef; + +/** + * @brief HAL WWDG Callback pointer definition + */ +typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */ + +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Constants WWDG Exported Constants + * @{ + */ + +/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition + * @{ + */ +#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */ +/** + * @} + */ + +/** @defgroup WWDG_Flag_definition WWDG Flag definition + * @brief WWDG Flag definition + * @{ + */ +#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */ +/** + * @} + */ + +/** @defgroup WWDG_Prescaler WWDG Prescaler + * @{ + */ +#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */ +#define WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 /*!< WWDG counter clock = (PCLK1/4096)/16 */ +#define WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/32 */ +#define WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/64 */ +#define WWDG_PRESCALER_128 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/128 */ +/** + * @} + */ + +/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode + * @{ + */ +#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */ +#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup WWDG_Private_Macros WWDG Private Macros + * @{ + */ +#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ + ((__PRESCALER__) == WWDG_PRESCALER_2) || \ + ((__PRESCALER__) == WWDG_PRESCALER_4) || \ + ((__PRESCALER__) == WWDG_PRESCALER_8) || \ + ((__PRESCALER__) == WWDG_PRESCALER_16) || \ + ((__PRESCALER__) == WWDG_PRESCALER_32) || \ + ((__PRESCALER__) == WWDG_PRESCALER_64) || \ + ((__PRESCALER__) == WWDG_PRESCALER_128)) + +#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W)) + +#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T)) + +#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \ + ((__MODE__) == WWDG_EWI_DISABLE)) +/** + * @} + */ + + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Macros WWDG Exported Macros + * @{ + */ + +/** + * @brief Enable the WWDG peripheral. + * @param __HANDLE__ WWDG handle + * @retval None + */ +#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) + +/** + * @brief Enable the WWDG early wakeup interrupt. + * @param __HANDLE__ WWDG handle + * @param __INTERRUPT__ specifies the interrupt to enable. + * This parameter can be one of the following values: + * @arg WWDG_IT_EWI: Early wakeup interrupt + * @note Once enabled this interrupt cannot be disabled except by a system reset. + * @retval None + */ +#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__)) + +/** + * @brief Check whether the selected WWDG interrupt has occurred or not. + * @param __HANDLE__ WWDG handle + * @param __INTERRUPT__ specifies the it to check. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT + * @retval The new state of WWDG_FLAG (SET or RESET). + */ +#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__)) + +/** @brief Clear the WWDG interrupt pending bits. + * bits to clear the selected interrupt pending bits. + * @param __HANDLE__ WWDG handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + */ +#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) + +/** + * @brief Check whether the specified WWDG flag is set or not. + * @param __HANDLE__ WWDG handle + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + * @retval The new state of WWDG_FLAG (SET or RESET). + */ +#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the WWDG's pending flags. + * @param __HANDLE__ WWDG handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + * @retval None + */ +#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** @brief Check whether the specified WWDG interrupt source is enabled or not. + * @param __HANDLE__ WWDG Handle. + * @param __INTERRUPT__ specifies the WWDG interrupt source to check. + * This parameter can be one of the following values: + * @arg WWDG_IT_EWI: Early Wakeup Interrupt + * @retval state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup WWDG_Exported_Functions + * @{ + */ + +/** @addtogroup WWDG_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, + pWWDG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ******************************************************/ +HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_WWDG_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_xspi.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_xspi.h new file mode 100644 index 00000000000..7babe99eb1a --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_hal_xspi.h @@ -0,0 +1,1269 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_xspi.h + * @author MCD Application Team + * @brief Header file of XSPI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_XSPI_H +#define STM32H7RSxx_HAL_XSPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +#if defined(XSPI) || defined(XSPI1) || defined(XSPI2) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup XSPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup XSPI_Exported_Types XSPI Exported Types + * @{ + */ + +/** + * @brief XSPI Init structure definition + */ +typedef struct +{ + uint32_t FifoThresholdByte; /*!< This is the threshold used by the Peripheral to generate the interrupt + indicating that data are available in reception or free place + is available in transmission. + For XSPI, this parameter can be a value between 1 and 64 */ + uint32_t MemoryMode; /*!< It Specifies the memory mode. + This parameter can be a value of @ref XSPI_MemoryMode */ + uint32_t MemoryType; /*!< It indicates the external device type connected to the XSPI. + This parameter can be a value of @ref XSPI_MemoryType */ + uint32_t MemorySize; /*!< It defines the size of the external device connected to the XSPI, + it corresponds to the number of address bits required to access + the external device. + This parameter can be a value of @ref XSPI_MemorySize*/ + uint32_t ChipSelectHighTimeCycle; /*!< It defines the minimum number of clocks which the chip select + must remain high between commands. + This parameter can be a value between 1 and 64U */ + uint32_t FreeRunningClock; /*!< It enables or not the free running clock. + This parameter can be a value of @ref XSPI_FreeRunningClock */ + uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. + This parameter can be a value of @ref XSPI_ClockMode */ + uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration. + This parameter can be a value of @ref XSPI_WrapSize */ + uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating + the external clock based on the AHB clock. + This parameter can be a value between 0 and 255U */ + uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order + to take in account external signal delays. + This parameter can be a value of @ref XSPI_SampleShifting */ + uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. + This parameter can be a value of @ref XSPI_DelayHoldQuarterCycle */ + uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and + defines the boundary of bytes to release the chip select. + This parameter can be a value of @ref XSPI_ChipSelectBoundary */ + uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is + released every MaxTran+1 bytes when the other XSPI request the access + to the bus. + This parameter can be a value between 0 and 255U */ + uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every + Refresh+1 clock cycles. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t MemorySelect; /*!< It indicates if the output of nCS. + This parameter can be a value of @ref XSPI_MemorySelect */ +} XSPI_InitTypeDef; + +/** + * @brief HAL XSPI Handle Structure definition + */ +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +typedef struct __XSPI_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ +{ + XSPI_TypeDef *Instance; /*!< XSPI registers base address */ + XSPI_InitTypeDef Init; /*!< XSPI initialization parameters */ + uint8_t *pBuffPtr; /*!< Address of the XSPI buffer for transfer */ + __IO uint32_t XferSize; /*!< Number of data to transfer */ + __IO uint32_t XferCount; /*!< Counter of data transferred */ + DMA_HandleTypeDef *hdmatx; /*!< Handle of the DMA channel used for transmit */ + DMA_HandleTypeDef *hdmarx; /*!< Handle of the DMA channel used for receive */ + __IO uint32_t State; /*!< Internal state of the XSPI HAL driver */ + __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ + uint32_t Timeout; /*!< Timeout used for the XSPI external device access */ +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + void (* ErrorCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* AbortCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* FifoThresholdCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* CmdCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* RxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* TxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* RxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* TxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* StatusMatchCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* TimeOutCallback)(struct __XSPI_HandleTypeDef *hxspi); + + void (* MspInitCallback)(struct __XSPI_HandleTypeDef *hxspi); + void (* MspDeInitCallback)(struct __XSPI_HandleTypeDef *hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ +} XSPI_HandleTypeDef; + +/** + * @brief HAL XSPI Regular Command Structure definition + */ +typedef struct +{ + uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or + to the registers for the write operation (these registers are only + used for memory-mapped mode). + This parameter can be a value of @ref XSPI_OperationType */ + uint32_t IOSelect; /*!< It indicates the IOs used to exchange data with external memory. + This parameter can be a value of @ref XSPI_IOSelect */ + uint32_t Instruction; /*!< It contains the instruction to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFFU */ + uint32_t InstructionMode; /*!< It indicates the mode of the instruction. + This parameter can be a value of @ref XSPI_InstructionMode */ + uint32_t InstructionWidth; /*!< It indicates the width of the instruction. + This parameter can be a value of @ref XSPI_InstructionWidth */ + uint32_t InstructionDTRMode; /*!< It enables or not the DTR mode for the instruction phase. + This parameter can be a value of @ref XSPI_InstructionDTRMode */ + uint32_t Address; /*!< It contains the address to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AddressMode; /*!< It indicates the address mode. Address mode precises number of lines + for address (except no address). + This parameter can be a value of @ref XSPI_AddressMode */ + uint32_t AddressWidth; /*!< It indicates the width of the address. + This parameter can be a value of @ref XSPI_AddressWidth */ + uint32_t AddressDTRMode; /*!< It enables or not the DTR mode for the address phase. + This parameter can be a value of @ref XSPI_AddressDTRMode */ + uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. + This parameter can be a value of @ref XSPI_AlternateBytesMode */ + uint32_t AlternateBytesWidth; /*!< It indicates the width of the alternate bytes. + This parameter can be a value of @ref XSPI_AlternateBytesWidth */ + uint32_t AlternateBytesDTRMode; /*!< It enables or not the DTR mode for the alternate bytes phase. + This parameter can be a value of @ref XSPI_AlternateBytesDTRMode */ + uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of lines + for data exchange (except no data). + This parameter can be a value of @ref XSPI_DataMode */ + uint32_t DataLength; /*!< It indicates the number of data transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between 1 and 0xFFFFFFFFU */ + uint32_t DataDTRMode; /*!< It enables or not the DTR mode for the data phase. + This parameter can be a value of @ref XSPI_DataDTRMode */ + uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. + This parameter can be a value between 0 and 31U */ + uint32_t DQSMode; /*!< It enables or not the data strobe management. + This parameter can be a value of @ref XSPI_DQSMode */ +} XSPI_RegularCmdTypeDef; +/** + * @brief HAL XSPI Hyperbus Configuration Structure definition + */ +typedef struct +{ + uint32_t RWRecoveryTimeCycle; /*!< It indicates the number of cycles for the device read write recovery time. + This parameter can be a value between 0 and 255U */ + uint32_t AccessTimeCycle; /*!< It indicates the number of cycles for the device access time. + This parameter can be a value between 0 and 255U */ + uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. + This parameter can be a value of @ref XSPI_WriteZeroLatency */ + uint32_t LatencyMode; /*!< It configures the latency mode. + This parameter can be a value of @ref XSPI_LatencyMode */ +} XSPI_HyperbusCfgTypeDef; + +/** + * @brief HAL XSPI Hyperbus Command Structure definition + */ +typedef struct +{ + uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. + This parameter can be a value of @ref XSPI_AddressSpace */ + uint32_t Address; /*!< It contains the address to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AddressWidth; /*!< It indicates the width of the address. + This parameter can be a value of @ref XSPI_AddressWidth */ + uint32_t DataLength; /*!< It indicates the number of data transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between 1 and 0xFFFFFFFF + In case of autopolling mode, this parameter can be + any value between 1 and 4 */ + uint32_t DQSMode; /*!< It enables or not the data strobe management. + This parameter can be a value of @ref XSPI_DQSMode */ + uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of lines + for data exchange (except no data). + This parameter can be a value of @ref XSPI_DataMode */ +} XSPI_HyperbusCmdTypeDef; + +/** + * @brief HAL XSPI Auto Polling mode configuration structure definition + */ +typedef struct +{ + uint32_t MatchValue; /*!< Specifies the value to be compared with the masked status register to get + a match. + This parameter can be any value between 0 and 0xFFFFFFFFU */ + uint32_t MatchMask; /*!< Specifies the mask to be applied to the status bytes received. + This parameter can be any value between 0 and 0xFFFFFFFFU */ + uint32_t MatchMode; /*!< Specifies the method used for determining a match. + This parameter can be a value of @ref XSPI_MatchMode */ + uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. + This parameter can be a value of @ref XSPI_AutomaticStop */ + uint32_t IntervalTime; /*!< Specifies the number of clock cycles between two read during automatic + polling phases. + This parameter can be any value between 0 and 0xFFFFU */ +} XSPI_AutoPollingTypeDef; + +/** + * @brief HAL XSPI Memory Mapped mode configuration structure definition + */ +typedef struct +{ + uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. + This parameter can be a value of @ref XSPI_TimeOutActivation */ + uint32_t TimeoutPeriodClock; /*!< Specifies the number of clock to wait when the FIFO is full before to + release the chip select. + This parameter can be any value between 0 and 0xFFFFU */ +} XSPI_MemoryMappedTypeDef; + +/** + * @brief HAL XSPI IO Manager Configuration structure definition + */ +typedef struct +{ + uint32_t nCSOverride; /*!< It indicates Chip select selector override setting for XSPI. + This parameter can be a value @ref XSPIM_MemorySelect_Override */ + uint32_t IOPort; /*!< It indicates which port of the XSPI IO Manager is used for the instance. + This parameter can be a value of @ref XSPI_IO_Manger_IOPort */ + uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) + expected if some signals are multiplexed in the XSPI IO Manager with the + other XSPI. + This parameter can be a value between 1 and 256 */ +} XSPIM_CfgTypeDef; + +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL XSPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_XSPI_ERROR_CB_ID = 0x00U, /*!< XSPI Error Callback ID */ + HAL_XSPI_ABORT_CB_ID = 0x01U, /*!< XSPI Abort Callback ID */ + HAL_XSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< XSPI FIFO Threshold Callback ID */ + HAL_XSPI_CMD_CPLT_CB_ID = 0x03U, /*!< XSPI Command Complete Callback ID */ + HAL_XSPI_RX_CPLT_CB_ID = 0x04U, /*!< XSPI Rx Complete Callback ID */ + HAL_XSPI_TX_CPLT_CB_ID = 0x05U, /*!< XSPI Tx Complete Callback ID */ + HAL_XSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< XSPI Rx Half Complete Callback ID */ + HAL_XSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< XSPI Tx Half Complete Callback ID */ + HAL_XSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< XSPI Status Match Callback ID */ + HAL_XSPI_TIMEOUT_CB_ID = 0x09U, /*!< XSPI Timeout Callback ID */ + HAL_XSPI_MSP_INIT_CB_ID = 0x0AU, /*!< XSPI MspInit Callback ID */ + HAL_XSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< XSPI MspDeInit Callback ID */ +} HAL_XSPI_CallbackIDTypeDef; + +/** + * @brief HAL XSPI Callback pointer definition + */ +typedef void (*pXSPI_CallbackTypeDef)(XSPI_HandleTypeDef *hxspi); + +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ +/** + * @brief HAL XSPI High-speed interface calibration structure definition + */ +typedef struct +{ + uint32_t DelayValueType; /*!< It indicates which calibration is concerned by the configuration. + This parameter can be a value of @ref XSPI_DelayType */ + uint32_t FineCalibrationUnit; /*!< It indicates the fine calibration value of the delay. + This parameter can be a value between 0 and 0x7FU */ + uint32_t CoarseCalibrationUnit; /*!< It indicates the coarse calibration value of the delay. + This parameter can be a value between 0 and 0x1FU */ + uint32_t MaxCalibration; /*!< It indicates that the calibration is outside the range of DLL master. + It applies only when the DelayValueType is HAL_XSPI_CAL_FULL_CYCLE_DELAY. + This parameter can be a value of @ref XSPI_MaxCal */ +} XSPI_HSCalTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup XSPI_Exported_Constants XSPI Exported Constants + * @{ + */ + +/** @defgroup XSPI_State XSPI State + * @{ + */ +#define HAL_XSPI_STATE_RESET (0x00000000U) /*!< Initial state */ +#define HAL_XSPI_STATE_READY (0x00000002U) /*!< Driver ready to be used */ +#define HAL_XSPI_STATE_HYPERBUS_INIT (0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ +#define HAL_XSPI_STATE_CMD_CFG (0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ +#define HAL_XSPI_STATE_READ_CMD_CFG (0x00000014U) /*!< Read command configuration done, not the write command configuration */ +#define HAL_XSPI_STATE_WRITE_CMD_CFG (0x00000024U) /*!< Write command configuration done, not the read command configuration */ +#define HAL_XSPI_STATE_BUSY_CMD (0x00000008U) /*!< Command without data on-going */ +#define HAL_XSPI_STATE_BUSY_TX (0x00000018U) /*!< Indirect Tx on-going */ +#define HAL_XSPI_STATE_BUSY_RX (0x00000028U) /*!< Indirect Rx on-going */ +#define HAL_XSPI_STATE_BUSY_AUTO_POLLING (0x00000048U) /*!< Auto-polling on-going */ +#define HAL_XSPI_STATE_BUSY_MEM_MAPPED (0x00000088U) /*!< Memory-mapped on-going */ +#define HAL_XSPI_STATE_ABORT (0x00000100U) /*!< Abort on-going */ +#define HAL_XSPI_STATE_ERROR (0x00000200U) /*!< Blocking error, driver should be re-initialized */ +/** + * @} + */ + +/** @defgroup XSPI_ErrorCode XSPI Error Code + * @{ + */ +#define HAL_XSPI_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_XSPI_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ +#define HAL_XSPI_ERROR_TRANSFER (0x00000002U) /*!< Transfer error */ +#define HAL_XSPI_ERROR_DMA (0x00000004U) /*!< DMA transfer error */ +#define HAL_XSPI_ERROR_INVALID_PARAM (0x00000008U) /*!< Invalid parameters error */ +#define HAL_XSPI_ERROR_INVALID_SEQUENCE (0x00000010U) /*!< Sequence is incorrect */ +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +#define HAL_XSPI_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid callback error */ +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ +/** + * @} + */ + +/** @defgroup XSPI_MemoryMode XSPI Memory Mode + * @{ + */ +#define HAL_XSPI_SINGLE_MEM (0x00000000U) /*!< Dual-memory mode disabled */ +#define HAL_XSPI_DUAL_MEM (XSPI_CR_DMM) /*!< Dual mode enabled */ + +/** + * @} + */ + +/** @defgroup XSPI_MemoryType XSPI Memory Type + * @{ + */ +#define HAL_XSPI_MEMTYPE_MICRON (0x00000000U) /*!< Micron mode */ +#define HAL_XSPI_MEMTYPE_MACRONIX (XSPI_DCR1_MTYP_0) /*!< Macronix mode */ +#define HAL_XSPI_MEMTYPE_APMEM (XSPI_DCR1_MTYP_1) /*!< AP Memory mode */ +#define HAL_XSPI_MEMTYPE_MACRONIX_RAM ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode*/ +#define HAL_XSPI_MEMTYPE_HYPERBUS (XSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ +#define HAL_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory mode */ + +/** + * @} + */ + +/** @defgroup XSPI_MemorySize XSPI Memory Size + * @{ + */ +#define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Byte = 2^( 0+1)) */ +#define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Byte = 2^( 1+1)) */ +#define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Byte = 2^( 2+1)) */ +#define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Byte = 2^( 3+1)) */ +#define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Byte = 2^( 4+1)) */ +#define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Byte = 2^( 5+1)) */ +#define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Byte = 2^( 6+1)) */ +#define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Byte = 2^( 7+1)) */ +#define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Byte = 2^( 8+1)) */ +#define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KByte = 2^( 9+1)) */ +#define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KByte = 2^(10+1)) */ +#define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KByte = 2^(11+1)) */ +#define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KByte = 2^(12+1)) */ +#define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KByte = 2^(13+1)) */ +#define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KByte = 2^(14+1)) */ +#define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KByte = 2^(15+1)) */ +#define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KByte = 2^(16+1)) */ +#define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KByte = 2^(17+1)) */ +#define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KByte = 2^(18+1)) */ +#define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MByte = 2^(19+1)) */ +#define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MByte = 2^(20+1)) */ +#define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MByte = 2^(21+1)) */ +#define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MByte = 2^(22+1)) */ +#define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MByte = 2^(23+1)) */ +#define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MByte = 2^(24+1)) */ +#define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MByte = 2^(25+1)) */ +#define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MByte = 2^(26+1)) */ +#define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MByte = 2^(27+1)) */ +#define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (256 MByte = 2^(28+1)) */ +#define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits (256 MByte = 2^(29+1)) */ +#define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits (256 MByte = 2^(30+1)) */ +#define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits (256 MByte = 2^(31+1)) */ +/** + * @} + */ + +/** @defgroup XSPI_FreeRunningClock XSPI Free Running Clock + * @{ + */ +#define HAL_XSPI_FREERUNCLK_DISABLE (0x00000000U) /*!< CLK is not free running */ +#define HAL_XSPI_FREERUNCLK_ENABLE ((uint32_t)XSPI_DCR1_FRCK) /*!< CLK is always provided (running) */ +/** + * @} + */ + +/** @defgroup XSPI_ClockMode XSPI Clock Mode + * @{ + */ +#define HAL_XSPI_CLOCK_MODE_0 (0x00000000U) /*!< CLK must stay low while nCS is high */ +#define HAL_XSPI_CLOCK_MODE_3 ((uint32_t)XSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ +/** + * @} + */ + +/** @defgroup XSPI_WrapSize XSPI Wrap-Size + * @{ + */ +#define HAL_XSPI_WRAP_NOT_SUPPORTED (0x00000000U) /*!< wrapped reads are not supported by the memory */ +#define HAL_XSPI_WRAP_16_BYTES ((uint32_t)XSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ +#define HAL_XSPI_WRAP_32_BYTES ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ +#define HAL_XSPI_WRAP_64_BYTES ((uint32_t)XSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ +#define HAL_XSPI_WRAP_128_BYTES ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ +/** + * @} + */ + +/** @defgroup XSPI_SampleShifting XSPI Sample Shifting + * @{ + */ +#define HAL_XSPI_SAMPLE_SHIFT_NONE (0x00000000U) /*!< No shift */ +#define HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE ((uint32_t)XSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ +/** + * @} + */ + +/** @defgroup XSPI_DelayHoldQuarterCycle XSPI Delay Hold Quarter Cycle + * @{ + */ +#define HAL_XSPI_DHQC_DISABLE (0x00000000U) /*!< No Delay */ +#define HAL_XSPI_DHQC_ENABLE ((uint32_t)XSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ +/** + * @} + */ + +/** @defgroup XSPI_ChipSelectBoundary XSPI Chip Select Boundary + * @{ + */ +#define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ +#define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Byte = 2^(1)) */ +#define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Byte = 2^(2)) */ +#define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Byte = 2^(3)) */ +#define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Byte = 2^(4)) */ +#define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Byte = 2^(5)) */ +#define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Byte = 2^(6)) */ +#define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Byte = 2^(7)) */ +#define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Byte = 2^(8)) */ +#define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Byte = 2^(9)) */ +#define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KByte = 2^(10)) */ +#define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KByte = 2^(11)) */ +#define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KByte = 2^(12)) */ +#define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KByte = 2^(13)) */ +#define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KByte = 2^(14)) */ +#define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KByte = 2^(15)) */ +#define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KByte = 2^(16)) */ +#define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KByte = 2^(17)) */ +#define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KByte = 2^(18)) */ +#define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KByte = 2^(19)) */ +#define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MByte = 2^(20)) */ +#define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MByte = 2^(21)) */ +#define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MByte = 2^(22)) */ +#define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MByte = 2^(23)) */ +#define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MByte = 2^(24)) */ +#define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MByte = 2^(25)) */ +#define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MByte = 2^(26)) */ +#define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MByte = 2^(27)) */ +#define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MByte = 2^(28)) */ +#define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MByte = 2^(29)) */ +#define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GByte = 2^(30)) */ +#define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GByte = 2^(31)) */ +/** + * @} + */ + +/** @defgroup XSPI_MemorySelect XSPI Memory Select + * @{ + */ +#define HAL_XSPI_CSSEL_NCS1 (0x00000000U) /*!< The output of nCS is nCS1 */ +#define HAL_XSPI_CSSEL_NCS2 ((uint32_t)XSPI_CR_CSSEL) /*!< The output of nCS is nCS2 */ +/** + * @} + */ + +/** @defgroup XSPI_OperationType XSPI Operation Type + * @{ + */ +#define HAL_XSPI_OPTYPE_COMMON_CFG (0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ +#define HAL_XSPI_OPTYPE_READ_CFG (0x00000001U) /*!< Read configuration (memory-mapped mode) */ +#define HAL_XSPI_OPTYPE_WRITE_CFG (0x00000002U) /*!< Write configuration (memory-mapped mode) */ +#define HAL_XSPI_OPTYPE_WRAP_CFG (0x00000003U) /*!< Wrap configuration (memory-mapped mode) */ + +/** + * @} + */ + +/** @defgroup XSPI_IOSelect XSPI IO Select + * @{ + */ +#define HAL_XSPI_SELECT_IO_3_0 (0x00000000U) /*!< Data exchanged over IO[3:0] */ +#define HAL_XSPI_SELECT_IO_7_4 ((uint32_t)XSPI_CR_MSEL_0) /*!< Data exchanged over IO[7:4] */ +#define HAL_XSPI_SELECT_IO_11_8 ((uint32_t)XSPI_CR_MSEL_1) /*!< Data exchanged over IO[11:8] */ +#define HAL_XSPI_SELECT_IO_15_12 ((uint32_t)XSPI_CR_MSEL ) /*!< Data exchanged over IO[15:12] */ +#define HAL_XSPI_SELECT_IO_7_0 (0x00000000U) /*!< Data exchanged over IO[7:0] */ +#define HAL_XSPI_SELECT_IO_15_8 ((uint32_t)XSPI_CR_MSEL_1) /*!< Data exchanged over IO[15:8] */ +/** + * @} + */ + +/** @defgroup XSPI_InstructionMode XSPI Instruction Mode + * @{ + */ +#define HAL_XSPI_INSTRUCTION_NONE (0x00000000U) /*!< No instruction */ +#define HAL_XSPI_INSTRUCTION_1_LINE ((uint32_t)XSPI_CCR_IMODE_0) /*!< Instruction on a single line */ +#define HAL_XSPI_INSTRUCTION_2_LINES ((uint32_t)XSPI_CCR_IMODE_1) /*!< Instruction on two lines */ +#define HAL_XSPI_INSTRUCTION_4_LINES ((uint32_t)(XSPI_CCR_IMODE_0 | XSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ +#define HAL_XSPI_INSTRUCTION_8_LINES ((uint32_t)XSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ +/** + * @} + */ + +/** @defgroup XSPI_InstructionWidth XSPI Instruction Width + * @{ + */ +#define HAL_XSPI_INSTRUCTION_8_BITS (0x00000000U) /*!< 8-bit instruction */ +#define HAL_XSPI_INSTRUCTION_16_BITS ((uint32_t)XSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ +#define HAL_XSPI_INSTRUCTION_24_BITS ((uint32_t)XSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ +#define HAL_XSPI_INSTRUCTION_32_BITS ((uint32_t)XSPI_CCR_ISIZE) /*!< 32-bit instruction */ +/** + * @} + */ + +/** @defgroup XSPI_InstructionDTRMode XSPI Instruction DTR Mode + * @{ + */ +#define HAL_XSPI_INSTRUCTION_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for instruction phase */ +#define HAL_XSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)XSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ +/** + * @} + */ + +/** @defgroup XSPI_AddressMode XSPI Address Mode + * @{ + */ +#define HAL_XSPI_ADDRESS_NONE (0x00000000U) /*!< No address */ +#define HAL_XSPI_ADDRESS_1_LINE ((uint32_t)XSPI_CCR_ADMODE_0) /*!< Address on a single line */ +#define HAL_XSPI_ADDRESS_2_LINES ((uint32_t)XSPI_CCR_ADMODE_1) /*!< Address on two lines */ +#define HAL_XSPI_ADDRESS_4_LINES ((uint32_t)(XSPI_CCR_ADMODE_0 | XSPI_CCR_ADMODE_1)) /*!< Address on four lines */ +#define HAL_XSPI_ADDRESS_8_LINES ((uint32_t)XSPI_CCR_ADMODE_2) /*!< Address on eight lines */ +/** + * @} + */ + +/** @defgroup XSPI_AddressWidth XSPI Address width + * @{ + */ +#define HAL_XSPI_ADDRESS_8_BITS (0x00000000U) /*!< 8-bit address */ +#define HAL_XSPI_ADDRESS_16_BITS ((uint32_t)XSPI_CCR_ADSIZE_0) /*!< 16-bit address */ +#define HAL_XSPI_ADDRESS_24_BITS ((uint32_t)XSPI_CCR_ADSIZE_1) /*!< 24-bit address */ +#define HAL_XSPI_ADDRESS_32_BITS ((uint32_t)XSPI_CCR_ADSIZE) /*!< 32-bit address */ +/** + * @} + */ + +/** @defgroup XSPI_AddressDTRMode XSPI Address DTR Mode + * @{ + */ +#define HAL_XSPI_ADDRESS_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for address phase */ +#define HAL_XSPI_ADDRESS_DTR_ENABLE ((uint32_t)XSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ +/** + * @} + */ + +/** @defgroup XSPI_AlternateBytesMode XSPI Alternate Bytes Mode + * @{ + */ +#define HAL_XSPI_ALT_BYTES_NONE (0x00000000U) /*!< No alternate bytes */ +#define HAL_XSPI_ALT_BYTES_1_LINE ((uint32_t)XSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ +#define HAL_XSPI_ALT_BYTES_2_LINES ((uint32_t)XSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ +#define HAL_XSPI_ALT_BYTES_4_LINES ((uint32_t)(XSPI_CCR_ABMODE_0 | XSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ +#define HAL_XSPI_ALT_BYTES_8_LINES ((uint32_t)XSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ +/** + * @} + */ + +/** @defgroup XSPI_AlternateBytesWidth XSPI Alternate Bytes Width + * @{ + */ +#define HAL_XSPI_ALT_BYTES_8_BITS (0x00000000U) /*!< 8-bit alternate bytes */ +#define HAL_XSPI_ALT_BYTES_16_BITS ((uint32_t)XSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ +#define HAL_XSPI_ALT_BYTES_24_BITS ((uint32_t)XSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ +#define HAL_XSPI_ALT_BYTES_32_BITS ((uint32_t)XSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ +/** + * @} + */ + +/** @defgroup XSPI_AlternateBytesDTRMode XSPI Alternate Bytes DTR Mode + * @{ + */ +#define HAL_XSPI_ALT_BYTES_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ +#define HAL_XSPI_ALT_BYTES_DTR_ENABLE ((uint32_t)XSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ +/** + * @} + */ + +/** @defgroup XSPI_DataMode XSPI Data Mode + * @{ + */ +#define HAL_XSPI_DATA_NONE (0x00000000U) /*!< No data */ +#define HAL_XSPI_DATA_1_LINE ((uint32_t)XSPI_CCR_DMODE_0) /*!< Data on a single line */ +#define HAL_XSPI_DATA_2_LINES ((uint32_t)XSPI_CCR_DMODE_1) /*!< Data on two lines */ +#define HAL_XSPI_DATA_4_LINES ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_1)) /*!< Data on four lines */ +#define HAL_XSPI_DATA_8_LINES ((uint32_t)XSPI_CCR_DMODE_2) /*!< Data on eight lines */ +#define HAL_XSPI_DATA_16_LINES ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_2)) /*!< Data on sixteen lines valid for HSPI only */ +/** + * @} + */ + +/** @defgroup XSPI_DataDTRMode XSPI Data DTR Mode + * @{ + */ +#define HAL_XSPI_DATA_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for data phase */ +#define HAL_XSPI_DATA_DTR_ENABLE ((uint32_t)XSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ +/** + * @} + */ + +/** @defgroup XSPI_DQSMode XSPI DQS Mode + * @{ + */ +#define HAL_XSPI_DQS_DISABLE (0x00000000U) /*!< DQS disabled */ +#define HAL_XSPI_DQS_ENABLE ((uint32_t)XSPI_CCR_DQSE) /*!< DQS enabled */ +/** + * @} + */ + +/** @defgroup XSPI_WriteZeroLatency XSPI Hyperbus Write Zero Latency Activation + * @{ + */ +#define HAL_XSPI_LATENCY_ON_WRITE (0x00000000U) /*!< Latency on write accesses */ +#define HAL_XSPI_NO_LATENCY_ON_WRITE ((uint32_t)XSPI_HLCR_WZL) /*!< No latency on write accesses */ +/** + * @} + */ + +/** @defgroup XSPI_LatencyMode XSPI Hyperbus Latency Mode + * @{ + */ +#define HAL_XSPI_VARIABLE_LATENCY (0x00000000U) /*!< Variable initial latency */ +#define HAL_XSPI_FIXED_LATENCY ((uint32_t)XSPI_HLCR_LM) /*!< Fixed latency */ +/** + * @} + */ + +/** @defgroup XSPI_AddressSpace XSPI Hyperbus Address Space + * @{ + */ +#define HAL_XSPI_MEMORY_ADDRESS_SPACE (0x00000000U) /*!< HyperBus memory mode */ +#define HAL_XSPI_REGISTER_ADDRESS_SPACE ((uint32_t)XSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ +/** + * @} + */ + +/** @defgroup XSPI_MatchMode XSPI Match Mode + * @{ + */ +#define HAL_XSPI_MATCH_MODE_AND (0x00000000U) /*!< AND match mode between unmasked bits */ +#define HAL_XSPI_MATCH_MODE_OR ((uint32_t)XSPI_CR_PMM) /*!< OR match mode between unmasked bits */ +/** + * @} + */ + +/** @defgroup XSPI_AutomaticStop XSPI Automatic Stop + * @{ + */ +#define HAL_XSPI_AUTOMATIC_STOP_DISABLE (0x00000000U) /*!< AutoPolling stops only with abort or XSPI disabling */ +#define HAL_XSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)XSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ +/** + * @} + */ + +/** @defgroup XSPI_TimeOutActivation XSPI Timeout Activation + * @{ + */ +#define HAL_XSPI_TIMEOUT_COUNTER_DISABLE (0x00000000U) /*!< Timeout counter disabled, nCS remains active */ +#define HAL_XSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)XSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ +/** + * @} + */ + +/** @defgroup XSPI_Flags XSPI Flags + * @{ + */ +#define HAL_XSPI_FLAG_BUSY XSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ +#define HAL_XSPI_FLAG_TO XSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ +#define HAL_XSPI_FLAG_SM XSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ +#define HAL_XSPI_FLAG_FT XSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ +#define HAL_XSPI_FLAG_TC XSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ +#define HAL_XSPI_FLAG_TE XSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ +/** + * @} + */ + +/** @defgroup XSPI_Interrupts XSPI Interrupts + * @{ + */ +#define HAL_XSPI_IT_TO XSPI_CR_TOIE /*!< Interrupt on the timeout flag */ +#define HAL_XSPI_IT_SM XSPI_CR_SMIE /*!< Interrupt on the status match flag */ +#define HAL_XSPI_IT_FT XSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ +#define HAL_XSPI_IT_TC XSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ +#define HAL_XSPI_IT_TE XSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ +/** + * @} + */ + +/** @defgroup XSPI_Timeout_definition XSPI Timeout definition + * @{ + */ +#define HAL_XSPI_TIMEOUT_DEFAULT_VALUE (5000U) /* 5 s */ +/** + * @} + */ + +/** @defgroup XSPI_IO_Manger_IOPort XSPI IO Port + * @{ + */ +#define HAL_XSPIM_IOPORT_1 (0x00000000U) /*!< Port 1 */ +#define HAL_XSPIM_IOPORT_2 (0x00000001U) /*!< Port 2 */ +/** + * @} + */ + + +/** @defgroup XSPI_DelayType XSPI Calibration Delay Type + * @{ + */ +#define HAL_XSPI_CAL_FULL_CYCLE_DELAY (0x00000000U) /*!< Delay value equivalent to full memory-clock cycle */ +#define HAL_XSPI_CAL_FEEDBACK_CLK_DELAY (0x00000001U) /*!< Delay value for the feedback clock when reading without DQS */ +#define HAL_XSPI_CAL_DATA_OUTPUT_DELAY (0x00000002U) /*!< Delay value for output data in DDR mode for write operations */ +#define HAL_XSPI_CAL_DQS_INPUT_DELAY (0x00000003U) /*!< Delay value for DQS input when sampling data for read operations */ +/** + * @} + */ + +/** @defgroup XSPIM_MemorySelect_Override XSPIM Memory Select Override + * @{ + */ +#define HAL_XSPI_CSSEL_OVR_DISABLED (0x00000000U) +#define HAL_XSPI_CSSEL_OVR_NCS1 (0x00000010U) /*!< The chip select signal from XSPI is sent to NCS1 */ +#define HAL_XSPI_CSSEL_OVR_NCS2 (0x00000070U) /*!< The chip select signal from XSPI is sent to NCS2 */ +/** + * @} + */ + +/** @defgroup XSPI_MaxCal XSPI Calibration Maximal Value + * @{ + */ +#define HAL_XSPI_MAXCAL_NOT_REACHED (0x00000000U) /*!< Memory-clock perido inside the range of DLL master */ +#define HAL_XSPI_MAXCAL_REACHED ((uint32_t)XSPI_CALFCR_CALMAX) /*!< Memory-clock period outside the range of DLL master (max delay values used) */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup XSPI_Exported_Macros XSPI Exported Macros + * @{ + */ +/** @brief Reset XSPI handle state. + * @param __HANDLE__ specifies the XSPI Handle. + * @retval None + */ +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +#define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_XSPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_XSPI_STATE_RESET) +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + +/** @brief Enable the XSPI peripheral. + * @param __HANDLE__ specifies the XSPI Handle. + * @retval None + */ +#define HAL_XSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN) + +/** @brief Disable the XSPI peripheral. + * @param __HANDLE__ specifies the XSPI Handle. + * @retval None + */ +#define HAL_XSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN) + +/** @brief Enable the specified XSPI interrupt. + * @param __HANDLE__ specifies the XSPI Handle. + * @param __INTERRUPT__ specifies the XSPI interrupt source to enable. + * This parameter can be one of the following values: + * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt + * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt + * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt + * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt + * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt + * @retval None + */ +#define HAL_XSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) + +/** @brief Disable the specified XSPI interrupt. + * @param __HANDLE__ specifies the XSPI Handle. + * @param __INTERRUPT__ specifies the XSPI interrupt source to disable. + * This parameter can be one of the following values: + * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt + * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt + * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt + * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt + * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt + * @retval None + */ +#define HAL_XSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) + +/** @brief Check whether the specified XSPI interrupt source is enabled or not. + * @param __HANDLE__ specifies the XSPI Handle. + * @param __INTERRUPT__ specifies the XSPI interrupt source to check. + * This parameter can be one of the following values: + * @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt + * @arg HAL_XSPI_IT_SM: XSPI Status match interrupt + * @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt + * @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt + * @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define HAL_XSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\ + == (__INTERRUPT__)) + +/** + * @brief Check whether the selected XSPI flag is set or not. + * @param __HANDLE__ specifies the XSPI Handle. + * @param __FLAG__ specifies the XSPI flag to check. + * This parameter can be one of the following values: + * @arg HAL_XSPI_FLAG_BUSY: XSPI Busy flag + * @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag + * @arg HAL_XSPI_FLAG_SM: XSPI Status match flag + * @arg HAL_XSPI_FLAG_FT: XSPI FIFO threshold flag + * @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag + * @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag + * @retval None + */ +#define HAL_XSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \ + != 0U) ? SET : RESET) + +/** @brief Clears the specified XSPI's flag status. + * @param __HANDLE__ specifies the XSPI Handle. + * @param __FLAG__ specifies the XSPI clear register flag that needs to be set + * This parameter can be one of the following values: + * @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag + * @arg HAL_XSPI_FLAG_SM: XSPI Status match flag + * @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag + * @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag + * @retval None + */ +#define HAL_XSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup XSPI_Exported_Functions XSPI Exported Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup XSPI_Exported_Functions_Group1 Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi); +HAL_StatusTypeDef HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi); + +/** + * @} + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup XSPI_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* XSPI IRQ handler function */ +void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi); + +/* XSPI command configuration functions */ +HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd, + uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd); +HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pCfg, + uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pCmd, + uint32_t Timeout); + +/* XSPI indirect mode functions */ +HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); +HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); +HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); + +/* XSPI status flag polling mode functions */ +HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg, + uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg); + +/* XSPI memory-mapped mode functions */ +HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const pCfg); + +/* Callback functions in non-blocking modes ***********************************/ +void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi); + +/* XSPI indirect mode Callback functions */ +void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi); +void HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi); + +/* XSPI status flag polling mode functions */ +void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi); + +/* XSPI memory-mapped mode functions */ +void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi); + +#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +/* XSPI callback registering/unregistering */ +HAL_StatusTypeDef HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID, + pXSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + +/** + * @} + */ + +/* Peripheral Control and State functions ************************************/ +/** @addtogroup XSPI_Exported_Functions_Group3 Peripheral Control and State functions + * @{ + */ +HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi); +HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi); +HAL_StatusTypeDef HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold); +uint32_t HAL_XSPI_GetFifoThreshold(const XSPI_HandleTypeDef *hxspi); +HAL_StatusTypeDef HAL_XSPI_SetMemoryType(XSPI_HandleTypeDef *hxspi, uint32_t Type); +HAL_StatusTypeDef HAL_XSPI_SetDeviceSize(XSPI_HandleTypeDef *hxspi, uint32_t Size); +HAL_StatusTypeDef HAL_XSPI_SetClockPrescaler(XSPI_HandleTypeDef *hxspi, uint32_t Prescaler); +HAL_StatusTypeDef HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout); +uint32_t HAL_XSPI_GetError(const XSPI_HandleTypeDef *hxspi); +uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi); + +/** + * @} + */ + +/* XSPI IO Manager configuration function ************************************/ +/** @addtogroup XSPI_Exported_Functions_Group4 IO Manager configuration function + * @{ + */ +HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout); + +/** + * @} + */ + +/* XSPI high-speed interface and calibration functions ***********************/ +/** @addtogroup XSPI_Exported_Functions_Group6 High-speed interface and calibration functions + * @{ + */ +HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg); +HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg); + +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** + @cond 0 + */ +#define IS_XSPI_FIFO_THRESHOLD_BYTE(THRESHOLD) (((THRESHOLD) >= 1U) &&\ + ((THRESHOLD) <= ((XSPI_CR_FTHRES >> XSPI_CR_FTHRES_Pos)+1U))) +#define IS_XSPI_MEMORY_MODE(MODE) (((MODE) == HAL_XSPI_SINGLE_MEM) || \ + ((MODE) == HAL_XSPI_DUAL_MEM)) + +#define IS_XSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_XSPI_MEMTYPE_MICRON) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_APMEM) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX_RAM) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_HYPERBUS) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_APMEM_16BITS)) + +#define IS_XSPI_MEMORY_SIZE(SIZE) (((SIZE) == HAL_XSPI_SIZE_16B) || \ + ((SIZE) == HAL_XSPI_SIZE_32B) || \ + ((SIZE) == HAL_XSPI_SIZE_64B) || \ + ((SIZE) == HAL_XSPI_SIZE_128B) || \ + ((SIZE) == HAL_XSPI_SIZE_256B) || \ + ((SIZE) == HAL_XSPI_SIZE_512B) || \ + ((SIZE) == HAL_XSPI_SIZE_1KB) || \ + ((SIZE) == HAL_XSPI_SIZE_2KB) || \ + ((SIZE) == HAL_XSPI_SIZE_4KB) || \ + ((SIZE) == HAL_XSPI_SIZE_8KB) || \ + ((SIZE) == HAL_XSPI_SIZE_16KB) || \ + ((SIZE) == HAL_XSPI_SIZE_32KB) || \ + ((SIZE) == HAL_XSPI_SIZE_64KB) || \ + ((SIZE) == HAL_XSPI_SIZE_128KB) || \ + ((SIZE) == HAL_XSPI_SIZE_256KB) || \ + ((SIZE) == HAL_XSPI_SIZE_512KB) || \ + ((SIZE) == HAL_XSPI_SIZE_1MB) || \ + ((SIZE) == HAL_XSPI_SIZE_2MB) || \ + ((SIZE) == HAL_XSPI_SIZE_4MB) || \ + ((SIZE) == HAL_XSPI_SIZE_8MB) || \ + ((SIZE) == HAL_XSPI_SIZE_16MB) || \ + ((SIZE) == HAL_XSPI_SIZE_32MB) || \ + ((SIZE) == HAL_XSPI_SIZE_64MB) || \ + ((SIZE) == HAL_XSPI_SIZE_128MB) || \ + ((SIZE) == HAL_XSPI_SIZE_256MB) || \ + ((SIZE) == HAL_XSPI_SIZE_512MB) || \ + ((SIZE) == HAL_XSPI_SIZE_1GB) || \ + ((SIZE) == HAL_XSPI_SIZE_2GB) || \ + ((SIZE) == HAL_XSPI_SIZE_4GB) || \ + ((SIZE) == HAL_XSPI_SIZE_8GB) || \ + ((SIZE) == HAL_XSPI_SIZE_16GB) || \ + ((SIZE) == HAL_XSPI_SIZE_32GB)) + +#define IS_XSPI_CS_HIGH_TIME_CYCLE(TIME) (((TIME) >= 1U) && ((TIME) <= 64U)) + +#define IS_XSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_XSPI_FREERUNCLK_DISABLE) || \ + ((CLK) == HAL_XSPI_FREERUNCLK_ENABLE)) + +#define IS_XSPI_CLOCK_MODE(MODE) (((MODE) == HAL_XSPI_CLOCK_MODE_0) || \ + ((MODE) == HAL_XSPI_CLOCK_MODE_3)) + +#define IS_XSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_XSPI_WRAP_NOT_SUPPORTED) || \ + ((SIZE) == HAL_XSPI_WRAP_16_BYTES) || \ + ((SIZE) == HAL_XSPI_WRAP_32_BYTES) || \ + ((SIZE) == HAL_XSPI_WRAP_64_BYTES) || \ + ((SIZE) == HAL_XSPI_WRAP_128_BYTES)) + +#define IS_XSPI_CLK_PRESCALER(PRESCALER) ((PRESCALER) <= 255U) + +#define IS_XSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_NONE) || \ + ((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE)) + +#define IS_XSPI_DHQC(CYCLE) (((CYCLE) == HAL_XSPI_DHQC_DISABLE) || \ + ((CYCLE) == HAL_XSPI_DHQC_ENABLE)) + +#define IS_XSPI_CS_BOUND(SIZE) (((SIZE) == HAL_XSPI_BONDARYOF_NONE) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_16B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_32B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_64B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_128B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_256B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_512B) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_1KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_2KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_4KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_8KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_16KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_32KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_64KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_128KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_256KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_512KB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_1MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_2MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_4MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_8MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_16MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_32MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_64MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_128MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_256MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_512MB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_1GB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_2GB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_4GB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_8GB) || \ + ((SIZE) == HAL_XSPI_BONDARYOF_16GB)) + + +#define IS_XSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) + +#define IS_XSPI_CSSEL(CSSEL) (((CSSEL) == HAL_XSPI_CSSEL_NCS1) || \ + ((CSSEL) == HAL_XSPI_CSSEL_NCS2)) + +#define IS_XSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \ + ((TYPE) == HAL_XSPI_OPTYPE_READ_CFG) || \ + ((TYPE) == HAL_XSPI_OPTYPE_WRITE_CFG) || \ + ((TYPE) == HAL_XSPI_OPTYPE_WRAP_CFG)) + +#define IS_XSPI_IO_SELECT(MEMSEL) (((MEMSEL) == HAL_XSPI_SELECT_IO_3_0) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_7_4) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_11_8) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_15_12) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_7_0) || \ + ((MEMSEL) == HAL_XSPI_SELECT_IO_15_8)) + +#define IS_XSPI_INSTRUCTION(OPCODE) ((OPCODE) <= 0xFFFFFFFFU) + +#define IS_XSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_NONE) || \ + ((MODE) == HAL_XSPI_INSTRUCTION_1_LINE) || \ + ((MODE) == HAL_XSPI_INSTRUCTION_2_LINES) || \ + ((MODE) == HAL_XSPI_INSTRUCTION_4_LINES) || \ + ((MODE) == HAL_XSPI_INSTRUCTION_8_LINES)) + +#define IS_XSPI_INSTRUCTION_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_INSTRUCTION_8_BITS) || \ + ((WIDTH) == HAL_XSPI_INSTRUCTION_16_BITS) || \ + ((WIDTH) == HAL_XSPI_INSTRUCTION_24_BITS) || \ + ((WIDTH) == HAL_XSPI_INSTRUCTION_32_BITS)) + +#define IS_XSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_DTR_DISABLE) || \ + ((MODE) == HAL_XSPI_INSTRUCTION_DTR_ENABLE)) + +#define IS_XSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_NONE) || \ + ((MODE) == HAL_XSPI_ADDRESS_1_LINE) || \ + ((MODE) == HAL_XSPI_ADDRESS_2_LINES) || \ + ((MODE) == HAL_XSPI_ADDRESS_4_LINES) || \ + ((MODE) == HAL_XSPI_ADDRESS_8_LINES)) + +#define IS_XSPI_ADDRESS_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_ADDRESS_8_BITS) || \ + ((WIDTH) == HAL_XSPI_ADDRESS_16_BITS) || \ + ((WIDTH) == HAL_XSPI_ADDRESS_24_BITS) || \ + ((WIDTH) == HAL_XSPI_ADDRESS_32_BITS)) + +#define IS_XSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_DTR_DISABLE) || \ + ((MODE) == HAL_XSPI_ADDRESS_DTR_ENABLE)) + +#define IS_XSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_NONE) || \ + ((MODE) == HAL_XSPI_ALT_BYTES_1_LINE) || \ + ((MODE) == HAL_XSPI_ALT_BYTES_2_LINES) || \ + ((MODE) == HAL_XSPI_ALT_BYTES_4_LINES) || \ + ((MODE) == HAL_XSPI_ALT_BYTES_8_LINES)) + +#define IS_XSPI_ALT_BYTES_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_ALT_BYTES_8_BITS) || \ + ((WIDTH) == HAL_XSPI_ALT_BYTES_16_BITS) || \ + ((WIDTH) == HAL_XSPI_ALT_BYTES_24_BITS) || \ + ((WIDTH) == HAL_XSPI_ALT_BYTES_32_BITS)) + +#define IS_XSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_DTR_DISABLE) || \ + ((MODE) == HAL_XSPI_ALT_BYTES_DTR_ENABLE)) + +#define IS_XSPI_DATA_MODE(TYPE,MODE) (((TYPE) == (HAL_XSPI_MEMTYPE_HYPERBUS)) ? \ + (((MODE) == HAL_XSPI_DATA_NONE) || \ + ((MODE) == HAL_XSPI_DATA_8_LINES) || \ + ((MODE) == HAL_XSPI_DATA_16_LINES)): \ + (((MODE) == HAL_XSPI_DATA_NONE) || \ + ((MODE) == HAL_XSPI_DATA_1_LINE) || \ + ((MODE) == HAL_XSPI_DATA_2_LINES) || \ + ((MODE) == HAL_XSPI_DATA_4_LINES) || \ + ((MODE) == HAL_XSPI_DATA_8_LINES) || \ + ((MODE) == HAL_XSPI_DATA_16_LINES))) +#define IS_XSPI_DATA_LENGTH(NUMBER) ((NUMBER) >= 1U) + +#define IS_XSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_XSPI_DATA_DTR_DISABLE) || \ + ((MODE) == HAL_XSPI_DATA_DTR_ENABLE)) + +#define IS_XSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) + +#define IS_XSPI_DQS_MODE(MODE) (((MODE) == HAL_XSPI_DQS_DISABLE) || \ + ((MODE) == HAL_XSPI_DQS_ENABLE)) + +#define IS_XSPI_RW_RECOVERY_TIME_CYCLE(CYCLE) ((CYCLE) <= 255U) + +#define IS_XSPI_ACCESS_TIME_CYCLE(CYCLE) ((CYCLE) <= 255U) + +#define IS_XSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_XSPI_LATENCY_ON_WRITE) || \ + ((MODE) == HAL_XSPI_NO_LATENCY_ON_WRITE)) + +#define IS_XSPI_LATENCY_MODE(MODE) (((MODE) == HAL_XSPI_VARIABLE_LATENCY) || \ + ((MODE) == HAL_XSPI_FIXED_LATENCY)) + +#define IS_XSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_XSPI_MEMORY_ADDRESS_SPACE) || \ + ((SPACE) == HAL_XSPI_REGISTER_ADDRESS_SPACE)) + +#define IS_XSPI_MATCH_MODE(MODE) (((MODE) == HAL_XSPI_MATCH_MODE_AND) || \ + ((MODE) == HAL_XSPI_MATCH_MODE_OR)) + +#define IS_XSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_XSPI_AUTOMATIC_STOP_ENABLE) || \ + ((MODE) == HAL_XSPI_AUTOMATIC_STOP_DISABLE)) + +#define IS_XSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) + +#define IS_XSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) + +#define IS_XSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_XSPI_TIMEOUT_COUNTER_DISABLE) || \ + ((MODE) == HAL_XSPI_TIMEOUT_COUNTER_ENABLE)) + +#define IS_XSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) + +#define IS_XSPIM_IO_PORT(PORT) (((PORT) == HAL_XSPIM_IOPORT_1) || \ + ((PORT) == HAL_XSPIM_IOPORT_2)) + +#define IS_XSPIM_NCS_OVR(PORT) (((PORT) == HAL_XSPI_CSSEL_OVR_DISABLED) || \ + ((PORT) == HAL_XSPI_CSSEL_OVR_NCS1) || \ + ((PORT) == HAL_XSPI_CSSEL_OVR_NCS2)) + +#define IS_XSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U)) + +#define IS_XSPI_DELAY_TYPE(TYPE) (((TYPE) == HAL_XSPI_CAL_FULL_CYCLE_DELAY) || \ + ((TYPE) == HAL_XSPI_CAL_FEEDBACK_CLK_DELAY) || \ + ((TYPE) == HAL_XSPI_CAL_DATA_OUTPUT_DELAY) || \ + ((TYPE) == HAL_XSPI_CAL_DQS_INPUT_DELAY)) + +#define IS_XSPI_FINECAL_VALUE(VALUE) ((VALUE) <= 0x7FU) + +#define IS_XSPI_COARSECAL_VALUE(VALUE) ((VALUE) <= 0x1FU) + +/** + @endcond + */ + +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* XSPI || XSPI1 || XSPI2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_XSPI_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_adc.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_adc.h new file mode 100644 index 00000000000..329c3d224fb --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_adc.h @@ -0,0 +1,8263 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_adc.h + * @author MCD Application Team + * @brief Header file of ADC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_ADC_H +#define STM32H7RSxx_LL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (ADC1) || defined (ADC2) + +/** @defgroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Constants ADC Private Constants + * @{ + */ + +/* Internal mask for ADC group regular sequencer: */ +/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ +/* - sequencer register offset */ +/* - sequencer rank bits position into the selected register */ + +/* Internal register offset for ADC group regular sequencer configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_SQR1_REGOFFSET (0x00000000UL) +#define ADC_SQR2_REGOFFSET (0x00000100UL) +#define ADC_SQR3_REGOFFSET (0x00000200UL) +#define ADC_SQR4_REGOFFSET (0x00000300UL) + +#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \ + | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) +#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/ +#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) + +/* Definition of ADC group regular sequencer bits information to be inserted */ +/* into ADC group regular sequencer ranks literals definition. */ +#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos) +#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos) +#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos) +#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos) +#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos) +#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos) +#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos) +#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos) +#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos) +#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos) +#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos) +#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos) +#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos) +#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos) +#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos) +#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos) + + + +/* Internal mask for ADC group injected sequencer: */ +/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ +/* - data register offset */ +/* - sequencer rank bits position into the selected register */ + +/* Internal register offset for ADC group injected data register */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_JDR1_REGOFFSET (0x00000000UL) +#define ADC_JDR2_REGOFFSET (0x00000100UL) +#define ADC_JDR3_REGOFFSET (0x00000200UL) +#define ADC_JDR4_REGOFFSET (0x00000300UL) + +#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \ + | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) +#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) +#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/ + +/* Definition of ADC group injected sequencer bits information to be inserted */ +/* into ADC group injected sequencer ranks literals definition. */ +#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos) +#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos) +#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos) +#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos) + + + +/* Internal mask for ADC group regular trigger: */ +/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ +/* - regular trigger source */ +/* - regular trigger edge */ +#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for + compatibility with some ADC on other STM32 series + having this setting set by HW default value) */ + +/* Mask containing trigger source masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \ + ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \ + ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \ + ((ADC_CFGR_EXTSEL) << (4U * 3UL)) ) + +/* Mask containing trigger edge masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) + +/* Definition of ADC group regular trigger bits information. */ +#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos) +#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos) + + + +/* Internal mask for ADC group injected trigger: */ +/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ +/* - injected trigger source */ +/* - injected trigger edge */ +#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for + compatibility with some ADC on other STM32 series + having this setting set by HW default value) */ + +/* Mask containing trigger source masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) ) + +/* Mask containing trigger edge masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) + +/* Definition of ADC group injected trigger bits information. */ +#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos) +#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos) + + + + + + +/* Internal mask for ADC channel: */ +/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ +/* - channel identifier defined by number */ +/* - channel identifier defined by bitfield */ +/* - channel differentiation between external channels (connected to */ +/* GPIO pins) and internal channels (connected to internal paths) */ +/* - channel sampling time defined by SMPRx register offset */ +/* and SMPx bits positions into SMPRx register */ +#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH) +#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH) +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos) +#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \ + | ADC_CHANNEL_ID_INTERNAL_CH_MASK) +/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK + >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ + +/* Channel differentiation between external and internal channels */ +#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */ +#define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case + of different ADC internal channels mapped on same channel + number on different ADC instances */ +#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) + +/* Internal register offset for ADC channel sampling time configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_SMPR1_REGOFFSET (0x00000000UL) +#define ADC_SMPR2_REGOFFSET (0x02000000UL) +#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) +#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET + in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */ + +#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL) +#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" + position in register */ + +/* Definition of channels ID number information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_NUMBER (0x00000000UL) +#define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2) +#define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3) +#define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2) +#define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \ + ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4) +#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1) + +/* Definition of channels ID bitfield information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0) +#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1) +#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2) +#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3) +#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4) +#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5) +#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6) +#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7) +#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8) +#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9) +#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10) +#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11) +#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12) +#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13) +#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14) +#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15) +#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16) +#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17) +#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18) + +/* Definition of channels sampling time information to be inserted into */ +/* channels literals definition. */ +/* Value shifted are equivalent to bitfield "ADC_SMPRx_SMPy" position */ +/* in register. */ +#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) +#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) + + +/* Internal mask for ADC mode single or differential ended: */ +/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */ +/* the relevant bits for: */ +/* (concatenation of multiple bits used in different registers) */ +/* - ADC calibration: calibration start, calibration factor get or set */ +/* - ADC channels: set each ADC channel ending mode */ +#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF) +#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S) +#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */ +#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen + to perform of shift when single mode is selected, shift value out of + channels bits range. */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: + mask of bit */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: + position of bit */ +#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit + ADC_SINGLEDIFF_CALIB_F_BIT_D to perform a shift of 4 ranks */ + +/* Internal mask for ADC analog watchdog: */ +/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ +/* (concatenation of multiple bits used in different analog watchdogs, */ +/* (feature of several watchdogs not available on all STM32 series)). */ +/* - analog watchdog 1: monitored channel defined by number, */ +/* selection of ADC group (ADC groups regular and-or injected). */ +/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */ +/* selection on groups. */ + +/* Internal register offset for ADC analog watchdog channel configuration */ +#define ADC_AWD_CR1_REGOFFSET (0x00000000UL) +#define ADC_AWD_CR2_REGOFFSET (0x00100000UL) +#define ADC_AWD_CR3_REGOFFSET (0x00200000UL) + +/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */ +/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */ +#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0) +#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL) + +#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET) + +#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) +#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) +#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) + +#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET + in ADC_AWD_CRX_REGOFFSET_MASK */ + +/* Internal register offset for ADC analog watchdog threshold configuration */ +#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) +#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) +#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET) +#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) +#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET + in ADC_AWD_TRX_REGOFFSET_MASK */ +#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate + threshold high: mask of bit */ +#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate + threshold high: position of bit */ +#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to + position to perform a shift of 4 ranks */ + +/* Internal mask for ADC offset: */ +/* Internal register offset for ADC offset instance configuration */ +#define ADC_OFR1_REGOFFSET (0x00000000UL) +#define ADC_OFR2_REGOFFSET (0x00000001UL) +#define ADC_OFR3_REGOFFSET (0x00000002UL) +#define ADC_OFR4_REGOFFSET (0x00000003UL) +#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \ + | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET) + + +/* ADC registers bits positions */ +#define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos) +#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos) +#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos) +#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos) +#define ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos) + + +/* ADC registers bits groups */ +#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \ + | ADC_CR_JADSTART | ADC_CR_JADSTP \ + | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with + HW property "rs": Software can read as well as set this bit. + Writing '0' has no effect on the bit value. */ + + +/* ADC internal channels related definitions */ +/* Internal voltage reference VrefInt */ +#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF1E810UL)) /* Internal voltage reference, address of + parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC + (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_VREF (3300UL) /* Analog voltage reference (Vref+) value + with which VrefInt has been calibrated in production + (tolerance: +-10 mV) (unit: mV). */ +/* Temperature sensor */ +#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF1E814UL)) /* Address of parameter TS_CAL1: On STM32H7RS, + temperature sensor ADC raw data acquired at temperature 30 DegC + (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF1E818UL)) /* Address of parameter TS_CAL2: On STM32H7RS, + temperature sensor ADC raw data acquired at temperature 130 DegC + (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_TEMP (30L) /* Temperature at which temperature sensor + has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR + (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL2_TEMP (130L) /* Temperature at which temperature sensor + has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR + (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) value + with which temperature sensor has been calibrated in production + (tolerance +-10 mV) (unit: mV). */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Macros ADC Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param __REG__ Register basis from which the offset is applied. + * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @retval Pointer to register address + */ +#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure + * @{ + */ + +/** + * @brief Structure definition of some features of ADC common parameters + * and multimode + * (all ADC instances belonging to the same ADC common instance). + * @note The setting of these parameters by function @ref LL_ADC_CommonInit() + * is conditioned to ADC instances state (all ADC instances + * sharing the same ADC common instance): + * All ADC instances sharing the same ADC common instance must be + * disabled. + */ +typedef struct +{ + uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. + This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE + @note On this STM32 series, if ADC group injected is used, some clock ratio + constraints between ADC clock and AHB clock must be respected. + Refer to reference manual. + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetCommonClock(). */ + +#if defined(ADC_MULTIMODE_SUPPORT) + uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode + (for devices with several ADC instances). + This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetMultimode(). */ + + uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. + This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetMultiDMATransfer(). */ + + uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. + This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetMultiTwoSamplingDelay(). */ +#endif /* ADC_MULTIMODE_SUPPORT */ + +} LL_ADC_CommonInitTypeDef; + +/** + * @brief Structure definition of some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Affects both group regular and group injected (availability + * of ADC group injected depends on STM32 series). + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 series. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t Resolution; /*!< Set ADC resolution. + This parameter can be a value of @ref ADC_LL_EC_RESOLUTION + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetResolution(). */ + + uint32_t DataAlignment; /*!< Set ADC conversion data alignment. + This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetDataAlignment(). */ + + uint32_t LowPowerMode; /*!< Set ADC low power mode. + This parameter can be a value of @ref ADC_LL_EC_LP_MODE + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetLowPowerMode(). */ + +} LL_ADC_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_REG_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 series. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or + from external peripheral (timer event, external interrupt line). + This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE + @note On this STM32 series, setting trigger source to external trigger also + set trigger polarity to rising edge(default setting for compatibility + with some ADC on other STM32 series having this setting set by HW + default value). + In case of need to modify trigger edge, use function + @ref LL_ADC_REG_SetTriggerEdge(). + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetTriggerSource(). */ + + uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetSequencerLength(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided + and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE + @note This parameter has an effect only if group regular sequencer is + enabled (scan length of 2 ranks or more). + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetSequencerDiscont(). */ + + uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC + conversions are performed in single mode (one conversion per trigger) or in + continuous mode (after the first trigger, following conversions launched + successively automatically). + This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE + Note: It is not possible to enable both ADC group regular continuous mode + and discontinuous mode. + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetContinuousMode(). */ + + uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer + by DMA, and DMA requests mode. + This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetDMATransfer(). */ + + uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: + data preserved or overwritten. + This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetOverrun(). */ + +} LL_ADC_REG_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group injected. + * @note These parameters have an impact on ADC scope: ADC group injected. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "INJ"). + * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 series. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) + or from external peripheral (timer event, external interrupt line). + This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE + @note On this STM32 series, setting trigger source to external trigger also + set trigger polarity to rising edge (default setting for + compatibility with some ADC on other STM32 series having this + setting set by HW default value). + In case of need to modify trigger edge, use function + @ref LL_ADC_INJ_SetTriggerEdge(). + This feature can be modified afterwards using unitary function + @ref LL_ADC_INJ_SetTriggerSource(). */ + + uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. + This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH + This feature can be modified afterwards using unitary function + @ref LL_ADC_INJ_SetSequencerLength(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided + and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE + @note This parameter has an effect only if group injected sequencer is + enabled (scan length of 2 ranks or more). + This feature can be modified afterwards using unitary function + @ref LL_ADC_INJ_SetSequencerDiscont(). */ + + uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group + regular. + This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO + Note: This parameter must be set to set to independent trigger if injected + trigger source is set to an external trigger. + This feature can be modified afterwards using unitary function + @ref LL_ADC_INJ_SetTrigAuto(). */ + +} LL_ADC_INJ_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_LL_EC_FLAG ADC flags + * @brief Flags defines which can be used with LL_ADC_ReadReg function + * @{ + */ +#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */ +#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary + conversion */ +#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence + conversions */ +#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ +#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ +#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary + conversion */ +#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence + conversions */ +#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue + overflow */ +#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ +#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */ +#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */ +#if defined(ADC_MULTIMODE_SUPPORT) +#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */ +#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */ +#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of + unitary conversion */ +#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of + unitary conversion */ +#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of + sequence conversions */ +#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of + sequence conversions */ +#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular + overrun */ +#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular + overrun */ +#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of + sampling phase */ +#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of + sampling phase */ +#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of + unitary conversion */ +#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of + unitary conversion */ +#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of + sequence conversions */ +#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of + sequence conversions */ +#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected + contexts queue overflow */ +#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected + contexts queue overflow */ +#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 + of the ADC master */ +#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 + of the ADC slave */ +#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 + of the ADC master */ +#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 + of the ADC slave */ +#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 + of the ADC master */ +#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 + of the ADC slave */ +#endif /* ADC_MULTIMODE_SUPPORT */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) + * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions + * @{ + */ +#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */ +#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary + conversion */ +#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence + conversions */ +#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */ +#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling + phase */ +#define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary + conversion */ +#define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence + conversions */ +#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue + overflow */ +#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */ +#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */ +#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose + * @{ + */ +/* List of ADC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ +#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register + (corresponding to register DR) to be used with ADC configured in independent + mode. Without DMA transfer, register accessed by LL function + @ref LL_ADC_REG_ReadConversionData32() and other + functions @ref LL_ADC_REG_ReadConversionDatax() */ +#if defined(ADC_MULTIMODE_SUPPORT) +#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register + (corresponding to register CDR) to be used with ADC configured in multimode + (available on STM32 devices with several ADC instances). + Without DMA transfer, register accessed by LL function + @ref LL_ADC_REG_ReadMultiConversionData32() */ +#endif /* ADC_MULTIMODE_SUPPORT */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source + * @{ + */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from + AHB clock without prescaler */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from + AHB clock with prescaler division by 2 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from + AHB clock with prescaler division by 4 */ +#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without + prescaler */ +#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 2 */ +#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with + prescaler division by 4 */ +#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 6 */ +#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with + prescaler division by 8 */ +#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 10 */ +#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with + prescaler division by 12 */ +#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \ + | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 16 */ +#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with + prescaler division by 32 */ +#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 64 */ +#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with + prescaler division by 128 */ +#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \ + | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 256 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels + * @{ + */ +/* Note: Other measurement paths to internal channels may be available */ +/* (connections to other peripherals). */ +/* If they are not listed below, they do not require any specific */ +/* path enable. In this case, Access to measurement path is done */ +/* only by selecting the corresponding ADC internal channel. */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ +#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ +#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel + temperature sensor */ +#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_PATH_INTERNAL ADC instance - Measurement path to internal channels + * @{ + */ +/* Note: Other measurement paths to internal channels may be available */ +/* (connections to other peripherals). */ +/* If they are not listed below, they do not require any specific */ +/* path enable. In this case, Access to measurement path is done */ +/* only by selecting the corresponding ADC internal channel. */ +#define LL_ADC_PATH_INTERNAL_VDDCORE (ADC_OR_OP0) /*!< ADC measurement path to internal channel VddCore */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution + * @{ + */ +#define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */ +#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */ +#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */ +#define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment + * @{ + */ +#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned + (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned + (alignment on data register MSB bit 15)*/ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode + * @{ + */ +#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ +#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power + mode, ADC conversions are performed only when necessary + (when previous ADC conversion data is read). + See description with function @ref LL_ADC_SetLowPowerMode(). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset instance + * @{ + */ +#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset instance 1: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + mapped on ADC group regular or injected) */ +#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset instance 2: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + mapped on ADC group regular or injected) */ +#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset instance 3: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + mapped on ADC group regular or injected) */ +#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset instance 4: ADC channel and offset level + to which the offset programmed will be applied (independently of channel + mapped on ADC group regular or injected) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state + * @{ + */ +#define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled + (setting offset instance wise) */ +#define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled + (setting offset instance wise) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign + * @{ + */ +#define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative */ +#define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode + * @{ + */ +#define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC + selected offset instance 1, 2, 3 or 4) */ +#define LL_ADC_OFFSET_SATURATION_ENABLE (ADC_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC + selected offset instance 1, 2, 3 or 4) */ +/** + * @} + */ +/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups + * @{ + */ +#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ +#define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 + devices)*/ +#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP \ + | ADC_CHANNEL_0_BITFIELD) /*!< ADC channel ADCx_IN0 */ +#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP \ + | ADC_CHANNEL_1_BITFIELD) /*!< ADC channel ADCx_IN1 */ +#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP \ + | ADC_CHANNEL_2_BITFIELD) /*!< ADC channel ADCx_IN2 */ +#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP \ + | ADC_CHANNEL_3_BITFIELD) /*!< ADC channel ADCx_IN3 */ +#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP \ + | ADC_CHANNEL_4_BITFIELD) /*!< ADC channel ADCx_IN4 */ +#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP \ + | ADC_CHANNEL_5_BITFIELD) /*!< ADC channel ADCx_IN5 */ +#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP \ + | ADC_CHANNEL_6_BITFIELD) /*!< ADC channel ADCx_IN6 */ +#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP \ + | ADC_CHANNEL_7_BITFIELD) /*!< ADC channel ADCx_IN7 */ +#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP \ + | ADC_CHANNEL_8_BITFIELD) /*!< ADC channel ADCx_IN8 */ +#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP \ + | ADC_CHANNEL_9_BITFIELD) /*!< ADC channel ADCx_IN9 */ +#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP \ + | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */ +#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP \ + | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */ +#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP \ + | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */ +#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP \ + | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */ +#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP \ + | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */ +#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP \ + | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */ +#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP \ + | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */ +#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP \ + | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */ +#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP \ + | ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to VrefInt: Internal voltage reference, channel specific to ADC1.*/ +#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to internal temperature sensor, channel specific to ADC1.*/ +#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel + connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 + to have channel voltage always below Vdda, channel specific to ADC2. */ +#define LL_ADC_CHANNEL_VDDCORE (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel + connected to Vcore, channel specific to ADC2. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source + * @{ + */ +#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular + conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM1 channel 1 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM1 channel 2 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM1 channel 3 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 \ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM2 channel 2 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 \ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM4 channel 4 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 \ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: external interrupt line 11 + event. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM12_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 \ + | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM12 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM9_TRGO (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 \ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 \ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 \ + | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 \ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 \ + | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 \ + | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 \ + | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 \ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM3 channel 4 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 \ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: LPTIM1 channel 1 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_REG_TRIG_EXT_LPTIM2_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 \ + | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: LPTIM2 channel 1 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_REG_TRIG_EXT_LPTIM3_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 \ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: LPTIM3 channel 1 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge + * @{ + */ +#define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion + trigger polarity set to rising edge */ +#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1) /*!< ADC group regular conversion + trigger polarity set to falling edge */ +#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion + trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode + * @{ + */ +#define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration + is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */ +#define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts + immediately after end of conversion, and stops upon trigger event. + Note: First conversion is using minimal sampling time + (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */ +#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is + controlled by trigger events: trigger rising edge for start sampling, + trigger falling edge for stop sampling and start conversion */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode + * @{ + */ +#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode: + one conversion per trigger */ +#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions performed in continuous mode: + after the first trigger, following conversions launched successively + automatically */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data + * @{ + */ +#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA + in limited mode (one shot mode): DMA transfer requests are stopped when + number of DMA data transfers (number of ADC conversions) is reached. + This ADC mode is intended to be used with DMA mode non-circular. */ +#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are + transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, + whatever number of DMA data transferred (number of ADC conversions). + This ADC mode is intended to be used with DMA mode circular. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_MDF_TRANSFER ADC group regular - ADC conversion data transfer to MDF peripheral + * @{ + */ +#define LL_ADC_REG_MDF_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions data are not transferred to MDF + peripheral */ +#define LL_ADC_REG_MDF_TRANSFER_ENABLE (ADC_CFGR_ADFCFG) /*!< ADC conversion data are transferred to MDF + peripheral. This configuration cannot be used if DMA transfer is enabled. */ +/** + * @} + */ + +#if defined(ADC_SMPR1_SMPPLUS) +/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration + * @{ + */ +#define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */ +#define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock + cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped + with selection sampling time 2.5 ADC clock cycles, whatever channels mapped + on ADC groups regular or injected). */ +/** + * @} + */ +#endif /* ADC_SMPR1_SMPPLUS */ + +/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data + * @{ + */ +#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: + data preserved */ +#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: + data overwritten */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length + * @{ + */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable + (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 2 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_SQR1_L_1) /*!< ADC group regular sequencer enable + with 3 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 4 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_SQR1_L_2) /*!< ADC group regular sequencer enable + with 5 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 6 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable + with 7 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1 \ + | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 8 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3) /*!< ADC group regular sequencer enable + with 9 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 10 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable + with 11 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 \ + | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 12 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2) /*!< ADC group regular sequencer enable + with 13 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \ + | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 14 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \ + | ADC_SQR1_L_1) /*!< ADC group regular sequencerenable + with 15 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \ + | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable + with 16 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer + discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every rank */ +#define LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enabled with sequence interruption every 2 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every 3 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_4RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 \ + | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every 4 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every 5 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 \ + | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every 6 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \ + | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every 7 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \ + | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every 8 ranks */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks + * @{ + */ +#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 1 */ +#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 2 */ +#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 3 */ +#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 4 */ +#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 5 */ +#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 6 */ +#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 7 */ +#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 8 */ +#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 9 */ +#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 10 */ +#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 11 */ +#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 12 */ +#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 13 */ +#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 14 */ +#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 15 */ +#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group + regular sequencer rank 16 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source + * @{ + */ +#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected + conversion trigger internal: SW start. */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected + conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected + conversion trigger from external peripheral: TIM1 channel 4 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected + conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \ + | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected + conversion trigger from external peripheral: TIM2 channel 1 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected + conversion trigger from external peripheral: TIM3 channel 4 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 \ + | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected + conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \ + | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected + conversion trigger from external peripheral: external interrupt line 15. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM9_CH1 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \ + | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)/*!< ADC group injected + conversion trigger from external peripheral: TIM9 channel 1 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected + conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM12_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 \ + | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected + conversion trigger from external peripheral: TIM12 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM9_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 \ + | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected + conversion trigger from external peripheral: TIM9 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 \ + | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)/*!< ADC group injected + conversion trigger from external peripheral: TIM3 channel 3 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \ + | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected + conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \ + | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)/*!< ADC group injected + conversion trigger from external peripheral: TIM3 channel 1 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \ + | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)/*!< ADC group injected + conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \ + | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \ + | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected + conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge + set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 \ + | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected + conversion trigger from external peripheral: LPTIM1 channel 2 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 \ + | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)/*!< ADC group injected + conversion trigger from external peripheral: LPTIM2 channel 2 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 \ + | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected + conversion trigger from external peripheral: LPTIM3 channel 1 event (capture + compare: input capture or output capture). Trigger edge set to rising edge + (default setting). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge + * @{ + */ +#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion + trigger polarity set to rising edge */ +#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion + trigger polarity set to falling edge */ +#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion + trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode + * @{ + */ +#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. + Setting mandatory if ADC group injected injected trigger source is set to + an external trigger. */ +#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group + regular. Setting compliant only with group injected trigger source set to + SW start, without any further action on ADC group injected conversion start + or stop: in this case, ADC group injected is controlled only from ADC group + regular. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode + * @{ + */ +#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled + and can contain up to 2 contexts. When all contexts have been processed, + the queue maintains the last context active perpetually. */ +#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled + and can contain up to 2 contexts. When all contexts have been processed, + the queue is empty and injected group triggers are disabled. */ +#define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: + only 1 sequence can be configured and is active perpetually. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length + * @{ + */ +#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable + (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable + with 2 ranks in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable + with 3 ranks in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable + with 4 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode + disable */ +#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode + enable with sequence interruption every rank */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks + * @{ + */ +#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \ + | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 1 */ +#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \ + | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 2 */ +#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \ + | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 3 */ +#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \ + | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 4 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @{ + */ +#define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_6CYCLES_5 (ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR2_SMP10_1) /*!< Sampling time 12.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_24CYCLES_5 (ADC_SMPR2_SMP10_1 \ + | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2) /*!< Sampling time 47.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 \ + | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 \ + | ADC_SMPR2_SMP10_1) /*!< Sampling time 247.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 \ + | ADC_SMPR2_SMP10_1 \ + | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending + * @{ + */ +#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending + set to single ended (literal also used to set calibration mode) */ +#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending + set to differential (literal also used to set calibration mode) */ +#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending + set to both single ended and differential (literal used only to set + calibration factors) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number + * @{ + */ +#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \ + | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ +#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ +#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels + * @{ + */ +#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring + disabled */ +#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring + of all channels, converted by group regular only */ +#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_CFGR_JAWD1EN) /*!< ADC analog watchdog monitoring + of all channels, converted by group injected only */ +#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring + of all channels, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN0, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN0, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN0, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN1, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN1, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN1, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN2, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN2, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN2, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN3, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN3, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN3, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN4, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN4, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN4, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN5, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN5, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN5, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN6, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN6, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN6, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN7, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN7, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN7, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN8, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN8, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN8, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN9, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN9, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN9, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN10, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN10, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)\ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN10, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN11, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN11, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN11, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN12, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN12, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN12, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN13, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN13, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN13, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN14, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN14, converted by group only */ +#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN14, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + monitoring of ADC channel ADCx_IN15, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN15, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN15, converted by either group + regular or injected */ +#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN16, + converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN16, + converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN16, + converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN17, + converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN17, + converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN17, + by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN18, + converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN18, + converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN18, + converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to VrefInt: Internal + voltage reference, converted by group regular only */ +#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to VrefInt: Internal + voltage reference, converted by group injected only */ +#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to VrefInt: Internal + voltage reference, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to internal temperature sensor, + converted by group regular only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to internal temperature sensor, + converted by group injected only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to internal temperature sensor, + converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to Vbat/4: Vbat + voltage through a divider ladder of factor 1/4 to have channel voltage + always below Vdda, converted by group regular only */ +#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to Vbat/4: Vbat + voltage through a divider ladder of factor 1/4 to have channel voltage + always below Vdda, converted by group injected only */ +#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to Vbat/4: Vbat + voltage through a divider ladder of factor 1/4 to have channel voltage + always below Vdda */ +#define LL_ADC_AWD_CH_VDDCORE_REG ((LL_ADC_CHANNEL_VDDCORE & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to VddCore, + converted by group regular only */ +#define LL_ADC_AWD_CH_VDDCORE_INJ ((LL_ADC_CHANNEL_VDDCORE & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + monitoring of ADC internal channel connected to VddCore, + converted by group injected only */ +#define LL_ADC_AWD_CH_VDDCORE_REG_INJ ((LL_ADC_CHANNEL_VDDCORE & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ + | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to VddCore, + converted by either group regular or injected */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds + * @{ + */ +#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1) /*!< ADC analog watchdog threshold high */ +#define LL_ADC_AWD_THRESHOLD_LOW (ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */ +#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 \ + | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low + concatenated into the same data */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config + * @{ + */ +#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, + one out-of-window sample is needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_2SAMPLES (ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 2 + out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_3SAMPLES (ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 3 + consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_4SAMPLES (ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 4 + consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_TR1_AWDFILT_2) /*!< ADC analog watchdog 5 + consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 6 + consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 7 + consecutives out-of-window samples are needed to raise flag or interrupt */ +#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \ + | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 8 + consecutives out-of-window samples are needed to raise flag or interrupt */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope + * @{ + */ +#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ +#define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of + ADC group regular. If group injected interrupts group regular: + when ADC group injected is triggered, the oversampling on ADC group regular + is temporary stopped and continued afterwards. */ +#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of + ADC group regular. If group injected interrupts group regular: + when ADC group injected is triggered, the oversampling on ADC group regular + is resumed from start (oversampler buffer reset). */ +#define LL_ADC_OVS_GRP_INJECTED (ADC_CFGR2_JOVSE) /*!< ADC oversampling on conversions of + ADC group injected. */ +#define LL_ADC_OVS_GRP_INJ_REG_RESUMED (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of + both ADC groups regular and injected. If group injected interrupting group + regular: when ADC group injected is triggered, the oversampling on ADC group + regular is resumed from start (oversampler buffer reset). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode + * @{ + */ +#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode +(all conversions of oversampling ratio are done from 1 trigger) */ +#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous + mode (each conversion of oversampling ratio needs a trigger) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio + * @{ + */ +#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \ + | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift + * @{ + */ +#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift + (sum of the ADC conversions data is not divided to result as oversampling + conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1 + (sum of the ADC conversions data (after OVS ratio) is divided by 2 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2 + (sum of the ADC conversions data (after OVS ratio) is divided by 4 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3 + (sum of the ADC conversions data (after OVS ratio) is divided by 8 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4 + (sum of the ADC conversions data (after OVS ratio) is divided by 16 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5 + (sum of the ADC conversions data (after OVS ratio) is divided by 32 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6 + (sum of the ADC conversions data (after OVS ratio) is divided by 64 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \ + | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7 + (sum of the ADC conversions data (after OVS ratio) is divided by 128 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8 + (sum of the ADC conversions data (after OVS ratio) is divided by 256 + to result as oversampling conversion data) */ +/** + * @} + */ + +#if defined(ADC_MULTIMODE_SUPPORT) +/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode + * @{ + */ +#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC + independent mode) */ +#define LL_ADC_MULTI_DUAL_REG_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: group regular + simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_INTERL (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 \ + | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group + regular interleaved */ +#define LL_ADC_MULTI_DUAL_INJ_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected + simultaneous */ +#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected + alternate trigger. Works only with external triggers (not SW start) */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM (ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group + regular simultaneous + group injected simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT (ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: Combined group + regular simultaneous + group injected alternate trigger */ +#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group + regular interleaved + group injected simultaneous */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer + * @{ + */ +#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular + conversions are transferred by DMA: each ADC uses its own DMA channel, + with its individual DMA transfer settings */ +#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (ADC_CCR_MDMA_1) /*!< ADC multimode group regular + conversions are transferred by DMA, one DMA channel for both ADC(DMA of + ADC master), in limited mode (one shot mode): DMA transfer requests + are stopped when number of DMA data transfers (number of ADC conversions) + is reached. This ADC mode is intended to be used with DMA mode + non-circular. Setting for ADC resolution of 12 and 10 bits */ +#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B (ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular + conversions are transferred by DMA, one DMA channel for both ADC(DMA of + ADC master), in limited mode (one shot mode): DMA transfer requests + are stopped when number of DMA data transfers (number of ADC conversions) + is reached. This ADC mode is intended to be used with DMA mode + non-circular. Setting for ADC resolution of 8 and 6 bits */ +#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1) /*!< ADC multimode group regular + conversions are transferred by DMA, one DMA channel for both ADC(DMA of + ADC master), in unlimited mode: DMA transfer requests are unlimited, + whatever number of DMA data transferred (number of ADC conversions). + This ADC mode is intended to be used with DMA mode circular. + Setting for ADC resolution of 12 and 10 bits */ +#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 \ + | ADC_CCR_MDMA_0) /*!< ADC multimode group regular + conversions are transferred by DMA, one DMA channel for both ADC (DMA of + ADC master), in unlimited mode: DMA transfer requests are unlimited, + whatever number of DMA data transferred (number of ADC conversions). + This ADC mode is intended to be used with DMA mode circular. + Setting for ADC resolution of 8 and 6 bits */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases + * @{ + */ +#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two + sampling phases: 1 ADC clock cycle */ +#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES (ADC_CCR_DELAY_0) /*!< ADC multimode delay between two + sampling phases: 2 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES (ADC_CCR_DELAY_1) /*!< ADC multimode delay between two + sampling phases: 3 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two + sampling phases: 4 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (ADC_CCR_DELAY_2) /*!< ADC multimode delay between two + sampling phases: 5 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two + sampling phases: 6 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two + sampling phases: 7 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \ + | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two + sampling phases: 8 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3) /*!< ADC multimode delay between two + sampling phases: 9 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two + sampling phases: 10 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two + sampling phases: 11 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 \ + | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two + sampling phases: 12 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave + * @{ + */ +#define LL_ADC_MULTI_MASTER (ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC + instances: ADC master */ +#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV) /*!< In multimode, selection among several ADC + instances: ADC slave */ +#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV \ + | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC + instances: both ADC master and ADC slave */ +/** + * @} + */ + +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro + * @{ + */ +#define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro + @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on + calibration parameters. This value is coded on 16 bits + (to fit on signed word or double word) and corresponds + to an inconsistent temperature value. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays + * @note Only ADC peripheral HW delays are defined in ADC LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ +/* not timeout values. */ +/* Timeout values for ADC operations are dependent to device clock */ +/* configuration (system clock versus ADC clock), */ +/* and therefore must be defined in user application. */ +/* Indications for estimation of ADC timeout delays, for this */ +/* STM32 series: */ +/* - ADC calibration time: maximum delay is 112/fADC. */ +/* (refer to device datasheet, parameter "tCAL") */ +/* - ADC enable time: maximum delay is 1 conversion cycle. */ +/* (refer to device datasheet, parameter "tSTAB") */ +/* - ADC disable time: maximum delay should be a few ADC clock cycles */ +/* - ADC stop conversion time: maximum delay should be a few ADC clock */ +/* cycles */ +/* - ADC conversion time: duration depending on ADC clock and ADC */ +/* configuration. */ +/* (refer to device reference manual, section "Timing") */ + +/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */ +/* Delay set to maximum value (refer to device datasheet, */ +/* parameter "tADCVREG_STUP"). */ +/* Unit: us */ +#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage + regulator start-up time) */ + +/* Delay for internal voltage reference stabilization time. */ +/* Delay set to maximum value (refer to device datasheet, */ +/* parameter "tstart_vrefint"). */ +/* Unit: us */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization + time */ + +/* Delay for temperature sensor stabilization time. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ +#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization + time (starting from ADC enable, refer to + @ref LL_ADC_Enable()) */ + +/* Delay required between ADC end of calibration and ADC enable. */ +/* Note: On this STM32 series, a minimum number of ADC clock cycles */ +/* are required between ADC end of calibration and ADC enable. */ +/* Wait time can be computed in user application by waiting for the */ +/* equivalent number of CPU cycles, by taking into account */ +/* ratio of CPU clock versus ADC clock prescalers. */ +/* Unit: ADC clock cycles. */ +#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration + and ADC enable */ + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros + * @{ + */ + +/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals LL_ADC_CHANNEL_x. + * @note Example: + * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (3) + * @arg @ref LL_ADC_CHANNEL_1 (3) + * @arg @ref LL_ADC_CHANNEL_2 (3) + * @arg @ref LL_ADC_CHANNEL_3 (3) + * @arg @ref LL_ADC_CHANNEL_4 (3) + * @arg @ref LL_ADC_CHANNEL_5 (3) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * @retval Value between Min_Data=0 and Max_Data=18 + */ +#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \ + ( \ + ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ + ) \ + : \ + ( \ + (uint32_t)POSITION_VAL((__CHANNEL__)) \ + ) \ + ) + +/** + * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "LL_ADC_CHANNEL_4". + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (2) + * @arg @ref LL_ADC_CHANNEL_1 (2) + * @arg @ref LL_ADC_CHANNEL_2 (2) + * @arg @ref LL_ADC_CHANNEL_3 (2) + * @arg @ref LL_ADC_CHANNEL_4 (2) + * @arg @ref LL_ADC_CHANNEL_5 (2) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3) + * @arg @ref LL_ADC_CHANNEL_VBAT (1)(3) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (2) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * (3) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) <= 9UL) ? \ + ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ + (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ + : \ + ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ + (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ + ) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (3) + * @arg @ref LL_ADC_CHANNEL_1 (3) + * @arg @ref LL_ADC_CHANNEL_2 (3) + * @arg @ref LL_ADC_CHANNEL_3 (3) + * @arg @ref LL_ADC_CHANNEL_4 (3) + * @arg @ref LL_ADC_CHANNEL_5 (3) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel + connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (3) + * @arg @ref LL_ADC_CHANNEL_1 (3) + * @arg @ref LL_ADC_CHANNEL_2 (3) + * @arg @ref LL_ADC_CHANNEL_3 (3) + * @arg @ref LL_ADC_CHANNEL_4 (3) + * @arg @ref LL_ADC_CHANNEL_5 (3) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + */ +#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1. + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + ((((__ADC_INSTANCE__) == ADC1) \ + &&(((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)) \ + ) \ + || \ + (((__ADC_INSTANCE__) == ADC2) \ + &&(((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VDDCORE)) \ + ) \ + ) + +/** + * @brief Helper macro to define ADC analog watchdog parameter: + * define a single channel to monitor with analog watchdog + * from sequencer channel and groups definition. + * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). + * Example: + * LL_ADC_SetAnalogWDMonitChannels( + * ADC1, LL_ADC_AWD1, + * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (2) + * @arg @ref LL_ADC_CHANNEL_1 (2) + * @arg @ref LL_ADC_CHANNEL_2 (2) + * @arg @ref LL_ADC_CHANNEL_3 (2) + * @arg @ref LL_ADC_CHANNEL_4 (2) + * @arg @ref LL_ADC_CHANNEL_5 (2) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3) + * @arg @ref LL_ADC_CHANNEL_VBAT (1)(3) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (2) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * (3) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @param __GROUP__ This parameter can be one of the following values: + * @arg @ref LL_ADC_GROUP_REGULAR + * @arg @ref LL_ADC_GROUP_INJECTED + * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1) + * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) + * + * (0) On STM32H7RS, parameter available only on analog watchdog number: AWD1.\n + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + */ +#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ + (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ + : \ + ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \ + : \ + (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ + ) + +/** + * @brief Helper macro to set the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds() + * or @ref LL_ADC_SetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to set the value of + * analog watchdog threshold high (on 8 bits): + * LL_ADC_SetAnalogWDThresholds + * (< ADCx param >, + * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ + ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) + +/** + * @brief Helper macro to get the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to get the value of + * analog watchdog threshold high (on 8 bits): + * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION + * (LL_ADC_RESOLUTION_8B, + * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ + ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) + +/** + * @brief Helper macro to get the ADC analog watchdog threshold high + * or low from raw value containing both thresholds concatenated. + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, to get analog watchdog threshold high from the register raw value: + * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, ); + * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ + (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \ + & LL_ADC_AWD_THRESHOLD_LOW) + +/** + * @brief Helper macro to set the ADC calibration value with both single ended + * and differential modes calibration factors concatenated. + * @note To be used with function @ref LL_ADC_SetCalibrationFactor(). + * Example, to set calibration factors single ended to 0x55 + * and differential ended to 0x2A: + * LL_ADC_SetCalibrationFactor( + * ADC1, + * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A)) + * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F + * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \ + (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__)) + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Helper macro to get the ADC multimode conversion data of ADC master + * or ADC slave from raw value with both ADC conversion data concatenated. + * @note This macro is intended to be used when multimode transfer by DMA + * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). + * In this case the transferred data need to processed with this macro + * to separate the conversion data of ADC master and ADC slave. + * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ + (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) +#endif /* ADC_MULTIMODE_SUPPORT */ + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Helper macro to select, from a ADC instance, to which ADC instance + * it has a dependence in multimode (ADC master of the corresponding + * ADC common instance). + * @note In case of device with multimode available and a mix of + * ADC instances compliant and not compliant with multimode feature, + * ADC instances not compliant with multimode feature are + * considered as master instances (do not depend to + * any other ADC instance). + * @param __ADCx__ ADC instance + * @retval __ADCx__ ADC instance master of the corresponding ADC common instance + */ +#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \ + ( ( ((__ADCx__) == ADC2) \ + )? \ + (ADC1) \ + : \ + (__ADCx__) \ + ) +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON) +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#if defined(ADC2) +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2)) +#else +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) (LL_ADC_IsEnabled(ADC1)) +#endif /* ADC2 */ + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data) + */ +#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param __DATA__ ADC conversion data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data to the requested resolution + */ +#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ + __ADC_RESOLUTION_CURRENT__,\ + __ADC_RESOLUTION_TARGET__) \ +(((__DATA__) \ + << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \ + >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \ +) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ +((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ +) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value) in + * differential ended mode. + * @note ADC data from ADC data register is unsigned and centered around + * middle code in. Converted voltage can be positive or negative + * depending on differential input voltages. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__)\ +((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__)\ + / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))\ + - (int32_t)(__VREFANALOG_VOLTAGE__)) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @note On this STM32 series, calibration data of internal voltage reference + * VrefInt corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * internal voltage reference VrefInt. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) + * of internal voltage reference VrefInt (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Analog reference voltage (unit: mV) + */ +#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ + / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ +) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor calibration values + * stored in system memory for each device during production. + * @note Calculation formula: + * Temperature = ((TS_ADC_DATA - TS_CAL1) + * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) + * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * Avg_Slope = (TS_CAL2 - TS_CAL1) + * / (TS_CAL2_TEMP - TS_CAL1_TEMP) + * TS_CAL1 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL1 (calibrated in factory) + * TS_CAL2 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL2 (calibrated in factory) + * Caution: Calculation relevancy under reserve that calibration + * parameters are correct (address and data). + * To calculate temperature using temperature sensor + * datasheet typical values (generic values less, therefore + * less accurate than calibrated values), + * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note On this STM32 series, calibration data of temperature sensor + * corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * temperature sensor. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal + * temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature + * sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value) + */ +#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__)\ +((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \ + (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ + * (__VREFANALOG_VOLTAGE__)) \ + / TEMPSENSOR_CAL_VREFANALOG) \ + - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ + ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ + ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ + ) + TEMPSENSOR_CAL1_TEMP \ + ) \ + : \ + ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \ +) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * If temperature sensor calibration values are available on + * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), + * temperature calculation will be more accurate using + * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note ADC measurement data must correspond to a resolution of 12 bits + * (full scale digital value 4095). If not the case, the data must be + * preliminarily rescaled to an equivalent resolution of 12 bits. + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value + * (unit: uV/DegCelsius). + * On STM32H7RS, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value + * (at temperature and Vref+ defined in parameters below) (unit: mV). + * On this STM32 series, refer to datasheet parameter "V30" (corresponding + * to TS_CAL1). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage + * (see parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ + * 1000UL) \ + - \ + (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ + * 1000UL) \ + ) \ + ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ +) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management + * @{ + */ +/* Note: LL ADC functions to set DMA transfer are located into sections of */ +/* configuration of ADC instance, groups and multimode (if available): */ +/* @ref LL_ADC_REG_SetDMATransfer(), ... */ + +/** + * @brief Function to help to configure DMA transfer from ADC: retrieve the + * ADC register address from ADC instance and a list of ADC registers + * intended to be used (most commonly) with DMA transfer. + * @note These ADC registers are data registers: + * when ADC conversion data is available in ADC data registers, + * ADC generates a DMA transfer request. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), + * (uint32_t)&< array or variable >, + * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + * @note For devices with several ADC: in multimode, some devices + * use a different data register outside of ADC instance scope + * (common data register). This macro manages this register difference, + * only ADC instance has to be set as parameter. + * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n + * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n + * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr + * @param ADCx ADC instance + * @param Register This parameter can be one of the following values: + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) + * + * (1) Available on devices with several ADC instances. + * @retval ADC register address + */ +#if defined(ADC_MULTIMODE_SUPPORT) +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) +{ + uint32_t data_reg_addr; + + if (Register == LL_ADC_DMA_REG_REGULAR_DATA) + { + /* Retrieve address of register DR */ + data_reg_addr = (uint32_t) &(ADCx->DR); + } + else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ + { + /* Retrieve address of register CDR */ + data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); + } + + return data_reg_addr; +} +#else +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(Register); + + /* Retrieve address of register DR */ + return (uint32_t) &(ADCx->DR); +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several + * ADC instances + * @{ + */ + +/** + * @brief Set parameter common to several ADC: Clock source and prescaler. + * @note On this STM32 series, if ADC group injected is used, some + * clock ratio constraints between ADC clock and AHB clock + * must be respected. + * Refer to reference manual. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n + * CCR PRESC LL_ADC_SetCommonClock + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param CommonClock This parameter can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); +} + +/** + * @brief Get parameter common to several ADC: Clock source and prescaler. + * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n + * CCR PRESC LL_ADC_GetCommonClock + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC)); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Configure all paths (overwrite current configuration). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * The values not selected are removed from configuration. + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US, + * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n + * CCR TSEN LL_ADC_SetCommonPathInternalCh\n + * CCR VBATEN LL_ADC_SetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Add paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US, + * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n + * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n + * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + SET_BIT(ADCxy_COMMON->CCR, PathInternal); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Remove paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n + * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n + * CCR VBATEN LL_ADC_SetCommonPathInternalChRem + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal); +} + +/** + * @brief Get parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n + * CCR TSEN LL_ADC_GetCommonPathInternalCh\n + * CCR VBATEN LL_ADC_GetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Set parameter on ADC instance scope: measurement path to + * internal channels (Vcore, Vcpu...). + * Configure all paths (overwrite current configuration). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VDDCORE | + * LL_ADC_PATH_INTERNAL_...) + * The values not selected are removed from configuration. + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay may be required required for analog stabilization. + * Refer to device datasheet. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @rmtoll OR OP0 LL_ADC_SetPathInternalCh + * @param ADCx ADC instance + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetPathInternalCh(ADC_TypeDef *ADCx, uint32_t PathInternal) +{ + MODIFY_REG(ADCx->OR, ADC_OR_OP0, PathInternal); +} + +/** + * @brief Set parameter on ADC instance scope: measurement path to + * internal channels (Vcore, Vcpu...). + * Add paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VDDCORE | + * LL_ADC_PATH_INTERNAL_...) + * The values not selected are removed from configuration. + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay may be required required for analog stabilization. + * Refer to device datasheet. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @rmtoll OR OP0 LL_ADC_SetPathInternalChAdd + * @param ADCx ADC instance + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetPathInternalChAdd(ADC_TypeDef *ADCx, uint32_t PathInternal) +{ + SET_BIT(ADCx->OR, PathInternal); +} + +/** + * @brief Set parameter on ADC instance scope: measurement path to + * internal channels (Vcore, Vcpu...). + * Remove paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VDDCORE | + * LL_ADC_PATH_INTERNAL_...) + * The values not selected are removed from configuration. + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay may be required required for analog stabilization. + * Refer to device datasheet. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @rmtoll OR OP0 LL_ADC_SetPathInternalChRem + * @param ADCx ADC instance + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetPathInternalChRem(ADC_TypeDef *ADCx, uint32_t PathInternal) +{ + CLEAR_BIT(ADCx->OR, PathInternal); +} + +/** + * @brief Get parameter on ADC instance scope: measurement path to + * internal channels (Vcore, Vcpu...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VDDCORE | + * LL_ADC_PATH_INTERNAL_...) + * @rmtoll OR OP0 LL_ADC_GetPathInternalCh + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE + */ +__STATIC_INLINE uint32_t LL_ADC_GetPathInternalCh(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->OR, ADC_OR_OP0)); +} + +/** + * @brief Set ADC calibration factor in the mode single-ended + * or differential (for devices with differential mode available). + * @note This function is intended to set calibration parameters + * without having to perform a new calibration using + * @ref LL_ADC_StartCalibration(). + * @note For devices with differential mode available: + * Calibration of offset is specific to each of + * single-ended and differential modes + * (calibration factor must be specified for each of these + * differential modes, if used afterwards and if the application + * requires their calibration). + * @note In case of setting calibration factors of both modes single ended + * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED): + * both calibration factors must be concatenated. + * To perform this processing, use helper macro + * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled, without calibration on going, without conversion + * on going on group regular. + * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n + * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor + * @param ADCx ADC instance + * @param SingleDiff This parameter can be one of the following values: + * @arg @ref LL_ADC_SINGLE_ENDED + * @arg @ref LL_ADC_DIFFERENTIAL_ENDED + * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED + * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor) +{ + MODIFY_REG(ADCx->CALFACT, + SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, + CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) + >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) + & ~(SingleDiff & ADC_CALFACT_CALFACT_S))); +} + +/** + * @brief Get ADC calibration factor in the mode single-ended + * or differential (for devices with differential mode available). + * @note Calibration factors are set by hardware after performing + * a calibration run using function @ref LL_ADC_StartCalibration(). + * @note For devices with differential mode available: + * Calibration of offset is specific to each of + * single-ended and differential modes + * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n + * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor + * @param ADCx ADC instance + * @param SingleDiff This parameter can be one of the following values: + * @arg @ref LL_ADC_SINGLE_ENDED + * @arg @ref LL_ADC_DIFFERENTIAL_ENDED + * @retval Value between Min_Data=0x00 and Max_Data=0x7F + */ +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff) +{ + /* Retrieve bits with position in register depending on parameter */ + /* "SingleDiff". */ + /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ + /* containing other bits reserved for other purpose. */ + return (uint32_t)(READ_BIT(ADCx->CALFACT, + (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) + >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> + ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); +} + +/** + * @brief Set ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll CFGR RES LL_ADC_SetResolution + * @param ADCx ADC instance + * @param Resolution This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution); +} + +/** + * @brief Get ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CFGR RES LL_ADC_GetResolution + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + */ +__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)); +} + +/** + * @brief Set ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment + * @param ADCx ADC instance + * @param DataAlignment This parameter can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment); +} + +/** + * @brief Get ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + */ +__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN)); +} + +/** + * @brief Set ADC low power mode. + * @note Description of ADC low power modes: + * - ADC low power mode "auto wait": Dynamic low power mode, + * ADC conversions occurrences are limited to the minimum necessary + * in order to reduce power consumption. + * New ADC conversion starts only when the previous + * unitary conversion data (for ADC group regular) + * or previous sequence conversions data (for ADC group injected) + * has been retrieved by user software. + * In the meantime, ADC remains idle: does not performs any + * other conversion. + * This mode allows to automatically adapt the ADC conversions + * triggers to the speed of the software that reads the data. + * Moreover, this avoids risk of overrun for low frequency + * applications. + * How to use this low power mode: + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). + * - Do use with polling: 1. Start conversion, + * 2. Later on, when conversion data is needed: poll for end of + * conversion to ensure that conversion is completed and + * retrieve ADC conversion data. This will trig another + * ADC conversion start. + * @note With ADC low power mode "auto wait", the ADC conversion data read + * is corresponding to previous ADC conversion start, independently + * of delay during which ADC was idle. + * Therefore, the ADC conversion data may be outdated: does not + * correspond to the current voltage level on the selected + * ADC channel. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode + * @param ADCx ADC instance + * @param LowPowerMode This parameter can be one of the following values: + * @arg @ref LL_ADC_LP_MODE_NONE + * @arg @ref LL_ADC_LP_AUTOWAIT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode); +} + +/** + * @brief Get ADC low power mode: + * @note Description of ADC low power modes: + * - ADC low power mode "auto wait": Dynamic low power mode, + * ADC conversions occurrences are limited to the minimum necessary + * in order to reduce power consumption. + * New ADC conversion starts only when the previous + * unitary conversion data (for ADC group regular) + * or previous sequence conversions data (for ADC group injected) + * has been retrieved by user software. + * In the meantime, ADC remains idle: does not performs any + * other conversion. + * This mode allows to automatically adapt the ADC conversions + * triggers to the speed of the software that reads the data. + * Moreover, this avoids risk of overrun for low frequency + * applications. + * How to use this low power mode: + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). + * - Do use with polling: 1. Start conversion, + * 2. Later on, when conversion data is needed: poll for end of + * conversion to ensure that conversion is completed and + * retrieve ADC conversion data. This will trig another + * ADC conversion start. + * @note With ADC low power mode "auto wait", the ADC conversion data read + * is corresponding to previous ADC conversion start, independently + * of delay during which ADC was idle. + * Therefore, the ADC conversion data may be outdated: does not + * correspond to the current voltage level on the selected + * ADC channel. + * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_LP_MODE_NONE + * @arg @ref LL_ADC_LP_AUTOWAIT + */ +__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY)); +} + +/** + * @brief Set ADC selected offset instance 1, 2, 3 or 4. + * @note This function set the 2 items of offset configuration: + * - ADC channel to which the offset programmed will be applied + * (independently of channel mapped on ADC group regular + * or group injected) + * - Offset level (offset to be subtracted from the raw + * converted data). + * @note Caution: Offset format is dependent to ADC resolution: + * offset has to be left-aligned on bit 11, the LSB (right bits) + * are set to 0. + * @note This function enables the offset, by default. It can be forced + * to disable state using function LL_ADC_SetOffsetState(). + * @note If a channel is mapped on several offsets numbers, only the offset + * with the lowest value is considered for the subtraction. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @note On STM32H7RS, some fast channels are available: fast analog inputs + * coming from GPIO pads (ADC_IN0..5). + * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n + * OFR1 OFFSET1 LL_ADC_SetOffset\n + * OFR1 OFFSET1_EN LL_ADC_SetOffset\n + * OFR2 OFFSET2_CH LL_ADC_SetOffset\n + * OFR2 OFFSET2 LL_ADC_SetOffset\n + * OFR2 OFFSET2_EN LL_ADC_SetOffset\n + * OFR3 OFFSET3_CH LL_ADC_SetOffset\n + * OFR3 OFFSET3 LL_ADC_SetOffset\n + * OFR3 OFFSET3_EN LL_ADC_SetOffset\n + * OFR4 OFFSET4_CH LL_ADC_SetOffset\n + * OFR4 OFFSET4 LL_ADC_SetOffset\n + * OFR4 OFFSET4_EN LL_ADC_SetOffset + * @param ADCx ADC instance + * @param Offsety This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (3) + * @arg @ref LL_ADC_CHANNEL_1 (3) + * @arg @ref LL_ADC_CHANNEL_2 (3) + * @arg @ref LL_ADC_CHANNEL_3 (3) + * @arg @ref LL_ADC_CHANNEL_4 (3) + * @arg @ref LL_ADC_CHANNEL_5 (3) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + + MODIFY_REG(*preg, + ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, + ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); +} + +/** + * @brief Get for the ADC selected offset instance 1, 2, 3 or 4: + * Channel to which the offset programmed will be applied + * (independently of channel mapped on ADC group regular + * or group injected) + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @note On STM32H7RS, some fast channels are available: fast analog inputs + * coming from GPIO pads (ADC_IN0..5). + * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n + * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n + * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n + * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel + * @param ADCx ADC instance + * @param Offsety This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (2) + * @arg @ref LL_ADC_CHANNEL_1 (2) + * @arg @ref LL_ADC_CHANNEL_2 (2) + * @arg @ref LL_ADC_CHANNEL_3 (2) + * @arg @ref LL_ADC_CHANNEL_4 (2) + * @arg @ref LL_ADC_CHANNEL_5 (2) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3) + * @arg @ref LL_ADC_CHANNEL_VBAT (1)(3) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (2) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * (3) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety) +{ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + + return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); +} + +/** + * @brief Get for the ADC selected offset instance 1, 2, 3 or 4: + * Offset level (offset to be subtracted from the raw + * converted data). + * @note Caution: Offset format is dependent to ADC resolution: + * offset has to be left-aligned on bit 11, the LSB (right bits) + * are set to 0. + * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n + * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n + * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n + * OFR4 OFFSET4 LL_ADC_GetOffsetLevel + * @param ADCx ADC instance + * @param Offsety This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety) +{ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + + return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1); +} + +/** + * @brief Set for the ADC selected offset instance 1, 2, 3 or 4: + * force offset state disable or enable + * without modifying offset channel or offset value. + * @note This function should be needed only in case of offset to be + * enabled-disabled dynamically, and should not be needed in other cases: + * function LL_ADC_SetOffset() automatically enables the offset. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n + * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n + * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n + * OFR4 OFFSET4_EN LL_ADC_SetOffsetState + * @param ADCx ADC instance + * @param Offsety This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @param OffsetState This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_DISABLE + * @arg @ref LL_ADC_OFFSET_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + + MODIFY_REG(*preg, + ADC_OFR1_OFFSET1_EN, + OffsetState); +} + +/** + * @brief Get for the ADC selected offset instance 1, 2, 3 or 4: + * offset state disabled or enabled. + * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n + * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n + * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n + * OFR4 OFFSET4_EN LL_ADC_GetOffsetState + * @param ADCx ADC instance + * @param Offsety This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OFFSET_DISABLE + * @arg @ref LL_ADC_OFFSET_ENABLE + */ +__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety) +{ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + + return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN); +} + +/** + * @brief Set for the ADC selected offset instance 1, 2, 3 or 4: + * choose offset sign. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n + * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n + * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n + * OFR4 OFFSETPOS LL_ADC_SetOffsetSign + * @param ADCx ADC instance + * @param Offsety This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @param OffsetSign This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE + * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + + MODIFY_REG(*preg, + ADC_OFR1_OFFSETPOS, + OffsetSign); +} + +/** + * @brief Get for the ADC selected offset instance 1, 2, 3 or 4: + * offset sign if positive or negative. + * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n + * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n + * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n + * OFR4 OFFSETPOS LL_ADC_GetOffsetSign + * @param ADCx ADC instance + * @param Offsety This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE + * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE + */ +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety) +{ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + + return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS); +} + +/** + * @brief Set for the ADC selected offset instance 1, 2, 3 or 4: + * choose offset saturation mode. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll OFR1 SATEN LL_ADC_SetOffsetSaturation\n + * OFR2 SATEN LL_ADC_SetOffsetSaturation\n + * OFR3 SATEN LL_ADC_SetOffsetSaturation\n + * OFR4 SATEN LL_ADC_SetOffsetSaturation + * @param ADCx ADC instance + * @param Offsety This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @param OffsetSaturation This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE + * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + + MODIFY_REG(*preg, + ADC_OFR1_SATEN, + OffsetSaturation); +} + +/** + * @brief Get for the ADC selected offset instance 1, 2, 3 or 4: + * offset saturation if enabled or disabled. + * @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n + * OFR2 SATEN LL_ADC_GetOffsetSaturation\n + * OFR3 SATEN LL_ADC_GetOffsetSaturation\n + * OFR4 SATEN LL_ADC_GetOffsetSaturation + * @param ADCx ADC instance + * @param Offsety This parameter can be one of the following values: + * @arg @ref LL_ADC_OFFSET_1 + * @arg @ref LL_ADC_OFFSET_2 + * @arg @ref LL_ADC_OFFSET_3 + * @arg @ref LL_ADC_OFFSET_4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE + * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE + */ +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety) +{ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + + return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN); +} + +#if defined(ADC_SMPR1_SMPPLUS) +/** + * @brief Set ADC sampling time common configuration impacting + * settings of sampling time channel wise. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig + * @param ADCx ADC instance + * @param SamplingTimeCommonConfig This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig) +{ + MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig); +} + +/** + * @brief Get ADC sampling time common configuration impacting + * settings of sampling time channel wise. + * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 + */ +__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS)); +} +#endif /* ADC_SMPR1_SMPPLUS */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Set ADC group regular conversion trigger source: + * internal (SW start) or from external peripheral (timer event, + * external interrupt line). + * @note On this STM32 series, setting trigger source to external trigger + * also set trigger polarity to rising edge + * (default setting for compatibility with some ADC on other + * STM32 series having this setting set by HW default value). + * In case of need to modify trigger edge, use + * function @ref LL_ADC_REG_SetTriggerEdge(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n + * CFGR EXTEN LL_ADC_REG_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM12_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1 + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource); +} + +/** + * @brief Get ADC group regular conversion trigger source: + * internal (SW start) or from external peripheral (timer event, + * external interrupt line). + * @note To determine whether group regular trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") + * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n + * CFGR EXTEN LL_ADC_REG_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM12_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1 + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx) +{ + __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); + + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ + /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ + uint32_t shift_exten = ((trigger_source & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + + /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ + /* to match with triggers literals definition. */ + return ((trigger_source + & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR_EXTSEL) + | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR_EXTEN) + ); +} + +/** + * @brief Get ADC group regular conversion trigger source internal (SW start) + * or external. + * @note In case of group regular trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_REG_GetTriggerSource(). + * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); +} + +/** + * @brief Set ADC group regular conversion trigger polarity. + * @note Applicable only for trigger source set to external trigger. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge + * @param ADCx ADC instance + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge); +} + +/** + * @brief Get ADC group regular conversion trigger polarity. + * @note Applicable only for trigger source set to external trigger. + * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN)); +} + +/** + * @brief Set ADC sampling mode. + * @note This function set the ADC conversion sampling mode + * @note This mode applies to regular group only. + * @note Set sampling mode is applied to all conversion of regular group. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n + * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode + * @param ADCx ADC instance + * @param SamplingMode This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL + * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB + * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode); +} + +/** + * @brief Get the ADC sampling mode + * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n + * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL + * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB + * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG)); +} + +/** + * @brief Set ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength + * @param ADCx ADC instance + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) +{ + MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); +} + +/** + * @brief Get ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); +} + +/** + * @brief Set ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note It is not possible to enable both ADC auto-injected mode + * and ADC group regular sequencer discontinuous mode. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n + * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont); +} + +/** + * @brief Get ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n + * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM)); +} + +/** + * @brief Set ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note This function performs configuration of: + * - Channels ordering into each rank of scan sequence: + * whatever channel can be placed into whatever rank. + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n + * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n + * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (3) + * @arg @ref LL_ADC_CHANNEL_1 (3) + * @arg @ref LL_ADC_CHANNEL_2 (3) + * @arg @ref LL_ADC_CHANNEL_3 (3) + * @arg @ref LL_ADC_CHANNEL_4 (3) + * @arg @ref LL_ADC_CHANNEL_5 (3) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register and register position depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, + ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); + + MODIFY_REG(*preg, + ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), + ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); +} + +/** + * @brief Get ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n + * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n + * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (2) + * @arg @ref LL_ADC_CHANNEL_1 (2) + * @arg @ref LL_ADC_CHANNEL_2 (2) + * @arg @ref LL_ADC_CHANNEL_3 (2) + * @arg @ref LL_ADC_CHANNEL_4 (2) + * @arg @ref LL_ADC_CHANNEL_5 (2) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3) + * @arg @ref LL_ADC_CHANNEL_VBAT (1)(3) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (2) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * (3) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) +{ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, + ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); + + return (uint32_t)((READ_BIT(*preg, + ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS + ); +} + +/** + * @brief Set ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode + * @param ADCx ADC instance + * @param Continuous This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous); +} + +/** + * @brief Get ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT)); +} + +/** + * @brief Set ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note For devices with several ADC instances: ADC multimode DMA + * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n + * CFGR DMACFG LL_ADC_REG_SetDMATransfer + * @param ADCx ADC instance + * @param DMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer); +} + +/** + * @brief Get ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note For devices with several ADC instances: ADC multimode DMA + * settings are available using function @ref LL_ADC_GetMultiDMATransfer(). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n + * CFGR DMACFG LL_ADC_REG_GetDMATransfer + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG)); +} + +/** + * @brief Set ADC group regular conversion data transfer to MDF (ADF). + * @note MDF transfer cannot be used if DMA transfer is enabled. + * @note To configure MDF source address (peripheral address), + * use the same function as for DMA transfer: + * function @ref LL_ADC_DMA_GetRegAddr(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll CFGR ADFCFG LL_ADC_REG_GetMDFTransfer + * @param ADCx ADC instance + * @param MDFTransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_MDF_TRANSFER_NONE + * @arg @ref LL_ADC_REG_MDF_TRANSFER_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetMDFTransfer(ADC_TypeDef *ADCx, uint32_t MDFTransfer) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_ADFCFG, MDFTransfer); +} + +/** + * @brief Get ADC group regular conversion data transfer to MDF (ADF). + * @rmtoll CFGR ADFCFG LL_ADC_REG_GetMDFTransfer + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_MDF_TRANSFER_NONE + * @arg @ref LL_ADC_REG_MDF_TRANSFER_ENABLE + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetMDFTransfer(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ADFCFG)); +} + +/** + * @brief Set ADC group regular behavior in case of overrun: + * data preserved or overwritten. + * @note Compatibility with devices without feature overrun: + * other devices without this feature have a behavior + * equivalent to data overwritten. + * The default setting of overrun is data preserved. + * Therefore, for compatibility with all devices, parameter + * overrun should be set to data overwritten. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun + * @param ADCx ADC instance + * @param Overrun This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED + * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun); +} + +/** + * @brief Get ADC group regular behavior in case of overrun: + * data preserved or overwritten. + * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED + * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected + * @{ + */ + +/** + * @brief Set ADC group injected conversion trigger source: + * internal (SW start) or from external peripheral (timer event, + * external interrupt line). + * @note On this STM32 series, setting trigger source to external trigger + * also set trigger polarity to rising edge + * (default setting for compatibility with some ADC on other + * STM32 series having this setting set by HW default value). + * In case of need to modify trigger edge, use + * function @ref LL_ADC_INJ_SetTriggerEdge(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must not be disabled. Can be enabled with or without conversion + * on going on either groups regular or injected. + * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n + * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM12_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1 + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ + MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource); +} + +/** + * @brief Get ADC group injected conversion trigger source: + * internal (SW start) or from external peripheral (timer event, + * external interrupt line). + * @note To determine whether group injected trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") + * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n + * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM12_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1 + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx) +{ + __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); + + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ + /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ + uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + + /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ + /* to match with triggers literals definition. */ + return ((trigger_source + & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL) + | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN) + ); +} + +/** + * @brief Get ADC group injected conversion trigger source internal (SW start) + or external + * @note In case of group injected trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_INJ_GetTriggerSource. + * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL); +} + +/** + * @brief Set ADC group injected conversion trigger polarity. + * Applicable only for trigger source set to external trigger. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must not be disabled. Can be enabled with or without conversion + * on going on either groups regular or injected. + * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge + * @param ADCx ADC instance + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING + * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge); +} + +/** + * @brief Get ADC group injected conversion trigger polarity. + * Applicable only for trigger source set to external trigger. + * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING + * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN)); +} + +/** + * @brief Set ADC group injected sequencer length and scan direction. + * @note This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must not be disabled. Can be enabled with or without conversion + * on going on either groups regular or injected. + * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength + * @param ADCx ADC instance + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) +{ + MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); +} + +/** + * @brief Get ADC group injected sequencer length and scan direction. + * @note This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); +} + +/** + * @brief Set ADC group injected sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group injected + * auto-injected mode and sequencer discontinuous mode. + * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont); +} + +/** + * @brief Get ADC group injected sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN)); +} + +/** + * @brief Set ADC group injected sequence: channel on the selected + * sequence rank. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On STM32H7RS, some fast channels are available: fast analog inputs + * coming from GPIO pads (ADC_IN0..5). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must not be disabled. Can be enabled with or without conversion + * on going on either groups regular or injected. + * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (3) + * @arg @ref LL_ADC_CHANNEL_1 (3) + * @arg @ref LL_ADC_CHANNEL_2 (3) + * @arg @ref LL_ADC_CHANNEL_3 (3) + * @arg @ref LL_ADC_CHANNEL_4 (3) + * @arg @ref LL_ADC_CHANNEL_5 (3) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + MODIFY_REG(ADCx->JSQR, + (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (Rank & ADC_INJ_RANK_ID_JSQR_MASK), + ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)); +} + +/** + * @brief Get ADC group injected sequence: channel on the selected + * sequence rank. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n + * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (2) + * @arg @ref LL_ADC_CHANNEL_1 (2) + * @arg @ref LL_ADC_CHANNEL_2 (2) + * @arg @ref LL_ADC_CHANNEL_3 (2) + * @arg @ref LL_ADC_CHANNEL_4 (2) + * @arg @ref LL_ADC_CHANNEL_5 (2) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1)(3) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(3) + * @arg @ref LL_ADC_CHANNEL_VBAT (1)(3) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (2) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * (3) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) +{ + return (uint32_t)((READ_BIT(ADCx->JSQR, + (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) + >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS + ); +} + +/** + * @brief Set ADC group injected conversion trigger: + * independent or from ADC group regular. + * @note This mode can be used to extend number of data registers + * updated after one ADC conversion trigger and with data + * permanently kept (not erased by successive conversions of scan of + * ADC sequencer ranks), up to 5 data registers: + * 1 data register on ADC group regular, 4 data registers + * on ADC group injected. + * @note If ADC group injected injected trigger source is set to an + * external trigger, this feature must be must be set to + * independent trigger. + * ADC group injected automatic trigger is compliant only with + * group injected trigger source set to SW start, without any + * further action on ADC group injected conversion start or stop: + * in this case, ADC group injected is controlled only + * from ADC group regular. + * @note It is not possible to enable both ADC group injected + * auto-injected mode and sequencer discontinuous mode. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto + * @param ADCx ADC instance + * @param TrigAuto This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT + * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto); +} + +/** + * @brief Get ADC group injected conversion trigger: + * independent or from ADC group regular. + * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT + * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO)); +} + +/** + * @brief Set ADC group injected contexts queue mode. + * @note A context is a setting of group injected sequencer: + * - group injected trigger + * - sequencer length + * - sequencer ranks + * If contexts queue is disabled: + * - only 1 sequence can be configured + * and is active perpetually. + * If contexts queue is enabled: + * - up to 2 contexts can be queued + * and are checked in and out as a FIFO stack (first-in, first-out). + * - If a new context is set when queues is full, error is triggered + * by interruption "Injected Queue Overflow". + * - Two behaviors are possible when all contexts have been processed: + * the contexts queue can maintain the last context active perpetually + * or can be empty and injected group triggers are disabled. + * - Triggers can be only external (not internal SW start) + * - Caution: The sequence must be fully configured in one time + * (one write of register JSQR makes a check-in of a new context + * into the queue). + * Therefore functions to set separately injected trigger and + * sequencer channels cannot be used, register JSQR must be set + * using function @ref LL_ADC_INJ_ConfigQueueContext(). + * @note This parameter can be modified only when no conversion is on going + * on either groups regular or injected. + * @note A modification of the context mode (bit JQDIS) causes the contexts + * queue to be flushed and the register JSQR is cleared. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n + * CFGR JQDIS LL_ADC_INJ_SetQueueMode + * @param ADCx ADC instance + * @param QueueMode This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_QUEUE_DISABLE + * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE + * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode) +{ + MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode); +} + +/** + * @brief Get ADC group injected context queue mode. + * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n + * CFGR JQDIS LL_ADC_INJ_GetQueueMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_QUEUE_DISABLE + * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE + * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS)); +} + +/** + * @brief Set one context on ADC group injected that will be checked in + * contexts queue. + * @note A context is a setting of group injected sequencer: + * - group injected trigger + * - sequencer length + * - sequencer ranks + * This function is intended to be used when contexts queue is enabled, + * because the sequence must be fully configured in one time + * (functions to set separately injected trigger and sequencer channels + * cannot be used): + * Refer to function @ref LL_ADC_INJ_SetQueueMode(). + * @note In the contexts queue, only the active context can be read. + * The parameters of this function can be read using functions: + * @arg @ref LL_ADC_INJ_GetTriggerSource() + * @arg @ref LL_ADC_INJ_GetTriggerEdge() + * @arg @ref LL_ADC_INJ_GetSequencerRanks() + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On STM32H7RS, some fast channels are available: fast analog inputs + * coming from GPIO pads (ADC_IN0..5). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must not be disabled. Can be enabled with or without conversion + * on going on either groups regular or injected. + * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n + * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n + * JSQR JL LL_ADC_INJ_ConfigQueueContext\n + * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n + * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n + * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n + * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM12_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1 + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING + * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING + * + * Note: This parameter is discarded in case of SW start: + * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE". + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + * @param Rank1_Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (3) + * @arg @ref LL_ADC_CHANNEL_1 (3) + * @arg @ref LL_ADC_CHANNEL_2 (3) + * @arg @ref LL_ADC_CHANNEL_3 (3) + * @arg @ref LL_ADC_CHANNEL_4 (3) + * @arg @ref LL_ADC_CHANNEL_5 (3) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * @param Rank2_Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (3) + * @arg @ref LL_ADC_CHANNEL_1 (3) + * @arg @ref LL_ADC_CHANNEL_2 (3) + * @arg @ref LL_ADC_CHANNEL_3 (3) + * @arg @ref LL_ADC_CHANNEL_4 (3) + * @arg @ref LL_ADC_CHANNEL_5 (3) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * @param Rank3_Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (3) + * @arg @ref LL_ADC_CHANNEL_1 (3) + * @arg @ref LL_ADC_CHANNEL_2 (3) + * @arg @ref LL_ADC_CHANNEL_3 (3) + * @arg @ref LL_ADC_CHANNEL_4 (3) + * @arg @ref LL_ADC_CHANNEL_5 (3) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * @param Rank4_Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (3) + * @arg @ref LL_ADC_CHANNEL_1 (3) + * @arg @ref LL_ADC_CHANNEL_2 (3) + * @arg @ref LL_ADC_CHANNEL_3 (3) + * @arg @ref LL_ADC_CHANNEL_4 (3) + * @arg @ref LL_ADC_CHANNEL_5 (3) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, + uint32_t TriggerSource, + uint32_t ExternalTriggerEdge, + uint32_t SequencerNbRanks, + uint32_t Rank1_Channel, + uint32_t Rank2_Channel, + uint32_t Rank3_Channel, + uint32_t Rank4_Channel) +{ + /* Set bits with content of parameter "Rankx_Channel" with bits position */ + /* in register depending on literal "LL_ADC_INJ_RANK_x". */ + /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */ + /* because containing other bits reserved for other purpose. */ + /* If parameter "TriggerSource" is set to SW start, then parameter */ + /* "ExternalTriggerEdge" is discarded. */ + uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); + MODIFY_REG(ADCx->JSQR, + ADC_JSQR_JEXTSEL | + ADC_JSQR_JEXTEN | + ADC_JSQR_JSQ4 | + ADC_JSQR_JSQ3 | + ADC_JSQR_JSQ2 | + ADC_JSQR_JSQ1 | + ADC_JSQR_JL, + (TriggerSource & ADC_JSQR_JEXTSEL) | + (ExternalTriggerEdge * (is_trigger_not_sw)) | + (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) | + (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) | + (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) | + (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) | + SequencerNbRanks + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels + * @{ + */ + +/** + * @brief Set sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * On this STM32 series, ADC processing time is: + * - 12.5 ADC clock cycles at ADC resolution 12 bits + * - 10.5 ADC clock cycles at ADC resolution 10 bits + * - 8.5 ADC clock cycles at ADC resolution 8 bits + * - 6.5 ADC clock cycles at ADC resolution 6 bits + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (3) + * @arg @ref LL_ADC_CHANNEL_1 (3) + * @arg @ref LL_ADC_CHANNEL_2 (3) + * @arg @ref LL_ADC_CHANNEL_3 (3) + * @arg @ref LL_ADC_CHANNEL_4 (3) + * @arg @ref LL_ADC_CHANNEL_5 (3) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * @param SamplingTime This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1) + * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5 + * + * (1) On some devices, ADC sampling time 2.5 ADC clock cycles + * can be replaced by 3.5 ADC clock cycles. + * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig(). + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) +{ + /* Set bits with content of parameter "SamplingTime" with bits position */ + /* in register and register position depending on parameter "Channel". */ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, + ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + + MODIFY_REG(*preg, + ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), + SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); +} + +/** + * @brief Get sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note Conversion time is the addition of sampling time and processing time. + * On this STM32 series, ADC processing time is: + * - 12.5 ADC clock cycles at ADC resolution 12 bits + * - 10.5 ADC clock cycles at ADC resolution 10 bits + * - 8.5 ADC clock cycles at ADC resolution 8 bits + * - 6.5 ADC clock cycles at ADC resolution 6 bits + * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 (3) + * @arg @ref LL_ADC_CHANNEL_1 (3) + * @arg @ref LL_ADC_CHANNEL_2 (3) + * @arg @ref LL_ADC_CHANNEL_3 (3) + * @arg @ref LL_ADC_CHANNEL_4 (3) + * @arg @ref LL_ADC_CHANNEL_5 (3) + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) + * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1) + * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5 + * + * (1) On some devices, ADC sampling time 2.5 ADC clock cycles + * can be replaced by 3.5 ADC clock cycles. + * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig(). + */ +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel) +{ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) + >> ADC_SMPRX_REGOFFSET_POS)); + + return (uint32_t)(READ_BIT(*preg, + ADC_SMPR1_SMP0 + << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) + >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS) + ); +} + +/** + * @brief Set mode single-ended or differential input of the selected + * ADC channel. + * @note Channel ending is on channel scope: independently of channel mapped + * on ADC group regular or injected. + * In differential mode: Differential measurement is carried out + * between the selected channel 'i' (positive input) and + * channel 'i+1' (negative input). Only channel 'i' has to be + * configured, channel 'i+1' is configured automatically. + * @note Refer to Reference Manual to ensure the selected channel is + * available in differential mode. + * For example, internal channels (VrefInt, TempSensor, ...) are + * not available in differential mode. + * @note When configuring a channel 'i' in differential mode, + * the channel 'i+1' is not usable separately. + * @note Channels 0, 5, 6, 7, 9, 13, 14, 15, 16, 17, 18 + * are internally fixed to single-ended inputs configuration. + * @note For ADC channels configured in differential mode, both inputs + * should be biased at (Vref+)/2 +/-200mV. + * (Vref+ is the analog voltage reference) + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @param SingleDiff This parameter can be a combination of the following values: + * @arg @ref LL_ADC_SINGLE_ENDED + * @arg @ref LL_ADC_DIFFERENTIAL_ENDED + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) +{ + /* Bits of channels in single or differential mode are set only for */ + /* differential mode (for single mode, mask of bits allowed to be set is */ + /* shifted out of range of bits of channels in single or differential mode. */ + MODIFY_REG(ADCx->DIFSEL, + Channel & ADC_SINGLEDIFF_CHANNEL_MASK, + (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) + & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); +} + +/** + * @brief Get mode single-ended or differential input of the selected + * ADC channel. + * @note When configuring a channel 'i' in differential mode, + * the channel 'i+1' is not usable separately. + * Therefore, to ensure a channel is configured in single-ended mode, + * the configuration of channel itself and the channel 'i-1' must be + * read back (to ensure that the selected channel channel has not been + * configured in differential mode by the previous channel). + * @note Refer to Reference Manual to ensure the selected channel is + * available in differential mode. + * For example, internal channels (VrefInt, TempSensor, ...) are + * not available in differential mode. + * @note When configuring a channel 'i' in differential mode, + * the channel 'i+1' is not usable separately. + * @note Channels 0, 5, 6, 7, 9, 13, 14, 15, 16, 17, 18 + * are internally fixed to single-ended inputs configuration. + * @note One or several values can be selected. In this case, the value + * returned is null if all channels are in single ended-mode. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @retval 0: channel in single-ended mode, else: channel in differential mode + */ +__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel) +{ + return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK))); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog + * @{ + */ + +/** + * @brief Set ADC analog watchdog monitored channels: + * a single channel, multiple channels or all channels, + * on ADC groups regular and-or injected. + * @note Once monitored channels are selected, analog watchdog + * is enabled. + * @note In case of need to define a single channel to monitor + * with analog watchdog from sequencer channel definition, + * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). + * @note On this STM32 series, there are 2 kinds of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * - AWD flexible (instances AWD2, AWD3): + * - channels monitored: flexible on channels monitored, selection is + * channel wise, from from 1 to all channels. + * Specificity of this analog watchdog: Multiple channels can + * be selected. For example: + * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) + * - groups monitored: not selection possible (monitoring on both + * groups regular and injected). + * Channels selected are monitored on groups regular and injected: + * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters + * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) + * - resolution: resolution is limited to 8 bits: if ADC resolution is + * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits + * the 2 LSB are ignored. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n + * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n + * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n + * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n + * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n + * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDChannelGroup This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1) + * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) + * + * (0) On STM32H7RS, parameter available only on analog watchdog number: AWD1.\n + * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) +{ + /* Set bits with content of parameter "AWDChannelGroup" with bits position */ + /* in register and register position depending on parameter "AWDy". */ + /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ + /* containing other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, + ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) + * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + + MODIFY_REG(*preg, + (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), + AWDChannelGroup & AWDy); +} + +/** + * @brief Get ADC analog watchdog monitored channel. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Applicable only when the analog watchdog is set to monitor + * one channel. + * @note On this STM32 series, there are 2 kinds of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * - AWD flexible (instances AWD2, AWD3): + * - channels monitored: flexible on channels monitored, selection is + * channel wise, from from 1 to all channels. + * Specificity of this analog watchdog: Multiple channels can + * be selected. For example: + * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) + * - groups monitored: not selection possible (monitoring on both + * groups regular and injected). + * Channels selected are monitored on groups regular and injected: + * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters + * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) + * - resolution: resolution is limited to 8 bits: if ADC resolution is + * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits + * the 2 LSB are ignored. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n + * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n + * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n + * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n + * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n + * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 (1) + * @arg @ref LL_ADC_AWD3 (1) + * + * (1) On this AWD number, monitored channel can be retrieved + * if only 1 channel is programmed (or none or all channels). + * This function cannot retrieve monitored channel if + * multiple channels are programmed simultaneously + * by bitfield. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) + * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ + * + * (0) On STM32H7RS, parameter available only on analog watchdog number: AWD1. + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) +{ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, + ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) + * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + + uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); + + /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */ + /* (parameter value LL_ADC_AWD_DISABLE). */ + /* Else, the selected AWD is enabled and is monitoring a group of channels */ + /* or a single channel. */ + if (analog_wd_monit_channels != 0UL) + { + if (AWDy == LL_ADC_AWD1) + { + if ((analog_wd_monit_channels & ADC_CFGR_AWD1SGL) == 0UL) + { + /* AWD monitoring a group of channels */ + analog_wd_monit_channels = ((analog_wd_monit_channels + | (ADC_AWD_CR23_CHANNEL_MASK) + ) + & (~(ADC_CFGR_AWD1CH)) + ); + } + else + { + /* AWD monitoring a single channel */ + analog_wd_monit_channels = (analog_wd_monit_channels + | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR_AWD1CH_Pos)) + ); + } + } + else + { + if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) + { + /* AWD monitoring a group of channels */ + analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK + | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)) + ); + } + else + { + /* AWD monitoring a single channel */ + /* AWD monitoring a group of channels */ + analog_wd_monit_channels = (analog_wd_monit_channels + | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) + | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR_AWD1CH_Pos) + ); + } + } + } + + return analog_wd_monit_channels; +} + +/** + * @brief Set ADC analog watchdog thresholds value of both thresholds + * high and low. + * @note If value of only one threshold high or low must be set, + * use function @ref LL_ADC_SetAnalogWDThresholds(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). + * @note On this STM32 series, there are 2 kinds of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * - AWD flexible (instances AWD2, AWD3): + * - channels monitored: flexible on channels monitored, selection is + * channel wise, from from 1 to all channels. + * Specificity of this analog watchdog: Multiple channels can + * be selected. For example: + * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) + * - groups monitored: not selection possible (monitoring on both + * groups regular and injected). + * Channels selected are monitored on groups regular and injected: + * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters + * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) + * - resolution: resolution is limited to 8 bits: if ADC resolution is + * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits + * the 2 LSB are ignored. + * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are + * impacted: the comparison of analog watchdog thresholds is done on + * oversampling final computation (after ratio and shift application): + * ADC data register bitfield [15:4] (12 most significant bits). + * Examples: + * - Oversampling ratio and shift selected to have ADC conversion data + * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): + * ADC analog watchdog thresholds must be divided by 16. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): + * ADC analog watchdog thresholds must be divided by 4. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): + * ADC analog watchdog thresholds match directly to ADC data register. + * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n + * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n + * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n + * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n + * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n + * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, + uint32_t AWDThresholdLowValue) +{ + /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ + /* position in register and register position depending on parameter */ + /* "AWDy". */ + /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ + /* containing other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, + ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + + MODIFY_REG(*preg, + ADC_TR1_HT1 | ADC_TR1_LT1, + (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue); +} + +/** + * @brief Set ADC analog watchdog threshold value of threshold + * high or low. + * @note If values of both thresholds high or low must be set, + * use function @ref LL_ADC_ConfigAnalogWDThresholds(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). + * @note On this STM32 series, there are 2 kinds of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * - AWD flexible (instances AWD2, AWD3): + * - channels monitored: flexible on channels monitored, selection is + * channel wise, from from 1 to all channels. + * Specificity of this analog watchdog: Multiple channels can + * be selected. For example: + * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) + * - groups monitored: not selection possible (monitoring on both + * groups regular and injected). + * Channels selected are monitored on groups regular and injected: + * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters + * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) + * - resolution: resolution is limited to 8 bits: if ADC resolution is + * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits + * the 2 LSB are ignored. + * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are + * impacted: the comparison of analog watchdog thresholds is done on + * oversampling final computation (after ratio and shift application): + * ADC data register bitfield [15:4] (12 most significant bits). + * Examples: + * - Oversampling ratio and shift selected to have ADC conversion data + * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): + * ADC analog watchdog thresholds must be divided by 16. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): + * ADC analog watchdog thresholds must be divided by 4. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): + * ADC analog watchdog thresholds match directly to ADC data register. + * @note On this STM32 series, setting of this feature is not conditioned to + * ADC state: + * ADC can be disabled, enabled with or without conversion on going + * on either ADC groups regular or injected. + * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n + * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n + * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n + * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n + * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n + * TR3 LT3 LL_ADC_SetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, + uint32_t AWDThresholdValue) +{ + /* Set bits with content of parameter "AWDThresholdValue" with bits */ + /* position in register and register position depending on parameters */ + /* "AWDThresholdsHighLow" and "AWDy". */ + /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ + /* containing other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, + ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + + MODIFY_REG(*preg, + AWDThresholdsHighLow, + AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); +} + +/** + * @brief Get ADC analog watchdog threshold value of threshold high, + * threshold low or raw data with ADC thresholds high and low + * concatenated. + * @note If raw data with ADC thresholds high and low is retrieved, + * the data of each threshold high or low can be isolated + * using helper macro: + * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). + * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n + * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n + * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n + * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n + * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n + * TR3 LT3 LL_ADC_GetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, + uint32_t AWDy, uint32_t AWDThresholdsHighLow) +{ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, + ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + + return (uint32_t)(READ_BIT(*preg, + (AWDThresholdsHighLow | ADC_TR1_LT1)) + >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) + & ~(AWDThresholdsHighLow & ADC_TR1_LT1))); +} + +/** + * @brief Set ADC analog watchdog filtering configuration + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @note On this STM32 series, this feature is only available on first + * analog watchdog (AWD1) + * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @param FilteringConfig This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_FILTERING_NONE + * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(AWDy); + MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig); +} + +/** + * @brief Get ADC analog watchdog filtering configuration + * @note On this STM32 series, this feature is only available on first + * analog watchdog (AWD1) + * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @retval Returned value can be: + * @arg @ref LL_ADC_AWD_FILTERING_NONE + * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES + * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES + */ +__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(AWDy); + return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling + * @{ + */ + +/** + * @brief Set ADC oversampling scope: ADC groups regular and-or injected + * (availability of ADC group injected depends on STM32 series). + * @note If both groups regular and injected are selected, + * specify behavior of ADC group injected interrupting + * group regular: when ADC group injected is triggered, + * the oversampling on ADC group regular is either + * temporary stopped and continued, or resumed from start + * (oversampler buffer reset). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n + * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n + * CFGR2 ROVSM LL_ADC_SetOverSamplingScope + * @param ADCx ADC instance + * @param OvsScope This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_DISABLE + * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED + * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED + * @arg @ref LL_ADC_OVS_GRP_INJECTED + * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope); +} + +/** + * @brief Get ADC oversampling scope: ADC groups regular and-or injected + * (availability of ADC group injected depends on STM32 series). + * @note If both groups regular and injected are selected, + * specify behavior of ADC group injected interrupting + * group regular: when ADC group injected is triggered, + * the oversampling on ADC group regular is either + * temporary stopped and continued, or resumed from start + * (oversampler buffer reset). + * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n + * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n + * CFGR2 ROVSM LL_ADC_GetOverSamplingScope + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OVS_DISABLE + * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED + * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED + * @arg @ref LL_ADC_OVS_GRP_INJECTED + * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); +} + +/** + * @brief Set ADC oversampling discontinuous mode (triggered mode) + * on the selected ADC group. + * @note Number of oversampled conversions are done either in: + * - continuous mode (all conversions of oversampling ratio + * are done from 1 trigger) + * - discontinuous mode (each conversion of oversampling ratio + * needs a trigger) + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note On this STM32 series, oversampling discontinuous mode + * (triggered mode) can be used only when oversampling is + * set on group regular only and in resumed mode. + * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont + * @param ADCx ADC instance + * @param OverSamplingDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_REG_CONT + * @arg @ref LL_ADC_OVS_REG_DISCONT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont); +} + +/** + * @brief Get ADC oversampling discontinuous mode (triggered mode) + * on the selected ADC group. + * @note Number of oversampled conversions are done either in: + * - continuous mode (all conversions of oversampling ratio + * are done from 1 trigger) + * - discontinuous mode (each conversion of oversampling ratio + * needs a trigger) + * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OVS_REG_CONT + * @arg @ref LL_ADC_OVS_REG_DISCONT + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS)); +} + +/** + * @brief Set ADC oversampling + * (impacting both ADC groups regular and injected) + * @note This function set the 2 items of oversampling configuration: + * - ratio + * - shift + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on either groups regular or injected. + * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n + * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift + * @param ADCx ADC instance + * @param Ratio This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_RATIO_2 + * @arg @ref LL_ADC_OVS_RATIO_4 + * @arg @ref LL_ADC_OVS_RATIO_8 + * @arg @ref LL_ADC_OVS_RATIO_16 + * @arg @ref LL_ADC_OVS_RATIO_32 + * @arg @ref LL_ADC_OVS_RATIO_64 + * @arg @ref LL_ADC_OVS_RATIO_128 + * @arg @ref LL_ADC_OVS_RATIO_256 + * @param Shift This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_SHIFT_NONE + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 + * @retval None + */ +__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift) +{ + MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); +} + +/** + * @brief Get ADC oversampling ratio + * (impacting both ADC groups regular and injected) + * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio + * @param ADCx ADC instance + * @retval Ratio This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_RATIO_2 + * @arg @ref LL_ADC_OVS_RATIO_4 + * @arg @ref LL_ADC_OVS_RATIO_8 + * @arg @ref LL_ADC_OVS_RATIO_16 + * @arg @ref LL_ADC_OVS_RATIO_32 + * @arg @ref LL_ADC_OVS_RATIO_64 + * @arg @ref LL_ADC_OVS_RATIO_128 + * @arg @ref LL_ADC_OVS_RATIO_256 + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); +} + +/** + * @brief Get ADC oversampling shift + * (impacting both ADC groups regular and injected) + * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift + * @param ADCx ADC instance + * @retval Shift This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_SHIFT_NONE + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode + * @{ + */ + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Set ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR DUAL LL_ADC_SetMultimode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param Multimode This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode); +} + +/** + * @brief Get ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @rmtoll CCR DUAL LL_ADC_GetMultimode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); +} + +/** + * @brief Set ADC multimode conversion data transfer: no transfer + * or transfer by DMA. + * @note If ADC multimode transfer by DMA is not selected: + * each ADC uses its own DMA channel, with its individual + * DMA transfer settings. + * If ADC multimode transfer by DMA is selected: + * One DMA channel is used for both ADC (DMA of ADC master) + * Specifies the DMA requests mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note How to retrieve multimode conversion data: + * Whatever multimode transfer by DMA setting: using function + * @ref LL_ADC_REG_ReadMultiConversionData32(). + * If ADC multimode transfer by DMA is selected: conversion data + * is a raw data with ADC master and slave concatenated. + * A macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled + * or enabled without conversion on going on group regular. + * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n + * CCR DMACFG LL_ADC_SetMultiDMATransfer + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param MultiDMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer); +} + +/** + * @brief Get ADC multimode conversion data transfer: no transfer + * or transfer by DMA. + * @note If ADC multimode transfer by DMA is not selected: + * each ADC uses its own DMA channel, with its individual + * DMA transfer settings. + * If ADC multimode transfer by DMA is selected: + * One DMA channel is used for both ADC (DMA of ADC master) + * Specifies the DMA requests mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note How to retrieve multimode conversion data: + * Whatever multimode transfer by DMA setting: using function + * @ref LL_ADC_REG_ReadMultiConversionData32(). + * If ADC multimode transfer by DMA is selected: conversion data + * is a raw data with ADC master and slave concatenated. + * A macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n + * CCR DMACFG LL_ADC_GetMultiDMATransfer + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG)); +} + +/** + * @brief Set ADC multimode delay between 2 sampling phases. + * @note The sampling delay range depends on ADC resolution: + * - ADC resolution 12 bits can have maximum delay of 12 cycles. + * - ADC resolution 10 bits can have maximum delay of 10 cycles. + * - ADC resolution 8 bits can have maximum delay of 8 cycles. + * - ADC resolution 6 bits can have maximum delay of 6 cycles. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param MultiTwoSamplingDelay This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3) + * + * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n + * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n + * (3) Parameter available only if ADC resolution is 12 bits. + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay); +} + +/** + * @brief Get ADC multimode delay between 2 sampling phases. + * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3) + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3) + * + * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n + * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n + * (3) Parameter available only if ADC resolution is 12 bits. + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ +/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Put ADC instance in deep power down state. + * @note In case of ADC calibration necessary: When ADC is in deep-power-down + * state, the internal analog calibration is lost. After exiting from + * deep power down, calibration must be relaunched or calibration factor + * (preliminarily saved) must be set back into calibration register. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_DEEPPWD); +} + +/** + * @brief Disable ADC deep power down mode. + * @note In case of ADC calibration necessary: When ADC is in deep-power-down + * state, the internal analog calibration is lost. After exiting from + * deep power down, calibration must be relaunched or calibration factor + * (preliminarily saved) must be set back into calibration register. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); +} + +/** + * @brief Get the selected ADC instance deep power down state. + * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled + * @param ADCx ADC instance + * @retval 0: deep power down is disabled, 1: deep power down is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); +} + +/** + * @brief Enable ADC instance internal voltage regulator. + * @note On this STM32 series, after ADC internal voltage regulator enable, + * a delay for ADC internal voltage regulator stabilization + * is required before performing a ADC calibration or ADC enable. + * Refer to device datasheet, parameter tADCVREG_STUP. + * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADVREGEN); +} + +/** + * @brief Disable ADC internal voltage regulator. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS)); +} + +/** + * @brief Get the selected ADC instance internal voltage regulator state. + * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled + * @param ADCx ADC instance + * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the selected ADC instance. + * @note On this STM32 series, after ADC enable, a delay for + * ADC internal analog stabilization is required before performing a + * ADC conversion start. + * Refer to device datasheet, parameter tSTAB. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled and ADC internal voltage regulator enabled. + * @rmtoll CR ADEN LL_ADC_Enable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADEN); +} + +/** + * @brief Disable the selected ADC instance. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be not disabled. Must be enabled without conversion on going + * on either groups regular or injected. + * @rmtoll CR ADDIS LL_ADC_Disable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADDIS); +} + +/** + * @brief Get the selected ADC instance enable state. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @rmtoll CR ADEN LL_ADC_IsEnabled + * @param ADCx ADC instance + * @retval 0: ADC is disabled, 1: ADC is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the selected ADC instance disable state. + * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing + * @param ADCx ADC instance + * @retval 0: no ADC disable command on going. + */ +__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); +} + +/** + * @brief Start ADC calibration in the mode single-ended + * or differential (for devices with differential mode available). + * @note On this STM32 series, a minimum number of ADC clock cycles + * are required between ADC end of calibration and ADC enable. + * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. + * @note For devices with differential mode available: + * Calibration of offset is specific to each of + * single-ended and differential modes + * (calibration run must be performed for each of these + * differential modes, if used afterwards and if the application + * requires their calibration). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @rmtoll CR ADCAL LL_ADC_StartCalibration\n + * CR ADCALDIF LL_ADC_StartCalibration + * @param ADCx ADC instance + * @param SingleDiff This parameter can be one of the following values: + * @arg @ref LL_ADC_SINGLE_ENDED + * @arg @ref LL_ADC_DIFFERENTIAL_ENDED + * @retval None + */ +__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK)); +} + +/** + * @brief Get ADC calibration state. + * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing + * @param ADCx ADC instance + * @retval 0: calibration complete, 1: calibration in progress. + */ +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Start ADC group regular conversion. + * @note On this STM32 series, this function is relevant for both + * internal trigger (SW start) and external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * will start at next trigger event (on the selected trigger edge) + * following the ADC start conversion command. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled without conversion on going on group regular, + * without conversion stop command on going on group regular, + * without ADC disable command on going. + * @rmtoll CR ADSTART LL_ADC_REG_StartConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADSTART); +} + +/** + * @brief Stop ADC group regular conversion. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled with conversion on going on group regular, + * without ADC disable command on going. + * @rmtoll CR ADSTP LL_ADC_REG_StopConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADSTP); +} + +/** + * @brief Get ADC group regular conversion state. + * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing + * @param ADCx ADC instance + * @retval 0: no conversion is on going on ADC group regular. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); +} + +/** + * @brief Get ADC group regular command of conversion stop state + * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing + * @param ADCx ADC instance + * @retval 0: no command of conversion stop is on going on ADC group regular. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); +} + +/** + * @brief Start ADC sampling phase for sampling time trigger mode + * @note This function is relevant only when + * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set + * using @ref LL_ADC_REG_SetSamplingMode + * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled without conversion on going on group regular, + * without conversion stop command on going on group regular, + * without ADC disable command on going. + * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG); +} + +/** + * @brief Stop ADC sampling phase for sampling time trigger mode and start conversion + * @note This function is relevant only when + * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set + * using @ref LL_ADC_REG_SetSamplingMode + * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source + * - @ref LL_ADC_REG_StartSamplingPhase has been called to start + * the sampling phase + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled without conversion on going on group regular, + * without conversion stop command on going on group regular, + * without ADC disable command on going. + * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 10 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 8 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) +{ + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 6 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx) +{ + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Get ADC multimode conversion data of ADC master, ADC slave + * or raw data with ADC master and slave concatenated. + * @note If raw data with ADC master and slave concatenated is retrieved, + * a macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * (however this macro is mainly intended for multimode + * transfer by DMA, because this function can do the same + * by getting multimode conversion data of ADC master or ADC slave + * separately). + * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n + * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param ConversionData This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @arg @ref LL_ADC_MULTI_MASTER_SLAVE + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON, + uint32_t ConversionData) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, + ConversionData) + >> (POSITION_VAL(ConversionData) & 0x1FUL) + ); +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected + * @{ + */ + +/** + * @brief Start ADC group injected conversion. + * @note On this STM32 series, this function is relevant for both + * internal trigger (SW start) and external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * will start at next trigger event (on the selected trigger edge) + * following the ADC start conversion command. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled without conversion on going on group injected, + * without conversion stop command on going on group injected, + * without ADC disable command on going. + * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_JADSTART); +} + +/** + * @brief Stop ADC group injected conversion. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled with conversion on going on group injected, + * without ADC disable command on going. + * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_JADSTP); +} + +/** + * @brief Get ADC group injected conversion state. + * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing + * @param ADCx ADC instance + * @retval 0: no conversion is on going on ADC group injected. + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); +} + +/** + * @brief Get ADC group injected command of conversion stop state + * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing + * @param ADCx ADC instance + * @retval 0: no command of conversion stop is on going on ADC group injected. + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank) +{ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, + ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + + return (uint32_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank) +{ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, + ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + + return (uint16_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 10 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank) +{ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, + ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + + return (uint16_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 8 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank) +{ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, + ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + + return (uint8_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 6 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData6 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank) +{ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, + ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + + return (uint8_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management + * @{ + */ + +/** + * @brief Get flag ADC ready. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular end of unitary conversion. + * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular end of sequence conversions. + * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular overrun. + * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular end of sampling phase. + * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group injected end of unitary conversion. + * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group injected end of sequence conversions. + * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group injected contexts queue overflow. + * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC analog watchdog 1 flag + * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC analog watchdog 2. + * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC analog watchdog 3. + * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); +} + +/** + * @brief Clear flag ADC ready. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY); +} + +/** + * @brief Clear flag ADC group regular end of unitary conversion. + * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC); +} + +/** + * @brief Clear flag ADC group regular end of sequence conversions. + * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS); +} + +/** + * @brief Clear flag ADC group regular overrun. + * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR); +} + +/** + * @brief Clear flag ADC group regular end of sampling phase. + * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP); +} + +/** + * @brief Clear flag ADC group injected end of unitary conversion. + * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC); +} + +/** + * @brief Clear flag ADC group injected end of sequence conversions. + * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS); +} + +/** + * @brief Clear flag ADC group injected contexts queue overflow. + * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF); +} + +/** + * @brief Clear flag ADC analog watchdog 1. + * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1); +} + +/** + * @brief Clear flag ADC analog watchdog 2. + * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2); +} + +/** + * @brief Clear flag ADC analog watchdog 3. + * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3); +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Get flag multimode ADC ready of the ADC master. + * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC ready of the ADC slave. + * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master. + * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave. + * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master. + * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave. + * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular overrun of the ADC master. + * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular overrun of the ADC slave. + * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular end of sampling of the ADC master. + * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group regular end of sampling of the ADC slave. + * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master. + * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave. + * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. + * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave. + * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group injected context queue overflow of the ADC master. + * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave. + * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. + * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode analog watchdog 1 of the ADC slave. + * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC analog watchdog 2 of the ADC master. + * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave. + * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC analog watchdog 3 of the ADC master. + * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL); +} + +/** + * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave. + * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL); +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_IT_Management ADC IT management + * @{ + */ + +/** + * @brief Enable ADC ready. + * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY); +} + +/** + * @brief Enable interruption ADC group regular end of unitary conversion. + * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOC); +} + +/** + * @brief Enable interruption ADC group regular end of sequence conversions. + * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOS); +} + +/** + * @brief Enable ADC group regular interruption overrun. + * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_OVR); +} + +/** + * @brief Enable interruption ADC group regular end of sampling. + * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP); +} + +/** + * @brief Enable interruption ADC group injected end of unitary conversion. + * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_JEOC); +} + +/** + * @brief Enable interruption ADC group injected end of sequence conversions. + * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_JEOS); +} + +/** + * @brief Enable interruption ADC group injected context queue overflow. + * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF); +} + +/** + * @brief Enable interruption ADC analog watchdog 1. + * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_AWD1); +} + +/** + * @brief Enable interruption ADC analog watchdog 2. + * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_AWD2); +} + +/** + * @brief Enable interruption ADC analog watchdog 3. + * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_AWD3); +} + +/** + * @brief Disable interruption ADC ready. + * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY); +} + +/** + * @brief Disable interruption ADC group regular end of unitary conversion. + * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC); +} + +/** + * @brief Disable interruption ADC group regular end of sequence conversions. + * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS); +} + +/** + * @brief Disable interruption ADC group regular overrun. + * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR); +} + +/** + * @brief Disable interruption ADC group regular end of sampling. + * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP); +} + +/** + * @brief Disable interruption ADC group regular end of unitary conversion. + * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC); +} + +/** + * @brief Disable interruption ADC group injected end of sequence conversions. + * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS); +} + +/** + * @brief Disable interruption ADC group injected context queue overflow. + * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF); +} + +/** + * @brief Disable interruption ADC analog watchdog 1. + * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1); +} + +/** + * @brief Disable interruption ADC analog watchdog 2. + * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2); +} + +/** + * @brief Disable interruption ADC analog watchdog 3. + * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3); +} + +/** + * @brief Get state of interruption ADC ready + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular end of unitary conversion + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular end of sequence conversions + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular overrun + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular end of sampling + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group injected end of unitary conversion + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group injected end of sequence conversions + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group injected context queue overflow interrupt state + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC analog watchdog 1 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption Get ADC analog watchdog 2 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption Get ADC analog watchdog 3 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +/* Initialization of some features of ADC common parameters and multimode */ +ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); + +/* De-initialization of ADC instance, ADC group regular and ADC group injected */ +/* (availability of ADC group injected depends on STM32 series) */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); + +/* Initialization of some features of ADC instance */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct); +void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct); + +/* Initialization of some features of ADC instance and ADC group regular */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); + +/* Initialization of some features of ADC instance and ADC group injected */ +ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct); +void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 || ADC2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_ADC_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_bus.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_bus.h new file mode 100644 index 00000000000..728d609f027 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_bus.h @@ -0,0 +1,2734 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_BUS_H +#define STM32H7RSxx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN +#define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN +#define LL_AHB1_GRP1_PERIPH_ETH1MAC RCC_AHB1ENR_ETH1MACEN +#define LL_AHB1_GRP1_PERIPH_ETH1TX RCC_AHB1ENR_ETH1TXEN +#define LL_AHB1_GRP1_PERIPH_ETH1RX RCC_AHB1ENR_ETH1RXEN +#define LL_AHB1_GRP1_PERIPH_USBOTGHS RCC_AHB1ENR_OTGHSEN +#define LL_AHB1_GRP1_PERIPH_USBOTGFS RCC_AHB1ENR_OTGFSEN +#define LL_AHB1_GRP1_PERIPH_USBPHYC RCC_AHB1ENR_USBPHYCEN +#define LL_AHB1_GRP1_PERIPH_ADF1 RCC_AHB1ENR_ADF1EN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_PSSI RCC_AHB2ENR_PSSIEN +#define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN +#define LL_AHB2_GRP1_PERIPH_CORDIC RCC_AHB2ENR_CORDICEN +#define LL_AHB2_GRP1_PERIPH_AHBSRAM1 RCC_AHB2ENR_SRAM1EN +#define LL_AHB2_GRP1_PERIPH_AHBSRAM2 RCC_AHB2ENR_SRAM2EN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + * @{ + */ +#define LL_AHB3_GRP1_PERIPH_RNG RCC_AHB3ENR_RNGEN +#define LL_AHB3_GRP1_PERIPH_HASH RCC_AHB3ENR_HASHEN +#if defined(CRYP) +#define LL_AHB3_GRP1_PERIPH_CRYP RCC_AHB3ENR_CRYPEN +#endif /* CRYP */ +#if defined(SAES) +#define LL_AHB3_GRP1_PERIPH_SAES RCC_AHB3ENR_SAESEN +#endif /* SAES */ +#define LL_AHB3_GRP1_PERIPH_PKA RCC_AHB3ENR_PKAEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH + * @{ + */ +#define LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN +#define LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN +#define LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN +#define LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN +#define LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN +#define LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN +#define LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN +#define LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN +#define LL_AHB4_GRP1_PERIPH_GPIOM RCC_AHB4ENR_GPIOMEN +#define LL_AHB4_GRP1_PERIPH_GPION RCC_AHB4ENR_GPIONEN +#define LL_AHB4_GRP1_PERIPH_GPIOO RCC_AHB4ENR_GPIOOEN +#define LL_AHB4_GRP1_PERIPH_GPIOP RCC_AHB4ENR_GPIOPEN +#define LL_AHB4_GRP1_PERIPH_CRC RCC_AHB4ENR_CRCEN +#define LL_AHB4_GRP1_PERIPH_BKPRAM RCC_AHB4ENR_BKPRAMEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB5_GRP1_PERIPH AHB5 GRP1 PERIPH + * @{ + */ +#define LL_AHB5_GRP1_PERIPH_HPDMA1 RCC_AHB5ENR_HPDMA1EN +#define LL_AHB5_GRP1_PERIPH_DMA2D RCC_AHB5ENR_DMA2DEN +#define LL_AHB5_GRP1_PERIPH_JPEG RCC_AHB5ENR_JPEGEN +#define LL_AHB5_GRP1_PERIPH_FMC RCC_AHB5ENR_FMCEN +#define LL_AHB5_GRP1_PERIPH_XSPI1 RCC_AHB5ENR_XSPI1EN +#define LL_AHB5_GRP1_PERIPH_XSPI2 RCC_AHB5ENR_XSPI2EN +#define LL_AHB5_GRP1_PERIPH_XSPIM RCC_AHB5ENR_XSPIMEN +#define LL_AHB5_GRP1_PERIPH_SDMMC1 RCC_AHB5ENR_SDMMC1EN +#define LL_AHB5_GRP1_PERIPH_GFXMMU RCC_AHB5ENR_GFXMMUEN +#if defined(GPU2D) +#define LL_AHB5_GRP1_PERIPH_GPU2D RCC_AHB5ENR_GPU2DEN +#endif /* GPU2D */ + +#define LL_AHB5_GRP1_PERIPH_FLASH RCC_AHB5LPENR_FLASHLPEN +#define LL_AHB5_GRP1_PERIPH_AXISRAM RCC_AHB5LPENR_AXISRAMLPEN +#define LL_AHB5_GRP1_PERIPH_DTCM1 RCC_AHB5LPENR_DTCM1LPEN +#define LL_AHB5_GRP1_PERIPH_DTCM2 RCC_AHB5LPENR_DTCM2LPEN +#define LL_AHB5_GRP1_PERIPH_ITCM RCC_AHB5LPENR_ITCMLPEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN +#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR1_TIM12EN +#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR1_TIM13EN +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR1_TIM14EN +#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN +#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR1_SPDIFRXEN +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1_I3C1EN +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN +#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN +#define LL_APB1_GRP1_PERIPH_I3C1 RCC_APB1ENR1_I2C1_I3C1EN +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR1_CECEN +#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR1_UART7EN +#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR1_UART8EN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#define LL_APB1_GRP2_PERIPH_CRS RCC_APB1ENR2_CRSEN +#define LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1ENR2_MDIOSEN +#define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1ENR2_FDCANEN +#define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN +#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN +#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN +#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN +#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH APB4 GRP1 PERIPH + * @{ + */ +#define LL_APB4_GRP1_PERIPH_SBS RCC_APB4ENR_SBSEN +#define LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR_LPUART1EN +#define LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR_SPI6EN +#define LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR_LPTIM2EN +#define LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR_LPTIM3EN +#define LL_APB4_GRP1_PERIPH_LPTIM4 RCC_APB4ENR_LPTIM4EN +#define LL_APB4_GRP1_PERIPH_LPTIM5 RCC_APB4ENR_LPTIM5EN +#define LL_APB4_GRP1_PERIPH_VREF RCC_APB4ENR_VREFEN +#define LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR_RTCAPBEN +#define LL_APB4_GRP1_PERIPH_DTS RCC_APB4ENR_DTSEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB5_GRP1_PERIPH APB5 GRP1 PERIPH + * @{ + */ +#if defined(LTDC) +#define LL_APB5_GRP1_PERIPH_LTDC RCC_APB5ENR_LTDCEN +#endif /* LTDC */ +#define LL_APB5_GRP1_PERIPH_DCMIPP RCC_APB5ENR_DCMIPPEN +#define LL_APB5_GRP1_PERIPH_GFXTIM RCC_APB5ENR_GFXTIMEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_CKGA_PERIPH CKGA (AXI Clocks Gating) PERIPH + * @{ + */ +#define LL_CKGA_PERIPH_AXI RCC_CKGDISR_AXICKG +#define LL_CKGA_PERIPH_AHBM RCC_CKGDISR_AHBMCKG +#define LL_CKGA_PERIPH_SDMMC1 RCC_CKGDISR_SDMMC1CKG +#define LL_CKGA_PERIPH_HPDMA1 RCC_CKGDISR_HPDMA1CKG +#define LL_CKGA_PERIPH_CPU RCC_CKGDISR_CPUCKG +#if defined(GPU2D) +#define LL_CKGA_PERIPH_GPU2DS1 RCC_CKGDISR_GPU2DS1CKG +#define LL_CKGA_PERIPH_GPU2DS0 RCC_CKGDISR_GPU2DS0CKG +#define LL_CKGA_PERIPH_GPU2DCL RCC_CKGDISR_GPU2DCLCKG +#endif /* GPU2D */ +#define LL_CKGA_PERIPH_DCMIPP RCC_CKGDISR_DCMIPPCKG +#define LL_CKGA_PERIPH_DMA2D RCC_CKGDISR_DMA2DCKG +#define LL_CKGA_PERIPH_GFXMMUS RCC_CKGDISR_GFXMMUSCKG +#if defined(LTDC) +#define LL_CKGA_PERIPH_LTDC RCC_CKGDISR_LTDCCKG +#endif /* LTDC */ +#define LL_CKGA_PERIPH_GFXMMUM RCC_CKGDISR_GFXMMUMCKG +#define LL_CKGA_PERIPH_AHBS RCC_CKGDISR_AHBSCKG +#define LL_CKGA_PERIPH_FMC RCC_CKGDISR_FMCCKG +#define LL_CKGA_PERIPH_XSPI1 RCC_CKGDISR_XSPI1CKG +#define LL_CKGA_PERIPH_XSPI2 RCC_CKGDISR_XSPI2CKG +#define LL_CKGA_PERIPH_AXIRAM1 RCC_CKGDISR_AXISRAM1CKG +#define LL_CKGA_PERIPH_AXIRAM2 RCC_CKGDISR_AXISRAM2CKG +#define LL_CKGA_PERIPH_AXIRAM3 RCC_CKGDISR_AXISRAM3CKG +#define LL_CKGA_PERIPH_AXIRAM4 RCC_CKGDISR_AXISRAM4CKG +#define LL_CKGA_PERIPH_FLASH RCC_CKGDISR_FLASHCKG +#define LL_CKGA_PERIPH_EXTI RCC_CKGDISR_EXTICKG +#define LL_CKGA_PERIPH_JTAG RCC_CKGDISR_JTAGCKG +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ADC12EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETH1MACEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETH1TXEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETH1RXEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR OTGFSEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR USBPHYCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ADF1EN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX + * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGFS + * @arg @ref LL_AHB1_GRP1_PERIPH_USBPHYC + * @arg @ref LL_AHB1_GRP1_PERIPH_ADF1 + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETH1MACEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETH1TXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETH1RXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USBPHYCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ADF1EN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX + * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGFS + * @arg @ref LL_AHB1_GRP1_PERIPH_USBPHYC + * @arg @ref LL_AHB1_GRP1_PERIPH_ADF1 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ADC12EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETH1MACEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETH1TXEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETH1RXEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR OTGFSEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR USBPHYCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ADF1EN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX + * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGFS + * @arg @ref LL_AHB1_GRP1_PERIPH_USBPHYC + * @arg @ref LL_AHB1_GRP1_PERIPH_ADF1 + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1ENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPDMA1RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR ADC12RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR ETH1RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR OTGFSRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR USBPHYCRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR ADF1RST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC + * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGFS + * @arg @ref LL_AHB1_GRP1_PERIPH_USBPHYC + * @arg @ref LL_AHB1_GRP1_PERIPH_ADF1 + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPDMA1RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR ETH1RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR USBPHYCRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR ADF1RST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC + * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGFS + * @arg @ref LL_AHB1_GRP1_PERIPH_USBPHYC + * @arg @ref LL_AHB1_GRP1_PERIPH_ADF1 + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR GPDMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR OTGFSLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USBPHYCLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ADF1LPEN LL_AHB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX + * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGFS + * @arg @ref LL_AHB1_GRP1_PERIPH_USBPHYC + * @arg @ref LL_AHB1_GRP1_PERIPH_ADF1 + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR GPDMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USBPHYCLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ADF1LPEN LL_AHB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX + * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USBOTGFS + * @arg @ref LL_AHB1_GRP1_PERIPH_USBPHYC + * @arg @ref LL_AHB1_GRP1_PERIPH_ADF1 + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENR PSSIEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR SDMMC2EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR CORDICEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR AHBSRAM1EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR AHBSRAM2EN LL_AHB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_PSSI + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM2 + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR PSSIEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR CORDICEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR AHBSRAM1EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR AHBSRAM2EN LL_AHB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_PSSI + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM2 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENR PSSIEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR SDMMC2EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR CORDICEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR AHBSRAM1EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR AHBSRAM2EN LL_AHB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_PSSI + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM2 + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2ENR, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RSTR PSSIRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR CORDICRST LL_AHB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_PSSI + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RSTR PSSIRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR CORDICRST LL_AHB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_PSSI + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR PSSILPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR CORDICLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR AHBSRAM1LPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR AHBSRAM2LPEN LL_AHB2_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_PSSI + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM2 + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR PSSILPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR CORDICLPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR AHBSRAM1LPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR AHBSRAM2LPEN LL_AHB2_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_PSSI + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC + * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_AHBSRAM2 + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable AHB3 peripherals clock. + * @rmtoll AHB3ENR RNGEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR HASHEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR CRYPEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR SAESEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR PKAEN LL_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HASH + * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR RNGEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR HASHEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR CRYPEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR SAESEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR PKAEN LL_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HASH + * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * + * (*) value not defined in all devices. + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB3 peripherals clock. + * @rmtoll AHB3ENR RNGEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR HASHEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR CRYPEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR SAESEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR PKAEN LL_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HASH + * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3ENR, Periphs); +} + +/** + * @brief Enable AHB3 peripherals clock. + * @rmtoll AHB3RSTR RNGRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR HASHRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR CRYPRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR SAESRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR PKARST LL_AHB3_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HASH + * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Release AHB3 peripherals reset. + * @rmtoll AHB3RSTR RNGRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR HASHRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR CRYPRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR SAESRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR PKARST LL_AHB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HASH + * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Enable AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR RNGLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR HASHLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR CRYPLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR SAESLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR PKALPEN LL_AHB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HASH + * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR RNGLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR HASHLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR CRYPLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR SAESLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR PKALPEN LL_AHB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_RNG + * @arg @ref LL_AHB3_GRP1_PERIPH_HASH + * @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_PKA + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB4 AHB4 + * @{ + */ + +/** + * @brief Enable AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOBEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOCEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIODEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOEEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOFEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOGEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOHEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOMEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIONEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOOEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOPEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR CRCEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR BKPRAMEN LL_AHB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOM + * @arg @ref LL_AHB4_GRP1_PERIPH_GPION + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB4 peripheral clock is enabled or not + * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOBEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOCEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIODEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOEEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOFEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOGEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOHEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOMEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIONEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOOEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOPEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR CRCEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR BKPRAMEN LL_AHB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOM + * @arg @ref LL_AHB4_GRP1_PERIPH_GPION + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOBEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOCEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIODEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOEEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOFEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOGEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOHEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOMEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIONEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOOEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOPEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR CRCEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR BKPRAMEN LL_AHB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOM + * @arg @ref LL_AHB4_GRP1_PERIPH_GPION + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4ENR, Periphs); +} + +/** + * @brief Force AHB4 peripherals reset. + * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIODRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOERST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOMRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIONRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOORST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOPRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR CRCRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR BKPRAMRST LL_AHB4_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOM + * @arg @ref LL_AHB4_GRP1_PERIPH_GPION + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB4RSTR, Periphs); +} + +/** + * @brief Release AHB4 peripherals reset. + * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIODRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOERST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOMRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIONRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOORST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOPRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR CRCRST LL_AHB4_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOM + * @arg @ref LL_AHB4_GRP1_PERIPH_GPION + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4RSTR, Periphs); +} + +/** + * @brief Enable AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOMLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIONLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOOLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOPLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR CRCLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOM + * @arg @ref LL_AHB4_GRP1_PERIPH_GPION + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOMLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIONLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOOLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOPLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR CRCLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOM + * @arg @ref LL_AHB4_GRP1_PERIPH_GPION + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB5 AHB5 + * @{ + */ + +/** + * @brief Enable AHB5 peripherals clock. + * @rmtoll AHB5ENR HPDMA1EN LL_AHB5_GRP1_EnableClock\n + * AHB5ENR DMA2DEN LL_AHB5_GRP1_EnableClock\n + * AHB5ENR JPEGEN LL_AHB5_GRP1_EnableClock\n + * AHB5ENR FMCEN LL_AHB5_GRP1_EnableClock\n + * AHB5ENR XSPI1EN LL_AHB5_GRP1_EnableClock\n + * AHB5ENR XSPI2EN LL_AHB5_GRP1_EnableClock\n + * AHB5ENR XSPIMEN LL_AHB5_GRP1_EnableClock\n + * AHB5ENR SDMMC1EN LL_AHB5_GRP1_EnableClock\n + * AHB5ENR GFXMMUEN LL_AHB5_GRP1_EnableClock\n + * AHB5ENR GPU2DEN LL_AHB5_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_FMC + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB5ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB5ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB5 peripheral clock is enabled or not + * @rmtoll AHB5ENR HPDMA1EN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR DMA2DEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR JPEGEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR FMCEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR XSPI1EN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR XSPI2EN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR XSPIMEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR SDMMC1EN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR GFXMMUEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR GPU2DEN LL_AHB5_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_FMC + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D (*) + * + * (*) value not defined in all devices. + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB5ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB5 peripherals clock. + * @rmtoll AHB5ENR HPDMA1EN LL_AHB5_GRP1_DisableClock\n + * AHB5ENR DMA2DEN LL_AHB5_GRP1_DisableClock\n + * AHB5ENR JPEGEN LL_AHB5_GRP1_DisableClock\n + * AHB5ENR FMCEN LL_AHB5_GRP1_DisableClock\n + * AHB5ENR XSPI1EN LL_AHB5_GRP1_DisableClock\n + * AHB5ENR XSPI2EN LL_AHB5_GRP1_DisableClock\n + * AHB5ENR XSPIMEN LL_AHB5_GRP1_DisableClock\n + * AHB5ENR SDMMC1EN LL_AHB5_GRP1_DisableClock\n + * AHB5ENR GFXMMUEN LL_AHB5_GRP1_DisableClock\n + * AHB5ENR GPU2DEN LL_AHB5_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_FMC + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB5ENR, Periphs); +} + +/** + * @brief Force AHB5 peripherals reset. + * @rmtoll AHB5RSTR HPDMA1RST LL_AHB5_GRP1_ForceReset\n + * AHB5RSTR DMA2DRST LL_AHB5_GRP1_ForceReset\n + * AHB5RSTR JPEGRST LL_AHB5_GRP1_ForceReset\n + * AHB5RSTR FMCRST LL_AHB5_GRP1_ForceReset\n + * AHB5RSTR XSPI1RST LL_AHB5_GRP1_ForceReset\n + * AHB5RSTR XSPI2RST LL_AHB5_GRP1_ForceReset\n + * AHB5RSTR XSPIMRST LL_AHB5_GRP1_ForceReset\n + * AHB5RSTR SDMMC1RST LL_AHB5_GRP1_ForceReset\n + * AHB5RSTR GFXMMURST LL_AHB5_GRP1_ForceReset\n + * AHB5RSTR GPU2DRST LL_AHB5_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_FMC + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB5RSTR, Periphs); +} + +/** + * @brief Release AHB5 peripherals reset. + * @rmtoll AHB5RSTR HPDMA1RST LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTR DMA2DRST LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTR JPEGRST LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTR FMCRST LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTR XSPI1RST LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTR XSPI2RST LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTR XSPIMRST LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTR SDMMC1RST LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTR GFXMMURST LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTR GPU2DRST LL_AHB5_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_FMC + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB5RSTR, Periphs); +} + +/** + * @brief Enable AHB5 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB5LPENR HPDMA1LPEN LL_AHB5_GRP1_EnableClockSleep\n + * AHB5LPENR DMA2DLPEN LL_AHB5_GRP1_EnableClockSleep\n + * AHB5LPENR JPEGLPEN LL_AHB5_GRP1_EnableClockSleep\n + * AHB5LPENR FMCLPEN LL_AHB5_GRP1_EnableClockSleep\n + * AHB5LPENR XSPI1LPEN LL_AHB5_GRP1_EnableClockSleep\n + * AHB5LPENR XSPI2LPEN LL_AHB5_GRP1_EnableClockSleep\n + * AHB5LPENR XSPIMLPEN LL_AHB5_GRP1_EnableClockSleep\n + * AHB5LPENR SDMMC1LPEN LL_AHB5_GRP1_EnableClockSleep\n + * AHB5LPENR GFXMMULPEN LL_AHB5_GRP1_EnableClockSleep\n + * AHB5LPENR GPU2DLPEN LL_AHB5_GRP1_EnableClockSleep\n + * AHB5LPENR AXISRAMPLEN LL_AHB5_GRP1_EnableClockSleep\n + * AHB5LPENR DTCM1PLEN LL_AHB5_GRP1_EnableClockSleep\n + * AHB5LPENR DTCM2PLEN LL_AHB5_GRP1_EnableClockSleep\n + * AHB5LPENR ITCMPLEN LL_AHB5_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB5_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_FMC + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_AXISRAM + * @arg @ref LL_AHB5_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB5_GRP1_PERIPH_ITCM + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB5LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB5LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB5 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB5LPENR HPDMA1LPEN LL_AHB5_GRP1_DisableClockSleep\n + * AHB5LPENR DMA2DLPEN LL_AHB5_GRP1_DisableClockSleep\n + * AHB5LPENR FLASHLPEN LL_AHB5_GRP1_DisableClockSleep\n + * AHB5LPENR JPEGLPEN LL_AHB5_GRP1_DisableClockSleep\n + * AHB5LPENR FMCLPEN LL_AHB5_GRP1_DisableClockSleep\n + * AHB5LPENR XSPI1LPEN LL_AHB5_GRP1_DisableClockSleep\n + * AHB5LPENR XSPI2LPEN LL_AHB5_GRP1_DisableClockSleep\n + * AHB5LPENR XSPIMLPEN LL_AHB5_GRP1_DisableClockSleep\n + * AHB5LPENR SDMMC1LPEN LL_AHB5_GRP1_DisableClockSleep\n + * AHB5LPENR GFXMMULPEN LL_AHB5_GRP1_DisableClockSleep\n + * AHB5LPENR GPU2DLPEN LL_AHB5_GRP1_DisableClockSleep\n + * AHB5LPENR AXISRAMPLEN LL_AHB5_GRP1_DisableClockSleep\n + * AHB5LPENR DTCM1PLEN LL_AHB5_GRP1_DisableClockSleep\n + * AHB5LPENR DTCM2PLEN LL_AHB5_GRP1_DisableClockSleep\n + * AHB5LPENR ITCMPLEN LL_AHB5_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB5_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB5_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_FMC + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2 + * @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM + * @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D (*) + * @arg @ref LL_AHB5_GRP1_PERIPH_AXISRAM + * @arg @ref LL_AHB5_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB5_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB5_GRP1_PERIPH_ITCM + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB5LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM12EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM13EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 SPDIFRXEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 I3C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 CECEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 UART7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 UART8EN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM13EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I3C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 CECEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 UART7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 UART8EN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM12EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM13EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM14EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 SPDIFRXEN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 I3C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 CECEN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 UART7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 UART8EN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR1, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM12RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM13RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM14RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 WWDGRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 SPDIFRXRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 I3C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 CECRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 UART7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 UART8RST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR1, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM12RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM13RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM14RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 WWDGRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 I3C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 CECRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 UART7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 UART8RST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR1, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LPENR1 TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 TIM12LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 TIM13LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 TIM14LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 LPTIM1LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 WWDGLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 SPDIFRXLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 USART2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 USART3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 UART4LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 UART5LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 I2C3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 I3C1LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 CECLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 DAC12LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 UART7LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR1 UART8LPEN LL_APB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LPENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LPENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LPENR1 TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 TIM12LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 TIM13LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 TIM14LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 LPTIM1LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 WWDGLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 SPDIFRXLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 USART2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 USART3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 UART4LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 UART5LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 I2C3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 I3C1LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 CECLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 UART7LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR1 UART8LPEN LL_APB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I3C1 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LPENR1, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR2 CRSEN LL_APB1_GRP2_EnableClock\n + * APB1ENR2 MDIOSEN LL_APB1_GRP2_EnableClock\n + * APB1ENR2 FDCANEN LL_APB1_GRP2_EnableClock\n + * APB1ENR2 UCPD1EN LL_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR2 CRSEN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 MDIOSEN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 FDCANEN LL_APB1_GRP2_IsEnabledClock\n + * APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR2 CRSEN LL_APB1_GRP2_DisableClock\n + * APB1ENR2 MDIOSEN LL_APB1_GRP2_DisableClock\n + * APB1ENR2 FDCANEN LL_APB1_GRP2_DisableClock\n + * APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR2, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR2 CRSRST LL_APB1_GRP2_ForceReset\n + * APB1ENR2 MDIOSRST LL_APB1_GRP2_ForceReset\n + * APB1ENR2 FDCANRST LL_APB1_GRP2_ForceReset\n + * APB1ENR2 UCPD1RST LL_APB1_GRP2_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR2, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR2 CRSRST LL_APB1_GRP2_ReleaseReset\n + * APB1ENR2 MDIOSRST LL_APB1_GRP2_ReleaseReset\n + * APB1ENR2 FDCANRST LL_APB1_GRP2_ReleaseReset\n + * APB1ENR2 UCPD1RST LL_APB1_GRP2_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR2, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LPENR2 CRSLPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1LPENR2 MDIOSLPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1LPENR2 FDCANLPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1LPENR2 UCPD1LPEN LL_APB1_GRP2_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LPENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LPENR2, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LPENR2 CRSLPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1LPENR2 MDIOSLPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1LPENR2 FDCANLPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1LPENR2 UCPD1LPEN LL_APB1_GRP2_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LPENR2, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB4 APB4 + * @{ + */ + +/** + * @brief Enable APB4 peripherals clock. + * @rmtoll APB4ENR SBSEN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPUART1EN LL_APB4_GRP1_EnableClock\n + * APB4ENR SPI6EN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM2EN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM3EN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM4EN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM5EN LL_APB4_GRP1_EnableClock\n + * APB4ENR VREFEN LL_APB4_GRP1_EnableClock\n + * APB4ENR RTCAPBEN LL_APB4_GRP1_EnableClock\n + * APB4ENR DTSEN LL_APB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SBS + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_DTS + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB4 peripheral clock is enabled or not + * @rmtoll APB4ENR SBSEN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPUART1EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR SPI6EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM2EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM3EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM4EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM5EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR VREFEN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR RTCAPBEN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR DTSEN LL_APB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SBS + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_DTS + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB4 peripherals clock. + * @rmtoll APB4ENR SBSEN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPUART1EN LL_APB4_GRP1_DisableClock\n + * APB4ENR SPI6EN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM2EN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM3EN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM4EN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM5EN LL_APB4_GRP1_DisableClock\n + * APB4ENR VREFEN LL_APB4_GRP1_DisableClock\n + * APB4ENR RTCAPBEN LL_APB4_GRP1_DisableClock\n + * APB4ENR DTSEN LL_APB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SBS + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_DTS + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB4ENR, Periphs); +} + +/** + * @brief Force APB4 peripherals reset. + * @rmtoll APB4RSTR SBSRST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPUART1RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR SPI6RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPTIM2RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPTIM3RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPTIM4RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPTIM5RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR VREFRST LL_APB4_GRP1_ForceReset\n + * APB4RSTR DTSRST LL_APB4_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SBS + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_DTS + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB4RSTR, Periphs); +} + +/** + * @brief Release APB4 peripherals reset. + * @rmtoll APB4RSTR SBSRST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPUART1RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR SPI6RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPTIM2RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPTIM3RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPTIM4RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPTIM5RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR VREFRST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR DTSRST LL_APB4_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SBS + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_DTS + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB4RSTR, Periphs); +} + +/** + * @brief Enable APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SBSLPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPUART1LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SPI6LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR VREFLPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR DTSLPEN LL_APB4_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SBS + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_DTS + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SBSLPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPUART1LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SPI6LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR VREFLPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR DTSLPEN LL_APB4_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SBS + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_DTS + * @retval None + */ +__STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB5 APB5 + * @{ + */ + +/** + * @brief Enable APB5 peripherals clock. + * @rmtoll APB5ENR LTDCEN LL_APB5_GRP1_EnableClock\n + * APB5ENR DCMIPPEN LL_APB5_GRP1_EnableClock\n + * APB5ENR GFXTIMEN LL_APB5_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB5_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP + * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB5_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB5ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB5ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB5 peripheral clock is enabled or not + * @rmtoll APB5ENR LTDCEN LL_APB5_GRP1_IsEnabledClock\n + * APB5ENR DCMIPPEN LL_APB5_GRP1_IsEnabledClock\n + * APB5ENR GFXTIMEN LL_APB5_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB5_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP + * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM + * + * (*) value not defined in all devices. + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_APB5_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB5ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB5 peripherals clock. + * @rmtoll APB5ENR LTDCEN LL_APB5_GRP1_DisableClock\n + * APB5ENR DCMIPPEN LL_APB5_GRP1_DisableClock\n + * APB5ENR GFXTIMEN LL_APB5_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB5_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP + * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB5_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB5ENR, Periphs); +} + +/** + * @brief Force APB5 peripherals reset. + * @rmtoll APB5RSTR LTDCRST LL_APB5_GRP1_ForceReset\n + * APB5RSTR DCMIPPRST LL_APB5_GRP1_ForceReset\n + * APB5RSTR GFXTIMRST LL_APB5_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB5_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP + * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB5_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB5RSTR, Periphs); +} + +/** + * @brief Release APB5 peripherals reset. + * @rmtoll APB5RSTR LTDCRST LL_APB5_GRP1_ReleaseReset\n + * APB5RSTR DCMIPPRST LL_APB5_GRP1_ForceReset\n + * APB5RSTR GFXTIMRST LL_APB5_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB5_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP + * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB5_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB5RSTR, Periphs); +} + +/** + * @brief Enable APB5 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB5LPENR LTDCLPEN LL_APB5_GRP1_EnableClockSleep\n + * APB5LPENR DCMIPPLPEN LL_APB5_GRP1_EnableClockSleep\n + * APB5LPENR GFXTIMLPEN LL_APB5_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB5_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP + * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB5_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB5LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB5LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB5 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB5LPENR LTDCLPEN LL_APB5_GRP1_DisableClockSleep\n + * APB5LPENR DCMIPPLPEN LL_APB5_GRP1_DisableClockSleep\n + * APB5LPENR GFXTIMLPEN LL_APB5_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB5_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP + * @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB5_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB5LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_CKGA CKGA (AXI Clocks Gating) + * @{ + */ + +/** + * @brief Enable clock gating for AXI bus peripherals. + * @rmtoll CKGDISR AXICKG LL_CKGA_Enable\n + * CKGDISR AHBMCKG LL_CKGA_Enable\n + * CKGDISR SDMMC1CKG LL_CKGA_Enable\n + * CKGDISR HPDMA1CKG LL_CKGA_Enable\n + * CKGDISR CPUCKG LL_CKGA_Enable\n + * CKGDISR GPU2DS0CKG LL_CKGA_Enable\n + * CKGDISR GPU2DS1CKG LL_CKGA_Enable\n + * CKGDISR GPUCLCKG LL_CKGA_Enable\n + * CKGDISR DCMIPPCKG LL_CKGA_Enable\n + * CKGDISR DMA2DCKG LL_CKGA_Enable\n + * CKGDISR GFXMMUSCKG LL_CKGA_Enable\n + * CKGDISR LTDCCKG LL_CKGA_Enable\n + * CKGDISR GFXMMUMCKG LL_CKGA_Enable\n + * CKGDISR AHBSCKG LL_CKGA_Enable\n + * CKGDISR FMCCKG LL_CKGA_Enable\n + * CKGDISR XSPI2CKG LL_CKGA_Enable\n + * CKGDISR XSPI1CKG LL_CKGA_Enable\n + * CKGDISR AXIRAM1CKG LL_CKGA_Enable\n + * CKGDISR AXIRAM2CKG LL_CKGA_Enable\n + * CKGDISR AXIRAM3CKG LL_CKGA_Enable\n + * CKGDISR AXIRAM4CKG LL_CKGA_Enable\n + * CKGDISR FLASHCKG LL_CKGA_Enable\n + * CKGDISR EXTICKG LL_CKGA_Enable\n + * CKGDISR JTAGCKG LL_CKGA_Enable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CKGA_PERIPH_AXI + * @arg @ref LL_CKGA_PERIPH_AHBM + * @arg @ref LL_CKGA_PERIPH_AHBS + * @arg @ref LL_CKGA_PERIPH_SDMMC1 + * @arg @ref LL_CKGA_PERIPH_HPDMA1 + * @arg @ref LL_CKGA_PERIPH_CPU + * @arg @ref LL_CKGA_PERIPH_GPU2DS0 (*) + * @arg @ref LL_CKGA_PERIPH_GPU2DS1 (*) + * @arg @ref LL_CKGA_PERIPH_GPU2DCL (*) + * @arg @ref LL_CKGA_PERIPH_DMA2D + * @arg @ref LL_CKGA_PERIPH_DCMIPP + * @arg @ref LL_CKGA_PERIPH_LTDC (*) + * @arg @ref LL_CKGA_PERIPH_FLASH + * @arg @ref LL_CKGA_PERIPH_XSPI2 + * @arg @ref LL_CKGA_PERIPH_XSPI1 + * @arg @ref LL_CKGA_PERIPH_FMC + * @arg @ref LL_CKGA_PERIPH_AXIRAM1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM2 + * @arg @ref LL_CKGA_PERIPH_AXIRAM3 + * @arg @ref LL_CKGA_PERIPH_AXIRAM4 + * @arg @ref LL_CKGA_PERIPH_GFXMMUM + * @arg @ref LL_CKGA_PERIPH_GFXMMUS + * @arg @ref LL_CKGA_PERIPH_EXTI + * @arg @ref LL_CKGA_PERIPH_JTAG + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs) +{ + CLEAR_BIT(RCC->CKGDISR, Periphs); +} + +/** + * @brief Check if AXI bus peripherals clock gating is enabled or not + * @rmtoll CKGDISR AXICKG LL_CKGA_IsEnabledClock\n + * CKGDISR AHBMCKG LL_CKGA_IsEnabledClock\n + * CKGDISR SDMMC1CKG LL_CKGA_IsEnabledClock\n + * CKGDISR HPDMA1CKG LL_CKGA_IsEnabledClock\n + * CKGDISR CPUCKG LL_CKGA_IsEnabledClock\n + * CKGDISR GPU2DS0CKG LL_CKGA_IsEnabledClock\n + * CKGDISR GPU2DS1CKG LL_CKGA_IsEnabledClock\n + * CKGDISR GPU2DCLCKG LL_CKGA_IsEnabledClock\n + * CKGDISR DCMIPPCKG LL_CKGA_IsEnabledClock\n + * CKGDISR DMA2DCKG LL_CKGA_IsEnabledClock\n + * CKGDISR GFXMMUSCKG LL_CKGA_IsEnabledClock\n + * CKGDISR LTDCCKG LL_CKGA_IsEnabledClock\n + * CKGDISR GFXMMUMCKG LL_CKGA_IsEnabledClock\n + * CKGDISR AHBSCKG LL_CKGA_IsEnabledClock\n + * CKGDISR FMCCKG LL_CKGA_IsEnabledClock\n + * CKGDISR XSPI2CKG LL_CKGA_IsEnabledClock\n + * CKGDISR XSPI1CKG LL_CKGA_IsEnabledClock\n + * CKGDISR AXIRAM1CKG LL_CKGA_IsEnabledClock\n + * CKGDISR AXIRAM2CKG LL_CKGA_IsEnabledClock\n + * CKGDISR AXIRAM3CKG LL_CKGA_IsEnabledClock\n + * CKGDISR AXIRAM4CKG LL_CKGA_IsEnabledClock\n + * CKGDISR FLASHCKG LL_CKGA_IsEnabledClock\n + * CKGDISR EXTICKG LL_CKGA_IsEnabledClock\n + * CKGDISR JTAGCKG LL_CKGA_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CKGA_PERIPH_AXI + * @arg @ref LL_CKGA_PERIPH_AHBM + * @arg @ref LL_CKGA_PERIPH_AHBS + * @arg @ref LL_CKGA_PERIPH_SDMMC1 + * @arg @ref LL_CKGA_PERIPH_HPDMA1 + * @arg @ref LL_CKGA_PERIPH_CPU + * @arg @ref LL_CKGA_PERIPH_GPU2DS0 (*) + * @arg @ref LL_CKGA_PERIPH_GPU2DS1 (*) + * @arg @ref LL_CKGA_PERIPH_GPU2DCL (*) + * @arg @ref LL_CKGA_PERIPH_DMA2D + * @arg @ref LL_CKGA_PERIPH_DCMIPP + * @arg @ref LL_CKGA_PERIPH_LTDC (*) + * @arg @ref LL_CKGA_PERIPH_FLASH + * @arg @ref LL_CKGA_PERIPH_XSPI2 + * @arg @ref LL_CKGA_PERIPH_XSPI1 + * @arg @ref LL_CKGA_PERIPH_FMC + * @arg @ref LL_CKGA_PERIPH_AXIRAM1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM2 + * @arg @ref LL_CKGA_PERIPH_AXIRAM3 + * @arg @ref LL_CKGA_PERIPH_AXIRAM4 + * @arg @ref LL_CKGA_PERIPH_GFXMMUM + * @arg @ref LL_CKGA_PERIPH_GFXMMUS + * @arg @ref LL_CKGA_PERIPH_EXTI + * @arg @ref LL_CKGA_PERIPH_JTAG + * + * (*) value not defined in all devices. + * @retval uint32_t + */ +__STATIC_INLINE uint32_t LL_CKGA_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->CKGDISR, Periphs) == 0U) ? 1U : 0U); +} + +/** + * @brief Disable clock gating for AXI bus peripherals. + * @rmtoll CKGDISR AXICKG LL_CKGA_Disable\n + * CKGDISR AHBMCKG LL_CKGA_Disable\n + * CKGDISR SDMMC1CKG LL_CKGA_Disable\n + * CKGDISR HPDMA1CKG LL_CKGA_Disable\n + * CKGDISR CPUCKG LL_CKGA_Disable\n + * CKGDISR GPU2DS0CKG LL_CKGA_Disable\n + * CKGDISR GPU2DS1CKG LL_CKGA_Disable\n + * CKGDISR GPUCLCKG LL_CKGA_Disable\n + * CKGDISR DCMIPPCKG LL_CKGA_Disable\n + * CKGDISR DMA2DCKG LL_CKGA_Disable\n + * CKGDISR GFXMMUSCKG LL_CKGA_Disable\n + * CKGDISR LTDCCKG LL_CKGA_Disable\n + * CKGDISR GFXMMUMCKG LL_CKGA_Disable\n + * CKGDISR AHBSCKG LL_CKGA_Disable\n + * CKGDISR FMCCKG LL_CKGA_Disable\n + * CKGDISR XSPI2CKG LL_CKGA_Disable\n + * CKGDISR XSPI1CKG LL_CKGA_Disable\n + * CKGDISR AXIRAM1CKG LL_CKGA_Disable\n + * CKGDISR AXIRAM2CKG LL_CKGA_Disable\n + * CKGDISR AXIRAM3CKG LL_CKGA_Disable\n + * CKGDISR AXIRAM4CKG LL_CKGA_Disable\n + * CKGDISR FLASHCKG LL_CKGA_Disable\n + * CKGDISR EXTICKG LL_CKGA_Disable\n + * CKGDISR JTAGCKG LL_CKGA_Disable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CKGA_PERIPH_AXI + * @arg @ref LL_CKGA_PERIPH_AHBM + * @arg @ref LL_CKGA_PERIPH_AHBS + * @arg @ref LL_CKGA_PERIPH_SDMMC1 + * @arg @ref LL_CKGA_PERIPH_HPDMA1 + * @arg @ref LL_CKGA_PERIPH_CPU + * @arg @ref LL_CKGA_PERIPH_GPU2DS0 + * @arg @ref LL_CKGA_PERIPH_GPU2DS1 + * @arg @ref LL_CKGA_PERIPH_GPU2DCL + * @arg @ref LL_CKGA_PERIPH_DMA2D + * @arg @ref LL_CKGA_PERIPH_DCMIPP + * @arg @ref LL_CKGA_PERIPH_LTDC + * @arg @ref LL_CKGA_PERIPH_FLASH + * @arg @ref LL_CKGA_PERIPH_XSPI2 + * @arg @ref LL_CKGA_PERIPH_XSPI1 + * @arg @ref LL_CKGA_PERIPH_FMC + * @arg @ref LL_CKGA_PERIPH_AXIRAM1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM2 + * @arg @ref LL_CKGA_PERIPH_AXIRAM3 + * @arg @ref LL_CKGA_PERIPH_AXIRAM4 + * @arg @ref LL_CKGA_PERIPH_GFXMMUM + * @arg @ref LL_CKGA_PERIPH_GFXMMUS + * @arg @ref LL_CKGA_PERIPH_EXTI + * @arg @ref LL_CKGA_PERIPH_JTAG + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs) +{ + SET_BIT(RCC->CKGDISR, Periphs); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_BUS_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_cordic.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_cordic.h new file mode 100644 index 00000000000..fedff00e717 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_cordic.h @@ -0,0 +1,783 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_cordic.h + * @author MCD Application Team + * @brief Header file of CORDIC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_CORDIC_H +#define STM32H7RSxx_LL_CORDIC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(CORDIC) + +/** @defgroup CORDIC_LL CORDIC + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORDIC_LL_Exported_Constants CORDIC Exported Constants + * @{ + */ + +/** @defgroup CORDIC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_CORDIC_ReadReg function. + * @{ + */ +#define LL_CORDIC_FLAG_RRDY CORDIC_CSR_RRDY +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_CORDIC_ReadReg and LL_CORDIC_WriteReg functions. + * @{ + */ +#define LL_CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result Ready interrupt enable */ +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_FUNCTION FUNCTION + * @{ + */ +#define LL_CORDIC_FUNCTION_COSINE (0x00000000U) /*!< Cosine */ +#define LL_CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0)) /*!< Sine */ +#define LL_CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1)) /*!< Phase */ +#define LL_CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0)) /*!< Modulus */ +#define LL_CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2)) /*!< Arctangent */ +#define LL_CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0)) /*!< Hyperbolic Cosine */ +#define LL_CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1)) /*!< Hyperbolic Sine */ +#define LL_CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */ +#define LL_CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */ +#define LL_CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */ +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_PRECISION PRECISION + * @{ + */ +#define LL_CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0)) +#define LL_CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1)) +#define LL_CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define LL_CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2)) +#define LL_CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) +#define LL_CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) +#define LL_CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\ + | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define LL_CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3)) +#define LL_CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0)) +#define LL_CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1)) +#define LL_CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define LL_CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2)) +#define LL_CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) +#define LL_CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) +#define LL_CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\ + | CORDIC_CSR_PRECISION_0)) +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_SCALE SCALE + * @{ + */ +#define LL_CORDIC_SCALE_0 (0x00000000U) +#define LL_CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0)) +#define LL_CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1)) +#define LL_CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0)) +#define LL_CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2)) +#define LL_CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0)) +#define LL_CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1)) +#define LL_CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0)) +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE + * @{ + */ +#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one + 32-bit data input (Q1.31 format), or two + 16-bit data input (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input + (Q1.31 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_NBREAD NBREAD + * @{ + */ +#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one + 32-bit data output (Q1.31 format), or two + 16-bit data output (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output + (Q1.31 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_INSIZE INSIZE + * @{ + */ +#define LL_CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */ +#define LL_CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_OUTSIZE OUTSIZE + * @{ + */ +#define LL_CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */ +#define LL_CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */ +/** + * @} + */ + +/** @defgroup CORDIC_LL_EC_DMA_REG_DATA DMA register data + * @{ + */ +#define LL_CORDIC_DMA_REG_DATA_IN (0x00000000U) /*!< Get address of input data register */ +#define LL_CORDIC_DMA_REG_DATA_OUT (0x00000001U) /*!< Get address of output data register */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CORDIC_LL_Exported_Macros CORDIC Exported Macros + * @{ + */ + +/** @defgroup CORDIC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CORDIC register. + * @param __INSTANCE__ CORDIC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CORDIC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in CORDIC register. + * @param __INSTANCE__ CORDIC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CORDIC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions + * @{ + */ + +/** @defgroup CORDIC_LL_EF_Configuration CORDIC Configuration functions + * @{ + */ + +/** + * @brief Configure the CORDIC processing. + * @note This function set all parameters of CORDIC processing. + * These parameters can also be set individually using + * dedicated functions: + * - @ref LL_CORDIC_SetFunction() + * - @ref LL_CORDIC_SetPrecision() + * - @ref LL_CORDIC_SetScale() + * - @ref LL_CORDIC_SetNbWrite() + * - @ref LL_CORDIC_SetNbRead() + * - @ref LL_CORDIC_SetInSize() + * - @ref LL_CORDIC_SetOutSize() + * @rmtoll CSR FUNC LL_CORDIC_Config\n + * CSR PRECISION LL_CORDIC_Config\n + * CSR SCALE LL_CORDIC_Config\n + * CSR NARGS LL_CORDIC_Config\n + * CSR NRES LL_CORDIC_Config\n + * CSR ARGSIZE LL_CORDIC_Config\n + * CSR RESIZE LL_CORDIC_Config + * @param CORDICx CORDIC instance + * @param Function parameter can be one of the following values: + * @arg @ref LL_CORDIC_FUNCTION_COSINE + * @arg @ref LL_CORDIC_FUNCTION_SINE + * @arg @ref LL_CORDIC_FUNCTION_PHASE + * @arg @ref LL_CORDIC_FUNCTION_MODULUS + * @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT + * @arg @ref LL_CORDIC_FUNCTION_HCOSINE + * @arg @ref LL_CORDIC_FUNCTION_HSINE + * @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT + * @arg @ref LL_CORDIC_FUNCTION_NATURALLOG + * @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT + * @param Precision parameter can be one of the following values: + * @arg @ref LL_CORDIC_PRECISION_1CYCLE + * @arg @ref LL_CORDIC_PRECISION_2CYCLES + * @arg @ref LL_CORDIC_PRECISION_3CYCLES + * @arg @ref LL_CORDIC_PRECISION_4CYCLES + * @arg @ref LL_CORDIC_PRECISION_5CYCLES + * @arg @ref LL_CORDIC_PRECISION_6CYCLES + * @arg @ref LL_CORDIC_PRECISION_7CYCLES + * @arg @ref LL_CORDIC_PRECISION_8CYCLES + * @arg @ref LL_CORDIC_PRECISION_9CYCLES + * @arg @ref LL_CORDIC_PRECISION_10CYCLES + * @arg @ref LL_CORDIC_PRECISION_11CYCLES + * @arg @ref LL_CORDIC_PRECISION_12CYCLES + * @arg @ref LL_CORDIC_PRECISION_13CYCLES + * @arg @ref LL_CORDIC_PRECISION_14CYCLES + * @arg @ref LL_CORDIC_PRECISION_15CYCLES + * @param Scale parameter can be one of the following values: + * @arg @ref LL_CORDIC_SCALE_0 + * @arg @ref LL_CORDIC_SCALE_1 + * @arg @ref LL_CORDIC_SCALE_2 + * @arg @ref LL_CORDIC_SCALE_3 + * @arg @ref LL_CORDIC_SCALE_4 + * @arg @ref LL_CORDIC_SCALE_5 + * @arg @ref LL_CORDIC_SCALE_6 + * @arg @ref LL_CORDIC_SCALE_7 + * @param NbWrite parameter can be one of the following values: + * @arg @ref LL_CORDIC_NBWRITE_1 + * @arg @ref LL_CORDIC_NBWRITE_2 + * @param NbRead parameter can be one of the following values: + * @arg @ref LL_CORDIC_NBREAD_1 + * @arg @ref LL_CORDIC_NBREAD_2 + * @param InSize parameter can be one of the following values: + * @arg @ref LL_CORDIC_INSIZE_32BITS + * @arg @ref LL_CORDIC_INSIZE_16BITS + * @param OutSize parameter can be one of the following values: + * @arg @ref LL_CORDIC_OUTSIZE_32BITS + * @arg @ref LL_CORDIC_OUTSIZE_16BITS + * @retval None + */ +__STATIC_INLINE void LL_CORDIC_Config(CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale, + uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize) +{ + MODIFY_REG(CORDICx->CSR, + CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE | + CORDIC_CSR_NARGS | CORDIC_CSR_NRES | CORDIC_CSR_ARGSIZE | CORDIC_CSR_RESSIZE, + Function | Precision | Scale | + NbWrite | NbRead | InSize | OutSize); +} + +/** + * @brief Configure function. + * @rmtoll CSR FUNC LL_CORDIC_SetFunction + * @param CORDICx CORDIC Instance + * @param Function parameter can be one of the following values: + * @arg @ref LL_CORDIC_FUNCTION_COSINE + * @arg @ref LL_CORDIC_FUNCTION_SINE + * @arg @ref LL_CORDIC_FUNCTION_PHASE + * @arg @ref LL_CORDIC_FUNCTION_MODULUS + * @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT + * @arg @ref LL_CORDIC_FUNCTION_HCOSINE + * @arg @ref LL_CORDIC_FUNCTION_HSINE + * @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT + * @arg @ref LL_CORDIC_FUNCTION_NATURALLOG + * @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT + * @retval None + */ +__STATIC_INLINE void LL_CORDIC_SetFunction(CORDIC_TypeDef *CORDICx, uint32_t Function) +{ + MODIFY_REG(CORDICx->CSR, CORDIC_CSR_FUNC, Function); +} + +/** + * @brief Return function. + * @rmtoll CSR FUNC LL_CORDIC_GetFunction + * @param CORDICx CORDIC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CORDIC_FUNCTION_COSINE + * @arg @ref LL_CORDIC_FUNCTION_SINE + * @arg @ref LL_CORDIC_FUNCTION_PHASE + * @arg @ref LL_CORDIC_FUNCTION_MODULUS + * @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT + * @arg @ref LL_CORDIC_FUNCTION_HCOSINE + * @arg @ref LL_CORDIC_FUNCTION_HSINE + * @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT + * @arg @ref LL_CORDIC_FUNCTION_NATURALLOG + * @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT + */ +__STATIC_INLINE uint32_t LL_CORDIC_GetFunction(const CORDIC_TypeDef *CORDICx) +{ + return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_FUNC)); +} + +/** + * @brief Configure precision in cycles number. + * @rmtoll CSR PRECISION LL_CORDIC_SetPrecision + * @param CORDICx CORDIC Instance + * @param Precision parameter can be one of the following values: + * @arg @ref LL_CORDIC_PRECISION_1CYCLE + * @arg @ref LL_CORDIC_PRECISION_2CYCLES + * @arg @ref LL_CORDIC_PRECISION_3CYCLES + * @arg @ref LL_CORDIC_PRECISION_4CYCLES + * @arg @ref LL_CORDIC_PRECISION_5CYCLES + * @arg @ref LL_CORDIC_PRECISION_6CYCLES + * @arg @ref LL_CORDIC_PRECISION_7CYCLES + * @arg @ref LL_CORDIC_PRECISION_8CYCLES + * @arg @ref LL_CORDIC_PRECISION_9CYCLES + * @arg @ref LL_CORDIC_PRECISION_10CYCLES + * @arg @ref LL_CORDIC_PRECISION_11CYCLES + * @arg @ref LL_CORDIC_PRECISION_12CYCLES + * @arg @ref LL_CORDIC_PRECISION_13CYCLES + * @arg @ref LL_CORDIC_PRECISION_14CYCLES + * @arg @ref LL_CORDIC_PRECISION_15CYCLES + * @retval None + */ +__STATIC_INLINE void LL_CORDIC_SetPrecision(CORDIC_TypeDef *CORDICx, uint32_t Precision) +{ + MODIFY_REG(CORDICx->CSR, CORDIC_CSR_PRECISION, Precision); +} + +/** + * @brief Return precision in cycles number. + * @rmtoll CSR PRECISION LL_CORDIC_GetPrecision + * @param CORDICx CORDIC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CORDIC_PRECISION_1CYCLE + * @arg @ref LL_CORDIC_PRECISION_2CYCLES + * @arg @ref LL_CORDIC_PRECISION_3CYCLES + * @arg @ref LL_CORDIC_PRECISION_4CYCLES + * @arg @ref LL_CORDIC_PRECISION_5CYCLES + * @arg @ref LL_CORDIC_PRECISION_6CYCLES + * @arg @ref LL_CORDIC_PRECISION_7CYCLES + * @arg @ref LL_CORDIC_PRECISION_8CYCLES + * @arg @ref LL_CORDIC_PRECISION_9CYCLES + * @arg @ref LL_CORDIC_PRECISION_10CYCLES + * @arg @ref LL_CORDIC_PRECISION_11CYCLES + * @arg @ref LL_CORDIC_PRECISION_12CYCLES + * @arg @ref LL_CORDIC_PRECISION_13CYCLES + * @arg @ref LL_CORDIC_PRECISION_14CYCLES + * @arg @ref LL_CORDIC_PRECISION_15CYCLES + */ +__STATIC_INLINE uint32_t LL_CORDIC_GetPrecision(const CORDIC_TypeDef *CORDICx) +{ + return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_PRECISION)); +} + +/** + * @brief Configure scaling factor. + * @rmtoll CSR SCALE LL_CORDIC_SetScale + * @param CORDICx CORDIC Instance + * @param Scale parameter can be one of the following values: + * @arg @ref LL_CORDIC_SCALE_0 + * @arg @ref LL_CORDIC_SCALE_1 + * @arg @ref LL_CORDIC_SCALE_2 + * @arg @ref LL_CORDIC_SCALE_3 + * @arg @ref LL_CORDIC_SCALE_4 + * @arg @ref LL_CORDIC_SCALE_5 + * @arg @ref LL_CORDIC_SCALE_6 + * @arg @ref LL_CORDIC_SCALE_7 + * @retval None + */ +__STATIC_INLINE void LL_CORDIC_SetScale(CORDIC_TypeDef *CORDICx, uint32_t Scale) +{ + MODIFY_REG(CORDICx->CSR, CORDIC_CSR_SCALE, Scale); +} + +/** + * @brief Return scaling factor. + * @rmtoll CSR SCALE LL_CORDIC_GetScale + * @param CORDICx CORDIC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CORDIC_SCALE_0 + * @arg @ref LL_CORDIC_SCALE_1 + * @arg @ref LL_CORDIC_SCALE_2 + * @arg @ref LL_CORDIC_SCALE_3 + * @arg @ref LL_CORDIC_SCALE_4 + * @arg @ref LL_CORDIC_SCALE_5 + * @arg @ref LL_CORDIC_SCALE_6 + * @arg @ref LL_CORDIC_SCALE_7 + */ +__STATIC_INLINE uint32_t LL_CORDIC_GetScale(const CORDIC_TypeDef *CORDICx) +{ + return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_SCALE)); +} + +/** + * @brief Configure number of 32-bit write expected for one calculation. + * @rmtoll CSR NARGS LL_CORDIC_SetNbWrite + * @param CORDICx CORDIC Instance + * @param NbWrite parameter can be one of the following values: + * @arg @ref LL_CORDIC_NBWRITE_1 + * @arg @ref LL_CORDIC_NBWRITE_2 + * @retval None + */ +__STATIC_INLINE void LL_CORDIC_SetNbWrite(CORDIC_TypeDef *CORDICx, uint32_t NbWrite) +{ + MODIFY_REG(CORDICx->CSR, CORDIC_CSR_NARGS, NbWrite); +} + +/** + * @brief Return number of 32-bit write expected for one calculation. + * @rmtoll CSR NARGS LL_CORDIC_GetNbWrite + * @param CORDICx CORDIC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CORDIC_NBWRITE_1 + * @arg @ref LL_CORDIC_NBWRITE_2 + */ +__STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite(const CORDIC_TypeDef *CORDICx) +{ + return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NARGS)); +} + +/** + * @brief Configure number of 32-bit read expected after one calculation. + * @rmtoll CSR NRES LL_CORDIC_SetNbRead + * @param CORDICx CORDIC Instance + * @param NbRead parameter can be one of the following values: + * @arg @ref LL_CORDIC_NBREAD_1 + * @arg @ref LL_CORDIC_NBREAD_2 + * @retval None + */ +__STATIC_INLINE void LL_CORDIC_SetNbRead(CORDIC_TypeDef *CORDICx, uint32_t NbRead) +{ + MODIFY_REG(CORDICx->CSR, CORDIC_CSR_NRES, NbRead); +} + +/** + * @brief Return number of 32-bit read expected after one calculation. + * @rmtoll CSR NRES LL_CORDIC_GetNbRead + * @param CORDICx CORDIC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CORDIC_NBREAD_1 + * @arg @ref LL_CORDIC_NBREAD_2 + */ +__STATIC_INLINE uint32_t LL_CORDIC_GetNbRead(const CORDIC_TypeDef *CORDICx) +{ + return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NRES)); +} + +/** + * @brief Configure width of input data. + * @rmtoll CSR ARGSIZE LL_CORDIC_SetInSize + * @param CORDICx CORDIC Instance + * @param InSize parameter can be one of the following values: + * @arg @ref LL_CORDIC_INSIZE_32BITS + * @arg @ref LL_CORDIC_INSIZE_16BITS + * @retval None + */ +__STATIC_INLINE void LL_CORDIC_SetInSize(CORDIC_TypeDef *CORDICx, uint32_t InSize) +{ + MODIFY_REG(CORDICx->CSR, CORDIC_CSR_ARGSIZE, InSize); +} + +/** + * @brief Return width of input data. + * @rmtoll CSR ARGSIZE LL_CORDIC_GetInSize + * @param CORDICx CORDIC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CORDIC_INSIZE_32BITS + * @arg @ref LL_CORDIC_INSIZE_16BITS + */ +__STATIC_INLINE uint32_t LL_CORDIC_GetInSize(const CORDIC_TypeDef *CORDICx) +{ + return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_ARGSIZE)); +} + +/** + * @brief Configure width of output data. + * @rmtoll CSR RESIZE LL_CORDIC_SetOutSize + * @param CORDICx CORDIC Instance + * @param OutSize parameter can be one of the following values: + * @arg @ref LL_CORDIC_OUTSIZE_32BITS + * @arg @ref LL_CORDIC_OUTSIZE_16BITS + * @retval None + */ +__STATIC_INLINE void LL_CORDIC_SetOutSize(CORDIC_TypeDef *CORDICx, uint32_t OutSize) +{ + MODIFY_REG(CORDICx->CSR, CORDIC_CSR_RESSIZE, OutSize); +} + +/** + * @brief Return width of output data. + * @rmtoll CSR RESIZE LL_CORDIC_GetOutSize + * @param CORDICx CORDIC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CORDIC_OUTSIZE_32BITS + * @arg @ref LL_CORDIC_OUTSIZE_16BITS + */ +__STATIC_INLINE uint32_t LL_CORDIC_GetOutSize(const CORDIC_TypeDef *CORDICx) +{ + return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_RESSIZE)); +} + +/** + * @} + */ + +/** @defgroup CORDIC_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable CORDIC result ready interrupt + * @rmtoll CSR IEN LL_CORDIC_EnableIT + * @param CORDICx CORDIC Instance + * @retval None + */ +__STATIC_INLINE void LL_CORDIC_EnableIT(CORDIC_TypeDef *CORDICx) +{ + SET_BIT(CORDICx->CSR, CORDIC_CSR_IEN); +} + +/** + * @brief Disable CORDIC result ready interrupt + * @rmtoll CSR IEN LL_CORDIC_DisableIT + * @param CORDICx CORDIC Instance + * @retval None + */ +__STATIC_INLINE void LL_CORDIC_DisableIT(CORDIC_TypeDef *CORDICx) +{ + CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_IEN); +} + +/** + * @brief Check CORDIC result ready interrupt state. + * @rmtoll CSR IEN LL_CORDIC_IsEnabledIT + * @param CORDICx CORDIC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT(const CORDIC_TypeDef *CORDICx) +{ + return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_IEN) == (CORDIC_CSR_IEN)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup CORDIC_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable CORDIC DMA read channel request. + * @rmtoll CSR DMAREN LL_CORDIC_EnableDMAReq_RD + * @param CORDICx CORDIC Instance + * @retval None + */ +__STATIC_INLINE void LL_CORDIC_EnableDMAReq_RD(CORDIC_TypeDef *CORDICx) +{ + SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN); +} + +/** + * @brief Disable CORDIC DMA read channel request. + * @rmtoll CSR DMAREN LL_CORDIC_DisableDMAReq_RD + * @param CORDICx CORDIC Instance + * @retval None + */ +__STATIC_INLINE void LL_CORDIC_DisableDMAReq_RD(CORDIC_TypeDef *CORDICx) +{ + CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN); +} + +/** + * @brief Check CORDIC DMA read channel request state. + * @rmtoll CSR DMAREN LL_CORDIC_IsEnabledDMAReq_RD + * @param CORDICx CORDIC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD(const CORDIC_TypeDef *CORDICx) +{ + return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN) == (CORDIC_CSR_DMAREN)) ? 1U : 0U); +} + +/** + * @brief Enable CORDIC DMA write channel request. + * @rmtoll CSR DMAWEN LL_CORDIC_EnableDMAReq_WR + * @param CORDICx CORDIC Instance + * @retval None + */ +__STATIC_INLINE void LL_CORDIC_EnableDMAReq_WR(CORDIC_TypeDef *CORDICx) +{ + SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN); +} + +/** + * @brief Disable CORDIC DMA write channel request. + * @rmtoll CSR DMAWEN LL_CORDIC_DisableDMAReq_WR + * @param CORDICx CORDIC Instance + * @retval None + */ +__STATIC_INLINE void LL_CORDIC_DisableDMAReq_WR(CORDIC_TypeDef *CORDICx) +{ + CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN); +} + +/** + * @brief Check CORDIC DMA write channel request state. + * @rmtoll CSR DMAWEN LL_CORDIC_IsEnabledDMAReq_WR + * @param CORDICx CORDIC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(const CORDIC_TypeDef *CORDICx) +{ + return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U); +} + +/** + * @brief Get the CORDIC data register address used for DMA transfer. + * @rmtoll RDATA RES LL_CORDIC_DMA_GetRegAddr\n + * @rmtoll WDATA ARG LL_CORDIC_DMA_GetRegAddr + * @param CORDICx CORDIC Instance + * @param Direction parameter can be one of the following values: + * @arg @ref LL_CORDIC_DMA_REG_DATA_IN + * @arg @ref LL_CORDIC_DMA_REG_DATA_OUT + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(const CORDIC_TypeDef *CORDICx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_CORDIC_DMA_REG_DATA_OUT) + { + /* return address of RDATA register */ + data_reg_addr = (uint32_t) &(CORDICx->RDATA); + } + else + { + /* return address of WDATA register */ + data_reg_addr = (uint32_t) &(CORDICx->WDATA); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup CORDIC_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check CORDIC result ready flag state. + * @rmtoll CSR RRDY LL_CORDIC_IsActiveFlag_RRDY + * @param CORDICx CORDIC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY(const CORDIC_TypeDef *CORDICx) +{ + return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_RRDY) == (CORDIC_CSR_RRDY)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup CORDIC_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Write 32-bit input data for the CORDIC processing. + * @rmtoll WDATA ARG LL_CORDIC_WriteData + * @param CORDICx CORDIC Instance + * @param InData 0 .. 0xFFFFFFFF : 32-bit value to be provided as input data for CORDIC processing. + * @retval None + */ +__STATIC_INLINE void LL_CORDIC_WriteData(CORDIC_TypeDef *CORDICx, uint32_t InData) +{ + WRITE_REG(CORDICx->WDATA, InData); +} + +/** + * @brief Return 32-bit output data of CORDIC processing. + * @rmtoll RDATA RES LL_CORDIC_ReadData + * @param CORDICx CORDIC Instance + * @retval 32-bit output data of CORDIC processing. + */ +__STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *CORDICx) +{ + return (uint32_t)(READ_REG(CORDICx->RDATA)); +} + +/** + * @} + */ + + + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_CORDIC_DeInit(const CORDIC_TypeDef *CORDICx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CORDIC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_CORDIC_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_cortex.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_cortex.h new file mode 100644 index 00000000000..6f6194230c6 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_cortex.h @@ -0,0 +1,715 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + (+) API to enable and disable the MPU + (+) API to configure the region of MPU + (+) API to configure the attributes region of MPU + + @endverbatim + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_CORTEX_H +#define STM32H7RSxx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK CORTEX LL SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0U /*!< AHB clock divided by 8 selected as SysTick + clock source */ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick + clock source */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT CORTEX LL Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF CORTEX LL MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION CORTEX LL MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0U /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 1U /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 2U /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 3U /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 4U /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 5U /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 6U /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 7U /*!< REGION Number 7 */ +#define LL_MPU_REGION_NUMBER8 8U /*!< REGION Number 8 */ +#define LL_MPU_REGION_NUMBER9 9U /*!< REGION Number 9 */ +#define LL_MPU_REGION_NUMBER10 10U /*!< REGION Number 10 */ +#define LL_MPU_REGION_NUMBER11 11U /*!< REGION Number 11 */ +#define LL_MPU_REGION_NUMBER12 12U /*!< REGION Number 12 */ +#define LL_MPU_REGION_NUMBER13 13U /*!< REGION Number 13 */ +#define LL_MPU_REGION_NUMBER14 14U /*!< REGION Number 14 */ +#define LL_MPU_REGION_NUMBER15 15U /*!< REGION Number 15 */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE CORTEX LL MPU Region Size + * @{ + */ +#define LL_MPU_REGION_SIZE_32B (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256B (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES CORTEX LL MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS (0U << MPU_RASR_AP_Pos) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW (1U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO (2U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS (3U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO (5U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO (6U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX CORTEX LL MPU TEX Level + * @{ + */ +#define LL_MPU_TEX_LEVEL0 (0U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 (1U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 (2U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ +#define LL_MPU_TEX_LEVEL4 (4U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS CORTEX LL MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS CORTEX LL MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS CORTEX LL MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE 0U /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS CORTEX LL MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE 0U /*!< Not Bufferable memory attribute */ +/** + * @} + */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK CORTEX LL SYSTICK + * @brief CORTEX SYSTICK LL module driver + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source); +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Clear pending events. + * @retval None + */ +__STATIC_INLINE void LL_LPM_ClearEvent(void) +{ + __SEV(); + __WFE(); +} +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n + * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n + * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n + * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n + * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Architecture version + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture + * @retval Value should be equal to 0xF for Cortex-M7 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC27 for Cortex-M7 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param MPU_Control This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); /* Force any outstanding transfers to complete before enabling MPU */ + + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_Control | MPU_CTRL_ENABLE_Msk)); + + /* Ensure MPU settings take effects */ + __DSB(); + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable the MPU and clear the control register */ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Check if MPU region is enabled or not + * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region) +{ + /* Set region index */ + WRITE_REG(MPU->RNR, Region); + + /* Return MPU region status */ + return ((READ_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk) == (MPU_RASR_ENABLE_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Configure and enable a MPU region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B + * or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B + * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB + * or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB + * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB + * or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB + * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB + * or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB + * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB + * or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB + * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO + * or @ref LL_MPU_REGION_FULL_ACCESS or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, + uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); +} + +/** + * @brief Disable a MPU region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_CORTEX_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_crc.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_crc.h new file mode 100644 index 00000000000..732c98e239b --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_crc.h @@ -0,0 +1,461 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_crc.h + * @author MCD Application Team + * @brief Header file of CRC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_CRC_H +#define STM32H7RSxx_LL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(CRC) + +/** @defgroup CRC_LL CRC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants + * @{ + */ + +/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length + * @{ + */ +#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse + * @{ + */ +#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */ +#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */ +#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */ +#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse + * @{ + */ +#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */ +#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value + * @brief Normal representation of this polynomial value is + * X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 . + * @{ + */ +#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value + * @{ + */ +#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__) + +/** + * @brief Read a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions + * @{ + */ + +/** + * @brief Reset the CRC calculation unit. + * @note If Programmable Initial CRC value feature + * is available, also set the Data Register to the value stored in the + * CRC_INIT register, otherwise, reset Data Register to its default value. + * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit + * @param CRCx CRC Instance + * @retval None + */ +__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_RESET); +} + +/** + * @brief Configure size of the polynomial. + * @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize + * @param CRCx CRC Instance + * @param PolySize This parameter can be one of the following values: + * @arg @ref LL_CRC_POLYLENGTH_32B + * @arg @ref LL_CRC_POLYLENGTH_16B + * @arg @ref LL_CRC_POLYLENGTH_8B + * @arg @ref LL_CRC_POLYLENGTH_7B + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize) +{ + MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize); +} + +/** + * @brief Return size of the polynomial. + * @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_POLYLENGTH_32B + * @arg @ref LL_CRC_POLYLENGTH_16B + * @arg @ref LL_CRC_POLYLENGTH_8B + * @arg @ref LL_CRC_POLYLENGTH_7B + */ +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE)); +} + +/** + * @brief Configure the reversal of the bit order of the input data + * @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode + * @param CRCx CRC Instance + * @param ReverseMode This parameter can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSE_NONE + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD + * @arg @ref LL_CRC_INDATA_REVERSE_WORD + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode) +{ + MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode); +} + +/** + * @brief Return type of reversal for input data bit order + * @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSE_NONE + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD + * @arg @ref LL_CRC_INDATA_REVERSE_WORD + */ +__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN)); +} + +/** + * @brief Configure the reversal of the bit order of the Output data + * @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode + * @param CRCx CRC Instance + * @param ReverseMode This parameter can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE + * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode) +{ + MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode); +} + +/** + * @brief Return type of reversal of the bit order of the Output data + * @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE + * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT + */ +__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT)); +} + +/** + * @brief Initialize the Programmable initial CRC value. + * @note If the CRC size is less than 32 bits, the least significant bits + * are used to write the correct value + * @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter. + * @rmtoll INIT INIT LL_CRC_SetInitialData + * @param CRCx CRC Instance + * @param InitCrc Value to be programmed in Programmable initial CRC value register + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc) +{ + WRITE_REG(CRCx->INIT, InitCrc); +} + +/** + * @brief Return current Initial CRC value. + * @note If the CRC size is less than 32 bits, the least significant bits + * are used to read the correct value + * @rmtoll INIT INIT LL_CRC_GetInitialData + * @param CRCx CRC Instance + * @retval Value programmed in Programmable initial CRC value register + */ +__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->INIT)); +} + +/** + * @brief Initialize the Programmable polynomial value + * (coefficients of the polynomial to be used for CRC calculation). + * @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter. + * @note Please check Reference Manual and existing Errata Sheets, + * regarding possible limitations for Polynomial values usage. + * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @rmtoll POL POL LL_CRC_SetPolynomialCoef + * @param CRCx CRC Instance + * @param PolynomCoef Value to be programmed in Programmable Polynomial value register + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef) +{ + WRITE_REG(CRCx->POL, PolynomCoef); +} + +/** + * @brief Return current Programmable polynomial value + * @note Please check Reference Manual and existing Errata Sheets, + * regarding possible limitations for Polynomial values usage. + * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @rmtoll POL POL LL_CRC_GetPolynomialCoef + * @param CRCx CRC Instance + * @retval Value programmed in Programmable Polynomial value register + */ +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->POL)); +} + +/** + * @} + */ + +/** @defgroup CRC_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Write given 32-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData32 + * @param CRCx CRC Instance + * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) +{ + WRITE_REG(CRCx->DR, InData); +} + +/** + * @brief Write given 16-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData16 + * @param CRCx CRC Instance + * @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData) +{ + __IO uint16_t *pReg; + + pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = InData; +} + +/** + * @brief Write given 8-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData8 + * @param CRCx CRC Instance + * @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData) +{ + *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData; +} + +/** + * @brief Return current CRC calculation result. 32 bits value is returned. + * @rmtoll DR DR LL_CRC_ReadData32 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). + */ +__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->DR)); +} + +/** + * @brief Return current CRC calculation result. 16 bits value is returned. + * @note This function is expected to be used in a 16 bits CRC polynomial size context. + * @rmtoll DR DR LL_CRC_ReadData16 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (16 bits). + */ +__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx) +{ + return (uint16_t)READ_REG(CRCx->DR); +} + +/** + * @brief Return current CRC calculation result. 8 bits value is returned. + * @note This function is expected to be used in a 8 bits CRC polynomial size context. + * @rmtoll DR DR LL_CRC_ReadData8 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (8 bits). + */ +__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx) +{ + return (uint8_t)READ_REG(CRCx->DR); +} + +/** + * @brief Return current CRC calculation result. 7 bits value is returned. + * @note This function is expected to be used in a 7 bits CRC polynomial size context. + * @rmtoll DR DR LL_CRC_ReadData7 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (7 bits). + */ +__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx) +{ + return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU); +} + +/** + * @brief Return data stored in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one 32-bit long data. + * @rmtoll IDR IDR LL_CRC_Read_IDR + * @param CRCx CRC Instance + * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register). + */ +__STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->IDR)); +} + +/** + * @brief Store data in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one 32-bit long data. + * @rmtoll IDR IDR LL_CRC_Write_IDR + * @param CRCx CRC Instance + * @param InData value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) +{ + *((uint32_t __IO *)(&CRCx->IDR)) = (uint32_t) InData; +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_CRC_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_crs.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_crs.h new file mode 100644 index 00000000000..6e4deb34fc3 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_crs.h @@ -0,0 +1,786 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_crs.h + * @author MCD Application Team + * @brief Header file of CRS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_CRS_H +#define STM32H7RSxx_LL_CRS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(CRS) + +/** @defgroup CRS_LL CRS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants + * @{ + */ + +/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_CRS_ReadReg function + * @{ + */ +#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF +#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF +#define LL_CRS_ISR_ERRF CRS_ISR_ERRF +#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF +#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR +#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS +#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF +/** + * @} + */ + +/** @defgroup CRS_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions + * @{ + */ +#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE +#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE +#define LL_CRS_CR_ERRIE CRS_CR_ERRIE +#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider + * @{ + */ +#define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */ +#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source + * @{ + */ +#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ +#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define LL_CRS_SYNC_SOURCE_OTG_FS CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source OTG_FS SOF (default) */ +#define LL_CRS_SYNC_SOURCE_OTG_HS (CRS_CFGR_SYNCSRC_1 | CRS_CFGR_SYNCSRC_0) /*!< Synchro Signal source OTG_HS SOF */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity + * @{ + */ +#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ +#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction + * @{ + */ +#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ +#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values + * @{ + */ +/** + * @brief Reset value of the RELOAD field + * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz + * and a synchronization signal frequency of 1 kHz (SOF signal from USB) + */ +#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU + +/** + * @brief Reset value of Frequency error limit. + */ +#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U + +/** + * @brief Reset value of the HSI48 Calibration field + * @note The default value is 32, which corresponds to the middle of the trimming interval. + * The trimming step is specified in the product datasheet. + * A higher TRIM value corresponds to a higher output frequency. + */ +#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros + * @{ + */ + +/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload + * @{ + */ + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between + * the target frequency and the frequency of the synchronization source after + * prescaling. It is then decreased by one in order to reach the expected + * synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval Reload value (in Hz) + */ +#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions + * @{ + */ + +/** @defgroup CRS_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable Frequency error counter + * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified + * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) +{ + SET_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Disable Frequency error counter + * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Check if Frequency error counter is enabled or not + * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) +{ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Disable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Check if Automatic trimming is enabled or not + * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL); +} + +/** + * @brief Set HSI48 oscillator smooth trimming + * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only + * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming + * @param Value a number between Min_Data = 0 and Max_Data = 63 + * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); +} + +/** + * @brief Get HSI48 oscillator smooth trimming + * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming + * @retval a number between Min_Data = 0 and Max_Data = 63 + */ +__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) +{ + return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); +} + +/** + * @brief Set counter reload value + * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter + * @param Value a number between Min_Data = 0 and Max_Data = 65535 (0xFFFF) + * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT + * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); +} + +/** + * @brief Get counter reload value + * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter + * @retval a number between Min_Data = 0 and Max_Data = 65535 (0xFFFF) + */ +__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); +} + +/** + * @brief Set frequency error limit + * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit + * @param Value a number between Min_Data = 0 and Max_Data = 255 + * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Get frequency error limit + * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit + * @retval A number between Min_Data = 0 and Max_Data = 255 + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Set division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); +} + +/** + * @brief Get division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); +} + +/** + * @brief Set SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_OTG_FS + * @arg @ref LL_CRS_SYNC_SOURCE_OTG_HS + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); +} + +/** + * @brief Get SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_OTG_FS + * @arg @ref LL_CRS_SYNC_SOURCE_OTG_HS + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); +} + +/** + * @brief Set input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); +} + +/** + * @brief Get input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); +} + +/** + * @brief Configure CRS for the synchronization + * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n + * CFGR RELOAD LL_CRS_ConfigSynchronization\n + * CFGR FELIM LL_CRS_ConfigSynchronization\n + * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n + * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n + * CFGR SYNCPOL LL_CRS_ConfigSynchronization + * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 + * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 255 + * @param ReloadValue a number between Min_Data = 0 and Max_Data = 65535 (0xFFFF) + * @param Settings This parameter can be a combination of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 + * or @ref LL_CRS_SYNC_DIV_8 or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 + * or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE + * or @ref LL_CRS_SYNC_SOURCE_OTG_FS or @ref LL_CRS_SYNC_SOURCE_OTG_HS + * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, + uint32_t ReloadValue, uint32_t Settings) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos); + MODIFY_REG(CRS->CFGR, + CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, + ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_CRS_Management CRS_Management + * @{ + */ + +/** + * @brief Generate software SYNC event + * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Get the frequency error direction latched in the time of the last + * SYNC event + * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP + * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Get the frequency error counter value latched in the time of the last SYNC event + * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture + * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if SYNC event OK signal occurred or not + * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC warning signal occurred or not + * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Synchronization or trimming error signal occurred or not + * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Expected SYNC signal occurred or not + * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC error signal occurred or not + * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC missed error signal occurred or not + * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL); +} + +/** + * @brief Check if Trimming overflow or underflow occurred or not + * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the SYNC event OK flag + * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); +} + +/** + * @brief Clear the SYNC warning flag + * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); +} + +/** + * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also + * the ERR flag + * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); +} + +/** + * @brief Clear Expected SYNC flag + * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Disable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Check if SYNC event OK interrupt is enabled or not + * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Disable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Check if SYNC warning interrupt is enabled or not + * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) +{ + SET_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Disable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Check if Synchronization or trimming error interrupt is enabled or not + * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Disable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Check if Expected SYNC interrupt is enabled or not + * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRS_DeInit(void); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRS) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_CRS_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_dlyb.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_dlyb.h new file mode 100644 index 00000000000..4a4c1135b68 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_dlyb.h @@ -0,0 +1,143 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_dlyb.h + * @author MCD Application Team + * @brief Header file of DelayBlock module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_DLYB_H +#define STM32H7RSxx_LL_DLYB_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(HAL_SD_MODULE_ENABLED) +#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DLYB_LL DLYB + * @{ + */ + +/** + * @brief DLYB Configuration Structure definition + */ + +typedef struct +{ + uint32_t Units; /*!< Specifies the Delay of a unit delay cell. + This parameter can be a value between 0 and DLYB_MAX_UNIT */ + + uint32_t PhaseSel; /*!< Specifies the Phase for the output clock. + This parameter can be a value between 0 and DLYB_MAX_SELECT */ +} LL_DLYB_CfgTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DLYB_Exported_Constants DLYB Exported Constants + * @{ + */ + +#define DLYB_MAX_UNIT ((uint32_t)0x00000080U) /*!< Max UNIT value (128) */ +#define DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12) */ + +/** + * @} + */ + +/** @defgroup DLYB_LL_Flags DLYB Flags + * @{ + */ + +#define DLYB_FLAG_LNGF DLYB_CFGR_LNGF + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DLYB_LL_Exported_Functions DLYB Exported Functions + * @{ + */ + +/** @defgroup DLYB_LL_Configuration Configuration functions + * @{ + */ + +/** + * @brief DLYB Enable + * @param DLYBx DLYB Instance + * @retval None + */ + +__STATIC_INLINE void LL_DLYB_Enable(DLYB_TypeDef *DLYBx) +{ + SET_BIT(DLYBx->CR, DLYB_CR_DEN); +} + +/** @brief Disable the DLYB. + * @param DLYBx DLYB Instance. + * @retval None + */ + +__STATIC_INLINE void LL_DLYB_Disable(DLYB_TypeDef *DLYBx) +{ + CLEAR_BIT(DLYBx->CR, DLYB_CR_DEN); +} + +/** + * @} + */ + +/** @defgroup DLYB_Control_Functions DLYB Control functions + * @{ + */ + +void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg); +void LL_DLYB_GetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg); +uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 */ +#endif /* HAL_SD_MODULE_ENABLED */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_DLYB_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_dma.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_dma.h new file mode 100644 index 00000000000..559dc8f3b45 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_dma.h @@ -0,0 +1,6677 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### LL DMA driver acronyms ##### + ============================================================================== + [..] Acronyms table : + ========================================= + || Acronym || || + ========================================= + || SRC || Source || + || DEST || Destination || + || ADDR || Address || + || ADDRS || Addresses || + || INC || Increment / Incremented || + || DEC || Decrement / Decremented || + || BLK || Block || + || RPT || Repeat / Repeated || + || TRIG || Trigger || + ========================================= + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_DMA_H +#define STM32H7RSxx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if (defined (GPDMA1) || defined (HPDMA1)) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +#define DMA_CHANNEL0_OFFSET (0x00000050UL) +#define DMA_CHANNEL1_OFFSET (0x000000D0UL) +#define DMA_CHANNEL2_OFFSET (0x00000150UL) +#define DMA_CHANNEL3_OFFSET (0x000001D0UL) +#define DMA_CHANNEL4_OFFSET (0x00000250UL) +#define DMA_CHANNEL5_OFFSET (0x000002D0UL) +#define DMA_CHANNEL6_OFFSET (0x00000350UL) +#define DMA_CHANNEL7_OFFSET (0x000003D0UL) +#define DMA_CHANNEL8_OFFSET (0x00000450UL) +#define DMA_CHANNEL9_OFFSET (0x000004D0UL) +#define DMA_CHANNEL10_OFFSET (0x00000550UL) +#define DMA_CHANNEL11_OFFSET (0x000005D0UL) +#define DMA_CHANNEL12_OFFSET (0x00000650UL) +#define DMA_CHANNEL13_OFFSET (0x000006D0UL) +#define DMA_CHANNEL14_OFFSET (0x00000750UL) +#define DMA_CHANNEL15_OFFSET (0x000007D0UL) + +/* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */ +static const uint32_t LL_DMA_CH_OFFSET_TAB[] = +{ + DMA_CHANNEL0_OFFSET, DMA_CHANNEL1_OFFSET, DMA_CHANNEL2_OFFSET, DMA_CHANNEL3_OFFSET, + DMA_CHANNEL4_OFFSET, DMA_CHANNEL5_OFFSET, DMA_CHANNEL6_OFFSET, DMA_CHANNEL7_OFFSET, + DMA_CHANNEL8_OFFSET, DMA_CHANNEL9_OFFSET, DMA_CHANNEL10_OFFSET, DMA_CHANNEL11_OFFSET, + DMA_CHANNEL12_OFFSET, DMA_CHANNEL13_OFFSET, DMA_CHANNEL14_OFFSET, DMA_CHANNEL15_OFFSET, +}; + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ + +/** + * @brief LL DMA init structure definition. + */ +typedef struct +{ + uint32_t SrcAddress; /*!< This field specify the data transfer source address. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAddress(). */ + + uint32_t DestAddress; /*!< This field specify the data transfer destination address. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAddress(). */ + + uint32_t Direction; /*!< This field specify the data transfer direction. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t BlkHWRequest; /*!< This field specify the hardware request unity. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkHWRequest(). */ + + uint32_t DataAlignment; /*!< This field specify the transfer data alignment. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDataAlignment(). */ + + uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcBurstLength(). */ + + uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestBurstLength(). */ + + uint32_t SrcDataWidth; /*!< This field specify the source data width. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcDataWidth(). */ + + uint32_t DestDataWidth; /*!< This field specify the destination data width. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestDataWidth(). */ + + uint32_t SrcIncMode; /*!< This field specify the source burst increment mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcIncMode(). */ + + uint32_t DestIncMode; /*!< This field specify the destination burst increment mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestIncMode(). */ + + uint32_t Priority; /*!< This field specify the channel priority level. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetChannelPriorityLevel(). */ + + uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkDataLength(). */ + + uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value between 1 and 2048 Min_Data = 0 + and Max_Data = 0x000007FF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptCount(). */ + + uint32_t TriggerMode; /*!< This field specify the trigger mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTriggerMode(). */ + + uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTriggerPolarity(). */ + + uint32_t TriggerSelection; /*!< This field specify the trigger event selection. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetHWTrigger(). */ + + uint32_t Request; /*!< This field specify the peripheral request selection. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetPeriphRequest(). */ + + uint32_t TransferEventMode; /*!< This field specify the transfer event mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTransferEventMode(). */ + + uint32_t DestWordExchange; /*!< This field specify the destination word exchange. + Programming this field is mandatory for all available HPDMA channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_WORD_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestWordExchange(). */ + + uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestHWordExchange(). */ + + uint32_t DestByteExchange; /*!< This field specify the destination byte exchange. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestByteExchange(). */ + + uint32_t SrcByteExchange; /*!< This field specify the source byte exchange. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcByteExchange(). */ + + uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAllocatedPort(). */ + + uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAllocatedPort(). */ + + uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkAllocatedPort(). */ + + uint32_t LinkStepMode; /*!< This field specify the link step mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkStepMode(). */ + + uint32_t SrcAddrUpdateMode; /*!< This field specify the source address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAddrUpdate(). */ + + uint32_t DestAddrUpdateMode; /*!< This field specify the destination address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAddrUpdate(). */ + + uint32_t SrcAddrOffset; /*!< This field specifies the source address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x00001FFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAddrUpdateValue(). */ + + uint32_t DestAddrOffset; /*!< This field specifies the destination address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x00001FFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAddrUpdateValue(). */ + + uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptSrcAddrUpdate(). */ + + uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptDestAddrUpdate(). */ + + uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x0000FFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptSrcAddrUpdateValue(). */ + + uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset. + Programming this field is mandatory only for 2D addressing channels. + This parameter can be a value Between 0 to 0x0000FFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkRptDestAddrUpdateValue(). */ + + uint32_t LinkedListBaseAddr; /*!< This field specify the linked list base address. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first + bytes are always forced to 0). + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkedListBaseAddr(). */ + + uint32_t LinkedListAddrOffset; /*!< Specifies the linked list address offset. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value Between 0 to 0x0000FFFC. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkedListAddrOffset(). */ + + uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel. + This parameter can be a value of @ref DMA_LL_TRANSFER_MODE */ +} LL_DMA_InitTypeDef; + + +/** + * @brief LL DMA init linked list structure definition. + */ +typedef struct +{ + uint32_t Priority; /*!< This field specify the channel priority level. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetChannelPriorityLevel(). */ + + uint32_t LinkStepMode; /*!< This field specify the link step mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkStepMode(). */ + + uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkAllocatedPort(). */ + + uint32_t TransferEventMode; /*!< This field specify the transfer event mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTransferEventMode(). */ +} LL_DMA_InitLinkedListTypeDef; + + +/** + * @brief LL DMA node init structure definition. + */ +typedef struct +{ + /* CTR1 register fields ****************************************************** + If any CTR1 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CTR1 register fields and enable update + CTR1 register in UpdateRegisters fields if it is not enabled in the + previous node. + + */ + uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */ + + uint32_t DestWordExchange; /*!< This field specify the destination word exchange. + This parameter can be a value of @ref DMA_LL_EC_DEST_WORD_EXCHANGE. */ + + uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange. + This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. */ + + uint32_t DestByteExchange; /*!< This field specify the destination byte exchange. + This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. */ + + uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. */ + + uint32_t DestIncMode; /*!< This field specify the destination increment mode. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. */ + + uint32_t DestDataWidth; /*!< This field specify the destination data width. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. */ + + uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */ + + uint32_t SrcByteExchange; /*!< This field specify the source byte exchange. + This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. */ + + uint32_t DataAlignment; /*!< This field specify the transfer data alignment. + This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. */ + + uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. */ + + uint32_t SrcIncMode; /*!< This field specify the source increment mode. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. */ + + uint32_t SrcDataWidth; /*!< This field specify the source data width. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. */ + + + /* CTR2 register fields ****************************************************** + If any CTR2 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CTR2 register fields and enable update + CTR2 register in UpdateRegisters fields if it is not enabled in the + previous node. + + For all node created, filling all fields is mandatory. + */ + uint32_t TransferEventMode; /*!< This field specify the transfer event mode. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. */ + + uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. */ + + uint32_t TriggerSelection; /*!< This field specify the trigger event selection. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. */ + + uint32_t TriggerMode; /*!< This field specify the trigger mode. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. */ + + uint32_t BlkHWRequest; /*!< This field specify the hardware request unity. + This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. */ + + uint32_t Direction; /*!< This field specify the transfer direction. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. */ + + uint32_t Request; /*!< This field specify the peripheral request selection. + This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */ + + uint32_t Mode; /*!< This field DMA Transfer Mode. + This parameter can be a value of @ref DMA_LL_TRANSFER_MODE. */ + + /* CBR1 register fields ****************************************************** + If any CBR1 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CBR1 register fields and enable update + CBR1 register in UpdateRegisters fields if it is not enabled in the + previous node. + + If the node to be created is not for 2D addressing channels, there is no + need to fill the following fields for CBR1 register : + - BlkReptDestAddrUpdate. + - BlkRptSrcAddrUpdate. + - DestAddrUpdate. + - SrcAddrUpdate. + - BlkRptCount. + */ + uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode. + This parameter can be a value of + @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. */ + + uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode. + This parameter can be a value of + @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. */ + + uint32_t DestAddrUpdateMode; /*!< This field specify the Destination address update mode. + This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. */ + + uint32_t SrcAddrUpdateMode; /*!< This field specify the Source address update mode. + This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. */ + + uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block. + This parameter can be a value between 1 and 2048 Min_Data = 0 + and Max_Data = 0x000007FF. */ + + uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes. + This parameter must be a value between Min_Data = 0 + and Max_Data = 0x0000FFFF. */ + + /* CSAR register fields ****************************************************** + If any CSAR fields need to be updated comparing to previous node, it is + mandatory to update the new value in CSAR register fields and enable update + CSAR register in UpdateRegisters fields if it is not enabled in the + previous node. + + For all node created, filling all fields is mandatory. + */ + uint32_t SrcAddress; /*!< This field specify the transfer source address. + This parameter must be a value between Min_Data = 0 + and Max_Data = 0xFFFFFFFF. */ + + + /* CDAR register fields ****************************************************** + If any CDAR fields need to be updated comparing to previous node, it is + mandatory to update the new value in CDAR register fields and enable update + CDAR register in UpdateRegisters fields if it is not enabled in the + previous node. + + For all node created, filling all fields is mandatory. + */ + uint32_t DestAddress; /*!< This field specify the transfer destination address. + This parameter must be a value between Min_Data = 0 + and Max_Data = 0xFFFFFFFF. */ + + /* CTR3 register fields ****************************************************** + If any CTR3 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CTR3 register fields and enable update + CTR3 register in UpdateRegisters fields if it is not enabled in the + previous node. + + This register is used only for 2D addressing channels. + If used channel is linear addressing, this register will be overwritten by + CLLR register in memory. + When this register is enabled on UpdateRegisters and the selected channel + is linear addressing, LL APIs will discard this register update in memory. + */ + uint32_t DestAddrOffset; /*!< This field specifies the destination address offset. + This parameter can be a value Between 0 to 0x00001FFF. */ + + uint32_t SrcAddrOffset; /*!< This field specifies the source address offset. + This parameter can be a value Between 0 to 0x00001FFF. */ + + + /* CBR2 register fields ****************************************************** + If any CBR2 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CBR2 register fields and enable update + CBR2 register in UpdateRegisters fields if it is not enabled in the + previous node. + + This register is used only for 2D addressing channels. + If used channel is linear addressing, this register will be discarded in + memory. When this register is enabled on UpdateRegisters and the selected + channel is linear addressing, LL APIs will discard this register update in + memory. + */ + uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset. + This parameter can be a value Between 0 to 0x0000FFFF. */ + + uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset. + This parameter can be a value Between 0 to 0x0000FFFF. */ + + /* CLLR register fields ****************************************************** + If any CLLR fields need to be updated comparing to previous node, it is + mandatory to update the new value in CLLR register fields and enable update + CLLR register in UpdateRegisters fields if it is not enabled in the + previous node. + + If used channel is linear addressing, there is no need to enable/disable + CTR3 and CBR2 register in UpdateRegisters fields as they will be discarded + by LL APIs. + */ + uint32_t UpdateRegisters; /*!< Specifies the linked list register update. + This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE. */ + + /* DMA Node type field ******************************************************* + This parameter defines node types as node size and node content varies + between channels. + Thanks to this fields, linked list queue could be created independently + from channel selection. So, one queue could be executed by all DMA channels. + */ + uint32_t NodeType; /*!< Specifies the node type to be created. + This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE. */ +} LL_DMA_InitNodeTypeDef; + +/** + * @brief LL DMA linked list node structure definition. + * @note For 2D addressing channels, the maximum node size is : + * (4 Bytes * 8 registers = 32 Bytes). + * For GPDMA & HPDMA linear addressing channels, the maximum node size is : + * (4 Bytes * 6 registers = 24 Bytes). + */ +typedef struct +{ + __IO uint32_t LinkRegisters[8U]; + +} LL_DMA_LinkNodeTypeDef; +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_LL_EC_CHANNEL Channel + * @{ + */ +#define LL_DMA_CHANNEL_0 (0x00U) +#define LL_DMA_CHANNEL_1 (0x01U) +#define LL_DMA_CHANNEL_2 (0x02U) +#define LL_DMA_CHANNEL_3 (0x03U) +#define LL_DMA_CHANNEL_4 (0x04U) +#define LL_DMA_CHANNEL_5 (0x05U) +#define LL_DMA_CHANNEL_6 (0x06U) +#define LL_DMA_CHANNEL_7 (0x07U) +#define LL_DMA_CHANNEL_8 (0x08U) +#define LL_DMA_CHANNEL_9 (0x09U) +#define LL_DMA_CHANNEL_10 (0x0AU) +#define LL_DMA_CHANNEL_11 (0x0BU) +#define LL_DMA_CHANNEL_12 (0x0CU) +#define LL_DMA_CHANNEL_13 (0x0DU) +#define LL_DMA_CHANNEL_14 (0x0EU) +#define LL_DMA_CHANNEL_15 (0x0FU) +#if defined (USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL (0x10U) +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset + * @{ + */ +#define LL_DMA_CLLR_OFFSET0 (0x00U) +#define LL_DMA_CLLR_OFFSET1 (0x01U) +#define LL_DMA_CLLR_OFFSET2 (0x02U) +#define LL_DMA_CLLR_OFFSET3 (0x03U) +#define LL_DMA_CLLR_OFFSET4 (0x04U) +#define LL_DMA_CLLR_OFFSET5 (0x05U) +#define LL_DMA_CLLR_OFFSET6 (0x06U) +#define LL_DMA_CLLR_OFFSET7 (0x07U) +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level + * @{ + */ +#define LL_DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low Weight */ +#define LL_DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight */ +#define LL_DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */ +#define LL_DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : High Priority */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port + * @{ + */ +#define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */ +#define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode + * @{ + */ +#define LL_DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel execute the full linked list */ +#define LL_DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel execute one node of the linked list */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DEST_WORD_EXCHANGE Destination Word Exchange + * @{ + */ +#define LL_DMA_DEST_WORD_PRESERVE 0x00000000U /*!< No destination Word exchange when destination data width + is double-word */ +#define LL_DMA_DEST_WORD_EXCHANGE DMA_CTR1_DWX /*!< Destination Word exchange when destination data width + is double-word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DEST_HALFWORD_EXCHANGE Destination Half-Word Exchange + * @{ + */ +#define LL_DMA_DEST_HALFWORD_PRESERVE 0x00000000U /*!< No destination Half-Word exchange when destination data width + is word */ +#define LL_DMA_DEST_HALFWORD_EXCHANGE DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width + is word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DEST_BYTE_EXCHANGE Destination Byte Exchange + * @{ + */ +#define LL_DMA_DEST_BYTE_PRESERVE 0x00000000U /*!< No destination Byte exchange when destination data width > Byte */ +#define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange + * @{ + */ +#define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U /*!< No source Byte exchange when source data width is word */ +#define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port + * @{ + */ +#define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */ +#define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port + * @{ + */ +#define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */ +#define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode + * @{ + */ +#define LL_DMA_DEST_FIXED 0x00000000U /*!< Destination fixed single/burst */ +#define LL_DMA_DEST_INCREMENT DMA_CTR1_DINC /*!< Destination incremented single/burst */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width + * @{ + */ +#define LL_DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination Data Width : Byte */ +#define LL_DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord */ +#define LL_DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word */ +#define LL_DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2 /*!< Destination Data Width : DoubleWord */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment + * @{ + */ +#define LL_DMA_DATA_ALIGN_ZEROPADD 0x00000000U /*!< If src data width < dest data width : + => Right Aligned padded with 0 up to destination + data width. + If src data width > dest data width : + => Right Aligned Left Truncated down to destination + data width. */ +#define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width : + => Right Aligned padded with sign extended up to destination + data width. + If src data width > dest data width : + => Left Aligned Right Truncated down to the destination + data width */ +#define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width : + => Packed at the destination data width + If src data width > dest data width : + => Unpacked at the destination data width */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode + * @{ + */ +#define LL_DMA_SRC_FIXED 0x00000000U /*!< Source fixed single/burst */ +#define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width + * @{ + */ +#define LL_DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source Data Width : Byte */ +#define LL_DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord */ +#define LL_DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word */ +#define LL_DMA_SRC_DATAWIDTH_DOUBLEWORD DMA_CTR1_SDW_LOG2 /*!< Source Data Width : DoubleWord */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request + * @{ + */ +#define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U /*!< Hardware request is driven by a peripheral with a hardware + request/acknowledge protocol at a burst level */ +#define LL_DMA_HWREQUEST_BLK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware + request/acknowledge protocol at a block level */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode + * @{ + */ +#define LL_DMA_TCEM_BLK_TRANSFER 0x00000000U /*!< The TC (and the HT) event is generated at the + (respectively half) end of each block */ +#define LL_DMA_TCEM_RPT_BLK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC (and the HT) event is generated at the + (respectively half) end of the repeated block */ +#define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated at the + (respectively half) end of each linked-list item */ +#define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the + (respectively half) end of the last linked-list item */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity + * @{ + */ +#define LL_DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. + Masked trigger event */ +#define LL_DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising + edge of the selected trigger event input */ +#define LL_DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling + edge of the selected trigger event input */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode + * @{ + */ +#define LL_DMA_TRIGM_BLK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) + one hit trigger */ +#define LL_DMA_TRIGM_RPT_BLK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) + one hit trigger */ +#define LL_DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) + one hit trigger */ +#define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned by (at least) + one hit trigger */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_TRANSFER_MODE Transfer Mode + * @{ + */ +#define LL_DMA_NORMAL 0x00000000U /*!< Normal DMA transfer */ +#define LL_DMA_PFCTRL DMA_CTR2_PFREQ /*!< HW request peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE Block Repeat Source Address Update Mode + * @{ + */ +#define LL_DMA_BLKRPT_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each block + transfer by source update value */ +#define LL_DMA_BLKRPT_SRC_ADDR_DECREMENT DMA_CBR1_BRSDEC /*!< Source address pointer is decremented after each block + transfer by source update value */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE Block Repeat Destination Address Update Mode + * @{ + */ +#define LL_DMA_BLKRPT_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address is incremented after each block + transfer by destination update value */ +#define LL_DMA_BLKRPT_DEST_ADDR_DECREMENT DMA_CBR1_BRDDEC /*!< Destination address is decremented after each block + transfer by destination update value */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SRC_ADDR_UPDATE_MODE Burst Source Address Update Mode + * @{ + */ +#define LL_DMA_BURST_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each burst + transfer by source update value */ +#define LL_DMA_BURST_SRC_ADDR_DECREMENT DMA_CBR1_SDEC /*!< Source address pointer is decremented after each burst + transfer by source update value */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DEST_ADDR_UPDATE_MODE Burst Destination Address Update Mode + * @{ + */ +#define LL_DMA_BURST_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address pointer is incremented after each + burst transfer by destination update value */ +#define LL_DMA_BURST_DEST_ADDR_DECREMENT DMA_CBR1_DDEC /*!< Destination address pointer is decremented after each + burst transfer by destination update value */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type + * @{ + */ +#define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */ +#define LL_DMA_GPDMA_2D_NODE 0x02U /*!< GPDMA node : 2 dimension addressing node */ +#define LL_DMA_HPDMA_LINEAR_NODE 0x04U /*!< HPDMA node : linear addressing node */ +#define LL_DMA_HPDMA_2D_NODE 0x08U /*!< HPDMA node : 2 dimension addressing node */ + +/** + * @} + */ + +/** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update + * @{ + */ +#define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory : + available only for 2D addressing DMA channels */ +#define LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2 /*!< Update CBR2 register from memory : + available only for 2D addressing DMA channels */ +#define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory : + available for all DMA channels */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection + * @{ + */ +/* HPDMA1 requests */ +#define LL_HPDMA1_REQUEST_JPEG_RX 0U /*!< HPDMA1 HW request is JPEG_RX */ +#define LL_HPDMA1_REQUEST_JPEG_TX 1U /*!< HPDMA1 HW request is JPEG_TX */ +#define LL_HPDMA1_REQUEST_XSPI1 2U /*!< HPDMA1 HW request is XSPI1 */ +#define LL_HPDMA1_REQUEST_XSPI2 3U /*!< HPDMA1 HW request is XSPI2 */ +#define LL_HPDMA1_REQUEST_SPI3_RX 4U /*!< HPDMA1 HW request is SPI3_RX */ +#define LL_HPDMA1_REQUEST_SPI3_TX 5U /*!< HPDMA1 HW request is SPI3_TX */ +#define LL_HPDMA1_REQUEST_SPI4_RX 6U /*!< HPDMA1 HW request is SPI4_RX */ +#define LL_HPDMA1_REQUEST_SPI4_TX 7U /*!< HPDMA1 HW request is SPI4_TX */ +#define LL_HPDMA1_REQUEST_ADC1 8U /*!< HPDMA1 HW request is ADC1 */ +#define LL_HPDMA1_REQUEST_ADC2 9U /*!< HPDMA1 HW request is ADC2 */ +#define LL_HPDMA1_REQUEST_ADF1_FLT0 10U /*!< HPDMA1 HW request is ADF1_FLT0 */ +#define LL_HPDMA1_REQUEST_UART4_RX 11U /*!< HPDMA1 HW request is UART4_RX */ +#define LL_HPDMA1_REQUEST_UART4_TX 12U /*!< HPDMA1 HW request is UART4_TX */ +#define LL_HPDMA1_REQUEST_UART5_RX 13U /*!< HPDMA1 HW request is UART5_RX */ +#define LL_HPDMA1_REQUEST_UART5_TX 14U /*!< HPDMA1 HW request is UART5_TX */ +#define LL_HPDMA1_REQUEST_UART7_RX 15U /*!< HPDMA1 HW request is UART7_RX */ +#define LL_HPDMA1_REQUEST_UART7_TX 16U /*!< HPDMA1 HW request is UART7_TX */ +#define LL_HPDMA1_REQUEST_LPTIM2_IC1 17U /*!< HPDMA1 HW request is LPTIM2_IC1 */ +#define LL_HPDMA1_REQUEST_LPTIM2_IC2 18U /*!< HPDMA1 HW request is LPTIM2_IC2 */ +#define LL_HPDMA1_REQUEST_LPTIM2_UE 19U /*!< HPDMA1 HW request is LPTIM2_UE */ + +/* GPDMA1 requests */ +#define LL_GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */ +#define LL_GPDMA1_REQUEST_ADC2 1U /*!< GPDMA1 HW request is ADC2 */ +#define LL_GPDMA1_REQUEST_CRYP_IN 2U /*!< GPDMA1 HW request is CRYP_IN */ +#define LL_GPDMA1_REQUEST_CRYP_OUT 3U /*!< GPDMA1 HW request is CRYP_OUT */ +#define LL_GPDMA1_REQUEST_SAES_IN 4U /*!< GPDMA1 HW request is SAES_IN */ +#define LL_GPDMA1_REQUEST_SAES_OUT 5U /*!< GPDMA1 HW request is SAES_OUT */ +#define LL_GPDMA1_REQUEST_HASH_IN 6U /*!< GPDMA1 HW request is HASH_IN */ +#define LL_GPDMA1_REQUEST_TIM1_CH1 7U /*!< GPDMA1 HW request is TIM1_CH1 */ +#define LL_GPDMA1_REQUEST_TIM1_CH2 8U /*!< GPDMA1 HW request is TIM1_CH2 */ +#define LL_GPDMA1_REQUEST_TIM1_CH3 9U /*!< GPDMA1 HW request is TIM1_CH3 */ +#define LL_GPDMA1_REQUEST_TIM1_CH4 10U /*!< GPDMA1 HW request is TIM1_CH4 */ +#define LL_GPDMA1_REQUEST_TIM1_UP 11U /*!< GPDMA1 HW request is TIM1_UP */ +#define LL_GPDMA1_REQUEST_TIM1_TRIG 12U /*!< GPDMA1 HW request is TIM1_TRIG */ +#define LL_GPDMA1_REQUEST_TIM1_COM 13U /*!< GPDMA1 HW request is TIM1_COM */ +#define LL_GPDMA1_REQUEST_TIM2_CH1 14U /*!< GPDMA1 HW request is TIM2_CH1 */ +#define LL_GPDMA1_REQUEST_TIM2_CH2 15U /*!< GPDMA1 HW request is TIM2_CH2 */ +#define LL_GPDMA1_REQUEST_TIM2_CH3 16U /*!< GPDMA1 HW request is TIM2_CH3 */ +#define LL_GPDMA1_REQUEST_TIM2_CH4 17U /*!< GPDMA1 HW request is TIM2_CH4 */ +#define LL_GPDMA1_REQUEST_TIM2_UP 18U /*!< GPDMA1 HW request is TIM2_UP */ +#define LL_GPDMA1_REQUEST_TIM2_TRIG 19U /*!< GPDMA1 HW request is TIM2_TRIG */ +#define LL_GPDMA1_REQUEST_TIM3_CH1 20U /*!< GPDMA1 HW request is TIM3_CH1 */ +#define LL_GPDMA1_REQUEST_TIM3_CH2 21U /*!< GPDMA1 HW request is TIM3_CH2 */ +#define LL_GPDMA1_REQUEST_TIM3_CH3 22U /*!< GPDMA1 HW request is TIM3_CH3 */ +#define LL_GPDMA1_REQUEST_TIM3_CH4 23U /*!< GPDMA1 HW request is TIM3_CH4 */ +#define LL_GPDMA1_REQUEST_TIM3_UP 24U /*!< GPDMA1 HW request is TIM3_UP */ +#define LL_GPDMA1_REQUEST_TIM3_TRIG 25U /*!< GPDMA1 HW request is TIM3_TRIG */ +#define LL_GPDMA1_REQUEST_TIM4_CH1 26U /*!< GPDMA1 HW request is TIM4_CH1 */ +#define LL_GPDMA1_REQUEST_TIM4_CH2 27U /*!< GPDMA1 HW request is TIM4_CH2 */ +#define LL_GPDMA1_REQUEST_TIM4_CH3 28U /*!< GPDMA1 HW request is TIM4_CH3 */ +#define LL_GPDMA1_REQUEST_TIM4_CH4 29U /*!< GPDMA1 HW request is TIM4_CH4 */ +#define LL_GPDMA1_REQUEST_TIM4_UP 30U /*!< GPDMA1 HW request is TIM4_UP */ +#define LL_GPDMA1_REQUEST_TIM4_TRIG 31U /*!< GPDMA1 HW request is TIM4_TRIG */ +#define LL_GPDMA1_REQUEST_TIM5_CH1 32U /*!< GPDMA1 HW request is TIM5_CH1 */ +#define LL_GPDMA1_REQUEST_TIM5_CH2 33U /*!< GPDMA1 HW request is TIM5_CH2 */ +#define LL_GPDMA1_REQUEST_TIM5_CH3 34U /*!< GPDMA1 HW request is TIM5_CH3 */ +#define LL_GPDMA1_REQUEST_TIM5_CH4 35U /*!< GPDMA1 HW request is TIM5_CH4 */ +#define LL_GPDMA1_REQUEST_TIM5_UP 36U /*!< GPDMA1 HW request is TIM5_UP */ +#define LL_GPDMA1_REQUEST_TIM5_TRIG 37U /*!< GPDMA1 HW request is TIM5_TRIG */ +#define LL_GPDMA1_REQUEST_TIM6_UP 38U /*!< GPDMA1 HW request is TIM6_UP */ +#define LL_GPDMA1_REQUEST_TIM7_UP 39U /*!< GPDMA1 HW request is TIM7_UP */ +#define LL_GPDMA1_REQUEST_TIM15_CH1 40U /*!< GPDMA1 HW request is TIM15_CH1 */ +#define LL_GPDMA1_REQUEST_TIM15_CH2 41U /*!< GPDMA1 HW request is TIM15_CH2 */ +#define LL_GPDMA1_REQUEST_TIM15_UP 42U /*!< GPDMA1 HW request is TIM15_UP */ +#define LL_GPDMA1_REQUEST_TIM15_TRIG 43U /*!< GPDMA1 HW request is TIM15_TRIG */ +#define LL_GPDMA1_REQUEST_TIM15_COM 44U /*!< GPDMA1 HW request is TIM15_COM */ +#define LL_GPDMA1_REQUEST_TIM16_CH1 45U /*!< GPDMA1 HW request is TIM16_CH1 */ +#define LL_GPDMA1_REQUEST_TIM16_UP 46U /*!< GPDMA1 HW request is TIM16_UP */ +#define LL_GPDMA1_REQUEST_TIM16_COM 47U /*!< GPDMA1 HW request is TIM16_COM */ +#define LL_GPDMA1_REQUEST_TIM17_CH1 48U /*!< GPDMA1 HW request is TIM17_CH1 */ +#define LL_GPDMA1_REQUEST_TIM17_UP 49U /*!< GPDMA1 HW request is TIM17_UP */ +#define LL_GPDMA1_REQUEST_TIM17_COM 50U /*!< GPDMA1 HW request is TIM17_COM */ +#define LL_GPDMA1_REQUEST_SPI1_RX 51U /*!< GPDMA1 HW request is SPI1_RX */ +#define LL_GPDMA1_REQUEST_SPI1_TX 52U /*!< GPDMA1 HW request is SPI1_TX */ +#define LL_GPDMA1_REQUEST_SPI2_RX 53U /*!< GPDMA1 HW request is SPI2_RX */ +#define LL_GPDMA1_REQUEST_SPI2_TX 54U /*!< GPDMA1 HW request is SPI2_TX */ +#define LL_GPDMA1_REQUEST_SPI3_RX 55U /*!< GPDMA1 HW request is SPI3_RX */ +#define LL_GPDMA1_REQUEST_SPI3_TX 56U /*!< GPDMA1 HW request is SPI3_TX */ +#define LL_GPDMA1_REQUEST_SPI4_RX 57U /*!< GPDMA1 HW request is SPI4_RX */ +#define LL_GPDMA1_REQUEST_SPI4_TX 58U /*!< GPDMA1 HW request is SPI4_TX */ +#define LL_GPDMA1_REQUEST_SPI5_RX 59U /*!< GPDMA1 HW request is SPI5_RX */ +#define LL_GPDMA1_REQUEST_SPI5_TX 60U /*!< GPDMA1 HW request is SPI5_TX */ +#define LL_GPDMA1_REQUEST_SPI6_RX 61U /*!< GPDMA1 HW request is SPI6_RX */ +#define LL_GPDMA1_REQUEST_SPI6_TX 62U /*!< GPDMA1 HW request is SPI6_TX */ +#define LL_GPDMA1_REQUEST_SAI1_A 63U /*!< GPDMA1 HW request is SAI1_A */ +#define LL_GPDMA1_REQUEST_SAI1_B 64U /*!< GPDMA1 HW request is SAI1_B */ +#define LL_GPDMA1_REQUEST_SAI2_A 65U /*!< GPDMA1 HW request is SAI2_A */ +#define LL_GPDMA1_REQUEST_SAI2_B 66U /*!< GPDMA1 HW request is SAI2_B */ +#define LL_GPDMA1_REQUEST_I2C1_RX 67U /*!< GPDMA1 HW request is I2C1_RX */ +#define LL_GPDMA1_REQUEST_I2C1_TX 68U /*!< GPDMA1 HW request is I2C1_TX */ +#define LL_GPDMA1_REQUEST_I2C2_RX 69U /*!< GPDMA1 HW request is I2C2_RX */ +#define LL_GPDMA1_REQUEST_I2C2_TX 70U /*!< GPDMA1 HW request is I2C2_TX */ +#define LL_GPDMA1_REQUEST_I2C3_RX 71U /*!< GPDMA1 HW request is I2C3_RX */ +#define LL_GPDMA1_REQUEST_I2C3_TX 72U /*!< GPDMA1 HW request is I2C3_TX */ +#define LL_GPDMA1_REQUEST_USART1_RX 73U /*!< GPDMA1 HW request is USART1_RX */ +#define LL_GPDMA1_REQUEST_USART1_TX 74U /*!< GPDMA1 HW request is USART1_TX */ +#define LL_GPDMA1_REQUEST_USART2_RX 75U /*!< GPDMA1 HW request is USART2_RX */ +#define LL_GPDMA1_REQUEST_USART2_TX 76U /*!< GPDMA1 HW request is USART2_TX */ +#define LL_GPDMA1_REQUEST_USART3_RX 77U /*!< GPDMA1 HW request is USART3_RX */ +#define LL_GPDMA1_REQUEST_USART3_TX 78U /*!< GPDMA1 HW request is USART3_TX */ +#define LL_GPDMA1_REQUEST_UART4_RX 79U /*!< GPDMA1 HW request is UART4_RX */ +#define LL_GPDMA1_REQUEST_UART4_TX 80U /*!< GPDMA1 HW request is UART4_TX */ +#define LL_GPDMA1_REQUEST_UART5_RX 81U /*!< GPDMA1 HW request is UART5_RX */ +#define LL_GPDMA1_REQUEST_UART5_TX 82U /*!< GPDMA1 HW request is UART5_TX */ +#define LL_GPDMA1_REQUEST_UART7_RX 83U /*!< GPDMA1 HW request is UART7_RX */ +#define LL_GPDMA1_REQUEST_UART7_TX 84U /*!< GPDMA1 HW request is UART7_TX */ +#define LL_GPDMA1_REQUEST_UART8_RX 85U /*!< GPDMA1 HW request is UART8_RX */ +#define LL_GPDMA1_REQUEST_UART8_TX 86U /*!< GPDMA1 HW request is UART8_TX */ +#define LL_GPDMA1_REQUEST_CORDIC_READ 87U /*!< GPDMA1 HW request is CORDIC_READ */ +#define LL_GPDMA1_REQUEST_CORDIC_WRITE 88U /*!< GPDMA1 HW request is CORDIC_WRITE */ +#define LL_GPDMA1_REQUEST_LPTIM1_IC1 89U /*!< GPDMA1 HW request is LPTIM1_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM1_IC2 90U /*!< GPDMA1 HW request is LPTIM1_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM1_UE 91U /*!< GPDMA1 HW request is LPTIM1_UE */ +#define LL_GPDMA1_REQUEST_LPTIM2_IC1 92U /*!< GPDMA1 HW request is LPTIM2_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM2_IC2 93U /*!< GPDMA1 HW request is LPTIM2_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM2_UE 94U /*!< GPDMA1 HW request is LPTIM2_UE */ +#define LL_GPDMA1_REQUEST_SPDIF_RX_DT 95U /*!< GPDMA1 HW request is SPDIF_RX_DT */ +#define LL_GPDMA1_REQUEST_SPDIF_RX_CS 96U /*!< GPDMA1 HW request is SPDIF_RX_CS */ +#define LL_GPDMA1_REQUEST_ADF1_FLT0 97U /*!< GPDMA1 HW request is ADF1_FLT0 */ +#define LL_GPDMA1_REQUEST_UCPD1_TX 98U /*!< GPDMA1 HW request is UCPD1_TX */ +#define LL_GPDMA1_REQUEST_UCPD1_RX 99U /*!< GPDMA1 HW request is USBPD_RX */ +#define LL_GPDMA1_REQUEST_PSSI 100U /*!< GPDMA1 HW request is PSSI */ +#define LL_GPDMA1_REQUEST_LPUART1_RX 101U /*!< GPDMA1 HW request is LPUART1_RX */ +#define LL_GPDMA1_REQUEST_LPUART1_TX 102U /*!< GPDMA1 HW request is LPUART1_TX */ +#define LL_GPDMA1_REQUEST_LPTIM3_IC1 103U /*!< GPDMA1 HW request is LPTIM3_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM3_IC2 104U /*!< GPDMA1 HW request is LPTIM3_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM3_UE 105U /*!< GPDMA1 HW request is LPTIM3_UE */ +#define LL_GPDMA1_REQUEST_I3C1_RX 106U /*!< GPDMA1 HW request is I3C1_RX */ +#define LL_GPDMA1_REQUEST_I3C1_TX 107U /*!< GPDMA1 HW request is I3C1_TX */ +#define LL_GPDMA1_REQUEST_I3C1_TC 108U /*!< GPDMA1 HW request is I3C1_TC */ +#define LL_GPDMA1_REQUEST_I3C1_RS 109U /*!< GPDMA1 HW request is I3C1_RS */ + +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection + * @{ + */ +/* HPDMA1 triggers */ +#define LL_HPDMA1_TRIGGER_DCMIPP_EVT_FRAMEEND 0U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_FRAMEEND */ +#define LL_HPDMA1_TRIGGER_DCMIPP_EVT_HSYNC 1U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_HSYNC */ +#define LL_HPDMA1_TRIGGER_DCMIPP_EVT_LINEEND 2U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_LINEEND */ +#define LL_HPDMA1_TRIGGER_DCMIPP_EVT_VSYNC 3U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_VSYNC */ +#define LL_HPDMA1_TRIGGER_DMA2D_CTC_FLAG 4U /*!< HPDMA1 HW Trigger signal is DMA2D_CTC_FLAG */ +#define LL_HPDMA1_TRIGGER_DMA2D_TC_FLAG 5U /*!< HPDMA1 HW Trigger signal is DMA2D_TC_FLAG */ +#define LL_HPDMA1_TRIGGER_DMA2D_TW_FLAG 6U /*!< HPDMA1 HW Trigger signal is DMA2D_TW_FLAG */ +#define LL_HPDMA1_TRIGGER_JPEG_EOC_FLAG 7U /*!< HPDMA1 HW Trigger signal is JPEG_EOC_FLAG */ +#define LL_HPDMA1_TRIGGER_JPEG_IFNF_FLAG 8U /*!< HPDMA1 HW Trigger signal is JPEG_IFNF_FLAG */ +#define LL_HPDMA1_TRIGGER_JPEG_IFT_FLAG 9U /*!< HPDMA1 HW Trigger signal is JPEG_IFT_FLAG */ +#define LL_HPDMA1_TRIGGER_JPEG_OFNE_FLAG 10U /*!< HPDMA1 HW Trigger signal is JPEG_OFNE_FLAG */ +#define LL_HPDMA1_TRIGGER_JPEG_OFT_FLAG 11U /*!< HPDMA1 HW Trigger signal is JPEG_OFT_FLAG */ +#define LL_HPDMA1_TRIGGER_LCD 12U /*!< HPDMA1 HW Trigger signal is LCD */ +#define LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG0 13U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG0 */ +#define LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG1 14U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG1 */ +#define LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG2 15U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG2 */ +#define LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG3 16U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG3 */ +#define LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_4 17U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_4 */ +#define LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_3 18U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_3 */ +#define LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_2 19U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_2 */ +#define LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_1 20U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_1 */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH0_TCF 21U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH1_TCF 22U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH2_TCF 23U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH3_TCF 24U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH4_TCF 25U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH5_TCF 26U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH6_TCF 27U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH7_TCF 28U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH8_TCF 29U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH9_TCF 30U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH10_TCF 31U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH11_TCF 32U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH12_TCF 33U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH13_TCF 34U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH14_TCF 35U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ +#define LL_HPDMA1_TRIGGER_GPDMA1_CH15_TCF 36U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH0_TCF 37U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH1_TCF 38U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH2_TCF 39U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH3_TCF 40U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH4_TCF 41U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH5_TCF 42U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH6_TCF 43U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH7_TCF 44U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH8_TCF 45U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH9_TCF 46U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH10_TCF 47U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH11_TCF 48U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH12_TCF 49U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH13_TCF 50U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH14_TCF 51U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */ +#define LL_HPDMA1_TRIGGER_HPDMA1_CH15_TCF 52U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */ + +/* GPDMA1 triggers */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH0_TCF 0U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH1_TCF 1U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH2_TCF 2U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH3_TCF 3U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH4_TCF 4U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH5_TCF 5U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH6_TCF 6U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH7_TCF 7U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH8_TCF 8U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH9_TCF 9U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH10_TCF 10U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH11_TCF 11U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH12_TCF 12U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH13_TCF 13U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH14_TCF 14U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */ +#define LL_GPDMA1_TRIGGER_HPDMA1_CH15_TCF 15U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */ +#define LL_GPDMA1_TRIGGER_LPTIM1_CH1 16U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM1_CH2 17U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#define LL_GPDMA1_TRIGGER_LPTIM2_CH1 18U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM2_CH2 19U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ +#define LL_GPDMA1_TRIGGER_LPTIM3_CH1 20U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM3_CH2 21U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */ +#define LL_GPDMA1_TRIGGER_LPTIM4_OUT 22U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */ +#define LL_GPDMA1_TRIGGER_LPTIM5_OUT 23U /*!< GPDMA1 HW Trigger signal is LPTIM5_OUT */ +#define LL_GPDMA1_TRIGGER_EXTIT0_SYNC 24U /*!< GPDMA1 HW Trigger signal is EXTIT0_SYNC */ +#define LL_GPDMA1_TRIGGER_RTC_WKUP 25U /*!< GPDMA1 HW Trigger signal is RTC_WKUP */ +#define LL_GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC 26U /*!< GPDMA1 HW Trigger signal is R_WUP_ASYNC */ +#define LL_GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC 27U /*!< GPDMA1 HW Trigger signal is T_WUP_ASYNC */ +#define LL_GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 28U /*!< GPDMA1 HW Trigger signal is SPI6_OR_SPI6_AIT_SYNC */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 34U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 35U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 36U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF 37U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF 38U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF 39U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF 40U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF 41U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF 42U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF 43U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF 44U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ +#define LL_GPDMA1_TRIGGER_TIM1_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM1_TRGO2 46U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO2 */ +#define LL_GPDMA1_TRIGGER_TIM2_TRGO 47U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM3_TRGO 48U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM4_TRGO 49U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM5_TRGO 50U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM6_TRGO 51U /*!< GPDMA1 HW Trigger signal is TIM6_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM7_TRGO 52U /*!< GPDMA1 HW Trigger signal is TIM7_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM9_TRGO 53U /*!< GPDMA1 HW Trigger signal is TIM9_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM12_TRGO 54U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */ +#define LL_GPDMA1_TRIGGER_TIM15_TRGO 55U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros + * @{ + */ +/** + * @brief Write a value in DMA register. + * @param __INSTANCE__ DMA Instance. + * @param __REG__ Register to be written. + * @param __VALUE__ Value to be written in the register. + * @retval None. + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register. + * @param __INSTANCE__ DMA Instance. + * @param __REG__ Register to be read. + * @retval Register value. + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx. + * @param __CHANNEL_INSTANCE__ DMAx_Channely. + * @retval DMAx. + */ +#define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)GPDMA1_Channel15)) ? HPDMA1 : GPDMA1) + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y. + * @param __CHANNEL_INSTANCE__ DMAx_Channely. + * @retval LL_DMA_CHANNEL_y. + */ +#define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel8)) ? LL_DMA_CHANNEL_8 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel8)) ? LL_DMA_CHANNEL_8 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel9)) ? LL_DMA_CHANNEL_9 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel9)) ? LL_DMA_CHANNEL_9 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel12)) ? LL_DMA_CHANNEL_12 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel12)) ? LL_DMA_CHANNEL_12 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel13)) ? LL_DMA_CHANNEL_13 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel13)) ? LL_DMA_CHANNEL_13 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel14)) ? LL_DMA_CHANNEL_14 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel14)) ? LL_DMA_CHANNEL_14 : \ + LL_DMA_CHANNEL_15) + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely. + * @param __DMA_INSTANCE__ DMAx. + * @param __CHANNEL__ LL_DMA_CHANNEL_y. + * @retval DMAx_Channely. + */ +#define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? HPDMA1_Channel0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? GPDMA1_Channel0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? HPDMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? GPDMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? HPDMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? GPDMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \ + ? HPDMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \ + ? GPDMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \ + ? HPDMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \ + ? GPDMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \ + ? HPDMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \ + ? GPDMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \ + ? HPDMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \ + ? GPDMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \ + ? HPDMA1_Channel7 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \ + ? GPDMA1_Channel7 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \ + ? HPDMA1_Channel8 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \ + ? GPDMA1_Channel8 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \ + ? HPDMA1_Channel9 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \ + ? GPDMA1_Channel9 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\ + ? HPDMA1_Channel10 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\ + ? GPDMA1_Channel10 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\ + ? HPDMA1_Channel11 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\ + ? GPDMA1_Channel11 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_12)))\ + ? HPDMA1_Channel12 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_12)))\ + ? GPDMA1_Channel12 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_13)))\ + ? HPDMA1_Channel13 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_13)))\ + ? GPDMA1_Channel13 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_14)))\ + ? HPDMA1_Channel14 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_14)))\ + ? GPDMA1_Channel14 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_15)))\ + ? HPDMA1_Channel15 : GPDMA1_Channel15) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance. + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance. + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + (DMA_CCR_SUSP | DMA_CCR_RESET)); +} + +/** + * @brief Check if channel is enabled or disabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN) + == (DMA_CCR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Reset channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR RESET LL_DMA_ResetChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ResetChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET); +} + +/** + * @brief Suspend channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSP LL_DMA_SuspendChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SuspendChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP); +} + +/** + * @brief Resume channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSP LL_DMA_ResumeChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ResumeChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP); +} + +/** + * @brief Check if channel is suspended. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSP LL_DMA_IsSuspendedChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP) + == (DMA_CCR_SUSP)) ? 1UL : 0UL); +} + +/** + * @brief Set linked-list base address. + * @note This API is used for all available DMA channels. + * @rmtoll CLBAR LBA LL_DMA_SetLinkedListBaseAddr + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes + * are always 0) + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t LinkedListBaseAddr) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA, + (LinkedListBaseAddr & DMA_CLBAR_LBA)); +} + +/** + * @brief Get linked-list base address. + * @note This API is used for all available DMA channels. + * @rmtoll CLBAR LBA LL_DMA_GetLinkedListBaseAddr + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0) + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA)); +} + +/** + * @brief Configure all parameters linked to channel control. + * @note This API is used for all available DMA channels. + * @rmtoll CCR PRIO LL_DMA_ConfigControl\n + * CCR LAP LL_DMA_ConfigControl\n + * CCR LSM LL_DMA_ConfigControl + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or + * @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 or @ref LL_DMA_LINK_ALLOCATED_PORT1 + * @arg @ref LL_DMA_LSM_FULL_EXECUTION or @ref LL_DMA_LSM_1LINK_EXECUTION + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration); +} + +/** + * @brief Set priority level. + * @note This API is used for all available DMA channels. + * @rmtoll CCR PRIO LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT + * @arg @ref LL_DMA_HIGH_PRIORITY + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority); +} + +/** + * @brief Get Channel priority level. + * @note This API is used for all available DMA channels. + * @rmtoll CCR PRIO LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT + * @arg @ref LL_DMA_HIGH_PRIORITY + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO)); +} + +/** + * @brief Set linked-list allocated port. + * @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param LinkAllocatedPort This parameter can be one of the following values: + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkAllocatedPort) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_LAP, LinkAllocatedPort); +} + +/** + * @brief Get linked-list allocated port. + * @rmtoll CCR LAP LL_DMA_GetLinkAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP)); +} + +/** + * @brief Set link step mode. + * @note This API is used for all available DMA channels. + * @rmtoll CCR LSM LL_DMA_SetLinkStepMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param LinkStepMode This parameter can be one of the following values: + * @arg @ref LL_DMA_LSM_FULL_EXECUTION + * @arg @ref LL_DMA_LSM_1LINK_EXECUTION + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode); +} + +/** + * @brief Get Link step mode. + * @note This API is used for all available DMA channels. + * @rmtoll CCR LSM LL_DMA_GetLinkStepMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LSM_FULL_EXECUTION + * @arg @ref LL_DMA_LSM_1LINK_EXECUTION + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM)); +} + +/** + * @brief Configure data transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DAP LL_DMA_ConfigTransfer\n + * CTR1 DWX LL_DMA_ConfigTransfer\n + * CTR1 DHX LL_DMA_ConfigTransfer\n + * CTR1 DBX LL_DMA_ConfigTransfer\n + * CTR1 DINC LL_DMA_ConfigTransfer\n + * CTR1 SAP LL_DMA_ConfigTransfer\n + * CTR1 SBX LL_DMA_ConfigTransfer\n + * CTR1 PAM LL_DMA_ConfigTransfer\n + * CTR1 SINC LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 or @ref LL_DMA_DEST_ALLOCATED_PORT1 + * @arg @ref LL_DMA_DEST_WORD_PRESERVE or @ref LL_DMA_DEST_WORD_EXCHANGE + * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE or @ref LL_DMA_DEST_HALFWORD_EXCHANGE + * @arg @ref LL_DMA_DEST_BYTE_PRESERVE or @ref LL_DMA_DEST_BYTE_EXCHANGE + * @arg @ref LL_DMA_SRC_BYTE_PRESERVE or @ref LL_DMA_SRC_BYTE_EXCHANGE + * @arg @ref LL_DMA_DEST_FIXED or @ref LL_DMA_DEST_INCREMENT + * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or + * @ref LL_DMA_DEST_DATAWIDTH_WORD or @ref LL_DMA_DEST_DATAWIDTH_DOUBLEWORD + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 or @ref LL_DMA_SRC_ALLOCATED_PORT1 + * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD or + * @ref LL_DMA_DATA_PACK_UNPACK + * @arg @ref LL_DMA_SRC_FIXED or @ref LL_DMA_SRC_INCREMENT + * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD or + * @ref LL_DMA_SRC_DATAWIDTH_WORD or @ref LL_DMA_SRC_DATAWIDTH_DOUBLEWORD + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + DMA_CTR1_DAP | DMA_CTR1_DWX | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | \ + DMA_CTR1_SINC | DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); +} + +/** + * @brief Configure source and destination burst length. + * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n + * @rmtoll CTR1 SBL_1 LL_DMA_SetDestBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcBurstLength Between 1 to 64 + * @param DestBurstLength Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength, + uint32_t DestBurstLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \ + (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1)); +} + +/** + * @brief Set destination allocated port. + * @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestAllocatedPort This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP, + DestAllocatedPort); +} + +/** + * @brief Get destination allocated port. + * @rmtoll CTR1 DAP LL_DMA_GetDestAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP)); +} + +/** + * @brief Set destination word exchange. + * @rmtoll CTR1 DWX LL_DMA_SetDestWordExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestWordExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_WORD_PRESERVE + * @arg @ref LL_DMA_DEST_WORD_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestWordExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DWX, + DestWordExchange); +} + +/** + * @brief Get destination word exchange. + * @rmtoll CTR1 DWX LL_DMA_GetDestWordExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_WORD_PRESERVE + * @arg @ref LL_DMA_DEST_WORD_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DWX)); +} + +/** + * @brief Set destination half-word exchange. + * @rmtoll CTR1 DHX LL_DMA_SetDestHWordExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestHWordExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE + * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX, + DestHWordExchange); +} + +/** + * @brief Get destination half-word exchange. + * @rmtoll CTR1 DHX LL_DMA_GetDestHWordExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE + * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX)); +} + +/** + * @brief Set destination byte exchange. + * @rmtoll CTR1 DBX LL_DMA_SetDestByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestByteExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_BYTE_PRESERVE + * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX, + DestByteExchange); +} + +/** + * @brief Get destination byte exchange. + * @rmtoll CTR1 DBX LL_DMA_GetDestByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_BYTE_PRESERVE + * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX)); +} + +/** + * @brief Set source byte exchange. + * @rmtoll CTR1 SBX LL_DMA_SetSrcByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcByteExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_BYTE_PRESERVE + * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX, + SrcByteExchange); +} + +/** + * @brief Get source byte exchange. + * @rmtoll CTR1 SBX LL_DMA_GetSrcByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_BYTE_PRESERVE + * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX)); +} + +/** + * @brief Set destination burst length. + * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestBurstLength Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1, + ((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1); +} + +/** + * @brief Get destination burst length. + * @rmtoll CTR1 DBL_1 LL_DMA_GetDestBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 1 to 64. + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U); +} + +/** + * @brief Set destination increment mode. + * @rmtoll CTR1 DINC LL_DMA_SetDestIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestInc This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_FIXED + * @arg @ref LL_DMA_DEST_INCREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc); +} + +/** + * @brief Get destination increment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DINC LL_DMA_GetDestIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_FIXED + * @arg @ref LL_DMA_DEST_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC)); +} + +/** + * @brief Set destination data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestDataWidth This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE + * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD + * @arg @ref LL_DMA_DEST_DATAWIDTH_DOUBLEWORD + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestDataWidth) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2, + DestDataWidth); +} + +/** + * @brief Get destination data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE + * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD + * @arg @ref LL_DMA_DEST_DATAWIDTH_DOUBLEWORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2)); +} + +/** + * @brief Set source allocated port. + * @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcAllocatedPort This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP, + SrcAllocatedPort); +} + +/** + * @brief Get source allocated port. + * @rmtoll CTR1 SAP LL_DMA_GetSrcAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP)); +} + +/** + * @brief Set data alignment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 PAM LL_DMA_SetDataAlignment + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DataAlignment This parameter can be one of the following values: + * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD + * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD + * @arg @ref LL_DMA_DATA_PACK_UNPACK + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM, + DataAlignment); +} + +/** + * @brief Get data alignment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 PAM LL_DMA_GetDataAlignment + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD + * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD + * @arg @ref LL_DMA_DATA_PACK_UNPACK + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM)); +} + +/** + * @brief Set source burst length. + * @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcBurstLength Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1, + ((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1); +} + +/** + * @brief Get source burst length. + * @rmtoll CTR1 SBL_1 LL_DMA_GetSrcBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U); +} + +/** + * @brief Set source increment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SINC LL_DMA_SetSrcIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcInc This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_FIXED + * @arg @ref LL_DMA_SRC_INCREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc); +} + +/** + * @brief Get source increment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SINC LL_DMA_GetSrcIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_FIXED + * @arg @ref LL_DMA_SRC_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC)); +} + +/** + * @brief Set source data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcDataWidth This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE + * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD + * @arg @ref LL_DMA_SRC_DATAWIDTH_DOUBLEWORD + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcDataWidth) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2, + SrcDataWidth); +} + +/** + * @brief Get Source Data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE + * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD + * @arg @ref LL_DMA_SRC_DATAWIDTH_DOUBLEWORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2)); +} + +/** + * @brief Configure channel transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TCEM LL_DMA_ConfigChannelTransfer\n + * CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer\n + * CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n + * CTR2 BREQ LL_DMA_ConfigChannelTransfer\n + * CTR2 DREQ LL_DMA_ConfigChannelTransfer\n + * CTR2 SWREQ LL_DMA_ConfigChannelTransfer\n + * CTR2 PFREQ LL_DMA_ConfigChannelTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or + * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_HWREQUEST_BLK + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or + * @ref LL_DMA_TRIG_POLARITY_FALLING + * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or + * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or + * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_NORMAL or @ref LL_DMA_PFCTRL + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ | + DMA_CTR2_PFREQ), Configuration); +} + +/** + * @brief Set transfer event mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TCEM LL_DMA_SetTransferEventMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param TransferEventMode This parameter can be one of the following values: + * @arg @ref LL_DMA_TCEM_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER + * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM, + TransferEventMode); +} + +/** + * @brief Get transfer event mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TCEM LL_DMA_GetTransferEventMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TCEM_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER + * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER + */ +__STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM)); +} + +/** + * @brief Set trigger polarity. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param TriggerPolarity This parameter can be one of the following values: + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED + * @arg @ref LL_DMA_TRIG_POLARITY_RISING + * @arg @ref LL_DMA_TRIG_POLARITY_FALLING + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL, + TriggerPolarity); +} + +/** + * @brief Get trigger polarity. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED + * @arg @ref LL_DMA_TRIG_POLARITY_RISING + * @arg @ref LL_DMA_TRIG_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL)); +} + +/** + * @brief Set trigger Mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param TriggerMode This parameter can be one of the following values: + * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER + * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER + * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM, + TriggerMode); +} + +/** + * @brief Get trigger Mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGM LL_DMA_GetTriggerMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER + * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER + * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER + */ +__STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM)); +} + +/** + * @brief Set destination hardware and software transfer request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 DREQ LL_DMA_SetDataTransferDirection\n + * @rmtoll CTR2 SWREQ LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction); +} + +/** + * @brief Get destination hardware and software transfer request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 DREQ LL_DMA_GetDataTransferDirection\n + * @rmtoll CTR2 SWREQ LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_DREQ | DMA_CTR2_SWREQ)); +} + +/** + * @brief Set block hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 BREQ LL_DMA_SetBlkHWRequest\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkHWRequest This parameter can be one of the following values: + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST + * @arg @ref LL_DMA_HWREQUEST_BLK + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ, + BlkHWRequest); +} + +/** + * @brief Get block hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 BREQ LL_DMA_GetBlkHWRequest\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST + * @arg @ref LL_DMA_HWREQUEST_BLK + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ)); +} + +/** + * @brief Set hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 REQSEL LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_HPDMA1_REQUEST_JPEG_RX + * @arg @ref LL_HPDMA1_REQUEST_JPEG_TX + * @arg @ref LL_HPDMA1_REQUEST_XSPI1 + * @arg @ref LL_HPDMA1_REQUEST_XSPI2 + * @arg @ref LL_HPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_HPDMA1_REQUEST_SPI4_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI4_TX + * @arg @ref LL_HPDMA1_REQUEST_ADC1 + * @arg @ref LL_HPDMA1_REQUEST_ADC2 + * @arg @ref LL_HPDMA1_REQUEST_ADF1_FLT0 + * @arg @ref LL_HPDMA1_REQUEST_UART4_RX + * @arg @ref LL_HPDMA1_REQUEST_UART4_TX + * @arg @ref LL_HPDMA1_REQUEST_UART5_RX + * @arg @ref LL_HPDMA1_REQUEST_UART5_TX + * @arg @ref LL_HPDMA1_REQUEST_UART7_RX + * @arg @ref LL_HPDMA1_REQUEST_UART7_TX + * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC1 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC2 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_UE + * @arg @ref LL_GPDMA1_REQUEST_ADC1 + * @arg @ref LL_GPDMA1_REQUEST_ADC2 + * @arg @ref LL_GPDMA1_REQUEST_CRYP_IN + * @arg @ref LL_GPDMA1_REQUEST_CRYP_OUT + * @arg @ref LL_GPDMA1_REQUEST_SAES_IN + * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT + * @arg @ref LL_GPDMA1_REQUEST_HASH_IN + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM2_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM4_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM16_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM17_COM + * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI4_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI4_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI5_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI5_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI6_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI6_TX + * @arg @ref LL_GPDMA1_REQUEST_SAI1_A + * @arg @ref LL_GPDMA1_REQUEST_SAI1_B + * @arg @ref LL_GPDMA1_REQUEST_SAI2_A + * @arg @ref LL_GPDMA1_REQUEST_SAI2_B + * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX + * @arg @ref LL_GPDMA1_REQUEST_USART1_RX + * @arg @ref LL_GPDMA1_REQUEST_USART1_TX + * @arg @ref LL_GPDMA1_REQUEST_USART2_RX + * @arg @ref LL_GPDMA1_REQUEST_USART2_TX + * @arg @ref LL_GPDMA1_REQUEST_USART3_RX + * @arg @ref LL_GPDMA1_REQUEST_USART3_TX + * @arg @ref LL_GPDMA1_REQUEST_UART4_RX + * @arg @ref LL_GPDMA1_REQUEST_UART4_TX + * @arg @ref LL_GPDMA1_REQUEST_UART5_RX + * @arg @ref LL_GPDMA1_REQUEST_UART5_TX + * @arg @ref LL_GPDMA1_REQUEST_UART7_RX + * @arg @ref LL_GPDMA1_REQUEST_UART7_TX + * @arg @ref LL_GPDMA1_REQUEST_UART8_RX + * @arg @ref LL_GPDMA1_REQUEST_UART8_TX + * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ + * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE + * @arg @ref LL_GPDMA1_REQUEST_SPDIF_RX_DT + * @arg @ref LL_GPDMA1_REQUEST_SPDIF_RX_CS + * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0 + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX + * @arg @ref LL_GPDMA1_REQUEST_PSSI + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE + * @arg @ref LL_GPDMA1_REQUEST_I3C1_RX + * @arg @ref LL_GPDMA1_REQUEST_I3C1_TX + * @arg @ref LL_GPDMA1_REQUEST_I3C1_TC + * @arg @ref LL_GPDMA1_REQUEST_I3C1_RS + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request); +} + +/** + * @brief Get hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 REQSEL LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_HPDMA1_REQUEST_JPEG_RX + * @arg @ref LL_HPDMA1_REQUEST_JPEG_TX + * @arg @ref LL_HPDMA1_REQUEST_XSPI1 + * @arg @ref LL_HPDMA1_REQUEST_XSPI2 + * @arg @ref LL_HPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_HPDMA1_REQUEST_SPI4_RX + * @arg @ref LL_HPDMA1_REQUEST_SPI4_TX + * @arg @ref LL_HPDMA1_REQUEST_ADC1 + * @arg @ref LL_HPDMA1_REQUEST_ADC2 + * @arg @ref LL_HPDMA1_REQUEST_ADF1_FLT0 + * @arg @ref LL_HPDMA1_REQUEST_UART4_RX + * @arg @ref LL_HPDMA1_REQUEST_UART4_TX + * @arg @ref LL_HPDMA1_REQUEST_UART5_RX + * @arg @ref LL_HPDMA1_REQUEST_UART5_TX + * @arg @ref LL_HPDMA1_REQUEST_UART7_RX + * @arg @ref LL_HPDMA1_REQUEST_UART7_TX + * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC1 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC2 + * @arg @ref LL_HPDMA1_REQUEST_LPTIM2_UE + * @arg @ref LL_GPDMA1_REQUEST_ADC1 + * @arg @ref LL_GPDMA1_REQUEST_ADC2 + * @arg @ref LL_GPDMA1_REQUEST_CRYP_IN + * @arg @ref LL_GPDMA1_REQUEST_CRYP_OUT + * @arg @ref LL_GPDMA1_REQUEST_SAES_IN + * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT + * @arg @ref LL_GPDMA1_REQUEST_HASH_IN + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM2_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM4_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM16_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM17_COM + * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI4_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI4_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI5_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI5_TX + * @arg @ref LL_GPDMA1_REQUEST_SPI6_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI6_TX + * @arg @ref LL_GPDMA1_REQUEST_SAI1_A + * @arg @ref LL_GPDMA1_REQUEST_SAI1_B + * @arg @ref LL_GPDMA1_REQUEST_SAI2_A + * @arg @ref LL_GPDMA1_REQUEST_SAI2_B + * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX + * @arg @ref LL_GPDMA1_REQUEST_USART1_RX + * @arg @ref LL_GPDMA1_REQUEST_USART1_TX + * @arg @ref LL_GPDMA1_REQUEST_USART2_RX + * @arg @ref LL_GPDMA1_REQUEST_USART2_TX + * @arg @ref LL_GPDMA1_REQUEST_USART3_RX + * @arg @ref LL_GPDMA1_REQUEST_USART3_TX + * @arg @ref LL_GPDMA1_REQUEST_UART4_RX + * @arg @ref LL_GPDMA1_REQUEST_UART4_TX + * @arg @ref LL_GPDMA1_REQUEST_UART5_RX + * @arg @ref LL_GPDMA1_REQUEST_UART5_TX + * @arg @ref LL_GPDMA1_REQUEST_UART7_RX + * @arg @ref LL_GPDMA1_REQUEST_UART7_TX + * @arg @ref LL_GPDMA1_REQUEST_UART8_RX + * @arg @ref LL_GPDMA1_REQUEST_UART8_TX + * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ + * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE + * @arg @ref LL_GPDMA1_REQUEST_SPDIF_RX_DT + * @arg @ref LL_GPDMA1_REQUEST_SPDIF_RX_CS + * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0 + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX + * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX + * @arg @ref LL_GPDMA1_REQUEST_PSSI + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE + * @arg @ref LL_GPDMA1_REQUEST_I3C1_RX + * @arg @ref LL_GPDMA1_REQUEST_I3C1_TX + * @arg @ref LL_GPDMA1_REQUEST_I3C1_TC + * @arg @ref LL_GPDMA1_REQUEST_I3C1_RS + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL)); +} + +/** + * @brief Set hardware trigger. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGSEL LL_DMA_SetHWTrigger + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Trigger This parameter can be one of the following values: + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_FRAMEEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_HSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_LINEEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_VSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_CTC_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TC_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TW_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_EOC_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFNF_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFT_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFNE_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFT_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_LCD + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG0 + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG1 + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG2 + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG3 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_4 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_3 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_2 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_1 + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH8_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH9_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH10_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH11_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH12_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH13_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH14_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH15_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH0_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH1_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH2_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH3_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH4_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH5_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH6_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH7_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH8_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH9_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH10_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH11_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH12_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH13_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH14_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH15_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH8_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH9_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH10_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH11_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH12_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH13_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH14_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH15_TCF + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_OUT + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT0_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_RTC_WKUP + * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC + * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC + * @arg @ref LL_GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF + * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO2 + * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM6_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM7_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM9_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL, + (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); +} + +/** + * @brief Get hardware triggers. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGSEL LL_DMA_GetHWTrigger + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_FRAMEEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_HSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_LINEEND + * @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_EVT_VSYNC + * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_CTC_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TC_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TW_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_EOC_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFNF_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFT_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFNE_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFT_FLAG + * @arg @ref LL_HPDMA1_TRIGGER_LCD + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG0 + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG1 + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG2 + * @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_FLAG3 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_4 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_3 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_2 + * @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0_EVT_1 + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH8_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH9_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH10_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH11_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH12_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH13_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH14_TCF + * @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH15_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH0_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH1_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH2_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH3_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH4_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH5_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH6_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH7_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH8_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH9_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH10_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH11_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH12_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH13_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH14_TCF + * @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH15_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH8_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH9_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH10_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH11_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH12_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH13_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH14_TCF + * @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH15_TCF + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_OUT + * @arg @ref LL_GPDMA1_TRIGGER_EXTIT0_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_RTC_WKUP + * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC + * @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC + * @arg @ref LL_GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF + * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO2 + * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM6_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM7_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM9_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO + */ +__STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos); +} + +/** + * @brief Set DMA transfer mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 PFREQ LL_DMA_SetTransferMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 (HW request peripheral flow control mode supported on GPDMA1) + * @arg @ref LL_DMA_CHANNEL_15 (HW request peripheral flow control mode supported on GPDMA1 & HPDMA1) + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_NORMAL + * @arg @ref LL_DMA_PFCTRL + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTransferMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_PFREQ, + Mode & DMA_CTR2_PFREQ); +} + +/** + * @brief Get DMA transfer mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGSEL LL_DMA_GetTransferMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 (HW request peripheral flow control mode supported on GPDMA1) + * @arg @ref LL_DMA_CHANNEL_15 (HW request peripheral flow control mode supported on GPDMA1 & HPDMA1) + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_NORMAL + * @arg @ref LL_DMA_PFCTRL + */ +__STATIC_INLINE uint32_t LL_DMA_GetTransferMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_PFREQ)); +} + +/** + * @brief Configure addresses update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRDDEC LL_DMA_ConfigBlkRptAddrUpdate\n + * CBR1 BRSDEC LL_DMA_ConfigBlkRptAddrUpdate\n + * CBR1 DDEC LL_DMA_ConfigBlkRptAddrUpdate\n + * CBR1 SDEC LL_DMA_ConfigBlkRptAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT + * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT or @ref LL_DMA_BURST_DEST_ADDR_DECREMENT + * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT or @ref LL_DMA_BURST_SRC_ADDR_DECREMENT + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, + DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration); +} + +/** + * @brief Configure DMA Block number of data and repeat Count. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BNDT LL_DMA_ConfigBlkCounters\n + * CBR1 BRC LL_DMA_ConfigBlkCounters + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkDataLength Block transfer length + Value between 0 to 0x0000FFFF + * @param BlkRptCount Block repeat counter + * Value between 0 to 0x000007FF + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBlkCounters(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength, + uint32_t BlkRptCount) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, + (DMA_CBR1_BNDT | DMA_CBR1_BRC), (BlkDataLength | (BlkRptCount << DMA_CBR1_BRC_Pos))); +} + +/** + * @brief Set block repeat destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRDDEC LL_DMA_SetBlkRptDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptDestAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptDestAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC, + BlkRptDestAddrUpdate); +} + +/** + * @brief Get block repeat destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRDDEC LL_DMA_GetBlkRptDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC)); +} + +/** + * @brief Set block repeat source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRSDEC LL_DMA_SetBlkRptSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptSrcAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptSrcAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC, + BlkRptSrcAddrUpdate); +} + +/** + * @brief Get block repeat source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRSDEC LL_DMA_GetBlkRptSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC)); +} + +/** + * @brief Set destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 DDEC LL_DMA_SetDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC, + DestAddrUpdate); +} + +/** + * @brief Get destination address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 DDEC LL_DMA_GetDestAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC)); +} + +/** + * @brief Set source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 SDEC LL_DMA_SetSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcAddrUpdate This parameter can be one of the following values: + * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrUpdate) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC, + SrcAddrUpdate); +} + +/** + * @brief Get source address update. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 SDEC LL_DMA_GetSrcAddrUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT + * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC)); +} + +/** + * @brief Set block repeat count. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRC LL_DMA_SetBlkRptCount + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptCount Block repeat counter + * Value between 0 to 0x000007FF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRC, + (BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC); +} + +/** + * @brief Get block repeat count. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR1 BRC LL_DMA_GetBlkRptCount + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x000007FF + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, + DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos); +} + +/** + * @brief Set block data length in bytes to transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CBR1 BNDT LL_DMA_SetBlkDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkDataLength Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT, + BlkDataLength); +} + +/** + * @brief Get block data length in bytes to transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CBR1 BNDT LL_DMA_GetBlkDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x0000FFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT)); +} + +/** + * @brief Configure the source and destination addresses. + * @note This API is used for all available DMA channels. + * @note This API must not be called when the DMA Channel is enabled. + * @rmtoll CSAR SA LL_DMA_ConfigAddresses\n + * CDAR DA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @param DestAddress Between 0 to 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t + DestAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress); +} + +/** + * @brief Set source address. + * @note This API is used for all available DMA channels. + * @rmtoll CSAR SA LL_DMA_SetSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress); +} + +/** + * @brief Get source address. + * @note This API is used for all available DMA channels. + * @rmtoll CSAR SA LL_DMA_GetSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR)); +} + +/** + * @brief Set destination address. + * @note This API is used for all available DMA channels. + * @rmtoll CDAR DA LL_DMA_SetDestAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestAddress Between 0 to 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress); +} + +/** + * @brief Get destination address. + * @note This API is used for all available DMA channels. + * @rmtoll CDAR DA LL_DMA_GetDestAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR)); +} + +/** + * @brief Configure source and destination addresses offset. + * @note This API is used only for 2D addressing channels. + * @note This API must not be called when the DMA Channel is enabled. + * @rmtoll CTR3 DAO LL_DMA_ConfigAddrUpdateValue\n + * CTR3 SAO LL_DMA_ConfigAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestAddrOffset Between 0 to 0x00001FFF + * @param SrcAddrOffset Between 0 to 0x00001FFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset, + uint32_t DestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, + (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); +} + +/** + * @brief Set destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CTR3 DAO LL_DMA_SetDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DestAddrOffset Between 0 to 0x00001FFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_DAO, + ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); +} + +/** + * @brief Get destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CDAR DAO LL_DMA_GetDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x00001FFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, + DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos); +} + +/** + * @brief Set source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CTR3 SAO LL_DMA_SetSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param SrcAddrOffset Between 0 to 0x00001FFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO, + SrcAddrOffset & DMA_CTR3_SAO); +} + +/** + * @brief Get source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CTR3 SAO LL_DMA_GetSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x00001FFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO)); +} + +/** + * @brief Configure the block repeated source and destination addresses offset. + * @note This API is used only for 2D addressing channels. + * @note This API must not be called when the DMA Channel is enabled. + * @rmtoll CBR2 BRDAO LL_DMA_ConfigBlkRptAddrUpdateValue\n + * CBR2 BRSAO LL_DMA_ConfigBlkRptAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF + * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptSrcAddrOffset, uint32_t BlkRptDestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, + ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO) | (BlkRptSrcAddrOffset & DMA_CBR2_BRSAO)); +} + +/** + * @brief Set block repeated destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRDAO LL_DMA_SetBlkRptDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptDestAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRDAO, + ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO)); +} + +/** + * @brief Get block repeated destination address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRDAO LL_DMA_GetBlkRptDestAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x0000FFFF. + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, + DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos); +} + +/** + * @brief Set block repeated source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRSAO LL_DMA_SetBlkRptSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t BlkRptSrcAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO, + BlkRptSrcAddrOffset); +} + +/** + * @brief Get block repeated source address offset. + * @note This API is used only for 2D addressing channels. + * @rmtoll CBR2 BRSAO LL_DMA_GetBlkRptSrcAddrUpdateValue + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x0000FFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO)); +} + +/** + * @brief Configure registers update and node address offset during the link transfer. + * @note This API is used for all available DMA channels. + * For linear addressing channels, UT3 and UB2 fields are discarded. + * @rmtoll CLLR UT1 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UT2 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UB1 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR USA LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UDA LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UT3 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UB2 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR ULL LL_DMA_ConfigLinkUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param RegistersUpdate This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_UPDATE_CTR1 + * @arg @ref LL_DMA_UPDATE_CTR2 + * @arg @ref LL_DMA_UPDATE_CBR1 + * @arg @ref LL_DMA_UPDATE_CSAR + * @arg @ref LL_DMA_UPDATE_CDAR + * @arg @ref LL_DMA_UPDATE_CTR3 (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_UPDATE_CBR2 (This value is allowed only for 2D addressing channels) + * @arg @ref LL_DMA_UPDATE_CLLR + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate, + uint32_t LinkedListAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, + (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ + DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA))); +} + +/** + * @brief Enable CTR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_EnableCTR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); +} + +/** + * @brief Disable CTR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_DisableCTR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); +} + +/** + * @brief Check if CTR1 update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_IsEnabledCTR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1) + == (DMA_CLLR_UT1)) ? 1UL : 0UL); +} + +/** + * @brief Enable CTR2 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT2 LL_DMA_EnableCTR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2); +} + +/** + * @brief Disable CTR2 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT2 LL_DMA_DisableCTR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2); +} + +/** + * @brief Check if CTR2 update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT2 LL_DMA_IsEnabledCTR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2) + == (DMA_CLLR_UT2)) ? 1UL : 0UL); +} + +/** + * @brief Enable CBR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UB1 LL_DMA_EnableCBR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); +} + +/** + * @brief Disable CBR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UB1 LL_DMA_DisableCBR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); +} + +/** + * @brief Check if CBR1 update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UB1 LL_DMA_IsEnabledCBR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1) + == (DMA_CLLR_UB1)) ? 1UL : 0UL); +} + +/** + * @brief Enable CSAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR USA LL_DMA_EnableCSARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); +} + +/** + * @brief Disable CSAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR USA LL_DMA_DisableCSARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); +} + +/** + * @brief Check if CSAR update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR USA LL_DMA_IsEnabledCSARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) + == (DMA_CLLR_USA)) ? 1UL : 0UL); +} + +/** + * @brief Enable CDAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UDA LL_DMA_EnableCDARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); +} + +/** + * @brief Disable CDAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UDA LL_DMA_DisableCDARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); +} + +/** + * @brief Check if CDAR update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UDA LL_DMA_IsEnabledCDARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA) + == (DMA_CLLR_UDA)) ? 1UL : 0UL); +} + +/** + * @brief Enable CTR3 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UT3 LL_DMA_EnableCTR3Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); +} + +/** + * @brief Disable CTR3 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UT3 LL_DMA_DisableCTR3Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); +} + +/** + * @brief Check if CTR3 update during the link transfer is enabled. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UT3 LL_DMA_IsEnabledCTR3Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3) + == (DMA_CLLR_UT3)) ? 1UL : 0UL); +} + +/** + * @brief Enable CBR2 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UB2 LL_DMA_EnableCBR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2); +} + +/** + * @brief Disable CBR2 update during the link transfer. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UB2 LL_DMA_DisableCBR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2); +} + +/** + * @brief Check if CBR2 update during the link transfer is enabled. + * @note This API is used only for 2D addressing channels. + * @rmtoll CLLR UB2 LL_DMA_IsEnabledCBR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2) + == (DMA_CLLR_UB2)) ? 1UL : 0UL); +} + +/** + * @brief Enable CLLR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR ULL LL_DMA_EnableCLLRUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); +} + +/** + * @brief Disable CLLR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR ULL LL_DMA_DisableCLLRUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); +} + +/** + * @brief Check if CLLR update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR ULL LL_DMA_IsEnabledCLLRUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL) + == (DMA_CLLR_ULL)) ? 1UL : 0UL); +} + +/** + * @brief Set linked list address offset. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR LA LL_DMA_SetLinkedListAddrOffset + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t LinkedListAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA, + (LinkedListAddrOffset & DMA_CLLR_LA)); +} + +/** + * @brief Get linked list address offset. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR LA LL_DMA_GetLinkedListAddrOffset + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x0000FFFC. + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, + DMA_CLLR_LA) >> DMA_CLLR_LA_Pos); +} + +/** + * @brief Get FIFO level. + * @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval Between 0 to 0x000000FF. + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, + DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); +} + + +/** + * @brief Enable the DMA channel privilege attribute. + * @note This API is used for all available DMA channels. + * @rmtoll PRIVCFGR PRIVx LL_DMA_EnableChannelPrivilege + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))); +} + +/** + * @brief Disable the DMA channel privilege attribute. + * @note This API is used for all available DMA channels. + * @rmtoll PRIVCFGR PRIVx LL_DMA_DisableChannelPrivilege + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))); +} + +/** + * @brief Check if DMA Channel privilege is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivilege + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) + == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} + + +/** + * @brief Enable the DMA channel lock attributes. + * @note This API is used for all available DMA channels. + * @rmtoll RCFGLOCKR LOCKx LL_DMA_EnableChannelLockAttribute + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))); +} + + +/** + * @brief Check if DMA channel attributes are locked. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR LOCKx LL_DMA_IsEnabledChannelLockAttribute + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) + == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management Flag Management + * @{ + */ + +/** + * @brief Clear trigger overrun flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR TOF LL_DMA_ClearFlag_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF); +} + +/** + * @brief Clear suspension flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR SUSPF LL_DMA_ClearFlag_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF); +} + +/** + * @brief Clear user setting error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR USEF LL_DMA_ClearFlag_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF); +} + +/** + * @brief Clear link transfer error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR ULEF LL_DMA_ClearFlag_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF); +} + +/** + * @brief Clear data transfer error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR DTEF LL_DMA_ClearFlag_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF); +} + +/** + * @brief Clear half transfer flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR HTF LL_DMA_ClearFlag_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF); +} + +/** + * @brief Clear transfer complete flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR TCF LL_DMA_ClearFlag_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF); +} + +/** + * @brief Get trigger overrun flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR TOF LL_DMA_IsActiveFlag_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF) + == (DMA_CSR_TOF)) ? 1UL : 0UL); +} + +/** + * @brief Get suspension flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR SUSPF LL_DMA_IsActiveFlag_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF) + == (DMA_CSR_SUSPF)) ? 1UL : 0UL); +} + +/** + * @brief Get user setting error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR USEF LL_DMA_IsActiveFlag_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF) + == (DMA_CSR_USEF)) ? 1UL : 0UL); +} + +/** + * @brief Get user setting error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR ULEF LL_DMA_IsActiveFlag_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF) + == (DMA_CSR_ULEF)) ? 1UL : 0UL); +} + +/** + * @brief Get data transfer error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR DTEF LL_DMA_IsActiveFlag_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF) + == (DMA_CSR_DTEF)) ? 1UL : 0UL); +} + +/** + * @brief Get half transfer flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR HTF LL_DMA_IsActiveFlag_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF) + == (DMA_CSR_HTF)) ? 1UL : 0UL); +} + +/** + * @brief Get transfer complete flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR TCF LL_DMA_IsActiveFlag_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF) + == (DMA_CSR_TCF)) ? 1UL : 0UL); +} + +/** + * @brief Get idle flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR IDLEF LL_DMA_IsActiveFlag_IDLE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF) + == (DMA_CSR_IDLEF)) ? 1UL : 0UL); +} + +/** + * @brief Check if masked interrupt is active. + * @note This API is used for all available DMA channels. + * @rmtoll MISR MISx LL_DMA_IsActiveFlag_MIS + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU))) + == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable trigger overrun interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TOIE LL_DMA_EnableIT_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE); +} + +/** + * @brief Enable suspension interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSPIE LL_DMA_EnableIT_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE); +} + +/** + * @brief Enable user setting error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR USEIE LL_DMA_EnableIT_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE); +} + +/** + * @brief Enable update link transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR ULEIE LL_DMA_EnableIT_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE); +} + +/** + * @brief Enable data transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR DTEIE LL_DMA_EnableIT_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE); +} + +/** + * @brief Enable half transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable trigger overrun interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TOIE LL_DMA_DisableIT_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE); +} + +/** + * @brief Disable suspension interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSPIE LL_DMA_DisableIT_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE); +} + +/** + * @brief Disable user setting error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR USEIE LL_DMA_DisableIT_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE); +} + +/** + * @brief Disable update link transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR ULEIE LL_DMA_DisableIT_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE); +} + +/** + * @brief Disable data transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR DTEIE LL_DMA_DisableIT_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE); +} + +/** + * @brief Disable half transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Check if trigger overrun interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TOIE LL_DMA_IsEnabledIT_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE) + == DMA_CCR_TOIE) ? 1UL : 0UL); +} + +/** + * @brief Check if suspension interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSPIE LL_DMA_IsEnabledIT_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE) + == DMA_CCR_SUSPIE) ? 1UL : 0UL); +} + +/** + * @brief Check if user setting error interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR USEIE LL_DMA_IsEnabledIT_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE) + == DMA_CCR_USEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if update link transfer error interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR ULEIE LL_DMA_IsEnabledIT_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE) + == DMA_CCR_ULEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if data transfer error interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR DTEIE LL_DMA_IsEnabledIT_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE) + == DMA_CCR_DTEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if half transfer complete interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE) + == DMA_CCR_HTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if transfer complete interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE) + == DMA_CCR_TCIE) ? 1UL : 0UL); +} +/** + * @} + */ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); + +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); +void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct); +void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct); + +uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, + LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct); +uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); + +uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode); +void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx, + LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx); +void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* GPDMA1 || HPDMA1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32H7RSxx_LL_DMA_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_dma2d.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_dma2d.h new file mode 100644 index 00000000000..c0a3e199000 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_dma2d.h @@ -0,0 +1,2231 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_dma2d.h + * @author MCD Application Team + * @brief Header file of DMA2D LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_DMA2D_H +#define STM32H7RSxx_LL_DMA2D_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (DMA2D) + +/** @defgroup DMA2D_LL DMA2D + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures + * @{ + */ + +/** + * @brief LL DMA2D Init Structure Definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the DMA2D transfer mode. + - This parameter can be one value of @ref DMA2D_LL_EC_MODE. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetMode(). */ + + uint32_t ColorMode; /*!< Specifies the color format of the output image. + - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. + + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetOutputColorMode(). */ + + uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputGreen; /*!< Specifies the Green value of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputRed; /*!< Specifies the Red value of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter is not considered if RGB888 or RGB565 color mode is selected. + + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputMemoryAddress; /*!< Specifies the memory address. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */ + + uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image. + - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */ + + uint32_t LineOffsetMode; /*!< Specifies the output line offset mode. + - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */ + + uint32_t LineOffset; /*!< Specifies the output line offset value. + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetLineOffset(). */ + + uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetNbrOfLines(). */ + + uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred. + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. + + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */ + + uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode. + - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */ + + uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode. + - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */ + +} LL_DMA2D_InitTypeDef; + +/** + * @brief LL DMA2D Layer Configuration Structure Definition + */ +typedef struct +{ + uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer, + - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */ + + uint32_t LineOffset; /*!< Specifies the foreground or background line offset value. + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer, + - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */ + + uint32_t ColorMode; /*!< Specifies the foreground or background color mode. + - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer, + - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */ + + uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode. + - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer, + - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */ + + uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer, + - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */ + + uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode. + - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer, + - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */ + + uint32_t Alpha; /*!< Specifies the foreground or background Alpha value. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer, + - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */ + + uint32_t Blue; /*!< Specifies the foreground or background Blue color value. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer, + - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */ + + uint32_t Green; /*!< Specifies the foreground or background Green color value. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer, + - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */ + + uint32_t Red; /*!< Specifies the foreground or background Red color value. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer, + - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */ + + uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer, + - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */ + + uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode. + - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer, + - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */ + + uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode. + This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP . + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer, + - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */ + + uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode + This parameter is applicable for foreground layer only. + This parameter can be one value of @ref DMA2D_LL_CHROMA_SUB_SAMPLING + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetChrSubSampling() for foreground layer. */ + +} LL_DMA2D_LayerCfgTypeDef; + +/** + * @brief LL DMA2D Output Color Structure Definition + */ +typedef struct +{ + uint32_t ColorMode; /*!< Specifies the color format of the output image. + - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. + + This parameter can be modified afterwards using + unitary function @ref LL_DMA2D_SetOutputColorMode(). */ + + uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputGreen; /*!< Specifies the Green value of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputRed; /*!< Specifies the Red value of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter is not considered if RGB888 or RGB565 color mode is selected. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + +} LL_DMA2D_ColorTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants + * @{ + */ + +/** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA2D_ReadReg function + * @{ + */ +#define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ +#define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ +#define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ +#define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ +#define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ +#define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions + * @{ + */ +#define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ +#define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ +#define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ +#define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ +#define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ +#define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_MODE Mode + * @{ + */ +#define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ +#define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ +#define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ +#define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */ +#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */ +#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode + * @{ + */ +#define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ +#define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */ +#define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */ +#define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */ +#define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode + * @{ + */ +#define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ +#define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */ +#define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */ +#define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */ +#define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */ +#define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */ +#define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */ +#define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */ +#define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */ +#define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */ +#define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */ +#define LL_DMA2D_INPUT_MODE_YCBCR (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< YCbCr */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode + * @{ + */ +#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */ +#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by + programmed alpha value */ +#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by + programmed alpha value with, + original alpha channel value */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode + * @{ + */ +#define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */ +#define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap + * @{ + */ +#define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */ +#define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion + * @{ + */ +#define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */ +#define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */ +/** + * @} + */ + + +/** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode + * @{ + */ +#define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */ +#define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode + * @{ + */ +#define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ +#define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_CHROMA_SUB_SAMPLING Chroma Sub Sampling + * @{ + */ +#define LL_DMA2D_CSS_444 0x00000000U /*!< No chroma sub-sampling 4:4:4 */ +#define LL_DMA2D_CSS_422 DMA2D_FGPFCCR_CSS_0 /*!< chroma sub-sampling 4:2:2 */ +#define LL_DMA2D_CSS_420 DMA2D_FGPFCCR_CSS_1 /*!< chroma sub-sampling 4:2:0 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros + * @{ + */ + +/** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in DMA2D register. + * @param __INSTANCE__ DMA2D Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA2D register. + * @param __INSTANCE__ DMA2D Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions + * @{ + */ + +/** @defgroup DMA2D_LL_EF_Configuration Configuration Functions + * @{ + */ + +/** + * @brief Start a DMA2D transfer. + * @rmtoll CR START LL_DMA2D_Start + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_START); +} + +/** + * @brief Indicate if a DMA2D transfer is ongoing. + * @rmtoll CR START LL_DMA2D_IsTransferOngoing + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL); +} + +/** + * @brief Suspend DMA2D transfer. + * @note This API can be used to suspend automatic foreground or background CLUT loading. + * @rmtoll CR SUSP LL_DMA2D_Suspend + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx) +{ + MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP); +} + +/** + * @brief Resume DMA2D transfer. + * @note This API can be used to resume automatic foreground or background CLUT loading. + * @rmtoll CR SUSP LL_DMA2D_Resume + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START); +} + +/** + * @brief Indicate if DMA2D transfer is suspended. + * @note This API can be used to indicate whether or not automatic foreground or + * background CLUT loading is suspended. + * @rmtoll CR SUSP LL_DMA2D_IsSuspended + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL); +} + +/** + * @brief Abort DMA2D transfer. + * @note This API can be used to abort automatic foreground or background CLUT loading. + * @rmtoll CR ABORT LL_DMA2D_Abort + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx) +{ + MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT); +} + +/** + * @brief Indicate if DMA2D transfer is aborted. + * @note This API can be used to indicate whether or not automatic foreground or + * background CLUT loading is aborted. + * @rmtoll CR ABORT LL_DMA2D_IsAborted + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL); +} + +/** + * @brief Set DMA2D mode. + * @rmtoll CR MODE LL_DMA2D_SetMode + * @param DMA2Dx DMA2D Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_MODE_M2M + * @arg @ref LL_DMA2D_MODE_M2M_PFC + * @arg @ref LL_DMA2D_MODE_M2M_BLEND + * @arg @ref LL_DMA2D_MODE_R2M + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) +{ + MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode); +} + +/** + * @brief Return DMA2D mode + * @rmtoll CR MODE LL_DMA2D_GetMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_MODE_M2M + * @arg @ref LL_DMA2D_MODE_M2M_PFC + * @arg @ref LL_DMA2D_MODE_M2M_BLEND + * @arg @ref LL_DMA2D_MODE_R2M + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE)); +} + +/** + * @brief Set DMA2D output color mode. + * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode + * @param DMA2Dx DMA2D Instance + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode); +} + +/** + * @brief Return DMA2D output color mode. + * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM)); +} + +/** + * @brief Set DMA2D output Red Blue swap mode. + * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode + * @param DMA2Dx DMA2D Instance + * @param RBSwapMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) +{ + MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode); +} + +/** + * @brief Return DMA2D output Red Blue swap mode. + * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS)); +} + +/** + * @brief Set DMA2D output alpha inversion mode. + * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @param AlphaInversionMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) +{ + MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode); +} + +/** + * @brief Return DMA2D output alpha inversion mode. + * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); +} + + +/** + * @brief Set DMA2D output swap mode. + * @rmtoll OPFCCR SB LL_DMA2D_SetOutputSwapMode + * @param DMA2Dx DMA2D Instance + * @param OutputSwapMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR + * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode) +{ + MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode); +} + +/** + * @brief Return DMA2D output swap mode. + * @rmtoll OPFCCR SB LL_DMA2D_GetOutputSwapMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR + * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB)); +} + +/** + * @brief Set DMA2D line offset mode. + * @rmtoll CR LOM LL_DMA2D_SetLineOffsetMode + * @param DMA2Dx DMA2D Instance + * @param LineOffsetMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS + * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode) +{ + MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode); +} + +/** + * @brief Return DMA2D line offset mode. + * @rmtoll CR LOM LL_DMA2D_GetLineOffsetMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS + * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM)); +} + +/** + * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll OOR LO LL_DMA2D_SetLineOffset + * @param DMA2Dx DMA2D Instance + * @param LineOffset Value between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) +{ + MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset); +} + +/** + * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll OOR LO LL_DMA2D_GetLineOffset + * @param DMA2Dx DMA2D Instance + * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO)); +} + +/** + * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits). + * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines + * @param DMA2Dx DMA2D Instance + * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines) +{ + MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos)); +} + +/** + * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits) + * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines + * @param DMA2Dx DMA2D Instance + * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos); +} + +/** + * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits). + * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines + * @param DMA2Dx DMA2D Instance + * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines) +{ + MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines); +} + +/** + * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits). + * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines + * @param DMA2Dx DMA2D Instance + * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL)); +} + +/** + * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr + * @param DMA2Dx DMA2D Instance + * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress) +{ + LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress); +} + +/** + * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr + * @param DMA2Dx DMA2D Instance + * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR)); +} + +/** + * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits). + * @note Output color format depends on output color mode, ARGB8888, RGB888, + * RGB565, ARGB1555 or ARGB4444. + * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting + * with respect to color mode is not done by the user code. + * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n + * OCOLR GREEN LL_DMA2D_SetOutputColor\n + * OCOLR RED LL_DMA2D_SetOutputColor\n + * OCOLR ALPHA LL_DMA2D_SetOutputColor + * @param DMA2Dx DMA2D Instance + * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor) +{ + MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \ + OutputColor); +} + +/** + * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits). + * @note Alpha channel and red, green, blue color values must be retrieved from the returned + * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444) + * as set by @ref LL_DMA2D_SetOutputColorMode. + * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n + * OCOLR GREEN LL_DMA2D_GetOutputColor\n + * OCOLR RED LL_DMA2D_GetOutputColor\n + * OCOLR ALPHA LL_DMA2D_GetOutputColor + * @param DMA2Dx DMA2D Instance + * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \ + (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1))); +} + +/** + * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits). + * @rmtoll LWR LW LL_DMA2D_SetLineWatermark + * @param DMA2Dx DMA2D Instance + * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark) +{ + MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark); +} + +/** + * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits). + * @rmtoll LWR LW LL_DMA2D_GetLineWatermark + * @param DMA2Dx DMA2D Instance + * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW)); +} + +/** + * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits). + * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime + * @param DMA2Dx DMA2D Instance + * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime) +{ + MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos)); +} + +/** + * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits). + * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime + * @param DMA2Dx DMA2D Instance + * @retval Dead time value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos); +} + +/** + * @brief Enable DMA2D dead time functionality. + * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); +} + +/** + * @brief Disable DMA2D dead time functionality. + * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); +} + +/** + * @brief Indicate if DMA2D dead time functionality is enabled. + * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); +} + +/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions + * @{ + */ + +/** + * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr + * @param DMA2Dx DMA2D Instance + * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress) +{ + LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress); +} + +/** + * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr + * @param DMA2Dx DMA2D Instance + * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR)); +} + +/** + * @brief Enable DMA2D foreground CLUT loading. + * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START); +} + +/** + * @brief Indicate if DMA2D foreground CLUT loading is enabled. + * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL); +} + +/** + * @brief Set DMA2D foreground color mode. + * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode + * @param DMA2Dx DMA2D Instance + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 + * @arg @ref LL_DMA2D_INPUT_MODE_L8 + * @arg @ref LL_DMA2D_INPUT_MODE_AL44 + * @arg @ref LL_DMA2D_INPUT_MODE_AL88 + * @arg @ref LL_DMA2D_INPUT_MODE_L4 + * @arg @ref LL_DMA2D_INPUT_MODE_A8 + * @arg @ref LL_DMA2D_INPUT_MODE_A4 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode); +} + +/** + * @brief Return DMA2D foreground color mode. + * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 + * @arg @ref LL_DMA2D_INPUT_MODE_L8 + * @arg @ref LL_DMA2D_INPUT_MODE_AL44 + * @arg @ref LL_DMA2D_INPUT_MODE_AL88 + * @arg @ref LL_DMA2D_INPUT_MODE_L4 + * @arg @ref LL_DMA2D_INPUT_MODE_A8 + * @arg @ref LL_DMA2D_INPUT_MODE_A4 + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM)); +} + +/** + * @brief Set DMA2D foreground alpha mode. + * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode + * @param DMA2Dx DMA2D Instance + * @param AphaMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF + * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE + * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode); +} + +/** + * @brief Return DMA2D foreground alpha mode. + * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF + * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE + * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM)); +} + +/** + * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha + * @param DMA2Dx DMA2D Instance + * @param Alpha Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos)); +} + +/** + * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha + * @param DMA2Dx DMA2D Instance + * @retval Alpha value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos); +} + +/** + * @brief Set DMA2D foreground Red Blue swap mode. + * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode + * @param DMA2Dx DMA2D Instance + * @param RBSwapMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode); +} + +/** + * @brief Return DMA2D foreground Red Blue swap mode. + * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS)); +} + +/** + * @brief Set DMA2D foreground alpha inversion mode. + * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @param AlphaInversionMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode); +} + +/** + * @brief Return DMA2D foreground alpha inversion mode. + * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI)); +} + +/** + * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset + * @param DMA2Dx DMA2D Instance + * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) +{ + MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset); +} + +/** + * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset + * @param DMA2Dx DMA2D Instance + * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO)); +} + +/** + * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits). + * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor + * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor + * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor + * @param DMA2Dx DMA2D Instance + * @param Red Value between Min_Data=0 and Max_Data=0xFF + * @param Green Value between Min_Data=0 and Max_Data=0xFF + * @param Blue Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue) +{ + MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \ + ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue)); +} + +/** + * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor + * @param DMA2Dx DMA2D Instance + * @param Red Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red) +{ + MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos)); +} + +/** + * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor + * @param DMA2Dx DMA2D Instance + * @retval Red color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos); +} + +/** + * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor + * @param DMA2Dx DMA2D Instance + * @param Green Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green) +{ + MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos)); +} + +/** + * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor + * @param DMA2Dx DMA2D Instance + * @retval Green color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos); +} + +/** + * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor + * @param DMA2Dx DMA2D Instance + * @param Blue Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue) +{ + MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue); +} + +/** + * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor + * @param DMA2Dx DMA2D Instance + * @retval Blue color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE)); +} + +/** + * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr + * @param DMA2Dx DMA2D Instance + * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress) +{ + LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress); +} + +/** + * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr + * @param DMA2Dx DMA2D Instance + * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR)); +} + +/** + * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). + * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize + * @param DMA2Dx DMA2D Instance + * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos)); +} + +/** + * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). + * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize + * @param DMA2Dx DMA2D Instance + * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos); +} + +/** + * @brief Set DMA2D foreground CLUT color mode. + * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode + * @param DMA2Dx DMA2D Instance + * @param CLUTColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode); +} + +/** + * @brief Return DMA2D foreground CLUT color mode. + * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM)); +} + +/** + * @brief Set DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode). + * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_SetChrSubSampling + * @param DMA2Dx DMA2D Instance + * @param ChromaSubSampling This parameter can be one of the following values: + * @arg @ref LL_DMA2D_CSS_444 + * @arg @ref LL_DMA2D_CSS_422 + * @arg @ref LL_DMA2D_CSS_420 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint32_t ChromaSubSampling) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS, ChromaSubSampling); +} + +/** + * @brief Return DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode). + * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_GetChrSubSampling + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_CSS_444 + * @arg @ref LL_DMA2D_CSS_422 + * @arg @ref LL_DMA2D_CSS_420 + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS)); +} +/** + * @} + */ + +/** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions + * @{ + */ + +/** + * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr + * @param DMA2Dx DMA2D Instance + * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress) +{ + LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress); +} + +/** + * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr + * @param DMA2Dx DMA2D Instance + * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR)); +} + +/** + * @brief Enable DMA2D background CLUT loading. + * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START); +} + +/** + * @brief Indicate if DMA2D background CLUT loading is enabled. + * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL); +} + +/** + * @brief Set DMA2D background color mode. + * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode + * @param DMA2Dx DMA2D Instance + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 + * @arg @ref LL_DMA2D_INPUT_MODE_L8 + * @arg @ref LL_DMA2D_INPUT_MODE_AL44 + * @arg @ref LL_DMA2D_INPUT_MODE_AL88 + * @arg @ref LL_DMA2D_INPUT_MODE_L4 + * @arg @ref LL_DMA2D_INPUT_MODE_A8 + * @arg @ref LL_DMA2D_INPUT_MODE_A4 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode); +} + +/** + * @brief Return DMA2D background color mode. + * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 + * @arg @ref LL_DMA2D_INPUT_MODE_L8 + * @arg @ref LL_DMA2D_INPUT_MODE_AL44 + * @arg @ref LL_DMA2D_INPUT_MODE_AL88 + * @arg @ref LL_DMA2D_INPUT_MODE_L4 + * @arg @ref LL_DMA2D_INPUT_MODE_A8 + * @arg @ref LL_DMA2D_INPUT_MODE_A4 + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM)); +} + +/** + * @brief Set DMA2D background alpha mode. + * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode + * @param DMA2Dx DMA2D Instance + * @param AphaMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF + * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE + * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode); +} + +/** + * @brief Return DMA2D background alpha mode. + * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF + * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE + * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM)); +} + +/** + * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha + * @param DMA2Dx DMA2D Instance + * @param Alpha Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos)); +} + +/** + * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha + * @param DMA2Dx DMA2D Instance + * @retval Alpha value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos); +} + +/** + * @brief Set DMA2D background Red Blue swap mode. + * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode + * @param DMA2Dx DMA2D Instance + * @param RBSwapMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode); +} + +/** + * @brief Return DMA2D background Red Blue swap mode. + * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS)); +} + +/** + * @brief Set DMA2D background alpha inversion mode. + * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @param AlphaInversionMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode); +} + +/** + * @brief Return DMA2D background alpha inversion mode. + * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI)); +} + +/** + * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset + * @param DMA2Dx DMA2D Instance + * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) +{ + MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset); +} + +/** + * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset + * @param DMA2Dx DMA2D Instance + * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO)); +} + +/** + * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits). + * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor + * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor + * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor + * @param DMA2Dx DMA2D Instance + * @param Red Value between Min_Data=0 and Max_Data=0xFF + * @param Green Value between Min_Data=0 and Max_Data=0xFF + * @param Blue Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue) +{ + MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \ + ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue)); +} + +/** + * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor + * @param DMA2Dx DMA2D Instance + * @param Red Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red) +{ + MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos)); +} + +/** + * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor + * @param DMA2Dx DMA2D Instance + * @retval Red color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos); +} + +/** + * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor + * @param DMA2Dx DMA2D Instance + * @param Green Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green) +{ + MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos)); +} + +/** + * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor + * @param DMA2Dx DMA2D Instance + * @retval Green color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos); +} + +/** + * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor + * @param DMA2Dx DMA2D Instance + * @param Blue Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue) +{ + MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue); +} + +/** + * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor + * @param DMA2Dx DMA2D Instance + * @retval Blue color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE)); +} + +/** + * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr + * @param DMA2Dx DMA2D Instance + * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress) +{ + LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress); +} + +/** + * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr + * @param DMA2Dx DMA2D Instance + * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR)); +} + +/** + * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). + * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize + * @param DMA2Dx DMA2D Instance + * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos)); +} + +/** + * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). + * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize + * @param DMA2Dx DMA2D Instance + * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos); +} + +/** + * @brief Set DMA2D background CLUT color mode. + * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode + * @param DMA2Dx DMA2D Instance + * @param CLUTColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode); +} + +/** + * @brief Return DMA2D background CLUT color mode. + * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM)); +} + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management + * @{ + */ + +/** + * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not + * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not + * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not + * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not + * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not + * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not + * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear DMA2D Configuration Error Interrupt Flag + * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF); +} + +/** + * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag + * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF); +} + +/** + * @brief Clear DMA2D CLUT Access Error Interrupt Flag + * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF); +} + +/** + * @brief Clear DMA2D Transfer Watermark Interrupt Flag + * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF); +} + +/** + * @brief Clear DMA2D Transfer Complete Interrupt Flag + * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF); +} + +/** + * @brief Clear DMA2D Transfer Error Interrupt Flag + * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF); +} + +/** + * @} + */ + +/** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management + * @{ + */ + +/** + * @brief Enable Configuration Error Interrupt + * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE); +} + +/** + * @brief Enable CLUT Transfer Complete Interrupt + * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE); +} + +/** + * @brief Enable CLUT Access Error Interrupt + * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); +} + +/** + * @brief Enable Transfer Watermark Interrupt + * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE); +} + +/** + * @brief Enable Transfer Complete Interrupt + * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE); +} + +/** + * @brief Enable Transfer Error Interrupt + * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE); +} + +/** + * @brief Disable Configuration Error Interrupt + * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE); +} + +/** + * @brief Disable CLUT Transfer Complete Interrupt + * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE); +} + +/** + * @brief Disable CLUT Access Error Interrupt + * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); +} + +/** + * @brief Disable Transfer Watermark Interrupt + * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE); +} + +/** + * @brief Disable Transfer Complete Interrupt + * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE); +} + +/** + * @brief Disable Transfer Error Interrupt + * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE); +} + +/** + * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled. + * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled. + * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled. + * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled. + * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled. + * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled. + * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(const DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL); +} + + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions + * @{ + */ + +ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx); +ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct); +void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct); +void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx); +void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg); +void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct); +uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (DMA2D) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_DMA2D_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_exti.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_exti.h new file mode 100644 index 00000000000..ca6590c606f --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_exti.h @@ -0,0 +1,1505 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_EXTI_H +#define STM32H7RSxx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +#define LL_EXTI_REGISTER_PINPOS_SHFT 16U /*!< Define used to shift pin position in EXTICR register */ + +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + uint32_t Line_64_95; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 64 to 95 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ +#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ +#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ +#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ +#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ +#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ +#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ +#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ +#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ +#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */ +#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */ +#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ +#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ +#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ +#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ +#define LL_EXTI_LINE_ALL_0_31 (LL_EXTI_LINE_0 |LL_EXTI_LINE_1 | LL_EXTI_LINE_2 | LL_EXTI_LINE_3 | \ + LL_EXTI_LINE_4 | LL_EXTI_LINE_5 | LL_EXTI_LINE_6 | LL_EXTI_LINE_7 | \ + LL_EXTI_LINE_8 | LL_EXTI_LINE_9 | LL_EXTI_LINE_10 | LL_EXTI_LINE_11 | \ + LL_EXTI_LINE_12 | LL_EXTI_LINE_13 | LL_EXTI_LINE_14 | LL_EXTI_LINE_15 | \ + LL_EXTI_LINE_16 | LL_EXTI_LINE_17 | LL_EXTI_LINE_18 | LL_EXTI_LINE_19 | \ + LL_EXTI_LINE_20 | LL_EXTI_LINE_21 | LL_EXTI_LINE_22 | LL_EXTI_LINE_23 | \ + LL_EXTI_LINE_24 | LL_EXTI_LINE_25 | LL_EXTI_LINE_26 | LL_EXTI_LINE_27 | \ + LL_EXTI_LINE_28 | LL_EXTI_LINE_29 | LL_EXTI_LINE_30 | LL_EXTI_LINE_31) +/*!< All Extended line not reserved*/ + +#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ +#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ +#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ +#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ +#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ +#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ +#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ +#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ +#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ +#define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */ +#define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */ +#define LL_EXTI_LINE_43 EXTI_IMR2_IM43 /*!< Extended line 43 */ +#define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */ +#define LL_EXTI_LINE_45 EXTI_IMR2_IM45 /*!< Extended line 45 */ +#define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */ +#define LL_EXTI_LINE_47 EXTI_IMR2_IM47 /*!< Extended line 47 */ +#define LL_EXTI_LINE_48 EXTI_IMR2_IM48 /*!< Extended line 48 */ +#define LL_EXTI_LINE_49 EXTI_IMR2_IM49 /*!< Extended line 49 */ +#define LL_EXTI_LINE_50 EXTI_IMR2_IM50 /*!< Extended line 50 */ +#define LL_EXTI_LINE_51 EXTI_IMR2_IM51 /*!< Extended line 51 */ +#define LL_EXTI_LINE_52 EXTI_IMR2_IM52 /*!< Extended line 52 */ +#define LL_EXTI_LINE_53 EXTI_IMR2_IM53 /*!< Extended line 53 */ +#define LL_EXTI_LINE_54 EXTI_IMR2_IM54 /*!< Extended line 54 */ +#define LL_EXTI_LINE_55 EXTI_IMR2_IM55 /*!< Extended line 55 */ +#define LL_EXTI_LINE_56 EXTI_IMR2_IM56 /*!< Extended line 56 */ +#define LL_EXTI_LINE_57 EXTI_IMR2_IM57 /*!< Extended line 57 */ +#define LL_EXTI_LINE_58 EXTI_IMR2_IM58 /*!< Extended line 58 */ +#define LL_EXTI_LINE_59 EXTI_IMR2_IM59 /*!< Extended line 59 */ +#define LL_EXTI_LINE_ALL_32_63 (LL_EXTI_LINE_32 | LL_EXTI_LINE_33 | LL_EXTI_LINE_34 | LL_EXTI_LINE_35 | \ + LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | \ + LL_EXTI_LINE_40 | LL_EXTI_LINE_41 | LL_EXTI_LINE_42 | LL_EXTI_LINE_43 | \ + LL_EXTI_LINE_44 | LL_EXTI_LINE_45 | LL_EXTI_LINE_46 | LL_EXTI_LINE_47 | \ + LL_EXTI_LINE_48 | LL_EXTI_LINE_49 | LL_EXTI_LINE_50 | LL_EXTI_LINE_51 | \ + LL_EXTI_LINE_52 | LL_EXTI_LINE_53 | LL_EXTI_LINE_54 | LL_EXTI_LINE_55 | \ + LL_EXTI_LINE_56 | LL_EXTI_LINE_57 | LL_EXTI_LINE_58 | LL_EXTI_LINE_59) +/*!< All Extended line not reserved*/ + +#define LL_EXTI_LINE_77 EXTI_IMR3_IM77 /*!< Extended line 77 */ +#define LL_EXTI_LINE_ALL_64_95 LL_EXTI_LINE_77 /*!< All Extended line not reserved*/ + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 + * @note The reset value for the the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 64 to 95 + * @note The reset value for the direct lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR3 IMx LL_EXTI_EnableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR3, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 + * @note The reset value for the direct lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 64 to 95 + * @note The reset value for the the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR3 IMx LL_EXTI_DisableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR3, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 + * @note The reset value for the the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95 + * @note The reset value for the direct lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR3 IMx LL_EXTI_IsEnabledIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR1, ExtiLine); + +} + +/** + * @brief Enable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Event request for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_EnableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR3, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_DisableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR3, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); + +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_IsEnabledEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set.Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR2, ExtiLine); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR2, ExtiLine); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR1, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR1 + * register (by writing a 1 into the bit) + * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER1, ExtiLine); +} + +/** + * @brief Generate a software Interrupt Event for Lines in range 32 to 63 + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR2 + * register (by writing a 1 into the bit) + * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER2, ExtiLine); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine)); +} + +/** + * @brief Read ExtLine Combination Flag for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine)); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR1, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_54 + * @retval Please check each device line mapping for EXTI Line availability + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR2, ExtiLine); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +ErrorStatus LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_EXTI_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_fmc.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_fmc.h new file mode 100644 index 00000000000..81885680615 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_fmc.h @@ -0,0 +1,1162 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_fmc.h + * @author MCD Application Team + * @brief Header file of FMC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_FMC_H +#define STM32H7RSxx_LL_FMC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup FMC_LL + * @{ + */ + +/** @addtogroup FMC_LL_Private_Macros + * @{ + */ + +#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ + ((__BANK__) == FMC_NORSRAM_BANK2) || \ + ((__BANK__) == FMC_NORSRAM_BANK3) || \ + ((__BANK__) == FMC_NORSRAM_BANK4)) +#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) +#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) +#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) +#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ + ((__SIZE__) == FMC_PAGE_SIZE_128) || \ + ((__SIZE__) == FMC_PAGE_SIZE_256) || \ + ((__SIZE__) == FMC_PAGE_SIZE_512) || \ + ((__SIZE__) == FMC_PAGE_SIZE_1024)) +#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ + ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) +#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ + ((__MODE__) == FMC_ACCESS_MODE_B) || \ + ((__MODE__) == FMC_ACCESS_MODE_C) || \ + ((__MODE__) == FMC_ACCESS_MODE_D)) +#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) +#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) +#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) +#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) +#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) +#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) +#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) +#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) +#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FMC_WRITE_BURST_ENABLE)) +#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ + ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) +#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) +#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) +#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) +#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) +#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) +#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) + + +#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) +#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ + ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) +#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) +#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ + ((__STATE__) == FMC_NAND_ECC_ENABLE)) + +#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) +#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) + + +#define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32)) +#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ + ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) +#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) +#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ + ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) +#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) +#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) +#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) +#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) +#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) +#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U)) +#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U) +#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U) +#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) +#define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \ + ((__BANK__) == FMC_SDRAM_BANK2)) +#define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11)) +#define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \ + ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \ + ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13)) +#define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ + ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4)) +#define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \ + ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \ + ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3)) + + +/** + * @} + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types + * @{ + */ + +#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef +#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef +#define FMC_NAND_TypeDef FMC_Bank3_TypeDef +#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef + +#define FMC_NORSRAM_DEVICE FMC_Bank1_R +#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R +#define FMC_NAND_DEVICE FMC_Bank3_R +#define FMC_SDRAM_DEVICE FMC_Bank5_6_R + +/** + * @brief FMC NORSRAM Configuration Structure definition + */ +typedef struct +{ + uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. + This parameter can be a value of @ref FMC_NORSRAM_Bank */ + + uint32_t DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the data bus or not. + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + + uint32_t MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory device. + This parameter can be a value of @ref FMC_Memory_Type */ + + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + + uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FMC_Burst_Access_Mode */ + + uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + + uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FMC_Wait_Timing */ + + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ + + uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal */ + + uint32_t ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FMC_Extended_Mode */ + + uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FMC_AsynchronousWait */ + + uint32_t WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FMC_Write_Burst */ + + uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. + This parameter is only enabled through the FMC_BCR1 register, + and don't care through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Continous_Clock */ + + uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. + This parameter is only enabled through the FMC_BCR1 register, + and don't care through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Write_FIFO */ + + uint32_t PageSize; /*!< Specifies the memory page size. + This parameter can be a value of @ref FMC_Page_Size */ +} FMC_NORSRAM_InitTypeDef; + +/** + * @brief FMC NORSRAM Timing parameters structure definition + */ +typedef struct +{ + uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between Min_Data = 1 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between Min_Data = 1 and Max_Data = 255. + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed + NOR Flash memories. */ + + uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is only used for multiplexed NOR Flash memories. */ + + uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of + HCLK cycles. This parameter can be a value between Min_Data = 2 and + Max_Data = 16. + @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM + accesses. */ + + uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The parameter value depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between Min_Data = 2 and Max_Data = 17 + in NOR Flash memories with synchronous burst mode enable */ + + uint32_t AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FMC_Access_Mode */ +} FMC_NORSRAM_TimingTypeDef; + +/** + * @brief FMC NAND Configuration Structure definition + */ +typedef struct +{ + uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. + This parameter can be a value of @ref FMC_NAND_Bank */ + + uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. + This parameter can be any value of @ref FMC_Wait_feature */ + + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FMC_NAND_Data_Width */ + + uint32_t EccComputation; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FMC_ECC */ + + uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FMC_ECC_Page_Size */ + + uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + + uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ +} FMC_NAND_InitTypeDef; + +/** + * @brief FMC NAND Timing parameters structure definition + */ +typedef struct +{ + uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ + + uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ + + uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command de-assertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ + + uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + data bus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ +} FMC_NAND_PCC_TimingTypeDef; + + +/** + * @brief FMC SDRAM Configuration Structure definition + */ +typedef struct +{ + uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. + This parameter can be a value of @ref FMC_SDRAM_Bank */ + + uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. + This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */ + + uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. + This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */ + + uint32_t MemoryDataWidth; /*!< Defines the memory device width. + This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */ + + uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. + This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */ + + uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. + This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */ + + uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. + This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ + + uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow + to disable the clock before changing frequency. + This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ + + uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read + commands during the CAS latency and stores data in the Read FIFO. + This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */ + + uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. + This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ +} FMC_SDRAM_InitTypeDef; + +/** + * @brief FMC SDRAM Timing parameters structure definition + */ +typedef struct +{ + uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and + an active or Refresh command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to + issuing the Activate command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock + cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command + and the delay between two consecutive Refresh commands in number of + memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command + in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write + command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ +} FMC_SDRAM_TimingTypeDef; + +/** + * @brief SDRAM command parameters structure definition + */ +typedef struct +{ + uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. + This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ + + uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. + This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ + + uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued + in auto refresh mode. + This parameter can be a value between Min_Data = 1 and Max_Data = 15 */ + + uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ +} FMC_SDRAM_CommandTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants + * @{ + */ + +/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller + * @{ + */ + +/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank + * @{ + */ +#define FMC_NORSRAM_BANK1 (0x00000000U) +#define FMC_NORSRAM_BANK2 (0x00000002U) +#define FMC_NORSRAM_BANK3 (0x00000004U) +#define FMC_NORSRAM_BANK4 (0x00000006U) +/** + * @} + */ + +/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing + * @{ + */ +#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) +#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) +/** + * @} + */ + +/** @defgroup FMC_Memory_Type FMC Memory Type + * @{ + */ +#define FMC_MEMORY_TYPE_SRAM (0x00000000U) +#define FMC_MEMORY_TYPE_PSRAM (0x00000004U) +#define FMC_MEMORY_TYPE_NOR (0x00000008U) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width + * @{ + */ +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access + * @{ + */ +#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) +/** + * @} + */ + +/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode + * @{ + */ +#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) +#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity + * @{ + */ +#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) +#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) +/** + * @} + */ + +/** @defgroup FMC_Wait_Timing FMC Wait Timing + * @{ + */ +#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) +#define FMC_WAIT_TIMING_DURING_WS (0x00000800U) +/** + * @} + */ + +/** @defgroup FMC_Write_Operation FMC Write Operation + * @{ + */ +#define FMC_WRITE_OPERATION_DISABLE (0x00000000U) +#define FMC_WRITE_OPERATION_ENABLE (0x00001000U) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal FMC Wait Signal + * @{ + */ +#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) +#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) +/** + * @} + */ + +/** @defgroup FMC_Extended_Mode FMC Extended Mode + * @{ + */ +#define FMC_EXTENDED_MODE_DISABLE (0x00000000U) +#define FMC_EXTENDED_MODE_ENABLE (0x00004000U) +/** + * @} + */ + +/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait + * @{ + */ +#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) +#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) +/** + * @} + */ + +/** @defgroup FMC_Page_Size FMC Page Size + * @{ + */ +#define FMC_PAGE_SIZE_NONE (0x00000000U) +#define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0 +#define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1 +#define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\ + | FMC_BCRx_CPSIZE_1) +#define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2 +/** + * @} + */ + +/** @defgroup FMC_Write_Burst FMC Write Burst + * @{ + */ +#define FMC_WRITE_BURST_DISABLE (0x00000000U) +#define FMC_WRITE_BURST_ENABLE (0x00080000U) +/** + * @} + */ + +/** @defgroup FMC_Continous_Clock FMC Continuous Clock + * @{ + */ +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) +#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) +/** + * @} + */ + +#if defined(FMC_BCR1_WFDIS) +/** @defgroup FMC_Write_FIFO FMC Write FIFO + * @{ + */ +#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS +#define FMC_WRITE_FIFO_ENABLE (0x00000000U) +#endif /* FMC_BCR1_WFDIS */ +/** + * @} + */ + +/** @defgroup FMC_Access_Mode FMC Access Mode + * @{ + */ +#define FMC_ACCESS_MODE_A (0x00000000U) +#define FMC_ACCESS_MODE_B (0x10000000U) +#define FMC_ACCESS_MODE_C (0x20000000U) +#define FMC_ACCESS_MODE_D (0x30000000U) +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller + * @{ + */ +/** @defgroup FMC_NAND_Bank FMC NAND Bank + * @{ + */ +#define FMC_NAND_BANK3 (0x00000100U) +/** + * @} + */ + +/** @defgroup FMC_Wait_feature FMC Wait feature + * @{ + */ +#define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) +#define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) +/** + * @} + */ + +/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type + * @{ + */ +#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) +/** + * @} + */ + +/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width + * @{ + */ +#define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) +/** + * @} + */ + +/** @defgroup FMC_ECC FMC ECC + * @{ + */ +#define FMC_NAND_ECC_DISABLE (0x00000000U) +#define FMC_NAND_ECC_ENABLE (0x00000040U) +/** + * @} + */ + +/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size + * @{ + */ +#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) +#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) +#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) +#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) +#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) +#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller + * @{ + */ +/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank + * @{ + */ +#define FMC_SDRAM_BANK1 (0x00000000U) +#define FMC_SDRAM_BANK2 (0x00000001U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number + * @{ + */ +#define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U) +#define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U) +#define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U) +#define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number + * @{ + */ +#define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U) +#define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U) +#define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width + * @{ + */ +#define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FMC_SDRAM_MEM_BUS_WIDTH_32 (0x00000020U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number + * @{ + */ +#define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U) +#define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency + * @{ + */ +#define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U) +#define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U) +#define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection + * @{ + */ +#define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U) +#define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period + * @{ + */ +#define FMC_SDRAM_CLOCK_DISABLE (0x00000000U) +#define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U) +#define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst + * @{ + */ +#define FMC_SDRAM_RBURST_DISABLE (0x00000000U) +#define FMC_SDRAM_RBURST_ENABLE (0x00001000U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay + * @{ + */ +#define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U) +#define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U) +#define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode + * @{ + */ +#define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U) +#define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U) +#define FMC_SDRAM_CMD_PALL (0x00000002U) +#define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U) +#define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U) +#define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U) +#define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target + * @{ + */ +#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 +#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 +#define FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status + * @{ + */ +#define FMC_SDRAM_NORMAL_MODE (0x00000000U) +#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 +#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition + * @{ + */ +#define FMC_IT_RISING_EDGE (0x00000008U) +#define FMC_IT_LEVEL (0x00000010U) +#define FMC_IT_FALLING_EDGE (0x00000020U) +#define FMC_IT_REFRESH_ERROR (0x00004000U) +/** + * @} + */ + +/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition + * @{ + */ +#define FMC_FLAG_RISING_EDGE (0x00000001U) +#define FMC_FLAG_LEVEL (0x00000002U) +#define FMC_FLAG_FALLING_EDGE (0x00000004U) +#define FMC_FLAG_FEMPT (0x00000040U) +#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE +#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY +#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros + * @{ + */ +/** + * @brief Enable the FMC Peripheral. + * @retval None + */ +#define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN) + +/** + * @brief Disable the FMC Peripheral. + * @retval None + */ +#define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN) +/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros + * @brief macros to handle NOR device enable/disable and read/write operations + * @{ + */ + +/** + * @brief Enable the NORSRAM device access. + * @param __INSTANCE__ FMC_NORSRAM Instance + * @param __BANK__ FMC_NORSRAM Bank + * @retval None + */ +#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + |= FMC_BCRx_MBKEN) + +/** + * @brief Disable the NORSRAM device access. + * @param __INSTANCE__ FMC_NORSRAM Instance + * @param __BANK__ FMC_NORSRAM Bank + * @retval None + */ +#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + &= ~FMC_BCRx_MBKEN) + +/** + * @} + */ + +/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros + * @brief macros to handle NAND device enable/disable + * @{ + */ + +/** + * @brief Enable the NAND device access. + * @param __INSTANCE__ FMC_NAND Instance + * @retval None + */ +#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) + +/** + * @brief Disable the NAND device access. + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @retval None + */ +#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) + +/** + * @} + */ + +/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt + * @brief macros to handle NAND interrupts + * @{ + */ + +/** + * @brief Enable the NAND device interrupt. + * @param __INSTANCE__ FMC_NAND instance + * @param __INTERRUPT__ FMC_NAND interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FMC_IT_LEVEL: Interrupt level. + * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) + +/** + * @brief Disable the NAND device interrupt. + * @param __INSTANCE__ FMC_NAND Instance + * @param __INTERRUPT__ FMC_NAND interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FMC_IT_LEVEL: Interrupt level. + * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) + +/** + * @brief Get flag status of the NAND device. + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @param __FLAG__ FMC_NAND flag + * This parameter can be any combination of the following values: + * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FMC_FLAG_FEMPT: FIFO empty flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear flag status of the NAND device. + * @param __INSTANCE__ FMC_NAND Instance + * @param __FLAG__ FMC_NAND flag + * This parameter can be any combination of the following values: + * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FMC_FLAG_FEMPT: FIFO empty flag. + * @retval None + */ +#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) + +/** + * @} + */ + + +/** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt + * @brief macros to handle SDRAM interrupts + * @{ + */ + +/** + * @brief Enable the SDRAM device interrupt. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __INTERRUPT__ FMC_SDRAM interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error + * @retval None + */ +#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) + +/** + * @brief Disable the SDRAM device interrupt. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __INTERRUPT__ FMC_SDRAM interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error + * @retval None + */ +#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) + +/** + * @brief Get flag status of the SDRAM device. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __FLAG__ FMC_SDRAM flag + * This parameter can be any combination of the following values: + * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. + * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. + * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear flag status of the SDRAM device. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __FLAG__ FMC_SDRAM flag + * This parameter can be any combination of the following values: + * @arg FMC_SDRAM_FLAG_REFRESH_ERROR + * @retval None + */ +#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions + * @{ + */ + +/** @defgroup FMC_LL_NORSRAM NOR SRAM + * @{ + */ +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode); +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions + * @{ + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); +/** + * @} + */ +/** + * @} + */ + +/** @defgroup FMC_LL_NAND NAND + * @{ + */ +/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions + * @{ + */ +HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout); +/** + * @} + */ +/** + * @} + */ + + +/** @defgroup FMC_LL_SDRAM SDRAM + * @{ + */ +/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions + * @{ + */ +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); +HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); +HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, + uint32_t AutoRefreshNumber); +uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_FMC_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_gpio.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_gpio.h new file mode 100644 index 00000000000..026cd7f779f --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_gpio.h @@ -0,0 +1,994 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7RSxx_LL_GPIO_H +#define __STM32H7RSxx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || \ + defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || \ + defined (GPIOM) || defined (GPION) || defined (GPIOO) || defined (GPIOP) + +/** @defgroup GPIO_LL GPIO + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] + * which may be out of array bounds [..,UNKNOWN] in following APIs: + * LL_GPIO_GetAFPin_0_7 + * LL_GPIO_SetAFPin_0_7 + * LL_GPIO_SetAFPin_8_15 + * LL_GPIO_GetAFPin_8_15 + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \ + GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \ + GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \ + GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \ + GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \ + GPIO_BSRR_BS15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)), + (Mode << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)), + (Speed << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)), + (Pull << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)), + (Alternate << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)), + (Alternate << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))) + >> (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)); +} + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) +{ + return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BRR, PinMask); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, const LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || */ +/* defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || */ +/* defined (GPIOM) || defined (GPION) || defined (GPIOO) || defined (GPIOP) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_GPIO_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_i2c.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_i2c.h new file mode 100644 index 00000000000..7b234c5dc06 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_i2c.h @@ -0,0 +1,2372 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_i2c.h + * @author MCD Application Team + * @brief Header file of I2C LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_I2C_H +#define STM32H7RSxx_LL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) || defined (I2C3) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_LL_Private_Constants I2C Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeripheralMode; /*!< Specifies the peripheral mode. + This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetMode(). */ + + uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. + This parameter must be set by referring to the STM32CubeMX Tool and + the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetTiming(). */ + + uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. + This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. + + This feature can be modified afterwards using unitary functions + @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ + + uint32_t DigitalFilter; /*!< Configures the digital noise filter. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetDigitalFilter(). */ + + uint32_t OwnAddress1; /*!< Specifies the device own address 1. + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ + + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive + match code or next received byte. + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_AcknowledgeNextData(). */ + + uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ +} LL_I2C_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_I2C_WriteReg function + * @{ + */ +#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */ +#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */ +#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */ +#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */ +#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */ +#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */ +#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */ +#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */ +#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2C_ReadReg function + * @{ + */ +#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */ +#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */ +#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */ +#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */ +#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */ +#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */ +#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */ +#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */ +#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */ +#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */ +#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */ +#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ +#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ +#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */ +#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions + * @{ + */ +#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */ +#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */ +#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */ +#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */ +#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */ +#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */ +#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode + * @{ + */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ +#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode + (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection + * @{ + */ +#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ +#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode + * @{ + */ +#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ +#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length + * @{ + */ +#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ +#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks + * @{ + */ +#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ +#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. + All Address2 are acknowledged. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ +#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length + * @{ + */ +#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ +#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction + * @{ + */ +#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ +#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_MODE Transfer End Mode + * @{ + */ +#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ +#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Software end mode with HW PEC comparison. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation + * @{ + */ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U +/*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +/*!< Generate Stop condition (Size should be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \ + I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) +/*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 10Bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction + * @{ + */ +#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, + slave enters receiver mode. */ +#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, + slave enters transmitter mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for + transmission */ +#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for + reception */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect + SCL low level timeout. */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect + both SCL and SDA high level timeout.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ +#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) + enable bit */ +#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \ + I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB +(extended clock) enable bits */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings + * @{ + */ +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tscldel = (SCLDEL+1)xtpresc) + * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tsdadel = SDADELxtpresc) + * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tsclh = (SCLH+1)xtpresc) + * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tscll = (SCLL+1)xtpresc) + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \ + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable I2C peripheral (PE = 1). + * @rmtoll CR1 PE LL_I2C_Enable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Disable I2C peripheral (PE = 0). + * @note When PE = 0, the I2C SCL and SDA lines are released. + * Internal state machines and status bits are put back to their reset value. + * When cleared, PE must be kept low for at least 3 APB clock cycles. + * @rmtoll CR1 PE LL_I2C_Disable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Check if the I2C peripheral is enabled or disabled. + * @rmtoll CR1 PE LL_I2C_IsEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); +} + +/** + * @brief Configure Noise Filters (Analog and Digital). + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * The filters can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n + * CR1 DNF LL_I2C_ConfigFilters + * @param I2Cx I2C Instance. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref LL_I2C_ANALOGFILTER_ENABLE + * @arg @ref LL_I2C_ANALOGFILTER_DISABLE + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); +} + +/** + * @brief Configure Digital Noise Filter. + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter + * @param I2Cx I2C Instance. + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); +} + +/** + * @brief Get the current Digital Noise Filter configuration. + * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); +} + +/** + * @brief Enable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Disable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Check if Analog Noise Filter is enabled or disabled. + * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Disable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Check if DMA transmission requests are enabled or disabled. + * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Disable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Check if DMA reception requests are enabled or disabled. + * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n + * RXDR RXDATA LL_I2C_DMA_GetRegAddr + * @param I2Cx I2C Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) + { + /* return address of TXDR register */ + data_reg_addr = (uint32_t) &(I2Cx->TXDR); + } + else + { + /* return address of RXDR register */ + data_reg_addr = (uint32_t) &(I2Cx->RXDR); + } + + return data_reg_addr; +} + +/** + * @brief Enable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Disable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Check if Clock stretching is enabled or disabled. + * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); +} + +/** + * @brief Enable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Disable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Check if hardware byte control in slave mode is enabled or disabled. + * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); +} + +/** + * @brief Enable Wakeup from STOP. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @note This bit can only be programmed when Digital Filter is disabled. + * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN); +} + +/** + * @brief Disable Wakeup from STOP. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN); +} + +/** + * @brief Check if Wakeup from STOP is enabled or disabled. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable General Call. + * @note When enabled the Address 0x00 is ACKed. + * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Disable General Call. + * @note When disabled the Address 0x00 is NACKed. + * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Check if General Call is enabled or disabled. + * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable I2C Fast Mode Plus (FMP = 1). + * @note 20mA I/O drive enable + * @rmtoll CR1 FMP LL_I2C_EnableFastModePlus + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_FMP); +} + +/** + * @brief Disable I2C Fast Mode Plus (FMP = 0). + * @note 20mA I/O drive disable + * @rmtoll CR1 FMP LL_I2C_DisableFastModePlus + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP); +} + +/** + * @brief Check if the I2C Fast Mode Plus is enabled or disabled. + * @rmtoll CR1 FMP LL_I2C_IsEnabledFastModePlus + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL); +} + +/** + * @brief Enable automatic clear of ADDR flag. + * @rmtoll CR1 ADDRACLR LL_I2C_EnableAutoClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR); +} + +/** + * @brief Disable automatic clear of ADDR flag. + * @rmtoll CR1 ADDRACLR LL_I2C_DisableAutoClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR); +} + +/** + * @brief Check if the automatic clear of ADDR flag is enabled or disabled. + * @rmtoll CR1 ADDRACLR LL_I2C_IsEnabledAutoClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_ADDR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR) == (I2C_CR1_ADDRACLR)) ? 1UL : 0UL); +} + +/** + * @brief Enable automatic clear of STOP flag. + * @rmtoll CR1 STOPFACLR LL_I2C_EnableAutoClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR); +} + +/** + * @brief Disable automatic clear of STOP flag. + * @rmtoll CR1 STOPFACLR LL_I2C_DisableAutoClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR); +} + +/** + * @brief Check if the automatic clear of STOP flag is enabled or disabled. + * @rmtoll CR1 STOPFACLR LL_I2C_IsEnabledAutoClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_STOP(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR) == (I2C_CR1_STOPFACLR)) ? 1UL : 0UL); +} + +/** + * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. + * @note Changing this bit is not allowed, when the START bit is set. + * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode + * @param I2Cx I2C Instance. + * @param AddressingMode This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode); +} + +/** + * @brief Get the Master addressing mode. + * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + */ +__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); +} + +/** + * @brief Set the Own Address1. + * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n + * OAR1 OA1MODE LL_I2C_SetOwnAddress1 + * @param I2Cx I2C Instance. + * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + * @param OwnAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS1_7BIT + * @arg @ref LL_I2C_OWNADDRESS1_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) +{ + MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize); +} + +/** + * @brief Enable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Disable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); +} + +/** + * @brief Set the 7bits Own Address2. + * @note This action has no effect if own address2 is enabled. + * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n + * OAR2 OA2MSK LL_I2C_SetOwnAddress2 + * @param I2Cx I2C Instance. + * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F. + * @param OwnAddrMask This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS2_NOMASK + * @arg @ref LL_I2C_OWNADDRESS2_MASK01 + * @arg @ref LL_I2C_OWNADDRESS2_MASK02 + * @arg @ref LL_I2C_OWNADDRESS2_MASK03 + * @arg @ref LL_I2C_OWNADDRESS2_MASK04 + * @arg @ref LL_I2C_OWNADDRESS2_MASK05 + * @arg @ref LL_I2C_OWNADDRESS2_MASK06 + * @arg @ref LL_I2C_OWNADDRESS2_MASK07 + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask) +{ + MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask); +} + +/** + * @brief Enable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Disable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming + * @param I2Cx I2C Instance. + * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. + * @note This parameter is computed with the STM32CubeMX Tool. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) +{ + WRITE_REG(I2Cx->TIMINGR, Timing); +} + +/** + * @brief Get the Timing Prescaler setting. + * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); +} + +/** + * @brief Get the SCL low period setting. + * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); +} + +/** + * @brief Get the SCL high period setting. + * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); +} + +/** + * @brief Get the SDA hold time. + * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); +} + +/** + * @brief Get the SDA setup time. + * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); +} + +/** + * @brief Configure peripheral mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n + * CR1 SMBDEN LL_I2C_SetMode + * @param I2Cx I2C Instance. + * @param PeripheralMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode); +} + +/** + * @brief Get peripheral mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n + * CR1 SMBDEN LL_I2C_GetMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + */ +__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); +} + +/** + * @brief Enable SMBus alert (Host or Device mode) + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is drived low and + * Alert Response Address Header acknowledge is enabled. + * SMBus Host mode: + * - SMBus Alert pin management is supported. + * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Disable SMBus alert (Host or Device mode) + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is not drived (can be used as a standard GPIO) and + * Alert Response Address Header acknowledge is disabled. + * SMBus Host mode: + * - SMBus Alert pin management is not supported. + * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SMBus Packet Error Calculation (PEC). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Disable SMBus Packet Error Calculation (PEC). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @param TimeoutB + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, + uint32_t TimeoutB) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, + TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); +} + +/** + * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutA); +} + +/** + * @brief Get the SMBus Clock TimeoutA setting. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); +} + +/** + * @brief Set the SMBus Clock TimeoutA mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This bit can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode); +} + +/** + * @brief Get the SMBus Clock TimeoutA mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); +} + +/** + * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutB is disabled. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Enable the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + SET_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Disable the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Check if the SMBus Clock Timeout is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ + (ClockTimeout)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Disable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Check if the TXIS Interrupt is enabled or disabled. + * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Disable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Check if the RXNE Interrupt is enabled or disabled. + * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Disable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Check if Address match interrupt is enabled or disabled. + * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Disable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Check if Not acknowledge received interrupt is enabled or disabled. + * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Disable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Check if STOP detection interrupt is enabled or disabled. + * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Disable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Check if Transfer Complete interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Error interrupts. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Disable Error interrupts. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Check if Error interrupts are enabled or disabled. + * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Indicate the status of Transmit data register empty flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transmit interrupt flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Receive data register not empty flag. + * @note RESET: When Receive data register is read. + * SET: When the received data is copied in Receive data register. + * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Address matched flag (slave mode). + * @note RESET: Clear default value. + * SET: When the received slave address matched with one of the enabled slave address. + * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Not Acknowledge received flag. + * @note RESET: Clear default value. + * SET: When a NACK is received after a byte transmission. + * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Stop detection flag. + * @note RESET: Clear default value. + * SET: When a Stop condition is detected. + * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred. + * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=1 and NBYTES date have been transferred. + * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus error flag. + * @note RESET: Clear default value. + * SET: When a misplaced Start or Stop condition is detected. + * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Arbitration lost flag. + * @note RESET: Clear default value. + * SET: When arbitration lost. + * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Overrun/Underrun flag (slave mode). + * @note RESET: Clear default value. + * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). + * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus PEC error flag in reception. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When the received PEC does not match with the PEC register content. + * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus Timeout detection flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When a timeout or extended clock timeout occurs. + * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus alert flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When SMBus host configuration, SMBus alert enabled and + * a falling edge event occurs on SMBA pin. + * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus Busy flag. + * @note RESET: Clear default value. + * SET: When a Start condition is detected. + * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Clear Address Matched flag. + * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF); +} + +/** + * @brief Clear Not Acknowledge flag. + * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF); +} + +/** + * @brief Clear Stop detection flag. + * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF); +} + +/** + * @brief Clear Transmit data register empty flag (TXE). + * @note This bit can be clear by software in order to flush the transmit data register (TXDR). + * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx) +{ + WRITE_REG(I2Cx->ISR, I2C_ISR_TXE); +} + +/** + * @brief Clear Bus error flag. + * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF); +} + +/** + * @brief Clear Arbitration lost flag. + * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF); +} + +/** + * @brief Clear Overrun/Underrun flag. + * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF); +} + +/** + * @brief Clear SMBus PEC error flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_PECCF); +} + +/** + * @brief Clear SMBus Timeout detection flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF); +} + +/** + * @brief Clear SMBus Alert flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Enable automatic STOP condition generation (master mode). + * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. + * This bit has no effect in slave mode or when RELOAD bit is set. + * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Disable automatic STOP condition generation (master mode). + * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low. + * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Check if automatic STOP condition is enabled or disabled. + * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); +} + +/** + * @brief Enable reload mode (master mode). + * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set. + * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Disable reload mode (master mode). + * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow). + * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Check if reload mode is enabled or disabled. + * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); +} + +/** + * @brief Configure the number of bytes for transfer. + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize + * @param I2Cx I2C Instance. + * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Get the number of bytes configured for transfer. + * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code + or next received byte. + * @note Usage in Slave mode only. + * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData + * @param I2Cx I2C Instance. + * @param TypeAcknowledge This parameter can be one of the following values: + * @arg @ref LL_I2C_ACK + * @arg @ref LL_I2C_NACK + * @retval None + */ +__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge); +} + +/** + * @brief Generate a START or RESTART condition + * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. + * This action has no effect when RELOAD is set. + * @rmtoll CR2 START LL_I2C_GenerateStartCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_START); +} + +/** + * @brief Generate a STOP condition after the current byte transfer (master mode). + * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_STOP); +} + +/** + * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master sends the complete 10bit slave address read sequence : + * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address + in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master only sends the first 7 bits of 10bit address in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled. + * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); +} + +/** + * @brief Configure the transfer direction (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest + * @param I2Cx I2C Instance. + * @param TransferRequest This parameter can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest); +} + +/** + * @brief Get the transfer direction requested (master mode). + * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); +} + +/** + * @brief Configure the slave address for transfer (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr + * @param I2Cx I2C Instance. + * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr); +} + +/** + * @brief Get the slave address programmed for transfer. + * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n + * CR2 ADD10 LL_I2C_HandleTransfer\n + * CR2 RD_WRN LL_I2C_HandleTransfer\n + * CR2 START LL_I2C_HandleTransfer\n + * CR2 STOP LL_I2C_HandleTransfer\n + * CR2 RELOAD LL_I2C_HandleTransfer\n + * CR2 NBYTES LL_I2C_HandleTransfer\n + * CR2 AUTOEND LL_I2C_HandleTransfer\n + * CR2 HEAD10R LL_I2C_HandleTransfer + * @param I2Cx I2C Instance. + * @param SlaveAddr Specifies the slave address to be programmed. + * @param SlaveAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRSLAVE_7BIT + * @arg @ref LL_I2C_ADDRSLAVE_10BIT + * @param TransferSize Specifies the number of bytes to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=255. + * @param EndMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_RELOAD + * @arg @ref LL_I2C_MODE_AUTOEND + * @arg @ref LL_I2C_MODE_SOFTEND + * @arg @ref LL_I2C_MODE_SMBUS_RELOAD + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC + * @param Request This parameter can be one of the following values: + * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP + * @arg @ref LL_I2C_GENERATE_STOP + * @arg @ref LL_I2C_GENERATE_START_READ + * @arg @ref LL_I2C_GENERATE_START_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE + * @retval None + */ +__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, + uint32_t TransferSize, uint32_t EndMode, uint32_t Request) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ + ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ + (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, + tmp); +} + +/** + * @brief Indicate the value of transfer direction (slave mode). + * @note RESET: Write transfer, Slave enters in receiver mode. + * SET: Read transfer, Slave enters in transmitter mode. + * @rmtoll ISR DIR LL_I2C_GetTransferDirection + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DIRECTION_WRITE + * @arg @ref LL_I2C_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); +} + +/** + * @brief Return the slave matched address. + * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); +} + +/** + * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition + or an Address Matched is received. + * This bit has no effect when RELOAD bit is set. + * This bit has no effect in device mode when SBC bit is not set. + * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE); +} + +/** + * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); +} + +/** + * @brief Get the SMBus Packet Error byte calculated. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll PECR PEC LL_I2C_GetSMBusPEC + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); +} + +/** + * @brief Read Receive Data register. + * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8 + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx) +{ + return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); +} + +/** + * @brief Write in Transmit Data Register . + * @rmtoll TXDR TXDATA LL_I2C_TransmitData8 + * @param I2Cx I2C Instance. + * @param Data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) +{ + WRITE_REG(I2Cx->TXDR, Data); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct); +ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx); +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 || I2C3 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_I2C_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_i3c.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_i3c.h new file mode 100644 index 00000000000..81450b1471b --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_i3c.h @@ -0,0 +1,4407 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_i3c.h + * @author MCD Application Team + * @brief Header file of I3C LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_I3C_H +#define STM32H7RSxx_LL_I3C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (I3C1) + +/** @defgroup I3C_LL I3C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I3C_LL_Private_Macros I3C Private Macros + * @{ + */ +#if !defined(UNUSED) +#define UNUSED(x) ((void)(x)) +#endif /* !UNUSED */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I3C_LL_ES_CONTROLLER_BUS_CONFIG_STRUCTURE_DEFINITION I3C Controller Bus Configuration Structure definition + * @brief I3C LL Controller Bus Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t SDAHoldTime; /*!< Specifies the I3C SDA hold time. + This parameter must be a value of @ref I3C_LL_EC_SDA_HOLD_TIME */ + + uint32_t WaitTime; /*!< Specifies the time that the main and the new controllers should wait before + issuing a start. + This parameter must be a value of @ref I3C_LL_EC_OWN_ACTIVITY_STATE */ + + uint8_t SCLPPLowDuration; /*!< Specifies the I3C SCL low duration in number of kernel clock cycles + in I3C push-pull phases. + This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */ + + uint8_t SCLI3CHighDuration; /*!< Specifies the I3C SCL high duration in number of kernel clock cycles, + used for I3C messages for I3C open-drain and push pull phases. + This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */ + + uint8_t SCLODLowDuration; /*!< Specifies the I3C SCL low duration in number of kernel clock cycles in + open-drain phases, used for legacy I2C commands and for I3C open-drain phases. + This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */ + + uint8_t SCLI2CHighDuration; /*!< Specifies the I3C SCL high duration in number of kernel clock cycles, used + for legacy I2C commands. + This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */ + + uint8_t BusFreeDuration; /*!< Specifies the I3C controller duration in number of kernel clock cycles, after + a stop and before a start. + This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */ + + uint8_t BusIdleDuration; /*!< Specifies the I3C controller duration in number of kernel clock cycles to be + elapsed, after that both SDA and SCL are continuously high and stable + before issuing a hot-join event. + This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */ +} LL_I3C_CtrlBusConfTypeDef; +/** + * @} + */ + +/** @defgroup I3C_LL_ES_TARGET_BUS_CONFIG_STRUCTURE_DEFINITION I3C Target Bus Configuration Structure definition + * @brief I3C LL Target Bus Configuration Structure definition + * @{ + */ +typedef struct +{ + uint8_t BusAvailableDuration; /*!< Specifies the I3C target duration in number of kernel clock cycles, when + the SDA and the SCL are high for at least taval. + This parameter must be a number between Min_Data=0 and Max_Data=0xFF. */ +} LL_I3C_TgtBusConfTypeDef; +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup I3C_LL_ES_INIT I3C Exported Init structure + * @brief I3C LL Init Structure definition + * @{ + */ +typedef struct +{ + LL_I3C_CtrlBusConfTypeDef CtrlBusCharacteristic; /*!< Specifies the I3C controller bus characteristic configuration + when Controller mode */ + + LL_I3C_TgtBusConfTypeDef TgtBusCharacteristic; /*!< Specifies the I3C target bus characteristic configuration + when Target mode */ + +} LL_I3C_InitTypeDef; +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I3C_LL_Exported_Constants I3C Exported Constants + * @{ + */ + +/** @defgroup I3C_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I3C_ReadReg function + * @{ + */ +#define LL_I3C_EVR_CFEF I3C_EVR_CFEF +#define LL_I3C_EVR_TXFEF I3C_EVR_TXFEF +#define LL_I3C_EVR_CFNFF I3C_EVR_CFNFF +#define LL_I3C_EVR_SFNEF I3C_EVR_SFNEF +#define LL_I3C_EVR_TXFNFF I3C_EVR_TXFNFF +#define LL_I3C_EVR_RXFNEF I3C_EVR_RXFNEF +#define LL_I3C_EVR_RXLASTF I3C_EVR_RXLASTF +#define LL_I3C_EVR_TXLASTF I3C_EVR_TXLASTF +#define LL_I3C_EVR_FCF I3C_EVR_FCF +#define LL_I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF +#define LL_I3C_EVR_ERRF I3C_EVR_ERRF +#define LL_I3C_EVR_IBIF I3C_EVR_IBIF +#define LL_I3C_EVR_IBIENDF I3C_EVR_IBIENDF +#define LL_I3C_EVR_CRF I3C_EVR_CRF +#define LL_I3C_EVR_CRUPDF I3C_EVR_CRUPDF +#define LL_I3C_EVR_HJF I3C_EVR_HJF +#define LL_I3C_EVR_WKPF I3C_EVR_WKPF +#define LL_I3C_EVR_GETF I3C_EVR_GETF +#define LL_I3C_EVR_STAF I3C_EVR_STAF +#define LL_I3C_EVR_DAUPDF I3C_EVR_DAUPDF +#define LL_I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF +#define LL_I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF +#define LL_I3C_EVR_RSTF I3C_EVR_RSTF +#define LL_I3C_EVR_ASUPDF I3C_EVR_ASUPDF +#define LL_I3C_EVR_INTUPDF I3C_EVR_INTUPDF +#define LL_I3C_EVR_DEFF I3C_EVR_DEFF +#define LL_I3C_EVR_GRPF I3C_EVR_GRPF +#define LL_I3C_SER_PERR I3C_SER_PERR +#define LL_I3C_SER_STALL I3C_SER_STALL +#define LL_I3C_SER_DOVR I3C_SER_DOVR +#define LL_I3C_SER_COVR I3C_SER_COVR +#define LL_I3C_SER_ANACK I3C_SER_ANACK +#define LL_I3C_SER_DNACK I3C_SER_DNACK +#define LL_I3C_SER_DERR I3C_SER_DERR +/** + * @} + */ + +/** @defgroup I3C_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_I3C_ReadReg and LL_I3C_WriteReg functions + * @{ + */ +#define LL_I3C_IER_CFNFIE I3C_IER_CFNFIE +#define LL_I3C_IER_SFNEIE I3C_IER_SFNEIE +#define LL_I3C_IER_TXFNFIE I3C_IER_TXFNFIE +#define LL_I3C_IER_RXFNEIE I3C_IER_RXFNEIE +#define LL_I3C_IER_FCIE I3C_IER_FCIE +#define LL_I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE +#define LL_I3C_IER_ERRIE I3C_IER_ERRIE +#define LL_I3C_IER_IBIIE I3C_IER_IBIIE +#define LL_I3C_IER_IBIENDIE I3C_IER_IBIENDIE +#define LL_I3C_IER_CRIE I3C_IER_CRIE +#define LL_I3C_IER_CRUPDIE I3C_IER_CRUPDIE +#define LL_I3C_IER_HJIE I3C_IER_HJIE +#define LL_I3C_IER_WKPIE I3C_IER_WKPIE +#define LL_I3C_IER_GETIE I3C_IER_GETIE +#define LL_I3C_IER_STAIE I3C_IER_STAIE +#define LL_I3C_IER_DAUPDIE I3C_IER_DAUPDIE +#define LL_I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE +#define LL_I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE +#define LL_I3C_IER_RSTIE I3C_IER_RSTIE +#define LL_I3C_IER_ASUPDIE I3C_IER_ASUPDIE +#define LL_I3C_IER_INTUPDIE I3C_IER_INTUPDIE +#define LL_I3C_IER_DEFIE I3C_IER_DEFIE +#define LL_I3C_IER_GRPIE I3C_IER_GRPIE +/** + * @} + */ + +/** @defgroup I3C_LL_EC_MODE MODE + * @{ + */ +#define LL_I3C_MODE_CONTROLLER I3C_CFGR_CRINIT /*!< I3C Controller mode */ +#define LL_I3C_MODE_TARGET 0x00000000U /*!< I3C Target (Controller capable) mode */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE 0x00000000U /*!< Get address of data register used + for transmission in Byte */ +#define LL_I3C_DMA_REG_DATA_RECEIVE_BYTE 0x00000001U /*!< Get address of data register used + for reception in Byte */ +#define LL_I3C_DMA_REG_DATA_TRANSMIT_WORD 0x00000002U /*!< Get address of data register used for + transmission in Word */ +#define LL_I3C_DMA_REG_DATA_RECEIVE_WORD 0x00000003U /*!< Get address of data register used + for reception in Word */ +#define LL_I3C_DMA_REG_STATUS 0x00000004U /*!< Get address of status register used + for transfer status in Word */ +#define LL_I3C_DMA_REG_CONTROL 0x00000005U /*!< Get address of control register used + for transfer control in Word */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_RX_THRESHOLD RX THRESHOLD + * @{ + */ +#define LL_I3C_RXFIFO_THRESHOLD_1_4 0x00000000U +/*!< Rx Fifo Threshold is 1 byte in a Fifo depth of 4 bytes */ +#define LL_I3C_RXFIFO_THRESHOLD_4_4 I3C_CFGR_RXTHRES +/*!< Rx Fifo Threshold is 4 bytes in a Fifo depth of 4 bytes */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_TX_THRESHOLD TX THRESHOLD + * @{ + */ +#define LL_I3C_TXFIFO_THRESHOLD_1_4 0x00000000U +/*!< Tx Fifo Threshold is 1 byte in a Fifo depth of 4 bytes */ +#define LL_I3C_TXFIFO_THRESHOLD_4_4 I3C_CFGR_TXTHRES +/*!< Tx Fifo Threshold is 4 bytes in a Fifo depth of 4 bytes */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_PAYLOAD PAYLOAD + * @{ + */ +#define LL_I3C_PAYLOAD_EMPTY 0x00000000U +/*!< Empty payload, no additional data after IBI acknowledge */ +#define LL_I3C_PAYLOAD_1_BYTE I3C_MAXRLR_IBIP_0 +/*!< One additional data byte after IBI acknowledge */ +#define LL_I3C_PAYLOAD_2_BYTES I3C_MAXRLR_IBIP_1 +/*!< Two additional data bytes after IBI acknowledge */ +#define LL_I3C_PAYLOAD_3_BYTES (I3C_MAXRLR_IBIP_1 | I3C_MAXRLR_IBIP_0) +/*!< Three additional data bytes after IBI acknowledge */ +#define LL_I3C_PAYLOAD_4_BYTES I3C_MAXRLR_IBIP_2 +/*!< Four additional data bytes after IBI acknowledge */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_SDA_HOLD_TIME SDA HOLD TIME 0 + * @{ + */ +#define LL_I3C_SDA_HOLD_TIME_0_5 0x00000000U /*!< SDA hold time is 0.5 x ti3cclk */ +#define LL_I3C_SDA_HOLD_TIME_1_5 I3C_TIMINGR1_SDA_HD /*!< SDA hold time is 1.5 x ti3cclk */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_OWN_ACTIVITY_STATE OWN ACTIVITY STATE + * @{ + */ +#define LL_I3C_OWN_ACTIVITY_STATE_0 0x00000000U +/*!< Own Controller Activity state 0 */ +#define LL_I3C_OWN_ACTIVITY_STATE_1 I3C_TIMINGR1_ASNCR_0 +/*!< Own Controller Activity state 1 */ +#define LL_I3C_OWN_ACTIVITY_STATE_2 I3C_TIMINGR1_ASNCR_1 +/*!< Own Controller Activity state 2 */ +#define LL_I3C_OWN_ACTIVITY_STATE_3 (I3C_TIMINGR1_ASNCR_1 | I3C_TIMINGR1_ASNCR_0) +/*!< Own Controller Activity state 3 */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_DEVICE_ROLE_AS DEVICE ROLE AS + * @{ + */ +#define LL_I3C_DEVICE_ROLE_AS_TARGET 0x00000000U /*!< I3C Target */ +#define LL_I3C_DEVICE_ROLE_AS_CONTROLLER I3C_BCR_BCR6 /*!< I3C Controller */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_IBI_NO_ADDITIONAL IBI NO ADDITIONAL + * @{ + */ +#define LL_I3C_IBI_NO_ADDITIONAL_DATA 0x00000000U /*!< No data byte follows the accepted IBI */ +#define LL_I3C_IBI_ADDITIONAL_DATA I3C_BCR_BCR2 /*!< A Mandatory Data Byte (MDB) + follows the accepted IBI */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_MAX_DATA_SPEED_LIMITATION MAX DATA SPEED LIMITATION + * @{ + */ +#define LL_I3C_NO_DATA_SPEED_LIMITATION 0x00000000U /*!< No max data speed limitation */ +#define LL_I3C_MAX_DATA_SPEED_LIMITATION I3C_BCR_BCR0 /*!< Max data speed limitation */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_IBI_MDB_READ_NOTIFICATION IBI MDB READ NOTIFICATION + * @{ + */ +#define LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION 0x00000000U +/*!< No support of pending read notification via the IBI MDB[7:0] value */ +#define LL_I3C_MDB_PENDING_READ_NOTIFICATION I3C_GETCAPR_CAPPEND +/*!< Support of pending read notification via the IBI MDB[7:0] value */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_HANDOFF_GRP_ADDR_NOT HANDOFF GRP ADDR NOT + * @{ + */ +#define LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED 0x00000000U /*!< Group Address Handoff is not supported */ +#define LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED I3C_CRCAPR_CAPGRP /*!< Group Address Handoff is supported */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_HANDOFF HANDOFF + * @{ + */ +#define LL_I3C_HANDOFF_NOT_DELAYED 0x00000000U +/*!< Additional time to process controllership handoff is not needed */ +#define LL_I3C_HANDOFF_DELAYED I3C_CRCAPR_CAPDHOFF +/*!< Additional time to process controllership handoff is needed */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_HANDOFF_ACTIVITY_STATE HANDOFF ACTIVITY STATE + * @{ + */ +#define LL_I3C_HANDOFF_ACTIVITY_STATE_0 0x00000000U +/*!< Indicates that will act according to Activity State 0 after controllership handoff */ +#define LL_I3C_HANDOFF_ACTIVITY_STATE_1 I3C_GETMXDSR_HOFFAS_0 +/*!< Indicates that will act according to Activity State 1 after controllership handoff */ +#define LL_I3C_HANDOFF_ACTIVITY_STATE_2 I3C_GETMXDSR_HOFFAS_1 +/*!< Indicates that will act according to Activity State 2 after controllership handoff */ +#define LL_I3C_HANDOFF_ACTIVITY_STATE_3 (I3C_GETMXDSR_HOFFAS_1 | I3C_GETMXDSR_HOFFAS_0) +/*!< Indicates that will act according to Activity State 3 after controllership handoff */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_GETMXDS_FORMAT GETMXDS FORMAT + * @{ + */ +#define LL_I3C_GETMXDS_FORMAT_1 0x00000000U +/*!< GETMXDS CCC Format 1 is used, no MaxRdTurn field in response */ +#define LL_I3C_GETMXDS_FORMAT_2_LSB I3C_GETMXDSR_FMT_0 +/*!< GETMXDS CCC Format 2 is used, MaxRdTurn field in response, LSB = RDTURN[7:0] */ +#define LL_I3C_GETMXDS_FORMAT_2_MID I3C_GETMXDSR_FMT_1 +/*!< GETMXDS CCC Format 2 is used, MaxRdTurn field in response, Middle byte = RDTURN[7:0] */ +#define LL_I3C_GETMXDS_FORMAT_2_MSB (I3C_GETMXDSR_FMT_1 | I3C_GETMXDSR_FMT_0) +/*!< GETMXDS CCC Format 2 is used, MaxRdTurn field in response, MSB = RDTURN[7:0] */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_GETMXDS_TSCO GETMXDS TSCO + * @{ + */ +#define LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS 0x00000000U /*!< clock-to-data turnaround time tSCO <= 12ns */ +#define LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS I3C_GETMXDSR_TSCO /*!< clock-to-data turnaround time tSCO > 12ns */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_BUS_ACTIVITY_STATE BUS ACTIVITY STATE + * @{ + */ +#define LL_I3C_BUS_ACTIVITY_STATE_0 0x00000000U +/*!< Controller on the Bus Activity State 0 */ +#define LL_I3C_BUS_ACTIVITY_STATE_1 I3C_DEVR0_AS_0 +/*!< Controller on the Bus Activity State 1 */ +#define LL_I3C_BUS_ACTIVITY_STATE_2 I3C_DEVR0_AS_1 +/*!< Controller on the Bus Activity State 2 */ +#define LL_I3C_BUS_ACTIVITY_STATE_3 (I3C_DEVR0_AS_1 | I3C_DEVR0_AS_0) +/*!< Controller on the Bus Activity State 3 */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_RESET_ACTION RESET ACTION + * @{ + */ +#define LL_I3C_RESET_ACTION_NONE 0x00000000U +/*!< No Reset Action Required */ +#define LL_I3C_RESET_ACTION_PARTIAL I3C_DEVR0_RSTACT_0 +/*!< Reset of some internal registers of the peripheral*/ +#define LL_I3C_RESET_ACTION_FULL I3C_DEVR0_RSTACT_1 +/*!< Reset all internal registers of the peripheral */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_DIRECTION DIRECTION + * @{ + */ +#define LL_I3C_DIRECTION_WRITE 0x00000000U /*!< Write transfer */ +#define LL_I3C_DIRECTION_READ I3C_CR_RNW /*!< Read transfer */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_GENERATE GENERATE + * @{ + */ +#define LL_I3C_GENERATE_STOP I3C_CR_MEND +/*!< Generate Stop condition after sending a message */ +#define LL_I3C_GENERATE_RESTART 0x00000000U +/*!< Generate Restart condition after sending a message */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_CONTROLLER_MTYPE CONTROLLER MTYPE + * @{ + */ +#define LL_I3C_CONTROLLER_MTYPE_RELEASE 0x00000000U +/*!< SCL output clock stops running until next instruction executed */ +#define LL_I3C_CONTROLLER_MTYPE_HEADER I3C_CR_MTYPE_0 +/*!< Header Message */ +#define LL_I3C_CONTROLLER_MTYPE_PRIVATE I3C_CR_MTYPE_1 +/*!< Private Message Type */ +#define LL_I3C_CONTROLLER_MTYPE_DIRECT (I3C_CR_MTYPE_1 | I3C_CR_MTYPE_0) +/*!< Direct Message Type */ +#define LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C I3C_CR_MTYPE_2 +/*!< Legacy I2C Message Type */ +#define LL_I3C_CONTROLLER_MTYPE_CCC (I3C_CR_MTYPE_2 | I3C_CR_MTYPE_1) +/*!< Common Command Code */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_TARGET_MTYPE_HOT TARGET MTYPE HOT + * @{ + */ +#define LL_I3C_TARGET_MTYPE_HOT_JOIN I3C_CR_MTYPE_3 /*!< Hot Join*/ +#define LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ (I3C_CR_MTYPE_3 | I3C_CR_MTYPE_0) /*!< Controller-role Request */ +#define LL_I3C_TARGET_MTYPE_IBI (I3C_CR_MTYPE_3 | I3C_CR_MTYPE_1) /*!< In Band Interrupt (IBI) */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_MESSAGE MESSAGE + * @{ + */ +#define LL_I3C_MESSAGE_ERROR 0x00000000U /*!< An error has been detected in the message */ +#define LL_I3C_MESSAGE_SUCCESS I3C_SR_OK /*!< The message ended with success */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_MESSAGE_DIRECTION MESSAGE DIRECTION + * @{ + */ +#define LL_I3C_MESSAGE_DIRECTION_WRITE 0x00000000U /*!< Write data or command */ +#define LL_I3C_MESSAGE_DIRECTION_READ I3C_SR_DIR /*!< Read data */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_CONTROLLER_ERROR CONTROLLER ERROR + * @{ + */ +#define LL_I3C_CONTROLLER_ERROR_CE0 0x00000000U +/*!< Controller detected an illegally formatted CCC */ +#define LL_I3C_CONTROLLER_ERROR_CE1 I3C_SER_CODERR_0 +/*!< Controller detected that transmitted data on the bus is different than expected */ +#define LL_I3C_CONTROLLER_ERROR_CE2 I3C_SER_CODERR_1 +/*!< Controller detected that broadcast address 7'h7E has been nacked */ +#define LL_I3C_CONTROLLER_ERROR_CE3 (I3C_SER_CODERR_1 | I3C_SER_CODERR_0) +/*!< Controller detected that new Controller did not drive the bus after Controller-role handoff */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_TARGET_ERROR TARGET ERROR + * @{ + */ +#define LL_I3C_TARGET_ERROR_TE0 I3C_SER_CODERR_3 +/*!< Target detected an invalid broadcast address */ +#define LL_I3C_TARGET_ERROR_TE1 (I3C_SER_CODERR_3 | I3C_SER_CODERR_0) +/*!< Target detected an invalid CCC Code */ +#define LL_I3C_TARGET_ERROR_TE2 (I3C_SER_CODERR_3 | I3C_SER_CODERR_1) +/*!< Target detected an invalid write data */ +#define LL_I3C_TARGET_ERROR_TE3 (I3C_SER_CODERR_3 | I3C_SER_CODERR_1 | I3C_SER_CODERR_0) +/*!< Target detected an invalid assigned address during Dynamic Address Assignment procedure */ +#define LL_I3C_TARGET_ERROR_TE4 (I3C_SER_CODERR_3 | I3C_SER_CODERR_2) +/*!< Target detected 7'h7E missing after Restart during Dynamic Address Assignment procedure */ +#define LL_I3C_TARGET_ERROR_TE5 (I3C_SER_CODERR_3 | I3C_SER_CODERR_2 | I3C_SER_CODERR_0) +/*!< Target detected an illegally formatted CCC */ +#define LL_I3C_TARGET_ERROR_TE6 (I3C_SER_CODERR_3 | I3C_SER_CODERR_2 | I3C_SER_CODERR_1) +/*!< Target detected that transmitted data on the bus is different than expected */ +/** + * @} + */ + +/** @defgroup I3C_BCR_IN_PAYLOAD I3C BCR IN PAYLOAD + * @{ + */ +#define LL_I3C_BCR_IN_PAYLOAD_SHIFT 48 /*!< BCR field in target payload */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_IBI_CAPABILITY IBI CAPABILITY + * @{ + */ +#define LL_I3C_IBI_CAPABILITY I3C_DEVRX_IBIACK +/*!< Controller acknowledge Target In Band Interrupt capable */ +#define LL_I3C_IBI_NO_CAPABILITY 0x00000000U +/*!< Controller no acknowledge Target In Band Interrupt capable */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_IBI_ADDITIONAL_DATA IBI ADDITIONAL DATA + * @{ + */ +#define LL_I3C_IBI_DATA_ENABLE I3C_DEVRX_IBIDEN +/*!< A mandatory data byte follows the IBI acknowledgement */ +#define LL_I3C_IBI_DATA_DISABLE 0x00000000U +/*!< No mandatory data byte follows the IBI acknowledgement */ +/** + * @} + */ + +/** @defgroup I3C_LL_EC_CR_CAPABILITY CR CAPABILITY + * @{ + */ +#define LL_I3C_CR_CAPABILITY I3C_DEVRX_CRACK +/*!< Controller acknowledge Target Controller Role capable */ +#define LL_I3C_CR_NO_CAPABILITY 0x00000000U +/*!< Controller no acknowledge Target Controller Role capable */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I3C_LL_Exported_Macros I3C Exported Macros + * @{ + */ + +/** @defgroup I3C_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** @brief Get Bus Characterics in payload (64bits) receive during ENTDAA procedure. + * @param __PAYLOAD__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFFFFFFFF. + * @retval The value of BCR Return value between Min_Data=0x00 and Max_Data=0xFF. + */ +#define LL_I3C_GET_BCR(__PAYLOAD__) (((uint32_t)((uint64_t)(__PAYLOAD__) >> LL_I3C_BCR_IN_PAYLOAD_SHIFT)) & \ + I3C_BCR_BCR) + +/** @brief Check IBI request capabilities. + * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval Value of @ref I3C_LL_EC_IBI_CAPABILITY. + */ +#define LL_I3C_GET_IBI_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR1_Msk) >> I3C_BCR_BCR1_Pos) == 1U) \ + ? LL_I3C_IBI_CAPABILITY : LL_I3C_IBI_NO_CAPABILITY) + +/** @brief Check IBI additional data byte capabilities. + * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval Value of @ref I3C_LL_EC_IBI_ADDITIONAL_DATA. + */ +#define LL_I3C_GET_IBI_PAYLOAD(__BCR__) (((((__BCR__) & I3C_BCR_BCR2_Msk) >> I3C_BCR_BCR2_Pos) == 1U) \ + ? LL_I3C_IBI_DATA_ENABLE : LL_I3C_IBI_DATA_DISABLE) + +/** @brief Check Controller role request capabilities. + * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval Value of @ref I3C_LL_EC_CR_CAPABILITY. + */ +#define LL_I3C_GET_CR_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR6_Msk) >> I3C_BCR_BCR6_Pos) == 1U) \ + ? LL_I3C_CR_CAPABILITY : LL_I3C_CR_NO_CAPABILITY) + +/** + * @brief Write a value in I3C register + * @param __INSTANCE__ I3C Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I3C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I3C register + * @param __INSTANCE__ I3C Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I3C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I3C_LL_Exported_Functions I3C Exported Functions + * @{ + */ + +/** @defgroup I3C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable I3C peripheral (EN = 1). + * @rmtoll CFGR EN LL_I3C_Enable + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_Enable(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_EN); +} + +/** + * @brief Disable I3C peripheral (EN = 0). + * @note Controller mode: before clearing EN, all possible target requests must be disabled using DISEC CCC. + * Target mode: software is not expected clearing EN unless a partial reset of the IP is needed + * @rmtoll CFGR EN LL_I3C_Disable + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_Disable(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_EN); +} + +/** + * @brief Check if the I3C peripheral is enabled or disabled. + * @rmtoll CFGR EN LL_I3C_IsEnabled + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabled(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_EN) == (I3C_CFGR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Check if Reset action is required or not required. + * @note This bit indicates if Reset Action field has been updated by HW upon reception + * of RSTACT during current frame. + * @rmtoll DEVR0 RSTVAL LL_I3C_IsEnabledReset + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledReset(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_RSTVAL) == (I3C_DEVR0_RSTVAL)) ? 1UL : 0UL); +} + +/** + * @brief Configure peripheral mode. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * @rmtoll CFGR CRINIT LL_I3C_SetMode + * @param I3Cx I3C Instance. + * @param PeripheralMode This parameter can be one of the following values: + * @arg @ref LL_I3C_MODE_CONTROLLER + * @arg @ref LL_I3C_MODE_TARGET + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetMode(I3C_TypeDef *I3Cx, uint32_t PeripheralMode) +{ + MODIFY_REG(I3Cx->CFGR, I3C_CFGR_CRINIT, PeripheralMode); +} + +/** + * @brief Get peripheral mode. + * @rmtoll CFGR CRINIT LL_I3C_GetMode + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_MODE_CONTROLLER + * @arg @ref LL_I3C_MODE_TARGET + */ +__STATIC_INLINE uint32_t LL_I3C_GetMode(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)((READ_BIT(I3Cx->CFGR, I3C_CFGR_CRINIT) == (I3C_CFGR_CRINIT)) ? 1UL : 0UL); +} + +/** + * @brief An arbitration header (7'h7E) is sent after Start in case of legacy I2C or I3C private transfers. + * @note This bit can be modified only when there is no frame ongoing + * @rmtoll CFGR NOARBH LL_I3C_EnableArbitrationHeader + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableArbitrationHeader(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_NOARBH); +} + +/** + * @brief Target address is sent directly after a Start in case of legacy I2C or I3C private transfers. + * @note This bit can be modified only when there is no frame ongoing + * @rmtoll CFGR NOARBH LL_I3C_DisableArbitrationHeader + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableArbitrationHeader(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_NOARBH); +} + +/** + * @brief Check if the arbitration header is enabled of disabled. + * @rmtoll CFGR NOARBH LL_I3C_IsEnabledArbitrationHeader + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledArbitrationHeader(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_NOARBH) == (I3C_CFGR_NOARBH)) ? 0UL : 1UL); +} + +/** + * @brief A Reset Pattern is inserted before the STOP at the end of a frame when the last CCC + * of the frame was RSTACT CCC. + * @note This bit can be modified only when there is no frame ongoing + * @rmtoll CFGR RSTPTRN LL_I3C_EnableResetPattern + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableResetPattern(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_RSTPTRN); +} + +/** + * @brief A single STOP is emitted at the end of a frame. + * @note This bit can be modified only when there is no frame ongoing + * @rmtoll CFGR RSTPTRN LL_I3C_DisableResetPattern + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableResetPattern(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_RSTPTRN); +} + +/** + * @brief Check if Reset Pattern is enabled of disabled. + * @rmtoll CFGR RSTPTRN LL_I3C_IsEnabledResetPattern + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledResetPattern(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_RSTPTRN) == (I3C_CFGR_RSTPTRN)) ? 1UL : 0UL); +} + +/** + * @brief An Exit Pattern is sent after header (MTYPE = header) to program an escalation fault. + * @note This bit can be modified only when there is no frame ongoing + * @rmtoll CFGR EXITPTRN LL_I3C_EnableExitPattern + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableExitPattern(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_EXITPTRN); +} + +/** + * @brief An Exit Pattern is not sent after header (MTYPE = header). + * @note This bit can be modified only when there is no frame ongoing + * @rmtoll CFGR EXITPTRN LL_I3C_DisableExitPattern + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableExitPattern(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_EXITPTRN); +} + +/** + * @brief Check if Exit Pattern is enabled or disabled. + * @rmtoll CFGR EXITPTRN LL_I3C_IsEnabledExitPattern + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledExitPattern(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_EXITPTRN) == (I3C_CFGR_EXITPTRN)) ? 1UL : 0UL); +} + +/** + * @brief High Keeper is enabled and will be used in place of standard Open drain Pull Up device + * during handoff procedures. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * @rmtoll CFGR HKSDAEN LL_I3C_EnableHighKeeperSDA + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableHighKeeperSDA(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_HKSDAEN); +} + +/** + * @brief High Keeper is disabled. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * @rmtoll CFGR HKSDAEN LL_I3C_DisableHighKeeperSDA + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableHighKeeperSDA(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_HKSDAEN); +} + +/** + * @brief Check if High Keeper is enabled or disabled. + * @rmtoll CFGR HKSDAEN LL_I3C_IsEnabledHighKeeperSDA + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledHighKeeperSDA(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_HKSDAEN) == (I3C_CFGR_HKSDAEN)) ? 1UL : 0UL); +} + +/** + * @brief Hot Join Request is Acked. Current frame on the bus is continued. + * An Hot Join interrupt is sent through HJF flag. + * @note This bit can be used when I3C is acting as a Controller. + * @rmtoll CFGR HJACK LL_I3C_EnableHJAck + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableHJAck(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_HJACK); +} + +/** + * @brief Hot Join Request is Nacked. Current frame on the bus is continued. + * No Hot Join interrupt is generated. + * @note This bit can be used when I3C is acting as a Controller. + * @rmtoll CFGR HJACK LL_I3C_DisableHJAck + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableHJAck(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_HJACK); +} + +/** + * @brief Check if Hot Join Request Acknowledgement is enabled or disabled. + * @rmtoll CFGR HJACK LL_I3C_IsEnabledHJAck + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledHJAck(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_HJACK) == (I3C_CFGR_HJACK)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TDR TDB0 LL_I3C_DMA_GetRegAddr\n + * TDWR TDWR LL_I3C_DMA_GetRegAddr\n + * RDR RXRB0 LL_I3C_DMA_GetRegAddr\n + * RDWR RDWR LL_I3C_DMA_GetRegAddr\n + * SR SR LL_I3C_DMA_GetRegAddr\n + * CR CR LL_I3C_DMA_GetRegAddr + * @param I3Cx I3C Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE + * @arg @ref LL_I3C_DMA_REG_DATA_RECEIVE_BYTE + * @arg @ref LL_I3C_DMA_REG_DATA_TRANSMIT_WORD + * @arg @ref LL_I3C_DMA_REG_DATA_RECEIVE_WORD + * @arg @ref LL_I3C_DMA_REG_STATUS + * @arg @ref LL_I3C_DMA_REG_CONTROL + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I3C_DMA_GetRegAddr(const I3C_TypeDef *I3Cx, uint32_t Direction) +{ + register uint32_t data_reg_addr; + + if (Direction == LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(I3Cx->TDR); + } + else if (Direction == LL_I3C_DMA_REG_DATA_RECEIVE_BYTE) + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(I3Cx->RDR); + } + else if (Direction == LL_I3C_DMA_REG_DATA_TRANSMIT_WORD) + { + /* return address of TDWR register */ + data_reg_addr = (uint32_t) &(I3Cx->TDWR); + } + else if (Direction == LL_I3C_DMA_REG_DATA_RECEIVE_WORD) + { + /* return address of RDWR register */ + data_reg_addr = (uint32_t) &(I3Cx->RDWR); + } + else if (Direction == LL_I3C_DMA_REG_STATUS) + { + /* return address of SR register */ + data_reg_addr = (uint32_t) &(I3Cx->SR); + } + else + { + /* return address of CR register */ + data_reg_addr = (uint32_t) &(I3Cx->CR); + } + + return data_reg_addr; +} + +/** + * @brief Enable DMA FIFO reception requests. + * @rmtoll CFGR RXDMAEN LL_I3C_EnableDMAReq_RX + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableDMAReq_RX(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_RXDMAEN); +} + +/** + * @brief Disable DMA FIFO reception requests. + * @rmtoll CFGR RXDMAEN LL_I3C_DisableDMAReq_RX + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableDMAReq_RX(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_RXDMAEN); +} + +/** + * @brief Check if DMA FIFO reception requests are enabled or disabled. + * @rmtoll CFGR RXDMAEN LL_I3C_IsEnabledDMAReq_RX + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_RX(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_RXDMAEN) == (I3C_CFGR_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the Receive FIFO Threshold level. + * @rmtoll CFGR RXTHRES LL_I3C_SetRxFIFOThreshold + * @param I3Cx I3C Instance. + * @param RxFIFOThreshold This parameter can be one of the following values: + * @arg @ref LL_I3C_RXFIFO_THRESHOLD_1_4 + * @arg @ref LL_I3C_RXFIFO_THRESHOLD_4_4 + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetRxFIFOThreshold(I3C_TypeDef *I3Cx, uint32_t RxFIFOThreshold) +{ + MODIFY_REG(I3Cx->CFGR, I3C_CFGR_RXTHRES, RxFIFOThreshold); +} + +/** + * @brief Get the Receive FIFO Threshold level. + * @rmtoll CFGR RXTHRES LL_I3C_GetRxFIFOThreshold + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_RXFIFO_THRESHOLD_1_4 + * @arg @ref LL_I3C_RXFIFO_THRESHOLD_4_4 + */ +__STATIC_INLINE uint32_t LL_I3C_GetRxFIFOThreshold(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->CFGR, I3C_CFGR_RXTHRES)); +} + +/** + * @brief Enable DMA FIFO transmission requests. + * @rmtoll CFGR TXDMAEN LL_I3C_EnableDMAReq_TX + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableDMAReq_TX(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_TXDMAEN); +} + +/** + * @brief Disable DMA FIFO transmission requests. + * @rmtoll CFGR TXDMAEN LL_I3C_DisableDMAReq_TX + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableDMAReq_TX(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_TXDMAEN); +} + +/** + * @brief Check if DMA FIFO transmission requests are enabled or disabled. + * @rmtoll CFGR TXDMAEN LL_I3C_IsEnabledDMAReq_TX + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_TX(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_TXDMAEN) == (I3C_CFGR_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the Transmit FIFO Threshold level. + * @rmtoll CFGR TXTHRES LL_I3C_SetTxFIFOThreshold + * @param I3Cx I3C Instance. + * @param TxFIFOThreshold This parameter can be one of the following values: + * @arg @ref LL_I3C_TXFIFO_THRESHOLD_1_4 + * @arg @ref LL_I3C_TXFIFO_THRESHOLD_4_4 + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetTxFIFOThreshold(I3C_TypeDef *I3Cx, uint32_t TxFIFOThreshold) +{ + MODIFY_REG(I3Cx->CFGR, I3C_CFGR_TXTHRES, TxFIFOThreshold); +} + +/** + * @brief Get the Transmit FIFO Threshold level. + * @rmtoll CFGR TXTHRES LL_I3C_GetTxFIFOThreshold + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_TXFIFO_THRESHOLD_1_4 + * @arg @ref LL_I3C_TXFIFO_THRESHOLD_4_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_GetTxFIFOThreshold(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->CFGR, I3C_CFGR_TXTHRES)); +} + +/** + * @brief Enable DMA FIFO Status requests. + * @rmtoll CFGR SDMAEN LL_I3C_EnableDMAReq_Status + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableDMAReq_Status(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_SDMAEN); +} + +/** + * @brief Disable DMA FIFO Status requests. + * @rmtoll CFGR SDMAEN LL_I3C_DisableDMAReq_Status + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableDMAReq_Status(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_SDMAEN); +} + +/** + * @brief Check if DMA FIFO Status requests are enabled or disabled. + * @rmtoll CFGR SDMAEN LL_I3C_IsEnabledDMAReq_Status + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_Status(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_SDMAEN) == (I3C_CFGR_SDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Status FIFO. + * @note Not applicable in target mode. Status FIFO always disabled in target mode. + * @rmtoll CFGR SMODE LL_I3C_EnableStatusFIFO + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableStatusFIFO(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_SMODE); +} + +/** + * @brief Disable the Status FIFO Threshold. + * @rmtoll CFGR SMODE LL_I3C_DisableStatusFIFO + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableStatusFIFO(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_SMODE); +} + +/** + * @brief Check if the Status FIFO Threshold is enabled or disabled. + * @rmtoll CFGR SMODE LL_I3C_IsEnabledStatusFIFO + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStatusFIFO(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_SMODE) == (I3C_CFGR_SMODE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Control and Transmit FIFO preloaded before starting a transfer on I3C bus. + * @note Not applicable in target mode. Control FIFO always disabled in target mode. + * @rmtoll CFGR TMODE LL_I3C_EnableControlFIFO + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableControlFIFO(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_TMODE); +} + +/** + * @brief Disable the Control and Transmit FIFO preloaded before starting a transfer on I3C bus. + * @rmtoll CFGR TMODE LL_I3C_DisableControlFIFO + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableControlFIFO(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_TMODE); +} + +/** + * @brief Check if the Control and Transmit FIFO preloaded is enabled or disabled. + * @rmtoll CFGR TMODE LL_I3C_IsEnabledControlFIFO + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledControlFIFO(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_TMODE) == (I3C_CFGR_TMODE)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA FIFO Control word transfer requests. + * @rmtoll CFGR CDMAEN LL_I3C_EnableDMAReq_Control + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableDMAReq_Control(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_CDMAEN); +} + +/** + * @brief Disable DMA FIFO Control word transfer requests. + * @rmtoll CFGR CDMAEN LL_I3C_DisableDMAReq_Control + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableDMAReq_Control(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_CDMAEN); +} + +/** + * @brief Check if DMA FIFO Control word transfer requests are enabled or disabled. + * @rmtoll CFGR CDMAEN LL_I3C_IsEnabledDMAReq_Control + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_Control(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_CDMAEN) == (I3C_CFGR_CDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Own Dynamic Address as Valid. + * @rmtoll DEVR0 DAVAL LL_I3C_EnableOwnDynAddress + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableOwnDynAddress(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->DEVR0, I3C_DEVR0_DAVAL); +} + +/** + * @brief Set Own Dynamic Address as Not-Valid. + * @rmtoll DEVR0 DAVAL LL_I3C_DisableOwnDynAddress + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableOwnDynAddress(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_DAVAL); +} + +/** + * @brief Check if Own Dynamic address is Valid or Not-Valid. + * @rmtoll DEVR0 DAVAL LL_I3C_IsEnabledOwnDynAddress + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledOwnDynAddress(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_DAVAL) == (I3C_DEVR0_DAVAL)) ? 1UL : 0UL); +} + +/** + * @brief Configure Own Dynamic Address. + * @note This bit can be programmed in controller mode or during Dynamic Address procedure from current controller. + * @rmtoll DEVR0 DA LL_I3C_SetOwnDynamicAddress + * @param I3Cx I3C Instance. + * @param OwnDynamicAddress This parameter must be a value between Min_Data=0 and Max_Data=0x7F + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetOwnDynamicAddress(I3C_TypeDef *I3Cx, uint32_t OwnDynamicAddress) +{ + MODIFY_REG(I3Cx->DEVR0, I3C_DEVR0_DA, (OwnDynamicAddress << I3C_DEVR0_DA_Pos)); +} + +/** + * @brief Get Own Dynamic Address. + * @rmtoll DEVR0 DA LL_I3C_GetOwnDynamicAddress + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0x7F + */ +__STATIC_INLINE uint8_t LL_I3C_GetOwnDynamicAddress(const I3C_TypeDef *I3Cx) +{ + return (uint8_t)(READ_BIT(I3Cx->DEVR0, I3C_DEVR0_DA) >> I3C_DEVR0_DA_Pos); +} + +/** + * @brief Set IBI procedure allowed (when the I3C is acting as target). + * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC. + * @rmtoll DEVR0 IBIEN LL_I3C_EnableIBI + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIBI(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->DEVR0, I3C_DEVR0_IBIEN); +} + +/** + * @brief Set IBI procedure not-allowed (when the I3C is acting as target). + * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC. + * @rmtoll DEVR0 IBIEN LL_I3C_DisableIBI + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIBI(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_IBIEN); +} + +/** + * @brief Check if IBI procedure is allowed or not allowed. + * @rmtoll DEVR0 IBIEN LL_I3C_IsEnabledIBI + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIBI(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_IBIEN) == (I3C_DEVR0_IBIEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Controller-role Request allowed (when the I3C is acting as target). + * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC. + * @rmtoll DEVR0 CREN LL_I3C_EnableControllerRoleReq + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableControllerRoleReq(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->DEVR0, I3C_DEVR0_CREN); +} + +/** + * @brief Set Controller-role Request as not-allowed (when the I3C is acting as target). + * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC. + * @rmtoll DEVR0 CREN LL_I3C_DisableControllerRoleReq + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableControllerRoleReq(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_CREN); +} + +/** + * @brief Check if Controller-role Request is allowed or not-allowed. + * @rmtoll DEVR0 CREN LL_I3C_IsEnabledControllerRoleReq + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledControllerRoleReq(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_CREN) == (I3C_DEVR0_CREN)) ? 1UL : 0UL); +} + +/** + * @brief Set Hot Join allowed (when the I3C is acting as target). + * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC. + * @rmtoll DEVR0 HJEN LL_I3C_EnableHotJoin + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableHotJoin(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->DEVR0, I3C_DEVR0_HJEN); +} + +/** + * @brief Set Hot Join as not-allowed (when the I3C is acting as target). + * @note This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC. + * @rmtoll DEVR0 HJEN LL_I3C_DisableHotJoin + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableHotJoin(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_HJEN); +} + +/** + * @brief Check if Hot Join is allowed or not-allowed. + * @rmtoll DEVR0 HJEN LL_I3C_IsEnabledHotJoin + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledHotJoin(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_HJEN) == (I3C_DEVR0_HJEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure Maximum Read Length (target mode). + * @note Those bits can be updated by HW upon reception of GETMRL CCC. + * @rmtoll MAXRLR MRL LL_I3C_SetMaxReadLength + * @param I3Cx I3C Instance. + * @param MaxReadLength This parameter must be a value between Min_Data=0x0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetMaxReadLength(I3C_TypeDef *I3Cx, uint16_t MaxReadLength) +{ + MODIFY_REG(I3Cx->MAXRLR, I3C_MAXRLR_MRL, MaxReadLength); +} + +/** + * @brief Return Maximum Read Length (target mode). + * @rmtoll MAXRLR MRL LL_I3C_GetMaxReadLength + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFFFFF + */ +__STATIC_INLINE uint32_t LL_I3C_GetMaxReadLength(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->MAXRLR, I3C_MAXRLR_MRL)); +} + +/** + * @brief Configure the number of additional Mandatory Data Byte (MDB) sent to the controller + * after an acknowledge of the IBI (target mode). + * @rmtoll MAXRLR IBIP LL_I3C_ConfigNbIBIAddData + * @param I3Cx I3C Instance. + * @param NbIBIAddData This parameter can be one of the following values: + * @arg @ref LL_I3C_PAYLOAD_EMPTY + * @arg @ref LL_I3C_PAYLOAD_1_BYTE + * @arg @ref LL_I3C_PAYLOAD_2_BYTES + * @arg @ref LL_I3C_PAYLOAD_3_BYTES + * @arg @ref LL_I3C_PAYLOAD_4_BYTES + * @retval None + */ +__STATIC_INLINE void LL_I3C_ConfigNbIBIAddData(I3C_TypeDef *I3Cx, uint32_t NbIBIAddData) +{ + MODIFY_REG(I3Cx->MAXRLR, I3C_MAXRLR_IBIP, NbIBIAddData); +} + +/** + * @brief Return the number of additional Mandatory Data Byte (MDB) sent to the controller + * after an acknowledge of the IBI (target mode). + * @rmtoll MAXRLR IBIP LL_I3C_GetConfigNbIBIAddData + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_PAYLOAD_EMPTY + * @arg @ref LL_I3C_PAYLOAD_1_BYTE + * @arg @ref LL_I3C_PAYLOAD_2_BYTES + * @arg @ref LL_I3C_PAYLOAD_3_BYTES + * @arg @ref LL_I3C_PAYLOAD_4_BYTES + */ +__STATIC_INLINE uint32_t LL_I3C_GetConfigNbIBIAddData(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->MAXRLR, I3C_MAXRLR_IBIP)); +} + +/** + * @brief Configure Maximum Write Length (target mode). + * @note Those bits can be updated by HW upon reception of GETMWL CCC. + * @rmtoll MAXWLR MWL LL_I3C_SetMaxWriteLength + * @param I3Cx I3C Instance. + * @param MaxWriteLength This parameter must be a value between Min_Data=0x0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetMaxWriteLength(I3C_TypeDef *I3Cx, uint16_t MaxWriteLength) +{ + MODIFY_REG(I3Cx->MAXWLR, I3C_MAXWLR_MWL, MaxWriteLength); +} + +/** + * @brief Return Maximum Write Length (target mode). + * @rmtoll MAXWLR MWL LL_I3C_GetMaxWriteLength + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFFFFF + */ +__STATIC_INLINE uint32_t LL_I3C_GetMaxWriteLength(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->MAXWLR, I3C_MAXWLR_MWL)); +} + +/** + * @brief Configure the SCL clock signal waveform. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + * @rmtoll TIMINGR0 TIMINGR0 LL_I3C_ConfigClockWaveForm + * @param I3Cx I3C Instance. + * @param ClockWaveForm This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ConfigClockWaveForm(I3C_TypeDef *I3Cx, uint32_t ClockWaveForm) +{ + WRITE_REG(I3Cx->TIMINGR0, ClockWaveForm); +} + +/** + * @brief Get the SCL clock signal waveform. + * @rmtoll TIMINGR0 TIMINGR0 LL_I3C_GetClockWaveForm + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetClockWaveForm(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_REG(I3Cx->TIMINGR0)); +} + +/** + * @brief Configure the SCL clock low period during I3C push-pull phases. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + * @rmtoll TIMINGR0 SCLL_PP LL_I3C_SetPeriodClockLowPP + * @param I3Cx I3C Instance. + * @param PeriodClockLowPP This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetPeriodClockLowPP(I3C_TypeDef *I3Cx, uint32_t PeriodClockLowPP) +{ + MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_PP, (PeriodClockLowPP << I3C_TIMINGR0_SCLL_PP_Pos)); +} + +/** + * @brief Get the SCL clock low period during I3C push-pull phases. + * @rmtoll TIMINGR0 SCLL_PP LL_I3C_GetPeriodClockLowPP + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetPeriodClockLowPP(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_PP) >> I3C_TIMINGR0_SCLL_PP_Pos); +} + +/** + * @brief Configure the SCL clock High period during I3C open drain and push-pull phases. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + * @rmtoll TIMINGR0 SCLH_I3C LL_I3C_SetPeriodClockHighI3C + * @param I3Cx I3C Instance. + * @param PeriodClockHighI3C This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetPeriodClockHighI3C(I3C_TypeDef *I3Cx, uint32_t PeriodClockHighI3C) +{ + MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I3C, (PeriodClockHighI3C << I3C_TIMINGR0_SCLH_I3C_Pos)); +} + +/** + * @brief Get the SCL clock high period during I3C open drain and push-pull phases. + * @rmtoll TIMINGR0 SCLH_I3C LL_I3C_GetPeriodClockHighI3C + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetPeriodClockHighI3C(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I3C) >> I3C_TIMINGR0_SCLH_I3C_Pos); +} + +/** + * @brief Configure the SCL clock low period during I3C open drain phases. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + * @rmtoll TIMINGR0 SCLL_OD LL_I3C_SetPeriodClockLowOD + * @param I3Cx I3C Instance. + * @param PeriodClockLowOD This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetPeriodClockLowOD(I3C_TypeDef *I3Cx, uint32_t PeriodClockLowOD) +{ + MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_OD, (PeriodClockLowOD << I3C_TIMINGR0_SCLL_OD_Pos)); +} + +/** + * @brief Get the SCL clock low period during I3C open phases. + * @rmtoll TIMINGR0 SCLL_OD LL_I3C_GetPeriodClockLowOD + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetPeriodClockLowOD(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_OD) >> I3C_TIMINGR0_SCLL_OD_Pos); +} + +/** + * @brief Configure the SCL clock High period during I2C open drain phases. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + * @rmtoll TIMINGR0 SCLH_I2C LL_I3C_SetPeriodClockHighI2C + * @param I3Cx I3C Instance. + * @param PeriodClockHighI2C This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetPeriodClockHighI2C(I3C_TypeDef *I3Cx, uint32_t PeriodClockHighI2C) +{ + MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I2C, PeriodClockHighI2C << I3C_TIMINGR0_SCLH_I2C_Pos); +} + +/** + * @brief Get the SCL clock high period during I2C open drain phases. + * @rmtoll TIMINGR0 SCLH_I2C LL_I3C_GetPeriodClockHighI2C + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetPeriodClockHighI2C(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I2C) >> I3C_TIMINGR0_SCLH_I2C_Pos); +} + +/** + * @brief Configure the Controller additional hold time on SDA line. + * @rmtoll TIMINGR1 SDA_HD LL_I3C_SetDataHoldTime + * @param I3Cx I3C Instance. + * @param DataHoldTime This parameter can be one of the following values: + * @arg @ref LL_I3C_SDA_HOLD_TIME_0_5 + * @arg @ref LL_I3C_SDA_HOLD_TIME_1_5 + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetDataHoldTime(I3C_TypeDef *I3Cx, uint32_t DataHoldTime) +{ + MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_SDA_HD, DataHoldTime); +} + +/** + * @brief Get the Controller additional hold time on SDA line. + * @rmtoll TIMINGR1 SDA_HD LL_I3C_GetDataHoldTime + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_SDA_HOLD_TIME_0_5 + * @arg @ref LL_I3C_SDA_HOLD_TIME_1_5 + */ +__STATIC_INLINE uint32_t LL_I3C_GetDataHoldTime(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_SDA_HD)); +} + +/** + * @brief Configure the Idle, Available state. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + * @rmtoll TIMINGR1 AVAL LL_I3C_SetAvalTiming + * @param I3Cx I3C Instance. + * @param AvalTiming This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetAvalTiming(I3C_TypeDef *I3Cx, uint32_t AvalTiming) +{ + MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL, (AvalTiming << I3C_TIMINGR1_AVAL_Pos)); +} + +/** + * @brief Get the Idle, Available integer value state. + * @rmtoll TIMINGR1 AVAL LL_I3C_GetAvalTiming + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetAvalTiming(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL) >> I3C_TIMINGR1_AVAL_Pos); +} + +/** + * @brief Configure the Free state. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + * @rmtoll TIMINGR1 FREE LL_I3C_SetFreeTiming + * @param I3Cx I3C Instance. + * @param FreeTiming This parameter must be a value between Min_Data=0 and Max_Data=0x3F. + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetFreeTiming(I3C_TypeDef *I3Cx, uint32_t FreeTiming) +{ + MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_FREE, (FreeTiming << I3C_TIMINGR1_FREE_Pos)); +} + +/** + * @brief Get the Free integeter value state. + * @rmtoll TIMINGR1 FREE LL_I3C_GetFreeTiming + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0x3F. + */ +__STATIC_INLINE uint32_t LL_I3C_GetFreeTiming(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_FREE) >> I3C_TIMINGR1_FREE_Pos); +} + +/** + * @brief Configure the activity state of the new controller. + * @note Refer to MIPI I3C specification (https:__www.mipi.org_specifications) + * for more details related to Activity State. + * @rmtoll TIMINGR1 ASNCR LL_I3C_SetControllerActivityState + * @param I3Cx I3C Instance. + * @param ControllerActivityState This parameter can be one of the following values: + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_0 + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_1 + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_2 + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_3 + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetControllerActivityState(I3C_TypeDef *I3Cx, uint32_t ControllerActivityState) +{ + MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_ASNCR, ControllerActivityState); +} + +/** + * @brief Get the activity state of the new controller. + * @note Refer to MIPI I3C specification (https:__www.mipi.org_specifications) + * for more details related to Activity State. + * @rmtoll TIMINGR1 ASNCR LL_I3C_GetControllerActivityState + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_0 + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_1 + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_2 + * @arg @ref LL_I3C_OWN_ACTIVITY_STATE_3 + */ +__STATIC_INLINE uint32_t LL_I3C_GetControllerActivityState(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_ASNCR)); +} + +/** + * @brief Configure the Controller SDA Hold time, Bus Free, Activity state, Idle state. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + * @rmtoll TIMINGR1 SDA_HD LL_I3C_SetCtrlBusCharacteristic\n + * TIMINGR1 FREE LL_I3C_SetCtrlBusCharacteristic\n + * TIMINGR1 ASNCR LL_I3C_SetCtrlBusCharacteristic\n + * TIMINGR1 IDLE LL_I3C_SetCtrlBusCharacteristic + * @param I3Cx I3C Instance. + * @param CtrlBusCharacteristic This parameter must be a value between Min_Data=0 and Max_Data=0x107F03FF. + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetCtrlBusCharacteristic(I3C_TypeDef *I3Cx, uint32_t CtrlBusCharacteristic) +{ + WRITE_REG(I3Cx->TIMINGR1, CtrlBusCharacteristic); +} + +/** + * @brief Get the Controller SDA Hold time, Bus Free, Activity state, Idle state. + * @rmtoll TIMINGR1 SDA_HD LL_I3C_GetCtrlBusCharacteristic\n + * TIMINGR1 FREE LL_I3C_GetCtrlBusCharacteristic\n + * TIMINGR1 ASNCR LL_I3C_GetCtrlBusCharacteristic\n + * TIMINGR1 IDLE LL_I3C_GetCtrlBusCharacteristic + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0x107F03FF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetCtrlBusCharacteristic(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_REG(I3Cx->TIMINGR1)); +} + +/** + * @brief Configure the Target Available state. + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + * @rmtoll TIMINGR1 IDLE LL_I3C_SetTgtBusCharacteristic + * @param I3Cx I3C Instance. + * @param TgtBusCharacteristic This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetTgtBusCharacteristic(I3C_TypeDef *I3Cx, uint32_t TgtBusCharacteristic) +{ + MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL, (TgtBusCharacteristic & I3C_TIMINGR1_AVAL)); +} + +/** + * @brief Get the Target Available state. + * @rmtoll TIMINGR1 IDLE LL_I3C_GetTgtBusCharacteristic + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetTgtBusCharacteristic(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL)); +} + +/** + * @brief Configure the SCL clock stalling time on I3C Bus (controller mode). + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note This parameter is computed with the STM32CubeMX Tool. + * @rmtoll TIMINGR2 STALL LL_I3C_SetStallTime + * @param I3Cx I3C Instance. + * @param ControllerStallTime This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetStallTime(I3C_TypeDef *I3Cx, uint32_t ControllerStallTime) +{ + MODIFY_REG(I3Cx->TIMINGR2, I3C_TIMINGR2_STALL, (ControllerStallTime << I3C_TIMINGR2_STALL_Pos)); +} + +/** + * @brief Get the SCL clock stalling time on I3C Bus (controller mode). + * @rmtoll TIMINGR2 STALL LL_I3C_GetStallTime + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetStallTime(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALL)); +} + +/** + * @brief Set stall on ACK bit (controller mode). + * @note This bit can be programmed when the I3C is disabled (EN = 0). + * @rmtoll TIMINGR2 STALLA LL_I3C_EnableStallACK + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableStallACK(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLA); +} + +/** + * @brief Disable stall on ACK bit (controller mode). + * @note This bit can be programmed when the I3C is disabled (EN = 0). + * @rmtoll TIMINGR2 STALLA LL_I3C_DisableStallACK + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableStallACK(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLA); +} + +/** + * @brief Check if stall on ACK bit is enabled or disabled (controller mode). + * @rmtoll TIMINGR2 STALLA LL_I3C_IsEnabledStallACK + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallACK(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLA) == (I3C_TIMINGR2_STALLA)) ? 1UL : 0UL); +} + +/** + * @brief Set stall on Parity bit of Command Code byte (controller mode). + * @note This bit can be programmed when the I3C is disabled (EN = 0). + * @rmtoll TIMINGR2 STALLC LL_I3C_EnableStallParityCCC + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableStallParityCCC(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLC); +} + +/** + * @brief Disable stall on Parity bit of Command Code byte (controller mode). + * @note This bit can be programmed when the I3C is disabled (EN = 0). + * @rmtoll TIMINGR2 STALLC LL_I3C_DisableStallParityCCC + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableStallParityCCC(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLC); +} + +/** + * @brief Check if stall on Parity bit of Command Code byte is enabled or disabled (controller mode). + * @rmtoll TIMINGR2 STALLC LL_I3C_IsEnabledStallParityCCC + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallParityCCC(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLC) == (I3C_TIMINGR2_STALLC)) ? 1UL : 0UL); +} + +/** + * @brief Set stall on Parity bit of Data bytes (controller mode). + * @note This bit can be programmed when the I3C is disabled (EN = 0). + * @rmtoll TIMINGR2 STALLD LL_I3C_EnableStallParityData + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableStallParityData(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLD); +} + +/** + * @brief Disable stall on Parity bit of Data bytes (controller mode). + * @note This bit can be programmed when the I3C is disabled (EN = 0). + * @rmtoll TIMINGR2 STALLD LL_I3C_DisableStallParityData + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableStallParityData(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLD); +} + +/** + * @brief Check if stall on Parity bit of Data bytes is enabled or disabled (controller mode). + * @rmtoll TIMINGR2 STALLD LL_I3C_IsEnabledStallParityData + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallParityData(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLD) == (I3C_TIMINGR2_STALLD)) ? 1UL : 0UL); +} + +/** + * @brief Set stall on T bit (controller mode). + * @note This bit can be programmed when the I3C is disabled (EN = 0). + * @rmtoll TIMINGR2 STALLT LL_I3C_EnableStallTbit + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableStallTbit(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLT); +} + +/** + * @brief Disable stall on T bit (controller mode). + * @note This bit can be programmed when the I3C is disabled (EN = 0). + * @rmtoll TIMINGR2 STALLT LL_I3C_DisableStallTbit + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableStallTbit(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLT); +} + +/** + * @brief Check if stall on T bit is enabled or disabled (controller mode). + * @rmtoll TIMINGR2 STALLT LL_I3C_IsEnabledStallTbit + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallTbit(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLT) == (I3C_TIMINGR2_STALLT)) ? 1UL : 0UL); +} + +/** + * @brief Configure the Device Capability on Bus as Target or Controller (MIPI Bus Characteristics Register BCR6). + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + * @rmtoll BCR BCR6 LL_I3C_SetDeviceCapabilityOnBus + * @param I3Cx I3C Instance. + * @param DeviceCapabilityOnBus This parameter can be one of the following values: + * @arg @ref LL_I3C_DEVICE_ROLE_AS_TARGET + * @arg @ref LL_I3C_DEVICE_ROLE_AS_CONTROLLER + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetDeviceCapabilityOnBus(I3C_TypeDef *I3Cx, uint32_t DeviceCapabilityOnBus) +{ + MODIFY_REG(I3Cx->BCR, I3C_BCR_BCR6, DeviceCapabilityOnBus); +} + +/** + * @brief Get the Device Capability on Bus as Target or Controller (MIPI Bus Characteristics Register BCR6). + * @rmtoll BCR BCR6 LL_I3C_GetDeviceCapabilityOnBus + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_DEVICE_ROLE_AS_TARGET + * @arg @ref LL_I3C_DEVICE_ROLE_AS_CONTROLLER + */ +__STATIC_INLINE uint32_t LL_I3C_GetDeviceCapabilityOnBus(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->BCR, I3C_BCR_BCR6)); +} + +/** + * @brief Configure the Device IBI Payload (MIPI Bus Characteristics Register BCR2). + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + * @rmtoll BCR BCR2 LL_I3C_SetDeviceIBIPayload + * @param I3Cx I3C Instance. + * @param DeviceIBIPayload This parameter can be one of the following values: + * @arg @ref LL_I3C_IBI_NO_ADDITIONAL_DATA + * @arg @ref LL_I3C_IBI_ADDITIONAL_DATA + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetDeviceIBIPayload(I3C_TypeDef *I3Cx, uint32_t DeviceIBIPayload) +{ + MODIFY_REG(I3Cx->BCR, I3C_BCR_BCR2, DeviceIBIPayload); +} + +/** + * @brief Get the Device IBI Payload (MIPI Bus Characteristics Register BCR2). + * @rmtoll BCR BCR2 LL_I3C_GetDeviceIBIPayload + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_IBI_NO_ADDITIONAL_DATA + * @arg @ref LL_I3C_IBI_ADDITIONAL_DATA + */ +__STATIC_INLINE uint32_t LL_I3C_GetDeviceIBIPayload(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->BCR, I3C_BCR_BCR2)); +} + +/** + * @brief Configure the Data Speed Limitation (limitation, as described by I3C_GETMXDSR). + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + * @rmtoll BCR BCR0 LL_I3C_SetDataSpeedLimitation + * @param I3Cx I3C Instance. + * @param DataSpeedLimitation This parameter can be one of the following values: + * @arg @ref LL_I3C_NO_DATA_SPEED_LIMITATION + * @arg @ref LL_I3C_MAX_DATA_SPEED_LIMITATION + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetDataSpeedLimitation(I3C_TypeDef *I3Cx, uint32_t DataSpeedLimitation) +{ + MODIFY_REG(I3Cx->BCR, I3C_BCR_BCR0, DataSpeedLimitation); +} + +/** + * @brief Get the Data Speed Limitation (limitation, as described by I3C_GETMXDSR). + * @rmtoll BCR BCR0 LL_I3C_GetDataSpeedLimitation + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_NO_DATA_SPEED_LIMITATION + * @arg @ref LL_I3C_MAX_DATA_SPEED_LIMITATION + */ +__STATIC_INLINE uint32_t LL_I3C_GetDataSpeedLimitation(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->BCR, I3C_BCR_BCR0)); +} + +/** + * @brief Configure the Device Characteristics Register (DCR). + * @note This bit can only be programmed when the I3C is disabled (EN = 0). + * + * @note Refer MIPI web site for the list of device code available. + * @rmtoll DCR DC LL_I3C_SetDeviceCharacteristics + * @param I3Cx I3C Instance. + * @param DeviceCharacteristics This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetDeviceCharacteristics(I3C_TypeDef *I3Cx, uint32_t DeviceCharacteristics) +{ + MODIFY_REG(I3Cx->DCR, I3C_DCR_DCR, DeviceCharacteristics); +} + +/** + * @brief Get the Device Characteristics Register (DCR). + * @note Refer MIPI web site to associated value with the list of device code available. + * @rmtoll DCR DCR LL_I3C_GetDeviceCharacteristics + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetDeviceCharacteristics(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->DCR, I3C_DCR_DCR)); +} + +/** + * @brief Configure IBI MDB support for pending read notification. + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + * @rmtoll GETCAPR CAPPEND LL_I3C_SetPendingReadMDB + * @param I3Cx I3C Instance. + * @param PendingReadMDB This parameter can be one of the following values: + * @arg @ref LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION + * @arg @ref LL_I3C_MDB_PENDING_READ_NOTIFICATION + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetPendingReadMDB(I3C_TypeDef *I3Cx, uint32_t PendingReadMDB) +{ + MODIFY_REG(I3Cx->GETCAPR, I3C_GETCAPR_CAPPEND, PendingReadMDB); +} + +/** + * @brief Get IBI MDB support for pending read notification value. + * @rmtoll GETCAPR CAPPEND LL_I3C_GetPendingReadMDB + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION + * @arg @ref LL_I3C_MDB_PENDING_READ_NOTIFICATION + */ +__STATIC_INLINE uint32_t LL_I3C_GetPendingReadMDB(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->GETCAPR, I3C_GETCAPR_CAPPEND)); +} + +/** + * @brief Configure the Group Management Support bit of MSTCAP1. + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + * @rmtoll CRCAPR CAPGRP LL_I3C_SetGrpAddrHandoffSupport + * @param I3Cx I3C Instance. + * @param GrpAddrHandoffSupport This parameter can be one of the following values: + * @arg @ref LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED + * @arg @ref LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetGrpAddrHandoffSupport(I3C_TypeDef *I3Cx, uint32_t GrpAddrHandoffSupport) +{ + MODIFY_REG(I3Cx->CRCAPR, I3C_CRCAPR_CAPGRP, GrpAddrHandoffSupport); +} + +/** + * @brief Get the Group Management Support bit of MSTCAP1. + * @rmtoll CRCAPR CAPGRP LL_I3C_GetGrpAddrHandoffSupport + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED + * @arg @ref LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED + */ +__STATIC_INLINE uint32_t LL_I3C_GetGrpAddrHandoffSupport(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->CRCAPR, I3C_CRCAPR_CAPGRP)); +} + +/** + * @brief Configure the Delayed Controller Handoff bit in MSTCAP2. + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + * @rmtoll CRCAPR CAPDHOFF LL_I3C_SetControllerHandoffDelayed + * @param I3Cx I3C Instance. + * @param ControllerHandoffDelayed This parameter can be one of the following values: + * @arg @ref LL_I3C_HANDOFF_NOT_DELAYED + * @arg @ref LL_I3C_HANDOFF_DELAYED + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetControllerHandoffDelayed(I3C_TypeDef *I3Cx, uint32_t ControllerHandoffDelayed) +{ + MODIFY_REG(I3Cx->CRCAPR, I3C_CRCAPR_CAPDHOFF, ControllerHandoffDelayed); +} + +/** + * @brief Get the Delayed Controller Handoff bit in MSTCAP2. + * @rmtoll CRCAPR CAPDHOFF LL_I3C_GetControllerHandoffDelayed + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_HANDOFF_NOT_DELAYED + * @arg @ref LL_I3C_HANDOFF_DELAYED + */ +__STATIC_INLINE uint32_t LL_I3C_GetControllerHandoffDelayed(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->CRCAPR, I3C_CRCAPR_CAPDHOFF)); +} + +/** + * @brief Configure the Activity State after controllership handoff. + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + * @rmtoll GETMXDSR HOFFAS LL_I3C_SetHandoffActivityState + * @param I3Cx I3C Instance. + * @param HandoffActivityState This parameter can be one of the following values: + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_0 + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_1 + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_2 + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_3 + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetHandoffActivityState(I3C_TypeDef *I3Cx, uint32_t HandoffActivityState) +{ + MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_HOFFAS, HandoffActivityState); +} + +/** + * @brief Get the Activity State after controllership handoff. + * @rmtoll GETMXDSR HOFFAS LL_I3C_GetHandoffActivityState + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_0 + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_1 + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_2 + * @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_3 + */ +__STATIC_INLINE uint32_t LL_I3C_GetHandoffActivityState(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_HOFFAS)); +} + +/** + * @brief Configure the Max Data Speed Format response for GETMXDS CCC. + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + * @rmtoll GETMXDSR FMT LL_I3C_SetMaxDataSpeedFormat + * @param I3Cx I3C Instance. + * @param MaxDataSpeedFormat This parameter can be one of the following values: + * @arg @ref LL_I3C_GETMXDS_FORMAT_1 + * @arg @ref LL_I3C_GETMXDS_FORMAT_2_LSB + * @arg @ref LL_I3C_GETMXDS_FORMAT_2_MID + * @arg @ref LL_I3C_GETMXDS_FORMAT_2_MSB + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetMaxDataSpeedFormat(I3C_TypeDef *I3Cx, uint32_t MaxDataSpeedFormat) +{ + MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_FMT, MaxDataSpeedFormat); +} + +/** + * @brief Get the Max Data Speed Format response for GETMXDS CCC. + * @rmtoll GETMXDSR FMT LL_I3C_GetMaxDataSpeedFormat + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_GETMXDS_FORMAT_1 + * @arg @ref LL_I3C_GETMXDS_FORMAT_2_LSB + * @arg @ref LL_I3C_GETMXDS_FORMAT_2_MID + * @arg @ref LL_I3C_GETMXDS_FORMAT_2_MSB + */ +__STATIC_INLINE uint32_t LL_I3C_GetMaxDataSpeedFormat(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_FMT)); +} + +/** + * @brief Configure the Middle byte of MaxRdTurn field of GETMXDS CCC Format 2 with turnaround. + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + * @rmtoll GETMXDSR RDTURN LL_I3C_SetMiddleByteTurnAround + * @param I3Cx I3C Instance. + * @param MiddleByteTurnAround This parameter must be a value between Min_Data=0 and Max_Data=0xF. + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetMiddleByteTurnAround(I3C_TypeDef *I3Cx, uint32_t MiddleByteTurnAround) +{ + MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_RDTURN, (MiddleByteTurnAround << I3C_GETMXDSR_RDTURN_Pos)); +} + +/** + * @brief Get the value of Middle byte of MaxRdTurn field of GETMXDS CCC Format 2 with turnaround. + * @rmtoll GETMXDSR RDTURN LL_I3C_GetMiddleByteTurnAround + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetMiddleByteTurnAround(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_RDTURN)); +} + +/** + * @brief Configure clock-to-data turnaround time. + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + * @rmtoll GETMXDSR TSCO LL_I3C_SetDataTurnAroundTime + * @param I3Cx I3C Instance. + * @param DataTurnAroundTime This parameter can be one of the following values: + * @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS + * @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetDataTurnAroundTime(I3C_TypeDef *I3Cx, uint32_t DataTurnAroundTime) +{ + MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_TSCO, DataTurnAroundTime); +} + +/** + * @brief Get clock-to-data turnaround time. + * @rmtoll GETMXDSR TSCO LL_I3C_GetDataTurnAroundTime + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS + * @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS + */ +__STATIC_INLINE uint32_t LL_I3C_GetDataTurnAroundTime(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_TSCO)); +} + +/** + * @brief Configure the MIPI Instance ID. + * @note Those bits can be programmed when the I3C is disabled (EN = 0). + * @rmtoll EPIDR MIPIID LL_I3C_SetMIPIInstanceID + * @param I3Cx I3C Instance. + * @param MIPIInstanceID This parameter must be a value between Min_Data=0 and Max_Data=0xF. + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetMIPIInstanceID(I3C_TypeDef *I3Cx, uint32_t MIPIInstanceID) +{ + MODIFY_REG(I3Cx->EPIDR, I3C_EPIDR_MIPIID, (MIPIInstanceID << I3C_EPIDR_MIPIID_Pos)); +} + +/** + * @brief Get the MIPI Instance ID. + * @rmtoll EPIDR MIPIID LL_I3C_GetMIPIInstanceID + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetMIPIInstanceID(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->EPIDR, I3C_EPIDR_MIPIID) >> I3C_EPIDR_MIPIID_Pos); +} + +/** + * @brief Get the ID type selector. + * @rmtoll EPIDR IDTSEL LL_I3C_GetIDTypeSelector + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0x1 + */ +__STATIC_INLINE uint32_t LL_I3C_GetIDTypeSelector(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->EPIDR, I3C_EPIDR_IDTSEL) >> I3C_EPIDR_IDTSEL_Pos); +} + +/** + * @brief Get the MIPI Manufacturer ID. + * @rmtoll EPIDR MIPIMID LL_I3C_GetMIPIManufacturerID + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 and Max_Data=0x7FFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetMIPIManufacturerID(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->EPIDR, I3C_EPIDR_MIPIMID) >> I3C_EPIDR_MIPIMID_Pos); +} + +/** + * @} + */ + +/** @defgroup I3C_LL_EF_Data Management + * @{ + */ + +/** + * @brief Request a reception Data FIFO Flush. + * @rmtoll CFGR RXFLUSH LL_I3C_RequestRxFIFOFlush + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_RequestRxFIFOFlush(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_RXFLUSH); +} + +/** + * @brief Request a transmission Data FIFO Flush. + * @rmtoll CFGR TXFLUSH LL_I3C_RequestTxFIFOFlush + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_RequestTxFIFOFlush(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_TXFLUSH); +} + +/** + * @brief Request a Status Data FIFO Flush. + * @rmtoll CFGR SFLUSH LL_I3C_RequestStatusFIFOFlush + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_RequestStatusFIFOFlush(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_SFLUSH); +} + +/** + * @brief Get Activity state of Controller on the I3C Bus (Target only). + * @rmtoll DEVR0 AS LL_I3C_GetActivityState + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_BUS_ACTIVITY_STATE_0 + * @arg @ref LL_I3C_BUS_ACTIVITY_STATE_1 + * @arg @ref LL_I3C_BUS_ACTIVITY_STATE_2 + * @arg @ref LL_I3C_BUS_ACTIVITY_STATE_3 + */ +__STATIC_INLINE uint32_t LL_I3C_GetActivityState(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->DEVR0, I3C_DEVR0_AS)); +} + +/** + * @brief Get Reset Action (Target only). + * @rmtoll DEVR0 RSTACT LL_I3C_GetResetAction + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_RESET_ACTION_NONE + * @arg @ref LL_I3C_RESET_ACTION_PARTIAL + * @arg @ref LL_I3C_RESET_ACTION_FULL + */ +__STATIC_INLINE uint32_t LL_I3C_GetResetAction(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->DEVR0, I3C_DEVR0_RSTACT)); +} + +/** + * @brief Request a Control word FIFO Flush. + * @rmtoll CFGR CFLUSH LL_I3C_RequestControlFIFOFlush + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_RequestControlFIFOFlush(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_CFLUSH); +} + +/** + * @brief Request a Transfer start. + * @note After request, the current instruction in Control Register is executed on I3C Bus. + * @rmtoll CFGR TSFSET LL_I3C_RequestTransfer + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_RequestTransfer(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->CFGR, I3C_CFGR_TSFSET); +} + +/** + * @brief Handles I3C Message content on the I3C Bus as Controller. + * @rmtoll CR ADD LL_I3C_ControllerHandleMessage\n + * CR DCNT LL_I3C_ControllerHandleMessage\n + * CR RNW LL_I3C_ControllerHandleMessage\n + * CR MTYPE LL_I3C_ControllerHandleMessage\n + * CR MEND LL_I3C_ControllerHandleMessage + * @param I3Cx I3C Instance. + * @param TargetAddr Specifies the target address to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @param TransferSize Specifies the number of bytes to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=65535. + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_I3C_DIRECTION_WRITE + * @arg @ref LL_I3C_DIRECTION_READ + * @param MessageType This parameter can be one of the following values: + * @arg @ref LL_I3C_CONTROLLER_MTYPE_RELEASE + * @arg @ref LL_I3C_CONTROLLER_MTYPE_HEADER + * @arg @ref LL_I3C_CONTROLLER_MTYPE_PRIVATE + * @arg @ref LL_I3C_CONTROLLER_MTYPE_DIRECT + * @arg @ref LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C + * @param EndMode This parameter can be one of the following values: + * @arg @ref LL_I3C_GENERATE_STOP + * @arg @ref LL_I3C_GENERATE_RESTART + * @retval None + */ +__STATIC_INLINE void LL_I3C_ControllerHandleMessage(I3C_TypeDef *I3Cx, uint32_t TargetAddr, uint32_t TransferSize, + uint32_t Direction, uint32_t MessageType, uint32_t EndMode) +{ + WRITE_REG(I3Cx->CR, ((TargetAddr << I3C_CR_ADD_Pos) | TransferSize | Direction | MessageType | EndMode) \ + & (I3C_CR_ADD | I3C_CR_DCNT | I3C_CR_RNW | I3C_CR_MTYPE | I3C_CR_MEND)); +} + +/** + * @brief Handles I3C Common Command Code content on the I3C Bus as Controller. + * @rmtoll CR CCC LL_I3C_ControllerHandleCCC\n + * CR DCNT LL_I3C_ControllerHandleCCC\n + * CR MTYPE LL_I3C_ControllerHandleCCC\n + * CR MEND LL_I3C_ControllerHandleCCC + * @param I3Cx I3C Instance. + * @param CCCValue Specifies the Command Code to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=0x1FF. + * @param AddByteSize Specifies the number of CCC additional bytes to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=65535. + * @param EndMode This parameter can be one of the following values: + * @arg @ref LL_I3C_GENERATE_STOP + * @arg @ref LL_I3C_GENERATE_RESTART + * @retval None + */ +__STATIC_INLINE void LL_I3C_ControllerHandleCCC(I3C_TypeDef *I3Cx, uint32_t CCCValue, + uint32_t AddByteSize, uint32_t EndMode) +{ + WRITE_REG(I3Cx->CR, ((CCCValue << I3C_CR_CCC_Pos) | AddByteSize | EndMode | LL_I3C_CONTROLLER_MTYPE_CCC) \ + & (I3C_CR_CCC | I3C_CR_DCNT | I3C_CR_MTYPE | I3C_CR_MEND)); +} + +/** + * @brief Handles I3C Message content on the I3C Bus as Target. + * @rmtoll CR MTYPE LL_I3C_TargetHandleMessage\n + * CR DCNT LL_I3C_TargetHandleMessage + * @param I3Cx I3C Instance. + * @param MessageType This parameter can be one of the following values: + * @arg @ref LL_I3C_TARGET_MTYPE_HOT_JOIN + * @arg @ref LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ + * @arg @ref LL_I3C_TARGET_MTYPE_IBI + * @param IBISize Specifies the number of IBI bytes. + * This parameter must be a value between Min_Data=0 and Max_Data=65535. + * @retval None + */ +__STATIC_INLINE void LL_I3C_TargetHandleMessage(I3C_TypeDef *I3Cx, uint32_t MessageType, uint32_t IBISize) +{ + WRITE_REG(I3Cx->CR, (MessageType | IBISize) & (I3C_CR_DCNT | I3C_CR_MTYPE)); +} + +/** + * @} + */ + +/** @defgroup I3C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receive Data Byte register. + * @rmtoll RDR RDB0 LL_I3C_ReceiveData8 + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 to Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_I3C_ReceiveData8(const I3C_TypeDef *I3Cx) +{ + return (uint8_t)(READ_BIT(I3Cx->RDR, I3C_RDR_RDB0)); +} + +/** + * @brief Write in Transmit Data Byte Register. + * @rmtoll TDR TDB0 LL_I3C_TransmitData8 + * @param I3Cx I3C Instance. + * @param Data This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I3C_TransmitData8(I3C_TypeDef *I3Cx, uint8_t Data) +{ + WRITE_REG(I3Cx->TDR, Data); +} + +/** + * @brief Read Receive Data Word register. + * @note Content of register is filled in Little Endian. + * Mean MSB correspond to last data byte received, + * LSB correspond to first data byte received. + * @rmtoll RDWR RDWR LL_I3C_ReceiveData32 + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 to Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_I3C_ReceiveData32(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_REG(I3Cx->RDWR)); +} + +/** + * @brief Write in Transmit Data Word Register. + * @note Content of register is filled in Little Endian. + * Mean MSB correspond to last data byte transmitted, + * LSB correspond to first data byte transmitted. + * @rmtoll TDWR TDWR LL_I3C_TransmitData32 + * @param I3Cx I3C Instance. + * @param Data This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. + * @retval None + */ +__STATIC_INLINE void LL_I3C_TransmitData32(I3C_TypeDef *I3Cx, uint32_t Data) +{ + WRITE_REG(I3Cx->TDWR, Data); +} + +/** + * @brief Configure the IBI data payload to be sent during IBI (target mode). + * @note Content of register is filled in Little Endian. + * Mean MSB correspond to last IBI data byte, + * LSB correspond to first IBI data byte. + * @rmtoll IBIDR IBIDR LL_I3C_SetIBIPayload + * @param I3Cx I3C Instance. + * @param OwnIBIPayload This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetIBIPayload(I3C_TypeDef *I3Cx, uint32_t OwnIBIPayload) +{ + WRITE_REG(I3Cx->IBIDR, OwnIBIPayload); +} + +/** + * @brief Get the own IBI data payload (target mode), or get the Target IBI received (controller mode). + * @note Content of register is filled in Little Endian. + * Mean MSB correspond to last IBI data byte, + * LSB correspond to first IBI data byte. + * @rmtoll IBIDR IBIDR LL_I3C_GetIBIPayload + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 to Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_I3C_GetIBIPayload(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_REG(I3Cx->IBIDR)); +} + +/** + * @brief Get the number of data bytes received when reading IBI data (controller mode). + * @rmtoll RMR IBIRDCNT LL_I3C_GetNbIBIAddData + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 to Max_Data=0x7 + */ +__STATIC_INLINE uint32_t LL_I3C_GetNbIBIAddData(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->RMR, I3C_RMR_IBIRDCNT)); +} + +/** + * @brief Get the target address received during accepted IBI or Controller-role request. + * @rmtoll RMR RADD LL_I3C_GetIBITargetAddr + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 to Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I3C_GetIBITargetAddr(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->RMR, I3C_RMR_RADD) >> I3C_RMR_RADD_Pos); +} + +/** + * @brief Set TX FIFO Preload (target mode). + * @note Set high by Software, cleared by hardware when all the bytes to transmit have been loaded to TX FIFO. + * @rmtoll TGTTDR PRELOAD LL_I3C_ConfigTxPreload + * @rmtoll TGTTDR TDCNT LL_I3C_ConfigTxPreload + * @param I3Cx I3C Instance. + * @param TxDataCount This parameter must be a value between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_I3C_ConfigTxPreload(I3C_TypeDef *I3Cx, uint16_t TxDataCount) +{ + MODIFY_REG(I3Cx->TGTTDR, (I3C_TGTTDR_PRELOAD | I3C_TGTTDR_TGTTDCNT), (I3C_TGTTDR_PRELOAD | TxDataCount)); +} + +/** + * @brief Indicates the status of TX FIFO preload (target mode). + * RESET: No preload of TX FIFO. + * SET: Preload of TX FIFO ongoing. + * @note Set high by Software, cleared by hardware when all the bytes to transmit have been loaded to TX FIFO. + * @rmtoll TGTTDR PRELOAD LL_I3C_IsActiveTxPreload + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveTxPreload(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->TGTTDR, I3C_TGTTDR_PRELOAD) == (I3C_TGTTDR_PRELOAD)) ? 1UL : 0UL); +} + +/** + * @brief Get the number of bytes to transmit (target mode). + * @note The return value correspond to the remaining number of bytes to load in TX FIFO. + * @rmtoll TGTTDR TDCNT LL_I3C_GetTxPreloadDataCount + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 to Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_I3C_GetTxPreloadDataCount(const I3C_TypeDef *I3Cx) +{ + return (uint16_t)(READ_BIT(I3Cx->TGTTDR, I3C_TGTTDR_TGTTDCNT)); +} + +/** + * @brief Get the number of data during a Transfer. + * @note The return value correspond to number of transmitted bytes reported + * during Address Assignment process in Target mode. + * The return value correspond to number of target detected + * during Address Assignment process in Controller mode. + * The return value correspond to number of data bytes read from or sent to the I3C bus + * during the message link to MID current value. + * @rmtoll SR XDCNT LL_I3C_GetXferDataCount + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 to Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_I3C_GetXferDataCount(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->SR, I3C_SR_XDCNT)); +} + +/** + * @brief Indicates if a Target abort a private read command. + * @rmtoll SR ABT LL_I3C_IsTargetAbortPrivateRead + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsTargetAbortPrivateRead(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->SR, I3C_SR_ABT) == (I3C_SR_ABT)) ? 1UL : 0UL); +} + +/** + * @brief Get Direction of the Message. + * @rmtoll SR DIR LL_I3C_GetMessageDirection + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_MESSAGE_DIRECTION_WRITE + * @arg @ref LL_I3C_MESSAGE_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_I3C_GetMessageDirection(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->SR, I3C_SR_DIR)); +} + +/** + * @brief Get Message identifier. + * @rmtoll SR MID LL_I3C_GetMessageIdentifier + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 to Max_Data=0xFF, representing the internal hardware counter value. + */ +__STATIC_INLINE uint32_t LL_I3C_GetMessageIdentifier(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->SR, I3C_SR_MID)); +} + +/** + * @brief Get Message error code. + * @rmtoll SER CODERR LL_I3C_GetMessageErrorCode + * @param I3Cx I3C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I3C_CONTROLLER_ERROR_CE0 + * @arg @ref LL_I3C_CONTROLLER_ERROR_CE1 + * @arg @ref LL_I3C_CONTROLLER_ERROR_CE2 + * @arg @ref LL_I3C_CONTROLLER_ERROR_CE3 + * @arg @ref LL_I3C_TARGET_ERROR_TE0 + * @arg @ref LL_I3C_TARGET_ERROR_TE1 + * @arg @ref LL_I3C_TARGET_ERROR_TE2 + * @arg @ref LL_I3C_TARGET_ERROR_TE3 + * @arg @ref LL_I3C_TARGET_ERROR_TE4 + * @arg @ref LL_I3C_TARGET_ERROR_TE5 + * @arg @ref LL_I3C_TARGET_ERROR_TE6 + */ +__STATIC_INLINE uint32_t LL_I3C_GetMessageErrorCode(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->SER, I3C_SER_CODERR)); +} + +/** + * @brief Get CCC code of received command. + * @rmtoll RMR RCODE LL_I3C_GetReceiveCommandCode + * @param I3Cx I3C Instance. + * @retval Value between Min_Data=0 to Max_Data=0xFF. + */ +__STATIC_INLINE uint32_t LL_I3C_GetReceiveCommandCode(const I3C_TypeDef *I3Cx) +{ + return (uint32_t)(READ_BIT(I3Cx->RMR, I3C_RMR_RCODE) >> I3C_RMR_RCODE_Pos); +} + +/** + * @} + */ + +/** @defgroup I3C_LL_EF_Target Payload + * @{ + */ + +/** + * @brief Set Dynamic Address assigned to target x. + * @rmtoll DEVRX DA LL_I3C_SetTargetDynamicAddress + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @param DynamicAddr Value between Min_Data=0 to Max_Data=0x7F + * @retval None + */ +__STATIC_INLINE void LL_I3C_SetTargetDynamicAddress(I3C_TypeDef *I3Cx, uint32_t TargetId, uint32_t DynamicAddr) +{ + MODIFY_REG(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_DA, (DynamicAddr << I3C_DEVRX_DA_Pos)); +} + +/** + * @brief Get Dynamic Address assigned to target x. + * @rmtoll DEVRX DA LL_I3C_GetTargetDynamicAddress + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval Value between Min_Data=0 to Max_Data=0x7F + */ +__STATIC_INLINE uint32_t LL_I3C_GetTargetDynamicAddress(const I3C_TypeDef *I3Cx, uint32_t TargetId) +{ + return (uint32_t)((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_DA)) >> I3C_DEVRX_DA_Pos); +} + +/** + * @brief Enable IBI Acknowledgement from target x(controller mode). + * @note The bit DIS is automatically set when CRACK or IBIACK are set. + * This mean DEVRX register access is not allowed. + * Reset CRACK and IBIACK will reset DIS bit. + * @rmtoll DEVRX IBIACK LL_I3C_EnableTargetIBIAck + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableTargetIBIAck(I3C_TypeDef *I3Cx, uint32_t TargetId) +{ + SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIACK); +} + +/** + * @brief Disable IBI Acknowledgement from target x (controller mode). + * @rmtoll DEVRX IBIACK LL_I3C_DisableTargetIBIAck + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableTargetIBIAck(I3C_TypeDef *I3Cx, uint32_t TargetId) +{ + CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIACK); +} + +/** + * @brief Indicates if IBI from target x will be Acknowledged or Not Acknowledged (controller mode). + * RESET: IBI Not Acknowledged. + * SET: IBI Acknowledged. + * @rmtoll DEVRX IBIACK LL_I3C_IsEnabledTargetIBIAck + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledTargetIBIAck(const I3C_TypeDef *I3Cx, uint32_t TargetId) +{ + return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIACK) == I3C_DEVRX_IBIACK) ? 1UL : 0UL); +} + +/** + * @brief Enable Controller-role Request Acknowledgement from target x(controller mode). + * @note The bit DIS is automatically set when CRACK or IBIACK are set. + * This mean DEVRX register access is not allowed. + * Reset CRACK and IBIACK will reset DIS bit. + * @rmtoll DEVRX CRACK LL_I3C_EnableTargetCRAck + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableTargetCRAck(I3C_TypeDef *I3Cx, uint32_t TargetId) +{ + SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_CRACK); +} + +/** + * @brief Disable Controller-role Request Acknowledgement from target x (controller mode). + * @rmtoll DEVRX CRACK LL_I3C_DisableTargetCRAck + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableTargetCRAck(I3C_TypeDef *I3Cx, uint32_t TargetId) +{ + CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_CRACK); +} + +/** + * @brief Indicates if Controller-role Request from target x will be + * Acknowledged or Not Acknowledged (controller mode). + * RESET: Controller-role Request Not Acknowledged. + * SET: Controller-role Request Acknowledged. + * @rmtoll DEVRX CRACK LL_I3C_IsEnabledTargetCRAck + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledTargetCRAck(const I3C_TypeDef *I3Cx, uint32_t TargetId) +{ + return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_CRACK) == I3C_DEVRX_CRACK) ? 1UL : 0UL); +} + +/** + * @brief Enable additional Mandatory Data Byte (MDB) follows the accepted IBI from target x. + * @rmtoll DEVRX IBIDEN LL_I3C_EnableIBIAddData + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIBIAddData(I3C_TypeDef *I3Cx, uint32_t TargetId) +{ + SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIDEN); +} + +/** + * @brief Disable additional Mandatory Data Byte (MDB) follows the accepted IBI from target x. + * @rmtoll DEVRX IBIDEN LL_I3C_DisableIBIAddData + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIBIAddData(I3C_TypeDef *I3Cx, uint32_t TargetId) +{ + CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIDEN); +} + +/** + * @brief Indicates if additional Mandatory Data Byte (MDB) follows the accepted IBI from target x. + * RESET: No Mandatory Data Byte follows IBI. + * SET: Mandatory Data Byte follows IBI. + * @rmtoll DEVRX IBIDEN LL_I3C_IsEnabledIBIAddData + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIBIAddData(const I3C_TypeDef *I3Cx, uint32_t TargetId) +{ + return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIDEN) == I3C_DEVRX_IBIDEN) ? 1UL : 0UL); +} + +/** + * @brief Enable Suspension of Current transfer during IBI treatment. + * @note When set, this feature will allow controller to send + * a Stop condition and CR FIFO is flushed after IBI treatment. + * Software has to rewrite instructions in Control Register to start a new transfer. + * @rmtoll DEVRX SUSP LL_I3C_EnableFrameSuspend + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableFrameSuspend(I3C_TypeDef *I3Cx, uint32_t TargetId) +{ + SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_SUSP); +} + +/** + * @brief Disable Suspension of Current transfer during IBI treatment. + * @note When set, this feature will allow controller to continue CR FIFO treatment after IBI treatment. + * @rmtoll DEVRX SUSP LL_I3C_DisableFrameSuspend + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableFrameSuspend(I3C_TypeDef *I3Cx, uint32_t TargetId) +{ + CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_SUSP); +} + +/** + * @brief Indicates if I3C transfer must be Suspended or not Suspended during IBI treatment from target x. + * RESET: Transfer is not suspended. Instruction in CR FIFO are executed after IBI. + * SET: Transfer is suspended (a Stop condition is sent). CR FIFO is flushed. + * @rmtoll DEVRX SUSP LL_I3C_IsFrameMustBeSuspended + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsFrameMustBeSuspended(const I3C_TypeDef *I3Cx, uint32_t TargetId) +{ + return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_SUSP) == I3C_DEVRX_SUSP) ? 1UL : 0UL); +} + +/** + * @brief Indicates if update of the Device Characteristics Register is Allowed or Not Allowed. + * RESET: Device Characteristics Register update is Not Allowed. + * SET: Device Characteristics Register update is Allowed. + * @note Used to prevent software writing during reception of an IBI or Controller-role Request from target x. + * @rmtoll DEVRX DIS LL_I3C_IsAllowedPayloadUpdate + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsAllowedPayloadUpdate(const I3C_TypeDef *I3Cx, uint32_t TargetId) +{ + return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_DIS) != I3C_DEVRX_DIS) ? 1UL : 0UL); +} + +/** + * @brief Set I3C bus devices configuration. + * @note This function is called only when the I3C instance is initialized as controller. + * This function can be called by the controller application to help the automatic treatment when target have + * capability of IBI and/or Control-Role. + * @rmtoll DEVRX DA LL_I3C_ConfigDeviceCapabilities + * @rmtoll DEVRX IBIACK LL_I3C_ConfigDeviceCapabilities + * @rmtoll DEVRX IBIDEN LL_I3C_ConfigDeviceCapabilities + * @rmtoll DEVRX CRACK LL_I3C_ConfigDeviceCapabilities + * @param I3Cx I3C Instance. + * @param TargetId This parameter must be a value between Min_Data=1 and Max_Data=4 + * @param DynamicAddr Value between Min_Data=0 to Max_Data=0x7F + * @param IBIAck Value This parameter can be one of the following values: + * @arg @ref LL_I3C_IBI_CAPABILITY + * @arg @ref LL_I3C_IBI_NO_CAPABILITY + * @param IBIAddData This parameter can be one of the following values: + * @arg @ref LL_I3C_IBI_DATA_ENABLE + * @arg @ref LL_I3C_IBI_DATA_DISABLE + * @param CRAck This parameter can be one of the following values: + * @arg @ref LL_I3C_CR_CAPABILITY + * @arg @ref LL_I3C_CR_NO_CAPABILITY + * @retval None + */ +__STATIC_INLINE void LL_I3C_ConfigDeviceCapabilities(I3C_TypeDef *I3Cx, + uint32_t TargetId, + uint32_t DynamicAddr, + uint32_t IBIAck, + uint32_t IBIAddData, + uint32_t CRAck) +{ + MODIFY_REG(I3Cx->DEVRX[TargetId - 1U], \ + (I3C_DEVRX_DA | I3C_DEVRX_IBIACK | I3C_DEVRX_CRACK | I3C_DEVRX_IBIDEN), \ + ((DynamicAddr << I3C_DEVRX_DA_Pos) | IBIAck | IBIAddData | CRAck)); +} +/** + * @} + */ + +/** @defgroup I3C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Indicates the status of Control FIFO Empty flag. + * RESET: One or more data are available in Control FIFO. + * SET: No more data available in Control FIFO. + * @rmtoll EVR CFEF LL_I3C_IsActiveFlag_CFE + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CFE(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_CFEF) == (I3C_EVR_CFEF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Transmit FIFO Empty flag. + * RESET: One or more data are available in Transmit FIFO. + * SET: No more data available in Transmit FIFO. + * @rmtoll EVR TXFEF LL_I3C_IsActiveFlag_TXFE + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_TXFE(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_TXFEF) == (I3C_EVR_TXFEF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Control FIFO Not Full flag. + * RESET: One or more free space available in Control FIFO. + * SET: No more free space available in Control FIFO. + * @note When a transfer is ongoing, the Control FIFO shall not be written unless this flag is set. + * @rmtoll EVR CFNFF LL_I3C_IsActiveFlag_CFNF + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CFNF(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_CFNFF) == (I3C_EVR_CFNFF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Status FIFO Not Empty flag. + * RESET: One or more free space available in Status FIFO. + * SET: No more free space available in Status FIFO. + * @note This flag is updated only when the FIFO is used, mean SMODE = 1. + * @rmtoll EVR SFNEF LL_I3C_IsActiveFlag_SFNE + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_SFNE(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_SFNEF) == (I3C_EVR_SFNEF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Transmit FIFO Not Full flag. + * RESET: One or more free space available in Transmit FIFO. + * SET: No more free space available in Transmit FIFO. + * @note When a transfer is ongoing, the Transmit FIFO shall not be written unless this flag is set. + * @rmtoll EVR TXFNFF LL_I3C_IsActiveFlag_TXFNF + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_TXFNF(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_TXFNFF) == (I3C_EVR_TXFNFF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Receive FIFO Not Full flag. + * RESET: One or more data are available in Receive FIFO. + * SET: No more data available in Receive FIFO. + * @rmtoll EVR RXFNEF LL_I3C_IsActiveFlag_RXFNE + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RXFNE(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_RXFNEF) == (I3C_EVR_RXFNEF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates that the last Receive byte is available. + * RESET: Clear default value. + * SET: Last Receive byte ready to read from Receive FIFO. + * @rmtoll EVR RXLASTF LL_I3C_IsActiveFlag_RXLAST + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RXLAST(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_RXLASTF) == (I3C_EVR_RXLASTF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates that the last Transmit byte is written in FIFO. + * RESET: Transmission is not finalized. + * SET: Last Transmit byte is written in transmit FIFO. + * @rmtoll EVR TXLASTF LL_I3C_IsActiveFlag_TXLAST + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_TXLAST(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_TXLASTF) == (I3C_EVR_TXLASTF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Frame Complete flag (controller and target mode). + * RESET: Current Frame transfer is not finalized. + * SET: Current Frame transfer is completed. + * @rmtoll EVR FCF LL_I3C_IsActiveFlag_FC + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_FC(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_FCF) == (I3C_EVR_FCF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Reception Target End flag (controller mode). + * RESET: Clear default value. + * SET: Target prematurely ended a Read Command. + * @note This flag is set only when status FIFO is not used, mean SMODE = 0. + * @rmtoll EVR RXTGTENDF LL_I3C_IsActiveFlag_RXTGTEND + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RXTGTEND(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_RXTGTENDF) == (I3C_EVR_RXTGTENDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Error flag (controller and target mode). + * RESET: Clear default value. + * SET: One or more Errors are detected. + * @rmtoll EVR ERRF LL_I3C_IsActiveFlag_ERR + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_ERR(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_ERRF) == (I3C_EVR_ERRF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of IBI flag (controller mode). + * RESET: Clear default value. + * SET: An IBI have been received. + * @rmtoll EVR IBIF LL_I3C_IsActiveFlag_IBI + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_IBI(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_IBIF) == (I3C_EVR_IBIF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of IBI End flag (target mode). + * RESET: Clear default value. + * SET: IBI procedure is finished. + * @rmtoll EVR IBIENDF LL_I3C_IsActiveFlag_IBIEND + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_IBIEND(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_IBIENDF) == (I3C_EVR_IBIENDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Controller-role Request flag (controller mode). + * RESET: Clear default value. + * SET: A Controller-role request procedure have been received. + * @rmtoll EVR CRF LL_I3C_IsActiveFlag_CR + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CR(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_CRF) == (I3C_EVR_CRF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Controller-role Request Update flag (target mode). + * RESET: Clear default value. + * SET: I3C device have gained Controller-role of the I3C Bus. + * @rmtoll EVR BCUPDF LL_I3C_IsActiveFlag_CRUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CRUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_CRUPDF) == (I3C_EVR_CRUPDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Hot Join flag (controller mode). + * RESET: Clear default value. + * SET: A Hot Join request have been received. + * @rmtoll EVR HJF LL_I3C_IsActiveFlag_HJ + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_HJ(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_HJF) == (I3C_EVR_HJF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Wake Up flag (target mode). + * RESET: Clear default value. + * SET: I3C Internal clock not available on time to treat the falling edge on SCL. + * @rmtoll EVR WKPF LL_I3C_IsActiveFlag_WKP + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_WKP(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_WKPF) == (I3C_EVR_WKPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Get flag (target mode). + * RESET: Clear default value. + * SET: A "get" type CCC have been received. + * @rmtoll EVR GETF LL_I3C_IsActiveFlag_GET + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_GET(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_GETF) == (I3C_EVR_GETF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Get Status flag (target mode). + * RESET: Clear default value. + * SET: A GETSTATUS Command have been received. + * @rmtoll EVR STAF LL_I3C_IsActiveFlag_STA + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_STA(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_STAF) == (I3C_EVR_STAF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Dynamic Address Update flag (target mode). + * RESET: Clear default value. + * SET: Own Dynamic Address have been updated. + * @rmtoll EVR DAUPDF LL_I3C_IsActiveFlag_DAUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DAUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_DAUPDF) == (I3C_EVR_DAUPDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Max Write Length flag (target mode). + * RESET: Clear default value. + * SET: Max Write Length have been updated. + * @rmtoll EVR MWLUPDF LL_I3C_IsActiveFlag_MWLUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_MWLUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_MWLUPDF) == (I3C_EVR_MWLUPDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Max Read Length flag (target mode). + * RESET: Clear default value. + * SET: Max Read Length have been updated. + * @rmtoll EVR MRLUPDF LL_I3C_IsActiveFlag_MRLUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_MRLUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_MRLUPDF) == (I3C_EVR_MRLUPDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Reset flag (target mode). + * RESET: Clear default value. + * SET: A Reset Pattern have been received. + * @rmtoll EVR RSTF LL_I3C_IsActiveFlag_RST + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RST(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_RSTF) == (I3C_EVR_RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Active State flag (target mode). + * RESET: Clear default value. + * SET: The Activity State have been updated. + * @rmtoll EVR ASUPDF LL_I3C_IsActiveFlag_ASUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_ASUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_ASUPDF) == (I3C_EVR_ASUPDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Interrupt Update flag (target mode). + * RESET: Clear default value. + * SET: One or more Interrupt autorized have been updated. + * @rmtoll EVR INTUPDF LL_I3C_IsActiveFlag_INTUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_INTUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_INTUPDF) == (I3C_EVR_INTUPDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Define List Targets flag (target mode). + * RESET: Clear default value. + * SET: A Define List Targets Command have been received. + * @rmtoll EVR DEFF LL_I3C_IsActiveFlag_DEF + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DEF(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_DEFF) == (I3C_EVR_DEFF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Define List Group Addresses flag. + * RESET: Clear default value. + * SET: A Define List Group Addresses have been received. + * @rmtoll EVR GRPF LL_I3C_IsActiveFlag_GRP + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_GRP(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->EVR, I3C_EVR_GRPF) == (I3C_EVR_GRPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Protocol Error flag. + * RESET: Clear default value. + * SET: Protocol error detected. + * @rmtoll SER PERR LL_I3C_IsActiveFlag_PERR + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_PERR(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->SER, I3C_SER_PERR) == (I3C_SER_PERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of SCL Stall Error flag (target mode). + * RESET: Clear default value. + * SET: Target detected that SCL was stable for more than 125us during I3C SDR read. + * @rmtoll SER STALL LL_I3C_IsActiveFlag_STALL + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_STALL(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->SER, I3C_SER_STALL) == (I3C_SER_STALL)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of RX or TX FIFO Overrun flag. + * RESET: Clear default value. + * SET: RX FIFO Full or TX FIFO Empty depending of direction of message. + * @rmtoll SER DOVR LL_I3C_IsActiveFlag_DOVR + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DOVR(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->SER, I3C_SER_DOVR) == (I3C_SER_DOVR)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Control or Status FIFO Overrun flag (controller mode). + * RESET: Clear default value. + * SET: Status FIFO Full or Control FIFO Empty after Restart. + * @rmtoll SER COVR LL_I3C_IsActiveFlag_COVR + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_COVR(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->SER, I3C_SER_COVR) == (I3C_SER_COVR)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Address not acknowledged flag (controller mode). + * RESET: Clear default value. + * SET: Controller detected that Target nacked static or dynamic address. + * @rmtoll SER ANACK LL_I3C_IsActiveFlag_ANACK + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_ANACK(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->SER, I3C_SER_ANACK) == (I3C_SER_ANACK)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Data not acknowledged flag (controller mode). + * RESET: Clear default value. + * SET: Controller detected that Target nacked Data byte. + * @rmtoll SER DNACK LL_I3C_IsActiveFlag_DNACK + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DNACK(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->SER, I3C_SER_DNACK) == (I3C_SER_DNACK)) ? 1UL : 0UL); +} + +/** + * @brief Indicates the status of Data error flag (controller mode). + * RESET: Clear default value. + * SET: Controller detected data error during Controller-role handoff process. + * @rmtoll SER DERR LL_I3C_IsActiveFlag_DERR + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DERR(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->SER, I3C_SER_DERR) == (I3C_SER_DERR)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I3C_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Control FIFO Not Full interrupt. + * @rmtoll IER CFNFIE LL_I3C_EnableIT_CFNF + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_CFNF(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_CFNFIE); +} + +/** + * @brief Disable Control FIFO Not Full interrupt. + * @rmtoll IER CFNFIE LL_I3C_DisableIT_CFNF + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_CFNF(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_CFNFIE); +} + +/** + * @brief Check if Control FIFO Not Full interrupt is enabled or disabled. + * @rmtoll IER CFNFIE LL_I3C_IsEnabledIT_CFNF + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_CFNF(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_CFNFIE) == (I3C_IER_CFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Status FIFO Not Empty interrupt. + * @rmtoll IER SFNEIE LL_I3C_EnableIT_SFNE + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_SFNE(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_SFNEIE); +} + +/** + * @brief Disable Status FIFO Not Empty interrupt. + * @rmtoll IER SFNEIE LL_I3C_DisableIT_SFNE + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_SFNE(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_SFNEIE); +} + +/** + * @brief Check if Status FIFO Not Empty interrupt is enabled or disabled. + * @rmtoll IER SFNEIE LL_I3C_IsEnabledIT_SFNE + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_SFNE(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_SFNEIE) == (I3C_IER_SFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Transmit FIFO Not Full interrupt. + * @rmtoll IER TXFNFIE LL_I3C_EnableIT_TXFNF + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_TXFNF(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_TXFNFIE); +} + +/** + * @brief Disable Transmit FIFO Not Full interrupt. + * @rmtoll IER TXFNFIE LL_I3C_DisableIT_TXFNF + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_TXFNF(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_TXFNFIE); +} + +/** + * @brief Check if Transmit FIFO Not Full interrupt is enabled or disabled. + * @rmtoll IER TXFNFIE LL_I3C_IsEnabledIT_TXFNF + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_TXFNF(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_TXFNFIE) == (I3C_IER_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Receive FIFO Not Empty interrupt. + * @rmtoll IER RXFNEIE LL_I3C_EnableIT_RXFNE + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_RXFNE(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_RXFNEIE); +} + +/** + * @brief Disable Receive FIFO Not Empty interrupt. + * @rmtoll IER RXFNEIE LL_I3C_DisableIT_RXFNE + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_RXFNE(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_RXFNEIE); +} + +/** + * @brief Check if Receive FIFO Not Empty interrupt is enabled or disabled. + * @rmtoll IER RXFNEIE LL_I3C_IsEnabledIT_RXFNE + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_RXFNE(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_RXFNEIE) == (I3C_IER_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Frame Complete interrupt. + * @rmtoll IER FCIE LL_I3C_EnableIT_FC + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_FC(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_FCIE); +} + +/** + * @brief Disable Frame Complete interrupt. + * @rmtoll IER FCIE LL_I3C_DisableIT_FC + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_FC(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_FCIE); +} + +/** + * @brief Check if Frame Complete interrupt is enabled or disabled. + * @rmtoll IER FCIE LL_I3C_IsEnabledIT_FC + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_FC(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_FCIE) == (I3C_IER_FCIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Reception Target End interrupt. + * @rmtoll IER RXTGTENDIE LL_I3C_EnableIT_RXTGTEND + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_RXTGTEND(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_RXTGTENDIE); +} + +/** + * @brief Disable Reception Target End interrupt. + * @rmtoll IER RXTGTENDIE LL_I3C_DisableIT_RXTGTEND + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_RXTGTEND(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_RXTGTENDIE); +} + +/** + * @brief Check if Reception Target End interrupt is enabled or disabled. + * @rmtoll IER RXTGTENDIE LL_I3C_IsEnabledIT_RXTGTEND + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_RXTGTEND(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_RXTGTENDIE) == (I3C_IER_RXTGTENDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Error interrupt. + * @rmtoll IER ERRIE LL_I3C_EnableIT_ERR + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_ERR(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_ERRIE); +} + +/** + * @brief Disable Error interrupt. + * @rmtoll IER ERRIE LL_I3C_DisableIT_ERR + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_ERR(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_ERRIE); +} + +/** + * @brief Check if Error interrupt is enabled or disabled. + * @rmtoll IER ERRIE LL_I3C_IsEnabledIT_ERR + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_ERR(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_ERRIE) == (I3C_IER_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable IBI interrupt. + * @rmtoll IER IBIIE LL_I3C_EnableIT_IBI + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_IBI(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_IBIIE); +} + +/** + * @brief Disable IBI interrupt. + * @rmtoll IER IBIIE LL_I3C_DisableIT_IBI + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_IBI(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_IBIIE); +} + +/** + * @brief Check if IBI interrupt is enabled or disabled. + * @rmtoll IER IBIIE LL_I3C_IsEnabledIT_IBI + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_IBI(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_IBIIE) == (I3C_IER_IBIIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable IBI End interrupt. + * @rmtoll IER IBIENDIE LL_I3C_EnableIT_IBIEND + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_IBIEND(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_IBIENDIE); +} + +/** + * @brief Disable IBI End interrupt. + * @rmtoll IER IBIENDIE LL_I3C_DisableIT_IBIEND + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_IBIEND(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_IBIENDIE); +} + +/** + * @brief Check if IBI End interrupt is enabled or disabled. + * @rmtoll IER IBIENDIE LL_I3C_IsEnabledIT_IBIEND + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_IBIEND(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_IBIENDIE) == (I3C_IER_IBIENDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Controller-role interrupt. + * @rmtoll IER CRIE LL_I3C_EnableIT_CR + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_CR(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_CRIE); +} + +/** + * @brief Disable Controller-role interrupt. + * @rmtoll IER CRIE LL_I3C_DisableIT_CR + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_CR(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_CRIE); +} + +/** + * @brief Check if Controller-role interrupt is enabled or disabled. + * @rmtoll IER CRIE LL_I3C_IsEnabledIT_CR + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_CR(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_CRIE) == (I3C_IER_CRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Controller-role Update interrupt. + * @rmtoll IER CRUPDIE LL_I3C_EnableIT_CRUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_CRUPD(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_CRUPDIE); +} + +/** + * @brief Disable Controller-role Update interrupt. + * @rmtoll IER CRUPDIE LL_I3C_DisableIT_CRUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_CRUPD(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_CRUPDIE); +} + +/** + * @brief Check if Controller-role Update interrupt is enabled or disabled. + * @rmtoll IER CRUPDIE LL_I3C_IsEnabledIT_CRUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_CRUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_CRUPDIE) == (I3C_IER_CRUPDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Hot Join interrupt. + * @rmtoll IER HJIE LL_I3C_EnableIT_HJ + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_HJ(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_HJIE); +} + +/** + * @brief Disable Hot Join interrupt. + * @rmtoll IER HJIE LL_I3C_DisableIT_HJ + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_HJ(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_HJIE); +} + +/** + * @brief Check if Hot Join interrupt is enabled or disabled. + * @rmtoll IER HJIE LL_I3C_IsEnabledIT_HJ + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_HJ(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_HJIE) == (I3C_IER_HJIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Wake Up interrupt. + * @rmtoll IER WKPIE LL_I3C_EnableIT_WKP + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_WKP(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_WKPIE); +} + +/** + * @brief Disable Wake Up interrupt. + * @rmtoll IER WKPIE LL_I3C_DisableIT_WKP + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_WKP(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_WKPIE); +} + +/** + * @brief Check if Wake Up is enabled or disabled. + * @rmtoll IER WKPIE LL_I3C_IsEnabledIT_WKP + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_WKP(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_WKPIE) == (I3C_IER_WKPIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Get Command interrupt. + * @rmtoll IER GETIE LL_I3C_EnableIT_GET + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_GET(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_GETIE); +} + +/** + * @brief Disable Get Command interrupt. + * @rmtoll IER GETIE LL_I3C_DisableIT_GET + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_GET(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_GETIE); +} + +/** + * @brief Check if Get Command is enabled or disabled. + * @rmtoll IER GETIE LL_I3C_IsEnabledIT_GET + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_GET(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_GETIE) == (I3C_IER_GETIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Get Status interrupt. + * @rmtoll IER STAIE LL_I3C_EnableIT_STA + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_STA(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_STAIE); +} + +/** + * @brief Disable Get Status interrupt. + * @rmtoll IER STAIE LL_I3C_DisableIT_STA + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_STA(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_STAIE); +} + +/** + * @brief Check if Get Status interrupt is enabled or disabled. + * @rmtoll IER STAIE LL_I3C_IsEnabledIT_STA + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_STA(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_STAIE) == (I3C_IER_STAIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Dynamic Address Update interrupt. + * @rmtoll IER DAUPDIE LL_I3C_EnableIT_DAUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_DAUPD(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_DAUPDIE); +} + +/** + * @brief Disable Dynamic Address Update interrupt. + * @rmtoll IER DAUPDIE LL_I3C_DisableIT_DAUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_DAUPD(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_DAUPDIE); +} + +/** + * @brief Check if Dynamic Address Update interrupt is enabled or disabled. + * @rmtoll IER DAUPDIE LL_I3C_IsEnabledIT_DAUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_DAUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_DAUPDIE) == (I3C_IER_DAUPDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Max Write Length Update interrupt. + * @rmtoll IER MWLUPDIE LL_I3C_EnableIT_MWLUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_MWLUPD(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_MWLUPDIE); +} + +/** + * @brief Disable Max Write Length Update interrupt. + * @rmtoll IER MWLUPDIE LL_I3C_DisableIT_MWLUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_MWLUPD(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_MWLUPDIE); +} + +/** + * @brief Check if Max Write Length Update interrupt is enabled or disabled. + * @rmtoll IER MWLUPDIE LL_I3C_IsEnabledIT_MWLUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_MWLUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_MWLUPDIE) == (I3C_IER_MWLUPDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Max Read Length Update interrupt. + * @rmtoll IER MRLUPDIE LL_I3C_EnableIT_MRLUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_MRLUPD(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_MRLUPDIE); +} + +/** + * @brief Disable Max Read Length Update interrupt. + * @rmtoll IER MRLUPDIE LL_I3C_DisableIT_MRLUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_MRLUPD(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_MRLUPDIE); +} + +/** + * @brief Check if Max Read Length Update interrupt is enabled or disabled. + * @rmtoll IER MRLUPDIE LL_I3C_IsEnabledIT_MRLUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_MRLUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_MRLUPDIE) == (I3C_IER_MRLUPDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Reset interrupt. + * @rmtoll IER RSTIE LL_I3C_EnableIT_RST + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_RST(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_RSTIE); +} + +/** + * @brief Disable Reset interrupt. + * @rmtoll IER RSTIE LL_I3C_DisableIT_RST + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_RST(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_RSTIE); +} + +/** + * @brief Check if Reset interrupt is enabled or disabled. + * @rmtoll IER RSTIE LL_I3C_IsEnabledIT_RST + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_RST(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_RSTIE) == (I3C_IER_RSTIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Activity State Update interrupt. + * @rmtoll IER ASUPDIE LL_I3C_EnableIT_ASUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_ASUPD(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_ASUPDIE); +} + +/** + * @brief Disable Activity State Update interrupt. + * @rmtoll IER ASUPDIE LL_I3C_DisableIT_ASUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_ASUPD(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_ASUPDIE); +} + +/** + * @brief Check if Activity State Update interrupt is enabled or disabled. + * @rmtoll IER ASUPDIE LL_I3C_IsEnabledIT_ASUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_ASUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_ASUPDIE) == (I3C_IER_ASUPDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Interrupt Update interrupt. + * @rmtoll IER INTUPDIE LL_I3C_EnableIT_INTUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_INTUPD(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_INTUPDIE); +} + +/** + * @brief Disable Interrupt Update interrupt. + * @rmtoll IER INTUPDIE LL_I3C_DisableIT_INTUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_INTUPD(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_INTUPDIE); +} + +/** + * @brief Check if Interrupt Update interrupt is enabled or disabled. + * @rmtoll IER INTUPDIE LL_I3C_IsEnabledIT_INTUPD + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_INTUPD(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_INTUPDIE) == (I3C_IER_INTUPDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Define List Target interrupt. + * @rmtoll IER DEFIE LL_I3C_EnableIT_DEF + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_DEF(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_DEFIE); +} + +/** + * @brief Disable Define List Target interrupt. + * @rmtoll IER DEFIE LL_I3C_DisableIT_DEF + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_DEF(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_DEFIE); +} + +/** + * @brief Check if Define List Target interrupt is enabled or disabled. + * @rmtoll IER DEFIE LL_I3C_IsEnabledIT_DEF + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_DEF(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_DEFIE) == (I3C_IER_DEFIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Define List Group Addresses interrupt. + * @rmtoll IER GRPIE LL_I3C_EnableIT_GRP + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_EnableIT_GRP(I3C_TypeDef *I3Cx) +{ + SET_BIT(I3Cx->IER, I3C_IER_GRPIE); +} + +/** + * @brief Disable Define List Group Addresses interrupt. + * @rmtoll IER GRPIE LL_I3C_DisableIT_GRP + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_DisableIT_GRP(I3C_TypeDef *I3Cx) +{ + CLEAR_BIT(I3Cx->IER, I3C_IER_GRPIE); +} + +/** + * @brief Check if Define List Group Addresses interrupt is enabled or disabled. + * @rmtoll IER GRPIE LL_I3C_IsEnabledIT_GRP + * @param I3Cx I3C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_GRP(const I3C_TypeDef *I3Cx) +{ + return ((READ_BIT(I3Cx->IER, I3C_IER_GRPIE) == (I3C_IER_GRPIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @addtogroup I3C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Clear Frame Complete flag (controller and target mode). + * @rmtoll CEVR CFCF LL_I3C_ClearFlag_FC + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_FC(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CFCF); +} + +/** + * @brief Clear Reception Target End flag (controller mode). + * @rmtoll CEVR CRXTGTENDF LL_I3C_ClearFlag_RXTGTEND + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_RXTGTEND(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CRXTGTENDF); +} + +/** + * @brief Clear Error flag (controller and target mode). + * @rmtoll CEVR CERRF LL_I3C_ClearFlag_ERR + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_ERR(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CERRF); +} + +/** + * @brief Clear IBI flag (controller mode). + * @rmtoll CEVR CIBIF LL_I3C_ClearFlag_IBI + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_IBI(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CIBIF); +} + +/** + * @brief Clear IBI End flag (target mode). + * @rmtoll CEVR CIBIENDF LL_I3C_ClearFlag_IBIEND + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_IBIEND(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CIBIENDF); +} + +/** + * @brief Clear Controller-role Request flag (controller mode). + * @rmtoll CEVR CCRF LL_I3C_ClearFlag_CR + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_CR(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CCRF); +} + +/** + * @brief Clear Controller-role Request Update flag (target mode). + * @rmtoll CEVR CCRUPDF LL_I3C_ClearFlag_CRUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_CRUPD(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CCRUPDF); +} + +/** + * @brief Clear Hot Join flag (controller mode). + * @rmtoll CEVR CHJF LL_I3C_ClearFlag_HJ + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_HJ(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CHJF); +} + +/** + * @brief Clear Wake Up flag (target mode). + * @rmtoll CEVR CWKPF LL_I3C_ClearFlag_WKP + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_WKP(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CWKPF); +} + +/** + * @brief Clear Get flag (target mode). + * @rmtoll CEVR CGETF LL_I3C_ClearFlag_GET + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_GET(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CGETF); +} + +/** + * @brief Clear Get Status flag (target mode). + * @rmtoll CEVR CSTAF LL_I3C_ClearFlag_STA + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_STA(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CSTAF); +} + +/** + * @brief Clear Dynamic Address Update flag (target mode). + * @rmtoll CEVR CDAUPDF LL_I3C_ClearFlag_DAUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_DAUPD(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CDAUPDF); +} + +/** + * @brief Clear Max Write Length flag (target mode). + * @rmtoll CEVR CMWLUPDF LL_I3C_ClearFlag_MWLUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_MWLUPD(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CMWLUPDF); +} + +/** + * @brief Clear Max Read Length flag (target mode). + * @rmtoll CEVR CMRLUPDF LL_I3C_ClearFlag_MRLUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_MRLUPD(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CMRLUPDF); +} + +/** + * @brief Clear Reset flag (target mode). + * @rmtoll CEVR CRSTF LL_I3C_ClearFlag_RST + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_RST(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CRSTF); +} + +/** + * @brief Clear Active State flag (target mode). + * @rmtoll CEVR CASUPDF LL_I3C_ClearFlag_ASUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_ASUPD(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CASUPDF); +} + +/** + * @brief Clear Interrupt Update flag (target mode). + * @rmtoll CEVR CINTUPDF LL_I3C_ClearFlag_INTUPD + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_INTUPD(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CINTUPDF); +} + +/** + * @brief Clear Define List Targets flag (target mode). + * @rmtoll CEVR CDEFF LL_I3C_ClearFlag_DEF + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_DEF(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CDEFF); +} + +/** + * @brief Clear Define List Group Addresses flag. + * @rmtoll CEVR CGRPF LL_I3C_ClearFlag_GRP + * @param I3Cx I3C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I3C_ClearFlag_GRP(I3C_TypeDef *I3Cx) +{ + WRITE_REG(I3Cx->CEVR, I3C_CEVR_CGRPF); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I3C_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I3C_Init(I3C_TypeDef *I3Cx, LL_I3C_InitTypeDef *I3C_InitStruct, uint32_t Mode); +ErrorStatus LL_I3C_DeInit(const I3C_TypeDef *I3Cx); +void LL_I3C_StructInit(LL_I3C_InitTypeDef *I3C_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I3C1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7RSxx_LL_I3C_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_icache.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_icache.h new file mode 100644 index 00000000000..a3921a43d2a --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_icache.h @@ -0,0 +1,453 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_icache.h + * @author MCD Application Team + * @brief Header file of ICACHE LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion ------------------------------------*/ +#ifndef STM32H7RSxx_LL_ICACHE_H +#define STM32H7RSxx_LL_ICACHE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -----------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(ICACHE) + +/** @defgroup ICACHE_LL ICACHE + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants -------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants + * @{ + */ + +/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection + * @{ + */ +#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ +#define LL_ICACHE_4WAYS ICACHE_CR_WAYSEL /*!< 4-ways set associative cache (default) */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type + * @{ + */ +#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */ +#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */ +#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_ICACHE_ReadReg function + * @{ + */ +#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */ +#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */ +#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_ICACHE_WriteReg function + * @{ + */ +#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */ +#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions + * @{ + */ +#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ +#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macros ----------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros + * @{ + */ + +/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in ICACHE register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__)) + +/** + * @brief Read a value in ICACHE register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions + * @{ + */ + +/** @defgroup ICACHE_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable the ICACHE. + * @rmtoll CR EN LL_ICACHE_Enable + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_Enable(void) +{ + SET_BIT(ICACHE->CR, ICACHE_CR_EN); +} + +/** + * @brief Disable the ICACHE. + * @rmtoll CR EN LL_ICACHE_Disable + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_Disable(void) +{ + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); +} + +/** + * @brief Return if ICACHE is enabled or not. + * @rmtoll CR EN LL_ICACHE_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void) +{ + return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Select the ICACHE operating mode. + * @rmtoll CR WAYSEL LL_ICACHE_SetMode + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_ICACHE_1WAY + * @arg @ref LL_ICACHE_4WAYS + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode) +{ + MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode); +} + +/** + * @brief Get the selected ICACHE operating mode. + * @rmtoll CR WAYSEL LL_ICACHE_GetMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_1WAY + * @arg @ref LL_ICACHE_4WAYS + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void) +{ + return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL)); +} + +/** + * @brief Invalidate the ICACHE. + * @note Until the BSYEND flag is set, the cache is bypassed. + * @rmtoll CR CACHEINV LL_ICACHE_Invalidate + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_Invalidate(void) +{ + SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_Monitors Monitors + * @{ + */ + +/** + * @brief Enable the hit/miss monitor(s). + * @rmtoll CR HITMEN LL_ICACHE_EnableMonitors + * @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors) +{ + SET_BIT(ICACHE->CR, Monitors); +} + +/** + * @brief Disable the hit/miss monitor(s). + * @rmtoll CR HITMEN LL_ICACHE_DisableMonitors + * @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors) +{ + CLEAR_BIT(ICACHE->CR, Monitors); +} + +/** + * @brief Check if the monitor(s) is(are) enabled or disabled. + * @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors + * @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval State of parameter value (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors) +{ + return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL); +} + +/** + * @brief Reset the hit/miss monitor(s). + * @rmtoll CR HITMRST LL_ICACHE_ResetMonitors + * @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors) +{ + /* Reset */ + SET_BIT(ICACHE->CR, (Monitors << 2U)); + /* Release reset */ + CLEAR_BIT(ICACHE->CR, (Monitors << 2U)); +} + +/** + * @brief Get the Hit monitor. + * @note Upon reaching the 32-bit maximum value, hit monitor does not wrap. + * @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void) +{ + return (ICACHE->HMONR); +} + +/** + * @brief Get the Miss monitor. + * @note Upon reaching the 16-bit maximum value, miss monitor does not wrap. + * @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor + * @retval Value between Min_Data=0 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void) +{ + return (ICACHE->MMONR); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable BSYEND interrupt. + * @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void) +{ + SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); +} + +/** + * @brief Disable BSYEND interrupt. + * @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void) +{ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); +} + +/** + * @brief Check if the BSYEND Interrupt is enabled or disabled. + * @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void) +{ + return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable ERR interrupt. + * @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void) +{ + SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE); +} + +/** + * @brief Disable ERR interrupt. + * @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void) +{ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); +} + +/** + * @brief Check if the ERR Interrupt is enabled or disabled. + * @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void) +{ + return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Indicate the status of an ongoing operation flag. + * @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void) +{ + return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of an operation end flag. + * @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void) +{ + return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of an error flag. + * @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void) +{ + return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear busy end of operation flag. + * @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void) +{ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); +} + +/** + * @brief Clear error flag. + * @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void) +{ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ICACHE */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_ICACHE_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_iwdg.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_iwdg.h new file mode 100644 index 00000000000..400440276bd --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_iwdg.h @@ -0,0 +1,453 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_iwdg.h + * @author MCD Application Team + * @brief Header file of IWDG LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_IWDG_H +#define STM32H7RSxx_LL_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(IWDG) + +/** @defgroup IWDG_LL IWDG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants + * @{ + */ +#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ +#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ +#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ +#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants + * @{ + */ + +/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_IWDG_ReadReg function + * @{ + */ +#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ +#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ +#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */ +/** + * @} + */ + +/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider + * @{ + */ +#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */ +#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */ +#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */ +#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ +#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */ +#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */ +#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */ +#define LL_IWDG_PRESCALER_512 (IWDG_PR_PR_2 | IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 512 */ +#define LL_IWDG_PRESCALER_1024 IWDG_PR_PR_3 /*!< Divider by 1024 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros + * @{ + */ + +/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in IWDG register + * @param __INSTANCE__ IWDG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in IWDG register + * @param __INSTANCE__ IWDG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions + * @{ + */ +/** @defgroup IWDG_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Start the Independent Watchdog + * @note Except if the hardware watchdog option is selected + * @rmtoll KR KEY LL_IWDG_Enable + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * @rmtoll KR KEY LL_IWDG_ReloadCounter + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); +} + +/** + * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers + * @rmtoll KR KEY LL_IWDG_EnableWriteAccess + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); +} + +/** + * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers + * @rmtoll KR KEY LL_IWDG_DisableWriteAccess + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); +} + +/** + * @brief Select the prescaler of the IWDG + * @rmtoll PR PR LL_IWDG_SetPrescaler + * @param IWDGx IWDG Instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + * @arg @ref LL_IWDG_PRESCALER_512 + * @arg @ref LL_IWDG_PRESCALER_1024 + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler) +{ + WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); +} + +/** + * @brief Get the selected prescaler of the IWDG + * @rmtoll PR PR LL_IWDG_GetPrescaler + * @param IWDGx IWDG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + * @arg @ref LL_IWDG_PRESCALER_512 + * @arg @ref LL_IWDG_PRESCALER_1024 + */ +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx) +{ + return (READ_REG(IWDGx->PR)); +} + +/** + * @brief Specify the IWDG down-counter reload value + * @rmtoll RLR RL LL_IWDG_SetReloadCounter + * @param IWDGx IWDG Instance + * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter) +{ + WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); +} + +/** + * @brief Get the specified IWDG down-counter reload value + * @rmtoll RLR RL LL_IWDG_GetReloadCounter + * @param IWDGx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx) +{ + return (READ_REG(IWDGx->RLR)); +} + +/** + * @brief Specify high limit of the window value to be compared to the down-counter. + * @rmtoll WINR WIN LL_IWDG_SetWindow + * @param IWDGx IWDG Instance + * @param Window Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) +{ + WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window); +} + +/** + * @brief Get the high limit of the window value specified. + * @rmtoll WINR WIN LL_IWDG_GetWindow + * @param IWDGx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx) +{ + return (READ_REG(IWDGx->WINR)); +} + +/** + * @} + */ + +/** @defgroup IWDG_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Specify comparator value that will be used to trig Early Wakeup interrupt + * @rmtoll EWCR EWIT LL_IWDG_SetEwiTime + * @param IWDGx IWDG Instance + * @param Time Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetEwiTime(IWDG_TypeDef *IWDGx, uint32_t Time) +{ + MODIFY_REG(IWDGx->EWCR, IWDG_EWCR_EWIT, Time); +} + +/** + * @brief Get the Early Wakeup interrupt comparator value + * @rmtoll EWCR EWIT LL_IWDG_GetEwiTime + * @param IWDGx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetEwiTime(const IWDG_TypeDef *IWDGx) +{ + return (READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIT)); +} + +/** + * @brief Enable Early wakeup interrupt + * @rmtoll EWCR EWIE LL_IWDG_EnableIT_EWI + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_EnableIT_EWI(IWDG_TypeDef *IWDGx) +{ + SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); +} + +/** + * @brief Disable Early wakeup interrupt + * @rmtoll EWCR EWIE LL_IWDG_DisableIT_EWI + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_DisableIT_EWI(IWDG_TypeDef *IWDGx) +{ + CLEAR_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); +} + +/** + * @brief Indicates whether Early wakeup interrupt is enable + * @rmtoll EWCR EWIE LL_IWDG_IsEnabledIT_EWI + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE uint32_t LL_IWDG_IsEnabledIT_EWI(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE) == (IWDG_EWCR_EWIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if flag Prescaler Value Update is set or not + * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); +} + +/** + * @brief Check if flag Reload Value Update is set or not + * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); +} + +/** + * @brief Check if flag Window Value Update is set or not + * @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL); +} + +/** + * @brief Check if flag EWI Value Update is set or not + * @rmtoll SR EVU LL_IWDG_IsActiveFlag_EWU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWU(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_EWU) == (IWDG_SR_EWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if all flags Prescaler, Reload, Window & Early Interrupt Value Update are reset or not + * @rmtoll SR PVU LL_IWDG_IsReady\n + * SR RVU LL_IWDG_IsReady\n + * SR WVU LL_IWDG_IsReady\n + * SR EWU LL_IWDG_IsReady + * @param IWDGx IWDG Instance + * @retval State of bits (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU | IWDG_SR_EWU) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Check if IWDG has been started or not + * @rmtoll SR ONF LL_IWDG_IsActiveFlag_ONF + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_ONF(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_ONF) == (IWDG_SR_ONF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Early Wakeup interrupt flag is set or not + * @rmtoll SR EWIF LL_IWDG_IsActiveFlag_EWIF + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWIF(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_EWIF) == (IWDG_SR_EWIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Early Wakeup interrupt flag + * @rmtoll EWCR EWIC LL_IWDG_ClearFlag_EWIF + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_ClearFlag_EWIF(IWDG_TypeDef *IWDGx) +{ + SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIC); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* IWDG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_IWDG_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_lptim.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_lptim.h new file mode 100644 index 00000000000..0bed724d60c --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_lptim.h @@ -0,0 +1,2458 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_lptim.h + * @author MCD Application Team + * @brief Header file of LPTIM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_LPTIM_H +#define STM32H7RSxx_LL_LPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5) + +/** @defgroup LPTIM_LL LPTIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup LPTIM_LL_Private_variables LPTIM Private variables + * @{ + */ + +static const uint8_t LL_LPTIM_SHIFT_TAB_CCxP[] = +{ + 0U, /* CC1P */ + 16U /* CC2P */ +}; + +static const uint8_t LL_LPTIM_SHIFT_TAB_ICxF[] = +{ + 0U, /* IC1F */ + 16U /* IC2F */ +}; + +static const uint8_t LL_LPTIM_SHIFT_TAB_ICxPSC[] = +{ + 0U, /* IC1PSC */ + 16U /* IC2PSC */ +}; + +static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] = +{ + 0U, /* CC1SEL */ + 16U /* CC2SEL */ +}; + +static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] = +{ + LPTIM_CCMR1_CC1E_Pos, /* CC1E */ + LPTIM_CCMR1_CC2E_Pos /* CC2E */ +}; + +static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] = +{ + {2, 7, 9, 13}, + {3, 5, 6, 8}, + {2, 3, 4, 5}, + {2, 2, 3, 3}, + {2, 2, 2, 2}, + {2, 2, 2, 2}, + {2, 2, 2, 2}, + {2, 2, 2, 2} + +}; + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure + * @{ + */ + +/** + * @brief LPTIM Init structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance. + This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE. + + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_SetClockSource().*/ + + uint32_t Prescaler; /*!< Specifies the prescaler division ratio. + This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER. + + This feature can be modified afterwards using using unitary + function @ref LL_LPTIM_SetPrescaler().*/ + + uint32_t Waveform; /*!< Specifies the waveform shape. + This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM. + + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_SetWaveform().*/ +} LL_LPTIM_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants + * @{ + */ + +/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_LPTIM_ReadReg function + * @{ + */ +#define LL_LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK /*!< Compare register 1 update OK */ +#define LL_LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK /*!< Compare register 2 update OK */ +#define LL_LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define LL_LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define LL_LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF /*!< Capture/Compare 1 over-capture flag */ +#define LL_LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF /*!< Capture/Compare 2 over-capture flag */ +#define LL_LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK /*!< Interrupt enable register update OK */ +#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */ +#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */ +#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */ +#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */ +#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */ +#define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */ +#define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions + * @{ + */ +#define LL_LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE /*!< Compare register 1 update OK */ +#define LL_LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE /*!< Compare register 2 update OK */ +#define LL_LPTIM_DIER_CC1IFIE LPTIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt flag */ +#define LL_LPTIM_DIER_CC2IFIE LPTIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt flag */ +#define LL_LPTIM_DIER_CC1OFIE LPTIM_DIER_CC1OIE /*!< Capture/Compare 1 over-capture flag */ +#define LL_LPTIM_DIER_CC2OFIE LPTIM_DIER_CC2OIE /*!< Capture/Compare 2 over-capture flag */ +#define LL_LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE /*!< Autoreload match */ +#define LL_LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE /*!< External trigger edge event */ +#define LL_LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE /*!< Autoreload register update OK */ +#define LL_LPTIM_DIER_UPIE LPTIM_DIER_UPIE /*!< Counter direction change down to up */ +#define LL_LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE /*!< Counter direction change up to down */ +#define LL_LPTIM_DIER_UEIE LPTIM_DIER_UEIE /*!< Update event */ +#define LL_LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE /*!< Repetition register update OK */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode + * @{ + */ +#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in LPTIM register + * @param __INSTANCE__ LPTIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) + +/** + * @brief LPTimer Input Capture Get Offset(in counter step unit) + * @note The real capture value corresponding to the input capture trigger can be calculated using + * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset + * The Offset value is depending on the glitch filter value for the channel + * and the value of the prescaler for the kernel clock. + * Please check Errata Sheet V1_8 for more details under "variable latency + * on input capture channel" section. + * @param __PSC__ This parameter can be one of the following values: + * @arg @ref LL_LPTIM_PRESCALER_DIV1 + * @arg @ref LL_LPTIM_PRESCALER_DIV2 + * @arg @ref LL_LPTIM_PRESCALER_DIV4 + * @arg @ref LL_LPTIM_PRESCALER_DIV8 + * @arg @ref LL_LPTIM_PRESCALER_DIV16 + * @arg @ref LL_LPTIM_PRESCALER_DIV32 + * @arg @ref LL_LPTIM_PRESCALER_DIV64 + * @arg @ref LL_LPTIM_PRESCALER_DIV128 + * @param __FLT__ This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8 + * @retval offset value + */ +#define LL_LPTIM_IC_GET_OFFSET(__PSC__, __FLT__) LL_LPTIM_OFFSET_TAB_ICx\ + [((__PSC__) & LPTIM_CFGR_PRESC_Msk) >> LPTIM_CFGR_PRESC_Pos]\ + [((__FLT__) & LPTIM_CCMR1_IC1F_Msk) >> LPTIM_CCMR1_IC1F_Pos] +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions + * @{ + */ + +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM +#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 +#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 +#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O +#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O +#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM +/** +@endcond + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx); +void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration + * @{ + */ + +/** + * @brief Enable the LPTIM instance + * @note After setting the ENABLE bit, a delay of two counter clock is needed + * before the LPTIM instance is actually enabled. + * @rmtoll CR ENABLE LL_LPTIM_Enable + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); +} + +/** + * @brief Disable the LPTIM instance + * @rmtoll CR ENABLE LL_LPTIM_Disable + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); +} + +/** + * @brief Indicates whether the LPTIM instance is enabled. + * @rmtoll CR ENABLE LL_LPTIM_IsEnabled + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); +} + +/** + * @brief Starts the LPTIM counter in the desired mode. + * @note LPTIM instance must be enabled before starting the counter. + * @note It is possible to change on the fly from One Shot mode to + * Continuous mode. + * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n + * CR SNGSTRT LL_LPTIM_StartCounter + * @param LPTIMx Low-Power Timer instance + * @param OperatingMode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS + * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode) +{ + MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode); +} + +/** + * @brief Enable reset after read. + * @note After calling this function any read access to LPTIM_CNT + * register will asynchronously reset the LPTIM_CNT register content. + * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE); +} + +/** + * @brief Disable reset after read. + * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE); +} + +/** + * @brief Indicate whether the reset after read feature is enabled. + * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL)); +} + +/** + * @brief Reset of the LPTIM_CNT counter register (synchronous). + * @note Due to the synchronous nature of this reset, it only takes + * place after a synchronization delay of 3 LPTIM core clock cycles + * (LPTIM core clock may be different from APB clock). + * @note COUNTRST is automatically cleared by hardware + * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST); +} + +/** + * @brief Set the LPTIM registers update mode (enable/disable register preload) + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode + * @param LPTIMx Low-Power Timer instance + * @param UpdateMode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE + * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode); +} + +/** + * @brief Get the LPTIM registers update mode + * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE + * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); +} + +/** + * @brief Set the auto reload value + * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled + * @note After a write to the LPTIMx_ARR register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the ARROK flag is set, will + * lead to unpredictable results. + * @note autoreload value be strictly greater than the compare value. + * @rmtoll ARR ARR LL_LPTIM_SetAutoReload + * @param LPTIMx Low-Power Timer instance + * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload) +{ + MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload); +} + +/** + * @brief Get actual auto reload value + * @rmtoll ARR ARR LL_LPTIM_GetAutoReload + * @param LPTIMx Low-Power Timer instance + * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); +} + +/** + * @brief Set the repetition value + * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled + * @rmtoll RCR REP LL_LPTIM_SetRepetition + * @param LPTIMx Low-Power Timer instance + * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition) +{ + MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition); +} + +/** + * @brief Get the repetition value + * @rmtoll RCR REP LL_LPTIM_GetRepetition + * @param LPTIMx Low-Power Timer instance + * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP)); +} + +/** + * @brief Enable capture/compare channel. + * @rmtoll CCMR1 CC1E LL_LPTIM_CC_EnableChannel\n + * CCMR1 CC2E LL_LPTIM_CC_EnableChannel + * @param LPTIMx LPTimer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + SET_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]); +} + +/** + * @brief Disable capture/compare channel. + * @rmtoll CCMR1 CC1E LL_LPTIM_CC_DisableChannel\n + * CCMR1 CC2E LL_LPTIM_CC_DisableChannel + * @param LPTIMx LPTimer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + CLEAR_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]); +} + +/** + * @brief Indicate whether channel is enabled. + * @rmtoll CCMR1 CC1E LL_LPTIM_CC_IsEnabledChannel\n + * CCMR1 CC2E LL_LPTIM_CC_IsEnabledChannel + * @param LPTIMx LPTimer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + return ((READ_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]) == \ + (0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel])) ? 1UL : 0UL); + +} + +/** + * @brief Set the compare value + * @note After a write to the LPTIMx_CCR1 register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the CMP1OK flag is set, will + * lead to unpredictable results. + * @rmtoll CCR1 CCR1 LL_LPTIM_OC_SetCompareCH1 + * @param LPTIMx Low-Power Timer instance + * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue) +{ + MODIFY_REG(LPTIMx->CCR1, LPTIM_CCR1_CCR1, CompareValue); +} + +/** + * @brief Get actual compare value + * @rmtoll CCR1 CCR1 LL_LPTIM_OC_GetCompareCH1 + * @param LPTIMx Low-Power Timer instance + * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1)); +} + +/** + * @brief Set the compare value + * @note After a write to the LPTIMx_CCR2 register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the CMP2OK flag is set, will + * lead to unpredictable results. + * @rmtoll CCR2 CCR2 LL_LPTIM_OC_SetCompareCH2 + * @param LPTIMx Low-Power Timer instance + * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue) +{ + MODIFY_REG(LPTIMx->CCR2, LPTIM_CCR2_CCR2, CompareValue); +} + +/** + * @brief Get actual compare value + * @rmtoll CCR2 CCR2 LL_LPTIM_OC_GetCompareCH2 + * @param LPTIMx Low-Power Timer instance + * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2)); +} + +/** + * @brief Get actual counter value + * @note When the LPTIM instance is running with an asynchronous clock, reading + * the LPTIMx_CNT register may return unreliable values. So in this case + * it is necessary to perform two consecutive read accesses and verify + * that the two returned values are identical. + * @rmtoll CNT CNT LL_LPTIM_GetCounter + * @param LPTIMx Low-Power Timer instance + * @retval Counter value + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT)); +} + +/** + * @brief Set the counter mode (selection of the LPTIM counter clock source). + * @note The counter mode can be set only when the LPTIM instance is disabled. + * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode + * @param LPTIMx Low-Power Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL + * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode); +} + +/** + * @brief Get the counter mode + * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL + * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); +} + +/** + * @brief Set waveform shape + * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform + * @param LPTIMx Low-Power Timer instance + * @param Waveform This parameter can be one of the following values: + * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform); +} + +/** + * @brief Get actual waveform shape + * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE)); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCMR1 CC1P LL_LPTIM_OC_SetPolarity\n + * @rmtoll CCMR1 CC2P LL_LPTIM_OC_SetPolarity\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity) +{ + if ((LPTIMx == LPTIM4) || (LPTIMx == LPTIM5)) + { + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, ((Polarity >> LPTIM_CCMR1_CC1P_Pos) << LPTIM_CFGR_WAVPOL_Pos)); + } + else + { + MODIFY_REG(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]), + (Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel])); + } +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCMR1 CC1P LL_LPTIM_OC_GetPolarity\n + * @rmtoll CCMR1 CC2P LL_LPTIM_OC_GetPolarity\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE + */ +__STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + if ((LPTIMx == LPTIM4) || (LPTIMx == LPTIM5)) + { + return (uint32_t)((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL) >> LPTIM_CFGR_WAVPOL_Pos) << LPTIM_CCMR1_CC1P_Pos); + } + else + { + return (uint32_t)(READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]) >> \ + LL_LPTIM_SHIFT_TAB_CCxP[Channel]); + } +} + +/** + * @brief Set actual prescaler division ratio. + * @note This function must be called when the LPTIM instance is disabled. + * @note When the LPTIM is configured to be clocked by an internal clock source + * and the LPTIM counter is configured to be updated by active edges + * detected on the LPTIM external Input1, the internal clock provided to + * the LPTIM must be not be prescaled. + * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler + * @param LPTIMx Low-Power Timer instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_LPTIM_PRESCALER_DIV1 + * @arg @ref LL_LPTIM_PRESCALER_DIV2 + * @arg @ref LL_LPTIM_PRESCALER_DIV4 + * @arg @ref LL_LPTIM_PRESCALER_DIV8 + * @arg @ref LL_LPTIM_PRESCALER_DIV16 + * @arg @ref LL_LPTIM_PRESCALER_DIV32 + * @arg @ref LL_LPTIM_PRESCALER_DIV64 + * @arg @ref LL_LPTIM_PRESCALER_DIV128 + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler); +} + +/** + * @brief Get actual prescaler division ratio. + * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_PRESCALER_DIV1 + * @arg @ref LL_LPTIM_PRESCALER_DIV2 + * @arg @ref LL_LPTIM_PRESCALER_DIV4 + * @arg @ref LL_LPTIM_PRESCALER_DIV8 + * @arg @ref LL_LPTIM_PRESCALER_DIV16 + * @arg @ref LL_LPTIM_PRESCALER_DIV32 + * @arg @ref LL_LPTIM_PRESCALER_DIV64 + * @arg @ref LL_LPTIM_PRESCALER_DIV128 + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC)); +} + +/** + * @brief Set LPTIM input 1 source (default GPIO). + * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src + * @param LPTIMx Low-Power Timer instance + * @param Src This parameter can be one of the following values: + * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) +{ + MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src); +} + +/** + * @brief Set LPTIM input 2 source (default GPIO). + * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src + * @param LPTIMx Low-Power Timer instance + * @param Src This parameter can be one of the following values: + * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) +{ + MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src); +} + +/** + * @brief Set LPTIM input source (default GPIO). + * @rmtoll CFGR2 IC1SEL LL_LPTIM_SetRemap + * @rmtoll CFGR2 IC2SEL LL_LPTIM_SetRemap + * @param LPTIMx Low-Power Timer instance + * @param Src This parameter can be one of the following values: + * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI + * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE + * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI_1024 + * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_CSI_128 + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetRemap(LPTIM_TypeDef *LPTIMx, uint32_t Src) +{ + MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL, Src); +} + +/** + * @brief Set the polarity of IC channel 1. + * @rmtoll CCMR1 CC1P LL_LPTIM_IC_SetPolarity\n + * @rmtoll CCMR1 CC2P LL_LPTIM_IC_SetPolarity\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ICPOLARITY_RISING + * @arg @ref LL_LPTIM_ICPOLARITY_FALLING + * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel], + Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]); +} + +/** + * @brief Get the polarity of IC channels. + * @rmtoll CCMR1 CC1P LL_LPTIM_IC_GetPolarity\n + * @rmtoll CCMR1 CC2P LL_LPTIM_IC_GetPolarity\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_ICPOLARITY_RISING + * @arg @ref LL_LPTIM_ICPOLARITY_FALLING + * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >> \ + LL_LPTIM_SHIFT_TAB_CCxP[Channel]); + +} + +/** + * @brief Set the filter of IC channels. + * @rmtoll CCMR1 IC1F LL_LPTIM_IC_SetFilter\n + * @rmtoll CCMR1 IC2F LL_LPTIM_IC_SetFilter\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param Filter This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Filter) +{ + MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel], + Filter << LL_LPTIM_SHIFT_TAB_ICxF[Channel]); +} + +/** + * @brief Get the filter of IC channels. + * @rmtoll CCMR1 IC1F LL_LPTIM_IC_GetFilter\n + * @rmtoll CCMR1 IC2F LL_LPTIM_IC_GetFilter\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8 + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel])) >> \ + LL_LPTIM_SHIFT_TAB_ICxF[Channel]); +} + +/** + * @brief Set the prescaler of IC channels. + * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_SetPrescaler\n + * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_SetPrescaler\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ICPSC_DIV1 + * @arg @ref LL_LPTIM_ICPSC_DIV2 + * @arg @ref LL_LPTIM_ICPSC_DIV4 + * @arg @ref LL_LPTIM_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Prescaler) +{ + MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel], + Prescaler << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]); +} + +/** + * @brief Get the prescaler of IC channels. + * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_GetPrescaler\n + * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_GetPrescaler\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_ICPSC_DIV1 + * @arg @ref LL_LPTIM_ICPSC_DIV2 + * @arg @ref LL_LPTIM_ICPSC_DIV4 + * @arg @ref LL_LPTIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel])) >> \ + LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]); +} + +/** + * @brief Set the Channel Mode. + * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_SetChannelMode\n + * CCMR1 CC2SEL LL_LPTIM_CC_SetChannelMode + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param CCMode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM + * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode) +{ + SET_BIT(LPTIMx->CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]); +} + +/** + * @brief Get the Channel Mode. + * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_GetChannelMode\n + * CCMR1 CC2SEL LL_LPTIM_CC_GetChannelMode + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM + * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE + */ +__STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel])) >> \ + LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]); +} + +/** + * @brief Get captured value for input channel 1. + * @rmtoll CCR1 CCR1 LL_LPTIM_IC_GetCaptureCH1 + * @note The real capture value corresponding to the input capture trigger can be calculated using + * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset + * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET + * @param LPTIMx Low-Power Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @rmtoll CCR2 CCR2 LL_LPTIM_IC_GetCaptureCH2 + * @note The real capture value corresponding to the input capture trigger can be calculated using + * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset + * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET + * @param LPTIMx Low-Power Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration + * @{ + */ + +/** + * @brief Enable the timeout function + * @note This function must be called when the LPTIM instance is disabled. + * @note The first trigger event will start the timer, any successive trigger + * event will reset the counter and the timer will restart. + * @note The timeout value corresponds to the compare value; if no trigger + * occurs within the expected time frame, the MCU is waked-up by the + * compare match event. + * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT); +} + +/** + * @brief Disable the timeout function + * @note This function must be called when the LPTIM instance is disabled. + * @note A trigger event arriving when the timer is already started will be + * ignored. + * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT); +} + +/** + * @brief Indicate whether the timeout function is enabled. + * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); +} + +/** + * @brief Start the LPTIM counter + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN); +} + +/** + * @brief Configure the external trigger used as a trigger event for the LPTIM. + * @note This function must be called when the LPTIM instance is disabled. + * @note An internal clock source must be present when a digital filter is + * required for the trigger. + * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n + * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n + * CFGR TRIGEN LL_LPTIM_ConfigTrigger + * @param LPTIMx Low-Power Timer instance + * @param Source This parameter can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 + * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_A + * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_B + * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A + * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B + * @arg @ref LL_LPTIM3_TRIG_SOURCE_LPTIM2_CH1 + * @arg @ref LL_LPTIM3_TRIG_SOURCE_LPTIM4 + * @arg @ref LL_LPTIM3_TRIG_SOURCE_LPTIM5 + * @arg @ref LL_LPTIM4_TRIG_SOURCE_LPTIM2_CH1 + * @arg @ref LL_LPTIM4_TRIG_SOURCE_LPTIM3_CH1 + * @arg @ref LL_LPTIM4_TRIG_SOURCE_LPTIM5 + * @arg @ref LL_LPTIM5_TRIG_SOURCE_LPTIM2_CH1 + * @arg @ref LL_LPTIM5_TRIG_SOURCE_LPTIM3_CH1 + * @arg @ref LL_LPTIM5_TRIG_SOURCE_LPTIM4 + * @param Filter This parameter can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_FILTER_NONE + * @arg @ref LL_LPTIM_TRIG_FILTER_2 + * @arg @ref LL_LPTIM_TRIG_FILTER_4 + * @arg @ref LL_LPTIM_TRIG_FILTER_8 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING + * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity); +} + +/** + * @brief Get actual external trigger source. + * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 + * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_A + * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_B + * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A + * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B + * @arg @ref LL_LPTIM3_TRIG_SOURCE_LPTIM2_CH1 + * @arg @ref LL_LPTIM3_TRIG_SOURCE_LPTIM4 + * @arg @ref LL_LPTIM3_TRIG_SOURCE_LPTIM5 + * @arg @ref LL_LPTIM4_TRIG_SOURCE_LPTIM2_CH1 + * @arg @ref LL_LPTIM4_TRIG_SOURCE_LPTIM3_CH1 + * @arg @ref LL_LPTIM4_TRIG_SOURCE_LPTIM5 + * @arg @ref LL_LPTIM5_TRIG_SOURCE_LPTIM2_CH1 + * @arg @ref LL_LPTIM5_TRIG_SOURCE_LPTIM3_CH1 + * @arg @ref LL_LPTIM5_TRIG_SOURCE_LPTIM4 + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL)); +} + +/** + * @brief Get actual external trigger filter. + * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_FILTER_NONE + * @arg @ref LL_LPTIM_TRIG_FILTER_2 + * @arg @ref LL_LPTIM_TRIG_FILTER_4 + * @arg @ref LL_LPTIM_TRIG_FILTER_8 + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT)); +} + +/** + * @brief Get actual external trigger polarity. + * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING + * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration + * @{ + */ + +/** + * @brief Set the source of the clock used by the LPTIM instance. + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource + * @param LPTIMx Low-Power Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL + * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource); +} + +/** + * @brief Get actual LPTIM instance clock source. + * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL + * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL)); +} + +/** + * @brief Configure the active edge or edges used by the counter when + the LPTIM is clocked by an external clock source. + * @note This function must be called when the LPTIM instance is disabled. + * @note When both external clock signal edges are considered active ones, + * the LPTIM must also be clocked by an internal clock source with a + * frequency equal to at least four times the external clock frequency. + * @note An internal clock source must be present when a digital filter is + * required for external clock. + * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n + * CFGR CKPOL LL_LPTIM_ConfigClock + * @param LPTIMx Low-Power Timer instance + * @param ClockFilter This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CLK_FILTER_NONE + * @arg @ref LL_LPTIM_CLK_FILTER_2 + * @arg @ref LL_LPTIM_CLK_FILTER_4 + * @arg @ref LL_LPTIM_CLK_FILTER_8 + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING + * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity); +} + +/** + * @brief Get actual clock polarity + * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING + * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); +} + +/** + * @brief Get actual clock digital filter + * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_CLK_FILTER_NONE + * @arg @ref LL_LPTIM_CLK_FILTER_2 + * @arg @ref LL_LPTIM_CLK_FILTER_4 + * @arg @ref LL_LPTIM_CLK_FILTER_8 + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode + * @{ + */ + +/** + * @brief Configure the encoder mode. + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode + * @param LPTIMx Low-Power Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING + * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode); +} + +/** + * @brief Get actual encoder mode. + * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING + * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); +} + +/** + * @brief Enable the encoder mode + * @note This function must be called when the LPTIM instance is disabled. + * @note In this mode the LPTIM instance must be clocked by an internal clock + * source. Also, the prescaler division ratio must be equal to 1. + * @note LPTIM instance must be configured in continuous mode prior enabling + * the encoder mode. + * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC); +} + +/** + * @brief Disable the encoder mode + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC); +} + +/** + * @brief Indicates whether the LPTIM operates in encoder mode. + * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear the compare match flag for channel 1 (CC1CF) + * @rmtoll ICR CC1CF LL_LPTIM_ClearFlag_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1CF); +} + +/** + * @brief Inform application whether a capture/compare interrupt has occurred for channel 1. + * @rmtoll ISR CC1IF LL_LPTIM_IsActiveFlag_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL)); +} + +/** + * @brief Clear the compare match flag for channel 2 (CC2CF) + * @rmtoll ICR CC2CF LL_LPTIM_ClearFlag_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2CF); +} + +/** + * @brief Inform application whether a capture/compare interrupt has occurred for channel 2. + * @rmtoll ISR CC2IF LL_LPTIM_IsActiveFlag_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL)); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF) + * @rmtoll ICR CC1OCF LL_LPTIM_ClearFlag_CC1O + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1OCF); +} + +/** + * @brief Inform application whether a Capture/Compare 1 over-capture has occurred for channel 1. + * @rmtoll ISR CC1OF LL_LPTIM_IsActiveFlag_CC1O + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL)); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF) + * @rmtoll ICR CC2OCF LL_LPTIM_ClearFlag_CC2O + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2OCF); +} + +/** + * @brief Inform application whether a Capture/Compare 2 over-capture has occurred for channel 2. + * @rmtoll ISR CC2OF LL_LPTIM_IsActiveFlag_CC2O + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL)); +} +/** + * @brief Clear the autoreload match flag (ARRMCF) + * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF); +} + +/** + * @brief Inform application whether a autoreload match interrupt has occurred. + * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); +} + +/** + * @brief Clear the external trigger valid edge flag(EXTTRIGCF). + * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF); +} + +/** + * @brief Inform application whether a valid edge on the selected external trigger input has occurred. + * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); +} + +/** + * @brief Clear the compare register update interrupt flag (CMP1OKCF). + * @rmtoll ICR CMP1OKCF LL_LPTIM_ClearFlag_CMP1OK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP1OKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR1 register has been successfully + completed. If so, a new one can be initiated. + * @rmtoll ISR CMP1OK LL_LPTIM_IsActiveFlag_CMP1OK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL)); +} + +/** + * @brief Clear the compare register update interrupt flag (CMP2OKCF). + * @rmtoll ICR CMP2OKCF LL_LPTIM_ClearFlag_CMP2OK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP2OKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR2 register has been successfully + completed. If so, a new one can be initiated. + * @rmtoll ISR CMP2OK LL_LPTIM_IsActiveFlag_CMP2OK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL)); +} + +/** + * @brief Clear the interrupt register update interrupt flag (DIEROKCF). + * @rmtoll ICR DIEROKCF LL_LPTIM_ClearFlag_DIEROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_DIEROKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_DIER register has been successfully + completed. If so, a new one can be initiated. + * @rmtoll ISR DIEROK LL_LPTIM_IsActiveFlag_DIEROK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL); +} + +/** + * @brief Clear the autoreload register update interrupt flag (ARROKCF). + * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully + completed. If so, a new one can be initiated. + * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); +} + +/** + * @brief Clear the counter direction change to up interrupt flag (UPCF). + * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF); +} + +/** + * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance + operates in encoder mode). + * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); +} + +/** + * @brief Clear the counter direction change to down interrupt flag (DOWNCF). + * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF); +} + +/** + * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance + operates in encoder mode). + * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); +} + +/** + * @brief Clear the repetition register update interrupt flag (REPOKCF). + * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully + completed; If so, a new one can be initiated. + * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL); +} + +/** + * @brief Clear the update event flag (UECF). + * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF); +} + +/** + * @brief Informs application whether the LPTIMx update event has occurred. + * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management + * @{ + */ +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_LPTIM_EnableIT_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_LPTIM_DisableIT_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll DIER CC1IE LL_LPTIM_IsEnabledIT_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL)); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_LPTIM_EnableIT_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_LPTIM_DisableIT_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll DIER CC2IE LL_LPTIM_IsEnabledIT_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL)); +} + +/** + * @brief Enable capture/compare 1 over-capture interrupt (CC1OIE). + * @rmtoll DIER CC1OIE LL_LPTIM_EnableIT_CC1O + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE); +} + +/** + * @brief Disable capture/compare 1 over-capture interrupt (CC1OIE). + * @rmtoll DIER CC1OIE LL_LPTIM_DisableIT_CC1O + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE); +} + +/** + * @brief Indicates whether the capture/compare 1 over-capture interrupt (CC1OIE) is enabled. + * @rmtoll DIER CC1OIE LL_LPTIM_IsEnabledIT_CC1O + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable capture/compare 1 over-capture interrupt (CC2OIE). + * @rmtoll DIER CC2OIE LL_LPTIM_EnableIT_CC2O + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE); +} + +/** + * @brief Disable capture/compare 1 over-capture interrupt (CC2OIE). + * @rmtoll DIER CC2OIE LL_LPTIM_DisableIT_CC2O + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE); +} + +/** + * @brief Indicates whether the capture/compare 2 over-capture interrupt (CC2OIE) is enabled. + * @rmtoll DIER CC2OIE LL_LPTIM_IsEnabledIT_CC2O + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable autoreload match interrupt (ARRMIE). + * @rmtoll DIER ARRMIE LL_LPTIM_EnableIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE); +} + +/** + * @brief Disable autoreload match interrupt (ARRMIE). + * @rmtoll DIER ARRMIE LL_LPTIM_DisableIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE); +} + +/** + * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled. + * @rmtoll DIER ARRMIE LL_LPTIM_IsEnabledIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable external trigger valid edge interrupt (EXTTRIGIE). + * @rmtoll DIER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE); +} + +/** + * @brief Disable external trigger valid edge interrupt (EXTTRIGIE). + * @rmtoll DIER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE); +} + +/** + * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled. + * @rmtoll DIER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable compare register write completed interrupt (CMP1OKIE). + * @rmtoll IER CMP1OKIE LL_LPTIM_EnableIT_CMP1OK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE); +} + +/** + * @brief Disable compare register write completed interrupt (CMP1OKIE). + * @rmtoll IER CMPO1KIE LL_LPTIM_DisableIT_CMP1OK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE); +} + +/** + * @brief Indicates whether the compare register write completed interrupt (CMP1OKIE) is enabled. + * @rmtoll IER CMP1OKIE LL_LPTIM_IsEnabledIT_CMP1OK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable compare register write completed interrupt (CMP2OKIE). + * @rmtoll IER CMP2OKIE LL_LPTIM_EnableIT_CMP2OK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE); +} + +/** + * @brief Disable compare register write completed interrupt (CMP2OKIE). + * @rmtoll IER CMP2OKIE LL_LPTIM_DisableIT_CMP2OK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE); +} + +/** + * @brief Indicates whether the compare register write completed interrupt (CMP2OKIE) is enabled. + * @rmtoll IER CMP2OKIE LL_LPTIM_IsEnabledIT_CMP2OK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable autoreload register write completed interrupt (ARROKIE). + * @rmtoll DIER ARROKIE LL_LPTIM_EnableIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE); +} + +/** + * @brief Disable autoreload register write completed interrupt (ARROKIE). + * @rmtoll DIER ARROKIE LL_LPTIM_DisableIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE); +} + +/** + * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. + * @rmtoll DIER ARROKIE LL_LPTIM_IsEnabledIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit(1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable direction change to up interrupt (UPIE). + * @rmtoll DIER UPIE LL_LPTIM_EnableIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE); +} + +/** + * @brief Disable direction change to up interrupt (UPIE). + * @rmtoll DIER UPIE LL_LPTIM_DisableIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE); +} + +/** + * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. + * @rmtoll DIER UPIE LL_LPTIM_IsEnabledIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval State of bit(1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable direction change to down interrupt (DOWNIE). + * @rmtoll DIER DOWNIE LL_LPTIM_EnableIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE); +} + +/** + * @brief Disable direction change to down interrupt (DOWNIE). + * @rmtoll DIER DOWNIE LL_LPTIM_DisableIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE); +} + +/** + * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. + * @rmtoll DIER DOWNIE LL_LPTIM_IsEnabledIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval State of bit(1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL); +} + +/** + * @brief Enable repetition register update successfully completed interrupt (REPOKIE). + * @rmtoll DIER REPOKIE LL_LPTIM_EnableIT_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE); +} + +/** + * @brief Disable repetition register update successfully completed interrupt (REPOKIE). + * @rmtoll DIER REPOKIE LL_LPTIM_DisableIT_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE); +} + +/** + * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled. + * @rmtoll DIER REPOKIE LL_LPTIM_IsEnabledIT_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit(1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable update event interrupt (UEIE). + * @rmtoll DIER UEIE LL_LPTIM_EnableIT_UE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE); +} + +/** + * @brief Disable update event interrupt (UEIE). + * @rmtoll DIER UEIE LL_LPTIM_DisableIT_UE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE); +} + +/** + * @brief Indicates whether the update event interrupt (UEIE) is enabled. + * @rmtoll DIER UEIE LL_LPTIM_IsEnabledIT_UE + * @param LPTIMx Low-Power Timer instance + *@ retval State of bit(1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL); +} +/** + * @} + */ + + +/** @defgroup TIM_LL_EF_DMA_Management DMA Management + * @{ + */ +/** + * @brief Enable update DMA request. + * @rmtoll DIER UEDE LL_LPTIM_EnableDMAReq_UPDATE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE); +} + +/** + * @brief Disable update DMA request. + * @rmtoll DIER UEDE LL_LPTIM_DisableDMAReq_UPDATE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE); +} + +/** + * @brief Indicates whether the update DMA request is enabled. + * @rmtoll DIER UEDE LL_LPTIM_IsEnabledDMAReq_UPDATE + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_LPTIM_EnableDMAReq_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_LPTIM_DisableDMAReq_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll DIER CC1DE LL_LPTIM_IsEnabledDMAReq_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_LPTIM_EnableDMAReq_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_LPTIM_DisableDMAReq_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll DIER CC2DE LL_LPTIM_IsEnabledDMAReq_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL); +} + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_LPTIM_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_lpuart.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_lpuart.h new file mode 100644 index 00000000000..c635c7da12f --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_lpuart.h @@ -0,0 +1,2658 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_lpuart.h + * @author MCD Application Team + * @brief Header file of LPUART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_LPUART_H +#define STM32H7RSxx_LL_LPUART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (LPUART1) + +/** @defgroup LPUART_LL LPUART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables + * @{ + */ +/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */ +static const uint16_t LPUART_PRESCALER_TAB[] = +{ + (uint16_t)1, + (uint16_t)2, + (uint16_t)4, + (uint16_t)6, + (uint16_t)8, + (uint16_t)10, + (uint16_t)12, + (uint16_t)16, + (uint16_t)32, + (uint16_t)64, + (uint16_t)128, + (uint16_t)256 +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants + * @{ + */ +/* Defines used in Baud Rate related macros and corresponding register setting computation */ +#define LPUART_LPUARTDIV_FREQ_MUL 256U +#define LPUART_BRR_MASK 0x000FFFFFU +#define LPUART_BRR_MIN_VALUE 0x00000300U +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures + * @{ + */ + +/** + * @brief LL LPUART Init Structure definition + */ +typedef struct +{ + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref LPUART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetPrescaler().*/ + + uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref LPUART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref LPUART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref LPUART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetHWFlowCtrl().*/ + +} LL_LPUART_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants + * @{ + */ + +/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_LPUART_WriteReg function + * @{ + */ +#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_LPUART_ReadReg function + * @{ + */ +#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions + * @{ + */ +#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty + interrupt enable */ +#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO + not full interrupt enable */ +#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DIRECTION Direction + * @{ + */ +#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ +#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received + in positive/direct logic. (1=H, 0=L) */ +#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received + in negative/inverse logic. (1=L, 0=H). + The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, + following the start bit */ +#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, + following the start bit */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested + when there is space in the receive buffer */ +#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted + when the nCTS input is asserted (tied to 0)*/ +#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation + * @{ + */ +#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros + * @{ + */ + +/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in LPUART register + * @param __INSTANCE__ LPUART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in LPUART register + * @param __INSTANCE__ LPUART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros + * @{ + */ + +/** + * @brief Compute LPUARTDIV value according to Peripheral Clock and + * expected Baud Rate (20-bit value of LPUARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud Rate value to achieve + * @retval LPUARTDIV value to be used for BRR register filling + */ +#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\ + ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\ + * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions + * @{ + */ + +/** @defgroup LPUART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief LPUART Enable + * @rmtoll CR1 UE LL_LPUART_Enable + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_UE); +} + +/** + * @brief LPUART Disable + * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the LPUART is kept, but all the status + * flags, in the LPUARTx_ISR are set to their default values. + * @note In order to go into low-power mode without generating errors on the line, + * the TE bit must be reset before and the software must wait + * for the TC bit in the LPUART_ISR to be set before resetting the UE bit. + * The DMA requests are also reset when UE = 0 so the DMA channel must + * be disabled before resetting the UE bit. + * @rmtoll CR1 UE LL_LPUART_Disable + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if LPUART is enabled + * @rmtoll CR1 UE LL_LPUART_IsEnabled + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +/** + * @brief FIFO Mode Enable + * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure TX FIFO Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold + * @param LPUARTx LPUART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ + (RXThreshold << USART_CR3_RXFTCFG_Pos)); +} + +/** + * @brief LPUART enabled in STOP Mode + * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that + * LPUART clock selection is HSI or LSE in RCC. + * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief LPUART disabled in STOP Mode + * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode + * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if LPUART is enabled in STOP Mode + * (able to wake up MCU from Stop mode or not) + * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n + * CR1 TE LL_LPUART_SetTransferDirection + * @param LPUARTx LPUART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n + * CR1 TE LL_LPUART_GetTransferDirection + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled) + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_LPUART_SetParity\n + * CR1 PCE LL_LPUART_SetParity + * @param LPUARTx LPUART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_LPUART_GetParity\n + * CR1 PCE LL_LPUART_GetParity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod + * @param LPUARTx LPUART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_LPUART_SetDataWidth + * @param LPUARTx LPUART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_LPUART_GetDataWidth + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_LPUART_EnableMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_LPUART_DisableMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler + * @param LPUARTx LPUART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength + * @param LPUARTx LPUART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function + * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n + * CR1 PCE LL_LPUART_ConfigCharacter\n + * CR1 M LL_LPUART_ConfigCharacter\n + * CR2 STOP LL_LPUART_ConfigCharacter + * @param LPUARTx LPUART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap + * @param LPUARTx LPUART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel + * @param LPUARTx LPUART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel + * @param LPUARTx LPUART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic + * @param LPUARTx LPUART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder + * @param LPUARTx LPUART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Set Address of the LPUART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n + * CR2 ADDM7 LL_LPUART_ConfigNodeAddress + * @param LPUARTx LPUART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the LPUART node. + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress + * @param LPUARTx LPUART Instance + * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n + * CR3 CTSE LL_LPUART_SetHWFlowCtrl + * @param LPUARTx LPUART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n + * CR3 CTSE LL_LPUART_GetHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @rmtoll CR3 WUS LL_LPUART_SetWKUPType + * @param LPUARTx LPUART Instance + * @param Type This parameter can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS + * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT + * @arg @ref LL_LPUART_WAKEUP_ON_RXNE + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type); +} + +/** + * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @rmtoll CR3 WUS LL_LPUART_GetWKUPType + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS + * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT + * @arg @ref LL_LPUART_WAKEUP_ON_RXNE + */ +__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS)); +} + +/** + * @brief Configure LPUART BRR register for achieving expected Baud Rate value. + * + * @note Compute and set LPUARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock and expected Baud Rate values + * @note Peripheral clock and Baud Rate values provided as function parameters should be valid + * (Baud rate value != 0). + * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, + * a care should be taken when generating high baud rates using high PeriphClk + * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate]. + * @rmtoll BRR BRR LL_LPUART_SetBaudRate + * @param LPUARTx LPUART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t BaudRate) +{ + if (BaudRate != 0U) + { + LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); + } +} + +/** + * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @rmtoll BRR BRR LL_LPUART_GetBaudRate + * @param LPUARTx LPUART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, + uint32_t PrescalerValue) +{ + uint32_t lpuartdiv; + uint32_t brrresult; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); + + lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; + + if (lpuartdiv >= LPUART_BRR_MIN_VALUE) + { + brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); + } + else + { + brrresult = 0x0UL; + } + + return (brrresult); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime + * @param LPUARTx LPUART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime + * @param LPUARTx LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : c + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime + * @param LPUARTx LPUART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime + * @param LPUARTx LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @rmtoll CR3 DEM LL_LPUART_EnableDEMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @rmtoll CR3 DEM LL_LPUART_DisableDEMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity + * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity + * @param LPUARTx LPUART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the LPUART Parity Error Flag is set or not + * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Framing Error Flag is set or not + * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Noise error detected Flag is set or not + * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not + * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not + * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS interrupt Flag is set or not + * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS Flag is set or not + * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Busy Flag is set or not + * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Character Match Flag is set or not + * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Wake Up from stop mode Flag is set or not + * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Empty Flag is set or not + * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Full Flag is set or not + * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Threshold Flag is set or not + * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Threshold Flag is set or not + * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); +} + +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise detected Flag + * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_NECF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF); +} + +/** + * @brief Clear Wake Up from stop mode Flag + * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); +} + +#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable Wake Up from Stop Mode Interrupt + * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); +} + +#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable Wake Up from Stop Mode Interrupt + * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled + * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled + * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS Interrupt is enabled or disabled. + * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled. + * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the LPUART data register address used for DMA transfer + * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr + * @param LPUARTx LPUART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(LPUARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(LPUARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_LPUART_ReceiveData8 + * @param LPUARTx LPUART Instance + * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx) +{ + return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_LPUART_ReceiveData9 + * @param LPUARTx LPUART Instance + * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx) +{ + return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_LPUART_TransmitData8 + * @param LPUARTx LPUART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value) +{ + LPUARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_LPUART_TransmitData9 + * @param LPUARTx LPUART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value) +{ + LPUARTx->TDR = Value & 0x1FFUL; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put LPUART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data and FIFO flush + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @brief Request a Transmit data FIFO flush + * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This + * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx); +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct); +void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPUART1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_LPUART_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_pka.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_pka.h new file mode 100644 index 00000000000..2771a0356a2 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_pka.h @@ -0,0 +1,601 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_pka.h + * @author MCD Application Team + * @brief Header file of PKA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_PKA_H +#define STM32H7RSxx_LL_PKA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(PKA) + +/** @defgroup PKA_LL PKA + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PKA_LL_ES_INIT PKA Exported Init structure + * @{ + */ + +/** + * @brief PKA Init structures definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the PKA operation mode. + This parameter can be a value of @ref PKA_LL_EC_MODE. + + This feature can be modified afterwards using unitary function @ref LL_PKA_SetMode(). */ +} LL_PKA_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PKA_LL_Exported_Constants PKA Exported Constants + * @{ + */ + +/** @defgroup PKA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PKA_ReadReg function + * @{ + */ +#define LL_PKA_SR_ADDRERRF PKA_SR_ADDRERRF +#define LL_PKA_SR_RAMERRF PKA_SR_RAMERRF +#define LL_PKA_SR_PROCENDF PKA_SR_PROCENDF +#define LL_PKA_SR_BUSY PKA_SR_BUSY +#define LL_PKA_SR_INITOK PKA_SR_INITOK +#define LL_PKA_SR_OPERRF PKA_SR_OPERRF +/** + * @} + */ + +/** @defgroup PKA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_PKA_ReadReg and LL_PKA_WriteReg functions + * @{ + */ +#define LL_PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE +#define LL_PKA_CR_RAMERRIE PKA_CR_RAMERRIE +#define LL_PKA_CR_PROCENDIE PKA_CR_PROCENDIE +#define LL_PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC +#define LL_PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC +#define LL_PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC +#define LL_PKA_CR_OPERRIE PKA_CR_OPERRIE +#define LL_PKA_CLRFR_OPERRFC PKA_CLRFR_OPERRFC +/** + * @} + */ + +/** @defgroup PKA_LL_EC_MODE Operation Mode + * @brief List of operation mode. + * @{ + */ +#define LL_PKA_MODE_MODULAR_EXP ((uint32_t)0x00000000U) /*!< modular exponentiation */ +#define LL_PKA_MODE_MONTGOMERY_PARAM ((uint32_t)0x00000001U) /*!< Compute Montgomery parameter only */ +#define LL_PKA_MODE_MODULAR_EXP_FAST ((uint32_t)0x00000002U) /*!< modular exponentiation fast mode */ +#define LL_PKA_MODE_MODULAR_EXP_PROTECT ((uint32_t)0x00000003U) /*!< modular exponentiation protect mode */ +#define LL_PKA_MODE_ECC_MUL ((uint32_t)0x00000020U) /*!< compute ECC kP operation */ +#define LL_PKA_MODE_ECC_COMPLETE_ADD ((uint32_t)0x00000023U) /*!< ECC complete addition */ +#define LL_PKA_MODE_ECDSA_SIGNATURE ((uint32_t)0x00000024U) /*!< ECDSA signature */ +#define LL_PKA_MODE_ECDSA_VERIFICATION ((uint32_t)0x00000026U) /*!< ECDSA verification */ +#define LL_PKA_MODE_POINT_CHECK ((uint32_t)0x00000028U) /*!< Point check */ +#define LL_PKA_MODE_RSA_CRT_EXP ((uint32_t)0x00000007U) /*!< RSA CRT exponentiation */ +#define LL_PKA_MODE_MODULAR_INV ((uint32_t)0x00000008U) /*!< Modular inversion */ +#define LL_PKA_MODE_ARITHMETIC_ADD ((uint32_t)0x00000009U) /*!< Arithmetic addition */ +#define LL_PKA_MODE_ARITHMETIC_SUB ((uint32_t)0x0000000AU) /*!< Arithmetic subtraction */ +#define LL_PKA_MODE_ARITHMETIC_MUL ((uint32_t)0x0000000BU) /*!< Arithmetic multiplication */ +#define LL_PKA_MODE_COMPARISON ((uint32_t)0x0000000CU) /*!< Comparison */ +#define LL_PKA_MODE_MODULAR_REDUC ((uint32_t)0x0000000DU) /*!< Modular reduction */ +#define LL_PKA_MODE_MODULAR_ADD ((uint32_t)0x0000000EU) /*!< Modular addition */ +#define LL_PKA_MODE_MODULAR_SUB ((uint32_t)0x0000000FU) /*!< Modular subtraction */ +#define LL_PKA_MODE_MONTGOMERY_MUL ((uint32_t)0x00000010U) /*!< Montgomery multiplication */ +#define LL_PKA_MODE_DOUBLE_BASE_LADDER ((uint32_t)0x00000027U) /*!< Double base ladder */ +#define LL_PKA_MODE_ECC_PROJECTIVE_AFF ((uint32_t)0x0000002FU) /*!< ECC projective to affine */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PKA_LL_Exported_Macros PKA Exported Macros + * @{ + */ + +/** @defgroup PKA_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PKA register + * @param __INSTANCE__ PKA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PKA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PKA register + * @param __INSTANCE__ PKA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PKA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PKA_LL_Exported_Functions PKA Exported Functions + * @{ + */ + +/** @defgroup PKA_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Configure PKA peripheral. + * @brief Set PKA operating mode. + * @rmtoll CR MODE LL_PKA_Config + * @param PKAx PKA Instance. + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM + * @arg @ref LL_PKA_MODE_MODULAR_EXP + * @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE + * @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION + * @arg @ref LL_PKA_MODE_POINT_CHECK + * @arg @ref LL_PKA_MODE_RSA_CRT_EXP + * @arg @ref LL_PKA_MODE_MODULAR_INV + * @arg @ref LL_PKA_MODE_ARITHMETIC_ADD + * @arg @ref LL_PKA_MODE_ARITHMETIC_SUB + * @arg @ref LL_PKA_MODE_ARITHMETIC_MUL + * @arg @ref LL_PKA_MODE_COMPARISON + * @arg @ref LL_PKA_MODE_MODULAR_REDUC + * @arg @ref LL_PKA_MODE_MODULAR_ADD + * @arg @ref LL_PKA_MODE_MODULAR_SUB + * @arg @ref LL_PKA_MODE_MONTGOMERY_MUL + * @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT + * @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER + * @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF + * @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD + * @arg @ref LL_PKA_MODE_ECC_MUL + * @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST + */ +__STATIC_INLINE void LL_PKA_Config(PKA_TypeDef *PKAx, uint32_t Mode) +{ + MODIFY_REG(PKAx->CR, (PKA_CR_MODE), (Mode << PKA_CR_MODE_Pos)); +} + +/** + * @brief Enable PKA peripheral. + * @rmtoll CR EN LL_PKA_Enable + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_Enable(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CR, PKA_CR_EN); +} + +/** + * @brief Disable PKA peripheral. + * @rmtoll CR EN LL_PKA_Disable + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_Disable(PKA_TypeDef *PKAx) +{ + CLEAR_BIT(PKAx->CR, PKA_CR_EN); +} + +/** + * @brief Check if the PKA peripheral is enabled or disabled. + * @rmtoll CR EN LL_PKA_IsEnabled + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabled(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->CR, PKA_CR_EN) == (PKA_CR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Set PKA operating mode. + * @rmtoll CR MODE LL_PKA_SetMode + * @param PKAx PKA Instance. + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM + * @arg @ref LL_PKA_MODE_MODULAR_EXP + * @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE + * @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION + * @arg @ref LL_PKA_MODE_POINT_CHECK + * @arg @ref LL_PKA_MODE_RSA_CRT_EXP + * @arg @ref LL_PKA_MODE_MODULAR_INV + * @arg @ref LL_PKA_MODE_ARITHMETIC_ADD + * @arg @ref LL_PKA_MODE_ARITHMETIC_SUB + * @arg @ref LL_PKA_MODE_ARITHMETIC_MUL + * @arg @ref LL_PKA_MODE_COMPARISON + * @arg @ref LL_PKA_MODE_MODULAR_REDUC + * @arg @ref LL_PKA_MODE_MODULAR_ADD + * @arg @ref LL_PKA_MODE_MODULAR_SUB + * @arg @ref LL_PKA_MODE_MONTGOMERY_MUL + * @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT + * @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER + * @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF + * @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD + * @arg @ref LL_PKA_MODE_ECC_MUL + * @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST + * @retval None + */ +__STATIC_INLINE void LL_PKA_SetMode(PKA_TypeDef *PKAx, uint32_t Mode) +{ + MODIFY_REG(PKAx->CR, PKA_CR_MODE, Mode << PKA_CR_MODE_Pos); +} + +/** + * @brief Get PKA operating mode. + * @rmtoll CR MODE LL_PKA_GetMode + * @param PKAx PKA Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM + * @arg @ref LL_PKA_MODE_MODULAR_EXP + * @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE + * @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION + * @arg @ref LL_PKA_MODE_POINT_CHECK + * @arg @ref LL_PKA_MODE_RSA_CRT_EXP + * @arg @ref LL_PKA_MODE_MODULAR_INV + * @arg @ref LL_PKA_MODE_ARITHMETIC_ADD + * @arg @ref LL_PKA_MODE_ARITHMETIC_SUB + * @arg @ref LL_PKA_MODE_ARITHMETIC_MUL + * @arg @ref LL_PKA_MODE_COMPARISON + * @arg @ref LL_PKA_MODE_MODULAR_REDUC + * @arg @ref LL_PKA_MODE_MODULAR_ADD + * @arg @ref LL_PKA_MODE_MODULAR_SUB + * @arg @ref LL_PKA_MODE_MONTGOMERY_MUL + * @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT + * @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER + * @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF + * @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD + * @arg @ref LL_PKA_MODE_ECC_MUL + * @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST + */ +__STATIC_INLINE uint32_t LL_PKA_GetMode(const PKA_TypeDef *PKAx) +{ + return (uint32_t)(READ_BIT(PKAx->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos); +} + +/** + * @brief Start the operation selected using LL_PKA_SetMode. + * @rmtoll CR START LL_PKA_Start + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_Start(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CR, PKA_CR_START); +} + +/** + * @} + */ + +/** @defgroup PKA_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable address error interrupt. + * @rmtoll CR ADDRERRIE LL_PKA_EnableIT_ADDRERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_EnableIT_ADDRERR(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CR, PKA_CR_ADDRERRIE); +} + +/** + * @brief Enable RAM error interrupt. + * @rmtoll CR RAMERRIE LL_PKA_EnableIT_RAMERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_EnableIT_RAMERR(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CR, PKA_CR_RAMERRIE); +} + +/** + * @brief Enable OPERATION error interrupt. + * @rmtoll CR OPERRIE LL_PKA_EnableIT_OPERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_EnableIT_OPERR(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CR, PKA_CR_OPERRIE); +} + +/** + * @brief Enable end of operation interrupt. + * @rmtoll CR PROCENDIE LL_PKA_EnableIT_PROCEND + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_EnableIT_PROCEND(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CR, PKA_CR_PROCENDIE); +} + +/** + * @brief Disable address error interrupt. + * @rmtoll CR ADDRERRIE LL_PKA_DisableIT_ADDERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_DisableIT_ADDERR(PKA_TypeDef *PKAx) +{ + CLEAR_BIT(PKAx->CR, PKA_CR_ADDRERRIE); +} + +/** + * @brief Disable RAM error interrupt. + * @rmtoll CR RAMERRIE LL_PKA_DisableIT_RAMERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_DisableIT_RAMERR(PKA_TypeDef *PKAx) +{ + CLEAR_BIT(PKAx->CR, PKA_CR_RAMERRIE); +} + +/** + * @brief Disable End of operation interrupt. + * @rmtoll CR PROCENDIE LL_PKA_DisableIT_PROCEND + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_DisableIT_PROCEND(PKA_TypeDef *PKAx) +{ + CLEAR_BIT(PKAx->CR, PKA_CR_PROCENDIE); +} + +/** + * @brief Disable OPERATION error interrupt. + * @rmtoll CR OPERRIE LL_PKA_EnableIT_OPERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_DisableIT_OPERR(PKA_TypeDef *PKAx) +{ + CLEAR_BIT(PKAx->CR, PKA_CR_OPERRIE); +} + +/** + * @brief Check if address error interrupt is enabled. + * @rmtoll CR ADDRERRIE LL_PKA_IsEnabledIT_ADDRERR + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->CR, PKA_CR_ADDRERRIE) == (PKA_CR_ADDRERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if RAM error interrupt is enabled. + * @rmtoll CR RAMERRIE LL_PKA_IsEnabledIT_RAMERR + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->CR, PKA_CR_RAMERRIE) == (PKA_CR_RAMERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if OPERATION error interrupt is enabled. + * @rmtoll CR OPERRIE LL_PKA_IsEnabledIT_OPERR + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_OPERR(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->CR, PKA_CR_OPERRIE) == (PKA_CR_OPERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if end of operation interrupt is enabled. + * @rmtoll CR PROCENDIE LL_PKA_IsEnabledIT_PROCEND + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->CR, PKA_CR_PROCENDIE) == (PKA_CR_PROCENDIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup PKA_LL_EF_FLAG_Management PKA flag management + * @{ + */ + +/** + * @brief Get PKA address error flag. + * @rmtoll SR ADDRERRF LL_PKA_IsActiveFlag_ADDRERR + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->SR, PKA_SR_ADDRERRF) == (PKA_SR_ADDRERRF)) ? 1UL : 0UL); +} + +/** + * @brief Get PKA RAM error flag. + * @rmtoll SR RAMERRF LL_PKA_IsActiveFlag_RAMERR + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->SR, PKA_SR_RAMERRF) == (PKA_SR_RAMERRF)) ? 1UL : 0UL); +} + +/** + * @brief Get PKA OPERATION error flag. + * @rmtoll SR OPERRF LL_PKA_IsActiveFlag_OPERR + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_OPERR(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->SR, PKA_SR_OPERRF) == (PKA_SR_OPERRF)) ? 1UL : 0UL); +} + +/** + * @brief Get PKA end of operation flag. + * @rmtoll SR PROCENDF LL_PKA_IsActiveFlag_PROCEND + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->SR, PKA_SR_PROCENDF) == (PKA_SR_PROCENDF)) ? 1UL : 0UL); +} + +/** + * @brief Get PKA busy flag. + * @rmtoll SR BUSY LL_PKA_IsActiveFlag_BUSY + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->SR, PKA_SR_BUSY) == (PKA_SR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Clear PKA address error flag. + * @rmtoll CLRFR ADDRERRFC LL_PKA_ClearFlag_ADDERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_ClearFlag_ADDERR(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CLRFR, PKA_CLRFR_ADDRERRFC); +} + +/** + * @brief Clear PKA RAM error flag. + * @rmtoll CLRFR RAMERRFC LL_PKA_ClearFlag_RAMERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_ClearFlag_RAMERR(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CLRFR, PKA_CLRFR_RAMERRFC); +} + +/** + * @brief Clear PKA OPERATION error flag. + * @rmtoll CLRFR OPERRFC LL_PKA_ClearFlag_OPERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_ClearFlag_OPERR(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CLRFR, PKA_CLRFR_OPERRFC); +} + +/** + * @brief Clear PKA end of operation flag. + * @rmtoll CLRFR PROCENDFC LL_PKA_ClearFlag_PROCEND + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_ClearFlag_PROCEND(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CLRFR, PKA_CLRFR_PROCENDFC); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup PKA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_PKA_DeInit(const PKA_TypeDef *PKAx); +ErrorStatus LL_PKA_Init(PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct); +void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct); + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PKA) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_PKA_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_pwr.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_pwr.h new file mode 100644 index 00000000000..d0968de437a --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_pwr.h @@ -0,0 +1,1887 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_PWR_H +#define STM32H7RSxx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_LL_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +/* Wake-Up Pins PWR register offsets */ +#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2UL) +#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK (0x1FU) +/** + * @} + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_SR_CSSF PWR_CSR3_CSSF /*!< Clear Stop and Standby flags */ +#define LL_PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1 /*!< Clear Wakeup flag 1 */ +#define LL_PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2 /*!< Clear Wakeup flag 2 */ +#define LL_PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3 /*!< Clear Wakeup flag 3 */ +#define LL_PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4 /*!< Clear Wakeup flag 4 */ +#define LL_PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC /*!< Clear all Wakeup flags */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_FLAG_VOSRDY PWR_CSR4_VOSRDY /*!< Voltage scaling ready flag */ +#define LL_PWR_FLAG_STOPF PWR_CSR3_STOPF /*!< Stop flag */ +#define LL_PWR_FLAG_SBF PWR_CSR3_SBF /*!< Standby flag */ +#define LL_PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag 1 */ +#define LL_PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag 2 */ +#define LL_PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag 3 */ +#define LL_PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag 4 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_MODE_PWR Power Down Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_POWERDOWN_MODE_DS_STOP (0U) /*!< Enter to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_POWERDOWN_MODE_DS_STANDBY PWR_CSR3_PDDS /*!< Enter to Standby mode when the CPU enters deepsleep */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling + * @{ + */ +#define LL_PWR_REGU_VOLTAGE_SCALE0 PWR_CSR4_VOS /*!< Voltage scaling range 0 (highest frequency) */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 (0U) /*!< Voltage scaling range 1 (lowest power) */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling + * @{ + */ +#define LL_PWR_REGU_STOP_VOLTAGE_SCALE3 PWR_CR1_SVOS /*!< Voltage scaling range 3 (highest frequency) when system enters STOP mode */ +#define LL_PWR_REGU_STOP_VOLTAGE_SCALE5 (0U) /*!< Voltage scaling range 5 (lowest power) when system enters STOP mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector + * @{ + */ +#define LL_PWR_PVDLEVEL_1 (0U) /*!< PVD level 1 */ +#define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_0 /*!< PVD level 2 */ +#define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_1 /*!< PVD level 3 */ +#define LL_PWR_PVDLEVEL_4 (PWR_CR1_PLS_0 | PWR_CR1_PLS_1) /*!< PVD level 4 */ +#define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_2 /*!< PVD level 5 */ +#define LL_PWR_PVDLEVEL_6 (PWR_CR1_PLS_0 | PWR_CR1_PLS_2) /*!< PVD level 6 */ +#define LL_PWR_PVDLEVEL_7 (PWR_CR1_PLS_1 | PWR_CR1_PLS_2) /*!< PVD level 7 */ +#define LL_PWR_PVDLEVEL_EXT (PWR_CR1_PLS_0 | PWR_CR1_PLS_1 | PWR_CR1_PLS_2) +/*!< External voltage level on PVD_IN pin, compared to internal VREFINT level */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector + * @{ + */ +#define LL_PWR_AVDLEVEL_1 (0U) /*!< Analog Voltage detector level 1 */ +#define LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_0 /*!< Analog Voltage detector level 2 */ +#define LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_1 /*!< Analog Voltage detector level 3 */ +#define LL_PWR_AVDLEVEL_4 (PWR_CR1_ALS_0 | PWR_CR1_ALS_1) /*!< Analog Voltage detector level 4 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_XSPI_CAP1 XSPI 1 capacitor + * @{ + */ +#define LL_PWR_XSPI1_CAPACITOR_OFF (0U) /*!< XSPI Port 1 Capacitor OFF */ +#define LL_PWR_XSPI1_CAPACITOR_1_DIV_3 PWR_CSR2_XSPICAP1_0 /*!< XSPI Port 1 Capacitor set to 1/3 */ +#define LL_PWR_XSPI1_CAPACITOR_2_DIV_3 PWR_CSR2_XSPICAP1_1 /*!< XSPI Port 1 Capacitor set to 2/3 */ +#define LL_PWR_XSPI1_CAPACITOR_FULL (PWR_CSR2_XSPICAP1_0 | PWR_CSR2_XSPICAP1_1) +/*!< XSPI Port 1 Capacitor set to full capacitance */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_XSPI_CAP2 XSPI 2 Capacitor + * @{ + */ +#define LL_PWR_XSPI2_CAPACITOR_OFF (0U) /*!< XSPI Port 2 Capacitor OFF */ +#define LL_PWR_XSPI2_CAPACITOR_1_DIV_3 PWR_CSR2_XSPICAP2_0 /*!< XSPI Port 2 Capacitor set to 1/3 */ +#define LL_PWR_XSPI2_CAPACITOR_2_DIV_3 PWR_CSR2_XSPICAP2_1 /*!< XSPI Port 2 Capacitor set to 2/3 */ +#define LL_PWR_XSPI2_CAPACITOR_FULL (PWR_CSR2_XSPICAP2_0 | PWR_CSR2_XSPICAP2_1) +/*!< XSPI Port 2 Capacitor set to full capacitance */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor + * @{ + */ +#define LL_PWR_BATT_CHARG_RESISTOR_5K (0U) /*!< Charge the Battery through a 5 kO resistor */ +#define LL_PWR_BATT_CHARG_RESISTOR_1_5K PWR_CSR2_VBRS /*!< Charge the Battery through a 1.5 kO resistor */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wake-Up pin 1 : PA0 */ +#define LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wake-Up pin 2 : PA2 */ +#define LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wake-Up pin 3 : PC13 */ +#define LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wake-Up pin 4 : PC1 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration + * @{ + */ +#define LL_PWR_WAKEUP_PIN_NOPULL (0UL) /*!< Configure Wake-Up pin in no pull */ +#define LL_PWR_WAKEUP_PIN_PULLUP (1UL) /*!< Configure Wake-Up pin in pull Up */ +#define LL_PWR_WAKEUP_PIN_PULLDOWN (2UL) /*!< Configure Wake-Up pin in pull Down */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration + * @{ + */ +#define LL_PWR_LDO_SUPPLY PWR_CSR2_LDOEN /*!< Core domains are supplied from the LDO */ +#define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CSR2_SDEN /*!< Core domains are supplied from the SMPS */ +#define LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CSR2_SDHILEVEL | PWR_CSR2_SDEN | PWR_CSR2_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ +#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | PWR_CSR2_SDEN | PWR_CSR2_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ +#define LL_PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | PWR_CSR2_SDEN | PWR_CSR2_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */ +#define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_CSR2_BYPASS /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GPIO_PIN_MASK PWR GPIO Pin Mask + * @{ + */ +#define LL_PWR_GPIO_PIN_0 (0x0001U) /*!< GPIO port I/O pin 0 */ +#define LL_PWR_GPIO_PIN_1 (0x0002U) /*!< GPIO port I/O pin 1 */ +#define LL_PWR_GPIO_PIN_2 (0x0004U) /*!< GPIO port I/O pin 2 */ +#define LL_PWR_GPIO_PIN_3 (0x0008U) /*!< GPIO port I/O pin 3 */ +#define LL_PWR_GPIO_PIN_4 (0x0010U) /*!< GPIO port I/O pin 4 */ +#define LL_PWR_GPIO_PIN_5 (0x0020U) /*!< GPIO port I/O pin 5 */ +#define LL_PWR_GPIO_PIN_6 (0x0040U) /*!< GPIO port I/O pin 6 */ +#define LL_PWR_GPIO_PIN_7 (0x0080U) /*!< GPIO port I/O pin 7 */ +#define LL_PWR_GPIO_PIN_8 (0x0100U) /*!< GPIO port I/O pin 8 */ +#define LL_PWR_GPIO_PIN_9 (0x0200U) /*!< GPIO port I/O pin 9 */ +#define LL_PWR_GPIO_PIN_10 (0x0400U) /*!< GPIO port I/O pin 10 */ +#define LL_PWR_GPIO_PIN_11 (0x0800U) /*!< GPIO port I/O pin 11 */ +#define LL_PWR_GPIO_PIN_12 (0x1000U) /*!< GPIO port I/O pin 12 */ +#define LL_PWR_GPIO_PIN_13 (0x2000U) /*!< GPIO port I/O pin 13 */ +#define LL_PWR_GPIO_PIN_14 (0x4000U) /*!< GPIO port I/O pin 14 */ +#define LL_PWR_GPIO_PIN_15 (0x8000U) /*!< GPIO port I/O pin 15 */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration PWR Configuration + * @{ + */ + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR1 PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_PVDE); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR1 PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR1 PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_PVDE) == (PWR_CR1_PVDE)) ? 1UL : 0UL); +} + +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR1 PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @arg @ref LL_PWR_PVDLEVEL_EXT + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR1 PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @arg @ref LL_PWR_PVDLEVEL_EXT + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return READ_BIT(PWR->CR1, PWR_CR1_PLS); +} + +/** + * @brief Enable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Flash low-power mode in Stop Mode + * @rmtoll CR1 FLPS LL_PWR_EnableFlashLowPower + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFlashLowPower(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_FLPS); +} + +/** + * @brief Disable the Flash low-power mode in Stop Mode + * @rmtoll CR1 FLPS LL_PWR_DisableFlashLowPower + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFlashLowPower(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS); +} + +/** + * @brief Check if the Flash low-power mode in Stop Mode is enabled + * @rmtoll CR1 FLPS LL_PWR_IsEnabledFlashLowPower + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashLowPower(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Analog Voltage Booster + * @rmtoll CR1 BOOSTE LL_PWR_EnableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAnalogBooster(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_BOOSTE); +} + +/** + * @brief Disable the Analog Voltage Booster + * @rmtoll CR1 BOOSTE LL_PWR_DisableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAnalogBooster(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE); +} + +/** + * @brief Check if the Analog Voltage Booster is enabled + * @rmtoll CR1 BOOSTE LL_PWR_IsEnabledAnalogBooster + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Analog Voltage Ready + * @rmtoll CR1 AVDREADY LL_PWR_EnableAnalogVoltageReady + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AVDREADY); +} + +/** + * @brief Disable the Analog Voltage Ready + * @rmtoll CR1 AVDREADY LL_PWR_DisableAnalogVoltageReady + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AVDREADY); +} + +/** + * @brief Check if the Analog Voltage Ready is enabled + * @rmtoll CR1 AVDREADY LL_PWR_IsEnabledAnalogVoltageReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AVDREADY) == (PWR_CR1_AVDREADY)) ? 1UL : 0UL); +} + +/** + * @brief Enable Analog Power Voltage Monitor + * @rmtoll CR1 AVDEN LL_PWR_EnableAVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAVD(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief Disable Analog Power Voltage Monitor + * @rmtoll CR1 AVDEN LL_PWR_DisableAVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAVD(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief Check if Analog Power Voltage Monitor is enabled + * @rmtoll CR1 AVDEN LL_PWR_IsEnabledAVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the Analog Voltage detector level + * @rmtoll CR1 ALS LL_PWR_SetAVDLevel + * @param AVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_AVDLEVEL_1 + * @arg @ref LL_PWR_AVDLEVEL_2 + * @arg @ref LL_PWR_AVDLEVEL_3 + * @arg @ref LL_PWR_AVDLEVEL_4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel); +} + +/** + * @brief Get the Analog Voltage detector level selected + * @rmtoll CR1 ALS LL_PWR_GetAVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_AVDLEVEL_1 + * @arg @ref LL_PWR_AVDLEVEL_2 + * @arg @ref LL_PWR_AVDLEVEL_3 + * @arg @ref LL_PWR_AVDLEVEL_4 + */ +__STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void) +{ + return READ_BIT(PWR->CR1, PWR_CR1_ALS); +} + +/** + * @brief Enable Backup Regulator + * @rmtoll CSR1 BREN LL_PWR_EnableBkUpRegulator + * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and + * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup + * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set, + * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that + * the data written into the RAM will be maintained in the Standby and VBAT modes. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) +{ + SET_BIT(PWR->CSR1, PWR_CSR1_BREN); +} + +/** + * @brief Disable Backup Regulator + * @rmtoll CSR1 BREN LL_PWR_DisableBkUpRegulator + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) +{ + CLEAR_BIT(PWR->CSR1, PWR_CSR1_BREN); +} + +/** + * @brief Check if the backup Regulator is enabled + * @rmtoll CSR1 BREN LL_PWR_IsEnabledBkUpRegulator + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_BREN) == (PWR_CSR1_BREN)) ? 1UL : 0UL); +} + +/** + * @brief Enable VBAT and Temperature monitoring + * @rmtoll CSR1 MONEN LL_PWR_EnableMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableMonitoring(void) +{ + SET_BIT(PWR->CSR1, PWR_CSR1_MONEN); +} + +/** + * @brief Disable VBAT and Temperature monitoring + * @rmtoll CSR1 MONEN LL_PWR_DisableMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableMonitoring(void) +{ + CLEAR_BIT(PWR->CSR1, PWR_CSR1_MONEN); +} + +/** + * @brief Check if the VBAT and Temperature monitoring is enabled + * @rmtoll CSR1 MONEN LL_PWR_IsEnabledMonitoring + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_MONEN) == (PWR_CSR1_MONEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the PWR supply + * @rmtoll CSR2 SDHILEVEL LL_PWR_ConfigSupply + * @rmtoll CSR2 SMPSEXTHP LL_PWR_ConfigSupply + * @rmtoll CSR2 SDEN LL_PWR_ConfigSupply + * @rmtoll CSR2 LDOEN LL_PWR_ConfigSupply + * @rmtoll CSR2 BYPASS LL_PWR_ConfigSupply + * @param SupplySource This parameter can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + * @retval None + */ +__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource) +{ + /* Set the power supply configuration */ + MODIFY_REG(PWR->CSR2, (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | PWR_CSR2_SDEN | PWR_CSR2_LDOEN | PWR_CSR2_BYPASS), + SupplySource); +} + +/** + * @brief Get the PWR supply + * @rmtoll CSR2 SDHILEVEL LL_PWR_GetSupply + * @rmtoll CSR2 SMPSEXTHP LL_PWR_GetSupply + * @rmtoll CSR2 SDEN LL_PWR_GetSupply + * @rmtoll CSR2 LDOEN LL_PWR_GetSupply + * @rmtoll CSR2 BYPASS LL_PWR_GetSupply + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + */ +__STATIC_INLINE uint32_t LL_PWR_GetSupply(void) +{ + /* Get the power supply configuration */ + return READ_BIT(PWR->CSR2, + (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | PWR_CSR2_SDEN | PWR_CSR2_LDOEN | PWR_CSR2_BYPASS)); +} + +/** + * @brief Enable VBAT battery charging + * @rmtoll CSR2 VBE LL_PWR_EnableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) +{ + SET_BIT(PWR->CSR2, PWR_CSR2_VBE); +} + +/** + * @brief Disable VBAT battery charging + * @rmtoll CSR2 VBE LL_PWR_DisableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) +{ + CLEAR_BIT(PWR->CSR2, PWR_CSR2_VBE); +} + +/** + * @brief Check if VBAT battery charging is enabled + * @rmtoll CSR2 VBE LL_PWR_IsEnabledBatteryCharging + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) +{ + return ((READ_BIT(PWR->CSR2, PWR_CSR2_VBE) == (PWR_CSR2_VBE)) ? 1UL : 0UL); +} + +/** + * @brief Set the Battery charge resistor impedance + * @rmtoll CSR2 VBRS LL_PWR_SetBattChargResistor + * @param Resistor This parameter can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) +{ + MODIFY_REG(PWR->CSR2, PWR_CSR2_VBRS, Resistor); +} + +/** + * @brief Get the Battery charge resistor impedance + * @rmtoll CSR2 VBRS LL_PWR_GetBattChargResistor + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K + */ +__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) +{ + return (READ_BIT(PWR->CSR2, PWR_CSR2_VBRS)); +} + +/** + * @brief Set the XSPI port 1 capacitor value + * @rmtoll CSR2 XSPICAP1 LL_PWR_SetXSPI1Capacitor + * @param Capacitor This parameter can be one of the following values: + * @arg @ref LL_PWR_XSPI1_CAPACITOR_OFF + * @arg @ref LL_PWR_XSPI1_CAPACITOR_1_DIV_3 + * @arg @ref LL_PWR_XSPI1_CAPACITOR_2_DIV_3 + * @arg @ref LL_PWR_XSPI1_CAPACITOR_FULL + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetXSPI1Capacitor(uint32_t Capacitor) +{ + MODIFY_REG(PWR->CSR2, PWR_CSR2_XSPICAP1, Capacitor); +} + +/** + * @brief Get the XSPI port 1 capacitor value + * @rmtoll CSR2 XSPICAP1 LL_PWR_GetXSPI1Capacitor + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_XSPI1_CAPACITOR_OFF + * @arg @ref LL_PWR_XSPI1_CAPACITOR_1_DIV_3 + * @arg @ref LL_PWR_XSPI1_CAPACITOR_2_DIV_3 + * @arg @ref LL_PWR_XSPI1_CAPACITOR_FULL + */ +__STATIC_INLINE uint32_t LL_PWR_GetXSPI1Capacitor(void) +{ + return (READ_BIT(PWR->CSR2, PWR_CSR2_XSPICAP1)); +} + +/** + * @brief Set the XSPI port 2 capacitor value + * @rmtoll CSR2 XSPICAP2 LL_PWR_SetXSPI2Capacitor + * @param Capacitor This parameter can be one of the following values: + * @arg @ref LL_PWR_XSPI2_CAPACITOR_OFF + * @arg @ref LL_PWR_XSPI2_CAPACITOR_1_DIV_3 + * @arg @ref LL_PWR_XSPI2_CAPACITOR_2_DIV_3 + * @arg @ref LL_PWR_XSPI2_CAPACITOR_FULL + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetXSPI2Capacitor(uint32_t Capacitor) +{ + MODIFY_REG(PWR->CSR2, PWR_CSR2_XSPICAP2, Capacitor); +} + +/** + * @brief Get the XSPI port 2 capacitor value + * @rmtoll CSR2 XSPICAP2 LL_PWR_GetXSPI2Capacitor + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_XSPI2_CAPACITOR_OFF + * @arg @ref LL_PWR_XSPI2_CAPACITOR_1_DIV_3 + * @arg @ref LL_PWR_XSPI2_CAPACITOR_2_DIV_3 + * @arg @ref LL_PWR_XSPI2_CAPACITOR_FULL + */ +__STATIC_INLINE uint32_t LL_PWR_GetXSPI2Capacitor(void) +{ + return (uint32_t)(READ_BIT(PWR->CSR2, PWR_CSR2_XSPICAP2)); +} + +/** + * @brief Enable the USB voltage detector + * @rmtoll CSR2 USB33DEN LL_PWR_EnableUSBVoltageDetector + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void) +{ + SET_BIT(PWR->CSR2, PWR_CSR2_USB33DEN); +} + +/** + * @brief Disable the USB voltage detector + * @rmtoll CSR2 USB33DEN LL_PWR_DisableUSBVoltageDetector + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void) +{ + CLEAR_BIT(PWR->CSR2, PWR_CSR2_USB33DEN); +} + +/** + * @brief Check if the USB voltage detector is enabled + * @rmtoll CSR2 USB33DEN LL_PWR_IsEnabledUSBVoltageDetector + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void) +{ + return ((READ_BIT(PWR->CSR2, PWR_CSR2_USB33DEN) == (PWR_CSR2_USB33DEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the USB regulator + * @rmtoll CSR2 USBREGEN LL_PWR_EnableUSBReg + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBReg(void) +{ + SET_BIT(PWR->CSR2, PWR_CSR2_USBREGEN); +} + +/** + * @brief Disable the USB regulator + * @rmtoll CSR2 USBREGEN LL_PWR_DisableUSBReg + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBReg(void) +{ + CLEAR_BIT(PWR->CSR2, PWR_CSR2_USBREGEN); +} + +/** + * @brief Check if the USB regulator is enabled + * @rmtoll CSR2 USBREGEN LL_PWR_IsEnabledUSBReg + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void) +{ + return ((READ_BIT(PWR->CSR2, PWR_CSR2_USBREGEN) == (PWR_CSR2_USBREGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the USB HS PHY regulator + * @rmtoll CSR2 USBHSREGEN LL_PWR_EnableUSBHSPHYReg + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBHSPHYReg(void) +{ + SET_BIT(PWR->CSR2, PWR_CSR2_USBHSREGEN); +} + +/** + * @brief Disable USB HS PHY regulator + * @rmtoll CSR2 USBHSREGEN LL_PWR_DisableUSBHSPHYReg + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBHSPHYReg(void) +{ + CLEAR_BIT(PWR->CSR2, PWR_CSR2_USBHSREGEN); +} + +/** + * @brief Check if the USB HS PHY regulator is enabled + * @rmtoll CSR2 USBHSREGEN LL_PWR_IsEnabledUSBHSPHYReg + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBHSPHYReg(void) +{ + return ((READ_BIT(PWR->CSR2, PWR_CSR2_USBHSREGEN) == (PWR_CSR2_USBHSREGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable UCPD configuration memorization in Standby. + * @rmtoll UCPDR UCPD_STBY LL_PWR_EnableUCPDStandbyMode + * @retval None + * @note This function must be called just before entering Standby mode when using UCPD. + */ +__STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void) +{ + /* Memorize UCPD configuration when entering standby mode */ + SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY); +} + +/** + * @brief Disable UCPD configuration memorization in Standby. + * @rmtoll UCPDR UCPD_STBY LL_PWR_DisableUCPDStandbyMode + * @retval None + * @note This function must be called on exiting the Standby mode and before any UCPD + * configuration update. + */ +__STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void) +{ + CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY); +} + +/** + * @brief Check if the UCPD configuration memorization in Standby is enabled + * @rmtoll UCPDR UCPD_STBY LL_PWR_IsEnabledUCPDStandbyMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void) +{ + return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY) == (PWR_UCPDR_UCPD_STBY)) ? 1UL : 0UL); +} + +/** + * @brief Enable the UCPD dead battery behavior + * @rmtoll UCPDR UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void) +{ + CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); +} + +/** + * @brief Disable the UCPD dead battery behavior + * @rmtoll UCPDR UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void) +{ + SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); +} + +/** + * @brief Check if the UCPD dead battery behavior is enabled + * @rmtoll UCPDR UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void) +{ + return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS) == (PWR_UCPDR_UCPD_DBDIS)) ? 1UL : 0UL); +} + +/** + * @brief Enable the XSPI_P1 interface + * @rmtoll CSR2 EN_XSPIM1 LL_PWR_EnableXSPIM1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableXSPIM1(void) +{ + SET_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM1); +} + +/** + * @brief Disable the XSPI_P1 interface + * @rmtoll CSR2 EN_XSPIM1 LL_PWR_DisableXSPIM1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableXSPIM1(void) +{ + CLEAR_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM1); +} + +/** + * @brief Check if the XSPI_P1 interface is enabled + * @rmtoll CSR2 EN_XSPIM1 LL_PWR_IsEnabledXSPIM1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledXSPIM1(void) +{ + return ((READ_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM1) == (PWR_CSR2_EN_XSPIM1)) ? 1UL : 0UL); +} + +/** + * @brief Enable the XSPI_P2 interface + * @rmtoll CSR2 EN_XSPIM2 LL_PWR_EnableXSPIM2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableXSPIM2(void) +{ + SET_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM2); +} + +/** + * @brief Disable the XSPI_P2 interface + * @rmtoll CSR2 EN_XSPIM2 LL_PWR_DisableXSPIM2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableXSPIM2(void) +{ + CLEAR_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM2); +} + +/** + * @brief Check if the XSPI_P2 interface is enabled + * @rmtoll CSR2 EN_XSPIM2 LL_PWR_IsEnabledXSPIM2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledXSPIM2(void) +{ + return ((READ_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM2) == (PWR_CSR2_EN_XSPIM2)) ? 1UL : 0UL); +} + +/** + * @brief Set the Power Down mode when device enters deepsleep mode + * @rmtoll CSR3 PDDS LL_PWR_SetPowerDownModeDS + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_POWERDOWN_MODE_DS_STOP + * @arg @ref LL_PWR_POWERDOWN_MODE_DS_STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerDownModeDS(uint32_t PDMode) +{ + MODIFY_REG(PWR->CSR3, PWR_CSR3_PDDS, PDMode); +} + +/** + * @brief Get the Power Down mode when device enters deepsleep mode + * @rmtoll CSR3 PDDS LL_PWR_GetPowerDownModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_POWERDOWN_MODE_DS_STOP + * @arg @ref LL_PWR_POWERDOWN_MODE_DS_STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerDownModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CSR3, PWR_CSR3_PDDS)); +} + +/** + * @brief Set the main internal Regulator output voltage + * @rmtoll CSR4 VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->CSR4, PWR_CSR4_VOS, VoltageScaling); +} + +/** + * @brief Get the main internal Regulator output voltage + * @rmtoll CSR4 VOS LL_PWR_GetRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->CSR4, PWR_CSR4_VOS)); +} + +/** + * @brief Set the internal Regulator output voltage in STOP mode + * @rmtoll CR1 SVOS LL_PWR_SetStopModeRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE3 + * @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling); +} + +/** + * @brief Get the internal Regulator output voltage in STOP mode + * @rmtoll CR1 SVOS LL_PWR_GetStopModeRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE3 + * @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE5 + */ +__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void) +{ + return READ_BIT(PWR->CR1, PWR_CR1_SVOS); +} + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll WKUPEPR WKUPEN1 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN2 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN3 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN4 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WKUPEPR, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll WKUPEPR WKUPEN1 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN2 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN3 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN4 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WKUPEPR, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll WKUPEPR WKUPEN1 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN2 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN3 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN4 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin polarity low for the event detection + * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); +} + +/** + * @brief Set the Wake-Up pin polarity high for the event detection + * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); +} + +/** + * @brief Check if the Wake-Up pin polarity is low for event detection + * @rmtoll WKUPEPR WKUPP1 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP2 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP3 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP4 LL_PWR_IsWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin Pull None + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullNone + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WKUPEPR, \ + (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ + (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Set the Wake-Up pin Pull Up + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullUp + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WKUPEPR, \ + (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ + (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Set the Wake-Up pin Pull Down + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullDown + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WKUPEPR, \ + (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ + (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Get the Wake-Up pin pull + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD2 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD3 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD4 LL_PWR_GetWakeUpPinPull\ + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_NOPULL + * @arg @ref LL_PWR_WAKEUP_PIN_PULLUP + * @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin) +{ + uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); + + return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)); +} + +/** + * @brief Enable the pull-up on I3C1_SCL (PB6)) in standby mode + * @rmtoll APCR I3CPB6_PU LL_PWR_EnableI3CPB6PU + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableI3CPB6PU(void) +{ + SET_BIT(PWR->APCR, PWR_APCR_I3CPB6_PU); +} + +/** + * @brief Disable the pull-up on I3C1_SCL (PB6) in standby mode + * @rmtoll APCR I3CPB6_PU LL_PWR_DisableI3CPB6PU + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableI3CPB6PU(void) +{ + CLEAR_BIT(PWR->APCR, PWR_APCR_I3CPB6_PU); +} + +/** + * @brief Check if the pull-up on I3C1_SCL (PB6) in standby mode is enabled + * @rmtoll APCR I3CPB6_PU LL_PWR_IsEnabledI3CPB6PU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledI3CPB6PU(void) +{ + return ((READ_BIT(PWR->APCR, PWR_APCR_I3CPB6_PU) == (PWR_APCR_I3CPB6_PU)) ? 1UL : 0UL); +} + +/** + * @brief Enable the pull-up on I3C1_SDA (PB7) in standby mode + * @rmtoll APCR I3CPB7_PU LL_PWR_EnableI3CPB7PU + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableI3CPB7PU(void) +{ + SET_BIT(PWR->APCR, PWR_APCR_I3CPB7_PU); +} + +/** + * @brief Disable the pull-up on I3C1_SDA (PB7) in standby mode + * @rmtoll APCR I3CPB7_PU LL_PWR_DisableI3CPB7PU + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableI3CPB7PU(void) +{ + CLEAR_BIT(PWR->APCR, PWR_APCR_I3CPB7_PU); +} + +/** + * @brief Check if the pull-up on I3C1_SDA (PB7) in standby mode is enabled + * @rmtoll APCR I3CPB7_PU LL_PWR_IsEnabledI3CPB7PU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledI3CPB7PU(void) +{ + return ((READ_BIT(PWR->APCR, PWR_APCR_I3CPB7_PU) == (PWR_APCR_I3CPB7_PU)) ? 1UL : 0UL); +} + +/** + * @brief Enable the pull-up on I3C1_SCL (PB8) in standby mode + * @rmtoll APCR I3CPB8_PU LL_PWR_EnableI3CPB8PU + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableI3CPB8PU(void) +{ + SET_BIT(PWR->APCR, PWR_APCR_I3CPB8_PU); +} + +/** + * @brief Disable the pull-up on I3C1_SCL (PB8) in standby mode + * @rmtoll APCR I3CPB8_PU LL_PWR_DisableI3CPB8PU + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableI3CPB8PU(void) +{ + CLEAR_BIT(PWR->APCR, PWR_APCR_I3CPB8_PU); +} + +/** + * @brief Check if the pull-up on I3C1_SCL (PB8) in standby mode is enabled + * @rmtoll APCR I3CPB8_PU LL_PWR_IsEnabledI3CPB8PU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledI3CPB8PU(void) +{ + return ((READ_BIT(PWR->APCR, PWR_APCR_I3CPB8_PU) == (PWR_APCR_I3CPB8_PU)) ? 1UL : 0UL); +} + +/** + * @brief Enable the pull-up on I3C1_SDA (PB9) in standby mode + * @rmtoll APCR I3CPB9_PU LL_PWR_EnableI3CPB9PU + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableI3CPB9PU(void) +{ + SET_BIT(PWR->APCR, PWR_APCR_I3CPB9_PU); +} + +/** + * @brief Disable the pull-up on I3C1_SDA (PB9) in standby mode + * @rmtoll APCR I3CPB9_PU LL_PWR_DisableI3CPB9PU + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableI3CPB9PU(void) +{ + CLEAR_BIT(PWR->APCR, PWR_APCR_I3CPB9_PU); +} + +/** + * @brief Check if the pull-up on I3C1_SDA (PB9) in standby mode is enabled + * @rmtoll APCR I3CPB9_PU LL_PWR_IsEnabledI3CPB9PU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledI3CPB9PU(void) +{ + return ((READ_BIT(PWR->APCR, PWR_APCR_I3CPB9_PU) == (PWR_APCR_I3CPB9_PU)) ? 1UL : 0UL); +} + +/** + * @brief Enable the pull-up and pull-down configuration + * @rmtoll APCR APC LL_PWR_EnablePUPDConfig + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePUPDConfig(void) +{ + SET_BIT(PWR->APCR, PWR_APCR_APC); +} + +/** + * @brief Disable the pull-up and pull-down configuration + * @rmtoll APCR APC LL_PWR_DisablePUPDConfig + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePUPDConfig(void) +{ + CLEAR_BIT(PWR->APCR, PWR_APCR_APC); +} + +/** + * @brief Check if the pull-up and pull-down configuration is enabled. + * @rmtoll APCR APC LL_PWR_IsEnabledPUPDConfig + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDConfig(void) +{ + return ((READ_BIT(PWR->APCR, PWR_APCR_APC) == (PWR_APCR_APC)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO N pull-up in Standby mode + * @rmtoll PUCRN PUx LL_PWR_EnableGPIONPullUp + * @param GPIOPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_EnableGPIONPullUp(uint32_t GPIOPin) +{ + SET_BIT(PWR->PUCRN, GPIOPin); +} + +/** + * @brief Disable GPIO N pull-up in Standby mode + * @rmtoll PUCRN PUx LL_PWR_DisableGPIONPullUp + * @param GPIOPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_DisableGPIONPullUp(uint32_t GPIOPin) +{ + CLEAR_BIT(PWR->PUCRN, GPIOPin); +} + +/** + * @brief Check if GPIO pull-up in Standby mode is enabled + * @rmtoll PUCRN PUx LL_PWR_IsEnabledGPIONPullUp + * @param GPIOPin This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIONPullUp(uint32_t GPIOPin) +{ + return ((READ_BIT(PWR->PUCRN, GPIOPin) == (GPIOPin)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO O pull-up in Standby mode + * @rmtoll PUCRO PUx LL_PWR_EnableGPIOOPullUp + * @param GPIOPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_4 + + * @retval None. + */ +__STATIC_INLINE void LL_PWR_EnableGPIOOPullUp(uint32_t GPIOPin) +{ + SET_BIT(PWR->PUCRO, GPIOPin); +} + +/** + * @brief Disable GPIO O pull-up in Standby mode + * @rmtoll PUCRO PUx LL_PWR_DisableGPIOOPullUp + * @param GPIOPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_DisableGPIOOPullUp(uint32_t GPIOPin) +{ + CLEAR_BIT(PWR->PUCRO, GPIOPin); +} + +/** + * @brief Check if GPIO O pull-up in Standby mode is enabled + * @rmtoll PUCRO PUx LL_PWR_IsEnabledGPIOOPullUp + * @param GPIOPin This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOOPullUp(uint32_t GPIOPin) +{ + return ((READ_BIT(PWR->PUCRO, GPIOPin) == (GPIOPin)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO N pull-down in Standby mode + * @rmtoll PDCRN PDx LL_PWR_EnableGPIONPullDown + * @param GPIOPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_EnableGPIONPullDown(uint32_t GPIOPin) +{ + SET_BIT(PWR->PDCRN, GPIOPin); +} + +/** + * @brief Disable GPIO N pull-down in Standby mode + * @rmtoll PDCRN PDx LL_PWR_DisableGPIONPullDown + * @param GPIOPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_DisableGPIONPullDown(uint32_t GPIOPin) +{ + CLEAR_BIT(PWR->PDCRN, GPIOPin); +} + +/** + * @brief Check if GPIO N pull-down in Standby mode is enabled + * @rmtoll PDCRN PDx LL_PWR_IsEnabledGPIONPullDown + * @param GPIOPin This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIONPullDown(uint32_t GPIOPin) +{ + return ((READ_BIT(PWR->PDCRN, GPIOPin) == (GPIOPin)) ? 1UL : 0UL); +} +/** + * @brief Enable GPIO O pull-down in Standby mode + * @rmtoll PDCRO PDx LL_PWR_EnableGPIOOPullDown + * @param GPIOPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_3 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_EnableGPIOOPullDown(uint32_t GPIOPin) +{ + SET_BIT(PWR->PDCRO, GPIOPin); +} + +/** + * @brief Disable GPIO O pull-down in Standby mode + * @rmtoll PDCRO PDx LL_PWR_DisableGPIOOPullDown + * @param GPIOPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_3 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_DisableGPIOOPullDown(uint32_t GPIOPin) +{ + CLEAR_BIT(PWR->PDCRO, GPIOPin); +} + +/** + * @brief Check if GPIO O pull-down in Standby mode is enabled + * @rmtoll PDCRO PDx LL_PWR_IsEnabledGPIOOPullDown + * @param GPIOPin This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_3 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOOPullDown(uint32_t GPIOPin) +{ + return ((READ_BIT(PWR->PDCRO, GPIOPin) == (GPIOPin)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO P pull-down in Standby mode + * @rmtoll PDCRP PDx LL_PWR_EnableGPIOPPullDown + * @param GPIOPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_EnableGPIOPPullDown(uint32_t GPIOPin) +{ + SET_BIT(PWR->PDCRP, GPIOPin); +} + +/** + * @brief Disable GPIO P pull-down in Standby mode + * @rmtoll PDCRP PDx LL_PWR_DisableGPIOPPullDown + * @param GPIOPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_DisableGPIOPPullDown(uint32_t GPIOPin) +{ + CLEAR_BIT(PWR->PDCRP, GPIOPin); +} + +/** + * @brief Check if GPIO P pull-down in Standby mode is enabled + * @rmtoll PDCRP PDx LL_PWR_IsEnabledGPIOPPullDown + * @param GPIOPin This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPPullDown(uint32_t GPIOPin) +{ + return ((READ_BIT(PWR->PDCRP, GPIOPin) == (GPIOPin)) ? 1UL : 0UL); +} +/** + * @} + */ + + +/** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management + * @{ + */ + +/** + * @brief Indicate whether the voltage level is ready for current actual used VOS + * @rmtoll SR1 ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOSRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOSRDY(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_ACTVOSRDY) == (PWR_SR1_ACTVOSRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll SR1 PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_PVDO) == (PWR_SR1_PVDO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether VDDA voltage is below the selected AVD threshold + * @rmtoll SR1 AVDO LL_PWR_IsActiveFlag_AVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void) +{ + return ((READ_BIT(PWR->SR1, PWR_SR1_AVDO) == (PWR_SR1_AVDO)) ? 1UL : 0UL); +} + +/** + * @brief Get Backup Regulator ready Flag + * @rmtoll CSR1 BRRDY LL_PWR_IsActiveFlag_BRRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRRDY(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_BRRDY) == (PWR_CSR1_BRRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VBAT level is above or below low threshold + * @rmtoll CSR1 VBATL LL_PWR_IsActiveFlag_VBATL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_VBATL) == (PWR_CSR1_VBATL)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VBAT level is above or below high threshold + * @rmtoll CSR1 VBATH LL_PWR_IsActiveFlag_VBATH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_VBATH) == (PWR_CSR1_VBATH)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the CPU temperature level is above or below low threshold + * @rmtoll CSR1 TEMPL LL_PWR_IsActiveFlag_TEMPL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_TEMPL) == (PWR_CSR1_TEMPL)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the CPU temperature level is above or below high threshold + * @rmtoll CSR1 TEMPH LL_PWR_IsActiveFlag_TEMPH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_TEMPH) == (PWR_CSR1_TEMPH)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the SMPS external supply is ready or not + * @rmtoll CSR2 SDEXTRDY LL_PWR_IsActiveFlag_SDEXTRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SDEXTRDY(void) +{ + return ((READ_BIT(PWR->CSR2, PWR_CSR2_SDEXTRDY) == (PWR_CSR2_SDEXTRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the USB supply is ready or not + * @rmtoll CSR2 USB33RDY LL_PWR_IsActiveFlag_USB33RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB33RDY(void) +{ + return ((READ_BIT(PWR->CSR2, PWR_CSR2_USB33RDY) == (PWR_CSR2_USB33RDY)) ? 1UL : 0UL); +} + +/** + * @brief Get System Stop Flag + * @rmtoll CSR3 STOPF LL_PWR_IsActiveFlag_STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void) +{ + return ((READ_BIT(PWR->CSR3, PWR_CSR3_STOPF) == (PWR_CSR3_STOPF)) ? 1UL : 0UL); +} + +/** + * @brief Get System Standby Flag + * @rmtoll CSR3 SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return ((READ_BIT(PWR->CSR3, PWR_CSR3_SBF) == (PWR_CSR3_SBF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the Regulator is ready in the selected voltage range + * or if its output voltage is still changing to the required voltage level + * @rmtoll CSR4 VOSRDY LL_PWR_IsActiveFlag_VOSRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSRDY(void) +{ + return ((READ_BIT(PWR->CSR4, PWR_CSR4_VOSRDY) == (PWR_CSR4_VOSRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 1 + * @rmtoll WKUPFR WKUPF1 LL_PWR_IsActiveFlag_WU1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 2 + * @rmtoll WKUPFR WKUPF2 LL_PWR_IsActiveFlag_WU2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 3 + * @rmtoll WKUPFR WKUPF3 LL_PWR_IsActiveFlag_WU3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 4 + * @rmtoll WKUPFR WKUPF4 LL_PWR_IsActiveFlag_WU4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL); +} + +/** + * @brief Clear STOP and STANDBY and flags + * @rmtoll CSR3 CSSF LL_PWR_ClearFlag_STOP_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_STOP_SB(void) +{ + SET_BIT(PWR->CSR3, PWR_CSR3_CSSF); +} + +/** + * @brief Clear Wake-up Flag 1 + * @rmtoll WKUPCR WKUPC1 LL_PWR_ClearFlag_WU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1); +} + +/** + * @brief Clear Wake-up Flag 2 + * @rmtoll WKUPCR WKUPC2 LL_PWR_ClearFlag_WU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2); +} + +/** + * @brief Clear Wake-up Flag 3 + * @rmtoll WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3); +} + +/** + * @brief Clear Wake-up Flag 4 + * @rmtoll WKUPCR WKUPC4 LL_PWR_ClearFlag_WU4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4); +} + +/** + * @brief Clear all wake up flags. + * @rmtoll WUSCR WKUPC LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC); +} + +/** + * @} + */ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* defined (USE_FULL_LL_DRIVER) */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_PWR_H */ + + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_rcc.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_rcc.h new file mode 100644 index 00000000000..a12be942397 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_rcc.h @@ -0,0 +1,5931 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_RCC_H +#define STM32H7RSxx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" +#include + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Constants RCC Private Constants + * @{ + */ +/* + LL_CLKSOURCE() macro output description + + 31 24 16 8 0 + -------------------------------------------------------- + | Mask | ClkSource | Bit | Register | + | | Config | Position | Offset | + -------------------------------------------------------- +*/ +#define LL_RCC_REG_SHIFT 0U +#define LL_RCC_POS_SHIFT 8U +#define LL_RCC_CONFIG_SHIFT 16U +#define LL_RCC_MASK_SHIFT 24U + +/* Clock source register offset vs CCIPR1 register */ +#define CCIPR1_OFFSET 0x0UL +#define CCIPR2_OFFSET 0x4UL +#define CCIPR3_OFFSET 0x8UL +#define CCIPR4_OFFSET 0xCUL + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +#if !defined(UNUSED) +#define UNUSED(x) ((void)(x)) +#endif /* UNUSED */ + +#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL) + +#define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) &\ + 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) + +#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) &\ + 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) + +#define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL) + +#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \ + (( __POS__ ) << LL_RCC_POS_SHIFT) | \ + (( __REG__ ) << LL_RCC_REG_SHIFT) | \ + (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT))) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; + uint32_t CPUCLK_Frequency; + uint32_t HCLK_Frequency; + uint32_t PCLK1_Frequency; + uint32_t PCLK2_Frequency; + uint32_t PCLK4_Frequency; + uint32_t PCLK5_Frequency; +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @brief PLL Clocks Frequency Structure + */ +typedef struct +{ + uint32_t PLL_P_Frequency; + uint32_t PLL_Q_Frequency; + uint32_t PLL_R_Frequency; + uint32_t PLL_S_Frequency; + uint32_t PLL_T_Frequency; +} LL_PLL_ClocksTypeDef; + +/** + * @brief PLL Spread Spectrum Mode Structure + */ +typedef struct +{ + uint16_t ModulationPeriod; /* Modulation Period (value between 0 to 2^13-1) */ + uint16_t IncrementStep; /* Modulation Depth (value between 0 to 2^15-1) */ + uint16_t SpreadMode; /* LL_RCC_PLL_SPREAD_CENTER or LL_RCC_PLL_SPREAD_DOWN */ + uint16_t DitheringRPDFN; /* Rectangular probability density function noise enable/disable */ + uint16_t DitheringTPDFN; /* Triangular probability density function noise enable/disable */ +} LL_PLL_SpreadSpectrumTypeDef; + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported variables --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Variables RCC Exported Variables + * @{ + */ +extern const uint8_t LL_RCC_PrescTable[16]; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 24000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (CSI_VALUE) +#define CSI_VALUE 4000000U /*!< Value of the CSI oscillator in Hz */ +#endif /* CSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ + +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ +#endif /* HSI48_VALUE */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider + * @{ + */ +#define LL_RCC_HSI_DIV_1 0U +#define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0 +#define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1 +#define LL_RCC_HSI_DIV_8 RCC_CR_HSIDIV +/** + * @} + */ + +/** @defgroup LL_RCC_EC_XSPI1SWP XSXPI1 kernel clock switch position + * @{ + */ +#define LL_RCC_SWP_XSPI1_NEUTRAL 0U +#define LL_RCC_SWP_XSPI1_HCLK5 RCC_CKPROTR_XSPI1SWP_0 +#define LL_RCC_SWP_XSPI1_PLL2S RCC_CKPROTR_XSPI1SWP_1 +#define LL_RCC_SWP_XSPI1_PLL2T (RCC_CKPROTR_XSPI1SWP_1 | RCC_CKPROTR_XSPI1SWP_0) +#define LL_RCC_SWP_XSPI1_HCLK_DIV4 RCC_CKPROTR_XSPI1SWP_2 +/** + * @} + */ + +/** @defgroup LL_RCC_EC_XSPI2SWP SXPI2 kernel clock switch position + * @{ + */ +#define LL_RCC_SWP_XSPI2_NEUTRAL 0U +#define LL_RCC_SWP_XSPI2_HCLK5 RCC_CKPROTR_XSPI2SWP_0 +#define LL_RCC_SWP_XSPI2_PLL2S RCC_CKPROTR_XSPI2SWP_1 +#define LL_RCC_SWP_XSPI2_PLL2T (RCC_CKPROTR_XSPI2SWP_1 | RCC_CKPROTR_XSPI2SWP_0) +#define LL_RCC_SWP_XSPI2_HCLK_DIV4 RCC_CKPROTR_XSPI2SWP_2 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_FMCSWP FMC kernel clock switch position + * @{ + */ +#define LL_RCC_SWP_FMC_NEUTRAL 0U +#define LL_RCC_SWP_FMC_HCLK5 RCC_CKPROTR_FMCSWP_0 +#define LL_RCC_SWP_FMC_PLL1Q RCC_CKPROTR_FMCSWP_1 +#define LL_RCC_SWP_FMC_PLL2R (RCC_CKPROTR_FMCSWP_1 | RCC_CKPROTR_FMCSWP_0) +#define LL_RCC_SWP_FMC_HSI RCC_CKPROTR_FMCSWP_2 +#define LL_RCC_SWP_FMC_HCLK_DIV4 (RCC_CKPROTR_FMCSWP_2 | RCC_CKPROTR_FMCSWP_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW 0U +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 +#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI 0U +#define LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR_SW_0 +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1 +#define LL_RCC_SYS_CLKSOURCE_PLL1 (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0U /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR_SWS_0 /*!< CSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< PLL1 used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE System wakeup clock source + * @{ + */ +#define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI 0U +#define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI RCC_CFGR_STOPWUCK +/** + * @} + */ + +/** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE Kernel wakeup clock source + * @{ + */ +#define LL_RCC_KERWAKEUP_CLKSOURCE_HSI 0U +#define LL_RCC_KERWAKEUP_CLKSOURCE_CSI RCC_CFGR_STOPKERWUCK +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV System prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 0U +#define LL_RCC_SYSCLK_DIV_2 RCC_CDCFGR_CPRE_3 +#define LL_RCC_SYSCLK_DIV_4 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_0) +#define LL_RCC_SYSCLK_DIV_8 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_1) +#define LL_RCC_SYSCLK_DIV_16 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_1 | RCC_CDCFGR_CPRE_0) +#define LL_RCC_SYSCLK_DIV_64 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_2) +#define LL_RCC_SYSCLK_DIV_128 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_2 | RCC_CDCFGR_CPRE_0) +#define LL_RCC_SYSCLK_DIV_256 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_2 | RCC_CDCFGR_CPRE_1) +#define LL_RCC_SYSCLK_DIV_512 RCC_CDCFGR_CPRE +/** + * @} + */ + +/** @defgroup RCC_LL_EC_AHB_DIV AHB prescaler + * @{ + */ +#define LL_RCC_AHB_DIV_1 0U +#define LL_RCC_AHB_DIV_2 RCC_BMCFGR_BMPRE_3 +#define LL_RCC_AHB_DIV_4 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_0) +#define LL_RCC_AHB_DIV_8 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_1) +#define LL_RCC_AHB_DIV_16 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_1 | RCC_BMCFGR_BMPRE_0) +#define LL_RCC_AHB_DIV_64 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_2) +#define LL_RCC_AHB_DIV_128 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_2 | RCC_BMCFGR_BMPRE_0) +#define LL_RCC_AHB_DIV_256 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_2 | RCC_BMCFGR_BMPRE_1) +#define LL_RCC_AHB_DIV_512 RCC_BMCFGR_BMPRE +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB1 prescaler + * @{ + */ +#define LL_RCC_APB1_DIV_1 0U +#define LL_RCC_APB1_DIV_2 RCC_APBCFGR_PPRE1_2 +#define LL_RCC_APB1_DIV_4 (RCC_APBCFGR_PPRE1_2 | RCC_APBCFGR_PPRE1_0) +#define LL_RCC_APB1_DIV_8 (RCC_APBCFGR_PPRE1_2 | RCC_APBCFGR_PPRE1_1) +#define LL_RCC_APB1_DIV_16 RCC_APBCFGR_PPRE1 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB2 prescaler + * @{ + */ +#define LL_RCC_APB2_DIV_1 0U +#define LL_RCC_APB2_DIV_2 RCC_APBCFGR_PPRE2_2 +#define LL_RCC_APB2_DIV_4 (RCC_APBCFGR_PPRE2_2 | RCC_APBCFGR_PPRE2_0) +#define LL_RCC_APB2_DIV_8 (RCC_APBCFGR_PPRE2_2 | RCC_APBCFGR_PPRE2_1) +#define LL_RCC_APB2_DIV_16 RCC_APBCFGR_PPRE2 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB4_DIV APB4 prescaler + * @{ + */ +#define LL_RCC_APB4_DIV_1 0U +#define LL_RCC_APB4_DIV_2 RCC_APBCFGR_PPRE4_2 +#define LL_RCC_APB4_DIV_4 (RCC_APBCFGR_PPRE4_2 | RCC_APBCFGR_PPRE4_0) +#define LL_RCC_APB4_DIV_8 (RCC_APBCFGR_PPRE4_2 | RCC_APBCFGR_PPRE4_1) +#define LL_RCC_APB4_DIV_16 RCC_APBCFGR_PPRE4 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB5_DIV APB5 prescaler + * @{ + */ +#define LL_RCC_APB5_DIV_1 0U +#define LL_RCC_APB5_DIV_2 RCC_APBCFGR_PPRE5_2 +#define LL_RCC_APB5_DIV_4 (RCC_APBCFGR_PPRE5_2 | RCC_APBCFGR_PPRE5_0) +#define LL_RCC_APB5_DIV_8 (RCC_APBCFGR_PPRE5_2 | RCC_APBCFGR_PPRE5_1) +#define LL_RCC_APB5_DIV_16 RCC_APBCFGR_PPRE5 +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_HSI ((RCC_CFGR_MCO1SEL>>16U) | 0U) +#define LL_RCC_MCO1SOURCE_LSE ((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_0) +#define LL_RCC_MCO1SOURCE_HSE ((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_1) +#define LL_RCC_MCO1SOURCE_PLL1Q ((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_1 | RCC_CFGR_MCO1SEL_0) +#define LL_RCC_MCO1SOURCE_HSI48 ((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_2) +#define LL_RCC_MCO2SOURCE_SYSCLK ((RCC_CFGR_MCO2SEL>>16U) | 0U) +#define LL_RCC_MCO2SOURCE_PLL2P ((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_0) +#define LL_RCC_MCO2SOURCE_HSE ((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_1) +#define LL_RCC_MCO2SOURCE_PLL1P ((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) +#define LL_RCC_MCO2SOURCE_CSI ((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_2) +#define LL_RCC_MCO2SOURCE_LSI ((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0) +#define LL_RCC_MCO1_DIV_2 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1) +#define LL_RCC_MCO1_DIV_3 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1) +#define LL_RCC_MCO1_DIV_4 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_5 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_6 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_7 ((RCC_CFGR_MCO1PRE>>16U) |\ + RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_8 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_9 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_10 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_11 ((RCC_CFGR_MCO1PRE>>16U) |\ + RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_12 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_13 ((RCC_CFGR_MCO1PRE>>16U) |\ + RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_14 ((RCC_CFGR_MCO1PRE>>16U) |\ + RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_15 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE) +#define LL_RCC_MCO2_DIV_1 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0) +#define LL_RCC_MCO2_DIV_2 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1) +#define LL_RCC_MCO2_DIV_3 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1) +#define LL_RCC_MCO2_DIV_4 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_5 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_6 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_7 ((RCC_CFGR_MCO2PRE>>16U) |\ + RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_8 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_9 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_10 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_11 ((RCC_CFGR_MCO2PRE>>16U) |\ + RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_12 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_13 ((RCC_CFGR_MCO2PRE>>16U) |\ + RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_14 ((RCC_CFGR_MCO2PRE>>16U) |\ + RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_15 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE) + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock + * @{ + */ +#define LL_RCC_RTC_NOCLOCK 0U +#define LL_RCC_RTC_HSE_DIV_2 (RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_4 (RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_8 (RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3 |\ + RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_16 (RCC_CFGR_RTCPRE_4) +#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4 |\ + RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4 |\ + RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4 |\ + RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4 |\ + RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4 |\ + RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_32 (RCC_CFGR_RTCPRE_5) +#define LL_RCC_RTC_HSE_DIV_33 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_34 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_35 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_36 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_37 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_38 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_39 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_40 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_41 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_42 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_43 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_44 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_45 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_46 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_47 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_48 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_4) +#define LL_RCC_RTC_HSE_DIV_49 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_50 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_51 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_52 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_53 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_54 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_55 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_56 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_57 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_58 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_59 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_60 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_61 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_62 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_63 (RCC_CFGR_RTCPRE_5 |\ + RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE_PLL2P 0U +#define LL_RCC_ADC_CLKSOURCE_PLL3R RCC_CCIPR1_ADCSEL_0 +#define LL_RCC_ADC_CLKSOURCE_CLKP RCC_CCIPR1_ADCSEL_1 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADFx_CLKSOURCE Peripheral ADF clock source selection + * @{ + */ +#define LL_RCC_ADF1_CLKSOURCE_HCLK 0U +#define LL_RCC_ADF1_CLKSOURCE_PLL2P RCC_CCIPR1_ADF1SEL_0 +#define LL_RCC_ADF1_CLKSOURCE_PLL3P RCC_CCIPR1_ADF1SEL_1 +#define LL_RCC_ADF1_CLKSOURCE_I2S_CKIN (RCC_CCIPR1_ADF1SEL_1 | RCC_CCIPR1_ADF1SEL_0) +#define LL_RCC_ADF1_CLKSOURCE_CSI RCC_CCIPR1_ADF1SEL_2 +#define LL_RCC_ADF1_CLKSOURCE_HSI (RCC_CCIPR1_ADF1SEL_2 | RCC_CCIPR1_ADF1SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE_LSE 0U +#define LL_RCC_CEC_CLKSOURCE_LSI RCC_CCIPR2_CECSEL_0 +#define LL_RCC_CEC_CLKSOURCE_CSI_DIV_122 RCC_CCIPR2_CECSEL_1 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP clock source selection + * @{ + */ +#define LL_RCC_CLKP_CLKSOURCE_HSI 0U +#define LL_RCC_CLKP_CLKSOURCE_CSI RCC_CCIPR1_CKPERSEL_0 +#define LL_RCC_CLKP_CLKSOURCE_HSE RCC_CCIPR1_CKPERSEL_1 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ETHxPHY_CLKSOURCE Peripheral ETHPHY clock source selection + * @{ + */ +#define LL_RCC_ETH1PHY_CLKSOURCE_HSE 0U +#define LL_RCC_ETH1PHY_CLKSOURCE_PLL3S RCC_CCIPR1_ETH1PHYCKSEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ETHxREF_CLKSOURCE Peripheral ETHREF clock source selection + * @{ + */ +#define LL_RCC_ETH1REF_CLKSOURCE_RMII 0U +#define LL_RCC_ETH1REF_CLKSOURCE_HSE RCC_CCIPR1_ETH1REFCKSEL_0 +#define LL_RCC_ETH1REF_CLKSOURCE_FB RCC_CCIPR1_ETH1REFCKSEL_1 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection + * @{ + */ +#define LL_RCC_FDCAN_CLKSOURCE_HSE 0U +#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q RCC_CCIPR2_FDCANSEL_0 +#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q RCC_CCIPR2_FDCANSEL_1 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC clock source selection + * @{ + */ +#define LL_RCC_FMC_CLKSOURCE_HCLK 0U +#define LL_RCC_FMC_CLKSOURCE_PLL1Q RCC_CCIPR1_FMCSEL_0 +#define LL_RCC_FMC_CLKSOURCE_PLL2R RCC_CCIPR1_FMCSEL_1 +#define LL_RCC_FMC_CLKSOURCE_HSI (RCC_CCIPR1_FMCSEL_1 | RCC_CCIPR1_FMCSEL_0) +#define LL_RCC_FMC_CLKSOURCE_HCLK_DIV4 LL_RCC_SWP_FMC_HCLK_DIV4 /* Recovery: Read-only */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C1_I3C1SEL, RCC_CCIPR2_I2C1_I3C1SEL_Pos, 0U) +#define LL_RCC_I2C1_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C1_I3C1SEL, RCC_CCIPR2_I2C1_I3C1SEL_Pos, RCC_CCIPR2_I2C1_I3C1SEL_0) +#define LL_RCC_I2C1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C1_I3C1SEL, RCC_CCIPR2_I2C1_I3C1SEL_Pos, RCC_CCIPR2_I2C1_I3C1SEL_1) +#define LL_RCC_I2C1_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C1_I3C1SEL, RCC_CCIPR2_I2C1_I3C1SEL_Pos, RCC_CCIPR2_I2C1_I3C1SEL_1 |\ + RCC_CCIPR2_I2C1_I3C1SEL_0) + +#define LL_RCC_I2C23_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C23SEL, RCC_CCIPR2_I2C23SEL_Pos, 0U) +#define LL_RCC_I2C23_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C23SEL, RCC_CCIPR2_I2C23SEL_Pos, RCC_CCIPR2_I2C23SEL_0) +#define LL_RCC_I2C23_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C23SEL, RCC_CCIPR2_I2C23SEL_Pos, RCC_CCIPR2_I2C23SEL_1) +#define LL_RCC_I2C23_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C23SEL, RCC_CCIPR2_I2C23SEL_Pos, RCC_CCIPR2_I2C23SEL_1 |\ + RCC_CCIPR2_I2C23SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I3Cx_CLKSOURCE Peripheral I3C clock source selection + * @{ + */ +#define LL_RCC_I3C1_CLKSOURCE_PCLK1 0U +#define LL_RCC_I3C1_CLKSOURCE_PLL3R RCC_CCIPR2_I2C1_I3C1SEL_0 +#define LL_RCC_I3C1_CLKSOURCE_HSI RCC_CCIPR2_I2C1_I3C1SEL_1 +#define LL_RCC_I3C1_CLKSOURCE_CSI (RCC_CCIPR2_I2C1_I3C1SEL_1 | RCC_CCIPR2_I2C1_I3C1SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0U) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_0) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_1) +#define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_1 |\ + RCC_CCIPR2_LPTIM1SEL_0) +#define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_2) +#define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_2 |\ + RCC_CCIPR2_LPTIM1SEL_0) + +#define LL_RCC_LPTIM23_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM23SEL, RCC_CCIPR4_LPTIM23SEL_Pos, 0U) +#define LL_RCC_LPTIM23_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM23SEL, RCC_CCIPR4_LPTIM23SEL_Pos, RCC_CCIPR4_LPTIM23SEL_0) +#define LL_RCC_LPTIM23_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM23SEL, RCC_CCIPR4_LPTIM23SEL_Pos, RCC_CCIPR4_LPTIM23SEL_1) +#define LL_RCC_LPTIM23_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM23SEL, RCC_CCIPR4_LPTIM23SEL_Pos, RCC_CCIPR4_LPTIM23SEL_1 |\ + RCC_CCIPR4_LPTIM23SEL_0) +#define LL_RCC_LPTIM23_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM23SEL, RCC_CCIPR4_LPTIM23SEL_Pos, RCC_CCIPR4_LPTIM23SEL_2) +#define LL_RCC_LPTIM23_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM23SEL, RCC_CCIPR4_LPTIM23SEL_Pos, RCC_CCIPR4_LPTIM23SEL_2 |\ + RCC_CCIPR4_LPTIM23SEL_0) + +#define LL_RCC_LPTIM45_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM45SEL, RCC_CCIPR4_LPTIM45SEL_Pos, 0U) +#define LL_RCC_LPTIM45_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM45SEL, RCC_CCIPR4_LPTIM45SEL_Pos, RCC_CCIPR4_LPTIM45SEL_0) +#define LL_RCC_LPTIM45_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM45SEL, RCC_CCIPR4_LPTIM45SEL_Pos, RCC_CCIPR4_LPTIM45SEL_1) +#define LL_RCC_LPTIM45_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM45SEL, RCC_CCIPR4_LPTIM45SEL_Pos, RCC_CCIPR4_LPTIM45SEL_1 |\ + RCC_CCIPR4_LPTIM45SEL_0) +#define LL_RCC_LPTIM45_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM45SEL, RCC_CCIPR4_LPTIM45SEL_Pos, RCC_CCIPR4_LPTIM45SEL_2) +#define LL_RCC_LPTIM45_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM45SEL, RCC_CCIPR4_LPTIM45SEL_Pos, RCC_CCIPR4_LPTIM45SEL_2 |\ + RCC_CCIPR4_LPTIM45SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE_PCLK4 0U +#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q RCC_CCIPR4_LPUART1SEL_0 +#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q RCC_CCIPR4_LPUART1SEL_1 +#define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_CCIPR4_LPUART1SEL_1 | RCC_CCIPR4_LPUART1SEL_0) +#define LL_RCC_LPUART1_CLKSOURCE_CSI RCC_CCIPR4_LPUART1SEL_2 +#define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_CCIPR4_LPUART1SEL_2 | RCC_CCIPR4_LPUART1SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE_PLL3R 0U +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PSSI_CLKSOURCE Peripheral PSSI clock source selection + * @{ + */ +#define LL_RCC_PSSI_CLKSOURCE_PLL3R 0U +#define LL_RCC_PSSI_CLKSOURCE_CLKP RCC_CCIPR1_PSSISEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection + * @{ + */ +#define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI1SEL, RCC_CCIPR3_SAI1SEL_Pos, 0U) +#define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI1SEL, RCC_CCIPR3_SAI1SEL_Pos, RCC_CCIPR3_SAI1SEL_0) +#define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI1SEL, RCC_CCIPR3_SAI1SEL_Pos, RCC_CCIPR3_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI1SEL, RCC_CCIPR3_SAI1SEL_Pos, RCC_CCIPR3_SAI1SEL_0 |\ + RCC_CCIPR3_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI1SEL, RCC_CCIPR3_SAI1SEL_Pos, RCC_CCIPR3_SAI1SEL_2) + +#define LL_RCC_SAI2_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI2SEL, RCC_CCIPR3_SAI2SEL_Pos, 0U) +#define LL_RCC_SAI2_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI2SEL, RCC_CCIPR3_SAI2SEL_Pos, RCC_CCIPR3_SAI2SEL_0) +#define LL_RCC_SAI2_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI2SEL, RCC_CCIPR3_SAI2SEL_Pos, RCC_CCIPR3_SAI2SEL_1) +#define LL_RCC_SAI2_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI2SEL, RCC_CCIPR3_SAI2SEL_Pos, RCC_CCIPR3_SAI2SEL_1 |\ + RCC_CCIPR3_SAI2SEL_0) +#define LL_RCC_SAI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI2SEL, RCC_CCIPR3_SAI2SEL_Pos, RCC_CCIPR3_SAI2SEL_2) +#define LL_RCC_SAI2_CLKSOURCE_SPDIFRX LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI2SEL, RCC_CCIPR3_SAI2SEL_Pos, RCC_CCIPR3_SAI1SEL_2 |\ + RCC_CCIPR3_SAI2SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMC clock source selection + * @{ + */ +#define LL_RCC_SDMMC_CLKSOURCE_PLL2S 0U +#define LL_RCC_SDMMC_CLKSOURCE_PLL2T RCC_CCIPR1_SDMMC12SEL +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE Peripheral SPDIF clock source selection + * @{ + */ +#define LL_RCC_SPDIFRX_CLKSOURCE_PLL1Q 0U +#define LL_RCC_SPDIFRX_CLKSOURCE_PLL2R RCC_CCIPR2_SPDIFRXSEL_0 +#define LL_RCC_SPDIFRX_CLKSOURCE_PLL3R RCC_CCIPR2_SPDIFRXSEL_1 +#define LL_RCC_SPDIFRX_CLKSOURCE_HSI (RCC_CCIPR2_SPDIFRXSEL_0 | RCC_CCIPR2_SPDIFRXSEL_1) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE Peripheral SPI clock source selection + * @{ + */ +#define LL_RCC_SPI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, 0U) +#define LL_RCC_SPI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_0) +#define LL_RCC_SPI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_1) +#define LL_RCC_SPI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_1 |\ + RCC_CCIPR3_SPI1SEL_0) +#define LL_RCC_SPI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_2) + +#define LL_RCC_SPI23_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_SPI23SEL, RCC_CCIPR2_SPI23SEL_Pos, 0U) +#define LL_RCC_SPI23_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_SPI23SEL, RCC_CCIPR2_SPI23SEL_Pos, RCC_CCIPR2_SPI23SEL_0) +#define LL_RCC_SPI23_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_SPI23SEL, RCC_CCIPR2_SPI23SEL_Pos, RCC_CCIPR2_SPI23SEL_1) +#define LL_RCC_SPI23_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_SPI23SEL, RCC_CCIPR2_SPI23SEL_Pos, RCC_CCIPR2_SPI23SEL_1 |\ + RCC_CCIPR2_SPI23SEL_0) +#define LL_RCC_SPI23_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_SPI23SEL, RCC_CCIPR2_SPI23SEL_Pos, RCC_CCIPR2_SPI23SEL_2) + +#define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI45SEL, RCC_CCIPR3_SPI45SEL_Pos, 0U) +#define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI45SEL, RCC_CCIPR3_SPI45SEL_Pos, RCC_CCIPR3_SPI45SEL_0) +#define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI45SEL, RCC_CCIPR3_SPI45SEL_Pos, RCC_CCIPR3_SPI45SEL_1) +#define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI45SEL, RCC_CCIPR3_SPI45SEL_Pos, RCC_CCIPR3_SPI45SEL_1 |\ + RCC_CCIPR3_SPI45SEL_0) +#define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI45SEL, RCC_CCIPR3_SPI45SEL_Pos, RCC_CCIPR3_SPI45SEL_2) +#define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI45SEL, RCC_CCIPR3_SPI45SEL_Pos, RCC_CCIPR3_SPI45SEL_2 |\ + RCC_CCIPR3_SPI45SEL_0) + +#define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SPI6SEL, RCC_CCIPR4_SPI6SEL_Pos, 0U) +#define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SPI6SEL, RCC_CCIPR4_SPI6SEL_Pos, RCC_CCIPR4_SPI6SEL_0) +#define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SPI6SEL, RCC_CCIPR4_SPI6SEL_Pos, RCC_CCIPR4_SPI6SEL_1) +#define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SPI6SEL, RCC_CCIPR4_SPI6SEL_Pos, RCC_CCIPR4_SPI6SEL_1 |\ + RCC_CCIPR4_SPI6SEL_0) +#define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SPI6SEL, RCC_CCIPR4_SPI6SEL_Pos, RCC_CCIPR4_SPI6SEL_2) +#define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SPI6SEL, RCC_CCIPR4_SPI6SEL_Pos, RCC_CCIPR4_SPI6SEL_2 |\ + RCC_CCIPR4_SPI6SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_USART1SEL, RCC_CCIPR3_USART1SEL_Pos, 0U) +#define LL_RCC_USART1_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_USART1SEL, RCC_CCIPR3_USART1SEL_Pos, RCC_CCIPR3_USART1SEL_0) +#define LL_RCC_USART1_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_USART1SEL, RCC_CCIPR3_USART1SEL_Pos, RCC_CCIPR3_USART1SEL_1) +#define LL_RCC_USART1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_USART1SEL, RCC_CCIPR3_USART1SEL_Pos, RCC_CCIPR3_USART1SEL_1 |\ + RCC_CCIPR3_USART1SEL_0) +#define LL_RCC_USART1_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_USART1SEL, RCC_CCIPR3_USART1SEL_Pos, RCC_CCIPR3_USART1SEL_2) +#define LL_RCC_USART1_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_USART1SEL, RCC_CCIPR3_USART1SEL_Pos, RCC_CCIPR3_USART1SEL_2 |\ + RCC_CCIPR3_USART1SEL_0) + +#define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART234578SEL, RCC_CCIPR2_UART234578SEL_Pos, 0U) +#define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART234578SEL, RCC_CCIPR2_UART234578SEL_Pos, RCC_CCIPR2_UART234578SEL_0) +#define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART234578SEL, RCC_CCIPR2_UART234578SEL_Pos, RCC_CCIPR2_UART234578SEL_1) +#define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART234578SEL, RCC_CCIPR2_UART234578SEL_Pos, RCC_CCIPR2_UART234578SEL_1 |\ + RCC_CCIPR2_UART234578SEL_0) +#define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART234578SEL, RCC_CCIPR2_UART234578SEL_Pos, RCC_CCIPR2_UART234578SEL_2) +#define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART234578SEL, RCC_CCIPR2_UART234578SEL_Pos, RCC_CCIPR2_UART234578SEL_2 |\ + RCC_CCIPR2_UART234578SEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_OTGFS_CLKSOURCE Peripheral OTGFS kernel clock source selection + * @{ + */ +#define LL_RCC_OTGFS_CLKSOURCE_HSI48 0U +#define LL_RCC_OTGFS_CLKSOURCE_PLL3Q RCC_CCIPR1_OTGFSSEL_0 +#define LL_RCC_OTGFS_CLKSOURCE_HSE RCC_CCIPR1_OTGFSSEL_1 +#define LL_RCC_OTGFS_CLKSOURCE_CLK48 (RCC_CCIPR1_OTGFSSEL_1 | RCC_CCIPR1_OTGFSSEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USBPHYC_CLKSOURCE Peripheral USBPHYC kernel clock source selection + * @{ + */ +#define LL_RCC_USBPHYC_CLKSOURCE_HSE 0U +#define LL_RCC_USBPHYC_CLKSOURCE_HSE_DIV_2 RCC_CCIPR1_USBPHYCSEL_0 +#define LL_RCC_USBPHYC_CLKSOURCE_PLL3Q RCC_CCIPR1_USBPHYCSEL_1 +#define LL_RCC_USBPHYC_CLKSOURCE_DISABLE (RCC_CCIPR1_USBPHYCSEL_1 | RCC_CCIPR1_USBPHYCSEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USBREF_CLKSOURCE Peripheral USBREF clock source selection + * @{ + */ +#define LL_RCC_USBREF_CLKSOURCE_16M (RCC_CCIPR1_USBREFCKSEL_1 | RCC_CCIPR1_USBREFCKSEL_0) +#define LL_RCC_USBREF_CLKSOURCE_19_2M RCC_CCIPR1_USBREFCKSEL_3 +#define LL_RCC_USBREF_CLKSOURCE_20M (RCC_CCIPR1_USBREFCKSEL_3 | RCC_CCIPR1_USBREFCKSEL_0) +#define LL_RCC_USBREF_CLKSOURCE_24M (RCC_CCIPR1_USBREFCKSEL_3 | RCC_CCIPR1_USBREFCKSEL_1) +#define LL_RCC_USBREF_CLKSOURCE_26M (RCC_CCIPR1_USBREFCKSEL_3 |\ + RCC_CCIPR1_USBREFCKSEL_2 | RCC_CCIPR1_USBREFCKSEL_1) +#define LL_RCC_USBREF_CLKSOURCE_32M (RCC_CCIPR1_USBREFCKSEL_3 |\ + RCC_CCIPR1_USBREFCKSEL_1 | RCC_CCIPR1_USBREFCKSEL_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_XSPI_CLKSOURCE Peripheral XSPI clock source selection + * @{ + */ +#define LL_RCC_XSPI1_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI1SEL, RCC_CCIPR1_XSPI1SEL_Pos, 0U) +#define LL_RCC_XSPI1_CLKSOURCE_PLL2S LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI1SEL, RCC_CCIPR1_XSPI1SEL_Pos, RCC_CCIPR1_XSPI1SEL_0) +#define LL_RCC_XSPI1_CLKSOURCE_PLL2T LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI1SEL, RCC_CCIPR1_XSPI1SEL_Pos, RCC_CCIPR1_XSPI1SEL_1) +#define LL_RCC_XSPI1_CLKSOURCE_HCLK_DIV4 LL_RCC_SWP_XSPI1_HCLK_DIV4 /* Recovery: Read-only */ + +#define LL_RCC_XSPI2_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI2SEL, RCC_CCIPR1_XSPI2SEL_Pos, 0U) +#define LL_RCC_XSPI2_CLKSOURCE_PLL2S LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI2SEL, RCC_CCIPR1_XSPI2SEL_Pos, RCC_CCIPR1_XSPI2SEL_0) +#define LL_RCC_XSPI2_CLKSOURCE_PLL2T LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI2SEL, RCC_CCIPR1_XSPI2SEL_Pos, RCC_CCIPR1_XSPI2SEL_1) +#define LL_RCC_XSPI2_CLKSOURCE_HCLK_DIV4 LL_RCC_SWP_XSPI2_HCLK_DIV4 /* Recovery: Read-only */ +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_ADC_CLKSOURCE + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR1_ADCSEL +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_ADFx_CLKSOURCE + * @{ + */ +#define LL_RCC_ADF1_CLKSOURCE RCC_CCIPR1_ADF1SEL +/** + * @} + */ + + +/** @addtogroup RCC_LL_EC_CEC_CLKSOURCE + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE RCC_CCIPR2_CECSEL +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_CLKP_CLKSOURCE + * @{ + */ +#define LL_RCC_CLKP_CLKSOURCE RCC_CCIPR1_CKPERSEL +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_ETHxPHY_CLKSOURCE + * @{ + */ +#define LL_RCC_ETH1PHY_CLKSOURCE RCC_CCIPR1_ETH1PHYCKSEL +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_ETHxREF_CLKSOURCE + * @{ + */ +#define LL_RCC_ETH1REF_CLKSOURCE RCC_CCIPR1_ETH1REFCKSEL +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_FDCAN_CLKSOURCE + * @{ + */ +#define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR2_FDCANSEL +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_FMC_CLKSOURCE + * @{ + */ +#define LL_RCC_FMC_CLKSOURCE RCC_CCIPR1_FMCSEL +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_I2Cx_CLKSOURCE + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C1_I3C1SEL, RCC_CCIPR2_I2C1_I3C1SEL_Pos, 0U) +#define LL_RCC_I2C23_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C23SEL, RCC_CCIPR2_I2C23SEL_Pos, 0U) +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_I3Cx_CLKSOURCE + * @{ + */ +#define LL_RCC_I3C1_CLKSOURCE RCC_CCIPR2_I2C1_I3C1SEL +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_LPTIMx_CLKSOURCE + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0U) +#define LL_RCC_LPTIM23_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM23SEL, RCC_CCIPR4_LPTIM23SEL_Pos, 0U) +#define LL_RCC_LPTIM45_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM45SEL, RCC_CCIPR4_LPTIM45SEL_Pos, 0U) +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_LPUARTx_CLKSOURCE + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR4_LPUART1SEL +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_OTGFS_CLKSOURCE + * @{ + */ +#define LL_RCC_OTGFS_CLKSOURCE RCC_CCIPR1_OTGFSSEL +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_PSSI_CLKSOURCE + * @{ + */ +#define LL_RCC_PSSI_CLKSOURCE RCC_CCIPR1_PSSISEL +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_SAIx_CLKSOURCE + * @{ + */ +#define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI1SEL, RCC_CCIPR3_SAI1SEL_Pos, 0U) +#define LL_RCC_SAI2_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI2SEL, RCC_CCIPR3_SAI2SEL_Pos, 0U) +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_SDMMC_CLKSOURCE + * @{ + */ +#define LL_RCC_SDMMC_CLKSOURCE RCC_CCIPR1_SDMMC12SEL +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_SPDIFRX_CLKSOURCE + * @{ + */ +#define LL_RCC_SPDIFRX_CLKSOURCE RCC_CCIPR2_SPDIFRXSEL +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_SPIx_CLKSOURCE + * @{ + */ +#define LL_RCC_SPI1_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, 0U) +#define LL_RCC_SPI23_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_SPI23SEL, RCC_CCIPR2_SPI23SEL_Pos, 0U) +#define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI45SEL, RCC_CCIPR3_SPI45SEL_Pos, 0U) +#define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SPI6SEL, RCC_CCIPR4_SPI6SEL_Pos, 0U) +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_USARTx_CLKSOURCE + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_USART1SEL, RCC_CCIPR3_USART1SEL_Pos, 0U) +#define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART234578SEL, RCC_CCIPR2_UART234578SEL_Pos, 0U) +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_USBPHYC_CLKSOURCE + * @{ + */ +#define LL_RCC_USBPHYC_CLKSOURCE RCC_CCIPR1_USBPHYCSEL +/** + * @} + */ + +/** @addtogroup RCC_LL_EC_USBREF_CLKSOURCE + * @{ + */ +#define LL_RCC_USBREF_CLKSOURCE RCC_CCIPR1_USBREFCKSEL +/** + * @} + */ + + +/** @addtogroup RCC_LL_EC_XSPIx_CLKSOURCE + * @{ + */ +#define LL_RCC_XSPI1_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI1SEL, RCC_CCIPR1_XSPI1SEL_Pos, 0U) +#define LL_RCC_XSPI2_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI2SEL, RCC_CCIPR1_XSPI2SEL_Pos, 0U) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0U +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 +#define LL_RCC_RTC_CLKSOURCE_HSE (RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection + * @{ + */ +#define LL_RCC_TIM_PRESCALER_DISABLE 0U +#define LL_RCC_TIM_PRESCALER_ENABLE RCC_CFGR_TIMPRE +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSOURCE All PLLs entry clock source + * @{ + */ +#define LL_RCC_PLLSOURCE_HSI 0U +#define LL_RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_0 +#define LL_RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_1 +#define LL_RCC_PLLSOURCE_NONE (RCC_PLLCKSELR_PLLSRC_1 | RCC_PLLCKSELR_PLLSRC_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input range + * @{ + */ +#define LL_RCC_PLLINPUTRANGE_1_2 0U +#define LL_RCC_PLLINPUTRANGE_2_4 RCC_PLLCFGR_PLL1RGE_0 +#define LL_RCC_PLLINPUTRANGE_4_8 RCC_PLLCFGR_PLL1RGE_1 +#define LL_RCC_PLLINPUTRANGE_8_16 (RCC_PLLCFGR_PLL1RGE_1 | RCC_PLLCFGR_PLL1RGE_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLVCORANGE All PLLs VCO range + * @{ + */ +#define LL_RCC_PLLVCORANGE_WIDE 0U /*!< VCO output range: 400 to 1600 MHz */ +#define LL_RCC_PLLVCORANGE_MEDIUM RCC_PLLCFGR_PLL1VCOSEL /*!< VCO output range: 150 to 420 MHz */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_SPREAD_SEL PLL Spread Spectrum Selection + * @{ + */ +#define LL_RCC_PLL_SPREAD_CENTER 0U /*!< PLL center spread spectrum selection */ +#define LL_RCC_PLL_SPREAD_DOWN RCC_PLL1SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_DITHERING_TPDFN PLL Dithering TPDF Noise Control + * @{ + */ +#define LL_RCC_PLL_DITHERING_TPDFN_ENABLE 0U /*!< PLL Dithering TPDF Noise injection enabled */ +#define LL_RCC_PLL_DITHERING_TPDFN_DISABLE RCC_PLL1SSCGR_TPDFNDIS /*!< PLL Dithering TPDF Noise injection disabled */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_DITHERING_RPDFN PLL Dithering RPDF Noise Control + * @{ + */ +#define LL_RCC_PLL_DITHERING_RPDFN_ENABLE 0U /*!< PLL Dithering RPDF Noise injection enabled */ +#define LL_RCC_PLL_DITHERING_RPDFN_DISABLE RCC_PLL1SSCGR_RPDFNDIS /*!< PLL Dithering RPDF Noise injection disabled */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the SYSCLK frequency + * @param __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P) + * @param __SYSPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval SYSCLK clock frequency (in Hz) + */ +#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) &\ + RCC_CDCFGR_CPRE) >> RCC_CDCFGR_CPRE_Pos]) & 0x1FU)) + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency. + * @param __HPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_AHB_DIV_1 + * @arg @ref LL_RCC_AHB_DIV_2 + * @arg @ref LL_RCC_AHB_DIV_4 + * @arg @ref LL_RCC_AHB_DIV_8 + * @arg @ref LL_RCC_AHB_DIV_16 + * @arg @ref LL_RCC_AHB_DIV_64 + * @arg @ref LL_RCC_AHB_DIV_128 + * @arg @ref LL_RCC_AHB_DIV_256 + * @arg @ref LL_RCC_AHB_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) &\ + RCC_BMCFGR_BMPRE) >> RCC_BMCFGR_BMPRE_Pos]) & 0x1FU)) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) &\ + RCC_APBCFGR_PPRE1) >> RCC_APBCFGR_PPRE1_Pos]) & 0x1FU)) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) &\ + RCC_APBCFGR_PPRE2) >> RCC_APBCFGR_PPRE2_Pos]) & 0x1FU)) + +/** + * @brief Helper macro to calculate the PCLK4 frequency (ABP4) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB4PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB4_DIV_1 + * @arg @ref LL_RCC_APB4_DIV_2 + * @arg @ref LL_RCC_APB4_DIV_4 + * @arg @ref LL_RCC_APB4_DIV_8 + * @arg @ref LL_RCC_APB4_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) &\ + RCC_APBCFGR_PPRE4) >> RCC_APBCFGR_PPRE4_Pos]) & 0x1FU)) + +/** + * @brief Helper macro to calculate the PCLK5 frequency (APB5) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB5PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB5_DIV_1 + * @arg @ref LL_RCC_APB5_DIV_2 + * @arg @ref LL_RCC_APB5_DIV_4 + * @arg @ref LL_RCC_APB5_DIV_8 + * @arg @ref LL_RCC_APB5_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define LL_RCC_CALC_PCLK5_FREQ(__HCLKFREQ__, __APB5PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB5PRESCALER__) &\ + RCC_APBCFGR_PPRE5) >> RCC_APBCFGR_PPRE5_Pos]) & 0x1FU)) + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless + * a reset occurs or system enter in standby mode. + * @rmtoll CR HSECSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSECSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Select the Analog HSE external clock type in Bypass mode + * @rmtoll CR HSEEXT LL_RCC_HSE_SelectAnalogClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); +} + +/** + * @brief Select the Digital HSE external clock type in Bypass mode + * @rmtoll CR HSEEXT LL_RCC_HSE_SelectDigitalClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEEXT); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI new divider applied and ready + * @rmtoll CR HSIDIVF LL_RCC_HSI_IsDividerReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == RCC_CR_HSIDIVF) ? 1UL : 0UL); +} + +/** + * @brief Set HSI divider + * @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @retval None. + */ +__STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider); +} + +/** + * @brief Get HSI divider + * @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider + * @retval can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIDIV)); +} + +/** + * @brief Enable HSI oscillator in Stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_EnableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Disable HSI oscillator in Stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_DisableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Check if HSI oscillator in Stop mode has been enabled or not + * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledStopMode(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL); +} + +/** + * @brief Enable XSPI clock protection + * @rmtoll CKPROTR XSPICKP LL_RCC_EnableXSPIClockProtection + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableXSPIClockProtection(void) +{ + SET_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPICKP); +} + +/** + * @brief Disable XSPI clock protection + * @rmtoll CKPROTR XSPICKP LL_RCC_DisableXSPIClockProtection + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableXSPIClockProtection(void) +{ + CLEAR_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPICKP); +} + +/** + * @brief Check if XSPI clock protection has been enabled or not + * @rmtoll CKPROTR XSPICKP LL_RCC_IsEnabledXSPIClockProtection + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledXSPIClockProtection(void) +{ + return ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPICKP) == (RCC_CKPROTR_XSPICKP)) ? 1UL : 0UL); +} + +/** + * @brief Enable FMC clock protection + * @rmtoll CKPROTR FMCCKP LL_RCC_EnableFMCClockProtection + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableFMCClockProtection(void) +{ + SET_BIT(RCC->CKPROTR, RCC_CKPROTR_FMCCKP); +} + +/** + * @brief Disable FMC clock protection + * @rmtoll CKPROTR FMCCKP LL_RCC_DisableFMCClockProtection + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableFMCClockProtection(void) +{ + CLEAR_BIT(RCC->CKPROTR, RCC_CKPROTR_FMCCKP); +} + +/** + * @brief Check if FMC clock protection has been enabled or not + * @rmtoll CKPROTR FMCCKP LL_RCC_IsEnabledFMCClockProtection + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledFMCClockProtection(void) +{ + return ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_FMCCKP) == (RCC_CKPROTR_FMCCKP)) ? 1UL : 0UL); +} + +/** + * @brief Get XSPI2 kernel clock switch position + * @rmtoll CKPROTR XSPI2SWP LL_RCC_GetXSPI2SwitchPosition + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SWP_XSPI2_NEUTRAL + @arg @ref LL_RCC_SWP_XSPI2_HCLK5 + @arg @ref LL_RCC_SWP_XSPI2_PLL2S + @arg @ref LL_RCC_SWP_XSPI2_PLL2T + @arg @ref LL_RCC_SWP_XSPI2_HCLK_DIV4 + */ +__STATIC_INLINE uint32_t LL_RCC_GetXSPI2SwitchPosition(void) +{ + return (READ_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPI2SWP)); +} + +/** + * @brief Get XSPI1 kernel clock switch position + * @rmtoll CKPROTR XSPI1SWP LL_RCC_GetXSPI1SwitchPosition + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SWP_XSPI1_NEUTRAL + @arg @ref LL_RCC_SWP_XSPI1_HCLK5 + @arg @ref LL_RCC_SWP_XSPI1_PLL2S + @arg @ref LL_RCC_SWP_XSPI1_PLL2T + @arg @ref LL_RCC_SWP_XSPI1_HCLK_DIV4 + */ +__STATIC_INLINE uint32_t LL_RCC_GetXSPI1SwitchPosition(void) +{ + return (READ_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPI1SWP)); +} + +/** + * @brief Get FMC kernel clock switch position + * @rmtoll CKPROTR FMCSWP LL_RCC_GetFMCSwitchPosition + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SWP_FMC_NEUTRAL + @arg @ref LL_RCC_SWP_FMC_HCLK5 + @arg @ref LL_RCC_SWP_FMC_PLL1Q + @arg @ref LL_RCC_SWP_FMC_PLL2R + @arg @ref LL_RCC_SWP_FMC_HSI + @arg @ref LL_RCC_SWP_FMC_HCLK_DIV4 + */ +__STATIC_INLINE uint32_t LL_RCC_GetFMCSwitchPosition(void) +{ + return (READ_BIT(RCC->CKPROTR, RCC_CKPROTR_FMCSWP)); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll HSICFGR HSICAL LL_RCC_HSI_GetCalibration + * @retval A value between 0 and 4095 (0xFFF) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 64, which, when added to the HSICAL value, + * should trim the HSI to 64 MHz +/- 1 % + * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value Parameter can be a value between 0 and 127 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval A value between 0 and 127 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_CSI CSI + * @{ + */ + +/** + * @brief Enable CSI oscillator + * @rmtoll CR CSION LL_RCC_CSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSION); +} + +/** + * @brief Disable CSI oscillator + * @rmtoll CR CSION LL_RCC_CSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSION); +} + +/** + * @brief Check if CSI clock is ready + * @rmtoll CR CSIRDY LL_RCC_CSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == RCC_CR_CSIRDY) ? 1UL : 0UL); +} + +/** + * @brief Enable CSI oscillator in Stop mode + * @rmtoll CR CSIKERON LL_RCC_CSI_EnableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSIKERON); +} + +/** + * @brief Disable CSI oscillator in Stop mode + * @rmtoll CR CSIKERON LL_RCC_CSI_DisableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON); +} + +/** + * @brief Check if CSI oscillator in Stop mode has been enabled or not + * @rmtoll CR CSIKERON LL_RCC_CSI_IsEnabledStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_IsEnabledStopMode(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_CSIKERON) == (RCC_CR_CSIKERON)) ? 1UL : 0UL); +} + +/** + * @brief Get CSI Calibration value + * @note When CSITRIM is written, CSICAL is updated with the sum of + * CSITRIM and the factory trim value + * @rmtoll CSICFGR CSICAL LL_RCC_CSI_GetCalibration + * @retval A value between 0 and 255 (0xFF) + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos); +} + +/** + * @brief Set CSI Calibration trimming + * @note user-programmable trimming value that is added to the CSICAL + * @note Default value is 16, which, when added to the CSICAL value, + * should trim the CSI to 4 MHz +/- 1 % + * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_SetCalibTrimming + * @param Value can be a value between 0 and 31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos); +} + +/** + * @brief Get CSI Calibration trimming + * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_GetCalibTrimming + * @retval A value between 0 and 31 + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI48 HSI48 + * @{ + */ + +/** + * @brief Enable HSI48 oscillator + * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Disable HSI48 oscillator + * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Check if HSI48 clock is ready + * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL); +} + +/** + * @brief Get HSI48 Calibration value + * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of + * HSI48TRIM and the factory trim value + * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration + * @retval A value between 0 and 1023 (0x3FF) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); +} +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable the Clock Security System on LSE. + * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless + * a clock failure is detected. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Disable the Clock Security System on LSE. + * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless + * a clock failure is detected. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Check if LSE failure is detected by Clock Security System + * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsFailureDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL); +} + +/** + * @brief Re-arm the Clock Security System on LSE. + * @note Once a clock failure is detected, the LSE Clock Security System can be re-armed providing that + * LSECSSON is disabled. + * @rmtoll BDCR LSECSSRA LL_RCC_LSE_ReArmCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_ReArmCSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSRA); +} + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active). + * @note The external clock must be enabled with the LSEON bit, to be used by the device. + * The LSEEXT bit can be written only if the LSE oscillator is disabled. + * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectDigitalClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); +} + +/** + * @brief Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset). + * @note The external clock must be enabled with the LSEON bit, to be used by the device. + * The LSEEXT bit can be written only if the LSE oscillator is disabled. + * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectAnalogClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_CSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Configure the system wakeup clock source + * @rmtoll CFGR STOPWUCK LL_RCC_SetSysWakeUpClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source); +} + +/** + * @brief Get the system wakeup clock source + * @rmtoll CFGR STOPWUCK LL_RCC_GetSysWakeUpClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK)); +} + +/** + * @brief Configure the kernel wakeup clock source + * @rmtoll CFGR STOPKERWUCK LL_RCC_SetKerWakeUpClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source); +} + +/** + * @brief Get the kernel wakeup clock source + * @rmtoll CFGR STOPKERWUCK LL_RCC_GetKerWakeUpClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK)); +} + +/** + * @brief Set System prescaler + * @rmtoll CDCFGR CPRE LL_RCC_SetSysPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CDCFGR, RCC_CDCFGR_CPRE, Prescaler); +} + +/** + * @brief Set AHB prescaler + * @rmtoll BMCFGR BMPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_AHB_DIV_1 + * @arg @ref LL_RCC_AHB_DIV_2 + * @arg @ref LL_RCC_AHB_DIV_4 + * @arg @ref LL_RCC_AHB_DIV_8 + * @arg @ref LL_RCC_AHB_DIV_16 + * @arg @ref LL_RCC_AHB_DIV_64 + * @arg @ref LL_RCC_AHB_DIV_128 + * @arg @ref LL_RCC_AHB_DIV_256 + * @arg @ref LL_RCC_AHB_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->BMCFGR, RCC_BMCFGR_BMPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll APBCFGR PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE1, Prescaler); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll APBCFGR PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE2, Prescaler); +} + +/** + * @brief Set APB4 prescaler + * @rmtoll APBCFGR PPRE4 LL_RCC_SetAPB4Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB4_DIV_1 + * @arg @ref LL_RCC_APB4_DIV_2 + * @arg @ref LL_RCC_APB4_DIV_4 + * @arg @ref LL_RCC_APB4_DIV_8 + * @arg @ref LL_RCC_APB4_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE4, Prescaler); +} + +/** + * @brief Set APB5 prescaler + * @rmtoll APBCFGR PPRE5 LL_RCC_SetAPB5Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB5_DIV_1 + * @arg @ref LL_RCC_APB5_DIV_2 + * @arg @ref LL_RCC_APB5_DIV_4 + * @arg @ref LL_RCC_APB5_DIV_8 + * @arg @ref LL_RCC_APB5_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB5Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE5, Prescaler); +} + +/** + * @brief Get System prescaler + * @rmtoll CDCFGR CPRE LL_RCC_GetSysPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CDCFGR, RCC_CDCFGR_CPRE)); +} + +/** + * @brief Get AHB prescaler + * @rmtoll BMCFGR BMPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_AHB_DIV_1 + * @arg @ref LL_RCC_AHB_DIV_2 + * @arg @ref LL_RCC_AHB_DIV_4 + * @arg @ref LL_RCC_AHB_DIV_8 + * @arg @ref LL_RCC_AHB_DIV_16 + * @arg @ref LL_RCC_AHB_DIV_64 + * @arg @ref LL_RCC_AHB_DIV_128 + * @arg @ref LL_RCC_AHB_DIV_256 + * @arg @ref LL_RCC_AHB_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->BMCFGR, RCC_BMCFGR_BMPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll APBCFGR PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->APBCFGR, RCC_APBCFGR_PPRE1)); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll APBCFGR PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->APBCFGR, RCC_APBCFGR_PPRE2)); +} + +/** + * @brief Get APB4 prescaler + * @rmtoll APBCFGR PPRE4 LL_RCC_GetAPB4Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB4_DIV_1 + * @arg @ref LL_RCC_APB4_DIV_2 + * @arg @ref LL_RCC_APB4_DIV_4 + * @arg @ref LL_RCC_APB4_DIV_8 + * @arg @ref LL_RCC_APB4_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->APBCFGR, RCC_APBCFGR_PPRE4)); +} + +/** + * @brief Get APB5 prescaler + * @rmtoll APBCFGR PPRE5 LL_RCC_GetAPB5Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB5_DIV_1 + * @arg @ref LL_RCC_APB5_DIV_2 + * @arg @ref LL_RCC_APB5_DIV_4 + * @arg @ref LL_RCC_APB5_DIV_8 + * @arg @ref LL_RCC_APB5_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB5Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->APBCFGR, RCC_APBCFGR_PPRE5)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCO1SEL LL_RCC_ConfigMCO\n + * CFGR MCO1PRE LL_RCC_ConfigMCO\n + * CFGR MCO2SEL LL_RCC_ConfigMCO\n + * CFGR MCO2PRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLL1Q + * @arg @ref LL_RCC_MCO1SOURCE_HSI48 + * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO2SOURCE_PLL2P + * @arg @ref LL_RCC_MCO2SOURCE_HSE + * @arg @ref LL_RCC_MCO2SOURCE_PLL1P + * @arg @ref LL_RCC_MCO2SOURCE_CSI + * @arg @ref LL_RCC_MCO2SOURCE_LSI + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_3 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_5 + * @arg @ref LL_RCC_MCO1_DIV_6 + * @arg @ref LL_RCC_MCO1_DIV_7 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_9 + * @arg @ref LL_RCC_MCO1_DIV_10 + * @arg @ref LL_RCC_MCO1_DIV_11 + * @arg @ref LL_RCC_MCO1_DIV_12 + * @arg @ref LL_RCC_MCO1_DIV_13 + * @arg @ref LL_RCC_MCO1_DIV_14 + * @arg @ref LL_RCC_MCO1_DIV_15 + * @arg @ref LL_RCC_MCO2_DIV_1 + * @arg @ref LL_RCC_MCO2_DIV_2 + * @arg @ref LL_RCC_MCO2_DIV_3 + * @arg @ref LL_RCC_MCO2_DIV_4 + * @arg @ref LL_RCC_MCO2_DIV_5 + * @arg @ref LL_RCC_MCO2_DIV_6 + * @arg @ref LL_RCC_MCO2_DIV_7 + * @arg @ref LL_RCC_MCO2_DIV_8 + * @arg @ref LL_RCC_MCO2_DIV_9 + * @arg @ref LL_RCC_MCO2_DIV_10 + * @arg @ref LL_RCC_MCO2_DIV_11 + * @arg @ref LL_RCC_MCO2_DIV_12 + * @arg @ref LL_RCC_MCO2_DIV_13 + * @arg @ref LL_RCC_MCO2_DIV_14 + * @arg @ref LL_RCC_MCO2_DIV_15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure periph clock source + * @rmtoll CCIPR1 * LL_RCC_SetClockSource\n + * CCIPR2 * LL_RCC_SetClockSource\n + * CCIPR3 * LL_RCC_SetClockSource\n + * CCIPR4 * LL_RCC_SetClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C23_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C23_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C23_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C23_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI23_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI23_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2S + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2T + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2S + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2T + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource) +{ + volatile uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CCIPR1 + LL_CLKSOURCE_REG(ClkSource)); + MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource)); +} + +/** + * @brief Configure ADCx Kernel clock source + * @rmtoll CCIPR1 ADCSEL LL_RCC_SetADCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADCSEL, ClkSource); +} + +/** + * @brief Configure ADFx Kernel clock source + * @rmtoll CCIPR1 ADF1SEL LL_RCC_SetADFClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_ADF1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_ADF1_CLKSOURCE_CSI + * @arg @ref LL_RCC_ADF1_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADFClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADF1SEL, ClkSource); +} + +/** + * @brief Configure CECx clock source + * @rmtoll CCIPR2 CECSEL LL_RCC_SetCECClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI + * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV_122 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_CECSEL, ClkSource); +} + +/** + * @brief Configure CLKP Kernel clock source + * @rmtoll CCIPR1 CKPERSEL LL_RCC_SetCLKPClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CKPERSEL, ClkSource); +} + +/** + * @brief Configure ETHx PHY clock source + * @rmtoll CCIPR1 ETH1PHYCKSEL LL_RCC_SetETHPHYClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1PHY_CLKSOURCE_HSE + * @arg @ref LL_RCC_ETH1PHY_CLKSOURCE_PLL3S + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetETHPHYClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ETH1PHYCKSEL, ClkSource); +} + +/** + * @brief Configure ETHx REF clock source + * @rmtoll CCIPR1 ETH1REFCKSEL LL_RCC_SetETHREFClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_RMII + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_HSE + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_FB + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetETHREFClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ETH1REFCKSEL, ClkSource); +} + +/** + * @brief Configure FDCANx Kernel clock source + * @rmtoll CCIPR2 FDCANSEL LL_RCC_SetFDCANClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, ClkSource); +} + +/** + * @brief Configure FMCx Kernel clock source + * @rmtoll CCIPR1 FMCSEL LL_RCC_SetFMCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_FMC_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FMCSEL, ClkSource); +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll CCIPR2 I2C1_I3C1SEL LL_RCC_SetI2CClockSource + * @rmtoll CCIPR2 I2C23SEL LL_RCC_SetI2CClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C23_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C23_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C23_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C23_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure I3Cx clock source + * @rmtoll CCIPR2 I2C1_I3C1SEL LL_RCC_SetI3CClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I3C1_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI3CClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C1_I3C1SEL, ClkSource); +} + +/** + * @brief Configure LPTIMx clock source + * @rmtoll CCIPR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource\n + * CCIPR4 LPTIM23SEL LL_RCC_SetLPTIMClockSource\n + * CCIPR4 LPTIM45SEL LL_RCC_SetLPTIMClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure LPUARTx clock source + * @rmtoll CCIPR4 LPUART1SEL LL_RCC_SetLPUARTClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_LPUART1SEL, ClkSource); +} + +/** + * @brief Configure OTGFSx clock source + * @rmtoll CCIPR1 OTGFSSEL LL_RCC_SetOTGFSClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_CLK48 + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_HSE + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_PLL3Q + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOTGFSClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_OTGFSSEL, ClkSource); +} + +/** + * @brief Configure XSPIx Kernel clock source + * @rmtoll CCIPR1 XSPI1SEL LL_RCC_SetXSPIClockSource\n + * CCIPR1 XSPI2SEL LL_RCC_SetXSPIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2S + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2T + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2S + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2T + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetXSPIClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure PSSI clock source + * @rmtoll CCIPR1 PSSISEL LL_RCC_SetPSSIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PSSI_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_PSSI_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetPSSIClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_PSSISEL, ClkSource); +} + +/** + * @brief Configure SAIx clock source + * @rmtoll CCIPR3 SAI1SEL LL_RCC_SetSAIClockSource\n + * CCIPR3 SAI2SEL LL_RCC_SetSAIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure SDMMCx clock source + * @rmtoll CCIPR1 SDMMCSEL LL_RCC_SetSDMMCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2S + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2T + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SDMMC12SEL, ClkSource); +} + +/** + * @brief Configure SPDIFRX Kernel clock source + * @rmtoll CCIPR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SPDIFRXSEL, ClkSource); +} + +/** + * @brief Configure SPIx Kernel clock source + * @rmtoll CCIPR3 SPI1SEL LL_RCC_SetSPIClockSource\n + * CCIPR2 SPI23SEL LL_RCC_SetSPIClockSource\n + * CCIPR3 SPI45SEL LL_RCC_SetSPIClockSource\n + * CCIPR4 SPI6SEL LL_RCC_SetSPIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI23_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI23_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure USARTx clock source + * @rmtoll CCIPR3 USART1SEL LL_RCC_SetUSARTClockSource\n + * CCIPR2 UART234578SEL LL_RCC_SetUSARTClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure USBPHYC clock source + * @rmtoll CCIPR1 USBPHYCSEL LL_RCC_SetUSBPHYCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_DISABLE + * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_HSE + * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_PLL3Q + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBPHYCClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USBPHYCSEL, ClkSource); +} + +/** + * @brief Configure USBREF clock source + * @rmtoll CCIPR1 USBREFCKSEL LL_RCC_SetUSBREFClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USBREF_CLKSOURCE_16M + * @arg @ref LL_RCC_USBREF_CLKSOURCE_19_2M + * @arg @ref LL_RCC_USBREF_CLKSOURCE_20M + * @arg @ref LL_RCC_USBREF_CLKSOURCE_24M + * @arg @ref LL_RCC_USBREF_CLKSOURCE_26M + * @arg @ref LL_RCC_USBREF_CLKSOURCE_32M + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBREFClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USBREFCKSEL, ClkSource); +} + +/** + * @brief Get periph clock source + * @rmtoll CCIPR1 * LL_RCC_GetClockSource\n + * CCIPR2 * LL_RCC_GetClockSource\n + * CCIPR3 * LL_RCC_GetClockSource\n + * CCIPR4 * LL_RCC_GetClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C23_CLKSOURCE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @arg @ref LL_RCC_SAI2_CLKSOURCE + * @arg @ref LL_RCC_SPI1_CLKSOURCE + * @arg @ref LL_RCC_SPI23_CLKSOURCE + * @arg @ref LL_RCC_SPI45_CLKSOURCE + * @arg @ref LL_RCC_SPI6_CLKSOURCE + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART234578_CLKSOURCE + * @arg @ref LL_RCC_XSPI1_CLKSOURCE + * @arg @ref LL_RCC_XSPI2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C23_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C23_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C23_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C23_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI23_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI23_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2S + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2T + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2S + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2T + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph) +{ + const volatile uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CCIPR1) + LL_CLKSOURCE_REG(Periph))); + return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT)); +} + +/** + * @brief Get ADC Kernel clock source + * @rmtoll CCIPR1 ADCSEL LL_RCC_GetADCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADCSEL)); +} + +/** + * @brief Get ADF clock source + * @rmtoll CCIPR1 ADF1SEL LL_RCC_GetADFClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ADF1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_ADF1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_ADF1_CLKSOURCE_CSI + * @arg @ref LL_RCC_ADF1_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetADFClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADF1SEL)); +} + +/** + * @brief Get CEC clock source + * @rmtoll CCIPR2 CECSEL LL_RCC_GetCECClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI + * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV_122 + */ +__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_CECSEL)); +} + +/** + * @brief Get CLKP Kernel clock source + * @rmtoll CCIPR1 CKPERSEL LL_RCC_GetCLKPClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CKPERSEL)); +} + +/** + * @brief Get ETH PHY clock source + * @rmtoll CCIPR1 ETH1PHYCKSEL LL_RCC_GetETHPHYClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1PHY_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ETH1PHY_CLKSOURCE_HSE + * @arg @ref LL_RCC_ETH1PHY_CLKSOURCE_PLL3S + */ +__STATIC_INLINE uint32_t LL_RCC_GetETHPHYClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ETH1PHYCKSEL)); +} + +/** + * @brief Get ETH REF clock source + * @rmtoll CCIPR1 ETH1REFCKSEL LL_RCC_GetETHREFClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_RMII + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_HSE + * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_FB + */ +__STATIC_INLINE uint32_t LL_RCC_GetETHREFClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ETH1REFCKSEL)); +} + +/** + * @brief Get FDCAN Kernel clock source + * @rmtoll CCIPR2 FDCANSEL LL_RCC_GetFDCANClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q + */ +__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL)); +} + +/** + * @brief Get FMC Kernel clock source + * @rmtoll CCIPR1 FMCSEL LL_RCC_GetFMCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_FMC_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FMCSEL)); +} + +/** + * @brief Get I2Cx clock source + * @rmtoll CCIPR2 I2C1_I3C1SEL LL_RCC_GetI2CClockSource + * @rmtoll CCIPR2 I2C23SEL LL_RCC_GetI2CClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C23_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C23_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C23_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C23_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C23_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get I3Cx clock source + * @rmtoll CCIPR2 I2C1_I3C1SEL LL_RCC_GetI3CClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_I3C1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I3C1_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetI3CClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C1_I3C1SEL)); +} + +/** + * @brief Get LPTIM clock source + * @rmtoll CCIPR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource\n + * CCIPR4 LPTIM23SEL LL_RCC_GetLPTIMClockSource\n + * CCIPR4 LPTIM45SEL LL_RCC_GetLPTIMClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get LPUART clock source + * @rmtoll CCIPR4 LPUART1SEL LL_RCC_GetLPUARTClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_LPUART1SEL)); +} + +/** + * @brief Get OTGFS clock source + * @rmtoll CCIPR1 OTGFSSEL LL_RCC_GetOTGFSClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGFS_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_HSE + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_CLK48 + */ +__STATIC_INLINE uint32_t LL_RCC_GetOTGFSClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_OTGFSSEL)); +} + +/** + * @brief Get XSPI Kernel clock source + * @rmtoll CCIPR1 XSPI1SEL LL_RCC_GetXSPIClockSource\n + * CCIPR1 XSPI2SEL LL_RCC_GetXSPIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_XSPI1_CLKSOURCE + * @arg @ref LL_RCC_XSPI2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2S + * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2T + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2S + * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2T + */ +__STATIC_INLINE uint32_t LL_RCC_GetXSPIClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get PSSI clock source + * @rmtoll CCIPR1 PSSISEL LL_RCC_GetPSSIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_PSSI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PSSI_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_PSSI_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetPSSIClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_PSSISEL)); +} + +/** + * @brief Get SAIx clock source + * @rmtoll CCIPR3 SAI1SEL LL_RCC_GetSAIClockSource\n + * CCIPR3 SAI2SEL LL_RCC_GetSAIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @arg @ref LL_RCC_SAI2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX + */ +__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get SDMMC clock source + * @rmtoll CCIPR1 SDMMCSEL LL_RCC_GetSDMMCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2S + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2T + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SDMMC12SEL)); +} + +/** + * @brief Get SPDIFRX Kernel clock source + * @rmtoll CCIPR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SPDIFRXSEL)); +} + +/** + * @brief Get SPIx Kernel clock source + * @rmtoll CCIPR3 SPI1SEL LL_RCC_GetSPIClockSource\n + * CCIPR2 SPI23SEL LL_RCC_GetSPIClockSource\n + * CCIPR3 SPI45SEL LL_RCC_GetSPIClockSource\n + * CCIPR4 SPI6SEL LL_RCC_GetSPIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE + * @arg @ref LL_RCC_SPI23_CLKSOURCE + * @arg @ref LL_RCC_SPI45_CLKSOURCE + * @arg @ref LL_RCC_SPI6_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI23_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI23_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get USARTx clock source + * @rmtoll CCIPR3 USART1SEL LL_RCC_GetUSARTClockSource\n + * CCIPR2 UART234578SEL LL_RCC_GetUSARTClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART234578_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get USBPHYC clock source + * @rmtoll CCIPR1 USBPHYCSEL LL_RCC_GetUSBPHYCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USBPHYC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_DISABLE + * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_HSE + * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_PLL3Q + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBPHYCClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USBPHYCSEL)); +} + +/** + * @brief Configure USBREF clock frequency + * @rmtoll CCIPR1 USBREFCKSEL LL_RCC_GetUSBREFClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USBREF_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USBREF_CLKSOURCE_16M + * @arg @ref LL_RCC_USBREF_CLKSOURCE_19_2M + * @arg @ref LL_RCC_USBREF_CLKSOURCE_20M + * @arg @ref LL_RCC_USBREF_CLKSOURCE_24M + * @arg @ref LL_RCC_USBREF_CLKSOURCE_26M + * @arg @ref LL_RCC_USBREF_CLKSOURCE_32M + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBREFClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USBREFCKSEL)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR VSWRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR VSWRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST); +} + +/** + * @brief Set HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + * @arg @ref LL_RCC_RTC_HSE_DIV_32 + * @arg @ref LL_RCC_RTC_HSE_DIV_33 + * @arg @ref LL_RCC_RTC_HSE_DIV_34 + * @arg @ref LL_RCC_RTC_HSE_DIV_35 + * @arg @ref LL_RCC_RTC_HSE_DIV_36 + * @arg @ref LL_RCC_RTC_HSE_DIV_37 + * @arg @ref LL_RCC_RTC_HSE_DIV_38 + * @arg @ref LL_RCC_RTC_HSE_DIV_39 + * @arg @ref LL_RCC_RTC_HSE_DIV_40 + * @arg @ref LL_RCC_RTC_HSE_DIV_41 + * @arg @ref LL_RCC_RTC_HSE_DIV_42 + * @arg @ref LL_RCC_RTC_HSE_DIV_43 + * @arg @ref LL_RCC_RTC_HSE_DIV_44 + * @arg @ref LL_RCC_RTC_HSE_DIV_45 + * @arg @ref LL_RCC_RTC_HSE_DIV_46 + * @arg @ref LL_RCC_RTC_HSE_DIV_47 + * @arg @ref LL_RCC_RTC_HSE_DIV_48 + * @arg @ref LL_RCC_RTC_HSE_DIV_49 + * @arg @ref LL_RCC_RTC_HSE_DIV_50 + * @arg @ref LL_RCC_RTC_HSE_DIV_51 + * @arg @ref LL_RCC_RTC_HSE_DIV_52 + * @arg @ref LL_RCC_RTC_HSE_DIV_53 + * @arg @ref LL_RCC_RTC_HSE_DIV_54 + * @arg @ref LL_RCC_RTC_HSE_DIV_55 + * @arg @ref LL_RCC_RTC_HSE_DIV_56 + * @arg @ref LL_RCC_RTC_HSE_DIV_57 + * @arg @ref LL_RCC_RTC_HSE_DIV_58 + * @arg @ref LL_RCC_RTC_HSE_DIV_59 + * @arg @ref LL_RCC_RTC_HSE_DIV_60 + * @arg @ref LL_RCC_RTC_HSE_DIV_61 + * @arg @ref LL_RCC_RTC_HSE_DIV_62 + * @arg @ref LL_RCC_RTC_HSE_DIV_63 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); +} + +/** + * @brief Get HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + * @arg @ref LL_RCC_RTC_HSE_DIV_32 + * @arg @ref LL_RCC_RTC_HSE_DIV_33 + * @arg @ref LL_RCC_RTC_HSE_DIV_34 + * @arg @ref LL_RCC_RTC_HSE_DIV_35 + * @arg @ref LL_RCC_RTC_HSE_DIV_36 + * @arg @ref LL_RCC_RTC_HSE_DIV_37 + * @arg @ref LL_RCC_RTC_HSE_DIV_38 + * @arg @ref LL_RCC_RTC_HSE_DIV_39 + * @arg @ref LL_RCC_RTC_HSE_DIV_40 + * @arg @ref LL_RCC_RTC_HSE_DIV_41 + * @arg @ref LL_RCC_RTC_HSE_DIV_42 + * @arg @ref LL_RCC_RTC_HSE_DIV_43 + * @arg @ref LL_RCC_RTC_HSE_DIV_44 + * @arg @ref LL_RCC_RTC_HSE_DIV_45 + * @arg @ref LL_RCC_RTC_HSE_DIV_46 + * @arg @ref LL_RCC_RTC_HSE_DIV_47 + * @arg @ref LL_RCC_RTC_HSE_DIV_48 + * @arg @ref LL_RCC_RTC_HSE_DIV_49 + * @arg @ref LL_RCC_RTC_HSE_DIV_50 + * @arg @ref LL_RCC_RTC_HSE_DIV_51 + * @arg @ref LL_RCC_RTC_HSE_DIV_52 + * @arg @ref LL_RCC_RTC_HSE_DIV_53 + * @arg @ref LL_RCC_RTC_HSE_DIV_54 + * @arg @ref LL_RCC_RTC_HSE_DIV_55 + * @arg @ref LL_RCC_RTC_HSE_DIV_56 + * @arg @ref LL_RCC_RTC_HSE_DIV_57 + * @arg @ref LL_RCC_RTC_HSE_DIV_58 + * @arg @ref LL_RCC_RTC_HSE_DIV_59 + * @arg @ref LL_RCC_RTC_HSE_DIV_60 + * @arg @ref LL_RCC_RTC_HSE_DIV_61 + * @arg @ref LL_RCC_RTC_HSE_DIV_62 + * @arg @ref LL_RCC_RTC_HSE_DIV_63 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM + * @{ + */ + +/** + * @brief Set Timers Clock Prescalers + * @rmtoll CFGR TIMPRE LL_RCC_SetTIMPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_DISABLE + * @arg @ref LL_RCC_TIM_PRESCALER_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler); +} + +/** + * @brief Get Timers Clock Prescalers + * @rmtoll CFGR TIMPRE LL_RCC_GetTIMPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_DISABLE + * @arg @ref LL_RCC_TIM_PRESCALER_ENABLE + */ +__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_USBPHYC USBPHYC + * @{ + */ + +/** + * @brief Enable USBPHYC power-down + * @rmtoll AHB1LPENR UCPDCTRL LL_RCC_USBPHYC_EnablePowerDown + * @retval None + */ +__STATIC_INLINE void LL_RCC_USBPHYC_EnablePowerDown(void) +{ + SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_UCPDCTRL); +} + +/** + * @brief Disable USBPHYC power-down + * @rmtoll AHB1LPENR UCPDCTRL LL_RCC_USBPHYC_DisablePowerDown + * @retval None + */ +__STATIC_INLINE void LL_RCC_USBPHYC_DisablePowerDown(void) +{ + CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_UCPDCTRL); +} + +/** + * @brief Check if USBPHYC is powered-down + * @rmtoll AHB1LPENR UCPDCTRL LL_RCC_USBPHYC_IsEnabledPowerDown + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_USBPHYC_IsEnabledPowerDown(void) +{ + return ((READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_UCPDCTRL) == (RCC_AHB1LPENR_UCPDCTRL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Set the oscillator used as PLL clock source. + * @note PLL clock source is common to all PLLs. + * @note PLLSRC can be written only when all PLLs are disabled. + * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_SetSource + * @param PLLSource parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_CSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_CSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_NONE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC)); +} + +/** + * @brief Enable PLL1 + * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL1ON); +} + +/** + * @brief Disable PLL1 + * @note Cannot be disabled if the PLL1 clock is used as the system clock + * @rmtoll CR PLL1ON LL_RCC_PLL1_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); +} + +/** + * @brief Check if PLL1 Ready + * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY)) ? 1UL : 0UL); +} + +/** + * @brief Configure PLL1 used for SYSCLK Domain + * @note PLL Source, DIVM1, DIVN and DIVP can be written only when PLL is disabled. + * @note PLLN/PLLR can be written only when PLL is disabled. + * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL1_ConfigDomain_SYS\n + * PLLCKSELR DIVM1 LL_RCC_PLL1_ConfigDomain_SYS\n + * PLL1DIVR1 DIVN LL_RCC_PLL1_ConfigDomain_SYS\n + * PLL1DIVR1 DIVP LL_RCC_PLL1_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_CSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @param M parameter can be a value between 1 and 64 + * @param N parameter can be a value between 8 to 420 + * @param P parameter can be a value between 2 and 128 (odd division factor not supported) + * + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source, uint32_t M, uint32_t N, uint32_t P) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1 | RCC_PLLCKSELR_PLLSRC, + (M << RCC_PLLCKSELR_DIVM1_Pos) | Source); + MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVP | RCC_PLL1DIVR1_DIVN, + ((P - 1UL) << RCC_PLL1DIVR1_DIVP_Pos) | ((N - 1UL) << RCC_PLL1DIVR1_DIVN_Pos)); +} + +/** + * @brief Enable PLL1P + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1PEN LL_RCC_PLL1P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1P_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1PEN); +} + +/** + * @brief Enable PLL1Q + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1QEN LL_RCC_PLL1Q_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1Q_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1QEN); +} + +/** + * @brief Enable PLL1R + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1REN LL_RCC_PLL1R_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1R_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1REN); +} + +/** + * @brief Enable PLL1S + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1SEN LL_RCC_PLL1S_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1S_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SEN); +} + +/** + * @brief Enable PLL1 FRACN + * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN); +} + +/** + * @brief Check if PLL1 P is enabled + * @rmtoll PLLCFGR PLL1PEN LL_RCC_PLL1P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1PEN) == RCC_PLLCFGR_PLL1PEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 Q is enabled + * @rmtoll PLLCFGR PLL1QEN LL_RCC_PLL1Q_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1QEN) == RCC_PLLCFGR_PLL1QEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 R is enabled + * @rmtoll PLLCFGR PLL1REN LL_RCC_PLL1R_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1REN) == RCC_PLLCFGR_PLL1REN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 S is enabled + * @rmtoll PLLCFGR PLL1SEN LL_RCC_PLL1S_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1S_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SEN) == RCC_PLLCFGR_PLL1SEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 FRACN is enabled + * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL1P + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1PEN LL_RCC_PLL1P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1P_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1PEN); +} + +/** + * @brief Disable PLL1Q + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1QEN LL_RCC_PLL1Q_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1Q_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1QEN); +} + +/** + * @brief Disable PLL1R + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1REN LL_RCC_PLL1R_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1R_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1REN); +} + +/** + * @brief Disable PLL1S + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1SEN LL_RCC_PLL1S_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1S_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SEN); +} + +/** + * @brief Disable PLL1 FRACN + * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN); +} + +/** + * @brief Get PLL1 VCO Input Range + * @rmtoll PLLCFGR PLL1RGE LL_RCC_PLL1_GetVCOInputRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetVCOInputRange(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE)); +} + +/** + * @brief Get PLL1 VCO OutputRange + * @rmtoll PLLCFGR PLL1VCOSEL LL_RCC_PLL1_GetVCOOutputRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetVCOOutputRange(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL)); +} + +/** + * @brief Set PLL1 VCO Input Range + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange); +} + +/** + * @brief Set PLL1 VCO OutputRange + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1VCOSEL LL_RCC_PLL1_SetVCOOutputRange + * @param VCORange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange); +} + +/** + * @brief Get PLL1 N Coefficient + * @rmtoll PLL1DIVR1 DIVN LL_RCC_PLL1_GetN + * @retval A value between 8 and 420 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVN) >> RCC_PLL1DIVR1_DIVN_Pos) + 1UL); +} + +/** + * @brief Get PLL1 M Coefficient + * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_GetM + * @retval A value between 0 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos); +} + +/** + * @brief Get PLL1 P Coefficient + * @rmtoll PLL1DIVR1 DIVP LL_RCC_PLL1_GetP + * @retval A value between 2 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1UL); +} + +/** + * @brief Get PLL1 Q Coefficient + * @rmtoll PLL1DIVR1 DIVQ LL_RCC_PLL1_GetQ + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVQ) >> RCC_PLL1DIVR1_DIVQ_Pos) + 1UL); +} + +/** + * @brief Get PLL1 R Coefficient + * @rmtoll PLL1DIVR1 DIVR LL_RCC_PLL1_GetR + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVR) >> RCC_PLL1DIVR1_DIVR_Pos) + 1UL); +} + +/** + * @brief Get PLL1 S Coefficient + * @rmtoll PLL1DIVR2 DIVS LL_RCC_PLL1_GetS + * @retval A value between 1 and 8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetS(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR2, RCC_PLL1DIVR2_DIVS) >> RCC_PLL1DIVR2_DIVS_Pos) + 1UL); +} + +/** + * @brief Get PLL1 FRACN Coefficient + * @rmtoll PLL1FRACR FRACN LL_RCC_PLL1_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN) >> RCC_PLL1FRACR_FRACN_Pos); +} + +/** + * @brief Set PLL1 N Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR1 DIVN LL_RCC_PLL1_SetN + * @param N parameter can be a value between 8 and 420 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVN, (N - 1UL) << RCC_PLL1DIVR1_DIVN_Pos); +} + +/** + * @brief Set PLL1 M Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_SetM + * @param M parameter can be a value between 1 and 64 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos); +} + +/** + * @brief Set PLL1 P Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR1 DIVP LL_RCC_PLL1_SetP + * @param P parameter can be a value between 2 and 128 (odd division factor not supported) + */ +__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P) +{ + MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVP, (P - 1UL) << RCC_PLL1DIVR1_DIVP_Pos); +} + +/** + * @brief Set PLL1 Q Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR1 DIVQ LL_RCC_PLL1_SetQ + * @param Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q) +{ + MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVQ, (Q - 1UL) << RCC_PLL1DIVR1_DIVQ_Pos); +} + +/** + * @brief Set PLL1 R Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR1 DIVR LL_RCC_PLL1_SetR + * @param R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R) +{ + MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVR, (R - 1UL) << RCC_PLL1DIVR1_DIVR_Pos); +} + +/** + * @brief Set PLL1 S Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR2 DIVS LL_RCC_PLL1_SetS + * @param S parameter can be a value between 1 and 8 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetS(uint32_t S) +{ + MODIFY_REG(RCC->PLL1DIVR2, RCC_PLL1DIVR2_DIVS, (S - 1UL) << RCC_PLL1DIVR2_DIVS_Pos); +} + +/** + * @brief Set PLL1 FRACN Coefficient + * @rmtoll PLL1FRACR FRACN LL_RCC_PLL1_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN, FRACN << RCC_PLL1FRACR_FRACN_Pos); +} + +/** + * @brief Enable Spread Spectrum for PLL1. + * @note Configuration to be done with LL_RCC_PLL1_ConfigSpreadSpectrum + * @rmtoll PLLCFGR PLL1SSCGEN LL_RCC_PLL1_EnableSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_EnableSpreadSpectrum(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SSCGEN); +} + +/** + * @brief Disable Spread Spectrum for PLL1. + * @rmtoll PLLCFGR PLL1SSCGEN LL_RCC_PLL1_DisableSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_DisableSpreadSpectrum(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SSCGEN); +} + +/** + * @brief Check if Spread Spectrum for PLL1 is enabled + * @rmtoll PLLCFGR PLL1SSCGEN LL_RCC_PLL1_IsEnabledSpreadSpectrum + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledSpreadSpectrum(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SSCGEN) == RCC_PLLCFGR_PLL1SSCGEN) ? 1UL : 0UL); +} + +/** + * @brief Get Spread Spectrum Modulation Period for PLL1 + * @rmtoll PLL1SSCGR MODPER LL_RCC_PLL1_GetModulationPeriod + * @retval Between Min_Data=0 and Max_Data=8191 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetModulationPeriod(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1SSCGR, RCC_PLL1SSCGR_MODPER)); +} + +/** + * @brief Get Spread Spectrum Increment Step for PLL1 + * @rmtoll PLL1SSCGR INCSTEP LL_RCC_PLL1_GetIncrementStep + * @retval Between Min_Data=0 and Max_Data=32767 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetIncrementStep(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1SSCGR, RCC_PLL1SSCGR_INCSTEP) >> RCC_PLL1SSCGR_INCSTEP_Pos); +} + +/** + * @brief Get Spread Spectrum Selection for PLL1 + * @rmtoll PLL1SSCGR SPREADSEL LL_RCC_PLL1_GetSpreadSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL_SPREAD_CENTER + * @arg @ref LL_RCC_PLL_SPREAD_DOWN + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetSpreadSelection(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1SSCGR, RCC_PLL1SSCGR_SPREADSEL)); +} + +/** + * @brief Check if Dithering RPDF Noise for PLL1 is enabled + * @rmtoll PLL1SSCGR RPDFNDIS LL_RCC_PLL1_IsEnabledRPDFNDithering + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledRPDFNDithering(void) +{ + return ((READ_BIT(RCC->PLL1SSCGR, RCC_PLL1SSCGR_RPDFNDIS) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Check if Dithering TPDF Noise for PLL1 is enabled + * @rmtoll PLL1SSCGR TPDFNDIS LL_RCC_PLL1_IsEnabledTPDFNDithering + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledTPDFNDithering(void) +{ + return ((READ_BIT(RCC->PLL1SSCGR, RCC_PLL1SSCGR_TPDFNDIS) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL2 + * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Disable PLL2 + * @note Cannot be disabled if the PLL2 clock is used as the system clock + * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Check if PLL2 Ready + * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == RCC_CR_PLL2RDY) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL2P + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2PEN LL_RCC_PLL2P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2P_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2PEN); +} + +/** + * @brief Enable PLL2Q + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2QEN LL_RCC_PLL2Q_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2Q_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2QEN); +} + +/** + * @brief Enable PLL2R + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2REN LL_RCC_PLL2R_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2R_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2REN); +} + +/** + * @brief Enable PLL2S + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2SEN LL_RCC_PLL2S_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2S_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2SEN); +} + +/** + * @brief Enable PLL2T + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2TEN LL_RCC_PLL2T_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2T_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2TEN); +} + +/** + * @brief Enable PLL2 FRACN + * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN); +} + +/** + * @brief Check if PLL2 P is enabled + * @rmtoll PLLCFGR PLL2PEN LL_RCC_PLL2P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2PEN) == RCC_PLLCFGR_PLL2PEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 Q is enabled + * @rmtoll PLLCFGR PLL2QEN LL_RCC_PLL2Q_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2QEN) == RCC_PLLCFGR_PLL2QEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 R is enabled + * @rmtoll PLLCFGR PLL2REN LL_RCC_PLL2R_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2REN) == RCC_PLLCFGR_PLL2REN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 S is enabled + * @rmtoll PLLCFGR PLL2SEN LL_RCC_PLL2S_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2S_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2SEN) == RCC_PLLCFGR_PLL2SEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 T is enabled + * @rmtoll PLLCFGR PLL2TEN LL_RCC_PLL2T_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2T_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2TEN) == RCC_PLLCFGR_PLL2TEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 FRACN is enabled + * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL2P + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2PEN LL_RCC_PLL2P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2P_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2PEN); +} + +/** + * @brief Disable PLL2Q + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2QEN LL_RCC_PLL2Q_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2Q_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2QEN); +} + +/** + * @brief Disable PLL2R + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2REN LL_RCC_PLL2R_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2R_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2REN); +} + +/** + * @brief Disable PLL2S + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2SEN LL_RCC_PLL2S_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2S_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2SEN); +} + +/** + * @brief Disable PLL2T + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2TEN LL_RCC_PLL2T_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2T_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2TEN); +} + +/** + * @brief Disable PLL2 FRACN + * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN); +} + +/** + * @brief Get PLL2 VCO Input Range + * @rmtoll PLLCFGR PLL2RGE LL_RCC_PLL2_GetVCOInputRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetVCOInputRange(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE) >> 11U); +} + +/** + * @brief Get PLL2 VCO OutputRange + * @rmtoll PLLCFGR PLL2VCOSEL LL_RCC_PLL2_GetVCOOutputRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetVCOOutputRange(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL) >> 11U); +} + +/** + * @brief Set PLL2 VCO Input Range + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (InputRange << 11U)); +} + +/** + * @brief Set PLL2 VCO OutputRange + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2VCOSEL LL_RCC_PLL2_SetVCOOutputRange + * @param VCORange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (VCORange << 11U)); +} + +/** + * @brief Get PLL2 N Coefficient + * @rmtoll PLL2DIVR1 DIVN LL_RCC_PLL2_GetN + * @retval A value between 8 and 420 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVN) >> RCC_PLL2DIVR1_DIVN_Pos) + 1UL); +} + +/** + * @brief Get PLL2 M Coefficient + * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_GetM + * @retval A value between 0 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos); +} + +/** + * @brief Get PLL2 P Coefficient + * @rmtoll PLL2DIVR1 DIVP LL_RCC_PLL2_GetP + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVP) >> RCC_PLL2DIVR1_DIVP_Pos) + 1UL); +} + +/** + * @brief Get PLL2 Q Coefficient + * @rmtoll PLL2DIVR1 DIVQ LL_RCC_PLL2_GetQ + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVQ) >> RCC_PLL2DIVR1_DIVQ_Pos) + 1UL); +} + +/** + * @brief Get PLL2 R Coefficient + * @rmtoll PLL2DIVR1 DIVR LL_RCC_PLL2_GetR + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVR) >> RCC_PLL2DIVR1_DIVR_Pos) + 1UL); +} + +/** + * @brief Get PLL2 S Coefficient + * @rmtoll PLL2DIVR2 DIVS LL_RCC_PLL2_GetS + * @retval A value between 1 and 8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetS(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR2, RCC_PLL2DIVR2_DIVS) >> RCC_PLL2DIVR2_DIVS_Pos) + 1UL); +} + +/** + * @brief Get PLL2 T Coefficient + * @rmtoll PLL2DIVR2 DIVT LL_RCC_PLL2_GetT + * @retval A value between 1 and 8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetT(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR2, RCC_PLL2DIVR2_DIVT) >> RCC_PLL2DIVR2_DIVT_Pos) + 1UL); +} + +/** + * @brief Get PLL2 FRACN Coefficient + * @rmtoll PLL2FRACR FRACN LL_RCC_PLL2_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN) >> RCC_PLL2FRACR_FRACN_Pos); +} + +/** + * @brief Set PLL2 N Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR1 DIVN LL_RCC_PLL2_SetN + * @param N parameter can be a value between 8 and 420 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVN, (N - 1UL) << RCC_PLL2DIVR1_DIVN_Pos); +} + +/** + * @brief Set PLL2 M Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_SetM + * @param M parameter can be a value between 1 and 64 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos); +} + +/** + * @brief Set PLL2 P Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR1 DIVP LL_RCC_PLL2_SetP + * @param P parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P) +{ + MODIFY_REG(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVP, (P - 1UL) << RCC_PLL2DIVR1_DIVP_Pos); +} + +/** + * @brief Set PLL2 Q Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR1 DIVQ LL_RCC_PLL2_SetQ + * @param Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q) +{ + MODIFY_REG(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVQ, (Q - 1UL) << RCC_PLL2DIVR1_DIVQ_Pos); +} + +/** + * @brief Set PLL2 R Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR1 DIVR LL_RCC_PLL2_SetR + * @param R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R) +{ + MODIFY_REG(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVR, (R - 1UL) << RCC_PLL2DIVR1_DIVR_Pos); +} + +/** + * @brief Set PLL2 S Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR2 DIVS LL_RCC_PLL2_SetS + * @param S parameter can be a value between 1 and 8 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetS(uint32_t S) +{ + MODIFY_REG(RCC->PLL2DIVR2, RCC_PLL2DIVR2_DIVS, (S - 1UL) << RCC_PLL2DIVR2_DIVS_Pos); +} + +/** + * @brief Set PLL2 T Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR2 DIVT LL_RCC_PLL2_SetT + * @param T parameter can be a value between 1 and 8 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetT(uint32_t T) +{ + MODIFY_REG(RCC->PLL2DIVR2, RCC_PLL2DIVR2_DIVT, (T - 1UL) << RCC_PLL2DIVR2_DIVT_Pos); +} + +/** + * @brief Set PLL2 FRACN Coefficient + * @rmtoll PLL2FRACR FRACN LL_RCC_PLL2_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN, FRACN << RCC_PLL2FRACR_FRACN_Pos); +} + +/** + * @brief Enable Spread Spectrum for PLL2. + * @note Configuration to be done with LL_RCC_PLL2_ConfigSpreadSpectrum + * @rmtoll PLLCFGR PLL2SSCGEN LL_RCC_PLL2_EnableSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_EnableSpreadSpectrum(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2SSCGEN); +} + +/** + * @brief Disable Spread Spectrum for PLL2. + * @rmtoll PLLCFGR PLL2SSCGEN LL_RCC_PLL2_DisableSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_DisableSpreadSpectrum(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2SSCGEN); +} + +/** + * @brief Check if Spread Spectrum for PLL2 is enabled + * @rmtoll PLLCFGR PLL2SSCGEN LL_RCC_PLL2_IsEnabledSpreadSpectrum + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledSpreadSpectrum(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2SSCGEN) == RCC_PLLCFGR_PLL2SSCGEN) ? 1UL : 0UL); +} + +/** + * @brief Get Spread Spectrum Modulation Period for PLL2 + * @rmtoll PLL2SSCGR MODPER LL_RCC_PLL2_GetModulationPeriod + * @retval Between Min_Data=0 and Max_Data=8191 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetModulationPeriod(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2SSCGR, RCC_PLL2SSCGR_MODPER)); +} + +/** + * @brief Get Spread Spectrum Increment Step for PLL2 + * @rmtoll PLL2SSCGR INCSTEP LL_RCC_PLL2_GetIncrementStep + * @retval Between Min_Data=0 and Max_Data=32767 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetIncrementStep(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2SSCGR, RCC_PLL2SSCGR_INCSTEP) >> RCC_PLL2SSCGR_INCSTEP_Pos); +} + +/** + * @brief Get Spread Spectrum Selection for PLL2 + * @rmtoll PLL2SSCGR SPREADSEL LL_RCC_PLL2_GetSpreadSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL_SPREAD_CENTER + * @arg @ref LL_RCC_PLL_SPREAD_DOWN + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetSpreadSelection(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2SSCGR, RCC_PLL2SSCGR_SPREADSEL)); +} + + +/** + * @brief Check if Dithering RPDF Noise for PLL2 is enabled + * @rmtoll PLL2SSCGR RPDFNDIS LL_RCC_PLL2_IsEnabledRPDFNDithering + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledRPDFNDithering(void) +{ + return ((READ_BIT(RCC->PLL2SSCGR, RCC_PLL2SSCGR_RPDFNDIS) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Check if Dithering TPDF Noise for PLL2 is enabled + * @rmtoll PLL2SSCGR TPDFNDIS LL_RCC_PLL2_IsEnabledTPDFNDithering + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledTPDFNDithering(void) +{ + return ((READ_BIT(RCC->PLL2SSCGR, RCC_PLL2SSCGR_TPDFNDIS) == 0U) ? 1UL : 0UL); +} +/** + * @brief Enable PLL3 + * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Disable PLL3 + * @note Cannot be disabled if the PLL3 clock is used as the system clock + * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Check if PLL3 Ready + * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == RCC_CR_PLL3RDY) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL3P + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3PEN LL_RCC_PLL3P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3P_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3PEN); +} + +/** + * @brief Enable PLL3Q + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3QEN LL_RCC_PLL3Q_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3Q_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3QEN); +} + +/** + * @brief Enable PLL3R + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3REN LL_RCC_PLL3R_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3R_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3REN); +} + +/** + * @brief Enable PLL3S + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3SEN LL_RCC_PLL3S_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3S_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3SEN); +} + +/** + * @brief Enable PLL3 FRACN + * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN); +} + +/** + * @brief Check if PLL3 P is enabled + * @rmtoll PLLCFGR PLL3PEN LL_RCC_PLL3P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3PEN) == RCC_PLLCFGR_PLL3PEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 Q is enabled + * @rmtoll PLLCFGR PLL3QEN LL_RCC_PLL3Q_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3QEN) == RCC_PLLCFGR_PLL3QEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 R is enabled + * @rmtoll PLLCFGR PLL3REN LL_RCC_PLL3R_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3REN) == RCC_PLLCFGR_PLL3REN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 S is enabled + * @rmtoll PLLCFGR PLL3SEN LL_RCC_PLL3S_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3S_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3SEN) == RCC_PLLCFGR_PLL3SEN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 FRACN is enabled + * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL3P + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3PEN LL_RCC_PLL3P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3P_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3PEN); +} + +/** + * @brief Disable PLL3Q + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3QEN LL_RCC_PLL3Q_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3Q_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3QEN); +} + +/** + * @brief Disable PLL3R + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3REN LL_RCC_PLL3R_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3R_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3REN); +} + +/** + * @brief Disable PLL3S + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3SEN LL_RCC_PLL3S_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3S_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3SEN); +} + +/** + * @brief Disable PLL3 FRACN + * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN); +} + +/** + * @brief Get PLL3 VCO Input Range + * @rmtoll PLLCFGR PLL3RGE LL_RCC_PLL3_GetVCOInputRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetVCOInputRange(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE) >> 22U); +} + +/** + * @brief Get PLL3 VCO OutputRange + * @rmtoll PLLCFGR PLL3VCOSEL LL_RCC_PLL3_GetVCOOutputRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetVCOOutputRange(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL) >> 22U); +} + +/** + * @brief Set PLL3 VCO Input Range + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (InputRange << 22U)); +} + +/** + * @brief Set PLL3 VCO OutputRange + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3VCOSEL LL_RCC_PLL3_SetVCOOutputRange + * @param VCORange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (VCORange << 22U)); +} + +/** + * @brief Get PLL3 N Coefficient + * @rmtoll PLL3DIVR1 DIVN LL_RCC_PLL3_GetN + * @retval A value between 8 and 420 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVN) >> RCC_PLL3DIVR1_DIVN_Pos) + 1UL); +} + +/** + * @brief Get PLL3 M Coefficient + * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_GetM + * @retval A value between 0 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos); +} + +/** + * @brief Get PLL3 P Coefficient + * @rmtoll PLL3DIVR1 DIVP LL_RCC_PLL3_GetP + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVP) >> RCC_PLL3DIVR1_DIVP_Pos) + 1UL); +} + +/** + * @brief Get PLL3 Q Coefficient + * @rmtoll PLL3DIVR1 DIVQ LL_RCC_PLL3_GetQ + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVQ) >> RCC_PLL3DIVR1_DIVQ_Pos) + 1UL); +} + +/** + * @brief Get PLL3 R Coefficient + * @rmtoll PLL3DIVR1 DIVR LL_RCC_PLL3_GetR + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVR) >> RCC_PLL3DIVR1_DIVR_Pos) + 1UL); +} + +/** + * @brief Get PLL3 S Coefficient + * @rmtoll PLL3DIVR2 DIVS LL_RCC_PLL3_GetS + * @retval A value between 1 and 8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetS(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR2, RCC_PLL3DIVR2_DIVS) >> RCC_PLL3DIVR2_DIVS_Pos) + 1UL); +} + +/** + * @brief Get PLL3 FRACN Coefficient + * @rmtoll PLL3FRACR FRACN LL_RCC_PLL3_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN) >> RCC_PLL3FRACR_FRACN_Pos); +} + +/** + * @brief Set PLL3 N Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR1 DIVN LL_RCC_PLL3_SetN + * @param N parameter can be a value between 8 and 420 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVN, (N - 1UL) << RCC_PLL3DIVR1_DIVN_Pos); +} + +/** + * @brief Set PLL3 M Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_SetM + * @param M parameter can be a value between 1 and 64 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos); +} + +/** + * @brief Set PLL3 P Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR1 DIVP LL_RCC_PLL3_SetP + * @param P parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P) +{ + MODIFY_REG(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVP, (P - 1UL) << RCC_PLL3DIVR1_DIVP_Pos); +} + +/** + * @brief Set PLL3 Q Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR1 DIVQ LL_RCC_PLL3_SetQ + * @param Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q) +{ + MODIFY_REG(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVQ, (Q - 1UL) << RCC_PLL3DIVR1_DIVQ_Pos); +} + +/** + * @brief Set PLL3 R Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR1 DIVR LL_RCC_PLL3_SetR + * @param R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R) +{ + MODIFY_REG(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVR, (R - 1UL) << RCC_PLL3DIVR1_DIVR_Pos); +} + +/** + * @brief Set PLL3 S Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR2 DIVS LL_RCC_PLL3_SetS + * @param S parameter can be a value between 1 and 8 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetS(uint32_t S) +{ + MODIFY_REG(RCC->PLL3DIVR2, RCC_PLL3DIVR2_DIVS, (S - 1UL) << RCC_PLL3DIVR2_DIVS_Pos); +} + +/** + * @brief Set PLL3 FRACN Coefficient + * @rmtoll PLL3FRACR FRACN LL_RCC_PLL3_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN, FRACN << RCC_PLL3FRACR_FRACN_Pos); +} + + +/** + * @brief Enable Spread Spectrum for PLL3. + * @note Configuration to be done with LL_RCC_PLL3_ConfigSpreadSpectrum + * @rmtoll PLLCFGR PLL3SSCGEN LL_RCC_PLL3_EnableSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_EnableSpreadSpectrum(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3SSCGEN); +} + +/** + * @brief Disable Spread Spectrum for PLL3. + * @rmtoll PLLCFGR PLL3SSCGEN LL_RCC_PLL3_DisableSpreadSpectrum + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_DisableSpreadSpectrum(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3SSCGEN); +} + +/** + * @brief Check if Spread Spectrum for PLL3 is enabled + * @rmtoll PLLCFGR PLL3SSCGEN LL_RCC_PLL3_IsEnabledSpreadSpectrum + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledSpreadSpectrum(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3SSCGEN) == RCC_PLLCFGR_PLL3SSCGEN) ? 1UL : 0UL); +} + +/** + * @brief Get Spread Spectrum Modulation Period for PLL3 + * @rmtoll PLL3SSCGR MODPER LL_RCC_PLL3_GetModulationPeriod + * @retval Between Min_Data=0 and Max_Data=8191 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetModulationPeriod(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3SSCGR, RCC_PLL3SSCGR_MODPER)); +} + +/** + * @brief Get Spread Spectrum Increment Step for PLL3 + * @rmtoll PLL3SSCGR INCSTEP LL_RCC_PLL3_GetIncrementStep + * @retval Between Min_Data=0 and Max_Data=32767 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetIncrementStep(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3SSCGR, RCC_PLL3SSCGR_INCSTEP) >> RCC_PLL3SSCGR_INCSTEP_Pos); +} + +/** + * @brief Get Spread Spectrum Selection for PLL3 + * @rmtoll PLL3SSCGR SPREADSEL LL_RCC_PLL3_GetSpreadSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL_SPREAD_CENTER + * @arg @ref LL_RCC_PLL_SPREAD_DOWN + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetSpreadSelection(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3SSCGR, RCC_PLL3SSCGR_SPREADSEL)); +} + + +/** + * @brief Check if Dithering RPDF Noise for PLL3 is enabled + * @rmtoll PLL3SSCGR RPDFNDIS LL_RCC_PLL3_IsEnabledRPDFNDithering + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledRPDFNDithering(void) +{ + return ((READ_BIT(RCC->PLL3SSCGR, RCC_PLL3SSCGR_RPDFNDIS) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Check if Dithering TPDF Noise for PLL3 is enabled + * @rmtoll PLL3SSCGR TPDFNDIS LL_RCC_PLL3_IsEnabledTPDFNDithering + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledTPDFNDithering(void) +{ + return ((READ_BIT(RCC->PLL3SSCGR, RCC_PLL3SSCGR_TPDFNDIS) == 0U) ? 1UL : 0UL); +} +/** + * @} + */ + + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); +} + +/** + * @brief Clear CSI ready interrupt flag + * @rmtoll CICR CSIRDYC LL_RCC_ClearFlag_CSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC); +} + +/** + * @brief Clear HSI48 ready interrupt flag + * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); +} + +/** + * @brief Clear PLL1 ready interrupt flag + * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL1RDYC); +} + +/** + * @brief Clear PLL2 ready interrupt flag + * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC); +} + +/** + * @brief Clear PLL3 ready interrupt flag + * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC); +} + +/** + * @brief Clear LSE Clock security system interrupt flag + * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); +} + +/** + * @brief Clear HSE Clock security system interrupt flag + * @rmtoll CICR HSECSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSECSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if CSI ready interrupt occurred or not + * @rmtoll CIFR CSIRDYF LL_RCC_IsActiveFlag_CSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == RCC_CIFR_CSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI48 ready interrupt occurred or not + * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 ready interrupt occurred or not + * @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 ready interrupt occurred or not + * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == RCC_CIFR_PLL2RDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 ready interrupt occurred or not + * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == RCC_CIFR_PLL3RDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE Clock security system interrupt occurred or not + * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE Clock security system interrupt occurred or not + * @rmtoll CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == RCC_CIFR_HSECSSF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == RCC_RSR_LPWRRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll RSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_WWDGRSTF) == RCC_RSR_WWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll RSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_IWDGRSTF) == RCC_RSR_IWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == RCC_RSR_SFTRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll RSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == RCC_RSR_PORRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll RSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == RCC_RSR_PINRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag BOR reset is set or not. + * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear all reset flags. + * @rmtoll RSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->RSR, RCC_RSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Enable CSI ready interrupt + * @rmtoll CIER CSIRDYIE LL_RCC_EnableIT_CSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE); +} + +/** + * @brief Enable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} + +/** + * @brief Enable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Enable PLL2 ready interrupt + * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); +} + +/** + * @brief Enable PLL3 ready interrupt + * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); +} + +/** + * @brief Enable LSECSS interrupt + * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Disable CSI ready interrupt + * @rmtoll CIER CSIRDYIE LL_RCC_DisableIT_CSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE); +} + +/** + * @brief Disable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} + +/** + * @brief Disable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Disable PLL2 ready interrupt + * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); +} + +/** + * @brief Disable PLL3 ready interrupt + * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); +} + +/** + * @brief Disable LSECSS interrupt + * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIER LSIRDYIE LL_RCC_IsEnableIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIER LSERDYIE LL_RCC_IsEnableIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIER HSIRDYIE LL_RCC_IsEnableIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIER HSERDYIE LL_RCC_IsEnableIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if CSI ready interrupt source is enabled or disabled. + * @rmtoll CIER CSIRDYIE LL_RCC_IsEnableIT_CSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI48 ready interrupt source is enabled or disabled. + * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnableIT_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL1 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnableIT_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL2 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnableIT_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL3 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnableIT_PLL3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSECSS interrupt source is enabled or disabled. + * @rmtoll CIER LSECSSIE LL_RCC_IsEnableIT_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL); +} +/** + * @} + */ + +/** @defgroup RCC_LL_EF_CALC_FREQ Calculate frequencies + * @{ + */ +/** + * @brief Helper function to calculate the PLL frequency output + * @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (), + * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetFRACN (), @ref LL_RCC_PLL1_GetP ()); + * @param PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI) + * @param M Between 1 and 63 + * @param N Between 4 and 512 + * @param FRACN Between 0 and 0x1FFF + * @param PQR VCO output divider (P, Q or R) + * Between 1 and 128, except for PLL1P Odd value not allowed + * @retval PLL1 clock frequency (in Hz) + */ +__STATIC_INLINE uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, + uint32_t PQR) +{ + float_t freq; + + freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN / (float_t)0x2000)); + + freq = freq / (float_t)PQR; + + return (uint32_t)freq; +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +void LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks); +void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks); +void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks); +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); + +void LL_RCC_PLL1_ConfigSpreadSpectrum(const LL_PLL_SpreadSpectrumTypeDef *pConfig); +void LL_RCC_PLL2_ConfigSpreadSpectrum(const LL_PLL_SpreadSpectrumTypeDef *pConfig); +void LL_RCC_PLL3_ConfigSpreadSpectrum(const LL_PLL_SpreadSpectrumTypeDef *pConfig); + +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); +uint32_t LL_RCC_GetADFClockFreq(uint32_t ADFxSource); +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); +uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource); +uint32_t LL_RCC_GetETHPHYClockFreq(uint32_t ETHxSource); +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource); +uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource); +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); +uint32_t LL_RCC_GetXSPIClockFreq(uint32_t XSPIxSource); +uint32_t LL_RCC_GetPSSIClockFreq(uint32_t PSSIxSource); +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); +uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource); +uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource); +uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetUSBPHYCClockFreq(uint32_t USBPHYCxSource); + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_RCC_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_rng.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_rng.h new file mode 100644 index 00000000000..4dc1918dade --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_rng.h @@ -0,0 +1,726 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_rng.h + * @author MCD Application Team + * @brief Header file of RNG LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_RNG_H +#define STM32H7RSxx_LL_RNG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (RNG) + +/** @defgroup RNG_LL RNG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures + * @{ + */ + + +/** + * @brief LL RNG Init Structure Definition + */ +typedef struct +{ + uint32_t ClockErrorDetection; /*!< Clock error detection. + This parameter can be one value of @ref RNG_LL_CED. + This parameter can be modified using unitary + functions @ref LL_RNG_EnableClkErrorDetect(). */ +} LL_RNG_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants + * @{ + */ + +/** @defgroup RNG_LL_CED Clock Error Detection + * @{ + */ +#define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */ +#define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */ +/** + * @} + */ +/** @defgroup RNG_LL_ARDIS Auto reset disable + * @{ + */ +#define LL_RNG_ARDIS_ENABLE 0x00000000U /*!< ARDIS enabled automatic reset to clear SECS bit*/ +#define LL_RNG_ARDIS_DISABLE RNG_CR_ARDIS /*!< ARDIS disabled no automatic reset to clear SECS bit*/ +/** + * @} + */ + +/** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal + * programmable divider acting on the incoming RNG clock + * @{ + */ +#define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */ +#define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) /*!< 2 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) /*!< 4 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 8 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) /*!< 16 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 32 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 64 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 128 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) /*!< 256 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) /*!< 512 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) /*!< 1024 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 2048 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) /*!< 4096 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 8192 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 16384 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 32768 RNG clock cycles per internal RNG clock */ +/** + * @} + */ + +/** @defgroup RNG_LL_NIST_Compliance NIST Compliance configuration + * @{ + */ +#define LL_RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration*/ +#define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */ + +/** + * @} + */ + +/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RNG_ReadReg function + * @{ + */ +#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */ +#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */ +#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */ +#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */ +#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */ +/** + * @} + */ + +/** @defgroup RNG_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros + * @{ + */ +#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros + * @{ + */ + +/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RNG register + * @param __INSTANCE__ RNG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RNG register + * @param __INSTANCE__ RNG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions + * @{ + */ +/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions + * @{ + */ + +/** + * @brief Enable Random Number Generation + * @rmtoll CR RNGEN LL_RNG_Enable + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_RNGEN); +} + +/** + * @brief Disable Random Number Generation + * @rmtoll CR RNGEN LL_RNG_Disable + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx) +{ + CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN); +} + +/** + * @brief Check if Random Number Generator is enabled + * @rmtoll CR RNGEN LL_RNG_IsEnabled + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Clock Error Detection + * @rmtoll CR CED LL_RNG_EnableClkErrorDetect + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Disable RNG Clock Error Detection + * @rmtoll CR CED LL_RNG_DisableClkErrorDetect + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Check if RNG Clock Error Detection is enabled + * @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL); +} + +/** + * @brief Set RNG Conditioning Soft Reset bit + * @rmtoll CR CONDRST LL_RNG_EnableCondReset + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Reset RNG Conditioning Soft Reset bit + * @rmtoll CR CONDRST LL_RNG_DisableCondReset + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx) +{ + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Check if RNG Conditioning Soft Reset bit is set + * @rmtoll CR CONDRST LL_RNG_IsEnabledCondReset + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL); +} + +/** + * @brief Enable RNG Config Lock + * @rmtoll CR CONFIGLOCK LL_RNG_ConfigLock + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK); +} + +/** + * @brief Check if RNG Config Lock is enabled + * @rmtoll CR CONFIGLOCK LL_RNG_IsConfigLocked + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL); +} + +/** + * @brief Enable NIST Compliance + * @rmtoll CR NISTC LL_RNG_EnableNistCompliance + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Disable NIST Compliance + * @rmtoll CR NISTC LL_RNG_DisableNistCompliance + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Check if NIST Compliance is enabled + * @rmtoll CR NISTC LL_RNG_IsEnabledNistCompliance + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL); +} + +/** + * @brief Set RNG Config1 Configuration field value + * @rmtoll CR RNG_CONFIG1 LL_RNG_SetConfig1 + * @param RNGx RNG Instance + * @param Config1 Value between 0 and 0x3F + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1) +{ + MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Get RNG Config1 Configuration field value + * @rmtoll CR RNG_CONFIG1 LL_RNG_GetConfig1 + * @param RNGx RNG Instance + * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos); +} + +/** + * @brief Set RNG Config2 Configuration field value + * @rmtoll CR RNG_CONFIG2 LL_RNG_SetConfig2 + * @param RNGx RNG Instance + * @param Config2 Value between 0 and 0x7 + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2) +{ + MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Get RNG Config2 Configuration field value + * @rmtoll CR RNG_CONFIG2 LL_RNG_GetConfig2 + * @param RNGx RNG Instance + * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7 + */ +__STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos); +} + +/** + * @brief Set RNG Config3 Configuration field value + * @rmtoll CR RNG_CONFIG3 LL_RNG_SetConfig3 + * @param RNGx RNG Instance + * @param Config3 Value between 0 and 0xF + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3) +{ + MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Get RNG Config3 Configuration field value + * @rmtoll CR RNG_CONFIG3 LL_RNG_GetConfig3 + * @param RNGx RNG Instance + * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF + */ +__STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos); +} + +/** + * @brief Set RNG Clock divider factor + * @rmtoll CR CLKDIV LL_RNG_SetClockDivider + * @param RNGx RNG Instance + * @param Divider can be one of the following values: + * @arg @ref LL_RNG_CLKDIV_BY_1 + * @arg @ref LL_RNG_CLKDIV_BY_2 + * @arg @ref LL_RNG_CLKDIV_BY_4 + * @arg @ref LL_RNG_CLKDIV_BY_8 + * @arg @ref LL_RNG_CLKDIV_BY_16 + * @arg @ref LL_RNG_CLKDIV_BY_32 + * @arg @ref LL_RNG_CLKDIV_BY_64 + * @arg @ref LL_RNG_CLKDIV_BY_128 + * @arg @ref LL_RNG_CLKDIV_BY_256 + * @arg @ref LL_RNG_CLKDIV_BY_512 + * @arg @ref LL_RNG_CLKDIV_BY_1024 + * @arg @ref LL_RNG_CLKDIV_BY_2048 + * @arg @ref LL_RNG_CLKDIV_BY_4096 + * @arg @ref LL_RNG_CLKDIV_BY_8192 + * @arg @ref LL_RNG_CLKDIV_BY_16384 + * @arg @ref LL_RNG_CLKDIV_BY_32768 + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider) +{ + MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Get RNG Clock divider factor + * @rmtoll CR CLKDIV LL_RNG_GetClockDivider + * @param RNGx RNG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RNG_CLKDIV_BY_1 + * @arg @ref LL_RNG_CLKDIV_BY_2 + * @arg @ref LL_RNG_CLKDIV_BY_4 + * @arg @ref LL_RNG_CLKDIV_BY_8 + * @arg @ref LL_RNG_CLKDIV_BY_16 + * @arg @ref LL_RNG_CLKDIV_BY_32 + * @arg @ref LL_RNG_CLKDIV_BY_64 + * @arg @ref LL_RNG_CLKDIV_BY_128 + * @arg @ref LL_RNG_CLKDIV_BY_256 + * @arg @ref LL_RNG_CLKDIV_BY_512 + * @arg @ref LL_RNG_CLKDIV_BY_1024 + * @arg @ref LL_RNG_CLKDIV_BY_2048 + * @arg @ref LL_RNG_CLKDIV_BY_4096 + * @arg @ref LL_RNG_CLKDIV_BY_8192 + * @arg @ref LL_RNG_CLKDIV_BY_16384 + * @arg @ref LL_RNG_CLKDIV_BY_32768 + */ +__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *RNGx) +{ + return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV); +} +/** + * @} + */ + +/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Indicate if the RNG Data ready Flag is set or not + * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if the Clock Error Current Status Flag is set or not + * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if the Seed Error Current Status Flag is set or not + * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if the Clock Error Interrupt Status Flag is set or not + * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if the Seed Error Interrupt Status Flag is set or not + * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL); +} + +/** + * @brief Clear Clock Error interrupt Status (CEIS) Flag + * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx) +{ + WRITE_REG(RNGx->SR, ~RNG_SR_CEIS); +} + +/** + * @brief Clear Seed Error interrupt Status (SEIS) Flag + * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx) +{ + WRITE_REG(RNGx->SR, ~RNG_SR_SEIS); +} + +/** + * @} + */ + +/** @defgroup RNG_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable Random Number Generator Interrupt + * (applies for either Seed error, Clock Error or Data ready interrupts) + * @rmtoll CR IE LL_RNG_EnableIT + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_IE); +} + +/** + * @brief Disable Random Number Generator Interrupt + * (applies for either Seed error, Clock Error or Data ready interrupts) + * @rmtoll CR IE LL_RNG_DisableIT + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx) +{ + CLEAR_BIT(RNGx->CR, RNG_CR_IE); +} + +/** + * @brief Check if Random Number Generator Interrupt is enabled + * (applies for either Seed error, Clock Error or Data ready interrupts) + * @rmtoll CR IE LL_RNG_IsEnabledIT + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RNG_LL_EF_Data_Management Data Management + * @{ + */ + +/** + * @brief Return32-bit Random Number value + * @rmtoll DR RNDATA LL_RNG_ReadRandData32 + * @param RNGx RNG Instance + * @retval Generated 32-bit random value + */ +__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) +{ + return (uint32_t)(READ_REG(RNGx->DR)); +} + +/** + * @} + */ + +/** + * @brief Enable Auto reset + * @rmtoll CR ARDIS LL_RNG_EnableArdis + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableArdis(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_ENABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Disable Auto reset + * @rmtoll CR ARDIS LL_RNG_DisableArdis + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableArdis(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_DISABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Check if RNG Auto reset is enabled + * @rmtoll CR ARDIS LL_RNG_IsEnabledArdis + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_ARDIS) != (RNG_CR_ARDIS)) ? 1UL : 0UL); +} + +/** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control + * @{ + */ + +/** + * @brief Set RNG Health Test Control + * @rmtoll HTCR HTCFG LL_RNG_SetHealthConfig + * @param RNGx RNG Instance + * @param HTCFG can be values of 32 bits + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) +{ + WRITE_REG(RNGx->HTCR, HTCFG); +} + +/** + * @brief Get RNG Health Test Control + * @rmtoll HTCR HTCFG LL_RNG_GetHealthConfig + * @param RNGx RNG Instance + * @retval Return 32-bit RNG Health Test configuration + */ +__STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) +{ + return (uint32_t)READ_REG(RNGx->HTCR); +} + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); +void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RNG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7RSxx_LL_RNG_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_rtc.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_rtc.h new file mode 100644 index 00000000000..52114283b33 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_rtc.h @@ -0,0 +1,6176 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_rtc.h + * @author MCD Application Team + * @brief Header file of RTC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_RTC_H +#define STM32H7RSxx_LL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @defgroup RTC_LL RTC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTC_LL_Private_Constants RTC Private Constants + * @{ + */ +/* Masks Definition */ +#define RTC_LL_INIT_MASK 0xFFFFFFFFU +#define RTC_LL_RSF_MASK 0xFFFFFF5FU + +/* Write protection defines */ +#define RTC_WRITE_PROTECTION_DISABLE (uint8_t)0xFF +#define RTC_WRITE_PROTECTION_ENABLE_1 (uint8_t)0xCA +#define RTC_WRITE_PROTECTION_ENABLE_2 (uint8_t)0x53 + +/* Defines used to combine date & time */ +#define RTC_OFFSET_WEEKDAY 24U +#define RTC_OFFSET_DAY 16U +#define RTC_OFFSET_MONTH 8U +#define RTC_OFFSET_HOUR 16U +#define RTC_OFFSET_MINUTE 8U + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_Private_Macros RTC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +#if !defined (UNUSED) +#define UNUSED(x) ((void)(x)) +#endif /* !defined (UNUSED) */ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure + * @{ + */ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t HourFormat; /*!< Specifies the RTC Hours Format. + This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetHourFormat(). */ + + uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetAsynchPrescaler(). */ + + uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetSynchPrescaler(). */ +} LL_RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT + + This feature can be modified afterwards using unitary function + @ref LL_RTC_TIME_SetFormat(). */ + + uint8_t Hours; /*!< Specifies the RTC Time Hours. + This parameter must be a number between Min_Data = 0 and Max_Data = 12 + if the @ref LL_RTC_TIME_FORMAT_PM is selected. + + This parameter must be a number between Min_Data = 0 and Max_Data = 23 + if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected. + + This feature can be modified afterwards using unitary function + @ref LL_RTC_TIME_SetHour(). */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 + + This feature can be modified afterwards using unitary function + @ref LL_RTC_TIME_SetMinute(). */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 + + This feature can be modified afterwards using unitary function + @ref LL_RTC_TIME_SetSecond(). */ +} LL_RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_LL_EC_WEEKDAY + + This feature can be modified afterwards using unitary function + @ref LL_RTC_DATE_SetWeekDay(). */ + + uint8_t Month; /*!< Specifies the RTC Date Month. + This parameter can be a value of @ref RTC_LL_EC_MONTH + + This feature can be modified afterwards using unitary function + @ref LL_RTC_DATE_SetMonth(). */ + + uint8_t Day; /*!< Specifies the RTC Date Day. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 + + This feature can be modified afterwards using unitary function + @ref LL_RTC_DATE_SetDay(). */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0 and Max_Data = 99 + + This feature can be modified afterwards using unitary function + @ref LL_RTC_DATE_SetYear(). */ +} LL_RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or + @ref RTC_LL_EC_ALMB_MASK for ALARM B. + + This feature can be modified afterwards using unitary function + @ref LL_RTC_ALMA_SetMask() for ALARM A or @ref LL_RTC_ALMB_SetMask() for ALARM B. + */ + + uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay. + This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION + for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B. + + This feature can be modified afterwards using unitary function + @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday() for ALARM A + or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() + for ALARM B. + */ + + uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay. + If AlarmDateWeekDaySel set to day, this parameter must be a number + between Min_Data = 1 and Max_Data = 31. + + This feature can be modified afterwards using unitary function + @ref LL_RTC_ALMA_SetDay() for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B. + + If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of + @ref RTC_LL_EC_WEEKDAY. + + This feature can be modified afterwards using unitary function + @ref LL_RTC_ALMA_SetWeekDay() for ALARM A or + @ref LL_RTC_ALMB_SetWeekDay() for ALARM B. + */ +} LL_RTC_AlarmTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants + * @{ + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EC_FORMAT FORMAT + * @{ + */ +#define LL_RTC_FORMAT_BIN 0U /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD 1U /*!< BCD data format */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay + * @{ + */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0U /*!< Alarm A Date is selected */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay + * @{ + */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0U /*!< Alarm B Date is selected */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */ +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RTC_ReadReg function + * @{ + */ +#define LL_RTC_SCR_SSRUF RTC_SCR_CSSRUF +#define LL_RTC_SCR_ITSF RTC_SCR_CITSF +#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF +#define LL_RTC_SCR_TSF RTC_SCR_CTSF +#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF +#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF +#define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF + +#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF +#define LL_RTC_ICSR_BCDU_2 RTC_ICSR_BCDU_2 +#define LL_RTC_ICSR_BCDU_1 RTC_ICSR_BCDU_1 +#define LL_RTC_ICSR_BCDU_0 RTC_ICSR_BCDU_0 +#define LL_RTC_ICSR_BIN_1 RTC_ICSR_BIN_1 +#define LL_RTC_ICSR_BIN_0 RTC_ICSR_BIN_0 +#define LL_RTC_ICSR_INITF RTC_ICSR_INITF +#define LL_RTC_ICSR_RSF RTC_ICSR_RSF +#define LL_RTC_ICSR_INITS RTC_ICSR_INITS +#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF +#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF +/** + * @} + */ + +/** @defgroup RTC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions + * @{ + */ +#define LL_RTC_CR_TSIE RTC_CR_TSIE +#define LL_RTC_CR_WUTIE RTC_CR_WUTIE +#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE +#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE +/** + * @} + */ + +/** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY + * @{ + */ +#define LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01 /*!< Monday */ +#define LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02 /*!< Tuesday */ +#define LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03 /*!< Wednesday */ +#define LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04 /*!< Thrusday */ +#define LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05 /*!< Friday */ +#define LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06 /*!< Saturday */ +#define LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07 /*!< Sunday */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_MONTH MONTH + * @{ + */ +#define LL_RTC_MONTH_JANUARY (uint8_t)0x01 /*!< January */ +#define LL_RTC_MONTH_FEBRUARY (uint8_t)0x02 /*!< February */ +#define LL_RTC_MONTH_MARCH (uint8_t)0x03 /*!< March */ +#define LL_RTC_MONTH_APRIL (uint8_t)0x04 /*!< April */ +#define LL_RTC_MONTH_MAY (uint8_t)0x05 /*!< May */ +#define LL_RTC_MONTH_JUNE (uint8_t)0x06 /*!< June */ +#define LL_RTC_MONTH_JULY (uint8_t)0x07 /*!< July */ +#define LL_RTC_MONTH_AUGUST (uint8_t)0x08 /*!< August */ +#define LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09 /*!< September */ +#define LL_RTC_MONTH_OCTOBER (uint8_t)0x10 /*!< October */ +#define LL_RTC_MONTH_NOVEMBER (uint8_t)0x11 /*!< November */ +#define LL_RTC_MONTH_DECEMBER (uint8_t)0x12 /*!< December */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT + * @{ + */ +#define LL_RTC_HOURFORMAT_24HOUR 0U /*!< 24 hour/day format */ +#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */ +/** + * @} + */ + +#if defined(RTC_CR_OSEL) +/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT + * @{ + */ +#define LL_RTC_ALARMOUT_DISABLE 0U /*!< Output disabled */ +#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */ +#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */ +#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */ +/** + * @} + */ +#endif /* RTC_CR_OSEL */ + +/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE + * @{ + */ +#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0U /*!< RTC_ALARM is push-pull output */ +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN + * @{ + */ +#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */ +#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT + * @{ + */ +#define LL_RTC_TIME_FORMAT_AM_OR_24 0U /*!< AM or 24-hour format */ +#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND + * @{ + */ +#define LL_RTC_SHIFT_SECOND_DELAY 0U /*!< Delay (seconds) = SUBFS / (PREDIV_S + 1) */ +#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /*!< Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK + * @{ + */ +#define LL_RTC_ALMA_MASK_NONE 0U /*!< No masks applied on Alarm A */ +#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT + * @{ + */ +#define LL_RTC_ALMA_TIME_FORMAT_AM 0U /*!< AM or 24-hour format */ +#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_SUBSECONDBIN_AUTOCLR RTC Alarm Sub Seconds with binary mode auto clear Definitions + * @{ + */ +#define LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO 0UL +/*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. */ + +#define LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES RTC_ALRMASSR_SSCLR +/*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR -> SS[31:0] + value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR -> SS[31:0]. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK + * @{ + */ +#define LL_RTC_ALMB_MASK_NONE 0U /*!< No masks applied on Alarm B */ +#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT + * @{ + */ +#define LL_RTC_ALMB_TIME_FORMAT_AM 0U /*!< AM or 24-hour format */ +#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_SUBSECONDBIN_AUTOCLR Alarm Sub Seconds with binary mode auto clear Definitions + * @{ + */ +#define LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO 0UL +/*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. */ + +#define LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES RTC_ALRMBSSR_SSCLR +/*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMBBINR -> SS[31:0] + value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMBBINR -> SS[31:0]. */ +/** + * @} + */ + +#if defined(RTC_CR_TSEDGE) +/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE + * @{ + */ +#define LL_RTC_TIMESTAMP_EDGE_RISING 0U /*!< RTC_TS input rising edge generates a time-stamp event */ +#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */ +/** + * @} + */ +#endif /* RTC_CR_TSEDGE */ + +/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT + * @{ + */ +#define LL_RTC_TS_TIME_FORMAT_AM 0U /*!< AM or 24-hour format */ +#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER TAMPER + * @{ + */ +#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */ +#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */ +#if (RTC_TAMP_NB == 3U) +#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */ +#elif (RTC_TAMP_NB == 8U) +#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */ +#define LL_RTC_TAMPER_4 TAMP_CR1_TAMP4E /*!< Tamper 4 input detection */ +#define LL_RTC_TAMPER_5 TAMP_CR1_TAMP5E /*!< Tamper 5 input detection */ +#define LL_RTC_TAMPER_6 TAMP_CR1_TAMP6E /*!< Tamper 6 input detection */ +#define LL_RTC_TAMPER_7 TAMP_CR1_TAMP7E /*!< Tamper 7 input detection */ +#define LL_RTC_TAMPER_8 TAMP_CR1_TAMP8E /*!< Tamper 8 input detection */ +#endif /* RTC_TAMP_NB */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK + * @{ + */ +#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased */ +#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased */ +#if (RTC_TAMP_NB > 2U) +#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */ +#endif /* (RTC_TAMP_NB > 2U) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE + * @{ + */ +#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1POM /*!< Tamper 1 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2POM /*!< Tamper 2 event does not erase the backup registers */ +#if (RTC_TAMP_NB == 3U) +#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3POM /*!< Tamper 3 event does not erase the backup registers */ +#elif (RTC_TAMP_NB == 8U) +#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3POM /*!< Tamper 3 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_TAMPER4 TAMP_CR2_TAMP4POM /*!< Tamper 4 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_TAMPER5 TAMP_CR2_TAMP5POM /*!< Tamper 5 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_TAMPER6 TAMP_CR2_TAMP6POM /*!< Tamper 6 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_TAMPER7 TAMP_CR2_TAMP7POM /*!< Tamper 7 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_TAMPER8 TAMP_CR2_TAMP8POM /*!< Tamper 8 event does not erase the backup registers */ +#endif /* RTC_TAMP_NB */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION + * @{ + */ +#define LL_RTC_TAMPER_DURATION_1RTCCLK 0U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER + * @{ + */ +#define LL_RTC_TAMPER_FILTER_DISABLE 0U /*!< Tamper filter is disabled */ +#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER + * @{ + */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL + * @{ + */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#if (RTC_TAMP_NB == 3U) +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#elif (RTC_TAMP_NB == 8U) +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP4 TAMP_CR2_TAMP4TRG /*!< Tamper 4 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP5 TAMP_CR2_TAMP5TRG /*!< Tamper 5 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP6 TAMP_CR2_TAMP6TRG /*!< Tamper 6 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP7 TAMP_CR2_TAMP7TRG /*!< Tamper 7 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP8 TAMP_CR2_TAMP8TRG /*!< Tamper 8 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#endif /* RTC_TAMP_NB */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_INTERNAL INTERNAL TAMPER + * @{ + */ +#define LL_RTC_TAMPER_ITAMP1 TAMP_CR1_ITAMP1E /*!< Internal tamper 1: Backup Domain voltage threshold monitoring */ +#define LL_RTC_TAMPER_ITAMP2 TAMP_CR1_ITAMP2E /*!< Internal tamper 2: Temperature monitoring */ +#define LL_RTC_TAMPER_ITAMP3 TAMP_CR1_ITAMP3E /*!< Internal tamper 3: LSE monitoring */ +#define LL_RTC_TAMPER_ITAMP4 TAMP_CR1_ITAMP4E /*!< Internal tamper 4: HSE monitoring */ +#define LL_RTC_TAMPER_ITAMP5 TAMP_CR1_ITAMP5E /*!< Internal tamper 5: RTC calendar overflow */ +#define LL_RTC_TAMPER_ITAMP6 TAMP_CR1_ITAMP6E /*!< Internal tamper 6: JTAG/SWD access when RDP > 0 */ +#define LL_RTC_TAMPER_ITAMP7 TAMP_CR1_ITAMP7E /*!< Internal tamper 7: ADC2 watchdog monitoring 1 */ +#define LL_RTC_TAMPER_ITAMP8 TAMP_CR1_ITAMP8E /*!< Internal tamper 8: Monotonic counter 1 overflow */ +#define LL_RTC_TAMPER_ITAMP9 TAMP_CR1_ITAMP9E /*!< Internal tamper 9: Cryptographic IPs fault */ +#define LL_RTC_TAMPER_ITAMP11 TAMP_CR1_ITAMP11E /*!< Internal tamper 11: IWDG reset when tamper flag is set */ +#define LL_RTC_TAMPER_ITAMP15 TAMP_CR1_ITAMP15E /*!< Internal tamper 15: System fault detection */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ITAMPER_NOERASE INTERNAL TAMPER NO ERASE + * @{ + */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER1 TAMP_CR3_ITAMP1POM /*!< Internal tamper 1 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER2 TAMP_CR3_ITAMP2POM /*!< Internal tamper 2 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER3 TAMP_CR3_ITAMP3POM /*!< Internal tamper 3 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER4 TAMP_CR3_ITAMP4POM /*!< Internal tamper 4 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER5 TAMP_CR3_ITAMP5POM /*!< Internal tamper 5 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER6 TAMP_CR3_ITAMP6POM /*!< Internal tamper 6 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER7 TAMP_CR3_ITAMP7POM /*!< Internal tamper 7 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER8 TAMP_CR3_ITAMP8POM /*!< Internal tamper 8 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER9 TAMP_CR3_ITAMP9POM /*!< Internal tamper 9 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER11 TAMP_CR3_ITAMP11POM /*!< Internal tamper 11 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER15 TAMP_CR3_ITAMP15POM /*!< Internal tamper 15 event does not erase the backup registers */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ACTIVE_MODE ACTIVE TAMPER MODE + * @{ + */ +#define LL_RTC_TAMPER_ATAMP_TAMP1AM TAMP_ATCR1_TAMP1AM /*!< Tamper 1 is active */ +#define LL_RTC_TAMPER_ATAMP_TAMP2AM TAMP_ATCR1_TAMP2AM /*!< Tamper 2 is active */ +#if (RTC_TAMP_NB == 3U) +#define LL_RTC_TAMPER_ATAMP_TAMP3AM TAMP_ATCR1_TAMP3AM /*!< Tamper 3 is active */ +#elif (RTC_TAMP_NB == 8U) +#define LL_RTC_TAMPER_ATAMP_TAMP3AM TAMP_ATCR1_TAMP3AM /*!< Tamper 3 is active */ +#define LL_RTC_TAMPER_ATAMP_TAMP4AM TAMP_ATCR1_TAMP4AM /*!< Tamper 4 is active */ +#define LL_RTC_TAMPER_ATAMP_TAMP5AM TAMP_ATCR1_TAMP5AM /*!< Tamper 5 is active */ +#define LL_RTC_TAMPER_ATAMP_TAMP6AM TAMP_ATCR1_TAMP6AM /*!< Tamper 6 is active */ +#define LL_RTC_TAMPER_ATAMP_TAMP7AM TAMP_ATCR1_TAMP7AM /*!< Tamper 7 is active */ +#define LL_RTC_TAMPER_ATAMP_TAMP8AM TAMP_ATCR1_TAMP8AM /*!< Tamper 8 is active */ +#endif /* RTC_TAMP_NB */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ACTIVE_ASYNC_PRESCALER ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK + * @{ + */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0U /*!< RTCCLK */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2048 (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/2048 */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ACTIVE_OUTPUT_SELECTION ACTIVE TAMPER OUTPUT SELECTION + * @{ + */ +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL1_Pos) +#if (RTC_TAMP_NB == 3U) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL1_Pos) +#elif (RTC_TAMP_NB == 8U) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL1_Pos) +#endif /* RTC_TAMP_NB */ + +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL2_Pos) +#if (RTC_TAMP_NB == 3U) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL2_Pos) +#elif (RTC_TAMP_NB == 8U) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL2_Pos) +#endif /* RTC_TAMP_NB */ + +#if (RTC_TAMP_NB == 3U) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL3_Pos) +#elif (RTC_TAMP_NB == 8U) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL3_Pos) +#endif /* RTC_TAMP_NB */ + +#if (RTC_TAMP_NB == 8U) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL4_Pos) + +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL5_Pos) + +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL6_Pos) + +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL7_Pos) +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL7_Pos) +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL7_Pos) +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL7_Pos) +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL7_Pos) +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL7_Pos) +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL7_Pos) +#define LL_RTC_TAMPER_ATAMP7IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL7_Pos) + +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL8_Pos) +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL8_Pos) +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL8_Pos) +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL8_Pos) +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL8_Pos) +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL8_Pos) +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP7OUT (6U << TAMP_ATCR2_ATOSEL8_Pos) +#define LL_RTC_TAMPER_ATAMP8IN_ATAMP8OUT (7U << TAMP_ATCR2_ATOSEL8_Pos) +#endif /* RTC_TAMP_NB */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_BKP BACKUP + * @{ + */ +#define LL_RTC_BKP_NUMBER RTC_BACKUP_NB +#define LL_RTC_BKP_DR0 0U +#define LL_RTC_BKP_DR1 1U +#define LL_RTC_BKP_DR2 2U +#define LL_RTC_BKP_DR3 3U +#define LL_RTC_BKP_DR4 4U +#define LL_RTC_BKP_DR5 5U +#define LL_RTC_BKP_DR6 6U +#define LL_RTC_BKP_DR7 7U +#define LL_RTC_BKP_DR8 8U +#define LL_RTC_BKP_DR9 9U +#define LL_RTC_BKP_DR10 10U +#define LL_RTC_BKP_DR11 11U +#define LL_RTC_BKP_DR12 12U +#define LL_RTC_BKP_DR13 13U +#define LL_RTC_BKP_DR14 14U +#define LL_RTC_BKP_DR15 15U +#define LL_RTC_BKP_DR16 16U +#define LL_RTC_BKP_DR17 17U +#define LL_RTC_BKP_DR18 18U +#define LL_RTC_BKP_DR19 19U +#define LL_RTC_BKP_DR20 20U +#define LL_RTC_BKP_DR21 21U +#define LL_RTC_BKP_DR22 22U +#define LL_RTC_BKP_DR23 23U +#define LL_RTC_BKP_DR24 24U +#define LL_RTC_BKP_DR25 25U +#define LL_RTC_BKP_DR26 26U +#define LL_RTC_BKP_DR27 27U +#define LL_RTC_BKP_DR28 28U +#define LL_RTC_BKP_DR29 29U +#define LL_RTC_BKP_DR30 30U +#define LL_RTC_BKP_DR31 31U +/** + * @} + */ + +/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV + * @{ + */ +#define LL_RTC_WAKEUPCLOCK_DIV_16 0U /*!< RTC/16 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0 /*!< RTC/8 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1 /*!< RTC/4 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2 /*!< ck_spre (usually 1 Hz) clock is selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value */ +/** + * @} + */ + +#if defined(RTC_CR_COE) +/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output + * @{ + */ +#define LL_RTC_CALIB_OUTPUT_NONE 0U /*!< Calibration output disabled */ +#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */ +#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE /*!< Calibration output is 512 Hz */ +/** + * @} + */ +#endif /* RTC_CR_COE */ + +/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion + * @{ + */ +#define LL_RTC_CALIB_INSERTPULSE_NONE 0U /*!< No RTCCLK pulses are added */ +#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period + * @{ + */ +#define LL_RTC_CALIB_PERIOD_32SEC 0U /*!< Use a 32-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_LOWPOWER Calibration low power + * @{ + */ +#define LL_RTC_CALIB_LOWPOWER_NONE 0U /*!< High conso mode */ +#define LL_RTC_CALIB_LOWPOWER_SET RTC_CALR_LPCAL /*!< Low power mode */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_BINARY_MODE Binary mode (Sub Second Register) + * @{ + */ +#define LL_RTC_BINARY_NONE 0U /*!< Free running BCD calendar mode (Binary mode disabled) */ +#define LL_RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */ +#define LL_RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary mode enable */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_BINARY_MIX_BCDU Calendar second incrementation in Binary mix mode + * @{ + */ +#define LL_RTC_BINARY_MIX_BCDU_0 0U /*!< 1s calendar increment is generated each time SS[7:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[8:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[9:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[10:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[11:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[12:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[13:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[14:0] = 0 */ +/** + * @} + */ +#if defined(RTC_PRIVCFGR_PRIV) +/** @defgroup RTC_LL_EC_PRIVILEGE_RTC_FULL Privilege full rtc + * @{ + */ +#define LL_RTC_PRIVILEGE_FULL_YES RTC_PRIVCFGR_PRIV /*!< RTC full privilege */ +#define LL_RTC_PRIVILEGE_FULL_NO 0U /*!< RTC is not full privilege, features can be unprivilege. See RTC_LL_EC_PRIVILEGE_RTC_FEATURE */ +/** + * @} + */ +#endif /* RTC_PRIVCFGR_PRIV */ + +/** @defgroup RTC_LL_EC_PRIVILEGE_RTC_FEATURE Privilege rtc features in case of LL_RTC_PRIVILEGE_FULL_NO. + * @{ + */ +#define LL_RTC_PRIVILEGE_FEATURE_INIT RTC_PRIVCFGR_INITPRIV /*!< Initialization feature is privilege */ +#define LL_RTC_PRIVILEGE_FEATURE_CAL RTC_PRIVCFGR_CALPRIV /*!< Calibration feature is privilege */ +#define LL_RTC_PRIVILEGE_FEATURE_TS RTC_PRIVCFGR_TSPRIV /*!< Time stamp feature is privilege */ +#define LL_RTC_PRIVILEGE_FEATURE_WUT RTC_PRIVCFGR_WUTPRIV /*!< Wake up timer feature is privilege */ +#define LL_RTC_PRIVILEGE_FEATURE_ALRA RTC_PRIVCFGR_ALRAPRIV /*!< Alarm A feature is privilege */ +#define LL_RTC_PRIVILEGE_FEATURE_ALRB RTC_PRIVCFGR_ALRBPRIV /*!< Alarm B feature is privilege */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_PRIVILEGE_TAMP_FULL Privilege full tamp + * @{ + */ +#define LL_TAMP_PRIVILEGE_FULL_YES TAMP_PRIVCFGR_TAMPPRIV /*!< TAMP full privilege */ +#define LL_TAMP_PRIVILEGE_FULL_NO 0U /*!< TAMP is not privilege */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_PRIVILEGE_BACKUP_REG_ZONE Privilege Backup register privilege zone + * @{ + */ +#define LL_RTC_PRIVILEGE_BKUP_ZONE_NONE 0U +#define LL_RTC_PRIVILEGE_BKUP_ZONE_1 TAMP_PRIVCFGR_BKPRWPRIV +#define LL_RTC_PRIVILEGE_BKUP_ZONE_2 TAMP_PRIVCFGR_BKPWPRIV +#define LL_RTC_PRIVILEGE_BKUP_ZONE_ALL (LL_RTC_PRIVILEGE_BKUP_ZONE_1 | LL_RTC_PRIVILEGE_BKUP_ZONE_2) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros + * @{ + */ + +/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Convert Convert helper Macros + * @{ + */ + +/** + * @brief Helper macro to convert a value from 2 digit decimal format to BCD format + * @param __VALUE__ Byte to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) ((uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))) + +/** + * @brief Helper macro to convert a value from BCD format to 2 digit decimal format + * @param __VALUE__ BCD value to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) \ + ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU))) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Date Date helper Macros + * @{ + */ + +/** + * @brief Helper macro to retrieve weekday. + * @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Year in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Year in BCD format (0x00 . . . 0x99) + */ +#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Month in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Day in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Day in BCD format (0x01 . . . 0x31) + */ +#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Time Time helper Macros + * @{ + */ + +/** + * @brief Helper macro to retrieve hour in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23) + */ +#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve minute in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Minutes in BCD format (0x00. . .0x59) + */ +#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve second in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Seconds in format (0x00. . .0x59) + */ +#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Set Hours format (24 hour/day or AM/PM hour format) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_CR FMT LL_RTC_SetHourFormat + * @param RTCx RTC Instance + * @param HourFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_HOURFORMAT_24HOUR + * @arg @ref LL_RTC_HOURFORMAT_AMPM + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat) +{ + MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); +} + +/** + * @brief Get Hours format (24 hour/day or AM/PM hour format) + * @rmtoll RTC_CR FMT LL_RTC_GetHourFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_HOURFORMAT_24HOUR + * @arg @ref LL_RTC_HOURFORMAT_AMPM + */ +__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); +} + +#if defined(RTC_CR_OSEL) +/** + * @brief Select the flag to be routed to RTC_ALARM output + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR OSEL LL_RTC_SetAlarmOutEvent + * @param RTCx RTC Instance + * @param AlarmOutput This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_DISABLE + * @arg @ref LL_RTC_ALARMOUT_ALMA + * @arg @ref LL_RTC_ALARMOUT_ALMB + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput) +{ + MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput); +} + +/** + * @brief Get the flag to be routed to RTC_ALARM output + * @rmtoll RTC_CR OSEL LL_RTC_GetAlarmOutEvent + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_DISABLE + * @arg @ref LL_RTC_ALARMOUT_ALMA + * @arg @ref LL_RTC_ALARMOUT_ALMB + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); +} +#endif /* RTC_CR_OSEL */ + +#ifdef RTC_CR_TAMPALRM_TYPE +/** + * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType + * @param RTCx RTC Instance + * @param Output This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output) +{ + MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output); +} + +/** + * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_GetAlarmOutputType + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE)); +} +#endif /* RTC_CR_TAMPALRM_TYPE */ + +/** + * @brief Enable initialization mode + * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) + * and prescaler register (RTC_PRER). + * Counters are stopped and start counting from the new value when INIT is reset. + * @rmtoll RTC_ICSR INIT LL_RTC_EnableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx) +{ + /* Set the Initialization mode */ + SET_BIT(RTCx->ICSR, RTC_ICSR_INIT); +} + +/** + * @brief Disable initialization mode (Free running mode) + * @rmtoll RTC_ICSR INIT LL_RTC_DisableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) +{ + /* Exit Initialization mode */ + CLEAR_BIT(RTCx->ICSR, RTC_ICSR_INIT); + +} + +/** + * @brief Set Binary mode (Sub Second Register) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function). + * @rmtoll RTC_ICSR BIN LL_RTC_SetBinaryMode + * @param RTCx RTC Instance + * @param BinaryMode can be one of the following values: + * @arg @ref LL_RTC_BINARY_NONE + * @arg @ref LL_RTC_BINARY_ONLY + * @arg @ref LL_RTC_BINARY_MIX + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetBinaryMode(RTC_TypeDef *RTCx, uint32_t BinaryMode) +{ + MODIFY_REG(RTCx->ICSR, RTC_ICSR_BIN, BinaryMode); +} + +/** + * @brief Get Binary mode (Sub Second Register) + * @rmtoll RTC_ICSR BIN LL_RTC_GetBinaryMode + * @param RTCx RTC Instance + * @retval This parameter can be one of the following values: + * @arg @ref LL_RTC_BINARY_NONE + * @arg @ref LL_RTC_BINARY_ONLY + * @arg @ref LL_RTC_BINARY_MIX + * @retval None + */ +__STATIC_INLINE uint32_t LL_RTC_GetBinaryMode(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BIN)); +} + +/** + * @brief Set Binary Mix mode BCDU + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function). + * @rmtoll RTC_ICSR BCDU LL_RTC_SetBinMixBCDU + * @param RTCx RTC Instance + * @param BinMixBcdU can be one of the following values: + * @arg @ref LL_RTC_BINARY_MIX_BCDU_0 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_1 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_2 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_3 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_4 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_5 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_6 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_7 + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetBinMixBCDU(RTC_TypeDef *RTCx, uint32_t BinMixBcdU) +{ + MODIFY_REG(RTCx->ICSR, RTC_ICSR_BCDU, BinMixBcdU); +} + +/** + * @brief Get Binary Mix mode BCDU + * @rmtoll RTC_ICSR BCDU LL_RTC_GetBinMixBCDU + * @param RTCx RTC Instance + * @retval This parameter can be one of the following values: + * @arg @ref LL_RTC_BINARY_MIX_BCDU_0 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_1 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_2 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_3 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_4 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_5 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_6 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_RTC_GetBinMixBCDU(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BCDU)); +} + +#ifdef RTC_CR_POL +/** + * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR POL LL_RTC_SetOutputPolarity + * @param RTCx RTC Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity) +{ + MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); +} + +/** + * @brief Get Output polarity + * @rmtoll RTC_CR POL LL_RTC_GetOutputPolarity + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + */ +__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); +} +#endif /* RTC_CR_POL */ + +/** + * @brief Enable Bypass the shadow registers + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR BYPSHAD LL_RTC_EnableShadowRegBypass + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_BYPSHAD); +} + +/** + * @brief Disable Bypass the shadow registers + * @rmtoll RTC_CR BYPSHAD LL_RTC_DisableShadowRegBypass + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD); +} + +/** + * @brief Check if Shadow registers bypass is enabled or not. + * @rmtoll RTC_CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1U : 0U); +} + +#if defined(RTC_CR_REFCKON) +/** + * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_CR REFCKON LL_RTC_EnableRefClock + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_REFCKON); +} + +/** + * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_CR REFCKON LL_RTC_DisableRefClock + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON); +} +#endif /* RTC_CR_REFCKON */ + +/** + * @brief Set Asynchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_A LL_RTC_SetAsynchPrescaler + * @param RTCx RTC Instance + * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler) +{ + MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos); +} + +/** + * @brief Set Synchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_S LL_RTC_SetSynchPrescaler + * @param RTCx RTC Instance + * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler) +{ + MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler); +} + +/** + * @brief Get Asynchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_A LL_RTC_GetAsynchPrescaler + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0x7F + */ +__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); +} + +/** + * @brief Get Synchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_S LL_RTC_GetSynchPrescaler + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF + */ +__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); +} + +/** + * @brief Enable the write protection for RTC registers. + * @rmtoll RTC_WPR KEY LL_RTC_EnableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE); +} + +/** + * @brief Disable the write protection for RTC registers. + * @rmtoll RTC_WPR KEY LL_RTC_DisableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1); + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); +} + +#ifdef RTC_CR_TAMPOE +/** + * @brief Enable tamper output. + * @note When the tamper output is enabled, all external and internal tamper flags + * are ORed and routed to the TAMPALRM output. + * @rmtoll RTC_CR TAMPOE LL_RTC_EnableTamperOutput + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Disable tamper output. + * @rmtoll RTC_CR TAMPOE LL_RTC_DisableTamperOutput + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Check if tamper output is enabled or not. + * @rmtoll RTC_CR TAMPOE LL_RTC_IsTamperOutputEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1U : 0U); +} + +/** + * @brief Enable internal pull-up in output mode. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU); +} +#endif /* RTC_CR_TAMPOE */ + +#ifdef RTC_CR_TAMPALRM_PU +/** + * @brief Disable internal pull-up in output mode. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU); +} + +/** + * @brief Check if internal pull-up in output mode is enabled or not. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_IsAlarmPullUpEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1U : 0U); +} +#endif /* RTC_CR_TAMPALRM_PU */ + +#if defined(RTC_CR_OUT2EN) +/** + * @brief Enable RTC_OUT2 output + * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent) + * and COE (@ref LL_RTC_CAL_SetOutputFreq) settings. + * @note RTC_OUT2 is not available in VBAT mode. + * @rmtoll RTC_CR OUT2EN LL_RTC_EnableOutput2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Disable RTC_OUT2 output + * @rmtoll RTC_CR OUT2EN LL_RTC_DisableOutput2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Check if RTC_OUT2 output is enabled or not. + * @rmtoll RTC_CR OUT2EN LL_RTC_IsOutput2Enabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1U : 0U); +} +#endif /* RTC_CR_OUT2EN */ +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Time Time + * @{ + */ + +/** + * @brief Set time format (AM/24-hour or PM notation) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_TR PM LL_RTC_TIME_SetFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); +} + +/** + * @brief Get time format (AM or PM notation) + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @rmtoll RTC_TR PM LL_RTC_TIME_GetFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); +} + +/** + * @brief Set Hours in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format + * @rmtoll RTC_TR HT LL_RTC_TIME_SetHour\n + * RTC_TR HU LL_RTC_TIME_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))); +} + +/** + * @brief Get Hours in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to + * Binary format + * @rmtoll RTC_TR HT LL_RTC_TIME_GetHour\n + * RTC_TR HU LL_RTC_TIME_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); +} + +/** + * @brief Set Minutes in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll RTC_TR MNT LL_RTC_TIME_SetMinute\n + * RTC_TR MNU LL_RTC_TIME_SetMinute + * @param RTCx RTC Instance + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU), + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos))); +} + +/** + * @brief Get Minutes in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD + * to Binary format + * @rmtoll RTC_TR MNT LL_RTC_TIME_GetMinute\n + * RTC_TR MNU LL_RTC_TIME_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); +} + +/** + * @brief Set Seconds in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll RTC_TR ST LL_RTC_TIME_SetSecond\n + * RTC_TR SU LL_RTC_TIME_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos))); +} + +/** + * @brief Get Seconds in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD + * to Binary format + * @rmtoll RTC_TR ST LL_RTC_TIME_GetSecond\n + * RTC_TR SU LL_RTC_TIME_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); +} + +/** + * @brief Set time (hour, minute and second) in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note TimeFormat and Hours should follow the same format + * @rmtoll RTC_TR PM LL_RTC_TIME_Config\n + * RTC_TR HT LL_RTC_TIME_Config\n + * RTC_TR HU LL_RTC_TIME_Config\n + * RTC_TR MNT LL_RTC_TIME_Config\n + * RTC_TR MNU LL_RTC_TIME_Config\n + * RTC_TR ST LL_RTC_TIME_Config\n + * RTC_TR SU LL_RTC_TIME_Config + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, + uint32_t Format12_24, + uint32_t Hours, + uint32_t Minutes, + uint32_t Seconds) +{ + uint32_t temp; + + temp = Format12_24 | \ + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)); + MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp); +} + +/** + * @brief Get time (hour, minute and second) in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_TR HT LL_RTC_TIME_Get\n + * RTC_TR HU LL_RTC_TIME_Get\n + * RTC_TR MNT LL_RTC_TIME_Get\n + * RTC_TR MNU LL_RTC_TIME_Get\n + * RTC_TR ST LL_RTC_TIME_Get\n + * RTC_TR SU LL_RTC_TIME_Get + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(const RTC_TypeDef *RTCx) +{ + uint32_t temp; + + temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); + return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | \ + ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ + (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | \ + ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ + ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos))); +} + +/** + * @brief Memorize whether the daylight saving time change has been performed + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR BKP LL_RTC_TIME_EnableDayLightStore + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_BKP); +} + +/** + * @brief Disable memorization whether the daylight saving time change has been performed. + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR BKP LL_RTC_TIME_DisableDayLightStore + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_BKP); +} + +/** + * @brief Check if RTC Day Light Saving stored operation has been enabled or not + * @rmtoll RTC_CR BKP LL_RTC_TIME_IsDayLightStoreEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1U : 0U); +} + +/** + * @brief Subtract 1 hour (winter time change) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR SUB1H LL_RTC_TIME_DecHour + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_SUB1H); +} + +/** + * @brief Add 1 hour (summer time change) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ADD1H LL_RTC_TIME_IncHour + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ADD1H); +} + +/** + * @brief Get Sub second value in the synchronous prescaler counter. + * @note You can use both SubSeconds value and SecondFraction (PREDIV_S through + * LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar + * SubSeconds value in second fraction ratio with time unit following + * generic formula: + * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit + * This conversion can be performed only if no shift operation is pending + * (ie. SHFP=0) when PREDIV_S >= SS. + * @rmtoll RTC_SSR SS LL_RTC_TIME_GetSubSecond + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); +} + +/** + * @brief Synchronize to a remote clock with a high degree of precision. + * @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second. + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @rmtoll RTC_SHIFTR ADD1S LL_RTC_TIME_Synchronize\n + * RTC_SHIFTR SUBFS LL_RTC_TIME_Synchronize + * @param RTCx RTC Instance + * @param ShiftSecond This parameter can be one of the following values: + * @arg @ref LL_RTC_SHIFT_SECOND_DELAY + * @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE + * @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF) + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction) +{ + WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Date Date + * @{ + */ + +/** + * @brief Set Year in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format + * @rmtoll RTC_DR YT LL_RTC_DATE_SetYear\n + * RTC_DR YU LL_RTC_DATE_SetYear + * @param RTCx RTC Instance + * @param Year Value between Min_Data=0x00 and Max_Data=0x99 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU), + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))); +} + +/** + * @brief Get Year in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format + * @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n + * RTC_DR YU LL_RTC_DATE_GetYear + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x99 + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); +} + +/** + * @brief Set Week day + * @rmtoll RTC_DR WDU LL_RTC_DATE_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos); +} + +/** + * @brief Get Week day + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); +} + +/** + * @brief Set Month in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format + * @rmtoll RTC_DR MT LL_RTC_DATE_SetMonth\n + * RTC_DR MU LL_RTC_DATE_SetMonth + * @param RTCx RTC Instance + * @param Month This parameter can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU), + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos))); +} + +/** + * @brief Get Month in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format + * @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n + * RTC_DR MU LL_RTC_DATE_GetMonth + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); +} + +/** + * @brief Set Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll RTC_DR DT LL_RTC_DATE_SetDay\n + * RTC_DR DU LL_RTC_DATE_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU), + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos))); +} + +/** + * @brief Get Day in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n + * RTC_DR DU LL_RTC_DATE_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); +} + +/** + * @brief Set date (WeekDay, Day, Month and Year) in BCD format + * @rmtoll RTC_DR WDU LL_RTC_DATE_Config\n + * RTC_DR MT LL_RTC_DATE_Config\n + * RTC_DR MU LL_RTC_DATE_Config\n + * RTC_DR DT LL_RTC_DATE_Config\n + * RTC_DR DU LL_RTC_DATE_Config\n + * RTC_DR YT LL_RTC_DATE_Config\n + * RTC_DR YU LL_RTC_DATE_Config + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @param Month This parameter can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @param Year Value between Min_Data=0x00 and Max_Data=0x99 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, + uint32_t WeekDay, + uint32_t Day, + uint32_t Month, + uint32_t Year) +{ + uint32_t temp; + + temp = (WeekDay << RTC_DR_WDU_Pos) | \ + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \ + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)); + + MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp); +} + +/** + * @brief Get date (WeekDay, Day, Month and Year) in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, + * and __LL_RTC_GET_DAY are available to get independently each parameter. + * @rmtoll RTC_DR WDU LL_RTC_DATE_Get\n + * RTC_DR MT LL_RTC_DATE_Get\n + * RTC_DR MU LL_RTC_DATE_Get\n + * RTC_DR DT LL_RTC_DATE_Get\n + * RTC_DR DU LL_RTC_DATE_Get\n + * RTC_DR YT LL_RTC_DATE_Get\n + * RTC_DR YU LL_RTC_DATE_Get + * @param RTCx RTC Instance + * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_Get(const RTC_TypeDef *RTCx) +{ + uint32_t temp; + + temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); + return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ + (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | \ + ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \ + (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | \ + ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \ + ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos))); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARMA ALARMA + * @{ + */ + +/** + * @brief Enable Alarm A + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRAE); +} + +/** + * @brief Disable Alarm A + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE); +} + +/** + * @brief Specify the Alarm A masks. + * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK3 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK2 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK1 LL_RTC_ALMA_SetMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_ALMA_MASK_NONE + * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMA_MASK_HOURS + * @arg @ref LL_RTC_ALMA_MASK_MINUTES + * @arg @ref LL_RTC_ALMA_MASK_SECONDS + * @arg @ref LL_RTC_ALMA_MASK_ALL + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask); +} + +/** + * @brief Get the Alarm A masks. + * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK3 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK2 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK1 LL_RTC_ALMA_GetMask + * @param RTCx RTC Instance + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_RTC_ALMA_MASK_NONE + * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMA_MASK_HOURS + * @arg @ref LL_RTC_ALMA_MASK_MINUTES + * @arg @ref LL_RTC_ALMA_MASK_SECONDS + * @arg @ref LL_RTC_ALMA_MASK_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); +} + +/** + * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) + * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); +} + +/** + * @brief Disable AlarmA Week day selection (DU[3:0] represents the date ) + * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); +} + +/** + * @brief Set ALARM A Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_SetDay\n + * RTC_ALRMAR DU LL_RTC_ALMA_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU), + (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos))); +} + +/** + * @brief Get ALARM A Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_GetDay\n + * RTC_ALRMAR DU LL_RTC_ALMA_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Set ALARM A Weekday + * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Get ALARM A Weekday + * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Set Alarm A time format (AM/24-hour or PM notation) + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_SetTimeFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat); +} + +/** + * @brief Get Alarm A time format (AM or PM notation) + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); +} + +/** + * @brief Set ALARM A Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_SetHour\n + * RTC_ALRMAR HU LL_RTC_ALMA_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU), + (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))); +} + +/** + * @brief Get ALARM A Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetHour\n + * RTC_ALRMAR HU LL_RTC_ALMA_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); +} + +/** + * @brief Set ALARM A Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_SetMinute\n + * RTC_ALRMAR MNU LL_RTC_ALMA_SetMinute + * @param RTCx RTC Instance + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU), + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos))); +} + +/** + * @brief Get ALARM A Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_GetMinute\n + * RTC_ALRMAR MNU LL_RTC_ALMA_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); +} + +/** + * @brief Set ALARM A Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_SetSecond\n + * RTC_ALRMAR SU LL_RTC_ALMA_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU), + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos))); +} + +/** + * @brief Get ALARM A Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_GetSecond\n + * RTC_ALRMAR SU LL_RTC_ALMA_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); +} + +/** + * @brief Set Alarm A Time (hour, minute and second) in BCD format + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR HT LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR HU LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR MNT LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR MNU LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR ST LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR SU LL_RTC_ALMA_ConfigTime + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, + uint32_t Format12_24, + uint32_t Hours, + uint32_t Minutes, + uint32_t Seconds) +{ + uint32_t temp; + + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)); + + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | \ + RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp); +} + +/** + * @brief Get Alarm B Time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR HU LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR MNT LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR MNU LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR ST LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR SU LL_RTC_ALMA_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | + (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx)); +} + +/** + * @brief Set Alarm A Mask the most-significant bits starting at this bit + * @note This register can be written only when ALRAE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask + * @param RTCx RTC Instance + * @param Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos); +} + +/** + * @brief Get Alarm A Mask the most-significant bits starting at this bit + * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); +} + +/** + * @brief Set Alarm A Binary mode auto clear + * @note This register can be written only when ALRAE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRABINR SSCLR LL_RTC_ALMA_SetBinAutoClr + * @param RTCx RTC Instance + * @param BinaryAutoClr This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t BinaryAutoClr) +{ + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SSCLR, BinaryAutoClr); +} + +/** + * @brief Get Alarm A Binary mode auto clear + * @rmtoll RTC_ALRABINR SSCLR LL_RTC_ALMA_GetBinAutoClr + * @param RTCx RTC Instance + * @retval It can be one of the following values: + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetBinAutoClr(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SSCLR)); +} + +/** + * @brief Set Alarm A Sub seconds value + * @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_SetSubSecond + * @param RTCx RTC Instance + * @param Subsecond If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) +{ + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond); +} + +/** + * @brief Get Alarm A Sub seconds value + * @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_GetSubSecond + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARMB ALARMB + * @{ + */ + +/** + * @brief Enable Alarm B + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRBE); +} + +/** + * @brief Disable Alarm B + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE); +} + +/** + * @brief Specify the Alarm B masks. + * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK3 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK2 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK1 LL_RTC_ALMB_SetMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_ALMB_MASK_NONE + * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMB_MASK_HOURS + * @arg @ref LL_RTC_ALMB_MASK_MINUTES + * @arg @ref LL_RTC_ALMB_MASK_SECONDS + * @arg @ref LL_RTC_ALMB_MASK_ALL + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask); +} + +/** + * @brief Get the Alarm B masks. + * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK3 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK2 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK1 LL_RTC_ALMB_GetMask + * @param RTCx RTC Instance + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_RTC_ALMB_MASK_NONE + * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMB_MASK_HOURS + * @arg @ref LL_RTC_ALMB_MASK_MINUTES + * @arg @ref LL_RTC_ALMB_MASK_SECONDS + * @arg @ref LL_RTC_ALMB_MASK_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); +} + +/** + * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) + * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); +} + +/** + * @brief Disable AlarmB Week day selection (DU[3:0] represents the date ) + * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); +} + +/** + * @brief Set ALARM B Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_SetDay\n + * RTC_ALRMBR DU LL_RTC_ALMB_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU), + (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos))); +} + +/** + * @brief Get ALARM B Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_GetDay\n + * RTC_ALRMBR DU LL_RTC_ALMB_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Set ALARM B Weekday + * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Get ALARM B Weekday + * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Set ALARM B time format (AM/24-hour or PM notation) + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_SetTimeFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat); +} + +/** + * @brief Get ALARM B time format (AM or PM notation) + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); +} + +/** + * @brief Set ALARM B Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_SetHour\n + * RTC_ALRMBR HU LL_RTC_ALMB_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU), + (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))); +} + +/** + * @brief Get ALARM B Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetHour\n + * RTC_ALRMBR HU LL_RTC_ALMB_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); +} + +/** + * @brief Set ALARM B Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_SetMinute\n + * RTC_ALRMBR MNU LL_RTC_ALMB_SetMinute + * @param RTCx RTC Instance + * @param Minutes between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU), + (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos))); +} + +/** + * @brief Get ALARM B Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_GetMinute\n + * RTC_ALRMBR MNU LL_RTC_ALMB_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); +} + +/** + * @brief Set ALARM B Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_SetSecond\n + * RTC_ALRMBR SU LL_RTC_ALMB_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU), + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos))); +} + +/** + * @brief Get ALARM B Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_GetSecond\n + * RTC_ALRMBR SU LL_RTC_ALMB_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); +} + +/** + * @brief Set Alarm B Time (hour, minute and second) in BCD format + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR HT LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR HU LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR MNT LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR MNU LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR ST LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR SU LL_RTC_ALMB_ConfigTime + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, + uint32_t Format12_24, + uint32_t Hours, + uint32_t Minutes, + uint32_t Seconds) +{ + uint32_t temp; + + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)); + + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | \ + RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp); +} + +/** + * @brief Get Alarm B Time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR HU LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR MNT LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR MNU LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR ST LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR SU LL_RTC_ALMB_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | \ + (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx)); +} + +/** + * @brief Set Alarm B Mask the most-significant bits starting at this bit + * @note This register can be written only when ALRBE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask + * @param RTCx RTC Instance + * @param Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos); +} + +/** + * @brief Get Alarm B Mask the most-significant bits starting at this bit + * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); +} + +/** + * @brief Set Alarm B Binary mode auto clear + * @note This register can be written only when ALRBE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRBBINR SSCLR LL_RTC_ALMB_SetBinAutoClr + * @param RTCx RTC Instance + * @param BinaryAutoClr This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t BinaryAutoClr) +{ + MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SSCLR, BinaryAutoClr); +} + +/** + * @brief Get Alarm B Binary mode auto clear + * @rmtoll RTC_ALRBBINR SSCLR LL_RTC_ALMB_GetBinAutoClr + * @param RTCx RTC Instance + * @retval It can be one of the following values: + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetBinAutoClr(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SSCLR)); +} + +/** + * @brief Set Alarm B Sub seconds value + * @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_SetSubSecond + * @param RTCx RTC Instance + * @param Subsecond If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) +{ + MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond); +} + +/** + * @brief Get Alarm B Sub seconds value + * @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_GetSubSecond + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Timestamp Timestamp + * @{ + */ + +/** + * @brief Enable internal event timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ITSE LL_RTC_TS_EnableInternalEvent + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ITSE); +} + +/** + * @brief Disable internal event timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ITSE LL_RTC_TS_DisableInternalEvent + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ITSE); +} + +#ifdef RTC_CR_TSE +/** + * @brief Enable Timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSE LL_RTC_TS_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TSE); +} + +/** + * @brief Disable Timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSE LL_RTC_TS_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TSE); +} +#endif /* RTC_CR_TSE */ + +#if defined(RTC_CR_TSEDGE) +/** + * @brief Set Time-stamp event active edge + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting + * @rmtoll RTC_CR TSEDGE LL_RTC_TS_SetActiveEdge + * @param RTCx RTC Instance + * @param Edge This parameter can be one of the following values: + * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING + * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) +{ + MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge); +} + +/** + * @brief Get Time-stamp event active edge + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSEDGE LL_RTC_TS_GetActiveEdge + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING + * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); +} +#endif /* RTC_CR_TSEDGE */ + +/** + * @brief Get Timestamp AM/PM notation (AM or 24-hour format) + * @rmtoll RTC_TSTR PM LL_RTC_TS_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TS_TIME_FORMAT_AM + * @arg @ref LL_RTC_TS_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); +} + +/** + * @brief Get Timestamp Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll RTC_TSTR HT LL_RTC_TS_GetHour\n + * RTC_TSTR HU LL_RTC_TS_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); +} + +/** + * @brief Get Timestamp Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll RTC_TSTR MNT LL_RTC_TS_GetMinute\n + * RTC_TSTR MNU LL_RTC_TS_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); +} + +/** + * @brief Get Timestamp Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll RTC_TSTR ST LL_RTC_TS_GetSecond\n + * RTC_TSTR SU LL_RTC_TS_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); +} + +/** + * @brief Get Timestamp time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_TSTR HT LL_RTC_TS_GetTime\n + * RTC_TSTR HU LL_RTC_TS_GetTime\n + * RTC_TSTR MNT LL_RTC_TS_GetTime\n + * RTC_TSTR MNU LL_RTC_TS_GetTime\n + * RTC_TSTR ST LL_RTC_TS_GetTime\n + * RTC_TSTR SU LL_RTC_TS_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, + RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); +} + +/** + * @brief Get Timestamp Week day + * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); +} + +/** + * @brief Get Timestamp Month in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format + * @rmtoll RTC_TSDR MT LL_RTC_TS_GetMonth\n + * RTC_TSDR MU LL_RTC_TS_GetMonth + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); +} + +/** + * @brief Get Timestamp Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_TSDR DT LL_RTC_TS_GetDay\n + * RTC_TSDR DU LL_RTC_TS_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); +} + +/** + * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format + * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, + * and __LL_RTC_GET_DAY are available to get independently each parameter. + * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetDate\n + * RTC_TSDR MT LL_RTC_TS_GetDate\n + * RTC_TSDR MU LL_RTC_TS_GetDate\n + * RTC_TSDR DT LL_RTC_TS_GetDate\n + * RTC_TSDR DU LL_RTC_TS_GetDate + * @param RTCx RTC Instance + * @retval Combination of Weekday, Day and Month + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); +} + +/** + * @brief Get time-stamp sub second value + * @rmtoll RTC_TSDR SS LL_RTC_TS_GetSubSecond + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); +} + +/** + * @brief Activate timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPTS); +} + +/** + * @brief Disable timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS); +} + + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Tamper Tamper + * @{ + */ + +/** + * @brief Enable TAMPx input detection + * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Enable\n + * TAMP_CR1 TAMP2E... LL_RTC_TAMPER_Enable\n + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Enable(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR1, Tamper); +} + +/** + * @brief Clear TAMPx input detection + * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Disable\n + * TAMP_CR1 TAMP2E... LL_RTC_TAMPER_Disable + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Disable(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR1, Tamper); +} + +/** + * @brief Enable Tamper mask flag + * @note Associated Tamper IT must not enabled when tamper mask is set. + * @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_EnableMask\n + * TAMP_CR2 TAMP2MF... LL_RTC_TAMPER_EnableMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_MASK + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(const RTC_TypeDef *RTCx, uint32_t Mask) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR2, Mask); +} + +/** + * @brief Disable Tamper mask flag + * @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_DisableMask\n + * TAMP_CR2 TAMP2MF... LL_RTC_TAMPER_DisableMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_MASK + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(const RTC_TypeDef *RTCx, uint32_t Mask) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR2, Mask); +} + +/** + * @brief Enable backup register erase after Tamper event detection + * @rmtoll TAMP_CR2 TAMP1POM LL_RTC_TAMPER_EnableEraseBKP\n + * TAMP_CR2 TAMP2POM... LL_RTC_TAMPER_EnableEraseBKP + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_NOERASE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Disable backup register erase after Tamper event detection + * @rmtoll TAMP_CR2 TAMP1POM LL_RTC_TAMPER_DisableEraseBKP\n + * TAMP_CR2 TAMP2POM... LL_RTC_TAMPER_DisableEraseBKP + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_NOERASE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins) + * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling) + * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Set RTC_TAMPx precharge duration + * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge + * @param RTCx RTC Instance + * @param Duration This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(const RTC_TypeDef *RTCx, uint32_t Duration) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration); +} + +/** + * @brief Get RTC_TAMPx precharge duration + * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH)); +} + +/** + * @brief Set RTC_TAMPx filter count + * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_SetFilterCount + * @param RTCx RTC Instance + * @param FilterCount This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(const RTC_TypeDef *RTCx, uint32_t FilterCount) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount); +} + +/** + * @brief Get RTC_TAMPx filter count + * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_GetFilterCount + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT)); +} + +/** + * @brief Set Tamper sampling frequency + * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq + * @param RTCx RTC Instance + * @param SamplingFreq This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(const RTC_TypeDef *RTCx, uint32_t SamplingFreq) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq); +} + +/** + * @brief Get Tamper sampling frequency + * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ)); +} + +/** + * @brief Enable Active level for Tamper input + * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n + * TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel\n + * TAMP_CR2 TAMPxTRG LL_RTC_TAMPER_EnableActiveLevel\n + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_ACTIVELEVEL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Disable Active level for Tamper input + * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n + * TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel\n + * TAMP_CR2 TAMPxTRG LL_RTC_TAMPER_DisableActiveLevel\n + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_ACTIVELEVEL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR2, Tamper); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Internal_Tamper Internal Tamper + * @{ + */ + +/** + * @brief Enable internal tamper detection. + * @rmtoll TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Enable\n + * TAMP_CR1 ITAMP2E LL_RTC_TAMPER_ITAMP_Enable\n + * TAMP_CR1 ITAMPxE LL_RTC_TAMPER_ITAMP_Enable + * @param RTCx RTC Instance + * @param InternalTamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_INTERNAL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(const RTC_TypeDef *RTCx, uint32_t InternalTamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR1, InternalTamper); +} + +/** + * @brief Disable internal tamper detection. + * @rmtoll TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Disable\n + * TAMP_CR1 ITAMP2E LL_RTC_TAMPER_ITAMP_Disable\n + * TAMP_CR1 ITAMPxE LL_RTC_TAMPER_ITAMP_Disable + * @param RTCx RTC Instance + * @param InternalTamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_INTERNAL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(const RTC_TypeDef *RTCx, uint32_t InternalTamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR1, InternalTamper); +} + +/** + * @brief Enable backup register erase after internal tamper event detection + * @rmtoll TAMP_CR3 ITAMP1POM LL_RTC_TAMPER_ITAMP_EnableEraseBKP\n + * TAMP_CR3 ITAMP2POM LL_RTC_TAMPER_ITAMP_EnableEraseBKP + * @param RTCx RTC Instance + * @param InternalTamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_ITAMPER_NOERASE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_EnableEraseBKP(const RTC_TypeDef *RTCx, uint32_t InternalTamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR3, InternalTamper); +} + +/** + * @brief Disable backup register erase after internal tamper event detection + * @rmtoll TAMP_CR3 ITAMP1POM LL_RTC_TAMPER_ITAMP_DisableEraseBKP\n + * TAMP_CR3 ITAMP2POM LL_RTC_TAMPER_ITAMP_DisableEraseBKP + * @param RTCx RTC Instance + * @param InternalTamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_ITAMPER_NOERASE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_DisableEraseBKP(const RTC_TypeDef *RTCx, uint32_t InternalTamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR3, InternalTamper); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Active_Tamper Active Tamper + * @{ + */ +/** + * @brief Enable tamper active mode. + * @rmtoll TAMP_ATCR1 TAMP1AM LL_RTC_TAMPER_ATAMP_EnableActiveMode\n + * @rmtoll TAMP_ATCR1 TAMP2AM LL_RTC_TAMPER_ATAMP_EnableActiveMode\n + * @rmtoll TAMP_ATCR1 TAMPxAM LL_RTC_TAMPER_ATAMP_EnableActiveMode + * @param Tamper to configure as active. This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_ACTIVE_MODE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableActiveMode(uint32_t Tamper) +{ + SET_BIT(TAMP->ATCR1, Tamper); +} + +/** + * @brief Disable tamper active mode. + * @rmtoll TAMP_ATCR1 TAMP1AM LL_RTC_TAMPER_ATAMP_DisableActiveMode\n + * @rmtoll TAMP_ATCR1 TAMP2AM LL_RTC_TAMPER_ATAMP_DisableActiveMode\n + * @rmtoll TAMP_ATCR1 TAMPxAM LL_RTC_TAMPER_ATAMP_DisableActiveMode + * @param Tamper to configure as active. This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_ACTIVE_MODE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableActiveMode(uint32_t Tamper) +{ + CLEAR_BIT(TAMP->ATCR1, Tamper); +} + +/** + * @brief Enable active tamper filter. + * @rmtoll TAMP_ATCR1 FLTEN LL_RTC_TAMPER_ATAMP_EnableFilter\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableFilter(void) +{ + SET_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN); +} + +/** + * @brief Disable active tamper filter. + * @rmtoll TAMP_ATCR1 FLTEN LL_RTC_TAMPER_ATAMP_DisableFilter\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableFilter(void) +{ + CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN); +} + +/** + * @brief Set Active tamper output change period. + * @rmtoll TAMP_ATCR1 ATPER LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod\n + * @param ActiveOutputChangePeriod This parameter can be a value from 0 to 7 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod(uint32_t ActiveOutputChangePeriod) +{ + MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATPER, (ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos)); +} + +/** + * @brief Get Active tamper output change period. + * @rmtoll TAMP_ATCR1 ATPER LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod\n + * @retval Output change period. This parameter can be a value from 0 to 7. + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod(void) +{ + return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATPER) >> TAMP_ATCR1_ATPER_Pos); +} + +/** + * @brief Set Active tamper asynchronous prescaler clock selection. + * @rmtoll TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler\n + * @param ActiveAsynvPrescaler Specifies the Active Tamper asynchronous Prescaler clock. + This parameter can be a value of the following values: + * @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler(uint32_t ActiveAsynvPrescaler) +{ + MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL, ActiveAsynvPrescaler); +} + +/** + * @brief Get Active tamper asynchronous prescaler clock selection. + * @rmtoll TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler\n + * @retval One of @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler(void) +{ + return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL)); +} + +/** + * @brief Enable active tamper output sharing. + * @rmtoll TAMP_ATCR1 ATOSHARE LL_RTC_TAMPER_ATAMP_EnableOutputSharing\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableOutputSharing(void) +{ + SET_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE); +} + +/** + * @brief Disable active tamper output sharing. + * @rmtoll TAMP_ATCR1 ATOSHARE LL_RTC_TAMPER_ATAMP_DisableOutputSharing\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableOutputSharing(void) +{ + CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE); +} + +/** + * @brief Set Active tamper shared output selection. + * @rmtoll TAMP_ATCR2 ATOSELx LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection\n + * @param OutputSelection Specifies all the output selection of the Active Tamper. + This parameter is a combinasation of the following values: + * One of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection(uint32_t OutputSelection) +{ +#if (RTC_TAMP_NB == 2U) + MODIFY_REG(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2), OutputSelection); +#elif (RTC_TAMP_NB == 3U) + MODIFY_REG(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3), OutputSelection); +#elif (RTC_TAMP_NB == 8U) + MODIFY_REG(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3 | TAMP_ATCR2_ATOSEL4 | \ + TAMP_ATCR2_ATOSEL5 | TAMP_ATCR2_ATOSEL6 | TAMP_ATCR2_ATOSEL7 | TAMP_ATCR2_ATOSEL8), \ + OutputSelection); +#endif /* RTC_TAMP_NB */ + +} + +/** + * @brief Get Active tamper shared output selection. + * @rmtoll TAMP_ATCR2 ATOSELx LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection\n + * @retval A combination of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection(void) +{ +#if (RTC_TAMP_NB == 2U) + return (READ_BIT(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2))); +#elif (RTC_TAMP_NB == 3U) + return (READ_BIT(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3))); +#elif (RTC_TAMP_NB == 8U) + return (READ_BIT(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3 | TAMP_ATCR2_ATOSEL4 | \ + TAMP_ATCR2_ATOSEL5 | TAMP_ATCR2_ATOSEL6 | TAMP_ATCR2_ATOSEL7 | TAMP_ATCR2_ATOSEL8))); +#endif /* RTC_TAMP_NB */ +} + +/** + * @brief Write active tamper seed. + * @rmtoll TAMP_ATSEEDR SEED LL_RTC_TAMPER_ATAMP_WriteSeed\n + * @param Seed + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_WriteSeed(uint32_t Seed) +{ + WRITE_REG(TAMP->ATSEEDR, Seed); +} + +/** + * @brief Get active tamper initialization status flag. + * @rmtoll TAMP_ATOR INITS LL_RTC_IsActiveFlag_ATAMP_INITS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_INITS(void) +{ + return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == (TAMP_ATOR_INITS)) ? 1U : 0U); +} + +/** + * @brief Get active tamper seed running status flag. + * @rmtoll TAMP_ATOR SEEDF LL_RTC_IsActiveFlag_ATAMP_SEEDF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_SEEDF(void) +{ + return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) == (TAMP_ATOR_SEEDF)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Wakeup Wakeup + * @{ + */ + +/** + * @brief Enable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_WUTE); +} + +/** + * @brief Disable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_WUTE); +} + +/** + * @brief Check if Wakeup timer is enabled or not + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_IsEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1U : 0U); +} + +/** + * @brief Select Wakeup clock + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ICSR WUTWF bit = 1 + * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_SetClock + * @param RTCx RTC Instance + * @param WakeupClock This parameter can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock) +{ + MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock); +} + +/** + * @brief Get Wakeup clock + * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_GetClock + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); +} + +/** + * @brief Set Wakeup auto-reload value + * @note Bit can be written only when WUTWF is set to 1 in RTC_ICSR + * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_SetAutoReload + * @param RTCx RTC Instance + * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value) +{ + MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); +} + +/** + * @brief Get Wakeup auto-reload value + * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_GetAutoReload + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers + * @{ + */ + +/** + * @brief Writes a data in a specified Backup data register. + * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_SetRegister + * @param RTCx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg LL_RTC_BKP_DRx ... + * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_BKP_SetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) +{ + __IO uint32_t tmp; + + UNUSED(RTCx); + + tmp = (uint32_t)(&(TAMP->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_GetRegister + * @param RTCx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg LL_RTC_BKP_DRx ... + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister) +{ + uint32_t tmp; + + UNUSED(RTCx); + + tmp = (uint32_t)(&(TAMP->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Calibration Calibration + * @{ + */ + +#if defined(RTC_CR_COE) +/** + * @brief Set Calibration output frequency (1 Hz or 512 Hz) + * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR COE LL_RTC_CAL_SetOutputFreq\n + * RTC_CR COSEL LL_RTC_CAL_SetOutputFreq + * @param RTCx RTC Instance + * @param Frequency This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency) +{ + MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency); +} + +/** + * @brief Get Calibration output frequency (1 Hz or 512 Hz) + * @rmtoll RTC_CR COE LL_RTC_CAL_GetOutputFreq\n + * RTC_CR COSEL LL_RTC_CAL_GetOutputFreq + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); +} +#endif /* RTC_CR_COE */ + +/** + * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR + * @rmtoll RTC_CALR CALP LL_RTC_CAL_SetPulse + * @param RTCx RTC Instance + * @param Pulse This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE + * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse); +} + +/** + * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm) + * @rmtoll RTC_CALR CALP LL_RTC_CAL_IsPulseInserted + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1U : 0U); +} + +/** + * @brief Set the calibration cycle period + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR + * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_SetPeriod\n + * RTC_CALR CALW16 LL_RTC_CAL_SetPeriod + * @param RTCx RTC Instance + * @param Period This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period); +} + +/** + * @brief Get the calibration cycle period + * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_GetPeriod\n + * RTC_CALR CALW16 LL_RTC_CAL_GetPeriod + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); +} + +/** + * @brief Set Calibration minus + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR + * @rmtoll RTC_CALR CALM LL_RTC_CAL_SetMinus + * @param RTCx RTC Instance + * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus); +} + +/** + * @brief Get Calibration minus + * @rmtoll RTC_CALR CALM LL_RTC_CAL_GetMinus + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); +} + +/** + * @brief Enable Calibration Low Power + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_LowPower_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CALR, RTC_CALR_LPCAL); +} + +/** + * @brief Disable Calibration Low Power + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_LowPower_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CALR, RTC_CALR_LPCAL); +} + +/** + * @brief Check if Calibration Low Power is enabled or not + * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_IsEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CALR, RTC_CALR_LPCAL) == (RTC_CALR_LPCAL)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Internal Time-stamp flag + * @rmtoll RTC_SR ITSF LL_RTC_IsActiveFlag_ITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1U : 0U); +} + +/** + * @brief Get Recalibration pending Flag + * @rmtoll RTC_ICSR RECALPF LL_RTC_IsActiveFlag_RECALP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp overflow flag + * @rmtoll RTC_SR TSOVF LL_RTC_IsActiveFlag_TSOV + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp flag + * @rmtoll RTC_SR TSF LL_RTC_IsActiveFlag_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1U : 0U); +} + +/** + * @brief Get Wakeup timer flag + * @rmtoll RTC_SR WUTF LL_RTC_IsActiveFlag_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm B flag + * @rmtoll RTC_SR ALRBF LL_RTC_IsActiveFlag_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm A flag + * @rmtoll RTC_SR ALRAF LL_RTC_IsActiveFlag_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1U : 0U); +} + +/** + * @brief Get SSR Underflow flag + * @rmtoll RTC_SR SSRUF LL_RTC_IsActiveFlag_SSRU + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRU(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_SSRUF) == (RTC_SR_SSRUF)) ? 1U : 0U); +} + +/** + * @brief Clear Internal Time-stamp flag + * @rmtoll RTC_SCR CITSF LL_RTC_ClearFlag_ITS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CITSF); +} + +/** + * @brief Clear Time-stamp overflow flag + * @rmtoll RTC_SCR CTSOVF LL_RTC_ClearFlag_TSOV + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CTSOVF); +} + +/** + * @brief Clear Time-stamp flag + * @rmtoll RTC_SCR CTSF LL_RTC_ClearFlag_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CTSF); +} + +/** + * @brief Clear Wakeup timer flag + * @rmtoll RTC_SCR CWUTF LL_RTC_ClearFlag_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CWUTF); +} + +/** + * @brief Clear Alarm B flag + * @rmtoll RTC_SCR CALRBF LL_RTC_ClearFlag_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CALRBF); +} + +/** + * @brief Clear Alarm A flag + * @rmtoll RTC_SCR CALRAF LL_RTC_ClearFlag_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CALRAF); +} + +/** + * @brief Clear SSR Underflow flag + * @rmtoll RTC_SCR CSSRUF LL_RTC_ClearFlag_SSRU + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_SSRU(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CSSRUF); +} + +/** + * @brief Get Initialization flag + * @rmtoll RTC_ICSR INITF LL_RTC_IsActiveFlag_INIT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1U : 0U); +} + +/** + * @brief Get Registers synchronization flag + * @rmtoll RTC_ICSR RSF LL_RTC_IsActiveFlag_RS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1U : 0U); +} + +/** + * @brief Clear Registers synchronization flag + * @rmtoll RTC_ICSR RSF LL_RTC_ClearFlag_RS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT))); +} + +/** + * @brief Get Initialization status flag + * @rmtoll RTC_ICSR INITS LL_RTC_IsActiveFlag_INITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1U : 0U); +} + +/** + * @brief Get Shift operation pending flag + * @rmtoll RTC_ICSR SHPF LL_RTC_IsActiveFlag_SHP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1U : 0U); +} + +/** + * @brief Get Wakeup timer write flag + * @rmtoll RTC_ICSR WUTWF LL_RTC_IsActiveFlag_WUTW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm A masked flag. + * @rmtoll RTC_MISR ALRAMF LL_RTC_IsActiveFlag_ALRAM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1U : 0U); +} + +/** + * @brief Get SSR Underflow masked flag. + * @rmtoll RTC_MISR SSRUMF LL_RTC_IsActiveFlag_SSRUM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRUM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_SSRUMF) == (RTC_MISR_SSRUMF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm B masked flag. + * @rmtoll RTC_MISR ALRBMF LL_RTC_IsActiveFlag_ALRBM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1U : 0U); +} + +/** + * @brief Get Wakeup timer masked flag. + * @rmtoll RTC_MISR WUTMF LL_RTC_IsActiveFlag_WUTM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp masked flag. + * @rmtoll RTC_MISR TSMF LL_RTC_IsActiveFlag_TSM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp overflow masked flag. + * @rmtoll RTC_MISR TSOVMF LL_RTC_IsActiveFlag_TSOVM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1U : 0U); +} + +/** + * @brief Get Internal Time-stamp masked flag. + * @rmtoll RTC_MISR ITSMF LL_RTC_IsActiveFlag_ITSM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 1 detection flag. + * @rmtoll TAMP_SR TAMP1F LL_RTC_IsActiveFlag_TAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 2 detection flag. + * @rmtoll TAMP_SR TAMP2F LL_RTC_IsActiveFlag_TAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1U : 0U); +} + +#if (RTC_TAMP_NB > 2U) +/** + * @brief Get tamper 3 detection flag. + * @rmtoll TAMP_SR TAMP3F LL_RTC_IsActiveFlag_TAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 4 detection flag. + * @rmtoll TAMP_SR TAMP4F LL_RTC_IsActiveFlag_TAMP4 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP4F) == (TAMP_SR_TAMP4F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 5 detection flag. + * @rmtoll TAMP_SR TAMP5F LL_RTC_IsActiveFlag_TAMP5 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP5F) == (TAMP_SR_TAMP5F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 6 detection flag. + * @rmtoll TAMP_SR TAMP6F LL_RTC_IsActiveFlag_TAMP6 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP6F) == (TAMP_SR_TAMP6F)) ? 1U : 0U); +} +#endif /* (RTC_TAMP_NB > 2U) */ + +#if (RTC_TAMP_NB > 6U) +/** + * @brief Get tamper 7 detection flag. + * @rmtoll TAMP_SR TAMP7F LL_RTC_IsActiveFlag_TAMP7 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP7F) == (TAMP_SR_TAMP7F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 8 detection flag. + * @rmtoll TAMP_SR TAMP8F LL_RTC_IsActiveFlag_TAMP8 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP8F) == (TAMP_SR_TAMP8F)) ? 1U : 0U); +} +#endif /* (RTC_TAMP_NB > 6U) */ + +/** + * @brief Get internal tamper 1 detection flag. + * @rmtoll TAMP_SR ITAMP1F LL_RTC_IsActiveFlag_ITAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP1F) == (TAMP_SR_ITAMP1F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 2 detection flag. + * @rmtoll TAMP_SR ITAMP2F LL_RTC_IsActiveFlag_ITAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP2F) == (TAMP_SR_ITAMP2F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 3 detection flag. + * @rmtoll TAMP_SR ITAMP3F LL_RTC_IsActiveFlag_ITAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP3F) == (TAMP_SR_ITAMP3F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 4 detection flag. + * @rmtoll TAMP_SR ITAMP4F LL_RTC_IsActiveFlag_ITAMP4 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP4F) == (TAMP_SR_ITAMP4F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 5 detection flag. + * @rmtoll TAMP_SR ITAMP5F LL_RTC_IsActiveFlag_ITAMP5 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP5F) == (TAMP_SR_ITAMP5F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 6 detection flag. + * @rmtoll TAMP_SR ITAMP6F LL_RTC_IsActiveFlag_ITAMP6 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP6F) == (TAMP_SR_ITAMP6F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 7 detection flag. + * @rmtoll TAMP_SR ITAMP7F LL_RTC_IsActiveFlag_ITAMP7 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP7F) == (TAMP_SR_ITAMP7F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 8 detection flag. + * @rmtoll TAMP_SR ITAMP8F LL_RTC_IsActiveFlag_ITAMP8 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP8F) == (TAMP_SR_ITAMP8F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 9 detection flag. + * @rmtoll TAMP_SR ITAMP9F LL_RTC_IsActiveFlag_ITAMP9 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP9(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP9F) == (TAMP_SR_ITAMP9F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 11 detection flag. + * @rmtoll TAMP_SR ITAMP11F LL_RTC_IsActiveFlag_ITAMP11 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP11(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP11F) == (TAMP_SR_ITAMP11F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 15 detection flag. + * @rmtoll TAMP_SR ITAMP15F LL_RTC_IsActiveFlag_ITAMP15 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP15(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP15F) == (TAMP_SR_ITAMP15F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 1 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP1MF LL_RTC_IsActiveFlag_TAMP1M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 2 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP2MF LL_RTC_IsActiveFlag_TAMP2M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1U : 0U); +} + +#if (RTC_TAMP_NB > 2U) +/** + * @brief Get tamper 3 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP3M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 4 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP4MF LL_RTC_IsActiveFlag_TAMP4M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP4MF) == (TAMP_MISR_TAMP4MF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 5 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP5MF LL_RTC_IsActiveFlag_TAMP5M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP5MF) == (TAMP_MISR_TAMP5MF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 6 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP6MF LL_RTC_IsActiveFlag_TAMP6M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP6MF) == (TAMP_MISR_TAMP6MF)) ? 1U : 0U); +} +#endif /* (RTC_TAMP_NB > 2U) */ + +#if (RTC_TAMP_NB > 6U) +/** + * @brief Get tamper 7 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP7MF LL_RTC_IsActiveFlag_TAMP7M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP7MF) == (TAMP_MISR_TAMP7MF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 8 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP8MF LL_RTC_IsActiveFlag_TAMP8M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP8MF) == (TAMP_MISR_TAMP8MF)) ? 1U : 0U); +} +#endif /* (RTC_TAMP_NB > 6U) */ + +/** + * @brief Get internal tamper 1 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP1MF LL_RTC_IsActiveFlag_ITAMP1M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP1MF) == (TAMP_MISR_ITAMP1MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 2 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP2MF LL_RTC_IsActiveFlag_ITAMP2M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP2MF) == (TAMP_MISR_ITAMP2MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 3 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP3MF LL_RTC_IsActiveFlag_ITAMP3M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP3MF) == (TAMP_MISR_ITAMP3MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 4 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP4MF LL_RTC_IsActiveFlag_ITAMP4M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP4MF) == (TAMP_MISR_ITAMP4MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 5 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP5MF LL_RTC_IsActiveFlag_ITAMP5M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP5MF) == (TAMP_MISR_ITAMP5MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 6 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP6MF LL_RTC_IsActiveFlag_ITAMP6M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP6MF) == (TAMP_MISR_ITAMP6MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 7 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP7MF LL_RTC_IsActiveFlag_ITAMP7M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP7M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP7MF) == (TAMP_MISR_ITAMP7MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 8 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP8MF LL_RTC_IsActiveFlag_ITAMP8M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP8MF) == (TAMP_MISR_ITAMP8MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 9 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP9MF LL_RTC_IsActiveFlag_ITAMP9M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP9M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP9MF) == (TAMP_MISR_ITAMP9MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 11 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP11MF LL_RTC_IsActiveFlag_ITAMP11M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP11M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP11MF) == (TAMP_MISR_ITAMP11MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 15 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP15MF LL_RTC_IsActiveFlag_ITAMP15M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP15M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP15MF) == (TAMP_MISR_ITAMP15MF)) ? 1U : 0U); +} + +/** + * @brief Clear tamper 1 detection flag. + * @rmtoll TAMP_SCR CTAMP1F LL_RTC_ClearFlag_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP1F); +} + +/** + * @brief Clear tamper 2 detection flag. + * @rmtoll TAMP_SCR CTAMP2F LL_RTC_ClearFlag_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP2F); +} + +#if (RTC_TAMP_NB > 2U) +/** + * @brief Clear tamper 3 detection flag. + * @rmtoll TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP3F); +} + +/** + * @brief Clear tamper 4 detection flag. + * @rmtoll TAMP_SCR CTAMP4F LL_RTC_ClearFlag_TAMP4 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP4F); +} + +/** + * @brief Clear tamper 5 detection flag. + * @rmtoll TAMP_SCR CTAMP5F LL_RTC_ClearFlag_TAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP5F); +} + +/** + * @brief Clear tamper 6 detection flag. + * @rmtoll TAMP_SCR CTAMP6F LL_RTC_ClearFlag_TAMP6 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP6F); +} +#endif /* (RTC_TAMP_NB > 2U) */ + +#if (RTC_TAMP_NB > 6U) +/** + * @brief Clear tamper 7 detection flag. + * @rmtoll TAMP_SCR CTAMP7F LL_RTC_ClearFlag_TAMP7 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP7F); +} + +/** + * @brief Clear tamper 8 detection flag. + * @rmtoll TAMP_SCR CTAMP8F LL_RTC_ClearFlag_TAMP8 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP8F); +} +#endif /* (RTC_TAMP_NB > 6U) */ + +/** + * @brief Clear internal tamper 1 detection flag. + * @rmtoll TAMP_SCR CITAMP1F LL_RTC_ClearFlag_ITAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP1F); +} + +/** + * @brief Clear internal tamper 2 detection flag. + * @rmtoll TAMP_SCR CITAMP2F LL_RTC_ClearFlag_ITAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP2F); +} + +/** + * @brief Clear internal tamper 3 detection flag. + * @rmtoll TAMP_SCR CITAMP3F LL_RTC_ClearFlag_ITAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP3F); +} + +/** + * @brief Clear internal tamper 4 detection flag. + * @rmtoll TAMP_SCR CITAMP4F LL_RTC_ClearFlag_ITAMP4 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP4(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP4F); +} + +/** + * @brief Clear internal tamper 5 detection flag. + * @rmtoll TAMP_SCR CITAMP5F LL_RTC_ClearFlag_ITAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP5F); +} + +/** + * @brief Clear internal tamper 6 detection flag. + * @rmtoll TAMP_SCR CITAMP6F LL_RTC_ClearFlag_ITAMP6 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP6F); +} + +/** + * @brief Clear internal tamper 7 detection flag. + * @rmtoll TAMP_SCR CITAMP7F LL_RTC_ClearFlag_ITAMP7 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP7F); +} + +/** + * @brief Clear internal tamper 8 detection flag. + * @rmtoll TAMP_SCR CITAMP8F LL_RTC_ClearFlag_ITAMP8 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP8F); +} + +/** + * @brief Clear internal tamper 9 detection flag. + * @rmtoll TAMP_SCR CITAMP9F LL_RTC_ClearFlag_ITAMP9 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP9(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP9F); +} + +/** + * @brief Clear internal tamper 11 detection flag. + * @rmtoll TAMP_SCR CITAMP11F LL_RTC_ClearFlag_ITAMP11 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP11(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP11F); +} + +/** + * @brief Clear internal tamper 15 detection flag. + * @rmtoll TAMP_SCR CITAMP15F LL_RTC_ClearFlag_ITAMP15 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP15(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP15F); +} + +/** + * @} + */ + +#if defined(RTC_PRIVCFGR_PRIV) +/** @defgroup RTC_LL_EF_PRIVILEGE PRIVILEGE_Management + * @{ + */ + +/** + * @brief Set RTC privilege level. + * @note Privilege features are relevant if LL_RTC_PRIVILEGE_FULL_NO. + * @rmtoll RTC_PRIVCFGR PRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR INITPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR CALPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR TSPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR WUTPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR ALRAPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR ALRBPRIV LL_RTC_SetRtcPrivilege + * @param RTCx RTC Instance + * @param rtcPrivilege This parameter can be a combination of the following values: + * @arg @ref LL_RTC_PRIVILEGE_FULL_YES + * @arg @ref LL_RTC_PRIVILEGE_FULL_NO + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_INIT + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_CAL + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_TS + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_WUT + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRA + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRB + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetRtcPrivilege(RTC_TypeDef *RTCx, uint32_t rtcPrivilege) +{ + MODIFY_REG(RTCx->PRIVCFGR, RTC_PRIVCFGR_PRIV | RTC_PRIVCFGR_INITPRIV | RTC_PRIVCFGR_CALPRIV | RTC_PRIVCFGR_TSPRIV | \ + RTC_PRIVCFGR_WUTPRIV | RTC_PRIVCFGR_ALRAPRIV | RTC_PRIVCFGR_ALRBPRIV, rtcPrivilege); +} + +/** + * @brief Get RTC privilege level. + * @note Privilege features are relevant if LL_RTC_PRIVILEGE_FULL_NO. + * @rmtoll RTC_PRIVCFGR PRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR INITPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR CALPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR TSPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR WUTPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR ALRAPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR ALRBPRIV LL_RTC_SetRtcPrivilege + * @param RTCx RTC Instance + * @retval Combination of the following values: + * @arg @ref LL_RTC_PRIVILEGE_FULL_YES + * @arg @ref LL_RTC_PRIVILEGE_FULL_NO + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_INIT + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_CAL + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_TS + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_WUT + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRA + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRB + */ +__STATIC_INLINE uint32_t LL_RTC_GetRtcPrivilege(const RTC_TypeDef *RTCx) +{ + return READ_BIT(RTCx->PRIVCFGR, RTC_PRIVCFGR_PRIV | RTC_PRIVCFGR_INITPRIV | RTC_PRIVCFGR_CALPRIV | \ + RTC_PRIVCFGR_TSPRIV | RTC_PRIVCFGR_WUTPRIV | RTC_PRIVCFGR_ALRAPRIV | \ + RTC_PRIVCFGR_ALRBPRIV); +} + +/** + * @brief Set TAMPER privilege level. + * @rmtoll TAMP_PRIVCFGR TAMPPRIV LL_RTC_SetTampPrivilege + * @param RTCx RTC Instance + * @param tampPrivilege This parameter can be one of the following values: + * @arg @ref LL_TAMP_PRIVILEGE_FULL_YES + * @arg @ref LL_TAMP_PRIVILEGE_FULL_NO + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetTampPrivilege(const RTC_TypeDef *RTCx, uint32_t tampPrivilege) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->PRIVCFGR, TAMP_PRIVCFGR_TAMPPRIV, tampPrivilege); +} + +/** + * @brief Get TAMPER privilege level. + * @rmtoll TAMP_PRIVCFGR TAMPPRIV LL_RTC_GetTampPrivilege + * @param RTCx RTC Instance + * @retval This parameter can be one of the following values: + * @arg @ref LL_TAMP_PRIVILEGE_FULL_YES + * @arg @ref LL_TAMP_PRIVILEGE_FULL_NO + */ +__STATIC_INLINE uint32_t LL_RTC_GetTampPrivilege(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_BIT(TAMP->PRIVCFGR, TAMP_PRIVCFGR_TAMPPRIV); +} + +/** + * @brief Set Backup Registers privilege level. + * @rmtoll TAMP_PRIVCFGR BKPWPRIV LL_RTC_SetBackupRegisterPrivilege + * @rmtoll TAMP_PRIVCFGR BKPRWPRIV LL_RTC_SetBackupRegisterPrivilege + * @param RTCx RTC Instance + * @param bckupRegisterPrivilege This parameter can be one of the following values: + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_NONE + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_1 + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_2 + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_ALL + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetBackupRegisterPrivilege(const RTC_TypeDef *RTCx, uint32_t bckupRegisterPrivilege) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->PRIVCFGR, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV), bckupRegisterPrivilege); +} + +/** + * @brief Get Backup Registers privilege level. + * @rmtoll TAMP_PRIVCFGR BKPWPRIV LL_RTC_GetBackupRegisterPrivilege + * @rmtoll TAMP_PRIVCFGR BKPRWPRIV LL_RTC_GetBackupRegisterPrivilege + * @param RTCx RTC Instance + * @retval This parameter can be one of the following values: + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_NONE + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_1 + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_2 + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_GetBackupRegisterPrivilege(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_BIT(TAMP->PRIVCFGR, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV)); +} +/** + * @} + */ +#endif /* RTC_PRIVCFGR_PRIV */ + +/** @defgroup RTC_LL_EF_BACKUP_REG_PROTECTION PROTECTION_BACKUP_REG_Management + * @brief Backup register protection is common to security and privilege. + * @{ + */ + +/** + * @brief Set Backup registers protection level. + * @note Zone 1 : read protection write protection + * @note Zone 2 : read non-protection write protection + * @note Zone 3 : read non-protection write non-protection + * @note zone 1 : start from 0 to startZone2 start value + * @note zone 2 : start from startZone2 start value to startZone3 start value + * @note zone 3 : start from to startZone3 to the end of BACKUPREG + * @rmtoll TAMP_CFGR BKPW LL_RTC_SetBackupRegProtection + * @rmtoll TAMP_CFGR BKPRW LL_RTC_SetBackupRegProtection + * @param RTCx RTC Instance + * @param startZone2 This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg LL_RTC_BKP_DRx ... + * @param startZone3 This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg LL_RTC_BKP_DRx ... + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetBackupRegProtection(const RTC_TypeDef *RTCx, uint32_t startZone2, uint32_t startZone3) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->CFGR, (TAMP_CFGR_BKPRW_Msk | TAMP_CFGR_BKPW_Msk), + (startZone2 << TAMP_CFGR_BKPRW_Pos) | (startZone3 << TAMP_CFGR_BKPW_Pos)); +} + +/** + * @brief Get Backup registers protection level start zone 2. + * @note Zone 1 : read protection write protection + * @note Zone 2 : read non-protection/non-privile write protection + * @note Zone 3 : read non-protection write non-protection + * @rmtoll TAMP_CFGR BKPRW LL_RTC_GetBackupRegProtectionStartZone2 + * @param RTCx RTC Instance + * @retval Start zone 2 + */ +__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_BIT(TAMP->CFGR, TAMP_CFGR_BKPRW_Msk) >> TAMP_CFGR_BKPRW_Pos; +} + +/** + * @brief Get Backup registers protection level start zone 3. + * @note Zone 1 : read protection write protection + * @note Zone 2 : read non-protection write protection + * @note Zone 3 : read non-protection write non-protection + * @rmtoll TAMP_CFGR BKPW LL_RTC_GetBackupRegProtectionStartZone3 + * @param RTCx RTC Instance + * @retval Start zone 2 + */ +__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_BIT(TAMP->CFGR, TAMP_CFGR_BKPW_Msk) >> TAMP_CFGR_BKPW_Pos; +} +/** + * @} + */ + +/** @defgroup RTC_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSIE LL_RTC_EnableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Disable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSIE LL_RTC_DisableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Enable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTIE LL_RTC_EnableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Disable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTIE LL_RTC_DisableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Enable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBIE LL_RTC_EnableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Disable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBIE LL_RTC_DisableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Enable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAIE LL_RTC_EnableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Disable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAIE LL_RTC_DisableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Enable SSR Underflow interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR SSRUIE LL_RTC_EnableIT_SSRU + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_SSRU(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_SSRUIE); +} + +/** + * @brief Disable SSR Underflow interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR SSRUIE LL_RTC_DisableIT_SSRU + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_SSRU(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_SSRUIE); +} + +/** + * @brief Check if Time-stamp interrupt is enabled or not + * @rmtoll RTC_CR TSIE LL_RTC_IsEnabledIT_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1U : 0U); +} + +/** + * @brief Check if Wakeup timer interrupt is enabled or not + * @rmtoll RTC_CR WUTIE LL_RTC_IsEnabledIT_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1U : 0U); +} + +/** + * @brief Check if Alarm B interrupt is enabled or not + * @rmtoll RTC_CR ALRBIE LL_RTC_IsEnabledIT_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1U : 0U); +} + +/** + * @brief Check if Alarm A interrupt is enabled or not + * @rmtoll RTC_CR ALRAIE LL_RTC_IsEnabledIT_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1U : 0U); +} + +/** + * @brief Check if SSR Underflow interrupt is enabled or not + * @rmtoll RTC_CR SSRUIE LL_RTC_IsEnabledIT_SSRU + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SSRU(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_SSRUIE) == (RTC_CR_SSRUIE)) ? 1U : 0U); +} + +/** + * @brief Enable tamper 1 interrupt. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_EnableIT_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP1IE); +} + +/** + * @brief Disable tamper 1 interrupt. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_DisableIT_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP1IE); +} + +/** + * @brief Enable tamper 2 interrupt. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_EnableIT_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP2IE); +} + +/** + * @brief Disable tamper 2 interrupt. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_DisableIT_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP2IE); +} + +#if (RTC_TAMP_NB > 2U) +/** + * @brief Enable tamper 3 interrupt. + * @rmtoll TAMP_IER TAMP3IE LL_RTC_EnableIT_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP3IE); +} + +/** + * @brief Disable tamper 3 interrupt. + * @rmtoll TAMP_IER TAMP3IE LL_RTC_DisableIT_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP3IE); +} + +/** + * @brief Enable tamper 4 interrupt. + * @rmtoll TAMP_IER TAMP4IE LL_RTC_EnableIT_TAMP4 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP4(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP4IE); +} + +/** + * @brief Disable tamper 4 interrupt. + * @rmtoll TAMP_IER TAMP4IE LL_RTC_DisableIT_TAMP4 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP4(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP4IE); +} + +/** + * @brief Enable tamper 5 interrupt. + * @rmtoll TAMP_IER TAMP5IE LL_RTC_EnableIT_TAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP5IE); +} + +/** + * @brief Disable tamper 5 interrupt. + * @rmtoll TAMP_IER TAMP5IE LL_RTC_DisableIT_TAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP5IE); +} + +/** + * @brief Enable tamper 6 interrupt. + * @rmtoll TAMP_IER TAMP6IE LL_RTC_EnableIT_TAMP6 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP6IE); +} + +/** + * @brief Disable tamper 6 interrupt. + * @rmtoll TAMP_IER TAMP6IE LL_RTC_DisableIT_TAMP6 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP6IE); +} +#endif /* (RTC_TAMP_NB > 2U) */ + +#if (RTC_TAMP_NB > 6U) +/** + * @brief Enable tamper 7 interrupt. + * @rmtoll TAMP_IER TAMP7IE LL_RTC_EnableIT_TAMP7 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP7IE); +} + +/** + * @brief Disable tamper 7 interrupt. + * @rmtoll TAMP_IER TAMP7IE LL_RTC_DisableIT_TAMP7 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP7IE); +} + +/** + * @brief Enable tamper 8 interrupt. + * @rmtoll TAMP_IER TAMP8IE LL_RTC_EnableIT_TAMP8 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP8IE); +} + +/** + * @brief Disable tamper 8 interrupt. + * @rmtoll TAMP_IER TAMP8IE LL_RTC_DisableIT_TAMP8 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP8IE); +} +#endif /* (RTC_TAMP_NB > 6U) */ + +/** + * @brief Enable internal tamper 1 interrupt. + * @rmtoll TAMP_IER ITAMP1IE LL_RTC_EnableIT_ITAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP1IE); +} + +/** + * @brief Disable internal tamper 1 interrupt. + * @rmtoll TAMP_IER ITAMP1IE LL_RTC_DisableIT_ITAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP1IE); +} + +/** + * @brief Enable internal tamper 2 interrupt. + * @rmtoll TAMP_IER ITAMP2IE LL_RTC_EnableIT_ITAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP2IE); +} + +/** + * @brief Disable internal tamper 2 interrupt. + * @rmtoll TAMP_IER ITAMP2IE LL_RTC_DisableIT_ITAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP2IE); +} + +/** + * @brief Enable internal tamper 3 interrupt. + * @rmtoll TAMP_IER ITAMP3IE LL_RTC_EnableIT_ITAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP3IE); +} + +/** + * @brief Disable internal tamper 3 interrupt. + * @rmtoll TAMP_IER ITAMP3IE LL_RTC_DisableIT_ITAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP3IE); +} + +/** + * @brief Enable internal tamper 4 interrupt. + * @rmtoll TAMP_IER ITAMP4IE LL_RTC_EnableIT_ITAMP4 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP4(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP4IE); +} + +/** + * @brief Disable internal tamper 4 interrupt. + * @rmtoll TAMP_IER ITAMP4IE LL_RTC_DisableIT_ITAMP4 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP4(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP4IE); +} + +/** + * @brief Enable internal tamper 5 interrupt. + * @rmtoll TAMP_IER ITAMP5IE LL_RTC_EnableIT_ITAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP5IE); +} + +/** + * @brief Disable internal tamper 5 interrupt. + * @rmtoll TAMP_IER ITAMP5IE LL_RTC_DisableIT_ITAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP5IE); +} + +/** + * @brief Enable internal tamper 6 interrupt. + * @rmtoll TAMP_IER ITAMP6IE LL_RTC_EnableIT_ITAMP6 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP6IE); +} + +/** + * @brief Disable internal tamper 6 interrupt. + * @rmtoll TAMP_IER ITAMP6IE LL_RTC_DisableIT_ITAMP6 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP6IE); +} + +/** + * @brief Enable internal tamper 7 interrupt. + * @rmtoll TAMP_IER ITAMP7IE LL_RTC_EnableIT_ITAMP7 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP7IE); +} + +/** + * @brief Disable internal tamper 7 interrupt. + * @rmtoll TAMP_IER ITAMP7IE LL_RTC_DisableIT_ITAMP7 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP7IE); +} + +/** + * @brief Enable internal tamper 8 interrupt. + * @rmtoll TAMP_IER ITAMP8IE LL_RTC_EnableIT_ITAMP8 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP8IE); +} + +/** + * @brief Disable internal tamper 8 interrupt. + * @rmtoll TAMP_IER ITAMP8IE LL_RTC_DisableIT_ITAMP8 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP8IE); +} + +/** + * @brief Enable internal tamper 9 interrupt. + * @rmtoll TAMP_IER ITAMP9IE LL_RTC_EnableIT_ITAMP9 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP9(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP9IE); +} + +/** + * @brief Disable internal tamper 9 interrupt. + * @rmtoll TAMP_IER ITAMP9IE LL_RTC_DisableIT_ITAMP9 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP9(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP9IE); +} + +/** + * @brief Enable internal tamper 11 interrupt. + * @rmtoll TAMP_IER ITAMP11IE LL_RTC_EnableIT_ITAMP11 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP11(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP11IE); +} + +/** + * @brief Disable internal tamper 11 interrupt. + * @rmtoll TAMP_IER ITAMP11IE LL_RTC_DisableIT_ITAMP11 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP11(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP11IE); +} + +/** + * @brief Enable internal tamper 15 interrupt. + * @rmtoll TAMP_IER ITAMP15IE LL_RTC_EnableIT_ITAMP15 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP15(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP15IE); +} + +/** + * @brief Disable internal tamper 15 interrupt. + * @rmtoll TAMP_IER ITAMP15IE LL_RTC_DisableIT_ITAMP15 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP15(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP15IE); +} + +/** + * @brief Check if tamper 1 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1U : 0U); +} + +/** + * @brief Check if tamper 2 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_IsEnabledIT_TAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1U : 0U); +} + +#if (RTC_TAMP_NB > 2U) +/** + * @brief Check if tamper 3 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP3IE LL_RTC_IsEnabledIT_TAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1U : 0U); +} + +/** + * @brief Check if tamper 4 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP4IE LL_RTC_IsEnabledIT_TAMP4 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP4IE) == (TAMP_IER_TAMP4IE)) ? 1U : 0U); +} + +/** + * @brief Check if tamper 5 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP5IE LL_RTC_IsEnabledIT_TAMP5 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP5IE) == (TAMP_IER_TAMP5IE)) ? 1U : 0U); +} + +/** + * @brief Check if tamper 6 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP6IE LL_RTC_IsEnabledIT_TAMP6 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP6IE) == (TAMP_IER_TAMP6IE)) ? 1U : 0U); +} +#endif /* (RTC_TAMP_NB > 2U) */ + +#if (RTC_TAMP_NB > 6U) +/** + * @brief Check if tamper 7 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP7IE LL_RTC_IsEnabledIT_TAMP7 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP7IE) == (TAMP_IER_TAMP7IE)) ? 1U : 0U); +} + +/** + * @brief Check if tamper 8 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP8IE LL_RTC_IsEnabledIT_TAMP8 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP8IE) == (TAMP_IER_TAMP8IE)) ? 1U : 0U); +} +#endif /* (RTC_TAMP_NB > 6U) */ + +/** + * @brief Check if internal tamper 1 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP1IE LL_RTC_IsEnabledIT_ITAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP1IE) == (TAMP_IER_ITAMP1IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 2 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP2IE LL_RTC_IsEnabledIT_ITAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP2IE) == (TAMP_IER_ITAMP2IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 3 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP3IE LL_RTC_IsEnabledIT_ITAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP3IE) == (TAMP_IER_ITAMP3IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 4 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP4IE LL_RTC_IsEnabledIT_ITAMP4 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP4(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP4IE) == (TAMP_IER_ITAMP4IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 5 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP5IE LL_RTC_IsEnabledIT_ITAMP5 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP5IE) == (TAMP_IER_ITAMP5IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 6 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP6IE LL_RTC_IsEnabledIT_ITAMP6 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP6IE) == (TAMP_IER_ITAMP6IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 7 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP7IE LL_RTC_IsEnabledIT_ITAMP7 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP7IE) == (TAMP_IER_ITAMP7IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 8 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP8IE LL_RTC_IsEnabledIT_ITAMP8 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP8IE) == (TAMP_IER_ITAMP8IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 9 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP9IE LL_RTC_IsEnabledIT_ITAMP9 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP9(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP9IE) == (TAMP_IER_ITAMP9IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 11 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP11IE LL_RTC_IsEnabledIT_ITAMP11 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP11(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP11IE) == (TAMP_IER_ITAMP11IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 15 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP15IE LL_RTC_IsEnabledIT_ITAMP15 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP15(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP15IE) == (TAMP_IER_ITAMP15IE)) ? 1U : 0U); +} + +/** + * @brief Increment Monotonic counter. + * @rmtoll TAMP_COUNT1R COUNT LL_RTC_IncrementMonotonicCounter + * @param RTCx RTC Instance + * @retval None. + */ +__STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->COUNT1R, 0U); +} + +/** + * @brief Increment Monotonic counter. + * @rmtoll TAMP_COUNT1R COUNT LL_RTC_GetMonotonicCounter + * @param RTCx RTC Instance + * @retval Monotonic counter value. + */ +__STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_REG(TAMP->COUNT1R); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct); +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct); +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct); +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct); +ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct); +void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct); +ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_RTC_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_sdmmc.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_sdmmc.h new file mode 100644 index 00000000000..a5b24bbe21e --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_sdmmc.h @@ -0,0 +1,1164 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_sdmmc.h + * @author MCD Application Team + * @brief Header file of SDMMC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_SDMMC_H +#define STM32H7RSxx_LL_SDMMC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +/** @addtogroup STM32H7RSxx_Driver + * @{ + */ +#if defined (SDMMC1) || defined (SDMMC2) +/** @addtogroup SDMMC_LL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types + * @{ + */ + +/** + * @brief SDMMC Configuration Structure definition + */ +typedef struct +{ + uint32_t ClockEdge; /*!< Specifies the SDMMC_CCK clock transition on which Data and Command change. + This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ + + uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ + + uint32_t BusWide; /*!< Specifies the SDMMC bus width. + This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ + + uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ + + uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. + This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ + +#if (USE_SD_TRANSCEIVER != 0U) + uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher. + This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */ +#endif /* USE_SD_TRANSCEIVER */ +} SDMMC_InitTypeDef; + + +/** + * @brief SDMMC Command Control structure + */ +typedef struct +{ + uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register. */ + + uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and + Max_Data = 64 */ + + uint32_t Response; /*!< Specifies the SDMMC response type. + This parameter can be a value of @ref SDMMC_LL_Response_Type */ + + uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is + enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ + + uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_CPSM_State */ +} SDMMC_CmdInitTypeDef; + + +/** + * @brief SDMMC Data Control structure + */ +typedef struct +{ + uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ + + uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ + + uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ + + uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_DPSM_State */ +} SDMMC_DataInitTypeDef; + +/** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure + * @{ + */ +typedef struct +{ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list configuration register */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register */ +} SDMMC_DMALinkNodeTypeDef; + +typedef struct +{ + uint32_t BufferAddress; /*!< Node Buffer address */ + uint32_t BufferSize ; /*!< Node Buffer size */ +} SDMMC_DMALinkNodeConfTypeDef; + +typedef struct +{ + SDMMC_DMALinkNodeTypeDef *pHeadNode; /*!< Linked List Node Head */ + SDMMC_DMALinkNodeTypeDef *pTailNode; /*!< Linked List Node Head */ + uint32_t NodesCounter ; /*!< Node is ready for execution */ +} SDMMC_DMALinkedListTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants + * @{ + */ +#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ +#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ +#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ +#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ +#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ +#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ +#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ +#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ +#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ +#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ +#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ +#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ +#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ +#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ +#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ +#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ +#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ +#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ +#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ +#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ +#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ +#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ +#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ +#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ +#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ +#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ +#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */ +#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */ +#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ +#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ +#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ +#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ + +/** + * @brief SDMMC Commands Index + */ +#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ +#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ +#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ +#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ +#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ +#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ +#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ +#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ +#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ +#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ +/*!< for SDHS and SDXC. */ +#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ +#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ +#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ +#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ +#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ +#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ +#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ +#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ +#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ +#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ +#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ +#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ + +/** + * @brief Following commands are SD Card Specific commands. + * SDMMC_APP_CMD should be sent before sending these commands. + */ +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ +#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ +#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ +#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ + +/** + * @brief Following commands are MMC Specific commands. + */ +#define SDMMC_CMD_MMC_SLEEP_AWAKE ((uint8_t)5U) /*!< Toggle the device between Sleep state and Standby state. */ + +/** + * @brief Following commands are SD Card Specific security commands. + * SDMMC_CMD_APP_CMD should be sent before sending these commands. + */ +#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) +#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) +#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) +#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) +#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) +#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) +#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) +#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) +#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) + +/** + * @brief Masks for errors Card Status R1 (OCR Register) + */ +#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) +#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) +#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) +#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) +#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) +#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) +#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) +#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) +#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) +#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) +#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U) +#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) +#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) +#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) +#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) +#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) +#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) +#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U) +#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) +#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) + +/** + * @brief Masks for R6 Response + */ +#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) +#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) +#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) + +#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) +#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) +#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) +#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) +#define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) +#define SDMMC_DDR50_SWITCH_PATTERN ((uint32_t)0x80FFFF04U) +#define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U) +#define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) +#define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) +#define SDMMC_SDR12_SWITCH_PATTERN ((uint32_t)0x80FFFF00U) + +#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) + +#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU) + +#define SDMMC_ALLZERO ((uint32_t)0x00000000U) + +#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) +#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) +#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) + +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */ +#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) +#endif /* SDMMC_DATATIMEOUT */ + +#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ +#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT +#endif /* SDMMC_SWDATATIMEOUT */ + +#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) +#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) +#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) +#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U) +#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) + +#define SDMMC_HALFFIFO ((uint32_t)0x00000008U) +#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) + +/* SDMMC FIFO Size */ +#define SDMMC_FIFO_SIZE 32U +/** + * @brief Command Class supported + */ +#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) + +#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ +#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ +#define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ + +/** @defgroup SDMMC_LL_Clock_Edge Clock Edge + * @{ + */ +#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) +#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE + +#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ + ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving + * @{ + */ +#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) +#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV + +#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ + ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Bus_Wide Bus Width + * @{ + */ +#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U) +#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 +#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 + +#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ + ((WIDE) == SDMMC_BUS_WIDE_4B) || \ + ((WIDE) == SDMMC_BUS_WIDE_8B)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Speed_Mode + * @{ + */ +#define SDMMC_SPEED_MODE_AUTO ((uint32_t)0x00000000U) +#define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U) +#define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U) +#define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U) +#define SDMMC_SPEED_MODE_ULTRA_SDR104 SDMMC_SPEED_MODE_ULTRA +#define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U) +#define SDMMC_SPEED_MODE_ULTRA_SDR50 ((uint32_t)0x00000005U) + +#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \ + ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \ + ((MODE) == SDMMC_SPEED_MODE_HIGH) || \ + ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \ + ((MODE) == SDMMC_SPEED_MODE_ULTRA_SDR50) || \ + ((MODE) == SDMMC_SPEED_MODE_DDR)) + +/** + * @} + */ + +/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control + * @{ + */ +#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) +#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN + +#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ + ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Clock_Division Clock Division + * @{ + */ +/* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ +#define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U) +/** + * @} + */ + +/** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Transceiver Present + * @{ + */ +#define SDMMC_TRANSCEIVER_UNKNOWN ((uint32_t)0x00000000U) +#define SDMMC_TRANSCEIVER_NOT_PRESENT ((uint32_t)0x00000001U) +#define SDMMC_TRANSCEIVER_PRESENT ((uint32_t)0x00000002U) + +/** + * @} + */ + +/** @defgroup SDMMC_LL_Command_Index Command Index + * @{ + */ +#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Response_Type Response Type + * @{ + */ +#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U) +#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 +#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP + +#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ + ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ + ((RESPONSE) == SDMMC_RESPONSE_LONG)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt + * @{ + */ +#define SDMMC_WAIT_NO ((uint32_t)0x00000000U) +#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT +#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND + +#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ + ((WAIT) == SDMMC_WAIT_IT) || \ + ((WAIT) == SDMMC_WAIT_PEND)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_CPSM_State CPSM State + * @{ + */ +#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U) +#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN + +#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ + ((CPSM) == SDMMC_CPSM_ENABLE)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Response_Registers Response Register + * @{ + */ +#define SDMMC_RESP1 ((uint32_t)0x00000000U) +#define SDMMC_RESP2 ((uint32_t)0x00000004U) +#define SDMMC_RESP3 ((uint32_t)0x00000008U) +#define SDMMC_RESP4 ((uint32_t)0x0000000CU) + +#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ + ((RESP) == SDMMC_RESP2) || \ + ((RESP) == SDMMC_RESP3) || \ + ((RESP) == SDMMC_RESP4)) + +/** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode + * @{ + */ +#define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000) +#define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN) +#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE) +#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT) + +/** + * @} + */ + +/** @defgroup SDMMC_LL_Data_Length Data Length + * @{ + */ +#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size + * @{ + */ +#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) +#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 +#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 +#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) +#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 +#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) +#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) +#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0| \ + SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) +#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 +#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0| \ + SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0| \ + SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1| \ + SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) + +#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction + * @{ + */ +#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) +#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR + +#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ + ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Transfer_Type Transfer Type + * @{ + */ +#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) +#define SDMMC_TRANSFER_MODE_SDIO SDMMC_DCTRL_DTMODE_0 +#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 + +#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ + ((MODE) == SDMMC_TRANSFER_MODE_SDIO) || \ + ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_DPSM_State DPSM State + * @{ + */ +#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U) +#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN + +#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ + ((DPSM) == SDMMC_DPSM_ENABLE)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode + * @{ + */ +#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) +#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) + +#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ + ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources + * @{ + */ +#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE +#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE +#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE +#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE +#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE +#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE +#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE +#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE +#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE +#define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE +#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE +#define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE +#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE +#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE +#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE +#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE +#define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE +#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE +#define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE +#define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE +#define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE +#define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE +#define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE +/** + * @} + */ + +/** @defgroup SDMMC_LL_Flags Flags + * @{ + */ +#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL +#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL +#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT +#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT +#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR +#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR +#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND +#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT +#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND +#define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD +#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND +#define SDMMC_FLAG_DABORT SDMMC_STA_DABORT +#define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT +#define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT +#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE +#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF +#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF +#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF +#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE +#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE +#define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0 +#define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END +#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT +#define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL +#define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT +#define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND +#define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP +#define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE +#define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC + +#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ + SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ + SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ + SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ + SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ + SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ + SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) + +#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ + SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) + +#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ + SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ + SDMMC_FLAG_IDMABTC)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros + * @{ + */ + +/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions + * @brief SDMMC_LL registers bit address in the alias region + * @{ + */ +/* ---------------------- SDMMC registers bit mask --------------------------- */ +/* --- CLKCR Register ---*/ +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ + SDMMC_CLKCR_WIDBUS |\ + SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\ + SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\ + SDMMC_CLKCR_SELCLKRX)) + +/* --- DCTRL Register ---*/ +/* SDMMC DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ + SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) + +/* --- CMD Register ---*/ +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ + SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ + SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND)) + +/* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 200MHz*/ +#define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA) + +/* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 200MHz*/ +#define SDMMC_NSPEED_CLK_DIV ((uint8_t)0x4) + +/* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 200MHz*/ +#define SDMMC_HSPEED_CLK_DIV ((uint8_t)0x2) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ + +/** + * @brief Enable the SDMMC device interrupt. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval None + */ +#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) + +/** + * @brief Disable the SDMMC device interrupt. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval None + */ +#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified SDMMC flag is set or not. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDMMC_FLAG_DHOLD: Data transfer Hold + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 + * @arg SDMMC_FLAG_DPSMACT: Data path state machine active + * @arg SDMMC_FLAG_CPSMACT: Command path state machine active + * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full + * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) + * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received + * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received + * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout + * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion + * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure + * @arg SDMMC_FLAG_IDMATE: IDMA transfer error + * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete + * @retval The new state of SDMMC_FLAG (SET or RESET). + */ +#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) + + +/** + * @brief Clears the SDMMC pending flags. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDMMC_FLAG_DHOLD: Data transfer Hold + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 + * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received + * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received + * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout + * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion + * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure + * @arg SDMMC_FLAG_IDMATE: IDMA transfer error + * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete + * @retval None + */ +#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) + +/** + * @brief Checks whether the specified SDMMC interrupt has occurred or not. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval The new state of SDMMC_IT (SET or RESET). + */ +#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clears the SDMMC's interrupt pending bits. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval None + */ +#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) + +/** + * @brief Enable Start the SD I/O Read Wait operation. + * @param __INSTANCE__ Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) + +/** + * @brief Disable Start the SD I/O Read Wait operations. + * @param __INSTANCE__ Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) + +/** + * @brief Enable Start the SD I/O Read Wait operation. + * @param __INSTANCE__ Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) + +/** + * @brief Disable Stop the SD I/O Read Wait operations. + * @param __INSTANCE__ Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) + +/** + * @brief Enable the SD I/O Mode Operation. + * @param __INSTANCE__ Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) + +/** + * @brief Disable the SD I/O Mode Operation. + * @param __INSTANCE__ Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) + +/** + * @brief Enable the SD I/O Suspend command sending. + * @param __INSTANCE__ Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND) + +/** + * @brief Disable the SD I/O Suspend command sending. + * @param __INSTANCE__ Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND) + +/** + * @brief Enable the CMDTRANS mode. + * @param __INSTANCE__ Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS) + +/** + * @brief Disable the CMDTRANS mode. + * @param __INSTANCE__ Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS) + +/** + * @brief Enable the CMDSTOP mode. + * @param __INSTANCE__ Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP) + +/** + * @brief Disable the CMDSTOP mode. + * @param __INSTANCE__ Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SDMMC_LL_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +/** @addtogroup HAL_SDMMC_LL_Group1 + * @{ + */ +HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); +/** + * @} + */ + +/* I/O operation functions *****************************************************/ +/** @addtogroup HAL_SDMMC_LL_Group2 + * @{ + */ +uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx); +HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); +/** + * @} + */ + +/* Peripheral Control functions ************************************************/ +/** @addtogroup HAL_SDMMC_LL_Group3 + * @{ + */ +HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); +HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); +HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx); + +/* Command path state machine (CPSM) management functions */ +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); +uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response); + +/* Data path state machine (DPSM) management functions */ +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data); +uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx); + +/* SDMMC Cards mode management functions */ +HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); +/** + * @} + */ + +/* SDMMC Commands management functions ******************************************/ +/** @addtogroup HAL_SDMMC_LL_Group4 + * @{ + */ +uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); +uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); +uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); +uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); +uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); +uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); +uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); +uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); +uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); +uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType); +uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr); +uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); +uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); +uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA); +uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount); +/** + * @} + */ + +/* SDMMC Responses management functions *****************************************/ +/** @addtogroup HAL_SDMMC_LL_Group5 + * @{ + */ +uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); +uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); +uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); +/** + * @} + */ + +/* Linked List functions *******************************************************/ +/** @addtogroup HAL_SDMMC_LL_Group6 + * @{ + */ +uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, SDMMC_DMALinkNodeConfTypeDef *pNodeConf); +uint32_t SDMMC_DMALinkedList_InsertNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pPrevNode, + SDMMC_DMALinkNodeTypeDef *pNode); +uint32_t SDMMC_DMALinkedList_RemoveNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pNode); +uint32_t SDMMC_DMALinkedList_LockNode(SDMMC_DMALinkNodeTypeDef *pNode); +uint32_t SDMMC_DMALinkedList_UnlockNode(SDMMC_DMALinkNodeTypeDef *pNode); +uint32_t SDMMC_DMALinkedList_EnableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList); +uint32_t SDMMC_DMALinkedList_DisableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SDMMC1 || SDMMC2 */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_SDMMC_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_spi.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_spi.h new file mode 100644 index 00000000000..b04bdbe46a9 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_spi.h @@ -0,0 +1,3662 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_spi.h + * @author MCD Application Team + * @brief Header file of SPI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_SPI_H +#define STM32H7RSxx_LL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) + +/** @defgroup SPI_LL SPI + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Private_Macros SPI Private Macros + * @{ + */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Init structures definition + */ +typedef struct +{ + uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetTransferDirection().*/ + + uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref SPI_LL_EC_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetMode().*/ + + uint32_t DataWidth; /*!< Specifies the SPI data width. + This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetDataWidth().*/ + + uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_LL_EC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetClockPolarity().*/ + + uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_LL_EC_PHASE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetClockPhase().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. + + This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetNSSMode().*/ + + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure + the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetBaudRatePrescaler().*/ + + uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetTransferBitOrder().*/ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. + + This feature can be modified afterwards using unitary functions + @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + + uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0x00 + and Max_Data = 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetCRCPolynomial().*/ + +} LL_SPI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_SPI_ReadReg function + * @{ + */ +#define LL_SPI_SR_RXP (SPI_SR_RXP) +#define LL_SPI_SR_TXP (SPI_SR_TXP) +#define LL_SPI_SR_DXP (SPI_SR_DXP) +#define LL_SPI_SR_EOT (SPI_SR_EOT) +#define LL_SPI_SR_TXTF (SPI_SR_TXTF) +#define LL_SPI_SR_UDR (SPI_SR_UDR) +#define LL_SPI_SR_CRCE (SPI_SR_CRCE) +#define LL_SPI_SR_MODF (SPI_SR_MODF) +#define LL_SPI_SR_OVR (SPI_SR_OVR) +#define LL_SPI_SR_TIFRE (SPI_SR_TIFRE) +#define LL_SPI_SR_SUSP (SPI_SR_SUSP) +#define LL_SPI_SR_TXC (SPI_SR_TXC) +#define LL_SPI_SR_RXWNE (SPI_SR_RXWNE) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_SPI_IER_RXPIE (SPI_IER_RXPIE) +#define LL_SPI_IER_TXPIE (SPI_IER_TXPIE) +#define LL_SPI_IER_DXPIE (SPI_IER_DXPIE) +#define LL_SPI_IER_EOTIE (SPI_IER_EOTIE) +#define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE) +#define LL_SPI_IER_UDRIE (SPI_IER_UDRIE) +#define LL_SPI_IER_OVRIE (SPI_IER_OVRIE) +#define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE) +#define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE) +#define LL_SPI_IER_MODFIE (SPI_IER_MODFIE) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_MODE Mode + * @{ + */ +#define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER) +#define LL_SPI_MODE_SLAVE (0x00000000UL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_SS_LEVEL SS Level + * @{ + */ +#define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI) +#define LL_SPI_SS_LEVEL_LOW (0x00000000UL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness + * @{ + */ +#define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL) +#define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2) +#define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3) +#define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2) +#define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\ + | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness + * @{ + */ +#define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL) +#define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2) +#define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3) +#define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2) +#define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\ + | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All + * @{ + */ +#define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL) +#define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All + * @{ + */ +#define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL) +#define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register + * @{ + */ +#define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL) +#define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PROTOCOL Protocol + * @{ + */ +#define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL) +#define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PHASE Phase + * @{ + */ +#define LL_SPI_PHASE_1EDGE (0x00000000UL) +#define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_POLARITY Polarity + * @{ + */ +#define LL_SPI_POLARITY_LOW (0x00000000UL) +#define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity + * @{ + */ +#define LL_SPI_NSS_POLARITY_LOW (0x00000000UL) +#define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + * @{ + */ +#define LL_SPI_BAUDRATEPRESCALER_BYPASS (SPI_CFG1_BPASS) +#define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL) +#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0) +#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1) +#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0) +#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2) +#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0) +#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1) +#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BIT_ORDER Bit Order + * @{ + */ +#define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST) +#define LL_SPI_MSB_FIRST (0x00000000UL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode + * @{ + */ +#define LL_SPI_FULL_DUPLEX (0x00000000UL) +#define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0) +#define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1) +#define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1) +#define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DATAWIDTH Data Width + * @{ + */ +#define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3) +#define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4) +#define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3) +#define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold + * @{ + */ +#define LL_SPI_FIFO_TH_01DATA (0x00000000UL) +#define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2) +#define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3) +#define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2) +#define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\ + | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation + * @{ + */ +#define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */ +#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /*!< CRC calculation enabled */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup SPI_LL_EC_CRC CRC + * @{ + */ +#define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3) +#define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4) +#define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3) +#define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_MODE NSS Mode + * @{ + */ +#define LL_SPI_NSS_SOFT (SPI_CFG2_SSM) +#define LL_SPI_NSS_HARD_INPUT (0x00000000UL) +#define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel + * @{ + */ +#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */ +#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) +#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) +#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable SPI peripheral + * @rmtoll CR1 SPE LL_SPI_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable SPI peripheral + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @rmtoll CR1 SPE LL_SPI_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Check if SPI peripheral is enabled + * @rmtoll CR1 SPE LL_SPI_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); +} + +/** + * @brief Swap the MOSI and MISO pin + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); +} + +/** + * @brief Restore default function for MOSI and MISO pin + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); +} + +/** + * @brief Check if MOSI and MISO pin are swapped + * @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO control + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); +} + +/** + * @brief Disable GPIO control + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); +} + +/** + * @brief Check if GPIO control is active + * @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL); +} + +/** + * @brief Set SPI Mode to Master or Slave + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 MASTER LL_SPI_SetMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode); +} + +/** + * @brief Get SPI Mode (Master or Slave) + * @rmtoll CFG2 MASTER LL_SPI_GetMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER)); +} + +/** + * @brief Configure the Idleness applied by master between active edge of SS and first send data + * @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness + * @param SPIx SPI Instance + * @param MasterSSIdleness This parameter can be one of the following values: + * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness); +} + +/** + * @brief Get the configured Idleness applied by master + * @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI)); +} + +/** + * @brief Configure the idleness applied by master between data frame + * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness + * @param SPIx SPI Instance + * @param MasterInterDataIdleness This parameter can be one of the following values: + * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness); +} + +/** + * @brief Get the configured inter data idleness + * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE + */ +__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI)); +} + +/** + * @brief Set transfer size + * @note Count is the number of frame to be transferred + * @rmtoll CR2 TSIZE LL_SPI_SetTransferSize + * @param SPIx SPI Instance + * @param Count 0..0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count); +} + +/** + * @brief Get transfer size + * @note Count is the number of frame to be transferred + * @rmtoll CR2 TSIZE LL_SPI_GetTransferSize + * @param SPIx SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE)); +} + +/** + * @brief Lock the AF configuration of associated IOs + * @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs. + * the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist. + * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK); +} + +/** + * @brief Check if the AF configuration is locked. + * @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL); +} + +/** + * @brief Set Tx CRC Initialization Pattern + * @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern + * @param SPIx SPI Instance + * @param TXCRCInitAll This parameter can be one of the following values: + * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll); +} + +/** + * @brief Get Tx CRC Initialization Pattern + * @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI)); +} + +/** + * @brief Set Rx CRC Initialization Pattern + * @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern + * @param SPIx SPI Instance + * @param RXCRCInitAll This parameter can be one of the following values: + * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll); +} + +/** + * @brief Get Rx CRC Initialization Pattern + * @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI)); +} + +/** + * @brief Set internal SS input level ignoring what comes from PIN. + * @note This configuration has effect only with config LL_SPI_NSS_SOFT + * @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel + * @param SPIx SPI Instance + * @param SSLevel This parameter can be one of the following values: + * @arg @ref LL_SPI_SS_LEVEL_HIGH + * @arg @ref LL_SPI_SS_LEVEL_LOW + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel); +} + +/** + * @brief Get internal SS input level + * @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_SS_LEVEL_HIGH + * @arg @ref LL_SPI_SS_LEVEL_LOW + */ +__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI)); +} + +/** + * @brief Enable CRC computation on 33/17 bits + * @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17); +} + +/** + * @brief Disable CRC computation on 33/17 bits + * @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17); +} + +/** + * @brief Check if Enable CRC computation on 33/17 bits is enabled + * @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL); +} + +/** + * @brief Suspend an ongoing transfer for Master configuration + * @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CSUSP); +} + +/** + * @brief Start effective transfer on wire for Master configuration + * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CSTART); +} + +/** + * @brief Check if there is an unfinished master transfer + * @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL); +} + +/** + * @brief Enable Master Rx auto suspend in case of overrun + * @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_MASRX); +} + +/** + * @brief Disable Master Rx auto suspend in case of overrun + * @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX); +} + +/** + * @brief Check if Master Rx auto suspend is activated + * @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL); +} + +/** + * @brief Set Underrun behavior + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration + * @param SPIx SPI Instance + * @param UDRConfig This parameter can be one of the following values: + * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN + * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig); +} + +/** + * @brief Get Underrun behavior + * @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN + * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED + */ +__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG)); +} + + +/** + * @brief Set Serial protocol used + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 SP LL_SPI_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard); +} + +/** + * @brief Get Serial protocol used + * @rmtoll CFG2 SP LL_SPI_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + */ +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP)); +} + +/** + * @brief Set Clock phase + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 CPHA LL_SPI_SetClockPhase + * @param SPIx SPI Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase); +} + +/** + * @brief Get Clock phase + * @rmtoll CFG2 CPHA LL_SPI_GetClockPhase + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA)); +} + +/** + * @brief Set Clock polarity + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity); +} + +/** + * @brief Get Clock polarity + * @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL)); +} + +/** + * @brief Set NSS polarity + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity + * @param SPIx SPI Instance + * @param NSSPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_POLARITY_LOW + * @arg @ref LL_SPI_NSS_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity); +} + +/** + * @brief Get NSS polarity + * @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_POLARITY_LOW + * @arg @ref LL_SPI_NSS_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP)); +} + +/** + * @brief Set Baudrate Prescaler + * @note This configuration can not be changed when SPI is enabled. + * SPI BaudRate = fPCLK/Pescaler. + * @rmtoll CFG1 MBR LL_SPI_SetBaudRatePrescaler\n + * CFG1 BPASS LL_SPI_SetBaudRatePrescaler + * @param SPIx SPI Instance + * @param Baudrate This parameter can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate) +{ + MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate); +} + +/** + * @brief Get Baudrate Prescaler + * @rmtoll CFG1 MBR LL_SPI_GetBaudRatePrescaler\n + * CFG1 BPASS LL_SPI_GetBaudRatePrescaler + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS))); +} + +/** + * @brief Set Transfer Bit Order + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder); +} + +/** + * @brief Get Transfer Bit Order + * @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST)); +} + +/** + * @brief Set Transfer Mode + * @note This configuration can not be changed when SPI is enabled except for half duplex direction + * using LL_SPI_SetHalfDuplexDirection. + * @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n + * CFG2 COMM LL_SPI_SetTransferDirection + * @param SPIx SPI Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_TX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR); + MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM); +} + +/** + * @brief Get Transfer Mode + * @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n + * CFG2 COMM LL_SPI_GetTransferDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_TX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) +{ + uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR); + uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM); + return (Hddir | Comm); +} + +/** + * @brief Set direction for Half-Duplex Mode + * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex. + * @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection + * @param SPIx SPI Instance + * @param HalfDuplexDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR); +} + +/** + * @brief Get direction for Half-Duplex Mode + * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex. + * @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM); +} + +/** + * @brief Set Frame Data Size + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth + * @param SPIx SPI Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @arg @ref LL_SPI_DATAWIDTH_17BIT + * @arg @ref LL_SPI_DATAWIDTH_18BIT + * @arg @ref LL_SPI_DATAWIDTH_19BIT + * @arg @ref LL_SPI_DATAWIDTH_20BIT + * @arg @ref LL_SPI_DATAWIDTH_21BIT + * @arg @ref LL_SPI_DATAWIDTH_22BIT + * @arg @ref LL_SPI_DATAWIDTH_23BIT + * @arg @ref LL_SPI_DATAWIDTH_24BIT + * @arg @ref LL_SPI_DATAWIDTH_25BIT + * @arg @ref LL_SPI_DATAWIDTH_26BIT + * @arg @ref LL_SPI_DATAWIDTH_27BIT + * @arg @ref LL_SPI_DATAWIDTH_28BIT + * @arg @ref LL_SPI_DATAWIDTH_29BIT + * @arg @ref LL_SPI_DATAWIDTH_30BIT + * @arg @ref LL_SPI_DATAWIDTH_31BIT + * @arg @ref LL_SPI_DATAWIDTH_32BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth); +} + +/** + * @brief Get Frame Data Size + * @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @arg @ref LL_SPI_DATAWIDTH_17BIT + * @arg @ref LL_SPI_DATAWIDTH_18BIT + * @arg @ref LL_SPI_DATAWIDTH_19BIT + * @arg @ref LL_SPI_DATAWIDTH_20BIT + * @arg @ref LL_SPI_DATAWIDTH_21BIT + * @arg @ref LL_SPI_DATAWIDTH_22BIT + * @arg @ref LL_SPI_DATAWIDTH_23BIT + * @arg @ref LL_SPI_DATAWIDTH_24BIT + * @arg @ref LL_SPI_DATAWIDTH_25BIT + * @arg @ref LL_SPI_DATAWIDTH_26BIT + * @arg @ref LL_SPI_DATAWIDTH_27BIT + * @arg @ref LL_SPI_DATAWIDTH_28BIT + * @arg @ref LL_SPI_DATAWIDTH_29BIT + * @arg @ref LL_SPI_DATAWIDTH_30BIT + * @arg @ref LL_SPI_DATAWIDTH_31BIT + * @arg @ref LL_SPI_DATAWIDTH_32BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE)); +} + +/** + * @brief Set threshold of FIFO that triggers a transfer event + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold + * @param SPIx SPI Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_SPI_FIFO_TH_01DATA + * @arg @ref LL_SPI_FIFO_TH_02DATA + * @arg @ref LL_SPI_FIFO_TH_03DATA + * @arg @ref LL_SPI_FIFO_TH_04DATA + * @arg @ref LL_SPI_FIFO_TH_05DATA + * @arg @ref LL_SPI_FIFO_TH_06DATA + * @arg @ref LL_SPI_FIFO_TH_07DATA + * @arg @ref LL_SPI_FIFO_TH_08DATA + * @arg @ref LL_SPI_FIFO_TH_09DATA + * @arg @ref LL_SPI_FIFO_TH_10DATA + * @arg @ref LL_SPI_FIFO_TH_11DATA + * @arg @ref LL_SPI_FIFO_TH_12DATA + * @arg @ref LL_SPI_FIFO_TH_13DATA + * @arg @ref LL_SPI_FIFO_TH_14DATA + * @arg @ref LL_SPI_FIFO_TH_15DATA + * @arg @ref LL_SPI_FIFO_TH_16DATA + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold); +} + +/** + * @brief Get threshold of FIFO that triggers a transfer event + * @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FIFO_TH_01DATA + * @arg @ref LL_SPI_FIFO_TH_02DATA + * @arg @ref LL_SPI_FIFO_TH_03DATA + * @arg @ref LL_SPI_FIFO_TH_04DATA + * @arg @ref LL_SPI_FIFO_TH_05DATA + * @arg @ref LL_SPI_FIFO_TH_06DATA + * @arg @ref LL_SPI_FIFO_TH_07DATA + * @arg @ref LL_SPI_FIFO_TH_08DATA + * @arg @ref LL_SPI_FIFO_TH_09DATA + * @arg @ref LL_SPI_FIFO_TH_10DATA + * @arg @ref LL_SPI_FIFO_TH_11DATA + * @arg @ref LL_SPI_FIFO_TH_12DATA + * @arg @ref LL_SPI_FIFO_TH_13DATA + * @arg @ref LL_SPI_FIFO_TH_14DATA + * @arg @ref LL_SPI_FIFO_TH_15DATA + * @arg @ref LL_SPI_FIFO_TH_16DATA + */ +__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV)); +} + +/** + * @brief Enable CRC + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 CRCEN LL_SPI_EnableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); +} + +/** + * @brief Disable CRC + * @rmtoll CFG1 CRCEN LL_SPI_DisableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); +} + +/** + * @brief Check if CRC is enabled + * @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL); +} + +/** + * @brief Set CRC Length + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth + * @param SPIx SPI Instance + * @param CRCLength This parameter can be one of the following values: + * @arg @ref LL_SPI_CRC_4BIT + * @arg @ref LL_SPI_CRC_5BIT + * @arg @ref LL_SPI_CRC_6BIT + * @arg @ref LL_SPI_CRC_7BIT + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_9BIT + * @arg @ref LL_SPI_CRC_10BIT + * @arg @ref LL_SPI_CRC_11BIT + * @arg @ref LL_SPI_CRC_12BIT + * @arg @ref LL_SPI_CRC_13BIT + * @arg @ref LL_SPI_CRC_14BIT + * @arg @ref LL_SPI_CRC_15BIT + * @arg @ref LL_SPI_CRC_16BIT + * @arg @ref LL_SPI_CRC_17BIT + * @arg @ref LL_SPI_CRC_18BIT + * @arg @ref LL_SPI_CRC_19BIT + * @arg @ref LL_SPI_CRC_20BIT + * @arg @ref LL_SPI_CRC_21BIT + * @arg @ref LL_SPI_CRC_22BIT + * @arg @ref LL_SPI_CRC_23BIT + * @arg @ref LL_SPI_CRC_24BIT + * @arg @ref LL_SPI_CRC_25BIT + * @arg @ref LL_SPI_CRC_26BIT + * @arg @ref LL_SPI_CRC_27BIT + * @arg @ref LL_SPI_CRC_28BIT + * @arg @ref LL_SPI_CRC_29BIT + * @arg @ref LL_SPI_CRC_30BIT + * @arg @ref LL_SPI_CRC_31BIT + * @arg @ref LL_SPI_CRC_32BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength); +} + +/** + * @brief Get CRC Length + * @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_CRC_4BIT + * @arg @ref LL_SPI_CRC_5BIT + * @arg @ref LL_SPI_CRC_6BIT + * @arg @ref LL_SPI_CRC_7BIT + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_9BIT + * @arg @ref LL_SPI_CRC_10BIT + * @arg @ref LL_SPI_CRC_11BIT + * @arg @ref LL_SPI_CRC_12BIT + * @arg @ref LL_SPI_CRC_13BIT + * @arg @ref LL_SPI_CRC_14BIT + * @arg @ref LL_SPI_CRC_15BIT + * @arg @ref LL_SPI_CRC_16BIT + * @arg @ref LL_SPI_CRC_17BIT + * @arg @ref LL_SPI_CRC_18BIT + * @arg @ref LL_SPI_CRC_19BIT + * @arg @ref LL_SPI_CRC_20BIT + * @arg @ref LL_SPI_CRC_21BIT + * @arg @ref LL_SPI_CRC_22BIT + * @arg @ref LL_SPI_CRC_23BIT + * @arg @ref LL_SPI_CRC_24BIT + * @arg @ref LL_SPI_CRC_25BIT + * @arg @ref LL_SPI_CRC_26BIT + * @arg @ref LL_SPI_CRC_27BIT + * @arg @ref LL_SPI_CRC_28BIT + * @arg @ref LL_SPI_CRC_29BIT + * @arg @ref LL_SPI_CRC_30BIT + * @arg @ref LL_SPI_CRC_31BIT + * @arg @ref LL_SPI_CRC_32BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE)); +} + +/** + * @brief Set NSS Mode + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n + * CFG2 SSOE LL_SPI_SetNSSMode + * @param SPIx SPI Instance + * @param NSS This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS); +} + +/** + * @brief Set NSS Mode + * @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n + * CFG2 SSOE LL_SPI_GetNSSMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE)); +} + +/** + * @brief Enable NSS pulse mgt + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM); +} + +/** + * @brief Disable NSS pulse mgt + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM); +} + +/** + * @brief Check if NSS pulse is enabled + * @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if there is enough data in FIFO to read a full packet + * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL); +} + +/** + * @brief Check if there is enough space in FIFO to hold a full packet + * @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL); +} + +/** + * @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet + * @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL); +} + +/** + * @brief Check that end of transfer event occurred + * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL); +} + +/** + * @brief Check that all required data has been filled in the fifo according to transfer size + * @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL); +} + +/** + * @brief Get Underrun error flag + * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Get CRC error flag + * @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL); +} + +/** + * @brief Get Mode fault error flag + * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); +} + +/** + * @brief Get Overrun error flag + * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get TI Frame format error flag + * @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL); +} + +/** + * @brief Check if a suspend operation is done + * @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL); +} + +/** + * @brief Check if last TxFIFO or CRC frame transmission is completed + * @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL); +} + +/** + * @brief Check if at least one 32-bit data is available in RxFIFO + * @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL); +} + +/** + * @brief Get number of data framed remaining in current TSIZE + * @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames + * @param SPIx SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos); +} + +/** + * @brief Get RxFIFO packing Level + * @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_0PACKET + * @arg @ref LL_SPI_RX_FIFO_1PACKET + * @arg @ref LL_SPI_RX_FIFO_2PACKET + * @arg @ref LL_SPI_RX_FIFO_3PACKET + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL)); +} + +/** + * @brief Clear End Of Transfer flag + * @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC); +} + +/** + * @brief Clear TXTF flag + * @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC); +} + +/** + * @brief Clear Underrun error flag + * @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC); +} + +/** + * @brief Clear Overrun error flag + * @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC); +} + +/** + * @brief Clear CRC error flag + * @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC); +} + +/** + * @brief Clear Mode fault error flag + * @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC); +} + +/** + * @brief Clear Frame format error flag + * @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC); +} + +/** + * @brief Clear SUSP flag + * @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Rx Packet available IT + * @rmtoll IER RXPIE LL_SPI_EnableIT_RXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXPIE); +} + +/** + * @brief Enable Tx Packet space available IT + * @rmtoll IER TXPIE LL_SPI_EnableIT_TXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXPIE); +} + +/** + * @brief Enable Duplex Packet available IT + * @rmtoll IER DXPIE LL_SPI_EnableIT_DXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_DXPIE); +} + +/** + * @brief Enable End Of Transfer IT + * @rmtoll IER EOTIE LL_SPI_EnableIT_EOT + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_EOTIE); +} + +/** + * @brief Enable TXTF IT + * @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXTFIE); +} + +/** + * @brief Enable Underrun IT + * @rmtoll IER UDRIE LL_SPI_EnableIT_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_UDRIE); +} + +/** + * @brief Enable Overrun IT + * @rmtoll IER OVRIE LL_SPI_EnableIT_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_OVRIE); +} + +/** + * @brief Enable CRC Error IT + * @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_CRCEIE); +} + +/** + * @brief Enable TI Frame Format Error IT + * @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TIFREIE); +} + +/** + * @brief Enable MODF IT + * @rmtoll IER MODFIE LL_SPI_EnableIT_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_MODFIE); +} + +/** + * @brief Disable Rx Packet available IT + * @rmtoll IER RXPIE LL_SPI_DisableIT_RXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE); +} + +/** + * @brief Disable Tx Packet space available IT + * @rmtoll IER TXPIE LL_SPI_DisableIT_TXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE); +} + +/** + * @brief Disable Duplex Packet available IT + * @rmtoll IER DXPIE LL_SPI_DisableIT_DXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE); +} + +/** + * @brief Disable End Of Transfer IT + * @rmtoll IER EOTIE LL_SPI_DisableIT_EOT + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE); +} + +/** + * @brief Disable TXTF IT + * @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE); +} + +/** + * @brief Disable Underrun IT + * @rmtoll IER UDRIE LL_SPI_DisableIT_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE); +} + +/** + * @brief Disable Overrun IT + * @rmtoll IER OVRIE LL_SPI_DisableIT_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE); +} + +/** + * @brief Disable CRC Error IT + * @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE); +} + +/** + * @brief Disable TI Frame Format Error IT + * @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE); +} + +/** + * @brief Disable MODF IT + * @rmtoll IER MODFIE LL_SPI_DisableIT_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE); +} + +/** + * @brief Check if Rx Packet available IT is enabled + * @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx Packet space available IT is enabled + * @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Duplex Packet available IT is enabled + * @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if End Of Transfer IT is enabled + * @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if TXTF IT is enabled + * @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Underrun IT is enabled + * @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Overrun IT is enabled + * @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if CRC Error IT is enabled + * @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if TI Frame Format Error IT is enabled + * @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if MODF IT is enabled + * @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL); +} +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDR LL_SPI_DMA_GetTxRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->TXDR); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RXDR RXDR LL_SPI_DMA_GetRxRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->RXDR); +} +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DATA_Management DATA_Management + * @{ + */ + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_SPI_ReceiveData8 + * @param SPIx SPI Instance + * @retval 0..0xFF + */ +__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ +{ + return (*((__IO uint8_t *)&SPIx->RXDR)); +} + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_SPI_ReceiveData16 + * @param SPIx SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ +{ +#if defined (__GNUC__) + __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR)); + return (*spirxdr); +#else + return (*((__IO uint16_t *)&SPIx->RXDR)); +#endif /* __GNUC__ */ +} + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_SPI_ReceiveData32 + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ +{ + return (*((__IO uint32_t *)&SPIx->RXDR)); +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_SPI_TransmitData8 + * @param SPIx SPI Instance + * @param TxData 0..0xFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) +{ + *((__IO uint8_t *)&SPIx->TXDR) = TxData; +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_SPI_TransmitData16 + * @param SPIx SPI Instance + * @param TxData 0..0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ +#if defined (__GNUC__) + __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR); + *spitxdr = TxData; +#else + *((__IO uint16_t *)&SPIx->TXDR) = TxData; +#endif /* __GNUC__ */ +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_SPI_TransmitData32 + * @param SPIx SPI Instance + * @param TxData 0..0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData) +{ + *((__IO uint32_t *)&SPIx->TXDR) = TxData; +} + +/** + * @brief Set polynomial for CRC calcul + * @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial + * @param SPIx SPI Instance + * @param CRCPoly 0..0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) +{ + WRITE_REG(SPIx->CRCPOLY, CRCPoly); +} + +/** + * @brief Get polynomial for CRC calcul + * @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CRCPOLY)); +} + +/** + * @brief Set the underrun pattern + * @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern + * @param SPIx SPI Instance + * @param Pattern 0..0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern) +{ + WRITE_REG(SPIx->UDRDR, Pattern); +} + +/** + * @brief Get the underrun pattern + * @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->UDRDR)); +} + +/** + * @brief Get Rx CRC + * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->RXCRC)); +} + +/** + * @brief Get Tx CRC + * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->TXCRC)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ +/** + * @} + */ + +/** @defgroup I2S_LL I2S + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure + * @{ + */ + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_LL_EC_MODE + + This feature can be modified afterwards using unitary function + @ref LL_I2S_SetTransferMode().*/ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_STANDARD + + This feature can be modified afterwards using unitary function + @ref LL_I2S_SetStandard().*/ + + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT + + This feature can be modified afterwards using unitary function + @ref LL_I2S_SetDataFormat().*/ + + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT + + This feature can be modified afterwards using unitary functions + @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ + + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ + + Audio Frequency can be modified afterwards using Reference manual formulas + to calculate Prescaler Linear, Parity and unitary functions + @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() + to set it.*/ + + + uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_LL_EC_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_I2S_SetClockPolarity().*/ + +} LL_I2S_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants + * @{ + */ + +/** @defgroup I2S_LL_EC_DATA_FORMAT Data Format + * @{ + */ +#define LL_I2S_DATAFORMAT_16B (0x00000000UL) +#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) +#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) +#define LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0 | SPI_I2SCFGR_DATFMT) +#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) +/** + * @} + */ + +/** @defgroup I2S_LL_EC_CHANNEL_LENGTH_TYPE Type of Channel Length + * @{ + */ +#define LL_I2S_SLAVE_VARIABLE_CH_LENGTH (0x00000000UL) +#define LL_I2S_SLAVE_FIXED_CH_LENGTH (SPI_I2SCFGR_FIXCH) +/** + * @} + */ + +/** @defgroup I2S_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_I2S_POLARITY_LOW (0x00000000UL) +#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) +/** + * @} + */ + +/** @defgroup I2S_LL_EC_STANDARD I2S Standard + * @{ + */ +#define LL_I2S_STANDARD_PHILIPS (0x00000000UL) +#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) +#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) +#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) +#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) +/** + * @} + */ + +/** @defgroup I2S_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_I2S_MODE_SLAVE_TX (0x00000000UL) +#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) +#define LL_I2S_MODE_SLAVE_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2) +#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) +#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0) +#define LL_I2S_MODE_MASTER_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0) +/** + * @} + */ + +/** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor + * @{ + */ +#define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL) /*!< Odd factor: Real divider value is = I2SDIV * 2 */ +#define LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_FIFO_TH FIFO Threshold Level + * @{ + */ +#define LL_I2S_FIFO_TH_01DATA (LL_SPI_FIFO_TH_01DATA) +#define LL_I2S_FIFO_TH_02DATA (LL_SPI_FIFO_TH_02DATA) +#define LL_I2S_FIFO_TH_03DATA (LL_SPI_FIFO_TH_03DATA) +#define LL_I2S_FIFO_TH_04DATA (LL_SPI_FIFO_TH_04DATA) +#define LL_I2S_FIFO_TH_05DATA (LL_SPI_FIFO_TH_05DATA) +#define LL_I2S_FIFO_TH_06DATA (LL_SPI_FIFO_TH_06DATA) +#define LL_I2S_FIFO_TH_07DATA (LL_SPI_FIFO_TH_07DATA) +#define LL_I2S_FIFO_TH_08DATA (LL_SPI_FIFO_TH_08DATA) +/** + * @} + */ + +/** @defgroup I2S_LL_EC_BIT_ORDER Transmission Bit Order + * @{ + */ +#define LL_I2S_LSB_FIRST (LL_SPI_LSB_FIRST) +#define LL_I2S_MSB_FIRST (LL_SPI_MSB_FIRST) +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output + * @{ + */ +#define LL_I2S_MCLK_OUTPUT_DISABLE (0x00000000UL) +#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SCFGR_MCKOE) +/** + * @} + */ + +/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency + * @{ + */ + +#define LL_I2S_AUDIOFREQ_192K 192000UL /*!< Audio Frequency configuration 192000 Hz */ +#define LL_I2S_AUDIOFREQ_96K 96000UL /*!< Audio Frequency configuration 96000 Hz */ +#define LL_I2S_AUDIOFREQ_48K 48000UL /*!< Audio Frequency configuration 48000 Hz */ +#define LL_I2S_AUDIOFREQ_44K 44100UL /*!< Audio Frequency configuration 44100 Hz */ +#define LL_I2S_AUDIOFREQ_32K 32000UL /*!< Audio Frequency configuration 32000 Hz */ +#define LL_I2S_AUDIOFREQ_22K 22050UL /*!< Audio Frequency configuration 22050 Hz */ +#define LL_I2S_AUDIOFREQ_16K 16000UL /*!< Audio Frequency configuration 16000 Hz */ +#define LL_I2S_AUDIOFREQ_11K 11025UL /*!< Audio Frequency configuration 11025 Hz */ +#define LL_I2S_AUDIOFREQ_8K 8000UL /*!< Audio Frequency configuration 8000 Hz */ +#define LL_I2S_AUDIOFREQ_DEFAULT 0UL /*!< Audio Freq not specified. Register I2SDIV = 0 */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros + * @{ + */ + +/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Set I2S Data frame format + * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n + * I2SCFGR CHLEN LL_I2S_SetDataFormat\n + * I2SCFGR DATFMT LL_I2S_SetDataFormat + * @param SPIx SPI Handle + * @param DataLength This parameter can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED + * @arg @ref LL_I2S_DATAFORMAT_32B + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataLength) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT, DataLength); +} + +/** + * @brief Get I2S Data frame format + * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n + * I2SCFGR CHLEN LL_I2S_GetDataFormat\n + * I2SCFGR DATFMT LL_I2S_GetDataFormat + * @param SPIx SPI Handle + * @retval Return value can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED + * @arg @ref LL_I2S_DATAFORMAT_32B + */ +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT)); +} + +/** + * @brief Set I2S Channel Length Type + * @note This feature is useful with SLAVE only + * @rmtoll I2SCFGR FIXCH LL_I2S_SetChannelLengthType + * @param SPIx SPI Handle + * @param ChannelLengthType This parameter can be one of the following values: + * @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH + * @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetChannelLengthType(SPI_TypeDef *SPIx, uint32_t ChannelLengthType) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH, ChannelLengthType); +} + +/** + * @brief Get I2S Channel Length Type + * @note This feature is useful with SLAVE only + * @rmtoll I2SCFGR FIXCH LL_I2S_GetChannelLengthType + * @param SPIx SPI Handle + * @retval Return value can be one of the following values: + * @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH + * @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH + */ +__STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH)); +} + +/** + * @brief Invert the default polarity of WS signal + * @rmtoll I2SCFGR WSINV LL_I2S_EnableWordSelectInversion + * @param SPIx SPI Handle + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableWordSelectInversion(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV); +} + +/** + * @brief Use the default polarity of WS signal + * @rmtoll I2SCFGR WSINV LL_I2S_DisableWordSelectInversion + * @param SPIx SPI Handle + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableWordSelectInversion(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV); +} + +/** + * @brief Check if polarity of WS signal is inverted + * @rmtoll I2SCFGR WSINV LL_I2S_IsEnabledWordSelectInversion + * @param SPIx SPI Handle + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL); +} + +/** + * @brief Set 2S Clock Polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity + * @param SPIx SPI Handle + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL, ClockPolarity); +} + +/** + * @brief Get 2S Clock Polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity + * @param SPIx SPI Handle + * @retval Return value can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); +} + +/** + * @brief Set I2S standard + * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n + * I2SCFGR PCMSYNC LL_I2S_SetStandard + * @param SPIx SPI Handle + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard); +} + +/** + * @brief Get I2S standard + * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n + * I2SCFGR PCMSYNC LL_I2S_GetStandard + * @param SPIx SPI Handle + * @retval Return value can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + */ +__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); +} + +/** + * @brief Set I2S config + * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode + * @param SPIx SPI Handle + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Standard); +} + +/** + * @brief Get I2S config + * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode + * @param SPIx SPI Handle + * @retval Return value can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX + */ +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); +} + +/** + * @brief Select I2S mode and Enable I2S peripheral + * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n + * CR1 SPE LL_I2S_Enable + * @param SPIx SPI Handle + * @retval None + */ +__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); + SET_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable I2S peripheral and disable I2S mode + * @rmtoll CR1 SPE LL_I2S_Disable\n + * I2SCFGR I2SMOD LL_I2S_Disable + * @param SPIx SPI Handle + * @retval None + */ +__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); +} + +/** + * @brief Swap the SDO and SDI pin + * @note This configuration can not be changed when I2S is enabled. + * @rmtoll CFG2 IOSWP LL_I2S_EnableIOSwap + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIOSwap(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIOSwap(SPIx); +} + +/** + * @brief Restore default function for SDO and SDI pin + * @note This configuration can not be changed when I2S is enabled. + * @rmtoll CFG2 IOSWP LL_I2S_DisableIOSwap + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIOSwap(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIOSwap(SPIx); +} + +/** + * @brief Check if SDO and SDI pin are swapped + * @rmtoll CFG2 IOSWP LL_I2S_IsEnabledIOSwap + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIOSwap(SPIx); +} + +/** + * @brief Enable GPIO control + * @note This configuration can not be changed when I2S is enabled. + * @rmtoll CFG2 AFCNTR LL_I2S_EnableGPIOControl + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableGPIOControl(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableGPIOControl(SPIx); +} + +/** + * @brief Disable GPIO control + * @note This configuration can not be changed when I2S is enabled. + * @rmtoll CFG2 AFCNTR LL_I2S_DisableGPIOControl + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableGPIOControl(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableGPIOControl(SPIx); +} + +/** + * @brief Check if GPIO control is active + * @rmtoll CFG2 AFCNTR LL_I2S_IsEnabledGPIOControl + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledGPIOControl(SPIx); +} + +/** + * @brief Lock the AF configuration of associated IOs + * @note Once this bit is set, the SPI_CFG2 register content can not be modified until a hardware reset occurs. + * The reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist. + * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIOLock(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIOLock(SPIx); +} + +/** + * @brief Check if the the SPI_CFG2 register is locked + * @rmtoll CR1 IOLOCK LL_I2S_IsEnabledIOLock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIOLock(SPIx); +} + +/** + * @brief Set Transfer Bit Order + * @note This configuration can not be changed when I2S is enabled. + * @rmtoll CFG2 LSBFRST LL_I2S_SetTransferBitOrder + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_I2S_LSB_FIRST + * @arg @ref LL_I2S_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + LL_SPI_SetTransferBitOrder(SPIx, BitOrder); +} +/** + * @brief Get Transfer Bit Order + * @rmtoll CFG2 LSBFRST LL_I2S_GetTransferBitOrder + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_LSB_FIRST + * @arg @ref LL_I2S_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(const SPI_TypeDef *SPIx) +{ + return LL_SPI_GetTransferBitOrder(SPIx); +} + +/** + * @brief Start effective transfer on wire + * @rmtoll CR1 CSTART LL_I2S_StartTransfer + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_StartTransfer(SPI_TypeDef *SPIx) +{ + LL_SPI_StartMasterTransfer(SPIx); +} + +/** + * @brief Check if there is an unfinished transfer + * @rmtoll CR1 CSTART LL_I2S_IsActiveTransfer + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveMasterTransfer(SPIx); +} + +/** + * @brief Set threshold of FIFO that triggers a transfer event + * @note This configuration can not be changed when I2S is enabled. + * @rmtoll CFG1 FTHLV LL_I2S_SetFIFOThreshold + * @param SPIx SPI Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_I2S_FIFO_TH_01DATA + * @arg @ref LL_I2S_FIFO_TH_02DATA + * @arg @ref LL_I2S_FIFO_TH_03DATA + * @arg @ref LL_I2S_FIFO_TH_04DATA + * @arg @ref LL_I2S_FIFO_TH_05DATA + * @arg @ref LL_I2S_FIFO_TH_06DATA + * @arg @ref LL_I2S_FIFO_TH_07DATA + * @arg @ref LL_I2S_FIFO_TH_08DATA + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) +{ + LL_SPI_SetFIFOThreshold(SPIx, Threshold); +} + +/** + * @brief Get threshold of FIFO that triggers a transfer event + * @rmtoll CFG1 FTHLV LL_I2S_GetFIFOThreshold + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_FIFO_TH_01DATA + * @arg @ref LL_I2S_FIFO_TH_02DATA + * @arg @ref LL_I2S_FIFO_TH_03DATA + * @arg @ref LL_I2S_FIFO_TH_04DATA + * @arg @ref LL_I2S_FIFO_TH_05DATA + * @arg @ref LL_I2S_FIFO_TH_06DATA + * @arg @ref LL_I2S_FIFO_TH_07DATA + * @arg @ref LL_I2S_FIFO_TH_08DATA + */ +__STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(const SPI_TypeDef *SPIx) +{ + return LL_SPI_GetFIFOThreshold(SPIx); +} + +/** + * @brief Set I2S linear prescaler + * @rmtoll I2SCFGR I2SDIV LL_I2S_SetPrescalerLinear + * @param SPIx SPI Instance + * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF + * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint32_t PrescalerLinear) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos)); +} + +/** + * @brief Get I2S linear prescaler + * @rmtoll I2SCFGR I2SDIV LL_I2S_GetPrescalerLinear + * @param SPIx SPI Instance + * @retval PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos); +} + +/** + * @brief Set I2S parity prescaler + * @rmtoll I2SCFGR ODD LL_I2S_SetPrescalerParity + * @param SPIx SPI Instance + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_ODD, PrescalerParity << SPI_I2SCFGR_ODD_Pos); +} + +/** + * @brief Get I2S parity prescaler + * @rmtoll I2SCFGR ODD LL_I2S_GetPrescalerParity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos); +} + +/** + * @brief Enable the Master Clock Output (Pin MCK) + * @rmtoll I2SCFGR MCKOE LL_I2S_EnableMasterClock + * @param SPIx SPI Handle + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE); +} + +/** + * @brief Disable the Master Clock Output (Pin MCK) + * @rmtoll I2SCFGR MCKOE LL_I2S_DisableMasterClock + * @param SPIx SPI Handle + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE); +} + +/** + * @brief Check if the master clock output (Pin MCK) is enabled + * @rmtoll I2SCFGR MCKOE LL_I2S_IsEnabledMasterClock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL); +} + +/** + * @} + */ + + +/** @defgroup I2S_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if there enough data in FIFO to read a full packet + * @rmtoll SR RXP LL_I2S_IsActiveFlag_RXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_RXP(SPIx); +} + +/** + * @brief Check if there enough space in FIFO to hold a full packet + * @rmtoll SR TXP LL_I2S_IsActiveFlag_TXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_TXP(SPIx); +} + +/** + * @brief Get Underrun error flag + * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_UDR(SPIx); +} + +/** + * @brief Get Overrun error flag + * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_OVR(SPIx); +} + +/** + * @brief Get TI Frame format error flag + * @rmtoll SR TIFRE LL_I2S_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_FRE(SPIx); +} + +/** + * @brief Clear Underrun error flag + * @rmtoll IFCR UDRC LL_I2S_ClearFlag_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_UDR(SPIx); +} + +/** + * @brief Clear Overrun error flag + * @rmtoll IFCR OVRC LL_I2S_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_OVR(SPIx); +} + +/** + * @brief Clear Frame format error flag + * @rmtoll IFCR TIFREC LL_I2S_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_FRE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Rx Packet available IT + * @rmtoll IER RXPIE LL_I2S_EnableIT_RXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_RXP(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_RXP(SPIx); +} + +/** + * @brief Enable Tx Packet space available IT + * @rmtoll IER TXPIE LL_I2S_EnableIT_TXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_TXP(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_TXP(SPIx); +} + +/** + * @brief Enable Underrun IT + * @rmtoll IER UDRIE LL_I2S_EnableIT_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_UDR(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_UDR(SPIx); +} + +/** + * @brief Enable Overrun IT + * @rmtoll IER OVRIE LL_I2S_EnableIT_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_OVR(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_OVR(SPIx); +} + +/** + * @brief Enable TI Frame Format Error IT + * @rmtoll IER TIFREIE LL_I2S_EnableIT_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_FRE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_FRE(SPIx); +} + +/** + * @brief Disable Rx Packet available IT + * @rmtoll IER RXPIE LL_I2S_DisableIT_RXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_RXP(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_RXP(SPIx); +} + +/** + * @brief Disable Tx Packet space available IT + * @rmtoll IER TXPIE LL_I2S_DisableIT_TXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_TXP(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_TXP(SPIx); +} + +/** + * @brief Disable Underrun IT + * @rmtoll IER UDRIE LL_I2S_DisableIT_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_UDR(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_UDR(SPIx); +} + +/** + * @brief Disable Overrun IT + * @rmtoll IER OVRIE LL_I2S_DisableIT_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_OVR(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_OVR(SPIx); +} + +/** + * @brief Disable TI Frame Format Error IT + * @rmtoll IER TIFREIE LL_I2S_DisableIT_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_FRE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_FRE(SPIx); +} + +/** + * @brief Check if Rx Packet available IT is enabled + * @rmtoll IER RXPIE LL_I2S_IsEnabledIT_RXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_RXP(SPIx); +} + +/** + * @brief Check if Tx Packet space available IT is enabled + * @rmtoll IER TXPIE LL_I2S_IsEnabledIT_TXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_TXP(SPIx); +} + +/** + * @brief Check if Underrun IT is enabled + * @rmtoll IER UDRIE LL_I2S_IsEnabledIT_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_UDR(SPIx); +} + +/** + * @brief Check if Overrun IT is enabled + * @rmtoll IER OVRIE LL_I2S_IsEnabledIT_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_OVR(SPIx); +} + +/** + * @brief Check if TI Frame Format Error IT is enabled + * @rmtoll IER TIFREIE LL_I2S_IsEnabledIT_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_FRE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CFG1 RXDMAEN LL_I2S_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_RX(SPIx); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CFG1 RXDMAEN LL_I2S_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_RX(SPIx); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CFG1 RXDMAEN LL_I2S_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_RX(SPIx); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CFG1 TXDMAEN LL_I2S_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_TX(SPIx); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CFG1 TXDMAEN LL_I2S_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_TX(SPIx); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CFG1 TXDMAEN LL_I2S_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_TX(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DATA_Management DATA_Management + * @{ + */ + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_I2S_ReceiveData16 + * @param SPIx SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ +{ + return LL_SPI_ReceiveData16(SPIx); +} + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_I2S_ReceiveData32 + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ +{ + return LL_SPI_ReceiveData32(SPIx); +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_I2S_TransmitData16 + * @param SPIx SPI Instance + * @param TxData 0..0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + LL_SPI_TransmitData16(SPIx, TxData); +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_I2S_TransmitData32 + * @param SPIx SPI Instance + * @param TxData 0..0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData) +{ + LL_SPI_TransmitData32(SPIx, TxData); +} + + +/** + * @} + */ + + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_SPI_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_system.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_system.h new file mode 100644 index 00000000000..ca89520cae9 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_system.h @@ -0,0 +1,2243 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SBS registers + (+) Access to VREFBUF registers + + @endverbatim + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_SYSTEM_H +#define STM32H7RSxx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SBS) || defined (DBGMCU) || defined (VREFBUF) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ +#define LL_SBS_REGISTER_PINPOS_SHFT 16U /*!< Define used to shift pin position in EXTICR register */ +#define LL_SBS_HDPL_INCREMENT_VALUE 0x6AU /*!< Define used for the HDPL increment */ +#define LL_SBS_DBG_UNLOCK (0xB4U << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< Define used to unlock debug */ +#define LL_SBS_ACCESS_PORT_UNLOCK 0xB4U /*!< Define used to unlock access port */ +#define LL_SBS_DBG_CONFIG_LOCK 0xC3U /*!< Define used to lock debug configuration */ +#define LL_SBS_DBG_CONFIG_UNLOCK 0xB4U /*!< Define used to unlock debug configuration */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_SBS_HDPL SBS hide protection level + * @{ + */ +#define LL_SBS_HDPL0 0xB4U /*!< Hide protection level 0 */ +#define LL_SBS_HDPL1 0x51U /*!< Hide protection level 1 */ +#define LL_SBS_HDPL2 0x8AU /*!< Hide protection level 2 */ +#define LL_SBS_HDPL3 0x6FU /*!< Hide protection level 3 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_SBS_AXISRAM_WS SBS AXISRAM wait state number (when ECC=0) + * @{ + */ +#define LL_SBS_AXISRAM_NO_WS 0U /*!< No wait state added when accessing AXISRAM */ +#define LL_SBS_AXISRAM_ONE_WS SBS_PMCR_AXISRAM_WS /*!< One wait state added when accessing AXISRAM */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_SBS_ETH_PHYSEL SBS Ethernet PHY interface selection + * @{ + */ +#define LL_SBS_ETH_PHYSEL_GMII_MII 0U /*!< GMII or MII interface */ +#define LL_SBS_ETH_PHYSEL_RMII SBS_PMCR_ETH_PHYSEL_2 /*!< RMII interface */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_SBS_BOOSTVDDSEL SBS Booster Vdd selection + * @{ + */ +#define LL_SBS_BOOSTVDDSEL_VDDA 0U /*!< Vdda selected as analog switch booster voltage supply */ +#define LL_SBS_BOOSTVDDSEL_VDD SBS_PMCR_BOOSTVDDSEL /*!< Vdd selected as analog switch booster voltage supply */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_SBS_XSPI2_COMP_CODESEL SBS XSPI2 compensation cell code selection + * @{ + */ +#define LL_SBS_XSPI2_CODE_CELL 0U /*!< Code applied to compensation cell from cell */ +#define LL_SBS_XSPI2_CODE_REG SBS_CCCSR_XSPI2_COMP_CODESEL /*!< Code applied to compensation cell from register */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_SBS_XSPI1_COMP_CODESEL SBS XSPI1 compensation cell code selection + * @{ + */ +#define LL_SBS_XSPI1_CODE_CELL 0U /*!< Code applied to compensation cell from cell */ +#define LL_SBS_XSPI1_CODE_REG SBS_CCCSR_XSPI1_COMP_CODESEL /*!< Code applied to compensation cell from register */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_SBS_COMP_CODESEL SBS I/O compensation cell code selection + * @{ + */ +#define LL_SBS_IO_CODE_CELL 0U /*!< Code applied to compensation cell from cell */ +#define LL_SBS_IO_CODE_REG SBS_CCCSR_COMP_CODESEL /*!< Code applied to compensation cell from register */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_SBS_TIMBREAK SBS break lockup input timer peripherals + * @{ + */ +#define LL_SBS_TIMBREAK_PVD SBS_BKLOCKR_PVD_BL /*!< Connect the PVD output with TIM1/15/16/17 break input */ +#define LL_SBS_TIMBREAK_FLASHECC SBS_BKLOCKR_FLASHECC_BL /*!< Connect the Flash ECC double error detection flag with TIM1/15/16/17 break input */ +#define LL_SBS_TIMBREAK_CM7LCKUP SBS_BKLOCKR_CM7LCKUP_BL /*!< Connect the Cortex M7 lockup output with TIM1/15/16/17 break input */ +#define LL_SBS_TIMBREAK_BKRAMECC SBS_BKLOCKR_BKRAMECC_BL /*!< Connect the Backup RAM ECC double error detection flag with TIM1/15/16/17 break input */ +#define LL_SBS_TIMBREAK_DTCMECC SBS_BKLOCKR_DTCMECC_BL /*!< Connect the DTCM ECC double error detection flag with TIM1/15/16/17 break input */ +#define LL_SBS_TIMBREAK_ITCMECC SBS_BKLOCKR_ITCMECC_BL /*!< Connect the ITCM ECC double error detection flag with TIM1/15/16/17 break input */ +#define LL_SBS_TIMBREAK_ARAM3ECC SBS_BKLOCKR_ARAM3ECC_BL /*!< Connect the AXISRAM3 ECC double error detection flag with TIM1/15/16/17 break input */ +#define LL_SBS_TIMBREAK_ARAM1ECC SBS_BKLOCKR_ARAM1ECC_BL /*!< Connect the AXISRAM1 ECC double error detection flag with TIM1/15/16/17 break input */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_SBS_EXTI_PORT SBS EXTI PORT + * @{ + */ +#define LL_SBS_EXTI_PORTA 0U /*!< EXTI PORT A */ +#define LL_SBS_EXTI_PORTB SBS_EXTICR1_PC_EXTI0_0 /*!< EXTI PORT B */ +#define LL_SBS_EXTI_PORTC SBS_EXTICR1_PC_EXTI0_1 /*!< EXTI PORT C */ +#define LL_SBS_EXTI_PORTD (SBS_EXTICR1_PC_EXTI0_1 | SBS_EXTICR1_PC_EXTI0_0) /*!< EXTI PORT D */ +#define LL_SBS_EXTI_PORTE SBS_EXTICR1_PC_EXTI0_2 /*!< EXTI PORT E */ +#define LL_SBS_EXTI_PORTF (SBS_EXTICR1_PC_EXTI0_2 | SBS_EXTICR1_PC_EXTI0_0) /*!< EXTI PORT F */ +#define LL_SBS_EXTI_PORTG (SBS_EXTICR1_PC_EXTI0_2 | SBS_EXTICR1_PC_EXTI0_1) /*!< EXTI PORT G */ +#define LL_SBS_EXTI_PORTH (SBS_EXTICR1_PC_EXTI0_2 | SBS_EXTICR1_PC_EXTI0_1 | \ + SBS_EXTICR1_PC_EXTI0_0) /*!< EXTI PORT H */ +#define LL_SBS_EXTI_PORTM (SBS_EXTICR1_PC_EXTI0_3 | SBS_EXTICR1_PC_EXTI0_2) /*!< EXTI PORT M */ +#define LL_SBS_EXTI_PORTN (SBS_EXTICR1_PC_EXTI0_3 | SBS_EXTICR1_PC_EXTI0_2 | \ + SBS_EXTICR1_PC_EXTI0_0) /*!< EXTI PORT N */ +#define LL_SBS_EXTI_PORTO (SBS_EXTICR1_PC_EXTI0_3 | SBS_EXTICR1_PC_EXTI0_2 | \ + SBS_EXTICR1_PC_EXTI0_1) /*!< EXTI PORT 0 */ +#define LL_SBS_EXTI_PORTP (SBS_EXTICR1_PC_EXTI0_3 | SBS_EXTICR1_PC_EXTI0_2 | \ + SBS_EXTICR1_PC_EXTI0_1 | SBS_EXTICR1_PC_EXTI0_0) /*!< EXTI PORT P */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_SBS_EXTI_LINE SBS EXTI LINE + * @{ + */ +#define LL_SBS_EXTI_LINE0 ((0U << LL_SBS_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SBS_EXTI_LINE1 ((4U << LL_SBS_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SBS_EXTI_LINE2 ((8U << LL_SBS_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_16 | EXTICR[0] */ +#define LL_SBS_EXTI_LINE3 ((12U << LL_SBS_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_24 | EXTICR[0] */ +#define LL_SBS_EXTI_LINE4 ((0U << LL_SBS_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SBS_EXTI_LINE5 ((4U << LL_SBS_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SBS_EXTI_LINE6 ((8U << LL_SBS_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_16 | EXTICR[1] */ +#define LL_SBS_EXTI_LINE7 ((12U << LL_SBS_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_24 | EXTICR[1] */ +#define LL_SBS_EXTI_LINE8 ((0U << LL_SBS_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SBS_EXTI_LINE9 ((4U << LL_SBS_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SBS_EXTI_LINE10 ((8U << LL_SBS_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_16 | EXTICR[2] */ +#define LL_SBS_EXTI_LINE11 ((12U << LL_SBS_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_24 | EXTICR[2] */ +#define LL_SBS_EXTI_LINE12 ((0U << LL_SBS_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SBS_EXTI_LINE13 ((4U << LL_SBS_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SBS_EXTI_LINE14 ((8U << LL_SBS_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_16 | EXTICR[3] */ +#define LL_SBS_EXTI_LINE15 ((12U << LL_SBS_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_24 | EXTICR[3] */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_DBGMCU_DCRT DBGMCU Debug credential reset type + * @{ + */ +#define LL_DBGMCU_DCRT_SYSTEM 0U /*!< System reset revoke the debug authentication credentials */ +#define LL_DBGMCU_DCRT_POWER DBGMCU_CR_DCRT /*!< Power reset revoke the debug authentication credentials */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_DBGMCU_AHB5_STOP DBGMCU AHB5 GRP1 STOP + * @{ + */ +#define LL_DBGMCU_AHB5_GRP1_HPDMA0_STOP DBGMCU_AHB5FZR_HPDMA_0 /*!< The counter clock of HPDMA0 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB5_GRP1_HPDMA1_STOP DBGMCU_AHB5FZR_HPDMA_1 /*!< The counter clock of HPDMA1 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB5_GRP1_HPDMA2_STOP DBGMCU_AHB5FZR_HPDMA_2 /*!< The counter clock of HPDMA2 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB5_GRP1_HPDMA3_STOP DBGMCU_AHB5FZR_HPDMA_3 /*!< The counter clock of HPDMA3 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB5_GRP1_HPDMA4_STOP DBGMCU_AHB5FZR_HPDMA_4 /*!< The counter clock of HPDMA4 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB5_GRP1_HPDMA5_STOP DBGMCU_AHB5FZR_HPDMA_5 /*!< The counter clock of HPDMA5 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB5_GRP1_HPDMA6_STOP DBGMCU_AHB5FZR_HPDMA_6 /*!< The counter clock of HPDMA6 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB5_GRP1_HPDMA7_STOP DBGMCU_AHB5FZR_HPDMA_7 /*!< The counter clock of HPDMA7 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB5_GRP1_HPDMA8_STOP DBGMCU_AHB5FZR_HPDMA_8 /*!< The counter clock of HPDMA8 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB5_GRP1_HPDMA9_STOP DBGMCU_AHB5FZR_HPDMA_9 /*!< The counter clock of HPDMAM9 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB5_GRP1_HPDMA10_STOP DBGMCU_AHB5FZR_HPDMA_10 /*!< The counter clock of HPDMAM10 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB5_GRP1_HPDMA11_STOP DBGMCU_AHB5FZR_HPDMA_11 /*!< The counter clock of HPDMAM11 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB5_GRP1_HPDMA12_STOP DBGMCU_AHB5FZR_HPDMA_12 /*!< The counter clock of HPDMAM12 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB5_GRP1_HPDMA13_STOP DBGMCU_AHB5FZR_HPDMA_13 /*!< The counter clock of HPDMAM13 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB5_GRP1_HPDMA14_STOP DBGMCU_AHB5FZR_HPDMA_14 /*!< The counter clock of HPDMAM14 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB5_GRP1_HPDMA15_STOP DBGMCU_AHB5FZR_HPDMA_15 /*!< The counter clock of HPDMAM15 is stopped when the core is halted*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_DBGMCU_AHB1_STOP DBGMCU AHB1 GRP1 STOP + * @{ + */ +#define LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP DBGMCU_AHB1FZR_GPDMA_0 /*!< The counter clock of GPDMA0 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP DBGMCU_AHB1FZR_GPDMA_1 /*!< The counter clock of GPDMA1 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP DBGMCU_AHB1FZR_GPDMA_2 /*!< The counter clock of GPDMA2 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP DBGMCU_AHB1FZR_GPDMA_3 /*!< The counter clock of GPDMA3 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP DBGMCU_AHB1FZR_GPDMA_4 /*!< The counter clock of GPDMA4 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP DBGMCU_AHB1FZR_GPDMA_5 /*!< The counter clock of GPDMA5 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP DBGMCU_AHB1FZR_GPDMA_6 /*!< The counter clock of GPDMA6 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP DBGMCU_AHB1FZR_GPDMA_7 /*!< The counter clock of GPDMA7 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP DBGMCU_AHB1FZR_GPDMA_8 /*!< The counter clock of GPDMA8 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP DBGMCU_AHB1FZR_GPDMA_9 /*!< The counter clock of GPDMAM9 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP DBGMCU_AHB1FZR_GPDMA_10 /*!< The counter clock of GPDMAM10 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP DBGMCU_AHB1FZR_GPDMA_11 /*!< The counter clock of GPDMAM11 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP DBGMCU_AHB1FZR_GPDMA_12 /*!< The counter clock of GPDMAM12 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP DBGMCU_AHB1FZR_GPDMA_13 /*!< The counter clock of GPDMAM13 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP DBGMCU_AHB1FZR_GPDMA_14 /*!< The counter clock of GPDMAM14 is stopped when the core is halted*/ +#define LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP DBGMCU_AHB1FZR_GPDMA_15 /*!< The counter clock of GPDMAM15 is stopped when the core is halted*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_DBGMCU_APB1_STOP DBGMCU APB1 GRP1 STOP + * @{ + */ +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR_TIM2 /*!< The counter clock of TIM2 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR_TIM3 /*!< The counter clock of TIM3 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR_TIM4 /*!< The counter clock of TIM4 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR_TIM5 /*!< The counter clock of TIM5 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR_TIM6 /*!< The counter clock of TIM6 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR_TIM7 /*!< The counter clock of TIM7 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1FZR_TIM12 /*!< The counter clock of TIM12 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1FZR_TIM13 /*!< The counter clock of TIM13 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1FZR_TIM14 /*!< The counter clock of TIM14 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR_LPTIM1 /*!< The counter clock of LPTIM1 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR_WWDG /*!< The window watchdog counter clock is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR_I2C1 /*!< The I2C1 SMBus timeout is frozen*/ +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR_I2C2 /*!< The I2C2 SMBus timeout is frozen*/ +#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR_I2C3 /*!< The I2C3 SMBus timeout is frozen*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_DBGMCU_APB2_STOP DBGMCU APB2 GRP1 STOP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_TIM1 /*!< The counter clock of TIM1 is stopped when the core is halted*/ +#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2FZR_TIM9 /*!< The counter clock of TIM9 is stopped when the core is halted*/ +#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZR_TIM15 /*!< The counter clock of TIM15 is stopped when the core is halted*/ +#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_TIM16 /*!< The counter clock of TIM16 is stopped when the core is halted*/ +#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_TIM17 /*!< The counter clock of TIM17 is stopped when the core is halted*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_DBGMCU_APB4_STOP DBGMCU APB4 GRP1 STOP + * @{ + */ +#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZR_LPTIM2 /*!< The counter clock of LPTIM2 is stopped when the core is halted*/ +#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZR_LPTIM3 /*!< The counter clock of LPTIM2 is stopped when the core is halted*/ +#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZR_LPTIM4 /*!< The counter clock of LPTIM4 is stopped when the core is halted*/ +#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZR_LPTIM5 /*!< The counter clock of LPTIM5 is stopped when the core is halted*/ +#define LL_DBGMCU_APB4_GRP1_IWDG_STOP DBGMCU_APB4FZR_IWDG /*!< The counter clock of IWDG is stopped when the core is halted*/ +#define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZR_RTC /*!< The counter clock of RTC is stopped when the core is halted*/ +/** + * @} + */ + + +#if defined(VREFBUF) +/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE + * @{ + */ +#define LL_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 2 (VREF_OUT3) */ +#define LL_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 3 (VREF_OUT4) */ +/** + * @} + */ +#endif /* VREFBUF */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 0 /*!< FLASH Zero wait state */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */ +#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ +#define LL_FLASH_LATENCY_3 (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Three wait states */ +#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_2 /*!< FLASH Four wait states */ +#define LL_FLASH_LATENCY_5 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0) /*!< FLASH Five wait state */ +#define LL_FLASH_LATENCY_6 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1) /*!< FLASH Six wait state */ +#define LL_FLASH_LATENCY_7 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Seven wait states */ +#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_3 /*!< FLASH Eight wait states */ +#define LL_FLASH_LATENCY_9 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_0) /*!< FLASH Nine wait states */ +#define LL_FLASH_LATENCY_10 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_1) /*!< FLASH Ten wait state */ +#define LL_FLASH_LATENCY_11 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Eleven wait state */ +#define LL_FLASH_LATENCY_12 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2) /*!< FLASH Twelve wait states */ +#define LL_FLASH_LATENCY_13 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0) /*!< FLASH Thirteen wait states */ +#define LL_FLASH_LATENCY_14 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1) /*!< FLASH Fourteen wait states */ +#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY /*!< FLASH Fifteen wait states */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SBS SBS + * @{ + */ + +/** + * @brief Get initial vector for Cortex-M7 + * @rmtoll SBS_BOOTSR INITVTOR LL_SBS_GetBootAddress + * @retval Returned value is the physical boot address used by the Cortex-M7 after reset + */ +__STATIC_INLINE uint32_t LL_SBS_GetBootAddress(void) +{ + return (uint32_t)(READ_BIT(SBS->BOOTSR, SBS_BOOTSR_INITVTOR)); +} + +/** + * @brief Increment hide protection level + * @rmtoll SBS_HDPLCR INCR_HDPL LL_SBS_IncrementHDPL + * @retval None + */ +__STATIC_INLINE void LL_SBS_IncrementHDPL(void) +{ + MODIFY_REG(SBS->HDPLCR, SBS_HDPLCR_INCR_HDPL, LL_SBS_HDPL_INCREMENT_VALUE); +} + +/** + * @brief Get current hide protection level + * @rmtoll SBS_HDPLSR HDPL LL_SBS_GetCurrentHDPL + * @retval Returned value is the current hide protection level of the device: + * @arg @ref LL_SBS_HDPL0 + * @arg @ref LL_SBS_HDPL1 + * @arg @ref LL_SBS_HDPL2 + * @arg @ref LL_SBS_HDPL3 + */ +__STATIC_INLINE uint32_t LL_SBS_GetCurrentHDPL(void) +{ + return (uint32_t)(READ_BIT(SBS->HDPLSR, SBS_HDPLSR_HDPL)); +} + +/** + * @brief Set the authenticated debug hide protection level + * @rmtoll SBS_DBGCR DBG_AUTH_HDPL LL_SBS_SetAuthDbgHDPL + * @param Level This parameter can be one of the following values: + * @arg @ref LL_SBS_HDPL1 + * @arg @ref LL_SBS_HDPL2 + * @arg @ref LL_SBS_HDPL3 + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetAuthDbgHDPL(uint32_t Level) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL, (Level << SBS_DBGCR_DBG_AUTH_HDPL_Pos)); +} + +/** + * @brief Get current hide protection level + * @rmtoll SBS_DBGCR DBG_AUTH_HDPL LL_SBS_GetAuthDbgHDPL + * @retval Returned value is the hide protection level where the authenticated debug is opened: + * @arg @ref LL_SBS_HDPL1 + * @arg @ref LL_SBS_HDPL2 + * @arg @ref LL_SBS_HDPL3 + */ +__STATIC_INLINE uint32_t LL_SBS_GetAuthDbgHDPL(void) +{ + return (uint32_t)(READ_BIT(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL) >> SBS_DBGCR_DBG_AUTH_HDPL_Pos); +} + +/** + * @brief Unlock the debug + * @rmtoll SBS_DBGCR DBG_UNLOCK LL_SBS_UnlockDebug + * @retval None + */ +__STATIC_INLINE void LL_SBS_UnlockDebug(void) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK, LL_SBS_DBG_UNLOCK); +} + +/** + * @brief Check if the debug is unlocked + * @rmtoll SBS_DBGCR DBG_UNLOCK LL_SBS_IsUnlockedDebug + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsUnlockedDebug(void) +{ + return ((READ_BIT(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK) == LL_SBS_DBG_UNLOCK) ? 1UL : 0UL); +} + +/** + * @brief Unlock the access port + * @rmtoll SBS_DBGCR AP_UNLOCK LL_SBS_UnlockAccessPort + * @retval None + */ +__STATIC_INLINE void LL_SBS_UnlockAccessPort(void) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK, LL_SBS_ACCESS_PORT_UNLOCK); +} + +/** + * @brief Check if the access port is unlocked + * @rmtoll SBS_DBGCR AP_UNLOCK LL_SBS_IsUnlockedAccessPort + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsUnlockedAccessPort(void) +{ + return ((READ_BIT(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK) == LL_SBS_ACCESS_PORT_UNLOCK) ? 1UL : 0UL); +} + +/** + * @brief Lock the debug configuration + * @rmtoll SBS_DBGLOCKR DBGCFG_LOCK LL_SBS_LockDebugConfig + * @retval None + */ +__STATIC_INLINE void LL_SBS_LockDebugConfig(void) +{ + MODIFY_REG(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK, LL_SBS_DBG_CONFIG_LOCK); +} + +/** + * @brief Unlock the debug configuration + * @rmtoll SBS_DBGLOCKR DBGCFG_LOCK LL_SBS_UnlockDebugConfig + * @retval None + */ +__STATIC_INLINE void LL_SBS_UnlockDebugConfig(void) +{ + MODIFY_REG(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK, LL_SBS_DBG_CONFIG_UNLOCK); +} + +/** + * @brief Check if the debug configuration is unlocked + * @rmtoll SBS_DBGLOCKR DBGCFG_LOCK LL_SBS_IsUnlockedDebugConfig + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsUnlockedDebugConfig(void) +{ + return ((READ_BIT(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK) == LL_SBS_DBG_CONFIG_UNLOCK) ? 1UL : 0UL); +} + +/** + * @brief Set the command to be passed to RSS + * @rmtoll SBS_RSSCMDR RSSCMD LL_SBS_SetRSSCmd + * @param Command This parameter can have a value between 0 and 0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetRSSCmd(uint32_t Command) +{ + MODIFY_REG(SBS->RSSCMDR, SBS_RSSCMDR_RSSCMD, Command); +} + +/** + * @brief Get the command which will be passed to RSS + * @rmtoll SBS_RSSCMDR RSSCMD LL_SBS_GetRSSCmd + * @retval Returned value is the command which will be passed to RSS (value between 0 and 0xFFFF) + */ +__STATIC_INLINE uint32_t LL_SBS_GetRSSCmd(void) +{ + return (uint32_t)(READ_BIT(SBS->RSSCMDR, SBS_RSSCMDR_RSSCMD)); +} + +/** + * @brief Set the number of AXISRAM wait state (when ECC=0) + * @rmtoll SBS_PMCR AXISRAM_WS LL_SBS_SetAXISRAMWaitState + * @param WaitState This parameter can be one of the following values: + * @arg @ref LL_SBS_AXISRAM_NO_WS + * @arg @ref LL_SBS_AXISRAM_ONE_WS + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetAXISRAMWaitState(uint32_t WaitState) +{ + MODIFY_REG(SBS->PMCR, SBS_PMCR_AXISRAM_WS, WaitState); +} + +/** + * @brief Get the number of AXISRAM wait state (when ECC=0) + * @rmtoll SBS_PMCR AXISRAM_WS LL_SBS_GetAXISRAMWaitState + * @retval Returned value is the number of wait state when accessing AXISRAM: + * @arg @ref LL_SBS_AXISRAM_NO_WS + * @arg @ref LL_SBS_AXISRAM_ONE_WS + */ +__STATIC_INLINE uint32_t LL_SBS_GetAXISRAMWaitState(void) +{ + return (uint32_t)(READ_BIT(SBS->PMCR, SBS_PMCR_AXISRAM_WS)); +} + +/** + * @brief Configure the Ethernet PHY interface + * @rmtoll SBS_PMCR ETH_PHYSEL LL_SBS_SetEthernetPhy + * @param Interface This parameter can be one of the following values: + * @arg @ref LL_SBS_ETH_PHYSEL_GMII_MII + * @arg @ref LL_SBS_ETH_PHYSEL_RMII + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetEthernetPhy(uint32_t Interface) +{ + MODIFY_REG(SBS->PMCR, SBS_PMCR_ETH_PHYSEL, Interface); +} + +/** + * @brief Get the selected Ethernet PHY interface + * @rmtoll SBS_PMCR ETH_PHYSEL LL_SBS_GetEthernetPhy + * @retval Returned value is the selected Ethernet PHY interface: + * @arg @ref LL_SBS_ETH_PHYSEL_GMII_MII + * @arg @ref LL_SBS_ETH_PHYSEL_RMII + */ +__STATIC_INLINE uint32_t LL_SBS_GetEthernetPhy(void) +{ + return (uint32_t)(READ_BIT(SBS->PMCR, SBS_PMCR_ETH_PHYSEL)); +} + +/** + * @brief Configure the analog switch supply voltage for booster + * @rmtoll SBS_PMCR BOOSTVDDSEL LL_SBS_SetBoosterVoltage + * @param Voltage This parameter can be one of the following values: + * @arg @ref LL_SBS_BOOSTVDDSEL_VDDA + * @arg @ref LL_SBS_BOOSTVDDSEL_VDD + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetBoosterVoltage(uint32_t Voltage) +{ + MODIFY_REG(SBS->PMCR, SBS_PMCR_BOOSTVDDSEL, Voltage); +} + +/** + * @brief Get the selected analog switch supply voltage for booster + * @rmtoll SBS_PMCR BOOSTVDDSEL LL_SBS_GetBoosterVoltage + * @retval Returned value is the selected analog switch supply voltage: + * @arg @ref LL_SBS_BOOSTVDDSEL_VDDA + * @arg @ref LL_SBS_BOOSTVDDSEL_VDD + */ +__STATIC_INLINE uint32_t LL_SBS_GetBoosterVoltage(void) +{ + return (uint32_t)(READ_BIT(SBS->PMCR, SBS_PMCR_BOOSTVDDSEL)); +} + +/** + * @brief Enable the booster + * @rmtoll SBS_PMCR BOOSTEN LL_SBS_EnableBooster + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableBooster(void) +{ + SET_BIT(SBS->PMCR, SBS_PMCR_BOOSTEN); +} + +/** + * @brief Disable the booster + * @rmtoll SBS_PMCR BOOSTEN LL_SBS_DisableBooster + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableBooster(void) +{ + CLEAR_BIT(SBS->PMCR, SBS_PMCR_BOOSTEN); +} + +/** + * @brief Check if the booster is enabled + * @rmtoll SBS_PMCR BOOSTEN LL_SBS_IsEnabledBooster + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledBooster(void) +{ + return ((READ_BIT(SBS->PMCR, SBS_PMCR_BOOSTEN) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Enable Floating Point Unit Invalid operation Interrupt + * @rmtoll SBS_FPUIMR FPU_IE_0 LL_SBS_EnableIT_FPU_IOC + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_IOC(void) +{ + SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0); +} + +/** + * @brief Enable Floating Point Unit Divide-by-zero Interrupt + * @rmtoll SBS_FPUIMR FPU_IE_1 LL_SBS_EnableIT_FPU_DZC + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_DZC(void) +{ + SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1); +} + +/** + * @brief Enable Floating Point Unit Underflow Interrupt + * @rmtoll SBS_FPUIMR FPU_IE_2 LL_SBS_EnableIT_FPU_UFC + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_UFC(void) +{ + SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2); +} + +/** + * @brief Enable Floating Point Unit Overflow Interrupt + * @rmtoll SBS_FPUIMR FPU_IE_3 LL_SBS_EnableIT_FPU_OFC + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_OFC(void) +{ + SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3); +} + +/** + * @brief Enable Floating Point Unit Input denormal Interrupt + * @rmtoll SBS_FPUIMR FPU_IE_4 LL_SBS_EnableIT_FPU_IDC + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_IDC(void) +{ + SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4); +} + +/** + * @brief Enable Floating Point Unit Inexact Interrupt + * @rmtoll SBS_FPUIMR FPU_IE_5 LL_SBS_EnableIT_FPU_IXC + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableIT_FPU_IXC(void) +{ + SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5); +} + +/** + * @brief Disable Floating Point Unit Invalid operation Interrupt + * @rmtoll SBS_FPUIMR FPU_IE_0 LL_SBS_DisableIT_FPU_IOC + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_IOC(void) +{ + CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0); +} + +/** + * @brief Disable Floating Point Unit Divide-by-zero Interrupt + * @rmtoll SBS_FPUIMR FPU_IE_1 LL_SBS_DisableIT_FPU_DZC + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_DZC(void) +{ + CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1); +} + +/** + * @brief Disable Floating Point Unit Underflow Interrupt + * @rmtoll SBS_FPUIMR FPU_IE_2 LL_SBS_DisableIT_FPU_UFC + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_UFC(void) +{ + CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2); +} + +/** + * @brief Disable Floating Point Unit Overflow Interrupt + * @rmtoll SBS_FPUIMR FPU_IE_3 LL_SBS_DisableIT_FPU_OFC + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_OFC(void) +{ + CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3); +} + +/** + * @brief Disable Floating Point Unit Input denormal Interrupt + * @rmtoll SBS_FPUIMR FPU_IE_4 LL_SBS_DisableIT_FPU_IDC + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_IDC(void) +{ + CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4); +} + +/** + * @brief Disable Floating Point Unit Inexact Interrupt + * @rmtoll SBS_FPUIMR FPU_IE_5 LL_SBS_DisableIT_FPU_IXC + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableIT_FPU_IXC(void) +{ + CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5); +} + +/** + * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled. + * @rmtoll SBS_FPUIMR FPU_IE_0 LL_SBS_IsEnabledIT_FPU_IOC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IOC(void) +{ + return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0) == SBS_FPUIMR_FPU_IE_0) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled. + * @rmtoll SBS_FPUIMR FPU_IE_1 LL_SBS_IsEnabledIT_FPU_DZC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_DZC(void) +{ + return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1) == SBS_FPUIMR_FPU_IE_1) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled. + * @rmtoll SBS_FPUIMR FPU_IE_2 LL_SBS_IsEnabledIT_FPU_UFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_UFC(void) +{ + return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2) == SBS_FPUIMR_FPU_IE_2) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled. + * @rmtoll SBS_FPUIMR FPU_IE_3 LL_SBS_IsEnabledIT_FPU_OFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_OFC(void) +{ + return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3) == SBS_FPUIMR_FPU_IE_3) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled. + * @rmtoll SBS_FPUIMR FPU_IE_4 LL_SBS_IsEnabledIT_FPU_IDC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IDC(void) +{ + return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4) == SBS_FPUIMR_FPU_IE_4) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled. + * @rmtoll SBS_FPUIMR FPU_IE_5 LL_SBS_IsEnabledIT_FPU_IXC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IXC(void) +{ + return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5) == SBS_FPUIMR_FPU_IE_5) ? 1UL : 0UL); +} + +/** + * @brief Check if the automatic erase of BKPRAM and PKARAM memories are done + * @rmtoll SBS_MESR MEF LL_SBS_IsDoneMemoryErase + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsDoneMemoryErase(void) +{ + return (READ_BIT(SBS->MESR, SBS_MESR_MEF)); +} + +/** + * @brief Enable the XSPI2 speed optimization + * @rmtoll SBS_CCCSR XSPI2_IOHSLV LL_SBS_EnableXSPI2SpeedOptim + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableXSPI2SpeedOptim(void) +{ + SET_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_IOHSLV); +} + +/** + * @brief Disable the XSPI2 speed optimization + * @rmtoll SBS_CCCSR XSPI2_IOHSLV LL_SBS_DisableXSPI2SpeedOptim + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableXSPI2SpeedOptim(void) +{ + CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_IOHSLV); +} + +/** + * @brief Check if the XSPI2 speed optimization is enabled + * @rmtoll SBS_CCCSR XSPI2_IOHSLV LL_SBS_IsEnabledXSPI2SpeedOptim + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledXSPI2SpeedOptim(void) +{ + return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_IOHSLV) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Enable the XSPI1 speed optimization + * @rmtoll SBS_CCCSR XSPI1_IOHSLV LL_SBS_EnableXSPI1SpeedOptim + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableXSPI1SpeedOptim(void) +{ + SET_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_IOHSLV); +} + +/** + * @brief Disable the XSPI1 speed optimization + * @rmtoll SBS_CCCSR XSPI1_IOHSLV LL_SBS_DisableXSPI1SpeedOptim + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableXSPI1SpeedOptim(void) +{ + CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_IOHSLV); +} + +/** + * @brief Check if the XSPI1 speed optimization is enabled + * @rmtoll SBS_CCCSR XSPI1_IOHSLV LL_SBS_IsEnabledXSPI1SpeedOptim + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledXSPI1SpeedOptim(void) +{ + return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_IOHSLV) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Enable the I/O speed optimization + * @rmtoll SBS_CCCSR IOHSLV LL_SBS_EnableIOSpeedOptim + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableIOSpeedOptim(void) +{ + SET_BIT(SBS->CCCSR, SBS_CCCSR_IOHSLV); +} + +/** + * @brief Disable the I/O speed optimization + * @rmtoll SBS_CCCSR IOHSLV LL_SBS_DisableIOSpeedOptim + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableIOSpeedOptim(void) +{ + CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_IOHSLV); +} + +/** + * @brief Check if the I/O speed optimization is enabled + * @rmtoll SBS_CCCSR IOHSLV LL_SBS_IsEnabledIOSpeedOptim + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIOSpeedOptim(void) +{ + return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_IOHSLV) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Check if the XSPI2 compensation cell is ready + * @rmtoll SBS_CCCSR XSPI2_COMP_RDY LL_SBS_IsReadyXSPI2CompCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsReadyXSPI2CompCell(void) +{ + return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_COMP_RDY) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Check if the XSPI1 compensation cell is ready + * @rmtoll SBS_CCCSR XSPI1_COMP_RDY LL_SBS_IsReadyXSPI1CompCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsReadyXSPI1CompCell(void) +{ + return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_COMP_RDY) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Check if the I/O compensation cell is ready + * @rmtoll SBS_CCCSR COMP_RDY LL_SBS_IsReadyIOCompCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsReadyIOCompCell(void) +{ + return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_COMP_RDY) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Configure the code for the XSPI2 compensation cell + * @rmtoll SBS_CCCSR XSPI2_COMP_CODESEL LL_SBS_SetXSPI2CompCellCode + * @param Code This parameter can be one of the following values: + * @arg @ref LL_SBS_XSPI2_CODE_CELL + * @arg @ref LL_SBS_XSPI2_CODE_REG + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetXSPI2CompCellCode(uint32_t Code) +{ + MODIFY_REG(SBS->CCCSR, SBS_CCCSR_XSPI2_COMP_CODESEL, Code); +} + +/** + * @brief Get the selected code for the XSPI2 compensation cell + * @rmtoll SBS_CCCSR XSPI2_COMP_CODESEL LL_SBS_GetXSPI2CompCellCode + * @retval Returned value is the selected code for the XSPI2 compensation cell: + * @arg @ref LL_SBS_XSPI2_CODE_CELL + * @arg @ref LL_SBS_XSPI2_CODE_REG + */ +__STATIC_INLINE uint32_t LL_SBS_GetXSPI2CompCellCode(void) +{ + return (uint32_t)(READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_COMP_CODESEL)); +} + +/** + * @brief Enable the XSPI2 compensation cell + * @rmtoll SBS_PMCR XSPI2_COMP_EN LL_SBS_EnableXSPI2CompCell + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableXSPI2CompCell(void) +{ + SET_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_COMP_EN); +} + +/** + * @brief Disable the XSPI2 compensation cell + * @rmtoll SBS_CCCSR XSPI2_COMP_EN LL_SBS_DisableXSPI2CompCell + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableXSPI2CompCell(void) +{ + CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_COMP_EN); +} + +/** + * @brief Check if the XSPI2 compensation cell is enabled + * @rmtoll SBS_CCCSR XSPI2_COMP_EN LL_SBS_IsEnabledXSPI2CompCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledXSPI2CompCell(void) +{ + return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_COMP_EN) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Configure the code for the XSPI1 compensation cell + * @rmtoll SBS_CCCSR XSPI1_COMP_CODESEL LL_SBS_SetXSPI1CompCellCode + * @param Code This parameter can be one of the following values: + * @arg @ref LL_SBS_XSPI1_CODE_CELL + * @arg @ref LL_SBS_XSPI1_CODE_REG + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetXSPI1CompCellCode(uint32_t Code) +{ + MODIFY_REG(SBS->CCCSR, SBS_CCCSR_XSPI1_COMP_CODESEL, Code); +} + +/** + * @brief Get the selected code for the XSPI2 compensation cell + * @rmtoll SBS_CCCSR XSPI1_COMP_CODESEL LL_SBS_GetXSPI1CompCellCode + * @retval Returned value is the selected code for the XSPI1 compensation cell: + * @arg @ref LL_SBS_XSPI1_CODE_CELL + * @arg @ref LL_SBS_XSPI1_CODE_REG + */ +__STATIC_INLINE uint32_t LL_SBS_GetXSPI1CompCellCode(void) +{ + return (uint32_t)(READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_COMP_CODESEL)); +} + +/** + * @brief Enable the XSPI1 compensation cell + * @rmtoll SBS_PMCR XSPI1_COMP_EN LL_SBS_EnableXSPI1CompCell + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableXSPI1CompCell(void) +{ + SET_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_COMP_EN); +} + +/** + * @brief Disable the XSPI1 compensation cell + * @rmtoll SBS_CCCSR XSPI1_COMP_EN LL_SBS_DisableXSPI1CompCell + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableXSPI1CompCell(void) +{ + CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_COMP_EN); +} + +/** + * @brief Check if the XSPI1 compensation cell is enabled + * @rmtoll SBS_CCCSR XSPI1_COMP_EN LL_SBS_IsEnabledXSPI1CompCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledXSPI1CompCell(void) +{ + return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_COMP_EN) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Configure the code for the I/O compensation cell + * @rmtoll SBS_CCCSR COMP_CODESEL LL_SBS_SetIOCompCellCode + * @param Code This parameter can be one of the following values: + * @arg @ref LL_SBS_IO_CODE_CELL + * @arg @ref LL_SBS_IO_CODE_REG + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetIOCompCellCode(uint32_t Code) +{ + MODIFY_REG(SBS->CCCSR, SBS_CCCSR_COMP_CODESEL, Code); +} + +/** + * @brief Get the selected code for the I/O compensation cell + * @rmtoll SBS_CCCSR COMP_CODESEL LL_SBS_GetIOCompCellCode + * @retval Returned value is the selected code for the I/O compensation cell: + * @arg @ref LL_SBS_IO_CODE_CELL + * @arg @ref LL_SBS_IO_CODE_REG + */ +__STATIC_INLINE uint32_t LL_SBS_GetIOCompCellCode(void) +{ + return (uint32_t)(READ_BIT(SBS->CCCSR, SBS_CCCSR_COMP_CODESEL)); +} + +/** + * @brief Enable the I/O compensation cell + * @rmtoll SBS_PMCR COMP_EN LL_SBS_EnableIOCompCell + * @retval None + */ +__STATIC_INLINE void LL_SBS_EnableIOCompCell(void) +{ + SET_BIT(SBS->CCCSR, SBS_CCCSR_COMP_EN); +} + +/** + * @brief Disable the I/O compensation cell + * @rmtoll SBS_CCCSR COMP_EN LL_SBS_DisableIOCompCell + * @retval None + */ +__STATIC_INLINE void LL_SBS_DisableIOCompCell(void) +{ + CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_COMP_EN); +} + +/** + * @brief Check if the I/O compensation cell is enabled + * @rmtoll SBS_CCCSR COMP_EN LL_SBS_IsEnabledIOCompCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SBS_IsEnabledIOCompCell(void) +{ + return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_COMP_EN) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Get the XSPI2 PMOS compensation + * @rmtoll SBS_CCVALR XSPI2_PSRC LL_SBS_GetXSPI2PmosComp + * @retval Returned value is the slew-rate compensation for XSPI2 PMOS transistors (value between 0 and 0xF) + */ +__STATIC_INLINE uint32_t LL_SBS_GetXSPI2PmosComp(void) +{ + return (uint32_t)((READ_BIT(SBS->CCVALR, SBS_CCVALR_XSPI2_PSRC)) >> SBS_CCVALR_XSPI2_PSRC_Pos); +} + +/** + * @brief Get the XSPI2 NMOS compensation + * @rmtoll SBS_CCVALR XSPI2_NSRC LL_SBS_GetXSPI2NmosComp + * @retval Returned value is the slew-rate compensation for XSPI2 NMOS transistors (value between 0 and 0xF) + */ +__STATIC_INLINE uint32_t LL_SBS_GetXSPI2NmosComp(void) +{ + return (uint32_t)((READ_BIT(SBS->CCVALR, SBS_CCVALR_XSPI2_NSRC)) >> SBS_CCVALR_XSPI2_NSRC_Pos); +} + +/** + * @brief Get the XSPI1 PMOS compensation + * @rmtoll SBS_CCVALR XSPI1_PSRC LL_SBS_GetXSPI1PmosComp + * @retval Returned value is the slew-rate compensation for XSPI1 PMOS transistors (value between 0 and 0xF) + */ +__STATIC_INLINE uint32_t LL_SBS_GetXSPI1PmosComp(void) +{ + return (uint32_t)((READ_BIT(SBS->CCVALR, SBS_CCVALR_XSPI1_PSRC)) >> SBS_CCVALR_XSPI1_PSRC_Pos); +} + +/** + * @brief Get the XSPI NMOS compensation + * @rmtoll SBS_CCVALR XSPI1_NSRC LL_SBS_GetXSPI1NmosComp + * @retval Returned value is the slew-rate compensation for XSPI1 NMOS transistors (value between 0 and 0xF) + */ +__STATIC_INLINE uint32_t LL_SBS_GetXSPI1NmosComp(void) +{ + return (uint32_t)((READ_BIT(SBS->CCVALR, SBS_CCVALR_XSPI1_NSRC)) >> SBS_CCVALR_XSPI1_NSRC_Pos); +} + +/** + * @brief Get the I/O PMOS compensation + * @rmtoll SBS_CCVALR PSRC LL_SBS_GetIOPmosComp + * @retval Returned value is the slew-rate compensation for I/O PMOS transistors (value between 0 and 0xF) + */ +__STATIC_INLINE uint32_t LL_SBS_GetIOPmosComp(void) +{ + return (uint32_t)((READ_BIT(SBS->CCVALR, SBS_CCVALR_PSRC)) >> SBS_CCVALR_PSRC_Pos); +} + +/** + * @brief Get the I/O NMOS compensation + * @rmtoll SBS_CCVALR NSRC LL_SBS_GetIONmosComp + * @retval Returned value is the slew-rate compensation for I/O NMOS transistors (value between 0 and 0xF) + */ +__STATIC_INLINE uint32_t LL_SBS_GetIONmosComp(void) +{ + return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_NSRC)); +} + +/** + * @brief Set the XSPI2 software PMOS compensation + * @rmtoll SBS_CCSWVALR XSPI2_SW_PSRC LL_SBS_SetXSPI2SwPmosComp + * @param Compensation This parameter can have a value between 0 and 0xF + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetXSPI2SwPmosComp(uint32_t Compensation) +{ + MODIFY_REG(SBS->CCSWVALR, SBS_CCSWVALR_XSPI2_SW_PSRC, (Compensation << SBS_CCSWVALR_XSPI2_SW_PSRC_Pos)); +} + +/** + * @brief Get the XSPI2 PMOS compensation + * @rmtoll SBS_CCSWVALR XSPI2_SW_PSRC LL_SBS_GetXSPI2SwPmosComp + * @retval Returned value is the slew-rate compensation for XSPI2 PMOS transistors (value between 0 and 0xF) + */ +__STATIC_INLINE uint32_t LL_SBS_GetXSPI2SwPmosComp(void) +{ + return (uint32_t)((READ_BIT(SBS->CCSWVALR, SBS_CCSWVALR_XSPI2_SW_PSRC)) >> SBS_CCSWVALR_XSPI2_SW_PSRC_Pos); +} + +/** + * @brief Set the XSPI2 software NMOS compensation + * @rmtoll SBS_CCSWVALR XSPI2_SW_NSRC LL_SBS_SetXSPI2SwNmosComp + * @param Compensation This parameter can have a value between 0 and 0xF + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetXSPI2SwNmosComp(uint32_t Compensation) +{ + MODIFY_REG(SBS->CCSWVALR, SBS_CCSWVALR_XSPI2_SW_NSRC, (Compensation << SBS_CCSWVALR_XSPI2_SW_NSRC_Pos)); +} + +/** + * @brief Get the XSPI2 software NMOS compensation + * @rmtoll SBS_CCSWVALR XSPI2_SW_NSRC LL_SBS_GetXSPI2SwNmosComp + * @retval Returned value is the slew-rate compensation for XSPI2 NMOS transistors (value between 0 and 0xF) + */ +__STATIC_INLINE uint32_t LL_SBS_GetXSPI2SwNmosComp(void) +{ + return (uint32_t)((READ_BIT(SBS->CCSWVALR, SBS_CCSWVALR_XSPI2_SW_NSRC)) >> SBS_CCSWVALR_XSPI2_SW_NSRC_Pos); +} + +/** + * @brief Set the XSPI1 software PMOS compensation + * @rmtoll SBS_CCSWVALR XSPI2_SW_PSRC LL_SBS_SetXSPI1SwPmosComp + * @param Compensation This parameter can have a value between 0 and 0xF + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetXSPI1SwPmosComp(uint32_t Compensation) +{ + MODIFY_REG(SBS->CCSWVALR, SBS_CCSWVALR_XSPI1_SW_PSRC, (Compensation << SBS_CCSWVALR_XSPI1_SW_PSRC_Pos)); +} + +/** + * @brief Get the XSPI1 PMOS compensation + * @rmtoll SBS_CCSWVALR XSPI1_SW_PSRC LL_SBS_GetXSPI1SwPmosComp + * @retval Returned value is the slew-rate compensation for XSPI1 PMOS transistors (value between 0 and 0xF) + */ +__STATIC_INLINE uint32_t LL_SBS_GetXSPI1SwPmosComp(void) +{ + return (uint32_t)((READ_BIT(SBS->CCSWVALR, SBS_CCSWVALR_XSPI1_SW_PSRC)) >> SBS_CCSWVALR_XSPI1_SW_PSRC_Pos); +} + +/** + * @brief Set the XSPI1 software NMOS compensation + * @rmtoll SBS_CCSWVALR XSPI1_SW_NSRC LL_SBS_SetXSPI1SwNmosComp + * @param Compensation This parameter can have a value between 0 and 0xF + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetXSPI1SwNmosComp(uint32_t Compensation) +{ + MODIFY_REG(SBS->CCSWVALR, SBS_CCSWVALR_XSPI1_SW_NSRC, (Compensation << SBS_CCSWVALR_XSPI1_SW_NSRC_Pos)); +} + +/** + * @brief Get the XSPI1 software NMOS compensation + * @rmtoll SBS_CCSWVALR XSPI1_SW_NSRC LL_SBS_GetXSPI1SwNmosComp + * @retval Returned value is the slew-rate compensation for XSPI1 NMOS transistors (value between 0 and 0xF) + */ +__STATIC_INLINE uint32_t LL_SBS_GetXSPI1SwNmosComp(void) +{ + return (uint32_t)((READ_BIT(SBS->CCSWVALR, SBS_CCSWVALR_XSPI1_SW_NSRC)) >> SBS_CCSWVALR_XSPI1_SW_NSRC_Pos); +} + +/** + * @brief Set the I/O software PMOS compensation + * @rmtoll SBS_CCSWVALR SW_PSRC LL_SBS_SetIOSwPmosComp + * @param Compensation This parameter can have a value between 0 and 0xF + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetIOSwPmosComp(uint32_t Compensation) +{ + MODIFY_REG(SBS->CCSWVALR, SBS_CCSWVALR_SW_PSRC, (Compensation << SBS_CCSWVALR_SW_PSRC_Pos)); +} + +/** + * @brief Get the I/O PMOS compensation + * @rmtoll SBS_CCSWVALR SW_PSRC LL_SBS_GetIOSwPmosComp + * @retval Returned value is the slew-rate compensation for I/O PMOS transistors (value between 0 and 0xF) + */ +__STATIC_INLINE uint32_t LL_SBS_GetIOSwPmosComp(void) +{ + return (uint32_t)((READ_BIT(SBS->CCSWVALR, SBS_CCSWVALR_SW_PSRC)) >> SBS_CCSWVALR_SW_PSRC_Pos); +} + +/** + * @brief Set the I/O software NMOS compensation + * @rmtoll SBS_CCSWVALR SW_NSRC LL_SBS_SetIOSwNmosComp + * @param Compensation This parameter can have a value between 0 and 0xF + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetIOSwNmosComp(uint32_t Compensation) +{ + MODIFY_REG(SBS->CCSWVALR, SBS_CCSWVALR_SW_NSRC, (Compensation << SBS_CCSWVALR_SW_NSRC_Pos)); +} + +/** + * @brief Get the I/O software NMOS compensation + * @rmtoll SBS_CCSWVALR SW_NSRC LL_SBS_GetIOSwNmosComp + * @retval Returned value is the slew-rate compensation for I/O NMOS transistors (value between 0 and 0xF) + */ +__STATIC_INLINE uint32_t LL_SBS_GetIOSwNmosComp(void) +{ + return (uint32_t)((READ_BIT(SBS->CCSWVALR, SBS_CCSWVALR_SW_NSRC)) >> SBS_CCSWVALR_SW_NSRC_Pos); +} + +/** + * @brief Set connections to TIM1/15/16/17 Break inputs + * @rmtoll SBS_BKLOCKR PVD_BL LL_SBS_SetTIMBreakInputs\n + * SBS_BKLOCKR FLASHECC_BL LL_SBS_SetTIMBreakInputs\n + * SBS_BKLOCKR CM7LCKUP_BL LL_SBS_SetTIMBreakInputs\n + * SBS_BKLOCKR BKRAMECC_BL LL_SBS_SetTIMBreakInputs\n + * SBS_BKLOCKR DTCMECC_BL LL_SBS_SetTIMBreakInputs\n + * SBS_BKLOCKR ITCMECC_BL LL_SBS_SetTIMBreakInputs\n + * SBS_BKLOCKR ARAM3ECC_BL LL_SBS_SetTIMBreakInputs\n + * SBS_BKLOCKR ARAM1ECC_BL LL_SBS_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SBS_TIMBREAK_PVD + * @arg @ref LL_SBS_TIMBREAK_FLASHECC + * @arg @ref LL_SBS_TIMBREAK_CM7LCKUP + * @arg @ref LL_SBS_TIMBREAK_BKRAMECC + * @arg @ref LL_SBS_TIMBREAK_DTCMECC + * @arg @ref LL_SBS_TIMBREAK_ITCMECC + * @arg @ref LL_SBS_TIMBREAK_ARAM3ECC + * @arg @ref LL_SBS_TIMBREAK_ARAM1ECC + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetTIMBreakInputs(uint32_t Break) +{ + MODIFY_REG(SBS->BKLOCKR, + (SBS_BKLOCKR_PVD_BL | SBS_BKLOCKR_FLASHECC_BL | SBS_BKLOCKR_CM7LCKUP_BL | SBS_BKLOCKR_BKRAMECC_BL | \ + SBS_BKLOCKR_DTCMECC_BL | SBS_BKLOCKR_ITCMECC_BL | SBS_BKLOCKR_ARAM3ECC_BL | SBS_BKLOCKR_ARAM1ECC_BL) + , Break); +} + +/** + * @brief Get connections to TIM1/15/16/17 Break inputs + * @rmtoll SBS_BKLOCKR CLL LL_SBS_GetTIMBreakInputs\n + * SBS_BKLOCKR SPL LL_SBS_GetTIMBreakInputs\n + * SBS_BKLOCKR PVDL LL_SBS_GetTIMBreakInputs\n + * SBS_BKLOCKR ECCL LL_SBS_GetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SBS_TIMBREAK_PVD + * @arg @ref LL_SBS_TIMBREAK_FLASHECC + * @arg @ref LL_SBS_TIMBREAK_CM7LCKUP + * @arg @ref LL_SBS_TIMBREAK_BKRAMECC + * @arg @ref LL_SBS_TIMBREAK_DTCMECC + * @arg @ref LL_SBS_TIMBREAK_ITCMECC + * @arg @ref LL_SBS_TIMBREAK_ARAM3ECC + * @arg @ref LL_SBS_TIMBREAK_ARAM1ECC + */ +__STATIC_INLINE uint32_t LL_SBS_GetTIMBreakInputs(void) +{ + return (uint32_t)(READ_BIT(SBS->BKLOCKR, + (SBS_BKLOCKR_PVD_BL | SBS_BKLOCKR_FLASHECC_BL | SBS_BKLOCKR_CM7LCKUP_BL | \ + SBS_BKLOCKR_BKRAMECC_BL | SBS_BKLOCKR_DTCMECC_BL | SBS_BKLOCKR_ITCMECC_BL | \ + SBS_BKLOCKR_ARAM3ECC_BL | SBS_BKLOCKR_ARAM1ECC_BL))); +} + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SBS_EXTICR1 EXTI0 LL_SBS_SetEXTISource\n + * SBS_EXTICR1 EXTI1 LL_SBS_SetEXTISource\n + * SBS_EXTICR1 EXTI2 LL_SBS_SetEXTISource\n + * SBS_EXTICR1 EXTI3 LL_SBS_SetEXTISource\n + * SBS_EXTICR2 EXTI4 LL_SBS_SetEXTISource\n + * SBS_EXTICR2 EXTI5 LL_SBS_SetEXTISource\n + * SBS_EXTICR2 EXTI6 LL_SBS_SetEXTISource\n + * SBS_EXTICR2 EXTI7 LL_SBS_SetEXTISource\n + * SBS_EXTICR3 EXTI8 LL_SBS_SetEXTISource\n + * SBS_EXTICR3 EXTI9 LL_SBS_SetEXTISource\n + * SBS_EXTICR3 EXTI10 LL_SBS_SetEXTISource\n + * SBS_EXTICR3 EXTI11 LL_SBS_SetEXTISource\n + * SBS_EXTICR4 EXTI12 LL_SBS_SetEXTISource\n + * SBS_EXTICR4 EXTI13 LL_SBS_SetEXTISource\n + * SBS_EXTICR4 EXTI14 LL_SBS_SetEXTISource\n + * SBS_EXTICR4 EXTI15 LL_SBS_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SBS_EXTI_PORTA + * @arg @ref LL_SBS_EXTI_PORTB + * @arg @ref LL_SBS_EXTI_PORTC + * @arg @ref LL_SBS_EXTI_PORTD + * @arg @ref LL_SBS_EXTI_PORTE + * @arg @ref LL_SBS_EXTI_PORTF + * @arg @ref LL_SBS_EXTI_PORTG + * @arg @ref LL_SBS_EXTI_PORTH + * @arg @ref LL_SBS_EXTI_PORTM + * @arg @ref LL_SBS_EXTI_PORTN + * @arg @ref LL_SBS_EXTI_PORTO + * @arg @ref LL_SBS_EXTI_PORTP + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SBS_EXTI_LINE0 + * @arg @ref LL_SBS_EXTI_LINE1 + * @arg @ref LL_SBS_EXTI_LINE2 + * @arg @ref LL_SBS_EXTI_LINE3 + * @arg @ref LL_SBS_EXTI_LINE4 + * @arg @ref LL_SBS_EXTI_LINE5 + * @arg @ref LL_SBS_EXTI_LINE6 + * @arg @ref LL_SBS_EXTI_LINE7 + * @arg @ref LL_SBS_EXTI_LINE8 + * @arg @ref LL_SBS_EXTI_LINE9 + * @arg @ref LL_SBS_EXTI_LINE10 + * @arg @ref LL_SBS_EXTI_LINE11 + * @arg @ref LL_SBS_EXTI_LINE12 + * @arg @ref LL_SBS_EXTI_LINE13 + * @arg @ref LL_SBS_EXTI_LINE14 + * @arg @ref LL_SBS_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SBS_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(SBS->EXTICR[Line & 0x03U], + SBS_EXTICR1_PC_EXTI0 << (Line >> LL_SBS_REGISTER_PINPOS_SHFT), + Port << (Line >> LL_SBS_REGISTER_PINPOS_SHFT)); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SBS_EXTICR1 EXTI0 LL_SBS_GetEXTISource\n + * SBS_EXTICR1 EXTI1 LL_SBS_GetEXTISource\n + * SBS_EXTICR1 EXTI2 LL_SBS_GetEXTISource\n + * SBS_EXTICR1 EXTI3 LL_SBS_GetEXTISource\n + * SBS_EXTICR2 EXTI4 LL_SBS_GetEXTISource\n + * SBS_EXTICR2 EXTI5 LL_SBS_GetEXTISource\n + * SBS_EXTICR2 EXTI6 LL_SBS_GetEXTISource\n + * SBS_EXTICR2 EXTI7 LL_SBS_GetEXTISource\n + * SBS_EXTICR3 EXTI8 LL_SBS_GetEXTISource\n + * SBS_EXTICR3 EXTI9 LL_SBS_GetEXTISource\n + * SBS_EXTICR3 EXTI10 LL_SBS_GetEXTISource\n + * SBS_EXTICR3 EXTI11 LL_SBS_GetEXTISource\n + * SBS_EXTICR4 EXTI12 LL_SBS_GetEXTISource\n + * SBS_EXTICR4 EXTI13 LL_SBS_GetEXTISource\n + * SBS_EXTICR4 EXTI14 LL_SBS_GetEXTISource\n + * SBS_EXTICR4 EXTI15 LL_SBS_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SBS_EXTI_LINE0 + * @arg @ref LL_SBS_EXTI_LINE1 + * @arg @ref LL_SBS_EXTI_LINE2 + * @arg @ref LL_SBS_EXTI_LINE3 + * @arg @ref LL_SBS_EXTI_LINE4 + * @arg @ref LL_SBS_EXTI_LINE5 + * @arg @ref LL_SBS_EXTI_LINE6 + * @arg @ref LL_SBS_EXTI_LINE7 + * @arg @ref LL_SBS_EXTI_LINE8 + * @arg @ref LL_SBS_EXTI_LINE9 + * @arg @ref LL_SBS_EXTI_LINE10 + * @arg @ref LL_SBS_EXTI_LINE11 + * @arg @ref LL_SBS_EXTI_LINE12 + * @arg @ref LL_SBS_EXTI_LINE13 + * @arg @ref LL_SBS_EXTI_LINE14 + * @arg @ref LL_SBS_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SBS_EXTI_PORTA + * @arg @ref LL_SBS_EXTI_PORTB + * @arg @ref LL_SBS_EXTI_PORTC + * @arg @ref LL_SBS_EXTI_PORTD + * @arg @ref LL_SBS_EXTI_PORTE + * @arg @ref LL_SBS_EXTI_PORTF + * @arg @ref LL_SBS_EXTI_PORTG + * @arg @ref LL_SBS_EXTI_PORTH + * @arg @ref LL_SBS_EXTI_PORTM + * @arg @ref LL_SBS_EXTI_PORTN + * @arg @ref LL_SBS_EXTI_PORTO + * @arg @ref LL_SBS_EXTI_PORTP + */ +__STATIC_INLINE uint32_t LL_SBS_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(SBS->EXTICR[Line & 0x03U], + (SBS_EXTICR1_PC_EXTI0 << (Line >> LL_SBS_REGISTER_PINPOS_SHFT))) >> (Line >> LL_SBS_REGISTER_PINPOS_SHFT)); +} + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415) + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during sleep mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during sleep mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Indicate if the Debug Module during sleep mode is enabled + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_IsEnabledDBGSleepMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledDBGSleepMode(void) +{ + return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP) == (DBGMCU_CR_DBG_SLEEP)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Indicate if the Debug Module during STOP mode is enabled + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_IsEnabledDBGStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledDBGStopMode(void) +{ + return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP) == (DBGMCU_CR_DBG_STOP)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Indicate if the Debug Module during STANDBY mode is enabled + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_IsEnabledDBGStandbyMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledDBGStandbyMode(void) +{ + return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY) == (DBGMCU_CR_DBG_STANDBY)) ? 1UL : 0UL); +} + +/** + * @brief Configure the debug credentials reset type + * @rmtoll DBGMCU_CR DCRT LL_DBGMCU_SetDbgCredentialResetType + * @param Type This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_DCRT_SYSTEM + * @arg @ref LL_DBGMCU_DCRT_POWER + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetDbgCredentialResetType(uint32_t Type) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DCRT, Type); +} + +/** + * @brief Get the selected debug credentials reset type + * @rmtoll DBGMCU_CR DCRT LL_DBGMCU_GetDbgCredentialResetType + * @retval Returned value is the debug credentials reset type: + * @arg @ref LL_DBGMCU_DCRT_SYSTEM + * @arg @ref LL_DBGMCU_DCRT_POWER + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDbgCredentialResetType(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DCRT)); +} + +/** + * @brief Enable the clock for Trace port + * @rmtoll DBGMCU_CR TRACECLKEN LL_DBGMCU_EnableTraceClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACECLKEN); +} + +/** + * @brief Disable the clock for Trace port + * @rmtoll DBGMCU_CR TRACECLKEN LL_DBGMCU_DisableTraceClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACECLKEN); +} + +/** + * @brief Indicate if the clock for Trace port is enabled + * @rmtoll DBGMCU_CR TRACE_EN LL_DBGMCU_IsEnabledTraceClock + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void) +{ + return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACECLKEN) == (DBGMCU_CR_TRACECLKEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the clock for debug port + * @rmtoll DBGMCU_CR D1DBGCKEN LL_DBGMCU_EnableDebugClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDebugClock(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBGCKEN); +} + +/** + * @brief Disable the clock for debug port + * @rmtoll DBGMCU_CR D1DBGCKEN LL_DBGMCU_DisableDebugClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDebugClock(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBGCKEN); +} + +/** + * @brief Indicate if the clock for debug port is enabled + * @rmtoll DBGMCU_CR D1DBGCKEN LL_DBGMCU_IsEnabledDebugClock + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledDebugClock(void) +{ + return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_DBGCKEN) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Enable the external trigger output + * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_EnableTriggerOutput + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableTriggerOutput(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_TRGOEN); +} + +/** + * @brief Disable the external trigger output + * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_DisableTriggerOutput + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableTriggerOutput(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRGOEN); +} + +/** + * @brief Indicate if the external trigger output is enabled + * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_IsEnabledTriggerOutput + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTriggerOutput(void) +{ + return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRGOEN) != 0UL) ? 1UL : 0UL); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZR, Periphs); +} + +/** + * @brief UnFreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1FZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZR, Periphs); +} + +/** + * @brief Freeze APB4 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB4FZR DBG_xxxx_STOP LL_DBGMCU_APB4_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB4FZR, Periphs); +} + +/** + * @brief UnFreeze APB4 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB4FZR DBG_xxxx_STOP LL_DBGMCU_APB4_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB4FZR, Periphs); +} + +/** + * @brief freeze APB2 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB2FZR DBG_xxxx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZR, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZR, Periphs); +} + +/** + * @brief freeze AHB5 peripherals (group1 peripherals) + * @rmtoll DBGMCU_AHB5FZR DBG_xxxx_STOP LL_DBGMCU_AHB5_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA0_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA2_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA3_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA4_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA5_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA6_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA7_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA8_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA9_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA10_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA11_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA12_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA13_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA14_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA15_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB5_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->AHB5FZR, Periphs); +} + +/** + * @brief Unfreeze AHB5 peripherals (group1 peripherals) + * @rmtoll DBGMCU_AHB5FZR DBG_xxxx_STOP LL_DBGMCU_AHB5_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA0_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA2_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA3_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA4_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA5_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA6_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA7_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA8_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA9_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA10_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA11_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA12_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA13_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA14_STOP + * @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA15_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB5_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->AHB5FZR, Periphs); +} + +/** + * @brief freeze AHB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_AHB1FZR DBG_xxxx_STOP LL_DBGMCU_AHB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->AHB1FZR, Periphs); +} + +/** + * @brief Unfreeze AHB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_AHB1FZR DBG_xxxx_STOP LL_DBGMCU_AHB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP + * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->AHB1FZR, Periphs); +} + +/** + * @} + */ + +#if defined(VREFBUF) +/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF + * @{ + */ + +/** + * @brief Enable Internal voltage reference + * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_Enable(void) +{ + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +/** + * @brief Disable Internal voltage reference + * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_Disable(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +/** + * @brief Enable high impedance (VREF+pin is high impedance) + * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void) +{ + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); +} + +/** + * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output) + * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); +} + +/** + * @brief Set the Voltage reference scale + * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling + * @param Scale This parameter can be one of the following values: + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3 + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale) +{ + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale); +} + +/** + * @brief Get the Voltage reference scale + * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2 + * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3 + */ +__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS)); +} + +/** + * @brief Check if Voltage reference buffer is ready + * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void) +{ + return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == VREFBUF_CSR_VRR) ? 1UL : 0UL); +} + +/** + * @brief Get the trimming code for VREFBUF calibration + * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming + * @retval Between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void) +{ + return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM)); +} + +/** + * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage) + * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming + * @param Value Between 0 and 0x3F + * @retval None + */ +__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) +{ + WRITE_REG(VREFBUF->CCR, Value); +} + +/** + * @} + */ +#endif /* VREFBUF */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Unlock the Flash + * @rmtoll FLASH_KEYR CUKEY LL_FLASH_Unlock + * @retval None + */ +__STATIC_INLINE void LL_FLASH_Unlock(void) +{ + /* Unlock Flash */ + FLASH->KEYR = 0x45670123U; + FLASH->KEYR = 0xCDEF89ABU; +} + +/** + * @brief Lock the Flash + * @rmtoll FLASH_CR LOCK LL_FLASH_Lock + * @retval None + */ +__STATIC_INLINE void LL_FLASH_Lock(void) +{ + /* Lock Flash */ + SET_BIT(FLASH->CR, FLASH_CR_LOCK); +} + +/** + * @brief Check if Flash is locked + * @rmtoll FLASH_CR LOCK LL_FLASH_IsLocked + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsLocked(void) +{ + return ((READ_BIT(FLASH->CR, FLASH_CR_LOCK) == FLASH_CR_LOCK) ? 1UL : 0UL); +} + +/** + * @brief Unlock the Option Bytes update + * @rmtoll FLASH_OPTKEYR OCUKEY LL_FLASH_OptionBytes_Unlock + * @retval None + */ +__STATIC_INLINE void LL_FLASH_OptionBytes_Unlock(void) +{ + /* Unlock Option Bytes */ + FLASH->OPTKEYR = 0x08192A3BU; + FLASH->OPTKEYR = 0x4C5D6E7FU; +} + +/** + * @brief Lock the Option Bytes update + * @rmtoll FLASH_OPTCR OPTLOCK LL_FLASH_OptionBytes_Lock + * @retval None + */ +__STATIC_INLINE void LL_FLASH_OptionBytes_Lock(void) +{ + /* Lock option bytes */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK); +} + +/** + * @brief Check if Option Bytes update is locked + * @rmtoll FLASH_OPTCR OPTLOCK LL_FLASH_OptionBytes_IsLocked + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_OptionBytes_IsLocked(void) +{ + return ((READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) == FLASH_OPTCR_OPTLOCK) ? 1UL : 0UL); +} + +/** + * @brief Enable Option Bytes programming + * @rmtoll FLASH_OPTCR PG_OPT LL_FLASH_OptionBytes_EnableProg + * @retval None + */ +__STATIC_INLINE void LL_FLASH_OptionBytes_EnableProg(void) +{ + /* Set PG_OPT Bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT); +} + +/** + * @brief Disable Option Bytes programming + * @rmtoll FLASH_OPTCR PG_OPT LL_FLASH_OptionBytes_DisableProg + * @retval None + */ +__STATIC_INLINE void LL_FLASH_OptionBytes_DisableProg(void) +{ + /* Clear PG_OPT Bit */ + CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT); +} + +/** + * @brief Check if Option Bytes programming is enabled + * @rmtoll FLASH_OPTCR PG_OPT LL_FLASH_OptionBytes_IsEnabledProg + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_OptionBytes_IsEnabledProg(void) +{ + return ((READ_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT) == FLASH_OPTCR_PG_OPT) ? 1UL : 0UL); +} + +/** + * @brief Check if operation pending + * @rmtoll FLASH_SR QW LL_FLASH_IsPendingOperation + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPendingOperation(void) +{ + return ((READ_BIT(FLASH->SR, FLASH_SR_QW) == FLASH_SR_QW) ? 1UL : 0UL); +} + +/** + * @brief Enable the I2C in Flash User Option bytes + * @rmtoll FLASH_OBW2SR I2C_NI3C LL_FLASH_OptionBytes_EnableI2C + * @retval None + */ +__STATIC_INLINE void LL_FLASH_OptionBytes_EnableI2C(void) +{ + /* Set I2C_N3C Bit */ + SET_BIT(FLASH->OBW2SRP, FLASH_OBW2SRP_I2C_NI3C); +} + +/** + * @brief Enable the I3C in Flash User Option bytes + * @rmtoll FLASH_OBW2SR I2C_NI3C LL_FLASH_OptionBytes_EnableI3C + * @retval None + */ +__STATIC_INLINE void LL_FLASH_OptionBytes_EnableI3C(void) +{ + /* Clear I2C_N3C Bit */ + CLEAR_BIT(FLASH->OBW2SRP, FLASH_OBW2SRP_I2C_NI3C); +} + +/** + * @brief Check if I2C is enabled in Flash User Option Bytes + * @rmtoll FLASH_OBW2SR I2C_NI3C LL_FLASH_OptionBytes_IsI2CEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_OptionBytes_IsI2CEnabled(void) +{ + return ((READ_BIT(FLASH->OBW2SR, FLASH_OBW2SR_I2C_NI3C) == FLASH_OBW2SR_I2C_NI3C) ? 1UL : 0UL); +} + +/** + * @brief Check if I3C is enabled in Flash User Option Bytes + * @rmtoll FLASH_OBW2SR I2C_NI3C LL_FLASH_OptionBytes_IsI3CEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_OptionBytes_IsI3CEnabled(void) +{ + return ((READ_BIT(FLASH->OBW2SR, FLASH_OBW2SR_I2C_NI3C) == 0U) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SBS) || defined (DBGMCU) || defined (VREFBUF) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_SYSTEM_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_tim.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_tim.h new file mode 100644 index 00000000000..246511979d1 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_tim.h @@ -0,0 +1,6101 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_tim.h + * @author MCD Application Team + * @brief Header file of TIM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7RSxx_LL_TIM_H +#define __STM32H7RSxx_LL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM9) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) + +/** @defgroup TIM_LL TIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Variables TIM Private Variables + * @{ + */ +static const uint8_t OFFSET_TAB_CCMRx[] = +{ + 0x00U, /* 0: TIMx_CH1 */ + 0x00U, /* 1: TIMx_CH1N */ + 0x00U, /* 2: TIMx_CH2 */ + 0x00U, /* 3: TIMx_CH2N */ + 0x04U, /* 4: TIMx_CH3 */ + 0x04U, /* 5: TIMx_CH3N */ + 0x04U, /* 6: TIMx_CH4 */ + 0x04U, /* 7: TIMx_CH4N */ + 0x38U, /* 8: TIMx_CH5 */ + 0x38U /* 9: TIMx_CH6 */ + +}; + +static const uint8_t SHIFT_TAB_OCxx[] = +{ + 0U, /* 0: OC1M, OC1FE, OC1PE */ + 0U, /* 1: - NA */ + 8U, /* 2: OC2M, OC2FE, OC2PE */ + 0U, /* 3: - NA */ + 0U, /* 4: OC3M, OC3FE, OC3PE */ + 0U, /* 5: - NA */ + 8U, /* 6: OC4M, OC4FE, OC4PE */ + 0U, /* 7: - NA */ + 0U, /* 8: OC5M, OC5FE, OC5PE */ + 8U /* 9: OC6M, OC6FE, OC6PE */ +}; + +static const uint8_t SHIFT_TAB_ICxx[] = +{ + 0U, /* 0: CC1S, IC1PSC, IC1F */ + 0U, /* 1: - NA */ + 8U, /* 2: CC2S, IC2PSC, IC2F */ + 0U, /* 3: - NA */ + 0U, /* 4: CC3S, IC3PSC, IC3F */ + 0U, /* 5: - NA */ + 8U, /* 6: CC4S, IC4PSC, IC4F */ + 0U, /* 7: - NA */ + 0U, /* 8: - NA */ + 0U /* 9: - NA */ +}; + +static const uint8_t SHIFT_TAB_CCxP[] = +{ + 0U, /* 0: CC1P */ + 2U, /* 1: CC1NP */ + 4U, /* 2: CC2P */ + 6U, /* 3: CC2NP */ + 8U, /* 4: CC3P */ + 10U, /* 5: CC3NP */ + 12U, /* 6: CC4P */ + 14U, /* 7: CC4NP */ + 16U, /* 8: CC5P */ + 20U /* 9: CC6P */ +}; + +static const uint8_t SHIFT_TAB_OISx[] = +{ + 0U, /* 0: OIS1 */ + 1U, /* 1: OIS1N */ + 2U, /* 2: OIS2 */ + 3U, /* 3: OIS2N */ + 4U, /* 4: OIS3 */ + 5U, /* 5: OIS3N */ + 6U, /* 6: OIS4 */ + 7U, /* 7: OIS4N */ + 8U, /* 8: OIS5 */ + 10U /* 9: OIS6 */ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Constants TIM Private Constants + * @{ + */ + +/* Defines used for the bit position in the register and perform offsets */ +#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) + +/* Generic bit definitions for TIMx_AF1 register */ +#define TIMx_AF1_BKINP TIM_AF1_BKINP /*!< BRK BKIN input polarity */ +#define TIMx_AF1_ETRSEL TIM_AF1_ETRSEL /*!< TIMx ETR source selection */ + + +/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ +#define DT_DELAY_1 ((uint8_t)0x7F) +#define DT_DELAY_2 ((uint8_t)0x3F) +#define DT_DELAY_3 ((uint8_t)0x1F) +#define DT_DELAY_4 ((uint8_t)0x1F) + +/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ +#define DT_RANGE_1 ((uint8_t)0x00) +#define DT_RANGE_2 ((uint8_t)0x80) +#define DT_RANGE_3 ((uint8_t)0xC0) +#define DT_RANGE_4 ((uint8_t)0xE0) + +/** Legacy definitions for compatibility purpose +@cond 0 + */ +/** +@endcond + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Macros TIM Private Macros + * @{ + */ +/** @brief Convert channel id into channel index. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval none + */ +#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U) + +/** @brief Calculate the deadtime sampling period(in ps). + * @param __TIMCLK__ timer input clock frequency (in Hz). + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval none + */ +#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + * @{ + */ + +/** + * @brief TIM Time Base configuration structure definition. + */ +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetPrescaler().*/ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetCounterMode().*/ + + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must + be a number between 0x0000 and 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetAutoReload().*/ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetClockDivision().*/ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetRepetitionCounter().*/ +} LL_TIM_InitTypeDef; + +/** + * @brief TIM Output Compare configuration structure definition. + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the output mode. + This parameter can be a value of @ref TIM_LL_EC_OCMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetMode().*/ + + uint32_t OCState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + LL_TIM_OC_SetCompareCHx (x=1..6).*/ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ +} LL_TIM_OC_InitTypeDef; + +/** + * @brief TIM Input Capture configuration structure definition. + */ + +typedef struct +{ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t ICActiveInput; /*!< Specifies the input. + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ +} LL_TIM_IC_InitTypeDef; + + +/** + * @brief TIM Encoder interface configuration structure definition. + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetEncoderMode().*/ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + +} LL_TIM_ENCODER_InitTypeDef; + +/** + * @brief TIM Hall sensor interface configuration structure definition. + */ +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + Prescaler must be set to get a maximum counter period longer than the + time interval between 2 consecutive changes on the Hall inputs. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of + @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. + A positive pulse (TRGO event) is generated with a programmable delay every time + a change occurs on the Hall inputs. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetCompareCH2().*/ +} LL_TIM_HALLSENSOR_InitTypeDef; + +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR + register has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been + programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. + This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK() + + @note Bidirectional break input is only supported by advanced timers instances. + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK2() + + @note Bidirectional break input is only supported by advanced timers instances. + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ +} LL_TIM_BDTR_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_TIM_ReadReg function. + * @{ + */ +#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ +#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ +#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ +#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ +#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ +#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ +#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ +#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ +#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ +#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ +#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ +#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ +#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ +#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ +#define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */ +#define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */ +#define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */ +#define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable + * @{ + */ +#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ +#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + * @{ + */ +#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ +#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ +#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ +#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ +#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ +#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ +#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ +#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ +#define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */ +#define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */ +#define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */ +#define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + * @{ + */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + * @{ + */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + * @{ + */ +#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */ +#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ +#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ +#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ +#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division + * @{ + */ +#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction + * @{ + */ +#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ +#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source + * @{ + */ +#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ +#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request + * @{ + */ +#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ +#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level + * @{ + */ +#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ +#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CHANNEL Channel + * @{ + */ +#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ +#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ +#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ +#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ +#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ +#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ +#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ +#define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */ +#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ +#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State + * @{ + */ +#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ +#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 +#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 +/** +@endcond + */ + +/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode + * @{ + */ +#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!TIMx_CCRy else active.*/ +#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ +#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in TIM register. + * @param __INSTANCE__ TIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** + * @brief HELPER macro retrieving the UIFCPY flag from the counter value. + * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); + * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied + * to TIMx_CNT register bit 31) + * @param __CNT__ Counter value + * @retval UIF status bit + */ +#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ + (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) + +/** + * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. + * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @param __DT__ deadtime duration (in ns) + * @retval DTG[0:7] + */ +#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + 0U) + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CNTCLK__ counter clock frequency (in Hz) + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required + * output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \ + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \ + (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U) + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer + * output compare active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required + * pulse duration (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro retrieving the ratio of the input capture prescaler + * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); + * @param __ICPSC__ This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval Input capture prescaler ratio (1, 2, 4 or 8) + */ +#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_LL_EF_Time_Base Time Base configuration + * @{ + */ +/** + * @brief Enable timer counter. + * @rmtoll CR1 CEN LL_TIM_EnableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Disable timer counter. + * @rmtoll CR1 CEN LL_TIM_DisableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable update event generation. + * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Disable update event generation. + * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Indicates whether update event generation is enabled. + * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent + * @param TIMx Timer instance + * @retval Inverted state of bit (0 or 1). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); +} + +/** + * @brief Set update event source + * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events + * generate an update interrupt or DMA request if enabled: + * - Counter overflow/underflow + * - Setting the UG bit + * - Update generation through the slave mode controller + * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter + * overflow/underflow generates an update interrupt or DMA request if enabled. + * @rmtoll CR1 URS LL_TIM_SetUpdateSource + * @param TIMx Timer instance + * @param UpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +} + +/** + * @brief Get actual event update source + * @rmtoll CR1 URS LL_TIM_GetUpdateSource + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + */ +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +} + +/** + * @brief Set one pulse mode (one shot v.s. repetitive). + * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode + * @param TIMx Timer instance + * @param OnePulseMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +} + +/** + * @brief Get actual one pulse mode. + * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + */ +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +} + +/** + * @brief Set the timer counter counting mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n + * CR1 CMS LL_TIM_SetCounterMode + * @param TIMx Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +{ + MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); +} + +/** + * @brief Get actual counter mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n + * CR1 CMS LL_TIM_GetCounterMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) +{ + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; +} + +/** + * @brief Enable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Disable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Indicates whether auto-reload (ARR) preload is enabled. + * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators + * (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_SetClockDivision + * @param TIMx Timer instance + * @param ClockDivision This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +} + +/** + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time + * generators (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_GetClockDivision + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +} + +/** + * @brief Set the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note If dithering is activated, pay attention to the Counter value interpretation + * @rmtoll CNT CNT LL_TIM_SetCounter + * @param TIMx Timer instance + * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + WRITE_REG(TIMx->CNT, Counter); +} + +/** + * @brief Get the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note If dithering is activated, pay attention to the Counter value interpretation + * @rmtoll CNT CNT LL_TIM_GetCounter + * @param TIMx Timer instance + * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CNT)); +} + +/** + * @brief Get the current direction of the counter + * @rmtoll CR1 DIR LL_TIM_GetDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERDIRECTION_UP + * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +} + +/** + * @brief Set the prescaler value. + * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). + * @note The prescaler can be changed on the fly as this control register is buffered. The new + * prescaler ratio is taken into account at the next update event. + * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter + * @rmtoll PSC PSC LL_TIM_SetPrescaler + * @param TIMx Timer instance + * @param Prescaler between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +{ + WRITE_REG(TIMx->PSC, Prescaler); +} + +/** + * @brief Get the prescaler value. + * @rmtoll PSC PSC LL_TIM_GetPrescaler + * @param TIMx Timer instance + * @retval Prescaler value between Min_Data=0 and Max_Data=65535 + */ +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->PSC)); +} + +/** + * @brief Set the auto-reload value. + * @note The counter is blocked while the auto-reload value is null. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter + * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload + * parameter. + * @rmtoll ARR ARR LL_TIM_SetAutoReload + * @param TIMx Timer instance + * @param AutoReload between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +{ + WRITE_REG(TIMx->ARR, AutoReload); +} + +/** + * @brief Get the auto-reload value. + * @rmtoll ARR ARR LL_TIM_GetAutoReload + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note If dithering is activated, pay attention to the returned value interpretation + * @param TIMx Timer instance + * @retval Auto-reload value + */ +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->ARR)); +} + +/** + * @brief Set the repetition counter value. + * @note For advanced timer instances RepetitionCounter can be up to 65535. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_SetRepetitionCounter + * @param TIMx Timer instance + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +{ + WRITE_REG(TIMx->RCR, RepetitionCounter); +} + +/** + * @brief Get the repetition counter value. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_GetRepetitionCounter + * @param TIMx Timer instance + * @retval Repetition counter value + */ +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->RCR)); +} + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) copy is set. + * @param Counter Counter value + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) +{ + return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +} + +/** + * @brief Enable dithering. + * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides dithering. + * @rmtoll CR1 DITHEN LL_TIM_EnableDithering + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_DITHEN); +} + +/** + * @brief Disable dithering. + * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides dithering. + * @rmtoll CR1 DITHEN LL_TIM_DisableDithering + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN); +} + +/** + * @brief Indicates whether dithering is activated. + * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides dithering. + * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration + * @{ + */ +/** + * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, + * they are updated only when a commutation event (COM) occurs. + * @note Only on channels that have a complementary output. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + +/** + * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate + * @param TIMx Timer instance + * @param CCUpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +} + +/** + * @brief Set the trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger + * @param TIMx Timer instance + * @param DMAReqTrigger This parameter can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +} + +/** + * @brief Get actual trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +} + +/** + * @brief Set the lock level to freeze the + * configuration of several capture/compare parameters. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * the lock mechanism is supported by a timer instance. + * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel + * @param TIMx Timer instance + * @param LockLevel This parameter can be one of the following values: + * @arg @ref LL_TIM_LOCKLEVEL_OFF + * @arg @ref LL_TIM_LOCKLEVEL_1 + * @arg @ref LL_TIM_LOCKLEVEL_2 + * @arg @ref LL_TIM_LOCKLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +} + +/** + * @brief Enable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n + * CCER CC1NE LL_TIM_CC_EnableChannel\n + * CCER CC2E LL_TIM_CC_EnableChannel\n + * CCER CC2NE LL_TIM_CC_EnableChannel\n + * CCER CC3E LL_TIM_CC_EnableChannel\n + * CCER CC3NE LL_TIM_CC_EnableChannel\n + * CCER CC4E LL_TIM_CC_EnableChannel\n + * CCER CC4NE LL_TIM_CC_EnableChannel\n + * CCER CC5E LL_TIM_CC_EnableChannel\n + * CCER CC6E LL_TIM_CC_EnableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + SET_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Disable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n + * CCER CC1NE LL_TIM_CC_DisableChannel\n + * CCER CC2E LL_TIM_CC_DisableChannel\n + * CCER CC2NE LL_TIM_CC_DisableChannel\n + * CCER CC3E LL_TIM_CC_DisableChannel\n + * CCER CC3NE LL_TIM_CC_DisableChannel\n + * CCER CC4E LL_TIM_CC_DisableChannel\n + * CCER CC4NE LL_TIM_CC_DisableChannel\n + * CCER CC5E LL_TIM_CC_DisableChannel\n + * CCER CC6E LL_TIM_CC_DisableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + CLEAR_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Indicate whether channel(s) is(are) enabled. + * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n + * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC2E LL_TIM_CC_IsEnabledChannel\n + * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC3E LL_TIM_CC_IsEnabledChannel\n + * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC4E LL_TIM_CC_IsEnabledChannel\n + * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC5E LL_TIM_CC_IsEnabledChannel\n + * CCER CC6E LL_TIM_CC_IsEnabledChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) +{ + return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration + * @{ + */ +/** + * @brief Configure an output channel. + * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n + * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n + * CCER CC1P LL_TIM_OC_ConfigOutput\n + * CCER CC2P LL_TIM_OC_ConfigOutput\n + * CCER CC3P LL_TIM_OC_ConfigOutput\n + * CCER CC4P LL_TIM_OC_ConfigOutput\n + * CCER CC5P LL_TIM_OC_ConfigOutput\n + * CCER CC6P LL_TIM_OC_ConfigOutput\n + * CR2 OIS1 LL_TIM_OC_ConfigOutput\n + * CR2 OIS2 LL_TIM_OC_ConfigOutput\n + * CR2 OIS3 LL_TIM_OC_ConfigOutput\n + * CR2 OIS4 LL_TIM_OC_ConfigOutput\n + * CR2 OIS5 LL_TIM_OC_ConfigOutput\n + * CR2 OIS6 LL_TIM_OC_ConfigOutput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW + * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), + (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), + (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Define the behavior of the output reference signal OCxREF from which + * OCx and OCxN (when relevant) are derived. + * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n + * CCMR1 OC2M LL_TIM_OC_SetMode\n + * CCMR2 OC3M LL_TIM_OC_SetMode\n + * CCMR2 OC4M LL_TIM_OC_SetMode\n + * CCMR3 OC5M LL_TIM_OC_SetMode\n + * CCMR3 OC6M LL_TIM_OC_SetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only) + * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only) + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Get the output compare mode of an output channel. + * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n + * CCMR1 OC2M LL_TIM_OC_GetMode\n + * CCMR2 OC3M LL_TIM_OC_GetMode\n + * CCMR2 OC4M LL_TIM_OC_GetMode\n + * CCMR3 OC5M LL_TIM_OC_GetMode\n + * CCMR3 OC6M LL_TIM_OC_GetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only) + * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n + * CCER CC1NP LL_TIM_OC_SetPolarity\n + * CCER CC2P LL_TIM_OC_SetPolarity\n + * CCER CC2NP LL_TIM_OC_SetPolarity\n + * CCER CC3P LL_TIM_OC_SetPolarity\n + * CCER CC3NP LL_TIM_OC_SetPolarity\n + * CCER CC4P LL_TIM_OC_SetPolarity\n + * CCER CC4NP LL_TIM_OC_SetPolarity\n + * CCER CC5P LL_TIM_OC_SetPolarity\n + * CCER CC6P LL_TIM_OC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n + * CCER CC1NP LL_TIM_OC_GetPolarity\n + * CCER CC2P LL_TIM_OC_GetPolarity\n + * CCER CC2NP LL_TIM_OC_GetPolarity\n + * CCER CC3P LL_TIM_OC_GetPolarity\n + * CCER CC3NP LL_TIM_OC_GetPolarity\n + * CCER CC4P LL_TIM_OC_GetPolarity\n + * CCER CC4NP LL_TIM_OC_GetPolarity\n + * CCER CC5P LL_TIM_OC_GetPolarity\n + * CCER CC6P LL_TIM_OC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the IDLE state of an output channel + * @note This function is significant only for the timer instances + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) + * can be used to check whether or not a timer instance provides + * a break input. + * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS2 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS3 LL_TIM_OC_SetIdleState\n + * CR2 OIS3N LL_TIM_OC_SetIdleState\n + * CR2 OIS4 LL_TIM_OC_SetIdleState\n + * CR2 OIS4N LL_TIM_OC_SetIdleState\n + * CR2 OIS5 LL_TIM_OC_SetIdleState\n + * CR2 OIS6 LL_TIM_OC_SetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param IdleState This parameter can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Get the IDLE state of an output channel + * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS2 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS3 LL_TIM_OC_GetIdleState\n + * CR2 OIS3N LL_TIM_OC_GetIdleState\n + * CR2 OIS4 LL_TIM_OC_GetIdleState\n + * CR2 OIS4N LL_TIM_OC_GetIdleState\n + * CR2 OIS5 LL_TIM_OC_GetIdleState\n + * CR2 OIS6 LL_TIM_OC_GetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Enable fast mode for the output channel. + * @note Acts only if the channel is configured in PWM1 or PWM2 mode. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n + * CCMR1 OC2FE LL_TIM_OC_EnableFast\n + * CCMR2 OC3FE LL_TIM_OC_EnableFast\n + * CCMR2 OC4FE LL_TIM_OC_EnableFast\n + * CCMR3 OC5FE LL_TIM_OC_EnableFast\n + * CCMR3 OC6FE LL_TIM_OC_EnableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Disable fast mode for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n + * CCMR1 OC2FE LL_TIM_OC_DisableFast\n + * CCMR2 OC3FE LL_TIM_OC_DisableFast\n + * CCMR2 OC4FE LL_TIM_OC_DisableFast\n + * CCMR3 OC5FE LL_TIM_OC_DisableFast\n + * CCMR3 OC6FE LL_TIM_OC_DisableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Indicates whether fast mode is enabled for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n + * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n + * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC6PE LL_TIM_OC_EnablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n + * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC6PE LL_TIM_OC_DisablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n + * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n + * CCMR1 OC2CE LL_TIM_OC_EnableClear\n + * CCMR2 OC3CE LL_TIM_OC_EnableClear\n + * CCMR2 OC4CE LL_TIM_OC_EnableClear\n + * CCMR3 OC5CE LL_TIM_OC_EnableClear\n + * CCMR3 OC6CE LL_TIM_OC_EnableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable clearing the output channel on an external event. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n + * CCMR1 OC2CE LL_TIM_OC_DisableClear\n + * CCMR2 OC3CE LL_TIM_OC_DisableClear\n + * CCMR2 OC4CE LL_TIM_OC_DisableClear\n + * CCMR3 OC5CE LL_TIM_OC_DisableClear\n + * CCMR3 OC6CE LL_TIM_OC_DisableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates clearing the output channel on an external event is enabled for the output channel. + * @note This function enables clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n + * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +} + +/** + * @brief Set compare value for output channel 1 (TIMx_CCR1). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR1, CompareValue); +} + +/** + * @brief Set compare value for output channel 2 (TIMx_CCR2). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR2, CompareValue); +} + +/** + * @brief Set compare value for output channel 3 (TIMx_CCR3). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR3, CompareValue); +} + +/** + * @brief Set compare value for output channel 4 (TIMx_CCR4). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR4, CompareValue); +} + +/** + * @brief Set compare value for output channel 5 (TIMx_CCR5). + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); +} + +/** + * @brief Set compare value for output channel 6 (TIMx_CCR6). + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR6, CompareValue); +} + +/** + * @brief Get compare value (TIMx_CCR1) set for output channel 1. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get compare value (TIMx_CCR2) set for output channel 2. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get compare value (TIMx_CCR3) set for output channel 3. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel 3 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get compare value (TIMx_CCR4) set for output channel 4. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @brief Get compare value (TIMx_CCR5) set for output channel 5. + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); +} + +/** + * @brief Get compare value (TIMx_CCR6) set for output channel 6. + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR6)); +} + +/** + * @brief Select on which reference signal the OC5REF is combined to. + * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the combined 3-phase PWM mode. + * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels + * @param TIMx Timer instance + * @param GroupCH5 This parameter can be a combination of the following values: + * @arg @ref LL_TIM_GROUPCH5_NONE + * @arg @ref LL_TIM_GROUPCH5_OC1REFC + * @arg @ref LL_TIM_GROUPCH5_OC2REFC + * @arg @ref LL_TIM_GROUPCH5_OC3REFC + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) +{ + MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); +} + +/** + * @brief Set the pulse on compare pulse width prescaler. + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler + * @param TIMx Timer instance + * @param PulseWidthPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_PWPRSC_X1 + * @arg @ref LL_TIM_PWPRSC_X2 + * @arg @ref LL_TIM_PWPRSC_X4 + * @arg @ref LL_TIM_PWPRSC_X8 + * @arg @ref LL_TIM_PWPRSC_X16 + * @arg @ref LL_TIM_PWPRSC_X32 + * @arg @ref LL_TIM_PWPRSC_X64 + * @arg @ref LL_TIM_PWPRSC_X128 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler); +} + +/** + * @brief Get the pulse on compare pulse width prescaler. + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_PWPRSC_X1 + * @arg @ref LL_TIM_PWPRSC_X2 + * @arg @ref LL_TIM_PWPRSC_X4 + * @arg @ref LL_TIM_PWPRSC_X8 + * @arg @ref LL_TIM_PWPRSC_X16 + * @arg @ref LL_TIM_PWPRSC_X32 + * @arg @ref LL_TIM_PWPRSC_X64 + * @arg @ref LL_TIM_PWPRSC_X128 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC)); +} + +/** + * @brief Set the pulse on compare pulse width duration. + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth + * @param TIMx Timer instance + * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos); +} + +/** + * @brief Get the pulse on compare pulse width duration. + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth + * @param TIMx Timer instance + * @retval Returned value can be between Min_Data=0 and Max_Data=255: + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration + * @{ + */ +/** + * @brief Configure input channel. + * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n + * CCMR1 IC1PSC LL_TIM_IC_Config\n + * CCMR1 IC1F LL_TIM_IC_Config\n + * CCMR1 CC2S LL_TIM_IC_Config\n + * CCMR1 IC2PSC LL_TIM_IC_Config\n + * CCMR1 IC2F LL_TIM_IC_Config\n + * CCMR2 CC3S LL_TIM_IC_Config\n + * CCMR2 IC3PSC LL_TIM_IC_Config\n + * CCMR2 IC3F LL_TIM_IC_Config\n + * CCMR2 CC4S LL_TIM_IC_Config\n + * CCMR2 IC4PSC LL_TIM_IC_Config\n + * CCMR2 IC4F LL_TIM_IC_Config\n + * CCER CC1P LL_TIM_IC_Config\n + * CCER CC1NP LL_TIM_IC_Config\n + * CCER CC2P LL_TIM_IC_Config\n + * CCER CC2NP LL_TIM_IC_Config\n + * CCER CC3P LL_TIM_IC_Config\n + * CCER CC3NP LL_TIM_IC_Config\n + * CCER CC4P LL_TIM_IC_Config\n + * CCER CC4NP LL_TIM_IC_Config + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC + * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 + * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << SHIFT_TAB_ICxx[iChannel]); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_SetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICActiveInput This parameter can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_GetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the prescaler of input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current prescaler value acting on an input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n + * CCMR1 IC2F LL_TIM_IC_SetFilter\n + * CCMR2 IC3F LL_TIM_IC_SetFilter\n + * CCMR2 IC4F LL_TIM_IC_SetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n + * CCMR1 IC2F LL_TIM_IC_GetFilter\n + * CCMR2 IC3F LL_TIM_IC_GetFilter\n + * CCMR2 IC4F LL_TIM_IC_GetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n + * CCER CC1NP LL_TIM_IC_SetPolarity\n + * CCER CC2P LL_TIM_IC_SetPolarity\n + * CCER CC2NP LL_TIM_IC_SetPolarity\n + * CCER CC3P LL_TIM_IC_SetPolarity\n + * CCER CC3NP LL_TIM_IC_SetPolarity\n + * CCER CC4P LL_TIM_IC_SetPolarity\n + * CCER CC4NP LL_TIM_IC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + ICPolarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the current input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n + * CCER CC1NP LL_TIM_IC_GetPolarity\n + * CCER CC2P LL_TIM_IC_GetPolarity\n + * CCER CC2NP LL_TIM_IC_GetPolarity\n + * CCER CC3P LL_TIM_IC_GetPolarity\n + * CCER CC3NP LL_TIM_IC_GetPolarity\n + * CCER CC4P LL_TIM_IC_GetPolarity\n + * CCER CC4NP LL_TIM_IC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> + SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); +} + +/** + * @brief Get captured value for input channel 1. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * input channel 1 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * input channel 2 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get captured value for input channel 3. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * input channel 3 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get captured value for input channel 4. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * input channel 4 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection + * @{ + */ +/** + * @brief Enable external clock mode 2. + * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_EnableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Disable external clock mode 2. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_DisableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Indicate whether external clock mode 2 is enabled. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); +} + +/** + * @brief Set the clock source of the counter clock. + * @note when selected clock source is external clock mode 1, the timer input + * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() + * function. This timer input must be configured by calling + * the @ref LL_TIM_IC_Config() function. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode1. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR SMS LL_TIM_SetClockSource\n + * SMCR ECE LL_TIM_SetClockSource + * @param TIMx Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +} + +/** + * @brief Set the encoder interface mode. + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the encoder mode. + * @rmtoll SMCR SMS LL_TIM_SetEncoderMode + * @param TIMx Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 + * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 + * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 + * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 + * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 + * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 + * @arg @ref LL_TIM_ENCODERMODE_X1_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X1_TI2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration + * @{ + */ +/** + * @brief Set the trigger output (TRGO) used for timer synchronization . + * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can operate as a master timer. + * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput + * @param TIMx Timer instance + * @param TimerSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO_RESET + * @arg @ref LL_TIM_TRGO_ENABLE + * @arg @ref LL_TIM_TRGO_UPDATE + * @arg @ref LL_TIM_TRGO_CC1IF + * @arg @ref LL_TIM_TRGO_OC1REF + * @arg @ref LL_TIM_TRGO_OC2REF + * @arg @ref LL_TIM_TRGO_OC3REF + * @arg @ref LL_TIM_TRGO_OC4REF + * @arg @ref LL_TIM_TRGO_ENCODERCLK + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +} + +/** + * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . + * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can be used for ADC synchronization. + * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 + * @param TIMx Timer Instance + * @param ADCSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO2_RESET + * @arg @ref LL_TIM_TRGO2_ENABLE + * @arg @ref LL_TIM_TRGO2_UPDATE + * @arg @ref LL_TIM_TRGO2_CC1F + * @arg @ref LL_TIM_TRGO2_OC1 + * @arg @ref LL_TIM_TRGO2_OC2 + * @arg @ref LL_TIM_TRGO2_OC3 + * @arg @ref LL_TIM_TRGO2_OC4 + * @arg @ref LL_TIM_TRGO2_OC5 + * @arg @ref LL_TIM_TRGO2_OC6 + * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); +} + +/** + * @brief Set the synchronization mode of a slave timer. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR SMS LL_TIM_SetSlaveMode + * @param TIMx Timer instance + * @param SlaveMode This parameter can be one of the following values: + * @arg @ref LL_TIM_SLAVEMODE_DISABLED + * @arg @ref LL_TIM_SLAVEMODE_RESET + * @arg @ref LL_TIM_SLAVEMODE_GATED + * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER + * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +} + +/** + * @brief Set the selects the trigger input to be used to synchronize the counter. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR TS LL_TIM_SetTriggerInput + * @param TIMx Timer instance + * @param TriggerInput This parameter can be one of the following values: + * @arg @ref LL_TIM_TS_ITR0 + * @arg @ref LL_TIM_TS_ITR1 + * @arg @ref LL_TIM_TS_ITR2 + * @arg @ref LL_TIM_TS_ITR3 + * @arg @ref LL_TIM_TS_ITR4 + * @arg @ref LL_TIM_TS_ITR5 + * @arg @ref LL_TIM_TS_ITR6 + * @arg @ref LL_TIM_TS_ITR7 + * @arg @ref LL_TIM_TS_ITR8 + * @arg @ref LL_TIM_TS_ITR9 + * @arg @ref LL_TIM_TS_ITR10 + * @arg @ref LL_TIM_TS_ITR11 + * @arg @ref LL_TIM_TS_ITR12 + * @arg @ref LL_TIM_TS_ITR13 + * @arg @ref LL_TIM_TS_ITR14 + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +} + +/** + * @brief Enable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Disable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Indicates whether the Master/Slave mode is enabled. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); +} + +/** + * @brief Configure the external trigger (ETR) input. + * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an external trigger input. + * @rmtoll SMCR ETP LL_TIM_ConfigETR\n + * SMCR ETPS LL_TIM_ConfigETR\n + * SMCR ETF LL_TIM_ConfigETR + * @param TIMx Timer instance + * @param ETRPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED + * @arg @ref LL_TIM_ETR_POLARITY_INVERTED + * @param ETRPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 + * @param ETRFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_FILTER_FDIV1 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, + uint32_t ETRFilter) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); +} + +/** + * @brief Select the external trigger (ETR) input source. + * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports ETR source selection. + * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource + * @param TIMx Timer instance + * @param ETRSource This parameter can be one of the following values: + * + * For TIM1, the parameter is one of the following values: + * + * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 + * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 + * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 + * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1 + * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2 + * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3 + * + * For TIM2, the parameter is one of the following values: + * + * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM2_ETRSOURCE_DCMIPP_HSYNC + * @arg @ref LL_TIM_TIM2_ETRSOURCE_LTDC_HSYNC + * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSA + * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSB + * @arg @ref LL_TIM_TIM2_ETRSOURCE_GFXTIM_TE + * @arg @ref LL_TIM_TIM2_ETRSOURCE_DCMIPP_VSYNC + * @arg @ref LL_TIM_TIM2_ETRSOURCE_LTDC_VSYNC + * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR + * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR + * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR + * @arg @ref LL_TIM_TIM2_ETRSOURCE_ETH_PPS + * + * For TIM3, the parameter is one of the following values: + * + * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM3_ETRSOURCE_DCMIPP_HSYNC + * @arg @ref LL_TIM_TIM3_ETRSOURCE_LTDC_HSYNC + * @arg @ref LL_TIM_TIM3_ETRSOURCE_GFXTIM_TE + * @arg @ref LL_TIM_TIM3_ETRSOURCE_DCMIPP_VSYNC + * @arg @ref LL_TIM_TIM3_ETRSOURCE_LTDC_VSYNC + * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR + * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR + * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM5_ETR + * @arg @ref LL_TIM_TIM3_ETRSOURCE_ETH_PPS + * + * For TIM4, the parameter is one of the following values: + * + * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM4_ETRSOURCE_DCMIPP_HSYNC + * @arg @ref LL_TIM_TIM4_ETRSOURCE_LTDC_HSYNC + * @arg @ref LL_TIM_TIM4_ETRSOURCE_GFXTIM_TE + * @arg @ref LL_TIM_TIM4_ETRSOURCE_DCMIPP_VSYNC + * @arg @ref LL_TIM_TIM4_ETRSOURCE_LTDC_VSYNC + * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM2_ETR + * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR + * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR + * + * For TIM5, the parameter is one of the following values: + * + * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSA + * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSB + * @arg @ref LL_TIM_TIM5_ETRSOURCE_DCMIPP_HSYNC + * @arg @ref LL_TIM_TIM5_ETRSOURCE_LTDC_HSYNC + * @arg @ref LL_TIM_TIM5_ETRSOURCE_GFXTIM_TE + * @arg @ref LL_TIM_TIM5_ETRSOURCE_DCMIPP_VSYNC + * @arg @ref LL_TIM_TIM5_ETRSOURCE_LTDC_VSYNC + * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR + * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR + * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM4_ETR + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) +{ + MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource); +} + +/** + * @brief Enable SMS preload. + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE); +} + +/** + * @brief Disable SMS preload. + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE); +} + +/** + * @brief Indicate whether SMS preload is enabled. + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the preload source of SMS. + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n + * @param TIMx Timer instance + * @param PreloadSource This parameter can be one of the following values: + * @arg @ref LL_TIM_SMSPS_TIMUPDATE + * @arg @ref LL_TIM_SMSPS_INDEX + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource); +} + +/** + * @brief Get the preload source of SMS. + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_SMSPS_TIMUPDATE + * @arg @ref LL_TIM_SMSPS_INDEX + */ +__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Break_Function Break function configuration + * @{ + */ +/** + * @brief Enable the break function. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKE LL_TIM_EnableBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +{ + __IO uint32_t tmpreg; + SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Disable the break function. + * @rmtoll BDTR BKE LL_TIM_DisableBRK + * @param TIMx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Configure the break input. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * a timer instance is an advanced-control timer. + * @note In bidirectional mode (BKBID bit set), the Break input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, BreakAFMode must be set to + * LL_TIM_BREAK_AFMODE_INPUT. + * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n + * BDTR BKF LL_TIM_ConfigBRK\n + * BDTR BKBID LL_TIM_ConfigBRK + * @param TIMx Timer instance + * @param BreakPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @param BreakFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 + * @param BreakAFMode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, + uint32_t BreakAFMode) +{ + __IO uint32_t tmpreg; + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode); + /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Disarm the break input (when it operates in bidirectional mode). + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); +} + +/** + * @brief Enable the break 2 function. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) +{ + __IO uint32_t tmpreg; + SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Disable the break 2 function. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Configure the break 2 input. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * a timer instance is an advanced-control timer. + * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break 2 input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, Break2AFMode must be set to + * LL_TIM_BREAK2_AFMODE_INPUT. + * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n + * BDTR BK2F LL_TIM_ConfigBRK2\n + * BDTR BK2BID LL_TIM_ConfigBRK2 + * @param TIMx Timer instance + * @param Break2Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_POLARITY_LOW + * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH + * @param Break2Filter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 + * @param Break2AFMode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, + uint32_t Break2AFMode) +{ + __IO uint32_t tmpreg; + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode); + /* Note: Any write operation to BK2P bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Disarm the break 2 input (when it operates in bidirectional mode). + * @note The break 2 input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output. + * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); +} + +/** + * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n + * BDTR OSSR LL_TIM_SetOffStates + * @param TIMx Timer instance + * @param OffStateIdle This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSI_DISABLE + * @arg @ref LL_TIM_OSSI_ENABLE + * @param OffStateRun This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSR_DISABLE + * @arg @ref LL_TIM_OSSR_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +} + +/** + * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Disable automatic output (MOE can be set only by software). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Indicate whether automatic output is enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Indicates whether outputs are enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the signals connected to the designated timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n + * AF2 BK2INE LL_TIM_EnableBreakInputSource\n + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + SET_BIT(*pReg, Source); +} + +/** + * @brief Disable the signals connected to the designated timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n + * AF2 BK2INE LL_TIM_DisableBreakInputSource\n + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + CLEAR_BIT(*pReg, Source); +} + +/** + * @brief Set the polarity of the break signal for the timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_POLARITY_LOW + * @arg @ref LL_TIM_BKIN_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, + uint32_t Polarity) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); +} +/** + * @brief Enable asymmetrical deadtime. + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides asymmetrical deadtime. + * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); +} + +/** + * @brief Disable asymmetrical dead-time. + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides asymmetrical deadtime. + * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); +} + +/** + * @brief Indicates whether asymmetrical deadtime is activated. + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides asymmetrical deadtime. + * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); +} + +/** + * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the + * rising edge of OCxN signals). + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not + * asymmetrical dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + * (LOCK bits in TIMx_BDTR register). + * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); +} + +/** + * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and + * the rising edge of OCxN signals). + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not + * asymmetrical dead-time insertion feature is supported by a timer instance. + * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + * (LOCK bits in TIMx_BDTR register). + * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime + * @param TIMx Timer instance + * @retval Returned value can be between Min_Data=0 and Max_Data=255: + */ +__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); +} + +/** + * @brief Enable deadtime preload. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides deadtime preload. + * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); +} + +/** + * @brief Disable dead-time preload. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides deadtime preload. + * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); +} + +/** + * @brief Indicates whether deadtime preload is activated. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides deadtime preload. + * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration + * @{ + */ +/** + * @brief Configures the timer DMA burst feature. + * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n + * DCR DBA LL_TIM_ConfigDMABurst + * @param TIMx Timer instance + * @param DMABurstBaseAddress This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER + * @arg @ref LL_TIM_DMABURST_BASEADDR_SR + * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER + * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT + * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC + * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR + * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 + * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR + * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 + * @param DMABurstLength This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS + * @param DMABurstSource This parameter can be one of the following values: + * @arg @ref LL_TIM_DMA_UPDATE + * @arg @ref LL_TIM_DMA_CC1 + * @arg @ref LL_TIM_DMA_CC2 + * @arg @ref LL_TIM_DMA_CC3 + * @arg @ref LL_TIM_DMA_CC4 + * @arg @ref LL_TIM_DMA_COM + * @arg @ref LL_TIM_DMA_TRIGGER + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength, + uint32_t DMABurstSource) +{ + MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS), + (DMABurstBaseAddress | DMABurstLength | DMABurstSource)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Encoder Encoder configuration + * @{ + */ + +/** + * @brief Enable encoder index. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IE LL_TIM_EnableEncoderIndex + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->ECR, TIM_ECR_IE); +} + +/** + * @brief Disable encoder index. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IE LL_TIM_DisableEncoderIndex + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->ECR, TIM_ECR_IE); +} + +/** + * @brief Indicate whether encoder index is enabled. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U); +} + +/** + * @brief Set index direction + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IDIR LL_TIM_SetIndexDirection + * @param TIMx Timer instance + * @param IndexDirection This parameter can be one of the following values: + * @arg @ref LL_TIM_INDEX_UP_DOWN + * @arg @ref LL_TIM_INDEX_UP + * @arg @ref LL_TIM_INDEX_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection); +} + +/** + * @brief Get actual index direction + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IDIR LL_TIM_GetIndexDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_INDEX_UP_DOWN + * @arg @ref LL_TIM_INDEX_UP + * @arg @ref LL_TIM_INDEX_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR)); +} + +/** + * @brief Set index blanking + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IBLK LL_TIM_SetIndexblanking + * @param TIMx Timer instance + * @param Indexblanking This parameter can be one of the following values: + * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS + * @arg @ref LL_TIM_INDEX_BLANK_TI3 + * @arg @ref LL_TIM_INDEX_BLANK_TI4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexblanking) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking); +} + +/** + * @brief Get actual index blanking + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IBLK LL_TIM_GetIndexblanking + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS + * @arg @ref LL_TIM_INDEX_BLANK_TI3 + * @arg @ref LL_TIM_INDEX_BLANK_TI4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK)); +} + + +/** + * @brief Enable first index. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->ECR, TIM_ECR_FIDX); +} + +/** + * @brief Disable first index. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX); +} + +/** + * @brief Indicates whether first index is enabled. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); +} + +/** + * @brief Set index positioning + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning + * @param TIMx Timer instance + * @param IndexPositionning This parameter can be one of the following values: + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP + * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP_UP + * @arg @ref LL_TIM_INDEX_POSITION_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning); +} + +/** + * @brief Get actual index positioning + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP + * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP_UP + * @arg @ref LL_TIM_INDEX_POSITION_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP + */ +__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS)); +} + +/** + * @brief Configure encoder index. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n + * ECR IBLK LL_TIM_ConfigIDX\n + * ECR FIDX LL_TIM_ConfigIDX\n + * ECR IPOS LL_TIM_ConfigIDX + * @param TIMx Timer instance + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN + * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4 + * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping + * @{ + */ +/** + * @brief Remap TIM inputs (input channel, internal/external triggers). + * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not + * a some timer inputs can be remapped. + * @rmtoll TIM3_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM9_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM12_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM17_TISEL TI1SEL LL_TIM_SetRemap\n + * + * @param TIMx Timer instance + * @param Remap Remap param depends on the TIMx. Description available only + * in CHM version of the User Manual (not in .pdf). + * Otherwise see Reference Manual description of TISEL registers. + * + * Below description summarizes "Timer Instance" and "Remap" param combinations: + * + * TIM3: one of the following values: + * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM3_TI1_RMP_ETH_PPS + * + * TIM9: one of the following values: + * @arg @ref LL_TIM_TIM9_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM9_TI1_RMP_MCO1 + * @arg @ref LL_TIM_TIM9_TI1_RMP_MCO2 + * + * TIM12: one of the following values: + * @arg @ref LL_TIM_TIM12_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM12_TI1_RMP_SPDIF_FS + * @arg @ref LL_TIM_TIM12_TI1_RMP_HSI_1024 + * @arg @ref LL_TIM_TIM12_TI1_RMP_CSI_128 + * @arg @ref LL_TIM_TIM12_TI1_RMP_MCO1 + * @arg @ref LL_TIM_TIM12_TI1_RMP_MCO2 + * + * TIM15: any combination of TI1_RMP and TI2_RMP where + * + * . . TI1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM2_CH1 + * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM3_CH1 + * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM4_CH1 + * @arg @ref LL_TIM_TIM15_TI1_RMP_MCO1 + * @arg @ref LL_TIM_TIM15_TI1_RMP_MCO2 + * + * . . TI2_RMP can be one of the following values + * @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO + * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM2_CH2 + * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM3_CH2 + * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM4_CH2 + * + * TIM16: one of the following values: + * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WKUP + * + * TIM17: one of the following values: + * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM17_TI1_RMP_SPDIF_FS + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) +{ + MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management + * @{ + */ +/** + * @brief Clear the update interrupt flag (UIF). + * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). + * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). + * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). + * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). + * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). + * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). + * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). + * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). + * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). + * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); +} + +/** + * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). + * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). + * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); +} + +/** + * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). + * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the commutation interrupt flag (COMIF). + * @rmtoll SR COMIF LL_TIM_ClearFlag_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); +} + +/** + * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). + * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the trigger interrupt flag (TIF). + * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); +} + +/** + * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). + * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break interrupt flag (BIF). + * @rmtoll SR BIF LL_TIM_ClearFlag_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); +} + +/** + * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). + * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break 2 interrupt flag (B2IF). + * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); +} + +/** + * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). + * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). + * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). + * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). + * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). + * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). + * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). + * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). + * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the system break interrupt flag (SBIF). + * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); +} + +/** + * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). + * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the transition error interrupt flag (TERRF). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF)); +} + +/** + * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the index error interrupt flag (IERRF). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF)); +} + +/** + * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the direction change interrupt flag (DIRF). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF)); +} + +/** + * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the index interrupt flag (IDXF). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF)); +} + +/** + * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL); +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_IT_Management IT-Management + * @{ + */ +/** + * @brief Enable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Disable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Indicates whether the update interrupt (UIE) is enabled. + * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Disable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. + * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Disable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. + * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_EnableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Disable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_DisableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Indicates whether the commutation interrupt (COMIE) is enabled. + * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Disable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Indicates whether the trigger interrupt (TIE) is enabled. + * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_EnableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Disable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_DisableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Indicates whether the break interrupt (BIE) is enabled. + * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable transition error interrupt (TERRIE). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TERRIE); +} + +/** + * @brief Disable transition error interrupt (TERRIE). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE); +} + +/** + * @brief Indicates whether the transition error interrupt (TERRIE) is enabled. + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable index error interrupt (IERRIE). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_IERRIE); +} + +/** + * @brief Disable index error interrupt (IERRIE). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE); +} + +/** + * @brief Indicates whether the index error interrupt (IERRIE) is enabled. + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable direction change interrupt (DIRIE). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_DIRIE); +} + +/** + * @brief Disable direction change interrupt (DIRIE). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE); +} + +/** + * @brief Indicates whether the direction change interrupt (DIRIE) is enabled. + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable index interrupt (IDXIE). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_IDXIE); +} + +/** + * @brief Disable index interrupt (IDXIE). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE); +} + +/** + * @brief Indicates whether the index interrupt (IDXIE) is enabled. + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Management DMA Management + * @{ + */ +/** + * @brief Enable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Disable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Indicates whether the update DMA request (UDE) is enabled. + * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Disable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. + * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Disable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. + * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Disable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Indicates whether the commutation DMA request (COMDE) is enabled. + * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Disable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Indicates whether the trigger interrupt (TDE) is enabled. + * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management + * @{ + */ +/** + * @brief Generate an update event. + * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_UG); +} + +/** + * @brief Generate Capture/Compare 1 event. + * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC1G); +} + +/** + * @brief Generate Capture/Compare 2 event. + * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC2G); +} + +/** + * @brief Generate Capture/Compare 3 event. + * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC3G); +} + +/** + * @brief Generate Capture/Compare 4 event. + * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC4G); +} + +/** + * @brief Generate commutation event. + * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_COMG); +} + +/** + * @brief Generate trigger event. + * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_TG); +} + +/** + * @brief Generate break event. + * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_BG); +} + +/** + * @brief Generate break 2 event. + * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_B2G); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM9 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7RSxx_LL_TIM_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_ucpd.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_ucpd.h new file mode 100644 index 00000000000..77dc3b986ba --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_ucpd.h @@ -0,0 +1,1885 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_ucpd.h + * @author MCD Application Team + * @brief Header file of UCPD LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_UCPD_H +#define STM32H7RSxx_LL_UCPD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (UCPD1) + +/** @defgroup UCPD_LL UCPD + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup UCPD_LL_ES_INIT UCPD Exported Init structure + * @{ + */ + +/** + * @brief UCPD Init structures definition + */ +typedef struct +{ + uint32_t psc_ucpdclk; /*!< Specify the prescaler for the UCPD clock. + This parameter can be a value of @ref UCPD_LL_EC_PSC. + This feature can be modified afterwards using function @ref LL_UCPD_SetPSCClk(). + */ + + uint32_t transwin; /*!< Specify the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV) + to achieve a legal tTransitionWindow (set according to peripheral clock to define + an interval of between 12 and 20 us). + This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F + This value can be modified afterwards using function @ref LL_UCPD_SetTransWin(). + */ + + uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order to generate + tInterframeGap from the peripheral clock. + This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F + This feature can be modified afterwards using function @ref LL_UCPD_SetIfrGap(). + */ + + uint32_t HbitClockDiv; /*!< Specify the number of cycles (minus one) at UCPD peripheral for a half bit clock + e.g. program 3 for a bit clock that takes 8 cycles of the peripheral clock : + "UCPD1_CLK". + This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F. + This feature can be modified using function @ref LL_UCPD_SetHbitClockDiv(). + */ + +} LL_UCPD_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UCPD_LL_Exported_Constants UCPD Exported Constants + * @{ + */ + +/** @defgroup UCPD_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_ucpd_ReadReg function + * @{ + */ +#define LL_UCPD_SR_TXIS UCPD_SR_TXIS /*!< Transmit interrupt status */ +#define LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC /*!< Transmit message discarded interrupt */ +#define LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT /*!< Transmit message sent interrupt */ +#define LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT /*!< Transmit message abort interrupt */ +#define LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC /*!< HRST discarded interrupt */ +#define LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT /*!< HRST sent interrupt */ +#define LL_UCPD_SR_TXUND UCPD_SR_TXUND /*!< Tx data underrun condition interrupt */ +#define LL_UCPD_SR_RXNE UCPD_SR_RXNE /*!< Receive data register not empty interrupt */ +#define LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET /*!< Rx ordered set (4 K-codes) detected interrupt */ +#define LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET /*!< Rx Hard Reset detect interrupt */ +#define LL_UCPD_SR_RXOVR UCPD_SR_RXOVR /*!< Rx data overflow interrupt */ +#define LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND /*!< Rx message received */ +#define LL_UCPD_SR_RXERR UCPD_SR_RXERR /*!< Rx error */ +#define LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1 /*!< Type C voltage level event on CC1 */ +#define LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2 /*!< Type C voltage level event on CC2 */ +#define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1 /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in UCPD register + * @param __INSTANCE__ UCPD Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UCPD_LL_Exported_Functions UCPD Exported Functions + * @{ + */ + +/** @defgroup UCPD_LL_EF_Configuration Configuration + * @{ + */ + +/** @defgroup UCPD_LL_EF_CFG1 CFG1 register + * @{ + */ +/** + * @brief Enable UCPD peripheral + * @rmtoll CFG1 UCPDEN LL_UCPD_Enable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_Enable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); +} + +/** + * @brief Disable UCPD peripheral + * @note When disabling the UCPD, follow the procedure described in the Reference Manual. + * @rmtoll CFG1 UCPDEN LL_UCPD_Disable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_Disable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); +} + +/** + * @brief Check if UCPD peripheral is enabled + * @rmtoll CFG1 UCPDEN LL_UCPD_IsEnabled + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnabled(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the receiver ordered set detection enable + * @rmtoll CFG1 RXORDSETEN LL_UCPD_SetRxOrderSet + * @param UCPDx UCPD Instance + * @param OrderSet This parameter can be combination of the following values: + * @arg @ref LL_UCPD_ORDERSET_SOP + * @arg @ref LL_UCPD_ORDERSET_SOP1 + * @arg @ref LL_UCPD_ORDERSET_SOP2 + * @arg @ref LL_UCPD_ORDERSET_HARDRST + * @arg @ref LL_UCPD_ORDERSET_CABLERST + * @arg @ref LL_UCPD_ORDERSET_SOP1_DEBUG + * @arg @ref LL_UCPD_ORDERSET_SOP2_DEBUG + * @arg @ref LL_UCPD_ORDERSET_SOP_EXT1 + * @arg @ref LL_UCPD_ORDERSET_SOP_EXT2 + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetRxOrderSet(UCPD_TypeDef *UCPDx, uint32_t OrderSet) +{ + MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet); +} + +/** + * @brief Set the prescaler for ucpd clock + * @rmtoll CFG1 UCPDCLK LL_UCPD_SetPSCClk + * @param UCPDx UCPD Instance + * @param Psc This parameter can be one of the following values: + * @arg @ref LL_UCPD_PSC_DIV1 + * @arg @ref LL_UCPD_PSC_DIV2 + * @arg @ref LL_UCPD_PSC_DIV4 + * @arg @ref LL_UCPD_PSC_DIV8 + * @arg @ref LL_UCPD_PSC_DIV16 + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetPSCClk(UCPD_TypeDef *UCPDx, uint32_t Psc) +{ + MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc); +} + +/** + * @brief Set the number of cycles (minus 1) of the half bit clock + * @rmtoll CFG1 TRANSWIN LL_UCPD_SetTransWin + * @param UCPDx UCPD Instance + * @param TransWin a value between Min_Data=0x1 and Max_Data=0x1F + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin) +{ + MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos); +} + +/** + * @brief Set the clock divider value to generate an interframe gap + * @rmtoll CFG1 IFRGAP LL_UCPD_SetIfrGap + * @param UCPDx UCPD Instance + * @param IfrGap a value between Min_Data=0x1 and Max_Data=0x1F + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap) +{ + MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); +} + +/** + * @brief Set the clock divider value to generate an interframe gap + * @rmtoll CFG1 HBITCLKDIV LL_UCPD_SetHbitClockDiv + * @param UCPDx UCPD Instance + * @param HbitClock a value between Min_Data=0x0 and Max_Data=0x3F + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetHbitClockDiv(UCPD_TypeDef *UCPDx, uint32_t HbitClock) +{ + MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos); +} + +/** + * @} + */ + +/** @defgroup UCPD_LL_EF_CFG2 CFG2 register + * @{ + */ + +/** + * @brief Enable Rx Analog Filter + * @rmtoll CFG2 RXAFILTEN LL_UCPD_RxAnalogFilterEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_RxAnalogFilterEnable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN); +} + +/** + * @brief Disable Rx Analog Filter + * @rmtoll CFG2 RXAFILTEN LL_UCPD_RxAnalogFilterDisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_RxAnalogFilterDisable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN); +} + +/** + * @brief Enable the wakeup mode + * @rmtoll CFG2 WUPEN LL_UCPD_WakeUpEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_WakeUpEnable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); +} + +/** + * @brief Disable the wakeup mode + * @rmtoll CFG2 WUPEN LL_UCPD_WakeUpDisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_WakeUpDisable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); +} + +/** + * @brief Force clock enable + * @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ForceClockEnable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); +} + +/** + * @brief Force clock disable + * @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockDisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ForceClockDisable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); +} + +/** + * @brief RxFilter enable + * @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_RxFilterEnable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); +} + +/** + * @brief RxFilter disable + * @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterDisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_RxFilterDisable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UCPD_LL_EF_CR CR register + * @{ + */ +/** + * @brief Type C detector for CC2 enable + * @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Enable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Enable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS); +} + +/** + * @brief Type C detector for CC2 disable + * @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Disable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Disable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS); +} + +/** + * @brief Type C detector for CC1 enable + * @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Enable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Enable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS); +} + +/** + * @brief Type C detector for CC1 disable + * @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Disable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Disable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS); +} + +/** + * @brief Source Vconn discharge enable + * @rmtoll CR RDCH LL_UCPD_VconnDischargeEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_VconnDischargeEnable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_RDCH); +} + +/** + * @brief Source Vconn discharge disable + * @rmtoll CR RDCH LL_UCPD_VconnDischargeDisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_VconnDischargeDisable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CR, UCPD_CR_RDCH); +} + +/** + * @brief Signal Fast Role Swap request + * @rmtoll CR FRSTX LL_UCPD_VconnDischargeDisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SignalFRSTX(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_FRSTX); +} + +/** + * @brief Fast Role swap RX detection enable + * @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_FRSDetectionEnable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_FRSRXEN); +} + +/** + * @brief Fast Role swap RX detection disable + * @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionDisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_FRSDetectionDisable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CR, UCPD_CR_FRSRXEN); +} + +/** + * @brief Set cc enable + * @rmtoll CR CC1VCONNEN LL_UCPD_SetccEnable + * @param UCPDx UCPD Instance + * @param CCEnable This parameter can be one of the following values: + * @arg @ref LL_UCPD_CCENABLE_NONE + * @arg @ref LL_UCPD_CCENABLE_CC1 + * @arg @ref LL_UCPD_CCENABLE_CC2 + * @arg @ref LL_UCPD_CCENABLE_CC1CC2 + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetccEnable(UCPD_TypeDef *UCPDx, uint32_t CCEnable) +{ + MODIFY_REG(UCPDx->CR, UCPD_CR_CCENABLE, CCEnable); +} + +/** + * @brief Set UCPD SNK role + * @rmtoll CR ANAMODE LL_UCPD_SetSNKRole + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetSNKRole(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_ANAMODE); +} + +/** + * @brief Set UCPD SRC role + * @rmtoll CR ANAMODE LL_UCPD_SetSRCRole + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetSRCRole(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CR, UCPD_CR_ANAMODE); +} + +/** + * @brief Get UCPD Role + * @rmtoll CR ANAMODE LL_UCPD_GetRole + * @param UCPDx UCPD Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_UCPD_ROLE_SNK + * @arg @ref LL_UCPD_ROLE_SRC + */ +__STATIC_INLINE uint32_t LL_UCPD_GetRole(UCPD_TypeDef const *const UCPDx) +{ + return (uint32_t)(READ_BIT(UCPDx->CR, UCPD_CR_ANAMODE)); +} + +/** + * @brief Set Rp resistor + * @rmtoll CR ANASUBMODE LL_UCPD_SetRpResistor + * @param UCPDx UCPD Instance + * @param Resistor This parameter can be one of the following values: + * @arg @ref LL_UCPD_RESISTOR_DEFAULT + * @arg @ref LL_UCPD_RESISTOR_1_5A + * @arg @ref LL_UCPD_RESISTOR_3_0A + * @arg @ref LL_UCPD_RESISTOR_NONE + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetRpResistor(UCPD_TypeDef *UCPDx, uint32_t Resistor) +{ + MODIFY_REG(UCPDx->CR, UCPD_CR_ANASUBMODE, Resistor); +} + +/** + * @brief Set CC pin + * @rmtoll CR PHYCCSEL LL_UCPD_SetCCPin + * @param UCPDx UCPD Instance + * @param CCPin This parameter can be one of the following values: + * @arg @ref LL_UCPD_CCPIN_CC1 + * @arg @ref LL_UCPD_CCPIN_CC2 + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetCCPin(UCPD_TypeDef *UCPDx, uint32_t CCPin) +{ + MODIFY_REG(UCPDx->CR, UCPD_CR_PHYCCSEL, CCPin); +} + +/** + * @brief Rx enable + * @rmtoll CR PHYRXEN LL_UCPD_RxEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_RxEnable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_PHYRXEN); +} + +/** + * @brief Rx disable + * @rmtoll CR PHYRXEN LL_UCPD_RxDisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_RxDisable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CR, UCPD_CR_PHYRXEN); +} + +/** + * @brief Set Rx mode + * @rmtoll CR RXMODE LL_UCPD_SetRxMode + * @param UCPDx UCPD Instance + * @param RxMode This parameter can be one of the following values: + * @arg @ref LL_UCPD_RXMODE_NORMAL + * @arg @ref LL_UCPD_RXMODE_BIST_TEST_DATA + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetRxMode(UCPD_TypeDef *UCPDx, uint32_t RxMode) +{ + MODIFY_REG(UCPDx->CR, UCPD_CR_RXMODE, RxMode); +} + +/** + * @brief Send Hard Reset + * @rmtoll CR TXHRST LL_UCPD_SendHardReset + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SendHardReset(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_TXHRST); +} + +/** + * @brief Send message + * @rmtoll CR TXSEND LL_UCPD_SendMessage + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SendMessage(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_TXSEND); +} + +/** + * @brief Set Tx mode + * @rmtoll CR TXMODE LL_UCPD_SetTxMode + * @param UCPDx UCPD Instance + * @param TxMode This parameter can be one of the following values: + * @arg @ref LL_UCPD_TXMODE_NORMAL + * @arg @ref LL_UCPD_TXMODE_CABLE_RESET + * @arg @ref LL_UCPD_TXMODE_BIST_CARRIER2 + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetTxMode(UCPD_TypeDef *UCPDx, uint32_t TxMode) +{ + MODIFY_REG(UCPDx->CR, UCPD_CR_TXMODE, TxMode); +} + +/** + * @} + */ + +/** @defgroup UCPD_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable FRS interrupt + * @rmtoll IMR FRSEVTIE LL_UCPD_EnableIT_FRS + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_FRS(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE); +} + +/** + * @brief Enable type c event on CC2 + * @rmtoll IMR TYPECEVT2IE LL_UCPD_EnableIT_TypeCEventCC2 + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE); +} + +/** + * @brief Enable type c event on CC1 + * @rmtoll IMR TYPECEVT1IE LL_UCPD_EnableIT_TypeCEventCC1 + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE); +} + +/** + * @brief Enable Rx message end interrupt + * @rmtoll IMR RXMSGENDIE LL_UCPD_EnableIT_RxMsgEnd + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_RxMsgEnd(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE); +} + +/** + * @brief Enable Rx overrun interrupt + * @rmtoll IMR RXOVRIE LL_UCPD_EnableIT_RxOvr + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE); +} + +/** + * @brief Enable Rx hard resrt interrupt + * @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_RxHRST(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE); +} + +/** + * @brief Enable Rx orderset interrupt + * @rmtoll IMR RXORDDETIE LL_UCPD_EnableIT_RxOrderSet + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_RxOrderSet(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE); +} + +/** + * @brief Enable Rx non empty interrupt + * @rmtoll IMR RXNEIE LL_UCPD_EnableIT_RxNE + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_RxNE(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE); +} + +/** + * @brief Enable TX underrun interrupt + * @rmtoll IMR TXUNDIE LL_UCPD_EnableIT_TxUND + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TxUND(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE); +} + +/** + * @brief Enable hard reset sent interrupt + * @rmtoll IMR HRSTSENTIE LL_UCPD_EnableIT_TxHRSTSENT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE); +} + +/** + * @brief Enable hard reset discard interrupt + * @rmtoll IMR HRSTDISCIE LL_UCPD_EnableIT_TxHRSTDISC + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE); +} + +/** + * @brief Enable Tx message abort interrupt + * @rmtoll IMR TXMSGABTIE LL_UCPD_EnableIT_TxMSGABT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGABT(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE); +} + +/** + * @brief Enable Tx message sent interrupt + * @rmtoll IMR TXMSGSENTIE LL_UCPD_EnableIT_TxMSGSENT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGSENT(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE); +} + +/** + * @brief Enable Tx message discarded interrupt + * @rmtoll IMR TXMSGDISCIE LL_UCPD_EnableIT_TxMSGDISC + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGDISC(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE); +} + +/** + * @brief Enable Tx data receive interrupt + * @rmtoll IMR TXISIE LL_UCPD_EnableIT_TxIS + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TxIS(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_TXISIE); +} + +/** + * @brief Disable FRS interrupt + * @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_FRS(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE); +} + +/** + * @brief Disable type c event on CC2 + * @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2 + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE); +} + +/** + * @brief Disable type c event on CC1 + * @rmtoll IMR TYPECEVT1IE LL_UCPD_DisableIT_TypeCEventCC1 + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE); +} + +/** + * @brief Disable Rx message end interrupt + * @rmtoll IMR RXMSGENDIE LL_UCPD_DisableIT_RxMsgEnd + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_RxMsgEnd(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE); +} + +/** + * @brief Disable Rx overrun interrupt + * @rmtoll IMR RXOVRIE LL_UCPD_DisableIT_RxOvr + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE); +} + +/** + * @brief Disable Rx hard resrt interrupt + * @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_RxHRST(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE); +} + +/** + * @brief Disable Rx orderset interrupt + * @rmtoll IMR RXORDDETIE LL_UCPD_DisableIT_RxOrderSet + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_RxOrderSet(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE); +} + +/** + * @brief Disable Rx non empty interrupt + * @rmtoll IMR RXNEIE LL_UCPD_DisableIT_RxNE + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_RxNE(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE); +} + +/** + * @brief Disable TX underrun interrupt + * @rmtoll IMR TXUNDIE LL_UCPD_DisableIT_TxUND + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TxUND(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE); +} + +/** + * @brief Disable hard reset sent interrupt + * @rmtoll IMR HRSTSENTIE LL_UCPD_DisableIT_TxHRSTSENT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE); +} + +/** + * @brief Disable hard reset discard interrupt + * @rmtoll IMR HRSTDISCIE LL_UCPD_DisableIT_TxHRSTDISC + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE); +} + +/** + * @brief Disable Tx message abort interrupt + * @rmtoll IMR TXMSGABTIE LL_UCPD_DisableIT_TxMSGABT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGABT(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE); +} + +/** + * @brief Disable Tx message sent interrupt + * @rmtoll IMR TXMSGSENTIE LL_UCPD_DisableIT_TxMSGSENT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGSENT(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE); +} + +/** + * @brief Disable Tx message discarded interrupt + * @rmtoll IMR TXMSGDISCIE LL_UCPD_DisableIT_TxMSGDISC + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGDISC(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE); +} + +/** + * @brief Disable Tx data receive interrupt + * @rmtoll IMR TXISIE LL_UCPD_DisableIT_TxIS + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TxIS(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXISIE); +} + +/** + * @brief Check if FRS interrupt enabled + * @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_FRS(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE) == UCPD_IMR_FRSEVTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if type c event on CC2 enabled + * @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2 + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE) == UCPD_IMR_TYPECEVT2IE) ? 1UL : 0UL); +} + +/** + * @brief Check if type c event on CC1 enabled + * @rmtoll IMR2 TYPECEVT1IE LL_UCPD_IsEnableIT_TypeCEventCC1 + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE) == UCPD_IMR_TYPECEVT1IE) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx message end interrupt enabled + * @rmtoll IMR RXMSGENDIE LL_UCPD_IsEnableIT_RxMsgEnd + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE) == UCPD_IMR_RXMSGENDIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx overrun interrupt enabled + * @rmtoll IMR RXOVRIE LL_UCPD_IsEnableIT_RxOvr + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE) == UCPD_IMR_RXOVRIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx hard resrt interrupt enabled + * @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE) == UCPD_IMR_RXHRSTDETIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx orderset interrupt enabled + * @rmtoll IMR RXORDDETIE LL_UCPD_IsEnableIT_RxOrderSet + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE) == UCPD_IMR_RXORDDETIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx non empty interrupt enabled + * @rmtoll IMR RXNEIE LL_UCPD_IsEnableIT_RxNE + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE) == UCPD_IMR_RXNEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if TX underrun interrupt enabled + * @rmtoll IMR TXUNDIE LL_UCPD_IsEnableIT_TxUND + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE) == UCPD_IMR_TXUNDIE) ? 1UL : 0UL); +} + +/** + * @brief Check if hard reset sent interrupt enabled + * @rmtoll IMR HRSTSENTIE LL_UCPD_IsEnableIT_TxHRSTSENT + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE) == UCPD_IMR_HRSTSENTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if hard reset discard interrupt enabled + * @rmtoll IMR HRSTDISCIE LL_UCPD_IsEnableIT_TxHRSTDISC + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE) == UCPD_IMR_HRSTDISCIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx message abort interrupt enabled + * @rmtoll IMR TXMSGABTIE LL_UCPD_IsEnableIT_TxMSGABT + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE) == UCPD_IMR_TXMSGABTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx message sent interrupt enabled + * @rmtoll IMR TXMSGSENTIE LL_UCPD_IsEnableIT_TxMSGSENT + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE) == UCPD_IMR_TXMSGSENTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx message discarded interrupt enabled + * @rmtoll IMR TXMSGDISCIE LL_UCPD_IsEnableIT_TxMSGDISC + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE) == UCPD_IMR_TXMSGDISCIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx data receive interrupt enabled + * @rmtoll IMR TXISIE LL_UCPD_IsEnableIT_TxIS + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXISIE) == UCPD_IMR_TXISIE) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup UCPD_LL_EF_IT_Clear Interrupt Clear + * @{ + */ + +/** + * @brief Clear FRS interrupt + * @rmtoll ICR FRSEVTIE LL_UCPD_ClearFlag_FRS + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_FRS(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_FRSEVTCF); +} + +/** + * @brief Clear type c event on CC2 + * @rmtoll IIMR TYPECEVT2IE LL_UCPD_ClearFlag_TypeCEventCC2 + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC2(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT2CF); +} + +/** + * @brief Clear type c event on CC1 + * @rmtoll IIMR TYPECEVT1IE LL_UCPD_ClearFlag_TypeCEventCC1 + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC1(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT1CF); +} + +/** + * @brief Clear Rx message end interrupt + * @rmtoll ICR RXMSGENDIE LL_UCPD_ClearFlag_RxMsgEnd + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_RxMsgEnd(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_RXMSGENDCF); +} + +/** + * @brief Clear Rx overrun interrupt + * @rmtoll ICR RXOVRIE LL_UCPD_ClearFlag_RxOvr + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_RXOVRCF); +} + +/** + * @brief Clear Rx hard resrt interrupt + * @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_RxHRST(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_RXHRSTDETCF); +} + +/** + * @brief Clear Rx orderset interrupt + * @rmtoll ICR RXORDDETIE LL_UCPD_ClearFlag_RxOrderSet + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_RxOrderSet(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_RXORDDETCF); +} + +/** + * @brief Clear TX underrun interrupt + * @rmtoll ICR TXUNDIE LL_UCPD_ClearFlag_TxUND + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TxUND(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_TXUNDCF); +} + +/** + * @brief Clear hard reset sent interrupt + * @rmtoll ICR HRSTSENTIE LL_UCPD_ClearFlag_TxHRSTSENT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTSENT(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTSENTCF); +} + +/** + * @brief Clear hard reset discard interrupt + * @rmtoll ICR HRSTDISCIE LL_UCPD_ClearFlag_TxHRSTDISC + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTDISC(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTDISCCF); +} + +/** + * @brief Clear Tx message abort interrupt + * @rmtoll ICR TXMSGABTIE LL_UCPD_ClearFlag_TxMSGABT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGABT(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGABTCF); +} + +/** + * @brief Clear Tx message sent interrupt + * @rmtoll ICR TXMSGSENTIE LL_UCPD_ClearFlag_TxMSGSENT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGSENT(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGSENTCF); +} + +/** + * @brief Clear Tx message discarded interrupt + * @rmtoll ICR TXMSGDISCIE LL_UCPD_ClearFlag_TxMSGDISC + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGDISCCF); +} + +/** + * @} + */ + +/** @defgroup UCPD_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Check if FRS interrupt + * @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_FRSEVT) == UCPD_SR_FRSEVT) ? 1UL : 0UL); +} + +/** + * @brief Check if type c event on CC2 + * @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2 + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT2) == UCPD_SR_TYPECEVT2) ? 1UL : 0UL); +} + +/** + * @brief Check if type c event on CC1 + * @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1 + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT1) == UCPD_SR_TYPECEVT1) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx message end interrupt + * @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXMSGEND) == UCPD_SR_RXMSGEND) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx overrun interrupt + * @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXOVR) == UCPD_SR_RXOVR) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx hard resrt interrupt + * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXHRSTDET) == UCPD_SR_RXHRSTDET) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx orderset interrupt + * @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXORDDET) == UCPD_SR_RXORDDET) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx non empty interrupt + * @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXNE) == UCPD_SR_RXNE) ? 1UL : 0UL); +} + +/** + * @brief Check if TX underrun interrupt + * @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_TXUND) == UCPD_SR_TXUND) ? 1UL : 0UL); +} + +/** + * @brief Check if hard reset sent interrupt + * @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTSENT) == UCPD_SR_HRSTSENT) ? 1UL : 0UL); +} + +/** + * @brief Check if hard reset discard interrupt + * @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTDISC) == UCPD_SR_HRSTDISC) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx message abort interrupt + * @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGABT) == UCPD_SR_TXMSGABT) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx message sent interrupt + * @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGSENT) == UCPD_SR_TXMSGSENT) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx message discarded interrupt + * @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGDISC) == UCPD_SR_TXMSGDISC) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx data receive interrupt + * @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_TXIS) == UCPD_SR_TXIS) ? 1UL : 0UL); +} + +/** + * @brief return the vstate value for CC2 + * @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC2 + * @param UCPDx UCPD Instance + * @retval val + */ +__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const *const UCPDx) +{ + return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC2; +} + +/** + * @brief return the vstate value for CC1 + * @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC1 + * @param UCPDx UCPD Instance + * @retval val + */ +__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const *const UCPDx) +{ + return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC1; +} + +/** + * @} + */ + + +/** @defgroup UCPD_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Rx DMA Enable + * @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMAEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_RxDMAEnable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); +} + +/** + * @brief Rx DMA Disable + * @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMADisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_RxDMADisable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); +} + +/** + * @brief Tx DMA Enable + * @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMAEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_TxDMAEnable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN); +} + +/** + * @brief Tx DMA Disable + * @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMADisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_TxDMADisable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_UCPD_IsEnabledTxDMA + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN) == (UCPD_CFG1_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_UCPD_IsEnabledRxDMA + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN) == (UCPD_CFG1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup UCPD_LL_EF_DATA_Management DATA Management + * @{ + */ + +/** + * @brief write the orderset for Tx message + * @rmtoll TX_ORDSET TXORDSET LL_UCPD_WriteTxOrderSet + * @param UCPDx UCPD Instance + * @param TxOrderSet one of the following value + * @arg @ref LL_UCPD_ORDERED_SET_SOP + * @arg @ref LL_UCPD_ORDERED_SET_SOP1 + * @arg @ref LL_UCPD_ORDERED_SET_SOP2 + * @arg @ref LL_UCPD_ORDERED_SET_HARD_RESET + * @arg @ref LL_UCPD_ORDERED_SET_CABLE_RESET + * @arg @ref LL_UCPD_ORDERED_SET_SOP1_DEBUG + * @arg @ref LL_UCPD_ORDERED_SET_SOP2_DEBUG + * @retval None + */ +__STATIC_INLINE void LL_UCPD_WriteTxOrderSet(UCPD_TypeDef *UCPDx, uint32_t TxOrderSet) +{ + WRITE_REG(UCPDx->TX_ORDSET, TxOrderSet); +} + +/** + * @brief write the Tx paysize + * @rmtoll TX_PAYSZ TXPAYSZ LL_UCPD_WriteTxPaySize + * @param UCPDx UCPD Instance + * @param TxPaySize + * @retval None. + */ +__STATIC_INLINE void LL_UCPD_WriteTxPaySize(UCPD_TypeDef *UCPDx, uint32_t TxPaySize) +{ + WRITE_REG(UCPDx->TX_PAYSZ, TxPaySize); +} + +/** + * @brief Write data + * @rmtoll TXDR DR LL_UCPD_WriteData + * @param UCPDx UCPD Instance + * @param Data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None. + */ +__STATIC_INLINE void LL_UCPD_WriteData(UCPD_TypeDef *UCPDx, uint8_t Data) +{ + WRITE_REG(UCPDx->TXDR, Data); +} + +/** + * @brief read RX the orderset + * @rmtoll RX_ORDSET RXORDSET LL_UCPD_ReadRxOrderSet + * @param UCPDx UCPD Instance + * @retval RxOrderSet one of the following value + * @arg @ref LL_UCPD_RXORDSET_SOP + * @arg @ref LL_UCPD_RXORDSET_SOP1 + * @arg @ref LL_UCPD_RXORDSET_SOP2 + * @arg @ref LL_UCPD_RXORDSET_SOP1_DEBUG + * @arg @ref LL_UCPD_RXORDSET_SOP2_DEBUG + * @arg @ref LL_UCPD_RXORDSET_CABLE_RESET + * @arg @ref LL_UCPD_RXORDSET_SOPEXT1 + * @arg @ref LL_UCPD_RXORDSET_SOPEXT2 + */ +__STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const *const UCPDx) +{ + return READ_BIT(UCPDx->RX_ORDSET, UCPD_RX_ORDSET_RXORDSET); +} + +/** + * @brief Read the Rx paysize + * @rmtoll RX_PAYSZ RXPAYSZ LL_UCPD_ReadRxPaySize + * @param UCPDx UCPD Instance + * @retval RXPaysize. + */ +__STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx) +{ + return READ_BIT(UCPDx->RX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ); +} + +/** + * @brief Read data + * @rmtoll RXDR RXDATA LL_UCPD_ReadData + * @param UCPDx UCPD Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_UCPD_ReadData(UCPD_TypeDef const *const UCPDx) +{ + return READ_REG(UCPDx->RXDR); +} + +/** + * @brief Set Rx OrderSet Ext1 + * @rmtoll RX_ORDEXT1 RXSOPX1 LL_UCPD_SetRxOrdExt1 + * @param UCPDx UCPD Instance + * @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetRxOrdExt1(UCPD_TypeDef *UCPDx, uint32_t SOPExt) +{ + WRITE_REG(UCPDx->RX_ORDEXT1, SOPExt); +} + +/** + * @brief Set Rx OrderSet Ext2 + * @rmtoll RX_ORDEXT2 RXSOPX2 LL_UCPD_SetRxOrdExt2 + * @param UCPDx UCPD Instance + * @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt) +{ + WRITE_REG(UCPDx->RX_ORDEXT2, SOPExt); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup UCPD_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx); +ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct); +void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +#endif /* defined (UCPD1) */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_UCPD_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_usart.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_usart.h new file mode 100644 index 00000000000..dabf7659ef2 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_usart.h @@ -0,0 +1,4400 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_usart.h + * @author MCD Application Team + * @brief Header file of USART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_USART_H +#define STM32H7RSxx_LL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) \ + || defined(UART7) || defined(UART8) + +/** @defgroup USART_LL USART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Variables USART Private Variables + * @{ + */ +/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */ +static const uint32_t USART_PRESCALER_TAB[] = +{ + 1UL, + 2UL, + 4UL, + 6UL, + 8UL, + 10UL, + 12UL, + 16UL, + 32UL, + 64UL, + 128UL, + 256UL +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_Private_Macros USART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_ES_INIT USART Exported Init structures + * @{ + */ + +/** + * @brief LL USART Init Structure definition + */ +typedef struct +{ + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref USART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetPrescaler().*/ + + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetHWFlowCtrl().*/ + + uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetOverSampling().*/ + +} LL_USART_InitTypeDef; + +/** + * @brief LL USART Clock Init Structure definition + */ +typedef struct +{ + uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_CLOCK. + + USART HW configuration can be modified afterwards using unitary functions + @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). + For more details, refer to description of this function. */ + + uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_LL_EC_POLARITY. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPolarity(). + For more details, refer to description of this function. */ + + uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_LL_EC_PHASE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPhase(). + For more details, refer to description of this function. */ + + uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetLastClkPulseOutput(). + For more details, refer to description of this function. */ + +} LL_USART_ClockInitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_USART_WriteReg function + * @{ + */ +#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ +#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ +#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ +#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ +#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ +#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */ +#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_USART_ReadReg function + * @{ + */ +#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ +#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */ +#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ +#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */ +#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ +#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ +#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ +#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + * @{ + */ +#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ +#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ +#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ +#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */ +#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ +#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ +#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DIRECTION Communication Direction + * @{ + */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + * @{ + */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EC_CLOCK Clock Signal + * @{ + */ + +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + * @{ + */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ +#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ +#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ +#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection + * @{ + */ +#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ +#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */ +#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */ +#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation + * @{ + */ +#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + * @{ + */ +#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + * @{ + */ +#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Macros USART Exported Macros + * @{ + */ + +/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + * @{ + */ + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + */ +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + */ +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_LL_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief USART Enable + * @rmtoll CR1 UE LL_USART_Enable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief USART Disable (all USART prescalers and outputs are disabled) + * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the USART is kept, but all the status + * flags, in the USARTx_ISR are set to their default values. + * @rmtoll CR1 UE LL_USART_Disable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if USART is enabled + * @rmtoll CR1 UE LL_USART_IsEnabled + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +/** + * @brief FIFO Mode Enable + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure TX FIFO Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold + * @param USARTx USART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | + (RXThreshold << USART_CR3_RXFTCFG_Pos)); +} + +/** + * @brief USART enabled in STOP Mode. + * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that + * USART clock selection is HSI or LSE in RCC. + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_EnableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief USART disabled in STOP Mode. + * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_DisableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_USART_EnableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_USART_DisableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_USART_EnableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_USART_DisableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + * CR1 TE LL_USART_SetTransferDirection + * @param USARTx USART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + * CR1 TE LL_USART_GetTransferDirection + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled). + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (9th or 8th bit depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_USART_SetParity\n + * CR1 PCE LL_USART_SetParity + * @param USARTx USART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_USART_GetParity\n + * CR1 PCE LL_USART_GetParity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + * @param USARTx USART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_SetDataWidth\n + * CR1 M1 LL_USART_SetDataWidth + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_GetDataWidth\n + * CR1 M1 LL_USART_GetDataWidth + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_USART_EnableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_USART_DisableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Set Oversampling to 8-bit or 16-bit mode + * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + * @param USARTx USART Instance + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); +} + +/** + * @brief Return Oversampling mode + * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); +} + +/** + * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + * @param USARTx USART Instance + * @param LastBitClockPulse This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); +} + +/** + * @brief Retrieve Clock pulse of the last data bit output configuration + * (Last bit Clock pulse output to the SCLK pin or not) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + */ +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); +} + +/** + * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_SetClockPhase + * @param USARTx USART Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); +} + +/** + * @brief Return phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_GetClockPhase + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); +} + +/** + * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + * @param USARTx USART Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); +} + +/** + * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); +} + +/** + * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function + * @rmtoll CR2 CPHA LL_USART_ConfigClock\n + * CR2 CPOL LL_USART_ConfigClock\n + * CR2 LBCL LL_USART_ConfigClock + * @param USARTx USART Instance + * @param Phase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @param LBCPOutput This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); +} + +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler + * @param USARTx USART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER)); +} + +/** + * @brief Enable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Disable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Indicate if Clock output on SCLK pin is enabled + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_USART_SetStopBitsLength + * @param USARTx USART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_USART_GetStopBitsLength + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_USART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_USART_SetParity() function + * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_USART_ConfigCharacter\n + * CR1 PCE LL_USART_ConfigCharacter\n + * CR1 M0 LL_USART_ConfigCharacter\n + * CR1 M1 LL_USART_ConfigCharacter\n + * CR2 STOP LL_USART_ConfigCharacter + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap + * @param USARTx USART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic + * @param USARTx USART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder + * @param USARTx USART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Enable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Disable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); +} + +/** + * @brief Set Auto Baud-Rate mode bits + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode + * @param USARTx USART Instance + * @param AutoBaudRateMode This parameter can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + * @retval None + */ +__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); +} + +/** + * @brief Return Auto Baud-Rate mode + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + */ +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); +} + +/** + * @brief Enable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Disable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Indicate if Receiver Timeout feature is enabled + * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Address of the USART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n + * CR2 ADDM7 LL_USART_ConfigNodeAddress + * @param USARTx USART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the USART node. + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_USART_GetNodeAddress + * @param USARTx USART Instance + * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n + * CR3 CTSE LL_USART_SetHWFlowCtrl + * @param USARTx USART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n + * CR3 CTSE LL_USART_GetHWFlowCtrl + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Disable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Indicate if One bit sampling method is enabled + * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUS LL_USART_SetWKUPType + * @param USARTx USART Instance + * @param Type This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); +} + +/** + * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUS LL_USART_GetWKUPType + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + */ +__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); +} + +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling, + uint32_t BaudRate) +{ + uint32_t usartdiv; + uint32_t brrtemp; + + if (PrescalerValue > LL_USART_PRESCALER_DIV256) + { + /* Do not overstep the size of USART_PRESCALER_TAB */ + } + else if (BaudRate == 0U) + { + /* Can Not divide per 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + USARTx->BRR = brrtemp; + } + else + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); + } +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling) +{ + uint32_t usartdiv; + uint32_t brrresult = 0x0U; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue])); + + usartdiv = USARTx->BRR; + + if (usartdiv == 0U) + { + /* Do not perform a division by 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + if (usartdiv != 0U) + { + brrresult = (periphclkpresc * 2U) / usartdiv; + } + } + else + { + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = periphclkpresc / usartdiv; + } + } + return (brrresult); +} + +/** + * @brief Set Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_SetRxTimeout + * @param USARTx USART Instance + * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); +} + +/** + * @brief Get Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_GetRxTimeout + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + */ +__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); +} + +/** + * @brief Set Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_SetBlockLength + * @param USARTx USART Instance + * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); +} + +/** + * @brief Get Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_GetBlockLength + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature + * @{ + */ + +/** + * @brief Enable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_EnableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Disable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_DisableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Indicate if IrDA mode is enabled + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_IsEnabledIrda + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); +} + +/** + * @brief Configure IrDA Power Mode (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode + * @param USARTx USART Instance + * @param PowerMode This parameter can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_IRDA_POWER_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); +} + +/** + * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); +} + +/** + * @brief Set Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler + * @param USARTx USART Instance + * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature + * @{ + */ + +/** + * @brief Enable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Disable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Indicate if Smartcard NACK transmission is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); +} + +/** + * @brief Enable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_EnableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Disable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_DisableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Indicate if Smartcard mode is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. + * In transmission mode, it specifies the number of automatic retransmission retries, before + * generating a transmission error (FE bit set). + * In reception mode, it specifies the number or erroneous reception trials, before generating a + * reception error (RXNE and PE bits set) + * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Set Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler + * @param USARTx USART Instance + * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime + * @param USARTx USART Instance + * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); +} + +/** + * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime + * @param USARTx USART Instance + * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature + * @{ + */ +/** + * @brief Enable SPI Synchronous Slave mode + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Disable SPI Synchronous Slave mode + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Indicate if SPI Synchronous Slave mode is enabled + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SPI Slave Selection using NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave Selection depends on NSS input pin + * (The slave is selected when NSS is low and deselected when NSS is high). + * @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Disable SPI Slave Selection using NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave will be always selected and NSS input pin will be ignored. + * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Indicate if SPI Slave Selection depends on NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature + * @{ + */ + +/** + * @brief Set LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen + * @param USARTx USART Instance + * @param LINBDLength This parameter can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); +} + +/** + * @brief Return LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + */ +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); +} + +/** + * @brief Enable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_EnableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Disable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_DisableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Indicate if LIN mode is enabled + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_EnableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_DisableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity + * @param USARTx USART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services + * @{ + */ + +/** + * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) + * @note In UART mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Asynchronous Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n + * CR2 CLKEN LL_USART_ConfigAsyncMode\n + * CR3 SCEN LL_USART_ConfigAsyncMode\n + * CR3 IREN LL_USART_ConfigAsyncMode\n + * CR3 HDSEL LL_USART_ConfigAsyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +{ + /* In Asynchronous mode, the following bits must be kept cleared: + - LINEN, CLKEN bits in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Mode + * @note In Synchronous mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n + * CR2 CLKEN LL_USART_ConfigSyncMode\n + * CR3 SCEN LL_USART_ConfigSyncMode\n + * CR3 IREN LL_USART_ConfigSyncMode\n + * CR3 HDSEL LL_USART_ConfigSyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + /* set the UART/USART in Synchronous mode */ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in LIN Mode + * @note In LIN mode, the following bits must be kept cleared: + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also set the UART/USART in LIN mode. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function + * @note Other remaining configurations items related to LIN Mode + * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n + * CR2 STOP LL_USART_ConfigLINMode\n + * CR2 LINEN LL_USART_ConfigLINMode\n + * CR3 IREN LL_USART_ConfigLINMode\n + * CR3 SCEN LL_USART_ConfigLINMode\n + * CR3 HDSEL LL_USART_ConfigLINMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) +{ + /* In LIN mode, the following bits must be kept cleared: + - STOP and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + /* Set the UART/USART in LIN mode */ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode + * @note In Half Duplex mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * This function also sets the UART/USART in Half Duplex mode. + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function + * @note Other remaining configurations items related to Half Duplex Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n + * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n + * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n + * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n + * CR3 IREN LL_USART_ConfigHalfDuplexMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +{ + /* In Half Duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); + /* set the UART/USART in Half Duplex mode */ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Smartcard Mode + * @note In Smartcard mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also configures Stop bits to 1.5 bits and + * sets the USART in Smartcard mode (SCEN bit). + * Clock Output is also enabled (CLKEN). + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function + * @note Other remaining configurations items related to Smartcard Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n + * CR2 STOP LL_USART_ConfigSmartcardMode\n + * CR2 CLKEN LL_USART_ConfigSmartcardMode\n + * CR3 HDSEL LL_USART_ConfigSmartcardMode\n + * CR3 SCEN LL_USART_ConfigSmartcardMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) +{ + /* In Smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); + /* Configure Stop bits to 1.5 bits */ + /* Synchronous mode is activated by default */ + SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); + /* set the UART/USART in Smartcard mode */ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Irda Mode + * @note In IRDA mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the UART/USART in IRDA mode (IREN bit). + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function + * @note Other remaining configurations items related to Irda Mode + * (as Baud Rate, Word length, Power mode, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n + * CR2 CLKEN LL_USART_ConfigIrdaMode\n + * CR2 STOP LL_USART_ConfigIrdaMode\n + * CR3 SCEN LL_USART_ConfigIrdaMode\n + * CR3 HDSEL LL_USART_ConfigIrdaMode\n + * CR3 IREN LL_USART_ConfigIrdaMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) +{ + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + /* set the UART/USART in IRDA mode */ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Multi processor Mode + * (several USARTs connected in a network, one of the USARTs can be the master, + * its TX output connected to the RX inputs of the other slaves USARTs). + * @note In MultiProcessor mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Multi processor Mode + * (as Baud Rate, Wake Up Method, Node address, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n + * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n + * CR3 SCEN LL_USART_ConfigMultiProcessMode\n + * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n + * CR3 IREN LL_USART_ConfigMultiProcessMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +{ + /* In Multi Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART Parity Error Flag is set or not + * @rmtoll ISR PE LL_USART_IsActiveFlag_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Framing Error Flag is set or not + * @rmtoll ISR FE LL_USART_IsActiveFlag_FE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Noise error detected Flag is set or not + * @rmtoll ISR NE LL_USART_IsActiveFlag_NE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_USART_IsActiveFlag_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Flag is set or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS interrupt Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Time Out Flag is set or not + * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Flag is set or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the SPI Slave Underrun error flag is set or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Error Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Busy Flag is set or not + * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Flag is set or not + * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Wake Up from stop mode Flag is set or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Empty Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Full Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not + * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Threshold Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Threshold Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); +} + +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_USART_ClearFlag_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_USART_ClearFlag_FE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise Error detected Flag + * @rmtoll ICR NECF LL_USART_ClearFlag_NE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_NECF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear TX FIFO Empty Flag + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TXFECF); +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_USART_ClearFlag_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear Smartcard Transmission Complete Before Guard Time Flag + * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); +} + +/** + * @brief Clear LIN Break Detection Flag + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Receiver Time Out Flag + * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); +} + +/** + * @brief Clear End Of Block Flag + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); +} + +/** + * @brief Clear SPI Slave Underrun Flag + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_UDRCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_USART_ClearFlag_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CMCF); +} + +/** + * @brief Clear Wake Up from stop mode Flag + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_WUCF); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_EnableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_EnableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_EnableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Enable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Enable TX FIFO Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Enable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable Wake Up from Stop Mode Interrupt + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_DisableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_DisableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_DisableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Disable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Disable TX FIFO Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Disable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable Wake Up from Stop Mode Interrupt + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Check if the USART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + +#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + +#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. + * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Interrupt is enabled or disabled. + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr + * @param USARTx USART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(USARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(USARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData8 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) +{ + return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData9 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) +{ + return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_USART_TransmitData8 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) +{ + USARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_USART_TransmitData9 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) +{ + USARTx->TDR = (uint16_t)(Value & 0x1FFUL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request an Automatic Baud Rate measurement on next received data frame + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ); +} + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put USART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data and FIFO flush + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @brief Request a Transmit data and FIFO flush + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || UART4 || UART5 || UART7 || UART8 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_USART_H */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_usb.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_usb.h new file mode 100644 index 00000000000..aa0708f8b06 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_usb.h @@ -0,0 +1,578 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_usb.h + * @author MCD Application Team + * @brief Header file of USB Low Layer HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_USB_H +#define STM32H7RSxx_LL_USB_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal_def.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup USB_LL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +#ifndef HAL_USB_TIMEOUT +#define HAL_USB_TIMEOUT 0xF000000U +#endif /* define HAL_USB_TIMEOUT */ + +#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS +#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U +#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */ + +/** + * @brief USB Mode definition + */ + +typedef enum +{ + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_ModeTypeDef; + +/** + * @brief URB States definition + */ +typedef enum +{ + URB_IDLE = 0, + URB_DONE, + URB_NOTREADY, + URB_NYET, + URB_ERROR, + URB_STALL +} USB_URBStateTypeDef; + +/** + * @brief Host channel States definition + */ +typedef enum +{ + HC_IDLE = 0, + HC_XFRC, + HC_HALTED, + HC_ACK, + HC_NAK, + HC_NYET, + HC_STALL, + HC_XACTERR, + HC_BBLERR, + HC_DATATGLERR +} USB_HCStateTypeDef; + + +/** + * @brief USB Instance Initialization Structure definition + */ +typedef struct +{ + uint8_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t Host_channels; /*!< Host Channels number. + This parameter Depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t dma_enable; /*!< USB DMA state. + If DMA is not supported this parameter shall be set by default to zero */ + + uint8_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + + uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + + uint8_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + + uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + + uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ + + uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ + + uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + + uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + + uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + + uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ + +} USB_CfgTypeDef; + +typedef struct +{ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_iso_incomplete; /*!< Endpoint isoc condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_LL_EP_Type */ + + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + + uint8_t even_odd_frame; /*!< IFrame parity + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t tx_fifo_num; /*!< Transmission FIFO number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ + + uint32_t xfer_size; /*!< requested transfer size */ +} USB_EPTypeDef; + +typedef struct +{ + uint8_t dev_addr; /*!< USB device address. + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + + uint8_t ch_num; /*!< Host channel number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t speed; /*!< USB Host Channel speed. + This parameter can be any value of @ref HCD_Device_Speed: + (HCD_DEVICE_SPEED_xxx) */ + + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ + uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ + uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */ + uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */ + + uint8_t hub_port_nbr; /*!< USB HUB port number */ + uint8_t hub_addr; /*!< USB HUB address */ + + uint8_t ep_type; /*!< Endpoint Type. + This parameter can be any value of @ref USB_LL_EP_Type */ + + uint16_t max_packet; /*!< Endpoint Max packet size. + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t data_pid; /*!< Initial data PID. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ + + uint32_t XferSize; /*!< OTG Channel transfer size. */ + + uint32_t xfer_len; /*!< Current transfer length. */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ + + uint8_t toggle_in; /*!< IN transfer current toggle flag. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t toggle_out; /*!< OUT transfer current toggle flag + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + + uint32_t ErrCnt; /*!< Host channel error count. */ + uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ + + USB_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_URBStateTypeDef */ + + USB_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_HCStateTypeDef */ +} USB_HCTypeDef; + +typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; +typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; +typedef USB_EPTypeDef USB_OTG_EPTypeDef; +typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; +typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; +typedef USB_HCTypeDef USB_OTG_HCTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @defgroup USB_OTG_CORE VERSION ID + * @{ + */ +#define USB_OTG_CORE_ID_300A 0x4F54300AU +#define USB_OTG_CORE_ID_310A 0x4F54310AU +/** + * @} + */ + +/** @defgroup USB_Core_Mode_ USB Core Mode + * @{ + */ +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U +/** + * @} + */ + +/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed + * @{ + */ +#define USB_OTG_SPEED_HIGH 0U +#define USB_OTG_SPEED_HIGH_IN_FULL 1U +#define USB_OTG_SPEED_FULL 3U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY + * @{ + */ +#define USB_OTG_EMBEDDED_PHY 2U +#define USB_OTG_HS_EMBEDDED_PHY 3U +/** + * @} + */ + +/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value + * @{ + */ +#ifndef USBD_HS_TRDT_VALUE +#define USBD_HS_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +#ifndef USBD_FS_TRDT_VALUE +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +/** + * @} + */ + +/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS + * @{ + */ +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency + * @{ + */ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) +/** + * @} + */ + +/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval + * @{ + */ +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS + * @{ + */ +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed + * @{ + */ +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +#define EP_SPEED_HIGH 2U +/** + * @} + */ + +/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type + * @{ + */ +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U +/** + * @} + */ + +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U +/** + * @} + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines + * @{ + */ +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U +/** + * @} + */ + +/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines + * @{ + */ +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U +/** + * @} + */ + +/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines + * @{ + */ +#define HFIR_6_MHZ 6000U +#define HFIR_60_MHZ 60000U +#define HFIR_48_MHZ 48000U +/** + * @} + */ + +/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines + * @{ + */ +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U +/** + * @} + */ + +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU + +#define HC_MAX_PKT_CNT 256U +#define ISO_SPLT_MPS 188U + +#define HCSPLT_BEGIN 1U +#define HCSPLT_MIDDLE 2U +#define HCSPLT_END 3U +#define HCSPLT_FULL 4U + +#define TEST_J 1U +#define TEST_K 2U +#define TEST_SE0_NAK 3U +#define TEST_PACKET 4U +#define TEST_FORCE_EN 5U + +#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) +#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) + +#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) + +#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\ + + USB_OTG_HOST_CHANNEL_BASE\ + + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) + + +#define EP_ADDR_MSK 0xFU +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) +#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) + +#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma); + +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup); +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); + +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps); +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, + USB_OTG_HCTypeDef *hc, uint8_t dma); + +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32H7RSxx_LL_USB_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_utils.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_utils.h new file mode 100644 index 00000000000..9bc82828cb3 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_utils.h @@ -0,0 +1,388 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_UTILS_H +#define STM32H7RSxx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" +#include "stm32h7rsxx_ll_system.h" +#include "stm32h7rsxx_ll_bus.h" +#include "stm32h7rsxx_ll_rcc.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @brief Package data register base address + */ +#define PACKAGE_BASE_ADDRESS PACKAGE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLM; /*!< Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 0 and Max_Data = 63 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetM(). */ + + uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetN(). */ + + uint32_t PLLP; /*!< Division for the main system clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 + odd division factors are not allowed + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetP(). */ + + uint32_t FRACN; /*!< Fractional part of the multiplication factor for PLL VCO. + This parameter can be a value between 0 and 8191 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetFRACN(). */ + + uint32_t VCO_Input; /*!< PLL clock Input range. + This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetVCOInputRange(). */ + + uint32_t VCO_Output; /*!< PLL clock Output range. + This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetVCOOutputRange(). */ + +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t SYSCLKDivider; /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output. + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetSysPrescaler(). */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_AHB_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + + uint32_t APB4CLKDivider; /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB4_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB4Prescaler(). */ + + uint32_t APB5CLKDivider; /*!< The APB5 clock (PCLK5) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB5_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB5Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + * @{ + */ +#define LL_UTILS_PACKAGETYPE_VFQFPN68_GP 0U /*!< VFQFPN68 GP package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS_GP 1U /*!< TFBGA100 SMPS GP package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_GP 2U /*!< LQFP100 GP package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_GP 3U /*!< LQFP144 GP package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA144_SMPS_GP 4U /*!< UFBGA144 SMPS GP package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA144_SMPS_GFX 5U /*!< UFBGA144 SMPS GFX package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS_GFX 6U /*!< UFBGA169 SMPS GFX package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS_GP 7U /*!< UFBGA169 SMPS GP package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176_25_SMPS_GP 8U /*!< UFBGA176+25 SMPS GP package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS_GP 9U /*!< LQFP176 SMPS GP package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS_GFX 10U /*!< LQFP176 SMPS GFX package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176_25_SMPS_GFX 11U /*!< UFBGA176+25 SMPS GFX package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA225_OCTO 12U /*!< TFBGA225 OCTO package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA225_HEXA 13U /*!< TFBGA225 HEXA package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP_SMPS_GP 14U /*!< WLCSP SMPS GP package type */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @note The read address belongs to an area which may contain virgin data generating + * double ECC error (as never programmed). Thus, in case of cache activation + * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable + * through the MPU. + * @retval UID[31:0] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((__IO uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @note The read address belongs to an area which may contain virgin data generating + * double ECC error (as never programmed). Thus, in case of cache activation + * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable + * through the MPU. + * @retval UID[63:32] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((__IO uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @note The read address belongs to an area which may contain virgin data generating + * double ECC error (as never programmed). Thus, in case of cache activation + * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable + * through the MPU. + * @retval UID[95:64] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((__IO uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @note The read address belongs to an area which may contain virgin data generating + * double ECC error (as never programmed). Thus, in case of cache activation + * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable + * through the MPU. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint32_t)((READ_REG(*((__IO uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF0000UL) >> 16UL); +} + +/** + * @brief Get Package type + * @note The read address belongs to an area which may contain virgin data generating + * double ECC error (as never programmed). Thus, in case of cache activation + * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable + * through the MPU. + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68_GP + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS_GP + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_GP + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_GP + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_SMPS_GP + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_SMPS_GFX + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_SMPS_GFX + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_SMPS_GP + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_25_SMPS_GP + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS_GP + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS_GFX + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_25_SMPS_GFX + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225_OCTO + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225_HEXA + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP_SMPS_GP + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ + return (uint32_t)(READ_REG(*((__IO uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0FUL); +} + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + if (Ticks > 0U) + { + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ + } +} + +void LL_Init1msTick(uint32_t CPU_Frequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t CPU_Frequency); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_CSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, + uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_UTILS_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_wwdg.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_wwdg.h new file mode 100644 index 00000000000..cc62c4d92de --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_ll_wwdg.h @@ -0,0 +1,328 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_wwdg.h + * @author MCD Application Team + * @brief Header file of WWDG LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_LL_WWDG_H +#define STM32H7RSxx_LL_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (WWDG) + +/** @defgroup WWDG_LL WWDG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants + * @{ + */ + +/** @defgroup WWDG_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions + * @{ + */ +#define LL_WWDG_CFR_EWI WWDG_CFR_EWI +/** + * @} + */ + +/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER + * @{ + */ +#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ +#define LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 /*!< WWDG counter clock = (PCLK1/4096)/16 */ +#define LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/32 */ +#define LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/64 */ +#define LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/128 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros + * @{ + */ +/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in WWDG register + * @param __INSTANCE__ WWDG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in WWDG register + * @param __INSTANCE__ WWDG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions + * @{ + */ + +/** @defgroup WWDG_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable Window Watchdog. The watchdog is always disabled after a reset. + * @note It is enabled by setting the WDGA bit in the WWDG_CR register, + * then it cannot be disabled again except by a reset. + * This bit is set by software and only cleared by hardware after a reset. + * When WDGA = 1, the watchdog can generate a reset. + * @rmtoll CR WDGA LL_WWDG_Enable + * @param WWDGx WWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) +{ + SET_BIT(WWDGx->CR, WWDG_CR_WDGA); +} + +/** + * @brief Checks if Window Watchdog is enabled + * @rmtoll CR WDGA LL_WWDG_IsEnabled + * @param WWDGx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx) +{ + return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); +} + +/** + * @brief Set the Watchdog counter value to provided value (7-bits T[6:0]) + * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset + * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles + * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) + * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled) + * @rmtoll CR T LL_WWDG_SetCounter + * @param WWDGx WWDG Instance + * @param Counter 0..0x7F (7 bit counter value) + * @retval None + */ +__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) +{ + MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter); +} + +/** + * @brief Return current Watchdog Counter Value (7 bits counter value) + * @rmtoll CR T LL_WWDG_GetCounter + * @param WWDGx WWDG Instance + * @retval 7 bit Watchdog Counter value + */ +__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->CR, WWDG_CR_T)); +} + +/** + * @brief Set the time base of the prescaler (WDGTB). + * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter + * is decremented every (4096 x 2expWDGTB) PCLK cycles + * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler + * @param WWDGx WWDG Instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_WWDG_PRESCALER_1 + * @arg @ref LL_WWDG_PRESCALER_2 + * @arg @ref LL_WWDG_PRESCALER_4 + * @arg @ref LL_WWDG_PRESCALER_8 + * @arg @ref LL_WWDG_PRESCALER_16 + * @arg @ref LL_WWDG_PRESCALER_32 + * @arg @ref LL_WWDG_PRESCALER_64 + * @arg @ref LL_WWDG_PRESCALER_128 + * @retval None + */ +__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler) +{ + MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler); +} + +/** + * @brief Return current Watchdog Prescaler Value + * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler + * @param WWDGx WWDG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_WWDG_PRESCALER_1 + * @arg @ref LL_WWDG_PRESCALER_2 + * @arg @ref LL_WWDG_PRESCALER_4 + * @arg @ref LL_WWDG_PRESCALER_8 + * @arg @ref LL_WWDG_PRESCALER_16 + * @arg @ref LL_WWDG_PRESCALER_32 + * @arg @ref LL_WWDG_PRESCALER_64 + * @arg @ref LL_WWDG_PRESCALER_128 + */ +__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); +} + +/** + * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]). + * @note This window value defines when write in the WWDG_CR register + * to program Watchdog counter is allowed. + * Watchdog counter value update must occur only when the counter value + * is lower than the Watchdog window register value. + * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value + * (in the control register) is refreshed before the downcounter has reached + * the watchdog window register value. + * Physically is possible to set the Window lower then 0x40 but it is not recommended. + * To generate an immediate reset, it is possible to set the Counter lower than 0x40. + * @rmtoll CFR W LL_WWDG_SetWindow + * @param WWDGx WWDG Instance + * @param Window 0x00..0x7F (7 bit Window value) + * @retval None + */ +__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) +{ + MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window); +} + +/** + * @brief Return current Watchdog Window Value (7 bits value) + * @rmtoll CFR W LL_WWDG_GetWindow + * @param WWDGx WWDG Instance + * @retval 7 bit Watchdog Window value + */ +__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); +} + +/** + * @} + */ + +/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management + * @{ + */ +/** + * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not. + * @note This bit is set by hardware when the counter has reached the value 0x40. + * It must be cleared by software by writing 0. + * A write of 1 has no effect. This bit is also set if the interrupt is not enabled. + * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP + * @param WWDGx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx) +{ + return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF) + * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP + * @param WWDGx WWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx) +{ + WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF); +} + +/** + * @} + */ + +/** @defgroup WWDG_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable the Early Wakeup Interrupt. + * @note When set, an interrupt occurs whenever the counter reaches value 0x40. + * This interrupt is only cleared by hardware after a reset + * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP + * @param WWDGx WWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) +{ + SET_BIT(WWDGx->CFR, WWDG_CFR_EWI); +} + +/** + * @brief Check if Early Wakeup Interrupt is enabled + * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP + * @param WWDGx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx) +{ + return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WWDG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_LL_WWDG_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_util_i3c.h b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_util_i3c.h new file mode 100644 index 00000000000..28ac0997a03 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Inc/stm32h7rsxx_util_i3c.h @@ -0,0 +1,135 @@ +/** + ********************************************************************************************************************** + * @file stm32h7rsxx_util_i3c.h + * @author MCD Application Team + * @brief Header of stm32h7rsxx_util_i3c.c + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32H7RSxx_UTIL_I3C_H +#define STM32H7RSxx_UTIL_I3C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#if defined (USE_HAL_DRIVER) +#include "stm32h7rsxx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#if defined (USE_FULL_LL_DRIVER) +#include "stm32h7rsxx_ll_i3c.h" +#endif /* USE_FULL_LL_DRIVER */ + +/** @addtogroup STM32H7RSxx_UTIL_Driver + * @{ + */ + +/** @defgroup UTILITY_I3C I3C Utility + * @{ + */ +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_UTIL_Exported_Types I3C Utility Exported Types + * @{ + */ + +/** @defgroup I3C_Controller_Timing_Structure_definition I3C Controller Timing Structure definition + * @brief I3C Controller Timing Structure definition + * @{ + */ +typedef struct +{ + uint32_t clockSrcFreq; /*!< Specifies the I3C clock source (in Hz). */ + + uint32_t i3cPPFreq; /*!< Specifies the I3C required bus clock for Push-Pull phase (in Hz). */ + + uint32_t i2cODFreq; /*!< Specifies I2C required bus clock for Open-Drain phase (in Hz). */ + + uint32_t dutyCycle; /*!< Specifies the I3C duty cycle for Pure I3C bus or I2C duty cycle for Mixed bus in percent + This parameter must be a value less than or equal to 50 percent. */ + + uint32_t busType; /*!< Specifies the Bus configuration type. + This parameter must be a value of @ref I3C_UTIL_EC_BUS_TYPE */ +} I3C_CtrlTimingTypeDef; +/** + * @} + */ + +/** @defgroup I3C_Target_Timing_Structure_definition I3C Target Timing Structure definition + * @brief I3C Target Timing Structure definition + * @{ + */ +typedef struct +{ + uint32_t clockSrcFreq; /*!< Specifies the I3C clock source (in Hz). */ +} I3C_TgtTimingTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported define ---------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_UTIL_Exported_Define I3C Utility Exported Define + * @{ + */ + +/** @defgroup I3C_UTIL_EC_BUS_TYPE I3C Utility Bus Type + * @brief Bus type defines which can be used with I3C_CtrlTimingComputation function + * @{ + */ +#define I3C_PURE_I3C_BUS 0U /*!< Pure I3C bus, no I2C */ +#define I3C_MIXED_BUS 1U /*!< Mixed bus I3C and I2C */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup I3C_UTIL_Exported_Functions + * @{ + */ +/** @addtogroup I3C_UTIL_EF_Computation + * @{ + */ +ErrorStatus I3C_CtrlTimingComputation(const I3C_CtrlTimingTypeDef *pInputTiming, + LL_I3C_CtrlBusConfTypeDef *pOutputConfig); +ErrorStatus I3C_TgtTimingComputation(const I3C_TgtTimingTypeDef *pInputTiming, + LL_I3C_TgtBusConfTypeDef *pOutputConfig); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7RSxx_UTIL_I3C_H */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Release_Notes.html b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Release_Notes.html new file mode 100644 index 00000000000..374918b26c7 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Release_Notes.html @@ -0,0 +1,92 @@ + + + + + + + Release Notes for STM32H7RSxx HAL Drivers + + + + + + +
+
+
+

Release Notes for

+

STM32H7RSxx HAL Drivers

+

Copyright © 2024 STMicroelectronics

+ +
+

Purpose

+

The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.

+

The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.

+

The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provides a basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not fully portable across the STM32 families; the availability of some functions depends on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:

+
    +
  • New set of inline functions for direct and atomic register access
    • +
  • One-shot operations that can be used by the HAL drivers or from application level
    • +
  • Full independence from HAL and standalone usage (without HAL drivers)
    • +
  • Full features coverage of all the supported peripherals
    • +
+
+
+

Update History

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+ +
+

First Release

+
    +
  • First official Release of STM32CubeH7RS HAL/LL Drivers supporting STM32H7Rx/Sx devices
    • +
+

Contents

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    +
  • HAL: ADC, CEC, CORDIC, CORTEX, CRC, CRS, CRYP, DBGMCU, DCMIPP, DLB, DMA (HPDMA and GPDMA), DMA2D, DTS, ETH, EXTI, FDCAN, FLASH, FMC, GPIO, GFXMMU, GFXTIM, GPU2D, HASH, I2C, I3C, I2S, ICACHE, IRDA, IWDG, JPEG, LPTIM, LTDC, MCE, MDF, MDIOS, MMC/NAND/NOR/SD/SDRAM/SRAM, PKA, PSSI, PWR, RAMECC, RCC, RNG, RTC, SAI, SBS, SPDIFRX, SMARTCARD, SMBUS, SPI, TIM, UART, USART, USB (HCD and PCD), WWDG, XSPI
    • +
  • LL: ADC, CORDIC, CORTEX, CRC, CRS, DMA, EXTI, FMC, GPIO, I2C, I3C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SDMMC, SPI, SYSTEM, TIM, USART, USB, UTILS, UCPD
    +
    • +
+

Supported Devices and boards

+
    +
  • STM32H7S7xx, STM32H7S3xx, STM32H7R7xx, STM32H7R3xx devices
    • +
+

Backward compatibility

+
    +
  • Not applicable
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Dependencies

+
    +
  • None
    • +
+

Notes

+
    +
  • None
    • +
+
+
+
+
+
+
+
+

For complete documentation on STM32H7Rx/Sx,

+

visit: www.st.com/stm32h7r7-7s7

+

visit: www.st.com/stm32h7r3-7s3

+

This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.

+
+

Info

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+
+
+ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal.c new file mode 100644 index 00000000000..9f99880ff07 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal.c @@ -0,0 +1,1497 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs (Version, Init, Tick) + (+) Services HAL APIs (DBGMCU, SBS) + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */ + +/* Value used to increment hide protection level */ +#define SBS_HDPL_INCREMENT_VALUE (uint8_t)0x6A + +/* Value used to lock/unlock debug functionalities */ +#define SBS_DEBUG_LOCK_VALUE (uint8_t)0xC3 +#define SBS_DEBUG_UNLOCK_VALUE (uint8_t)0xB4 + +/* Mask for SBS_BKLOCKR register update */ +#define SBS_BKLOCKR_MASK (SBS_BKLOCKR_PVD_BL | \ + SBS_BKLOCKR_FLASHECC_BL | \ + SBS_BKLOCKR_CM7LCKUP_BL | \ + SBS_BKLOCKR_BKRAMECC_BL | \ + SBS_BKLOCKR_DTCMECC_BL | \ + SBS_BKLOCKR_ITCMECC_BL | \ + SBS_BKLOCKR_ARAM3ECC_BL | \ + SBS_BKLOCKR_ARAM1ECC_BL) + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup SBS_Private_Macros Private Macros + * @{ + */ +#define IS_SBS_TIMER_BREAK_INPUT(__VALUE__) \ + ((((__VALUE__) & SBS_BKLOCKR_MASK) != 0U) && \ + (((__VALUE__) & ~SBS_BKLOCKR_MASK) == 0U)) + +#define IS_SBS_IO_COMPENSATION_CODE(__VALUE__) \ + (((__VALUE__) == SBS_IO_CELL_CODE) || \ + ((__VALUE__) == SBS_IO_REGISTER_CODE)) + +#define IS_SBS_IO_COMPENSATION_CELL_PMOS_VALUE(__VALUE__) (((__VALUE__) < 16U)) +#define IS_SBS_IO_COMPENSATION_CELL_NMOS_VALUE(__VALUE__) (((__VALUE__) < 16U)) + +#define IS_SBS_ETHERNET_PHY(__VALUE__) \ + (((__VALUE__) == SBS_ETHERNET_PHY_GMII_OR_MII) || \ + ((__VALUE__) == SBS_ETHERNET_PHY_RMII)) + +#define IS_SBS_AXISRAM_WS(__VALUE__) \ + (((__VALUE__) == SBS_AXISRAM_WS_0) || \ + ((__VALUE__) == SBS_AXISRAM_WS_1)) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported variables --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the Flash interface the NVIC allocation and initial time base + clock configuration. + (+) De-initialize common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief Configure the time base source, NVIC and any required global low level hardware + * by calling the HAL_MspInit() callback function to be optionally defined in user file + * stm32h7rsxx_hal_msp.c. + * + * @note HAL_Init() function is called at the beginning of program after reset and before + * the clock configuration. + * + * @note In the default implementation the System Timer (Systick) is used as source of time base. + * The Systick configuration is based on HSI clock, as HSI is the clock + * used after a system Reset and the NVIC configuration is set to Priority group 4. + * Once done, time base tick starts incrementing: the tick variable counter is incremented + * each 1ms in the SysTick_Handler() interrupt handler. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Use SysTick as time base source and configure 1ms tick */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + } + + /* Return function status */ + return status; +} + +/** + * @brief De-initialize common part of the HAL and stop the source of time base. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_APB4_FORCE_RESET(); + __HAL_RCC_APB4_RELEASE_RESET(); + + __HAL_RCC_APB5_FORCE_RESET(); + __HAL_RCC_APB5_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + + __HAL_RCC_AHB3_FORCE_RESET(); + __HAL_RCC_AHB3_RELEASE_RESET(); + + __HAL_RCC_AHB4_FORCE_RESET(); + __HAL_RCC_AHB4_RELEASE_RESET(); + + __HAL_RCC_AHB5_FORCE_RESET(); + __HAL_RCC_AHB5_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base: + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/ + if ((uint32_t)uwTickFreq != 0U) + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U) + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += (uint32_t)uwTickFreq; +} + +/** + * @brief Provide a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @param Freq tick frequency + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a period to ensure minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)uwTickFreq; + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Return the HAL revision. + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return STM32H7RSXX_HAL_VERSION; +} + +/** + * @brief Return the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Return the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); +} + +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @note The read address belongs to an area which may contain virgin data generating + * double ECC error (as never programmed). Thus, in case of cache activation + * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable + * through the MPU. + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @note The read address belongs to an area which may contain virgin data generating + * double ECC error (as never programmed). Thus, in case of cache activation + * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable + * through the MPU. + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @note The read address belongs to an area which may contain virgin data generating + * double ECC error (as never programmed). Thus, in case of cache activation + * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable + * through the MPU. + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions + * @brief HAL Debug functions + * +@verbatim + =============================================================================== + ##### HAL Debug functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Debug Module during SLEEP mode. + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode. + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group4 HAL SBS configuration functions + * @brief HAL SBS configuration functions + * +@verbatim + =============================================================================== + ##### HAL SBS configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Increment/get the HDPL value + (+) Configure the debug access + (+) Configure timer break inputs + (+) Enable/Disable the I/O analog switch voltage booster + (+) Enable/Disable the I/O analog switch supplied by VDD + (+) Configure/Enable/Disable the compensation cell (IO, XSPI1, XSPI2) + +@endverbatim + * @{ + */ + +/** + * @brief Get the boot address holding the initial vector table for Cortex-M7. + * @retval Physical boot address used by the Cortex-M7 after reset + */ +uint32_t HAL_SBS_GetBootAddress(void) +{ + return SBS->BOOTSR; +} + +/** + * @brief Increment hise protection level. + * @retval None + */ +void HAL_SBS_IncrementHDPLValue(void) +{ + MODIFY_REG(SBS->HDPLCR, SBS_HDPLCR_INCR_HDPL, SBS_HDPL_INCREMENT_VALUE); +} + +/** + * @brief Get the current value of the hide protection level. + * @retval Current hide protection level + * This value is one of @ref SBS_HDPL_Value + */ +uint32_t HAL_SBS_GetHDPLValue(void) +{ + return (SBS->HDPLSR & SBS_HDPLSR_HDPL); +} + +/** + * @brief Open the device access port. + * @note This function can be only used when device state is Closed. + * @retval None + */ +void HAL_SBS_OpenAccessPort(void) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK, SBS_DEBUG_UNLOCK_VALUE); +} + +/** + * @brief Open the debug when the hide protection level is authorized. + * @note This function can be only used when device state is Closed. + * @retval None + */ +void HAL_SBS_OpenDebug(void) +{ + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK, (SBS_DEBUG_UNLOCK_VALUE << SBS_DBGCR_DBG_UNLOCK_Pos)); +} + +/** + * @brief Configure the authenticated debug hide protection level. + * @note This function can be only used when device state is Closed. + * @param Level Hide protection level where the authenticated debug opens + * This value is one of @ref SBS_HDPL_Value (except SBS_HDPL_VALUE_0) + * @retval HAL_OK if parameter is correct + * HAL_ERROR otherwise + */ +HAL_StatusTypeDef HAL_SBS_ConfigDebugLevel(uint32_t Level) +{ + /* Check the parameter */ + assert_param(IS_SBS_HDPL(Level)); + + if (Level != SBS_HDPL_VALUE_0) + { + MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL, (Level << SBS_DBGCR_DBG_AUTH_HDPL_Pos)); + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Get the current value of the hide protection level. + * @note This function can be only used when device state is Closed. + * @retval Current hide protection level + * This value is one of @ref SBS_HDPL_Value + */ +uint32_t HAL_SBS_GetDebugLevel(void) +{ + return ((SBS->DBGCR & SBS_DBGCR_DBG_AUTH_HDPL) >> SBS_DBGCR_DBG_AUTH_HDPL_Pos); +} + +/** + * @brief Unlock the access to the debug control register. + * @note This function can be only used when device state is Closed. + * @retval None + */ +void HAL_SBS_UnlockDebugConfig(void) +{ + MODIFY_REG(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK, SBS_DEBUG_UNLOCK_VALUE); +} + +/** + * @brief Lock the access to the debug control register. + * @note This function can be only used when device state is Closed. + * @retval None + */ +void HAL_SBS_LockDebugConfig(void) +{ + MODIFY_REG(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK, SBS_DEBUG_LOCK_VALUE); +} + +/** + * @brief Configure the command passed to the RSS for execution at next reset. + * @param Cmd Command passed to the RSS for execution at next reset + * This value is between 0 and 0xFFFF + * @retval None + */ +void HAL_SBS_ConfigRSSCommand(uint32_t Cmd) +{ + MODIFY_REG(SBS->RSSCMDR, SBS_RSSCMDR_RSSCMD, Cmd); +} + +/** + * @brief Get the command passed to the RSS for execution at next reset. + * @retval Command passed to the RSS for execution at next reset + */ +uint32_t HAL_SBS_GetRSSCommand(void) +{ + return (SBS->RSSCMDR & SBS_RSSCMDR_RSSCMD); +} + +/** + * @brief Enable the I/O analog switch voltage booster + * @note Insure low VDDA voltage operation with I/O analog switch control + * @retval None + */ +void HAL_SBS_EnableIOAnalogBooster(void) +{ + MODIFY_REG(SBS->PMCR, (SBS_PMCR_BOOSTEN | SBS_PMCR_BOOSTVDDSEL), SBS_PMCR_BOOSTEN); +} + +/** + * @brief Disable the I/O analog switch voltage booster + * @retval None + */ +void HAL_SBS_DisableIOAnalogBooster(void) +{ + CLEAR_BIT(SBS->PMCR, SBS_PMCR_BOOSTEN); +} + +/** + * @brief Enable the I/O analog switch supplied by VDD + * @note To be used when I/O analog switch voltage booster is not enabled + * @retval None + */ +void HAL_SBS_EnableIOAnalogSwitchVdd(void) +{ + MODIFY_REG(SBS->PMCR, (SBS_PMCR_BOOSTEN | SBS_PMCR_BOOSTVDDSEL), SBS_PMCR_BOOSTVDDSEL); +} + +/** + * @brief Disable the I/O analog switch supplied by VDD + * @retval None + */ +void HAL_SBS_DisableIOAnalogSwitchVdd(void) +{ + CLEAR_BIT(SBS->PMCR, SBS_PMCR_BOOSTVDDSEL); +} + +/** + * @brief Configure the Ethernet PHY interface + * @param Config specifies the Ethernet PHY interface + * This parameter can be one of the following values: + * @arg SBS_ETHERNET_PHY_GMII_OR_MII GMMI or MII selection + * @arg SBS_ETHERNET_PHY_RMII RMII selection + * @retval None + */ +void HAL_SBS_ConfigEthernetPHY(uint32_t Config) +{ + /* Check the parameter */ + assert_param(IS_SBS_ETHERNET_PHY(Config)); + + MODIFY_REG(SBS->PMCR, SBS_PMCR_ETH_PHYSEL, Config); +} + +/** + * @brief Configure the ECC AXISRAMs wait state when ECC=0 + * @param Config specifies the number of wait state + * This parameter can be one of the following values: + * @arg SBS_AXISRAM_WS_0 0 wait state selection + * @arg SBS_AXISRAM_WS_1 1 wait state selection + * @retval None + */ +void HAL_SBS_ConfigAXISRAMWaitState(uint32_t Config) +{ + /* Check the parameter */ + assert_param(IS_SBS_AXISRAM_WS(Config)); + + MODIFY_REG(SBS->PMCR, SBS_PMCR_AXISRAM_WS, Config); +} + +/** + * @brief Enable the compensation cell + * @param Selection specifies the concerned compensation cell + * This parameter can the combination of the following values: + * @arg SBS_IO_ANALOG_CELL Compensation cell for the I/O analog switches + * @arg SBS_IO_XSPI1_CELL Compensation cell for the I/O of the XSPI1 + * @arg SBS_IO_XSPI2_CELL Compensation cell for the I/O of the XSPI2 + * @retval None + */ +void HAL_SBS_EnableCompensationCell(uint32_t Selection) +{ + /* Check the parameter */ + assert_param(IS_SBS_COMPENSATION_CELL(Selection)); + + SET_BIT(SBS->CCCSR, Selection); +} + +/** + * @brief Disable the compensation cell + * @param Selection specifies the concerned compensation cell + * This parameter can the combination of the following values: + * @arg SBS_IO_ANALOG_CELL Compensation cell for the I/O analog switches + * @arg SBS_IO_XSPI1_CELL Compensation cell for the I/O of the XSPI1 + * @arg SBS_IO_XSPI2_CELL Compensation cell for the I/O of the XSPI2 + * @retval None + */ +void HAL_SBS_DisableCompensationCell(uint32_t Selection) +{ + /* Check the parameter */ + assert_param(IS_SBS_COMPENSATION_CELL(Selection)); + + MODIFY_REG(SBS->CCCSR, Selection, 0U); +} + +/** + * @brief Get the compensation cell ready status + * @param Selection specifies the concerned compensation cell + * This parameter can one of the following values: + * @arg SBS_IO_ANALOG_CELL_READY Compensation cell for the I/O analog switches + * @arg SBS_IO_XSPI1_CELL_READY Compensation cell for the I/O of the XSPI1 + * @arg SBS_IO_XSPI2_CELL_READY Compensation cell for the I/O of the XSPI2 + * @retval Ready status (1 or 0) + */ +uint32_t HAL_SBS_GetCompensationCellReadyStatus(uint32_t Selection) +{ + /* Check the parameter */ + assert_param(IS_SBS_COMPENSATION_CELL_READY(Selection)); + + return (((SBS->CCCSR & Selection) == 0U) ? 0UL : 1UL); +} + +/** + * @brief Configure the code selection for the compensation cell + * @param Selection specifies the concerned compensation cell + * This parameter can one of the following values: + * @arg SBS_IO_ANALOG_CELL Compensation cell for the I/O analog switches + * @arg SBS_IO_XSPI1_CELL Compensation cell for the I/O of the XSPI1 + * @arg SBS_IO_XSPI2_CELL Compensation cell for the I/O of the XSPI2 + * @param Code code selection to be applied for the I/O compensation cell + * This parameter can be one of the following values: + * @arg SBS_IO_CELL_CODE Code from the cell (available in the SBS_CCVALR) + * @arg SBS_IO_REGISTER_CODE Code from the compensation cell code register (SBS_CCSWVALR) + * @param NmosValue In case SBS_IO_REGISTER_CODE is selected, it provides the Nmos value + * to apply in range 0 to 15 else this parameter is not used + * @param PmosValue In case SBS_IO_REGISTER_CODE is selected, it provides the Pmos value + * to apply in range 0 to 15 else this parameter is not used + * @retval None + */ +void HAL_SBS_ConfigCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue, uint32_t PmosValue) +{ + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_SBS_COMPENSATION_CELL(Selection)); + assert_param(IS_SBS_IO_COMPENSATION_CODE(Code)); + + if (Code == SBS_IO_REGISTER_CODE) + { + /* Check the parameters */ + assert_param(IS_SBS_IO_COMPENSATION_CELL_NMOS_VALUE(NmosValue)); + assert_param(IS_SBS_IO_COMPENSATION_CELL_PMOS_VALUE(PmosValue)); + + offset = ((Selection == SBS_IO_ANALOG_CELL) ? 0U : ((Selection == SBS_IO_XSPI1_CELL) ? 8U : 16U)); + + MODIFY_REG(SBS->CCSWVALR, (0xFFU << offset), ((NmosValue << offset) | (PmosValue << (offset + 4U)))); + } + + MODIFY_REG(SBS->CCCSR, (Selection << 1U), (Code << (POSITION_VAL(Selection) + 1U))); +} + +/** + * @brief Get the code selection for the compensation cell + * @param Selection specifies the concerned compensation cell + * This parameter can one of the following values: + * @arg SBS_IO_ANALOG_CELL Compensation cell for the I/O analog switches + * @arg SBS_IO_XSPI1_CELL Compensation cell for the I/O of the XSPI1 + * @arg SBS_IO_XSPI2_CELL Compensation cell for the I/O of the XSPI2 + * @param pCode pointer code selection + * This parameter can be one of the following values: + * @arg SBS_IO_CELL_CODE Code from the cell (available in the SBS_CCVALR) + * @arg SBS_IO_REGISTER_CODE Code from the compensation cell code register (SBS_CCSWVALR) + * @param pNmosValue pointer to the Nmos value in range 0 to 15 + * @param pPmosValue pointer to the Pmos value in range 0 to 15 + * @retval HAL_OK (all values available) or HAL_ERROR (check parameters) + */ +HAL_StatusTypeDef HAL_SBS_GetCompensationCell(uint32_t Selection, uint32_t *pCode, uint32_t *pNmosValue, + uint32_t *pPmosValue) +{ + uint32_t reg; + uint32_t offset; + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check parameters */ + if ((pCode != NULL) && (pNmosValue != NULL) && (pPmosValue != NULL)) + { + *pCode = ((SBS->CCCSR & (Selection << 1U)) == 0U) ? SBS_IO_CELL_CODE : SBS_IO_REGISTER_CODE; + + reg = (*pCode == SBS_IO_CELL_CODE) ? (SBS->CCVALR) : (SBS->CCSWVALR); + offset = ((Selection == SBS_IO_ANALOG_CELL) ? 0U : ((Selection == SBS_IO_XSPI1_CELL) ? 8U : 16U)); + + *pNmosValue = ((reg >> offset) & 0xFU); + *pPmosValue = ((reg >> (offset + 4U)) & 0xFU); + + status = HAL_OK; + } + return status; +} + +/** + * @brief Enable the high speed at low voltage + * @param Selection specifies the concerned IOs + * This parameter can the combination of the following values: + * @arg SBS_IO_ANALOG_HSLV High speed at low voltage for the I/O analog switches + * @arg SBS_IO_XSPI1_HSLV High speed at low voltage for the I/O of the XSPI1 + * @arg SBS_IO_XSPI2_HSLV High speed at low voltage for the I/O of the XSPI2 + * @retval None + */ +void HAL_SBS_EnableIOSpeedOptimize(uint32_t Selection) +{ + /* Check the parameter */ + assert_param(IS_SBS_IOHSLV(Selection)); + + SET_BIT(SBS->CCCSR, Selection); +} + +/** + * @brief Disable the high speed at low voltage + * @param Selection specifies the concerned IOs + * This parameter can the combination of the following values: + * @arg SBS_IO_ANALOG_HSLV High speed at low voltage for the I/O analog switches + * @arg SBS_IO_XSPI1_HSLV High speed at low voltage for the I/O of the XSPI1 + * @arg SBS_IO_XSPI2_HSLV High speed at low voltage for the I/O of the XSPI2 + * @retval None + */ +void HAL_SBS_DisableIOSpeedOptimize(uint32_t Selection) +{ + /* Check the parameter */ + assert_param(IS_SBS_IOHSLV(Selection)); + + MODIFY_REG(SBS->CCCSR, Selection, 0U); +} + +/** + * @brief Configure the Timer Break input for error flag(s). + * @note When a configuration is set, only a system reset can reset it. + * @param Input input configuration + * This parameter can be one or a combinartion of the following values: + * @arg SBS_TIMER_BREAK_LOCK_PVD PVD flag + * @arg SBS_TIMER_BREAK_LOCK_FLASH FLASH double ECC error flag + * @arg SBS_TIMER_BREAK_LOCK_CORE M7 LOCKUP (Hardfault) output + * @arg SBS_TIMER_BREAK_LOCK_ITCM ITCM double ECC error flag + * @arg SBS_TIMER_BREAK_LOCK_DTCM DTCM double ECC error flag + * @arg SBS_TIMER_BREAK_LOCK_AXISRAM1 AXISRAM1 double ECC error flag + * @arg SBS_TIMER_BREAK_LOCK_AXISRAM3 AXISRAM3 double ECC error flag + * @arg SBS_TIMER_BREAK_LOCK_BKPRAM Backup SRAM double ECC error flag + * @retval None + */ +void HAL_SBS_ConfigTimerBreakInput(uint32_t Input) +{ + /* Check the parameter */ + assert_param(IS_SBS_TIMER_BREAK_INPUT(Input)); + + SET_BIT(SBS->BKLOCKR, Input); +} + +/** + * @brief Get the Timer Break input configuration. + * @note When a configuration is set, only a system reset can reset it. + * @retval Timer break input configuration + * This return value can be one or a combinartion of the following values: + * @arg SBS_TIMER_BREAK_LOCK_PVD PVD flag + * @arg SBS_TIMER_BREAK_LOCK_FLASH FLASH double ECC error flag + * @arg SBS_TIMER_BREAK_LOCK_CORE M7 LOCKUP (Hardfault) output + * @arg SBS_TIMER_BREAK_LOCK_ITCM ITCM double ECC error flag + * @arg SBS_TIMER_BREAK_LOCK_DTCM DTCM double ECC error flag + * @arg SBS_TIMER_BREAK_LOCK_AXISRAM1 AXISRAM1 double ECC error flag + * @arg SBS_TIMER_BREAK_LOCK_AXISRAM3 AXISRAM3 double ECC error flag + * @arg SBS_TIMER_BREAK_LOCK_BKPRAM Backup SRAM double ECC error flag + */ +uint32_t HAL_SBS_GetTimerBreakInputConfig(void) +{ + return (SBS->BKLOCKR & SBS_BKLOCKR_MASK); +} + +/** + * @brief Configure the source input used for EXTI. + * @param Exti EXTI event to be configured + * This parameter should be between 0 and 15 + * @param Port Port whom pin is used + * This parameter can be one of the following values: + * @arg SBS_EXTI_PIN_PORTA Port A pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTB Port B pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTC Port C pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTD Port D pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTE Port E pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTF Port F pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTG Port G pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTH Port H pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTM Port M pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTN Port N pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTO Port O pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTP Port P pin input of EXTI event detection + * @retval None + */ +void HAL_SBS_EXTIConfig(uint32_t Exti, uint32_t Port) +{ + uint32_t reg; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_SBS_EXTI_INPUT(Exti)); + assert_param(IS_SBS_EXTI_PIN(Port)); + + reg = (Exti / 4U); + offset = (4U * (Exti % 4U)); + + MODIFY_REG(SBS->EXTICR[reg], (0xFU << offset), (Port << offset)); +} + +/** + * @brief Get the source input used for EXTI. + * @param Exti EXTI configuration requested + * This parameter should be between 0 and 15 + * @retval Return value is port whom pin is used + * This return value can be one of the following values: + * @arg SBS_EXTI_PIN_PORTA Port A pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTB Port B pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTC Port C pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTD Port D pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTE Port E pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTF Port F pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTG Port G pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTH Port H pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTM Port M pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTN Port N pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTO Port O pin input of EXTI event detection + * @arg SBS_EXTI_PIN_PORTP Port P pin input of EXTI event detection + */ +uint32_t HAL_SBS_GetEXTIConfig(uint32_t Exti) +{ + uint32_t reg; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_SBS_EXTI_INPUT(Exti)); + + reg = (Exti / 4U); + offset = (4U * (Exti % 4U)); + + return ((SBS->EXTICR[reg] & (0xFUL << offset)) >> offset); +} +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group5 VREFBUF Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the internal voltage reference buffer voltage scale + (+) Configure the internal voltage reference buffer high impedance mode + (+) Tune the Internal Voltage Reference buffer + (+) Enable the Internal Voltage Reference buffer + (+) Disable the Internal Voltage Reference buffer + +@endverbatim + * @{ + */ + +/** + * @brief Configure the internal voltage reference buffer voltage scale. + * @param VoltageScaling specifies the output voltage to achieve + * This parameter can be one of the following values: + * @arg VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.5 V. + * This requires VDDA equal to or higher than 2.8 V. + * @arg VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.048 V. + * This requires VDDA equal to or higher than 2.4 V. + * @arg VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.8 V. + * This requires VDDA equal to or higher than 2.1 V. + * @arg VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.5 V. + * This requires VDDA equal to or higher than 1.8 V. + * @retval None + */ +void HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) +{ + /* Check the parameters */ + assert_param(IS_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); +} + +/** + * @brief Configure the internal voltage reference buffer high impedance mode. + * @param Mode specifies the high impedance mode + * This parameter can be one of the following values: + * @arg VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. + * @arg VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. + * @retval None + */ +void HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode) +{ + /* Check the parameters */ + assert_param(IS_VREFBUF_HIGH_IMPEDANCE(Mode)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); +} + +/** + * @brief Tune the Internal Voltage Reference buffer (VREFBUF). + * @retval None + */ +void HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) +{ + /* Check the parameters */ + assert_param(IS_VREFBUF_TRIMMING(TrimmingValue)); + + MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); +} + +/** + * @brief Enable the Internal Voltage Reference buffer (VREFBUF). + * @retval HAL_OK/HAL_TIMEOUT + */ +HAL_StatusTypeDef HAL_VREFBUF_Enable(void) +{ + uint32_t tickstart; + + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for VRR bit */ + while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL) + { + if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the Internal Voltage Reference buffer (VREFBUF). + * + * @retval None + */ +void HAL_VREFBUF_Disable(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group6 HAL AXIM configuration functions + * @brief HAL AXI Interconnect Matrix (AXIM) configuration functions + * +@verbatim + =============================================================================== + ##### HAL AXIM configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configures ASIB (AMBA slave interface blocks) and AMIB (AMBA master interface blocks) parameters, + such as the QoS (quality of service) level. +@endverbatim + * @{ + */ + +/** + * @brief Enable packing for ASIB. + * @note Normal operation, Enable packing of beats to match the output data width. + * @param AsibInstance specifies the ASIB to configure + * This parameter can be one of the following values: + * @arg AXIM_ASIB_1 : ASIB 1 connected to AHB master + * @arg AXIM_ASIB_2 : ASIB 2 connected to SDMMC1 master + * @retval None + */ +void HAL_AXIM_ASIB_EnablePacking(AXIM_ASIB_TypeDef *AsibInstance) +{ + /* Check the parameters */ + assert_param(IS_AXIM_ASIB_ALL_INSTANCE(AsibInstance)); + + /* Apply packing configuration for the selected ASIB */ + WRITE_REG(AsibInstance->FNMOD2, 0U); +} + +/** + * @brief Disable packing for ASIB. + * @note Network does not perform any packing of beats to match the output data width. + * @note Unaligned transactions are not realigned to the input data word boundary. + * @param AsibInstance specifies the ASIB to configure + * This parameter can be one of the following values: + * @arg AXIM_ASIB_1 : ASIB 1 connected to AHB master + * @arg AXIM_ASIB_2 : ASIB 2 connected to SDMMC1 master + * @retval None + */ +void HAL_AXIM_ASIB_DisablePacking(AXIM_ASIB_TypeDef *AsibInstance) +{ + /* Check the parameters */ + assert_param(IS_AXIM_ASIB_ALL_INSTANCE(AsibInstance)); + + /* Apply packing configuration for the selected ASIB */ + WRITE_REG(AsibInstance->FNMOD2, AXIM_ASIB_FNMOD2_BYPASS_MERGE); +} + +/** + * @brief Configure ASIB read/write issuing capability. + * @param AsibInstance specifies the ASIB to configure + * This parameter can be one of the following values: + * @arg AXIM_ASIB_1 : ASIB 1 connected to AHB master + * @arg AXIM_ASIB_2 : ASIB 2 connected to SDMMC1 master + * @arg AXIM_ASIB_3 : ASIB 3 connected to HPDMA master + * @arg AXIM_ASIB_4 : ASIB 4 connected to C-M7 master + * @arg AXIM_ASIB_5 : ASIB 5 connected to GPU master + * @arg AXIM_ASIB_6 : ASIB 6 connected to GPU master + * @arg AXIM_ASIB_7 : ASIB 7 connected to GPU master + * @arg AXIM_ASIB_8 : ASIB 8 connected to DCMIPP master + * @arg AXIM_ASIB_9 : ASIB 9 connected to GFXMMU master + * @arg AXIM_ASIB_10 : ASIB 10 connected to LTDC master + * @arg AXIM_ASIB_11 : ASIB 11 connected to DMA2D master + * @param ReadIssuing specifies the Read issuing capability to configure + * This parameter can be one of the following values: + * @arg AXIM_ASIB_READ_ISS_NORMAL : Normal issuing capability, default value. + * @arg AXIM_ASIB_READ_ISS_FORCE_TO_1: Force issuing capability to 1. + * @param WriteIssuing specifies the write issuing capability to configure + * This parameter can be one of the following values: + * @arg AXIM_ASIB_WRITE_ISS_NORMAL : Normal issuing capability, default value. + * @arg AXIM_ASIB_WRITE_ISS_FORCE_TO_1: Force issuing capability to 1. + * @retval None + */ +void HAL_AXIM_ASIB_IssuingConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t ReadIssuing, uint32_t WriteIssuing) +{ + /* Check the parameters */ + assert_param(IS_AXIM_ASIB_ALL_INSTANCE(AsibInstance)); + assert_param(IS_AXIM_ASIB_READ_ISS(ReadIssuing)); + assert_param(IS_AXIM_ASIB_WRITE_ISS(WriteIssuing)); + + /* Apply read/write issuing configuration for the selected ASIB */ + WRITE_REG(AsibInstance->FNMOD, (ReadIssuing | WriteIssuing)); +} + +/** + * @brief Configure ASIB read QOS priority. + * @param AsibInstance specifies the ASIB to configure + * This parameter can be one of the following values: + * @arg AXIM_ASIB_1 : ASIB 1 connected to AHB master + * @arg AXIM_ASIB_2 : ASIB 2 connected to SDMMC1 master + * @arg AXIM_ASIB_3 : ASIB 3 connected to HPDMA master + * @arg AXIM_ASIB_4 : ASIB 4 connected to C-M7 master + * @arg AXIM_ASIB_5 : ASIB 5 connected to GPU master + * @arg AXIM_ASIB_6 : ASIB 6 connected to GPU master + * @arg AXIM_ASIB_7 : ASIB 7 connected to GPU master + * @arg AXIM_ASIB_8 : ASIB 8 connected to DCMIPP master + * @arg AXIM_ASIB_9 : ASIB 9 connected to GFXMMU master + * @arg AXIM_ASIB_10 : ASIB 10 connected to LTDC master + * @arg AXIM_ASIB_11 : ASIB 11 connected to DMA2D master + * @param QosPriority specifies read channel QoS setting + * This parameter can be a value between 0 to 15. + * With 0 value (default value) for the lowest priority and 15 value for Highest priority. + * @retval None + */ +void HAL_AXIM_ASIB_ReadQoSConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t QosPriority) +{ + /* Check the parameters */ + assert_param(IS_AXIM_ASIB_ALL_INSTANCE(AsibInstance)); + assert_param(IS_AXIM_QOS(QosPriority)); + + /* Apply read QOS priority setting for the selected ASIB */ + WRITE_REG(AsibInstance->READQOS, QosPriority); +} + +/** + * @brief Configure ASIB write QOS priority. + * @param AsibInstance specifies the ASIB to configure + * This parameter can be one of the following values: + * @arg AXIM_ASIB_1 : ASIB 1 connected to AHB master + * @arg AXIM_ASIB_2 : ASIB 2 connected to SDMMC1 master + * @arg AXIM_ASIB_3 : ASIB 3 connected to HPDMA master + * @arg AXIM_ASIB_4 : ASIB 4 connected to C-M7 master + * @arg AXIM_ASIB_5 : ASIB 5 connected to GPU master + * @arg AXIM_ASIB_6 : ASIB 6 connected to GPU master + * @arg AXIM_ASIB_7 : ASIB 7 connected to GPU master + * @arg AXIM_ASIB_8 : ASIB 8 connected to DCMIPP master + * @arg AXIM_ASIB_9 : ASIB 9 connected to GFXMMU master + * @arg AXIM_ASIB_10 : ASIB 10 connected to LTDC master + * @arg AXIM_ASIB_11 : ASIB 11 connected to DMA2D master + * @param QosPriority specifies write channel QoS setting + * This parameter can be a value between 0 to 15. + * With 0 value (default value) for the lowest priority and 15 value for highest priority. + * + * @retval None + */ +void HAL_AXIM_ASIB_WriteQoSConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t QosPriority) +{ + /* Check the parameters */ + assert_param(IS_AXIM_ASIB_ALL_INSTANCE(AsibInstance)); + assert_param(IS_AXIM_QOS(QosPriority)); + + /* Apply write QOS priority setting for the selected ASIB */ + WRITE_REG(AsibInstance->WRITEQOS, QosPriority); +} + +/** + * @brief Enable Packing for AMIB. + * @note Normal operation, Enable packing of beats to match the output data width. + * @param AmibInstance specifies the AMIB to configure + * This parameter can be one of the following values: + * @arg AXIM_AMIB_2 : AMIB 2 connected to AHB Sram slave + * @retval None + */ +void HAL_AXIM_AMIB_EnablePacking(AXIM_AMIB_TypeDef *AmibInstance) +{ + /* Check the parameters */ + assert_param(IS_AXIM_AMIB_ALL_INSTANCE(AmibInstance)); + + /* Apply packing configuration for the selected AMIB */ + WRITE_REG(AmibInstance->FNMOD2, 0U); +} + +/** + * @brief Disable Packing for AMIB. + * @note Network does not perform any packing of beats to match the output data width. + * @note Unaligned transactions are not realigned to the input data word boundary. + * @param AmibInstance specifies the AMIB to configure + * This parameter can be one of the following values: + * @arg AXIM_AMIB_2 : AMIB 2 connected to AHB Sram slave + * @retval None + */ +void HAL_AXIM_AMIB_DisablePacking(AXIM_AMIB_TypeDef *AmibInstance) +{ + /* Check the parameters */ + assert_param(IS_AXIM_AMIB_ALL_INSTANCE(AmibInstance)); + + /* Apply packing configuration for the selected AMIB */ + WRITE_REG(AmibInstance->FNMOD2, AXIM_AMIB_FNMOD2_BYPASS_MERGE); +} + +/** + * @brief Configure AMIB read/write issuing capability. + * @param AmibInstance specifies the AMIB to configure + * This parameter can be one of the following values: + * @arg AXIM_AMIB_1 : AMIB 1 connected to GFXMMU slave + * @arg AXIM_AMIB_2 : AMIB 2 connected to AHB Sram slave + * @arg AXIM_AMIB_3 : AMIB 3 connected to FMC slave + * @arg AXIM_AMIB_4 : AMIB 4 connected to XSPI1 slave + * @arg AXIM_AMIB_5 : AMIB 5 connected to XSPI2 slave + * @arg AXIM_AMIB_6 : AMIB 6 connected to AXI SRAM4 slave + * @arg AXIM_AMIB_7 : AMIB 7 connected to AXI SRAM3 slave + * @arg AXIM_AMIB_8 : AMIB 8 connected to AXI SRAM2 slave + * @arg AXIM_AMIB_9 : AMIB 9 connected to AXI SRAM1 slave + * @arg AXIM_AMIB_10 : AMIB 10 connected to FLASH slave + * @param ReadIssuing specifies the Read issuing capability to configure + * This parameter can be one of the following values: + * @arg AXIM_AMIB_READ_ISS_NORMAL : Normal issuing capability, default value. + * @arg AXIM_AMIB_READ_ISS_FORCE_TO_1: Force issuing capability to 1. + * @param WriteIssuing specifies the write issuing capability to configure + * This parameter can be one of the following values: + * @arg AXIM_AMIB_WRITE_ISS_NORMAL : Normal issuing capability, default value. + * @arg AXIM_AMIB_WRITE_ISS_FORCE_TO_1: Force issuing capability to 1. + * @retval None + */ +void HAL_AXIM_AMIB_IssuingConfig(AXIM_AMIB_TypeDef *AmibInstance, uint32_t ReadIssuing, uint32_t WriteIssuing) +{ + /* Check the parameters */ + assert_param(IS_AXIM_AMIB_ALL_INSTANCE(AmibInstance)); + assert_param(IS_AXIM_AMIB_READ_ISS(ReadIssuing)); + assert_param(IS_AXIM_AMIB_WRITE_ISS(WriteIssuing)); + + /* Apply read/write issuing configuration for the selected AMIB */ + WRITE_REG(AmibInstance->FNMOD, (ReadIssuing | WriteIssuing)); +} + +/** + * @brief Configure AMIB read/write issuing bus matrix capability. + * @param AmibInstance specifies the AMIB to configure + * This parameter can be one of the following values: + * @arg AXIM_AMIB_1 : AMIB 1 connected to GFXMMU slave + * @arg AXIM_AMIB_2 : AMIB 2 connected to AHB Sram slave + * @arg AXIM_AMIB_3 : AMIB 3 connected to FMC slave + * @arg AXIM_AMIB_4 : AMIB 4 connected to XSPI1 slave + * @arg AXIM_AMIB_5 : AMIB 5 connected to XSPI2 slave + * @arg AXIM_AMIB_6 : AMIB 6 connected to AXI SRAM4 slave + * @arg AXIM_AMIB_7 : AMIB 7 connected to AXI SRAM3 slave + * @arg AXIM_AMIB_8 : AMIB 8 connected to AXI SRAM2 slave + * @arg AXIM_AMIB_9 : AMIB 9 connected to AXI SRAM1 slave + * @arg AXIM_AMIB_10 : AMIB 10 connected to FLASH slave + * @param ReadIssuing specifies the Read issuing capability to configure + * This parameter can be one of the following values: + * @arg AXIM_AMIB_READ_ISS_NORMAL : Normal issuing capability, default value. + * @arg AXIM_AMIB_READ_ISS_FORCE_TO_1: Force issuing capability to 1. + * @param WriteIssuing specifies the write issuing capability to configure + * This parameter can be one of the following values: + * @arg AXIM_AMIB_WRITE_ISS_NORMAL : Normal issuing capability, default value. + * @arg AXIM_AMIB_WRITE_ISS_FORCE_TO_1: Force issuing capability to 1. + * @retval None + */ +void HAL_AXIM_AMIB_IssuingConfigBusMatrix(AXIM_AMIB_TypeDef *AmibInstance, uint32_t ReadIssuing, uint32_t WriteIssuing) +{ + /* Check the parameters */ + assert_param(IS_AXIM_AMIB_ALL_INSTANCE(AmibInstance)); + assert_param(IS_AXIM_AMIB_READ_ISS_BM(ReadIssuing)); + assert_param(IS_AXIM_AMIB_WRITE_ISS_BM(WriteIssuing)); + + /* Apply read/write issuing configuration for the selected AMIB */ + WRITE_REG(AmibInstance->FNMODBMISS, (ReadIssuing | WriteIssuing)); +} + +/** + * @brief Enable Long burst for AMIB. + * @note Long bursts can be generated at the output of the AMIB. + * @param AmibInstance specifies the AMIB to configure + * This parameter can be one of the following values: + * @arg AXIM_AMIB_2 : AMIB 2 connected to AHB Sram slave + * @retval None + */ +void HAL_AXIM_AMIB_EnableLongBurst(AXIM_AMIB_TypeDef *AmibInstance) +{ + /* Check the parameters */ + assert_param(IS_AXIM_AMIB_ALL_INSTANCE(AmibInstance)); + + /* Apply Long burst configuration for the selected AMIB */ + WRITE_REG(AmibInstance->FNMODLB, AXIM_AMIB_FNMODLB_LONG_BURST); +} + +/** + * @brief Disable Long burst for AMIB. + * @note Long bursts can not be generated at the output of the AMIB. + * @param AmibInstance specifies the AMIB to configure + * This parameter can be one of the following values: + * @arg AXIM_AMIB_2 : AMIB 2 connected to AHB Sram slave + * @retval None + */ +void HAL_AXIM_AMIB_DisableLongBurst(AXIM_AMIB_TypeDef *AmibInstance) +{ + /* Check the parameters */ + assert_param(IS_AXIM_AMIB_ALL_INSTANCE(AmibInstance)); + + /* Apply Long burst configuration for the selected AMIB */ + WRITE_REG(AmibInstance->FNMODLB, 0U); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_adc.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_adc.c new file mode 100644 index 00000000000..cb0a7045ace --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_adc.c @@ -0,0 +1,3768 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_adc.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Converter (ADC) + * peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * Other functions (extended functions) are available in file + * "stm32h7rsxx_hal_adc_ex.c". + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### ADC peripheral features ##### + ============================================================================== + [..] + (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. + + (+) Interrupt generation at the end of regular conversion and in case of + analog watchdog or overrun events. + + (+) Single and continuous conversion modes. + + (+) Scan mode for conversion of several channels sequentially. + + (+) Data alignment with in-built data coherency. + + (+) Programmable sampling time (channel wise) + + (+) External trigger (timer or EXTI) with configurable polarity + + (+) DMA request generation for transfer of conversions data of regular group. + + (+) Configurable delay between conversions in Dual interleaved mode. + + (+) ADC channels selectable single/differential input. + + (+) ADC offset shared on 4 offset instances. + (+) ADC calibration + + (+) ADC conversion of regular group. + + (+) ADC supply requirements: 1.62 V to 3.6 V. + + (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to + Vdda or to an external voltage reference). + + + ##### How to use this driver ##### + ============================================================================== + [..] + + *** Configuration of top level parameters related to ADC *** + ============================================================ + [..] + + (#) Enable the ADC interface + (++) As prerequisite, ADC clock must be configured at RCC top level. + + (++) Two clock settings are mandatory: + (+++) ADC clock (core clock, also possibly conversion clock). + + (+++) ADC clock (conversions clock). + Two possible clock sources: synchronous clock derived from AHB clock + or asynchronous clock derived from system clock or PLL. + + (+++) Example: + Into HAL_ADC_MspInit() (recommended code location) or with + other device clock parameters configuration: + (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory) + + RCC_ADCCLKSOURCE_PLL enable: (optional: if asynchronous clock selected) + (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit; + (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; + (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL; + (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); + + (++) ADC clock source and clock prescaler are configured at ADC level with + parameter "ClockPrescaler" using function HAL_ADC_Init(). + + (#) ADC pins configuration + (++) Enable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_ENABLE() + (++) Configure these ADC pins in analog mode + using function HAL_GPIO_Init() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Configure the NVIC for ADC + using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding ADC interruption vector + ADCx_IRQHandler(). + + (#) Optionally, in case of usage of DMA: + (++) Configure the DMA (DMA channel, mode normal or circular, ...) + using function HAL_DMA_Init(). + (++) Configure the NVIC for DMA + using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding DMA interruption vector + DMAx_Channelx_IRQHandler(). + + *** Configuration of ADC, group regular, channels parameters *** + ================================================================ + [..] + + (#) Configure the ADC parameters (resolution, data alignment, ...) + and regular group parameters (conversion trigger, sequencer, ...) + using function HAL_ADC_Init(). + + (#) Configure the channels for regular group parameters (channel number, + channel rank into sequencer, ..., into regular group) + using function HAL_ADC_ConfigChannel(). + + (#) Optionally, configure the analog watchdog parameters (channels + monitored, thresholds, ...) + using function HAL_ADC_AnalogWDGConfig(). + + *** Execution of ADC conversions *** + ==================================== + [..] + + (#) Optionally, perform an automatic ADC calibration to improve the + conversion accuracy + using function HAL_ADCEx_Calibration_Start(). + + (#) ADC driver can be used among three modes: polling, interruption, + transfer by DMA. + + (++) ADC conversion by polling: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start() + (+++) Wait for ADC conversion completion + using function HAL_ADC_PollForConversion() + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop() + + (++) ADC conversion by interruption: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_IT() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() + (this function must be implemented in user program) + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_IT() + + (++) ADC conversion with transfer by DMA: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_DMA() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() + (these functions must be implemented in user program) + (+++) Conversion results are automatically transferred by DMA into + destination variable address. + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_DMA() + + [..] + + (@) Callback functions must be implemented in user program: + (+@) HAL_ADC_ErrorCallback() + (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) + (+@) HAL_ADC_ConvCpltCallback() + (+@) HAL_ADC_ConvHalfCpltCallback + + *** Deinitialization of ADC *** + ============================================================ + [..] + + (#) Disable the ADC interface + (++) ADC clock can be hard reset and disabled at RCC top level. + (++) Hard reset of ADC peripherals + using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). + (++) ADC clock disable + using the equivalent macro/functions as configuration step. + (+++) Example: + Into HAL_ADC_MspDeInit() (recommended code location) or with + other device clock parameters configuration: + (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; + (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock) + (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + + (#) ADC pins configuration + (++) Disable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_DISABLE() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Disable the NVIC for ADC + using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + + (#) Optionally, in case of usage of DMA: + (++) Deinitialize the DMA + using function HAL_DMA_Init(). + (++) Disable the NVIC for DMA + using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + + [..] + + *** Callback registration *** + ============================================= + [..] + + The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_ADC_RegisterCallback() + to register an interrupt callback. + [..] + + Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + [..] + + By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() + or @ref HAL_ADC_Init() function. + [..] + + When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ + +#define ADC_CFGR_FIELDS_1 (ADC_CFGR_RES | ADC_CFGR_ALIGN |\ + ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ + ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ + ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL) /*!< ADC_CFGR fields of parameters that can + be updated when no regular conversion is on-going */ + +/* Timeout values for ADC operations (enable settling time, */ +/* disable settling time, ...). */ +/* Values defined to be higher than worst cases: low clock frequency, */ +/* maximum prescalers. */ +#define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */ +#define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */ + +/* Timeout to wait for current conversion on going to be completed. */ +/* Timeout fixed to longest ADC conversion possible, for 1 channel: */ +/* - maximum sampling time (640.5 adc_clk) */ +/* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */ +/* - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio) */ +/* - ADC oversampling ratio 256 */ +/* Calculation: 653 * 4096 * 256 CPU clock cycles max */ +/* Unit: cycles of CPU clock. */ +#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */ + + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief ADC Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC. + (+) De-initialize the ADC. +@endverbatim + * @{ + */ + +/** + * @brief Initialize the ADC peripheral and regular group according to + * parameters specified in structure "ADC_InitTypeDef". + * @note As prerequisite, ADC clock must be configured at RCC top level + * (refer to description of RCC configuration for ADC + * in header of this file). + * @note Possibility to update parameters on the fly: + * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when + * coming from ADC state reset. Following calls to this function can + * be used to reconfigure some parameters of ADC_InitTypeDef + * structure on the fly, without modifying MSP configuration. If ADC + * MSP has to be modified again, HAL_ADC_DeInit() must be called + * before HAL_ADC_Init(). + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_InitTypeDef". + * @note This function configures the ADC within 2 scopes: scope of entire + * ADC and scope of regular group. For parameters details, see comments + * of structure "ADC_InitTypeDef". + * @note Parameters related to common ADC registers (ADC clock mode) are set + * only if all ADCs are disabled. + * If this is not the case, these common parameters setting are + * bypassed without error reporting: it can be the intended behaviour in + * case of update of a parameter of ADC_InitTypeDef on the fly, + * without disabling the other ADCs. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmp_cfgr; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + __IO uint32_t wait_loop_index = 0UL; + + /* Check ADC handle */ + if (hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); + assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); + assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); + assert_param(IS_ADC_SAMPLINGMODE(hadc->Init.SamplingMode)); + assert_param(IS_ADC_CONVERSIONDATAMGT(hadc->Init.ConversionDataManagement)); + assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); + assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); + + if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + { + assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + + if (hadc->Init.DiscontinuousConvMode == ENABLE) + { + assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); + } + } + + /* DISCEN and CONT bits cannot be set at the same time */ + assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); + + /* Actions performed only if ADC is coming from state reset: */ + /* - Initialization of ADC MSP */ + if (hadc->State == HAL_ADC_STATE_RESET) + { +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + /* Init the ADC Callback settings */ + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ + hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ + hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ + hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */ + hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */ + hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */ + + if (hadc->MspInitCallback == NULL) + { + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Initialize Lock */ + hadc->Lock = HAL_UNLOCKED; + } + + /* - Exit from deep-power-down mode and ADC voltage regulator enable */ + if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) + { + /* Disable ADC deep power down mode */ + LL_ADC_DisableDeepPowerDown(hadc->Instance); + + /* System was in deep power down mode, calibration must + be relaunched or a previously saved calibration factor + re-applied once the ADC voltage regulator is enabled */ + } + + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) + { + /* Enable ADC internal voltage regulator */ + LL_ADC_EnableInternalRegulator(hadc->Instance); + + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + + /* Verification that ADC voltage regulator is correctly enabled, whether */ + /* or not ADC is coming from state reset (if any potential problem of */ + /* clocking, voltage regulator would not be enabled). */ + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed and if there is no conversion on going on regular */ + /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ + /* called to update a parameter on the fly). */ + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + + if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + && (tmp_adc_is_conversion_on_going_regular == 0UL) + ) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Configuration of common ADC parameters */ + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - clock configuration */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) + { + /* Reset configuration of ADC common register CCR: */ + /* */ + /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */ + /* according to adc->Init.ClockPrescaler. It selects the clock */ + /* source and sets the clock division factor. */ + /* */ + /* Some parameters of this register are not reset, since they are set */ + /* by other functions and must be kept in case of usage of this */ + /* function on the fly (update of a parameter of ADC_InitTypeDef */ + /* without needing to reconfigure all other ADC groups/channels */ + /* parameters): */ + /* - when multimode feature is available, multimode-related */ + /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ + /* HAL_ADCEx_MultiModeConfigChannel() ) */ + /* - internal measurement paths: Vbat, temperature sensor, Vref */ + /* (set into HAL_ADC_ConfigChannel() or */ + /* HAL_ADCEx_InjectedConfigChannel() ) */ + LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); + } + } + + /* Configuration of ADC: */ + /* - resolution Init.Resolution */ + /* - data alignment Init.DataAlign */ + /* - external trigger to start conversion Init.ExternalTrigConv */ + /* - external trigger polarity Init.ExternalTrigConvEdge */ + /* - continuous conversion mode Init.ContinuousConvMode */ + /* - overrun Init.Overrun */ + /* - discontinuous mode Init.DiscontinuousConvMode */ + /* - discontinuous mode channel count Init.NbrOfDiscConversion */ + tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + hadc->Init.Overrun | + hadc->Init.DataAlign | + hadc->Init.Resolution | + ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); + + if (hadc->Init.DiscontinuousConvMode == ENABLE) + { + tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); + } + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) + | hadc->Init.ExternalTrigConvEdge + ); + } + + /* Update Configuration Register CFGR */ + MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr); + + /* Configuration of sampling mode */ + MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular and injected groups: */ + /* - DMA continuous request Init.DMAContinuousRequests */ + /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ + /* - Oversampling parameters Init.Oversampling */ + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + if ((tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) + { + tmp_cfgr = ( + ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + hadc->Init.ConversionDataManagement); + + MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr); + + if (hadc->Init.OversamplingMode == ENABLE) + { + assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); + assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); + assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); + assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); + + /* Configuration of Oversampler: */ + /* - Oversampling Ratio */ + /* - Right bit shift */ + /* - Triggered mode */ + /* - Oversampling mode (continued/resumed) */ + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS | + ADC_CFGR2_TROVS | + ADC_CFGR2_ROVSM, + ADC_CFGR2_ROVSE | + hadc->Init.Oversampling.Ratio | + hadc->Init.Oversampling.RightBitShift | + hadc->Init.Oversampling.TriggeredMode | + hadc->Init.Oversampling.OversamplingStopReset + ); + } + else + { + /* Disable ADC oversampling scope on ADC group regular */ + CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); + } + + } + + /* Configuration of regular group sequencer: */ + /* - if scan mode is disabled, regular channels sequence length is set to */ + /* 0x00: 1 channel converted (channel on regular rank 1) */ + /* Parameter "NbrOfConversion" is discarded. */ + /* Note: Scan mode is not present by hardware on this device, but */ + /* emulated by software for alignment over all STM32 devices. */ + /* - if scan mode is enabled, regular channels sequence length is set to */ + /* parameter "NbrOfConversion". */ + + if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) + { + /* Set number of ranks in regular group sequencer */ + MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); + } + else + { + CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); + } + + /* Initialize the ADC state */ + /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Deinitialize the ADC peripheral registers to their default reset + * values, with deinitialization of the ADC MSP. + * @note For devices with several ADCs: reset of ADC common registers is done + * only if all ADCs sharing the same common group are disabled. + * (function "HAL_ADC_MspDeInit()" is also called under the same conditions: + * all ADC instances use the same core clock at RCC level, disabling + * the core clock reset all ADC instances). + * If this is not the case, reset of these common parameters reset is + * bypassed without error reporting: it can be the intended behavior in + * case of reset of a single ADC while the other ADCs sharing the same + * common group is still running. + * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: + * this saves more power by reducing leakage currents + * and is particularly interesting before entering MCU low-power modes. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check ADC handle */ + if (hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); + + /* Stop potential conversion on going */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); + + /* Disable ADC peripheral if conversions are effectively stopped */ + /* Flush register JSQR: reset the queue sequencer when injected */ + /* queue sequencer is enabled and ADC disabled. */ + /* The software and hardware triggers of the injected sequence are both */ + /* internally disabled just after the completion of the last valid */ + /* injected sequence. */ + SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + } + + /* Note: HAL ADC deInit is done independently of ADC conversion stop */ + /* and disable return status. In case of status fail, attempt to */ + /* perform deinitialization anyway and it is up user code in */ + /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */ + /* system RCC hard reset. */ + + /* ========== Reset ADC registers ========== */ + /* Reset register IER */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | + ADC_IT_JQOVF | ADC_IT_OVR | + ADC_IT_JEOS | ADC_IT_JEOC | + ADC_IT_EOS | ADC_IT_EOC | + ADC_IT_EOSMP | ADC_IT_RDY)); + + /* Reset register ISR */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | + ADC_FLAG_JQOVF | ADC_FLAG_OVR | + ADC_FLAG_JEOS | ADC_FLAG_JEOC | + ADC_FLAG_EOS | ADC_FLAG_EOC | + ADC_FLAG_EOSMP | ADC_FLAG_RDY)); + + /* Reset register CR */ + /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, + ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set": + no direct reset applicable. + Update CR register to reset value where doable by software */ + CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); + SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); + + /* Reset register CFGR */ + CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS); + SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); + + /* Reset register CFGR2 */ + CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | + ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE); + + /* Reset register SMPR1 */ + CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS); + + /* Reset register SMPR2 */ + CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | + ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | + ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10); + + /* Reset register TR1 */ + CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1); + + /* Reset register TR2 */ + CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2); + + /* Reset register TR3 */ + CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3); + + /* Reset register SQR1 */ + CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | + ADC_SQR1_SQ1 | ADC_SQR1_L); + + /* Reset register SQR2 */ + CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | + ADC_SQR2_SQ6 | ADC_SQR2_SQ5); + + /* Reset register SQR3 */ + CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | + ADC_SQR3_SQ11 | ADC_SQR3_SQ10); + + /* Reset register SQR4 */ + CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); + + /* Register JSQR was reset when the ADC was disabled */ + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable*/ + + /* Reset register OFR1 */ + CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); + /* Reset register OFR2 */ + CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); + /* Reset register OFR3 */ + CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); + /* Reset register OFR4 */ + CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4); + + /* Reset registers JDR1, JDR2, JDR3, JDR4 */ + /* bits in access mode read only, no direct reset applicable*/ + + /* Reset register AWD2CR */ + CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH); + + /* Reset register AWD3CR */ + CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH); + + /* Reset register DIFSEL */ + CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL); + + /* Reset register CALFACT */ + CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); + + + /* ========== Reset common ADC registers ========== */ + + /* Software is allowed to change common parameters only when all the other + ADCs are disabled. */ + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) + { + /* Reset configuration of ADC common register CCR: + - clock mode: CKMODE, PRESCEN + - multimode related parameters (when this feature is available): MDMA, + DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API) + - internal measurement paths: Vbat, temperature sensor, Vref (set into + HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() ) + */ + ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc); + + /* ========== Hard reset ADC peripheral ========== */ + /* Performs a global reset of the entire ADC peripherals instances */ + /* sharing the same common ADC instance: ADC state is forced to */ + /* a similar state as after device power-on. */ + /* Note: A possible implementation is to add RCC bus reset of ADC */ + /* (for example, using macro */ + /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */ + /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hadc->MspDeInitCallback(hadc); +#else + /* DeInit the low level hardware */ + HAL_ADC_MspDeInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Reset injected channel configuration parameters */ + hadc->InjectionConfig.ContextQueue = 0; + hadc->InjectionConfig.ChannelCount = 0; + + /* Set ADC state */ + hadc->State = HAL_ADC_STATE_RESET; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Initialize the ADC MSP. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspInit must be implemented in the user file. + */ +} + +/** + * @brief DeInitialize the ADC MSP. + * @param hadc ADC handle + * @note All ADC instances use the same core clock at RCC level, disabling + * the core clock reset all ADC instances). + * @retval None + */ +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspDeInit must be implemented in the user file. + */ +} + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ADC Callback + * To be used instead of the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID + * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, + pADC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = pCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = pCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = pCallback; + break; + + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + hadc->InjectedConvCpltCallback = pCallback; + break; + + case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : + hadc->InjectedQueueOverflowCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : + hadc->LevelOutOfWindow2Callback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : + hadc->LevelOutOfWindow3Callback = pCallback; + break; + + case HAL_ADC_END_OF_SAMPLING_CB_ID : + hadc->EndOfSamplingCallback = pCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a ADC Callback + * ADC callback is redirected to the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID + * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = HAL_ADC_ErrorCallback; + break; + + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; + break; + + case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : + hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : + hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : + hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; + break; + + case HAL_ADC_END_OF_SAMPLING_CB_ID : + hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions + * @brief ADC IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of regular group. + (+) Stop conversion of regular group. + (+) Poll for conversion complete on regular group. + (+) Poll for conversion event. + (+) Get result of regular channel conversion. + (+) Start conversion of regular group and enable interruptions. + (+) Stop conversion of regular group and disable interruptions. + (+) Handle ADC interrupt request + (+) Start conversion of regular group and enable DMA transfer. + (+) Stop conversion of regular group and disable ADC DMA transfer. +@endverbatim + * @{ + */ + +/** + * @brief Enable ADC, start conversion of regular group. + * @note Interruptions enabled in this function: None. + * @note Case of multimode enabled (when multimode feature is available): + * if ADC is Slave, ADC is enabled but conversion is not started, + * if ADC is master, ADC is enabled and multimode conversion is started. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmpADC_Master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Perform ADC enable and conversion start if no conversion is on going */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + +#if defined(ADC_MULTIMODE_SUPPORT) + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) + { + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Set ADC error code */ + /* Check if a conversion is on going on ADC group injected */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to regular conversions only */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Clear ADC group regular conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Case of multimode enabled (when multimode feature is available): */ + /* - if ADC is slave and dual regular conversions are enabled, ADC is */ + /* enabled only (conversion is not started), */ + /* - if ADC is master, ADC is enabled and conversion is started. */ +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) + { + /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + else + { + /* ADC instance is a multimode slave instance with multimode regular conversions enabled */ + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + /* if Master ADC JAUTO bit is set, update Slave State in setting + HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + } +#else + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); +#endif /* ADC_MULTIMODE_SUPPORT */ + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + } + else + { + tmp_hal_status = HAL_BUSY; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected channels in + * case of auto_injection mode), disable ADC peripheral. + * @note: ADC peripheral disable is forcing stop of potential + * conversion on injected group. If injected group is under use, it + * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going, on ADC groups regular and injected */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* 2. Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Wait for regular group conversion to be completed. + * @note ADC conversion flags EOS (end of sequence) and EOC (end of + * conversion) are cleared by this function, with an exception: + * if low power feature "LowPowerAutoWait" is enabled, flags are + * not cleared to not interfere with this feature until data register + * is read using function HAL_ADC_GetValue(). + * @note This function cannot be used in a particular setup: ADC configured + * in DMA mode and polling for end of each conversion (ADC init + * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + * In this case, DMA resets the flag EOC and polling cannot be + * performed on each conversion. Nevertheless, polling can still + * be performed on the complete sequence (ADC init + * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). + * @param hadc ADC handle + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t tmp_Flag_End; + uint32_t tmp_cfgr; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmpADC_Master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* If end of conversion selected to end of sequence conversions */ + if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) + { + tmp_Flag_End = ADC_FLAG_EOS; + } + /* If end of conversion selected to end of unitary conversion */ + else /* ADC_EOC_SINGLE_CONV */ + { + /* Verification that ADC configuration is compliant with polling for */ + /* each conversion: */ + /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + /* several ranks and polling for end of each conversion. */ + /* For code simplicity sake, this particular case is generalized to */ + /* ADC configured in DMA mode and and polling for end of each conversion. */ +#if defined(ADC_MULTIMODE_SUPPORT) + if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) + { + /* Check ADC DMA mode in independent mode on ADC group regular */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + return HAL_ERROR; + } + else + { + tmp_Flag_End = (ADC_FLAG_EOC); + } + } + else + { + /* Check ADC DMA mode in multimode on ADC group regular */ + if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) + { + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + return HAL_ERROR; + } + else + { + tmp_Flag_End = (ADC_FLAG_EOC); + } + } +#else + /* Check ADC DMA mode */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + return HAL_ERROR; + } + else + { + tmp_Flag_End = (ADC_FLAG_EOC); + } +#endif /* ADC_MULTIMODE_SUPPORT */ + } + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Wait until End of unitary conversion or sequence conversions flag is raised */ + while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + { + /* Check if timeout is disabled (set to infinite wait) */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + } + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + && (hadc->Init.ContinuousConvMode == DISABLE) + ) + { + /* Check whether end of sequence is reached */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + } + + /* Get relevant register CFGR in ADC instance of ADC master or slave */ + /* in function of multimode state (for devices with multimode */ + /* available). */ +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) + { + /* Retrieve handle ADC CFGR register */ + tmp_cfgr = READ_REG(hadc->Instance->CFGR); + } + else + { + /* Retrieve Master ADC CFGR register */ + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + tmp_cfgr = READ_REG(tmpADC_Master->CFGR); + } +#else + /* Retrieve handle ADC CFGR register */ + tmp_cfgr = READ_REG(hadc->Instance->CFGR); +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Clear polled flag */ + if (tmp_Flag_End == ADC_FLAG_EOS) + { + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); + } + else + { + /* Clear end of conversion EOC flag of regular group if low power feature */ + /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ + /* until data register is read using function HAL_ADC_GetValue(). */ + if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) + { + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Poll for ADC event. + * @param hadc ADC handle + * @param EventType the ADC event type. + * This parameter can be one of the following values: + * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event + * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on + * all STM32 series) + * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on + * all STM32 series) + * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on + * all STM32 series) + * @arg @ref ADC_OVR_EVENT ADC Overrun event + * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event + * @param Timeout Timeout value in millisecond. + * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. + * Indeed, the latter is reset only if hadc->Init.Overrun field is set + * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten + * by a new converted data as soon as OVR is cleared. + * To reset OVR flag once the preserved data is retrieved, the user can resort + * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EVENT_TYPE(EventType)); + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Check selected event flag */ + while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + { + /* Check if timeout is disabled (set to infinite wait) */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + } + + switch (EventType) + { + /* End Of Sampling event */ + case ADC_EOSMP_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); + + /* Clear the End Of Sampling flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); + + break; + + /* Analog watchdog (level out of window) event */ + /* Note: In case of several analog watchdog enabled, if needed to know */ + /* which one triggered and on which ADCx, test ADC state of analog watchdog */ + /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ + /* For example: */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */ + + /* Check analog watchdog 1 flag */ + case ADC_AWD_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); + + break; + + /* Check analog watchdog 2 flag */ + case ADC_AWD2_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); + + break; + + /* Check analog watchdog 3 flag */ + case ADC_AWD3_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); + + break; + + /* Injected context queue overflow event */ + case ADC_JQOVF_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); + + /* Set ADC error code to Injected context queue overflow */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); + + /* Clear ADC Injected context queue overflow flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); + + break; + + /* Overrun event */ + default: /* Case ADC_OVR_EVENT */ + /* If overrun is set to overwrite previous data, overrun event is not */ + /* considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + } + else + { + /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN + otherwise, data register is potentially overwritten by new converted data as soon + as OVR is cleared. */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + break; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enable ADC, start conversion of regular group with interruption. + * @note Interruptions enabled in this function according to initialization + * setting : EOC (end of conversion), EOS (end of sequence), + * OVR overrun. + * Each of these interruptions has its dedicated callback function. + * @note Case of multimode enabled (when multimode feature is available): + * HAL_ADC_Start_IT() must be called for ADC Slave first, then for + * ADC Master. + * For ADC Slave, ADC is enabled only (conversion is not started). + * For ADC Master, ADC is enabled and multimode conversion is started. + * @note To guarantee a proper reset of all interruptions once all the needed + * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure + * a correct stop of the IT-based conversions. + * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling + * interruption. If required (e.g. in case of oversampling with trigger + * mode), the user must: + * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) + * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) + * before calling HAL_ADC_Start_IT(). + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmpADC_Master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Perform ADC enable and conversion start if no conversion is on going */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + +#if defined(ADC_MULTIMODE_SUPPORT) + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) + { + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Set ADC error code */ + /* Check if a conversion is on going on ADC group injected */ + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) + { + /* Reset ADC error code fields related to regular conversions only */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Clear ADC group regular conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Disable all interruptions before enabling the desired ones */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); + + /* Enable ADC end of conversion interrupt */ + switch (hadc->Init.EOCSelection) + { + case ADC_EOC_SEQ_CONV: + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); + break; + /* case ADC_EOC_SINGLE_CONV */ + default: + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); + break; + } + + /* Enable ADC overrun interrupt */ + /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is + ADC_IT_OVR enabled; otherwise data overwrite is considered as normal + behavior and no CPU time is lost for a non-processed interruption */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + } + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Case of multimode enabled (when multimode feature is available): */ + /* - if ADC is slave and dual regular conversions are enabled, ADC is */ + /* enabled only (conversion is not started), */ + /* - if ADC is master, ADC is enabled and conversion is started. */ +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) + { + /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + + /* Enable as well injected interruptions in case + HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This + allows to start regular and injected conversions when JAUTO is + set with a single call to HAL_ADC_Start_IT() */ + switch (hadc->Init.EOCSelection) + { + case ADC_EOC_SEQ_CONV: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); + break; + /* case ADC_EOC_SINGLE_CONV */ + default: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + break; + } + } + + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + else + { + /* ADC instance is a multimode slave instance with multimode regular conversions enabled */ + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + /* if Master ADC JAUTO bit is set, Slave injected interruptions + are enabled nevertheless (for same reason as above) */ + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) + { + /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit + and in resetting HAL_ADC_STATE_INJ_EOC bit */ + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + /* Next, set Slave injected interruptions */ + switch (hadc->Init.EOCSelection) + { + case ADC_EOC_SEQ_CONV: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); + break; + /* case ADC_EOC_SINGLE_CONV */ + default: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + break; + } + } + } +#else + /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + + /* Enable as well injected interruptions in case + HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This + allows to start regular and injected conversions when JAUTO is + set with a single call to HAL_ADC_Start_IT() */ + switch (hadc->Init.EOCSelection) + { + case ADC_EOC_SEQ_CONV: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); + break; + /* case ADC_EOC_SINGLE_CONV */ + default: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + break; + } + } + + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); +#endif /* ADC_MULTIMODE_SUPPORT */ + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + + } + else + { + tmp_hal_status = HAL_BUSY; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable interrution of + * end-of-conversion, disable ADC peripheral. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going, on ADC groups regular and injected */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable ADC end of conversion interrupt for regular group */ + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); + + /* 2. Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Enable ADC, start conversion of regular group and transfer result through DMA. + * @note Interruptions enabled in this function: + * overrun (if applicable), DMA half transfer, DMA transfer complete. + * Each of these interruptions has its dedicated callback function. + * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() + * is designed for single-ADC mode only. For multimode, the dedicated + * HAL_ADCEx_MultiModeStart_DMA() function must be used. + * @param hadc ADC handle + * @param pData Destination Buffer address. + * @param Length Number of data to be transferred from ADC peripheral to memory + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) +{ + HAL_StatusTypeDef tmp_hal_status; +#if defined(ADC_MULTIMODE_SUPPORT) + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* ADC_MULTIMODE_SUPPORT */ + uint32_t length_bytes; + DMA_NodeConfTypeDef node_conf; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Perform ADC enable and conversion start if no conversion is on going */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Process locked */ + __HAL_LOCK(hadc); + +#if defined(ADC_MULTIMODE_SUPPORT) + /* Ensure that multimode regular conversions are not enabled. */ + /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ + if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) +#endif /* ADC_MULTIMODE_SUPPORT */ + { + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + +#if defined(ADC_MULTIMODE_SUPPORT) + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) + { + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Check if a conversion is on going on ADC group injected */ + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) + { + /* Reset ADC error code fields related to regular conversions only */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */ + /* ADC start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC */ + /* operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* With DMA, overrun event is always considered as an error even if + hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, + ADC_IT_OVR is enabled. */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Enable ADC DMA mode */ + SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); + + /* Check linkedlist mode */ + if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL)) + { + /* Length should be converted to number of bytes */ + if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK) + { + return HAL_ERROR; + } + + /* Length should be converted to number of bytes */ + if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + /* Word -> Bytes */ + length_bytes = Length * 4U; + } + else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + /* Halfword -> Bytes */ + length_bytes = Length * 2U; + } + else /* Bytes */ + { + /* Same size already expressed in Bytes */ + length_bytes = Length; + } + + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)length_bytes; + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \ + (uint32_t)&hadc->Instance->DR; + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle); + } + else + { + return HAL_ERROR; + } + } + else + { + /* Length should be converted to number of bytes */ + if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + /* Word -> Bytes */ + length_bytes = Length * 4U; + } + else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + /* Halfword -> Bytes */ + length_bytes = Length * 2U; + } + else /* Bytes */ + { + /* Same size already expressed in Bytes */ + length_bytes = Length; + } + + /* Start the DMA channel */ + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, \ + length_bytes); + } + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + + } +#if defined(ADC_MULTIMODE_SUPPORT) + else + { + tmp_hal_status = HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } +#endif /* ADC_MULTIMODE_SUPPORT */ + } + else + { + tmp_hal_status = HAL_BUSY; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable ADC DMA transfer, disable + * ADC peripheral. + * @note: ADC peripheral disable is forcing stop of potential + * conversion on ADC group injected. If ADC group injected is under use, it + * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. + * @note Case of multimode enabled (when multimode feature is available): + * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. + * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential ADC group regular conversion on going */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ + CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); + + /* Disable the DMA channel (in case of DMA in circular mode or stop */ + /* while DMA transfer is on going) */ + if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) + { + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmp_hal_status != HAL_OK) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + } + } + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + + /* 2. Disable the ADC peripheral */ + /* Update "tmp_hal_status" only if DMA channel disabling passed, */ + /* to keep in memory a potential failing status. */ + if (tmp_hal_status == HAL_OK) + { + tmp_hal_status = ADC_Disable(hadc); + } + else + { + (void)ADC_Disable(hadc); + } + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Get ADC regular group conversion result. + * @note Reading register DR automatically clears ADC flag EOC + * (ADC group regular end of unitary conversion). + * @note This function does not clear ADC flag EOS + * (ADC group regular end of sequence conversion). + * Occurrence of flag EOS rising: + * - If sequencer is composed of 1 rank, flag EOS is equivalent + * to flag EOC. + * - If sequencer is composed of several ranks, during the scan + * sequence flag EOC only is raised, at the end of the scan sequence + * both flags EOC and EOS are raised. + * To clear this flag, either use function: + * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming + * model polling: @ref HAL_ADC_PollForConversion() + * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). + * @param hadc ADC handle + * @retval ADC group regular conversion data + */ +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Note: EOC flag is not cleared here by software because automatically */ + /* cleared by hardware when reading register DR. */ + + /* Return ADC converted value */ + return hadc->Instance->DR; +} + +/** + * @brief Start ADC conversion sampling phase of regular group + * @note: This function should only be called to start sampling when + * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling + * mode has been selected + * - @ref ADC_SOFTWARE_START has been selected as trigger source + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Start sampling */ + SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop ADC conversion sampling phase of regular group and start conversion + * @note: This function should only be called to stop sampling when + * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling + * mode has been selected + * - @ref ADC_SOFTWARE_START has been selected as trigger source + * - after sampling has been started using @ref HAL_ADC_StartSampling. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Start sampling */ + CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handle ADC interrupt request. + * @param hadc ADC handle + * @retval None + */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) +{ + uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */ + uint32_t tmp_isr = hadc->Instance->ISR; + uint32_t tmp_ier = hadc->Instance->IER; + uint32_t tmp_adc_inj_is_trigger_source_sw_start; + uint32_t tmp_adc_reg_is_trigger_source_sw_start; + uint32_t tmp_cfgr; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmpADC_Master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); + + /* ========== Check End of Sampling flag for ADC group regular ========== */ + if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) + { + /* Update state machine on end of sampling status if not in error state */ + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); + } + + /* End Of Sampling callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->EndOfSamplingCallback(hadc); +#else + HAL_ADCEx_EndOfSamplingCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); + } + + /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */ + if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || + (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) + { + /* Update state machine on conversion status if not in error state */ + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + } + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going */ + /* to disable interruption. */ + if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + { + /* Get relevant register CFGR in ADC instance of ADC master or slave */ + /* in function of multimode state (for devices with multimode */ + /* available). */ +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + ) + { + /* check CONT bit directly in handle ADC CFGR register */ + tmp_cfgr = READ_REG(hadc->Instance->CFGR); + } + else + { + /* else need to check Master ADC CONT bit */ + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + tmp_cfgr = READ_REG(tmpADC_Master->CFGR); + } +#else + tmp_cfgr = READ_REG(hadc->Instance->CFGR); +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Carry on if continuous mode is disabled */ + if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) + { + /* If End of Sequence is reached, disable interrupts */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Disable ADC end of sequence conversion interrupt */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + } + + /* Conversion complete callback */ + /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ + /* to determine if conversion has been triggered from EOC or EOS, */ + /* possibility to use: */ + /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear regular group conversion flag */ + /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ + /* conversion flags clear induces the release of the preserved data.*/ + /* Therefore, if the preserved data value is needed, it must be */ + /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); + } + + /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */ + if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || + (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))) + { + /* Update state machine on conversion status if not in error state */ + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + } + + /* Retrieve ADC configuration */ + tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); + tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); + /* Get relevant register CFGR in ADC instance of ADC master or slave */ + /* in function of multimode state (for devices with multimode */ + /* available). */ +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + ) + { + tmp_cfgr = READ_REG(hadc->Instance->CFGR); + } + else + { + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + tmp_cfgr = READ_REG(tmpADC_Master->CFGR); + } +#else + tmp_cfgr = READ_REG(hadc->Instance->CFGR); +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Disable interruption if no further conversion upcoming by injected */ + /* external trigger or by automatic injected conversion with regular */ + /* group having no further conversion upcoming (same conditions as */ + /* regular group interruption disabling above), */ + /* and if injected scan sequence is completed. */ + if (tmp_adc_inj_is_trigger_source_sw_start != 0UL) + { + if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) || + ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && + (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))) + { + /* If End of Sequence is reached, disable interrupts */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) + { + /* Particular case if injected contexts queue is enabled: */ + /* when the last context has been fully processed, JSQR is reset */ + /* by the hardware. Even if no injected conversion is planned to come */ + /* (queue empty, triggers are ignored), it can start again */ + /* immediately after setting a new context (JADSTART is still set). */ + /* Therefore, state of HAL ADC injected group is kept to busy. */ + if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) + { + /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ + /* JADSTART==0 (no conversion on going) */ + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Disable ADC end of sequence conversion interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + } + } + + /* Injected Conversion complete callback */ + /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to + if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or + if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether + interruption has been triggered by end of conversion or end of + sequence. */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->InjectedConvCpltCallback(hadc); +#else + HAL_ADCEx_InjectedConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear injected group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); + } + + /* ========== Check Analog watchdog 1 flag ========== */ + if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Level out of window 1 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindowCallback(hadc); +#else + HAL_ADC_LevelOutOfWindowCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); + } + + /* ========== Check analog watchdog 2 flag ========== */ + if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Level out of window 2 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindow2Callback(hadc); +#else + HAL_ADCEx_LevelOutOfWindow2Callback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); + } + + /* ========== Check analog watchdog 3 flag ========== */ + if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Level out of window 3 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindow3Callback(hadc); +#else + HAL_ADCEx_LevelOutOfWindow3Callback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); + } + + /* ========== Check Overrun flag ========== */ + if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) + { + /* If overrun is set to overwrite previous data (default setting), */ + /* overrun event is not considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + /* Exception for usage with DMA overrun event always considered as an */ + /* error. */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + overrun_error = 1UL; + } + else + { + /* Check DMA configuration */ +#if defined(ADC_MULTIMODE_SUPPORT) + if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT) + { + /* Multimode (when feature is available) is enabled, + Common Control Register MDMA bits must be checked. */ + if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) + { + overrun_error = 1UL; + } + } + else +#endif /* ADC_MULTIMODE_SUPPORT */ + { + /* Multimode not set or feature not available or ADC independent */ + if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL) + { + overrun_error = 1UL; + } + } + } + + if (overrun_error == 1UL) + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + + /* Error callback */ + /* Note: In case of overrun, ADC conversion data is preserved until */ + /* flag OVR is reset. */ + /* Therefore, old ADC conversion data can be retrieved in */ + /* function "HAL_ADC_ErrorCallback()". */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + + /* ========== Check Injected context queue overflow flag ========== */ + if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) + { + /* Change ADC state to overrun state */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); + + /* Set ADC error code to Injected context queue overflow */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); + + /* Clear the Injected context queue overflow flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); + + /* Injected context queue overflow callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->InjectedQueueOverflowCallback(hadc); +#else + HAL_ADCEx_InjectedQueueOverflowCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + +} + +/** + * @brief Conversion complete callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Conversion DMA half-transfer callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Analog watchdog 1 callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. + */ +} + +/** + * @brief ADC error callback in non-blocking mode + * (ADC conversion with interruption or transfer by DMA). + * @note In case of error due to overrun when using ADC with DMA transfer + * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): + * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". + * - If needed, restart a new ADC conversion using function + * "HAL_ADC_Start_DMA()" + * (this function is also clearing overrun flag) + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ErrorCallback must be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels on regular group + (+) Configure the analog watchdog + +@endverbatim + * @{ + */ + +/** + * @brief Configure a channel to be assigned to ADC group regular. + * @note In case of usage of internal measurement channels: + * Vbat/VrefInt/TempSensor. + * These internal paths can be disabled using function + * HAL_ADC_DeInit(). + * @note Possibility to update parameters on the fly: + * This function initializes channel into ADC group regular, + * following calls to this function can be used to reconfigure + * some parameters of structure "ADC_ChannelConfTypeDef" on the fly, + * without resetting the ADC. + * The setting of these parameters is conditioned to ADC state: + * Refer to comments of structure "ADC_ChannelConfTypeDef". + * @param hadc ADC handle + * @param pConfig Structure of ADC channel assigned to ADC group regular. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmpOffsetShifted; + uint32_t tmp_config_internal_channel; + __IO uint32_t wait_loop_index = 0UL; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank)); + assert_param(IS_ADC_SAMPLE_TIME(pConfig->SamplingTime)); + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfig->SingleDiff)); + assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset)); + + /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is + ignored (considered as reset) */ + assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); + + /* Verification of channel number */ + if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) + { + assert_param(IS_ADC_CHANNEL(hadc, pConfig->Channel)); + } + else + { + assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - Channel number */ + /* - Channel rank */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Set ADC group regular sequence: channel on the selected scan sequence rank */ + LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - Channel sampling time */ + /* - Channel offset */ + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + if ((tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) + { + /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ + if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) + { + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5); + + /* Set ADC sampling time common configuration */ + LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); + } + else + { + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime); + + /* Set ADC sampling time common configuration */ + LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); + } + + /* Configure the offset: offset enable/disable, channel, offset value */ + + /* Shift the offset with respect to the selected ADC resolution. */ + /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ + tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset); + + if (pConfig->OffsetNumber != ADC_OFFSET_NONE) + { + /* Set ADC selected offset number */ + LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted); + + assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign)); + assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation)); + /* Set ADC selected offset sign & saturation */ + LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign); + LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber, + (pConfig->OffsetSaturation == ENABLE) ? + LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE); + } + else + { + /* Scan each offset register to check if the selected channel is targeted. */ + /* If this is the case, the corresponding offset number is disabled. */ + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) + { + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); + } + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) + { + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); + } + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) + { + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); + } + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) + { + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); + } + } + } + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - Single or differential mode */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + /* Set mode single-ended or differential input of the selected ADC channel */ + LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff); + + /* Configuration of differential mode */ + if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) + { + /* Set sampling time of the selected ADC channel */ + /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, + (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( + (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel) + + 1UL) & 0x1FUL)), + pConfig->SamplingTime); + } + + } + + /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ + /* If internal channel selected, enable dedicated internal buffers and */ + /* paths. */ + /* Note: these internal measurement paths can be disabled using */ + /* HAL_ADC_DeInit(). */ + + if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) + { + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + + /* If the requested internal measurement path has already been enabled, */ + /* bypass the configuration processing. */ + if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) + { + if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); + + /* Delay for temperature sensor stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + } + else if ((pConfig->Channel == ADC_CHANNEL_VBAT) + && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) + { + if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); + } + } + else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) + && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) + { + if (ADC_VREFINT_INSTANCE(hadc)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); + } + } + else if (pConfig->Channel == ADC_CHANNEL_VDDCORE) + { + if (ADC_VDDCORE_INSTANCE(hadc)) + { + LL_ADC_SetPathInternalChAdd(hadc->Instance, LL_ADC_PATH_INTERNAL_VDDCORE); + } + } + else + { + /* nothing to do */ + } + } + } + + /* If a conversion is on going on regular group, no update on regular */ + /* channel could be done on neither of the channel configuration structure */ + /* parameters. */ + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Configure the analog watchdog. + * @note Possibility to update parameters on the fly: + * This function initializes the selected analog watchdog, successive + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting + * the ADC. + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_AnalogWDGConfTypeDef". + * @note On this STM32 series, analog watchdog thresholds can be modified + * while ADC conversion is on going. + * In this case, some constraints must be taken into account: + * the programmed threshold values are effective from the next + * ADC EOC (end of unitary conversion). + * Considering that registers write delay may happen due to + * bus activity, this might cause an uncertainty on the + * effective timing of the new programmed threshold values. + * @param hadc ADC handle + * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmp_awd_high_threshold_shifted; + uint32_t tmp_awd_low_threshold_shifted; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber)); + assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode)); + assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(pAnalogWDGConfig->FilteringConfig)); + assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode)); + + if ((pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || + (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || + (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) + { + assert_param(IS_ADC_CHANNEL(hadc, pAnalogWDGConfig->Channel)); + } + + /* Verify thresholds range */ + if (hadc->Init.OversamplingMode == ENABLE) + { + /* Case of oversampling enabled: depending on ratio and shift configuration, + analog watchdog thresholds can be higher than ADC resolution. + Verify if thresholds are within maximum thresholds range. */ + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold)); + } + else + { + /* Verify if thresholds are within the selected ADC resolution */ + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on ADC groups regular and injected: */ + /* - Analog watchdog channels */ + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + if ((tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) + { + /* Analog watchdog configuration */ + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + { + /* Configuration of analog watchdog: */ + /* - Set the analog watchdog enable mode: one or overall group of */ + /* channels, on groups regular and-or injected. */ + switch (pAnalogWDGConfig->WatchdogMode) + { + case ADC_ANALOGWATCHDOG_SINGLE_REG: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, + __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, + LL_ADC_GROUP_REGULAR)); + break; + + case ADC_ANALOGWATCHDOG_SINGLE_INJEC: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, + __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, + LL_ADC_GROUP_INJECTED)); + break; + + case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, + __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, + LL_ADC_GROUP_REGULAR_INJECTED)); + break; + + case ADC_ANALOGWATCHDOG_ALL_REG: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG); + break; + + case ADC_ANALOGWATCHDOG_ALL_INJEC: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ); + break; + + case ADC_ANALOGWATCHDOG_ALL_REGINJEC: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); + break; + + default: /* ADC_ANALOGWATCHDOG_NONE */ + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE); + break; + } + + /* Set the filtering configuration */ + MODIFY_REG(hadc->Instance->TR1, + ADC_TR1_AWDFILT, + pAnalogWDGConfig->FilteringConfig); + + /* Update state, clear previous result related to AWD1 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD1(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if (pAnalogWDGConfig->ITMode == ENABLE) + { + LL_ADC_EnableIT_AWD1(hadc->Instance); + } + else + { + LL_ADC_DisableIT_AWD1(hadc->Instance); + } + } + /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ + else + { + switch (pAnalogWDGConfig->WatchdogMode) + { + case ADC_ANALOGWATCHDOG_SINGLE_REG: + case ADC_ANALOGWATCHDOG_SINGLE_INJEC: + case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: + /* Update AWD by bitfield to keep the possibility to monitor */ + /* several channels by successive calls of this function. */ + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + { + SET_BIT(hadc->Instance->AWD2CR, + (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL))); + } + else + { + SET_BIT(hadc->Instance->AWD3CR, + (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL))); + } + break; + + case ADC_ANALOGWATCHDOG_ALL_REG: + case ADC_ANALOGWATCHDOG_ALL_INJEC: + case ADC_ANALOGWATCHDOG_ALL_REGINJEC: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, + pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); + break; + + default: /* ADC_ANALOGWATCHDOG_NONE */ + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); + break; + } + + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + { + /* Update state, clear previous result related to AWD2 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD2(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if (pAnalogWDGConfig->ITMode == ENABLE) + { + LL_ADC_EnableIT_AWD2(hadc->Instance); + } + else + { + LL_ADC_DisableIT_AWD2(hadc->Instance); + } + } + /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ + else + { + /* Update state, clear previous result related to AWD3 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD3(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if (pAnalogWDGConfig->ITMode == ENABLE) + { + LL_ADC_EnableIT_AWD3(hadc->Instance); + } + else + { + LL_ADC_DisableIT_AWD3(hadc->Instance); + } + } + } + + } + + /* Analog watchdog thresholds configuration */ + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + { + /* Shift the offset with respect to the selected ADC resolution: */ + /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ + /* are set to 0. */ + tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold); + tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold); + } + /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */ + else + { + /* Shift the offset with respect to the selected ADC resolution: */ + /* Thresholds have to be left-aligned on bit 7, the LSB (right bits) */ + /* are set to 0. */ + tmp_awd_high_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold); + tmp_awd_low_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold); + } + + /* Set ADC analog watchdog thresholds value of both thresholds high and low */ + LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted, + tmp_awd_low_threshold_shifted); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions + * @brief ADC Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral state and errors functions ##### + =============================================================================== + [..] + This subsection provides functions to get in run-time the status of the + peripheral. + (+) Check the ADC state + (+) Check the ADC error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the ADC handle state. + * @note ADC state machine is managed by bitfields, ADC status must be + * compared with states bits. + * For example: + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " + * @param hadc ADC handle + * @retval ADC handle state (bitfield on 32 bits) + */ +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Return ADC handle state */ + return hadc->State; +} + +/** + * @brief Return the ADC error code. + * @param hadc ADC handle + * @retval ADC error code (bitfield on 32 bits) + */ +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + return hadc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @brief Stop ADC conversion. + * @param hadc ADC handle + * @param ConversionGroup ADC group regular and/or injected. + * This parameter can be one of the following values: + * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type. + * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type. + * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type. + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup) +{ + uint32_t tickstart; + uint32_t Conversion_Timeout_CPU_cycles = 0UL; + uint32_t conversion_group_reassigned = ConversionGroup; + uint32_t tmp_ADC_CR_ADSTART_JADSTART; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup)); + + /* Verification if ADC is not already stopped (on regular and injected */ + /* groups) to bypass this function if not needed. */ + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + if ((tmp_adc_is_conversion_on_going_regular != 0UL) + || (tmp_adc_is_conversion_on_going_injected != 0UL) + ) + { + /* Particular case of continuous auto-injection mode combined with */ + /* auto-delay mode. */ + /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */ + /* injected group stop ADC_CR_JADSTP). */ + /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */ + /* (see reference manual). */ + if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL) + && (hadc->Init.ContinuousConvMode == ENABLE) + && (hadc->Init.LowPowerAutoWait == ENABLE) + ) + { + /* Use stop of regular group */ + conversion_group_reassigned = ADC_REGULAR_GROUP; + + /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */ + while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) + { + if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL)) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + Conversion_Timeout_CPU_cycles ++; + } + + /* Clear JEOS */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS); + } + + /* Stop potential conversion on going on ADC group regular */ + if (conversion_group_reassigned != ADC_INJECTED_GROUP) + { + /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) + { + if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) + { + /* Stop ADC group regular conversion */ + LL_ADC_REG_StopConversion(hadc->Instance); + } + } + } + + /* Stop potential conversion on going on ADC group injected */ + if (conversion_group_reassigned != ADC_REGULAR_GROUP) + { + /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */ + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) + { + if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) + { + /* Stop ADC group injected conversion */ + LL_ADC_INJ_StopConversion(hadc->Instance); + } + } + } + + /* Selection of start and stop bits with respect to the regular or injected group */ + switch (conversion_group_reassigned) + { + case ADC_REGULAR_INJECTED_GROUP: + tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART); + break; + case ADC_INJECTED_GROUP: + tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART; + break; + /* Case ADC_REGULAR_GROUP only*/ + default: + tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART; + break; + } + + /* Wait for conversion effectively stopped */ + tickstart = HAL_GetTick(); + + while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) + { + if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + } + + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief Enable the selected ADC. + * @note Prerequisite condition to use this function: ADC must be disabled + * and voltage regulator must be enabled (done into HAL_ADC_Init()). + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) +{ + uint32_t tickstart; + __IO uint32_t wait_loop_index = 0UL; + + /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ + /* enabling phase not yet completed: flag ADC ready not yet set). */ + /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ + /* causes: ADC clock not running, ...). */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + /* Check if conditions to enable the ADC are fulfilled */ + if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART + | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + + /* Enable the ADC peripheral */ + LL_ADC_Enable(hadc->Instance); + + if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) + & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL) + { + /* Delay for temperature sensor buffer stabilization time */ + /* Note: Value LL_ADC_DELAY_TEMPSENSOR_STAB_US used instead of */ + /* LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US because needed */ + /* in case of ADC enable after a system wake up */ + /* from low power mode. */ + + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + + /* Wait for ADC effectively enabled */ + tickstart = HAL_GetTick(); + + while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + { + /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit + has been cleared (after a calibration), ADEN bit is reset by the + calibration logic. + The workaround is to continue setting ADEN until ADRDY is becomes 1. + Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this + 4 ADC clock cycle duration */ + /* Note: Test of ADC enabled required due to hardware constraint to */ + /* not enable ADC if already enabled. */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + LL_ADC_Enable(hadc->Instance); + } + + if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + } + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief Disable the selected ADC. + * @note Prerequisite condition to use this function: ADC conversions must be + * stopped. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) +{ + uint32_t tickstart; + const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); + + /* Verification if ADC is not already disabled: */ + /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ + /* disabled. */ + if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) + && (tmp_adc_is_disable_on_going == 0UL) + ) + { + /* Check if conditions to disable the ADC are fulfilled */ + if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) + { + /* Disable the ADC peripheral */ + LL_ADC_Disable(hadc->Instance); + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + + /* Wait for ADC effectively disabled */ + /* Get tick count */ + tickstart = HAL_GetTick(); + + while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) + { + if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + } + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief DMA transfer complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going */ + /* to disable interruption. */ + /* Is it the end of the regular sequence ? */ + if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) + { + /* Are conversions software-triggered ? */ + if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + { + /* Is CONT bit set ? */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) + { + /* CONT bit is not set, no more conversions expected */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + } + } + else + { + /* DMA End of Transfer interrupt was triggered but conversions sequence + is not over. If DMACFG is set to 0, conversions are stopped. */ + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL) + { + /* DMACFG bit is not set, conversions are stopped. */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else /* DMA and-or internal error occurred */ + { + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) + { + /* Call HAL ADC Error Callback function */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else + { + /* Call ADC DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } + } +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Half conversion callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvHalfCpltCallback(hadc); +#else + HAL_ADC_ConvHalfCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void ADC_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + + /* Set ADC error code to DMA error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); + + /* Error callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_adc_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_adc_ex.c new file mode 100644 index 00000000000..e5c4036e951 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_adc_ex.c @@ -0,0 +1,2447 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_adc_ex.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Converter (ADC) + * peripheral: + * + Peripheral Control functions + * Other functions (generic functions) are available in file + * "stm32h7rsxx_hal_adc.c". + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + [..] + (@) Sections "ADC peripheral features" and "How to use this driver" are + available in file of generic functions "stm32h7rsxx_hal_adc.c". + [..] + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup ADCEx ADCEx + * @brief ADC Extended HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants + * @{ + */ + +#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\ + ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\ + ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can + be updated anytime once the ADC is enabled */ + +/* Fixed timeout value for ADC calibration. */ +/* Fixed timeout value for ADC calibration. */ +/* Values defined to be higher than worst cases: low clock frequency, */ +/* maximum prescalers. */ +/* Ex of profile low frequency : f_ADC at 0.125 Mhz (minimum value */ +/* according to Data sheet), calibration_time MAX = 165010 / f_ADC */ +/* 165010 / 125000 = 1.32s */ +/* At maximum CPU speed (480 MHz), this means */ +/* 1.32 * 480 MHz = 633600000 CPU cycles */ +#define ADC_CALIBRATION_TIMEOUT (633600000UL) /*!< ADC calibration time-out value */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions + * @{ + */ + +/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + + (+) Perform the ADC self-calibration for single or differential ending. + (+) Get calibration factors for single or differential ending. + (+) Set calibration factors for single or differential ending. + + (+) Start conversion of ADC group injected. + (+) Stop conversion of ADC group injected. + (+) Poll for conversion complete on ADC group injected. + (+) Get result of ADC group injected channel conversion. + (+) Start conversion of ADC group injected and enable interruptions. + (+) Stop conversion of ADC group injected and disable interruptions. + + (+) When multimode feature is available, start multimode and enable DMA transfer. + (+) Stop multimode and disable ADC DMA transfer. + (+) Get result of multimode conversion. + +@endverbatim + * @{ + */ + +/** + * @brief Perform an ADC automatic self-calibration + * Calibration prerequisite: ADC must be disabled (execute this + * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). + * @param hadc ADC handle + * @param SingleDiff Selection of single-ended or differential input + * This parameter can be one of the following values: + * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended + * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) +{ + HAL_StatusTypeDef tmp_hal_status; + __IO uint32_t wait_loop_index = 0UL; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Calibration prerequisite: ADC must be disabled. */ + + /* Disable the ADC (if not already disabled) */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Start ADC calibration in mode single-ended or differential */ + LL_ADC_StartCalibration(hadc->Instance, SingleDiff); + + /* Wait for calibration completion */ + while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) + { + wait_loop_index++; + if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Note: No need to update variable "tmp_hal_status" here: already set */ + /* to state "HAL_ERROR" by function disabling the ADC. */ + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Get the calibration factor. + * @param hadc ADC handle. + * @param SingleDiff This parameter can be only: + * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended + * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended + * @retval Calibration value. + */ +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); + + /* Return the selected ADC calibration value */ + return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff); +} + +/** + * @brief Set the calibration factor to overwrite automatic conversion result. + * ADC must be enabled and no conversion is ongoing. + * @param hadc ADC handle + * @param SingleDiff This parameter can be only: + * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended + * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended + * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) + * @retval HAL state + */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, + uint32_t CalibrationFactor) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); + assert_param(IS_ADC_CALFACT(CalibrationFactor)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Verification of hardware constraints before modifying the calibration */ + /* factors register: ADC must be enabled, no conversion on going. */ + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + + if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) + && (tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) + { + /* Set the selected ADC calibration value */ + LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor); + } + else + { + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + /* Update ADC error code */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + /* Update ADC state machine to error */ + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Enable ADC, start conversion of injected group. + * @note Interruptions enabled in this function: None. + * @note Case of multimode enabled when multimode feature is available: + * HAL_ADCEx_InjectedStart() API must be called for ADC slave first, + * then for ADC master. + * For ADC slave, ADC is enabled only (conversion is not started). + * For ADC master, ADC is enabled and multimode conversion is started. + * @param hadc ADC handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + uint32_t tmp_config_injected_queue; +#if defined(ADC_MULTIMODE_SUPPORT) + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) + { + return HAL_BUSY; + } + else + { + /* In case of software trigger detection enabled, JQDIS must be set + (which can be done only if ADSTART and JADSTART are both cleared). + If JQDIS is not set at that point, returns an error + - since software trigger detection is disabled. User needs to + resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. + - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means + the queue is empty */ + tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); + + if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) + && (tmp_config_injected_queue == 0UL) + ) + { + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Check if a regular conversion is ongoing */ + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) + { + /* Reset ADC error code field related to injected conversions only */ + CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); + } + else + { + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); + +#if defined(ADC_MULTIMODE_SUPPORT) + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) + { + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Clear ADC group injected group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Enable conversion of injected group, if automatic injected conversion */ + /* is disabled. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Case of multimode enabled (when multimode feature is available): */ + /* if ADC is slave, */ + /* - ADC is enabled only (conversion is not started), */ + /* - if multimode only concerns regular conversion, ADC is enabled */ + /* and conversion is started. */ + /* If ADC is master or independent, */ + /* - ADC is enabled and conversion is started. */ +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + ) + { + /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ + if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) + { + LL_ADC_INJ_StartConversion(hadc->Instance); + } + } + else + { + /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } +#else + if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) + { + /* Start ADC group injected conversion */ + LL_ADC_INJ_StartConversion(hadc->Instance); + } +#endif /* ADC_MULTIMODE_SUPPORT */ + + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + + /* Return function status */ + return tmp_hal_status; + } +} + +/** + * @brief Stop conversion of injected channels. Disable ADC peripheral if + * no regular conversion is on going. + * @note If ADC must be disabled and if conversion is on going on + * regular group, function HAL_ADC_Stop must be used to stop both + * injected and regular groups, and disable the ADC. + * @note If injected group mode auto-injection is enabled, + * function HAL_ADC_Stop must be used. + * @note In case of multimode enabled (when multimode feature is available), + * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave. + * For ADC master, conversion is stopped and ADC is disabled. + * For ADC slave, ADC is disabled only (conversion stop of ADC master + * has already stopped conversion of ADC slave). + * @param hadc ADC handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going on injected group only. */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); + + /* Disable ADC peripheral if injected conversions are effectively stopped */ + /* and if no conversion on regular group is on-going */ + if (tmp_hal_status == HAL_OK) + { + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* 2. Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + /* Conversion on injected group is stopped, but ADC not disabled since */ + /* conversion on regular group is still running. */ + else + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Wait for injected group conversion to be completed. + * @param hadc ADC handle + * @param Timeout Timeout value in millisecond. + * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is + * checked and cleared depending on AUTDLY bit status. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t tmp_flag_end; + uint32_t tmp_adc_inj_is_trigger_source_sw_start; + uint32_t tmp_adc_reg_is_trigger_source_sw_start; + uint32_t tmp_cfgr; +#if defined(ADC_MULTIMODE_SUPPORT) + const ADC_TypeDef *tmpADC_Master; + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* If end of sequence selected */ + if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) + { + tmp_flag_end = ADC_FLAG_JEOS; + } + else /* end of conversion selected */ + { + tmp_flag_end = ADC_FLAG_JEOC; + } + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait until End of Conversion or Sequence flag is raised */ + while ((hadc->Instance->ISR & tmp_flag_end) == 0UL) + { + /* Check if timeout is disabled (set to infinite wait) */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->ISR & tmp_flag_end) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + } + + /* Retrieve ADC configuration */ + tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); + tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); + /* Get relevant register CFGR in ADC instance of ADC master or slave */ + /* in function of multimode state (for devices with multimode */ + /* available). */ +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + ) + { + tmp_cfgr = READ_REG(hadc->Instance->CFGR); + } + else + { + tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); + tmp_cfgr = READ_REG(tmpADC_Master->CFGR); + } +#else + tmp_cfgr = READ_REG(hadc->Instance->CFGR); +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger or by automatic injected conversion */ + /* from group regular. */ + if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || + ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && + ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && + (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) + { + /* Check whether end of sequence is reached */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) + { + /* Particular case if injected contexts queue is enabled: */ + /* when the last context has been fully processed, JSQR is reset */ + /* by the hardware. Even if no injected conversion is planned to come */ + /* (queue empty, triggers are ignored), it can start again */ + /* immediately after setting a new context (JADSTART is still set). */ + /* Therefore, state of HAL ADC injected group is kept to busy. */ + if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + } + } + + /* Clear polled flag */ + if (tmp_flag_end == ADC_FLAG_JEOS) + { + /* Clear end of sequence JEOS flag of injected group if low power feature */ + /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */ + /* For injected groups, no new conversion will start before JEOS is */ + /* cleared. */ + if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) + { + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); + } + } + else + { + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + } + + /* Return API HAL status */ + return HAL_OK; +} + +/** + * @brief Enable ADC, start conversion of injected group with interruption. + * @note Interruptions enabled in this function according to initialization + * setting : JEOC (end of conversion) or JEOS (end of sequence) + * @note Case of multimode enabled (when multimode feature is enabled): + * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, + * then for ADC master. + * For ADC slave, ADC is enabled only (conversion is not started). + * For ADC master, ADC is enabled and multimode conversion is started. + * @param hadc ADC handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + uint32_t tmp_config_injected_queue; +#if defined(ADC_MULTIMODE_SUPPORT) + uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) + { + return HAL_BUSY; + } + else + { + /* In case of software trigger detection enabled, JQDIS must be set + (which can be done only if ADSTART and JADSTART are both cleared). + If JQDIS is not set at that point, returns an error + - since software trigger detection is disabled. User needs to + resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. + - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means + the queue is empty */ + tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); + + if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) + && (tmp_config_injected_queue == 0UL) + ) + { + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Check if a regular conversion is ongoing */ + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) + { + /* Reset ADC error code field related to injected conversions only */ + CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); + } + else + { + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); + +#if defined(ADC_MULTIMODE_SUPPORT) + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit + - if ADC instance is master or if multimode feature is not available + - if multimode setting is disabled (ADC instance slave in independent mode) */ + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + ) + { + CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Clear ADC group injected group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Enable ADC Injected context queue overflow interrupt if this feature */ + /* is enabled. */ + if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL) + { + __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF); + } + + /* Enable ADC end of conversion interrupt */ + switch (hadc->Init.EOCSelection) + { + case ADC_EOC_SEQ_CONV: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); + break; + /* case ADC_EOC_SINGLE_CONV */ + default: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + break; + } + + /* Enable conversion of injected group, if automatic injected conversion */ + /* is disabled. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Case of multimode enabled (when multimode feature is available): */ + /* if ADC is slave, */ + /* - ADC is enabled only (conversion is not started), */ + /* - if multimode only concerns regular conversion, ADC is enabled */ + /* and conversion is started. */ + /* If ADC is master or independent, */ + /* - ADC is enabled and conversion is started. */ +#if defined(ADC_MULTIMODE_SUPPORT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + ) + { + /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ + if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) + { + LL_ADC_INJ_StartConversion(hadc->Instance); + } + } + else + { + /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ + SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); + } +#else + if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) + { + /* Start ADC group injected conversion */ + LL_ADC_INJ_StartConversion(hadc->Instance); + } +#endif /* ADC_MULTIMODE_SUPPORT */ + + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + + /* Return function status */ + return tmp_hal_status; + } +} + +/** + * @brief Stop conversion of injected channels, disable interruption of + * end-of-conversion. Disable ADC peripheral if no regular conversion + * is on going. + * @note If ADC must be disabled and if conversion is on going on + * regular group, function HAL_ADC_Stop must be used to stop both + * injected and regular groups, and disable the ADC. + * @note If injected group mode auto-injection is enabled, + * function HAL_ADC_Stop must be used. + * @note Case of multimode enabled (when multimode feature is available): + * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, + * then for ADC slave. + * For ADC master, conversion is stopped and ADC is disabled. + * For ADC slave, ADC is disabled only (conversion stop of ADC master + * has already stopped conversion of ADC slave). + * @note In case of auto-injection mode, HAL_ADC_Stop() must be used. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going on injected group only. */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); + + /* Disable ADC peripheral if injected conversions are effectively stopped */ + /* and if no conversion on the other group (regular group) is intended to */ + /* continue. */ + if (tmp_hal_status == HAL_OK) + { + /* Disable ADC end of conversion interrupt for injected channels */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF)); + + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* 2. Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + /* Conversion on injected group is stopped, but ADC not disabled since */ + /* conversion on regular group is still running. */ + else + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA. + * @note Multimode must have been previously configured using + * HAL_ADCEx_MultiModeConfigChannel() function. + * Interruptions enabled in this function: + * overrun, DMA half transfer, DMA transfer complete. + * Each of these interruptions has its dedicated callback function. + * @note State field of Slave ADC handle is not updated in this configuration: + * user should not rely on it for information related to Slave regular + * conversions. + * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) + * @param pData Destination Buffer address. + * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) +{ + HAL_StatusTypeDef tmp_hal_status; + ADC_HandleTypeDef tmp_hadc_slave; + ADC_Common_TypeDef *tmpADC_Common; + uint32_t length_bytes; + DMA_NodeConfTypeDef node_conf; + + /* Check the parameters */ + assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) + { + return HAL_BUSY; + } + else + { + /* Process locked */ + __HAL_LOCK(hadc); + + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); + ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); + + /* Set a temporary handle of the ADC slave associated to the ADC master */ + ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); + + if (tmp_hadc_slave.Instance == NULL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + + /* Enable the ADC peripherals: master and slave (in case if not already */ + /* enabled previously) */ + tmp_hal_status = ADC_Enable(hadc); + if (tmp_hal_status == HAL_OK) + { + tmp_hal_status = ADC_Enable(&tmp_hadc_slave); + } + + /* Start multimode conversion of ADCs pair */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP), + HAL_ADC_STATE_REG_BUSY); + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; + + /* Pointer to the common control register */ + tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Check linkedlist mode */ + if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL)) + { + /* Length should be converted to number of bytes */ + if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK) + { + return HAL_ERROR; + } + + /* Length should be converted to number of bytes */ + if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + /* Word -> Bytes */ + length_bytes = Length * 4U; + } + else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + /* Halfword -> Bytes */ + length_bytes = Length * 2U; + } + else /* Bytes */ + { + /* Same size already expressed in Bytes */ + length_bytes = Length; + } + + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)length_bytes; + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \ + (uint32_t)&tmpADC_Common->CDR; + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle); + } + else + { + return HAL_ERROR; + } + } + else + { + /* Length should be converted to number of bytes */ + if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + /* Word -> Bytes */ + length_bytes = Length * 4U; + } + else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + /* Halfword -> Bytes */ + length_bytes = Length * 2U; + } + else /* Bytes */ + { + /* Same size already expressed in Bytes */ + length_bytes = Length; + } + + /* Start the DMA channel */ + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, \ + length_bytes); + } + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + + /* Return function status */ + return tmp_hal_status; + } +} + +/** + * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral. + * @note Multimode is kept enabled after this function. MultiMode DMA bits + * (MDMA and DMACFG bits of common CCR register) are maintained. To disable + * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be + * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can + * resort to HAL_ADCEx_DisableMultiMode() API. + * @note In case of DMA configured in circular mode, function + * HAL_ADC_Stop_DMA() must be called after this function with handle of + * ADC slave, to properly disable the DMA channel. + * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + uint32_t tickstart; + ADC_HandleTypeDef tmp_hadc_slave; + uint32_t tmp_hadc_slave_conversion_on_going; + HAL_StatusTypeDef tmp_hadc_slave_disable_status; + + /* Check the parameters */ + assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential multimode conversion on going, on regular and injected groups */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); + ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); + + /* Set a temporary handle of the ADC slave associated to the ADC master */ + ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); + + if (tmp_hadc_slave.Instance == NULL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + + /* Procedure to disable the ADC peripheral: wait for conversions */ + /* effectively stopped (ADC master and ADC slave), then disable ADC */ + + /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ + tickstart = HAL_GetTick(); + + tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); + while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmp_hadc_slave_conversion_on_going == 1UL) + ) + { + if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); + if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmp_hadc_slave_conversion_on_going == 1UL) + ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + + tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); + } + + /* Disable the DMA channel (in case of DMA in circular mode or stop */ + /* while DMA transfer is on going) */ + /* Note: DMA channel of ADC slave should be stopped after this function */ + /* with HAL_ADC_Stop_DMA() API. */ + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmp_hal_status == HAL_ERROR) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + } + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + + /* 2. Disable the ADC peripherals: master and slave */ + /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ + /* memory a potential failing status. */ + if (tmp_hal_status == HAL_OK) + { + tmp_hadc_slave_disable_status = ADC_Disable(&tmp_hadc_slave); + if ((ADC_Disable(hadc) == HAL_OK) && + (tmp_hadc_slave_disable_status == HAL_OK)) + { + tmp_hal_status = HAL_OK; + } + } + else + { + /* In case of error, attempt to disable ADC master and slave without status assert */ + (void) ADC_Disable(hadc); + (void) ADC_Disable(&tmp_hadc_slave); + } + + /* Set ADC state (ADC master) */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration. + * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used) + * @retval The converted data values. + */ +uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc) +{ + const ADC_Common_TypeDef *tmpADC_Common; + + /* Check the parameters */ + assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */ + UNUSED(hadc); + + /* Pointer to the common control register */ + tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); + + /* Return the multi mode conversion value */ + return tmpADC_Common->CDR; +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @brief Get ADC injected group conversion result. + * @note Reading register JDRx automatically clears ADC flag JEOC + * (ADC group injected end of unitary conversion). + * @note This function does not clear ADC flag JEOS + * (ADC group injected end of sequence conversion) + * Occurrence of flag JEOS rising: + * - If sequencer is composed of 1 rank, flag JEOS is equivalent + * to flag JEOC. + * - If sequencer is composed of several ranks, during the scan + * sequence flag JEOC only is raised, at the end of the scan sequence + * both flags JEOC and EOS are raised. + * Flag JEOS must not be cleared by this function because + * it would not be compliant with low power features + * (feature low power auto-wait, not available on all STM32 series). + * To clear this flag, either use function: + * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming + * model polling: @ref HAL_ADCEx_InjectedPollForConversion() + * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). + * @param hadc ADC handle + * @param InjectedRank the converted ADC injected rank. + * This parameter can be one of the following values: + * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1 + * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2 + * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3 + * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4 + * @retval ADC group injected conversion data + */ +uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank) +{ + uint32_t tmp_jdr; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); + + /* Get ADC converted value */ + switch (InjectedRank) + { + case ADC_INJECTED_RANK_4: + tmp_jdr = hadc->Instance->JDR4; + break; + case ADC_INJECTED_RANK_3: + tmp_jdr = hadc->Instance->JDR3; + break; + case ADC_INJECTED_RANK_2: + tmp_jdr = hadc->Instance->JDR2; + break; + case ADC_INJECTED_RANK_1: + default: + tmp_jdr = hadc->Instance->JDR1; + break; + } + + /* Return ADC converted value */ + return tmp_jdr; +} + +/** + * @brief Injected conversion complete callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Injected context queue overflow callback. + * @note This callback is called if injected context queue is enabled + (parameter "QueueInjectedContext" in injected channel configuration) + and if a new injected context is set when queue is full (maximum 2 + contexts). + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file. + */ +} + +/** + * @brief Analog watchdog 2 callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file. + */ +} + +/** + * @brief Analog watchdog 3 callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file. + */ +} + + +/** + * @brief End Of Sampling callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file. + */ +} + +/** + * @brief Stop ADC conversion of regular group (and injected channels in + * case of auto_injection mode), disable ADC peripheral if no + * conversion is on going on injected group. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential regular conversion on going */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); + + /* Disable ADC peripheral if regular conversions are effectively stopped + and if no injected conversions are on-going */ + if (tmp_hal_status == HAL_OK) + { + /* Clear HAL_ADC_STATE_REG_BUSY bit */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* 2. Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + /* Conversion on injected group is stopped, but ADC not disabled since */ + /* conversion on regular group is still running. */ + else + { + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + + +/** + * @brief Stop ADC conversion of ADC groups regular and injected, + * disable interrution of end-of-conversion, + * disable ADC peripheral if no conversion is on going + * on injected group. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential regular conversion on going */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); + + /* Disable ADC peripheral if conversions are effectively stopped + and if no injected conversion is on-going */ + if (tmp_hal_status == HAL_OK) + { + /* Clear HAL_ADC_STATE_REG_BUSY bit */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + /* Disable all regular-related interrupts */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); + + /* 2. Disable ADC peripheral if no injected conversions are on-going */ + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + { + tmp_hal_status = ADC_Disable(hadc); + /* if no issue reported */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + else + { + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable ADC DMA transfer, disable + * ADC peripheral if no conversion is on going + * on injected group. + * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. + * For multimode (when multimode feature is available), + * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential regular conversion on going */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); + + /* Disable ADC peripheral if conversions are effectively stopped + and if no injected conversion is on-going */ + if (tmp_hal_status == HAL_OK) + { + /* Clear HAL_ADC_STATE_REG_BUSY bit */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ + CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); + + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ + /* while DMA transfer is on going) */ + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmp_hal_status != HAL_OK) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + } + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + + /* 2. Disable the ADC peripheral */ + /* Update "tmp_hal_status" only if DMA channel disabling passed, */ + /* to keep in memory a potential failing status. */ + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + { + if (tmp_hal_status == HAL_OK) + { + tmp_hal_status = ADC_Disable(hadc); + } + else + { + (void)ADC_Disable(hadc); + } + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + else + { + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected + * conversion is on-going. + * @note Multimode is kept enabled after this function. Multimode DMA bits + * (MDMA and DMACFG bits of common CCR register) are maintained. To disable + * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be + * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can + * resort to HAL_ADCEx_DisableMultiMode() API. + * @note In case of DMA configured in circular mode, function + * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of + * ADC slave, to properly disable the DMA channel. + * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + uint32_t tickstart; + ADC_HandleTypeDef tmp_hadc_slave; + uint32_t tmp_hadc_slave_conversion_on_going; + + /* Check the parameters */ + assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + + /* 1. Stop potential multimode conversion on going, on regular groups */ + tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Clear HAL_ADC_STATE_REG_BUSY bit */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); + ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); + + /* Set a temporary handle of the ADC slave associated to the ADC master */ + ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); + + if (tmp_hadc_slave.Instance == NULL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + + /* Procedure to disable the ADC peripheral: wait for conversions */ + /* effectively stopped (ADC master and ADC slave), then disable ADC */ + + /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ + tickstart = HAL_GetTick(); + + tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); + while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmp_hadc_slave_conversion_on_going == 1UL) + ) + { + if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); + if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmp_hadc_slave_conversion_on_going == 1UL) + ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + + tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); + } + + /* Disable the DMA channel (in case of DMA in circular mode or stop */ + /* while DMA transfer is on going) */ + /* Note: DMA channel of ADC slave should be stopped after this function */ + /* with HAL_ADCEx_RegularStop_DMA() API. */ + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmp_hal_status != HAL_OK) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + } + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + + /* 2. Disable the ADC peripherals: master and slave if no injected */ + /* conversion is on-going. */ + /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ + /* memory a potential failing status. */ + if (tmp_hal_status == HAL_OK) + { + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + { + tmp_hal_status = ADC_Disable(hadc); + if (tmp_hal_status == HAL_OK) + { + if (LL_ADC_INJ_IsConversionOngoing((&tmp_hadc_slave)->Instance) == 0UL) + { + tmp_hal_status = ADC_Disable(&tmp_hadc_slave); + } + } + } + + if (tmp_hal_status == HAL_OK) + { + /* Both Master and Slave ADC's could be disabled. Update Master State */ + /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */ + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); + } + else + { + /* injected (Master or Slave) conversions are still on-going, + no Master State change */ + } + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions + * @brief ADC Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels on injected group + (+) Configure multimode when multimode feature is available + (+) Enable or Disable Injected Queue + (+) Disable ADC voltage regulator + (+) Enter ADC deep-power-down mode + +@endverbatim + * @{ + */ + +/** + * @brief Configure a channel to be assigned to ADC group injected. + * @note Possibility to update parameters on the fly: + * This function initializes injected group, following calls to this + * function can be used to reconfigure some parameters of structure + * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC. + * The setting of these parameters is conditioned to ADC state: + * Refer to comments of structure "ADC_InjectionConfTypeDef". + * @note In case of usage of internal measurement channels: + * Vbat/VrefInt/TempSensor. + * These internal paths can be disabled using function + * HAL_ADC_DeInit(). + * @note Caution: For Injected Context Queue use, a context must be fully + * defined before start of injected conversion. All channels are configured + * consecutively for the same ADC instance. Therefore, the number of calls to + * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter + * InjectedNbrOfConversion for each context. + * - Example 1: If 1 context is intended to be used (or if there is no use of the + * Injected Queue Context feature) and if the context contains 3 injected ranks + * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be + * called once for each channel (i.e. 3 times) before starting a conversion. + * This function must not be called to configure a 4th injected channel: + * it would start a new context into context queue. + * - Example 2: If 2 contexts are intended to be used and each of them contains + * 3 injected ranks (InjectedNbrOfConversion = 3), + * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and + * for each context (3 channels x 2 contexts = 6 calls). Conversion can + * start once the 1st context is set, that is after the first three + * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly. + * @param hadc ADC handle + * @param pConfigInjected Structure of ADC injected group and ADC channel for + * injected group. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, + const ADC_InjectionConfTypeDef *pConfigInjected) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmp_offset_shifted; + uint32_t tmp_config_internal_channel; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + __IO uint32_t wait_loop_index = 0; + + uint32_t tmp_jsqr_context_queue_being_built = 0U; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime)); + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff)); + assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv)); + assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->QueueInjectedContext)); + assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge)); + assert_param(IS_ADC_EXTTRIGINJEC(pConfigInjected->ExternalTrigInjecConv)); + assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset)); + assert_param(IS_ADC_OFFSET_SIGN(pConfigInjected->InjectedOffsetSign)); + assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedOffsetSaturation)); + assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode)); + + if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + { + assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank)); + assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion)); + assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode)); + } + + + /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is + ignored (considered as reset) */ + assert_param(!((pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) + && (pConfigInjected->InjecOversamplingMode == ENABLE))); + + /* JDISCEN and JAUTO bits can't be set at the same time */ + assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE) + && (pConfigInjected->AutoInjectedConv == ENABLE))); + + /* DISCEN and JAUTO bits can't be set at the same time */ + assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE))); + + /* Verification of channel number */ + if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) + { + assert_param(IS_ADC_CHANNEL(hadc, pConfigInjected->InjectedChannel)); + } + else + { + assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfigInjected->InjectedChannel)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Configuration of injected group sequencer: */ + /* Hardware constraint: Must fully define injected context register JSQR */ + /* before make it entering into injected sequencer queue. */ + /* */ + /* - if scan mode is disabled: */ + /* * Injected channels sequence length is set to 0x00: 1 channel */ + /* converted (channel on injected rank 1) */ + /* Parameter "InjectedNbrOfConversion" is discarded. */ + /* * Injected context register JSQR setting is simple: register is fully */ + /* defined on one call of this function (for injected rank 1) and can */ + /* be entered into queue directly. */ + /* - if scan mode is enabled: */ + /* * Injected channels sequence length is set to parameter */ + /* "InjectedNbrOfConversion". */ + /* * Injected context register JSQR setting more complex: register is */ + /* fully defined over successive calls of this function, for each */ + /* injected channel rank. It is entered into queue only when all */ + /* injected ranks have been set. */ + /* Note: Scan mode is not present by hardware on this device, but used */ + /* by software for alignment over all STM32 devices. */ + + if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || + (pConfigInjected->InjectedNbrOfConversion == 1U)) + { + /* Configuration of context register JSQR: */ + /* - number of ranks in injected group sequencer: fixed to 1st rank */ + /* (scan mode disabled, only rank 1 used) */ + /* - external trigger to start conversion */ + /* - external trigger polarity */ + /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */ + + if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) + { + /* Enable external trigger if trigger selection is different of */ + /* software start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + { + tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) + | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | pConfigInjected->ExternalTrigInjecConvEdge + ); + } + else + { + tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)); + } + + MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_jsqr_context_queue_being_built); + /* For debug and informative reasons, hadc handle saves JSQR setting */ + hadc->InjectionConfig.ContextQueue = tmp_jsqr_context_queue_being_built; + + } + } + else + { + /* Case of scan mode enabled, several channels to set into injected group */ + /* sequencer. */ + /* */ + /* Procedure to define injected context register JSQR over successive */ + /* calls of this function, for each injected channel rank: */ + /* 1. Start new context and set parameters related to all injected */ + /* channels: injected sequence length and trigger. */ + + /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */ + /* call of the context under setting */ + if (hadc->InjectionConfig.ChannelCount == 0U) + { + /* Initialize number of channels that will be configured on the context */ + /* being built */ + hadc->InjectionConfig.ChannelCount = pConfigInjected->InjectedNbrOfConversion; + /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel() + call, this context will be written in JSQR register at the last call. + At this point, the context is merely reset */ + hadc->InjectionConfig.ContextQueue = 0x00000000U; + + /* Configuration of context register JSQR: */ + /* - number of ranks in injected group sequencer */ + /* - external trigger to start conversion */ + /* - external trigger polarity */ + + /* Enable external trigger if trigger selection is different of */ + /* software start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + { + tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U) + | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | pConfigInjected->ExternalTrigInjecConvEdge + ); + } + else + { + tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U)); + } + + } + + /* 2. Continue setting of context under definition with parameter */ + /* related to each channel: channel rank sequence */ + /* Clear the old JSQx bits for the selected rank */ + tmp_jsqr_context_queue_being_built &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank); + + /* Set the JSQx bits for the selected rank */ + tmp_jsqr_context_queue_being_built |= ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank); + + /* Decrease channel count */ + hadc->InjectionConfig.ChannelCount--; + + /* 3. tmp_jsqr_context_queue_being_built is fully built for this HAL_ADCEx_InjectedConfigChannel() + call, aggregate the setting to those already built during the previous + HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */ + hadc->InjectionConfig.ContextQueue |= tmp_jsqr_context_queue_being_built; + + /* 4. End of context setting: if this is the last channel set, then write context + into register JSQR and make it enter into queue */ + if (hadc->InjectionConfig.ChannelCount == 0U) + { + MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); + } + } + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on injected group: */ + /* - Injected context queue: Queue disable (active context is kept) or */ + /* enable (context decremented, up to 2 contexts queued) */ + /* - Injected discontinuous mode: can be enabled only if auto-injected */ + /* mode is disabled. */ + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* If auto-injected mode is disabled: no constraint */ + if (pConfigInjected->AutoInjectedConv == DISABLE) + { + MODIFY_REG(hadc->Instance->CFGR, + ADC_CFGR_JQM | ADC_CFGR_JDISCEN, + ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext) | + ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode)); + } + /* If auto-injected mode is enabled: Injected discontinuous setting is */ + /* discarded. */ + else + { + MODIFY_REG(hadc->Instance->CFGR, + ADC_CFGR_JQM | ADC_CFGR_JDISCEN, + ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext)); + } + + } + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular and injected groups: */ + /* - Automatic injected conversion: can be enabled if injected group */ + /* external triggers are disabled. */ + /* - Channel sampling time */ + /* - Channel offset */ + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + + if ((tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) + { + /* If injected group external triggers are disabled (set to injected */ + /* software start): no constraint */ + if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) + || (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) + { + if (pConfigInjected->AutoInjectedConv == ENABLE) + { + SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); + } + else + { + CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); + } + } + /* If Automatic injected conversion was intended to be set and could not */ + /* due to injected group external triggers enabled, error is reported. */ + else + { + if (pConfigInjected->AutoInjectedConv == ENABLE) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + else + { + CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); + } + } + + if (pConfigInjected->InjecOversamplingMode == ENABLE) + { + assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio)); + assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift)); + + /* JOVSE must be reset in case of triggered regular mode */ + assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) + == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS))); + + /* Configuration of Injected Oversampler: */ + /* - Oversampling Ratio */ + /* - Right bit shift */ + + /* Enable OverSampling mode */ + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_JOVSE | + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS, + ADC_CFGR2_JOVSE | + pConfigInjected->InjecOversampling.Ratio | + pConfigInjected->InjecOversampling.RightBitShift + ); + } + else + { + /* Disable Regular OverSampling */ + CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE); + } + + /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ + if (pConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5) + { + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5); + + /* Set ADC sampling time common configuration */ + LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); + } + else + { + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel, + pConfigInjected->InjectedSamplingTime); + + /* Set ADC sampling time common configuration */ + LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); + } + + /* Configure the offset: offset enable/disable, channel, offset value */ + + /* Shift the offset with respect to the selected ADC resolution. */ + /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ + tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset); + + if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) + { + /* Set ADC selected offset number */ + LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel, + tmp_offset_shifted); + + /* Set ADC selected offset sign & saturation */ + LL_ADC_SetOffsetSign(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedOffsetSign); + LL_ADC_SetOffsetSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber, + (pConfigInjected->InjectedOffsetSaturation == ENABLE) ? + LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE); + } + else + { + /* Scan each offset register to check if the selected channel is targeted. */ + /* If this is the case, the corresponding offset number is disabled. */ + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) + { + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); + } + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) + { + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); + } + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) + { + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); + } + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) + { + LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); + } + } + + } + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - Single or differential mode */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + /* Set mode single-ended or differential input of the selected ADC channel */ + LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff); + + /* Configuration of differential mode */ + /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ + if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) + { + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, + (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( + (__LL_ADC_CHANNEL_TO_DECIMAL_NB( + (uint32_t)pConfigInjected->InjectedChannel) + + 1UL) & 0x1FUL)), + pConfigInjected->InjectedSamplingTime); + } + + } + + /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ + /* internal measurement paths enable: If internal channel selected, */ + /* enable dedicated internal buffers and path. */ + /* Note: these internal measurement paths can be disabled using */ + /* HAL_ADC_DeInit(). */ + + if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel)) + { + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + + /* If the requested internal measurement path has already been enabled, */ + /* bypass the configuration processing. */ + if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) + && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) + { + if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); + + /* Delay for temperature sensor stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) + * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + } + else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) + && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) + { + if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); + } + } + else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) + && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) + { + if (ADC_VREFINT_INSTANCE(hadc)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); + } + } + else if (pConfigInjected->InjectedChannel == ADC_CHANNEL_VDDCORE) + { + if (ADC_VDDCORE_INSTANCE(hadc)) + { + LL_ADC_SetPathInternalChAdd(hadc->Instance, LL_ADC_PATH_INTERNAL_VDDCORE); + } + } + else + { + /* nothing to do */ + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Enable ADC multimode and configure multimode parameters + * @note Possibility to update parameters on the fly: + * This function initializes multimode parameters, following + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_MultiModeTypeDef" on the fly, without resetting + * the ADCs. + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_MultiModeTypeDef". + * @note To move back configuration from multimode to single mode, ADC must + * be reset (using function HAL_ADC_Init() ). + * @param hadc Master ADC handle + * @param pMultimode Structure of ADC multimode configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + ADC_Common_TypeDef *tmpADC_Common; + ADC_HandleTypeDef tmp_hadc_slave; + uint32_t tmp_hadc_slave_conversion_on_going; + + /* Check the parameters */ + assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_MULTIMODE(pMultimode->Mode)); + if (pMultimode->Mode != ADC_MODE_INDEPENDENT) + { + assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode)); + assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); + ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); + + ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); + + if (tmp_hadc_slave.Instance == NULL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - Multimode DMA configuration */ + /* - Multimode DMA mode */ + tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); + if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + && (tmp_hadc_slave_conversion_on_going == 0UL)) + { + /* Pointer to the common control register */ + tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); + + /* If multimode is selected, configure all multimode parameters. */ + /* Otherwise, reset multimode parameters (can be used in case of */ + /* transition from multimode to independent mode). */ + if (pMultimode->Mode != ADC_MODE_INDEPENDENT) + { + MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, + pMultimode->DMAAccessMode | + ADC_CCR_MULTI_DMACONTREQ((hadc->Init.ConversionDataManagement & ADC_CFGR_DMACFG) + >> ADC_CFGR_DMACFG_Pos)); + + /* Parameters that can be updated only when ADC is disabled: */ + /* - Multimode mode selection */ + /* - Multimode delay */ + /* Note: Delay range depends on selected resolution: */ + /* from 1 to 12 clock cycles for 12 bits */ + /* from 1 to 10 clock cycles for 10 bits, */ + /* from 1 to 8 clock cycles for 8 bits */ + /* from 1 to 6 clock cycles for 6 bits */ + /* If a higher delay is selected, it will be clipped to maximum delay */ + /* range */ + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) + { + MODIFY_REG(tmpADC_Common->CCR, + ADC_CCR_DUAL | + ADC_CCR_DELAY, + pMultimode->Mode | + pMultimode->TwoSamplingDelay + ); + } + } + else /* ADC_MODE_INDEPENDENT */ + { + CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); + + /* Parameters that can be updated only when ADC is disabled: */ + /* - Multimode mode selection */ + /* - Multimode delay */ + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) + { + CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); + } + } + } + /* If one of the ADC sharing the same common group is enabled, no update */ + /* could be done on neither of the multimode structure parameters. */ + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @brief Enable Injected Queue + * @note This function resets CFGR register JQDIS bit in order to enable the + * Injected Queue. JQDIS can be written only when ADSTART and JDSTART + * are both equal to 0 to ensure that no regular nor injected + * conversion is ongoing. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + + /* Parameter can be set only if no conversion is on-going */ + if ((tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) + { + CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); + + /* Update state, clear previous result related to injected queue overflow */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); + + tmp_hal_status = HAL_OK; + } + else + { + tmp_hal_status = HAL_ERROR; + } + + return tmp_hal_status; +} + +/** + * @brief Disable Injected Queue + * @note This function sets CFGR register JQDIS bit in order to disable the + * Injected Queue. JQDIS can be written only when ADSTART and JDSTART + * are both equal to 0 to ensure that no regular nor injected + * conversion is ongoing. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + uint32_t tmp_adc_is_conversion_on_going_regular; + uint32_t tmp_adc_is_conversion_on_going_injected; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); + + /* Parameter can be set only if no conversion is on-going */ + if ((tmp_adc_is_conversion_on_going_regular == 0UL) + && (tmp_adc_is_conversion_on_going_injected == 0UL) + ) + { + LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE); + tmp_hal_status = HAL_OK; + } + else + { + tmp_hal_status = HAL_ERROR; + } + + return tmp_hal_status; +} + +/** + * @brief Disable ADC voltage regulator. + * @note Disabling voltage regulator allows to save power. This operation can + * be carried out only when ADC is disabled. + * @note To enable again the voltage regulator, the user is expected to + * resort to HAL_ADC_Init() API. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + LL_ADC_DisableInternalRegulator(hadc->Instance); + tmp_hal_status = HAL_OK; + } + else + { + tmp_hal_status = HAL_ERROR; + } + + return tmp_hal_status; +} + +/** + * @brief Enter ADC deep-power-down mode + * @note This mode is achieved in setting DEEPPWD bit and allows to save power + * in reducing leakage currents. It is particularly interesting before + * entering stop modes. + * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the + * ADC voltage regulator. This means that this API encompasses + * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal + * calibration is lost. + * @note To exit the ADC deep-power-down mode, the user is expected to + * resort to HAL_ADC_Init() API as well as to relaunch a calibration + * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously + * saved calibration factor. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + LL_ADC_EnableDeepPowerDown(hadc->Instance); + tmp_hal_status = HAL_OK; + } + else + { + tmp_hal_status = HAL_ERROR; + } + + return tmp_hal_status; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cec.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cec.c new file mode 100644 index 00000000000..029aea49048 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cec.c @@ -0,0 +1,997 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_cec.c + * @author MCD Application Team + * @brief CEC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the High Definition Multimedia Interface + * Consumer Electronics Control Peripheral (CEC). + * + Initialization and de-initialization function + * + IO operation function + * + Peripheral Control function + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The CEC HAL driver can be used as follow: + + (#) Declare a CEC_HandleTypeDef handle structure. + (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API: + (##) Enable the CEC interface clock. + (##) CEC pins configuration: + (+++) Enable the clock for the CEC GPIOs. + (+++) Configure these CEC pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT() + and HAL_CEC_Receive_IT() APIs): + (+++) Configure the CEC interrupt priority. + (+++) Enable the NVIC CEC IRQ handle. + (+++) The specific CEC interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit + and receive process. + + (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in + in case of Bit Rising Error, Error-Bit generation conditions, device logical + address and Listen mode in the hcec Init structure. + + (#) Initialize the CEC registers by calling the HAL_CEC_Init() API. + + [..] + (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_CEC_MspInit() API. + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_CEC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback() + to register an interrupt callback. + + Function HAL_CEC_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : Tx Transfer completed callback. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : CEC MspInit. + (+) MspDeInitCallback : CEC MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks + HAL_CEC_RegisterRxCpltCallback(). + + Use function HAL_CEC_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : Tx Transfer completed callback. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : CEC MspInit. + (+) MspDeInitCallback : CEC MspDeInit. + + For callback HAL_CEC_RxCpltCallback use dedicated unregister callback : + HAL_CEC_UnRegisterRxCpltCallback(). + + By default, after the HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET + all callbacks are set to the corresponding weak functions : + examples HAL_CEC_TxCpltCallback() , HAL_CEC_RxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_CEC_Init()/ HAL_CEC_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_CEC_Init() / HAL_CEC_DeInit() + keep and use the user MspInit/MspDeInit functions (registered beforehand) + + Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only. + Exception done MspInit/MspDeInit callbacks that can be registered/unregistered + in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_CEC_RegisterCallback() before calling HAL_CEC_DeInit() + or HAL_CEC_Init() function. + + When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup CEC CEC + * @brief HAL CEC module driver + * @{ + */ +#ifdef HAL_CEC_MODULE_ENABLED +#if defined (CEC) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup CEC_Private_Constants CEC Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CEC_Private_Functions CEC Private Functions + * @{ + */ +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup CEC_Exported_Functions CEC Exported Functions + * @{ + */ + +/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the CEC + (+) The following parameters need to be configured: + (++) SignalFreeTime + (++) Tolerance + (++) BRERxStop (RX stopped or not upon Bit Rising Error) + (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error) + (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error) + (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error) + (++) SignalFreeTimeOption (SFT Timer start definition) + (++) OwnAddress (CEC device address) + (++) ListenMode + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CEC mode according to the specified + * parameters in the CEC_InitTypeDef and creates the associated handle . + * @param hcec CEC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) +{ + /* Check the CEC handle allocation */ + if ((hcec == NULL) || (hcec->Init.RxBuffer == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); + assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime)); + assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance)); + assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop)); + assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen)); + assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen)); + assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen)); + assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption)); + assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode)); + assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress)); + +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) + if (hcec->gState == HAL_CEC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcec->Lock = HAL_UNLOCKED; + + hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hcec->MspInitCallback == NULL) + { + hcec->MspInitCallback = HAL_CEC_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hcec->MspInitCallback(hcec); + } +#else + if (hcec->gState == HAL_CEC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcec->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK */ + HAL_CEC_MspInit(hcec); + } +#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ + + hcec->gState = HAL_CEC_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_CEC_DISABLE(hcec); + + /* Write to CEC Control Register */ + hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \ + hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | \ + hcec->Init.BroadcastMsgNoErrorBitGen | \ + hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \ + hcec->Init.ListenMode; + + /* Enable the following CEC Transmission/Reception interrupts as + * well as the following CEC Transmission/Reception Errors interrupts + * Rx Byte Received IT + * End of Reception IT + * Rx overrun + * Rx bit rising error + * Rx short bit period error + * Rx long bit period error + * Rx missing acknowledge + * Tx Byte Request IT + * End of Transmission IT + * Tx Missing Acknowledge IT + * Tx-Error IT + * Tx-Buffer Underrun IT + * Tx arbitration lost */ + __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND | + CEC_IER_TX_ALL_ERR); + + /* Enable the CEC Peripheral */ + __HAL_CEC_ENABLE(hcec); + + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + hcec->gState = HAL_CEC_STATE_READY; + hcec->RxState = HAL_CEC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the CEC peripheral + * @param hcec CEC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) +{ + /* Check the CEC handle allocation */ + if (hcec == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); + + hcec->gState = HAL_CEC_STATE_BUSY; + +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) + if (hcec->MspDeInitCallback == NULL) + { + hcec->MspDeInitCallback = HAL_CEC_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hcec->MspDeInitCallback(hcec); + +#else + /* DeInit the low level hardware */ + HAL_CEC_MspDeInit(hcec); +#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ + + /* Disable the Peripheral */ + __HAL_CEC_DISABLE(hcec); + + /* Clear Flags */ + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND | CEC_FLAG_TXBR | CEC_FLAG_RXBR | CEC_FLAG_RXEND | CEC_ISR_ALL_ERROR); + + /* Disable the following CEC Transmission/Reception interrupts as + * well as the following CEC Transmission/Reception Errors interrupts + * Rx Byte Received IT + * End of Reception IT + * Rx overrun + * Rx bit rising error + * Rx short bit period error + * Rx long bit period error + * Rx missing acknowledge + * Tx Byte Request IT + * End of Transmission IT + * Tx Missing Acknowledge IT + * Tx-Error IT + * Tx-Buffer Underrun IT + * Tx arbitration lost */ + __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND | + CEC_IER_TX_ALL_ERR); + + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + hcec->gState = HAL_CEC_STATE_RESET; + hcec->RxState = HAL_CEC_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(hcec); + + return HAL_OK; +} + +/** + * @brief Initializes the Own Address of the CEC device + * @param hcec CEC handle + * @param CEC_OwnAddress The CEC own address. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress) +{ + /* Check the parameters */ + assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress)); + + if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcec); + + hcec->gState = HAL_CEC_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_CEC_DISABLE(hcec); + + if (CEC_OwnAddress != CEC_OWN_ADDRESS_NONE) + { + hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress << 16); + } + else + { + hcec->Instance->CFGR &= ~(CEC_CFGR_OAR); + } + + hcec->gState = HAL_CEC_STATE_READY; + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hcec); + + /* Enable the Peripheral */ + __HAL_CEC_ENABLE(hcec); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief CEC MSP Init + * @param hcec CEC handle + * @retval None + */ +__weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcec); + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CEC_MspInit can be implemented in the user file + */ +} + +/** + * @brief CEC MSP DeInit + * @param hcec CEC handle + * @retval None + */ +__weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcec); + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CEC_MspDeInit can be implemented in the user file + */ +} +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User CEC Callback + * To be used instead of the weak predefined callback + * @param hcec CEC handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID + * @arg HAL_CEC_ERROR_CB_ID Error callback ID + * @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, + pCEC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hcec); + + if (hcec->gState == HAL_CEC_STATE_READY) + { + switch (CallbackID) + { + case HAL_CEC_TX_CPLT_CB_ID : + hcec->TxCpltCallback = pCallback; + break; + + case HAL_CEC_ERROR_CB_ID : + hcec->ErrorCallback = pCallback; + break; + + case HAL_CEC_MSPINIT_CB_ID : + hcec->MspInitCallback = pCallback; + break; + + case HAL_CEC_MSPDEINIT_CB_ID : + hcec->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcec->gState == HAL_CEC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CEC_MSPINIT_CB_ID : + hcec->MspInitCallback = pCallback; + break; + + case HAL_CEC_MSPDEINIT_CB_ID : + hcec->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hcec); + + return status; +} + +/** + * @brief Unregister an CEC Callback + * CEC callback is redirected to the weak predefined callback + * @param hcec uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID + * @arg HAL_CEC_ERROR_CB_ID Error callback ID + * @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hcec); + + if (hcec->gState == HAL_CEC_STATE_READY) + { + switch (CallbackID) + { + case HAL_CEC_TX_CPLT_CB_ID : + hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_CEC_ERROR_CB_ID : + hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_CEC_MSPINIT_CB_ID : + hcec->MspInitCallback = HAL_CEC_MspInit; + break; + + case HAL_CEC_MSPDEINIT_CB_ID : + hcec->MspDeInitCallback = HAL_CEC_MspDeInit; + break; + + default : + /* Update the error code */ + hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcec->gState == HAL_CEC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CEC_MSPINIT_CB_ID : + hcec->MspInitCallback = HAL_CEC_MspInit; + break; + + case HAL_CEC_MSPDEINIT_CB_ID : + hcec->MspDeInitCallback = HAL_CEC_MspDeInit; + break; + + default : + /* Update the error code */ + hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hcec); + + return status; +} + +/** + * @brief Register CEC RX complete Callback + * To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback + * @param hcec CEC handle + * @param pCallback pointer to the Rx transfer compelete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hcec); + + if (HAL_CEC_STATE_READY == hcec->RxState) + { + hcec->RxCpltCallback = pCallback; + } + else + { + /* Update the error code */ + hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hcec); + return status; +} + +/** + * @brief UnRegister CEC RX complete Callback + * CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback + * @param hcec CEC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hcec); + + if (HAL_CEC_STATE_READY == hcec->RxState) + { + hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak CEC RxCpltCallback */ + } + else + { + /* Update the error code */ + hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hcec); + return status; +} +#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions + * @brief CEC Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the CEC data transfers. + + (#) The CEC handle must contain the initiator (TX side) and the destination (RX side) + logical addresses (4-bit long addresses, 0xF for broadcast messages destination) + + (#) The communication is performed using Interrupts. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated CEC IRQ when using Interrupt mode. + The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_CEC_ErrorCallback() user callback will be executed when a communication + error is detected + + (#) API's with Interrupt are : + (+) HAL_CEC_Transmit_IT() + (+) HAL_CEC_IRQHandler() + + (#) A set of User Callbacks are provided: + (+) HAL_CEC_TxCpltCallback() + (+) HAL_CEC_RxCpltCallback() + (+) HAL_CEC_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Send data in interrupt mode + * @param hcec CEC handle + * @param InitiatorAddress Initiator address + * @param DestinationAddress destination logical address + * @param pData pointer to input byte data buffer + * @param Size amount of data to be sent in bytes (without counting the header). + * 0 means only the header is sent (ping operation). + * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, + const uint8_t *pData, uint32_t Size) +{ + /* if the peripheral isn't already busy and if there is no previous transmission + already pending due to arbitration lost */ + if (hcec->gState == HAL_CEC_STATE_READY) + { + if ((pData == NULL) && (Size > 0U)) + { + return HAL_ERROR; + } + + assert_param(IS_CEC_ADDRESS(DestinationAddress)); + assert_param(IS_CEC_ADDRESS(InitiatorAddress)); + assert_param(IS_CEC_MSGSIZE(Size)); + + /* Process Locked */ + __HAL_LOCK(hcec); + hcec->pTxBuffPtr = pData; + hcec->gState = HAL_CEC_STATE_BUSY_TX; + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + + /* initialize the number of bytes to send, + * 0 means only one header is sent (ping operation) */ + hcec->TxXferCount = (uint16_t)Size; + + /* in case of no payload (Size = 0), sender is only pinging the system; + Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */ + if (Size == 0U) + { + __HAL_CEC_LAST_BYTE_TX_SET(hcec); + } + + /* send header block */ + hcec->Instance->TXDR = (uint32_t)(((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress); + + /* Set TX Start of Message (TXSOM) bit */ + __HAL_CEC_FIRST_BYTE_TX_SET(hcec); + + /* Process Unlocked */ + __HAL_UNLOCK(hcec); + + return HAL_OK; + + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Get size of the received frame. + * @param hcec CEC handle + * @retval Frame size + */ +uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec) +{ + return hcec->RxXferSize; +} + +/** + * @brief Change Rx Buffer. + * @param hcec CEC handle + * @param Rxbuffer Rx Buffer + * @note This function can be called only inside the HAL_CEC_RxCpltCallback() + * @retval Frame size + */ +void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer) +{ + hcec->Init.RxBuffer = Rxbuffer; +} + +/** + * @brief This function handles CEC interrupt requests. + * @param hcec CEC handle + * @retval None + */ +void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) +{ + + /* save interrupts register for further error or interrupts handling purposes */ + uint32_t itflag; + itflag = hcec->Instance->ISR; + + + /* ----------------------------Arbitration Lost Management----------------------------------*/ + /* CEC TX arbitration error interrupt occurred --------------------------------------*/ + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_ARBLST)) + { + hcec->ErrorCode = HAL_CEC_ERROR_ARBLST; + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST); + } + + /* ----------------------------Rx Management----------------------------------*/ + /* CEC RX byte received interrupt ---------------------------------------------------*/ + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXBR)) + { + /* reception is starting */ + hcec->RxState = HAL_CEC_STATE_BUSY_RX; + hcec->RxXferSize++; + /* read received byte */ + *hcec->Init.RxBuffer = (uint8_t) hcec->Instance->RXDR; + hcec->Init.RxBuffer++; + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR); + } + + /* CEC RX end received interrupt ---------------------------------------------------*/ + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXEND)) + { + /* clear IT */ + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND); + + /* Rx process is completed, restore hcec->RxState to Ready */ + hcec->RxState = HAL_CEC_STATE_READY; + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + hcec->Init.RxBuffer -= hcec->RxXferSize; +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U) + hcec->RxCpltCallback(hcec, hcec->RxXferSize); +#else + HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize); +#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ + hcec->RxXferSize = 0U; + } + + /* ----------------------------Tx Management----------------------------------*/ + /* CEC TX byte request interrupt ------------------------------------------------*/ + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXBR)) + { + --hcec->TxXferCount; + if (hcec->TxXferCount == 0U) + { + /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ + __HAL_CEC_LAST_BYTE_TX_SET(hcec); + } + /* In all cases transmit the byte */ + hcec->Instance->TXDR = (uint8_t) * hcec->pTxBuffPtr; + hcec->pTxBuffPtr++; + /* clear Tx-Byte request flag */ + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); + } + + /* CEC TX end interrupt ------------------------------------------------*/ + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXEND)) + { + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND); + + /* Tx process is ended, restore hcec->gState to Ready */ + hcec->gState = HAL_CEC_STATE_READY; + /* Call the Process Unlocked before calling the Tx call back API to give the possibility to + start again the Transmission under the Tx call back API */ + __HAL_UNLOCK(hcec); + hcec->ErrorCode = HAL_CEC_ERROR_NONE; +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U) + hcec->TxCpltCallback(hcec); +#else + HAL_CEC_TxCpltCallback(hcec); +#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ + } + + /* ----------------------------Rx/Tx Error Management----------------------------------*/ + if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | + CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U) + { + hcec->ErrorCode = itflag; + __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE | + HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE); + + + if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U) + { + hcec->Init.RxBuffer -= hcec->RxXferSize; + hcec->RxXferSize = 0U; + hcec->RxState = HAL_CEC_STATE_READY; + } + else if (((itflag & CEC_ISR_ARBLST) == 0U) && ((itflag & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)) + { + /* Set the CEC state ready to be able to start again the process */ + hcec->gState = HAL_CEC_STATE_READY; + } + else + { + /* Nothing todo*/ + } +#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U) + hcec->ErrorCallback(hcec); +#else + /* Error Call Back */ + HAL_CEC_ErrorCallback(hcec); +#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ + } + else + { + /* Nothing todo*/ + } +} + +/** + * @brief Tx Transfer completed callback + * @param hcec CEC handle + * @retval None + */ +__weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcec); + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CEC_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback + * @param hcec CEC handle + * @param RxFrameSize Size of frame + * @retval None + */ +__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcec); + UNUSED(RxFrameSize); + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CEC_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief CEC error callbacks + * @param hcec CEC handle + * @retval None + */ +__weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcec); + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CEC_ErrorCallback can be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function + * @brief CEC control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control function ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the CEC. + (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral. + (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral. +@endverbatim + * @{ + */ +/** + * @brief return the CEC state + * @param hcec pointer to a CEC_HandleTypeDef structure that contains + * the configuration information for the specified CEC module. + * @retval HAL state + */ +HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec) +{ + uint32_t temp1; + uint32_t temp2; + temp1 = hcec->gState; + temp2 = hcec->RxState; + + return (HAL_CEC_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the CEC error code + * @param hcec pointer to a CEC_HandleTypeDef structure that contains + * the configuration information for the specified CEC. + * @retval CEC Error Code + */ +uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec) +{ + return hcec->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* CEC */ +#endif /* HAL_CEC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cordic.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cordic.c new file mode 100644 index 00000000000..5413781ae4d --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cordic.c @@ -0,0 +1,1357 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_cordic.c + * @author MCD Application Team + * @brief CORDIC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORDIC peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Callback functions + * + IRQ handler management + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ================================================================================ + ##### How to use this driver ##### + ================================================================================ + [..] + The CORDIC HAL driver can be used as follows: + + (#) Initialize the CORDIC low level resources by implementing the HAL_CORDIC_MspInit(): + (++) Enable the CORDIC interface clock using __HAL_RCC_CORDIC_CLK_ENABLE() + (++) In case of using interrupts (e.g. HAL_CORDIC_Calculate_IT()) + (+++) Configure the CORDIC interrupt priority using HAL_NVIC_SetPriority() + (+++) Enable the CORDIC IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CORDIC IRQ handler, call HAL_CORDIC_IRQHandler() + (++) In case of using DMA to control data transfer (e.g. HAL_CORDIC_Calculate_DMA()) + (+++) Enable the DMA2 interface clock using + __HAL_RCC_DMA2_CLK_ENABLE() + (+++) Configure and enable two DMA channels one for managing data transfer from + memory to peripheral (input channel) and another channel for managing data + transfer from peripheral to memory (output channel) + (+++) Associate the initialized DMA handle to the CORDIC DMA handle + using __HAL_LINKDMA() + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the two DMA channels. + Resort to HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() + + (#) Initialize the CORDIC HAL using HAL_CORDIC_Init(). This function + (++) resorts to HAL_CORDIC_MspInit() for low-level initialization, + + (#) Configure CORDIC processing (calculation) using HAL_CORDIC_Configure(). + This function configures: + (++) Processing functions: Cosine, Sine, Phase, Modulus, Arctangent, + Hyperbolic cosine, Hyperbolic sine, Hyperbolic arctangent, + Natural log, Square root + (++) Scaling factor: 1 to 2exp(-7) + (++) Width of input data: 32 bits input data size (Q1.31 format) or 16 bits + input data size (Q1.15 format) + (++) Width of output data: 32 bits output data size (Q1.31 format) or 16 bits + output data size (Q1.15 format) + (++) Number of 32-bit write expected for one calculation: One 32-bits write + or Two 32-bit write + (++) Number of 32-bit read expected after one calculation: One 32-bits read + or Two 32-bit read + (++) Precision: 1 to 15 cycles for calculation (the more cycles, the better precision) + + (#) Four processing (calculation) functions are available: + (++) Polling mode: processing API is blocking function + i.e. it processes the data and wait till the processing is finished + API is HAL_CORDIC_Calculate + (++) Polling Zero-overhead mode: processing API is blocking function + i.e. it processes the data and wait till the processing is finished + A bit faster than standard polling mode, but blocking also AHB bus + API is HAL_CORDIC_CalculateZO + (++) Interrupt mode: processing API is not blocking functions + i.e. it processes the data under interrupt + API is HAL_CORDIC_Calculate_IT + (++) DMA mode: processing API is not blocking functions and the CPU is + not used for data transfer, + i.e. the data transfer is ensured by DMA + API is HAL_CORDIC_Calculate_DMA + + (#) Call HAL_CORDIC_DeInit() to de-initialize the CORDIC peripheral. This function + (++) resorts to HAL_CORDIC_MspDeInit() for low-level de-initialization, + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_CORDIC_RegisterCallback() to register an interrupt callback. + + Function HAL_CORDIC_RegisterCallback() allows to register following callbacks: + (+) ErrorCallback : Error Callback. + (+) CalculateCpltCallback : Calculate complete Callback. + (+) MspInitCallback : CORDIC MspInit. + (+) MspDeInitCallback : CORDIC MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_CORDIC_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ErrorCallback : Error Callback. + (+) CalculateCpltCallback : Calculate complete Callback. + (+) MspInitCallback : CORDIC MspInit. + (+) MspDeInitCallback : CORDIC MspDeInit. + + By default, after the HAL_CORDIC_Init() and when the state is HAL_CORDIC_STATE_RESET, + all callbacks are set to the corresponding weak functions: + examples HAL_CORDIC_ErrorCallback(), HAL_CORDIC_CalculateCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_CORDIC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_CORDIC_STATE_READY or HAL_CORDIC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_CORDIC_RegisterCallback() before calling HAL_CORDIC_DeInit() + or HAL_CORDIC_Init() function. + + When The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +#if defined(CORDIC) +#ifdef HAL_CORDIC_MODULE_ENABLED + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup CORDIC CORDIC + * @brief CORDIC HAL driver modules. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup CORDIC_Private_Functions CORDIC Private Functions + * @{ + */ +static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff); +static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff); +static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma); +static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma); +static void CORDIC_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CORDIC_Exported_Functions CORDIC Exported Functions + * @{ + */ + +/** @defgroup CORDIC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CORDIC peripheral and the associated handle + (+) DeInitialize the CORDIC peripheral + (+) Initialize the CORDIC MSP (MCU Specific Package) + (+) De-Initialize the CORDIC MSP + + [..] + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the CORDIC peripheral and the associated handle. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CORDIC_Init(CORDIC_HandleTypeDef *hcordic) +{ + /* Check the CORDIC handle allocation */ + if (hcordic == NULL) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Check the instance */ + assert_param(IS_CORDIC_ALL_INSTANCE(hcordic->Instance)); + +#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 + if (hcordic->State == HAL_CORDIC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcordic->Lock = HAL_UNLOCKED; + + /* Reset callbacks to legacy functions */ + hcordic->ErrorCallback = HAL_CORDIC_ErrorCallback; /* Legacy weak ErrorCallback */ + hcordic->CalculateCpltCallback = HAL_CORDIC_CalculateCpltCallback; /* Legacy weak CalculateCpltCallback */ + + if (hcordic->MspInitCallback == NULL) + { + hcordic->MspInitCallback = HAL_CORDIC_MspInit; /* Legacy weak MspInit */ + } + + /* Initialize the low level hardware */ + hcordic->MspInitCallback(hcordic); + } +#else + if (hcordic->State == HAL_CORDIC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcordic->Lock = HAL_UNLOCKED; + + /* Initialize the low level hardware */ + HAL_CORDIC_MspInit(hcordic); + } +#endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */ + + /* Set CORDIC error code to none */ + hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE; + + /* Reset pInBuff and pOutBuff */ + hcordic->pInBuff = NULL; + hcordic->pOutBuff = NULL; + + /* Reset NbCalcToOrder and NbCalcToGet */ + hcordic->NbCalcToOrder = 0U; + hcordic->NbCalcToGet = 0U; + + /* Reset DMADirection */ + hcordic->DMADirection = CORDIC_DMA_DIR_NONE; + + /* Change CORDIC peripheral state */ + hcordic->State = HAL_CORDIC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the CORDIC peripheral. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CORDIC_DeInit(CORDIC_HandleTypeDef *hcordic) +{ + /* Check the CORDIC handle allocation */ + if (hcordic == NULL) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CORDIC_ALL_INSTANCE(hcordic->Instance)); + + /* Change CORDIC peripheral state */ + hcordic->State = HAL_CORDIC_STATE_BUSY; + +#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 + if (hcordic->MspDeInitCallback == NULL) + { + hcordic->MspDeInitCallback = HAL_CORDIC_MspDeInit; + } + + /* De-Initialize the low level hardware */ + hcordic->MspDeInitCallback(hcordic); +#else + /* De-Initialize the low level hardware: CLOCK, NVIC, DMA */ + HAL_CORDIC_MspDeInit(hcordic); +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + + /* Set CORDIC error code to none */ + hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE; + + /* Reset pInBuff and pOutBuff */ + hcordic->pInBuff = NULL; + hcordic->pOutBuff = NULL; + + /* Reset NbCalcToOrder and NbCalcToGet */ + hcordic->NbCalcToOrder = 0U; + hcordic->NbCalcToGet = 0U; + + /* Reset DMADirection */ + hcordic->DMADirection = CORDIC_DMA_DIR_NONE; + + /* Change CORDIC peripheral state */ + hcordic->State = HAL_CORDIC_STATE_RESET; + + /* Reset Lock */ + hcordic->Lock = HAL_UNLOCKED; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the CORDIC MSP. + * @param hcordic CORDIC handle + * @retval None + */ +__weak void HAL_CORDIC_MspInit(CORDIC_HandleTypeDef *hcordic) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcordic); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CORDIC_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the CORDIC MSP. + * @param hcordic CORDIC handle + * @retval None + */ +__weak void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcordic); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CORDIC_MspDeInit can be implemented in the user file + */ +} + +#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 +/** + * @brief Register a CORDIC CallBack. + * To be used instead of the weak predefined callback. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains + * the configuration information for CORDIC module + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_CORDIC_ERROR_CB_ID error Callback ID + * @arg @ref HAL_CORDIC_CALCULATE_CPLT_CB_ID calculate complete Callback ID + * @arg @ref HAL_CORDIC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CORDIC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, + void (* pCallback)(CORDIC_HandleTypeDef *_hcordic)) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + return HAL_ERROR; + } + + if (hcordic->State == HAL_CORDIC_STATE_READY) + { + switch (CallbackID) + { + case HAL_CORDIC_ERROR_CB_ID : + hcordic->ErrorCallback = pCallback; + break; + + case HAL_CORDIC_CALCULATE_CPLT_CB_ID : + hcordic->CalculateCpltCallback = pCallback; + break; + + case HAL_CORDIC_MSPINIT_CB_ID : + hcordic->MspInitCallback = pCallback; + break; + + case HAL_CORDIC_MSPDEINIT_CB_ID : + hcordic->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcordic->State == HAL_CORDIC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CORDIC_MSPINIT_CB_ID : + hcordic->MspInitCallback = pCallback; + break; + + case HAL_CORDIC_MSPDEINIT_CB_ID : + hcordic->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + +#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 +/** + * @brief Unregister a CORDIC CallBack. + * CORDIC callback is redirected to the weak predefined callback. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains + * the configuration information for CORDIC module + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_CORDIC_ERROR_CB_ID error Callback ID + * @arg @ref HAL_CORDIC_CALCULATE_CPLT_CB_ID calculate complete Callback ID + * @arg @ref HAL_CORDIC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CORDIC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hcordic->State == HAL_CORDIC_STATE_READY) + { + switch (CallbackID) + { + case HAL_CORDIC_ERROR_CB_ID : + hcordic->ErrorCallback = HAL_CORDIC_ErrorCallback; + break; + + case HAL_CORDIC_CALCULATE_CPLT_CB_ID : + hcordic->CalculateCpltCallback = HAL_CORDIC_CalculateCpltCallback; + break; + + case HAL_CORDIC_MSPINIT_CB_ID : + hcordic->MspInitCallback = HAL_CORDIC_MspInit; + break; + + case HAL_CORDIC_MSPDEINIT_CB_ID : + hcordic->MspDeInitCallback = HAL_CORDIC_MspDeInit; + break; + + default : + /* Update the error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcordic->State == HAL_CORDIC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CORDIC_MSPINIT_CB_ID : + hcordic->MspInitCallback = HAL_CORDIC_MspInit; + break; + + case HAL_CORDIC_MSPDEINIT_CB_ID : + hcordic->MspDeInitCallback = HAL_CORDIC_MspDeInit; + break; + + default : + /* Update the error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup CORDIC_Exported_Functions_Group2 Peripheral Control functions + * @brief Control functions. + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure the CORDIC peripheral: function, precision, scaling factor, + number of input data and output data, size of input data and output data. + (+) Calculate output data of CORDIC processing on input date, using the + existing CORDIC configuration + [..] Four processing functions are available for calculation: + (+) Polling mode + (+) Polling mode, with Zero-Overhead register access + (+) Interrupt mode + (+) DMA mode + +@endverbatim + * @{ + */ + +/** + * @brief Configure the CORDIC processing according to the specified + parameters in the CORDIC_ConfigTypeDef structure. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains + * the configuration information for CORDIC module + * @param sConfig pointer to a CORDIC_ConfigTypeDef structure that + * contains the CORDIC configuration information. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_CORDIC_FUNCTION(sConfig->Function)); + assert_param(IS_CORDIC_PRECISION(sConfig->Precision)); + assert_param(IS_CORDIC_SCALE(sConfig->Scale)); + assert_param(IS_CORDIC_NBWRITE(sConfig->NbWrite)); + assert_param(IS_CORDIC_NBREAD(sConfig->NbRead)); + assert_param(IS_CORDIC_INSIZE(sConfig->InSize)); + assert_param(IS_CORDIC_OUTSIZE(sConfig->OutSize)); + + /* Check handle state is ready */ + if (hcordic->State == HAL_CORDIC_STATE_READY) + { + /* Apply all configuration parameters in CORDIC control register */ + MODIFY_REG(hcordic->Instance->CSR, \ + (CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE | \ + CORDIC_CSR_NARGS | CORDIC_CSR_NRES | CORDIC_CSR_ARGSIZE | CORDIC_CSR_RESSIZE), \ + (sConfig->Function | sConfig->Precision | sConfig->Scale | \ + sConfig->NbWrite | sConfig->NbRead | sConfig->InSize | sConfig->OutSize)); + } + else + { + /* Set CORDIC error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +/** + * @brief Carry out data of CORDIC processing in polling mode, + * according to the existing CORDIC configuration. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains + * the configuration information for CORDIC module. + * @param pInBuff Pointer to buffer containing input data for CORDIC processing. + * @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored. + * @param NbCalc Number of CORDIC calculation to process. + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t index; + const int32_t *p_tmp_in_buff = pInBuff; + int32_t *p_tmp_out_buff = pOutBuff; + + /* Check parameters setting */ + if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U)) + { + /* Update the error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM; + + /* Return error status */ + return HAL_ERROR; + } + + /* Check handle state is ready */ + if (hcordic->State == HAL_CORDIC_STATE_READY) + { + /* Reset CORDIC error code */ + hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE; + + /* Change the CORDIC state */ + hcordic->State = HAL_CORDIC_STATE_BUSY; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Write of input data in Write Data register, and increment input buffer pointer */ + CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff); + + /* Calculation is started. + Provide next set of input data, until number of calculation is achieved */ + for (index = (NbCalc - 1U); index > 0U; index--) + { + /* Write of input data in Write Data register, and increment input buffer pointer */ + CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff); + + /* Wait for RRDY flag to be raised */ + do + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if ((HAL_GetTick() - tickstart) > Timeout) + { + /* Set CORDIC error code */ + hcordic->ErrorCode = HAL_CORDIC_ERROR_TIMEOUT; + + /* Change the CORDIC state */ + hcordic->State = HAL_CORDIC_STATE_READY; + + /* Return function status */ + return HAL_ERROR; + } + } + } while (HAL_IS_BIT_CLR(hcordic->Instance->CSR, CORDIC_CSR_RRDY)); + + /* Read output data from Read Data register, and increment output buffer pointer */ + CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff); + } + + /* Read output data from Read Data register, and increment output buffer pointer */ + CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff); + + /* Change the CORDIC state */ + hcordic->State = HAL_CORDIC_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Set CORDIC error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Carry out data of CORDIC processing in Zero-Overhead mode (output data being read + * soon as input data are written), according to the existing CORDIC configuration. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains + * the configuration information for CORDIC module. + * @param pInBuff Pointer to buffer containing input data for CORDIC processing. + * @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored. + * @param NbCalc Number of CORDIC calculation to process. + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t index; + const int32_t *p_tmp_in_buff = pInBuff; + int32_t *p_tmp_out_buff = pOutBuff; + + /* Check parameters setting */ + if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U)) + { + /* Update the error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM; + + /* Return error status */ + return HAL_ERROR; + } + + /* Check handle state is ready */ + if (hcordic->State == HAL_CORDIC_STATE_READY) + { + /* Reset CORDIC error code */ + hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE; + + /* Change the CORDIC state */ + hcordic->State = HAL_CORDIC_STATE_BUSY; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Write of input data in Write Data register, and increment input buffer pointer */ + CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff); + + /* Calculation is started. + Provide next set of input data, until number of calculation is achieved */ + for (index = (NbCalc - 1U); index > 0U; index--) + { + /* Write of input data in Write Data register, and increment input buffer pointer */ + CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff); + + /* Read output data from Read Data register, and increment output buffer pointer + The reading is performed in Zero-Overhead mode: + reading is ordered immediately without waiting result ready flag */ + CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff); + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if ((HAL_GetTick() - tickstart) > Timeout) + { + /* Set CORDIC error code */ + hcordic->ErrorCode = HAL_CORDIC_ERROR_TIMEOUT; + + /* Change the CORDIC state */ + hcordic->State = HAL_CORDIC_STATE_READY; + + /* Return function status */ + return HAL_ERROR; + } + } + } + + /* Read output data from Read Data register, and increment output buffer pointer + The reading is performed in Zero-Overhead mode: + reading is ordered immediately without waiting result ready flag */ + CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff); + + /* Change the CORDIC state */ + hcordic->State = HAL_CORDIC_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Set CORDIC error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Carry out data of CORDIC processing in interrupt mode, + * according to the existing CORDIC configuration. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains + * the configuration information for CORDIC module. + * @param pInBuff Pointer to buffer containing input data for CORDIC processing. + * @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored. + * @param NbCalc Number of CORDIC calculation to process. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc) +{ + const int32_t *tmp_pInBuff = pInBuff; + + /* Check parameters setting */ + if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U)) + { + /* Update the error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM; + + /* Return error status */ + return HAL_ERROR; + } + + /* Check handle state is ready */ + if (hcordic->State == HAL_CORDIC_STATE_READY) + { + /* Reset CORDIC error code */ + hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE; + + /* Change the CORDIC state */ + hcordic->State = HAL_CORDIC_STATE_BUSY; + + /* Store the buffers addresses and number of calculations in handle, + provisioning initial write of input data that will be done */ + if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS)) + { + /* Two writes of input data are expected */ + tmp_pInBuff++; + tmp_pInBuff++; + } + else + { + /* One write of input data is expected */ + tmp_pInBuff++; + } + hcordic->pInBuff = tmp_pInBuff; + hcordic->pOutBuff = pOutBuff; + hcordic->NbCalcToOrder = NbCalc - 1U; + hcordic->NbCalcToGet = NbCalc; + + /* Enable Result Ready Interrupt */ + __HAL_CORDIC_ENABLE_IT(hcordic, CORDIC_IT_IEN); + + /* Set back pointer to start of input data buffer */ + tmp_pInBuff = pInBuff; + + /* Initiate the processing by providing input data + in the Write Data register */ + WRITE_REG(hcordic->Instance->WDATA, (uint32_t)*tmp_pInBuff); + + /* Check if second write of input data is expected */ + if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS)) + { + /* Increment pointer to input data */ + tmp_pInBuff++; + + /* Perform second write of input data */ + WRITE_REG(hcordic->Instance->WDATA, (uint32_t)*tmp_pInBuff); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Set CORDIC error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Carry out input and/or output data of CORDIC processing in DMA mode, + * according to the existing CORDIC configuration. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains + * the configuration information for CORDIC module. + * @param pInBuff Pointer to buffer containing input data for CORDIC processing. + * @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored. + * @param NbCalc Number of CORDIC calculation to process. + * @param DMADirection Direction of DMA transfers. + * This parameter can be one of the following values: + * @arg @ref CORDIC_DMA_Direction CORDIC DMA direction + * @note pInBuff or pOutBuff is unused in case of unique DMADirection transfer, and can + * be set to NULL value in this case. + * @note pInBuff and pOutBuff buffers must be 32-bit aligned to ensure a correct + * DMA transfer to and from the Peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t DMADirection) +{ + uint32_t sizeinbuff; + uint32_t sizeoutbuff; + + /* Check the parameters */ + assert_param(IS_CORDIC_DMA_DIRECTION(DMADirection)); + + /* Check parameters setting */ + if (NbCalc == 0U) + { + /* Update the error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM; + + /* Return error status */ + return HAL_ERROR; + } + + /* Check if CORDIC DMA direction "Out" is requested */ + if ((DMADirection == CORDIC_DMA_DIR_OUT) || (DMADirection == CORDIC_DMA_DIR_IN_OUT)) + { + /* Check parameters setting */ + if (pOutBuff == NULL) + { + /* Update the error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM; + + /* Return error status */ + return HAL_ERROR; + } + } + + /* Check if CORDIC DMA direction "In" is requested */ + if ((DMADirection == CORDIC_DMA_DIR_IN) || (DMADirection == CORDIC_DMA_DIR_IN_OUT)) + { + /* Check parameters setting */ + if (pInBuff == NULL) + { + /* Update the error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM; + + /* Return error status */ + return HAL_ERROR; + } + } + + if (hcordic->State == HAL_CORDIC_STATE_READY) + { + /* Reset CORDIC error code */ + hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE; + + /* Change the CORDIC state */ + hcordic->State = HAL_CORDIC_STATE_BUSY; + + /* Get DMA direction */ + hcordic->DMADirection = DMADirection; + + /* Check if CORDIC DMA direction "Out" is requested */ + if ((DMADirection == CORDIC_DMA_DIR_OUT) || (DMADirection == CORDIC_DMA_DIR_IN_OUT)) + { + /* Set the CORDIC DMA transfer complete callback */ + hcordic->hdmaOut->XferCpltCallback = CORDIC_DMAOutCplt; + /* Set the DMA error callback */ + hcordic->hdmaOut->XferErrorCallback = CORDIC_DMAError; + + /* Check number of output data at each calculation, + to retrieve the size of output data buffer */ + if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NRES)) + { + sizeoutbuff = 2U * NbCalc; + } + else + { + sizeoutbuff = NbCalc; + } + + /* Convert the output buffer size into corresponding number of bytes. + This is necessary as the DMA handles the data at byte-level. */ + sizeoutbuff = 4U * sizeoutbuff; + + /* Enable the DMA stream managing CORDIC output data read */ + if (HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, (uint32_t) pOutBuff, sizeoutbuff) + != HAL_OK) + { + /* Update the error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA; + + /* Return error status */ + return HAL_ERROR; + } + + /* Enable output data Read DMA requests */ + SET_BIT(hcordic->Instance->CSR, CORDIC_DMA_REN); + } + + /* Check if CORDIC DMA direction "In" is requested */ + if ((DMADirection == CORDIC_DMA_DIR_IN) || (DMADirection == CORDIC_DMA_DIR_IN_OUT)) + { + /* Set the CORDIC DMA transfer complete callback */ + hcordic->hdmaIn->XferCpltCallback = CORDIC_DMAInCplt; + /* Set the DMA error callback */ + hcordic->hdmaIn->XferErrorCallback = CORDIC_DMAError; + + /* Check number of input data expected for each calculation, + to retrieve the size of input data buffer */ + if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS)) + { + sizeinbuff = 2U * NbCalc; + } + else + { + sizeinbuff = NbCalc; + } + + /* Convert the input buffer size into corresponding number of bytes. + This is necessary as the DMA handles the data at byte-level. */ + sizeinbuff = 4U * sizeinbuff; + + /* Enable the DMA stream managing CORDIC input data write */ + if (HAL_DMA_Start_IT(hcordic->hdmaIn, (uint32_t) pInBuff, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff) + != HAL_OK) + { + /* Update the error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA; + + /* Return error status */ + return HAL_ERROR; + } + + /* Enable input data Write DMA request */ + SET_BIT(hcordic->Instance->CSR, CORDIC_DMA_WEN); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Set CORDIC error code */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup CORDIC_Exported_Functions_Group3 Callback functions + * @brief Callback functions. + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] This section provides Interruption and DMA callback functions: + (+) DMA or Interrupt calculate complete + (+) DMA or Interrupt error + +@endverbatim + * @{ + */ + +/** + * @brief CORDIC error callback. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains + * the configuration information for CORDIC module + * @retval None + */ +__weak void HAL_CORDIC_ErrorCallback(CORDIC_HandleTypeDef *hcordic) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcordic); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CORDIC_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief CORDIC calculate complete callback. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains + * the configuration information for CORDIC module + * @retval None + */ +__weak void HAL_CORDIC_CalculateCpltCallback(CORDIC_HandleTypeDef *hcordic) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcordic); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CORDIC_CalculateCpltCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CORDIC_Exported_Functions_Group4 IRQ handler management + * @brief IRQ handler. + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== +[..] This section provides IRQ handler function. + +@endverbatim + * @{ + */ + +/** + * @brief Handle CORDIC interrupt request. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains + * the configuration information for CORDIC module + * @retval None + */ +void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic) +{ + /* Check if calculation complete interrupt is enabled and if result ready + flag is raised */ + if (__HAL_CORDIC_GET_IT_SOURCE(hcordic, CORDIC_IT_IEN) != 0U) + { + if (__HAL_CORDIC_GET_FLAG(hcordic, CORDIC_FLAG_RRDY) != 0U) + { + /* Decrement number of calculations to get */ + hcordic->NbCalcToGet--; + + /* Read output data from Read Data register, and increment output buffer pointer */ + CORDIC_ReadOutDataIncrementPtr(hcordic, &(hcordic->pOutBuff)); + + /* Check if calculations are still to be ordered */ + if (hcordic->NbCalcToOrder > 0U) + { + /* Decrement number of calculations to order */ + hcordic->NbCalcToOrder--; + + /* Continue the processing by providing another write of input data + in the Write Data register, and increment input buffer pointer */ + CORDIC_WriteInDataIncrementPtr(hcordic, &(hcordic->pInBuff)); + } + + /* Check if all calculations results are got */ + if (hcordic->NbCalcToGet == 0U) + { + /* Disable Result Ready Interrupt */ + __HAL_CORDIC_DISABLE_IT(hcordic, CORDIC_IT_IEN); + + /* Change the CORDIC state */ + hcordic->State = HAL_CORDIC_STATE_READY; + + /* Call calculation complete callback */ +#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 + /*Call registered callback*/ + hcordic->CalculateCpltCallback(hcordic); +#else + /*Call legacy weak callback*/ + HAL_CORDIC_CalculateCpltCallback(hcordic); +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + } + } + } +} + +/** + * @} + */ + +/** @defgroup CORDIC_Exported_Functions_Group5 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CORDIC handle state. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains + * the configuration information for CORDIC module + * @retval HAL state + */ +HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic) +{ + /* Return CORDIC handle state */ + return hcordic->State; +} + +/** + * @brief Return the CORDIC peripheral error. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains + * the configuration information for CORDIC module + * @note The returned error is a bit-map combination of possible errors + * @retval Error bit-map + */ +uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic) +{ + /* Return CORDIC error code */ + return hcordic->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CORDIC_Private_Functions + * @{ + */ + +/** + * @brief Write input data for CORDIC processing, and increment input buffer pointer. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains + * the configuration information for CORDIC module. + * @param ppInBuff Pointer to pointer to input buffer. + * @retval none + */ +static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff) +{ + /* First write of input data in the Write Data register */ + WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff); + + /* Increment input data pointer */ + (*ppInBuff)++; + + /* Check if second write of input data is expected */ + if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS)) + { + /* Second write of input data in the Write Data register */ + WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff); + + /* Increment input data pointer */ + (*ppInBuff)++; + } +} + +/** + * @brief Read output data of CORDIC processing, and increment output buffer pointer. + * @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains + * the configuration information for CORDIC module. + * @param ppOutBuff Pointer to pointer to output buffer. + * @retval none + */ +static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff) +{ + /* First read of output data from the Read Data register */ + **ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA); + + /* Increment output data pointer */ + (*ppOutBuff)++; + + /* Check if second read of output data is expected */ + if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NRES)) + { + /* Second read of output data from the Read Data register */ + **ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA); + + /* Increment output data pointer */ + (*ppOutBuff)++; + } +} + +/** + * @brief DMA CORDIC Input Data process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma) +{ + CORDIC_HandleTypeDef *hcordic = (CORDIC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable the DMA transfer for input request */ + CLEAR_BIT(hcordic->Instance->CSR, CORDIC_DMA_WEN); + + /* Check if DMA direction is CORDIC Input only (no DMA for CORDIC Output) */ + if (hcordic->DMADirection == CORDIC_DMA_DIR_IN) + { + /* Change the CORDIC DMA direction to none */ + hcordic->DMADirection = CORDIC_DMA_DIR_NONE; + + /* Change the CORDIC state to ready */ + hcordic->State = HAL_CORDIC_STATE_READY; + + /* Call calculation complete callback */ +#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 + /*Call registered callback*/ + hcordic->CalculateCpltCallback(hcordic); +#else + /*Call legacy weak callback*/ + HAL_CORDIC_CalculateCpltCallback(hcordic); +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA CORDIC Output Data process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma) +{ + CORDIC_HandleTypeDef *hcordic = (CORDIC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable the DMA transfer for output request */ + CLEAR_BIT(hcordic->Instance->CSR, CORDIC_DMA_REN); + + /* Change the CORDIC DMA direction to none */ + hcordic->DMADirection = CORDIC_DMA_DIR_NONE; + + /* Change the CORDIC state to ready */ + hcordic->State = HAL_CORDIC_STATE_READY; + + /* Call calculation complete callback */ +#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 + /*Call registered callback*/ + hcordic->CalculateCpltCallback(hcordic); +#else + /*Call legacy weak callback*/ + HAL_CORDIC_CalculateCpltCallback(hcordic); +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA CORDIC communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void CORDIC_DMAError(DMA_HandleTypeDef *hdma) +{ + CORDIC_HandleTypeDef *hcordic = (CORDIC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Set CORDIC handle state to error */ + hcordic->State = HAL_CORDIC_STATE_READY; + + /* Set CORDIC handle error code to DMA error */ + hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA; + + /* Call user callback */ +#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 + /*Call registered callback*/ + hcordic->ErrorCallback(hcordic); +#else + /*Call legacy weak callback*/ + HAL_CORDIC_ErrorCallback(hcordic); +#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORDIC_MODULE_ENABLED */ +#endif /* CORDIC */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cortex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cortex.c new file mode 100644 index 00000000000..ef802386a66 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cortex.c @@ -0,0 +1,569 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and Configuration functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M7 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest pre-emption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure SysTick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32h7rsxx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. + + ========================================================================================================================== + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ========================================================================================================================== + NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority + | | | 4 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority + | | | 3 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bit for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bit for subpriority + ========================================================================================================================== + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + SysTick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Set the priority grouping field (pre-emption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority, + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority, + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority, + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority, + * 1 bit for subpriority + * @arg NVIC_PRIORITYGROUP_4 4 bits for pre-emption priority, + * 0 bit for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Set the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32h7rsxxxx.h)) + * @param PreemptPriority The pre-emption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup; + + /* Check the parameters */ + assert_param(IS_NVIC_PRIO_INTERRUPT(IRQn)); + prioritygroup = NVIC_GetPriorityGrouping(); + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority, prioritygroup)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority, prioritygroup)); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enable a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32h7rsxxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disable a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32h7rsxxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiate a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +/** + * @brief Get the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Get the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32h7rsxxxx.h)) + * @param PriorityGroup the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority, + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority, + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority, + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority, + * 1 bit for subpriority + * @arg NVIC_PRIORITYGROUP_4 4 bits for pre-emption priority, + * 0 bit for subpriority + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIO_INTERRUPT(IRQn)); + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Set Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32h7rsxxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Get Pending Interrupt (read the pending register in the NVIC + * and return the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32h7rsxxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clear the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32h7rsxxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Get active interrupt (read the active register in NVIC and return the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32h7rsxxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configure the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK AHB clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8 AHB clock divided by 8 selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + + MODIFY_REG(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk, CLKSource); +} + +/** + * @brief Handle SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @brief Enable the MPU. + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Force any outstanding transfers to complete before enabling MPU */ + __DMB(); + + /* Enable the MPU */ + MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk); + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +/** + * @brief Disable the MPU. + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Force any outstanding transfers to complete before disabling MPU */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register */ + MPU->CTRL = 0U; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +/** + * @brief Enable the MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Disable the MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Initialize and configure the Region and the memory to be protected. + * @param pMPU_RegionInit Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @note The region base address must be aligned to the size of the region. + * @retval None + */ +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *pMPU_RegionInit) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number)); + assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable)); + + /* Set the Region number */ + MPU->RNR = pMPU_RegionInit->Number; + + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(pMPU_RegionInit->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(pMPU_RegionInit->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(pMPU_RegionInit->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(pMPU_RegionInit->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(pMPU_RegionInit->Size)); + assert_param(IS_MPU_ADDRESS_MULTIPLE_SIZE(pMPU_RegionInit->BaseAddress, pMPU_RegionInit->Size)); + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + MPU->RBAR = pMPU_RegionInit->BaseAddress; + MPU->RASR = ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)pMPU_RegionInit->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)pMPU_RegionInit->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)pMPU_RegionInit->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)pMPU_RegionInit->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)pMPU_RegionInit->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)pMPU_RegionInit->Enable << MPU_RASR_ENABLE_Pos); +} + +/** + * @brief Clear pending events. + * @retval None + */ +void HAL_CORTEX_ClearEvent(void) +{ + __SEV(); + __WFE(); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_crc.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_crc.c new file mode 100644 index 00000000000..9bc048e6469 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_crc.c @@ -0,0 +1,516 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_crc.c + * @author MCD Application Team + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Cyclic Redundancy Check (CRC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); + (+) Initialize CRC calculator + (++) specify generating polynomial (peripheral default or non-default one) + (++) specify initialization value (peripheral default or non-default one) + (++) specify input data format + (++) specify input or output data inversion mode if any + (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the + input data buffer starting with the previously computed CRC as + initialization value + (+) Use HAL_CRC_Calculate() function to compute the CRC value of the + input data buffer starting with the defined initialization value + (default or non-default) to initiate CRC calculation + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC HAL module driver. + * @{ + */ + +#ifdef HAL_CRC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CRC_Private_Functions CRC Private Functions + * @{ + */ +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CRC according to the specified parameters + in the CRC_InitTypeDef and create the associated handle + (+) DeInitialize the CRC peripheral + (+) Initialize the CRC MSP (MCU Specific Package) + (+) DeInitialize the CRC MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the CRC according to the specified + * parameters in the CRC_InitTypeDef and create the associated handle. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if (hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + if (hcrc->State == HAL_CRC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcrc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_CRC_MspInit(hcrc); + } + + hcrc->State = HAL_CRC_STATE_BUSY; + + /* check whether or not non-default generating polynomial has been + * picked up by user */ + assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); + if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) + { + /* initialize peripheral with default generating polynomial */ + WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); + } + else + { + /* initialize CRC peripheral with generating polynomial defined by user */ + if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* check whether or not non-default CRC initial value has been + * picked up by user */ + assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); + if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) + { + WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); + } + else + { + WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); + } + + + /* set input data inversion mode */ + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); + + /* set output data inversion mode */ + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); + + /* makes sure the input data format (bytes, halfwords or words stream) + * is properly specified by user */ + assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the CRC peripheral. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if (hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + /* Check the CRC peripheral state */ + if (hcrc->State == HAL_CRC_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC calculation unit */ + __HAL_CRC_DR_RESET(hcrc); + + /* Reset IDR register content */ + CLEAR_REG(hcrc->Instance->IDR); + + /* DeInit the low level hardware */ + HAL_CRC_MspDeInit(hcrc); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_RESET; + + /* Process unlocked */ + __HAL_UNLOCK(hcrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CRC MSP. + * @param hcrc CRC handle + * @retval None + */ +__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the CRC MSP. + * @param hcrc CRC handle + * @retval None + */ +__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions. + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + using combination of the previous CRC value and the new one. + + [..] or + + (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + independently of the previous CRC value. + +@endverbatim + * @{ + */ + +/** + * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + * starting with the previously computed CRC as initialization value. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is + * provided by hcrc->InputDataFormat. + * @param BufferLength input data buffer length (number of bytes if pBuffer + * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, + * number of words if pBuffer type is * uint32_t). + * @note By default, the API expects a uint32_t pointer as input buffer parameter. + * Input buffer pointers with other types simply need to be cast in uint32_t + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + switch (hcrc->InputDataFormat) + { + case CRC_INPUTDATA_FORMAT_WORDS: + /* Enter Data to the CRC calculator */ + for (index = 0U; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + break; + + case CRC_INPUTDATA_FORMAT_BYTES: + temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + break; + + case CRC_INPUTDATA_FORMAT_HALFWORDS: + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + break; + default: + break; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return the CRC computed value */ + return temp; +} + +/** + * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + * starting with hcrc->Instance->INIT as initialization value. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is + * provided by hcrc->InputDataFormat. + * @param BufferLength input data buffer length (number of bytes if pBuffer + * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, + * number of words if pBuffer type is * uint32_t). + * @note By default, the API expects a uint32_t pointer as input buffer parameter. + * Input buffer pointers with other types simply need to be cast in uint32_t + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC Calculation Unit (hcrc->Instance->INIT is + * written in hcrc->Instance->DR) */ + __HAL_CRC_DR_RESET(hcrc); + + switch (hcrc->InputDataFormat) + { + case CRC_INPUTDATA_FORMAT_WORDS: + /* Enter 32-bit input data to the CRC calculator */ + for (index = 0U; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + break; + + case CRC_INPUTDATA_FORMAT_BYTES: + /* Specific 8-bit input data handling */ + temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + break; + + case CRC_INPUTDATA_FORMAT_HALFWORDS: + /* Specific 16-bit input data handling */ + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + break; + + default: + break; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return the CRC computed value */ + return temp; +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CRC handle state. + * @param hcrc CRC handle + * @retval HAL state + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc) +{ + /* Return CRC handle state */ + return hcrc->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Enter 8-bit input data to the CRC calculator. + * Specific data handling to optimize processing time. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) +{ + uint32_t i; /* input data buffer index */ + uint16_t data; + __IO uint16_t *pReg; + + /* Processing time optimization: 4 bytes are entered in a row with a single word write, + * last bytes must be carefully fed to the CRC calculator to ensure a correct type + * handling by the peripheral */ + for (i = 0U; i < (BufferLength / 4U); i++) + { + hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ + ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ + ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ + (uint32_t)pBuffer[(4U * i) + 3U]; + } + /* last bytes specific handling */ + if ((BufferLength % 4U) != 0U) + { + if ((BufferLength % 4U) == 1U) + { + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ + } + if ((BufferLength % 4U) == 2U) + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = data; + } + if ((BufferLength % 4U) == 3U) + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = data; + + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ + } + } + + /* Return the CRC computed value */ + return hcrc->Instance->DR; +} + +/** + * @brief Enter 16-bit input data to the CRC calculator. + * Specific data handling to optimize processing time. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) +{ + uint32_t i; /* input data buffer index */ + __IO uint16_t *pReg; + + /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, + * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure + * a correct type handling by the peripheral */ + for (i = 0U; i < (BufferLength / 2U); i++) + { + hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; + } + if ((BufferLength % 2U) != 0U) + { + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = pBuffer[2U * i]; + } + + /* Return the CRC computed value */ + return hcrc->Instance->DR; +} + +/** + * @} + */ + +#endif /* HAL_CRC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_crc_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_crc_ex.c new file mode 100644 index 00000000000..cc4ebb87b84 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_crc_ex.c @@ -0,0 +1,232 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_crc_ex.c + * @author MCD Application Team + * @brief Extended CRC HAL module driver. + * This file provides firmware functions to manage the extended + * functionalities of the CRC peripheral. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim +================================================================================ + ##### How to use this driver ##### +================================================================================ + [..] + (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set() + (+) Configure Input or Output data inversion + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup CRCEx CRCEx + * @brief CRC Extended HAL module driver + * @{ + */ + +#ifdef HAL_CRC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions + * @{ + */ + +/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions + * @brief Extended Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Extended configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the generating polynomial + (+) Configure the input data inversion + (+) Configure the output data inversion + +@endverbatim + * @{ + */ + + +/** + * @brief Initialize the CRC polynomial if different from default one. + * @param hcrc CRC handle + * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long). + * This parameter is written in normal representation, e.g. + * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 + * @param PolyLength CRC polynomial length. + * This parameter can be one of the following values: + * @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7) + * @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8) + * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) + * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ + + /* Check the parameters */ + assert_param(IS_CRC_POL_LENGTH(PolyLength)); + + /* Ensure that the generating polynomial is odd */ + if ((Pol & (uint32_t)(0x1U)) == 0U) + { + status = HAL_ERROR; + } + else + { + /* check polynomial definition vs polynomial size: + * polynomial length must be aligned with polynomial + * definition. HAL_ERROR is reported if Pol degree is + * larger than that indicated by PolyLength. + * Look for MSB position: msb will contain the degree of + * the second to the largest polynomial member. E.g., for + * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ + while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + { + } + + switch (PolyLength) + { + + case CRC_POLYLENGTH_7B: + if (msb >= HAL_CRC_LENGTH_7B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_8B: + if (msb >= HAL_CRC_LENGTH_8B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_16B: + if (msb >= HAL_CRC_LENGTH_16B) + { + status = HAL_ERROR; + } + break; + + case CRC_POLYLENGTH_32B: + /* no polynomial definition vs. polynomial length issue possible */ + break; + default: + status = HAL_ERROR; + break; + } + } + if (status == HAL_OK) + { + /* set generating polynomial */ + WRITE_REG(hcrc->Instance->POL, Pol); + + /* set generating polynomial size */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); + } + /* Return function status */ + return status; +} + +/** + * @brief Set the Reverse Input data mode. + * @param hcrc CRC handle + * @param InputReverseMode Input Data inversion mode. + * This parameter can be one of the following values: + * @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value) + * @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal + * @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal + * @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode) +{ + /* Check the parameters */ + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* set input data inversion mode */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode); + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the Reverse Output data mode. + * @param hcrc CRC handle + * @param OutputReverseMode Output Data inversion mode. + * This parameter can be one of the following values: + * @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value) + * @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode) +{ + /* Check the parameters */ + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* set output data inversion mode */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + + + + +/** + * @} + */ + + +/** + * @} + */ + + +#endif /* HAL_CRC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cryp.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cryp.c new file mode 100644 index 00000000000..ca29a2d14aa --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cryp.c @@ -0,0 +1,8100 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_cryp.c + * @author MCD Application Team + * @brief CRYP HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Cryptography (CRYP) peripheral: + * + Initialization and de-initialization functions + * + AES processing functions + * + DMA callback functions + * + CRYP IRQ handler management + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The CRYP HAL driver can be used in CRYP IP as follows: + + (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): + (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE() + (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT()) + (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority() + (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler() + (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA()) + (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE() + (+++) Configure and enable two DMA streams one for managing data transfer from + memory to peripheral (input stream) and another stream for managing data + transfer from peripheral to memory (output stream) + (+++) Associate the initialized DMA handle to the CRYP DMA handle + using __HAL_LINKDMA() + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the two DMA Streams. The output stream should have higher + priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() + + (#)Initialize the CRYP according to the specified parameters : + (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit. + (##) The key size: 128, 192 or 256. + (##) The AlgoMode AES Algorithm ECB/CBC/CTR/GCM or CCM. + (##) The initialization vector (counter). It is not used in ECB mode. + (##) The key buffer used for encryption/decryption. + (##) The Header used only in AES GCM and CCM Algorithm for authentication. + (##) The HeaderSize used to give size of header buffer in words or bytes, depending upon + HeaderWidthUnit field. + (##) The HeaderWidthUnit field. It specifies whether the header length + (##) The HeaderSize The size of header buffer in word. + (##) The B0 block is the first authentication block used only in AES CCM mode. + + (#)Three processing (encryption/decryption) functions are available: + (##) Polling mode: encryption and decryption APIs are blocking functions + i.e. they process the data and wait till the processing is finished, + e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt + (##) Interrupt mode: encryption and decryption APIs are not blocking functions + i.e. they process the data under interrupt, + e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT + (##) DMA mode: encryption and decryption APIs are not blocking functions + i.e. the data transfer is ensured by DMA, + e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA + + (#)When the processing function is called at first time after HAL_CRYP_Init() + the CRYP peripheral is configured and processes the buffer in input. + At second call, no need to Initialize the CRYP, user have to get current configuration via + HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set + new parameters, finally user can start encryption/decryption. + + (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. + + (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt() + without having to configure again the Key or the Initialization Vector between each API call, + the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE. + Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), + HAL_CRYP_Encrypt_DMA()or HAL_CRYP_Decrypt_DMA(). + + [..] + The cryptographic processor supports following standards: + (#) The advanced encryption standard (AES) supported by CRYP: + (##)128-bit data block processing + (##) chaining modes supported : + (+++) Electronic Code Book(ECB) + (+++) Cipher Block Chaining (CBC) + (+++) Counter mode (CTR) + (+++) Galois/counter mode (GCM/GMAC) + (+++) Counter with Cipher Block Chaining-Message(CCM) + (##) keys length Supported : + (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit. + + [..] This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP: + (#) Algorithm supported : + (##) Galois/counter mode (GCM) + (##) Galois message authentication code (GMAC) :is exactly the same as + GCM algorithm composed only by an header. + (#) Four phases are performed in GCM : + (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing + (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash + computation only. + (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream + encryption + data XORing. It works in a similar way for ciphertext (C). + (##) Final phase: IP generates the authenticated tag (T) using the last block of data. + HAL_CRYPEx_AESGCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond + to the Tag. user should consider only part of this 4 words, if Tag length is less than 128 bits. + (#) structure of message construction in GCM is defined as below : + (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter + (##) The authenticated header A (also knows as Additional Authentication Data AAD) + this part of the message is only authenticated, not encrypted. + (##) The plaintext message P is both authenticated and encrypted as ciphertext. + GCM standard specifies that ciphertext has same bit length as the plaintext. + (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext + (on 64 bits) + + [..] This section describe The AES Counter with Cipher Block Chaining-Message + Authentication Code (CCM) supported by both CRYP IP: + (#) Specific parameters for CCM : + + (##) B0 block : According to NIST Special Publication 800-38C, + The first block B0 is formatted as follows, where l(m) is encoded in + most-significant-byte first order(see below table 3) + + (+++) Q: a bit string representation of the octet length of P (plaintext) + (+++) q The octet length of the binary representation of the octet length of the payload + (+++) A nonce (N), n The octet length of the where n+q=15. + (+++) Flags: most significant octet containing four flags for control information, + (+++) t The octet length of the MAC. + (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A) + the associated data length expressed in bytes (a) defined as below: + (+++) If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets + (+++) If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets + (+++) If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets + (##) CTRx block : control blocks + (+++) Generation of CTR1 from first block B0 information : + equal to B0 with first 5 bits zeroed and most significant bits storing octet + length of P also zeroed, then incremented by one ( see below Table 4) + (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero. + + (#) Four phases are performed in CCM for CRYP IP: + (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing + (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash + computation only. + (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream + encryption + data XORing. It works in a similar way for ciphertext (C). + (##) Final phase: IP generates the authenticated tag (T) using the last block of data. + HAL_CRYPEx_AESCCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond to the Tag. + user should consider only part of this 4 words, if Tag length is less than 128 bits + + *** Callback registration *** + ============================= + + [..] + The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() + to register an interrupt callback. + + [..] + Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks: + (+) InCpltCallback : Input FIFO transfer completed callback. + (+) OutCpltCallback : Output FIFO transfer completed callback. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : CRYP MspInit. + (+) MspDeInitCallback : CRYP MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) InCpltCallback : Input FIFO transfer completed callback. + (+) OutCpltCallback : Output FIFO transfer completed callback. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : CRYP MspInit. + (+) MspDeInitCallback : CRYP MspDeInit. + + [..] + By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET + all callbacks are set to the corresponding weak functions : + examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit() + keep and use the user MspInit/MspDeInit functions (registered beforehand) + + [..] + Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only. + Exception done MspInit/MspDeInit callbacks that can be registered/unregistered + in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit() + or @ref HAL_CRYP_Init() function. + + [..] + When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + + Table 1. Initial Counter Block (ICB) + +-------------------------------------------------------+ + | Initialization vector (IV) | Counter | + |----------------|----------------|-----------|---------| + 127 95 63 31 0 + + + Bit Number Register Contents + ---------- --------------- ----------- + 127 ...96 CRYP_IV1R[31:0] ICB[127:96] + 95 ...64 CRYP_IV1L[31:0] B0[95:64] + 63 ... 32 CRYP_IV0R[31:0] ICB[63:32] + 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2 + + Table 2. GCM last block definition + + +-------------------------------------------------------------------+ + | Bit[0] | Bit[32] | Bit[64] | Bit[96] | + |-----------|--------------------|-----------|----------------------| + | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] | + |-----------|--------------------|-----------|----------------------| + + Table 3. B0 block + Octet Number Contents + ------------ --------- + 0 Flags + 1 ... 15-q Nonce N + 16-q ... 15 Q + + the Flags field is formatted as follows: + + Bit Number Contents + ---------- ---------------------- + 7 Reserved (always zero) + 6 Adata + 5 ... 3 (t-2)/2 + 2 ... 0 [q-1]3 + + Table 4. CTRx block + Bit Number Register Contents + ---------- --------------- ----------- + 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for + bit 0 that is set to 1 + 95 ...64 CRYP_IV1L[31:0] B0[95:64] + 63 ... 32 CRYP_IV0R[31:0] B0[63:32] + 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0 + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#if defined (CRYP) + +/** @defgroup CRYP CRYP + * @brief CRYP HAL module driver. + * @{ + */ + + +#ifdef HAL_CRYP_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup CRYP_Private_Defines + * @{ + */ +#define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/ +#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is + 299 clock cycles.*/ +#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/ + +#define CRYP_GENERAL_TIMEOUT 500U + +#define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */ +#define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */ +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) +#define CRYP_PHASE_HEADER_SUSPENDED 0x00000004U /*!< GCM/GMAC/CCM header phase is suspended */ +#define CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U /*!< GCM/CCM payload phase is suspended */ +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ +#define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in + DMA mode */ + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) +#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ +#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */ +#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */ +#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */ +#endif /* USE_HAL_CRYP_ONLY */ + +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +#define SAES_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ +#define SAES_PHASE_HEADER SAES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */ +#define SAES_PHASE_PAYLOAD SAES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */ +#define SAES_PHASE_FINAL SAES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */ +#endif /* USE_HAL_SAES_ONLY */ + +/* CTR1 information to use in CCM algorithm */ +#define CRYP_CCM_CTR1_0 0x07FFFFFFU +#define CRYP_CCM_CTR1_1 0xFFFFFF00U +#define CRYP_CCM_CTR1_2 0x00000001U + +#define IT_SUSPENDED 0x00000000U +#define DMA_SUSPENDED 0x00000001U + +#define ALGOMODE_CRYP_TO_CHMOD_SAES 0 +#define ALGOMODE_SAES_TO_CHMOD_CRYP 1 +/** + * @} + */ + + +/* Private macro -------------------------------------------------------------*/ +/** @addtogroup CRYP_Private_Macros + * @{ + */ + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) +#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{MODIFY_REG(((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR, \ + CRYP_CR_GCM_CCMPH, (__PHASE__)); \ + }while(0) +#endif /* USE_HAL_CRYP_ONLY */ + +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +#define SAES_SET_PHASE(__HANDLE__, __PHASE__) do{MODIFY_REG(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, \ + SAES_CR_GCMPH, (__PHASE__)); \ + }while(0) +#endif /* USE_HAL_SAES_ONLY */ + +#define HAL_CRYP_FIFO_FLUSH(__HANDLE__) (((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR |= CRYP_CR_FFLUSH) + + +/** + * @} + */ + +/* Private struct -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup CRYP_Private_Functions_prototypes + * @{ + */ + +static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr); +static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma); +static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma); +static void CRYP_DMAError(DMA_HandleTypeDef *hdma); +static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize); +static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp); +static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp); +static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp); +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) +static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +#endif /* USE_HAL_CRYP_ONLY */ +static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +static HAL_StatusTypeDef CRYP_WaitOnCCFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +#endif /* USE_HAL_SAES_ONLY */ +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) +static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output); +static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input); +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) +static void CRYP_Read_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t Algorithm); +#endif /* USE_HAL_CRYP_ONLY */ +static void CRYP_Write_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t Algorithm); +static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +static uint32_t CRYP_SAES_AlgoConversion(uint32_t algo, uint32_t order); +#endif /* USE_HAL_SAES_ONLY */ +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup CRYP_Exported_Functions CRYP Exported Functions + * @{ + */ + + +/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief CRYP Initialization and Configuration functions. + * +@verbatim + ======================================================================================== + ##### Initialization, de-initialization and Set and Get configuration functions ##### + ======================================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CRYP + (+) DeInitialize the CRYP + (+) Initialize the CRYP MSP + (+) DeInitialize the CRYP MSP + (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef + Parameters which are configured in This section are : + (++) Key size + (++) Data Type : 32, 16, 8 or 1 bit + ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard. + (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef + + +@endverbatim + * @{ + */ + + +/** + * @brief Initializes the CRYP according to the specified + * parameters in the CRYP_ConfigTypeDef and creates the associated handle. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) +{ + /* Check the CRYP handle allocation */ + if (hcryp == NULL) + { + return HAL_ERROR; + } + +#if ((USE_HAL_CRYP_ONLY == 1) && (USE_HAL_SAES_ONLY == 0)) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + return HAL_ERROR; + } +#endif /* USE_HAL_CRYP_ONLY */ + +#if ((USE_HAL_CRYP_ONLY == 0) && (USE_HAL_SAES_ONLY == 1)) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + return HAL_ERROR; + } +#endif /* USE_HAL_SAES_ONLY */ + + /* Check parameters */ +#ifdef USE_FULL_ASSERT +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize)); + assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm)); + assert_param(IS_CRYP_KEYMODE(hcryp->Init.KeyMode)); + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE) + { + return HAL_ERROR; /* CRYP does not support BYTE as header width unit */ + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + assert_param(IS_SAES_KEYSIZE(hcryp->Init.KeySize)); + assert_param(IS_SAES_ALGORITHM(hcryp->Init.Algorithm)); + assert_param(IS_SAES_KEYMODE(hcryp->Init.KeyMode)); + assert_param(IS_SAES_KEYSEL(hcryp->Init.KeySelect)); + } +#endif /* USE_HAL_SAES_ONLY */ + assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType)); + assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip)); +#endif /* USE_FULL_ASSERT */ + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + if (hcryp->State == HAL_CRYP_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcryp->Lock = HAL_UNLOCKED; + + hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy InCpltCallback */ + hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy OutCpltCallback */ + hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy ErrorCallback */ + + if (hcryp->MspInitCallback == NULL) + { + hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy MspInit */ + } + + /* Init the low level hardware */ + hcryp->MspInitCallback(hcryp); + } +#else + if (hcryp->State == HAL_CRYP_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcryp->Lock = HAL_UNLOCKED; + + /* Init the low level hardware */ + HAL_CRYP_MspInit(hcryp); + } +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + + /* Set the key size, data type and algorithm */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, + CRYP_CR_KMOD | CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, + hcryp->Init.KeyMode | hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Wait for BUSY flag to go to 0 */ + if (CRYP_WaitOnBUSYFlag(hcryp, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, + SAES_CR_KEYSEL | SAES_CR_KMOD | SAES_CR_DATATYPE | SAES_CR_KEYSIZE | SAES_CR_CHMOD, + hcryp->Init.KeySelect | hcryp->Init.KeyMode | SAES_CONV_DATATYPE(hcryp->Init.DataType) | \ + SAES_CONV_KEYSIZE(hcryp->Init.KeySize) | CRYP_SAES_AlgoConversion(hcryp->Init.Algorithm, + ALGOMODE_CRYP_TO_CHMOD_SAES)); + } +#endif /* USE_HAL_CRYP_ONLY */ + + /* Read Device ID to indicate CRYP1 IP Version */ + hcryp->Version = HAL_GetREVID(); + + /* Reset Error Code field */ + hcryp->ErrorCode = HAL_CRYP_ERROR_NONE; + + /* Reset peripheral Key and IV configuration flag */ + hcryp->KeyIVConfig = 0U; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Set the default CRYP phase */ + hcryp->Phase = CRYP_PHASE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief De-Initializes the CRYP peripheral. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) +{ + /* Check the CRYP handle allocation */ + if (hcryp == NULL) + { + return HAL_ERROR; + } + +#if ((USE_HAL_CRYP_ONLY == 1) && (USE_HAL_SAES_ONLY == 0)) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + return HAL_ERROR; + } +#endif /* USE_HAL_CRYP_ONLY */ + +#if ((USE_HAL_CRYP_ONLY == 0) && (USE_HAL_SAES_ONLY == 1)) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + return HAL_ERROR; + } +#endif /* USE_HAL_SAES_ONLY */ + + /* Set the default CRYP phase */ + hcryp->Phase = CRYP_PHASE_READY; + + /* Reset CrypInCount and CrypOutCount */ + hcryp->CrypInCount = 0; + hcryp->CrypOutCount = 0; + hcryp->CrypHeaderCount = 0; + + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + if (hcryp->MspDeInitCallback == NULL) + { + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy MspDeInit */ + } + /* DeInit the low level hardware */ + hcryp->MspDeInitCallback(hcryp); + +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_CRYP_MspDeInit(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the CRYP according to the specified + * parameters in the CRYP_ConfigTypeDef + * @param hcryp: pointer to a CRYP_HandleTypeDef structure + * @param pConf: pointer to a CRYP_ConfigTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf) +{ + /* Check the CRYP handle allocation */ + if ((hcryp == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ +#ifdef USE_FULL_ASSERT +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + assert_param(IS_CRYP_KEYSIZE(pConf->KeySize)); + assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm)); + assert_param(IS_CRYP_KEYMODE(pConf->KeyMode)); + if (pConf->HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE) + { + return HAL_ERROR; /* CRYP does not support BYTE as header width unit */ + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + assert_param(IS_SAES_KEYSIZE(pConf->KeySize)); + assert_param(IS_SAES_ALGORITHM(pConf->Algorithm)); + assert_param(IS_SAES_KEYMODE(pConf->KeyMode)); + assert_param(IS_SAES_KEYSEL(pConf->KeySelect)); + } +#endif /* USE_HAL_SAES_ONLY */ + assert_param(IS_CRYP_DATATYPE(pConf->DataType)); + assert_param(IS_CRYP_INIT(pConf->KeyIVConfigSkip)); +#endif /* USE_FULL_ASSERT */ + + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Process locked */ + __HAL_LOCK(hcryp); + + /* Set CRYP parameters */ + hcryp->Init.DataType = pConf->DataType; + hcryp->Init.pKey = pConf->pKey; + hcryp->Init.Algorithm = pConf->Algorithm; + hcryp->Init.KeySize = pConf->KeySize; + hcryp->Init.pInitVect = pConf->pInitVect; + hcryp->Init.Header = pConf->Header; + hcryp->Init.HeaderSize = pConf->HeaderSize; + hcryp->Init.B0 = pConf->B0; + hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; + hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit; + hcryp->Init.KeyMode = pConf->KeyMode; + hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; + hcryp->Init.KeySelect = pConf->KeySelect; + + /* Set the key size, data type, algo Mode and operating mode*/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /*in case of HSW, HW, SW or AHK key selection, we should specify Key mode selection (SAES_CR_KMOD) */ + if ((hcryp->Init.KeySelect != CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_WRAPPED)) + { + /* Set key mode selection (Normal, Wrapped or Shared key )*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_WRAPPED); + } + + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, \ + SAES_CR_KEYSEL | SAES_CR_KMOD | SAES_CR_DATATYPE | SAES_CR_KEYSIZE | SAES_CR_CHMOD, + hcryp->Init.KeySelect | hcryp->Init.KeyMode | SAES_CONV_DATATYPE(hcryp->Init.DataType) | \ + SAES_CONV_KEYSIZE(hcryp->Init.KeySize) | CRYP_SAES_AlgoConversion(hcryp->Init.Algorithm, + ALGOMODE_CRYP_TO_CHMOD_SAES)); + } +#endif /* USE_HAL_SAES_ONLY */ + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Reset Error Code field */ + hcryp->ErrorCode = HAL_CRYP_ERROR_NONE; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Set the default CRYP phase */ + hcryp->Phase = CRYP_PHASE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Get CRYP Configuration parameters in associated handle. + * @param pConf: pointer to a CRYP_ConfigTypeDef structure + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf) +{ + /* Check the CRYP handle allocation */ + if ((hcryp == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Process locked */ + __HAL_LOCK(hcryp); + + /* Get CRYP parameters */ + pConf->DataType = hcryp->Init.DataType; + pConf->pKey = hcryp->Init.pKey; + pConf->Algorithm = hcryp->Init.Algorithm; + pConf->KeySize = hcryp->Init.KeySize ; + pConf->pInitVect = hcryp->Init.pInitVect; + pConf->Header = hcryp->Init.Header ; + pConf->HeaderSize = hcryp->Init.HeaderSize; + pConf->B0 = hcryp->Init.B0; + pConf->DataWidthUnit = hcryp->Init.DataWidthUnit; + pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit; + pConf->KeyMode = hcryp->Init.KeyMode; + pConf->KeySelect = hcryp->Init.KeySelect; + pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } +} +/** + * @brief Initializes the CRYP MSP. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CRYP_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes CRYP MSP. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CRYP_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User CRYP Callback + * To be used instead of the weak predefined callback + * @param hcryp cryp handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID + * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID + * @arg @ref HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID + * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, + pCRYP_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hcryp); + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + switch (CallbackID) + { + case HAL_CRYP_INPUT_COMPLETE_CB_ID : + hcryp->InCpltCallback = pCallback; + break; + + case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : + hcryp->OutCpltCallback = pCallback; + break; + + case HAL_CRYP_ERROR_CB_ID : + hcryp->ErrorCallback = pCallback; + break; + + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = pCallback; + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcryp->State == HAL_CRYP_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = pCallback; + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hcryp); + + return status; +} + +/** + * @brief Unregister an CRYP Callback + * CRYP callback is redirected to the weak predefined callback + * @param hcryp cryp handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID + * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID + * @arg @ref HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID + * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hcryp); + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + switch (CallbackID) + { + case HAL_CRYP_INPUT_COMPLETE_CB_ID : + hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy InCpltCallback */ + break; + + case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : + hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy OutCpltCallback */ + break; + + case HAL_CRYP_ERROR_CB_ID : + hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy ErrorCallback */ + break; + + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = HAL_CRYP_MspInit; + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcryp->State == HAL_CRYP_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = HAL_CRYP_MspInit; + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hcryp); + + return status; +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) +/** + * @brief Request CRYP processing suspension when in interruption mode. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @note Set the handle field SuspendRequest to the appropriate value so that + * the on-going CRYP processing is suspended as soon as the required + * conditions are met. + * @note HAL_CRYP_ProcessSuspend() can only be invoked when the processing is done + * in non-blocking interrupt mode. + * @retval None + */ +void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp) +{ + /* Set Handle SuspendRequest field */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND; +} + +/** + * @brief Request CRYP processing suspension when in DMA mode. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @note Set the handle field SuspendRequest to the appropriate value so that + * the on-going CRYP processing is suspended as soon as the required + * conditions are met. + * @note HAL_CRYP_ProcessSuspend() can only be invoked when the processing is done + * in non-blocking DMA mode. + * @retval None + */ +HAL_StatusTypeDef HAL_CRYP_DMAProcessSuspend(CRYP_HandleTypeDef *hcryp) +{ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + uint32_t Timeout = CRYP_GENERAL_TIMEOUT; +#endif /* USE_HAL_SAES_ONLY */ + uint32_t tmp_remaining_DMATransferSize_inWords; + uint32_t tmp_initial_DMATransferSize_inWords; + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* Stop the DMA transfers to the IN FIFO by clearing to 0 the DIEN bit in + the CRYP_DMACR register */ + ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (~CRYP_DMACR_DIEN); + + /* Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the + CRYP_SR) and the BUSY bit is cleared */ + while (((((CRYP_TypeDef *)(hcryp->Instance))->SR) & (CRYP_SR_IFEM | CRYP_SR_OFNE | CRYP_SR_BUSY)) != CRYP_SR_IFEM) + { + /* nothing todo */ + } + + /* Stop the DMA transfers from the OUT FIFO by clearing to 0 the DOEN + bit in the CRYP_DMACR register */ + ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (~CRYP_DMACR_DOEN); + + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Stop the DMA transfer to the IN FIFO by clearing the DMAINEN bit of the SAES_CR register */ + (((SAES_TypeDef *)(hcryp->Instance)))->CR &= (~SAES_CR_DMAINEN); + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + /*Call registered error callback*/ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + /* Stop the DMA transfer from the OUT FIFO by clearing the DMAOUTEN bit of the SAES_CR register */ + ((SAES_TypeDef *)(hcryp->Instance))->CR &= (~SAES_CR_DMAOUTEN); + + /* Clear the CCF flag by setting the CCF bit of the SAES_ICR register */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } +#endif /* USE_HAL_SAES_ONLY */ + + /* At this point, DMA interface is disabled and no transfer is on-going */ + /* Retrieve from the DMA handle how many words remain to be read and written */ + /* DMA3 used, DMA_CBR1_BNDT in bytes, DMA_CSR_FIFOL in words */ + tmp_remaining_DMATransferSize_inWords = ((((DMA_Channel_TypeDef *)hcryp->hdmain->Instance)->CBR1) & \ + DMA_CBR1_BNDT) / 4U; + tmp_remaining_DMATransferSize_inWords += ((((DMA_Channel_TypeDef *)hcryp->hdmain->Instance)->CSR) & \ + DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos; + + /* Disable DMA channels */ + /* Note that the Abort function will + - Clear the transfer error flags + - Unlock + - Set the State + */ + if (HAL_DMA_Abort(hcryp->hdmain) != HAL_OK) + { + return HAL_ERROR; + } + if (HAL_DMA_Abort(hcryp->hdmaout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Compute how many words were supposed to be transferred by DMA */ + /* hcryp->CrypInCount is in bytes, must be a multiple of 4 (no padding handled for ECB or CBC) */ + tmp_initial_DMATransferSize_inWords = ((uint32_t) hcryp->Size / 4U); + + /* Accordingly, update the input and output pointers that points at the next word to be + transferred to the Peripheral by DMA or read from the Peripheral by the DMA */ + hcryp->pCrypInBuffPtr += (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ; + hcryp->pCrypOutBuffPtr += (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ; + + /* And store in CrypInCount the remaining size to transfer (in words) */ + hcryp->CrypInCount = (uint16_t)tmp_remaining_DMATransferSize_inWords; + hcryp->CrypOutCount = (uint16_t)tmp_remaining_DMATransferSize_inWords; + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + + return HAL_OK; + +} + + +/** + * @brief CRYP processing suspension and peripheral internal parameters storage. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @note peripheral internal parameters are stored to be readily available when + * suspended processing is resumed later on. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp) +{ + HAL_CRYP_STATETypeDef state; + uint32_t tmp_SAES_CR_DMAIN_bit; + + /* Request suspension */ + /* Check whether the processing is in DMA mode or not */ + tmp_SAES_CR_DMAIN_bit = (((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_DMAINEN); + if ((((((CRYP_TypeDef *)(hcryp->Instance))->DMACR & CRYP_DMACR_DIEN) == CRYP_DMACR_DIEN) \ + && (IS_CRYP_INSTANCE(hcryp->Instance))) || \ + ((tmp_SAES_CR_DMAIN_bit == SAES_CR_DMAINEN) && (IS_SAES_INSTANCE(hcryp->Instance)))) + { + if (HAL_CRYP_DMAProcessSuspend(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + hcryp->SuspendedProcessing = DMA_SUSPENDED; + } + else + { + HAL_CRYP_ProcessSuspend(hcryp); + hcryp->SuspendedProcessing = IT_SUSPENDED; + } + + do + { + state = HAL_CRYP_GetState(hcryp); + } while ((state != HAL_CRYP_STATE_SUSPENDED) && (state != HAL_CRYP_STATE_READY)); + + /* Make sure there is no unwanted suspension */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + + if (HAL_CRYP_GetState(hcryp) == HAL_CRYP_STATE_READY) + { + /* Processing was already over or was about to end. No suspension done */ + return HAL_ERROR; + } + else + { + if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \ + (hcryp->Init.Algorithm == CRYP_AES_CTR) || \ + (hcryp->Init.Algorithm == CRYP_AES_GCM) || \ + (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + /* Save Initialisation Vector registers */ + CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved); + } + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* Save Control register */ + hcryp->CR_saved = ((CRYP_TypeDef *)(hcryp->Instance))->CR; + + /* Save context swap registers */ + if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + CRYP_Read_ContextSwapRegisters(hcryp, hcryp->SUSPxR_saved, hcryp->Init.Algorithm); + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Disable AES */ + __HAL_CRYP_DISABLE(hcryp); + + /* Clear keys */ + ((SAES_TypeDef *)(hcryp->Instance))->KEYR7 = 0x0U; + ((SAES_TypeDef *)(hcryp->Instance))->KEYR6 = 0x0U; + ((SAES_TypeDef *)(hcryp->Instance))->KEYR5 = 0x0U; + ((SAES_TypeDef *)(hcryp->Instance))->KEYR4 = 0x0U; + ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = 0x0U; + ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = 0x0U; + ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = 0x0U; + ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = 0x0U; + + /* Save Control register */ + hcryp->CR_saved = ((SAES_TypeDef *)(hcryp->Instance))->CR; + } +#endif /* USE_HAL_SAES_ONLY */ + + /* Save low-priority block CRYP handle parameters */ + hcryp->Init_saved = hcryp->Init; + hcryp->pCrypInBuffPtr_saved = hcryp->pCrypInBuffPtr; + hcryp->pCrypOutBuffPtr_saved = hcryp->pCrypOutBuffPtr; + hcryp->CrypInCount_saved = hcryp->CrypInCount; + hcryp->CrypOutCount_saved = hcryp->CrypOutCount; + hcryp->Phase_saved = hcryp->Phase; + hcryp->State_saved = hcryp->State; + hcryp->Size_saved = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? \ + (hcryp->Size / 4U) : hcryp->Size); + hcryp->SizesSum_saved = hcryp->SizesSum; + hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount; + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + } + return HAL_OK; +} + + +/** + * @brief CRYP processing resumption. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @note Processing restarts at the exact point where it was suspended, based + * on the parameters saved at suspension time. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) +{ + /* Check the CRYP handle allocation */ + if (hcryp == NULL) + { + return HAL_ERROR; + } + + if (hcryp->State_saved != HAL_CRYP_STATE_SUSPENDED) + { + /* CRYP was not suspended */ + return HAL_ERROR; + } + else + { + /* Restore low-priority block CRYP handle parameters */ + hcryp->Init = hcryp->Init_saved; + hcryp->State = hcryp->State_saved; + hcryp->Phase = hcryp->Phase_saved; + hcryp->CrypHeaderCount = hcryp->CrypHeaderCount_saved; + + /* Restore low-priority block CRYP handle parameters */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + hcryp->Init.pInitVect = hcryp->IV_saved; + } + /* Set State to reset to trigger a HAL_CRYP_MspInit() call in HAL_CRYP_Init() */ + __HAL_CRYP_RESET_HANDLE_STATE(hcryp); +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + ((CRYP_TypeDef *)(hcryp->Instance))->CR |= CRYP_CR_IPRST; + ((CRYP_TypeDef *)(hcryp->Instance))->CR &= (~CRYP_CR_IPRST); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + ((SAES_TypeDef *)(hcryp->Instance))->CR |= SAES_CR_IPRST; + ((SAES_TypeDef *)(hcryp->Instance))->CR &= (~SAES_CR_IPRST); + } +#endif /* USE_HAL_SAES_ONLY */ + + /* Peripheral must be disabled */ + __HAL_CRYP_DISABLE(hcryp); + + if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || \ + (hcryp->Init.Algorithm == CRYP_AES_CBC) || \ + (hcryp->Init.Algorithm == CRYP_AES_CTR)) + { + (void) HAL_CRYP_Init(hcryp); + } + else + { + /* The following lines are applicable to CRYP peripheral only */ + + /* Configure again the cryptographic processor with the initial setting in CRYP_CR */ + ((CRYP_TypeDef *)(hcryp->Instance))->CR = hcryp->CR_saved; + + /* Configure again the key registers */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Restore context swap registers */ + CRYP_Write_ContextSwapRegisters(hcryp, hcryp->SUSPxR_saved, hcryp->Init.Algorithm); + + /* Restore IV registers */ + CRYP_Write_IVRegisters(hcryp, hcryp->IV_saved); + + /* At the same time, set handle state back to READY to be able to resume the AES calculations + without the processing APIs returning HAL_BUSY when called. */ + hcryp->State = HAL_CRYP_STATE_READY; + } + + if (hcryp->SuspendedProcessing == DMA_SUSPENDED) + { + if (((IS_CRYP_INSTANCE(hcryp->Instance)) && \ + (READ_BIT(hcryp->CR_saved, CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)) || \ + ((IS_SAES_INSTANCE(hcryp->Instance)) && \ + (READ_BIT(hcryp->CR_saved, SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT))) + { + if (HAL_CRYP_Encrypt_DMA(hcryp, hcryp->pCrypInBuffPtr_saved, (uint16_t) hcryp->CrypInCount_saved, + hcryp->pCrypOutBuffPtr_saved) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { + if (HAL_CRYP_Decrypt_DMA(hcryp, hcryp->pCrypInBuffPtr_saved, (uint16_t) hcryp->CrypInCount_saved, + hcryp->pCrypOutBuffPtr_saved) != HAL_OK) + { + return HAL_ERROR; + } + } + } + else + { + /* Resume low-priority block processing under IT */ + hcryp->ResumingFlag = 1U; + + if (((IS_CRYP_INSTANCE(hcryp->Instance)) && + (READ_BIT(hcryp->CR_saved, CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)) || \ + ((IS_SAES_INSTANCE(hcryp->Instance)) && \ + (READ_BIT(hcryp->CR_saved, SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT))) + { + if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, + hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { + if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, + hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK) + { + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + +/** + * @} + */ + +/** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions + * @brief CRYP processing functions. + * +@verbatim + ============================================================================== + ##### Encrypt Decrypt functions ##### + ============================================================================== + [..] This section provides API allowing to Encrypt/Decrypt Data following + Standard AES algorithm configured by the user: + + (+) Standard AES supported by CRYP1 IP, list of Algorithm supported: + (++) Electronic Code Book(ECB) + (++) Cipher Block Chaining (CBC) + (++) Counter mode (CTR) + (++) Cipher Block Chaining (CBC) + (++) Counter mode (CTR) + (++) Galois/counter mode (GCM) + (++) Counter with Cipher Block Chaining-Message(CCM) + [..] Three processing functions are available: + (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt + (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT + (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA + +@endverbatim + * @{ + */ + + +/** + * @brief Encryption mode. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Input: Pointer to the input buffer (plaintext) + * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit. + * @param Output: Pointer to the output buffer(ciphertext) + * @param Timeout: Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout) +{ + uint32_t algo = 0U; + HAL_StatusTypeDef status; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Process locked */ + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = Input; + hcryp->pCrypOutBuffPtr = Output; + + /* Calculate Size parameter in Byte*/ + if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) + { + hcryp->Size = Size * 4U; + } + else + { + hcryp->Size = Size; + } + + /* Set Encryption operating mode*/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT); + + /* algo get algorithm selected */ + algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE; + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_ENCRYPT); + + /* algo get algorithm selected */ + algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD), + ALGOMODE_SAES_TO_CHMOD_CRYP); + } +#endif /* USE_HAL_SAES_ONLY */ + + switch (algo) + { + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: + + /* AES encryption */ + status = CRYP_AES_Encrypt(hcryp, Timeout); + break; + + case CRYP_AES_GCM: + + /* AES GCM encryption */ + status = CRYP_AESGCM_Process(hcryp, Timeout); + break; + + case CRYP_AES_CCM: + + /* AES CCM encryption */ + status = CRYP_AESCCM_Process(hcryp, Timeout); + break; + + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return function status */ + return status ; +} + +/** + * @brief Decryption mode. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Input: Pointer to the input buffer (ciphertext ) + * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit + * @param Output: Pointer to the output buffer(plaintext) + * @param Timeout: Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t algo = 0U; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Process locked */ + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = Input; + hcryp->pCrypOutBuffPtr = Output; + + /* Calculate Size parameter in Byte*/ + if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) + { + hcryp->Size = Size * 4U; + } + else + { + hcryp->Size = Size; + } + + /* Set Decryption operating mode*/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT); + + /* algo get algorithm selected */ + algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE; + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT); + + /* algo get algorithm selected */ + algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD), + ALGOMODE_SAES_TO_CHMOD_CRYP); + } +#endif /* USE_HAL_SAES_ONLY */ + + switch (algo) + { + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: + + /* AES decryption */ + status = CRYP_AES_Decrypt(hcryp, Timeout); + break; + + case CRYP_AES_GCM: + + /* AES GCM decryption */ + status = CRYP_AESGCM_Process(hcryp, Timeout) ; + break; + + case CRYP_AES_CCM: + + /* AES CCM decryption */ + status = CRYP_AESCCM_Process(hcryp, Timeout); + break; + + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +/** + * @brief Encryption in interrupt mode. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Input: Pointer to the input buffer (plaintext) + * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit + * @param Output: Pointer to the output buffer(ciphertext) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output) +{ + uint32_t algo = 0U; + HAL_StatusTypeDef status; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Process locked */ + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/ +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + if (hcryp->ResumingFlag == 1U) + { + hcryp->ResumingFlag = 0U; + hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; + hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; + } + else +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } + + hcryp->pCrypInBuffPtr = Input; + hcryp->pCrypOutBuffPtr = Output; + + /* Calculate Size parameter in Byte*/ + if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) + { + hcryp->Size = Size * 4U; + } + else + { + hcryp->Size = Size; + } + + /* Set encryption operating mode*/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT); + + /* algo get algorithm selected */ + algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE; + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_ENCRYPT); + + /* algo get algorithm selected */ + algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD), + ALGOMODE_SAES_TO_CHMOD_CRYP); + } +#endif /* USE_HAL_SAES_ONLY */ + + switch (algo) + { + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: + + status = CRYP_AES_Encrypt_IT(hcryp); + break; + + case CRYP_AES_GCM: + + status = CRYP_AESGCM_Process_IT(hcryp) ; + break; + + case CRYP_AES_CCM: + + status = CRYP_AESCCM_Process_IT(hcryp); + break; + + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return function status */ + return status ; +} + +/** + * @brief Decryption in interrupt mode. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Input: Pointer to the input buffer (ciphertext ) + * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit + * @param Output: Pointer to the output buffer(plaintext) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output) +{ + uint32_t algo = 0U; + HAL_StatusTypeDef status; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Process locked */ + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/ +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + if (hcryp->ResumingFlag == 1U) + { + hcryp->ResumingFlag = 0U; + hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; + hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; + } + else +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } + hcryp->pCrypInBuffPtr = Input; + hcryp->pCrypOutBuffPtr = Output; + + /* Calculate Size parameter in Byte*/ + if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) + { + hcryp->Size = Size * 4U; + } + else + { + hcryp->Size = Size; + } + + /* Set decryption operating mode*/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT); + + /* algo get algorithm selected */ + algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE; + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT); + + /* algo get algorithm selected */ + algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD), + ALGOMODE_SAES_TO_CHMOD_CRYP); + } +#endif /* USE_HAL_SAES_ONLY */ + + switch (algo) + { + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: + + /* AES decryption */ + status = CRYP_AES_Decrypt_IT(hcryp); + break; + + case CRYP_AES_GCM: + + /* AES GCM decryption */ + status = CRYP_AESGCM_Process_IT(hcryp) ; + break; + + case CRYP_AES_CCM: + + /* AES CCMdecryption */ + status = CRYP_AESCCM_Process_IT(hcryp); + break; + + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +/** + * @brief Encryption in DMA mode. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Input: Pointer to the input buffer (plaintext) + * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit + * @param Output: Pointer to the output buffer(ciphertext) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t algo = 0U; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t tickstart; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Process locked */ + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = Input; + hcryp->pCrypOutBuffPtr = Output; + + /* Calculate Size parameter in Byte*/ + if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) + { + hcryp->Size = Size * 4U; + } + else + { + hcryp->Size = Size; + } + + /* Set Encryption operating mode*/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT); + + /* algo get algorithm selected */ + algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE; + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_ENCRYPT); + + /* algo get algorithm selected */ + algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD), + ALGOMODE_SAES_TO_CHMOD_CRYP); + } +#endif /* USE_HAL_SAES_ONLY */ + + switch (algo) + { + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if (DoKeyIVConfig == 1U) + { + /* Set the Key */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + while (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEYVALID) == 0x0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + + /* Set the Initialization Vector*/ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } +#endif /* USE_HAL_SAES_ONLY */ + } + + } /* if (DoKeyIVConfig == 1U) */ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Start DMA process transfer for AES */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size, (uint32_t)(hcryp->pCrypOutBuffPtr)); + break; + + case CRYP_AES_GCM: + + /* AES GCM encryption */ + status = CRYP_AESGCM_Process_DMA(hcryp); + break; + + case CRYP_AES_CCM: + + /* AES CCM encryption */ + status = CRYP_AESCCM_Process_DMA(hcryp); + break; + + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +/** + * @brief Decryption in DMA mode. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Input: Pointer to the input buffer (ciphertext ) + * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit + * @param Output: Pointer to the output buffer(plaintext) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output) +{ + uint32_t algo = 0U; + HAL_StatusTypeDef status; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Process locked */ + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = Input; + hcryp->pCrypOutBuffPtr = Output; + + /* Calculate Size parameter in Byte*/ + if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) + { + hcryp->Size = Size * 4U; + } + else + { + hcryp->Size = Size; + } + + /* Set decryption operating mode*/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT); + + /* algo get algorithm selected */ + algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE; + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT); + + /* algo get algorithm selected */ + algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD), + ALGOMODE_SAES_TO_CHMOD_CRYP); + } +#endif /* USE_HAL_SAES_ONLY */ + + switch (algo) + { + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: + + /* AES decryption */ + status = CRYP_AES_Decrypt_DMA(hcryp); + break; + + case CRYP_AES_GCM: + + /* AES GCM decryption */ + status = CRYP_AESGCM_Process_DMA(hcryp); + + break; + + case CRYP_AES_CCM: + + /* AES CCM decryption */ + status = CRYP_AESCCM_Process_DMA(hcryp); + break; + + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management + * @brief CRYP IRQ handler. + * +@verbatim + ============================================================================== + ##### CRYP IRQ handler management ##### + ============================================================================== +[..] This section provides CRYP IRQ handler and callback functions. + (+) HAL_CRYP_IRQHandler CRYP interrupt request + (+) HAL_CRYP_InCpltCallback input data transfer complete callback + (+) HAL_CRYP_OutCpltCallback output data transfer complete callback + (+) HAL_CRYP_ErrorCallback CRYP error callback + (+) HAL_CRYP_GetState return the CRYP state + (+) HAL_CRYP_GetError return the CRYP error code +@endverbatim + * @{ + */ + +/** + * @brief This function handles cryptographic interrupt request. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) +{ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + uint32_t itstatus = ((CRYP_TypeDef *)(hcryp->Instance))->MISR; + + if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U) + { + if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) + || (hcryp->Init.Algorithm == CRYP_AES_CTR)) + { + CRYP_AES_IT(hcryp); /*AES*/ + } + + else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + /* if header phase */ + if ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER) + { + CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); + } + else /* if payload phase */ + { + CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + } + } + else + { + /* Nothing to do */ + } + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Check if Read or write error occurred */ + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RWEIE) != RESET) + { + /* If write Error occurred */ + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_WRERR) != RESET) + { + hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); + } + /* If read Error occurred */ + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RDERR) != RESET) + { + hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); + } + /*Call error callback*/ + HAL_CRYP_ErrorCallback(hcryp); + } + /* Check if Key error occurred */ + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_KEIE) != RESET) + { + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEIF) != RESET) + { + hcryp->ErrorCode |= HAL_CRYP_ERROR_KEY; + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_KEIF); + /*Call error callback*/ + HAL_CRYP_ErrorCallback(hcryp); + } + } + /* Check if RNG error occurred */ + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RNGEIE) != RESET) + { + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RNGEIF) != RESET) + { + hcryp->ErrorCode |= HAL_CRYP_ERROR_RNG; + /*Call error callback*/ + HAL_CRYP_ErrorCallback(hcryp); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RNGEIF); + } + } + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET) + { + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) + { + /* Clear computation complete flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + /* if header phase */ + if ((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_PHASE_HEADER) == SAES_PHASE_HEADER) + { + CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); + } + else /* if payload phase */ + { + CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + } + } + else /* AES Algorithm ECB,CBC or CTR*/ + { + CRYP_AES_IT(hcryp); + } + } + } + } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */ +#endif /* USE_HAL_SAES_ONLY */ +} + +/** + * @brief Return the CRYP error code. + * @param hcryp : pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for the CRYP IP + * @retval CRYP error code + */ +uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp) +{ + return hcryp->ErrorCode; +} + +/** + * @brief Returns the CRYP state. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @retval HAL state + */ +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp) +{ + return hcryp->State; +} + +/** + * @brief Input FIFO transfer completed callback. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @retval None + */ +__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CRYP_InCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output FIFO transfer completed callback. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @retval None + */ +__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CRYP_OutCpltCallback could be implemented in the user file + */ +} + +/** + * @brief CRYP error callback. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @retval None + */ +__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CRYP_ErrorCallback could be implemented in the user file + */ +} +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup CRYP_Private_Functions + * @{ + */ + + +/** + * @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard + * @param hcryp: pointer to a CRYP_HandleTypeDef structure + * @param Timeout: specify Timeout value + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t tickstart; + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if (DoKeyIVConfig == 1U) + { + /* Set the Key */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + while (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEYVALID) == 0x0U) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + if (hcryp->Init.KeyMode == CRYP_KEYMODE_SHARED) + { + /* As KEYVALID is set, the key share target peripheral is initialized with a valid, shared key. + The application can proceed with the processing of data, setting KMOD[1:0]to 00 */ + CLEAR_BIT(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_KMOD); + } + } +#endif /* USE_HAL_CRYP_ONLY */ + + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } +#endif /* USE_HAL_SAES_ONLY */ + } + } /* if (DoKeyIVConfig == 1U) */ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + /*Temporary CrypOutCount Value */ + outcount = hcryp->CrypOutCount; + + while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U))) + { + /* Write plain Ddta and get cipher data */ + CRYP_AES_ProcessData(hcryp, Timeout); + /*Temporary CrypOutCount Value */ + outcount = hcryp->CrypOutCount; + } + + /* Disable CRYP */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t tickstart; + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if (DoKeyIVConfig == 1U) + { + /* Set the Key */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + while (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEYVALID) == 0x0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + if (hcryp->Init.KeyMode == CRYP_KEYMODE_SHARED) + { + /* As KEYVALID is set, the key share target peripheral is initialized with a valid, shared key. + The application can proceed with the processing of data, setting KMOD[1:0]to 00 */ + CLEAR_BIT(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_KMOD); + } + } +#endif /* USE_HAL_CRYP_ONLY */ + + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } +#endif /* USE_HAL_SAES_ONLY */ + } + } /* if (DoKeyIVConfig == 1U) */ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + if (hcryp->Size != 0U) + { + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Write the input block in the IN FIFO */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } +#endif /* USE_HAL_SAES_ONLY */ + + /* Enable interrupts */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE | CRYP_IT_RNGEIE); + } +#endif /* USE_HAL_SAES_ONLY */ + } + else + { + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Decryption in ECB/CBC & CTR mode with AES Standard + * @param hcryp: pointer to a CRYP_HandleTypeDef structure + * @param Timeout: Specify Timeout value + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if (DoKeyIVConfig == 1U) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ + { +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* change ALGOMODE to key preparation for decryption*/ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, CRYP_AES_KEY); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for BUSY flag go to 0 */ + if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Turn back to ALGOMODE of the configuration */ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* When KMOD[1:0] = 01 (wrapped key) or KMOD[1:0] = 01 (shared key) + and MODE[1:0] = 10 (decryption), then a read access to + SAES_DOUTR register triggers a read error (RDERR). So, clear KMOD for the upcoming deciphering */ + if (((((SAES_TypeDef *)(hcryp->Instance))->CR) & (CRYP_KEYMODE_WRAPPED | CRYP_KEYMODE_SHARED)) != 0U) + { + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_NORMAL); + } + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_KEY_DERIVATION); + + /* we should re-write Key, in the case where we change key after first operation*/ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } + + /* Enable SAES */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state & update error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* End of Key preparation for ECB/CBC */ + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT); + } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */ +#endif /* USE_HAL_SAES_ONLY */ + } + else /*Algorithm CTR */ + { +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED; + } + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } +#endif /* USE_HAL_SAES_ONLY */ + } + + /* Set IV */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } +#endif /* USE_HAL_SAES_ONLY */ + } + } /* if (DoKeyIVConfig == 1U) */ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /*Temporary CrypOutCount Value */ + outcount = hcryp->CrypOutCount; + + while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U))) + { + /* Write plain data and get cipher data */ + CRYP_AES_ProcessData(hcryp, Timeout); + /*Temporary CrypOutCount Value */ + outcount = hcryp->CrypOutCount; + } + + /* Disable CRYP */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Return function status */ + return HAL_OK; +} +/** + * @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t Timeout = CRYP_GENERAL_TIMEOUT; + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if (DoKeyIVConfig == 1U) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) + { +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* change ALGOMODE to key preparation for decryption*/ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, CRYP_AES_KEY); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED; + } + } + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for BUSY flag go to 0 */ + if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + + /* Turn back to ALGOMODE of the configuration */ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* When KMOD[1:0] = 01 (wrapped key) or KMOD[1:0] = 01 (shared key) + and MODE[1:0] = 10 (decryption), then a read access to + SAES_DOUTR register triggers a read error (RDERR). So, clear KMOD for the upcoming deciphering */ + if (((((SAES_TypeDef *)(hcryp->Instance))->CR) & (CRYP_KEYMODE_WRAPPED | CRYP_KEYMODE_SHARED)) != 0U) + { + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_NORMAL); + } + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_KEY_DERIVATION); + + /* we should re-write Key, in the case where we change key after first operation*/ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } + + /* Enable SAES */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state & update error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* End of Key preparation for ECB/CBC */ + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT); + } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */ +#endif /* USE_HAL_SAES_ONLY */ + } + else /*Algorithm CTR */ + { +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED; + } + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } +#endif /* USE_HAL_SAES_ONLY */ + } /* if (hcryp->Init.Algorithm != CRYP_AES_CTR) */ + + /* Set IV */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } +#endif /* USE_HAL_SAES_ONLY */ + } + } /* if (DoKeyIVConfig == 1U) */ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + if (hcryp->Size != 0U) + { + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Write the input block in the IN FIFO */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } +#endif /* USE_HAL_SAES_ONLY */ + + /* Enable interrupts */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE | CRYP_IT_RNGEIE); + } +#endif /* USE_HAL_SAES_ONLY */ + } + else + { + /* Process locked */ + __HAL_UNLOCK(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) +{ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t Timeout = CRYP_GENERAL_TIMEOUT; + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if (DoKeyIVConfig == 1U) + { + if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ + { + /* Key preparation for ECB/CBC */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* change ALGOMODE to key preparation for decryption*/ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, CRYP_AES_KEY); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED; + } + } + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for BUSY flag go to 0 */ + if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Turn back to ALGOMODE of the configuration */ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* When KMOD[1:0] = 01 (wrapped key) or KMOD[1:0] = 01 (shared key) + and MODE[1:0] = 10 (decryption), then a read access to + SAES_DOUTR register triggers a read error (RDERR). So, clear KMOD for the upcoming deciphering */ + if (((((SAES_TypeDef *)(hcryp->Instance))->CR) & (CRYP_KEYMODE_WRAPPED | CRYP_KEYMODE_SHARED)) != 0U) + { + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_NORMAL); + } + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_KEY_DERIVATION); + + /* we should re-write Key, in the case where we change key after first operation*/ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } + + /* Enable SAES */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state & update error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* End of Key preparation for ECB/CBC */ + /* Return to decryption operating mode(Mode 3) */ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT); + + } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */ +#endif /* USE_HAL_SAES_ONLY */ + } + else /*Algorithm CTR */ + { +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED; + } + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } +#endif /* USE_HAL_SAES_ONLY */ + } + + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } +#endif /* IS_SAES_INSTANCE */ + } + } /* if (DoKeyIVConfig == 1U) */ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + if (hcryp->Size != 0U) + { + /* Start DMA process transfer for AES */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size, (uint32_t)(hcryp->pCrypOutBuffPtr)); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DMA CRYP input data process complete callback. + * @param hdma: DMA handle + * @retval None + */ +static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) +{ + CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit + in the DMACR register */ + ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Disable the DMA transfer for input FIFO request by resetting the DMAINEN bit + in the CR register */ + ((SAES_TypeDef *)(hcryp->Instance))->CR &= (uint32_t)(~SAES_CR_DMAINEN); + } +#endif /* USE_HAL_SAES_ONLY */ + + /* Call input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA CRYP output data process complete callback. + * @param hdma: DMA handle + * @retval None + */ +static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) +{ + uint32_t count; + uint32_t npblb; + uint32_t lastwordsize; + uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t mode; + + CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + + /* Disable the DMA transfer for output FIFO */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + ((SAES_TypeDef *)(hcryp->Instance))->CR &= (uint32_t)(~SAES_CR_DMAOUTEN); + + /* Disable the DMA transfer for output FIFO request by resetting + the DOEN bit in the DMACR register */ + CLEAR_BIT(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_DMAOUTEN); + } +#endif /* USE_HAL_SAES_ONLY */ + + /* Last block transfer in case of GCM or CCM with Size not %16 */ + /* Applicable to CRYP peripheral only */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + if (((hcryp->Size) % 16U) != 0U) + { + /* set CrypInCount and CrypOutCount to exact number of word already computed via DMA */ + hcryp->CrypInCount = (hcryp->Size / 16U) * 4U; + hcryp->CrypOutCount = hcryp->CrypInCount; + + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); + + /* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */ + mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE); + if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) || + ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Disable the CRYP */ + __HAL_CRYP_DISABLE(hcryp); + + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20); + + /* Enable CRYP to start the final phase */ + __HAL_CRYP_ENABLE(hcryp); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + /* Write the last input block in the IN FIFO */ + for (count = 0U; count < lastwordsize; count ++) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + /* Pad the data with zeros to have a complete block */ + while (count < 4U) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U; + count++; + } + /* Wait for OFNE flag to be raised */ + count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_OFNE)); + + /*Read the output block from the output FIFO */ + for (count = 0U; count < 4U; count++) + { + /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from + temporary buffer */ + temp = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT; + + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; + hcryp->CrypOutCount++; + } + } /*End of last block transfer in case of GCM or CCM */ + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + temp = 0; + /* Last block transfer in case of GCM or CCM with Size not %16*/ + if (((hcryp->Size) % 16U) != 0U) + { + /* set CrypInCount and CrypOutCount to exact number of words already computed via DMA */ + hcryp->CrypInCount = (hcryp->Size / 16U) * 4U; + hcryp->CrypOutCount = hcryp->CrypInCount; + + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size); + + mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE); + if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) || + ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Last block optionally pad the data with zeros*/ + for (count = 0U; count < lastwordsize; count++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (count < 4U) + { + /* Pad the data with zeros to have a complete block */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + count++; + } + + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /*Read the output block from the output FIFO */ + for (count = 0U; count < 4U; count++) + { + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ + temp = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR; + } + + count = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (count < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; + hcryp->CrypOutCount++; + count++; + } + } + } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */ +#endif /* USE_HAL_SAES_ONLY */ + + if (((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM) + && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM)) + { + /* Disable CRYP (not allowed in GCM) */ + __HAL_CRYP_DISABLE(hcryp); + } + + /* Change the CRYP state to ready */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + + /* Call output data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); +#else + /*Call legacy Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA CRYP communication error callback. + * @param hdma: DMA handle + * @retval None + */ +static void CRYP_DMAError(DMA_HandleTypeDef *hdma) +{ + CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* DMA error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; + + /* Call error callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +} + +/** + * @brief Set the DMA configuration and start the DMA transfer + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param inputaddr: address of the input buffer + * @param Size: size of the input buffer, must be a multiple of 16. + * @param outputaddr: address of the output buffer + * @retval None + */ +static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) +{ + HAL_StatusTypeDef status; + uint32_t peripheral_in_address = 0U; + uint32_t peripheral_out_address = 0U; + + /* Set the CRYP DMA transfer complete callback */ + hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt; + + /* Set the DMA input error callback */ + hcryp->hdmain->XferErrorCallback = CRYP_DMAError; + + /* Set the CRYP DMA transfer complete callback */ + hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt; + + /* Set the DMA output error callback */ + hcryp->hdmaout->XferErrorCallback = CRYP_DMAError; + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + peripheral_in_address = (uint32_t) &((CRYP_TypeDef *)(hcryp->Instance))->DIN; + peripheral_out_address = (uint32_t) &((CRYP_TypeDef *)(hcryp->Instance))->DOUT; + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + peripheral_in_address = (uint32_t) &((SAES_TypeDef *)(hcryp->Instance))->DINR; + peripheral_out_address = (uint32_t) &((SAES_TypeDef *)(hcryp->Instance))->DOUTR; + } +#endif /* USE_HAL_SAES_ONLY */ + + /* Enable the DMA input channel */ + if ((hcryp->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hcryp->hdmain->LinkedListQueue != NULL) && (hcryp->hdmain->LinkedListQueue->Head != NULL)) + { + /* Enable the DMA channel */ + hcryp->hdmain->LinkedListQueue->Head->\ + LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size; /* Set DMA data size */ + hcryp->hdmain->LinkedListQueue->Head->\ + LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = inputaddr; /* Set DMA source address */ + hcryp->hdmain->LinkedListQueue->Head->\ + LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = peripheral_in_address; /* Set DMA destination address */ + + status = HAL_DMAEx_List_Start_IT(hcryp->hdmain); + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, peripheral_in_address, Size); + } + + if (status != HAL_OK) + { + /* DMA error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; + + /* Call error callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + /* Enable the DMA output channel */ + if ((hcryp->hdmaout->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hcryp->hdmaout->LinkedListQueue != NULL) && (hcryp->hdmaout->LinkedListQueue->Head != NULL)) + { + /* Enable the DMA channel */ + hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = \ + Size; /* Set DMA data size */ + hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \ + peripheral_out_address; /* Set DMA source address */ + hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = \ + outputaddr; /* Set DMA destination address */ + + status = HAL_DMAEx_List_Start_IT(hcryp->hdmaout); + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hcryp->hdmaout, peripheral_out_address, outputaddr, Size); + } + + if (status != HAL_OK) + { + /* DMA error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; + + /* Call error callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + /* Enable In/Out DMA request */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DMACR = (CRYP_DMACR_DOEN | CRYP_DMACR_DIEN); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + ((SAES_TypeDef *)(hcryp->Instance))->CR |= (SAES_CR_DMAINEN | SAES_CR_DMAOUTEN); + } +#endif /* USE_HAL_SAES_ONLY */ +} + +/** + * @brief Process Data: Write Input data in polling mode and used in AES functions. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Timeout: Specify Timeout value + * @retval None + */ +static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + + uint32_t temp[4]; /* Temporary CrypOutBuff */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + uint16_t incount; /* Temporary CrypInCount Value */ + uint16_t outcount; /* Temporary CrypOutCount Value */ +#endif /* USE_HAL_CRYP_ONLY */ + uint32_t i; + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /*Temporary CrypOutCount Value */ + incount = hcryp->CrypInCount; + + if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < ((hcryp->Size) / 4U))) + { + /* Write the input block in the IN FIFO */ + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + + /* Wait for OFNE flag to be raised */ + if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state & update error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + /*Temporary CrypOutCount Value */ + outcount = hcryp->CrypOutCount; + + if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < ((hcryp->Size) / 4U))) + { + /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from + temporary buffer */ + for (i = 0U; i < 4U; i++) + { + temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT; + } + i = 0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Write the input block in the IN FIFO */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + /*Call registered error callback*/ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Read the output block from the output FIFO and put them in temporary buffer then + get CrypOutBuff from temporary buffer*/ + for (i = 0U; i < 4U; i++) + { + temp[i] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR; + } + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } + } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */ +#endif /* USE_HAL_SAES_ONLY */ +} + +/** + * @brief Handle CRYP block input/output data handling under interruption. + * @note The function is called under interruption only, once + * interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @retval HAL status + */ +static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t temp[4]; /* Temporary CrypOutBuff */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + uint16_t incount; /* Temporary CrypInCount Value */ + uint16_t outcount; /* Temporary CrypOutCount Value */ +#endif /* USE_HAL_CRYP_ONLY */ + uint32_t i; + + if (hcryp->State == HAL_CRYP_STATE_BUSY) + { +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + /* If suspension flag has been raised, suspend processing + only if not already at the end of the payload */ + if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) + { + /* Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the + CRYP_SR) and the BUSY bit is cleared */ + while (((((CRYP_TypeDef *)(hcryp->Instance))->SR) & (CRYP_SR_IFEM | CRYP_SR_OFNE | \ + CRYP_SR_BUSY)) != CRYP_SR_IFEM) + { + /* Nothing to do */ + } + + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); + + /* Disable CRYP */ + __HAL_CRYP_DISABLE(hcryp); + + /* reset SuspendRequest */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + } + else +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + { + /*Temporary CrypOutCount Value */ + incount = hcryp->CrypInCount; + + if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U))) + { + /* Write the input block in the IN FIFO */ + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + if (hcryp->CrypInCount == (hcryp->Size / 4U)) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); + + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + + /*Temporary CrypOutCount Value */ + outcount = hcryp->CrypOutCount; + + if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U))) + { + /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from + temporary buffer */ + for (i = 0U; i < 4U; i++) + { + temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT; + } + i = 0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } + if (hcryp->CrypOutCount == (hcryp->Size / 4U)) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Disable CRYP */ + __HAL_CRYP_DISABLE(hcryp); + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + + /* Call output transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); +#else + /*Call legacy Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + } /* if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) */ + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Read the output block from the output FIFO and put them in temporary buffer then + get CrypOutBuff from temporary buffer*/ + for (i = 0U; i < 4U; i++) + { + temp[i] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR; + } + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } + if (hcryp->CrypOutCount == (hcryp->Size / 4U)) + { + /* Disable Computation Complete flag and errors interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Disable CRYP */ + __HAL_CRYP_DISABLE(hcryp); + __HAL_UNLOCK(hcryp); + + /* Call Output transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); +#else + /*Call legacy Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + /* If suspension flag has been raised, suspend processing + only if not already at the end of the payload */ + if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) + { + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* reset SuspendRequest */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + + /* Mark that the payload phase is suspended */ + hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED; + + __HAL_UNLOCK(hcryp); + } + else +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + { + /* Write the input block in the IN FIFO */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + if (hcryp->CrypInCount == (hcryp->Size / 4U)) + { + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + } /* if (hcryp->CrypOutCount == (hcryp->Size / 4U)) */ + } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */ +#endif /* USE_HAL_SAES_ONLY */ + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Writes Key in Key registers. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param KeySize: Size of Key + * @retval None + */ +static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize) +{ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + switch (KeySize) + { + case CRYP_KEYSIZE_256B: + ((CRYP_TypeDef *)(hcryp->Instance))->K0LR = *(uint32_t *)(hcryp->Init.pKey); + ((CRYP_TypeDef *)(hcryp->Instance))->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1); + ((CRYP_TypeDef *)(hcryp->Instance))->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2); + ((CRYP_TypeDef *)(hcryp->Instance))->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3); + ((CRYP_TypeDef *)(hcryp->Instance))->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4); + ((CRYP_TypeDef *)(hcryp->Instance))->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5); + ((CRYP_TypeDef *)(hcryp->Instance))->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6); + ((CRYP_TypeDef *)(hcryp->Instance))->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7); + break; + + case CRYP_KEYSIZE_192B: + ((CRYP_TypeDef *)(hcryp->Instance))->K1LR = *(uint32_t *)(hcryp->Init.pKey); + ((CRYP_TypeDef *)(hcryp->Instance))->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); + ((CRYP_TypeDef *)(hcryp->Instance))->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); + ((CRYP_TypeDef *)(hcryp->Instance))->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); + ((CRYP_TypeDef *)(hcryp->Instance))->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); + ((CRYP_TypeDef *)(hcryp->Instance))->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); + break; + + case CRYP_KEYSIZE_128B: + ((CRYP_TypeDef *)(hcryp->Instance))->K2LR = *(uint32_t *)(hcryp->Init.pKey); + ((CRYP_TypeDef *)(hcryp->Instance))->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1); + ((CRYP_TypeDef *)(hcryp->Instance))->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2); + ((CRYP_TypeDef *)(hcryp->Instance))->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3); + break; + + default: + break; + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + if (hcryp->Init.pKey != NULL) + { + switch (KeySize) + { + case CRYP_KEYSIZE_256B: + ((SAES_TypeDef *)(hcryp->Instance))->KEYR7 = *(uint32_t *)(hcryp->Init.pKey); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U); + break; + case CRYP_KEYSIZE_128B: + ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = *(uint32_t *)(hcryp->Init.pKey); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U); + + break; + default: + break; + } + } /* if (hcryp->Init.pKey != NULL) */ + } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */ +#endif /* USE_HAL_SAES_ONLY */ +} + +/** + * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U; + uint32_t npblb ; + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t index ; + uint32_t lastwordsize ; + uint32_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t mode; + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; + + /****************************** Init phase **********************************/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED; + } + } + + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /*Wait for the CRYPEN bit to be cleared*/ + while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + SAES_SET_PHASE(hcryp, SAES_PHASE_INIT); + + /* We should re-write Key, in the case where we change key after first operation */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } +#endif /* USE_HAL_SAES_ONLY */ + + /************************ Header phase *************************************/ + + if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /*************************Payload phase ************************************/ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select payload phase once the header phase is performed */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); + + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Select payload phase once the header phase is performed */ + SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U); + } +#endif /* USE_HAL_SAES_ONLY */ + + } /* if (DoKeyIVConfig == 1U) */ + + if ((hcryp->Size % 16U) != 0U) + { + /* recalculate wordsize */ + wordsize = ((wordsize / 4U) * 4U) ; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /*Temporary CrypOutCount Value */ + outcount = hcryp->CrypOutCount; + /* Write input data and get output data */ + while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) + { + /* Write plain data and get cipher data */ + CRYP_AES_ProcessData(hcryp, Timeout); + + /*Temporary CrypOutCount Value */ + outcount = hcryp->CrypOutCount; + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + + if ((hcryp->Size % 16U) != 0U) + { + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); + + /* Set Npblb in case of AES GCM payload encryption to get right tag */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR; + if (mode == CRYP_OPERATINGMODE_ENCRYPT) + { + /* Disable the CRYP */ + __HAL_CRYP_DISABLE(hcryp); + + /* Specify the number of non-valid bytes using NPBLB register */ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20U); + + /* Enable CRYP to start the final phase */ + __HAL_CRYP_ENABLE(hcryp); + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE); + if (mode == CRYP_OPERATINGMODE_ENCRYPT) + { + /* Specify the number of non-valid bytes using NPBLB register */ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20U); + } + } +#endif /* USE_HAL_SAES_ONLY */ + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* Write the last input block in the IN FIFO */ + for (index = 0U; index < lastwordsize; index ++) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + + /* Pad the data with zeros to have a complete block */ + while (index < 4U) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U; + index++; + } + + /* Wait for OFNE flag to be raised */ + if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + /*Read the output block from the output FIFO */ + if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U) + { + for (index = 0U; index < 4U; index++) + { + /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from + temporary buffer */ + temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT; + } + } + else + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Write the last input block in the IN FIFO */ + for (index = 0U; index < lastwordsize; index ++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (index < 4U) + { + /* pad the data with zeros to have a complete block */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U; + index++; + } + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /*Read the output block from the output FIFO */ + for (index = 0U; index < 4U; index++) + { + /* Read the output block from the output FIFO and put them in temporary buffer then + get CrypOutBuff from temporary buffer */ + temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR; + } + } +#endif /* USE_HAL_SAES_ONLY */ + for (index = 0U; index < lastwordsize; index++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index]; + hcryp->CrypOutCount++; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + uint32_t Timeout = CRYP_GENERAL_TIMEOUT; + uint32_t tickstart; +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + uint32_t count; + uint32_t loopcounter; + uint32_t lastwordsize; + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t npblb; + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ +#endif /* USE_HAL_SAES_ONLY */ + +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) + { + CRYP_PhaseProcessingResume(hcryp); + return HAL_OK; + } +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + /* Manage header size given in bytes to handle cases where + header size is not a multiple of 4 bytes */ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } +#endif /* USE_HAL_SAES_ONLY */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + /* Configure Key, IV and process message (header and payload) */ + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; + + /******************************* Init phase *********************************/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED; + } + } + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* Get tick */ + tickstart = HAL_GetTick(); + /*Wait for the CRYPEN bit to be cleared */ + while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) + { + /* Check for the Timeout */ + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + SAES_SET_PHASE(hcryp, SAES_PHASE_INIT); + + /* We should re-write Key, in the case where we change key after first operation */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + ((SAES_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED; + } + + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for KEYVALID flag to be set */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count--; + if (count == 0U) + { + /* Disable the SAES peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_KEYVALID)); + + /* just wait for hash computation */ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count--; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF)); + + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } +#endif /* USE_HAL_SAES_ONLY */ + + /***************************** Header phase *********************************/ + + /* Select header phase */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER); + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + if (headersize_in_bytes == 0U) /*header phase is skipped*/ + { + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select payload phase once the header phase is performed */ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_GCMPH, SAES_PHASE_PAYLOAD); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U); + + /* Write the payload Input block in the IN FIFO */ + if (hcryp->Size == 0U) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + } + else if (hcryp->Size >= 16U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else /* Size < 16Bytes : first block is the last block*/ + { + /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption: + Workaround is implemented in polling mode, so if last block of + payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */ + + + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - ((uint32_t)hcryp->Size); + + if ((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) + { + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + /* Enter header data */ + /* Cher first whether header length is small enough to enter the full header in one shot */ + else if (headersize_in_bytes <= 16U) + { + /* Write header data, padded with zeros if need be */ + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp; + loopcounter++; + hcryp->CrypHeaderCount++ ; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + else + { + /* Write the first input header block in the Input FIFO, + the following header data will be fed after interrupt occurrence */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } + } +#endif /* USE_HAL_SAES_ONLY */ + } /* end of if (DoKeyIVConfig == 1U) */ + else /* Key and IV have already been configured, + header has already been processed; + only process here message payload */ + { +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U); + + /* Write the payload Input block in the IN FIFO */ + if (hcryp->Size == 0U) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + } + else if (hcryp->Size >= 16U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + if (hcryp->CrypInCount == (hcryp->Size / 4U)) + { + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else /* Size < 16Bytes : first block is the last block*/ + { + /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption: + Workaround is implemented in polling mode, so if last block of + payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */ + + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - ((uint32_t)hcryp->Size); + + if ((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) + { + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + } + } + } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */ +#endif /* USE_HAL_SAES_ONLY */ + } /* if (DoKeyIVConfig != 1U) */ + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + + /* Enable interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + } +#endif /* USE_HAL_CRYP_ONLY */ + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) +{ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + __IO uint32_t count = 0U; +#endif /* USE_HAL_CRYP_ONLY */ + uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ; + uint32_t index; + uint32_t npblb; + uint32_t lastwordsize = 0U; + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t mode; + uint32_t Timeout = CRYP_GENERAL_TIMEOUT; +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + uint32_t tickstart; +#endif /* USE_HAL_CRYP_ONLY */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; + + /*************************** Init phase ************************************/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED; + } + } + + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* Get tick */ + tickstart = HAL_GetTick(); + /*Wait for the CRYPEN bit to be cleared */ + while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) + { + /* Check for the Timeout */ + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + SAES_SET_PHASE(hcryp, SAES_PHASE_INIT); + + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } +#endif /* USE_HAL_SAES_ONLY */ + /************************ Header phase *************************************/ + + if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + /************************ Payload phase ************************************/ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select payload phase once the header phase is performed */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); + + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U); + } +#endif /* USE_HAL_SAES_ONLY */ + + } /* if (DoKeyIVConfig == 1U) */ + + if (hcryp->Size == 0U) + { + /* Process unLocked */ + __HAL_UNLOCK(hcryp); + + /* Change the CRYP state and phase */ + hcryp->State = HAL_CRYP_STATE_READY; + } + else if (hcryp->Size >= 16U) + { + /* DMA transfer must not include the last block in case of Size is not %16 */ + wordsize = wordsize - (wordsize % 4U); + + /* DMA transfer */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize * 4U, + (uint32_t)(hcryp->pCrypOutBuffPtr)); + } + else /* length of input data is < 16 */ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - (uint32_t)hcryp->Size; + + /* Set Npblb in case of AES GCM payload encryption to get right tag*/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR; + + if (mode == CRYP_OPERATINGMODE_ENCRYPT) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20); + } + + /* Enable CRYP to start the final phase */ + __HAL_CRYP_ENABLE(hcryp); + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Write the last input block in the IN FIFO */ + for (index = 0; index < lastwordsize; index ++) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + + /* Pad the data with zeros to have a complete block */ + while (index < 4U) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U; + index++; + } + + /* Wait for OFNE flag to be raised */ + count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_OFNE)); + + /*Read the output block from the output FIFO */ + for (index = 0U; index < 4U; index++) + { + /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from + temporary buffer */ + temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT; + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + + mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE); + if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) || + ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Write the last input block in the IN FIFO */ + for (index = 0; index < lastwordsize; index ++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + + /* Pad the data with zeros to have a complete block */ + while (index < 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U; + index++; + } + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + /*Call registered error callback*/ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + /* Clear the CCF flag by setting the CCF bit of the SAES_ICR register */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /*Read the output block from the output FIFO */ + for (index = 0U; index < 4U; index++) + { + /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from + temporary buffer */ + temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR; + } + } +#endif /* USE_HAL_SAES_ONLY */ + + for (index = 0; index < lastwordsize; index++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; + hcryp->CrypOutCount++; + } + + /* Change the CRYP state to ready */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + + /* Return function status */ + return HAL_OK; +} + + +/** + * @brief AES CCM encryption/decryption processing in polling mode + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U; + uint32_t npblb ; + uint32_t lastwordsize ; + uint32_t temp[4] ; /* Temporary CrypOutBuff */ + uint32_t index ; + uint32_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t mode; + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; + + /********************** Init phase ******************************************/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED; + } + } + /* Set the initialization vector (IV) with CTR1 information */ + ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; + ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = hcryp->Init.B0[1]; + ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = hcryp->Init.B0[2]; + ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* Set the initialization vector (IV) with B0 */ + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0); + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /*Wait for the CRYPEN bit to be cleared*/ + while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + SAES_SET_PHASE(hcryp, SAES_PHASE_INIT); + + /* We should re-write Key, in the case where we change key after first operation */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + + /* Set the initialization vector (IV) with B0 */ + ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.B0); + ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } +#endif /* USE_HAL_SAES_ONLY */ + + /************************* Header phase *************************************/ + /* Header block(B1) : associated data length expressed in bytes concatenated + with Associated Data (A)*/ + + if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /********************** Payload phase ***************************************/ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + /* Select payload phase once the header phase is performed */ + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U); + + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U); + + /* Select payload phase once the header phase is performed */ + SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD); + } +#endif /* USE_HAL_SAES_ONLY */ + + } /* if (DoKeyIVConfig == 1U) */ + + if ((hcryp->Size % 16U) != 0U) + { + /* recalculate wordsize */ + wordsize = ((wordsize / 4U) * 4U) ; + } + /* Get tick */ + tickstart = HAL_GetTick(); + + /*Temporary CrypOutCount Value */ + outcount = hcryp->CrypOutCount; + /* Write input data and get output data */ + while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) + { + /* Write plain data and get cipher data */ + CRYP_AES_ProcessData(hcryp, Timeout); + + /*Temporary CrypOutCount Value */ + outcount = hcryp->CrypOutCount; + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + if ((hcryp->Size % 16U) != 0U) + { + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); + + mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR; + if (mode == CRYP_OPERATINGMODE_DECRYPT) + { + /* Disable the CRYP */ + __HAL_CRYP_DISABLE(hcryp); + + /* Set Npblb in case of AES CCM payload decryption to get right tag */ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20); + + /* Enable CRYP to start the final phase */ + __HAL_CRYP_ENABLE(hcryp); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Write the last input block in the IN FIFO */ + for (index = 0U; index < lastwordsize; index ++) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + + /* Pad the data with zeros to have a complete block */ + while (index < 4U) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U; + index++; + } + + /* Wait for OFNE flag to be raised */ + if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + /*Read the output block from the output FIFO */ + if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U) + { + for (index = 0U; index < 4U; index++) + { + /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from + temporary buffer */ + temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT; + } + for (index = 0; index < lastwordsize; index++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; + hcryp->CrypOutCount++; + } + } + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + + if ((hcryp->Size % 16U) != 0U) + { + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size); + + mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE); + if (mode == CRYP_OPERATINGMODE_DECRYPT) + { + /* Set Npblb in case of AES CCM payload decryption to get right tag */ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20); + } + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Write the last input block in the IN FIFO */ + for (index = 0U; index < lastwordsize; index ++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + + /* Pad the data with zeros to have a complete block */ + while (index < 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U; + index++; + } + /* just wait for hash computation */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + for (index = 0U; index < 4U; index++) + { + /* Read the output block from the output FIFO and put them in temporary buffer then + get CrypOutBuff from temporary buffer */ + temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR; + } + for (index = 0U; index < lastwordsize; index++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; + hcryp->CrypOutCount++; + } + } + } +#endif /* USE_HAL_SAES_ONLY */ + /* Wait until the complete message has been processed */ + if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked & return error */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief AES CCM encryption/decryption process in interrupt mode + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t Timeout = CRYP_GENERAL_TIMEOUT; +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + uint32_t tickstart; +#endif /* USE_HAL_CRYP_ONLY */ + uint32_t loopcounter; + uint32_t lastwordsize; + uint32_t npblb; + uint32_t mode; +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + uint32_t headersize_in_bytes; + uint32_t tmp; + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ +#endif /* USE_HAL_SAES_ONLY */ + +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) + { + CRYP_PhaseProcessingResume(hcryp); + return HAL_OK; + } +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + /* Configure Key, IV and process message (header and payload) */ + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; + + /************ Init phase ************/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED; + } + } + + /* Set the initialization vector (IV) with CTR1 information */ + ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; + ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = hcryp->Init.B0[1]; + ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = hcryp->Init.B0[2]; + ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /*Write the B0 packet into CRYP_DR*/ + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0); + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /*Wait for the CRYPEN bit to be cleared */ + while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) + { + /* Check for the Timeout */ + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + SAES_SET_PHASE(hcryp, SAES_PHASE_INIT); + + /* We should re-write Key, in the case where we change key after first operation */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + + /* Set the initialization vector (IV) with B0 */ + ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.B0); + ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } +#endif /* USE_HAL_SAES_ONLY */ + + /***************************** Header phase *********************************/ + + /* Select header phase */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + + /* Enable interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Select header phase */ + SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER); + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + if (headersize_in_bytes == 0U) /* Header phase is skipped */ + { + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select payload phase once the header phase is performed */ + SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U); + + if (hcryp->Init.Algorithm == CRYP_AES_CCM) + { + /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */ + hcryp->CrypHeaderCount++; + } + /* Write the payload Input block in the IN FIFO */ + if (hcryp->Size == 0U) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + } + else if (hcryp->Size >= 16U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else /* Size < 4 words : first block is the last block*/ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - (uint32_t)hcryp->Size; + + mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE); + if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) || + ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* Pad the data with zeros to have a complete block */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + /* Enter header data */ + /* Check first whether header length is small enough to enter the full header in one shot */ + else if (headersize_in_bytes <= 16U) + { + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp; + hcryp->CrypHeaderCount++; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + } + } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + else + { + /* Write the first input header block in the Input FIFO, + the following header data will be fed after interrupt occurrence */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } /* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/ + } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */ +#endif /* USE_HAL_SAES_ONLY */ + } /* end of if (dokeyivconfig == 1U) */ + else /* Key and IV have already been configured, + header has already been processed; + only process here message payload */ + { + /* Write the payload Input block in the IN FIFO */ + if (hcryp->Size == 0U) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + } + else if (hcryp->Size >= 16U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else /* Size < 4 words : first block is the last block*/ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - (uint32_t)hcryp->Size; + + mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE); + if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) || + ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* Pad the data with zeros to have a complete block */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } /* end of if (DoKeyIVConfig == 1U) */ + + /* Return function status */ + return HAL_OK; +} + + +/** + * @brief AES CCM encryption/decryption process in DMA mode + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) +{ + uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ; + uint32_t index; + uint32_t npblb; + uint32_t lastwordsize = 0U; + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t mode; +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + uint32_t tickstart; +#endif /* USE_HAL_CRYP_ONLY */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; + + /************************** Init phase **************************************/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED; + } + } + /* Set the initialization vector (IV) with CTR1 information */ + ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; + ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = hcryp->Init.B0[1]; + ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = hcryp->Init.B0[2]; + ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /*Write the B0 packet into CRYP_DR*/ + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0); + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /*Wait for the CRYPEN bit to be cleared*/ + while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CRYP_TIMEOUT_GCMCCMINITPHASE) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + SAES_SET_PHASE(hcryp, SAES_PHASE_INIT); + + /* We should re-write Key, in the case where we change key after first operation */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + }; + + /* Set the initialization vector (IV) with B0 */ + ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.B0); + ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMINITPHASE) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } +#endif /* USE_HAL_SAES_ONLY */ + + /********************* Header phase *****************************************/ + + if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + /******************** Payload phase *****************************************/ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select payload phase once the header phase is performed */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); + + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U); + } +#endif /* USE_CRYP_INSTANCE */ + } /* if (DoKeyIVConfig == 1U) */ + + if (hcryp->Size == 0U) + { + /* Process unLocked */ + __HAL_UNLOCK(hcryp); + + /* Change the CRYP state and phase */ + hcryp->State = HAL_CRYP_STATE_READY; + } + else if (hcryp->Size >= 16U) + { + wordsize = wordsize - (wordsize % 4U); + /* DMA transfer */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t) wordsize * 4U, + (uint32_t)(hcryp->pCrypOutBuffPtr)); + } + else /* length of input data is < 16U */ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - (uint32_t)(hcryp->Size); + + /* Set Npblb in case of AES CCM payload decryption to get right tag*/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR; + + if (mode == CRYP_OPERATINGMODE_DECRYPT) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20); + } + + /* Enable CRYP to start the final phase */ + __HAL_CRYP_ENABLE(hcryp); + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Write the last input block in the IN FIFO */ + for (index = 0U; index < lastwordsize; index ++) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + + /* Pad the data with zeros to have a complete block */ + while (index < 4U) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U; + index++; + } + + /* Wait for OFNE flag to be raised */ + if (CRYP_WaitOnOFNEFlag(hcryp, CRYP_TIMEOUT_GCMCCMINITPHASE) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state & update error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + /*Read the output block from the output FIFO */ + for (index = 0U; index < 4U; index++) + { + /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from + temporary buffer */ + temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT; + } + } /* SAES peripheral */ +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE); + + if (mode == CRYP_OPERATINGMODE_DECRYPT) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Write the last input block in the IN FIFO */ + for (index = 0U; index < lastwordsize; index ++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + + /* Pad the data with zeros to have a complete block */ + while (index < 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U; + index++; + } + /* just wait for hash computation */ + if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMINITPHASE) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state & update error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /*Read the output block from the output FIFO */ + for (index = 0U; index < 4U; index++) + { + /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from + temporary buffer */ + temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR; + } + } +#endif /* USE_HAL_SAES_ONLY */ + + for (index = 0; index < lastwordsize; index++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; + hcryp->CrypOutCount++; + } + + /* Change the CRYP state to ready */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Sets the payload phase in interrupt mode + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval state + */ +static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t loopcounter; + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t lastwordsize; + uint32_t npblb; + uint32_t mode; +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + uint8_t negative = 0U; +#endif /* USE_HAL_CRYP_ONLY */ + uint32_t i; + + /***************************** Payload phase *******************************/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + if ((hcryp->Size / 4U) < hcryp->CrypInCount) + { + negative = 1U; + } + + if (hcryp->Size == 0U) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + } + + else if ((((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) && + (negative == 0U)) + { + if ((((CRYP_TypeDef *)(hcryp->Instance))->IMSCR & CRYP_IMSCR_INIM) != 0x0U) + { + +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + /* If suspension flag has been raised, suspend processing + only if not already at the end of the payload */ + if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) + { + /* Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the + CRYP_SR) and the BUSY bit is cleared */ + while (((((CRYP_TypeDef *)(hcryp->Instance))->SR) & (CRYP_SR_IFEM | CRYP_SR_OFNE | \ + CRYP_SR_BUSY)) != CRYP_SR_IFEM) + { + /* Nothing to do */ + } + + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); + + /* Disable CRYP */ + __HAL_CRYP_DISABLE(hcryp); + + /* reset SuspendRequest */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + + /* Mark that the payload phase is suspended */ + hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + } + else +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + { + /* Write the input block in the IN FIFO */ + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U)) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + if (hcryp->CrypOutCount < (hcryp->Size / 4U)) + { + if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U) + { + /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from + temporary buffer */ + for (i = 0U; i < 4U; i++) + { + temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT; + } + i = 0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } + if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U)) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Disable CRYP */ + __HAL_CRYP_DISABLE(hcryp); + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + + /* Call output transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); +#else + /*Call legacy Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + } + } /* if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) */ + } + } + else if ((hcryp->Size % 16U) != 0U) + { + /* Set padding only in case of input fifo interrupt */ + if ((((CRYP_TypeDef *)(hcryp->Instance))->IMSCR & CRYP_IMSCR_INIM) != 0x0U) + { + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); + + mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR; + if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) || + ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Disable the CRYP */ + __HAL_CRYP_DISABLE(hcryp); + + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20); + + /* Enable CRYP to start the final phase */ + __HAL_CRYP_ENABLE(hcryp); + } + + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Write the last input block in the IN FIFO */ + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U; + loopcounter++; + } + + /* Disable the input FIFO Interrupt */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); + } + + /*Read the output block from the output FIFO */ + if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U) + { + for (i = 0U; i < 4U; i++) + { + temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT; + } + if (((hcryp->Size) / 4U) == 0U) + { + for (i = 0U; (uint16_t)i < ((hcryp->Size) % 4U); i++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + } + } + i = 0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } + } + + /* Disable the output FIFO Interrupt */ + if (hcryp->CrypOutCount >= ((hcryp->Size) / 4U)) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI); + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + + /* Call output transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); +#else + /*Call legacy Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + uint32_t incount; + uint32_t outcount; + + /* Read the output block from the output FIFO and put them in temporary buffer then + get CrypOutBuff from temporary buffer*/ + for (i = 0U; i < 4U; i++) + { + temp[i] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR; + } + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } + incount = hcryp->CrypInCount; + outcount = hcryp->CrypOutCount; + if ((outcount >= ((uint32_t)(hcryp->Size) / 4U)) && ((incount * 4U) >= (uint32_t)(hcryp->Size))) + { + + /* When in CCM with Key and IV configuration skipped, don't disable interruptions */ + if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U))) + { + /* Disable computation complete flag and errors interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + } + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + + /* Call output transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); +#else + /*Call legacy Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) + { + +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + /* If suspension flag has been raised, suspend processing + only if not already at the end of the payload */ + if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) + { + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* reset SuspendRequest */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + /* Mark that the payload phase is suspended */ + hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED; + __HAL_UNLOCK(hcryp); + } + else +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + { + /* Write the input block in the IN FIFO */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) + { + /* Call output transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + } + else /* Last block of payload < 128bit*/ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size); + + mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE); + if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) || + ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + } + } + } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */ +#endif /* USE_HAL_SAES_ONLY */ +} + + +/** + * @brief Sets the header phase in polling mode + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module(Header & HeaderSize) + * @param Timeout: Timeout value + * @retval state + */ +static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t loopcounter; +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + uint32_t headersize_in_bytes; + uint32_t tmp; + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ +#endif /* USE_HAL_SAES_ONLY */ + + /***************************** Header phase for GCM/GMAC or CCM *********************************/ + + /* Select header phase */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + if ((hcryp->Init.HeaderSize % 4U) == 0U) + { + /* HeaderSize %4, no padding */ + for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + /* Wait for IFEM to be raised */ + if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + else + { + /*Write header block in the IN FIFO without last block */ + for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); + loopcounter += 4U) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + /* Wait for IFEM to be raised */ + if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0x0U; + loopcounter++; + } + /* Wait for IFEM to be raised */ + if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + + /* Set Header phase */ + SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + if ((headersize_in_bytes % 16U) == 0U) + { + /* HeaderSize %4, no padding */ + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + /* Wait for CCF to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } + } + else + { + /*Write header block in the IN FIFO without last block */ + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + /* Wait for CCF to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } + /* Write last complete words */ + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(SAES_CONV_DATATYPE(hcryp->Init.DataType) * 2U) + (headersize_in_bytes % 4U)]; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + } + } + + /* Wait for CCF to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } + } +#endif /* USE_HAL_SAES_ONLY */ + /* Wait until the complete message has been processed */ + if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked & return error */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Return function status */ + return HAL_OK; +} + + +/** + * @brief Sets the header phase when using DMA in process + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module(Header & HeaderSize) + * @retval None + */ +static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp) +{ + uint32_t loopcounter; + uint32_t Timeout = CRYP_TIMEOUT_GCMCCMHEADERPHASE; +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + uint32_t headersize_in_bytes; + uint32_t tmp; + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ +#endif /* USE_HAL_SAES_ONLY */ + + /***************************** Header phase for GCM/GMAC or CCM *********************************/ + if ((hcryp->Init.HeaderSize != 0U)) + { + /* Select header phase */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + if ((hcryp->Init.HeaderSize % 4U) == 0U) + { + /* HeaderSize %4, no padding */ + for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + /* Wait for IFEM to be raised */ + if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + else + { + /*Write header block in the IN FIFO without last block */ + for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); + loopcounter += 4U) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + /* Wait for IFEM to be raised */ + if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + while (loopcounter < 4U) + { + /* Pad the data with zeros to have a complete block */ + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0x0U; + loopcounter++; + } + + /* Wait for IFEM to be raised */ + if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + /* Set header phase*/ + SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + if ((headersize_in_bytes % 16U) == 0U) + { + /* HeaderSize %4, no padding */ + for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + /* Wait for CCF to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + else + { + /*Write header block in the IN FIFO without last block */ + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + /* Wait for CCF to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + /* Write last complete words */ + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(SAES_CONV_DATATYPE(hcryp->Init.DataType) * 2U) + (headersize_in_bytes % 4U)]; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + } + } + + /* Wait for CCF to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } +#endif /* USE_HAL_SAES_ONLY */ + /* Wait until the complete message has been processed */ + Timeout = CRYP_GENERAL_TIMEOUT; + if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Sets the header phase in interrupt mode + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module(Header & HeaderSize) + * @retval None + */ +static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t loopcounter; +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + uint32_t lastwordsize; + uint32_t npblb; + uint32_t mode; + uint32_t headersize_in_bytes; + uint32_t tmp; + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ +#endif /* USE_HAL_SAES_ONLY */ + + /***************************** Header phase *********************************/ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); + + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U); + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + + /* Enable Interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + } + else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U) + + { + /* HeaderSize %4, no padding */ + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + else + { + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + while (loopcounter < 4U) + { + /* Pad the data with zeros to have a complete block */ + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0x0U; + loopcounter++ ; + } + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + /***************************** Header phase *********************************/ + /* Test whether or not the header phase is over. + If the test below is true, move to payload phase */ + if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U)) + { + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + /* Select payload phase */ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_GCMPH, SAES_PHASE_PAYLOAD); + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U); + + if (hcryp->Init.Algorithm == CRYP_AES_CCM) + { + /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */ + hcryp->CrypHeaderCount++; + } + /* Write the payload Input block in the IN FIFO */ + if (hcryp->Size == 0U) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + } + else if (hcryp->Size >= 16U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else /* Size < 4 words : first block is the last block*/ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - ((uint32_t)hcryp->Size); + mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE); + if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) || + ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* Pad the data with zeros to have a complete block */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + } + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)) + { + /* Can enter full 4 header words */ +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + /* If suspension flag has been raised, suspend processing + only if not already at the end of the header */ + if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) + { + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* reset SuspendRequest */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + /* Mark that the payload phase is suspended */ + hcryp->Phase = CRYP_PHASE_HEADER_SUSPENDED; + __HAL_UNLOCK(hcryp); + } + else +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + { + /* Write the input block in the IN FIFO */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } + } + else /* Write last header block (4 words), padded with zeros if needed */ + { + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(SAES_CONV_DATATYPE(hcryp->Init.DataType) * 2U) + (headersize_in_bytes % 4U)]; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp; + loopcounter++; + hcryp->CrypHeaderCount++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + } + } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */ +#endif /* USE_HAL_SAES_ONLY */ +} + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) +/** + * @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_IFEM)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_ERROR; + } + } + } + return HAL_OK; +} +#endif /* USE_HAL_CRYP_ONLY */ + +/** + * @brief Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t flag_busy = 0U; + + /* Get timeout */ + tickstart = HAL_GetTick(); + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + flag_busy = CRYP_FLAG_BUSY; + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + flag_busy = SAES_FLAG_BUSY; + } +#endif /* USE_HAL_SAES_ONLY */ + while (HAL_IS_BIT_SET(((CRYP_TypeDef *)(hcryp->Instance))->SR, flag_busy)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) +/** + * @brief Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_OFNE)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_ERROR; + } + } + } + return HAL_OK; +} +#endif /* USE_HAL_CRYP_ONLY */ + +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +/** + * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Timeout Timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_WaitOnCCFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_ERROR; + } + } + } + return HAL_OK; +} +#endif /* USE_HAL_SAES_ONLY */ + +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) +/** + * @brief In case of message processing suspension, read the Initialization Vector. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Output Pointer to the buffer containing the saved Initialization Vector. + * @note This value has to be stored for reuse by writing the AES_IVRx registers + * as soon as the suspended processing has to be resumed. + * @retval None + */ +static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output) +{ + uint32_t outputaddr = (uint32_t)Output; + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR; + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR3; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR2; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR1; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR0; + } +#endif /* USE_HAL_SAES_ONLY */ +} + +/** + * @brief In case of GCM/GMAC/CCM processing resumption, rewrite the Initialization + * Vector in the SAES_IVx registers. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Input Pointer to the buffer containing the saved Initialization Vector to + * write back in the CRYP hardware block. + * @note Applicable only to CRYP peripheral + * @note CRYP must be disabled when reconfiguring the IV values. + * @retval None + */ +static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input) +{ + uint32_t ivaddr = (uint32_t)Input; +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(ivaddr); + ivaddr += 4U; + ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(ivaddr); + ivaddr += 4U; + ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(ivaddr); + ivaddr += 4U; + ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(ivaddr); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(ivaddr); + ivaddr += 4U; + ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(ivaddr); + ivaddr += 4U; + ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(ivaddr); + ivaddr += 4U; + ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(ivaddr); + } +#endif /* USE_HAL_SAES_ONLY */ +} + +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) +/** + * @brief In case of message GCM/GMAC/CCM processing suspension, + * read the context swap Registers. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Output Pointer to the buffer containing the saved Suspend Registers. + * @param Algorithm specifies whether CCM or GCM/GMAC is suspended. + * @note These values have to be stored for reuse by writing back the CRYP_CSGCMCCMxR CRYP_CSGCMxR registers + * as soon as the suspended processing has to be resumed. + * @retval None + */ +static void CRYP_Read_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t Algorithm) +{ + uint32_t outputaddr = (uint32_t)Output; + uint32_t inputaddr = (uint32_t)(&((CRYP_TypeDef *)(hcryp->Instance))->CSGCMCCM0R); + uint32_t i; + + for (i = 0; i < 8U; i++) + { + *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr); + outputaddr += 4U; + inputaddr += 4U; + } + if (Algorithm == CRYP_AES_GCM) + { + for (i = 0; i < 8U; i++) + { + *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr); + outputaddr += 4U; + inputaddr += 4U; + } + } +} +#endif /* USE_HAL_CRYP_ONLY */ + +/** + * @brief In case of message GCM/GMAC/CCM processing resumption, rewrite the context swap registers. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Input Pointer to the buffer containing the saved suspend registers to + * write back in the CRYP hardware block. + * @param Algorithm specifies whether CCM or GCM/GMAC is suspended. + * @note AES must be disabled when reconfiguring the suspend registers. + * @retval None + */ +static void CRYP_Write_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t Algorithm) +{ + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)(&((CRYP_TypeDef *)(hcryp->Instance))->CSGCMCCM0R); + uint32_t i; + + for (i = 0; i < 8U; i++) + { + *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr); + outputaddr += 4U; + inputaddr += 4U; + } + if (Algorithm == CRYP_AES_GCM) + { + for (i = 0; i < 8U; i++) + { + *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr); + outputaddr += 4U; + inputaddr += 4U; + } + } +} + +/** + * @brief Authentication phase resumption in case of GCM/GMAC/CCM process in interrupt mode + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module(Header & HeaderSize) + * @retval None + */ +static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) +{ + /* Case of header phase resumption =================================================*/ + if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) + { + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select header phase */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER); + } +#endif /* USE_HAL_SAES_ONLY */ + + /* Enable interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + } + /* Case of payload phase resumption =================================================*/ + else + { + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select payload phase once the header phase is performed */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD); + } +#endif /* USE_HAL_SAES_ONLY */ + + /* Enable Interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + } +} + +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +/* + * @brief Adaptation needed do differentiate between CRYP and SAES CR_CHMOD fields + * @param algo: corresponds to the algorithm to set + * order: determines if conversion is done from CRYP to SAES and vice versa + order = ALGOMODE_CRYP_TO_CHMOD_SAES means from algomode CRYP to chmod SAES + order = ALGOMODE_SAES_TO_CHMOD_CRYP means from algomode SAES to chmod CRYP + * @retval new_algo: correspond to the CR_CHMOD setting applied + */ +static uint32_t CRYP_SAES_AlgoConversion(uint32_t algo, uint32_t order) +{ + uint32_t new_algo = 0x0; + + if (order == 0U) /* from algomode CRYP to chmod SAES */ + { + switch (algo) + { + case CRYP_AES_ECB : + new_algo = SAES_CR_CHMOD_AES_ECB; + break; + case CRYP_AES_CBC : + new_algo = SAES_CR_CHMOD_AES_CBC; + break; + case CRYP_AES_CTR : + new_algo = SAES_CR_CHMOD_AES_CTR; + break; + case CRYP_AES_GCM : + new_algo = SAES_CR_CHMOD_AES_GCM; + break; + case CRYP_AES_CCM : + new_algo = SAES_CR_CHMOD_AES_CCM; + break; + default : + break; + } + + } + else /* order == 1 , from chmod SAES to algomode CRYP */ + { + switch (algo) + { + case SAES_CR_CHMOD_AES_ECB : + new_algo = CRYP_AES_ECB; + break; + case SAES_CR_CHMOD_AES_CBC : + new_algo = CRYP_AES_CBC; + break; + case SAES_CR_CHMOD_AES_CTR : + new_algo = CRYP_AES_CTR; + break; + case SAES_CR_CHMOD_AES_GCM : + new_algo = CRYP_AES_GCM; + break; + case SAES_CR_CHMOD_AES_CCM : + new_algo = CRYP_AES_CCM; + break; + default : + break; + } + } + + return new_algo; +} +#endif /* USE_HAL_SAES_ONLY */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CRYP_MODULE_ENABLED */ + + +/** + * @} + */ +#endif /* CRYP */ +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cryp_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cryp_ex.c new file mode 100644 index 00000000000..9a580a27225 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cryp_ex.c @@ -0,0 +1,1016 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_cryp_ex.c + * @author MCD Application Team + * @brief Extended CRYP HAL module driver + * This file provides firmware functions to manage the following + * functionalities of CRYP extension peripheral: + * + Extended AES processing functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The CRYP extension HAL driver can be used after AES-GCM or AES-CCM + Encryption/Decryption to get the authentication messages. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#if defined (CRYP) +/** @defgroup CRYPEx CRYPEx + * @brief CRYP Extension HAL module driver. + * @{ + */ + +#ifdef HAL_CRYP_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup CRYPEx_Private_Defines + * @{ + */ + +#define CRYP_PHASE_INIT 0x00000000U +#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 +#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 +#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH + +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +#define SAES_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ +#define SAES_PHASE_HEADER SAES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */ +#define SAES_PHASE_PAYLOAD SAES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */ +#define SAES_PHASE_FINAL SAES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */ +#endif /* USE_HAL_SAES_ONLY */ + +#define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */ +#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant + only with CCM and GCM modes */ + +/* CTR0 information to use in CCM algorithm */ +#define CRYP_CCM_CTR0_0 0x07FFFFFFU +#define CRYP_CCM_CTR0_3 0xFFFFFF00U + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static void CRYPEx_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize); +#endif /* USE_HAL_SAES_ONLY */ +/* Exported functions---------------------------------------------------------*/ +/** @addtogroup CRYPEx_Exported_Functions + * @{ + */ + +/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions + * @brief CRYPEx Extended processing functions. + * +@verbatim + ============================================================================== + ##### Extended AES processing functions ##### + ============================================================================== + [..] This section provides functions allowing to generate the authentication + TAG in Polling mode + (+)HAL_CRYPEx_AESGCM_GenerateAuthTAG + (+)HAL_CRYPEx_AESCCM_GenerateAuthTAG + they should be used after Encrypt/Decrypt operation. + +@endverbatim + * @{ + */ + + +/** + * @brief generate the GCM authentication TAG. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pAuthTag: Pointer to the authentication buffer + * the AuthTag generated here is 128bits length, if the TAG length is + * less than 128bits, user should consider only the valid part of AuthTag + * buffer which correspond exactly to TAG length. + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag, + uint32_t Timeout) +{ + uint32_t tickstart; + uint64_t headerlength; + uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */ + uint32_t tagaddr = (uint32_t)pAuthTag; + uint8_t i; + + + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */ + } + else + { + headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 8U; /* Header length in bits */ + } + + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Process locked */ + __HAL_LOCK(hcryp); + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if (hcryp->Phase == CRYPEx_PHASE_PROCESS) + { + /* Change the CRYP phase */ + hcryp->Phase = CRYPEx_PHASE_FINAL; + } + else /* Initialization phase has not been performed*/ + { + /* Disable the Peripheral */ + __HAL_CRYP_DISABLE(hcryp); + + /* Sequence error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE; + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + + /* Select final phase */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* Disable CRYP to start the final phase */ + __HAL_CRYP_DISABLE(hcryp); + + /* ALGODIR bit must be set to '0'. */ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL); + ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_CR_ALGODIR; + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* Write the number of bits in header (64 bits) followed by the number of bits + in the payload */ + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = (uint32_t)(headerlength); + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U; + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = (uint32_t)(inputlength); + + /* Wait for OFNE flag to be raised */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_OFNE)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP Peripheral Clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + /* Read the authentication TAG in the output FIFO */ + for (i = 0U; i < 4U; i++) + { + *(uint32_t *)(tagaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT; + tagaddr += 4U; + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Select final phase */ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_GCMPH, SAES_PHASE_FINAL); + + /* Write the number of bits in header (64 bits) followed by the number of bits + in the payload */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = (uint32_t)(headerlength); + ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = (uint32_t)(inputlength); + + /* Wait for CCF flag to be raised */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral Clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + + /* Read the authentication TAG in the output FIFO */ + for (i = 0U; i < 4U; i++) + { + *(uint32_t *)(tagaddr) = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR; + tagaddr += 4U; + } + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } +#endif /* USE_HAL_SAES_ONLY */ + + /* Disable the peripheral */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief AES CCM Authentication TAG generation. + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pAuthTag: Pointer to the authentication buffer + * the AuthTag generated here is 128bits length, if the TAG length is + * less than 128bits, user should consider only the valid part of AuthTag + * buffer which correspond exactly to TAG length. + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag, + uint32_t Timeout) +{ + uint32_t tagaddr = (uint32_t)pAuthTag; + uint32_t ctr0 [4] = {0}; + uint32_t ctr0addr = (uint32_t)ctr0; + uint32_t tickstart; + uint8_t i; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Process locked */ + __HAL_LOCK(hcryp); +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Disable interrupts, we are now in polling mode to TAG generation */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + } +#endif /* USE_HAL_SAES_ONLY */ + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if (hcryp->Phase == CRYPEx_PHASE_PROCESS) + { + /* Change the CRYP phase */ + hcryp->Phase = CRYPEx_PHASE_FINAL; + } + else /* Initialization phase has not been performed*/ + { + /* Disable the peripheral */ + __HAL_CRYP_DISABLE(hcryp); + + /* Sequence error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE; + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + + /* Select final phase */ +#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) + if (IS_CRYP_INSTANCE(hcryp->Instance)) + { + /* Disable CRYP to start the final phase */ + __HAL_CRYP_DISABLE(hcryp); + + /* ALGODIR bit must be set to '0' */ + MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL); + ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_CR_ALGODIR; + + /* Write the counter block in the IN FIFO, CTR0 information from B0 + data has to be swapped according to the DATATYPE*/ + ctr0[0] = hcryp->Init.B0[0] & CRYP_CCM_CTR0_0; + ctr0[1] = hcryp->Init.B0[1]; + ctr0[2] = hcryp->Init.B0[2]; + ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3; + + for (i = 0U; i < 4U; i++) + { + ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(ctr0addr); + ctr0addr += 4U; + } + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for OFNE flag to be raised */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)((hcryp->Instance)))->SR, CRYP_FLAG_OFNE)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral Clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + /* Read the authentication TAG in the output FIFO */ + for (i = 0U; i < 4U; i++) + { + *(uint32_t *)(tagaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT; + tagaddr += 4U; + } + } +#endif /* USE_HAL_CRYP_ONLY */ +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) + if (IS_SAES_INSTANCE(hcryp->Instance)) + { + /* Change SAES final phase */ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_GCMPH, SAES_PHASE_FINAL); + + for (i = 0U; i < 4U; i++) + { + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(ctr0addr); + ctr0addr += 4U; + } + + /* Wait for CCF flag to be raised */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_CCF)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral Clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + /* Read the authentication TAG in the output FIFO */ + for (i = 0U; i < 4U; i++) + { + *(uint32_t *)(tagaddr) = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR; + tagaddr += 4U; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } +#endif /* USE_HAL_SAES_ONLY */ + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + + /* Disable CRYP */ + __HAL_CRYP_DISABLE(hcryp); + } + else + { + /* Busy error code field */ + hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } + /* Return function status */ + return HAL_OK; +} + + +/** @defgroup CRYPEx_Exported_Functions_Group2 Wrap and Unwrap key functions + * @brief Wrap and Unwrap key functions. + * +@verbatim + ============================================================================== + ##### Wrap and Unwrap key ##### + ============================================================================== + [..] This section provides API allowing to wrap (encrypt) and unwrap (decrypt) + key using one of the following keys, and AES Algorithm. + Key selection : + - Derived hardware unique key (DHUK) + - XOR of DHUK and BHK + - Boot hardware key (BHK) + - Key registers AES_KEYx + +@endverbatim + * @{ + */ + +#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1) +/** + * @brief Wrap (encrypt) application keys . + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Input Pointer to the Key buffer to encrypt + * @param Output Pointer to the Key buffer encrypted + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t *Output, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Process locked */ + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = Input; + hcryp->pCrypOutBuffPtr = Output; + + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Set the operating mode*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_WRAPPED); + + status = CRYPEx_KeyEncrypt(hcryp, Timeout); + + if (status == HAL_OK) + { + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @brief Unwrap (Decrypt) application keys . + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Input Pointer to the Key buffer to decrypt + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Process locked */ + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = Input; + + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Set the operating mode*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_WRAPPED); + + status = CRYPEx_KeyDecrypt(hcryp, Timeout); + + if (status == HAL_OK) + { + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup CRYPEx_Exported_Functions_Group3 Encrypt/Decrypt Shared key functions + * @brief Encrypt/Decrypt Shared key functions. + * +@verbatim + ============================================================================== + ##### Encrypt/Decrypt Shared key functions ##### + ============================================================================== + [..] This section provides API allowing to Encrypt/Decrypt Shared key + +@endverbatim + * @{ + */ + +/** + * @brief Encrypt Shared key. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Key Pointer to the Key buffer to share + * @param Output buffer pointer + * @param ID Key share identification + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t *Output, uint32_t ID, + uint32_t Timeout) +{ + HAL_StatusTypeDef status; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Process locked */ + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = Key; + hcryp->pCrypOutBuffPtr = Output; + + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Set the operating mode*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD | SAES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); + + status = CRYPEx_KeyEncrypt(hcryp, Timeout); + + if (status == HAL_OK) + { + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @brief Decrypt Shared key. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Key Pointer to the Key buffer to share + * @param ID Key share identification + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t ID, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Process locked */ + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = Key; + + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Set the operating mode*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD | SAES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); + + status = CRYPEx_KeyDecrypt(hcryp, Timeout); + + if (status == HAL_OK) + { + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @brief Key Decryption + * @param hcryp pointer to a CRYP_HandleTypeDef structure + * @param Timeout specify Timeout value + * @note It is strongly recommended to select hardware secret keys + * @retval HAL status + */ +static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t incount; /* Temporary CrypInCount Value */ + uint32_t tickstart; + + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_KEY_DERIVATION); + + /*It is strongly recommended to select hardware secret keys*/ + if (hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) + { + /* Set the Key*/ + CRYPEx_SetKey(hcryp, hcryp->Init.KeySize); + } + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* End of Key preparation for ECB/CBC */ + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT); + + + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Set the phase */ + hcryp->Phase = CRYPEx_PHASE_PROCESS; + + if (hcryp->Init.KeySize == CRYP_KEYSIZE_128B) + { + incount = 4; + } + else + { + incount = 8; + } + while (hcryp->CrypInCount < incount) + { + /* Write four times to input the key to encrypt */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + /* Wait for CCF flag to be raised */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } + + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + return HAL_OK; +} + +/** + * @brief Key Encryption + * @param hcryp pointer to a CRYP_HandleTypeDef structure + * @param Timeout specify Timeout value + * @retval HAL status + */ +static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t incount; /* Temporary CrypInCount Value */ + uint32_t tickstart; + uint32_t temp; /* Temporary CrypOutBuff */ + + MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } + /*It is strongly recommended to select hardware secret keys*/ + if (hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) + { + /* Set the Key*/ + CRYPEx_SetKey(hcryp, hcryp->Init.KeySize); + } + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for Valid KEY flag to set */ + while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_KEYVALID)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + return HAL_ERROR; + } + } + } + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Set the phase */ + hcryp->Phase = CRYPEx_PHASE_PROCESS; + + if (hcryp->Init.KeySize == CRYP_KEYSIZE_128B) + { + incount = 4; + } + else + { + incount = 8; + } + while (hcryp->CrypInCount < incount) + { + /* Write four times to input the key to encrypt */ + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + /* Wait for CCF flag to be raised */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Read the output block from the output FIFO and put them in temporary buffer then + get CrypOutBuff from temporary buffer*/ + temp = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR; + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; + hcryp->CrypOutCount++; + temp = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR; + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; + hcryp->CrypOutCount++; + temp = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR; + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; + hcryp->CrypOutCount++; + temp = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR; + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; + hcryp->CrypOutCount++; + } + + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + return HAL_OK; +} + +/** + * @brief Write Key in Key registers. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param KeySize Size of Key + * @note If pKey is NULL, the Key registers are not written. + * @retval None + */ +static void CRYPEx_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize) +{ + if (hcryp->Init.pKey != NULL) + { + switch (KeySize) + { + case CRYP_KEYSIZE_256B: + ((SAES_TypeDef *)(hcryp->Instance))->KEYR7 = *(uint32_t *)(hcryp->Init.pKey); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U); + break; + case CRYP_KEYSIZE_128B: + ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = *(uint32_t *)(hcryp->Init.pKey); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U); + ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U); + + break; + default: + break; + } + } +} + +/** + * @} + */ +#endif /* USE_HAL_SAES_ONLY */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CRYP_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* CRYP */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dcmipp.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dcmipp.c new file mode 100644 index 00000000000..b6195ed75a8 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dcmipp.c @@ -0,0 +1,2276 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_dcmipp.c + * @author MCD Application Team + * @brief DCMIPP HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DCMIPP (Digital Camera Interface Pixel Pipeline) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The sequence below describes how to use this driver to capture image + from a camera module connected to the DCMI Interface. + This sequence does not take into account the configuration of the + camera module, which should be made before to configure and enable + the DCMI to capture images. + + (#) Program the required configuration through the following parameters: + the Format, the VSPolarity,the HSPolarity, the PCKPolarity, the ExtendedDataMode + the SynchroMode, the SynchroCodes of the frame delimite, the SwapBits and the SwapCycles + using HAL_DCMIPP_Init() and HAL_DCMIPP_SetParallelConfig + (#) Program the required configuration through the following parameters: + the FrameRate using HAL_DCMIPP_PIPE_Config function. + + *** Interrupt mode IO operation *** + =================================== + (#) Configure Pipe parameter, destination (one or two) and Capture Mode (Snapshot or Continuous) and enable + the capture request using the following functions: + HAL_DCMIPP_PIPE_Start() or HAL_DCMIPP_PIPE_DoubleBufferStart(). + + (#) Use HAL_DCMIPP_IRQHandler() called under DCMIPP_IRQHandler() interrupt subroutine. + (#) At the end of frame capture request HAL_DCMIPP_IRQHandler() function is executed and user can + add his own function by customization of function pointer PipeFrameEventCallback (member + of DCMIPP handle structure). + (#) In case of common error, the HAL_DCMIPP_IRQHandler() function calls the callback + ErrorCallback otherwise in case of Pipe error + the HAL_DCMIPP_IRQHandler() function calls the callbackPipeErrorCallback. + + (#) The Pipe capture can be suspended and resumed using the following functions + HAL_DCMIPP_PIPE_Suspend() and HAL_DCMIPP_PIPE_Resume(). + + (#) For Snapshot Mode the capture can be re-enabled using the HAL_DCMIPP_PIPE_EnableCapture(); + + (#) Optionally, Program the required configuration through the following parameters: + Client, MemoryPageSize, Traffic, MaxOutstandingTransactions, DPREGStart, DPREGEnd + and WLRURatio using HAL_DCMIPP_SetIPPlugConfig(). + + (#) Optionally, configure and Enable the CROP feature to select a rectangular + window from the received image using HAL_DCMIPP_PIPE_SetCropConfig() + and HAL_DCMIPP_PIPE_EnableCrop() functions. + + (#) Optionally, configure and Enable the line and bytes decimation features + using the following functions HAL_DCMIPP_PIPE_SetLinesDecimationConfig and + HAL_DCMIPP_PIPE_SetBytesDecimationConfig. + + (#) Optionally, configure and enable the line event using the function HAL_DCMIPP_PIPE_EnableLineEvent(). + + (#) Optionally, configure and enable the Limit event using the function HAL_DCMIPP_PIPE_EnableLimitEvent(). + + (#) If needed, reconfigure and change the input pixel format value, the frame rate + value, the capture Mode , the destination memory address , the syncunmask values, + Multiline value and Limit value using respectively + the following functions: HAL_DCMIPP_PIPE_SetInputPixelFormat(), HAL_DCMIPP_PIPE_SetFrameRate(), + HAL_DCMIPP_PIPE_SetCaptureMode(), HAL_DCMIPP_PIPE_SetMemoryAddress(), HAL_DCMIPP_SetSyncUnmask(), + HAL_DCMIPP_PIPE_EnableLineEvent() and HAL_DCMIPP_PIPE_EnableLimitEvent(). + + (#) To read the transferred data counter , use the HAL_DCMIPP_PIPE_GetDataCounter() + + (#) To read and reset the Frame counter of the pipe, use the following functions: + HAL_DCMIPP_PIPE_ReadFrameCounter() and HAL_DCMIPP_PIPE_ResetFrameCounter(). + + (#) The Pipe capture can be Stopped using HAL_DCMIPP_PIPE_Stop() function. + + + (#) To control the DCMIPP state, use the following function: HAL_DCMIPP_GetState(). + + (#) To control the DCMIPP Pipe state, use the following function: HAL_DCMIPP_PIPE_GetState(). + + (#) To read the DCMIPP error code, use the following function: HAL_DCMIPP_GetError(). + + *** DCMIPP HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DCMIPP HAL driver : + + (+) __HAL_DCMIPP_GET_FLAG: Get the DCMIPP pending flags. + (+) __HAL_DCMIPP_CLEAR_FLAG: Clear the DCMIPP pending flags. + (+) __HAL_DCMIPP_ENABLE_IT: Enable the specified DCMIPP interrupts. + (+) __HAL_DCMIPP_DISABLE_IT: Disable the specified DCMIPP interrupts. + (+) __HAL_DCMIPP_GET_IT_SOURCE: Check whether the specified DCMIPP interrupt is enabled or not. + + *** Callback registration *** + =================================== + [..] + (#) The compilation define USE_HAL_DCMIPP_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use function @ref HAL_DCMIPP_RegisterCallback() to register a user callback. + Use function @ref HAL_DCMIPP_PIPE_RegisterCallback() to register a user pipe callback. + + (#) Function @ref HAL_DCMIPP_RegisterCallback() allows to register following callbacks: + (+) ErrorCallback : callback for Error + (+) MspInitCallback : DCMIPP MspInit. + (+) MspDeInitCallback : DCMIPP MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + (#) Function @ref HAL_DCMIPP_PIPE_RegisterCallback() allows to register following callbacks: + (+) PipeFrameEventCallback : callback for Pipe Frame Event. + (+) PipeVsyncEventCallback : callback for Pipe Vsync Event. + (+) PipeLineEventCallback : callback for Pipe Line Event. + (+) PipeLimitEventCallback : callback for Pipe Limit Event. + (+) PipeErrorCallback : callback for Pipe Error + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (#) Use function @ref HAL_DCMIPP_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_DCMIPP_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ErrorCallback : callback for Error + (+) MspInitCallback : DCMIPP MspInit. + (+) MspDeInitCallback : DCMIPP MspDeInit. + (#) Use function @ref HAL_DCMIPP_PIPE_UnRegisterCallback() to reset a pipe callback to the default + weak (surcharged) function. + @ref HAL_DCMIPP_PIPE_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) PipeFrameEventCallback : callback for Pipe Frame Event. + (+) PipeVsyncEventCallback : callback for Pipe Vsync Event. + (+) PipeLineEventCallback : callback for Pipe Line Event. + (+) PipeLimitEventCallback : callback for Pipe Limit Event. + (+) PipeErrorCallback : callback for Pipe Error + + (#) By default, after the @ref HAL_DCMIPP_Init and if the state is HAL_DCMIPP_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples @ref PipeFrameEventCallback(), @ref PipeVsyncEventCallback() + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_DCMIPP_Init + and @ref HAL_DCMIPP_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the @ref HAL_DCMIPP_Init and @ref HAL_DCMIPP_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_DCMIPP_RegisterCallback before calling @ref HAL_DCMIPP_DeInit + or @ref HAL_DCMIPP_Init function. + + When The compilation define USE_HAL_DCMIPP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + [..] + (@) You can refer to the DCMIPP HAL driver header file for more useful macros + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +#ifdef HAL_DCMIPP_MODULE_ENABLED +#if defined (DCMIPP) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +/** @defgroup DCMIPP DCMIPP + * @brief DCMIPP HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup DCMIPP_Private_Functions DCMIPP Private Functions + * @{ + */ +static void Pipe_Config(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, const DCMIPP_PipeConfTypeDef *pPipeConfig); +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DCMIPP_Private_Functions DCMIPP Private Functions + * @{ + */ +/** + * @brief Configure the Pipe + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @param pPipeConfig pointer to the pipe configuration structure + * @param Pipe + * @retval None + */ +static void Pipe_Config(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, const DCMIPP_PipeConfTypeDef *pPipeConfig) +{ + if (Pipe == DCMIPP_PIPE0) + { + /* Configure Pipe0 */ + /* Configure Frame Rate */ + MODIFY_REG(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_FRATE, pPipeConfig->FrameRate); + } +} +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DCMIPP_Exported_Functions DCMIPP Exported Functions + * @{ + */ + +/** @addtogroup DCMIPP_Initialization_De-Initialization_Functions DCMIPP Initialization De-Initialization Functions + * @brief Initialization and De-Initialization Functions + * @{ + */ + +/** + * @brief Initializes the DCMIPP according to the specified + * parameters in the DCMIPP_InitTypeDef and create the associated handle. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_Init(DCMIPP_HandleTypeDef *hdcmipp) +{ + uint32_t pipe_index; + + /* Check pointer validity */ + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance)); + + if (hdcmipp->State == HAL_DCMIPP_STATE_RESET) + { + /* Init the DCMIPP Callback settings */ +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hdcmipp->PIPE_FrameEventCallback = HAL_DCMIPP_PIPE_FrameEventCallback; /* Legacy weak PIPE_FrameEventCallback */ + hdcmipp->PIPE_VsyncEventCallback = HAL_DCMIPP_PIPE_VsyncEventCallback; /* Legacy weak PIPE_VsyncEventCallback */ + hdcmipp->PIPE_LineEventCallback = HAL_DCMIPP_PIPE_LineEventCallback; /* Legacy weak PIPE_LineEventCallback */ + hdcmipp->PIPE_LimitEventCallback = HAL_DCMIPP_PIPE_LimitEventCallback; /* Legacy weak PIPE_LimitEventCallback */ + hdcmipp->PIPE_ErrorCallback = HAL_DCMIPP_PIPE_ErrorCallback; /* Legacy weak PIPE_ErrorCallback */ + hdcmipp->ErrorCallback = HAL_DCMIPP_ErrorCallback; /* Legacy weak _ErrorCallback */ + + if (hdcmipp->MspInitCallback == NULL) + { + /* Legacy weak MspInit Callback */ + hdcmipp->MspInitCallback = HAL_DCMIPP_MspInit; + } + /* Initialize the low level hardware (MSP) */ + hdcmipp->MspInitCallback(hdcmipp); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_DCMIPP_MspInit(hdcmipp); +#endif /* (USE_HAL_DCMIPP_REGISTER_CALLBACKS) */ + } + + /* Change the DCMIPP state */ + hdcmipp->State = HAL_DCMIPP_STATE_BUSY; + + /* Reset DCMIPP Pipe state */ + for (pipe_index = 0U; pipe_index < DCMIPP_NUM_OF_PIPES; pipe_index++) + { + hdcmipp->PipeState[pipe_index] = HAL_DCMIPP_PIPE_STATE_RESET; + } + + /* Update error code */ + hdcmipp->ErrorCode = HAL_DCMIPP_ERROR_NONE; + + /* Update the DCMIPP state*/ + hdcmipp->State = HAL_DCMIPP_STATE_INIT; + + return HAL_OK; +} + +/** + * @brief De-initializes the DCMIPP peripheral registers to their default reset + * values. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_DeInit(DCMIPP_HandleTypeDef *hdcmipp) +{ + uint32_t pipe_index; + + /* Check pointer validity */ + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + /* Disable the Parallel Interface */ + hdcmipp->Instance->PRCR &= ~DCMIPP_PRCR_ENABLE; + + /* Reset flow selection configuration register for the Pipe0 */ + hdcmipp->Instance->P0FSCR = 0; + +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) + if (hdcmipp->MspDeInitCallback == NULL) + { + hdcmipp->MspDeInitCallback = HAL_DCMIPP_MspDeInit; + } + + /* DeInit the low level hardware */ + hdcmipp->MspDeInitCallback(hdcmipp); +#else + /* DeInit the low level hardware */ + HAL_DCMIPP_MspDeInit(hdcmipp); +#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */ + + /* Update error code */ + hdcmipp->ErrorCode = HAL_DCMIPP_ERROR_NONE; + + /* Initialize the DCMIPP state*/ + hdcmipp->State = HAL_DCMIPP_STATE_RESET; + + /* Reset DCMIPP Pipe state */ + for (pipe_index = 0U; pipe_index < DCMIPP_NUM_OF_PIPES; pipe_index++) + { + hdcmipp->PipeState[pipe_index] = HAL_DCMIPP_PIPE_STATE_RESET; + } + + return HAL_OK; +} + +/** + * @brief Initializes the DCMIPP MSP. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @retval None + */ +__weak void HAL_DCMIPP_MspInit(DCMIPP_HandleTypeDef *hdcmipp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdcmipp); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DCMIPP_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-Initializes the DCMIPP MSP. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @retval None + */ +__weak void HAL_DCMIPP_MspDeInit(DCMIPP_HandleTypeDef *hdcmipp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdcmipp); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DCMIPP_MspDeInit could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup DCMIPP_Configuration_Functions DCMIPP Configuration Functions + * @brief Configuration Functions + * @{ + */ +/** + * @brief Configure the DCMIPP Parallel Interface according to the specified + * parameters in the pParallelConfig. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure + * @param pParallelConfig pointer to DCMIPP_ParallelConfTypeDef that contains + * the parallel Interface configuration information for DCMIPP. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PARALLEL_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, + const DCMIPP_ParallelConfTypeDef *pParallelConfig) +{ + uint32_t prcr_reg; + uint32_t prescr_reg; + + /* Check parameters */ + if ((hdcmipp == NULL) || (pParallelConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_DCMIPP_FORMAT(pParallelConfig->Format)); + assert_param(IS_DCMIPP_VSPOLARITY(pParallelConfig->VSPolarity)); + assert_param(IS_DCMIPP_HSPOLARITY(pParallelConfig->HSPolarity)); + assert_param(IS_DCMIPP_PCKPOLARITY(pParallelConfig->PCKPolarity)); + assert_param(IS_DCMIPP_EXTENDED_DATA_MODE(pParallelConfig->ExtendedDataMode)); + assert_param(IS_DCMIPP_SYNC_MODE(pParallelConfig->SynchroMode)); + assert_param(IS_DCMIPP_SWAP_BITS(pParallelConfig->SwapBits)); + assert_param(IS_DCMIPP_SWAP_CYCLES(pParallelConfig->SwapCycles)); + + /* Check DCMIPP state */ + if (hdcmipp->State != HAL_DCMIPP_STATE_INIT) + { + return HAL_ERROR; + } + else + { + /* Configures the Format, VS, HS, PCK polarity, ExtendedDataMode, SynchronisationMode, Swap Cycles and bits */ + prcr_reg = ((pParallelConfig->Format) | \ + (pParallelConfig->VSPolarity) | \ + (pParallelConfig->HSPolarity) | \ + (pParallelConfig->PCKPolarity) | \ + (pParallelConfig->ExtendedDataMode) | \ + (pParallelConfig->SynchroMode) | \ + (pParallelConfig->SwapCycles) | \ + (pParallelConfig->SwapBits)); + + WRITE_REG(hdcmipp->Instance->PRCR, prcr_reg); + + if (pParallelConfig->SynchroMode == DCMIPP_SYNCHRO_EMBEDDED) + { + /* Set Embedded Sync codes */ + prescr_reg = (((uint32_t)pParallelConfig->SynchroCodes.FrameEndCode << DCMIPP_PRESCR_FEC_Pos) | \ + ((uint32_t)pParallelConfig->SynchroCodes.LineEndCode << DCMIPP_PRESCR_LEC_Pos) | \ + ((uint32_t)pParallelConfig->SynchroCodes.FrameStartCode << DCMIPP_PRESCR_FSC_Pos) | \ + ((uint32_t)pParallelConfig->SynchroCodes.LineStartCode << DCMIPP_PRESCR_LSC_Pos)); + + WRITE_REG(hdcmipp->Instance->PRESCR, prescr_reg); + + /* Set Embedded Sync Unmask codes : All codes are unmasked */ + WRITE_REG(hdcmipp->Instance->PRESUR, 0xFFFFFFFFU); + } + + /* Enable the Synchronization error interrupt on parallel interface */ + __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PARALLEL_SYNC_ERROR); + + /* Enable Parallel interface */ + SET_BIT(hdcmipp->Instance->PRCR, DCMIPP_PRCR_ENABLE); + + } + + /* Update the DCMIPP state */ + hdcmipp->State = HAL_DCMIPP_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief Configure pipe + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for the DCMIPP. + * @param Pipe pipe to be configured can be a value from @ref DCMIPP_Pipes + * @param pPipeConfig pointer to pipe configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, + const DCMIPP_PipeConfTypeDef *pPipeConfig) +{ + HAL_DCMIPP_PipeStateTypeDef pipe_state; + + /* Check the DCMIPP peripheral handle parameter and pPipeConfig parameter */ + if ((hdcmipp == NULL) || (pPipeConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance)); + assert_param(IS_DCMIPP_PIPE(Pipe)); + assert_param(IS_DCMIPP_FRAME_RATE(pPipeConfig->FrameRate)); + /* Get Pipe State */ + pipe_state = hdcmipp->PipeState[Pipe]; + + if (hdcmipp->State == HAL_DCMIPP_STATE_READY) + { + if ((pipe_state == HAL_DCMIPP_PIPE_STATE_RESET) || (pipe_state == HAL_DCMIPP_PIPE_STATE_ERROR)) + { + /* Update the DCMIPP PIPE state */ + hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY; + + /* Initialize the DCMIPP Pipe registers */ + Pipe_Config(hdcmipp, Pipe, pPipeConfig); + + /* Update the DCMIPP pipe state */ + hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_READY; + } + else + { + return HAL_ERROR; + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Configure the DCMIPP AXI master memory IP-Plug. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure + * @param pIPPlugConfig pointer to IPPLUG configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_SetIPPlugConfig(DCMIPP_HandleTypeDef *hdcmipp, + const DCMIPP_IPPlugConfTypeDef *pIPPlugConfig) +{ + uint32_t timeout = HAL_GetTick(); + + /* Check handle validity */ + if ((hdcmipp == NULL) || (pIPPlugConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DCMIPP_CLIENT(pIPPlugConfig->Client)); + assert_param(IS_DCMIPP_DPREG_END(pIPPlugConfig->DPREGEnd)); + assert_param(IS_DCMIPP_DPREG_START(pIPPlugConfig->DPREGStart)); + assert_param(IS_DCMIPP_MAX_OUTSTANDING_TRANSACTIONS(pIPPlugConfig->MaxOutstandingTransactions)); + assert_param(IS_DCMIPP_MEMORY_PAGE_SIZE(pIPPlugConfig->MemoryPageSize)); + assert_param(IS_DCMIPP_TRAFFIC(pIPPlugConfig->Traffic)); + assert_param(IS_DCMIPP_WLRU_RATIO(pIPPlugConfig->WLRURatio)); + + + if (hdcmipp->State != HAL_DCMIPP_STATE_RESET) + { + /* Request to lock the IP-Plug, to allow reconfiguration */ + SET_BIT(hdcmipp->Instance->IPGR2, DCMIPP_IPGR2_PSTART); + + do + { + timeout--; + if (timeout == 0U) + { + return HAL_ERROR; + } + } while ((hdcmipp->Instance->IPGR3 & DCMIPP_IPGR3_IDLE) != DCMIPP_IPGR3_IDLE); + } + else + { + return HAL_ERROR; + } + + /* IP-Plug is currently locked and can be reconfigured */ + + /* Set Memory page size */ + hdcmipp->Instance->IPGR1 = (pIPPlugConfig->MemoryPageSize); + + /* IP-PLUG Client1 configuration */ + switch (pIPPlugConfig->Client) + { + case DCMIPP_CLIENT1: + { + /* Set Traffic : Burst size and Maximum Outstanding transactions */ + hdcmipp->Instance->IPC1R1 = (pIPPlugConfig->Traffic | pIPPlugConfig->MaxOutstandingTransactions); + + /* Set End word and Start Word of the FIFO of the Clientx */ + hdcmipp->Instance->IPC1R2 = (pIPPlugConfig->WLRURatio << DCMIPP_IPC1R2_WLRU_Pos); + + /* Set End word and Start Word of the FIFO of the Clientx */ + hdcmipp->Instance->IPC1R3 = ((pIPPlugConfig->DPREGStart << DCMIPP_IPC1R3_DPREGSTART_Pos) | + (pIPPlugConfig->DPREGEnd << DCMIPP_IPC1R3_DPREGEND_Pos)); + break; + } + default: + break; + } + + /* No lock requested, IP-Plug runs on demand by background HW */ + CLEAR_BIT(hdcmipp->Instance->IPGR2, DCMIPP_IPGR2_PSTART); + + /* Enable DCMIPP_IT_AXI_TRANSFER_ERR */ + __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_AXI_TRANSFER_ERROR); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup DCMIPP_IO_operation_Functions DCMIPP IO operation Functions + * @brief IO operation functions + * @{ + */ +/** + * @brief Enables DCMIPP capture on the specified pipe + * @param hdcmipp Pointer to a DCMIPP_HandleTypeDef structure + * @param Pipe pipe to be started can be a value from @ref DCMIPP_Pipes + * @param DstAddress the destination address + * @param CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_Start(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress, + uint32_t CaptureMode) +{ + assert_param(IS_DCMIPP_PIPE(Pipe)); + assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode)); + + /* Check pointer validity */ + if ((hdcmipp == NULL) || ((DstAddress & 0xFU) != 0U)) + { + return HAL_ERROR; + } + + /* Check DCMIPP pipe state */ + if (hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) + { + return HAL_ERROR; + } + + if (Pipe == DCMIPP_PIPE0) + { + /* Update the DCMIPP pipe State */ + hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY; + + /* Set the capture mode */ + hdcmipp->Instance->P0FCTCR |= CaptureMode; + + /* Set the destination address */ + WRITE_REG(hdcmipp->Instance->P0PPM0AR1, DstAddress); + + /* Enable all required interrupts lines for the PIPE0 */ + __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_OVR | + DCMIPP_IT_AXI_TRANSFER_ERROR); + + /* Activate the Pipe */ + SET_BIT(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_PIPEN); + + /* Start the capture */ + SET_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + + +/** + * @brief Enables DCMIPP capture on the specified pipe with double buffering Mode Enabled + * @param hdcmipp Pointer to a DCMIPP_HandleTypeDef structure + * @param Pipe pipe to be started can be a value from @ref DCMIPP_Pipes + * @param DstAddress0 the first destination address + * @param DstAddress1 the second destination address + * @param CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_DoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress0, + uint32_t DstAddress1, uint32_t CaptureMode) +{ + assert_param(IS_DCMIPP_PIPE(Pipe)); + assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode)); + + /* Check pointer validity */ + if ((hdcmipp == NULL) || ((DstAddress0 & 0xFU) != 0U) || ((DstAddress1 & 0xFU) != 0U)) + { + return HAL_ERROR; + } + + /* Check DCMIPP pipe state */ + if (hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) + { + return HAL_ERROR; + } + + if (Pipe == DCMIPP_PIPE0) + { + /* Update the DCMIPP pipe State */ + hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY; + + /* Set the capture mode */ + hdcmipp->Instance->P0FCTCR |= CaptureMode; + + /* Set the destination address */ + WRITE_REG(hdcmipp->Instance->P0PPM0AR1, DstAddress0); + + /* Set the second destination address */ + WRITE_REG(hdcmipp->Instance->P0PPM0AR2, DstAddress1); + + /* Enable Double buffering Mode */ + SET_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_DBM); + + /* Enable all required interrupts lines for the Pipe0 */ + __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_OVR); + + /* Activate the Pipe */ + SET_BIT(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_PIPEN); + + /* Start the capture */ + SET_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Stop DCMIPP capture on the specified pipe + * @param hdcmipp Pointer to a DCMIPP_HandleTypeDef structure + * @param Pipe pipe to be stopped can be a value from @ref DCMIPP_Pipes + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe) +{ + uint32_t timeout = HAL_GetTick(); + HAL_DCMIPP_PipeStateTypeDef pipe_state; + + assert_param(IS_DCMIPP_PIPE(Pipe)); + + /* Check pointer validity */ + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + /* Get Pipe State */ + pipe_state = hdcmipp->PipeState[Pipe]; + + /* Check DCMIPP Pipe state */ + if (pipe_state != HAL_DCMIPP_PIPE_STATE_RESET) + { + if (Pipe == DCMIPP_PIPE0) + { + /* Stop the capture */ + CLEAR_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ); + + /* Check that the Capture Request is effectively stopped */ + do + { + timeout--; + if (timeout == 0U) + { + return HAL_ERROR; + } + } while ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTREQ) != 0U); + + /* Disable DBM when enabled */ + if ((hdcmipp->Instance->P0PPCR & DCMIPP_P0PPCR_DBM) == DCMIPP_P0PPCR_DBM) + { + CLEAR_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_DBM); + } + + /* Disable the pipe */ + CLEAR_BIT(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_PIPEN); + + /* Disable all interrupts for this pipe */ + __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_LINE | \ + DCMIPP_IT_PIPE0_LIMIT | DCMIPP_IT_PIPE0_OVR); + + } + else + { + return HAL_ERROR; + } + + /* Update DCMIPP Pipe State */ + hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Suspend DCMIPP Pipe capture + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure + * @param Pipe pipe to be suspended can be a value from @ref DCMIPP_Pipes + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_Suspend(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe) +{ + HAL_DCMIPP_PipeStateTypeDef pipe_state; + uint32_t timeout = HAL_GetTick(); + + assert_param(IS_DCMIPP_PIPE(Pipe)); + + if (hdcmipp == NULL) + { + /* Return Function Status */ + return HAL_ERROR; + } + + pipe_state = hdcmipp->PipeState[Pipe]; + + if (Pipe == DCMIPP_PIPE0) + { + /* Check Pipe0 State */ + if (pipe_state == HAL_DCMIPP_PIPE_STATE_BUSY) + { + /* Disable Capture Request */ + hdcmipp->Instance->P0FCTCR &= ~DCMIPP_P0FCTCR_CPTREQ; + /* Change Pipe State */ + hdcmipp->PipeState[0] = HAL_DCMIPP_PIPE_STATE_SUSPEND; + + /* Check if the DCMIPP capture effectively disabled */ + do + { + timeout-- ; + if (timeout == 0U) + { + /* Change Pipe State */ + hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_ERROR; + + return HAL_ERROR; + } + } while ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTREQ) != 0U); + + } + else + { + /* Return Function Status */ + return HAL_ERROR; + } + } + else + { + return HAL_ERROR; + } + + /* Return Function Status */ + return HAL_OK; +} + +/** + * @brief Resume DCMIPP Pipe capture + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure + * @param Pipe Pipe to be resumed can be a value from @ref DCMIPP_Pipes + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_Resume(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe) +{ + HAL_DCMIPP_PipeStateTypeDef pipe_state ; + + assert_param(IS_DCMIPP_PIPE(Pipe)); + + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + pipe_state = hdcmipp->PipeState[Pipe]; + + if (Pipe == DCMIPP_PIPE0) + { + /* Check Pipe0 State */ + if (pipe_state == HAL_DCMIPP_PIPE_STATE_SUSPEND) + { + /* Enable Capture Request */ + hdcmipp->Instance->P0FCTCR |= DCMIPP_P0FCTCR_CPTREQ; + + /* Change Pipe State */ + hdcmipp->PipeState[0] = HAL_DCMIPP_PIPE_STATE_BUSY; + } + else + { + return HAL_ERROR; + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup DCMIPP_IRQ_and_Callbacks_Functions DCMIPP IRQ and Callbacks Functions + * @brief IRQ and Callbacks functions + * @{ + */ + +/** @addtogroup DCMIPP_IRQHandler_Functions IRQHandler Functions + * @{ + */ +/** + * @brief Handles DCMIPP interrupt request. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for the DCMIPP. + * @retval None + */ +void HAL_DCMIPP_IRQHandler(DCMIPP_HandleTypeDef *hdcmipp) +{ + uint32_t cmsr2flags = READ_REG(hdcmipp->Instance->CMSR2); + uint32_t cmierflags = READ_REG(hdcmipp->Instance->CMIER); + + /* ========================= PIPE0 INTERRUPTS ==================== */ + /* Limit error on the PIPE0 ********************************************/ + if ((cmsr2flags & DCMIPP_FLAG_PIPE0_LIMIT) != 0U) + { + if ((cmierflags & DCMIPP_IT_PIPE0_LIMIT) != 0U) + { + /* Disable Limit error Interrupt for pipe0 */ + __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_LIMIT); + + /* Update error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_PIPE0_LIMIT; + + /* Clear the Limit error flag */ + __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE0_LIMIT); + + /* LIMIT Callback */ +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) + hdcmipp->PIPE_LimitEventCallback(hdcmipp, DCMIPP_PIPE0); +#else + HAL_DCMIPP_PIPE_LimitEventCallback(hdcmipp, DCMIPP_PIPE0); +#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */ + } + } + + /* VSYNC interrupt management **********************************************/ + if ((cmsr2flags & DCMIPP_FLAG_PIPE0_VSYNC) != 0U) + { + if ((cmierflags & DCMIPP_IT_PIPE0_VSYNC) != 0U) + { + /* Clear the VSYNC flag for pipe0 */ + __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE0_VSYNC); + + /* VSYNC Callback */ +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) + hdcmipp->PIPE_VsyncEventCallback(hdcmipp, DCMIPP_PIPE0); +#else + HAL_DCMIPP_PIPE_VsyncEventCallback(hdcmipp, DCMIPP_PIPE0); +#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */ + } + } + + /* FRAME interrupt management ****************************/ + if ((cmsr2flags & DCMIPP_FLAG_PIPE0_FRAME) != 0U) + { + if ((cmierflags & DCMIPP_IT_PIPE0_FRAME) != 0U) + { + /* When snapshot mode, disable Vsync, Error and Overrun interrupts */ + if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT) + { + __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_OVR); + + /* Update Pipe State */ + hdcmipp->PipeState[0] = HAL_DCMIPP_PIPE_STATE_READY; + } + + /* Clear the End of Frame flag */ + __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE0_FRAME); + + /* Frame Callback */ +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) + hdcmipp->PIPE_FrameEventCallback(hdcmipp, DCMIPP_PIPE0); +#else + HAL_DCMIPP_PIPE_FrameEventCallback(hdcmipp, DCMIPP_PIPE0); +#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */ + } + } + + /* LINE interrupt management **********************************************/ + if ((cmsr2flags & DCMIPP_FLAG_PIPE0_LINE) != 0U) + { + if ((cmierflags & DCMIPP_IT_PIPE0_LINE) != 0U) + { + /* Clear the LINE flag */ + __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE0_LINE); + + /* LINE Callback */ +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) + hdcmipp->PIPE_LineEventCallback(hdcmipp, DCMIPP_PIPE0); +#else + HAL_DCMIPP_PIPE_LineEventCallback(hdcmipp, DCMIPP_PIPE0); +#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */ + } + } + + /* Overrun error interrupt for Pipe0 ***************************************/ + if ((cmsr2flags & DCMIPP_FLAG_PIPE0_OVR) != 0U) + { + if ((cmierflags & DCMIPP_IT_PIPE0_OVR) != 0U) + { + /* Disable Overrun Error Interrupt for pipe0 */ + __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_OVR); + + /* Update error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_PIPE0_OVR; + + /* Clear the overrun error flag */ + __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE0_OVR); + + /* Change DCMIPP Pipe state */ + hdcmipp->PipeState[0] = HAL_DCMIPP_PIPE_STATE_ERROR; + + /* Error Callback */ +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) + hdcmipp->PIPE_ErrorCallback(hdcmipp, DCMIPP_PIPE0); +#else + HAL_DCMIPP_PIPE_ErrorCallback(hdcmipp, DCMIPP_PIPE0); +#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */ + } + } + + + /* Synchronization Error Interrupt on the parallel interface **************/ + if ((cmsr2flags & DCMIPP_FLAG_PARALLEL_SYNC_ERROR) != 0U) + { + if ((cmierflags & DCMIPP_IT_PARALLEL_SYNC_ERROR) != 0U) + { + /* Disable Synchronization error interrupt on parallel interface */ + __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PARALLEL_SYNC_ERROR); + + /* Update error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_PARALLEL_SYNC; + + /* Clear the synchronization error flag */ + __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PARALLEL_SYNC_ERROR); + + /* Change DCMIPP state */ + hdcmipp->State = HAL_DCMIPP_STATE_ERROR; + + /* Error Callback */ +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) + hdcmipp->ErrorCallback(hdcmipp); +#else + HAL_DCMIPP_ErrorCallback(hdcmipp); +#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */ + } + } + + /* IPPLUG AXI transfer Error Interrupt *********************************/ + if ((cmsr2flags & DCMIPP_FLAG_AXI_TRANSFER_ERROR) != 0U) + { + if ((cmierflags & DCMIPP_IT_AXI_TRANSFER_ERROR) != 0U) + { + /* Disable IPPLUG AXI transfer Error Interrupt */ + __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_AXI_TRANSFER_ERROR); + + /* Update error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_AXI_TRANSFER; + + /* Clear the AXI transfer error flag */ + __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_AXI_TRANSFER_ERROR); + + /* Change DCMIPP state */ + hdcmipp->State = HAL_DCMIPP_STATE_ERROR; + + /* Error Callback */ +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) + hdcmipp->ErrorCallback(hdcmipp); +#else + HAL_DCMIPP_ErrorCallback(hdcmipp); +#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */ + } + } +} +/** + * @} + */ + +/** @addtogroup DCMIPP_Callback_Functions Callback Functions + * @{ + */ +/** + * @brief Frame Event callback on the pipe + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @param Pipe pipe to be configured + * @retval None + */ +__weak void HAL_DCMIPP_PIPE_FrameEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DCMIPP_FrameEventDumpPipeCallback could be implemented in the user file + */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Pipe); + UNUSED(hdcmipp); +} + +/** + * @brief Vsync Event callback on pipe + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @param Pipe pipe to be configured + * @retval None + */ +__weak void HAL_DCMIPP_PIPE_VsyncEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DCMIPP_VsyncEventDumpPipeCallback could be implemented in the user file + */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Pipe); + UNUSED(hdcmipp); +} + + +/** + * @brief Line Event callback on the pipe + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @param Pipe pipe to be configured + * @retval None + */ +__weak void HAL_DCMIPP_PIPE_LineEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DCMIPP_LineEventMainPipeCallback could be implemented in the user file + */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Pipe); + UNUSED(hdcmipp); +} + +/** + * @brief Limit callback on the Pipe0 + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @param Pipe pipe to be configured + * @retval None + */ +__weak void HAL_DCMIPP_PIPE_LimitEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DCMIPP_LimitEventDumpPipeCallback could be implemented in the user file + */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Pipe); + UNUSED(hdcmipp); +} + +/** + * @brief Error callback on the pipe + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @param Pipe pipe to be configured + * @retval None + */ +__weak void HAL_DCMIPP_PIPE_ErrorCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DCMIPP_SyncErrorEventCallback could be implemented in the user file + */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Pipe); + UNUSED(hdcmipp); +} + + +/** + * @brief Error callback on DCMIPP + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @retval None + */ +__weak void HAL_DCMIPP_ErrorCallback(DCMIPP_HandleTypeDef *hdcmipp) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DCMIPP_ErrorCallback could be implemented in the user file + */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdcmipp); +} +/** + * @} + */ + +/** @addtogroup DCMIPP_RegisterCallback_Functions Register Callback Functions + * @{ + */ +#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User DCMIPP Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hdcmipp DCMIPP handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_DCMIPP_ERROR_CB_ID DCMIPP Error callback ID + * @arg @ref HAL_DCMIPP_MSPINIT_CB_ID DCMIPP MspInit callback ID + * @arg @ref HAL_DCMIPP_MSPDEINIT_CB_ID DCMIPP MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_DCMIPP_RegisterCallback(DCMIPP_HandleTypeDef *hdcmipp, HAL_DCMIPP_CallbackIDTypeDef CallbackID, + pDCMIPP_CallbackTypeDef pCallback) +{ + + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hdcmipp->State == HAL_DCMIPP_STATE_READY) + { + switch (CallbackID) + { + case HAL_DCMIPP_MSPINIT_CB_ID : + hdcmipp->MspInitCallback = pCallback; + break; + + case HAL_DCMIPP_MSPDEINIT_CB_ID : + hdcmipp->MspDeInitCallback = pCallback; + break; + + case HAL_DCMIPP_ERROR_CB_ID : + hdcmipp->ErrorCallback = pCallback; + break; + + default : + /* Update the error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hdcmipp->State == HAL_DCMIPP_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DCMIPP_MSPINIT_CB_ID : + hdcmipp->MspInitCallback = pCallback; + break; + + case HAL_DCMIPP_MSPDEINIT_CB_ID : + hdcmipp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User DCMIPP Callback + * DCMIPP Callback is redirected to the weak (surcharged) predefined callback + * @param hdcmipp DCMIPP handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_DCMIPP_ERROR_CB_ID DCMIPP Error callback ID + * @arg @ref HAL_DCMIPP_MSPINIT_CB_ID DCMIPP MspInit callback ID + * @arg @ref HAL_DCMIPP_MSPDEINIT_CB_ID DCMIPP MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_DCMIPP_UnRegisterCallback(DCMIPP_HandleTypeDef *hdcmipp, HAL_DCMIPP_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hdcmipp->State == HAL_DCMIPP_STATE_READY) + { + switch (CallbackID) + { + case HAL_DCMIPP_MSPINIT_CB_ID : + hdcmipp->MspInitCallback = HAL_DCMIPP_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_DCMIPP_MSPDEINIT_CB_ID : + hdcmipp->MspDeInitCallback = HAL_DCMIPP_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hdcmipp->State == HAL_DCMIPP_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DCMIPP_MSPINIT_CB_ID : + hdcmipp->MspInitCallback = HAL_DCMIPP_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_DCMIPP_MSPDEINIT_CB_ID : + hdcmipp->MspDeInitCallback = HAL_DCMIPP_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register a User DCMIPP Pipe Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hdcmipp DCMIPP handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_DCMIPP_PIPE_FRAME_EVENT_CB_ID DCMIPP Pipe Frame event callback ID + * @arg @ref HAL_DCMIPP_PIPE_VSYNC_EVENT_CB_ID DCMIPP Pipe Vsync event callback ID + * @arg @ref HAL_DCMIPP_PIPE_LINE_EVENT_CB_ID DCMIPP Pipe Line event callback ID + * @arg @ref HAL_DCMIPP_PIPE_LIMIT_EVENT_CB_ID DCMIPP Pipe Limit event callback ID + * @arg @ref HAL_DCMIPP_PIPE_ERROR_CB_ID DCMIPP Pipe Error callback ID + * @param pCallback pointer to the Pipe Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_RegisterCallback(DCMIPP_HandleTypeDef *hdcmipp, + HAL_DCMIPP_PIPE_CallbackIDTypeDef CallbackID, + pDCMIPP_PIPE_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hdcmipp->State == HAL_DCMIPP_STATE_READY) + { + switch (CallbackID) + { + case HAL_DCMIPP_PIPE_FRAME_EVENT_CB_ID : + hdcmipp->PIPE_FrameEventCallback = pCallback; + break; + + case HAL_DCMIPP_PIPE_VSYNC_EVENT_CB_ID : + hdcmipp->PIPE_VsyncEventCallback = pCallback; + break; + + case HAL_DCMIPP_PIPE_LINE_EVENT_CB_ID : + hdcmipp->PIPE_LineEventCallback = pCallback; + break; + + case HAL_DCMIPP_PIPE_LIMIT_EVENT_CB_ID : + hdcmipp->PIPE_LimitEventCallback = pCallback; + break; + + case HAL_DCMIPP_PIPE_ERROR_CB_ID : + hdcmipp->PIPE_ErrorCallback = pCallback; + break; + + default : + /* Update the error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister a User DCMIPP Pipe Callback + * DCMIPP Callback is redirected to the weak (surcharged) predefined callback + * @param hdcmipp DCMIPP handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_DCMIPP_PIPE_FRAME_EVENT_CB_ID DCMIPP Pipe Frame event callback ID + * @arg @ref HAL_DCMIPP_PIPE_VSYNC_EVENT_CB_ID DCMIPP Pipe Vsync event callback ID + * @arg @ref HAL_DCMIPP_PIPE_LINE_EVENT_CB_ID DCMIPP Pipe Line event callback ID + * @arg @ref HAL_DCMIPP_PIPE_LIMIT_EVENT_CB_ID DCMIPP Pipe Limit event callback ID + * @arg @ref HAL_DCMIPP_PIPE_ERROR_CB_ID DCMIPP Pipe Error callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_UnRegisterCallback(DCMIPP_HandleTypeDef *hdcmipp, + HAL_DCMIPP_PIPE_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hdcmipp->State == HAL_DCMIPP_STATE_READY) + { + switch (CallbackID) + { + case HAL_DCMIPP_PIPE_FRAME_EVENT_CB_ID : + hdcmipp->PIPE_FrameEventCallback = HAL_DCMIPP_PIPE_FrameEventCallback; + break; + + case HAL_DCMIPP_PIPE_VSYNC_EVENT_CB_ID : + hdcmipp->PIPE_VsyncEventCallback = HAL_DCMIPP_PIPE_VsyncEventCallback; + break; + + case HAL_DCMIPP_PIPE_LINE_EVENT_CB_ID : + hdcmipp->PIPE_LineEventCallback = HAL_DCMIPP_PIPE_LineEventCallback; + break; + + case HAL_DCMIPP_PIPE_LIMIT_EVENT_CB_ID : + hdcmipp->PIPE_LimitEventCallback = HAL_DCMIPP_PIPE_LimitEventCallback; + break; + + case HAL_DCMIPP_PIPE_ERROR_CB_ID : + hdcmipp->PIPE_ErrorCallback = HAL_DCMIPP_PIPE_ErrorCallback; + break; + + default : + /* Update the error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */ +/** + * @} + */ +/** + * @} + */ +/** @defgroup DCMIPP_Crop_Functions DCMIPP Crop Functions + * @{ + */ +/** + * @brief Configure the DCMIPP CROP coordinate. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure + * @param pCropConfig pointer to DCMIPP_CropConfTypeDef structure that contains + * the configuration information for Crop + * @param Pipe pipe where crop is configured + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetCropConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, + const DCMIPP_CropConfTypeDef *pCropConfig) +{ + uint32_t tmp; + + /* Check handle validity */ + if ((hdcmipp == NULL) || (pCropConfig == NULL)) + { + return HAL_ERROR; + } + + assert_param(IS_DCMIPP_PIPE(Pipe)); + assert_param(IS_DCMIPP_PIPE_CROP_AREA(pCropConfig->PipeArea)); + assert_param(IS_DCMIPP_PIPE_CROP_HSTART(pCropConfig->HStart)); + assert_param(IS_DCMIPP_PIPE_CROP_HSIZE(pCropConfig->HSize)); + assert_param(IS_DCMIPP_PIPE_CROP_VSIZE(pCropConfig->VSize)); + assert_param(IS_DCMIPP_PIPE_CROP_VSTART(pCropConfig->VStart)); + + /* Check the DCMIPP State */ + if (hdcmipp->State == HAL_DCMIPP_STATE_READY) + { + + if (Pipe == DCMIPP_PIPE0) + { + tmp = READ_REG(hdcmipp->Instance->PRCR); + + /* Verify for parallel mode with jpeg format , no Line Crop enable */ + if (((tmp & DCMIPP_PRCR_ENABLE) == DCMIPP_PRCR_ENABLE) && ((tmp & DCMIPP_PRCR_FORMAT) == DCMIPP_FORMAT_BYTE)) + { + return HAL_ERROR; + } + else + { + /* Set Cropping horizontal and vertical start for Pipe0 */ + MODIFY_REG(hdcmipp->Instance->P0SCSTR, DCMIPP_P0SCSTR_HSTART | DCMIPP_P0SCSTR_VSTART, + (pCropConfig->HStart << DCMIPP_P0SCSTR_HSTART_Pos) | + (pCropConfig->VStart << DCMIPP_P0SCSTR_VSTART_Pos)); + + /* Set Cropping horizontal and vertical width for Pipe0 */ + /* Set crop Area (Inner or outer) for Pipe0 */ + MODIFY_REG(hdcmipp->Instance->P0SCSZR, DCMIPP_P0SCSZR_HSIZE | DCMIPP_P0SCSZR_VSIZE | DCMIPP_P0SCSZR_POSNEG, + (pCropConfig->HSize << DCMIPP_P0SCSZR_HSIZE_Pos) | (pCropConfig->VSize << DCMIPP_P0SCSZR_VSIZE_Pos) | + (pCropConfig->PipeArea)); + } + } + else + { + return HAL_ERROR; + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Enable the Crop feature. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @param Pipe pipe where crop is enabled + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableCrop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe) +{ + uint32_t tmp; + + assert_param(IS_DCMIPP_PIPE(Pipe)); + + /* Check handle validity */ + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + if (hdcmipp->State == HAL_DCMIPP_STATE_READY) + { + if (Pipe == DCMIPP_PIPE0) + { + /* This bit must be kept cleared if the input format is JPEG */ + /* Verify for parallel mode with jpeg format , no Line Crop enable */ + + tmp = READ_REG(hdcmipp->Instance->PRCR); + + if (((tmp & DCMIPP_PRCR_ENABLE) == DCMIPP_PRCR_ENABLE) && ((tmp & DCMIPP_PRCR_FORMAT) == DCMIPP_FORMAT_BYTE)) + { + return HAL_ERROR; + } + else + { + SET_BIT(hdcmipp->Instance->P0SCSZR, DCMIPP_P0SCSZR_ENABLE); + } + } + else + { + return HAL_ERROR; + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disable the Crop feature. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @param Pipe pipe where crop is disabled + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableCrop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe) +{ + assert_param(IS_DCMIPP_PIPE(Pipe)); + + /* Check handle validity */ + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + if (Pipe == DCMIPP_PIPE0) + { + CLEAR_BIT(hdcmipp->Instance->P0SCSZR, DCMIPP_P0SCSZR_ENABLE); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup DCMIPP_Decimation_Functions DCMIPP Decimation Functions + * @{ + */ +/** + * @brief Configure the Bytes decimation for the selected Pipe. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure + * @param Pipe pipe where bytes decimation is enabled + * @param SelectStart can a be value from @ref DCMIPP_Byte_Start_Mode + * @param SelectMode can be a value from @ref DCMIPP_Byte_Select_Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetBytesDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, + uint32_t SelectStart, uint32_t SelectMode) +{ + uint32_t tmp; + + assert_param(IS_DCMIPP_PIPE(Pipe)); + assert_param(IS_DCMIPP_BYTE_SELECT_START(SelectStart)); + assert_param(IS_DCMIPP_BYTE_SELECT_MODE(SelectMode)); + + /* Check handle validity */ + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + if (Pipe == DCMIPP_PIPE0) + { + /* OEBS : This bit works in conjunction with BSM field (BSM != 00) */ + /* Modes 10 and 11 work only with EDM [2:0] = 000 into the DCMIPP_PRCR */ + tmp = (hdcmipp->Instance->PRCR & DCMIPP_PRCR_EDM); + + if (((SelectStart == DCMIPP_OEBS_EVEN) && (SelectMode > DCMIPP_BSM_ALL)) || \ + ((SelectMode > DCMIPP_BSM_DATA_OUT_2) && (tmp != DCMIPP_INTERFACE_8BITS))) + { + return HAL_ERROR; + } + else + { + /* Set Bytes select Start and Bytes select Mode */ + MODIFY_REG(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_BSM | DCMIPP_P0PPCR_OEBS, (SelectStart | SelectMode)); + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Configure the Lines decimation for the selected Pipe. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure + * @param Pipe pipe where Lines decimation is enabled + * @param SelectStart can a be value from @ref DCMIPP_Line_Start_Mode + * @param SelectMode can be a value from @ref DCMIPP_Line_Select_Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetLinesDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, + uint32_t SelectStart, uint32_t SelectMode) +{ + assert_param(IS_DCMIPP_PIPE(Pipe)); + assert_param(IS_DCMIPP_LINE_SELECT_MODE(SelectMode)); + assert_param(IS_DCMIPP_LINE_SELECT_START(SelectStart)); + + /* Check handle validity */ + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + if (Pipe == DCMIPP_PIPE0) + { + /* This bit works in conjunction with LSM field (LSM = 1) */ + if ((SelectStart == DCMIPP_OELS_EVEN) && (SelectMode == DCMIPP_LSM_ALTERNATE_2)) + { + return HAL_ERROR; + } + else + { + /* Set Lines select Start and Bytes select Mode */ + MODIFY_REG(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_LSM | DCMIPP_P0PPCR_OELS, (SelectStart | SelectMode)); + } + } + else + { + return HAL_ERROR; + } + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup DCMIPP_LimitEvent_Functions DCMIPP Limit Event Functions + * @{ + */ +/** + * @brief Define the Data dump limit for the Pipe0. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure + * @param Pipe pipe where Data limit is enabled + * @param Limit Data dump Limit. + * @note User application may resort to HAL_DCMIPP_PIPE_LimitCallback() at Limit interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableLimitEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Limit) +{ + assert_param(IS_DCMIPP_PIPE(Pipe)); + assert_param(IS_DCMIPP_DATA_LIMIT(Limit)); + + /* Check Parameters */ + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + if (Pipe == DCMIPP_PIPE0) + { + /* Set and enable data limit on Pipe 0 */ + WRITE_REG(hdcmipp->Instance->P0DCLMTR, (Limit << DCMIPP_P0DCLMTR_LIMIT_Pos) | DCMIPP_P0DCLMTR_ENABLE); + + /* Enable Limit Interrupt for pipe0 */ + __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_LIMIT); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disable the the Limit interrupt. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure + * @param Pipe pipe where Limit interrupt is disabled + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableLimitEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe) +{ + assert_param(IS_DCMIPP_PIPE(Pipe)); + + /* Check Parameters */ + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + if (Pipe == DCMIPP_PIPE0) + { + /* Disable data limit on Pipe 0 */ + CLEAR_BIT(hdcmipp->Instance->P0DCLMTR, DCMIPP_P0DCLMTR_ENABLE); + + /* Disable Limit Interrupt for pipe0 */ + __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_LIMIT); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DCMIPP_PeripheralControl_Functions DCMIPP Peripheral Control Functions + * @{ + */ +/** + * @brief Reconfigure the Frame Rate for the selected pipe + * @param hdcmipp pointer to a DCMIPP_HandleTypeDfef structure + * @param FrameRate the new Frame Rate value. + * @param Pipe Pipe to be reconfigured + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetFrameRate(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t FrameRate) +{ + /* Check Parameters */ + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_DCMIPP_PIPE(Pipe)); + assert_param(IS_DCMIPP_FRAME_RATE(FrameRate)); + + /* Set Frame Rate for the Pipe */ + if (Pipe == DCMIPP_PIPE0) + { + MODIFY_REG(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_FRATE, FrameRate); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reconfigure Capture Mode for the selected pipe + * @param hdcmipp pointer to a DCMIPP_HandleTypeDfef structure + * @param CaptureMode the new Capture Mode value. + * @param Pipe Pipe to be reconfigured + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetCaptureMode(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t CaptureMode) +{ + /* Check Parameters */ + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + assert_param(IS_DCMIPP_PIPE(Pipe)); + assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode)); + + + /* Set Capture Mode */ + if (Pipe == DCMIPP_PIPE0) + { + MODIFY_REG(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTMODE, CaptureMode); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Re-Enable Capture for the selected pipe + * @param hdcmipp pointer to a DCMIPP_HandleTypeDfef structure + * @param Pipe Pipe to be re-enable capture request + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableCapture(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe) +{ + /* Check Parameters */ + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + /* Request Capture for the chosen Pipe */ + + if (Pipe == DCMIPP_PIPE0) + { + SET_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reconfigure the destination memory address for the selected pipe + * @param hdcmipp pointer to a DCMIPP_HandleTypeDfef structure + * @param Memory the destination address to be changed can be value from DCMIPP. + * @param DstAddress the new destination address + * @param Pipe Pipe to be reconfigured + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetMemoryAddress(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Memory, + uint32_t DstAddress) +{ + /* Check Parameters */ + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + assert_param(IS_DCMIPP_PIPE(Pipe)); + assert_param(IS_DCMIPP_MEMORY_ADDRESS(Memory)); + + /* Request Capture for the chosen Pipe */ + + if (Pipe == DCMIPP_PIPE0) + { + if (Memory == DCMIPP_MEMORY_ADDRESS_0) + { + /* Set Memory0 destination addresses for pipe0 */ + WRITE_REG(hdcmipp->Instance->P0PPM0AR1, DstAddress); + } + else + { + if ((hdcmipp->Instance->P0PPCR & DCMIPP_P0PPCR_DBM) == DCMIPP_P0PPCR_DBM) + { + /* Set Memory1 destination addresses for pipe0 */ + WRITE_REG(hdcmipp->Instance->P0PPM0AR2, DstAddress); + } + else + { + return HAL_ERROR; + } + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; + +} + +/** + * @brief Reconfigure the input pixel format for the selected pipe + * @param hdcmipp pointer to a DCMIPP_HandleTypeDfef structure + * @param InputPixelFormat new pixel format value. + * @param Pipe Pipe to be reconfigured + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_PARALLEL_SetInputPixelFormat(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, + uint32_t InputPixelFormat) +{ + assert_param(IS_DCMIPP_PIPE(Pipe)); + assert_param(IS_DCMIPP_FORMAT(InputPixelFormat)); + + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + if (Pipe == DCMIPP_PIPE0) + { + /* Set Frame Rate */ + MODIFY_REG(hdcmipp->Instance->PRCR, DCMIPP_PRCR_FORMAT, InputPixelFormat); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} +/** + * @brief Set embedded synchronization delimiters unmasks. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure + * @param SyncUnmask pointer to a DCMIPP_SyncUnmaskTypeDef structure that contains + * the embedded synchronization delimiters unmasks. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PARALLEL_SetSyncUnmask(DCMIPP_HandleTypeDef *hdcmipp, + const DCMIPP_EmbeddedSyncUnmaskTypeDef *SyncUnmask) +{ + uint32_t presur_reg; + uint32_t prcr_reg; + + /* Check pointer validity */ + if ((hdcmipp == NULL) || (SyncUnmask == NULL)) + { + return HAL_ERROR; + } + + /* Check the DCMIPP State */ + if (hdcmipp->State == HAL_DCMIPP_STATE_READY) + { + prcr_reg = hdcmipp->Instance->PRCR; + /* Check that Embedded synchronisation mode is configured */ + if ((prcr_reg & DCMIPP_PRCR_ESS) == DCMIPP_SYNCHRO_EMBEDDED) + { + /* Configure DCMIPP embedded synchronization unmask register */ + presur_reg = (((uint32_t)SyncUnmask->FrameStartUnmask << DCMIPP_PRESUR_FSU_Pos) | \ + ((uint32_t)SyncUnmask->LineStartUnmask << DCMIPP_PRESUR_LSU_Pos) | \ + ((uint32_t)SyncUnmask->LineEndUnmask << DCMIPP_PRESUR_LEU_Pos) | \ + ((uint32_t)SyncUnmask->FrameEndUnmask << DCMIPP_PRESUR_FEU_Pos)); + + WRITE_REG(hdcmipp->Instance->PRESUR, presur_reg); + } + else + { + return HAL_ERROR; + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DCMIPP_Line_Event_Functions DCMIPP Line Event Functions + * @{ + */ + +/** + * @brief Define the position of the line interrupt. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure + * @param Pipe pipe where Line event is enabled + * @param Line Line Interrupt Position. + * @note User application may resort to HAL_DCMIPP_PIPE_LineEventCallback() at line interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableLineEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Line) +{ + assert_param(IS_DCMIPP_PIPE(Pipe)); + assert_param(IS_DCMIPP_PIPE_MULTILINE(Line)); + + if (Pipe == DCMIPP_PIPE0) + { + /* Set MultiLine configuration */ + MODIFY_REG(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_LINEMULT, Line); + + /* Enable Multiline Interrupt */ + __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_LINE); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disable the the line event interrupt. + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure + * @param Pipe pipe where Line event is disabled + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableLineEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe) +{ + assert_param(IS_DCMIPP_PIPE(Pipe)); + + /* Disable Multiline Interrupt */ + if (Pipe == DCMIPP_PIPE0) + { + __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_LINE); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + + + +/** + * @} + */ + +/** @defgroup DCMIPP_Frame_Counter_Functions DCMIPP Frame Counter Functions + * @{ + */ + +/** + * @brief Reset the DCMIPP Pipe frame counter + * @param Pipe Pipe selected to reset frame + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_ResetFrameCounter(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe) +{ + + /* Check pointer validity */ + if (hdcmipp == NULL) + { + return HAL_ERROR; + } + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Pipe); + /* Check parameters */ + assert_param(IS_DCMIPP_PIPE(Pipe)); + + /* Check the DCMIPP State */ + if (hdcmipp->State == HAL_DCMIPP_STATE_READY) + { + /* Clear Frame counter */ + SET_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_CFC); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Read the DCMIPP frame counter + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure + * @param Pipe Pipe selected to read frame counter + * @param pCounter pointer to store the value of the frame counter + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_ReadFrameCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, + uint32_t *pCounter) +{ + + /* Check parameters */ + assert_param(IS_DCMIPP_PIPE(Pipe)); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Pipe); + /* Check pointer validity */ + if ((hdcmipp == NULL) || (pCounter == NULL)) + { + return HAL_ERROR; + } + + /* Check the DCMIPP State */ + if (hdcmipp->State == HAL_DCMIPP_STATE_READY) + { + /* Read frame counter */ + *pCounter = READ_REG(hdcmipp->Instance->CMFRCR); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup DCMIPP_Data_Counter_Functions DCMIPP Data Counter Functions + * @{ + */ +/** + * @brief Read Number of data dumped during the frame for the Pipe0 + * The counter saturates at 0x3FFFFFF. Granularity is 32-bit for all the + * formats except for the byte stream formats (e.g. JPEG) having byte granularity + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for the DCMIPP. + * @param Pipe Pipe selected to get data counter + * @param pCounter pointer to amount of word transferred + * @retval Status + */ +HAL_StatusTypeDef HAL_DCMIPP_PIPE_GetDataCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, + uint32_t *pCounter) +{ + /* Check parameters */ + assert_param(IS_DCMIPP_PIPE(Pipe)); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Pipe); + /* Check pointer validity */ + if ((hdcmipp == NULL) || (pCounter == NULL)) + { + return HAL_ERROR; + } + + /* Check the DCMIPP State */ + if (hdcmipp->State == HAL_DCMIPP_STATE_READY) + { + /* Read Pipe0 dump counter register */ + *pCounter = READ_REG(hdcmipp->Instance->P0DCCNTR); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + + +/** + * @} + */ + +/** @defgroup DCMIPP_State_and_Error_Functions DCMIPP State and Error Functions + * @{ + */ + +/** + * @brief Return the DCMIPP state + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @retval HAL state + */ +HAL_DCMIPP_StateTypeDef HAL_DCMIPP_GetState(const DCMIPP_HandleTypeDef *hdcmipp) +{ + return hdcmipp->State; +} + +/** + * @brief Return the DCMIPP error code + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @retval DCMIPP Error Code + */ +uint32_t HAL_DCMIPP_GetError(const DCMIPP_HandleTypeDef *hdcmipp) +{ + return hdcmipp->ErrorCode; +} + +/** + * @brief Return the DCMIPP state + * @param hdcmipp pointer to a DCMIPP_HandleTypeDef structure that contains + * the configuration information for DCMIPP. + * @param Pipe Pipe selected to get state + * @retval HAL state + */ +HAL_DCMIPP_PipeStateTypeDef HAL_DCMIPP_PIPE_GetState(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe) +{ + /* Check Parameters */ + assert_param(IS_DCMIPP_PIPE(Pipe)); + + return hdcmipp->PipeState[Pipe]; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* DCMIPP */ +#endif /* HAL_DCMIPP_MODULE_ENABLED */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma.c new file mode 100644 index 00000000000..5a136cd7883 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma.c @@ -0,0 +1,1745 @@ +/** + ********************************************************************************************************************** + * @file stm32h7rsxx_hal_dma.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following functionalities of the Direct Memory Access + * (DMA) peripheral: + * + Initialization/De-Initialization Functions + * + I/O Operation Functions + * + State and Errors Functions + * + DMA Attributes Functions + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + @verbatim + ====================================================================================================================== + ##### How to use this driver ##### + ====================================================================================================================== + [..] + (#) GPDMA and HPDMA are made available on this series. + Transfer could be done thanks to AXI or AHB ports. + + HPDMA support transmission through: + AXI port 0. + AHB port 1. + GPDMA allows transmission through: + GPDMA_P = port-0. + GPDMA_M = port-1 + + The following table list the supported configurations for HPDMA. + HPDMA support the following transfer + Table 1. HPDMA: supported transfer with source (SAP in CTR1 register) + / (DAP in CTR1 register) destination settings. + +-----------------------------------------------------------------------+ + | Destination|0 1 2 3 | 4 5 | 6 | 7 | 8 | 9 | + | Source | | | | | | | + |-----------------|--------|--------|--------|--------|--------|--------| + | 0 1 2 3 |0/0 |0/0-1 |0/0-1 |0/1 |0/0 |0/1 | + |-----------------|--------|--------|--------|--------|--------|--------| + | 4 5 |0-1/0 |0-1/0-1 |0-1/0-1 |0-1/1 |0-1/0 |0-1/1 | + +-----------------------------------------------------------------------+ + | 6 |0-1/0 |0-1/0-1 |0-1/0-1 |0-1/1 |0-1/0 |0-1/1 | + +-----------------------------------------------------------------------+ + | 7 |1/0 |1/0-1 |1/0-1 |1/1 |1/0 |1/1 | + +-----------------------------------------------------------------------+ + | 8 9 |0/0 |0/0-1 |0/0-1 |0/1 |0/0 |0/1 | + +-----------------------------------------------------------------------+ + | 10 11 |1/0 |1/0-1 |1/0-1 |1/1 |1/0 |1/1 | + +-----------------------------------------------------------------------+ + + Source: + 0 AXI_SRAM_IC1_L1 + 1 AXI_SRAM_IC2_L2 + 2 AXI_SRAM_IC3_L3 + 3 AXI_SRAM_IC4_L4 + 4 AHB_SRAM1_IC2_L0 + 5 AHB_SRAM2_IC2_L1 + 6 BACKUP_SRAM + 7 DTCM + 8 FLASH_IC1_L0 + 9 GFXMMU_RAM + 10 FDCAN_SRAM + 11 ITCM + + Destination: + 0 AXI_SRAM_IC1_L1 + 1 AXI_SRAM_IC2_L2 + 2 AXI_SRAM_IC3_L3 + 3 AXI_SRAM_IC4_L4 + 4 AHB_SRAM1_IC2_L0 + 5 AHB_SRAM2_IC2_L1 + 6 BACKUP_SRAM + 7 DTCM + 8 GFXMMU_RAM + 9 FDCAN_SRAM + + The following table list the supported configurations for GPDMA. + GPDMA support the following transfer + Table 2. GPDMA: supported transfer with source (SAP in CTR1 register) + / (DAP in CTR1 register) destination settings. + +-----------------------------------------------------------------------+ + | Destination|0 1 2 3 | 4 5 | 6 | 7 | 8 | 9 | + | Source | | | | | | | + |-----------------|--------|--------|--------|--------|--------|--------| + | 0 1 2 3 |0-1/0 |0-1/0-1 |0-1/0-1 | XXX | XXX |0-1/0-1 | + |-----------------|--------|--------|--------|--------|--------|--------| + | 4 5 |0-1/0 |0-1/0-1 |0-1/0-1 | XXX | XXX |0-1/0-1 | + +-----------------------------------------------------------------------+ + | 6 |0-1/0 |0-1/0-1 |0-1/0-1 | XXX | XXX |0-1/0-1 | + +-----------------------------------------------------------------------+ + | 7 | XXX | XXX | XXX | XXX | XXX | XXX | + +-----------------------------------------------------------------------+ + | 8 |0-1/0 |0-1/0-1 |0-1/0-1 | XXX | XXX |0-1/0-1 | + +-----------------------------------------------------------------------+ + | 9 | XXX | XXX | XXX | XXX | XXX | XXX | + +-----------------------------------------------------------------------+ + | 10 |0-1/0 |0-1/0-1 |0-1/0-1 | XXX | XXX |0-1/0-1 | + +-----------------------------------------------------------------------+ + | 11 | XXX | XXX | XXX | XXX | XXX | XXX | + +-----------------------------------------------------------------------+ + + Link-list transfer requires the nodes to be located in a memory than be be + accessed by the HPDMA or GPDMA. + + Table 3. HPDMA: supported linked-list node memory location versus Linked-List + allocated port (LPA in CCR register). + +--------------------------+ + | | Port | + | Node location | | + |-----------------|--------| + | 0 1 2 3 | 0 | + |-----------------|--------| + | 4 5 | 0-1 | + +--------------------------- + | 6 | 0-1 | + +--------------------------- + | 7 | 1 | + +--------------------------- + | 8 9 | 0 | + +--------------------------- + | 10 11 | 1 | + +--------------------------+ + + Table 4. GPDMA: supported linked-list node memory location versus Linked-List + allocated port (LPA in CCR register). + +--------------------------+ + | | Port | + | Node location | | + |-----------------|--------| + | 0 1 2 3 | 0-1 | + |-----------------|--------| + | 4 5 | 0-1 | + +--------------------------- + | 6 | 0-1 | + +--------------------------- + | 7 | XXX | + +--------------------------- + | 8 | 0-1 | + +--------------------------- + | 9 | XXX | + +--------------------------- + | 10 | 0-1 | + +--------------------------- + | 11 | XXX | + +--------------------------+ + + + When the HPDMA is used with the following peripherals: JPEG, XSPI1, XSPI2, + SPI3, SPI4, ADC1, ADC2, ADF1, UART4, UART5, UART7 or LPTIM2, + the AHB port 1 should be selected on the peripheral side. + + + + [..] + DMA transfer modes are divided to 2 major categories : + (+) Normal transfers (legacy) + (+) Linked-list transfers + + [..] + Normal transfers mode is initialized via the standard module and linked-list mode is configured via the extended + module. + + [..] + Additionally to linked-list capability, all advanced DMA features are managed and configured via the extended + module as extensions to normal mode. + Advanced features are : + (+) Repeated block feature. + (+) Trigger feature. + (+) Data handling feature. + + [..] + DMA Legacy circular transfer, is replaced by circular linked-list configuration. + + + *** Initialization and De-Initialization *** + ============================================ + [..] + For a given channel, enable and configure the peripheral to be connected to the DMA Channel (except for internal + SRAM/FLASH memories: no initialization is necessary) please refer to Reference manual for connection between + peripherals and DMA requests. + + [..] + For a given channel, use HAL_DMA_Init function to program the required configuration for normal transfer through + the following parameters: + + (+) Request : Specifies the DMA channel request + Request parameters : + (++) can be a value of DMA_Request_Selection + + (+) BlkHWRequest : Specifies the Block hardware request mode for DMA channel + (++) can be a value of DMA_Block_Request + + (+) Direction : Specifies the transfer direction for DMA channel + (++) can be a value of DMA_Transfer_Direction + + (+) SrcInc : Specifies the source increment mode for the DMA channel + (++) can be a value of DMA_Source_Increment_Mode + + (+) DestInc : Specifies the destination increment mode for the DMA channel + (++) can be a value of DMA_Destination_Increment_Mode + + (+) SrcDataWidth : Specifies the source data width for the DMA channel + (++) can be a value of DMA_Source_Data_Width + + (+) DestDataWidth : Specifies the destination data width for the DMA channel + (++) can be a value of DMA_Destination_Data_Width + + (+) Priority : Specifies the priority for the DMA channel + (++) can be a value of DMA_Priority_Level + + (+) SrcBurstLength : Specifies the source burst length (number of beats) for the DMA channel + (++) can be a value of between 1 and 64 + + (+) DestBurstLength : Specifies the destination burst length (number of beats) for the DMA channel + (++) can be a value of between 1 and 64 + + (+) TransferAllocatedPort : Specifies the source and destination allocated ports + (++) can be a value of DMA_Transfer_Allocated_Port + + (+) TransferEventMode : Specifies the transfer event mode for the DMA channel + (++) can be a value of DMA_Transfer_Event_Mode + + (+) Mode : Specifies the transfer mode for the DMA channel + (++) can be one of the following modes : + (+++) DMA_NORMAL : Normal Mode + (+++) DMA_PFCTRL : Peripheral Flow Control (peripheral early termination) Mode + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start a DMA normal transfer after the configuration of source address, destination + address and the size of data to be transferred. + + (+) Use HAL_DMA_PollForTransfer() to poll for selected transfer level. In this case a fixed Timeout can be + configured by User depending on his application. + Transfer level can be : + (++) HAL_DMA_HALF_TRANSFER + (++) HAL_DMA_FULL_TRANSFER + For circular transfer, this API returns an HAL_ERROR with HAL_DMA_ERROR_NOT_SUPPORTED error code. + + (+) Use HAL_DMA_Abort() function to abort any ongoing DMA transfer in blocking mode. + This API returns HAL_ERROR when there is no ongoing transfer or timeout is reached when disabling the DMA + channel. (This API should not be called from an interrupt service routine) + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + + (+) Use HAL_DMA_RegisterCallback() function to register user callbacks from the following list : + (++) XferCpltCallback : transfer complete callback. + (++) XferHalfCpltCallback : half transfer complete callback. + (++) XferErrorCallback : transfer error callback. + (++) XferAbortCallback : transfer abort complete callback. + (++) XferSuspendCallback : transfer suspend complete callback. + + (+) Use HAL_DMA_Start_IT() to start the DMA transfer after the enable of DMA interrupts and the configuration + of source address,destination address and the size of data to be transferred. + + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() interrupt subroutine to handle any DMA interrupt. + + (+) Use HAL_DMA_Abort_IT() function to abort any on-going DMA transfer in non-blocking mode. + This API will suspend immediately the DMA channel execution. When the transfer is effectively suspended, + an interrupt is generated and HAL_DMA_IRQHandler() will reset the channel and execute the callback + XferAbortCallback. (This API could be called from an interrupt service routine) + + + *** State and errors *** + ======================== + [..] + (+) Use HAL_DMA_GetState() function to get the DMA state. + (+) Use HAL_DMA_GetError() function to get the DMA error code. + + + *** Privilege attributes *** + ========================================= + [..] + (+) Use HAL_DMA_ConfigChannelAttributes() function to configure privilege attribute. + (++) Privilege : at channel level. + (+) Use HAL_DMA_GetConfigChannelAttributes() function to get the DMA channel attributes. + (+) Use HAL_DMA_LockChannelAttributes() function to lock the DMA channel privilege attribute + configuration. This API can be called once after each system boot. + If called again, HAL_DMA_ConfigChannelAttributes() API has no effect. + Unlock is done either by a system boot or a by an RCC reset. + (+) Use HAL_DMA_GetLockChannelAttributes() function to get the attributes lock status. + + + *** DMA HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE : Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE : Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG : Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG : Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT : Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT : Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE : Check whether the specified DMA Channel interrupt has occurred or not. + + [..] + (@) You can refer to the header file of the DMA HAL driver for more useful macros. + + @endverbatim + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef ---------------------------------------------------------------------------------------------------*/ +/* Private constants -------------------------------------------------------------------------------------------------*/ +/* Private macro -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize); +static void DMA_Init(DMA_HandleTypeDef const *const hdma); + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * +@verbatim + ====================================================================================================================== + ##### Initialization and de-initialization functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the DMA channel in normal mode. + + [..] + (+) The HAL_DMA_Init() function follows the DMA channel configuration procedures as described in reference manual. + (+) The HAL_DMA_DeInit() function allows to de-initialize the DMA channel. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef and + * create the associated handle. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) + { + assert_param(IS_DMA_REQUEST(hdma->Init.Request)); + } + assert_param(IS_DMA_BLOCK_HW_REQUEST(hdma->Init.BlkHWRequest)); + assert_param(IS_DMA_SOURCE_INC(hdma->Init.SrcInc)); + assert_param(IS_DMA_DESTINATION_INC(hdma->Init.DestInc)); + assert_param(IS_DMA_SOURCE_DATA_WIDTH(hdma->Init.SrcDataWidth)); + assert_param(IS_DMA_DESTINATION_DATA_WIDTH(hdma->Init.DestDataWidth)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + assert_param(IS_DMA_TCEM_EVENT_MODE(hdma->Init.TransferEventMode)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + if (hdma->Init.Mode == DMA_PFCTRL) + { + assert_param(IS_DMA_PFREQ_INSTANCE(hdma->Instance)); + } + /* Check DMA channel instance */ + if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)) + { + assert_param(IS_DMA_BURST_LENGTH(hdma->Init.SrcBurstLength)); + assert_param(IS_DMA_BURST_LENGTH(hdma->Init.DestBurstLength)); + assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(hdma->Init.TransferAllocatedPort)); + } + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Initialize the DMA channel registers */ + DMA_Init(hdma); + + /* Update DMA channel operation mode */ + hdma->Mode = hdma->Init.Mode; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA channel when it is configured in normal mode. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + /* Disable the selected DMA Channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset DMA Channel registers */ + hdma->Instance->CLBAR = 0U; + hdma->Instance->CCR = 0U; + hdma->Instance->CTR1 = 0U; + hdma->Instance->CTR2 = 0U; + hdma->Instance->CBR1 = 0U; + hdma->Instance->CSAR = 0U; + hdma->Instance->CDAR = 0U; + hdma->Instance->CLLR = 0U; + + /* Reset 2D Addressing registers */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + hdma->Instance->CTR3 = 0U; + hdma->Instance->CBR2 = 0U; + } + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO)); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + + /* Clean DMA queue */ + hdma->LinkedListQueue = NULL; + + /* Clean DMA parent */ + if (hdma->Parent != NULL) + { + hdma->Parent = NULL; + } + + /* Update DMA channel operation mode */ + hdma->Mode = DMA_NORMAL; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * +@verbatim + ====================================================================================================================== + ##### IO operation functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure the source, destination address and data size and Start DMA transfer in normal mode + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + (+) Register and Unregister DMA callbacks + + [..] + (+) The HAL_DMA_Start() function allows to start the DMA channel transfer in normal mode (Blocking mode). + (+) The HAL_DMA_Start_IT() function allows to start the DMA channel transfer in normal mode (Non-blocking mode). + (+) The HAL_DMA_Abort() function allows to abort any on-going transfer (Blocking mode). + (+) The HAL_DMA_Abort_IT() function allows to abort any on-going transfer (Non-blocking mode). + (+) The HAL_DMA_PollForTransfer() function allows to poll on half transfer and transfer complete (Blocking mode). + This API cannot be used for circular transfers. + (+) The HAL_DMA_IRQHandler() function allows to handle any DMA channel interrupt (Non-blocking mode). + (+) The HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() functions allow respectively to register and + unregister user customized callbacks. + User callbacks are called under HAL_DMA_IRQHandler(). + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA channel transfer in normal mode (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for + * the specified DMA Channel. + * @param SrcAddress : The source data address. + * @param DstAddress : The destination data address. + * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize)); + + /* Process locked */ + __HAL_LOCK(hdma); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source address, destination address, the data size and clear flags */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize); + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Starts the DMA channel transfer in normal mode with interrupts enabled (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param SrcAddress : The source data address. + * @param DstAddress : The destination data address. + * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize)); + + /* Process locked */ + __HAL_LOCK(hdma); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source address, destination address, the data size and clear flags */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize); + + /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO)); + + /* Check half transfer complete callback */ + if (hdma->XferHalfCpltCallback != NULL) + { + /* If Half Transfer complete callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + } + + /* Check Half suspend callback */ + if (hdma->XferSuspendCallback != NULL) + { + /* If Transfer suspend callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP); + } + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Abort any on-going DMA channel transfer (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @note After suspending a DMA channel, a wait until the DMA channel is effectively stopped is added. If a channel + * is suspended while a data transfer is on-going, the current data will be transferred and the channel will be + * effectively suspended only after the transfer of any on-going data is finished. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Suspend the channel */ + hdma->Instance->CCR |= DMA_CCR_SUSP; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; + + /* Check if the DMA Channel is suspended */ + while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Reset the channel */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Clear all status flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO)); + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + + /* Clear remaining data size to ensure loading linked-list from memory next start */ + hdma->Instance->CBR1 = 0U; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + return HAL_OK; +} + +/** + * @brief Abort any on-going DMA channel transfer in interrupt mode (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + return HAL_ERROR; + } + else + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Suspend the channel and activate suspend interrupt */ + hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE); + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer status (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param CompleteLevel : Specifies the DMA level complete. + * @param Timeout : Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, + HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + uint32_t level_flag; + uint32_t tmp_csr; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_LEVEL_COMPLETE(CompleteLevel)); + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Polling mode is not supported in circular mode */ + if ((hdma->Mode & DMA_LINKEDLIST_CIRCULAR) == DMA_LINKEDLIST_CIRCULAR) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + level_flag = ((CompleteLevel == HAL_DMA_FULL_TRANSFER) ? DMA_FLAG_IDLE : DMA_FLAG_HT); + + /* Get DMA channel status */ + tmp_csr = hdma->Instance->CSR; + + while ((tmp_csr & level_flag) == 0U) + { + /* Check for the timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + + /* + If timeout, abort the current transfer. + Note that the Abort function will + - Clear all transfer flags. + - Unlock. + - Set the State. + */ + (void)HAL_DMA_Abort(hdma); + + return HAL_ERROR; + } + } + + /* Get a newer CSR register value */ + tmp_csr = hdma->Instance->CSR; + } + + /* Check trigger overrun flag */ + if ((tmp_csr & DMA_FLAG_TO) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TO; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO); + } + + /* Check error flags */ + if ((tmp_csr & (DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE)) != 0U) + { + /* Check the data transfer error flag */ + if ((tmp_csr & DMA_FLAG_DTE) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DTE; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE); + } + + /* Check the update link error flag */ + if ((tmp_csr & DMA_FLAG_ULE) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_ULE; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE); + } + + /* Check the user setting error flag */ + if ((tmp_csr & DMA_FLAG_USE) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_USE; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE); + } + + /* Reset the channel */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Clear the transfer level flag */ + if (CompleteLevel == HAL_DMA_HALF_TRANSFER) + { + /* Clear the Half Transfer flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT); + } + else if (CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the transfer flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT)); + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Handle DMA interrupt request (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval None. + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) +{ + const DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma); + uint32_t global_it_flag = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Global Interrupt Flag management *********************************************************************************/ + if (IS_DMA_GLOBAL_ACTIVE_FLAG(p_dma_instance, global_it_flag) == 0U) + { + return; /* the global interrupt flag for the current channel is down , nothing to do */ + } + + /* Data Transfer Error Interrupt management *************************************************************************/ + if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U)) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DTE) != 0U) + { + /* Clear the transfer error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DTE; + } + } + + /* Update Linked-list Error Interrupt management ********************************************************************/ + if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U)) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_ULE) != 0U) + { + /* Clear the update linked-list error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_ULE; + } + } + + /* User Setting Error Interrupt management **************************************************************************/ + if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U)) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_USE) != 0U) + { + /* Clear the user setting error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_USE; + } + } + + /* Trigger Overrun Interrupt management *****************************************************************************/ + if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U)) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TO) != 0U) + { + /* Clear the trigger overrun flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TO; + } + } + + /* Half Transfer Complete Interrupt management **********************************************************************/ + if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U)) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) + { + /* Clear the half transfer flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT); + + /* Check half transfer complete callback */ + if (hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + + /* Suspend Transfer Interrupt management ****************************************************************************/ + if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U)) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_SUSP) != 0U) + { + /* Clear the block transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_SUSP); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_ABORT) + { + /* Disable the suspend transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_SUSP); + + /* Reset the channel internal state and reset the FIFO */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + + /* Clear remaining data size to ensure loading linked-list from memory next start */ + hdma->Instance->CBR1 = 0U; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Check transfer abort callback */ + if (hdma->XferAbortCallback != NULL) + { + /* Transfer abort callback */ + hdma->XferAbortCallback(hdma); + } + + return; + } + else + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; + + /* Check transfer suspend callback */ + if (hdma->XferSuspendCallback != NULL) + { + /* Transfer suspend callback */ + hdma->XferSuspendCallback(hdma); + } + } + } + } + + /* Transfer Complete Interrupt management ***************************************************************************/ + if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U)) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) + { + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* If linked-list transfer */ + if (hdma->Instance->CLLR == 0U) + { + if (hdma->Instance->CBR1 == 0U) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + } + } + else + { + /* If normal transfer */ + if (hdma->Instance->CBR1 == 0U) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + } + } + + /* Clear TC and HT transfer flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT)); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Check transfer complete callback */ + if (hdma->XferCpltCallback != NULL) + { + /* Channel Transfer Complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + + /* Manage error case ************************************************************************************************/ + if (hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + /* Reset the channel internal state and reset the FIFO */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Check transfer error callback */ + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callback according to specified ID. + * @note The HAL_DMA_RegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET + * to register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enumeration. + * @param pCallback : Pointer to private callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID, + void (*const pCallback)(DMA_HandleTypeDef *const _hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Check callback ID */ + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + { + /* Register transfer complete callback */ + hdma->XferCpltCallback = pCallback; + break; + } + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + { + /* Register half transfer callback */ + hdma->XferHalfCpltCallback = pCallback; + break; + } + + case HAL_DMA_XFER_ERROR_CB_ID: + { + /* Register transfer error callback */ + hdma->XferErrorCallback = pCallback; + break; + } + + case HAL_DMA_XFER_ABORT_CB_ID: + { + /* Register abort callback */ + hdma->XferAbortCallback = pCallback; + break; + } + + case HAL_DMA_XFER_SUSPEND_CB_ID: + { + /* Register suspend callback */ + hdma->XferSuspendCallback = pCallback; + break; + } + + default: + { + /* Update error status */ + status = HAL_ERROR; + break; + } + } + } + else + { + /* Update error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister callback according to specified ID. + * @note The HAL_DMA_UnRegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET + * to un-register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enum. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Check callback ID */ + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + { + /* UnRegister transfer complete callback */ + hdma->XferCpltCallback = NULL; + break; + } + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + { + /* UnRegister half transfer callback */ + hdma->XferHalfCpltCallback = NULL; + break; + } + + case HAL_DMA_XFER_ERROR_CB_ID: + { + /* UnRegister transfer error callback */ + hdma->XferErrorCallback = NULL; + break; + } + + case HAL_DMA_XFER_ABORT_CB_ID: + { + /* UnRegister abort callback */ + hdma->XferAbortCallback = NULL; + break; + } + + case HAL_DMA_XFER_SUSPEND_CB_ID: + { + /* UnRegister suspend callback */ + hdma->XferSuspendCallback = NULL; + break; + } + + case HAL_DMA_XFER_ALL_CB_ID: + { + /* UnRegister all available callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + break; + } + + default: + { + /* Update error status */ + status = HAL_ERROR; + break; + } + } + } + else + { + /* Update error status */ + status = HAL_ERROR; + } + + return status; +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * +@verbatim + ====================================================================================================================== + ##### State and Errors functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Check the DMA state + (+) Get error code + + [..] + (+) The HAL_DMA_GetState() function allows to get the DMA channel state. + (+) The HAL_DMA_DeInit() function allows to get the DMA channel error code. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA channel state. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval DMA state. + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma) +{ + /* Return the DMA channel state */ + return hdma->State; +} + +/** + * @brief Return the DMA channel error code. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval DMA Error Code. + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma) +{ + /* Return the DMA channel error code */ + return hdma->ErrorCode; +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group4 + * +@verbatim + ====================================================================================================================== + ##### DMA Attributes functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure DMA channel privilege attribute. + (+) Get DMA channel privilege attribute. + (+) Lock DMA channel privilege attribute configuration. + (+) Check whether DMA channel privilege attribute configuration is locked or not. + + [..] + (+) The HAL_DMA_ConfigChannelAttributes() function allows to configure DMA channel privilege attribute. + (+) The HAL_DMA_GetConfigChannelAttributes() function allows to get DMA channel privilege attribute + configuration. + (+) The HAL_DMA_LockChannelAttributes() function allows to lock the DMA channel privilege attribute. + (+) The HAL_DMA_GetLockChannelAttributes() function allows to get the DMA channel privilege attribute lock + status. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMA channel privilege attribute. + * @note These attributes cannot be modified when the corresponding lock state is enabled. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for + * the specified DMA Channel. + * @param ChannelAttributes : Specifies the DMA channel privilege attribute. + * This parameter can be a one or a combination of @ref DMA_Channel_Attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, uint32_t ChannelAttributes) +{ + DMA_TypeDef *p_dma_instance; + uint32_t channel_idx; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes)); + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Check DMA channel privilege attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) == DMA_CHANNEL_ATTR_PRIV_MASK) + { + /* Configure DMA channel privilege attribute */ + if ((ChannelAttributes & DMA_CHANNEL_PRIV) == DMA_CHANNEL_PRIV) + { + p_dma_instance->PRIVCFGR |= channel_idx; + } + else + { + p_dma_instance->PRIVCFGR &= (~channel_idx); + } + } + + return HAL_OK; +} + +/** + * @brief Get the DMA channel privilege attribute. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA Channel. + * @param pChannelAttributes : Pointer to the returned attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, + uint32_t *const pChannelAttributes) +{ + const DMA_TypeDef *p_dma_instance; + uint32_t attributes; + uint32_t channel_idx; + + /* Check the DMA peripheral handle and channel attributes parameters */ + if ((hdma == NULL) || (pChannelAttributes == NULL)) + { + return HAL_ERROR; + } + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Get DMA channel privilege attribute */ + attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV; + /* return value */ + *pChannelAttributes = attributes; + + return HAL_OK; +} + + + +/** + * @brief Lock the DMA channel privilege attribute. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma) +{ + DMA_TypeDef *p_dma_instance; + uint32_t channel_idx; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Lock the DMA channel privilege attribute */ + p_dma_instance->RCFGLOCKR |= channel_idx; + + return HAL_OK; +} + + +/** + * @brief Get the privilege attribute lock state of a DMA channel. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param pLockState : Pointer to lock state (returned value can be DMA_CHANNEL_ATTRIBUTE_UNLOCKED or + * DMA_CHANNEL_ATTRIBUTE_LOCKED). + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState) +{ + const DMA_TypeDef *p_dma_instance; + uint32_t channel_idx; + + /* Check the DMA peripheral handle and lock state parameters */ + if ((hdma == NULL) || (pLockState == NULL)) + { + return HAL_ERROR; + } + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Get channel lock attribute state */ + *pLockState = ((p_dma_instance->RCFGLOCKR & channel_idx) == 0U) ? DMA_CHANNEL_ATTRIBUTE_UNLOCKED : \ + DMA_CHANNEL_ATTRIBUTE_LOCKED; + + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA Private Functions + * @{ + */ + +/** + * @brief Set the DMA channel normal transfer parameters. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param SrcAddress : The source data address. + * @param DstAddress : The destination data address. + * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. + * @retval None. + */ +static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize) +{ + /* Configure the DMA channel data size */ + MODIFY_REG(hdma->Instance->CBR1, DMA_CBR1_BNDT, (SrcDataSize & DMA_CBR1_BNDT)); + + /* Clear all interrupt flags */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO); + + /* Configure DMA channel source address */ + hdma->Instance->CSAR = SrcAddress; + + /* Configure DMA channel destination address */ + hdma->Instance->CDAR = DstAddress; +} + +/** + * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval None. + */ +static void DMA_Init(DMA_HandleTypeDef const *const hdma) +{ + uint32_t tmpreg; + + /* Prepare DMA Channel Control Register (CCR) value *****************************************************************/ + tmpreg = hdma->Init.Priority; + + /* Write DMA Channel Control Register (CCR) */ + MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg); + + /* Prepare DMA Channel Transfer Register (CTR1) value ***************************************************************/ + tmpreg = hdma->Init.DestInc | hdma->Init.DestDataWidth | hdma->Init.SrcInc | hdma->Init.SrcDataWidth; + + /* Add parameters specific to HPDMA and GPDMA */ + if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)) + { + tmpreg |= (hdma->Init.TransferAllocatedPort | + (((hdma->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) | + (((hdma->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1)); + } + + /* Write DMA Channel Transfer Register 1 (CTR1) */ + WRITE_REG(hdma->Instance->CTR1, tmpreg); + + /* Prepare DMA Channel Transfer Register 2 (CTR2) value *************************************************************/ + tmpreg = hdma->Init.BlkHWRequest | (hdma->Init.Request & DMA_CTR2_REQSEL) | hdma->Init.TransferEventMode; + + /* Memory to Peripheral Transfer */ + if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)) + { + tmpreg |= DMA_CTR2_DREQ; + } + } + /* Memory to Memory Transfer */ + else if ((hdma->Init.Direction) == DMA_MEMORY_TO_MEMORY) + { + tmpreg |= DMA_CTR2_SWREQ; + } + else + { + /* Nothing to do */ + } + + /* Set DMA channel operation mode */ + tmpreg |= hdma->Init.Mode; + + /* Write DMA Channel Transfer Register 2 (CTR2) */ + MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM | + DMA_CTR2_PFREQ | DMA_CTR2_BREQ | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | + DMA_CTR2_REQSEL), tmpreg); + + + /* Write DMA Channel Block Register 1 (CBR1) ************************************************************************/ + WRITE_REG(hdma->Instance->CBR1, 0U); + + /* If 2D Addressing is supported by current channel */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + /* Write DMA Channel Transfer Register 3 (CTR3) *******************************************************************/ + WRITE_REG(hdma->Instance->CTR3, 0U); + + /* Write DMA Channel Block Register 2 (CBR2) **********************************************************************/ + WRITE_REG(hdma->Instance->CBR2, 0U); + } + + /* Write DMA Channel linked-list address register (CLLR) ************************************************************/ + WRITE_REG(hdma->Instance->CLLR, 0U); +} +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma2d.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma2d.c new file mode 100644 index 00000000000..6bbf3288115 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma2d.c @@ -0,0 +1,2186 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_dma2d.c + * @author MCD Application Team + * @brief DMA2D HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the DMA2D peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Program the required configuration through the following parameters: + the transfer mode, the output color mode and the output offset using + HAL_DMA2D_Init() function. + + (#) Program the required configuration through the following parameters: + the input color mode, the input color, the input alpha value, the alpha mode, + the red/blue swap mode, the inverted alpha mode and the input offset using + HAL_DMA2D_ConfigLayer() function for foreground or/and background layer. + + *** Polling mode IO operation *** + ================================= + [..] + (#) Configure pdata parameter (explained hereafter), destination and data length + and enable the transfer using HAL_DMA2D_Start(). + (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage + user can specify the value of timeout according to his end application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (#) Configure pdata parameter, destination and data length and enable + the transfer using HAL_DMA2D_Start_IT(). + (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine. + (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback (member + of DMA2D handle structure). + (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback + XferErrorCallback. + + -@- In Register-to-Memory transfer mode, pdata parameter is the register + color, in Memory-to-memory or Memory-to-Memory with pixel format + conversion pdata is the source address. + + -@- Configure the foreground source address, the background source address, + the destination and data length then Enable the transfer using + HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT() + in interrupt mode. + + -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions + are used if the memory to memory with blending transfer mode is selected. + + (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling + mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode. + + (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent(). + + (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two + consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime() + and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or + HAL_DMA2D_DisableDeadTime(). + + (#) The transfer can be suspended, resumed and aborted using the following + functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort(). + + (#) The CLUT loading can be suspended, resumed and aborted using the following + functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(), + HAL_DMA2D_CLUTLoading_Abort(). + + (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState(). + + (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError(). + + *** DMA2D HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA2D HAL driver : + + (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral. + (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags. + (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags. + (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts. + (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts. + (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not. + + *** Callback registration *** + =================================== + [..] + (#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback. + + (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks: + (+) XferCpltCallback : callback for transfer complete. + (+) XferErrorCallback : callback for transfer error. + (+) LineEventCallback : callback for line event. + (+) CLUTLoadingCpltCallback : callback for CLUT loading completion. + (+) MspInitCallback : DMA2D MspInit. + (+) MspDeInitCallback : DMA2D MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) XferCpltCallback : callback for transfer complete. + (+) XferErrorCallback : callback for transfer error. + (+) LineEventCallback : callback for line event. + (+) CLUTLoadingCpltCallback : callback for CLUT loading completion. + (+) MspInitCallback : DMA2D MspInit. + (+) MspDeInitCallback : DMA2D MspDeInit. + + (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback() + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init + and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + Exception as well for Transfer Completion and Transfer Error callbacks that are not defined + as weak (surcharged) functions. They must be defined by the user to be resorted to. + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit + or @ref HAL_DMA2D_Init function. + + When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + [..] + (@) You can refer to the DMA2D HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +#ifdef HAL_DMA2D_MODULE_ENABLED +#if defined (DMA2D) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup DMA2D DMA2D + * @brief DMA2D HAL module driver + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup DMA2D_Private_Constants DMA2D Private Constants + * @{ + */ + +/** @defgroup DMA2D_TimeOut DMA2D Time Out + * @{ + */ +#define DMA2D_TIMEOUT_ABORT (1000U) /*!< 1s */ +#define DMA2D_TIMEOUT_SUSPEND (1000U) /*!< 1s */ +/** + * @} + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup DMA2D_Private_Functions DMA2D Private Functions + * @{ + */ +static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height); +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions + * @{ + */ + +/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DMA2D + (+) De-initialize the DMA2D + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA2D according to the specified + * parameters in the DMA2D_InitTypeDef and create the associated handle. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) +{ + /* Check the DMA2D peripheral state */ + if (hdma2d == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance)); + assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode)); + assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode)); + assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset)); + assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted)); + assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap)); + assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode)); + assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap)); + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + if (hdma2d->State == HAL_DMA2D_STATE_RESET) + { + /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */ + hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; + hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; + if (hdma2d->MspInitCallback == NULL) + { + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; + } + + /* Init the low level hardware */ + hdma2d->MspInitCallback(hdma2d); + } +#else + if (hdma2d->State == HAL_DMA2D_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hdma2d->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_DMA2D_MspInit(hdma2d); + } +#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* DMA2D CR register configuration -------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode); + + /* DMA2D OPFCCR register configuration ---------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB, + hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap); + + /* DMA2D OOR register configuration ------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); + /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/ + MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI | DMA2D_OPFCCR_RBS), + ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | \ + (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos))); + + + /* Update error code */ + hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; + + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Deinitializes the DMA2D peripheral registers to their default reset + * values. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ + +HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) +{ + + /* Check the DMA2D peripheral state */ + if (hdma2d == NULL) + { + return HAL_ERROR; + } + + /* Before aborting any DMA2D transfer or CLUT loading, check + first whether or not DMA2D clock is enabled */ + if (__HAL_RCC_DMA2D_IS_CLK_ENABLED() == 1U) + { + /* Abort DMA2D transfer if any */ + if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START) + { + if (HAL_DMA2D_Abort(hdma2d) != HAL_OK) + { + /* Issue when aborting DMA2D transfer */ + return HAL_ERROR; + } + } + else + { + /* Abort background CLUT loading if any */ + if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) + { + if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK) + { + /* Issue when aborting background CLUT loading */ + return HAL_ERROR; + } + } + else + { + /* Abort foreground CLUT loading if any */ + if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) + { + if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK) + { + /* Issue when aborting foreground CLUT loading */ + return HAL_ERROR; + } + } + } + } + } + + /* Reset DMA2D control registers*/ + hdma2d->Instance->CR = 0U; + hdma2d->Instance->IFCR = 0x3FU; + hdma2d->Instance->FGOR = 0U; + hdma2d->Instance->BGOR = 0U; + hdma2d->Instance->FGPFCCR = 0U; + hdma2d->Instance->BGPFCCR = 0U; + hdma2d->Instance->OPFCCR = 0U; + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + + if (hdma2d->MspDeInitCallback == NULL) + { + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; + } + + /* DeInit the low level hardware */ + hdma2d->MspDeInitCallback(hdma2d); + +#else + /* Carry on with de-initialization of low level hardware */ + HAL_DMA2D_MspDeInit(hdma2d); +#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ + + /* Update error code */ + hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; + + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Initializes the DMA2D MSP. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ +__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_MspInit can be implemented in the user file. + */ +} + +/** + * @brief DeInitializes the DMA2D MSP. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ +__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_MspDeInit can be implemented in the user file. + */ +} + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User DMA2D Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hdma2d DMA2D handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID + * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID + * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID + * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID + * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID + * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID + * @retval status + */ +HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, + pDMA2D_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hdma2d); + + if (HAL_DMA2D_STATE_READY == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : + hdma2d->XferCpltCallback = pCallback; + break; + + case HAL_DMA2D_TRANSFERERROR_CB_ID : + hdma2d->XferErrorCallback = pCallback; + break; + + case HAL_DMA2D_LINEEVENT_CB_ID : + hdma2d->LineEventCallback = pCallback; + break; + + case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : + hdma2d->CLUTLoadingCpltCallback = pCallback; + break; + + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = pCallback; + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_DMA2D_STATE_RESET == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = pCallback; + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma2d); + return status; +} + +/** + * @brief Unregister a DMA2D Callback + * DMA2D Callback is redirected to the weak (surcharged) predefined callback + * @param hdma2d DMA2D handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID + * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID + * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID + * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID + * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID + * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID + * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID + * @retval status + */ +HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma2d); + + if (HAL_DMA2D_STATE_READY == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : + hdma2d->XferCpltCallback = NULL; + break; + + case HAL_DMA2D_TRANSFERERROR_CB_ID : + hdma2d->XferErrorCallback = NULL; + break; + + case HAL_DMA2D_LINEEVENT_CB_ID : + hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; + break; + + case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : + hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; + break; + + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_DMA2D_STATE_RESET == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma2d); + return status; +} +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + +/** + * @} + */ + + +/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the pdata, destination address and data size then + start the DMA2D transfer. + (+) Configure the source for foreground and background, destination address + and data size then start a MultiBuffer DMA2D transfer. + (+) Configure the pdata, destination address and data size then + start the DMA2D transfer with interrupt. + (+) Configure the source for foreground and background, destination address + and data size then start a MultiBuffer DMA2D transfer with interrupt. + (+) Abort DMA2D transfer. + (+) Suspend DMA2D transfer. + (+) Resume DMA2D transfer. + (+) Enable CLUT transfer. + (+) Configure CLUT loading then start transfer in polling mode. + (+) Configure CLUT loading then start transfer in interrupt mode. + (+) Abort DMA2D CLUT loading. + (+) Suspend DMA2D CLUT loading. + (+) Resume DMA2D CLUT loading. + (+) Poll for transfer complete. + (+) handle DMA2D interrupt request. + (+) Transfer watermark callback. + (+) CLUT Transfer Complete callback. + + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA2D Transfer. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param pdata Configure the source memory Buffer address if + * Memory-to-Memory or Memory-to-Memory with pixel format + * conversion mode is selected, or configure + * the color value if Register-to-Memory mode is selected. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source + * to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); + + /* Enable the Peripheral */ + __HAL_DMA2D_ENABLE(hdma2d); + + return HAL_OK; +} + +/** + * @brief Start the DMA2D Transfer with interrupt enabled. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param pdata Configure the source memory Buffer address if + * the Memory-to-Memory or Memory-to-Memory with pixel format + * conversion mode is selected, or configure + * the color value if Register-to-Memory mode is selected. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source + * to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); + + /* Enable the transfer complete, transfer error and configuration error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE); + + /* Enable the Peripheral */ + __HAL_DMA2D_ENABLE(hdma2d); + + return HAL_OK; +} + +/** + * @brief Start the multi-source DMA2D Transfer. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param SrcAddress1 The source memory Buffer address for the foreground layer. + * @param SrcAddress2 The source memory Buffer address for the background layer. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source + * to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, + uint32_t DstAddress, uint32_t Width, uint32_t Height) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) + { + /*blending & fixed FG*/ + WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1); + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height); + } + else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG) + { + /*blending & fixed BG*/ + WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2); + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); + } + else + { + /* Configure DMA2D Stream source2 address */ + WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); + + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); + } + + /* Enable the Peripheral */ + __HAL_DMA2D_ENABLE(hdma2d); + + return HAL_OK; +} + +/** + * @brief Start the multi-source DMA2D Transfer with interrupt enabled. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param SrcAddress1 The source memory Buffer address for the foreground layer. + * @param SrcAddress2 The source memory Buffer address for the background layer. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source + * to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, + uint32_t DstAddress, uint32_t Width, uint32_t Height) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) + { + /*blending & fixed FG*/ + WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1); + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height); + } + else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG) + { + /*blending & fixed BG*/ + WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2); + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); + } + else + { + WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); + + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); + } + + /* Enable the transfer complete, transfer error and configuration error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE); + + /* Enable the Peripheral */ + __HAL_DMA2D_ENABLE(hdma2d); + + return HAL_OK; +} + +/** + * @brief Abort the DMA2D Transfer. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) +{ + uint32_t tickstart; + + /* Abort the DMA2D transfer */ + /* START bit is reset to make sure not to set it again, in the event the HW clears it + between the register read and the register write by the CPU (writing 0 has no + effect on START bitvalue) */ + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the DMA2D is effectively disabled */ + while ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) + { + if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_TIMEOUT; + } + } + + /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE); + + /* Change the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Suspend the DMA2D Transfer. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) +{ + uint32_t tickstart; + + /* Suspend the DMA2D transfer */ + /* START bit is reset to make sure not to set it again, in the event the HW clears it + between the register read and the register write by the CPU (writing 0 has no + effect on START bitvalue). */ + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the DMA2D is effectively suspended */ + while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START) + { + if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ + if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) + { + hdma2d->State = HAL_DMA2D_STATE_SUSPEND; + } + else + { + /* Make sure SUSP bit is cleared since it is meaningless + when no transfer is on-going */ + CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + } + + return HAL_OK; +} + +/** + * @brief Resume the DMA2D Transfer. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) +{ + /* Check the SUSP and START bits */ + if ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START)) + { + /* Ongoing transfer is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } + + /* Resume the DMA2D transfer */ + /* START bit is reset to make sure not to set it again, in the event the HW clears it + between the register read and the register write by the CPU (writing 0 has no + effect on START bitvalue). */ + CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP | DMA2D_CR_START)); + + return HAL_OK; +} + + +/** + * @brief Enable the DMA2D CLUT Transfer. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + if (LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Enable the background CLUT loading */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); + } + else + { + /* Enable the foreground CLUT loading */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + } + + return HAL_OK; +} + +/** + * @brief Start DMA2D CLUT Loading. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * the configuration information for the color look up table. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, + uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the CLUT of the background DMA2D layer */ + if (LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT); + + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + + /* Enable the CLUT loading for the background */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + + /* Enable the CLUT loading for the foreground */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + } + + return HAL_OK; +} + +/** + * @brief Start DMA2D CLUT Loading with interrupt enabled. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * the configuration information for the color look up table. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, + uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the CLUT of the background DMA2D layer */ + if (LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT); + + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); + + /* Enable the CLUT loading for the background */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); + + /* Enable the CLUT loading for the foreground */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + } + + return HAL_OK; +} + +/** + * @brief Start DMA2D CLUT Loading. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * the configuration information for the color look up table. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @note API obsolete and maintained for compatibility with legacy. User is + * invited to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from + * code compactness, code size and improved heap usage. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the CLUT of the background DMA2D layer */ + if (LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + + /* Enable the CLUT loading for the background */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + + /* Enable the CLUT loading for the foreground */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + } + + return HAL_OK; +} + +/** + * @brief Start DMA2D CLUT Loading with interrupt enabled. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * the configuration information for the color look up table. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @note API obsolete and maintained for compatibility with legacy. User is + * invited to resort to HAL_DMA2D_CLUTStartLoad_IT() instead to benefit + * from code compactness, code size and improved heap usage. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the CLUT of the background DMA2D layer */ + if (LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); + + /* Enable the CLUT loading for the background */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); + + /* Enable the CLUT loading for the foreground */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + } + + return HAL_OK; +} + +/** + * @brief Abort the DMA2D CLUT loading. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + uint32_t tickstart; + const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ + + /* Abort the CLUT loading */ + SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT); + + /* If foreground CLUT loading is considered, update local variables */ + if (LayerIdx == DMA2D_FOREGROUND_LAYER) + { + reg = &(hdma2d->Instance->FGPFCCR); + } + + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the CLUT loading is aborted */ + while ((*reg & DMA2D_BGPFCCR_START) != 0U) + { + if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_TIMEOUT; + } + } + + /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); + + /* Change the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Suspend the DMA2D CLUT loading. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + uint32_t tickstart; + uint32_t loadsuspended; + const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ + + /* Suspend the CLUT loading */ + SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + + /* If foreground CLUT loading is considered, update local variables */ + if (LayerIdx == DMA2D_FOREGROUND_LAYER) + { + reg = &(hdma2d->Instance->FGPFCCR); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the CLUT loading is suspended */ + /* 1st condition: Suspend Check */ + loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL; + /* 2nd condition: Not Start Check */ + loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL; + while (loadsuspended == 0UL) + { + if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + /* 1st condition: Suspend Check */ + loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL; + /* 2nd condition: Not Start Check */ + loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL; + } + + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ + if ((*reg & DMA2D_BGPFCCR_START) != 0U) + { + hdma2d->State = HAL_DMA2D_STATE_SUSPEND; + } + else + { + /* Make sure SUSP bit is cleared since it is meaningless + when no transfer is on-going */ + CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + } + + return HAL_OK; +} + +/** + * @brief Resume the DMA2D CLUT loading. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + /* Check the SUSP and START bits for background or foreground CLUT loading */ + if (LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Background CLUT loading suspension check */ + if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) + { + if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) + { + /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } + } + } + else + { + /* Foreground CLUT loading suspension check */ + if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) + { + if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) + { + /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } + } + } + + /* Resume the CLUT loading */ + CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + + return HAL_OK; +} + + +/** + + * @brief Polling for transfer complete or CLUT loading. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t layer_start; + __IO uint32_t isrflags = 0x0U; + + /* Polling for DMA2D transfer */ + if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U) + { + isrflags = READ_REG(hdma2d->Instance->ISR); + if ((isrflags & (DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U) + { + if ((isrflags & DMA2D_FLAG_CE) != 0U) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + } + if ((isrflags & DMA2D_FLAG_TE) != 0U) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + } + /* Clear the transfer and configuration error flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE); + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_TIMEOUT; + } + } + } + } + /* Polling for CLUT loading (foreground or background) */ + layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START; + layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START; + if (layer_start != 0U) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U) + { + isrflags = READ_REG(hdma2d->Instance->ISR); + if ((isrflags & (DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U) + { + if ((isrflags & DMA2D_FLAG_CAE) != 0U) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; + } + if ((isrflags & DMA2D_FLAG_CE) != 0U) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + } + if ((isrflags & DMA2D_FLAG_TE) != 0U) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + } + /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE); + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_TIMEOUT; + } + } + } + } + + /* Clear the transfer complete and CLUT loading flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC); + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} +/** + * @brief Handle DMA2D interrupt request. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) +{ + uint32_t isrflags = READ_REG(hdma2d->Instance->ISR); + uint32_t crflags = READ_REG(hdma2d->Instance->CR); + + /* Transfer Error Interrupt management ***************************************/ + if ((isrflags & DMA2D_FLAG_TE) != 0U) + { + if ((crflags & DMA2D_IT_TE) != 0U) + { + /* Disable the transfer Error interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + + /* Clear the transfer error flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + if (hdma2d->XferErrorCallback != NULL) + { + /* Transfer error Callback */ + hdma2d->XferErrorCallback(hdma2d); + } + } + } + /* Configuration Error Interrupt management **********************************/ + if ((isrflags & DMA2D_FLAG_CE) != 0U) + { + if ((crflags & DMA2D_IT_CE) != 0U) + { + /* Disable the Configuration Error interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE); + + /* Clear the Configuration error flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + if (hdma2d->XferErrorCallback != NULL) + { + /* Transfer error Callback */ + hdma2d->XferErrorCallback(hdma2d); + } + } + } + /* CLUT access Error Interrupt management ***********************************/ + if ((isrflags & DMA2D_FLAG_CAE) != 0U) + { + if ((crflags & DMA2D_IT_CAE) != 0U) + { + /* Disable the CLUT access error interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE); + + /* Clear the CLUT access error flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + if (hdma2d->XferErrorCallback != NULL) + { + /* Transfer error Callback */ + hdma2d->XferErrorCallback(hdma2d); + } + } + } + /* Transfer watermark Interrupt management **********************************/ + if ((isrflags & DMA2D_FLAG_TW) != 0U) + { + if ((crflags & DMA2D_IT_TW) != 0U) + { + /* Disable the transfer watermark interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW); + + /* Clear the transfer watermark flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW); + + /* Transfer watermark Callback */ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + hdma2d->LineEventCallback(hdma2d); +#else + HAL_DMA2D_LineEventCallback(hdma2d); +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + + } + } + /* Transfer Complete Interrupt management ************************************/ + if ((isrflags & DMA2D_FLAG_TC) != 0U) + { + if ((crflags & DMA2D_IT_TC) != 0U) + { + /* Disable the transfer complete interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC); + + /* Clear the transfer complete flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + if (hdma2d->XferCpltCallback != NULL) + { + /* Transfer complete Callback */ + hdma2d->XferCpltCallback(hdma2d); + } + } + } + /* CLUT Transfer Complete Interrupt management ******************************/ + if ((isrflags & DMA2D_FLAG_CTC) != 0U) + { + if ((crflags & DMA2D_IT_CTC) != 0U) + { + /* Disable the CLUT transfer complete interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC); + + /* Clear the CLUT transfer complete flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + /* CLUT Transfer complete Callback */ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + hdma2d->CLUTLoadingCpltCallback(hdma2d); +#else + HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d); +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + } + } + +} + +/** + * @brief Transfer watermark callback. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ +__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_LineEventCallback can be implemented in the user file. + */ +} + +/** + * @brief CLUT Transfer Complete callback. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ +__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the DMA2D foreground or background layer parameters. + (+) Configure the DMA2D CLUT transfer. + (+) Configure the line watermark + (+) Configure the dead time value. + (+) Enable or disable the dead time value functionality. + + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMA2D Layer according to the specified + * parameters in the DMA2D_HandleTypeDef. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + const DMA2D_LayerCfgTypeDef *pLayerCfg; + uint32_t regMask; + uint32_t regValue; + + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset)); + if (hdma2d->Init.Mode != DMA2D_R2M) + { + assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode)); + if (hdma2d->Init.Mode != DMA2D_M2M) + { + assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode)); + } + } + assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted)); + assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap)); + + if ((LayerIdx == DMA2D_FOREGROUND_LAYER) && (hdma2d->LayerCfg[LayerIdx].InputColorMode == DMA2D_INPUT_YCBCR)) + { + assert_param(IS_DMA2D_CHROMA_SUB_SAMPLING(hdma2d->LayerCfg[LayerIdx].ChromaSubSampling)); + } + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; + + /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */ + regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) | \ + (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos); + regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS); + + + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + { + regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA); + } + else + { + regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos); + } + + /* Configure the background DMA2D layer */ + if (LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Write DMA2D BGPFCCR register */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue); + + /* DMA2D BGOR register configuration -------------------------------------*/ + WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset); + + /* DMA2D BGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + { + WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \ + DMA2D_BGCOLR_RED)); + } + } + /* Configure the foreground DMA2D layer */ + else + { + + if (pLayerCfg->InputColorMode == DMA2D_INPUT_YCBCR) + { + regValue |= (pLayerCfg->ChromaSubSampling << DMA2D_FGPFCCR_CSS_Pos); + regMask |= DMA2D_FGPFCCR_CSS; + } + + /* Write DMA2D FGPFCCR register */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue); + + /* DMA2D FGOR register configuration -------------------------------------*/ + WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset); + + /* DMA2D FGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + { + WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \ + DMA2D_FGCOLR_RED)); + } + } + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Configure the DMA2D CLUT Transfer. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * the configuration information for the color look up table. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @note API obsolete and maintained for compatibility with legacy. User is invited + * to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from code compactness, + * code size and improved heap usage. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the CLUT of the background DMA2D layer */ + if (LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + } + + /* Set the DMA2D state to Ready*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + + +/** + * @brief Configure the line watermark. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param Line Line Watermark configuration (maximum 16-bit long value expected). + * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt. + * @note The transfer watermark interrupt is disabled once it has occurred. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line) +{ + /* Check the parameters */ + if (Line > DMA2D_LWR_LW) + { + return HAL_ERROR; + } + else + { + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Sets the Line watermark configuration */ + WRITE_REG(hdma2d->Instance->LWR, Line); + + /* Enable the Line interrupt */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW); + + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; + } +} + +/** + * @brief Enable DMA2D dead time feature. + * @param hdma2d DMA2D handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d) +{ + /* Process Locked */ + __HAL_LOCK(hdma2d); + + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Set DMA2D_AMTCR EN bit */ + SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); + + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Disable DMA2D dead time feature. + * @param hdma2d DMA2D handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d) +{ + /* Process Locked */ + __HAL_LOCK(hdma2d); + + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Clear DMA2D_AMTCR EN bit */ + CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); + + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Configure dead time. + * @note The dead time value represents the guaranteed minimum number of cycles between + * two consecutive transactions on the AHB bus. + * @param hdma2d DMA2D handle. + * @param DeadTime dead time value. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime) +{ + /* Process Locked */ + __HAL_LOCK(hdma2d); + + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Set DMA2D_AMTCR DT field */ + MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos)); + + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @} + */ + + +/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to: + (+) Get the DMA2D state + (+) Get the DMA2D error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the DMA2D state + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL state + */ +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d) +{ + return hdma2d->State; +} + +/** + * @brief Return the DMA2D error code + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for DMA2D. + * @retval DMA2D Error Code + */ +uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d) +{ + return hdma2d->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup DMA2D_Private_Functions DMA2D Private Functions + * @{ + */ + +/** + * @brief Set the DMA2D transfer parameters. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the specified DMA2D. + * @param pdata The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param Width The width of data to be transferred from source to destination. + * @param Height The height of data to be transferred from source to destination. + * @retval HAL status + */ +static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height) +{ + uint32_t tmp; + uint32_t tmp1; + uint32_t tmp2; + uint32_t tmp3; + uint32_t tmp4; + + /* Configure DMA2D data size */ + MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos))); + + /* Configure DMA2D destination address */ + WRITE_REG(hdma2d->Instance->OMAR, DstAddress); + + /* Register to memory DMA2D mode selected */ + if (hdma2d->Init.Mode == DMA2D_R2M) + { + tmp1 = pdata & DMA2D_OCOLR_ALPHA_1; + tmp2 = pdata & DMA2D_OCOLR_RED_1; + tmp3 = pdata & DMA2D_OCOLR_GREEN_1; + tmp4 = pdata & DMA2D_OCOLR_BLUE_1; + + /* Prepare the value to be written to the OCOLR register according to the color mode */ + if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888) + { + tmp = (tmp3 | tmp2 | tmp1 | tmp4); + } + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888) + { + tmp = (tmp3 | tmp2 | tmp4); + } + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565) + { + tmp2 = (tmp2 >> 19U); + tmp3 = (tmp3 >> 10U); + tmp4 = (tmp4 >> 3U); + tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4); + } + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555) + { + tmp1 = (tmp1 >> 31U); + tmp2 = (tmp2 >> 19U); + tmp3 = (tmp3 >> 11U); + tmp4 = (tmp4 >> 3U); + tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4); + } + else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */ + { + tmp1 = (tmp1 >> 28U); + tmp2 = (tmp2 >> 20U); + tmp3 = (tmp3 >> 12U); + tmp4 = (tmp4 >> 4U); + tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4); + } + /* Write to DMA2D OCOLR register */ + WRITE_REG(hdma2d->Instance->OCOLR, tmp); + } + else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/ + { + WRITE_REG(hdma2d->Instance->BGMAR, pdata); + } + else /* M2M, M2M_PFC,M2M_Blending or M2M_blending with fixed color BG DMA2D Mode */ + { + /* Configure DMA2D source address */ + WRITE_REG(hdma2d->Instance->FGMAR, pdata); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* DMA2D */ +#endif /* HAL_DMA2D_MODULE_ENABLED */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma_ex.c new file mode 100644 index 00000000000..cdb6725003a --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma_ex.c @@ -0,0 +1,4661 @@ +/** + ********************************************************************************************************************** + * @file stm32h7rsxx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following functionalities of the DMA extension + * peripheral: + * + Linked-List Initialization and De-Initialization Functions + * + Linked-List I/O Operation Functions + * + Linked-List Management Functions + * + Data Handling, Repeated Block and Trigger Configuration Functions + * + Suspend and Resume Operation Functions + * + FIFO Status Function + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + @verbatim + ====================================================================================================================== + ##### How to use this driver ##### + ====================================================================================================================== + [..] + Alternatively to the normal programming mode, a DMA channel can be programmed by a list of transfers, known as + linked-list (list of Node items). Each node is defined by its data structure. + Each node specifies a standalone DMA channel. + When enabled, the DMA channel fetch the first linked-list node from SRAM (known as head node). When executed, the + next linked list node will be fetched and executed. This operation is repeated until the end of the whole + linked-list queue. Optionally, the linked-list can be linear where the last linked-list queue node is not linked + to another queue node or circular where the last linked-list node is linked to any linked-list queue node. + + (+) Linear linked-list: + The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node + (tail node) ones. When the last node is completed, the DMA channel remains in idle state and another + transfer can be lunched. + + (+) Circular linked-list: + The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node (tail + node). When last node is executed, the DMA channel fetches the first circular node another time and repeat + the same sequence in an infinite loop (Circular transfer). To stop the DMA channel, an abort operation is + required. This linked-list mode replaces the legacy circular transfers. + + [..] + In order to reduce linked-list queue executing time and power consumption, the DMA channel supports executing the + dynamic linked-list format. In fact, the DMA supports the execution of 2 types of linked-list formats : static and + dynamic. + + (+) Static linked-list: + The static linked-list format refers to the full linked-list node where all DMA channel parameters are + fetched and executed independently of the redundancy of information. + + (+) Dynamic linked-list: + The dynamic linked-list format refer to the customized linked-list node where only DMA channel necessary + parameters are fetched and executed (Example: data size = 20 on previous node, and data size = 20 on the + current node => No need to update it). + + For linked-list transfers, the DMA channel can execute the linked-list queue node by node. This feature is named + link step mode. When activated, enabling the DMA channel first time allows to fetch the head node from memory + then it stops. Then, another DMA channel enable is needed to execute the node. After that, keeping enabling the + DMA channel is needed to execute each node until the end of linked-list queue. When the linked-list queue is + circular, enabling the DMA channel in an infinite loop is required to keep the DMA channel running. This feature + is useful for debug purpose or asynchronously executing queue nodes. + + [..] + Each DMA channel transfer (normal or linked-list), is highly configurable according to DMA channel instance + integrated in devices. These configuration can be : + + (+) Repeated block configuration : + If the feature is supported, the DMA channel can performs a repeated block transfers. Named also 2 + dimension addressing transfers, this feature can transfer n iteration of programmed block transfer (Block + transfer is the legacy data size). Additional to the repeat count of a block, DMA channel addresses can + jump after at burst and block level. The jump length is a programmable parameter defined by DMA user. + (++) Jump at burst level : + The DMA channel keep an empty area, between each 2 consecutive bursts transmitted. + (++) Jump at block level : + The DMA channel keep an empty area, between each 2 consecutive blocks transmitted. + + (+) Trigger : + The DMA channel transfers can be conditioned by hardware signals edges (rising or falling) named hardware + triggers. Trigger condition can be applied at : + (++) Single/Burst level : + Each single/burst data transmission is conditioned by a signal trigger hit. + (++) Block level : + Each block data transmission is conditioned by a signal trigger hit. + (++) Repeated block level : + Each repeated block data transmission is conditioned by a signal trigger hit. + (++) Node level : + Each node execution is conditioned by a signal trigger hit. + The DMA channel can report a trigger overrun when detects more than 2 trigger signal edges before + executing the current transfer. + + (+) Data handling : + The data handling feature is a FIFO capability that can be : + (++) Padding pattern : + Padding selected pattern (zero padding or sign extension) when the source data width is smaller + than the destination data width at single level. + (++) Truncation : + Truncate section from the source data single when the source data width is bigger than the + destination data width. + (++) Pack/Unpack : + Pack a set of data when source data width is smaller than the destination data width. + Unpack a set of data when source data width is bigger than the destination data width. + (++) Exchange : + Exchange data at byte, half-word and word on the destination and at byte level on the source. + + [..] + Each DMA channel transfer (normal or linked-list) when it is active, can be suspended and resumed at run time + application. When trying to suspend an ongoing transfer, the DMA channel isn't suspended instantly but complete + the current ongoing single/burst then it stops. + When the DMA channel is suspended, the current transfer can be resumed instantly. + + [..] + The DMA channel that supports FIFO, can report in real time the number of beats remains on destination (Output) + FIFO level. + + *** Linked-List Initialization and De-Initialization operation *** + ================================================================== + [..] + Differently from normal transfers, DMA channel initialization and de-initialization need less parameters as the + remaining transfer parameters are defined by linked-list nodes. + + (+) Use HAL_DMAEx_List_Init() to initialize a DMA channel in linked-list mode according to programmed fields. + When called, the DMA channel will be ready to execute linked-list queues. + + (+) Use HAL_DMAEx_List_DeInit() to de-initialize a DMA channel in linked-list mode. + When called, the DMA channel will be in reset. It is mandatory to reinitialize it for next transfer. + + *** Linked-List I/O Operation *** + ================================= + [..] + (+) Use HAL_DMAEx_List_Start() to start a DMA transfer in linked-list mode after the configuration of + linked-list queue base address and offset in polling mode (Blocking mode). + + (+) Use HAL_DMAEx_List_Start_IT() to start a DMA transfer in linked-list mode after the configuration of + linked-list queue base address and offset in interrupt mode (Non-blocking mode). + + *** Linked-List Management *** + ============================== + [..] + The linked-list management is a software processing independently of DMA channel hardware. It allows to reset, + build, create, insert, remove, replace, circularize, convert both nodes and queue in order to perform DMA + channel transfers in linked-list mode. + Linked-list APIs and types are adapted to reduce memory footprint. + + *** Linked-list nodes building *** + [..] + At node level, the operations that can be done are building a new linked-list node or get a linked-list node + information from a built node. The linked-list nodes have two forms according to 2 dimensions addressing + capability. The linear addressing nodes contains the information of all DMA channel features except the 2 + dimension addressing features and the 2 dimensions addressing nodes contain the information of all available + features. + + (+) Use HAL_DMAEx_List_BuildNode() to build the DMA linked-list node according to the specified parameters. + Build operation allow to convert the specified parameter in values known by the DMA channel and place them + in memory. + Placing DMA linked-list in SRAM must be done in accordance to product specification to ensure that the + link access port can access to the specified SRAM. + (++) The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte + addressable space. + + (+) Use HAL_DMAEx_List_GetNodeConfig() to get the specified configuration parameter on building node. + This API can be used when need to change few parameter to build new node. + + *** Inserting nodes to linked-list queue *** + [..] + In order to build a sequence of DMA transaction with different configuration, we need to insert built node at + linked-list queue (node present an elementary DMA transaction) in linked-list queue on any position to have the + full flexibility of ordering nodes or extend the sequence of queue transactions. + + (+) Use HAL_DMAEx_List_InsertNode() to insert new built node in any queue position of linked-list queue + according to selecting previous node. When calling this API with previous node parameter is NULL, the + inserted node will be placed at the head of the linked-list queue. + (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. + (++) This API must be called for static queues format. + (++) This API shall be avoided when adding new node at the head or the tail of queue (overhead of + footprint and performance : use HAL_DMAEx_List_InsertNode_Head() or HAL_DMAEx_List_InsertNode_Tail() + instead). + + (+) Use HAL_DMAEx_List_InsertNode_Head() to insert new built node at the head of linked-list queue. The head + node will not be overwritten but will be the second queue node. + (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_InsertNode_Tail() to insert new built node at the tail of linked-list queue. The tail + node will not be overwritten but will be the penultimate queue node. + (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. + (++) This API must be called for static queues format. + + *** Removing nodes from linked-list queue *** + [..] + There is some cases when removing a node from linked-list queue is needed (need to remove an elementary DMA + transaction). Removing node allows to unlink a node from DMA linked-list queue (NOT DELETED), so the removed node + can be reused for another queue or to be added to the same queue without need to rebuild it in next step. + + (+) Use HAL_DMAEx_List_RemoveNode() to remove any yet built and inserted node from linked-list queue according + to selected node. + (++) This API must be called for static queues format. + (++) This API shall be avoided when removing the head or the tail of linked-list queue (overhead of + footprint and performance : use HAL_DMAEx_List_RemoveNode_Head() or HAL_DMAEx_List_RemoveNode_Tail() + instead). + + (+) Use HAL_DMAEx_List_RemoveNode_Head() to remove the head node from linked-list queue. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_RemoveNode_Tail() to remove the tail node from linked-list queue. + (++) This API must be called for static queues format. + + *** Replacing nodes on linked-list queue *** + [..] + There is some cases when replacing a node from linked-list queue is needed (need to replace an elementary DMA + transfer, by another one that have not the same configuration). Replacing node allows to unlink the node to be + replaced from DMA linked-list queue (NOT DELETED) and link instead a new node. So the replaced node can be reused + for another queue or to be added to the same queue without need to rebuild it in next step and the new node cannot + be reused except when remove it or replaced in next step. + + (+) Use HAL_DMAEx_List_ReplaceNode() to replace any yet built and inserted node on linked-list queue according + to selected node. + (++) This API must be called for static queues format. + (++) This API shall be avoided when replacing the head or the tail linked-list queue (overhead of + footprint and performance : use HAL_DMAEx_List_ReplaceNode_Head() or + HAL_DMAEx_List_ReplaceNode_Tail() instead). + + (+) Use HAL_DMAEx_List_ReplaceNode_Head() to replace the head node of linked-list queue. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_ReplaceNode_Tail() to replace the tail node from linked-list queue. + (++) This API must be called for static queues format. + + *** Reset linked-list queue *** + [..] + After finishing using a linked-list queue, it can be reset and cleared and it's content nodes will be + unlinked (NOT DELETED) and reused on another queue. + + (+) Use HAL_DMAEx_List_ResetQ() to reset a linked-list queue and unlink all it's content nodes. + (++) This API must be called for ready state queues. + (++) This API must be called for static queues format. + + *** Inserting linked-list queue *** + [..] + To ensure the flexibility of building linked-list queue by their targeted functionalities (Example: 3 nodes for + action 1 and 5 nodes for action 2), it is possible to build a queue for action 1 that contains action 1 nodes and + a queue for action 2 that contains action 2 nodes then concatenating the 2 queues. So, there are some cases where + the management of linked-list at queue granularity is needed. + + (+) Use HAL_DMAEx_List_InsertQ() to insert source linked-list queue to a destination linked-list queue + according to selecting previous node. + (++) This API must be called for static queues format. + (++) This API shall be avoided when inserting source linked-list queue at the head or the tail of + destination queue (overhead of footprint and performance : use HAL_DMAEx_List_InsertQ_Head() or + HAL_DMAEx_List_InsertQ_Tail() instead). + + (+) Use HAL_DMAEx_List_InsertQ_Head() to insert a source linked-list queue at the head of linked-list + destination queue. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_InsertQ_Tail() to insert a source linked-list queue at the tail of linked-list + destination queue. + (++) This API must be called for static queues format. + + *** Circularizing linked-list queue *** + [..] + In order to perform tasks in infinite loop with DMA channel, it is possible to circularize the linked-list queues. + Circularizing queue allows to link last linked-list queue node to any previous node of the same queue (This node + is named first circular queue). When the first circular node is the head node, all linked-list queue nodes will be + executed in infinite loop. When the first circular node is not the head nodes, all precedent nodes are executed + once and all remaining nodes are executed in an infinite loop. + + (+) Use HAL_DMAEx_List_SetCircularModeConfig() to circularize the linked-list queue according to first + circular node selected. + (++) This API must be called for static queues format. + (++) This API shall be avoided when first circular node is the head linked-list queue node (overhead of + footprint and performance : use HAL_DMAEx_List_SetCircularMode() instead). + + (+) Use HAL_DMAEx_List_SetCircularMode() to circularize the linked-list queue with linking last queue node + with first queue node. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_ClearCircularMode() to clear any linked-list queue circular configuration. + (++) This API must be called for static queues format. + + + *** Converting linked-list queue *** + [..] + To have the best DMA channel linked-list queue execution, it is recommended to convert yet build linked-list queue + to dynamic format (Static is the default format). When linked-list queue becomes dynamic, all queue nodes are + optimized and only changed parameters will be updated between nodes. So, the DMA will fetch only changes + parameters instead of the whole node. + + (+) Use HAL_DMAEx_List_ConvertQToDynamic() to convert a linked-list queue to dynamic format. + (++) This API must be called for ready state queues. + (++) This API must be called for static queues format. + (++) This API must be called as the last API before starting the DMA channel in linked-list mode. + + (+) Use HAL_DMAEx_List_ConvertQToStatic() to convert a linked-list queue to static format. + (++) This API must be called for ready state queues. + (++) This API must be called for dynamic queues format. + (++) This API must be called as the first API after the full execution of linked-list queue when the + execution mode is linear (not circular) if it is dynamic and a linked-list queue management is + needed. + (++) This API must be called as the first API after the aborting the execution of the current linked-list + queue when the execution mode is linear (not circular) if it is dynamic and a linked-list queue + management is needed. + + [..] + When converting a circular queue to dynamic format and when the first circular node is the last queue node, it is + recommended to duplicate the last circular node in order to ensure the full optimization when calling + HAL_DMAEx_List_ConvertQToDynamic() API. In this case, updated information are only addresses which allow to reduce + 4 words of update for linear nodes per node execution and 6 words update for 2 dimensions addressing nodes per + node execution. + + + *** Linking linked-list queue to DMA channel *** + [..] + In order to have the possibility of the creation of an infinity queues (limited by available memory size), the + building of linked-list queue is fully independent from DMA channels. It is possible to build all needed queues if + their size is less then available memory at startup time, then linking each time when needed a linked-list queue + to an idle DMA channel. + + (+) Use HAL_DMAEx_List_LinkQ() to link a ready linked-list queue to ready DMA channel. + (++) This API supports the two format of linked-list (Static and dynamic). + (++) This API must be called for ready state queues and DMA channels. + + (+) Use HAL_DMAEx_List_ConvertQToStatic() to unlink a ready linked-list queue to ready DMA channel. + (++) This API supports the two format of linked-list (Static and dynamic). + (++) This API must be called for ready state queues and DMA channels. + + *** User sequence *** + [..] + To use cleanly the DMA linked-list library, ensure to apply the following call sequences : + + (+) Linear transfer : + Linked-list queue building + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + . + . + . + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + (++) HAL_DMAEx_List_ConvertQToDynamic() + Linked-list queue execution + (++) HAL_DMAEx_List_Init() + (++) HAL_DMAEx_List_LinkQ() + (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT() + (++) HAL_DMAEx_List_UnLinkQ() + (++) HAL_DMAEx_List_DeInit() + + (+) Circular transfer : + Linked-list queue building + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + . + . + . + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + (++) HAL_DMAEx_List_SetCircularModeConfig() / HAL_DMAEx_List_SetCircularMode() + (++) HAL_DMAEx_List_ConvertQToDynamic() + Linked-list queue execution + (++) HAL_DMAEx_List_Init() + (++) HAL_DMAEx_List_LinkQ() + (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT() + (++) HAL_DMA_Abort() / HAL_DMA_Abort_IT() + (++) HAL_DMAEx_List_UnLinkQ() + (++) HAL_DMAEx_List_DeInit() + + + *** Data Handling *** + ===================== + [..] + In order to avoid some CPU data processing in several cases, the DMA channel provides some features related to + FIFO capabilities titled data handling. + (++) Padding pattern + Padding selected pattern (zero padding or sign extension) when the source data width is smaller + than the destination data width at single level. + Zero padding (Source : 0xABAB ------> Destination : 0xABAB0000) + Sign bit extension (Source : 0x0ABA ------> Destination : 0x00000ABA) + (Source : 0xFABA ------> Destination : 0xFFFFFABA) + (++) Truncation : + Truncate section from the source data single when the source data width is bigger than the + destination data width. + Left truncation (Source : 0xABABCDCD ------> Destination : 0xCDCD) + Right truncation (Source : 0xABABCDCD ------> Destination : 0xABAB) + (++) Pack/Unpack : + Pack a set of data when source data width is smaller than the destination data width. + Unpack a set of data when source data width is bigger than the destination data width. + Pack (Source : 0xAB, 0xCD ------> Destination : 0xABCD) + UnPack (Source : 0xABCD ------> Destination : 0xAB, 0xCD) + (++) Exchange : + Exchange data at byte and half-word on the destination and at byte level on the source. + Considering source and destination are both word type. Exchange operation can be as follows. + In examples below, one exchange setting is enabled at a time. + Source byte exchange only (Source : 0xAB12CD34 ------> Destination : 0xABCD1234) + Destination byte exchange only (Source : 0xAB12CD34 ------> Destination : 0x12AB34CD) + Destination half-word exchange only (Source : 0xAB12CD34 ------> Destination : 0xCD34AB12) + In addition, in case of double-word, Exchange data at word level on the destination is also + available. + Considering source and destination are both double-word type. + word exchange only (Source : 0xAB12CD34EF567890 ------> Destination : 0xEF567890AB12CD34) + + (+) Use HAL_DMAEx_ConfigDataHandling() to configure data handling features. Previous elementary explained + can be combined according to application needs. + (++) This API is complementary of normal transfers. + (++) This API must not be called for linked-list transfers as data handling information are configured at + node level. + + *** User sequence *** + [..] + To configure cleanly the DMA channel data handling, ensure to apply the following call sequence : + + (+) Linear transfer : + (++) HAL_DMA_Init() + (++) HAL_DMAEx_ConfigDataHandling() + (++) HAL_DMA_Start() + + *** Repeated Block *** + ====================== + [..] + When available, this feature is used when the data size is higher then 65535 bytes (Maximum block size) or for + scattering / gathering data. + (++) Gather data + Source Destination + 0xAA 0xAA + 0xBB 0xAA + 0xAA ==> 0xAA + 0xCC + 0xAA + (++) Scatter data + Source Destination + 0xAA 0xAA + 0xAA 0xBB + 0xAA ==> 0xAA + 0xBB + 0xAA + + (+) Use HAL_DMAEx_ConfigRepeatBlock() to configure data repeated block feature. Jump addresses and + incrementing or decrementing on source and destination can be combined to have the need application + behavior. + (++) This API is complementary of normal transfers. + (++) This API must not be called for linked-list transfers as repeated block information are configured at + node level. + (++) This API must be called only for DMA channel that supports repeated block feature. + + *** User sequence *** + [..] + To configure cleanly the DMA channel repeated block, ensure to apply the following call sequence : + + (+) Linear transfer : + (++) HAL_DMA_Init() + (++) HAL_DMAEx_ConfigRepeatBlock() + (++) HAL_DMA_Start() + + *** Trigger Configuration *** + ============================= + [..] + When application needs that DMA transfers are conditioned by internal or external events, the trigger feature can + do that. Trigger signals are a set of device signal that are linked to DMA trigger inputs that allows to start the + DMA transfers. + To setup a trigger transfers, three DMA channel parameters are needed: + + (+) Trigger mode + This parameter specifies the trig level. + (++) Block level + (++) Repeated block level + (++) Node level + (++) Single / Burst level + + (+) Trigger polarity + This parameter specifies the DMA trigger sensitivity (Rising or falling). + + (+) Trigger selection + This parameter specifies the DMA trigger hardware signal. + + (+) Use HAL_DMAEx_ConfigTrigger() to configure trigger feature. + (++) This API is complementary to normal transfers APIs. + (++) This API must not be called for linked-list transfers as trigger information are configured at + node level. + + *** User sequence *** + [..] + To configure cleanly the DMA channel trigger, ensure to apply the following call sequence : + (+) Linear transfer : + (++) HAL_DMA_Init() + (++) HAL_DMAEx_ConfigTrigger() + (++) HAL_DMA_Start() + + *** Suspend and resume operation *** + ==================================== + [..] + There are several cases when needs to suspend a DMA current transfer (Example: liberate bandwidth for more + priority DMA channel transfer). Suspending DMA channel (same as abort) is available in polling (blocking mode) and + interrupt (non-blocking mode) modes. When suspended, a DMA channel can be instantly resumed. + + (+) Use HAL_DMAEx_Suspend() to suspend an ongoing DMA channel transfer in polling mode (Blocking mode). + + (+) Use HAL_DMAEx_Suspend_IT() to suspend an ongoing DMA channel transfer in interrupt mode (Non-blocking + mode). + + (+) Use HAL_DMAEx_Resume() to resume a suspended DMA channel transfer execution. + + *** FIFO status *** + =================== + [..] + In several cases, the information of FIFO level is useful to inform at application level how to process remaining + data. When not empty, the DMA channel FIFO cannot be flashed only by reset. + + (+) Use HAL_DMAEx_GetFifoLevel() to get the DMA channel FIFO level (available beats in FIFO). + + @endverbatim + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private Constants -------------------------------------------------------------------------------------------------*/ +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +static void DMA_List_Init(DMA_HandleTypeDef const *const hdma); +static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode); +static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode); +static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3); +static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3); +static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, + uint32_t *const cllr_mask, + uint32_t *const cllr_offset); +static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList, + DMA_NodeTypeDef const *const pNode, + DMA_NodeInQInfoTypeDef *const NodeInfo); +static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList, + DMA_NodeInQInfoTypeDef const *const NodeInfo); +static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode, + DMA_NodeTypeDef *const pDestNode); +static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber); +static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber); +static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t LastNode_IsCircular); +static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t operation); +static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode, + uint32_t RegisterIdx, + uint32_t RegisterNumber, + uint32_t Format); +static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode, + uint32_t FirstUnusedField); +static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList); + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + +/** @addtogroup DMAEx_Exported_Functions_Group1 + * +@verbatim + ====================================================================================================================== + ##### Linked-List Initialization and De-Initialization Functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the DMA channel in linked-list mode. + [..] + (+) The HAL_DMAEx_List_Init() function follows the DMA channel linked-list mode configuration procedures as + described in reference manual. + (+) The HAL_DMAEx_List_DeInit() function allows to de-initialize the DMA channel in linked-list mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA channel in linked-list mode according to the specified parameters in the + * DMA_InitLinkedListTypeDef and create the associated handle. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA channel handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_PRIORITY(hdma->InitLinkedList.Priority)); + assert_param(IS_DMA_LINK_STEP_MODE(hdma->InitLinkedList.LinkStepMode)); + assert_param(IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(hdma->InitLinkedList.TransferEventMode)); + assert_param(IS_DMA_LINKEDLIST_MODE(hdma->InitLinkedList.LinkedListMode)); + /* Check DMA channel instance */ + if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)) + { + assert_param(IS_DMA_LINK_ALLOCATED_PORT(hdma->InitLinkedList.LinkAllocatedPort)); + } + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Initialize the DMA channel registers */ + DMA_List_Init(hdma); + + /* Update DMA channel operation mode */ + hdma->Mode = hdma->InitLinkedList.LinkedListMode; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA channel when it is configured in linked-list mode. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset DMA Channel registers */ + hdma->Instance->CCR = 0U; + hdma->Instance->CLBAR = 0U; + hdma->Instance->CTR1 = 0U; + hdma->Instance->CTR2 = 0U; + hdma->Instance->CBR1 = 0U; + hdma->Instance->CSAR = 0U; + hdma->Instance->CDAR = 0U; + hdma->Instance->CLLR = 0U; + + /* Reset 2D Addressing registers */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + hdma->Instance->CTR3 = 0U; + hdma->Instance->CBR2 = 0U; + } + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO)); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + + /* Check the linked-list queue */ + if (hdma->LinkedListQueue != NULL) + { + /* Update the queue state and error code */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Clean DMA queue */ + hdma->LinkedListQueue = NULL; + } + + /* Clean DMA parent */ + if (hdma->Parent != NULL) + { + hdma->Parent = NULL; + } + + /* Update DMA channel operation mode */ + hdma->Mode = DMA_NORMAL; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group2 + * +@verbatim + ====================================================================================================================== + ##### Linked-List IO Operation Functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure to start DMA transfer in linked-list mode. + + [..] + (+) The HAL_DMAEx_List_Start() function allows to start the DMA channel transfer in linked-list mode (Blocking + mode). + (+) The HAL_DMAEx_List_Start_IT() function allows to start the DMA channel transfer in linked-list mode + (Non-blocking mode). + (++) It is mandatory to register a linked-list queue to be executed by a DMA channel before starting + transfer otherwise a HAL_ERROR will be returned. + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA channel transfer in linked-list mode (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma) +{ + HAL_DMA_StateTypeDef dma_state; + uint32_t ccr_value; + uint32_t cllr_mask; + + /* Check the DMA peripheral handle and the linked-list queue parameters */ + if ((hdma == NULL) || (hdma->LinkedListQueue == NULL)) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + dma_state = hdma->State; + ccr_value = hdma->Instance->CCR & DMA_CCR_LSM; + if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U))) + { + /* Check DMA channel state is ready */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Process locked */ + __HAL_LOCK(hdma); + + /* Update the DMA channel and the queue states */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the DMA channel and the queue error codes */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL); + + /* Update DMA registers for linked-list transfer */ + hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA); + hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; + } + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Starts the DMA channel transfer in linked-list mode with interrupts enabled (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma) +{ + HAL_DMA_StateTypeDef dma_state; + uint32_t ccr_value; + uint32_t cllr_mask; + + /* Check the DMA peripheral handle and the linked-list queue parameters */ + if ((hdma == NULL) || (hdma->LinkedListQueue == NULL)) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + dma_state = hdma->State; + ccr_value = hdma->Instance->CCR & DMA_CCR_LSM; + if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U))) + { + /* Check DMA channel state is ready */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Process locked */ + __HAL_LOCK(hdma); + + /* Update the DMA channel and the queue states */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the DMA channel and the queue error codes */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO)); + + /* Check half transfer complete callback */ + if (hdma->XferHalfCpltCallback != NULL) + { + /* If half transfer complete callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + } + + /* Check suspend callback */ + if (hdma->XferSuspendCallback != NULL) + { + /* If transfer suspend callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP); + } + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL); + + /* Update DMA registers for linked-list transfer */ + hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA); + hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; + } + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Change the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group3 + * +@verbatim + ====================================================================================================================== + ##### Linked-List Management Functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Build linked-list node. + (+) Get linked-list node configuration. + (+) Insert node to linked-list queue in any queue position. + (+) Remove any node from linked-list queue. + (+) Replace any node from linked-list queue. + (+) Reset linked-list queue. + (+) Insert linked-list queue in any queue position. + (+) Set circular mode configuration to linked-list queue. + (+) Clear circular mode configuration from linked-list queue. + (+) Convert static linked-list queue to dynamic format. + (+) Convert dynamic linked-list queue to static format. + (+) Link linked-list queue to DMA channel. + (+) Unlink linked-list queue from DMA channel. + + [..] + (+) The HAL_DMAEx_List_BuildNode() function allows to build linked-list node. + Node type can be : + (++) 2 dimensions addressing node. + (++) Linear addressing node. + + (+) The HAL_DMAEx_List_GetNodeConfig() function allows to get the linked-list node configuration from built node. + + (+) The HAL_DMAEx_List_InsertNode() function allows to insert built linked-list node to static linked-list queue + according to selected position. + + (+) The HAL_DMAEx_List_InsertNode_Head() and HAL_DMAEx_List_InsertNode_Tail() functions allow to insert built + linked-list node to the head (respectively the tail) of static linked-list queue. + + (+) The HAL_DMAEx_List_RemoveNode() function allows to remove selected built linked-list node from static + linked-list queue. + + (+) The HAL_DMAEx_List_RemoveNode_Head() and HAL_DMAEx_List_RemoveNode_Tail() functions allow to remove the head + (respectively the tail) built linked-list node from static linked-list queue. + + (+) The HAL_DMAEx_List_ReplaceNode() function allows to replace selected built linked-list node from static + linked-list queue. + + (+) The HAL_DMAEx_List_ReplaceNode_Head() and HAL_DMAEx_List_ReplaceNode_Tail() functions allow to replace the + head (respectively the tail) built linked-list node of static linked-list queue. + + (+) The HAL_DMAEx_List_ResetQ() function allows to reset static linked-list queue and unlink all built linked-list + nodes. + + (+) The HAL_DMAEx_List_InsertQ() function allows to insert static linked-list source queue to static linked-list + destination queue according to selected position. + + (+) The HAL_DMAEx_List_InsertQ_Head() and HAL_DMAEx_List_InsertQ_Tail() functions allow to insert static + linked-list source queue to the head (respectively the tail) of static linked-list destination queue. + + (+) The HAL_DMAEx_List_SetCircularModeConfig() function allows to link the last static linked-list queue node to + the selected first circular node. + + (+) The HAL_DMAEx_List_SetCircularMode() function allows to link the last static linked-list queue node to the + first static linked-list queue node. + + (+) The HAL_DMAEx_List_ClearCircularMode() function allows to unlink the last static linked-list queue node from + any first circular node position. + + (+) The HAL_DMAEx_List_ConvertQToDynamic() function allows to convert the static linked-list queue to dynamic + format. (Optimized queue execution) + + (+) The HAL_DMAEx_List_ConvertQToStatic() function allows to convert the dynamic linked-list queue to static + format. (Not optimized queue execution) + + (+) The HAL_DMAEx_List_LinkQ() function allows to link the (Dynamic / Static) linked-list queue to DMA channel to + be executed. + + (+) The HAL_DMAEx_List_UnLinkQ() function allows to unlink the (Dynamic / Static) linked-list queue from DMA + channel when execution is completed. + +@endverbatim + * @{ + */ + +/** + * @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @note The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte + * addressable space. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode) +{ + /* Check the node configuration and physical node parameters */ + if ((pNodeConfig == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Check node type parameter */ + assert_param(IS_DMA_NODE_TYPE(pNodeConfig->NodeType)); + + /* Check DMA channel basic transfer parameters */ + assert_param(IS_DMA_SOURCE_INC(pNodeConfig->Init.SrcInc)); + assert_param(IS_DMA_DESTINATION_INC(pNodeConfig->Init.DestInc)); + assert_param(IS_DMA_SOURCE_DATA_WIDTH(pNodeConfig->Init.SrcDataWidth)); + assert_param(IS_DMA_DESTINATION_DATA_WIDTH(pNodeConfig->Init.DestDataWidth)); + assert_param(IS_DMA_DATA_ALIGNMENT(pNodeConfig->DataHandlingConfig.DataAlignment)); + assert_param(IS_DMA_REQUEST(pNodeConfig->Init.Request)); + assert_param(IS_DMA_DIRECTION(pNodeConfig->Init.Direction)); + assert_param(IS_DMA_TCEM_EVENT_MODE(pNodeConfig->Init.TransferEventMode)); + assert_param(IS_DMA_BLOCK_HW_REQUEST(pNodeConfig->Init.BlkHWRequest)); + assert_param(IS_DMA_MODE(pNodeConfig->Init.Mode)); + + /* Check DMA channel parameters */ + if ((pNodeConfig->NodeType & (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_HPDMA)) != 0U) + { + assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.SrcBurstLength)); + assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.DestBurstLength)); + assert_param(IS_DMA_DATA_EXCHANGE(pNodeConfig->DataHandlingConfig.DataExchange)); + assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(pNodeConfig->Init.TransferAllocatedPort)); + } + + /* Check DMA channel trigger parameters */ + assert_param(IS_DMA_TRIGGER_POLARITY(pNodeConfig->TriggerConfig.TriggerPolarity)); + if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED) + { + assert_param(IS_DMA_TRIGGER_MODE(pNodeConfig->TriggerConfig.TriggerMode)); + assert_param(IS_DMA_TRIGGER_SELECTION(pNodeConfig->TriggerConfig.TriggerSelection)); + } + + /* Check DMA channel repeated block parameters */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + assert_param(IS_DMA_REPEAT_COUNT(pNodeConfig->RepeatBlockConfig.RepeatCount)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); + } + + /* Build the DMA channel node */ + DMA_List_BuildNode(pNodeConfig, pNode); + + return HAL_OK; +} + +/** + * @brief Get a DMA channel node configuration. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode) +{ + /* Check the node configuration and physical node parameters */ + if ((pNodeConfig == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Get the DMA channel node configuration */ + DMA_List_GetNodeConfig(pNodeConfig, pNode); + + return HAL_OK; +} + +/** + * @brief Insert new node in any queue position of linked-list queue according to selecting previous node. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers + * configurations. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pPrevNode, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Empty queue */ + if (pQList->Head == NULL) + { + /* Add only new node to queue */ + if (pPrevNode == NULL) + { + pQList->Head = pNewNode; + pQList->NodeNumber = 1U; + } + /* Add previous node then new node to queue */ + else + { + pQList->Head = pPrevNode; + pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + pQList->NodeNumber = 2U; + } + } + /* Not empty queue */ + else + { + /* Add new node at the head of queue */ + if (pPrevNode == NULL) + { + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + pQList->Head = pNewNode; + } + /* Add new node according to selected position */ + else + { + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pPrevNode, &node_info) == 0U) + { + /* Selected node is the last queue node */ + if (node_info.currentnode_pos == pQList->NodeNumber) + { + /* Check if queue is circular */ + if (pQList->FirstCircularNode != NULL) + { + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + + pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + } + /* Selected node is not the last queue node */ + else + { + pNewNode->LinkRegisters[cllr_offset] = pPrevNode->LinkRegisters[cllr_offset]; + pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + } + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + } + + /* Increment queue node number */ + pQList->NodeNumber++; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Insert new node at the head of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Empty queue */ + if (pQList->Head == NULL) + { + pQList->Head = pNewNode; + } + /* Not empty queue */ + else + { + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + pQList->Head = pNewNode; + } + + /* Increment queue node number */ + pQList->NodeNumber++; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Insert new node at the tail of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Empty queue */ + if (pQList->Head == NULL) + { + pQList->Head = pNewNode; + } + /* Not empty queue */ + else + { + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Check if queue is circular */ + if (pQList->FirstCircularNode != NULL) + { + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + + ((DMA_NodeTypeDef *)node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + } + + /* Increment queue node number */ + pQList->NodeNumber++; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Remove node from any linked-list queue position. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNode) +{ + uint32_t previousnode_addr; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the node parameters */ + if ((pQList == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNode, NULL, &cllr_offset); + + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pNode, &node_info) == 0U) + { + /* Removed node is the head node */ + if (node_info.currentnode_pos == 1U) + { + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) + { + /* Find last queue node */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + /* Update the queue head node */ + pQList->Head = (DMA_NodeTypeDef *)(((uint32_t)pQList->Head & DMA_CLBAR_LBA) + + (pNode->LinkRegisters[cllr_offset] & DMA_CLLR_LA)); + /* Unlink node to be removed */ + pNode->LinkRegisters[cllr_offset] = 0U; + } + /* Removed node is the last node */ + else if (node_info.currentnode_pos == pQList->NodeNumber) + { + /* Clear CLLR for previous node */ + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear CLLR for last node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + /* Removed node is in the middle */ + else + { + /* Store previous node address to be updated later */ + previousnode_addr = node_info.previousnode_addr; + + /* Check if first circular node queue is the current node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) + { + /* Find last queue node */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + /* Link previous node */ + ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[cllr_offset] = pNode->LinkRegisters[cllr_offset]; + + /* Unlink node to be removed */ + pNode->LinkRegisters[cllr_offset] = 0U; + } + + /* Decrement node number */ + pQList->NodeNumber--; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + + /* Check if queue is empty */ + if (pQList->NodeNumber == 0U) + { + /* Clean empty queue parameter */ + DMA_List_CleanQueue(pQList); + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Remove the head node from linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + uint32_t current_addr; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Queue contains only one node */ + if (pQList->NodeNumber == 1U) + { + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->FirstCircularNode = 0U; + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + } + /* Queue contains more then one node */ + else + { + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == pQList->Head) + { + /* Find last queue node */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + current_addr = pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->Head = ((DMA_NodeTypeDef *)(current_addr + ((uint32_t)pQList->Head & DMA_CLBAR_LBA))); + } + + /* Decrement node number */ + pQList->NodeNumber--; + + /* Check if queue is empty */ + if (pQList->NodeNumber == 0U) + { + /* Clean empty queue parameter */ + DMA_List_CleanQueue(pQList); + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Remove the tail node from linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Queue contains only one node */ + if (pQList->NodeNumber == 1U) + { + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->FirstCircularNode = 0U; + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + } + /* Queue contains more then one node */ + else + { + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear CLLR for previous node */ + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear CLLR for last node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + /* Decrement node number */ + pQList->NodeNumber--; + + /* Check if queue is empty */ + if (pQList->NodeNumber == 0U) + { + /* Clean empty queue parameter */ + DMA_List_CleanQueue(pQList); + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Replace node in linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pOldNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list old node registers + * configurations. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pOldNode, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the nodes parameters */ + if ((pQList == NULL) || (pOldNode == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pOldNode, &node_info) == 0U) + { + /* Replaced node is the head node */ + if (node_info.currentnode_pos == 1U) + { + pNewNode->LinkRegisters[cllr_offset] = + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset]; + pQList->Head = pNewNode; + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) + { + /* Find last queue node */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + } + /* Replaced node is the last */ + else if (node_info.currentnode_pos == pQList->NodeNumber) + { + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the last node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + /* Check if first circular node queue is not the last node */ + else if (pQList->FirstCircularNode != NULL) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + } + /* Replaced node is in the middle */ + else + { + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + pNewNode->LinkRegisters[cllr_offset] = + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset]; + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the current node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) + { + /* Find last node and get its position in selected queue */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Link last queue node to new node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + } + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Replace the head node of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_offset; + uint32_t cllr_mask; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == pQList->Head) + { + /* Find last queue node */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + + /* Replace head node */ + pNewNode->LinkRegisters[cllr_offset] = pQList->Head->LinkRegisters[cllr_offset]; + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->Head = pNewNode; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Replace the tail node of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Find last node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Link previous node to new node */ + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Clear CLLR for current node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the last node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + /* Check if first circular node queue is not the last node */ + else if (pQList->FirstCircularNode != NULL) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check if queue contains one node */ + if (pQList->NodeNumber == 1U) + { + pQList->Head = pNewNode; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Reset the linked-list queue and unlink queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check queue state */ + if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Check the queue */ + if (pQList->Head != NULL) + { + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Reset selected queue nodes */ + node_info.cllr_offset = cllr_offset; + DMA_List_ResetQueueNodes(pQList, &node_info); + } + + /* Reset head node address */ + pQList->Head = NULL; + + /* Reset node number */ + pQList->NodeNumber = 0U; + + /* Reset first circular node */ + pQList->FirstCircularNode = NULL; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Insert a source linked-list queue to a destination linked-list queue according to selecting previous node. + * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. + * @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers + * configurations. + * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, + DMA_NodeTypeDef const *const pPrevNode, + DMA_QListTypeDef *const pDestQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef src_q_node_info; + DMA_NodeInQInfoTypeDef dest_q_node_info; + + /* Check the source and destination queues and the previous node parameters */ + if ((pSrcQList == NULL) || (pDestQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the source queue */ + if (pSrcQList->Head == NULL) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check the source queue type */ + if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the destination queue type */ + if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the source queue circularity */ + if (pSrcQList->FirstCircularNode != NULL) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the source queue state */ + pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); + + /* Empty destination queue */ + if (pDestQList->Head == NULL) + { + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber = pSrcQList->NodeNumber; + } + /* Not empty destination queue */ + else + { + /* Previous node is empty */ + if (pPrevNode == NULL) + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Check if first circular node queue is the first node */ + if (pDestQList->FirstCircularNode == pDestQList->Head) + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); + + /* Link destination queue tail node to new first circular node */ + ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Set the head node of source queue as the first circular node */ + pDestQList->FirstCircularNode = pSrcQList->Head; + } + + /* Link the last node of source queue to the fist node of destination queue */ + ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + } + /* Previous node is not empty */ + else + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pDestQList, pPrevNode, &dest_q_node_info) == 0U) + { + /* Selected node is the last destination queue node */ + if (dest_q_node_info.currentnode_pos == pDestQList->NodeNumber) + { + /* Link the first node of source queue to the last node of destination queue */ + ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + + /* Check if first circular node queue is not empty */ + if (pDestQList->FirstCircularNode != NULL) + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Find first circular node */ + (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info); + + /* Link last source queue node to first destination queue */ + ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask; + } + } + /* Selected node is not the last destination queue node */ + else + { + /* Link the first node of source queue to the previous node of destination queue */ + ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Link the last node of source queue to the next node of destination queue */ + ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + (dest_q_node_info.nextnode_addr & DMA_CLLR_LA) | cllr_mask; + + /* Update queues counter */ + pDestQList->NodeNumber += pSrcQList->NodeNumber; + } + } + else + { + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + } + } + + /* Clean the source queue variable as it is obsolete */ + DMA_List_CleanQueue(pSrcQList); + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(src_q_node_info); + UNUSED(dest_q_node_info); + + return HAL_OK; +} + +/** + * @brief Insert a source linked-list queue at the head of destination queue. + * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. + * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef src_q_node_info; + DMA_NodeInQInfoTypeDef dest_q_node_info; + + /* Check the source and destination queues and the previous node parameters */ + if ((pSrcQList == NULL) || (pDestQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the source queue */ + if (pSrcQList->Head == NULL) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check the source queue type */ + if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the destination queue type */ + if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the source queue state */ + pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); + + /* Empty destination queue */ + if (pDestQList->Head == NULL) + { + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber = pSrcQList->NodeNumber; + } + /* Not empty destination queue */ + else + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Check if first circular node queue is the first node */ + if (pDestQList->FirstCircularNode == pDestQList->Head) + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); + + /* Link destination queue tail node to new first circular node */ + ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Set the head node of source queue as the first circular node */ + pDestQList->FirstCircularNode = pSrcQList->Head; + } + + /* Link the last node of source queue to the fist node of destination queue */ + ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + } + + /* Clean the source queue variable as it is obsolete */ + DMA_List_CleanQueue(pSrcQList); + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(src_q_node_info); + UNUSED(dest_q_node_info); + + return HAL_OK; +} + +/** + * @brief Insert a source linked-list queue at the tail of destination queue. + * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. + * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef src_q_node_info; + DMA_NodeInQInfoTypeDef dest_q_node_info; + + /* Check the source and destination queues and the previous node parameters */ + if ((pSrcQList == NULL) || (pDestQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the source queue */ + if (pSrcQList->Head == NULL) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check the source queue type */ + if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the destination queue type */ + if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the source queue state */ + pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); + + /* Empty destination queue */ + if (pDestQList->Head == NULL) + { + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber = pSrcQList->NodeNumber; + } + /* Not empty destination queue */ + else + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); + + /* Update source queue last node CLLR to link it with destination first node */ + ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + + /* Check if first circular node queue is not empty */ + if (pDestQList->FirstCircularNode != NULL) + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Find first circular node */ + (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info); + + /* Link last source queue node to first destination queue */ + ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask; + } + } + + /* Clean the source queue variable as it is obsolete */ + DMA_List_CleanQueue(pSrcQList); + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(src_q_node_info); + + return HAL_OK; +} + +/** + * @brief Set circular mode configuration for linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pFirstCircularNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list first circular node + * registers configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pFirstCircularNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the first circular node parameters */ + if ((pQList == NULL) || (pFirstCircularNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue circular mode */ + if (pQList->FirstCircularNode != NULL) + { + if (pQList->FirstCircularNode == pFirstCircularNode) + { + return HAL_OK; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pFirstCircularNode, &cllr_mask, &cllr_offset); + + /* Find the first circular node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pFirstCircularNode, &node_info) == 0U) + { + /* Find the last queue node and get its position in selected queue */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Set circular mode */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pFirstCircularNode & DMA_CLLR_LA) | cllr_mask; + + /* Update first circular node in queue */ + pQList->FirstCircularNode = pFirstCircularNode; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Set circular mode for linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue circular mode */ + if (pQList->FirstCircularNode != NULL) + { + if (pQList->FirstCircularNode == pQList->Head) + { + return HAL_OK; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_mask, &cllr_offset); + + /* Find the last queue node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Set circular mode */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Update linked-list circular state */ + pQList->FirstCircularNode = pQList->Head; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Clear circular mode for linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue circular mode */ + if (pQList->FirstCircularNode == NULL) + { + return HAL_OK; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Find the last queue node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear circular mode */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Update linked-list circular configuration */ + pQList->FirstCircularNode = NULL; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Convert a linked-list queue to dynamic (Optimized DMA queue execution). + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + uint32_t currentnode_addr; + DMA_NodeTypeDef context_node; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check if queue is dynamic */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + return HAL_OK; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Check queue circularity */ + if (pQList->FirstCircularNode != 0U) + { + /* Find the last queue node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + } + + /* Set current node address */ + currentnode_addr = (uint32_t)pQList->Head; + + /* Store register value */ + DMA_List_FillNode(pQList->Head, &context_node); + + /* Convert all nodes to dyncamic (Bypass head node) */ + for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++) + { + /* Update node address */ + MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA)); + + /* Bypass the first circular node when first circular node isn't the last queue node */ + if (((uint32_t)pQList->FirstCircularNode != 0U) && + ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr) && + ((uint32_t)pQList->FirstCircularNode == currentnode_addr)) + { + /* Copy first circular node to context node */ + DMA_List_FillNode(pQList->FirstCircularNode, &context_node); + } + else + { + /* Convert current node to dynamic */ + DMA_List_ConvertNodeToDynamic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U)); + } + } + + /* Check if first circular node is the last node queue */ + if (((uint32_t)pQList->FirstCircularNode != 0U) && + ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr)) + { + /* Update all queue nodes CLLR */ + DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_ISNOT_CIRCULAR); + } + else + { + /* Update all queue nodes CLLR */ + DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_IS_CIRCULAR); + } + + /* Set queue type */ + pQList->Type = QUEUE_TYPE_DYNAMIC; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Convert a linked-list queue to static (Not optimized DMA queue execution). + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + uint32_t currentnode_addr; + DMA_NodeTypeDef context_node; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check if queue is static */ + if (pQList->Type == QUEUE_TYPE_STATIC) + { + return HAL_OK; + } + + /* Set current node address */ + currentnode_addr = (uint32_t)pQList->Head; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Set all CLLR queue nodes to their default positions */ + DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_POSITION); + + /* Convert all nodes to static (Bypass head node) */ + for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++) + { + /* Update context node register values */ + DMA_List_FillNode((DMA_NodeTypeDef *)currentnode_addr, &context_node); + + /* Update node address */ + MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA)); + + /* Convert current node to static */ + DMA_List_ConvertNodeToStatic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U)); + } + + /* Set all CLLR queue nodes to their default values */ + DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_VALUE); + + /* Set queue type */ + pQList->Type = QUEUE_TYPE_STATIC; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Link linked-list queue to a DMA channel. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, + DMA_QListTypeDef *const pQList) +{ + HAL_DMA_StateTypeDef state; + + /* Check the DMA channel handle and the queue parameters */ + if ((hdma == NULL) || (pQList == NULL)) + { + return HAL_ERROR; + } + + /* Get DMA state */ + state = hdma->State; + + /* Check DMA channel state */ + if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND)) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Check queue state */ + if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY; + + return HAL_ERROR; + } + + /* Check linearity compatibility */ + if ((IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) == 0U) && + ((pQList->Head->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_UNSUPPORTED; + + return HAL_ERROR; + } + + /* Check circularity compatibility */ + if (hdma->Mode == DMA_LINKEDLIST_CIRCULAR) + { + /* Check first circular node */ + if (pQList->FirstCircularNode == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + else + { + /* Check first circular node */ + if (pQList->FirstCircularNode != NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + + /* Register queue to DMA handle */ + hdma->LinkedListQueue = pQList; + + return HAL_OK; +} + +/** + * @brief Unlink linked-list queue from a DMA channel. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma) +{ + HAL_DMA_StateTypeDef state; + + /* Check the DMA channel parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Get DMA state */ + state = hdma->State; + + /* Check DMA channel state */ + if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND)) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Clear queue information from DMA channel handle */ + hdma->LinkedListQueue = NULL; + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group4 + * +@verbatim + ====================================================================================================================== + ##### Data handling, repeated block and trigger configuration functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure DMA channel data handling. + (+) Configure DMA channel repeated block. + (+) Configure DMA channel trigger. + + [..] + (+) The HAL_DMAEx_ConfigDataHandling() function allows to configure DMA channel data handling. + (++) GPDMA or HPDMA data handling : byte-based reordering, packing/unpacking, padding/truncation, + sign extension and left/right alignment. + + (+) The HAL_DMAEx_ConfigTrigger() function allows to configure DMA channel HW triggers. + + (+) The HAL_DMAEx_ConfigRepeatBlock() function allows to configure DMA channel repeated block. + (++) This feature is available only for channel that supports 2 dimensions addressing capability. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMA channel data handling according to the specified parameters in the + * DMA_DataHandlingConfTypeDef. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA Channel. + * @param pConfigDataHandling : Pointer to a DMA_DataHandlingConfTypeDef structure that contains the data handling + * configuration. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, + DMA_DataHandlingConfTypeDef const *const pConfigDataHandling) +{ + /* Check the DMA peripheral handle and data handling parameters */ + if ((hdma == NULL) || (pConfigDataHandling == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_DATA_ALIGNMENT(pConfigDataHandling->DataAlignment)); + assert_param(IS_DMA_DATA_EXCHANGE(pConfigDataHandling->DataExchange)); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + MODIFY_REG(hdma->Instance->CTR1, (DMA_CTR1_DWX | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM), + (pConfigDataHandling->DataAlignment | pConfigDataHandling->DataExchange)); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Configure the DMA channel trigger according to the specified parameters in the DMA_TriggerConfTypeDef. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for + * the specified DMA Channel. + * @param pConfigTrigger : Pointer to a DMA_TriggerConfTypeDef structure that contains the trigger configuration. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, + DMA_TriggerConfTypeDef const *const pConfigTrigger) +{ + /* Check the DMA peripheral handle and trigger parameters */ + if ((hdma == NULL) || (pConfigTrigger == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_TRIGGER_POLARITY(pConfigTrigger->TriggerPolarity)); + assert_param(IS_DMA_TRIGGER_MODE(pConfigTrigger->TriggerMode)); + assert_param(IS_DMA_TRIGGER_SELECTION(pConfigTrigger->TriggerSelection)); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM), + (pConfigTrigger->TriggerPolarity | pConfigTrigger->TriggerMode | + (pConfigTrigger->TriggerSelection << DMA_CTR2_TRIGSEL_Pos))); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Configure the DMA channel repeated block according to the specified parameters in the + * DMA_RepeatBlockConfTypeDef. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA Channel. + * @param pConfigRepeatBlock : Pointer to a DMA_RepeatBlockConfTypeDef structure that contains the repeated block + * configuration. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, + DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock) +{ + uint32_t tmpreg1; + uint32_t tmpreg2; + + /* Check the DMA peripheral handle and repeated block parameters */ + if ((hdma == NULL) || (pConfigRepeatBlock == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_REPEAT_COUNT(pConfigRepeatBlock->RepeatCount)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->SrcAddrOffset)); + assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->DestAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkSrcAddrOffset)); + assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkDestAddrOffset)); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Store repeat block count */ + tmpreg1 = ((pConfigRepeatBlock->RepeatCount - 1U) << DMA_CBR1_BRC_Pos); + + /* Check the sign of single/burst destination address offset value */ + if (pConfigRepeatBlock->DestAddrOffset < 0) + { + /* Store single/burst destination address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_DDEC; + tmpreg2 = (uint32_t)(- pConfigRepeatBlock->DestAddrOffset); + tmpreg2 = tmpreg2 << DMA_CTR3_DAO_Pos; + } + else + { + /* Store single/burst destination address offset configuration (unsigned case) */ + tmpreg2 = ((uint32_t)pConfigRepeatBlock->DestAddrOffset << DMA_CTR3_DAO_Pos); + } + + /* Check the sign of single/burst source address offset value */ + if (pConfigRepeatBlock->SrcAddrOffset < 0) + { + /* Store single/burst source address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_SDEC; + tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->SrcAddrOffset); + } + else + { + /* Store single/burst source address offset configuration (unsigned case) */ + tmpreg2 |= (uint32_t)pConfigRepeatBlock->SrcAddrOffset; + } + + /* Write DMA Channel Transfer Register 3 (CTR3) */ + WRITE_REG(hdma->Instance->CTR3, tmpreg2); + + /* Check the sign of block destination address offset value */ + if (pConfigRepeatBlock->BlkDestAddrOffset < 0) + { + /* Store block destination address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_BRDDEC; + tmpreg2 = (uint32_t)(- pConfigRepeatBlock->BlkDestAddrOffset); + tmpreg2 = tmpreg2 << DMA_CBR2_BRDAO_Pos; + } + else + { + /* Store block destination address offset configuration (unsigned case) */ + tmpreg2 = ((uint32_t)pConfigRepeatBlock->BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos); + } + + /* Check the sign of block source address offset value */ + if (pConfigRepeatBlock->BlkSrcAddrOffset < 0) + { + /* Store block source address offset configuration (signed case) */ + tmpreg1 |= DMA_CBR1_BRSDEC; + tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->BlkSrcAddrOffset); + } + else + { + /* Store block source address offset configuration (unsigned case) */ + tmpreg2 |= (uint32_t)pConfigRepeatBlock->BlkSrcAddrOffset; + } + + /* Write DMA Channel block register 2 (CBR2) */ + WRITE_REG(hdma->Instance->CBR2, tmpreg2); + + /* Write DMA Channel block register 1 (CBR1) */ + WRITE_REG(hdma->Instance->CBR1, tmpreg1); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group5 + * +@verbatim + ====================================================================================================================== + ##### Suspend and resume operation functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Suspend any ongoing DMA channel transfer. + (+) Resume any suspended DMA channel transfer. + + [..] + (+) The HAL_DMAEx_Suspend() function allows to suspend any ongoing DMA channel transfer in polling mode (Blocking + mode). + + (+) The HAL_DMAEx_Suspend_IT() function allows to suspend any ongoing DMA channel transfer in interrupt mode + (Non-blocking mode). + + (+) The HAL_DMAEx_Resume() function allows to resume any suspended DMA channel transfer. + +@endverbatim + * @{ + */ + +/** + * @brief Suspend any ongoing DMA channel transfer in polling mode (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA channel. + * @note After suspending a DMA channel, a check for wait until the DMA channel is effectively suspended is added. If + * a channel is suspended while a data transfer is ongoing, the current data will be transferred and the + * channel will be effectively suspended only after the transfer of this single/burst data is finished. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Suspend the channel */ + hdma->Instance->CCR |= DMA_CCR_SUSP; + + /* Check if the DMA channel is suspended */ + while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) + { + /* Check for the timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; + } + + return HAL_OK; +} + +/** + * @brief Suspend any ongoing DMA channel transfer in polling mode (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Suspend the DMA channel and activate suspend interrupt */ + hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE); + } + + return HAL_OK; +} + +/** + * @brief Resume any suspended DMA channel transfer. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_SUSPEND) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Resume the DMA channel */ + hdma->Instance->CCR &= (~DMA_CCR_SUSP); + + /* Clear the suspend flag */ + hdma->Instance->CFCR |= DMA_CFCR_SUSPF; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group6 + * +@verbatim + ====================================================================================================================== + ##### Fifo status function ##### + ====================================================================================================================== + [..] + This section provides function allowing to get DMA channel FIFO level. + + [..] + (+) The HAL_DMAEx_GetFifoLevel() function allows to return the number of available write beats in the FIFO, in + units of the programmed destination data. + (++) This API is available only for DMA channels that supports FIFO. + +@endverbatim + * @{ + */ + +/** + * @brief Get and returns the DMA channel FIFO level. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval Returns the number of available beats in FIFO. + */ +uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma) +{ + return ((hdma->Instance->CSR & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private Functions + * @{ + */ + +/** + * @brief Initialize the DMA handle according to the specified parameters in the DMA_InitTypeDef. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval None. + */ +static void DMA_List_Init(DMA_HandleTypeDef const *const hdma) +{ + uint32_t tmpreg; + + /* Prepare DMA Channel Control Register (CCR) value */ + tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode; + + /* Check DMA channel instance */ + if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)) + { + tmpreg |= hdma->InitLinkedList.LinkAllocatedPort; + } + + /* Write DMA Channel Control Register (CCR) */ + MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg); + + /* Write DMA Channel Control Register (CTR1) */ + WRITE_REG(hdma->Instance->CTR1, 0U); + + /* Write DMA Channel Control Register (CTR2) */ + WRITE_REG(hdma->Instance->CTR2, hdma->InitLinkedList.TransferEventMode); + + /* Write DMA Channel Control Register (CBR1) */ + WRITE_REG(hdma->Instance->CBR1, 0U); + + /* Write DMA Channel Control Register (CSAR) */ + WRITE_REG(hdma->Instance->CSAR, 0U); + + /* Write DMA Channel Control Register (CDAR) */ + WRITE_REG(hdma->Instance->CDAR, 0U); + + /* If 2D Addressing is supported by current channel */ + if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) + { + /* Write DMA Channel Control Register (CTR3) */ + WRITE_REG(hdma->Instance->CTR3, 0U); + + /* Write DMA Channel Control Register (CBR2) */ + WRITE_REG(hdma->Instance->CBR2, 0U); + } + + /* Write DMA Channel linked-list address register (CLLR) */ + WRITE_REG(hdma->Instance->CLLR, 0U); +} + +/** + * @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @retval None. + */ +static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode) +{ + int32_t blockoffset; + + /* Update CTR1 register value ***************************************************************************************/ + /* Prepare DMA channel transfer register (CTR1) value */ + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] = pNodeConfig->Init.DestInc | + pNodeConfig->Init.DestDataWidth | + pNodeConfig->DataHandlingConfig.DataAlignment | + pNodeConfig->Init.SrcInc | + pNodeConfig->Init.SrcDataWidth; + + + /* Add parameters related to DMA configuration */ + if ((pNodeConfig->NodeType & (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_HPDMA)) != 0U) + { + /* Prepare DMA channel transfer register (CTR1) value */ + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= + (pNodeConfig->Init.TransferAllocatedPort | pNodeConfig->DataHandlingConfig.DataExchange | + (((pNodeConfig->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) | + (((pNodeConfig->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1)); + } + /*********************************************************************************** CTR1 register value is updated */ + + + /* Update CTR2 register value ***************************************************************************************/ + /* Prepare DMA channel transfer register 2 (CTR2) value */ + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] = pNodeConfig->Init.TransferEventMode | + (pNodeConfig->Init.Request & (DMA_CTR2_REQSEL | DMA_CTR2_SWREQ)); + + /* Check for memory to peripheral transfer */ + if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Check for GPDMA OR HPDMA */ + if ((pNodeConfig->NodeType & (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_HPDMA)) != 0U) + { + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_DREQ; + } + } + /* Memory to memory transfer */ + else if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_MEMORY) + { + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_SWREQ; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Configure HW Peripheral flow control selection */ + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= pNodeConfig->Init.Mode; + + /* Check if trigger feature is active */ + if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED) + { + /* Prepare DMA channel transfer register 2 (CTR2) value */ + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= + pNodeConfig->TriggerConfig.TriggerMode | pNodeConfig->TriggerConfig.TriggerPolarity | + ((pNodeConfig->TriggerConfig.TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); + } + /*********************************************************************************** CTR2 register value is updated */ + + + /* Update CBR1 register value ***************************************************************************************/ + /* Prepare DMA channel block register 1 (CBR1) value */ + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (pNodeConfig->DataSize & DMA_CBR1_BNDT); + + /* If 2D addressing is supported by the selected DMA channel */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Set the new CBR1 Register value */ + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= + (((pNodeConfig->RepeatBlockConfig.RepeatCount - 1U) << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC); + + /* If the source address offset is negative, set SDEC bit */ + if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_SDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_SDEC); + } + + /* If the destination address offset is negative, set DDEC bit */ + if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_DDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_DDEC); + } + + /* If the repeated block source address offset is negative, set BRSEC bit */ + if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRSDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRSDEC); + } + + /* if the repeated block destination address offset is negative, set BRDEC bit */ + if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0) + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRDDEC; + } + else + { + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRDDEC); + } + } + /*********************************************************************************** CBR1 register value is updated */ + + + /* Update CSAR register value ***************************************************************************************/ + pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = pNodeConfig->SrcAddress; + /*********************************************************************************** CSAR register value is updated */ + + + /* Update CDAR register value ***************************************************************************************/ + pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pNodeConfig->DstAddress; + /*********************************************************************************** CDAR register value is updated */ + + /* Check if the selected channel is 2D addressing */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Update CTR3 register value *************************************************************************************/ + /* Write new CTR3 Register value : source address offset */ + if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.SrcAddrOffset); + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CTR3_SAO); + } + else + { + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = + ((uint32_t)pNodeConfig->RepeatBlockConfig.SrcAddrOffset & DMA_CTR3_SAO); + } + + /* Write new CTR3 Register value : destination address offset */ + if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.DestAddrOffset); + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |= (((uint32_t)blockoffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO); + } + else + { + pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |= + (((uint32_t)pNodeConfig->RepeatBlockConfig.DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO); + } + /********************************************************************************* CTR3 register value is updated */ + + + /* Update CBR2 register value *************************************************************************************/ + /* Write new CBR2 Register value : repeated block source address offset */ + if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset); + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CBR2_BRSAO); + } + else + { + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] = + ((uint32_t)pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset & DMA_CBR2_BRSAO); + } + + /* Write new CBR2 Register value : repeated block destination address offset */ + if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0) + { + blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset); + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |= + (((uint32_t)blockoffset & DMA_CBR2_BRSAO) << DMA_CBR2_BRDAO_Pos); + } + else + { + pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |= + (((uint32_t)pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO); + } + /********************************************************************************* CBR2 register value is updated */ + } + + + /* Update node information value ************************************************************************************/ + /* Set node information */ + pNode->NodeInfo = pNodeConfig->NodeType; + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + pNode->NodeInfo |= (NODE_CLLR_2D_DEFAULT_OFFSET << NODE_CLLR_IDX_POS); + } + else + { + pNode->NodeInfo |= (NODE_CLLR_LINEAR_DEFAULT_OFFSET << NODE_CLLR_IDX_POS); + } + /******************************************************************************** Node information value is updated */ +} + +/** + * @brief Get a DMA channel node configuration. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @retval None. + */ +static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode) +{ + uint16_t offset; + + /* Get node information *********************************************************************************************/ + pNodeConfig->NodeType = (pNode->NodeInfo & NODE_TYPE_MASK); + /*************************************************************************************** Node type value is updated */ + + + /* Get CTR1 fields values *******************************************************************************************/ + pNodeConfig->Init.SrcInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SINC; + pNodeConfig->Init.DestInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DINC; + pNodeConfig->Init.SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SDW_LOG2; + pNodeConfig->Init.DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; + pNodeConfig->Init.SrcBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U; + pNodeConfig->Init.DestBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U; + pNodeConfig->Init.TransferAllocatedPort = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + (DMA_CTR1_SAP | DMA_CTR1_DAP); + pNodeConfig->DataHandlingConfig.DataExchange = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + (DMA_CTR1_SBX | DMA_CTR1_DBX | DMA_CTR1_DHX | DMA_CTR1_DWX); + pNodeConfig->DataHandlingConfig.DataAlignment = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_PAM; + /*********************************************************************************** CTR1 fields values are updated */ + + + /* Get CTR2 fields values *******************************************************************************************/ + if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_SWREQ) != 0U) + { + pNodeConfig->Init.Request = DMA_REQUEST_SW; + pNodeConfig->Init.Direction = DMA_MEMORY_TO_MEMORY; + } + else + { + pNodeConfig->Init.Request = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_REQSEL; + + if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_DREQ) != 0U) + { + pNodeConfig->Init.Direction = DMA_MEMORY_TO_PERIPH; + } + else + { + pNodeConfig->Init.Direction = DMA_PERIPH_TO_MEMORY; + } + } + + pNodeConfig->Init.BlkHWRequest = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_BREQ); + pNodeConfig->TriggerConfig.TriggerMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGM; + pNodeConfig->TriggerConfig.TriggerPolarity = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGPOL; + pNodeConfig->TriggerConfig.TriggerSelection = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & + DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos; + pNodeConfig->Init.TransferEventMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TCEM; + /*********************************************************************************** CTR2 fields values are updated */ + + + /* Get CBR1 fields **************************************************************************************************/ + pNodeConfig->DataSize = pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BNDT; + + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + pNodeConfig->RepeatBlockConfig.RepeatCount = + ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos) + 1U; + } + else + { + pNodeConfig->RepeatBlockConfig.RepeatCount = 1U; + } + /*********************************************************************************** CBR1 fields values are updated */ + + + /* Get CSAR field ***************************************************************************************************/ + pNodeConfig->SrcAddress = pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]; + /************************************************************************************** CSAR field value is updated */ + + + /* Get CDAR field ***************************************************************************************************/ + pNodeConfig->DstAddress = pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]; + /************************************************************************************** CDAR field value is updated */ + + /* Check if the selected channel is 2D addressing */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Get CTR3 field *************************************************************************************************/ + offset = (uint16_t)(pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_SAO); + pNodeConfig->RepeatBlockConfig.SrcAddrOffset = (int32_t)offset; + + offset = (uint16_t)((pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos); + pNodeConfig->RepeatBlockConfig.DestAddrOffset = (int32_t)offset; + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_SDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.SrcAddrOffset *= (-1); + } + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_DDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.DestAddrOffset *= (-1); + } + /************************************************************************************ CTR3 field value is updated */ + + + /* Get CBR2 fields ************************************************************************************************/ + offset = (uint16_t)(pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRSAO); + pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset = (int32_t)offset; + + offset = (uint16_t)((pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos); + pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = (int32_t)offset; + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRSDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset *= (-1); + } + + if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRDDEC) != 0U) + { + pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset *= (-1); + } + /************************************************************************************ CBR2 field value is updated */ + } + else + { + /* Get CTR3 field *************************************************************************************************/ + pNodeConfig->RepeatBlockConfig.SrcAddrOffset = 0; + pNodeConfig->RepeatBlockConfig.DestAddrOffset = 0; + /************************************************************************************ CTR3 field value is updated */ + + + /* Get CBR2 fields ************************************************************************************************/ + pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset = 0; + pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = 0; + /************************************************************************************ CBR2 field value is updated */ + } +} + +/** + * @brief Check nodes base addresses compatibility. + * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. + * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. + * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. + * @retval Return 0 when nodes addresses are compatible, 1 otherwise. + */ +static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3) +{ + uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA); + uint32_t ref = 0U; + + /* Check node 1 address */ + if ((uint32_t)pNode1 != 0U) + { + ref = (uint32_t)pNode1; + } + /* Check node 2 address */ + else if ((uint32_t)pNode2 != 0U) + { + ref = (uint32_t)pNode2; + } + /* Check node 3 address */ + else if ((uint32_t)pNode3 != 0U) + { + ref = (uint32_t)pNode3; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check addresses compatibility */ + if (temp != ((uint32_t)ref & DMA_CLBAR_LBA)) + { + return 1U; + } + + return 0U; +} + +/** + * @brief Check nodes types compatibility. + * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. + * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. + * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. + * @retval Return 0 when nodes types are compatible, otherwise nodes types are not compatible. + */ +static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3) +{ + uint32_t ref = 0U; + + /* Check node 1 parameter */ + if (pNode1 != NULL) + { + ref = pNode1->NodeInfo & NODE_TYPE_MASK; + } + /* Check node 2 parameter */ + else if (pNode2 != NULL) + { + ref = pNode2->NodeInfo & NODE_TYPE_MASK; + } + /* Check node 3 parameter */ + else if (pNode3 != NULL) + { + ref = pNode3->NodeInfo & NODE_TYPE_MASK; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check node 2 parameter */ + if (pNode2 != NULL) + { + /* Check node type compatibility */ + if (ref != (pNode2->NodeInfo & NODE_TYPE_MASK)) + { + return 2U; + } + } + + /* Check node 3 parameter */ + if (pNode3 != NULL) + { + /* Check node type compatibility */ + if (ref != (pNode3->NodeInfo & NODE_TYPE_MASK)) + { + return 3U; + } + } + + return 0U; +} + +/** + * @brief Check nodes types compatibility. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @param cllr_mask : Pointer to CLLR register mask value. + * @param cllr_offset : Pointer to CLLR register offset value. + * @retval None. + */ +static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, + uint32_t *const cllr_mask, + uint32_t *const cllr_offset) +{ + /* Check node type */ + if ((pNode->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) + { + /* Update CLLR register mask value */ + if (cllr_mask != NULL) + { + *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | + DMA_CLLR_UB2 | DMA_CLLR_ULL; + } + + /* Update CLLR register offset */ + if (cllr_offset != NULL) + { + *cllr_offset = NODE_CLLR_2D_DEFAULT_OFFSET; + } + } + /* Update CLLR and register number for linear addressing node */ + else + { + /* Update CLLR register mask value */ + if (cllr_mask != NULL) + { + *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL; + } + + /* Update CLLR register offset */ + if (cllr_offset != NULL) + { + *cllr_offset = NODE_CLLR_LINEAR_DEFAULT_OFFSET; + } + } +} + +/** + * @brief Find node in queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers configurations. + * @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information. + * @retval Return 0 when node is found in selected queue, otherwise node is not found. + */ +static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList, + DMA_NodeTypeDef const *const pNode, + DMA_NodeInQInfoTypeDef *const NodeInfo) +{ + uint32_t node_idx = 0U; + uint32_t currentnode_address = 0U; + uint32_t previousnode_address = 0U; + uint32_t cllr_offset = NodeInfo->cllr_offset; + + /* Find last node in queue */ + if (pNode == NULL) + { + /* Check that previous node is linked to the selected queue */ + while (node_idx < pQList->NodeNumber) + { + /* Get head node address */ + if (node_idx == 0U) + { + currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; + } + /* Calculate nodes addresses */ + else + { + previousnode_address = currentnode_address; + currentnode_address = + ((DMA_NodeTypeDef *)(currentnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + } + + /* Increment node index */ + node_idx++; + } + } + /* Find selected node node in queue */ + else + { + /* Check that previous node is linked to the selected queue */ + while ((node_idx < pQList->NodeNumber) && (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA))) + { + /* Get head node address */ + if (node_idx == 0U) + { + currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; + } + /* Calculate nodes addresses */ + else + { + previousnode_address = currentnode_address; + currentnode_address = + ((DMA_NodeTypeDef *)(currentnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + } + + /* Increment node index */ + node_idx++; + } + } + + /* Check stored address */ + if (pNode != NULL) + { + if (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA)) + { + return 1U; + } + } + + /* Update current node position */ + NodeInfo->currentnode_pos = node_idx; + + /* Update previous node address */ + NodeInfo->previousnode_addr = previousnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + + /* Update current node address */ + NodeInfo->currentnode_addr = currentnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + + /* Update next node address */ + if (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] != 0U) + { + NodeInfo->nextnode_addr = (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] & + DMA_CLLR_LA) | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + } + + return 0U; +} + +/** + * @brief Reset queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information. + * @retval None. + */ +static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList, + DMA_NodeInQInfoTypeDef const *const NodeInfo) +{ + uint32_t node_idx = 0U; + uint32_t currentnode_address = 0U; + uint32_t previousnode_address; + uint32_t cllr_offset = NodeInfo->cllr_offset; + + /* Check that previous node is linked to the selected queue */ + while (node_idx < pQList->NodeNumber) + { + /* Get head node address */ + if (node_idx == 0U) + { + previousnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; + currentnode_address = (pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA); + } + /* Calculate nodes addresses */ + else + { + previousnode_address = currentnode_address; + currentnode_address = + ((DMA_NodeTypeDef *)(currentnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + } + + /* Reset node */ + ((DMA_NodeTypeDef *)(previousnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] = 0U; + + /* Increment node index */ + node_idx++; + } +} + +/** + * @brief Fill source node registers values by destination nodes registers values. + * @param pSrcNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list source node registers + * configurations. + * @param pDestNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list destination node registers + * configurations. + * @retval None. + */ +static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode, + DMA_NodeTypeDef *const pDestNode) +{ + /* Repeat for all register nodes */ + for (uint32_t reg_idx = 0U; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++) + { + pDestNode->LinkRegisters[reg_idx] = pSrcNode->LinkRegisters[reg_idx]; + } + + /* Fill node information */ + pDestNode->NodeInfo = pSrcNode->NodeInfo; +} + +/** + * @brief Convert node to dynamic. + * @param ContextNodeAddr : The context node address. + * @param CurrentNodeAddr : The current node address to be converted. + * @param RegisterNumber : The register number to be converted. + * @retval None. + */ +static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber) +{ + uint32_t currentnode_reg_counter = 0U; + uint32_t contextnode_reg_counter = 0U; + uint32_t cllr_idx = RegisterNumber - 1U; + DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; + DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; + uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, + DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL + }; + + /* Update ULL position according to register number */ + update_link[cllr_idx] = update_link[NODE_MAXIMUM_SIZE - 1U]; + + /* Repeat for all node registers */ + while (contextnode_reg_counter != RegisterNumber) + { + /* Check if register values are equal (exception for CSAR, CDAR and CLLR registers) */ + if ((context_node->LinkRegisters[contextnode_reg_counter] == + current_node->LinkRegisters[currentnode_reg_counter]) && + (contextnode_reg_counter != NODE_CSAR_DEFAULT_OFFSET) && + (contextnode_reg_counter != NODE_CDAR_DEFAULT_OFFSET) && + (contextnode_reg_counter != (RegisterNumber - 1U))) + { + /* Format the node according to unused registers */ + DMA_List_FormatNode(current_node, currentnode_reg_counter, RegisterNumber, NODE_DYNAMIC_FORMAT); + + /* Update CLLR index */ + cllr_idx --; + + /* Update CLLR fields */ + current_node->LinkRegisters[cllr_idx] &= ~update_link[contextnode_reg_counter]; + } + else + { + /* Update context node register fields with new values */ + context_node->LinkRegisters[contextnode_reg_counter] = current_node->LinkRegisters[currentnode_reg_counter]; + + /* Update CLLR fields */ + current_node->LinkRegisters[cllr_idx] |= update_link[contextnode_reg_counter]; + + /* Increment current node number register counter */ + currentnode_reg_counter++; + } + + /* Increment context node number register counter */ + contextnode_reg_counter++; + } + + /* Update node information */ + MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((currentnode_reg_counter - 1U) << NODE_CLLR_IDX_POS)); + + /* Clear unused node fields */ + DMA_List_ClearUnusedFields(current_node, currentnode_reg_counter); +} + +/** + * @brief Convert node to static. + * @param ContextNodeAddr : The context node address. + * @param CurrentNodeAddr : The current node address to be converted. + * @param RegisterNumber : The register number to be converted. + * @retval None. + */ +static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber) +{ + uint32_t contextnode_reg_counter = 0U; + uint32_t cllr_idx; + uint32_t cllr_mask; + const DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; + DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; + uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, + DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL + }; + + /* Update ULL position according to register number */ + update_link[RegisterNumber - 1U] = update_link[NODE_MAXIMUM_SIZE - 1U]; + + /* Get context node CLLR information */ + cllr_idx = (context_node->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + cllr_mask = context_node->LinkRegisters[cllr_idx]; + + /* Repeat for all node registers */ + while (contextnode_reg_counter != RegisterNumber) + { + /* Check if node field is dynamic */ + if ((cllr_mask & update_link[contextnode_reg_counter]) == 0U) + { + /* Format the node according to unused registers */ + DMA_List_FormatNode(current_node, contextnode_reg_counter, RegisterNumber, NODE_STATIC_FORMAT); + + /* Update node field */ + current_node->LinkRegisters[contextnode_reg_counter] = context_node->LinkRegisters[contextnode_reg_counter]; + } + + /* Increment context node number register counter */ + contextnode_reg_counter++; + } + + /* Update node information */ + MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((RegisterNumber - 1U) << NODE_CLLR_IDX_POS)); +} + +/** + * @brief Format the node according to unused registers. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @param RegisterIdx : The first register index to be formatted. + * @param RegisterNumber : The number of node registers. + * @param Format : The format type. + * @retval None. + */ +static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode, + uint32_t RegisterIdx, + uint32_t RegisterNumber, + uint32_t Format) +{ + if (Format == NODE_DYNAMIC_FORMAT) + { + /* Repeat for all registers to be formatted */ + for (uint32_t reg_idx = RegisterIdx; reg_idx < (RegisterNumber - 1U); reg_idx++) + { + pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx + 1U]; + } + } + else + { + /* Repeat for all registers to be formatted */ + for (uint32_t reg_idx = (RegisterNumber - 2U); reg_idx > RegisterIdx; reg_idx--) + { + pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx - 1U]; + } + } +} + +/** + * @brief Clear unused register fields. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @param FirstUnusedField : The first unused field to be cleared. + * @retval None. + */ +static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode, + uint32_t FirstUnusedField) +{ + /* Repeat for all unused fields */ + for (uint32_t reg_idx = FirstUnusedField; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++) + { + pNode->LinkRegisters[reg_idx] = 0U; + } +} + +/** + * @brief Update CLLR for all dynamic queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param LastNode_IsCircular : The first circular node is the last queue node or not. + * @retval None. + */ +static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t LastNode_IsCircular) +{ + uint32_t previous_cllr_offset; + uint32_t current_cllr_offset = 0U; + uint32_t previousnode_addr; + uint32_t currentnode_addr = (uint32_t)pQList->Head; + uint32_t cllr_mask; + uint32_t node_idx = 0U; + + /* Repeat for all register nodes */ + while (node_idx < pQList->NodeNumber) + { + /* Get head node address */ + if (node_idx == 0U) + { + /* Get current node information */ + current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + } + /* Calculate nodes addresses */ + else + { + /* Get previous node information */ + previousnode_addr = currentnode_addr; + previous_cllr_offset = current_cllr_offset; + + /* Get current node information */ + currentnode_addr = (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA) + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + + /* Calculate CLLR register value to be updated */ + cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & ~DMA_CLLR_LA) | + (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA); + + /* Set new CLLR value to previous node */ + ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] = cllr_mask; + } + + /* Increment node index */ + node_idx++; + } + + /* Check queue circularity */ + if (pQList->FirstCircularNode != 0U) + { + /* First circular queue is not last queue node */ + if (LastNode_IsCircular == 0U) + { + /* Get CLLR node information */ + DMA_List_GetCLLRNodeInfo(((DMA_NodeTypeDef *)currentnode_addr), &cllr_mask, NULL); + + /* Update CLLR register for last circular node */ + ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] = + ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + } + /* First circular queue is last queue node */ + else + { + /* Disable CLLR updating */ + ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL; + } + } + else + { + /* Clear CLLR register for last node */ + ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] = 0U; + } +} + +/** + * @brief Update CLLR for all static queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param operation : The operation type. + * @retval None. + */ +static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t operation) +{ + uint32_t currentnode_addr = (uint32_t)pQList->Head; + uint32_t current_cllr_offset = ((uint32_t)pQList->Head->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + uint32_t cllr_default_offset; + uint32_t cllr_default_mask; + uint32_t cllr_mask; + uint32_t node_idx = 0U; + + /* Get CLLR node information */ + DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_default_mask, &cllr_default_offset); + + /* Repeat for all register nodes (Bypass last queue node) */ + while (node_idx < pQList->NodeNumber) + { + if (operation == UPDATE_CLLR_POSITION) + { + /* Get CLLR value */ + cllr_mask = ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset]; + } + else + { + /* Calculate CLLR value */ + cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & DMA_CLLR_LA) | + cllr_default_mask; + } + + /* Set new CLLR value to default position */ + if ((node_idx == (pQList->NodeNumber - 1U)) && (pQList->FirstCircularNode == NULL)) + { + ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = 0U; + } + else + { + ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = cllr_mask; + } + + /* Update current node address with next node address */ + currentnode_addr = (currentnode_addr & DMA_CLBAR_LBA) | (cllr_mask & DMA_CLLR_LA); + + /* Update current CLLR offset with next CLLR offset */ + current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + + /* Increment node index */ + node_idx++; + } +} + +/** + * @brief Clean linked-list queue variable. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval None. + */ +static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList) +{ + /* Clear head node */ + pQList->Head = NULL; + + /* Clear first circular queue node */ + pQList->FirstCircularNode = NULL; + + /* Reset node number */ + pQList->NodeNumber = 0U; + + /* Reset queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_RESET; + + /* Reset queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Reset queue type */ + pQList->Type = QUEUE_TYPE_STATIC; +} +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dts.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dts.c new file mode 100644 index 00000000000..660fbd52d94 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dts.c @@ -0,0 +1,1087 @@ +/** + ********************************************************************************************************************** + * @file stm32h7rsxx_hal_dts.c + * @author MCD Application Team + * @brief DTS HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the DTS peripheral: + * + Initialization and de-initialization functions + * + Start/Stop operation functions in polling mode. + * + Start/Stop operation functions in interrupt mode. + * + Peripheral Control functions + * + Peripheral State functions + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + @verbatim + ====================================================================================================================== + ##### DTS Peripheral features ##### + ====================================================================================================================== + + [..] + The STM32h7rsxx device family integrate one DTS sensor interface that converts the temperature into a square wave + which frequency is proportional to the temperature. + + (+) Temperature window comparator feature: + The DTS allows defining the high and low threshold that will be used for temperature comparison. + If the temperature data is equal or higher than the high threshold, or equal or lower than the low threshold, + an interrupt is generated and the corresponding flag. + + (+) Synchronous interrupts: + A global interrupt output line is available on the DTS block. The interrupt can be generated + at the end of measurement and/or when the measurement result is equal/higher or equal/lower than + a predefined threshold. + + (+) Asynchronous wakeup: + The DTS block provides an asynchronous interrupt line. It is used only when the LSE is selected as reference + clock. This line can generate a signal that wakes up the system from Sleep and stop mode at the end of + measurement and/or when the measurement result is equal/higher or equal/lower than a + predefined threshold. + + (+) Trigger inputs: + The temperature measurement can be triggered either by software or by an external event + as well as lowpower timer. + + (+) Measurement modes: + (++) Quick measure : measure without a calibration when a high precision is not required. + (++) Slow measure : measure with a calibration used when a high precision is required. + + (+) Sampling time: + The sampling time can be used to increase temperature measurement precision. + + (+) Prescaler: + When a calibration is ongoing, the counter clock must be slower than 1 MHz. This is + achieved by the PCLK clock prescaler embedded in the temperature sensor. + + (+) Operating Modes: + + (++) PCLK only : The temperature sensor registers can be accessed. The interface can consequently be + reconfigured and the measurement sequence is performed using PCLK clock. + + (++) PCLK and LSE : The temperature sensor registers can be accessed. The interface can consequently be + reconfigured and the measurement sequence is performed using the LSE clock. + + (++) LSE only : The registers cannot be accessed. The measurement can be performed using the LSE + clock This mode is used to exit from Sleep and stop mode by using hardware triggers + and the asynchronous interrupt line. + (+) Calibration: + The temperature sensor must run the calibration prior to any frequency measurement. The calibration is + performed automatically when the temperature measurement is triggered except for quick measurement mode. + + (+) Low power modes: + (++) Sleep mode: only works in LSE mode. + (++) Stop mode: only works in LSE mode. + + ====================================================================================================================== + ##### How to use this driver ##### + ====================================================================================================================== + [..] + This driver provides functions to configure and program the DTS instances of STM32H7RSxx devices. + + To use the DTS, perform the following steps: + + (+) Initialize the DTS low level resources by implementing the HAL_DTS_MspInit(): + + (++) If required enable the DTS interrupt by configuring and enabling EXTI line in Interrupt mode After that + enable the DTS interrupt vector using HAL_NVIC_EnableIRQ() function. + + (+) Configure the DTS using HAL_DTS_Init() function: + + (++) Select the quick measure option + (++) Select the reference clock. + (++) Select the trigger input. + (++) Select the sampling time. + (++) Select the high speed clock ratio divider. + (++) Select the low threshold + (++) Select the high threshold + + + (+) Use HAL_DTS_Start() to enable and start the DTS sensor in polling mode. + + (+) Use HAL_DTS_Start_IT() to enable and start the DTS sensor in interrupt mode. + + (+) Use HAL_DTS_GetTemperature() to get temperature from DTS. + + (+) Use HAL_DTS_Stop() to disable and stop the DTS sensor in polling mode. + + (+) Use HAL_DTS_Stop_IT() to disable and stop the DTS sensor in interrupt mode. + + (+) De-initialize the DTS using HAL_DTS_DeInit() function. + + *** Callback and interrupts *** + ============================================= + [..] + When the compilation flag USE_HAL_DTS_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration + feature is not available and all callbacks are set to the corresponding weak functions. + + (+) Implement the weak function HAL_DTS_EndCallback() to get a callback at the end of the temperature measurement. + (+) Implement the weak function HAL_DTS_HighCallback() to get a callback when the temperature + exceed the high threshold. + (+) Implement the weak function HAL_DTS_LowCallback() to get a callback when the temperature + go down the low threshold. + (+) Implement the weak function HAL_DTS_AsyncEndCallback() to get a callback at the end + of an asynchronous temperature measurement. + (+) Implement the weak function HAL_DTS_AsyncHighCallback() to get a callback when the temperature + exceed the high threshold in an asynchronous measurement. + (+) Implement the weak function HAL_DTS_AsyncLowCallback() to get a callback when the temperature + go down the low threshold in an asynchronous measurement. + + [..] + The compilation flag USE_HAL_DTS_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically + the driver callbacks. + + *** State *** + ============================================= + [..] + The driver permits to get in run time the status of the peripheral. + + (+) Use HAL_DTS_GetState() to get the state of the DTS. + + @endverbatim + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#ifdef HAL_DTS_MODULE_ENABLED + +/** @defgroup DTS DTS + * @brief DTS HAL module driver + * @{ + */ + +/* Private typedef ---------------------------------------------------------------------------------------------------*/ +/* Private define ----------------------------------------------------------------------------------------------------*/ +/** @addtogroup DTS_Private_Constants + * @{ + */ + +/* @brief Delay for DTS startup time + * @note Delay required to get ready for DTS Block. + * @note Unit: ms + */ +#define DTS_DELAY_STARTUP (1UL) + +/* @brief DTS measure ready flag time out value. + * @note Maximal measurement time is when LSE is selected as ref_clock and + * maximal sampling time is used, taking calibration into account this + * is equivalent to ~620 us. Use 5 ms as arbitrary timeout + * @note Unit: ms + */ +#define TS_TIMEOUT_MS (5UL) + +/* @brief DTS factory temperatures + * @note Unit: degree Celsius + */ +#define DTS_FACTORY_TEMPERATURE1 (30UL) +#define DTS_FACTORY_TEMPERATURE2 (130UL) + +/** + * @} + */ + +/* Private macro -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup DTS_Exported_Functions DTS Exported Functions + * @{ + */ + +/** @defgroup DTS_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and de-initialization functions. + * +@verbatim + ======================================================================================================================= + ##### Initialization and de-initialization functions ##### + ======================================================================================================================= + [..] This section provides functions to initialize and de-initialize DTS + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DTS according to the specified + * parameters in the DTS_InitTypeDef and initialize the associated handle. + * @param hdts DTS handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts) +{ + /* Check the DTS handle allocation */ + if (hdts == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance)); + assert_param(IS_DTS_QUICKMEAS(hdts->Init.QuickMeasure)); + assert_param(IS_DTS_REFCLK(hdts->Init.RefClock)); + assert_param(IS_DTS_TRIGGERINPUT(hdts->Init.TriggerInput)); + assert_param(IS_DTS_SAMPLINGTIME(hdts->Init.SamplingTime)); + assert_param(IS_DTS_THRESHOLD(hdts->Init.HighThreshold)); + assert_param(IS_DTS_THRESHOLD(hdts->Init.LowThreshold)); + + if (hdts->State == HAL_DTS_STATE_RESET) + { +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U) + /* Reset the DTS callback to the legacy weak callbacks */ + hdts->EndCallback = HAL_DTS_EndCallback; /* End measure Callback */ + hdts->LowCallback = HAL_DTS_LowCallback; /* low threshold Callback */ + hdts->HighCallback = HAL_DTS_HighCallback; /* high threshold Callback */ + hdts->AsyncEndCallback = HAL_DTS_AsyncEndCallback; /* Asynchronous end of measure Callback */ + hdts->AsyncLowCallback = HAL_DTS_AsyncLowCallback; /* Asynchronous low threshold Callback */ + hdts->AsyncHighCallback = HAL_DTS_AsyncHighCallback; /* Asynchronous high threshold Callback */ + + if (hdts->MspInitCallback == NULL) + { + hdts->MspInitCallback = HAL_DTS_MspInit; + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + hdts->MspInitCallback(hdts); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_DTS_MspInit(hdts); +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ + } + + /* Change the DTS state */ + hdts->State = HAL_DTS_STATE_BUSY; + + /* Check ramp coefficient */ + if (hdts->Instance->RAMPVALR == 0UL) + { + return HAL_ERROR; + } + + /* Check factory calibration temperature */ + if (hdts->Instance->T0VALR1 == 0UL) + { + return HAL_ERROR; + } + + /* Check Quick Measure option is enabled or disabled */ + if (hdts->Init.QuickMeasure == DTS_QUICKMEAS_DISABLE) + { + /* Check Reference clock selection */ + if (hdts->Init.RefClock == DTS_REFCLKSEL_PCLK) + { + assert_param(IS_DTS_DIVIDER_RATIO_NUMBER(hdts->Init.Divider)); + } + /* Quick measurement mode disabled */ + CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_Q_MEAS_OPT); + } + else + { + /* DTS_QUICKMEAS_ENABLE shall be used only when the LSE clock is + selected as reference clock */ + if (hdts->Init.RefClock != DTS_REFCLKSEL_LSE) + { + return HAL_ERROR; + } + + /* Quick measurement mode enabled - no calibration needed */ + SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_Q_MEAS_OPT); + } + + /* set the DTS clk source */ + if (hdts->Init.RefClock == DTS_REFCLKSEL_LSE) + { + SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_REFCLK_SEL); + } + else + { + CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_REFCLK_SEL); + } + + MODIFY_REG(hdts->Instance->CFGR1, DTS_CFGR1_HSREF_CLK_DIV, (hdts->Init.Divider << DTS_CFGR1_HSREF_CLK_DIV_Pos)); + MODIFY_REG(hdts->Instance->CFGR1, DTS_CFGR1_TS1_SMP_TIME, hdts->Init.SamplingTime); + MODIFY_REG(hdts->Instance->CFGR1, DTS_CFGR1_TS1_INTRIG_SEL, hdts->Init.TriggerInput); + MODIFY_REG(hdts->Instance->ITR1, DTS_ITR1_TS1_HITTHD, (hdts->Init.HighThreshold << DTS_ITR1_TS1_HITTHD_Pos)); + MODIFY_REG(hdts->Instance->ITR1, DTS_ITR1_TS1_LITTHD, hdts->Init.LowThreshold); + + /* Change the DTS state */ + hdts->State = HAL_DTS_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DTS peripheral. + * @note Deinitialization cannot be performed if the DTS configuration is locked. + * To unlock the configuration, perform a system reset. + * @param hdts DTS handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts) +{ + /* Check the DTS handle allocation */ + if (hdts == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance)); + + /* Set DTS_CFGR register to reset value */ + CLEAR_REG(hdts->Instance->CFGR1); + +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U) + if (hdts->MspDeInitCallback == NULL) + { + hdts->MspDeInitCallback = HAL_DTS_MspDeInit; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hdts->MspDeInitCallback(hdts); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_DTS_MspDeInit(hdts); +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ + + hdts->State = HAL_DTS_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initialize the DTS MSP. + * @param hdts DTS handle + * @retval None + */ +__weak void HAL_DTS_MspInit(DTS_HandleTypeDef *hdts) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdts); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DTS_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the DTS MSP. + * @param hdts DTS handle + * @retval None + */ +__weak void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdts); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DTS_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a user DTS callback to be used instead of the weak predefined callback. + * @param hdts DTS handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_DTS_MEAS_COMPLETE_CB_ID measure complete callback ID. + * @arg @ref HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID asynchronous measure complete callback ID. + * @arg @ref HAL_DTS_LOW_THRESHOLD_CB_ID low threshold detection callback ID. + * @arg @ref HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID asynchronous low threshold detection callback ID. + * @arg @ref HAL_DTS_HIGH_THRESHOLD_CB_ID high threshold detection callback ID. + * @arg @ref HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID asynchronous high threshold detection callback ID. + * @arg @ref HAL_DTS_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_DTS_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DTS_RegisterCallback(DTS_HandleTypeDef *hdts, + HAL_DTS_CallbackIDTypeDef CallbackID, + pDTS_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + if (pCallback == NULL) + { + /* Update status */ + status = HAL_ERROR; + } + else + { + if (hdts->State == HAL_DTS_STATE_READY) + { + switch (CallbackID) + { + case HAL_DTS_MEAS_COMPLETE_CB_ID : + hdts->EndCallback = pCallback; + break; + case HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID : + hdts->AsyncEndCallback = pCallback; + break; + case HAL_DTS_LOW_THRESHOLD_CB_ID : + hdts->LowCallback = pCallback; + break; + case HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID : + hdts->AsyncLowCallback = pCallback; + break; + case HAL_DTS_HIGH_THRESHOLD_CB_ID : + hdts->HighCallback = pCallback; + break; + case HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID : + hdts->AsyncHighCallback = pCallback; + break; + case HAL_DTS_MSPINIT_CB_ID : + hdts->MspInitCallback = pCallback; + break; + case HAL_DTS_MSPDEINIT_CB_ID : + hdts->MspDeInitCallback = pCallback; + break; + default : + /* Update status */ + status = HAL_ERROR; + break; + } + } + else if (hdts->State == HAL_DTS_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DTS_MSPINIT_CB_ID : + hdts->MspInitCallback = pCallback; + break; + case HAL_DTS_MSPDEINIT_CB_ID : + hdts->MspDeInitCallback = pCallback; + break; + default : + /* Update status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Unregister a user DTS callback. + * DTS callback is redirected to the weak predefined callback. + * @param hdts DTS handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_DTS_MEAS_COMPLETE_CB_ID measure complete callback ID. + * @arg @ref HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID asynchronous measure complete callback ID. + * @arg @ref HAL_DTS_LOW_THRESHOLD_CB_ID low threshold detection callback ID. + * @arg @ref HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID asynchronous low threshold detection callback ID. + * @arg @ref HAL_DTS_HIGH_THRESHOLD_CB_ID high threshold detection callback ID. + * @arg @ref HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID asynchronous high threshold detection callback ID. + * @arg @ref HAL_DTS_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_DTS_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DTS_UnRegisterCallback(DTS_HandleTypeDef *hdts, + HAL_DTS_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hdts->State == HAL_DTS_STATE_READY) + { + switch (CallbackID) + { + case HAL_DTS_MEAS_COMPLETE_CB_ID : + hdts->EndCallback = HAL_DTS_EndCallback; + break; + case HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID : + hdts->AsyncEndCallback = HAL_DTS_AsyncEndCallback; + break; + case HAL_DTS_LOW_THRESHOLD_CB_ID : + hdts->LowCallback = HAL_DTS_LowCallback; + break; + case HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID : + hdts->AsyncLowCallback = HAL_DTS_AsyncLowCallback; + break; + case HAL_DTS_HIGH_THRESHOLD_CB_ID : + hdts->HighCallback = HAL_DTS_HighCallback; + break; + case HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID : + hdts->AsyncHighCallback = HAL_DTS_AsyncHighCallback; + break; + case HAL_DTS_MSPINIT_CB_ID : + hdts->MspInitCallback = HAL_DTS_MspInit; + break; + case HAL_DTS_MSPDEINIT_CB_ID : + hdts->MspDeInitCallback = HAL_DTS_MspDeInit; + break; + default : + /* Update status */ + status = HAL_ERROR; + break; + } + } + else if (hdts->State == HAL_DTS_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DTS_MSPINIT_CB_ID : + hdts->MspInitCallback = HAL_DTS_MspInit; + break; + case HAL_DTS_MSPDEINIT_CB_ID : + hdts->MspDeInitCallback = HAL_DTS_MspDeInit; + break; + default : + /* Update status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update status */ + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup DTS_Exported_Functions_Group2 Start-Stop operation functions + * @brief Start-Stop operation functions. + * +@verbatim + ======================================================================================================================= + ##### DTS Start Stop operation functions ##### + ======================================================================================================================= + [..] This section provides functions allowing to: + (+) Start a DTS Sensor without interrupt. + (+) Stop a DTS Sensor without interrupt. + (+) Start a DTS Sensor with interrupt generation. + (+) Stop a DTS Sensor with interrupt generation. + +@endverbatim + * @{ + */ + +/** + * @brief Start the DTS sensor. + * @param hdts DTS handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DTS_Start(DTS_HandleTypeDef *hdts) +{ + uint32_t Ref_Time; + + /* Check the DTS handle allocation */ + if (hdts == NULL) + { + return HAL_ERROR; + } + + if (hdts->State == HAL_DTS_STATE_READY) + { + hdts->State = HAL_DTS_STATE_BUSY; + + /* Enable DTS sensor */ + __HAL_DTS_ENABLE(hdts); + + /* Get Start Tick*/ + Ref_Time = HAL_GetTick(); + + /* Wait till TS1_RDY flag is set */ + while (__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_RDY) == RESET) + { + if ((HAL_GetTick() - Ref_Time) > DTS_DELAY_STARTUP) + { + return HAL_TIMEOUT; + } + } + + if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE) + { + /* Start continuous measures */ + SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START); + + /* Ensure start is taken into account */ + HAL_Delay(TS_TIMEOUT_MS); + } + + hdts->State = HAL_DTS_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Stop the DTS Sensor. + * @param hdts DTS handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DTS_Stop(DTS_HandleTypeDef *hdts) +{ + /* Check the DTS handle allocation */ + if (hdts == NULL) + { + return HAL_ERROR; + } + + if (hdts->State == HAL_DTS_STATE_READY) + { + hdts->State = HAL_DTS_STATE_BUSY; + + if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE) + { + CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START); + } + + /* Disable the selected DTS sensor */ + __HAL_DTS_DISABLE(hdts); + + hdts->State = HAL_DTS_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Enable the interrupt(s) and start the DTS sensor + * @param hdts DTS handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts) +{ + uint32_t Ref_Time; + + /* Check the DTS handle allocation */ + if (hdts == NULL) + { + return HAL_ERROR; + } + + if (hdts->State == HAL_DTS_STATE_READY) + { + hdts->State = HAL_DTS_STATE_BUSY; + + /* On Asynchronous mode enable the asynchronous IT */ + if (hdts->Init.RefClock == DTS_REFCLKSEL_LSE) + { + __HAL_DTS_ENABLE_IT(hdts, DTS_IT_TS1_AITE | DTS_IT_TS1_AITL | DTS_IT_TS1_AITH); + } + else + { + /* Enable the IT(s) */ + __HAL_DTS_ENABLE_IT(hdts, DTS_IT_TS1_ITE | DTS_IT_TS1_ITL | DTS_IT_TS1_ITH); + } + + /* Enable the selected DTS sensor */ + __HAL_DTS_ENABLE(hdts); + + /* Get Start Tick*/ + Ref_Time = HAL_GetTick(); + + /* Wait till TS1_RDY flag is set */ + while (__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_RDY) == RESET) + { + if ((HAL_GetTick() - Ref_Time) > DTS_DELAY_STARTUP) + { + return HAL_TIMEOUT; + } + } + + if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE) + { + /* Start continuous measures */ + SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START); + + /* Ensure start is taken into account */ + HAL_Delay(TS_TIMEOUT_MS); + } + + hdts->State = HAL_DTS_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Disable the interrupt(s) and stop the DTS sensor. + * @param hdts DTS handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts) +{ + /* Check the DTS handle allocation */ + if (hdts == NULL) + { + return HAL_ERROR; + } + + if (hdts->State == HAL_DTS_STATE_READY) + { + hdts->State = HAL_DTS_STATE_BUSY; + + /* On Asynchronous mode disable the asynchronous IT */ + if (hdts->Init.RefClock == DTS_REFCLKSEL_LSE) + { + __HAL_DTS_DISABLE_IT(hdts, DTS_IT_TS1_AITE | DTS_IT_TS1_AITL | DTS_IT_TS1_AITH); + } + else + { + /* Disable the IT(s) */ + __HAL_DTS_DISABLE_IT(hdts, DTS_IT_TS1_ITE | DTS_IT_TS1_ITL | DTS_IT_TS1_ITH); + } + + if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE) + { + CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START); + } + + /* Disable the selected DTS sensor */ + __HAL_DTS_DISABLE(hdts); + + hdts->State = HAL_DTS_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Get temperature from DTS + * @param hdts DTS handle + * @param Temperature Temperature in deg C + * @note This function retrieves latest available measure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Temperature) +{ + uint32_t freq_meas; + uint32_t samples; + uint32_t t0_temp; + uint32_t t0_freq; + uint32_t ramp_coeff; + + if (hdts->State == HAL_DTS_STATE_READY) + { + hdts->State = HAL_DTS_STATE_BUSY; + + /* Get the total number of samples */ + samples = (hdts->Instance->DR & DTS_DR_TS1_MFREQ); + + if ((hdts->Init.SamplingTime == 0UL) || (samples == 0UL)) + { + hdts->State = HAL_DTS_STATE_READY; + return HAL_ERROR; + } + + if ((hdts->Init.RefClock) == DTS_REFCLKSEL_LSE) + { + /* Measured frequency On Hz */ + freq_meas = (LSE_VALUE * samples) / (hdts->Init.SamplingTime >> DTS_CFGR1_TS1_SMP_TIME_Pos); + } + else + { + /* Measured frequency On Hz */ + freq_meas = (HAL_RCC_GetPCLK1Freq() * (hdts->Init.SamplingTime >> DTS_CFGR1_TS1_SMP_TIME_Pos)) / samples; + } + + /* Read factory settings */ + t0_temp = hdts->Instance->T0VALR1 >> DTS_T0VALR1_TS1_T0_Pos; + + if (t0_temp == 0UL) + { + t0_temp = DTS_FACTORY_TEMPERATURE1; /* 30 deg C */ + } + else if (t0_temp == 1UL) + { + t0_temp = DTS_FACTORY_TEMPERATURE2; /* 130 deg C */ + } + else + { + hdts->State = HAL_DTS_STATE_READY; + return HAL_ERROR; + } + + t0_freq = (hdts->Instance->T0VALR1 & DTS_T0VALR1_TS1_FMT0) * 100UL; /* Hz */ + + ramp_coeff = hdts->Instance->RAMPVALR & DTS_RAMPVALR_TS1_RAMP_COEFF; /* deg C/Hz */ + + if (ramp_coeff == 0UL) + { + hdts->State = HAL_DTS_STATE_READY; + return HAL_ERROR; + } + + /* Figure out the temperature deg C */ + *Temperature = (int32_t)t0_temp + (((int32_t)freq_meas - (int32_t)t0_freq) / (int32_t)ramp_coeff); + + hdts->State = HAL_DTS_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief DTS sensor IRQ Handler. + * @param hdts DTS handle + * @retval None + */ +void HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts) +{ + /* Check end of measure Asynchronous IT */ + if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_AITE)) != RESET) + { + __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_AITE); + +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U) + hdts->AsyncEndCallback(hdts); +#else + HAL_DTS_AsyncEndCallback(hdts); +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ + } + + /* Check low threshold Asynchronous IT */ + if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_AITL)) != RESET) + { + __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_AITL); + +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U) + hdts->AsyncLowCallback(hdts); +#else + HAL_DTS_AsyncLowCallback(hdts); +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ + } + + /* Check high threshold Asynchronous IT */ + if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_AITH)) != RESET) + { + __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_AITH); + +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U) + hdts->AsyncHighCallback(hdts); +#else + HAL_DTS_AsyncHighCallback(hdts); +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ + } + + /* Check end of measure IT */ + if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_ITE)) != RESET) + { + __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_ITE); + +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U) + hdts->EndCallback(hdts); +#else + HAL_DTS_EndCallback(hdts); +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ + } + + /* Check low threshold IT */ + if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_ITL)) != RESET) + { + __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_ITL); + +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U) + hdts->LowCallback(hdts); +#else + HAL_DTS_LowCallback(hdts); +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ + } + + /* Check high threshold IT */ + if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_ITH)) != RESET) + { + __HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_ITH); + +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U) + hdts->HighCallback(hdts); +#else + HAL_DTS_HighCallback(hdts); +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DTS Sensor End measure callback. + * @param hdts DTS handle + * @retval None + */ +__weak void HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdts); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DTS_EndCallback should be implemented in the user file + */ +} + +/** + * @brief DTS Sensor low threshold measure callback. + * @param hdts DTS handle + * @retval None + */ +__weak void HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdts); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DTS_LowCallback should be implemented in the user file + */ +} + +/** + * @brief DTS Sensor high threshold measure callback. + * @param hdts DTS handle + * @retval None + */ +__weak void HAL_DTS_HighCallback(DTS_HandleTypeDef *hdts) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdts); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DTS_HighCallback should be implemented in the user file + */ +} + +/** + * @brief DTS Sensor asynchronous end measure callback. + * @param hdts DTS handle + * @retval None + */ +__weak void HAL_DTS_AsyncEndCallback(DTS_HandleTypeDef *hdts) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdts); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DTS_AsyncEndCallback should be implemented in the user file + */ +} + +/** + * @brief DTS Sensor asynchronous low threshold measure callback. + * @param hdts DTS handle + * @retval None + */ +__weak void HAL_DTS_AsyncLowCallback(DTS_HandleTypeDef *hdts) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdts); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DTS_AsyncLowCallback should be implemented in the user file + */ +} + +/** + * @brief DTS Sensor asynchronous high threshold measure callback. + * @param hdts DTS handle + * @retval None + */ +__weak void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdts); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DTS_AsyncHighCallback should be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DTS_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + ======================================================================================================================= + ##### Peripheral State functions ##### + ======================================================================================================================= + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the DTS handle state. + * @param hdts DTS handle + * @retval HAL state + */ +HAL_DTS_StateTypeDef HAL_DTS_GetState(const DTS_HandleTypeDef *hdts) +{ + /* Check the DTS handle allocation */ + if (hdts == NULL) + { + return HAL_DTS_STATE_RESET; + } + + /* Return DTS handle state */ + return hdts->State; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_DTS_MODULE_ENABLED */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_eth.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_eth.c new file mode 100644 index 00000000000..cb854cfe314 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_eth.c @@ -0,0 +1,3341 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_eth.c + * @author MCD Application Team + * @brief ETH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Ethernet (ETH) peripheral: + * + Initialization and deinitialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The ETH HAL driver can be used as follows: + + (#)Declare a ETH_HandleTypeDef handle structure, for example: + ETH_HandleTypeDef heth; + + (#)Fill parameters of Init structure in heth handle + + (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) + + (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: + (##) Enable the Ethernet interface clock using + (+++) __HAL_RCC_ETH1MAC_CLK_ENABLE() + (+++) __HAL_RCC_ETH1TX_CLK_ENABLE() + (+++) __HAL_RCC_ETH1RX_CLK_ENABLE() + + (##) Initialize the related GPIO clocks + (##) Configure Ethernet pinout + (##) Configure Ethernet NVIC interrupt (in Interrupt mode) + + (#) Ethernet data reception is asynchronous, so call the following API + to start the listening mode: + (##) HAL_ETH_Start(): + This API starts the MAC and DMA transmission and reception process, + without enabling end of transfer interrupts, in this mode user + has to poll for data reception by calling HAL_ETH_ReadData() + (##) HAL_ETH_Start_IT(): + This API starts the MAC and DMA transmission and reception process, + end of transfer interrupts are enabled in this mode, + HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received + + (#) When data is received user can call the following API to get received data: + (##) HAL_ETH_ReadData(): Read a received packet + + (#) For transmission path, two APIs are available: + (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode + (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode, + HAL_ETH_TxCpltCallback() will be executed when end of transfer occur + + (#) Communication with an external PHY device: + (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY + (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register + + (#) Configure the Ethernet MAC after ETH peripheral initialization + (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef + (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef + + (#) Configure the Ethernet DMA after ETH peripheral initialization + (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef + (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef + + (#) Configure the Ethernet PTP after ETH peripheral initialization + (##) Define HAL_ETH_USE_PTP to use PTP APIs. + (##) HAL_ETH_PTP_GetConfig(): Get PTP actual configuration into ETH_PTP_ConfigTypeDef + (##) HAL_ETH_PTP_SetConfig(): Set PTP configuration based on ETH_PTP_ConfigTypeDef + (##) HAL_ETH_PTP_GetTime(): Get Seconds and Nanoseconds for the Ethernet PTP registers + (##) HAL_ETH_PTP_SetTime(): Set Seconds and Nanoseconds for the Ethernet PTP registers + (##) HAL_ETH_PTP_AddTimeOffset(): Add Seconds and Nanoseconds offset for the Ethernet PTP registers + (##) HAL_ETH_PTP_InsertTxTimestamp(): Insert Timestamp in transmission + (##) HAL_ETH_PTP_GetTxTimestamp(): Get transmission timestamp + (##) HAL_ETH_PTP_GetRxTimestamp(): Get reception timestamp + + -@- The ARP offload feature is not supported in this driver. + + -@- The PTP offload feature is not supported in this driver. + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_ETH_RegisterCallback() to register an interrupt callback. + + Function HAL_ETH_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) PMTCallback : Power Management Callback + (+) EEECallback : EEE Callback. + (+) WakeUpCallback : Wake UP Callback + (+) MspInitCallback : MspInit Callback. + (+) MspDeInitCallback: MspDeInit Callback. + + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + For specific callbacks RxAllocateCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterRxAllocateCallback(). + + For specific callbacks RxLinkCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterRxLinkCallback(). + + For specific callbacks TxFreeCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterTxFreeCallback(). + + For specific callbacks TxPtpCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterTxPtpCallback(). + + Use function HAL_ETH_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) PMTCallback : Power Management Callback + (+) EEECallback : EEE Callback. + (+) WakeUpCallback : Wake UP Callback + (+) MspInitCallback : MspInit Callback. + (+) MspDeInitCallback: MspDeInit Callback. + + For specific callbacks RxAllocateCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterRxAllocateCallback(). + + For specific callbacks RxLinkCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterRxLinkCallback(). + + For specific callbacks TxFreeCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterTxFreeCallback(). + + For specific callbacks TxPtpCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterTxPtpCallback(). + + By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_ETH_TxCpltCallback(), HAL_ETH_RxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_ETH_Init/ HAL_ETH_DeInit only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ HAL_ETH_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_ETH_RegisterCallback() before calling HAL_ETH_DeInit + or HAL_ETH_Init function. + + When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#ifdef HAL_ETH_MODULE_ENABLED + +#if defined(ETH) + +/** @defgroup ETH ETH + * @brief ETH HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup ETH_Private_Constants ETH Private Constants + * @{ + */ +#define ETH_MACCR_MASK 0xFFFB7F7CU +#define ETH_MACECR_MASK 0x3F077FFFU +#define ETH_MACPFR_MASK 0x800007FFU +#define ETH_MACWTR_MASK 0x0000010FU +#define ETH_MACTFCR_MASK 0xFFFF00F2U +#define ETH_MACRFCR_MASK 0x00000003U +#define ETH_MTLTQOMR_MASK 0x00000072U +#define ETH_MTLRQOMR_MASK 0x0000007BU + +#define ETH_DMAMR_MASK 0x00007802U +#define ETH_DMASBMR_MASK 0x0000D001U +#define ETH_DMACCR_MASK 0x00013FFFU +#define ETH_DMACTCR_MASK 0x003F1010U +#define ETH_DMACRCR_MASK 0x803F0000U +#define ETH_MACPCSR_MASK (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \ + ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \ + ETH_MACPCSR_RWKPFE) + +/* Timeout values */ +#define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \ + ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\ + ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE)) + +#define ETH_MACTSCR_MASK 0x0087FF2FU + +#define ETH_MACSTSUR_VALUE 0xFFFFFFFFU +#define ETH_MACSTNUR_VALUE 0xBB9ACA00U +#define ETH_SEGMENT_SIZE_DEFAULT 0x218U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ETH_Private_Macros ETH Private Macros + * @{ + */ +/* Helper macros for TX descriptor handling */ +#define INCR_TX_DESC_INDEX(inx, offset) do {\ + (inx) += (offset);\ + if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\ + (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\ + } while (0) + +/* Helper macros for RX descriptor handling */ +#define INCR_RX_DESC_INDEX(inx, offset) do {\ + (inx) += (offset);\ + if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\ + (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\ + } while (0) +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup ETH_Private_Functions ETH Private Functions + * @{ + */ +static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf); +static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf); +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth); +static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth); +static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth); +static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig, + uint32_t ItMode); +static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup ETH_Exported_Functions ETH Exported Functions + * @{ + */ + +/** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the ETH peripheral: + + (+) User must Implement HAL_ETH_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO and NVIC ). + + (+) Call the function HAL_ETH_Init() to configure the selected device with + the selected configuration: + (++) MAC address + (++) Media interface (MII or RMII) + (++) Rx DMA Descriptors Tab + (++) Tx DMA Descriptors Tab + (++) Length of Rx Buffers + + (+) Call the function HAL_ETH_DeInit() to restore the default configuration + of the selected ETH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the Ethernet peripheral registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) +{ + uint32_t tickstart; + + if (heth == NULL) + { + return HAL_ERROR; + } + if (heth->gState == HAL_ETH_STATE_RESET) + { + heth->gState = HAL_ETH_STATE_BUSY; + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + + ETH_InitCallbacksToDefault(heth); + + if (heth->MspInitCallback == NULL) + { + heth->MspInitCallback = HAL_ETH_MspInit; + } + + /* Init the low level hardware */ + heth->MspInitCallback(heth); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC. */ + HAL_ETH_MspInit(heth); + +#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ + } + + __HAL_RCC_SBS_CLK_ENABLE(); + + if (heth->Init.MediaInterface == HAL_ETH_MII_MODE) + { + HAL_SBS_ConfigEthernetPHY(SBS_ETHERNET_PHY_GMII_OR_MII); + } + else + { + HAL_SBS_ConfigEthernetPHY(SBS_ETHERNET_PHY_RMII); + } + + /* Dummy read to sync with ETH */ + (void)SBS->PMCR; + + /* Ethernet Software reset */ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for software reset */ + while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U) + { + if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT)) + { + /* Set Error Code */ + heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT; + /* Set State as Error */ + heth->gState = HAL_ETH_STATE_ERROR; + /* Return Error */ + return HAL_ERROR; + } + } + + /*------------------ MDIO CSR Clock Range Configuration --------------------*/ + HAL_ETH_SetMDIOClockRange(heth); + + /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/ + WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U)); + + /*------------------ MAC, MTL and DMA default Configuration ----------------*/ + ETH_MACDMAConfig(heth); + + /* SET DSL to 64 bit */ + MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT); + + /* Set Receive Buffers Length (must be a multiple of 4) */ + if ((heth->Init.RxBuffLen % 0x4U) != 0x0U) + { + /* Set Error Code */ + heth->ErrorCode = HAL_ETH_ERROR_PARAM; + /* Set State as Error */ + heth->gState = HAL_ETH_STATE_ERROR; + /* Return Error */ + return HAL_ERROR; + } + else + { + MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ((heth->Init.RxBuffLen) << 1)); + } + + /*------------------ DMA Tx Descriptors Configuration ----------------------*/ + ETH_DMATxDescListInit(heth); + + /*------------------ DMA Rx Descriptors Configuration ----------------------*/ + ETH_DMARxDescListInit(heth); + + /*--------------------- ETHERNET MAC Address Configuration ------------------*/ + /* Set MAC addr bits 32 to 47 */ + heth->Instance->MACA0HR = (((uint32_t)(heth->Init.MACAddr[5]) << 8) | (uint32_t)heth->Init.MACAddr[4]); + /* Set MAC addr bits 0 to 31 */ + heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) | + ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]); + + /* Disable Rx MMC Interrupts */ + SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \ + ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM); + + /* Disable Tx MMC Interrupts */ + SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \ + ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM); + + heth->ErrorCode = HAL_ETH_ERROR_NONE; + heth->gState = HAL_ETH_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the ETH peripheral. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) +{ + /* Set the ETH peripheral state to BUSY */ + heth->gState = HAL_ETH_STATE_BUSY; + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + + if (heth->MspDeInitCallback == NULL) + { + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + } + /* DeInit the low level hardware */ + heth->MspDeInitCallback(heth); +#else + + /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ + HAL_ETH_MspDeInit(heth); + +#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ + + /* Set ETH HAL state to Disabled */ + heth->gState = HAL_ETH_STATE_RESET; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the ETH MSP. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes ETH MSP. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ETH Callback + * To be used instead of the weak predefined callback + * @param heth eth handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID + * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID + * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID + * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, + pETH_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (heth->gState == HAL_ETH_STATE_READY) + { + switch (CallbackID) + { + case HAL_ETH_TX_COMPLETE_CB_ID : + heth->TxCpltCallback = pCallback; + break; + + case HAL_ETH_RX_COMPLETE_CB_ID : + heth->RxCpltCallback = pCallback; + break; + + case HAL_ETH_ERROR_CB_ID : + heth->ErrorCallback = pCallback; + break; + + case HAL_ETH_PMT_CB_ID : + heth->PMTCallback = pCallback; + break; + + case HAL_ETH_EEE_CB_ID : + heth->EEECallback = pCallback; + break; + + case HAL_ETH_WAKEUP_CB_ID : + heth->WakeUpCallback = pCallback; + break; + + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = pCallback; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (heth->gState == HAL_ETH_STATE_RESET) + { + switch (CallbackID) + { + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = pCallback; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an ETH Callback + * ETH callback is redirected to the weak predefined callback + * @param heth eth handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID + * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID + * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID + * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (heth->gState == HAL_ETH_STATE_READY) + { + switch (CallbackID) + { + case HAL_ETH_TX_COMPLETE_CB_ID : + heth->TxCpltCallback = HAL_ETH_TxCpltCallback; + break; + + case HAL_ETH_RX_COMPLETE_CB_ID : + heth->RxCpltCallback = HAL_ETH_RxCpltCallback; + break; + + case HAL_ETH_ERROR_CB_ID : + heth->ErrorCallback = HAL_ETH_ErrorCallback; + break; + + case HAL_ETH_PMT_CB_ID : + heth->PMTCallback = HAL_ETH_PMTCallback; + break; + + case HAL_ETH_EEE_CB_ID : + heth->EEECallback = HAL_ETH_EEECallback; + break; + + case HAL_ETH_WAKEUP_CB_ID : + heth->WakeUpCallback = HAL_ETH_WakeUpCallback; + break; + + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = HAL_ETH_MspInit; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (heth->gState == HAL_ETH_STATE_RESET) + { + switch (CallbackID) + { + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = HAL_ETH_MspInit; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group2 IO operation functions + * @brief ETH Transmit and Receive functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the ETH + data transfer. + +@endverbatim + * @{ + */ + +/** + * @brief Enables Ethernet MAC and DMA reception and transmission + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) +{ + if (heth->gState == HAL_ETH_STATE_READY) + { + heth->gState = HAL_ETH_STATE_BUSY; + + /* Set number of descriptors to build */ + heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; + + /* Build all descriptors */ + ETH_UpdateDescriptor(heth); + + /* Enable the MAC transmission */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + /* Enable the MAC reception */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + + /* Set the Flush Transmit FIFO bit */ + SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); + + /* Enable the DMA transmission */ + SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST); + + /* Enable the DMA reception */ + SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR); + + /* Clear Tx and Rx process stopped flags */ + heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS); + + heth->gState = HAL_ETH_STATE_STARTED; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enables Ethernet MAC and DMA reception/transmission in Interrupt mode + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) +{ + if (heth->gState == HAL_ETH_STATE_READY) + { + heth->gState = HAL_ETH_STATE_BUSY; + + /* save IT mode to ETH Handle */ + heth->RxDescList.ItMode = 1U; + + /* Set number of descriptors to build */ + heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; + + /* Build all descriptors */ + ETH_UpdateDescriptor(heth); + + /* Enable the DMA transmission */ + SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST); + + /* Enable the DMA reception */ + SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR); + + /* Clear Tx and Rx process stopped flags */ + heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS); + + /* Set the Flush Transmit FIFO bit */ + SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); + + /* Enable the MAC transmission */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + /* Enable the MAC reception */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + + /* Enable ETH DMA interrupts: + - Tx complete interrupt + - Rx complete interrupt + - Fatal bus interrupt + */ + __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE | + ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE)); + + heth->gState = HAL_ETH_STATE_STARTED; + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Stop Ethernet MAC and DMA reception/transmission + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) +{ + if (heth->gState == HAL_ETH_STATE_STARTED) + { + /* Set the ETH peripheral state to BUSY */ + heth->gState = HAL_ETH_STATE_BUSY; + + /* Disable the DMA transmission */ + CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST); + + /* Disable the DMA reception */ + CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR); + + /* Disable the MAC reception */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + + /* Set the Flush Transmit FIFO bit */ + SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); + + /* Disable the MAC transmission */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + heth->gState = HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Stop Ethernet MAC and DMA reception/transmission in Interrupt mode + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) +{ + ETH_DMADescTypeDef *dmarxdesc; + uint32_t descindex; + + if (heth->gState == HAL_ETH_STATE_STARTED) + { + /* Set the ETH peripheral state to BUSY */ + heth->gState = HAL_ETH_STATE_BUSY; + + /* Disable interrupts: + - Tx complete interrupt + - Rx complete interrupt + - Fatal bus interrupt + */ + __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE | + ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE)); + + /* Disable the DMA transmission */ + CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST); + + /* Disable the DMA reception */ + CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR); + + /* Disable the MAC reception */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + + /* Set the Flush Transmit FIFO bit */ + SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); + + /* Disable the MAC transmission */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + /* Clear IOC bit to all Rx descriptors */ + for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++) + { + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex]; + CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC); + } + + heth->RxDescList.ItMode = 0U; + + heth->gState = HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sends an Ethernet Packet in polling mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pTxConfig: Hold the configuration of packet to be transmitted + * @param Timeout: timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout) +{ + uint32_t tickstart; + ETH_DMADescTypeDef *dmatxdesc; + + if (pTxConfig == NULL) + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + return HAL_ERROR; + } + + if (heth->gState == HAL_ETH_STATE_STARTED) + { + /* Config DMA Tx descriptor by Tx Packet info */ + if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE) + { + /* Set the ETH error code */ + heth->ErrorCode |= HAL_ETH_ERROR_BUSY; + return HAL_ERROR; + } + + /* Ensure completion of descriptor preparation before transmission start */ + __DSB(); + + dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc]; + + /* Incr current tx desc index */ + INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); + + /* Start transmission */ + /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ + WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc])); + + tickstart = HAL_GetTick(); + + /* Wait for data to be transmitted or timeout occurred */ + while ((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET) + { + if ((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET) + { + heth->ErrorCode |= HAL_ETH_ERROR_DMA; + heth->DMAErrorCode = heth->Instance->DMACSR; + /* Return function status */ + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT; + /* Clear TX descriptor so that we can proceed */ + dmatxdesc->DESC3 = (ETH_DMATXNDESCWBF_FD | ETH_DMATXNDESCWBF_LD); + return HAL_ERROR; + } + } + } + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sends an Ethernet Packet in interrupt mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pTxConfig: Hold the configuration of packet to be transmitted + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig) +{ + if (pTxConfig == NULL) + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + return HAL_ERROR; + } + + if (heth->gState == HAL_ETH_STATE_STARTED) + { + /* Save the packet pointer to release. */ + heth->TxDescList.CurrentPacketAddress = (uint32_t *)pTxConfig->pData; + + /* Config DMA Tx descriptor by Tx Packet info */ + if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE) + { + heth->ErrorCode |= HAL_ETH_ERROR_BUSY; + return HAL_ERROR; + } + + /* Ensure completion of descriptor preparation before transmission start */ + __DSB(); + + /* Incr current tx desc index */ + INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); + + /* Start transmission */ + /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ + WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc])); + + return HAL_OK; + + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Read a received packet. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pAppBuff: Pointer to an application buffer to receive the packet. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) +{ + uint32_t descidx; + ETH_DMADescTypeDef *dmarxdesc; + uint32_t desccnt = 0U; + uint32_t desccntmax; + uint32_t bufflength; + uint8_t rxdataready = 0U; + + if (pAppBuff == NULL) + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + return HAL_ERROR; + } + + if (heth->gState != HAL_ETH_STATE_STARTED) + { + return HAL_ERROR; + } + + descidx = heth->RxDescList.RxDescIdx; + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt; + + /* Check if descriptor is not owned by DMA */ + while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax) + && (rxdataready == 0U)) + { + if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_CTXT) != (uint32_t)RESET) + { + /* Get timestamp high */ + heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC1; + /* Get timestamp low */ + heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC0; + } + if ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL)) + { + /* Check if first descriptor */ + if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) + { + heth->RxDescList.RxDescCnt = 0; + heth->RxDescList.RxDataLength = 0; + } + + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength; + + /* Check if last descriptor */ + if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET) + { + /* Save Last descriptor index */ + heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC3; + + /* Packet ready */ + rxdataready = 1; + } + + /* Link data */ +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Link callback*/ + heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + (uint8_t *)dmarxdesc->BackupAddr0, bufflength); +#else + /* Link callback */ + HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + heth->RxDescList.RxDescCnt++; + heth->RxDescList.RxDataLength += bufflength; + + /* Clear buffer pointer */ + dmarxdesc->BackupAddr0 = 0; + } + + /* Increment current rx descriptor index */ + INCR_RX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccnt++; + } + + heth->RxDescList.RxBuildDescCnt += desccnt; + if ((heth->RxDescList.RxBuildDescCnt) != 0U) + { + /* Update Descriptors */ + ETH_UpdateDescriptor(heth); + } + + heth->RxDescList.RxDescIdx = descidx; + + if (rxdataready == 1U) + { + /* Return received packet */ + *pAppBuff = heth->RxDescList.pRxStart; + /* Reset first element */ + heth->RxDescList.pRxStart = NULL; + + return HAL_OK; + } + + /* Packet not ready */ + return HAL_ERROR; +} + +/** + * @brief This function gives back Rx Desc of the last received Packet + * to the DMA, so ETH DMA will be able to use these descriptors + * to receive next Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) +{ + uint32_t descidx; + uint32_t tailidx; + uint32_t desccount; + ETH_DMADescTypeDef *dmarxdesc; + uint8_t *buff = NULL; + uint8_t allocStatus = 1U; + + descidx = heth->RxDescList.RxBuildDescIdx; + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccount = heth->RxDescList.RxBuildDescCnt; + + while ((desccount > 0U) && (allocStatus != 0U)) + { + /* Check if a buffer's attached the descriptor */ + if (READ_REG(dmarxdesc->BackupAddr0) == 0U) + { + /* Get a new buffer. */ +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Allocate callback*/ + heth->rxAllocateCallback(&buff); +#else + /* Allocate callback */ + HAL_ETH_RxAllocateCallback(&buff); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + if (buff == NULL) + { + allocStatus = 0U; + } + else + { + WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff); + WRITE_REG(dmarxdesc->DESC0, (uint32_t)buff); + } + } + + if (allocStatus != 0U) + { + + if (heth->RxDescList.ItMode != 0U) + { + WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V | ETH_DMARXNDESCRF_IOC); + } + else + { + WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V); + } + + /* Increment current rx descriptor index */ + INCR_RX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccount--; + } + } + + if (heth->RxDescList.RxBuildDescCnt != desccount) + { + /* Set the tail pointer index */ + tailidx = (descidx + 1U) % ETH_RX_DESC_CNT; + + /* DMB instruction to avoid race condition */ + __DMB(); + + /* Set the Tail pointer address */ + WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (tailidx)))); + + heth->RxDescList.RxBuildDescIdx = descidx; + heth->RxDescList.RxBuildDescCnt = desccount; + } +} + +/** + * @brief Register the Rx alloc callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param rxAllocateCallback: pointer to function to alloc buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, + pETH_rxAllocateCallbackTypeDef rxAllocateCallback) +{ + if (rxAllocateCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + + /* Set function to allocate buffer */ + heth->rxAllocateCallback = rxAllocateCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Rx alloc callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; + + return HAL_OK; +} + +/** + * @brief Rx Allocate callback. + * @param buff: pointer to allocated buffer + * @retval None + */ +__weak void HAL_ETH_RxAllocateCallback(uint8_t **buff) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_RxAllocateCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Link callback. + * @param pStart: pointer to packet start + * @param pEnd: pointer to packet end + * @param buff: pointer to received data + * @param Length: received data length + * @retval None + */ +__weak void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(pStart); + UNUSED(pEnd); + UNUSED(buff); + UNUSED(Length); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_RxLinkCallback could be implemented in the user file + */ +} + +/** + * @brief Set the Rx link data function. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param rxLinkCallback: pointer to function to link data + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback) +{ + if (rxLinkCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + + /* Set function to link data */ + heth->rxLinkCallback = rxLinkCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Rx link callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->rxLinkCallback = HAL_ETH_RxLinkCallback; + + return HAL_OK; +} + +/** + * @brief Get the error state of the last received packet. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pErrorCode: pointer to uint32_t to hold the error code + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode) +{ + /* Get error bits. */ + *pErrorCode = READ_BIT(heth->RxDescList.pRxLastRxDesc, ETH_DMARXNDESCWBF_ERRORS_MASK); + + return HAL_OK; +} + +/** + * @brief Set the Tx free function. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txFreeCallback: pointer to function to release the packet + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback) +{ + if (txFreeCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + + /* Set function to free transmmitted packet */ + heth->txFreeCallback = txFreeCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Tx free callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->txFreeCallback = HAL_ETH_TxFreeCallback; + + return HAL_OK; +} + +/** + * @brief Tx Free callback. + * @param buff: pointer to buffer to free + * @retval None + */ +__weak void HAL_ETH_TxFreeCallback(uint32_t *buff) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxFreeCallback could be implemented in the user file + */ +} + +/** + * @brief Release transmitted Tx packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t numOfBuf = dmatxdesclist->BuffersInUse; + uint32_t idx = dmatxdesclist->releaseIndex; + uint8_t pktTxStatus = 1U; + uint8_t pktInUse; +#ifdef HAL_ETH_USE_PTP + ETH_TimeStampTypeDef *timestamp = &heth->TxTimestamp; +#endif /* HAL_ETH_USE_PTP */ + + /* Loop through buffers in use. */ + while ((numOfBuf != 0U) && (pktTxStatus != 0U)) + { + pktInUse = 1U; + numOfBuf--; + /* If no packet, just examine the next packet. */ + if (dmatxdesclist->PacketAddress[idx] == NULL) + { + /* No packet in use, skip to next. */ + INCR_TX_DESC_INDEX(idx, 1U); + pktInUse = 0U; + } + + if (pktInUse != 0U) + { + /* Determine if the packet has been transmitted. */ + if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCRF_OWN) == 0U) + { +#ifdef HAL_ETH_USE_PTP + + /* Disable Ptp transmission */ + CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, (0x40000000U)); + + if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_LD) + && (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_TTSS)) + { + /* Get timestamp low */ + timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0; + /* Get timestamp high */ + timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC1; + } + else + { + timestamp->TimeStampHigh = timestamp->TimeStampLow = UINT32_MAX; + } +#endif /* HAL_ETH_USE_PTP */ + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered callbacks*/ +#ifdef HAL_ETH_USE_PTP + /* Handle Ptp */ + if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX) + { + heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); + } +#endif /* HAL_ETH_USE_PTP */ + /* Release the packet. */ + heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]); +#else + /* Call callbacks */ +#ifdef HAL_ETH_USE_PTP + /* Handle Ptp */ + if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX) + { + HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); + } +#endif /* HAL_ETH_USE_PTP */ + /* Release the packet. */ + HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Clear the entry in the in-use array. */ + dmatxdesclist->PacketAddress[idx] = NULL; + + /* Update the transmit relesae index and number of buffers in use. */ + INCR_TX_DESC_INDEX(idx, 1U); + dmatxdesclist->BuffersInUse = numOfBuf; + dmatxdesclist->releaseIndex = idx; + } + else + { + /* Get out of the loop! */ + pktTxStatus = 0U; + } + } + } + return HAL_OK; +} + +#ifdef HAL_ETH_USE_PTP +/** + * @brief Set the Ethernet PTP configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains + * the configuration information for PTP + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig) +{ + uint32_t tmpTSCR; + ETH_TimeTypeDef time; + + if (ptpconfig == NULL) + { + return HAL_ERROR; + } + + tmpTSCR = ptpconfig->Timestamp | + ((uint32_t)ptpconfig->TimestampUpdate << ETH_MACTSCR_TSUPDT_Pos) | + ((uint32_t)ptpconfig->TimestampAll << ETH_MACTSCR_TSENALL_Pos) | + ((uint32_t)ptpconfig->TimestampRolloverMode << ETH_MACTSCR_TSCTRLSSR_Pos) | + ((uint32_t)ptpconfig->TimestampV2 << ETH_MACTSCR_TSVER2ENA_Pos) | + ((uint32_t)ptpconfig->TimestampEthernet << ETH_MACTSCR_TSIPENA_Pos) | + ((uint32_t)ptpconfig->TimestampIPv6 << ETH_MACTSCR_TSIPV6ENA_Pos) | + ((uint32_t)ptpconfig->TimestampIPv4 << ETH_MACTSCR_TSIPV4ENA_Pos) | + ((uint32_t)ptpconfig->TimestampEvent << ETH_MACTSCR_TSEVNTENA_Pos) | + ((uint32_t)ptpconfig->TimestampMaster << ETH_MACTSCR_TSMSTRENA_Pos) | + ((uint32_t)ptpconfig->TimestampSnapshots << ETH_MACTSCR_SNAPTYPSEL_Pos) | + ((uint32_t)ptpconfig->TimestampFilter << ETH_MACTSCR_TSENMACADDR_Pos) | + ((uint32_t)ptpconfig->TimestampChecksumCorrection << ETH_MACTSCR_CSC_Pos) | + ((uint32_t)ptpconfig->TimestampStatusMode << ETH_MACTSCR_TXTSSTSM_Pos); + + /* Write to MACTSCR */ + MODIFY_REG(heth->Instance->MACTSCR, ETH_MACTSCR_MASK, tmpTSCR); + + /* Enable Timestamp */ + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENA); + WRITE_REG(heth->Instance->MACSSIR, ptpconfig->TimestampSubsecondInc); + WRITE_REG(heth->Instance->MACTSAR, ptpconfig->TimestampAddend); + + /* Enable Timestamp */ + if (ptpconfig->TimestampAddendUpdate == ENABLE) + { + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSADDREG); + while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0) + { + + } + } + + /* Ptp Init */ + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT); + + /* Set PTP Configuration done */ + heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED; + + /* Set Seconds */ + time.Seconds = heth->Instance->MACSTSR; + /* Set NanoSeconds */ + time.NanoSeconds = heth->Instance->MACSTNR; + + HAL_ETH_PTP_SetTime(heth, &time); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Get the Ethernet PTP configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains + * the configuration information for PTP + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig) +{ + if (ptpconfig == NULL) + { + return HAL_ERROR; + } + ptpconfig->Timestamp = READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENA); + ptpconfig->TimestampUpdate = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSCFUPDT) >> ETH_MACTSCR_TSUPDT_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampAll = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSENALL) >> ETH_MACTSCR_TSENALL_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampRolloverMode = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSCTRLSSR) >> ETH_MACTSCR_TSCTRLSSR_Pos) > 0U) + ? ENABLE : DISABLE; + ptpconfig->TimestampV2 = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSVER2ENA) >> ETH_MACTSCR_TSVER2ENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampEthernet = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSIPENA) >> ETH_MACTSCR_TSIPENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampIPv6 = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSIPV6ENA) >> ETH_MACTSCR_TSIPV6ENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampIPv4 = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSIPV4ENA) >> ETH_MACTSCR_TSIPV4ENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampEvent = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSEVNTENA) >> ETH_MACTSCR_TSEVNTENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampMaster = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSMSTRENA) >> ETH_MACTSCR_TSMSTRENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampSnapshots = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_SNAPTYPSEL) >> ETH_MACTSCR_SNAPTYPSEL_Pos) > 0U) + ? ENABLE : DISABLE; + ptpconfig->TimestampFilter = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSENMACADDR) >> ETH_MACTSCR_TSENMACADDR_Pos) > 0U) + ? ENABLE : DISABLE; + ptpconfig->TimestampChecksumCorrection = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_CSC) >> ETH_MACTSCR_CSC_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampStatusMode = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TXTSSTSM) >> ETH_MACTSCR_TXTSSTSM_Pos) > 0U) + ? ENABLE : DISABLE; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set Seconds and Nanoseconds for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param time: pointer to a ETH_TimeTypeDef structure that contains + * time to set + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) + { + /* Set Seconds */ + heth->Instance->MACSTSUR = time->Seconds; + + /* Set NanoSeconds */ + heth->Instance->MACSTNUR = time->NanoSeconds; + + /* the system time is updated */ + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Get Seconds and Nanoseconds for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param time: pointer to a ETH_TimeTypeDef structure that contains + * time to get + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) + { + /* Get Seconds */ + time->Seconds = heth->Instance->MACSTSR; + /* Get NanoSeconds */ + time->NanoSeconds = heth->Instance->MACSTNR; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Update time for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timeoffset: pointer to a ETH_PtpUpdateTypeDef structure that contains + * the time update information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, + ETH_TimeTypeDef *timeoffset) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) + { + if (ptpoffsettype == HAL_ETH_PTP_NEGATIVE_UPDATE) + { + /* Set Seconds update */ + heth->Instance->MACSTSUR = ETH_MACSTSUR_VALUE - timeoffset->Seconds + 1U; + + if (READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCTRLSSR) == ETH_MACTSCR_TSCTRLSSR) + { + /* Set nanoSeconds update */ + heth->Instance->MACSTNUR = ETH_MACSTNUR_VALUE - timeoffset->NanoSeconds; + } + else + { + /* Set nanoSeconds update */ + heth->Instance->MACSTNUR = ETH_MACSTSUR_VALUE - timeoffset->NanoSeconds + 1U; + } + } + else + { + /* Set Seconds update */ + heth->Instance->MACSTSUR = timeoffset->Seconds; + /* Set nanoSeconds update */ + heth->Instance->MACSTNUR = timeoffset->NanoSeconds; + } + + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Insert Timestamp in transmission. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t descidx = dmatxdesclist->CurTxDesc; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) + { + /* Enable Time Stamp transmission */ + SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_TTSE); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Get transmission timestamp. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains + * transmission timestamp + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t idx = dmatxdesclist->releaseIndex; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx]; + + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) + { + /* Get timestamp low */ + timestamp->TimeStampLow = dmatxdesc->DESC0; + /* Get timestamp high */ + timestamp->TimeStampHigh = dmatxdesc->DESC1; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Get receive timestamp. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains + * receive timestamp + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) + { + /* Get timestamp low */ + timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow; + /* Get timestamp high */ + timestamp->TimeStampHigh = heth->RxDescList.TimeStamp.TimeStampHigh; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Register the Tx Ptp callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txPtpCallback: Function to handle Ptp transmission + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback) +{ + if (txPtpCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + /* Set Function to handle Tx Ptp */ + heth->txPtpCallback = txPtpCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Tx Ptp callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->txPtpCallback = HAL_ETH_TxPtpCallback; + + return HAL_OK; +} + +/** + * @brief Tx Ptp callback. + * @param buff: pointer to application buffer + * @param timestamp: pointer to ETH_TimeStampTypeDef structure that contains + * transmission timestamp + * @retval None + */ +__weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxPtpCallback could be implemented in the user file + */ +} +#endif /* HAL_ETH_USE_PTP */ + +/** + * @brief This function handles ETH interrupt request. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) +{ + uint32_t mac_flag = READ_REG(heth->Instance->MACISR); + uint32_t dma_flag = READ_REG(heth->Instance->DMACSR); + uint32_t dma_itsource = READ_REG(heth->Instance->DMACIER); + uint32_t exti_flag = READ_REG(EXTI->PR2); + + /* Packet received */ + if (((dma_flag & ETH_DMACSR_RI) != 0U) && ((dma_itsource & ETH_DMACIER_RIE) != 0U)) + { + /* Clear the Eth DMA Rx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Receive complete callback*/ + heth->RxCpltCallback(heth); +#else + /* Receive complete callback */ + HAL_ETH_RxCpltCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + + /* Packet transmitted */ + if (((dma_flag & ETH_DMACSR_TI) != 0U) && ((dma_itsource & ETH_DMACIER_TIE) != 0U)) + { + /* Clear the Eth DMA Tx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Transmit complete callback*/ + heth->TxCpltCallback(heth); +#else + /* Transfer complete callback */ + HAL_ETH_TxCpltCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + + /* ETH DMA Error */ + if (((dma_flag & ETH_DMACSR_AIS) != 0U) && ((dma_itsource & ETH_DMACIER_AIE) != 0U)) + { + heth->ErrorCode |= HAL_ETH_ERROR_DMA; + /* if fatal bus error occurred */ + if ((dma_flag & ETH_DMACSR_FBE) != 0U) + { + /* Get DMA error code */ + heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS)); + + /* Disable all interrupts */ + __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE); + + /* Set HAL state to ERROR */ + heth->gState = HAL_ETH_STATE_ERROR; + } + else + { + /* Get DMA error status */ + heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | + ETH_DMACSR_RBU | ETH_DMACSR_AIS)); + + /* Clear the interrupt summary flag */ + __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | + ETH_DMACSR_RBU | ETH_DMACSR_AIS)); + } +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered Error callback*/ + heth->ErrorCallback(heth); +#else + /* Ethernet DMA Error callback */ + HAL_ETH_ErrorCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + + /* ETH MAC Error IT */ + if (((mac_flag & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \ + ((mac_flag & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE)) + { + heth->ErrorCode |= HAL_ETH_ERROR_MAC; + + /* Get MAC Rx Tx status and clear Status register pending bit */ + heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR); + + heth->gState = HAL_ETH_STATE_ERROR; + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered Error callback*/ + heth->ErrorCallback(heth); +#else + /* Ethernet Error callback */ + HAL_ETH_ErrorCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + heth->MACErrorCode = (uint32_t)(0x0U); + } + + /* ETH PMT IT */ + if ((mac_flag & ETH_MAC_PMT_IT) != 0U) + { + /* Get MAC Wake-up source and clear the status register pending bit */ + heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD)); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered PMT callback*/ + heth->PMTCallback(heth); +#else + /* Ethernet PMT callback */ + HAL_ETH_PMTCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + heth->MACWakeUpEvent = (uint32_t)(0x0U); + } + + /* ETH EEE IT */ + if ((mac_flag & ETH_MAC_LPI_IT) != 0U) + { + /* Get MAC LPI interrupt source and clear the status register pending bit */ + heth->MACLPIEvent = READ_BIT(heth->Instance->MACLCSR, 0x0000000FU); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered EEE callback*/ + heth->EEECallback(heth); +#else + /* Ethernet EEE callback */ + HAL_ETH_EEECallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + heth->MACLPIEvent = (uint32_t)(0x0U); + } + + /* check ETH WAKEUP exti flag */ + if ((exti_flag & ETH_WAKEUP_EXTI_LINE) != 0U) + { + /* Clear ETH WAKEUP Exti pending bit */ + __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE); +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered WakeUp callback*/ + heth->WakeUpCallback(heth); +#else + /* ETH WAKEUP callback */ + HAL_ETH_WakeUpCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Tx Transfer completed callbacks. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Ethernet transfer error callbacks + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Ethernet Power Management module IT callback + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_PMTCallback could be implemented in the user file + */ +} + +/** + * @brief Energy Efficient Etherent IT callback + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_EEECallback could be implemented in the user file + */ +} + +/** + * @brief ETH WAKEUP interrupt callback + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_WakeUpCallback could be implemented in the user file + */ +} + +/** + * @brief Read a PHY register + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYAddr: PHY port address, must be a value from 0 to 31 + * @param PHYReg: PHY register address, must be a value from 0 to 31 + * @param pRegValue: parameter to hold read value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t *pRegValue) +{ + uint32_t tickstart; + uint32_t tmpreg; + + /* Check for the Busy flag */ + if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET) + { + return HAL_ERROR; + } + + /* Get the MACMDIOAR value */ + WRITE_REG(tmpreg, heth->Instance->MACMDIOAR); + + /* Prepare the MDIO Address Register value + - Set the PHY device address + - Set the PHY register address + - Set the read mode + - Set the MII Busy bit */ + + MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21)); + MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16)); + MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD); + SET_BIT(tmpreg, ETH_MACMDIOAR_MB); + + /* Write the result value into the MDII Address register */ + WRITE_REG(heth->Instance->MACMDIOAR, tmpreg); + + tickstart = HAL_GetTick(); + + /* Wait for the Busy flag */ + while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) + { + if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) + { + return HAL_ERROR; + } + } + + /* Get MACMIIDR value */ + WRITE_REG(*pRegValue, (uint16_t)heth->Instance->MACMDIODR); + + return HAL_OK; +} + +/** + * @brief Writes to a PHY register. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYAddr: PHY port address, must be a value from 0 to 31 + * @param PHYReg: PHY register address, must be a value from 0 to 31 + * @param RegValue: the value to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t RegValue) +{ + uint32_t tickstart; + uint32_t tmpreg; + + /* Check for the Busy flag */ + if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET) + { + return HAL_ERROR; + } + + /* Get the MACMDIOAR value */ + WRITE_REG(tmpreg, heth->Instance->MACMDIOAR); + + /* Prepare the MDIO Address Register value + - Set the PHY device address + - Set the PHY register address + - Set the write mode + - Set the MII Busy bit */ + + MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21)); + MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16)); + MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR); + SET_BIT(tmpreg, ETH_MACMDIOAR_MB); + + /* Give the value to the MII data register */ + WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue); + + /* Write the result value into the MII Address register */ + WRITE_REG(ETH->MACMDIOAR, tmpreg); + + tickstart = HAL_GetTick(); + + /* Wait for the Busy flag */ + while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) + { + if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions + * @brief ETH control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the ETH + peripheral. + +@endverbatim + * @{ + */ +/** + * @brief Get the configuration of the MAC and MTL subsystems. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param macconf: pointer to a ETH_MACConfigTypeDef structure that will hold + * the configuration of the MAC. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + if (macconf == NULL) + { + return HAL_ERROR; + } + + /* Get MAC parameters */ + macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN); + macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE; + macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL); + macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE; + macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U) + ? ENABLE : DISABLE; + macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE; + macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR, + ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE; + macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE; + macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM); + macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES); + macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE; + macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 17) == 0U) ? ENABLE : DISABLE; + macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 19) == 0U) ? ENABLE : DISABLE; + macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE; + macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE; + macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE; + macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR, + ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE; + macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG); + macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE; + macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC); + + macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL); + macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE; + macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE; + macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR, + ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE; + macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U) + ? ENABLE : DISABLE; + macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25; + + macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE; + macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO); + + macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_TFE) >> 1) > 0U) ? ENABLE : DISABLE; + macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE; + macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT); + macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16); + macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE; + macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U) + ? ENABLE : DISABLE; + + macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF)); + + macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF)); + macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR, + ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE; + macconf->ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE; + macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, + ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE; + + return HAL_OK; +} + +/** + * @brief Get the configuration of the DMA. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold + * the configuration of the ETH DMA. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) +{ + if (dmaconf == NULL) + { + return HAL_ERROR; + } + + dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_AAL) >> 12) > 0U) ? ENABLE : DISABLE; + dmaconf->BurstMode = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_FB | ETH_DMASBMR_MB); + dmaconf->RebuildINCRxBurst = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB) >> 15) > 0U) ? ENABLE : DISABLE; + + dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR | ETH_DMAMR_PR | ETH_DMAMR_DA)); + + dmaconf->PBLx8Mode = ((READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL) >> 16) > 0U) ? ENABLE : DISABLE; + dmaconf->MaximumSegmentSize = READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_MSS); + + dmaconf->FlushRxPacket = ((READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPF) >> 31) > 0U) ? ENABLE : DISABLE; + dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPBL); + + dmaconf->SecondPacketOperate = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_OSP) >> 4) > 0U) ? ENABLE : DISABLE; + dmaconf->TCPSegmentation = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12) > 0U) ? ENABLE : DISABLE; + dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL); + + return HAL_OK; +} + +/** + * @brief Set the MAC configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param macconf: pointer to a ETH_MACConfigTypeDef structure that contains + * the configuration of the MAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + if (macconf == NULL) + { + return HAL_ERROR; + } + + if (heth->gState == HAL_ETH_STATE_READY) + { + ETH_SetMACConfig(heth, macconf); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Set the ETH DMA configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold + * the configuration of the ETH DMA. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) +{ + if (dmaconf == NULL) + { + return HAL_ERROR; + } + + if (heth->gState == HAL_ETH_STATE_READY) + { + ETH_SetDMAConfig(heth, dmaconf); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configures the Clock range of ETH MDIO interface. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth) +{ + uint32_t hclk; + uint32_t tmpreg; + + /* Get the ETHERNET MACMDIOAR value */ + tmpreg = (heth->Instance)->MACMDIOAR; + + /* Clear CSR Clock Range bits */ + tmpreg &= ~ETH_MACMDIOAR_CR; + + /* Get hclk frequency value */ + hclk = HAL_RCC_GetHCLKFreq(); + + /* Set CR bits depending on hclk value */ + if (hclk < 35000000U) + { + /* CSR Clock Range between 0-35 MHz */ + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16; + } + else if (hclk < 60000000U) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26; + } + else if (hclk < 100000000U) + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42; + } + else if (hclk < 150000000U) + { + /* CSR Clock Range between 100-150 MHz */ + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62; + } + else if (hclk < 250000000U) + { + /* CSR Clock Range between 150-250 MHz */ + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102; + } + else /* (hclk >= 250000000U) */ + { + /* CSR Clock >= 250 MHz */ + tmpreg |= (uint32_t)(ETH_MACMDIOAR_CR_DIV124); + } + + /* Configure the CSR Clock Range */ + (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg; +} + +/** + * @brief Set the ETH MAC (L2) Filters configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains + * the configuration of the ETH MAC filters. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig) +{ + uint32_t filterconfig; + + if (pFilterConfig == NULL) + { + return HAL_ERROR; + } + + filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode | + ((uint32_t)pFilterConfig->HashUnicast << 1) | + ((uint32_t)pFilterConfig->HashMulticast << 2) | + ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) | + ((uint32_t)pFilterConfig->PassAllMulticast << 4) | + ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) | + ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) | + ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) | + ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) | + ((uint32_t)pFilterConfig->ReceiveAllMode << 31) | + pFilterConfig->ControlPacketsFilter); + + MODIFY_REG(heth->Instance->MACPFR, ETH_MACPFR_MASK, filterconfig); + + return HAL_OK; +} + +/** + * @brief Get the ETH MAC (L2) Filters configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold + * the configuration of the ETH MAC filters. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig) +{ + if (pFilterConfig == NULL) + { + return HAL_ERROR; + } + + pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PR)) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HUC) >> 1) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HMC) >> 2) > 0U) ? ENABLE : DISABLE; + pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, + ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE; + pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE; + pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE; + pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF); + pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, + ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE; + pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10) > 0U) + ? ENABLE : DISABLE; + pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_RA) >> 31) > 0U) ? ENABLE : DISABLE; + + return HAL_OK; +} + +/** + * @brief Set the source MAC Address to be matched. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param AddrNbr: The MAC address to configure + * This parameter must be a value of the following: + * ETH_MAC_ADDRESS1 + * ETH_MAC_ADDRESS2 + * ETH_MAC_ADDRESS3 + * @param pMACAddr: Pointer to MAC address buffer data (6 bytes) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr, + const uint8_t *pMACAddr) +{ + uint32_t macaddrlr; + uint32_t macaddrhr; + + if (pMACAddr == NULL) + { + return HAL_ERROR; + } + + /* Get mac addr high reg offset */ + macaddrhr = ((uint32_t) &(heth->Instance->MACA0HR) + AddrNbr); + /* Get mac addr low reg offset */ + macaddrlr = ((uint32_t) &(heth->Instance->MACA0LR) + AddrNbr); + + /* Set MAC addr bits 32 to 47 */ + (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]); + /* Set MAC addr bits 0 to 31 */ + (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) | + ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]); + + /* Enable address and set source address bit */ + (*(__IO uint32_t *)macaddrhr) |= (ETH_MACAHR_SA | ETH_MACAHR_AE); + + return HAL_OK; +} + +/** + * @brief Set the ETH Hash Table Value. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pHashTable: pointer to a table of two 32 bit values, that contains + * the 64 bits of the hash table. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable) +{ + if (pHashTable == NULL) + { + return HAL_ERROR; + } + + heth->Instance->MACHT0R = pHashTable[0]; + heth->Instance->MACHT1R = pHashTable[1]; + + return HAL_OK; +} + +/** + * @brief Set the VLAN Identifier for Rx packets + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param ComparisonBits: 12 or 16 bit comparison mode + must be a value of @ref ETH_VLAN_Tag_Comparison + * @param VLANIdentifier: VLAN Identifier value + * @retval None + */ +void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier) +{ + if (ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT) + { + MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL, VLANIdentifier); + CLEAR_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV); + } + else + { + MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID, VLANIdentifier); + SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV); + } +} + +/** + * @brief Enters the Power down mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure + * that contains the Power Down configuration + * @retval None. + */ +void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, const ETH_PowerDownConfigTypeDef *pPowerDownConfig) +{ + uint32_t powerdownconfig; + + powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << 1) | + ((uint32_t)pPowerDownConfig->WakeUpPacket << 2) | + ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) | + ((uint32_t)pPowerDownConfig->WakeUpForward << 10) | + ETH_MACPCSR_PWRDWN); + + /* Enable PMT interrupt */ + __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_PMTIE); + + MODIFY_REG(heth->Instance->MACPCSR, ETH_MACPCSR_MASK, powerdownconfig); +} + +/** + * @brief Exits from the Power down mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None. + */ +void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth) +{ + /* clear wake up sources */ + CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | + ETH_MACPCSR_RWKPFE); + + if (READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != (uint32_t)RESET) + { + /* Exit power down mode */ + CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN); + } + + /* Disable PMT interrupt */ + __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_PMTIE); +} + +/** + * @brief Set the WakeUp filter. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pFilter: pointer to filter registers values + * @param Count: number of filter registers, must be from 1 to 8. + * @retval None. + */ +HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count) +{ + uint32_t regindex; + + if (pFilter == NULL) + { + return HAL_ERROR; + } + + /* Reset Filter Pointer */ + SET_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKFILTRST); + + /* Wake up packet filter config */ + for (regindex = 0; regindex < Count; regindex++) + { + /* Write filter regs */ + WRITE_REG(heth->Instance->MACRWKPFR, pFilter[regindex]); + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief ETH State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + ETH communication process, return Peripheral Errors occurred during communication + process + + +@endverbatim + * @{ + */ + +/** + * @brief Returns the ETH state. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL state + */ +HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth) +{ + return heth->gState; +} + +/** + * @brief Returns the ETH error code + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH Error Code + */ +uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth) +{ + return heth->ErrorCode; +} + +/** + * @brief Returns the ETH DMA error code + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH DMA Error Code + */ +uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth) +{ + return heth->DMAErrorCode; +} + +/** + * @brief Returns the ETH MAC error code + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH MAC Error Code + */ +uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth) +{ + return heth->MACErrorCode; +} + +/** + * @brief Returns the ETH MAC WakeUp event source + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH MAC WakeUp event source + */ +uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth) +{ + return heth->MACWakeUpEvent; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup ETH_Private_Functions ETH Private Functions + * @{ + */ + +static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf) +{ + uint32_t macregval; + + /*------------------------ MACCR Configuration --------------------*/ + macregval = (macconf->InterPacketGapVal | + macconf->SourceAddrControl | + ((uint32_t)macconf->ChecksumOffload << 27) | + ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) | + ((uint32_t)macconf->Support2KPacket << 22) | + ((uint32_t)macconf->CRCStripTypePacket << 21) | + ((uint32_t)macconf->AutomaticPadCRCStrip << 20) | + ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) | + ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) | + ((uint32_t)macconf->JumboPacket << 16) | + macconf->Speed | + macconf->DuplexMode | + ((uint32_t)macconf->LoopbackMode << 12) | + ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) | + ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) | + ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) | + ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) | + macconf->BackOffLimit | + ((uint32_t)macconf->DeferralCheck << 4) | + macconf->PreambleLength); + + /* Write to MACCR */ + MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval); + + /*------------------------ MACECR Configuration --------------------*/ + macregval = ((macconf->ExtendedInterPacketGapVal << 25) | + ((uint32_t)macconf->ExtendedInterPacketGap << 24) | + ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) | + ((uint32_t)macconf->SlowProtocolDetect << 17) | + ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U) << 16) | + macconf->GiantPacketSizeLimit); + + /* Write to MACECR */ + MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval); + + /*------------------------ MACWTR Configuration --------------------*/ + macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) | + macconf->WatchdogTimeout); + + /* Write to MACWTR */ + MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval); + + /*------------------------ MACTFCR Configuration --------------------*/ + macregval = (((uint32_t)macconf->TransmitFlowControl << 1) | + macconf->PauseLowThreshold | + ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7) | + (macconf->PauseTime << 16)); + + /* Write to MACTFCR */ + MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval); + + /*------------------------ MACRFCR Configuration --------------------*/ + macregval = ((uint32_t)macconf->ReceiveFlowControl | + ((uint32_t)macconf->UnicastPausePacketDetect << 1)); + + /* Write to MACRFCR */ + MODIFY_REG(heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval); + + /*------------------------ MTLTQOMR Configuration --------------------*/ + /* Write to MTLTQOMR */ + MODIFY_REG(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode); + + /*------------------------ MTLRQOMR Configuration --------------------*/ + macregval = (macconf->ReceiveQueueMode | + ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) | + ((uint32_t)macconf->ForwardRxErrorPacket << 4) | + ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3)); + + /* Write to MTLRQOMR */ + MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval); +} + +static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf) +{ + uint32_t dmaregval; + + /*------------------------ DMAMR Configuration --------------------*/ + MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration); + + /*------------------------ DMASBMR Configuration --------------------*/ + dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) | + dmaconf->BurstMode | + ((uint32_t)dmaconf->RebuildINCRxBurst << 15)); + + MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval); + + /*------------------------ DMACCR Configuration --------------------*/ + dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) | + dmaconf->MaximumSegmentSize); + MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval); + + /*------------------------ DMACTCR Configuration --------------------*/ + dmaregval = (dmaconf->TxDMABurstLength | + ((uint32_t)dmaconf->SecondPacketOperate << 4) | + ((uint32_t)dmaconf->TCPSegmentation << 12)); + + MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval); + + /*------------------------ DMACRCR Configuration --------------------*/ + dmaregval = (((uint32_t)dmaconf->FlushRxPacket << 31) | + dmaconf->RxDMABurstLength); + + /* Write to DMACRCR */ + MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval); +} + +/** + * @brief Configures Ethernet MAC and DMA with default parameters. + * called by HAL_ETH_Init() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth) +{ + ETH_MACConfigTypeDef macDefaultConf; + ETH_DMAConfigTypeDef dmaDefaultConf; + + /*--------------- ETHERNET MAC registers default Configuration --------------*/ + macDefaultConf.AutomaticPadCRCStrip = ENABLE; + macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10; + macDefaultConf.CarrierSenseBeforeTransmit = DISABLE; + macDefaultConf.CarrierSenseDuringTransmit = DISABLE; + macDefaultConf.ChecksumOffload = ENABLE; + macDefaultConf.CRCCheckingRxPackets = ENABLE; + macDefaultConf.CRCStripTypePacket = ENABLE; + macDefaultConf.DeferralCheck = DISABLE; + macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE; + macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE; + macDefaultConf.ExtendedInterPacketGap = DISABLE; + macDefaultConf.ExtendedInterPacketGapVal = 0x0U; + macDefaultConf.ForwardRxErrorPacket = DISABLE; + macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE; + macDefaultConf.GiantPacketSizeLimit = 0x618U; + macDefaultConf.GiantPacketSizeLimitControl = DISABLE; + macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT; + macDefaultConf.Jabber = ENABLE; + macDefaultConf.JumboPacket = DISABLE; + macDefaultConf.LoopbackMode = DISABLE; + macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4; + macDefaultConf.PauseTime = 0x0U; + macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7; + macDefaultConf.ProgrammableWatchdog = DISABLE; + macDefaultConf.ReceiveFlowControl = DISABLE; + macDefaultConf.ReceiveOwn = ENABLE; + macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD; + macDefaultConf.RetryTransmission = ENABLE; + macDefaultConf.SlowProtocolDetect = DISABLE; + macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0; + macDefaultConf.Speed = ETH_SPEED_100M; + macDefaultConf.Support2KPacket = DISABLE; + macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD; + macDefaultConf.TransmitFlowControl = DISABLE; + macDefaultConf.UnicastPausePacketDetect = DISABLE; + macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE; + macDefaultConf.Watchdog = ENABLE; + macDefaultConf.WatchdogTimeout = ETH_MACWTR_WTO_2KB; + macDefaultConf.ZeroQuantaPause = ENABLE; + + /* MAC default configuration */ + ETH_SetMACConfig(heth, &macDefaultConf); + + /*--------------- ETHERNET DMA registers default Configuration --------------*/ + dmaDefaultConf.AddressAlignedBeats = ENABLE; + dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED; + dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1; + dmaDefaultConf.FlushRxPacket = DISABLE; + dmaDefaultConf.PBLx8Mode = DISABLE; + dmaDefaultConf.RebuildINCRxBurst = DISABLE; + dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; + dmaDefaultConf.SecondPacketOperate = DISABLE; + dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; + dmaDefaultConf.TCPSegmentation = DISABLE; + dmaDefaultConf.MaximumSegmentSize = ETH_SEGMENT_SIZE_DEFAULT; + + /* DMA default configuration */ + ETH_SetDMAConfig(heth, &dmaDefaultConf); +} + +/** + * @brief Initializes the DMA Tx descriptors. + * called by HAL_ETH_Init() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) +{ + ETH_DMADescTypeDef *dmatxdesc; + uint32_t i; + + /* Fill each DMATxDesc descriptor with the right values */ + for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) + { + dmatxdesc = heth->Init.TxDesc + i; + + WRITE_REG(dmatxdesc->DESC0, 0x0U); + WRITE_REG(dmatxdesc->DESC1, 0x0U); + WRITE_REG(dmatxdesc->DESC2, 0x0U); + WRITE_REG(dmatxdesc->DESC3, 0x0U); + + WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc); + + } + + heth->TxDescList.CurTxDesc = 0; + + /* Set Transmit Descriptor Ring Length */ + WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT - 1U)); + + /* Set Transmit Descriptor List Address */ + WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc); + + /* Set Transmit Descriptor Tail pointer */ + WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t) heth->Init.TxDesc); +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * called by HAL_ETH_Init() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) +{ + ETH_DMADescTypeDef *dmarxdesc; + uint32_t i; + + for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) + { + dmarxdesc = heth->Init.RxDesc + i; + + WRITE_REG(dmarxdesc->DESC0, 0x0U); + WRITE_REG(dmarxdesc->DESC1, 0x0U); + WRITE_REG(dmarxdesc->DESC2, 0x0U); + WRITE_REG(dmarxdesc->DESC3, 0x0U); + WRITE_REG(dmarxdesc->BackupAddr0, 0x0U); + WRITE_REG(dmarxdesc->BackupAddr1, 0x0U); + + /* Set Rx descritors addresses */ + WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc); + + } + + WRITE_REG(heth->RxDescList.RxDescIdx, 0U); + WRITE_REG(heth->RxDescList.RxDescCnt, 0U); + WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U); + WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U); + WRITE_REG(heth->RxDescList.ItMode, 0U); + + /* Set Receive Descriptor Ring Length */ + WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1U))); + + /* Set Receive Descriptor List Address */ + WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc); + + /* Set Receive Descriptor Tail pointer Address */ + WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1U)))); +} + +/** + * @brief Prepare Tx DMA descriptor before transmission. + * called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pTxConfig: Tx packet configuration + * @param ItMode: Enable or disable Tx EOT interrept + * @retval Status + */ +static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig, + uint32_t ItMode) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t descidx = dmatxdesclist->CurTxDesc; + uint32_t firstdescidx = dmatxdesclist->CurTxDesc; + uint32_t idx; + uint32_t descnbr = 0; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer; + uint32_t bd_count = 0; + uint32_t primask_bit; + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) + || (dmatxdesclist->PacketAddress[descidx] != NULL)) + { + return HAL_ETH_ERROR_BUSY; + } + + /***************************************************************************/ + /***************** Context descriptor configuration (Optional) **********/ + /***************************************************************************/ + /* If VLAN tag is enabled for this packet */ + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) + { + /* Set vlan tag value */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag); + /* Set vlan tag valid bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV); + /* Set the descriptor as the vlan input source */ + SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI); + + /* if inner VLAN is enabled */ + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != (uint32_t)RESET) + { + /* Set inner vlan tag value */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16)); + /* Set inner vlan tag valid bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV); + + /* Set Vlan Tag control */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl); + + /* Set the descriptor as the inner vlan input source */ + SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI); + /* Enable double VLAN processing */ + SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP); + } + } + + /* if tcp segmentation is enabled for this packet */ + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) + { + /* Set MSS value */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize); + /* Set MSS valid bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV); + } + + if ((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) + || (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)) + { + /* Set as context descriptor */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT); + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* Set own bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN); + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + descnbr += 1U; + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if (READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) + { + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx]; + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* Clear own bit */ + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN); + + return HAL_ETH_ERROR_BUSY; + } + } + + /***************************************************************************/ + /***************** Normal descriptors configuration *****************/ + /***************************************************************************/ + + descnbr += 1U; + + /* Set header or buffer 1 address */ + WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer); + /* Set header or buffer 1 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); + + if (txbuffer->next != NULL) + { + txbuffer = txbuffer->next; + /* Set buffer 2 address */ + WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer); + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16)); + } + else + { + WRITE_REG(dmatxdesc->DESC1, 0x0U); + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); + } + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) + { + /* Set TCP Header length */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19)); + /* Set TCP payload length */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen); + /* Set TCP Segmentation Enabled bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE); + } + else + { + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length); + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET) + { + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl); + } + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != (uint32_t)RESET) + { + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl); + } + } + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) + { + /* Set Vlan Tag control */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl); + } + + /* Mark it as First Descriptor */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD); + /* Mark it as NORMAL descriptor */ + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT); + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* set OWN bit of FIRST descriptor */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); + + /* If source address insertion/replacement is enabled for this packet */ + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != (uint32_t)RESET) + { + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl); + } + + /* only if the packet is split into more than one descriptors > 1 */ + while (txbuffer->next != NULL) + { + /* Clear the LD bit of previous descriptor */ + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD); + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + /* Clear the FD bit of new Descriptor */ + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD); + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN) + || (dmatxdesclist->PacketAddress[descidx] != NULL)) + { + descidx = firstdescidx; + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + /* clear previous desc own bit */ + for (idx = 0; idx < descnbr; idx ++) + { + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); + + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + } + + return HAL_ETH_ERROR_BUSY; + } + + descnbr += 1U; + + /* Get the next Tx buffer in the list */ + txbuffer = txbuffer->next; + + /* Set header or buffer 1 address */ + WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer); + /* Set header or buffer 1 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); + + if (txbuffer->next != NULL) + { + /* Get the next Tx buffer in the list */ + txbuffer = txbuffer->next; + /* Set buffer 2 address */ + WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer); + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16)); + } + else + { + WRITE_REG(dmatxdesc->DESC1, 0x0U); + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); + } + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) + { + /* Set TCP payload length */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen); + /* Set TCP Segmentation Enabled bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE); + } + else + { + /* Set the packet length */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length); + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET) + { + /* Checksum Insertion Control */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl); + } + } + + bd_count += 1U; + + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* Set Own bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); + /* Mark it as NORMAL descriptor */ + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT); + } + + if (ItMode != ((uint32_t)RESET)) + { + /* Set Interrupt on completion bit */ + SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC); + } + else + { + /* Clear Interrupt on completion bit */ + CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC); + } + + /* Mark it as LAST descriptor */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD); + /* Save the current packet address to expose it to the application */ + dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress; + + dmatxdesclist->CurTxDesc = descidx; + + /* Enter critical section */ + primask_bit = __get_PRIMASK(); + __set_PRIMASK(1); + + dmatxdesclist->BuffersInUse += bd_count + 1U; + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); + + /* Return function status */ + return HAL_ETH_ERROR_NONE; +} + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) +{ + /* Init the ETH Callback settings */ + heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */ + heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */ + heth->ErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak ErrorCallback */ + heth->PMTCallback = HAL_ETH_PMTCallback; /* Legacy weak PMTCallback */ + heth->EEECallback = HAL_ETH_EEECallback; /* Legacy weak EEECallback */ + heth->WakeUpCallback = HAL_ETH_WakeUpCallback; /* Legacy weak WakeUpCallback */ + heth->rxLinkCallback = HAL_ETH_RxLinkCallback; /* Legacy weak RxLinkCallback */ + heth->txFreeCallback = HAL_ETH_TxFreeCallback; /* Legacy weak TxFreeCallback */ +#ifdef HAL_ETH_USE_PTP + heth->txPtpCallback = HAL_ETH_TxPtpCallback; /* Legacy weak TxPtpCallback */ +#endif /* HAL_ETH_USE_PTP */ + heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; /* Legacy weak RxAllocateCallback */ +} +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ETH */ + +#endif /* HAL_ETH_MODULE_ENABLED */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_eth_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_eth_ex.c new file mode 100644 index 00000000000..5754ead3859 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_eth_ex.c @@ -0,0 +1,660 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_eth_ex.c + * @author MCD Application Team + * @brief ETH HAL Extended module driver. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#ifdef HAL_ETH_MODULE_ENABLED + +#if defined(ETH) + +/** @defgroup ETHEx ETHEx + * @brief ETH HAL Extended module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup ETHEx_Private_Constants ETHEx Private Constants + * @{ + */ +#define ETH_MACL4CR_MASK (ETH_MACL3L4CR_L4PEN | ETH_MACL3L4CR_L4SPM | \ + ETH_MACL3L4CR_L4SPIM | ETH_MACL3L4CR_L4DPM | \ + ETH_MACL3L4CR_L4DPIM) + +#define ETH_MACL3CR_MASK (ETH_MACL3L4CR_L3PEN | ETH_MACL3L4CR_L3SAM | \ + ETH_MACL3L4CR_L3SAIM | ETH_MACL3L4CR_L3DAM | \ + ETH_MACL3L4CR_L3DAIM | ETH_MACL3L4CR_L3HSBM | \ + ETH_MACL3L4CR_L3HDBM) + +#define ETH_MACRXVLAN_MASK (ETH_MACVTR_EIVLRXS | ETH_MACVTR_EIVLS | \ + ETH_MACVTR_ERIVLT | ETH_MACVTR_EDVLP | \ + ETH_MACVTR_VTHM | ETH_MACVTR_EVLRXS | \ + ETH_MACVTR_EVLS | ETH_MACVTR_DOVLTC | \ + ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL | \ + ETH_MACVTR_VTIM | ETH_MACVTR_ETV) + +#define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \ + ETH_MACVIR_VLP | ETH_MACVIR_VLC) + +#define ETH_MAC_L4_SRSP_MASK 0x0000FFFFU +#define ETH_MAC_L4_DSTP_MASK 0xFFFF0000U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup ETHEx_Exported_Functions ETH Extended Exported Functions + * @{ + */ + +/** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure ARP offload module + (+) Configure L3 and L4 filters + (+) Configure Extended VLAN features + (+) Configure Energy Efficient Ethernet module + +@endverbatim + * @{ + */ + +/** + * @brief Enables ARP Offload. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ + +void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth) +{ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP); +} + +/** + * @brief Disables ARP Offload. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth) +{ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_ARP); +} + +/** + * @brief Set the ARP Match IP address + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param IpAddress: IP Address to be matched for incoming ARP requests + * @retval None + */ +void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress) +{ + WRITE_REG(heth->Instance->MACARPAR, IpAddress); +} + +/** + * @brief Configures the L4 Filter, this function allow to: + * set the layer 4 protocol to be matched (TCP or UDP) + * enable/disable L4 source/destination port perfect/inverse match. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param Filter: L4 filter to configured, this parameter must be one of the following + * ETH_L4_FILTER_0 + * ETH_L4_FILTER_1 + * @param pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure + * that contains L4 filter configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + const ETH_L4FilterConfigTypeDef *pL4FilterConfig) +{ + if (pL4FilterConfig == NULL) + { + return HAL_ERROR; + } + + if (Filter == ETH_L4_FILTER_0) + { + /* Write configuration to MACL3L4C0R register */ + MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol | + pL4FilterConfig->SrcPortFilterMatch | + pL4FilterConfig->DestPortFilterMatch)); + + /* Write configuration to MACL4A0R register */ + WRITE_REG(heth->Instance->MACL4A0R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16))); + + } + else /* Filter == ETH_L4_FILTER_1 */ + { + /* Write configuration to MACL3L4C1R register */ + MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol | + pL4FilterConfig->SrcPortFilterMatch | + pL4FilterConfig->DestPortFilterMatch)); + + /* Write configuration to MACL4A1R register */ + WRITE_REG(heth->Instance->MACL4A1R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16))); + } + + /* Enable L4 filter */ + SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE); + + return HAL_OK; +} + +/** + * @brief Configures the L4 Filter, this function allow to: + * set the layer 4 protocol to be matched (TCP or UDP) + * enable/disable L4 source/destination port perfect/inverse match. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param Filter: L4 filter to configured, this parameter must be one of the following + * ETH_L4_FILTER_0 + * ETH_L4_FILTER_1 + * @param pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure + * that contains L4 filter configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L4FilterConfigTypeDef *pL4FilterConfig) +{ + if (pL4FilterConfig == NULL) + { + return HAL_ERROR; + } + + if (Filter == ETH_L4_FILTER_0) + { + /* Get configuration from MACL3L4C0R register */ + pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C0R, ETH_MACL3L4CR_L4PEN); + pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R, + (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)); + pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R, + (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM)); + + /* Get configuration from MACL4A0R register */ + pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_DSTP_MASK) >> 16); + pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_SRSP_MASK); + } + else /* Filter == ETH_L4_FILTER_1 */ + { + /* Get configuration from MACL3L4C1R register */ + pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C1R, ETH_MACL3L4CR_L4PEN); + pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R, + (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)); + pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R, + (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM)); + + /* Get configuration from MACL4A1R register */ + pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_DSTP_MASK) >> 16); + pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_SRSP_MASK); + } + + return HAL_OK; +} + +/** + * @brief Configures the L3 Filter, this function allow to: + * set the layer 3 protocol to be matched (IPv4 or IPv6) + * enable/disable L3 source/destination port perfect/inverse match. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param Filter: L3 filter to configured, this parameter must be one of the following + * ETH_L3_FILTER_0 + * ETH_L3_FILTER_1 + * @param pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure + * that contains L3 filter configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + const ETH_L3FilterConfigTypeDef *pL3FilterConfig) +{ + if (pL3FilterConfig == NULL) + { + return HAL_ERROR; + } + + if (Filter == ETH_L3_FILTER_0) + { + /* Write configuration to MACL3L4C0R register */ + MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol | + pL3FilterConfig->SrcAddrFilterMatch | + pL3FilterConfig->DestAddrFilterMatch | + (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) | + (pL3FilterConfig->DestAddrHigherBitsMatch << 11))); + } + else /* Filter == ETH_L3_FILTER_1 */ + { + /* Write configuration to MACL3L4C1R register */ + MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol | + pL3FilterConfig->SrcAddrFilterMatch | + pL3FilterConfig->DestAddrFilterMatch | + (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) | + (pL3FilterConfig->DestAddrHigherBitsMatch << 11))); + } + + if (Filter == ETH_L3_FILTER_0) + { + /* Check if IPv6 protocol is selected */ + if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) + { + /* Set the IPv6 address match */ + /* Set Bits[31:0] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip6Addr[0]); + /* Set Bits[63:32] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip6Addr[1]); + /* update Bits[95:64] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A2R0R, pL3FilterConfig->Ip6Addr[2]); + /* update Bits[127:96] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A3R0R, pL3FilterConfig->Ip6Addr[3]); + } + else /* IPv4 protocol is selected */ + { + /* Set the IPv4 source address match */ + WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip4SrcAddr); + /* Set the IPv4 destination address match */ + WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip4DestAddr); + } + } + else /* Filter == ETH_L3_FILTER_1 */ + { + /* Check if IPv6 protocol is selected */ + if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) + { + /* Set the IPv6 address match */ + /* Set Bits[31:0] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip6Addr[0]); + /* Set Bits[63:32] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[1]); + /* update Bits[95:64] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[2]); + /* update Bits[127:96] of 128-bit IP addr */ + WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[3]); + } + else /* IPv4 protocol is selected */ + { + /* Set the IPv4 source address match */ + WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4SrcAddr); + /* Set the IPv4 destination address match */ + WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4DestAddr); + + } + } + + /* Enable L3 filter */ + SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE); + + return HAL_OK; +} + +/** + * @brief Configures the L3 Filter, this function allow to: + * set the layer 3 protocol to be matched (IPv4 or IPv6) + * enable/disable L3 source/destination port perfect/inverse match. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param Filter: L3 filter to configured, this parameter must be one of the following + * ETH_L3_FILTER_0 + * ETH_L3_FILTER_1 + * @param pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure + * that will contain the L3 filter configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L3FilterConfigTypeDef *pL3FilterConfig) +{ + if (pL3FilterConfig == NULL) + { + return HAL_ERROR; + } + pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + ETH_MACL3L4CR_L3PEN); + pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)); + pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)); + pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + ETH_MACL3L4CR_L3HSBM) >> 6); + pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + ETH_MACL3L4CR_L3HDBM) >> 11); + + if (Filter == ETH_L3_FILTER_0) + { + if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) + { + WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R0R); + WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R0R); + WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R0R); + WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R0R); + } + else + { + WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R0R); + WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R0R); + } + } + else /* ETH_L3_FILTER_1 */ + { + if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) + { + WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R1R); + WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R1R); + WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R1R); + WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R1R); + } + else + { + WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R1R); + WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R1R); + } + } + + return HAL_OK; +} + +/** + * @brief Enables L3 and L4 filtering process. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None. + */ +void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth) +{ + /* Enable L3/L4 filter */ + SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE); +} + +/** + * @brief Disables L3 and L4 filtering process. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None. + */ +void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth) +{ + /* Disable L3/L4 filter */ + CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE); +} + +/** + * @brief Get the VLAN Configuration for Receive Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure + * that will contain the VLAN filter configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig) +{ + if (pVlanConfig == NULL) + { + return HAL_ERROR; + } + + pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, + ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE; + pVlanConfig->StripInnerVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS); + pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, + ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE; + pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR, + ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE; + pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR, + ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE; + pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, + ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE; + pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS); + pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, + (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)); + pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U) + ? DISABLE : ENABLE; + + return HAL_OK; +} + +/** + * @brief Set the VLAN Configuration for Receive Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure + * that contains VLAN filter configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig) +{ + if (pVlanConfig == NULL) + { + return HAL_ERROR; + } + + /* Write config to MACVTR */ + MODIFY_REG(heth->Instance->MACVTR, ETH_MACRXVLAN_MASK, (((uint32_t)pVlanConfig->InnerVLANTagInStatus << 31) | + pVlanConfig->StripInnerVLANTag | + ((uint32_t)pVlanConfig->InnerVLANTag << 27) | + ((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) | + ((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) | + ((uint32_t)pVlanConfig->VLANTagInStatus << 24) | + pVlanConfig->StripVLANTag | + pVlanConfig->VLANTypeCheck | + ((uint32_t)pVlanConfig->VLANTagInverceMatch << 17))); + + return HAL_OK; +} + +/** + * @brief Set the VLAN Hash Table + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param VLANHashTable: VLAN hash table 16 bit value + * @retval None + */ +void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable) +{ + MODIFY_REG(heth->Instance->MACVHTR, ETH_MACVHTR_VLHT, VLANHashTable); +} + +/** + * @brief Get the VLAN Configuration for Transmit Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param VLANTag: Selects the vlan tag, this parameter must be one of the following + * ETH_OUTER_TX_VLANTAG + * ETH_INNER_TX_VLANTAG + * @param pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure + * that will contain the Tx VLAN filter configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag, + ETH_TxVLANConfigTypeDef *pVlanConfig) +{ + if (pVlanConfig == NULL) + { + return HAL_ERROR; + } + + if (VLANTag == ETH_INNER_TX_VLANTAG) + { + pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE; + pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE; + pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACIVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC)); + } + else + { + pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE; + pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE; + pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC)); + } + + return HAL_OK;; +} + +/** + * @brief Set the VLAN Configuration for Transmit Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param VLANTag: Selects the vlan tag, this parameter must be one of the following + * ETH_OUTER_TX_VLANTAG + * ETH_INNER_TX_VLANTAG + * @param pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure + * that contains Tx VLAN filter configuration. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag, + const ETH_TxVLANConfigTypeDef *pVlanConfig) +{ + if (VLANTag == ETH_INNER_TX_VLANTAG) + { + MODIFY_REG(heth->Instance->MACIVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) | + ((uint32_t)pVlanConfig->SVLANType << 19) | + pVlanConfig->VLANTagControl)); + /* Enable Double VLAN processing */ + SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP); + } + else + { + MODIFY_REG(heth->Instance->MACVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) | + ((uint32_t)pVlanConfig->SVLANType << 19) | + pVlanConfig->VLANTagControl)); + } + + return HAL_OK; +} + +/** + * @brief Set the VLAN Tag Identifier for Transmit Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param VLANTag: Selects the vlan tag, this parameter must be one of the following + * ETH_OUTER_TX_VLANTAG + * ETH_INNER_TX_VLANTAG + * @param VLANIdentifier: VLAN Identifier 16 bit value + * @retval None + */ +void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier) +{ + if (VLANTag == ETH_INNER_TX_VLANTAG) + { + MODIFY_REG(heth->Instance->MACIVIR, ETH_MACVIR_VLT, VLANIdentifier); + } + else + { + MODIFY_REG(heth->Instance->MACVIR, ETH_MACVIR_VLT, VLANIdentifier); + } +} + +/** + * @brief Enables the VLAN Tag Filtering process. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None. + */ +void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth) +{ + /* Enable VLAN processing */ + SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE); +} + +/** + * @brief Disables the VLAN Tag Filtering process. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None. + */ +void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth) +{ + /* Disable VLAN processing */ + CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE); +} + +/** + * @brief Enters the Low Power Idle (LPI) mode + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param TxAutomate: Enable/Disable automate enter/exit LPI mode. + * @param TxClockStop: Enable/Disable Tx clock stop in LPI mode. + * @retval None + */ +void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop) +{ + /* Enable LPI Interrupts */ + __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE); + + /* Write to LPI Control register: Enter low power mode */ + MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE), + (((uint32_t)TxAutomate << 19) | + ((uint32_t)TxClockStop << 21) | + ETH_MACLCSR_LPIEN)); +} + +/** + * @brief Exits the Low Power Idle (LPI) mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth) +{ + /* Clear the LPI Config and exit low power mode */ + CLEAR_BIT(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE)); + + /* Enable LPI Interrupts */ + __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE); +} + +/** + * @brief Returns the ETH MAC LPI event + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH MAC WakeUp event + */ +uint32_t HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth) +{ + return heth->MACLPIEvent; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ETH */ + +#endif /* HAL_ETH_MODULE_ENABLED */ +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_exti.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_exti.c new file mode 100644 index 00000000000..d7cb40f142e --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_exti.c @@ -0,0 +1,639 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupts pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +#define EXTI_MODE_OFFSET 0x04u /* 0x10: Offset between MCU IMRx/EMRx registers */ +#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: Offset between MCU Rising/Falling configuration registers */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* Compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store rising trigger mode */ + *regaddr = regval; + + /* Configure falling trigger */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store falling trigger mode */ + *regaddr = regval; + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SBS->EXTICR[linepos >> 2u]; + regval &= ~(SBS_EXTICR1_PC_EXTI0 << (SBS_EXTICR1_PC_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (SBS_EXTICR1_PC_EXTI1_Pos * (linepos & 0x03u))); + SBS->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* The event mode cannot be configured if the line does not support it */ + assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT)); + + /* Configure event mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; + + return HAL_OK; +} + + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + const __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* Compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + } + + /* Get falling configuration */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SBS->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = (regval >> (SBS_EXTICR1_PC_EXTI1_Pos * (linepos & 0x03u))) & SBS_EXTICR1_PC_EXTI0; + } + else + { + pExtiConfig->GPIOSel = 0x00u; + } + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + } + + return HAL_OK; +} + + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SBS->EXTICR[linepos >> 2u]; + regval &= ~(SBS_EXTICR1_PC_EXTI0 << (SBS_EXTICR1_PC_EXTI1_Pos * (linepos & 0x03u))); + SBS->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t maskline; + uint32_t offset; + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0x00u) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + const __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Edge); + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Get pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & maskline) >> linepos); + return regval; +} + + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Edge); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + + /* Clear Pending bit */ + *regaddr = maskline; +} + + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = maskline; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_fdcan.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_fdcan.c new file mode 100644 index 00000000000..0e3ce4ed612 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_fdcan.c @@ -0,0 +1,3538 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_fdcan.c + * @author MCD Application Team + * @brief FDCAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Flexible DataRate Controller Area Network + * (FDCAN) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Configuration and Control functions + * + Peripheral State and Error functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function. + + (#) If needed , configure the reception filters and optional features using + the following configuration functions: + (++) HAL_FDCAN_ConfigFilter + (++) HAL_FDCAN_ConfigGlobalFilter + (++) HAL_FDCAN_ConfigExtendedIdMask + (++) HAL_FDCAN_ConfigRxFifoOverwrite + (++) HAL_FDCAN_ConfigRamWatchdog + (++) HAL_FDCAN_ConfigTimestampCounter + (++) HAL_FDCAN_EnableTimestampCounter + (++) HAL_FDCAN_DisableTimestampCounter + (++) HAL_FDCAN_ConfigTimeoutCounter + (++) HAL_FDCAN_EnableTimeoutCounter + (++) HAL_FDCAN_DisableTimeoutCounter + (++) HAL_FDCAN_ConfigTxDelayCompensation + (++) HAL_FDCAN_EnableTxDelayCompensation + (++) HAL_FDCAN_DisableTxDelayCompensation + (++) HAL_FDCAN_EnableISOMode + (++) HAL_FDCAN_DisableISOMode + (++) HAL_FDCAN_EnableEdgeFiltering + (++) HAL_FDCAN_DisableEdgeFiltering + + (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level + the node is active on the bus: it can send and receive messages. + + (#) The following Tx control functions can only be called when the FDCAN + module is started: + (++) HAL_FDCAN_AddMessageToTxFifoQ + (++) HAL_FDCAN_AbortTxRequest + + (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to + get Tx buffer location used to place the Tx request thanks to + HAL_FDCAN_GetLatestTxFifoQRequestBuffer API. + It is then possible to abort later on the corresponding Tx Request using + HAL_FDCAN_AbortTxRequest API. + + (#) When a message is received into the FDCAN message RAM, it can be + retrieved using the HAL_FDCAN_GetRxMessage function. + + (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering + it to initialization mode and re-enabling access to configuration + registers through the configuration functions listed here above. + + (#) All other control functions can be called any time after initialization + phase, no matter if the FDCAN module is started or stopped. + + *** Polling mode operation *** + ============================== + [..] + (#) Reception and transmission states can be monitored via the following + functions: + (++) HAL_FDCAN_IsTxBufferMessagePending + (++) HAL_FDCAN_GetRxFifoFillLevel + (++) HAL_FDCAN_GetTxFifoFreeLevel + + *** Interrupt mode operation *** + ================================ + [..] + (#) There are two interrupt lines: line 0 and 1. + By default, all interrupts are assigned to line 0. Interrupt lines + can be configured using HAL_FDCAN_ConfigInterruptLines function. + + (#) Notifications are activated using HAL_FDCAN_ActivateNotification + function. Then, the process can be controlled through one of the + available user callbacks: HAL_FDCAN_xxxCallback. + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback() + to register an interrupt callback. + + Function HAL_FDCAN_RegisterCallback() allows to register following callbacks: + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) HighPriorityMessageCallback : High Priority Message Callback. + (+) TimestampWraparoundCallback : Timestamp Wraparound Callback. + (+) TimeoutOccurredCallback : Timeout Occurred Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : FDCAN MspInit. + (+) MspDeInitCallback : FDCAN MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback, + TxBufferCompleteCallback, TxBufferAbortCallback and ErrorStatusCallback use dedicated + register callbacks: respectively HAL_FDCAN_RegisterTxEventFifoCallback(), + HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), + HAL_FDCAN_RegisterTxBufferCompleteCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback() + and HAL_FDCAN_RegisterErrorStatusCallback(). + + Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) HighPriorityMessageCallback : High Priority Message Callback. + (+) TimestampWraparoundCallback : Timestamp Wraparound Callback. + (+) TimeoutOccurredCallback : Timeout Occurred Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : FDCAN MspInit. + (+) MspDeInitCallback : FDCAN MspDeInit. + + For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback, + TxBufferCompleteCallback and TxBufferAbortCallback, use dedicated + unregister callbacks: respectively HAL_FDCAN_UnRegisterTxEventFifoCallback(), + HAL_FDCAN_UnRegisterRxFifo0Callback(), HAL_FDCAN_UnRegisterRxFifo1Callback(), + HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), HAL_FDCAN_UnRegisterTxBufferAbortCallback() + and HAL_FDCAN_UnRegisterErrorStatusCallback(). + + By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET, + all callbacks are set to the corresponding weak functions: + examples HAL_FDCAN_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit() + or HAL_FDCAN_Init() function. + + When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +#if defined(FDCAN1) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup FDCAN FDCAN + * @brief FDCAN HAL module driver + * @{ + */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FDCAN_Private_Constants + * @{ + */ +#define FDCAN_TIMEOUT_VALUE 10U + +#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFN) +#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0N) +#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1N) +#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA) +#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO) + +#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */ +#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */ +#define FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */ +#define FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */ +#define FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */ +#define FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */ +#define FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */ +#define FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */ +#define FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */ +#define FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */ +#define FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */ +#define FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */ +#define FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */ +#define FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */ + +#define SRAMCAN_FLS_NBR (28U) /* Max. Filter List Standard Number */ +#define SRAMCAN_FLE_NBR ( 8U) /* Max. Filter List Extended Number */ +#define SRAMCAN_RF0_NBR ( 3U) /* RX FIFO 0 Elements Number */ +#define SRAMCAN_RF1_NBR ( 3U) /* RX FIFO 1 Elements Number */ +#define SRAMCAN_TEF_NBR ( 3U) /* TX Event FIFO Elements Number */ +#define SRAMCAN_TFQ_NBR ( 3U) /* TX FIFO/Queue Elements Number */ + +#define SRAMCAN_FLS_SIZE ( 1U * 4U) /* Filter Standard Element Size in bytes */ +#define SRAMCAN_FLE_SIZE ( 2U * 4U) /* Filter Extended Element Size in bytes */ +#define SRAMCAN_RF0_SIZE (18U * 4U) /* RX FIFO 0 Elements Size in bytes */ +#define SRAMCAN_RF1_SIZE (18U * 4U) /* RX FIFO 1 Elements Size in bytes */ +#define SRAMCAN_TEF_SIZE ( 2U * 4U) /* TX Event FIFO Elements Size in bytes */ +#define SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */ + +#define SRAMCAN_FLSSA ((uint32_t)0) /* Filter List Standard Start + Address */ +#define SRAMCAN_FLESA ((uint32_t)(SRAMCAN_FLSSA + (SRAMCAN_FLS_NBR * SRAMCAN_FLS_SIZE))) /* Filter List Extended Start + Address */ +#define SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */ +#define SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */ +#define SRAMCAN_TEFSA ((uint32_t)(SRAMCAN_RF1SA + (SRAMCAN_RF1_NBR * SRAMCAN_RF1_SIZE))) /* Tx Event FIFO Start + Address */ +#define SRAMCAN_TFQSA ((uint32_t)(SRAMCAN_TEFSA + (SRAMCAN_TEF_NBR * SRAMCAN_TEF_SIZE))) /* Tx FIFO/Queue Start + Address */ +#define SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FDCAN_Private_Variables + * @{ + */ +static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FDCAN_Private_Functions_Prototypes + * @{ + */ +static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan); +static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData, uint32_t BufferIndex); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions + * @{ + */ + +/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the FDCAN. + (+) De-initialize the FDCAN. + (+) Enter FDCAN peripheral in power down mode. + (+) Exit power down mode. + (+) Register callbacks. + (+) Unregister callbacks. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FDCAN peripheral according to the specified + * parameters in the FDCAN_InitTypeDef structure. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t tickstart; + + /* Check FDCAN handle */ + if (hfdcan == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + if (hfdcan->Instance == FDCAN1) + { + assert_param(IS_FDCAN_CKDIV(hfdcan->Init.ClockDivider)); + } + assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat)); + assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode)); + assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause)); + assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException)); + assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler)); + assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth)); + assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1)); + assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2)); + if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS) + { + assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler)); + assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth)); + assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1)); + assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2)); + } + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, SRAMCAN_FLS_NBR)); + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, SRAMCAN_FLE_NBR)); + assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode)); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hfdcan->Lock = HAL_UNLOCKED; + + /* Reset callbacks to legacy functions */ + hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* TxEventFifoCallback */ + hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* RxFifo0Callback */ + hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* RxFifo1Callback */ + hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* TxFifoEmptyCallback */ + hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* TxBufferCompleteCallback */ + hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* TxBufferAbortCallback */ + hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* HighPriorityMessageCallback */ + hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* TimestampWraparoundCallback */ + hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* TimeoutOccurredCallback */ + hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* ErrorCallback */ + hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* ErrorStatusCallback */ + + if (hfdcan->MspInitCallback == NULL) + { + hfdcan->MspInitCallback = HAL_FDCAN_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware: CLOCK, NVIC */ + hfdcan->MspInitCallback(hfdcan); + } +#else + if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hfdcan->Lock = HAL_UNLOCKED; + + /* Init the low level hardware: CLOCK, NVIC */ + HAL_FDCAN_MspInit(hfdcan); + } +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + + /* Exit from Sleep mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check Sleep mode acknowledge */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) + { + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Request initialisation */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the INIT bit into CCCR register is set */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Enable configuration change */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE); + + /* Check FDCAN instance */ + if (hfdcan->Instance == FDCAN1) + { + /* Configure Clock divider */ + FDCAN_CONFIG->CKDIV = hfdcan->Init.ClockDivider; + } + + /* Set the no automatic retransmission */ + if (hfdcan->Init.AutoRetransmission == ENABLE) + { + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR); + } + else + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR); + } + + /* Set the transmit pause feature */ + if (hfdcan->Init.TransmitPause == ENABLE) + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP); + } + else + { + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP); + } + + /* Set the Protocol Exception Handling */ + if (hfdcan->Init.ProtocolException == ENABLE) + { + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD); + } + else + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD); + } + + /* Set FDCAN Frame Format */ + MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat); + + /* Reset FDCAN Operation Mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM)); + CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK); + + /* Set FDCAN Operating Mode: + | Normal | Restricted | Bus | Internal | External + | | Operation | Monitoring | LoopBack | LoopBack + CCCR.TEST | 0 | 0 | 0 | 1 | 1 + CCCR.MON | 0 | 0 | 1 | 1 | 0 + TEST.LBCK | 0 | 0 | 0 | 1 | 1 + CCCR.ASM | 0 | 1 | 0 | 0 | 0 + */ + if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION) + { + /* Enable Restricted Operation mode */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM); + } + else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL) + { + if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING) + { + /* Enable write access to TEST register */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST); + + /* Enable LoopBack mode */ + SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK); + + if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK) + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON); + } + } + else + { + /* Enable bus monitoring mode */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON); + } + } + else + { + /* Nothing to do: normal mode */ + } + + /* Set the nominal bit timing register */ + hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ + (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \ + (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \ + (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos)); + + /* If FD operation with BRS is selected, set the data bit timing register */ + if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS) + { + hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ + (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \ + (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \ + (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos)); + } + + /* Select between Tx FIFO and Tx Queue operation modes */ + SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode); + + /* Calculate each RAM block address */ + FDCAN_CalcultateRamBlockAddresses(hfdcan); + + /* Initialize the Latest Tx request buffer index */ + hfdcan->LatestTxFifoQRequest = 0U; + + /* Initialize the error code */ + hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; + + /* Initialize the FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the FDCAN peripheral registers to their default reset values. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan) +{ + /* Check FDCAN handle */ + if (hfdcan == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + /* Stop the FDCAN module: return value is voluntary ignored */ + (void)HAL_FDCAN_Stop(hfdcan); + + /* Disable Interrupt lines */ + CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1)); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + if (hfdcan->MspDeInitCallback == NULL) + { + hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: CLOCK, NVIC */ + hfdcan->MspDeInitCallback(hfdcan); +#else + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_FDCAN_MspDeInit(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + + /* Reset the FDCAN ErrorCode */ + hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_RESET; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the FDCAN MSP. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the FDCAN MSP. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Enter FDCAN peripheral in sleep mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t tickstart; + + /* Request clock stop */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until FDCAN is ready for power down */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U) + { + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Exit power down mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t tickstart; + + /* Reset clock stop request */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until FDCAN exits sleep mode */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) + { + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Enter normal operation */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Return function status */ + return HAL_OK; +} + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +/** + * @brief Register a FDCAN CallBack. + * To be used instead of the weak predefined callback + * @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains + * the configuration information for FDCAN module + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID + * @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID + * @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID + * @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID + * @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN)) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID : + hfdcan->TxFifoEmptyCallback = pCallback; + break; + + case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID : + hfdcan->HighPriorityMessageCallback = pCallback; + break; + + case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID : + hfdcan->TimestampWraparoundCallback = pCallback; + break; + + case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID : + hfdcan->TimeoutOccurredCallback = pCallback; + break; + + case HAL_FDCAN_ERROR_CALLBACK_CB_ID : + hfdcan->ErrorCallback = pCallback; + break; + + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = pCallback; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = pCallback; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a FDCAN CallBack. + * FDCAN callback is redirected to the weak predefined callback + * @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains + * the configuration information for FDCAN module + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID + * @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID + * @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID + * @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID + * @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID : + hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; + break; + + case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID : + hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; + break; + + case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID : + hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; + break; + + case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID : + hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; + break; + + case HAL_FDCAN_ERROR_CALLBACK_CB_ID : + hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; + break; + + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = HAL_FDCAN_MspInit; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = HAL_FDCAN_MspInit; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Tx Event Fifo FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Tx Event Fifo Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxEventFifoCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxEventFifoCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Tx Event Fifo FDCAN Callback + * Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Rx Fifo 0 FDCAN Callback + * To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Rx Fifo 0 Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo0CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo0Callback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Rx Fifo 0 FDCAN Callback + * Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Rx Fifo 1 FDCAN Callback + * To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Rx Fifo 1 Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo1CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo1Callback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Rx Fifo 1 FDCAN Callback + * Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Tx Buffer Complete FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Tx Buffer Complete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferCompleteCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferCompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Tx Buffer Complete FDCAN Callback + * Tx Buffer Complete FDCAN Callback is redirected to + * the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Tx Buffer Abort FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Tx Buffer Abort Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferAbortCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferAbortCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Tx Buffer Abort FDCAN Callback + * Tx Buffer Abort FDCAN Callback is redirected to + * the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Error Status FDCAN Callback + * To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Error Status Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_ErrorStatusCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->ErrorStatusCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Error Status FDCAN Callback + * Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions + * @brief FDCAN Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_FDCAN_ConfigFilter : Configure the FDCAN reception filters + (+) HAL_FDCAN_ConfigGlobalFilter : Configure the FDCAN global filter + (+) HAL_FDCAN_ConfigExtendedIdMask : Configure the extended ID mask + (+) HAL_FDCAN_ConfigRxFifoOverwrite : Configure the Rx FIFO operation mode + (+) HAL_FDCAN_ConfigRamWatchdog : Configure the RAM watchdog + (+) HAL_FDCAN_ConfigTimestampCounter : Configure the timestamp counter + (+) HAL_FDCAN_EnableTimestampCounter : Enable the timestamp counter + (+) HAL_FDCAN_DisableTimestampCounter : Disable the timestamp counter + (+) HAL_FDCAN_GetTimestampCounter : Get the timestamp counter value + (+) HAL_FDCAN_ResetTimestampCounter : Reset the timestamp counter to zero + (+) HAL_FDCAN_ConfigTimeoutCounter : Configure the timeout counter + (+) HAL_FDCAN_EnableTimeoutCounter : Enable the timeout counter + (+) HAL_FDCAN_DisableTimeoutCounter : Disable the timeout counter + (+) HAL_FDCAN_GetTimeoutCounter : Get the timeout counter value + (+) HAL_FDCAN_ResetTimeoutCounter : Reset the timeout counter to its start value + (+) HAL_FDCAN_ConfigTxDelayCompensation : Configure the transmitter delay compensation + (+) HAL_FDCAN_EnableTxDelayCompensation : Enable the transmitter delay compensation + (+) HAL_FDCAN_DisableTxDelayCompensation : Disable the transmitter delay compensation + (+) HAL_FDCAN_EnableISOMode : Enable ISO 11898-1 protocol mode + (+) HAL_FDCAN_DisableISOMode : Disable ISO 11898-1 protocol mode + (+) HAL_FDCAN_EnableEdgeFiltering : Enable edge filtering during bus integration + (+) HAL_FDCAN_DisableEdgeFiltering : Disable edge filtering during bus integration + +@endverbatim + * @{ + */ + +/** + * @brief Configure the FDCAN reception filter according to the specified + * parameters in the FDCAN_FilterTypeDef structure. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param sFilterConfig pointer to an FDCAN_FilterTypeDef structure that + * contains the filter configuration information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig) +{ + uint32_t FilterElementW1; + uint32_t FilterElementW2; + uint32_t *FilterAddress; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check function parameters */ + assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType)); + assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig)); + + if (sFilterConfig->IdType == FDCAN_STANDARD_ID) + { + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU)); + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU)); + assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType)); + + /* Build filter element */ + FilterElementW1 = ((sFilterConfig->FilterType << 30U) | + (sFilterConfig->FilterConfig << 27U) | + (sFilterConfig->FilterID1 << 16U) | + sFilterConfig->FilterID2); + + /* Calculate filter address */ + FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * SRAMCAN_FLS_SIZE)); + + /* Write filter element to the message RAM */ + *FilterAddress = FilterElementW1; + } + else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */ + { + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU)); + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU)); + assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType)); + + /* Build first word of filter element */ + FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1); + + /* Build second word of filter element */ + FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2); + + /* Calculate filter address */ + FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * SRAMCAN_FLE_SIZE)); + + /* Write filter element to the message RAM */ + *FilterAddress = FilterElementW1; + FilterAddress++; + *FilterAddress = FilterElementW2; + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the FDCAN global filter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param NonMatchingStd Defines how received messages with 11-bit IDs that + * do not match any element of the filter list are treated. + * This parameter can be a value of @arg FDCAN_Non_Matching_Frames. + * @param NonMatchingExt Defines how received messages with 29-bit IDs that + * do not match any element of the filter list are treated. + * This parameter can be a value of @arg FDCAN_Non_Matching_Frames. + * @param RejectRemoteStd Filter or reject all the remote 11-bit IDs frames. + * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames. + * @param RejectRemoteExt Filter or reject all the remote 29-bit IDs frames. + * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, + uint32_t NonMatchingStd, + uint32_t NonMatchingExt, + uint32_t RejectRemoteStd, + uint32_t RejectRemoteExt) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd)); + assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt)); + assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd)); + assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure global filter */ + MODIFY_REG(hfdcan->Instance->RXGFC, (FDCAN_RXGFC_ANFS | + FDCAN_RXGFC_ANFE | + FDCAN_RXGFC_RRFS | + FDCAN_RXGFC_RRFE), + ((NonMatchingStd << FDCAN_RXGFC_ANFS_Pos) | + (NonMatchingExt << FDCAN_RXGFC_ANFE_Pos) | + (RejectRemoteStd << FDCAN_RXGFC_RRFS_Pos) | + (RejectRemoteExt << FDCAN_RXGFC_RRFE_Pos))); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the extended ID mask. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param Mask Extended ID Mask. + * This parameter must be a number between 0 and 0x1FFFFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure the extended ID mask */ + hfdcan->Instance->XIDAM = Mask; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the Rx FIFO operation mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo Rx FIFO. + * This parameter can be one of the following values: + * @arg FDCAN_RX_FIFO0: Rx FIFO 0 + * @arg FDCAN_RX_FIFO1: Rx FIFO 1 + * @param OperationMode operation mode. + * This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_RX_FIFO(RxFifo)); + assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + if (RxFifo == FDCAN_RX_FIFO0) + { + /* Select FIFO 0 Operation Mode */ + MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F0OM, (OperationMode << FDCAN_RXGFC_F0OM_Pos)); + } + else /* RxFifo == FDCAN_RX_FIFO1 */ + { + /* Select FIFO 1 Operation Mode */ + MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F1OM, (OperationMode << FDCAN_RXGFC_F1OM_Pos)); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the RAM watchdog. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param CounterStartValue Start value of the Message RAM Watchdog Counter, + * This parameter must be a number between 0x00 and 0xFF, + * with the reset value of 0x00 the counter is disabled. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure the RAM watchdog counter start value */ + MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the timestamp counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimestampPrescaler Timestamp Counter Prescaler. + * This parameter can be a value of @arg FDCAN_Timestamp_Prescaler. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure prescaler */ + MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable the timestamp counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimestampOperation Timestamp counter operation. + * This parameter can be a value of @arg FDCAN_Timestamp. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable timestamp counter */ + MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable the timestamp counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable timestamp counter */ + CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Get the timestamp counter value. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Timestamp counter value + */ +uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan) +{ + return (uint16_t)(hfdcan->Instance->TSCV); +} + +/** + * @brief Reset the timestamp counter to zero. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL) + { + /* Reset timestamp counter. + Actually any write operation to TSCV clears the counter */ + CLEAR_REG(hfdcan->Instance->TSCV); + } + else + { + /* Update error code. + Unable to reset external counter */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the timeout counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimeoutOperation Timeout counter operation. + * This parameter can be a value of @arg FDCAN_Timeout_Operation. + * @param TimeoutPeriod Start value of the timeout down-counter. + * This parameter must be a number between 0x0000 and 0xFFFF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, + uint32_t TimeoutPeriod) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation)); + assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Select timeout operation and configure period */ + MODIFY_REG(hfdcan->Instance->TOCC, + (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos))); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable the timeout counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable timeout counter */ + SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable the timeout counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable timeout counter */ + CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Get the timeout counter value. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Timeout counter value + */ +uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan) +{ + return (uint16_t)(hfdcan->Instance->TOCV); +} + +/** + * @brief Reset the timeout counter to its start value. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS) + { + /* Reset timeout counter to start value */ + CLEAR_REG(hfdcan->Instance->TOCV); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Unable to reset counter: controlled only by FIFO empty state */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the transmitter delay compensation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TdcOffset Transmitter Delay Compensation Offset. + * This parameter must be a number between 0x00 and 0x7F. + * @param TdcFilter Transmitter Delay Compensation Filter Window Length. + * This parameter must be a number between 0x00 and 0x7F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, + uint32_t TdcFilter) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU)); + assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure TDC offset and filter window */ + hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos)); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable the transmitter delay compensation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable transmitter delay compensation */ + SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable the transmitter delay compensation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable transmitter delay compensation */ + CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable ISO 11898-1 protocol mode. + * CAN FD frame format is according to ISO 11898-1 standard. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable Non ISO protocol mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable ISO 11898-1 protocol mode. + * CAN FD frame format is according to Bosch CAN FD specification V1.0. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable Non ISO protocol mode */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable edge filtering during bus integration. + * Two consecutive dominant tq are required to detect an edge for hard synchronization. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable edge filtering */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable edge filtering during bus integration. + * One dominant tq is required to detect an edge for hard synchronization. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable edge filtering */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_FDCAN_Start : Start the FDCAN module + (+) HAL_FDCAN_Stop : Stop the FDCAN module and enable access to configuration registers + (+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx FIFO/Queue and activate the corresponding + transmission request + (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request + (+) HAL_FDCAN_AbortTxRequest : Abort transmission request + (+) HAL_FDCAN_GetRxMessage : Get an FDCAN frame from the Rx FIFO zone into the message RAM + (+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from the Tx Event FIFO zone + into the message RAM + (+) HAL_FDCAN_GetHighPriorityMessageStatus : Get high priority message status + (+) HAL_FDCAN_GetProtocolStatus : Get protocol status + (+) HAL_FDCAN_GetErrorCounters : Get error counter values + (+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission request is pending + on the selected Tx buffer + (+) HAL_FDCAN_GetRxFifoFillLevel : Return Rx FIFO fill level + (+) HAL_FDCAN_GetTxFifoFreeLevel : Return Tx FIFO free level + (+) HAL_FDCAN_IsRestrictedOperationMode : Check if the FDCAN peripheral entered Restricted Operation Mode + (+) HAL_FDCAN_ExitRestrictedOperationMode : Exit Restricted Operation Mode + +@endverbatim + * @{ + */ + +/** + * @brief Start the FDCAN module. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Change FDCAN peripheral state */ + hfdcan->State = HAL_FDCAN_STATE_BUSY; + + /* Request leave initialisation */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Reset the FDCAN ErrorCode */ + hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Stop the FDCAN module and enable access to configuration registers. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + + if (hfdcan->State == HAL_FDCAN_STATE_BUSY) + { + /* Request initialisation */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Wait until the INIT bit into CCCR register is set */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Reset counter */ + Counter = 0U; + + /* Exit from Sleep mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Wait until FDCAN exits sleep mode */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Enable configuration change */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE); + + /* Reset Latest Tx FIFO/Queue Request Buffer Index */ + hfdcan->LatestTxFifoQRequest = 0U; + + /* Change FDCAN peripheral state */ + hfdcan->State = HAL_FDCAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Add a message to the Tx FIFO/Queue and activate the corresponding transmission request + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure. + * @param pTxData pointer to a buffer containing the payload of the Tx frame. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData) +{ + uint32_t PutIndex; + + /* Check function parameters */ + assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType)); + if (pTxHeader->IdType == FDCAN_STANDARD_ID) + { + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU)); + } + else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */ + { + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU)); + } + assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType)); + assert_param(IS_FDCAN_DLC(pTxHeader->DataLength)); + assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator)); + assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch)); + assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat)); + assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl)); + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_BUSY) + { + /* Check that the Tx FIFO/Queue is not full */ + if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL; + + return HAL_ERROR; + } + else + { + /* Retrieve the Tx FIFO PutIndex */ + PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos); + + /* Add the message to the Tx FIFO/Queue */ + FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex); + + /* Activate the corresponding transmission request */ + hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex); + + /* Store the Latest Tx FIFO/Queue Request Buffer Index */ + hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get Tx buffer index of latest Tx FIFO/Queue request + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Tx buffer index of last Tx FIFO/Queue request + * - Any value of @arg FDCAN_Tx_location if Tx request has been submitted. + * - 0 if no Tx FIFO/Queue request have been submitted. + */ +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan) +{ + /* Return Last Tx FIFO/Queue Request Buffer */ + return hfdcan->LatestTxFifoQRequest; +} + +/** + * @brief Abort transmission request + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param BufferIndex buffer index. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndex)); + + if (hfdcan->State == HAL_FDCAN_STATE_BUSY) + { + /* Add cancellation request */ + hfdcan->Instance->TXBCR = BufferIndex; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get an FDCAN frame from the Rx FIFO zone into the message RAM. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxLocation Location of the received message to be read. + * This parameter can be a value of @arg FDCAN_Rx_location. + * @param pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure. + * @param pRxData pointer to a buffer where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, + FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData) +{ + uint32_t *RxAddress; + uint8_t *pData; + uint32_t ByteCounter; + uint32_t GetIndex = 0; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_RX_FIFO(RxLocation)); + + if (state == HAL_FDCAN_STATE_BUSY) + { + if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY; + + return HAL_ERROR; + } + else + { + /* Check that the Rx FIFO 0 is full & overwrite mode is on */ + if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U) + { + if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F0OM) >> FDCAN_RXGFC_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) + { + /* When overwrite status is on discard first message in FIFO */ + GetIndex = 1U; + } + } + + /* Calculate Rx FIFO 0 element index */ + GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); + + /* Calculate Rx FIFO 0 element address */ + RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * SRAMCAN_RF0_SIZE)); + } + } + else /* Rx element is assigned to the Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY; + + return HAL_ERROR; + } + else + { + /* Check that the Rx FIFO 1 is full & overwrite mode is on */ + if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U) + { + if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F1OM) >> FDCAN_RXGFC_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) + { + /* When overwrite status is on discard first message in FIFO */ + GetIndex = 1U; + } + } + + /* Calculate Rx FIFO 1 element index */ + GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); + /* Calculate Rx FIFO 1 element address */ + RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * SRAMCAN_RF1_SIZE)); + } + } + + /* Retrieve IdType */ + pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD; + + /* Retrieve Identifier */ + if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */ + { + pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U); + } + else /* Extended ID element */ + { + pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID); + } + + /* Retrieve RxFrameType */ + pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR); + + /* Retrieve ErrorStateIndicator */ + pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI); + + /* Increment RxAddress pointer to second word of Rx FIFO element */ + RxAddress++; + + /* Retrieve RxTimestamp */ + pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS); + + /* Retrieve DataLength */ + pRxHeader->DataLength = ((*RxAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U); + + /* Retrieve BitRateSwitch */ + pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS); + + /* Retrieve FDFormat */ + pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF); + + /* Retrieve FilterIndex */ + pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24U); + + /* Retrieve NonMatchingFrame */ + pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31U); + + /* Increment RxAddress pointer to payload of Rx FIFO element */ + RxAddress++; + + /* Retrieve Rx payload */ + pData = (uint8_t *)RxAddress; + for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength]; ByteCounter++) + { + pRxData[ByteCounter] = pData[ByteCounter]; + } + + if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */ + { + /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */ + hfdcan->Instance->RXF0A = GetIndex; + } + else /* Rx element is assigned to the Rx FIFO 1 */ + { + /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */ + hfdcan->Instance->RXF1A = GetIndex; + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent) +{ + uint32_t *TxEventAddress; + uint32_t GetIndex; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + if (state == HAL_FDCAN_STATE_BUSY) + { + /* Check that the Tx event FIFO is not empty */ + if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY; + + return HAL_ERROR; + } + + /* Calculate Tx event FIFO element address */ + GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos); + TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * SRAMCAN_TEF_SIZE)); + + /* Retrieve IdType */ + pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD; + + /* Retrieve Identifier */ + if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */ + { + pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U); + } + else /* Extended ID element */ + { + pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID); + } + + /* Retrieve TxFrameType */ + pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR); + + /* Retrieve ErrorStateIndicator */ + pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI); + + /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */ + TxEventAddress++; + + /* Retrieve TxTimestamp */ + pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS); + + /* Retrieve DataLength */ + pTxEvent->DataLength = ((*TxEventAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U); + + /* Retrieve BitRateSwitch */ + pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS); + + /* Retrieve FDFormat */ + pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF); + + /* Retrieve EventType */ + pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET); + + /* Retrieve MessageMarker */ + pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24U); + + /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */ + hfdcan->Instance->TXEFA = GetIndex; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get high priority message status. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_HpMsgStatusTypeDef *HpMsgStatus) +{ + HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos); + HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos); + HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI); + HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Get protocol status. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ProtocolStatusTypeDef *ProtocolStatus) +{ + uint32_t StatusReg; + + /* Read the protocol status register */ + StatusReg = READ_REG(hfdcan->Instance->PSR); + + /* Fill the protocol status structure */ + ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC); + ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos); + ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT); + ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos); + ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos); + ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos); + ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos); + ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos); + ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos); + ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos); + ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Get error counter values. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan, + FDCAN_ErrorCountersTypeDef *ErrorCounters) +{ + uint32_t CountersReg; + + /* Read the error counters register */ + CountersReg = READ_REG(hfdcan->Instance->ECR); + + /* Fill the error counters structure */ + ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos); + ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos); + ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos); + ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx buffer. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TxBufferIndex Tx buffer index. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval Status + * - 0 : No pending transmission request on TxBufferIndex list. + * - 1 : Pending transmission request on TxBufferIndex. + */ +uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TX_LOCATION_LIST(TxBufferIndex)); + + /* Check pending transmission request on the selected buffer */ + if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U) + { + return 0; + } + return 1; +} + +/** + * @brief Return Rx FIFO fill level. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo Rx FIFO. + * This parameter can be one of the following values: + * @arg FDCAN_RX_FIFO0: Rx FIFO 0 + * @arg FDCAN_RX_FIFO1: Rx FIFO 1 + * @retval Rx FIFO fill level. + */ +uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo) +{ + uint32_t FillLevel; + + /* Check function parameters */ + assert_param(IS_FDCAN_RX_FIFO(RxFifo)); + + if (RxFifo == FDCAN_RX_FIFO0) + { + FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL; + } + else /* RxFifo == FDCAN_RX_FIFO1 */ + { + FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL; + } + + /* Return Rx FIFO fill level */ + return FillLevel; +} + +/** + * @brief Return Tx FIFO free level: number of consecutive free Tx FIFO + * elements starting from Tx FIFO GetIndex. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Tx FIFO free level. + */ +uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t FreeLevel; + + FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL; + + /* Return Tx FIFO free level */ + return FreeLevel; +} + +/** + * @brief Check if the FDCAN peripheral entered Restricted Operation Mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Status + * - 0 : Normal FDCAN operation. + * - 1 : Restricted Operation Mode active. + */ +uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t OperationMode; + + /* Get Operation Mode */ + OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos); + + return OperationMode; +} + +/** + * @brief Exit Restricted Operation Mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Exit Restricted Operation mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_FDCAN_ConfigInterruptLines : Assign interrupts to either Interrupt line 0 or 1 + (+) HAL_FDCAN_ActivateNotification : Enable interrupts + (+) HAL_FDCAN_DeactivateNotification : Disable interrupts + (+) HAL_FDCAN_IRQHandler : Handles FDCAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Assign interrupts to either Interrupt line 0 or 1. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ITList indicates which interrupts group will be assigned to the selected interrupt line. + * This parameter can be any combination of @arg FDCAN_Interrupts_Group. + * @param InterruptLine Interrupt line. + * This parameter can be a value of @arg FDCAN_Interrupt_Line. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_IT_GROUP(ITList)); + assert_param(IS_FDCAN_IT_LINE(InterruptLine)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Assign list of interrupts to the selected line */ + if (InterruptLine == FDCAN_INTERRUPT_LINE0) + { + CLEAR_BIT(hfdcan->Instance->ILS, ITList); + } + else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */ + { + SET_BIT(hfdcan->Instance->ILS, ITList); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable interrupts. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg FDCAN_Interrupts. + * @param BufferIndexes Tx Buffer Indexes. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * This parameter is ignored if ActiveITs does not include one of the following: + * - FDCAN_IT_TX_COMPLETE + * - FDCAN_IT_TX_ABORT_COMPLETE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, + uint32_t BufferIndexes) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + uint32_t ITs_lines_selection; + + /* Check function parameters */ + assert_param(IS_FDCAN_IT(ActiveITs)); + if ((ActiveITs & (FDCAN_IT_TX_COMPLETE | FDCAN_IT_TX_ABORT_COMPLETE)) != 0U) + { + assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndexes)); + } + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Get interrupts line selection */ + ITs_lines_selection = hfdcan->Instance->ILS; + + /* Enable Interrupt lines */ + if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U))) + { + /* Enable Interrupt line 0 */ + SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0); + } + if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U))) + { + /* Enable Interrupt line 1 */ + SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1); + } + + if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U) + { + /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register, + but interrupt will only occur if TC is enabled in IE register */ + SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes); + } + + if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U) + { + /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register, + but interrupt will only occur if TCF is enabled in IE register */ + SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes); + } + + /* Enable the selected interrupts */ + __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable interrupts. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg FDCAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + uint32_t ITs_enabled; + uint32_t ITs_lines_selection; + + /* Check function parameters */ + assert_param(IS_FDCAN_IT(InactiveITs)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Disable the selected interrupts */ + __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs); + + if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U) + { + /* Disable Tx Buffer Transmission Interrupts */ + CLEAR_REG(hfdcan->Instance->TXBTIE); + } + + if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U) + { + /* Disable Tx Buffer Cancellation Finished Interrupt */ + CLEAR_REG(hfdcan->Instance->TXBCIE); + } + + /* Get interrupts enabled and interrupts line selection */ + ITs_enabled = hfdcan->Instance->IE; + ITs_lines_selection = hfdcan->Instance->ILS; + + /* Check if some interrupts are still enabled on interrupt line 0 */ + if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U))) + { + /* Do nothing */ + } + else /* no more interrupts enabled on interrupt line 0 */ + { + /* Disable interrupt line 0 */ + CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0); + } + + /* Check if some interrupts are still enabled on interrupt line 1 */ + if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U))) + { + /* Do nothing */ + } + else /* no more interrupts enabled on interrupt line 1 */ + { + /* Disable interrupt line 1 */ + CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Handles FDCAN interrupt request. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t TxEventFifoITs; + uint32_t RxFifo0ITs; + uint32_t RxFifo1ITs; + uint32_t Errors; + uint32_t ErrorStatusITs; + uint32_t TransmittedBuffers; + uint32_t AbortedBuffers; + uint32_t itsource; + uint32_t itflag; + + TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK; + TxEventFifoITs &= hfdcan->Instance->IE; + RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK; + RxFifo0ITs &= hfdcan->Instance->IE; + RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK; + RxFifo1ITs &= hfdcan->Instance->IE; + Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK; + Errors &= hfdcan->Instance->IE; + ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK; + ErrorStatusITs &= hfdcan->Instance->IE; + itsource = hfdcan->Instance->IE; + itflag = hfdcan->Instance->IR; + + /* High Priority Message interrupt management *******************************/ + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET) + { + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET) + { + /* Clear the High Priority Message flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->HighPriorityMessageCallback(hfdcan); +#else + /* High Priority Message Callback */ + HAL_FDCAN_HighPriorityMessageCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Transmission Abort interrupt management **********************************/ + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET) + { + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_ABORT_COMPLETE) != RESET) + { + /* List of aborted monitored buffers */ + AbortedBuffers = hfdcan->Instance->TXBCF; + AbortedBuffers &= hfdcan->Instance->TXBCIE; + + /* Clear the Transmission Cancellation flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers); +#else + /* Transmission Cancellation Callback */ + HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Tx event FIFO interrupts management **************************************/ + if (TxEventFifoITs != 0U) + { + /* Clear the Tx Event FIFO flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs); +#else + /* Tx Event FIFO Callback */ + HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Rx FIFO 0 interrupts management ******************************************/ + if (RxFifo0ITs != 0U) + { + /* Clear the Rx FIFO 0 flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs); +#else + /* Rx FIFO 0 Callback */ + HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Rx FIFO 1 interrupts management ******************************************/ + if (RxFifo1ITs != 0U) + { + /* Clear the Rx FIFO 1 flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs); +#else + /* Rx FIFO 1 Callback */ + HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Tx FIFO empty interrupt management ***************************************/ + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET) + { + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_FIFO_EMPTY) != RESET) + { + /* Clear the Tx FIFO empty flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxFifoEmptyCallback(hfdcan); +#else + /* Tx FIFO empty Callback */ + HAL_FDCAN_TxFifoEmptyCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Transmission Complete interrupt management *******************************/ + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TX_COMPLETE) != RESET) + { + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TX_COMPLETE) != RESET) + { + /* List of transmitted monitored buffers */ + TransmittedBuffers = hfdcan->Instance->TXBTO; + TransmittedBuffers &= hfdcan->Instance->TXBTIE; + + /* Clear the Transmission Complete flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers); +#else + /* Transmission Complete Callback */ + HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Timestamp Wraparound interrupt management ********************************/ + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET) + { + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET) + { + /* Clear the Timestamp Wraparound flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TimestampWraparoundCallback(hfdcan); +#else + /* Timestamp Wraparound Callback */ + HAL_FDCAN_TimestampWraparoundCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Timeout Occurred interrupt management ************************************/ + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET) + { + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_TIMEOUT_OCCURRED) != RESET) + { + /* Clear the Timeout Occurred flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TimeoutOccurredCallback(hfdcan); +#else + /* Timeout Occurred Callback */ + HAL_FDCAN_TimeoutOccurredCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Message RAM access failure interrupt management **************************/ + if (FDCAN_CHECK_FLAG(itflag, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET) + { + if (FDCAN_CHECK_IT_SOURCE(itsource, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET) + { + /* Clear the Message RAM access failure flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE); + + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS; + } + } + + /* Error Status interrupts management ***************************************/ + if (ErrorStatusITs != 0U) + { + /* Clear the Error flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs); +#else + /* Error Status Callback */ + HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Error interrupts management **********************************************/ + if (Errors != 0U) + { + /* Clear the Error flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors); + + /* Update error code */ + hfdcan->ErrorCode |= Errors; + } + + if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE) + { +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->ErrorCallback(hfdcan); +#else + /* Error Callback */ + HAL_FDCAN_ErrorCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group5 Callback functions + * @brief FDCAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_FDCAN_TxEventFifoCallback + (+) HAL_FDCAN_RxFifo0Callback + (+) HAL_FDCAN_RxFifo1Callback + (+) HAL_FDCAN_TxFifoEmptyCallback + (+) HAL_FDCAN_TxBufferCompleteCallback + (+) HAL_FDCAN_TxBufferAbortCallback + (+) HAL_FDCAN_HighPriorityMessageCallback + (+) HAL_FDCAN_TimestampWraparoundCallback + (+) HAL_FDCAN_TimeoutOccurredCallback + (+) HAL_FDCAN_ErrorCallback + (+) HAL_FDCAN_ErrorStatusCallback + +@endverbatim + * @{ + */ + +/** + * @brief Tx Event callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(TxEventFifoITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file + */ +} + +/** + * @brief Rx FIFO 0 callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(RxFifo0ITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxFifo0Callback could be implemented in the user file + */ +} + +/** + * @brief Rx FIFO 1 callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(RxFifo1ITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxFifo1Callback could be implemented in the user file + */ +} + +/** + * @brief Tx FIFO Empty callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file + */ +} + +/** + * @brief Transmission Complete callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param BufferIndexes Indexes of the transmitted buffers. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval None + */ +__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(BufferIndexes); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Transmission Cancellation callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param BufferIndexes Indexes of the aborted buffers. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval None + */ +__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(BufferIndexes); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file + */ +} + +/** + * @brief Timestamp Wraparound callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file + */ +} + +/** + * @brief Timeout Occurred callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file + */ +} + +/** + * @brief High Priority Message callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file + */ +} + +/** + * @brief Error callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Error status callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ErrorStatusITs indicates which Error Status interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(ErrorStatusITs); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group6 Peripheral State functions + * @brief FDCAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) HAL_FDCAN_GetState() : Return the FDCAN state. + (+) HAL_FDCAN_GetError() : Return the FDCAN error code if any. + +@endverbatim + * @{ + */ +/** + * @brief Return the FDCAN state + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL state + */ +HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan) +{ + /* Return FDCAN state */ + return hfdcan->State; +} + +/** + * @brief Return the FDCAN error code + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval FDCAN Error Code + */ +uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan) +{ + /* Return FDCAN error code */ + return hfdcan->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FDCAN_Private_Functions FDCAN Private Functions + * @{ + */ + +/** + * @brief Calculate each RAM block start address and size + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval none + */ +static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t RAMcounter; + uint32_t SramCanInstanceBase = SRAMCAN_BASE; + + if (hfdcan->Instance == FDCAN2) + { + SramCanInstanceBase += SRAMCAN_SIZE; + } + + /* Standard filter list start address */ + hfdcan->msgRam.StandardFilterSA = SramCanInstanceBase + SRAMCAN_FLSSA; + + /* Standard filter elements number */ + MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_RXGFC_LSS_Pos)); + + /* Extended filter list start address */ + hfdcan->msgRam.ExtendedFilterSA = SramCanInstanceBase + SRAMCAN_FLESA; + + /* Extended filter elements number */ + MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_RXGFC_LSE_Pos)); + + /* Rx FIFO 0 start address */ + hfdcan->msgRam.RxFIFO0SA = SramCanInstanceBase + SRAMCAN_RF0SA; + + /* Rx FIFO 1 start address */ + hfdcan->msgRam.RxFIFO1SA = SramCanInstanceBase + SRAMCAN_RF1SA; + + /* Tx event FIFO start address */ + hfdcan->msgRam.TxEventFIFOSA = SramCanInstanceBase + SRAMCAN_TEFSA; + + /* Tx FIFO/queue start address */ + hfdcan->msgRam.TxFIFOQSA = SramCanInstanceBase + SRAMCAN_TFQSA; + + /* Flush the allocated Message RAM area */ + for (RAMcounter = SramCanInstanceBase; RAMcounter < (SramCanInstanceBase + SRAMCAN_SIZE); RAMcounter += 4U) + { + *(uint32_t *)(RAMcounter) = 0x00000000U; + } +} + +/** + * @brief Copy Tx message to the message RAM. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure. + * @param pTxData pointer to a buffer containing the payload of the Tx frame. + * @param BufferIndex index of the buffer to be configured. + * @retval none + */ +static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader, + const uint8_t *pTxData, uint32_t BufferIndex) +{ + uint32_t TxElementW1; + uint32_t TxElementW2; + uint32_t *TxAddress; + uint32_t ByteCounter; + + /* Build first word of Tx header element */ + if (pTxHeader->IdType == FDCAN_STANDARD_ID) + { + TxElementW1 = (pTxHeader->ErrorStateIndicator | + FDCAN_STANDARD_ID | + pTxHeader->TxFrameType | + (pTxHeader->Identifier << 18U)); + } + else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */ + { + TxElementW1 = (pTxHeader->ErrorStateIndicator | + FDCAN_EXTENDED_ID | + pTxHeader->TxFrameType | + pTxHeader->Identifier); + } + + /* Build second word of Tx header element */ + TxElementW2 = ((pTxHeader->MessageMarker << 24U) | + pTxHeader->TxEventFifoControl | + pTxHeader->FDFormat | + pTxHeader->BitRateSwitch | + (pTxHeader->DataLength << 16U)); + + /* Calculate Tx element address */ + TxAddress = (uint32_t *)(hfdcan->msgRam.TxFIFOQSA + (BufferIndex * SRAMCAN_TFQ_SIZE)); + + /* Write Tx element header to the message RAM */ + *TxAddress = TxElementW1; + TxAddress++; + *TxAddress = TxElementW2; + TxAddress++; + + /* Write Tx payload to the message RAM */ + for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength]; ByteCounter += 4U) + { + *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) | + ((uint32_t)pTxData[ByteCounter + 2U] << 16U) | + ((uint32_t)pTxData[ByteCounter + 1U] << 8U) | + (uint32_t)pTxData[ByteCounter]); + TxAddress++; + } +} + +/** + * @} + */ +#endif /* HAL_FDCAN_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* FDCAN1 */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_flash.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_flash.c new file mode 100644 index 00000000000..7e535faa090 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_flash.c @@ -0,0 +1,969 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB C-Bus accesses to the Flash memory. + It implements the erase and program Flash memory operations and the read + and write protection mechanisms. + + [..] The Flash memory interface implements the TrustZone security features (TZ) supported + by ARM Cortex-M33 core (CM33). + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Option bytes programming + (+) TrustZone aware + (+) Watermark-based area protection including PCROP and secure hide area + (+) Block-based page protection + (+) Error code correction (ECC) : Data in flash are 137-bits word + (9 bits added per quad-word) + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32H7RSxx devices. + + (#) Flash Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: quad-words and burst program (8 quad-words) + (++) There are two modes of programming : + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions : + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Callback functions are called when the flash operations are finished : + HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise + HAL_FLASH_OperationErrorCallback() + (++) Get error flag status by calling HAL_GetError() + + (#) Option bytes management functions : + (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and + HAL_FLASH_OB_Lock() functions + (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function. + In this case, a reset is generated + + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the Flash power-down during low-power run and sleep modes + (+) Enable/Disable the Flash interrupts + (+) Monitor the Flash flags status + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/** + * @brief Variable used for Program/Erase sectors under interruption + */ +FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ + .ErrorCode = HAL_FLASH_ERROR_NONE, \ + .ProcedureOnGoing = 0U, \ + .Address = 0U, \ + .Sector = 0U, \ + .NbSectorsToErase = 0U + }; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_Program_Byte(uint32_t Address, uint32_t DataAddress); +static void FLASH_Program_HalfWord(uint32_t Address, uint32_t DataAddress); +static void FLASH_Program_Word(uint32_t Address, uint32_t DataAddress); +static void FLASH_Program_DoubleWord(uint32_t Address, uint32_t DataAddress); +static void FLASH_Program_QuadWord(uint32_t Address, uint32_t DataAddress); +static void FLASH_Program_OTPHalfWord(uint32_t Address, uint32_t DataAddress); +static void FLASH_Program_OTPWord(uint32_t Address, uint32_t DataAddress); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program a data at a specified address. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + switch (TypeProgram) + { + case FLASH_TYPEPROGRAM_BYTE: + /* Program a byte (8-bit) at a specified address */ + FLASH_Program_Byte(Address, DataAddress); + break; + + case FLASH_TYPEPROGRAM_HALFWORD: + /* Program a half-word (16-bit) at a specified address */ + FLASH_Program_HalfWord(Address, DataAddress); + break; + + case FLASH_TYPEPROGRAM_WORD: + /* Program a word (32-bit) at a specified address */ + FLASH_Program_Word(Address, DataAddress); + break; + + case FLASH_TYPEPROGRAM_DOUBLEWORD: + /* Program a double-word (64-bit) at a specified address */ + FLASH_Program_DoubleWord(Address, DataAddress); + break; + + case FLASH_TYPEPROGRAM_QUADWORD: + /* Program a quad-word (128-bit) at a specified address */ + FLASH_Program_QuadWord(Address, DataAddress); + break; + + case FLASH_TYPEPROGRAM_OTP_HALFWORD: + /* Program a half-word (16-bit) at a OTP address */ + FLASH_Program_OTPHalfWord(Address, DataAddress); + break; + + case FLASH_TYPEPROGRAM_OTP_WORD: + /* Program a word (32-bit) at a OTP address */ + FLASH_Program_OTPWord(Address, DataAddress); + break; + + default: + status = HAL_ERROR; + break; + } + + if (status != HAL_ERROR) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG (and FW Bit in non quad-word mode) */ + CLEAR_BIT(FLASH->CR, (TypeProgram & ~(FLASH_WORD_SIZE_MASK))); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + /* return status */ + return status; +} + +/** + * @brief Program a data at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = TypeProgram; + pFlash.Address = Address; + + /* Enable End of Operation and Error interrupts */ + SET_BIT(FLASH->IER, (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | FLASH_IT_STRBERR | FLASH_IT_INCERR)); + + switch (TypeProgram) + { + case FLASH_TYPEPROGRAM_BYTE: + /* Program a byte (8-bit) at a specified address */ + FLASH_Program_Byte(Address, DataAddress); + break; + + case FLASH_TYPEPROGRAM_HALFWORD: + /* Program a half-word (16-bit) at a specified address */ + FLASH_Program_HalfWord(Address, DataAddress); + break; + + case FLASH_TYPEPROGRAM_WORD: + /* Program a word (32-bit) at a specified address */ + FLASH_Program_Word(Address, DataAddress); + break; + + case FLASH_TYPEPROGRAM_DOUBLEWORD: + /* Program a double-word (64-bit) at a specified address */ + FLASH_Program_DoubleWord(Address, DataAddress); + break; + + case FLASH_TYPEPROGRAM_QUADWORD: + /* Program a quad-word (128-bit) at a specified address */ + FLASH_Program_QuadWord(Address, DataAddress); + break; + + case FLASH_TYPEPROGRAM_OTP_HALFWORD: + /* Program a half-word (16-bit) at a OTP address */ + FLASH_Program_OTPHalfWord(Address, DataAddress); + break; + + case FLASH_TYPEPROGRAM_OTP_WORD: + /* Program a word (32-bit) at a OTP address */ + FLASH_Program_OTPWord(Address, DataAddress); + break; + + default: + status = HAL_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + break; + } + } + + return status; +} + +/** + * @brief Handle FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t param = 0U; + uint32_t error; + + /* Save Flash errors */ + error = FLASH->ISR & FLASH_FLAG_ISR_ERRORS; + error |= (FLASH->OPTISR & FLASH_FLAG_OPTISR_ERRORS); + + /* Set parameter of the callback */ + if (pFlash.ProcedureOnGoing == FLASH_TYPEERASE_SECTORS) + { + param = pFlash.Sector; + } + else if ((pFlash.ProcedureOnGoing & FLASH_CR_PG) != 0U) + { + param = pFlash.Address; + } + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } + + /* Clear operation bit on the on-going procedure */ + CLEAR_BIT(FLASH->CR, (pFlash.ProcedureOnGoing & ~(FLASH_WORD_SIZE_MASK))); + + /* Check FLASH operation error flags */ + if (error != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= error; + + /* Clear error programming flags */ + FLASH->ICR = (error & FLASH_FLAG_ISR_ERRORS); + FLASH->OPTICR = (error & FLASH_FLAG_OPTISR_ERRORS); + + /* Stop the procedure ongoing */ + pFlash.ProcedureOnGoing = 0U; + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(param); + } + + /* Check FLASH End of Operation flag */ + if ((FLASH->ISR & FLASH_FLAG_EOP) != 0U) + { + /* Clear FLASH End of Operation pending bit */ + FLASH->ICR = FLASH_FLAG_EOP; + + if (pFlash.ProcedureOnGoing == FLASH_TYPEERASE_SECTORS) + { + /* Nb of sectors to erase can be decreased */ + pFlash.NbSectorsToErase--; + + /* Check if there are still sectors to erase */ + if (pFlash.NbSectorsToErase != 0U) + { + /* Increment sector number */ + pFlash.Sector++; + FLASH_SectorErase(pFlash.Sector); + } + else + { + /* No more sectors to Erase */ + pFlash.ProcedureOnGoing = 0U; + param = 0xFFFFFFFFU; + } + } + else + { + /*Clear the procedure ongoing*/ + pFlash.ProcedureOnGoing = 0U; + } + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(param); + } + + if (pFlash.ProcedureOnGoing == 0U) + { + /* Disable End of Operation and Error interrupts */ + CLEAR_BIT(FLASH->IER, (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | FLASH_IT_STRBERR | FLASH_IT_INCERR)); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + + /* Check ECC Correction Error */ + if ((FLASH->IER & FLASH_IT_SNECCERR) != 0U) + { + if ((FLASH->ISR & FLASH_FLAG_SNECCERR) != 0U) + { + /* Call User callback */ + HAL_FLASHEx_EccCorrectionCallback(); + + /* Clear ECC correction flag in order to allow new ECC error record */ + FLASH->ICR = FLASH_FLAG_SNECCERR; + } + } + + /* Check ECC Detection Error */ + if ((FLASH->IER & FLASH_IT_DBECCERR) != 0U) + { + if ((FLASH->ISR & FLASH_FLAG_DBECCERR) != 0U) + { + /* Call User callback */ + HAL_FLASHEx_EccDetectionCallback(); + + /* Clear ECC detection flag in order to allow new ECC error record */ + FLASH->ICR = FLASH_FLAG_DBECCERR; + } + } +} + +/** + * @brief FLASH end of operation interrupt callback. + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sector Erase: Sector which has been erased + * (if 0xFFFFFFFF, it means that all the selected sectors have been erased) + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback. + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sector Erase: Sector number which returned an error + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* verify Flash is unlocked */ + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH control register access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_LOCK); + + /* verify Flash is locked */ + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) + { + return HAL_OK; + } + + return HAL_ERROR; +} + +/** + * @brief Unlock the FLASH Option Bytes Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) + { + /* Authorizes the Option Byte register programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + + /* Verify that the Option Bytes are unlocked */ + if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Bytes Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK); + + /* Verify that the Option Bytes are locked */ + if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) + { + return HAL_OK; + } + + return HAL_ERROR; +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode The returned value can be: + * @arg HAL_FLASH_ERROR_NONE: No error set + * @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error + * @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error + * @arg HAL_FLASH_ERROR_STRB: FLASH Strobe error + * @arg HAL_FLASH_ERROR_INC: FLASH Inconsistency error + * @arg HAL_FLASH_ERROR_RDS: FLASH Read security error + * @arg HAL_FLASH_ERROR_SNECC: FLASH ECC single error + * @arg HAL_FLASH_ERROR_DBECC: FLASH ECC double error + * @arg HAL_FLASH_ERROR_CRC: FLASH CRC error + * @arg HAL_FLASH_ERROR_KDR: FLASH Key data register error + * @arg HAL_FLASH_ERROR_OBC: FLASH Options byte change error + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t timeout = HAL_GetTick() + Timeout; + uint32_t error; + + while ((FLASH->SR & FLASH_SR_QW) != 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (HAL_GetTick() >= timeout) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH operation error flags */ + error = (FLASH->ISR & FLASH_FLAG_ISR_ERRORS); + error |= (FLASH->OPTISR & FLASH_FLAG_OPTISR_ERRORS); + + if (error != 0U) + { + /*Save the error code*/ + pFlash.ErrorCode |= error; + + /* Clear error programming flags */ + FLASH->ICR = (error & FLASH_FLAG_ISR_ERRORS); + FLASH->OPTICR = (error & FLASH_FLAG_OPTISR_ERRORS); + + return HAL_ERROR; + } + + /* Check FLASH End of Operation flag */ + if ((FLASH->ISR & FLASH_FLAG_EOP) != 0U) + { + /* Clear FLASH End of Operation pending bit */ + FLASH->ICR = FLASH_FLAG_EOP; + } + + /* If there is no error flag set */ + return HAL_OK; +} + +/** + * @brief Program a byte (8-bit) at a specified address. + * @param Address specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed. + * @retval None + */ +static void FLASH_Program_Byte(uint32_t Address, uint32_t DataAddress) +{ + uint8_t *dest_addr = (uint8_t *)Address; + uint8_t *src_addr = (uint8_t *)DataAddress; + uint32_t primask_bit; + + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address)); + + /* Set PG bit */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program the byte */ + *dest_addr = *src_addr; + + __ISB(); + __DSB(); + + /* Set FW bit */ + SET_BIT(FLASH->CR, FLASH_CR_FW); + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @param Address specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint32_t DataAddress) +{ + uint16_t *dest_addr = (uint16_t *)Address; + uint16_t *src_addr = (uint16_t *)DataAddress; + uint32_t primask_bit; + + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address)); + + /* Set PG bit */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program the half-word */ + *dest_addr = *src_addr; + + __ISB(); + __DSB(); + + /* Set FW bit */ + SET_BIT(FLASH->CR, FLASH_CR_FW); + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @brief Program a word (32-bit) at a specified address. + * @param Address specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed. + * @retval None + */ +static void FLASH_Program_Word(uint32_t Address, uint32_t DataAddress) +{ + uint8_t index = 2; + uint16_t *dest_addr = (uint16_t *)Address; + uint16_t *src_addr = (uint16_t *)DataAddress; + uint32_t primask_bit; + + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address)); + + /* Set PG bit */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program the word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + index--; + } while (index != 0U); + + __ISB(); + __DSB(); + + /* Set FW bit */ + SET_BIT(FLASH->CR, FLASH_CR_FW); + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @brief Program a double-word (64-bit) at a specified address. + * @param Address specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed. + * @retval None + */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint32_t DataAddress) +{ + uint8_t index = 4; + uint16_t *dest_addr = (uint16_t *)Address; + uint16_t *src_addr = (uint16_t *)DataAddress; + uint32_t primask_bit; + + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address)); + + /* Set PG bit */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program the double-word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + index--; + } while (index != 0U); + + __ISB(); + __DSB(); + + /* Set FW bit */ + SET_BIT(FLASH->CR, FLASH_CR_FW); + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @brief Program a quad-word (128-bit) at a specified address. + * @param Address specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed. + * @retval None + */ +static void FLASH_Program_QuadWord(uint32_t Address, uint32_t DataAddress) +{ + uint8_t index = 8; + uint16_t *dest_addr = (uint16_t *)Address; + uint16_t *src_addr = (uint16_t *)DataAddress; + uint32_t primask_bit; + + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address)); + + /* Set PG bit */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program the quad-word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + index--; + } while (index != 0U); + + __ISB(); + __DSB(); + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @brief Program a half-word (16-bit) at a OTP address. + * @param Address specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed. + * @retval None + */ +static void FLASH_Program_OTPHalfWord(uint32_t Address, uint32_t DataAddress) +{ + uint16_t *dest_addr = (uint16_t *)Address; + uint16_t *src_addr = (uint16_t *)DataAddress; + uint32_t primask_bit; + + /* Check the parameters */ + assert_param(IS_FLASH_OTP_ADDRESS(Address)); + + /* Set PG_OTP bit */ + SET_BIT(FLASH->CR, FLASH_CR_PG_OTP); + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program the half-word */ + *dest_addr = *src_addr; + + __ISB(); + __DSB(); + + /* Set FW bit */ + SET_BIT(FLASH->CR, FLASH_CR_FW); + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @brief Program a word (32-bit) at a OTP address. + * @param Address specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed. + * @retval None + */ +static void FLASH_Program_OTPWord(uint32_t Address, uint32_t DataAddress) +{ + uint8_t index = 2; + uint16_t *dest_addr = (uint16_t *)Address; + uint16_t *src_addr = (uint16_t *)DataAddress; + uint32_t primask_bit; + + /* Check the parameters */ + assert_param(IS_FLASH_OTP_ADDRESS(Address)); + + /* Set PG_OTP bit */ + SET_BIT(FLASH->CR, FLASH_CR_PG_OTP); + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program the word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + index--; + } while (index != 0U); + + __ISB(); + __DSB(); + + /* Set FW bit */ + SET_BIT(FLASH->CR, FLASH_CR_FW); + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_flash_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_flash_ex.c new file mode 100644 index 00000000000..7be7eacc0dd --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_flash_ex.c @@ -0,0 +1,1306 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extended peripheral: + * + Extended programming operations functions + * + @verbatim + ============================================================================== + ##### Flash Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32H7RSxx + devices contains the following additional features + + (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write + capability (RWW) + (+) Dual bank memory organization + (+) Watermark-based secure area including PCROP and secure hide areas + (+) Block-based secure pages + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32H7RSxx devices. It includes: + (#) Flash Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: page Erase and Bank/Mass Erase + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to: + (++) Configure the write protection for each area + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Configure the watermark security for each area including PCROP and secure hide areas + (++) Configure the boot lock (BOOT_LOCK) + (++) Configure the Boot addresses + + (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to: + (++) Get the value of a write protection area + (++) Know if the read protection is activated + (++) Get the value of the user Option Bytes + (++) Get the configuration of a watermark security area including PCROP and secure hide areas + (++) Get the boot lock (BOOT_LOCK) configuration + (++) Get the value of a boot address + + (#) Block-based secure / privilege area configuration function: Use HAL_FLASHEx_ConfigBBAttributes() + (++) Bit-field allowing to secure or un-secure each page + (++) Bit-field allowing to privilege or un-privilege each page + + (#) Get the block-based secure / privilege area configuration function: Use HAL_FLASHEx_GetBBSec() + (++) Return the configuration of the block-based security and privilege for all the pages + + (#) Activation of the secure hide area function: Use HAL_FLASHEx_EnableSecHideProtection() + (++) Deny the access to the secure hide area + + (#) Privilege mode configuration function: Use HAL_FLASHEx_ConfigPrivMode() + (++) FLASH register can be protected against non-privilege accesses + + (#) Get the privilege mode configuration function: Use HAL_FLASHEx_GetPrivMode() + (++) Return if the FLASH registers are protected against non-privilege accesses + + (#) Security inversion configuration function: Use HAL_FLASHEx_ConfigSecInversion() + (++) FLASH secure state can be override + + (#) Get the security inversion configuration function: Use HAL_FLASHEx_GetSecInversion() + (++) Return if FLASH secure state is override + + (#) Enable bank low-power mode function: Use HAL_FLASHEx_EnablePowerDown() + (++) Enable low-power mode for Flash Bank 1 and/or Bank 2 + + (#) Enable low-power read mode function: Use HAL_FLASHEx_ConfigLowPowerRead() + (++) Enable low-power read mode for Flash memory + + (#) Get the low-power read mode configuration function: Use HAL_FLASHEx_GetLowPowerRead() + (++) Return if FLASH is in low-power read mode or normal read mode + + (#) Get Flash operation function: Use HAL_FLASHEx_GetOperation() + (++) Return information about the on-going Flash operation. After a + system reset, return information about the interrupted Flash operation, if any. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH Extended HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define SYSTEM_FLASH_SIZE 0x00020000UL /*!< System Flash size : 128 KB */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +static void FLASH_MassErase(void); + +static void FLASH_OB_WRPConfig(uint32_t WRPState, uint32_t WRPSector); +static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig1, uint32_t UserConfig2); +static void FLASH_OB_HDPConfig(uint32_t HDPStartPage, uint32_t HDPEndPage); +static void FLASH_OB_NVConfig(uint32_t NVState); + +static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector); +static void FLASH_OB_GetUser(uint32_t *UserConfig1, uint32_t *UserConfig2); +static void FLASH_OB_GetHDP(uint32_t *HDPStartPage, uint32_t *HDPEndPage); +static uint32_t FLASH_OB_GetNV(void); +static uint32_t FLASH_OB_GetRoT(void); +static uint32_t FLASH_OB_GetEpoch(void); + +static void FLASH_CRC_AddSector(uint32_t Sector); +static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr); +static HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Exported functions -------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + programming operations Operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors. + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] SectorError pointer to variable that contains the configuration + * information on faulty sector in case of error (0xFFFFFFFF means that all + * the sectors have been correctly erased). + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(const FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) +{ + HAL_StatusTypeDef status; + uint32_t sector_index; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /* Mass erase to be done */ + FLASH_MassErase(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + else + { + /*Initialization of SectorError variable*/ + *SectorError = 0xFFFFFFFFU; + + for (sector_index = pEraseInit->Sector; sector_index < (pEraseInit->Sector + pEraseInit->NbSectors); + sector_index++) + { + FLASH_SectorErase(sector_index); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty sector */ + *SectorError = sector_index; + break; + } + } + } + + /* If the erase operation is completed, disable the associated bits */ + CLEAR_BIT(FLASH->CR, (pEraseInit->TypeErase | FLASH_CR_SSN)); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled. + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(const FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = pEraseInit->TypeErase; + + /* Enable End of Operation and Error interrupts */ + SET_BIT(FLASH->IER, (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | FLASH_IT_STRBERR | FLASH_IT_INCERR)); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /* Mass erase to be done */ + FLASH_MassErase(); + } + else + { + /* Erase by sector to be done */ + pFlash.NbSectorsToErase = pEraseInit->NbSectors; + pFlash.Sector = pEraseInit->Sector; + + /* Erase first sector and wait for IT */ + FLASH_SectorErase(pEraseInit->Sector); + } + } + + return status; +} + +/** + * @brief Program Option bytes. + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @note To configure any option bytes, the option lock bit OPTLOCK must be + * cleared with the call of HAL_FLASH_OB_Unlock() function. + * @note New option bytes configuration will be taken into account in two cases: + * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() + * - after a power reset (BOR reset or exit from Standby/Shutdown modes) + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(const FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if ((status == HAL_OK) && (pOBInit->OptionType != 0U)) + { + /* Set PG_OPT Bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT); + + /* Write protection configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U) + { + /* Configure of Write protection on the selected area */ + FLASH_OB_WRPConfig(pOBInit->WRPState, pOBInit->WRPSector); + } + + /* User Configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) + { + /* Configure the user option bytes */ + FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig1, pOBInit->USERConfig2); + } + + /* HDP configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_HDP) != 0U) + { + /* Configure the HDP Protection */ + FLASH_OB_HDPConfig(pOBInit->HDPStartPage, pOBInit->HDPEndPage); + } + + /* Non-volatile state configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_NV) != 0U) + { + /* Configure the non-volatile state */ + FLASH_OB_NVConfig(pOBInit->NVState); + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* Clear PG_OPT Bit */ + CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option bytes configuration. + * @param pOBInit pointer to an FLASH_OBInitStruct structure that contains the + * configuration information. + * @note The fields pOBInit->WRPArea, pOBInit->WMSecConfig and pOBInit->BootAddrConfig + * should indicate which area/address is requested for the WRP, WM Security or + * Boot Address, else no information will be returned + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + /* Get write protection on the selected area */ + FLASH_OB_GetWRP(&(pOBInit->WRPState), &(pOBInit->WRPSector)); + + /* Get the user option bytes */ + FLASH_OB_GetUser(&(pOBInit->USERConfig1), &(pOBInit->USERConfig2)); + + /* Get the HDP Protection */ + FLASH_OB_GetHDP(&(pOBInit->HDPStartPage), &(pOBInit->HDPEndPage)); + + /* Get the non-volatile state */ + pOBInit->NVState = FLASH_OB_GetNV(); + + /* Get the Root-Of-Trust configuration */ + pOBInit->ROTConfig = FLASH_OB_GetRoT(); + + /* Get the epoch */ + pOBInit->EPOCH = FLASH_OB_GetEpoch(); +} + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group2 Extended CRC operation functions + * @brief Extended CRC operation functions + * +@verbatim + =============================================================================== + ##### Extended CRC operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + CRC Operations. + +@endverbatim + * @{ + */ +/** + * @brief Configure the OTP Lock. + * + * @note To configure the OTP Lock options, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_OB_Unlock() function. + * + * @param OTPLBlock Specifies the block(s) to be OTP locked (used for OPTIONBYTE_OTPL). + * The value of this parameter depend on device used within the same series + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OTPLockConfig(uint32_t OTPLBlock) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_OB_OTP_BLOCK(OTPLBlock)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Set the bit for the OTP programmation */ + SET_BIT(FLASH->CR, FLASH_CR_PG_OTP); + + /* Set PG_OPT Bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT); + + /* Configure the write protected area */ + MODIFY_REG(FLASH->OTPLSRP, FLASH_OTPLSRP_OTPL, (OTPLBlock & FLASH_OTPLSRP_OTPL)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* Clear PG_OPT Bit */ + CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT); + + /* Clear the bit for the OTP programmation */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG_OTP); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Return the FLASH OTP Lock Option Bytes value. + * + * @retval Status of the OTP Lock + */ +uint32_t HAL_FLASHEx_GetOTPLock(void) +{ + return (FLASH->OTPLSR & FLASH_OTPLSR_OTPL); +} + +/** + * @brief Configure the Keys. + * + * @note To configure the Keys options, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_OB_Unlock() function. + * + * @param pKeyConfig Key(s) to be configured. + * + * @param pKey Address of the key + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_KeyConfig(const FLASH_KeyConfigTypeDef *pKeyConfig, const uint32_t *pKey) +{ + uint32_t index; + uint32_t index_max; + const uint32_t *pdata; + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_KEY_INDEX(pKeyConfig->Index)); + assert_param(IS_KEY_SIZE(pKeyConfig->Size)); + assert_param(IS_KEY_HDPL_LEVEL(pKeyConfig->HDPLLevel)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Set PG_OPT Bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT); + + switch (pKeyConfig->Size) + { + case FLASH_KEY_32_BITS : + index_max = 1U; + break; + + case FLASH_KEY_64_BITS : + index_max = 2U; + break; + + case FLASH_KEY_128_BITS : + index_max = 4U; + break; + + case FLASH_KEY_256_BITS : + index_max = 8U; + break; + + default: + /* This case should not occur */ + index_max = 0U; + break; + } + + pdata = pKey; + for (index = 0U; index < index_max; index++) + { + FLASH->OBKDR[index] = pdata[index]; + } + + MODIFY_REG(FLASH->OBKCR, (FLASH_OBKCR_OBKINDEX | FLASH_OBKCR_NEXTKL | FLASH_OBKCR_OBKSIZE), + (pKeyConfig->Index | pKeyConfig->HDPLLevel | pKeyConfig->Size)); + + SET_BIT(FLASH->OBKCR, (FLASH_OBKCR_KEYSTART | FLASH_OBKCR_KEYPROG)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + CLEAR_BIT(FLASH->OBKCR, FLASH_OBKCR_KEYPROG); + + /* Clear PG_OPT Bit */ + CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Load and optionally return the FLASH Option Bytes Key value. + * + * @param pKeyConfig Configuration of the key to be loaded and optionally returned + * + * @param pKey Address to return the FLASH Option Bytes Key value if not NULL. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_GetKey(const FLASH_KeyConfigTypeDef *pKeyConfig, uint32_t *pKey) +{ + uint32_t index; + uint32_t *pdata; + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_KEY_INDEX(pKeyConfig->Index)); + assert_param(IS_KEY_HDPL_LEVEL(pKeyConfig->HDPLLevel)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Set PG_OPT Bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT); + + /* Configure index and HDPL level */ + MODIFY_REG(FLASH->OBKCR, (FLASH_OBKCR_OBKINDEX | FLASH_OBKCR_NEXTKL | FLASH_OBKCR_OBKSIZE | FLASH_OBKCR_KEYPROG), + (pKeyConfig->Index | pKeyConfig->HDPLLevel)); + + /* Set the start bit to get the key value */ + SET_BIT(FLASH->OBKCR, FLASH_OBKCR_KEYSTART); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if ((status == HAL_OK) && (pKey != NULL)) + { + pdata = pKey; + for (index = 0U; index < 8U; index++) + { + *pdata = FLASH->OBKDR[index]; + pdata++; + } + } + + /* Clear PG_OPT Bit */ + CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a CRC computation on the specified FLASH memory area + * @param pCRCInit pointer to an FLASH_CRCInitTypeDef structure that + * contains the configuration information for the CRC computation. + * @param CRC_Result pointer to CRC result + * @note CRC computation uses CRC-32 (Ethernet) polynomial 0x4C11DB7 + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(const FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result) +{ + HAL_StatusTypeDef status; + uint32_t sector_index; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPE_CRC(pCRCInit->TypeCRC)); + assert_param(IS_FLASH_BURST_SIZE_CRC(pCRCInit->BurstSize)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Enable CRC feature */ + SET_BIT(FLASH->CR, FLASH_CR_CRC_EN); + + /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */ + FLASH->ICR = (FLASH_ICR_CRCRDERRF | FLASH_ICR_CRCENDF); + + /* Clear current CRC result and program burst size */ + MODIFY_REG(FLASH->CRCCR, (FLASH_CRCCR_CLEAN_CRC | FLASH_CRCCR_CRC_BURST), + (FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize)); + + if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS) + { + /* Select CRC by sector and clear sectors list */ + SET_BIT(FLASH->CRCCR, (FLASH_CRCCR_CRC_BY_SECT | FLASH_CRCCR_CLEAN_SECT)); + + /* Select CRC sectors */ + for (sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++) + { + FLASH_CRC_AddSector(sector_index); + } + } + else if (pCRCInit->TypeCRC == FLASH_CRC_BANK) + { + /* Select CRC by sector and all sectors */ + SET_BIT(FLASH->CRCCR, (FLASH_CRCCR_CRC_BY_SECT | FLASH_CRCCR_ALL_SECT)); + } + else + { + /* Select CRC by address */ + CLEAR_BIT(FLASH->CRCCR, FLASH_CRCCR_CRC_BY_SECT); + + /* Select CRC start and end addresses */ + FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr); + } + + /* Start the CRC calculation */ + SET_BIT(FLASH->CRCCR, FLASH_CRCCR_START_CRC); + + /* Wait on CRC busy flag */ + status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* Return CRC result */ + (*CRC_Result) = FLASH->CRCDATAR; + + /* Disable CRC feature */ + CLEAR_BIT(FLASH->CR, FLASH_CR_CRC_EN); + + /* Clear CRC flags */ + FLASH->ICR = (FLASH_ICR_CRCRDERRF | FLASH_ICR_CRCENDF); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + + return status; +} + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group3 Extended ECC operation functions + * @brief Extended ECC operation functions + * +@verbatim + =============================================================================== + ##### Extended ECC operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + ECC Operations. + +@endverbatim + * @{ + */ +/** + * @brief Enable ECC correction interrupt + * @retval None + */ +void HAL_FLASHEx_EnableEccCorrectionInterrupt(void) +{ + __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR); +} + +/** + * @brief Disable ECC correction interrupt + * @retval None + */ +void HAL_FLASHEx_DisableEccCorrectionInterrupt(void) +{ + __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR); +} + +/** + * @brief Enable ECC detection interrupt + * @retval None + */ +void HAL_FLASHEx_EnableEccDetectionInterrupt(void) +{ + __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR); +} + +/** + * @brief Disable ECC detection interrupt + * @retval None + */ +void HAL_FLASHEx_DisableEccDetectionInterrupt(void) +{ + __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR); +} + +/** + * @brief Get the ECC error information. + * @param pData Pointer to an FLASH_EccInfoTypeDef structure that contains the + * ECC error information. + * @note This function should be called before ECC bit is cleared + * (in callback function) + * @retval None + */ +void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData) +{ + /* Check Null pointer */ + assert_param(pData != NULL); + + /* Set address which generate ECC error */ + if ((FLASH->ISR & FLASH_FLAG_SNECCERR) != 0U) + { + pData->Address = FLASH->ECCSFADDR; + } + else + { + pData->Address = FLASH->ECCDFADDR; + } + + /* Set area according address */ + if (IS_FLASH_MAIN_MEM_ADDRESS(pData->Address)) + { + pData->Area = FLASH_ECC_AREA_USER_BANK1; + } + else if (IS_FLASH_OTP_ADDRESS(pData->Address)) + { + pData->Area = FLASH_ECC_AREA_OTP; + } + else if ((pData->Address >= SYSTEM_FLASH_BASE) && + (pData->Address < (SYSTEM_FLASH_BASE + SYSTEM_FLASH_SIZE))) + { + pData->Area = FLASH_ECC_AREA_SYSTEM; + } + else + { + pData->Area = FLASH_ECC_AREA_READ_ONLY; + } + + /* Set Master which initiates transaction. On H7RS, it's necessary CPU1 */ + pData->MasterID = FLASH_ECC_MASTER_CPU1; +} + +/** + * @brief Handle Flash ECC Detection interrupt request. + * @note On STM32H7RS, this Irq Handler should be called in Bus Fault + * interrupt subroutine. + * @retval None + */ +void HAL_FLASHEx_ECCD_IRQHandler(void) +{ + /* Check ECC Detection Error */ + if ((FLASH->ISR & FLASH_FLAG_DBECCERR) != 0U) + { + /* Call User callback */ + HAL_FLASHEx_EccDetectionCallback(); + + /* Clear ECC detection flag in order to allow new ECC error record */ + FLASH->ICR = FLASH_FLAG_DBECCERR; + } +} + +/** + * @brief FLASH ECC Correction interrupt callback. + * @retval None + */ +__weak void HAL_FLASHEx_EccCorrectionCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASHEx_EccCorrectionCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH ECC Detection interrupt callback. + * @retval None + */ +__weak void HAL_FLASHEx_EccDetectionCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASHEx_EccDetectionCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ +/** + * @brief Mass erase of FLASH memory. + * @retval None + */ +static void FLASH_MassErase(void) +{ + /* Set the Mass Erase Bit and proceed to erase */ + SET_BIT(FLASH->CR, (FLASH_CR_BER | FLASH_CR_START)); +} + +/** + * @brief Erase the specified FLASH memory sector. + * @param Sector FLASH sector to erase + * This parameter must be a value between 0 and (max number of sectors in the bank - 1) + * @retval None + */ +void FLASH_SectorErase(uint32_t Sector) +{ + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + + /* Proceed to erase the page */ + MODIFY_REG(FLASH->CR, (FLASH_CR_SSN | FLASH_CR_SER | FLASH_CR_START), \ + ((Sector << FLASH_CR_SSN_Pos) | FLASH_CR_SER | FLASH_CR_START)); +} + +/** + * @brief Configure the write protection of the desired sectors. + * + * @note To configure the WRP options, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_OB_Unlock() function. + * + * @param WRPState + * + * @param WRPSector + * + * @retval None + */ +static void FLASH_OB_WRPConfig(uint32_t WRPState, uint32_t WRPSector) +{ + /* Check the parameters */ + assert_param(IS_OB_WRPSTATE(WRPState)); + + /* Configure the write protected area */ + if (WRPState == OB_WRPSTATE_DISABLE) + { + FLASH->WRPSRP |= (WRPSector & FLASH_WRPSRP_WRPS); + } + else if (WRPState == OB_WRPSTATE_ENABLE) + { + FLASH->WRPSRP &= (~(WRPSector & FLASH_WRPSRP_WRPS)); + } + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } +} + +/** + * @brief Program the FLASH User Option Byte. + * + * @note To configure the user option bytes, the option lock bit OPTLOCK must + * be cleared with the call of the HAL_FLASH_OB_Unlock() function. + * @param UserType: The FLASH User Option Bytes to be modified. + * This parameter can be a combination of @ref FLASH_OB_USER_TYPE + * @param UserConfig1 The selected User Option Bytes values + * @param UserConfig2 The selected User Option Bytes values + * @retval None + */ +static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig1, uint32_t UserConfig2) +{ + uint32_t optr_reg_val = 0; + uint32_t optr_reg_mask = 0; + + /* Check the parameters */ + assert_param(IS_OB_USER_TYPE(UserType)); + + if ((UserType & OB_USER_BOR_LEV) != 0U) + { + /* BOR level option byte should be modified */ + assert_param(IS_OB_USER_BOR_LEVEL(UserConfig1 & FLASH_OBW1SR_BOR_LEVEL)); + + /* Set value and mask for BOR level option byte */ + optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_BOR_LEVEL); + optr_reg_mask |= FLASH_OBW1SR_BOR_LEVEL; + } + + if ((UserType & OB_USER_IWDG_SW) != 0U) + { + /* IWDG1_HW option byte should be modified */ + assert_param(IS_OB_USER_IWDG(UserConfig1 & FLASH_OBW1SR_IWDG_HW)); + + /* Set value and mask for IWDG1_HW option byte */ + optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_IWDG_HW); + optr_reg_mask |= FLASH_OBW1SR_IWDG_HW; + } + + if ((UserType & OB_USER_NRST_STOP) != 0U) + { + /* NRST_STOP_D1 option byte should be modified */ + assert_param(IS_OB_USER_STOP(UserConfig1 & FLASH_OBW1SR_NRST_STOP)); + + /* Set value and mask for NRST_STOP_D1 option byte */ + optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_NRST_STOP); + optr_reg_mask |= FLASH_OBW1SR_NRST_STOP; + } + + if ((UserType & OB_USER_NRST_STDBY) != 0U) + { + /* NRST_STBY_D1 option byte should be modified */ + assert_param(IS_OB_USER_STANDBY(UserConfig1 & FLASH_OBW1SR_NRST_STBY)); + + /* Set value and mask for NRST_STBY_D1 option byte */ + optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_NRST_STBY); + optr_reg_mask |= FLASH_OBW1SR_NRST_STBY; + } + + if ((UserType & OB_USER_XSPI1_HSLV) != 0U) + { + /* XSPI1_HSLV option byte should be modified */ + assert_param(IS_OB_USER_XSPI1_HSLV(UserConfig1 & FLASH_OBW1SR_XSPI1_HSLV)); + + /* Set value and mask for XSPI1_HSLV option byte */ + optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_XSPI1_HSLV); + optr_reg_mask |= FLASH_OBW1SR_XSPI1_HSLV; + } + + if ((UserType & OB_USER_XSPI2_HSLV) != 0U) + { + /* XSPI2_HSLV option byte should be modified */ + assert_param(IS_OB_USER_XSPI2_HSLV(UserConfig1 & FLASH_OBW1SR_XSPI2_HSLV)); + + /* Set value and mask for XSPI2_HSLV option byte */ + optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_XSPI2_HSLV); + optr_reg_mask |= FLASH_OBW1SR_XSPI2_HSLV; + } + + if ((UserType & OB_USER_IWDG_STOP) != 0U) + { + /* IWDG_FZ_STOP option byte should be modified */ + assert_param(IS_OB_USER_IWDG_STOP(UserConfig1 & FLASH_OBW1SR_IWDG_FZ_STOP)); + + /* Set value and mask for IWDG_FZ_STOP option byte */ + optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_IWDG_FZ_STOP); + optr_reg_mask |= FLASH_OBW1SR_IWDG_FZ_STOP; + } + + if ((UserType & OB_USER_IWDG_STDBY) != 0U) + { + /* IWDG_FZ_SDBY option byte should be modified */ + assert_param(IS_OB_USER_IWDG_STDBY(UserConfig1 & FLASH_OBW1SR_IWDG_FZ_STBY)); + + /* Set value and mask for IWDG_FZ_SDBY option byte */ + optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_IWDG_FZ_STBY); + optr_reg_mask |= FLASH_OBW1SR_IWDG_FZ_STBY; + } + + if ((UserType & OB_USER_VDDIO_HSLV) != 0U) + { + /* VDDIO_HSLV option byte should be modified */ + assert_param(IS_OB_USER_VDDIO_HSLV(UserConfig1 & FLASH_OBW1SR_VDDIO_HSLV)); + + /* Set value and mask for VDDIO_HSLV option byte */ + optr_reg_val |= (UserConfig1 & FLASH_OBW1SR_VDDIO_HSLV); + optr_reg_mask |= FLASH_OBW1SR_VDDIO_HSLV; + } + + /* Configure the option bytes register 1 if necessary */ + if (optr_reg_mask != 0U) + { + MODIFY_REG(FLASH->OBW1SRP, optr_reg_mask, optr_reg_val); + } + + optr_reg_val = 0; + optr_reg_mask = 0; + + if ((UserType & OB_USER_ITCM_AXI_SHARE) != 0U) + { + /* ITCM_AXI_SHARE option byte should be modified */ + assert_param(IS_OB_USER_ITCM_AXI_SHARE(UserConfig2 & FLASH_OBW2SR_ITCM_AXI_SHARE)); + + /* Set value and mask for ITCM_AXI_SHARE option byte */ + optr_reg_val |= (UserConfig2 & FLASH_OBW2SR_ITCM_AXI_SHARE); + optr_reg_mask |= FLASH_OBW2SR_ITCM_AXI_SHARE; + } + + if ((UserType & OB_USER_DTCM_AXI_SHARE) != 0U) + { + /* DTCM_AXI_SHARE option byte should be modified */ + assert_param(IS_OB_USER_DTCM_AXI_SHARE(UserConfig2 & FLASH_OBW2SR_DTCM_AXI_SHARE)); + + /* Set value and mask for DTCM_AXI_SHARE option byte */ + optr_reg_val |= (UserConfig2 & FLASH_OBW2SR_DTCM_AXI_SHARE); + optr_reg_mask |= FLASH_OBW2SR_DTCM_AXI_SHARE; + } + + if ((UserType & OB_USER_SRAM_ECC) != 0U) + { + /* SRAM_ECC option byte should be modified */ + assert_param(IS_OB_USER_AXISRAM_ECC(UserConfig2 & FLASH_OBW2SR_ECC_ON_SRAM)); + + /* Set value and mask for SRAM_ECC option byte */ + optr_reg_val |= (UserConfig2 & FLASH_OBW2SR_ECC_ON_SRAM); + optr_reg_mask |= FLASH_OBW2SR_ECC_ON_SRAM; + } + + if ((UserType & OB_USER_I2C_NI3C) != 0U) + { + /* I2C_NI3C option byte should be modified */ + assert_param(IS_OB_USER_I2C_NI3C(UserConfig2 & FLASH_OBW2SR_I2C_NI3C)); + + /* Set value and mask for I2C_NI3C option byte */ + optr_reg_val |= (UserConfig2 & FLASH_OBW2SR_I2C_NI3C); + optr_reg_mask |= FLASH_OBW2SR_I2C_NI3C; + } + + /* Configure the option bytes register 2 if necessary */ + if (optr_reg_mask != 0U) + { + MODIFY_REG(FLASH->OBW2SRP, optr_reg_mask, optr_reg_val); + } +} + +/** + * @brief Configure the Hide Protection. + * + * @note To configure the HDP options, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_OB_Unlock() function. + * + * @param HDPStartPage + * + * @param HDPEndPage + * + * @retval None + */ +static void FLASH_OB_HDPConfig(uint32_t HDPStartPage, uint32_t HDPEndPage) +{ + /* Check the parameters */ + assert_param(IS_OB_HDP_PAGE(HDPStartPage)); + assert_param(IS_OB_HDP_PAGE(HDPEndPage)); + + MODIFY_REG(FLASH->HDPSRP, (FLASH_HDPSRP_HDP_AREA_START | FLASH_HDPSRP_HDP_AREA_END), \ + (HDPStartPage | (HDPEndPage << FLASH_HDPSRP_HDP_AREA_END_Pos))); +} + +/** + * @brief Configure the Non-Volatile state. + * + * @note To configure the Non-volatile options, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_OB_Unlock() function. + * + * @param NVState + * + * @retval None + */ +static void FLASH_OB_NVConfig(uint32_t NVState) +{ + /* Check the parameter */ + assert_param(IS_OB_NVSTATE(NVState)); + + MODIFY_REG(FLASH->NVSRP, FLASH_NVSRP_NVSTATE, NVState); +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * + * @param WRPState + * + * @param WRPSector + * + * @retval None + */ +static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector) +{ + if ((FLASH->WRPSR & FLASH_WRPSR_WRPS) == FLASH_WRPSR_WRPS) + { + /* All sectors aren't write protected */ + *WRPState = OB_WRPSTATE_DISABLE; + } + else + { + /* Some sectors are write protected */ + *WRPState = OB_WRPSTATE_ENABLE; + *WRPSector = ((~(FLASH->WRPSR)) & FLASH_WRPSR_WRPS); + } +} + +/** + * @brief Return the FLASH User Option Byte value. + * + * @param UserConfig1 Address to return the FLASH User Option Bytes values configuration 1. + * The return value can be a combination of + * @param UserConfig2 Address to return the FLASH User Option Bytes values configuration 2. + * The return value can be a combination of + * + * @retval None + */ +static void FLASH_OB_GetUser(uint32_t *UserConfig1, uint32_t *UserConfig2) +{ + *UserConfig1 = FLASH->OBW1SR; + *UserConfig2 = FLASH->OBW2SR; +} + +/** + * @brief Return the FLASH Hide Protection Option Bytes value. + * + * @param HDPStartPage Address to return the FLASH HDP Option Bytes Start Sector. + * The return value can be a combination of + * @param HDPEndPage Address to return the FLASH HDP Option Bytes End Sector. + * The return value can be a combination of + * + * @retval None + */ +static void FLASH_OB_GetHDP(uint32_t *HDPStartPage, uint32_t *HDPEndPage) +{ + *HDPStartPage = (FLASH->HDPSR & FLASH_HDPSR_HDP_AREA_START); + *HDPEndPage = ((FLASH->HDPSR & FLASH_HDPSR_HDP_AREA_END) >> FLASH_HDPSR_HDP_AREA_END_Pos); +} + +/** + * @brief Return the FLASH Non-volatile state Option Bytes value. + * + * @retval Value of Non-volatile state + */ +static uint32_t FLASH_OB_GetNV(void) +{ + return (FLASH->NVSR & FLASH_NVSR_NVSTATE); +} + +/** + * @brief Return the FLASH RoT Option Bytes value. + * + * @retval Value of the RoT + */ +static uint32_t FLASH_OB_GetRoT(void) +{ + return (FLASH->ROTSR & (FLASH_ROTSR_OEM_PROVD | FLASH_ROTSR_DBG_AUTH | FLASH_ROTSR_IROT_SELECT)); +} + +/** + * @brief Return the FLASH Epoch Option Bytes value. + * + * @retval Value of the Epoch + */ +static uint32_t FLASH_OB_GetEpoch(void) +{ + return (FLASH->EPOCHSR & FLASH_EPOCHSR_EPOCH); +} + +/** + * @brief Add a CRC sector to the list of sectors on which the CRC will be calculated + * @param Sector Specifies the CRC sector number + * @retval None + */ +static void FLASH_CRC_AddSector(uint32_t Sector) +{ + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + + /* Clear CRC sector */ + MODIFY_REG(FLASH->CRCCR, FLASH_CRCCR_CRC_SECT, Sector); + + /* Activate ADD_SECT bit */ + SET_BIT(FLASH->CRCCR, FLASH_CRCCR_ADD_SECT); +} + +/** + * @brief Select CRC start and end memory addresses on which the CRC will be calculated + * @param CRCStartAddr Specifies the CRC start address + * @param CRCEndAddr Specifies the CRC end address + * @retval None + */ +static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr) +{ + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(CRCStartAddr)); + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(CRCEndAddr)); + + /* Write CRC Start and End addresses */ + FLASH->CRCSADDR = (CRCStartAddr - FLASH_BASE); + FLASH->CRCEADDR = (CRCEndAddr - FLASH_BASE); +} + +/** + * @brief Wait for a FLASH CRC computation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL_StatusTypeDef HAL Status + */ +static HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout) +{ + uint32_t timeout = HAL_GetTick() + Timeout; + + /* Wait for the FLASH CRC computation to complete by polling on CRC_BUSY flag to be reset */ + while ((FLASH->SR & FLASH_SR_CRC_BUSY) != 0U) + { + if (HAL_GetTick() >= timeout) + { + return HAL_TIMEOUT; + } + } + + /* Check FLASH CRC calculation error flag */ + if ((FLASH->ISR & FLASH_FLAG_CRCERR) != 0U) + { + /*Save the error code*/ + pFlash.ErrorCode |= HAL_FLASH_ERROR_CRC; + + /* Clear CRC error flag */ + FLASH->ICR = FLASH_FLAG_CRCERR; + + return HAL_ERROR; + } + + /* Check FLASH CRC End of Calculation flag */ + if ((FLASH->ISR & FLASH_FLAG_CRCEND) != 0U) + { + /* Clear FLASH End of Calculation pending bit */ + FLASH->ICR = FLASH_FLAG_CRCEND; + } + + /* If there is no error flag set */ + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gfxmmu.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gfxmmu.c new file mode 100644 index 00000000000..5ab6ac7b72e --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gfxmmu.c @@ -0,0 +1,872 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_gfxmmu.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Graphic MMU (GFXMMU) peripheral: + * + Initialization and De-initialization. + * + LUT configuration. + * + Modify physical buffer addresses. + * + Packing configuration. + * + Error management. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** Initialization *** + ====================== + [..] + (#) As prerequisite, fill in the HAL_GFXMMU_MspInit() : + (++) Enable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE(). + (++) If interrupts are used, enable and configure GFXMMU global + interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (#) Configure the number of blocks per line, default value, physical + buffer addresses and interrupts using the HAL_GFXMMU_Init() function. + + *** LUT configuration *** + ========================= + [..] + (#) Use HAL_GFXMMU_DisableLutLines() to deactivate all LUT lines (or a + range of lines). + (#) Use HAL_GFXMMU_ConfigLut() to copy LUT from flash to look up RAM. + (#) Use HAL_GFXMMU_ConfigLutLine() to configure one line of LUT. + + *** Modify physical buffer addresses *** + ======================================== + [..] + (#) Use HAL_GFXMMU_ModifyBuffers() to modify physical buffer addresses. + + *** Packing configuration *** + ============================= + [..] + (#) Use HAL_GFXMMU_ConfigPacking() to configure packing. + + *** Error management *** + ======================== + [..] + (#) If interrupts are used, HAL_GFXMMU_IRQHandler() will be called when + an error occurs. This function will call HAL_GFXMMU_ErrorCallback(). + Use HAL_GFXMMU_GetError() to get the error code. + + *** De-initialization *** + ========================= + [..] + (#) As prerequisite, fill in the HAL_GFXMMU_MspDeInit() : + (++) Disable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE(). + (++) If interrupts has been used, disable GFXMMU global interrupt with + HAL_NVIC_DisableIRQ(). + (#) De-initialize GFXMMU using the HAL_GFXMMU_DeInit() function. + + *** Callback registration *** + ============================= + [..] + The compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use functions HAL_GFXMMU_RegisterCallback() to register a user callback. + + [..] + Function HAL_GFXMMU_RegisterCallback() allows to register following callbacks: + (+) ErrorCallback : GFXMMU error. + (+) MspInitCallback : GFXMMU MspInit. + (+) MspDeInitCallback : GFXMMU MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_GFXMMU_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. + HAL_GFXMMU_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the callback ID. + [..] + This function allows to reset following callbacks: + (+) ErrorCallback : GFXMMU error. + (+) MspInitCallback : GFXMMU MspInit. + (+) MspDeInitCallback : GFXMMU MspDeInit. + + [..] + By default, after the HAL_GFXMMU_Init and if the state is HAL_GFXMMU_STATE_RESET + all callbacks are reset to the corresponding legacy weak (overridden) functions: + examples HAL_GFXMMU_ErrorCallback(). + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (overridden) functions in the HAL_GFXMMU_Init + and HAL_GFXMMU_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_GFXMMU_Init and HAL_GFXMMU_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_GFXMMU_RegisterCallback before calling HAL_GFXMMU_DeInit + or HAL_GFXMMU_Init function. + + [..] + When the compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (overridden) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#ifdef HAL_GFXMMU_MODULE_ENABLED +#if defined(GFXMMU) +/** @defgroup GFXMMU GFXMMU + * @brief GFXMMU HAL driver module + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup GFXMMU_Private_Constants GFXMMU Private Constants + * @{ + */ +#define GFXMMU_LUTXL_FVB_OFFSET 8U +#define GFXMMU_LUTXL_LVB_OFFSET 16U +#define GFXMMU_CR_ITS_MASK 0x1FU +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GFXMMU_Exported_Functions GFXMMU Exported Functions + * @{ + */ + +/** @defgroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the GFXMMU. + (+) De-initialize the GFXMMU. +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GFXMMU according to the specified parameters in the + * GFXMMU_InitTypeDef structure and initialize the associated handle. + * @param hgfxmmu GFXMMU handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check GFXMMU handle */ + if (hgfxmmu == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_BLOCK_SIZE(hgfxmmu->Init.BlockSize)); + assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.AddressTranslation)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf0Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf1Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf2Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf3Address)); + assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.Interrupts.Activation)); + +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback; + + /* Call GFXMMU MSP init function */ + if (hgfxmmu->MspInitCallback == NULL) + { + hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit; + } + hgfxmmu->MspInitCallback(hgfxmmu); +#else + /* Call GFXMMU MSP init function */ + HAL_GFXMMU_MspInit(hgfxmmu); +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */ + + /* Configure GFXMMU_CR register */ + hgfxmmu->Instance->CR = 0U; + hgfxmmu->Instance->CR |= (hgfxmmu->Init.BlockSize); + if (hgfxmmu->Init.AddressTranslation == ENABLE) + { + hgfxmmu->Instance->CR |= GFXMMU_CR_ATE; + } + if (hgfxmmu->Init.Interrupts.Activation == ENABLE) + { + assert_param(IS_GFXMMU_INTERRUPTS(hgfxmmu->Init.Interrupts.UsedInterrupts)); + hgfxmmu->Instance->CR |= hgfxmmu->Init.Interrupts.UsedInterrupts; + } + + /* Configure default value on GFXMMU_DVR register */ + hgfxmmu->Instance->DVR = hgfxmmu->Init.DefaultValue; + + /* Configure physical buffer addresses on GFXMMU_BxCR registers */ + hgfxmmu->Instance->B0CR = hgfxmmu->Init.Buffers.Buf0Address; + hgfxmmu->Instance->B1CR = hgfxmmu->Init.Buffers.Buf1Address; + hgfxmmu->Instance->B2CR = hgfxmmu->Init.Buffers.Buf2Address; + hgfxmmu->Instance->B3CR = hgfxmmu->Init.Buffers.Buf3Address; + + /* Reset GFXMMU error code */ + hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE; + + /* Set GFXMMU to ready state */ + hgfxmmu->State = HAL_GFXMMU_STATE_READY; + } + /* Return function status */ + return status; +} + +/** + * @brief De-initialize the GFXMMU. + * @param hgfxmmu GFXMMU handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check GFXMMU handle */ + if (hgfxmmu == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + + /* Disable all interrupts on GFXMMU_CR register */ + hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE | + GFXMMU_CR_AMEIE); + + /* Call GFXMMU MSP de-init function */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + if (hgfxmmu->MspDeInitCallback == NULL) + { + hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit; + } + hgfxmmu->MspDeInitCallback(hgfxmmu); +#else + HAL_GFXMMU_MspDeInit(hgfxmmu); +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */ + + /* Set GFXMMU to reset state */ + hgfxmmu->State = HAL_GFXMMU_STATE_RESET; + } + /* Return function status */ + return status; +} + +/** + * @brief Initialize the GFXMMU MSP. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +__weak void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxmmu); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXMMU_MspInit could be implemented in the user file. + */ +} + +/** + * @brief De-initialize the GFXMMU MSP. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +__weak void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxmmu); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXMMU_MspDeInit could be implemented in the user file. + */ +} + +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user GFXMMU callback + * to be used instead of the weak predefined callback. + * @param hgfxmmu GFXMMU handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID. + * @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID, + pGFXMMU_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if (HAL_GFXMMU_STATE_READY == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_ERROR_CB_ID : + hgfxmmu->ErrorCallback = pCallback; + break; + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = pCallback; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_GFXMMU_STATE_RESET == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = pCallback; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user GFXMMU callback. + * GFXMMU callback is redirected to the weak predefined callback. + * @param hgfxmmu GFXMMU handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID. + * @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu, + HAL_GFXMMU_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_GFXMMU_STATE_READY == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_ERROR_CB_ID : + hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback; + break; + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_GFXMMU_STATE_RESET == hgfxmmu->State) + { + switch (CallbackID) + { + case HAL_GFXMMU_MSPINIT_CB_ID : + hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit; + break; + case HAL_GFXMMU_MSPDEINIT_CB_ID : + hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit; + break; + default : + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + return status; +} +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup GFXMMU_Exported_Functions_Group2 Operations functions + * @brief GFXMMU operation functions + * +@verbatim + ============================================================================== + ##### Operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure LUT. + (+) Modify physical buffer addresses. + (+) Configure packing. + (+) Manage error. +@endverbatim + * @{ + */ + +/** + * @brief This function allows to copy LUT from flash to look up RAM. + * @param hgfxmmu GFXMMU handle. + * @param FirstLine First line enabled on LUT. + * This parameter must be a number between Min_Data = 0 and Max_Data = 1023. + * @param LinesNumber Number of lines enabled on LUT. + * This parameter must be a number between Min_Data = 1 and Max_Data = 1024. + * @param Address Start address of LUT in flash. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber, + uint32_t Address) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_LUT_LINE(FirstLine)); + assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber)); + + /* Check GFXMMU state and coherent parameters */ + if ((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U)) + { + status = HAL_ERROR; + } + /* Check address translation status */ + else if ((hgfxmmu->Instance->CR & GFXMMU_CR_ATE) == 0U) + { + status = HAL_ERROR; + } + else + { + uint32_t current_address; + uint32_t current_line; + uint32_t lutxl_address; + uint32_t lutxh_address; + + /* Initialize local variables */ + current_address = Address; + current_line = 0U; + lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]); + lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]); + + /* Copy LUT from flash to look up RAM */ + while (current_line < LinesNumber) + { + *((uint32_t *)lutxl_address) = *((uint32_t *)current_address); + current_address += 4U; + *((uint32_t *)lutxh_address) = *((uint32_t *)current_address); + current_address += 4U; + lutxl_address += 8U; + lutxh_address += 8U; + current_line++; + } + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to disable a range of LUT lines. + * @param hgfxmmu GFXMMU handle. + * @param FirstLine First line to disable on LUT. + * This parameter must be a number between Min_Data = 0 and Max_Data = 1023. + * @param LinesNumber Number of lines to disable on LUT. + * This parameter must be a number between Min_Data = 1 and Max_Data = 1024. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu, + uint32_t FirstLine, + uint32_t LinesNumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_LUT_LINE(FirstLine)); + assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber)); + + /* Check GFXMMU state and coherent parameters */ + if ((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U)) + { + status = HAL_ERROR; + } + /* Check address translation status */ + else if ((hgfxmmu->Instance->CR & GFXMMU_CR_ATE) == 0U) + { + status = HAL_ERROR; + } + else + { + uint32_t current_line; + uint32_t lutxl_address; + uint32_t lutxh_address; + + /* Initialize local variables */ + current_line = 0U; + lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]); + lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]); + + /* Disable LUT lines */ + while (current_line < LinesNumber) + { + *((uint32_t *)lutxl_address) = 0U; + *((uint32_t *)lutxh_address) = 0U; + lutxl_address += 8U; + lutxh_address += 8U; + current_line++; + } + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to configure one line of LUT. + * @param hgfxmmu GFXMMU handle. + * @param lutLine LUT line parameters. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_LutLineTypeDef *lutLine) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_LUT_LINE(lutLine->LineNumber)); + assert_param(IS_GFXMMU_LUT_LINE_STATUS(lutLine->LineStatus)); + assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->FirstVisibleBlock)); + assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->LastVisibleBlock)); + assert_param(IS_GFXMMU_LUT_LINE_OFFSET(lutLine->LineOffset)); + + /* Check GFXMMU state */ + if (hgfxmmu->State != HAL_GFXMMU_STATE_READY) + { + status = HAL_ERROR; + } + /* Check address translation status */ + else if ((hgfxmmu->Instance->CR & GFXMMU_CR_ATE) == 0U) + { + status = HAL_ERROR; + } + else + { + uint32_t lutxl_address; + uint32_t lutxh_address; + + /* Initialize local variables */ + lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * lutLine->LineNumber]); + lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * lutLine->LineNumber) + 1U]); + + /* Configure LUT line */ + if (lutLine->LineStatus == GFXMMU_LUT_LINE_ENABLE) + { + /* Enable and configure LUT line */ + *((uint32_t *)lutxl_address) = (lutLine->LineStatus | + (lutLine->FirstVisibleBlock << GFXMMU_LUTXL_FVB_OFFSET) | + (lutLine->LastVisibleBlock << GFXMMU_LUTXL_LVB_OFFSET)); + *((uint32_t *)lutxh_address) = (uint32_t) lutLine->LineOffset; + } + else + { + /* Disable LUT line */ + *((uint32_t *)lutxl_address) = 0U; + *((uint32_t *)lutxh_address) = 0U; + } + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to modify physical buffer addresses. + * @param hgfxmmu GFXMMU handle. + * @param Buffers Buffers parameters. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_BuffersTypeDef *Buffers) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf0Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf1Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf2Address)); + assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf3Address)); + + /* Check GFXMMU state */ + if (hgfxmmu->State != HAL_GFXMMU_STATE_READY) + { + status = HAL_ERROR; + } + else + { + /* Modify physical buffer addresses on GFXMMU_BxCR registers */ + hgfxmmu->Instance->B0CR = Buffers->Buf0Address; + hgfxmmu->Instance->B1CR = Buffers->Buf1Address; + hgfxmmu->Instance->B2CR = Buffers->Buf2Address; + hgfxmmu->Instance->B3CR = Buffers->Buf3Address; + } + /* Return function status */ + return status; +} + +/** + * @brief This function allows to configure packing. + * @param hgfxmmu GFXMMU handle. + * @param pPacking Packing parameters. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXMMU_ConfigPacking(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_PackingTypeDef *pPacking) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance)); + assert_param(IS_FUNCTIONAL_STATE(pPacking->Buffer0Activation)); + assert_param(IS_FUNCTIONAL_STATE(pPacking->Buffer1Activation)); + assert_param(IS_FUNCTIONAL_STATE(pPacking->Buffer2Activation)); + assert_param(IS_FUNCTIONAL_STATE(pPacking->Buffer3Activation)); + assert_param(IS_GFXMMU_PACKING_MODE(pPacking->Buffer0Mode)); + assert_param(IS_GFXMMU_PACKING_MODE(pPacking->Buffer1Mode)); + assert_param(IS_GFXMMU_PACKING_MODE(pPacking->Buffer2Mode)); + assert_param(IS_GFXMMU_PACKING_MODE(pPacking->Buffer3Mode)); + assert_param(IS_GFXMMU_DEFAULT_ALPHA_VALUE(pPacking->DefaultAlpha)); + + /* Check GFXMMU state */ + if (hgfxmmu->State != HAL_GFXMMU_STATE_READY) + { + status = HAL_ERROR; + } + /* Check block size is set to 12-byte*/ + else if ((hgfxmmu->Instance->CR & GFXMMU_CR_BS) == 0U) + { + status = HAL_ERROR; + } + else + { + uint32_t reg_value = 0U; + + /* Configure packing for all buffers on GFXMMU_CR register */ + if (pPacking->Buffer0Activation == ENABLE) + { + reg_value |= ((pPacking->Buffer0Mode << GFXMMU_CR_B0PM_Pos) | GFXMMU_CR_B0PE); + } + if (pPacking->Buffer1Activation == ENABLE) + { + reg_value |= ((pPacking->Buffer1Mode << GFXMMU_CR_B1PM_Pos) | GFXMMU_CR_B1PE); + } + if (pPacking->Buffer2Activation == ENABLE) + { + reg_value |= ((pPacking->Buffer2Mode << GFXMMU_CR_B2PM_Pos) | GFXMMU_CR_B2PE); + } + if (pPacking->Buffer3Activation == ENABLE) + { + reg_value |= ((pPacking->Buffer3Mode << GFXMMU_CR_B3PM_Pos) | GFXMMU_CR_B3PE); + } + hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0PE_Msk | GFXMMU_CR_B0PM_Msk | + GFXMMU_CR_B1PE_Msk | GFXMMU_CR_B1PM_Msk | + GFXMMU_CR_B2PE_Msk | GFXMMU_CR_B2PM_Msk | + GFXMMU_CR_B3PE_Msk | GFXMMU_CR_B3PM_Msk); + hgfxmmu->Instance->CR |= reg_value; + + /* Configure default alpha value on GFXMMU_DAR register */ + hgfxmmu->Instance->DAR = pPacking->DefaultAlpha; + } + /* Return function status */ + return status; +} + +/** + * @brief This function handles the GFXMMU interrupts. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu) +{ + uint32_t flags, interrupts, error; + + /* Read current flags and interrupts and determine which error occurs */ + flags = hgfxmmu->Instance->SR; + interrupts = (hgfxmmu->Instance->CR & GFXMMU_CR_ITS_MASK); + error = (flags & interrupts); + + if (error != 0U) + { + /* Clear flags on GFXMMU_FCR register */ + hgfxmmu->Instance->FCR = error; + + /* Update GFXMMU error code */ + hgfxmmu->ErrorCode |= error; + + /* Call GFXMMU error callback */ +#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1) + hgfxmmu->ErrorCallback(hgfxmmu); +#else + HAL_GFXMMU_ErrorCallback(hgfxmmu); +#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */ + } +} + +/** + * @brief Error callback. + * @param hgfxmmu GFXMMU handle. + * @retval None. + */ +__weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxmmu); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_GFXMMU_ErrorCallback could be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup GFXMMU_Exported_Functions_Group3 State functions + * @brief GFXMMU state functions + * +@verbatim + ============================================================================== + ##### State functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Get GFXMMU handle state. + (+) Get GFXMMU error code. +@endverbatim + * @{ + */ + +/** + * @brief This function allows to get the current GFXMMU handle state. + * @param hgfxmmu GFXMMU handle. + * @retval GFXMMU state. + */ +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu) +{ + /* Return GFXMMU handle state */ + return hgfxmmu->State; +} + +/** + * @brief This function allows to get the current GFXMMU error code. + * @param hgfxmmu GFXMMU handle. + * @retval GFXMMU error code. + */ +uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu) +{ + uint32_t error_code; + + /* Enter in critical section */ + __disable_irq(); + + /* Store and reset GFXMMU error code */ + error_code = hgfxmmu->ErrorCode; + hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE; + + /* Exit from critical section */ + __enable_irq(); + + /* Return GFXMMU error code */ + return error_code; +} + +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ +#endif /* GFXMMU */ +#endif /* HAL_GFXMMU_MODULE_ENABLED */ +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gfxtim.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gfxtim.c new file mode 100644 index 00000000000..2a1b90c1864 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gfxtim.c @@ -0,0 +1,2032 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_gfxtim.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Multi-function Digital Filter (GFXTIM) + * peripheral: + * + Initialization and de-initialization + * + Integrated frame and line clock generation + * + One absolute frame counter with one compare channel + * + Two auto reload relative frame counter + * + One line timer with two compare channel + * + External Tearing Effect line management & synchronization + * + Four programmable event generators with external trigger generation + * + One watchdog counter + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** Initialization and de-initialization *** + ============================================ + [..] + (#) User has first to initialize GFXTIM. + (#) As prerequisite, fill in the HAL_GFXTIM_MspInit() : + (++) Enable GFXTIM with __HAL_RCC_GFXTIM_CLK_ENABLE + (++) Enable the clocks for the used GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). + (++) Configure these pins in alternate mode using HAL_GPIO_Init(). + (++) If interrupt mode is used, enable and configure GFXTIM + interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + + [..] + (#) User can de-initialize GFXTIM with HAL_GFXTIM_DeInit() function. + + *** generic functions *** + ========================= + [..] + (#) HAL_GFXTIM_IRQHandler will be called when GFXTIM interrupt occurs. + (#) HAL_GFXTIM_ErrorCallback will be called when GFXTIM or ADF error occurs. + (#) Use HAL_GFXTIM_GetState() to get the current GFXTIM or ADF instance state. + (#) Use HAL_GFXTIM_GetErrorCode() to get the current GFXTIM or ADF instance error code. + + + +#if defined(GENERATOR_CALLBACKS_REGISTERING_AVAILABLE) + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_GFXTIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_GFXTIM_RegisterCallback() to register an interrupt callback. + + Function @ref HAL_GFXTIM_RegisterCallback() registers following callbacks: + (+) HAL_GFXTIM_AbsoluteTimer_AFCC1Callback + (+) HAL_GFXTIM_AbsoluteTimer_AFCOFCallback + (+) HAL_GFXTIM_AbsoluteTimer_ALCC1Callback + (+) HAL_GFXTIM_AbsoluteTimer_ALCC2Callback + (+) HAL_GFXTIM_AbsoluteTimer_ALCOFCallback + (+) HAL_GFXTIM_RelativeTimer_RFC1RCallback + (+) HAL_GFXTIM_RelativeTimer_RFC2RCallback + (+) HAL_GFXTIM_TECallback + (+) HAL_GFXTIM_EventGenerator_EV1Callback + (+) HAL_GFXTIM_EventGenerator_EV2Callback + (+) HAL_GFXTIM_EventGenerator_EV3Callback + (+) HAL_GFXTIM_EventGenerator_EV4Callback + (+) HAL_GFXTIM_WatchdogTimer_AlarmCallback + (+) HAL_GFXTIM_WatchdogTimer_PreAlarmCallback + (+) MspInitCallback + (+) MspDeInitCallback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_GFXTIM_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_GFXTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function resets following callbacks: + (+) HAL_GFXTIM_AbsoluteTimer_AFCC1Callback + (+) HAL_GFXTIM_AbsoluteTimer_AFCOFCallback + (+) HAL_GFXTIM_AbsoluteTimer_ALCC1Callback + (+) HAL_GFXTIM_AbsoluteTimer_ALCC2Callback + (+) HAL_GFXTIM_AbsoluteTimer_ALCOFCallback + (+) HAL_GFXTIM_RelativeTimer_RFC1RCallback + (+) HAL_GFXTIM_RelativeTimer_RFC2RCallback + (+) HAL_GFXTIM_TECallback + (+) HAL_GFXTIM_EventGenerator_EV1Callback + (+) HAL_GFXTIM_EventGenerator_EV2Callback + (+) HAL_GFXTIM_EventGenerator_EV3Callback + (+) HAL_GFXTIM_EventGenerator_EV4Callback + (+) HAL_GFXTIM_WatchdogTimer_AlarmCallback + (+) HAL_GFXTIM_WatchdogTimer_PreAlarmCallback + (+) MspInitCallback + (+) MspDeInitCallback + + By default, after the HAL_GFXTIM_Init() and when the state is HAL_GFXTIM_STATE_RESET, + all callbacks are set to the corresponding weak functions: + examples @ref HAL_GFXTIM_ErrorCallback(), @ref HAL_GFXTIM_CalculateCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_GFXTIM_Init()/ @ref HAL_GFXTIM_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_GFXTIM_Init()/ @ref HAL_GFXTIM_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_GFXTIM_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_GFXTIM_STATE_READY or HAL_GFXTIM_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_GFXTIM_RegisterCallback() before calling @ref HAL_GFXTIM_DeInit() + or HAL_GFXTIM_Init() function. + + When The compilation define USE_HAL_GFXTIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. +#endif + + @endverbatim + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#ifdef HAL_GFXTIM_MODULE_ENABLED +#if defined(GFXTIM) +/** @defgroup GFXTIM GFXTIM + * @brief GFXTIM HAL module driver + * @{ + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup GFXTIM_Exported_Functions GFXTIM Exported Functions + * @{ + */ + +/** @defgroup GFXTIM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to : + (+) Initialize the GFXTIM instance. + (+) De-initialize the GFXTIM instance. + (+) Register and unregister callbacks. +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GFXTIM instance according to the specified parameters + * in the GFXTIM_InitTypeDef structure and initialize the associated handle. + * @param hgfxtim GFXTIM handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_Init(GFXTIM_HandleTypeDef *hgfxtim) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + if (hgfxtim != NULL) + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + assert_param(IS_GFXTIM_SYNC_SRC(hgfxtim->Init.SynchroSrc)); + assert_param(IS_GFXTIM_TE_SRC(hgfxtim->Init.TearingEffectSrc)); + assert_param(IS_GFXTIM_TE_POLARITY(hgfxtim->Init.TearingEffectPolarity)); + assert_param(IS_GFXTIM_INTERRUPT(hgfxtim->Init.TearingEffectInterrupt)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_RESET) + { +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCC1Callback = HAL_GFXTIM_AbsoluteTimer_AFCC1Callback; + hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCOFCallback = HAL_GFXTIM_AbsoluteTimer_AFCOFCallback; + hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC1Callback = HAL_GFXTIM_AbsoluteTimer_ALCC1Callback; + hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC2Callback = HAL_GFXTIM_AbsoluteTimer_ALCC2Callback; + hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCOFCallback = HAL_GFXTIM_AbsoluteTimer_ALCOFCallback; + hgfxtim->HAL_GFXTIM_RelativeTimer_RFC1RCallback = HAL_GFXTIM_RelativeTimer_RFC1RCallback; + hgfxtim->HAL_GFXTIM_RelativeTimer_RFC2RCallback = HAL_GFXTIM_RelativeTimer_RFC2RCallback; + hgfxtim->HAL_GFXTIM_TECallback = HAL_GFXTIM_TECallback; + hgfxtim->HAL_GFXTIM_EventGenerator_EV1Callback = HAL_GFXTIM_EventGenerator_EV1Callback; + hgfxtim->HAL_GFXTIM_EventGenerator_EV2Callback = HAL_GFXTIM_EventGenerator_EV2Callback; + hgfxtim->HAL_GFXTIM_EventGenerator_EV3Callback = HAL_GFXTIM_EventGenerator_EV3Callback; + hgfxtim->HAL_GFXTIM_EventGenerator_EV4Callback = HAL_GFXTIM_EventGenerator_EV4Callback; + hgfxtim->HAL_GFXTIM_WatchdogTimer_AlarmCallback = HAL_GFXTIM_WatchdogTimer_AlarmCallback; + hgfxtim->HAL_GFXTIM_WatchdogTimer_PreAlarmCallback = HAL_GFXTIM_WatchdogTimer_PreAlarmCallback; + hgfxtim->ErrorCallback = HAL_GFXTIM_ErrorCallback; + + /* Call GFXTIM MSP init function */ + if (hgfxtim->MspInitCallback == NULL) + { + hgfxtim->MspInitCallback = HAL_GFXTIM_MspInit; + } + hgfxtim->MspInitCallback(hgfxtim); +#else /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + /* Call GFXTIM MSP init function */ + HAL_GFXTIM_MspInit(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + + /* Set Synchronization signals sources (HSYNC and VSYNC), Tearing Effect source and polarity, */ + MODIFY_REG(hgfxtim->Instance->CR, \ + GFXTIM_CR_SYNCS | GFXTIM_CR_TES | GFXTIM_CR_TEPOL, + hgfxtim->Init.SynchroSrc | hgfxtim->Init.TearingEffectSrc | hgfxtim->Init.TearingEffectPolarity); + + /* Set tearing effect interrupt */ + MODIFY_REG(hgfxtim->Instance->IER, GFXTIM_IER_TEIE, + (hgfxtim->Init.TearingEffectInterrupt << GFXTIM_IER_TEIE_Pos)); + + /* Update error code and state */ + hgfxtim->ErrorCode = GFXTIM_ERROR_NONE; + hgfxtim->State = HAL_GFXTIM_STATE_READY; + status = HAL_OK; + } + } + + return status; +} + +/** + * @brief De-initialize the GFXTIM instance. + * @param hgfxtim GFXTIM handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_DeInit(GFXTIM_HandleTypeDef *hgfxtim) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + if (hgfxtim != NULL) + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + /* Call GFXTIM MSP deinit function */ +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1) + if (hgfxtim->MspDeInitCallback == NULL) + { + hgfxtim->MspDeInitCallback = HAL_GFXTIM_MspDeInit; + } + hgfxtim->MspDeInitCallback(hgfxtim); +#else /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + HAL_GFXTIM_MspDeInit(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + + /* Update state */ + hgfxtim->State = HAL_GFXTIM_STATE_RESET; + status = HAL_OK; + } + } + + return status; +} + +/** + * @brief Initialize the GFXTIM instance MSP. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_MspInit(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_MspInit could be implemented in the user file */ +} + +/** + * @brief De-initialize the GFXTIM instance MSP. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_MspDeInit(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_MspDeInit could be implemented in the user file */ +} + +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user GFXTIM callback to be used instead of the weak predefined callback. + * @param hgfxtim GFXTIM handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_GFXTIM_AFC_COMPARE1_CB_ID Absolute frame counter compare 1 callback ID + * @arg @ref HAL_GFXTIM_AFC_OVERFLOW_CB_ID Absolute frame counter overflow callback ID + * @arg @ref HAL_GFXTIM_ALC_COMPARE1_CB_ID Absolute line counter compare 1 callback ID + * @arg @ref HAL_GFXTIM_ALC_COMPARE2_CB_ID Absolute line counter compare 2 callback ID + * @arg @ref HAL_GFXTIM_ALC_OVERFLOW_CB_ID Absolute line counter overflow callback ID + * @arg @ref HAL_GFXTIM_RFC1_RELOAD_CB_ID Relative frame counter 1 reload callback ID + * @arg @ref HAL_GFXTIM_RFC2_RELOAD_CB_ID Relative frame counter 2 reload callback ID + * @arg @ref HAL_GFXTIM_TE_CB_ID External tearing effect callback ID + * @arg @ref HAL_GFXTIM_EVENT1_CB_ID Event events 1 callback ID + * @arg @ref HAL_GFXTIM_EVENT2_CB_ID Event events 2 callback ID + * @arg @ref HAL_GFXTIM_EVENT3_CB_ID Event events 3 callback ID + * @arg @ref HAL_GFXTIM_EVENT4_CB_ID Event events 4 callback ID + * @arg @ref HAL_GFXTIM_WDG_ALARM_CB_ID Watchdog alarm callback ID + * @arg @ref HAL_GFXTIM_WDG_PREALARM_CB_ID Watchdog pre alarm callback ID + * @arg @ref HAL_GFXTIM_ERROR_CB_ID error callback ID + * @arg @ref HAL_GFXTIM_MSP_INIT_CB_ID MSP initialization user callback ID + * @arg @ref HAL_GFXTIM_MSP_DEINIT_CB_ID MSP de-initialization user callback ID + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_RegisterCallback(GFXTIM_HandleTypeDef *hgfxtim, + HAL_GFXTIM_CallbackIDTypeDef CallbackID, + pGFXTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else if (pCallback == NULL) + { + /* Update error code and status */ + hgfxtim->ErrorCode |= GFXTIM_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + else + { + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_GFXTIM_AFC_COMPARE1_CB_ID : + hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCC1Callback = pCallback; + break; + case HAL_GFXTIM_AFC_OVERFLOW_CB_ID : + hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCOFCallback = pCallback; + break; + case HAL_GFXTIM_ALC_COMPARE1_CB_ID : + hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC1Callback = pCallback; + break; + case HAL_GFXTIM_ALC_COMPARE2_CB_ID : + hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC2Callback = pCallback; + break; + case HAL_GFXTIM_ALC_OVERFLOW_CB_ID : + hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCOFCallback = pCallback; + break; + case HAL_GFXTIM_RFC1_RELOAD_CB_ID : + hgfxtim->HAL_GFXTIM_RelativeTimer_RFC1RCallback = pCallback; + break; + case HAL_GFXTIM_RFC2_RELOAD_CB_ID : + hgfxtim->HAL_GFXTIM_RelativeTimer_RFC2RCallback = pCallback; + break; + case HAL_GFXTIM_TE_CB_ID : + hgfxtim->HAL_GFXTIM_TECallback = pCallback; + break; + case HAL_GFXTIM_EVENT1_CB_ID : + hgfxtim->HAL_GFXTIM_EventGenerator_EV1Callback = pCallback; + break; + case HAL_GFXTIM_EVENT2_CB_ID : + hgfxtim->HAL_GFXTIM_EventGenerator_EV2Callback = pCallback; + break; + case HAL_GFXTIM_EVENT3_CB_ID : + hgfxtim->HAL_GFXTIM_EventGenerator_EV3Callback = pCallback; + break; + case HAL_GFXTIM_EVENT4_CB_ID : + hgfxtim->HAL_GFXTIM_EventGenerator_EV4Callback = pCallback; + break; + case HAL_GFXTIM_WDG_ALARM_CB_ID : + hgfxtim->HAL_GFXTIM_WatchdogTimer_AlarmCallback = pCallback; + break; + case HAL_GFXTIM_WDG_PREALARM_CB_ID : + hgfxtim->HAL_GFXTIM_WatchdogTimer_PreAlarmCallback = pCallback; + break; + case HAL_GFXTIM_ERROR_CB_ID : + hgfxtim->ErrorCallback = pCallback; + break; + case HAL_GFXTIM_MSP_INIT_CB_ID : + hgfxtim->MspInitCallback = pCallback; + break; + case HAL_GFXTIM_MSP_DEINIT_CB_ID : + hgfxtim->MspDeInitCallback = pCallback; + break; + default : + /* Update error code and status */ + hgfxtim->ErrorCode |= GFXTIM_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else if (hgfxtim->State == HAL_GFXTIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_GFXTIM_MSP_INIT_CB_ID : + hgfxtim->MspInitCallback = pCallback; + break; + case HAL_GFXTIM_MSP_DEINIT_CB_ID : + hgfxtim->MspDeInitCallback = pCallback; + break; + default : + /* Update error code and status */ + hgfxtim->ErrorCode |= GFXTIM_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else + { + /* Update error code and status */ + hgfxtim->ErrorCode |= GFXTIM_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Unregister a user GFXTIM callback. + * GFXTIM callback is redirected to the weak predefined callback. + * @param hgfxtim GFXTIM handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_GFXTIM_AFC_COMPARE1_CB_ID Absolute frame counter compare 1 callback ID + * @arg @ref HAL_GFXTIM_AFC_OVERFLOW_CB_ID Absolute frame counter overflow callback ID + * @arg @ref HAL_GFXTIM_ALC_COMPARE1_CB_ID Absolute line counter compare 1 callback ID + * @arg @ref HAL_GFXTIM_ALC_COMPARE2_CB_ID Absolute line counter compare 2 callback ID + * @arg @ref HAL_GFXTIM_ALC_OVERFLOW_CB_ID Absolute line counter overflow callback ID + * @arg @ref HAL_GFXTIM_RFC1_RELOAD_CB_ID Relative frame counter 1 reload callback ID + * @arg @ref HAL_GFXTIM_RFC2_RELOAD_CB_ID Relative frame counter 2 reload callback ID + * @arg @ref HAL_GFXTIM_TE_CB_ID External tearing effect callback ID + * @arg @ref HAL_GFXTIM_EVENT1_CB_ID Event events 1 callback ID + * @arg @ref HAL_GFXTIM_EVENT2_CB_ID Event events 2 callback ID + * @arg @ref HAL_GFXTIM_EVENT3_CB_ID Event events 3 callback ID + * @arg @ref HAL_GFXTIM_EVENT4_CB_ID Event events 4 callback ID + * @arg @ref HAL_GFXTIM_WDG_ALARM_CB_ID Watchdog alarm callback ID + * @arg @ref HAL_GFXTIM_WDG_PREALARM_CB_ID Watchdog pre alarm callback ID + * @arg @ref HAL_GFXTIM_ERROR_CB_ID error callback ID + * @arg @ref HAL_GFXTIM_MSP_INIT_CB_ID MSP initialization user callback ID + * @arg @ref HAL_GFXTIM_MSP_DEINIT_CB_ID MSP de-initialization user callback ID + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_UnRegisterCallback(GFXTIM_HandleTypeDef *hgfxtim, + HAL_GFXTIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_GFXTIM_AFC_COMPARE1_CB_ID : + hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCC1Callback = HAL_GFXTIM_AbsoluteTimer_AFCC1Callback; + break; + case HAL_GFXTIM_AFC_OVERFLOW_CB_ID : + hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCOFCallback = HAL_GFXTIM_AbsoluteTimer_AFCOFCallback; + break; + case HAL_GFXTIM_ALC_COMPARE1_CB_ID : + hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC1Callback = HAL_GFXTIM_AbsoluteTimer_ALCC1Callback; + break; + case HAL_GFXTIM_ALC_COMPARE2_CB_ID : + hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC2Callback = HAL_GFXTIM_AbsoluteTimer_ALCC2Callback; + break; + case HAL_GFXTIM_ALC_OVERFLOW_CB_ID : + hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCOFCallback = HAL_GFXTIM_AbsoluteTimer_ALCOFCallback; + break; + case HAL_GFXTIM_RFC1_RELOAD_CB_ID : + hgfxtim->HAL_GFXTIM_RelativeTimer_RFC1RCallback = HAL_GFXTIM_RelativeTimer_RFC1RCallback; + break; + case HAL_GFXTIM_RFC2_RELOAD_CB_ID : + hgfxtim->HAL_GFXTIM_RelativeTimer_RFC2RCallback = HAL_GFXTIM_RelativeTimer_RFC2RCallback; + break; + case HAL_GFXTIM_TE_CB_ID : + hgfxtim->HAL_GFXTIM_TECallback = HAL_GFXTIM_TECallback; + break; + case HAL_GFXTIM_EVENT1_CB_ID : + hgfxtim->HAL_GFXTIM_EventGenerator_EV1Callback = HAL_GFXTIM_EventGenerator_EV1Callback; + break; + case HAL_GFXTIM_EVENT2_CB_ID : + hgfxtim->HAL_GFXTIM_EventGenerator_EV2Callback = HAL_GFXTIM_EventGenerator_EV2Callback; + break; + case HAL_GFXTIM_EVENT3_CB_ID : + hgfxtim->HAL_GFXTIM_EventGenerator_EV3Callback = HAL_GFXTIM_EventGenerator_EV3Callback; + break; + case HAL_GFXTIM_EVENT4_CB_ID : + hgfxtim->HAL_GFXTIM_EventGenerator_EV4Callback = HAL_GFXTIM_EventGenerator_EV4Callback; + break; + case HAL_GFXTIM_WDG_ALARM_CB_ID : + hgfxtim->HAL_GFXTIM_WatchdogTimer_AlarmCallback = HAL_GFXTIM_WatchdogTimer_AlarmCallback; + break; + case HAL_GFXTIM_WDG_PREALARM_CB_ID : + hgfxtim->HAL_GFXTIM_WatchdogTimer_PreAlarmCallback = HAL_GFXTIM_WatchdogTimer_PreAlarmCallback; + break; + case HAL_GFXTIM_ERROR_CB_ID : + hgfxtim->ErrorCallback = HAL_GFXTIM_ErrorCallback; + break; + case HAL_GFXTIM_MSP_INIT_CB_ID : + hgfxtim->MspInitCallback = HAL_GFXTIM_MspInit; + break; + case HAL_GFXTIM_MSP_DEINIT_CB_ID : + hgfxtim->MspDeInitCallback = HAL_GFXTIM_MspDeInit; + break; + default : + /* Update error code and status */ + hgfxtim->ErrorCode |= GFXTIM_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else if (hgfxtim->State == HAL_GFXTIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_GFXTIM_MSP_INIT_CB_ID : + hgfxtim->MspInitCallback = HAL_GFXTIM_MspInit; + break; + case HAL_GFXTIM_MSP_DEINIT_CB_ID : + hgfxtim->MspDeInitCallback = HAL_GFXTIM_MspDeInit; + break; + default : + /* Update error code and status */ + hgfxtim->ErrorCode |= GFXTIM_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else + { + /* Update error code and status */ + hgfxtim->ErrorCode |= GFXTIM_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + } + + return status; +} +#endif /* #if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1) */ + +/** + * @} + */ + +/** @defgroup GFXTIM_Exported_Functions_Group2 Clock Generator functions + * @brief Clock Generator functions + * +@verbatim + ============================================================================== + ##### Clock Generator functions ##### + ============================================================================== + [..] This section provides functions allowing to : + (+) Configure the clock generator. + (+) Force reload of FCC and LCC. + +@endverbatim + * @{ + */ + +/** + * @brief This function configures the clock generator. + * @param hgfxtim GFXTIM handle. + * @param pClockGeneratorConfig Clock Generator configuration parameters. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_ClockGenerator_Config(GFXTIM_HandleTypeDef *hgfxtim, + const GFXTIM_ClockGeneratorConfigTypeDef *pClockGeneratorConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hgfxtim == NULL) || (pClockGeneratorConfig == NULL)) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + assert_param(IS_GFXTIM_LCC_HW_RELOAD_SRC(pClockGeneratorConfig->LCCHwReloadSrc)); + assert_param(IS_GFXTIM_LCC_RELOAD_VALUE(pClockGeneratorConfig->LCCReloadValue)); + assert_param(IS_GFXTIM_LCC_CLK_SRC(pClockGeneratorConfig->LCCClockSrc)); + assert_param(IS_GFXTIM_LINE_CLK_SRC(pClockGeneratorConfig->LineClockSrc)); + assert_param(IS_GFXTIM_FCC_HW_RELOAD_SRC(pClockGeneratorConfig->FCCHwReloadSrc)); + assert_param(IS_GFXTIM_FCC_RELOAD_VALUE(pClockGeneratorConfig->FCCReloadValue)); + assert_param(IS_GFXTIM_FCC_CLK_SRC(pClockGeneratorConfig->FCCClockSrc)); + assert_param(IS_GFXTIM_FRAME_CLK_SRC(pClockGeneratorConfig->FrameClockSrc)); + assert_param(IS_GFXTIM_LINE_CLK_CALIB(pClockGeneratorConfig->LineClockCalib)); + assert_param(IS_GFXTIM_FRAME_CLK_CALIB(pClockGeneratorConfig->FrameClockCalib)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + /* Disable FCC and LCC */ + CLEAR_BIT(hgfxtim->Instance->CGCR, + GFXTIM_CGCR_LCCCS | GFXTIM_CGCR_FCCCS); + + /* Set Line Clock Counter (LCC) reload value (22 bits) */ + MODIFY_REG(hgfxtim->Instance->LCCRR, GFXTIM_LCCRR_RELOAD, + (pClockGeneratorConfig->LCCReloadValue << GFXTIM_LCCRR_RELOAD_Pos)); + + /* Set Frame Clock Counter (FCC) reload value (12 bits) */ + MODIFY_REG(hgfxtim->Instance->FCCRR, GFXTIM_FCCRR_RELOAD, + (pClockGeneratorConfig->FCCReloadValue << GFXTIM_FCCRR_RELOAD_Pos)); + + /* Set line and frame config */ + MODIFY_REG(hgfxtim->Instance->CGCR, + GFXTIM_CGCR_LCCHRS | GFXTIM_CGCR_LCCCS | GFXTIM_CGCR_LCS | + GFXTIM_CGCR_FCCHRS | GFXTIM_CGCR_FCCCS | GFXTIM_CGCR_FCS, + pClockGeneratorConfig->LCCHwReloadSrc | pClockGeneratorConfig->LCCClockSrc | + pClockGeneratorConfig->LineClockSrc | pClockGeneratorConfig->FCCHwReloadSrc | + pClockGeneratorConfig->FCCClockSrc | pClockGeneratorConfig->FrameClockSrc); + + /* Set debug output config for Line and frame clocks */ + MODIFY_REG(hgfxtim->Instance->CR, + GFXTIM_CR_LCCOE | GFXTIM_CR_FCCOE, + pClockGeneratorConfig->LineClockCalib | pClockGeneratorConfig->FrameClockCalib); + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief This function force clock generator counter(s) reload + * @param hgfxtim GFXTIM handle. + * @param ClockGeneratorCounter Clock Generator counter + * This parameter can be a value of @ref GFXTIM_ClockGeneratorCounter. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_ClockGenerator_Reload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t ClockGeneratorCounter) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + assert_param(IS_GFXTIM_CLOCK_GENERATOR_COUNTER(ClockGeneratorCounter)); + + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + SET_BIT(hgfxtim->Instance->CGCR, ClockGeneratorCounter); + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + + +/** + * @brief GFXTIM Tearing effect callback. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_TECallback(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_TECallback could be implemented in the user file */ +} + +/** + * @} + */ + +/** @defgroup GFXTIM_Exported_Functions_Group3 Absolute Timer functions + * @brief Absolute Timer functions + * +@verbatim + ============================================================================== + ##### Absolute Timers functions ##### + ============================================================================== + [..] This section provides functions allowing to : + (+) Configure the absolute timer. + (+) Start the absolute timer. + (+) Stop the absolute timer. + (+) Reset the absolute timer counters. + (+) Get the absolute time value. + (+) Set the absolute frame compare value. + (+) Set the absolute line compare value. +@endverbatim + * @{ + */ + +/** + * @brief This function configures an absolute Timer. + * @param hgfxtim GFXTIM handle. + * @param pAbsoluteTimerConfig pointer to a GFXTIM_AbsoluteTimerConfigTypeDef structure that + * contains absoluite timer comparators and counters values. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Config(GFXTIM_HandleTypeDef *hgfxtim, + const GFXTIM_AbsoluteTimerConfigTypeDef *pAbsoluteTimerConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hgfxtim == NULL) || (pAbsoluteTimerConfig == NULL)) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + assert_param(IS_GFXTIM_ABSOLUTE_FRAME_VALUE(pAbsoluteTimerConfig->FrameCompare1Value)); + assert_param(IS_GFXTIM_ABSOLUTE_FRAME_VALUE(pAbsoluteTimerConfig->FrameCounterValue)); + assert_param(IS_GFXTIM_INTERRUPT(pAbsoluteTimerConfig->FrameOverflowInterrupt)); + assert_param(IS_GFXTIM_INTERRUPT(pAbsoluteTimerConfig->FrameCompare1Interrupt)); + assert_param(IS_GFXTIM_ABSOLUTE_LINE_VALUE(pAbsoluteTimerConfig->LineCompare1Value)); + assert_param(IS_GFXTIM_ABSOLUTE_LINE_VALUE(pAbsoluteTimerConfig->LineCompare2Value)); + assert_param(IS_GFXTIM_ABSOLUTE_LINE_VALUE(pAbsoluteTimerConfig->LineCounterValue)); + assert_param(IS_GFXTIM_INTERRUPT(pAbsoluteTimerConfig->LineOverflowInterrupt)); + assert_param(IS_GFXTIM_INTERRUPT(pAbsoluteTimerConfig->LineCompare1Interrupt)); + assert_param(IS_GFXTIM_INTERRUPT(pAbsoluteTimerConfig->LineCompare2Interrupt)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + + /* Set AFC compare 1 value */ + MODIFY_REG(hgfxtim->Instance->AFCC1R, GFXTIM_AFCC1R_FRAME, + (pAbsoluteTimerConfig->FrameCompare1Value << GFXTIM_AFCC1R_FRAME_Pos)); + + /* Set AFC counter value */ + MODIFY_REG(hgfxtim->Instance->AFCR, GFXTIM_AFCR_FRAME, + (pAbsoluteTimerConfig->FrameCounterValue << GFXTIM_AFCR_FRAME_Pos)); + + /* Set ALC compare 1 value */ + MODIFY_REG(hgfxtim->Instance->ALCC1R, GFXTIM_ALCC1R_LINE, + (pAbsoluteTimerConfig->LineCompare1Value << GFXTIM_ALCC1R_LINE_Pos)); + + /* Set ALC compare 2 value */ + MODIFY_REG(hgfxtim->Instance->ALCC2R, GFXTIM_ALCC2R_LINE, + (pAbsoluteTimerConfig->LineCompare2Value << GFXTIM_ALCC2R_LINE_Pos)); + + /* Set ALC counter value */ + MODIFY_REG(hgfxtim->Instance->ALCR, GFXTIM_ALCR_LINE, + (pAbsoluteTimerConfig->LineCounterValue << GFXTIM_ALCR_LINE_Pos)); + + /* Set ALC compare 1, compare 2, overflow interrupts, AFC compare 1 and overflow interrupts */ + MODIFY_REG(hgfxtim->Instance->IER, + GFXTIM_IER_ALCC1IE | GFXTIM_IER_ALCC2IE | GFXTIM_IER_ALCOIE | GFXTIM_IER_AFCC1IE | GFXTIM_IER_AFCOIE, + (pAbsoluteTimerConfig->FrameOverflowInterrupt << GFXTIM_IER_AFCOIE_Pos) | + (pAbsoluteTimerConfig->FrameCompare1Interrupt << GFXTIM_IER_AFCC1IE_Pos) | + (pAbsoluteTimerConfig->LineOverflowInterrupt << GFXTIM_IER_ALCOIE_Pos) | + (pAbsoluteTimerConfig->LineCompare1Interrupt << GFXTIM_IER_ALCC1IE_Pos) | + (pAbsoluteTimerConfig->LineCompare2Interrupt << GFXTIM_IER_ALCC2IE_Pos)); + } + else + { + status = HAL_ERROR; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief This function starts absolute timer. + * @param hgfxtim GFXTIM handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Start(GFXTIM_HandleTypeDef *hgfxtim) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + /* Enable absolute Timer */ + SET_BIT(hgfxtim->Instance->TCR, (GFXTIM_TCR_AFCEN | GFXTIM_TCR_ALCEN)); + } + else + { + status = HAL_ERROR; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief This function stops absolute timer counter(s). + * @param hgfxtim GFXTIM handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Stop(GFXTIM_HandleTypeDef *hgfxtim) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + /* Disable absolute counter(s) */ + SET_BIT(hgfxtim->Instance->TDR, (GFXTIM_TDR_ALCDIS | GFXTIM_TDR_AFCDIS)); + } + else + { + status = HAL_ERROR; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief This function resets absolute timer counters. + * @param hgfxtim GFXTIM handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Reset(GFXTIM_HandleTypeDef *hgfxtim) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + /* Disable absolute counter(s) */ + SET_BIT(hgfxtim->Instance->TCR, (GFXTIM_TCR_FAFCR | GFXTIM_TCR_FALCR)); + } + else + { + status = HAL_ERROR; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief This function gets absolute timer value. + * @param hgfxtim GFXTIM handle. + * @param AbsoluteTime absolute time + * This parameter can be a value of @ref GFXTIM_AbsoluteTime. + * @param pValue Absolute time value + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_GetCounter(const GFXTIM_HandleTypeDef *hgfxtim, uint32_t AbsoluteTime, + uint32_t *pValue) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hgfxtim == NULL) || (pValue == NULL)) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + assert_param(IS_GFXTIM_ABSOLUTE_TIME(AbsoluteTime)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + switch (AbsoluteTime) + { + case GFXTIM_ABSOLUTE_GLOBAL_TIME: + *pValue = READ_REG(hgfxtim->Instance->ATR); + break; + case GFXTIM_ABSOLUTE_FRAME_TIME: + *pValue = READ_REG(hgfxtim->Instance->AFCR); + break; + default: + /* GFXTIM_ABSOLUTE_LINE_TIME */ + *pValue = READ_REG(hgfxtim->Instance->ALCR); + break; + } + } + else + { + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief This function sets absolute frame compare value. + * @param hgfxtim GFXTIM handle. + * @param Value Absolute frame compare 1 value + * This parameter can be a number between Min_Data = 0x00000 and Max_Data = 0xFFFFF + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_SetFrameCompare(GFXTIM_HandleTypeDef *hgfxtim, uint32_t Value) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + /* Set absolute frame counter compare 1 register value */ + MODIFY_REG(hgfxtim->Instance->AFCC1R, GFXTIM_AFCC1R_FRAME, + (Value << GFXTIM_AFCC1R_FRAME_Pos)); + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief This function sets line compare value. + * @param hgfxtim GFXTIM handle. + * @param AbsoluteLineComparator Absolute line compare value + * This parameter can be a value of @ref GFXTIM_AbsoluteLineComparator. + * @param Value Absolute line compare value + * This parameter can be a number between Min_Data = 0x000 and Max_Data = 0xFFF + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_SetLineCompare(GFXTIM_HandleTypeDef *hgfxtim, + uint32_t AbsoluteLineComparator, uint32_t Value) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + assert_param(IS_GFXTIM_ABSOLUTE_LINE_COMPARATOR(AbsoluteLineComparator)); + assert_param(IS_GFXTIM_ABSOLUTE_LINE_VALUE(Value)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + switch (AbsoluteLineComparator) + { + case GFXTIM_ABSOLUTE_LINE_COMPARE1: + WRITE_REG(hgfxtim->Instance->ALCC1R, Value); + break; + default: + /* GFXTIM_ABSOLUTE_LINE_COMPARE2 */ + WRITE_REG(hgfxtim->Instance->ALCC2R, Value); + break; + } + } + else + { + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief GFXTIM Absolute frame counter overflow callback. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_AbsoluteTimer_AFCOFCallback(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_AbsoluteTimer_AFCOFCallback could be implemented in the user file */ +} + +/** + * @brief GFXTIM Absolute frame counter compare 1 callback. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_AbsoluteTimer_AFCC1Callback(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_AbsoluteTimer_AFCC1Callback could be implemented in the user file */ +} + +/** + * @brief GFXTIM Absolute line counter compare 1 callback. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_AbsoluteTimer_ALCC1Callback(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_AbsoluteTimer_ALCC1Callback could be implemented in the user file */ +} + +/** + * @brief GFXTIM Absolute line counter compare 2 callback. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_AbsoluteTimer_ALCC2Callback(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_AbsoluteTimer_ALCC2Callback could be implemented in the user file */ +} + +/** + * @brief GFXTIM Absolute line counter overflow callback. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_AbsoluteTimer_ALCOFCallback(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_AbsoluteTimer_ALCOFCallback could be implemented in the user file */ +} + +/** + * @} + */ + +/** @defgroup GFXTIM_Exported_Functions_Group4 Relative Timer functions + * @brief Clock Generator functions + * +@verbatim + ============================================================================== + ##### Relative Timer functions ##### + ============================================================================== + [..] This section provides functions allowing to : + (+) Configure a relative timer. + (+) Start a relative timer counter. + (+) Stop a relative timer counter. + (+) Force a relative timer counter reload. + (+) Set a relative timer reload value. + (+) Get a relative timer counter value. + +@endverbatim + * @{ + */ + +/** + * @brief This function configures a Relative Timer. + * @param hgfxtim GFXTIM handle. + * @param pRelativeTimerConfig pointer to a GFXTIM_RelativeTimerConfigTypeDef structure that + * contains relative timer comparators and counters values. + * @param RelativeTimer Relative Timer identifier + * This parameter can be a value of @ref GFXTIM_RelativeTimer. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Config(GFXTIM_HandleTypeDef *hgfxtim, + const GFXTIM_RelativeTimerConfigTypeDef *pRelativeTimerConfig, + uint32_t RelativeTimer) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hgfxtim == NULL) || (pRelativeTimerConfig == NULL)) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + assert_param(IS_GFXTIM_RELATIVE_FRAME_VALUE(pRelativeTimerConfig->AutoReloadValue)); + assert_param(IS_GFXTIM_RELATIVE_FRAME_VALUE(pRelativeTimerConfig->CounterMode)); + assert_param(IS_GFXTIM_INTERRUPT(pRelativeTimerConfig->ReloadInterrupt)); + assert_param(IS_GFXTIM_RELATIVE_TIMER(RelativeTimer)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + if (RelativeTimer == GFXTIM_RELATIVE_TIMER1) + { + /* Set RFC1 auto reload */ + MODIFY_REG(hgfxtim->Instance->RFC1RR, GFXTIM_RFC1RR_FRAME, + pRelativeTimerConfig->AutoReloadValue << GFXTIM_RFC1RR_FRAME_Pos); + + /* Set relative timer mode */ + MODIFY_REG(hgfxtim->Instance->TCR, GFXTIM_TCR_RFC1CM, + (pRelativeTimerConfig->CounterMode << GFXTIM_TCR_RFC1CM_Pos)); + + /* Set relative timer 1 interrupt */ + MODIFY_REG(hgfxtim->Instance->IER, GFXTIM_IER_RFC1RIE_Msk, + (pRelativeTimerConfig->ReloadInterrupt << GFXTIM_IER_RFC1RIE_Pos)); + } + else + { + /* Set RFC2 auto reload */ + MODIFY_REG(hgfxtim->Instance->RFC2RR, GFXTIM_RFC2RR_FRAME, + pRelativeTimerConfig->AutoReloadValue << GFXTIM_RFC2RR_FRAME_Pos); + + /* Set relative timer mode */ + MODIFY_REG(hgfxtim->Instance->TCR, GFXTIM_TCR_RFC2CM, + (pRelativeTimerConfig->CounterMode << GFXTIM_TCR_RFC2CM_Pos)); + + /* Set relative timer 2 interrupt */ + MODIFY_REG(hgfxtim->Instance->IER, GFXTIM_IER_RFC2RIE_Msk, + (pRelativeTimerConfig->ReloadInterrupt << GFXTIM_IER_RFC2RIE_Pos)); + } + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief This function starts a relative Timer. + * @param hgfxtim GFXTIM handle. + * @param RelativeTimer Relative timer counter to Enable + * This parameter can be a value of @ref GFXTIM_RelativeTimer. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Start(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + assert_param(IS_GFXTIM_RELATIVE_TIMER(RelativeTimer)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + if (RelativeTimer == GFXTIM_RELATIVE_TIMER1) + { + /* Enable relative timer 1 */ + SET_BIT(hgfxtim->Instance->TCR, GFXTIM_TCR_RFC1EN); + } + else + { + /* Enable relative timer 2 */ + SET_BIT(hgfxtim->Instance->TCR, GFXTIM_TCR_RFC2EN); + } + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief This function stops a relative Timer counter. + * @param hgfxtim GFXTIM handle. + * @param RelativeTimer Relative timer counter to Disable + * This parameter can be a value of @ref GFXTIM_RelativeTimer. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Stop(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + assert_param(IS_GFXTIM_RELATIVE_TIMER(RelativeTimer)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + if (RelativeTimer == GFXTIM_RELATIVE_TIMER1) + { + /* Disable relative timer 1 */ + SET_BIT(hgfxtim->Instance->TDR, GFXTIM_TDR_RFC1DIS); + } + else + { + /* Disable relative timer 2 */ + SET_BIT(hgfxtim->Instance->TDR, GFXTIM_TDR_RFC2DIS); + } + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + + +/** + * @brief This function force a relative Timer reload. + * @param hgfxtim GFXTIM handle. + * @param RelativeTimer Relative timer to Foce Reload + * This parameter can be a value of @ref GFXTIM_RelativeTimer. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_ForceReload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + assert_param(IS_GFXTIM_RELATIVE_TIMER(RelativeTimer)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + if (RelativeTimer == GFXTIM_RELATIVE_TIMER1) + { + /* Force relative timer 1 reload */ + SET_BIT(hgfxtim->Instance->TCR, GFXTIM_TCR_FRFC1R); + } + else + { + /* Force relative timer 2 reload*/ + SET_BIT(hgfxtim->Instance->TCR, GFXTIM_TCR_FRFC2R); + } + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + + +/** + * @brief This function sets Relative frame timer reload value. + * @param hgfxtim GFXTIM handle. + * @param RelativeTimer specifies the Auto-reload register to be modified. + * This parameter can be a value of @ref GFXTIM_RelativeTimer. + * @param Value Reload value + * This parameter can be a number between Min_Data = 0x000 and Max_Data = 0xFFF + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_SetReload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer, + uint32_t Value) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + assert_param(IS_GFXTIM_RELATIVE_FRAME_VALUE(Value)); + assert_param(IS_GFXTIM_RELATIVE_TIMER(RelativeTimer)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + if (RelativeTimer == GFXTIM_RELATIVE_TIMER1) + { + /* Set RFC1 auto reload */ + WRITE_REG(hgfxtim->Instance->RFC1RR, Value); + } + else + { + /* Set RFC2 auto reload */ + WRITE_REG(hgfxtim->Instance->RFC2RR, Value); + } + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief This function sets Relative frame timer compare value. + * @param hgfxtim GFXTIM handle. + * @param RelativeTimer Relative frame counter reload + * This parameter can be a value of @ref GFXTIM_RelativeTimer. + * @param pValue pointer to a relative frame counter value + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_GetCounter(const GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer, + uint32_t *pValue) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hgfxtim == NULL) || (pValue == NULL)) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + assert_param(IS_GFXTIM_RELATIVE_TIMER(RelativeTimer)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + if (RelativeTimer == GFXTIM_RELATIVE_TIMER1) + { + /* Set RFC1 auto reload */ + *pValue = READ_REG(hgfxtim->Instance->RFC1R); + } + else + { + /* Set RFC2 auto reload */ + *pValue = READ_REG(hgfxtim->Instance->RFC2R); + } + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + + + + +/** + * @brief GFXTIM Relative frame counter 1 reload callback. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_RelativeTimer_RFC1RCallback(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_RelativeTimer_RFC1RCallback could be implemented in the user file */ +} + +/** + * @brief GFXTIM Relative frame counter 2 reload callback. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_RelativeTimer_RFC2RCallback(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_RelativeTimer_RFC2RCallback could be implemented in the user file */ +} + +/** + * @} + */ + +/** @defgroup GFXTIM_Exported_Functions_Group5 Event Generator functions + * @brief Event Generator functions + * +@verbatim + ============================================================================== + ##### Event Generator functions ##### + ============================================================================== + [..] This section provides functions allowing to : + (+) Configure an Event Generator. + (+) Enable an Event Generator. + (+) Disable an Event Generator. +@endverbatim + * @{ + */ + +/** + * @brief This function configures an Event Generator. + * @param hgfxtim GFXTIM handle. + * @param EventGenerator Event Generator + * This parameter can be a value of @ref GFXTIM_EventGenerator. + * @param pEventGeneratorConfig pointer to a GFXTIM_EventGeneratorConfigTypeDef structure that + * contains Event Generator configuration parameters. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_EventGenerator_Config(GFXTIM_HandleTypeDef *hgfxtim, uint32_t EventGenerator, + const GFXTIM_EventGeneratorConfigTypeDef *pEventGeneratorConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t shift; + + if ((hgfxtim == NULL) || (pEventGeneratorConfig == NULL)) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_EVENT_GENERATOR(EventGenerator)); + assert_param(IS_GFXTIM_EVENT_LINE(pEventGeneratorConfig->LineEvent)); + assert_param(IS_GFXTIM_EVENT_FRAME(pEventGeneratorConfig->FrameEvent)); + assert_param(IS_GFXTIM_INTERRUPT(pEventGeneratorConfig->EventInterrupt)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + /* Select frame and line events */ + shift = (EventGenerator) * 8U; + MODIFY_REG(hgfxtim->Instance->EVSR, \ + ((GFXTIM_EVSR_LES1 | GFXTIM_EVSR_FES1) << shift), + ((pEventGeneratorConfig->LineEvent | pEventGeneratorConfig->FrameEvent) << shift)); + + /* Event interrupt */ + MODIFY_REG(hgfxtim->Instance->IER, \ + (GFXTIM_IER_EV1IE << (EventGenerator)), \ + (pEventGeneratorConfig->EventInterrupt << (EventGenerator + GFXTIM_IER_EV1IE_Pos))); + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief This function enables an Event Generator. + * @param hgfxtim GFXTIM handle. + * @param EventGenerator Event Generator + * This parameter can be a value of @ref GFXTIM_EventGenerator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_EventGenerator_Enable(GFXTIM_HandleTypeDef *hgfxtim, uint32_t EventGenerator) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_EVENT_GENERATOR(EventGenerator)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + /* Enable event generator */ + SET_BIT(hgfxtim->Instance->EVCR, GFXTIM_EVCR_EV1EN << EventGenerator); + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief This function disables an Event Generator. + * @param hgfxtim GFXTIM handle. + * @param EventGenerator Event Generator + * This parameter can be a value of @ref GFXTIM_EventGenerator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_EventGenerator_Disable(GFXTIM_HandleTypeDef *hgfxtim, uint32_t EventGenerator) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_EVENT_GENERATOR(EventGenerator)); + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + /* Disable event generator */ + CLEAR_BIT(hgfxtim->Instance->EVCR, GFXTIM_EVCR_EV1EN << EventGenerator); + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + + + +/** + * @brief GFXTIM Combined events 1 callback. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_EventGenerator_EV1Callback(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_EventGenerator_EV1Callback could be implemented in the user file */ +} + +/** + * @brief GFXTIM Combined events 2 callback. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_EventGenerator_EV2Callback(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_EventGenerator_EV2Callback could be implemented in the user file */ +} + +/** + * @brief GFXTIM Combined events 3 callback. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_EventGenerator_EV3Callback(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_EventGenerator_EV3Callback could be implemented in the user file */ +} + +/** + * @brief GFXTIM Combined events 4 callback. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_EventGenerator_EV4Callback(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_EventGenerator_EV4Callback could be implemented in the user file */ +} + +/** + * @} + */ + +/** @defgroup GFXTIM_Exported_Functions_Group6 Watchdog functions + * @brief Event Generator functions + * +@verbatim + ============================================================================== + ##### Watchdog functions ##### + ============================================================================== + [..] This section provides functions allowing to : + (+) Configure the Watchdog. + (+) Enable the Watchdog + (+) Disable the Watchdog. + (+) Refresh the Watchdog. +@endverbatim + * @{ + */ + +/** + * @brief This function configures the Watchdog. + * @param hgfxtim GFXTIM handle. + * @param pWatchdogConfig Watchdog configuration parameters. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Config(GFXTIM_HandleTypeDef *hgfxtim, + const GFXTIM_WatchdogConfigTypeDef *pWatchdogConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hgfxtim == NULL) || (pWatchdogConfig == NULL)) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + assert_param(IS_GFXTIM_WATCHDOG_CLOCK_SRC(pWatchdogConfig->ClockSrc)); + assert_param(IS_GFXTIM_WATCHDOG_HW_RELOAD_CONFIG(pWatchdogConfig->HwReloadConfig)); + + assert_param(IS_GFXTIM_WATCHDOG_VALUE(pWatchdogConfig->AutoReloadValue)); + assert_param(IS_GFXTIM_WATCHDOG_VALUE(pWatchdogConfig->PreAlarmValue)); + + assert_param(IS_GFXTIM_INTERRUPT(pWatchdogConfig->AlarmInterrupt)); + assert_param(IS_GFXTIM_INTERRUPT(pWatchdogConfig->PreAlarmInterrupt)); + + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + /* Set watchdog auto reload value */ + MODIFY_REG(hgfxtim->Instance->WDGRR, GFXTIM_WDGRR_RELOAD, + (pWatchdogConfig->AutoReloadValue << GFXTIM_WDGRR_RELOAD_Pos)); + + /* Set watchdog pre alarm value */ + MODIFY_REG(hgfxtim->Instance->WDGPAR, GFXTIM_WDGPAR_PREALARM, + pWatchdogConfig->PreAlarmValue << GFXTIM_WDGPAR_PREALARM_Pos); + + /* Set watchdog clock source and hardware reload */ + MODIFY_REG(hgfxtim->Instance->WDGTCR, (GFXTIM_WDGTCR_WDGCS | GFXTIM_WDGTCR_WDGHRC), + (pWatchdogConfig->ClockSrc | pWatchdogConfig->HwReloadConfig)); + + /* Set watchdog interrupts */ + MODIFY_REG(hgfxtim->Instance->IER, \ + (GFXTIM_IER_WDGAIE | GFXTIM_IER_WDGPIE), \ + ((pWatchdogConfig->AlarmInterrupt << GFXTIM_IER_WDGAIE_Pos) | \ + (pWatchdogConfig->PreAlarmInterrupt << GFXTIM_IER_WDGPIE_Pos))); + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief This function Enable the Watchdog Counter. + * @param hgfxtim GFXTIM handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Enable(GFXTIM_HandleTypeDef *hgfxtim) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + /* Set watchdog enable bit */ + SET_BIT(hgfxtim->Instance->WDGTCR, GFXTIM_WDGTCR_WDGEN); + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief This function Disable the Watchdog Counter. + * @param hgfxtim GFXTIM handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Disable(GFXTIM_HandleTypeDef *hgfxtim) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + /* Set watchdog disable bit */ + SET_BIT(hgfxtim->Instance->WDGTCR, GFXTIM_WDGTCR_WDGDIS); + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief This function refresh the Watchdog counter. + * @param hgfxtim GFXTIM handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Refresh(GFXTIM_HandleTypeDef *hgfxtim) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hgfxtim == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance)); + + + if (hgfxtim->State == HAL_GFXTIM_STATE_READY) + { + /* Set watchdog SW relaod */ + SET_BIT(hgfxtim->Instance->WDGTCR, GFXTIM_WDGTCR_FWDGR); + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief GFXTIM Watchdog alarm callback. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_WatchdogTimer_AlarmCallback(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_WatchdogTimer_AlarmCallback could be implemented in the user file */ +} + +/** + * @brief GFXTIM Watchdog pre alarm callback. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_WatchdogTimer_PreAlarmCallback(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_WatchdogTimer_PreAlarmCallback could be implemented in the user file */ +} + +/** + * @} + */ + +/** @defgroup GFXTIM_Exported_Functions_Group7 Generic functions + * @brief Generic functions + * +@verbatim + ============================================================================== + ##### Generic functions ##### + ============================================================================== + [..] This section provides functions allowing to : + (+) Handle GFXTIM interrupt. + (+) Inform user that error occurs. + (+) Get the current GFXTIM instance state + (+) Get the current GFXTIM instance error code. +@endverbatim + * @{ + */ + +/** + * @brief This function handles the GFXTIM interrupts. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +void HAL_GFXTIM_IRQHandler(GFXTIM_HandleTypeDef *hgfxtim) +{ + uint32_t tmp_reg1; + uint32_t tmp_reg2; + uint32_t interrupts; + + /* Read all pending interrupts */ + tmp_reg1 = READ_REG(hgfxtim->Instance->ISR); + tmp_reg2 = READ_REG(hgfxtim->Instance->IER); + interrupts = tmp_reg1 & tmp_reg2; + + if ((interrupts & GFXTIM_ISR_AFCC1F) != 0U) + { +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U) + hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCC1Callback(hgfxtim); +#else + HAL_GFXTIM_AbsoluteTimer_AFCC1Callback(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + } + + if ((interrupts & GFXTIM_ISR_AFCOF) != 0U) + { +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U) + hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCOFCallback(hgfxtim); +#else + HAL_GFXTIM_AbsoluteTimer_AFCOFCallback(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + } + + if ((interrupts & GFXTIM_ISR_ALCC1F) != 0U) + { +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U) + hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC1Callback(hgfxtim); +#else + HAL_GFXTIM_AbsoluteTimer_ALCC1Callback(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + } + + if ((interrupts & GFXTIM_ISR_ALCC2F) != 0U) + { +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U) + hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC2Callback(hgfxtim); +#else + HAL_GFXTIM_AbsoluteTimer_ALCC2Callback(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + } + + if ((interrupts & GFXTIM_ISR_ALCOF) != 0U) + { +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U) + hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCOFCallback(hgfxtim); +#else + HAL_GFXTIM_AbsoluteTimer_ALCOFCallback(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + } + + if ((interrupts & GFXTIM_ISR_TEF) != 0U) + { +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U) + hgfxtim->HAL_GFXTIM_TECallback(hgfxtim); +#else + HAL_GFXTIM_TECallback(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + } + + if ((interrupts & GFXTIM_ISR_RFC1RF) != 0U) + { +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U) + hgfxtim->HAL_GFXTIM_RelativeTimer_RFC1RCallback(hgfxtim); +#else + HAL_GFXTIM_RelativeTimer_RFC1RCallback(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + } + + if ((interrupts & GFXTIM_ISR_RFC2RF) != 0U) + { +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U) + hgfxtim->HAL_GFXTIM_RelativeTimer_RFC2RCallback(hgfxtim); +#else + HAL_GFXTIM_RelativeTimer_RFC2RCallback(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + } + + if ((interrupts & GFXTIM_ISR_EV1F) != 0U) + { +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U) + hgfxtim->HAL_GFXTIM_EventGenerator_EV1Callback(hgfxtim); +#else + HAL_GFXTIM_EventGenerator_EV1Callback(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + } + + if ((interrupts & GFXTIM_ISR_EV2F) != 0U) + { +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U) + hgfxtim->HAL_GFXTIM_EventGenerator_EV2Callback(hgfxtim); +#else + HAL_GFXTIM_EventGenerator_EV2Callback(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + } + + if ((interrupts & GFXTIM_ISR_EV3F) != 0U) + { +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U) + hgfxtim->HAL_GFXTIM_EventGenerator_EV3Callback(hgfxtim); +#else + HAL_GFXTIM_EventGenerator_EV3Callback(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + } + + if ((interrupts & GFXTIM_ISR_EV4F) != 0U) + { +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U) + hgfxtim->HAL_GFXTIM_EventGenerator_EV4Callback(hgfxtim); +#else + HAL_GFXTIM_EventGenerator_EV4Callback(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + } + + if ((interrupts & GFXTIM_ISR_WDGAF) != 0U) + { +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U) + hgfxtim->HAL_GFXTIM_WatchdogTimer_AlarmCallback(hgfxtim); +#else + HAL_GFXTIM_WatchdogTimer_AlarmCallback(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + } + + if ((interrupts & GFXTIM_ISR_WDGPF) != 0U) + { +#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U) + hgfxtim->HAL_GFXTIM_WatchdogTimer_PreAlarmCallback(hgfxtim); +#else + HAL_GFXTIM_WatchdogTimer_PreAlarmCallback(hgfxtim); +#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */ + } + /* Clear all pending interrupts */ + WRITE_REG(hgfxtim->Instance->ICR, interrupts); +} + +/** + * @brief GFXTIM error callback. + * @param hgfxtim GFXTIM handle. + * @retval None. + */ +__weak void HAL_GFXTIM_ErrorCallback(GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgfxtim); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_GFXTIM_ErrorCallback could be implemented in the user file. */ +} + +/** + * @brief This function get the current GFXTIM state. + * @param hgfxtim GFXTIM handle. + * @retval GFXTIM state. + */ +HAL_GFXTIM_StateTypeDef HAL_GFXTIM_GetState(const GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Return GFXTIM state */ + return hgfxtim->State; +} + +/** + * @brief This function get the current GFXTIM error. + * @param hgfxtim GFXTIM handle. + * @retval GFXTIM error code. + */ +uint32_t HAL_GFXTIM_GetError(const GFXTIM_HandleTypeDef *hgfxtim) +{ + /* Return GFXTIM error code */ + return hgfxtim->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* GFXTIM */ +#endif /* HAL_GFXTIM_MODULE_ENABLED */ +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gpio.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gpio.c new file mode 100644 index 00000000000..23933192f72 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gpio.c @@ -0,0 +1,555 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + (+) The external interrupt/event controller consists of up to 39 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To set the level of several pins and reset level of several other pins in + same cycle, use HAL_GPIO_WriteMultipleStatePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + * range of the shift operator in following API : + * HAL_GPIO_Init + * HAL_GPIO_DeInit + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants + * @{ + */ +#define GPIO_NUMBER (16u) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..H and M..P) to select the GPIO peripheral for STM32H7RSxx family + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t temp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + temp |= (GPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT0 << position) ; + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); + temp |= ((GPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos)); + GPIOx->PUPDR = temp; + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + temp &= ~(0xFu << ((position & 0x07u) * GPIO_AFRL_AFSEL1_Pos)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * GPIO_AFRL_AFSEL1_Pos)); + GPIOx->AFR[position >> 3u] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + { + temp = SBS->EXTICR[position >> 2u]; + temp &= ~(0x0FuL << ((position & 0x03u) * SBS_EXTICR1_PC_EXTI1_Pos)); + temp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03u) * SBS_EXTICR1_PC_EXTI1_Pos)); + SBS->EXTICR[position >> 2u] = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + { + temp |= iocurrent; + } + EXTI->RTSR1 = temp; + + temp = EXTI->FTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + { + temp |= iocurrent; + } + EXTI->FTSR1 = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->EMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + { + temp |= iocurrent; + } + EXTI->EMR1 = temp; + + temp = EXTI->IMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) + { + temp |= iocurrent; + } + EXTI->IMR1 = temp; + } + } + + position++; + } +} + +/** + * @brief De-initialize the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..H and M..P) to select the GPIO peripheral for STM32H7RSxx family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = SBS->EXTICR[position >> 2u]; + tmp &= (0x0FuL << ((position & 0x03u) * SBS_EXTICR1_PC_EXTI1_Pos)); + if (tmp == (GPIO_GET_INDEX(GPIOx) << ((position & 0x03u) * SBS_EXTICR1_PC_EXTI1_Pos))) + { + /* Clear EXTI line configuration */ + EXTI->IMR1 &= ~(iocurrent); + EXTI->EMR1 &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->FTSR1 &= ~(iocurrent); + EXTI->RTSR1 &= ~(iocurrent); + + /* Clear EXTICR configuration */ + tmp = 0x0FuL << ((position & 0x03u) * SBS_EXTICR1_PC_EXTI1_Pos); + SBS->EXTICR[position >> 2u] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * GPIO_AFRL_AFSEL1_Pos)) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); + } + + position++; + } +} + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx where x can be (A..H and M..P) to select the GPIO peripheral for STM32H7RSxx family + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0x00u) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Set or clear the selected data port bit. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx where x can be (A..H and M..P) to select the GPIO peripheral for STM32H7RSxx family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + +/** + * @brief Set and clear several pins of a dedicated port in same cycle. + * @param GPIOx where x can be (A..H and M..P) to select the GPIO peripheral for STM32H7RSxx family + * @param PinReset specifies the port bits to be reset + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @param PinSet specifies the port bits to be set + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @note Both PinReset and PinSet combinations shall not get any common bit, else + * assert would be triggered. + * @note At least one of the two parameters used to set or reset shall be different from zero. + * @retval None + */ +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet) +{ + uint32_t tmp; + + /* Check the parameters */ + /* Make sure at least one parameter is different from zero and that there is no common pin */ + assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet)); + assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet)); + + tmp = (((uint32_t)PinReset << 16) | PinSet); + GPIOx->BSRR = tmp; +} + +/** + * @brief Toggle the specified GPIO pin. + * @param GPIOx where x can be (A..H and M..P) to select the GPIO peripheral for STM32H7RSxx family + * @param GPIO_Pin specifies the pin to be toggled. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** + * @brief Lock GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx where x can be (A..H and M..P) to select the GPIO peripheral for STM32H7RSxx family + * @param GPIO_Pin specifies the port bits to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0U) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gpu2d.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gpu2d.c new file mode 100644 index 00000000000..cb8b2171e04 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gpu2d.c @@ -0,0 +1,750 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_gpu2d.c + * @author MCD Application Team + * @brief GPU2D HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the GPU2D peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Peripheral control is exclusively done by the accompanying middleware library. + + *** Interrupt mode IO operation *** + =================================== + [..] + (#) Configure the GPU2D hardware to perform graphics operation using the Third Party MW + Library APIs. + (#) Submit command List to the hardware. + (#) Wait indefinitely for the completion of submitted Command List by GPU2D hardware. + (#) Use HAL_GPU2D_IRQHandler() called under GPU2D_IRQHandler() interrupt subroutine. + (#) At the end of Command List execution HAL_GPU2D_IRQHandler() function is executed + and user can add his own function by customization of function pointer + (#) CommandListCpltCallback (member of GPU2D handle structure) to notify the upper level + about the completion of Command List execution. + + (#) Callback HAL_GPU2D_CommandListCpltCallback is invoked when the GPU2D hardware executes + the programmed command list (Command List execution completion). + + (++) This callback is called when the compilation defines USE_HAL_GPU2D_REGISTER_CALLBACKS + is set to 0 or not defined. + + (++) This callback should be implemented in the application side. It should notify + the upper level that the programmed command list is completed. + + (#) To control the GPU2D state, use the following function: HAL_GPU2D_GetState(). + + (#) To read the GPU2D error code, use the following function: HAL_GPU2D_GetError(). + + *** GPU2D HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in GPU2D HAL driver : + + (+) __HAL_GPU2D_RESET_HANDLE_STATE: Reset GPU2D handle state. + (+) __HAL_GPU2D_GET_FLAG: Get the GPU2D pending flags. + (+) __HAL_GPU2D_CLEAR_FLAG: Clear the GPU2D pending flags. + (+) __HAL_GPU2D_GET_IT_SOURCE: Check whether the specified GPU2D interrupt is enabled or not. + + *** Callback registration *** + =================================== + [..] + (#) The compilation define USE_HAL_GPU2D_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use function @ref HAL_GPU2D_RegisterCallback() to register a user callback. + + (#) Function @ref HAL_GPU2D_RegisterCallback() allows to register following callbacks: + (+) CommandListCpltCallback : callback for Command List completion. + (+) MspInitCallback : GPU2D MspInit. + (+) MspDeInitCallback : GPU2D MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (#) Use function @ref HAL_GPU2D_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_GPU2D_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) CommandListCpltCallback : callback for Command List completion. + (+) MspInitCallback : GPU2D MspInit. + (+) MspDeInitCallback : GPU2D MspDeInit. + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_GPU2D_RegisterCallback before calling @ref HAL_GPU2D_DeInit + or @ref HAL_GPU2D_Init function. + + When The compilation define USE_HAL_GPU2D_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + [..] + (@) You can refer to the GPU2D HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +#ifdef HAL_GPU2D_MODULE_ENABLED +#if defined (GPU2D) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup GPU2D GPU2D + * @brief GPU2D HAL module driver + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup GPU2D_Private_Macros GPU2D Private Macros + * @{ + */ + +/** @defgroup GPU2D_Write_Read Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPU2D register + * @param __INSTANCE__ GPU2D Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define GPU2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(*(__IO uint32_t *)(__INSTANCE__\ + + __REG__), __VALUE__) + +/** + * @brief Read a value in GPU2D register + * @param __INSTANCE__ GPU2D Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define GPU2D_ReadReg(__INSTANCE__, __REG__) READ_REG(*(__IO uint32_t *)(__INSTANCE__ + __REG__)) +/** + * @} + */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPU2D_Exported_Functions GPU2D Exported Functions + * @{ + */ + +/** @defgroup GPU2D_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the GPU2D + (+) De-initialize the GPU2D + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPU2D according to the specified + * parameters in the GPU2D_InitTypeDef and create the associated handle. + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_GPU2D_Init(GPU2D_HandleTypeDef *hgpu2d) +{ + /* Check the GPU2D handle validity */ + if (hgpu2d == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance)); + + if (hgpu2d->State == HAL_GPU2D_STATE_RESET) + { +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) + /* Reset Callback pointers in HAL_GPU2D_STATE_RESET only */ + hgpu2d->CommandListCpltCallback = HAL_GPU2D_CommandListCpltCallback; + if (hgpu2d->MspInitCallback == NULL) + { + hgpu2d->MspInitCallback = HAL_GPU2D_MspInit; + } + + /* Init the low level hardware */ + hgpu2d->MspInitCallback(hgpu2d); +#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */ + /* Init the low level hardware */ + HAL_GPU2D_MspInit(hgpu2d); +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + + /* Allocate lock resource and initialize it */ + hgpu2d->Lock = HAL_UNLOCKED; + } + + /* Process locked */ + __HAL_LOCK(hgpu2d); + +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) + /* Reset the CommandListCpltCallback handler */ + hgpu2d->CommandListCpltCallback = NULL; +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + + /* Update error code */ + hgpu2d->ErrorCode = HAL_GPU2D_ERROR_NONE; + + /* Initialize the GPU2D state*/ + hgpu2d->State = HAL_GPU2D_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(hgpu2d); + + return HAL_OK; +} + +/** + * @brief Deinitializes the GPU2D peripheral registers to their default reset + * values. + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval None + */ +HAL_StatusTypeDef HAL_GPU2D_DeInit(GPU2D_HandleTypeDef *hgpu2d) +{ + /* Check the GPU2D handle validity */ + if (hgpu2d == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance)); + + /* Process locked */ + __HAL_LOCK(hgpu2d); + + if (hgpu2d->State == HAL_GPU2D_STATE_READY) + { +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) + if (hgpu2d->MspDeInitCallback == NULL) + { + hgpu2d->MspDeInitCallback = HAL_GPU2D_MspDeInit; + } + + /* DeInit the low level hardware */ + hgpu2d->MspDeInitCallback(hgpu2d); +#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */ + /* Carry on with de-initialization of low level hardware */ + HAL_GPU2D_MspDeInit(hgpu2d); +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + } + +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) + /* Reset the CommandListCpltCallback handler */ + hgpu2d->CommandListCpltCallback = NULL; +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + + /* Update error code */ + hgpu2d->ErrorCode = HAL_GPU2D_ERROR_NONE; + + /* Reset the GPU2D state*/ + hgpu2d->State = HAL_GPU2D_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hgpu2d); + + return HAL_OK; +} + +/** + * @brief Initializes the GPU2D MSP. + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval None + */ +__weak void HAL_GPU2D_MspInit(GPU2D_HandleTypeDef *hgpu2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgpu2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_GPU2D_MspInit can be implemented in the user file. + */ +} + +/** + * @brief DeInitializes the GPU2D MSP. + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval None + */ +__weak void HAL_GPU2D_MspDeInit(GPU2D_HandleTypeDef *hgpu2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgpu2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_GPU2D_MspDeInit can be implemented in the user file. + */ +} + +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User GPU2D callback + * To be used instead of the weak (surcharged) predefined callback + * @param hgpu2d GPU2D handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_GPU2D_MSPINIT_CB_ID GPU2D MspInit callback ID + * @arg @ref HAL_GPU2D_MSPDEINIT_CB_ID GPU2D MspDeInit callback ID + * @param pCallback pointer to the callback function + * @note Weak predefined callback is defined for HAL_GPU2D_MSPINIT_CB_ID and HAL_GPU2D_MSPDEINIT_CB_ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_GPU2D_RegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID, + pGPU2D_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the GPU2D handle validity */ + if (hgpu2d == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hgpu2d); + + /* Check the pCallback parameter is valid or not */ + if (pCallback == NULL) + { + /* Update the error code */ + hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + else + { + if ((hgpu2d->State == HAL_GPU2D_STATE_READY) + || (hgpu2d->State == HAL_GPU2D_STATE_RESET)) + { + switch (CallbackID) + { + case HAL_GPU2D_MSPINIT_CB_ID: + hgpu2d->MspInitCallback = pCallback; + break; + + case HAL_GPU2D_MSPDEINIT_CB_ID: + hgpu2d->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + } + + /* Release lock */ + __HAL_UNLOCK(hgpu2d); + + return status; +} + +/** + * @brief Unregister a GPU2D callback + * GPU2D Callback is redirected to the weak (surcharged) predefined callback + * @param hgpu2d GPU2D handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_GPU2D_MSPINIT_CB_ID GPU2D MspInit callback ID + * @arg @ref HAL_GPU2D_MSPDEINIT_CB_ID GPU2D MspDeInit callback ID + * @note Callback pointers will be set to legacy weak predefined callbacks for HAL_GPU2D_MSPINIT_CB_ID and + * HAL_GPU2D_MSPDEINIT_CB_ID + * @retval status + */ +HAL_StatusTypeDef HAL_GPU2D_UnRegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the GPU2D handle validity */ + if (hgpu2d == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hgpu2d); + + if ((HAL_GPU2D_STATE_READY == hgpu2d->State) + || (HAL_GPU2D_STATE_RESET == hgpu2d->State)) + { + switch (CallbackID) + { + case HAL_GPU2D_MSPINIT_CB_ID: + hgpu2d->MspInitCallback = HAL_GPU2D_MspInit; /* Legacy weak Msp Init */ + break; + + case HAL_GPU2D_MSPDEINIT_CB_ID: + hgpu2d->MspDeInitCallback = HAL_GPU2D_MspDeInit; /* Legacy weak Msp DeInit */ + break; + + default : + /* Update the error code */ + hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release lock */ + __HAL_UNLOCK(hgpu2d); + + return status; +} + +/** + * @brief Register GPU2D Command List Complete Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hgpu2d GPU2D handle + * @param pCallback pointer to the Command List Complete Callback function + * @note Weak predefined callback is defined for Command List Complete + * @retval status + */ +HAL_StatusTypeDef HAL_GPU2D_RegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, + pGPU2D_CommandListCpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the GPU2D handle validity */ + if (hgpu2d == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hgpu2d); + + /* Check the CallbackID is valid or not */ + if (pCallback == NULL) + { + /* Update the error code */ + hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + else + { + if ((HAL_GPU2D_STATE_READY == hgpu2d->State) + || (HAL_GPU2D_STATE_RESET == hgpu2d->State)) + { + hgpu2d->CommandListCpltCallback = pCallback; + } + else + { + status = HAL_ERROR; + } + } + + /* Release lock */ + __HAL_UNLOCK(hgpu2d); + + return status; +} + +/** + * @brief Unregister a GPU2D Command List Complete Callback + * GPU2D Command List Complete Callback is redirected to the weak (surcharged) predefined callback + * @param hgpu2d GPU2D handle + * @note Callback pointer will be invalidate (NULL value) + * @retval status + */ +HAL_StatusTypeDef HAL_GPU2D_UnRegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the GPU2D handle validity */ + if (hgpu2d == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hgpu2d); + + if ((hgpu2d->State == HAL_GPU2D_STATE_READY) + || (hgpu2d->State == HAL_GPU2D_STATE_RESET)) + { + hgpu2d->CommandListCpltCallback = NULL; /* Invalidate the Callback pointer */ + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hgpu2d); + + return status; +} +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + +/** + * @} + */ + + +/** @defgroup GPU2D_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Read GPU2D Register value. + (+) Write a value to GPU2D Register. + (+) handle GPU2D interrupt request. + (+) Command List Complete Transfer Complete callback. + + +@endverbatim + * @{ + */ + +/** + * @brief Read GPU2D Register. Helper function for the higher-level library. + * @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @param offset The register offset from GPU2D base address to read. + * @retval Register value + */ +uint32_t HAL_GPU2D_ReadRegister(const GPU2D_HandleTypeDef *hgpu2d, uint32_t offset) +{ + uint32_t value; + + /* Check the GPU2D handle validity */ + assert_param(hgpu2d != NULL); + + /* Check the parameters */ + assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance)); + assert_param(IS_GPU2D_OFFSET(offset)); + + /* No locking is required since reading a register is an atomic operation + * and doesn't incur a state change in hal_gpu2d. */ + value = GPU2D_ReadReg(hgpu2d->Instance, offset); + + return value; +} + +/** + * @brief Write a value to GPU2D Register. Helper function for the higher-level library. + * @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @param offset The register offset from GPU2D base address to write. + * @param value The value to be written to provided register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_GPU2D_WriteRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset, uint32_t value) +{ + /* Check the GPU2D handle validity */ + assert_param(hgpu2d != NULL); + + /* Check the parameters */ + assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance)); + assert_param(IS_GPU2D_OFFSET(offset)); + + /* No locking is required since writing a register is an atomic operation + * and doesn't incur a state change in hal_gpu2d. */ + GPU2D_WriteReg(hgpu2d->Instance, offset, value); + + return HAL_OK; +} + +/** + * @brief Handle GPU2D interrupt request. + * @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval None + */ +void HAL_GPU2D_IRQHandler(GPU2D_HandleTypeDef *hgpu2d) +{ + uint32_t isr_flags = GPU2D_ReadReg(hgpu2d->Instance, GPU2D_ITCTRL); + + /* Command List Complete Interrupt management */ + if ((isr_flags & GPU2D_FLAG_CLC) != 0U) + { + uint32_t last_cl_id; + + /* Clear the completion flag */ + __HAL_GPU2D_CLEAR_FLAG(hgpu2d, GPU2D_FLAG_CLC); + + last_cl_id = GPU2D_ReadReg(hgpu2d->Instance, GPU2D_CLID); + + /* Command List Complete Callback */ +#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1) + if (hgpu2d->CommandListCpltCallback != NULL) + { + hgpu2d->CommandListCpltCallback(hgpu2d, last_cl_id); + } +#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */ + HAL_GPU2D_CommandListCpltCallback(hgpu2d, last_cl_id); +#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */ + } +} + +/** + * @brief Handle GPU2D Error interrupt request. + * @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval None + */ +void HAL_GPU2D_ER_IRQHandler(GPU2D_HandleTypeDef *hgpu2d) +{ + HAL_GPU2D_ErrorCallback(hgpu2d); +} + +/** + * @brief Command List Complete callback. + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @param CmdListID Command list ID that got completed. + * @retval None + */ +__weak void HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgpu2d); + UNUSED(CmdListID); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_GPU2D_CommandListCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Error handler callback. + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval None + */ +__weak void HAL_GPU2D_ErrorCallback(GPU2D_HandleTypeDef *hgpu2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hgpu2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_GPU2D_ErrorCallback can be implemented in the user file. + The default implementation stops the execution as an error is considered + fatal and non recoverable. + */ + + /* Infinite loop */ + for (;;) {}; +} + +/** + * @} + */ + + +/** @defgroup GPU2D_Exported_Functions_Group3 Peripheral State and Error functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to: + (+) Get the GPU2D state + (+) Get the GPU2D error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the GPU2D state + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for the GPU2D. + * @retval GPU2D state + */ +HAL_GPU2D_StateTypeDef HAL_GPU2D_GetState(GPU2D_HandleTypeDef const *const hgpu2d) +{ + return hgpu2d->State; +} + +/** + * @brief Return the GPU2D error code + * @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains + * the configuration information for GPU2D. + * @retval GPU2D Error Code + */ +uint32_t HAL_GPU2D_GetError(GPU2D_HandleTypeDef const *const hgpu2d) +{ + return hgpu2d->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* GPU2D */ +#endif /* HAL_GPU2D_MODULE_ENABLED */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_hash.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_hash.c new file mode 100644 index 00000000000..764382228ce --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_hash.c @@ -0,0 +1,3170 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_hash.c + * @author MCD Application Team + * @brief HASH HAL module driver. + * This file provides firmware functions to manage HASH peripheral + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The HASH HAL driver can be used as follows: + + (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit(): + (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE() + (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_Start_IT()) + (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority() + (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API + (##) When resorting to DMA-based APIs (e.g. HAL_HASH_Start_DMA()) + (+++) Enable the DMA interface clock + (+++) Configure and enable one DMA to manage data transfer from + memory to peripheral (input DMA). Managing data transfer from + peripheral to memory can be performed only using CPU. + (+++) Associate the initialized DMA handle to the HASH DMA handle + using __HAL_LINKDMA() + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA: use + HAL_NVIC_SetPriority() and + HAL_NVIC_EnableIRQ() + + (#)Initialize the HASH HAL using HAL_HASH_Init(). This function: + (##) resorts to HAL_HASH_MspInit() for low-level initialization, + (##) configures the data type: no swap, half word swap, bit swap or byte swap, + (##) configures the Algorithm : MD5, SHA1 or SHA2 + + (#)Three processing schemes are available: + (##) Polling mode: processing APIs are blocking functions + i.e. they process the data and wait till the digest computation is finished, + e.g. HAL_HASH_Start() for HASH or HAL_HMAC_Start() for HMAC + (##) Interrupt mode: processing APIs are not blocking functions + i.e. they process the data under interrupt, + e.g. HAL_HASH_Start_IT() for HASH or HAL_HMAC_Start_IT() for HMAC + (##) DMA mode: processing APIs are not blocking functions and the CPU is + not used for data transfer i.e. the data transfer is ensured by DMA, + e.g. HAL_HASH_Start_DMA() for HASH or HAL_HMAC_Start_DMA() for HMAC. + + (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is + initialized and processes the buffer fed in input. When the input data have all been + fed to the Peripheral, the digest computation can start. + + (#)Multi-buffer processing HASH and HMAC are possible in polling, interrupt and DMA modes. + (##) In polling mode, API HAL_HASH_Accumulate()/HAL_HASH_HMAC_Accumulate() must be called + for each input buffer, except for the last one. + User must resort to HAL_HASH_AccumulateLast()/HAL_HASH_HMAC_AccumulateLast() + to enter the last one and retrieve as well the computed digest. + + (##) In interrupt mode, API HAL_HASH_Accumulate_IT()/HAL_HASH_HMAC_Accumulate_IT() must + be called for each input buffer, except for the last one. + User must resort to HAL_HASH_AccumulateLast_IT()/HAL_HASH_HMAC_AccumulateLast_IT() + to enter the last one and retrieve as well the computed digest. + + (##) In DMA mode, once initialization is done, MDMAT bit must be set through + __HAL_HASH_SET_MDMAT() macro. + From that point, each buffer can be fed to the Peripheral through HAL_HASH_Start_DMA() API + for HASH and HAL_HASH_HMAC_Start_DMA() API for HMAC . + Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() + macro then wrap-up the HASH processing in feeding the last input buffer through the + same API HAL_HASH_Start_DMA()for HASH and HAL_HASH_HMAC_Start_DMA() API for HMAC and + retrieve as well the computed digest. + + (#)To use this driver (version 2.0.0) with application developed with old driver (version 1.0.0) user have to: + (##) Add Algorithm as parameter like DataType or KeySize. + (##) Use new API HAL_HASH_Start() for HASH and HAL_HASH_HMAC_Start() for HMAC processing instead of old API + like HAL_HASH_SHA1_Start and HAL_HMAC_SHA1_Start. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#if defined (HASH) + +/** @defgroup HASH HASH + * @brief HASH HAL module driver. + * @{ + */ + +#ifdef HAL_HASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup HASH_Private_Defines HASH Private Defines + * @{ + */ +#define HASH_TIMEOUTVALUE 1000U /*!< Time-out value */ +#define BLOCK_64B 64U /*!< block Size equal to 64 bytes */ +#define BLOCK_128B 128U /*!< block Size equal to 128 bytes */ +/** + * @} + */ + +/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers + * @{ + */ +#define HASH_NUMBER_OF_CSR_REGISTERS 103U /*!< Number of Context Swap Registers */ +/** + * @} + */ + +/* Private Constants ---------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup HASH_Private_Functions HASH Private Functions + * @{ + */ +static void HASH_GetDigest(const HASH_HandleTypeDef *hhash, const uint8_t *pMsgDigest, uint8_t Size); +static void HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *pInBuffer, uint32_t Size); +static HAL_StatusTypeDef HASH_WriteData_IT(HASH_HandleTypeDef *hhash); +static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); +static void HASH_DMAError(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, + uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup HASH_Exported_Functions HASH Exported Functions + * @{ + */ + +/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and configuration functions. + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the HASH according to the specified parameters + in the HASH_InitTypeDef and create the associated handle + (+) DeInitialize the HASH peripheral + (+) Initialize the HASH MCU Specific Package (MSP) + (+) DeInitialize the HASH MSP + (+) Configure HASH (HAL_HASH_SetConfig) with the specified parameters in the HASH_ConfigTypeDef + Parameters which are configured in This section are : + (+) Data Type : no swap, half word swap, bit swap or byte swap + (+) Algorithm : MD5,SHA1 or SHA2 + (+) Get HASH configuration (HAL_HASH_GetConfig) from the specified parameters in the HASH_HandleTypeDef + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the HASH according to the specified parameters in the + HASH_HandleTypeDef and create the associated handle. + * @note Only Algorithm and DATATYPE bits of HASH Peripheral are set by HAL_HASH_Init(), + * other configuration bits are set by HASH or HMAC processing APIs. + * @param hhash pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) +{ + uint32_t cr_value; + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_HASH_DATATYPE(hhash->Init.DataType)); + assert_param(IS_HASH_ALGORITHM(hhash->Init.Algorithm)); + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + if (hhash->State == HAL_HASH_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhash->Lock = HAL_UNLOCKED; + + /* Reset Callback pointers in HAL_HASH_STATE_RESET only */ + hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak InCpltCallback */ + hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak DgstCpltCallback */ + hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak ErrorCallback */ + if (hhash->MspInitCallback == NULL) + { + hhash->MspInitCallback = HAL_HASH_MspInit; + } + + /* Init the low level hardware */ + hhash->MspInitCallback(hhash); + } +#else + if (hhash->State == HAL_HASH_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhash->Lock = HAL_UNLOCKED; + + /* Init the low level hardware */ + HAL_HASH_MspInit(hhash); + } +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ + + /* Set the key size, data type and Algorithm */ + cr_value = (uint32_t)(hhash->Init.DataType | hhash->Init.Algorithm); + /* Set the key size, data type, algorithm and mode */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_DATATYPE | HASH_CR_ALGO | HASH_CR_INIT, cr_value); + + /* Change HASH phase to Ready */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Change HASH state to Ready */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset error code field */ + hhash->ErrorCode = HAL_HASH_ERROR_NONE; + +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) + /* Reset suspension request flag */ + hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; +#endif /* (USE_HAL_HASH_SUSPEND_RESUME) */ + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the HASH peripheral. + * @param hhash pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) +{ + /* Check the HASH handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Change the default HASH phase */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Reset HashInCount */ + hhash->HashInCount = 0U; + + /* Reset multi buffers accumulation flag */ + hhash->Accumulation = 0U; + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + if (hhash->MspDeInitCallback == NULL) + { + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; + } + + /* DeInit the low level hardware */ + hhash->MspDeInitCallback(hhash); +#else + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_HASH_MspDeInit(hhash); +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ + + /* Set the HASH state to Ready */ + hhash->State = HAL_HASH_STATE_RESET; + + __HAL_UNLOCK(hhash); + + return HAL_OK; +} + +/** + * @brief Configure the HASH according to the specified + * parameters in the HASH_ConfigTypeDef + * @param hhash pointer to a HASH_HandleTypeDef structure + * @param pConf pointer to a HASH_ConfigTypeDef structure that contains + * the configuration information for HASH module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf) +{ + uint32_t cr_value; + + /* Check the HASH handle allocation */ + if ((hhash == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_HASH_DATATYPE(pConf->DataType)); + assert_param(IS_HASH_ALGORITHM(pConf->Algorithm)); + + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + __HAL_LOCK(hhash); + + /* Set HASH parameters */ + hhash->Init.DataType = pConf->DataType; + hhash->Init.pKey = pConf->pKey; + hhash->Init.Algorithm = pConf->Algorithm; + hhash->Init.KeySize = pConf->KeySize; + + /* Set the key size, data type and Algorithm */ + cr_value = (uint32_t)(hhash->Init.DataType | hhash->Init.Algorithm); + /* Set the key size, data type, algorithm and mode */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_DATATYPE | HASH_CR_ALGO | HASH_CR_INIT, cr_value); + + /* Change HASH phase to Ready */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Change HASH state to Ready */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset error code field */ + hhash->ErrorCode = HAL_HASH_ERROR_NONE; + + __HAL_UNLOCK(hhash); + + return HAL_OK; + + } + else + { + /* Busy error code field */ + hhash->ErrorCode |= HAL_HASH_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Get HASH Configuration parameters in associated handle + * @param pConf pointer to a HASH_HandleTypeDef structure + * @param hhash pointer to a HASH_ConfigTypeDef structure that contains + * the configuration information for HASH module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_GetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf) +{ + + /* Check the HASH handle allocation */ + if ((hhash == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + __HAL_LOCK(hhash); + + /* Set HASH parameters */ + pConf->DataType = hhash->Init.DataType; + pConf->pKey = hhash->Init.pKey; + pConf->Algorithm = hhash->Init.Algorithm; + pConf->KeySize = hhash->Init.KeySize; + + /* Change HASH state to Ready */ + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + + return HAL_OK; + + } + else + { + /* Busy error code field */ + hhash->ErrorCode |= HAL_HASH_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Initialize the HASH MSP. + * @param hhash pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module. + * @retval None + */ +__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhash); + + /* NOTE : This function should not be modified; when the callback is needed, + HAL_HASH_MspInit() can be implemented in the user file. + */ +} + +/** + * @brief DeInitialize the HASH MSP. + * @param hhash pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module. + * @retval None + */ +__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhash); + + /* NOTE : This function should not be modified; when the callback is needed, + HAL_HASH_MspDeInit() can be implemented in the user file. + */ +} + + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User HASH Callback + * To be used instead of the weak (overridden) predefined callback + * @param hhash HASH handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg HAL_HASH_INPUTCPLT_CB_ID input completion callback ID + * @arg HAL_HASH_DGSTCPLT_CB_ID digest computation completion callback ID + * @arg HAL_HASH_ERROR_CB_ID error callback ID + * @arg HAL_HASH_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_HASH_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, + pHASH_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hhash->State == HAL_HASH_STATE_READY) + { + switch (CallbackID) + { + case HAL_HASH_INPUTCPLT_CB_ID : + hhash->InCpltCallback = pCallback; + break; + + case HAL_HASH_DGSTCPLT_CB_ID : + hhash->DgstCpltCallback = pCallback; + break; + + case HAL_HASH_ERROR_CB_ID : + hhash->ErrorCallback = pCallback; + break; + + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = pCallback; + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hhash->State == HAL_HASH_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = pCallback; + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a HASH Callback + * HASH Callback is redirected to the weak (overridden) predefined callback + * @param hhash HASH handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID + * @arg HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID + * @arg HAL_HASH_ERROR_CB_ID HASH error Callback ID + * @arg HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID + * @arg HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + + if (hhash->State == HAL_HASH_STATE_READY) + { + switch (CallbackID) + { + case HAL_HASH_INPUTCPLT_CB_ID : + hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak input completion callback */ + break; + + case HAL_HASH_DGSTCPLT_CB_ID : + hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak digest computation + completion callback */ + break; + + case HAL_HASH_ERROR_CB_ID : + hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak error callback */ + break; + + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak MspInit Callback */ + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hhash->State == HAL_HASH_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak MspInit Callback */ + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) +/** + * @brief Save the HASH context in case of processing suspension. + * @param hhash HASH handle. + * @param pMemBuffer pointer to the memory buffer where the HASH context + * is saved. + * @note The IMR, STR, CR then all the CSR registers are saved + * in that order. Only the r/w bits are read to be restored later on. + * @note By default, all the context swap registers (there are + * HASH_NUMBER_OF_CSR_REGISTERS of those) are saved. + * @note pMemBuffer points to a buffer allocated by the user. The buffer size + * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long. + * @retval None + */ +void HAL_HASH_Suspend(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) +{ + uint32_t mem_ptr = (uint32_t)pMemBuffer; + uint32_t csr_ptr = (uint32_t)(hhash->Instance->CSR); + uint32_t i; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhash); + + /* Save IMR register content */ + *(uint32_t *)(mem_ptr) = READ_BIT(hhash->Instance->IMR, HASH_IT_DINI | HASH_IT_DCI); + mem_ptr += 4U; + /* Save STR register content */ + *(uint32_t *)(mem_ptr) = READ_BIT(hhash->Instance->STR, HASH_STR_NBLW); + mem_ptr += 4U; + /* Save CR register content */ + *(uint32_t *)(mem_ptr) = READ_BIT(hhash->Instance->CR, HASH_CR_DMAE | HASH_CR_DATATYPE | HASH_CR_MODE | HASH_CR_ALGO | + HASH_CR_LKEY | HASH_CR_MDMAT); + + mem_ptr += 4U; + /* By default, save all CSRs registers */ + for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--) + { + *(uint32_t *)(mem_ptr) = *(uint32_t *)(csr_ptr); + mem_ptr += 4U; + csr_ptr += 4U; + } + /* Save low-priority block HASH handle parameters */ + hhash->Init_saved = hhash->Init; + hhash->pHashOutBuffPtr_saved = hhash->pHashOutBuffPtr; + hhash->HashInCount_saved = hhash->HashInCount; + hhash->Size_saved = hhash->Size; + hhash->pHashInBuffPtr_saved = hhash->pHashInBuffPtr; + hhash->Phase_saved = hhash->Phase; + hhash->pHashKeyBuffPtr_saved = hhash->pHashKeyBuffPtr; +} + + +/** + * @brief Restore the HASH context in case of processing resumption. + * @param hhash HASH handle. + * @param pMemBuffer pointer to the memory buffer where the HASH context + * is stored. + * @note The IMR, STR, CR then all the CSR registers are restored + * in that order. Only the r/w bits are restored. + * @note By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS + * of those) are restored (all of them have been saved by default + * beforehand). + * @retval None + */ +void HAL_HASH_Resume(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) +{ + uint32_t mem_ptr = (uint32_t)pMemBuffer; + uint32_t csr_ptr = (uint32_t)(hhash->Instance->CSR); + uint32_t i; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhash); + + /* Restore IMR register content */ + WRITE_REG(hhash->Instance->IMR, (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; + /* Restore STR register content */ + WRITE_REG(hhash->Instance->STR, (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; + /* Restore CR register content */ + WRITE_REG(hhash->Instance->CR, (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; + + /* Reset the HASH processor before restoring the Context + Swap Registers (CSR) */ + SET_BIT(hhash->Instance->CR, HASH_CR_INIT); + + + /* By default, restore all CSR registers */ + for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--) + { + WRITE_REG((*(uint32_t *)(csr_ptr)), (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; + csr_ptr += 4U; + } + + /* Restore low-priority block HASH handle parameters */ + hhash->Init = hhash->Init_saved; + hhash->pHashOutBuffPtr = hhash->pHashOutBuffPtr_saved; + hhash->HashInCount = hhash->HashInCount_saved; + hhash->Size = hhash->Size_saved; + hhash->pHashInBuffPtr = hhash->pHashInBuffPtr_saved; + hhash->Phase = hhash->Phase_saved; + hhash->State = HAL_HASH_STATE_SUSPENDED; + hhash->pHashKeyBuffPtr = hhash->pHashKeyBuffPtr_saved; +} + +/** + * @brief Initiate HASH processing suspension when in interruption mode. + * @param hhash HASH handle. + * @note Set the handle field SuspendRequest to the appropriate value so that + * the on-going HASH processing is suspended as soon as the required + * conditions are met. Note that the actual suspension is carried out + * by the functions HASH_WriteData() in polling mode and HASH_IT() in + * interruption mode. + * @retval None + */ +HAL_StatusTypeDef HAL_HASH_ProcessSuspend(HASH_HandleTypeDef *hhash) +{ + uint32_t remainingwords; /*remaining number in of source block to be transferred.*/ + uint32_t nbbytePartialHash = (((hhash->Instance->SR) >> 16U) * 4U); /* Nb byte to enter in HASH fifo + to trig a partial HASH computation*/ + uint32_t sizeinwords;/* number in word of source block to be transferred.*/ + + /* suspension in DMA mode*/ + if (__HAL_HASH_GET_FLAG(hhash, HASH_FLAG_DMAS) != RESET) + { + if (hhash->State == HAL_HASH_STATE_READY) + { + return HAL_ERROR; + } + else + { + + /* Clear the DMAE bit to disable the DMA interface */ + CLEAR_BIT(HASH->CR, HASH_CR_DMAE); + + /* Wait until the last DMA transfer is complete (DMAS = 0 in the HASH_SR register) */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DMAS, SET, HASH_TIMEOUTVALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* At this point, DMA interface is disabled and no transfer is on-going */ + /* Retrieve from the DMA handle how many words remain to be written */ + /* DMA3 used, DMA_CBR1_BNDT in bytes, DMA_CSR_FIFOL in words */ + remainingwords = ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CBR1) \ + & DMA_CBR1_BNDT) / 4U; + remainingwords += ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CSR) \ + & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos; + + if (remainingwords <= nbbytePartialHash) + { + /* No suspension attempted since almost to the end of the transferred data. */ + /* Best option for user code is to wrap up low priority message hashing */ + return HAL_ERROR; + } + + /* Disable DMA channel */ + /* Note that the Abort function will + - Clear the transfer error flags + - Unlock + - Set the State + */ + if (HAL_DMA_Abort(hhash->hdmain) != HAL_OK) + { + return HAL_ERROR; + } + + if (__HAL_HASH_GET_FLAG(hhash, HASH_FLAG_DCIS) != RESET) + { + return HAL_ERROR; + } + + /* Wait until the hash processor is ready (no block is being processed), that is wait for DINIS=1 in HASH_SR */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DINIS, RESET, HASH_TIMEOUTVALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Compute how many words were supposed to be transferred by DMA */ + sizeinwords = (((hhash->Size % 4U) != 0U) ? \ + ((hhash->Size + 3U) / 4U) : (hhash->Size / 4U)); + /* Accordingly, update the input pointer that points at the next word to be + transferred to the Peripheral by DMA */ + hhash->pHashInBuffPtr += 4U * (sizeinwords - remainingwords) ; + + /* And store in HashInCount the remaining size to transfer (in bytes) */ + hhash->HashInCount = 4U * remainingwords; + + + hhash->State = HAL_HASH_STATE_SUSPENDED; + __HAL_UNLOCK(hhash); + return HAL_OK; + } + + } + else /* suspension when in interruption mode*/ + { + /* Set Handle Suspend Request field */ + hhash->SuspendRequest = HAL_HASH_SUSPEND; + return HAL_OK; + } +} +#endif /* USE_HAL_HASH_SUSPEND_RESUME */ +/** + * @} + */ + + +/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions + * @brief HASH processing functions using different mode. + * +@verbatim + =============================================================================== + ##### HASH processing functions ##### + =============================================================================== + [..] This section provides API allowing to calculate the hash value using + one of the HASH algorithms supported by the peripheral. + + [..] For a single buffer to be hashed, user can resort to one of three processing + functions available . + (+) Polling mode : HAL_HASH_Start() + (+) Interrupt mode : HAL_HASH_Start_IT() + (+) DMA mode : HAL_HASH_Start_DMA() + + [..] In case of multi-buffer HASH processing (a single digest is computed while + several buffers are fed to the Peripheral), the user can resort to successive calls + to : + (+) Polling mode : HAL_HASH_Accumulate() and wrap-up the digest computation by a call + to HAL_HASH_AccumulateLast() + (+) Interrupt mode : HAL_HASH_Accumulate_IT() and wrap-up the digest computation by a call + to HAL_HASH_AccumulateLast_IT() + (+) DMA mode : HAL_HASH_Start_DMA(), MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro, + before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() + macro then wrap-up the HASH processing in feeding the last input buffer through the + same API HAL_HASH_Start_DMA() + +@endverbatim + * @{ + */ + +/** + * @brief HASH peripheral processes in polling mode pInBuffer then reads the computed digest. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @param Timeout specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, uint32_t Timeout) +{ + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->HashInCount = 0U; + hhash->Size = Size; + + /* Set HASH mode */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE); + /* Reset the HASH processor core */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT); + + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U)); + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + + HASH_WriteData(hhash, pInBuffer, Size); + + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for digest calculation completion status(DCIS) flag to be set */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read the message digest */ + HASH_GetDigest(hhash, pOutBuffer, HASH_DIGEST_LENGTH(hhash)); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief HASH peripheral processes in interrupt mode pInBuffer then reads the computed digest. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer) +{ + HAL_StatusTypeDef status; + HAL_HASH_StateTypeDef temp_state; + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process or suspended */ + temp_state = hhash->State; + if ((temp_state == HAL_HASH_STATE_READY) || (temp_state == HAL_HASH_STATE_SUSPENDED)) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->HashInCount = 0U; + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->Size = Size; + + /* Set HASH mode */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE); + /* Reset the HASH processor core */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT); + + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U)); + } + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + + /* Enable the specified HASH interrupt*/ + __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + status = HASH_WriteData_IT(hhash); + } + else + { + status = HAL_BUSY; + } + /* Return function status */ + return status; +} + +/** + * @brief HASH peripheral processes in DMA mode pInBuffer then reads the computed digest. + * @note Multi-buffer HASH processing is possible, consecutive calls to HAL_HASH_Start_DMA + * (MDMAT bit must be set) can be used to feed several input buffers + * back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_Start_DMA (MDMAT bit must be reset). + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes (must be a multiple of 4 in + * case of Multi-buffer and not last buffer). + * @param pOutBuffer pointer to the computed digest. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer) +{ + HAL_StatusTypeDef status; + HAL_HASH_StateTypeDef temp_state; + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process or suspended */ + temp_state = hhash->State; + if ((temp_state == HAL_HASH_STATE_READY) || (temp_state == HAL_HASH_STATE_SUSPENDED)) + { + + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Check if initialization phase has not been already performed */ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->HashInCount = 0U; + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->HashInCount = 0U; + hhash->Size = Size; + + /* Check if initialization phase has already been performed. + If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the + API is processing a new input data message in case of multi-buffer HASH + computation. */ + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Set HASH mode */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE); + /* Reset the HASH processor core */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT); + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + /* Configure the number of valid bits in last word of the message */ + if ((hhash->Instance->CR & HASH_CR_MDMAT) == 0U) + { + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Size) % 4U)); + } + else + { + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 0U); + } + + } + else /* HAL_HASH_STATE_SUSPENDED */ + { + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + /*only part not yet hashed to compute */ + hhash->Size = hhash->HashInCount; + } + /* Set the HASH DMA transfer complete callback */ + hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; + /* Set the DMA error callback */ + hhash->hdmain->XferErrorCallback = HASH_DMAError; + + if ((hhash->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hhash->hdmain->LinkedListQueue != NULL) && (hhash->hdmain->LinkedListQueue->Head != NULL)) + { + /* Enable the DMA channel */ + hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET]\ + = ((((hhash->Size) % 4U) != 0U) ? ((hhash->Size) + (4U - ((hhash->Size) % 4U))) : (hhash->Size)); + hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]\ + = (uint32_t)(hhash->pHashInBuffPtr); /* Set DMA source address */ + hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]\ + = (uint32_t)&hhash->Instance->DIN; /* Set DMA destination address */ + + status = HAL_DMAEx_List_Start_IT(hhash->hdmain); + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hhash->hdmain, (uint32_t)pInBuffer, (uint32_t)&hhash->Instance->DIN, \ + ((((hhash->Size) % 4U) != 0U) ? ((hhash->Size) + (4U - ((hhash->Size) % 4U))) : \ + (hhash->Size))); + } + if (status != HAL_OK) + { + /* DMA error code field */ + hhash->ErrorCode |= HAL_HASH_ERROR_DMA; + + /* Return error */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hhash->ErrorCallback(hhash); +#else + /*Call legacy weak error callback*/ + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + else + { + /* Enable DMA requests */ + SET_BIT(hhash->Instance->CR, HASH_CR_DMAE); + } + } + else + { + status = HAL_BUSY; + + } + + /* Return function status */ + return status; +} + + +/** + * @brief HASH peripheral processes in polling mode several input buffers. + * @note Consecutive calls to HAL_HASH_Accumulate() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_AccumulateLast() + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes and a multiple of 4. + * @param Timeout specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Timeout) +{ + HAL_HASH_StateTypeDef temp_state; + + /* Check the hash handle allocation and buffer length multiple of 4 */ + if ((hhash == NULL) || ((Size % 4U) != 0U)) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process or suspended */ + temp_state = hhash->State; + if ((temp_state == HAL_HASH_STATE_READY) || (temp_state == HAL_HASH_STATE_SUSPENDED)) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->HashInCount = 0U; + hhash->Size = Size; + + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Set HASH mode */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE); + /* Reset the HASH processor core */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT); + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + HASH_WriteData(hhash, pInBuffer, Size); + + /* Wait for BUSY flag to be cleared */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief End computation of a single HASH signature after several calls to HAL_HASH_Accumulate() API. + * @note Digest is available in pOutBuffer + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @param Timeout specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, uint32_t Timeout) +{ + HAL_HASH_StateTypeDef temp_state; + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process or suspended */ + temp_state = hhash->State; + if ((temp_state == HAL_HASH_STATE_READY) || (temp_state == HAL_HASH_STATE_SUSPENDED)) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->HashInCount = 0U; + hhash->Size = Size; + + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Set HASH mode */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE); + /* Reset the HASH processor core */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT); + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U)); + + + HASH_WriteData(hhash, pInBuffer, Size); + + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for digest calculation completion status(DCIS) flag to be set */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Read the message digest */ + HASH_GetDigest(hhash, pOutBuffer, HASH_DIGEST_LENGTH(hhash)); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + hhash->Accumulation = 0; + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief HASH peripheral processes in interrupt mode several input buffers. + * @note Consecutive calls to HAL_HASH_Accumulate_IT() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_AccumulateLast_IT() + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes and a multiple of 4. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) +{ + HAL_StatusTypeDef status; + + /* Check the hash handle allocation */ + if ((hhash == NULL) || ((Size % 4U) != 0U)) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size and pHashInBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->HashInCount = 0U; + hhash->Size = Size; + /* Set multi buffers accumulation flag */ + hhash->Accumulation = 1U; + + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Set HASH mode */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE); + /* Reset the HASH processor core */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT); + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + /* Enable the specified HASH interrupt*/ + __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI); + + status = HASH_WriteData_IT(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + } + else + { + status = HAL_BUSY; + } + /* Return function status */ + return status; +} + + +/** + * @brief End computation of a single HASH signature after several calls to HAL_HASH_Accumulate_IT() API. + * @note Digest is available in pOutBuffer + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer) +{ + HAL_StatusTypeDef status; + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->HashInCount = 0U; + hhash->Size = Size; + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Set HASH mode */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE); + /* Reset the HASH processor core */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT); + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U)); + + /* Enable the specified HASH interrupt*/ + __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + status = HASH_WriteData_IT(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + } + else + { + status = HAL_BUSY; + } + /* Return function status */ + return status; +} + +/** + * @} + */ + + +/** @defgroup HASH_Exported_Functions_Group3 HMAC processing functions + * @brief HMAC processing functions using different mode. + * +@verbatim + =============================================================================== + ##### HMAC processing functions ##### + =============================================================================== + [..] This section provides API allowing to calculate the HMAC (keyed-hash + message authentication code) value using: + (+) one of the algorithms supported by the peripheral + (+) Key selection + (++) Long key : HMAC key is longer than the block size + (++) Short key : HMAC key is shorter or equal to the block size + + [..] To calculate the HMAC for a single buffer, user can resort to one of three processing + functions available . + (+) Polling mode : HAL_HASH_HMAC_Start() + (+) Interrupt mode : HAL_HASH_HMAC_Start_IT() + (+) DMA mode : HAL_HASH_HMAC_Start_DMA() + + [..] In case of multi-buffer HMAC processing (a single digest is computed while + several buffers are fed to the Peripheral), the user can resort to successive calls + to : + (+) Polling mode : HAL_HASH_HMAC_Accumulate() and wrap-up the digest computation by a call + to HAL_HASH_HMAC_AccumulateLast() + (+) Interrupt mode : HAL_HASH_HMAC_Accumulate_IT() and wrap-up the digest computation by a call + to HAL_HASH_HMAC_AccumulateLast_IT() + (+) DMA mode : HAL_HASH_HMAC_Start_DMA(),MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro, + before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() + macro then wrap-up the HMAC processing in feeding the last input buffer through the + same API HAL_HASH_HMAC_Start_DMA() + +@endverbatim + * @{ + */ + +/** + * @brief HMAC in polling mode, HASH peripheral processes Key then pInBuffer then reads the computed digest. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @param Timeout specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, uint32_t Timeout) +{ + uint32_t blocksize; /* Block size in bytes */ + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HASH Phase */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Reset HashInCount and Initialize Size, pHashKeyBuffPtr, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + hhash->HashInCount = 0U; + hhash->Size = Size; + + /* Check if key size is larger than block size of the algorithm, accordingly set LKEY and the other setting bits */ + if ((hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA1) || + (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA224) || + (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA256)) + { + blocksize = BLOCK_64B; + } + else + { + blocksize = BLOCK_128B; + } + if (hhash->Init.KeySize > blocksize) + { + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_LONGKEY | HASH_CR_INIT); + } + else + { + + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_CR_INIT); + } + + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + /* Write Key */ + HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize); + + /* Start the Key padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for BUSY flag to be cleared */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U)); + + /* Write message */ + HASH_WriteData(hhash, pInBuffer, Size); + + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for BUSY flag to be cleared */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + /* Write Key */ + HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize); + + /* Start the Key padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for digest calculation completion status(DCIS) flag to be set */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read the message digest */ + HASH_GetDigest(hhash, pOutBuffer, HASH_DIGEST_LENGTH(hhash)); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Change the HASH phase */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + /* Return function status */ + return HAL_OK; + + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief HMAC accumulate mode, HASH peripheral processes Key then several input buffers. + * @note Consecutive calls to HAL_HASH_HMAC_Accumulate() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_HMAC_AccumulateLast() + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes and a multiple of 4 + * @param Timeout specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Timeout) +{ + uint32_t blocksize; /* Block size in bytes */ + + /* Check the hash handle allocation and buffer length multiple of 4 */ + if ((hhash == NULL) || ((Size % 4U) != 0U)) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Initialize Size, pHashInBuffPtr and pHashKeyBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + hhash->Size = Size; + + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Reset HashInCount parameter */ + hhash->HashInCount = 0U; + /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */ + /* Check if key size is larger than block size of the algorithm, accordingly set LKEY and the other setting */ + if ((hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA1) || + (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA224) || + (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA256)) + { + blocksize = BLOCK_64B; + } + else + { + blocksize = BLOCK_128B; + } + if (hhash->Init.KeySize > blocksize) + { + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_LONGKEY | HASH_CR_INIT); + } + else + { + + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_CR_INIT); + } + /* Set phase process */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + /* Write Key */ + HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize); + + /* Start the Key padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for BUSY flag to be cleared */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* Change the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 0U); + + /* Write message */ + HASH_WriteData(hhash, pInBuffer, Size); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + /* Return function status */ + return HAL_OK; + + } + else + { + return HAL_BUSY; + } +} +/** + * @brief End computation of a single HMAC signature after several calls to HAL_HASH_HMAC_Accumulate() API. + * @note Digest is available in pOutBuffer + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @param Timeout specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, uint32_t Timeout) +{ + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Initialize Size, pHashInBuffPtr, pHashKeyBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + hhash->Size = Size; + + if (hhash->Phase != HAL_HASH_PHASE_PROCESS) + { + return HAL_ERROR; + } + else + { + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U)); + + /* Write message */ + HASH_WriteData(hhash, pInBuffer, Size); + + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for BUSY flag to be cleared */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + /* Write Key */ + HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize); + + /* Start the Key padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for digest calculation completion status(DCIS) flag to be set */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read the message digest */ + HASH_GetDigest(hhash, pOutBuffer, HASH_DIGEST_LENGTH(hhash)); + } + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief HMAC in interrupt mode, HASH peripheral process Key then pInBuffer then read the computed digest. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer) +{ + HAL_StatusTypeDef status; + uint32_t blocksize; /* Block size in bytes */ + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HASH Phase */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Reset HashInCount and Initialize Size, pHashKeyBuffPtr, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + hhash->HashInCount = 0U; + hhash->Size = Size; + + /* Check if key size is larger than block size of the algorithm, accordingly set LKEY and the other setting bits */ + if ((hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA1) || + (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA224) || + (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA256)) + { + blocksize = BLOCK_64B; + } + else + { + blocksize = BLOCK_128B; + } + if (hhash->Init.KeySize > blocksize) + { + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_LONGKEY | HASH_CR_INIT); + } + else + { + + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_CR_INIT); + } + + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + else if (hhash->State == HAL_HASH_STATE_SUSPENDED) + { + /* Process Locked */ + __HAL_LOCK(hhash); + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + } + else + { + return HAL_BUSY; + } + + /* Enable the specified HASH interrupt*/ + __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + status = HASH_WriteData_IT(hhash); + + /* Return function status */ + return status; +} + +/** + * @brief HMAC accumulate in interrupt mode, HASH peripheral processes Key then several input buffers. + * @note Consecutive calls to HAL_HASH_HMAC_Accumulate_IT() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_HMAC_AccumulateLast_IT() + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes and a multiple of 4. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) +{ + HAL_StatusTypeDef status; + uint32_t blocksize; /* Block size in bytes */ + + /* Check the hash handle allocation and buffer length multiple of 4 */ + if ((hhash == NULL) || ((Size % 4U) != 0U)) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + hhash->HashInCount = 0U; + hhash->Size = Size; + /* Set multi buffers accumulation flag */ + hhash->Accumulation = 1U; + + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Check if key size is larger than block size of the algorithm, accordingly set LKEY and the other setting */ + if ((hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA1) || + (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA224) || + (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA256)) + { + blocksize = BLOCK_64B; + } + else + { + blocksize = BLOCK_128B; + } + if (hhash->Init.KeySize > blocksize) + { + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_LONGKEY | HASH_CR_INIT); + } + else + { + + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_CR_INIT); + } + + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + /* Enable the specified HASH interrupt*/ + __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + status = HASH_WriteData_IT(hhash); + } + else + { + status = HAL_BUSY; + } + /* Return function status */ + return status; +} +/** + * @brief End computation of a single HMAC signature in interrupt mode, after + * several calls to HAL_HASH_HMAC_Accumulate() API. + * @note Digest is available in pOutBuffer + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *const pOutBuffer) +{ + HAL_StatusTypeDef status; + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process*/ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + hhash->HashInCount = 0U; + hhash->Size = Size; + /* Set multi buffers accumulation flag */ + hhash->Accumulation = 0U; + /* Enable the specified HASH interrupt*/ + __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + status = HASH_WriteData_IT(hhash); + } + else + { + status = HAL_BUSY; + } + /* Return function status */ + return status; +} + +/** + * @brief HMAC in DMA mode,HASH peripheral processes Key then pInBuffer in DMA mode + * then read the computed digest. + * @note Multi-buffer HMAC processing is possible, consecutive calls to HAL_HASH_HMAC_Start_DMA + * (MDMAT bit must be set) can be used to feed several input buffers + * back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_HMAC_Start_DMA (MDMAT bit must be reset). + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer) +{ + HAL_StatusTypeDef status; + uint32_t count; + uint32_t blocksize; /* Block size in bytes */ + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process*/ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + hhash->HashInCount = 0U; + hhash->Size = Size; + + /* Set the phase */ + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Check if key size is larger than block size of the algorithm, accordingly set LKEY and the other setting */ + if ((hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA1) || + (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA224) || + (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA256)) + { + blocksize = BLOCK_64B; + } + else + { + blocksize = BLOCK_128B; + } + if (hhash->Init.KeySize > blocksize) + { + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_LONGKEY | HASH_CR_INIT); + } + else + { + + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_CR_INIT); + } + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; + + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + /* Write Key */ + HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize); + + /* Start the Key padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for DCIS flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_BUSY)); + } + + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; + if ((hhash->Instance->CR & HASH_CR_MDMAT) == 0U) + { + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Size) % 4U)); + } + else + { + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 0U); + } + } + else if (hhash->State == HAL_HASH_STATE_SUSPENDED) + { + /* Process Locked */ + __HAL_LOCK(hhash); + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /*only part not yet hashed to compute */ + hhash->Size = hhash->HashInCount; + } + + else + { + /* Return busy status */ + return HAL_BUSY; + } + + /* Set the HASH DMA transfer complete callback */ + hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; + /* Set the DMA error callback */ + hhash->hdmain->XferErrorCallback = HASH_DMAError; + + if ((hhash->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hhash->hdmain->LinkedListQueue != NULL) && (hhash->hdmain->LinkedListQueue->Head != NULL)) + { + /* Enable the DMA channel */ + hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET]\ + = ((((hhash->Size) % 4U) != 0U) ? ((hhash->Size) + (4U - ((hhash->Size) % 4U))) : ((hhash->Size))); + hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]\ + = (uint32_t)(hhash->pHashInBuffPtr); /* Set DMA source address */ + hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]\ + = (uint32_t)&hhash->Instance->DIN; /* Set DMA destination address */ + + status = HAL_DMAEx_List_Start_IT(hhash->hdmain); + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hhash->hdmain, (uint32_t)(hhash->pHashInBuffPtr), (uint32_t)&hhash->Instance->DIN, \ + ((((hhash->Size) % 4U) != 0U) ? ((hhash->Size) + (4U - ((hhash->Size) % 4U))) : \ + ((hhash->Size)))); + } + if (status != HAL_OK) + { + /* DMA error code field */ + hhash->ErrorCode |= HAL_HASH_ERROR_DMA; + + /* Return error */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hhash->ErrorCallback(hhash); +#else + /*Call legacy weak error callback*/ + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + else + { + /* Enable DMA requests */ + SET_BIT(hhash->Instance->CR, HASH_CR_DMAE); + } + + /* Return function status */ + return status; +} + + +/** + * @} + */ + +/** @defgroup HASH_Exported_Functions_Group4 HASH IRQ handler management + * @brief HASH IRQ handler. + * +@verbatim + ============================================================================== + ##### HASH IRQ handler management ##### + ============================================================================== +[..] This section provides HASH IRQ handler and callback functions. + (+) HAL_HASH_IRQHandler HASH interrupt request + (+) HAL_HASH_InCpltCallback input data transfer complete callback + (+) HAL_HASH_DgstCpltCallback digest computation complete callback + (+) HAL_HASH_ErrorCallback HASH error callback + (+) HAL_HASH_GetState return the HASH state + (+) HAL_HASH_GetError return the HASH error code +@endverbatim + * @{ + */ + +/** + * @brief Handle HASH interrupt request. + * @param hhash HASH handle. + * @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well. + * @retval None + */ +void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) +{ + HAL_StatusTypeDef status; + uint32_t itsource = hhash->Instance->IMR; + uint32_t itflag = hhash->Instance->SR; + + /* If digest is ready */ + if ((itflag & HASH_FLAG_DCIS) == HASH_FLAG_DCIS) + { + /* Read the digest */ + HASH_GetDigest(hhash, hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH(hhash)); + + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + /* Call digest computation complete call back */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->DgstCpltCallback(hhash); +#else + HAL_HASH_DgstCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + + } + /* If Peripheral ready to accept new data */ + if ((itflag & HASH_FLAG_DINIS) == HASH_FLAG_DINIS) + { + if ((itsource & HASH_IT_DINI) == HASH_IT_DINI) + { + status = HASH_WriteData_IT(hhash); + if (status != HAL_OK) + { + /* Call error callback */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->ErrorCallback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + } + } +} + +/** + * @brief Input data transfer complete call back. + * @note HAL_HASH_InCpltCallback() is called when the complete input message + * has been fed to the Peripheral. This API is invoked only when input data are + * entered under interruption or through DMA. + * @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set), + * HAL_HASH_InCpltCallback() is called at the end of each buffer feeding + * to the Peripheral. + * @param hhash pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module. + * @retval None + */ +__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhash); + + /* NOTE : This function should not be modified; when the callback is needed, + HAL_HASH_InCpltCallback() can be implemented in the user file. + */ +} + +/** + * @brief Digest computation complete call back. + * @note HAL_HASH_DgstCpltCallback() is used under interruption, is not + * relevant with DMA. + * @param hhash pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module. + * @retval None + */ +__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhash); + + /* NOTE : This function should not be modified; when the callback is needed, + HAL_HASH_DgstCpltCallback() can be implemented in the user file. + */ +} + +/** + * @brief HASH error callback. + * @note Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...) + * to retrieve the error type. + * @param hhash pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module. + * @retval None + */ +__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhash); + + /* NOTE : This function should not be modified; when the callback is needed, + HAL_HASH_ErrorCallback() can be implemented in the user file. + */ +} + +/** + * @brief Return the HASH handle state. + * @note The API yields the current state of the handle (BUSY, READY,...). + * @param hhash HASH handle. + * @retval HAL HASH state + */ +HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash) +{ + return hhash->State; +} + +/** + * @brief Return the HASH handle error code. + * @param hhash pointer to a HASH_HandleTypeDef structure. + * @retval HASH Error Code + */ +uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash) +{ + /* Return HASH Error Code */ + return hhash->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup HASH_Private_Functions + * @{ + */ + +/** + * @brief DMA HASH Input Data transfer completion callback. + * @param hdma DMA handle. + * @retval None + */ +static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) +{ + HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + uint32_t count; + + if (READ_BIT(hhash->Instance->CR, HASH_CR_MODE) == 0U) + { + if ((hhash->Instance->CR & HASH_CR_MDMAT) == 0U) + { + /* Disable the DMA transfer */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_DMAE); + + + /* Wait for DCIS flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->ErrorCallback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DCIS)); + /* Call Input data transfer complete call back */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->InCpltCallback(hhash); +#else + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + + /* Read the message digest */ + HASH_GetDigest(hhash, hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH(hhash)); + + /* Change the HASH state to ready */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Process UnLock */ + __HAL_UNLOCK(hhash); + + /* Call digest complete call back */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->DgstCpltCallback(hhash); +#else + HAL_HASH_DgstCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + else + { + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + } + } + else /*HMAC DMA*/ + { + if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) + { + if ((hhash->Instance->CR & HASH_CR_MDMAT) == 0U) + { + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + /* Write Key */ + HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize); + + /* Start the Key padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for DCIS flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable the DMA transfer */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_DMAE); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_DMA; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->ErrorCallback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DCIS)); + + /* Read the message digest */ + HASH_GetDigest(hhash, hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH(hhash)); + + /* Change the HASH state to ready */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Process UnLock */ + __HAL_UNLOCK(hhash); + + /* Call digest complete call back */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->DgstCpltCallback(hhash); +#else + HAL_HASH_DgstCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + + } + else + { + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + hhash->Accumulation = 1; + } + } + } +} + +/** + * @brief DMA HASH communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void HASH_DMAError(DMA_HandleTypeDef *hdma) +{ + HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hhash->ErrorCode |= HAL_HASH_ERROR_DMA; + /* Set HASH state to ready to prevent any blocking issue in user code + present in HAL_HASH_ErrorCallback() */ + hhash->State = HAL_HASH_STATE_READY; + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->ErrorCallback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ +} + +/** + * @brief Feed the input buffer to the HASH peripheral in polling. + * @param hhash HASH handle. + * @param pInBuffer pointer to input buffer. + * @param Size the size of input buffer in bytes. + * @retval HAL status + */ +static void HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *pInBuffer, uint32_t Size) +{ + uint32_t buffercounter; + __IO uint32_t inputaddr = (uint32_t) pInBuffer; + uint8_t tmp1; + uint8_t tmp2; + uint8_t tmp3; + + for (buffercounter = 0U; buffercounter < (Size / 4U) ; buffercounter++) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + hhash->HashInCount += 4U; + } + + if ((Size % 4U) != 0U) + { + if (hhash->Init.DataType == HASH_HALFWORD_SWAP) + { + /* Write remaining input data */ + if ((Size % 4U) <= 2U) + { + hhash->Instance->DIN = (uint32_t) * (uint16_t *)inputaddr; + } + if ((Size % 4U) == 3U) + { + hhash->Instance->DIN = *(uint32_t *)inputaddr; + } + } + else if ((hhash->Init.DataType == HASH_BYTE_SWAP) + || (hhash->Init.DataType == HASH_BIT_SWAP)) /* byte swap or bit swap or */ + { + /* Write remaining input data */ + if ((Size % 4U) == 1U) + { + hhash->Instance->DIN = (uint32_t) * (uint8_t *)inputaddr; + } + if ((Size % 4U) == 2U) + { + hhash->Instance->DIN = (uint32_t) * (uint16_t *)inputaddr; + } + if ((Size % 4U) == 3U) + { + tmp1 = *(uint8_t *)inputaddr; + tmp2 = *(((uint8_t *)inputaddr) + 1U); + tmp3 = *(((uint8_t *)inputaddr) + 2U); + hhash->Instance->DIN = ((uint32_t)tmp1) | ((uint32_t)tmp2 << 8U) | ((uint32_t)tmp3 << 16U); + } + } + else + { + hhash->Instance->DIN = *(uint32_t *)inputaddr; + } + hhash->HashInCount += 4U; + } +} + +/** + * @brief Feed the input buffer to the HASH peripheral in interruption mode. + * @param hhash HASH handle. + * @retval HAL status + */ +static HAL_StatusTypeDef HASH_WriteData_IT(HASH_HandleTypeDef *hhash) +{ + uint32_t buffercounter; + uint32_t count; + __IO uint32_t keyaddr = (uint32_t)(hhash->pHashKeyBuffPtr); + __IO uint32_t inputaddr = (uint32_t)(hhash->pHashInBuffPtr); + uint32_t nbbytePartialHash = (((hhash->Instance->SR) >> 16U) * 4U); /* Nb byte to enter in HASH fifo to trig + a partial HASH computation*/ + + if (hhash->State == HAL_HASH_STATE_BUSY) + { + if ((hhash->Instance->CR & HASH_CR_MODE) == 0U) + { +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) + /* If suspension flag has been raised, suspend processing */ + if (hhash->SuspendRequest == HAL_HASH_SUSPEND) + { + /* reset SuspendRequest */ + hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_SUSPENDED; + __HAL_UNLOCK(hhash); + } + else + { +#endif /* USE_HAL_HASH_SUSPEND_RESUME */ + + if (((hhash->HashInCount) + nbbytePartialHash) < (hhash->Size)) + { + for (buffercounter = 0U; buffercounter < nbbytePartialHash ; buffercounter += 4U) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + hhash->HashInCount += 4U; + hhash->pHashInBuffPtr += 4U; + } + /* Wait for HASH_IT_DINI flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DINIS)); + } + else + { + while ((hhash->HashInCount) < hhash->Size) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + hhash->HashInCount += 4U; + hhash->pHashInBuffPtr += 4U; + } + /* Call Input transfer complete callback */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hhash->InCpltCallback(hhash); +#else + /*Call legacy weak Input complete callback*/ + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + if (hhash->Accumulation == 0U) + { + if (__HAL_HASH_GET_IT_SOURCE(hhash, HASH_IT_DINI)) + { + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for HASH_FLAG_DCIS flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DCIS)); + } + } + else + { + /* Reset multi buffers accumulation flag */ + hhash->Accumulation = 0U; + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI); + } + } +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) + } +#endif /* USE_HAL_HASH_SUSPEND_RESUME */ + } + else /*HMAC */ + { + if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) /* loading input*/ + { +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) + /* If suspension flag has been raised, suspend processing */ + if (hhash->SuspendRequest == HAL_HASH_SUSPEND) + { + /* reset SuspendRequest */ + hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_SUSPENDED; + __HAL_UNLOCK(hhash); + } + else + { +#endif /* USE_HAL_HASH_SUSPEND_RESUME */ + if (hhash->Accumulation == 1U) + { + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 0U); + } + else + { + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (hhash->Size % 4U)); + } + if (((hhash->HashInCount) + nbbytePartialHash) < (hhash->Size)) + { + for (buffercounter = 0U; buffercounter < nbbytePartialHash ; buffercounter += 4U) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + hhash->HashInCount += 4U; + hhash->pHashInBuffPtr += 4U; + } + /* Wait for HASH_IT_DINI flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DINIS)); + } + else + { + while ((hhash->HashInCount) < hhash->Size) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + hhash->HashInCount += 4U; + hhash->pHashInBuffPtr += 4U; + } + /* Call Input transfer complete callback */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hhash->InCpltCallback(hhash); +#else + /*Call legacy weak Input complete callback*/ + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + + if (hhash->Accumulation == 0U) + { + if (__HAL_HASH_GET_IT_SOURCE(hhash, HASH_IT_DINI)) + { + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for HASH_FLAG_BUSY flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(hhash->Instance->SR, HASH_FLAG_BUSY)); + + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; + hhash->HashInCount = 0U; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + } + } + + else + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_OK; + } + } +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) + } +#endif /* USE_HAL_HASH_SUSPEND_RESUME */ + } + + else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)/* loading Key*/ + { + + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + if (((hhash->HashInCount) + nbbytePartialHash) < (hhash->Init.KeySize)) + { + for (buffercounter = 0U; buffercounter < nbbytePartialHash ; buffercounter += 4U) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)keyaddr; + keyaddr += 4U; + hhash->HashInCount += 4U; + hhash->pHashKeyBuffPtr += 4U; + } + /* Wait for HASH_IT_DINI flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DINIS)); + } + else + { + while ((hhash->HashInCount) < (hhash->Init.KeySize)) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)keyaddr; + keyaddr += 4U; + hhash->HashInCount += 4U; + } + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for HASH_FLAG_DCIS flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DCIS)); + } + } + else /*first step , loading key*/ + { + + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; + + if (((hhash->HashInCount) + nbbytePartialHash) < (hhash->Init.KeySize)) + { + for (buffercounter = 0U; buffercounter < nbbytePartialHash ; buffercounter += 4U) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)keyaddr; + keyaddr += 4U; + hhash->HashInCount += 4U; + hhash->pHashKeyBuffPtr += 4U; + } + /* Wait for HASH_IT_DINI flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DINIS)); + } + else + { + while ((hhash->HashInCount) < (hhash->Init.KeySize)) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)keyaddr; + keyaddr += 4U; + hhash->HashInCount += 4U; + hhash->pHashKeyBuffPtr += 4U; + } + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for HASH_FLAG_BUSY flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(hhash->Instance->SR, HASH_FLAG_BUSY)); + /*change Phase to step 2*/ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; + hhash->HashInCount = 0U; + } + } + } + } + else if ((hhash->State == HAL_HASH_STATE_SUSPENDED)) + { + return HAL_OK; + } + else + { + /* Busy error code field */ + hhash->ErrorCode |= HAL_HASH_ERROR_BUSY; +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hhash->ErrorCallback(hhash); +#else + /*Call legacy weak error callback*/ + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Retrieve the message digest. + * @param hhash HASH handle + * @param pMsgDigest pointer to the computed digest. + * @param Size message digest size in bytes. + * @retval None + */ +static void HASH_GetDigest(const HASH_HandleTypeDef *hhash, const uint8_t *pMsgDigest, uint8_t Size) +{ + uint32_t msgdigest = (uint32_t)pMsgDigest; + + switch (Size) + { + case 20: /* SHA1 */ + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[3]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[4]); + break; + + case 28: /* SHA224 */ + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[3]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[4]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]); + + break; + case 32: /* SHA256 */ + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[3]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[4]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[7]); + break; + case 48: /* SHA384 */ + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[3]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[4]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[7]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[8]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[9]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[10]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[11]); + break; + + case 64: /* SHA 512 */ + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[3]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[4]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[7]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[8]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[9]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[10]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[11]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[12]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[13]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[14]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[15]); + + break; + default: + break; + } +} + +/** + * @brief Handle HASH processing Timeout. + * @param hhash HASH handle. + * @param Flag specifies the HASH flag to check. + * @param Status the Flag status (SET or RESET). + * @param Timeout Timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, + uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if (Status == RESET) + { + while (__HAL_HASH_GET_FLAG(hhash, Flag) == RESET) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Set State to Ready to be able to restart later on */ + hhash->State = HAL_HASH_STATE_READY; + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } + } + } + else + { + while (__HAL_HASH_GET_FLAG(hhash, Flag) != RESET) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Set State to Ready to be able to restart later on */ + hhash->State = HAL_HASH_STATE_READY; + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @} + */ + + +#endif /* HAL_HASH_MODULE_ENABLED */ + +#endif /* HASH*/ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_hcd.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_hcd.c new file mode 100644 index 00000000000..50bd50fdc78 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_hcd.c @@ -0,0 +1,1985 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_hcd.c + * @author MCD Application Team + * @brief HCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Declare a HCD_HandleTypeDef handle structure, for example: + HCD_HandleTypeDef hhcd; + + (#)Fill parameters of Init structure in HCD handle + + (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) + + (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API: + (##) Enable the HCD/USB Low Level interface clock using the following macros + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) + + (##) Initialize the related GPIO clocks + (##) Configure HCD pin-out + (##) Configure HCD NVIC interrupt + + (#)Associate the Upper USB Host stack to the HAL HCD Driver: + (##) hhcd.pData = phost; + + (#)Enable HCD transmission and reception: + (##) HAL_HCD_Start(); + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#ifdef HAL_HCD_MODULE_ENABLED +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + +/** @defgroup HCD HCD + * @brief HCD HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup HCD_Private_Functions HCD Private Functions + * @{ + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd); +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HCD_Exported_Functions HCD Exported Functions + * @{ + */ + +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) +{ +#if defined (USB_OTG_FS) + const USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ + + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); + +#if defined (USB_OTG_FS) + USBx = hhcd->Instance; +#endif /* defined (USB_OTG_FS) */ + + if (hhcd->State == HAL_HCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhcd->Lock = HAL_UNLOCKED; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; + + if (hhcd->MspInitCallback == NULL) + { + hhcd->MspInitCallback = HAL_HCD_MspInit; + } + + /* Init the low level hardware */ + hhcd->MspInitCallback(hhcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_HCD_MspInit(hhcd); +#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */ + } + + hhcd->State = HAL_HCD_STATE_BUSY; + +#if defined (USB_OTG_FS) + /* Disable DMA mode for FS instance */ + if (USBx == USB_OTG_FS) + { + hhcd->Init.dma_enable = 0U; + } +#endif /* defined (USB_OTG_FS) */ + + /* Disable the Interrupts */ + __HAL_HCD_DISABLE(hhcd); + + /* Init the Core (common init.) */ + if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Force Host Mode */ + if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Init Host */ + if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } + + hhcd->State = HAL_HCD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initialize a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number. + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed. + * This parameter can be one of these values: + * HCD_DEVICE_SPEED_HIGH: High speed mode, + * HCD_DEVICE_SPEED_FULL: Full speed mode, + * HCD_DEVICE_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type, + * EP_TYPE_ISOC: Isochronous type, + * EP_TYPE_BULK: Bulk type, + * EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size. + * This parameter can be a value from 0 to32K + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef status; + uint32_t HostCoreSpeed; + uint32_t HCcharMps = mps; + + __HAL_LOCK(hhcd); + hhcd->hc[ch_num].do_ping = 0U; + hhcd->hc[ch_num].dev_addr = dev_address; + hhcd->hc[ch_num].ch_num = ch_num; + hhcd->hc[ch_num].ep_type = ep_type; + hhcd->hc[ch_num].ep_num = epnum & 0x7FU; + + (void)HAL_HCD_HC_ClearHubInfo(hhcd, ch_num); + + if ((epnum & 0x80U) == 0x80U) + { + hhcd->hc[ch_num].ep_is_in = 1U; + } + else + { + hhcd->hc[ch_num].ep_is_in = 0U; + } + + HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance); + + if (ep_type == EP_TYPE_ISOC) + { + /* FS device plugged to HS HUB */ + if ((speed == HCD_DEVICE_SPEED_FULL) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) + { + if (HCcharMps > ISO_SPLT_MPS) + { + /* ISO Max Packet Size for Split mode */ + HCcharMps = ISO_SPLT_MPS; + } + } + } + + hhcd->hc[ch_num].speed = speed; + hhcd->hc[ch_num].max_packet = (uint16_t)HCcharMps; + + status = USB_HC_Init(hhcd->Instance, ch_num, epnum, + dev_address, speed, ep_type, (uint16_t)HCcharMps); + + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief Halt a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(hhcd); + (void)USB_HC_Halt(hhcd->Instance, ch_num); + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief DeInitialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) +{ + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + hhcd->State = HAL_HCD_STATE_BUSY; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + if (hhcd->MspDeInitCallback == NULL) + { + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hhcd->MspDeInitCallback(hhcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_HCD_MspDeInit(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_DISABLE(hhcd); + + hhcd->State = HAL_HCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @brief HCD IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USB Host Data + Transfer + +@endverbatim + * @{ + */ + +/** + * @brief Submit a new URB for processing. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param direction Channel number. + * This parameter can be one of these values: + * 0 : Output / 1 : Input + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type/ + * EP_TYPE_ISOC: Isochronous type/ + * EP_TYPE_BULK: Bulk type/ + * EP_TYPE_INTR: Interrupt type/ + * @param token Endpoint Type. + * This parameter can be one of these values: + * 0: HC_PID_SETUP / 1: HC_PID_DATA1 + * @param pbuff pointer to URB data + * @param length Length of URB data + * @param do_ping activate do ping protocol (for high speed only). + * This parameter can be one of these values: + * 0 : do ping inactive / 1 : do ping active + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, + uint8_t ch_num, + uint8_t direction, + uint8_t ep_type, + uint8_t token, + uint8_t *pbuff, + uint16_t length, + uint8_t do_ping) +{ + hhcd->hc[ch_num].ep_is_in = direction; + hhcd->hc[ch_num].ep_type = ep_type; + + if (token == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_SETUP; + hhcd->hc[ch_num].do_ping = do_ping; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + + /* Manage Data Toggle */ + switch (ep_type) + { + case EP_TYPE_CTRL: + if (token == 1U) /* send data */ + { + if (direction == 0U) + { + if (length == 0U) + { + /* For Status OUT stage, Length == 0U, Status Out PID = 1 */ + hhcd->hc[ch_num].toggle_out = 1U; + } + + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].do_ssplit == 1U) + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + } + } + break; + + case EP_TYPE_BULK: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + + break; + case EP_TYPE_INTR: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_ISOC: + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + break; + + default: + break; + } + + hhcd->hc[ch_num].xfer_buff = pbuff; + hhcd->hc[ch_num].xfer_len = length; + hhcd->hc[ch_num].urb_state = URB_IDLE; + hhcd->hc[ch_num].xfer_count = 0U; + hhcd->hc[ch_num].ch_num = ch_num; + hhcd->hc[ch_num].state = HC_IDLE; + + return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable); +} + +/** + * @brief Handle HCD interrupt request. + * @param hhcd HCD handle + * @retval None + */ +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + uint32_t interrupt; + + /* Ensure that we are in device mode */ + if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) + { + /* Avoid spurious interrupt */ + if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) + { + return; + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); + } + + /* Handle Host Disconnect Interrupts */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) + { + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); + + if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) + { + /* Flush USB Fifo */ + (void)USB_FlushTxFifo(USBx, 0x10U); + (void)USB_FlushRxFifo(USBx); + + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + { + /* Restore FS Clock */ + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } + + /* Handle Host Port Disconnect Interrupt */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->DisconnectCallback(hhcd); +#else + HAL_HCD_Disconnect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + + /* Handle Host Port Interrupts */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) + { + HCD_Port_IRQHandler(hhcd); + } + + /* Handle Host SOF Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback(hhcd); +#else + HAL_HCD_SOF_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); + } + + /* Handle Host channel Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) + { + interrupt = USB_HC_ReadInterrupt(hhcd->Instance); + for (i = 0U; i < hhcd->Init.Host_channels; i++) + { + if ((interrupt & (1UL << (i & 0xFU))) != 0U) + { + if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) + { + HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i); + } + else + { + HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i); + } + } + } + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); + } + + /* Handle Rx Queue Level Interrupts */ + if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) + { + USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + HCD_RXQLVL_IRQHandler(hhcd); + + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + } +} + + +/** + * @brief SOF callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_SOF_Callback could be implemented in the user file + */ +} + +/** + * @brief Connection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Connect_Callback could be implemented in the user file + */ +} + +/** + * @brief Disconnection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Enabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Disabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Notify URB state change callback. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @param urb_state: + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL/ + * @retval None + */ +__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + UNUSED(chnum); + UNUSED(urb_state); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file + */ +} + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB HCD Callback + * To be used instead of the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = pCallback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = pCallback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = pCallback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = pCallback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = pCallback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Unregister an USB HCD Callback + * USB HCD callback is redirected to the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + /* Setup Legacy weak Callbacks */ + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Register USB HCD Host Channel Notify URB Change Callback + * To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = pCallback; + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief Unregister the USB HCD Host Channel Notify URB Change Callback + * USB HCD Host Channel Notify URB Change Callback is redirected + * to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the HCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + /* Enable port power */ + (void)USB_DriveVbus(hhcd->Instance, 1U); + + /* Enable global interrupt */ + __HAL_HCD_ENABLE(hhcd); + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Stop the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + (void)USB_StopHost(hhcd->Instance); + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Reset the host port. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) +{ + return (USB_ResetPort(hhcd->Instance)); +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the HCD handle state. + * @param hhcd HCD handle + * @retval HAL state + */ +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd) +{ + return hhcd->State; +} + +/** + * @brief Return URB state for a channel. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval URB state. + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL + */ +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].urb_state; +} + + +/** + * @brief Return the last host transfer size. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval last transfer size in byte + */ +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].xfer_count; +} + +/** + * @brief Return the Host Channel state. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval Host channel state + * This parameter can be one of these values: + * HC_IDLE/ + * HC_XFRC/ + * HC_HALTED/ + * HC_NYET/ + * HC_NAK/ + * HC_STALL/ + * HC_XACTERR/ + * HC_BBLERR/ + * HC_DATATGLERR + */ +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].state; +} + +/** + * @brief Return the current Host frame number. + * @param hhcd HCD handle + * @retval Current Host frame number + */ +uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetCurrentFrame(hhcd->Instance)); +} + +/** + * @brief Return the Host enumeration speed. + * @param hhcd HCD handle + * @retval Enumeration speed + */ +uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetHostSpeed(hhcd->Instance)); +} + +/** + * @brief Set host channel Hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param addr Hub address + * @param PortNbr Hub port number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr) +{ + uint32_t HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance); + + /* LS/FS device plugged to HS HUB */ + if ((hhcd->hc[ch_num].speed != HCD_DEVICE_SPEED_HIGH) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) + { + hhcd->hc[ch_num].do_ssplit = 1U; + + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) && (hhcd->hc[ch_num].ep_is_in != 0U)) + { + hhcd->hc[ch_num].toggle_in = 1U; + } + } + + hhcd->hc[ch_num].hub_addr = addr; + hhcd->hc[ch_num].hub_port_nbr = PortNbr; + + return HAL_OK; +} + + +/** + * @brief Clear host channel hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + hhcd->hc[ch_num].do_ssplit = 0U; + hhcd->hc[ch_num].do_csplit = 0U; + hhcd->hc[ch_num].hub_addr = 0U; + hhcd->hc[ch_num].hub_port_nbr = 0U; + + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup HCD_Private_Functions + * @{ + */ +/** + * @brief Handle Host Channel IN interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR); + hhcd->hc[chnum].state = HC_BBLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else + { + /* ... */ + } + + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) + { + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) + { + /* Clear any pending ACK IT */ + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + if (hhcd->Init.dma_enable != 0U) + { + hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); + } + + hhcd->hc[chnum].state = HC_XFRC; + hhcd->hc[chnum].ErrCnt = 0U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + } + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) || + (hhcd->hc[chnum].ep_type == EP_TYPE_ISOC)) + { + USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + hhcd->hc[chnum].urb_state = URB_DONE; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else + { + /* ... */ + } + + if (hhcd->Init.dma_enable == 1U) + { + if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U) + { + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else + { + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 1U; + hhcd->hc[chnum].state = HC_ACK; + + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + + if (hhcd->hc[chnum].state == HC_XFRC) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; + } + else if (hhcd->hc[chnum].state == HC_STALL) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; + } + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) + { + hhcd->hc[chnum].ErrCnt = 0U; + + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + hhcd->hc[chnum].ep_ss_schedule = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_NYET) + { + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + { + hhcd->hc[chnum].NyetErrCnt++; + if (hhcd->hc[chnum].NyetErrCnt > 2U) + { + hhcd->hc[chnum].NyetErrCnt = 0U; + hhcd->hc[chnum].do_csplit = 0U; + + if (hhcd->hc[chnum].ErrCnt < 3U) + { + hhcd->hc[chnum].ep_ss_schedule = 1U; + } + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_ACK) + { + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Set Complete split and re-activate the channel */ + USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; + USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + else if (hhcd->hc[chnum].state == HC_BBLERR) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + if (hhcd->hc[chnum].state == HC_HALTED) + { + return; + } + } + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].state = HC_NYET; + + if (hhcd->hc[chnum].do_ssplit == 0U) + { + hhcd->hc[chnum].ErrCnt = 0U; + } + + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) + { + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + hhcd->hc[chnum].ErrCnt = 0U; + + if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U)) + { + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + } + else + { + /* ... */ + } + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + __HAL_HCD_UNMASK_ACK_HC_INT(chnum); + } + + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + } + else + { + /* ... */ + } +} + +/** + * @brief Handle Host Channel OUT interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + uint32_t num_packets; + + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_ping == 1U) + { + hhcd->hc[chnum].do_ping = 0U; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_ACK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + + if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U)) + { + if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC) + { + hhcd->hc[chnum].do_csplit = 1U; + } + + hhcd->hc[chnum].state = HC_ACK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + + /* reset error_count */ + hhcd->hc[chnum].ErrCnt = 0U; + } + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) + { + hhcd->hc[chnum].ErrCnt = 0U; + + /* transaction completed with NYET state, update do ping state */ + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + hhcd->hc[chnum].do_ping = 1U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + } + + if (hhcd->hc[chnum].do_csplit != 0U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); + hhcd->hc[chnum].state = HC_XFRC; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + hhcd->hc[chnum].state = HC_NYET; + + if (hhcd->hc[chnum].do_ssplit == 0U) + { + hhcd->hc[chnum].do_ping = 1U; + } + + hhcd->hc[chnum].ErrCnt = 0U; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; + + if (hhcd->hc[chnum].do_ping == 0U) + { + if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH) + { + hhcd->hc[chnum].do_ping = 1U; + } + } + + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) + { + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else + { + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + } + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) + { + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + + if (hhcd->hc[chnum].state == HC_XFRC) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) || + (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)) + { + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[chnum].toggle_out ^= 1U; + } + + if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U)) + { + num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet; + + if ((num_packets & 1U) != 0U) + { + hhcd->hc[chnum].toggle_out ^= 1U; + } + } + } + } + else if (hhcd->hc[chnum].state == HC_ACK) + { + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + } + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + } + else if (hhcd->hc[chnum].state == HC_NYET) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + else if (hhcd->hc[chnum].state == HC_STALL) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; + } + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + else + { + return; + } + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else + { + return; + } +} + +/** + * @brief Handle Rx Queue Level interrupt requests. + * @param hhcd HCD handle + * @retval none + */ +static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t pktsts; + uint32_t pktcnt; + uint32_t GrxstspReg; + uint32_t xferSizePktCnt; + uint32_t tmpreg; + uint32_t chnum; + + GrxstspReg = hhcd->Instance->GRXSTSP; + chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; + pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17; + pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4; + + switch (pktsts) + { + case GRXSTS_PKTSTS_IN: + /* Read the data into the host buffer. */ + if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0)) + { + if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len) + { + (void)USB_ReadPacket(hhcd->Instance, + hhcd->hc[chnum].xfer_buff, (uint16_t)pktcnt); + + /* manage multiple Xfer */ + hhcd->hc[chnum].xfer_buff += pktcnt; + hhcd->hc[chnum].xfer_count += pktcnt; + + /* get transfer size packet count */ + xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; + + if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U)) + { + /* re-activate the channel when more packets are expected */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else + { + hhcd->hc[chnum].urb_state = URB_ERROR; + } + } + break; + + case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + case GRXSTS_PKTSTS_CH_HALTED: + default: + break; + } +} + +/** + * @brief Handle Host Port interrupt requests. + * @param hhcd HCD handle + * @retval None + */ +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0; + __IO uint32_t hprt0_dup; + + /* Handle Host Port Interrupts */ + hprt0 = USBx_HPRT0; + hprt0_dup = USBx_HPRT0; + + hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + /* Check whether Port Connect detected */ + if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) + { + if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->ConnectCallback(hhcd); +#else + HAL_HCD_Connect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + hprt0_dup |= USB_OTG_HPRT_PCDET; + } + + /* Check whether Port Enable Changed */ + if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) + { + hprt0_dup |= USB_OTG_HPRT_PENCHNG; + + if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) + { + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + { + if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) + { + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ); + } + else + { + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } + } + else + { + if (hhcd->Init.speed == HCD_SPEED_FULL) + { + USBx_HOST->HFIR = HFIR_60_MHZ; + } + } +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortEnabledCallback(hhcd); +#else + HAL_HCD_PortEnabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + } + else + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortDisabledCallback(hhcd); +#else + HAL_HCD_PortDisabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + + /* Check for an overcurrent */ + if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) + { + hprt0_dup |= USB_OTG_HPRT_POCCHNG; + } + + /* Clear Port Interrupts */ + USBx_HPRT0 = hprt0_dup; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* HAL_HCD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i2c.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i2c.c new file mode 100644 index 00000000000..6503ce390cc --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i2c.c @@ -0,0 +1,7809 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive channel + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx channel + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx channel + + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. + + (+) Different sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). + [..] + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + +#define MAX_NBYTE_SIZE 255U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) +/*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT + and @ref I2C_XFER_RX_IT */ + +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Macro + * @{ + */ +#if defined(HAL_DMA_MODULE_ENABLED) +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__)) +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +#if defined(HAL_DMA_MODULE_ENABLED) +/* Private functions to handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +#if defined(HAL_DMA_MODULE_ENABLED) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +#endif /* HAL_DMA_MODULE_ENABLED */ + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + +/* Private function to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private function to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + else + { + /* Clear the I2C ADD10 bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_WRITE); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until AF flag is set */ + error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + + tmpXferCount = hi2c->XferCount; + if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + { + /* Reset ErrorCode to NONE */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + } + else + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + if (hi2c->XferCount != 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, + (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->XferSize = 0U; + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t I2C_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Increment Trials */ + I2C_Trials++; + } while (I2C_Trials < Trials); + + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort DMA Xfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + +#if defined(HAL_DMA_MODULE_ENABLED) + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + uint32_t tmperror; + + /* I2C Bus error interrupt occurred ------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, tmperror); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + if (hi2c->Memaddress == 0xFFFFFFFFU) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + + if ((hi2c->XferCount == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + else + { + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t xfermode; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if (hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + xfermode = hi2c->XferOptions; + } + else + { + xfermode = I2C_AUTOEND_MODE; + } + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error and NACK interrupt for data transfer */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + { + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } + } + } + + if (treatdmanack == 1U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else + { + /* Only Clear NACK Flag, no DMA treatment is pending */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection; + uint16_t slaveaddrcode; + uint16_t ownadd1code; + uint16_t ownadd2code; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if (hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hi2c->XferOptions; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else if (tmpstate == HAL_I2C_STATE_LISTEN) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + /* Do nothing */ + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + if (hi2c->hdmatx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); + } + } + else + { + /* Do nothing */ + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + } + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ + I2C_ITSlaveSeqCplt(hi2c); + + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + +#if defined(HAL_DMA_MODULE_ENABLED) + uint32_t tmppreviousstate; +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + } + hi2c->XferISR = NULL; + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort DMA TX transfer if any */ + tmppreviousstate = hi2c->PreviousState; + + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef dmaxferstatus = HAL_OK; + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + + if (dmaxferstatus != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef dmaxferstatus = HAL_OK; + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + hi2c->XferSize); + } + + if (dmaxferstatus != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +} + + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Reset AbortCpltCallback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferAbortCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferAbortCallback = NULL; + } + + I2C_TreatErrorCallback(hi2c); +} + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief This function handles I2C Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The actual Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + + /* Check if a STOPF is detected */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + status = HAL_OK; + } + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + status = HAL_ERROR; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + } + + /* Check for the Timeout */ + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + status = HAL_ERROR; + } + } + } + return status; +} + +/** + * @brief This function handles errors detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t itflag = hi2c->Instance->ISR; + uint32_t error_code = 0; + uint32_t tickstart = Tickstart; + uint32_t tmp1; + HAL_I2C_ModeTypeDef tmp2; + + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP Flag is set or timeout occurred */ + /* AutoEnd should be initiate after AF */ + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); + tmp2 = hi2c->Mode; + + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ + (tmp1 != I2C_CR2_STOP) && \ + (tmp2 != HAL_I2C_MODE_SLAVE)) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + } + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) + { + error_code |= HAL_I2C_ERROR_TIMEOUT; + + status = HAL_ERROR; + + break; + } + } + } + } + } + + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + error_code |= HAL_I2C_ERROR_AF; + + status = HAL_ERROR; + } + + /* Refresh Content of Status register */ + itflag = hi2c->Instance->ISR; + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + { + error_code |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + + status = HAL_ERROR; + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + { + error_code |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + + status = HAL_ERROR; + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + { + error_code |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + + status = HAL_ERROR; + } + + if (status != HAL_OK) + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode |= error_code; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + + return status; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, \ + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), tmp); +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + +#if defined(HAL_DMA_MODULE_ENABLED) + if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ + (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + (hi2c->XferISR != I2C_Mem_ISR_DMA)) +#endif /* HAL_DMA_MODULE_ENABLED */ + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + +#if defined(HAL_DMA_MODULE_ENABLED) + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i2c_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i2c_ex.c new file mode 100644 index 00000000000..71dcd76070b --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i2c_ex.c @@ -0,0 +1,359 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C Extended peripheral: + * + Filter Mode Functions + * + WakeUp Mode Functions + * + FastModePlus Functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### I2C peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32H7RSxx + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter and Wake Up Feature + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + (++) HAL_I2CEx_EnableWakeUp() + (++) HAL_I2CEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_ConfigFastModePlus() + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions + * +@verbatim + =============================================================================== + ##### Filter Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Analog noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure I2C Digital noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Enable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Fast Mode Plus. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param FastModePlus New state of the Fast Mode Plus. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_FASTMODEPLUS(FastModePlus)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + if (FastModePlus == I2C_FASTMODEPLUS_ENABLE) + { + /* Set I2Cx FMP bit */ + hi2c->Instance->CR1 |= (I2C_CR1_FMP); + } + else + { + /* Reset I2Cx FMP bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_FMP); + } + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i2s.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i2s.c new file mode 100644 index 00000000000..76a3622d5f2 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i2s.c @@ -0,0 +1,2710 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_i2s.c + * @author MCD Application Team + * @brief I2S HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Integrated Interchip Sound (I2S) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The I2S HAL driver can be used as follow: + + (#) Declare a I2S_HandleTypeDef handle structure. + (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: + (##) Enable the SPIx interface clock. + (##) I2S pins configuration: + (+++) Enable the clock for the I2S GPIOs. + (+++) Configure these I2S pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT() + and HAL_I2S_Receive_IT() APIs). + (+++) Configure the I2Sx interrupt priority. + (+++) Enable the NVIC I2S IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA() + and HAL_I2S_Receive_DMA() APIs: + (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx Stream/Channel. + (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the + DMA Tx/Rx Stream/Channel. + + (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity + using HAL_I2S_Init() function. + + -@- The specific I2S interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process. + + (+@) External clock source is configured after setting correctly + the define constant EXTERNAL_CLOCK_VALUE in the stm32h7rsxx_hal_conf.h file. + + (#) Three mode of operations are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() + (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() + (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback + (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() + (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback + (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxCpltCallback + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2S_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() + (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback + (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() + (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback + (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxCpltCallback + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2S_ErrorCallback + (+) Pause the DMA Transfer using HAL_I2S_DMAPause() + (+) Resume the DMA Transfer using HAL_I2S_DMAResume() + (+) Stop the DMA Transfer using HAL_I2S_DMAStop() + + *** I2S HAL driver macros list *** + =================================== + [..] + Below the list of most used macros in I2S HAL driver. + + (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) + (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) + (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts + (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts + (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not + + [..] + (@) You can refer to the I2S HAL driver header file for more useful macros + + *** I2S HAL driver macros list *** + =================================== + [..] + Callback registration: + + (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1UL + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback. + + Function HAL_I2S_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : I2S Tx Completed callback + (+) RxCpltCallback : I2S Rx Completed callback + (+) TxRxCpltCallback : I2S TxRx Completed callback + (+) TxHalfCpltCallback : I2S Tx Half Completed callback + (+) RxHalfCpltCallback : I2S Rx Half Completed callback + (+) TxRxHalfCpltCallback : I2S TxRx Half Completed callback + (+) ErrorCallback : I2S Error callback + (+) MspInitCallback : I2S Msp Init callback + (+) MspDeInitCallback : I2S Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : I2S Tx Completed callback + (+) RxCpltCallback : I2S Rx Completed callback + (+) TxRxCpltCallback : I2S TxRx Completed callback + (+) TxHalfCpltCallback : I2S Tx Half Completed callback + (+) RxHalfCpltCallback : I2S Rx Half Completed callback + (+) TxRxHalfCpltCallback : I2S TxRx Half Completed callback + (+) ErrorCallback : I2S Error callback + (+) MspInitCallback : I2S Msp Init callback + (+) MspDeInitCallback : I2S Msp DeInit callback + + By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit() + or HAL_I2S_Init() function. + + When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +#ifdef HAL_I2S_MODULE_ENABLED + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup I2S I2S + * @brief I2S HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup I2S_Private_Define I2S Private Define + * @{ + */ +#define I2S_TIMEOUT 0xFFFFUL +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup I2S_Private_Functions I2S Private Functions + * @{ + */ +static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma); +static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMAError(DMA_HandleTypeDef *hdma); +static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s); +static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s); +static void I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s); +static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s); +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, + uint32_t Tickstart, uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup I2S_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the I2Sx peripheral in simplex mode: + + (+) User must Implement HAL_I2S_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2S_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Standard + (++) Data Format + (++) MCLK Output + (++) Audio frequency + (++) Polarity + + (+) Call the function HAL_I2S_DeInit() to restore the default configuration + of the selected I2Sx peripheral. + @endverbatim + * @{ + */ + +/** + * @brief Initializes the I2S according to the specified parameters + * in the I2S_InitTypeDef and create the associated handle. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) +{ + uint32_t i2sdiv; + uint32_t i2sodd; + uint32_t packetlength; + uint32_t tmp; + uint32_t i2sclk; + uint32_t ispcm; + + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); + assert_param(IS_I2S_MODE(hi2s->Init.Mode)); + assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); + assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); + assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); + assert_param(IS_I2S_FIRST_BIT(hi2s->Init.FirstBit)); + assert_param(IS_I2S_WS_INVERSION(hi2s->Init.WSInversion)); + assert_param(IS_I2S_DATA_24BIT_ALIGNMENT(hi2s->Init.Data24BitAlignment)); + assert_param(IS_I2S_MASTER_KEEP_IO_STATE(hi2s->Init.MasterKeepIOState)); + + if (hi2s->State == HAL_I2S_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2s->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) + /* Init the I2S Callback settings */ + hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hi2s->MspInitCallback == NULL) + { + hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hi2s->MspInitCallback(hi2s); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2S_MspInit(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + + hi2s->State = HAL_I2S_STATE_BUSY; + + /* Disable the selected I2S peripheral */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE) + { + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + } + + /* Clear I2S configuration register */ + CLEAR_REG(hi2s->Instance->I2SCFGR); + + if (IS_I2S_MASTER(hi2s->Init.Mode)) + { + /*------------------------- I2SDIV and ODD Calculation ---------------------*/ + /* If the requested audio frequency is not the default, compute the prescaler */ + if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) + { + /* Check the frame length (For the Prescaler computing) ********************/ + if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) + { + /* Channel length is 32 bits */ + packetlength = 2UL; + } + else + { + /* Channel length is 16 bits */ + packetlength = 1UL; + } + + /* Check if PCM standard is used */ + if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || + (hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)) + { + ispcm = 1UL; + } + else + { + ispcm = 0UL; + } + + /* Get the source clock value: based on System Clock value */ + if (hi2s->Instance == SPI1) + { + i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI1); + } + else if ((hi2s->Instance == SPI2) || (hi2s->Instance == SPI3)) + { + i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI23); + } + else /* SPI6 source clock */ + { + i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6); + } + + /* Compute the Real divider depending on the MCLK output state, with a floating point */ + if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) + { + /* MCLK output is enabled */ + tmp = (uint32_t)((((i2sclk / (256UL >> ispcm)) * 10UL) / hi2s->Init.AudioFreq) + 5UL); + } + else + { + /* MCLK output is disabled */ + tmp = (uint32_t)((((i2sclk / ((32UL >> ispcm) * packetlength)) * 10UL) / hi2s->Init.AudioFreq) + 5UL); + } + + /* Remove the flatting point */ + tmp = tmp / 10UL; + + /* Check the parity of the divider */ + i2sodd = (uint32_t)(tmp & (uint32_t)1UL); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint32_t)((tmp - i2sodd) / 2UL); + } + else + { + /* Set the default values */ + i2sdiv = 2UL; + i2sodd = 0UL; + } + + /* Test if the obtain values are forbidden or out of range */ + if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL)) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER); + return HAL_ERROR; + } + + /* Force i2smod to 1 just to be sure that (2xi2sdiv + i2sodd) is always higher than 0 */ + if (i2sdiv == 0UL) + { + i2sodd = 1UL; + } + + MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD), + ((i2sdiv << SPI_I2SCFGR_I2SDIV_Pos) | (i2sodd << SPI_I2SCFGR_ODD_Pos))); + } + + /*-------------------------- I2Sx I2SCFGR Configuration --------------------*/ + /* Configure I2SMOD, I2SCFG, I2SSTD, PCMSYNC, DATLEN ,CHLEN ,CKPOL, WSINV, DATAFMT, I2SDIV, ODD and MCKOE bits bits */ + /* And configure the I2S with the I2S_InitStruct values */ + MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SCFG | \ + SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | \ + SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | \ + SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_WSINV | \ + SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_MCKOE), + (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \ + hi2s->Init.Standard | hi2s->Init.DataFormat | \ + hi2s->Init.CPOL | hi2s->Init.WSInversion | \ + hi2s->Init.Data24BitAlignment | hi2s->Init.MCLKOutput)); + /*Clear status register*/ + WRITE_REG(hi2s->Instance->IFCR, 0x0FF8); + + /*---------------------------- I2Sx CFG2 Configuration ----------------------*/ + + /* Unlock the AF configuration to configure CFG2 register*/ + CLEAR_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK); + + MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_LSBFRST, hi2s->Init.FirstBit); + + /* Insure that AFCNTR is managed only by Master */ + if (IS_I2S_MASTER(hi2s->Init.Mode)) + { + /* Alternate function GPIOs control */ + MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_AFCNTR, (hi2s->Init.MasterKeepIOState)); + } + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the I2S peripheral + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); + + hi2s->State = HAL_I2S_STATE_BUSY; + + /* Disable the I2S Peripheral Clock */ + __HAL_I2S_DISABLE(hi2s); + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) + if (hi2s->MspDeInitCallback == NULL) + { + hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hi2s->MspDeInitCallback(hi2s); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_I2S_MspDeInit(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief I2S MSP Init + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_MspInit could be implemented in the user file + */ +} + +/** + * @brief I2S MSP DeInit + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) +/** + * @brief Register a User I2S Callback + * To be used instead of the weak predefined callback + * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for the specified I2S. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, + pI2S_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2s); + + if (HAL_I2S_STATE_READY == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_TX_COMPLETE_CB_ID : + hi2s->TxCpltCallback = pCallback; + break; + + case HAL_I2S_RX_COMPLETE_CB_ID : + hi2s->RxCpltCallback = pCallback; + break; + + case HAL_I2S_TX_RX_COMPLETE_CB_ID : + hi2s->TxRxCpltCallback = pCallback; + break; + + case HAL_I2S_TX_HALF_COMPLETE_CB_ID : + hi2s->TxHalfCpltCallback = pCallback; + break; + + case HAL_I2S_RX_HALF_COMPLETE_CB_ID : + hi2s->RxHalfCpltCallback = pCallback; + break; + + + case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID : + hi2s->TxRxHalfCpltCallback = pCallback; + break; + + case HAL_I2S_ERROR_CB_ID : + hi2s->ErrorCallback = pCallback; + break; + + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = pCallback; + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2S_STATE_RESET == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = pCallback; + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2s); + return status; +} + +/** + * @brief Unregister an I2S Callback + * I2S callback is redirected to the weak predefined callback + * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for the specified I2S. + * @param CallbackID ID of the callback to be unregistered + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2s); + + if (HAL_I2S_STATE_READY == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_TX_COMPLETE_CB_ID : + hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_I2S_RX_COMPLETE_CB_ID : + hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_I2S_TX_RX_COMPLETE_CB_ID : + hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_I2S_TX_HALF_COMPLETE_CB_ID : + hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_I2S_RX_HALF_COMPLETE_CB_ID : + hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID : + hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + break; + + case HAL_I2S_ERROR_CB_ID : + hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2S_STATE_RESET == hi2s->State) + { + switch (CallbackID) + { + case HAL_I2S_MSPINIT_CB_ID : + hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2S_MSPDEINIT_CB_ID : + hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2s); + return status; +} +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2S data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2S_Transmit() + (++) HAL_I2S_Receive() + (++) HAL_I2SEx_TransmitReceive() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2S_Transmit_IT() + (++) HAL_I2S_Receive_IT() + (++) HAL_I2SEx_TransmitReceive_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2S_Transmit_DMA() + (++) HAL_I2S_Receive_DMA() + (++) HAL_I2SEx_TransmitReceive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2S_TxCpltCallback() + (++) HAL_I2S_RxCpltCallback() + (++) HAL_I2SEx_TxRxCpltCallback() + (++) HAL_I2S_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @param Timeout Timeout duration + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size, uint32_t Timeout) +{ +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR)); +#endif /* __GNUC__ */ + uint32_t tickstart; + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pTxBuffPtr = (const uint16_t *)pData; + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + + /* Initialize fields not used in handle to zero */ + hi2s->pRxBuffPtr = NULL; + hi2s->RxXferSize = (uint16_t) 0UL; + hi2s->RxXferCount = (uint16_t) 0UL; + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Start the transfer */ + SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); + + + /* Wait until TXP flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, tickstart, Timeout) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_TIMEOUT; + } + + while (hi2s->TxXferCount > 0UL) + { + if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B)) + { + /* Transmit data in 32 Bit mode */ + hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr); + hi2s->pTxBuffPtr += 2; + hi2s->TxXferCount--; + } + else + { + /* Transmit data in 16 Bit mode */ +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr); +#else + *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr); +#endif /* __GNUC__ */ + + hi2s->pTxBuffPtr++; + hi2s->TxXferCount--; + } + + /* Wait until TXP flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, tickstart, Timeout) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_TIMEOUT; + } + + /* Check if an underrun occurs */ + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) + { + /* Clear underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + } + } + + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @param Timeout Timeout duration + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate + * in continuous way and as the I2S is not disabled at the end of the I2S transaction. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) +{ +#if defined (__GNUC__) + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR)); +#endif /* __GNUC__ */ + uint32_t tickstart; + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pRxBuffPtr = pData; + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + + /* Initialize fields not used in handle to zero */ + hi2s->pTxBuffPtr = NULL; + hi2s->TxXferSize = (uint16_t) 0UL; + hi2s->TxXferCount = (uint16_t) 0UL; + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Start the transfer */ + SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); + + /* Receive data */ + while (hi2s->RxXferCount > 0UL) + { + /* Wait until RXP flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXP, SET, tickstart, Timeout) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_TIMEOUT; + } + + if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B)) + { + /* Receive data in 32 Bit mode */ + *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR; + hi2s->pRxBuffPtr += 2; + hi2s->RxXferCount--; + } + else + { + /* Receive data in 16 Bit mode */ +#if defined (__GNUC__) + *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR); +#endif /* __GNUC__ */ + hi2s->pRxBuffPtr++; + hi2s->RxXferCount--; + } + + /* Check if an overrun occurs */ + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) + { + /* Clear overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + } + } + + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Full-Duplex Transmit/Receive data in blocking mode. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pTxData a 16-bit pointer to the Transmit data buffer. + * @param pRxData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @param Timeout Timeout duration + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tmp_TxXferCount; + uint32_t tmp_RxXferCount; + uint32_t tickstart; + +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR)); + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR)); +#endif /* __GNUC__ */ + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + hi2s->pTxBuffPtr = (const uint16_t *)pTxData; + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + hi2s->pRxBuffPtr = pRxData; + + tmp_TxXferCount = hi2s->TxXferCount; + tmp_RxXferCount = hi2s->RxXferCount; + + /* Set state and reset error code */ + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Start the transfer */ + SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); + + while ((tmp_TxXferCount > 0UL) || (tmp_RxXferCount > 0UL)) + { + if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXP) == SET) && (tmp_TxXferCount != 0UL)) + { + if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B)) + { + /* Transmit data in 32 Bit mode */ + hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr); + hi2s->pTxBuffPtr += 2; + tmp_TxXferCount--; + } + else + { + /* Transmit data in 16 Bit mode */ +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr); +#else + *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr); +#endif /* __GNUC__ */ + + hi2s->pTxBuffPtr++; + tmp_TxXferCount--; + } + + /* Check if an underrun occurs */ + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) + { + /* Clear underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + } + } + + if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXP) == SET) && (tmp_RxXferCount != 0UL)) + { + if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B)) + { + /* Receive data in 32 Bit mode */ + *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR; + hi2s->pRxBuffPtr += 2; + tmp_RxXferCount--; + } + else + { + /* Receive data in 16 Bit mode */ +#if defined (__GNUC__) + *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR); +#endif /* __GNUC__ */ + hi2s->pRxBuffPtr++; + tmp_RxXferCount--; + } + + /* Check if an overrun occurs */ + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) + { + /* Clear overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + } + } + + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_TIMEOUT; + } + } + + hi2s->State = HAL_I2S_STATE_READY; + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size) +{ + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pTxBuffPtr = (const uint16_t *)pData; + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + + /* Initialize fields not used in handle to zero */ + hi2s->pRxBuffPtr = NULL; + hi2s->RxXferSize = (uint16_t) 0UL; + hi2s->RxXferCount = (uint16_t) 0UL; + + /* Set the function for IT treatment */ + if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B)) + { + hi2s->TxISR = I2S_Transmit_32Bit_IT; + } + else + { + hi2s->TxISR = I2S_Transmit_16Bit_IT; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Enable TXP and UDR interrupt */ + __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_UDR)); + + /* Enable TIFRE interrupt if the mode is Slave */ + if (hi2s->Init.Mode == I2S_MODE_SLAVE_TX) + { + __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE); + } + + /* Start the transfer */ + SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); + + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization + * between Master and Slave otherwise the I2S interrupt should be optimized. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pRxBuffPtr = pData; + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + + /* Initialize fields not used in handle to zero */ + hi2s->pTxBuffPtr = NULL; + hi2s->TxXferSize = (uint16_t) 0UL; + hi2s->TxXferCount = (uint16_t) 0UL; + + /* Set the function for IT treatment */ + if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B)) + { + hi2s->RxISR = I2S_Receive_32Bit_IT; + } + else + { + hi2s->RxISR = I2S_Receive_16Bit_IT; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + /* Enable RXP and ERR interrupt */ + __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_OVR)); + + /* Enable TIFRE interrupt if the mode is Slave */ + if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX) + { + __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE); + } + + /* Start the transfer */ + SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); + + __HAL_UNLOCK(hi2s); + return HAL_OK; +} + +/** + * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pTxData a 16-bit pointer to the Transmit data buffer. + * @param pRxData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData, + uint16_t Size) +{ + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + hi2s->pTxBuffPtr = (const uint16_t *)pTxData; + hi2s->pRxBuffPtr = pRxData; + + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; + + + /* Set the function for IT treatment */ + if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B)) + { + hi2s->TxISR = I2S_Transmit_32Bit_IT; + hi2s->RxISR = I2S_Receive_32Bit_IT; + } + else + { + hi2s->TxISR = I2S_Transmit_16Bit_IT; + hi2s->RxISR = I2S_Receive_16Bit_IT; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Enable TXP, RXP, DXP, UDR, OVR interrupts */ + __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_UDR | I2S_IT_OVR)); + + /* Enable TIFRE interrupt if the mode is Slave */ + if (hi2s->Init.Mode == I2S_MODE_SLAVE_FULLDUPLEX) + { + __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE); + } + + /* Start the transfer */ + SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); + + __HAL_UNLOCK(hi2s); + return HAL_OK; + +} + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to the Transmit data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode; + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pTxBuffPtr = (const uint16_t *)pData; + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hi2s->pRxBuffPtr = NULL; + hi2s->RxXferSize = (uint16_t)0UL; + hi2s->RxXferCount = (uint16_t)0UL; + + /* Set the I2S Tx DMA Half transfer complete callback */ + hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; + + /* Set the I2S Tx DMA transfer complete callback */ + hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; + + /* Set the DMA error callback */ + hi2s->hdmatx->XferErrorCallback = I2S_DMAError; + + if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED)) + { + hi2s->TxXferCount = Size * 2U; + } + else + { + hi2s->TxXferCount = Size * 4U; + } + + /* Enable the Tx DMA Stream/Channel */ + if ((hi2s->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2s->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->TxXferCount; + + /* Set DMA source address */ + hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pTxBuffPtr; + + /* Set DMA destination address */ + hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->TXDR; + + errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmatx); + } + else + { + /* Update SPI error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + + /* Unlock the process */ + __HAL_UNLOCK(hi2s); + + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + return errorcode; + } + } + else + { + errorcode = HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, + hi2s->TxXferCount); + } + + /* Check status */ + if (errorcode != HAL_OK) + { + /* Update I2S error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + hi2s->State = HAL_I2S_STATE_READY; + + __HAL_UNLOCK(hi2s); + errorcode = HAL_ERROR; + return errorcode; + } + + /* Check if the I2S Tx request is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN)) + { + /* Enable Tx DMA Request */ + SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); + } + + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Start the transfer */ + SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); + + __HAL_UNLOCK(hi2s); + return errorcode; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode; + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->pRxBuffPtr = pData; + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hi2s->pTxBuffPtr = NULL; + hi2s->TxXferSize = (uint16_t)0UL; + hi2s->TxXferCount = (uint16_t)0UL; + + + /* Set the I2S Rx DMA Half transfer complete callback */ + hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; + + /* Set the I2S Rx DMA transfer complete callback */ + hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; + + /* Set the DMA error callback */ + hi2s->hdmarx->XferErrorCallback = I2S_DMAError; + + if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED)) + { + hi2s->RxXferCount = Size * 2U; + } + else + { + hi2s->RxXferCount = Size * 4U; + } + + /* Enable the Rx DMA Stream/Channel */ + if ((hi2s->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2s->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->RxXferCount; + + /* Set DMA source address */ + hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->RXDR; + + /* Set DMA destination address */ + hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pRxBuffPtr; + + errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmarx); + } + else + { + /* Update SPI error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + + /* Unlock the process */ + __HAL_UNLOCK(hi2s); + + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + return errorcode; + } + } + else + { + errorcode = HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, + hi2s->RxXferCount); + } + + /* Check status */ + if (errorcode != HAL_OK) + { + /* Update I2S error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + __HAL_UNLOCK(hi2s); + return errorcode; + } + + /* Check if the I2S Rx request is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + /* Enable Rx DMA Request */ + SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN); + } + + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Start the transfer */ + SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); + + __HAL_UNLOCK(hi2s); + return errorcode; +} + +/** + * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param pTxData a 16-bit pointer to the Transmit data buffer. + * @param pRxData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: + * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData, + uint16_t Size) +{ + HAL_StatusTypeDef errorcode; + + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + + hi2s->pTxBuffPtr = (const uint16_t *)pTxData; + hi2s->pRxBuffPtr = pRxData; + + hi2s->TxXferSize = Size; + hi2s->TxXferCount = Size; + hi2s->RxXferSize = Size; + hi2s->RxXferCount = Size; + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; + + /* Reset the Tx/Rx DMA bits */ + CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Set the I2S Rx DMA Half transfer complete callback */ + hi2s->hdmarx->XferHalfCpltCallback = I2SEx_DMATxRxHalfCplt; + + /* Set the I2S Rx DMA transfer complete callback */ + hi2s->hdmarx->XferCpltCallback = I2SEx_DMATxRxCplt; + + /* Set the I2S Rx DMA error callback */ + hi2s->hdmarx->XferErrorCallback = I2S_DMAError; + if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED)) + { + hi2s->TxXferCount = Size * 2U; + } + else + { + hi2s->TxXferCount = Size * 4U; + } + + /* Enable the Tx DMA Stream/Channel */ + if ((hi2s->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2s->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->TxXferCount; + + /* Set DMA source address */ + hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pTxBuffPtr; + + /* Set DMA destination address */ + hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->TXDR; + + errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmatx); + } + else + { + /* Update SPI error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + + /* Unlock the process */ + __HAL_UNLOCK(hi2s); + + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + return errorcode; + } + } + else + { + errorcode = HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, + hi2s->TxXferCount); + } + + /* Check status */ + if (errorcode != HAL_OK) + { + /* Update I2S error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + hi2s->State = HAL_I2S_STATE_READY; + + __HAL_UNLOCK(hi2s); + errorcode = HAL_ERROR; + return errorcode; + } + + /* Check if the I2S Tx request is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN)) + { + /* Enable Tx DMA Request */ + SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); + } + + if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED)) + { + hi2s->RxXferCount = Size * 2U; + } + else + { + hi2s->RxXferCount = Size * 4U; + } + + /* Enable the Rx DMA Stream/Channel */ + if ((hi2s->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2s->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->RxXferCount; + + /* Set DMA source address */ + hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->RXDR; + + /* Set DMA destination address */ + hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pRxBuffPtr; + + errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmarx); + } + else + { + /* Update SPI error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + + /* Unlock the process */ + __HAL_UNLOCK(hi2s); + + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + return errorcode; + } + } + else + { + errorcode = HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, + hi2s->RxXferCount); + } + + /* Check status */ + if (errorcode != HAL_OK) + { + /* Update I2S error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + __HAL_UNLOCK(hi2s); + return errorcode; + } + + /* Check if the I2S Rx request is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + /* Enable Rx DMA Request */ + SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN); + } + + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + + /* Start the transfer */ + SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); + + __HAL_UNLOCK(hi2s); + return errorcode; +} + +/** + * @brief Pauses the audio DMA Stream/Channel playing from the Media. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) +{ + /* Process Locked */ + __HAL_LOCK(hi2s); + + uint32_t tickstart; + + /* Get tick */ + tickstart = HAL_GetTick(); + + + /* Check if the I2S peripheral is in master mode */ + if (IS_I2S_MASTER(hi2s->Init.Mode)) + { + /* Check if there is a transfer on-going */ + if (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) == 0UL) + { + /* Set error code to no on going transfer */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NO_OGT); + hi2s->State = HAL_I2S_STATE_READY; + + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSUSP); + + while (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) != 0UL) + { + if ((((HAL_GetTick() - tickstart) >= I2S_TIMEOUT) && (I2S_TIMEOUT != HAL_MAX_DELAY)) || (I2S_TIMEOUT == 0U)) + { + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + hi2s->State = HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; + } + else + { + /* Set error code to not supported */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NOT_SUPPORTED); + hi2s->State = HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_ERROR; + } +} + +/** + * @brief Resumes the audio DMA Stream/Channel playing from the Media. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) +{ + /* Process Locked */ + __HAL_LOCK(hi2s); + + if (hi2s->State != HAL_I2S_STATE_READY) + { + hi2s->State = HAL_I2S_STATE_READY; + + __HAL_UNLOCK(hi2s); + return HAL_ERROR; + } + + /* Set state and reset error code */ + hi2s->State = HAL_I2S_STATE_BUSY; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + + /* Start the transfer */ + SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_OK; +} + +/** + * @brief Stops the audio DMA Stream/Channel playing from the Media. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + /* The Lock is not implemented on this API to allow the user application + to call the HAL I2S API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() + when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() + */ + + /* Disable the I2S Tx/Rx DMA requests */ + CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); + CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN); + + /* Abort the I2S DMA tx Stream/Channel */ + if (hi2s->hdmatx != NULL) + { + /* Disable the I2S DMA tx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Abort the I2S DMA rx Stream/Channel */ + if (hi2s->hdmarx != NULL) + { + /* Disable the I2S DMA rx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + hi2s->State = HAL_I2S_STATE_READY; + + return errorcode; +} + +/** + * @brief This function handles I2S interrupt request. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) +{ + uint32_t i2sier = hi2s->Instance->IER; + uint32_t i2ssr = hi2s->Instance->SR; + uint32_t trigger = i2sier & i2ssr; + + if (hi2s->State == HAL_I2S_STATE_BUSY_RX) + { + /* I2S in mode Receiver ------------------------------------------------*/ + if (HAL_IS_BIT_SET(trigger, I2S_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_OVR)) + { + hi2s->RxISR(hi2s); + } + + /* I2S Overrun error interrupt occurred -------------------------------------*/ + if (HAL_IS_BIT_SET(trigger, I2S_FLAG_OVR)) + { + /* Disable RXP and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR)); + + /* Clear Overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } + + if (hi2s->State == HAL_I2S_STATE_BUSY_TX) + { + /* I2S in mode Transmitter -----------------------------------------------*/ + if (HAL_IS_BIT_SET(trigger, I2S_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_UDR)) + { + hi2s->TxISR(hi2s); + } + + /* I2S Underrun error interrupt occurred --------------------------------*/ + if (HAL_IS_BIT_SET(trigger, I2S_FLAG_UDR)) + { + /* Disable TXP and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR)); + + /* Clear Underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } + if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) + { + /* I2S in mode Transmitter -----------------------------------------------*/ + if (HAL_IS_BIT_SET(trigger, I2S_FLAG_DXP)) + { + hi2s->TxISR(hi2s); + hi2s->RxISR(hi2s); + } + /* I2S in mode Receiver ------------------------------------------------*/ + if (HAL_IS_BIT_SET(trigger, I2S_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_DXP)) + { + hi2s->RxISR(hi2s); + } + /* I2S in mode Transmitter -----------------------------------------------*/ + if (HAL_IS_BIT_SET(trigger, I2S_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_DXP)) + { + hi2s->TxISR(hi2s); + } + + /* I2S Underrun error interrupt occurred --------------------------------*/ + if (HAL_IS_BIT_SET(trigger, I2S_FLAG_UDR)) + { + /* Disable TXP, RXP and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_ERR)); + + /* Clear Underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + + /* I2S Overrun error interrupt occurred -------------------------------------*/ + if (HAL_IS_BIT_SET(trigger, I2S_FLAG_OVR)) + { + /* Disable TXP, RXP and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_ERR)); + + /* Clear Overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Tx Transfer Half completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Transfer completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer half completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer half completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2S error callbacks + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2s); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I2S_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2S state + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL state + */ +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s) +{ + return hi2s->State; +} + +/** + * @brief Return the I2S error code + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval I2S Error Code + */ +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s) +{ + return hi2s->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2S_Private_Functions + * @{ + */ +/** + * @brief DMA I2S transmit process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* if DMA is configured in DMA_NORMAL Mode */ + if (hdma->Init.Mode == DMA_NORMAL) + { + /* Disable Tx DMA Request */ + CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); + + hi2s->TxXferCount = (uint16_t) 0UL; + hi2s->State = HAL_I2S_STATE_READY; + } + /* Call user Tx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) + hi2s->TxCpltCallback(hi2s); +#else + HAL_I2S_TxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S transmit process half complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Call user Tx half complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) + hi2s->TxHalfCpltCallback(hi2s); +#else + HAL_I2S_TxHalfCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S receive process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* if DMA is configured in DMA_NORMAL Mode */ + if (hdma->Init.Mode == DMA_NORMAL) + { + /* Disable Rx DMA Request */ + CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN); + hi2s->RxXferCount = (uint16_t)0UL; + hi2s->State = HAL_I2S_STATE_READY; + } + /* Call user Rx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) + hi2s->RxCpltCallback(hi2s); +#else + HAL_I2S_RxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S receive process half complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Call user Rx half complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) + hi2s->RxHalfCpltCallback(hi2s); +#else + HAL_I2S_RxHalfCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S transmit receive process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* if DMA is configured in DMA_NORMAL Mode */ + if (hdma->Init.Mode == DMA_NORMAL) + { + /* Disable Tx DMA Request */ + CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); + hi2s->TxXferCount = (uint16_t) 0UL; + + /* Disable Rx DMA Request */ + CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN); + hi2s->RxXferCount = (uint16_t)0UL; + + /* Updated HAL State */ + hi2s->State = HAL_I2S_STATE_READY; + } + + /* Call user TxRx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxRxCpltCallback(hi2s); +#else + HAL_I2SEx_TxRxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S transmit receive process half complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma) +{ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Call user TxRx Half complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) + hi2s->TxRxHalfCpltCallback(hi2s); +#else + HAL_I2SEx_TxRxHalfCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA I2S communication error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void I2S_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable Rx and Tx DMA Request */ + CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN)); + hi2s->TxXferCount = (uint16_t) 0UL; + hi2s->RxXferCount = (uint16_t) 0UL; + + hi2s->State = HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + /* Call user error callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) + hi2s->ErrorCallback(hi2s); +#else + HAL_I2S_ErrorCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +} + +/** + * @brief Manage the transmission 16-bit in Interrupt context + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s) +{ + /* Transmit data */ +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR)); + + *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr); +#else + *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr); +#endif /* __GNUC__ */ + hi2s->pTxBuffPtr++; + hi2s->TxXferCount--; + + if (hi2s->TxXferCount == 0UL) + { + /* Disable TXP and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR)); + + if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX)) + { + hi2s->State = HAL_I2S_STATE_READY; + + /* Call user Tx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) + hi2s->TxCpltCallback(hi2s); +#else + HAL_I2S_TxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Manage the transmission 32-bit in Interrupt context + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s) +{ + /* Transmit data */ + hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr); + hi2s->pTxBuffPtr += 2; + hi2s->TxXferCount--; + + if (hi2s->TxXferCount == 0UL) + { + /* Disable TXP and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR)); + + if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX)) + { + hi2s->State = HAL_I2S_STATE_READY; + + /* Call user Tx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) + hi2s->TxCpltCallback(hi2s); +#else + HAL_I2S_TxCpltCallback(hi2s); +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Manage the reception 16-bit in Interrupt context + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s) +{ + /* Receive data */ +#if defined (__GNUC__) + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR)); + + *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR); +#endif /* __GNUC__ */ + hi2s->pRxBuffPtr++; + hi2s->RxXferCount--; + + if (hi2s->RxXferCount == 0UL) + { + if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode)) + { + /* Disable TXP, RXP, DXP, ERR interrupts */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_ERR)); + } + else + { + /* Disable RXP and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR)); + } + + hi2s->State = HAL_I2S_STATE_READY; + /* Call user Rx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) + if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode)) + { + hi2s->TxRxCpltCallback(hi2s); + } + else + { + hi2s->RxCpltCallback(hi2s); + } +#else + if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode)) + { + HAL_I2SEx_TxRxCpltCallback(hi2s); + } + else + { + HAL_I2S_RxCpltCallback(hi2s); + } +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Manage the reception 32-bit in Interrupt context + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval None + */ +static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s) +{ + /* Receive data */ + *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR; + hi2s->pRxBuffPtr += 2; + hi2s->RxXferCount--; + + if (hi2s->RxXferCount == 0UL) + { + if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode)) + { + /* Disable TXP, RXP, DXP, ERR interrupts */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_ERR)); + } + else + { + /* Disable RXP and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR)); + } + + hi2s->State = HAL_I2S_STATE_READY; + /* Call user Rx complete callback */ +#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) + if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode)) + { + hi2s->TxRxCpltCallback(hi2s); + } + else + { + hi2s->RxCpltCallback(hi2s); + } +#else + if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode)) + { + HAL_I2SEx_TxRxCpltCallback(hi2s); + } + else + { + HAL_I2S_RxCpltCallback(hi2s); + } +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } +} + +/** + * @brief This function handles I2S Communication Timeout. + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Tickstart Tick start value + * @param Timeout Duration of the timeout + * @retval HAL status + */ +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set to status*/ + while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0UL)) + { + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_I2S_MODULE_ENABLED */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i2s_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i2s_ex.c new file mode 100644 index 00000000000..3dba98a897d --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i2s_ex.c @@ -0,0 +1,31 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_i2s_ex.c + * @author MCD Application Team + * @brief I2S HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2S extension peripheral: + * + Extension features Functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** + ****************************************************************************** + ===== I2S FULL DUPLEX FEATURE ===== + I2S Full Duplex APIs are available in stm32h7rsxx_hal_i2s.c/.h + ****************************************************************************** + */ + + + + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i3c.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i3c.c new file mode 100644 index 00000000000..ace4f5f7f4b --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_i3c.c @@ -0,0 +1,9623 @@ +/** + ********************************************************************************************************************** + * @file stm32h7rsxx_hal_i3c.c + * @author MCD Application Team + * @brief I3C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Improvement Inter Integrated Circuit (I3C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + @verbatim + ====================================================================================================================== + ##### How to use this driver ##### + ====================================================================================================================== + [..] + The I3C HAL driver can be used as follows: + + (#) Declare a I3C_HandleTypeDef handle structure, for example: + I3C_HandleTypeDef hi3c; + + (#) Declare a I3C_XferTypeDef transfer descriptor structure, for example: + I3C_XferTypeDef ContextBuffers; + + (#)Initialize the I3C low level resources by implementing the HAL_I3C_MspInit() API: + (##) Enable the I3Cx interface clock + (##) I3C pins configuration + (+++) Enable the clock for the I3C GPIOs + (+++) Configure I3C pins as alternate function push-pull with no-pull + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I3Cx interrupt priority + (+++) Enable the NVIC I3C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for + the Command Common Code (CCC) management channel + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit channel + (+++) Declare a DMA_HandleTypeDef handle structure for + the receive channel + (+++) Declare a DMA_HandleTypeDef handle structure for + the status channel + (+++) Enable the DMAx interface clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Command Common Code (CCC) channel + (+++) Configure the DMA Tx channel + (+++) Configure the DMA Rx channel + (+++) Configure the DMA Status channel + (+++) Associate the initialized DMA handle to the hi3c DMA CCC, Tx, Rx or Status handle as necessary + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA CCC, Tx, Rx or Status instance + + (#) Configure the HAL I3C Communication Mode as Controller or Target in the hi3c Init structure. + + (#) Configure the Controller Communication Bus characterics for Controller mode. + This mean, configure the parameters SDAHoldTime, WaitTime, SCLPPLowDuration, + SCLI3CHighDuration, SCLODLowDuration, SCLI2CHighDuration, BusFreeDuration, + BusIdleDuration in the LL_I3C_CtrlBusConfTypeDef structure through h3c Init structure. + + (#) Configure the Target Communication Bus characterics for Target mode. + This mean, configure the parameter BusAvailableDuration in the LL_I3C_TgtBusConfTypeDef structure + through h3c Init structure. + + All these parameters for Controller or Target can be configured directly in user code or + by using CubeMx generation. + To help the computation of the different parameters, the recommendation is to use CubeMx. + + Those parameters can be modified after the hi3c initialization by using + HAL_I3C_Ctrl_BusCharacteristicConfig() for controller and + HAL_I3C_Tgt_BusCharacteristicConfig() for target. + + (#) Initialize the I3C registers by calling the HAL_I3C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I3C_MspInit(&hi3c) API. + + (#) Configure the different FIFO parameters in I3C_FifoConfTypeDef structure as RxFifoThreshold, TxFifoThreshold + for Controller or Target mode. + And enable/disable the Control or Status FIFO only for Controller Mode. + Use HAL_I3C_SetConfigFifo() function to finalize the configuration, and HAL_I3C_GetConfigFifo() to retrieve + FIFO configuration. + Possibility to clear the FIFO configuration by using HAL_I3C_ClearConfigFifo() which reset the configuration + FIFO to their default hardware value + + (#) Configure the different additional Controller configuration in I3C_CtrlConfTypeDef structure as DynamicAddr, + StallTime, HotJoinAllowed, ACKStallState, CCCStallState, TxStallState, RxStallState, HighKeeperSDA. + Use HAL_I3C_Ctrl_Config() function to finalize the Controller configuration. + + (#) Configure the different additional Target configuration in I3C_TgtConfTypeDef structure as Identifier, + MIPIIdentifier, CtrlRoleRequest, HotJoinRequest, IBIRequest, IBIPayload, IBIPayloadSize, MaxReadDataSize, + MaxWriteDataSize, CtrlCapability, GroupAddrCapability, DataTurnAroundDuration, MaxReadTurnAround, + MaxDataSpeed, MaxSpeedLimitation, HandOffActivityState, HandOffDelay, PendingReadMDB. + Use HAL_I3C_Tgt_Config() function to finalize the Target configuration. + + (#) Before initiate any IO operation, the application must launch an assignment of the different + Target dynamic address by using HAL_I3C_Ctrl_DynAddrAssign() in polling mode or + HAL_I3C_Ctrl_DynAddrAssign_IT() in interrupt mode. + This procedure is named Enter Dynamic Address Assignment (ENTDAA CCC command). + For the initiation of ENTDAA procedure from the controller, each target connected and powered on the I3C bus + must repond to this particular Command Common Code by sending its proper Payload (a amount of 48bits which + contain the target characteristics) + Each time a target responds to ENTDAA sequence, the application is informed through + HAL_I3C_TgtReqDynamicAddrCallback() of the reception of the target paylaod. + And then application must send a associated dynamic address through HAL_I3C_Ctrl_SetDynAddr(). + This procedure in loop automatically in hardware side until a target respond to repeated ENTDAA sequence. + The application is informed of the end of the procedure at reception of HAL_I3C_CtrlDAACpltCallback(). + Then application can easily retrieve ENTDAA payload information through HAL_I3C_Get_ENTDAA_Payload_Info() + function. + At the end of procedure, the function HAL_I3C_Ctrl_ConfigBusDevices() must be called to store in hardware + register part the target capabilities as Dynamic address, IBI support with or without additional data byte, + Controller role request support, Controller stop transfer after IBI through I3C_DeviceConfTypeDef structure. + + (#) Other action to be done, before initiate any IO operation, the application must prepare the different frame + descriptor with its associated buffer allocation in their side. + Configure the different information related to CCC transfer through I3C_CCCTypeDef structure + Configure the different information related to Private or I2C transfer through I3C_PrivateTypeDef structure + Configure the different buffer pointers and associated size needed for the driver communication + through I3C_XferTypeDef structure + The I3C_XferTypeDef structure contains different parameters about Control, Status buffer, + and Transmit and Receive buffer. + Use HAL_I3C_AddDescToFrame() function each time application add a descriptor in the frame before call + an IO operation interface + One element of the frame descriptor correspond to one frame to manage through IO operation. + + (#) To check if I3C target device is ready for communication, use the function HAL_I3C_Ctrl_IsDeviceI3C_Ready() + + (#) To check if I2C target device is ready for communication, use the function HAL_I3C_Ctrl_IsDeviceI2C_Ready() + + (#) For I3C IO operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Activate asynchronous event in controller or target mode a Common Command Code in a broadcast + or a direct communication in blocking mode using HAL_I3C_Ctrl_TransmitCCC() + (+) Transmit in controller mode a Common Command Code in a broadcast or a direct communication in blocking mode + using HAL_I3C_Ctrl_TransmitCCC() + (+) Receive in controller mode a Common Command Code in a direct communication in blocking mode + using HAL_I3C_Ctrl_ReceiveCCC() + (+) Transmit in controller mode an amount of private data in an I3C or an I2C communication in blocking mode + using HAL_I3C_Ctrl_Transmit() + (+) Receive in controller mode an amount of private data in an I3C or an I2C communication in blocking mode + using HAL_I3C_Ctrl_Receive() + (+) Transmit in target mode an amount of private data in an I3C communication in blocking mode + using HAL_I3C_Tgt_Transmit() + (+) Receive in target mode an amount of private data in an I3C communication in blocking mode + using HAL_I3C_Tgt_Receive() + (+) At the end of a transfer, the different FIFO can be flushed if necessary by using HAL_I3C_FlushAllFifo() for + flush all the FIFO, or flush individually y using HAL_I3C_FlushTxFifo(), HAL_I3C_FlushRxFifo(), + HAL_I3C_FlushControlFifo(), HAL_I3C_FlushStatusFifo(). + (+) Request a HotJoin in target mode in blocking mode using HAL_I3C_Tgt_HotJoinReq() + (+) Request a In Band Interrupt in target mode in blocking mode using HAL_I3C_Tgt_IBIReq() + (+) Request a Controller Role in target mode in blocking mode using HAL_I3C_Tgt_ControlRoleReq() + + + *** DMA and Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in controller mode a Common Command Code in a broadcast or a direct communication in non-blocking + mode using HAL_I3C_Ctrl_TransmitCCC_IT() or HAL_I3C_Ctrl_TransmitCCC_DMA() + (+) At transmission end of transfer, HAL_I3C_CtrlTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I3C_CtrlTxCpltCallback() + (+) Receive in controller mode a Common Command Code in a direct communication in non-blocking + mode using HAL_I3C_Ctrl_ReceiveCCC_IT() or HAL_I3C_Ctrl_ReceiveCCC_DMA() + (+) At reception end of transfer, HAL_I3C_CtrlRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I3C_CtrlRxCpltCallback() + (+) Transmit in controller mode an amount of private data in an I3C or an I2C communication in non-blocking mode + using HAL_I3C_Ctrl_Transmit_IT() or HAL_I3C_Ctrl_Transmit_DMA() + (+) At transmission end of transfer, HAL_I3C_CtrlTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I3C_CtrlTxCpltCallback() + (+) Receive in controller mode an amount of private data in an I3C or an I2C communication in non-blocking mode + using HAL_I3C_Ctrl_Receive_IT() or HAL_I3C_Ctrl_Receive_DMA() + (+) At reception end of transfer, HAL_I3C_CtrlRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I3C_CtrlRxCpltCallback() + (+) Transfer in multiple direction (transmit/receive) in controller mode a Common Command Code in a direct + communication or an amount of private data in an I2C or I3C communication in non-blocking mode using + HAL_I3C_Ctrl_MultipleTransfer_IT() or HAL_I3C_Ctrl_MultipleTransfer_DMA() + (+) At the end of transfer, HAL_I3C_CtrlMultipleXferCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I3C_CtrlMultipleXferCpltCallback() + (+) Transmit in target mode an amount of private data in an I3C communication in non-blocking mode + using HAL_I3C_Tgt_Transmit_IT() or HAL_I3C_Tgt_Transmit_DMA() + (+) At transmission end of transfer, HAL_I3C_TgtTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I3C_TgtTxCpltCallback() + (+) Receive in target mode an amount of private data in an I3C communication in non-blocking mode + using HAL_I3C_Tgt_Receive_IT() or HAL_I3C_Tgt_Receive_DMA() + (+) At reception end of transfer, HAL_I3C_TgtRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I3C_TgtRxCpltCallback() + (+) To treat asynchronous event, HAL_I3C_ActivateNotification() or HAL_I3C_DeactivateNotification() function is + used for enable or disable one or more notification related to specific asynchronous event. + Each time one or more event detected by hardware the associated HAL_I3C_NotifyCallback() is executed + and users can add their own code by customization of function pointer HAL_I3C_NotifyCallback(). + Then application can easily retrieve some specific associated event data through HAL_I3C_GetCCCInfo() function + (+) At the end of a transfer, the different FIFO can be flushed if necessary by using HAL_I3C_FlushAllFifo() for + flush all the FIFO, or flush individually y using HAL_I3C_FlushTxFifo(), HAL_I3C_FlushRxFifo(), + HAL_I3C_FlushControlFifo(), HAL_I3C_FlushStatusFifo(). + (+) Request a HotJoin in target mode in non-blocking mode using HAL_I3C_Tgt_HotJoinReq_IT + (+) At completion, HAL_I3C_TgtHotJoinCallback() is executed and users can + add their own code by customization of function pointer HAL_I3C_TgtHotJoinCallback() + (+) Request an In Band Interrupt in target mode in non-blocking mode using HAL_I3C_Tgt_IBIReq_IT() + (+) At completion, HAL_I3C_NotifyCallback() is executed and users can + add their own code by customization of function pointer HAL_I3C_NotifyCallback() + (+) Request a Controller Role in target mode in non-blocking mode using HAL_I3C_Tgt_ControlRoleReq_IT() + (+) At completion, HAL_I3C_NotifyCallback() is executed and users can + add their own code by customization of function pointer HAL_I3C_NotifyCallback() + (+) To manage the wakeup capability, HAL_I3C_ActivateNotification() or HAL_I3C_DeactivateNotification() function + is used for enable or disable Wake Up interrupt. + At wakeup detection the associated HAL_I3C_NotifyCallback() is executed. + (+) In case of transfer Error, HAL_I3C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I3C_ErrorCallback() + (+) Abort an I3C process communication with Interrupt using HAL_I3C_Abort_IT() + (+) End of abort process, HAL_I3C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I3C_AbortCpltCallback() + + + *** I3C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I3C HAL driver. + + (+) __HAL_I3C_ENABLE: Enable the I3C peripheral + (+) __HAL_I3C_DISABLE: Disable the I3C peripheral + (+) __HAL_I3C_RESET_HANDLE_STATE: Reset the I3C handle state + (+) __HAL_I3C_GET_FLAG: Check whether the specified I3C flag is set or not + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I3C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I3C_RegisterCallback() or HAL_I3C_RegisterNotifyCallback() + or HAL_I3C_RegisterTgtReqDynamicAddrCallback() or HAL_I3C_RegisterTgtHotJoinCallback() + to register an interrupt callback. + [..] + Function HAL_I3C_RegisterCallback() allows to register following callbacks: + (+) CtrlTxCpltCallback : callback for Controller transmission CCC, I3C private or I2C end of transfer. + (+) CtrlRxCpltCallback : callback for Controller reception CCC, I3C private or I2C end of transfer. + (+) CtrlMultipleXferCpltCallback : callback for Controller multiple Direct CCC, I3C private or I2C + end of transfer. + (+) CtrlDAACpltCallback : callback for Controller Enter Dynamic Address Assignment end of transfer. + (+) TgtTxCpltCallback : callback for Target transmission I3C private end of transfer. + (+) TgtRxCpltCallback : callback for Target reception I3C private end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback NotifyCallback + use dedicated register callbacks : HAL_I3C_RegisterNotifyCallback(). + [..] + For specific callback TgtReqDynamicAddrCallback + use dedicated register callbacks : HAL_I3C_RegisterTgtReqDynamicAddrCallback(). + [..] + For specific callback TgtHotJoinCallback + use dedicated register callbacks : HAL_I3C_RegisterTgtHotJoinCallback(). + [..] + Use function HAL_I3C_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I3C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) CtrlTxCpltCallback : callback for Controller transmission CCC, I3C private or I2C end of transfer. + (+) CtrlRxCpltCallback : callback for Controller reception CCC, I3C private or I2C end of transfer. + (+) CtrlMultipleXferCpltCallback : callback for Controller multiple Direct CCC, I3C private or I2C + end of transfer. + (+) CtrlDAACpltCallback : callback for Controller Enter Dynamic Address Assignment end of transfer. + (+) TgtTxCpltCallback : callback for Target transmission I3C private end of transfer. + (+) TgtRxCpltCallback : callback for Target reception I3C private end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + (+) NotifyCallback : callback for Controller and Target notification process. + (+) TgtReqDynamicAddrCallback : callback for controller application + when a target sent its payload to the controller during Dynamic Address Assignment process. + (+) TgtHotJoinCallback : callback for Target Hotjoin completion process. + [..] + By default, after the HAL_I3C_Init() and when the state is HAL_I3C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I3C_CtrlTxCpltCallback(), HAL_I3C_CtrlRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I3C_Init()/ HAL_I3C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I3C_Init()/ HAL_I3C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in HAL_I3C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I3C_STATE_READY or HAL_I3C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I3C_RegisterCallback() before calling HAL_I3C_DeInit() + or HAL_I3C_Init() function. + [..] + When the compilation flag USE_HAL_I3C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the I3C HAL driver header file for more useful macros + + @endverbatim + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup I3C I3C + * @brief I3C HAL module driver + * @{ + */ + +#ifdef HAL_I3C_MODULE_ENABLED + +/* Private typedef ---------------------------------------------------------------------------------------------------*/ +/* Private define ----------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_Private_Define I3C Private Define + * @{ + */ + +/* Private define to centralize the enable/disable of Interrupts */ +#define I3C_XFER_LISTEN_IT (0x00000001U) +#define I3C_XFER_TARGET_TX_IT (0x00000002U) +#define I3C_XFER_TARGET_RX_IT (0x00000004U) +#define I3C_XFER_DMA (0x00000008U) +#define I3C_XFER_TARGET_CTRLROLE (0x00000010U) +#define I3C_XFER_TARGET_HOTJOIN (0x00000020U) +#define I3C_XFER_TARGET_IBI (0x00000040U) +#define I3C_XFER_CONTROLLER_TX_IT (0x00000080U) +#define I3C_XFER_CONTROLLER_RX_IT (0x00000100U) +#define I3C_XFER_CONTROLLER_RX_CCC_IT (0x00000400U) +#define I3C_XFER_CONTROLLER_DAA_IT (0x00001000U) + +/* Private defines for control buffer prior preparation */ +#define I3C_OPERATION_TYPE_MASK (0x78000000U) +#define I3C_RESTART_STOP_MASK (0x80000000U) +#define I3C_ARBITRATION_HEADER_MASK (0x00000004U) +#define I3C_DEFINE_BYTE_MASK (0x00000001U) + +/* Private define for CCC command */ +#define I3C_BROADCAST_RSTDAA (0x00000006U) +#define I3C_BROADCAST_ENTDAA (0x00000007U) + +/* Private define to split ENTDAA payload */ +#define I3C_DCR_IN_PAYLOAD_SHIFT 56 +#define I3C_PID_IN_PAYLOAD_MASK 0xFFFFFFFFFFFFU + +/* Private define to split PID */ +/* Bits[47:33]: MIPI Manufacturer ID */ +#define I3C_MIPIMID_PID_SHIFT 33 +#define I3C_MIPIMID_PID_MASK 0x7FFFU + +/* Bit[32]: Provisioned ID Type Selector */ +#define I3C_IDTSEL_PID_SHIFT 32 +#define I3C_IDTSEL_PID_MASK 0x01U + +/* Bits[31:16]: Part ID */ +#define I3C_PART_ID_PID_SHIFT 16 +#define I3C_PART_ID_PID_MASK 0xFFFFU + +/* Bits[15:12]: MIPI Instance ID */ +#define I3C_MIPIID_PID_SHIFT 12 +#define I3C_MIPIID_PID_MASK 0xFU +/** + * @} + */ + +/* Private macro -----------------------------------------------------------------------------------------------------*/ + +/** @brief Get Provisioned ID in payload (64bits) receive during ENTDAA procedure. + * @param __PAYLOAD__ specifies the Device Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFFFFFF. + * @retval The value of PID Return value between Min_Data=0x00 and Max_Data=0xFFFFFFFFFFFF. + */ +#define I3C_GET_PID(__PAYLOAD__) ((uint64_t)(__PAYLOAD__) & I3C_PID_IN_PAYLOAD_MASK) + +/** @brief Get MIPI Manufacturer ID in PID (48bits). + * @param __PID__ specifies the Provisioned ID retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFF. + * @retval The value of MIPI ID Return value between Min_Data=0x00 and Max_Data=0x7FFF. + */ +#define I3C_GET_MIPIMID(__PID__) ((uint16_t)((uint64_t)(__PID__) >> I3C_MIPIMID_PID_SHIFT) & \ + I3C_MIPIMID_PID_MASK) + +/** @brief Get Type Selector in PID (48bits). + * @param __PID__ specifies the Provisioned ID retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFF. + * @retval The value of Type Selector Return 0 or 1. + */ +#define I3C_GET_IDTSEL(__PID__) ((uint8_t)((uint64_t)(__PID__) >> I3C_IDTSEL_PID_SHIFT) & \ + I3C_IDTSEL_PID_MASK) + +/** @brief Get Part ID in PID (48bits). + * @param __PID__ specifies the Provisioned ID retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFF. + * @retval The value of Part ID Return value between Min_Data=0x00 and Max_Data=0xFFFF. + */ +#define I3C_GET_PART_ID(__PID__) ((uint16_t)((uint64_t)(__PID__) >> I3C_PART_ID_PID_SHIFT) & \ + I3C_PART_ID_PID_MASK) + +/** @brief Get Instance ID in PID (48bits). + * @param __PID__ specifies the Provisioned ID retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFF. + * @retval The value of Instance ID Return value between Min_Data=0x00 and Max_Data=0xF. + */ +#define I3C_GET_MIPIID(__PID__) ((uint8_t)((uint64_t)(__PID__) >> I3C_MIPIID_PID_SHIFT) & \ + I3C_MIPIID_PID_MASK) + +/** @brief Get Device Characterics in payload (64bits) receive during ENTDAA procedure. + * @param __PAYLOAD__ specifies the Device Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFFFFFFFF. + * @retval The value of BCR Return value between Min_Data=0x00 and Max_Data=0xFF. + */ +#define I3C_GET_DCR(__PAYLOAD__) (((uint32_t)((uint64_t)(__PAYLOAD__) >> I3C_DCR_IN_PAYLOAD_SHIFT)) & \ + I3C_DCR_DCR) + +/** @brief Get Advanced Capabilities. + * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval The value of advanced capabilities: + * ENABLE: supports optional advanced capabilities. + * DISABLE: not supports optional advanced capabilities. + */ +#define I3C_GET_ADVANCED_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR5_Msk) >> \ + I3C_BCR_BCR5_Pos) == 1U) ? ENABLE : DISABLE) + +/** @brief Get virtual target support. + * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval The value of offline capable: + * ENABLE: is a Virtual Target + * DISABLE: is not a Virtual Target + */ +#define I3C_GET_VIRTUAL_TGT(__BCR__) (((((__BCR__) & I3C_BCR_BCR4_Msk) >> \ + I3C_BCR_BCR4_Pos) == 1U) ? ENABLE : DISABLE) + +/** @brief Get offline capable. + * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval The value of offline capable + * ENABLE: Device will not always respond to I3C Bus commands + * DISABLE: Device will always respond to I3C Bus commands + */ +#define I3C_GET_OFFLINE_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR3_Msk) >> \ + I3C_BCR_BCR3_Pos) == 1U) ? ENABLE : DISABLE) + +/** @brief Get Max data speed limitation. + * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. + * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. + * @retval The value of offline capable: + * ENABLE: Limitation + * DISABLE: No Limitation + */ +#define I3C_GET_MAX_DATA_SPEED_LIMIT(__BCR__) (((((__BCR__) & I3C_BCR_BCR0_Msk) >> \ + I3C_BCR_BCR0_Pos) == 1U) ? ENABLE : DISABLE) + +/** @brief Change uint32_t variable form big endian to little endian. + * @param __DATA__ .uint32_t variable in big endian. + * This parameter must be a number between Min_Data=0x00(uint32_t) and Max_Data=0xFFFFFFFF. + * @retval uint32_t variable in little endian. + */ +#define I3C_BIG_TO_LITTLE_ENDIAN(__DATA__) ((uint32_t)((((__DATA__) & 0xff000000U) >> 24) | \ + (((__DATA__) & 0x00ff0000U) >> 8) | \ + (((__DATA__) & 0x0000ff00U) << 8) | \ + (((__DATA__) & 0x000000ffU) << 24))) + +/* Private variables -------------------------------------------------------------------------------------------------*/ +/** @addtogroup I3C_Private_Variables + * @{ + */ +/* Structure containing address device and message type used for the private function I3C_Ctrl_IsDevice_Ready() */ +typedef struct +{ + uint8_t Address; /* Dynamic or Static target Address */ + uint32_t MessageType; /* Message Type */ + +} I3C_DeviceTypeDef; +/** + * @} + */ + +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +/** @addtogroup I3C_Private_Functions + * @{ + */ +static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Tgt_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Tgt_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +#if defined(HAL_DMA_MODULE_ENABLED) +static HAL_StatusTypeDef I3C_Tgt_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Tgt_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +#endif /* HAL_DMA_MODULE_ENABLED */ +static HAL_StatusTypeDef I3C_Tgt_HotJoin_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Tgt_CtrlRole_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Tgt_IBI_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Tx_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Rx_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +#if defined(HAL_DMA_MODULE_ENABLED) +static HAL_StatusTypeDef I3C_Ctrl_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +#endif /* HAL_DMA_MODULE_ENABLED */ +static HAL_StatusTypeDef I3C_Ctrl_DAA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); +static HAL_StatusTypeDef I3C_Abort_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks); + +static HAL_StatusTypeDef I3C_WaitOnDAAUntilTimeout(I3C_HandleTypeDef *hi3c, uint32_t timeout, uint32_t tickstart); +static HAL_StatusTypeDef I3C_WaitOnFlagUntilTimeout(I3C_HandleTypeDef *hi3c, uint32_t flag, FlagStatus flagstatus, + uint32_t timeout, uint32_t tickstart); +static void I3C_TransmitByteTreatment(I3C_HandleTypeDef *hi3c); +static void I3C_TransmitWordTreatment(I3C_HandleTypeDef *hi3c); +static void I3C_ReceiveByteTreatment(I3C_HandleTypeDef *hi3c); +static void I3C_ReceiveWordTreatment(I3C_HandleTypeDef *hi3c); +static void I3C_ControlDataTreatment(I3C_HandleTypeDef *hi3c); +static void I3C_ErrorTreatment(I3C_HandleTypeDef *hi3c); +static void I3C_GetErrorSources(I3C_HandleTypeDef *hi3c); +static void I3C_StateUpdate(I3C_HandleTypeDef *hi3c); +#if defined(HAL_DMA_MODULE_ENABLED) +static void I3C_DMAAbort(DMA_HandleTypeDef *hdma); +static void I3C_DMAControlTransmitCplt(DMA_HandleTypeDef *hdma); +static void I3C_DMADataTransmitCplt(DMA_HandleTypeDef *hdma); +static void I3C_DMADataReceiveCplt(DMA_HandleTypeDef *hdma); +static void I3C_DMAError(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static void I3C_Enable_IRQ(I3C_HandleTypeDef *hi3c, uint32_t InterruptRequest); +static void I3C_Disable_IRQ(I3C_HandleTypeDef *hi3c, uint32_t InterruptRequest); +static HAL_StatusTypeDef I3C_Xfer_PriorPreparation(I3C_HandleTypeDef *hi3c, uint8_t counter, uint32_t option); +static uint32_t I3C_FillTxBuffer_CCC(I3C_HandleTypeDef *hi3c, + uint32_t indexDesc, + uint32_t txSize, + uint32_t txCurrentIndex); +static uint32_t I3C_FillTxBuffer_Private(I3C_HandleTypeDef *hi3c, + uint32_t indexDesc, + uint32_t txSize, + uint32_t txCurrentIndex); +static HAL_StatusTypeDef I3C_ControlBuffer_PriorPreparation(I3C_HandleTypeDef *hi3c, + uint8_t counter, + uint32_t option); +static HAL_StatusTypeDef I3C_Ctrl_IsDevice_Ready(I3C_HandleTypeDef *hi3c, + const I3C_DeviceTypeDef *pDevice, + uint32_t trials, + uint32_t timeout); +static void I3C_TreatErrorCallback(I3C_HandleTypeDef *hi3c); +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @addtogroup I3C_Exported_Functions I3C Exported Functions + * @{ + */ + +/** @defgroup I3C_Exported_Functions_Group1 Initialization and de-initialization functions. + * @brief I3C initialization and de-initialization functions + * +@verbatim + ======================================================================================================================= + ##### Initialization and de-initialization functions ##### + ======================================================================================================================= + [..] This subsection provides a set of functions allowing to initialize and deinitialize the I3Cx peripheral: + + (+) Users must implement HAL_I3C_MspInit() function in which they configure all related peripherals + resources (APB and Kernel CLOCK, GPIO, DMA, IT and NVIC). + + (+) Call the function HAL_I3C_Init() to configure the bus characteristic depends on the device mode + with the selected configuration below: + + (++) Controller mode, Serial source clock wave form configuration: + (+++) SCL push pull low duration + (+++) SCL I3C high duration + (+++) SCL open drain low duration + (+++) SCL I2C high duration + + (++) Controller mode, Bus timing configuration: + (+++) SDA hold time + (+++) Wait time + (+++) Bus free duration + (+++) Bus available duration + + (++) Target mode, Bus timing configuration: + (+++) Bus available duration + + (+) Call the function HAL_I3C_DeInit() to restore the default configuration of the selected I3Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I3C instance by activating the low-level hardware and configuring the bus + * characteristic according to the specified parameters in the I3C_InitTypeDef. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Init(I3C_HandleTypeDef *hi3c) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t waveform_value; + uint32_t timing_value; + + /* Check the I3C handle allocation */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Check the I3C state */ + if (hi3c->State == HAL_I3C_STATE_RESET) + { +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Init the I3C Callback settings */ + /* Legacy weak CtrlTxCpltCallback */ + hi3c->CtrlTxCpltCallback = HAL_I3C_CtrlTxCpltCallback; + /* Legacy weak CtrlRxCpltCallback */ + hi3c->CtrlRxCpltCallback = HAL_I3C_CtrlRxCpltCallback; + /* Legacy weak CtrlMultipleXferCpltCallback */ + hi3c->CtrlMultipleXferCpltCallback = HAL_I3C_CtrlMultipleXferCpltCallback; + /* Legacy weak CtrlDAACpltCallback */ + hi3c->CtrlDAACpltCallback = HAL_I3C_CtrlDAACpltCallback; + /* Legacy weak TgtReqDynamicAddrCallback */ + hi3c->TgtReqDynamicAddrCallback = HAL_I3C_TgtReqDynamicAddrCallback; + /* Legacy weak TgtTxCpltCallback */ + hi3c->TgtTxCpltCallback = HAL_I3C_TgtTxCpltCallback; + /* Legacy weak TgtRxCpltCallback */ + hi3c->TgtRxCpltCallback = HAL_I3C_TgtRxCpltCallback; + /* Legacy weak TgtHotJoinCallback */ + hi3c->TgtHotJoinCallback = HAL_I3C_TgtHotJoinCallback; + /* Legacy weak NotifyCallback */ + hi3c->NotifyCallback = HAL_I3C_NotifyCallback; + /* Legacy weak ErrorCallback */ + hi3c->ErrorCallback = HAL_I3C_ErrorCallback; + /* Legacy weak AbortCpltCallback */ + hi3c->AbortCpltCallback = HAL_I3C_AbortCpltCallback; + + /* Check on the MSP init callback */ + if (hi3c->MspInitCallback == NULL) + { + /* Legacy weak MspInit */ + hi3c->MspInitCallback = HAL_I3C_MspInit; + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi3c->MspInitCallback(hi3c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I3C_MspInit(hi3c); + +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + + /* Update the I3C state to busy */ + hi3c->State = HAL_I3C_STATE_BUSY; + + /* Disable the selected I3C peripheral */ + LL_I3C_Disable(hi3c->Instance); + + /* Check on the I3C mode: initialization depends on the mode */ + if (hi3c->Mode == HAL_I3C_MODE_CONTROLLER) + { + /* Check the parameters */ + assert_param(IS_I3C_SDAHOLDTIME_VALUE(hi3c->Init.CtrlBusCharacteristic.SDAHoldTime)); + assert_param(IS_I3C_WAITTIME_VALUE(hi3c->Init.CtrlBusCharacteristic.WaitTime)); + + /* Set Controller mode */ + LL_I3C_SetMode(hi3c->Instance, LL_I3C_MODE_CONTROLLER); + + /*----------------- SCL signal waveform configuration : I3C timing register 0 (I3C_TIMINGR0) ------------------ */ + /* Set the controller SCL waveform */ + waveform_value = ((uint32_t)hi3c->Init.CtrlBusCharacteristic.SCLPPLowDuration | + ((uint32_t)hi3c->Init.CtrlBusCharacteristic.SCLI3CHighDuration << I3C_TIMINGR0_SCLH_I3C_Pos) | + ((uint32_t)hi3c->Init.CtrlBusCharacteristic.SCLODLowDuration << I3C_TIMINGR0_SCLL_OD_Pos) | + ((uint32_t)hi3c->Init.CtrlBusCharacteristic.SCLI2CHighDuration << I3C_TIMINGR0_SCLH_I2C_Pos)); + + LL_I3C_ConfigClockWaveForm(hi3c->Instance, waveform_value); + + /*------------------ Timing configuration : I3C timing register 1 (I3C_TIMINGR1) ------------------------------ */ + /* Set SDA hold time, activity state, bus free duration and bus available duration */ + timing_value = ((uint32_t)hi3c->Init.CtrlBusCharacteristic.SDAHoldTime | + (uint32_t)hi3c->Init.CtrlBusCharacteristic.WaitTime | + ((uint32_t)hi3c->Init.CtrlBusCharacteristic.BusFreeDuration << I3C_TIMINGR1_FREE_Pos) | + (uint32_t)hi3c->Init.CtrlBusCharacteristic.BusIdleDuration); + + LL_I3C_SetCtrlBusCharacteristic(hi3c->Instance, timing_value); + } + else + { + /* Set target mode */ + LL_I3C_SetMode(hi3c->Instance, LL_I3C_MODE_TARGET); + + /*------------------ Timing configuration : I3C timing register 1 (I3C_TIMINGR1) ------------------------------ */ + /* Set the number of kernel clocks cycles for the bus available condition time */ + LL_I3C_SetAvalTiming(hi3c->Instance, hi3c->Init.TgtBusCharacteristic.BusAvailableDuration); + } + + /* Enable the selected I3C peripheral */ + LL_I3C_Enable(hi3c->Instance); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Update I3C state */ + hi3c->State = HAL_I3C_STATE_READY; + hi3c->PreviousState = HAL_I3C_STATE_READY; + } + + return status; +} + +/** + * @brief DeInitialize the I3C peripheral. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_DeInit(I3C_HandleTypeDef *hi3c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the I3C handle allocation */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + + /* Update the I3C state to busy */ + hi3c->State = HAL_I3C_STATE_BUSY; + + /* Disable the selected I3C peripheral */ + LL_I3C_Disable(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Check on the MSP init callback */ + if (hi3c->MspDeInitCallback == NULL) + { + /* Legacy weak MspDeInit */ + hi3c->MspDeInitCallback = HAL_I3C_MspDeInit; + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi3c->MspDeInitCallback(hi3c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I3C_MspDeInit(hi3c); + +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + + /* Update the I3C Error code, state and mode */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_RESET; + hi3c->PreviousState = HAL_I3C_STATE_RESET; + hi3c->Mode = HAL_I3C_MODE_NONE; + } + + return status; +} + +/** + * @brief Initialize the I3C MSP. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval None + */ +__weak void HAL_I3C_MspInit(I3C_HandleTypeDef *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi3c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I3C_MspInit could be implemented in the user file */ +} + +/** + * @brief DeInitialize the I3C MSP. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval None + */ +__weak void HAL_I3C_MspDeInit(I3C_HandleTypeDef *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi3c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I3C_MspDeInit could be implemented in the user file */ +} +/** + * @} + */ + +/** @defgroup I3C_Exported_Functions_Group2 Interrupt and callback functions. + * @brief I3C interrupt and callback functions. + * +@verbatim + ======================================================================================================================= + ##### Interrupt and callback functions ##### + ======================================================================================================================= + [..] This subsection provides a set of functions allowing to manage callbacks and interrupts request: + + (+) Register/Unregister callback function: + (++) Call the function HAL_I3C_RegisterCallback() to register an I3C user callback. + (++) Call the function HAL_I3C_RegisterNotifyCallback() to register an I3C user notification callback. + (++) Call the function HAL_I3C_RegisterDynamicAddrCallback() to register an I3C user address callback. + (++) Call the function HAL_I3C_RegisterHotJoinCallback() to register an I3C user hot join callback. + (++) Call the function HAL_I3C_UnRegisterCallback() to unregister an I3C user callback. + + (+) Notification management function: + (++) Call the function HAL_I3C_ActivateNotification() to activate the I3C notifications. + (++) Call the function HAL_I3C_DeactivateNotification() to deactivate the I3C notifications. + + (+) Controller callback functions: + (++) Users must implement HAL_I3C_CtrlTxCpltCallback() function when the transmission of private data or + Tx CCC transfer is completed. + (++) Users must implement HAL_I3C_CtrlRxCpltCallback() function when the reception of private data or + Rx CCC transfer is completed. + (++) Users must implement HAL_I3C_CtrlMultipleXferCpltCallback() function when the multiple + transfer of CCC, I3C private or I2C transfer is completed. + (++) Users must implement HAL_I3C_CtrlDAACpltCallback() function when Dynamic Address Assignment + procedure is completed. + (++) Users must implement HAL_I3C_TgtReqDynamicAddrCallback() function in the controller application + when a target sent its payload to the controller during Dynamic Address Assignment procedure. + + (+) Target callback functions: + (++) Users must implement HAL_I3C_TgtTxCpltCallback() function when the transmission of private + data is completed. + (++) Users must implement HAL_I3C_TgtRxCpltCallback() function when the reception of private + data is completed. + (++) Users must implement HAL_I3C_TgtHotJoinCallback() function when a target hot join process + is completed. + + (+) Common callback functions: + (++) Users must implement HAL_I3C_NotifyCallback() function when the device receives + an asynchronous event like IBI, a Hot-join, CCC command for target... + (++) Users must implement HAL_I3C_AbortCpltCallback() function when an abort process is completed. + (++) Users must implement HAL_I3C_ErrorCallback() function when an error is occurred. + + (+) Interrupt and event function: + (++) Call the function HAL_I3C_ER_IRQHandler() in the ISR file to handle I3C error interrupts request. + (++) Call the function HAL_I3C_EV_IRQHandler() in the ISR file to handle I3C event interrupts request. +@endverbatim + * @{ + */ + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User I3C Callback to be used instead of the weak predefined callback. + * @note The HAL_I3C_RegisterCallback() may be called before HAL_I3C_Init() in HAL_I3C_STATE_RESET + * to register callbacks for HAL_I3C_MSPINIT_CB_ID and HAL_I3C_MSPDEINIT_CB_ID + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param callbackID : [IN] ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_I3C_CTRL_TX_COMPLETE_CB_ID + * @arg @ref HAL_I3C_CTRL_RX_COMPLETE_CB_ID + * @arg @ref HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID + * @arg @ref HAL_I3C_CTRL_DAA_COMPLETE_CB_ID + * @arg @ref HAL_I3C_TGT_TX_COMPLETE_CB_ID + * @arg @ref HAL_I3C_TGT_RX_COMPLETE_CB_ID + * @arg @ref HAL_I3C_ERROR_CB_ID + * @arg @ref HAL_I3C_ABORT_CB_ID + * @arg @ref HAL_I3C_MSPINIT_CB_ID + * @arg @ref HAL_I3C_MSPDEINIT_CB_ID + * @param pCallback : [IN] Pointer to the Callback function. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_RegisterCallback(I3C_HandleTypeDef *hi3c, + HAL_I3C_CallbackIDTypeDef callbackID, + pI3C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the I3C handle allocation */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the user callback allocation */ + if (pCallback == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else if (HAL_I3C_STATE_READY == hi3c->State) + { + switch (callbackID) + { + case HAL_I3C_CTRL_TX_COMPLETE_CB_ID : + hi3c->CtrlTxCpltCallback = pCallback; + break; + + case HAL_I3C_CTRL_RX_COMPLETE_CB_ID : + hi3c->CtrlRxCpltCallback = pCallback; + break; + + case HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID : + hi3c->CtrlMultipleXferCpltCallback = pCallback; + break; + + case HAL_I3C_CTRL_DAA_COMPLETE_CB_ID : + hi3c->CtrlDAACpltCallback = pCallback; + break; + + case HAL_I3C_TGT_TX_COMPLETE_CB_ID : + hi3c->TgtTxCpltCallback = pCallback; + break; + + case HAL_I3C_TGT_RX_COMPLETE_CB_ID : + hi3c->TgtRxCpltCallback = pCallback; + break; + + case HAL_I3C_ERROR_CB_ID : + hi3c->ErrorCallback = pCallback; + break; + + case HAL_I3C_ABORT_CB_ID : + hi3c->AbortCpltCallback = pCallback; + break; + + case HAL_I3C_MSPINIT_CB_ID : + hi3c->MspInitCallback = pCallback; + break; + + case HAL_I3C_MSPDEINIT_CB_ID : + hi3c->MspDeInitCallback = pCallback; + break; + + default : + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else if (HAL_I3C_STATE_RESET == hi3c->State) + { + switch (callbackID) + { + case HAL_I3C_MSPINIT_CB_ID : + hi3c->MspInitCallback = pCallback; + break; + + case HAL_I3C_MSPDEINIT_CB_ID : + hi3c->MspDeInitCallback = pCallback; + break; + + default : + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Register a User I3C Notify Callback to be used instead of the weak predefined callback. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param pNotifyCallback : [IN] Pointer to the Callback function. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_RegisterNotifyCallback(I3C_HandleTypeDef *hi3c, pI3C_NotifyCallbackTypeDef pNotifyCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the I3C handle allocation */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the user callback allocation */ + if (pNotifyCallback == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else if (HAL_I3C_STATE_READY == hi3c->State) + { + hi3c->NotifyCallback = pNotifyCallback; + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Register a User I3C dynamic address Callback to be used instead of the weak predefined callback. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param pTgtReqAddrCallback : [IN] Pointer to the Callback function. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_RegisterTgtReqDynamicAddrCallback(I3C_HandleTypeDef *hi3c, + pI3C_TgtReqDynamicAddrCallbackTypeDef pTgtReqAddrCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the I3C handle allocation */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the user callback allocation */ + if (pTgtReqAddrCallback == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else if (HAL_I3C_STATE_READY == hi3c->State) + { + hi3c->TgtReqDynamicAddrCallback = pTgtReqAddrCallback; + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Register a User I3C hot join Callback to be used instead of the weak predefined callback. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param pTgtHotJoinCallback : [IN] Pointer to the Callback function. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_RegisterTgtHotJoinCallback(I3C_HandleTypeDef *hi3c, + pI3C_TgtHotJoinCallbackTypeDef pTgtHotJoinCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the I3C handle allocation */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the user callback allocation */ + if (pTgtHotJoinCallback == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else if (HAL_I3C_STATE_READY == hi3c->State) + { + hi3c->TgtHotJoinCallback = pTgtHotJoinCallback; + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Unregister a user I3C Callback. + * The I3C callback is redirected to the weak predefined callback + * @note The HAL_I3C_UnRegisterCallback() may be called before HAL_I3C_Init() in HAL_I3C_STATE_RESET + * to un-register callbacks for HAL_I3C_MSPINIT_CB_ID and HAL_I3C_MSPDEINIT_CB_ID + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param callbackID : [IN] ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_I3C_CTRL_TX_COMPLETE_CB_ID + * @arg @ref HAL_I3C_CTRL_RX_COMPLETE_CB_ID + * @arg @ref HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID + * @arg @ref HAL_I3C_CTRL_DAA_COMPLETE_CB_ID + * @arg @ref HAL_I3C_TGT_REQ_DYNAMIC_ADDR_CB_ID + * @arg @ref HAL_I3C_TGT_TX_COMPLETE_CB_ID + * @arg @ref HAL_I3C_TGT_RX_COMPLETE_CB_ID + * @arg @ref HAL_I3C_TGT_HOTJOIN_CB_ID + * @arg @ref HAL_I3C_NOTIFY_CB_ID + * @arg @ref HAL_I3C_ERROR_CB_ID + * @arg @ref HAL_I3C_ABORT_CB_ID + * @arg @ref HAL_I3C_MSPINIT_CB_ID + * @arg @ref HAL_I3C_MSPDEINIT_CB_ID + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_UnRegisterCallback(I3C_HandleTypeDef *hi3c, HAL_I3C_CallbackIDTypeDef callbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the I3C handle allocation */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + if (HAL_I3C_STATE_READY == hi3c->State) + { + switch (callbackID) + { + case HAL_I3C_CTRL_TX_COMPLETE_CB_ID : + /* Legacy weak CtrlTxCpltCallback */ + hi3c->CtrlTxCpltCallback = HAL_I3C_CtrlTxCpltCallback; + break; + + case HAL_I3C_CTRL_RX_COMPLETE_CB_ID : + /* Legacy weak CtrlRxCpltCallback */ + hi3c->CtrlRxCpltCallback = HAL_I3C_CtrlRxCpltCallback; + break; + + case HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID : + /* Legacy weak CtrlMultipleXferCpltCallback */ + hi3c->CtrlMultipleXferCpltCallback = HAL_I3C_CtrlMultipleXferCpltCallback; + break; + + case HAL_I3C_CTRL_DAA_COMPLETE_CB_ID : + /* Legacy weak CtrlDAACpltCallback */ + hi3c->CtrlDAACpltCallback = HAL_I3C_CtrlDAACpltCallback; + break; + + case HAL_I3C_TGT_REQ_DYNAMIC_ADDR_CB_ID : + /*Legacy weak TgtReqDynamicAddrCallback */ + hi3c->TgtReqDynamicAddrCallback = HAL_I3C_TgtReqDynamicAddrCallback; + break; + + case HAL_I3C_TGT_TX_COMPLETE_CB_ID : + /* Legacy weak TgtTxCpltCallback */ + hi3c->TgtTxCpltCallback = HAL_I3C_TgtTxCpltCallback; + break; + + case HAL_I3C_TGT_RX_COMPLETE_CB_ID : + /* Legacy weak TgtRxCpltCallback */ + hi3c->TgtRxCpltCallback = HAL_I3C_TgtRxCpltCallback; + break; + + case HAL_I3C_TGT_HOTJOIN_CB_ID : + /* Legacy weak TgtHotJoinCallback */ + hi3c->TgtHotJoinCallback = HAL_I3C_TgtHotJoinCallback; + break; + + case HAL_I3C_NOTIFY_CB_ID : + /* Legacy weak NotifyCallback */ + hi3c->NotifyCallback = HAL_I3C_NotifyCallback; + break; + + case HAL_I3C_ERROR_CB_ID : + /* Legacy weak ErrorCallback */ + hi3c->ErrorCallback = HAL_I3C_ErrorCallback; + break; + + case HAL_I3C_ABORT_CB_ID : + /* Legacy weak AbortCpltCallback */ + hi3c->AbortCpltCallback = HAL_I3C_AbortCpltCallback; + break; + + case HAL_I3C_MSPINIT_CB_ID : + /* Legacy weak MspInit */ + hi3c->MspInitCallback = HAL_I3C_MspInit; + break; + + case HAL_I3C_MSPDEINIT_CB_ID : + /* Legacy weak MspDeInit */ + hi3c->MspDeInitCallback = HAL_I3C_MspDeInit; + break; + + default : + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else if (HAL_I3C_STATE_RESET == hi3c->State) + { + switch (callbackID) + { + case HAL_I3C_MSPINIT_CB_ID : + /* Legacy weak MspInit */ + hi3c->MspInitCallback = HAL_I3C_MspInit; + break; + + case HAL_I3C_MSPDEINIT_CB_ID : + /* Legacy weak MspDeInit */ + hi3c->MspDeInitCallback = HAL_I3C_MspDeInit; + break; + + default : + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + } + + return status; +} +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + +/** + * @brief This function permits to activate the I3C notifications. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param pXferData : [IN/OUT] Pointer to an I3C_XferTypeDef structure that contains the reception buffer to + * retrieve data during broadcast CCC DEFTGTS and DEFGRPA when Target mode only. + * @param interruptMask : [IN] Parameter indicates which interrupts will be enabled. + * This parameter can be any combination of @arg I3C_TARGET_INTERRUPT when + * the I3C is in target mode or a combination of @arg I3C_CONTROLLER_INTERRUPT + * when it is in controller mode. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_ActivateNotification(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, + uint32_t interruptMask) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + assert_param(IS_I3C_INTERRUPTMASK(hi3c->Mode, interruptMask)); + + /* Check the I3C state and mode */ + if ((hi3c->State == HAL_I3C_STATE_RESET) || + ((hi3c->Mode != HAL_I3C_MODE_CONTROLLER) && (hi3c->Mode != HAL_I3C_MODE_TARGET))) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* Check the I3C mode */ + else if ((hi3c->Mode == HAL_I3C_MODE_TARGET) && + ((interruptMask & (HAL_I3C_IT_DEFIE | HAL_I3C_IT_GRPIE)) != 0U) && + (pXferData == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + /* Check the I3C mode */ + if (hi3c->Mode == HAL_I3C_MODE_TARGET) + { + if ((interruptMask & (HAL_I3C_IT_DEFIE | HAL_I3C_IT_GRPIE)) != 0U) + { + hi3c->pXferData = pXferData; + hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size; + + /* Check on the Rx threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment; + } + } + /* Store the target event treatment function */ + hi3c->XferISR = I3C_Tgt_Event_ISR; + } + else + { + /* Store the controller event treatment function */ + hi3c->XferISR = I3C_Ctrl_Event_ISR; + } + + /* Update handle parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_LISTEN; + hi3c->PreviousState = HAL_I3C_STATE_LISTEN; + + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + /* Enable selected notifications */ + I3C_Enable_IRQ(hi3c, (interruptMask | I3C_XFER_LISTEN_IT)); + } + } + + return status; +} + +/** + * @brief This function permits to deactivate the I3C notifications. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param interruptMask : [IN] Parameter indicates which interrupts will be disabled. + * This parameter can be any combination of @arg I3C_TARGET_INTERRUPT when + * the I3C is in target mode or a combination of @arg I3C_CONTROLLER_INTERRUPT + * when it is in controller mode. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_DeactivateNotification(I3C_HandleTypeDef *hi3c, uint32_t interruptMask) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance parameter */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + + /* Check on the State */ + if (hi3c->State == HAL_I3C_STATE_RESET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Disable selected notifications */ + I3C_Disable_IRQ(hi3c, (interruptMask | I3C_XFER_LISTEN_IT)); + + if (READ_REG(hi3c->Instance->IER) == 0U) + { + /* Update the XferISR pointer */ + hi3c->XferISR = NULL; + + /* Update I3C state */ + hi3c->State = HAL_I3C_STATE_READY; + hi3c->PreviousState = HAL_I3C_STATE_READY; + } + } + } + + return status; +} + +/** + * @brief Controller Transmission Complete callback. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval None + */ +__weak void HAL_I3C_CtrlTxCpltCallback(I3C_HandleTypeDef *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi3c); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I3C_CtrlTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Controller Reception Complete callback. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval None + */ +__weak void HAL_I3C_CtrlRxCpltCallback(I3C_HandleTypeDef *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi3c); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I3C_CtrlRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Controller multiple Direct CCC Command, I3C private or I2C transfer Complete callback. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval None + */ +__weak void HAL_I3C_CtrlMultipleXferCpltCallback(I3C_HandleTypeDef *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi3c); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I3C_CtrlMultipleXferCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Controller dynamic address assignment Complete callback. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval None + */ +__weak void HAL_I3C_CtrlDAACpltCallback(I3C_HandleTypeDef *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi3c); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I3C_CtrlDAACpltCallback could be implemented in the user file + */ +} + +/** + * @brief Target Request Dynamic Address callback. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param targetPayload : [IN] Parameter indicates the target payload. + * @retval None + */ +__weak void HAL_I3C_TgtReqDynamicAddrCallback(I3C_HandleTypeDef *hi3c, uint64_t targetPayload) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi3c); + UNUSED(targetPayload); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I3C_TgtReqDynamicAddrCallback could be implemented in the user file + */ +} + +/** + * @brief Target Transmission Complete callback. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval None + */ +__weak void HAL_I3C_TgtTxCpltCallback(I3C_HandleTypeDef *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi3c); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I3C_TgtTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Target Reception Complete callback. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval None + */ +__weak void HAL_I3C_TgtRxCpltCallback(I3C_HandleTypeDef *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi3c); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I3C_TgtRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Target Hot join process Complete callback. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param dynamicAddress : [IN] The returned dynamic address value after the hot join process. + * @retval None + */ +__weak void HAL_I3C_TgtHotJoinCallback(I3C_HandleTypeDef *hi3c, uint8_t dynamicAddress) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi3c); + UNUSED(dynamicAddress); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I3C_TgtHotJoinCallback could be implemented in the user file + */ +} + +/** + * @brief Target/Controller Notification event callback. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param eventId : [IN] Parameter indicates which notification is signaled. + * It can be a combination value of @ref HAL_I3C_Notification_ID_definition. + * @retval None + */ +__weak void HAL_I3C_NotifyCallback(I3C_HandleTypeDef *hi3c, uint32_t eventId) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi3c); + UNUSED(eventId); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I3C_NotifyCallback could be implemented in the user file + */ +} + +/** + * @brief Abort complete callback. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval None + */ +__weak void HAL_I3C_AbortCpltCallback(I3C_HandleTypeDef *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi3c); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I3C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Error callback. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval None + */ +__weak void HAL_I3C_ErrorCallback(I3C_HandleTypeDef *hi3c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi3c); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_I3C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief This function handles I3C error interrupt request. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval None + */ +void HAL_I3C_ER_IRQHandler(I3C_HandleTypeDef *hi3c) +{ + uint32_t it_flag = READ_REG(hi3c->Instance->EVR); + uint32_t it_source = READ_REG(hi3c->Instance->IER); + + /* Check on the error interrupt flag and source */ + if ((I3C_CHECK_FLAG(it_flag, HAL_I3C_FLAG_ERRF) != RESET) && + (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_ERRIE) != RESET)) + { + /* Clear the error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + if (hi3c->State != HAL_I3C_STATE_ABORT) + { + /* Get error sources */ + I3C_GetErrorSources(hi3c); + } + + /* Errors treatment */ + I3C_ErrorTreatment(hi3c); + } +} + +/** + * @brief This function handles I3C event interrupt request. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval None + */ +void HAL_I3C_EV_IRQHandler(I3C_HandleTypeDef *hi3c) /* Derogation MISRAC2012-Rule-8.13 */ +{ + uint32_t it_flags = READ_REG(hi3c->Instance->EVR); + uint32_t it_sources = READ_REG(hi3c->Instance->IER); + + uint32_t it_masks = (uint32_t)(it_flags & it_sources); + + /* I3C events treatment */ + if (hi3c->XferISR != NULL) + { + hi3c->XferISR(hi3c, it_masks); + } +} +/** + * @} + */ + +/** @defgroup I3C_Exported_Functions_Group3 Configuration functions. + * @brief I3C configuration functions. + * +@verbatim + ======================================================================================================================= + ##### Configuration functions ##### + ======================================================================================================================= + [..] This subsection provides a set of functions allowing to configure the I3C instances. + + (+) Call the function HAL_I3C_Ctrl_BusCharacteristicConfig() to modify the controller Bus Characteristics + after initialize the bus through HAL_I3C_Init. + + (+) Call the function HAL_I3C_Tgt_BusCharacteristicConfig() to modify the target Bus Characteristics + after initialize the bus through HAL_I3C_Init. + + (+) Call the function HAL_I3C_SetConfigFifo() to set FIFOs configuration (enabled FIFOs and + threshold level) with the selected parameters in the configuration structure I3C_FifoConfTypeDef. + + (+) Call the function HAL_I3C_Ctrl_Config() to configure the I3C Controller instances with the selected + parameters in the configuration structure I3C_CtrlConfTypeDef. + This function is called only when mode is Controller. + + (+) Call the function HAL_I3C_Tgt_Config() to configure the I3C Target instances with the selected + parameters in the configuration structure I3C_TgtConfTypeDef. + This function is called only when mode is Target. + + (+) Call the function HAL_I3C_Ctrl_ConfigBusDevices() to configure Hardware device characteristics register + with Devices capabilities present on the Bus. + All different characteristics must be fill through structure I3C_DeviceConfTypeDef. + This function is called only when mode is Controller. + + (+) Call the function HAL_I3C_AddDescToFrame() to prepare the full transfer usecase in a transfer descriptor + which contained different buffer pointers and their associated size through I3C_XferTypeDef. + This function must be called before initiate any communication transfer. + [..] + (@) Users must call all above functions after I3C initialization. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the Controller Bus characterics. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pConfig : [IN] Pointer to an LL_I3C_CtrlBusConfTypeDef structure contains controller bus configuration. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_BusCharacteristicConfig(I3C_HandleTypeDef *hi3c, + const LL_I3C_CtrlBusConfTypeDef *pConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t waveform_value; + uint32_t timing_value; + + /* Check the I3C handle allocation */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Check on user parameters */ + if (pConfig == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check the I3C state and mode */ + else if ((hi3c->State != HAL_I3C_STATE_READY) || (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Check the parameters */ + assert_param(IS_I3C_SDAHOLDTIME_VALUE(pConfig->SDAHoldTime)); + assert_param(IS_I3C_WAITTIME_VALUE(pConfig->WaitTime)); + + /* Disable the selected I3C peripheral */ + LL_I3C_Disable(hi3c->Instance); + + /*----------------- SCL signal waveform configuration : I3C timing register 0 (I3C_TIMINGR0) ------------------ */ + /* Set the controller SCL waveform */ + waveform_value = ((uint32_t)pConfig->SCLPPLowDuration | + ((uint32_t)pConfig->SCLI3CHighDuration << I3C_TIMINGR0_SCLH_I3C_Pos) | + ((uint32_t)pConfig->SCLODLowDuration << I3C_TIMINGR0_SCLL_OD_Pos) | + ((uint32_t)pConfig->SCLI2CHighDuration << I3C_TIMINGR0_SCLH_I2C_Pos)); + + LL_I3C_ConfigClockWaveForm(hi3c->Instance, waveform_value); + + /*------------------ Timing configuration : I3C timing register 1 (I3C_TIMINGR1) ------------------------------ */ + /* Set SDA hold time, activity state, bus free duration and bus available duration */ + timing_value = ((uint32_t)pConfig->SDAHoldTime | + (uint32_t)pConfig->WaitTime | + ((uint32_t)pConfig->BusFreeDuration << I3C_TIMINGR1_FREE_Pos) | + (uint32_t)pConfig->BusIdleDuration); + + LL_I3C_SetCtrlBusCharacteristic(hi3c->Instance, timing_value); + + /* Enable the selected I3C peripheral */ + LL_I3C_Enable(hi3c->Instance); + } + } + + return status; +} + +/** + * @brief Configure the target Bus characterics. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pConfig : [IN] Pointer to an LL_I3C_TgtBusConfTypeDef structure contains target bus configuration. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Tgt_BusCharacteristicConfig(I3C_HandleTypeDef *hi3c, + const LL_I3C_TgtBusConfTypeDef *pConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the I3C handle allocation */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check on user parameters */ + if (pConfig == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Check the I3C state and mode */ + if ((hi3c->State != HAL_I3C_STATE_READY) || (hi3c->Mode != HAL_I3C_MODE_TARGET)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Disable the selected I3C peripheral */ + LL_I3C_Disable(hi3c->Instance); + + /*------------------ Timing configuration : I3C timing register 1 (I3C_TIMINGR1) ---------------------------- */ + /* Set the number of kernel clocks cycles for the bus available condition time */ + LL_I3C_SetAvalTiming(hi3c->Instance, pConfig->BusAvailableDuration); + + /* Enable the selected I3C peripheral */ + LL_I3C_Enable(hi3c->Instance); + } + } + } + + return status; +} + +/** + * @brief Set I3C FIFOs configuration. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pConfig : [IN] Pointer to an I3C_FifoConfTypeDef structure contains FIFOs configuration. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_SetConfigFifo(I3C_HandleTypeDef *hi3c, const I3C_FifoConfTypeDef *pConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t cfgr_value; + uint32_t cfgr_mask; + + /* Check the I3C handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check on user parameters */ + if (pConfig == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check the I3C state */ + else if (hi3c->State == HAL_I3C_STATE_RESET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Check configuration parameters */ + assert_param(IS_I3C_TXFIFOTHRESHOLD_VALUE(pConfig->TxFifoThreshold)); + assert_param(IS_I3C_RXFIFOTHRESHOLD_VALUE(pConfig->RxFifoThreshold)); + + /* Set Tx and Rx Fifo threshold */ + cfgr_value = (pConfig->TxFifoThreshold | pConfig->RxFifoThreshold); + cfgr_mask = (I3C_CFGR_TXTHRES | I3C_CFGR_RXTHRES); + + /* Check on the I3C mode: Control and status FIFOs available only with controller mode */ + if (hi3c->Mode == HAL_I3C_MODE_CONTROLLER) + { + /* Check configuration parameters */ + assert_param(IS_I3C_CONTROLFIFOSTATE_VALUE(pConfig->ControlFifo)); + assert_param(IS_I3C_STATUSFIFOSTATE_VALUE(pConfig->StatusFifo)); + + /* Set Control and Status Fifo states */ + cfgr_value |= (pConfig->StatusFifo | pConfig->ControlFifo); + cfgr_mask |= (I3C_CFGR_TMODE | I3C_CFGR_SMODE); + } + + /* Set configuration in the CFGR register */ + MODIFY_REG(hi3c->Instance->CFGR, cfgr_mask, cfgr_value); + } + } + + return status; +} + +/** + * @brief Set I3C controller configuration. + * @note This function is called only when the I3C instance is initialized as controller. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pConfig : [IN] Pointer to an I3C_CtrlConfTypeDef structure that contains controller configuration. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_Config(I3C_HandleTypeDef *hi3c, const I3C_CtrlConfTypeDef *pConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t timing2_value; + uint32_t cfgr_value; + + /* Check the I3C handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Check on user parameters */ + if (pConfig == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check the I3C state and mode */ + else if ((hi3c->State == HAL_I3C_STATE_RESET) || (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Check configuration parameters values */ + assert_param(IS_I3C_DYNAMICADDRESS_VALUE(pConfig->DynamicAddr)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->HighKeeperSDA)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->HotJoinAllowed)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->ACKStallState)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->CCCStallState)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->TxStallState)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->RxStallState)); + + /* Disable the selected I3C peripheral */ + LL_I3C_Disable(hi3c->Instance); + + /* Calculate value to be written in timing register 2 */ + timing2_value = (((uint32_t)pConfig->StallTime << I3C_TIMINGR2_STALL_Pos) | + ((uint32_t)pConfig->ACKStallState << I3C_TIMINGR2_STALLA_Pos) | + ((uint32_t)pConfig->CCCStallState << I3C_TIMINGR2_STALLC_Pos) | + ((uint32_t)pConfig->TxStallState << I3C_TIMINGR2_STALLD_Pos) | + ((uint32_t)pConfig->RxStallState << I3C_TIMINGR2_STALLT_Pos)); + + /* Set value in timing 2 register */ + WRITE_REG(hi3c->Instance->TIMINGR2, timing2_value); + + /* Calculate value to be written in CFGR register */ + cfgr_value = (((uint32_t)pConfig->HighKeeperSDA << I3C_CFGR_HKSDAEN_Pos) | + ((uint32_t)pConfig->HotJoinAllowed << I3C_CFGR_HJACK_Pos)); + + /* Set hot join acknowledge and high keeper values */ + MODIFY_REG(hi3c->Instance->CFGR, I3C_CFGR_HKSDAEN | I3C_CFGR_HJACK, cfgr_value); + + /* Set dynamic address value */ + LL_I3C_SetOwnDynamicAddress(hi3c->Instance, pConfig->DynamicAddr); + + /* Validate the controller dynamic address */ + LL_I3C_EnableOwnDynAddress(hi3c->Instance); + + /* Enable the selected I3C peripheral */ + LL_I3C_Enable(hi3c->Instance); + } + } + + return status; +} + +/** + * @brief Set I3C target configuration. + * @note This function is called only when the I3C instance is initialized as target. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pConfig : [IN] Pointer to an I3C_TgtConfTypeDef structure that contains target configuration. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Tgt_Config(I3C_HandleTypeDef *hi3c, const I3C_TgtConfTypeDef *pConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t getmxdsr_value; + uint32_t maxrlr_value; + uint32_t crccapr_value; + uint32_t bcr_value; + uint32_t devr0_value; + + /* Check the I3C handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Check on user parameters */ + if (pConfig == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check the I3C state and mode */ + else if ((hi3c->State == HAL_I3C_STATE_RESET) || (hi3c->Mode != HAL_I3C_MODE_TARGET)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Check configuration parameters values */ + assert_param(IS_I3C_HANDOFFACTIVITYSTATE_VALUE(pConfig->HandOffActivityState)); + assert_param(IS_I3C_TSCOTIME_VALUE(pConfig->DataTurnAroundDuration)); + assert_param(IS_I3C_MAXSPEEDDATA_VALUE(pConfig->MaxDataSpeed)); + assert_param(IS_I3C_IBIPAYLOADSIZE_VALUE(pConfig->IBIPayloadSize)); + assert_param(IS_I3C_MIPIIDENTIFIER_VALUE(pConfig->MIPIIdentifier)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->HandOffDelay)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->GroupAddrCapability)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->PendingReadMDB)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->IBIPayload)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->MaxSpeedLimitation)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->CtrlCapability)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->IBIRequest)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->CtrlRoleRequest)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->HotJoinRequest)); + + /* Disable the selected I3C peripheral */ + LL_I3C_Disable(hi3c->Instance); + + /* Calculate value to be written in the GETMXDSR register */ + getmxdsr_value = (pConfig->HandOffActivityState | pConfig->MaxDataSpeed | pConfig->DataTurnAroundDuration | + ((uint32_t)pConfig->MaxReadTurnAround << I3C_GETMXDSR_RDTURN_Pos)); + + /* Set value in GETMXDSR register */ + WRITE_REG(hi3c->Instance->GETMXDSR, getmxdsr_value); + + /* Calculate value to be written in MAXRLR register */ + maxrlr_value = (pConfig->IBIPayloadSize | (pConfig->MaxReadDataSize & I3C_MAXRLR_MRL)); + + /* Set payload size and max read data size in MAXRLR register */ + WRITE_REG(hi3c->Instance->MAXRLR, maxrlr_value); + + /* Set max write data size in MAXWLR register */ + LL_I3C_SetMaxWriteLength(hi3c->Instance, pConfig->MaxWriteDataSize); + + /* Set MIPI identifier value in EPIDR register */ + LL_I3C_SetMIPIInstanceID(hi3c->Instance, pConfig->MIPIIdentifier); + + /* Set identifier value in DCR register */ + LL_I3C_SetDeviceCharacteristics(hi3c->Instance, pConfig->Identifier); + + /* Calculate value to be written in CRCCAPR register */ + crccapr_value = (((uint32_t)pConfig->HandOffDelay << I3C_CRCAPR_CAPDHOFF_Pos) | + ((uint32_t)pConfig->GroupAddrCapability << I3C_CRCAPR_CAPGRP_Pos)); + + /* Set hand off dealy and group address capability in CRCCAPR register */ + WRITE_REG(hi3c->Instance->CRCAPR, crccapr_value); + + /* Set pending read MDB notification value in GETCAPR register */ + LL_I3C_SetPendingReadMDB(hi3c->Instance, ((uint32_t)pConfig->PendingReadMDB << I3C_GETCAPR_CAPPEND_Pos)); + + /* Calculate value to be written in BCR register */ + bcr_value = (((uint32_t)pConfig->MaxSpeedLimitation << I3C_BCR_BCR0_Pos) | + ((uint32_t)pConfig->IBIPayload << I3C_BCR_BCR2_Pos) | + ((uint32_t)pConfig->CtrlCapability << I3C_BCR_BCR6_Pos)); + + /* Set control capability, IBI payload support and max speed limitation in BCR register */ + WRITE_REG(hi3c->Instance->BCR, bcr_value); + + /* Calculate value to be written in CFGR register */ + devr0_value = (((uint32_t)pConfig->IBIRequest << I3C_DEVR0_IBIEN_Pos) | + ((uint32_t)pConfig->CtrlRoleRequest << I3C_DEVR0_CREN_Pos) | + ((uint32_t)pConfig->HotJoinRequest << I3C_DEVR0_HJEN_Pos)); + + /* Set IBI request, control role request and hot join request in DEVR0 register */ + MODIFY_REG(hi3c->Instance->DEVR0, (I3C_DEVR0_HJEN | I3C_DEVR0_IBIEN | I3C_DEVR0_CREN), devr0_value); + + /* Enable the selected I3C peripheral */ + LL_I3C_Enable(hi3c->Instance); + } + } + + return status; +} + +/** + * @brief Set I3C bus devices configuration. + * @note This function is called only when the I3C instance is initialized as controller. + * This function can be called by the controller application to help the automatic treatment when target have + * capability of IBI and/or Control-Role. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pDesc : [IN] Pointer to an I3C_DeviceConfTypeDef descriptor that contains the bus devices + * configurations. + * @param nbDevice : [IN] Value specifies the number of devices to be treated. + * This parameter must be a number between Min_Data=1U and Max_Data=4U. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_ConfigBusDevices(I3C_HandleTypeDef *hi3c, + const I3C_DeviceConfTypeDef *pDesc, + uint8_t nbDevice) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t write_value; + + /* Check the I3C handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check on user parameters */ + if (pDesc == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check the I3C state and mode */ + else if ((hi3c->State == HAL_I3C_STATE_RESET) || (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + assert_param(IS_I3C_DEVICE_VALUE(nbDevice)); + + /* Loop on the nbDevice to be treated */ + for (uint32_t index = 0U; index < nbDevice; index++) + { + /* Check configuration parameters values */ + assert_param(IS_I3C_DEVICE_VALUE(pDesc[index].DeviceIndex)); + assert_param(IS_I3C_DYNAMICADDRESS_VALUE(pDesc[index].TargetDynamicAddr)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pDesc[index].IBIAck)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pDesc[index].CtrlRoleReqAck)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pDesc[index].CtrlStopTransfer)); + assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pDesc[index].IBIPayload)); + + /* Set value to be written */ + write_value = (((uint32_t)pDesc[index].TargetDynamicAddr << I3C_DEVRX_DA_Pos) | + ((uint32_t)pDesc[index].IBIAck << I3C_DEVRX_IBIACK_Pos) | + ((uint32_t)pDesc[index].CtrlRoleReqAck << I3C_DEVRX_CRACK_Pos) | + ((uint32_t)pDesc[index].CtrlStopTransfer << I3C_DEVRX_SUSP_Pos) | + ((uint32_t)pDesc[index].IBIPayload << I3C_DEVRX_IBIDEN_Pos)); + + /* Write configuration in the DEVRx register */ + WRITE_REG(hi3c->Instance->DEVRX[(pDesc[index].DeviceIndex - 1U)], write_value); + } + } + } + + return status; +} + +/** + * @brief Add Private or CCC descriptor in the user data transfer descriptor. + * @note This function must be called before initiate any communication transfer. This function help the preparation + * of the full transfer usecase in a transfer descriptor which contained different buffer pointers + * and their associated size through I3C_XferTypeDef. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pCCCDesc : [IN] Pointer to an I3C_CCCTypeDef structure that contains the CCC descriptor information. + * @param pPrivateDesc : [IN] Pointer to an I3C_PrivateTypeDef structure that contains the transfer descriptor. + * @param pXferData : [IN/OUT] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers + * (control buffer, data buffer and status buffer). + * @param nbFrame : [IN] The number of CCC commands or the number of device to treat. + * @param option : [IN] Value indicates the transfer option. It can be one value of @ref I3C_OPTION_DEFINITION + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_AddDescToFrame(I3C_HandleTypeDef *hi3c, + const I3C_CCCTypeDef *pCCCDesc, + const I3C_PrivateTypeDef *pPrivateDesc, + I3C_XferTypeDef *pXferData, + uint8_t nbFrame, + uint32_t option) +{ + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->pCCCDesc = pCCCDesc; + hi3c->pPrivateDesc = pPrivateDesc; + hi3c->pXferData = pXferData; + hi3c->RxXferCount = 0; + hi3c->TxXferCount = 0; + + /* Prepare Direction, and Check on user parameters */ + if (((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_CCC) || + ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_DIRECT)) + { + /* Check on user parameters */ + if ((pCCCDesc == NULL) || + (pXferData == NULL) || + (nbFrame < 1U) || + (((option & (I3C_OPERATION_TYPE_MASK | I3C_DEFINE_BYTE_MASK)) == \ + (LL_I3C_CONTROLLER_MTYPE_DIRECT | I3C_DEFINE_BYTE_MASK)) && (pCCCDesc->CCCBuf.Size == 0U))) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + } + else + { + /* Check on user parameters */ + if ((pPrivateDesc == NULL) || (pXferData == NULL) || (nbFrame <= 0U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + } + + if (status == HAL_OK) + { + /* check on the State */ + if ((handle_state == HAL_I3C_STATE_READY) || (handle_state == HAL_I3C_STATE_LISTEN)) + { + /* I3C control buffer prior preparation */ + if (I3C_ControlBuffer_PriorPreparation(hi3c, nbFrame, option) != HAL_OK) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + + /* I3C Tx Buffer prior preparation, set and check RxCount */ + if (I3C_Xfer_PriorPreparation(hi3c, nbFrame, option) != HAL_OK) + { + status = HAL_ERROR; + } + } + else + { + status = HAL_BUSY; + } + } + } + + return status; +} + +/** + * @} + */ + +/** @defgroup I3C_Exported_Functions_Group4 FIFO Management functions. + * @brief I3C FIFO management functions. + * +@verbatim + ======================================================================================================================= + ##### FIFO Management functions ##### + ======================================================================================================================= + [..] This subsection provides a set of functions allowing to manage I3C FIFOs. + + (+) Call the function HAL_I3C_FlushAllFifo() to flush the content of all used FIFOs (Control, Status, + Tx and Rx FIFO). + (+) Call the function HAL_I3C_FlushTxFifo() to flush only the content of Tx FIFO. + (+) Call the function HAL_I3C_FlushRxFifo() to flush only the content of Rx FIFO. + (+) Call the function HAL_I3C_FlushControlFifo() to flush only the content of Control FIFO. + This function is called only when mode is controller. + (+) Call the function HAL_I3C_FlushStatusFifo() to flush only the content of Status FIFO. + This function is called only when mode is controller. + (+) Call the function HAL_I3C_ClearConfigFifo() to clear the FIFOs configuration and set it to default values. + (+) Call the function HAL_I3C_GetConfigFifo() to get the current FIFOs configuration (enabled FIFOs and + threshold level). + + (+) Users must not call all above functions before I3C initialization. + + (+) Users should call Flush APIs after an end of process, before starting a transfer or in case of bus + failure and error detection. + +@endverbatim + * @{ + */ + +/** + * @brief Flush all I3C FIFOs content. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_FlushAllFifo(I3C_HandleTypeDef *hi3c) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t cfgr_value; + + /* Check the I3C handle allocation */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Check the I3C state */ + if (hi3c->State == HAL_I3C_STATE_RESET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Flush the content of Tx and Rx Fifo */ + cfgr_value = (I3C_CFGR_TXFLUSH | I3C_CFGR_RXFLUSH); + + /* Check on the I3C mode: Control and status FIFOs available only with controller mode */ + if (hi3c->Mode == HAL_I3C_MODE_CONTROLLER) + { + /* Flush the content of Control and Status Fifo */ + cfgr_value = (I3C_CFGR_SFLUSH | I3C_CFGR_CFLUSH); + } + + /* Set configuration in the CFGR register */ + MODIFY_REG(hi3c->Instance->CFGR, cfgr_value, cfgr_value); + } + } + + return status; +} + +/** + * @brief Flush I3C Tx FIFO content. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_FlushTxFifo(I3C_HandleTypeDef *hi3c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the I3C handle allocation */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Check the I3C state */ + if (hi3c->State == HAL_I3C_STATE_RESET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Flush the content of Tx Fifo */ + LL_I3C_RequestTxFIFOFlush(hi3c->Instance); + } + } + + return status; +} + +/** + * @brief Flush I3C Rx FIFO content. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_FlushRxFifo(I3C_HandleTypeDef *hi3c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the I3C handle allocation */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Check the I3C state */ + if (hi3c->State == HAL_I3C_STATE_RESET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Flush the content of Rx Fifo */ + LL_I3C_RequestRxFIFOFlush(hi3c->Instance); + } + } + + return status; +} + +/** + * @brief Flush I3C control FIFO content. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_FlushControlFifo(I3C_HandleTypeDef *hi3c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the I3C handle allocation */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Check the I3C state and mode */ + if ((hi3c->State == HAL_I3C_STATE_RESET) || (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Flush the content of Control Fifo */ + LL_I3C_RequestControlFIFOFlush(hi3c->Instance); + } + } + + return status; +} + +/** + * @brief Flush I3C status FIFO content. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_FlushStatusFifo(I3C_HandleTypeDef *hi3c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the I3C handle allocation */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Check the I3C state and mode */ + if ((hi3c->State == HAL_I3C_STATE_RESET) || (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Flush the content of Control Fifo */ + LL_I3C_RequestStatusFIFOFlush(hi3c->Instance); + } + } + + return status; +} + +/** + * @brief Clear I3C FIFOs configuration and set it to default values. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_ClearConfigFifo(I3C_HandleTypeDef *hi3c) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t cfgr_value; + uint32_t cfgr_mask; + + /* Check the I3C handle allocation */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Check the I3C state */ + if (hi3c->State == HAL_I3C_STATE_RESET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Clear Tx Fifo and Rx Fifo threshold and set it to default value */ + cfgr_value = (LL_I3C_TXFIFO_THRESHOLD_1_4 | LL_I3C_RXFIFO_THRESHOLD_1_4); + cfgr_mask = (I3C_CFGR_TXTHRES | I3C_CFGR_RXTHRES); + + /* Check on the I3C mode: Control and status FIFOs available only with controller mode */ + if (hi3c->Mode == HAL_I3C_MODE_CONTROLLER) + { + /* Disable the status and Control Fifo state */ + cfgr_value |= (HAL_I3C_STATUSFIFO_DISABLE | HAL_I3C_CONTROLFIFO_DISABLE); + cfgr_mask |= (I3C_CFGR_TMODE | I3C_CFGR_SMODE); + } + + /* Set configuration in the CFGR register */ + MODIFY_REG(hi3c->Instance->CFGR, cfgr_mask, cfgr_value); + } + } + + return status; +} + +/** + * @brief Get I3C FIFOs current configuration. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pConfig : [IN/OUT] Pointer to an I3C_FifoConfTypeDef structure that returns current FIFOs configuration. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_GetConfigFifo(I3C_HandleTypeDef *hi3c, I3C_FifoConfTypeDef *pConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the I3C handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Check on user parameters */ + if (pConfig == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check the I3C state */ + else if (hi3c->State == HAL_I3C_STATE_RESET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Get Tx Fifo threshold */ + pConfig->TxFifoThreshold = LL_I3C_GetTxFIFOThreshold(hi3c->Instance); + + /* Get Rx Fifo threshold */ + pConfig->RxFifoThreshold = LL_I3C_GetRxFIFOThreshold(hi3c->Instance); + + /* Get the Control Fifo state */ + pConfig->ControlFifo = (uint32_t)(LL_I3C_IsEnabledControlFIFO(hi3c->Instance) << I3C_CFGR_TMODE_Pos); + + /* Get the status Fifo state */ + pConfig->StatusFifo = (uint32_t)(LL_I3C_IsEnabledStatusFIFO(hi3c->Instance) << I3C_CFGR_SMODE_Pos); + } + } + + return status; +} +/** + * @} + */ + +/** @defgroup I3C_Exported_Functions_Group5 Controller operational functions. + * @brief I3C controller operational functions. + * +@verbatim + ======================================================================================================================= + ##### Controller operational functions ##### + ======================================================================================================================= + [..] This subsection provides a set of functions allowing to manage controller I3C operation. + + (+) Call the function HAL_I3C_Ctrl_TransmitCCC() to transmit direct write or a broadcast + CCC command in polling mode. + (+) Call the function HAL_I3C_Ctrl_TransmitCCC_IT() to transmit direct write or a broadcast + CCC command in interrupt mode. + (+) Call the function HAL_I3C_Ctrl_TransmitCCC_DMA() to transmit direct write or a broadcast + CCC command in DMA mode. + (+) Call the function HAL_I3C_Ctrl_ReceiveCCC() to transmit direct read CCC command in polling mode. + (+) Call the function HAL_I3C_Ctrl_ReceiveCCC_IT() to transmit direct read CCC command in interrupt mode. + (+) Call the function HAL_I3C_Ctrl_ReceiveCCC_DMA() to transmit direct read CCC command in DMA mode. + (+) Call the function HAL_I3C_Ctrl_Transmit() to transmit private data in polling mode. + (+) Call the function HAL_I3C_Ctrl_Transmit_IT() to transmit private data in interrupt mode. + (+) Call the function HAL_I3C_Ctrl_Transmit_DMA() to transmit private data in DMA mode. + (+) Call the function HAL_I3C_Ctrl_Receive() to receive private data in polling mode. + (+) Call the function HAL_I3C_Ctrl_Receive_IT() to receive private data in interrupt mode. + (+) Call the function HAL_I3C_Ctrl_Receive_DMA() to receive private data in DMA mode. + (+) Call the function HAL_I3C_Ctrl_MultipleTransfer_IT() to transfer I3C or I2C private data or CCC command + in multiple direction in interrupt mode. + (+) Call the function HAL_I3C_Ctrl_MultipleTransfer_DMA() to transfer I3C or I2C private data or CCC command + in multiple direction in DMA mode. + (+) Call the function HAL_I3C_Ctrl_DynAddrAssign() to send a broadcast ENTDAA CCC + command in polling mode. + (+) Call the function HAL_I3C_Ctrl_DynAddrAssign_IT() to send a broadcast ENTDAA CCC + command in interrupt mode. + (+) Call the function HAL_I3C_Ctrl_SetDynAddr() to set, asscociate the target dynamic address + during the Dynamic Address Assignment processus. + (+) Call the function HAL_I3C_Ctrl_IsDeviceI3C_Ready() to check if I3C target device is ready. + (+) Call the function HAL_I3C_Ctrl_IsDeviceI2C_Ready() to check if I2C target device is ready. + + (+) Those functions are called only when mode is Controller. + +@endverbatim + * @{ + */ + +/** + * @brief Controller transmit direct write or a broadcast CCC command in polling mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers + * (control buffer, data buffer and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @param timeout : [IN] Timeout duration in millisecond. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData, + uint32_t timeout) +{ + uint32_t tickstart; + uint32_t exit_condition; + HAL_StatusTypeDef status = HAL_OK; + HAL_I3C_StateTypeDef handle_state; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || + ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL))) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + /* Update returned status value */ + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_TX; + hi3c->pXferData = pXferData; + + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitWordTreatment; + } + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check on control FIFO enable/disable state */ + if (LL_I3C_IsEnabledControlFIFO(hi3c->Instance) == 1U) + { + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + else + { + /* Decrement remaining control buffer data counter */ + hi3c->ControlXferCount--; + + /* Initiate a start condition by writing in the CR register */ + WRITE_REG(hi3c->Instance->CR, *hi3c->pXferData->CtrlBuf.pBuffer); + + /* Increment Buffer pointer */ + hi3c->pXferData->CtrlBuf.pBuffer++; + } + + /* Do while until FC (Frame Complete) is set or timeout */ + do + { + /* Check if hardware asks for control data */ + if (hi3c->ControlXferCount > 0U) + { + /* Call control data treatment function */ + I3C_ControlDataTreatment(hi3c); + } + + /* Check if hardware asks for Tx data */ + if (hi3c->TxXferCount > 0U) + { + /* Call transmit treatment function */ + hi3c->ptrTxFunc(hi3c); + } + + /* Check for the timeout */ + if (timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_TIMEOUT; + status = HAL_TIMEOUT; + break; + } + } + + if ((__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) && (hi3c->ControlXferCount > 0U)) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + /* Then Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + + /* Calculate exit_condition value based on Frame complete and error flags */ + exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)); + } while ((exit_condition == 0U) || + ((exit_condition == I3C_EVR_FCF) && (hi3c->ControlXferCount > 0U))); + + /* Clear frame complete flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) + { + LL_I3C_ClearFlag_FC(hi3c->Instance); + } + + /* Check on error flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET) + { + /* Clear error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + /* Update handle error code parameter */ + I3C_GetErrorSources(hi3c); + + /* Update returned status value */ + status = HAL_ERROR; + } + + /* At the end of Tx process update state to Previous state */ + I3C_StateUpdate(hi3c); + } + } + + return status; +} + +/** + * @brief Controller transmit direct write or a broadcast CCC command in interrupt mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers + * (control buffer, data buffer and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_IT(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData) +{ + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || + ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL))) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + if (handle_state == HAL_I3C_STATE_LISTEN) + { + hi3c->XferISR = I3C_Ctrl_Tx_Listen_Event_ISR; + } + else + { + hi3c->XferISR = I3C_Ctrl_Tx_ISR; + } + + hi3c->pXferData = pXferData; + hi3c->State = HAL_I3C_STATE_BUSY_TX; + + + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitWordTreatment; + } + + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Tx process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_CONTROLLER_TX_IT); + + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + } + + return status; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Controller transmit direct write or a broadcast CCC command in DMA mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers + * (control buffer, data buffer and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_DMA(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData) +{ + HAL_StatusTypeDef control_dma_status; + HAL_StatusTypeDef tx_dma_status = HAL_OK; + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + uint32_t size_align_word; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || + ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL))) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check on hdmatx and hdmacr handle */ + else if ((hi3c->hdmatx == NULL) || (hi3c->hdmacr == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->XferISR = I3C_Ctrl_Tx_DMA_ISR; + hi3c->pXferData = pXferData; + hi3c->State = HAL_I3C_STATE_BUSY_TX; + + /*------------------------------------ I3C DMA channel for Control Data ----------------------------------------*/ + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmacr->XferCpltCallback = I3C_DMAControlTransmitCplt; + + /* Set the DMA error callback */ + hi3c->hdmacr->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmacr->XferHalfCpltCallback = NULL; + hi3c->hdmacr->XferAbortCallback = NULL; + + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmacr->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmacr->Init.DestDataWidth)); + + /* Enable the control data DMA channel */ + control_dma_status = HAL_DMA_Start_IT(hi3c->hdmacr, (uint32_t)hi3c->pXferData->CtrlBuf.pBuffer, + (uint32_t)&hi3c->Instance->CR, (hi3c->ControlXferCount * 4U)); + + /*------------------------------------ I3C DMA channel for the Tx Data -----------------------------------------*/ + /* Check if Tx counter different from zero */ + if (hi3c->TxXferCount != 0U) + { + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmatx->XferCpltCallback = I3C_DMADataTransmitCplt; + + /* Set the DMA error callback */ + hi3c->hdmatx->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmatx->XferHalfCpltCallback = NULL; + hi3c->hdmatx->XferAbortCallback = NULL; + + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* assert that DMA source and destination width are configured in byte */ + assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmatx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmatx->Init.DestDataWidth)); + + /* Enable the Tx data DMA channel */ + tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer, + (uint32_t)&hi3c->Instance->TDR, hi3c->pXferData->TxBuf.Size); + } + else + { + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmatx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmatx->Init.DestDataWidth)); + + /* Check to align data size in words */ + if ((hi3c->pXferData->TxBuf.Size % 4U) == 0U) + { + /* Keep the same size */ + size_align_word = hi3c->pXferData->TxBuf.Size; + } + else + { + /* Modify size to be multiple of 4 */ + size_align_word = ((hi3c->pXferData->TxBuf.Size + 4U) - (hi3c->pXferData->TxBuf.Size % 4U)); + } + + /* Enable the Tx data DMA channel */ + tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer, + (uint32_t)&hi3c->Instance->TDWR, size_align_word); + } + } + + /* Check if DMA process is well started */ + if ((control_dma_status == HAL_OK) && (tx_dma_status == HAL_OK)) + { + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Tx process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_DMA); + + /* Update the number of remaining data bytes */ + hi3c->ControlXferCount = 0U; + + /* Enable control DMA Request */ + LL_I3C_EnableDMAReq_Control(hi3c->Instance); + + /* Check if Tx counter different from zero */ + if (hi3c->TxXferCount != 0U) + { + /* Update the number of remaining data bytes */ + hi3c->TxXferCount = 0U; + + /* Enable Tx data DMA Request */ + LL_I3C_EnableDMAReq_TX(hi3c->Instance); + } + + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + else + { + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdmacr) == HAL_OK) + { + hi3c->hdmacr->XferCpltCallback = NULL; + hi3c->hdmacr->XferErrorCallback = NULL; + } + + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdmatx) == HAL_OK) + { + hi3c->hdmatx->XferCpltCallback = NULL; + hi3c->hdmatx->XferErrorCallback = NULL; + } + + hi3c->ErrorCode = HAL_I3C_ERROR_DMA; + status = HAL_ERROR; + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + } + } + } + + return status; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Controller transmit direct read CCC command in polling mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers + * (control buffer, data buffer and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @param timeout : [IN] Timeout duration in millisecond. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData, + uint32_t timeout) +{ + uint32_t tickstart; + uint32_t exit_condition; + HAL_StatusTypeDef status = HAL_OK; + HAL_I3C_StateTypeDef handle_state; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || + (pXferData->RxBuf.pBuffer == NULL) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_RX; + hi3c->pXferData = pXferData; + hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size; + + /* Check on CCC defining byte */ + if (hi3c->TxXferCount != 0U) + { + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitWordTreatment; + } + } + + /* Check on the Rx threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment; + } + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check on control FIFO enable/disable state */ + if (LL_I3C_IsEnabledControlFIFO(hi3c->Instance) == 1U) + { + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + else + { + /* Decrement remaining control buffer data counter */ + hi3c->ControlXferCount--; + + /* Initiate a start condition by writing in the CR register */ + WRITE_REG(hi3c->Instance->CR, *hi3c->pXferData->CtrlBuf.pBuffer); + + /* Increment Buffer pointer */ + hi3c->pXferData->CtrlBuf.pBuffer++; + } + + /* Do while until FC (Frame Complete) is set or timeout */ + do + { + /* Call control data treatment function */ + I3C_ControlDataTreatment(hi3c); + + if (hi3c->TxXferCount != 0U) + { + /* Call transmit treatment function */ + hi3c->ptrTxFunc(hi3c); + } + + /* Call receive treatment function */ + hi3c->ptrRxFunc(hi3c); + + /* Check for the timeout */ + if (timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_TIMEOUT; + status = HAL_TIMEOUT; + + break; + } + } + + if ((__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) && (hi3c->ControlXferCount > 0U)) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + /* Then Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + + /* Calculate exit_condition value based on Frame complete and error flags */ + exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)); + } while ((exit_condition == 0U) || + ((exit_condition == I3C_EVR_FCF) && (hi3c->ControlXferCount > 0U))); + + /* Clear frame complete flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) + { + LL_I3C_ClearFlag_FC(hi3c->Instance); + } + + /* Check if all data bytes are received */ + if ((hi3c->RxXferCount != 0U) && (status == HAL_OK)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_SIZE; + status = HAL_ERROR; + } + + /* Check on error flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET) + { + /* Clear error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + /* Update handle error code parameter */ + I3C_GetErrorSources(hi3c); + + /* Update returned status value */ + status = HAL_ERROR; + } + + /* At the end of Rx process update state to Previous state */ + I3C_StateUpdate(hi3c); + } + } + + return status; +} + +/** + * @brief Controller transmit direct read CCC command in interrupt mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers + * (control buffer, data buffer and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_IT(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData) +{ + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || + (pXferData->RxBuf.pBuffer == NULL) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + if (handle_state == HAL_I3C_STATE_LISTEN) + { + hi3c->XferISR = I3C_Ctrl_Rx_Listen_Event_ISR; + } + else + { + hi3c->XferISR = I3C_Ctrl_Rx_ISR; + } + hi3c->pXferData = pXferData; + hi3c->RxXferCount = pXferData->RxBuf.Size; + hi3c->State = HAL_I3C_STATE_BUSY_RX; + + /* Check on CCC defining byte */ + if (hi3c->TxXferCount != 0U) + { + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitWordTreatment; + } + } + + /* Check on the Rx threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment; + } + + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Rx process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_CONTROLLER_RX_CCC_IT); + + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + + } + } + + return status; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Controller transmit direct read CCC command in DMA mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers + * (control buffer, data buffer and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_DMA(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData) +{ + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef control_dma_status; + HAL_StatusTypeDef tx_dma_status = HAL_OK; + HAL_StatusTypeDef rx_dma_status = HAL_OK; + uint32_t size_align_word; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || + (pXferData->RxBuf.pBuffer == NULL) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check on hdmarx and hdmacr handle */ + else if ((hi3c->hdmarx == NULL) || (hi3c->hdmacr == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM; + status = HAL_ERROR; + } + else if ((hi3c->TxXferCount != 0U) && (hi3c->hdmatx == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->XferISR = I3C_Ctrl_Rx_DMA_ISR; + hi3c->pXferData = pXferData; + hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size; + hi3c->State = HAL_I3C_STATE_BUSY_RX; + + /*------------------------------------ I3C DMA channel for Control Data ----------------------------------------*/ + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmacr->XferCpltCallback = I3C_DMAControlTransmitCplt; + + /* Set the DMA error callback */ + hi3c->hdmacr->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmacr->XferHalfCpltCallback = NULL; + hi3c->hdmacr->XferAbortCallback = NULL; + + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmacr->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmacr->Init.DestDataWidth)); + + /* Enable the control data DMA channel */ + control_dma_status = HAL_DMA_Start_IT(hi3c->hdmacr, (uint32_t)hi3c->pXferData->CtrlBuf.pBuffer, + (uint32_t)&hi3c->Instance->CR, (hi3c->ControlXferCount * 4U)); + + /*------------------------------------ I3C DMA channel for defining byte ---------------------------------------*/ + /* Check if Tx counter different from zero */ + if (hi3c->TxXferCount != 0U) + { + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmatx->XferCpltCallback = I3C_DMADataTransmitCplt; + + /* Set the DMA error callback */ + hi3c->hdmatx->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmatx->XferHalfCpltCallback = NULL; + hi3c->hdmatx->XferAbortCallback = NULL; + + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* assert that DMA source and destination width are configured in byte */ + assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmatx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmatx->Init.DestDataWidth)); + + /* Enable the Tx data DMA channel */ + tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer, + (uint32_t)&hi3c->Instance->TDR, hi3c->pXferData->TxBuf.Size); + } + else + { + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmatx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmatx->Init.DestDataWidth)); + + /* Modify size to be multiple of 4 */ + size_align_word = ((hi3c->pXferData->TxBuf.Size + 4U) - (hi3c->pXferData->TxBuf.Size % 4U)); + + /* Enable the Tx data DMA channel */ + tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer, + (uint32_t)&hi3c->Instance->TDWR, size_align_word); + } + } + /*------------------------------------ I3C DMA channel for the Rx Data -----------------------------------------*/ + /* Check if Rx counter different from zero */ + if (hi3c->RxXferCount != 0U) + { + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmarx->XferCpltCallback = I3C_DMADataReceiveCplt; + + /* Set the DMA error callback */ + hi3c->hdmarx->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmarx->XferHalfCpltCallback = NULL; + hi3c->hdmarx->XferAbortCallback = NULL; + + /* Check on the Rx threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* assert that DMA source and destination width are configured in byte */ + assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmarx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmarx->Init.DestDataWidth)); + + /* Enable the Rx data DMA channel */ + rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDR, + (uint32_t)hi3c->pXferData->RxBuf.pBuffer, hi3c->pXferData->RxBuf.Size); + } + else + { + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmarx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmarx->Init.DestDataWidth)); + + /* Check to align data size in words */ + if ((hi3c->pXferData->RxBuf.Size % 4U) == 0U) + { + /* Keep the same size */ + size_align_word = hi3c->pXferData->RxBuf.Size; + } + else + { + /* Modify size to be multiple of 4 */ + size_align_word = ((hi3c->pXferData->RxBuf.Size + 4U) - (hi3c->pXferData->RxBuf.Size % 4U)); + } + + /* Enable the Rx data DMA channel */ + rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDWR, + (uint32_t)hi3c->pXferData->RxBuf.pBuffer, size_align_word); + } + } + + /* Check if DMA process is well started */ + if ((control_dma_status == HAL_OK) && (tx_dma_status == HAL_OK) && (rx_dma_status == HAL_OK)) + { + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Rx process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_DMA); + + /* Update the number of remaining data bytes */ + hi3c->ControlXferCount = 0U; + + /* Enable control DMA Request */ + LL_I3C_EnableDMAReq_Control(hi3c->Instance); + + /* Check if Tx counter different from zero */ + if (hi3c->TxXferCount != 0U) + { + /* Update the number of remaining data bytes */ + hi3c->TxXferCount = 0U; + + /* Enable Tx data DMA Request */ + LL_I3C_EnableDMAReq_TX(hi3c->Instance); + } + + /* Check if Rx counter different from zero */ + if (hi3c->RxXferCount != 0U) + { + /* Update the number of remaining data bytes */ + hi3c->RxXferCount = 0U; + + /* Enable Rx data DMA Request */ + LL_I3C_EnableDMAReq_RX(hi3c->Instance); + } + + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + else + { + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdmacr) == HAL_OK) + { + hi3c->hdmacr->XferCpltCallback = NULL; + hi3c->hdmacr->XferErrorCallback = NULL; + } + + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdmatx) == HAL_OK) + { + hi3c->hdmatx->XferCpltCallback = NULL; + hi3c->hdmatx->XferErrorCallback = NULL; + } + + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdmarx) == HAL_OK) + { + hi3c->hdmarx->XferCpltCallback = NULL; + hi3c->hdmarx->XferErrorCallback = NULL; + } + + hi3c->ErrorCode = HAL_I3C_ERROR_DMA; + status = HAL_ERROR; + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + } + } + } + + return status; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Controller private write in polling mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. + * @note The TxBuf.Size must be equal to the sum of all TxBuf.Size exist in the descriptor. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers + * (control buffer, data buffer and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @param timeout : [IN] Timeout duration in millisecond. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData, + uint32_t timeout) +{ + uint32_t tickstart; + uint32_t exit_condition; + HAL_StatusTypeDef status = HAL_OK; + HAL_I3C_StateTypeDef handle_state; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || + ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL))) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_TX; + hi3c->pXferData = pXferData; + + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitWordTreatment; + } + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check on control FIFO enable/disable state */ + if (LL_I3C_IsEnabledControlFIFO(hi3c->Instance) == 1U) + { + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + else + { + /* Decrement remaining control buffer data counter */ + hi3c->ControlXferCount--; + + /* Initiate a start condition by writing in the CR register */ + WRITE_REG(hi3c->Instance->CR, *hi3c->pXferData->CtrlBuf.pBuffer); + + /* Increment Buffer pointer */ + hi3c->pXferData->CtrlBuf.pBuffer++; + } + + /* Do while until FC (Frame Complete) is set or timeout */ + do + { + /* Call control data treatment function */ + I3C_ControlDataTreatment(hi3c); + + /* Call transmit treatment function */ + hi3c->ptrTxFunc(hi3c); + + /* Check for the timeout */ + if (timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_TIMEOUT; + status = HAL_TIMEOUT; + + break; + } + } + + if ((__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) && (hi3c->ControlXferCount > 0U)) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + /* Then Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + + /* Calculate exit_condition value based on Frame complete and error flags */ + exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)); + } while ((exit_condition == 0U) || + ((exit_condition == I3C_EVR_FCF) && (hi3c->ControlXferCount > 0U))); + + /* Clear frame complete flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) + { + LL_I3C_ClearFlag_FC(hi3c->Instance); + } + + /* Check if all data bytes are transmitted */ + if ((hi3c->TxXferCount != 0U) && (status == HAL_OK)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_SIZE; + status = HAL_ERROR; + } + + /* Check on error flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET) + { + /* Clear error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + /* Update handle error code parameter */ + I3C_GetErrorSources(hi3c); + + /* Update returned status value */ + status = HAL_ERROR; + } + + /* At the end of Tx process update state to Previous state */ + I3C_StateUpdate(hi3c); + } + } + + return status; +} + +/** + * @brief Controller private write in interrupt mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. + * @note The TxBuf.Size must be equal to the sum of all TxBuf.Size exist in the descriptor. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers + * (control buffer, data buffer and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_IT(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData) +{ + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || + ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL))) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + if (handle_state == HAL_I3C_STATE_LISTEN) + { + hi3c->XferISR = I3C_Ctrl_Tx_Listen_Event_ISR; + } + else + { + hi3c->XferISR = I3C_Ctrl_Tx_ISR; + } + hi3c->pXferData = pXferData; + hi3c->State = HAL_I3C_STATE_BUSY_TX; + + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitWordTreatment; + } + + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Tx process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_CONTROLLER_TX_IT); + + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + } + + return status; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Controller private write in DMA mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. + * @note The TxBuf.Size must be equal to the sum of all TxBuf.Size exist in the descriptor. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers + * (control buffer, data buffer and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_DMA(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData) +{ + HAL_StatusTypeDef control_dma_status; + HAL_StatusTypeDef tx_dma_status = HAL_OK; + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + uint32_t size_align_word; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || + ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL))) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check on hdmatx and hdmacr handle */ + else if ((hi3c->hdmatx == NULL) || (hi3c->hdmacr == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->XferISR = I3C_Ctrl_Tx_DMA_ISR; + hi3c->State = HAL_I3C_STATE_BUSY_TX; + hi3c->pXferData = pXferData; + + /*------------------------------------ I3C DMA channel for Control Data ----------------------------------------*/ + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmacr->XferCpltCallback = I3C_DMAControlTransmitCplt; + + /* Set the DMA error callback */ + hi3c->hdmacr->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmacr->XferHalfCpltCallback = NULL; + hi3c->hdmacr->XferAbortCallback = NULL; + + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmacr->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmacr->Init.DestDataWidth)); + + /* Enable the control data DMA channel */ + control_dma_status = HAL_DMA_Start_IT(hi3c->hdmacr, (uint32_t)hi3c->pXferData->CtrlBuf.pBuffer, + (uint32_t)&hi3c->Instance->CR, (hi3c->ControlXferCount * 4U)); + + /*------------------------------------ I3C DMA channel for the Tx Data -----------------------------------------*/ + /* Check if Tx counter different from zero */ + if (hi3c->TxXferCount != 0U) + { + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmatx->XferCpltCallback = I3C_DMADataTransmitCplt; + + /* Set the DMA error callback */ + hi3c->hdmatx->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmatx->XferHalfCpltCallback = NULL; + hi3c->hdmatx->XferAbortCallback = NULL; + + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* assert that DMA source and destination width are configured in byte */ + assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmatx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmatx->Init.DestDataWidth)); + + /* Enable the Tx data DMA channel */ + tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer, + (uint32_t)&hi3c->Instance->TDR, hi3c->pXferData->TxBuf.Size); + } + else + { + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmatx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmatx->Init.DestDataWidth)); + + /* Check to align data size in words */ + if ((hi3c->pXferData->TxBuf.Size % 4U) == 0U) + { + /* Keep the same size */ + size_align_word = hi3c->pXferData->TxBuf.Size; + } + else + { + /* Modify size to be multiple of 4 */ + size_align_word = ((hi3c->pXferData->TxBuf.Size + 4U) - (hi3c->pXferData->TxBuf.Size % 4U)); + } + + /* Enable the Tx data DMA channel */ + tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer, + (uint32_t)&hi3c->Instance->TDWR, size_align_word); + } + } + + /* Check if DMA process is well started */ + if ((control_dma_status == HAL_OK) && (tx_dma_status == HAL_OK)) + { + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Tx process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_DMA); + + /* Update the number of remaining data bytes */ + hi3c->ControlXferCount = 0U; + + /* Enable control DMA Request */ + LL_I3C_EnableDMAReq_Control(hi3c->Instance); + + /* Check if Tx counter different from zero */ + if (hi3c->TxXferCount != 0U) + { + /* Update the number of remaining data bytes */ + hi3c->TxXferCount = 0U; + + /* Enable Tx data DMA Request */ + LL_I3C_EnableDMAReq_TX(hi3c->Instance); + } + + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + else + { + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdmacr) == HAL_OK) + { + hi3c->hdmacr->XferCpltCallback = NULL; + hi3c->hdmacr->XferErrorCallback = NULL; + } + + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdmatx) == HAL_OK) + { + hi3c->hdmatx->XferCpltCallback = NULL; + hi3c->hdmatx->XferErrorCallback = NULL; + } + + hi3c->ErrorCode = HAL_I3C_ERROR_DMA; + status = HAL_ERROR; + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + } + } + } + + return status; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Controller private read in polling mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers + * (control buffer, data buffer and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @param timeout : [IN] Timeout duration in millisecond. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_Receive(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData, + uint32_t timeout) +{ + uint32_t tickstart; + uint32_t exit_condition; + HAL_StatusTypeDef status = HAL_OK; + HAL_I3C_StateTypeDef handle_state; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || (pXferData->RxBuf.pBuffer == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_RX; + hi3c->pXferData = pXferData; + hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size; + + /* Check on the Rx threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment; + } + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check on control FIFO enable/disable state */ + if (LL_I3C_IsEnabledControlFIFO(hi3c->Instance) == 1U) + { + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + else + { + /* Decrement remaining control buffer data counter */ + hi3c->ControlXferCount--; + + /* Initiate a start condition by writing in the CR register */ + WRITE_REG(hi3c->Instance->CR, *hi3c->pXferData->CtrlBuf.pBuffer); + + /* Increment Buffer pointer */ + hi3c->pXferData->CtrlBuf.pBuffer++; + } + + /* Do while until FC (Frame Complete) is set or timeout */ + do + { + /* Call control data treatment function */ + I3C_ControlDataTreatment(hi3c); + + /* Call receive treatment function */ + hi3c->ptrRxFunc(hi3c); + + /* Check for the timeout */ + if (timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_TIMEOUT; + status = HAL_TIMEOUT; + + break; + } + } + + if ((__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) && (hi3c->ControlXferCount > 0U)) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + /* Then Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + + /* Calculate exit_condition value based on Frame complete and error flags */ + exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)); + } while ((exit_condition == 0U) || + ((exit_condition == I3C_EVR_FCF) && (hi3c->ControlXferCount > 0U))); + + /* Clear frame complete flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) + { + LL_I3C_ClearFlag_FC(hi3c->Instance); + } + + /* Check if all data bytes are received */ + if ((hi3c->RxXferCount != 0U) && (status == HAL_OK)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_SIZE; + status = HAL_ERROR; + } + + /* Check on error flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET) + { + /* Clear error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + /* Update handle error code parameter */ + I3C_GetErrorSources(hi3c); + + /* Update returned status value */ + status = HAL_ERROR; + } + + /* At the end of Rx process update state to Previous state */ + I3C_StateUpdate(hi3c); + } + } + + return status; +} + +/** + * @brief Controller private read in interrupt mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers + * (control buffer, data buffer and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_IT(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData) +{ + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || (pXferData->RxBuf.pBuffer == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + if (handle_state == HAL_I3C_STATE_LISTEN) + { + hi3c->XferISR = I3C_Ctrl_Rx_Listen_Event_ISR; + } + else + { + hi3c->XferISR = I3C_Ctrl_Rx_ISR; + } + hi3c->pXferData = pXferData; + hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size; + hi3c->State = HAL_I3C_STATE_BUSY_RX; + + /* Check on the Rx threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment; + } + + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Rx process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_CONTROLLER_RX_IT); + + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + } + + return status; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Controller private read in DMA mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers + * (control buffer, data buffer and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_DMA(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData) +{ + HAL_StatusTypeDef control_dma_status; + HAL_StatusTypeDef rx_dma_status = HAL_OK; + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + uint32_t size_align_word; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || (pXferData->RxBuf.pBuffer == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check on hdmarx and hdmacr handle */ + else if ((hi3c->hdmarx == NULL) || (hi3c->hdmacr == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->XferISR = I3C_Ctrl_Rx_DMA_ISR; + hi3c->pXferData = pXferData; + hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size; + hi3c->State = HAL_I3C_STATE_BUSY_RX; + + /*------------------------------------ I3C DMA channel for Control Data ----------------------------------------*/ + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmacr->XferCpltCallback = I3C_DMAControlTransmitCplt; + + /* Set the DMA error callback */ + hi3c->hdmacr->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmacr->XferHalfCpltCallback = NULL; + hi3c->hdmacr->XferAbortCallback = NULL; + + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmacr->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmacr->Init.DestDataWidth)); + + /* Enable the control data DMA channel */ + control_dma_status = HAL_DMA_Start_IT(hi3c->hdmacr, (uint32_t)hi3c->pXferData->CtrlBuf.pBuffer, + (uint32_t)&hi3c->Instance->CR, (hi3c->ControlXferCount * 4U)); + + /*------------------------------------ I3C DMA channel for the Rx Data -----------------------------------------*/ + /* Check if Rx counter different from zero */ + if (hi3c->RxXferCount != 0U) + { + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmarx->XferCpltCallback = I3C_DMADataReceiveCplt; + + /* Set the DMA error callback */ + hi3c->hdmarx->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmarx->XferHalfCpltCallback = NULL; + hi3c->hdmarx->XferAbortCallback = NULL; + + /* Check on the Rx threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* assert that DMA source and destination width are configured in byte */ + assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmarx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmarx->Init.DestDataWidth)); + + /* Enable the Rx data DMA channel */ + rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDR, + (uint32_t)hi3c->pXferData->RxBuf.pBuffer, hi3c->pXferData->RxBuf.Size); + } + else + { + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmarx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmarx->Init.DestDataWidth)); + + /* Check to align data size in words */ + if ((hi3c->pXferData->RxBuf.Size % 4U) == 0U) + { + /* Keep the same size */ + size_align_word = hi3c->pXferData->RxBuf.Size; + } + else + { + /* Modify size to be multiple of 4 */ + size_align_word = ((hi3c->pXferData->RxBuf.Size + 4U) - (hi3c->pXferData->RxBuf.Size % 4U)); + } + + /* Enable the Rx data DMA channel */ + rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDWR, + (uint32_t)hi3c->pXferData->RxBuf.pBuffer, size_align_word); + } + } + + /* Check if DMA process is well started */ + if ((control_dma_status == HAL_OK) && (rx_dma_status == HAL_OK)) + { + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Rx process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_DMA); + + /* Update the number of remaining data bytes */ + hi3c->ControlXferCount = 0U; + + /* Enable control DMA Request */ + LL_I3C_EnableDMAReq_Control(hi3c->Instance); + + /* Check if Rx counter different from zero */ + if (hi3c->RxXferCount != 0U) + { + /* Update the number of remaining data bytes */ + hi3c->RxXferCount = 0U; + + /* Enable Rx data DMA Request */ + LL_I3C_EnableDMAReq_RX(hi3c->Instance); + } + + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + else + { + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdmacr) == HAL_OK) + { + hi3c->hdmacr->XferCpltCallback = NULL; + hi3c->hdmacr->XferErrorCallback = NULL; + } + + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdmarx) == HAL_OK) + { + hi3c->hdmarx->XferCpltCallback = NULL; + hi3c->hdmarx->XferErrorCallback = NULL; + } + + hi3c->ErrorCode = HAL_I3C_ERROR_DMA; + status = HAL_ERROR; + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + } + + } + } + + return status; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Controller multiple Direct CCC Command, I3C private or I2C transfer in interrupt mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. + * @note This function must be called to transfer read/write I3C or I2C private data or a direct read/write CCC. + * @note The TxBuf.Size must be equal to the sum of all TxBuf.Size exist in the descriptor. + * @note The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmit and receive + * buffers (control buffer, data buffers and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_IT(I3C_HandleTypeDef *hi3c, + I3C_XferTypeDef *pXferData) +{ + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || + ((pXferData->RxBuf.pBuffer == NULL) && (hi3c->RxXferCount != 0U)) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + if (handle_state == HAL_I3C_STATE_LISTEN) + { + hi3c->XferISR = I3C_Ctrl_Multiple_Xfer_Listen_Event_ISR; + } + else + { + hi3c->XferISR = I3C_Ctrl_Multiple_Xfer_ISR; + } + hi3c->pXferData = pXferData; + hi3c->TxXferCount = hi3c->pXferData->TxBuf.Size; + hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size; + hi3c->State = HAL_I3C_STATE_BUSY_TX_RX; + + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitWordTreatment; + } + + /* Check on the Rx threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment; + } + + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Tx and Rx process interrupts */ + I3C_Enable_IRQ(hi3c, (I3C_XFER_CONTROLLER_TX_IT | I3C_XFER_CONTROLLER_RX_IT)); + + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + } + return status; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Controller multiple Direct CCC Command, I3C private or I2C transfer in DMA mode. + * @note The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer. + * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + * multiple transmission frames. + * @note The TxBuf.Size must be equal to the sum of all TxBuf.Size exist in the descriptor. + * @note The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor. + * @note This function must be called to transfer read/write private data or a direct read/write CCC command. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmit and receive + * buffers(control buffer, data buffer and status buffer). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData) +{ + HAL_StatusTypeDef control_dma_status; + HAL_StatusTypeDef tx_dma_status = HAL_OK; + HAL_StatusTypeDef rx_dma_status = HAL_OK; + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + uint32_t size_align_word; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || + ((pXferData->RxBuf.pBuffer == NULL) && (hi3c->RxXferCount != 0U)) || + ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U))) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check on hdmatx, hdmarx and hdmacr handle */ + else if ((hi3c->hdmatx == NULL) || (hi3c->hdmacr == NULL) || (hi3c->hdmarx == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->XferISR = I3C_Ctrl_Multiple_Xfer_DMA_ISR; + hi3c->pXferData = pXferData; + hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size; + hi3c->TxXferCount = hi3c->pXferData->TxBuf.Size; + hi3c->State = HAL_I3C_STATE_BUSY_TX_RX; + + /*------------------------------------ I3C DMA channel for Control Data -------------------------------------*/ + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmacr->XferCpltCallback = I3C_DMAControlTransmitCplt; + + /* Set the DMA error callback */ + hi3c->hdmacr->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmacr->XferHalfCpltCallback = NULL; + hi3c->hdmacr->XferAbortCallback = NULL; + + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmacr->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmacr->Init.DestDataWidth)); + + /* Enable the control data DMA channel */ + control_dma_status = HAL_DMA_Start_IT(hi3c->hdmacr, (uint32_t)hi3c->pXferData->CtrlBuf.pBuffer, + (uint32_t)&hi3c->Instance->CR, (hi3c->ControlXferCount * 4U)); + + /*------------------------------------ I3C DMA channel for the Rx Data --------------------------------*/ + /* Check if Rx counter different from zero */ + if (hi3c->RxXferCount != 0U) + { + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmarx->XferCpltCallback = I3C_DMADataReceiveCplt; + + /* Set the DMA error callback */ + hi3c->hdmarx->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmarx->XferHalfCpltCallback = NULL; + hi3c->hdmarx->XferAbortCallback = NULL; + + /* Check on the Rx threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* assert that DMA source and destination width are configured in byte */ + assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmarx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmarx->Init.DestDataWidth)); + + /* Enable the Rx data DMA channel */ + rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDR, + (uint32_t)hi3c->pXferData->RxBuf.pBuffer, hi3c->pXferData->RxBuf.Size); + } + else + { + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmarx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmarx->Init.DestDataWidth)); + + /* Check to align data size in words */ + if ((hi3c->pXferData->RxBuf.Size % 4U) == 0U) + { + /* Keep the same size */ + size_align_word = hi3c->pXferData->RxBuf.Size; + } + else + { + /* Modify size to be multiple of 4 */ + size_align_word = ((hi3c->pXferData->RxBuf.Size + 4U) - (hi3c->pXferData->RxBuf.Size % 4U)); + } + + /* Enable the Rx data DMA channel */ + rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDWR, + (uint32_t)hi3c->pXferData->RxBuf.pBuffer, size_align_word); + } + } + + /*------------------------------------ I3C DMA channel for the Tx Data --------------------------------*/ + /* Check if Tx counter different from zero */ + if (hi3c->TxXferCount != 0U) + { + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmatx->XferCpltCallback = I3C_DMADataTransmitCplt; + + /* Set the DMA error callback */ + hi3c->hdmatx->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmatx->XferHalfCpltCallback = NULL; + hi3c->hdmatx->XferAbortCallback = NULL; + + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* assert that DMA source and destination width are configured in byte */ + assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmatx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmatx->Init.DestDataWidth)); + + /* Enable the Tx data DMA channel */ + tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer, + (uint32_t)&hi3c->Instance->TDR, hi3c->pXferData->TxBuf.Size); + } + else + { + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmatx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmatx->Init.DestDataWidth)); + + /* Check to align data size in words */ + if ((hi3c->pXferData->TxBuf.Size % 4U) == 0U) + { + /* Keep the same size */ + size_align_word = hi3c->pXferData->TxBuf.Size; + } + else + { + /* Modify size to be multiple of 4 */ + size_align_word = ((hi3c->pXferData->TxBuf.Size + 4U) - (hi3c->pXferData->TxBuf.Size % 4U)); + } + + /* Enable the Tx data DMA channel */ + tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer, + (uint32_t)&hi3c->Instance->TDWR, size_align_word); + } + } + + /* Check if DMA process is well started */ + if ((control_dma_status == HAL_OK) && (tx_dma_status == HAL_OK) && (rx_dma_status == HAL_OK)) + { + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Tx process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_DMA); + + /* Update the number of remaining data bytes */ + hi3c->ControlXferCount = 0U; + + /* Enable control DMA Request */ + LL_I3C_EnableDMAReq_Control(hi3c->Instance); + + /* Check if Rx counter different from zero */ + if (hi3c->RxXferCount != 0U) + { + /* Update the number of remaining data bytes */ + hi3c->RxXferCount = 0U; + + /* Enable Rx data DMA Request */ + LL_I3C_EnableDMAReq_RX(hi3c->Instance); + } + + /* Check if Tx counter different from zero */ + if (hi3c->TxXferCount != 0U) + { + /* Update the number of remaining data bytes */ + hi3c->TxXferCount = 0U; + + /* Enable Tx data DMA Request */ + LL_I3C_EnableDMAReq_TX(hi3c->Instance); + } + + /* Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + else + { + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdmacr) == HAL_OK) + { + hi3c->hdmacr->XferCpltCallback = NULL; + hi3c->hdmacr->XferErrorCallback = NULL; + } + + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdmatx) == HAL_OK) + { + hi3c->hdmatx->XferCpltCallback = NULL; + hi3c->hdmatx->XferErrorCallback = NULL; + } + + /* Set callback to NULL if DMA started */ + if (HAL_DMA_Abort(hi3c->hdmarx) == HAL_OK) + { + hi3c->hdmarx->XferCpltCallback = NULL; + hi3c->hdmarx->XferErrorCallback = NULL; + } + + hi3c->ErrorCode = HAL_I3C_ERROR_DMA; + status = HAL_ERROR; + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + } + } + } + return status; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Controller assign dynamic address (send a broadcast ENTDAA CCC command) in polling mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param target_payload : [IN/OUT] Pointer to the returned target payload value. + * @param dynOption : [IN] Parameter indicates the Dynamic address assignment option. + * It can be one value of @ref I3C_DYNAMIC_ADDRESS_OPTION_DEFINITION. + * @param timeout : [IN] Timeout duration in millisecond. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign(I3C_HandleTypeDef *hi3c, + uint64_t *target_payload, + uint32_t dynOption, + uint32_t timeout) +{ + uint32_t tickstart; + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + + /* check on parameters */ + assert_param(IS_I3C_ENTDAA_OPTION(dynOption)); + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + if (target_payload == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Launch a RSTDAA procedure before launch ENTDAA */ + if ((dynOption == I3C_RSTDAA_THEN_ENTDAA) && + ((handle_state == HAL_I3C_STATE_READY) || (handle_state == HAL_I3C_STATE_LISTEN))) + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_DAA; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Enable arbitration header */ + LL_I3C_EnableArbitrationHeader(hi3c->Instance); + + /* Write CCC information in the control register */ + LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_RSTDAA, 0U, LL_I3C_GENERATE_STOP); + + /* Wait Frame completion flag */ + status = I3C_WaitOnFlagUntilTimeout(hi3c, HAL_I3C_FLAG_FCF, RESET, timeout, tickstart); + + /* Clear frame complete flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) + { + LL_I3C_ClearFlag_FC(hi3c->Instance); + } + + /* Check on error flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET) + { + /* Clear error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + /* Update handle error code parameter */ + I3C_GetErrorSources(hi3c); + + status = HAL_ERROR; + } + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + } + + if (status == HAL_OK) + { + /* check on the State */ + if ((handle_state == HAL_I3C_STATE_READY) || (handle_state == HAL_I3C_STATE_LISTEN) || + (handle_state == HAL_I3C_STATE_BUSY_DAA)) + { + /* Check on the state */ + if (handle_state != HAL_I3C_STATE_BUSY_DAA) + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_DAA; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Enable arbitration header */ + LL_I3C_EnableArbitrationHeader(hi3c->Instance); + + /* Write CCC information in the control register */ + LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_ENTDAA, 0U, LL_I3C_GENERATE_STOP); + } + else + { + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + } + + /* Wait frame complete flag or TX FIFO not full flag until timeout */ + status = I3C_WaitOnDAAUntilTimeout(hi3c, timeout, tickstart); + + /* Check TX FIFO not full flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_TXFNFF) == SET) + { + /* Check on the Rx FIFO threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* For loop to get target payload */ + for (uint32_t index = 0U; index < 8U; index++) + { + /* Retrieve payload byte by byte */ + *target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData8(hi3c->Instance) << (index * 8U)); + } + } + else + { + /* Retrieve first 32 bits payload */ + *target_payload = (uint64_t)LL_I3C_ReceiveData32(hi3c->Instance); + + /* Retrieve second 32 bits payload */ + *target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData32(hi3c->Instance) << 32U); + } + + status = HAL_BUSY; + } + /* Check on frame complete flag */ + else + { + /* Clear frame complete flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + } + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + } + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + } + } + } + + return status; +} + +/** + * @brief Controller assign dynamic address (send a broadcast ENTDAA CCC command) in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param dynOption : [IN] Parameter indicates the Dynamic address assignment option. + * It can be one value of @ref I3C_DYNAMIC_ADDRESS_OPTION_DEFINITION. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign_IT(I3C_HandleTypeDef *hi3c, uint32_t dynOption) +{ + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + + /* check on parameters */ + assert_param(IS_I3C_ENTDAA_OPTION(dynOption)); + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* check on the Mode */ + if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_DAA; + hi3c->XferISR = I3C_Ctrl_DAA_ISR; + + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Dynamic Address Assignment process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_CONTROLLER_DAA_IT); + + /* Enable arbitration header */ + LL_I3C_EnableArbitrationHeader(hi3c->Instance); + + /* Launch a RSTDAA procedure before launch ENTDAA */ + if (dynOption == I3C_RSTDAA_THEN_ENTDAA) + { + /* Write RSTDAA CCC information in the control register */ + LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_RSTDAA, 0U, LL_I3C_GENERATE_RESTART); + } + else + { + /* Write ENTDAA CCC information in the control register */ + LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_ENTDAA, 0U, LL_I3C_GENERATE_STOP); + } + } + } + + return status; +} + +/** + * @brief Controller set dynamic address. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param devAddress : [IN] Value of the dynamic address to be assigned. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_SetDynAddr(I3C_HandleTypeDef *hi3c, uint8_t devAddress) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check if Tx FIFO requests data */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_TXFNFF) == SET) + { + /* Write device address in the TDR register */ + LL_I3C_TransmitData8(hi3c->Instance, devAddress); + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Check if I3C target device is ready for communication. + * @param hi3c : [IN] Pointer to a I3C_HandleTypeDef structure that contains + * the configuration information for the specified I3C. + * @param devAddress : [IN] Value of the device dynamic address. + * @param trials : [IN] Number of trials + * @param timeout : [IN] Timeout duration + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI3C_Ready(I3C_HandleTypeDef *hi3c, + uint8_t devAddress, + uint32_t trials, + uint32_t timeout) +{ + I3C_DeviceTypeDef device; + HAL_StatusTypeDef status; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Initiate a device address */ + device.Address = devAddress; + + /* Initiate a message type */ + device.MessageType = LL_I3C_CONTROLLER_MTYPE_PRIVATE; + + /* Check if the device is ready*/ + status = I3C_Ctrl_IsDevice_Ready(hi3c, &device, trials, timeout); + } + + return status; +} + +/** + * @brief Check if I2C target device is ready for communication. + * @param hi3c : [IN] Pointer to a I3C_HandleTypeDef structure that contains + * the configuration information for the specified I3C. + * @param devAddress : [IN] Value of the device dynamic address. + * @param trials : [IN] Number of trials + * @param timeout : [IN] Timeout duration + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI2C_Ready(I3C_HandleTypeDef *hi3c, + uint8_t devAddress, + uint32_t trials, + uint32_t timeout) +{ + I3C_DeviceTypeDef device; + HAL_StatusTypeDef status; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Initiate a device address */ + device.Address = devAddress; + + /* Initiate a message type */ + device.MessageType = LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C; + + /* Check if the device is ready*/ + status = I3C_Ctrl_IsDevice_Ready(hi3c, &device, trials, timeout); + } + + return status; +} +/** + * @} + */ + +/** @defgroup I3C_Exported_Functions_Group6 Target operational functions. + * @brief I3C target operational functions. + * +@verbatim + ======================================================================================================================= + ##### Target operational functions ##### + ======================================================================================================================= + [..] This subsection provides a set of functions allowing to manage target I3C operation. + + (+) Call the function HAL_I3C_Tgt_Transmit() to transmit private data in polling mode. + (+) Call the function HAL_I3C_Tgt_Transmit_IT() to transmit private data in interrupt mode. + (+) Call the function HAL_I3C_Tgt_Transmit_DMA() to transmit private data in DMA mode. + (+) Call the function HAL_I3C_Tgt_Receive() to receive private data in polling mode. + (+) Call the function HAL_I3C_Tgt_Receive_IT() to receive private data in interrupt mode. + (+) Call the function HAL_I3C_Tgt_Receive_DMA() to receive private data in DMA mode. + (+) Call the function HAL_I3C_Tgt_ControlRoleReq() to send a control-role request in polling mode. + (+) Call the function HAL_I3C_Tgt_ControlRoleReq_IT() to send a control-role request in interrupt mode. + (+) Call the function HAL_I3C_Tgt_HotJoinReq() to send a Hot-Join request in polling mode. + (+) Call the function HAL_I3C_Tgt_HotJoinReq_IT() to send a Hot-Join request in interrupt mode. + (+) Call the function HAL_I3C_Tgt_IBIReq() to send an IBI request in polling mode. + (+) Call the function HAL_I3C_Tgt_IBIReq_IT() to send an IBI request in interrupt mode. + + (+) Those functions are called only when mode is Target. + +@endverbatim + * @{ + */ + +/** + * @brief Target transmit private data in polling mode. + * @note Target FIFO preload data is forced within this API for timing purpose. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers + * information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data + * to transmit in bytes (TxBuf.Size)). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @param timeout : [IN] Timeout duration in millisecond. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Tgt_Transmit(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, uint32_t timeout) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + HAL_I3C_StateTypeDef handle_state; + uint32_t it_source; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + it_source = READ_REG(hi3c->Instance->IER); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || (pXferData->TxBuf.pBuffer == NULL) || (pXferData->TxBuf.Size == 0U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_TARGET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + /* check if DEF or GRP CCC notifications are enabled */ + else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) || + (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* Verify the dynamic address validity */ + else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_TX; + hi3c->pXferData = pXferData; + hi3c->TxXferCount = pXferData->TxBuf.Size; + + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitWordTreatment; + } + + /* Set Preload information */ + LL_I3C_ConfigTxPreload(hi3c->Instance, (uint16_t)hi3c->pXferData->TxBuf.Size); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Do while until FC (Frame Complete) is set or timeout */ + do + { + /* Call transmit treatment function */ + hi3c->ptrTxFunc(hi3c); + + /* Check for the Timeout */ + if (timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_TIMEOUT; + status = HAL_TIMEOUT; + + break; + } + } + /* Exit loop on Frame complete or error flags */ + } while ((READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)) == 0U); + + /* Clear frame complete flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) + { + LL_I3C_ClearFlag_FC(hi3c->Instance); + } + + /* Check if all data bytes are transmitted */ + if ((LL_I3C_GetXferDataCount(hi3c->Instance) != hi3c->pXferData->TxBuf.Size) && (status == HAL_OK)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_SIZE; + status = HAL_ERROR; + } + + /* Check on error flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET) + { + /* Clear error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + /* Update handle error code parameter */ + I3C_GetErrorSources(hi3c); + + /* Update returned status value */ + status = HAL_ERROR; + } + + /* At the end of Tx process update state to Previous state */ + I3C_StateUpdate(hi3c); + } + } + + return status; +} + +/** + * @brief Target transmit private data in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers + * information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data + * to transmit in bytes (TxBuf.Size)). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData) +{ + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + uint32_t it_source; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + it_source = READ_REG(hi3c->Instance->IER); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || (pXferData->TxBuf.pBuffer == NULL) || (pXferData->TxBuf.Size == 0U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_TARGET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + /* check if DEF and GRP CCC notifications are enabled */ + else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) || + (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* Verify the dynamic address validity */ + else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + + status = HAL_ERROR; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_TX; + hi3c->pXferData = pXferData; + hi3c->TxXferCount = pXferData->TxBuf.Size; + hi3c->XferISR = I3C_Tgt_Tx_ISR; + + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrTxFunc = &I3C_TransmitWordTreatment; + } + + /* Set Preload information */ + LL_I3C_ConfigTxPreload(hi3c->Instance, (uint16_t)hi3c->pXferData->TxBuf.Size); + + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Tx process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_TARGET_TX_IT); + } + } + + return status; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Target transmit private data in DMA mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers + * information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data + * to transmit in bytes (TxBuf.Size)). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData) +{ + HAL_StatusTypeDef tx_dma_status; + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + uint32_t size_align_word; + uint32_t it_source; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + it_source = READ_REG(hi3c->Instance->IER); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || (pXferData->TxBuf.pBuffer == NULL) || (pXferData->TxBuf.Size == 0U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check on hdmatx handle */ + else if (hi3c->hdmatx == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_TARGET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + /* check if DEF and GRP CCC notifications are enabled */ + else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) || + (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* Verify the dynamic address validity */ + else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_TX; + hi3c->pXferData = pXferData; + hi3c->TxXferCount = pXferData->TxBuf.Size; + hi3c->XferISR = I3C_Tgt_Tx_DMA_ISR; + + /* Set Preload information */ + LL_I3C_ConfigTxPreload(hi3c->Instance, (uint16_t)hi3c->pXferData->TxBuf.Size); + + /*------------------------------------ I3C DMA channel for the Tx Data -----------------------------------------*/ + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmatx->XferCpltCallback = I3C_DMADataTransmitCplt; + + /* Set the DMA error callback */ + hi3c->hdmatx->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmatx->XferHalfCpltCallback = NULL; + hi3c->hdmatx->XferAbortCallback = NULL; + + /* Check on the Tx threshold to know the Tx treatment process : byte or word */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4) + { + /* assert that DMA source and destination width are configured in byte */ + assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmatx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmatx->Init.DestDataWidth)); + + /* Enable the Tx data DMA channel */ + tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer, + (uint32_t)&hi3c->Instance->TDR, hi3c->pXferData->TxBuf.Size); + } + else + { + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmatx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmatx->Init.DestDataWidth)); + + /* Check to align data size in words */ + if ((hi3c->pXferData->TxBuf.Size % 4U) == 0U) + { + /* Keep the same size */ + size_align_word = hi3c->pXferData->TxBuf.Size; + } + else + { + /* Modify size to be multiple of 4 */ + size_align_word = ((hi3c->pXferData->TxBuf.Size + 4U) - (hi3c->pXferData->TxBuf.Size % 4U)); + } + + /* Enable the Tx data DMA channel */ + tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer, + (uint32_t)&hi3c->Instance->TDWR, size_align_word); + } + + /* Check if DMA process is well started */ + if (tx_dma_status == HAL_OK) + { + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Tx process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_DMA); + + /* Update the number of remaining data bytes */ + hi3c->TxXferCount = 0U; + + /* Enable Tx data DMA Request */ + LL_I3C_EnableDMAReq_TX(hi3c->Instance); + } + else + { + /* Set callback to NULL if DMA started */ + hi3c->hdmatx->XferCpltCallback = NULL; + hi3c->hdmatx->XferErrorCallback = NULL; + + hi3c->ErrorCode = HAL_I3C_ERROR_DMA; + status = HAL_ERROR; + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + } + } + } + + return status; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Target receive private data in polling mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers + * information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data + * to be received in bytes (RxBuf.Size)). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @param timeout : [IN] Timeout duration in millisecond. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Tgt_Receive(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, uint32_t timeout) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + HAL_I3C_StateTypeDef handle_state; + uint32_t it_source; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + it_source = READ_REG(hi3c->Instance->IER); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || (pXferData->RxBuf.pBuffer == NULL) || (pXferData->RxBuf.Size == 0U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_TARGET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + /* check if DEF and GRP CCC notifications are enabled */ + else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) || + (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* Verify the dynamic address validity */ + else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_RX; + hi3c->pXferData = pXferData; + hi3c->RxXferCount = pXferData->RxBuf.Size; + + /* Check on the Rx threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment; + } + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Do while until FC (Frame Complete) is set or timeout */ + do + { + if (hi3c->RxXferCount > 0U) + { + /* Call receive treatment function */ + hi3c->ptrRxFunc(hi3c); + } + + /* Check for the Timeout */ + if (timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_TIMEOUT; + status = HAL_TIMEOUT; + + break; + } + } + /* Exit loop on Frame complete or error flags */ + } while ((READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)) == 0U); + + /* Clear frame complete flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) + { + LL_I3C_ClearFlag_FC(hi3c->Instance); + } + + /* Check if all data bytes are received */ + if ((LL_I3C_GetXferDataCount(hi3c->Instance) != hi3c->pXferData->RxBuf.Size) && (status == HAL_OK)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_SIZE; + status = HAL_ERROR; + } + + /* Check on error flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET) + { + /* Clear error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + /* Update handle error code parameter */ + I3C_GetErrorSources(hi3c); + + status = HAL_ERROR; + } + + /* At the end of Rx process update state to previous state */ + I3C_StateUpdate(hi3c); + } + } + + return status; +} + +/** + * @brief Target receive private data in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers + * information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data + * to be received in bytes (RxBuf.Size)). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData) +{ + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + uint32_t it_source; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + it_source = READ_REG(hi3c->Instance->IER); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || (pXferData->RxBuf.pBuffer == NULL) || (pXferData->RxBuf.Size == 0U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_TARGET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + /* check if DEF and GRP CCC notifications are enabled */ + else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) || + (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* Verify the dynamic address validity */ + else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_RX; + hi3c->pXferData = pXferData; + hi3c->RxXferCount = pXferData->RxBuf.Size; + hi3c->XferISR = I3C_Tgt_Rx_ISR; + + /* Check on the Rx threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* Set byte treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment; + } + else + { + /* Set word treatment function pointer */ + hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment; + } + + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Rx process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_TARGET_RX_IT); + } + } + + return status; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Target receive private data in DMA mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers + * information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data + * to be received in bytes (RxBuf.Size)). + * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Tgt_Receive_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData) +{ + HAL_StatusTypeDef rx_dma_status; + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + uint32_t size_align_word; + uint32_t it_source; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + it_source = READ_REG(hi3c->Instance->IER); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on user parameters */ + if ((pXferData == NULL) || (pXferData->RxBuf.pBuffer == NULL) || (pXferData->RxBuf.Size == 0U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check on hdmarx handle */ + else if (hi3c->hdmarx == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM; + status = HAL_ERROR; + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + } + /* check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_TARGET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + /* check if DEF and GRP CCC notifications are enabled */ + else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) || + (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* Verify the dynamic address validity */ + else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY_RX; + hi3c->pXferData = pXferData; + hi3c->RxXferCount = pXferData->RxBuf.Size; + hi3c->XferISR = I3C_Tgt_Rx_DMA_ISR; + + /*------------------------------------ I3C DMA channel for the Rx Data ---------------------------------------*/ + /* Set the I3C DMA transfer complete callback */ + hi3c->hdmarx->XferCpltCallback = I3C_DMADataReceiveCplt; + + /* Set the DMA error callback */ + hi3c->hdmarx->XferErrorCallback = I3C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi3c->hdmarx->XferHalfCpltCallback = NULL; + hi3c->hdmarx->XferAbortCallback = NULL; + + /* Check on the Rx threshold to know the Rx treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* assert that DMA source and destination width are configured in byte */ + assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmarx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmarx->Init.DestDataWidth)); + + /* Enable the Rx data DMA channel */ + rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDR, + (uint32_t)hi3c->pXferData->RxBuf.pBuffer, hi3c->pXferData->RxBuf.Size); + } + else + { + /* assert that DMA source and destination width are configured in word */ + assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmarx->Init.SrcDataWidth)); + assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmarx->Init.DestDataWidth)); + + /* Check to align data size in words */ + if ((hi3c->pXferData->RxBuf.Size % 4U) == 0U) + { + /* Keep the same size */ + size_align_word = hi3c->pXferData->RxBuf.Size; + } + else + { + /* Modify size to be multiple of 4 */ + size_align_word = ((hi3c->pXferData->RxBuf.Size + 4U) - (hi3c->pXferData->RxBuf.Size % 4U)); + } + + /* Enable the Rx data DMA channel */ + rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDWR, + (uint32_t)hi3c->pXferData->RxBuf.pBuffer, size_align_word); + } + + if (rx_dma_status == HAL_OK) + { + /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk + of I3C interrupt handle execution before current process unlock */ + + /* Enable Rx process interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_DMA); + + /* Update the number of remaining data bytes */ + hi3c->RxXferCount = 0U; + + /* Enable Rx data DMA Request */ + LL_I3C_EnableDMAReq_RX(hi3c->Instance); + } + else + { + /* Set callback to NULL if DMA started */ + hi3c->hdmarx->XferCpltCallback = NULL; + hi3c->hdmarx->XferErrorCallback = NULL; + + hi3c->ErrorCode = HAL_I3C_ERROR_DMA; + status = HAL_ERROR; + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + } + } + } + + return status; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Target send control role request in polling mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param timeout : [IN] Timeout duration in millisecond. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Tgt_ControlRoleReq(I3C_HandleTypeDef *hi3c, uint32_t timeout) +{ + uint32_t tickstart; + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* check on the Mode */ + if (hi3c->Mode != HAL_I3C_MODE_TARGET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + /* Verify the dynamic address validity */ + else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Verify if control role request feature is enabled */ + if (LL_I3C_IsEnabledControllerRoleReq(hi3c->Instance) != 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + } + + if (status == HAL_OK) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Request Controllership */ + LL_I3C_TargetHandleMessage(hi3c->Instance, LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ, 0U); + + /* Wait Controllership completion confirmation flag */ + status = I3C_WaitOnFlagUntilTimeout(hi3c, HAL_I3C_FLAG_CRUPDF, RESET, timeout, tickstart); + + /* Clear Control role request flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_CRUPDF) == SET) + { + LL_I3C_ClearFlag_CRUPD(hi3c->Instance); + } + + /* Check on error flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET) + { + /* Clear error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + /* Update handle error code parameter */ + I3C_GetErrorSources(hi3c); + + /* Update handle state parameter to previous state */ + I3C_StateUpdate(hi3c); + + status = HAL_ERROR; + } + else + { + /* Update handle state parameter to previous state */ + I3C_StateUpdate(hi3c); + } + } + } + + return status; +} + +/** + * @brief Target send control role request in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Tgt_ControlRoleReq_IT(I3C_HandleTypeDef *hi3c) +{ + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on the Mode */ + if (hi3c->Mode != HAL_I3C_MODE_TARGET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + /* Verify the dynamic address validity */ + else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Verify if control role request feature is enabled */ + if (LL_I3C_IsEnabledControllerRoleReq(hi3c->Instance) != 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + } + + if (status == HAL_OK) + { + /* Update handle parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY; + hi3c->XferISR = I3C_Tgt_CtrlRole_ISR; + + /* Enable controller-role update and error interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_TARGET_CTRLROLE); + + /* Request Controllership */ + LL_I3C_TargetHandleMessage(hi3c->Instance, LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ, 0U); + } + } + + return status; +} + +/** + * @brief Target send hot join request in polling mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param pAddress : [IN/OUT] Pointer to the target own dynamic address assigned by the controller. + * @param timeout : [IN] Timeout duration in millisecond. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Tgt_HotJoinReq(I3C_HandleTypeDef *hi3c, uint8_t *pAddress, uint32_t timeout) +{ + uint32_t tickstart; + HAL_I3C_StateTypeDef handle_state; + uint32_t valid_dynamic_address; + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on the pAddress value */ + if (pAddress == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check on the Mode */ + else if (hi3c->Mode != HAL_I3C_MODE_TARGET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Check on the hot join request feature */ + if (LL_I3C_IsEnabledHotJoin(hi3c->Instance) != 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + } + + if (status == HAL_OK) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Request hot join */ + LL_I3C_TargetHandleMessage(hi3c->Instance, LL_I3C_TARGET_MTYPE_HOT_JOIN, 0U); + + /* Wait hot join completion confirmation flag */ + status = I3C_WaitOnFlagUntilTimeout(hi3c, HAL_I3C_FLAG_DAUPDF, RESET, timeout, tickstart); + + /* Clear dynamic address update flag */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_DAUPDF) == SET) + { + LL_I3C_ClearFlag_DAUPD(hi3c->Instance); + } + + /* Get dynamic address validity flag */ + valid_dynamic_address = LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance); + + /* Check the validity of the own dynamic address */ + if (valid_dynamic_address == 0U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_DYNAMIC_ADDR; + status = HAL_ERROR; + + /* Update handle state parameter to previous state */ + I3C_StateUpdate(hi3c); + } + /* Check on error flag */ + else if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET) + { + /* Clear error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + /* Update handle error code parameter */ + I3C_GetErrorSources(hi3c); + + /* Update handle state parameter to previous state */ + I3C_StateUpdate(hi3c); + + status = HAL_ERROR; + } + else + { + /* Update handle state parameter to previous state */ + I3C_StateUpdate(hi3c); + + /* Get assigned dynamic address */ + *pAddress = LL_I3C_GetOwnDynamicAddress(hi3c->Instance); + } + } + } + + return status; +} + +/** + * @brief Target send hot join request in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Tgt_HotJoinReq_IT(I3C_HandleTypeDef *hi3c) +{ + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on the Mode */ + if (hi3c->Mode != HAL_I3C_MODE_TARGET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + /* Check on the hot join request feature */ + else if (LL_I3C_IsEnabledHotJoin(hi3c->Instance) != 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Update handle parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY; + hi3c->XferISR = I3C_Tgt_HotJoin_ISR; + + /* Enable dynamic address update and error interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_TARGET_HOTJOIN); + + /* Request hot join */ + LL_I3C_TargetHandleMessage(hi3c->Instance, LL_I3C_TARGET_MTYPE_HOT_JOIN, 0U); + } + } + + return status; +} + +/** + * @brief Target send IBI request in polling mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param pPayload : [IN] Pointer to the buffer contains the payload data. + * @param payloadSize : [IN] Payload buffer size in bytes. + * @param timeout : [IN] Timeout duration in millisecond. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Tgt_IBIReq(I3C_HandleTypeDef *hi3c, const uint8_t *pPayload, + uint8_t payloadSize, uint32_t timeout) +{ + uint32_t tickstart; + uint32_t payload_value = 0U; + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on the Mode */ + if (hi3c->Mode != HAL_I3C_MODE_TARGET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + /* Verify the dynamic address validity */ + else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Verify if IBI request feature is enabled*/ + if ((LL_I3C_IsEnabledIBI(hi3c->Instance) != 1U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + } + + if (status == HAL_OK) + { + /* Update handle parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY; + + /* Check on the IBI additional data */ + if (LL_I3C_GetDeviceIBIPayload(hi3c->Instance) == LL_I3C_IBI_ADDITIONAL_DATA) + { + /* Check on the pPayload and payloadSize values */ + if ((pPayload == NULL) || (payloadSize == 0U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + } + else + { + /* For loop to calculate the payload value */ + for (uint32_t index = 0U; index < payloadSize; index++) + { + payload_value |= ((uint32_t)pPayload[index] << (index * 8U)); + } + + /* Load IBI payload data */ + LL_I3C_SetIBIPayload(hi3c->Instance, payload_value); + } + } + + if (status == HAL_OK) + { + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Request IBI */ + LL_I3C_TargetHandleMessage(hi3c->Instance, LL_I3C_TARGET_MTYPE_IBI, payloadSize); + + /* Wait IBI completion confirmation flag */ + status = I3C_WaitOnFlagUntilTimeout(hi3c, HAL_I3C_FLAG_IBIENDF, RESET, timeout, tickstart); + + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_IBIENDF) == SET) + { + /* Clear IBI end process flag */ + LL_I3C_ClearFlag_IBIEND(hi3c->Instance); + } + + /* Check on error flag value */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET) + { + /* Clear error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + /* Update handle error code parameter */ + I3C_GetErrorSources(hi3c); + + /* Update handle state parameter to previous state */ + I3C_StateUpdate(hi3c); + + status = HAL_ERROR; + } + else + { + /* Update handle state parameter to previous state */ + I3C_StateUpdate(hi3c); + } + } + } + } + + return status; +} + +/** + * @brief Target send IBI request in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param pPayload : [IN] Pointer to the buffer contains the payload data. + * @param payloadSize : [IN] Payload buffer size in bytes. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Tgt_IBIReq_IT(I3C_HandleTypeDef *hi3c, const uint8_t *pPayload, uint8_t payloadSize) +{ + uint32_t payload_value = 0U; + HAL_I3C_StateTypeDef handle_state; + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check the instance and the mode parameters */ + assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance)); + assert_param(IS_I3C_MODE(hi3c->Mode)); + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* Check on the Mode */ + if (hi3c->Mode != HAL_I3C_MODE_TARGET) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + /* Verify the dynamic address validity */ + else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Verify if IBI request feature is enabled */ + if (LL_I3C_IsEnabledIBI(hi3c->Instance) != 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + } + + if (status == HAL_OK) + { + /* Update handle parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY; + hi3c->XferISR = I3C_Tgt_IBI_ISR; + + /* Check on the IBI additional data */ + if (LL_I3C_GetDeviceIBIPayload(hi3c->Instance) == LL_I3C_IBI_ADDITIONAL_DATA) + { + /* Check on the pPayload and payloadSize values */ + if ((pPayload == NULL) || (payloadSize == 0U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + } + else + { + /* For loop to calculate the payload value */ + for (uint32_t index = 0U; index < payloadSize; index++) + { + payload_value |= ((uint32_t)pPayload[index] << (index * 8U)); + } + + /* Load IBI payload data */ + LL_I3C_SetIBIPayload(hi3c->Instance, payload_value); + } + } + + /* Enable IBI end and error interrupts */ + I3C_Enable_IRQ(hi3c, I3C_XFER_TARGET_IBI); + + /* Request IBI */ + LL_I3C_TargetHandleMessage(hi3c->Instance, LL_I3C_TARGET_MTYPE_IBI, payloadSize); + } + } + + return status; +} +/** + * @} + */ + +/** @defgroup I3C_Exported_Functions_Group7 Generic and Common functions. + * @brief I3C generic and common functions. + * +@verbatim + ======================================================================================================================= + ##### Generic and Common functions ##### + ======================================================================================================================= + [..] This subsection provides a set of functions allowing to Abort transfer or to get in run-time the status + of the peripheral. + + (+) Call the function HAL_I3C_Abort_IT() to abort the current transfer either in DMA or IT. + (+) Call the function HAL_I3C_GetState() to get the I3C handle state. + (+) Call the function HAL_I3C_GetMode() to get the I3C handle mode. + (+) Call the function HAL_I3C_GetError() to get the error code. + +@endverbatim + * @{ + */ + +/** + * @brief Abort an I3C IT or DMA process communication with Interrupt. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Abort_IT(I3C_HandleTypeDef *hi3c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + if (hi3c->State != HAL_I3C_STATE_ABORT) + { + /* Set State at HAL_I3C_STATE_ABORT */ + hi3c->State = HAL_I3C_STATE_ABORT; + + /* Disable Error Interrupts */ + __HAL_I3C_DISABLE_IT(hi3c, HAL_I3C_IT_ERRIE); + + hi3c->XferISR = I3C_Abort_ISR; + + /* Flush the different Fifos to generate an automatic stop mode link to underflow or overflow detection timeout */ + /* Flush the content of Tx Fifo */ + LL_I3C_RequestTxFIFOFlush(hi3c->Instance); + + /* Flush the content of Rx Fifo */ + LL_I3C_RequestRxFIFOFlush(hi3c->Instance); + + /* Check on the I3C mode: Control and status FIFOs available only with controller mode */ + if (hi3c->Mode == HAL_I3C_MODE_CONTROLLER) + { + /* Flush the content of Control Fifo */ + LL_I3C_RequestControlFIFOFlush(hi3c->Instance); + + /* Flush the content of Status Fifo */ + LL_I3C_RequestStatusFIFOFlush(hi3c->Instance); + } + + /* Disable all DMA Requests */ + LL_I3C_DisableDMAReq_Control(hi3c->Instance); + LL_I3C_DisableDMAReq_RX(hi3c->Instance); + LL_I3C_DisableDMAReq_TX(hi3c->Instance); + LL_I3C_DisableDMAReq_Status(hi3c->Instance); + + if (hi3c->Mode == HAL_I3C_MODE_CONTROLLER) + { + /* Note : The I3C interrupts must be enabled after unlocking current process + to avoid the risk of I3C interrupt handle execution before current + process unlock */ + I3C_Enable_IRQ(hi3c, I3C_XFER_CONTROLLER_RX_CCC_IT); + } + else + { + /* Note : The I3C interrupts must be enabled after unlocking current process + to avoid the risk of I3C interrupt handle execution before current + process unlock */ + I3C_Enable_IRQ(hi3c, I3C_XFER_TARGET_RX_IT); + } + } + else + { + return HAL_BUSY; + } + } + + return status; +} + +/** + * @brief Return the I3C handle state. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @retval HAL State : [OUT] Value from HAL_I3C_StateTypeDef enumeration. + */ +HAL_I3C_StateTypeDef HAL_I3C_GetState(const I3C_HandleTypeDef *hi3c) +{ + return hi3c->State; +} + +/** + * @brief Returns the I3C handle mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @retval HAL Mode : [OUT] Value from HAL_I3C_ModeTypeDef enumeration. + */ +HAL_I3C_ModeTypeDef HAL_I3C_GetMode(const I3C_HandleTypeDef *hi3c) +{ + return hi3c->Mode; +} + +/** + * @brief Return the I3C error code. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @retval I3C Error Code : [OUT] Value from @ref I3C_ERROR_CODE_DEFINITION. + */ +uint32_t HAL_I3C_GetError(const I3C_HandleTypeDef *hi3c) +{ + return hi3c->ErrorCode; +} + +/** + * @brief Target/Controller Get Common Command Code Information updated after event. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param notifyId : [IN] Parameter indicates which notification is signaled. + * It can be a combination of value of @ref HAL_I3C_Notification_ID_definition. + * @param pCCCInfo : [IN/OUT] Pointer to an I3C_CCCInfoTypeDef structure that contains the CCC information + * updated after CCC event. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_GetCCCInfo(I3C_HandleTypeDef *hi3c, + uint32_t notifyId, + I3C_CCCInfoTypeDef *pCCCInfo) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check on user parameters */ + if (pCCCInfo == NULL) + { + /* Update handle error code parameter */ + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + /* Check the I3C state */ + else if (hi3c->State == HAL_I3C_STATE_RESET) + { + /* Update handle error code parameter */ + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + else + { + /* Retrieve Target Dynamic Address value and Validity (target/controller) */ + if ((notifyId & EVENT_ID_DAU) == EVENT_ID_DAU) + { + pCCCInfo->DynamicAddrValid = LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance); + pCCCInfo->DynamicAddr = LL_I3C_GetOwnDynamicAddress(hi3c->Instance); + } + + /* Retrieve Maximum Write Data Length (target) */ + if ((notifyId & EVENT_ID_SETMWL) == EVENT_ID_SETMWL) + { + pCCCInfo->MaxWriteLength = LL_I3C_GetMaxWriteLength(hi3c->Instance); + } + + /* Retrieve Maximum Read Data Length (target) */ + if ((notifyId & EVENT_ID_SETMRL) == EVENT_ID_SETMRL) + { + pCCCInfo->MaxReadLength = LL_I3C_GetMaxReadLength(hi3c->Instance); + } + + /* Retrieve Reset Action/Level on received reset pattern (target) */ + if ((notifyId & EVENT_ID_RSTACT) == EVENT_ID_RSTACT) + { + pCCCInfo->ResetAction = LL_I3C_GetResetAction(hi3c->Instance); + } + + /* Retrieve Activity State (target) */ + if ((notifyId & EVENT_ID_ENTASx) == EVENT_ID_ENTASx) + { + pCCCInfo->ActivityState = LL_I3C_GetActivityState(hi3c->Instance); + } + + /* Retrieve Interrupt allowed status (target) */ + if ((notifyId & EVENT_ID_ENEC_DISEC) == EVENT_ID_ENEC_DISEC) + { + pCCCInfo->HotJoinAllowed = LL_I3C_IsEnabledHotJoin(hi3c->Instance); + pCCCInfo->InBandAllowed = LL_I3C_IsEnabledIBI(hi3c->Instance); + pCCCInfo->CtrlRoleAllowed = LL_I3C_IsEnabledControllerRoleReq(hi3c->Instance); + } + + /* Retrieve In Band Interrupt information (controller) */ + if ((notifyId & EVENT_ID_IBI) == EVENT_ID_IBI) + { + pCCCInfo->IBICRTgtAddr = LL_I3C_GetIBITargetAddr(hi3c->Instance); + pCCCInfo->IBITgtNbPayload = LL_I3C_GetNbIBIAddData(hi3c->Instance); + pCCCInfo->IBITgtPayload = LL_I3C_GetIBIPayload(hi3c->Instance); + } + + /* Retrieve Controller role request Interrupt information (controller) */ + if ((notifyId & EVENT_ID_CR) == EVENT_ID_CR) + { + pCCCInfo->IBICRTgtAddr = LL_I3C_GetIBITargetAddr(hi3c->Instance); + } + } + } + + return status; +} + +/** + * @brief Get BCR, DCR and PID information after ENTDAA. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param ENTDAA_payload :[IN] Payload received after ENTDAA + * @param pENTDAA_payload :[OUT] Pointer to an I3C_ENTDAAPayloadTypeDef structure that contains the BCR, DCR and PID + * information. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +HAL_StatusTypeDef HAL_I3C_Get_ENTDAA_Payload_Info(I3C_HandleTypeDef *hi3c, + uint64_t ENTDAA_payload, + I3C_ENTDAAPayloadTypeDef *pENTDAA_payload) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t BCR; + uint64_t PID; + + /* check on the handle */ + if (hi3c == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check on user parameters */ + if (pENTDAA_payload == NULL) + { + /* Update handle error code parameter */ + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + /* Get Bus Characterics */ + BCR = __HAL_I3C_GET_BCR(ENTDAA_payload); + + /* Retrieve BCR information */ + pENTDAA_payload->BCR.IBIPayload = __HAL_I3C_GET_IBI_PAYLOAD(BCR); + pENTDAA_payload->BCR.IBIRequestCapable = __HAL_I3C_GET_IBI_CAPABLE(BCR); + pENTDAA_payload->BCR.DeviceRole = __HAL_I3C_GET_CR_CAPABLE(BCR); + pENTDAA_payload->BCR.AdvancedCapabilities = I3C_GET_ADVANCED_CAPABLE(BCR); + pENTDAA_payload->BCR.OfflineCapable = I3C_GET_OFFLINE_CAPABLE(BCR); + pENTDAA_payload->BCR.VirtualTargetSupport = I3C_GET_VIRTUAL_TGT(BCR); + pENTDAA_payload->BCR.MaxDataSpeedLimitation = I3C_GET_MAX_DATA_SPEED_LIMIT(BCR); + + /* Get Device Characterics */ + pENTDAA_payload->DCR = I3C_GET_DCR(ENTDAA_payload); + + /* Get Provisioned ID */ + PID = I3C_GET_PID(ENTDAA_payload); + + /* Change PID from BigEndian to litlleEndian */ + PID = (uint64_t)((((uint64_t)I3C_BIG_TO_LITTLE_ENDIAN((uint32_t) PID) << 32) | + ((uint64_t)I3C_BIG_TO_LITTLE_ENDIAN((uint32_t)(PID >> 32)))) >> 16); + + /* Retrieve PID information*/ + pENTDAA_payload->PID.MIPIMID = I3C_GET_MIPIMID(PID); + pENTDAA_payload->PID.IDTSEL = I3C_GET_IDTSEL(PID); + pENTDAA_payload->PID.PartID = I3C_GET_PART_ID(PID); + pENTDAA_payload->PID.MIPIID = I3C_GET_MIPIID(PID); + } + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_Private_Functions I3C Private Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handles target received events. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + uint32_t tmpevent = 0U; + + /* I3C Rx FIFO not empty interrupt Check */ + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET) + { + /* Call receive treatment function */ + hi3c->ptrRxFunc(hi3c); + } + + /* I3C target complete controller-role hand-off procedure (direct GETACCR CCC) event management --------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRUPDF) != RESET) + { + /* Clear controller-role update flag */ + LL_I3C_ClearFlag_CRUPD(hi3c->Instance); + + /* Set Identifier EVENT_ID_GETACCCR */ + tmpevent |= EVENT_ID_GETACCCR; + } + + /* I3C target receive any direct GETxxx CCC event management -------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_GETF) != RESET) + { + /* Clear GETxxx CCC flag */ + LL_I3C_ClearFlag_GET(hi3c->Instance); + + /* Set Identifier EVENT_ID_GETx */ + tmpevent |= EVENT_ID_GETx; + } + + /* I3C target receive get status command (direct GETSTATUS CCC) event management -----------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_STAF) != RESET) + { + /* Clear GETSTATUS CCC flag */ + LL_I3C_ClearFlag_STA(hi3c->Instance); + + /* Set Identifier EVENT_ID_GETSTATUS */ + tmpevent |= EVENT_ID_GETSTATUS; + } + + /* I3C target receive a dynamic address update (ENTDAA/RSTDAA/SETNEWDA CCC) event management -----------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_DAUPDF) != RESET) + { + /* Clear dynamic address update flag */ + LL_I3C_ClearFlag_DAUPD(hi3c->Instance); + + /* Set Identifier EVENT_ID_DAU */ + tmpevent |= EVENT_ID_DAU; + } + + /* I3C target receive maximum write length update (direct SETMWL CCC) event management -----------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_MWLUPDF) != RESET) + { + /* Clear SETMWL CCC flag */ + LL_I3C_ClearFlag_MWLUPD(hi3c->Instance); + + /* Set Identifier EVENT_ID_SETMWL */ + tmpevent |= EVENT_ID_SETMWL; + } + + /* I3C target receive maximum read length update(direct SETMRL CCC) event management -------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_MRLUPDF) != RESET) + { + /* Clear SETMRL CCC flag */ + LL_I3C_ClearFlag_MRLUPD(hi3c->Instance); + + /* Set Identifier EVENT_ID_SETMRL */ + tmpevent |= EVENT_ID_SETMRL; + } + + /* I3C target detect reset pattern (broadcast or direct RSTACT CCC) event management -------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_RSTF) != RESET) + { + /* Clear reset pattern flag */ + LL_I3C_ClearFlag_RST(hi3c->Instance); + + /* Set Identifier EVENT_ID_RSTACT */ + tmpevent |= EVENT_ID_RSTACT; + } + + /* I3C target receive activity state update (direct or broadcast ENTASx) CCC event management ----------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_ASUPDF) != RESET) + { + /* Clear ENTASx CCC flag */ + LL_I3C_ClearFlag_ASUPD(hi3c->Instance); + + /* Set Identifier EVENT_ID_ENTASx */ + tmpevent |= EVENT_ID_ENTASx; + } + + /* I3C target receive a direct or broadcast ENEC/DISEC CCC event management ----------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_INTUPDF) != RESET) + { + /* Clear ENEC/DISEC CCC flag */ + LL_I3C_ClearFlag_INTUPD(hi3c->Instance); + + /* Set Identifier EVENT_ID_ENEC_DISEC */ + tmpevent |= EVENT_ID_ENEC_DISEC; + } + + /* I3C target receive a broadcast DEFTGTS CCC event management -----------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_DEFF) != RESET) + { + /* Clear DEFTGTS CCC flag */ + LL_I3C_ClearFlag_DEF(hi3c->Instance); + + /* Set Identifier EVENT_ID_DEFTGTS */ + tmpevent |= EVENT_ID_DEFTGTS; + } + + /* I3C target receive a group addressing (broadcast DEFGRPA CCC) event management ----------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_GRPF) != RESET) + { + /* Clear DEFGRPA CCC flag */ + LL_I3C_ClearFlag_GRP(hi3c->Instance); + + /* Set Identifier EVENT_ID_DEFGRPA */ + tmpevent |= EVENT_ID_DEFGRPA; + } + + /* I3C target wakeup event management ----------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET) + { + /* Clear WKP flag */ + LL_I3C_ClearFlag_WKP(hi3c->Instance); + + /* Set Identifier EVENT_ID_WKP */ + tmpevent |= EVENT_ID_WKP; + } + + if (tmpevent != 0U) + { +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, tmpevent); +#else + /* Asynchronous receive CCC event Callback */ + HAL_I3C_NotifyCallback(hi3c, tmpevent); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles Controller received events. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* I3C controller receive IBI event management ---------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET) + { + /* Clear IBI request flag */ + LL_I3C_ClearFlag_IBI(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_IBI); +#else + /* Asynchronous IBI event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_IBI); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* I3C controller controller-role request event management ---------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET) + { + /* Clear controller-role request flag */ + LL_I3C_ClearFlag_CR(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_CR); +#else + /* Asynchronous controller-role event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_CR); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* I3C controller hot-join event management ------------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET) + { + /* Clear hot-join flag */ + LL_I3C_ClearFlag_HJ(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_HJ); +#else + /* Asynchronous hot-join event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_HJ); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles target hot join event. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Tgt_HotJoin_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* I3C target receive a dynamic address update event management */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_DAUPDF) != RESET) + { + /* Clear dynamic address update flag */ + LL_I3C_ClearFlag_DAUPD(hi3c->Instance); + + /* Disable dynamic address update and error interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_TARGET_HOTJOIN); + + /* Check the validity of the own dynamic address */ + if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) == 1U) + { + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->TgtHotJoinCallback(hi3c, (uint8_t)LL_I3C_GetOwnDynamicAddress(hi3c->Instance)); +#else + /* Asynchronous receive ENTDAA/RSTDAA/SETNEWDA CCC event Callback */ + HAL_I3C_TgtHotJoinCallback(hi3c, (uint8_t)LL_I3C_GetOwnDynamicAddress(hi3c->Instance)); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_DYNAMIC_ADDR; + + /* Call error treatment function */ + I3C_ErrorTreatment(hi3c); + } + } + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles target control role event. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Tgt_CtrlRole_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* I3C target complete controller-role hand-off procedure (direct GETACCR CCC) event management -------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRUPDF) != RESET) + { + /* Clear controller-role update flag */ + LL_I3C_ClearFlag_CRUPD(hi3c->Instance); + + /* Disable controller-role update and error interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_TARGET_CTRLROLE); + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_GETACCCR); +#else + /* Asynchronous receive GETACCR CCC event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_GETACCCR); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles target IBI event. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Tgt_IBI_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* I3C target IBI end process event management ---------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIENDF) != RESET) + { + /* Clear IBI end flag */ + LL_I3C_ClearFlag_IBIEND(hi3c->Instance); + + /* Disable IBI end and error interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_TARGET_IBI); + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_IBIEND); +#else + /* Asynchronous IBI end event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_IBIEND); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles target transmit data in Interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Tgt_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* Check that a Tx process is ongoing */ + if (hi3c->State == HAL_I3C_STATE_BUSY_TX) + { + /* I3C Tx FIFO not full interrupt Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET) + { + if (hi3c->TxXferCount > 0U) + { + /* Call transmit treatment function */ + hi3c->ptrTxFunc(hi3c); + } + } + + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + /* Check if all data bytes are transmitted */ + if (LL_I3C_GetXferDataCount(hi3c->Instance) == hi3c->pXferData->TxBuf.Size) + { + /* Disable Tx process interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_TARGET_TX_IT); + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Call the transmit complete callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->TgtTxCpltCallback(hi3c); +#else + HAL_I3C_TgtTxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_SIZE; + + /* Call error treatment function */ + I3C_ErrorTreatment(hi3c); + } + } + + /* I3C target wakeup event management ----------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET) + { + /* Clear WKP flag */ + LL_I3C_ClearFlag_WKP(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_WKP); +#else + /* Asynchronous receive CCC event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_WKP); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + } + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles target receive data in Interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Tgt_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* Check that an Rx process is ongoing */ + if (hi3c->State == HAL_I3C_STATE_BUSY_RX) + { + /* I3C Rx FIFO not empty interrupt Check */ + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET) + { + if (hi3c->RxXferCount > 0U) + { + /* Call receive treatment function */ + hi3c->ptrRxFunc(hi3c); + } + } + + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + /* Check if all data bytes are received */ + if (LL_I3C_GetXferDataCount(hi3c->Instance) == hi3c->pXferData->RxBuf.Size) + { + /* Disable Rx process interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_TARGET_RX_IT); + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Call the receive complete callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->TgtRxCpltCallback(hi3c); +#else + HAL_I3C_TgtRxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_SIZE; + + /* Call error treatment function */ + I3C_ErrorTreatment(hi3c); + } + } + + /* I3C target wakeup event management ----------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET) + { + /* Clear WKP flag */ + LL_I3C_ClearFlag_WKP(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_WKP); +#else + /* Asynchronous receive CCC event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_WKP); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + } + + return HAL_OK; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Interrupt Sub-Routine which handles target transmit data in DMA mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Tgt_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* Check that a Tx process is ongoing */ + if (hi3c->State == HAL_I3C_STATE_BUSY_TX) + { + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + /* Check if all data bytes are transmitted */ + if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmatx) == 0U) + { + /* Disable Tx process interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_DMA); + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Update the number of remaining data bytes */ + hi3c->TxXferCount = 0U; + + /* Call target transmit complete callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->TgtTxCpltCallback(hi3c); +#else + HAL_I3C_TgtTxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_SIZE; + + /* Call error treatment function */ + I3C_ErrorTreatment(hi3c); + } + } + + /* I3C target wakeup event management ----------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET) + { + /* Clear WKP flag */ + LL_I3C_ClearFlag_WKP(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_WKP); +#else + /* Asynchronous receive CCC event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_WKP); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + } + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles target receive data in DMA mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Tgt_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* Check that a Rx process is ongoing */ + if (hi3c->State == HAL_I3C_STATE_BUSY_RX) + { + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + /* Check if all data bytes are received */ + if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmarx) == 0U) + { + /* Disable Rx process interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_DMA); + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Update the number of remaining data bytes */ + hi3c->RxXferCount = 0U; + + /* Call target receive complete callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->TgtRxCpltCallback(hi3c); +#else + HAL_I3C_TgtRxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_SIZE; + + /* Call error treatment function */ + I3C_ErrorTreatment(hi3c); + } + } + + /* I3C target wakeup event management ----------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET) + { + /* Clear WKP flag */ + LL_I3C_ClearFlag_WKP(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_WKP); +#else + /* Asynchronous receive CCC event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_WKP); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + } + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Interrupt Sub-Routine which handles controller transmission in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* Check that a Tx process is ongoing */ + if (hi3c->State == HAL_I3C_STATE_BUSY_TX) + { + /* Check if Control FIFO requests data */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET) + { + if (hi3c->ControlXferCount > 0U) + { + /* Call control data treatment function */ + I3C_ControlDataTreatment(hi3c); + } + } + + /* I3C Tx FIFO not full interrupt Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET) + { + if (hi3c->TxXferCount > 0U) + { + /* Call Transmit treatment function */ + hi3c->ptrTxFunc(hi3c); + } + } + + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + if (hi3c->ControlXferCount == 0U) + { + /* Disable Tx process interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_CONTROLLER_TX_IT); + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Call the transmit complete callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->CtrlTxCpltCallback(hi3c); +#else + HAL_I3C_CtrlTxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Call the transmit complete callback */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->CtrlTxCpltCallback(hi3c); +#else + HAL_I3C_CtrlTxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + + /* Then Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + + } + } + } + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles controller reception in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* Check that an Rx process is ongoing */ + if (hi3c->State == HAL_I3C_STATE_BUSY_RX) + { + /* Check if Control FIFO requests data */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET) + { + if (hi3c->ControlXferCount > 0U) + { + /* Call control data treatment function */ + I3C_ControlDataTreatment(hi3c); + } + } + + /* I3C Rx FIFO not empty interrupt Check */ + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET) + { + if (hi3c->RxXferCount > 0U) + { + /* Call receive treatment function */ + hi3c->ptrRxFunc(hi3c); + } + } + + /* I3C Tx FIFO not full interrupt Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET) + { + if (hi3c->TxXferCount > 0U) + { + /* Call Transmit treatment function */ + hi3c->ptrTxFunc(hi3c); + } + } + + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + if (hi3c->ControlXferCount == 0U) + { + /* Disable Rx process interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_CONTROLLER_RX_CCC_IT); + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Call the receive complete callback */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->CtrlRxCpltCallback(hi3c); +#else + HAL_I3C_CtrlRxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Call the receive complete callback */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->CtrlRxCpltCallback(hi3c); +#else + HAL_I3C_CtrlRxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + + /* Then Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + } + } + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles controller multiple transmission/reception in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* Check that a Tx/Rx process is ongoing */ + if (hi3c->State == HAL_I3C_STATE_BUSY_TX_RX) + { + /* Check if Control FIFO requests data */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET) + { + if (hi3c->ControlXferCount > 0U) + { + /* Call control data treatment function */ + I3C_ControlDataTreatment(hi3c); + } + } + + /* I3C Tx FIFO not full interrupt Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET) + { + if (hi3c->TxXferCount > 0U) + { + /* Call Transmit treatment function */ + hi3c->ptrTxFunc(hi3c); + } + } + + /* I3C Rx FIFO not empty interrupt Check */ + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET) + { + if (hi3c->RxXferCount > 0U) + { + /* Call receive treatment function */ + hi3c->ptrRxFunc(hi3c); + } + } + + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + if (hi3c->ControlXferCount == 0U) + { + /* Disable Tx process interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_CONTROLLER_TX_IT); + + /* Disable Rx process interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_CONTROLLER_RX_CCC_IT); + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Call the transmit, receive complete callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->CtrlMultipleXferCpltCallback(hi3c); +#else + HAL_I3C_CtrlMultipleXferCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Then Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + } + } + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles controller transmission and Controller received events + * in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_Tx_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* I3C controller receive IBI event management ---------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET) + { + /* Clear IBI request flag */ + LL_I3C_ClearFlag_IBI(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_IBI); +#else + /* Asynchronous IBI event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_IBI); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* I3C controller controller-role request event management ---------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET) + { + /* Clear controller-role request flag */ + LL_I3C_ClearFlag_CR(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_CR); +#else + /* Asynchronous controller-role event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_CR); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* I3C controller hot-join event management ------------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET) + { + /* Clear hot-join flag */ + LL_I3C_ClearFlag_HJ(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_HJ); +#else + /* Asynchronous hot-join event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_HJ); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* ISR controller transmission */ + return (I3C_Ctrl_Tx_ISR(hi3c, itMasks)); +} + +/** + * @brief Interrupt Sub-Routine which handles controller reception and Controller received events in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_Rx_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* I3C controller receive IBI event management ---------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET) + { + /* Clear IBI request flag */ + LL_I3C_ClearFlag_IBI(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_IBI); +#else + /* Asynchronous IBI event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_IBI); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* I3C controller controller-role request event management ---------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET) + { + /* Clear controller-role request flag */ + LL_I3C_ClearFlag_CR(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_CR); +#else + /* Asynchronous controller-role event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_CR); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* I3C controller hot-join event management ------------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET) + { + /* Clear hot-join flag */ + LL_I3C_ClearFlag_HJ(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_HJ); +#else + /* Asynchronous hot-join event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_HJ); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* ISR controller reception */ + return (I3C_Ctrl_Rx_ISR(hi3c, itMasks)); +} + +/** + * @brief Interrupt Sub-Routine which handles controller multiple transmission/reception and + * Controller received eventsin interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* I3C controller receive IBI event management ---------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET) + { + /* Clear IBI request flag */ + LL_I3C_ClearFlag_IBI(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_IBI); +#else + /* Asynchronous IBI event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_IBI); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* I3C controller controller-role request event management ---------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET) + { + /* Clear controller-role request flag */ + LL_I3C_ClearFlag_CR(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_CR); +#else + /* Asynchronous controller-role event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_CR); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* I3C controller hot-join event management ------------------------------------------------------------------------*/ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET) + { + /* Clear hot-join flag */ + LL_I3C_ClearFlag_HJ(hi3c->Instance); + +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + /* Call registered callback */ + hi3c->NotifyCallback(hi3c, EVENT_ID_HJ); +#else + /* Asynchronous hot-join event Callback */ + HAL_I3C_NotifyCallback(hi3c, EVENT_ID_HJ); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + + /* ISR controller transmission/reception */ + return (I3C_Ctrl_Multiple_Xfer_ISR(hi3c, itMasks)); +} +/** + * @brief Interrupt Sub-Routine which handles controller CCC Dynamic Address Assignment command in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_DAA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + uint64_t target_payload = 0U; + + /* Check that a Dynamic Address Assignment process is ongoing */ + if (hi3c->State == HAL_I3C_STATE_BUSY_DAA) + { + /* I3C Control FIFO not full interrupt Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET) + { + /* Write ENTDAA CCC information in the control register */ + LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_ENTDAA, 0U, LL_I3C_GENERATE_STOP); + } + + /* I3C Tx FIFO not full interrupt Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET) + { + /* Check on the Rx FIFO threshold to know the Dynamic Address Assignment treatment process : byte or word */ + if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4) + { + /* For loop to get target payload */ + for (uint32_t index = 0U; index < 8U; index++) + { + /* Retrieve payload byte by byte */ + target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData8(hi3c->Instance) << (index * 8U)); + } + } + else + { + /* Retrieve first 32 bits payload */ + target_payload = (uint64_t)LL_I3C_ReceiveData32(hi3c->Instance); + + /* Retrieve second 32 bits payload */ + target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData32(hi3c->Instance) << 32U); + } + + /* Call the corresponding callback */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->TgtReqDynamicAddrCallback(hi3c, target_payload); +#else + HAL_I3C_TgtReqDynamicAddrCallback(hi3c, target_payload); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + + /* I3C frame complete event Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + /* Disable Dynamic Address Assignment process interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_CONTROLLER_DAA_IT); + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Call the Dynamic Address Assignment complete callback */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->CtrlDAACpltCallback(hi3c); +#else + HAL_I3C_CtrlDAACpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + } + return HAL_OK; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Interrupt Sub-Routine which handles controller transmit data in DMA mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* Check that a Tx process is ongoing */ + if (hi3c->State == HAL_I3C_STATE_BUSY_TX) + { + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmacr) == 0U) + { + /* Check if all data bytes are transmitted */ + if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmatx) == 0U) + { + /* Disable Tx process interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_DMA); + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Update the number of remaining data bytes */ + hi3c->TxXferCount = 0U; + + /* Call controller transmit complete callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->CtrlTxCpltCallback(hi3c); +#else + HAL_I3C_CtrlTxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_SIZE; + + /* Call error treatment function */ + I3C_ErrorTreatment(hi3c); + } + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Call the transmit complete callback */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->CtrlTxCpltCallback(hi3c); +#else + HAL_I3C_CtrlTxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + + /* Then Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + } + } + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles controller receive data in DMA mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* Check that an Rx process is ongoing */ + if (hi3c->State == HAL_I3C_STATE_BUSY_RX) + { + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmacr) == 0U) + { + /* Check if all data bytes are received */ + if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmarx) == 0U) + { + /* Disable Rx process interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_DMA); + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Update the number of remaining data bytes */ + hi3c->RxXferCount = 0U; + + /* Call controller receive complete callback */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->CtrlRxCpltCallback(hi3c); +#else + HAL_I3C_CtrlRxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_SIZE; + + /* Call error treatment function */ + I3C_ErrorTreatment(hi3c); + } + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Call the receive complete callback */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->CtrlRxCpltCallback(hi3c); +#else + HAL_I3C_CtrlRxCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + + /* Then Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + } + } + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handles controller multiple receive and transmit data in DMA mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* Check that an Rx or Tx process is ongoing */ + if (hi3c->State == HAL_I3C_STATE_BUSY_TX_RX) + { + /* I3C target frame complete event Check */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmacr) == 0U) + { + /* Check if all data bytes are received or transmitted */ + if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmarx) == 0U) + { + if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmatx) == 0U) + { + /* Disable transfer Tx/Rx process interrupts */ + I3C_Disable_IRQ(hi3c, I3C_XFER_DMA); + + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Update the number of remaining data bytes */ + hi3c->RxXferCount = 0U; + + /* Update the number of remaining data bytes */ + hi3c->TxXferCount = 0U; + + /* Call controller transmit, receive complete callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) + hi3c->CtrlMultipleXferCpltCallback(hi3c); +#else + HAL_I3C_CtrlMultipleXferCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_SIZE; + + /* Call error treatment function */ + I3C_ErrorTreatment(hi3c); + } + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_SIZE; + + /* Call error treatment function */ + I3C_ErrorTreatment(hi3c); + } + } + else + { + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + + /* Then Initiate a Start condition */ + LL_I3C_RequestTransfer(hi3c->Instance); + } + } + } + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Interrupt Sub-Routine which handles abort process in interrupt mode. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information + * for the specified I3C. + * @param itMasks : [IN] Flag Interrupt Masks flags to handle. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Abort_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks) +{ + /* Check that an Abort process is ongoing */ + if (hi3c->State == HAL_I3C_STATE_ABORT) + { + /* I3C Rx FIFO not empty interrupt Check */ + if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET) + { + if (LL_I3C_IsActiveFlag_DOVR(hi3c->Instance) == 1U) + { + /* Flush remaining Rx data */ + LL_I3C_RequestRxFIFOFlush(hi3c->Instance); + } + } + + /* I3C Abort frame complete event Check */ + /* Evenif abort is called, the Frame completion can arrive if abort is requested at the end of the processus */ + /* Evenif completion occurs, treat this end of processus as abort completion process */ + if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + /* Call error treatment function */ + I3C_ErrorTreatment(hi3c); + } + } + return HAL_OK; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA I3C control transmit process complete callback. + * @param hdma : [IN] Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA channel. + * @retval None + */ +static void I3C_DMAControlTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Get the address of the I3C handle : Derogation MISRAC2012-Rule-11.5 */ + I3C_HandleTypeDef *hi3c = (I3C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable control DMA Request */ + LL_I3C_DisableDMAReq_Control(hi3c->Instance); +} + +/** + * @brief DMA I3C transmit data process complete callback. + * @param hdma : [IN] Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA channel. + * @retval None + */ +static void I3C_DMADataTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Get the address of the I3C handle : Derogation MISRAC2012-Rule-11.5 */ + I3C_HandleTypeDef *hi3c = (I3C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable Tx DMA Request */ + LL_I3C_DisableDMAReq_TX(hi3c->Instance); +} + +/** + * @brief DMA I3C receive data process complete callback. + * @param hdma : [IN] Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA channel. + * @retval None + */ +static void I3C_DMADataReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Get the address of the I3C handle : Derogation MISRAC2012-Rule-11.5 */ + I3C_HandleTypeDef *hi3c = (I3C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable Rx DMA Request */ + LL_I3C_DisableDMAReq_RX(hi3c->Instance); +} + +/** + * @brief DMA I3C communication error callback. + * @param hdma : [IN] Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA channel. + * @retval None + */ +static void I3C_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Just to solve MisraC error then to be removed */ + /* Derogation MISRAC2012-Rule-11.5 */ + I3C_HandleTypeDef *hi3c = (I3C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + hi3c->ErrorCode |= HAL_I3C_ERROR_DMA; +} + +/** + * @brief DMA I3C communication abort callback to be called at end of DMA Abort procedure. + * @param hdma : [IN] Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA channel. + * @retval None + */ +static void I3C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I3C_HandleTypeDef *hi3c = (I3C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Reset Tx DMA AbortCpltCallback */ + if (hi3c->hdmatx != NULL) + { + hi3c->hdmatx->XferAbortCallback = NULL; + } + + /* Reset Rx DMA AbortCpltCallback */ + if (hi3c->hdmarx != NULL) + { + hi3c->hdmarx->XferAbortCallback = NULL; + } + + /* Reset control DMA AbortCpltCallback */ + if (hi3c->hdmacr != NULL) + { + hi3c->hdmacr->XferAbortCallback = NULL; + } + + I3C_TreatErrorCallback(hi3c); +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief This function handles I3C Communication Timeout. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param flag : [IN] Specifies the I3C flag to check. + * @param flagstatus : [IN] The new Flag status (SET or RESET). + * @param timeout : [IN] Timeout duration in millisecond. + * @param tickstart : [IN] Tick start value + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_WaitOnFlagUntilTimeout(I3C_HandleTypeDef *hi3c, uint32_t flag, FlagStatus flagstatus, + uint32_t timeout, uint32_t tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I3C_GET_FLAG(hi3c, flag) == flagstatus) && (status == HAL_OK)) + { + /* Check for the Timeout */ + if (timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U)) + { + if (__HAL_I3C_GET_FLAG(hi3c, flag) == flagstatus) + { + hi3c->ErrorCode = HAL_I3C_ERROR_TIMEOUT; + status = HAL_TIMEOUT; + } + } + } + + /* Check if an error occurs during Flag waiting */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET) + { + /* Clear error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + /* Update handle error code parameter */ + I3C_GetErrorSources(hi3c); + + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief This function handles I3C Dynamic Address Assignment timeout. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param timeout : [IN] Timeout duration in millisecond. + * @param tickstart : [IN] Tick start value + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_WaitOnDAAUntilTimeout(I3C_HandleTypeDef *hi3c, uint32_t timeout, uint32_t tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t active_flags = READ_REG(hi3c->Instance->EVR); + + while (((active_flags & (HAL_I3C_FLAG_FCF | HAL_I3C_FLAG_TXFNFF)) == 0U) && (status == HAL_OK)) + { + /* Check for the Timeout */ + if (timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U)) + { + if ((active_flags & (HAL_I3C_FLAG_FCF | HAL_I3C_FLAG_TXFNFF)) == 0U) + { + hi3c->ErrorCode |= HAL_I3C_ERROR_TIMEOUT; + status = HAL_TIMEOUT; + } + } + } + + /* Check if an error occurs during Flag waiting */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET) + { + /* Clear error flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + + /* Update handle error code parameter */ + I3C_GetErrorSources(hi3c); + + status = HAL_ERROR; + } + + /* Read active flags from EVR register */ + active_flags = READ_REG(hi3c->Instance->EVR); + } + return status; +} + +/** + * @brief I3C transmit by byte. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @retval None + */ +static void I3C_TransmitByteTreatment(I3C_HandleTypeDef *hi3c) +{ + /* Check TX FIFO not full flag */ + while ((__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_TXFNFF) == SET) && (hi3c->TxXferCount > 0U)) + { + /* Write Tx buffer data to transmit register */ + LL_I3C_TransmitData8(hi3c->Instance, *hi3c->pXferData->TxBuf.pBuffer); + + /* Increment Buffer pointer */ + hi3c->pXferData->TxBuf.pBuffer++; + + /* Decrement remaining bytes counter */ + hi3c->TxXferCount--; + } +} + +/** + * @brief I3C transmit by word. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @retval None + */ +static void I3C_TransmitWordTreatment(I3C_HandleTypeDef *hi3c) +{ + /* Check TX FIFO not full flag */ + while (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_TXFNFF) == SET) + { + /* Write Tx buffer data to transmit register */ + LL_I3C_TransmitData32(hi3c->Instance, *((uint32_t *)hi3c->pXferData->TxBuf.pBuffer)); + + /* Increment Buffer pointer */ + hi3c->pXferData->TxBuf.pBuffer += sizeof(uint32_t); + + if (hi3c->TxXferCount < sizeof(uint32_t)) + { + hi3c->TxXferCount = 0U; + } + else + { + /* Decrement remaining bytes counter */ + hi3c->TxXferCount -= sizeof(uint32_t); + } + } +} + +/** + * @brief I3C receive by byte. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @retval None + */ +static void I3C_ReceiveByteTreatment(I3C_HandleTypeDef *hi3c) +{ + /* Check RX FIFO not empty flag */ + while (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_RXFNEF) == SET) + { + /* Store received bytes in the Rx buffer */ + *hi3c->pXferData->RxBuf.pBuffer = LL_I3C_ReceiveData8(hi3c->Instance); + + /* Increment Buffer pointer */ + hi3c->pXferData->RxBuf.pBuffer++; + + /* Decrement remaining bytes counter */ + hi3c->RxXferCount--; + } +} + +/** + * @brief I3C receive by word. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @retval None + */ +static void I3C_ReceiveWordTreatment(I3C_HandleTypeDef *hi3c) +{ + /* Check RX FIFO not empty flag */ + while (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_RXFNEF) == SET) + { + /* Store received bytes in the Rx buffer */ + *((uint32_t *)hi3c->pXferData->RxBuf.pBuffer) = LL_I3C_ReceiveData32(hi3c->Instance); + + /* Increment Buffer pointer */ + hi3c->pXferData->RxBuf.pBuffer += sizeof(uint32_t); + + if (hi3c->RxXferCount > sizeof(uint32_t)) + { + /* Decrement remaining bytes counter */ + hi3c->RxXferCount -= sizeof(uint32_t); + } + else + { + /* Reset counter as last modulo word Rx data received */ + hi3c->RxXferCount = 0U; + } + } +} + +/** + * @brief I3C Control data treatment. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @retval None + */ +static void I3C_ControlDataTreatment(I3C_HandleTypeDef *hi3c) +{ + /* Check if Control FIFO requests data */ + if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_CFNFF) == SET) + { + /* Decrement remaining control buffer data counter */ + hi3c->ControlXferCount--; + + /* Write Control buffer data to control register */ + WRITE_REG(hi3c->Instance->CR, *hi3c->pXferData->CtrlBuf.pBuffer); + + /* Increment Buffer pointer */ + hi3c->pXferData->CtrlBuf.pBuffer++; + } +} + +/** + * @brief I3C state update. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @retval None + */ +static void I3C_StateUpdate(I3C_HandleTypeDef *hi3c) +{ + /* Check on previous state */ + if (hi3c->PreviousState == HAL_I3C_STATE_LISTEN) + { + /* Set state to listen */ + hi3c->State = HAL_I3C_STATE_LISTEN; + + /* Check the I3C mode */ + if (hi3c->Mode == HAL_I3C_MODE_TARGET) + { + /* Store the target event treatment function */ + hi3c->XferISR = I3C_Tgt_Event_ISR; + } + else + { + /* Store the controller event treatment function */ + hi3c->XferISR = I3C_Ctrl_Event_ISR; + } + } + else + { + /* Set state to ready */ + hi3c->State = HAL_I3C_STATE_READY; + + /* Reset XferISR */ + hi3c->XferISR = NULL; + } +} + +/** + * @brief I3C get error source. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @retval None + */ +static void I3C_GetErrorSources(I3C_HandleTypeDef *hi3c) +{ + /* Check on the I3C mode */ + switch (hi3c->Mode) + { + case HAL_I3C_MODE_CONTROLLER: + { + /* I3C data error during controller-role hand-off procedure */ + if (LL_I3C_IsActiveFlag_DERR(hi3c->Instance) == 1U) + { + hi3c->ErrorCode |= HAL_I3C_ERROR_DATA_HAND_OFF; + } + + /* I3C data not acknowledged error */ + if (LL_I3C_IsActiveFlag_DNACK(hi3c->Instance) == 1U) + { + hi3c->ErrorCode |= HAL_I3C_ERROR_DATA_NACK; + } + + /* I3C address not acknowledged error */ + if (LL_I3C_IsActiveFlag_ANACK(hi3c->Instance) == 1U) + { + hi3c->ErrorCode |= HAL_I3C_ERROR_ADDRESS_NACK; + } + + /* I3C Status FIFO Over-Run or Control FIFO Under-Run error */ + if (LL_I3C_IsActiveFlag_COVR(hi3c->Instance) == 1U) + { + hi3c->ErrorCode |= HAL_I3C_ERROR_COVR; + } + + break; + } + + case HAL_I3C_MODE_TARGET: + { + /* I3C SCL stall error */ + if (LL_I3C_IsActiveFlag_STALL(hi3c->Instance) == 1U) + { + hi3c->ErrorCode |= HAL_I3C_ERROR_STALL; + } + + break; + } + + default: + { + break; + } + } + + /* I3C Rx FIFO Over-Run or Tx FIFO Under-Run error */ + if (LL_I3C_IsActiveFlag_DOVR(hi3c->Instance) == 1U) + { + hi3c->ErrorCode |= HAL_I3C_ERROR_DOVR; + } + + /* I3C Protocol error */ + if (LL_I3C_IsActiveFlag_PERR(hi3c->Instance) == 1U) + { + hi3c->ErrorCode |= (I3C_SER_PERR | LL_I3C_GetMessageErrorCode(hi3c->Instance)); + } +} + +/** + * @brief I3C transfer prior preparation. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param counter : [IN] Number of devices or commands to treat. + * @param option : [IN] Parameter indicates the transfer option. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Xfer_PriorPreparation(I3C_HandleTypeDef *hi3c, uint8_t counter, uint32_t option) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t current_tx_index = 0U; + uint32_t global_tx_size = 0U; + uint32_t global_rx_size = 0U; + uint32_t nb_tx_frame = 0U; + uint32_t direction; + + for (uint32_t descr_index = 0U; descr_index < counter; descr_index++) + { + /* Direct CCC command */ + if ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_DIRECT) + { + /* Update direction of frame */ + direction = hi3c->pCCCDesc[descr_index].Direction; + + /* Direction read with Define byte */ + if (((option & I3C_DEFINE_BYTE_MASK) != 0U) && (direction == HAL_I3C_DIRECTION_READ)) + { + nb_tx_frame += 1U; + + global_tx_size += 1U; + + global_rx_size += hi3c->pCCCDesc[descr_index].CCCBuf.Size - 1U; + + /* Check on the global size and on the Tx buffer pointer */ + if ((global_tx_size > hi3c->pXferData->TxBuf.Size) || \ + (current_tx_index > hi3c->pXferData->TxBuf.Size) || \ + (hi3c->pXferData->TxBuf.pBuffer == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + + status = HAL_ERROR; + } + else + { + /* Fill global Tx buffer with data and update the current index of the Tx buffer */ + current_tx_index = I3C_FillTxBuffer_CCC(hi3c, descr_index, 1U, current_tx_index); + } + } + else if (direction == HAL_I3C_DIRECTION_WRITE) + { + nb_tx_frame += 1U; + + global_tx_size += hi3c->pCCCDesc[descr_index].CCCBuf.Size; + + /* Check on the global size and on the Tx buffer pointer */ + if ((global_tx_size > hi3c->pXferData->TxBuf.Size) || \ + (current_tx_index > hi3c->pXferData->TxBuf.Size) || \ + (hi3c->pXferData->TxBuf.pBuffer == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + + status = HAL_ERROR; + } + else + { + /* Fill global Tx buffer with data and update the current index of the Tx buffer */ + current_tx_index = I3C_FillTxBuffer_CCC(hi3c, + descr_index, + hi3c->pCCCDesc[descr_index].CCCBuf.Size, + current_tx_index); + } + } + /* Direction read without Define byte */ + else + { + global_rx_size += hi3c->pCCCDesc[descr_index].CCCBuf.Size; + } + } + /* Broadcast CCC command */ + else if ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_CCC) + { + /* Update direction of frame */ + direction = hi3c->pCCCDesc[descr_index].Direction; + + if (direction == HAL_I3C_DIRECTION_WRITE) + { + nb_tx_frame += 1U; + + global_tx_size += hi3c->pCCCDesc[descr_index].CCCBuf.Size; + + /* Check on the global size and on the Tx buffer pointer */ + if ((global_tx_size > hi3c->pXferData->TxBuf.Size) || \ + (current_tx_index > hi3c->pXferData->TxBuf.Size) || \ + (hi3c->pXferData->TxBuf.pBuffer == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + + status = HAL_ERROR; + } + else + { + /* Fill global Tx buffer with data and update the current index of the Tx buffer */ + current_tx_index = I3C_FillTxBuffer_CCC(hi3c, + descr_index, + hi3c->pCCCDesc[descr_index].CCCBuf.Size, + current_tx_index); + } + } + else + { + status = HAL_ERROR; + } + } + /* Private */ + else + { + /* Update direction of frame */ + direction = hi3c->pPrivateDesc[descr_index].Direction; + + if (direction == HAL_I3C_DIRECTION_WRITE) + { + nb_tx_frame += 1U; + + global_tx_size += hi3c->pPrivateDesc[descr_index].TxBuf.Size; + + /* Check on the global size and on the Tx buffer pointer */ + if ((global_tx_size > hi3c->pXferData->TxBuf.Size) || \ + (current_tx_index > hi3c->pXferData->TxBuf.Size) || \ + (hi3c->pXferData->TxBuf.pBuffer == NULL)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + + status = HAL_ERROR; + } + else + { + /* Fill global Tx buffer with data and update the current index of the Tx buffer */ + current_tx_index = I3C_FillTxBuffer_Private(hi3c, + descr_index, + hi3c->pPrivateDesc[descr_index].TxBuf.Size, + current_tx_index); + } + } + else + { + global_rx_size += hi3c->pPrivateDesc[descr_index].RxBuf.Size; + } + } + + /* Check if there is an error in the Tx Buffer*/ + if (status == HAL_ERROR) + { + break; + } + } + + if (status == HAL_OK) + { + /* Check on the Tx threshold and the number of Tx frame */ + if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_4_4) + { + /* LL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains + multiple transmission frames */ + if (nb_tx_frame > 1U) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + } + } + + if (status == HAL_OK) + { + /* Check on the size Rx buffer */ + if (global_rx_size > hi3c->pXferData->RxBuf.Size) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hi3c->RxXferCount = global_rx_size; + } + + /* Set handle transfer parameters */ + hi3c->TxXferCount = global_tx_size; + } + + return status; +} + +/** + * @brief I3C fill Tx Buffer with data from CCC Descriptor. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param indexDesc : [IN] Index of descriptor. + * @param txSize : [IN] Size of Tx data. + * @param txCurrentIndex : [IN] Current Index of TxBuffer. + * @retval index_tx : [OUT] New current Index of TxBuffer. + */ +static uint32_t I3C_FillTxBuffer_CCC(I3C_HandleTypeDef *hi3c, + uint32_t indexDesc, + uint32_t txSize, + uint32_t txCurrentIndex) +{ + uint32_t index_tx = txCurrentIndex; + + for (uint32_t index = 0U; index < txSize; index++) + { + hi3c->pXferData->TxBuf.pBuffer[index_tx] = hi3c->pCCCDesc[indexDesc].CCCBuf.pBuffer[index]; + + index_tx++; + } + + return index_tx; +} + +/** + * @brief I3C fill Tx Buffer with data from Private Descriptor. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param indexDesc : [IN] Index of descriptor. + * @param txSize : [IN] Size of Tx data. + * @param txCurrentIndex : [IN] Current Index of TxBuffer. + * @retval index_tx : [OUT] New current Index of TxBuffer. + */ +static uint32_t I3C_FillTxBuffer_Private(I3C_HandleTypeDef *hi3c, + uint32_t indexDesc, + uint32_t txSize, + uint32_t txCurrentIndex) +{ + uint32_t index_tx = txCurrentIndex; + + for (uint32_t index = 0U; index < txSize; index++) + { + hi3c->pXferData->TxBuf.pBuffer[index_tx] = hi3c->pPrivateDesc[indexDesc].TxBuf.pBuffer[index]; + + index_tx++; + } + + return index_tx; +} + +/** + * @brief I3C Control buffer prior preparation. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param counter : [IN] Number of devices or commands to treat. + * @param option : [IN] Parameter indicates the transfer option. + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_ControlBuffer_PriorPreparation(I3C_HandleTypeDef *hi3c, + uint8_t counter, + uint32_t option) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t nb_define_bytes; + uint32_t stop_condition; + uint32_t nb_data_bytes; + uint32_t index; + + /* Check on the control buffer pointer */ + if (hi3c->pXferData->CtrlBuf.pBuffer == NULL) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + /* Extract from option required information */ + nb_define_bytes = (option & I3C_DEFINE_BYTE_MASK); + stop_condition = (option & I3C_RESTART_STOP_MASK); + + /* Check on the deactivation of the arbitration */ + if ((option & I3C_ARBITRATION_HEADER_MASK) == I3C_ARBITRATION_HEADER_MASK) + { + /* Disable arbitration header */ + LL_I3C_DisableArbitrationHeader(hi3c->Instance); + } + else + { + /* Enable arbitration header */ + LL_I3C_EnableArbitrationHeader(hi3c->Instance); + } + + /* Check on the operation type */ + if ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_CCC) + { + /*------------------------------------------ Broadcast CCC -----------------------------------------------------*/ + /* Check on the control buffer size */ + if (hi3c->pXferData->CtrlBuf.Size < (uint32_t)counter) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + /* Set remaining control buffer data counter */ + hi3c->ControlXferCount = (uint32_t)counter; + + /* For loop on the number of commands */ + for (index = 0U; index < ((uint32_t)counter - 1U); index++) + { + /* Update control buffer value */ + hi3c->pXferData->CtrlBuf.pBuffer[index] = ((uint32_t)hi3c->pCCCDesc[index].CCCBuf.Size | + ((uint32_t)hi3c->pCCCDesc[index].CCC << I3C_CR_CCC_Pos) | + LL_I3C_CONTROLLER_MTYPE_CCC | stop_condition); + } + + /* At the last device we should generate a stop condition */ + hi3c->pXferData->CtrlBuf.pBuffer[index] = ((uint32_t)hi3c->pCCCDesc[index].CCCBuf.Size | + ((uint32_t)hi3c->pCCCDesc[index].CCC << I3C_CR_CCC_Pos) | + LL_I3C_CONTROLLER_MTYPE_CCC | LL_I3C_GENERATE_STOP); + } + } + else if ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_DIRECT) + { + /*------------------------------------------ Direct CCC --------------------------------------------------------*/ + /* Check on the control buffer size */ + if (hi3c->pXferData->CtrlBuf.Size < ((uint32_t)counter * 2U)) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + /* Set remaining control buffer data counter */ + hi3c->ControlXferCount = ((uint32_t)counter * 2U); + + /* For loop on the number of (devices or commands) * 2 */ + for (index = 0U; index < (((uint32_t)counter * 2U) - 2U); index += 2U) + { + /* Step 1 : update control buffer value for the CCC command */ + hi3c->pXferData->CtrlBuf.pBuffer[index] = (nb_define_bytes | + ((uint32_t)hi3c->pCCCDesc[index / 2U].CCC << I3C_CR_CCC_Pos) | + LL_I3C_CONTROLLER_MTYPE_CCC | LL_I3C_GENERATE_RESTART); + + /* Step 2 : update control buffer value for target address */ + hi3c->pXferData->CtrlBuf.pBuffer[index + 1U] = + (((uint32_t)hi3c->pCCCDesc[index / 2U].CCCBuf.Size - nb_define_bytes) | + hi3c->pCCCDesc[index / 2U].Direction | + ((uint32_t)hi3c->pCCCDesc[index / 2U].TargetAddr << I3C_CR_ADD_Pos) | + LL_I3C_CONTROLLER_MTYPE_DIRECT | stop_condition); + } + + /* Update control buffer value for the last CCC command */ + hi3c->pXferData->CtrlBuf.pBuffer[index] = (nb_define_bytes | + ((uint32_t)hi3c->pCCCDesc[index / 2U].CCC << I3C_CR_CCC_Pos) | + LL_I3C_CONTROLLER_MTYPE_CCC | LL_I3C_GENERATE_RESTART); + + /* At the last device we should generate a stop condition */ + hi3c->pXferData->CtrlBuf.pBuffer[index + 1U] = + (((uint32_t)hi3c->pCCCDesc[index / 2U].CCCBuf.Size - nb_define_bytes) | + hi3c->pCCCDesc[index / 2U].Direction | + ((uint32_t)hi3c->pCCCDesc[index / 2U].TargetAddr << I3C_CR_ADD_Pos) | + LL_I3C_CONTROLLER_MTYPE_DIRECT | LL_I3C_GENERATE_STOP); + } + } + else + { + /*------------------------------------------ Private I3C/I2C ---------------------------------------------------*/ + /* Check on the control buffer size */ + if (hi3c->pXferData->CtrlBuf.Size < (uint32_t)counter) + { + hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + /* Set remaining control buffer data counter */ + hi3c->ControlXferCount = (uint32_t)counter; + + /* For loop on the number of devices */ + for (index = 0U; index < ((uint32_t)counter - 1U); index++) + { + /* Check on transfer direction */ + if (hi3c->pPrivateDesc[index].Direction == HAL_I3C_DIRECTION_READ) + { + nb_data_bytes = hi3c->pPrivateDesc[index].RxBuf.Size; + } + else + { + nb_data_bytes = hi3c->pPrivateDesc[index].TxBuf.Size; + } + + /* Update control buffer value */ + hi3c->pXferData->CtrlBuf.pBuffer[index] = + (nb_data_bytes | hi3c->pPrivateDesc[index].Direction | + ((uint32_t)hi3c->pPrivateDesc[index].TargetAddr << I3C_CR_ADD_Pos) | + (option & I3C_OPERATION_TYPE_MASK) | stop_condition); + } + + /* Check on transfer direction */ + if (hi3c->pPrivateDesc[index].Direction == HAL_I3C_DIRECTION_READ) + { + nb_data_bytes = hi3c->pPrivateDesc[index].RxBuf.Size; + } + else + { + nb_data_bytes = hi3c->pPrivateDesc[index].TxBuf.Size; + } + + /* At the last device we should generate a stop condition */ + hi3c->pXferData->CtrlBuf.pBuffer[index] = + (nb_data_bytes | hi3c->pPrivateDesc[index].Direction | + ((uint32_t)hi3c->pPrivateDesc[index].TargetAddr << I3C_CR_ADD_Pos) | + (option & I3C_OPERATION_TYPE_MASK) | LL_I3C_GENERATE_STOP); + } + } + } + + return status; +} + +/** + * @brief Check if target device is ready for communication. + * @param hi3c : Pointer to a I3C_HandleTypeDef structure that contains + * the configuration information for the specified I3C. + * @param pDevice : [IN] Structure to define the device address and the device type. + * @param trials : [IN] Number of trials + * @param timeout : [IN] Timeout duration + * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. + */ +static HAL_StatusTypeDef I3C_Ctrl_IsDevice_Ready(I3C_HandleTypeDef *hi3c, + const I3C_DeviceTypeDef *pDevice, + uint32_t trials, + uint32_t timeout) +{ + __IO uint32_t I3C_Trials = 0UL; + __IO uint32_t exit_condition; + uint32_t CR_tmp; + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + HAL_I3C_StateTypeDef handle_state; + uint32_t arbitration_previous_state; + + /* Get I3C handle state */ + handle_state = hi3c->State; + + /* check on the Mode */ + if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER) + { + hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED; + status = HAL_ERROR; + } + /* check on the State */ + else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN)) + { + status = HAL_BUSY; + } + else + { + /* Set handle transfer parameters */ + hi3c->ErrorCode = HAL_I3C_ERROR_NONE; + hi3c->State = HAL_I3C_STATE_BUSY; + + /* Before modify the arbitration, get the current arbitration state */ + arbitration_previous_state = LL_I3C_IsEnabledArbitrationHeader(hi3c->Instance); + + /* Disable arbitration header */ + LL_I3C_DisableArbitrationHeader(hi3c->Instance); + + CR_tmp = (HAL_I3C_DIRECTION_WRITE | + ((uint32_t)pDevice->Address << I3C_CR_ADD_Pos) | + pDevice->MessageType | LL_I3C_GENERATE_STOP); + + do + { + /* Initiate a start condition by writing in the CR register */ + WRITE_REG(hi3c->Instance->CR, CR_tmp); + + /* Calculate exit_condition value based on Frame complete and error flags */ + exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)); + + tickstart = HAL_GetTick(); + + while (exit_condition == 0U) + { + if (timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U)) + { + /* Update I3C error code */ + hi3c->ErrorCode |= HAL_I3C_ERROR_TIMEOUT; + status = HAL_TIMEOUT; + + break; + } + } + /* Calculate exit_condition value based on Frame complete and error flags */ + exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)); + } + + if (status == HAL_OK) + { + /* Check if the FCF flag has been set */ + if (__HAL_I3C_GET_FLAG(hi3c, I3C_EVR_FCF) == SET) + { + /* Clear frame complete flag */ + LL_I3C_ClearFlag_FC(hi3c->Instance); + + /* Device is ready */ + break; + } + else + { + /* Clear ERR flag */ + LL_I3C_ClearFlag_ERR(hi3c->Instance); + } + } + + /* Increment Trials */ + I3C_Trials++; + + } while ((I3C_Trials < trials) && (status == HAL_OK)); + + /* Device is not ready */ + if (trials == I3C_Trials) + { + hi3c->ErrorCode = HAL_I3C_ERROR_ADDRESS_NACK; + status = HAL_ERROR; + } + + /* update state to Previous state */ + I3C_StateUpdate(hi3c); + + /* Check if previous arbitration state is enabled */ + if (arbitration_previous_state == 1U) + { + LL_I3C_EnableArbitrationHeader(hi3c->Instance); + } + } + + return status; +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param InterruptRequest : [IN] Value of the interrupt request + * @retval None + */ +static void I3C_Enable_IRQ(I3C_HandleTypeDef *hi3c, uint32_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + /* Check if requested interrupts are related to listening mode */ + if ((InterruptRequest & I3C_XFER_LISTEN_IT) != 0U) + { + tmpisr |= ((InterruptRequest & (~I3C_XFER_LISTEN_IT)) | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to target transmit in IT mode */ + if ((InterruptRequest & I3C_XFER_TARGET_TX_IT) != 0U) + { + /* Enable frame complete, transmit FIFO not full and error interrupts */ + tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to target receive in IT mode */ + if ((InterruptRequest & I3C_XFER_TARGET_RX_IT) != 0U) + { + /* Enable frame complete, receive FIFO not empty and error interrupts */ + tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_RXFNEIE | HAL_I3C_IT_ERRIE) ; + } + + /* Check if requested interrupts are related to transmit/receive in DMA mode */ + if ((InterruptRequest & I3C_XFER_DMA) != 0U) + { + /* Enable frame complete and error interrupts */ + tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to target hot join */ + if ((InterruptRequest & I3C_XFER_TARGET_HOTJOIN) != 0U) + { + /* Enable dynamic address update and error interrupts */ + tmpisr |= (HAL_I3C_IT_DAUPDIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to target control role */ + if ((InterruptRequest & I3C_XFER_TARGET_CTRLROLE) != 0U) + { + /* Enable control role update and error interrupts */ + tmpisr |= (HAL_I3C_IT_CRUPDIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to target in band interrupt */ + if ((InterruptRequest & I3C_XFER_TARGET_IBI) != 0U) + { + /* Enable IBI end and error interrupts */ + tmpisr |= (HAL_I3C_IT_IBIENDIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to controller transmit in IT mode */ + if ((InterruptRequest & I3C_XFER_CONTROLLER_TX_IT) != 0U) + { + /* Enable frame complete, control FIFO not full, transmit FIFO not full and error interrupts */ + tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_CFNFIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to controller receive in IT mode */ + if ((InterruptRequest & I3C_XFER_CONTROLLER_RX_IT) != 0U) + { + /* Enable frame complete, control FIFO not full, receive FIFO not empty and error interrupts */ + tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_CFNFIE | HAL_I3C_IT_RXFNEIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to controller transmit read or a broadcast CCC in IT mode */ + if ((InterruptRequest & I3C_XFER_CONTROLLER_RX_CCC_IT) != 0U) + { + /* Enable frame complete, transmit FIFO not full, control FIFO not full, + receive FIFO not empty and error interrupts */ + tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_CFNFIE | HAL_I3C_IT_RXFNEIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to controller transmit broadcast ENTDAA CCC in IT mode */ + if ((InterruptRequest & I3C_XFER_CONTROLLER_DAA_IT) != 0U) + { + /* Enable frame complete, control FIFO not full, transmit FIFO not full and error interrupts */ + tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_CFNFIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_ERRIE); + } + + /* Enable requested interrupts */ + __HAL_I3C_ENABLE_IT(hi3c, tmpisr); +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @param InterruptRequest : [IN] Value of the interrupt request + * @retval None + */ +static void I3C_Disable_IRQ(I3C_HandleTypeDef *hi3c, uint32_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + /* Check if requested interrupts are related to listening mode */ + if ((InterruptRequest & I3C_XFER_LISTEN_IT) != 0U) + { + tmpisr |= ((InterruptRequest & (~I3C_XFER_LISTEN_IT)) | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to target transmit mode */ + if ((InterruptRequest & I3C_XFER_TARGET_TX_IT) != 0U) + { + /* Disable frame complete, transmit FIFO not full and error interrupts */ + tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to target receive mode */ + if ((InterruptRequest & I3C_XFER_TARGET_RX_IT) != 0U) + { + /* Disable frame complete, receive FIFO not empty and error interrupts */ + tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_RXFNEIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to transmit/receive in DMA mode */ + if ((InterruptRequest & I3C_XFER_DMA) != 0U) + { + /* Disable frame complete and error interrupts */ + tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to target hot join */ + if ((InterruptRequest & I3C_XFER_TARGET_HOTJOIN) != 0U) + { + /* Disable dynamic address update and error interrupts */ + tmpisr |= (HAL_I3C_IT_DAUPDIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to target control role */ + if ((InterruptRequest & I3C_XFER_TARGET_CTRLROLE) != 0U) + { + /* Disable control role update and error interrupts */ + tmpisr |= (HAL_I3C_IT_CRUPDIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to target in band interrupt */ + if ((InterruptRequest & I3C_XFER_TARGET_IBI) != 0U) + { + /* Disable IBI end and error interrupts */ + tmpisr |= (HAL_I3C_IT_IBIENDIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to controller transmit in IT mode */ + if ((InterruptRequest & I3C_XFER_CONTROLLER_TX_IT) != 0U) + { + /* Disable frame complete, control FIFO not full, transmit FIFO not full and error interrupts */ + tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_CFNFIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to controller transmit read or a broadcast CCC in IT mode */ + if ((InterruptRequest & I3C_XFER_CONTROLLER_RX_CCC_IT) != 0U) + { + /* Disable frame complete, transmit FIFO not full, control FIFO not full, + receive FIFO not empty and error interrupts */ + tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_CFNFIE | HAL_I3C_IT_RXFNEIE | HAL_I3C_IT_ERRIE); + } + + /* Check if requested interrupts are related to controller transmit broadcast ENTDAA CCC in IT mode */ + if ((InterruptRequest & I3C_XFER_CONTROLLER_DAA_IT) != 0U) + { + /* Disable frame complete, control FIFO not full, transmit FIFO not full and error interrupts */ + tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_CFNFIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_ERRIE); + } + + /* Disable requested interrupts */ + __HAL_I3C_DISABLE_IT(hi3c, tmpisr); +} + +/** + * @brief I3C error treatment. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @retval None + */ +static void I3C_ErrorTreatment(I3C_HandleTypeDef *hi3c) +{ + HAL_I3C_StateTypeDef tmpstate = hi3c->State; + uint32_t dmaabortongoing = 0U; + + /* Check on the state */ + if (tmpstate == HAL_I3C_STATE_BUSY) + { + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + /* Disable all interrupts related to busy state */ + I3C_Disable_IRQ(hi3c, (I3C_XFER_TARGET_IBI | I3C_XFER_TARGET_HOTJOIN | I3C_XFER_TARGET_CTRLROLE)); + } + else + { + /* Disable all interrupts related to busy Tx and Rx state */ + I3C_Disable_IRQ(hi3c, I3C_XFER_CONTROLLER_RX_CCC_IT); + + /* Reset Tx counter */ + hi3c->TxXferCount = 0U; + + /* Reset Rx counter */ + hi3c->RxXferCount = 0U; + + /* Reset Control counter */ + hi3c->ControlXferCount = 0U; + + /* Reset Tx function pointer */ + hi3c->ptrTxFunc = NULL; + + /* Reset Rx function pointer */ + hi3c->ptrRxFunc = NULL; + + /* Reset Context pointer */ + hi3c->pXferData = NULL; + hi3c->pCCCDesc = NULL; + hi3c->pPrivateDesc = NULL; + + /* Flush all FIFOs */ + /* Flush the content of Tx Fifo */ + LL_I3C_RequestTxFIFOFlush(hi3c->Instance); + + /* Flush the content of Rx Fifo */ + LL_I3C_RequestRxFIFOFlush(hi3c->Instance); + + /* Check on the I3C mode: Control and status FIFOs available only with controller mode */ + if (hi3c->Mode == HAL_I3C_MODE_CONTROLLER) + { + /* Flush the content of Control Fifo */ + LL_I3C_RequestControlFIFOFlush(hi3c->Instance); + + /* Flush the content of Status Fifo */ + LL_I3C_RequestStatusFIFOFlush(hi3c->Instance); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort control DMA transfer if any */ + if (hi3c->hdmacr != NULL) + { + /* Disable control DMA Request */ + LL_I3C_DisableDMAReq_Control(hi3c->Instance); + + /* Check DMA state */ + if (HAL_DMA_GetState(hi3c->hdmacr) != HAL_DMA_STATE_READY) + { + /* Set the I3C DMA Abort callback : will lead to call HAL_I3C_AbortCpltCallback() + at end of DMA abort procedure */ + + /* DMA abort on going */ + dmaabortongoing = 1U; + + /* Abort control DMA */ + if (HAL_DMA_Abort_IT(hi3c->hdmacr) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi3c->hdmacr->XferAbortCallback(hi3c->hdmacr); + } + } + } + + /* Abort RX DMA transfer if any */ + if (hi3c->hdmarx != NULL) + { + /* Disable Rx DMA Request */ + LL_I3C_DisableDMAReq_RX(hi3c->Instance); + + /* Check DMA state */ + if (HAL_DMA_GetState(hi3c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I3C DMA Abort callback : will lead to call HAL_I3C_AbortCpltCallback() + at end of DMA abort procedure */ + hi3c->hdmarx->XferAbortCallback = I3C_DMAAbort; + + /* DMA abort on going */ + dmaabortongoing = 1U; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi3c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi3c->hdmarx->XferAbortCallback(hi3c->hdmarx); + } + } + } + + /* Abort TX DMA transfer if any */ + if (hi3c->hdmatx != NULL) + { + /* Disable Tx DMA Request */ + LL_I3C_DisableDMAReq_TX(hi3c->Instance); + + /* Check DMA state */ + if (HAL_DMA_GetState(hi3c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I3C DMA Abort callback : will lead to call HAL_I3C_AbortCpltCallback() + at end of DMA abort procedure */ + hi3c->hdmatx->XferAbortCallback = I3C_DMAAbort; + + /* DMA abort on going */ + dmaabortongoing = 1U; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi3c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi3c->hdmatx->XferAbortCallback(hi3c->hdmatx); + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + + /* Call Error callback if there is no DMA abort on going */ + if (dmaabortongoing == 0U) + { + I3C_TreatErrorCallback(hi3c); + } +} + +/** + * @brief I3C Error callback treatment. + * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration + * information for the specified I3C. + * @retval None + */ +static void I3C_TreatErrorCallback(I3C_HandleTypeDef *hi3c) +{ + if (hi3c->State == HAL_I3C_STATE_ABORT) + { + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->AbortCpltCallback(hi3c); +#else + HAL_I3C_AbortCpltCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } + else + { + /* Update handle state parameter */ + I3C_StateUpdate(hi3c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1) + hi3c->ErrorCallback(hi3c); +#else + HAL_I3C_ErrorCallback(hi3c); +#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ + } +} + +/** + * @} + */ + +#endif /* HAL_I3C_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_icache.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_icache.c new file mode 100644 index 00000000000..e46b8a0574c --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_icache.c @@ -0,0 +1,512 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_icache.c + * @author MCD Application Team + * @brief ICACHE HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Instruction Cache (ICACHE). + * + Initialization and Configuration + * + Invalidate functions + * + Monitoring management + * + Memory address remap management + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### ICACHE main features ##### + ============================================================================== + [..] + The Texture Cache (ICACHE) is introduced on AXI read-only texture port of + the GPU2D to improve performance when reading texture data from internal and + external memories. + + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The ICACHE HAL driver can be used as follows: + + (#) Optionally configure the Instruction Cache mode with + HAL_ICACHE_ConfigAssociativityMode() if the default configuration + does not suit the application requirements. + + (#) Enable and disable the Instruction Cache with respectively + HAL_ICACHE_Enable() and HAL_ICACHE_Disable(). + Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status. + To ensure a deterministic cache behavior after power on, system reset or after + a call to @ref HAL_ICACHE_Disable(), the application must call + @ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset + or cache disable, an automatic cache invalidation procedure is launched and the + cache is bypassed until the operation completes. + + (#) Initiate the cache maintenance invalidation procedure with either + HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT() + (interrupt mode). When interrupt mode is used, the callback function + HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate + procedure is complete. The function HAL_ICACHE_WaitForInvalidateComplete() + may be called to wait for the end of the invalidate procedure automatically + initiated when disabling the Instruction Cache with HAL_ICACHE_Disable(). + The cache operation is bypassed during the invalidation procedure. + + (#) Use the performance monitoring counters for Hit and Miss with the following + functions: HAL_ICACHE_Monitor_Start(), HAL_ICACHE_Monitor_Stop(), + HAL_ICACHE_Monitor_Reset(), HAL_ICACHE_Monitor_GetHitValue() and + HAL_ICACHE_Monitor_GetMissValue() + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup ICACHE ICACHE + * @brief HAL ICACHE module driver + * @{ + */ +#if defined(ICACHE) && defined (HAL_ICACHE_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup ICACHE_Private_Constants ICACHE Private Constants + * @{ + */ +#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */ +#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ICACHE_Private_Macros ICACHE Private Macros + * @{ + */ + +#define IS_ICACHE_ASSOCIATIVITY_MODE(__MODE__) (((__MODE__) == ICACHE_1WAY) || \ + ((__MODE__) == ICACHE_4WAYS)) + +#define IS_ICACHE_MONITOR_TYPE(__TYPE__) (((__TYPE__) == ICACHE_MONITOR_HIT_MISS) || \ + ((__TYPE__) == ICACHE_MONITOR_HIT) || \ + ((__TYPE__) == ICACHE_MONITOR_MISS)) + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup ICACHE_Exported_Functions ICACHE Exported Functions + * @{ + */ + +/** @defgroup ICACHE_Exported_Functions_Group1 Initialization and control functions + * @brief Initialization and control functions + * + @verbatim + ============================================================================== + ##### Initialization and control functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize and control the + Instruction Cache (mode, invalidate procedure, performance counters). + @endverbatim + * @{ + */ + +/** + * @brief Configure the Instruction Cache cache associativity mode selection. + * @param AssociativityMode Associativity mode selection + * This parameter can be one of the following values: + * @arg ICACHE_1WAY 1-way cache (direct mapped cache) + * @arg ICACHE_4WAYS 4-ways set associative cache (default) + * @retval HAL status (HAL_OK/HAL_ERROR) + */ +HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ICACHE_ASSOCIATIVITY_MODE(AssociativityMode)); + + /* Check cache is not enabled */ + if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + status = HAL_ERROR; + } + else + { + MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, AssociativityMode); + } + + return status; +} + +/** + * @brief DeInitialize the Instruction Cache. + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_DeInit(void) +{ + /* Reset interrupt enable value */ + WRITE_REG(ICACHE->IER, 0U); + + /* Clear any pending flags */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); + + /* Disable cache then set default associative mode value */ + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); + WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL); + + /* Stop monitor and reset monitor values */ + CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS); + SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); + CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); + + + return HAL_OK; +} + +/** + * @brief Enable the Instruction Cache. + * @note This function always returns HAL_OK even if there is any ongoing + * cache operation. The Instruction Cache is bypassed until the + * cache operation completes. + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Enable(void) +{ + SET_BIT(ICACHE->CR, ICACHE_CR_EN); + + return HAL_OK; +} + +/** + * @brief Disable the Instruction Cache. + * @note This function waits for the cache being disabled but + * not for the end of the automatic cache invalidation procedure. + * @retval HAL status (HAL_OK/HAL_TIMEOUT) + */ +HAL_StatusTypeDef HAL_ICACHE_Disable(void) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Make sure BSYENDF is reset before to disable the instruction cache */ + /* as it automatically starts a cache invalidation procedure */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for instruction cache being disabled */ + while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + status = HAL_TIMEOUT; + break; + } + } + } + + return status; +} + +/** + * @brief Check whether the Instruction Cache is enabled or not. + * @retval Status (0: disabled, 1: enabled) + */ +uint32_t HAL_ICACHE_IsEnabled(void) +{ + return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL); +} + +/** + * @brief Invalidate the Instruction Cache. + * @note This function waits for the end of cache invalidation procedure + * and clears the associated BSYENDF flag. + * @retval HAL status (HAL_OK/HAL_ERROR/HAL_TIMEOUT) + */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate(void) +{ + HAL_StatusTypeDef status; + + /* Check if no ongoing operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U) + { + /* Launch cache invalidation */ + SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); + } + + status = HAL_ICACHE_WaitForInvalidateComplete(); + + return status; +} + +/** + * @brief Invalidate the Instruction Cache with interrupt. + * @note This function launches cache invalidation and returns. + * User application shall resort to interrupt generation to check + * the end of the cache invalidation with the BSYENDF flag and the + * HAL_ICACHE_InvalidateCompleteCallback() callback. + * @retval HAL status (HAL_OK/HAL_ERROR) + */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check no ongoing operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Make sure BSYENDF is reset before to start cache invalidation */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + /* Enable end of cache invalidation interrupt */ + SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); + + /* Launch cache invalidation */ + SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); + } + + return status; +} + +/** + * @brief Wait for the end of the Instruction Cache invalidate procedure. + * @note This function checks and clears the BSYENDF flag when set. + * @retval HAL status (HAL_OK/HAL_TIMEOUT) + */ +HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Check if ongoing invalidation operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for end of cache invalidation */ + while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U) + { + if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U) + { + status = HAL_TIMEOUT; + break; + } + } + } + } + + /* Clear BSYENDF */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + return status; +} + + +/** + * @brief Start the Instruction Cache performance monitoring. + * @param MonitorType Monitoring type + * This parameter can be one of the following values: + * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring + * @arg ICACHE_MONITOR_HIT Hit monitoring + * @arg ICACHE_MONITOR_MISS Miss monitoring + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType) +{ + /* Check the parameters */ + assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); + + SET_BIT(ICACHE->CR, MonitorType); + + return HAL_OK; +} + +/** + * @brief Stop the Instruction Cache performance monitoring. + * @note Stopping the monitoring does not reset the values. + * @param MonitorType Monitoring type + * This parameter can be one of the following values: + * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring + * @arg ICACHE_MONITOR_HIT Hit monitoring + * @arg ICACHE_MONITOR_MISS Miss monitoring + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType) +{ + /* Check the parameters */ + assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); + + CLEAR_BIT(ICACHE->CR, MonitorType); + + return HAL_OK; +} + +/** + * @brief Reset the Instruction Cache performance monitoring values. + * @param MonitorType Monitoring type + * This parameter can be one of the following values: + * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring + * @arg ICACHE_MONITOR_HIT Hit monitoring + * @arg ICACHE_MONITOR_MISS Miss monitoring + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType) +{ + /* Check the parameters */ + assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); + + /* Force/Release reset */ + SET_BIT(ICACHE->CR, (MonitorType << 2U)); + CLEAR_BIT(ICACHE->CR, (MonitorType << 2U)); + + return HAL_OK; +} + +/** + * @brief Get the Instruction Cache performance Hit monitoring value. + * @note Upon reaching the 32-bit maximum value, monitor does not wrap. + * @retval Hit monitoring value + */ +uint32_t HAL_ICACHE_Monitor_GetHitValue(void) +{ + return (ICACHE->HMONR); +} + +/** + * @brief Get the Instruction Cache performance Miss monitoring value. + * @note Upon reaching the 32-bit maximum value, monitor does not wrap. + * @retval Miss monitoring value + */ +uint32_t HAL_ICACHE_Monitor_GetMissValue(void) +{ + return (ICACHE->MMONR); +} + +/** + * @} + */ + +/** @defgroup ICACHE_Exported_Functions_Group2 IRQ and callback functions + * @brief IRQ and callback functions + * + @verbatim + ============================================================================== + ##### IRQ and callback functions ##### + ============================================================================== + [..] + This section provides functions allowing to handle ICACHE global interrupt + and the associated callback functions. + @endverbatim + * @{ + */ + +/** + * @brief Handle the Instruction Cache interrupt request. + * @note This function should be called under the ICACHE_IRQHandler(). + * @note This function respectively disables the interrupt and clears the + * flag of any pending flag before calling the associated user callback. + * @retval None + */ +void HAL_ICACHE_IRQHandler(void) +{ + /* Get current interrupt flags and interrupt sources value */ + uint32_t itflags = READ_REG(ICACHE->SR); + uint32_t itsources = READ_REG(ICACHE->IER); + + /* Check Instruction cache Error interrupt flag */ + if (((itflags & itsources) & ICACHE_FLAG_ERROR) != 0U) + { + /* Disable error interrupt */ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); + + /* Clear ERR pending flag */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); + + /* Instruction cache error interrupt user callback */ + HAL_ICACHE_ErrorCallback(); + } + + /* Check Instruction cache BusyEnd interrupt flag */ + if (((itflags & itsources) & ICACHE_FLAG_BUSYEND) != 0U) + { + /* Disable end of cache invalidation interrupt */ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); + + /* Clear BSYENDF pending flag */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + /* Instruction cache busyend interrupt user callback */ + HAL_ICACHE_InvalidateCompleteCallback(); + } +} + +/** + * @brief Cache invalidation complete callback. + */ +__weak void HAL_ICACHE_InvalidateCompleteCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_ICACHE_InvalidateCompleteCallback() should be implemented in the user file + */ +} + +/** + * @brief Error callback. + */ +__weak void HAL_ICACHE_ErrorCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_ICACHE_ErrorCallback() should be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* ICACHE && HAL_ICACHE_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_irda.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_irda.c new file mode 100644 index 00000000000..1f434280430 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_irda.c @@ -0,0 +1,3015 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_irda.c + * @author MCD Application Team + * @brief IRDA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the IrDA (Infrared Data Association) Peripheral + * (IRDA) + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The IRDA HAL driver can be used as follows: + + (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda). + (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API + in setting the associated USART or UART in IRDA mode: + (++) Enable the USARTx/UARTx interface clock. + (++) USARTx/UARTx pins configuration: + (+++) Enable the clock for the USARTx/UARTx GPIOs. + (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input). + (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT() + and HAL_IRDA_Receive_IT() APIs): + (+++) Configure the USARTx/UARTx interrupt priority. + (+++) Enable the NVIC USARTx/UARTx IRQ handle. + (+++) The specific IRDA interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. + + (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA() + and HAL_IRDA_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter), + the normal or low power mode and the clock prescaler in the hirda handle Init structure. + + (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_IRDA_MspInit() API. + + -@@- The specific IRDA interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. + + (#) Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() + (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT() + (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT() + (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxCpltCallback() + (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_IRDA_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA() + (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback() + (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA() + (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback() + (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxCpltCallback() + (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_IRDA_ErrorCallback() + + *** IRDA HAL driver macros list *** + ==================================== + [..] + Below the list of most used macros in IRDA HAL driver. + + (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral + (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral + (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not + (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag + (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt + (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt + (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled + + [..] + (@) You can refer to the IRDA HAL driver header file for more useful macros + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_IRDA_RegisterCallback() to register a user callback. + Function HAL_IRDA_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : IRDA MspInit. + (+) MspDeInitCallback : IRDA MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : IRDA MspInit. + (+) MspDeInitCallback : IRDA MspDeInit. + + [..] + By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_IRDA_Init() + and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit() + or HAL_IRDA_Init() function. + + [..] + When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup IRDA IRDA + * @brief HAL IRDA module driver + * @{ + */ + +#ifdef HAL_IRDA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup IRDA_Private_Constants IRDA Private Constants + * @{ + */ +#define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */ + +#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ + | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ + +#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ + +#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup IRDA_Private_Macros IRDA Private Macros + * @{ + */ +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ IRDA clock source. + * @param __BAUD__ Baud rate set by the user. + * @param __PRESCALER__ IRDA clock prescaler value. + * @retval Division result + */ +#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\ + + ((__BAUD__)/2U)) / (__BAUD__)) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup IRDA_Private_Functions + * @{ + */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ +static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +#if defined(HAL_DMA_MODULE_ENABLED) +static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda); +#endif /* HAL_DMA_MODULE_ENABLED */ +static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda); +#if defined(HAL_DMA_MODULE_ENABLED) +static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMAError(DMA_HandleTypeDef *hdma); +static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); +static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); +static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup IRDA_Exported_Functions IRDA Exported Functions + * @{ + */ + +/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx + in asynchronous IRDA mode. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Power mode + (++) Prescaler setting + (++) Receiver/transmitter modes + + [..] + The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures + (details for the procedures are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible IRDA frame formats are listed in the + following table. + + Table 1. IRDA frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | IRDA frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the IRDA mode according to the specified + * parameters in the IRDA_InitTypeDef and initialize the associated handle. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) +{ + /* Check the IRDA handle allocation */ + if (hirda == NULL) + { + return HAL_ERROR; + } + + /* Check the USART/UART associated to the IRDA handle */ + assert_param(IS_IRDA_INSTANCE(hirda->Instance)); + + if (hirda->gState == HAL_IRDA_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hirda->Lock = HAL_UNLOCKED; + +#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 + IRDA_InitCallbacksToDefault(hirda); + + if (hirda->MspInitCallback == NULL) + { + hirda->MspInitCallback = HAL_IRDA_MspInit; + } + + /* Init the low level hardware */ + hirda->MspInitCallback(hirda); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_IRDA_MspInit(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + } + + hirda->gState = HAL_IRDA_STATE_BUSY; + + /* Disable the Peripheral to update the configuration registers */ + __HAL_IRDA_DISABLE(hirda); + + /* Set the IRDA Communication parameters */ + if (IRDA_SetConfig(hirda) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + + /* set the UART/USART in IRDA mode */ + hirda->Instance->CR3 |= USART_CR3_IREN; + + /* Enable the Peripheral */ + __HAL_IRDA_ENABLE(hirda); + + /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */ + return (IRDA_CheckIdleState(hirda)); +} + +/** + * @brief DeInitialize the IRDA peripheral. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) +{ + /* Check the IRDA handle allocation */ + if (hirda == NULL) + { + return HAL_ERROR; + } + + /* Check the USART/UART associated to the IRDA handle */ + assert_param(IS_IRDA_INSTANCE(hirda->Instance)); + + hirda->gState = HAL_IRDA_STATE_BUSY; + + /* DeInit the low level hardware */ +#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 + if (hirda->MspDeInitCallback == NULL) + { + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; + } + /* DeInit the low level hardware */ + hirda->MspDeInitCallback(hirda); +#else + HAL_IRDA_MspDeInit(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + /* Disable the Peripheral */ + __HAL_IRDA_DISABLE(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->gState = HAL_IRDA_STATE_RESET; + hirda->RxState = HAL_IRDA_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief Initialize the IRDA MSP. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the IRDA MSP. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User IRDA Callback + * To be used to override the weak predefined callback + * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID + * @param hirda irda handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, + pIRDA_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hirda->gState == HAL_IRDA_STATE_READY) + { + switch (CallbackID) + { + case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : + hirda->TxHalfCpltCallback = pCallback; + break; + + case HAL_IRDA_TX_COMPLETE_CB_ID : + hirda->TxCpltCallback = pCallback; + break; + + case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : + hirda->RxHalfCpltCallback = pCallback; + break; + + case HAL_IRDA_RX_COMPLETE_CB_ID : + hirda->RxCpltCallback = pCallback; + break; + + case HAL_IRDA_ERROR_CB_ID : + hirda->ErrorCallback = pCallback; + break; + + case HAL_IRDA_ABORT_COMPLETE_CB_ID : + hirda->AbortCpltCallback = pCallback; + break; + + case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : + hirda->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : + hirda->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = pCallback; + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hirda->gState == HAL_IRDA_STATE_RESET) + { + switch (CallbackID) + { + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = pCallback; + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an IRDA callback + * IRDA callback is redirected to the weak predefined callback + * @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID + * @param hirda irda handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_IRDA_STATE_READY == hirda->gState) + { + switch (CallbackID) + { + case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : + hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_IRDA_TX_COMPLETE_CB_ID : + hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : + hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_IRDA_RX_COMPLETE_CB_ID : + hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_IRDA_ERROR_CB_ID : + hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_IRDA_ABORT_COMPLETE_CB_ID : + hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : + hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + break; + + case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : + hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + break; + + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_IRDA_STATE_RESET == hirda->gState) + { + switch (CallbackID) + { + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = HAL_IRDA_MspInit; + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions + * @brief IRDA Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the IRDA data transfers. + + [..] + IrDA is a half duplex communication protocol. If the Transmitter is busy, any data + on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver + is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. + While receiving data, transmission should be avoided as the data to be transmitted + could be corrupted. + + [..] + (#) There are two modes of transfer: + (++) Blocking mode: the communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: the communication is performed using Interrupts + or DMA, these API's return the HAL status. + The end of the data processing will be indicated through the + dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks + will be executed respectively at the end of the Transmit or Receive process + The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected + + (#) Blocking mode APIs are : + (++) HAL_IRDA_Transmit() + (++) HAL_IRDA_Receive() + + (#) Non Blocking mode APIs with Interrupt are : + (++) HAL_IRDA_Transmit_IT() + (++) HAL_IRDA_Receive_IT() + (++) HAL_IRDA_IRQHandler() + + (#) Non Blocking mode functions with DMA are : + (++) HAL_IRDA_Transmit_DMA() + (++) HAL_IRDA_Receive_DMA() + (++) HAL_IRDA_DMAPause() + (++) HAL_IRDA_DMAResume() + (++) HAL_IRDA_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode: + (++) HAL_IRDA_TxHalfCpltCallback() + (++) HAL_IRDA_TxCpltCallback() + (++) HAL_IRDA_RxHalfCpltCallback() + (++) HAL_IRDA_RxCpltCallback() + (++) HAL_IRDA_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_IRDA_Abort() + (++) HAL_IRDA_AbortTransmit() + (++) HAL_IRDA_AbortReceive() + (++) HAL_IRDA_Abort_IT() + (++) HAL_IRDA_AbortTransmit_IT() + (++) HAL_IRDA_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (++) HAL_IRDA_AbortCpltCallback() + (++) HAL_IRDA_AbortTransmitCpltCallback() + (++) HAL_IRDA_AbortReceiveCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + Transfer is kept ongoing on IRDA side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and + HAL_IRDA_ErrorCallback() user callback is executed. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Specify timeout value. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (hirda->gState == HAL_IRDA_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->gState = HAL_IRDA_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + hirda->TxXferSize = Size; + hirda->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (const uint16_t *) pData; /* Derogation R.11.3 */ + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (hirda->TxXferCount > 0U) + { + hirda->TxXferCount--; + + if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + } + + if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Specify timeout value. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (hirda->RxState == HAL_IRDA_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->RxState = HAL_IRDA_STATE_BUSY_RX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + hirda->RxXferSize = Size; + hirda->RxXferCount = Size; + + /* Computation of the mask to apply to RDR register + of the UART associated to the IRDA */ + IRDA_MASK_COMPUTATION(hirda); + uhMask = hirda->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */ + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Check data remaining to be received */ + while (hirda->RxXferCount > 0U) + { + hirda->RxXferCount--; + + if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + } + + /* At end of Rx process, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (hirda->gState == HAL_IRDA_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pTxBuffPtr = pData; + hirda->TxXferSize = Size; + hirda->TxXferCount = Size; + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->gState = HAL_IRDA_STATE_BUSY_TX; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Enable the IRDA Transmit Data Register Empty Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (hirda->RxState == HAL_IRDA_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pRxBuffPtr = pData; + hirda->RxXferSize = Size; + hirda->RxXferCount = Size; + + /* Computation of the mask to apply to the RDR register + of the UART associated to the IRDA */ + IRDA_MASK_COMPUTATION(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->RxState = HAL_IRDA_STATE_BUSY_RX; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + /* Enable the IRDA Parity Error and Data Register not empty Interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + /* Enable the IRDA Data Register not empty Interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + + /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint16_t nbByte = Size; + + /* Check that a Tx process is not already ongoing */ + if (hirda->gState == HAL_IRDA_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pTxBuffPtr = pData; + hirda->TxXferSize = Size; + hirda->TxXferCount = Size; + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->gState = HAL_IRDA_STATE_BUSY_TX; + + /* Set the IRDA DMA transfer complete callback */ + hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt; + + /* Set the IRDA DMA half transfer complete callback */ + hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt; + + /* Set the DMA error callback */ + hirda->hdmatx->XferErrorCallback = IRDA_DMAError; + + /* Set the DMA abort callback */ + hirda->hdmatx->XferAbortCallback = NULL; + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((hirda->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hirda->hdmatx->LinkedListQueue != NULL) && (hirda->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + hirda->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + hirda->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)hirda->pTxBuffPtr; + + /* Set DMA destination address */ + hirda->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&hirda->Instance->TDR; + + /* Enable the IRDA transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(hirda->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the IRDA transmit DMA channel */ + status = HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, nbByte); + } + + if (status == HAL_OK) + { + /* Clear the TC flag in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF); + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Restore hirda->gState to ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. + * @note When the IRDA parity is enabled (PCE = 1), the received data contains + * the parity bit (MSB position). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint16_t nbByte = Size; + + /* Check that a Rx process is not already ongoing */ + if (hirda->RxState == HAL_IRDA_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pRxBuffPtr = pData; + hirda->RxXferSize = Size; + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->RxState = HAL_IRDA_STATE_BUSY_RX; + + /* Set the IRDA DMA transfer complete callback */ + hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt; + + /* Set the IRDA DMA half transfer complete callback */ + hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt; + + /* Set the DMA error callback */ + hirda->hdmarx->XferErrorCallback = IRDA_DMAError; + + /* Set the DMA abort callback */ + hirda->hdmarx->XferAbortCallback = NULL; + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((hirda->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hirda->hdmarx->LinkedListQueue != NULL) && (hirda->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + hirda->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + hirda->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&hirda->Instance->RDR; + + /* Set DMA destination address */ + hirda->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hirda->pRxBuffPtr; + + /* Enable the DMA channel */ + status = HAL_DMAEx_List_Start_IT(hirda->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the DMA channel */ + status = HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, nbByte); + } + + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + /* Enable the UART Parity Error Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Restore hirda->RxState to ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Pause the DMA Transfer. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) +{ + /* Process Locked */ + __HAL_LOCK(hirda); + + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) + { + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the IRDA DMA Tx request */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + } + } + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + { + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Disable the IRDA DMA Rx request */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) +{ + /* Process Locked */ + __HAL_LOCK(hirda); + + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) + { + /* Enable the IRDA DMA Tx request */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + } + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer*/ + __HAL_IRDA_CLEAR_OREFLAG(hirda); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + } + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Enable the IRDA DMA Rx request */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() / + HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + /* Stop IRDA DMA Tx request if ongoing */ + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) + { + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel */ + if (hirda->hdmatx != NULL) + { + if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + IRDA_EndTxTransfer(hirda); + } + } + + /* Stop IRDA DMA Rx request if ongoing */ + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + { + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel */ + if (hirda->hdmarx != NULL) + { + if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + IRDA_EndRxTransfer(hirda); + } + } + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) +{ + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \ + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the IRDA DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (hirda->hdmatx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx and Rx transfer counters */ + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->gState and hirda->RxState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Reset Handle ErrorCode to No Error */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the IRDA DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (hirda->hdmatx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx transfer counter */ + hirda->TxXferCount = 0U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Rx transfer counter */ + hirda->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) +{ + uint32_t abortcplt = 1U; + + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \ + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (hirda->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback; + } + else + { + hirda->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (hirda->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback; + } + else + { + hirda->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the IRDA DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (hirda->hdmatx != NULL) + { + /* IRDA Tx DMA Abort callback has already been initialised : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) + { + hirda->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (hirda->hdmarx != NULL) + { + /* IRDA Rx DMA Abort callback has already been initialised : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + { + hirda->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; + + /* Reset errorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->gState and hirda->RxState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hirda->AbortCpltCallback(hirda); +#else + /* Call legacy weak Abort complete callback */ + HAL_IRDA_AbortCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the IRDA DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (hirda->hdmatx != NULL) + { + /* Set the IRDA DMA Abort callback : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) + { + /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */ + hirda->hdmatx->XferAbortCallback(hirda->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + hirda->TxXferCount = 0U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hirda->AbortTransmitCpltCallback(hirda); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_IRDA_AbortTransmitCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Tx transfer counter */ + hirda->TxXferCount = 0U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hirda->AbortTransmitCpltCallback(hirda); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_IRDA_AbortTransmitCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + { + /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ + hirda->hdmarx->XferAbortCallback(hirda->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + hirda->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hirda->AbortReceiveCpltCallback(hirda); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_IRDA_AbortReceiveCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Rx transfer counter */ + hirda->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hirda->AbortReceiveCpltCallback(hirda); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_IRDA_AbortReceiveCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + + return HAL_OK; +} + +/** + * @brief Handle IRDA interrupt request. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) +{ + uint32_t isrflags = READ_REG(hirda->Instance->ISR); + uint32_t cr1its = READ_REG(hirda->Instance->CR1); + uint32_t cr3its; + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + if (errorflags == 0U) + { + /* IRDA in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)) + { + IRDA_Receive_IT(hirda); + return; + } + } + + /* If some errors occur */ + cr3its = READ_REG(hirda->Instance->CR3); + if ((errorflags != 0U) + && (((cr3its & USART_CR3_EIE) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))) + { + /* IRDA parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_PE; + } + + /* IRDA frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_FE; + } + + /* IRDA noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_NE; + } + + /* IRDA Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) && + (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U))) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; + } + + /* Call IRDA Error Call back function if need be --------------------------*/ + if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE) + { + /* IRDA in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)) + { + IRDA_Receive_IT(hirda); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + errorcode = hirda->ErrorCode; + if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & HAL_IRDA_ERROR_ORE) != 0U)) + { + /* Blocking error : transfer is aborted + Set the IRDA state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + IRDA_EndRxTransfer(hirda); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel */ + if (hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback : + will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + { + /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ + hirda->hdmarx->XferAbortCallback(hirda->hdmarx); + } + } + else + { +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ + HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ + HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ + HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* IRDA in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)) + { + IRDA_Transmit_IT(hirda); + return; + } + + /* IRDA in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + IRDA_EndTransmit_IT(hirda); + return; + } + +} + +/** + * @brief Tx Transfer completed callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer complete callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief IRDA error callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief IRDA Abort Complete callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief IRDA Abort Complete callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief IRDA Abort Receive Complete callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions + * @brief IRDA State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of IrDA + communication process and also return Peripheral Errors occurred during communication process + (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state + of the IRDA peripheral handle. + (+) HAL_IRDA_GetError() checks in run-time errors that could occur during + communication. + +@endverbatim + * @{ + */ + +/** + * @brief Return the IRDA handle state. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL state + */ +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda) +{ + /* Return IRDA handle state */ + uint32_t temp1; + uint32_t temp2; + temp1 = (uint32_t)hirda->gState; + temp2 = (uint32_t)hirda->RxState; + + return (HAL_IRDA_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the IRDA handle error code. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval IRDA Error Code + */ +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda) +{ + return hirda->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup IRDA_Private_Functions IRDA Private Functions + * @{ + */ + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +/** + * @brief Initialize the callbacks to their default values. + * @param hirda IRDA handle. + * @retval none + */ +void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda) +{ + /* Init the IRDA Callback settings */ + hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ + hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + +} +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + +/** + * @brief Configure the IRDA peripheral. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) +{ + uint32_t tmpreg; + IRDA_ClockSourceTypeDef clocksource; + HAL_StatusTypeDef ret = HAL_OK; + static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + uint32_t pclk; + + /* Check the communication parameters */ + assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); + assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength)); + assert_param(IS_IRDA_PARITY(hirda->Init.Parity)); + assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode)); + assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler)); + assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode)); + assert_param(IS_IRDA_CLOCKPRESCALER(hirda->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Configure the IRDA Word Length, Parity and transfer Mode: + Set the M bits according to hirda->Init.WordLength value + Set PCE and PS bits according to hirda->Init.Parity value + Set TE and RE bits according to hirda->Init.Mode value */ + tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ; + + MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode); + + /*--------------------- USART clock PRESC Configuration ----------------*/ + /* Configure + * - IRDA Clock Prescaler: set PRESCALER according to hirda->Init.ClockPrescaler value */ + MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler); + + /*-------------------------- USART GTPR Configuration ----------------------*/ + MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + IRDA_GETCLOCKSOURCE(hirda, clocksource); + tmpreg = 0U; + switch (clocksource) + { + case IRDA_CLOCKSOURCE_PLL2Q: + pclk = HAL_RCC_GetPLL2QFreq(); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + break; + case IRDA_CLOCKSOURCE_PLL3Q: + pclk = HAL_RCC_GetPLL3QFreq(); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + break; + case IRDA_CLOCKSOURCE_CSI: + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(CSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + break; + case IRDA_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + break; + case IRDA_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + break; + case IRDA_CLOCKSOURCE_HSI: + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + break; + case IRDA_CLOCKSOURCE_LSE: + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + break; + default: + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) + { + hirda->Instance->BRR = (uint16_t)tmpreg; + } + else + { + ret = HAL_ERROR; + } + + return ret; +} + +/** + * @brief Check the IRDA Idle State. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) +{ + uint32_t tickstart; + + /* Initialize the IRDA ErrorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + /* Check if the Receiver is enabled */ + if ((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the IRDA state*/ + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief Handle IRDA Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param Flag Specifies the IRDA flag to check. + * @param Status The actual Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; +} + + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA IRDA transmit process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + hirda->TxXferCount = 0U; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the IRDA CR3 register */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Enable the IRDA Transmit Complete Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Tx complete callback */ + hirda->TxCpltCallback(hirda); +#else + /* Call legacy weak Tx complete callback */ + HAL_IRDA_TxCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + +} + +/** + * @brief DMA IRDA transmit process half complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Tx Half complete callback */ + hirda->TxHalfCpltCallback(hirda); +#else + /* Call legacy weak Tx complete callback */ + HAL_IRDA_TxHalfCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + +/** + * @brief DMA IRDA receive process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + hirda->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the IRDA CR3 register */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + } + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hirda->RxCpltCallback(hirda); +#else + /* Call legacy weak Rx complete callback */ + HAL_IRDA_RxCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA IRDA receive process half complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + hirda->RxHalfCpltCallback(hirda); +#else + /* Call legacy weak Rx Half complete callback */ + HAL_IRDA_RxHalfCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + +/** + * @brief DMA IRDA communication error callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMAError(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + + /* Stop IRDA DMA Tx request if ongoing */ + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) + { + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + hirda->TxXferCount = 0U; + IRDA_EndTxTransfer(hirda); + } + } + + /* Stop IRDA DMA Rx request if ongoing */ + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + { + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + hirda->RxXferCount = 0U; + IRDA_EndRxTransfer(hirda); + } + } + + hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ + HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + +/** + * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + hirda->RxXferCount = 0U; + hirda->TxXferCount = 0U; + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ + HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + +/** + * @brief DMA IRDA Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + + hirda->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hirda->hdmarx != NULL) + { + if (hirda->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; + + /* Reset errorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->gState and hirda->RxState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hirda->AbortCpltCallback(hirda); +#else + /* Call legacy weak Abort complete callback */ + HAL_IRDA_AbortCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + + +/** + * @brief DMA IRDA Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + + hirda->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hirda->hdmatx != NULL) + { + if (hirda->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; + + /* Reset errorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->gState and hirda->RxState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hirda->AbortCpltCallback(hirda); +#else + /* Call legacy weak Abort complete callback */ + HAL_IRDA_AbortCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + + +/** + * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to + * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + + hirda->TxXferCount = 0U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hirda->AbortTransmitCpltCallback(hirda); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_IRDA_AbortTransmitCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + +/** + * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to + * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hirda->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hirda->AbortReceiveCpltCallback(hirda); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_IRDA_AbortReceiveCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Send an amount of data in interrupt mode. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_IRDA_Transmit_IT(). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) +{ + const uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) + { + if (hirda->TxXferCount == 0U) + { + /* Disable the IRDA Transmit Data Register Empty Interrupt */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the IRDA Transmit Complete Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); + } + else + { + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + tmp = (const uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */ + hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); + hirda->pTxBuffPtr += 2U; + } + else + { + hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU); + hirda->pTxBuffPtr++; + } + hirda->TxXferCount--; + } + } +} + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) +{ + /* Disable the IRDA Transmit Complete Interrupt */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE); + + /* Tx process is ended, restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Tx complete callback */ + hirda->TxCpltCallback(hirda); +#else + /* Call legacy weak Tx complete callback */ + HAL_IRDA_TxCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_IRDA_Receive_IT() + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) +{ + uint16_t *tmp; + uint16_t uhMask = hirda->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(hirda->Instance->RDR); + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */ + *tmp = (uint16_t)(uhdata & uhMask); + hirda->pRxBuffPtr += 2U; + } + else + { + *hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + hirda->pRxBuffPtr++; + } + + hirda->RxXferCount--; + if (hirda->RxXferCount == 0U) + { + /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hirda->RxCpltCallback(hirda); +#else + /* Call legacy weak Rx complete callback */ + HAL_IRDA_RxCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_IRDA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_iwdg.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_iwdg.c new file mode 100644 index 00000000000..8b677fee573 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_iwdg.c @@ -0,0 +1,510 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_iwdg.c + * @author MCD Application Team + * @brief IWDG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Independent Watchdog (IWDG) peripheral: + * + Initialization and Start functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### IWDG Generic features ##### + ============================================================================== + [..] + (+) The IWDG can be started by either software or hardware (configurable + through option byte). + + (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays + active even if the main clock fails. + + (+) Once the IWDG is started, the LSI is forced ON and both cannot be + disabled. The counter starts counting down from the reset value (0xFFF). + When it reaches the end of count value (0x000) a reset signal is + generated (IWDG reset). + + (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, + the IWDG_RLR value is reloaded into the counter and the watchdog reset + is prevented. + + (+) The IWDG is implemented in the VDD voltage domain that is still functional + in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY). + IWDGRST flag in RCC_CSR register can be used to inform when an IWDG + reset occurs. + + (+) Debug mode: When the microcontroller enters debug mode (core halted), + the IWDG counter either continues to work normally or stops, depending + on DBG_IWDG_STOP configuration bit in DBG module, accessible through + __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros. + + [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s + The IWDG timeout may vary due to LSI clock frequency dispersion. + STM32H7RSxx devices provide the capability to measure the LSI clock + frequency (LSI clock is internally connected to TIM16 CH1 input capture). + The measured value can be used to have an IWDG timeout with an + acceptable accuracy. + + [..] Default timeout value (necessary for IWDG_SR status register update): + Constant LSI_VALUE is defined based on the nominal LSI clock frequency. + This frequency being subject to variations as mentioned above, the + default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT + below) may become too short or too long. + In such cases, this default timeout value can be tuned by redefining + the constant LSI_VALUE at user-application level (based, for instance, + on the measured LSI clock frequency as explained above). + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Register callback to treat Iwdg interrupt and MspInit using HAL_IWDG_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + HAL_IWDG_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Use IWDG using HAL_IWDG_Init() function to : + (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI + clock is forced ON and IWDG counter starts counting down. + (++) Enable write access to configuration registers: + IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR. + (++) Configure the IWDG prescaler and counter reload value. This reload + value will be loaded in the IWDG counter each time the watchdog is + reloaded, then the IWDG will start counting down from this value. + (++) Depending on window parameter: + (+++) If Window Init parameter is same as Window register value, + nothing more is done but reload counter value in order to exit + function with exact time base. + (+++) Else modify Window register. This will automatically reload + watchdog counter. + (++) Depending on Early Wakeup Interrupt parameter: + (+++) If EWI is set to disable, comparator is set to 0, interrupt is + disable & flag is clear. + (+++) Else modify EWCR register, setting comparator value, enable + interrupt & clear flag. + (++) Wait for status flags to be reset. + + (#) Then the application program must refresh the IWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + HAL_IWDG_Refresh() function. + + *** IWDG HAL driver macros list *** + ==================================== + [..] + Below the list of most used macros in IWDG HAL driver: + (+) __HAL_IWDG_START: Enable the IWDG peripheral + (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in + the reload register + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#ifdef HAL_IWDG_MODULE_ENABLED +/** @addtogroup IWDG + * @brief IWDG HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup IWDG_Private_Defines IWDG Private Defines + * @{ + */ +/* Status register needs up to 5 LSI clock periods to be updated. However a + synchronisation is added on prescaled LSI clock rising edge, so we only + consider a highest prescaler cycle. + The timeout value is calculated using the highest prescaler (1024) and + the LSI_VALUE constant. The value of this constant can be changed by the user + to take into account possible LSI clock period variations. + The timeout value is multiplied by 1000 to be converted in milliseconds. + LSI startup time is also considered here by adding LSI_STARTUP_TIME + converted in milliseconds. */ +#define HAL_IWDG_DEFAULT_TIMEOUT (((1UL * 1024UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) +#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_EWU | IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup IWDG_Exported_Functions + * @{ + */ + +/** @addtogroup IWDG_Exported_Functions_Group1 + * @brief Initialization and Start functions. + * +@verbatim + =============================================================================== + ##### Initialization and Start functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the IWDG according to the specified parameters in the + IWDG_InitTypeDef of associated handle. + (+) Manage Window option. + (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog + is reloaded in order to exit function with correct time base. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the IWDG according to the specified parameters in the + * IWDG_InitTypeDef and start watchdog. Before exiting function, + * watchdog is refreshed in order to have correct time base. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) +{ + uint32_t tickstart; + + /* Check the IWDG handle allocation */ + if (hiwdg == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); + assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); + assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); + assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); + assert_param(IS_IWDG_EWI(hiwdg->Init.EWI)); + +#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1) + /* Reset Callback pointers */ + if (hiwdg->EwiCallback == NULL) + { + hiwdg->EwiCallback = HAL_IWDG_EarlyWakeupCallback; + } + if (hiwdg->MspInitCallback == NULL) + { + hiwdg->MspInitCallback = HAL_IWDG_MspInit; + } + + /* Init the low level hardware */ + hiwdg->MspInitCallback(hiwdg); +#else + /* Init the low level hardware */ + HAL_IWDG_MspInit(hiwdg); +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ + + /* Enable IWDG. LSI is turned on automatically */ + __HAL_IWDG_START(hiwdg); + + /* Enable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers by writing + 0x5555 in KR */ + IWDG_ENABLE_WRITE_ACCESS(hiwdg); + + /* Write to IWDG registers the Prescaler & Reload values to work with */ + hiwdg->Instance->PR = hiwdg->Init.Prescaler; + hiwdg->Instance->RLR = hiwdg->Init.Reload; + + /* Check Reload update flag, before performing any reload of the counter, else previous value + will be taken. */ + tickstart = HAL_GetTick(); + + /* Wait for register to be updated */ + while ((hiwdg->Instance->SR & IWDG_SR_RVU) != 0x00u) + { + if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) + { + if ((hiwdg->Instance->SR & IWDG_SR_RVU) != 0x00u) + { + return HAL_TIMEOUT; + } + } + } + + if (hiwdg->Init.EWI == IWDG_EWI_DISABLE) + { + /* EWI comparator value equal 0, disable the early wakeup interrupt + * acknowledge the early wakeup interrupt in any cases. it clears the EWIF flag in SR register + * Set Watchdog Early Wakeup Comparator to 0x00 */ + hiwdg->Instance->EWCR = IWDG_EWCR_EWIC; + } + else + { + /* EWI comparator value different from 0, enable the early wakeup interrupt, + * acknowledge the early wakeup interrupt in any cases. it clears the EWIF flag in SR register + * Set Watchdog Early Wakeup Comparator value */ + hiwdg->Instance->EWCR = IWDG_EWCR_EWIE | IWDG_EWCR_EWIC | hiwdg->Init.EWI; + } + + /* Check pending flag, if previous update not done, return timeout */ + tickstart = HAL_GetTick(); + + /* Wait for register to be updated */ + while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) + { + if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) + { + if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) + { + return HAL_TIMEOUT; + } + } + } + + /* If window parameter is different than current value, modify window + register */ + if (hiwdg->Instance->WINR != hiwdg->Init.Window) + { + /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, + even if window feature is disabled, Watchdog will be reloaded by writing + windows register */ + hiwdg->Instance->WINR = hiwdg->Init.Window; + } + else + { + /* Reload IWDG counter with value defined in the reload register */ + __HAL_IWDG_RELOAD_COUNTER(hiwdg); + } + + /* Return function status */ + return HAL_OK; +} + + +/** + * @brief Initialize the IWDG MSP. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @note When rewriting this function in user file, mechanism may be added + * to avoid multiple initialize when HAL_IWDG_Init function is called + * again to change parameters. + * @retval None + */ +__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hiwdg); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IWDG_MspInit could be implemented in the user file + */ +} + + +#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User IWDG Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hiwdg IWDG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_IWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID + * @arg @ref HAL_IWDG_MSPINIT_CB_ID MspInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_IWDG_RegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID, + pIWDG_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + status = HAL_ERROR; + } + else + { + switch (CallbackID) + { + case HAL_IWDG_EWI_CB_ID: + hiwdg->EwiCallback = pCallback; + break; + case HAL_IWDG_MSPINIT_CB_ID: + hiwdg->MspInitCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + + return status; +} + + +/** + * @brief Unregister a IWDG Callback + * IWDG Callback is redirected to the weak (surcharged) predefined callback + * @param hiwdg IWDG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_IWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID + * @arg @ref HAL_IWDG_MSPINIT_CB_ID MspInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_IWDG_UnRegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_IWDG_EWI_CB_ID: + hiwdg->EwiCallback = HAL_IWDG_EarlyWakeupCallback; + break; + case HAL_IWDG_MSPINIT_CB_ID: + hiwdg->MspInitCallback = HAL_IWDG_MspInit; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ + + +/** + * @} + */ + + +/** @addtogroup IWDG_Exported_Functions_Group2 + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Refresh the IWDG. + +@endverbatim + * @{ + */ + +/** + * @brief Refresh the IWDG. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) +{ + /* Reload IWDG counter with value defined in the reload register */ + __HAL_IWDG_RELOAD_COUNTER(hiwdg); + + /* Return function status */ + return HAL_OK; +} + + +/** + * @brief Get back IWDG running status + * @note This API allows to know if IWDG has been started by other master, thread + * or by hardware. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval can be one of following value : + * @arg @ref IWDG_STATUS_DISABLE + * @arg @ref IWDG_STATUS_ENABLE + */ +uint32_t HAL_IWDG_GetActiveStatus(const IWDG_HandleTypeDef *hiwdg) +{ + uint32_t status; + + /* Get back ONF flag */ + status = (hiwdg->Instance->SR & IWDG_SR_ONF); + + /* Return status */ + return status; +} + + +/** + * @brief Handle IWDG interrupt request. + * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations + * or data logging must be performed before the actual reset is generated. + * The EWI interrupt is enabled by calling HAL_IWDG_Init function with + * EWIMode set to IWDG_EWI_ENABLE. + * When the downcounter reaches the value 0x40, and EWI interrupt is + * generated and the corresponding Interrupt Service Routine (ISR) can + * be used to trigger specific actions (such as communications or data + * logging), before resetting the device. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval None + */ +void HAL_IWDG_IRQHandler(IWDG_HandleTypeDef *hiwdg) +{ + /* Check if IWDG Early Wakeup Interrupt occurred */ + if ((hiwdg->Instance->SR & IWDG_SR_EWIF) != 0x00u) + { + /* Clear the IWDG Early Wakeup flag */ + hiwdg->Instance->EWCR |= IWDG_EWCR_EWIC; + +#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1) + /* Early Wakeup registered callback */ + hiwdg->EwiCallback(hiwdg); +#else + /* Early Wakeup callback */ + HAL_IWDG_EarlyWakeupCallback(hiwdg); +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ + } +} + + +/** + * @brief IWDG Early Wakeup callback. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval None + */ +__weak void HAL_IWDG_EarlyWakeupCallback(IWDG_HandleTypeDef *hiwdg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hiwdg); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IWDG_EarlyWakeupCallback could be implemented in the user file + */ +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_IWDG_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_jpeg.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_jpeg.c new file mode 100644 index 00000000000..3c18ec82d2d --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_jpeg.c @@ -0,0 +1,4280 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_jpeg.c + * @author MCD Application Team + * @brief JPEG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the JPEG encoder/decoder peripheral: + * + Initialization and de-initialization functions + * + JPEG processing functions encoding and decoding + * + JPEG decoding Getting Info and encoding configuration setting + * + JPEG enable/disable header parsing functions (for decoding) + * + JPEG Input/Output Buffer configuration. + * + JPEG callback functions + * + JPEG Abort/Pause/Resume functions + * + JPEG custom quantization tables setting functions + * + IRQ handler management + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the JPEG peripheral using HAL_JPEG_Init : No initialization parameters are required. + Only the call to HAL_JPEG_Init is necessary to initialize the JPEG peripheral. + + (#) If operation is JPEG encoding use function HAL_JPEG_ConfigEncoding to set + the encoding parameters (mandatory before calling the encoding function). + the application can change the encoding parameter ImageQuality from + 1 to 100 to obtain a more or less quality (visual quality vs the original row image), + and inversely more or less jpg file size. + + (#) Note that for decoding operation the JPEG peripheral output data are organized in + YCbCr blocks called MCU (Minimum Coded Unit) as defioned in the JPEG specification + ISO/IEC 10918-1 standard. + It is up to the application to transform these YCbCr blocks to RGB data that can be display. + + Respectively, for Encoding operation the JPEG peripheral input should be organized + in YCbCr MCU blocks. It is up to the application to perform the necessary RGB to YCbCr + MCU blocks transformation before feeding the JPEG peripheral with data. + + (#) Use functions HAL_JPEG_Encode and HAL_JPEG_Decode to start respectively + a JPEG encoding/decoding operation in polling method (blocking). + + (#) Use functions HAL_JPEG_Encode_IT and HAL_JPEG_Decode_IT to start respectively + a JPEG encoding/decoding operation with Interrupt method (not blocking). + + (#) Use functions HAL_JPEG_Encode_DMA and HAL_JPEG_Decode_DMA to start respectively + a JPEG encoding/decoding operation with DMA method (not blocking). + + (#) Callback HAL_JPEG_InfoReadyCallback is asserted if the current operation + is a JPEG decoding to provide the application with JPEG image parameters. + This callback is asserted when the JPEG peripheral successfully parse the + JPEG header. + + (#) Callback HAL_JPEG_GetDataCallback is asserted for both encoding and decoding + operations to inform the application that the input buffer has been + consumed by the peripheral and to ask for a new data chunk if the operation + (encoding/decoding) has not been complete yet. + + (++) This CallBack should be implemented in the application side. It should + call the function HAL_JPEG_ConfigInputBuffer if new input data are available, + or call HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_INPUT + to inform the JPEG HAL driver that the ongoing operation shall pause waiting for the + application to provide a new input data chunk. + Once the application succeed getting new data and if the input has been paused, + the application can call the function HAL_JPEG_ConfigInputBuffer to set the new + input buffer and size, then resume the JPEG HAL input by calling new function HAL_JPEG_Resume. + If the application has ended feeding the HAL JPEG with input data (no more input data), the application + Should call the function HAL_JPEG_ConfigInputBuffer (within the callback HAL_JPEG_GetDataCallback) + with the parameter InDataLength set to zero. + + (++) The mechanism of HAL_JPEG_ConfigInputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows + to the application to provide the input data (for encoding or decoding) by chunks. + If the new input data chunk is not available (because data should be read from an input file + for example) the application can pause the JPEG input (using function HAL_JPEG_Pause) + Once the new input data chunk is available ( read from a file for example), the application + can call the function HAL_JPEG_ConfigInputBuffer to provide the HAL with the new chunk + then resume the JPEG HAL input by calling function HAL_JPEG_Resume. + + (++) The application can call functions HAL_JPEG_ConfigInputBuffer then HAL_JPEG_Resume. + any time (outside the HAL_JPEG_GetDataCallback) Once the new input chunk data available. + However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called + (if necessary) within the callback HAL_JPEG_GetDataCallback, i.e when the HAL JPEG has ended + Transferring the previous chunk buffer to the JPEG peripheral. + + (#) Callback HAL_JPEG_DataReadyCallback is asserted when the HAL JPEG driver + has filled the given output buffer with the given size. + + (++) This CallBack should be implemented in the application side. It should + call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver + with the new output buffer location and size to be used to store next data chunk. + if the application is not ready to provide the output chunk location then it can + call the function HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_OUTPUT + to inform the JPEG HAL driver that it shall pause output data. Once the application + is ready to receive the new data chunk (output buffer location free or available) it should call + the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver + with the new output chunk buffer location and size, then call HAL_JPEG_Resume + to inform the HAL that it shall resume outputting data in the given output buffer. + + (++) The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows + the application to receive data from the JPEG peripheral by chunks. when a chunk + is received, the application can pause the HAL JPEG output data to be able to process + these received data (YCbCr to RGB conversion in case of decoding or data storage in case + of encoding). + + (++) The application can call functions HAL_JPEG_ ConfigOutputBuffer then HAL_JPEG_Resume. + any time (outside the HAL_JPEG_DataReadyCallback) Once the output data buffer is free to use. + However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called + (if necessary) within the callback HAL_JPEG_ DataReadyCallback, i.e when the HAL JPEG has ended + Transferring the previous chunk buffer from the JPEG peripheral to the application. + + (#) Callback HAL_JPEG_EncodeCpltCallback is asserted when the HAL JPEG driver has + ended the current JPEG encoding operation, and all output data has been transmitted + to the application. + + (#) Callback HAL_JPEG_DecodeCpltCallback is asserted when the HAL JPEG driver has + ended the current JPEG decoding operation. and all output data has been transmitted + to the application. + + (#) Callback HAL_JPEG_ErrorCallback is asserted when an error occurred during + the current operation. the application can call the function HAL_JPEG_GetError() + to retrieve the error codes. + + (#) By default the HAL JPEG driver uses the default quantization tables + as provide in the JPEG specification (ISO/IEC 10918-1 standard) for encoding. + User can change these default tables if necessary using the function HAL_JPEG_SetUserQuantTables + Note that for decoding the quantization tables are automatically extracted from + the JPEG header. + + (#) To control JPEG state you can use the following function: HAL_JPEG_GetState() + + *** JPEG HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in JPEG HAL driver. + + (+) __HAL_JPEG_RESET_HANDLE_STATE : Reset JPEG handle state. + (+) __HAL_JPEG_ENABLE : Enable the JPEG peripheral. + (+) __HAL_JPEG_DISABLE : Disable the JPEG peripheral. + (+) __HAL_JPEG_GET_FLAG : Check the specified JPEG status flag. + (+) __HAL_JPEG_CLEAR_FLAG : Clear the specified JPEG status flag. + (+) __HAL_JPEG_ENABLE_IT : Enable the specified JPEG Interrupt. + (+) __HAL_JPEG_DISABLE_IT : Disable the specified JPEG Interrupt. + (+) __HAL_JPEG_GET_IT_SOURCE : returns the state of the specified JPEG Interrupt (Enabled or disabled). + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_JPEG_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_JPEG_RegisterCallback() or HAL_JPEG_RegisterXXXCallback() + to register an interrupt callback. + + Function HAL_JPEG_RegisterCallback() allows to register following callbacks: + (+) EncodeCpltCallback : callback for end of encoding operation. + (+) DecodeCpltCallback : callback for end of decoding operation. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : JPEG MspInit. + (+) MspDeInitCallback : JPEG MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + For specific callbacks InfoReadyCallback, GetDataCallback and DataReadyCallback use dedicated + register callbacks : respectively HAL_JPEG_RegisterInfoReadyCallback(), + HAL_JPEG_RegisterGetDataCallback() and HAL_JPEG_RegisterDataReadyCallback(). + + Use function HAL_JPEG_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_JPEG_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) EncodeCpltCallback : callback for end of encoding operation. + (+) DecodeCpltCallback : callback for end of decoding operation. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : JPEG MspInit. + (+) MspDeInitCallback : JPEG MspDeInit. + + For callbacks InfoReadyCallback, GetDataCallback and DataReadyCallback use dedicated + unregister callbacks : respectively HAL_JPEG_UnRegisterInfoReadyCallback(), + HAL_JPEG_UnRegisterGetDataCallback() and HAL_JPEG_UnRegisterDataReadyCallback(). + + By default, after the HAL_JPEG_Init() and when the state is HAL_JPEG_STATE_RESET + all callbacks are set to the corresponding weak functions : + examples HAL_JPEG_DecodeCpltCallback() , HAL_JPEG_GetDataCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_JPEG_Init()/ HAL_JPEG_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_JPEG_Init() / HAL_JPEG_DeInit() + keep and use the user MspInit/MspDeInit functions (registered beforehand) + + Callbacks can be registered/unregistered in HAL_JPEG_STATE_READY state only. + Exception done MspInit/MspDeInit callbacks that can be registered/unregistered + in HAL_JPEG_STATE_READY or HAL_JPEG_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_JPEG_RegisterCallback() before calling HAL_JPEG_DeInit() + or HAL_JPEG_Init() function. + + When The compilation define USE_HAL_JPEG_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#ifdef HAL_JPEG_MODULE_ENABLED + +#if defined (JPEG) + +/** @defgroup JPEG JPEG + * @brief JPEG HAL module driver. + * @{ + */ + +/* Private define ------------------------------------------------------------*/ +/** @addtogroup JPEG_Private_Constants + * @{ + */ +#define JPEG_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */ +#define JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162) /* Huffman AC table size : 162 codes*/ +#define JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12) /* Huffman DC table size : 12 codes*/ + +#define JPEG_QUANTVAL_MAX ((uint32_t)255) /* Quantization values are 8-bit numbers*/ +#define JPEG_LOW_QUALITY_REFERENCE ((uint32_t)5000) /*Reference value to generate scaling factor + for low quality factors (<50) */ +#define JPEG_HIGH_QUALITY_REFERENCE ((uint32_t)200) /*Reference value to generate scaling factor + for high quality factors (>=50)*/ + +#define JPEG_FIFO_SIZE ((uint32_t)16U) /* JPEG Input/Output HW FIFO size in words*/ + +#define JPEG_FIFO_TH_SIZE ((uint32_t)4U) /* JPEG Input/Output HW FIFO Threshold in words*/ + +#define JPEG_DMA_MASK ((uint32_t)0x00001800) /* JPEG DMA request Mask*/ +#define JPEG_DMA_IDMA ((uint32_t)JPEG_CR_IDMAEN) /* DMA request for the input FIFO */ +#define JPEG_DMA_ODMA ((uint32_t)JPEG_CR_ODMAEN) /* DMA request for the output FIFO */ + +#define JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/ + +#define JPEG_CONTEXT_ENCODE ((uint32_t)0x00000001) /* JPEG context : operation is encoding*/ +#define JPEG_CONTEXT_DECODE ((uint32_t)0x00000002) /* JPEG context : operation is decoding*/ +#define JPEG_CONTEXT_OPERATION_MASK ((uint32_t)0x00000003) /* JPEG context : operation Mask */ + +#define JPEG_CONTEXT_POLLING ((uint32_t)0x00000004) /* JPEG context : Transfer use Polling */ +#define JPEG_CONTEXT_IT ((uint32_t)0x00000008) /* JPEG context : Transfer use Interrupt */ +#define JPEG_CONTEXT_DMA ((uint32_t)0x0000000C) /* JPEG context : Transfer use DMA */ +#define JPEG_CONTEXT_METHOD_MASK ((uint32_t)0x0000000C) /* JPEG context : Transfer Mask */ + + +#define JPEG_CONTEXT_CONF_ENCODING ((uint32_t)0x00000100) /* JPEG context : encoding config done */ + +#define JPEG_CONTEXT_PAUSE_INPUT ((uint32_t)0x00001000) /* JPEG context : Pause Input */ +#define JPEG_CONTEXT_PAUSE_OUTPUT ((uint32_t)0x00002000) /* JPEG context : Pause Output */ + +#define JPEG_CONTEXT_CUSTOM_TABLES ((uint32_t)0x00004000) /* JPEG context : Use custom quantization tables */ + +#define JPEG_CONTEXT_ENDING_DMA ((uint32_t)0x00008000) /* JPEG context : ending with DMA in progress */ + +#define JPEG_PROCESS_ONGOING ((uint32_t)0x00000000) /* Process is on going */ +#define JPEG_PROCESS_DONE ((uint32_t)0x00000001) /* Process is done (ends) */ +#define JPEG_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__)\ + + HAL_DMAEx_GetFifoLevel(__HANDLE__)) +/** + * @} + */ + +/* Private typedef -----------------------------------------------------------*/ +/** @addtogroup JPEG_Private_Types + * @{ + */ + +/* + JPEG Huffman Table Structure definition : + This implementation of Huffman table structure is compliant with ISO/IEC 10918-1 standard, + Annex C Huffman Table specification + */ +typedef struct +{ + /* These two fields directly represent the contents of a JPEG DHT marker */ + uint8_t Bits[16]; /*!< bits[k] = # of symbols with codes of length k bits, + this parameter corresponds to BITS list in the Annex C */ + + uint8_t HuffVal[162]; /*!< The symbols, in order of incremented code length, + this parameter corresponds to HUFFVAL list in the Annex C */ + + +} JPEG_ACHuffTableTypeDef; + +typedef struct +{ + /* These two fields directly represent the contents of a JPEG DHT marker */ + uint8_t Bits[16]; /*!< bits[k] = # of symbols with codes of length k bits, + this parameter corresponds to BITS list in the Annex C */ + + uint8_t HuffVal[12]; /*!< The symbols, in order of incremented code length, + this parameter corresponds to HUFFVAL list in the Annex C */ + + +} JPEG_DCHuffTableTypeDef; + +typedef struct +{ + uint8_t CodeLength[JPEG_AC_HUFF_TABLE_SIZE]; /*!< Code length */ + + uint32_t HuffmanCode[JPEG_AC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */ + +} JPEG_AC_HuffCodeTableTypeDef; + +typedef struct +{ + uint8_t CodeLength[JPEG_DC_HUFF_TABLE_SIZE]; /*!< Code length */ + + uint32_t HuffmanCode[JPEG_DC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */ + +} JPEG_DC_HuffCodeTableTypeDef; +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @addtogroup JPEG_Private_Macros + * @{ + */ +#define JPEG_ENABLE_DMA(__HANDLE__,__DMA__) ((__HANDLE__)->Instance->CR |= ((__DMA__) & JPEG_DMA_MASK)) +/*note : To disable a DMA request we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits + located in the same DMA request enable register (CR register). */ +#define JPEG_DISABLE_DMA(__HANDLE__,__DMA__) MODIFY_REG((__HANDLE__)->Instance->CR, ((__DMA__) & JPEG_DMA_MASK), 0UL) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup JPEG_Private_Variables + * @{ + */ + +static const JPEG_DCHuffTableTypeDef JPEG_DCLUM_HuffTable = +{ + { 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 }, /*Bits*/ + + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb } /*HUFFVAL */ + +}; + +static const JPEG_DCHuffTableTypeDef JPEG_DCCHROM_HuffTable = +{ + { 0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 }, /*Bits*/ + + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb } /*HUFFVAL */ +}; + +static const JPEG_ACHuffTableTypeDef JPEG_ACLUM_HuffTable = +{ + { 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d }, /*Bits*/ + + { + 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, /*HUFFVAL */ + 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, + 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08, + 0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0, + 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16, + 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28, + 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, + 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, + 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, + 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, + 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, + 0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, + 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, + 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, + 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5, + 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4, + 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2, + 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, + 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, + 0xf9, 0xfa + } +}; + +static const JPEG_ACHuffTableTypeDef JPEG_ACCHROM_HuffTable = +{ + { 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 }, /*Bits*/ + + { + 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, /*HUFFVAL */ + 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, + 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, + 0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0, + 0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34, + 0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26, + 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38, + 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, + 0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, + 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, + 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, + 0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, + 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, + 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, + 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, + 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, + 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, + 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, + 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, + 0xf9, 0xfa + } +}; + +static const uint8_t JPEG_ZIGZAG_ORDER[JPEG_QUANT_TABLE_SIZE] = +{ + 0, 1, 8, 16, 9, 2, 3, 10, + 17, 24, 32, 25, 18, 11, 4, 5, + 12, 19, 26, 33, 40, 48, 41, 34, + 27, 20, 13, 6, 7, 14, 21, 28, + 35, 42, 49, 56, 57, 50, 43, 36, + 29, 22, 15, 23, 30, 37, 44, 51, + 58, 59, 52, 45, 38, 31, 39, 46, + 53, 60, 61, 54, 47, 55, 62, 63 +}; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup JPEG_Private_Functions_Prototypes + * @{ + */ + +static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(const uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, + uint32_t *LastK); +static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, + JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable); +static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, + JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable); +static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(const JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, + const __IO uint32_t *DCTableAddress); +static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(const JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, + const __IO uint32_t *ACTableAddress); +static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg); +static void JPEG_Set_Huff_DHTMem(const JPEG_HandleTypeDef *hjpeg); +static uint32_t JPEG_Set_Quantization_Mem(const JPEG_HandleTypeDef *hjpeg, const uint8_t *QTable, + __IO uint32_t *QTableAddress); +static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg); +static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg); +static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg); + +static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg); +static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg); +static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords); +static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords); +static uint32_t JPEG_GetQuality(const JPEG_HandleTypeDef *hjpeg); + +static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg); +static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg); +static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg); +static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg); +static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma); +static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma); +static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma); +static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) ; + +/** + * @} + */ + +/** @defgroup JPEG_Exported_Functions JPEG Exported Functions + * @{ + */ + +/** @defgroup JPEG_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions. + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the JPEG peripheral and creates the associated handle + (+) DeInitialize the JPEG peripheral + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the JPEG according to the specified + * parameters in the JPEG_InitTypeDef and creates the associated handle. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg) +{ + /* These are the sample quantization tables given in JPEG spec ISO/IEC 10918-1 standard , section K.1. */ + static const uint8_t JPEG_LUM_QuantTable[JPEG_QUANT_TABLE_SIZE] = + { + 16, 11, 10, 16, 24, 40, 51, 61, + 12, 12, 14, 19, 26, 58, 60, 55, + 14, 13, 16, 24, 40, 57, 69, 56, + 14, 17, 22, 29, 51, 87, 80, 62, + 18, 22, 37, 56, 68, 109, 103, 77, + 24, 35, 55, 64, 81, 104, 113, 92, + 49, 64, 78, 87, 103, 121, 120, 101, + 72, 92, 95, 98, 112, 100, 103, 99 + }; + static const uint8_t JPEG_CHROM_QuantTable[JPEG_QUANT_TABLE_SIZE] = + { + 17, 18, 24, 47, 99, 99, 99, 99, + 18, 21, 26, 66, 99, 99, 99, 99, + 24, 26, 56, 99, 99, 99, 99, 99, + 47, 66, 99, 99, 99, 99, 99, 99, + 99, 99, 99, 99, 99, 99, 99, 99, + 99, 99, 99, 99, 99, 99, 99, 99, + 99, 99, 99, 99, 99, 99, 99, 99, + 99, 99, 99, 99, 99, 99, 99, 99 + }; + + /* Check the JPEG handle allocation */ + if (hjpeg == NULL) + { + return HAL_ERROR; + } + +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + if (hjpeg->State == HAL_JPEG_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hjpeg->Lock = HAL_UNLOCKED; + + hjpeg->InfoReadyCallback = HAL_JPEG_InfoReadyCallback; /* Legacy weak InfoReadyCallback */ + hjpeg->EncodeCpltCallback = HAL_JPEG_EncodeCpltCallback; /* Legacy weak EncodeCpltCallback */ + hjpeg->DecodeCpltCallback = HAL_JPEG_DecodeCpltCallback; /* Legacy weak DecodeCpltCallback */ + hjpeg->ErrorCallback = HAL_JPEG_ErrorCallback; /* Legacy weak ErrorCallback */ + hjpeg->GetDataCallback = HAL_JPEG_GetDataCallback; /* Legacy weak GetDataCallback */ + hjpeg->DataReadyCallback = HAL_JPEG_DataReadyCallback; /* Legacy weak DataReadyCallback */ + + if (hjpeg->MspInitCallback == NULL) + { + hjpeg->MspInitCallback = HAL_JPEG_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hjpeg->MspInitCallback(hjpeg); + } +#else + if (hjpeg->State == HAL_JPEG_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hjpeg->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK */ + HAL_JPEG_MspInit(hjpeg); + } +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_BUSY; + + /* Start the JPEG Core*/ + __HAL_JPEG_ENABLE(hjpeg); + + /* Stop the JPEG encoding/decoding process*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + /* Disable All Interrupts */ + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + + /* Disable All DMA requests */ + JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK); + + /* Flush input and output FIFOs*/ + hjpeg->Instance->CR |= JPEG_CR_IFF; + hjpeg->Instance->CR |= JPEG_CR_OFF; + + /* Clear all flags */ + __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL); + + /* init default quantization tables*/ + hjpeg->QuantTable0 = (uint8_t *)((uint32_t)JPEG_LUM_QuantTable); + hjpeg->QuantTable1 = (uint8_t *)((uint32_t)JPEG_CHROM_QuantTable); + hjpeg->QuantTable2 = NULL; + hjpeg->QuantTable3 = NULL; + + /* init the default Huffman tables*/ + if (JPEG_Set_HuffEnc_Mem(hjpeg) != HAL_OK) + { + hjpeg->ErrorCode = HAL_JPEG_ERROR_HUFF_TABLE; + + return HAL_ERROR; + } + + /* Enable header processing*/ + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR; + + /* Reset JpegInCount and JpegOutCount */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /* Reset the JPEG ErrorCode */ + hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE; + + /* Clear the context fields */ + hjpeg->Context = 0; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitializes the JPEG peripheral. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg) +{ + /* Check the JPEG handle allocation */ + if (hjpeg == NULL) + { + return HAL_ERROR; + } + +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + if (hjpeg->MspDeInitCallback == NULL) + { + hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hjpeg->MspDeInitCallback(hjpeg); + +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_JPEG_MspDeInit(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_BUSY; + + /* Reset the JPEG ErrorCode */ + hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE; + + /* Reset JpegInCount and JpegOutCount */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_RESET; + + /*Clear the context fields*/ + hjpeg->Context = 0; + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the JPEG MSP. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +__weak void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes JPEG MSP. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +__weak void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User JPEG Callback + * To be used to override the weak predefined callback + * @param hjpeg JPEG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_JPEG_ENCODE_CPLT_CB_ID Encode Complete callback ID + * @arg @ref HAL_JPEG_DECODE_CPLT_CB_ID Decode Complete callback ID + * @arg @ref HAL_JPEG_ERROR_CB_ID Error callback ID + * @arg @ref HAL_JPEG_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_JPEG_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_RegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID, + pJPEG_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + switch (CallbackID) + { + case HAL_JPEG_ENCODE_CPLT_CB_ID : + hjpeg->EncodeCpltCallback = pCallback; + break; + + case HAL_JPEG_DECODE_CPLT_CB_ID : + hjpeg->DecodeCpltCallback = pCallback; + break; + + case HAL_JPEG_ERROR_CB_ID : + hjpeg->ErrorCallback = pCallback; + break; + + case HAL_JPEG_MSPINIT_CB_ID : + hjpeg->MspInitCallback = pCallback; + break; + + case HAL_JPEG_MSPDEINIT_CB_ID : + hjpeg->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_JPEG_STATE_RESET == hjpeg->State) + { + switch (CallbackID) + { + case HAL_JPEG_MSPINIT_CB_ID : + hjpeg->MspInitCallback = pCallback; + break; + + case HAL_JPEG_MSPDEINIT_CB_ID : + hjpeg->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +/** + * @brief Unregister a JPEG Callback + * JPEG callback is redirected to the weak predefined callback + * @param hjpeg JPEG handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_JPEG_ENCODE_CPLT_CB_ID Encode Complete callback ID + * @arg @ref HAL_JPEG_DECODE_CPLT_CB_ID Decode Complete callback ID + * @arg @ref HAL_JPEG_ERROR_CB_ID Error callback ID + * @arg @ref HAL_JPEG_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_JPEG_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_UnRegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + switch (CallbackID) + { + case HAL_JPEG_ENCODE_CPLT_CB_ID : + hjpeg->EncodeCpltCallback = HAL_JPEG_EncodeCpltCallback; /* Legacy weak EncodeCpltCallback */ + break; + + case HAL_JPEG_DECODE_CPLT_CB_ID : + hjpeg->DecodeCpltCallback = HAL_JPEG_DecodeCpltCallback; /* Legacy weak DecodeCpltCallback */ + break; + + case HAL_JPEG_ERROR_CB_ID : + hjpeg->ErrorCallback = HAL_JPEG_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_JPEG_MSPINIT_CB_ID : + hjpeg->MspInitCallback = HAL_JPEG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_JPEG_MSPDEINIT_CB_ID : + hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_JPEG_STATE_RESET == hjpeg->State) + { + switch (CallbackID) + { + case HAL_JPEG_MSPINIT_CB_ID : + hjpeg->MspInitCallback = HAL_JPEG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_JPEG_MSPDEINIT_CB_ID : + hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit; /* Legacy weak MspInit */ + break; + + default : + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +/** + * @brief Register Info Ready JPEG Callback + * To be used instead of the weak HAL_JPEG_InfoReadyCallback() predefined callback + * @param hjpeg JPEG handle + * @param pCallback pointer to the Info Ready Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_RegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg, + pJPEG_InfoReadyCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + hjpeg->InfoReadyCallback = pCallback; + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +/** + * @brief UnRegister the Info Ready JPEG Callback + * Info Ready JPEG Callback is redirected to the weak HAL_JPEG_InfoReadyCallback() predefined callback + * @param hjpeg JPEG handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_UnRegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + hjpeg->InfoReadyCallback = HAL_JPEG_InfoReadyCallback; /* Legacy weak InfoReadyCallback */ + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +/** + * @brief Register Get Data JPEG Callback + * To be used instead of the weak HAL_JPEG_GetDataCallback() predefined callback + * @param hjpeg JPEG handle + * @param pCallback pointer to the Get Data Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_RegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + hjpeg->GetDataCallback = pCallback; + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +/** + * @brief UnRegister the Get Data JPEG Callback + * Get Data JPEG Callback is redirected to the weak HAL_JPEG_GetDataCallback() predefined callback + * @param hjpeg JPEG handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_UnRegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + hjpeg->GetDataCallback = HAL_JPEG_GetDataCallback; /* Legacy weak GetDataCallback */ + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +/** + * @brief Register Data Ready JPEG Callback + * To be used instead of the weak HAL_JPEG_DataReadyCallback() predefined callback + * @param hjpeg JPEG handle + * @param pCallback pointer to the Get Data Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_RegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg, + pJPEG_DataReadyCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + hjpeg->DataReadyCallback = pCallback; + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +/** + * @brief UnRegister the Data Ready JPEG Callback + * Get Data Ready Callback is redirected to the weak HAL_JPEG_DataReadyCallback() predefined callback + * @param hjpeg JPEG handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + hjpeg->DataReadyCallback = HAL_JPEG_DataReadyCallback; /* Legacy weak DataReadyCallback */ + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup JPEG_Exported_Functions_Group2 Configuration functions + * @brief JPEG Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_JPEG_ConfigEncoding() : JPEG encoding configuration + (+) HAL_JPEG_GetInfo() : Extract the image configuration from the JPEG header during the decoding + (+) HAL_JPEG_EnableHeaderParsing() : Enable JPEG Header parsing for decoding + (+) HAL_JPEG_DisableHeaderParsing() : Disable JPEG Header parsing for decoding + (+) HAL_JPEG_SetUserQuantTables : Modify the default Quantization tables used for JPEG encoding. + +@endverbatim + * @{ + */ + +/** + * @brief Set the JPEG encoding configuration. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pConf pointer to a JPEG_ConfTypeDef structure that contains + * the encoding configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, const JPEG_ConfTypeDef *pConf) +{ + uint32_t error; + uint32_t numberMCU; + uint32_t hfactor; + uint32_t vfactor; + uint32_t hMCU; + uint32_t vMCU; + + /* Check the JPEG handle allocation */ + if ((hjpeg == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + else + { + /* Check the parameters */ + assert_param(IS_JPEG_COLORSPACE(pConf->ColorSpace)); + assert_param(IS_JPEG_CHROMASUBSAMPLING(pConf->ChromaSubsampling)); + assert_param(IS_JPEG_IMAGE_QUALITY(pConf->ImageQuality)); + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + hjpeg->State = HAL_JPEG_STATE_BUSY; + + hjpeg->Conf.ColorSpace = pConf->ColorSpace; + hjpeg->Conf.ChromaSubsampling = pConf->ChromaSubsampling; + hjpeg->Conf.ImageHeight = pConf->ImageHeight; + hjpeg->Conf.ImageWidth = pConf->ImageWidth; + hjpeg->Conf.ImageQuality = pConf->ImageQuality; + + /* Reset the Color Space : by default only one quantization table is used*/ + hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_COLORSPACE; + + /* Set Number of color components*/ + if (hjpeg->Conf.ColorSpace == JPEG_GRAYSCALE_COLORSPACE) + { + /*Gray Scale is only one component 8x8 blocks i.e 4:4:4*/ + hjpeg->Conf.ChromaSubsampling = JPEG_444_SUBSAMPLING; + + JPEG_SetColorGrayScale(hjpeg); + /* Set quantization table 0*/ + error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0)); + } + else if (hjpeg->Conf.ColorSpace == JPEG_YCBCR_COLORSPACE) + { + /* + Set the Color Space for YCbCr : 2 quantization tables are used + one for Luminance(Y) and one for both Chrominances (Cb & Cr) + */ + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_0; + + JPEG_SetColorYCBCR(hjpeg); + + /* Set quantization table 0*/ + error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0)); + /*By default quantization table 0 for component 0 and quantization table 1 for both components 1 and 2*/ + (void) JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1)); + + if ((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0UL) + { + /*Use user customized quantization tables , 1 table per component*/ + /* use 3 quantization tables , one for each component*/ + hjpeg->Instance->CONFR1 &= (~JPEG_CONFR1_COLORSPACE); + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_1; + + (void) JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2)); + + /*Use Quantization 1 table for component 1*/ + hjpeg->Instance->CONFR5 &= (~JPEG_CONFR5_QT); + hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0; + + /*Use Quantization 2 table for component 2*/ + hjpeg->Instance->CONFR6 &= (~JPEG_CONFR6_QT); + hjpeg->Instance->CONFR6 |= JPEG_CONFR6_QT_1; + } + } + else /* ColorSpace == JPEG_CMYK_COLORSPACE */ + { + JPEG_SetColorCMYK(hjpeg); + + /* Set quantization table 0*/ + error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0)); + /*By default quantization table 0 for All components*/ + + if ((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0UL) + { + /*Use user customized quantization tables , 1 table per component*/ + /* use 4 quantization tables , one for each component*/ + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE; + + (void) JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1)); + (void) JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2)); + (void) JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable3, (hjpeg->Instance->QMEM3)); + + /*Use Quantization 1 table for component 1*/ + hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0; + + /*Use Quantization 2 table for component 2*/ + hjpeg->Instance->CONFR6 |= JPEG_CONFR6_QT_1; + + /*Use Quantization 3 table for component 3*/ + hjpeg->Instance->CONFR7 |= JPEG_CONFR7_QT; + } + } + + if (error != 0UL) + { + hjpeg->ErrorCode = HAL_JPEG_ERROR_QUANT_TABLE; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Set the JPEG State to ready */ + hjpeg->State = HAL_JPEG_STATE_READY; + + return HAL_ERROR; + } + /* Set the image size*/ + /* set the number of lines*/ + MODIFY_REG(hjpeg->Instance->CONFR1, JPEG_CONFR1_YSIZE, ((hjpeg->Conf.ImageHeight & 0x0000FFFFUL) << 16)); + /* set the number of pixels per line*/ + MODIFY_REG(hjpeg->Instance->CONFR3, JPEG_CONFR3_XSIZE, ((hjpeg->Conf.ImageWidth & 0x0000FFFFUL) << 16)); + + + if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) /* 4:2:0*/ + { + hfactor = 16; + vfactor = 16; + } + else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) /* 4:2:2*/ + { + hfactor = 16; + vfactor = 8; + } + else /* Default is 8x8 MCU, 4:4:4*/ + { + hfactor = 8; + vfactor = 8; + } + + hMCU = (hjpeg->Conf.ImageWidth / hfactor); + if ((hjpeg->Conf.ImageWidth % hfactor) != 0UL) + { + hMCU++; /*+1 for horizontal incomplete MCU */ + } + + vMCU = (hjpeg->Conf.ImageHeight / vfactor); + if ((hjpeg->Conf.ImageHeight % vfactor) != 0UL) + { + vMCU++; /*+1 for vertical incomplete MCU */ + } + + numberMCU = (hMCU * vMCU) - 1UL; /* Bit Field JPEG_CONFR2_NMCU shall be set to NB_MCU - 1*/ + /* Set the number of MCU*/ + hjpeg->Instance->CONFR2 = (numberMCU & JPEG_CONFR2_NMCU); + + hjpeg->Context |= JPEG_CONTEXT_CONF_ENCODING; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Set the JPEG State to ready */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Return function status */ + return HAL_BUSY; + } + } +} + +/** + * @brief Extract the image configuration from the JPEG header during the decoding + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pInfo pointer to a JPEG_ConfTypeDef structure that contains + * The JPEG decoded header information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo) +{ + uint32_t yblockNb; + uint32_t cBblockNb; + uint32_t cRblockNb; + + /* Check the JPEG handle allocation */ + if ((hjpeg == NULL) || (pInfo == NULL)) + { + return HAL_ERROR; + } + + /*Read the conf parameters */ + if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF_1) + { + pInfo->ColorSpace = JPEG_YCBCR_COLORSPACE; + } + else if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == 0UL) + { + pInfo->ColorSpace = JPEG_GRAYSCALE_COLORSPACE; + } + else if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF) + { + pInfo->ColorSpace = JPEG_CMYK_COLORSPACE; + } + else + { + return HAL_ERROR; + } + + pInfo->ImageHeight = (hjpeg->Instance->CONFR1 & 0xFFFF0000UL) >> 16; + pInfo->ImageWidth = (hjpeg->Instance->CONFR3 & 0xFFFF0000UL) >> 16; + + if ((pInfo->ColorSpace == JPEG_YCBCR_COLORSPACE) || (pInfo->ColorSpace == JPEG_CMYK_COLORSPACE)) + { + yblockNb = (hjpeg->Instance->CONFR4 & JPEG_CONFR4_NB) >> 4; + cBblockNb = (hjpeg->Instance->CONFR5 & JPEG_CONFR5_NB) >> 4; + cRblockNb = (hjpeg->Instance->CONFR6 & JPEG_CONFR6_NB) >> 4; + + if ((yblockNb == 1UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL)) + { + pInfo->ChromaSubsampling = JPEG_422_SUBSAMPLING; /*16x8 block*/ + } + else if ((yblockNb == 0UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL)) + { + pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING; + } + else if ((yblockNb == 3UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL)) + { + pInfo->ChromaSubsampling = JPEG_420_SUBSAMPLING; + } + else /*Default is 4:4:4*/ + { + pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING; + } + } + else + { + pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING; + } + + pInfo->ImageQuality = JPEG_GetQuality(hjpeg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enable JPEG Header parsing for decoding + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for the JPEG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg) +{ + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_BUSY; + + /* Enable header processing*/ + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR; + + /* Process unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + return HAL_OK; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } +} + +/** + * @brief Disable JPEG Header parsing for decoding + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for the JPEG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg) +{ + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_BUSY; + + /* Disable header processing*/ + hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_HDR; + + /* Process unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + return HAL_OK; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } +} + +/** + * @brief Modify the default Quantization tables used for JPEG encoding. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param QTable0 pointer to uint8_t , define the user quantification table for color component 1. + * If NULL assume no need to update the table and no error return + * @param QTable1 pointer to uint8_t , define the user quantification table for color component 2. + * If NULL assume no need to update the table and no error return. + * @param QTable2 pointer to uint8_t , define the user quantification table for color component 3, + * If NULL assume no need to update the table and no error return. + * @param QTable3 pointer to uint8_t , define the user quantification table for color component 4. + * If NULL assume no need to update the table and no error return. + * + * @retval HAL status + */ + + +HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, + uint8_t *QTable2, uint8_t *QTable3) +{ + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + /* Change the DMA state */ + hjpeg->State = HAL_JPEG_STATE_BUSY; + + hjpeg->Context |= JPEG_CONTEXT_CUSTOM_TABLES; + + hjpeg->QuantTable0 = QTable0; + hjpeg->QuantTable1 = QTable1; + hjpeg->QuantTable2 = QTable2; + hjpeg->QuantTable3 = QTable3; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the DMA state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** @defgroup JPEG_Exported_Functions_Group3 encoding/decoding processing functions + * @brief processing functions. + * +@verbatim + ============================================================================== + ##### JPEG processing functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_JPEG_Encode() : JPEG encoding with polling process + (+) HAL_JPEG_Decode() : JPEG decoding with polling process + (+) HAL_JPEG_Encode_IT() : JPEG encoding with interrupt process + (+) HAL_JPEG_Decode_IT() : JPEG decoding with interrupt process + (+) HAL_JPEG_Encode_DMA() : JPEG encoding with DMA process + (+) HAL_JPEG_Decode_DMA() : JPEG decoding with DMA process + (+) HAL_JPEG_Pause() : Pause the Input/Output processing + (+) HAL_JPEG_Resume() : Resume the JPEG Input/Output processing + (+) HAL_JPEG_ConfigInputBuffer() : Config Encoding/Decoding Input Buffer + (+) HAL_JPEG_ConfigOutputBuffer() : Config Encoding/Decoding Output Buffer + (+) HAL_JPEG_Abort() : Aborts the JPEG Encoding/Decoding + +@endverbatim + * @{ + */ + +/** + * @brief Starts JPEG encoding with polling processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataInMCU Pointer to the Input buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOut Pointer to the jpeg output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, + uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param((InDataLength >= 4UL)); + assert_param((OutDataLength >= 4UL)); + + /* Check In/out buffer allocation and size */ + if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL)) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State != HAL_JPEG_STATE_READY) + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING; + + /*Set the Context to Encode with Polling*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_POLLING); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataInMCU; + hjpeg->pJpegOutBuffPtr = pDataOut; + hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /* In Data length must be multiple + of 4 Bytes (1 word)*/ + hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /* Out Data length must be multiple + of 4 Bytes (1 word)*/ + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + /*JPEG data processing : In/Out FIFO transfer*/ + while ((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + + /* Update error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_READY; + + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_ERROR; + } + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts JPEG decoding with polling processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataIn Pointer to the input data buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOutMCU Pointer to the Output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, + uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param((InDataLength >= 4UL)); + assert_param((OutDataLength >= 4UL)); + + /* Check In/out buffer allocation and size */ + if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + /* Get tick */ + tickstart = HAL_GetTick(); + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING; + + /*Set the Context to Decode with Polling*/ + /*Set the Context to Encode with Polling*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_POLLING); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataIn; + hjpeg->pJpegOutBuffPtr = pDataOutMCU; + hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /*In Data length must be multiple + of 4 Bytes (1 word)*/ + hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple + of 4 Bytes (1 word)*/ + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + /*JPEG data processing : In/Out FIFO transfer*/ + while ((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + + /* Update error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_READY; + + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts JPEG encoding with interrupt processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataInMCU Pointer to the Input buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOut Pointer to the jpeg output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, + uint8_t *pDataOut, uint32_t OutDataLength) +{ + /* Check the parameters */ + assert_param((InDataLength >= 4UL)); + assert_param((OutDataLength >= 4UL)); + + /* Check In/out buffer allocation and size */ + if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State != HAL_JPEG_STATE_READY) + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + else + { + if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING; + + /*Set the Context to Encode with IT*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_IT); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataInMCU; + hjpeg->pJpegOutBuffPtr = pDataOut; + hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /*In Data length must be multiple + of 4 Bytes (1 word)*/ + hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple + of 4 Bytes (1 word)*/ + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_ERROR; + } + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts JPEG decoding with interrupt processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataIn Pointer to the input data buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOutMCU Pointer to the Output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, + uint8_t *pDataOutMCU, uint32_t OutDataLength) +{ + /* Check the parameters */ + assert_param((InDataLength >= 4UL)); + assert_param((OutDataLength >= 4UL)); + + /* Check In/out buffer allocation and size */ + if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING; + + /*Set the Context to Decode with IT*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_IT); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataIn; + hjpeg->pJpegOutBuffPtr = pDataOutMCU; + hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /*In Data length must be multiple + of 4 Bytes (1 word)*/ + hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple + of 4 Bytes (1 word)*/ + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts JPEG encoding with DMA processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataInMCU Pointer to the Input buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOut Pointer to the jpeg output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, + uint8_t *pDataOut, uint32_t OutDataLength) +{ + /* Check the parameters */ + assert_param((InDataLength >= 4UL)); + assert_param((OutDataLength >= 4UL)); + + /* Check In/out buffer allocation and size */ + if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State != HAL_JPEG_STATE_READY) + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + else + { + if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING; + + /*Set the Context to Encode with DMA*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_DMA); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataInMCU; + hjpeg->pJpegOutBuffPtr = pDataOut; + hjpeg->InDataLength = InDataLength; + hjpeg->OutDataLength = OutDataLength; + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + /* JPEG encoding process using DMA */ + if (JPEG_DMA_StartProcess(hjpeg) != HAL_OK) + { + /* Update State */ + hjpeg->State = HAL_JPEG_STATE_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_ERROR; + } + + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_ERROR; + } + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts JPEG decoding with DMA processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataIn Pointer to the input data buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOutMCU Pointer to the Output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, + uint8_t *pDataOutMCU, uint32_t OutDataLength) +{ + /* Check the parameters */ + assert_param((InDataLength >= 4UL)); + assert_param((OutDataLength >= 4UL)); + + /* Check In/out buffer allocation and size */ + if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING; + + /*Set the Context to Decode with DMA*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_DMA); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataIn; + hjpeg->pJpegOutBuffPtr = pDataOutMCU; + hjpeg->InDataLength = InDataLength; + hjpeg->OutDataLength = OutDataLength; + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + /* JPEG decoding process using DMA */ + if (JPEG_DMA_StartProcess(hjpeg) != HAL_OK) + { + /* Update State */ + hjpeg->State = HAL_JPEG_STATE_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_ERROR; + } + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Pause the JPEG Input/Output processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param XferSelection This parameter can be one of the following values : + * JPEG_PAUSE_RESUME_INPUT : Pause Input processing + * JPEG_PAUSE_RESUME_OUTPUT: Pause Output processing + * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Pause Input and Output processing + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection) +{ + uint32_t mask = 0; + + assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection)); + + if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) + { + if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) + { + hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT; + mask |= JPEG_DMA_IDMA; + } + if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) + { + hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT; + mask |= JPEG_DMA_ODMA; + } + JPEG_DISABLE_DMA(hjpeg, mask); + + } + else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) + { + + if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) + { + hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT; + mask |= (JPEG_IT_IFT | JPEG_IT_IFNF); + } + if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) + { + hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT; + mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC); + } + __HAL_JPEG_DISABLE_IT(hjpeg, mask); + + } + else + { + /* Nothing to do */ + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Resume the JPEG Input/Output processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param XferSelection This parameter can be one of the following values : + * JPEG_PAUSE_RESUME_INPUT : Resume Input processing + * JPEG_PAUSE_RESUME_OUTPUT: Resume Output processing + * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Resume Input and Output processing + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection) +{ + uint32_t mask = 0; + + assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection)); + + if ((hjpeg->Context & (JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT)) == 0UL) + { + /* if nothing paused to resume return error*/ + return HAL_ERROR; + } + + if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) + { + + if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) + { + hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT); + mask |= JPEG_DMA_IDMA; + + /*JPEG Input DMA transfer data number must be multiple of DMA buffer size + as the destination is a 32 bits register */ + hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL); + + if (hjpeg->InDataLength > 0UL) + { + /* Start DMA FIFO In transfer */ + if (HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, + hjpeg->InDataLength) != HAL_OK) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + hjpeg->State = HAL_JPEG_STATE_ERROR; + return HAL_ERROR; + } + } + } + if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) + { + hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT); + + if ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0UL) + { + JPEG_DMA_PollResidualData(hjpeg); + } + else + { + mask |= JPEG_DMA_ODMA; + + /* Start DMA FIFO Out transfer */ + if (HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, + hjpeg->OutDataLength) != HAL_OK) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + hjpeg->State = HAL_JPEG_STATE_ERROR; + return HAL_ERROR; + } + } + + } + JPEG_ENABLE_DMA(hjpeg, mask); + + } + else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) + { + if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) + { + hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT); + mask |= (JPEG_IT_IFT | JPEG_IT_IFNF); + } + if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) + { + hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT); + mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC); + } + __HAL_JPEG_ENABLE_IT(hjpeg, mask); + + } + else + { + /* Nothing to do */ + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Config Encoding/Decoding Input Buffer. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module. + * @param pNewInputBuffer Pointer to the new input data buffer + * @param InDataLength Size in bytes of the new Input data buffer + * @retval HAL status + */ +void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength) +{ + hjpeg->pJpegInBuffPtr = pNewInputBuffer; + hjpeg->InDataLength = InDataLength; +} + +/** + * @brief Config Encoding/Decoding Output Buffer. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module. + * @param pNewOutputBuffer Pointer to the new output data buffer + * @param OutDataLength Size in bytes of the new Output data buffer + * @retval HAL status + */ +void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength) +{ + hjpeg->pJpegOutBuffPtr = pNewOutputBuffer; + hjpeg->OutDataLength = OutDataLength; +} + +/** + * @brief Aborts the JPEG Encoding/Decoding. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t tickstart; + uint32_t tmpContext; + tmpContext = hjpeg->Context; + + /*Reset the Context operation and method*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA); + + if ((tmpContext & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) + { + /* Stop the DMA In/out Xfer*/ + if (HAL_DMA_Abort(hjpeg->hdmaout) != HAL_OK) + { + if (hjpeg->hdmaout->ErrorCode == HAL_DMA_ERROR_TIMEOUT) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + } + } + if (HAL_DMA_Abort(hjpeg->hdmain) != HAL_OK) + { + if (hjpeg->hdmain->ErrorCode == HAL_DMA_ERROR_TIMEOUT) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + } + } + + } + + /* Stop the JPEG encoding/decoding process*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the JPEG Codec is effectively disabled */ + while (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_COF) != 0UL) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > JPEG_TIMEOUT_VALUE) + { + /* Update error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; + + /* Change the DMA state */ + hjpeg->State = HAL_JPEG_STATE_ERROR; + break; + } + } + + /* Disable All Interrupts */ + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + + /* Disable All DMA requests */ + JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK); + + /* Flush input and output FIFOs*/ + hjpeg->Instance->CR |= JPEG_CR_IFF; + hjpeg->Instance->CR |= JPEG_CR_OFF; + + /* Clear all flags */ + __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL); + + /* Reset JpegInCount and JpegOutCount */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Reset the Context Pause*/ + hjpeg->Context &= ~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT); + + /* Change the DMA state*/ + if (hjpeg->ErrorCode != HAL_JPEG_ERROR_NONE) + { + hjpeg->State = HAL_JPEG_STATE_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + /* Return function status */ + return HAL_ERROR; + } + else + { + hjpeg->State = HAL_JPEG_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + /* Return function status */ + return HAL_OK; + } + +} + + +/** + * @} + */ + +/** @defgroup JPEG_Exported_Functions_Group4 JPEG Decode/Encode callback functions + * @brief JPEG process callback functions. + * +@verbatim + ============================================================================== + ##### JPEG Decode and Encode callback functions ##### + ============================================================================== + [..] This section provides callback functions: + (+) HAL_JPEG_InfoReadyCallback() : Decoding JPEG Info ready callback + (+) HAL_JPEG_EncodeCpltCallback() : Encoding complete callback. + (+) HAL_JPEG_DecodeCpltCallback() : Decoding complete callback. + (+) HAL_JPEG_ErrorCallback() : JPEG error callback. + (+) HAL_JPEG_GetDataCallback() : Get New Data chunk callback. + (+) HAL_JPEG_DataReadyCallback() : Decoded/Encoded Data ready callback. + +@endverbatim + * @{ + */ + +/** + * @brief Decoding JPEG Info ready callback. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pInfo pointer to a JPEG_ConfTypeDef structure that contains + * The JPEG decoded header information + * @retval None + */ +__weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + UNUSED(pInfo); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_HeaderParsingCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Encoding complete callback. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +__weak void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_EncodeCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Decoding complete callback. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +__weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_EncodeCpltCallback could be implemented in the user file + */ +} + +/** + * @brief JPEG error callback. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +__weak void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Get New Data chunk callback. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param NbDecodedData Number of consumed data in the previous chunk in bytes + * @retval None + */ +__weak void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + UNUSED(NbDecodedData); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_GetDataCallback could be implemented in the user file + */ +} + +/** + * @brief Decoded/Encoded Data ready callback. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataOut pointer to the output data buffer + * @param OutDataLength number in bytes of data available in the specified output buffer + * @retval None + */ +__weak void HAL_JPEG_DataReadyCallback(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + UNUSED(pDataOut); + UNUSED(OutDataLength); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_DataReadyCallback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** @defgroup JPEG_Exported_Functions_Group5 JPEG IRQ handler management + * @brief JPEG IRQ handler. + * +@verbatim + ============================================================================== + ##### JPEG IRQ handler management ##### + ============================================================================== + [..] This section provides JPEG IRQ handler function. + (+) HAL_JPEG_IRQHandler() : handles JPEG interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief This function handles JPEG interrupt request. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg) +{ + switch (hjpeg->State) + { + case HAL_JPEG_STATE_BUSY_ENCODING: + case HAL_JPEG_STATE_BUSY_DECODING: + /* continue JPEG data encoding/Decoding*/ + /* JPEG data processing : In/Out FIFO transfer*/ + if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) + { + (void) JPEG_Process(hjpeg); + } + else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) + { + JPEG_DMA_ContinueProcess(hjpeg); + } + else + { + /* Nothing to do */ + } + break; + + default: + break; + } +} + +/** + * @} + */ + +/** @defgroup JPEG_Exported_Functions_Group6 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] This section provides JPEG State and Errors function. + (+) HAL_JPEG_GetState() : permits to get in run-time the JPEG state. + (+) HAL_JPEG_GetError() : Returns the JPEG error code if any. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the JPEG state. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG state + */ +HAL_JPEG_STATETypeDef HAL_JPEG_GetState(const JPEG_HandleTypeDef *hjpeg) +{ + return hjpeg->State; +} + +/** + * @brief Return the JPEG error code + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for the specified JPEG. + * @retval JPEG Error Code + */ +uint32_t HAL_JPEG_GetError(const JPEG_HandleTypeDef *hjpeg) +{ + return hjpeg->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + + +/** @addtogroup JPEG_Private_Functions + * @{ + */ + +/** + * @brief Generates Huffman sizes/Codes Table from Bits/vals Table + * @param Bits pointer to bits table + * @param Huffsize pointer to sizes table + * @param Huffcode pointer to codes table + * @param LastK pointer to last Coeff (table dimension) + * @retval HAL status + */ +static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(const uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, + uint32_t *LastK) +{ + uint32_t i; + uint32_t j; + uint32_t k; + uint32_t code; + uint32_t si; + + /* Figure C.1: Generation of table of Huffman code sizes */ + j = 0; + for (k = 0; k < 16UL; k++) + { + i = (uint32_t)Bits[k]; + if ((j + i) > 256UL) + { + /* check for table overflow */ + return HAL_ERROR; + } + while (i != 0UL) + { + Huffsize[j] = (uint8_t) k + 1U; + j++; + i--; + } + } + Huffsize[j] = 0; + *LastK = j; + + /* Figure C.2: Generation of table of Huffman codes */ + code = 0; + si = Huffsize[0]; + j = 0; + while (Huffsize[j] != 0U) + { + while (((uint32_t) Huffsize[j]) == si) + { + Huffcode[j] = code; + j++; + code++; + } + /* code must fit in "size" bits (si), no code is allowed to be all ones*/ + if (si > 31UL) + { + return HAL_ERROR; + } + if (((uint32_t) code) >= (((uint32_t) 1) << si)) + { + return HAL_ERROR; + } + code <<= 1; + si++; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table + * that can programmed to the JPEG encoder registers + * @param AC_BitsValsTable pointer to AC huffman bits/vals table + * @param AC_SizeCodesTable pointer to AC huffman Sizes/Codes table + * @retval HAL status + */ +static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, + JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable) +{ + HAL_StatusTypeDef error; + uint8_t huffsize[257]; + uint32_t huffcode[257]; + uint32_t k; + uint32_t i; + uint32_t lsb; + uint32_t msb; + uint32_t lastK; + + error = JPEG_Bits_To_SizeCodes(AC_BitsValsTable->Bits, huffsize, huffcode, &lastK); + if (error != HAL_OK) + { + return error; + } + + /* Figure C.3: Ordering procedure for encoding procedure code tables */ + k = 0; + + while (k < lastK) + { + i = AC_BitsValsTable->HuffVal[k]; + if (i == 0UL) + { + i = JPEG_AC_HUFF_TABLE_SIZE - 2UL; /*i = 0x00 EOB code*/ + } + else if (i == 0xF0UL) /* i = 0xF0 ZRL code*/ + { + i = JPEG_AC_HUFF_TABLE_SIZE - 1UL; + } + else + { + msb = (i & 0xF0UL) >> 4; + lsb = (i & 0x0FUL); + i = (msb * 10UL) + lsb - 1UL; + } + if (i >= JPEG_AC_HUFF_TABLE_SIZE) + { + return HAL_ERROR; /* Huffman Table overflow error*/ + } + else + { + AC_SizeCodesTable->HuffmanCode[i] = huffcode[k]; + AC_SizeCodesTable->CodeLength[i] = huffsize[k] - 1U; + k++; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table + * that can programmed to the JPEG encoder registers + * @param DC_BitsValsTable pointer to DC huffman bits/vals table + * @param DC_SizeCodesTable pointer to DC huffman Sizes/Codes table + * @retval HAL status + */ +static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, + JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable) +{ + HAL_StatusTypeDef error; + + uint32_t k; + uint32_t i; + uint32_t lastK; + uint8_t huffsize[257]; + uint32_t huffcode[257]; + error = JPEG_Bits_To_SizeCodes(DC_BitsValsTable->Bits, huffsize, huffcode, &lastK); + if (error != HAL_OK) + { + return error; + } + /* Figure C.3: ordering procedure for encoding procedure code tables */ + k = 0; + + while (k < lastK) + { + i = DC_BitsValsTable->HuffVal[k]; + if (i >= JPEG_DC_HUFF_TABLE_SIZE) + { + return HAL_ERROR; /* Huffman Table overflow error*/ + } + else + { + DC_SizeCodesTable->HuffmanCode[i] = huffcode[k]; + DC_SizeCodesTable->CodeLength[i] = huffsize[k] - 1U; + k++; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the JPEG register with an DC huffman table at the given DC table address + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param HuffTableDC pointer to DC huffman table + * @param DCTableAddress Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1. + * @retval HAL status + */ +static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(const JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, + const __IO uint32_t *DCTableAddress) +{ + HAL_StatusTypeDef error; + JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable; + uint32_t i; + uint32_t lsb; + uint32_t msb; + __IO uint32_t *address; + __IO uint32_t *addressDef; + + if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC0)) + { + address = (hjpeg->Instance->HUFFENC_DC0 + (JPEG_DC_HUFF_TABLE_SIZE / 2UL)); + } + else if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC1)) + { + address = (hjpeg->Instance->HUFFENC_DC1 + (JPEG_DC_HUFF_TABLE_SIZE / 2UL)); + } + else + { + return HAL_ERROR; + } + + if (HuffTableDC != NULL) + { + error = JPEG_DCHuff_BitsVals_To_SizeCodes(HuffTableDC, &dcSizeCodesTable); + if (error != HAL_OK) + { + return error; + } + addressDef = address; + *addressDef = 0x0FFF0FFF; + addressDef++; + *addressDef = 0x0FFF0FFF; + + i = JPEG_DC_HUFF_TABLE_SIZE; + while (i > 1UL) + { + i--; + address --; + msb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | + ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFFUL); + i--; + lsb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | + ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFFUL); + + *address = lsb | (msb << 16); + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the JPEG register with an AC huffman table at the given AC table address + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param HuffTableAC pointer to AC huffman table + * @param ACTableAddress Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1. + * @retval HAL status + */ +static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(const JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, + const __IO uint32_t *ACTableAddress) +{ + HAL_StatusTypeDef error; + JPEG_AC_HuffCodeTableTypeDef acSizeCodesTable; + uint32_t i; + uint32_t lsb; + uint32_t msb; + __IO uint32_t *address; + __IO uint32_t *addressDef; + + if (ACTableAddress == (hjpeg->Instance->HUFFENC_AC0)) + { + address = (hjpeg->Instance->HUFFENC_AC0 + (JPEG_AC_HUFF_TABLE_SIZE / 2UL)); + } + else if (ACTableAddress == (hjpeg->Instance->HUFFENC_AC1)) + { + address = (hjpeg->Instance->HUFFENC_AC1 + (JPEG_AC_HUFF_TABLE_SIZE / 2UL)); + } + else + { + return HAL_ERROR; + } + + if (HuffTableAC != NULL) + { + error = JPEG_ACHuff_BitsVals_To_SizeCodes(HuffTableAC, &acSizeCodesTable); + if (error != HAL_OK) + { + return error; + } + /* Default values settings: 162:167 FFFh , 168:175 FD0h_FD7h */ + /* Locations 162:175 of each AC table contain information used internally by the core */ + + addressDef = address; + for (i = 0; i < 3UL; i++) + { + *addressDef = 0x0FFF0FFF; + addressDef++; + } + *addressDef = 0x0FD10FD0; + addressDef++; + *addressDef = 0x0FD30FD2; + addressDef++; + *addressDef = 0x0FD50FD4; + addressDef++; + *addressDef = 0x0FD70FD6; + /* end of Locations 162:175 */ + + + i = JPEG_AC_HUFF_TABLE_SIZE; + while (i > 1UL) + { + i--; + address--; + msb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | + ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFFUL); + i--; + lsb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | + ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFFUL); + + *address = lsb | (msb << 16); + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the JPEG encoder register huffman tables to used during + * the encdoing operation + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg) +{ + HAL_StatusTypeDef error; + + JPEG_Set_Huff_DHTMem(hjpeg); + error = JPEG_Set_HuffAC_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACLUM_HuffTable, + (hjpeg->Instance->HUFFENC_AC0)); + if (error != HAL_OK) + { + return error; + } + + error = JPEG_Set_HuffAC_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACCHROM_HuffTable, + (hjpeg->Instance->HUFFENC_AC1)); + if (error != HAL_OK) + { + return error; + } + + error = JPEG_Set_HuffDC_Mem(hjpeg, (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCLUM_HuffTable, + hjpeg->Instance->HUFFENC_DC0); + if (error != HAL_OK) + { + return error; + } + + error = JPEG_Set_HuffDC_Mem(hjpeg, (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCCHROM_HuffTable, + hjpeg->Instance->HUFFENC_DC1); + if (error != HAL_OK) + { + return error; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the JPEG register huffman tables to be included in the JPEG + * file header (used for encoding only) + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static void JPEG_Set_Huff_DHTMem(const JPEG_HandleTypeDef *hjpeg) +{ + const JPEG_ACHuffTableTypeDef *HuffTableAC0 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACLUM_HuffTable; + const JPEG_ACHuffTableTypeDef *HuffTableAC1 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACCHROM_HuffTable; + const JPEG_DCHuffTableTypeDef *HuffTableDC0 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCLUM_HuffTable; + const JPEG_DCHuffTableTypeDef *HuffTableDC1 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCCHROM_HuffTable; + uint32_t value; + uint32_t index; + __IO uint32_t *address; + + /* DC0 Huffman Table : BITS*/ + /* DC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address to DHTMEM + 3*/ + address = (hjpeg->Instance->DHTMEM + 3); + index = 16; + while (index > 3UL) + { + + *address = (((uint32_t)HuffTableDC0->Bits[index - 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableDC0->Bits[index - 2UL] & 0xFFUL) << 16) | + (((uint32_t)HuffTableDC0->Bits[index - 3UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableDC0->Bits[index - 4UL] & 0xFFUL); + address--; + index -= 4UL; + + } + /* DC0 Huffman Table : Val*/ + /* DC0 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +4 to DHTMEM + 6 */ + address = (hjpeg->Instance->DHTMEM + 6); + index = 12; + while (index > 3UL) + { + *address = (((uint32_t)HuffTableDC0->HuffVal[index - 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableDC0->HuffVal[index - 2UL] & 0xFFUL) << 16) | + (((uint32_t)HuffTableDC0->HuffVal[index - 3UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableDC0->HuffVal[index - 4UL] & 0xFFUL); + address--; + index -= 4UL; + } + + /* AC0 Huffman Table : BITS*/ + /* AC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 7 to DHTMEM + 10*/ + address = (hjpeg->Instance->DHTMEM + 10UL); + index = 16; + while (index > 3UL) + { + + *address = (((uint32_t)HuffTableAC0->Bits[index - 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableAC0->Bits[index - 2UL] & 0xFFUL) << 16) | + (((uint32_t)HuffTableAC0->Bits[index - 3UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableAC0->Bits[index - 4UL] & 0xFFUL); + address--; + index -= 4UL; + + } + /* AC0 Huffman Table : Val*/ + /* AC0 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 11 to DHTMEM + 51 */ + /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 51) belong to AC0 VALS table */ + address = (hjpeg->Instance->DHTMEM + 51); + value = *address & 0xFFFF0000U; + value = value | (((uint32_t)HuffTableAC0->HuffVal[161] & 0xFFUL) << 8) | + ((uint32_t)HuffTableAC0->HuffVal[160] & 0xFFUL); + *address = value; + + /*continue setting 160 AC0 huffman values */ + address--; /* address = hjpeg->Instance->DHTMEM + 50*/ + index = JPEG_AC_HUFF_TABLE_SIZE - 2UL; + while (index > 3UL) + { + *address = (((uint32_t)HuffTableAC0->HuffVal[index - 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableAC0->HuffVal[index - 2UL] & 0xFFUL) << 16) | + (((uint32_t)HuffTableAC0->HuffVal[index - 3UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableAC0->HuffVal[index - 4UL] & 0xFFUL); + address--; + index -= 4UL; + } + + /* DC1 Huffman Table : BITS*/ + /* DC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM + 51 base address to DHTMEM + 55*/ + /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 51) belong to DC1 Bits table */ + address = (hjpeg->Instance->DHTMEM + 51); + value = *address & 0x0000FFFFU; + value = value | (((uint32_t)HuffTableDC1->Bits[1] & 0xFFUL) << 24) | + (((uint32_t)HuffTableDC1->Bits[0] & 0xFFUL) << 16); + *address = value; + + /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 55) belong to DC1 Bits table */ + address = (hjpeg->Instance->DHTMEM + 55); + value = *address & 0xFFFF0000U; + value = value | (((uint32_t)HuffTableDC1->Bits[15] & 0xFFUL) << 8) | + ((uint32_t)HuffTableDC1->Bits[14] & 0xFFUL); + *address = value; + + /*continue setting 12 DC1 huffman Bits from DHTMEM + 54 down to DHTMEM + 52*/ + address--; + index = 12; + while (index > 3UL) + { + + *address = (((uint32_t)HuffTableDC1->Bits[index + 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableDC1->Bits[index] & 0xFFUL) << 16) | + (((uint32_t)HuffTableDC1->Bits[index - 1UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableDC1->Bits[index - 2UL] & 0xFFUL); + address--; + index -= 4UL; + + } + /* DC1 Huffman Table : Val*/ + /* DC1 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +55 to DHTMEM + 58 */ + /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 55) belong to DC1 Val table */ + address = (hjpeg->Instance->DHTMEM + 55); + value = *address & 0x0000FFFFUL; + value = value | (((uint32_t)HuffTableDC1->HuffVal[1] & 0xFFUL) << 24) | + (((uint32_t)HuffTableDC1->HuffVal[0] & 0xFFUL) << 16); + *address = value; + + /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 58) belong to DC1 Val table */ + address = (hjpeg->Instance->DHTMEM + 58); + value = *address & 0xFFFF0000UL; + value = value | (((uint32_t)HuffTableDC1->HuffVal[11] & 0xFFUL) << 8) | + ((uint32_t)HuffTableDC1->HuffVal[10] & 0xFFUL); + *address = value; + + /*continue setting 8 DC1 huffman val from DHTMEM + 57 down to DHTMEM + 56*/ + address--; + index = 8; + while (index > 3UL) + { + *address = (((uint32_t)HuffTableDC1->HuffVal[index + 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableDC1->HuffVal[index] & 0xFFUL) << 16) | + (((uint32_t)HuffTableDC1->HuffVal[index - 1UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableDC1->HuffVal[index - 2UL] & 0xFFUL); + address--; + index -= 4UL; + } + + /* AC1 Huffman Table : BITS*/ + /* AC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 58 to DHTMEM + 62*/ + /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 58) belong to AC1 Bits table */ + address = (hjpeg->Instance->DHTMEM + 58); + value = *address & 0x0000FFFFU; + value = value | (((uint32_t)HuffTableAC1->Bits[1] & 0xFFUL) << 24) | + (((uint32_t)HuffTableAC1->Bits[0] & 0xFFUL) << 16); + *address = value; + + /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 62) belong to Bits Val table */ + address = (hjpeg->Instance->DHTMEM + 62); + value = *address & 0xFFFF0000U; + value = value | (((uint32_t)HuffTableAC1->Bits[15] & 0xFFUL) << 8) | ((uint32_t)HuffTableAC1->Bits[14] & 0xFFUL); + *address = value; + + /*continue setting 12 AC1 huffman Bits from DHTMEM + 61 down to DHTMEM + 59*/ + address--; + index = 12; + while (index > 3UL) + { + + *address = (((uint32_t)HuffTableAC1->Bits[index + 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableAC1->Bits[index] & 0xFFUL) << 16) | + (((uint32_t)HuffTableAC1->Bits[index - 1UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableAC1->Bits[index - 2UL] & 0xFFUL); + address--; + index -= 4UL; + + } + /* AC1 Huffman Table : Val*/ + /* AC1 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 62 to DHTMEM + 102 */ + /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 62) belong to AC1 VALS table */ + address = (hjpeg->Instance->DHTMEM + 62); + value = *address & 0x0000FFFFUL; + value = value | (((uint32_t)HuffTableAC1->HuffVal[1] & 0xFFUL) << 24) | + (((uint32_t)HuffTableAC1->HuffVal[0] & 0xFFUL) << 16); + *address = value; + + /*continue setting 160 AC1 huffman values from DHTMEM + 63 to DHTMEM+102 */ + address = (hjpeg->Instance->DHTMEM + 102); + index = JPEG_AC_HUFF_TABLE_SIZE - 2UL; + while (index > 3UL) + { + *address = (((uint32_t)HuffTableAC1->HuffVal[index + 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableAC1->HuffVal[index] & 0xFFUL) << 16) | + (((uint32_t)HuffTableAC1->HuffVal[index - 1UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableAC1->HuffVal[index - 2UL] & 0xFFUL); + address--; + index -= 4UL; + } + +} + +/** + * @brief Configure the JPEG registers with a given quantization table + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param QTable pointer to an array of 64 bytes giving the quantization table + * @param QTableAddress destination quantization address in the JPEG peripheral + * it could be QMEM0, QMEM1, QMEM2 or QMEM3 + * @retval 0 if no error, 1 if error + */ +static uint32_t JPEG_Set_Quantization_Mem(const JPEG_HandleTypeDef *hjpeg, const uint8_t *QTable, + __IO uint32_t *QTableAddress) +{ + uint32_t i; + uint32_t j; + uint32_t quantRow; + uint32_t quantVal; + uint32_t ScaleFactor; + __IO uint32_t *tableAddress; + + tableAddress = QTableAddress; + + if ((hjpeg->Conf.ImageQuality >= 50UL) && (hjpeg->Conf.ImageQuality <= 100UL)) + { + ScaleFactor = JPEG_HIGH_QUALITY_REFERENCE - (hjpeg->Conf.ImageQuality * 2UL); + } + else if (hjpeg->Conf.ImageQuality > 0UL) + { + ScaleFactor = JPEG_LOW_QUALITY_REFERENCE / ((uint32_t) hjpeg->Conf.ImageQuality); + } + else + { + return 1UL; + } + + /*Quantization_table = (Standard_quanization_table * ScaleFactor + 50) / 100*/ + i = 0; + while (i < (JPEG_QUANT_TABLE_SIZE - 3UL)) + { + quantRow = 0; + for (j = 0; j < 4UL; j++) + { + /* Note that the quantization coefficients must be specified in the table in zigzag order */ + quantVal = ((((uint32_t) QTable[JPEG_ZIGZAG_ORDER[i + j]]) * ScaleFactor) + 50UL) / 100UL; + + if (quantVal == 0UL) + { + quantVal = 1UL; + } + else if (quantVal > 255UL) + { + quantVal = JPEG_QUANTVAL_MAX; + } + else + { + /* Nothing to do, keep same value of quantVal */ + } + + quantRow |= ((quantVal & 0xFFUL) << (8UL * j)); + } + + i += 4UL; + *tableAddress = quantRow; + tableAddress ++; + } + + /* Return function status */ + return 0UL; +} + +/** + * @brief Configure the JPEG registers for YCbCr color space + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t ySamplingH; + uint32_t ySamplingV; + uint32_t yblockNb; + + /*Set Number of color components to 3*/ + hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_NF; + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_NF_1; + + /* compute MCU block size and Y, Cb ,Cr sampling factors*/ + if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) + { + ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ + ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/ + + yblockNb = 0x30; /* 4 blocks of 8x8*/ + } + else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) + { + ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ + ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ + + yblockNb = 0x10; /* 2 blocks of 8x8*/ + } + else /*JPEG_444_SUBSAMPLING and default*/ + { + ySamplingH = JPEG_CONFR4_HSF_0; /* Hs = 1*/ + ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ + + yblockNb = 0; /* 1 block of 8x8*/ + } + + hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS); + hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF_1 | JPEG_CONFR1_NS_1); + + /*Reset CONFR4 register*/ + hjpeg->Instance->CONFR4 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks, + Quantization table and Huffman AC/DC tables for component 0*/ + hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB)); + + /*Reset CONFR5 register*/ + hjpeg->Instance->CONFR5 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks, + Quantization table and Huffman AC/DC tables for component 1*/ + hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0 | JPEG_CONFR5_QT_0 | JPEG_CONFR5_HA | + JPEG_CONFR5_HD); + + /*Reset CONFR6 register*/ + hjpeg->Instance->CONFR6 = 0; + /*Set Horizental and Vertical sampling factor and number of blocks for component 2*/ + /* In YCBCR , by default, both chrominance components (component 1 and component 2) + use the same Quantization table (table 1) */ + /* In YCBCR , both chrominance components (component 1 and component 2) use the same Huffman tables (table 1) */ + hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0 | JPEG_CONFR6_QT_0 | JPEG_CONFR6_HA | + JPEG_CONFR6_HD); + +} + +/** + * @brief Configure the JPEG registers for GrayScale color space + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg) +{ + /*Set Number of color components to 1*/ + hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS); + + /*in GrayScale use 1 single Quantization table (Table 0)*/ + /*in GrayScale use only one couple of AC/DC huffman table (table 0)*/ + + /*Reset CONFR4 register*/ + hjpeg->Instance->CONFR4 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks, + Quantization table and Huffman AC/DC tables for component 0*/ + hjpeg->Instance->CONFR4 |= JPEG_CONFR4_HSF_0 | JPEG_CONFR4_VSF_0 ; +} + +/** + * @brief Configure the JPEG registers for CMYK color space + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t ySamplingH; + uint32_t ySamplingV; + uint32_t yblockNb; + + /*Set Number of color components to 4*/ + hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF | JPEG_CONFR1_NS); + + /* compute MCU block size and Y, Cb ,Cr sampling factors*/ + if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) + { + ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ + ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/ + + yblockNb = 0x30; /* 4 blocks of 8x8*/ + } + else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) + { + ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ + ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ + + yblockNb = 0x10; /* 2 blocks of 8x8*/ + } + else /*JPEG_444_SUBSAMPLING and default*/ + { + ySamplingH = JPEG_CONFR4_HSF_0; /* Hs = 1*/ + ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ + + yblockNb = 0; /* 1 block of 8x8*/ + } + + /*Reset CONFR4 register*/ + hjpeg->Instance->CONFR4 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks, + Quantization table and Huffman AC/DC tables for component 0*/ + hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB)); + + /*Reset CONFR5 register*/ + hjpeg->Instance->CONFR5 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks, + Quantization table and Huffman AC/DC tables for component 1*/ + hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0); + + /*Reset CONFR6 register*/ + hjpeg->Instance->CONFR6 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks, + Quantization table and Huffman AC/DC tables for component 2*/ + hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0); + + /*Reset CONFR7 register*/ + hjpeg->Instance->CONFR7 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks, + Quantization table and Huffman AC/DC tables for component 3*/ + hjpeg->Instance->CONFR7 |= (JPEG_CONFR7_HSF_0 | JPEG_CONFR7_VSF_0); +} + +/** + * @brief Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg) +{ + /*Reset pause*/ + hjpeg->Context &= (~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT)); + + if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) + { + /*Set JPEG Codec to Decoding mode */ + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_DE; + } + else /* JPEG_CONTEXT_ENCODE */ + { + /*Set JPEG Codec to Encoding mode */ + hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_DE; + } + + /*Stop JPEG processing */ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + /* Disable All Interrupts */ + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + + /* Disable All DMA requests */ + JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK); + /* Flush input and output FIFOs*/ + hjpeg->Instance->CR |= JPEG_CR_IFF; + hjpeg->Instance->CR |= JPEG_CR_OFF; + + /* Clear all flags */ + __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL); + + /*Start Encoding/Decoding*/ + hjpeg->Instance->CONFR0 |= JPEG_CONFR0_START; + + if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) + { + /*Enable IN/OUT, end of Conversation, and end of header parsing interruptions*/ + __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_IFT | JPEG_IT_IFNF | JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC | JPEG_IT_HPD); + } + else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) + { + /*Enable End Of Conversation, and End Of Header parsing interruptions*/ + __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD); + + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief JPEG encoding/decoding process in case of Polling or Interrupt + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG_PROCESS_DONE if the process has ends else JPEG_PROCESS_ONGOING + */ +static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t tmpContext; + + /*End of header processing flag */ + if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) + { + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL) + { + /*Call Header parsing complete callback */ + (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf); + /* Reset the ImageQuality */ + hjpeg->Conf.ImageQuality = 0; + /* Note : the image quality is only available at the end of the decoding operation */ + /* at the current stage the calculated image quality is not correct so reset it */ + + /*Call Info Ready callback */ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->InfoReadyCallback(hjpeg, &hjpeg->Conf); +#else + HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_IT_HPD); + + /* Clear header processing done flag */ + __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_HPDF); + } + } + + /*Input FIFO status handling*/ + if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) + { + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != 0UL) + { + /*Input FIFO threshold flag */ + /*JPEG_FIFO_TH_SIZE words can be written in */ + JPEG_ReadInputData(hjpeg, JPEG_FIFO_TH_SIZE); + } + else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != 0UL) + { + /*Input FIFO Not Full flag */ + /*32-bit value can be written in */ + JPEG_ReadInputData(hjpeg, 1); + } + else + { + /* Nothing to do */ + } + } + + + /*Output FIFO flag handling*/ + if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL) + { + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != 0UL) + { + /*Output FIFO threshold flag */ + /*JPEG_FIFO_TH_SIZE words can be read out */ + JPEG_StoreOutputData(hjpeg, JPEG_FIFO_TH_SIZE); + } + else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL) + { + /*Output FIFO Not Empty flag */ + /*32-bit value can be read out */ + JPEG_StoreOutputData(hjpeg, 1); + } + else + { + /* Nothing to do */ + } + } + + /*End of Conversion handling :i.e EOC flag is high and OFTF low and OFNEF low*/ + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF | JPEG_FLAG_OFTF | JPEG_FLAG_OFNEF) == JPEG_FLAG_EOCF) + { + /*Stop Encoding/Decoding*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) + { + /* Disable All Interrupts */ + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + } + + /* Clear all flags */ + __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL); + + /*Call End of conversion callback */ + if (hjpeg->JpegOutCount > 0UL) + { + /*Output Buffer is not empty, call DecodedDataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + hjpeg->JpegOutCount = 0; + } + + /*Reset Context Operation*/ + tmpContext = hjpeg->Context; + /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ + hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /*Call End of Encoding/Decoding callback */ + if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) + { +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DecodeCpltCallback(hjpeg); +#else + HAL_JPEG_DecodeCpltCallback(hjpeg); +#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/ + } + else /* JPEG_CONTEXT_ENCODE */ + { +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->EncodeCpltCallback(hjpeg); +#else + HAL_JPEG_EncodeCpltCallback(hjpeg); +#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/ + } + + return JPEG_PROCESS_DONE; + } + + + return JPEG_PROCESS_ONGOING; +} + +/** + * @brief Store some output data from the JPEG peripheral to the output buffer. + * This function is used when the JPEG peripheral has new data to output + * in case of Polling or Interrupt process + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param nbOutputWords Number of output words (of 32 bits) ready from the JPEG peripheral + * @retval None + */ +static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords) +{ + uint32_t index; + uint32_t nb_words; + uint32_t nb_bytes; + uint32_t dataword; + + if (hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords * 4UL))) + { + for (index = 0; index < nbOutputWords; index++) + { + /*Transfer 32 bits from the JPEG output FIFO*/ + dataword = hjpeg->Instance->DOR; + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataword & 0x000000FFUL); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataword & 0x0000FF00UL) >> 8); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataword & 0x00FF0000UL) >> 16); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataword & 0xFF000000UL) >> 24); + hjpeg->JpegOutCount += 4UL; + } + if (hjpeg->OutDataLength == hjpeg->JpegOutCount) + { + /*Output Buffer is full, call DecodedDataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/ + hjpeg->JpegOutCount = 0; + } + } + else if (hjpeg->OutDataLength > hjpeg->JpegOutCount) + { + nb_words = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL; + for (index = 0; index < nb_words; index++) + { + /*Transfer 32 bits from the JPEG output FIFO*/ + dataword = hjpeg->Instance->DOR; + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataword & 0x000000FFUL); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataword & 0x0000FF00UL) >> 8); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataword & 0x00FF0000UL) >> 16); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataword & 0xFF000000UL) >> 24); + hjpeg->JpegOutCount += 4UL; + } + if (hjpeg->OutDataLength == hjpeg->JpegOutCount) + { + /*Output Buffer is full, call DecodedDataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + hjpeg->JpegOutCount = 0; + } + else + { + nb_bytes = hjpeg->OutDataLength - hjpeg->JpegOutCount; + dataword = hjpeg->Instance->DOR; + for (index = 0; index < nb_bytes; index++) + { + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * (index & 0x3UL))) & 0xFFUL); + hjpeg->JpegOutCount++; + } + /*Output Buffer is full, call DecodedDataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + hjpeg->JpegOutCount = 0; + + nb_bytes = 4UL - nb_bytes; + for (index = nb_bytes; index < 4UL; index++) + { + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * index)) & 0xFFUL); + hjpeg->JpegOutCount++; + } + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief Read some input Data from the input buffer. + * This function is used when the JPEG peripheral needs new data + * in case of Polling or Interrupt process + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param nbRequestWords Number of input words (of 32 bits) that the JPE peripheral request + * @retval None + */ +static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords) +{ + uint32_t nb_bytes = 0; + uint32_t nb_words; + uint32_t index; + uint32_t dataword; + uint32_t input_count; + + if ((hjpeg->InDataLength == 0UL) || (nbRequestWords == 0UL)) + { + /* No more Input data : nothing to do*/ + (void) HAL_JPEG_Pause(hjpeg, JPEG_PAUSE_RESUME_INPUT); + } + else if (hjpeg->InDataLength > hjpeg->JpegInCount) + { + nb_bytes = hjpeg->InDataLength - hjpeg->JpegInCount; + } + else if (hjpeg->InDataLength == hjpeg->JpegInCount) + { + /*Call HAL_JPEG_GetDataCallback to get new data */ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->GetDataCallback(hjpeg, hjpeg->JpegInCount); +#else + HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount); +#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/ + + if (hjpeg->InDataLength > 4UL) + { + hjpeg->InDataLength = ((hjpeg->InDataLength + 3UL) / 4UL) * 4UL; + } + hjpeg->JpegInCount = 0; + nb_bytes = hjpeg->InDataLength; + } + else + { + /* Nothing to do */ + } + if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nb_bytes > 0UL)) + { + nb_words = nb_bytes / 4UL; + if (nb_words >= nbRequestWords) + { + for (index = 0; index < nbRequestWords; index++) + { + input_count = hjpeg->JpegInCount; + hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24)); + + hjpeg->JpegInCount += 4UL; + } + } + else /*nb_words < nbRequestWords*/ + { + if (nb_words > 0UL) + { + for (index = 0; index < nb_words; index++) + { + input_count = hjpeg->JpegInCount; + hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24)); + + hjpeg->JpegInCount += 4UL; + } + } + else + { + /* end of file*/ + dataword = 0; + for (index = 0; index < nb_bytes; index++) + { + dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL)); + hjpeg->JpegInCount++; + } + hjpeg->Instance->DIR = dataword; + } + } + } +} + +/** + * @brief Start the JPEG DMA process (encoding/decoding) + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING + */ +static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg) +{ + if ((hjpeg->InDataLength < 4UL) || (hjpeg->OutDataLength < 4UL)) + { + return HAL_ERROR; + } + /* Reset Ending DMA internal context flag*/ + hjpeg->Context &= ~JPEG_CONTEXT_ENDING_DMA; + + /* Disable DMA In/Out Request*/ + JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_ODMA | JPEG_DMA_IDMA); + + /* Set the JPEG DMA In transfer complete callback */ + hjpeg->hdmain->XferCpltCallback = JPEG_DMAInCpltCallback; + /* Set the DMA In error callback */ + hjpeg->hdmain->XferErrorCallback = JPEG_DMAErrorCallback; + + /* Set the JPEG DMA Out transfer complete callback */ + hjpeg->hdmaout->XferCpltCallback = JPEG_DMAOutCpltCallback; + /* Set the DMA Out error callback */ + hjpeg->hdmaout->XferErrorCallback = JPEG_DMAErrorCallback; + /* Set the DMA Out Abort callback */ + hjpeg->hdmaout->XferAbortCallback = JPEG_DMAOutAbortCallback; + + /*DMA transfer size must be a multiple of 4 bytes i.e multiple of 32bits words*/ + hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL); + + /*DMA transfer size must be a multiple of 4 bytes i.e multiple of 32bits words*/ + hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % 4UL); + + if ((hjpeg->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hjpeg->hdmain->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hjpeg->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hjpeg->InDataLength; + + /* Set DMA source address */ + hjpeg->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hjpeg->pJpegInBuffPtr; + + /* Set DMA destination address */ + hjpeg->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hjpeg->Instance->DIR; + + if (HAL_DMAEx_List_Start_IT(hjpeg->hdmain) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { + /* Set the JPEG State to ready */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /* Update JPEG error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_ERROR; + } + } + else + { + /* Start DMA FIFO In transfer */ + if (HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, + hjpeg->InDataLength) != HAL_OK) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + return HAL_ERROR; + } + } + + if ((hjpeg->hdmaout->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hjpeg->hdmaout->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hjpeg->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hjpeg->OutDataLength; + + /* Set DMA source address */ + hjpeg->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hjpeg->Instance->DOR; + + /* Set DMA destination address */ + hjpeg->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hjpeg->pJpegOutBuffPtr; + + if (HAL_DMAEx_List_Start_IT(hjpeg->hdmaout) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { + /* Set the JPEG State to ready */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /* Update JPEG error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_ERROR; + } + } + else + { + /* Start DMA FIFO Out transfer */ + if (HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, + hjpeg->OutDataLength) != HAL_OK) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + return HAL_ERROR; + } + } + + /* Enable JPEG In/Out DMA requests*/ + JPEG_ENABLE_DMA(hjpeg, JPEG_DMA_IDMA | JPEG_DMA_ODMA); + + return HAL_OK; +} + +/** + * @brief Continue the current JPEG DMA process (encoding/decoding) + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING + */ +static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg) +{ + /*End of header processing flag rises*/ + if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) + { + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL) + { + /*Call Header parsing complete callback */ + (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf); + + /* Reset the ImageQuality */ + hjpeg->Conf.ImageQuality = 0; + /* Note : the image quality is only available at the end of the decoding operation */ + /* at the current stage the calculated image quality is not correct so reset it */ + + /*Call Info Ready callback */ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->InfoReadyCallback(hjpeg, &hjpeg->Conf); +#else + HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_IT_HPD); + + /* Clear header processing done flag */ + __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_HPDF); + } + } + + /*End of Conversion handling*/ + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) != 0UL) + { + /*Disabkle JPEG In/Out DMA Requests*/ + JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_ODMA | JPEG_DMA_IDMA); + + hjpeg->Context |= JPEG_CONTEXT_ENDING_DMA; + + /*Stop Encoding/Decoding*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + + /* Clear all flags */ + __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL); + + if (hjpeg->hdmain->State == HAL_DMA_STATE_BUSY) + { + /* Stop the DMA In Xfer*/ + (void) HAL_DMA_Abort(hjpeg->hdmain); + } + + if (hjpeg->hdmaout->State == HAL_DMA_STATE_BUSY) + { + /* Stop the DMA out Xfer*/ + (void) HAL_DMA_Abort(hjpeg->hdmaout); + } + + JPEG_DMA_EndProcess(hjpeg); + } + + +} + +/** + * @brief Finalize the current JPEG DMA process (encoding/decoding) + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG_PROCESS_DONE + */ +static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t tmpContext; + hjpeg->JpegOutCount = hjpeg->OutDataLength - JPEG_GET_DMA_REMAIN_DATA(hjpeg->hdmaout); + + /*if Output Buffer is full, call HAL_JPEG_DataReadyCallback*/ + if (hjpeg->JpegOutCount == hjpeg->OutDataLength) + { +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + hjpeg->JpegOutCount = 0; + } + + /*Check if remaining data in the output FIFO*/ + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0UL) + { + if (hjpeg->JpegOutCount > 0UL) + { + /*Output Buffer is not empty, call DecodedDataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + hjpeg->JpegOutCount = 0; + } + + /*Stop Encoding/Decoding*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + tmpContext = hjpeg->Context; + /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ + hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /*Call End of Encoding/Decoding callback */ + if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) + { +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DecodeCpltCallback(hjpeg); +#else + HAL_JPEG_DecodeCpltCallback(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + } + else /* JPEG_CONTEXT_ENCODE */ + { +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->EncodeCpltCallback(hjpeg); +#else + HAL_JPEG_EncodeCpltCallback(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + } + } + else if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL) + { + JPEG_DMA_PollResidualData(hjpeg); + } + else + { + /* Nothing to do */ + } + +} + +/** + * @brief Poll residual output data when DMA process (encoding/decoding) + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None. + */ +static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t tmpContext; + uint32_t count; + uint32_t dataOut; + + for (count = JPEG_FIFO_SIZE; count > 0UL; count--) + { + if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL) + { + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL) + { + dataOut = hjpeg->Instance->DOR; + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataOut & 0x000000FFUL); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataOut & 0x0000FF00UL) >> 8); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataOut & 0x00FF0000UL) >> 16); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataOut & 0xFF000000UL) >> 24); + hjpeg->JpegOutCount += 4UL; + + if (hjpeg->JpegOutCount == hjpeg->OutDataLength) + { + /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + hjpeg->JpegOutCount = 0; + } + + } + } + } + + tmpContext = hjpeg->Context; + + if ((__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0UL) || ((tmpContext & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL)) + { + /*Stop Encoding/Decoding*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + if (hjpeg->JpegOutCount > 0UL) + { + /*Output Buffer is not empty, call DecodedDataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + hjpeg->JpegOutCount = 0; + } + + tmpContext = hjpeg->Context; + /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ + hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /*Call End of Encoding/Decoding callback */ + if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) + { +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DecodeCpltCallback(hjpeg); +#else + HAL_JPEG_DecodeCpltCallback(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + } + else /* JPEG_CONTEXT_ENCODE */ + { +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->EncodeCpltCallback(hjpeg); +#else + HAL_JPEG_EncodeCpltCallback(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief DMA input transfer complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure. + * @retval None + */ +static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma) +{ + JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable The JPEG IT so the DMA Input Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */ + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + + if ((hjpeg->Context & (JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA)) == + JPEG_CONTEXT_DMA) /* Check if context method is DMA and we are not in ending DMA stage */ + { + JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_IDMA); + + hjpeg->JpegInCount = hjpeg->InDataLength - JPEG_GET_DMA_REMAIN_DATA(hdma); + + /*Call HAL_JPEG_GetDataCallback to get new data */ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->GetDataCallback(hjpeg, hjpeg->JpegInCount); +#else + HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + if (hjpeg->InDataLength >= 4UL) + { + /*JPEG Input DMA transfer data number must be multiple of 32 bits word + as the destination is a 32 bits (4 bytes) register */ + hjpeg->InDataLength = ((hjpeg->InDataLength + 3UL) / 4UL) * 4UL; + } + else + { + /* Nothing to do */ + } + + if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (hjpeg->InDataLength > 0UL)) + { + /* Start DMA FIFO In transfer */ + if (HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, + hjpeg->InDataLength) != HAL_OK) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + hjpeg->State = HAL_JPEG_STATE_ERROR; +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->ErrorCallback(hjpeg); +#else + HAL_JPEG_ErrorCallback(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + return; + } + JPEG_ENABLE_DMA(hjpeg, JPEG_DMA_IDMA); + } + + /* JPEG Conversion still on going : Enable the JPEG IT */ + __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD); + } +} + +/** + * @brief DMA output transfer complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure. + * @retval None + */ +static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma) +{ + JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable The JPEG IT so the DMA Output Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */ + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + + if ((hjpeg->Context & (JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA)) == + JPEG_CONTEXT_DMA) /* Check if context method is DMA and we are not in ending DMA stage */ + { + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) == 0UL) + { + JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_ODMA); + hjpeg->JpegOutCount = hjpeg->OutDataLength - JPEG_GET_DMA_REMAIN_DATA(hdma); + + /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL) + { + /* Start DMA FIFO Out transfer */ + if (HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, + hjpeg->OutDataLength) != HAL_OK) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + hjpeg->State = HAL_JPEG_STATE_ERROR; +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->ErrorCallback(hjpeg); +#else + HAL_JPEG_ErrorCallback(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + return; + } + JPEG_ENABLE_DMA(hjpeg, JPEG_DMA_ODMA); + } + } + + /* JPEG Conversion still on going : Enable the JPEG IT */ + __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD); + } +} + + +/** + * @brief DMA Transfer error callback + * @param hdma pointer to a DMA_HandleTypeDef structure. + * @retval None + */ +static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma) +{ + JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_NONE) + { + /*Stop Encoding/Decoding*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + /* Disable All Interrupts */ + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + + /* Disable All DMA requests */ + JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK); + + hjpeg->State = HAL_JPEG_STATE_READY; + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->ErrorCallback(hjpeg); +#else + HAL_JPEG_ErrorCallback(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA output Abort callback + * @param hdma pointer to a DMA_HandleTypeDef structure. + * @retval None + */ +static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) +{ + JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0UL) + { + JPEG_DMA_EndProcess(hjpeg); + } +} + + +/** + * @brief Calculate the decoded image quality (from 1 to 100) + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG image quality from 1 to 100. + */ +static uint32_t JPEG_GetQuality(const JPEG_HandleTypeDef *hjpeg) +{ + uint32_t quality = 0; + uint32_t quantRow; + uint32_t quantVal; + uint32_t scale; + uint32_t i; + uint32_t j; + const __IO uint32_t *tableAddress = hjpeg->Instance->QMEM0; + + i = 0; + while (i < (JPEG_QUANT_TABLE_SIZE - 3UL)) + { + quantRow = *tableAddress; + for (j = 0; j < 4UL; j++) + { + quantVal = (quantRow >> (8UL * j)) & 0xFFUL; + if (quantVal == 1UL) + { + /* if Quantization value = 1 then quality is 100%*/ + quality += 100UL; + } + else + { + /* Note that the quantization coefficients must be specified in the table in zigzag order */ + scale = (quantVal * 100UL) / ((uint32_t) hjpeg->QuantTable0[JPEG_ZIGZAG_ORDER[i + j]]); + + if (scale <= 100UL) + { + quality += (200UL - scale) / 2UL; + } + else + { + quality += 5000UL / scale; + } + } + } + + i += 4UL; + tableAddress ++; + } + + return (quality / 64UL); +} +/** + * @} + */ + +/** + * @} + */ +#endif /* JPEG */ +#endif /* HAL_JPEG_MODULE_ENABLED */ + + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_lptim.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_lptim.c new file mode 100644 index 00000000000..7b219e2beed --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_lptim.c @@ -0,0 +1,3777 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_lptim.c + * @author MCD Application Team + * @brief LPTIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Low Power Timer (LPTIM) peripheral: + * + Initialization and de-initialization functions. + * + Start/Stop operation functions in polling mode. + * + Start/Stop operation functions in interrupt mode. + * + Reading operation functions. + * + Peripheral State functions. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LPTIM HAL driver can be used as follows: + + (#)Initialize the LPTIM low level resources by implementing the + HAL_LPTIM_MspInit(): + (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE(). + (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()): + (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority(). + (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ(). + (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler(). + + (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function + configures mainly: + (++) The instance: LPTIM1, LPTIM2, LPTIM3, LPTIM4 or LPTIM5. + (++) Clock: the counter clock. + (+++) Source : it can be either the ULPTIM input (IN1) or one of + the internal clock; (APB, LSE or LSI). + (+++) Prescaler: select the clock divider. + (++) UltraLowPowerClock : To be used only if the ULPTIM is selected + as counter clock source. + (+++) Polarity: polarity of the active edge for the counter unit + if the ULPTIM input is selected. + (+++) SampleTime: clock sampling time to configure the clock glitch + filter. + (++) Trigger: How the counter start. + (+++) Source: trigger can be software or one of the hardware triggers. + (+++) ActiveEdge : only for hardware trigger. + (+++) SampleTime : trigger sampling time to configure the trigger + glitch filter. + (++) OutputPolarity : 2 opposite polarities are possible. + (++) UpdateMode: specifies whether the update of the autoreload and + the compare values is done immediately or after the end of current + period. + (++) Input1Source: Source selected for input1 (GPIO or comparator output). + (++) Input2Source: Source selected for input2 (GPIO or comparator output). + Input2 is used only for encoder feature so is used only for LPTIM1 instance. + + (#)Six modes are available: + + (++) PWM Mode: To generate a PWM signal with specified period and pulse, + call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption + mode. + + (++) One Pulse Mode: To generate pulse with specified width in response + to a stimulus, call HAL_LPTIM_OnePulse_Start() or + HAL_LPTIM_OnePulse_Start_IT() for interruption mode. + + (++) Set once Mode: In this mode, the output changes the level (from + low level to high level if the output polarity is configured high, else + the opposite) when a compare match occurs. To start this mode, call + HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for + interruption mode. + + (++) Encoder Mode: To use the encoder interface call + HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for + interruption mode. Only available for LPTIM1 instance. + + (++) Time out Mode: an active edge on one selected trigger input rests + the counter. The first trigger event will start the timer, any + successive trigger event will reset the counter and the timer will + restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or + HAL_LPTIM_TimeOut_Start_IT() for interruption mode. + + (++) Counter Mode: counter can be used to count external events on + the LPTIM Input1 or it can be used to count internal clock cycles. + To start this mode, call HAL_LPTIM_Counter_Start() or + HAL_LPTIM_Counter_Start_IT() for interruption mode. + + + (#) User can stop any process by calling the corresponding API: + HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is + already started in interruption mode. + + (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit(). + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + [..] + Use Function HAL_LPTIM_RegisterCallback() to register a callback. + HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + [..] + Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the + default weak function. + HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + [..] + These functions allow to register/unregister following callbacks: + + (+) MspInitCallback : LPTIM Base Msp Init Callback. + (+) MspDeInitCallback : LPTIM Base Msp DeInit Callback. + (+) CompareMatchCallback : Compare match Callback. + (+) AutoReloadMatchCallback : Auto-reload match Callback. + (+) TriggerCallback : External trigger event detection Callback. + (+) CompareWriteCallback : Compare register write complete Callback. + (+) AutoReloadWriteCallback : Auto-reload register write complete Callback. + (+) DirectionUpCallback : Up-counting direction change Callback. + (+) DirectionDownCallback : Down-counting direction change Callback. + (+) UpdateEventCallback : Update event detection Callback. + (+) RepCounterWriteCallback : Repetition counter register write complete Callback. + + [..] + By default, after the Init and when the state is HAL_LPTIM_STATE_RESET + all interrupt callbacks are set to the corresponding weak functions: + examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init/DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + [..] + Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup LPTIM LPTIM + * @brief LPTIM HAL module driver. + * @{ + */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + +#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup LPTIM_Private_Constants + * @{ + */ +#define TIMEOUT 1000UL /* Timeout is 1s */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @addtogroup LPTIM_Private_Macros + * @{ + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) \ + (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() :\ + ((__INSTANCE__) == LPTIM2) ? __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() :\ + ((__INSTANCE__) == LPTIM3) ? __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT() :\ + ((__INSTANCE__) == LPTIM4) ? __HAL_LPTIM_LPTIM4_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM5_EXTI_ENABLE_IT()) + +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) \ + (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() :\ + ((__INSTANCE__) == LPTIM2) ? __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() :\ + ((__INSTANCE__) == LPTIM3) ? __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT() :\ + ((__INSTANCE__) == LPTIM4) ? __HAL_LPTIM_LPTIM4_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM5_EXTI_DISABLE_IT()) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig); +static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig); +static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig); +static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag); +void LPTIM_DMAError(DMA_HandleTypeDef *hdma); +void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma); +void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst, + uint32_t length); + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions + * @{ + */ + +/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the LPTIM according to the specified parameters in the + LPTIM_InitTypeDef and initialize the associated handle. + (+) DeInitialize the LPTIM peripheral. + (+) Initialize the LPTIM MSP. + (+) DeInitialize the LPTIM MSP. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the LPTIM according to the specified parameters in the + * LPTIM_InitTypeDef and initialize the associated handle. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) +{ + uint32_t tmpcfgr; + + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(hlptim->Init.Period)); + + assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); + assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + { + assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); + assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); + } + assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) + { + assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); + assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); + } + assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); + assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); + assert_param(IS_LPTIM_REPETITION(hlptim->Init.RepetitionCounter)); + + if (hlptim->State == HAL_LPTIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hlptim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + LPTIM_ResetCallback(hlptim); + + if (hlptim->MspInitCallback == NULL) + { + hlptim->MspInitCallback = HAL_LPTIM_MspInit; + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + hlptim->MspInitCallback(hlptim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_LPTIM_MspInit(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK); + + /* Set the repetition counter */ + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + + /* Wait for the completion of the write operation to the LPTIM_RCR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_REPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Set LPTIM Period */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, hlptim->Init.Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Get the LPTIMx CFGR value */ + tmpcfgr = hlptim->Instance->CFGR; + + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + { + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); + } + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) + { + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); + } + + /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | + LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE)); + + /* Set initialization parameters */ + tmpcfgr |= (hlptim->Init.Clock.Source | + hlptim->Init.Clock.Prescaler | + hlptim->Init.UpdateMode | + hlptim->Init.CounterSource); + + /* Glitch filters for internal triggers and external inputs are configured + * only if an internal clock source is provided to the LPTIM + */ + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) + { + tmpcfgr |= (hlptim->Init.Trigger.SampleTime | + hlptim->Init.UltraLowPowerClock.SampleTime); + } + + /* Configure LPTIM external clock polarity and digital filter */ + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + { + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + hlptim->Init.UltraLowPowerClock.SampleTime); + } + + /* Configure LPTIM external trigger */ + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Enable External trigger and set the trigger source */ + tmpcfgr |= (hlptim->Init.Trigger.Source | + hlptim->Init.Trigger.ActiveEdge | + hlptim->Init.Trigger.SampleTime); + } + + /* Write to LPTIMx CFGR */ + hlptim->Instance->CFGR = tmpcfgr; + + /* Configure LPTIM input sources */ + if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2)) + { + /* Check LPTIM Input1 and Input2 sources */ + assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); + assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source)); + + /* Configure LPTIM Input1 and Input2 sources */ + hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source); + } + else + { + if (hlptim->Instance == LPTIM3) + { + /* Check LPTIM3 Input1 source */ + assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); + + /* Configure LPTIM3 Input1 source */ + hlptim->Instance->CFGR2 = hlptim->Init.Input1Source; + } + } + + /* Initialize the LPTIM channels state */ + LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the LPTIM peripheral. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + { + return HAL_ERROR; + } + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + __HAL_LPTIM_ENABLE(hlptim); + if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) + { + hlptim->Instance->CCMR1 = 0; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK); + + __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, 0); + /* Wait for the completion of the write operation to the LPTIM_CCR1 register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) + { + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK); + + __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, 0); + /* Wait for the completion of the write operation to the LPTIM_CCR2 register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + __HAL_LPTIM_AUTORELOAD_SET(hlptim, 0); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the LPTIM Peripheral Clock */ + __HAL_LPTIM_DISABLE(hlptim); + + hlptim->Instance->CFGR = 0; + hlptim->Instance->CFGR2 = 0; + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + if (hlptim->MspDeInitCallback == NULL) + { + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hlptim->MspDeInitCallback(hlptim); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_LPTIM_MspDeInit(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + + /* Change the LPTIM channels state */ + LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_RESET); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hlptim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the LPTIM MSP. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize LPTIM MSP. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions + * @brief Start-Stop operation functions. + * +@verbatim + ============================================================================== + ##### LPTIM Start Stop operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start the PWM mode. + (+) Stop the PWM mode. + (+) Start the One pulse mode. + (+) Stop the One pulse mode. + (+) Start the Set once mode. + (+) Stop the Set once mode. + (+) Start the Encoder mode. + (+) Stop the Encoder mode. + (+) Start the Timeout mode. + (+) Stop the Timeout mode. + (+) Start the Counter mode. + (+) Stop the Counter mode. + + +@endverbatim + * @{ + */ + +/** + * @brief Start the LPTIM PWM generation. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Reset WAVE bit to set PWM mode */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Enable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the LPTIM PWM generation. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable LPTIM signal from the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the LPTIM PWM generation in interrupt mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Reset WAVE bit to set PWM mode */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Enable interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + case LPTIM_CHANNEL_2: + /* Enable interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* If external trigger source is used, then enable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Enable external trigger interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the LPTIM PWM generation in interrupt mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable LPTIM signal from the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Disable interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + case LPTIM_CHANNEL_2: + /* Disable interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* If external trigger source is used, then enable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Enable external trigger interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the LPTIM PWM generation in DMA mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @param pData The destination Buffer address + * @param Length The length of data to be transferred from LPTIM peripheral to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, const uint32_t *pData, + uint32_t Length) +{ + DMA_HandleTypeDef *hdma; + + /* Check the parameters */ + assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Reset WAVE bit to set PWM mode */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Enable update event DMA request */ + __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_UPDATE); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Set the DMA update event callbacks */ + hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMAUpdateEventCplt; + hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt; + + /* Set the DMA error callback */ + hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError; + + /* Enable the DMA Channel */ + hdma = hlptim->hdma[LPTIM_DMA_ID_CC1]; + if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + case LPTIM_CHANNEL_2: + /* Set the DMA update event callbacks */ + hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMAUpdateEventCplt; + hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt; + + /* Set the DMA error callback */ + hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError; + + /* Enable the DMA Channel */ + hdma = hlptim->hdma[LPTIM_DMA_ID_CC2]; + if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + default: + break; + } + + /* Enable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the LPTIM PWM generation in DMA mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable update event DMA request */ + __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_UPDATE); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Disable update event DMA request */ + (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]); + break; + case LPTIM_CHANNEL_2: + /* Disable update event DMA request */ + (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]); + break; + default: + break; + } + + /* Disable LPTIM signal from the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the LPTIM One pulse generation. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Reset WAVE bit to set one pulse mode */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Enable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Start timer in single (one shot) mode */ + __HAL_LPTIM_START_SINGLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the LPTIM One pulse generation. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the LPTIM One pulse generation in interrupt mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Reset WAVE bit to set one pulse mode */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Enable interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + case LPTIM_CHANNEL_2: + /* Enable interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* If external trigger source is used, then enable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + /* Enable external trigger interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Enable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Start timer in single (one shot) mode */ + __HAL_LPTIM_START_SINGLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the LPTIM One pulse generation in interrupt mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Disable interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + case LPTIM_CHANNEL_2: + /* Disable interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* If external trigger source is used, then enable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + /* Enable external trigger interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the LPTIM in Set once mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Set WAVE bit to enable the set once mode */ + hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Enable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Start timer in single (one shot) mode */ + __HAL_LPTIM_START_SINGLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the LPTIM Set once mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the LPTIM Set once mode in interrupt mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Set WAVE bit to enable the set once mode */ + hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Enable interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE); + break; + case LPTIM_CHANNEL_2: + /* Enable interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE); + break; + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* If external trigger source is used, then enable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + /* Enable external trigger interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Enable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Start timer in single (one shot) mode */ + __HAL_LPTIM_START_SINGLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the LPTIM Set once mode in interrupt mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Disable interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM); + break; + case LPTIM_CHANNEL_2: + /* Disable interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM); + break; + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* If external trigger source is used, then enable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + /* Enable external trigger interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the Encoder interface. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim) +{ + uint32_t tmpcfgr; + + /* Check the parameters */ + assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance)); + assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC); + assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1); + assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Get the LPTIMx CFGR value */ + tmpcfgr = hlptim->Instance->CFGR; + + /* Clear CKPOL bits */ + tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL); + + /* Set Input polarity */ + tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity; + + /* Write to LPTIMx CFGR */ + hlptim->Instance->CFGR = tmpcfgr; + + /* Set ENC bit to enable the encoder interface */ + hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the Encoder interface. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Reset ENC bit to disable the encoder interface */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the Encoder interface in interrupt mode. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim) +{ + uint32_t tmpcfgr; + + /* Check the parameters */ + assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance)); + assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC); + assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1); + assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Configure edge sensitivity for encoder mode */ + /* Get the LPTIMx CFGR value */ + tmpcfgr = hlptim->Instance->CFGR; + + /* Clear CKPOL bits */ + tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL); + + /* Set Input polarity */ + tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity; + + /* Write to LPTIMx CFGR */ + hlptim->Instance->CFGR = tmpcfgr; + + /* Set ENC bit to enable the encoder interface */ + hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Enable "switch to up/down direction" interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the Encoder interface in interrupt mode. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Reset ENC bit to disable the encoder interface */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Disable "switch to down/up direction" interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the Timeout function. + * @note The first trigger event will start the timer, any successive + * trigger event will reset the counter and the timer restarts. + * @param hlptim LPTIM handle + * @param Timeout Specifies the TimeOut value to reset the counter. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PULSE(Timeout)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set TIMOUT bit to enable the timeout function */ + hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK); + + /* Load the Timeout value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout); + + /* Wait for the completion of the write operation to the LPTIM_CCR1 register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the Timeout function. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Reset TIMOUT bit to enable the timeout function */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the Timeout function in interrupt mode. + * @note The first trigger event will start the timer, any successive + * trigger event will reset the counter and the timer restarts. + * @param hlptim LPTIM handle + * @param Timeout Specifies the TimeOut value to reset the counter. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PULSE(Timeout)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance); + + /* Set TIMOUT bit to enable the timeout function */ + hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Enable Compare match CH1 interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK); + + /* Load the Timeout value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout); + + /* Wait for the completion of the write operation to the LPTIM_CCR1 register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the Timeout function in interrupt mode. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + + /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Reset TIMOUT bit to enable the timeout function */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Disable Compare match CH1 interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the Counter mode. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + { + /* Check if clock is prescaled */ + assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); + /* Set clock prescaler to 0 */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; + } + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the Counter mode. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the Counter mode in interrupt mode. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance); + + /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + { + /* Check if clock is prescaled */ + assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); + /* Set clock prescaler to 0 */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; + } + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Enable interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the Counter mode in interrupt mode. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + + /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Disable interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the LPTIM Input Capture measurement. + * @param hlptim LPTIM Input Capture handle + * @param Channel LPTIM Channels to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Enable capture */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the LPTIM Input Capture measurement. + * @param hlptim LPTIM Input Capture handle + * @param Channel LPTIM Channels to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable capture */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the LPTIM Input Capture measurement in interrupt mode. + * @param hlptim LPTIM Input Capture handle + * @param Channel LPTIM Channels to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Enable Capture/Compare 1 interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1); + break; + case LPTIM_CHANNEL_2: + /* Disable Capture/Compare 2 interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC2); + break; + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Enable capture */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the LPTIM Input Capture measurement in interrupt mode. + * @param hlptim LPTIM Input Capture handle + * @param Channel LPTIM Channels to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Disable Capture/Compare 1 interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1); + break; + case LPTIM_CHANNEL_2: + /* Disable Capture/Compare 2 interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC2); + break; + default: + return HAL_ERROR; + break; + } + /* Disable capture */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the LPTIM Input Capture measurement in DMA mode. + * @param hlptim LPTIM Input Capture handle + * @param Channel LPTIM Channels to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected + * @param pData The destination Buffer address + * @param Length The length of data to be transferred from LPTIM peripheral to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData, + uint32_t Length) +{ + DMA_HandleTypeDef *hdma; + + /* Check the parameters */ + assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Set the DMA capture callbacks */ + hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMACaptureCplt; + hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError; + + /* Enable the DMA Channel */ + hdma = hlptim->hdma[LPTIM_DMA_ID_CC1]; + if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable Capture/Compare 1 DMA request */ + __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC1); + break; + + case LPTIM_CHANNEL_2: + /* Set the DMA capture callbacks */ + hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMACaptureCplt; + hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError; + + /* Enable the DMA Channel */ + hdma = hlptim->hdma[LPTIM_DMA_ID_CC2]; + if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable Capture/Compare 2 DMA request */ + __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC2); + break; + + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Enable capture */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the LPTIM Input Capture measurement in DMA mode. + * @param hlptim LPTIM Input Capture handle + * @param Channel LPTIM Channels to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Disable Capture/Compare 1 DMA request */ + __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]); + break; + + case LPTIM_CHANNEL_2: + /* Disable Capture/Compare 2 DMA request */ + __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]); + break; + default: + return HAL_ERROR; + break; + } + + /* Disable capture */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions + * @brief Read operation functions. + * +@verbatim + ============================================================================== + ##### LPTIM Read operation functions ##### + ============================================================================== +[..] This section provides LPTIM Reading functions. + (+) Read the counter value. + (+) Read the period (Auto-reload) value. + (+) Read the pulse (Compare)value. +@endverbatim + * @{ + */ + +/** + * @brief Return the current counter value. + * @param hlptim LPTIM handle + * @retval Counter value. + */ +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + return (hlptim->Instance->CNT); +} + +/** + * @brief Return the current Autoreload (Period) value. + * @param hlptim LPTIM handle + * @retval Autoreload value. + */ +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + return (hlptim->Instance->ARR); +} + +/** + * @brief Return the current Compare (Pulse) value. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be selected + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval Compare value. + */ +uint32_t HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + uint32_t tmpccr; + + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + tmpccr = hlptim->Instance->CCR1; + break; + case LPTIM_CHANNEL_2: + tmpccr = hlptim->Instance->CCR2; + break; + default: + tmpccr = 0; + break; + } + return tmpccr; +} + +/** + * @brief LPTimer Input Capture Get Offset(in counter step unit) + * @note The real capture value corresponding to the input capture trigger can be calculated using + * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset + * The Offset value is depending on the glitch filter value for the channel + * and the value of the prescaler for the kernel clock. + * Please check Errata Sheet V1_8 for more details under "variable latency + * on input capture channel" section. + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param Channel This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval The offset value + */ +uint8_t HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + + uint8_t offset ; + uint32_t prescaler; + uint32_t filter ; + + /* Get prescaler value */ + prescaler = LL_LPTIM_GetPrescaler(hlptim->Instance); + + /* Get filter value */ + filter = LL_LPTIM_IC_GetFilter(hlptim->Instance, Channel); + + /* Get offset value */ + offset = LL_LPTIM_IC_GET_OFFSET(prescaler, filter); + + /* return offset value */ + return offset; +} + +/** + * @} + */ +/** @defgroup LPTIM_Exported_Functions_Group5 LPTIM Config function + * @brief Config channel + * +@verbatim + ============================================================================== + ##### LPTIM Config function ##### + ============================================================================== +[..] This section provides LPTIM Config function. + (+) Configure channel: Output Compare mode, Period, Polarity. +@endverbatim + * @{ + */ + +/** + * @brief + * @param hlptim LPTIM handle + * @param sConfig The output configuration structure + * @param Channel LPTIM Channel to be configured + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @note Successive calls to HAL_LPTIM_OC_ConfigChannel can only be performed + * after a delay that must be greater or equal than the value of + * (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal + * division factor (1, 2, 4, ..., 128). Any successive call violating + * this delay, leads to unpredictable results. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status; + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + assert_param(IS_LPTIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_LPTIM_PULSE(sConfig->Pulse)); + + hlptim->State = HAL_LPTIM_STATE_BUSY; + + switch (Channel) + { + case LPTIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance)); + + /* Configure the LPTIM Channel 1 in Output Compare */ + status = LPTIM_OC1_SetConfig(hlptim, sConfig); + if (status != HAL_OK) + { + return status; + } + break; + } + case LPTIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance)); + + /* Configure the LPTIM Channel 2 in Output Compare */ + status = LPTIM_OC2_SetConfig(hlptim, sConfig); + if (status != HAL_OK) + { + return status; + } + break; + } + default: + break; + } + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief + * @param hlptim LPTIM handle + * @param sConfig The input configuration structure + * @param Channel LPTIM Channel to be configured + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @note Successive calls to HAL_LPTIM_IC_ConfigChannel can only be performed + * after a delay that must be greater or equal than the value of + * (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal + * division factor (1, 2, 4, ..., 128). Any successive call violating + * this delay, leads to unpredictable results. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + assert_param(IS_LPTIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_LPTIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_LPTIM_IC_FILTER(sConfig->ICFilter)); + + hlptim->State = HAL_LPTIM_STATE_BUSY; + + switch (Channel) + { + case LPTIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_IC1_SOURCE(hlptim->Instance, sConfig->ICInputSource)); + + /* Configure the LPTIM Channel 1 in Input Capture */ + LPTIM_IC1_SetConfig(hlptim, sConfig); + break; + } + case LPTIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_IC2_SOURCE(hlptim->Instance, sConfig->ICInputSource)); + + /* Configure the LPTIM Channel 2 in Input Capture */ + LPTIM_IC2_SetConfig(hlptim, sConfig); + break; + } + default: + break; + } + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks + * @brief LPTIM IRQ handler. + * +@verbatim + ============================================================================== + ##### LPTIM IRQ handler and callbacks ##### + ============================================================================== +[..] This section provides LPTIM IRQ handler and callback functions called within + the IRQ handler: + (+) LPTIM interrupt request handler + (+) Compare match Callback + (+) Auto-reload match Callback + (+) External trigger event detection Callback + (+) Compare register write complete Callback + (+) Auto-reload register write complete Callback + (+) Up-counting direction change Callback + (+) Down-counting direction change Callback + +@endverbatim + * @{ + */ + +/** + * @brief Handle LPTIM interrupt request. + * @param hlptim LPTIM handle + * @retval None + */ +void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) +{ + /* Capture Compare 1 interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1) != RESET) + { + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1); + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC1SEL) != 0x00U) + { +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->IC_CaptureCallback(hlptim); +#else + HAL_LPTIM_IC_CaptureCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->CompareMatchCallback(hlptim); +#else + HAL_LPTIM_CompareMatchCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; + } + } + + /* Capture Compare 2 interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2) != RESET) + { + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2); + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2; + + /* Input capture event */ + if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC2SEL) != 0x00U) + { +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->IC_CaptureCallback(hlptim); +#else + HAL_LPTIM_IC_CaptureCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->CompareMatchCallback(hlptim); +#else + HAL_LPTIM_CompareMatchCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; + } + } + + /* Over Capture 1 interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1O) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1O) != RESET) + { + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1O); + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1; + + /* Over capture event */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->IC_OverCaptureCallback(hlptim); +#else + HAL_LPTIM_IC_OverCaptureCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; + } + } + + /* Over Capture 2 interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2O) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2O) != RESET) + { + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2O); + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2; + + /* Over capture event */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->IC_OverCaptureCallback(hlptim); +#else + HAL_LPTIM_IC_OverCaptureCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; + } + } + + /* Autoreload match interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET) + { + /* Clear Autoreload match flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM); + + /* Autoreload match Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->AutoReloadMatchCallback(hlptim); +#else + HAL_LPTIM_AutoReloadMatchCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Trigger detected interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET) + { + /* Clear Trigger detected flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG); + + /* Trigger detected callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->TriggerCallback(hlptim); +#else + HAL_LPTIM_TriggerCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Compare write interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP1OK) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP1OK) != RESET) + { + /* Clear Compare write flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK); + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1; + /* Compare write Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->CompareWriteCallback(hlptim); +#else + HAL_LPTIM_CompareWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Compare write interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP2OK) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP2OK) != RESET) + { + /* Clear Compare write flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK); + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2; + /* Compare write Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->CompareWriteCallback(hlptim); +#else + HAL_LPTIM_CompareWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Autoreload write interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET) + { + /* Clear Autoreload write flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Autoreload write Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->AutoReloadWriteCallback(hlptim); +#else + HAL_LPTIM_AutoReloadWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Direction counter changed from Down to Up interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET) + { + /* Clear Direction counter changed from Down to Up flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP); + + /* Direction counter changed from Down to Up Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->DirectionUpCallback(hlptim); +#else + HAL_LPTIM_DirectionUpCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Direction counter changed from Up to Down interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET) + { + /* Clear Direction counter changed from Up to Down flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN); + + /* Direction counter changed from Up to Down Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->DirectionDownCallback(hlptim); +#else + HAL_LPTIM_DirectionDownCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Repetition counter underflowed (or contains zero) and the LPTIM counter + overflowed */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UPDATE) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UPDATE) != RESET) + { + /* Clear update event flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UPDATE); + + /* Update event Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->UpdateEventCallback(hlptim); +#else + HAL_LPTIM_UpdateEventCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Successful APB bus write to repetition counter register */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPOK) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPOK) != RESET) + { + /* Clear successful APB bus write to repetition counter flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK); + + /* Successful APB bus write to repetition counter Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->RepCounterWriteCallback(hlptim); +#else + HAL_LPTIM_RepCounterWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Compare match callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_CompareMatchCallback could be implemented in the user file + */ +} + +/** + * @brief Autoreload match callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file + */ +} + +/** + * @brief Trigger detected callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Compare write callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_CompareWriteCallback could be implemented in the user file + */ +} + +/** + * @brief Autoreload write callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file + */ +} + +/** + * @brief Direction counter changed from Down to Up callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_DirectionUpCallback could be implemented in the user file + */ +} + +/** + * @brief Direction counter changed from Up to Down callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_DirectionDownCallback could be implemented in the user file + */ +} + +/** + * @brief Repetition counter underflowed (or contains zero) and LPTIM counter overflowed callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_UpdateEventCallback could be implemented in the user file + */ +} + +/** + * @brief Successful APB bus write to repetition counter register callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_RepCounterWriteCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Over Capture callback in non-blocking mode + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_IC_OverCaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param hlptim LPTIM IC handle + * @retval None + */ +__weak void HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Update event half complete callback in non-blocking mode + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_UpdateEventHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Error callback in non-blocking mode + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_ErrorCallback could be implemented in the user file + */ +} + + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User LPTIM callback to be used instead of the weak predefined callback + * @param hlptim LPTIM handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID + * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID + * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID + * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID + * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID + * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID + * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID + * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID + * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, + HAL_LPTIM_CallbackIDTypeDef CallbackID, + pLPTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + if (hlptim->State == HAL_LPTIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = pCallback; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = pCallback; + break; + + case HAL_LPTIM_COMPARE_MATCH_CB_ID : + hlptim->CompareMatchCallback = pCallback; + break; + + case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : + hlptim->AutoReloadMatchCallback = pCallback; + break; + + case HAL_LPTIM_TRIGGER_CB_ID : + hlptim->TriggerCallback = pCallback; + break; + + case HAL_LPTIM_COMPARE_WRITE_CB_ID : + hlptim->CompareWriteCallback = pCallback; + break; + + case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : + hlptim->AutoReloadWriteCallback = pCallback; + break; + + case HAL_LPTIM_DIRECTION_UP_CB_ID : + hlptim->DirectionUpCallback = pCallback; + break; + + case HAL_LPTIM_DIRECTION_DOWN_CB_ID : + hlptim->DirectionDownCallback = pCallback; + break; + + case HAL_LPTIM_UPDATE_EVENT_CB_ID : + hlptim->UpdateEventCallback = pCallback; + break; + + case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID : + hlptim->RepCounterWriteCallback = pCallback; + break; + + case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID : + hlptim->UpdateEventHalfCpltCallback = pCallback; + break; + + case HAL_LPTIM_ERROR_CB_ID : + hlptim->ErrorCallback = pCallback; + break; + + case HAL_LPTIM_IC_CAPTURE_CB_ID : + hlptim->IC_CaptureCallback = pCallback; + break; + + case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID : + hlptim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_LPTIM_OVER_CAPTURE_CB_ID : + hlptim->IC_OverCaptureCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hlptim->State == HAL_LPTIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = pCallback; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a LPTIM callback + * LLPTIM callback is redirected to the weak predefined callback + * @param hlptim LPTIM handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID + * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID + * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID + * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID + * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID + * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID + * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID + * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID + * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, + HAL_LPTIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hlptim->State == HAL_LPTIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + /* Legacy weak MspInit Callback */ + hlptim->MspInitCallback = HAL_LPTIM_MspInit; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + /* Legacy weak Msp DeInit Callback */ + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; + break; + + case HAL_LPTIM_COMPARE_MATCH_CB_ID : + /* Legacy weak Compare match Callback */ + hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; + break; + + case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : + /* Legacy weak Auto-reload match Callback */ + hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; + break; + + case HAL_LPTIM_TRIGGER_CB_ID : + /* Legacy weak External trigger event detection Callback */ + hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; + break; + + case HAL_LPTIM_COMPARE_WRITE_CB_ID : + /* Legacy weak Compare register write complete Callback */ + hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; + break; + + case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : + /* Legacy weak Auto-reload register write complete Callback */ + hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; + break; + + case HAL_LPTIM_DIRECTION_UP_CB_ID : + /* Legacy weak Up-counting direction change Callback */ + hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; + break; + + case HAL_LPTIM_DIRECTION_DOWN_CB_ID : + /* Legacy weak Down-counting direction change Callback */ + hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; + break; + + case HAL_LPTIM_UPDATE_EVENT_CB_ID : + /* Legacy weak Update event detection Callback */ + hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback; + break; + + case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID : + /* Legacy weak Repetition counter register write complete Callback */ + hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback; + break; + + case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID : + /* Legacy weak Update event half complete detection Callback */ + hlptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback; + break; + + case HAL_LPTIM_ERROR_CB_ID : + /* Legacy weak error Callback */ + hlptim->ErrorCallback = HAL_LPTIM_ErrorCallback; + break; + + case HAL_LPTIM_IC_CAPTURE_CB_ID : + /* Legacy weak IC Capture Callback */ + hlptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback; + break; + + case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID : + /* Legacy weak IC Capture half complete Callback */ + hlptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback; + break; + + case HAL_LPTIM_OVER_CAPTURE_CB_ID : + /* Legacy weak IC over capture Callback */ + hlptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hlptim->State == HAL_LPTIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + /* Legacy weak MspInit Callback */ + hlptim->MspInitCallback = HAL_LPTIM_MspInit; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + /* Legacy weak Msp DeInit Callback */ + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup LPTIM_Group5 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the LPTIM handle state. + * @param hlptim LPTIM handle + * @retval HAL state + */ +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim) +{ + /* Return LPTIM handle state */ + return hlptim->State; +} + +/** + * @} + */ + + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @retval None + */ +static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) +{ + /* Reset the LPTIM callback to the legacy weak callbacks */ + lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; + lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; + lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; + lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; + lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; + lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; + lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; + lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback; + lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback; + lptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback; + lptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback; + lptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback; + lptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback; + lptim->ErrorCallback = HAL_LPTIM_ErrorCallback; +} +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + +/** + * @brief LPTimer Wait for flag set + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param flag The lptim flag + * @retval HAL status + */ +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag) +{ + HAL_StatusTypeDef result = HAL_OK; + uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL); + do + { + count--; + if (count == 0UL) + { + result = HAL_TIMEOUT; + } + } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); + + return result; +} + +/** + * @brief LPTIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void LPTIM_DMAError(DMA_HandleTypeDef *hdma) +{ + LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hlptim->State = HAL_LPTIM_STATE_READY; + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->ErrorCallback(hlptim); +#else + HAL_LPTIM_ErrorCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +} + +/** + * @brief LPTIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hlptim->State = HAL_LPTIM_STATE_READY; + + if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1; + } + else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->IC_CaptureCallback(hlptim); +#else + HAL_LPTIM_IC_CaptureCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief LPTIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hlptim->State = HAL_LPTIM_STATE_READY; + + if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1; + } + else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->IC_CaptureHalfCpltCallback(hlptim); +#else + HAL_LPTIM_IC_CaptureHalfCpltCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief LPTIM DMA Update event complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma) +{ + LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hlptim->State = HAL_LPTIM_STATE_READY; + + if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1; + } + else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->UpdateEventCallback(hlptim); +#else + HAL_LPTIM_UpdateEventCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief LPTIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma) +{ + LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hlptim->State = HAL_LPTIM_STATE_READY; + + if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1; + } + else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->UpdateEventHalfCpltCallback(hlptim); +#else + HAL_LPTIM_UpdateEventHalfCpltCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; +} +/** + * @brief LPTimer Output Compare 1 configuration + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param sConfig The output configuration structure + * @retval None + */ +static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig) +{ + uint32_t tmpccmr1; + uint32_t tmpcfgr; + + tmpccmr1 = hlptim->Instance->CCMR1; + tmpccmr1 &= ~(LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_CC1SEL_Msk); + + if ((hlptim->Instance == LPTIM4) || (hlptim->Instance == LPTIM5)) + { + tmpcfgr = hlptim->Instance->CFGR; + tmpcfgr &= ~LPTIM_CFGR_WAVPOL_Msk; + tmpcfgr |= sConfig->OCPolarity << LPTIM_CFGR_WAVPOL_Pos; + + /* Write to CFGR register */ + hlptim->Instance->CFGR = tmpcfgr; + } + else + { + tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC1P_Pos; + } + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK); + + /* Write to CCR1 register */ + __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, sConfig->Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CCR1 register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Write to CCMR1 register */ + hlptim->Instance->CCMR1 = tmpccmr1; + + return HAL_OK; +} + +/** + * @brief LPTimer Output Compare 2 configuration + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param sConfig The output configuration structure + * @retval None + */ +static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig) +{ + uint32_t tmpccmr1; + + tmpccmr1 = hlptim->Instance->CCMR1; + tmpccmr1 &= ~(LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_CC2SEL_Msk); + tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC2P_Pos; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK); + + /* Write to CCR2 register */ + __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, sConfig->Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CCR2 register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Write to CCMR1 register */ + hlptim->Instance->CCMR1 = tmpccmr1; + + return HAL_OK; +} + +/** + * @brief LPTimer Input Capture 1 configuration + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param sConfig The input configuration structure + * @retval None + */ +static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig) +{ + uint32_t tmpccmr1; + uint32_t tmpcfgr2; + + tmpccmr1 = hlptim->Instance->CCMR1; + tmpccmr1 &= ~(LPTIM_CCMR1_IC1PSC_Msk | LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_IC1F_Msk); + tmpccmr1 |= sConfig->ICPrescaler | + sConfig->ICPolarity | + sConfig->ICFilter | + LPTIM_CCMR1_CC1SEL; + + tmpcfgr2 = hlptim->Instance->CFGR2; + tmpcfgr2 &= ~(LPTIM_CFGR2_IC1SEL_Msk); + tmpcfgr2 |= sConfig->ICInputSource; + + /* Write to CCMR1 register */ + hlptim->Instance->CCMR1 = tmpccmr1; + + /* Write to CFGR2 register */ + hlptim->Instance->CFGR2 = tmpcfgr2; +} + +/** + * @brief LPTimer Input Capture 2 configuration + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param sConfig The input configuration structure + * @retval None + */ +static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig) +{ + uint32_t tmpccmr1; + uint32_t tmpcfgr2; + + tmpccmr1 = hlptim->Instance->CCMR1; + tmpccmr1 &= ~(LPTIM_CCMR1_IC2PSC_Msk | LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_IC2F_Msk); + tmpccmr1 |= (sConfig->ICPrescaler << (LPTIM_CCMR1_IC2PSC_Pos - LPTIM_CCMR1_IC1PSC_Pos)) | + (sConfig->ICPolarity << (LPTIM_CCMR1_CC2P_Pos - LPTIM_CCMR1_CC1P_Pos)) | + (sConfig->ICFilter << (LPTIM_CCMR1_IC2F_Pos - LPTIM_CCMR1_IC1F_Pos)) | + LPTIM_CCMR1_CC2SEL; + + tmpcfgr2 = hlptim->Instance->CFGR2; + tmpcfgr2 &= ~(LPTIM_CFGR2_IC2SEL_Msk); + tmpcfgr2 |= sConfig->ICInputSource; + + /* Write to CCMR1 register */ + hlptim->Instance->CCMR1 = tmpccmr1; + + /* Write to CFGR2 register */ + hlptim->Instance->CFGR2 = tmpcfgr2; +} + +/** + * @brief Start the DMA data transfer. + * @param hdma DMA handle + * @param src The source memory Buffer address. + * @param dst The destination memory Buffer address. + * @param length The size of a source block transfer in byte. + * @retval HAL status + */ +HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst, + uint32_t length) +{ + HAL_StatusTypeDef status; + + /* Enable the DMA channel */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U)) + { + /* Enable the DMA channel */ + hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length; + hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)src; + hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)dst; + + status = HAL_DMAEx_List_Start_IT(hdma); + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hdma, src, dst, length); + } + + return status; +} +/** + * @} + */ +#endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */ + +#endif /* HAL_LPTIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_ltdc.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_ltdc.c new file mode 100644 index 00000000000..fc03a09c89d --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_ltdc.c @@ -0,0 +1,2219 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_ltdc.c + * @author MCD Application Team + * @brief LTDC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the LTDC peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LTDC HAL driver can be used as follows: + + (#) Declare a LTDC_HandleTypeDef handle structure, for example: LTDC_HandleTypeDef hltdc; + + (#) Initialize the LTDC low level resources by implementing the HAL_LTDC_MspInit() API: + (##) Enable the LTDC interface clock + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the LTDC interrupt priority + (+++) Enable the NVIC LTDC IRQ Channel + + (#) Initialize the required configuration through the following parameters: + the LTDC timing, the horizontal and vertical polarity, the pixel clock polarity, + Data Enable polarity and the LTDC background color value using HAL_LTDC_Init() function + + *** Configuration *** + ========================= + [..] + (#) Program the required configuration through the following parameters: + the pixel format, the blending factors, input alpha value, the window size + and the image size using HAL_LTDC_ConfigLayer() function for foreground + or/and background layer. + + (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and + HAL_LTDC_EnableCLUT functions. + + (#) Optionally, enable the Dither using HAL_LTDC_EnableDither(). + + (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying() + and HAL_LTDC_EnableColorKeying functions. + + (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent() + function + + (#) If needed, reconfigure and change the pixel format value, the alpha value + value, the window size, the window position and the layer start address + for foreground or/and background layer using respectively the following + functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(), + HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress(). + + (#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload. + This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) + then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload(). + + After calling the _NoReload functions to set different color/format/layer settings, + the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings. + Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if + an immediate reload is required. + Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if + the reload should be done in the next vertical blanking period, + this option allows to avoid display flicker by applying the new settings during the vertical blanking period. + + + (#) To control LTDC state you can use the following function: HAL_LTDC_GetState() + + *** LTDC HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in LTDC HAL driver. + + (+) __HAL_LTDC_ENABLE: Enable the LTDC. + (+) __HAL_LTDC_DISABLE: Disable the LTDC. + (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer. + (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer. + (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload Layer Configuration. + (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags. + (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags. + (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. + (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts. + (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not. + + [..] + (@) You can refer to the LTDC HAL driver header file for more useful macros + + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use function HAL_LTDC_RegisterCallback() to register a callback. + + [..] + Function HAL_LTDC_RegisterCallback() allows to register following callbacks: + (+) LineEventCallback : LTDC Line Event Callback. + (+) ReloadEventCallback : LTDC Reload Event Callback. + (+) ErrorCallback : LTDC Error Callback + (+) MspInitCallback : LTDC MspInit. + (+) MspDeInitCallback : LTDC MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_LTDC_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_LTDC_UnRegisterCallback() takes as parameters the HAL peripheral handle + and the callback ID. + [..] + This function allows to reset following callbacks: + (+) LineEventCallback : LTDC Line Event Callback + (+) ReloadEventCallback : LTDC Reload Event Callback + (+) ErrorCallback : LTDC Error Callback + (+) MspInitCallback : LTDC MspInit + (+) MspDeInitCallback : LTDC MspDeInit. + + [..] + By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_LTDC_LineEventCallback(), HAL_LTDC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak (surcharged) functions in the HAL_LTDC_Init() and HAL_LTDC_DeInit() + only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_LTDC_Init() and HAL_LTDC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_LTDC_RegisterCallback() before calling HAL_LTDC_DeInit() + or HAL_LTDC_Init() function. + + [..] + When the compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#ifdef HAL_LTDC_MODULE_ENABLED + +#if defined (LTDC) + +/** @defgroup LTDC LTDC + * @brief LTDC HAL module driver + * @{ + */ + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup LTDC_Private_Define LTDC Private Define + * @{ + */ +#define LTDC_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup LTDC_Exported_Functions LTDC Exported Functions + * @{ + */ + +/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + (+) De-initialize the LTDC + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) +{ + uint32_t tmp; + uint32_t tmp1; + + /* Check the LTDC peripheral state */ + if (hltdc == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); + assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync)); + assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync)); + assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP)); + assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP)); + assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH)); + assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW)); + assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh)); + assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth)); + assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity)); + assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity)); + assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity)); + assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity)); + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + if (hltdc->State == HAL_LTDC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; + + /* Reset the LTDC callback to the legacy weak callbacks */ + hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */ + hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */ + hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hltdc->MspInitCallback == NULL) + { + hltdc->MspInitCallback = HAL_LTDC_MspInit; + } + /* Init the low level hardware */ + hltdc->MspInitCallback(hltdc); + } +#else + if (hltdc->State == HAL_LTDC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_LTDC_MspInit(hltdc); + } +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the HS, VS, DE and PC polarity */ + hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL); + hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ + hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); + + /* Set Synchronization size */ + hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); + tmp = (hltdc->Init.HorizontalSync << 16U); + hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); + + /* Set Accumulated Back porch */ + hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); + tmp = (hltdc->Init.AccumulatedHBP << 16U); + hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); + + /* Set Accumulated Active Width */ + hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); + tmp = (hltdc->Init.AccumulatedActiveW << 16U); + hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); + + /* Set Total Width */ + hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); + tmp = (hltdc->Init.TotalWidth << 16U); + hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); + + /* Set the background color value */ + tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); + tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U); + hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); + hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue); + + /* Enable the Transfer Error and FIFO underrun interrupts */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU); + + /* Enable LTDC by setting LTDCEN bit */ + __HAL_LTDC_ENABLE(hltdc); + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-initialize the LTDC peripheral. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ + +HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) +{ + uint32_t tickstart; + + /* Check the LTDC peripheral state */ + if (hltdc == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); + + /* Disable LTDC Layer 1 */ + __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_1); + +#if defined(LTDC_Layer2_BASE) + /* Disable LTDC Layer 2 */ + __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_2); +#endif /* LTDC_Layer2_BASE */ + + /* Reload during vertical blanking period */ + __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(hltdc); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for VSYNC Interrupt */ + while (READ_BIT(hltdc->Instance->CDSR, LTDC_CDSR_VSYNCS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > LTDC_TIMEOUT_VALUE) + { + break; + } + } + + /* Disable LTDC */ + __HAL_LTDC_DISABLE(hltdc); + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + if (hltdc->MspDeInitCallback == NULL) + { + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; + } + /* DeInit the low level hardware */ + hltdc->MspDeInitCallback(hltdc); +#else + /* DeInit the low level hardware */ + HAL_LTDC_MspDeInit(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Initialize the LTDC MSP. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-initialize the LTDC MSP. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User LTDC Callback + * To be used instead of the weak predefined callback + * @param hltdc ltdc handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID + * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID + * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, + pLTDC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hltdc); + + if (hltdc->State == HAL_LTDC_STATE_READY) + { + switch (CallbackID) + { + case HAL_LTDC_LINE_EVENT_CB_ID : + hltdc->LineEventCallback = pCallback; + break; + + case HAL_LTDC_RELOAD_EVENT_CB_ID : + hltdc->ReloadEventCallback = pCallback; + break; + + case HAL_LTDC_ERROR_CB_ID : + hltdc->ErrorCallback = pCallback; + break; + + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = pCallback; + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hltdc->State == HAL_LTDC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = pCallback; + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return status; +} + +/** + * @brief Unregister an LTDC Callback + * LTDC callback is redirected to the weak predefined callback + * @param hltdc ltdc handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID + * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID + * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hltdc); + + if (hltdc->State == HAL_LTDC_STATE_READY) + { + switch (CallbackID) + { + case HAL_LTDC_LINE_EVENT_CB_ID : + hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */ + break; + + case HAL_LTDC_RELOAD_EVENT_CB_ID : + hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */ + break; + + case HAL_LTDC_ERROR_CB_ID : + hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hltdc->State == HAL_LTDC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return status; +} +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides function allowing to: + (+) Handle LTDC interrupt request + +@endverbatim + * @{ + */ +/** + * @brief Handle LTDC interrupt request. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) +{ + uint32_t isrflags = READ_REG(hltdc->Instance->ISR); + uint32_t itsources = READ_REG(hltdc->Instance->IER); + + /* Transfer Error Interrupt management ***************************************/ + if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U)) + { + /* Disable the transfer Error interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE); + + /* Clear the transfer error flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE); + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_TE; + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Transfer error Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + hltdc->ErrorCallback(hltdc); +#else + /* Call legacy error callback*/ + HAL_LTDC_ErrorCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } + + /* FIFO underrun Interrupt management ***************************************/ + if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U)) + { + /* Disable the FIFO underrun interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU); + + /* Clear the FIFO underrun flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU); + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_FU; + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Transfer error Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + hltdc->ErrorCallback(hltdc); +#else + /* Call legacy error callback*/ + HAL_LTDC_ErrorCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } + + /* Line Interrupt management ************************************************/ + if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U)) + { + /* Disable the Line interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); + + /* Clear the Line interrupt flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI); + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Line interrupt Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered Line Event callback */ + hltdc->LineEventCallback(hltdc); +#else + /*Call Legacy Line Event callback */ + HAL_LTDC_LineEventCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } + + /* Register reload Interrupt management ***************************************/ + if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U)) + { + /* Disable the register reload interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR); + + /* Clear the register reload flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR); + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Reload interrupt Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered reload Event callback */ + hltdc->ReloadEventCallback(hltdc); +#else + /*Call Legacy Reload Event callback */ + HAL_LTDC_ReloadEventCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Error LTDC callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Line Event callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_LineEventCallback could be implemented in the user file + */ +} + +/** + * @brief Reload Event callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ReloadEvenCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the LTDC foreground or/and background parameters. + (+) Set the active layer. + (+) Configure the color keying. + (+) Configure the C-LUT. + (+) Enable / Disable the color keying. + (+) Enable / Disable the C-LUT. + (+) Update the layer position. + (+) Update the layer size. + (+) Update pixel format on the fly. + (+) Update transparency on the fly. + (+) Update address on the fly. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the LTDC Layer according to the specified + * parameters in the LTDC_InitTypeDef and create the associated handle. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains + * the configuration information for the Layer. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); + assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Configure the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the default color values */ + LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Load the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pCLUT pointer to the color lookup table address. + * @param CLUTSize the color lookup table size. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize, + uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t counter; + const uint32_t *pcolorlut = pCLUT; + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + for (counter = 0U; (counter < CLUTSize); counter++) + { + if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44) + { + tmp = (((counter + (16U * counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \ + ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); + } + else + { + tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \ + ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); + } + + pcolorlut++; + + /* Specifies the C-LUT address and RGB value */ + LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp; + } + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable Dither. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable Dither by setting DTEN bit */ + LTDC->GCR |= (uint32_t)LTDC_GCR_DEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable Dither. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable Dither by setting DTEN bit */ + LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window size. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters (Layers parameters)*/ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(XSize)); + assert_param(IS_LTDC_CFBLNBR(YSize)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal stop */ + pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; + + /* update vertical stop */ + pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; + + /* Reconfigures the color frame buffer pitch in byte */ + pLayerCfg->ImageWidth = XSize; + + /* Reconfigures the frame buffer line number */ + pLayerCfg->ImageHeight = YSize; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window position. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(X0)); + assert_param(IS_LTDC_CFBLNBR(Y0)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = X0; + pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = Y0; + pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the pixel format. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the pixel format */ + pLayerCfg->PixelFormat = Pixelformat; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the layer alpha value. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_ALPHA(Alpha)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Alpha value */ + pLayerCfg->Alpha = Alpha; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} +/** + * @brief Reconfigure the frame buffer Address. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Address */ + pLayerCfg->FBStartAdress = Address; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width + * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to + * layer for which we want to read and display on screen only a portion 320x240 taken in the center + * of the buffer. + * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous + * call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default + * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t pitchUpdate; + uint32_t pixelFormat; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4U; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3U; + } + else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2U; + } + else + { + tmp = 1U; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16U); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Set the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Set the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Define the position of the line interrupt. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Line Line Interrupt Position. + * @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LIPOS(Line)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable the Line interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); + + /* Set the Line Interrupt position */ + LTDC->LIPCR = (uint32_t)Line; + + /* Enable the Line interrupt */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reload LTDC Layers configuration. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param ReloadType This parameter can be one of the following values : + * LTDC_RELOAD_IMMEDIATE : Immediate Reload + * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking + * @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType) +{ + /* Check the parameters */ + assert_param(IS_LTDC_RELOAD(ReloadType)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable the Reload interrupt */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR); + + /* Apply Reload type */ + hltdc->Instance->SRCR = ReloadType; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Configure the LTDC Layer according to the specified without reloading + * parameters in the LTDC_InitTypeDef and create the associated handle. + * Variant of the function HAL_LTDC_ConfigLayer without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains + * the configuration information for the Layer. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, + uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); + assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window size without reloading. + * Variant of the function HAL_LTDC_SetWindowSize without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, + uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters (Layers parameters)*/ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(XSize)); + assert_param(IS_LTDC_CFBLNBR(YSize)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal stop */ + pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; + + /* update vertical stop */ + pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; + + /* Reconfigures the color frame buffer pitch in byte */ + pLayerCfg->ImageWidth = XSize; + + /* Reconfigures the frame buffer line number */ + pLayerCfg->ImageHeight = YSize; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window position without reloading. + * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, + uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(X0)); + assert_param(IS_LTDC_CFBLNBR(Y0)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = X0; + pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = Y0; + pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the pixel format without reloading. + * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDfef structure that contains + * the configuration information for the LTDC. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the pixel format */ + pLayerCfg->PixelFormat = Pixelformat; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the layer alpha value without reloading. + * Variant of the function HAL_LTDC_SetAlpha without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_ALPHA(Alpha)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Alpha value */ + pLayerCfg->Alpha = Alpha; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the frame buffer Address without reloading. + * Variant of the function HAL_LTDC_SetAddress without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Address */ + pLayerCfg->FBStartAdress = Address; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width + * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to + * layer for which we want to read and display on screen only a portion 320x240 taken in the center + * of the buffer. + * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by + * previous call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default + * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * Variant of the function HAL_LTDC_SetPitch without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t pitchUpdate; + uint32_t pixelFormat; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4U; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3U; + } + else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2U; + } + else + { + tmp = 1U; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16U); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + + +/** + * @brief Configure the color keying without reloading. + * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the default color values */ + LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color keying without reloading. + * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color keying without reloading. + * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color lookup table without reloading. + * Variant of the function HAL_LTDC_EnableCLUT without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color lookup table without reloading. + * Variant of the function HAL_LTDC_DisableCLUT without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the LTDC handle state. + (+) Get the LTDC handle error code. + +@endverbatim + * @{ + */ + +/** + * @brief Return the LTDC handle state. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL state + */ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc) +{ + return hltdc->State; +} + +/** + * @brief Return the LTDC handle error code. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval LTDC Error Code + */ +uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc) +{ + return hltdc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup LTDC_Private_Functions LTDC Private Functions + * @{ + */ + +/** + * @brief Configure the LTDC peripheral + * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg Pointer LTDC Layer Configuration structure + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval None + */ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t tmp1; + uint32_t tmp2; + + /* Configure the horizontal start and stop position */ + tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); + + /* Configure the vertical start and stop position */ + tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp); + + /* Specifies the pixel format */ + LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF); + LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat); + + /* Configure the default color values */ + tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); + tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); + tmp2 = (pLayerCfg->Alpha0 << 24U); + WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->DCCR, (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2)); + + /* Specifies the constant alpha value */ + LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); + LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha); + + /* Specifies the blending factors */ + LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); + LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); + + /* Configure the color frame buffer start address */ + WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CFBAR, pLayerCfg->FBStartAdress); + + if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4U; + } + else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3U; + } + else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2U; + } + else + { + tmp = 1U; + } + + /* Configure the color frame buffer pitch in byte */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); + LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | + (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 7U)); + /* Configure the frame buffer line number */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); + + /* Enable LTDC_Layer by setting LEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN; +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* LTDC */ + +#endif /* HAL_LTDC_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_ltdc_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_ltdc_ex.c new file mode 100644 index 00000000000..49d32d7351a --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_ltdc_ex.c @@ -0,0 +1,154 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_ltdc_ex.c + * @author MCD Application Team + * @brief LTDC Extension HAL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED) + +#if defined (LTDC) && defined (DSI) + +/** @defgroup LTDCEx LTDCEx + * @brief LTDC HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions + * @{ + */ + +/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + +@endverbatim + * @{ + */ + +/** + * @brief Retrieve common parameters from DSI Video mode configuration structure + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarity is inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */ + +#if !defined(POLARITIES_INVERSION_UPDATED) + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \ + DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL; + hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL; +#else + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; +#endif /* POLARITIES_INVERSION_UPDATED */ + + /* Retrieve vertical timing parameters from DSI */ + hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U; + hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U; + hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \ + VidCfg->VerticalActive - 1U; + hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \ + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U; + + return HAL_OK; +} + +/** + * @brief Retrieve common parameters from DSI Adapted command mode configuration structure + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains + * the DSI command mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarities are inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH + LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH + LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ + +#if !defined(POLARITIES_INVERSION_UPDATED) + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \ + DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; + hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; +#else + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; +#endif /* POLARITIES_INVERSION_UPDATED */ + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LTDC && DSI */ + +#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mce.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mce.c new file mode 100644 index 00000000000..58a0f939430 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mce.c @@ -0,0 +1,1063 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_mce.c + * @author MCD Application Team + * @brief MCE HAL module driver. + * This file provides firmware functions to manage the following + * features of the Memory Cipher Engine (MCE) peripheral: + * + Initialization and de-initialization functions + * + Region setting/enable functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The MCE HAL driver can be used as follows: + + (#) ToBC (refer to MCE comments) + + + [..] + + *** Callback registration *** + ============================================= + [..] + + The compilation flag USE_HAL_MCE_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_MCE_RegisterCallback() + to register an interrupt callback. + [..] + + ToBC (refer to MCE comments) + + When the compilation flag USE_HAL_MCE_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup MCE MCE + * @brief MCE HAL module driver. + * @{ + */ + + +#ifdef HAL_MCE_MODULE_ENABLED + +#if defined(MCE1) + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +#define MCE_TIMEOUT_VALUE 255U /* Internal timeout for keys valid flag */ +#define MCE1_CONTEXT_NB 2U +/* Private macros ------------------------------------------------------------*/ + + +#define IS_MCE_AES_INSTANCE(INSTANCE) ((INSTANCE) == MCE1) +#define IS_MCE_NOEKEON_INSTANCE(INSTANCE) ((INSTANCE) == MCE2) || ((INSTANCE) == MCE3) + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup MCE_Exported_Functions + * @{ + */ + +/** @defgroup MCE_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the MCE peripheral and create the associated handle. + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MCE_Init(MCE_HandleTypeDef *hmce) +{ + /* Check the MCE handle allocation */ + if (hmce == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance)); + + if (hmce->State == HAL_MCE_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + __HAL_UNLOCK(hmce); + +#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1) + /* Init the MCE Callback settings */ + hmce->ErrorCallback = HAL_MCE_ErrorCallback; /* Legacy weak callback */ + + if (hmce->MspInitCallback == NULL) + { + hmce->MspInitCallback = HAL_MCE_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hmce->MspInitCallback(hmce); +#else + /* Init the low level hardware */ + HAL_MCE_MspInit(hmce); +#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */ + } + + /* Change the MCE state */ + hmce->State = HAL_MCE_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the MCE peripheral. + * @note Any lock set at peripheral, key or cipher context level requires a MCE peripheral reset + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MCE_DeInit(MCE_HandleTypeDef *hmce) +{ + MCE_Region_TypeDef *p_region; + MCE_Context_TypeDef *p_context; + + /* Check the MCE handle allocation */ + if (hmce == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance)); + + /* Change the MCE state */ + hmce->State = HAL_MCE_STATE_BUSY; + + /* Disable interrupts */ + CLEAR_BIT(hmce->Instance->IAIER, MCE_IAIER_IAEIE | MCE_IAIER_CAEIE); + + /* Disable all regions */ + for (uint32_t i = MCE_REGION1; i <= MCE_REGION4; i++) + { + p_region = (MCE_Region_TypeDef *)((uint32_t)(hmce->Instance) + 0x40U + (0x10U * i)); + CLEAR_BIT(p_region->REGCR, MCE_REGCR_BREN); + CLEAR_BIT(p_region->ATTR, MCE_ATTR_WREN); + } + + /* Disable all cipher contexts if any for the MCE instance */ + if (hmce->Instance == MCE1) + { + for (uint32_t i = 0; i < MCE1_CONTEXT_NB; i++) + { + p_context = (MCE_Context_TypeDef *)((uint32_t)(hmce->Instance) + 0x240U + (0x30U * i)); + CLEAR_BIT(p_context->CCCFGR, MCE_CCCFGR_CCEN); + } + } + + /* Clear privileged-only configuration access */ + CLEAR_BIT(hmce->Instance->PRIVCFGR, MCE_PRIVCFGR_PRIV); + + /* Clear flags */ + WRITE_REG(hmce->Instance->IACR, MCE_IACR_IAEF | MCE_IACR_CAEF); + +#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1) + if (hmce->MspDeInitCallback == NULL) + { + hmce->MspDeInitCallback = HAL_MCE_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: CLOCK, NVIC */ + hmce->MspDeInitCallback(hmce); +#else + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_MCE_MspDeInit(hmce); +#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */ + + /* Change the MCE state */ + hmce->State = HAL_MCE_STATE_RESET; + + /* Reset MCE error status */ + hmce->ErrorCode = HAL_MCE_ERROR_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hmce); + + /* Return function status */ + return HAL_OK; +} + + +/** ********* main sequence functions : set the configuration of regions, AES context and Noekeon config *********/ + +/** + * @brief Write instance master or fast master keys + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @param pConfig pointer at an MCE_NoekeonConfig structure that contains + the configuration on the Noekeon encryption engine + * @note Writes are ignored if MKLOCK or GLOCK bit is set in MCE_CR register and HAL error + * is reported in that case + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MCE_ConfigNoekeon(MCE_HandleTypeDef *hmce, const MCE_NoekeonConfigTypeDef *pConfig) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance)); + + assert_param(IS_MCE_NOEKEON_INSTANCE(hmce->Instance)); + /* If Key is null, or + if the global lock is set or + if the master keys lock is set, + return an error */ + tickstart = HAL_GetTick(); + if (((hmce->Instance->CR & (MCE_CR_GLOCK | MCE_CR_MKLOCK)) == 0U) && (pConfig->pKey != NULL)) + { + /* Take Lock */ + __HAL_LOCK(hmce); + + /* master keys are used for encryption */ + if (pConfig->KeyType == MCE_USE_MASTERKEYS) + { + /* If Master Key valid flag is set, need to write dummy value in MKEYRx to reset it */ + if ((hmce->Instance->SR & MCE_SR_MKVALID) != 0U) + { + WRITE_REG(hmce->Instance->MKEYR0, 0U); + } + + /* Set Key */ + WRITE_REG(hmce->Instance->MKEYR0, pConfig->pKey[0]); + WRITE_REG(hmce->Instance->MKEYR1, pConfig->pKey[1]); + WRITE_REG(hmce->Instance->MKEYR2, pConfig->pKey[2]); + WRITE_REG(hmce->Instance->MKEYR3, pConfig->pKey[3]); + if (HAL_IS_BIT_CLR(hmce->Instance->SR, MCE_SR_MKVALID)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > MCE_TIMEOUT_VALUE) + { + + hmce->ErrorCode |= HAL_MCE_MASTER_KEY_ERROR; + ret = HAL_ERROR; + } + } + + } + else if (pConfig->KeyType == MCE_USE_FASTMASTERKEYS) + { + /* If Fast Master Key valid flag is set, need to write dummy value in FMKEYRx to reset it */ + if ((hmce->Instance->SR & MCE_SR_FMKVALID) != 0U) + { + WRITE_REG(hmce->Instance->FMKEYR0, 0U); + } + /* Set Key */ + WRITE_REG(hmce->Instance->FMKEYR0, pConfig->pKey[0]); + WRITE_REG(hmce->Instance->FMKEYR1, pConfig->pKey[1]); + WRITE_REG(hmce->Instance->FMKEYR2, pConfig->pKey[2]); + WRITE_REG(hmce->Instance->FMKEYR3, pConfig->pKey[3]); + if (HAL_IS_BIT_CLR(hmce->Instance->SR, MCE_SR_FMKVALID)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > MCE_TIMEOUT_VALUE) + { + hmce->ErrorCode |= HAL_MCE_FASTMASTER_KEY_ERROR; + ret = HAL_ERROR; + } + } + } + else + { + /* nothing to do, the keytype is not valid */ + } + __HAL_UNLOCK(hmce); + } + return ret; +} + + +/** + * @brief Set context configuration. + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @param AESConfig context configuration + * @param ContextIndex index of context that is configured + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MCE_ConfigAESContext(MCE_HandleTypeDef *hmce, const MCE_AESConfigTypeDef *AESConfig, + uint32_t ContextIndex) +{ + HAL_StatusTypeDef ret = HAL_ERROR; + MCE_Context_TypeDef *p_context; + uint32_t *p_key; + __IO uint32_t address; + + /* Check the parameters */ + assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance)); + assert_param(IS_MCE_AES_INSTANCE(hmce->Instance)); + assert_param(IS_MCE_CONTEXT(hmce->Instance, ContextIndex)); + + + /* If global lock is set or no configuration provided, context cannot be configured */ + if (((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK) && (AESConfig != NULL) && \ + ((ContextIndex == MCE_CONTEXT1) || (ContextIndex == MCE_CONTEXT2))) + { + address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x240UL + \ + (0x30UL * ((ContextIndex - MCE_CONTEXT1) >> MCE_REGCR_CTXID_Pos))); + p_context = (MCE_Context_TypeDef *)address; + /* Check cipher context is not locked */ + if (((p_context->CCCFGR & MCE_CCCFGR_CCLOCK) != MCE_CCCFGR_CCLOCK)) + { + if ((p_context->CCCFGR & MCE_CCCFGR_KEYLOCK) != MCE_CCCFGR_KEYLOCK) + { + /* Take Lock */ + __HAL_LOCK(hmce); + + /* Write nonce */ + WRITE_REG(p_context->CCNR0, AESConfig->Nonce[0]); + WRITE_REG(p_context->CCNR1, AESConfig->Nonce[1]); + + if (AESConfig->pKey != NULL) + { + p_key = AESConfig->pKey; + WRITE_REG(p_context->CCKEYR0, *p_key); + p_key++; + WRITE_REG(p_context->CCKEYR1, *p_key); + p_key++; + WRITE_REG(p_context->CCKEYR2, *p_key); + p_key++; + WRITE_REG(p_context->CCKEYR3, *p_key); + } + /* Compute theoretically expected CRC and compare it with that reported by the peripheral */ + + /* Write version */ + MODIFY_REG(p_context->CCCFGR, MCE_CCCFGR_VERSION, ((uint32_t) AESConfig->Version) << MCE_CCCFGR_VERSION_Pos); + + ret = HAL_OK; + + /* Release Lock */ + __HAL_UNLOCK(hmce); + } + } + } + return ret; +} + + +/** + * @brief Set region configuration. + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @param RegionIndex index of region that is configured + * @param pConfig region configuration + * @note The region is enabled by default once the configuration is complete + * @note An enabled region is temporary disabled to apply the new configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MCE_ConfigRegion(MCE_HandleTypeDef *hmce, uint32_t RegionIndex, + const MCE_RegionConfigTypeDef *pConfig) +{ + HAL_StatusTypeDef ret = HAL_ERROR; + MCE_Region_TypeDef *p_region; + __IO uint32_t address; + + /* Check the parameters */ + assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance)); + assert_param(IS_MCE_REGIONINDEX(RegionIndex)); + assert_param(IS_MCE_ALGORITHM(hmce->Instance, pConfig->Mode)); + + assert_param(IS_MCE_WRITE(pConfig->AccessMode)); + assert_param(IS_MCE_REGIONPRIVILEGED(pConfig->PrivilegedAccess)); + + /* If global lock is set or no configuration provided, region cannot be configured */ + if (((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK) && (pConfig != NULL)) + { + /* Take Lock */ + __HAL_LOCK(hmce); + + address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x40U + (0x10U * RegionIndex)); + p_region = (MCE_Region_TypeDef *)address; + + /* If region is enabled, disable it during the configuration process */ + if ((p_region->REGCR & MCE_REGCR_BREN) == MCE_REGCR_BREN) + { + CLEAR_BIT(p_region->REGCR, MCE_REGCR_BREN); + } + + /* Set privileged access, ciphering algorithm and context ID */ + MODIFY_REG(p_region->REGCR, MCE_REGCR_ENC | MCE_REGCR_PRIV, \ + pConfig->PrivilegedAccess | pConfig->Mode); + + /* Set start and end addresses */ + WRITE_REG(p_region->SADDR, pConfig->StartAddress); + WRITE_REG(p_region->EADDR, pConfig->EndAddress); + + /* Set write attribute for the region */ + MODIFY_REG(p_region->ATTR, MCE_ATTR_WREN, pConfig->AccessMode); + + /* Enable the region by default */ + SET_BIT(p_region->REGCR, MCE_REGCR_BREN); + + ret = HAL_OK; + + /* Release Lock */ + __HAL_UNLOCK(hmce); + } + + return ret; + +} + +HAL_StatusTypeDef HAL_MCE_SetRegionAESContext(MCE_HandleTypeDef *hmce, uint32_t ContextIndex, uint32_t RegionIndex) +{ + HAL_StatusTypeDef ret = HAL_ERROR; + MCE_Region_TypeDef *p_region; + __IO uint32_t address; + + assert_param(IS_MCE_CONTEXT(hmce->Instance, ContextIndex)); + assert_param(IS_MCE_REGIONINDEX(RegionIndex)); + + /* If global lock is set, region cannot be configured */ + if ((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK) + { + + /* Take Lock */ + __HAL_LOCK(hmce); + + address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x40U + (0x10U * RegionIndex)); + p_region = (MCE_Region_TypeDef *)address; + + /* If region is enabled, disable it during the configuration process */ + if ((p_region->REGCR & MCE_REGCR_BREN) == MCE_REGCR_BREN) + { + CLEAR_BIT(p_region->REGCR, MCE_REGCR_BREN); + } + + /* Set context ID */ + MODIFY_REG(p_region->REGCR, MCE_REGCR_CTXID, ContextIndex); + + /* Enable the region by default */ + SET_BIT(p_region->REGCR, MCE_REGCR_BREN); + + ret = HAL_OK; + + /* Release Lock */ + __HAL_UNLOCK(hmce); + + } + + return ret; +} + + +/** ********* Enabling and disabling functions : enable/disable AES and Noekeon configurations and regions *********/ + + +/** + * @brief Cipher context enable + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @param ContextIndex index of context that is enabled + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MCE_EnableAESContext(MCE_HandleTypeDef *hmce, uint32_t ContextIndex) +{ + MCE_Context_TypeDef *p_context; + __IO uint32_t address; + + /* Check the parameters */ + assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance)); + assert_param(IS_MCE_CONTEXT(hmce->Instance, ContextIndex)); + + if ((ContextIndex != MCE_CONTEXT1) && (ContextIndex != MCE_CONTEXT2)) + { + return HAL_ERROR; + } + + address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x240UL + \ + (0x30UL * ((ContextIndex - MCE_CONTEXT1) >> MCE_REGCR_CTXID_Pos))); + p_context = (MCE_Context_TypeDef *)address; + + /* If cipher context is locked or if global lock is set, + and if cipher context is not enabled already, return an error */ + + if ((p_context->CCCFGR & MCE_CCCFGR_CCEN) != MCE_CCCFGR_CCEN) + { + if ((p_context->CCCFGR & MCE_CCCFGR_CCLOCK) == MCE_CCCFGR_CCLOCK) + { + return HAL_ERROR; + } + if ((hmce->Instance->CR & MCE_CR_GLOCK) == MCE_CR_GLOCK) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(hmce); + + /* Enable context */ + SET_BIT(p_context->CCCFGR, MCE_CCCFGR_CCEN); + + __HAL_UNLOCK(hmce); + + return HAL_OK; + +} + +/** + * @brief Cipher context disable + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @param ContextIndex index of context that is disabled + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MCE_DisableAESContext(MCE_HandleTypeDef *hmce, uint32_t ContextIndex) +{ + MCE_Context_TypeDef *p_context; + __IO uint32_t address; + + /* Check the parameters */ + assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance)); + assert_param(IS_MCE_CONTEXT(hmce->Instance, ContextIndex)); + + if ((ContextIndex != MCE_CONTEXT1) && (ContextIndex != MCE_CONTEXT2)) + { + return HAL_ERROR; + } + + address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x240UL + \ + (0x30UL * ((ContextIndex - MCE_CONTEXT1) >> MCE_REGCR_CTXID_Pos))); + p_context = (MCE_Context_TypeDef *)address; + + /* If cipher context is locked or if global lock is set, + and if cipher context is not disabled already, return an error */ + + if ((p_context->CCCFGR & MCE_CCCFGR_CCEN) == MCE_CCCFGR_CCEN) + { + if ((p_context->CCCFGR & MCE_CCCFGR_CCLOCK) == MCE_CCCFGR_CCLOCK) + { + return HAL_ERROR; + } + if ((hmce->Instance->CR & MCE_CR_GLOCK) == MCE_CR_GLOCK) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(hmce); + + /* Disable context */ + CLEAR_BIT(p_context->CCCFGR, MCE_CCCFGR_CCEN); + + __HAL_UNLOCK(hmce); + + return HAL_OK; + +} + + +/** + * @brief Enable region. + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @param RegionIndex index of region that is enabled + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MCE_EnableRegion(MCE_HandleTypeDef *hmce, uint32_t RegionIndex) +{ + HAL_StatusTypeDef ret = HAL_ERROR; + MCE_Region_TypeDef *p_region; + __IO uint32_t address; + + /* Check the parameters */ + assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance)); + assert_param(IS_MCE_REGIONINDEX(RegionIndex)); + + /* If global lock is set, region cannot be configured */ + if ((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK) + { + address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x40U + (0x10U * RegionIndex)); + p_region = (MCE_Region_TypeDef *)address; + + /* Take Lock */ + __HAL_LOCK(hmce); + + /* Check region is not enabled, else error */ + if ((p_region->REGCR & MCE_REGCR_BREN) != MCE_REGCR_BREN) + { + /* Enable the region */ + SET_BIT(p_region->REGCR, MCE_REGCR_BREN); + + ret = HAL_OK; + } + + /* Release Lock */ + __HAL_UNLOCK(hmce); + } + + return ret; + +} + + +/** + * @brief Disable region. + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @param RegionIndex index of region that is disabled + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MCE_DisableRegion(MCE_HandleTypeDef *hmce, uint32_t RegionIndex) +{ + HAL_StatusTypeDef ret = HAL_ERROR; + MCE_Region_TypeDef *p_region; + __IO uint32_t address; + + /* Check the parameters */ + assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance)); + assert_param(IS_MCE_REGIONINDEX(RegionIndex)); + + address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x40U + (0x10U * RegionIndex)); + p_region = (MCE_Region_TypeDef *)address; + + /* If global lock is set, region cannot be configured */ + if ((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK) + { + /* Take Lock */ + __HAL_LOCK(hmce); + + /* Check region is enabled, else error */ + if ((p_region->REGCR & MCE_REGCR_BREN) == MCE_REGCR_BREN) + { + /* Disable the region */ + CLEAR_BIT(p_region->REGCR, MCE_REGCR_BREN); + + ret = HAL_OK; + } + + /* Release Lock */ + __HAL_UNLOCK(hmce); + } + + return ret; + +} + + +/** ************* Lock functions : Lock AES and Noekeon configurations and keys *********/ + +/** + * @brief Lock MCE instance registers configuration + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @note Once MCE_CR_GLOCK is set, all writes to MCE registers are ignored, + * with the exception of MCE_IACR and MCE_IAIER registers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MCE_LockGlobalConfig(MCE_HandleTypeDef *hmce) +{ + /* Check the parameters */ + assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance)); + + /* Take Lock */ + __HAL_LOCK(hmce); + + SET_BIT(hmce->Instance->CR, MCE_CR_GLOCK); + + /* Release Lock */ + __HAL_UNLOCK(hmce); + + return HAL_OK; + +} + +/** + * @brief Lock cipher context + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @param ContextIndex index of context that is locked + * @note Once MCE_CCCFGR_CCLOCK is set, writes to MCE_CCxCFGR and MCE_CCxNR registers + * are ignored until next MCE reset. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MCE_LockAESContextConfig(MCE_HandleTypeDef *hmce, uint32_t ContextIndex) +{ + HAL_StatusTypeDef ret = HAL_ERROR; + MCE_Context_TypeDef *p_context; + __IO uint32_t address; + + /* Check the parameters */ + assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance)); + assert_param(IS_MCE_CONTEXT(hmce->Instance, ContextIndex)); + + /* If global lock is set or no configuration provided, context cannot be configured */ + if (((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK) && \ + ((ContextIndex == MCE_CONTEXT1) || (ContextIndex == MCE_CONTEXT2))) + { + address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x240UL + \ + (0x30UL * ((ContextIndex - MCE_CONTEXT1) >> MCE_REGCR_CTXID_Pos))); + p_context = (MCE_Context_TypeDef *)address; + + /* Take Lock */ + __HAL_LOCK(hmce); + + SET_BIT(p_context->CCCFGR, MCE_CCCFGR_CCLOCK); + + ret = HAL_OK; + + /* Release Lock */ + __HAL_UNLOCK(hmce); + } + + return ret; + +} + +/** + * @brief Lock context cipher key + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @param ContextIndex index of context the cipher key of which is locked + * @note Once MCE_CCCFGR_KEYLOCK is set, writes to MCE_CCxKEYR registers are ignored + * until next MCE reset. KEYCRC bitfield value does not change. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MCE_LockAESContextKey(MCE_HandleTypeDef *hmce, uint32_t ContextIndex) +{ + HAL_StatusTypeDef ret = HAL_ERROR; + MCE_Context_TypeDef *p_context; + __IO uint32_t address; + + /* Check the parameters */ + assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance)); + assert_param(IS_MCE_CONTEXT(hmce->Instance, ContextIndex)); + + /* If global lock is set or no configuration provided, context cannot be configured */ + if (((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK) && \ + ((ContextIndex == MCE_CONTEXT1) || (ContextIndex == MCE_CONTEXT2))) + { + address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x240UL + \ + (0x30UL * ((ContextIndex - MCE_CONTEXT1) >> MCE_REGCR_CTXID_Pos))); + p_context = (MCE_Context_TypeDef *)address; + + /* Take Lock */ + __HAL_LOCK(hmce); + + SET_BIT(p_context->CCCFGR, MCE_CCCFGR_KEYLOCK); + + ret = HAL_OK; + + /* Release Lock */ + __HAL_UNLOCK(hmce); + } + + return ret; + +} + +/** + * @brief Lock Noekeon master keys + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @note Once MCE_CR_MKLOCK is set, writes to MCE_MKEYRx and MCE_FMKEYRx registers are ignored until next MCE reset. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MCE_LockNoekeonMasterKeys(MCE_HandleTypeDef *hmce) +{ + HAL_StatusTypeDef ret = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance)); + + /* If global lock is set, master keys lock cannot be set */ + if ((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK) + { + /* Take Lock */ + __HAL_LOCK(hmce); + + SET_BIT(hmce->Instance->CR, MCE_CR_MKLOCK); + + ret = HAL_OK; + + /* Release Lock */ + __HAL_UNLOCK(hmce); + } + + return ret; + +} + + +/** + * @brief Initialize the MCE MSP. + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @retval None + */ +__weak void HAL_MCE_MspInit(MCE_HandleTypeDef *hmce) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmce); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_MCE_MspInit can be implemented in the user file. + */ +} + +/** + * @brief DeInitialize MCE MSP. + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @retval None + */ +__weak void HAL_MCE_MspDeInit(MCE_HandleTypeDef *hmce) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmce); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_MCE_MspDeInit can be implemented in the user file. + */ +} + +/** + * @brief get the CRC key of the specified context. + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @param pCRCKey pointer to the CRC key + * @param ContextIndex index of CONTEXT the CRC key + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_MCE_GetAESContextCRCKey(const MCE_HandleTypeDef *hmce, uint32_t *pCRCKey, uint32_t ContextIndex) +{ + HAL_StatusTypeDef ret = HAL_OK; + MCE_Context_TypeDef *p_context; + __IO uint32_t address; + + /* Check the parameters */ + assert_param(IS_MCE_AES_INSTANCE(hmce->Instance)); + assert_param(IS_MCE_CONTEXT(hmce->Instance, ContextIndex)); + + address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x240UL + \ + (0x30UL * ((ContextIndex - MCE_CONTEXT1) >> MCE_REGCR_CTXID_Pos))); + p_context = (MCE_Context_TypeDef *)address; + + *pCRCKey = READ_REG((p_context->CCCFGR)) & MCE_CCCFGR_KEYCRC; + + *pCRCKey >>= MCE_CCCFGR_KEYCRC_Pos; + if (*pCRCKey == 0x00U) + { + ret = HAL_ERROR; + } + + return ret; +} + +/** + * @brief Compute Key CRC + * @param pKey pointer at set of keys + * @retval CRC value + */ +uint32_t HAL_MCE_KeyCRCComputation(const uint32_t *pKey) +{ + uint8_t crc7_poly = 0x7; + const uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U}; + uint8_t i; + uint8_t crc = 0; + uint32_t j; + uint32_t keyval; + uint32_t k; + const uint32_t *temp = pKey; + + for (j = 0U; j < 4U; j++) + { + keyval = *temp; + temp++; + if (j == 0U) + { + keyval ^= key_strobe[0]; + } + else + { + keyval ^= (key_strobe[j] << 24) | ((uint32_t)crc << 16) | (key_strobe[j] << 8) | crc; + } + + crc = 0; + for (i = 0; i < (uint8_t)32; i++) + { + k = ((((uint32_t)crc >> 7) ^ ((keyval >> ((uint8_t)31 - i)) & ((uint8_t)0xF)))) & 1U; + crc <<= 1; + if (k != 0U) + { + crc ^= crc7_poly; + } + } + + crc ^= (uint8_t)0x55; + } + + return (uint32_t) crc; +} + +/** + * @brief Handle MCE interrupt request. + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @retval None + */ +void HAL_MCE_IRQHandler(MCE_HandleTypeDef *hmce) +{ + uint32_t isr_reg; + uint32_t iaesr_reg; + + isr_reg = READ_REG(hmce->Instance->IASR); + if ((isr_reg & MCE_IASR_CAEF) == MCE_IASR_CAEF) + { + /* Set configuration access error */ + hmce->ErrorCode |= HAL_MCE_CONFIGURATION_ACCESS_ERROR; + + /* Clear configuration access error flag */ + WRITE_REG(hmce->Instance->IACR, MCE_IACR_CAEF); + } + if ((isr_reg & MCE_IASR_IAEF) == MCE_IASR_IAEF) + { + iaesr_reg = (READ_REG(hmce->Instance->IAESR) & (MCE_IAESR_IAPRIV | MCE_IAESR_IANRW)); + + /* Clear illegal access error flag */ + WRITE_REG(hmce->Instance->IACR, MCE_IACR_IAEF); + + /* Set precise illegal access error */ + if (iaesr_reg == MCE_IAESR_IAPRIV) + { + /* Illegal privileged data read or instruction fetch access error */ + hmce->ErrorCode |= HAL_MCE_ILLEGAL_ACCESS_READ_PRIV_ERROR; + } + else if (iaesr_reg == (MCE_IAESR_IAPRIV | MCE_IAESR_IANRW)) + { + /* Illegal privileged data write access error */ + hmce->ErrorCode |= HAL_MCE_ILLEGAL_ACCESS_WRITE_PRIV_ERROR; + } + else if (iaesr_reg == MCE_IAESR_IANRW) + { + /* Illegal un privileged data write access error */ + hmce->ErrorCode |= HAL_MCE_ILLEGAL_ACCESS_WRITE_NPRIV_ERROR; + } + else + { + /* Illegal unprivileged data read or instruction fetch access error */ + hmce->ErrorCode |= HAL_MCE_ILLEGAL_ACCESS_READ_NPRIV_ERROR; + } + } + +#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1) + hmce->ErrorCallback(hmce); +#else + HAL_MCE_ErrorCallback(hmce); +#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */ +} + +/** + * @brief MCE error callback. + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @retval None + */ +__weak void HAL_MCE_ErrorCallback(MCE_HandleTypeDef *hmce) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmce); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_MCE_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief Return the MCE state. + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @retval HAL status + */ +HAL_MCE_StateTypeDef HAL_MCE_GetState(MCE_HandleTypeDef const *hmce) +{ + /* Check the parameters */ + assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance)); + + return hmce->State; +} + +/** + * @brief Return the MCE error code. + * @param hmce pointer to an MCE_HandleTypeDef structure that contains + * the configuration information for MCE module + * @retval MCE error code (bitfield on 32 bits) + */ +uint32_t HAL_MCE_GetError(MCE_HandleTypeDef const *hmce) +{ + /* Check the parameters */ + assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance)); + + return hmce->ErrorCode; +} + + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* MCE1 */ + +#endif /* HAL_MCE_MODULE_ENABLED */ + + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mdf.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mdf.c new file mode 100644 index 00000000000..11d2f4bcf0f --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mdf.c @@ -0,0 +1,2236 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_mdf.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Multi-function Digital Filter (MDF) + * peripheral: + * + Initialization and de-initialization + * + Acquisition + * + Clock absence detection + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** Initialization and de-initialization *** + ============================================ + [..] + (#) User has first to initialize ADF instance. + (#) As prerequisite, fill in the HAL_MDF_MspInit() : + (++) Enable ADFz clock interface with __HAL_RCC_ADFz_CLK_ENABLE(). + (++) Enable the clocks for the used GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). + (++) Configure these pins in alternate mode using HAL_GPIO_Init(). + (++) If interrupt mode is used, enable and configure ADFz_FLTx + interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (++) If DMA mode is used, initialize and configure DMA. + (#) Configure the common parameters, serial interface parameters and + filter bitstream selection by calling HAL_MDF_Init() function. + + [..] + (#) User can de-initialize ADF instance with HAL_MDF_DeInit() function. + + *** Acquisition *** + =================== + [..] + (#) Configure filter parameters and start acquisition using HAL_MDF_AcqStart(), + HAL_MDF_AcqStart_IT() or HAL_MDF_AcqStart_DMA(). + (#) In polling mode : + (++) Use HAL_MDF_PollForAcq() to detect the end of acquisition. + Use HAL_MDF_GetAcqValue to get acquisition value. + (++) Use HAL_MDF_PollForSndLvl() to detect and get + new sound level value and ambient noise value. + (++) Use HAL_MDF_PollForSad() to detect sound activity. + (#) In interrupt mode : + (++) HAL_MDF_AcqCpltCallback() will be called at the end of acquisition. + Use HAL_MDF_GetAcqValue to get acquisition value. + (++) HAL_MDF_SndLvlCallback() will be called when new + sound level and ambient noise values are available. + (++) HAL_MDF_SadCallback() will be called when + sound activity detection occurs. + (++) HAL_MDF_ErrorCallback() will be called if overflow, filter overrun or + saturation occurs. + Use HAL_MDF_GetErrorCode() to get the corresponding error. + (#) In DMA mode : + (++) HAL_MDF_AcqHalfCpltCallback() and HAL_MDF_AcqCpltCallback() will be called + respectively at the half acquisition and at the acquisition complete. + (++) HAL_MDF_SndLvlCallback() will be called when new + sound level and ambient noise values are available. + (++) HAL_MDF_SadCallback() will be called when + sound activity detection occurs. + (++) HAL_MDF_ErrorCallback() will be called if overflow, filter overrun, + saturation or DMA error occurs. + Use HAL_MDF_GetErrorCode() to get the corresponding error. + (#) Use HAL_MDF_GenerateTrgo() to generate pulse on TRGO signal. + (#) During acquisition, use HAL_MDF_SetDelay() and HAL_MDF_GetDelay() to respectively + set and get the delay on data source. + (#) During acquisition, use HAL_MDF_SetGain() and HAL_MDF_GetGain() to respectively + set and get the filter gain. + (#) Stop acquisition using HAL_MDF_AcqStop(), HAL_MDF_AcqStop_IT() or HAL_MDF_AcqStop_DMA(). + + *** Clock absence detection *** + =============================== + [..] + (#) Clock absence detection is always enabled so no need to start clock absence detection + in polling mode. + Use HAL_MDF_CkabStart_IT() to start clock absence detection in interrupt mode. + (#) In polling mode, use HAL_MDF_PollForCkab() to detect the clock absence. + (#) In interrupt mode, HAL_MDF_ErrorCallback() will be called if clock absence detection + occurs. + Use HAL_MDF_GetErrorCode() to get the corresponding error. + (#) Stop clock absence detection in interrupt mode using HAL_MDF_CkabStop_IT(). + + *** generic functions *** + ========================= + [..] + (#) HAL_MDF_IRQHandler will be called when ADF interrupt occurs. + (#) HAL_MDF_ErrorCallback will be called when ADF error occurs. + (#) Use HAL_MDF_GetState() to get the current ADF instance state. + (#) Use HAL_MDF_GetErrorCode() to get the current ADF instance error code. + + *** Callback registration *** + ============================= + [..] + The compilation define USE_HAL_MDF_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use functions HAL_MDF_RegisterCallback(), HAL_MDF_RegisterOldCallback() + or HAL_MDF_RegisterSndLvlCallback() to register a user callback. + + [..] + Function HAL_MDF_RegisterCallback() allows to register following callbacks : + (+) AcqCpltCallback : Acquisition complete callback. + (+) AcqHalfCpltCallback : Acquisition half complete callback. + (+) SadCallback : Sound activity detection callback (only for ADF instance). + (+) ErrorCallback : Error callback. + (+) MspInitCallback : MSP init callback. + (+) MspDeInitCallback : MSP de-init callback. + [..] + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + For specific sound level callback use dedicated register callback : + HAL_MDF_RegisterSndLvlCallback(). + + [..] + Use function HAL_MDF_UnRegisterCallback() to reset a callback to the default weak function. + + [..] + HAL_MDF_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID. + [..] + This function allows to reset following callbacks : + (+) AcqCpltCallback : Acquisition complete callback. + (+) AcqHalfCpltCallback : Acquisition half complete callback. + (+) SadCallback : Sound activity detection callback (only for ADF instance). + (+) ErrorCallback : Error callback. + (+) MspInitCallback : MSP init callback. + (+) MspDeInitCallback : MSP de-init callback. + + [..] + For specific sound level callback use dedicated unregister callback : + HAL_MDF_UnRegisterSndLvlCallback(). + + [..] + By default, after the call of init function and if the state is RESET + all callbacks are reset to the corresponding legacy weak functions : + examples HAL_MDF_AcqCpltCallback(), HAL_MDF_ErrorCallback(). + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak functions in the init and de-init only when these + callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the init and de-init keep and use + the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the init/de-init. + In that case first register the MspInit/MspDeInit user callbacks using + HAL_MDF_RegisterCallback() before calling init or de-init function. + + [..] + When the compilation define USE_HAL_MDF_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak callbacks are used. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup MDF MDF + * @brief MDF HAL module driver + * @{ + */ + +#ifdef HAL_MDF_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/** @defgroup MDF_Private_Typedefs MDF Private Typedefs + * @{ + */ +/** + * @} + */ + +/* Private define ------------------------------------------------------------*/ +/** @defgroup MDF_Private_Constants MDF Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup MDF_Private_Variables MDF Private Variables + * @{ + */ +static MDF_HandleTypeDef *v_mdfHandle = NULL; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup MDF_Private_Functions MDF Private Functions + * @{ + */ +static void MDF_AcqStart(MDF_HandleTypeDef *const hmdf, const MDF_FilterConfigTypeDef *const pFilterConfig); +static void MDF_DmaXferCpltCallback(DMA_HandleTypeDef *hdma); +static void MDF_DmaXferHalfCpltCallback(DMA_HandleTypeDef *hdma); +static void MDF_DmaErrorCallback(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup MDF_Exported_Functions MDF Exported Functions + * @{ + */ + +/** @defgroup MDF_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to : + (+) Initialize the ADF instance. + (+) De-initialize the ADF instance. + (+) Register and unregister callbacks. +@endverbatim + * @{ + */ + +/** + * @brief Initialize the MDF instance according to the specified parameters + * in the MDF_InitTypeDef structure and initialize the associated handle. + * @param hmdf MDF handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_Init(MDF_HandleTypeDef *hmdf) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check MDF handle */ + if (hmdf == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_MDF_ALL_INSTANCE(hmdf->Instance)); + assert_param(IS_MDF_FILTER_BITSTREAM(hmdf->Init.FilterBistream)); + assert_param(IS_FUNCTIONAL_STATE(hmdf->Init.SerialInterface.Activation)); + + /* Check that instance has not been already initialized */ + if (v_mdfHandle != NULL) + { + status = HAL_ERROR; + } + else + { +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hmdf->SndLvCallback = HAL_MDF_SndLvlCallback; + hmdf->SadCallback = HAL_MDF_SadCallback; + hmdf->AcqCpltCallback = HAL_MDF_AcqCpltCallback; + hmdf->AcqHalfCpltCallback = HAL_MDF_AcqHalfCpltCallback; + hmdf->ErrorCallback = HAL_MDF_ErrorCallback; + + /* Call MDF MSP init function */ + if (hmdf->MspInitCallback == NULL) + { + hmdf->MspInitCallback = HAL_MDF_MspInit; + } + hmdf->MspInitCallback(hmdf); +#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ + /* Call MDF MSP init function */ + HAL_MDF_MspInit(hmdf); +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ + + /* Configure common parameters */ + /* Check clock generator status */ + if ((ADF1->CKGCR & MDF_CKGCR_CKGACTIVE) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Configure processing clock divider, output clock divider, + output clock pins and output clock generation trigger */ + assert_param(IS_MDF_PROC_CLOCK_DIVIDER(hmdf->Init.CommonParam.ProcClockDivider)); + assert_param(IS_FUNCTIONAL_STATE(hmdf->Init.CommonParam.OutputClock.Activation)); + ADF1->CKGCR = 0U; + ADF1->CKGCR |= ((hmdf->Init.CommonParam.ProcClockDivider - 1U) << MDF_CKGCR_PROCDIV_Pos); + if (hmdf->Init.CommonParam.OutputClock.Activation == ENABLE) + { + assert_param(IS_MDF_OUTPUT_CLOCK_PINS(hmdf->Init.CommonParam.OutputClock.Pins)); + assert_param(IS_MDF_OUTPUT_CLOCK_DIVIDER(hmdf->Init.CommonParam.OutputClock.Divider)); + assert_param(IS_FUNCTIONAL_STATE(hmdf->Init.CommonParam.OutputClock.Trigger.Activation)); + ADF1->CKGCR |= (((hmdf->Init.CommonParam.OutputClock.Divider - 1U) << MDF_CKGCR_CCKDIV_Pos) | + hmdf->Init.CommonParam.OutputClock.Pins | + (hmdf->Init.CommonParam.OutputClock.Pins >> 4U)); + if (hmdf->Init.CommonParam.OutputClock.Trigger.Activation == ENABLE) + { + assert_param(IS_MDF_OUTPUT_CLOCK_TRIGGER_SOURCE(hmdf->Init.CommonParam.OutputClock.Trigger.Source)); + assert_param(IS_MDF_OUTPUT_CLOCK_TRIGGER_EDGE(hmdf->Init.CommonParam.OutputClock.Trigger.Edge)); + ADF1->CKGCR |= (hmdf->Init.CommonParam.OutputClock.Trigger.Source | + hmdf->Init.CommonParam.OutputClock.Trigger.Edge | + MDF_CKGCR_CKGMOD); + } + } + + /* Activate clock generator */ + ADF1->CKGCR |= MDF_CKGCR_CKGDEN; + } + + /* Configure serial interface */ + if ((status == HAL_OK) && (hmdf->Init.SerialInterface.Activation == ENABLE)) + { + /* Check serial interface status */ + if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Configure mode, clock source and threshold */ + assert_param(IS_MDF_SITF_MODE(hmdf->Init.SerialInterface.Mode)); + assert_param(IS_MDF_SITF_CLOCK_SOURCE(hmdf->Init.SerialInterface.ClockSource)); + assert_param(IS_MDF_SITF_THRESHOLD(hmdf->Init.SerialInterface.Threshold)); + hmdf->Instance->SITFCR = 0U; + hmdf->Instance->SITFCR |= ((hmdf->Init.SerialInterface.Threshold << MDF_SITFCR_STH_Pos) | + hmdf->Init.SerialInterface.Mode | hmdf->Init.SerialInterface.ClockSource); + + /* Activate serial interface */ + hmdf->Instance->SITFCR |= MDF_SITFCR_SITFEN; + } + } + + if (status == HAL_OK) + { + /* Configure filter bitstream */ + hmdf->Instance->BSMXCR &= ~(MDF_BSMXCR_BSSEL); + hmdf->Instance->BSMXCR |= hmdf->Init.FilterBistream; + + /* Update instance pointer */ + v_mdfHandle = hmdf; + + /* Update error code and state */ + hmdf->ErrorCode = MDF_ERROR_NONE; + hmdf->State = HAL_MDF_STATE_READY; + } + } + } + + /* Return function status */ + return status; +} + +/** + * @brief De-initialize the MDF instance. + * @param hmdf MDF handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_DeInit(MDF_HandleTypeDef *hmdf) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check MDF handle */ + if (hmdf == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check parameters */ + assert_param(IS_MDF_ALL_INSTANCE(hmdf->Instance)); + + /* Check that instance has not been already deinitialized */ + if (v_mdfHandle == NULL) + { + status = HAL_ERROR; + } + else + { + /* Disable sound activity detector if needed */ + if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U) + { + hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN); + } + + /* Disable filter if needed */ + if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U) + { + hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN); + } + + /* Disable serial interface if needed */ + if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) != 0U) + { + hmdf->Instance->SITFCR &= ~(MDF_SITFCR_SITFEN); + } + + /* Disable all interrupts and clear all pending flags */ + hmdf->Instance->DFLTIER = 0U; + hmdf->Instance->DFLTISR = 0xFFFFFFFFU; + + /* Disable clock generator */ + ADF1->CKGCR &= ~(MDF_CKGCR_CKGDEN); + + /* Call MDF MSP deinit function */ +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) + if (hmdf->MspDeInitCallback == NULL) + { + hmdf->MspDeInitCallback = HAL_MDF_MspDeInit; + } + hmdf->MspDeInitCallback(hmdf); +#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ + HAL_MDF_MspDeInit(hmdf); +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ + + /* Update instance pointer */ + v_mdfHandle = (MDF_HandleTypeDef *) NULL; + + /* Update state */ + hmdf->State = HAL_MDF_STATE_RESET; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Initialize the MDF instance MSP. + * @param hmdf MDF handle. + * @retval None. + */ +__weak void HAL_MDF_MspInit(MDF_HandleTypeDef *hmdf) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdf); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_MDF_MspInit could be implemented in the user file */ +} + +/** + * @brief De-initialize the MDF instance MSP. + * @param hmdf MDF handle. + * @retval None. + */ +__weak void HAL_MDF_MspDeInit(MDF_HandleTypeDef *hmdf) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdf); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_MDF_MspDeInit could be implemented in the user file */ +} + +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user MDF callback to be used instead of the weak predefined callback. + * @param hmdf MDF handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_MDF_ACQ_COMPLETE_CB_ID acquisition complete callback ID. + * @arg @ref HAL_MDF_ACQ_HALFCOMPLETE_CB_ID acquisition half complete callback ID. + * @arg @ref HAL_MDF_SAD_CB_ID sound activity detector callback ID (only for ADF instance). + * @arg @ref HAL_MDF_ERROR_CB_ID error callback ID. + * @arg @ref HAL_MDF_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_MDF_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_RegisterCallback(MDF_HandleTypeDef *hmdf, + HAL_MDF_CallbackIDTypeDef CallbackID, + pMDF_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + if (pCallback == NULL) + { + /* Update error code and status */ + hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + else + { + if (hmdf->State == HAL_MDF_STATE_READY) + { + switch (CallbackID) + { + case HAL_MDF_ACQ_COMPLETE_CB_ID : + hmdf->AcqCpltCallback = pCallback; + break; + case HAL_MDF_ACQ_HALFCOMPLETE_CB_ID : + hmdf->AcqHalfCpltCallback = pCallback; + break; + case HAL_MDF_SAD_CB_ID : + hmdf->SadCallback = pCallback; + break; + case HAL_MDF_ERROR_CB_ID : + hmdf->ErrorCallback = pCallback; + break; + case HAL_MDF_MSPINIT_CB_ID : + hmdf->MspInitCallback = pCallback; + break; + case HAL_MDF_MSPDEINIT_CB_ID : + hmdf->MspDeInitCallback = pCallback; + break; + default : + /* Update error code and status */ + hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else if (hmdf->State == HAL_MDF_STATE_RESET) + { + switch (CallbackID) + { + case HAL_MDF_MSPINIT_CB_ID : + hmdf->MspInitCallback = pCallback; + break; + case HAL_MDF_MSPDEINIT_CB_ID : + hmdf->MspDeInitCallback = pCallback; + break; + default : + /* Update error code and status */ + hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else + { + /* Update error code and status */ + hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Unregister a user MDF callback. + * MDF callback is redirected to the weak predefined callback. + * @param hmdf MDF handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_MDF_ACQ_COMPLETE_CB_ID acquisition complete callback ID. + * @arg @ref HAL_MDF_ACQ_HALFCOMPLETE_CB_ID acquisition half complete callback ID. + * @arg @ref HAL_MDF_SAD_CB_ID sound activity detector callback ID (only for ADF instance). + * @arg @ref HAL_MDF_ERROR_CB_ID error callback ID. + * @arg @ref HAL_MDF_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_MDF_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_UnRegisterCallback(MDF_HandleTypeDef *hmdf, + HAL_MDF_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hmdf->State == HAL_MDF_STATE_READY) + { + switch (CallbackID) + { + case HAL_MDF_ACQ_COMPLETE_CB_ID : + hmdf->AcqCpltCallback = HAL_MDF_AcqCpltCallback; + break; + case HAL_MDF_ACQ_HALFCOMPLETE_CB_ID : + hmdf->AcqHalfCpltCallback = HAL_MDF_AcqHalfCpltCallback; + break; + case HAL_MDF_SAD_CB_ID : + hmdf->SadCallback = HAL_MDF_SadCallback; + break; + case HAL_MDF_ERROR_CB_ID : + hmdf->ErrorCallback = HAL_MDF_ErrorCallback; + break; + case HAL_MDF_MSPINIT_CB_ID : + hmdf->MspInitCallback = HAL_MDF_MspInit; + break; + case HAL_MDF_MSPDEINIT_CB_ID : + hmdf->MspDeInitCallback = HAL_MDF_MspDeInit; + break; + default : + /* Update error code and status */ + hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else if (hmdf->State == HAL_MDF_STATE_RESET) + { + switch (CallbackID) + { + case HAL_MDF_MSPINIT_CB_ID : + hmdf->MspInitCallback = HAL_MDF_MspInit; + break; + case HAL_MDF_MSPDEINIT_CB_ID : + hmdf->MspDeInitCallback = HAL_MDF_MspDeInit; + break; + default : + /* Update error code and status */ + hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else + { + /* Update error code and status */ + hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +/** + * @brief Register specific MDF sound level callback + * to be used instead of the weak predefined callback. + * @param hmdf MDF handle. + * @param pCallback pointer to the sound level callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_RegisterSndLvlCallback(MDF_HandleTypeDef *hmdf, + pMDF_SndLvlCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + if (pCallback == NULL) + { + /* Update error code and status */ + hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + else + { + if (hmdf->State == HAL_MDF_STATE_READY) + { + hmdf->SndLvCallback = pCallback; + } + else + { + /* Update error code and status */ + hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Unregister the specific MDF sound level callback. + * MDF sound level callback is redirected to the weak predefined callback. + * @param hmdf MDF handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_UnRegisterSndLvlCallback(MDF_HandleTypeDef *hmdf) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hmdf->State == HAL_MDF_STATE_READY) + { + hmdf->SndLvCallback = HAL_MDF_SndLvlCallback; + } + else + { + /* Update error code and status */ + hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup MDF_Exported_Functions_Group2 Acquisition functions + * @brief Acquisition functions + * +@verbatim + ============================================================================== + ##### Acquisition functions ##### + ============================================================================== + [..] This section provides functions allowing to : + (+) Start and stop acquisition in polling, interrupt or DMA mode. + (+) Wait and get acquisition values. + (+) Generate pulse on TRGO signal. + (+) Modify and get some filter parameters during acquisition. + (+) Wait and get sound level values. + (+) Detect sound activity. +@endverbatim + * @{ + */ + +/** + * @brief This function allows to start acquisition in polling mode. + * @param hmdf MDF handle. + * @param pFilterConfig Filter configuration parameters. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + if (pFilterConfig == NULL) + { + status = HAL_ERROR; + } + else + { + assert_param(IS_MDF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode)); + assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation)); + if ((pFilterConfig->SoundActivity.Activation == ENABLE) && + ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE) || + (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SINGLE) || + (pFilterConfig->AcquisitionMode == MDF_MODE_WINDOW_CONT))) + { + status = HAL_ERROR; + } + /* Check state */ + else if (hmdf->State != HAL_MDF_STATE_READY) + { + status = HAL_ERROR; + } + /* Check filter status */ + else if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Check SAD status */ + if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U) + { + status = HAL_ERROR; + } + } + + if (status == HAL_OK) + { + /* Configure filter and start acquisition */ + hmdf->Instance->DFLTCR = 0U; + MDF_AcqStart(hmdf, pFilterConfig); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to poll for available acquisition value. + * @param hmdf MDF handle. + * @param Timeout Timeout value in milliseconds. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_PollForAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check state */ + if (hmdf->State != HAL_MDF_STATE_ACQUISITION) + { + status = HAL_ERROR; + } + else + { + uint32_t tickstart = HAL_GetTick(); + + /* Wait for available acquisition value */ + while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_RXNEF) != MDF_DFLTISR_RXNEF) && (status == HAL_OK)) + { + /* Check the timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + status = HAL_TIMEOUT; + } + } + } + + /* Check if data overflow, saturation or reshape filter occurs */ + uint32_t error_flags = (hmdf->Instance->DFLTISR & (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF)); + if (error_flags != 0U) + { + /* Update error code */ + if ((error_flags & MDF_DFLTISR_DOVRF) == MDF_DFLTISR_DOVRF) + { + hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW; + } + if ((error_flags & MDF_DFLTISR_SATF) == MDF_DFLTISR_SATF) + { + hmdf->ErrorCode |= MDF_ERROR_SATURATION; + } + if ((error_flags & MDF_DFLTISR_RFOVRF) == MDF_DFLTISR_RFOVRF) + { + hmdf->ErrorCode |= MDF_ERROR_RSF_OVERRUN; + } + + /* Clear corresponding flags */ + hmdf->Instance->DFLTISR |= error_flags; + + /* Call error callback */ +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) + hmdf->ErrorCallback(hmdf); +#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ + HAL_MDF_ErrorCallback(hmdf); +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ + } + + if (status == HAL_OK) + { + /* Update state only in asynchronous single shot mode */ + if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_ACQMOD) == MDF_MODE_ASYNC_SINGLE) + { + hmdf->State = HAL_MDF_STATE_READY; + } + } + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to get acquisition value. + * @param hmdf MDF handle. + * @param pValue Acquisition value on 24 MSB. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_GetAcqValue(const MDF_HandleTypeDef *hmdf, int32_t *pValue) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + if (pValue == NULL) + { + status = HAL_ERROR; + } + else + { + /* Check state */ + if (hmdf->State != HAL_MDF_STATE_ACQUISITION) + { + if (hmdf->State != HAL_MDF_STATE_READY) + { + status = HAL_ERROR; + } + } + } + + if (status == HAL_OK) + { + /* Get acquisition value */ + *pValue = (int32_t) hmdf->Instance->DFLTDR; + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to stop acquisition in polling mode. + * @param hmdf MDF handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_AcqStop(MDF_HandleTypeDef *hmdf) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check state */ + if (hmdf->State != HAL_MDF_STATE_ACQUISITION) + { + /* Check if state is ready and filter active */ + if (hmdf->State == HAL_MDF_STATE_READY) + { + if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != MDF_DFLTCR_DFLTACTIVE) + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + } + else + { + /* Disable sound activity detector if needed */ + if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U) + { + hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN); + } + } + + if (status == HAL_OK) + { + /* Disable filter */ + hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN); + + /* Clear all potential pending flags */ + hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF | + MDF_DFLTISR_SDDETF | MDF_DFLTISR_SDLVLF); + + /* Update state */ + hmdf->State = HAL_MDF_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to start acquisition in interrupt mode. + * @param hmdf MDF handle. + * @param pFilterConfig Filter configuration parameters. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + if (pFilterConfig == NULL) + { + status = HAL_ERROR; + } + else + { + assert_param(IS_MDF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode)); + assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation)); + if ((pFilterConfig->SoundActivity.Activation == ENABLE) && + ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE) || + (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SINGLE) || + (pFilterConfig->AcquisitionMode == MDF_MODE_WINDOW_CONT))) + { + status = HAL_ERROR; + } + /* Check state */ + else if (hmdf->State != HAL_MDF_STATE_READY) + { + status = HAL_ERROR; + } + /* Check filter status */ + else if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Check SAD status */ + if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U) + { + status = HAL_ERROR; + } + } + + if (status == HAL_OK) + { + if ((pFilterConfig->SoundActivity.Activation == DISABLE) || + (pFilterConfig->SoundActivity.DataMemoryTransfer != MDF_SAD_NO_MEMORY_TRANSFER)) + { + /* Enable data overflow and fifo threshold interrupts */ + hmdf->Instance->DFLTIER |= (MDF_DFLTIER_DOVRIE | MDF_DFLTIER_FTHIE); + } + + if (pFilterConfig->ReshapeFilter.Activation == ENABLE) + { + /* Enable reshape filter overrun interrupt */ + hmdf->Instance->DFLTIER |= MDF_DFLTIER_RFOVRIE; + } + + /* Enable saturation interrupt */ + hmdf->Instance->DFLTIER |= MDF_DFLTIER_SATIE; + + if (pFilterConfig->SoundActivity.Activation == ENABLE) + { + /* Enable sound level value ready and sound activity detection interrupts */ + assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.SoundLevelInterrupt)); + hmdf->Instance->DFLTIER |= (pFilterConfig->SoundActivity.SoundLevelInterrupt == ENABLE) ? + (MDF_DFLTIER_SDLVLIE | MDF_DFLTIER_SDDETIE) : + MDF_DFLTIER_SDDETIE; + } + + /* Configure filter and start acquisition */ + hmdf->Instance->DFLTCR = 0U; + MDF_AcqStart(hmdf, pFilterConfig); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to stop acquisition in interrupt mode. + * @param hmdf MDF handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_AcqStop_IT(MDF_HandleTypeDef *hmdf) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check state */ + if (hmdf->State != HAL_MDF_STATE_ACQUISITION) + { + /* Check if state is ready and filter active */ + if (hmdf->State == HAL_MDF_STATE_READY) + { + if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != MDF_DFLTCR_DFLTACTIVE) + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + } + else + { + /* Disable sound activity detector if needed */ + if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U) + { + hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN); + } + } + + if (status == HAL_OK) + { + /* Disable filter */ + hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN); + + /* Disable interrupts and clear all potential pending flags */ + hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_FTHIE | MDF_DFLTIER_DOVRIE | MDF_DFLTIER_SATIE | + MDF_DFLTIER_RFOVRIE | MDF_DFLTIER_SDDETIE | MDF_DFLTIER_SDLVLIE); + hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF | + MDF_DFLTISR_SDDETF | MDF_DFLTISR_SDLVLF); + + /* Update state */ + hmdf->State = HAL_MDF_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to start acquisition in DMA mode. + * @param hmdf MDF handle. + * @param pFilterConfig Filter configuration parameters. + * @param pDmaConfig DMA configuration parameters. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig, + const MDF_DmaConfigTypeDef *pDmaConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + if ((pFilterConfig == NULL) || (pDmaConfig == NULL)) + { + status = HAL_ERROR; + } + else + { + assert_param(IS_FUNCTIONAL_STATE(pDmaConfig->MsbOnly)); + assert_param(IS_MDF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode)); + assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation)); + if ((pFilterConfig->SoundActivity.Activation == ENABLE) && + ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE) || + (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SINGLE) || + (pFilterConfig->AcquisitionMode == MDF_MODE_WINDOW_CONT))) + { + status = HAL_ERROR; + } + /* Check state */ + else if (hmdf->State != HAL_MDF_STATE_READY) + { + status = HAL_ERROR; + } + /* Check filter status */ + else if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Check SAD status */ + if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U) + { + status = HAL_ERROR; + } + } + + if (status == HAL_OK) + { + uint32_t SrcAddress; + + if (pFilterConfig->ReshapeFilter.Activation == ENABLE) + { + /* Enable reshape filter overrun interrupt */ + hmdf->Instance->DFLTIER |= MDF_DFLTIER_RFOVRIE; + } + + /* Enable saturation interrupt */ + hmdf->Instance->DFLTIER |= MDF_DFLTIER_SATIE; + + if (pFilterConfig->SoundActivity.Activation == ENABLE) + { + /* Enable sound level value ready and sound activity detection interrupts */ + assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.SoundLevelInterrupt)); + hmdf->Instance->DFLTIER |= (pFilterConfig->SoundActivity.SoundLevelInterrupt == ENABLE) ? + (MDF_DFLTIER_SDLVLIE | MDF_DFLTIER_SDDETIE) : + MDF_DFLTIER_SDDETIE; + } + + /* Enable MDF DMA requests */ + hmdf->Instance->DFLTCR = MDF_DFLTCR_DMAEN; + + /* Start DMA transfer */ + hmdf->hdma->XferCpltCallback = MDF_DmaXferCpltCallback; + hmdf->hdma->XferHalfCpltCallback = MDF_DmaXferHalfCpltCallback; + hmdf->hdma->XferErrorCallback = MDF_DmaErrorCallback; + SrcAddress = (pDmaConfig->MsbOnly == ENABLE) ? (((uint32_t) &hmdf->Instance->DFLTDR) + 2U) : + (uint32_t) &hmdf->Instance->DFLTDR; + if ((hmdf->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hmdf->hdma->LinkedListQueue != NULL) + { + hmdf->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = pDmaConfig->DataLength; + hmdf->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = SrcAddress; + hmdf->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pDmaConfig->Address; + + status = HAL_DMAEx_List_Start_IT(hmdf->hdma); + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hmdf->hdma, SrcAddress, pDmaConfig->Address, pDmaConfig->DataLength); + } + if (status != HAL_OK) + { + /* Update state */ + hmdf->State = HAL_MDF_STATE_ERROR; + status = HAL_ERROR; + } + else + { + /* Configure filter and start acquisition */ + MDF_AcqStart(hmdf, pFilterConfig); + } + } + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to stop acquisition in DMA mode. + * @param hmdf MDF handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_AcqStop_DMA(MDF_HandleTypeDef *hmdf) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check if state is ready and filter active */ + if (hmdf->State == HAL_MDF_STATE_READY) + { + if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != MDF_DFLTCR_DFLTACTIVE) + { + status = HAL_ERROR; + } + } + else + { + /* Check state */ + if (hmdf->State != HAL_MDF_STATE_ACQUISITION) + { + status = HAL_ERROR; + } + else + { + /* Stop the DMA transfer */ + if (HAL_DMA_Abort(hmdf->hdma) != HAL_OK) + { + /* Update state */ + hmdf->State = HAL_MDF_STATE_ERROR; + status = HAL_ERROR; + } + } + } + + if (status == HAL_OK) + { + /* Disable sound activity detector if needed */ + if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U) + { + hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN); + } + + /* Disable filter */ + hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN); + + /* Disable interrupts and clear all potential pending flags */ + hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_SATIE | MDF_DFLTIER_RFOVRIE | MDF_DFLTIER_SDDETIE | + MDF_DFLTIER_SDLVLIE); + hmdf->Instance->DFLTISR |= (MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF | MDF_DFLTISR_SDDETF | + MDF_DFLTISR_SDLVLF); + + /* Disable MDF DMA requests */ + hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DMAEN); + + /* Update state */ + hmdf->State = HAL_MDF_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to generate pulse on TRGO signal. + * @param hmdf MDF handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_GenerateTrgo(const MDF_HandleTypeDef *hmdf) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check state */ + if (hmdf->State != HAL_MDF_STATE_READY) + { + if (hmdf->State != HAL_MDF_STATE_ACQUISITION) + { + status = HAL_ERROR; + } + } + + if (status == HAL_OK) + { + /* Check if trigger output control is already active */ + if ((ADF1->GCR & MDF_GCR_TRGO) == MDF_GCR_TRGO) + { + status = HAL_ERROR; + } + else + { + /* Generate pulse on trigger output control signal */ + ADF1->GCR |= MDF_GCR_TRGO; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to set delay to apply on data source in number of samples. + * @param hmdf MDF handle. + * @param Delay Delay to apply on data source in number of samples. + * This parameter must be a number between Min_Data = 0 and Max_Data = 127. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_SetDelay(MDF_HandleTypeDef *hmdf, uint32_t Delay) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_MDF_DELAY(Delay)); + + /* Check state */ + if (hmdf->State != HAL_MDF_STATE_ACQUISITION) + { + status = HAL_ERROR; + } + else + { + /* Check if bitstream delay is already active */ + if ((hmdf->Instance->DLYCR & MDF_DLYCR_SKPBF) == MDF_DLYCR_SKPBF) + { + status = HAL_ERROR; + } + else + { + /* Configure bitstream delay */ + hmdf->Instance->DLYCR |= Delay; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to get current delay applied on data source in number of samples. + * @param hmdf MDF handle. + * @param pDelay Current delay applied on data source in number of samples. + * This value is between Min_Data = 0 and Max_Data = 127. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_GetDelay(const MDF_HandleTypeDef *hmdf, uint32_t *pDelay) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + if (pDelay == NULL) + { + status = HAL_ERROR; + } + /* Check state */ + else if (hmdf->State != HAL_MDF_STATE_ACQUISITION) + { + status = HAL_ERROR; + } + else + { + /* Get current bitstream delay */ + *pDelay = (hmdf->Instance->DLYCR & MDF_DLYCR_SKPDLY); + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to set filter gain. + * @param hmdf MDF handle. + * @param Gain Filter gain in step of around 3db (from -48db to 72dB). + * This parameter must be a number between Min_Data = -16 and Max_Data = 24. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_SetGain(MDF_HandleTypeDef *hmdf, int32_t Gain) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_MDF_GAIN(Gain)); + + /* Check state */ + if (hmdf->State != HAL_MDF_STATE_ACQUISITION) + { + status = HAL_ERROR; + } + else + { + uint32_t register_gain_value; + uint32_t tmp_register; + + if (Gain < 0) + { + int32_t adjust_gain; + + /* adjust gain value to set on register for negative value (offset of -16) */ + adjust_gain = Gain - 16; + register_gain_value = ((uint32_t) adjust_gain & 0x3FU); + } + else + { + /* for positive value, no offset to apply */ + register_gain_value = (uint32_t) Gain; + } + /* Set gain */ + tmp_register = (hmdf->Instance->DFLTCICR & ~(MDF_DFLTCICR_SCALE)); + hmdf->Instance->DFLTCICR = (tmp_register | (register_gain_value << MDF_DFLTCICR_SCALE_Pos)); + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to get filter gain. + * @param hmdf MDF handle. + * @param pGain Filter gain in step of around 3db (from -48db to 72dB). + * This parameter is between Min_Data = -16 and Max_Data = 24. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_GetGain(const MDF_HandleTypeDef *hmdf, int32_t *pGain) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + if (pGain == NULL) + { + status = HAL_ERROR; + } + /* Check state */ + else if (hmdf->State != HAL_MDF_STATE_ACQUISITION) + { + status = HAL_ERROR; + } + else + { + uint32_t register_gain_value; + + /* Get current gain */ + register_gain_value = ((hmdf->Instance->DFLTCICR & MDF_DFLTCICR_SCALE) >> MDF_DFLTCICR_SCALE_Pos); + if (register_gain_value > 31U) + { + /* adjust gain value to set on register for negative value (offset of +16) */ + register_gain_value |= 0xFFFFFFC0U; + *pGain = (int32_t) register_gain_value + 16; + } + else + { + /* for positive value, no offset to apply */ + *pGain = (int32_t) register_gain_value; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to poll for sound level data. + * @param hmdf MDF handle. + * @param Timeout Timeout value in milliseconds. + * @param pSoundLevel Sound level. + This parameter can be a value between Min_Data = 0 and Max_Data = 32767. + * @param pAmbientNoise Ambient noise. + This parameter can be a value between Min_Data = 0 and Max_Data = 32767. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_PollForSndLvl(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pSoundLevel, + uint32_t *pAmbientNoise) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + if ((pSoundLevel == NULL) || (pAmbientNoise == NULL)) + { + status = HAL_ERROR; + } + /* Check state */ + else if (hmdf->State != HAL_MDF_STATE_ACQUISITION) + { + status = HAL_ERROR; + } + /* Check SAD status */ + else if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) == 0U) + { + status = HAL_ERROR; + } + else + { + uint32_t tickstart = HAL_GetTick(); + + /* Wait for available sound level data */ + while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SDLVLF) != MDF_DFLTISR_SDLVLF) && (status == HAL_OK)) + { + /* Check the timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + status = HAL_TIMEOUT; + } + } + } + + if (status == HAL_OK) + { + /* Get sound level */ + *pSoundLevel = hmdf->Instance->SADSDLVR; + + /* Get ambient noise */ + *pAmbientNoise = hmdf->Instance->SADANLVR; + + /* Clear sound level ready flag */ + hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDLVLF; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to poll for sound activity detection. + * @param hmdf MDF handle. + * @param Timeout Timeout value in milliseconds. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_PollForSad(MDF_HandleTypeDef *hmdf, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check state */ + if (hmdf->State != HAL_MDF_STATE_ACQUISITION) + { + status = HAL_ERROR; + } + /* Check SAD status */ + else if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) == 0U) + { + status = HAL_ERROR; + } + else + { + uint32_t tickstart = HAL_GetTick(); + + /* Wait for sound activity detection */ + while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SDDETF) != MDF_DFLTISR_SDDETF) && (status == HAL_OK)) + { + /* Check the timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + status = HAL_TIMEOUT; + } + } + } + + if (status == HAL_OK) + { + /* Clear sound activity detection flag */ + hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDDETF; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief MDF acquisition complete callback. + * @param hmdf MDF handle. + * @retval None. + */ +__weak void HAL_MDF_AcqCpltCallback(MDF_HandleTypeDef *hmdf) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdf); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_MDF_AcqCpltCallback could be implemented in the user file */ +} + +/** + * @brief MDF acquisition half complete callback. + * @param hmdf MDF handle. + * @retval None. + */ +__weak void HAL_MDF_AcqHalfCpltCallback(MDF_HandleTypeDef *hmdf) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdf); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_MDF_AcqHalfCpltCallback could be implemented in the user file */ +} + +/** + * @brief MDF sound level callback. + * @param hmdf MDF handle. + * @param SoundLevel Sound level value computed by sound activity detector. + * This parameter can be a value between Min_Data = 0 and Max_Data = 32767. + * @param AmbientNoise Ambient noise value computed by sound activity detector. + * This parameter can be a value between Min_Data = 0 and Max_Data = 32767. + * @retval None. + */ +__weak void HAL_MDF_SndLvlCallback(MDF_HandleTypeDef *hmdf, uint32_t SoundLevel, uint32_t AmbientNoise) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdf); + UNUSED(SoundLevel); + UNUSED(AmbientNoise); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_MDF_SndLvlCallback could be implemented in the user file */ +} + +/** + * @brief MDF sound activity detector callback. + * @param hmdf MDF handle. + * @retval None. + */ +__weak void HAL_MDF_SadCallback(MDF_HandleTypeDef *hmdf) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdf); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_MDF_SadCallback could be implemented in the user file */ +} + +/** + * @} + */ + +/** @defgroup MDF_Exported_Functions_Group3 Clock absence detection functions + * @brief Clock absence detection functions + * +@verbatim + ============================================================================== + ##### Clock absence detection functions ##### + ============================================================================== + [..] This section provides functions allowing to : + (+) Start and stop clock absence detection in interrupt mode. + (+) Detect clock absence. +@endverbatim + * @{ + */ + +/** + * @brief This function allows to poll for the clock absence detection. + * @param hmdf MDF handle. + * @param Timeout Timeout value in milliseconds. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_PollForCkab(MDF_HandleTypeDef *hmdf, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check state */ + if (hmdf->State != HAL_MDF_STATE_ACQUISITION) + { + if (hmdf->State != HAL_MDF_STATE_READY) + { + status = HAL_ERROR; + } + } + + if (status == HAL_OK) + { + /* Check serial interface status and mode */ + if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) == 0U) + { + status = HAL_ERROR; + } + else + { + if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFMOD) != MDF_SITF_NORMAL_SPI_MODE) + { + status = HAL_ERROR; + } + } + } + + if (status == HAL_OK) + { + uint32_t tickstart = HAL_GetTick(); + + /* Wait for clock absence detection */ + while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_CKABF) != MDF_DFLTISR_CKABF) && (status == HAL_OK)) + { + /* Check the timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + status = HAL_TIMEOUT; + } + } + } + + if (status == HAL_OK) + { + /* Clear clock absence detection flag */ + hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to start clock absence detection in interrupt mode. + * @param hmdf MDF handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_CkabStart_IT(MDF_HandleTypeDef *hmdf) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check state */ + if (hmdf->State != HAL_MDF_STATE_ACQUISITION) + { + if (hmdf->State != HAL_MDF_STATE_READY) + { + status = HAL_ERROR; + } + } + + if (status == HAL_OK) + { + /* Check serial interface status and mode */ + if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) == 0U) + { + status = HAL_ERROR; + } + else + { + if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFMOD) != MDF_SITF_NORMAL_SPI_MODE) + { + status = HAL_ERROR; + } + } + } + + if (status == HAL_OK) + { + /* Clear clock absence detection flag */ + hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF; + + /* Check clock absence detection flag */ + if ((hmdf->Instance->DFLTISR & MDF_DFLTISR_CKABF) == MDF_DFLTISR_CKABF) + { + status = HAL_ERROR; + } + else + { + /* Enable clock absence detection interrupt */ + hmdf->Instance->DFLTIER |= MDF_DFLTIER_CKABIE; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief This function allows to stop clock absence detection in interrupt mode. + * @param hmdf MDF handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_MDF_CkabStop_IT(MDF_HandleTypeDef *hmdf) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check state */ + if (hmdf->State != HAL_MDF_STATE_ACQUISITION) + { + if (hmdf->State != HAL_MDF_STATE_READY) + { + status = HAL_ERROR; + } + } + + if (status == HAL_OK) + { + /* Check serial interface status and mode */ + if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) == 0U) + { + status = HAL_ERROR; + } + else + { + if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFMOD) != MDF_SITF_NORMAL_SPI_MODE) + { + status = HAL_ERROR; + } + } + } + + if (status == HAL_OK) + { + /* Disable clock absence detection interrupt */ + hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_CKABIE); + + /* Clear potential pending clock absence detection flag */ + hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF; + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup MDF_Exported_Functions_Group4 Generic functions + * @brief Generic functions + * +@verbatim + ============================================================================== + ##### Generic functions ##### + ============================================================================== + [..] This section provides functions allowing to : + (+) Handle MDF interrupt. + (+) Inform user that error occurs. + (+) Get the current MDF instance state. + (+) Get the current MDF instance error code. +@endverbatim + * @{ + */ + +/** + * @brief This function handles the MDF interrupts. + * @param hmdf MDF handle. + * @retval None. + */ +void HAL_MDF_IRQHandler(MDF_HandleTypeDef *hmdf) +{ + uint32_t tmp_reg1; + uint32_t tmp_reg2; + uint32_t interrupts; + + /* Read current flags and interrupts and determine which ones occur */ + tmp_reg1 = hmdf->Instance->DFLTIER; + tmp_reg2 = hmdf->Instance->DFLTISR; + interrupts = (tmp_reg1 & tmp_reg2); + + /* Check if data overflow occurs */ + if ((interrupts & MDF_DFLTISR_DOVRF) == MDF_DFLTISR_DOVRF) + { + /* Clear data overflow flag */ + hmdf->Instance->DFLTISR |= MDF_DFLTISR_DOVRF; + + /* Update error code */ + hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW; + + /* Call error callback */ +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) + hmdf->ErrorCallback(hmdf); +#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ + HAL_MDF_ErrorCallback(hmdf); +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ + } + /* Check if RXFIFO threshold occurs */ + else if ((interrupts & MDF_DFLTISR_FTHF) == MDF_DFLTISR_FTHF) + { + /* Call acquisition complete callback */ +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) + hmdf->AcqCpltCallback(hmdf); +#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ + HAL_MDF_AcqCpltCallback(hmdf); +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ + + /* Update state only in asynchronous single shot mode */ + if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_ACQMOD) == MDF_MODE_ASYNC_SINGLE) + { + hmdf->State = HAL_MDF_STATE_READY; + } + } + /* Check if reshape filter overrun occurs */ + else if ((interrupts & MDF_DFLTISR_RFOVRF) == MDF_DFLTISR_RFOVRF) + { + /* Clear reshape filter overrun flag */ + hmdf->Instance->DFLTISR |= MDF_DFLTISR_RFOVRF; + + /* Update error code */ + hmdf->ErrorCode |= MDF_ERROR_RSF_OVERRUN; + + /* Call error callback */ +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) + hmdf->ErrorCallback(hmdf); +#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ + HAL_MDF_ErrorCallback(hmdf); +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ + } + /* Check if clock absence detection occurs */ + else if ((interrupts & MDF_DFLTISR_CKABF) == MDF_DFLTISR_CKABF) + { + /* Clear clock absence detection flag */ + hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF; + + /* Update error code */ + hmdf->ErrorCode |= MDF_ERROR_CLOCK_ABSENCE; + + /* Call error callback */ +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) + hmdf->ErrorCallback(hmdf); +#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ + HAL_MDF_ErrorCallback(hmdf); +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ + } + /* Check if saturation occurs */ + else if ((interrupts & MDF_DFLTISR_SATF) == MDF_DFLTISR_SATF) + { + /* Clear saturation flag */ + hmdf->Instance->DFLTISR |= MDF_DFLTISR_SATF; + + /* Update error code */ + hmdf->ErrorCode |= MDF_ERROR_SATURATION; + + /* Call error callback */ +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) + hmdf->ErrorCallback(hmdf); +#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ + HAL_MDF_ErrorCallback(hmdf); +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ + } + /* Check if sound activity detection occurs */ + else if ((interrupts & MDF_DFLTISR_SDDETF) == MDF_DFLTISR_SDDETF) + { + /* Clear sound activity detection flag */ + hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDDETF; + + /* Call sound activity detection callback */ +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) + hmdf->SadCallback(hmdf); +#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ + HAL_MDF_SadCallback(hmdf); +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ + } + else + { + /* Check if sound level ready occurs */ + if ((interrupts & MDF_DFLTISR_SDLVLF) == MDF_DFLTISR_SDLVLF) + { + uint32_t sound_level; + uint32_t ambient_noise; + + /* Get sound level */ + sound_level = hmdf->Instance->SADSDLVR; + + /* Get ambient noise */ + ambient_noise = hmdf->Instance->SADANLVR; + + /* Clear sound level ready flag */ + hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDLVLF; + + /* Call sound level callback */ +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) + hmdf->SndLvCallback(hmdf, sound_level, ambient_noise); +#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ + HAL_MDF_SndLvlCallback(hmdf, sound_level, ambient_noise); +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief MDF error callback. + * @param hmdf MDF handle. + * @retval None. + */ +__weak void HAL_MDF_ErrorCallback(MDF_HandleTypeDef *hmdf) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdf); + + /* NOTE : This function should not be modified, when the function is needed, + the HAL_MDF_ErrorCallback could be implemented in the user file */ +} + +/** + * @brief This function allows to get the current MDF state. + * @param hmdf MDF handle. + * @retval MDF state. + */ +HAL_MDF_StateTypeDef HAL_MDF_GetState(const MDF_HandleTypeDef *hmdf) +{ + /* Return MDF state */ + return hmdf->State; +} + +/** + * @brief This function allows to get the current MDF error. + * @param hmdf MDF handle. + * @retval MDF error code. + */ +uint32_t HAL_MDF_GetError(const MDF_HandleTypeDef *hmdf) +{ + /* Return MDF error code */ + return hmdf->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup MDF_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief This function allows to configure filter and start acquisition. + * @param hmdf MDF handle. + * @param pFilterConfig Filter configuration parameters. + * @retval None. + */ +static void MDF_AcqStart(MDF_HandleTypeDef *const hmdf, const MDF_FilterConfigTypeDef *const pFilterConfig) +{ + uint32_t register_gain_value; + + /* Configure acquisition mode, discard samples, trigger and fifo threshold */ + assert_param(IS_MDF_DISCARD_SAMPLES(pFilterConfig->DiscardSamples)); + assert_param(IS_MDF_FIFO_THRESHOLD(pFilterConfig->FifoThreshold)); + if ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_CONT) || + (pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE)) + { + /* Trigger parameters are not used */ + hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold | + (pFilterConfig->DiscardSamples << MDF_DFLTCR_NBDIS_Pos)); + } + else + { + /* Trigger parameters are used */ + assert_param(IS_MDF_TRIGGER_SOURCE(pFilterConfig->Trigger.Source)); + assert_param(IS_MDF_TRIGGER_EDGE(pFilterConfig->Trigger.Edge)); + hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold | + pFilterConfig->Trigger.Source | pFilterConfig->Trigger.Edge | + (pFilterConfig->DiscardSamples << MDF_DFLTCR_NBDIS_Pos)); + } + + /* Configure data source, CIC mode, decimation ratio and gain */ + assert_param(IS_MDF_DATA_SOURCE(pFilterConfig->DataSource)); + assert_param(IS_MDF_CIC_MODE(pFilterConfig->CicMode)); + assert_param(IS_MDF_DECIMATION_RATIO(pFilterConfig->DecimationRatio)); + assert_param(IS_MDF_GAIN(pFilterConfig->Gain)); + if (pFilterConfig->Gain < 0) + { + int32_t adjust_gain; + + /* adjust gain value to set on register for negative value (offset of -16) */ + adjust_gain = pFilterConfig->Gain - 16; + register_gain_value = ((uint32_t) adjust_gain & 0x3FU); + } + else + { + /* for positive value, no offset to apply */ + register_gain_value = (uint32_t) pFilterConfig->Gain; + } + hmdf->Instance->DFLTCICR = (pFilterConfig->DataSource | pFilterConfig->CicMode | + ((pFilterConfig->DecimationRatio - 1U) << MDF_DFLTCICR_MCICD_Pos) | + (register_gain_value << MDF_DFLTCICR_SCALE_Pos)); + + /* Configure bitstream delay */ + assert_param(IS_MDF_DELAY(pFilterConfig->Delay)); + hmdf->Instance->DLYCR = pFilterConfig->Delay; + + /* Configure reshape filter */ + assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->ReshapeFilter.Activation)); + hmdf->Instance->DFLTRSFR = 0U; + if (pFilterConfig->ReshapeFilter.Activation == ENABLE) + { + /* Configure reshape filter decimation ratio */ + assert_param(IS_MDF_RSF_DECIMATION_RATIO(pFilterConfig->ReshapeFilter.DecimationRatio)); + hmdf->Instance->DFLTRSFR |= pFilterConfig->ReshapeFilter.DecimationRatio; + } + else + { + /* Bypass reshape filter */ + hmdf->Instance->DFLTRSFR |= MDF_DFLTRSFR_RSFLTBYP; + } + + /* Configure high-pass filter */ + assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->HighPassFilter.Activation)); + if (pFilterConfig->HighPassFilter.Activation == ENABLE) + { + /* Configure high-pass filter cut-off frequency */ + assert_param(IS_MDF_HPF_CUTOFF_FREQ(pFilterConfig->HighPassFilter.CutOffFrequency)); + hmdf->Instance->DFLTRSFR |= pFilterConfig->HighPassFilter.CutOffFrequency; + } + else + { + /* Bypass high-pass filter */ + hmdf->Instance->DFLTRSFR |= MDF_DFLTRSFR_HPFBYP; + } + + assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation)); + if (pFilterConfig->SoundActivity.Activation == ENABLE) + { + /* Configure SAD mode, frame size, hysteresis, sound trigger event + and data memory transfer only for ADF instance */ + assert_param(IS_MDF_SAD_MODE(pFilterConfig->SoundActivity.Mode)); + assert_param(IS_MDF_SAD_FRAME_SIZE(pFilterConfig->SoundActivity.FrameSize)); + if (pFilterConfig->SoundActivity.Mode != MDF_SAD_AMBIENT_NOISE_DETECTOR) + { + assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Hysteresis)); + } + assert_param(IS_MDF_SAD_SOUND_TRIGGER(pFilterConfig->SoundActivity.SoundTriggerEvent)); + assert_param(IS_MDF_SAD_DATA_MEMORY_TRANSFER(pFilterConfig->SoundActivity.DataMemoryTransfer)); + if ((pFilterConfig->SoundActivity.Mode != MDF_SAD_AMBIENT_NOISE_DETECTOR) && + (pFilterConfig->SoundActivity.Hysteresis == ENABLE)) + { + hmdf->Instance->SADCR = (pFilterConfig->SoundActivity.Mode | pFilterConfig->SoundActivity.FrameSize | + MDF_SADCR_HYSTEN | pFilterConfig->SoundActivity.SoundTriggerEvent | + pFilterConfig->SoundActivity.DataMemoryTransfer); + } + else + { + hmdf->Instance->SADCR = (pFilterConfig->SoundActivity.Mode | pFilterConfig->SoundActivity.FrameSize | + pFilterConfig->SoundActivity.SoundTriggerEvent | + pFilterConfig->SoundActivity.DataMemoryTransfer); + } + + /* Configure SAD minimum noise level, hangover window, learning frames, + ambient noise slope control and signal noise threshold only for ADF instance */ + assert_param(IS_MDF_SAD_MIN_NOISE_LEVEL(pFilterConfig->SoundActivity.MinNoiseLevel)); + assert_param(IS_MDF_SAD_HANGOVER_WINDOW(pFilterConfig->SoundActivity.HangoverWindow)); + assert_param(IS_MDF_SAD_LEARNING_FRAMES(pFilterConfig->SoundActivity.LearningFrames)); + assert_param(IS_MDF_SAD_SIGNAL_NOISE_THRESHOLD(pFilterConfig->SoundActivity.SignalNoiseThreshold)); + if (pFilterConfig->SoundActivity.Mode != MDF_SAD_SOUND_DETECTOR) + { + assert_param(IS_MDF_SAD_AMBIENT_NOISE_SLOPE(pFilterConfig->SoundActivity.AmbientNoiseSlope)); + hmdf->Instance->SADCFGR = ((pFilterConfig->SoundActivity.MinNoiseLevel << MDF_SADCFGR_ANMIN_Pos) | + pFilterConfig->SoundActivity.HangoverWindow | + pFilterConfig->SoundActivity.LearningFrames | + (pFilterConfig->SoundActivity.AmbientNoiseSlope << MDF_SADCFGR_ANSLP_Pos) | + pFilterConfig->SoundActivity.SignalNoiseThreshold); + } + else + { + hmdf->Instance->SADCFGR = ((pFilterConfig->SoundActivity.MinNoiseLevel << MDF_SADCFGR_ANMIN_Pos) | + pFilterConfig->SoundActivity.HangoverWindow | + pFilterConfig->SoundActivity.LearningFrames | + pFilterConfig->SoundActivity.SignalNoiseThreshold); + } + } + else + { + /* SAD is not used */ + hmdf->Instance->SADCR = 0U; + hmdf->Instance->SADCFGR = 0U; + } + + /* Update instance state */ + hmdf->State = HAL_MDF_STATE_ACQUISITION; + + /* Enable sound activity detector if needed */ + if (pFilterConfig->SoundActivity.Activation == ENABLE) + { + hmdf->Instance->SADCR |= MDF_SADCR_SADEN; + } + + /* Enable filter */ + hmdf->Instance->DFLTCR |= MDF_DFLTCR_DFLTEN; +} + +/** + * @brief This function handles DMA transfer complete callback. + * @param hdma DMA handle. + * @retval None. + */ +static void MDF_DmaXferCpltCallback(DMA_HandleTypeDef *hdma) +{ + MDF_HandleTypeDef *hmdf = (MDF_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + hmdf->State = HAL_MDF_STATE_READY; + } + +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) + hmdf->AcqCpltCallback(hmdf); +#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ + HAL_MDF_AcqCpltCallback(hmdf); +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ +} + +/** + * @brief This function handles DMA half transfer complete callback. + * @param hdma DMA handle. + * @retval None. + */ +static void MDF_DmaXferHalfCpltCallback(DMA_HandleTypeDef *hdma) +{ + MDF_HandleTypeDef *hmdf = (MDF_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) + hmdf->AcqHalfCpltCallback(hmdf); +#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ + HAL_MDF_AcqHalfCpltCallback(hmdf); +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ +} + +/** + * @brief This function handles DMA error callback. + * @param hdma DMA handle. + * @retval None. + */ +static void MDF_DmaErrorCallback(DMA_HandleTypeDef *hdma) +{ + MDF_HandleTypeDef *hmdf = (MDF_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Update error code */ + hmdf->ErrorCode |= MDF_ERROR_DMA; + +#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) + hmdf->ErrorCallback(hmdf); +#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ + HAL_MDF_ErrorCallback(hmdf); +#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ +} + +/** + * @} + */ + +#endif /* HAL_MDF_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mdios.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mdios.c new file mode 100644 index 00000000000..dc2038a992b --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mdios.c @@ -0,0 +1,921 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_mdios.c + * @author MCD Application Team + * @brief MDIOS HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the MDIOS Peripheral. + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The MDIOS HAL driver can be used as follow: + + (#) Declare a MDIOS_HandleTypeDef handle structure. + + (#) Initialize the MDIOS low level resources by implementing the HAL_MDIOS_MspInit() API: + (##) Enable the MDIOS interface clock. + (##) MDIOS pins configuration: + (+++) Enable clocks for the MDIOS GPIOs. + (+++) Configure the MDIOS pins as alternate function. + (##) NVIC configuration if you need to use interrupt process: + (+++) Configure the MDIOS interrupt priority. + (+++) Enable the NVIC MDIOS IRQ handle. + + (#) Program the Port Address and the Preamble Check in the Init structure. + + (#) Initialize the MDIOS registers by calling the HAL_MDIOS_Init() API. + + (#) Perform direct slave read/write operations using the following APIs: + (##) Read the value of a DINn register: HAL_MDIOS_ReadReg() + (##) Write a value to a DOUTn register: HAL_MDIOS_WriteReg() + + (#) Get the Master read/write operations flags using the following APIs: + (##) Bit map of DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress() + (##) Bit map of DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress() + + (#) Clear the read/write flags using the following APIs: + (##) Clear read flags of a set of registers: HAL_MDIOS_ClearReadRegAddress() + (##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress() + + (#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called + the MDIOS will generate an interrupt in the following cases: + (##) a DINn register written by the Master + (##) a DOUTn register read by the Master + (##) an error occur + + (@) A callback is executed for each generated interrupt, so the driver provide the following + HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback() + (@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt + and execute the previous callbacks + + (#) Reset the MDIOS peripheral and all related resources by calling the HAL_MDIOS_DeInit() API. + (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level resources + (GPIO, Clocks, NVIC configuration ...) + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_MDIOS_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_MDIOS_RegisterCallback() to register an interrupt callback. + + Function @ref HAL_MDIOS_RegisterCallback() allows to register following callbacks: + (+) WriteCpltCallback : Write Complete Callback. + (+) ReadCpltCallback : Read Complete Callback. + (+) ErrorCallback : Error Callback. + (+) WakeUpCallback : Wake UP Callback + (+) MspInitCallback : MspInit Callback. + (+) MspDeInitCallback : MspDeInit Callback. + + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_MDIOS_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_MDIOS_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) WriteCpltCallback : Write Complete Callback. + (+) ReadCpltCallback : Read Complete Callback. + (+) ErrorCallback : Error Callback. + (+) WakeUpCallback : Wake UP Callback + (+) MspInitCallback : MspInit Callback. + (+) MspDeInitCallback : MspDeInit Callback. + + By default, after the HAL_MDIOS_Init and when the state is HAL_MDIOS_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_MDIOS_WriteCpltCallback(), @ref HAL_MDIOS_ReadCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_MDIOS_Init/ @ref HAL_MDIOS_DeInit only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_MDIOS_Init/ @ref HAL_MDIOS_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_MDIOS_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_MDIOS_STATE_READY or HAL_MDIOS_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_MDIOS_RegisterCallback() before calling @ref HAL_MDIOS_DeInit + or HAL_MDIOS_Init function. + + When The compilation define USE_HAL_MDIOS_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#if defined (MDIOS) +/** @defgroup MDIOS MDIOS + * @brief HAL MDIOS module driver + * @{ + */ +#ifdef HAL_MDIOS_MODULE_ENABLED + + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8) +#define MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU) +#define MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF)) + +#define MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100U) +#define MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180U) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) +static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios); +#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions + * @{ + */ + +/** @defgroup MDIOS_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the MDIOS + (+) The following parameters can be configured: + (++) Port Address + (++) Preamble Check + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the MDIOS according to the specified parameters in + * the MDIOS_InitTypeDef and creates the associated handle . + * @param hmdios: pointer to a MDIOS_HandleTypeDef structure that contains + * the configuration information for MDIOS module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios) +{ + uint32_t tmpcr; + + /* Check the MDIOS handle allocation */ + if (hmdios == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance)); + assert_param(IS_MDIOS_PORTADDRESS(hmdios->Init.PortAddress)); + assert_param(IS_MDIOS_PREAMBLECHECK(hmdios->Init.PreambleCheck)); + +#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) + + if (hmdios->State == HAL_MDIOS_STATE_RESET) + { + MDIOS_InitCallbacksToDefault(hmdios); + + if (hmdios->MspInitCallback == NULL) + { + hmdios->MspInitCallback = HAL_MDIOS_MspInit; + } + + /* Init the low level hardware */ + hmdios->MspInitCallback(hmdios); + } + +#else + + if (hmdios->State == HAL_MDIOS_STATE_RESET) + { + /* Init the low level hardware */ + HAL_MDIOS_MspInit(hmdios); + } + +#endif /* (USE_HAL_MDIOS_REGISTER_CALLBACKS) */ + + /* Change the MDIOS state */ + hmdios->State = HAL_MDIOS_STATE_BUSY; + + /* Get the MDIOS CR value */ + tmpcr = hmdios->Instance->CR; + + /* Clear PORT_ADDRESS, DPC and EN bits */ + tmpcr &= ((uint32_t)~(MDIOS_CR_EN | MDIOS_CR_DPC | MDIOS_CR_PORT_ADDRESS)); + + /* Set MDIOS control parameters and enable the peripheral */ + tmpcr |= (uint32_t)(((hmdios->Init.PortAddress) << MDIOS_PORT_ADDRESS_SHIFT) | \ + (hmdios->Init.PreambleCheck) | \ + (MDIOS_CR_EN)); + + /* Write the MDIOS CR */ + hmdios->Instance->CR = tmpcr; + + hmdios->ErrorCode = HAL_MDIOS_ERROR_NONE; + + /* Change the MDIOS state */ + hmdios->State = HAL_MDIOS_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(hmdios); + + /* Return function status */ + return HAL_OK; + +} + +/** + * @brief DeInitializes the MDIOS peripheral. + * @param hmdios: MDIOS handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios) +{ + /* Check the MDIOS handle allocation */ + if (hmdios == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance)); + + /* Change the MDIOS state */ + hmdios->State = HAL_MDIOS_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_MDIOS_DISABLE(hmdios); + +#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) + + if (hmdios->MspDeInitCallback == NULL) + { + hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit; + } + /* DeInit the low level hardware */ + hmdios->MspDeInitCallback(hmdios); +#else + + /* DeInit the low level hardware */ + HAL_MDIOS_MspDeInit(hmdios); + +#endif /* (USE_HAL_MDIOS_REGISTER_CALLBACKS) */ + + /* Change the MDIOS state */ + hmdios->State = HAL_MDIOS_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hmdios); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief MDIOS MSP Init + * @param hmdios: mdios handle + * @retval None + */ +__weak void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdios); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MDIOS_MspInit can be implemented in the user file + */ +} + +/** + * @brief MDIOS MSP DeInit + * @param hmdios: mdios handle + * @retval None + */ +__weak void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdios); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MDIOS_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User MDIOS Callback + * To be used instead of the weak predefined callback + * @param hmdios mdios handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_MDIOS_WRITE_COMPLETE_CB_ID Write Complete Callback ID + * @arg @ref HAL_MDIOS_READ_COMPLETE_CB_ID Read Complete Callback ID + * @arg @ref HAL_MDIOS_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_MDIOS_WAKEUP_CB_ID Wake Up Callback ID + * @arg @ref HAL_MDIOS_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_MDIOS_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_MDIOS_RegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID, + pMDIOS_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hmdios); + + if (hmdios->State == HAL_MDIOS_STATE_READY) + { + switch (CallbackID) + { + case HAL_MDIOS_WRITE_COMPLETE_CB_ID : + hmdios->WriteCpltCallback = pCallback; + break; + + case HAL_MDIOS_READ_COMPLETE_CB_ID : + hmdios->ReadCpltCallback = pCallback; + break; + + case HAL_MDIOS_ERROR_CB_ID : + hmdios->ErrorCallback = pCallback; + break; + + case HAL_MDIOS_WAKEUP_CB_ID : + hmdios->WakeUpCallback = pCallback; + break; + + case HAL_MDIOS_MSPINIT_CB_ID : + hmdios->MspInitCallback = pCallback; + break; + + case HAL_MDIOS_MSPDEINIT_CB_ID : + hmdios->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hmdios->State == HAL_MDIOS_STATE_RESET) + { + switch (CallbackID) + { + case HAL_MDIOS_MSPINIT_CB_ID : + hmdios->MspInitCallback = pCallback; + break; + + case HAL_MDIOS_MSPDEINIT_CB_ID : + hmdios->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hmdios); + + return status; +} + +/** + * @brief Unregister an MDIOS Callback + * MDIOS callback is redirected to the weak predefined callback + * @param hmdios mdios handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_MDIOS_WRITE_COMPLETE_CB_ID Write Complete Callback ID + * @arg @ref HAL_MDIOS_READ_COMPLETE_CB_ID Read Complete Callback ID + * @arg @ref HAL_MDIOS_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_MDIOS_WAKEUP_CB_ID Wake Up Callback ID + * @arg @ref HAL_MDIOS_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_MDIOS_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hmdios); + + if (hmdios->State == HAL_MDIOS_STATE_READY) + { + switch (CallbackID) + { + case HAL_MDIOS_WRITE_COMPLETE_CB_ID : + hmdios->WriteCpltCallback = HAL_MDIOS_WriteCpltCallback; + break; + + case HAL_MDIOS_READ_COMPLETE_CB_ID : + hmdios->ReadCpltCallback = HAL_MDIOS_ReadCpltCallback; + break; + + case HAL_MDIOS_ERROR_CB_ID : + hmdios->ErrorCallback = HAL_MDIOS_ErrorCallback; + break; + + case HAL_MDIOS_WAKEUP_CB_ID : + hmdios->WakeUpCallback = HAL_MDIOS_WakeUpCallback; + break; + + case HAL_MDIOS_MSPINIT_CB_ID : + hmdios->MspInitCallback = HAL_MDIOS_MspInit; + break; + + case HAL_MDIOS_MSPDEINIT_CB_ID : + hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit; + break; + + default : + /* Update the error code */ + hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hmdios->State == HAL_MDIOS_STATE_RESET) + { + switch (CallbackID) + { + case HAL_MDIOS_MSPINIT_CB_ID : + hmdios->MspInitCallback = HAL_MDIOS_MspInit; + break; + + case HAL_MDIOS_MSPDEINIT_CB_ID : + hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit; + break; + + default : + /* Update the error code */ + hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hmdios); + + return status; +} +#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup MDIOS_Exported_Functions_Group2 IO operation functions + * @brief MDIOS Read/Write functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the MDIOS + read and write operations. + + (#) APIs that allow to the MDIOS to read/write from/to the + values of one of the DINn/DOUTn registers: + (+) Read the value of a DINn register: HAL_MDIOS_ReadReg() + (+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg() + + (#) APIs that provide if there are some Slave registres have been + read or written by the Master: + (+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress() + (+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress() + + (#) APIs that Clear the read/write flags: + (+) Clear read registers flags: HAL_MDIOS_ClearReadRegAddress() + (+) Clear write registers flags: HAL_MDIOS_ClearWriteRegAddress() + + (#) A set of Callbacks are provided: + (+) HAL_MDIOS_WriteCpltCallback() + (+) HAL_MDIOS_ReadCpltCallback() + (+) HAL_MDIOS_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Writes to an MDIOS output register + * @param hmdios: mdios handle + * @param RegNum: MDIOS output register address + * @param Data: Data to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_MDIOS_REGISTER(RegNum)); + + /* Process Locked */ + __HAL_LOCK(hmdios); + + /* Get the addr of output register to be written by the MDIOS */ + tmpreg = MDIOS_DOUT_BASE_ADDR + (4U * RegNum); + + /* Write to DOUTn register */ + *((uint32_t *)tmpreg) = Data; + + /* Process Unlocked */ + __HAL_UNLOCK(hmdios); + + return HAL_OK; +} + +/** + * @brief Reads an MDIOS input register + * @param hmdios: mdios handle + * @param RegNum: MDIOS input register address + * @param pData: pointer to Data + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_MDIOS_REGISTER(RegNum)); + + /* Process Locked */ + __HAL_LOCK(hmdios); + + /* Get the addr of input register to be read by the MDIOS */ + tmpreg = MDIOS_DIN_BASE_ADDR + (4U * RegNum); + + /* Read DINn register */ + *pData = (uint16_t)(*((uint32_t *)tmpreg)); + + /* Process Unlocked */ + __HAL_UNLOCK(hmdios); + + return HAL_OK; +} + +/** + * @brief Gets Written registers by MDIO master + * @param hmdios: mdios handle + * @retval bit map of written registers addresses + */ +uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios) +{ + return hmdios->Instance->WRFR; +} + +/** + * @brief Gets Read registers by MDIO master + * @param hmdios: mdios handle + * @retval bit map of read registers addresses + */ +uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios) +{ + return hmdios->Instance->RDFR; +} + +/** + * @brief Clears Write registers flag + * @param hmdios: mdios handle + * @param RegNum: registers addresses to be cleared + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum) +{ + /* Check the parameters */ + assert_param(IS_MDIOS_REGISTER(RegNum)); + + /* Process Locked */ + __HAL_LOCK(hmdios); + + /* Clear write registers flags */ + hmdios->Instance->CWRFR |= (RegNum); + + /* Release Lock */ + __HAL_UNLOCK(hmdios); + + return HAL_OK; +} + +/** + * @brief Clears Read register flag + * @param hmdios: mdios handle + * @param RegNum: registers addresses to be cleared + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum) +{ + /* Check the parameters */ + assert_param(IS_MDIOS_REGISTER(RegNum)); + + /* Process Locked */ + __HAL_LOCK(hmdios); + + /* Clear read registers flags */ + hmdios->Instance->CRDFR |= (RegNum); + + /* Release Lock */ + __HAL_UNLOCK(hmdios); + + return HAL_OK; +} + +/** + * @brief Enables Events for MDIOS peripheral + * @param hmdios: mdios handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios) +{ + /* Process Locked */ + __HAL_LOCK(hmdios); + + /* Enable MDIOS interrupts: Register Write, Register Read and Error ITs */ + __HAL_MDIOS_ENABLE_IT(hmdios, (MDIOS_IT_WRITE | MDIOS_IT_READ | MDIOS_IT_ERROR)); + + /* Process Unlocked */ + __HAL_UNLOCK(hmdios); + + return HAL_OK; +} + +/** + * @brief This function handles MDIOS interrupt request. + * @param hmdios: MDIOS handle + * @retval None + */ +void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios) +{ + /* Write Register Interrupt enabled ? */ + if (__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_WRITE) != (uint32_t)RESET) + { + /* Write register flag */ + if (HAL_MDIOS_GetWrittenRegAddress(hmdios) != (uint32_t)RESET) + { +#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) + /*Call registered Write complete callback*/ + hmdios->WriteCpltCallback(hmdios); +#else + /* Write callback function */ + HAL_MDIOS_WriteCpltCallback(hmdios); +#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ + + /* Clear write register flag */ + hmdios->Instance->CWRFR |= MDIOS_ALL_REG_FLAG; + } + } + + /* Read Register Interrupt enabled ? */ + if (__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != (uint32_t)RESET) + { + /* Read register flag */ + if (HAL_MDIOS_GetReadRegAddress(hmdios) != (uint32_t)RESET) + { +#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) + /*Call registered Read complete callback*/ + hmdios->ReadCpltCallback(hmdios); +#else + /* Read callback function */ + HAL_MDIOS_ReadCpltCallback(hmdios); +#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ + + /* Clear read register flag */ + hmdios->Instance->CRDFR |= MDIOS_ALL_REG_FLAG; + } + } + + /* Error Interrupt enabled ? */ + if (__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != (uint32_t)RESET) + { + /* All Errors Flag */ + if (__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) != (uint32_t)RESET) + { + hmdios->ErrorCode |= HAL_MDIOS_ERROR_DATA; + +#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) + /*Call registered Error callback*/ + hmdios->ErrorCallback(hmdios); +#else + /* Error Callback */ + HAL_MDIOS_ErrorCallback(hmdios); +#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ + + /* Clear errors flag */ + __HAL_MDIOS_CLEAR_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG); + } + hmdios->ErrorCode = HAL_MDIOS_ERROR_NONE; + } + /* check MDIOS WAKEUP exti flag */ + if (__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != (uint32_t)RESET) + { + /* Clear MDIOS WAKEUP Exti pending bit */ + __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE); +#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) + /*Call registered WakeUp callback*/ + hmdios->WakeUpCallback(hmdios); +#else + /* MDIOS WAKEUP callback */ + HAL_MDIOS_WakeUpCallback(hmdios); +#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ + } + +} + +/** + * @brief Write Complete Callback + * @param hmdios: mdios handle + * @retval None + */ +__weak void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdios); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MDIOS_WriteCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Read Complete Callback + * @param hmdios: mdios handle + * @retval None + */ +__weak void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdios); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MDIOS_ReadCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Error Callback + * @param hmdios: mdios handle + * @retval None + */ +__weak void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdios); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MDIOS_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief MDIOS WAKEUP interrupt callback + * @param hmdios: mdios handle + * @retval None + */ +__weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdios); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MDIOS_WakeUpCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup MDIOS_Exported_Functions_Group3 Peripheral Control functions + * @brief MDIOS control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the MDIOS. + (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state. + (+) HAL_MDIOS_GetError() API, returns the errors code of the HAL state machine. + +@endverbatim + * @{ + */ + +/** + * @brief Gets MDIOS error code + * @param hmdios: mdios handle + * @retval mdios error code + */ +uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios) +{ + /* return the error code */ + return hmdios->ErrorCode; +} + +/** + * @brief Return the MDIOS HAL state + * @param hmdios: mdios handle + * @retval HAL state + */ +HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios) +{ + /* Return MDIOS state */ + return hmdios->State; +} + +/** + * @} + */ + +/** + * @} + */ + +#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) +static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios) +{ + /* Init the MDIOS Callback settings */ + hmdios->WriteCpltCallback = HAL_MDIOS_WriteCpltCallback; /* Legacy weak WriteCpltCallback */ + hmdios->ReadCpltCallback = HAL_MDIOS_ReadCpltCallback; /* Legacy weak ReadCpltCallback */ + hmdios->ErrorCallback = HAL_MDIOS_ErrorCallback; /* Legacy weak ErrorCallback */ + hmdios->WakeUpCallback = HAL_MDIOS_WakeUpCallback; /* Legacy weak WakeUpCallback */ +} +#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ + +/** + * @} + */ +#endif /* HAL_MDIOS_MODULE_ENABLED */ +/** + * @} + */ +#endif /* MDIOS */ +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mmc.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mmc.c new file mode 100644 index 00000000000..1fb9a27f005 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mmc.c @@ -0,0 +1,5890 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_mmc.c + * @author MCD Application Team + * @brief MMC card HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital (MMC) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + MMC card Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver implements a high level communication layer for read and write from/to + this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by + the user in HAL_MMC_MspInit() function (MSP layer). + Basically, the MSP layer configuration should be the same as we provide in the + examples. + You can easily tailor this configuration according to hardware resources. + + [..] + This driver is a generic layered driver for SDMMC memories which uses the HAL + SDMMC driver functions to interface with MMC and eMMC cards devices. + It is used as follows: + + (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API: + (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); + (##) SDMMC pins configuration for MMC card + (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() + and according to your pin assignment; + (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT() + and HAL_MMC_WriteBlocks_IT() APIs). + (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); + (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() + and __HAL_MMC_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT() + and __HAL_MMC_CLEAR_IT() + (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used. + + (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization + + *** MMC Card Initialization and configuration *** + ================================================ + [..] + To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes + SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer). + This function provide the following operations: + + (#) Initialize the SDMMC peripheral interface with default configuration. + The initialization process is done at 400KHz. You can change or adapt + this frequency by adjusting the "ClockDiv" field. + The MMC Card frequency (SDMMC_CK) is computed as follows: + + SDMMC_CK = SDMMCCLK / (2 * ClockDiv) + + In initialization mode and according to the MMC Card standard, + make sure that the SDMMC_CK frequency doesn't exceed 400KHz. + + This phase of initialization is done through SDMMC_Init() and + SDMMC_PowerState_ON() SDMMC low level APIs. + + (#) Initialize the MMC card. The API used is HAL_MMC_InitCard(). + This phase allows the card initialization and identification + and check the MMC Card type (Standard Capacity or High Capacity) + The initialization flow is compatible with MMC standard. + + This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case + of plug-off plug-in. + + (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer + frequency by adjusting the "ClockDiv" field. + In transfer mode and according to the MMC Card standard, make sure that the + SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch. + + (#) Select the corresponding MMC Card according to the address read with the step 2. + + (#) Configure the MMC Card in wide bus mode: 4-bits data. + (#) Select the MMC Card partition using HAL_MMC_SwitchPartition() + + *** MMC Card Read operation *** + ============================== + [..] + (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + + (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the DMA transfer process through the MMC Rx interrupt event. + + (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the IT transfer process through the MMC Rx interrupt event. + + *** MMC Card Write operation *** + =============================== + [..] + (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + + (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA(). + This function support only 512-bytes block length (the block size should be + chosen as 512 byte). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the DMA transfer process through the MMC Tx interrupt event. + + (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the IT transfer process through the MMC Tx interrupt event. + + *** MMC card information *** + =========================== + [..] + (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo(). + It returns useful information about the MMC card such as block size, card type, + block number ... + + *** MMC card CSD register *** + ============================ + [..] + (+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register. + Some of the CSD parameters are useful for card initialization and identification. + + *** MMC card CID register *** + ============================ + [..] + (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register. + Some of the CID parameters are useful for card initialization and identification. + + *** MMC Card Reply Protected Memory Block (RPMB) Key Programming operation *** + ============================== + [..] + (+) You can program the authentication key of RPMB area in polling mode by using function + HAL_MMC_RPMB_ProgramAuthenticationKey(). + This function is only used once during the life of an MMC card. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + (+) You can program the authentication key of RPMB area in Interrupt mode by using function + HAL_MMC_RPMB_ProgramAuthenticationKey_IT(). + This function is only used once during the life of an MMC card. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + + *** MMC Card Reply Protected Memory Block (RPMB) write counter operation *** + ============================== + [..] + (+) You can get the write counter value of RPMB area in polling mode by using function + HAL_MMC_RPMB_GetWriteCounter(). + (+) You can get the write counter value of RPMB area in Interrupt mode by using function + HAL_MMC_RPMB_GetWriteCounter_IT(). + + *** MMC Card Reply Protected Memory Block (RPMB) write operation *** + ============================== + [..] + (+) You can write to the RPMB area of MMC card in polling mode by using function + HAL_MMC_WriteBlocks(). + This function supports the one, two, or thirty two blocks write operation + (with 512-bytes block length). + You can choose the number of blocks at the multiple block read operation by adjusting + the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + (+) You can write to the RPMB area of MMC card in Interrupt mode by using function + HAL_MMC_WriteBlocks_IT(). + This function supports the one, two, or thirty two blocks write operation + (with 512-bytes block length). + You can choose the number of blocks at the multiple block read operation by adjusting + the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + + *** MMC Card Reply Protected Memory Block (RPMB) read operation *** + ============================== + [..] + (+) You can read from the RPMB area of MMC card in polling mode by using function + HAL_MMC_RPMB_ReadBlocks(). + The block size should be chosen as multiple of 512 bytes. + You can choose the number of blocks by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for MMC card state. + (+) You can read from the RPMB area of MMC card in Interrupt mode by using function + HAL_MMC_RPMB_ReadBlocks_IT(). + The block size should be chosen as multiple of 512 bytes. + You can choose the number of blocks by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for MMC card state. + + *** MMC HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in MMC HAL driver. + + (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt + (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt + (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not + (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags + + [..] + (@) You can refer to the MMC HAL driver header file for more useful macros + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_MMC_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) Read_DMALnkLstBufCpltCallback : callback when the DMA reception of linked list node buffer is completed. + (+) Write_DMALnkLstBufCpltCallback : callback when the DMA transmission of linked list node buffer is completed. + (+) MspInitCallback : MMC MspInit. + (+) MspDeInitCallback : MMC MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. It allows to reset following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed. + (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed. + (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed. + (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed. + (+) MspInitCallback : MMC MspInit. + (+) MspDeInitCallback : MMC MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET + all callbacks are reset to the corresponding legacy weak (overridden) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (overridden) functions in the HAL_MMC_Init + and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_MMC_RegisterCallback before calling HAL_MMC_DeInit + or HAL_MMC_Init function. + + When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (overridden) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup MMC MMC + * @brief MMC HAL module driver + * @{ + */ + +#if defined (SDMMC1) || defined (SDMMC2) +#ifdef HAL_MMC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup MMC_Private_Defines + * @{ + */ +#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U) +#define MMC_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define MMC_EXT_CSD_PWR_CL_26_INDEX 201 +#define MMC_EXT_CSD_PWR_CL_52_INDEX 200 +#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 238 + +#define MMC_EXT_CSD_PWR_CL_26_POS 8 +#define MMC_EXT_CSD_PWR_CL_52_POS 0 +#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16 +#else +#define MMC_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE + +#define MMC_EXT_CSD_PWR_CL_26_INDEX 203 +#define MMC_EXT_CSD_PWR_CL_52_INDEX 202 +#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 239 + +#define MMC_EXT_CSD_PWR_CL_26_POS 24 +#define MMC_EXT_CSD_PWR_CL_52_POS 16 +#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24 +#endif /* (VDD_VALUE) && (VDD_VALUE <= 1950U)*/ + +#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX 216 +#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS 0 +#define MMC_EXT_CSD_S_A_TIMEOUT_INDEX 217 +#define MMC_EXT_CSD_S_A_TIMEOUT_POS 8 + +/* Frequencies used in the driver for clock divider calculation */ +#define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */ +#define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */ + +/* The Data elements' postitions in the frame Frame for RPMB area */ +#define MMC_RPMB_KEYMAC_POSITION 196U +#define MMC_RPMB_DATA_POSITION 228U +#define MMC_RPMB_NONCE_POSITION 484U +#define MMC_RPMB_WRITE_COUNTER_POSITION 500U +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Functions MMC Private Functions + * @{ + */ +static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc); +static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc); +static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus); +static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc); +static void MMC_Write_IT(MMC_HandleTypeDef *hmmc); +static void MMC_Read_IT(MMC_HandleTypeDef *hmmc); +static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state); +static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state); +static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, + uint32_t Timeout); +static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed); + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup MMC_Exported_Functions + * @{ + */ + +/** @addtogroup MMC_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize the MMC + card device to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the MMC according to the specified parameters in the + MMC_HandleTypeDef and create the associated handle. + * @param hmmc Pointer to the MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) +{ + /* Check the MMC handle allocation */ + if (hmmc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance)); + assert_param(IS_SDMMC_CLOCK_EDGE(hmmc->Init.ClockEdge)); + assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave)); + assert_param(IS_SDMMC_BUS_WIDE(hmmc->Init.BusWide)); + assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl)); + assert_param(IS_SDMMC_CLKDIV(hmmc->Init.ClockDiv)); + + if (hmmc->State == HAL_MMC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hmmc->Lock = HAL_UNLOCKED; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + /* Reset Callback pointers in HAL_MMC_STATE_RESET only */ + hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback; + hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback; + hmmc->ErrorCallback = HAL_MMC_ErrorCallback; + hmmc->AbortCpltCallback = HAL_MMC_AbortCallback; + hmmc->Read_DMALnkLstBufCpltCallback = HAL_MMCEx_Read_DMALnkLstBufCpltCallback; + hmmc->Write_DMALnkLstBufCpltCallback = HAL_MMCEx_Write_DMALnkLstBufCpltCallback; + + if (hmmc->MspInitCallback == NULL) + { + hmmc->MspInitCallback = HAL_MMC_MspInit; + } + + /* Init the low level hardware */ + hmmc->MspInitCallback(hmmc); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_MMC_MspInit(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize the Card parameters */ + if (HAL_MMC_InitCard(hmmc) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Initialize the error code */ + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the MMC operation */ + hmmc->Context = MMC_CONTEXT_NONE; + + /* Initialize the MMC state */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Configure bus width */ + if (hmmc->Init.BusWide != SDMMC_BUS_WIDE_1B) + { + if (HAL_MMC_ConfigWideBusOperation(hmmc, hmmc->Init.BusWide) != HAL_OK) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Initializes the MMC Card. + * @param hmmc Pointer to MMC handle + * @note This function initializes the MMC card. It could be used when a card + re-initialization is needed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate; + MMC_InitTypeDef Init; + uint32_t sdmmc_clk; + + /* Default SDMMC peripheral configuration for MMC card initialization */ + Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = SDMMC_BUS_WIDE_1B; + Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + + /* Init Clock should be less or equal to 400Khz*/ + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC12); + if (sdmmc_clk == 0U) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; + return HAL_ERROR; + } + Init.ClockDiv = sdmmc_clk / (2U * MMC_INIT_FREQ); + +#if (USE_SD_TRANSCEIVER != 0U) + Init.TranceiverPresent = SDMMC_TRANSCEIVER_NOT_PRESENT; +#endif /* USE_SD_TRANSCEIVER */ + + /* Initialize SDMMC peripheral interface with default configuration */ + (void)SDMMC_Init(hmmc->Instance, Init); + + /* Set Power State to ON */ + (void)SDMMC_PowerState_ON(hmmc->Instance); + + /* wait 74 Cycles: required power up waiting time before starting + the MMC initialization sequence */ + if (Init.ClockDiv != 0U) + { + sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); + } + + if (sdmmc_clk != 0U) + { + HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + } + + /* Identify card operating voltage */ + errorstate = MMC_PowerON(hmmc); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + /* Card initialization */ + errorstate = MMC_InitCard(hmmc); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief De-Initializes the MMC card. + * @param hmmc Pointer to MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) +{ + /* Check the MMC handle allocation */ + if (hmmc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance)); + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Set MMC power state to off */ + MMC_PowerOFF(hmmc); + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + if (hmmc->MspDeInitCallback == NULL) + { + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + } + + /* DeInit the low level hardware */ + hmmc->MspDeInitCallback(hmmc); +#else + /* De-Initialize the MSP layer */ + HAL_MMC_MspDeInit(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initializes the MMC MSP. + * @param hmmc Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MMC_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-Initialize MMC MSP. + * @param hmmc Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MMC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup MMC_Exported_Functions_Group2 + * @brief Data transfer functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the data + transfer from/to MMC card. + +@endverbatim + * @{ + */ + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc Pointer to MMC handle + * @param pData pointer to the buffer that will contain the received data + * @param BlockAdd Block Address from where data is to be read + * @param NumberOfBlocks Number of MMC blocks to read + * @param Timeout Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, + uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t data; + uint32_t dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; + + if (NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) + & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= MMC_BLOCKSIZE; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Read block(s) in polling mode */ + if (NumberOfBlocks > 1U) + { + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK; + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); + } + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Send stop transmission command in case of multiblock read */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to write block(s) to a specified address in a card. The Data + * transfer is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc Pointer to MMC handle + * @param pData pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of MMC blocks to write + * @param Timeout Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t data; + uint32_t dataremaining; + uint32_t add = BlockAdd; + const uint8_t *tempbuff = pData; + + if (NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= MMC_BLOCKSIZE; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + if (NumberOfBlocks > 1U) + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK; + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); + } + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*tempbuff); + tempbuff++; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Send stop transmission command in case of multiblock write */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the IT transfer process through the MMC Rx + * interrupt event. + * @param hmmc Pointer to MMC handle + * @param pData Pointer to the buffer that will contain the received data + * @param BlockAdd Block Address from where data is to be read + * @param NumberOfBlocks Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if (NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + hmmc->pRxBuffPtr = pData; + hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= MMC_BLOCKSIZE; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Read Blocks in IT mode */ + if (NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_RXFIFOHF)); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the IT transfer process through the MMC Tx + * interrupt event. + * @param hmmc Pointer to MMC handle + * @param pData Pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, + uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if (NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + hmmc->pTxBuffPtr = pData; + hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= MMC_BLOCKSIZE; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + if (NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_IT); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); + } + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Enable transfer interrupts */ + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_TXFIFOHE)); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the DMA transfer process through the MMC Rx + * interrupt event. + * @param hmmc Pointer MMC handle + * @param pData Pointer to the buffer that will contain the received data + * @param BlockAdd Block Address from where data is to be read + * @param NumberOfBlocks Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if (NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + hmmc->pRxBuffPtr = pData; + hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= MMC_BLOCKSIZE; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + hmmc->Instance->IDMABASER = (uint32_t) pData ; + hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + + /* Read Blocks in DMA mode */ + if (NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); + } + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode = errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Enable transfer interrupts */ + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the DMA transfer process through the MMC Tx + * interrupt event. + * @param hmmc Pointer to MMC handle + * @param pData Pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData, + uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if (NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + hmmc->pTxBuffPtr = pData; + hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= MMC_BLOCKSIZE; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + hmmc->Instance->IDMABASER = (uint32_t) pData ; + hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + + /* Write Blocks in Polling mode */ + if (NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); + } + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Enable transfer interrupts */ + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Erases the specified memory area of the given MMC card. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc Pointer to MMC handle + * @param BlockStartAdd: Start Block address + * @param BlockEndAdd: End Block address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd) +{ + uint32_t errorstate; + uint32_t start_add = BlockStartAdd; + uint32_t end_add = BlockEndAdd; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if (end_add < start_add) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if (end_add > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) + & 0x000000FFU) != 0x0U) + { + if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U)) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Check if the card command class supports erase command */ + if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + start_add *= MMC_BLOCKSIZE; + end_add *= MMC_BLOCKSIZE; + } + + /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */ + errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD36 MMC_ERASE_GRP_END with argument as addr */ + errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD38 ERASE */ + errorstate = SDMMC_CmdErase(hmmc->Instance, 0UL); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles MMC card interrupt request. + * @param hmmc Pointer to MMC handle + * @retval None + */ +void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate; + uint32_t context = hmmc->Context; + + /* Check for SDMMC interrupt flags */ + if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) + { + MMC_Read_IT(hmmc); + } + + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET) + { + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND); + + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | \ + SDMMC_IT_RXFIFOHF); + + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC); + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + if ((context & MMC_CONTEXT_DMA) != 0U) + { + hmmc->Instance->DLEN = 0; + hmmc->Instance->DCTRL = 0; + hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA ; + + /* Stop Transfer for Write Multi blocks or Read Multi blocks */ + if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + if (((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->TxCpltCallback(hmmc); +#else + HAL_MMC_TxCpltCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->RxCpltCallback(hmmc); +#else + HAL_MMC_RxCpltCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + } + else if ((context & MMC_CONTEXT_IT) != 0U) + { + /* Stop Transfer for Write Multi blocks or Read Multi blocks */ + if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->RxCpltCallback(hmmc); +#else + HAL_MMC_RxCpltCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + else + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->TxCpltCallback(hmmc); +#else + HAL_MMC_TxCpltCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } + } + + else if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) + { + MMC_Write_IT(hmmc); + } + + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL | + SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) + { + /* Set Error code */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + } + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + } + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + } + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + } + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + /* Disable all interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; + hmmc->Instance->CMD |= SDMMC_CMD_CMDSTOP; + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + hmmc->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DABORT); + + if ((context & MMC_CONTEXT_IT) != 0U) + { + /* Set the MMC state to ready to be able to start again the process */ + hmmc->State = HAL_MMC_STATE_READY; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + else if ((context & MMC_CONTEXT_DMA) != 0U) + { + if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + /* Disable Internal DMA */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC); + hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + /* Set the MMC state to ready to be able to start again the process */ + hmmc->State = HAL_MMC_STATE_READY; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } + } + + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET) + { + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC); + + if ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->Write_DMALnkLstBufCpltCallback(hmmc); +#else + HAL_MMCEx_Write_DMALnkLstBufCpltCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */ + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->Read_DMALnkLstBufCpltCallback(hmmc); +#else + HAL_MMCEx_Read_DMALnkLstBufCpltCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + } + + else + { + /* Nothing to do */ + } +} + +/** + * @brief return the MMC state + * @param hmmc Pointer to mmc handle + * @retval HAL state + */ +HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc) +{ + return hmmc->State; +} + +/** + * @brief Return the MMC error code + * @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. + * @retval MMC Error Code + */ +uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc) +{ + return hmmc->ErrorCode; +} + +/** + * @brief Tx Transfer completed callbacks + * @param hmmc Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hmmc Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief MMC error callbacks + * @param hmmc Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief MMC Abort callbacks + * @param hmmc Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_AbortCallback can be implemented in the user file + */ +} + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User MMC Callback + * To be used instead of the weak (overridden) predefined callback + * @note The HAL_MMC_RegisterCallback() may be called before HAL_MMC_Init() in + * HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID + * and HAL_MMC_MSP_DEINIT_CB_ID. + * @param hmmc : MMC handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID + * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID + * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID + * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID + * @arg @ref HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID MMC DMA Rx Linked List Node buffer Callback ID + * @arg @ref HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID MMC DMA Tx Linked List Node buffer Callback ID + * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID + * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, + pMMC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + switch (CallbackId) + { + case HAL_MMC_TX_CPLT_CB_ID : + hmmc->TxCpltCallback = pCallback; + break; + case HAL_MMC_RX_CPLT_CB_ID : + hmmc->RxCpltCallback = pCallback; + break; + case HAL_MMC_ERROR_CB_ID : + hmmc->ErrorCallback = pCallback; + break; + case HAL_MMC_ABORT_CB_ID : + hmmc->AbortCpltCallback = pCallback; + break; + case HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID : + hmmc->Read_DMALnkLstBufCpltCallback = pCallback; + break; + case HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID : + hmmc->Write_DMALnkLstBufCpltCallback = pCallback; + break; + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = pCallback; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hmmc->State == HAL_MMC_STATE_RESET) + { + switch (CallbackId) + { + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = pCallback; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User MMC Callback + * MMC Callback is redirected to the weak (overridden) predefined callback + * @note The HAL_MMC_UnRegisterCallback() may be called before HAL_MMC_Init() in + * HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID + * and HAL_MMC_MSP_DEINIT_CB_ID. + * @param hmmc : MMC handle + * @param CallbackId : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID + * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID + * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID + * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID + * @arg @ref HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID MMC DMA Rx Linked List Node buffer Callback ID + * @arg @ref HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID MMC DMA Tx Linked List Node buffer Callback ID + * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID + * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + switch (CallbackId) + { + case HAL_MMC_TX_CPLT_CB_ID : + hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback; + break; + case HAL_MMC_RX_CPLT_CB_ID : + hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback; + break; + case HAL_MMC_ERROR_CB_ID : + hmmc->ErrorCallback = HAL_MMC_ErrorCallback; + break; + case HAL_MMC_ABORT_CB_ID : + hmmc->AbortCpltCallback = HAL_MMC_AbortCallback; + break; + case HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID : + hmmc->Read_DMALnkLstBufCpltCallback = HAL_MMCEx_Read_DMALnkLstBufCpltCallback; + break; + case HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID : + hmmc->Write_DMALnkLstBufCpltCallback = HAL_MMCEx_Write_DMALnkLstBufCpltCallback; + break; + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = HAL_MMC_MspInit; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hmmc->State == HAL_MMC_STATE_RESET) + { + switch (CallbackId) + { + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = HAL_MMC_MspInit; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup MMC_Exported_Functions_Group3 + * @brief management functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the MMC card + operations and get the related information + +@endverbatim + * @{ + */ + +/** + * @brief Returns information the information of the card which are stored on + * the CID register. + * @param hmmc Pointer to MMC handle + * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that + * contains all CID register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) +{ + pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U); + + pCID->OEM_AppliID = (uint16_t)((hmmc->CID[0] & 0x00FFFF00U) >> 8U); + + pCID->ProdName1 = (((hmmc->CID[0] & 0x000000FFU) << 24U) | ((hmmc->CID[1] & 0xFFFFFF00U) >> 8U)); + + pCID->ProdName2 = (uint8_t)(hmmc->CID[1] & 0x000000FFU); + + pCID->ProdRev = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24U); + + pCID->ProdSN = (((hmmc->CID[2] & 0x00FFFFFFU) << 8U) | ((hmmc->CID[3] & 0xFF000000U) >> 24U)); + + pCID->Reserved1 = (uint8_t)((hmmc->CID[3] & 0x00F00000U) >> 20U); + + pCID->ManufactDate = (uint16_t)((hmmc->CID[3] & 0x000FFF00U) >> 8U); + + pCID->CID_CRC = (uint8_t)((hmmc->CID[3] & 0x000000FEU) >> 1U); + + pCID->Reserved2 = 1U; + + return HAL_OK; +} + +/** + * @brief Returns information the information of the card which are stored on + * the CSD register. + * @param hmmc Pointer to MMC handle + * @param pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that + * contains all CSD register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD) +{ + uint32_t block_nbr = 0; + + pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U); + + pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U); + + pCSD->Reserved1 = (uint8_t)((hmmc->CSD[0] & 0x03000000U) >> 24U); + + pCSD->TAAC = (uint8_t)((hmmc->CSD[0] & 0x00FF0000U) >> 16U); + + pCSD->NSAC = (uint8_t)((hmmc->CSD[0] & 0x0000FF00U) >> 8U); + + pCSD->MaxBusClkFrec = (uint8_t)(hmmc->CSD[0] & 0x000000FFU); + + pCSD->CardComdClasses = (uint16_t)((hmmc->CSD[1] & 0xFFF00000U) >> 20U); + + pCSD->RdBlockLen = (uint8_t)((hmmc->CSD[1] & 0x000F0000U) >> 16U); + + pCSD->PartBlockRead = (uint8_t)((hmmc->CSD[1] & 0x00008000U) >> 15U); + + pCSD->WrBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00004000U) >> 14U); + + pCSD->RdBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00002000U) >> 13U); + + pCSD->DSRImpl = (uint8_t)((hmmc->CSD[1] & 0x00001000U) >> 12U); + + pCSD->Reserved2 = 0U; /*!< Reserved */ + + if (MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */ + { + return HAL_ERROR; + } + + if (hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD) + { + pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U)); + + pCSD->MaxRdCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x38000000U) >> 27U); + + pCSD->MaxRdCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x07000000U) >> 24U); + + pCSD->MaxWrCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x00E00000U) >> 21U); + + pCSD->MaxWrCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x001C0000U) >> 18U); + + pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U); + + hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ; + hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + + hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / MMC_BLOCKSIZE); + hmmc->MmcCard.LogBlockSize = MMC_BLOCKSIZE; + } + else if (hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD) + { + hmmc->MmcCard.BlockNbr = block_nbr; + hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr; + hmmc->MmcCard.BlockSize = MMC_BLOCKSIZE; + hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize; + } + else + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U); + + pCSD->EraseGrMul = (uint8_t)((hmmc->CSD[2] & 0x00003F80U) >> 7U); + + pCSD->WrProtectGrSize = (uint8_t)(hmmc->CSD[2] & 0x0000007FU); + + pCSD->WrProtectGrEnable = (uint8_t)((hmmc->CSD[3] & 0x80000000U) >> 31U); + + pCSD->ManDeflECC = (uint8_t)((hmmc->CSD[3] & 0x60000000U) >> 29U); + + pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U); + + pCSD->MaxWrBlockLen = (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U); + + pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U); + + pCSD->Reserved3 = 0; + + pCSD->ContentProtectAppli = (uint8_t)((hmmc->CSD[3] & 0x00010000U) >> 16U); + + pCSD->FileFormatGroup = (uint8_t)((hmmc->CSD[3] & 0x00008000U) >> 15U); + + pCSD->CopyFlag = (uint8_t)((hmmc->CSD[3] & 0x00004000U) >> 14U); + + pCSD->PermWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00002000U) >> 13U); + + pCSD->TempWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00001000U) >> 12U); + + pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U); + + pCSD->ECC = (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U); + + pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U); + + pCSD->Reserved4 = 1; + + return HAL_OK; +} + +/** + * @brief Gets the MMC card info. + * @param hmmc Pointer to MMC handle + * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that + * will contain the MMC card status information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) +{ + pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType); + pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class); + pCardInfo->RelCardAdd = (uint32_t)(hmmc->MmcCard.RelCardAdd); + pCardInfo->BlockNbr = (uint32_t)(hmmc->MmcCard.BlockNbr); + pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize); + pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr); + pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize); + + return HAL_OK; +} + +/** + * @brief Returns information the information of the card which are stored on + * the Extended CSD register. + * @param hmmc Pointer to MMC handle + * @param pExtCSD Pointer to a memory area (512 bytes) that contains all + * Extended CSD register parameters + * @param Timeout Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t *tmp_buf; + + if (NULL == pExtCSD) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + /* Initiaize the destination pointer */ + tmp_buf = pExtCSD; + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Send ExtCSD Read command to Card */ + errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | + SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + *tmp_buf = SDMMC_ReadFIFO(hmmc->Instance); + tmp_buf++; + } + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + hmmc->State = HAL_MMC_STATE_READY; + } + + return HAL_OK; +} + +/** + * @brief Enables wide bus operation for the requested card if supported by + * card. + * @param hmmc Pointer to MMC handle + * @param WideMode: Specifies the MMC card wide bus mode + * This parameter can be one of the following values: + * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer + * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer + * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode) +{ + uint32_t count; + SDMMC_InitTypeDef Init; + uint32_t errorstate; + uint32_t response = 0U; + + /* Check the parameters */ + assert_param(IS_SDMMC_BUS_WIDE(WideMode)); + + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Check and update the power class if needed */ + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) + { + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) + { + errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DDR); + } + else + { + errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_HIGH); + } + } + else + { + errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DEFAULT); + } + + if (errorstate == HAL_MMC_ERROR_NONE) + { + if (WideMode == SDMMC_BUS_WIDE_8B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); + } + else if (WideMode == SDMMC_BUS_WIDE_4B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); + } + else if (WideMode == SDMMC_BUS_WIDE_1B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U); + } + else + { + /* WideMode is not a valid argument*/ + errorstate = HAL_MMC_ERROR_PARAM; + } + + /* Check for switch error and violation of the trial number of sending CMD 13 */ + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + else + { + /* Configure the SDMMC peripheral */ + Init = hmmc->Init; + Init.BusWide = WideMode; + (void)SDMMC_Init(hmmc->Instance, Init); + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Configure the speed bus mode + * @param hmmc Pointer to the MMC handle + * @param SpeedMode: Specifies the MMC card speed bus mode + * This parameter can be one of the following values: + * @arg SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card + * @arg SDMMC_SPEED_MODE_DEFAULT: Default Speed (MMC @ 26MHz) + * @arg SDMMC_SPEED_MODE_HIGH: High Speed (MMC @ 52 MHz) + * @arg SDMMC_SPEED_MODE_DDR: High Speed DDR (MMC DDR @ 52 MHz) + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + uint32_t device_type; + uint32_t errorstate; + + /* Check the parameters */ + assert_param(IS_SDMMC_SPEED_MODE(SpeedMode)); + + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Field DEVICE_TYPE [196 = 49*4] of Extended CSD register */ + device_type = (hmmc->Ext_CSD[49] & 0x000000FFU); + + switch (SpeedMode) + { + case SDMMC_SPEED_MODE_AUTO: + { + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U)) + { + /* High Speed DDR mode allowed */ + errorstate = MMC_HighSpeed(hmmc, ENABLE); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + else + { + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U) + { + /* DDR mode not supported with CLKDIV = 0 */ + errorstate = MMC_DDR_Mode(hmmc, ENABLE); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + } + } + else if ((device_type & 0x02U) != 0U) + { + /* High Speed mode allowed */ + errorstate = MMC_HighSpeed(hmmc, ENABLE); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + else + { + /* Nothing to do : keep current speed */ + } + break; + } + case SDMMC_SPEED_MODE_DDR: + { + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U)) + { + /* High Speed DDR mode allowed */ + errorstate = MMC_HighSpeed(hmmc, ENABLE); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + else + { + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U) + { + /* DDR mode not supported with CLKDIV = 0 */ + errorstate = MMC_DDR_Mode(hmmc, ENABLE); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + } + } + else + { + /* High Speed DDR mode not allowed */ + hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_HIGH: + { + if ((device_type & 0x02U) != 0U) + { + /* High Speed mode allowed */ + errorstate = MMC_HighSpeed(hmmc, ENABLE); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + else + { + /* High Speed mode not allowed */ + hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_DEFAULT: + { + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) + { + /* High Speed DDR mode activated */ + errorstate = MMC_DDR_Mode(hmmc, DISABLE); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) + { + /* High Speed mode activated */ + errorstate = MMC_HighSpeed(hmmc, DISABLE); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + break; + } + default: + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + status = HAL_ERROR; + break; + } + + /* Verify that MMC card is ready to use after Speed mode switch*/ + tickstart = HAL_GetTick(); + while ((HAL_MMC_GetCardState(hmmc) != HAL_MMC_CARD_TRANSFER)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + return status; +} + +/** + * @brief Gets the current mmc card data state. + * @param hmmc pointer to MMC handle + * @retval Card state + */ +HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) +{ + uint32_t cardstate; + uint32_t errorstate; + uint32_t resp1 = 0U; + + errorstate = MMC_SendStatus(hmmc, &resp1); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + cardstate = ((resp1 >> 9U) & 0x0FU); + + return (HAL_MMC_CardStateTypeDef)cardstate; +} + +/** + * @brief Abort the current transfer and disable the MMC. + * @param hmmc pointer to a MMC_HandleTypeDef structure that contains + * the configuration information for MMC module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) +{ + uint32_t error_code; + uint32_t tickstart; + + if (hmmc->State == HAL_MMC_STATE_BUSY) + { + /* DIsable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /*we will send the CMD12 in all cases in order to stop the data transfers*/ + /*In case the data transfer just finished, the external memory will not respond + and will return HAL_MMC_ERROR_CMD_RSP_TIMEOUT*/ + /*In case the data transfer aborted , the external memory will respond and will return HAL_MMC_ERROR_NONE*/ + /*Other scenario will return HAL_ERROR*/ + + hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); + error_code = hmmc->ErrorCode; + if ((error_code != HAL_MMC_ERROR_NONE) && (error_code != HAL_MMC_ERROR_CMD_RSP_TIMEOUT)) + { + return HAL_ERROR; + } + + tickstart = HAL_GetTick(); + if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_CARD) + { + if (hmmc->ErrorCode == HAL_MMC_ERROR_NONE) + { + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + } + + if (hmmc->ErrorCode == HAL_MMC_ERROR_CMD_RSP_TIMEOUT) + { + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + } + } + else if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC) + { + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + } + else + { + /* Nothing to do*/ + } + + /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear + the appropriate flags that will be set depending of the abort/non abort of the memory */ + /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared and will result + in next SDMMC read/write operation to fail */ + + /*SDMMC ready for clear data flags*/ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* If IDMA Context, disable Internal DMA */ + hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + hmmc->State = HAL_MMC_STATE_READY; + + /* Initialize the MMC operation */ + hmmc->Context = MMC_CONTEXT_NONE; + } + return HAL_OK; +} +/** + * @brief Abort the current transfer and disable the MMC (IT mode). + * @param hmmc pointer to a MMC_HandleTypeDef structure that contains + * the configuration information for MMC module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardStateTypeDef CardState; + + /* DIsable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + + /* If IDMA Context, disable Internal DMA */ + hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->State = HAL_MMC_STATE_READY; + + if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); + } + if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + return HAL_ERROR; + } + else + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else + HAL_MMC_AbortCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Perform specific commands sequence for the different type of erase. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc Pointer to MMC handle + * @param EraseType Specifies the type of erase to be performed + * This parameter can be one of the following values: + * @arg HAL_MMC_TRIM Erase the write blocks identified by CMD35 & 36 + * @arg HAL_MMC_ERASE Erase the erase groups identified by CMD35 & 36 + * @arg HAL_MMC_DISCARD Discard the write blocks identified by CMD35 & 36 + * @arg HAL_MMC_SECURE_ERASE Perform a secure purge according SRT on the erase groups identified + * by CMD35 & 36 + * @arg HAL_MMC_SECURE_TRIM_STEP1 Mark the write blocks identified by CMD35 & 36 for secure erase + * @arg HAL_MMC_SECURE_TRIM_STEP2 Perform a secure purge according SRT on the write blocks + * previously identified + * @param BlockStartAdd Start Block address + * @param BlockEndAdd End Block address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, + uint32_t BlockStartAdd, uint32_t BlockEndAdd) +{ + uint32_t errorstate; + uint32_t start_add = BlockStartAdd; + uint32_t end_add = BlockEndAdd; + uint32_t tickstart = HAL_GetTick(); + + /* Check the erase type value is correct */ + assert_param(IS_MMC_ERASE_TYPE(EraseType)); + + /* Check the coherence between start and end address */ + if (end_add < start_add) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + /* Check that the end address is not out of range of device memory */ + if (end_add > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U)) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + + /* Check if the card command class supports erase command */ + if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + return HAL_ERROR; + } + + /* Check the state of the driver */ + if (hmmc->State == HAL_MMC_STATE_READY) + { + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Check that the card is not locked */ + if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* In case of low capacity card, the address is not block number but bytes */ + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + start_add *= MMC_BLOCKSIZE; + end_add *= MMC_BLOCKSIZE; + } + + /* Send CMD35 MMC_ERASE_GRP_START with start address as argument */ + errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Send CMD36 MMC_ERASE_GRP_END with end address as argument */ + errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Send CMD38 ERASE with erase type as argument */ + errorstate = SDMMC_CmdErase(hmmc->Instance, EraseType); + if (errorstate == HAL_MMC_ERROR_NONE) + { + if ((EraseType == HAL_MMC_SECURE_ERASE) || (EraseType == HAL_MMC_SECURE_TRIM_STEP2)) + { + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT) + { + errorstate = HAL_MMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + } + } + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Manage errors */ + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + + if (errorstate != HAL_MMC_ERROR_TIMEOUT) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + else + { + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Perform sanitize operation on the device. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc Pointer to MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate; + uint32_t response = 0U; + uint32_t count; + uint32_t tickstart = HAL_GetTick(); + + /* Check the state of the driver */ + if (hmmc->State == HAL_MMC_STATE_READY) + { + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Index : 165 - Value : 0x01 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03A50100U); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT) + { + errorstate = HAL_MMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Manage errors */ + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + + if (errorstate != HAL_MMC_ERROR_TIMEOUT) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + else + { + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure the Secure Removal Type (SRT) in the Extended CSD register. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc Pointer to MMC handle + * @param SRTMode Specifies the type of erase to be performed + * This parameter can be one of the following values: + * @arg HAL_MMC_SRT_ERASE Information removed by an erase + * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character + * followed by an erase + * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, + * its complement then a random character + * @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode) +{ + uint32_t srt; + uint32_t errorstate; + uint32_t response = 0U; + uint32_t count; + + /* Check the erase type value is correct */ + assert_param(IS_MMC_SRT_TYPE(SRTMode)); + + /* Check the state of the driver */ + if (hmmc->State == HAL_MMC_STATE_READY) + { + /* Get the supported values by the device */ + if (HAL_MMC_GetSupportedSecRemovalType(hmmc, &srt) == HAL_OK) + { + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Check the value passed as parameter is supported by the device */ + if ((SRTMode & srt) != 0U) + { + /* Index : 16 - Value : SRTMode */ + srt |= ((POSITION_VAL(SRTMode)) << 4U); + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03100000U | (srt << 8U))); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + else + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + } + else + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + + /* Manage errors */ + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + else + { + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Gets the supported values of the the Secure Removal Type (SRT). + * @param hmmc pointer to MMC handle + * @param SupportedSRT pointer for supported SRT value + * This parameter is a bit field of the following values: + * @arg HAL_MMC_SRT_ERASE Information removed by an erase + * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed + * by an erase + * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, + * its complement then a random character + * @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT) +{ + /* Check the state of the driver */ + if (hmmc->State == HAL_MMC_STATE_READY) + { + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Read field SECURE_REMOVAL_TYPE [16 = 4*4] of the Extended CSD register */ + *SupportedSRT = (hmmc->Ext_CSD[4] & 0x0000000FU); /* Bits [3:0] of field 16 */ + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Switch the device from Standby State to Sleep State. + * @param hmmc pointer to MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate, + sleep_timeout, + timeout, + count, + response = 0U ; + uint32_t tickstart = HAL_GetTick(); + + /* Check the state of the driver */ + if (hmmc->State == HAL_MMC_STATE_READY) + { + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U)); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* Set the power-off notification to sleep notification : Ext_CSD[34] = 4 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220400U)); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Field SLEEP_NOTIFICATION_TIME [216] */ + sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX / 4)] >> + MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS) & 0x000000FFU); + + /* Sleep/Awake Timeout = 10us * 2^SLEEP_NOTIFICATION_TIME */ + /* In HAL, the tick interrupt occurs each ms */ + if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U)) + { + sleep_timeout = 0x17U; /* Max register value defined is 0x17 */ + } + timeout = (((1UL << sleep_timeout) / 100U) + 1U); + + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= timeout) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, + (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* Switch the device in stand-by mode */ + (void)SDMMC_CmdSelDesel(hmmc->Instance, 0U); + + /* Field S_A_TIEMOUT [217] */ + sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >> + MMC_EXT_CSD_S_A_TIMEOUT_POS) & 0x000000FFU); + + /* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */ + /* In HAL, the tick interrupt occurs each ms */ + if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U)) + { + sleep_timeout = 0x17U; /* Max register value defined is 0x17 */ + } + timeout = (((1UL << sleep_timeout) / 10000U) + 1U); + + if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY) + { + /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and SLEEP as argument */ + errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, + ((hmmc->MmcCard.RelCardAdd << 16U) | (0x1U << 15U))); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= timeout) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + } + } + else + { + errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE; + } + } + } + else + { + /* Nothing to do */ + } + } + } + } + } + else + { + /* Nothing to do */ + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Manage errors */ + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + + if (errorstate != HAL_MMC_ERROR_TIMEOUT) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + else + { + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Switch the device from Sleep State to Standby State. + * @param hmmc pointer to MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate; + uint32_t sleep_timeout; + uint32_t timeout; + uint32_t count; + uint32_t response = 0U; + uint32_t tickstart = HAL_GetTick(); + + /* Check the state of the driver */ + if (hmmc->State == HAL_MMC_STATE_READY) + { + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Field S_A_TIEMOUT [217] */ + sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >> MMC_EXT_CSD_S_A_TIMEOUT_POS) & + 0x000000FFU); + + /* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */ + /* In HAL, the tick interrupt occurs each ms */ + if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U)) + { + sleep_timeout = 0x17U; /* Max register value defined is 0x17 */ + } + timeout = (((1UL << sleep_timeout) / 10000U) + 1U); + + /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and AWAKE as argument */ + errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U)); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= timeout) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + + if (errorstate == HAL_MMC_ERROR_NONE) + { + if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY) + { + /* Switch the device in transfer mode */ + errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U)); + if (errorstate == HAL_MMC_ERROR_NONE) + { + if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_TRANSFER) + { + /* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U)); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, + (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + } + else + { + /* NOthing to do */ + } + } + } + else + { + errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE; + } + } + } + else + { + errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE; + } + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Manage errors */ + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + + if (errorstate != HAL_MMC_ERROR_TIMEOUT) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + else + { + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup MMC_Private_Functions + * @{ + */ + +/** + * @brief Initializes the mmc card. + * @param hmmc Pointer to MMC handle + * @retval MMC Card error state + */ +static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardCSDTypeDef CSD; + uint32_t errorstate; + uint16_t mmc_rca = 2U; + MMC_InitTypeDef Init; + + /* Check the power State */ + if (SDMMC_GetPowerState(hmmc->Instance) == 0U) + { + /* Power off */ + return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + } + + /* Send CMD2 ALL_SEND_CID */ + errorstate = SDMMC_CmdSendCID(hmmc->Instance); + if (errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card identification number data */ + hmmc->CID[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + hmmc->CID[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); + hmmc->CID[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); + hmmc->CID[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); + } + + /* Send CMD3 SET_REL_ADDR with RCA = 2 (should be greater than 1) */ + /* MMC Card publishes its RCA. */ + errorstate = SDMMC_CmdSetRelAddMmc(hmmc->Instance, mmc_rca); + if (errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Get the MMC card RCA */ + hmmc->MmcCard.RelCardAdd = mmc_rca; + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card Specific Data */ + hmmc->CSD[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + hmmc->CSD[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); + hmmc->CSD[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); + hmmc->CSD[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); + } + + /* Get the Card Class */ + hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U); + + /* Select the Card */ + errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Get CSD parameters */ + if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK) + { + return hmmc->ErrorCode; + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Get Extended CSD parameters */ + if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK) + { + return hmmc->ErrorCode; + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Configure the SDMMC peripheral */ + Init = hmmc->Init; + Init.BusWide = SDMMC_BUS_WIDE_1B; + (void)SDMMC_Init(hmmc->Instance, Init); + + /* All cards are initialized */ + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Enquires cards about their operating voltage and configures clock + * controls and stores MMC information that will be needed in future + * in the MMC handle. + * @param hmmc Pointer to MMC handle + * @retval error state + */ +static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) +{ + __IO uint32_t count = 0U; + uint32_t response = 0U; + uint32_t validvoltage = 0U; + uint32_t errorstate; + + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hmmc->Instance); + if (errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + while (validvoltage == 0U) + { + if (count++ == SDMMC_MAX_VOLT_TRIAL) + { + return HAL_MMC_ERROR_INVALID_VOLTRANGE; + } + + /* SEND CMD1 APP_CMD with voltage range as argument */ + errorstate = SDMMC_CmdOpCondition(hmmc->Instance, MMC_VOLTAGE_RANGE); + if (errorstate != HAL_MMC_ERROR_NONE) + { + return HAL_MMC_ERROR_UNSUPPORTED_FEATURE; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); + } + + /* When power routine is finished and command returns valid voltage */ + if (((response & (0xFF000000U)) >> 24) == 0xC0U) + { + hmmc->MmcCard.CardType = MMC_HIGH_CAPACITY_CARD; + } + else + { + hmmc->MmcCard.CardType = MMC_LOW_CAPACITY_CARD; + } + + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Turns the SDMMC output signals off. + * @param hmmc Pointer to MMC handle + * @retval None + */ +static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc) +{ + /* Set Power State to OFF */ + (void)SDMMC_PowerState_OFF(hmmc->Instance); +} + +/** + * @brief Returns the current card's status. + * @param hmmc Pointer to MMC handle + * @param pCardStatus: pointer to the buffer that will contain the MMC card + * status (Card Status register) + * @retval error state + */ +static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) +{ + uint32_t errorstate; + + if (pCardStatus == NULL) + { + return HAL_MMC_ERROR_PARAM; + } + + /* Send Status command */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Get MMC card status */ + *pCardStatus = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Reads extended CSD register to get the sectors number of the device + * @param hmmc Pointer to MMC handle + * @param pFieldData: Pointer to the read buffer + * @param FieldIndex: Index of the field to be read + * @param Timeout Specify timeout value + * @retval HAL status + */ +static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, + uint16_t FieldIndex, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t i = 0; + uint32_t tmp_data; + + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + tmp_data = SDMMC_ReadFIFO(hmmc->Instance); + /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */ + /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */ + if ((i + count) == ((uint32_t)FieldIndex / 4U)) + { + *pFieldData = tmp_data; + } + } + i += 8U; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Wrap up reading in non-blocking mode. + * @param hmmc pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) +{ + uint32_t count; + uint32_t data; + uint8_t *tmp; + + tmp = hmmc->pRxBuffPtr; + + if (hmmc->RxXferSize >= SDMMC_FIFO_SIZE) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tmp = (uint8_t)(data & 0xFFU); + tmp++; + *tmp = (uint8_t)((data >> 8U) & 0xFFU); + tmp++; + *tmp = (uint8_t)((data >> 16U) & 0xFFU); + tmp++; + *tmp = (uint8_t)((data >> 24U) & 0xFFU); + tmp++; + } + + hmmc->pRxBuffPtr = tmp; + hmmc->RxXferSize -= SDMMC_FIFO_SIZE; + } +} + +/** + * @brief Wrap up writing in non-blocking mode. + * @param hmmc pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) +{ + uint32_t count; + uint32_t data; + const uint8_t *tmp; + + tmp = hmmc->pTxBuffPtr; + + if (hmmc->TxXferSize >= SDMMC_FIFO_SIZE) + { + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*tmp); + tmp++; + data |= ((uint32_t)(*tmp) << 8U); + tmp++; + data |= ((uint32_t)(*tmp) << 16U); + tmp++; + data |= ((uint32_t)(*tmp) << 24U); + tmp++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + } + + hmmc->pTxBuffPtr = tmp; + hmmc->TxXferSize -= SDMMC_FIFO_SIZE; + } +} + +/** + * @brief Switches the MMC card to high speed mode. + * @param hmmc MMC handle + * @param state: State of high speed mode + * @retval MMC Card error state + */ +static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) +{ + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t response = 0U; + uint32_t count; + uint32_t sdmmc_clk; + SDMMC_InitTypeDef Init; + + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE)) + { + errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_DEFAULT); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Index : 185 - Value : 0 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U); + } + } + + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE)) + { + errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_HIGH); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Index : 185 - Value : 1 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U); + } + } + + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* Configure high speed */ + Init.ClockEdge = hmmc->Init.ClockEdge; + Init.ClockPowerSave = hmmc->Init.ClockPowerSave; + Init.BusWide = (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS); + Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl; + + if (state == DISABLE) + { + Init.ClockDiv = hmmc->Init.ClockDiv; + (void)SDMMC_Init(hmmc->Instance, Init); + + CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED); + } + else + { + /* High Speed Clock should be less or equal to 52MHz*/ + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC12); + + if (sdmmc_clk == 0U) + { + errorstate = SDMMC_ERROR_INVALID_PARAMETER; + } + else + { + if (sdmmc_clk <= MMC_HIGH_SPEED_FREQ) + { + Init.ClockDiv = 0; + } + else + { + Init.ClockDiv = (sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ)) + 1U; + } + (void)SDMMC_Init(hmmc->Instance, Init); + + SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED); + } + } + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + + return errorstate; +} + +/** + * @brief Switches the MMC card to Double Data Rate (DDR) mode. + * @param hmmc MMC handle + * @param state: State of DDR mode + * @retval MMC Card error state + */ +static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) +{ + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t response = 0U; + uint32_t count; + + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) && (state == DISABLE)) + { + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U) + { + errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_HIGH); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Index : 183 - Value : 1 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); + } + } + else + { + errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_HIGH); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Index : 183 - Value : 2 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); + } + } + } + + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) && (state != DISABLE)) + { + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U) + { + errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_DDR); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Index : 183 - Value : 5 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70500U); + } + } + else + { + errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_DDR); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Index : 183 - Value : 6 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70600U); + } + } + } + + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* Configure DDR mode */ + if (state == DISABLE) + { + CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR); + } + else + { + SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR); + } + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + + return errorstate; +} + +/** + * @brief Update the power class of the device. + * @param hmmc MMC handle + * @param Wide Wide of MMC bus + * @param Speed Speed of the MMC bus + * @retval MMC Card error state + */ +static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed) +{ + uint32_t count; + uint32_t response = 0U; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t power_class; + uint32_t supported_pwr_class; + + if ((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B)) + { + power_class = 0U; /* Default value after power-on or software reset */ + + /* Read the PowerClass field of the Extended CSD register */ + if (MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */ + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + else + { + power_class = ((power_class >> 24U) & 0x000000FFU); + } + + /* Get the supported PowerClass field of the Extended CSD register */ + if (Speed == SDMMC_SPEED_MODE_DDR) + { + /* Field PWR_CL_DDR_52_xxx [238 or 239] */ + supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_DDR_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_DDR_52_POS) & + 0x000000FFU); + } + else if (Speed == SDMMC_SPEED_MODE_HIGH) + { + /* Field PWR_CL_52_xxx [200 or 202] */ + supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_52_POS) & + 0x000000FFU); + } + else + { + /* Field PWR_CL_26_xxx [201 or 203] */ + supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_26_POS) & + 0x000000FFU); + } + + if (errorstate == HAL_MMC_ERROR_NONE) + { + if (Wide == SDMMC_BUS_WIDE_8B) + { + /* Bit [7:4]: power class for 8-bits bus configuration - Bit [3:0]: power class for 4-bits bus configuration */ + supported_pwr_class = (supported_pwr_class >> 4U); + } + + if ((power_class & 0x0FU) != (supported_pwr_class & 0x0FU)) + { + /* Need to change current power class */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03BB0000U | ((supported_pwr_class & 0x0FU) << 8U))); + + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + } + } + + return errorstate; +} + +/** + * @brief Used to select the partition. + * @param hmmc Pointer to MMC handle + * @param Partition Partition type + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition) +{ + uint32_t errorstate; + uint32_t response = 0U; + uint32_t count; + uint32_t tickstart = HAL_GetTick(); + uint32_t arg = Partition | 0x03B30000U; + + /* Check the state of the driver */ + if (hmmc->State == HAL_MMC_STATE_READY) + { + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Index : 179 - Value : partition */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, arg); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT) + { + errorstate = HAL_MMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Manage errors */ + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + + if (errorstate != HAL_MMC_ERROR_TIMEOUT) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + else + { + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Allows to program the authentication key within the RPMB partition + * @param hmmc Pointer to MMC handle + * @param pKey pointer to the authentication key (32 bytes) + * @param Timeout Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint32_t dataremaining; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + const uint8_t *rtempbuff; + uint8_t *tempbuff; + + tail_pack[11] = 0x01; + + if (NULL == pKey) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x80000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + rtempbuff = zero_pack; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_KEYMAC_POSITION) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_KEYMAC_POSITION) + { + rtempbuff = pKey; + } + else if ((byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) && \ + (byte_count >= MMC_RPMB_DATA_POSITION)) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packet */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + byte_count = 0; + + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + /* Check result of operation */ + if ((tail_pack[9] != 0x00U) || (tail_pack[10] != 0x01U)) + { + hmmc->RPMBErrorCode |= tail_pack[9]; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to get the value of write counter within the RPMB partition. + * @param hmmc Pointer to MMC handle + * @param pNonce pointer to the value of nonce (16 bytes) + * @param Timeout Specify timeout value + * @retval write counter value. + */ +uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint32_t dataremaining; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + uint8_t echo_nonce[16] = {0}; + uint8_t *tempbuff = zero_pack; + + tail_pack[11] = 0x02; + + if (NULL == pNonce) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Send Request Packet */ + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*tempbuff); + tempbuff++; + byte_count++; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + byte_count++; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + byte_count++; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = (uint8_t *)pNonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packt */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + + byte_count = 0; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = echo_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + for (uint8_t i = 0; i < 16U; i++) + { + if (pNonce[i] != echo_nonce[i]) + { + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + } + + return ((uint32_t)tail_pack[3] | ((uint32_t)tail_pack[2] << 8) | ((uint32_t)tail_pack[1] << 16) | \ + ((uint32_t)tail_pack[0] << 24)); + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } +} + +/** + * @brief Allows to write block(s) to a specified address in the RPMB partition. The Data + * transfer is managed by polling mode. + * @param hmmc Pointer to MMC handle + * @param pData Pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of blocks to write + * @param pMAC Pointer to the authentication MAC buffer + * @param Timeout Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout) +{ + + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint32_t dataremaining; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + uint8_t echo_nonce[16] = {0}; + const uint8_t local_nonce[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x00, 0x01, 0x02, + 0x03, 0x04, 0x00, 0x01, 0x02, 0x03, 0x04, 0x08 + }; + const uint8_t *rtempbuff; + uint8_t *tempbuff; + uint32_t arg = 0x80000000U; + uint32_t offset = 0; + + if ((NumberOfBlocks != 0x1U) && (NumberOfBlocks != 0x2U) && (NumberOfBlocks != 0x20U)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if ((NULL == pData) || (NULL == pMAC)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + tail_pack[11] = 0x02; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send Request Packet */ + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + rtempbuff = zero_pack; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + rtempbuff = local_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packt */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + + byte_count = 0; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = echo_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + for (uint8_t i = 0; i < 16U; i++) + { + if (local_nonce[i] != echo_nonce[i]) + { + return HAL_ERROR; + } + } + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } + tail_pack[11] = 0x03; + tail_pack[10] = 0x00; + tail_pack[7] = (uint8_t)(NumberOfBlocks) & 0xFFU; + tail_pack[6] = (uint8_t)(NumberOfBlocks >> 8) & 0xFFU; + tail_pack[5] = (uint8_t)(BlockAdd) & 0xFFU; + tail_pack[4] = (uint8_t)(BlockAdd >> 8) & 0xFFU; + + rtempbuff = zero_pack; + byte_count = 0; + arg |= NumberOfBlocks; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send Request Packet */ + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count == MMC_RPMB_KEYMAC_POSITION) + { + rtempbuff = pMAC; + } + if (byte_count == MMC_RPMB_DATA_POSITION) + { + rtempbuff = &pData[offset]; + } + if ((byte_count >= MMC_RPMB_NONCE_POSITION) && \ + (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION)) + { + rtempbuff = zero_pack; + } + if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else if (byte_count == MMC_BLOCKSIZE) + { + offset += (uint32_t)256U; + byte_count = 0; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Response Packet */ + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + + { + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + byte_count = 0; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + /* Check result of operation */ + if (((tail_pack[9] & (uint8_t)0xFEU) != 0x00U) || (tail_pack[10] != 0x03U)) + { + hmmc->RPMBErrorCode |= tail_pack[9]; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to read block(s) to a specified address in the RPMB partition. The Data + * transfer is managed by polling mode. + * @param hmmc Pointer to MMC handle + * @param pData Pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of blocks to write + * @param pNonce Pointer to the buffer that will contain the nonce to transmit + * @param pMAC Pointer to the authentication MAC buffer + * @param Timeout Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC, + uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + uint8_t echo_nonce[16] = {0}; + uint32_t dataremaining; + const uint8_t *rtempbuff; + uint8_t *tempbuff; + uint32_t arg = 0; + uint32_t offset = 0; + + arg |= NumberOfBlocks; + + tail_pack[11] = 0x04; + tail_pack[10] = 0x00; + tail_pack[7] = 0x00; + tail_pack[6] = 0x00; + tail_pack[5] = (uint8_t)(BlockAdd) & 0xFFU; + tail_pack[4] = (uint8_t)(BlockAdd >> 8) & 0xFFU; + tail_pack[3] = 0x00; + tail_pack[2] = 0x00; + tail_pack[1] = 0x00; + tail_pack[0] = 0x00; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 1); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send Request Packet */ + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + rtempbuff = zero_pack; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + rtempbuff = pNonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packet */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + byte_count = 0; + + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_KEYMAC_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_KEYMAC_POSITION) + { + tempbuff = (uint8_t *)pMAC; + } + else if (byte_count == MMC_RPMB_DATA_POSITION) + { + tempbuff = &pData[offset]; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = echo_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else if (byte_count == MMC_BLOCKSIZE) + { + byte_count = 0; + offset += (uint32_t)256U; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + for (uint8_t i = 0; i < 16U; i++) + { + if (pNonce[i] != echo_nonce[i]) + { + return HAL_ERROR; + } + } + + /* Check result of operation */ + if ((tail_pack[9] != 0x00U) || (tail_pack[10] != 0x04U)) + { + hmmc->RPMBErrorCode |= tail_pack[9]; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + + +/** + * @brief Read DMA Linked list node Transfer completed callbacks + * @param hmmc MMC handle + * @retval None + */ +__weak void HAL_MMCEx_Read_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMCEx_Read_DMALnkLstBufCpltCallback can be implemented in the user file + */ +} +/** + * @brief Read DMA Linked list node Transfer completed callbacks + * @param hmmc MMC handle + * @retval None + */ +__weak void HAL_MMCEx_Write_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMCEx_Write_DMALnkLstBufCpltCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +#endif /* HAL_MMC_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mmc_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mmc_ex.c new file mode 100644 index 00000000000..a067070ed3a --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_mmc_ex.c @@ -0,0 +1,448 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_mmc_ex.c + * @author MCD Application Team + * @brief MMC card Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital (MMC) peripheral: + * + Extended features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The MMC Extension HAL driver can be used as follows: + (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function. + + (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and + HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup MMCEx MMCEx + * @brief MMC Extended HAL module driver + * @{ + */ + +#if defined (SDMMC1) || defined (SDMMC2) +#ifdef HAL_MMC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup MMCEx_Exported_Functions + * @{ + */ + + + +/** @addtogroup MMCEx_Exported_Functions_Group1 + * @brief Linked List management functions + * +@verbatim + =============================================================================== + ##### Linked List management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the needed functions. + +@endverbatim + * @{ + */ + +/** + * @brief Build Linked List node. + * @param pNode: Pointer to new node to add. + * @param pNodeConf: Pointer to configuration parameters for new node to add. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_BuildNode(MMC_DMALinkNodeTypeDef *pNode, + MMC_DMALinkNodeConfTypeDef *pNodeConf) +{ + + if (SDMMC_DMALinkedList_BuildNode(pNode, pNodeConf) != SDMMC_ERROR_NONE) + { + return (HAL_ERROR); + } + else + { + return (HAL_OK); + } + +} +/** + * @brief Insert Linked List node. + * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes + * @param pPrevNode: Pointer to previous node. + * @param pNewNode: Pointer to new node to insert. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_InsertNode(MMC_DMALinkedListTypeDef *pLinkedList, + MMC_DMALinkNodeTypeDef *pPrevNode, + MMC_DMALinkNodeTypeDef *pNewNode) +{ + + if (SDMMC_DMALinkedList_InsertNode(pLinkedList, pPrevNode, pNewNode) != SDMMC_ERROR_NONE) + { + return (HAL_ERROR); + } + else + { + return (HAL_OK); + } + +} +/** + * @brief Remove Linked List node. + * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes + * @param pNode: Pointer to node to remove. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_RemoveNode(MMC_DMALinkedListTypeDef *pLinkedList, + MMC_DMALinkNodeTypeDef *pNode) +{ + + if (SDMMC_DMALinkedList_RemoveNode(pLinkedList, pNode) != SDMMC_ERROR_NONE) + { + return (HAL_ERROR); + } + else + { + return (HAL_OK); + } +} + +/** + * @brief Lock Linked List node. + * @param pNode: Pointer to node to remove. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_LockNode(MMC_DMALinkNodeTypeDef *pNode) +{ + + if (SDMMC_DMALinkedList_LockNode(pNode) != SDMMC_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Unlock Linked List node. + * @param pNode: Pointer to node to remove. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_UnlockNode(MMC_DMALinkNodeTypeDef *pNode) +{ + + if (SDMMC_DMALinkedList_UnlockNode(pNode) != SDMMC_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Enable Circular mode for DMA Linked List mode. + * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_EnableCircularMode(MMC_DMALinkedListTypeDef *pLinkedList) +{ + + if (SDMMC_DMALinkedList_EnableCircularMode(pLinkedList) != SDMMC_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} +/** + * @brief Disable Circular mode for DMA Linked List mode. + * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_DisableCircularMode(MMC_DMALinkedListTypeDef *pLinkedList) +{ + + if (SDMMC_DMALinkedList_DisableCircularMode(pLinkedList) != SDMMC_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + + +/** + * @brief Reads block(s) from a specified address in a card. The received Data will be stored in linked list buffers. + * linked list should be prepared before call this function . + * @param hmmc: MMC handle + * @param pLinkedList: pointer to first linked list node + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Total number of blocks to read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, MMC_DMALinkedListTypeDef *pLinkedList, + uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t DmaBase0_reg; + uint32_t DmaBase1_reg; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + + hmmc->Instance->IDMABASER = (uint32_t) pLinkedList->pHeadNode->IDMABASER; + hmmc->Instance->IDMABSIZE = (uint32_t) pLinkedList->pHeadNode->IDMABSIZE; + hmmc->Instance->IDMABAR = (uint32_t) pLinkedList->pHeadNode; + hmmc->Instance->IDMALAR = (uint32_t) SDMMC_IDMALAR_ABR | SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ULA | + sizeof(SDMMC_DMALinkNodeTypeDef) ; /* Initial configuration */ + + DmaBase0_reg = hmmc->Instance->IDMABASER; + DmaBase1_reg = hmmc->Instance->IDMABAR; + + if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U)) + { + hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; + + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; + + /* Read Blocks in DMA mode */ + hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + +} + +/** + * @brief Write block(s) to a specified address in a card. The transferred Data are stored linked list nodes buffers . + * linked list should be prepared before call this function . + * @param hmmc: MMC handle + * @param pLinkedList: pointer to first linked list node + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Total number of blocks to read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, MMC_DMALinkedListTypeDef *pLinkedList, + uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t DmaBase0_reg; + uint32_t DmaBase1_reg; + uint32_t add = BlockAdd; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + + hmmc->Instance->IDMABASER = (uint32_t) pLinkedList->pHeadNode->IDMABASER; + hmmc->Instance->IDMABSIZE = (uint32_t) pLinkedList->pHeadNode->IDMABSIZE; + + hmmc->Instance->IDMABAR = (uint32_t) pLinkedList->pHeadNode; + hmmc->Instance->IDMALAR = (uint32_t) SDMMC_IDMALAR_ABR | SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ULA | + sizeof(SDMMC_DMALinkNodeTypeDef) ; /* Initial configuration */ + + DmaBase0_reg = hmmc->Instance->IDMABASER; + DmaBase1_reg = hmmc->Instance->IDMABAR; + + if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U)) + { + hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + hmmc->State = HAL_MMC_STATE_BUSY; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; + + /* Write Blocks in DMA mode */ + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MMC_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_msp_template.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_msp_template.c new file mode 100644 index 00000000000..39f93844de2 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_msp_template.c @@ -0,0 +1,97 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_msp.c + * @author MCD Application Team + * @brief HAL MSP module. + * This file should be copied to the application folder and renamed + * to stm32h7rsxx_hal_msp.c + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup HAL_MSP HAL MSP module driver + * @brief HAL MSP module. + * @{ + */ + +/* Private typedefs ----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HAL_MSP_Private_Functions + * @{ + */ + +/** + * @brief Initialize the Global MSP. + * @retval None + */ +void HAL_MspInit(void) +{ + /* NOTE : This function is generated automatically by STM32CubeMX and eventually + modified by the user + */ +} + +/** + * @brief DeInitialize the Global MSP. + * @retval None + */ +void HAL_MspDeInit(void) +{ + /* NOTE : This function is generated automatically by STM32CubeMX and eventually + modified by the user + */ +} + +/** + * @brief Initialize the PPP MSP. + * @retval None + */ +/* +void HAL_PPP_MspInit(void) +{ +} +*/ + +/** + * @brief DeInitialize the PPP MSP. + * @retval None + */ +/* +void HAL_PPP_MspDeInit(void) +{ +} +*/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_nand.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_nand.c new file mode 100644 index 00000000000..e78e1f41b6a --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_nand.c @@ -0,0 +1,2231 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_nand.c + * @author MCD Application Team + * @brief NAND HAL module driver. + * This file provides a generic firmware to drive NAND memories mounted + * as external device. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a generic layered driver which contains a set of APIs used to + control NAND flash memories. It uses the FMC layer functions to interface + with NAND devices. This driver is used as follows: + + (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() + with control and timing parameters for both common and attribute spaces. + + (+) Read NAND flash memory maker and device IDs using the function + HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef + structure declared by the function caller. + + (+) Access NAND flash memory by read/write operations using the functions + HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(), + HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(), + HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(), + HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b() + to read/write page(s)/spare area(s). These functions use specific device + information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef + structure. The read/write address information is contained by the Nand_Address_Typedef + structure passed as parameter. + + (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset(). + + (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block(). + The erase block address information is contained in the Nand_Address_Typedef + structure passed as parameter. + + (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status(). + + (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/ + HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction + feature or the function HAL_NAND_GetECC() to get the ECC correction code. + + (+) You can monitor the NAND device HAL state by calling the function + HAL_NAND_GetState() + + [..] + (@) This driver is a set of generic APIs which handle standard NAND flash operations. + If a NAND flash device contains different operations and/or implementations, + it should be implemented separately. + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_NAND_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) MspInitCallback : NAND MspInit. + (+) MspDeInitCallback : NAND MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. It allows to reset following callbacks: + (+) MspInitCallback : NAND MspInit. + (+) MspDeInitCallback : NAND MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET + all callbacks are reset to the corresponding legacy weak (overridden) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (overridden) functions in the HAL_NAND_Init + and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit + or HAL_NAND_Init function. + + When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (overridden) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#ifdef HAL_NAND_MODULE_ENABLED + +/** @defgroup NAND NAND + * @brief NAND HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private Constants ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup NAND_Exported_Functions NAND Exported Functions + * @{ + */ + +/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### NAND Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize + the NAND memory + +@endverbatim + * @{ + */ + +/** + * @brief Perform NAND memory Initialization sequence + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param ComSpace_Timing pointer to Common space timing structure + * @param AttSpace_Timing pointer to Attribute space timing structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, + FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) +{ + /* Check the NAND handle state */ + if (hnand == NULL) + { + return HAL_ERROR; + } + + if (hnand->State == HAL_NAND_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hnand->Lock = HAL_UNLOCKED; + +#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) + if (hnand->MspInitCallback == NULL) + { + hnand->MspInitCallback = HAL_NAND_MspInit; + } + hnand->ItCallback = HAL_NAND_ITCallback; + + /* Init the low level hardware */ + hnand->MspInitCallback(hnand); +#else + /* Initialize the low level hardware (MSP) */ + HAL_NAND_MspInit(hnand); +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ + } + + /* Initialize NAND control Interface */ + (void)FMC_NAND_Init(hnand->Instance, &(hnand->Init)); + + /* Initialize NAND common space timing Interface */ + (void)FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank); + + /* Initialize NAND attribute space timing Interface */ + (void)FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank); + + /* Enable the NAND device */ + __FMC_NAND_ENABLE(hnand->Instance); + + /* Enable FMC Peripheral */ + __FMC_ENABLE(); + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Perform NAND memory De-Initialization sequence + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) +{ +#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) + if (hnand->MspDeInitCallback == NULL) + { + hnand->MspDeInitCallback = HAL_NAND_MspDeInit; + } + + /* DeInit the low level hardware */ + hnand->MspDeInitCallback(hnand); +#else + /* Initialize the low level hardware (MSP) */ + HAL_NAND_MspDeInit(hnand); +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ + + /* Configure the NAND registers with their reset values */ + (void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank); + + /* Reset the NAND controller state */ + hnand->State = HAL_NAND_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief NAND MSP Init + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @retval None + */ +__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hnand); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_NAND_MspInit could be implemented in the user file + */ +} + +/** + * @brief NAND MSP DeInit + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @retval None + */ +__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hnand); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_NAND_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief This function handles NAND device interrupt request. + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @retval HAL status + */ +void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) +{ + /* Check NAND interrupt Rising edge flag */ + if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE)) + { + /* NAND interrupt callback*/ +#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) + hnand->ItCallback(hnand); +#else + HAL_NAND_ITCallback(hnand); +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ + + /* Clear NAND interrupt Rising edge pending bit */ + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE); + } + + /* Check NAND interrupt Level flag */ + if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL)) + { + /* NAND interrupt callback*/ +#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) + hnand->ItCallback(hnand); +#else + HAL_NAND_ITCallback(hnand); +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ + + /* Clear NAND interrupt Level pending bit */ + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL); + } + + /* Check NAND interrupt Falling edge flag */ + if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE)) + { + /* NAND interrupt callback*/ +#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) + hnand->ItCallback(hnand); +#else + HAL_NAND_ITCallback(hnand); +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ + + /* Clear NAND interrupt Falling edge pending bit */ + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE); + } + + /* Check NAND interrupt FIFO empty flag */ + if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT)) + { + /* NAND interrupt callback*/ +#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) + hnand->ItCallback(hnand); +#else + HAL_NAND_ITCallback(hnand); +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ + + /* Clear NAND interrupt FIFO empty pending bit */ + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT); + } + +} + +/** + * @brief NAND interrupt feature callback + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @retval None + */ +__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hnand); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_NAND_ITCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions + * + @verbatim + ============================================================================== + ##### NAND Input and Output functions ##### + ============================================================================== + [..] + This section provides functions allowing to use and control the NAND + memory + +@endverbatim + * @{ + */ + +/** + * @brief Read the NAND memory electronic signature + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pNAND_ID NAND ID structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID) +{ + __IO uint32_t data = 0; + __IO uint32_t data1 = 0; + uint32_t deviceaddress; + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ + deviceaddress = NAND_DEVICE; + + /* Send Read ID command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + __DSB(); + + /* Read the electronic signature from NAND flash */ + if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) + { + data = *(__IO uint32_t *)deviceaddress; + + /* Return the data read */ + pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); + pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); + pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); + pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); + } + else + { + data = *(__IO uint32_t *)deviceaddress; + data1 = *((__IO uint32_t *)deviceaddress + 4); + + /* Return the data read */ + pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); + pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data); + pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1); + pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief NAND memory reset + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) +{ + uint32_t deviceaddress; + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ + deviceaddress = NAND_DEVICE; + + /* Send NAND reset command */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; + +} + +/** + * @brief Configure the device: Enter the physical parameters of the device + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) +{ + hnand->Config.PageSize = pDeviceConfig->PageSize; + hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize; + hnand->Config.BlockSize = pDeviceConfig->BlockSize; + hnand->Config.BlockNbr = pDeviceConfig->BlockNbr; + hnand->Config.PlaneSize = pDeviceConfig->PlaneSize; + hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr; + hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable; + + return HAL_OK; +} + +/** + * @brief Read Page(s) from NAND memory block (8-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to destination read buffer + * @param NumPageToRead number of pages to read from block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumPageToRead) +{ + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numpagesread = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToRead; + uint8_t *buff = pBuffer; + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ + deviceaddress = NAND_DEVICE; + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) read loop */ + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* Send read page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + + if (hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + __DSB(); + } + + /* Get Data into Buffer */ + for (index = 0U; index < hnand->Config.PageSize; index++) + { + *buff = *(uint8_t *)deviceaddress; + buff++; + } + + /* Increment read pages number */ + numpagesread++; + + /* Decrement pages to read */ + nbpages--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Read Page(s) from NAND memory block (16-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned + * @param NumPageToRead number of pages to read from block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumPageToRead) +{ + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numpagesread = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToRead; + uint16_t *buff = pBuffer; + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ + deviceaddress = NAND_DEVICE; + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) read loop */ + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* Send read page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + if (hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + __DSB(); + } + + /* Calculate PageSize */ + if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) + { + hnand->Config.PageSize = hnand->Config.PageSize / 2U; + } + else + { + /* Do nothing */ + /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ + } + + /* Get Data into Buffer */ + for (index = 0U; index < hnand->Config.PageSize; index++) + { + *buff = *(uint16_t *)deviceaddress; + buff++; + } + + /* Increment read pages number */ + numpagesread++; + + /* Decrement pages to read */ + nbpages--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Write Page(s) to NAND memory block (8-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write + * @param NumPageToWrite number of pages to write to block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumPageToWrite) +{ + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numpageswritten = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToWrite; + const uint8_t *buff = pBuffer; + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ + deviceaddress = NAND_DEVICE; + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) write loop */ + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + + /* Write data to memory */ + for (index = 0U; index < hnand->Config.PageSize; index++) + { + *(__IO uint8_t *)deviceaddress = *buff; + buff++; + __DSB(); + } + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + + /* Increment written pages number */ + numpageswritten++; + + /* Decrement pages to write */ + nbpages--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Write Page(s) to NAND memory block (16-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned + * @param NumPageToWrite number of pages to write to block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumPageToWrite) +{ + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numpageswritten = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToWrite; + const uint16_t *buff = pBuffer; + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ + deviceaddress = NAND_DEVICE; + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) write loop */ + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + + /* Calculate PageSize */ + if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) + { + hnand->Config.PageSize = hnand->Config.PageSize / 2U; + } + else + { + /* Do nothing */ + /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ + } + + /* Write data to memory */ + for (index = 0U; index < hnand->Config.PageSize; index++) + { + *(__IO uint16_t *)deviceaddress = *buff; + buff++; + __DSB(); + } + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + + /* Increment written pages number */ + numpageswritten++; + + /* Decrement pages to write */ + nbpages--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Read Spare area(s) from NAND memory (8-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write + * @param NumSpareAreaToRead Number of spare area to read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaToRead) +{ + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numsparearearead = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaToRead; + uint8_t *buff = pBuffer; + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ + deviceaddress = NAND_DEVICE; + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnaddress = COLUMN_ADDRESS(hnand); + + /* Spare area(s) read loop */ + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + if (hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + __DSB(); + } + + /* Get Data into Buffer */ + for (index = 0U; index < hnand->Config.SpareAreaSize; index++) + { + *buff = *(uint8_t *)deviceaddress; + buff++; + } + + /* Increment read spare areas number */ + numsparearearead++; + + /* Decrement spare areas to read */ + nbspare--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Read Spare area(s) from NAND memory (16-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. + * @param NumSpareAreaToRead Number of spare area to read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaToRead) +{ + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numsparearearead = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaToRead; + uint16_t *buff = pBuffer; + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ + deviceaddress = NAND_DEVICE; + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); + + /* Spare area(s) read loop */ + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + if (hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + __DSB(); + } + + /* Get Data into Buffer */ + for (index = 0U; index < hnand->Config.SpareAreaSize; index++) + { + *buff = *(uint16_t *)deviceaddress; + buff++; + } + + /* Increment read spare areas number */ + numsparearearead++; + + /* Decrement spare areas to read */ + nbspare--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Write Spare area(s) to NAND memory (8-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write + * @param NumSpareAreaTowrite number of spare areas to write to block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) +{ + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numspareareawritten = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaTowrite; + const uint8_t *buff = pBuffer; + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ + deviceaddress = NAND_DEVICE; + + /* Page address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnaddress = COLUMN_ADDRESS(hnand); + + /* Spare area(s) write loop */ + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + + /* Write data to memory */ + for (index = 0U; index < hnand->Config.SpareAreaSize; index++) + { + *(__IO uint8_t *)deviceaddress = *buff; + buff++; + __DSB(); + } + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + + /* Increment written spare areas number */ + numspareareawritten++; + + /* Decrement spare areas to write */ + nbspare--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Write Spare area(s) to NAND memory (16-bits addressing) + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. + * @param NumSpareAreaTowrite number of spare areas to write to block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, + const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) +{ + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numspareareawritten = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaTowrite; + const uint16_t *buff = pBuffer; + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ + deviceaddress = NAND_DEVICE; + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); + + /* Spare area(s) write loop */ + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + + /* Write data to memory */ + for (index = 0U; index < hnand->Config.SpareAreaSize; index++) + { + *(__IO uint16_t *)deviceaddress = *buff; + buff++; + __DSB(); + } + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + + /* Increment written spare areas number */ + numspareareawritten++; + + /* Decrement spare areas to write */ + nbspare--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief NAND memory Block erase + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress) +{ + uint32_t deviceaddress; + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ + deviceaddress = NAND_DEVICE; + + /* Send Erase block command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; + __DSB(); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Increment the NAND memory address + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress pointer to NAND address structure + * @retval The new status of the increment address operation. It can be: + * - NAND_VALID_ADDRESS: When the new address is valid address + * - NAND_INVALID_ADDRESS: When the new address is invalid address + */ +uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) +{ + uint32_t status = NAND_VALID_ADDRESS; + + /* Increment page address */ + pAddress->Page++; + + /* Check NAND address is valid */ + if (pAddress->Page == hnand->Config.BlockSize) + { + pAddress->Page = 0; + pAddress->Block++; + + if (pAddress->Block == hnand->Config.PlaneSize) + { + pAddress->Block = 0; + pAddress->Plane++; + + if (pAddress->Plane == (hnand->Config.PlaneNbr)) + { + status = NAND_INVALID_ADDRESS; + } + } + } + + return (status); +} + +#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User NAND Callback + * To be used to override the weak predefined callback + * @param hnand : NAND handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID + * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID + * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, + pNAND_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + if (hnand->State == HAL_NAND_STATE_READY) + { + switch (CallbackId) + { + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = pCallback; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = pCallback; + break; + case HAL_NAND_IT_CB_ID : + hnand->ItCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hnand->State == HAL_NAND_STATE_RESET) + { + switch (CallbackId) + { + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = pCallback; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User NAND Callback + * NAND Callback is redirected to the weak predefined callback + * @param hnand : NAND handle + * @param CallbackId : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID + * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID + * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hnand->State == HAL_NAND_STATE_READY) + { + switch (CallbackId) + { + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = HAL_NAND_MspInit; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = HAL_NAND_MspDeInit; + break; + case HAL_NAND_IT_CB_ID : + hnand->ItCallback = HAL_NAND_ITCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hnand->State == HAL_NAND_STATE_RESET) + { + switch (CallbackId) + { + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = HAL_NAND_MspInit; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = HAL_NAND_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### NAND Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the NAND interface. + +@endverbatim + * @{ + */ + + +/** + * @brief Enables dynamically NAND ECC feature. + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) +{ + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Enable ECC feature */ + (void)FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank); + + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_NAND ECC feature. + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) +{ + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Disable ECC feature */ + (void)FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank); + + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disables dynamically NAND ECC feature. + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param ECCval pointer to ECC value + * @param Timeout maximum timeout to wait + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Get NAND ECC value */ + status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout); + + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return status; +} + +/** + * @} + */ + + +/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### NAND State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the NAND controller + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief return the NAND state + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @retval HAL state + */ +HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand) +{ + return hnand->State; +} + +/** + * @brief NAND memory read status + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @retval NAND status + */ +uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand) +{ + uint32_t data; + uint32_t deviceaddress; + UNUSED(hnand); + + /* Identify the device address */ + deviceaddress = NAND_DEVICE; + + /* Send Read status operation command */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; + + /* Read status register data */ + data = *(__IO uint8_t *)deviceaddress; + + /* Return the status */ + if ((data & NAND_ERROR) == NAND_ERROR) + { + return NAND_ERROR; + } + else if ((data & NAND_READY) == NAND_READY) + { + return NAND_READY; + } + else + { + return NAND_BUSY; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_NAND_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_nor.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_nor.c new file mode 100644 index 00000000000..627e959d08d --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_nor.c @@ -0,0 +1,1642 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_nor.c + * @author MCD Application Team + * @brief NOR HAL module driver. + * This file provides a generic firmware to drive NOR memories mounted + * as external device. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a generic layered driver which contains a set of APIs used to + control NOR flash memories. It uses the FMC layer functions to interface + with NOR devices. This driver is used as follows: + + (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() + with control and timing parameters for both normal and extended mode. + + (+) Read NOR flash memory manufacturer code and device IDs using the function + HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef + structure declared by the function caller. + + (+) Access NOR flash memory by read/write data unit operations using the functions + HAL_NOR_Read(), HAL_NOR_Program(). + + (+) Perform NOR flash erase block/chip operations using the functions + HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip(). + + (+) Read the NOR flash CFI (common flash interface) IDs using the function + HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef + structure declared by the function caller. + + (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/ + HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation + + (+) You can monitor the NOR device HAL state by calling the function + HAL_NOR_GetState() + [..] + (@) This driver is a set of generic APIs which handle standard NOR flash operations. + If a NOR flash device contains different operations and/or implementations, + it should be implemented separately. + + *** NOR HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in NOR HAL driver. + + (+) NOR_WRITE : NOR memory write data to specified address + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_NOR_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) MspInitCallback : NOR MspInit. + (+) MspDeInitCallback : NOR MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. It allows to reset following callbacks: + (+) MspInitCallback : NOR MspInit. + (+) MspDeInitCallback : NOR MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET + all callbacks are reset to the corresponding legacy weak (overridden) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (overridden) functions in the HAL_NOR_Init + and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit + or HAL_NOR_Init function. + + When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (overridden) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#ifdef HAL_NOR_MODULE_ENABLED + +/** @defgroup NOR NOR + * @brief NOR driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup NOR_Private_Defines NOR Private Defines + * @{ + */ + +/* Constants to define address to set to write a command */ +#define NOR_CMD_ADDRESS_FIRST_BYTE (uint16_t)0x0AAA +#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE (uint16_t)0x00AA +#define NOR_CMD_ADDRESS_SECOND_BYTE (uint16_t)0x0555 +#define NOR_CMD_ADDRESS_THIRD_BYTE (uint16_t)0x0AAA + +#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 +#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 +#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA +#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555 +#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555 +#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA +#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555 + +/* Constants to define data to program a command */ +#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0 +#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA +#define NOR_CMD_DATA_SECOND (uint16_t)0x0055 +#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090 +#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0 +#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080 +#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA +#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055 +#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010 +#define NOR_CMD_DATA_CFI (uint16_t)0x0098 + +#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25 +#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29 +#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30 + +#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF +#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040 +#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8 +#define NOR_CMD_CONFIRM (uint16_t)0x00D0 +#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020 +#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060 +#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070 +#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050 + +/* Mask on NOR STATUS REGISTER */ +#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010 +#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020 +#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040 +#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080 + +/* Address of the primary command set */ +#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013 + +/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */ +#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */ +#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */ +#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */ +#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */ +#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */ +#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */ +#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */ +#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */ +#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */ +#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup NOR_Private_Variables NOR Private Variables + * @{ + */ + +static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup NOR_Exported_Functions NOR Exported Functions + * @{ + */ + +/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### NOR Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize + the NOR memory + +@endverbatim + * @{ + */ + +/** + * @brief Perform the NOR memory Initialization sequence + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param Timing pointer to NOR control timing structure + * @param ExtTiming pointer to NOR extended mode timing structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming) +{ + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the NOR handle parameter */ + if (hnor == NULL) + { + return HAL_ERROR; + } + + if (hnor->State == HAL_NOR_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hnor->Lock = HAL_UNLOCKED; + +#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) + if (hnor->MspInitCallback == NULL) + { + hnor->MspInitCallback = HAL_NOR_MspInit; + } + + /* Init the low level hardware */ + hnor->MspInitCallback(hnor); +#else + /* Initialize the low level hardware (MSP) */ + HAL_NOR_MspInit(hnor); +#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */ + } + + /* Initialize NOR control Interface */ + (void)FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); + + /* Initialize NOR timing Interface */ + (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); + + /* Initialize NOR extended mode timing Interface */ + (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, + hnor->Init.NSBank, hnor->Init.ExtendedMode); + + /* Enable the NORSRAM device */ + __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); + + /* Initialize NOR Memory Data Width*/ + if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8) + { + uwNORMemoryDataWidth = NOR_MEMORY_8B; + } + else + { + uwNORMemoryDataWidth = NOR_MEMORY_16B; + } + + /* Enable FMC Peripheral */ + __FMC_ENABLE(); + + /* Initialize the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE) + { + (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_PROTECTED; + } + else + { + /* Get the value of the command set */ + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), + NOR_CMD_DATA_CFI); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + } + + hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); + + status = HAL_NOR_ReturnToReadMode(hnor); + } + + return status; +} + +/** + * @brief Perform NOR memory De-Initialization sequence + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) +{ +#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) + if (hnor->MspDeInitCallback == NULL) + { + hnor->MspDeInitCallback = HAL_NOR_MspDeInit; + } + + /* DeInit the low level hardware */ + hnor->MspDeInitCallback(hnor); +#else + /* De-Initialize the low level hardware (MSP) */ + HAL_NOR_MspDeInit(hnor); +#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */ + + /* Configure the NOR registers with their reset values */ + (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); + + /* Reset the NOR controller state */ + hnor->State = HAL_NOR_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hnor); + + return HAL_OK; +} + +/** + * @brief NOR MSP Init + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @retval None + */ +__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hnor); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_NOR_MspInit could be implemented in the user file + */ +} + +/** + * @brief NOR MSP DeInit + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @retval None + */ +__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hnor); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_NOR_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief NOR MSP Wait for Ready/Busy signal + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param Timeout Maximum timeout value + * @retval None + */ +__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hnor); + UNUSED(Timeout); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_NOR_MspWait could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions + * + @verbatim + ============================================================================== + ##### NOR Input and Output functions ##### + ============================================================================== + [..] + This section provides functions allowing to use and control the NOR memory + +@endverbatim + * @{ + */ + +/** + * @brief Read NOR flash IDs + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param pNOR_ID pointer to NOR ID structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) +{ + uint32_t deviceaddress; + HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the NOR controller state */ + state = hnor->State; + if (state == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Send read ID command */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_AUTO_SELECT); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_AUTO_SELECT); + } + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + if (status != HAL_ERROR) + { + /* Read the NOR IDs */ + pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); + pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE1_ADDR); + pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE2_ADDR); + pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE3_ADDR); + } + + /* Check the NOR controller state */ + hnor->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return status; +} + +/** + * @brief Returns the NOR memory to Read mode. + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) +{ + uint32_t deviceaddress; + HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the NOR controller state */ + state = hnor->State; + if (state == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + /* Check the NOR controller state */ + hnor->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return status; +} + +/** + * @brief Read data from NOR memory + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param pAddress pointer to Device address + * @param pData pointer to read data + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) +{ + uint32_t deviceaddress; + HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the NOR controller state */ + state = hnor->State; + if (state == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Send read data command */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_READ_RESET); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_READ_RESET); + } + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + if (status != HAL_ERROR) + { + /* Read the data */ + *pData = (uint16_t)(*(__IO uint32_t *)pAddress); + } + + /* Check the NOR controller state */ + hnor->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return status; +} + +/** + * @brief Program data to NOR memory + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param pAddress Device address + * @param pData pointer to the data to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) +{ + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the NOR controller state */ + if (hnor->State == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnor->State == HAL_NOR_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Send program data command */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_PROGRAM); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + } + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + if (status != HAL_ERROR) + { + /* Write the data */ + NOR_WRITE(pAddress, *pData); + } + + /* Check the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return status; +} + +/** + * @brief Reads a half-word buffer from the NOR memory. + * @param hnor pointer to the NOR handle + * @param uwAddress NOR memory internal address to read from. + * @param pData pointer to the buffer that receives the data read from the + * NOR memory. + * @param uwBufferSize number of Half word to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize) +{ + uint32_t deviceaddress; + uint32_t size = uwBufferSize; + uint32_t address = uwAddress; + uint16_t *data = pData; + HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the NOR controller state */ + state = hnor->State; + if (state == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Send read data command */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_READ_RESET); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_READ_RESET); + } + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + if (status != HAL_ERROR) + { + /* Read buffer */ + while (size > 0U) + { + *data = *(__IO uint16_t *)address; + data++; + address += 2U; + size--; + } + } + + /* Check the NOR controller state */ + hnor->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return status; +} + +/** + * @brief Writes a half-word buffer to the NOR memory. This function must be used + only with S29GL128P NOR memory. + * @param hnor pointer to the NOR handle + * @param uwAddress NOR memory internal start write address + * @param pData pointer to source data buffer. + * @param uwBufferSize Size of the buffer to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize) +{ + uint16_t *p_currentaddress; + const uint16_t *p_endaddress; + uint16_t *data = pData; + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the NOR controller state */ + if (hnor->State == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnor->State == HAL_NOR_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Initialize variables */ + p_currentaddress = (uint16_t *)(deviceaddress + uwAddress); + p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U))); + + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + } + else + { + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + } + /* Write Buffer Load Command */ + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); + NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + /* Write Buffer Load Command */ + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM); + NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + if (status != HAL_ERROR) + { + /* Load Data into NOR Buffer */ + while (p_currentaddress <= p_endaddress) + { + NOR_WRITE(p_currentaddress, *data); + + data++; + p_currentaddress ++; + } + + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); + } + else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */ + { + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM); + } + } + + /* Check the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return status; + +} + +/** + * @brief Erase the specified block of the NOR memory + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param BlockAddress Block to erase address + * @param Address Device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) +{ + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the NOR controller state */ + if (hnor->State == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnor->State == HAL_NOR_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Send block erase command sequence */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + } + NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK); + NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM); + NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE); + NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + /* Check the NOR memory status and update the controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return status; + +} + +/** + * @brief Erase the entire NOR chip. + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param Address Device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) +{ + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; + UNUSED(Address); + + /* Check the NOR controller state */ + if (hnor->State == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hnor->State == HAL_NOR_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Send NOR chip erase command sequence */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), + NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), + NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), + NOR_CMD_DATA_CHIP_ERASE); + } + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + /* Check the NOR memory status and update the controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return status; +} + +/** + * @brief Read NOR flash CFI IDs + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param pNOR_CFI pointer to NOR CFI IDs structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) +{ + uint32_t deviceaddress; + HAL_NOR_StateTypeDef state; + + /* Check the NOR controller state */ + state = hnor->State; + if (state == HAL_NOR_STATE_BUSY) + { + return HAL_BUSY; + } + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Send read CFI query command */ + if (uwNORMemoryDataWidth == NOR_MEMORY_8B) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), + NOR_CMD_DATA_CFI); + } + else + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + } + /* read the NOR CFI information */ + pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); + pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); + pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS); + pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS); + + /* Check the NOR controller state */ + hnor->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User NOR Callback + * To be used to override the weak predefined callback + * @param hnor : NOR handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID + * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, + pNOR_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_NOR_StateTypeDef state; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + state = hnor->State; + if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_NOR_MSP_INIT_CB_ID : + hnor->MspInitCallback = pCallback; + break; + case HAL_NOR_MSP_DEINIT_CB_ID : + hnor->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User NOR Callback + * NOR Callback is redirected to the weak predefined callback + * @param hnor : NOR handle + * @param CallbackId : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID + * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_NOR_StateTypeDef state; + + state = hnor->State; + if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_NOR_MSP_INIT_CB_ID : + hnor->MspInitCallback = HAL_NOR_MspInit; + break; + case HAL_NOR_MSP_DEINIT_CB_ID : + hnor->MspDeInitCallback = HAL_NOR_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */ + +/** + * @} + */ + +/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### NOR Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the NOR interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically NOR write operation. + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) +{ + /* Check the NOR controller state */ + if (hnor->State == HAL_NOR_STATE_PROTECTED) + { + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Enable write operation */ + (void)FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disables dynamically NOR write operation. + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) +{ + /* Check the NOR controller state */ + if (hnor->State == HAL_NOR_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Disable write operation */ + (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_PROTECTED; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup NOR_Exported_Functions_Group4 NOR State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### NOR State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the NOR controller + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief return the NOR controller state + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @retval NOR controller state + */ +HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor) +{ + return hnor->State; +} + +/** + * @brief Returns the NOR operation status. + * @param hnor pointer to a NOR_HandleTypeDef structure that contains + * the configuration information for NOR module. + * @param Address Device address + * @param Timeout NOR programming Timeout + * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR + * or HAL_NOR_STATUS_TIMEOUT + */ +HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) +{ + HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; + uint16_t tmpsr1; + uint16_t tmpsr2; + uint32_t tickstart; + + /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ + HAL_NOR_MspWait(hnor, Timeout); + + /* Get the NOR memory operation status -------------------------------------*/ + + /* Get tick */ + tickstart = HAL_GetTick(); + + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + status = HAL_NOR_STATUS_TIMEOUT; + } + } + + /* Read NOR status register (DQ6 and DQ5) */ + tmpsr1 = *(__IO uint16_t *)Address; + tmpsr2 = *(__IO uint16_t *)Address; + + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) + { + return HAL_NOR_STATUS_SUCCESS ; + } + + if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + { + status = HAL_NOR_STATUS_ONGOING; + } + + tmpsr1 = *(__IO uint16_t *)Address; + tmpsr2 = *(__IO uint16_t *)Address; + + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) + { + return HAL_NOR_STATUS_SUCCESS; + } + if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + { + return HAL_NOR_STATUS_ERROR; + } + } + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + do + { + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + tmpsr2 = *(__IO uint16_t *)(Address); + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_NOR_STATUS_TIMEOUT; + } + } + } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U); + + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + tmpsr1 = *(__IO uint16_t *)(Address); + if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U) + { + /* Clear the Status Register */ + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + status = HAL_NOR_STATUS_ERROR; + } + else + { + status = HAL_NOR_STATUS_SUCCESS; + } + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_NOR_STATUS_ERROR; + } + + /* Return the operation status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_NOR_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pcd.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pcd.c new file mode 100644 index 00000000000..2dcff89a0d6 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pcd.c @@ -0,0 +1,2362 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_pcd.c + * @author MCD Application Team + * @brief PCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The PCD HAL driver can be used as follows: + + (#) Declare a PCD_HandleTypeDef handle structure, for example: + PCD_HandleTypeDef hpcd; + + (#) Fill parameters of Init structure in HCD handle + + (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) + + (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: + (##) Enable the PCD/USB Low Level interface clock using + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) + + (##) Initialize the related GPIO clocks + (##) Configure PCD pin-out + (##) Configure PCD NVIC interrupt + + (#)Associate the Upper USB device stack to the HAL PCD Driver: + (##) hpcd.pData = pdev; + + (#)Enable PCD transmission and reception: + (##) HAL_PCD_Start(); + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup PCD PCD + * @brief PCD HAL module driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Macros + * @{ + */ +#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup PCD_Private_Functions PCD Private Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the PCD according to the specified + * parameters in the PCD_InitTypeDef and initialize the associated handle. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) +{ +#if defined (USB_OTG_FS) + const USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ + uint8_t i; + + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); + +#if defined (USB_OTG_FS) + USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + + if (hpcd->State == HAL_PCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpcd->Lock = HAL_UNLOCKED; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback = HAL_PCD_SOFCallback; + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + hpcd->ResetCallback = HAL_PCD_ResetCallback; + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; + hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; + hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; + + if (hpcd->MspInitCallback == NULL) + { + hpcd->MspInitCallback = HAL_PCD_MspInit; + } + + /* Init the low level hardware */ + hpcd->MspInitCallback(hpcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); +#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ + } + + hpcd->State = HAL_PCD_STATE_BUSY; + +#if defined (USB_OTG_FS) + /* Disable DMA mode for FS instance */ + if (USBx == USB_OTG_FS) + { + hpcd->Init.dma_enable = 0U; + } +#endif /* defined (USB_OTG_FS) */ + + /* Disable the Interrupts */ + __HAL_PCD_DISABLE(hpcd); + + /*Init the Core (common init.) */ + if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Force Device Mode */ + if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Init endpoints structures */ + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1U; + hpcd->IN_ep[i].num = i; + hpcd->IN_ep[i].tx_fifo_num = i; + /* Control until ep is activated */ + hpcd->IN_ep[i].type = EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; + } + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + hpcd->OUT_ep[i].is_in = 0U; + hpcd->OUT_ep[i].num = i; + /* Control until ep is activated */ + hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; + } + + /* Init Device */ + if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + hpcd->USB_Address = 0U; + hpcd->State = HAL_PCD_STATE_READY; + + /* Activate LPM */ + if (hpcd->Init.lpm_enable == 1U) + { + (void)HAL_PCDEx_ActivateLPM(hpcd); + } + + (void)USB_DevDisconnect(hpcd->Instance); + + return HAL_OK; +} + +/** + * @brief DeInitializes the PCD peripheral. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) +{ + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return HAL_ERROR; + } + + hpcd->State = HAL_PCD_STATE_BUSY; + + /* Stop Device */ + if (USB_StopDevice(hpcd->Instance) != HAL_OK) + { + return HAL_ERROR; + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + if (hpcd->MspDeInitCallback == NULL) + { + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hpcd->MspDeInitCallback(hpcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_PCD_MspDeInit(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + hpcd->State = HAL_PCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initializes the PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB PCD Callback + * To be used instead of the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = pCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = pCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = pCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = pCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = pCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = pCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = pCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Unregister an USB PCD Callback + * USB PCD callback is redirected to the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + /* Setup Legacy weak Callbacks */ + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = HAL_PCD_SOFCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = HAL_PCD_ResetCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Register USB PCD Data OUT Stage Callback + * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data OUT Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Data OUT Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Data IN Stage Callback + * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data IN Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Data IN Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso OUT incomplete Callback + * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Iso OUT incomplete Callback + * USB PCD Iso OUT incomplete Callback is redirected + * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso IN incomplete Callback + * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Iso IN incomplete Callback + * USB PCD Iso IN incomplete Callback is redirected + * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD BCD Callback + * To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD BCD Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->BCDCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD BCD Callback + * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD LPM Callback + * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD LPM Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->LPMCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD LPM Callback + * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + __HAL_LOCK(hpcd); + + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) + { + /* Enable USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } + + __HAL_PCD_ENABLE(hpcd); + (void)USB_DevConnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Stop the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + __HAL_LOCK(hpcd); + __HAL_PCD_DISABLE(hpcd); + (void)USB_DevDisconnect(hpcd->Instance); + + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) + { + /* Disable USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; + uint32_t i; + uint32_t ep_intr; + uint32_t epint; + uint32_t epnum; + uint32_t fifoemptymsk; + uint32_t RegVal; + + /* ensure that we are in device mode */ + if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) + { + /* avoid spurious interrupt */ + if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) + { + return; + } + + /* store current frame number */ + hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) + { + /* incorrect mode, acknowledge the interrupt */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); + } + + /* Handle RxQLevel Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) + { + USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + RegVal = USBx->GRXSTSP; + + ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; + + if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + { + if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) + { + (void)USB_ReadPacket(USBx, ep->xfer_buff, + (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); + + ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + } + } + else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + { + (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + } + else + { + /* ... */ + } + + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) + { + epnum = 0U; + + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) + { + epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); + (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); + } + + if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); + /* Class B setup phase done for previous decoded setup */ + (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); + } + + if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); + } + + /* Clear OUT Endpoint disable interrupt */ + if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) + { + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; + } + + ep = &hpcd->OUT_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); + } + + /* Clear Status Phase Received interrupt */ + if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + + /* Clear OUT NAK interrupt */ + if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) + { + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); + + epnum = 0U; + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) /* In ITR */ + { + epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); + + if (hpcd->Init.dma_enable == 1U) + { + hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; + + /* this is ZLP, so prepare EP0 for next setup */ + if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) + { + /* prepare to rx more setup packets */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); + } + if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); + } + if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); + } + if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) + { + (void)USB_FlushTxFifo(USBx, epnum); + + ep = &hpcd->IN_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); + } + if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) + { + (void)PCD_WriteEmptyTxFifo(hpcd, epnum); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + /* Handle Resume Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) + { + /* Clear the Remote Wake-up Signaling */ + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + + if (hpcd->LPM_State == LPM_L1) + { + hpcd->LPM_State = LPM_L0; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResumeCallback(hpcd); +#else + HAL_PCD_ResumeCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); + } + + /* Handle Suspend Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) + { + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); + } + + /* Handle LPM Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); + + if (hpcd->LPM_State == LPM_L0) + { + hpcd->LPM_State = LPM_L1; + hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + /* Handle Reset Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) + { + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + } + USBx_DEVICE->DAINTMSK |= 0x10001U; + + if (hpcd->Init.use_dedicated_ep1 != 0U) + { + USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM; + + USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; + } + else + { + USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM | + USB_OTG_DOEPMSK_OTEPSPRM | + USB_OTG_DOEPMSK_NAKM; + + USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; + } + + /* Set Default Address to 0 */ + USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; + + /* setup EP0 to receive SETUP packets */ + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, + (uint8_t *)hpcd->Setup); + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); + } + + /* Handle Enumeration done Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) + { + (void)USB_ActivateSetup(hpcd->Instance); + hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); + + /* Set USB Turnaround time */ + (void)USB_SetTurnaroundTime(hpcd->Instance, + HAL_RCC_GetHCLKFreq(), + (uint8_t)hpcd->Init.speed); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResetCallback(hpcd); +#else + HAL_PCD_ResetCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); + } + + /* Handle SOF Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback(hpcd); +#else + HAL_PCD_SOFCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); + } + + /* Handle Global OUT NAK effective Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) + { + USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; + + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) + { + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); + } + } + } + + /* Handle Incomplete ISO IN Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) + { + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_INEP(epnum)->DIEPCTL; + + if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) + { + hpcd->IN_ep[epnum].is_iso_incomplete = 1U; + + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); + } + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); + } + + /* Handle Incomplete ISO OUT Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + { + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_OUTEP(epnum)->DOEPCTL; + + if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && + ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) + { + hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; + + USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; + + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; + break; + } + } + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + } + + /* Handle Connection event Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ConnectCallback(hpcd); +#else + HAL_PCD_ConnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); + } + + /* Handle Disconnection event Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) + { + RegVal = hpcd->Instance->GOTGINT; + + if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DisconnectCallback(hpcd); +#else + HAL_PCD_DisconnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + hpcd->Instance->GOTGINT |= RegVal; + } + } +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +/** + * @brief Data OUT stage callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DataOutStageCallback could be implemented in the user file + */ +} + +/** + * @brief Data IN stage callback + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DataInStageCallback could be implemented in the user file + */ +} +/** + * @brief Setup stage callback + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SetupStageCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SOFCallback could be implemented in the user file + */ +} + +/** + * @brief USB Reset callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ResetCallback could be implemented in the user file + */ +} + +/** + * @brief Suspend event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SuspendCallback could be implemented in the user file + */ +} + +/** + * @brief Resume event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ResumeCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO OUT callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO IN callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Connection event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ConnectCallback could be implemented in the user file + */ +} + +/** + * @brief Disconnection event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DisconnectCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Connect the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + __HAL_LOCK(hpcd); + + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) + { + /* Enable USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } + (void)USB_DevConnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Disconnect the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + __HAL_LOCK(hpcd); + (void)USB_DevDisconnect(hpcd->Instance); + + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) + { + /* Disable USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Set the USB Device address. + * @param hpcd PCD handle + * @param address new device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) +{ + __HAL_LOCK(hpcd); + hpcd->USB_Address = address; + (void)USB_SetDevAddress(hpcd->Instance, address); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} +/** + * @brief Open and configure an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packet size + * @param ep_type endpoint type + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type) +{ + HAL_StatusTypeDef ret = HAL_OK; + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->num = ep_addr & EP_ADDR_MSK; + ep->maxpacket = ep_mps; + ep->type = ep_type; + + if (ep->is_in != 0U) + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = ep->num; + } + + /* Set initial data PID. */ + if (ep_type == EP_TYPE_BULK) + { + ep->data_pid_start = 0U; + } + + __HAL_LOCK(hpcd); + (void)USB_ActivateEndpoint(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + + return ret; +} + +/** + * @brief Deactivate an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + (void)USB_DeactivateEndpoint(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + + +/** + * @brief Receive an amount of data. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + if (hpcd->Init.dma_enable == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); + + return HAL_OK; +} + +/** + * @brief Get Received Data Size + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval Data Size + */ +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) +{ + return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; +} +/** + * @brief Send an amount of data + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + + if (hpcd->Init.dma_enable == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); + + return HAL_OK; +} + +/** + * @brief Set a STALL condition over an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + ep->is_in = 0U; + } + + ep->is_stall = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + + (void)USB_EPSetStall(hpcd->Instance, ep); + + if ((ep_addr & EP_ADDR_MSK) == 0U) + { + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Clear a STALL condition over in an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->is_stall = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + (void)USB_EPClearStall(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Abort an USB EP transaction. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + HAL_StatusTypeDef ret; + PCD_EPTypeDef *ep; + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + } + + /* Stop Xfer */ + ret = USB_EPStopXfer(hpcd->Instance, ep); + + return ret; +} + +/** + * @brief Flush an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + __HAL_LOCK(hpcd); + + if ((ep_addr & 0x80U) == 0x80U) + { + (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK); + } + else + { + (void)USB_FlushRxFifo(hpcd->Instance); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Activate remote wakeup signalling + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + return (USB_ActivateRemoteWakeup(hpcd->Instance)); +} + +/** + * @brief De-activate remote wakeup signalling. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + return (USB_DeActivateRemoteWakeup(hpcd->Instance)); +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PCD handle state. + * @param hpcd PCD handle + * @retval HAL state + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) +{ + return hpcd->State; +} + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Set the USB Device high speed test mode. + * @param hpcd PCD handle + * @param testmode USB Device high speed test mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode) +{ + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + + switch (testmode) + { + case TEST_J: + case TEST_K: + case TEST_SE0_NAK: + case TEST_PACKET: + case TEST_FORCE_EN: + USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; + break; + + default: + break; + } + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup PCD_Private_Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Check FIFO for the next packet to be loaded. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; + uint32_t len; + uint32_t len32b; + uint32_t fifoemptymsk; + + ep = &hpcd->IN_ep[epnum]; + + if (ep->xfer_count > ep->xfer_len) + { + return HAL_ERROR; + } + + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + + len32b = (len + 3U) / 4U; + + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && + (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) + { + /* Write the FIFO */ + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + len32b = (len + 3U) / 4U; + + (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, + (uint8_t)hpcd->Init.dma_enable); + + ep->xfer_buff += len; + ep->xfer_count += len; + } + + if (ep->xfer_len <= ep->xfer_count) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT transfer complete interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_EPTypeDef *ep; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + if (hpcd->Init.dma_enable == 1U) + { + if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + } + else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + else + { + ep = &hpcd->OUT_ep[epnum]; + + /* out data packet received over EP */ + ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); + + if (epnum == 0U) + { + if (ep->xfer_len == 0U) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + else + { + ep->xfer_buff += ep->xfer_count; + } + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else + { + /* ... */ + } + } + else + { + if (gSNPSiD == USB_OTG_CORE_ID_310A) + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + else + { + if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else + { + if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT setup packet received interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + + /* Inform the upper layer that a setup packet is available */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SetupStageCallback(hpcd); +#else + HAL_PCD_SetupStageCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) + { + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* HAL_PCD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pcd_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pcd_ex.c new file mode 100644 index 00000000000..0ad2a6a5e75 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pcd_ex.c @@ -0,0 +1,400 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_pcd_ex.c + * @author MCD Application Team + * @brief PCD Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Extended features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup PCDEx PCDEx + * @brief PCD Extended HAL module driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ + +/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @brief PCDEx control functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Update FIFO configuration + +@endverbatim + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Set Tx FIFO + * @param hpcd PCD handle + * @param fifo The number of Tx fifo + * @param size Fifo size + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) +{ + uint8_t i; + uint32_t Tx_Offset; + + /* TXn min size = 16 words. (n : Transmit FIFO index) + When a TxFIFO is not used, the Configuration should be as follows: + case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txm can use the space allocated for Txn. + case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txn should be configured with the minimum space of 16 words + The FIFO is used optimally when used TxFIFOs are allocated in the top + of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ + + Tx_Offset = hpcd->Instance->GRXFSIZ; + + if (fifo == 0U) + { + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; + } + else + { + Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; + for (i = 0U; i < (fifo - 1U); i++) + { + Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); + } + + /* Multiply Tx_Size by 2 to get higher performance */ + hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; + } + + return HAL_OK; +} + +/** + * @brief Set Rx FIFO + * @param hpcd PCD handle + * @param size Size of Rx fifo + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) +{ + hpcd->Instance->GRXFSIZ = size; + + return HAL_OK; +} + +/** + * @brief Activate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 1U; + hpcd->LPM_State = LPM_L0; + USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; + USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + + return HAL_OK; +} + +/** + * @brief Deactivate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 0U; + USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; + USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + + return HAL_OK; +} + + +/** + * @brief Handle BatteryCharging Process. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t gccfg_msk; + uint32_t tickstart = HAL_GetTick(); + + /* Enable DCD : Data Contact Detect */ + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; + } + else + { + USBx->GCCFG |= USB_OTG_GCCFG_DCDETEN; + } + + /* Wait for Min DCD Timeout */ + HAL_Delay(300U); + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + /* Check Detect flag */ + if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + /* Primary detection: checks if connected to Standard Downstream Port + (without charging capability) */ + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GCCFG &= ~USB_OTG_GCCFG_DCDEN; + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_PDEN; + } + else + { + USBx->GCCFG &= ~USB_OTG_GCCFG_DCDETEN; + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_PDETEN; + } + HAL_Delay(50U); + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + gccfg_msk = USB_OTG_GCCFG_PDET; + } + else + { + gccfg_msk = USB_OTG_GCCFG_CHGDET; + } + + if ((USBx->GCCFG & gccfg_msk) == 0U) + { + /* Case of Standard Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* start secondary detection to check connection to Charging Downstream + Port or Dedicated Charging Port */ + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_SDEN; + HAL_Delay(50U); + + gccfg_msk = USB_OTG_GCCFG_SDET; + } + else + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDETEN); + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_SDETEN; + HAL_Delay(50U); + + gccfg_msk = USB_OTG_GCCFG_FSVPLUS; + } + + if ((USBx->GCCFG & gccfg_msk) == gccfg_msk) + { + /* case Dedicated Charging Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* case Charging Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + /* Battery Charging capability discovery finished */ + (void)HAL_PCDEx_DeActivateBCD(hpcd); + + /* Check for the Timeout, else start USB Device */ + if ((HAL_GetTick() - tickstart) > 1000U) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Activate BatteryCharging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + + /* Power Down USB transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + + /* Enable Battery charging */ + USBx->GCCFG |= USB_OTG_GCCFG_BCDEN; + } + else + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDETEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDETEN); + } + + hpcd->battery_charging_active = 1U; + + return HAL_OK; +} + +/** + * @brief Deactivate BatteryCharging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + + /* Disable Battery charging */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); + } + else + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDETEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDETEN); + } + + hpcd->battery_charging_active = 0U; + + return HAL_OK; +} + +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @brief Send LPM message to user layer callback. + * @param hpcd PCD handle + * @param msg LPM message + * @retval HAL status + */ +__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(msg); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_LPM_Callback could be implemented in the user file + */ +} + +/** + * @brief Send BatteryCharging message to user layer callback. + * @param hpcd PCD handle + * @param msg LPM message + * @retval HAL status + */ +__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(msg); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_BCD_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* HAL_PCD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pka.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pka.c new file mode 100644 index 00000000000..6c755a987e3 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pka.c @@ -0,0 +1,3042 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_pka.c + * @author MCD Application Team + * @brief PKA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of public key accelerator(PKA): + * + Initialization and de-initialization functions + * + Start an operation + * + Retrieve the operation result + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The PKA HAL driver can be used as follows: + + (#) Declare a PKA_HandleTypeDef handle structure, for example: PKA_HandleTypeDef hpka; + + (#) Initialize the PKA low level resources by implementing the HAL_PKA_MspInit() API: + (##) Enable the PKA interface clock + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the PKA interrupt priority + (+++) Enable the NVIC PKA IRQ Channel + + (#) Initialize the PKA registers by calling the HAL_PKA_Init() API which trig + HAL_PKA_MspInit(). + + (#) Fill entirely the input structure corresponding to your operation: + For instance: PKA_ModExpInTypeDef for HAL_PKA_ModExp(). + + (#) Execute the operation (in polling or interrupt) and check the returned value. + + (#) Retrieve the result of the operation (For instance, HAL_PKA_ModExp_GetResult for + HAL_PKA_ModExp operation). The function to gather the result is different for each + kind of operation. The correspondence can be found in the following section. + + (#) Call the function HAL_PKA_DeInit() to restore the default configuration which trig + HAL_PKA_MspDeInit(). + + *** High level operation *** + ================================= + [..] + (+) Input structure requires buffers as uint8_t array. + + (+) Output structure requires buffers as uint8_t array. + + (+) Modular exponentiation using: + (++) HAL_PKA_ModExp(). + (++) HAL_PKA_ModExp_IT(). + (++) HAL_PKA_ModExpFastMode(). + (++) HAL_PKA_ModExpFastMode_IT(). + (++) HAL_PKA_ModExpProtectMode(). + (++) HAL_PKA_ModExpProtectMode_IT(). + (++) HAL_PKA_ModExp_GetResult() to retrieve the result of the operation. + + (+) RSA Chinese Remainder Theorem (CRT) using: + (++) HAL_PKA_RSACRTExp(). + (++) HAL_PKA_RSACRTExp_IT(). + (++) HAL_PKA_RSACRTExp_GetResult() to retrieve the result of the operation. + + (+) ECC Point Check using: + (++) HAL_PKA_PointCheck(). + (++) HAL_PKA_PointCheck_IT(). + (++) HAL_PKA_PointCheck_IsOnCurve() to retrieve the result of the operation. + + (+) ECDSA Sign + (++) HAL_PKA_ECDSASign(). + (++) HAL_PKA_ECDSASign_IT(). + (++) HAL_PKA_ECDSASign_GetResult() to retrieve the result of the operation. + + (+) ECDSA Verify + (++) HAL_PKA_ECDSAVerif(). + (++) HAL_PKA_ECDSAVerif_IT(). + (++) HAL_PKA_ECDSAVerif_IsValidSignature() to retrieve the result of the operation. + + (+) ECC Scalar Multiplication using: + (++) HAL_PKA_ECCMul(). + (++) HAL_PKA_ECCMul_IT(). + (++) HAL_PKA_ECCMul_GetResult() to retrieve the result of the operation. + + (+) ECC double base ladder using: + (++) HAL_PKA_ECCDoubleBaseLadder(). + (++) HAL_PKA_ECCDoubleBaseLadder_IT(). + (++) HAL_PKA_ECCDoubleBaseLadder_GetResult() to retrieve the result of the operation. + + (+) ECC projective to affine using: + (++) HAL_PKA_ECCProjective2Affine(). + (++) HAL_PKA_ECCProjective2Affine_IT(). + (++) HAL_PKA_ECCProjective2Affine_GetResult() to retrieve the result of the operation. + + (+) ECC complete addition using: + (++) HAL_PKA_ECCCompleteAddition(). + (++) HAL_PKA_ECCCompleteAddition_IT(). + (++) HAL_PKA_ECCCompleteAddition_GetResult() to retrieve the result of the operation. + + *** Low level operation *** + ================================= + [..] + (+) Input structure requires buffers as uint32_t array. + + (+) Output structure requires buffers as uint32_t array. + + (+) Arithmetic addition using: + (++) HAL_PKA_Add(). + (++) HAL_PKA_Add_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + The resulting size can be the input parameter or the input parameter size + 1 (overflow). + + (+) Arithmetic subtraction using: + (++) HAL_PKA_Sub(). + (++) HAL_PKA_Sub_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + (+) Arithmetic multiplication using: + (++) HAL_PKA_Mul(). + (++) HAL_PKA_Mul_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + (+) Comparison using: + (++) HAL_PKA_Cmp(). + (++) HAL_PKA_Cmp_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + (+) Modular addition using: + (++) HAL_PKA_ModAdd(). + (++) HAL_PKA_ModAdd_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + (+) Modular subtraction using: + (++) HAL_PKA_ModSub(). + (++) HAL_PKA_ModSub_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + (+) Modular inversion using: + (++) HAL_PKA_ModInv(). + (++) HAL_PKA_ModInv_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + (+) Modular reduction using: + (++) HAL_PKA_ModRed(). + (++) HAL_PKA_ModRed_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + (+) Montgomery multiplication using: + (++) HAL_PKA_MontgomeryMul(). + (++) HAL_PKA_MontgomeryMul_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + *** Montgomery parameter *** + ================================= + (+) For some operation, the computation of the Montgomery parameter is a prerequisite. + (+) Input structure requires buffers as uint8_t array. + (+) Output structure requires buffers as uint32_t array.(Only used inside PKA). + (+) You can compute the Montgomery parameter using: + (++) HAL_PKA_MontgomeryParam(). + (++) HAL_PKA_MontgomeryParam_IT(). + (++) HAL_PKA_MontgomeryParam_GetResult() to retrieve the result of the operation. + + *** Polling mode operation *** + =================================== + [..] + (+) When an operation is started in polling mode, the function returns when: + (++) A timeout is encounter. + (++) The operation is completed. + + *** Interrupt mode operation *** + =================================== + [..] + (+) Add HAL_PKA_IRQHandler to the IRQHandler of PKA. + (+) Enable the IRQ using HAL_NVIC_EnableIRQ(). + (+) When an operation is started in interrupt mode, the function returns immediately. + (+) When the operation is completed, the callback HAL_PKA_OperationCpltCallback is called. + (+) When an error is encountered, the callback HAL_PKA_ErrorCallback is called. + (+) To stop any operation in interrupt mode, use HAL_PKA_Abort(). + + *** Utilities *** + =================================== + [..] + (+) To clear the PKA RAM, use HAL_PKA_RAMReset(). + (+) To get current state, use HAL_PKA_GetState(). + (+) To get current error, use HAL_PKA_GetError(). + + *** Callback registration *** + ============================================= + [..] + + The compilation flag USE_HAL_PKA_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_PKA_RegisterCallback() + to register an interrupt callback. + [..] + + Function HAL_PKA_RegisterCallback() allows to register following callbacks: + (+) OperationCpltCallback : callback for End of operation. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function HAL_PKA_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) OperationCpltCallback : callback for End of operation. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + + By default, after the HAL_PKA_Init() and when the state is HAL_PKA_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_PKA_OperationCpltCallback(), HAL_PKA_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_PKA_Init()/ HAL_PKA_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the HAL_PKA_Init()/ HAL_PKA_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in HAL_PKA_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_PKA_STATE_READY or HAL_PKA_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_PKA_RegisterCallback() before calling HAL_PKA_DeInit() + or HAL_PKA_Init() function. + [..] + + When the compilation flag USE_HAL_PKA_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) + +/** @defgroup PKA PKA + * @brief PKA HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PKA_Private_Define PKA Private Define + * @{ + */ +#define PKA_RAM_SIZE 1334U + +/* Private macro -------------------------------------------------------------*/ +#define __PKA_RAM_PARAM_END(TAB,INDEX) do{ \ + TAB[INDEX] = 0UL; \ + TAB[INDEX + 1U] = 0UL; \ + } while(0) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +static uint32_t primeordersize; +static uint32_t opsize; +static uint32_t modulussize; +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup PKA_Private_Functions PKA Private Functions + * @{ + */ +uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka); +HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart); +uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode); +uint32_t PKA_GetBitSize_u8(uint32_t byteNumber); +uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb); +uint32_t PKA_GetBitSize_u32(uint32_t wordNumber); +uint32_t PKA_GetArraySize_u8(uint32_t bitSize); +void PKA_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], size_t n); +void PKA_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], size_t n); +void PKA_Memcpy_u32_to_u32(__IO uint32_t dst[], __IO const uint32_t src[], size_t n); +HAL_StatusTypeDef PKA_Process(PKA_HandleTypeDef *hpka, uint32_t mode, uint32_t Timeout); +HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode); +void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in); +void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in); +void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in); +void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in); +void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in); +void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in); +void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in); +void PKA_PointCheck_Set(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in); +void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in); +void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in); +void PKA_ModInv_Set(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in); +void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1); +void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2, + const uint8_t *pOp3); +void PKA_ECCDoubleBaseLadder_Set(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in); +void PKA_ECCProjective2Affine_Set(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in); +void PKA_ECCCompleteAddition_Set(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in); +HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +uint32_t PKA_Result_GetSize(const PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PKA_Exported_Functions PKA Exported Functions + * @{ + */ + +/** @defgroup PKA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the PKAx peripheral: + + (+) User must implement HAL_PKA_MspInit() function in which he configures + all related peripherals resources (CLOCK, IT and NVIC ). + + (+) Call the function HAL_PKA_Init() to configure the device. + + (+) Call the function HAL_PKA_DeInit() to restore the default configuration + of the selected PKAx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the PKA according to the specified + * parameters in the PKA_InitTypeDef and initialize the associated handle. + * @param hpka PKA handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka) +{ + HAL_StatusTypeDef err = HAL_OK; + uint32_t tickstart; + + /* Check the PKA handle allocation */ + if (hpka != NULL) + { + /* Check the parameters */ + assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); + + if (hpka->State == HAL_PKA_STATE_RESET) + { + +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) + /* Init the PKA Callback settings */ + hpka->OperationCpltCallback = HAL_PKA_OperationCpltCallback; /* Legacy weak OperationCpltCallback */ + hpka->ErrorCallback = HAL_PKA_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hpka->MspInitCallback == NULL) + { + hpka->MspInitCallback = HAL_PKA_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hpka->MspInitCallback(hpka); +#else + /* Init the low level hardware */ + HAL_PKA_MspInit(hpka); +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + } + + /* Set the state to busy */ + hpka->State = HAL_PKA_STATE_BUSY; + + /* Reset the control register and enable the PKA */ + hpka->Instance->CR = PKA_CR_EN; + + /* Get current tick */ + tickstart = HAL_GetTick(); + + /* Wait the INITOK flag Setting */ + if (PKA_WaitOnFlagUntilTimeout(hpka, PKA_SR_INITOK, RESET, tickstart, 5000) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Reset any pending flag */ + SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + + /* Initialize the error code */ + hpka->ErrorCode = HAL_PKA_ERROR_NONE; + + /* Set the state to ready */ + hpka->State = HAL_PKA_STATE_READY; + } + else + { + err = HAL_ERROR; + } + + return err; +} + +/** + * @brief DeInitialize the PKA peripheral. + * @param hpka PKA handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_DeInit(PKA_HandleTypeDef *hpka) +{ + HAL_StatusTypeDef err = HAL_OK; + + /* Check the PKA handle allocation */ + if (hpka != NULL) + { + /* Check the parameters */ + assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); + + /* Set the state to busy */ + hpka->State = HAL_PKA_STATE_BUSY; + + /* Reset the control register */ + /* This abort any operation in progress (PKA RAM content is not guaranteed in this case) */ + hpka->Instance->CR = 0; + + /* Reset any pending flag */ + SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) + if (hpka->MspDeInitCallback == NULL) + { + hpka->MspDeInitCallback = HAL_PKA_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hpka->MspDeInitCallback(hpka); +#else + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_PKA_MspDeInit(hpka); +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + + /* Reset the error code */ + hpka->ErrorCode = HAL_PKA_ERROR_NONE; + + /* Reset the state */ + hpka->State = HAL_PKA_STATE_RESET; + } + else + { + err = HAL_ERROR; + } + + return err; +} + +/** + * @brief Initialize the PKA MSP. + * @param hpka PKA handle + * @retval None + */ +__weak void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpka); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PKA_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the PKA MSP. + * @param hpka PKA handle + * @retval None + */ +__weak void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpka); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PKA_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User PKA Callback + * To be used instead of the weak predefined callback + * @param hpka Pointer to a PKA_HandleTypeDef structure that contains + * the configuration information for the specified PKA. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_PKA_OPERATION_COMPLETE_CB_ID End of operation callback ID + * @arg @ref HAL_PKA_ERROR_CB_ID Error callback ID + * @arg @ref HAL_PKA_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_PKA_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, + pPKA_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_PKA_STATE_READY == hpka->State) + { + switch (CallbackID) + { + case HAL_PKA_OPERATION_COMPLETE_CB_ID : + hpka->OperationCpltCallback = pCallback; + break; + + case HAL_PKA_ERROR_CB_ID : + hpka->ErrorCallback = pCallback; + break; + + case HAL_PKA_MSPINIT_CB_ID : + hpka->MspInitCallback = pCallback; + break; + + case HAL_PKA_MSPDEINIT_CB_ID : + hpka->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_PKA_STATE_RESET == hpka->State) + { + switch (CallbackID) + { + case HAL_PKA_MSPINIT_CB_ID : + hpka->MspInitCallback = pCallback; + break; + + case HAL_PKA_MSPDEINIT_CB_ID : + hpka->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a PKA Callback + * PKA callback is redirected to the weak predefined callback + * @param hpka Pointer to a PKA_HandleTypeDef structure that contains + * the configuration information for the specified PKA. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_PKA_OPERATION_COMPLETE_CB_ID End of operation callback ID + * @arg @ref HAL_PKA_ERROR_CB_ID Error callback ID + * @arg @ref HAL_PKA_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_PKA_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_PKA_STATE_READY == hpka->State) + { + switch (CallbackID) + { + case HAL_PKA_OPERATION_COMPLETE_CB_ID : + hpka->OperationCpltCallback = HAL_PKA_OperationCpltCallback; /* Legacy weak OperationCpltCallback */ + break; + + case HAL_PKA_ERROR_CB_ID : + hpka->ErrorCallback = HAL_PKA_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_PKA_MSPINIT_CB_ID : + hpka->MspInitCallback = HAL_PKA_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_PKA_MSPDEINIT_CB_ID : + hpka->MspDeInitCallback = HAL_PKA_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_PKA_STATE_RESET == hpka->State) + { + switch (CallbackID) + { + case HAL_PKA_MSPINIT_CB_ID : + hpka->MspInitCallback = HAL_PKA_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_PKA_MSPDEINIT_CB_ID : + hpka->MspDeInitCallback = HAL_PKA_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup PKA_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PKA operations. + + (#) There are two modes of operation: + + (++) Blocking mode : The operation is performed in the polling mode. + These functions return when data operation is completed. + (++) No-Blocking mode : The operation is performed using Interrupts. + These functions return immediately. + The end of the operation is indicated by HAL_PKA_ErrorCallback in case of error. + The end of the operation is indicated by HAL_PKA_OperationCpltCallback in case of success. + To stop any operation in interrupt mode, use HAL_PKA_Abort(). + + (#) Blocking mode functions are : + + (++) HAL_PKA_ModExp() + (++) HAL_PKA_ModExpFastMode() + (++) HAL_PKA_ModExpProtectMode() + (++) HAL_PKA_ModExp_GetResult(); + + (++) HAL_PKA_ECDSASign() + (++) HAL_PKA_ECDSASign_GetResult(); + + (++) HAL_PKA_ECDSAVerif() + (++) HAL_PKA_ECDSAVerif_IsValidSignature(); + + (++) HAL_PKA_RSACRTExp() + (++) HAL_PKA_RSACRTExp_GetResult(); + + (++) HAL_PKA_PointCheck() + (++) HAL_PKA_PointCheck_IsOnCurve(); + + (++) HAL_PKA_ECCMul() + (++) HAL_PKA_ECCMulFastMode() + (++) HAL_PKA_ECCMul_GetResult(); + + (++) HAL_PKA_ECCMulEx() + (++) HAL_PKA_ECCDoubleBaseLadder() + (++) HAL_PKA_ECCDoubleBaseLadder_GetResult(); + (++) HAL_PKA_ECCProjective2Affine() + (++) HAL_PKA_ECCProjective2Affine_GetResult(); + (++) HAL_PKA_ECCCompleteAddition() + (++) HAL_PKA_ECCCompleteAddition_GetResult(); + + (++) HAL_PKA_Add() + (++) HAL_PKA_Sub() + (++) HAL_PKA_Cmp() + (++) HAL_PKA_Mul() + (++) HAL_PKA_ModAdd() + (++) HAL_PKA_ModSub() + (++) HAL_PKA_ModInv() + (++) HAL_PKA_ModRed() + (++) HAL_PKA_MontgomeryMul() + (++) HAL_PKA_Arithmetic_GetResult(P); + + (++) HAL_PKA_MontgomeryParam() + (++) HAL_PKA_MontgomeryParam_GetResult(); + + (#) No-Blocking mode functions with Interrupt are : + + (++) HAL_PKA_ModExp_IT(); + (++) HAL_PKA_ModExpFastMode_IT(); + (++) HAL_PKA_ModExpProtectMode_IT() + (++) HAL_PKA_ModExp_GetResult(); + + (++) HAL_PKA_ECDSASign_IT(); + (++) HAL_PKA_ECDSASign_GetResult(); + + (++) HAL_PKA_ECDSAVerif_IT(); + (++) HAL_PKA_ECDSAVerif_IsValidSignature(); + + (++) HAL_PKA_RSACRTExp_IT(); + (++) HAL_PKA_RSACRTExp_GetResult(); + + (++) HAL_PKA_PointCheck_IT(); + (++) HAL_PKA_PointCheck_IsOnCurve(); + + (++) HAL_PKA_ECCMul_IT(); + (++) HAL_PKA_ECCMulFastMode_IT(); + (++) HAL_PKA_ECCMul_GetResult(); + + (++) HAL_PKA_ECCMulEx_IT(); + (++) HAL_PKA_ECCDoubleBaseLadder_IT() + (++) HAL_PKA_ECCDoubleBaseLadder_GetResult(); + (++) HAL_PKA_ECCProjective2Affine_IT() + (++) HAL_PKA_ECCProjective2Affine_GetResult(); + (++) HAL_PKA_ECCCompleteAddition_IT() + (++) HAL_PKA_ECCCompleteAddition_GetResult(); + (++) HAL_PKA_Add_IT(); + (++) HAL_PKA_Sub_IT(); + (++) HAL_PKA_Cmp_IT(); + (++) HAL_PKA_Mul_IT(); + (++) HAL_PKA_ModAdd_IT(); + (++) HAL_PKA_ModSub_IT(); + (++) HAL_PKA_ModInv_IT(); + (++) HAL_PKA_ModRed_IT(); + (++) HAL_PKA_MontgomeryMul_IT(); + (++) HAL_PKA_Arithmetic_GetResult(); + + (++) HAL_PKA_MontgomeryParam_IT(); + (++) HAL_PKA_MontgomeryParam_GetResult(); + + (++) HAL_PKA_Abort(); + +@endverbatim + * @{ + */ + +/** + * @brief Modular exponentiation in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ModExp_Set(hpka, in); + + opsize = in->OpSize; + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout); +} + +/** + * @brief Modular exponentiation in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ModExp_Set(hpka, in); + + opsize = in->OpSize; + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP); +} + +/** + * @brief Modular exponentiation in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ModExpFastMode_Set(hpka, in); + + opsize = in->OpSize; + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout); +} + +/** + * @brief Modular exponentiation in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ModExpFastMode_Set(hpka, in); + + opsize = in->OpSize; + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE); +} + +/** + * @brief Modular exponentiation (protected) in blocking mode. + * Useful when a secret information is involved (RSA decryption) + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in, + uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ModExpProtectMode_Set(hpka, in); + + opsize = in->OpSize; + + return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_PROTECT, Timeout); +} + +/** + * @brief Modular exponentiation (protected) in non-blocking mode with Interrupt. + * Useful when a secret information is involved (RSA decryption) + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ModExpProtectMode_Set(hpka, in); + + opsize = in->OpSize; + + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT); +} + + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param pRes Output buffer + * @retval HAL status + */ +void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) +{ + uint32_t size; + + /* Get output result size */ + size = opsize; + + /* Move the result to appropriate location (indicated in out parameter) */ + PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size); +} + +/** + * @brief Sign a message using elliptic curves over prime fields in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECDSASign_Set(hpka, in); + + primeordersize = in->primeOrderSize; + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout); +} + +/** + * @brief Sign a message using elliptic curves over prime fields in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECDSASign_Set(hpka, in); + + primeordersize = in->primeOrderSize; + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE); +} + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param out Output information + * @param outExt Additional Output information (facultative) + */ +void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, + PKA_ECDSASignOutExtParamTypeDef *outExt) +{ + uint32_t size; + + /* Get output result size */ + size = primeordersize; + + + if (out != NULL) + { + PKA_Memcpy_u32_to_u8(out->RSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], size); + PKA_Memcpy_u32_to_u8(out->SSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], size); + } + + /* If user requires the additional information */ + if (outExt != NULL) + { + /* Move the result to appropriate location (indicated in outExt parameter) */ + PKA_Memcpy_u32_to_u8(outExt->ptX, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_X], size); + PKA_Memcpy_u32_to_u8(outExt->ptY, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y], size); + } +} + +/** + * @brief Verify the validity of a signature using elliptic curves over prime fields in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECDSAVerif_Set(hpka, in); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ECDSA_VERIFICATION, Timeout); +} + +/** + * @brief Verify the validity of a signature using elliptic curves + * over prime fields in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECDSAVerif_Set(hpka, in); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ECDSA_VERIFICATION); +} + +/** + * @brief Return the result of the ECDSA verification operation. + * @param hpka PKA handle + * @retval 1 if signature is verified, 0 in other case + */ +uint32_t HAL_PKA_ECDSAVerif_IsValidSignature(PKA_HandleTypeDef const *const hpka) +{ + return (hpka->Instance->RAM[PKA_ECDSA_VERIF_OUT_RESULT] == 0xD60DU) ? 1UL : 0UL; +} + +/** + * @brief RSA CRT exponentiation in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_RSACRTExp(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_RSACRTExp_Set(hpka, in); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_RSA_CRT_EXP, Timeout); +} + +/** + * @brief RSA CRT exponentiation in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_RSACRTExp_Set(hpka, in); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_RSA_CRT_EXP); +} + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param pRes Pointer to memory location to receive the result of the operation + * @retval HAL status + */ +void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) +{ + uint32_t size; + + /* Move the result to appropriate location (indicated in out parameter) */ + size = (hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_MOD_NB_BITS] + 7UL) / 8UL; + + PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_RSA_CRT_EXP_OUT_RESULT], size); +} + +/** + * @brief Point on elliptic curve check in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); +} + +/** + * @brief Point on elliptic curve check in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); +} + +/** + * @brief Return the result of the point check operation. + * @param hpka PKA handle + * @retval 1 if point is on curve, 0 in other case + */ +uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka) +{ +#define PKA_POINT_IS_ON_CURVE 0xD60DUL + /* Invert the value of the PKA RAM containing the result of the operation */ + return (hpka->Instance->RAM[PKA_POINT_CHECK_OUT_ERROR] == PKA_POINT_IS_ON_CURVE) ? 1UL : 0UL; +} + +/** + * @brief ECC scalar multiplication in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMul_Set(hpka, in); + + modulussize = in->modulusSize; + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); +} + +/** + * @brief ECC scalar multiplication in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMul_Set(hpka, in); + + modulussize = in->modulusSize; + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); +} +/** + * @brief ECC scalar multiplication extended in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMulEx_Set(hpka, in); + + modulussize = in->modulusSize; + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); +} + +/** + * @brief ECC scalar multiplication extended in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMulEx_Set(hpka, in); + + modulussize = in->modulusSize; + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); +} +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param out Output information + * @retval HAL status + */ +void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out) +{ + uint32_t size; + + /* Get output result size */ + size = modulussize; + + /* If a destination buffer is provided */ + if (out != NULL) + { + /* Move the result to appropriate location (indicated in out parameter) */ + PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X], size); + PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y], size); + } +} + +/** + * @brief Arithmetic addition in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ARITHMETIC_ADD, Timeout); +} + +/** + * @brief Arithmetic addition in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Add_IT(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_ADD); +} + +/** + * @brief Arithmetic subtraction in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Sub(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ARITHMETIC_SUB, Timeout); +} + +/** + * @brief Arithmetic subtraction in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Sub_IT(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_SUB); +} + +/** + * @brief Arithmetic multiplication in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Mul(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ARITHMETIC_MUL, Timeout); +} + +/** + * @brief Arithmetic multiplication in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Mul_IT(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_MUL); +} + +/** + * @brief Comparison in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Cmp(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_COMPARISON, Timeout); +} + +/** + * @brief Comparison in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Cmp_IT(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_COMPARISON); +} + +/** + * @brief Modular addition in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModAdd(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MODULAR_ADD, Timeout); +} + +/** + * @brief Modular addition in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModAdd_IT(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_ADD); +} + +/** + * @brief Modular inversion in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModInv(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ModInv_Set(hpka, in); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MODULAR_INV, Timeout); +} + +/** + * @brief Modular inversion in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModInv_IT(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ModInv_Set(hpka, in); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_INV); +} + +/** + * @brief Modular subtraction in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModSub(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MODULAR_SUB, Timeout); +} + +/** + * @brief Modular subtraction in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModSub_IT(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_SUB); +} + +/** + * @brief Modular reduction in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModRed(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ModRed_Set(hpka, in); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MODULAR_RED, Timeout); +} + +/** + * @brief Modular reduction in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModRed_IT(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ModRed_Set(hpka, in); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_RED); +} + +/** + * @brief Montgomery multiplication in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_MontgomeryMul(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MONTGOMERY_MUL, Timeout); +} + +/** + * @brief Montgomery multiplication in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MONTGOMERY_MUL); +} + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param pRes Pointer to memory location to receive the result of the operation + */ +void HAL_PKA_Arithmetic_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes) +{ + uint32_t mode = (hpka->Instance->CR & PKA_CR_MODE_Msk) >> PKA_CR_MODE_Pos; + uint32_t size = 0; + + /* Move the result to appropriate location (indicated in pRes parameter) */ + switch (mode) + { + case PKA_MODE_MONTGOMERY_PARAM: + case PKA_MODE_ARITHMETIC_SUB: + case PKA_MODE_MODULAR_ADD: + case PKA_MODE_MODULAR_RED: + case PKA_MODE_MODULAR_INV: + case PKA_MODE_MONTGOMERY_MUL: + size = hpka->Instance->RAM[2] / 32UL; + break; + case PKA_MODE_ARITHMETIC_ADD: + case PKA_MODE_MODULAR_SUB: + size = hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_NB_BITS] / 32UL; + + /* Manage the overflow of the addition */ + if (hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT + size] != 0UL) + { + size += 1UL; + } + + break; + case PKA_MODE_COMPARISON: + size = 1; + break; + case PKA_MODE_ARITHMETIC_MUL: + size = hpka->Instance->RAM[PKA_ARITHMETIC_MUL_NB_BITS] / 32UL * 2UL; + break; + default: + break; + } + + if (pRes != NULL) + { + switch (mode) + { + case PKA_MODE_ARITHMETIC_SUB: + case PKA_MODE_MODULAR_ADD: + case PKA_MODE_MODULAR_RED: + case PKA_MODE_MODULAR_INV: + case PKA_MODE_MODULAR_SUB: + case PKA_MODE_MONTGOMERY_MUL: + case PKA_MODE_ARITHMETIC_ADD: + case PKA_MODE_COMPARISON: + case PKA_MODE_ARITHMETIC_MUL: + PKA_Memcpy_u32_to_u32(pRes, &hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT], size); + break; + default: + break; + } + } +} + +/** + * @brief Montgomery parameter computation in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_MontgomeryParam_Set(hpka, in->size, in->pOp1); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MONTGOMERY_PARAM, Timeout); +} + +/** + * @brief Montgomery parameter computation in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_MontgomeryParam_Set(hpka, in->size, in->pOp1); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MONTGOMERY_PARAM); +} + +/** + * @brief ECC double base ladder in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in, + uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCDoubleBaseLadder_Set(hpka, in); + + return PKA_Process(hpka, PKA_MODE_DOUBLE_BASE_LADDER, Timeout); +} + +/** + * @brief ECC double base ladder in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder_IT(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCDoubleBaseLadder_Set(hpka, in); + + return PKA_Process_IT(hpka, PKA_MODE_DOUBLE_BASE_LADDER); +} + +/** + * @brief ECC projective to affine in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in, + uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCProjective2Affine_Set(hpka, in); + + return PKA_Process(hpka, PKA_MODE_ECC_PROJECTIVE_AFF, Timeout); +} + +/** + * @brief ECC projective to affine in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine_IT(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCProjective2Affine_Set(hpka, in); + + return PKA_Process_IT(hpka, PKA_MODE_ECC_PROJECTIVE_AFF); +} + +/** + * @brief ECC complete addition in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in, + uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCCompleteAddition_Set(hpka, in); + + return PKA_Process(hpka, PKA_MODE_ECC_COMPLETE_ADD, Timeout); +} + +/** + * @brief ECC complete addition in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition_IT(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCCompleteAddition_Set(hpka, in); + + return PKA_Process_IT(hpka, PKA_MODE_ECC_COMPLETE_ADD); +} + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param pRes pointer to buffer where the result will be copied + * @retval HAL status + */ +void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes) +{ + uint32_t size; + + /* Retrieve the size of the buffer from the PKA RAM */ + size = (hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] + 31UL) / 32UL; + + /* Move the result to appropriate location (indicated in out parameter) */ + PKA_Memcpy_u32_to_u32(pRes, &hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_OUT_PARAMETER], size); +} + +/** + * @brief Abort any ongoing operation. + * @param hpka PKA handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka) +{ + HAL_StatusTypeDef err = HAL_OK; + + /* Clear EN bit */ + /* This abort any operation in progress (PKA RAM content is not guaranteed in this case) */ + CLEAR_BIT(hpka->Instance->CR, PKA_CR_EN); + SET_BIT(hpka->Instance->CR, PKA_CR_EN); + + /* Reset any pending flag */ + SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + + /* Reset the error code */ + hpka->ErrorCode = HAL_PKA_ERROR_NONE; + + /* Reset the state */ + hpka->State = HAL_PKA_STATE_READY; + + return err; +} + +/** + * @brief Reset the PKA RAM. + * @param hpka PKA handle + * @retval None + */ +void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka) +{ + uint32_t index; + + /* For each element in the PKA RAM */ + for (index = 0; index < PKA_RAM_SIZE; index++) + { + /* Clear the content */ + hpka->Instance->RAM[index] = 0UL; + } +} + +/** + * @brief This function handles PKA event interrupt request. + * @param hpka PKA handle + * @retval None + */ +void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) +{ + uint32_t mode = PKA_GetMode(hpka); + uint32_t itsource = READ_REG(hpka->Instance->CR); + uint32_t flag = READ_REG(hpka->Instance->SR); + + /* Address error interrupt occurred */ + if (((itsource & PKA_IT_ADDRERR) == PKA_IT_ADDRERR) && ((flag & PKA_FLAG_ADDRERR) == PKA_FLAG_ADDRERR)) + { + hpka->ErrorCode |= HAL_PKA_ERROR_ADDRERR; + + /* Clear ADDRERR flag */ + __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_ADDRERR); + } + + /* RAM access error interrupt occurred */ + if (((itsource & PKA_IT_RAMERR) == PKA_IT_RAMERR) && ((flag & PKA_FLAG_RAMERR) == PKA_FLAG_RAMERR)) + { + hpka->ErrorCode |= HAL_PKA_ERROR_RAMERR; + + /* Clear RAMERR flag */ + __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_RAMERR); + } + + /* OPERATION access error interrupt occurred */ + if (((itsource & PKA_IT_OPERR) == PKA_IT_OPERR) && ((flag & PKA_FLAG_OPERR) == PKA_FLAG_OPERR)) + { + hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; + + /* Clear OPERR flag */ + __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_OPERR); + } + + /* Check the operation success in case of ECDSA signature */ + switch (mode) + { + case PKA_MODE_ECDSA_SIGNATURE : + /* If error output result is different from no error, operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_ERROR] != PKA_NO_ERROR) + { + hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; + } + break; + + case PKA_MODE_DOUBLE_BASE_LADDER : + /* If error output result is different from no error, operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_ERROR] != PKA_NO_ERROR) + { + hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; + } + break; + + case PKA_MODE_ECC_PROJECTIVE_AFF : + /* If error output result is different from no error, operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_ERROR] != PKA_NO_ERROR) + { + hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; + } + break; + + case PKA_MODE_ECC_MUL : + /* If error output result is different from no error, operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_ERROR] != PKA_NO_ERROR) + { + hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; + } + break; + + case PKA_MODE_MODULAR_EXP_PROTECT : + /* If error output result is different from no error, operation need to be repeated */ + if (hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_ERROR] != PKA_NO_ERROR) + { + hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; + } + break; + default : + break; + } + /* Trigger the error callback if an error is present */ + if (hpka->ErrorCode != HAL_PKA_ERROR_NONE) + { +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) + hpka->ErrorCallback(hpka); +#else + HAL_PKA_ErrorCallback(hpka); +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + } + + /* End Of Operation interrupt occurred */ + if (((itsource & PKA_IT_PROCEND) == PKA_IT_PROCEND) && ((flag & PKA_FLAG_PROCEND) == PKA_FLAG_PROCEND)) + { + /* Clear PROCEND flag */ + __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_PROCEND); + + /* Set the state to ready */ + hpka->State = HAL_PKA_STATE_READY; + +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) + hpka->OperationCpltCallback(hpka); +#else + HAL_PKA_OperationCpltCallback(hpka); +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Process completed callback. + * @param hpka PKA handle + * @retval None + */ +__weak void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpka); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PKA_OperationCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Error callback. + * @param hpka PKA handle + * @retval None + */ +__weak void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpka); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PKA_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PKA_Exported_Functions_Group3 Peripheral State and Error functions + * @brief Peripheral State and Error functions + * + @verbatim + =============================================================================== + ##### Peripheral State and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PKA handle state. + * @param hpka PKA handle + * @retval HAL status + */ +HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka) +{ + /* Return PKA handle state */ + return hpka->State; +} + +/** + * @brief Return the PKA error code. + * @param hpka PKA handle + * @retval PKA error code + */ +uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka) +{ + /* Return PKA handle error code */ + return hpka->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup PKA_Private_Functions + * @{ + */ + +/** + * @brief Get PKA operating mode. + * @param hpka PKA handle + * @retval Return the current mode + */ +uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka) +{ + /* return the shifted PKA_CR_MODE value */ + return (uint32_t)(READ_BIT(hpka->Instance->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos); +} + +/** + * @brief Wait for operation completion or timeout. + * @param hpka PKA handle + * @param Timeout Timeout duration in millisecond. + * @param Tickstart Tick start value + * @retval HAL status + */ +HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart) +{ + /* Wait for the end of operation or timeout */ + while ((hpka->Instance->SR & PKA_SR_PROCENDF) == 0UL) + { + /* Check if timeout is disabled (set to infinite wait) */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0UL)) + { + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Return a hal error code based on PKA error flags. + * @param hpka PKA handle + * @param mode PKA operating mode + * @retval error code + */ +uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode) +{ + uint32_t err = HAL_PKA_ERROR_NONE; + + /* Check RAMERR error */ + if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR) == SET) + { + err |= HAL_PKA_ERROR_RAMERR; + } + + /* Check ADDRERR error */ + if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR) == SET) + { + err |= HAL_PKA_ERROR_ADDRERR; + } + + /* Check OPEERR error */ + if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_OPERR) == SET) + { + err |= HAL_PKA_ERROR_OPERATION; + } + + /* Check the operation success in case of ECDSA signature */ + if (mode == PKA_MODE_ECDSA_SIGNATURE) + { +#define EDCSA_SIGN_NOERROR PKA_NO_ERROR + /* If error output result is different from no error, ecsa sign operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_ERROR] != EDCSA_SIGN_NOERROR) + { + err |= HAL_PKA_ERROR_OPERATION; + } + } + + /* Check the operation success in case of ECC double base ladder*/ + if (mode == PKA_MODE_DOUBLE_BASE_LADDER) + { + /* If error output result is different from no error, PKA operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_ERROR] != PKA_NO_ERROR) + { + err |= HAL_PKA_ERROR_OPERATION; + } + } + + /* Check the operation success in case of ECC projective to affine*/ + if (mode == PKA_MODE_ECC_PROJECTIVE_AFF) + { + /* If error output result is different from no error, PKA operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_ERROR] != PKA_NO_ERROR) + { + err |= HAL_PKA_ERROR_OPERATION; + } + } + + /* Check the operation success in case of ECC Fp scalar multiplication*/ + if (mode == PKA_MODE_ECC_MUL) + { + /* If error output result is different from no error, PKA operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_ERROR] != PKA_NO_ERROR) + { + err |= HAL_PKA_ERROR_OPERATION; + } + } + + /* Check the operation success in case of protected modular exponentiation*/ + if (mode == PKA_MODE_MODULAR_EXP_PROTECT) + { + /* If error output result is different from no error, PKA operation need to be repeated */ + if (hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_ERROR] != PKA_NO_ERROR) + { + err |= HAL_PKA_ERROR_OPERATION; + } + } + + return err; +} + +/** + * @brief Get number of bits inside an array of u8. + * @param byteNumber Number of u8 inside the array + */ +uint32_t PKA_GetBitSize_u8(uint32_t byteNumber) +{ + /* Convert from number of uint8_t in an array to the associated number of bits in this array */ + return byteNumber * 8UL; +} + +/** + * @brief Get optimal number of bits inside an array of u8. + * @param byteNumber Number of u8 inside the array + * @param msb Most significant uint8_t of the array + */ +uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb) +{ + uint32_t position; + + position = 32UL - __CLZ(msb); + + return (((byteNumber - 1UL) * 8UL) + position); +} + +/** + * @brief Get number of bits inside an array of u32. + * @param wordNumber Number of u32 inside the array + */ +uint32_t PKA_GetBitSize_u32(uint32_t wordNumber) +{ + /* Convert from number of uint32_t in an array to the associated number of bits in this array */ + return wordNumber * 32UL; +} + +/** + * @brief Get number of uint8_t element in an array of bitSize bits. + * @param bitSize Number of bits in an array + */ +uint32_t PKA_GetArraySize_u8(uint32_t bitSize) +{ + /* Manage the non aligned on uint8_t bitsize: */ + /* 512 bits requires 64 uint8_t */ + /* 521 bits requires 66 uint8_t */ + return ((bitSize + 7UL) / 8UL); +} + +/** + * @brief Copy uint32_t array to uint8_t array to fit PKA number representation. + * @param dst Pointer to destination + * @param src Pointer to source + * @param n Number of uint8_t to copy + * @retval dst + */ +void PKA_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], size_t n) +{ + if (dst != NULL) + { + if (src != NULL) + { + uint32_t index_uint32_t = 0UL; /* This index is used outside of the loop */ + + for (; index_uint32_t < (n / 4UL); index_uint32_t++) + { + /* Avoid casting from uint8_t* to uint32_t* by copying 4 uint8_t in a row */ + /* Apply __REV equivalent */ + uint32_t index_uint8_t = n - 4UL - (index_uint32_t * 4UL); + dst[index_uint8_t + 3UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU)); + dst[index_uint8_t + 2UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL); + dst[index_uint8_t + 1UL] = (uint8_t)((src[index_uint32_t] & 0x00FF0000U) >> 16UL); + dst[index_uint8_t + 0UL] = (uint8_t)((src[index_uint32_t] & 0xFF000000U) >> 24UL); + } + + /* Manage the buffers not aligned on uint32_t */ + if ((n % 4UL) == 1UL) + { + dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU)); + } + else if ((n % 4UL) == 2UL) + { + dst[1UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU)); + dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL); + } + else if ((n % 4UL) == 3UL) + { + dst[2UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU)); + dst[1UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL); + dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x00FF0000U) >> 16UL); + } + else + { + /* The last element is already handle in the loop */ + } + } + } +} + +/** + * @brief Copy uint8_t array to uint32_t array to fit PKA number representation. + * @param dst Pointer to destination + * @param src Pointer to source + * @param n Number of uint8_t to copy (must be multiple of 4) + * @retval dst + */ +void PKA_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], size_t n) +{ + if (dst != NULL) + { + if (src != NULL) + { + uint32_t index = 0UL; /* This index is used outside of the loop */ + + for (; index < (n / 4UL); index++) + { + /* Apply the equivalent of __REV from uint8_t to uint32_t */ + dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \ + | ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL) \ + | ((uint32_t)src[(n - (index * 4UL) - 3UL)] << 16UL) \ + | ((uint32_t)src[(n - (index * 4UL) - 4UL)] << 24UL); + } + + /* Manage the buffers not aligned on uint32_t */ + if ((n % 4UL) == 1UL) + { + dst[index] = (uint32_t)src[(n - (index * 4UL) - 1UL)]; + } + else if ((n % 4UL) == 2UL) + { + dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \ + | ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL); + } + else if ((n % 4UL) == 3UL) + { + dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \ + | ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL) \ + | ((uint32_t)src[(n - (index * 4UL) - 3UL)] << 16UL); + } + else + { + /* The last element is already handle in the loop */ + } + } + } +} + +/** + * @brief Copy uint32_t array to uint32_t array. + * @param dst Pointer to destination + * @param src Pointer to source + * @param n Number of u32 to be handled + * @retval dst + */ +void PKA_Memcpy_u32_to_u32(__IO uint32_t dst[], __IO const uint32_t src[], size_t n) +{ + /* If a destination buffer is provided */ + if (dst != NULL) + { + /* If a source buffer is provided */ + if (src != NULL) + { + /* For each element in the array */ + for (uint32_t index = 0UL; index < n; index++) + { + /* Copy the content */ + dst[index] = src[index]; + } + } + } +} + +/** + * @brief Generic function to start a PKA operation in blocking mode. + * @param hpka PKA handle + * @param mode PKA operation + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef PKA_Process(PKA_HandleTypeDef *hpka, uint32_t mode, uint32_t Timeout) +{ + HAL_StatusTypeDef err = HAL_OK; + uint32_t tickstart; + + if (hpka->State == HAL_PKA_STATE_READY) + { + /* Set the state to busy */ + hpka->State = HAL_PKA_STATE_BUSY; + + /* Clear any pending error */ + hpka->ErrorCode = HAL_PKA_ERROR_NONE; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Set the mode and deactivate the interrupts */ + MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, + mode << PKA_CR_MODE_Pos); + + /* Start the computation */ + hpka->Instance->CR |= PKA_CR_START; + + /* Wait for the end of operation or timeout */ + if (PKA_PollEndOfOperation(hpka, Timeout, tickstart) != HAL_OK) + { + /* Abort any ongoing operation */ + CLEAR_BIT(hpka->Instance->CR, PKA_CR_EN); + + hpka->ErrorCode |= HAL_PKA_ERROR_TIMEOUT; + + /* Make ready for the next operation */ + SET_BIT(hpka->Instance->CR, PKA_CR_EN); + } + + /* Check error */ + hpka->ErrorCode |= PKA_CheckError(hpka, mode); + + /* Clear all flags */ + hpka->Instance->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + + /* Set the state to ready */ + hpka->State = HAL_PKA_STATE_READY; + + /* Manage the result based on encountered errors */ + if (hpka->ErrorCode != HAL_PKA_ERROR_NONE) + { + err = HAL_ERROR; + } + } + else + { + err = HAL_ERROR; + } + return err; +} + +/** + * @brief Generic function to start a PKA operation in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param mode PKA operation + * @retval HAL status + */ +HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode) +{ + HAL_StatusTypeDef err = HAL_OK; + + if (hpka->State == HAL_PKA_STATE_READY) + { + /* Set the state to busy */ + hpka->State = HAL_PKA_STATE_BUSY; + + /* Clear any pending error */ + hpka->ErrorCode = HAL_PKA_ERROR_NONE; + + /* Set the mode and activate interrupts */ + MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, + (mode << PKA_CR_MODE_Pos) | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE); + + /* Start the computation */ + hpka->Instance->CR |= PKA_CR_START; + } + else + { + err = HAL_ERROR; + } + return err; +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in) +{ + /* Get the number of bit per operand */ + hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize); + + /* Get the number of bit of the exponent */ + hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize); + + /* Move the input parameters pOp1 to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + ((in->OpSize + 3UL) / 4UL)); + + /* Move the exponent to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + ((in->expSize + 3UL) / 4UL)); + + /* Move the modulus to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + ((in->OpSize + 3UL) / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in) +{ + /* Get the number of bit per operand */ + hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize); + + /* Get the number of bit of the exponent */ + hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize); + + /* Move the input parameters pOp1 to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL)); + + /* Move the exponent to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL)); + + /* Move the modulus to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL)); + + /* Move the Montgomery parameter to PKA RAM */ + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, + in->OpSize / 4UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + (in->OpSize / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in) +{ + /* Get the number of bit per operand */ + hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize); + + /* Get the number of bit of the exponent */ + hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize); + + /* Move the input parameters pOp1 to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE], in->pOp1, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + (in->OpSize / 4UL)); + + /* Move the exponent to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT], in->pExp, in->expSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + (in->expSize / 4UL)); + + /* Move the modulus to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_MODULUS], in->pMod, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_MODULUS + (in->OpSize / 4UL)); + + /* Move Phi value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI], in->pPhi, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + (in->OpSize / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + * @note If the modulus size is bigger than the hash size (with a curve SECP521R1 when using a SHA256 hash + * for example)the hash value should be written at the end of the buffer with zeros padding at beginning. + */ +void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in) +{ + /* Get the prime order n length */ + hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder)); + + /* Get the modulus p length */ + hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus)); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF], in->coef, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters coefficient B to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_B_COEFF], in->coefB, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_GF], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters integer k to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_K], in->integer, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_K + ((in->primeOrderSize + 3UL) / 4UL)); + + /* Move the input parameters base point G coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters base point G coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters hash of message z to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_HASH_E], in->hash, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL)); + + /* Move the input parameters private key d to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D], in->privateKey, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + ((in->primeOrderSize + 3UL) / 4UL)); + + /* Move the input parameters prime order n to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_N], in->primeOrder, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in) +{ + /* Get the prime order n length */ + hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder)); + + /* Get the modulus p length */ + hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus)); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF], in->coef, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_GF], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters base point G coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters base point G coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X], in->pPubKeyCurvePtX, + in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y], in->pPubKeyCurvePtY, + in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters signature part r to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_R], in->RSign, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_R + ((in->primeOrderSize + 3UL) / 4UL)); + + /* Move the input parameters signature part s to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_S], in->SSign, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_S + ((in->primeOrderSize + 3UL) / 4UL)); + + /* Move the input parameters hash of message z to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_HASH_E], in->hash, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL)); + + /* Move the input parameters curve prime order n to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_N], in->primeOrder, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in) +{ + /* Get the operand length M */ + hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->size); + + /* Move the input parameters operand dP to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DP_CRT], in->pOpDp, in->size / 2UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_DP_CRT + (in->size / 8UL)); + + /* Move the input parameters operand dQ to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DQ_CRT], in->pOpDq, in->size / 2UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_DQ_CRT + (in->size / 8UL)); + + /* Move the input parameters operand qinv to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_QINV_CRT], in->pOpQinv, in->size / 2UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_QINV_CRT + (in->size / 8UL)); + + /* Move the input parameters prime p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_P], in->pPrimeP, in->size / 2UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_PRIME_P + (in->size / 8UL)); + + /* Move the input parameters prime q to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_Q], in->pPrimeQ, in->size / 2UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_PRIME_Q + (in->size / 8UL)); + + /* Move the input parameters operand A to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_EXPONENT_BASE], in->popA, in->size); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_EXPONENT_BASE + (in->size / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_PointCheck_Set(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in) +{ + /* Get the modulus length */ + hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus)); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF], in->coefA, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters coefficient b to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_B_COEFF], in->coefB, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_GF], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters montgomery param R2 modulus N to PKA RAM */ + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, + (in->modulusSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_MONTGOMERY_PARAM + ((in->modulusSize + 3UL) / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in) +{ + /* Get the prime order n length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = PKA_GetOptBitSize_u8(in->scalarMulSize, *(in->primeOrder)); + + /* Get the modulus length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus)); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters coefficient b to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters scalar multiplier k to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], in->pointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters curve prime order N to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL)); +} +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in) +{ + /* Get the prime order n length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder)); + + /* Get the modulus length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus)); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters coefficient b to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters scalar multiplier k to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], in->pointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters curve prime order N to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ModInv_Set(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in) +{ + /* Get the number of bit per operand */ + hpka->Instance->RAM[PKA_MODULAR_INV_NB_BITS] = PKA_GetBitSize_u32(in->size); + + /* Move the input parameters operand A to PKA RAM */ + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP1], in->pOp1, in->size); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_INV_IN_OP1 + in->size); + + /* Move the input parameters modulus value n to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP2_MOD], in->pMod, in->size * 4UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_INV_IN_OP2_MOD + in->size); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in) +{ + /* Get the number of bit per operand */ + hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OP_LENGTH] = PKA_GetBitSize_u32(in->OpSize); + + /* Get the number of bit per modulus */ + hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MOD_LENGTH] = PKA_GetBitSize_u8(in->modSize); + + /* Move the input parameters operand A to PKA RAM */ + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OPERAND], in->pOp1, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_OPERAND + in->OpSize); + + /* Move the input parameters modulus value n to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS], in->pMod, in->modSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + ((in->modSize + 3UL) / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param size Size of the operand + * @param pOp1 Generic pointer to input data + */ +void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1) +{ + uint32_t bytetoskip = 0UL; + uint32_t newSize; + + if (pOp1 != NULL) + { + /* Count the number of zero bytes */ + while ((bytetoskip < size) && (pOp1[bytetoskip] == 0UL)) + { + bytetoskip++; + } + + /* Get new size after skipping zero bytes */ + newSize = size - bytetoskip; + + /* Get the number of bit per operand */ + hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(newSize, pOp1[bytetoskip]); + + /* Move the input parameters pOp1 to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MODULUS], pOp1, size); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MONTGOMERY_PARAM_IN_MODULUS + ((size + 3UL) / 4UL)); + } +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECCDoubleBaseLadder_Set(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in) +{ + /* Get the prime order n length */ + hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS] = PKA_GetBitSize_u8(in->primeOrderSize); + + /* Get the modulus p length */ + hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->modulusSize); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_A_COEFF], in->coefA, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_A_COEFF + (in->modulusSize / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_MOD_P], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_MOD_P + (in->modulusSize / 4UL)); + + /* Move the input parameters integer k to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER], in->integerK, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER + (in->modulusSize / 4UL)); + + /* Move the input parameters integer m to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER], in->integerM, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER + (in->modulusSize / 4UL)); + + /* Move the input parameters first point coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT1_X], in->basePointX1, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT1_X + (in->modulusSize / 4UL)); + + /* Move the input parameters first point coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y], in->basePointY1, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y + (in->modulusSize / 4UL)); + + /* Move the input parameters first point coordinate z to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z], in->basePointZ1, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z + (in->modulusSize / 4UL)); + + /* Move the input parameters second point coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT2_X], in->basePointX2, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT2_X + (in->modulusSize / 4UL)); + + /* Move the input parameters second point coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y], in->basePointY2, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y + (in->modulusSize / 4UL)); + + /* Move the input parameters second point coordinate z to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z], in->basePointZ2, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z + (in->modulusSize / 4UL)); +} + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param out Output information + * @retval HAL status + */ +void HAL_PKA_ECCDoubleBaseLadder_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderOutTypeDef *out) +{ + uint32_t size; + + /* Move the result to appropriate location (indicated in out parameter) */ + size = hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS] / 8UL; + if (out != NULL) + { + PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X], size); + PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y], size); + } +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECCProjective2Affine_Set(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in) +{ + /* Get the modulus p length */ + hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->modulusSize); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MOD_P], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_MOD_P + (in->modulusSize / 4UL)); + + /* Move the input parameters point coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_POINT_X], in->basePointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_POINT_X + (in->modulusSize / 4UL)); + + /* Move the input parameters point coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y], in->basePointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y + (in->modulusSize / 4UL)); + + /* Move the input parameters point coordinate z to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z], in->basePointZ, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z + (in->modulusSize / 4UL)); + + /* Move the input parameters montgomery parameter R2 modulus n to PKA RAM */ + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2], in->pMontgomeryParam, + (in->modulusSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 + (in->modulusSize / 4UL)); +} + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param out Output information + * @retval HAL status + */ +void HAL_PKA_ECCProjective2Affine_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineOutTypeDef *out) +{ + uint32_t size; + + /* Move the result to appropriate location (indicated in out parameter) */ + size = hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS] / 8UL; + if (out != NULL) + { + PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X], size); + PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y], size); + } +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECCCompleteAddition_Set(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in) +{ + /* Get the modulus p length */ + hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->modulusSize); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_MOD_P], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_MOD_P + (in->modulusSize / 4UL)); + + /* Move the input parameters coefA value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_A_COEFF], in->coefA, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_A_COEFF + (in->modulusSize / 4UL)); + + /* Move the input parameters first point x value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT1_X], in->basePointX1, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT1_X + (in->modulusSize / 4UL)); + + /* Move the input parameters first point y value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT1_Y], in->basePointY1, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT1_Y + (in->modulusSize / 4UL)); + + /* Move the input parameters first point z value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT1_Z], in->basePointZ1, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT1_Z + (in->modulusSize / 4UL)); + + /* Move the input parameters second point x value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT2_X], in->basePointX2, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT2_X + (in->modulusSize / 4UL)); + + /* Move the input parameters second point y value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT2_Y], in->basePointY2, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT2_Y + (in->modulusSize / 4UL)); + + /* Move the input parameters second point z value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT2_Z], in->basePointZ2, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT2_Z + (in->modulusSize / 4UL)); +} + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param out Output information + * @retval HAL status + */ +void HAL_PKA_ECCCompleteAddition_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionOutTypeDef *out) +{ + uint32_t size; + + /* Move the result to appropriate location (indicated in out parameter) */ + size = (hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS] + 7UL) / 8UL; + if (out != NULL) + { + PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_X], size); + PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y], size); + PKA_Memcpy_u32_to_u8(out->ptZ, &hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z], size); + } +} +/** + * @brief Generic function to set input parameters. + * @param hpka PKA handle + * @param size Size of the operand + * @param pOp1 Generic pointer to input data + * @param pOp2 Generic pointer to input data + * @param pOp3 Generic pointer to input data + */ +void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2, + const uint8_t *pOp3) +{ + /* Get the number of bit per operand */ + hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_NB_BITS] = PKA_GetBitSize_u32(size); + + if (pOp1 != NULL) + { + /* Move the input parameters pOp1 to PKA RAM */ + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP1], pOp1, size); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP1 + size); + } + + if (pOp2 != NULL) + { + /* Move the input parameters pOp2 to PKA RAM */ + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP2], pOp2, size); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP2 + size); + } + + if (pOp3 != NULL) + { + /* Move the input parameters pOp3 to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP3], pOp3, size * 4UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP3 + size); + } +} +/** + * @brief Handle PKA init Timeout. + * @param hpka PKA handle. + * @param Flag Specifies the PKA flag to check + * @param Status Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while (__HAL_PKA_GET_FLAG(hpka, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + /* Set the state to ready */ + hpka->State = HAL_PKA_STATE_READY; + + /* Set the error code to timeout error */ + hpka->ErrorCode = HAL_PKA_ERROR_TIMEOUT; + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Get the size of output result. + * @param hpka PKA handle + * @param Startindex Specifies the start index of the result in the PKA RAM + * @param Maxsize Specifies the possible max size of the result in words + * @retval size + */ +uint32_t PKA_Result_GetSize(const PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize) +{ + uint32_t size; + uint32_t current_index = Maxsize - 1UL; + + /* Determinate the last index of the result in the PKA RAM */ + while ((hpka->Instance->RAM[Startindex + current_index] == 0UL) && (current_index != 0UL)) + { + current_index--; + } + /* Get the size in bytes */ + size = (current_index + 1UL) * 4UL; + + return size; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pssi.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pssi.c new file mode 100644 index 00000000000..d554dca2d99 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pssi.c @@ -0,0 +1,1929 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_pssi.c + * @author MCD Application Team + * @brief PSSI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Parallel Synchronous Slave Interface (PSSI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The PSSI HAL driver can be used as follows: + + (#) Declare a PSSI_HandleTypeDef handle structure, for example: + PSSI_HandleTypeDef hpssi; + + (#) Initialize the PSSI low level resources by implementing the @ref HAL_PSSI_MspInit() API: + (##) Enable the PSSIx interface clock + (##) PSSI pins configuration + (+++) Enable the clock for the PSSI GPIOs + (+++) Configure PSSI pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the PSSIx interrupt priority + (+++) Enable the NVIC PSSI IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare DMA_HandleTypeDef handles structure for the transmit and receive + (+++) Enable the DMAx interface clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx and Rx + (+++) Associate the initialized DMA handle to the hpssi DMA Tx and Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx and Rx + + (#) Configure the Communication Bus Width, Control Signals, Input Polarity and Output Polarity + in the hpssi Init structure. + + (#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API. + + (#) Configure the PSSI clock as internal or external by calling the @ref HAL_PSSI_ClockConfig(). + + (#) For PSSI IO operations, two operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit an amount of data by byte in blocking mode using @ref HAL_PSSI_Transmit() + (+) Receive an amount of data by byte in blocking mode using @ref HAL_PSSI_Receive() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit an amount of data in non-blocking mode (DMA) using + @ref HAL_PSSI_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_PSSI_TxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_PSSI_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode (DMA) using + @ref HAL_PSSI_Receive_DMA() + (+) At reception end of transfer, @ref HAL_PSSI_RxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_PSSI_RxCpltCallback() + (+) In case of transfer Error, @ref HAL_PSSI_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_PSSI_ErrorCallback() + (+) Abort a PSSI process communication with Interrupt using @ref HAL_PSSI_Abort_IT() + (+) End of abort process, @ref HAL_PSSI_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_PSSI_AbortCpltCallback() + + *** PSSI HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in PSSI HAL driver. + + (+) @ref HAL_PSSI_ENABLE : Enable the PSSI peripheral + (+) @ref HAL_PSSI_DISABLE : Disable the PSSI peripheral + (+) @ref HAL_PSSI_GET_FLAG : Check whether the specified PSSI flag is set or not + (+) @ref HAL_PSSI_CLEAR_FLAG : Clear the specified PSSI pending flag + (+) @ref HAL_PSSI_ENABLE_IT : Enable the specified PSSI interrupt + (+) @ref HAL_PSSI_DISABLE_IT : Disable the specified PSSI interrupt + + *** Callback registration *** + ============================================= + Use Functions @ref HAL_PSSI_RegisterCallback() or @ref HAL_PSSI_RegisterAddrCallback() + to register an interrupt callback. + + Function @ref HAL_PSSI_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : callback for transmission end of transfer. + (+) RxCpltCallback : callback for reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + Use function @ref HAL_PSSI_UnRegisterCallback to reset a callback to the default + weak function. + @ref HAL_PSSI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : callback for transmission end of transfer. + (+) RxCpltCallback : callback for reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + + + By default, after the @ref HAL_PSSI_Init() and when the state is @ref HAL_PSSI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_PSSI_TxCpltCallback(), @ref HAL_PSSI_RxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + Callbacks can be registered/unregistered in @ref HAL_PSSI_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_PSSI_STATE_READY or @ref HAL_PSSI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_PSSI_RegisterCallback() before calling @ref HAL_PSSI_DeInit() + or @ref HAL_PSSI_Init() function. + + + [..] + (@) You can refer to the PSSI HAL driver header file for more useful macros + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup PSSI PSSI + * @brief PSSI HAL module driver + * @{ + */ + +#ifdef HAL_PSSI_MODULE_ENABLED +#if defined(PSSI) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PSSI_Private_Define PSSI Private Define + * @{ + */ + + + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup PSSI_Private_Functions PSSI Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +#if defined(HAL_DMA_MODULE_ENABLED) +void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +void PSSI_DMAError(DMA_HandleTypeDef *hdma); +void PSSI_DMAAbort(DMA_HandleTypeDef *hdma); +#endif /*HAL_DMA_MODULE_ENABLED*/ + +/* Private functions to handle IT transfer */ +static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode); + + +/* Private functions for PSSI transfer IRQ handler */ + + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PSSI_Exported_Functions PSSI Exported Functions + * @{ + */ + +/** @defgroup PSSI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the PSSIx peripheral: + + (+) User must implement HAL_PSSI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_PSSI_Init() to configure the selected device with + the selected configuration: + (++) Data Width + (++) Control Signals + (++) Input Clock polarity + (++) Output Clock polarity + + (+) Call the function HAL_PSSI_DeInit() to restore the default configuration + of the selected PSSIx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the PSSI according to the specified parameters + * in the PSSI_InitTypeDef and initialize the associated handle. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi) +{ + /* Check the PSSI handle allocation */ + if (hpssi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_PSSI_ALL_INSTANCE(hpssi->Instance)); + assert_param(IS_PSSI_CONTROL_SIGNAL(hpssi->Init.ControlSignal)); + assert_param(IS_PSSI_BUSWIDTH(hpssi->Init.BusWidth)); + assert_param(IS_PSSI_CLOCK_POLARITY(hpssi->Init.ClockPolarity)); + assert_param(IS_PSSI_DE_POLARITY(hpssi->Init.DataEnablePolarity)); + assert_param(IS_PSSI_RDY_POLARITY(hpssi->Init.ReadyPolarity)); + + if (hpssi->State == HAL_PSSI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpssi->Lock = HAL_UNLOCKED; + +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) + /* Init the PSSI Callback settings */ + hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hpssi->ErrorCallback = HAL_PSSI_ErrorCallback; /* Legacy weak ErrorCallback */ + hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + + if (hpssi->MspInitCallback == NULL) + { + hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hpssi->MspInitCallback(hpssi); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_PSSI_MspInit(hpssi); +#endif /*USE_HAL_PSSI_REGISTER_CALLBACKS*/ + } + + hpssi->State = HAL_PSSI_STATE_BUSY; + + /* Disable the selected PSSI peripheral */ + HAL_PSSI_DISABLE(hpssi); + + /*---------------------------- PSSIx CR Configuration ----------------------*/ + /* Configure PSSIx: Control Signal and Bus Width*/ + + MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DERDYCFG | PSSI_CR_EDM | PSSI_CR_DEPOL | PSSI_CR_RDYPOL, + hpssi->Init.ControlSignal | hpssi->Init.DataEnablePolarity | + hpssi->Init.ReadyPolarity | hpssi->Init.BusWidth); + + hpssi->ErrorCode = HAL_PSSI_ERROR_NONE; + hpssi->State = HAL_PSSI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the PSSI peripheral. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi) +{ + /* Check the PSSI handle allocation */ + if (hpssi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_PSSI_ALL_INSTANCE(hpssi->Instance)); + + hpssi->State = HAL_PSSI_STATE_BUSY; + + /* Disable the PSSI Peripheral Clock */ + HAL_PSSI_DISABLE(hpssi); + +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) + if (hpssi->MspDeInitCallback == NULL) + { + hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hpssi->MspDeInitCallback(hpssi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_PSSI_MspDeInit(hpssi); +#endif /*USE_HAL_PSSI_REGISTER_CALLBACKS*/ + + hpssi->ErrorCode = HAL_PSSI_ERROR_NONE; + hpssi->State = HAL_PSSI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hpssi); + + return HAL_OK; +} + +/** + * @brief Initialize the PSSI MSP. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @retval None + */ +__weak void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpssi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PSSI_MspInit can be implemented in the user file + */ +} + +/** + * @brief De-Initialize the PSSI MSP. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @retval None + */ +__weak void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpssi); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_PSSI_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User PSSI Callback + * To be used instead of the weak predefined callback + * @note The HAL_PSSI_RegisterCallback() may be called before HAL_PSSI_Init() in + * HAL_PSSI_STATE_RESET to register callbacks for HAL_PSSI_MSPINIT_CB_ID + * and HAL_PSSI_MSPDEINIT_CB_ID. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_PSSI_TX_COMPLETE_CB_ID Tx Transfer completed callback ID + * @arg @ref HAL_PSSI_RX_COMPLETE_CB_ID Rx Transfer completed callback ID + * @arg @ref HAL_PSSI_ERROR_CB_ID Error callback ID + * @arg @ref HAL_PSSI_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_PSSI_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_PSSI_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, + pPSSI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_PSSI_STATE_READY == hpssi->State) + { + switch (CallbackID) + { + case HAL_PSSI_TX_COMPLETE_CB_ID : + hpssi->TxCpltCallback = pCallback; + break; + + case HAL_PSSI_RX_COMPLETE_CB_ID : + hpssi->RxCpltCallback = pCallback; + break; + + case HAL_PSSI_ERROR_CB_ID : + hpssi->ErrorCallback = pCallback; + break; + + case HAL_PSSI_ABORT_CB_ID : + hpssi->AbortCpltCallback = pCallback; + break; + + case HAL_PSSI_MSPINIT_CB_ID : + hpssi->MspInitCallback = pCallback; + break; + + case HAL_PSSI_MSPDEINIT_CB_ID : + hpssi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_PSSI_STATE_RESET == hpssi->State) + { + switch (CallbackID) + { + case HAL_PSSI_MSPINIT_CB_ID : + hpssi->MspInitCallback = pCallback; + break; + + case HAL_PSSI_MSPDEINIT_CB_ID : + hpssi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an PSSI Callback + * PSSI callback is redirected to the weak predefined callback + * @note The HAL_PSSI_UnRegisterCallback() may be called before HAL_PSSI_Init() in + * HAL_PSSI_STATE_RESET to un-register callbacks for HAL_PSSI_MSPINIT_CB_ID + * and HAL_PSSI_MSPDEINIT_CB_ID. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_PSSI_TX_COMPLETE_CB_ID Tx Transfer completed callback ID + * @arg @ref HAL_PSSI_RX_COMPLETE_CB_ID Rx Transfer completed callback ID + * @arg @ref HAL_PSSI_ERROR_CB_ID Error callback ID + * @arg @ref HAL_PSSI_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_PSSI_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_PSSI_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_PSSI_STATE_READY == hpssi->State) + { + switch (CallbackID) + { + case HAL_PSSI_TX_COMPLETE_CB_ID : + hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_PSSI_RX_COMPLETE_CB_ID : + hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_PSSI_ERROR_CB_ID : + hpssi->ErrorCallback = HAL_PSSI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_PSSI_ABORT_CB_ID : + hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_PSSI_MSPINIT_CB_ID : + hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_PSSI_MSPDEINIT_CB_ID : + hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_PSSI_STATE_RESET == hpssi->State) + { + switch (CallbackID) + { + case HAL_PSSI_MSPINIT_CB_ID : + hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_PSSI_MSPDEINIT_CB_ID : + hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup PSSI_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PSSI data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using DMA. + These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated the DMA IRQ . + + (#) Blocking mode functions are : + (++) HAL_PSSI_Transmit() + (++) HAL_PSSI_Receive() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_PSSI_Transmit_DMA() + (++) HAL_PSSI_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_PSSI_TxCpltCallback() + (++) HAL_PSSI_RxCpltCallback() + (++) HAL_PSSI_ErrorCallback() + (++) HAL_PSSI_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent (in bytes) + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t transfer_size = Size; + + if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) || + ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size % 2U) != 0U)) || + ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size % 4U) != 0U))) + { + hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + if (hpssi->State == HAL_PSSI_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hpssi); + + hpssi->State = HAL_PSSI_STATE_BUSY; + hpssi->ErrorCode = HAL_PSSI_ERROR_NONE; + + /* Disable the selected PSSI peripheral */ + HAL_PSSI_DISABLE(hpssi); + + /* Configure transfer parameters */ + MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL), + (PSSI_CR_OUTEN_OUTPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL))); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* DMA Disable */ + hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE; +#endif /*HAL_DMA_MODULE_ENABLED*/ + + /* Enable the selected PSSI peripheral */ + HAL_PSSI_ENABLE(hpssi); + + if (hpssi->Init.DataWidth == HAL_PSSI_8BITS) + { + uint8_t *pbuffer = pData; + while (transfer_size > 0U) + { + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + /* Wait until Fifo is ready to transfer one byte flag is set */ + if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT1B, RESET, Timeout, tickstart) != HAL_OK) + { + hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT; + hpssi->State = HAL_PSSI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + return HAL_ERROR; + } + /* Write data to DR */ + *(__IO uint8_t *)(&hpssi->Instance->DR) = *(uint8_t *)pbuffer; + + /* Increment Buffer pointer */ + pbuffer++; + + transfer_size--; + } + } + else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS) + { + uint16_t *pbuffer = (uint16_t *)pData; + __IO uint16_t *dr = (__IO uint16_t *)(&hpssi->Instance->DR); + + while (transfer_size > 0U) + { + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + /* Wait until Fifo is ready to transfer four bytes flag is set */ + if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK) + { + hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT; + hpssi->State = HAL_PSSI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + return HAL_ERROR; + } + /* Write data to DR */ + *dr = *pbuffer; + + /* Increment Buffer pointer */ + pbuffer++; + transfer_size -= 2U; + } + } + else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS) + { + uint32_t *pbuffer = (uint32_t *)pData; + while (transfer_size > 0U) + { + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + /* Wait until Fifo is ready to transfer four bytes flag is set */ + if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK) + { + hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT; + hpssi->State = HAL_PSSI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + return HAL_ERROR; + } + /* Write data to DR */ + *(__IO uint32_t *)(&hpssi->Instance->DR) = *pbuffer; + + /* Increment Buffer pointer */ + pbuffer++; + transfer_size -= 4U; + } + } + else + { + hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED; + hpssi->State = HAL_PSSI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + return HAL_ERROR; + } + + /* Check Errors Flags */ + if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_RIS) != 0U) + { + HAL_PSSI_CLEAR_FLAG(hpssi, PSSI_FLAG_OVR_RIS); + HAL_PSSI_DISABLE(hpssi); + hpssi->ErrorCode = HAL_PSSI_ERROR_UNDER_RUN; + hpssi->State = HAL_PSSI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + return HAL_ERROR; + } + + hpssi->State = HAL_PSSI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in blocking mode. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @param pData Pointer to data buffer + * @param Size Amount of data to be received (in bytes) + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t transfer_size = Size; + + if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) || + ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size % 2U) != 0U)) || + ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size % 4U) != 0U))) + { + hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + if (hpssi->State == HAL_PSSI_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hpssi); + + hpssi->State = HAL_PSSI_STATE_BUSY; + hpssi->ErrorCode = HAL_PSSI_ERROR_NONE; + + /* Disable the selected PSSI peripheral */ + HAL_PSSI_DISABLE(hpssi); + /* Configure transfer parameters */ + MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL), + (PSSI_CR_OUTEN_INPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL))); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* DMA Disable */ + hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE; +#endif /*HAL_DMA_MODULE_ENABLED*/ + + /* Enable the selected PSSI peripheral */ + HAL_PSSI_ENABLE(hpssi); + if (hpssi->Init.DataWidth == HAL_PSSI_8BITS) + { + uint8_t *pbuffer = pData; + + while (transfer_size > 0U) + { + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + /* Wait until Fifo is ready to receive one byte flag is set */ + if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT1B, RESET, Timeout, tickstart) != HAL_OK) + { + hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT; + hpssi->State = HAL_PSSI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + return HAL_ERROR; + } + /* Read data from DR */ + *pbuffer = *(__IO uint8_t *)(&hpssi->Instance->DR); + pbuffer++; + transfer_size--; + } + } + else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS) + { + uint16_t *pbuffer = (uint16_t *)pData; + __IO uint16_t *dr = (__IO uint16_t *)(&hpssi->Instance->DR); + + while (transfer_size > 0U) + { + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + /* Wait until Fifo is ready to receive four bytes flag is set */ + if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK) + { + hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT; + hpssi->State = HAL_PSSI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + return HAL_ERROR; + } + + /* Read data from DR */ + *pbuffer = *dr; + pbuffer++; + transfer_size -= 2U; + } + } + else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS) + { + uint32_t *pbuffer = (uint32_t *)pData; + + while (transfer_size > 0U) + { + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + /* Wait until Fifo is ready to receive four bytes flag is set */ + if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK) + { + hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT; + hpssi->State = HAL_PSSI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + return HAL_ERROR; + } + + /* Read data from DR */ + *pbuffer = *(__IO uint32_t *)(&hpssi->Instance->DR); + pbuffer++; + transfer_size -= 4U; + } + } + else + { + hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED; + hpssi->State = HAL_PSSI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + return HAL_ERROR; + } + /* Check Errors Flags */ + + if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_RIS) != 0U) + { + HAL_PSSI_CLEAR_FLAG(hpssi, PSSI_FLAG_OVR_RIS); + hpssi->ErrorCode = HAL_PSSI_ERROR_OVER_RUN; + __HAL_UNLOCK(hpssi); + return HAL_ERROR; + } + + hpssi->State = HAL_PSSI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Transmit an amount of data in non-blocking mode with DMA + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent (in bytes) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hpssi->State == HAL_PSSI_STATE_READY) + { + + /* Process Locked */ + __HAL_LOCK(hpssi); + + hpssi->State = HAL_PSSI_STATE_BUSY_TX; + hpssi->ErrorCode = HAL_PSSI_ERROR_NONE; + + /* Disable the selected PSSI peripheral */ + HAL_PSSI_DISABLE(hpssi); + + /* Prepare transfer parameters */ + hpssi->pBuffPtr = pData; + hpssi->XferCount = Size; + + if (hpssi->XferCount > PSSI_MAX_NBYTE_SIZE) + { + hpssi->XferSize = PSSI_MAX_NBYTE_SIZE; + } + else + { + hpssi->XferSize = hpssi->XferCount; + } + + if (hpssi->XferSize > 0U) + { + if (hpssi->hdmatx != NULL) + { + + /* Configure BusWidth */ + if (hpssi->hdmatx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE) + { + MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, + PSSI_CR_DMA_ENABLE | PSSI_CR_OUTEN_OUTPUT | + ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL)); + } + else + { + MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, + PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | PSSI_CR_OUTEN_OUTPUT | + ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL)); + } + + /* Set the PSSI DMA transfer complete callback */ + hpssi->hdmatx->XferCpltCallback = PSSI_DMATransmitCplt; + + /* Set the DMA error callback */ + hpssi->hdmatx->XferErrorCallback = PSSI_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hpssi->hdmatx->XferHalfCpltCallback = NULL; + hpssi->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA */ + if ((hpssi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hpssi->hdmatx->LinkedListQueue != NULL) + { + /* Enable the DMA channel */ + /* Set DMA data size */ + hpssi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hpssi->XferSize; + /* Set DMA source address */ + hpssi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + /* Set DMA destination address */ + hpssi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&hpssi->Instance->DR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hpssi->hdmatx); + } + else + { + /* Return error status */ + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmatx, (uint32_t)pData, (uint32_t)&hpssi->Instance->DR, + hpssi->XferSize); + } + } + else + { + /* Update PSSI state */ + hpssi->State = HAL_PSSI_STATE_READY; + + /* Update PSSI error code */ + hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hpssi->XferCount -= hpssi->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + /* Note : The PSSI interrupts must be enabled after unlocking current process + to avoid the risk of PSSI interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); + + /* Enable DMA Request */ + hpssi->Instance->CR |= PSSI_CR_DMA_ENABLE; + /* Enable the selected PSSI peripheral */ + HAL_PSSI_ENABLE(hpssi); + } + else + { + /* Update PSSI state */ + hpssi->State = HAL_PSSI_STATE_READY; + + /* Update PSSI error code */ + hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + return HAL_ERROR; + } + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + /* Note : The PSSI interrupts must be enabled after unlocking current process + to avoid the risk of PSSI interrupt handle execution before current + process unlock */ + /* Enable ERRinterrupt */ + /* possible to enable all of these */ + + HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @param pData Pointer to data buffer + * @param Size Amount of data to be received (in bytes) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size) +{ + + HAL_StatusTypeDef dmaxferstatus; + + if (hpssi->State == HAL_PSSI_STATE_READY) + { + + /* Disable the selected PSSI peripheral */ + HAL_PSSI_DISABLE(hpssi); + /* Process Locked */ + __HAL_LOCK(hpssi); + + hpssi->State = HAL_PSSI_STATE_BUSY_RX; + hpssi->ErrorCode = HAL_PSSI_ERROR_NONE; + + /* Prepare transfer parameters */ + hpssi->pBuffPtr = pData; + hpssi->XferCount = Size; + + if (hpssi->XferCount > PSSI_MAX_NBYTE_SIZE) + { + hpssi->XferSize = PSSI_MAX_NBYTE_SIZE; + } + else + { + hpssi->XferSize = hpssi->XferCount; + } + + if (hpssi->XferSize > 0U) + { + if (hpssi->hdmarx != NULL) + { + /* Configure BusWidth */ + if (hpssi->hdmarx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE) + { + MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, PSSI_CR_DMA_ENABLE | + ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U)); + } + else + { + MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, + PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | + ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U)); + } + + /* Set the PSSI DMA transfer complete callback */ + hpssi->hdmarx->XferCpltCallback = PSSI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hpssi->hdmarx->XferErrorCallback = PSSI_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hpssi->hdmarx->XferHalfCpltCallback = NULL; + hpssi->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA */ + if ((hpssi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hpssi->hdmarx->LinkedListQueue != NULL) + { + /* Enable the DMA channel */ + /* Set DMA data size */ + hpssi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hpssi->XferSize; + /* Set DMA source address */ + hpssi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&hpssi->Instance->DR; + /* Set DMA destination address */ + hpssi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hpssi->hdmarx); + } + else + { + /* Return error status */ + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmarx, (uint32_t)&hpssi->Instance->DR, (uint32_t)pData, + hpssi->XferSize); + } + } + else + { + /* Update PSSI state */ + hpssi->State = HAL_PSSI_STATE_READY; + + /* Update PSSI error code */ + hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hpssi->XferCount -= hpssi->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + /* Note : The PSSI interrupts must be enabled after unlocking current process + to avoid the risk of PSSI interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); + + /* Enable DMA Request */ + hpssi->Instance->CR |= PSSI_CR_DMA_ENABLE; + /* Enable the selected PSSI peripheral */ + HAL_PSSI_ENABLE(hpssi); + } + else + { + /* Update PSSI state */ + hpssi->State = HAL_PSSI_STATE_READY; + + /* Update PSSI error code */ + hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + return HAL_ERROR; + } + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + /* Enable ERR,interrupt */ + HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a DMA process communication with Interrupt. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi) +{ + /* Process Locked */ + __HAL_LOCK(hpssi); + + /* Disable Interrupts */ + HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); + + /* Set State at HAL_PSSI_STATE_ABORT */ + hpssi->State = HAL_PSSI_STATE_ABORT; + + /* Abort DMA TX transfer if any */ + if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN) + { + if (hpssi->State == HAL_PSSI_STATE_BUSY_TX) + { + hpssi->Instance->CR &= ~PSSI_CR_DMAEN; + + if (hpssi->hdmatx != NULL) + { + /* Set the PSSI DMA Abort callback : + will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */ + hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx); + } + } + } + /* Abort DMA RX transfer if any */ + else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX) + { + hpssi->Instance->CR &= ~PSSI_CR_DMAEN; + + if (hpssi->hdmarx != NULL) + { + /* Set the PSSI DMA Abort callback : + will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */ + hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK) + { + /* Call Directly hpssi->hdma->XferAbortCallback function in case of error */ + hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx); + } + } + } + else + { + + /* Call the error callback */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) + hpssi->ErrorCallback(hpssi); +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + /* Note : The PSSI interrupts must be enabled after unlocking current process + to avoid the risk of PSSI interrupt handle execution before current + process unlock */ + HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); + + return HAL_OK; +} +#endif /*HAL_DMA_MODULE_ENABLED*/ + +/** + * @} + */ + +/** @addtogroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles PSSI event interrupt request. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @retval None + */ +void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi) +{ + /* Overrun/ Underrun Errors */ + if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_MIS) != 0U) + { + /* Reset handle parameters */ + hpssi->XferCount = 0U; + + /* Disable all interrupts */ + HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort DMA TX transfer if any */ + if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN) + { + if (hpssi->State == HAL_PSSI_STATE_BUSY_TX) + { + /* Set new error code */ + hpssi->ErrorCode |= HAL_PSSI_ERROR_UNDER_RUN; + + hpssi->Instance->CR &= ~PSSI_CR_DMAEN; + + if (hpssi->hdmatx != NULL) + { + /* Set the PSSI DMA Abort callback : + will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */ + hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx); + } + } + } + /* Abort DMA RX transfer if any */ + else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX) + { + /* Set new error code */ + hpssi->ErrorCode |= HAL_PSSI_ERROR_OVER_RUN; + + hpssi->Instance->CR &= ~PSSI_CR_DMAEN; + + if (hpssi->hdmarx != NULL) + { + /* Set the PSSI DMA Abort callback : + will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */ + hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK) + { + /* Call Directly hpssi->hdma->XferAbortCallback function in case of error */ + hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx); + } + } + } + else + { +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) + /* Call the corresponding callback to inform upper layer of the error */ + hpssi->ErrorCallback(hpssi); +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + } + } +#endif /*HAL_DMA_MODULE_ENABLED*/ + + /* If state is an abort treatment on going, don't change state */ + if (hpssi->State == HAL_PSSI_STATE_ABORT) + { + hpssi->State = HAL_PSSI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) + /* Call the corresponding callback to inform upper layer of End of Transfer */ + hpssi->AbortCpltCallback(hpssi); +#else + HAL_PSSI_AbortCpltCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + } + else + { + /* Set HAL_PSSI_STATE_READY */ + hpssi->State = HAL_PSSI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) + /* Call the corresponding callback to inform upper layer of End of Transfer */ + hpssi->ErrorCallback(hpssi); +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Tx Transfer complete callback. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @retval None + */ +__weak void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpssi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PSSI_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer complete callback. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @retval None + */ +__weak void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpssi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PSSI_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief PSSI error callback. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @retval None + */ +__weak void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpssi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PSSI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief PSSI abort callback. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @retval None + */ +__weak void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpssi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PSSI_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PSSI_Exported_Functions_Group3 Peripheral State and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PSSI handle state. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @retval HAL state + */ +HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi) +{ + /* Return PSSI handle state */ + return hpssi->State; +} + +/** + * @brief Return the PSSI error code. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @retval PSSI Error Code + */ +uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi) +{ + return hpssi->ErrorCode; +} + +/** + * @} + */ + +/** @defgroup PSSI_Exported_Functions_Group4 Clock Source Selection function + * @brief Clock Source Selection function to pick between an internal or + * external clock. + * +@verbatim + =============================================================================== + ##### Clock Source Selection function ##### + =============================================================================== + [..] This subsection provides a function allowing to: + (+) Configure Clock source + (++) The clock source could be external (default) or internal (the clock + is generated by the device RCC). + (++) The AHB clock frequency must be at least 2.5 times higher than the + PSSI_PDCK frequency + +@endverbatim + * @{ + */ + +/** + * @brief Configure PSSI Clock Source. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI peripheral. + * @param ClockSource New Clock Configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PSSI_ClockConfig(PSSI_HandleTypeDef *hpssi, uint32_t ClockSource) +{ + /* Check the parameter */ + assert_param(IS_PSSI_CLOCK_SOURCE(ClockSource)); + + if (hpssi->State == HAL_PSSI_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hpssi); + + HAL_PSSI_DISABLE(hpssi); + + /* Set CKSRC to ClockSource */ + MODIFY_REG(hpssi->Instance->CR, PSSI_CR_CKSRC, ClockSource); + + HAL_PSSI_ENABLE(hpssi); + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup PSSI_Private_Functions + * @{ + */ + +/** + * @brief PSSI Errors process. + * @param hpssi PSSI handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode) +{ + /* Reset handle parameters */ + hpssi->XferCount = 0U; + + /* Set new error code */ + hpssi->ErrorCode |= ErrorCode; + + /* Disable all interrupts */ + HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort DMA TX transfer if any */ + if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN) + { + if (hpssi->State == HAL_PSSI_STATE_BUSY_TX) + { + hpssi->Instance->CR &= ~PSSI_CR_DMAEN; + + if (hpssi->hdmatx != NULL) + { + /* Set the PSSI DMA Abort callback : + will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */ + hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx); + } + } + } + /* Abort DMA RX transfer if any */ + else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX) + { + hpssi->Instance->CR &= ~PSSI_CR_DMAEN; + + if (hpssi->hdmarx != NULL) + { + /* Set the PSSI DMA Abort callback : + will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */ + hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK) + { + /* Call Directly hpssi->hdma->XferAbortCallback function in case of error */ + hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx); + } + } + } + else + { + /*Nothing to do*/ + } + } +#endif /*HAL_DMA_MODULE_ENABLED*/ + + /* If state is an abort treatment on going, don't change state */ + if (hpssi->State == HAL_PSSI_STATE_ABORT) + { + hpssi->State = HAL_PSSI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) + hpssi->AbortCpltCallback(hpssi); +#else + HAL_PSSI_AbortCpltCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + } + else + { + /* Set HAL_PSSI_STATE_READY */ + hpssi->State = HAL_PSSI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) + hpssi->ErrorCallback(hpssi); +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA PSSI slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + uint32_t tmperror; + + /* Disable Interrupts */ + HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); + + /* Store current volatile hpssi->ErrorCode, misra rule */ + tmperror = hpssi->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + PSSI_Error(hpssi, hpssi->ErrorCode); + } + /* hpssi->State == HAL_PSSI_STATE_BUSY_TX */ + else + { + hpssi->State = HAL_PSSI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) + hpssi->TxCpltCallback(hpssi); +#else + HAL_PSSI_TxCpltCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA PSSI master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + uint32_t tmperror; + + /* Disable Interrupts */ + HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); + + /* Store current volatile hpssi->ErrorCode, misra rule */ + tmperror = hpssi->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + PSSI_Error(hpssi, hpssi->ErrorCode); + } + /* hpssi->State == HAL_PSSI_STATE_BUSY_RX */ + else + { + hpssi->State = HAL_PSSI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) + hpssi->RxCpltCallback(hpssi); +#else + HAL_PSSI_RxCpltCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA PSSI communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +void PSSI_DMAAbort(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Reset AbortCpltCallback */ + hpssi->hdmatx->XferAbortCallback = NULL; + hpssi->hdmarx->XferAbortCallback = NULL; + + /* Check if come from abort from user */ + if (hpssi->State == HAL_PSSI_STATE_ABORT) + { + hpssi->State = HAL_PSSI_STATE_READY; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) + hpssi->AbortCpltCallback(hpssi); +#else + HAL_PSSI_AbortCpltCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) + hpssi->ErrorCallback(hpssi); +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + } +} +#endif /*HAL_DMA_MODULE_ENABLED*/ + +/** + * @brief This function handles PSSI Communication Timeout. + * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains + * the configuration information for the specified PSSI. + * @param Flag Specifies the PSSI flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + while ((HAL_PSSI_GET_STATUS(hpssi, Flag) & Flag) == (uint32_t)Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hpssi->ErrorCode |= HAL_PSSI_ERROR_TIMEOUT; + hpssi->State = HAL_PSSI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +void PSSI_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + uint32_t tmperror; + + /* Disable the selected PSSI peripheral */ + HAL_PSSI_DISABLE(hpssi); + + /* Disable Interrupts */ + HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS); + + /* Store current volatile hpssi->ErrorCode, misra rule */ + tmperror = hpssi->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + PSSI_Error(hpssi, hpssi->ErrorCode); + } + else + { + hpssi->State = HAL_PSSI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hpssi); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1) + hpssi->ErrorCallback(hpssi); +#else + HAL_PSSI_ErrorCallback(hpssi); +#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */ + } +} +#endif /*HAL_DMA_MODULE_ENABLED*/ + + +/** + * @} + */ +#endif /* PSSI */ +#endif /* HAL_PSSI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pwr.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pwr.c new file mode 100644 index 00000000000..251bacf7539 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pwr.c @@ -0,0 +1,692 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/De-Initialization Functions. + * + Peripheral Control Functions. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### PWR peripheral overview ##### + ============================================================================== + [..] + (#) The Power control (PWR) provides an overview of the supply architecture + for the different power domains and of the supply configuration + controller. + + (#) Several low-power modes are available to save power when the CPU does not need to + execute code : + (+) Sleep (CPU clock stopped and still in RUN mode) + (+) Stop (System clock stopped) + (+) Standby (System powered down) + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions + to enable/disable access to the backup domain (RCC Backup domain control + register RCC_BDCR, RTC registers, TAMP registers, backup registers and + backup SRAM). + + (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event + mode and voltage threshold) in order to set up the Programmed Voltage + Detector, then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD() + functions to start and stop the PVD detection. + (+) PVD level can be one of the following values : + (++) 2V0 + (++) 2V2 + (++) 2V4 + (++) 2V5 + (++) 2V6 + (++) 2V8 + (++) 2V9 + (++) External input analog voltage PVD_IN (compared internally to + VREFINT) + + (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions + with the right parameter to configure the wake up pin polarity (Low or + High), the wake up pin selection and to enable and disable it. + + (#) Call HAL_PWR_EnterSLEEPMode() function to enter the CPU in Sleep mode. + Wake-up from Sleep mode could be following to an event or an + interrupt according to low power mode intrinsic request called (__WFI() + or __WFE()). + + (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop + mode. Wake-up from Stop mode could be following to an event or an + interrupt according to low power mode intrinsic request called (__WFI() + or __WFE()). + + (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in + Standby mode. Wake-up from Standby mode can be following only by an + interrupt. + + (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to + enable and disable the Cortex-M7 re-entry in Sleep mode after an + interruption handling is over. + + (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions + to configure the Cortex-M7 to wake-up after any pending event / interrupt + even if it's disabled or has insufficient priority to cause exception + entry. + + *** PWR HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in PWR HAL driver. + + (+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags. + (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags. + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PWR_Private_Defines PWR Private Defines + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_MODE_IT (0x00010000U) +#define PVD_MODE_EVT (0x00020000U) +#define PVD_RISING_EDGE (0x00000001U) +#define PVD_FALLING_EDGE (0x00000002U) +#define PVD_RISING_FALLING_EDGE (0x00000003U) +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and de-Initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and De-Initialization Functions ##### + =============================================================================== + [..] + This section provides functions allowing to deinitialize power peripheral. + + [..] + After system reset, the backup domain (RCC Backup domain control register + RCC_BDCR, RTC registers, TAMP registers, backup registers and backup SRAM) + is protected against possible unwanted write accesses. + The HAL_PWR_EnableBkUpAccess() function enables the access to the backup + domain. + The HAL_PWR_DisableBkUpAccess() function disables the access to the backup + domain. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the HAL PWR peripheral registers to their default reset + * values. + * @note This functionality is not available in this product. + * The prototype is kept just to maintain compatibility with other + * products. + * @retval None. + */ +void HAL_PWR_DeInit(void) +{ +} + +/** + * @brief Enable access to the backup domain (RCC Backup domain control + * register RCC_BDCR, RTC registers, TAMP registers, backup registers + * and backup SRAM). + * @note After a system reset, the backup domain is protected against + * possible unwanted write accesses. + * @retval None. + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disable access to the backup domain (RCC Backup domain control + * register RCC_BDCR, RTC registers, TAMP registers, backup registers + * and backup SRAM). + * @retval None. + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); +} +/** + * @} + */ + + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions + * @brief Power Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control Functions ##### + =============================================================================== + [..] + This section provides functions allowing to control power peripheral. + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR1 + register). + + (+) A PVDO flag is available to indicate if VDD is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line 16 to generate an interrupt if enabled. + It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + + (+) The PVD is stopped in STANDBY mode. + + *** Wake-up pin configuration *** + ================================= + [..] + (+) Wake-up pin is used to wake up the system from STANDBY mode. + The pin pull is configurable through the WKUPEPR register to be in + No-pull, Pull-up and Pull-down. + The pin polarity is configurable through the WKUPEPR register to be + active on rising or falling edges. + + (+) There are up to four Wake-up pin in the STM32H7RS devices family. + + *** Low Power modes configuration *** + ===================================== + [..] + The device present 3 principles low-power modes : + (+) SLEEP mode : Cortex-M7 is stopped and all PWR domains are remaining + active (Powered and Clocked). + + (+) STOP mode : Cortex-M7 is stopped, clocks are stopped and the + regulator is running. The Main regulator or the LP + regulator could be selected. + + (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE + supply regulator is powered off. + + *** SLEEP mode *** + ================== + [..] + (+) Entry: + The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, + SLEEPEntry) function. + + (++) PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction. + (++) PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and + clear of pending events before. + (++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE instruction and + no clear of pending event before. + -@@- The Regulator parameter is not used for the STM32H7RS family + and is kept as parameter just to maintain compatibility with the + lower power families. (STM32L). + + (+) Exit: + Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from SLEEP mode. + + *** STOP mode *** + ================= + [..] + In system STOP mode, the CPU clock is stopped. All CPU subsystem peripheral + clocks are stopped too. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption in STOP mode, FLASH can be powered off before + entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function. + It can be switched on again by software after exiting the STOP mode using + the HAL_PWREx_DisableFlashPowerDown() function. + (+) Entry: + The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, + STOPEntry) function with: + (++) Regulator: + (+++) PWR_MAINREGULATOR_ON: Main regulator ON. + This parameter is not used for the STM32H7RS family and is kept as parameter + just to maintain compatibility with the lower power families. + (++) STOPEntry: + (+++) PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + (+++) PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and + clear of pending events before. + (+++) PWR_STOPENTRY_WFE_NO_EVT_CLEAR: Enter STOP mode with WFE instruction and + no clear of pending event before. + (+) Exit: + Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + *** STANDBY mode *** + ==================== + [..] + (+) + The system STANDBY mode allows to achieve the lowest power consumption. + It is based on the Cortex-M7 deep SLEEP mode, with the voltage regulator + disabled. The system is consequently powered off. The PLL, the HSI + oscillator and the HSE oscillator are also switched off. SRAM and register + contents are lost except for the RTC registers, RTC backup registers, + backup SRAM and standby circuitry. + + [..] + The voltage regulator is OFF. + + (++) Entry: + (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode() + function. + + (++) Exit: + (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), + RTC wakeup, tamper event, time stamp event, external reset in NRST + pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an + RTC Wakeup event, a tamper event or a time-stamp event, without + depending on an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes + + (++) To wake up from the STOP mode with an RTC alarm event, it is + necessary to configure the RTC to generate the RTC alarm using the + HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the STOP mode with an RTC Tamper or time stamp event, + it is necessary to configure the RTC to detect the tamper or time + stamp event using the HAL_RTCEx_SetTimeStamp_IT() or + HAL_RTCEx_SetTamper_IT() functions. + + (++) To wake up from the STOP mode with an RTC WakeUp event, it is + necessary to configure the RTC to generate the RTC WakeUp event + using the HAL_RTCEx_SetWakeUpTimer_IT() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the voltage threshold detected by the Programmed Voltage + * Detector (PVD). + * @param sConfigPVD : Pointer to a PWR_PVDTypeDef structure that contains the + * PVD configuration information (PVDLevel and EventMode). + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @note As PVD and AVD share the same EXTI line, the EXTI operating mode to + * configure will replace a possible previous configuration done through + * HAL_PWREx_ConfigAVD. + * @retval None. + */ +void HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the PVD configuration parameter */ + if (sConfigPVD == NULL) + { + return; + } + + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the PVD in interrupt mode */ + if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure the PVD in event mode */ + if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Rising edge configuration */ + if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + /* Falling edge configuration */ + if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enable the programmable voltage detector (PVD). + * @retval None. + */ +void HAL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_PVDE); +} + +/** + * @brief Disable the programmable voltage detector (PVD). + * @retval None. + */ +void HAL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE); +} + +/** + * @brief Enable the WakeUp PINx functionality. + * @param WakeUpPinPolarity : Specifies which Wake-Up pin to enable. + * This parameter can be one of the following legacy values, which + * sets the default (rising edge): + * @arg PWR_WAKEUP_PIN1, + * PWR_WAKEUP_PIN2, + * PWR_WAKEUP_PIN3, + * PWR_WAKEUP_PIN4. + * or one of the following values where the user can explicitly states + * the enabled pin and the chosen polarity: + * @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW. + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @retval None. + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + + /* + Enable and Specify the Wake-Up pin polarity and the pull configuration + for the event detection (rising or falling edge). + */ + MODIFY_REG(PWR->WKUPEPR, PWR_WKUPEPR_WKUPEN | PWR_WKUPEPR_WKUPP, WakeUpPinPolarity); +} + +/** + * @brief Disable the WakeUp PINx functionality. + * @param WakeUpPinx : Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1, + * PWR_WAKEUP_PIN2, + * PWR_WAKEUP_PIN3, + * PWR_WAKEUP_PIN4, + * PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW. + * @retval None. + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + /* Disable the wake up pin selected */ + CLEAR_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx)); +} + +/** + * @brief Enter the current core in SLEEP mode (CSLEEP). + * @param Regulator : NA in this family project + * Specifies the regulator state in SLEEP mode. + * @note This parameter is not used for the STM32H7RS family and is kept as + * parameter just to maintain compatibility with the lower power + * families. + * @param SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction. + * @arg PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and + * clear of pending events before. + * @arg PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR : Enter SLEEP mode with WFE instruction and + * no clear of pending event before. + * @retval None. + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Regulator); + + /* Check the parameters */ + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Select Sleep mode entry */ + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + if (SLEEPEntry != PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + + /* Request Wait For Event */ + __WFE(); + } +} + +/** + * @brief Enter the whole system to Stop mode. + * @note This API will enter the system in STOP mode + * @param Regulator : This parameter is not used for this product family. + and is kept as parameter just to maintain compatibility with the + lower power families. + * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and + * clear of pending events before. + * @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and + * no clear of pending event before. + * @note In System STOP mode, all I/O pins keep the same state as in Run mode. + * @note When exiting System STOP mode by issuing an interrupt or a wakeup + * event, the HSI RC oscillator is selected as default system wakeup + * clock. + * @note In System STOP mode, when the voltage regulator operates in low + * power mode, an additional startup delay is incurred when the system + * is waking up. By keeping the internal regulator ON during STOP mode, + * the consumption is higher although the startup time is reduced. + * @retval None. + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Regulator); + + /* Check the parameters */ + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select Stop mode when device enters Deepsleep */ + CLEAR_BIT(PWR->CSR3, PWR_CSR3_PDDS); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB(); + __ISB(); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + if (STOPEntry != PWR_STOPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + /* Request Wait For Event */ + __WFE(); + } + + /* Clear SLEEPDEEP bit of Cortex-M7 in the System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enter the whole system to Standby mode. + * @note The Standby mode allows achieving the lowest power consumption. + * @note When the system enters in Standby mode, the voltage regulator is disabled. + * The complete VCORE domain is consequently powered off. + * The PLLs, HSI oscillator, CSI oscillator, HSI48 and the HSE oscillator are + * also switched off. + * SRAM and register contents are lost except for backup domain registers + * (RTC registers, RTC backup register and backup RAM), and Standby circuitry. + * @note When the System exit STANDBY mode by issuing an interrupt or a + * wakeup event, the HSI RC oscillator is selected as system clock. + * @retval None. + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select Standby when device enters Deepsleep */ + SET_BIT(PWR->CSR3, PWR_CSR3_PDDS); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STANDBY mode */ + __DSB(); + __ISB(); + + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Indicate SLEEP-ON-EXIT feature when returning from handler mode to + * thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters Sleep mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run + * only on interruptions handling. + * @retval None. + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex-M7 System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Disable SLEEP-ON-EXIT feature when returning from handler mode to + * thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters Sleep mode when an interruption handling is over. + * @retval None. + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex-M7 System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enable CORTEX SEV-ON-PEND feature. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, any + * pending event / interrupt even if it's disabled or has insufficient + * priority to cause exception entry wakes up the Cortex-M7. + * @retval None. + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex-M7 System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Disable CORTEX SEVONPEND feature. + * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only + * enabled pending causes exception entry wakes up the Cortex-M7. + * @retval None. + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex-M7 System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} +/** + * @} + */ + +/** + * @} + */ +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pwr_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pwr_ex.c new file mode 100644 index 00000000000..0036f4a07e2 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pwr_ex.c @@ -0,0 +1,1601 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of PWR extension peripheral: + * + Peripheral Extended features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply + with the following different setups according to hardware (support SMPS): + (+) PWR_DIRECT_SMPS_SUPPLY + (+) PWR_SMPS_1V8_SUPPLIES_LDO + (+) PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + (+) PWR_SMPS_1V8_SUPPLIES_EXT + (+) PWR_LDO_SUPPLY + (+) PWR_EXTERNAL_SOURCE_SUPPLY + + (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup. + + (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main + internal regulator output voltage. The voltage scaling could be one of + the following scales : + (+) PWR_REGULATOR_VOLTAGE_SCALE0 + (+) PWR_REGULATOR_VOLTAGE_SCALE1 + + (#) Call HAL_PWREx_GetVoltageRange() function to get the current output + voltage applied to the main regulator. + + (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the main + internal regulator output voltage in STOP mode. The voltage scaling could be one of + the following scales : + (+) PWR_REGULATOR_STOP_VOLTAGE_SCALE3 + (+) PWR_REGULATOR_STOP_VOLTAGE_SCALE5 + + (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current output + voltage applied to the main regulator in STOP mode. + + (#) Call HAL_PWREx_EnableFlashPowerDown() and + HAL_PWREx_DisableFlashPowerDown() functions to enable and disable the + Flash Power Down in STOP mode. + + (#) Call HAL_PWREx_EnableWakeUpPin() and HAL_PWREx_DisableWakeUpPin() + functions to enable and disable the Wake-up pin functionality for + the selected pin. + + (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag() + functions to manage wake-up flag for the selected pin. + + (#) Call HAL_PWREx_WAKEUP_PIN_IRQHandler() function to handle all wake-up + pins interrupts. + + (#) Call HAL_PWREx_EnableBkUpReg() and HAL_PWREx_DisableBkUpReg() functions + to enable and disable the backup domain regulator. + + (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(), + HAL_PWREx_EnableUSBVoltageDetector() and + HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power + regulation functionalities. + + (#) Call HAL_PWREx_EnableUCPDStandbyMode() and HAL_PWREx_DisableUCPDStandbyMode() functions + to enable and disable UCPD Standby mode. + + (#) Call HAL_PWREx_EnableUCPDDeadBattery() and HAL_PWREx_DisableUCPDDeadBattery() functions + to enable and disable UCPD dead battery. + + (#) Call HAL_PWREx_EnableBatteryCharging() and + HAL_PWREx_DisableBatteryCharging() functions to enable and disable the + battery charging feature with the selected resistor. + + (#) Call HAL_PWREx_EnableAnalogBooster() and HAL_PWREx_DisableAnalogBooster() functions + to enable and disable the AVD boost feature when the VDD supply voltage is below 2V7. + + (#) Call HAL_PWREx_EnableXSPIM1() and HAL_PWREx_DisableXSPIM1() functions + to enable and disable the XSPIM1. + + (#) Call HAL_PWREx_EnableXSPIM2() and HAL_PWREx_DisableXSPIM2() functions + to enable and disable the XSPIM2. + + (#) Call HAL_PWREx_ConfigXSPIPortCap() functions to configure the XSPI capacitor port 1 and 2. + The capacitor setting could be one of the following values : + (+) PWR_CAPACITOR_OFF + (+) PWR_CAPACITOR_ONE_THIRD_CAPACITANCE + (+) PWR_CAPACITOR_TWO_THIRD_CAPACITANCE + (+) PWR_CAPACITOR_FULL_CAPACITANCE + + (#) Call HAL_PWREx_GetConfigXSPIPortCap() function to get the current + capacitor port setting. + + (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() + functions to enable and disable the VBAT and Temperature monitoring. + When VBAT and Temperature monitoring feature is enables, use + HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get + respectively the Temperature level and VBAT level. + + (#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured + (event mode and voltage threshold) in order to set up the Analog Voltage + Detector then use HAL_PWREx_EnableAVD() and HAL_PWREx_DisableAVD() + functions to start and stop the AVD detection. + (+) AVD level could be one of the following values : + (++) 1V7 + (++) 2V1 + (++) 2V5 + (++) 2V8 + + (#) Call HAL_PWREx_PVD_AVD_IRQHandler() function to handle the PWR PVD and + AVD interrupt request. + + (#) Call HAL_PWREx_EnablePullUpPullDownConfig() and + HAL_PWREx_DisablePullUpPullDownConfig() to I/O enable / disable pull-up + and pull-down configuration. + + (#) Call HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() to + apply respectively pull-up and pull-down to selected I/O. + Call HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() to + disable applied respectively pull-up and pull-down to selected I/O. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR Extended HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @addtogroup PWREx_Private_Constants + * @{ + */ + +/** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask + * @{ + */ +#define AVD_MODE_IT (0x00010000U) +#define AVD_MODE_EVT (0x00020000U) +#define AVD_RISING_EDGE (0x00000001U) +#define AVD_FALLING_EDGE (0x00000002U) +#define AVD_RISING_FALLING_EDGE (0x00000003U) +/** + * @} + */ + +/** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value + * @{ + */ +#define PWR_FLAG_SETTING_DELAY (1000U) +/** + * @} + */ + +/** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets + * @{ + */ +/* Wake-Up Pins EXTI register mask */ +#define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\ + EXTI_IMR2_IM57 | EXTI_IMR2_IM58 ) + +/* Wake-Up Pins PWR Pin Pull shift offsets */ +#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U) +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + * @brief Power supply control functions + * +@verbatim + =============================================================================== + ##### Power supply control functions ##### + =============================================================================== + [..] + (#) When the system is powered on, the POR monitors VDD supply. Once VDD is + above the POR threshold level, the SMPS step-down converter and voltage + regulator are enabled in the default supply configuration: + + (+) The SMPS step-down converter output level is set at 1.35 V. + The voltage regulator LDO output level is set at 1.11 V. + Depending on the package and configuration the SMPS provides the + voltage to internal power domain and/or LDO or external supply. + + (+) The system is kept in reset mode as long as VCORE is not stable. + + (+) Once VCORE is stable, the system is taken out of reset and the HSI + oscillator is enabled. + + (+) Once the oscillator is stable, the system is initialized: Flash memory + is ready, option bytes are loaded and the CPU starts in limited run mode. + + (+) The software must then initialize the system including supply + configuration programming in PWR control register 2 (PWR_CSR2). + Once the supply configuration has been configured, the ACTVOSRDY bit in + the PWR control status register 1 (PWR_SR1) must be checked to guarantee + valid voltage levels: + a) As long as ACTVOSRDY indicates that voltage levels are invalid, the + system is in Run mode, write accesses to the RAMs are not permitted and + VOS must not be changed. + b) Once ACTVOSRDY indicates that voltage levels are valid, the system is + in normal Run mode, write accesses to RAMs are allowed and VOS can be + changed. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the system Power Supply. + * @param SupplySource : Specifies the Power Supply source to set after a + * system startup. + * This parameter can be one of the following values : + * @arg PWR_DIRECT_SMPS_SUPPLY : The SMPS supplies the Vcore Power + * Domains. The LDO is Bypassed. + * @arg PWR_SMPS_1V8_SUPPLIES_LDO : The SMPS 1.8V output supplies + * the LDO. The Vcore Power Domains + * are supplied from the LDO. + * @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : The SMPS 1.8V output + * supplies external + * circuits and the LDO. + * The Vcore Power Domains + * are supplied from the + * LDO. + * @arg PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies + * external circuits. The LDO is + * Bypassed. The Vcore Power + * Domains are supplied from + * external source. + * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power + * Domains. The SMPS regulator is Bypassed. + * @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS is disabled and the LDO are + * Bypassed. The Vcore Power + * Domains are supplied from + * external source. + * @note The SMPS step-down converter is not available on all packages, + * and the Bypass mode is available only when the SMPS is available. + * @note The PWR_DIRECT_SMPS_SUPPLY, PWR_SMPS_1V8_SUPPLIES_LDO, + * PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO and PWR_SMPS_1V8_SUPPLIES_EXT are used + * only for lines that supports SMPS regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_PWR_SUPPLY(SupplySource)); + + /* Check if supply source was configured */ + if ((PWR->CSR2 & (PWR_CSR2_SDEN | PWR_CSR2_LDOEN | PWR_CSR2_BYPASS)) != (PWR_CSR2_SDEN | PWR_CSR2_LDOEN)) + { + /* Check supply configuration */ + if ((PWR->CSR2 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) + { + /* Supply configuration update locked, can't apply a new supply config */ + return HAL_ERROR; + } + else + { + /* Supply configuration update locked, but new supply configuration + matches with old supply configuration : nothing to do + */ + return HAL_OK; + } + } + + /* Set the power supply configuration */ + MODIFY_REG(PWR->CSR2, PWR_SUPPLY_CONFIG_MASK, SupplySource); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till voltage level flag is set */ + while ((PWR->SR1 & PWR_SR1_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */ + if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || + (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT)) + { + /* Get the current tick number */ + tickstart = HAL_GetTick(); + + /* Wait till SMPS external supply ready flag is set */ + while ((PWR->CSR2 & PWR_CSR2_SDEXTRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief Get the power supply configuration. + * @retval The supply configuration. + */ +uint32_t HAL_PWREx_GetSupplyConfig(void) +{ + return (PWR->CSR2 & PWR_SUPPLY_CONFIG_MASK); +} + +/** + * @brief Configure the main internal regulator output voltage. + * @param VoltageScaling : Specifies the regulator output voltage to achieve + * a tradeoff between performance and power + * consumption. + * This parameter can be one of the following values : + * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage scaling range 0 (highest frequency). + * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage scaling range 1 (lowest power). + * @note When increasing the performance, the voltage scaling must be changed + * before increasing the system frequency. + * When decreasing performance, the system frequency must first be decreased + * before changing the voltage scaling. + * @note When exiting from Stop mode or Standby mode, the Run mode voltage + * scaling is reset to the default VOS low value. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling)); + + /* Set the voltage range */ + MODIFY_REG(PWR->CSR4, PWR_CSR4_VOS, VoltageScaling); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till voltage level flag is set */ + while ((PWR->CSR4 & PWR_CSR4_VOSRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Get the main internal regulator output voltage. Reflecting the last + * VOS value applied to the PMU. + * @retval The current applied VOS selection. + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + /* Get the active voltage scaling */ + return (PWR->SR1 & PWR_SR1_ACTVOS); +} + +/** + * @brief Configure the main internal regulator output voltage in STOP mode. + * @param VoltageScaling : Specifies the regulator output voltage when the + * system enters Stop mode to achieve a tradeoff between performance + * and power consumption. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_STOP_VOLTAGE_SCALE3 : System Stop mode voltage scaling range 3 (highest frequency). + * @arg PWR_REGULATOR_STOP_VOLTAGE_SCALE5 : System Stop mode voltage scaling range 5 (lowest power). + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling) +{ + /* Check the parameters */ + assert_param(IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VoltageScaling)); + + /* Return the stop mode voltage range */ + MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling); + + return HAL_OK; +} + +/** + * @brief Get the main internal regulator output voltage in STOP mode. + * @retval The actual applied SVOS selection. + */ +uint32_t HAL_PWREx_GetStopModeVoltageRange(void) +{ + /* Return the stop voltage scaling */ + return (PWR->CR1 & PWR_CR1_SVOS); +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions + * @brief Low Power Control Functions + * +@verbatim + =============================================================================== + ##### Low Power Control Functions ##### + =============================================================================== + + *** FLASH Power Down configuration **** + ======================================= + [..] + By setting the FLPS bit in the PWR_CR1 register using the + HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters + power down mode when the device enters STOP mode. When the Flash memory is + in power down mode, an additional startup delay is incurred when waking up + from STOP mode. + + *** Wakeup Pins configuration **** + =================================== + [..] + Wakeup pins allow the system to exit from Standby mode. The configuration + of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams) + function with: + (+) sPinParams: structure to enable and configure a wakeup pin: + (++) WakeUpPin: Wakeup pin to be enabled. + (++) PinPolarity: Wakeup pin polarity (rising or falling edge). + (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down). + [..] + The wakeup pins are internally connected to the EXTI lines [55-58] to + generate an interrupt if enabled. The EXTI lines configuration is done by + the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7rsxxhal.c + file. + [..] + When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is + called and the appropriate flag is set in the PWR_WKUPFR register. Then in + the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be + cleared and the appropriate user callback will be called. The user can add + his own code by customization of function pointer HAL_PWREx_WKUPx_Callback. + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Flash Power Down in Stop mode. + * @note When Flash Power Down is enabled the Flash memory enters low-power + * mode when device is in Stop mode. This feature allows to + * obtain the best trade-off between low-power consumption and restart + * time when exiting from Stop mode. + * @retval None. + */ +void HAL_PWREx_EnableFlashPowerDown(void) +{ + /* Enable the Flash Power Down */ + SET_BIT(PWR->CR1, PWR_CR1_FLPS); +} + +/** + * @brief Disable the Flash Power Down in Stop mode. + * @note When Flash Power Down is disabled the Flash memory is kept on + * normal mode when device is in Stop mode. This feature allows + * to obtain the best trade-off between low-power consumption and + * restart time when exiting from Stop mode. + * @retval None. + */ +void HAL_PWREx_DisableFlashPowerDown(void) +{ + /* Disable the Flash Power Down */ + CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS); +} + +/** + * @brief Enable the Wake-up PINx functionality. + * @param sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that + * contains the configuration information for the wake-up + * Pin. + * @retval None. + */ +void HAL_PWREx_EnableWakeUpPin(const PWREx_WakeupPinTypeDef *sPinParams) +{ + uint32_t pinConfig; + uint32_t regMask; + const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1; + + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(sPinParams->WakeUpPin)); + assert_param(IS_PWR_WAKEUP_PIN_POLARITY(sPinParams->PinPolarity)); + assert_param(IS_PWR_WAKEUP_PIN_PULL(sPinParams->PinPull)); + + pinConfig = sPinParams->WakeUpPin | \ + (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP1_Pos) & 0x1FU)) | \ + (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) + PWR_WKUPEPR_WKUPPUPD1_Pos) & 0x1FU)); + + regMask = sPinParams->WakeUpPin | \ + (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \ + (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU)); + + /* Enable and Specify the Wake-Up pin polarity and the pull configuration + for the event detection (rising or falling edge) */ + MODIFY_REG(PWR->WKUPEPR, regMask, pinConfig); + + /* Configure the Wakeup Pin EXTI Line */ + MODIFY_REG(EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos)); +} + +/** + * @brief Disable the Wake-up PINx functionality. + * @param WakeUpPin : Specifies the Wake-Up pin to be disabled. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 : Disable PA0 wake-up PIN. + * @arg PWR_WAKEUP_PIN2 : Disable PA2 wake-up PIN. + * @arg PWR_WAKEUP_PIN3 : Disable PC13 wake-up PIN. + * @arg PWR_WAKEUP_PIN4 : Disable PC1 wake-up PIN. + * @retval None + */ +void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin)); + + /* Disable the WakeUpPin */ + CLEAR_BIT(PWR->WKUPEPR, WakeUpPin); +} + +/** + * @brief Get the Wake-Up Pin pending flags. + * @param WakeUpFlag : Specifies the Wake-Up PIN flag to be checked. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_FLAG1 : Get wakeup event received from PA0. + * @arg PWR_WAKEUP_FLAG2 : Get wakeup event received from PA2. + * @arg PWR_WAKEUP_FLAG3 : Get wakeup event received from PC13. + * @arg PWR_WAKEUP_FLAG4 : Get wakeup event received from PC1. + * @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all + * wake up pins. + * @retval The Wake-Up pin flag. + */ +uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_FLAG(WakeUpFlag)); + + /* Return the wake up pin flag */ + return (PWR->WKUPFR & WakeUpFlag); +} + +/** + * @brief Clear the Wake-Up pin pending flag. + * @param WakeUpFlag: Specifies the Wake-Up PIN flag to clear. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0. + * @arg PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2. + * @arg PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PC13. + * @arg PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC1. + * @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from all + * wake up pins. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_FLAG(WakeUpFlag)); + + /* Clear the wake up event received from wake up pin x */ + WRITE_REG(PWR->WKUPCR, WakeUpFlag); + + /* Check if the wake up event is well cleared */ + if ((PWR->WKUPFR & WakeUpFlag) != 0U) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief This function handles the PWR WAKEUP PIN interrupt request. + * @note This API should be called under the WAKEUP_PIN_IRQHandler(). + * @retval None. + */ +void HAL_PWREx_WAKEUP_PIN_IRQHandler(void) +{ + /* Wakeup pin EXTI line interrupt detected */ + if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U) + { + /* Clear PWR WKUPF1 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG(PWR_FLAG_WKUP1); + + /* PWR WKUP1 interrupt user callback */ + HAL_PWREx_WKUP1_Callback(); + } + + if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U) + { + /* Clear PWR WKUPF2 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG(PWR_FLAG_WKUP2); + + /* PWR WKUP2 interrupt user callback */ + HAL_PWREx_WKUP2_Callback(); + } + + if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U) + { + /* Clear PWR WKUPF3 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG(PWR_FLAG_WKUP3); + + /* PWR WKUP3 interrupt user callback */ + HAL_PWREx_WKUP3_Callback(); + } + + if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U) + { + /* Clear PWR WKUPF4 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG(PWR_FLAG_WKUP4); + + /* PWR WKUP4 interrupt user callback */ + HAL_PWREx_WKUP4_Callback(); + } +} + +/** + * @brief PWR WKUP1 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP1_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP1Callback can be implemented in the user file + */ +} + +/** + * @brief PWR WKUP2 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP2_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP2Callback can be implemented in the user file + */ +} + +/** + * @brief PWR WKUP3 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP3_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP3Callback can be implemented in the user file + */ +} + +/** + * @brief PWR WKUP4 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP4_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP4Callback can be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group3 Peripherals Control Functions + * @brief Peripherals Control Functions + * +@verbatim + =============================================================================== + ##### Peripherals Control Functions ##### + =============================================================================== + + *** Main and Backup Regulators configuration *** + ================================================ + [..] + (+) The backup domain includes 4 Kbytes of backup SRAM accessible only + from the CPU, and addressed in 32-bit, 16-bit or 8-bit mode. Its + content is retained even in Standby or VBAT mode when the low power + backup regulator is enabled. It can be considered as an internal + EEPROM when VBAT is always present. You can use the + HAL_PWREx_EnableBkUpReg() function to enable the low power backup + regulator. + (+) When the backup domain is supplied by VDD (analog switch connected to + VDD) the backup SRAM is powered from VDD which replaces the VBAT power + supply to save battery life. + (+) The backup SRAM is not mass erased by a tamper event. It is read + protected to prevent confidential data, such as cryptographic private + key, from being accessed. The backup SRAM can be erased only through + the Flash interface when a protection level change from level 1 to + level 0 is requested. + -@- Refer to the description of Read protection (RDP) in the Flash + programming manual. + (+) The main internal regulator can be configured to have a tradeoff + between performance and power consumption when the device does not + operate at the maximum frequency. This is done through + HAL_PWREx_ControlVoltageScaling(VOS) function which configure the VOS + bit in PWR_CSR4 register. + (+) The main internal regulator can be configured to operate in Low Power + mode when the system enters STOP mode to further reduce power + consumption. + This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS) + function which configure the SVOS bit in PWR_CR1 register. + -@- Refer to the product datasheets for more details. + + *** USB Regulator configuration *** + =================================== + [..] + (+) The USB transceivers are supplied from a dedicated VDD33USB supply + that can be provided either by the integrated USB regulator, or by an + external USB supply. + (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the + VDD33USB is then provided from the USB regulator. + (+) When the USB regulator is enabled, the VDD33USB supply level detector + shall be enabled through HAL_PWREx_EnableUSBVoltageDetector() + function. + (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg() + function and VDD33USB can be provided from an external supply. In this + case VDD33USB and VDD50USB shall be connected together. + + *** VBAT battery charging *** + ============================= + [..] + (+) When VDD is present, the external battery connected to VBAT can be + charged through an internal resistance. VBAT charging can be performed + either through a 5 KOhm resistor or through a 1.5 KOhm resistor. + (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging + (ResistorValue) function with: + (++) ResistorValue: + (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor. + (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor. + (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging() + function. + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Backup Regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) +{ + uint32_t tickstart; + + /* Enable the Backup regulator */ + SET_BIT(PWR->CSR1, PWR_CSR1_BREN); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till Backup regulator ready flag is set */ + while ((PWR->CSR1 & PWR_CSR1_BRRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the Backup Regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) +{ + uint32_t tickstart; + + /* Disable the Backup regulator */ + CLEAR_BIT(PWR->CSR1, PWR_CSR1_BREN); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till Backup regulator ready flag is reset */ + while ((PWR->CSR1 & PWR_CSR1_BRRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Enable the USB Regulator. + * @retval None. + */ +void HAL_PWREx_EnableUSBReg(void) +{ + /* Enable the USB regulator */ + SET_BIT(PWR->CSR2, PWR_CSR2_USBREGEN); +} + +/** + * @brief Disable the USB Regulator. + * @retval None. + */ +void HAL_PWREx_DisableUSBReg(void) +{ + /* Disable the USB regulator */ + CLEAR_BIT(PWR->CSR2, PWR_CSR2_USBREGEN); +} + +/** + * @brief Enable the USB voltage level detector. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_EnableUSBVoltageDetector(void) +{ + uint32_t tickstart; + + /* Enable the USB voltage detector */ + SET_BIT(PWR->CSR2, PWR_CSR2_USB33DEN); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till the USB regulator ready flag is set */ + while ((PWR->CSR2 & PWR_CSR2_USB33RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief Disable the USB voltage level detector. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_DisableUSBVoltageDetector(void) +{ + uint32_t tickstart; + + /* Disable the USB voltage detector */ + CLEAR_BIT(PWR->CSR2, PWR_CSR2_USB33DEN); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till the USB regulator ready flag is reset */ + while ((PWR->CSR2 & PWR_CSR2_USB33RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Enable the USB HS regulator. + * @retval None. + */ +void HAL_PWREx_EnableUSBHSregulator(void) +{ + /* Enable the USB HS regulator */ + SET_BIT(PWR->CSR2, PWR_CSR2_USBHSREGEN); +} + +/** + * @brief Disable the USB HS regulator. + * @retval None. + */ +void HAL_PWREx_DisableUSBHSregulator(void) +{ + /* Disable the USB HS regulator */ + CLEAR_BIT(PWR->CSR2, PWR_CSR2_USBHSREGEN); +} + +/** + * @brief Enable UCPD configuration memorization in Standby. + * @retval None + * @note This function must be called just before entering Standby mode when using UCPD. + */ +void HAL_PWREx_EnableUCPDStandbyMode(void) +{ + /* Memorize UCPD configuration when entering standby mode */ + SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY); +} + +/** + * @brief Disable UCPD configuration memorization in Standby. + * @note This function must be called on exiting the Standby mode and before any UCPD + * configuration update. + * @retval None + */ +void HAL_PWREx_DisableUCPDStandbyMode(void) +{ + CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY); +} + +/** + * @brief Enable dead battery behavior. + * @retval None + */ +void HAL_PWREx_EnableUCPDDeadBattery(void) +{ + /* Enable dead battery behavior */ + CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); +} + +/** + * @brief Disable dead battery behavior. + * @retval None + */ +void HAL_PWREx_DisableUCPDDeadBattery(void) +{ + /* Disable dead battery behavior */ + SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); +} + +/** + * @brief Enable the Battery charging. + * @note When VDD is present, charge the external battery through an internal + * resistor. + * It is automatically disabled in VBAT mode. + * @param ResistorValue : Specifies the charging resistor. + * This parameter can be one of the following values : + * @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor. + * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor. + * @retval None. + */ +void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue) +{ + /* Check the parameter */ + assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorValue)); + + /* Specify the charging resistor and enable the Battery charging */ + MODIFY_REG(PWR->CSR2, (PWR_CSR2_VBRS | PWR_CSR2_VBE), (ResistorValue | PWR_CSR2_VBE)); + +} + +/** + * @brief Disable the Battery charging. + * @retval None. + */ +void HAL_PWREx_DisableBatteryCharging(void) +{ + /* Disable the Battery charging and restore default charging resistor value */ + CLEAR_BIT(PWR->CSR2, (PWR_CSR2_VBE | PWR_CSR2_VBRS)); +} + +/** + * @brief Enable the booster to guarantee the analog switch AC performance when + * the VDD supply voltage is below 2V7. + * @note The VDD supply voltage can be monitored through the PVD and the PLS + * field bits. + * @retval None. + */ +void HAL_PWREx_EnableAnalogBooster(void) +{ + /* Enable the Analog voltage */ + SET_BIT(PWR->CR1, PWR_CR1_AVDREADY); + + /* Enable VDDA booster */ + SET_BIT(PWR->CR1, PWR_CR1_BOOSTE); +} + +/** + * @brief Disable the analog booster. + * @retval None. + */ +void HAL_PWREx_DisableAnalogBooster(void) +{ + /* Disable VDDA booster */ + CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE); + + /* Disable the Analog voltage */ + CLEAR_BIT(PWR->CR1, PWR_CR1_AVDREADY); +} + +/** + * @brief Enable the XSPIM_P1 interface. + * @note The XSPIM_P1 supply must be stable prior to setting + this bit. + * @retval None. + */ +void HAL_PWREx_EnableXSPIM1(void) +{ + SET_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM1); +} + +/** + * @brief Disable the XSPIM_P1 interface. + * @retval None. + */ +void HAL_PWREx_DisableXSPIM1(void) +{ + CLEAR_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM1); +} + +/** + * @brief Enable the XSPIM_P2 interface. + * @note The XSPIM_P2 supply must be stable prior to setting + this bit. + * @retval None. + */ +void HAL_PWREx_EnableXSPIM2(void) +{ + SET_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM2); +} + +/** + * @brief Disable the XSPIM_P2 interface. + * @retval None. + */ +void HAL_PWREx_DisableXSPIM2(void) +{ + CLEAR_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM2); +} + +/** + * @brief Configure the capacitor port + * @param PortCapacitor Select the Port + * This parameter can be one of the following values: + * @arg @ref PWR_CAPACITOR_PORT1 XSPI port 1 capacitor + * @arg @ref PWR_CAPACITOR_PORT2 XSPI port 2 capacitor + * @param PortCapacitorSetting Select the capacitor setting + * This parameter can be one of the following values: + * @arg @ref PWR_CAPACITOR_OFF XSPI Capacitor OFF + * @arg @ref PWR_CAPACITOR_ONE_THIRD_CAPACITANCE XSPI Capacitor set to 1/3 + * @arg @ref PWR_CAPACITOR_TWO_THIRD_CAPACITANCE XSPI Capacitor set to 2/3 + * @arg @ref PWR_CAPACITOR_FULL_CAPACITANCE XSPI Capacitor set to full capacitance + * @retval None. + */ +void HAL_PWREx_ConfigXSPIPortCap(uint32_t PortCapacitor, uint32_t PortCapacitorSetting) +{ + /* Check the parameters */ + assert_param(IS_PWR_CAPACITOR(PortCapacitor)); + assert_param(IS_PWR_CAPACITOR_SETTING(PortCapacitorSetting)); + + if (PortCapacitor == PWR_CAPACITOR_PORT1) + { + /* Set Port1 Capacitor setting */ + MODIFY_REG(PWR->CSR2, PWR_CSR2_XSPICAP1, PortCapacitorSetting); + } + else + { + /* Set Port2 Capacitor setting */ + MODIFY_REG(PWR->CSR2, PWR_CSR2_XSPICAP2, PortCapacitorSetting << (PWR_CSR2_XSPICAP2_Pos - PWR_CSR2_XSPICAP1_Pos)); + } +} + +/** + * @brief Get the capacitor port setting + * @param PortCapacitor Select the Port + * This parameter can be one of the following values: + * @arg @ref PWR_CAPACITOR_PORT1 XSPI port 1 capacitor + * @arg @ref PWR_CAPACITOR_PORT2 XSPI port 2 capacitor + * @retval The capacitor setting: + * @arg @ref PWR_CAPACITOR_OFF XSPI Capacitor OFF + * @arg @ref PWR_CAPACITOR_ONE_THIRD_CAPACITANCE XSPI Capacitor set to 1/3 + * @arg @ref PWR_CAPACITOR_TWO_THIRD_CAPACITANCE XSPI Capacitor set to 2/3 + * @arg @ref PWR_CAPACITOR_FULL_CAPACITANCE XSPI Capacitor set to full capacitance + */ +uint32_t HAL_PWREx_GetConfigXSPIPortCap(uint32_t PortCapacitor) +{ + uint32_t PortCapacitorSetting; + + /* Check the parameter */ + assert_param(IS_PWR_CAPACITOR(PortCapacitor)); + + if (PortCapacitor == PWR_CAPACITOR_PORT1) + { + /* Get Port1 Capacitor setting */ + PortCapacitorSetting = READ_BIT(PWR->CSR2, PWR_CSR2_XSPICAP1); + } + else + { + /* Get Port2 Capacitor setting */ + PortCapacitorSetting = (READ_BIT(PWR->CSR2, PWR_CSR2_XSPICAP2) >> (PWR_CSR2_XSPICAP2_Pos - PWR_CSR2_XSPICAP1_Pos)); + } + + return PortCapacitorSetting; +} + +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions + * @brief Power Monitoring functions + * +@verbatim + =============================================================================== + ##### Power Monitoring functions ##### + =============================================================================== + + *** VBAT and Temperature supervision *** + ======================================== + [..] + (+) The VBAT battery voltage supply can be monitored by comparing it with + two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags + in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or + lower than the threshold. + (+) The temperature can be monitored by comparing it with two threshold + levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR + control register 2 (PWR_CR2), indicate whether the device temperature + is higher or lower than the threshold. + (+) The VBAT and the temperature monitoring is enabled by + HAL_PWREx_EnableMonitoring() function and disabled by + HAL_PWREx_DisableMonitoring() function. + (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can + be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or + PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD. + (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature + level which can be : + PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or + PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD. + + *** AVD configuration *** + ========================= + [..] + (+) The AVD is used to monitor the VDDA power supply by comparing it to a + threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1 + register). + (+) A AVDO flag is available to indicate if VDDA is higher or lower + than the AVD threshold. This event is internally connected to the EXTI + line 16 to generate an interrupt if enabled. + It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro. + (+) The AVD is stopped in System Standby mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enable the VBAT and temperature monitoring. + * @retval HAL status. + */ +void HAL_PWREx_EnableMonitoring(void) +{ + /* Enable the VBAT and Temperature monitoring */ + SET_BIT(PWR->CSR1, PWR_CSR1_MONEN); +} + +/** + * @brief Disable the VBAT and temperature monitoring. + * @retval HAL status. + */ +void HAL_PWREx_DisableMonitoring(void) +{ + /* Disable the VBAT and Temperature monitoring */ + CLEAR_BIT(PWR->CSR1, PWR_CSR1_MONEN); +} + +/** + * @brief Indicate whether the junction temperature is between, above or below + * the thresholds. + * @retval Temperature level. + */ +uint32_t HAL_PWREx_GetTemperatureLevel(void) +{ + uint32_t tempLevel; + uint32_t regValue; + + /* Read the temperature flags */ + regValue = READ_BIT(PWR->CSR1, (PWR_CSR1_TEMPH | PWR_CSR1_TEMPL)); + + /* Check if the temperature is below the threshold */ + if (regValue == PWR_CSR1_TEMPL) + { + tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD; + } + /* Check if the temperature is above the threshold */ + else if (regValue == PWR_CSR1_TEMPH) + { + tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD; + } + /* The temperature is between the thresholds */ + else + { + tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD; + } + + return tempLevel; +} + +/** + * @brief Indicate whether the Battery voltage level is between, above or below + * the thresholds. + * @retval VBAT level. + */ +uint32_t HAL_PWREx_GetVBATLevel(void) +{ + uint32_t vbatLevel; + uint32_t regValue; + + /* Read the VBAT flags */ + regValue = READ_BIT(PWR->CSR1, (PWR_CSR1_VBATH | PWR_CSR1_VBATL)); + + /* Check if the VBAT is below the threshold */ + if (regValue == PWR_CSR1_VBATL) + { + vbatLevel = PWR_VBAT_BELOW_LOW_THRESHOLD; + } + /* Check if the VBAT is above the threshold */ + else if (regValue == PWR_CSR1_VBATH) + { + vbatLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD; + } + /* The VBAT is between the thresholds */ + else + { + vbatLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD; + } + + return vbatLevel; +} + +/** + * @brief Configure the event mode and the voltage threshold detected by the + * Analog Voltage Detector (AVD). + * @param sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains + * the configuration information for the AVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @note As PVD and AVD share the same EXTI line, the EXTI operating mode to + * configure will replace a possible previous configuration done through + * HAL_PWR_ConfigPVD. + * @retval None. + */ +void HAL_PWREx_ConfigAVD(const PWREx_AVDTypeDef *sConfigAVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_AVD_LEVEL(sConfigAVD->AVDLevel)); + assert_param(IS_PWR_AVD_MODE(sConfigAVD->Mode)); + + /* Set the ALS[18:17] bits according to AVDLevel value */ + MODIFY_REG(PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); + + /* Clear any previous config */ + __HAL_PWR_AVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_AVD_EXTI_DISABLE_IT(); + + __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the interrupt mode */ + if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) + { + __HAL_PWR_AVD_EXTI_ENABLE_IT(); + } + + /* Configure the event mode */ + if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) + { + __HAL_PWR_AVD_EXTI_ENABLE_EVENT(); + } + + /* Rising edge configuration */ + if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) + { + __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); + } + + /* Falling edge configuration */ + if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) + { + __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enable the Analog Voltage Detector (AVD). + * @retval None. + */ +void HAL_PWREx_EnableAVD(void) +{ + /* Enable the Analog Voltage Detector */ + SET_BIT(PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief Disable the Analog Voltage Detector(AVD). + * @retval None. + */ +void HAL_PWREx_DisableAVD(void) +{ + /* Disable the Analog Voltage Detector */ + CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief This function handles the PWR PVD/AVD interrupt request. + * @note This API should be called under the PVD_AVD_IRQHandler(). + * @retval None + */ +void HAL_PWREx_PVD_AVD_IRQHandler(void) +{ + /* Check PWR EXTI flags for PVD/AVD */ + if (((EXTI->PR1) & EXTI_PR1_PR16) != 0U) + { + /* Clear PVD/AVD exti pending bit */ + WRITE_REG(EXTI->PR1, EXTI_PR1_PR16); + + /* PWR PVD/AVD interrupt user callback */ + HAL_PWREx_PVD_AVD_Callback(); + } +} + +/** + * @brief PWR PVD/AVD interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_PVD_AVD_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_PVD_AVD_Callback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions + * @brief I/O pull-up / pull-down configuration functions + * +@verbatim + =============================================================================== + ##### Voltage monitoring Functions ##### + =============================================================================== + [..] + In Standby mode, pull up and pull down can be configured to + maintain an I/O in the selected state. If the APC bit in the PWR_APCR + register is set, the I/Os can be configured either with a pull-up through + PWR_PUCRx registers (x=N,O), or with a pull-down through + PWR_PDCRx registers (x=N,O,P), or can be kept in analog state + if none of the PWR_PUCRx or PWR_PDCRx register is set. + + [..] + The pull-down configuration has highest priority over pull-up + configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same + I/O. + +@endverbatim + * @{ + */ + +/** + * @brief Enable pull-up and pull-down configuration. + * @note When APC bit is set, the I/O pull-up and pull-down configurations + * defined in PWR_PUCRx and PWR_PDCRx registers are applied in Standby + * mode. + * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the + * corresponding PDy bit of PWR_PDCRx register is also set (pull-down + * configuration priority is higher). HAL_PWREx_EnableGPIOPullUp() and + * HAL_PWREx_EnableGPIOPullDown() API's ensure there is no conflict + * when setting PUy or PDy bit. + * @retval None. + */ +void HAL_PWREx_EnablePullUpPullDownConfig(void) +{ + SET_BIT(PWR->APCR, PWR_APCR_APC); +} + +/** + * @brief Disable pull-up and pull-down configuration. + * @note When APC bit is cleared, the I/O pull-up and pull-down configurations + * defined in PWR_PUCRx and PWR_PDCRx registers are not applied in + * Standby mode. + * @retval None. + */ +void HAL_PWREx_DisablePullUpPullDownConfig(void) +{ + CLEAR_BIT(PWR->APCR, PWR_APCR_APC); +} + +/** + * @brief Enable GPIO pull-up state in Standby mode. + * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in + * pull-up state in Standby mode. + * @note This state is effective in Standby mode only if APC bit + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is maintained when exiting the Standby mode. + * @note Even if a PUy bit to set is reserved, the other PUy bits entered as + * input parameter at the same time are set. + * @note The pullup is not activated if the corresponding PDy bit is also set. + * @param GPIO_Port : Specify the IO port. + * This parameter can be a value of @ref PWREx_GPIO_PullUp_Port. + * @param GPIO_Pin : Specify the I/O pins numbers. + * This parameter can be a combination of @ref PWREx_GPIO_PullUp_Pin_Mask. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_PWR_GPIO_PULLPUP_PORT(GPIO_Port)); + assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin)); + + switch (GPIO_Port) + { + case PWR_GPIO_PULLUP_PORT_N: + SET_BIT(PWR->PUCRN, GPIO_Pin); + break; + + case PWR_GPIO_PULLUP_PORT_O: + SET_BIT(PWR->PUCRO, GPIO_Pin); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Disable GPIO pull-up state in Standby mode. + * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O + * in pull-up state in Standby mode. + * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input + * parameter at the same time are reset. + * @param GPIO_Port : Specify the IO port. + * This parameter can be a value of @ref PWREx_GPIO_PullUp_Port. + * @param GPIO_Pin : Specify the I/O pins numbers. + * This parameter can be a combination of @ref PWREx_GPIO_PullUp_Pin_Mask. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_PWR_GPIO_PULLPUP_PORT(GPIO_Port)); + assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin)); + + switch (GPIO_Port) + { + case PWR_GPIO_PULLUP_PORT_N: + CLEAR_BIT(PWR->PUCRN, GPIO_Pin); + break; + + case PWR_GPIO_PULLUP_PORT_O: + CLEAR_BIT(PWR->PUCRO, GPIO_Pin); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Enable GPIO pull-down state in Standby mode. + * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in + * pull-down state in Standby mode. + * @note This state is effective in Standby mode only if APC bit + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is maintained when exiting the Standby mode. + * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input + * parameter at the same time are set. + * @param GPIO_Port : Specify the IO port. + * This parameter can be a value of @ref PWREx_GPIO_PullDown_Port. + * @param GPIO_Pin : Specify the I/O pins numbers. + * This parameter can be a combination of @ref PWREx_GPIO_PullDown_Pin_Mask. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_PWR_GPIO_PULLDOWN_PORT(GPIO_Port)); + assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin)); + + switch (GPIO_Port) + { + case PWR_GPIO_PULLDOWN_PORT_N: + SET_BIT(PWR->PDCRN, GPIO_Pin); + break; + + case PWR_GPIO_PULLDOWN_PORT_O: + SET_BIT(PWR->PDCRO, GPIO_Pin); + break; + + case PWR_GPIO_PULLDOWN_PORT_P: + SET_BIT(PWR->PDCRP, GPIO_Pin); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Disable GPIO pull-down state in Standby mode. + * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O + * in pull-down state in Standby mode. + * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input + * parameter at the same time are reset. + * @param GPIO_Port : Specify the IO port. + * This parameter can be a value of @ref PWREx_GPIO_PullDown_Port. + * @param GPIO_Pin : Specify the I/O pins numbers. + * This parameter can be a value of @ref PWREx_GPIO_PullDown_Pin_Mask. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_PWR_GPIO_PULLDOWN_PORT(GPIO_Port)); + assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin)); + + switch (GPIO_Port) + { + case PWR_GPIO_PULLDOWN_PORT_N: + CLEAR_BIT(PWR->PDCRN, GPIO_Pin); + break; + + case PWR_GPIO_PULLDOWN_PORT_O: + CLEAR_BIT(PWR->PDCRO, GPIO_Pin); + break; + + case PWR_GPIO_PULLDOWN_PORT_P: + CLEAR_BIT(PWR->PDCRP, GPIO_Pin); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_ramecc.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_ramecc.c new file mode 100644 index 00000000000..784b689179d --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_ramecc.c @@ -0,0 +1,966 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_ramecc.c + * @author MCD Application Team + * @brief RAMECC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the RAM ECC monitoring (RAMECC) peripheral: + * + Initialization and de-initialization functions + * + Monitoring operation functions + * + Error information functions + * + State and error functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and latch error information through HAL_RAMECC_Init(). + + (#) For a given Monitor, enable and disable interrupt through + HAL_RAMECC_EnableNotification(). + To enable a notification for a given RAMECC instance, use global + interrupts. + To enable a notification for only RAMECC monitor, use monitor interrupts. + All possible notifications are defined in the driver header file under + RAMECC_Interrupt group. + + *** Silent mode *** + =================== + [..] + (+) Use HAL_RAMECC_StartMonitor() to start RAMECC latch failing + information without enabling any notification. + + *** Interrupt mode *** + ====================== + [..] + (+) Use HAL_RAMECC_EnableNotification() to enable interrupts for a + given error. + (+) Configure the RAMECC interrupt priority using + HAL_NVIC_SetPriority(). + (+) Enable the RAMECC IRQ handler using HAL_NVIC_EnableIRQ(). + (+) Start RAMECC latch failing information using HAL_RAMECC_StartMonitor(). + + *** Failing information *** + ====================== + [..] + (#) Use HAL_RAMECC_GetFailingAddress() function to return the RAMECC + failing address. + (#) Use HAL_RAMECC_GetFailingDataLow() function to return the RAMECC + failing data low. + (#) Use HAL_RAMECC_GetFailingDataHigh() function to return the RAMECC + failing data high. + (#) Use HAL_RAMECC_GetHammingErrorCode() function to return the RAMECC + Hamming bits injected. + (#) Use HAL_RAMECC_IsECCSingleErrorDetected() function to check if a single + error was detected and corrected. + (#) Use HAL_RAMECC_IsECCDoubleErrorDetected() function to check if a double + error was dedetected. + + *** RAMECC HAL driver macros list *** + ============================================= + [..] + Below the list of used macros in RAMECC HAL driver. + + (+) __HAL_RAMECC_ENABLE_IT : Enable the specified ECCRAM Monitor + interrupts. + (+) __HAL_RAMECC_DISABLE_IT : Disable the specified ECCRAM Monitor + interrupts. + (+) __HAL_RAMECC_GET_FLAG : Return the current RAMECC Monitor selected + flag. + (+) __HAL_RAMECC_CLEAR_FLAG : Clear the current RAMECC Monitor selected + flag. + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup RAMECC RAMECC + * @brief RAMECC HAL module driver + * @{ + */ + +#ifdef HAL_RAMECC_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup RAMECC_Exported_Functions + * @{ + */ + +/** @addtogroup RAMECC_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the RAMECC Monitor. + [..] + The HAL_RAMECC_Init() function follows the RAMECC configuration procedures + as described in reference manual. + The HAL_RAMECC_DeInit() function allows to deinitialize the RAMECC monitor. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the RAMECC by clearing flags and disabling interrupts. + * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains + * the configuration information for the specified RAMECC + * Monitor. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMECC_Init(RAMECC_HandleTypeDef *hramecc) +{ + /* Check the RAMECC peripheral handle */ + if (hramecc == NULL) + { + /* Return HAL status */ + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance)); + + /* Change RAMECC peripheral state */ + hramecc->State = HAL_RAMECC_STATE_BUSY; + +#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1) + /* Check if a valid MSP API was registered */ + if (hramecc->MspInitCallback == NULL) + { + /* Init the low level hardware */ + hramecc->MspInitCallback = HAL_RAMECC_MspInit; + } + + /* Init the low level hardware */ + hramecc->MspInitCallback(hramecc); +#else + HAL_RAMECC_MspInit(hramecc); +#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */ + + /* Disable RAMECC monitor */ + hramecc->Instance->CR &= ~RAMECC_CR_ECCELEN; + + /* Disable all global interrupts */ + ((RAMECC_TypeDef *)((uint32_t)hramecc->Instance & 0xFFFFFF00U))->IER &= \ + ~(RAMECC_IER_GIE | RAMECC_IER_GECCSEIE | RAMECC_IER_GECCDEIE | RAMECC_IER_GECCDEBWIE); + + /* Disable all interrupts monitor */ + hramecc->Instance->CR &= ~(RAMECC_CR_ECCSEIE | RAMECC_CR_ECCDEIE | RAMECC_CR_ECCDEBWIE); + + /* Clear RAMECC monitor flags */ + __HAL_RAMECC_CLEAR_FLAG(hramecc, RAMECC_FLAGS_ALL); + + /* Initialise the RAMECC error code */ + hramecc->ErrorCode = HAL_RAMECC_ERROR_NONE; + + /* Update the RAMECC state */ + hramecc->State = HAL_RAMECC_STATE_READY; + + /* Return HAL status */ + return HAL_OK; +} + + +/** + * @brief DeInitializes the RAMECC peripheral. + * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains + * the configuration information for the specified RAMECC + * Monitor. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMECC_DeInit(RAMECC_HandleTypeDef *hramecc) +{ + /* Check the RAMECC peripheral handle */ + if (hramecc == NULL) + { + /* Return HAL status */ + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance)); + + /* Disable RAMECC monitor */ + hramecc->Instance->CR &= ~RAMECC_CR_ECCELEN; + + /* Disable all global interrupts */ + ((RAMECC_TypeDef *)((uint32_t)hramecc->Instance & 0xFFFFFF00U))->IER &= \ + ~(RAMECC_IER_GIE | RAMECC_IER_GECCSEIE | RAMECC_IER_GECCDEIE | RAMECC_IER_GECCDEBWIE); + + /* Disable all interrupts monitor */ + hramecc->Instance->CR &= ~(RAMECC_CR_ECCSEIE | RAMECC_CR_ECCDEIE | RAMECC_CR_ECCDEBWIE); + + /* Clear RAMECC monitor flags */ + __HAL_RAMECC_CLEAR_FLAG(hramecc, RAMECC_FLAGS_ALL); + + +#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1) + /* Check if a valid MSP API was registered */ + if (hramecc->MspDeInitCallback != NULL) + { + /* Init the low level hardware */ + hramecc->MspDeInitCallback(hramecc); + } + + /* Clean callbacks */ + hramecc->DetectSingleErrorCallback = NULL; + hramecc->DetectDoubleErrorCallback = NULL; +#else + HAL_RAMECC_MspDeInit(hramecc); +#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */ + + /* Initialise the RAMECC error code */ + hramecc->ErrorCode = HAL_RAMECC_ERROR_NONE; + + /* Change RAMECC peripheral state */ + hramecc->State = HAL_RAMECC_STATE_RESET; + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief Initialize the RAMECC MSP. + * @param hramecc : Pointer to a RAMECC_HandleTypeDef structure that contains + * the configuration information for the specified RAMECC. + * @retval None. + */ +__weak void HAL_RAMECC_MspInit(RAMECC_HandleTypeDef *hramecc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hramecc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RAMECC_MspInit can be implemented in the user file */ +} + +/** + * @brief DeInitialize the RAMECC MSP. + * @param hramecc : Pointer to a RAMECC_HandleTypeDef structure that contains + * the configuration information for the specified RAMECC. + * @retval None. + */ +__weak void HAL_RAMECC_MspDeInit(RAMECC_HandleTypeDef *hramecc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hramecc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RAMECC_MspDeInit can be implemented in the user file */ +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RAMECC_Exported_Functions_Group2 + * +@verbatim + =============================================================================== + ##### Monitoring operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure latching error information. + (+) Configure RAMECC Global/Monitor interrupts. + (+) Register and Unregister RAMECC callbacks + (+) Handle RAMECC interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the RAMECC latching error information. + * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains + * the configuration information for the specified RAMECC + * Monitor. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMECC_StartMonitor(RAMECC_HandleTypeDef *hramecc) +{ + /* Check the parameters */ + assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance)); + + /* Check RAMECC state */ + if (hramecc->State == HAL_RAMECC_STATE_READY) + { + /* Change RAMECC peripheral state */ + hramecc->State = HAL_RAMECC_STATE_BUSY; + + /* Enable RAMECC monitor */ + hramecc->Instance->CR |= RAMECC_CR_ECCELEN; + + /* Change RAMECC peripheral state */ + hramecc->State = HAL_RAMECC_STATE_READY; + } + else + { + /* Update the error code */ + hramecc->ErrorCode = HAL_RAMECC_ERROR_BUSY; + + /* Return HAL status */ + return HAL_ERROR; + } + + /* Return HAL status */ + return HAL_OK; +} + + +/** + * @brief Stop the RAMECC latching error information. + * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains + * the configuration information for the specified RAMECC + * Monitor. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMECC_StopMonitor(RAMECC_HandleTypeDef *hramecc) +{ + /* Check the parameters */ + assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance)); + + /* Check RAMECC state */ + if (hramecc->State == HAL_RAMECC_STATE_READY) + { + /* Change RAMECC peripheral state */ + hramecc->State = HAL_RAMECC_STATE_BUSY; + + /* Disable RAMECC monitor */ + hramecc->Instance->CR &= ~RAMECC_CR_ECCELEN; + + /* Change RAMECC peripheral state */ + hramecc->State = HAL_RAMECC_STATE_READY; + } + else + { + /* Update the error code */ + hramecc->ErrorCode = HAL_RAMECC_ERROR_BUSY; + + /* Return HAL status */ + return HAL_ERROR; + } + + /* Return HAL status */ + return HAL_OK; +} + + +/** + * @brief Enable the RAMECC error interrupts. + * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMECC Monitor. + * @param Notifications Select the notification. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMECC_EnableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications) +{ + /* Check the parameters */ + assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance)); + assert_param(IS_RAMECC_INTERRUPT(Notifications)); + + /* Check RAMECC state */ + if (hramecc->State == HAL_RAMECC_STATE_READY) + { + /* Change RAMECC peripheral state */ + hramecc->State = HAL_RAMECC_STATE_BUSY; + + /* Enable RAMECC interrupts */ + __HAL_RAMECC_ENABLE_IT(hramecc, Notifications); + + /* Change RAMECC peripheral state */ + hramecc->State = HAL_RAMECC_STATE_READY; + } + else + { + /* Update the error code */ + hramecc->ErrorCode = HAL_RAMECC_ERROR_BUSY; + + /* Return HAL status */ + return HAL_ERROR; + } + + /* Return HAL status */ + return HAL_OK; +} + + +/** + * @brief Disable the RAMECC error interrupts. + * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMECC Monitor. + * @param Notifications Select the notification. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMECC_DisableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications) +{ + /* Check the parameters */ + assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance)); + assert_param(IS_RAMECC_INTERRUPT(Notifications)); + + /* Check RAMECC state */ + if (hramecc->State == HAL_RAMECC_STATE_READY) + { + /* Change RAMECC peripheral state */ + hramecc->State = HAL_RAMECC_STATE_BUSY; + + /* Disable RAMECC interrupts */ + __HAL_RAMECC_DISABLE_IT(hramecc, Notifications); + + /* Change RAMECC peripheral state */ + hramecc->State = HAL_RAMECC_STATE_READY; + } + else + { + /* Update the error code */ + hramecc->ErrorCode = HAL_RAMECC_ERROR_BUSY; + + /* Return HAL status */ + return HAL_ERROR; + } + + /* Return HAL status */ + return HAL_OK; +} + + +/** @addtogroup RAMCECC_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### Handle Interrupt and Callbacks Functions ##### + =============================================================================== + [..] + This section provides functions to handle RAMECC interrupts and + Register / UnRegister the different callbacks. + [..] + The HAL_RAMECC_IRQHandler() function allows handling the active RAMECC + interrupt request. + The HAL_RAMECC_RegisterCallback() function allows registering the selected + RAMECC callbacks. + The HAL_RAMECC_UnRegisterCallback() function allows unregistering the + selected RAMECC callbacks. +@endverbatim + * @{ + */ + +/** + * @brief Handles RAMECC interrupt request. + * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains + * the configuration information for the specified RAMECC + * Monitor. + * @retval None. + */ +void HAL_RAMECC_IRQHandler(RAMECC_HandleTypeDef *hramecc) +{ + uint32_t monitor_it_source; + uint32_t global_it_source; + + monitor_it_source = READ_REG(hramecc->Instance->CR); + global_it_source = READ_REG(((RAMECC_TypeDef *)((uint32_t)hramecc->Instance & 0xFFFFFF00U))->IER); + + /* Single Error Interrupt Management ****************************************/ + if (((monitor_it_source & RAMECC_CR_ECCSEIE) == RAMECC_CR_ECCSEIE) || + ((global_it_source & RAMECC_IER_GECCSEIE) == RAMECC_IER_GECCSEIE) || + ((global_it_source & RAMECC_IER_GIE) == RAMECC_IER_GIE)) + { + if (__HAL_RAMECC_GET_FLAG(hramecc, RAMECC_FLAG_SINGLEERR_R) != 0U) + { + /* Clear active flags */ + __HAL_RAMECC_CLEAR_FLAG(hramecc, RAMECC_FLAG_SINGLEERR_R); + +#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1) + /* Check if a valid single error callback is registered */ + if (hramecc->DetectSingleErrorCallback != NULL) + { + /* Single error detection callback */ + hramecc->DetectSingleErrorCallback(hramecc); + } +#else + HAL_RAMECC_DetectSingleErrorCallback(hramecc); +#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */ + } + } + + /* Double Error Interrupt Management ****************************************/ + if (((monitor_it_source & RAMECC_CR_ECCDEIE) == RAMECC_CR_ECCDEIE) || + ((monitor_it_source & RAMECC_CR_ECCDEBWIE) == RAMECC_CR_ECCDEBWIE) || + ((global_it_source & RAMECC_IER_GECCDEIE) == RAMECC_IER_GECCDEIE) || + ((global_it_source & RAMECC_IER_GECCDEBWIE) == RAMECC_IER_GECCDEBWIE) || + ((global_it_source & RAMECC_IER_GIE) == RAMECC_IER_GIE)) + { + /* ECC double error detected flag */ + if (__HAL_RAMECC_GET_FLAG(hramecc, RAMECC_FLAG_DOUBLEERR_R) != 0U) + { + /* Clear active flags */ + __HAL_RAMECC_CLEAR_FLAG(hramecc, RAMECC_FLAG_DOUBLEERR_R); + +#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1) + /* Check if a valid Double error callback is registered */ + if (hramecc->DetectDoubleErrorCallback != NULL) + { + /* Double error detection callback */ + hramecc->DetectDoubleErrorCallback(hramecc); + } +#else + HAL_RAMECC_DetectDoubleErrorCallback(hramecc); +#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */ + } + + /* ECC double error on byte write */ + if (__HAL_RAMECC_GET_FLAG(hramecc, RAMECC_FLAG_DOUBLEERR_W) != 0U) + { + /* Clear active flags */ + __HAL_RAMECC_CLEAR_FLAG(hramecc, RAMECC_FLAG_DOUBLEERR_W); + +#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1) + /* Check if a valid Double error callback is registered */ + if (hramecc->DetectDoubleErrorCallback != NULL) + { + /* Double error detection callback */ + hramecc->DetectDoubleErrorCallback(hramecc); + } +#else + HAL_RAMECC_DetectDoubleErrorCallback(hramecc); +#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief RAMECC single error detection callback. + * @param hramecc : Pointer to a RAMECC_HandleTypeDef structure that contains + * the configuration information for the specified RAMECC. + * @retval None. + */ +__weak void HAL_RAMECC_DetectSingleErrorCallback(RAMECC_HandleTypeDef *hramecc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hramecc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RAMECC_DetectSingleErrorCallback can be implemented in + the user file. */ +} + +/** + * @brief RAMECC double error detection callback. + * @param hramecc : Pointer to a RAMECC_HandleTypeDef structure that contains + * the configuration information for the specified RAMECC. + * @retval None. + */ +__weak void HAL_RAMECC_DetectDoubleErrorCallback(RAMECC_HandleTypeDef *hramecc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hramecc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RAMECC_DetectDoubleErrorCallback can be implemented in + the user file. */ +} + +#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1) +/** + * @brief Register RAMECC callbacks. + * @param hramecc : Pointer to a RAMECC_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMECC instance. + * @param CallbackID : User Callback identifier a HAL_RAMECC_CallbackIDTypeDef + * ENUM as parameter. + * @param pCallback : Pointer to private callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMECC_RegisterCallback(RAMECC_HandleTypeDef *hramecc, + HAL_RAMECC_CallbackIDTypeDef CallbackID, + void (* pCallback)(RAMECC_HandleTypeDef *_hramecc)) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code and return error */ + hramecc->ErrorCode |= HAL_RAMECC_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance)); + + /* Check RAMECC state */ + if (hramecc->State == HAL_RAMECC_STATE_READY) + { + switch (CallbackID) + { + case HAL_RAMECC_SE_DETECT_CB_ID: + /* Register single error callback */ + hramecc->DetectSingleErrorCallback = pCallback; + break; + + case HAL_RAMECC_DE_DETECT_CB_ID: + /* Register double error callback */ + hramecc->DetectDoubleErrorCallback = pCallback; + break; + + case HAL_RAMECC_MSPINIT_CB_ID : + /* Register msp init callback */ + hramecc->MspInitCallback = pCallback; + break; + + case HAL_RAMECC_MSPDEINIT_CB_ID : + /* Register msp de-init callback */ + hramecc->MspDeInitCallback = pCallback; + break; + + default: + /* Update the error code and return error */ + hramecc->ErrorCode |= HAL_RAMECC_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else if (hramecc->State == HAL_RAMECC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_RAMECC_MSPINIT_CB_ID : + /* Register msp init callback */ + hramecc->MspInitCallback = pCallback; + break; + + case HAL_RAMECC_MSPDEINIT_CB_ID : + /* Register msp de-init callback */ + hramecc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code and return error */ + hramecc->ErrorCode |= HAL_RAMECC_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code and return error */ + hramecc->ErrorCode = HAL_RAMECC_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister RAMECC callbacks. + * @param hramecc : Pointer to a RAMECC_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMECC instance. + * @param CallbackID : User Callback identifier a HAL_RAMECC_CallbackIDTypeDef + * ENUM as parameter. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback(RAMECC_HandleTypeDef *hramecc, HAL_RAMECC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance)); + + /* Check RAMECC state */ + if (hramecc->State == HAL_RAMECC_STATE_READY) + { + switch (CallbackID) + { + case HAL_RAMECC_SE_DETECT_CB_ID: + /* UnRegister single error callback */ + hramecc->DetectSingleErrorCallback = NULL; + break; + + case HAL_RAMECC_DE_DETECT_CB_ID: + /* UnRegister double error callback */ + hramecc->DetectDoubleErrorCallback = NULL; + break; + + case HAL_RAMECC_MSPINIT_CB_ID : + /* UnRegister msp init callback */ + hramecc->MspInitCallback = NULL; + break; + + case HAL_RAMECC_MSPDEINIT_CB_ID : + /* UnRegister msp de-init callback */ + hramecc->MspDeInitCallback = NULL; + break; + + case HAL_RAMECC_ALL_CB_ID: + /* UnRegister all available callbacks */ + hramecc->DetectSingleErrorCallback = NULL; + hramecc->DetectDoubleErrorCallback = NULL; + hramecc->MspDeInitCallback = NULL; + hramecc->MspInitCallback = NULL; + break; + + default: + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hramecc->State == HAL_RAMECC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_RAMECC_MSPINIT_CB_ID : + /* UnRegister msp init callback */ + hramecc->MspInitCallback = NULL; + break; + + case HAL_RAMECC_MSPDEINIT_CB_ID : + /* UnRegister msp de-init callback */ + hramecc->MspDeInitCallback = NULL; + break; + + case HAL_RAMECC_ALL_CB_ID: + /* UnRegister all available callbacks */ + hramecc->MspDeInitCallback = NULL; + hramecc->MspInitCallback = NULL; + break; + + default : + /* Update the error code */ + hramecc->ErrorCode |= HAL_RAMECC_ERROR_INVALID_CALLBACK; + + /* Update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code and return error */ + hramecc->ErrorCode = HAL_RAMECC_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + + return status; +} +/** + * @} + */ +#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup RAMECC_Exported_Functions_Group4 + * +@verbatim + =============================================================================== + ##### Error information functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Get failing address. + (+) Get failing data low. + (+) Get failing data high. + (+) Get hamming bits injected. + (+) Check single error flag. + (+) Check double error flag. + +@endverbatim + * @{ + */ + +/** + * @brief Return the RAMECC failing address. + * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains + * the configuration information for the specified RAMECC + * Monitor. + * @retval Failing address offset. + */ +uint32_t HAL_RAMECC_GetFailingAddress(const RAMECC_HandleTypeDef *hramecc) +{ + /* Check the parameters */ + assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance)); + + /* Return failing address */ + return hramecc->Instance->FAR; +} + + +/** + * @brief Return the RAMECC data low. + * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains + * the configuration information for the specified RAMECC + * Monitor. + * @retval Failing data low. + */ +uint32_t HAL_RAMECC_GetFailingDataLow(const RAMECC_HandleTypeDef *hramecc) +{ + /* Check the parameters */ + assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance)); + + /* Return failing data low */ + return hramecc->Instance->FDRL; +} + + +/** + * @brief Return the RAMECC data high. + * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains + * the configuration information for the specified RAMECC + * Monitor. + * @retval Failing data high. + */ +uint32_t HAL_RAMECC_GetFailingDataHigh(const RAMECC_HandleTypeDef *hramecc) +{ + /* Check the parameters */ + assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance)); + + /* Return failing data high */ + return hramecc->Instance->FDRH; +} + + +/** + * @brief Return the RAMECC Hamming bits injected. + * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains + * the configuration information for the specified RAMECC + * Monitor. + * @retval Hamming bits injected. + */ +uint32_t HAL_RAMECC_GetHammingErrorCode(const RAMECC_HandleTypeDef *hramecc) +{ + /* Check the parameters */ + assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance)); + + /* Return hamming bits injected */ + return hramecc->Instance->FECR; +} + +/** + * @brief Check if an ECC single error was occurred. + * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains + * the configuration information for the specified RAMECC + * Monitor. + * @retval State of bit (1 or 0). + */ +uint32_t HAL_RAMECC_IsECCSingleErrorDetected(const RAMECC_HandleTypeDef *hramecc) +{ + /* Check the parameters */ + assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance)); + + /* Return the state of SEDC flag */ + return ((READ_BIT(hramecc->Instance->SR, RAMECC_SR_SEDCF) == (RAMECC_SR_SEDCF)) ? 1UL : 0UL); +} + +/** + * @brief Check if an ECC double error was occurred. + * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains + * the configuration information for the specified RAMECC + * Monitor. + * @retval State of bit (1 or 0). + */ +uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(const RAMECC_HandleTypeDef *hramecc) +{ + /* Check the parameters */ + assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance)); + + /* Return the state of DEDF | DEBWDF flags */ + return ((READ_BIT(hramecc->Instance->SR, (RAMECC_SR_DEDF | RAMECC_SR_DEBWDF)) != 0U) ? 1UL : 0UL); +} +/** + * @} + */ + + +/** @addtogroup RAMECC_Exported_Functions_Group5 + * +@verbatim + =============================================================================== + ##### State and Error Functions ##### + =============================================================================== + [..] + This section provides functions allowing to check and get the RAMECC state + and the error code . + [..] + The HAL_RAMECC_GetState() function allows to get the RAMECC peripheral + state. + The HAL_RAMECC_GetError() function allows to Get the RAMECC peripheral error + code. + +@endverbatim + * @{ + */ + +/** + * @brief Get the RAMECC peripheral state. + * @param hramecc : Pointer to a RAMECC_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMECC instance. + * @retval RAMECC state. + */ +HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(const RAMECC_HandleTypeDef *hramecc) +{ + /* Return the RAMECC state */ + return hramecc->State; +} + +/** + * @brief Get the RAMECC peripheral error code. + * @param hramecc : Pointer to a RAMECC_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMECC instance. + * @retval RAMECC error code. + */ +uint32_t HAL_RAMECC_GetError(const RAMECC_HandleTypeDef *hramecc) +{ + /* Return the RAMECC error code */ + return hramecc->ErrorCode; +} +/** + * @} + */ +#endif /* HAL_RAMECC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rcc.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rcc.c new file mode 100644 index 00000000000..6af6d0edd35 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rcc.c @@ -0,0 +1,2332 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except + internal SRAM, Flash, JTAG and PWR + (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in analogue mode , except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses pre-scalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock kernel source(s) for peripherals which clocks are not + derived from the System clock. + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + after the clock enable bit is set on the hardware register + (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + after the clock enable bit is set on the hardware register + + [..] + Implemented Workaround: + (+) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +#define RCC_CSI_TIMEOUT_VALUE 1U /* 1 ms */ +#define RCC_HSI_TIMEOUT_VALUE 1U /* 1 ms */ +#define RCC_HSI48_TIMEOUT_VALUE 1U /* 1 ms */ +#define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define RCC_LSI_TIMEOUT_VALUE 1U /* 1 ms */ +#define RCC_CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ +#define RCC_PLL_FRAC_WAIT_VALUE 1U /* PLL Fractional part waiting time before new latch enable : 1 ms */ +#define RCC_PLL_INPUTRANGE0_FREQMAX 2000000U /* 2 MHz is maximum frequency for VCO input range 0 */ +#define RCC_PLL_INPUTRANGE1_FREQMAX 4000000U /* 4 MHz is maximum frequency for VCO input range 1 */ +#define RCC_PLL_INPUTRANGE2_FREQMAX 8000000U /* 8 MHz is maximum frequency for VCO input range 2 */ + +#define RCC_PLL1_CONFIG 0U +#define RCC_PLL2_CONFIG 1U +#define RCC_PLL3_CONFIG 2U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ +#define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK) + +#define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS) + +#define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS) + +#define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) (GPIOA_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX((__RCC_MCOx__)))) + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables Private Variables + * @{ + */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_Private_Functions RCC Private Functions + * @{ + */ +static uint32_t RCC_PLL1_GetVCOOutputFreq(void); +static uint32_t RCC_PLL2_GetVCOOutputFreq(void); +static uint32_t RCC_PLL3_GetVCOOutputFreq(void); +static HAL_StatusTypeDef RCC_PLL_Config(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1 + AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral + clock, or PLL input.But even with frequency calibration, is less accurate than an + external crystal oscillator or ceramic resonator. + (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI), + featuring three different output clocks and able to work either in integer or Fractional mode. + (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU + and to some peripherals. + (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals. + + + (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt) + exception vector. + + (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q) + or HSI48 clock (through a configurable pre-scaler) on PA8 pin. + + (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK, + LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin. + + [..] System, AHB and APB buses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System core clock through configurable + pre-scaler and used to clock the CPU, memory and peripherals mapped + on AHB and APB bus through configurable pre-scalers + and used to clock the peripherals mapped on these buses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency. + +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL1, PLL2 and PLL3 OFF + * - AHB, APB Bus pre-scaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @note In case the FMC or XSPI clock protection have been set, it must be disabled + * prior to calling this API. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[6:0] bits to the reset value */ + SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6); + + if (HAL_RCC_GetHCLKFreq() > HSI_VALUE) + { + /* Reset CFGR register (HSI is selected as system clock source) */ + CLEAR_REG(RCC->CFGR); + + /* Update the SystemCoreClock global variables */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reduce flash latency */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1); + } + else + { + /* Increase flash latency */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1); + + /* Reset CFGR register (HSI is selected as system clock source) */ + CLEAR_REG(RCC->CFGR); + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_CSION | RCC_CR_CSIKERON \ + | RCC_CR_HSI48ON | RCC_CR_HSECSSON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLL2ON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); + + /* Wait till PLL2 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLL3 bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); + + /* Wait till PLL3 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset CDCFGR register */ + CLEAR_REG(RCC->CDCFGR); + + /* Reset BMCFGR register */ + CLEAR_REG(RCC->BMCFGR); + + /* Reset APBCFGR register */ + CLEAR_REG(RCC->APBCFGR); + + /* Reset PLLCKSELR register to default value */ + WRITE_REG(RCC->PLLCKSELR, 0x02020200U); + + /* Reset PLLCFGR register */ + CLEAR_REG(RCC->PLLCFGR); + + /* Reset PLL1DIVR1 register to default value */ + WRITE_REG(RCC->PLL1DIVR1, 0x01010280U); + + /* Reset PLL1DIVR2 register to default value */ + WRITE_REG(RCC->PLL1DIVR2, 0x00000101U); + + /* Reset PLL1FRACR register */ + CLEAR_REG(RCC->PLL1FRACR); + + /* Reset PLL2DIVR1 register to default value */ + WRITE_REG(RCC->PLL2DIVR1, 0x01010280U); + + /* Reset PLL2DIVR2 register to default value */ + WRITE_REG(RCC->PLL2DIVR2, 0x00000101U); + + /* Reset PLL2FRACR register */ + CLEAR_REG(RCC->PLL2FRACR); + + /* Reset PLL3DIVR1 register to default value */ + WRITE_REG(RCC->PLL3DIVR1, 0x01010280U); + + /* Reset PLL3DIVR2 register to default value */ + WRITE_REG(RCC->PLL3DIVR2, 0x00000101U); + + /* Reset PLL3FRACR register */ + CLEAR_REG(RCC->PLL3FRACR); + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIER); + + /* Clear all interrupts flags */ + WRITE_REG(RCC->CICR, 0xFFFFFFFFU); + + /* Reset all RSR flags */ + SET_BIT(RCC->RSR, RCC_RSR_RMVF); + + return HAL_OK; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t sysclksrc; + uint32_t pllsrc; + uint32_t pllrdy; + uint32_t tmpreg1; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + pllsrc = __HAL_RCC_GET_PLL_OSCSOURCE(); + pllrdy = RCC->CR & (RCC_CR_PLL1RDY | RCC_CR_PLL2RDY | RCC_CR_PLL3RDY); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ + if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) || + ((pllrdy != 0U) && (pllsrc == RCC_PLLSOURCE_HSE))) + { + if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Wait till HSE is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL1 source when PLL1 is selected as system clock */ + if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) || + ((pllrdy != 0U) && (pllsrc == RCC_PLLSOURCE_HSI))) + { + /* When HSI is used as system clock it will not be disabled */ + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) + { + return HAL_ERROR; + } + /* Otherwise, calibration is allowed, divider update also unless used for any enabled PLL */ + else + { + /* HSI must not be used as reference clock for any enabled PLL clock source */ + tmpreg1 = (RCC->CR & RCC_CR_HSIDIV); + if ((pllsrc == RCC_PLLSOURCE_HSI) && (pllrdy != 0U) && \ + (tmpreg1 != RCC_OscInitStruct->HSIDiv)) + { + return HAL_ERROR; + } + + assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); + + /* Set the Internal High Speed oscillator new divider */ + __HAL_RCC_HSI_CONFIG(RCC_HSI_ON | RCC_OscInitStruct->HSIDiv); + + if (sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) + { + SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos))); + } + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + } + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState | RCC_OscInitStruct->HSIDiv); + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- CSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) + { + /* Check the parameters */ + assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); + + /* When the CSI is used as system clock it will not disabled */ + if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_CSI) || + ((pllrdy != 0U) && (pllsrc == RCC_PLLSOURCE_CSI))) + { + /* When CSI is used as system clock it will not disabled */ + if (RCC_OscInitStruct->CSIState == RCC_CSI_OFF) + { + return HAL_ERROR; + } + } + else + { + /* Check the CSI State */ + if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) + { + /* Enable the Internal High Speed oscillator (CSI). */ + __HAL_RCC_CSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till CSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_CSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_CSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal High Speed oscillator (CSI). */ + __HAL_RCC_CSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till CSI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_CSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /*------------------------------ HSI48 Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* Check the HSI48 State */ + if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) + { + /* Enable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + + /* Get time-out */ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + + /* Get time-out */ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /*-------------------------------- PLL1 Configuration ----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL1.PLLState)); + + if (RCC_OscInitStruct->PLL1.PLLState != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + /* No PLL off possible */ + if (RCC_OscInitStruct->PLL1.PLLState == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Check if only fractional part needs to be updated */ + tmpreg1 = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN) >> RCC_PLL1FRACR_FRACN_Pos); + + if (RCC_OscInitStruct->PLL1.PLLFractional != tmpreg1) + { + assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL1.PLLFractional)); + + /* Disable PLL1FRACLE */ + __HAL_RCC_PLL1_FRACN_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ + while ((HAL_GetTick() - tickstart) < RCC_PLL_FRAC_WAIT_VALUE) + { + /* Do nothing */ + } + + /* Configure PLL1FRACN */ + __HAL_RCC_PLL1_FRACN_CONFIG(RCC_OscInitStruct->PLL1.PLLFractional); + + /* Enable PLL1FRACLE to latch new value . */ + __HAL_RCC_PLL1_FRACN_ENABLE(); + } + } + } + else + { + /* Initialize PLL1T to 1 to use common PLL initialization function */ + RCC_OscInitStruct->PLL1.PLLT = 1U; + if (RCC_PLL_Config(RCC_PLL1_CONFIG, &(RCC_OscInitStruct->PLL1)) != HAL_OK) + { + return HAL_ERROR; + } + } + } + + /*-------------------------------- PLL2 Configuration ----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL2.PLLState)); + + if (RCC_OscInitStruct->PLL2.PLLState != RCC_PLL_NONE) + { + if (RCC_PLL_Config(RCC_PLL2_CONFIG, &(RCC_OscInitStruct->PLL2)) != HAL_OK) + { + return HAL_ERROR; + } + } + + /*-------------------------------- PLL3 Configuration ----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL3.PLLState)); + + if (RCC_OscInitStruct->PLL3.PLLState != RCC_PLL_NONE) + { + /* Initialize PLL3T to 1 to use common PLL initialization function */ + RCC_OscInitStruct->PLL3.PLLT = 1U; + if (RCC_PLL_Config(RCC_PLL3_CONFIG, &(RCC_OscInitStruct->PLL3)) != HAL_OK) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency: FLASH Latency, this parameter depend on device selected + * + * @note The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency + * and updated by HAL_InitTick() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after start-up delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + HAL_StatusTypeDef halstatus; + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + + } + + /* Increasing the BUS frequency divider ? */ + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->APBCFGR & RCC_APBCFGR_PPRE1)) + { + MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->APBCFGR & RCC_APBCFGR_PPRE2)) + { + MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } + } + + /*-------------------------- PCLK4 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK4) == RCC_CLOCKTYPE_PCLK4) + { + assert_param(IS_RCC_PCLK4(RCC_ClkInitStruct->APB4CLKDivider)); + if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->APBCFGR & RCC_APBCFGR_PPRE4)) + { + MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE4, (RCC_ClkInitStruct->APB4CLKDivider)); + } + } + + /*-------------------------- PCLK5 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK5) == RCC_CLOCKTYPE_PCLK5) + { + assert_param(IS_RCC_PCLK5(RCC_ClkInitStruct->APB5CLKDivider)); + if ((RCC_ClkInitStruct->APB5CLKDivider) > (RCC->APBCFGR & RCC_APBCFGR_PPRE5)) + { + MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE5, (RCC_ClkInitStruct->APB5CLKDivider)); + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->BMCFGR & RCC_BMCFGR_BMPRE)) + { + /* Set the new HCLK clock divider */ + MODIFY_REG(RCC->BMCFGR, RCC_BMCFGR_BMPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + } + + /*------------------------- SYSCLK Configuration -------------------------*/ + if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); + MODIFY_REG(RCC->CDCFGR, RCC_CDCFGR_CPRE, RCC_ClkInitStruct->SYSCLKDivider); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U) + { + return HAL_ERROR; + } + } + /* CSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) + { + /* Check the PLL ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) == 0U) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + return HAL_ERROR; + } + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Decreasing the BUS frequency divider ? */ + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->BMCFGR & RCC_BMCFGR_BMPRE)) + { + /* Set the new HCLK clock divider */ + MODIFY_REG(RCC->BMCFGR, RCC_BMCFGR_BMPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->APBCFGR & RCC_APBCFGR_PPRE1)) + { + MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->APBCFGR & RCC_APBCFGR_PPRE2)) + { + MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } + } + + /*-------------------------- PCLK4 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK4) == RCC_CLOCKTYPE_PCLK4) + { + assert_param(IS_RCC_PCLK4(RCC_ClkInitStruct->APB4CLKDivider)); + if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->APBCFGR & RCC_APBCFGR_PPRE4)) + { + MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE4, (RCC_ClkInitStruct->APB4CLKDivider)); + } + } + + /*-------------------------- PCLK5 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK5) == RCC_CLOCKTYPE_PCLK5) + { + assert_param(IS_RCC_PCLK5(RCC_ClkInitStruct->APB5CLKDivider)); + if ((RCC_ClkInitStruct->APB5CLKDivider) < (RCC->APBCFGR & RCC_APBCFGR_PPRE5)) + { + MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE5, (RCC_ClkInitStruct->APB5CLKDivider)); + } + } + + /* Update the SystemCoreClock global variable with the System CPU clock */ + SystemCoreClock = HAL_RCC_GetSysClockFreq(); + + /* Configure the source of time base considering new system clocks settings*/ + halstatus = HAL_InitTick(uwTickPrio); + + return halstatus; +} + +/** + * @} + */ + +/** @defgroup RCC_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + +@endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). + * @note PA8/PC9 should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1_PA8 Clock source to output on MCO1 pin(PA8). + * @arg RCC_MCO2_PC9 Clock source to output on MCO2 pin(PC9). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLL1Q: PLL1Q clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSI48 HSI48 (48MHZ) selected as MCO1 source + * @arg RCC_MCO2SOURCE_SYSCLK System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLL2PCLK PLL2P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLL1P PLL1P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_CSI CSI clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source + * @param RCC_MCODiv: specifies the MCOx pre-scaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCOx clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ +#if defined(HAL_GPIO_MODULE_ENABLED) + GPIO_InitTypeDef GPIO_InitStruct; + uint32_t mcoindex; + uint32_t mco_gpio_index; + GPIO_TypeDef *mco_gpio_port; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + + /* Common GPIO init parameters */ + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + + /* Get MCOx selection */ + mcoindex = RCC_MCOx & RCC_MCO_INDEX_MASK; + + /* Get MCOx GPIO Port */ + mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx); + + /* MCOx Clock Enable */ + mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx); + SET_BIT(RCC->AHB4ENR, (1UL << mco_gpio_index)); + + /* Configure the MCOx pin in alternate function mode */ + GPIO_InitStruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx); + GPIO_InitStruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx); + HAL_GPIO_Init(mco_gpio_port, &GPIO_InitStruct); + + if (mcoindex == RCC_MCO1_INDEX) + { + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1SEL | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); + } + else if (mcoindex == RCC_MCO2_INDEX) + { + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7))); + } + else + { + /* Do nothing */ + } + +#endif /* HAL_GPIO_MODULE_ENABLED */ +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M NMI (Non-Mask-able Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSECSSON); +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSECSSON); +} + +/** + * @brief Returns the SYSCLK frequency + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(*) + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on CSI_VALUE(*), + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (*) CSI_VALUE is a constant defined in stm32h7rsxx_hal_conf.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSI_VALUE is a constant defined in stm32h7rsxx_hal_conf.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in stm32h7rsxx_hal_conf.h file (default value + * 24 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud rate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllp; + uint32_t pllsource; + uint32_t pllm; + uint32_t pllfracen; + uint32_t hsivalue; + float_t fracn1; + float_t pllvco; + uint32_t sysclockfreq; + uint32_t prescaler; + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else + { + /* Can't retrieve HSIDIV value */ + sysclockfreq = 0U; + } + + break; + + case RCC_SYSCLKSOURCE_STATUS_CSI: /* CSI used as system clock source */ + sysclockfreq = CSI_VALUE; + break; + + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + break; + + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) ; + pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN) >> 3)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + else + { + /* Can't retrieve HSIDIV value */ + pllvco = (float_t)0; + } + break; + + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + default: + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + } + pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U) ; + sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); + } + else + { + sysclockfreq = 0U; + } + break; + + default: + sysclockfreq = CSI_VALUE; + break; + } + + prescaler = RCC->CDCFGR & RCC_CDCFGR_CPRE; + if (prescaler >= 8U) + { + sysclockfreq = sysclockfreq >> (prescaler - RCC_CDCFGR_CPRE_3 + 1U); + } + + return sysclockfreq; +} + + +/** + * @brief Return the HCLK frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + uint32_t clock; + uint32_t prescaler; + const uint8_t AHBPrescTable[8] = {1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + + /* SysClk */ + clock = HAL_RCC_GetSysClockFreq(); + /* Bus matrix divider */ + prescaler = (RCC->BMCFGR & RCC_BMCFGR_BMPRE) >> RCC_BMCFGR_BMPRE_Pos; + if (prescaler >= 8U) + { + clock = clock >> AHBPrescTable[prescaler - 8U]; + } + return (clock); +} + +/** + * @brief Return the PCLK1 frequency. + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + uint32_t clock; + uint32_t prescaler; + /* Get HCLK source and compute PCLK1 frequency ---------------------------*/ + clock = HAL_RCC_GetHCLKFreq(); + /* APB1 prescaler */ + prescaler = (RCC->APBCFGR & RCC_APBCFGR_PPRE1) >> RCC_APBCFGR_PPRE1_Pos; + if (prescaler >= 4U) + { + clock = clock >> (prescaler - 3U); + } + return (clock); +} + +/** + * @brief Return the PCLK2 frequency. + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + uint32_t clock; + uint32_t prescaler; + /* Get HCLK source and compute PCLK2 frequency ---------------------------*/ + clock = HAL_RCC_GetHCLKFreq(); + /* APB2 prescaler */ + prescaler = (RCC->APBCFGR & RCC_APBCFGR_PPRE2) >> RCC_APBCFGR_PPRE2_Pos; + if (prescaler >= 4U) + { + clock = clock >> (prescaler - 3U); + } + return (clock); +} + +/** + * @brief Return the PCLK4 frequency. + * @note Each time PCLK4 changes, this function must be called to update the + * right PCLK4 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK4 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK4Freq(void) +{ + uint32_t clock; + uint32_t prescaler; + /* Get HCLK source and compute PCLK4 frequency ---------------------------*/ + clock = HAL_RCC_GetHCLKFreq(); + /* APB4 prescaler */ + prescaler = (RCC->APBCFGR & RCC_APBCFGR_PPRE4) >> RCC_APBCFGR_PPRE4_Pos; + if (prescaler >= 4U) + { + clock = clock >> (prescaler - 3U); + } + return (clock); +} + +/** + * @brief Return the PCLK5 frequency. + * @note Each time PCLK5 changes, this function must be called to update the + * right PCLK5 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK5 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK5Freq(void) +{ + uint32_t clock; + uint32_t prescaler; + /* Get HCLK source and compute PCLK5 frequency ---------------------------*/ + clock = HAL_RCC_GetHCLKFreq(); + /* APB5 prescaler */ + prescaler = (RCC->APBCFGR & RCC_APBCFGR_PPRE5) >> RCC_APBCFGR_PPRE5_Pos; + if (prescaler >= 4U) + { + clock = clock >> (prescaler - 3U); + } + return (clock); +} + +/** + * @brief Return the PLL1P frequency. + * @retval PLL1P frequency in Hz + */ +uint32_t HAL_RCC_GetPLL1PFreq(void) +{ + uint32_t pllp; + + /* PLL1P divider */ + pllp = ((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U; + + /* Compute VCO output frequency and return PLL1P one */ + return ((uint32_t)RCC_PLL1_GetVCOOutputFreq() / pllp); +} + +/** + * @brief Return the PLL1Q frequency. + * @retval PLL1Q frequency in Hz + */ +uint32_t HAL_RCC_GetPLL1QFreq(void) +{ + uint32_t pllq; + + /* PLL1Q divider */ + pllq = ((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVQ) >> RCC_PLL1DIVR1_DIVQ_Pos) + 1U; + + /* Compute VCO output frequency and return PLL1Q one */ + return ((uint32_t)RCC_PLL1_GetVCOOutputFreq() / pllq); +} + +/** + * @brief Return the PLL1R frequency. + * @retval PLL1R frequency in Hz + */ +uint32_t HAL_RCC_GetPLL1RFreq(void) +{ + uint32_t pllr; + + /* PLL1R divider */ + pllr = ((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVR) >> RCC_PLL1DIVR1_DIVR_Pos) + 1U; + + /* Compute VCO output frequency and return PLL1R one */ + return ((uint32_t)RCC_PLL1_GetVCOOutputFreq() / pllr); +} + +/** + * @brief Return the PLL1S frequency. + * @retval PLL1S frequency in Hz + */ +uint32_t HAL_RCC_GetPLL1SFreq(void) +{ + uint32_t plls; + + /* PLL1S divider */ + plls = ((RCC->PLL1DIVR2 & RCC_PLL1DIVR2_DIVS) >> RCC_PLL1DIVR2_DIVS_Pos) + 1U; + + /* Compute VCO output frequency and return PLL1S one */ + return ((uint32_t)RCC_PLL1_GetVCOOutputFreq() / plls); +} + +/** + * @brief Return the PLL2P frequency. + * @retval PLL2P frequency in Hz + */ +uint32_t HAL_RCC_GetPLL2PFreq(void) +{ + uint32_t pllp; + + /* PLL2P divider */ + pllp = ((RCC->PLL2DIVR1 & RCC_PLL2DIVR1_DIVP) >> RCC_PLL2DIVR1_DIVP_Pos) + 1U; + + /* Compute VCO output frequency and return PLL2P one */ + return ((uint32_t)RCC_PLL2_GetVCOOutputFreq() / pllp); +} + +/** + * @brief Return the PLL2Q frequency. + * @retval PLL2Q frequency in Hz + */ +uint32_t HAL_RCC_GetPLL2QFreq(void) +{ + uint32_t pllq; + + /* PLL2Q divider */ + pllq = ((RCC->PLL2DIVR1 & RCC_PLL2DIVR1_DIVQ) >> RCC_PLL2DIVR1_DIVQ_Pos) + 1U; + + /* Compute VCO output frequency and return PLL2Q one */ + return ((uint32_t)RCC_PLL2_GetVCOOutputFreq() / pllq); +} + +/** + * @brief Return the PLL2R frequency. + * @retval PLL2R frequency in Hz + */ +uint32_t HAL_RCC_GetPLL2RFreq(void) +{ + uint32_t pllr; + + /* PLL2R divider */ + pllr = ((RCC->PLL2DIVR1 & RCC_PLL2DIVR1_DIVR) >> RCC_PLL2DIVR1_DIVR_Pos) + 1U; + + /* Compute VCO output frequency and return PLL2R one */ + return ((uint32_t)RCC_PLL2_GetVCOOutputFreq() / pllr); +} + +/** + * @brief Return the PLL2S frequency. + * @retval PLL2S frequency in Hz + */ +uint32_t HAL_RCC_GetPLL2SFreq(void) +{ + uint32_t plls; + + /* PLL2S divider */ + plls = ((RCC->PLL2DIVR2 & RCC_PLL2DIVR2_DIVS) >> RCC_PLL2DIVR2_DIVS_Pos) + 1U; + + /* Compute VCO output frequency and return PLL2R one */ + return ((uint32_t)RCC_PLL2_GetVCOOutputFreq() / plls); +} + +/** + * @brief Return the PLL2T frequency. + * @retval PLL2T frequency in Hz + */ +uint32_t HAL_RCC_GetPLL2TFreq(void) +{ + uint32_t pllt; + + /* PLL2T divider */ + pllt = ((RCC->PLL2DIVR2 & RCC_PLL2DIVR2_DIVT) >> RCC_PLL2DIVR2_DIVT_Pos) + 1U; + + /* Compute VCO output frequency and return PLL2T one */ + return ((uint32_t)RCC_PLL2_GetVCOOutputFreq() / pllt); +} + +/** + * @brief Return the PLL3P frequency. + * @retval PLL3P frequency in Hz + */ +uint32_t HAL_RCC_GetPLL3PFreq(void) +{ + uint32_t pllp; + + /* PLL3P divider */ + pllp = ((RCC->PLL3DIVR1 & RCC_PLL3DIVR1_DIVP) >> RCC_PLL3DIVR1_DIVP_Pos) + 1U; + + /* Compute VCO output frequency and return PLL3P one */ + return ((uint32_t)RCC_PLL3_GetVCOOutputFreq() / pllp); +} + +/** + * @brief Return the PLL3Q frequency. + * @retval PLL3Q frequency in Hz + */ +uint32_t HAL_RCC_GetPLL3QFreq(void) +{ + uint32_t pllq; + + /* PLL3Q divider */ + pllq = ((RCC->PLL3DIVR1 & RCC_PLL3DIVR1_DIVQ) >> RCC_PLL3DIVR1_DIVQ_Pos) + 1U; + + /* Compute VCO output frequency and return PLL3Q one */ + return ((uint32_t)RCC_PLL3_GetVCOOutputFreq() / pllq); +} + +/** + * @brief Return the PLL3R frequency. + * @retval PLL3R frequency in Hz + */ +uint32_t HAL_RCC_GetPLL3RFreq(void) +{ + uint32_t pllr; + + /* PLL3R divider */ + pllr = ((RCC->PLL3DIVR1 & RCC_PLL3DIVR1_DIVR) >> RCC_PLL3DIVR1_DIVR_Pos) + 1U; + + /* Compute VCO output frequency and return PLL3R one */ + return ((uint32_t)RCC_PLL3_GetVCOOutputFreq() / pllr); +} + +/** + * @brief Return the PLL3S frequency. + * @retval PLL3S frequency in Hz + */ +uint32_t HAL_RCC_GetPLL3SFreq(void) +{ + uint32_t plls; + + /* PLL3S divider */ + plls = ((RCC->PLL3DIVR2 & RCC_PLL3DIVR2_DIVS) >> RCC_PLL3DIVR2_DIVS_Pos) + 1U; + + /* Compute VCO output frequency and return PLL3S one */ + return ((uint32_t)RCC_PLL3_GetVCOOutputFreq() / plls); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + + uint32_t regvalue; + uint32_t mask; + + /* Check the parameters */ + assert_param(RCC_OscInitStruct != (void *)NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; + + /* Get Backup Domain register */ + regvalue = RCC->BDCR; + + /* Get the LSE configuration -----------------------------------------------*/ + mask = (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT | RCC_BDCR_LSEON); + RCC_OscInitStruct->LSEState = (regvalue & mask); + + /* Get RCC clock control and status register */ + regvalue = RCC->CSR; + + /* Get the LSI configuration -----------------------------------------------*/ + mask = RCC_CSR_LSION; + RCC_OscInitStruct->LSIState = (regvalue & mask); + + /* Get Control register */ + regvalue = RCC->CR; + + /* Get the HSE configuration -----------------------------------------------*/ + mask = (RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSEON); + RCC_OscInitStruct->HSEState = (regvalue & mask); + + /* Get the HSI configuration -----------------------------------------------*/ + mask = RCC_CR_HSION; + RCC_OscInitStruct->HSIState = (regvalue & mask); + RCC_OscInitStruct->HSIDiv = (regvalue & RCC_CR_HSIDIV); + RCC_OscInitStruct->HSICalibrationValue = ((RCC->HSICFGR & RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); + + /* Get the HSI48 configuration ---------------------------------------------*/ + mask = RCC_CR_HSI48ON; + RCC_OscInitStruct->HSI48State = (regvalue & mask); + + /* Get the CSI configuration -----------------------------------------------*/ + mask = RCC_CR_CSION; + RCC_OscInitStruct->CSIState = (regvalue & mask); + + /* Get the PLL1 configuration -----------------------------------------------*/ + if ((regvalue & RCC_CR_PLL1ON) == RCC_CR_PLL1ON) + { + RCC_OscInitStruct->PLL1.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL1.PLLState = RCC_PLL_OFF; + } + + /* Get PLL1 configuration register */ + regvalue = RCC->PLLCKSELR; + RCC_OscInitStruct->PLL1.PLLSource = (regvalue & RCC_PLLCKSELR_PLLSRC); + RCC_OscInitStruct->PLL1.PLLM = ((regvalue & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos); + + /* Check if fractional part is enable */ + regvalue = RCC->PLLCFGR; + if ((regvalue & RCC_PLLCFGR_PLL1FRACEN) != 0x00u) + { + regvalue = (((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN) >> RCC_PLL1FRACR_FRACN_Pos)); + } + else + { + regvalue = 0; + } + RCC_OscInitStruct->PLL1.PLLFractional = regvalue; + + /* Get PLL1 dividers register */ + regvalue = RCC->PLL1DIVR1; + RCC_OscInitStruct->PLL1.PLLN = ((regvalue & RCC_PLL1DIVR1_DIVN) + 1U); + RCC_OscInitStruct->PLL1.PLLR = (((regvalue & RCC_PLL1DIVR1_DIVR) >> RCC_PLL1DIVR1_DIVR_Pos) + 1U); + RCC_OscInitStruct->PLL1.PLLP = (((regvalue & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U); + RCC_OscInitStruct->PLL1.PLLQ = (((regvalue & RCC_PLL1DIVR1_DIVQ) >> RCC_PLL1DIVR1_DIVQ_Pos) + 1U); + regvalue = RCC->PLL1DIVR2; + RCC_OscInitStruct->PLL1.PLLS = (((regvalue & RCC_PLL1DIVR2_DIVS) >> RCC_PLL1DIVR2_DIVS_Pos) + 1U); + RCC_OscInitStruct->PLL1.PLLT = 0; + + /* Get the PLL2 configuration -----------------------------------------------*/ + /* Get Control register */ + regvalue = RCC->CR; + if ((regvalue & RCC_CR_PLL2ON) == RCC_CR_PLL2ON) + { + RCC_OscInitStruct->PLL2.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL2.PLLState = RCC_PLL_OFF; + } + + /* Get PLL2 configuration register */ + regvalue = RCC->PLLCKSELR; + RCC_OscInitStruct->PLL2.PLLSource = (regvalue & RCC_PLLCKSELR_PLLSRC); + RCC_OscInitStruct->PLL2.PLLM = ((regvalue & RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos); + + /* Check if fractional part is enable */ + regvalue = RCC->PLLCFGR; + if ((regvalue & RCC_PLLCFGR_PLL2FRACEN) != 0x00u) + { + regvalue = (((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN) >> RCC_PLL2FRACR_FRACN_Pos)); + } + else + { + regvalue = 0; + } + RCC_OscInitStruct->PLL2.PLLFractional = regvalue; + + /* Get PLL2 dividers register */ + regvalue = RCC->PLL2DIVR1; + RCC_OscInitStruct->PLL2.PLLN = ((regvalue & RCC_PLL2DIVR1_DIVN) + 1U); + RCC_OscInitStruct->PLL2.PLLR = (((regvalue & RCC_PLL2DIVR1_DIVR) >> RCC_PLL2DIVR1_DIVR_Pos) + 1U); + RCC_OscInitStruct->PLL2.PLLP = (((regvalue & RCC_PLL2DIVR1_DIVP) >> RCC_PLL2DIVR1_DIVP_Pos) + 1U); + RCC_OscInitStruct->PLL2.PLLQ = (((regvalue & RCC_PLL2DIVR1_DIVQ) >> RCC_PLL2DIVR1_DIVQ_Pos) + 1U); + regvalue = RCC->PLL2DIVR2; + RCC_OscInitStruct->PLL2.PLLS = (((regvalue & RCC_PLL2DIVR2_DIVS) >> RCC_PLL2DIVR2_DIVS_Pos) + 1U); + RCC_OscInitStruct->PLL2.PLLT = (((regvalue & RCC_PLL2DIVR2_DIVT) >> RCC_PLL2DIVR2_DIVT_Pos) + 1U); + + /* Get the PLL3 configuration -----------------------------------------------*/ + /* Get Control register */ + regvalue = RCC->CR; + if ((regvalue & RCC_CR_PLL3ON) == RCC_CR_PLL3ON) + { + RCC_OscInitStruct->PLL3.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL3.PLLState = RCC_PLL_OFF; + } + + /* Get PLL3 configuration register */ + regvalue = RCC->PLLCKSELR; + RCC_OscInitStruct->PLL3.PLLSource = (regvalue & RCC_PLLCKSELR_PLLSRC); + RCC_OscInitStruct->PLL3.PLLM = ((regvalue & RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos); + + + /* Check if fractional part is enable */ + regvalue = RCC->PLLCFGR; + if ((regvalue & RCC_PLLCFGR_PLL3FRACEN) != 0x00u) + { + regvalue = (((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN) >> RCC_PLL3FRACR_FRACN_Pos)); + } + else + { + regvalue = 0; + } + RCC_OscInitStruct->PLL3.PLLFractional = regvalue; + + /* Get PLL3 dividers register */ + regvalue = RCC->PLL3DIVR1; + RCC_OscInitStruct->PLL3.PLLN = ((regvalue & RCC_PLL3DIVR1_DIVN) + 1U); + RCC_OscInitStruct->PLL3.PLLR = (((regvalue & RCC_PLL3DIVR1_DIVR) >> RCC_PLL3DIVR1_DIVR_Pos) + 1U); + RCC_OscInitStruct->PLL3.PLLP = (((regvalue & RCC_PLL3DIVR1_DIVP) >> RCC_PLL3DIVR1_DIVP_Pos) + 1U); + RCC_OscInitStruct->PLL3.PLLQ = (((regvalue & RCC_PLL3DIVR1_DIVQ) >> RCC_PLL3DIVR1_DIVQ_Pos) + 1U); + regvalue = RCC->PLL3DIVR2; + RCC_OscInitStruct->PLL3.PLLS = (((regvalue & RCC_PLL3DIVR2_DIVS) >> RCC_PLL3DIVR2_DIVS_Pos) + 1U); + RCC_OscInitStruct->PLL3.PLLT = 0; + +} + +/** + * @brief Configures the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency: Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | \ + RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | \ + RCC_CLOCKTYPE_PCLK4 | RCC_CLOCKTYPE_PCLK5; + + /* Get the SYSCLK source ---------------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW); + + /* Get the SYSCLK configuration---------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKDivider = READ_BIT(RCC->CDCFGR, RCC_CDCFGR_CPRE); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->BMCFGR, RCC_BMCFGR_BMPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->APBCFGR, RCC_APBCFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = READ_BIT(RCC->APBCFGR, RCC_APBCFGR_PPRE2); + + /* Get the APB4 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB4CLKDivider = READ_BIT(RCC->APBCFGR, RCC_APBCFGR_PPRE4); + + /* Get the APB5 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB5CLKDivider = READ_BIT(RCC->APBCFGR, RCC_APBCFGR_PPRE5); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = __HAL_FLASH_GET_LATENCY(); +} + +/** + * @brief This function handles the RCC HSE CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC HSECSSF interrupt flag */ + if (__HAL_RCC_GET_IT(RCC_IT_HSECSS)) + { + /* Clear RCC HSE CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_HSECSS); + + /* RCC HSE Clock Security System interrupt user callback */ + HAL_RCC_HSECSSCallback(); + } +} + +/** + * @brief RCC HSE Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_HSECSSCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RCC_HSECSSCallback could be implemented in the user file + */ +} + +/** + * @brief RCC LSE Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_LSECSSCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RCC_LSECSSCallback could be implemented in the user file + */ +} + +/** + * @brief Get and clear reset flags + * @note Once reset flags are retrieved, this API is clearing them in order + * to isolate next reset reason. + * @retval can be a combination of @ref RCC_Reset_Flag + */ +uint32_t HAL_RCC_GetResetSource(void) +{ + uint32_t reset; + + /* Get all reset flags */ + reset = RCC->RSR & RCC_RESET_FLAG_ALL; + + /* Clear Reset flags */ + RCC->RSR |= RCC_RSR_RMVF; + + return reset; +} + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup RCC_Private_Functions + * @{ + */ + +/** + * @brief Configure the requested PLL + * @param PLLnumber PLL number to configure + * @param pPLLInit Pointer to an RCC_PLLInitTypeDef structure that + * contains the configuration parameters. + * @note PLL is temporary disabled to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_PLL_Config(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit) +{ + __IO uint32_t *p_rcc_pll_divr1_reg; + __IO uint32_t *p_rcc_pll_divr2_reg; + __IO uint32_t *p_rcc_pll_fracr_reg; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t tickstart; + uint32_t pllsrc; + uint32_t pllvco; + + p_rcc_pll_divr1_reg = &(RCC->PLL1DIVR1) + (((uint32_t)0x02) * PLLnumber); + p_rcc_pll_divr2_reg = &(RCC->PLL1DIVR2) + (((uint32_t)0x01) * PLLnumber); + + /* Disable the post-dividers */ + CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLL1PEN | RCC_PLLCFGR_PLL1QEN | RCC_PLLCFGR_PLL1REN | RCC_PLLCFGR_PLL1SEN | + 0x00000200U) /* Hardcoded because no definition in CMSIS */ + << ((RCC_PLLCFGR_PLL2PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos)*PLLnumber)); + + /* Ensure PLLx is disabled */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON << ((RCC_CR_PLL2ON_Pos - RCC_CR_PLL1ON_Pos)*PLLnumber)); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLx is disabled */ + while (READ_BIT(RCC->CR, (RCC_CR_PLL1RDY << ((RCC_CR_PLL2RDY_Pos - RCC_CR_PLL1RDY_Pos)*PLLnumber))) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + if (pPLLInit->PLLState == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(pPLLInit->PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(pPLLInit->PLLM)); + assert_param(IS_RCC_PLLN_VALUE(pPLLInit->PLLN)); + assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(pPLLInit->PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(pPLLInit->PLLR)); + assert_param(IS_RCC_PLLS_VALUE(pPLLInit->PLLS)); + assert_param(IS_RCC_PLLT_VALUE(pPLLInit->PLLT)); + + pllsrc = pPLLInit->PLLSource; + + /* Compute VCO input frequency and define range accordingly. First check clock source frequency */ + if (pllsrc == RCC_PLLSOURCE_HSI) + { + /* Clock source is HSI or HSI/HSIDIV */ + pllvco = HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos); + } + else if (pllsrc == RCC_PLLSOURCE_HSE) + { + /* Clock source is HSE */ + pllvco = HSE_VALUE; + } + else + { + /* Clock source is CSI */ + pllvco = CSI_VALUE; + } + + /* Compute VCO input frequency depending on M divider */ + pllvco = (pllvco / pPLLInit->PLLM); + assert_param(IS_RCC_PLL_VCOINPUTFREQ(pllvco)); + + if (pllvco >= RCC_PLL_INPUTRANGE2_FREQMAX) + { + pllvco = RCC_PLL_VCOINPUT_RANGE3 | RCC_PLL_VCO_HIGH; + } + else if (pllvco >= RCC_PLL_INPUTRANGE1_FREQMAX) + { + pllvco = RCC_PLL_VCOINPUT_RANGE2 | RCC_PLL_VCO_HIGH; + } + else if (pllvco >= RCC_PLL_INPUTRANGE0_FREQMAX) + { + pllvco = RCC_PLL_VCOINPUT_RANGE1 | RCC_PLL_VCO_HIGH; + } + else + { + pllvco = RCC_PLL_VCOINPUT_RANGE0 | RCC_PLL_VCO_LOW; + } + + pllvco = (pllvco << ((RCC_PLLCFGR_PLL2RGE_Pos - RCC_PLLCFGR_PLL1RGE_Pos) * PLLnumber)); + + /* Configure PLL source and PLLM divider */ + MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | (RCC_PLLCKSELR_DIVM1 << ((RCC_PLLCKSELR_DIVM2_Pos - RCC_PLLCKSELR_DIVM1_Pos)*PLLnumber))), \ + pllsrc | (pPLLInit->PLLM << (RCC_PLLCKSELR_DIVM1_Pos + ((RCC_PLLCKSELR_DIVM2_Pos - RCC_PLLCKSELR_DIVM1_Pos)*PLLnumber)))); + + if ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) != pllsrc) + { + /* There is another PLL activated with another source */ + return HAL_ERROR; + } + + /* Configure VCO input range, VCO selection and clear FRACEN */ + MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLL1RGE | RCC_PLLCFGR_PLL1VCOSEL | RCC_PLLCFGR_PLL1FRACEN) << (((RCC_PLLCFGR_PLL2RGE_Pos - RCC_PLLCFGR_PLL1RGE_Pos)*PLLnumber)), \ + pllvco); + + /* Configure PLLN, PLLP, PLLQ, PLLR, PLLS and PLLT dividers */ + WRITE_REG(*p_rcc_pll_divr1_reg, ((pPLLInit->PLLN - 1U) | + ((pPLLInit->PLLP - 1U) << RCC_PLL1DIVR1_DIVP_Pos) | + ((pPLLInit->PLLQ - 1U) << RCC_PLL1DIVR1_DIVQ_Pos) | + ((pPLLInit->PLLR - 1U) << RCC_PLL1DIVR1_DIVR_Pos))); + WRITE_REG(*p_rcc_pll_divr2_reg, ((pPLLInit->PLLS - 1U) | + ((pPLLInit->PLLT - 1U) << RCC_PLL2DIVR2_DIVT_Pos))); + + if (PLLnumber == RCC_PLL1_CONFIG) + { + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1PEN); + } + + if (pPLLInit->PLLFractional != 0U) + { + assert_param(IS_RCC_PLLFRACN_VALUE(pPLLInit->PLLFractional)); + + p_rcc_pll_fracr_reg = &(RCC->PLL1FRACR) + (((uint32_t)0x02) * PLLnumber); + + /* Configure PLLFRACN */ + MODIFY_REG(*p_rcc_pll_fracr_reg, RCC_PLL1FRACR_FRACN, pPLLInit->PLLFractional << RCC_PLL1FRACR_FRACN_Pos); + + /* Enable PLLFRACLE */ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN << ((RCC_PLLCFGR_PLL2FRACEN_Pos - RCC_PLLCFGR_PLL1FRACEN_Pos)*PLLnumber)); + } + + /* Enable the PLLx */ + SET_BIT(RCC->CR, RCC_CR_PLL1ON << ((RCC_CR_PLL2ON_Pos - RCC_CR_PLL1ON_Pos)*PLLnumber)); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLx is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY << ((RCC_CR_PLL2RDY_Pos - RCC_CR_PLL1RDY_Pos)*PLLnumber)) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable outputs to save power when PLLx is off */ + MODIFY_REG(RCC->PLLCKSELR, ((RCC_PLLCKSELR_DIVM1 << (RCC_PLLCKSELR_DIVM1_Pos + ((RCC_PLLCKSELR_DIVM2_Pos - RCC_PLLCKSELR_DIVM1_Pos)*PLLnumber))) + | RCC_PLLCKSELR_PLLSRC), RCC_PLLSOURCE_NONE); + } + + return ret; +} + +/** + * @brief Compute PLL1 VCO output frequency + * @retval Value of PLL1 VCO output frequency + */ +static uint32_t RCC_PLL1_GetVCOOutputFreq(void) +{ + uint32_t tmpreg1; + uint32_t tmpreg2; + uint32_t pllsrc; + uint32_t pllm; + uint32_t plln; + uint32_t pllfracn; + float_t frequency; + + /* Get PLL1 CKSELR and DIVR register values */ + tmpreg1 = RCC->PLLCKSELR; + tmpreg2 = RCC->PLL1DIVR1; + + /* Retrieve PLL1 multiplication factor and divider */ + pllm = (tmpreg1 & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos; + plln = (tmpreg2 & RCC_PLL1DIVR1_DIVN) + 1U; + + if (pllm == 0U) + { + /* Prescaler disabled */ + return 0U; + } + + /* Check if fractional part is enable */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) != 0U) + { + pllfracn = (RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN) >> RCC_PLL1FRACR_FRACN_Pos; + } + else + { + pllfracn = 0U; + } + + /* determine PLL source */ + switch (tmpreg1 & RCC_PLLCKSELR_PLLSRC) + { + /* HSI used as PLL1 clock source */ + case RCC_PLLSOURCE_HSI: + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + pllsrc = HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos); + } + else + { + /* Can't retrieve HSIDIV value */ + pllsrc = 0U; + } + break; + + /* HSE used as PLL1 clock source */ + case RCC_PLLSOURCE_HSE: + pllsrc = HSE_VALUE; + break; + + /* CSI used as PLL1 clock source */ + case RCC_PLLSOURCE_CSI: + pllsrc = CSI_VALUE; + break; + + default: + pllsrc = 0U; + break; + } + + /* Compute VCO output frequency */ + frequency = ((float_t)pllsrc / (float_t)pllm) * ((float_t)plln + ((float_t)pllfracn / (float_t)0x2000U)); + + return (uint32_t)frequency; +} + +/** + * @brief Compute PLL2 VCO output frequency + * @retval Value of PLL2 VCO output frequency + */ +static uint32_t RCC_PLL2_GetVCOOutputFreq(void) +{ + uint32_t tmpreg1; + uint32_t tmpreg2; + uint32_t pllsrc; + uint32_t pllm; + uint32_t plln; + uint32_t pllfracn; + float_t frequency; + + /* Get PLL2 CKSELR and DIVR register values */ + tmpreg1 = RCC->PLLCKSELR; + tmpreg2 = RCC->PLL2DIVR1; + + /* Retrieve PLL2 multiplication factor and divider */ + pllm = (tmpreg1 & RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos; + plln = (tmpreg2 & RCC_PLL2DIVR1_DIVN) + 1U; + + if (pllm == 0U) + { + /* Prescaler disabled */ + return 0U; + } + + /* Check if fractional part is enable */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) != 0U) + { + pllfracn = (RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN) >> RCC_PLL2FRACR_FRACN_Pos; + } + else + { + pllfracn = 0U; + } + + /* determine PLL source */ + switch (tmpreg1 & RCC_PLLCKSELR_PLLSRC) + { + /* HSI used as PLL2 clock source */ + case RCC_PLLSOURCE_HSI: + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + pllsrc = HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos); + } + else + { + /* Can't retrieve HSIDIV value */ + pllsrc = 0U; + } + break; + + /* HSE used as PLL2 clock source */ + case RCC_PLLSOURCE_HSE: + pllsrc = HSE_VALUE; + break; + + /* CSI used as PLL2 clock source */ + case RCC_PLLSOURCE_CSI: + pllsrc = CSI_VALUE; + break; + + default: + pllsrc = 0U; + break; + } + + /* Compute VCO output frequency */ + frequency = ((float_t)pllsrc / (float_t)pllm) * ((float_t)plln + ((float_t)pllfracn / (float_t)0x2000U)); + + return (uint32_t)frequency; +} + +/** + * @brief Compute PLL3 VCO output frequency + * @retval Value of PLL3 VCO output frequency + */ +static uint32_t RCC_PLL3_GetVCOOutputFreq(void) +{ + uint32_t tmpreg1; + uint32_t tmpreg2; + uint32_t pllsrc; + uint32_t pllm; + uint32_t plln; + uint32_t pllfracn; + float_t frequency; + + /* Get PLL3 CKSELR and DIVR register values */ + tmpreg1 = RCC->PLLCKSELR; + tmpreg2 = RCC->PLL3DIVR1; + + /* Retrieve PLL3 multiplication factor and divider */ + pllm = (tmpreg1 & RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos; + plln = (tmpreg2 & RCC_PLL3DIVR1_DIVN) + 1U; + + if (pllm == 0U) + { + /* Prescaler disabled */ + return 0U; + } + + /* Check if fractional part is enable */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) != 0U) + { + pllfracn = (RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN) >> RCC_PLL3FRACR_FRACN_Pos; + } + else + { + pllfracn = 0U; + } + + /* determine PLL source */ + switch (tmpreg1 & RCC_PLLCKSELR_PLLSRC) + { + /* HSI used as PLL3 clock source */ + case RCC_PLLSOURCE_HSI: + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + pllsrc = HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos); + } + else + { + /* Can't retrieve HSIDIV value */ + pllsrc = 0U; + } + break; + + /* HSE used as PLL3 clock source */ + case RCC_PLLSOURCE_HSE: + pllsrc = HSE_VALUE; + break; + + /* CSI used as PLL3 clock source */ + case RCC_PLLSOURCE_CSI: + pllsrc = CSI_VALUE; + break; + + default: + pllsrc = 0U; + break; + } + + /* Compute VCO output frequency */ + frequency = ((float_t)pllsrc / (float_t)pllm) * ((float_t)plln + ((float_t)pllfracn / (float_t)0x2000U)); + + return (uint32_t)frequency; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* HAL_RCC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rcc_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rcc_ex.c new file mode 100644 index 00000000000..c2d43983c59 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rcc_ex.c @@ -0,0 +1,3242 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RCCEx_Private_defines RCCEx Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCCEx_Private_Functions RCCEx Private Functions + * @{ + */ +static uint32_t RCC_GetCLKPFreq(void); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register are set to their reset values. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks (SDMMC12, CKPER, FMC, XSPI1, XSPI2, ADC, ADF1, CEC, FDCAN, I2C1/I3C1, + * I2C2, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, SAI1, + * SAI2, SPDIF, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SAI1, USART1, USART2, + * USART3, UART4, UART5, UART7, UART8, ETH1, USB and RTC). + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tmpreg; + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- RTC configuration -------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + /* check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* As the RTC clock source selection can be changed only if the Backup Domain is reset */ + /* reset the Backup domain only if the RTC Clock source selection is modified from default reset value */ + tmpreg = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); + + if ((tmpreg != RCC_RTCCLKSOURCE_DISABLE) && (tmpreg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + + /* Read back to check Backup domain enabled */ + if (READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U) + { + ret = HAL_ERROR; + } + else + { + /* Store the content of BDCR register before the reset of Backup Domain */ + /* excepted the RTC clock source selection that will be changed */ + tmpreg = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the content of BDCR register */ + WRITE_REG(RCC->BDCR, tmpreg); + } + } + + if (ret == HAL_OK) + { + /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ + if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + } + + if (ret == HAL_OK) + { + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + __HAL_RCC_RTC_ENABLE(); + } + else + { + /* set overall return value */ + status = ret; + } + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- FMC configuration -------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) + { + /* Check the parameters */ + assert_param(IS_RCC_FMCCLKSOURCE(PeriphClkInit->FmcClockSelection)); + + switch (PeriphClkInit->FmcClockSelection) + { + case RCC_FMCCLKSOURCE_HCLK: /* HCLK clock selected as FMC kernel peripheral clock */ + break; + + case RCC_FMCCLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for FMC kernel */ + /* Enable FMC kernel clock output generated form System PLL . */ + __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK); + /* FMC kernel clock source configuration done later after clock selection check */ + break; + + case RCC_FMCCLKSOURCE_PLL2R: /* PLL2_R is used as clock source for FMC kernel */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_RCLK); + /* FMC kernel clock source configuration done later after clock selection check */ + break; + + case RCC_FMCCLKSOURCE_HSI: /* HSI oscillator is used as clock source for FMC kernel */ + /* FMC kernel clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of FMC kernel clock*/ + __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- XSPI1 clock source configuration ----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_XSPI1) == RCC_PERIPHCLK_XSPI1) + { + /* Check the parameters */ + assert_param(IS_RCC_XSPI1CLKSOURCE(PeriphClkInit->Xspi1ClockSelection)); + + switch (PeriphClkInit->Xspi1ClockSelection) + { + case RCC_XSPI1CLKSOURCE_HCLK: /* HCLK is used as clock source for Xspi1 */ + /* Nothing to do */ + break; + + case RCC_XSPI1CLKSOURCE_PLL2S: /* PLL2_S is used as clock source for Xspi1 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_SCLK); + /* XSPI1 clock source configuration done later after clock selection check */ + break; + + case RCC_XSPI1CLKSOURCE_PLL2T: /* PLL2_T is used as clock source for Xspi1 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_TCLK); + /* XSPI1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Configure the XSPI1 clock source */ + __HAL_RCC_XSPI1_CONFIG(PeriphClkInit->Xspi1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- XSPI2 clock source configuration ----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_XSPI2) == RCC_PERIPHCLK_XSPI2) + { + /* Check the parameters */ + assert_param(IS_RCC_XSPI2CLKSOURCE(PeriphClkInit->Xspi2ClockSelection)); + + switch (PeriphClkInit->Xspi2ClockSelection) + { + case RCC_XSPI2CLKSOURCE_HCLK: /* HCLK is used as clock source for Xspi2 */ + /* Nothing to do */ + break; + + case RCC_XSPI2CLKSOURCE_PLL2S: /* PLL2_S is used as clock source for Xspi2 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_SCLK); + /* XSPI2 clock source configuration done later after clock selection check */ + break; + + case RCC_XSPI2CLKSOURCE_PLL2T: /* PLL2_T is used as clock source for Xspi2 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_TCLK); + /* XSPI2 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Configure the XSPI2 clock source */ + __HAL_RCC_XSPI2_CONFIG(PeriphClkInit->Xspi2ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------------ CKPER configuration --------------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) + { + /* Check the parameters */ + assert_param(IS_RCC_CKPERCLKSOURCE(PeriphClkInit->CkperClockSelection)); + + /* Configure the CKPER clock source */ + __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); + } + + /*------------------------------------- SDMMC12 Configuration ------------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SDMMC12) == RCC_PERIPHCLK_SDMMC12) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC12CLKSOURCE(PeriphClkInit->Sdmmc12ClockSelection)); + + switch (PeriphClkInit->Sdmmc12ClockSelection) + { + case RCC_SDMMC12CLKSOURCE_PLL2S: /* PLL2_S is used as clock source for SDMMC12 kernel */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_SCLK); + /* SDMMC12 kernel clock source configuration done later after clock selection check */ + break; + + case RCC_SDMMC12CLKSOURCE_PLL2T: /* PLL2_T is used as clock source for SDMMC12 kernel */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_TCLK); + /* SDMMC12 kernel clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SDMMC12 clock*/ + __HAL_RCC_SDMMC12_CONFIG(PeriphClkInit->Sdmmc12ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- ADC configuration -------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + { + /* Check the parameters */ + assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); + + switch (PeriphClkInit->AdcClockSelection) + { + + case RCC_ADCCLKSOURCE_PLL2P: /* PLL2_P is used as clock source for ADC */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); + /* ADC clock source configuration done later after clock selection check */ + break; + + case RCC_ADCCLKSOURCE_PLL3R: /* PLL3_R is used as clock source for ADC */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); + /* ADC clock source configuration done later after clock selection check */ + break; + + case RCC_ADCCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ + /* ADC clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of ADC clock*/ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- ADF1 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1) + { + /* Check the parameters */ + assert_param(IS_RCC_ADF1CLKSOURCE(PeriphClkInit->Adf1ClockSelection)); + + switch (PeriphClkInit->Adf1ClockSelection) + { + case RCC_ADF1CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for ADF1 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); + /* ADF1 clock source configuration done later after clock selection check */ + break; + + case RCC_ADF1CLKSOURCE_PLL3P: /* PLL3_P is used as clock source for ADF1 */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_PCLK); + /* ADF1 clock source configuration done later after clock selection check */ + break; + + case RCC_ADF1CLKSOURCE_HCLK: /* HCLK is used as clock source for ADF1 */ + case RCC_ADF1CLKSOURCE_PIN: /* External I2S_CKIN is used as clock source for ADF1 */ + case RCC_ADF1CLKSOURCE_CSI: /* CSI is used as clock source for ADF1 */ + case RCC_ADF1CLKSOURCE_HSI: /* HSI is used as clock source for ADF1 */ + /* ADF1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of ADF1 clock*/ + __HAL_RCC_ADF1_CONFIG(PeriphClkInit->Adf1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------- CEC configuration ---------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } + + /*---------------------- ETH1 REF configuration --------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1REF) == RCC_PERIPHCLK_ETH1REF) + { + /* Check the parameters */ + assert_param(IS_RCC_ETH1REFCLKSOURCE(PeriphClkInit->Eth1RefClockSelection)); + + /* Configure the ETH1 REF clock source */ + __HAL_RCC_ETH1REF_CONFIG(PeriphClkInit->Eth1RefClockSelection); + } + + /*---------------------- ETH1PHY configuration --------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1PHY) == RCC_PERIPHCLK_ETH1PHY) + { + /* Check the parameters */ + assert_param(IS_RCC_ETH1PHYCLKSOURCE(PeriphClkInit->Eth1PhyClockSelection)); + + switch (PeriphClkInit->Eth1PhyClockSelection) + { + case RCC_ETH1PHYCLKSOURCE_HSE: /* HSE is used as clock source for ETH PHY */ + /* ETH PHY clock source configuration done later after clock selection check */ + break; + + case RCC_ETH1PHYCLKSOURCE_PLL3S: /* PLL3_S is used as clock source for ETH PHY */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_SCLK); + /* ETH PHY clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of ETH PHY clock*/ + __HAL_RCC_ETH1PHY_CONFIG(PeriphClkInit->Eth1PhyClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------- FDCAN configuration -------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) + { + /* Check the parameters */ + assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection)); + + switch (PeriphClkInit->FdcanClockSelection) + { + case RCC_FDCANCLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for FDCAN kernel */ + /* Enable FDCAN Clock output generated form System PLL . */ + __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK); + /* FDCAN clock source configuration done later after clock selection check */ + break; + + case RCC_FDCANCLKSOURCE_PLL2P: /* PLL2_P is used as clock source for FDCAN kernel */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); + /* FDCAN clock source configuration done later after clock selection check */ + break; + + case RCC_FDCANCLKSOURCE_HSE: /* HSE is used as clock source for FDCAN kernel */ + /* FDCAN clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of FDCAN clock*/ + __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------ I2C1/I3C1 Configuration ------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C1_I3C1) == RCC_PERIPHCLK_I2C1_I3C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1_I3C1CLKSOURCE(PeriphClkInit->I2c1_I3c1ClockSelection)); + + switch (PeriphClkInit->I2c1_I3c1ClockSelection) + { + case RCC_I2C1_I3C1CLKSOURCE_PLL3R: /* PLL3_R is used as clock source for I2C1/I3C1*/ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); + /* I2C1/I3C1 clock source configuration done later after clock selection check */ + break; + + case RCC_I2C1_I3C1CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I2C1/I3C1*/ + case RCC_I2C1_I3C1CLKSOURCE_HSI: /* HSI is used as clock source for I2C1/I3C1*/ + case RCC_I2C1_I3C1CLKSOURCE_CSI: /* CSI is used as clock source for I2C1/I3C1*/ + /* I2C1/I3C1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of I2C1/I3C1 clock*/ + __HAL_RCC_I2C1_I3C1_CONFIG(PeriphClkInit->I2c1_I3c1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------ I2C2/I2C3 Configuration -------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C23) == RCC_PERIPHCLK_I2C23) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C23CLKSOURCE(PeriphClkInit->I2c23ClockSelection)); + + switch (PeriphClkInit->I2c23ClockSelection) + { + case RCC_I2C23CLKSOURCE_PLL3R: /* PLL3_R is used as clock source for I2C2/I2C3 */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); + /* I2C2/I2C3 clock source configuration done later after clock selection check */ + break; + + case RCC_I2C23CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I2C2/I2C3 */ + case RCC_I2C23CLKSOURCE_HSI: /* HSI is used as clock source for I2C2/I2C3 */ + case RCC_I2C23CLKSOURCE_CSI: /* CSI is used as clock source for I2C2/I2C3 */ + /* I2C2/I2C3 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of I2C2/I2C3 clock*/ + __HAL_RCC_I2C23_CONFIG(PeriphClkInit->I2c23ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- LPTIM1 configuration -------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + + switch (PeriphClkInit->Lptim1ClockSelection) + { + case RCC_LPTIM1CLKSOURCE_PCLK1: /* PCLK1 as clock source for LPTIM1 */ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for LPTIM1 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_PLL3R: /* PLL3_R is used as clock source for LPTIM1 */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_LSE: + /* External low speed OSC clock is used as clock source for LPTIM1 */ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as clock source for LPTIM1 */ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as clock source for LPTIM1 */ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM1 clock*/ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- LPTIM2/LPTIM3 configuration -----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM23) == RCC_PERIPHCLK_LPTIM23) + { + switch (PeriphClkInit->Lptim23ClockSelection) + { + case RCC_LPTIM23CLKSOURCE_PCLK4: /* PCLK4 as clock source for LPTIM2/LPTIM3 */ + /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM23CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for LPTIM2/LPTIM3 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); + /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM23CLKSOURCE_PLL3R: /* PLL3_R is used as clock source for LPTIM2/LPTIM3 */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); + /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM23CLKSOURCE_LSE: + /* External low speed OSC clock is used as clock source for LPTIM2/LPTIM3 */ + /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM23CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as clock source for LPTIM2/LPTIM3 */ + /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM23CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ + /* LPTIM2/LPTIM3 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM2/LPTIM3 clock*/ + __HAL_RCC_LPTIM23_CONFIG(PeriphClkInit->Lptim23ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- LPTIM4/LPTIM5 configuration -----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM45) == RCC_PERIPHCLK_LPTIM45) + { + switch (PeriphClkInit->Lptim45ClockSelection) + { + case RCC_LPTIM45CLKSOURCE_PCLK4: /* PCLK4 as clock source for LPTIM4/LPTIM5 */ + /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM45CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM4/LPTIM5 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); + /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM45CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM4/LPTIM5 */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); + /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM45CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM4/LPTIM5 clock */ + /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM45CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM4/LPTIM5 clock */ + /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM45CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM4/LPTIM5 clock */ + /* LPTIM4/LPTIM5 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM4/LPTIM5 clock */ + __HAL_RCC_LPTIM45_CONFIG(PeriphClkInit->Lptim45ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- LPUART1 Configuration -------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + + switch (PeriphClkInit->Lpuart1ClockSelection) + { + case RCC_LPUART1CLKSOURCE_PCLK4: /* PCLK4 selected as clock source for LPUART1 */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_PLL2Q: /* PLL2_Q is used as clock source for LPUART1 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_QCLK); + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for LPUART1 */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK); + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_LSE: + /* LSE, oscillator is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPUART1 clock */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- LTDC Configuration ----------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + { + /* LTDC internally connected to PLL3_R output clock */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); + } + + /*---------------------------- PSSI configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PSSI) == RCC_PERIPHCLK_PSSI) + { + /* Check the parameters */ + assert_param(IS_RCC_PSSICLKSOURCE(PeriphClkInit->PssiClockSelection)); + + switch (PeriphClkInit->PssiClockSelection) + { + case RCC_PSSICLKSOURCE_PLL3R: /* PLL3_R is used as clock source for PSSI */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); + /* PSSI clock source configuration done later after clock selection check */ + break; + + case RCC_PSSICLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of PSSI clock */ + /* PSSI clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of PSSI clock*/ + __HAL_RCC_PSSI_CONFIG(PeriphClkInit->PssiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SAI1 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + switch (PeriphClkInit->Sai1ClockSelection) + { + case RCC_SAI1CLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for SAI1 */ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK); + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for SAI1 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PLL3P: /* PLL3_P is used as clock source for SAI1 */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_PCLK); + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI1 clock*/ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SAI2 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + switch (PeriphClkInit->Sai2ClockSelection) + { + case RCC_SAI2CLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for SAI2 */ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK); + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for SAI2 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2CLKSOURCE_PLL3P: /* PLL3_P is used as clock source for SAI2 */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_PCLK); + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock */ + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2CLKSOURCE_SPDIF: /* SPDIF clock is used as source of SAI2 clock */ + /* SAI2 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI2 clock*/ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SPDIFRX configuration -------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + { + /* Check the parameters */ + assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifrxClockSelection)); + + switch (PeriphClkInit->SpdifrxClockSelection) + { + case RCC_SPDIFRXCLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for SPDIFRX */ + /* Enable PLL1Q Clock output generated form System PLL . */ + __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK); + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + case RCC_SPDIFRXCLKSOURCE_PLL2R: /* PLL2_R is used as clock source for SPDIFRX */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_RCLK); + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + case RCC_SPDIFRXCLKSOURCE_PLL3R: /* PLL3_R is used as clock source for SPDIFRX */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_RCLK); + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + case RCC_SPDIFRXCLKSOURCE_HSI: + /* Internal OSC clock is used as source of SPDIFRX clock*/ + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPDIFRX clock */ + __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SPI1 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1) + { + /* Check the parameters */ + assert_param(IS_RCC_SPI1CLKSOURCE(PeriphClkInit->Spi1ClockSelection)); + + switch (PeriphClkInit->Spi1ClockSelection) + { + case RCC_SPI1CLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for SPI1 */ + /* Enable SPI Clock output generated form System PLL . */ + __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK); + /* SPI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI1CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for SPI1 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); + /* SPI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI1CLKSOURCE_PLL3P: /* PLL3_P is used as clock source for SPI1 */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_PCLK); + /* SPI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI1CLKSOURCE_PIN: /* External I2S_CKIN is used as clock source for SPI1 */ + /* SPI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI1CLKSOURCE_CLKP: /* HSI, HSE, or CSI oscillator is used as source of SPI1 clock */ + /* SPI1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI1 clock*/ + __HAL_RCC_SPI1_CONFIG(PeriphClkInit->Spi1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SPI2/SPI3 configuration ---------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI23) == RCC_PERIPHCLK_SPI23) + { + /* Check the parameters */ + assert_param(IS_RCC_SPI23CLKSOURCE(PeriphClkInit->Spi23ClockSelection)); + + switch (PeriphClkInit->Spi23ClockSelection) + { + case RCC_SPI23CLKSOURCE_PLL1Q: /* PLL1_Q is used as clock source for SPI2/SPI3 */ + /* Enable SPI Clock output generated form System PLL . */ + __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL_QCLK); + /* SPI2/SPI3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI23CLKSOURCE_PLL2P: /* PLL2_P is used as clock source for SPI2/SPI3 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_PCLK); + /* SPI2/SPI3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI23CLKSOURCE_PLL3P: /* PLL3_P is used as clock source for SPI2/SPI3 */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_PCLK); + /* SPI2/SPI3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI23CLKSOURCE_PIN: /* External clock I2S_CKIN is used as clock source for SPI2/SPI3 */ + /* SPI2/SPI3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI23CLKSOURCE_CLKP: /* HSI, HSE, or CSI oscillator is used as source of SPI2/SPI3 clock */ + /* SPI2/SPI3 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI2/SPI3 clock*/ + __HAL_RCC_SPI23_CONFIG(PeriphClkInit->Spi23ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SPI4/5 configuration -------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) + { + /* Check the parameters */ + assert_param(IS_RCC_SPI45CLKSOURCE(PeriphClkInit->Spi45ClockSelection)); + + switch (PeriphClkInit->Spi45ClockSelection) + { + case RCC_SPI45CLKSOURCE_PCLK2: /* PCLK2 as clock source for SPI4/SPI5 */ + /* SPI4/SPI5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_PLL2Q: /* PLL2_Q is used as clock source for SPI4/SPI5 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_QCLK); + /* SPI4/SPI5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for SPI4/SPI5 */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK); + /* SPI4/SPI5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_HSI: /* HSI oscillator clock is used as source of SPI4/SPI5 */ + /* SPI4/SPI5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_CSI: /* CSI oscillator clock is used as source of SPI4/SPI5 */ + /* SPI4/SPI5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_HSE: /* HSE oscillator clock is used as source of SPI4/SPI5 */ + /* SPI4/SPI5 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI4/SPI5 clock */ + __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SPI6 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) + { + /* Check the parameters */ + assert_param(IS_RCC_SPI6CLKSOURCE(PeriphClkInit->Spi6ClockSelection)); + + switch (PeriphClkInit->Spi6ClockSelection) + { + case RCC_SPI6CLKSOURCE_PCLK4: /* PCLK4 as clock source for SPI6 */ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_PLL2Q: /* PLL2_Q is used as clock source for SPI6 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_QCLK); + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for SPI6 */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK); + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_HSI: /* HSI oscillator clock is used as source for SPI6 */ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_CSI: /* CSI oscillator clock is used as source for SPI6 */ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_HSE: /* HSE oscillator is used as source for SPI6 */ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI6 clock*/ + __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- USART1 configuration --------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + switch (PeriphClkInit->Usart1ClockSelection) + { + case RCC_USART1CLKSOURCE_PCLK2: /* PCLK2 as clock source for USART1 */ + /* USART1 clock source configuration done later after clock selection check */ + break; + + case RCC_USART1CLKSOURCE_PLL2Q: /* PLL2_Q is used as clock source for USART1 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_QCLK); + /* USART1 clock source configuration done later after clock selection check */ + break; + + case RCC_USART1CLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for USART1 */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK); + /* USART1 clock source configuration done later after clock selection check */ + break; + + case RCC_USART1CLKSOURCE_HSI: /* HSI oscillator clock is used as source for USART1 */ + /* USART1 clock source configuration done later after clock selection check */ + break; + + case RCC_USART1CLKSOURCE_CSI: /* CSI oscillator clock is used as source for USART1 */ + /* USART1 clock source configuration done later after clock selection check */ + break; + + case RCC_USART1CLKSOURCE_LSE: /* LSE oscillator is used as source for USART1 */ + /* USART1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART1 clock */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------- USART2/USART3/UART4/UART5/UART7/UART8 Configuration --------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) + { + /* Check the parameters */ + assert_param(IS_RCC_USART234578CLKSOURCE(PeriphClkInit->Usart234578ClockSelection)); + + switch (PeriphClkInit->Usart234578ClockSelection) + { + case RCC_USART234578CLKSOURCE_PCLK1: /* PCLK1 as clock source for USART2/USART3/UART4/UART5/UART7/UART8 */ + /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_PLL2Q: /* PLL2_Q is used as clock source for USART2/USART3/UART4/UART5/UART7/UART8 */ + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL_QCLK); + /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for USART2/USART3/UART4/UART5/UART7/UART8 */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK); + /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of USART2/USART3/UART4/UART5/UART7/UART8 clock */ + /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of USART2/USART3/UART4/UART5/UART7/UART8 clock */ + /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_LSE: + /* LSE, oscillator is used as source of USART2/USART3/UART4/UART5/UART7/UART8 clock */ + /* USART2/USART3/UART4/UART5/UART7/UART8 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART2/USART3/UART4/UART5/UART7/UART8 clock */ + __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------ USBPHYC Configuration ---------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBPHYC) == RCC_PERIPHCLK_USBPHYC) + { + /* Check the parameters */ + assert_param(IS_RCC_USBPHYCCLKSOURCE(PeriphClkInit->UsbPhycClockSelection)); + + switch (PeriphClkInit->UsbPhycClockSelection) + { + case RCC_USBPHYCCLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for USBPHYC */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK); + /* USBPHYC clock source configuration done later after clock selection check */ + break; + + case RCC_USBPHYCCLKSOURCE_HSE: /* HSE is used as clock source for USBPHYC */ + case RCC_USBPHYCCLKSOURCE_HSE_DIV2: /* HSE divided by 2 is used as clock source for USBPHYC */ + /* USBPHYC clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USBPHYC clock*/ + __HAL_RCC_USBPHYC_CONFIG(PeriphClkInit->UsbPhycClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------ USBOTGFS Configuration ---------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBOTGFS) == RCC_PERIPHCLK_USBOTGFS) + { + /* Check the parameters */ + assert_param(IS_RCC_USBOTGFSCLKSOURCE(PeriphClkInit->UsbOtgFsClockSelection)); + + switch (PeriphClkInit->UsbOtgFsClockSelection) + { + case RCC_USBOTGFSCLKSOURCE_PLL3Q: /* PLL3_Q is used as clock source for USB OTG FS */ + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL_QCLK); + /* USB OTG FS clock source configuration done later after clock selection check */ + break; + + case RCC_USBOTGFSCLKSOURCE_HSI48: /* HSI48 is used as clock source for USB OTG FS */ + case RCC_USBOTGFSCLKSOURCE_HSE: /* HSE is used as clock source for USB OTG FS */ + case RCC_USBOTGFSCLKSOURCE_CLK48: /* USBPHYC CLK48 is used as clock source for USB OTG FS */ + /* USB OTG FS clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USBPHYC clock*/ + __HAL_RCC_USBOTGFS_CONFIG(PeriphClkInit->UsbOtgFsClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------------ TIM configuration --------------------------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER_CONFIG(PeriphClkInit->TIMPresSelection); + } + + if (status == HAL_OK) + { + return HAL_OK; + } + return HAL_ERROR; +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks : + * (SDMMC12, CKPER, FMC, ADC, ADF1, CEC, FDCAN, I2C2/I2C3, I3C1, LPTIM1, + * LPTIM2/LPTIM3, LPTIM4/LPTIM5, LTDC, LPUART1, XSPI1, XSPI2, PSSI, RTC, SAI1, SAI2, + * SPDIF, SPI1, SPI2/SPI3, SPI4/SPI5, SPI6, TIM, USART1, USART2/USART3/UART4/UART5/UART7/UART8 + * USBPHYC, USB OTGFS). + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_CKPER | RCC_PERIPHCLK_ETH1REF | RCC_PERIPHCLK_ETH1PHY | \ + RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_I2C1_I3C1 | \ + RCC_PERIPHCLK_I2C23 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM23 | \ + RCC_PERIPHCLK_LPTIM45 | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_LPUART1 | \ + RCC_PERIPHCLK_XSPI1 | RCC_PERIPHCLK_XSPI2 | RCC_PERIPHCLK_PSSI | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ + RCC_PERIPHCLK_SDMMC12 | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_SPI1 | \ + RCC_PERIPHCLK_SPI23 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART234578 | \ + RCC_PERIPHCLK_USBPHYC | RCC_PERIPHCLK_USBOTGFS; + + /* Get the ADC clock source ------------------------------------------------*/ + PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); + /* Get the ADF1 clock source -----------------------------------------------*/ + PeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE(); + /* Get the CEC clock source ------------------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + /* Get the CKPER clock source ----------------------------------------------*/ + PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE(); + /* Get the ETH1 clock source ----------------------------------------------*/ + PeriphClkInit->Eth1RefClockSelection = __HAL_RCC_GET_ETH1REF_SOURCE(); + /* Get the ETH1PHY clock source ----------------------------------------------*/ + PeriphClkInit->Eth1PhyClockSelection = __HAL_RCC_GET_ETH1PHY_SOURCE(); + /* Get the FDCAN kernel clock source ---------------------------------------*/ + PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE(); + /* Get the FMC kernel clock source -----------------------------------------*/ + PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE(); + /* Get the I2C1 clock source -----------------------------------------------*/ + PeriphClkInit->I2c1_I3c1ClockSelection = __HAL_RCC_GET_I2C1_I3C1_SOURCE(); + /* Get the I2C2/I2C3 clock source ------------------------------------------*/ + PeriphClkInit->I2c23ClockSelection = __HAL_RCC_GET_I2C23_SOURCE(); + /* Get the LPTIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + /* Get the LPTIM2/LPTIM3 clock source --------------------------------------*/ + PeriphClkInit->Lptim23ClockSelection = __HAL_RCC_GET_LPTIM23_SOURCE(); + /* Get the LPTIM4/LPTIM5 clock source --------------------------------------*/ + PeriphClkInit->Lptim45ClockSelection = __HAL_RCC_GET_LPTIM45_SOURCE(); + /* Get the LPUART1 clock source --------------------------------------------*/ + PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); + /* Get the LTDC clock source -----------------------------------------------*/ + PeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); + /* Get the XSPI1 clock source -----------------------------------------------*/ + PeriphClkInit->Xspi1ClockSelection = __HAL_RCC_GET_XSPI1_SOURCE(); + /* Get the XSPI2 clock source -----------------------------------------------*/ + PeriphClkInit->Xspi2ClockSelection = __HAL_RCC_GET_XSPI2_SOURCE(); + /* Get the PSSI clock source -----------------------------------------------*/ + PeriphClkInit->PssiClockSelection = __HAL_RCC_GET_PSSI_SOURCE(); + /* Get the RTC clock source -----------------------------------------------*/ + PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + /* Get the SAI1 clock source -----------------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); + /* Get the SAI2 clock source -----------------------------------------------*/ + PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); + /* Get the SDMMC clock source ----------------------------------------------*/ + PeriphClkInit->Sdmmc12ClockSelection = __HAL_RCC_GET_SDMMC12_SOURCE(); + /* Get the SPDIFRX clock source --------------------------------------------*/ + PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE(); + /* Get the SPI1 clock source -----------------------------------------------*/ + PeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE(); + /* Get the SPI2/SPI3 clock source ------------------------------------------*/ + PeriphClkInit->Spi23ClockSelection = __HAL_RCC_GET_SPI23_SOURCE(); + /* Get the SPI4/SPI5 clock source ------------------------------------------*/ + PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE(); + /* Get the SPI6 clock source -----------------------------------------------*/ + PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE(); + /* Get the TIM Prescaler configuration -------------------------------------*/ + if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DISABLE; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ENABLE; + } + /* Get the USART1 configuration --------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + /* Get the USART2/USART3/UART4/UART5/UART7/UART8 clock source --------------*/ + PeriphClkInit->Usart234578ClockSelection = __HAL_RCC_GET_USART234578_SOURCE(); + /* Get the USBPHYC clock source --------------------------------------------*/ + PeriphClkInit->UsbPhycClockSelection = __HAL_RCC_GET_USBPHYC_SOURCE(); + /* Get the USB OTG FS clock source -----------------------------------------*/ + PeriphClkInit->UsbOtgFsClockSelection = __HAL_RCC_GET_USBOTGFS_SOURCE(); +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral (SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API or + * if the selected clock source is not enabled (HSI, PLLs clock output..) + * @param PeriphClk: Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_FMC : FMC peripheral clock + * @arg RCC_PERIPHCLK_XSPI1 : Xspi1 peripheral clock + * @arg RCC_PERIPHCLK_XSPI2 : Xspi2 peripheral clock + * @arg RCC_PERIPHCLK_CKPER : CKPER peripheral clock + * @arg RCC_PERIPHCLK_ADC : ADC peripheral clock + * @arg RCC_PERIPHCLK_ADF1 : ADF1 peripheral clock + * @arg RCC_PERIPHCLK_CEC : CEC peripheral clock + * @arg RCC_PERIPHCLK_ETH1REF : ETH1REF peripheral clock + * @arg RCC_PERIPHCLK_ETH1PHY : ETH1PHY peripheral clock + * @arg RCC_PERIPHCLK_FDCAN : FDCAN peripheral clock + * @arg RCC_PERIPHCLK_I2C23 : I2C2/I2C3 peripheral clock + * @arg RCC_PERIPHCLK_I2C1_I3C1 : I2C1/I3C1 peripheral clock + * @arg RCC_PERIPHCLK_LPTIM1 : LPTIM1 peripheral clock + * @arg RCC_PERIPHCLK_LPTIM23 : LPTIM23 peripheral clock + * @arg RCC_PERIPHCLK_LPTIM45 : LPTIM45 peripheral clock + * @arg RCC_PERIPHCLK_LPUART1 : LPUART1 peripheral clock + * @arg RCC_PERIPHCLK_LTDC : LTDC peripheral clock + * @arg RCC_PERIPHCLK_PSSI : PSSI peripheral clock + * @arg RCC_PERIPHCLK_RTC : RTC peripheral clock + * @arg RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock + * @arg RCC_PERIPHCLK_SAI2 : SAI2 peripheral clock + * @arg RCC_PERIPHCLK_SDMMC12 : SDMMC12 peripheral clock + * @arg RCC_PERIPHCLK_SPDIFRX : SPDIFRX peripheral clock + * @arg RCC_PERIPHCLK_SPI1 : SPI1 peripheral clock + * @arg RCC_PERIPHCLK_SPI23 : SPI2/SPI3 peripheral clock + * @arg RCC_PERIPHCLK_SPI45 : SPI4/SPI5 peripheral clock + * @arg RCC_PERIPHCLK_SPI6 : SPI6 peripheral clock + * @arg RCC_PERIPHCLK_USART1 : USART1 peripheral clock + * @arg RCC_PERIPHCLK_USART234578 : USART2/3/5/7/8 peripheral clock + * @arg RCC_PERIPHCLK_USBOTGFS : USBOTGFS peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + uint32_t frequency = 0; /* Set to 0 for returned value if no source clock */ + uint32_t clocksource; + uint32_t ethclocksource; + uint32_t prescaler; + + switch (PeriphClk) + { + case RCC_PERIPHCLK_FMC: + clocksource = __HAL_RCC_GET_FMC_SOURCE(); + + switch (clocksource) + { + case RCC_FMCCLKSOURCE_HCLK: /* HCLK is the clock source for FMC kernel peripheral clock */ + frequency = HAL_RCC_GetHCLKFreq(); + break; + case RCC_FMCCLKSOURCE_PLL1Q: /* PLL1 'Q' is the clock source for FMC kernel peripheral clock */ + if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL1QFreq(); + } + break; + case RCC_FMCCLKSOURCE_PLL2R: /* PLL2 'R' is the clock source for FMC kernel peripheral clock */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2RFreq(); + } + break; + case RCC_FMCCLKSOURCE_HSI: /* HSI is the clock source for FMC kernel peripheral clock */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else + { + /* Can't retrieve HSIDIV value */ + } + } + break; + case RCC_FMCCLKSOURCE_HCLK_DIV4: /* HCLK/4 is the clock source for FMC kernel peripheral clock */ + frequency = (HAL_RCC_GetHCLKFreq() / 4U); + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_XSPI1: + clocksource = __HAL_RCC_GET_XSPI1_SOURCE(); + + switch (clocksource) + { + case RCC_XSPI1CLKSOURCE_HCLK: /* HCLK is the clock source for XSPI1 kernel peripheral clock */ + frequency = HAL_RCC_GetHCLKFreq(); + break; + case RCC_XSPI1CLKSOURCE_PLL2S: /* PLL2 'S' is the clock source for XSPI1 kernel peripheral clock */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_SCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2SFreq(); + } + break; + case RCC_XSPI1CLKSOURCE_PLL2T: /* PLL2 'T' is the clock source for XSPI1 kernel peripheral clock */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_TCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2TFreq(); + } + break; + case RCC_XSPI1CLKSOURCE_HCLK_DIV4: /* HCLK/4 is the clock source for XSPI1 kernel peripheral clock */ + frequency = (HAL_RCC_GetHCLKFreq() / 4U); + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_XSPI2: + clocksource = __HAL_RCC_GET_XSPI2_SOURCE(); + + switch (clocksource) + { + case RCC_XSPI2CLKSOURCE_HCLK: /* HCLK is the clock source for XSPI2 kernel peripheral clock */ + frequency = HAL_RCC_GetHCLKFreq(); + break; + case RCC_XSPI2CLKSOURCE_PLL2S: /* PLL2 'S' is the clock source for XSPI2 kernel peripheral clock */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_SCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2SFreq(); + } + break; + case RCC_XSPI2CLKSOURCE_PLL2T: /* PLL2 'T' is the clock source for XSPI2 kernel peripheral clock */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_TCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2TFreq(); + } + break; + case RCC_XSPI2CLKSOURCE_HCLK_DIV4: /* HCLK/4 is the clock source for XSPI2 kernel peripheral clock */ + frequency = (HAL_RCC_GetHCLKFreq() / 4U); + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_CKPER: + clocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + switch (clocksource) + { + case RCC_CLKPSOURCE_HSI: /* HSI is the clock source for CKPER */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else + { + /* Can't retrieve HSIDIV value */ + } + } + break; + case RCC_CLKPSOURCE_CSI: /* CSI is the clock source for CKPER */ + if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) + { + frequency = CSI_VALUE; + } + break; + case RCC_CLKPSOURCE_HSE: /* HSE is the clock source for CKPER */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + frequency = HSE_VALUE; + } + break; + + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_ADC: + clocksource = __HAL_RCC_GET_ADC_SOURCE(); + + switch (clocksource) + { + case RCC_ADCCLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for ADC */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2PFreq(); + } + break; + case RCC_ADCCLKSOURCE_PLL3R: /* PLL3 'R' is the clock source for ADC */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3RFreq(); + } + break; + case RCC_ADCCLKSOURCE_CLKP: /* CKPER is the clock source for ADC */ + frequency = RCC_GetCLKPFreq(); + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_ADF1: + clocksource = __HAL_RCC_GET_ADF1_SOURCE(); + + switch (clocksource) + { + case RCC_ADF1CLKSOURCE_HCLK: /* HCLK is the clock source for ADF1 */ + frequency = HAL_RCC_GetHCLKFreq(); + break; + case RCC_ADF1CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for ADF1 */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2PFreq(); + } + break; + case RCC_ADF1CLKSOURCE_PLL3P: /* PLL3 'P' is the clock source for ADF1 */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3PFreq(); + } + break; + case RCC_ADF1CLKSOURCE_PIN: /* External I2S_CKIN is used as clock source for ADF1 */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + case RCC_ADF1CLKSOURCE_CSI: /* CSI is the clock source for ADF1 */ + if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) + { + frequency = CSI_VALUE; + } + break; + case RCC_ADF1CLKSOURCE_HSI: /* HSI is the clock source for ADF1 */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else + { + /* Can't retrieve HSIDIV value */ + } + } + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_CEC: + clocksource = __HAL_RCC_GET_CEC_SOURCE(); + + switch (clocksource) + { + case RCC_CECCLKSOURCE_LSE: /* LSE is the clock source for CEC */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + { + frequency = LSE_VALUE; + } + break; + case RCC_CECCLKSOURCE_LSI: /* LSI is the clock source for CEC */ + if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + { + frequency = LSI_VALUE; + } + break; + case RCC_CECCLKSOURCE_CSI: /* CSI is the clock source for CEC */ + if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) + { + frequency = CSI_VALUE; + } + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_ETH1REF: + clocksource = __HAL_RCC_GET_ETH1REF_SOURCE(); + + switch (clocksource) + { + case RCC_ETH1REFCLKSOURCE_PHY: /* PHY is the clock source for ETH1REF */ + /* Can't retrieve this source's frequency, it is by default set to 0 */ + break; + case RCC_ETH1REFCLKSOURCE_HSE: /* HSE is the clock source for ETH1REF */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + frequency = HSE_VALUE; + } + break; + case RCC_ETH1REFCLKSOURCE_ETH: /* ETH is the clock source for ETH1REF */ + ethclocksource = __HAL_RCC_GET_ETH1PHY_SOURCE(); + + switch (ethclocksource) + { + case RCC_ETH1PHYCLKSOURCE_HSE: + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + frequency = HSE_VALUE; + } + break; + case RCC_ETH1PHYCLKSOURCE_PLL3S: + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_SCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3SFreq(); + } + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_ETH1PHY: + clocksource = __HAL_RCC_GET_ETH1PHY_SOURCE(); + + switch (clocksource) + { + case RCC_ETH1PHYCLKSOURCE_HSE: + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + frequency = HSE_VALUE; + } + break; + case RCC_ETH1PHYCLKSOURCE_PLL3S: + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_SCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3SFreq(); + } + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_FDCAN: + clocksource = __HAL_RCC_GET_FDCAN_SOURCE(); + + switch (clocksource) + { + case RCC_FDCANCLKSOURCE_HSE: /*!< HSE is the clock source for FDCAN */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + frequency = HSE_VALUE; + } + break; + case RCC_FDCANCLKSOURCE_PLL1Q: /*!< PLL1 'Q' ois the clock source for FDCAN */ + if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL1QFreq(); + } + break; + case RCC_FDCANCLKSOURCE_PLL2P: /*!< PLL2 'P' is the clock source for FDCAN */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2PFreq(); + } + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_I2C23: + clocksource = __HAL_RCC_GET_I2C23_SOURCE(); + + switch (clocksource) + { + case RCC_I2C23CLKSOURCE_PCLK1: /*!< PCLK1 is the clock source for I2C23 */ + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_I2C23CLKSOURCE_PLL3R: /*!< PLL3R is the clock source for I2C23 */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3RFreq(); + } + break; + case RCC_I2C23CLKSOURCE_HSI: /*!< HSI is the clock source for I2C23 */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else + { + /* Can't retrieve HSIDIV value */ + } + } + break; + case RCC_I2C23CLKSOURCE_CSI: /*!< CSI is the clock source for I2C23 */ + if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) + { + frequency = CSI_VALUE; + } + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_I2C1_I3C1: + clocksource = __HAL_RCC_GET_I2C1_I3C1_SOURCE(); + + switch (clocksource) + { + case RCC_I2C1_I3C1CLKSOURCE_PCLK1: /*!< PCLK1 is the clock source for I2C1/I3C1 */ + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_I2C1_I3C1CLKSOURCE_PLL3R: /*!< PLL3 'R' is the clock source for I2C1/I3C1 */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3RFreq(); + } + break; + case RCC_I2C1_I3C1CLKSOURCE_HSI: /*!< HSI is the clock source for I2C1/I3C1 */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else + { + /* Can't retrieve HSIDIV value */ + } + } + break; + case RCC_I2C1_I3C1CLKSOURCE_CSI: /*!< CSI is the clock source for I2C1/I3C1 */ + if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) + { + frequency = CSI_VALUE; + } + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_LPTIM1: + clocksource = __HAL_RCC_GET_LPTIM1_SOURCE(); + + switch (clocksource) + { + case RCC_LPTIM1CLKSOURCE_PCLK1: /* PCLK1 is the clock source for LPTIM1 */ + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_LPTIM1CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for LPTIM1 */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2PFreq(); + } + break; + case RCC_LPTIM1CLKSOURCE_PLL3R: /* PLL3 'R' is the clock source for LPTIM1 */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3RFreq(); + } + break; + case RCC_LPTIM1CLKSOURCE_LSE: /* LSE is the clock source for LPTIM1 */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + { + frequency = LSE_VALUE; + } + break; + case RCC_LPTIM1CLKSOURCE_LSI: /* LSI is the clock source for LPTIM1 */ + if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + { + frequency = LSI_VALUE; + } + break; + case RCC_LPTIM1CLKSOURCE_CLKP: /* CKPER is the clock source for LPTIM1 */ + frequency = RCC_GetCLKPFreq(); + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_LPTIM23: + clocksource = __HAL_RCC_GET_LPTIM23_SOURCE(); + + switch (clocksource) + { + case RCC_LPTIM23CLKSOURCE_PCLK4: /* PCLK4 is the clock source for LPTIM2/LPTIM3 */ + frequency = HAL_RCC_GetPCLK4Freq(); + break; + case RCC_LPTIM23CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for LPTIM2/LPTIM3 */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2PFreq(); + } + break; + case RCC_LPTIM23CLKSOURCE_PLL3R: /* PLL3 'R' is the clock source for LPTIM2/LPTIM3 */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3RFreq(); + } + break; + case RCC_LPTIM23CLKSOURCE_LSE: /* LSE is the clock source for LPTIM2/LPTIM3 */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + { + frequency = LSE_VALUE; + } + break; + case RCC_LPTIM23CLKSOURCE_LSI: /* LSI is the clock source for LPTIM2/LPTIM3 */ + if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + { + frequency = LSI_VALUE; + } + break; + case RCC_LPTIM23CLKSOURCE_CLKP: /* CKPER is the clock source for LPTIM2/LPTIM3 */ + frequency = RCC_GetCLKPFreq(); + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_LPTIM45: + clocksource = __HAL_RCC_GET_LPTIM45_SOURCE(); + + switch (clocksource) + { + case RCC_LPTIM45CLKSOURCE_PCLK4: /* PCLK4 is the clock source for LPTIM4/LPTIM5 */ + frequency = HAL_RCC_GetPCLK4Freq(); + break; + case RCC_LPTIM45CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for LPTIM4/LPTIM5 */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2PFreq(); + } + break; + case RCC_LPTIM45CLKSOURCE_PLL3R: /* PLL3 'R' is the clock source for LPTIM4/LPTIM5 */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3RFreq(); + } + break; + case RCC_LPTIM45CLKSOURCE_LSE: /* LSE is the clock source for LPTIM4/LPTIM5 */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + { + frequency = LSE_VALUE; + } + break; + case RCC_LPTIM45CLKSOURCE_LSI: /* LSI is the clock source for LPTIM4/LPTIM5 */ + if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + { + frequency = LSI_VALUE; + } + break; + case RCC_LPTIM45CLKSOURCE_CLKP: /* CKPER is the clock source for LPTIM4/LPTIM5 */ + frequency = RCC_GetCLKPFreq(); + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_LPUART1: + clocksource = __HAL_RCC_GET_LPUART1_SOURCE(); + + switch (clocksource) + { + case RCC_LPUART1CLKSOURCE_PCLK4: /*!< PCLK4 is the clock source for LPUART1 */ + frequency = HAL_RCC_GetPCLK4Freq(); + break; + case RCC_LPUART1CLKSOURCE_PLL2Q: /*!< PLL2 'Q' is the clock source for LPUART1 */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2QFreq(); + } + break; + case RCC_LPUART1CLKSOURCE_PLL3Q: /*!< PLL3 'Q' is the clock source for LPUART1 */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3QFreq(); + } + break; + case RCC_LPUART1CLKSOURCE_HSI: /*!< HSI is the clock source for LPUART1 */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else + { + /* Can't retrieve HSIDIV value */ + } + } + break; + case RCC_LPUART1CLKSOURCE_CSI: /*!< CSI is the clock source for LPUART1 */ + if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) + { + frequency = CSI_VALUE; + } + break; + case RCC_LPUART1CLKSOURCE_LSE: /*!< LSE is the clock source for LPUART1 */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + { + frequency = LSE_VALUE; + } + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_LTDC: + /* Unique PLL3 'R' clock source */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3RFreq(); + } + break; + + case RCC_PERIPHCLK_PSSI: + clocksource = __HAL_RCC_GET_PSSI_SOURCE(); + + switch (clocksource) + { + case RCC_PSSICLKSOURCE_PLL3R: /*!< PLL3 'R' is the clock source for PSSI */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3RFreq(); + } + break; + case RCC_PSSICLKSOURCE_CLKP: /*!< CLKP is the clock source for PSSI */ + frequency = RCC_GetCLKPFreq(); + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_RTC: + clocksource = __HAL_RCC_GET_RTC_SOURCE(); + + switch (clocksource) + { + case RCC_RTCCLKSOURCE_DISABLE: + /* Nothing to do, frequency is by default set to 0 */ + break; + case RCC_RTCCLKSOURCE_LSE: /*!< LSE is the clock source for RTC */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + { + frequency = LSE_VALUE; + } + break; + case RCC_RTCCLKSOURCE_LSI: /*!< LSI is the clock source for RTC */ + if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + { + frequency = LSI_VALUE; + } + break; + default: + if (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) /*!< HSE is the clock source for RTC */ + { + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + prescaler = READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) >> RCC_CFGR_RTCPRE_Pos; + if (prescaler > 1U) + { + frequency = HSE_VALUE / prescaler; + } + } + } + else + { + /* Nothing to do, frequency is by default set to 0 */ + } + break; + } + break; + + case RCC_PERIPHCLK_SAI1: + clocksource = __HAL_RCC_GET_SAI1_SOURCE(); + + switch (clocksource) + { + case RCC_SAI1CLKSOURCE_PLL1Q: /* PLL1 'Q' is the clock source for SAI1 */ + if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL1QFreq(); + } + break; + case RCC_SAI1CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for SAI1 */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2PFreq(); + } + break; + case RCC_SAI1CLKSOURCE_PLL3P: /* PLL3 'P' is the clock source for SAI1 */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3PFreq(); + } + break; + case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1 */ + frequency = RCC_GetCLKPFreq(); + break; + case RCC_SAI1CLKSOURCE_PIN: /* External clock is the clock source for SAI1 */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_SAI2: + clocksource = __HAL_RCC_GET_SAI2_SOURCE(); + + switch (clocksource) + { + case RCC_SAI2CLKSOURCE_PLL1Q: /* PLL1 'Q' is the clock source for SAI2 */ + if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL1QFreq(); + } + break; + case RCC_SAI2CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for SAI2 */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2PFreq(); + } + break; + case RCC_SAI2CLKSOURCE_PLL3P: /* PLL3 'P' is the clock source for SAI2 */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3PFreq(); + } + break; + case RCC_SAI2CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2 */ + frequency = RCC_GetCLKPFreq(); + break; + case RCC_SAI2CLKSOURCE_SPDIF: + /* Can't retrieve this source's frequency, it is by default set to 0 */ + break; + case RCC_SAI2CLKSOURCE_PIN: /* External clock is the clock source for SAI2 */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_SDMMC12: /* SDMMC1 and SDMMC2 */ + + clocksource = __HAL_RCC_GET_SDMMC12_SOURCE(); + + if (clocksource == + RCC_SDMMC12CLKSOURCE_PLL2S) /* PLL2 'S' is the clock source for SDMMC1 and SDMMC2 kernel peripheral clock */ + { + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_SCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2SFreq(); + } + } + else /* PLL2 'T' is the clock source for SDMMC1 and SDMMC2 kernel peripheral clock */ + { + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_TCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2TFreq(); + } + } + break; + + case RCC_PERIPHCLK_SPDIFRX: + clocksource = __HAL_RCC_GET_SPDIFRX_SOURCE(); + + switch (clocksource) + { + case RCC_SPDIFRXCLKSOURCE_PLL1Q: /* PLL1 'Q' is the clock source for SPDIFRX */ + if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL1QFreq(); + } + break; + case RCC_SPDIFRXCLKSOURCE_PLL2R: /* PLL2 'R' is the clock source for SPDIFRX */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2RFreq(); + } + break; + case RCC_SPDIFRXCLKSOURCE_PLL3R: /* PLL3 'R' is the clock source for SPDIFRX */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_RCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3RFreq(); + } + break; + case RCC_SPDIFRXCLKSOURCE_HSI: /* HSI is the clock source for SPDIFRX */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else + { + /* Can't retrieve HSIDIV value */ + } + } + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_SPI1: + clocksource = __HAL_RCC_GET_SPI1_SOURCE(); + + switch (clocksource) + { + case RCC_SPI1CLKSOURCE_PLL1Q: /* PLL1 'Q' is the clock source for SPI1 */ + if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL1QFreq(); + } + break; + case RCC_SPI1CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for SPI1 */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2PFreq(); + } + break; + case RCC_SPI1CLKSOURCE_PLL3P: /* PLL3 'P' is the clock source for SPI1 */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3PFreq(); + } + break; + case RCC_SPI1CLKSOURCE_CLKP: /* CKPER is the clock source for SPI1 */ + frequency = RCC_GetCLKPFreq(); + break; + case RCC_SPI1CLKSOURCE_PIN: /* External I2S_CKIN is used as clock source for SPI1 */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_SPI23: + clocksource = __HAL_RCC_GET_SPI23_SOURCE(); + + switch (clocksource) + { + case RCC_SPI23CLKSOURCE_PLL1Q: /* PLL1 'Q' is the clock source for SPI2/SPI3 */ + if (__HAL_RCC_GET_PLL1CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL1QFreq(); + } + break; + case RCC_SPI23CLKSOURCE_PLL2P: /* PLL2 'P' is the clock source for SPI2/SPI3 */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2PFreq(); + } + break; + case RCC_SPI23CLKSOURCE_PLL3P: /* PLL3 'P' is the clock source for SPI2/SPI3 */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_PCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3PFreq(); + } + break; + case RCC_SPI23CLKSOURCE_CLKP: /* CKPER is the clock source for SPI2/SPI3 */ + frequency = RCC_GetCLKPFreq(); + break; + case RCC_SPI23CLKSOURCE_PIN: /* External I2S_CKIN is used as clock source for SPI2/SPI3 */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_SPI45: + clocksource = __HAL_RCC_GET_SPI45_SOURCE(); + + switch (clocksource) + { + case RCC_SPI45CLKSOURCE_PCLK2: /* PCLK2 is the clock source for SPI4/SPI5 */ + frequency = HAL_RCC_GetPCLK2Freq(); + break; + case RCC_SPI45CLKSOURCE_PLL2Q: /* PLL2 'Q' is the clock source for SPI4/SPI5 */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2QFreq(); + } + break; + case RCC_SPI45CLKSOURCE_PLL3Q: /* PLL3 'Q' is the clock source for SPI4/SPI5 */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3QFreq(); + } + break; + case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI4/SPI5 */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else + { + /* Can't retrieve HSIDIV value */ + } + } + break; + case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI4/SPI5 */ + if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) + { + frequency = CSI_VALUE; + } + break; + case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI4/SPI5 */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + frequency = HSE_VALUE; + } + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_SPI6: + clocksource = __HAL_RCC_GET_SPI6_SOURCE(); + + switch (clocksource) + { + case RCC_SPI6CLKSOURCE_PCLK4: /* PCLK4 is the clock source for SPI6 */ + frequency = HAL_RCC_GetPCLK4Freq(); + break; + case RCC_SPI6CLKSOURCE_PLL2Q: /* PLL2 'Q' is the clock source for SPI6 */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2QFreq(); + } + break; + case RCC_SPI6CLKSOURCE_PLL3Q: /* PLL3 'Q' is the clock source for SPI6 */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3QFreq(); + } + break; + case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else + { + /* Can't retrieve HSIDIV value */ + } + } + break; + case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ + if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) + { + frequency = CSI_VALUE; + } + break; + case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + frequency = HSE_VALUE; + } + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_USART1: + clocksource = __HAL_RCC_GET_USART1_SOURCE(); + + switch (clocksource) + { + case RCC_USART1CLKSOURCE_PCLK2: /*!< PCLK2 is the clock source for USART1 */ + frequency = HAL_RCC_GetPCLK2Freq(); + break; + case RCC_USART1CLKSOURCE_PLL2Q: /*!< PLL2 'Q' is the clock source for USART1 */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2QFreq(); + } + break; + case RCC_USART1CLKSOURCE_PLL3Q: /*!< PLL3 'Q' is the clock source for USART1 */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3QFreq(); + } + break; + case RCC_USART1CLKSOURCE_HSI: /*!< HSI is the clock source for USART1 */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else + { + /* Can't retrieve HSIDIV value */ + } + } + break; + case RCC_USART1CLKSOURCE_CSI: /*!< CSI is the clock source for USART1 */ + if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) + { + frequency = CSI_VALUE; + } + break; + case RCC_USART1CLKSOURCE_LSE: /*!< LSE is the clock source for USART1 */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + { + frequency = LSE_VALUE; + } + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_USART234578: + clocksource = __HAL_RCC_GET_USART234578_SOURCE(); + + switch (clocksource) + { + case RCC_USART234578CLKSOURCE_PCLK1: /*!< PCLK2 is the clock source for USART234578 */ + frequency = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_USART234578CLKSOURCE_PLL2Q: /*!< PLL2 'Q' is the clock source for USART234578 */ + if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL2QFreq(); + } + break; + case RCC_USART234578CLKSOURCE_PLL3Q: /*!< PLL3 'Q' is the clock source for USART234578 */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3QFreq(); + } + break; + case RCC_USART234578CLKSOURCE_HSI: /*!< HSI is the clock source for USART234578 */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else + { + /* Can't retrieve HSIDIV value */ + } + } + break; + case RCC_USART234578CLKSOURCE_CSI: /*!< CSI is the clock source for USART234578 */ + if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) + { + frequency = CSI_VALUE; + } + break; + case RCC_USART234578CLKSOURCE_LSE: /*!< LSE is the clock source for USART234578 */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + { + frequency = LSE_VALUE; + } + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_USBPHYC: + clocksource = __HAL_RCC_GET_USBPHYC_SOURCE(); + + switch (clocksource) + { + case RCC_USBPHYCCLKSOURCE_HSE: /*!< HSE is the clock source for USBPHYC */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + frequency = HSE_VALUE; + } + break; + case RCC_USBPHYCCLKSOURCE_HSE_DIV2: /*!< HSE/2 is the clock source for USBPHYC */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + frequency = (HSE_VALUE >> 1UL); + } + break; + case RCC_USBPHYCCLKSOURCE_PLL3Q: /*!< PLL3Q is the clock source for USBPHYC */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3QFreq(); + } + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + case RCC_PERIPHCLK_USBOTGFS: + clocksource = __HAL_RCC_GET_USBOTGFS_SOURCE(); + + switch (clocksource) + { + case RCC_USBOTGFSCLKSOURCE_HSI48: /*!< HSI48 is the clock source for USBOTGFS */ + if (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U) + { + frequency = HSI48_VALUE; + } + break; + case RCC_USBOTGFSCLKSOURCE_PLL3Q: /*!< PLL3Q is the clock source for USBOTGFS */ + if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL_QCLK) != 0U) + { + frequency = HAL_RCC_GetPLL3QFreq(); + } + break; + case RCC_USBOTGFSCLKSOURCE_HSE: /*!< HSE is the clock source for USBOTGFS */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + frequency = HSE_VALUE; + } + break; + case RCC_USBOTGFSCLKSOURCE_CLK48: /*!< CLK48 is the clock source for USBOTGFS */ + /* Can't retrieve this source's frequency, it is by default set to 0 */ + break; + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + break; + + default: + /* Nothing to do, frequency is by default set to 0 */ + break; + } + + return frequency; +} + +/** + * @brief Enable clock protection. + * @note When set, this prevents disabling accidentally clock related data. + * @param ProtectClk Clock(s) to enable protection on + * This parameter can be one or a combination of the following + * @arg RCC_CLOCKPROTECT_FMC FMC clock protection + * @arg RCC_CLOCKPROTECT_XSPI XSPIs clock protection + * @retval None + */ +void HAL_RCCEx_EnableClockProtection(uint32_t ProtectClk) +{ + /* Check the parameter */ + assert_param(IS_RCC_CLOCKPROTECTION(ProtectClk)); + + SET_BIT(RCC->CKPROTR, ProtectClk); +} + +/** + * @brief Disable clock protection. + * @param ProtectClk Clock(s) to disable protection on + * This parameter can be one or a combination of the following + * @arg RCC_CLOCKPROTECT_FMC FMC clock protection + * @arg RCC_CLOCKPROTECT_XSPI XSPIs clock protection + * @retval None + */ +void HAL_RCCEx_DisableClockProtection(uint32_t ProtectClk) +{ + /* Check the parameter */ + assert_param(IS_RCC_CLOCKPROTECTION(ProtectClk)); + + CLEAR_BIT(RCC->CKPROTR, ProtectClk); +} + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions + * @brief Extended Peripheral Control functions + * @{ + */ +/** + * @brief Enables the LSE Clock Security System. + * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled + * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC + * clock with HAL_RCCEx_PeriphCLKConfig(). + * @note Backup domain access should be enabled + * @retval None + */ +void HAL_RCCEx_EnableLSECSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; +} + +/** + * @brief Disables the LSE Clock Security System. + * @note LSE Clock Security System can only be disabled after a LSE failure detection. + * @note Backup domain access should be enabled + * @retval None + */ +void HAL_RCCEx_DisableLSECSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + /* Disable LSE CSS IT if any */ + __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); +} + +/** + * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. + * @note LSE Clock Security System Interrupt is mapped on EXTI line 18 + * @retval None + */ +void HAL_RCCEx_EnableLSECSS_IT(void) +{ + /* Enable LSE CSS */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + + /* Enable LSE CSS IT */ + __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); + + /* Enable IT on EXTI Line 18 */ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); + __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); +} + +/** + * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock + * @param WakeUpClk: Wakeup clock + * This parameter can be one of the following values: + * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection + * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection + * @note This function shall not be called after the Clock Security System on HSE has been + * enabled. + * @retval None + */ +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +/** + * @brief Configure the oscillator Kernel clock source for wakeup from Stop + * @param WakeUpClk: Kernel Wakeup clock + * This parameter can be one of the following values: + * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection + * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection + * @retval None + */ +void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +/** + * @brief Handle the RCC LSE Clock Security System interrupt request. + * @retval None + */ +void HAL_RCCEx_LSECSS_IRQHandler(void) +{ + /* Check RCC LSE CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_LSECSS)) + { + /* Clear RCC LSE CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); + + /* RCC LSE Clock Security System interrupt user callback */ + HAL_RCCEx_LSECSS_Callback(); + } +} + +/** + * @brief RCCEx LSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_LSECSS_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions + * @brief Extended Clock Recovery System Control functions + * +@verbatim + =============================================================================== + ##### Extended Clock Recovery System Control functions ##### + =============================================================================== + [..] + For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: + + (#) In System clock config, HSI48 needs to be enabled + + (#) Enable CRS clock + + (#) Call CRS functions as follows: + (##) Prepare synchronization configuration necessary for HSI48 calibration + (+++) Default values can be set for frequency Error Measurement (reload and error limit) + and also HSI48 oscillator smooth trimming. + (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + directly reload value with target and synchronization frequencies values + (##) Call function HAL_RCCEx_CRSConfig which + (+++) Resets CRS registers to their default values. + (+++) Configures CRS registers with synchronization configuration + (+++) Enables automatic calibration and frequency error counter feature + Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. No SYNC signal will therefore be + provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock + precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs + should be used as SYNC signal. + + (##) A polling function is provided to wait for complete synchronization + (+++) Call function HAL_RCCEx_CRSWaitSynchronization() + (+++) According to CRS status, user can decide to adjust again the calibration or continue + application if synchronization is OK + + (#) User can retrieve information related to synchronization in calling function + HAL_RCCEx_CRSGetSynchronizationInfo() + + (#) Regarding synchronization status and synchronization information, user can try a new calibration + in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the upcounting phase it means that the actual frequency + is higher (and that the TRIM value should be decremented). + + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + through CRS Handler (CRS_IRQn/CRS_IRQHandler) + (++) Call function HAL_RCCEx_CRSConfig() + (++) Enable CRS_IRQn (thanks to NVIC functions) + (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) + (++) Implement CRS status management in the following user callbacks called from + HAL_RCCEx_CRS_IRQHandler(): + (+++) HAL_RCCEx_CRS_SyncOkCallback() + (+++) HAL_RCCEx_CRS_SyncWarnCallback() + (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() + (+++) HAL_RCCEx_CRS_ErrorCallback() + + (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). + This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) + +@endverbatim + * @{ + */ + +/** + * @brief Start automatic synchronization for polling mode. + * @param pInit Pointer on RCC_CRSInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit) +{ + uint32_t value; + + /* Check the parameters */ + assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); + assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + + /* CONFIGURATION */ + + /* Before configuration, reset CRS registers to their default values*/ + __HAL_RCC_CRS_FORCE_RESET(); + __HAL_RCC_CRS_RELEASE_RESET(); + + /* Set the SYNCDIV[2:0] bits according to Prescaler value */ + /* Set the SYNCSRC[1:0] bits according to Source value */ + /* Set the SYNCSPOL bit according to Polarity value */ + value = (pInit->Prescaler | pInit->Source | pInit->Polarity); + /* Set the RELOAD[15:0] bits according to ReloadValue value */ + value |= pInit->ReloadValue; + /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); + WRITE_REG(CRS->CFGR, value); + + /* Adjust HSI48 oscillator smooth trimming */ + /* Set the TRIM[5:0] bits according to HSI48CalibrationValue value */ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); + + /* START AUTOMATIC SYNCHRONIZATION*/ + + /* Enable Automatic trimming & Frequency error counter */ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); +} + +/** + * @brief Generate the software synchronization event. + * @retval None + */ +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Return synchronization info. + * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) +{ + /* Check the parameter */ + assert_param(pSynchroInfo != (void *)NULL); + + /* Get the reload value */ + pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + + /* Get HSI48 oscillator smooth trimming */ + pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); + + /* Get Frequency error capture */ + pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); + + /* Get Frequency error direction */ + pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Wait for CRS Synchronization status. + * @param Timeout Duration of the timeout + * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization + * frequency. + * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. + * @retval Combination of Synchronization status + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_TIMEOUT + * @arg @ref RCC_CRS_SYNCOK + * @arg @ref RCC_CRS_SYNCWARN + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + */ +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +{ + uint32_t crsstatus = RCC_CRS_NONE; + uint32_t tickstart; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait for CRS flag or timeout detection */ + do + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + crsstatus = RCC_CRS_TIMEOUT; + } + } + /* Check CRS SYNCOK flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + { + /* CRS SYNC event OK */ + crsstatus |= RCC_CRS_SYNCOK; + + /* Clear CRS SYNC event OK bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); + } + + /* Check CRS SYNCWARN flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + { + /* CRS SYNC warning */ + crsstatus |= RCC_CRS_SYNCWARN; + + /* Clear CRS SYNCWARN bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); + } + + /* Check CRS TRIM overflow flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_TRIMOVF; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); + } + + /* Check CRS Error flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_SYNCERR; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); + } + + /* Check CRS SYNC Missed flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + { + /* CRS SYNC Missed */ + crsstatus |= RCC_CRS_SYNCMISS; + + /* Clear CRS SYNC Missed bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); + } + + /* Check CRS Expected SYNC flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + { + /* frequency error counter reached a zero value */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); + } + } while (RCC_CRS_NONE == crsstatus); + + return crsstatus; +} + +/** + * @brief Handle the Clock Recovery System interrupt request. + * @retval None + */ +void HAL_RCCEx_CRS_IRQHandler(void) +{ + uint32_t crserror = RCC_CRS_NONE; + /* Get current IT flags and IT sources values */ + uint32_t itflags = READ_REG(CRS->ISR); + uint32_t itsources = READ_REG(CRS->CR); + + /* Check CRS SYNCOK flag */ + if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) + { + /* Clear CRS SYNC event OK flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); + + /* user callback */ + HAL_RCCEx_CRS_SyncOkCallback(); + } + /* Check CRS SYNCWARN flag */ + else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) + { + /* Clear CRS SYNCWARN flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); + + /* user callback */ + HAL_RCCEx_CRS_SyncWarnCallback(); + } + /* Check CRS Expected SYNC flag */ + else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) + { + /* frequency error counter reached a zero value */ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); + + /* user callback */ + HAL_RCCEx_CRS_ExpectedSyncCallback(); + } + /* Check CRS Error flags */ + else + { + if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) + { + if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) + { + crserror |= RCC_CRS_SYNCERR; + } + if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) + { + crserror |= RCC_CRS_SYNCMISS; + } + if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) + { + crserror |= RCC_CRS_TRIMOVF; + } + + /* Clear CRS Error flags */ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); + + /* user error callback */ + HAL_RCCEx_CRS_ErrorCallback(crserror); + } + } +} + +/** + * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncOkCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Error interrupt callback. + * @param Error Combination of Error status. + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + * @retval none + */ +__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Error); + + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file + */ +} + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup RCC_Private_Functions + * @{ + */ + +/** + * @brief Compute PLL2 VCO output frequency + * @retval Value of PLL2 VCO output frequency + */ +static uint32_t RCC_GetCLKPFreq(void) +{ + uint32_t frequency = 0U; + uint32_t ckpclocksource; + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if (ckpclocksource == RCC_CLKPSOURCE_HSI) + { + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0U) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos)); + } + else + { + /* Can't retrieve HSIDIV value */ + } + } + } + else if (ckpclocksource == RCC_CLKPSOURCE_CSI) + { + if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) != 0U) + { + frequency = CSI_VALUE; + } + } + else if (ckpclocksource == RCC_CLKPSOURCE_HSE) + { + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + frequency = HSE_VALUE; + } + } + else + { + /* Nothing to do, case the CKPER is disabled */ + /* frequency is by default set to 0 */ + } + + return frequency; +} +/** + * @} + */ + +/** + * @} + */ +#endif /* HAL_RCC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rng.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rng.c new file mode 100644 index 00000000000..3f2be663859 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rng.c @@ -0,0 +1,1025 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_rng.c + * @author MCD Application Team + * @brief RNG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Random Number Generator (RNG) peripheral: + * + Initialization and configuration functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The RNG HAL driver can be used as follows: + + (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro + in HAL_RNG_MspInit(). + (#) Activate the RNG peripheral using HAL_RNG_Init() function. + (#) Wait until the 32 bit Random Number Generator contains a valid + random data using (polling/interrupt) mode. + (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_RNG_RegisterCallback() to register a user callback. + Function HAL_RNG_RegisterCallback() allows to register following callbacks: + (+) ErrorCallback : RNG Error Callback. + (+) MspInitCallback : RNG MspInit. + (+) MspDeInitCallback : RNG MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. + HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ErrorCallback : RNG Error Callback. + (+) MspInitCallback : RNG MspInit. + (+) MspDeInitCallback : RNG MspDeInit. + + [..] + For specific callback ReadyDataCallback, use dedicated register callbacks: + respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback(). + + [..] + By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET + all callbacks are set to the corresponding weak (overridden) functions: + example HAL_RNG_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (overridden) functions in the HAL_RNG_Init() + and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit() + or HAL_RNG_Init() function. + + [..] + When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (overridden) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#if defined (RNG) + +/** @addtogroup RNG + * @brief RNG HAL module driver. + * @{ + */ + +#ifdef HAL_RNG_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RNG_Private_Constants RNG Private Constants + * @{ + */ +#define RNG_TIMEOUT_VALUE 10U +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions prototypes ----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup RNG_Exported_Functions + * @{ + */ + +/** @addtogroup RNG_Exported_Functions_Group1 + * @brief Initialization and configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the RNG according to the specified parameters + in the RNG_InitTypeDef and create the associated handle + (+) DeInitialize the RNG peripheral + (+) Initialize the RNG MSP + (+) DeInitialize RNG MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RNG peripheral and creates the associated handle. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) +{ + uint32_t tickstart; + /* Check the RNG handle allocation */ + if (hrng == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ + assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); + assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection)); + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + if (hrng->State == HAL_RNG_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrng->Lock = HAL_UNLOCKED; + + hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */ + hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hrng->MspInitCallback == NULL) + { + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hrng->MspInitCallback(hrng); + } +#else + if (hrng->State == HAL_RNG_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrng->Lock = HAL_UNLOCKED; + + /* Init the low level hardware */ + HAL_RNG_MspInit(hrng); + } +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Disable RNG */ + __HAL_RNG_DISABLE(hrng); + + /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ + MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST); + + /* Writing bit CONDRST=0 */ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for conditioning reset process to be completed */ + while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } + } + } + + /* Enable the RNG Peripheral */ + __HAL_RNG_ENABLE(hrng); + + /* verify that no seed error */ + if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + { + hrng->State = HAL_RNG_STATE_ERROR; + return HAL_ERROR; + } + /* Get tick */ + tickstart = HAL_GetTick(); + /* Check if data register contains valid random data */ + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + { + hrng->State = HAL_RNG_STATE_ERROR; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } + } + } + + /* Initialize the RNG state */ + hrng->State = HAL_RNG_STATE_READY; + + /* Initialise the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_NONE; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitializes the RNG peripheral. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) +{ + uint32_t tickstart; + + /* Check the RNG handle allocation */ + if (hrng == NULL) + { + return HAL_ERROR; + } + + /* Clear Clock Error Detection bit when CONDRT bit is set to 1 */ + MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, RNG_CED_ENABLE | RNG_CR_CONDRST); + + /* Writing bit CONDRST=0 */ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for conditioning reset process to be completed */ + while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } + } + } + + /* Disable the RNG Peripheral */ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN); + + /* Clear RNG interrupt status flags */ + CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS); + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + if (hrng->MspDeInitCallback == NULL) + { + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hrng->MspDeInitCallback(hrng); +#else + /* DeInit the low level hardware */ + HAL_RNG_MspDeInit(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + + /* Update the RNG state */ + hrng->State = HAL_RNG_STATE_RESET; + + /* Initialise the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hrng); + + /* Return the function status */ + return HAL_OK; +} + +/** + * @brief Initializes the RNG MSP. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval None + */ +__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_MspInit must be implemented in the user file. + */ +} + +/** + * @brief DeInitializes the RNG MSP. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval None + */ +__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_MspDeInit must be implemented in the user file. + */ +} + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User RNG Callback + * To be used instead of the weak predefined callback + * @param hrng RNG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID + * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (HAL_RNG_STATE_READY == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = pCallback; + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RNG_STATE_RESET == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an RNG Callback + * RNG callback is redirected to the weak predefined callback + * @param hrng RNG handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID + * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + + if (HAL_RNG_STATE_READY == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RNG_STATE_RESET == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Data Ready RNG Callback + * To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback + * @param hrng RNG handle + * @param pCallback pointer to the Data Ready Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hrng); + + if (HAL_RNG_STATE_READY == hrng->State) + { + hrng->ReadyDataCallback = pCallback; + } + else + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrng); + return status; +} + +/** + * @brief UnRegister the Data Ready RNG Callback + * Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback + * @param hrng RNG handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hrng); + + if (HAL_RNG_STATE_READY == hrng->State) + { + hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */ + } + else + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrng); + return status; +} + +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup RNG_Exported_Functions_Group2 + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Get the 32 bit Random number + (+) Get the 32 bit Random number with interrupt enabled + (+) Handle RNG interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Generates a 32-bit random number. + * @note This function checks value of RNG_FLAG_DRDY flag to know if valid + * random number is available in the DR register (RNG_FLAG_DRDY flag set + * whenever a random number is available through the RNG_DR register). + * After transitioning from 0 to 1 (random number available), + * RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading + * four words from the RNG_DR register, i.e. further function calls + * will immediately return a new u32 random number (additional words are + * available and can be read by the application, till RNG_FLAG_DRDY flag remains high). + * @note When no more random number data is available in DR register, RNG_FLAG_DRDY + * flag is automatically cleared. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @param random32bit pointer to generated random number variable if successful. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hrng); + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + /* Check if there is a seed error */ + if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; + /* Reset from seed error */ + status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + return status; + } + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if data register contains valid random data */ + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } + } + } + + /* Get a 32bit Random number */ + hrng->RandomNumber = hrng->Instance->DR; + /* In case of seed error, the value available in the RNG_DR register must not + be used as it may not have enough entropy */ + if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + { + /* Update the error code and status */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; + status = HAL_ERROR; + } + else /* No seed error */ + { + *random32bit = hrng->RandomNumber; + } + hrng->State = HAL_RNG_STATE_READY; + } + else + { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + + return status; +} + +/** + * @brief Generates a 32-bit random number in interrupt mode. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hrng); + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ + __HAL_RNG_ENABLE_IT(hrng); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Handles RNG interrupt request. + * @note In the case of a clock error, the RNG is no more able to generate + * random numbers because the PLL48CLK clock is not correct. User has + * to check that the clock controller is correctly configured to provide + * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). + * The clock error has no impact on the previously generated + * random numbers, and the RNG_DR register contents can be used. + * @note In the case of a seed error, the generation of random numbers is + * interrupted as long as the SECS bit is '1'. If a number is + * available in the RNG_DR register, it must not be used because it may + * not have enough entropy. In this case, it is recommended to clear the + * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable + * the RNG peripheral to reinitialize and restart the RNG. + * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS + * or CEIS are set. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval None + + */ +void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) +{ + uint32_t rngclockerror = 0U; + uint32_t itflag = hrng->Instance->SR; + + /* RNG clock error interrupt occurred */ + if ((itflag & RNG_IT_CEI) == RNG_IT_CEI) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; + rngclockerror = 1U; + } + else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI) + { + /* Check if Seed Error Current Status (SECS) is set */ + if ((itflag & RNG_FLAG_SECS) != RNG_FLAG_SECS) + { + /* RNG IP performed the reset automatically (auto-reset) */ + /* Clear bit SEIS */ + CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI); + } + else + { + /* Seed Error has not been recovered : Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; + rngclockerror = 1U; + /* Disable the IT */ + __HAL_RNG_DISABLE_IT(hrng); + } + } + else + { + /* Nothing to do */ + } + + if (rngclockerror == 1U) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_ERROR; + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Error callback */ + hrng->ErrorCallback(hrng); +#else + /* Call legacy weak Error callback */ + HAL_RNG_ErrorCallback(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + + /* Clear the clock error flag */ + __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI); + + return; + } + + /* Check RNG data ready interrupt occurred */ + if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY) + { + /* Generate random number once, so disable the IT */ + __HAL_RNG_DISABLE_IT(hrng); + + /* Get the 32bit Random number (DRDY flag automatically cleared) */ + hrng->RandomNumber = hrng->Instance->DR; + + if (hrng->State != HAL_RNG_STATE_ERROR) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Data Ready callback */ + hrng->ReadyDataCallback(hrng, hrng->RandomNumber); +#else + /* Call legacy weak Data Ready callback */ + HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Read latest generated random number. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval random value + */ +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng) +{ + return (hrng->RandomNumber); +} + +/** + * @brief Data Ready callback in non-blocking mode. + * @note When RNG_FLAG_DRDY flag value is set, first random number has been read + * from DR register in IRQ Handler and is provided as callback parameter. + * Depending on valid data available in the conditioning output buffer, + * additional words can be read by the application from DR register till + * DRDY bit remains high. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @param random32bit generated random number. + * @retval None + */ +__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + UNUSED(random32bit); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_ReadyDataCallback must be implemented in the user file. + */ +} + +/** + * @brief RNG error callbacks. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval None + */ +__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_ErrorCallback must be implemented in the user file. + */ +} +/** + * @} + */ + + +/** @addtogroup RNG_Exported_Functions_Group3 + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the RNG state. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval HAL state + */ +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng) +{ + return hrng->State; +} + +/** + * @brief Return the RNG handle error code. + * @param hrng: pointer to a RNG_HandleTypeDef structure. + * @retval RNG Error Code + */ +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng) +{ + /* Return RNG Error Code */ + return hrng->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup RNG_Private_Functions + * @{ + */ + +/** + * @brief RNG sequence to recover from a seed error + * @param hrng pointer to a RNG_HandleTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng) +{ + __IO uint32_t count = 0U; + + /*Check if seed error current status (SECS)is set */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET) + { + /* RNG performed the reset automatically (auto-reset) */ + /* Clear bit SEIS */ + CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI); + } + else /* Sequence to fully recover from a seed error*/ + { + /* Writing bit CONDRST=1*/ + SET_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + /* Writing bit CONDRST=0*/ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + + /* Wait for conditioning reset process to be completed */ + count = RNG_TIMEOUT_VALUE; + do + { + count-- ; + if (count == 0U) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Error callback */ + hrng->ErrorCallback(hrng); +#else + /* Call legacy weak Error callback */ + HAL_RNG_ErrorCallback(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)); + + if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + { + /* Clear bit SEIS */ + CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI); + } + + /* Wait for SECS to be cleared */ + count = RNG_TIMEOUT_VALUE; + do + { + count-- ; + if (count == 0U) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Error callback */ + hrng->ErrorCallback(hrng); +#else + /* Call legacy weak Error callback */ + HAL_RNG_ErrorCallback(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_FLAG_SECS)); + } + /* Update the error code */ + hrng->ErrorCode &= ~ HAL_RNG_ERROR_SEED; + return HAL_OK; +} + +/** + * @} + */ + + +#endif /* HAL_RNG_MODULE_ENABLED */ +/** + * @} + */ + +#endif /* RNG */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rng_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rng_ex.c new file mode 100644 index 00000000000..80ac5ebf662 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rng_ex.c @@ -0,0 +1,339 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_rng_ex.c + * @author MCD Application Team + * @brief Extended RNG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Random Number Generator (RNG) peripheral: + * + Lock configuration functions + * + Reset the RNG + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#if defined(RNG) + +/** @addtogroup RNGEx + * @brief RNG Extended HAL module driver. + * @{ + */ + +#ifdef HAL_RNG_MODULE_ENABLED +#if defined(RNG_CR_CONDRST) +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RNGEx_Private_Constants + * @{ + */ +#define RNG_TIMEOUT_VALUE 2U +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions prototypes ----------------------------------------------*/ +/* Private functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions + * @{ + */ + +/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration and lock functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the RNG with the specified parameters in the RNG_ConfigTypeDef + (+) Lock RNG configuration Allows user to lock a configuration until next reset. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the RNG with the specified parameters in the + * RNG_ConfigTypeDef. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @param pConf pointer to a RNG_ConfigTypeDef structure that contains + * the configuration information for RNG module + + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf) +{ + uint32_t tickstart; + uint32_t cr_value; + HAL_StatusTypeDef status ; + + /* Check the RNG handle allocation */ + if ((hrng == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); + assert_param(IS_RNG_CLOCK_DIVIDER(pConf->ClockDivider)); + assert_param(IS_RNG_NIST_COMPLIANCE(pConf->NistCompliance)); + assert_param(IS_RNG_CONFIG1(pConf->Config1)); + assert_param(IS_RNG_CONFIG2(pConf->Config2)); + assert_param(IS_RNG_CONFIG3(pConf->Config3)); + assert_param(IS_RNG_ARDIS(pConf->AutoReset)); + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Disable RNG */ + __HAL_RNG_DISABLE(hrng); + + /* RNG CR register configuration. Set value in CR register for : + - NIST Compliance setting + - Clock divider value + - Automatic reset to clear SECS bit + - CONFIG 1, CONFIG 2 and CONFIG 3 values */ + cr_value = (uint32_t)(pConf->ClockDivider | pConf->NistCompliance | pConf->AutoReset + | (pConf->Config1 << RNG_CR_RNG_CONFIG1_Pos) + | (pConf->Config2 << RNG_CR_RNG_CONFIG2_Pos) + | (pConf->Config3 << RNG_CR_RNG_CONFIG3_Pos)); + + MODIFY_REG(hrng->Instance->CR, RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1 + | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3 | RNG_CR_ARDIS, + (uint32_t)(RNG_CR_CONDRST | cr_value)); + + /* RNG health test control in accordance with NIST */ + WRITE_REG(hrng->Instance->HTCR, pConf->HealthTest); + + /* Writing bit CONDRST=0*/ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for conditioning reset process to be completed */ + while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of prememption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } + } + } + + /* Enable RNG */ + __HAL_RNG_ENABLE(hrng); + + /* Initialize the RNG state */ + hrng->State = HAL_RNG_STATE_READY; + + /* function status */ + status = HAL_OK; + } + else + { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return the function status */ + return status; +} + +/** + * @brief Get the RNG Configuration and fill parameters in the + * RNG_ConfigTypeDef. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @param pConf pointer to a RNG_ConfigTypeDef structure that contains + * the configuration information for RNG module + + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf) +{ + + HAL_StatusTypeDef status ; + + /* Check the RNG handle allocation */ + if ((hrng == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Get RNG parameters */ + pConf->Config1 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos) ; + pConf->Config2 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos); + pConf->Config3 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos); + pConf->ClockDivider = (hrng->Instance->CR & RNG_CR_CLKDIV); + pConf->NistCompliance = (hrng->Instance->CR & RNG_CR_NISTC); + pConf->AutoReset = (hrng->Instance->CR & RNG_CR_ARDIS); + pConf->HealthTest = (hrng->Instance->HTCR); + + /* Initialize the RNG state */ + hrng->State = HAL_RNG_STATE_READY; + + /* function status */ + status = HAL_OK; + } + else + { + hrng->ErrorCode |= HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return the function status */ + return status; +} + +/** + * @brief RNG current configuration lock. + * @note This function allows to lock RNG peripheral configuration. + * Once locked, HW RNG reset has to be performed prior any further + * configuration update. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) +{ + HAL_StatusTypeDef status; + + /* Check the RNG handle allocation */ + if (hrng == NULL) + { + return HAL_ERROR; + } + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Perform RNG configuration Lock */ + MODIFY_REG(hrng->Instance->CR, RNG_CR_CONFIGLOCK, RNG_CR_CONFIGLOCK); + + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_READY; + + /* function status */ + status = HAL_OK; + } + else + { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return the function status */ + return status; +} + + +/** + * @} + */ + +/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function + * @brief Recover from seed error function + * +@verbatim + =============================================================================== + ##### Recover from seed error function ##### + =============================================================================== + [..] This section provide function allowing to: + (+) Recover from a seed error + +@endverbatim + * @{ + */ + +/** + * @brief RNG sequence to recover from a seed error + * @param hrng: pointer to a RNG_HandleTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) +{ + HAL_StatusTypeDef status; + + /* Check the RNG handle allocation */ + if (hrng == NULL) + { + return HAL_ERROR; + } + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* sequence to fully recover from a seed error */ + status = RNG_RecoverSeedError(hrng); + } + else + { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return the function status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RNG_CR_CONDRST */ +#endif /* HAL_RNG_MODULE_ENABLED */ +/** + * @} + */ + +#endif /* RNG */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rtc.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rtc.c new file mode 100644 index 00000000000..adee0c534fa --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rtc.c @@ -0,0 +1,2270 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_rtc.c + * @author MCD Application Team + * @brief RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real-Time Clock (RTC) peripheral: + * + Initialization/de-initialization functions + * + Calendar (Time and Date) configuration + * + Alarms (Alarm A and Alarm B) configuration + * + WakeUp Timer configuration + * + TimeStamp configuration + * + Tampers configuration + * + Backup Data Registers configuration + * + RTC Tamper and TimeStamp Pins Selection + * + Interrupts and flags management + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### RTC Operating Condition ##### + =============================================================================== + [..] The real-time clock (RTC) and the RTC backup registers can be powered + from the VBAT voltage when the main VDD supply is powered off. + To retain the content of the RTC backup registers and supply the RTC + when VDD is turned off, VBAT pin can be connected to an optional + standby voltage supplied by a battery or by another source. + + ##### Backup Domain Reset ##### + =============================================================================== + [..] The backup domain reset sets all RTC registers and the RCC_BDCR register + to their reset values. + A backup domain reset is generated when one of the following events occurs: + (#) Software reset, triggered by setting the BDRST bit in the + RCC Backup domain control register (RCC_BDCR). + (#) VDD or VBAT power on, if both supplies have previously been powered off. + (#) Tamper detection event resets all data backup registers. + + ##### Backup Domain Access ##### + ================================================================== + [..] After reset, the backup domain (RTC registers and RTC backup data registers) + is protected against possible unwanted write accesses. + [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + (+) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for + PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32) + (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. + + ##### How to use RTC Driver ##### + =================================================================== + [..] + (+) Enable the RTC domain access (see description in the section above). + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the HAL_RTC_Init() function. + + *** Time and Date configuration *** + =================================== + [..] + (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() + and HAL_RTC_SetDate() functions. + (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. + + *** Alarm configuration *** + =========================== + [..] + (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. + You can also configure the RTC Alarm with interrupt mode using the + HAL_RTC_SetAlarm_IT() function. + (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. + + ##### RTC and low power modes ##### + ================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate + function. + [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), + RTC wakeup, RTC tamper event detection and RTC time stamp event detection. + These RTC alternate functions can wake up the system from the Stop and + Standby low power modes. + [..] The system can also wake up from low power modes without depending + on an external interrupt (Auto-wakeup mode), by using the RTC alarm + or the RTC wakeup events. + [..] The RTC provides a programmable time base for waking up from the + Stop or Standby mode at regular intervals. + Wakeup from STOP and STANDBY modes is possible only when the RTC clock source + is LSE or LSI. + + *** Callback registration *** + ============================================= + When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. This is the recommended configuration + in order to optimize memory/code consumption footprint/performances. + + The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_RTC_RegisterCallback() to register an interrupt callback. + + Function HAL_RTC_RegisterCallback() allows to register following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) AlarmBEventCallback : RTC Alarm B Event callback. + (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. + (+) SSRUEventCallback : RTC SSRU Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) Tamper4EventCallback : RTC Tamper 4 Event callback. + (+) Tamper5EventCallback : RTC Tamper 5 Event callback. + (+) Tamper6EventCallback : RTC Tamper 6 Event callback. + (+) Tamper7EventCallback : RTC Tamper 7 Event callback. + (+) Tamper8EventCallback : RTC Tamper 8 Event callback. + (+) InternalTamper1EventCallback : RTC InternalTamper 1 Event callback. + (+) InternalTamper2EventCallback : RTC InternalTamper 2 Event callback. + (+) InternalTamper3EventCallback : RTC InternalTamper 3 Event callback. + (+) InternalTamper4EventCallback : RTC InternalTamper 4 Event callback. + (+) InternalTamper5EventCallback : RTC InternalTamper 5 Event callback. + (+) InternalTamper6EventCallback : RTC InternalTamper 6 Event callback. + (+) InternalTamper7EventCallback : RTC InternalTamper 7 Event callback. + (+) InternalTamper8EventCallback : RTC InternalTamper 8 Event callback. + (+) InternalTamper9EventCallback : RTC InternalTamper 9 Event callback. + (+) InternalTamper11EventCallback : RTC InternalTamper 11 Event callback. + (+) InternalTamper15EventCallback : RTC InternalTamper 15 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) AlarmBEventCallback : RTC Alarm B Event callback. + (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. + (+) SSRUEventCallback : RTC SSRU Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) Tamper4EventCallback : RTC Tamper 4 Event callback. + (+) Tamper5EventCallback : RTC Tamper 5 Event callback. + (+) Tamper6EventCallback : RTC Tamper 6 Event callback. + (+) Tamper7EventCallback : RTC Tamper 7 Event callback. + (+) Tamper8EventCallback : RTC Tamper 8 Event callback. + (+) InternalTamper1EventCallback : RTC InternalTamper 1 Event callback. + (+) InternalTamper2EventCallback : RTC InternalTamper 2 Event callback. + (+) InternalTamper3EventCallback : RTC InternalTamper 3 Event callback. + (+) InternalTamper4EventCallback : RTC InternalTamper 4 Event callback. + (+) InternalTamper5EventCallback : RTC InternalTamper 5 Event callback. + (+) InternalTamper6EventCallback : RTC InternalTamper 6 Event callback. + (+) InternalTamper7EventCallback : RTC InternalTamper 7 Event callback. + (+) InternalTamper8EventCallback : RTC InternalTamper 8 Event callback. + (+) InternalTamper9EventCallback : RTC InternalTamper 9 Event callback. + (+) InternalTamper11EventCallback : RTC InternalTamper 11 Event callback. + (+) InternalTamper15EventCallback : RTC InternalTamper 15 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + + By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, + all callbacks are set to the corresponding weak functions : + examples AlarmAEventCallback(), TimeStampEventCallback(). + Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function + in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null + (not registered beforehand). + If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() + or HAL_RTC_Init() function. + + When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + + +/** @addtogroup RTC + * @brief RTC HAL module driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup RTC_Exported_Functions + * @{ + */ + +/** @addtogroup RTC_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + RTC registers Write protection, enter and exit the RTC initialization mode, + RTC registers synchronization check and reference clock detection enable. + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize power consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WPR. + (#) To configure the RTC Calendar, user application should enter + initialization mode. In this mode, the calendar counter is stopped + and its value can be updated. When the initialization sequence is + complete, the calendar restarts counting after 4 RTCCLK cycles. + (#) To read the calendar through the shadow registers after Calendar + initialization, calendar update or after wakeup from low power modes + the software must first clear the RSF flag. The software must then + wait until it is set again before reading the calendar, which means + that the calendar registers have been correctly copied into the + RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function + implements the above software sequence (RSF clear and RSF check). + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the RTC peripheral + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the RTC peripheral state */ + if (hrtc != NULL) + { + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); + assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); + assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); +#if defined(RTC_CR_OSEL) + assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); + assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); + assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); + assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp)); +#endif /* RTC_CR_OSEL */ +#if defined(RTC_CR_OUT2EN) + assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap)); +#endif /* RTC_CR_OUT2EN */ + assert_param(IS_RTC_BINARY_MODE(hrtc->Init.BinMode)); + assert_param(IS_RTC_BINARY_MIX_BCDU(hrtc->Init.BinMixBcdU)); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + /* Legacy weak AlarmAEventCallback */ + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; + /* Legacy weak AlarmBEventCallback */ + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; + /* Legacy weak TimeStampEventCallback */ + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; + /* Legacy weak WakeUpTimerEventCallback */ + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; + /* Legacy weak SSRUEventCallback */ + hrtc->SSRUEventCallback = HAL_RTCEx_SSRUEventCallback; + /* Legacy weak Tamper1EventCallback */ + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; + /* Legacy weak Tamper2EventCallback */ + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; + /* Legacy weak Tamper3EventCallback */ + hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; + /* Legacy weak Tamper4EventCallback */ + hrtc->Tamper4EventCallback = HAL_RTCEx_Tamper4EventCallback; + /* Legacy weak Tamper5EventCallback */ + hrtc->Tamper5EventCallback = HAL_RTCEx_Tamper5EventCallback; + /* Legacy weak Tamper6EventCallback */ + hrtc->Tamper6EventCallback = HAL_RTCEx_Tamper6EventCallback; + /* Legacy weak Tamper7EventCallback */ + hrtc->Tamper7EventCallback = HAL_RTCEx_Tamper7EventCallback; + /* Legacy weak Tamper8EventCallback */ + hrtc->Tamper8EventCallback = HAL_RTCEx_Tamper8EventCallback; + /* Legacy weak InternalTamper1EventCallback */ + hrtc->InternalTamper1EventCallback = HAL_RTCEx_InternalTamper1EventCallback; + /* Legacy weak InternalTamper2EventCallback */ + hrtc->InternalTamper2EventCallback = HAL_RTCEx_InternalTamper2EventCallback; + /* Legacy weak InternalTamper3EventCallback */ + hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; + /* Legacy weak InternalTamper4EventCallback */ + hrtc->InternalTamper4EventCallback = HAL_RTCEx_InternalTamper4EventCallback; + /* Legacy weak InternalTamper5EventCallback */ + hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback; + /* Legacy weak InternalTamper6EventCallback */ + hrtc->InternalTamper6EventCallback = HAL_RTCEx_InternalTamper6EventCallback; + /* Legacy weak InternalTamper7EventCallback */ + hrtc->InternalTamper7EventCallback = HAL_RTCEx_InternalTamper7EventCallback; + /* Legacy weak InternalTamper8EventCallback */ + hrtc->InternalTamper8EventCallback = HAL_RTCEx_InternalTamper8EventCallback; + /* Legacy weak InternalTamper9EventCallback */ + hrtc->InternalTamper9EventCallback = HAL_RTCEx_InternalTamper9EventCallback; + /* Legacy weak InternalTamper11EventCallback */ + hrtc->InternalTamper11EventCallback = HAL_RTCEx_InternalTamper11EventCallback; + /* Legacy weak InternalTamper15EventCallback */ + hrtc->InternalTamper15EventCallback = HAL_RTCEx_InternalTamper15EventCallback; + + if (hrtc->MspInitCallback == NULL) + { + hrtc->MspInitCallback = HAL_RTC_MspInit; + } + /* Init the low level hardware */ + hrtc->MspInitCallback(hrtc); + + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else + if (hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + } +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Check if the calendar has been not initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) + { + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { +#if defined(RTC_CR_OSEL) + /* Clear RTC_CR FMT, OSEL and POL Bits */ + CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); + + /* Set RTC_CR register */ + SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); +#else + /* Clear RTC_CR FMT Bits */ + CLEAR_BIT(RTC->CR, RTC_CR_FMT); + + /* Set RTC_CR register */ + SET_BIT(RTC->CR, hrtc->Init.HourFormat); +#endif /* RTC_CR_OSEL */ + + /* Configure the RTC PRER */ + WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + + /* Configure the Binary mode */ + MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + +#if defined(RTC_CR_OSEL) + if (status == HAL_OK) + { +#if defined(RTC_CR_OUT2EN) + MODIFY_REG(RTC->CR, \ + RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); +#else + MODIFY_REG(RTC->CR, \ + RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE, \ + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType); +#endif /* RTC_CR_OUT2EN */ + } +#endif /* RTC_CR_OSEL */ + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + } + else + { + /* Calendar is already initialized */ + /* Set flag to OK */ + status = HAL_OK; + } + + if (status == HAL_OK) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + } + } + + return status; +} + +/** + * @brief DeInitialize the RTC peripheral. + * @note This function does not reset the RTC Backup Data registers. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t tickstart; + + /* Check RTC handler */ + if (hrtc != NULL) + { + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Reset All CR bits except CR[2:0] (which cannot be written before bit + WUTE of CR is cleared) */ + CLEAR_REG(RTC->CR); + + /* Reset TR and DR registers */ + WRITE_REG(RTC->DR, (uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + CLEAR_REG(RTC->TR); + + /* Reset other RTC registers */ + WRITE_REG(RTC->PRER, ((uint32_t)(RTC_PRER_PREDIV_A | 0xFFU))); + CLEAR_REG(RTC->ALRMAR); + CLEAR_REG(RTC->ALRMBR); + CLEAR_REG(RTC->SHIFTR); + CLEAR_REG(RTC->CALR); + CLEAR_REG(RTC->ALRMASSR); + CLEAR_REG(RTC->ALRMBSSR); + CLEAR_BIT(RTC->ICSR, (RTC_ICSR_BCDU_Msk | RTC_ICSR_BIN_Msk)); + WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSOVF | RTC_SCR_CTSF | RTC_SCR_CWUTF | RTC_SCR_CALRBF | \ + RTC_SCR_CALRAF); +#if defined (RTC_PRIVCFGR_ALRAPRIV) + CLEAR_REG(RTC->PRIVCFGR); +#endif /* RTC_PRIVCFGR_ALRAPRIV */ + + /* Exit initialization mode */ + status = RTC_ExitInitMode(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + + if (status == HAL_OK) + { + /* Wait till WUTWF is set (to be able to reset CR[2:0] and WUTR) and if + timeout is reached exit */ + tickstart = HAL_GetTick(); + + while ((((hrtc->Instance->ICSR) & RTC_ICSR_WUTWF) == 0U) && (status != HAL_TIMEOUT)) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + status = HAL_TIMEOUT; + } + else + { + break; + } + } + } + + /* Reset RTC CR register bits [2:0] */ + CLEAR_REG(RTC->CR); + + /* Reset RTC WUTR register */ + WRITE_REG(RTC->WUTR, RTC_WUTR_WUT); + + /* Reset TAMP registers */ + CLEAR_REG(TAMP->CR1); + CLEAR_REG(TAMP->CR2); + CLEAR_REG(TAMP->CR3); + CLEAR_REG(TAMP->FLTCR); + WRITE_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL); + CLEAR_REG(TAMP->ATOR); + CLEAR_REG(TAMP->ATCR2); + CLEAR_REG(TAMP->PRIVCFGR); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hrtc->MspDeInitCallback(hrtc); + +#else + /* De-Initialize RTC MSP */ + HAL_RTC_MspDeInit(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + } + } + + return status; +} + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User RTC Callback + * To be used instead of the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID + * @arg @ref HAL_RTC_SSRU_EVENT_CB_ID SSRU Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID + * @arg @ref HAL_RTC_TAMPER4_EVENT_CB_ID Tamper 4 Callback ID + * @arg @ref HAL_RTC_TAMPER5_EVENT_CB_ID Tamper 5 Callback ID + * @arg @ref HAL_RTC_TAMPER6_EVENT_CB_ID Tamper 6 Callback ID + * @arg @ref HAL_RTC_TAMPER7_EVENT_CB_ID Tamper 7 Callback ID + * @arg @ref HAL_RTC_TAMPER8_EVENT_CB_ID Tamper 8 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID Internal Tamper 7 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID Internal Tamper 9 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID Internal Tamper 11 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER15_EVENT_CB_ID Internal Tamper 15 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @param pCallback pointer to the Callback function + * @note The HAL_RTC_RegisterCallback() may be called before HAL_RTC_Init() in HAL_RTC_STATE_RESET + * to register callbacks for HAL_RTC_MSPINIT_CB_ID and HAL_RTC_MSPDEINIT_CB_ID. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, + pRTC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + if (HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = pCallback; + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = pCallback; + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = pCallback; + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = pCallback; + break; + + case HAL_RTC_SSRU_EVENT_CB_ID : + hrtc->SSRUEventCallback = pCallback; + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER3_EVENT_CB_ID : + hrtc->Tamper3EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER4_EVENT_CB_ID : + hrtc->Tamper4EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER5_EVENT_CB_ID : + hrtc->Tamper5EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER6_EVENT_CB_ID : + hrtc->Tamper6EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER7_EVENT_CB_ID : + hrtc->Tamper7EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER8_EVENT_CB_ID : + hrtc->Tamper8EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID : + hrtc->InternalTamper1EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID : + hrtc->InternalTamper2EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : + hrtc->InternalTamper3EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID : + hrtc->InternalTamper4EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : + hrtc->InternalTamper5EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID : + hrtc->InternalTamper6EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID : + hrtc->InternalTamper7EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID : + hrtc->InternalTamper8EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID : + hrtc->InternalTamper9EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID : + hrtc->InternalTamper11EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER15_EVENT_CB_ID : + hrtc->InternalTamper15EventCallback = pCallback; + break; + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an RTC Callback + * RTC callback is redirected to the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID + * @arg @ref HAL_RTC_SSRU_EVENT_CB_ID SSRU Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID + * @arg @ref HAL_RTC_TAMPER4_EVENT_CB_ID Tamper 4 Callback ID + * @arg @ref HAL_RTC_TAMPER5_EVENT_CB_ID Tamper 5 Callback ID + * @arg @ref HAL_RTC_TAMPER6_EVENT_CB_ID Tamper 6 Callback ID + * @arg @ref HAL_RTC_TAMPER7_EVENT_CB_ID Tamper 7 Callback ID + * @arg @ref HAL_RTC_TAMPER8_EVENT_CB_ID Tamper 8 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID Internal Tamper 4 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID Internal Tamper 7 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID Internal Tamper 9 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID Internal Tamper 11 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER15_EVENT_CB_ID Internal Tamper 15 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @note The HAL_RTC_UnRegisterCallback() may be called before HAL_RTC_Init() in HAL_RTC_STATE_RESET + * to un-register callbacks for HAL_RTC_MSPINIT_CB_ID and HAL_RTC_MSPDEINIT_CB_ID. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + /* Legacy weak AlarmAEventCallback */ + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + /* Legacy weak AlarmBEventCallback */ + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + /* Legacy weak TimeStampEventCallback */ + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + /* Legacy weak WakeUpTimerEventCallback */ + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; + break; + + case HAL_RTC_SSRU_EVENT_CB_ID : + /* Legacy weak SSRUEventCallback */ + hrtc->SSRUEventCallback = HAL_RTCEx_SSRUEventCallback; + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + /* Legacy weak Tamper1EventCallback */ + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; + break; + + case HAL_RTC_TAMPER2_EVENT_CB_ID : + /* Legacy weak Tamper2EventCallback */ + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; + break; + + case HAL_RTC_TAMPER3_EVENT_CB_ID : + /* Legacy weak Tamper3EventCallback */ + hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; + break; + + case HAL_RTC_TAMPER4_EVENT_CB_ID : + /* Legacy weak Tamper4EventCallback */ + hrtc->Tamper4EventCallback = HAL_RTCEx_Tamper4EventCallback; + break; + + case HAL_RTC_TAMPER5_EVENT_CB_ID : + /* Legacy weak Tamper5EventCallback */ + hrtc->Tamper5EventCallback = HAL_RTCEx_Tamper5EventCallback; + break; + + case HAL_RTC_TAMPER6_EVENT_CB_ID : + /* Legacy weak Tamper6EventCallback */ + hrtc->Tamper6EventCallback = HAL_RTCEx_Tamper6EventCallback; + break; + + case HAL_RTC_TAMPER7_EVENT_CB_ID : + /* Legacy weak Tamper7EventCallback */ + hrtc->Tamper7EventCallback = HAL_RTCEx_Tamper7EventCallback; + break; + + case HAL_RTC_TAMPER8_EVENT_CB_ID : + /* Legacy weak Tamper8EventCallback */ + hrtc->Tamper8EventCallback = HAL_RTCEx_Tamper8EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID : + /* Legacy weak InternalTamper1EventCallback */ + hrtc->InternalTamper1EventCallback = HAL_RTCEx_InternalTamper1EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID : + /* Legacy weak InternalTamper2EventCallback */ + hrtc->InternalTamper2EventCallback = HAL_RTCEx_InternalTamper2EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : + /* Legacy weak InternalTamper3EventCallback */ + hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID : + /* Legacy weak InternalTamper4EventCallback */ + hrtc->InternalTamper4EventCallback = HAL_RTCEx_InternalTamper4EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : + /* Legacy weak InternalTamper5EventCallback */ + hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID : + /* Legacy weak InternalTamper6EventCallback */ + hrtc->InternalTamper6EventCallback = HAL_RTCEx_InternalTamper6EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID : + /* Legacy weak InternalTamper7EventCallback */ + hrtc->InternalTamper7EventCallback = HAL_RTCEx_InternalTamper7EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID : + /* Legacy weak InternalTamper8EventCallback */ + hrtc->InternalTamper8EventCallback = HAL_RTCEx_InternalTamper8EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID : + /* Legacy weak InternalTamper9EventCallback */ + hrtc->InternalTamper9EventCallback = HAL_RTCEx_InternalTamper9EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID : + /* Legacy weak InternalTamper11EventCallback */ + hrtc->InternalTamper11EventCallback = HAL_RTCEx_InternalTamper11EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER15_EVENT_CB_ID : + /* Legacy weak InternalTamper15EventCallback */ + hrtc->InternalTamper15EventCallback = HAL_RTCEx_InternalTamper15EventCallback; + break; + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @brief Initialize the RTC MSP. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the RTC MSP. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group2 + * @brief RTC Time and Date functions + * +@verbatim + =============================================================================== + ##### RTC Time and Date functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Time and Date features + +@endverbatim + * @{ + */ + +/** + * @brief Set RTC current time. + * @param hrtc RTC handle + * @param sTime Pointer to Time structure + * if Binary mode is RTC_BINARY_ONLY, this parameter is not used and RTC_SSR will be automatically + * reset to 0xFFFFFFFF + * else sTime->SubSeconds is not used and RTC_SSR will be automatically reset to the + * A 7-bit async prescaler (RTC_PRER_PREDIV_A) + * @param Format Format of sTime->Hours, sTime->Minutes and sTime->Seconds. + * if Binary mode is RTC_BINARY_ONLY, this parameter is not used + * else this parameter can be one of the following values + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t tmpreg; + HAL_StatusTypeDef status; + +#ifdef USE_FULL_ASSERT + /* Check the parameters depending of the Binary mode with 32-bit free-running counter configuration */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_NONE) + { + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + } +#endif /* USE_FULL_ASSERT */ + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Check Binary mode ((32-bit free-running counter) */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) != RTC_BINARY_ONLY) + { + if (Format == RTC_FORMAT_BIN) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(sTime->Hours)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(sTime->Hours)); + } + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); + + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Seconds) << RTC_TR_SU_Pos) | \ + (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos)); + } + else + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t)(sTime->Seconds) << RTC_TR_SU_Pos) | \ + ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos)); + } + + /* Set the RTC_TR register */ + WRITE_REG(RTC->TR, (tmpreg & RTC_TR_RESERVED_MASK)); + + /* Clear the bits to be configured */ + CLEAR_BIT(RTC->CR, RTC_CR_BKP); + } + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Get RTC current time. + * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds + * value in second fraction ratio with time unit following generic formula: + * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit + * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * in the higher-order calendar shadow registers to ensure consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers until Current date is read + * to ensure consistency between the time and date values. + * @param hrtc RTC handle + * @param sTime + * if Binary mode is RTC_BINARY_ONLY, sTime->SubSeconds only is updated + * else + * Pointer to Time structure with Hours, Minutes and Seconds fields returned + * with input format (BIN or BCD), also SubSeconds field returning the + * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler + * factor to be used for second fraction ratio computation. + * @param Format Format of sTime->Hours, sTime->Minutes and sTime->Seconds. + * if Binary mode is RTC_BINARY_ONLY, this parameter is not used + * else this parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t tmpreg; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Get subseconds structure field from the corresponding register */ + sTime->SubSeconds = READ_REG(RTC->SSR); + + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) != RTC_BINARY_ONLY) + { + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get SecondFraction structure field from the corresponding register field */ + sTime->SecondFraction = (uint32_t)(READ_REG(RTC->PRER) & RTC_PRER_PREDIV_S); + + /* Get the TR register */ + tmpreg = (uint32_t)(READ_REG(RTC->TR) & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos); + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); + sTime->Seconds = (uint8_t)((tmpreg & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos); + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + { + /* Convert the time structure parameters to Binary format */ + sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); + sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); + sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); + } + } + + return HAL_OK; +} + +/** + * @brief Set RTC current date. + * @param hrtc RTC handle + * @param sDate Pointer to date structure + * @param Format Format of sDate->Year, sDate->Month and sDate->Weekday. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t datetmpreg; + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) + { + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); + } + + assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); + + if (Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_YEAR(sDate->Year)); + assert_param(IS_RTC_MONTH(sDate->Month)); + assert_param(IS_RTC_DATE(sDate->Date)); + + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Date) << RTC_DR_DU_Pos) | \ + ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); + + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ + (((uint32_t)sDate->Date) << RTC_DR_DU_Pos) | \ + (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos)); + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Set the RTC_DR register */ + WRITE_REG(RTC->DR, (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK)); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Get RTC current date. + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * in the higher-order calendar shadow registers to ensure consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers until Current date is read. + * @param hrtc RTC handle + * @param sDate Pointer to Date structure + * @param Format Format of sDate->Year, sDate->Month and sDate->Weekday. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t datetmpreg; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the DR register */ + datetmpreg = (uint32_t)(READ_REG(RTC->DR) & RTC_DR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos); + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos); + sDate->Date = (uint8_t)((datetmpreg & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos); + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos); + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + { + /* Convert the date structure parameters to Binary format */ + sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); + sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); + sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); + } + return HAL_OK; +} + +/** + * @brief Daylight Saving Time, Add one hour to the calendar in one single operation + * without going through the initialization procedure. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_Add1Hour(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set RTC_CR_ADD1H Bit */ + SET_BIT(RTC->CR, RTC_CR_ADD1H); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Subtract one hour from the calendar in one + * single operation without going through the initialization procedure. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_Sub1Hour(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set RTC_CR_SUB1H Bit */ + SET_BIT(RTC->CR, RTC_CR_SUB1H); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Set the store operation bit. + * @note It can be used by the software in order to memorize the DST status. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Set RTC_CR_BKP Bit */ + SET_BIT(RTC->CR, RTC_CR_BKP); +} + +/** + * @brief Daylight Saving Time, Clear the store operation bit. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Clear RTC_CR_BKP Bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BKP); +} + +/** + * @brief Daylight Saving Time, Read the store operation bit. + * @param hrtc RTC handle + * @retval operation see RTC_StoreOperation_Definitions + */ +uint32_t HAL_RTC_DST_ReadStoreOperation(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Get RTC_CR_BKP Bit */ + return READ_BIT(RTC->CR, RTC_CR_BKP); +} + + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group3 + * @brief RTC Alarm functions + * +@verbatim + =============================================================================== + ##### RTC Alarm functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Alarm feature + +@endverbatim + * @{ + */ +/** + * @brief Set the specified RTC Alarm. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * if Binary mode is RTC_BINARY_ONLY, 3 fields only are used + * sAlarm->AlarmTime.SubSeconds + * sAlarm->AlarmSubSecondMask + * sAlarm->BinaryAutoClr + * @param Format of the entered parameters. + * if Binary mode is RTC_BINARY_ONLY, this parameter is not used + * else this parameter can be one of the following values + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t tmpreg = 0; + uint32_t binary_mode; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + +#ifdef USE_FULL_ASSERT + /* Check the parameters depending of the Binary mode (32-bit free-running counter configuration) */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_NONE) + { + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); + } + else if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_ONLY) + { + assert_param(IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(sAlarm->AlarmSubSecondMask)); + assert_param(IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(sAlarm->BinaryAutoClr)); + } + else /* RTC_BINARY_MIX */ + { + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + /* In Binary Mix Mode, the RTC can not generate an alarm on a match + involving all calendar items + the upper SSR bits */ + assert_param((sAlarm->AlarmSubSecondMask >> RTC_ALRMASSR_MASKSS_Pos) <= + (8U + (READ_BIT(RTC->ICSR, RTC_ICSR_BCDU) >> RTC_ICSR_BCDU_Pos))); + } +#endif /* USE_FULL_ASSERT */ + + /* Get Binary mode (32-bit free-running counter configuration) */ + binary_mode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN); + + if (binary_mode != RTC_BINARY_ONLY) + { + if (Format == RTC_FORMAT_BIN) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + else /* format BCD */ + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + +#ifdef USE_FULL_ASSERT + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + +#endif /* USE_FULL_ASSERT */ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + } + + /* Configure the Alarm register */ + if (sAlarm->Alarm == RTC_ALARM_A) + { + /* Disable the Alarm A interrupt */ + + /* In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + + /* Clear flag alarm A */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + + if (binary_mode == RTC_BINARY_ONLY) + { + WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr); + } + else + { + WRITE_REG(RTC->ALRMAR, tmpreg); + WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask); + } + + WRITE_REG(RTC->ALRABINR, sAlarm->AlarmTime.SubSeconds); + + if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) + { + /* Configure the Alarm A output clear */ + SET_BIT(RTC->CR, RTC_CR_ALRAFCLR); + } + else + { + /* Disable the Alarm A output clear */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRAFCLR); + } + /* Configure the Alarm state: Enable Alarm */ + SET_BIT(RTC->CR, RTC_CR_ALRAE); + } + else + { + /* Disable the Alarm B interrupt */ + + /* In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + + /* Clear flag alarm B */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + + if (binary_mode == RTC_BINARY_ONLY) + { + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr); + } + else + { + WRITE_REG(RTC->ALRMBR, tmpreg); + + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask); + } + + WRITE_REG(RTC->ALRBBINR, sAlarm->AlarmTime.SubSeconds); + + if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) + { + /* Configure the Alarm B output clear */ + SET_BIT(RTC->CR, RTC_CR_ALRBFCLR); + } + else + { + /* Disable the Alarm B output clear */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRBFCLR); + } + + /* Configure the Alarm state: Enable Alarm */ + SET_BIT(RTC->CR, RTC_CR_ALRBE); + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Set the specified RTC Alarm with Interrupt. + * @note The application must ensure that the EXTI RTC interrupt line is configured and enabled. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * if Binary mode is RTC_BINARY_ONLY, 3 fields only are used + * sAlarm->AlarmTime.SubSeconds + * sAlarm->AlarmSubSecondMask + * sAlarm->BinaryAutoClr + * @param Format Specifies the format of the entered parameters. + * if Binary mode is RTC_BINARY_ONLY, this parameter is not used + * else this parameter can be one of the following values + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t tmpreg = 0; + uint32_t binary_mode; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + +#ifdef USE_FULL_ASSERT + /* Check the parameters depending of the Binary mode (32-bit free-running counter configuration) */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_NONE) + { + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); + } + else if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_ONLY) + { + assert_param(IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(sAlarm->AlarmSubSecondMask)); + assert_param(IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(sAlarm->BinaryAutoClr)); + } + else /* RTC_BINARY_MIX */ + { + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + /* In Binary Mix Mode, the RTC can not generate an alarm on a match + involving all calendar items + the upper SSR bits */ + assert_param((sAlarm->AlarmSubSecondMask >> RTC_ALRMASSR_MASKSS_Pos) <= + (8U + (READ_BIT(RTC->ICSR, RTC_ICSR_BCDU) >> RTC_ICSR_BCDU_Pos))); + } +#endif /* USE_FULL_ASSERT */ + + /* Get Binary mode (32-bit free-running counter configuration) */ + binary_mode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN); + + if (binary_mode != RTC_BINARY_ONLY) + { + if (Format == RTC_FORMAT_BIN) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + else /* Format BCD */ + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + +#ifdef USE_FULL_ASSERT + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + +#endif /* USE_FULL_ASSERT */ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + + } + } + + /* Configure the Alarm registers */ + if (sAlarm->Alarm == RTC_ALARM_A) + { + /* Disable the Alarm A interrupt */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + + /* Clear flag alarm A */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + + if (binary_mode == RTC_BINARY_ONLY) + { + RTC->ALRMASSR = sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr; + } + else + { + WRITE_REG(RTC->ALRMAR, tmpreg); + + WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask); + } + + WRITE_REG(RTC->ALRABINR, sAlarm->AlarmTime.SubSeconds); + + if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) + { + /* Configure the Alarm A output clear */ + SET_BIT(RTC->CR, RTC_CR_ALRAFCLR); + } + else + { + /* Disable the Alarm A output clear */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRAFCLR); + } + + /* Configure the Alarm interrupt */ + SET_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + } + else + { + /* Disable the Alarm B interrupt */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + + /* Clear flag alarm B */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + + if (binary_mode == RTC_BINARY_ONLY) + { + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr); + } + else + { + WRITE_REG(RTC->ALRMBR, tmpreg); + + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask); + } + + WRITE_REG(RTC->ALRBBINR, sAlarm->AlarmTime.SubSeconds); + + if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) + { + /* Configure the Alarm B Output clear */ + SET_BIT(RTC->CR, RTC_CR_ALRBFCLR); + } + else + { + /* Disable the Alarm B Output clear */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRBFCLR); + } + + /* Configure the Alarm interrupt */ + SET_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate the specified RTC Alarm. + * @param hrtc RTC handle + * @param Alarm Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) +{ + /* Check the parameters */ + assert_param(IS_RTC_ALARM(Alarm)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* In case of interrupt mode is used, the interrupt source must disabled */ + if (Alarm == RTC_ALARM_A) + { + CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + + /* AlarmA, Clear SSCLR */ + CLEAR_BIT(RTC->ALRMASSR, RTC_ALRMASSR_SSCLR); + } + else + { + CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + + /* AlarmB, Clear SSCLR */ + CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR); + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Get the RTC Alarm value and masks. + * @param hrtc RTC handle + * @param sAlarm Pointer to Date structure + * @param Alarm Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, + uint32_t Format) +{ + uint32_t tmpreg; + uint32_t subsecondtmpreg; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(Alarm)); + + if (Alarm == RTC_ALARM_A) + { + /* AlarmA */ + sAlarm->Alarm = RTC_ALARM_A; + + tmpreg = READ_REG(RTC->ALRMAR); + subsecondtmpreg = (uint32_t)(READ_REG(RTC->ALRMASSR) & RTC_ALRMASSR_SS); + + /* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)) >> RTC_ALRMAR_SU_Pos); + sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMAR_PM) >> RTC_ALRMAR_PM_Pos); + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + } + else + { + sAlarm->Alarm = RTC_ALARM_B; + + tmpreg = READ_REG(RTC->ALRMBR); + subsecondtmpreg = (uint32_t)(READ_REG(RTC->ALRMBSSR) & RTC_ALRMBSSR_SS); + + /* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> RTC_ALRMBR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> RTC_ALRMBR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU)) >> RTC_ALRMBR_SU_Pos); + sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMBR_PM) >> RTC_ALRMBR_PM_Pos); + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> RTC_ALRMBR_DU_Pos); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + } + + if (Format == RTC_FORMAT_BIN) + { + sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); + sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); + sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); + sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + } + + return HAL_OK; +} + +/** + * @brief Handle Alarm interrupt request. + * @note Alarm is available in driver. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get interrupt status */ + uint32_t tmp = READ_REG(RTC->MISR); + + if ((tmp & RTC_MISR_ALRAMF) != 0U) + { + /* Clear the AlarmA interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmAEventCallback(hrtc); +#else + HAL_RTC_AlarmAEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + if ((tmp & RTC_MISR_ALRBMF) != 0U) + { + /* Clear the AlarmB interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmBEventCallback(hrtc); +#else + HAL_RTCEx_AlarmBEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief Alarm A callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTC_AlarmAEventCallback could be implemented in the user file + */ +} + +/** + * @brief Handle Alarm A Polling request. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_ALRAF) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_ALRAF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + /* Clear the Alarm interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group4 + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Wait for RTC Time and Date Synchronization + +@endverbatim + * @{ + */ + +/** + * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart; + + /* Clear RSF flag */ + CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF); + + tickstart = HAL_GetTick(); + + /* Wait the registers to be synchronised */ + while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group5 + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Get RTC state + +@endverbatim + * @{ + */ +/** + * @brief Return the RTC handle state. + * @param hrtc RTC handle + * @retval HAL state + */ +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc) +{ + /* Return RTC handle state */ + return hrtc->State; +} + +/** + * @} + */ +/** + * @} + */ + +/** @addtogroup RTC_Private_Functions + * @{ + */ +/** + * @brief Enter the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + /* Check if the Initialization mode is set */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + /* Set the Initialization mode */ + SET_BIT(RTC->ICSR, RTC_ICSR_INIT); + + tickstart = HAL_GetTick(); + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + status = HAL_TIMEOUT; + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + } + else + { + break; + } + } + } + } + + return status; +} + +/** + * @brief Exit the RTC Initialization mode. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Exit Initialization mode */ + CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT); + + /* If CR_BYPSHAD bit = 0, wait for synchro */ + if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + status = HAL_TIMEOUT; + } + } + else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry. */ + { + /* Clear BYPSHAD bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + status = HAL_TIMEOUT; + } + /* Restore BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + } + return status; +} + +/** + * @brief Convert a 2 digit decimal to BCD format. + * @param Value Byte to be converted + * @retval Converted byte + */ +uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint32_t bcd_high = 0U; + uint8_t tmp_value = Value; + + while (tmp_value >= 10U) + { + bcd_high++; + tmp_value -= 10U; + } + + return ((uint8_t)(bcd_high << 4U) | tmp_value); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value BCD value to be converted + * @retval Converted word + */ +uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint32_t tmp; + + tmp = (((uint32_t)Value & 0xF0U) >> 4) * 10U; + + return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU)); +} + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rtc_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rtc_ex.c new file mode 100644 index 00000000000..ba3c6b18e5b --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rtc_ex.c @@ -0,0 +1,2934 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_rtc_ex.c + * @author GPM Application Team + * @brief Extended RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real Time Clock (RTC) Extended peripheral: + * + RTC Time Stamp functions + * + RTC Tamper functions + * + RTC Wake-up functions + * + Extended Control functions + * + Extended RTC features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (+) Enable the RTC domain access. + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the HAL_RTC_Init() function. + + *** RTC Wakeup configuration *** + ================================ + [..] + (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() + function. You can also configure the RTC Wakeup timer with interrupt mode + using the HAL_RTCEx_SetWakeUpTimer_IT() function. + (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer() + function. + + *** Outputs configuration *** + ============================= + [..] The RTC has 2 outputs pins (RTC_OUT1 & RTC_OUT2). + To configure the outputs, use the HAL_RTC_Init() function. + (+) RTC_OUT1 and RTC_OUT2 which select one of the following two outputs: + (+) CALIB: 512Hz or 1Hz clock output (with an LSE frequency of 32.768kHz). + To enable the CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function. + (+) TAMPALRM: This output is the OR between rtc_tamp_evt and ALARM signals. + ALARM is enabled by configuring the OSEL[1:0] bits in the RTC_CR register + which select the alarm A, alarm B or wakeup outputs. + rtc_tamp_evt is enabled by setting the TAMPOE bit + in the RTC_CR register which selects the tamper event outputs. + + *** Smooth digital Calibration configuration *** + ================================================ + [..] + (+) Configure the RTC Original Digital Calibration Value and the corresponding + calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib() + function. + + *** RTC synchronization *** + ================================================ + [..] + (+) The RTC can be finely adjusted using HAL_RTCEx_SetSynchroShift() function. + Writing to RTC_SHIFTR can shift (either delay or advance) the clock with + a resolution of 1 ck_apre period. + The shift operation consists in adding the SUBFS[14:0] value to the synchronous + prescaler counter SS[15:0]: this delays the clock. + + *** Bypass shadow registers *** + ================================================ + [..] + (+) Enable bypass shadow registers using the HAL_RTCEx_EnableBypassShadow(). + When the Bypass Shadow is enabled the calendar value are taken directly + from the Calendar counter. + Thus eliminating the need to wait for the RSF bit to be set. + This is especially useful after exiting from low-power modes (Stop or Standby), + since the shadow registers are not updated during these modes. + + *** RTC ultra-low-power mode *** + ================================================ + [..] + (+) Configure the RTC ultra-low-power mode using HAL_RTCEx_SetLowPowerCalib() function. + In this case, the calibration mechanism is applied on ck_apre instead of RTCCLK. + The resulting accuracy is the same, but the calibration is performed during a + calibration cycle of about 220 x PREDIV_A x RTCCLK pulses instead of 220 RTCCLK pulses. + + *** RTC subsecond register underflow interruption *** + ================================================ + [..] + (+) Enable the RTC SSRU interruption mode using HAL_RTCEx_SetSSRU_IT() function. + In this case, when the SSR rolls under 0, an SSRU interruption is triggered. + Disable the RTC SSRU interruption mode using HAL_RTCEx_DeactivateSSRU() function. + + *** TimeStamp configuration *** + =============================== + [..] + (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function. + You can also configure the RTC TimeStamp with interrupt mode using the + HAL_RTCEx_SetTimeStamp_IT() function. + (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() + function. + + *** Internal TimeStamp configuration *** + =============================== + [..] + (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function. + User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG. + (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() + function. + + *** Tamper configuration *** + ============================ + [..] + (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge + or Level according to the Tamper filter (if equal to 0 Edge else Level) + value, sampling frequency, NoErase, MaskFlag, precharge or discharge and + Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper + with interrupt mode using HAL_RTCEx_SetTamper_IT() function. + (+) The default configuration of the Tamper erases the backup registers. To avoid + erase, enable the TAMPxPOM field on the TAMP_CR2 register. + (+) With new RTC tamper configuration, you have to call HAL_RTC_Init() in order to + perform TAMP base address offset calculation. + (+) Enable Internal tamper using HAL_RTCEx_SetInternalTamper. IT mode can be chosen using + setting Interrupt field. + + *** Backup Data Registers and Device Secrets configuration *** + =========================================== + [..] + (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() + function. + (+) To read the RTC Backup registers, use the HAL_RTCEx_BKUPRead() + function. + (+) To reset the RTC Backup registers and erase the device secrets, + use HAL_RTCEx_BKUPErase() function. + (+) Enable the lock of the Boot hardware Key using the HAL_RTCEx_LockBootHardwareKey() + function. + The backup registers from TAMP_BKP0R to TAMP_BKP7R cannot be accessed neither in + read nor in write (they are read as 0 and write ignore). + (+) Configure the erase of the Device Secrets using HAL_RTCEx_ConfigEraseDeviceSecrets() + function. + (+) Block the access to the RTC Backup registers and all the device secrets + using HAL_RTCEx_BKUPBlock() function. + + *** Monotonic counter *** + ================================================ + [..] + (+) To increment the Monotonic counter, use the HAL_RTCEx_MonotonicCounterIncrement() + function. + (+) To get the current value of the Monotonic counter, use the HAL_RTCEx_MonotonicCounterGet() + function. + + *** RTC & TAMP privilege protection modes *** + ================================================ + [..] + (+) Set the privilege level of the RTC/TAMP/Backup registers using HAL_RTCEx_PrivilegeModeSet() + function. + +) Get the privilege level of the RTC/TAMP/Backup registers using HAL_RTCEx_PrivilegeModeGet() + function. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup RTCEx + * @brief RTC Extended HAL module driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define TAMP_ALL RTC_TAMPER_ALL + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup RTCEx_Exported_Functions + * @{ + */ + + +/** @addtogroup RTCEx_Exported_Functions_Group1 + * @brief RTC TimeStamp and Tamper functions + * +@verbatim + =============================================================================== + ##### RTC TimeStamp and Tamper functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure TimeStamp feature + +@endverbatim + * @{ + */ + +#ifdef RTC_CR_TSE +/** + * @brief Set TimeStamp. + * @note This API must be called before enabling the TimeStamp feature. + * @param hrtc RTC handle + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * falling edge of the related pin. + * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. + * The RTC TimeStamp Pin is per default PC13, but for reasons of + * compatibility, this parameter is required. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +{ + /* Check the parameters */ +#if defined(RTC_CR_TSEDGE) + assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); +#endif /* RTC_CR_TSEDGE */ + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + UNUSED(RTC_TimeStampPin); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Get the RTC_CR register and clear the bits to be configured */ +#if defined(RTC_CR_TSEDGE) + CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE)); +#else + CLEAR_BIT(RTC->CR, RTC_CR_TSE); +#endif /* RTC_CR_TSEDGE */ + + /* Configure the Time Stamp TSEDGE and Enable bits */ + SET_BIT(RTC->CR, (uint32_t)TimeStampEdge | RTC_CR_TSE); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Set TimeStamp with Interrupt. + * @note This API must be called before enabling the TimeStamp feature. + * @note The application must ensure that the EXTI RTC interrupt line is configured and enabled. + * @param hrtc RTC handle + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * falling edge of the related pin. + * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. + * The RTC TimeStamp Pin is per default PC13, but for reasons of + * compatibility, this parameter is required. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +{ + /* Check the parameters */ +#if defined(RTC_CR_TSEDGE) + assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); +#endif /* RTC_CR_TSEDGE */ + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + UNUSED(RTC_TimeStampPin); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Get the RTC_CR register and clear the bits to be configured */ +#if defined(RTC_CR_TSEDGE) + CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE)); +#else + CLEAR_BIT(RTC->CR, (RTC_CR_TSE | RTC_CR_TSIE)); +#endif /* RTC_CR_TSEDGE */ + + /* Configure the Time Stamp TSEDGE before Enable bit to avoid unwanted TSF setting. */ + SET_BIT(RTC->CR, (uint32_t)TimeStampEdge); + + /* Enable timestamp and IT */ + SET_BIT(RTC->CR, RTC_CR_TSE | RTC_CR_TSIE); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate TimeStamp. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* In case of interrupt mode is used, the interrupt source must disabled */ +#if defined(RTC_CR_TSEDGE) + CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE)); +#else + CLEAR_BIT(RTC->CR, (RTC_CR_TSE | RTC_CR_TSIE)); +#endif /* RTC_CR_TSEDGE */ + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} +#endif /* RTC_CR_TSE */ + +/** + * @brief Set Internal TimeStamp. + * @note This API must be called before enabling the internal TimeStamp feature. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Configure the internal Time Stamp Enable bits */ + SET_BIT(RTC->CR, RTC_CR_ITSE); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate Internal TimeStamp. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Configure the internal Time Stamp Enable bits */ + CLEAR_BIT(RTC->CR, RTC_CR_ITSE); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Get the RTC TimeStamp value. + * @param hrtc RTC handle + * @param sTimeStamp Pointer to Time structure + * @param sTimeStampDate Pointer to Date structure + * @param Format specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, + RTC_DateTypeDef *sTimeStampDate, uint32_t Format) +{ + uint32_t tmptime; + uint32_t tmpdate; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = READ_BIT(RTC->TSTR, RTC_TR_RESERVED_MASK); + tmpdate = READ_BIT(RTC->TSDR, RTC_DR_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TSTR_HT | RTC_TSTR_HU)) >> RTC_TSTR_HU_Pos); + sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> RTC_TSTR_MNU_Pos); + sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TSTR_ST | RTC_TSTR_SU)) >> RTC_TSTR_SU_Pos); + sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TSTR_PM)) >> RTC_TSTR_PM_Pos); + sTimeStamp->SubSeconds = READ_BIT(RTC->TSSSR, RTC_TSSSR_SS); + + /* Fill the Date structure fields with the read parameters */ + sTimeStampDate->Year = 0U; + sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> RTC_TSDR_MU_Pos); + sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU)); + sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU)) >> RTC_TSDR_WDU_Pos); + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + { + /* Convert the TimeStamp structure parameters to Binary format */ + sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); + sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); + sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); + + /* Convert the DateTimeStamp structure parameters to Binary format */ + sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); + sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); + sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); + } + + /* Check if TIMESTAMP flag is set */ + if (READ_BIT(RTC->SR, RTC_SR_TSF) != 0U) + { + /* Clear the TIMESTAMP Flags */ + WRITE_REG(RTC->SCR, (RTC_SCR_CITSF | RTC_SCR_CTSF)); + + /* Check if TIMESTAMP OverRun flag is set */ + if (READ_BIT(RTC->SR, RTC_SR_TSOVF) != 0U) + { + /* Clear the TIMESTAMP OverRun Flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF); + + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Handle TimeStamp interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get the pending status of the TimeStamp Interrupt */ + if (READ_BIT(RTC->MISR, RTC_MISR_TSMF) != 0U) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call TimeStampEvent registered Callback */ + hrtc->TimeStampEventCallback(hrtc); +#else + HAL_RTCEx_TimeStampEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when + TSF bit is reset.*/ + WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSF); + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief TimeStamp callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file + */ +} + +/** + * @brief Handle TimeStamp polling request. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_TSF) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_TSF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group2 + * @brief RTC Wake-up functions + * +@verbatim + =============================================================================== + ##### RTC Wake-up functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Wake-up feature + +@endverbatim + * @{ + */ + +/** + * @brief Set wake up timer. + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Clear WUTE in RTC_CR to disable the wakeup timer */ + CLEAR_BIT(RTC->CR, RTC_CR_WUTE); + + /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload + counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in + calendar initialization mode. */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + /* Configure the clock source */ + MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock); + + /* Configure the Wakeup Timer counter */ + WRITE_REG(RTC->WUTR, (uint32_t)WakeUpCounter); + + /* Enable the Wakeup Timer */ + SET_BIT(RTC->CR, RTC_CR_WUTE); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Set wake up timer with interrupt. + * @note The application must ensure that the EXTI RTC interrupt line is configured and enabled. + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock + * @param WakeUpAutoClr Wake up auto clear value (look at WUTOCLR in reference manual) + * - No effect if WakeUpAutoClr is set to zero + * - This feature is meaningful in case of Low power mode to avoid any RTC software execution + * after Wake Up. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, + uint32_t WakeUpAutoClr) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); + /* (0x0000<=WUTOCLR<=WUT) */ + assert_param(WakeUpAutoClr <= WakeUpCounter); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Clear WUTE in RTC_CR to disable the wakeup timer */ + CLEAR_BIT(RTC->CR, RTC_CR_WUTE); + + /* Clear flag Wake-Up */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); + + /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload + counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in + calendar initialization mode. */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + tickstart = HAL_GetTick(); + while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + /* Configure the Wakeup Timer counter and auto clear value */ + WRITE_REG(RTC->WUTR, (uint32_t)(WakeUpCounter | (WakeUpAutoClr << RTC_WUTR_WUTOCLR_Pos))); + + /* Configure the clock source */ + MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock); + + /* Configure the Interrupt in the RTC_CR register and Enable the Wakeup Timer*/ + SET_BIT(RTC->CR, (RTC_CR_WUTIE | RTC_CR_WUTE)); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate wake up timer counter. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the Wakeup Timer */ + /* In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, (RTC_CR_WUTE | RTC_CR_WUTIE)); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Get wake up timer counter. + * @param hrtc RTC handle + * @retval Counter value + */ +uint32_t HAL_RTCEx_GetWakeUpTimer(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Get the counter value */ + return (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT)); +} + +/** + * @brief Handle Wake Up Timer interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get the pending status of the Wake-Up Timer Interrupt */ + if (READ_BIT(RTC->MISR, RTC_MISR_WUTMF) != 0U) + { + /* Immediately clear flags */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call wake up timer registered Callback */ + hrtc->WakeUpTimerEventCallback(hrtc); +#else + HAL_RTCEx_WakeUpTimerEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief Wake Up Timer callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file + */ +} + +/** + * @brief Handle Wake Up Timer Polling. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + /* Clear the WAKEUPTIMER Flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group3 + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Write a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register + (+) Set the Coarse calibration parameters. + (+) Deactivate the Coarse calibration parameters + (+) Set the Smooth calibration parameters. + (+) Set Low Power calibration parameter. + (+) Configure the Synchronization Shift Control Settings. + (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Enable the RTC reference clock detection. + (+) Disable the RTC reference clock detection. + (+) Enable the Bypass Shadow feature. + (+) Disable the Bypass Shadow feature. + +@endverbatim + * @{ + */ + +/** + * @brief Set the Smooth calibration parameters. + * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses + * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field + * SmoothCalibMinusPulsesValue must be equal to 0. + * @param hrtc RTC handle + * @param SmoothCalibPeriod Select the Smooth Calibration Period. + * This parameter can be one of the following values : + * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. + * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. + * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. + * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. + * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. + * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, + uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + tickstart = HAL_GetTick(); + + /* check if a calibration is pending */ + while (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) + { + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Smooth calibration settings */ + MODIFY_REG(RTC->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM), + (uint32_t)(SmoothCalibPeriod | SmoothCalibPlusPulses | SmoothCalibMinusPulsesValue)); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Select the low power Calibration mode. + * @param hrtc: RTC handle + * @param LowPowerCalib: Low power Calibration mode. + * This parameter can be one of the following values : + * @arg RTC_LPCAL_SET: Low power mode. + * @arg RTC_LPCAL_RESET: High consumption mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib) +{ + /* Check the parameters */ + assert_param(IS_RTC_LOW_POWER_CALIB(LowPowerCalib)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Smooth calibration settings */ + MODIFY_REG(RTC->CALR, RTC_CALR_LPCAL, LowPowerCalib); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Configure the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @param hrtc RTC handle + * @param ShiftAdd1S Select to add or not 1 second to the time calendar. + * This parameter can be one of the following values: + * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. + * @arg RTC_SHIFTADD1S_RESET: No effect. + * @param ShiftSubFS Select the number of Second Fractions to substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + tickstart = HAL_GetTick(); + + /* Wait until the shift is completed */ + while (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + +#if defined(RTC_CR_REFCKON) + /* Check if the reference clock detection is disabled */ + if (READ_BIT(RTC->CR, RTC_CR_REFCKON) == 0U) + { +#endif /* RTC_CR_REFCKON */ + /* Configure the Shift settings */ + MODIFY_REG(RTC->SHIFTR, RTC_SHIFTR_SUBFS, (uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S)); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } +#if defined(RTC_CR_REFCKON) + } + else + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } +#endif /* RTC_CR_REFCKON */ + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +#if defined(RTC_CR_COSEL) +/** + * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc RTC handle + * @param CalibOutput Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. + * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Configure the RTC_CR register */ + MODIFY_REG(RTC->CR, RTC_CR_COSEL, CalibOutput); + + /* Enable calibration output */ + SET_BIT(RTC->CR, RTC_CR_COE); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable calibration output */ + CLEAR_BIT(RTC->CR, RTC_CR_COE); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} +#endif /* RTC_CR_COSEL */ + +#if defined(RTC_CR_REFCKON) +/** + * @brief Enable the RTC reference clock detection. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Enable clockref detection */ + SET_BIT(RTC->CR, RTC_CR_REFCKON); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Disable the RTC reference clock detection. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Disable clockref detection */ + CLEAR_BIT(RTC->CR, RTC_CR_REFCKON); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} +#endif /* RTC_CR_REFCKON */ + +/** + * @brief Enable the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Set the BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Disable the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Reset the BYPSHAD bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Increment Monotonic counter. + * @param hrtc RTC handle + * @param Instance Monotonic counter Instance + * This parameter can be one of the following values : + * @arg RTC_MONOTONIC_COUNTER_1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(const RTC_HandleTypeDef *hrtc, uint32_t Instance) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + UNUSED(Instance); + + /* This register is read-only only and is incremented by one when a write access is done to this + register. This register cannot roll-over and is frozen when reaching the maximum value. */ + CLEAR_REG(TAMP->COUNT1R); + + return HAL_OK; +} + +/** + * @brief Monotonic counter. + * @param hrtc RTC handle + * @param Instance Monotonic counter Instance + * This parameter can be one of the following values : + * @arg RTC_MONOTONIC_COUNTER_1 + * @param pValue Pointer to the counter monotonic counter value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(const RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *pValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + UNUSED(Instance); + + /* This register is read-only only and is incremented by one when a write access is done to this + register. This register cannot roll-over and is frozen when reaching the maximum value. */ + *pValue = READ_REG(TAMP->COUNT1R); + + return HAL_OK; +} + +/** + * @brief Set SSR Underflow detection with Interrupt. + * @note The application must ensure that the EXTI RTC interrupt line is configured and enabled. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Enable IT SSRU */ + __HAL_RTC_SSRU_ENABLE_IT(hrtc, RTC_IT_SSRU); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate SSR Underflow. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_SSRU_DISABLE_IT(hrtc, RTC_IT_SSRU); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Handle SSR underflow interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get the pending status of the SSR Underflow Interrupt */ + if (READ_BIT(RTC->MISR, RTC_MISR_SSRUMF) != 0U) + { + /* Immediately clear SSR underflow flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CSSRUF); + + /* SSRU callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call SSRUEvent registered Callback */ + hrtc->SSRUEventCallback(hrtc); +#else + HAL_RTCEx_SSRUEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief SSR underflow callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_SSRUEventCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group4 + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) RTC Alarm B callback + (+) RTC Poll for Alarm B request + +@endverbatim + * @{ + */ + +/** + * @brief Alarm B callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file + */ +} + +/** + * @brief Handle Alarm B Polling request. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_ALRBF) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_ALRBF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + /* Clear the Alarm Flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group5 + * @brief Extended RTC Tamper functions + * +@verbatim + ============================================================================== + ##### Tamper functions ##### + ============================================================================== + [..] + (+) Before calling any tamper or internal tamper function, you have to call first + HAL_RTC_Init() function. + (+) In that one you can select to output tamper event on RTC pin. + [..] + (+) Enable the Tamper and configure the Tamper filter count, trigger Edge + or Level according to the Tamper filter (if equal to 0 Edge else Level) + value, sampling frequency, NoErase, MaskFlag, precharge or discharge and + Pull-UP, timestamp using the HAL_RTCEx_SetTamper() function. + You can configure Tamper with interrupt mode using HAL_RTCEx_SetTamper_IT() function. + (+) The default configuration of the Tamper erases the backup registers. To avoid + erase, enable the NoErase field on the TAMP_TAMPCR register. + [..] + (+) Enable Internal Tamper and configure it with interrupt, timestamp using + the HAL_RTCEx_SetInternalTamper() function. + +@endverbatim + * @{ + */ + + +/** + * @brief Set Tamper + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(const RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper) +{ + uint32_t tmpreg; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); +#if (RTC_TAMP_NB > 2U) + /* Mask flag only supported by TAMPER 1, 2 and 3 */ + assert_param(!((sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) && (sTamper->Tamper > RTC_TAMPER_3))); +#else + assert_param(!((sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) && (sTamper->Tamper > RTC_TAMPER_2))); +#endif /* (RTC_TAMP_NB > 2U) */ + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + /* Trigger and Filter have exclusive configurations */ + assert_param(((sTamper->Filter != RTC_TAMPERFILTER_DISABLE) && + ((sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL) || + (sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL))) || + ((sTamper->Filter == RTC_TAMPERFILTER_DISABLE) && + ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) || + (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)))); + + /* Configuration register 2 */ + tmpreg = READ_REG(TAMP->CR2); + tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | + (sTamper->Tamper << TAMP_CR2_TAMP1POM_Pos)); + + if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); + } + + if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos); + } + + if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1POM_Pos); + } + WRITE_REG(TAMP->CR2, tmpreg); + + /* Filter control register */ + WRITE_REG(TAMP->FLTCR, sTamper->Filter | sTamper->SamplingFrequency | sTamper->PrechargeDuration | + sTamper->TamperPullUp); + + /* Timestamp on tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection) + { + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection); + } + + /* Control register 1 */ + SET_BIT(TAMP->CR1, sTamper->Tamper); + + return HAL_OK; +} + + +/** + * @brief Set Tamper in IT mode + * @note The application must ensure that the EXTI TAMP interrupt line is configured and enabled. + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(const RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper) +{ + uint32_t tmpreg; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + /* The interrupt must not be enabled when TAMPxMSK is set. */ + assert_param(sTamper->MaskFlag == RTC_TAMPERMASK_FLAG_DISABLE); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + /* Trigger and Filter have exclusive configurations */ + assert_param(((sTamper->Filter != RTC_TAMPERFILTER_DISABLE) && + ((sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL) || + (sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL))) || + ((sTamper->Filter == RTC_TAMPERFILTER_DISABLE) && + ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) || + (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)))); + + /* Configuration register 2 */ + tmpreg = READ_REG(TAMP->CR2); + tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | + (sTamper->Tamper << TAMP_CR2_TAMP1POM_Pos)); + + if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); + } + + if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1POM_Pos); + } + WRITE_REG(TAMP->CR2, tmpreg); + + /* Filter control register */ + WRITE_REG(TAMP->FLTCR, sTamper->Filter | sTamper->SamplingFrequency | sTamper->PrechargeDuration | + sTamper->TamperPullUp); + + /* Timestamp on tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection) + { + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection); + } + + /* Interrupt enable register */ + SET_BIT(TAMP->IER, sTamper->Tamper); + + /* Control register 1 */ + SET_BIT(TAMP->CR1, sTamper->Tamper); + + return HAL_OK; +} + +/** + * @brief Deactivate Tamper. + * @param hrtc RTC handle + * @param Tamper Selected tamper pin. + * This parameter can be a combination of the following values: + * @arg RTC_TAMPER_1 + * @arg RTC_TAMPER_2 + * @arg RTC_TAMPER_3 + * @arg RTC_TAMPER_4 + * @arg RTC_TAMPER_5 + * @arg RTC_TAMPER_6 + * @arg RTC_TAMPER_7 + * @arg RTC_TAMPER_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(const RTC_HandleTypeDef *hrtc, uint32_t Tamper) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + assert_param(IS_RTC_TAMPER(Tamper)); + + /* Disable the selected Tamper pin */ + CLEAR_BIT(TAMP->CR1, Tamper); + + /* Clear tamper interrupt and event flags (WO register) */ + WRITE_REG(TAMP->SCR, Tamper); + + /* Clear tamper mask/noerase/trigger configuration */ + CLEAR_BIT(TAMP->CR2, (Tamper << TAMP_CR2_TAMP1TRG_Pos) | (Tamper << TAMP_CR2_TAMP1MSK_Pos) | \ + (Tamper << TAMP_CR2_TAMP1POM_Pos)); + + /* Clear tamper interrupt mode configuration */ + CLEAR_BIT(TAMP->IER, Tamper); + + return HAL_OK; +} + +/** + * @brief Set all active Tampers at the same time. + * @note For interrupt mode, the application must ensure that the EXTI RTC interrupt line is configured and enabled. + * @param hrtc RTC handle + * @param sAllTamper Pointer to active Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, const RTC_ActiveTampersTypeDef *sAllTamper) +{ + uint32_t tmp_ier; + uint32_t tmp_cr1; + uint32_t tmp_cr2; + uint32_t tmp_atcr1; + uint32_t tmp_atcr2; + uint32_t tmp_cr; + uint32_t i; + uint32_t tickstart; + +#ifdef USE_FULL_ASSERT + for (i = 0; i < RTC_TAMP_NB; i++) + { + assert_param(IS_RTC_TAMPER_ERASE_MODE(sAllTamper->TampInput[i].NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sAllTamper->TampInput[i].MaskFlag)); + /* Mask flag only supported by TAMPER 1, 2 and 3 */ + assert_param(!((sAllTamper->TampInput[i].MaskFlag == RTC_TAMPERMASK_FLAG_ENABLE) && + (i >= RTC_TAMPER_MASKABLE_NB))); + } + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sAllTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_ATAMPER_FILTER(sAllTamper->ActiveFilter)); + assert_param(IS_RTC_ATAMPER_OUTPUT_CHANGE_PERIOD(sAllTamper->ActiveOutputChangePeriod)); + assert_param(IS_RTC_ATAMPER_ASYNCPRES_RTCCLK(sAllTamper->ActiveAsyncPrescaler)); +#endif /* USE_FULL_ASSERT */ + + /* Active Tampers must not be already enabled */ + if (READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) != 0U) + { + /* Disable all actives tampers with HAL_RTCEx_DeactivateActiveTampers. + No need to check return value because it returns always HAL_OK */ + (void) HAL_RTCEx_DeactivateActiveTampers(hrtc); + } + + /* Set TimeStamp on tamper detection */ + tmp_cr = READ_REG(RTC->CR); + if ((tmp_cr & RTC_CR_TAMPTS) != (sAllTamper->TimeStampOnTamperDetection)) + { + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sAllTamper->TimeStampOnTamperDetection); + } + + tmp_cr1 = READ_REG(TAMP->CR1); + tmp_cr2 = READ_REG(TAMP->CR2); + tmp_atcr2 = 0U; + tmp_ier = READ_REG(TAMP->IER); + + /* Set common parameters */ + tmp_atcr1 = (sAllTamper->ActiveFilter | (sAllTamper->ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos) | + sAllTamper->ActiveAsyncPrescaler); + + /* Set specific parameters for each active tamper inputs if enable */ + for (i = 0; i < RTC_TAMP_NB; i++) + { + if (sAllTamper->TampInput[i].Enable != RTC_ATAMP_DISABLE) + { + tmp_cr1 |= (TAMP_CR1_TAMP1E << i); + tmp_atcr1 |= (TAMP_ATCR1_TAMP1AM << i); + + if (sAllTamper->TampInput[i].Interrupt != RTC_ATAMP_INTERRUPT_DISABLE) + { + /* Interrupt enable register */ + tmp_ier |= (TAMP_IER_TAMP1IE << i); + } + + if (sAllTamper->TampInput[i].MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + tmp_cr2 |= (TAMP_CR2_TAMP1MSK << i); + } + + if (sAllTamper->TampInput[i].NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + tmp_cr2 |= (TAMP_CR2_TAMP1POM << i); + } + + /* Configure ATOSELx[] in case of output sharing */ + tmp_atcr2 |= sAllTamper->TampInput[i].Output << ((3U * i) + TAMP_ATCR2_ATOSEL1_Pos); + + if (i != sAllTamper->TampInput[i].Output) + { + tmp_atcr1 |= TAMP_ATCR1_ATOSHARE; + } + } + } + + WRITE_REG(TAMP->IER, tmp_ier); + WRITE_REG(TAMP->ATCR1, tmp_atcr1); + WRITE_REG(TAMP->ATCR2, tmp_atcr2); + WRITE_REG(TAMP->CR2, tmp_cr2); + WRITE_REG(TAMP->CR1, tmp_cr1); + + /* Write seed */ + for (i = 0; i < RTC_ATAMP_SEED_NB_UINT32; i++) + { + WRITE_REG(TAMP->ATSEEDR, sAllTamper->Seed[i]); + } + + /* Wait till RTC SEEDF flag is cleared and if Time out is reached exit */ + tickstart = HAL_GetTick(); + while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + + return HAL_OK; +} + +/** + * @brief Write a new seed. Active tamper must be enabled. + * @param hrtc RTC handle + * @param pSeed Pointer to active tamper seed values. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, const uint32_t *pSeed) +{ + uint32_t i; + uint32_t tickstart; + + /* Active Tampers must be enabled */ + if (READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == 0U) + { + return HAL_ERROR; + } + + for (i = 0; i < RTC_ATAMP_SEED_NB_UINT32; i++) + { + WRITE_REG(TAMP->ATSEEDR, pSeed[i]); + } + + /* Wait till RTC SEEDF flag is cleared and if Time out is reached exit */ + tickstart = HAL_GetTick(); + while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + + return HAL_OK; +} + +#if defined(TAMP_CFGR_BHKLOCK) +/** + * @brief Lock the Boot hardware Key + * @param hrtc RTC handle + * @note The backup registers from TAMP_BKP0R to TAMP_BKP7R cannot be accessed neither in + * read nor in write (they are read as 0 and write ignore). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_LockBootHardwareKey(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + WRITE_REG(TAMP->CFGR, TAMP_CFGR_BHKLOCK); + + return HAL_OK; +} +#endif /* TAMP_CFGR_BHKLOCK */ + +/** + * @brief Deactivate all Active Tampers at the same time. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Get Active tampers */ + uint32_t atamp_mask = READ_BIT(TAMP->ATCR1, TAMP_ALL); + + /* Disable all actives tampers but not passives tampers */ + CLEAR_BIT(TAMP->CR1, atamp_mask); + + /* Clear tamper interrupt and event flags (WO register) of all actives tampers but not passives tampers */ + WRITE_REG(TAMP->SCR, atamp_mask); + + /* Disable no erase and mask */ + CLEAR_BIT(TAMP->CR2, (atamp_mask | ((atamp_mask & (TAMP_ATCR1_TAMP1AM | TAMP_ATCR1_TAMP2AM | TAMP_ATCR1_TAMP3AM)) << + TAMP_CR2_TAMP1MSK_Pos))); + + /* Clear all active tampers interrupt mode configuration but not passives tampers */ + CLEAR_BIT(TAMP->IER, atamp_mask); + + /* Set reset value for active tamper control register 1 */ + WRITE_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL_0 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_2); + + /* Set reset value for active tamper control register 2 */ + CLEAR_REG(TAMP->ATCR2); + + return HAL_OK; +} + +/** + * @brief Tamper event polling. + * @param hrtc RTC handle + * @param Tamper Selected tamper pin. + * This parameter can be a combination of the following values: + * @arg RTC_TAMPER_1 + * @arg RTC_TAMPER_2 + * @arg RTC_TAMPER_3 + * @arg RTC_TAMPER_4 + * @arg RTC_TAMPER_5 + * @arg RTC_TAMPER_6 + * @arg RTC_TAMPER_7 + * @arg RTC_TAMPER_8 + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(const RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + assert_param(IS_RTC_TAMPER(Tamper)); + + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while (READ_BIT(TAMP->SR, Tamper) != Tamper) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->SR, Tamper) != Tamper) + { + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + /* Clear the Tamper Flag */ + WRITE_REG(TAMP->SCR, Tamper); + + return HAL_OK; +} + + +/** + * @brief Set Internal Tamper + * @param hrtc RTC handle + * @param sIntTamper Pointer to Internal Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(const RTC_HandleTypeDef *hrtc, + const RTC_InternalTamperTypeDef *sIntTamper) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sIntTamper->NoErase)); + + /* Timestamp enable on internal tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection) + { + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection); + } + + /* No Erase Backup register enable for Internal Tamper */ + if (sIntTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + SET_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP1E_Pos - TAMP_CR3_ITAMP1POM_Pos))); + } + else + { + CLEAR_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP1E_Pos - TAMP_CR3_ITAMP1POM_Pos))); + } + + /* Enable Internal Tamper */ + SET_BIT(TAMP->CR1, sIntTamper->IntTamper); + + return HAL_OK; +} + + +/** + * @brief Set Internal Tamper in interrupt mode + * @note The application must ensure that the EXTI RTC tamper interrupt line is configured and enabled. + * @param hrtc RTC handle + * @param sIntTamper Pointer to Internal Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(const RTC_HandleTypeDef *hrtc, + const RTC_InternalTamperTypeDef *sIntTamper) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sIntTamper->NoErase)); + + /* Timestamp enable on internal tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection) + { + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection); + } + + /* Interrupt enable register */ + SET_BIT(TAMP->IER, sIntTamper->IntTamper); + + /* No Erase Backup register enable for Internal Tamper */ + if (sIntTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + SET_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP1E_Pos - TAMP_CR3_ITAMP1POM_Pos))); + } + else + { + CLEAR_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP1E_Pos - TAMP_CR3_ITAMP1POM_Pos))); + } + + /* Enable Internal Tamper */ + SET_BIT(TAMP->CR1, sIntTamper->IntTamper); + + return HAL_OK; +} + +/** + * @brief Deactivate Internal Tamper. + * @param hrtc RTC handle + * @param IntTamper Selected internal tamper event. + * This parameter can be any combination of existing internal tampers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(const RTC_HandleTypeDef *hrtc, uint32_t IntTamper) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper)); + + /* Disable the selected Tamper pin */ + CLEAR_BIT(TAMP->CR1, IntTamper); + + /* Clear internal tamper interrupt mode configuration */ + CLEAR_BIT(TAMP->IER, IntTamper); + + /* Clear internal tamper interrupt */ + WRITE_REG(TAMP->SCR, IntTamper); + + return HAL_OK; +} + +/** + * @brief Internal Tamper event polling. + * @param hrtc RTC handle + * @param IntTamper selected tamper. + * This parameter can be any combination of existing internal tampers. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(const RTC_HandleTypeDef *hrtc, uint32_t IntTamper, + uint32_t Timeout) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper)); + + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while (READ_BIT(TAMP->SR, IntTamper) != IntTamper) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->SR, IntTamper) != IntTamper) + { + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + /* Clear the Tamper Flag */ + WRITE_REG(TAMP->SCR, IntTamper); + + return HAL_OK; +} + +/** + * @brief Handle Tamper interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get the pending status of the Tampers Interrupt */ + uint32_t tmp = READ_REG(TAMP->MISR); + + /* Check Tamper1 status */ + if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 1 Event registered Callback */ + hrtc->Tamper1EventCallback(hrtc); +#else + /* Tamper1 callback */ + HAL_RTCEx_Tamper1EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Tamper2 status */ + if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 2 Event registered Callback */ + hrtc->Tamper2EventCallback(hrtc); +#else + /* Tamper2 callback */ + HAL_RTCEx_Tamper2EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + +#if (RTC_TAMP_NB > 2U) + + /* Check Tamper3 status */ + if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 3 Event registered Callback */ + hrtc->Tamper3EventCallback(hrtc); +#else + /* Tamper3 callback */ + HAL_RTCEx_Tamper3EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Tamper4 status */ + if ((tmp & RTC_TAMPER_4) == RTC_TAMPER_4) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 4 Event registered Callback */ + hrtc->Tamper4EventCallback(hrtc); +#else + /* Tamper4 callback */ + HAL_RTCEx_Tamper4EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Tamper5 status */ + if ((tmp & RTC_TAMPER_5) == RTC_TAMPER_5) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 5 Event registered Callback */ + hrtc->Tamper5EventCallback(hrtc); +#else + /* Tamper5 callback */ + HAL_RTCEx_Tamper5EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Tamper6 status */ + if ((tmp & RTC_TAMPER_6) == RTC_TAMPER_6) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 6 Event registered Callback */ + hrtc->Tamper6EventCallback(hrtc); +#else + /* Tamper6 callback */ + HAL_RTCEx_Tamper6EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + +#endif /* (RTC_TAMP_NB > 2U) */ +#if (RTC_TAMP_NB > 6U) + + /* Check Tamper7 status */ + if ((tmp & RTC_TAMPER_7) == RTC_TAMPER_7) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 7 Event registered Callback */ + hrtc->Tamper7EventCallback(hrtc); +#else + /* Tamper7 callback */ + HAL_RTCEx_Tamper7EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Tamper8 status */ + if ((tmp & RTC_TAMPER_8) == RTC_TAMPER_8) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 8 Event registered Callback */ + hrtc->Tamper8EventCallback(hrtc); +#else + /* Tamper8 callback */ + HAL_RTCEx_Tamper8EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + +#endif /* (RTC_TAMP_NB > 6U) */ + + /* Check Internal Tamper1 status */ + if ((tmp & RTC_INT_TAMPER_1) == RTC_INT_TAMPER_1) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 1 Event registered Callback */ + hrtc->InternalTamper1EventCallback(hrtc); +#else + /* Internal Tamper1 callback */ + HAL_RTCEx_InternalTamper1EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper2 status */ + if ((tmp & RTC_INT_TAMPER_2) == RTC_INT_TAMPER_2) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 2 Event registered Callback */ + hrtc->InternalTamper2EventCallback(hrtc); +#else + /* Internal Tamper2 callback */ + HAL_RTCEx_InternalTamper2EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper3 status */ + if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 3 Event registered Callback */ + hrtc->InternalTamper3EventCallback(hrtc); +#else + /* Internal Tamper3 callback */ + HAL_RTCEx_InternalTamper3EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper4 status */ + if ((tmp & RTC_INT_TAMPER_4) == RTC_INT_TAMPER_4) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 4 Event registered Callback */ + hrtc->InternalTamper4EventCallback(hrtc); +#else + /* Internal Tamper4 callback */ + HAL_RTCEx_InternalTamper4EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper5 status */ + if ((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 5 Event registered Callback */ + hrtc->InternalTamper5EventCallback(hrtc); +#else + /* Internal Tamper5 callback */ + HAL_RTCEx_InternalTamper5EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper6 status */ + if ((tmp & RTC_INT_TAMPER_6) == RTC_INT_TAMPER_6) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 6 Event registered Callback */ + hrtc->InternalTamper6EventCallback(hrtc); +#else + /* Internal Tamper6 callback */ + HAL_RTCEx_InternalTamper6EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper7 status */ + if ((tmp & RTC_INT_TAMPER_7) == RTC_INT_TAMPER_7) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 7 Event registered Callback */ + hrtc->InternalTamper7EventCallback(hrtc); +#else + /* Internal Tamper7 callback */ + HAL_RTCEx_InternalTamper7EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper8 status */ + if ((tmp & RTC_INT_TAMPER_8) == RTC_INT_TAMPER_8) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 8 Event registered Callback */ + hrtc->InternalTamper8EventCallback(hrtc); +#else + /* Internal Tamper8 callback */ + HAL_RTCEx_InternalTamper8EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper9 status */ + if ((tmp & RTC_INT_TAMPER_9) == RTC_INT_TAMPER_9) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 9 Event registered Callback */ + hrtc->InternalTamper9EventCallback(hrtc); +#else + /* Internal Tamper9 callback */ + HAL_RTCEx_InternalTamper9EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper11 status */ + if ((tmp & RTC_INT_TAMPER_11) == RTC_INT_TAMPER_11) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 11 Event registered Callback */ + hrtc->InternalTamper11EventCallback(hrtc); +#else + /* Internal Tamper11 callback */ + HAL_RTCEx_InternalTamper11EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper15 status */ + if ((tmp & RTC_INT_TAMPER_15) == RTC_INT_TAMPER_15) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 15 Event registered Callback */ + hrtc->InternalTamper15EventCallback(hrtc); +#else + /* Internal Tamper15 callback */ + HAL_RTCEx_InternalTamper15EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Clear flags after treatment to allow the potential tamper feature */ + WRITE_REG(TAMP->SCR, tmp); +} + +/** + * @brief Tamper 1 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 2 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 3 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 4 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper4EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper4EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 5 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper5EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper5EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 6 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper6EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper6EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 7 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper7EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper7EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 8 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper8EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper8EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 1 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper1EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 2 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper2EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 3 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper3EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 4 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper4EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 5 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper5EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 6 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper6EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 7 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper7EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper7EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 8 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper8EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 9 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper9EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper9EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 11 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper11EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper11EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 15 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper15EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper15EventCallback could be implemented in the user file + */ +} +/** + * @} + */ + + +/** @addtogroup RTCEx_Exported_Functions_Group6 + * @brief Extended RTC Backup register functions + * +@verbatim + =============================================================================== + ##### Extended RTC Backup register functions ##### + =============================================================================== + [..] + (+) Before calling any tamper or internal tamper function, you have to call first + HAL_RTC_Init() function. + (+) In that one you can select to output tamper event on RTC pin. + [..] + This subsection provides functions allowing to + (+) Write a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register +@endverbatim + * @{ + */ + + +/** + * @brief Write a data in a specified RTC Backup data register. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. + * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB + * @param Data Data to be written in the specified Backup data register. + * @retval None + */ +void HAL_RTCEx_BKUPWrite(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +{ + uint32_t tmp; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + /* Determine address of the specified Backup register */ + tmp = (uint32_t)(&(TAMP->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Write data in the specified register Backup register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. + * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB + * @retval Read value + */ +uint32_t HAL_RTCEx_BKUPRead(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +{ + uint32_t tmp; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + /* Determine address of the specified Backup register */ + tmp = (uint32_t)(&(TAMP->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Read the data from the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @brief Reset the RTC Backup data Registers and the device secrets. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_BKUPErase(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + SET_BIT(TAMP->CR2, TAMP_CR2_BKERASE); +} + +/** + * @brief Block the access to the RTC Backup data Register and all the device secrets. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_BKUPBlock(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + WRITE_REG(TAMP->CR2, TAMP_CR2_BKBLOCK); +} + +/** + * @brief Disable the Block to the access to the RTC Backup data Register and the device secrets. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_BKUPUnblock(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + CLEAR_BIT(TAMP->CR2, TAMP_CR2_BKBLOCK); +} + +#ifdef TAMP_RPCFGR_RPCFG0 +/** + * @brief Enable and Disable the erase of the configurable Device Secrets + * @note This API must be called before enabling the Tamper. + * @param hrtc RTC handle + * @param DeviceSecretConf Specifies the configuration of the Device Secrets + * This parameter can be a combination of the following values: + * @arg TAMP_DEVICESECRETS_ERASE_NONE + * @arg TAMP_DEVICESECRETS_ERASE_BKPSRAM + * + * @retval None + */ +void HAL_RTCEx_ConfigEraseDeviceSecrets(const RTC_HandleTypeDef *hrtc, uint32_t DeviceSecretConf) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + MODIFY_REG(TAMP->RPCFGR, TAMP_RPCFGR_RPCFG0, DeviceSecretConf); +} +#endif /* TAMP_RPCFGR_RPCFG0 */ + +/** + * @} + */ + +#if defined(TAMP_PRIVCFGR_TAMPPRIV) +/** @addtogroup RTCEx_Exported_Functions_Group8 + * @brief Extended RTC privilege functions + * +@verbatim + =============================================================================== + ##### Extended RTC privilege functions ##### + =============================================================================== + [..] + (+) Before calling privilege function, you have to call first + HAL_RTC_Init() function. +@endverbatim + * @{ + */ + +/** + * @brief Set the privilege level of the RTC/TAMP/Backup registers. + * To get the current privilege level call HAL_RTCEx_PrivilegeModeGet. + * @param hrtc RTC handle + * @param privilegeState Privilege state + * @retval HAL_StatusTypeDef + */ +HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(const RTC_HandleTypeDef *hrtc, + const RTC_PrivilegeStateTypeDef *privilegeState) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + assert_param(IS_RTC_PRIVILEGE_FULL(privilegeState->rtcPrivilegeFull)); + assert_param(IS_RTC_PRIVILEGE_FEATURES(privilegeState->rtcPrivilegeFeatures)); + assert_param(IS_TAMP_PRIVILEGE_FULL(privilegeState->tampPrivilegeFull)); + assert_param(IS_TAMP_MONOTONIC_CNT_PRIVILEGE(privilegeState->MonotonicCounterPrivilege)); + assert_param(IS_RTC_PRIVILEGE_BKUP_ZONE(privilegeState->backupRegisterPrivZone)); + assert_param(IS_RTC_BKP(privilegeState->backupRegisterStartZone2)); + assert_param(IS_RTC_BKP(privilegeState->backupRegisterStartZone3)); + + /* RTC privilege configuration */ + WRITE_REG(RTC->PRIVCFGR, privilegeState->rtcPrivilegeFull | privilegeState->rtcPrivilegeFeatures); + + /* TAMP, Monotonic counter and Backup registers privilege configuration */ + WRITE_REG(TAMP->PRIVCFGR, privilegeState->tampPrivilegeFull | privilegeState->backupRegisterPrivZone | \ + privilegeState->MonotonicCounterPrivilege); + + /* Backup register start zone */ + MODIFY_REG(TAMP->CFGR, + (TAMP_CFGR_BKPRW | TAMP_CFGR_BKPW), + ((privilegeState->backupRegisterStartZone2 << TAMP_CFGR_BKPRW_Pos) | (privilegeState->backupRegisterStartZone3 << TAMP_CFGR_BKPW_Pos))); + + return HAL_OK; +} + +/** + * @brief Get the privilege level of the RTC/TAMP/Backup registers. + * To set the privilege level please call HAL_RTCEx_PrivilegeModeSet. + * @param hrtc RTC handle + * @param privilegeState Privilege state + * @retval HAL_StatusTypeDef + */ +HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(const RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Read registers */ + uint32_t rtc_privcfgr = READ_REG(RTC->PRIVCFGR); + uint32_t tamp_privcfgr = READ_REG(TAMP->PRIVCFGR); + uint32_t tamp_cfgr = READ_REG(TAMP->CFGR); + + /* RTC privilege configuration */ + privilegeState->rtcPrivilegeFull = READ_BIT(rtc_privcfgr, RTC_PRIVCFGR_PRIV); + + /* Warning, rtcPrivilegeFeatures is only relevant if privilegeState->rtcPrivilegeFull == RTC_PRIVILEGE_FULL_NO */ + privilegeState->rtcPrivilegeFeatures = READ_BIT(rtc_privcfgr, RTC_PRIVILEGE_FEATURE_ALL); + + /* TAMP and Backup registers privilege configuration */ + privilegeState->tampPrivilegeFull = READ_BIT(tamp_privcfgr, TAMP_PRIVCFGR_TAMPPRIV); + + /* Monotonic registers privilege configuration */ + privilegeState->MonotonicCounterPrivilege = READ_BIT(tamp_privcfgr, TAMP_PRIVCFGR_CNT1PRIV); + + /* Backup registers Zones */ + privilegeState->backupRegisterPrivZone = READ_BIT(tamp_privcfgr, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV)); + + /* Backup registers start zones */ + privilegeState->backupRegisterStartZone2 = READ_BIT(tamp_cfgr, TAMP_CFGR_BKPRW) >> TAMP_CFGR_BKPRW_Pos; + privilegeState->backupRegisterStartZone3 = READ_BIT(tamp_cfgr, TAMP_CFGR_BKPW) >> TAMP_CFGR_BKPW_Pos; + + return HAL_OK; +} + +/** + * @} + */ +#endif /* TAMP_PRIVCFGR_TAMPPRIV */ + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ + +/** + * @} + */ + + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sai.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sai.c new file mode 100644 index 00000000000..6e2221c171a --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sai.c @@ -0,0 +1,2898 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_sai.c + * @author MCD Application Team + * @brief SAI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Audio Interface (SAI) peripheral: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + The SAI HAL driver can be used as follows: + + (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai). + (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API: + (##) Enable the SAI interface clock. + (##) SAI pins configuration: + (+++) Enable the clock for the SAI GPIOs. + (+++) Configure these SAI pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT() + and HAL_SAI_Receive_IT() APIs): + (+++) Configure the SAI interrupt priority. + (+++) Enable the NVIC SAI IRQ handle. + + (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA() + and HAL_SAI_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx stream. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx Stream. + (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the + DMA Tx/Rx Stream. + + (#) The initialization can be done by two ways + (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init(). + (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol(). + + [..] + (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt) + will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT() + inside the transmit and receive process. + [..] + (@) Make sure that either: + (+@) PLLSAI1CLK output is configured or + (+@) PLLSAI2CLK output is configured or + (+@) PLLSAI3CLK output is configured or + (+@) External clock source is configured after setting correctly + the define constant EXTERNAL_SAI1_CLOCK_VALUE or EXTERNAL_SAI2_CLOCK_VALUE + in the stm32h7rsxx_hal_conf.h file. + + [..] + (@) In master Tx mode: enabling the audio block immediately generates the bit clock + for the external slaves even if there is no data in the FIFO, However FS signal + generation is conditioned by the presence of data in the FIFO. + + [..] + (@) In master Rx mode: enabling the audio block immediately generates the bit clock + and FS signal for the external slaves. + + [..] + (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior: + (+@) First bit Offset <= (SLOT size - Data size) + (+@) Data size <= SLOT size + (+@) Number of SLOT x SLOT size = Frame length + (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected. + + [..] + (@) PDM interface can be activated through HAL_SAI_Init function. + Please note that PDM interface is only available for SAI1 sub-block A. + PDM microphone delays can be tuned with HAL_SAIEx_ConfigPdmMicDelay function. + + [..] + Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_SAI_Transmit() + (+) Receive an amount of data in blocking mode using HAL_SAI_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT() + (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SAI_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT() + (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SAI_RxCpltCallback() + (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SAI_ErrorCallback() + + *** DMA mode IO operation *** + ============================= + [..] + (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA() + (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SAI_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA() + (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SAI_RxCpltCallback() + (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SAI_ErrorCallback() + (+) Pause the DMA Transfer using HAL_SAI_DMAPause() + (+) Resume the DMA Transfer using HAL_SAI_DMAResume() + (+) Stop the DMA Transfer using HAL_SAI_DMAStop() + + *** SAI HAL driver additional function list *** + =============================================== + [..] + Below the list the others API available SAI HAL driver : + + (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode + (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode + (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode + (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode + (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo. + (+) HAL_SAI_Abort(): Abort the current transfer + + *** SAI HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SAI HAL driver : + + (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral + (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral + (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts + (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts + (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is + enabled or disabled + (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not + + *** Callback registration *** + ============================= + [..] + The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use functions HAL_SAI_RegisterCallback() to register a user callback. + + [..] + Function HAL_SAI_RegisterCallback() allows to register following callbacks: + (+) RxCpltCallback : SAI receive complete. + (+) RxHalfCpltCallback : SAI receive half complete. + (+) TxCpltCallback : SAI transmit complete. + (+) TxHalfCpltCallback : SAI transmit half complete. + (+) ErrorCallback : SAI error. + (+) MspInitCallback : SAI MspInit. + (+) MspDeInitCallback : SAI MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the callback ID. + [..] + This function allows to reset following callbacks: + (+) RxCpltCallback : SAI receive complete. + (+) RxHalfCpltCallback : SAI receive half complete. + (+) TxCpltCallback : SAI transmit complete. + (+) TxHalfCpltCallback : SAI transmit half complete. + (+) ErrorCallback : SAI error. + (+) MspInitCallback : SAI MspInit. + (+) MspDeInitCallback : SAI MspDeInit. + + [..] + By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET + all callbacks are reset to the corresponding legacy weak functions: + examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback(). + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak functions in the HAL_SAI_Init + and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit + or HAL_SAI_Init function. + + [..] + When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak callbacks are used. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup SAI SAI + * @brief SAI HAL module driver + * @{ + */ + +#ifdef HAL_SAI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/** @defgroup SAI_Private_Typedefs SAI Private Typedefs + * @{ + */ +typedef enum +{ + SAI_MODE_DMA, + SAI_MODE_IT +} SAI_ModeTypedef; +/** + * @} + */ + +/* Private define ------------------------------------------------------------*/ +/** @defgroup SAI_Private_Constants SAI Private Constants + * @{ + */ +#define SAI_DEFAULT_TIMEOUT 4U +#define SAI_LONG_TIMEOUT 1000U +#define SAI_SPDIF_FRAME_LENGTH 64U +#define SAI_AC97_FRAME_LENGTH 256U +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SAI_Private_Functions SAI Private Functions + * @{ + */ +static void SAI_FillFifo(SAI_HandleTypeDef *hsai); +static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode); +static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); +static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); + +static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai); +static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai); +static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai); +static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai); +static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai); +static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai); +static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai); + +static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma); +static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma); +static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void SAI_DMAError(DMA_HandleTypeDef *hdma); +static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup SAI_Exported_Functions SAI Exported Functions + * @{ + */ + +/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SAIx peripheral: + + (+) User must implement HAL_SAI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SAI_Init() to configure the selected device with + the selected configuration: + (++) Mode (Master/slave TX/RX) + (++) Protocol + (++) Data Size + (++) MCLK Output + (++) Audio frequency + (++) FIFO Threshold + (++) Frame Config + (++) Slot Config + (++) PDM Config + + (+) Call the function HAL_SAI_DeInit() to restore the default configuration + of the selected SAI peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the structure FrameInit, SlotInit and the low part of + * Init according to the specified parameters and call the function + * HAL_SAI_Init to initialize the SAI block. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param protocol one of the supported protocol @ref SAI_Protocol + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize + * the configuration information for SAI module. + * @param nbslot Number of slot. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol)); + assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize)); + + switch (protocol) + { + case SAI_I2S_STANDARD : + case SAI_I2S_MSBJUSTIFIED : + case SAI_I2S_LSBJUSTIFIED : + status = SAI_InitI2S(hsai, protocol, datasize, nbslot); + break; + case SAI_PCM_LONG : + case SAI_PCM_SHORT : + status = SAI_InitPCM(hsai, protocol, datasize, nbslot); + break; + default : + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + status = HAL_SAI_Init(hsai); + } + + return status; +} + +/** + * @brief Initialize the SAI according to the specified parameters. + * in the SAI_InitTypeDef structure and initialize the associated handle. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) +{ + uint32_t tmpregisterGCR; + uint32_t ckstr_bits; + uint32_t syncen_bits; + + /* Check the SAI handle allocation */ + if (hsai == NULL) + { + return HAL_ERROR; + } + + /* check the instance */ + assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance)); + + /* Check the SAI Block parameters */ + assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency)); + assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol)); + assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode)); + assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize)); + assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit)); + assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing)); + assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro)); + assert_param(IS_SAI_BLOCK_MCK_OUTPUT(hsai->Init.MckOutput)); + assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive)); + assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider)); + assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold)); + assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode)); + assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode)); + assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState)); + assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt)); + assert_param(IS_SAI_BLOCK_MCK_OVERSAMPLING(hsai->Init.MckOverSampling)); + + /* Check the SAI Block Frame parameters */ + assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength)); + assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength)); + assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition)); + assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity)); + assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset)); + + /* Check the SAI Block Slot parameters */ + assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset)); + assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize)); + assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber)); + assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive)); + + /* Check the SAI PDM parameters */ + assert_param(IS_FUNCTIONAL_STATE(hsai->Init.PdmInit.Activation)); + if (hsai->Init.PdmInit.Activation == ENABLE) + { + assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(hsai->Init.PdmInit.MicPairsNbr)); + assert_param(IS_SAI_PDM_CLOCK_ENABLE(hsai->Init.PdmInit.ClockEnable)); + /* Check that SAI sub-block is SAI1 sub-block A, in master RX mode with free protocol */ + if ((hsai->Instance != SAI1_Block_A) || + (hsai->Init.AudioMode != SAI_MODEMASTER_RX) || + (hsai->Init.Protocol != SAI_FREE_PROTOCOL)) + { + return HAL_ERROR; + } + } + + if (hsai->State == HAL_SAI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsai->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hsai->RxCpltCallback = HAL_SAI_RxCpltCallback; + hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback; + hsai->TxCpltCallback = HAL_SAI_TxCpltCallback; + hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback; + hsai->ErrorCallback = HAL_SAI_ErrorCallback; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + if (hsai->MspInitCallback == NULL) + { + hsai->MspInitCallback = HAL_SAI_MspInit; + } + hsai->MspInitCallback(hsai); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_SAI_MspInit(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + + /* Disable the selected SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + return HAL_ERROR; + } + + hsai->State = HAL_SAI_STATE_BUSY; + + /* SAI Block Synchro Configuration -----------------------------------------*/ + /* This setting must be done with both audio block (A & B) disabled */ + switch (hsai->Init.SynchroExt) + { + case SAI_SYNCEXT_DISABLE : + tmpregisterGCR = 0; + break; + case SAI_SYNCEXT_OUTBLOCKA_ENABLE : + tmpregisterGCR = SAI_GCR_SYNCOUT_0; + break; + case SAI_SYNCEXT_OUTBLOCKB_ENABLE : + tmpregisterGCR = SAI_GCR_SYNCOUT_1; + break; + default : + tmpregisterGCR = 0; + break; + } + + switch (hsai->Init.Synchro) + { + case SAI_ASYNCHRONOUS : + syncen_bits = 0; + break; + case SAI_SYNCHRONOUS : + syncen_bits = SAI_xCR1_SYNCEN_0; + break; + case SAI_SYNCHRONOUS_EXT_SAI1 : + syncen_bits = SAI_xCR1_SYNCEN_1; + break; + case SAI_SYNCHRONOUS_EXT_SAI2 : + syncen_bits = SAI_xCR1_SYNCEN_1; + tmpregisterGCR |= SAI_GCR_SYNCIN_0; + break; + default : + syncen_bits = 0; + break; + } + + if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) + { + SAI1->GCR = tmpregisterGCR; + } + else + { + SAI2->GCR = tmpregisterGCR; + } + + if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) + { + uint32_t freq = 0; + uint32_t tmpval; + + /* In this case, the MCKDIV value is calculated to get AudioFrequency */ + if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) + { + freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); + } + if ((hsai->Instance == SAI2_Block_A) || (hsai->Instance == SAI2_Block_B)) + { + freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2); + } + + /* Configure Master Clock Divider using the following formula : + - If NODIV = 1 : + MCKDIV[5:0] = SAI_CK_x / (FS * (FRL + 1)) + - If NODIV = 0 : + MCKDIV[5:0] = SAI_CK_x / (FS * (OSR + 1) * 256) */ + if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE) + { + /* NODIV = 1 */ + uint32_t tmpframelength; + + if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL) + { + /* For SPDIF protocol, frame length is set by hardware to 64 */ + tmpframelength = SAI_SPDIF_FRAME_LENGTH; + } + else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL) + { + /* For AC97 protocol, frame length is set by hardware to 256 */ + tmpframelength = SAI_AC97_FRAME_LENGTH; + } + else + { + /* For free protocol, frame length is set by user */ + tmpframelength = hsai->FrameInit.FrameLength; + } + + /* (freq x 10) to keep Significant digits */ + tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmpframelength); + } + else + { + /* NODIV = 0 */ + uint32_t tmposr; + tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2U : 1U; + /* (freq x 10) to keep Significant digits */ + tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmposr * 256U); + } + hsai->Init.Mckdiv = tmpval / 10U; + + /* Round result to the nearest integer */ + if ((tmpval % 10U) > 8U) + { + hsai->Init.Mckdiv += 1U; + } + + /* For SPDIF protocol, SAI shall provide a bit clock twice faster the symbol-rate */ + if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL) + { + hsai->Init.Mckdiv = hsai->Init.Mckdiv >> 1; + } + } + + /* Check the SAI Block master clock divider parameter */ + assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv)); + + /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */ + if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + /* Transmit */ + ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0U : SAI_xCR1_CKSTR; + } + else + { + /* Receive */ + ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0U; + } + + /* SAI Block Configuration -------------------------------------------------*/ + /* SAI CR1 Configuration */ + hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ + SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \ + SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ + SAI_xCR1_NODIV | SAI_xCR1_MCKDIV | SAI_xCR1_OSR | \ + SAI_xCR1_MCKEN); + + hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol | \ + hsai->Init.DataSize | hsai->Init.FirstBit | \ + ckstr_bits | syncen_bits | \ + hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ + hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | \ + hsai->Init.MckOverSampling | hsai->Init.MckOutput); + + /* SAI CR2 Configuration */ + hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL); + hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState); + + /* SAI Frame Configuration -----------------------------------------*/ + hsai->Instance->FRCR &= (~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \ + SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF)); + hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1U) | + hsai->FrameInit.FSOffset | + hsai->FrameInit.FSDefinition | + hsai->FrameInit.FSPolarity | + ((hsai->FrameInit.ActiveFrameLength - 1U) << 8)); + + /* SAI Block_x SLOT Configuration ------------------------------------------*/ + /* This register has no meaning in AC 97 and SPDIF audio protocol */ + hsai->Instance->SLOTR &= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \ + SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN)); + + hsai->Instance->SLOTR |= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize | \ + (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1U) << 8); + + /* SAI PDM Configuration ---------------------------------------------------*/ + if (hsai->Instance == SAI1_Block_A) + { + /* Disable PDM interface */ + SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN); + if (hsai->Init.PdmInit.Activation == ENABLE) + { + /* Configure and enable PDM interface */ + SAI1->PDMCR = (hsai->Init.PdmInit.ClockEnable | + ((hsai->Init.PdmInit.MicPairsNbr - 1U) << SAI_PDMCR_MICNBR_Pos)); + SAI1->PDMCR |= SAI_PDMCR_PDMEN; + } + } + + /* Initialize the error code */ + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + + /* Initialize the SAI state */ + hsai->State = HAL_SAI_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(hsai); + + return HAL_OK; +} + +/** + * @brief DeInitialize the SAI peripheral. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) +{ + /* Check the SAI handle allocation */ + if (hsai == NULL) + { + return HAL_ERROR; + } + + hsai->State = HAL_SAI_STATE_BUSY; + + /* Disabled All interrupt and clear all the flag */ + hsai->Instance->IMR = 0; + hsai->Instance->CLRFR = 0xFFFFFFFFU; + + /* Disable the SAI */ + if (SAI_Disable(hsai) != HAL_OK) + { + /* Reset SAI state to ready */ + hsai->State = HAL_SAI_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(hsai); + + return HAL_ERROR; + } + + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + + /* Disable SAI PDM interface */ + if (hsai->Instance == SAI1_Block_A) + { + /* Reset PDM delays */ + SAI1->PDMDLY = 0U; + + /* Disable PDM interface */ + SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN); + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + if (hsai->MspDeInitCallback == NULL) + { + hsai->MspDeInitCallback = HAL_SAI_MspDeInit; + } + hsai->MspDeInitCallback(hsai); +#else + HAL_SAI_MspDeInit(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + + /* Initialize the error code */ + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + + /* Initialize the SAI state */ + hsai->State = HAL_SAI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsai); + + return HAL_OK; +} + +/** + * @brief Initialize the SAI MSP. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +__weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsai); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SAI_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the SAI MSP. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +__weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsai); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SAI_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user SAI callback + * to be used instead of the weak predefined callback. + * @param hsai SAI handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID. + * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID. + * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID. + * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID. + * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID. + * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID, + pSAI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if (HAL_SAI_STATE_READY == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_RX_COMPLETE_CB_ID : + hsai->RxCpltCallback = pCallback; + break; + case HAL_SAI_RX_HALFCOMPLETE_CB_ID : + hsai->RxHalfCpltCallback = pCallback; + break; + case HAL_SAI_TX_COMPLETE_CB_ID : + hsai->TxCpltCallback = pCallback; + break; + case HAL_SAI_TX_HALFCOMPLETE_CB_ID : + hsai->TxHalfCpltCallback = pCallback; + break; + case HAL_SAI_ERROR_CB_ID : + hsai->ErrorCallback = pCallback; + break; + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = pCallback; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SAI_STATE_RESET == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = pCallback; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user SAI callback. + * SAI callback is redirected to the weak predefined callback. + * @param hsai SAI handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID. + * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID. + * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID. + * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID. + * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID. + * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_SAI_STATE_READY == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_RX_COMPLETE_CB_ID : + hsai->RxCpltCallback = HAL_SAI_RxCpltCallback; + break; + case HAL_SAI_RX_HALFCOMPLETE_CB_ID : + hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback; + break; + case HAL_SAI_TX_COMPLETE_CB_ID : + hsai->TxCpltCallback = HAL_SAI_TxCpltCallback; + break; + case HAL_SAI_TX_HALFCOMPLETE_CB_ID : + hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback; + break; + case HAL_SAI_ERROR_CB_ID : + hsai->ErrorCallback = HAL_SAI_ErrorCallback; + break; + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = HAL_SAI_MspInit; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = HAL_SAI_MspDeInit; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SAI_STATE_RESET == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = HAL_SAI_MspInit; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = HAL_SAI_MspDeInit; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + return status; +} +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup SAI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SAI data + transfers. + + (+) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (+) Blocking mode functions are : + (++) HAL_SAI_Transmit() + (++) HAL_SAI_Receive() + + (+) Non Blocking mode functions with Interrupt are : + (++) HAL_SAI_Transmit_IT() + (++) HAL_SAI_Receive_IT() + + (+) Non Blocking mode functions with DMA are : + (++) HAL_SAI_Transmit_DMA() + (++) HAL_SAI_Receive_DMA() + + (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_SAI_TxCpltCallback() + (++) HAL_SAI_RxCpltCallback() + (++) HAL_SAI_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t temp; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hsai->State == HAL_SAI_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsai); + + hsai->XferSize = Size; + hsai->XferCount = Size; + hsai->pBuffPtr = pData; + hsai->State = HAL_SAI_STATE_BUSY_TX; + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + + /* Check if the SAI is already enabled */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) + { + /* fill the fifo with data before to enabled the SAI */ + SAI_FillFifo(hsai); + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + + while (hsai->XferCount > 0U) + { + /* Write data if the FIFO is not full */ + if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) + { + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + { + hsai->Instance->DR = *hsai->pBuffPtr; + hsai->pBuffPtr++; + } + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) + { + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; + } + else + { + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 16); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 24); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; + } + hsai->XferCount--; + } + else + { + /* Check for the Timeout */ + if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY)) + { + /* Update error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; + + /* Clear all the flags */ + hsai->Instance->CLRFR = 0xFFFFFFFFU; + + /* Disable SAI peripheral */ + /* No need to check return value because state update, unlock and error return will be performed later */ + (void) SAI_Disable(hsai); + + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + + /* Change the SAI state */ + hsai->State = HAL_SAI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_ERROR; + } + } + } + + hsai->State = HAL_SAI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t temp; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hsai->State == HAL_SAI_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsai); + + hsai->pBuffPtr = pData; + hsai->XferSize = Size; + hsai->XferCount = Size; + hsai->State = HAL_SAI_STATE_BUSY_RX; + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + + /* Check if the SAI is already enabled */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) + { + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + + /* Receive data */ + while (hsai->XferCount > 0U) + { + if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY) + { + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + { + *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR; + hsai->pBuffPtr++; + } + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) + { + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; + } + else + { + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 16); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 24); + hsai->pBuffPtr++; + } + hsai->XferCount--; + } + else + { + /* Check for the Timeout */ + if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY)) + { + /* Update error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; + + /* Clear all the flags */ + hsai->Instance->CLRFR = 0xFFFFFFFFU; + + /* Disable SAI peripheral */ + /* No need to check return value because state update, unlock and error return will be performed later */ + (void) SAI_Disable(hsai); + + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + + /* Change the SAI state */ + hsai->State = HAL_SAI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_ERROR; + } + } + } + + hsai->State = HAL_SAI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) +{ + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hsai->State == HAL_SAI_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsai); + + hsai->pBuffPtr = pData; + hsai->XferSize = Size; + hsai->XferCount = Size; + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + hsai->State = HAL_SAI_STATE_BUSY_TX; + + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + { + hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit; + } + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) + { + hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit; + } + else + { + hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit; + } + + /* Fill the fifo before starting the communication */ + SAI_FillFifo(hsai); + + /* Enable FRQ and OVRUDR interrupts */ + __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + + /* Check if the SAI is already enabled */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) + { + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) +{ + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hsai->State == HAL_SAI_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsai); + + hsai->pBuffPtr = pData; + hsai->XferSize = Size; + hsai->XferCount = Size; + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + hsai->State = HAL_SAI_STATE_BUSY_RX; + + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + { + hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit; + } + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) + { + hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit; + } + else + { + hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit; + } + + /* Enable TXE and OVRUDR interrupts */ + __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + + /* Check if the SAI is already enabled */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) + { + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the audio stream playing from the Media. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai) +{ + /* Process Locked */ + __HAL_LOCK(hsai); + + /* Pause the audio file playing by disabling the SAI DMA requests */ + hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; +} + +/** + * @brief Resume the audio stream playing from the Media. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai) +{ + /* Process Locked */ + __HAL_LOCK(hsai); + + /* Enable the SAI DMA requests */ + hsai->Instance->CR1 |= SAI_xCR1_DMAEN; + + /* If the SAI peripheral is still not enabled, enable it */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) + { + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; +} + +/** + * @brief Stop the audio stream playing from the Media. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hsai); + + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + + /* Disable the SAI DMA request */ + hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; + + /* Abort the SAI Tx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL)) + { + if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) + { + /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } + } + } + + /* Abort the SAI Rx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL)) + { + if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) + { + /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } + } + } + + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + + /* Set hsai state to ready */ + hsai->State = HAL_SAI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return status; +} + +/** + * @brief Abort the current transfer and disable the SAI. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hsai); + + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + + /* Check SAI DMA is enabled or not */ + if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + { + /* Disable the SAI DMA request */ + hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; + + /* Abort the SAI Tx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL)) + { + if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) + { + /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } + } + } + + /* Abort the SAI Rx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL)) + { + if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) + { + /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } + } + } + } + + /* Disabled All interrupt and clear all the flag */ + hsai->Instance->IMR = 0; + hsai->Instance->CLRFR = 0xFFFFFFFFU; + + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + + /* Set hsai state to ready */ + hsai->State = HAL_SAI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return status; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hsai->State == HAL_SAI_STATE_READY) + { + uint32_t dmaSrcSize; + + /* Process Locked */ + __HAL_LOCK(hsai); + + hsai->pBuffPtr = pData; + hsai->XferSize = Size; + hsai->XferCount = Size; + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + hsai->State = HAL_SAI_STATE_BUSY_TX; + + /* Set the SAI Tx DMA Half transfer complete callback */ + hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt; + + /* Set the SAI TxDMA transfer complete callback */ + hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt; + + /* Set the DMA error callback */ + hsai->hdmatx->XferErrorCallback = SAI_DMAError; + + /* Set the DMA Tx abort callback */ + hsai->hdmatx->XferAbortCallback = NULL; + + /* For transmission, the DMA source is data buffer. + We have to compute DMA size of a source block transfer in bytes according SAI data size. */ + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + { + dmaSrcSize = (uint32_t) Size; + } + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) + { + dmaSrcSize = 2U * (uint32_t) Size; + } + else + { + dmaSrcSize = 4U * (uint32_t) Size; + } + + /* Enable the Tx DMA Stream */ + if ((hsai->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hsai->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hsai->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = dmaSrcSize; + + /* Set DMA source address */ + hsai->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hsai->pBuffPtr; + + /* Set DMA destination address */ + hsai->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hsai->Instance->DR; + + status = HAL_DMAEx_List_Start_IT(hsai->hdmatx); + } + else + { + __HAL_UNLOCK(hsai); + return HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, dmaSrcSize); + } + + if (status != HAL_OK) + { + __HAL_UNLOCK(hsai); + return HAL_ERROR; + } + + /* Enable the interrupts for error handling */ + __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); + + /* Enable SAI Tx DMA Request */ + hsai->Instance->CR1 |= SAI_xCR1_DMAEN; + + /* Wait until FIFO is not empty */ + while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT) + { + /* Update error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_TIMEOUT; + } + } + + /* Check if the SAI is already enabled */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) + { + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hsai->State == HAL_SAI_STATE_READY) + { + uint32_t dmaSrcSize; + + /* Process Locked */ + __HAL_LOCK(hsai); + + hsai->pBuffPtr = pData; + hsai->XferSize = Size; + hsai->XferCount = Size; + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + hsai->State = HAL_SAI_STATE_BUSY_RX; + + /* Set the SAI Rx DMA Half transfer complete callback */ + hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt; + + /* Set the SAI Rx DMA transfer complete callback */ + hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt; + + /* Set the DMA error callback */ + hsai->hdmarx->XferErrorCallback = SAI_DMAError; + + /* Set the DMA Rx abort callback */ + hsai->hdmarx->XferAbortCallback = NULL; + + /* For reception, the DMA source is SAI DR register. + We have to compute DMA size of a source block transfer in bytes according SAI data size. */ + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + { + dmaSrcSize = (uint32_t) Size; + } + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) + { + dmaSrcSize = 2U * (uint32_t) Size; + } + else + { + dmaSrcSize = 4U * (uint32_t) Size; + } + + /* Enable the Rx DMA Stream */ + if ((hsai->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hsai->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hsai->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = dmaSrcSize; + + /* Set DMA source address */ + hsai->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hsai->Instance->DR; + + /* Set DMA destination address */ + hsai->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hsai->pBuffPtr; + + status = HAL_DMAEx_List_Start_IT(hsai->hdmarx); + } + else + { + __HAL_UNLOCK(hsai); + return HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, dmaSrcSize); + } + + if (status != HAL_OK) + { + __HAL_UNLOCK(hsai); + return HAL_ERROR; + } + + /* Enable the interrupts for error handling */ + __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); + + /* Enable SAI Rx DMA Request */ + hsai->Instance->CR1 |= SAI_xCR1_DMAEN; + + /* Check if the SAI is already enabled */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) + { + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the Tx mute mode. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param val value sent during the mute @ref SAI_Block_Mute_Value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val) +{ + assert_param(IS_SAI_BLOCK_MUTE_VALUE(val)); + + if (hsai->State != HAL_SAI_STATE_RESET) + { + CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE); + SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | (uint32_t)val); + return HAL_OK; + } + return HAL_ERROR; +} + +/** + * @brief Disable the Tx mute mode. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) +{ + if (hsai->State != HAL_SAI_STATE_RESET) + { + CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE); + return HAL_OK; + } + return HAL_ERROR; +} + +/** + * @brief Enable the Rx mute detection. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param callback function called when the mute is detected. + * @param counter number a data before mute detection max 63. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter) +{ + assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter)); + + if (hsai->State != HAL_SAI_STATE_RESET) + { + /* set the mute counter */ + CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT); + SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_Pos)); + hsai->mutecallback = callback; + /* enable the IT interrupt */ + __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET); + return HAL_OK; + } + return HAL_ERROR; +} + +/** + * @brief Disable the Rx mute detection. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) +{ + if (hsai->State != HAL_SAI_STATE_RESET) + { + /* set the mutecallback to NULL */ + hsai->mutecallback = NULL; + /* enable the IT interrupt */ + __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET); + return HAL_OK; + } + return HAL_ERROR; +} + +/** + * @brief Handle SAI interrupt request. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) +{ + if (hsai->State != HAL_SAI_STATE_RESET) + { + uint32_t itflags = hsai->Instance->SR; + uint32_t itsources = hsai->Instance->IMR; + uint32_t cr1config = hsai->Instance->CR1; + uint32_t tmperror; + + /* SAI Fifo request interrupt occurred -----------------------------------*/ + if (((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) + { + hsai->InterruptServiceRoutine(hsai); + } + /* SAI Overrun error interrupt occurred ----------------------------------*/ + else if (((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR)) + { + /* Clear the SAI Overrun flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); + /* Get the SAI error code */ + tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR); + /* Change the SAI error code */ + hsai->ErrorCode |= tmperror; + /* the transfer is not stopped, we will forward the information to the user and we let + the user decide what needs to be done */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + /* SAI mutedet interrupt occurred ----------------------------------*/ + else if (((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET)) + { + /* Clear the SAI mutedet flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET); + /* call the call back function */ + if (hsai->mutecallback != NULL) + { + /* inform the user that an RX mute event has been detected */ + hsai->mutecallback(); + } + } + /* SAI AFSDET interrupt occurred ----------------------------------*/ + else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET)) + { + /* Clear the SAI AFSDET flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_AFSDET); + + /* Change the SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET; + + /* Check SAI DMA is enabled or not */ + if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + { + /* Abort the SAI DMA Streams */ + if (hsai->hdmatx != NULL) + { + /* Set the DMA Tx abort callback */ + hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; + + /* Abort DMA in IT mode */ + if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + if (hsai->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; + + /* Abort DMA in IT mode */ + if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Abort SAI */ + /* No need to check return value because HAL_SAI_ErrorCallback will be called later */ + (void) HAL_SAI_Abort(hsai); + + /* Set error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + /* SAI LFSDET interrupt occurred ----------------------------------*/ + else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET)) + { + /* Clear the SAI LFSDET flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_LFSDET); + + /* Change the SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET; + + /* Check SAI DMA is enabled or not */ + if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + { + /* Abort the SAI DMA Streams */ + if (hsai->hdmatx != NULL) + { + /* Set the DMA Tx abort callback */ + hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; + + /* Abort DMA in IT mode */ + if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + if (hsai->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; + + /* Abort DMA in IT mode */ + if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Abort SAI */ + /* No need to check return value because HAL_SAI_ErrorCallback will be called later */ + (void) HAL_SAI_Abort(hsai); + + /* Set error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + /* SAI WCKCFG interrupt occurred ----------------------------------*/ + else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG)) + { + /* Clear the SAI WCKCFG flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_WCKCFG); + + /* Change the SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG; + + /* Check SAI DMA is enabled or not */ + if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + { + /* Abort the SAI DMA Streams */ + if (hsai->hdmatx != NULL) + { + /* Set the DMA Tx abort callback */ + hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; + + /* Abort DMA in IT mode */ + if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + if (hsai->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; + + /* Abort DMA in IT mode */ + if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + } + else + { + /* If WCKCFG occurs, SAI audio block is automatically disabled */ + /* Disable all interrupts and clear all flags */ + hsai->Instance->IMR = 0U; + hsai->Instance->CLRFR = 0xFFFFFFFFU; + /* Set the SAI state to ready to be able to start again the process */ + hsai->State = HAL_SAI_STATE_READY; + + /* Initialize XferCount */ + hsai->XferCount = 0U; + + /* SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + /* SAI CNRDY interrupt occurred ----------------------------------*/ + else if (((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY)) + { + /* Clear the SAI CNRDY flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY); + /* Change the SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY; + /* the transfer is not stopped, we will forward the information to the user and we let + the user decide what needs to be done */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsai); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SAI_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Transfer Half completed callback. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +__weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsai); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SAI_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsai); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SAI_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer half completed callback. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsai); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SAI_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief SAI error callback. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsai); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SAI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the SAI handle state. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL state + */ +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai) +{ + return hsai->State; +} + +/** + * @brief Return the SAI error code. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for the specified SAI Block. + * @retval SAI Error Code + */ +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai) +{ + return hsai->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SAI_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief Initialize the SAI I2S protocol according to the specified parameters + * in the SAI_InitTypeDef and create the associated handle. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param protocol one of the supported protocol. + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize. + * @param nbslot number of slot minimum value is 2 and max is 16. + * the value must be a multiple of 2. + * @retval HAL status + */ +static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) +{ + HAL_StatusTypeDef status = HAL_OK; + + hsai->Init.Protocol = SAI_FREE_PROTOCOL; + hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; + /* Compute ClockStrobing according AudioMode */ + if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + /* Transmit */ + hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; + } + else + { + /* Receive */ + hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; + } + hsai->FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; + hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; + hsai->SlotInit.FirstBitOffset = 0; + hsai->SlotInit.SlotNumber = nbslot; + + /* in IS2 the number of slot must be even */ + if ((nbslot & 0x1U) != 0U) + { + return HAL_ERROR; + } + + if (protocol == SAI_I2S_STANDARD) + { + hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + } + else + { + /* SAI_I2S_MSBJUSTIFIED or SAI_I2S_LSBJUSTIFIED */ + hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; + hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT; + } + + /* Frame definition */ + switch (datasize) + { + case SAI_PROTOCOL_DATASIZE_16BIT: + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 32U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 16U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; + break; + case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 64U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_24BIT: + hsai->Init.DataSize = SAI_DATASIZE_24; + hsai->FrameInit.FrameLength = 64U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_32BIT: + hsai->Init.DataSize = SAI_DATASIZE_32; + hsai->FrameInit.FrameLength = 64U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + default : + status = HAL_ERROR; + break; + } + if (protocol == SAI_I2S_LSBJUSTIFIED) + { + if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) + { + hsai->SlotInit.FirstBitOffset = 16; + } + if (datasize == SAI_PROTOCOL_DATASIZE_24BIT) + { + hsai->SlotInit.FirstBitOffset = 8; + } + } + return status; +} + +/** + * @brief Initialize the SAI PCM protocol according to the specified parameters + * in the SAI_InitTypeDef and create the associated handle. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param protocol one of the supported protocol + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize + * @param nbslot number of slot minimum value is 1 and the max is 16. + * @retval HAL status + */ +static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) +{ + HAL_StatusTypeDef status = HAL_OK; + + hsai->Init.Protocol = SAI_FREE_PROTOCOL; + hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; + /* Compute ClockStrobing according AudioMode */ + if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + /* Transmit */ + hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; + } + else + { + /* Receive */ + hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; + } + hsai->FrameInit.FSDefinition = SAI_FS_STARTFRAME; + hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; + hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + hsai->SlotInit.FirstBitOffset = 0; + hsai->SlotInit.SlotNumber = nbslot; + hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; + + if (protocol == SAI_PCM_SHORT) + { + hsai->FrameInit.ActiveFrameLength = 1; + } + else + { + /* SAI_PCM_LONG */ + hsai->FrameInit.ActiveFrameLength = 13; + } + + switch (datasize) + { + case SAI_PROTOCOL_DATASIZE_16BIT: + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 16U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; + break; + case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 32U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_24BIT : + hsai->Init.DataSize = SAI_DATASIZE_24; + hsai->FrameInit.FrameLength = 32U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_32BIT: + hsai->Init.DataSize = SAI_DATASIZE_32; + hsai->FrameInit.FrameLength = 32U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + default : + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Fill the fifo. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static void SAI_FillFifo(SAI_HandleTypeDef *hsai) +{ + uint32_t temp; + + /* fill the fifo with data before to enabled the SAI */ + while (((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0U)) + { + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + { + hsai->Instance->DR = *hsai->pBuffPtr; + hsai->pBuffPtr++; + } + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) + { + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; + } + else + { + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 16); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 24); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; + } + hsai->XferCount--; + } +} + +/** + * @brief Return the interrupt flag to set according the SAI setup. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param mode SAI_MODE_DMA or SAI_MODE_IT + * @retval the list of the IT flag to enable + */ +static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode) +{ + uint32_t tmpIT = SAI_IT_OVRUDR; + + if (mode == SAI_MODE_IT) + { + tmpIT |= SAI_IT_FREQ; + } + + if ((hsai->Init.Protocol == SAI_AC97_PROTOCOL) && + ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX))) + { + tmpIT |= SAI_IT_CNRDY; + } + + if ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + tmpIT |= SAI_IT_AFSDET | SAI_IT_LFSDET; + } + else + { + /* hsai has been configured in master mode */ + tmpIT |= SAI_IT_WCKCFG; + } + return tmpIT; +} + +/** + * @brief Disable the SAI and wait for the disabling. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) +{ + uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U); + HAL_StatusTypeDef status = HAL_OK; + + /* Disable the SAI instance */ + __HAL_SAI_DISABLE(hsai); + + do + { + /* Check for the Timeout */ + if (count == 0U) + { + /* Update error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; + status = HAL_TIMEOUT; + break; + } + count--; + } while ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != 0U); + + return status; +} + +/** + * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) +{ + if (hsai->XferCount == 0U) + { + /* Handle the end of the transmission */ + /* Disable FREQ and OVRUDR interrupts */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else + HAL_SAI_TxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + else + { + /* Write data on DR register */ + hsai->Instance->DR = *hsai->pBuffPtr; + hsai->pBuffPtr++; + hsai->XferCount--; + } +} + +/** + * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) +{ + if (hsai->XferCount == 0U) + { + /* Handle the end of the transmission */ + /* Disable FREQ and OVRUDR interrupts */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else + HAL_SAI_TxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + else + { + /* Write data on DR register */ + uint32_t temp; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; + hsai->XferCount--; + } +} + +/** + * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) +{ + if (hsai->XferCount == 0U) + { + /* Handle the end of the transmission */ + /* Disable FREQ and OVRUDR interrupts */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else + HAL_SAI_TxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + else + { + /* Write data on DR register */ + uint32_t temp; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 16); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 24); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; + hsai->XferCount--; + } +} + +/** + * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai) +{ + /* Receive data */ + *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR; + hsai->pBuffPtr++; + hsai->XferCount--; + + /* Check end of the transfer */ + if (hsai->XferCount == 0U) + { + /* Disable TXE and OVRUDR interrupts */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + + /* Clear the SAI Overrun flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); + + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else + HAL_SAI_RxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai) +{ + uint32_t temp; + + /* Receive data */ + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; + hsai->XferCount--; + + /* Check end of the transfer */ + if (hsai->XferCount == 0U) + { + /* Disable TXE and OVRUDR interrupts */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + + /* Clear the SAI Overrun flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); + + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else + HAL_SAI_RxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai) +{ + uint32_t temp; + + /* Receive data */ + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 16); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 24); + hsai->pBuffPtr++; + hsai->XferCount--; + + /* Check end of the transfer */ + if (hsai->XferCount == 0U) + { + /* Disable TXE and OVRUDR interrupts */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + + /* Clear the SAI Overrun flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); + + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else + HAL_SAI_RxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA SAI transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) +{ + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + hsai->XferCount = 0; + + /* Disable SAI Tx DMA Request */ + hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); + + /* Stop the interrupts error handling */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); + + hsai->State = HAL_SAI_STATE_READY; + } + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else + HAL_SAI_TxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SAI transmit process half complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxHalfCpltCallback(hsai); +#else + HAL_SAI_TxHalfCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SAI receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) +{ + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Check if DMA in circular mode*/ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + /* Disable Rx DMA Request */ + hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); + hsai->XferCount = 0; + + /* Stop the interrupts error handling */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); + + hsai->State = HAL_SAI_STATE_READY; + } + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else + HAL_SAI_RxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SAI receive process half complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxHalfCpltCallback(hsai); +#else + HAL_SAI_RxHalfCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SAI communication error callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SAI_DMAError(DMA_HandleTypeDef *hdma) +{ + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Set SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Disable the SAI DMA request */ + hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; + + /* Disable SAI peripheral */ + /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */ + (void) SAI_Disable(hsai); + + /* Set the SAI state ready to be able to start again the process */ + hsai->State = HAL_SAI_STATE_READY; + + /* Initialize XferCount */ + hsai->XferCount = 0U; + + /* SAI error Callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SAI Abort callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SAI_DMAAbort(DMA_HandleTypeDef *hdma) +{ + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable DMA request */ + hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; + + /* Disable all interrupts and clear all flags */ + hsai->Instance->IMR = 0U; + hsai->Instance->CLRFR = 0xFFFFFFFFU; + + if (hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG) + { + /* Disable SAI peripheral */ + /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */ + (void) SAI_Disable(hsai); + + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + } + /* Set the SAI state to ready to be able to start again the process */ + hsai->State = HAL_SAI_STATE_READY; + + /* Initialize XferCount */ + hsai->XferCount = 0U; + + /* SAI error Callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +} + +/** + * @} + */ + +#endif /* HAL_SAI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sai_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sai_ex.c new file mode 100644 index 00000000000..57de5db8b07 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sai_ex.c @@ -0,0 +1,129 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_sai_ex.c + * @author MCD Application Team + * @brief SAI Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionality of the SAI Peripheral Controller: + * + Modify PDM microphone delays. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#ifdef HAL_SAI_MODULE_ENABLED + +/** @defgroup SAIEx SAIEx + * @brief SAI Extended HAL module driver + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SAIEx_Private_Defines SAIEx Extended Private Defines + * @{ + */ +#define SAI_PDM_DELAY_MASK 0x77U +#define SAI_PDM_DELAY_OFFSET 8U +#define SAI_PDM_RIGHT_DELAY_OFFSET 4U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SAIEx_Exported_Functions SAIEx Extended Exported Functions + * @{ + */ + +/** @defgroup SAIEx_Exported_Functions_Group1 Peripheral Control functions + * @brief SAIEx control functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Modify PDM microphone delays + +@endverbatim + * @{ + */ + +/** + * @brief Configure PDM microphone delays. + * @param hsai SAI handle. + * @param pdmMicDelay Microphone delays configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai, + const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t offset; + + /* Check that SAI sub-block is SAI1 sub-block A */ + if (hsai->Instance != SAI1_Block_A) + { + status = HAL_ERROR; + } + else + { + /* Check microphone delay parameters */ + assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(pdmMicDelay->MicPair)); + assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay)); + assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay)); + + /* Compute offset on PDMDLY register according mic pair number */ + offset = SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1U); + + /* Check SAI state and offset */ + if ((hsai->State != HAL_SAI_STATE_RESET) && (offset <= 24U)) + { + /* Reset current delays for specified microphone */ + SAI1->PDMDLY &= ~(SAI_PDM_DELAY_MASK << offset); + + /* Apply new microphone delays */ + SAI1->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << offset); + } + else + { + status = HAL_ERROR; + } + } + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SAI_MODULE_ENABLED */ +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sd.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sd.c new file mode 100644 index 00000000000..61049c8a667 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sd.c @@ -0,0 +1,4070 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_sd.c + * @author MCD Application Team + * @brief SD card HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital (SD) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver implements a high level communication layer for read and write from/to + this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by + the user in HAL_SD_MspInit() function (MSP layer). + Basically, the MSP layer configuration should be the same as we provide in the + examples. + You can easily tailor this configuration according to hardware resources. + + [..] + This driver is a generic layered driver for SDMMC memories which uses the HAL + SDMMC driver functions to interface with SD and uSD cards devices. + It is used as follows: + + (#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API: + (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); + (##) SDMMC pins configuration for SD card + (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() + and according to your pin assignment; + (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT() + and HAL_SD_WriteBlocks_IT() APIs). + (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); + (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() + and __HAL_SD_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT() + and __HAL_SD_CLEAR_IT() + (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used. + + (#) At this stage, you can perform SD read/write/erase operations after SD card initialization + + *** SD Card Initialization and configuration *** + ================================================ + [..] + To initialize the SD Card, use the HAL_SD_Init() function. It Initializes + SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer). + This function provide the following operations: + + (#) Apply the SD Card initialization process at 400KHz and check the SD Card + type (Standard Capacity or High Capacity). You can change or adapt this + frequency by adjusting the "ClockDiv" field. + The SD Card frequency (SDMMC_CK) is computed as follows: + + SDMMC_CK = SDMMCCLK / (2 * ClockDiv) + + In initialization mode and according to the SD Card standard, + make sure that the SDMMC_CK frequency doesn't exceed 400KHz. + + This phase of initialization is done through SDMMC_Init() and + SDMMC_PowerState_ON() SDMMC low level APIs. + + (#) Initialize the SD card. The API used is HAL_SD_InitCard(). + This phase allows the card initialization and identification + and check the SD Card type (Standard Capacity or High Capacity) + The initialization flow is compatible with SD standard. + + This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case + of plug-off plug-in. + + (#) Configure the SD Card Data transfer frequency. You can change or adapt this + frequency by adjusting the "ClockDiv" field. + In transfer mode and according to the SD Card standard, make sure that the + SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch. + + (#) Select the corresponding SD Card according to the address read with the step 2. + + (#) Configure the SD Card in wide bus mode: 4-bits data. + + *** SD Card Read operation *** + ============================== + [..] + (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + + (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the DMA transfer process through the SD Rx interrupt event. + + (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the IT transfer process through the SD Rx interrupt event. + + *** SD Card Write operation *** + =============================== + [..] + (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + + (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the DMA transfer process through the SD Tx interrupt event. + + (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the IT transfer process through the SD Tx interrupt event. + + *** SD card status *** + ====================== + [..] + (+) The SD Status contains status bits that are related to the SD Memory + Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus(). + + *** SD card information *** + =========================== + [..] + (+) To get SD card information, you can use the function HAL_SD_GetCardInfo(). + It returns useful information about the SD card such as block size, card type, + block number ... + + *** SD card CSD register *** + ============================ + (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register. + Some of the CSD parameters are useful for card initialization and identification. + + *** SD card CID register *** + ============================ + (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register. + Some of the CSD parameters are useful for card initialization and identification. + + *** SD HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SD HAL driver. + + (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt + (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt + (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not + (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags + + (@) You can refer to the SD HAL driver header file for more useful macros + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_SD_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed. + (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed. + (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed. + (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed. + (+) MspInitCallback : SD MspInit. + (+) MspDeInitCallback : SD MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + For specific callbacks TransceiverCallback use dedicated register callbacks: + respectively HAL_SD_RegisterTransceiverCallback(). + + Use function HAL_SD_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. It allows to reset following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) Read_DMALnkLstBufCpltCallback : callback when the DMA reception of linked list node buffer is completed. + (+) Write_DMALnkLstBufCpltCallback : callback when the DMA transmission of linked list node buffer is completed. + (+) MspInitCallback : SD MspInit. + (+) MspDeInitCallback : SD MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + For specific callbacks TransceiverCallback use dedicated unregister callbacks: + respectively HAL_SD_UnRegisterTransceiverCallback(). + + By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET + all callbacks are reset to the corresponding legacy weak (overridden) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (overridden) functions in the HAL_SD_Init + and HAL_SD_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SD_RegisterCallback before calling HAL_SD_DeInit + or HAL_SD_Init function. + + When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (overridden) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup SD + * @{ + */ + +#if defined (SDMMC1) || defined (SDMMC2) +#ifdef HAL_SD_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup SD_Private_Defines + * @{ + */ +/* Frequencies used in the driver for clock divider calculation */ +#define SD_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */ +#define SD_NORMAL_SPEED_FREQ 25000000U /* Normal speed phase : 25 MHz max */ +#define SD_HIGH_SPEED_FREQ 50000000U /* High speed phase : 50 MHz max */ +/* Private macro -------------------------------------------------------------*/ +#if defined (DLYB_SDMMC1) && defined (DLYB_SDMMC2) +#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) (((SDMMC_INSTANCE) == SDMMC1)? \ + DLYB_SDMMC1 : DLYB_SDMMC2 ) +#elif defined (DLYB_SDMMC1) +#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) ( DLYB_SDMMC1 ) +#endif /* (DLYB_SDMMC1) && defined (DLYB_SDMMC2) */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SD_Private_Functions SD Private Functions + * @{ + */ +static uint32_t SD_InitCard(SD_HandleTypeDef *hsd); +static uint32_t SD_PowerON(SD_HandleTypeDef *hsd); +static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); +static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); +static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd); +static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd); +static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); +static void SD_PowerOFF(SD_HandleTypeDef *hsd); +static void SD_Write_IT(SD_HandleTypeDef *hsd); +static void SD_Read_IT(SD_HandleTypeDef *hsd); +static uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode); +#if (USE_SD_TRANSCEIVER != 0U) +static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeedMode); +static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd); +#endif /* USE_SD_TRANSCEIVER */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SD_Exported_Functions + * @{ + */ + +/** @addtogroup SD_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize the SD + card device to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SD according to the specified parameters in the + SD_HandleTypeDef and create the associated handle. + * @param hsd: Pointer to the SD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) +{ + HAL_SD_CardStatusTypeDef CardStatus; + uint32_t speedgrade; + uint32_t unitsize; + uint32_t tickstart; + + /* Check the SD handle allocation */ + if (hsd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance)); + assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge)); + assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave)); + assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide)); + assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); + assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv)); + + if (hsd->State == HAL_SD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsd->Lock = HAL_UNLOCKED; + +#if (USE_SD_TRANSCEIVER != 0U) + /* Force SDMMC_TRANSCEIVER_PRESENT for Legacy usage */ + if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_UNKNOWN) + { + hsd->Init.TranceiverPresent = SDMMC_TRANSCEIVER_PRESENT; + } +#endif /*USE_SD_TRANSCEIVER */ +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + /* Reset Callback pointers in HAL_SD_STATE_RESET only */ + hsd->TxCpltCallback = HAL_SD_TxCpltCallback; + hsd->RxCpltCallback = HAL_SD_RxCpltCallback; + hsd->ErrorCallback = HAL_SD_ErrorCallback; + hsd->AbortCpltCallback = HAL_SD_AbortCallback; + hsd->Read_DMALnkLstBufCpltCallback = HAL_SDEx_Read_DMALnkLstBufCpltCallback; + hsd->Write_DMALnkLstBufCpltCallback = HAL_SDEx_Write_DMALnkLstBufCpltCallback; +#if (USE_SD_TRANSCEIVER != 0U) + if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) + { + hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback; + } +#endif /* USE_SD_TRANSCEIVER */ + + if (hsd->MspInitCallback == NULL) + { + hsd->MspInitCallback = HAL_SD_MspInit; + } + + /* Init the low level hardware */ + hsd->MspInitCallback(hsd); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_SD_MspInit(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + + hsd->State = HAL_SD_STATE_PROGRAMMING; + + /* Initialize the Card parameters */ + if (HAL_SD_InitCard(hsd) != HAL_OK) + { + return HAL_ERROR; + } + + if (HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK) + { + return HAL_ERROR; + } + /* Get Initial Card Speed from Card Status*/ + speedgrade = CardStatus.UhsSpeedGrade; + unitsize = CardStatus.UhsAllocationUnitSize; + if ((hsd->SdCard.CardType == CARD_SDHC_SDXC) && ((speedgrade != 0U) || (unitsize != 0U))) + { + hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; + } + else + { + if (hsd->SdCard.CardType == CARD_SDHC_SDXC) + { + hsd->SdCard.CardSpeed = CARD_HIGH_SPEED; + } + else + { + hsd->SdCard.CardSpeed = CARD_NORMAL_SPEED; + } + + } + /* Configure the bus wide */ + if (HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK) + { + return HAL_ERROR; + } + + /* Verify that SD card is ready to use after Initialization */ + tickstart = HAL_GetTick(); + while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Initialize the error code */ + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + /* Initialize the SD operation */ + hsd->Context = SD_CONTEXT_NONE; + + /* Initialize the SD state */ + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the SD Card. + * @param hsd: Pointer to SD handle + * @note This function initializes the SD card. It could be used when a card + re-initialization is needed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) +{ + uint32_t errorstate; + SD_InitTypeDef Init; + uint32_t sdmmc_clk; + + /* Default SDMMC peripheral configuration for SD card initialization */ + Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = SDMMC_BUS_WIDE_1B; + Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + + /* Init Clock should be less or equal to 400Khz*/ + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC12); + if (sdmmc_clk == 0U) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; + return HAL_ERROR; + } + Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ); + +#if (USE_SD_TRANSCEIVER != 0U) + Init.TranceiverPresent = hsd->Init.TranceiverPresent; + + if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) + { + /* Set Transceiver polarity */ + hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; + } +#elif defined (USE_SD_DIRPOL) + /* Set Transceiver polarity */ + hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; +#endif /* USE_SD_TRANSCEIVER */ + + /* Initialize SDMMC peripheral interface with default configuration */ + (void)SDMMC_Init(hsd->Instance, Init); + + /* Set Power State to ON */ + (void)SDMMC_PowerState_ON(hsd->Instance); + + /* wait 74 Cycles: required power up waiting time before starting + the SD initialization sequence */ + if (Init.ClockDiv != 0U) + { + sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); + } + + if (sdmmc_clk != 0U) + { + HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + } + + /* Identify card operating voltage */ + errorstate = SD_PowerON(hsd); + if (errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } + + /* Card initialization */ + errorstate = SD_InitCard(hsd); + if (errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief De-Initializes the SD card. + * @param hsd: Pointer to SD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) +{ + /* Check the SD handle allocation */ + if (hsd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance)); + + hsd->State = HAL_SD_STATE_BUSY; + +#if (USE_SD_TRANSCEIVER != 0U) + /* Deactivate the 1.8V Mode */ + if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + if (hsd->DriveTransceiver_1_8V_Callback == NULL) + { + hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback; + } + hsd->DriveTransceiver_1_8V_Callback(RESET); +#else + HAL_SD_DriveTransceiver_1_8V_Callback(RESET); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } +#endif /* USE_SD_TRANSCEIVER */ + + /* Set SD power state to off */ + SD_PowerOFF(hsd); + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + if (hsd->MspDeInitCallback == NULL) + { + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + } + + /* DeInit the low level hardware */ + hsd->MspDeInitCallback(hsd); +#else + /* De-Initialize the MSP layer */ + HAL_SD_MspDeInit(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initializes the SD MSP. + * @param hsd: Pointer to SD handle + * @retval None + */ +__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-Initialize SD MSP. + * @param hsd: Pointer to SD handle + * @retval None + */ +__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup SD_Exported_Functions_Group2 + * @brief Data transfer functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the data + transfer from/to SD card. + +@endverbatim + * @{ + */ + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @param hsd: Pointer to SD handle + * @param pData: pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of SD blocks to read + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, + uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t data; + uint32_t dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; + + if (NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if (hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= BLOCKSIZE; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); + + /* Read block(s) in polling mode */ + if (NumberOfBlocks > 1U) + { + hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK; + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); + } + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + dataremaining = config.DataLength; + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hsd->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hsd->Instance); + + /* Send stop transmission command in case of multiblock read */ + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + if (hsd->SdCard.CardType != CARD_SECURED) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + } + } + + /* Get error state */ + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to write block(s) to a specified address in a card. The Data + * transfer is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @param hsd: Pointer to SD handle + * @param pData: pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of SD blocks to write + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t data; + uint32_t dataremaining; + uint32_t add = BlockAdd; + const uint8_t *tempbuff = pData; + + if (NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if (hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= BLOCKSIZE; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); + + /* Write Blocks in Polling mode */ + if (NumberOfBlocks > 1U) + { + hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK; + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); + } + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + SDMMC_FLAG_DATAEND)) + { + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*tempbuff); + tempbuff++; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + (void)SDMMC_WriteFIFO(hsd->Instance, &data); + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hsd->Instance); + + /* Send stop transmission command in case of multiblock write */ + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + if (hsd->SdCard.CardType != CARD_SECURED) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + } + } + + /* Get error state */ + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the IT transfer process through the SD Rx + * interrupt event. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if (NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if (hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + hsd->pRxBuffPtr = pData; + hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; + + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= BLOCKSIZE; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); + + /* Read Blocks in IT mode */ + if (NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); + } + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_RXFIFOHF)); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the IT transfer process through the SD Tx + * interrupt event. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if (NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if (hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + hsd->pTxBuffPtr = pData; + hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; + + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= BLOCKSIZE; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); + + /* Write Blocks in Polling mode */ + if (NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_IT); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); + } + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + /* Enable transfer interrupts */ + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_TXFIFOHE)); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the DMA transfer process through the SD Rx + * interrupt event. + * @param hsd: Pointer SD handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if (NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if (hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + hsd->pRxBuffPtr = pData; + hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; + + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= BLOCKSIZE; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); + hsd->Instance->IDMABASER = (uint32_t) pData ; + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + + /* Read Blocks in DMA mode */ + if (NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); + } + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + /* Enable transfer interrupts */ + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the DMA transfer process through the SD Tx + * interrupt event. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if (NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if (hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + hsd->pTxBuffPtr = pData; + hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; + + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= BLOCKSIZE; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); + + hsd->Instance->IDMABASER = (uint32_t) pData ; + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + + /* Write Blocks in Polling mode */ + if (NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); + } + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + /* Enable transfer interrupts */ + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Erases the specified memory area of the given SD card. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @param hsd: Pointer to SD handle + * @param BlockStartAdd: Start Block address + * @param BlockEndAdd: End Block address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd) +{ + uint32_t errorstate; + uint32_t start_add = BlockStartAdd; + uint32_t end_add = BlockEndAdd; + + if (hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if (end_add < start_add) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if (end_add > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Check if the card command class supports erase command */ + if (((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Get start and end block for high capacity cards */ + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + start_add *= BLOCKSIZE; + end_add *= BLOCKSIZE; + } + + /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ + if (hsd->SdCard.CardType != CARD_SECURED) + { + /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ + errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add); + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ + errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add); + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + } + + /* Send CMD38 ERASE */ + errorstate = SDMMC_CmdErase(hsd->Instance, 0UL); + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles SD card interrupt request. + * @param hsd: Pointer to SD handle + * @retval None + */ +void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) +{ + uint32_t errorstate; + uint32_t context = hsd->Context; + + /* Check for SDMMC interrupt flags */ + if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) + { + SD_Read_IT(hsd); + } + + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); + + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | \ + SDMMC_IT_RXFIFOHF); + + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); + __SDMMC_CMDTRANS_DISABLE(hsd->Instance); + + if ((context & SD_CONTEXT_IT) != 0U) + { + if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if (errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->RxCpltCallback(hsd); +#else + HAL_SD_RxCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + else + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->TxCpltCallback(hsd); +#else + HAL_SD_TxCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + else if ((context & SD_CONTEXT_DMA) != 0U) + { + hsd->Instance->DLEN = 0; + hsd->Instance->DCTRL = 0; + hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + /* Stop Transfer for Write Multi blocks or Read Multi blocks */ + if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if (errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->TxCpltCallback(hsd); +#else + HAL_SD_TxCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->RxCpltCallback(hsd); +#else + HAL_SD_RxCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } + } + + else if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) + { + SD_Write_IT(hsd); + } + + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | + SDMMC_FLAG_TXUNDERR) != RESET) + { + /* Set Error code */ + if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + } + if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + } + if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; + } + if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; + } + + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + /* Disable all interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + + __SDMMC_CMDTRANS_DISABLE(hsd->Instance); + hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; + hsd->Instance->CMD |= SDMMC_CMD_CMDSTOP; + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + hsd->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DABORT); + + if ((context & SD_CONTEXT_IT) != 0U) + { + /* Set the SD state to ready to be able to start again the process */ + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + else if ((context & SD_CONTEXT_DMA) != 0U) + { + if (hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + /* Disable Internal DMA */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); + hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + /* Set the SD state to ready to be able to start again the process */ + hsd->State = HAL_SD_STATE_READY; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } + } + + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC); + + if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->Write_DMALnkLstBufCpltCallback(hsd); +#else + HAL_SDEx_Write_DMALnkLstBufCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */ + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->Read_DMALnkLstBufCpltCallback(hsd); +#else + HAL_SDEx_Read_DMALnkLstBufCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief return the SD state + * @param hsd: Pointer to sd handle + * @retval HAL state + */ +HAL_SD_StateTypeDef HAL_SD_GetState(const SD_HandleTypeDef *hsd) +{ + return hsd->State; +} + +/** + * @brief Return the SD error code + * @param hsd : Pointer to a SD_HandleTypeDef structure that contains + * the configuration information. + * @retval SD Error Code + */ +uint32_t HAL_SD_GetError(const SD_HandleTypeDef *hsd) +{ + return hsd->ErrorCode; +} + +/** + * @brief Tx Transfer completed callbacks + * @param hsd: Pointer to SD handle + * @retval None + */ +__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hsd: Pointer SD handle + * @retval None + */ +__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief SD error callbacks + * @param hsd: Pointer SD handle + * @retval None + */ +__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief SD Abort callbacks + * @param hsd: Pointer SD handle + * @retval None + */ +__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_AbortCallback can be implemented in the user file + */ +} + +#if (USE_SD_TRANSCEIVER != 0U) +/** + * @brief Enable/Disable the SD Transceiver 1.8V Mode Callback. + * @param status: Voltage Switch State + * @retval None + */ +__weak void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(status); + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_EnableTransceiver could be implemented in the user file + */ +} +#endif /* USE_SD_TRANSCEIVER */ + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SD Callback + * To be used instead of the weak (overridden) predefined callback + * @note The HAL_SD_RegisterCallback() may be called before HAL_SD_Init() in + * HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID + * and HAL_SD_MSP_DEINIT_CB_ID. + * @param hsd : SD handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID + * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID + * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID + * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID + * @arg @ref HAL_SD_READ_DMA_LNKLST_BUF_CPLT_CB_ID SD DMA Rx Linked List Node buffer Callback ID + * @arg @ref HAL_SD_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID SD DMA Tx Linked List Node buffer Callback ID + * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID + * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, + pSD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hsd->State == HAL_SD_STATE_READY) + { + switch (CallbackID) + { + case HAL_SD_TX_CPLT_CB_ID : + hsd->TxCpltCallback = pCallback; + break; + case HAL_SD_RX_CPLT_CB_ID : + hsd->RxCpltCallback = pCallback; + break; + case HAL_SD_ERROR_CB_ID : + hsd->ErrorCallback = pCallback; + break; + case HAL_SD_ABORT_CB_ID : + hsd->AbortCpltCallback = pCallback; + break; + case HAL_SD_READ_DMA_LNKLST_BUF_CPLT_CB_ID : + hsd->Read_DMALnkLstBufCpltCallback = pCallback; + break; + case HAL_SD_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID : + hsd->Write_DMALnkLstBufCpltCallback = pCallback; + break; + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = pCallback; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsd->State == HAL_SD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = pCallback; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User SD Callback + * SD Callback is redirected to the weak (overridden) predefined callback + * @note The HAL_SD_UnRegisterCallback() may be called before HAL_SD_Init() in + * HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID + * and HAL_SD_MSP_DEINIT_CB_ID. + * @param hsd : SD handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID + * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID + * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID + * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID + * @arg @ref HAL_SD_READ_DMA_LNKLST_BUF_CPLT_CB_ID SD DMA Rx Linked List Node buffer Callback ID + * @arg @ref HAL_SD_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID SD DMA Tx Linked List Node buffer Callback ID + * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID + * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hsd->State == HAL_SD_STATE_READY) + { + switch (CallbackID) + { + case HAL_SD_TX_CPLT_CB_ID : + hsd->TxCpltCallback = HAL_SD_TxCpltCallback; + break; + case HAL_SD_RX_CPLT_CB_ID : + hsd->RxCpltCallback = HAL_SD_RxCpltCallback; + break; + case HAL_SD_ERROR_CB_ID : + hsd->ErrorCallback = HAL_SD_ErrorCallback; + break; + case HAL_SD_ABORT_CB_ID : + hsd->AbortCpltCallback = HAL_SD_AbortCallback; + break; + case HAL_SD_READ_DMA_LNKLST_BUF_CPLT_CB_ID : + hsd->Read_DMALnkLstBufCpltCallback = HAL_SDEx_Read_DMALnkLstBufCpltCallback; + break; + case HAL_SD_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID : + hsd->Write_DMALnkLstBufCpltCallback = HAL_SDEx_Write_DMALnkLstBufCpltCallback; + break; + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = HAL_SD_MspInit; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsd->State == HAL_SD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = HAL_SD_MspInit; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +#if (USE_SD_TRANSCEIVER != 0U) +/** + * @brief Register a User SD Transceiver Callback + * To be used instead of the weak (overridden) predefined callback + * @param hsd : SD handle + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsd); + + if (hsd->State == HAL_SD_STATE_READY) + { + hsd->DriveTransceiver_1_8V_Callback = pCallback; + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsd); + return status; +} + +/** + * @brief Unregister a User SD Transceiver Callback + * SD Callback is redirected to the weak (overridden) predefined callback + * @param hsd : SD handle + * @retval status + */ +HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hsd); + + if (hsd->State == HAL_SD_STATE_READY) + { + hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback; + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsd); + return status; +} +#endif /* USE_SD_TRANSCEIVER */ +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup SD_Exported_Functions_Group3 + * @brief management functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the SD card + operations and get the related information + +@endverbatim + * @{ + */ + +/** + * @brief Returns information the information of the card which are stored on + * the CID register. + * @param hsd: Pointer to SD handle + * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that + * contains all CID register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) +{ + pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); + + pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U); + + pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U)); + + pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU); + + pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U); + + pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U)); + + pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U); + + pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U); + + pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U); + + pCID->Reserved2 = 1U; + + return HAL_OK; +} + +/** + * @brief Returns information the information of the card which are stored on + * the CSD register. + * @param hsd: Pointer to SD handle + * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that + * contains all CSD register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD) +{ + pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U); + + pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U); + + pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U); + + pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U); + + pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U); + + pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU); + + pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U); + + pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U); + + pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U); + + pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U); + + pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U); + + pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U); + + pCSD->Reserved2 = 0U; /*!< Reserved */ + + if (hsd->SdCard.CardType == CARD_SDSC) + { + pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U)); + + pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U); + + pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U); + + pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U); + + pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U); + + pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U); + + hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ; + hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + + hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / BLOCKSIZE); + hsd->SdCard.LogBlockSize = BLOCKSIZE; + } + else if (hsd->SdCard.CardType == CARD_SDHC_SDXC) + { + /* Byte 7 */ + pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U)); + + hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U); + hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; + hsd->SdCard.BlockSize = BLOCKSIZE; + hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; + } + else + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U); + + pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U); + + pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU); + + pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U); + + pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U); + + pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U); + + pCSD->MaxWrBlockLen = (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); + + pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U); + + pCSD->Reserved3 = 0; + + pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U); + + pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U); + + pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U); + + pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U); + + pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U); + + pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U); + + pCSD->ECC = (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); + + pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U); + + pCSD->Reserved4 = 1; + + return HAL_OK; +} + +/** + * @brief Gets the SD status info.( shall be called if there is no SD transaction ongoing ) + * @param hsd: Pointer to SD handle + * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that + * will contain the SD card status information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus) +{ + uint32_t sd_status[16]; + uint32_t errorstate; + HAL_StatusTypeDef status = HAL_OK; + + if (hsd->State == HAL_SD_STATE_BUSY) + { + return HAL_ERROR; + } + + errorstate = SD_SendSDStatus(hsd, sd_status); + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + status = HAL_ERROR; + } + else + { + pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U); + + pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U); + + pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U)); + + pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) | + ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U)); + + pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU); + + pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U); + + pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U); + + pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU)); + + pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U); + + pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U); + + pStatus->UhsSpeedGrade = (uint8_t)((sd_status[3] & 0x00F0U) >> 4U); + pStatus->UhsAllocationUnitSize = (uint8_t)(sd_status[3] & 0x000FU) ; + pStatus->VideoSpeedClass = (uint8_t)((sd_status[4] & 0xFF000000U) >> 24U); + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode = errorstate; + hsd->State = HAL_SD_STATE_READY; + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Gets the SD card info. + * @param hsd: Pointer to SD handle + * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that + * will contain the SD card status information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) +{ + pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); + pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); + pCardInfo->Class = (uint32_t)(hsd->SdCard.Class); + pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd); + pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr); + pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize); + pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr); + pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize); + + return HAL_OK; +} + +/** + * @brief Enables wide bus operation for the requested card if supported by + * card. + * @param hsd: Pointer to SD handle + * @param WideMode: Specifies the SD card wide bus mode + * This parameter can be one of the following values: + * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer + * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer + * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode) +{ + SDMMC_InitTypeDef Init; + uint32_t errorstate; + uint32_t sdmmc_clk; + + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_SDMMC_BUS_WIDE(WideMode)); + + /* Change State */ + hsd->State = HAL_SD_STATE_BUSY; + + if (hsd->SdCard.CardType != CARD_SECURED) + { + if (WideMode == SDMMC_BUS_WIDE_8B) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + else if (WideMode == SDMMC_BUS_WIDE_4B) + { + errorstate = SD_WideBus_Enable(hsd); + + hsd->ErrorCode |= errorstate; + } + else if (WideMode == SDMMC_BUS_WIDE_1B) + { + errorstate = SD_WideBus_Disable(hsd); + + hsd->ErrorCode |= errorstate; + } + else + { + /* WideMode is not a valid argument*/ + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + } + } + else + { + /* SD Card does not support this feature */ + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + if (hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + status = HAL_ERROR; + } + else + { + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC12); + if (sdmmc_clk != 0U) + { + /* Configure the SDMMC peripheral */ + Init.ClockEdge = hsd->Init.ClockEdge; + Init.ClockPowerSave = hsd->Init.ClockPowerSave; + Init.BusWide = WideMode; + Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; + + /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */ + if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ))) + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) + { + /* UltraHigh speed SD card,user Clock div */ + Init.ClockDiv = hsd->Init.ClockDiv; + } + else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) + { + /* High speed SD card, Max Frequency = 50Mhz */ + if (hsd->Init.ClockDiv == 0U) + { + if (sdmmc_clk > SD_HIGH_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + else + { + if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + } + else + { + /* No High speed SD card, Max Frequency = 25Mhz */ + if (hsd->Init.ClockDiv == 0U) + { + if (sdmmc_clk > SD_NORMAL_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + else + { + if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + } + +#if (USE_SD_TRANSCEIVER != 0U) + Init.TranceiverPresent = hsd->Init.TranceiverPresent; +#endif /* USE_SD_TRANSCEIVER */ + + (void)SDMMC_Init(hsd->Instance, Init); + } + else + { + hsd->ErrorCode |= SDMMC_ERROR_INVALID_PARAMETER; + status = HAL_ERROR; + } + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + status = HAL_ERROR; + } + + /* Change State */ + hsd->State = HAL_SD_STATE_READY; + + return status; +} + +/** + * @brief Configure the speed bus mode + * @param hsd: Pointer to the SD handle + * @param SpeedMode: Specifies the SD card speed bus mode + * This parameter can be one of the following values: + * @arg SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card + * @arg SDMMC_SPEED_MODE_DEFAULT: Default Speed/SDR12 mode + * @arg SDMMC_SPEED_MODE_HIGH: High Speed/SDR25 mode + * @arg SDMMC_SPEED_MODE_ULTRA: Ultra high speed mode + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode) +{ + uint32_t tickstart; + uint32_t errorstate; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_SDMMC_SPEED_MODE(SpeedMode)); + /* Change State */ + hsd->State = HAL_SD_STATE_BUSY; + +#if (USE_SD_TRANSCEIVER != 0U) + if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) + { + switch (SpeedMode) + { + case SDMMC_SPEED_MODE_AUTO: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED; + /* Enable Ultra High Speed */ + if (SD_UltraHighSpeed(hsd, SDMMC_SDR104_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + } + else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) + { + /* Enable High Speed */ + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + else + { + /*Nothing to do, Use defaultSpeed */ + } + break; + } + case SDMMC_SPEED_MODE_ULTRA_SDR104: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable UltraHigh Speed */ + if (SD_UltraHighSpeed(hsd, SDMMC_SDR104_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED; + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_ULTRA_SDR50: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable UltraHigh Speed */ + if (SD_UltraHighSpeed(hsd, SDMMC_SDR50_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED; + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_DDR: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable DDR Mode*/ + if (SD_DDR_Mode(hsd) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED | SDMMC_CLKCR_DDR; + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_HIGH: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable High Speed */ + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_DEFAULT: + { + /* Switch to default Speed */ + if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + + break; + } + default: + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + status = HAL_ERROR; + break; + } + } + else + { + switch (SpeedMode) + { + case SDMMC_SPEED_MODE_AUTO: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable High Speed */ + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + else + { + /*Nothing to do, Use defaultSpeed */ + } + break; + } + case SDMMC_SPEED_MODE_HIGH: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable High Speed */ + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_DEFAULT: + { + /* Switch to default Speed */ + if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + + break; + } + case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ + default: + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + status = HAL_ERROR; + break; + } + } +#else + switch (SpeedMode) + { + case SDMMC_SPEED_MODE_AUTO: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable High Speed */ + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + else + { + /*Nothing to do, Use defaultSpeed */ + } + break; + } + case SDMMC_SPEED_MODE_HIGH: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable High Speed */ + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_DEFAULT: + { + /* Switch to default Speed */ + if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + + break; + } + case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ + default: + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + status = HAL_ERROR; + break; + } +#endif /* USE_SD_TRANSCEIVER */ + + /* Verify that SD card is ready to use after Speed mode switch*/ + tickstart = HAL_GetTick(); + while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if (errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + status = HAL_ERROR; + } + + /* Change State */ + hsd->State = HAL_SD_STATE_READY; + return status; +} + +/** + * @brief Gets the current sd card data state. + * @param hsd: pointer to SD handle + * @retval Card state + */ +HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) +{ + uint32_t cardstate; + uint32_t errorstate; + uint32_t resp1 = 0; + + errorstate = SD_SendStatus(hsd, &resp1); + if (errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; + } + + cardstate = ((resp1 >> 9U) & 0x0FU); + + return (HAL_SD_CardStateTypeDef)cardstate; +} + +/** + * @brief Abort the current transfer and disable the SD. + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information for SD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) +{ + uint32_t error_code; + uint32_t tickstart; + + if (hsd->State == HAL_SD_STATE_BUSY) + { + /* DIsable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + __SDMMC_CMDTRANS_DISABLE(hsd->Instance); + + /*we will send the CMD12 in all cases in order to stop the data transfers*/ + /*In case the data transfer just finished , the external memory will not respond + and will return HAL_SD_ERROR_CMD_RSP_TIMEOUT*/ + /*In case the data transfer aborted , the external memory will respond and will return HAL_SD_ERROR_NONE*/ + /*Other scenario will return HAL_ERROR*/ + + hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); + error_code = hsd->ErrorCode; + if ((error_code != HAL_SD_ERROR_NONE) && (error_code != HAL_SD_ERROR_CMD_RSP_TIMEOUT)) + { + return HAL_ERROR; + } + + tickstart = HAL_GetTick(); + if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_CARD) + { + if (hsd->ErrorCode == HAL_SD_ERROR_NONE) + { + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + } + + if (hsd->ErrorCode == HAL_SD_ERROR_CMD_RSP_TIMEOUT) + { + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + } + } + else if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC) + { + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + } + else + { + /* Nothing to do*/ + } + + /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear + the appropriate flags that will be set depending of the abort/non abort of the memory */ + /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared + and will result in next SDMMC read/write operation to fail */ + + /*SDMMC ready for clear data flags*/ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_BUSYD0END); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + /* If IDMA Context, disable Internal DMA */ + hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + hsd->State = HAL_SD_STATE_READY; + + /* Initialize the SD operation */ + hsd->Context = SD_CONTEXT_NONE; + } + return HAL_OK; +} + +/** + * @brief Abort the current transfer and disable the SD (IT mode). + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information for SD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) +{ + HAL_SD_CardStateTypeDef CardState; + + /* Disable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + + /* If IDMA Context, disable Internal DMA */ + hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + + if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); + } + + if (hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + return HAL_ERROR; + } + else + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->AbortCpltCallback(hsd); +#else + HAL_SD_AbortCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup SD_Private_Functions + * @{ + */ + +/** + * @brief Initializes the sd card. + * @param hsd: Pointer to SD handle + * @retval SD Card error state + */ +static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) +{ + HAL_SD_CardCSDTypeDef CSD; + uint32_t errorstate; + uint16_t sd_rca = 0U; + uint32_t tickstart = HAL_GetTick(); + + /* Check the power State */ + if (SDMMC_GetPowerState(hsd->Instance) == 0U) + { + /* Power off */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } + + if (hsd->SdCard.CardType != CARD_SECURED) + { + /* Send CMD2 ALL_SEND_CID */ + errorstate = SDMMC_CmdSendCID(hsd->Instance); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card identification number data */ + hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + } + } + + if (hsd->SdCard.CardType != CARD_SECURED) + { + /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* SD Card publishes its RCA. */ + while (sd_rca == 0U) + { + errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + if ((HAL_GetTick() - tickstart) >= SDMMC_CMDTIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } + } + if (hsd->SdCard.CardType != CARD_SECURED) + { + /* Get the SD card RCA */ + hsd->SdCard.RelCardAdd = sd_rca; + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card Specific Data */ + hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + } + } + + /* Get the Card Class */ + hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U); + + /* Get CSD parameters */ + if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + /* Select the Card */ + errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U)); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* All cards are initialized */ + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Enquires cards about their operating voltage and configures clock + * controls and stores SD information that will be needed in future + * in the SD handle. + * @param hsd: Pointer to SD handle + * @retval error state + */ +static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) +{ + __IO uint32_t count = 0U; + uint32_t response = 0U; + uint32_t validvoltage = 0U; + uint32_t errorstate; +#if (USE_SD_TRANSCEIVER != 0U) + uint32_t tickstart = HAL_GetTick(); +#endif /* USE_SD_TRANSCEIVER */ + + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hsd->Instance); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ + errorstate = SDMMC_CmdOperCond(hsd->Instance); + if (errorstate == SDMMC_ERROR_TIMEOUT) /* No response to CMD8 */ + { + hsd->SdCard.CardVersion = CARD_V1_X; + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hsd->Instance); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + } + else + { + hsd->SdCard.CardVersion = CARD_V2_X; + } + + if (hsd->SdCard.CardVersion == CARD_V2_X) + { + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if (errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + } + /* SD CARD */ + /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while ((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) + { + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send CMD41 */ + errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | + SD_SWITCH_1_8V_CAPACITY); + if (errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + /* Get command response */ + response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); + + count++; + } + + if (count >= SDMMC_MAX_VOLT_TRIAL) + { + return HAL_SD_ERROR_INVALID_VOLTRANGE; + } + + /* Set default card type */ + hsd->SdCard.CardType = CARD_SDSC; + + if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) + { + hsd->SdCard.CardType = CARD_SDHC_SDXC; +#if (USE_SD_TRANSCEIVER != 0U) + if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) + { + if ((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY) + { + hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; + + /* Start switching procedue */ + hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN; + + /* Send CMD11 to switch 1.8V mode */ + errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Check to CKSTOP */ + while ((hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } + + /* Clear CKSTOP Flag */ + hsd->Instance->ICR = SDMMC_FLAG_CKSTOP; + + /* Check to BusyD0 */ + if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0) + { + /* Error when activate Voltage Switch in SDMMC Peripheral */ + return SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* Enable Transceiver Switch PIN */ +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->DriveTransceiver_1_8V_Callback(SET); +#else + HAL_SD_DriveTransceiver_1_8V_Callback(SET); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + + /* Switch ready */ + hsd->Instance->POWER |= SDMMC_POWER_VSWITCH; + + /* Check VSWEND Flag */ + while ((hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } + + /* Clear VSWEND Flag */ + hsd->Instance->ICR = SDMMC_FLAG_VSWEND; + + /* Check BusyD0 status */ + if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0) + { + /* Error when enabling 1.8V mode */ + return HAL_SD_ERROR_INVALID_VOLTRANGE; + } + /* Switch to 1.8V OK */ + + /* Disable VSWITCH FLAG from SDMMC Peripheral */ + hsd->Instance->POWER = 0x13U; + + /* Clean Status flags */ + hsd->Instance->ICR = 0xFFFFFFFFU; + } + } + } +#endif /* USE_SD_TRANSCEIVER */ + } + + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Turns the SDMMC output signals off. + * @param hsd: Pointer to SD handle + * @retval None + */ +static void SD_PowerOFF(SD_HandleTypeDef *hsd) +{ + /* Set Power State to OFF */ + (void)SDMMC_PowerState_OFF(hsd->Instance); +} + +/** + * @brief Send Status info command. + * @param hsd: pointer to SD handle + * @param pSDstatus: Pointer to the buffer that will contain the SD card status + * SD Status register) + * @retval error state + */ +static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t *pData = pSDstatus; + + /* Check SD response */ + if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + } + + /* Set block size for card if it is not equal to current block size for card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); + if (errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_NONE; + return errorstate; + } + + /* Send CMD55 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if (errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_NONE; + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 64U; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ + errorstate = SDMMC_CmdStatusRegister(hsd->Instance); + if (errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_NONE; + return errorstate; + } + + /* Get status data */ + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + { + for (count = 0U; count < 8U; count++) + { + *pData = SDMMC_ReadFIFO(hsd->Instance); + pData++; + } + } + + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } + + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + return HAL_SD_ERROR_DATA_TIMEOUT; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + return HAL_SD_ERROR_DATA_CRC_FAIL; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + { + return HAL_SD_ERROR_RX_OVERRUN; + } + else + { + /* Nothing to do */ + } + + while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT))) + { + *pData = SDMMC_ReadFIFO(hsd->Instance); + pData++; + + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } + + /* Clear all the static status flags*/ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Returns the current card's status. + * @param hsd: Pointer to SD handle + * @param pCardStatus: pointer to the buffer that will contain the SD card + * status (Card Status register) + * @retval error state + */ +static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) +{ + uint32_t errorstate; + + if (pCardStatus == NULL) + { + return HAL_SD_ERROR_PARAM; + } + + /* Send Status command */ + errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Get SD card status */ + *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Enables the SDMMC wide bus mode. + * @param hsd: pointer to SD handle + * @retval error state + */ +static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) +{ + uint32_t scr[2U] = {0UL, 0UL}; + uint32_t errorstate; + + if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + } + + /* Get SCR Register */ + errorstate = SD_FindSCR(hsd, scr); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* If requested card supports wide bus operation */ + if ((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) + { + /* Send CMD55 APP_CMD with argument as card's RCA.*/ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + return HAL_SD_ERROR_NONE; + } + else + { + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } +} + +/** + * @brief Disables the SDMMC wide bus mode. + * @param hsd: Pointer to SD handle + * @retval error state + */ +static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) +{ + uint32_t scr[2U] = {0UL, 0UL}; + uint32_t errorstate; + + if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + } + + /* Get SCR Register */ + errorstate = SD_FindSCR(hsd, scr); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* If requested card supports 1 bit mode operation */ + if ((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) + { + /* Send CMD55 APP_CMD with argument as card's RCA */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + return HAL_SD_ERROR_NONE; + } + else + { + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } +} + +/** + * @brief Finds the SD card SCR register value. + * @param hsd: Pointer to SD handle + * @param pSCR: pointer to the buffer that will contain the SCR value + * @retval error state + */ +static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t index = 0U; + uint32_t tempscr[2U] = {0UL, 0UL}; + uint32_t *scr = pSCR; + + /* Set Block Size To 8 Bytes */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send CMD55 APP_CMD with argument as card's RCA */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U)); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 8U; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ + errorstate = SDMMC_CmdSendSCR(hsd->Instance); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | + SDMMC_FLAG_DATAEND)) + { + if ((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U)) + { + tempscr[0] = SDMMC_ReadFIFO(hsd->Instance); + tempscr[1] = SDMMC_ReadFIFO(hsd->Instance); + index++; + } + + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } + + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); + + return HAL_SD_ERROR_DATA_TIMEOUT; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); + + return HAL_SD_ERROR_DATA_CRC_FAIL; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); + + return HAL_SD_ERROR_RX_OVERRUN; + } + else + { + /* No error flag set */ + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24U) | ((tempscr[1] & SDMMC_8TO15BITS) << 8U) | \ + ((tempscr[1] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24U)); + scr++; + *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24U) | ((tempscr[0] & SDMMC_8TO15BITS) << 8U) | \ + ((tempscr[0] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24U)); + + } + + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Wrap up reading in non-blocking mode. + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void SD_Read_IT(SD_HandleTypeDef *hsd) +{ + uint32_t count; + uint32_t data; + uint8_t *tmp; + + tmp = hsd->pRxBuffPtr; + + if (hsd->RxXferSize >= SDMMC_FIFO_SIZE) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hsd->Instance); + *tmp = (uint8_t)(data & 0xFFU); + tmp++; + *tmp = (uint8_t)((data >> 8U) & 0xFFU); + tmp++; + *tmp = (uint8_t)((data >> 16U) & 0xFFU); + tmp++; + *tmp = (uint8_t)((data >> 24U) & 0xFFU); + tmp++; + } + + hsd->pRxBuffPtr = tmp; + hsd->RxXferSize -= SDMMC_FIFO_SIZE; + } +} + +/** + * @brief Wrap up writing in non-blocking mode. + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void SD_Write_IT(SD_HandleTypeDef *hsd) +{ + uint32_t count; + uint32_t data; + const uint8_t *tmp; + + tmp = hsd->pTxBuffPtr; + + if (hsd->TxXferSize >= SDMMC_FIFO_SIZE) + { + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*tmp); + tmp++; + data |= ((uint32_t)(*tmp) << 8U); + tmp++; + data |= ((uint32_t)(*tmp) << 16U); + tmp++; + data |= ((uint32_t)(*tmp) << 24U); + tmp++; + (void)SDMMC_WriteFIFO(hsd->Instance, &data); + } + + hsd->pTxBuffPtr = tmp; + hsd->TxXferSize -= SDMMC_FIFO_SIZE; + } +} + +/** + * @brief Switches the SD card to High Speed mode. + * This API must be used after "Transfer State" + * @note This operation should be followed by the configuration + * of PLL to have SDMMCCK clock between 25 and 50 MHz + * @param hsd: SD handle + * @param SwitchSpeedMode: SD speed mode( SDMMC_SDR12_SWITCH_PATTERN, SDMMC_SDR25_SWITCH_PATTERN) + * @retval SD Card error state + */ +uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode) +{ + uint32_t errorstate = HAL_SD_ERROR_NONE; + SDMMC_DataInitTypeDef sdmmc_datainitstructure; + uint32_t SD_hs[16] = {0}; + uint32_t count; + uint32_t loop = 0 ; + uint32_t Timeout = HAL_GetTick(); + + if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) + { + /* Standard Speed Card <= 12.5Mhz */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } + + if (hsd->SdCard.CardSpeed >= CARD_HIGH_SPEED) + { + /* Initialize the Data control register */ + hsd->Instance->DCTRL = 0; + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); + + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT; + sdmmc_datainitstructure.DataLength = 64U; + sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ; + sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; + + (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); + + errorstate = SDMMC_CmdSwitch(hsd->Instance, SwitchSpeedMode); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | + SDMMC_FLAG_DATAEND)) + { + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + { + for (count = 0U; count < 8U; count++) + { + SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance); + } + loop ++; + } + if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_SD_ERROR_TIMEOUT; + } + } + + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); + + errorstate = SDMMC_ERROR_DATA_CRC_FAIL; + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); + + errorstate = SDMMC_ERROR_RX_OVERRUN; + + return errorstate; + } + else + { + /* No error flag set */ + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + /* Test if the switch mode HS is ok */ + if ((((uint8_t *)SD_hs)[13] & 2U) != 2U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + + } + + return errorstate; +} + +#if (USE_SD_TRANSCEIVER != 0U) +/** + * @brief Switches the SD card to Ultra High Speed mode. + * This API must be used after "Transfer State" + * @note This operation should be followed by the configuration + * of PLL to have SDMMCCK clock between 50 and 120 MHz + * @param hsd: SD handle + * @param UltraHighSpeedMode: SD speed mode( SDMMC_SDR50_SWITCH_PATTERN, SDMMC_SDR104_SWITCH_PATTERN) + * @retval SD Card error state + */ +static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeedMode) +{ + uint32_t errorstate = HAL_SD_ERROR_NONE; + SDMMC_DataInitTypeDef sdmmc_datainitstructure; + uint32_t SD_hs[16] = {0}; + uint32_t count; + uint32_t loop = 0 ; + uint32_t Timeout = HAL_GetTick(); + + if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) + { + /* Standard Speed Card <= 12.5Mhz */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } + + if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) + { + /* Initialize the Data control register */ + hsd->Instance->DCTRL = 0; + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); + + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT; + sdmmc_datainitstructure.DataLength = 64U; + sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ; + sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; + + if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK) + { + return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); + } + + errorstate = SDMMC_CmdSwitch(hsd->Instance, UltraHighSpeedMode); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | + SDMMC_FLAG_DATAEND)) + { + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + { + for (count = 0U; count < 8U; count++) + { + SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance); + } + loop ++; + } + + if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_SD_ERROR_TIMEOUT; + } + } + + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); + + errorstate = SDMMC_ERROR_DATA_CRC_FAIL; + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); + + errorstate = SDMMC_ERROR_RX_OVERRUN; + + return errorstate; + } + else + { + /* No error flag set */ + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + /* Test if the switch mode HS is ok */ + if ((((uint8_t *)SD_hs)[13] & 2U) != 2U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->DriveTransceiver_1_8V_Callback(SET); +#else + HAL_SD_DriveTransceiver_1_8V_Callback(SET); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) + /* Enable DelayBlock Peripheral */ + /* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */ + MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_1); + LL_DLYB_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)); +#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */ + } + } + + return errorstate; +} + +/** + * @brief Switches the SD card to Double Data Rate (DDR) mode. + * This API must be used after "Transfer State" + * @note This operation should be followed by the configuration + * of PLL to have SDMMCCK clock less than 50MHz + * @param hsd: SD handle + * @retval SD Card error state + */ +static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) +{ + uint32_t errorstate = HAL_SD_ERROR_NONE; + SDMMC_DataInitTypeDef sdmmc_datainitstructure; + uint32_t SD_hs[16] = {0}; + uint32_t count; + uint32_t loop = 0 ; + uint32_t Timeout = HAL_GetTick(); + + if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) + { + /* Standard Speed Card <= 12.5Mhz */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } + + if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) + { + /* Initialize the Data control register */ + hsd->Instance->DCTRL = 0; + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); + + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT; + sdmmc_datainitstructure.DataLength = 64U; + sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ; + sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; + + if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK) + { + return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); + } + + errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_DDR50_SWITCH_PATTERN); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | + SDMMC_FLAG_DATAEND)) + { + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + { + for (count = 0U; count < 8U; count++) + { + SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance); + } + loop ++; + } + + if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_SD_ERROR_TIMEOUT; + } + } + + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); + + errorstate = SDMMC_ERROR_DATA_CRC_FAIL; + + return errorstate; + } + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); + + errorstate = SDMMC_ERROR_RX_OVERRUN; + + return errorstate; + } + else + { + /* No error flag set */ + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + /* Test if the switch mode is ok */ + if ((((uint8_t *)SD_hs)[13] & 2U) != 2U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->DriveTransceiver_1_8V_Callback(SET); +#else + HAL_SD_DriveTransceiver_1_8V_Callback(SET); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) + /* Enable DelayBlock Peripheral */ + /* SDMMC_CKin feedback clock selected as receive clock, for DDR50 */ + MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_0); + LL_DLYB_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)); +#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */ + } + } + + return errorstate; +} + +#endif /* USE_SD_TRANSCEIVER */ + +/** + * @brief Read DMA Linked list node Transfer completed callbacks + * @param hsd: SD handle + * @retval None + */ +__weak void HAL_SDEx_Read_DMALnkLstBufCpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDEx_Read_DMALnkLstBufCpltCallback can be implemented in the user file + */ +} +/** + * @brief Read DMA Linked list node Transfer completed callbacks + * @param hsd: SD handle + * @retval None + */ +__weak void HAL_SDEx_Write_DMALnkLstBufCpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDEx_Write_DMALnkLstBufCpltCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +#endif /* HAL_SD_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sd_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sd_ex.c new file mode 100644 index 00000000000..c788096e63a --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sd_ex.c @@ -0,0 +1,393 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_sd_ex.c + * @author MCD Application Team + * @brief SD card Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital (SD) peripheral: + * + Extended features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SD Extension HAL driver can be used as follows: + (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function. + (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() + and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup SDEx SDEx + * @brief SD Extended HAL module driver + * @{ + */ + +#if defined (SDMMC1) || defined (SDMMC2) +#ifdef HAL_SD_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SDEx_Exported_Functions + * @{ + */ + + +/** @addtogroup SDEx_Exported_Functions_Group1 + * @brief Linked List management functions + * +@verbatim + =============================================================================== + ##### Linked List management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the needed functions. + +@endverbatim + * @{ + */ + +/** + * @brief Build Linked List node. + * @param pNode: Pointer to new node to add. + * @param pNodeConf: Pointer to configuration parameters for new node to add. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_BuildNode(SD_DMALinkNodeTypeDef *pNode, SD_DMALinkNodeConfTypeDef *pNodeConf) +{ + + (void)SDMMC_DMALinkedList_BuildNode(pNode, pNodeConf); + + return (HAL_OK); + +} + +/** + * @brief Insert new Linked List node. + * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes + * @param pPrevNode: Pointer to previous node. + * @param pNewNode: Pointer to new node to insert. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_InsertNode(SD_DMALinkedListTypeDef *pLinkedList, + SD_DMALinkNodeTypeDef *pPrevNode, SD_DMALinkNodeTypeDef *pNewNode) +{ + + (void)SDMMC_DMALinkedList_InsertNode(pLinkedList, pPrevNode, pNewNode); + + return (HAL_OK); + +} +/** + * @brief Remove Linked List node. + * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes + * @param pNode: Pointer to node to remove. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_RemoveNode(SD_DMALinkedListTypeDef *pLinkedList, SD_DMALinkNodeTypeDef *pNode) +{ + + if (SDMMC_DMALinkedList_RemoveNode(pLinkedList, pNode) != SDMMC_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Lock Linked List node. + * @param pNode: Pointer to node to remove. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_LockNode(SD_DMALinkNodeTypeDef *pNode) +{ + + if (SDMMC_DMALinkedList_LockNode(pNode) != SDMMC_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Unlock Linked List node. + * @param pNode: Pointer to node to remove. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_UnlockNode(SD_DMALinkNodeTypeDef *pNode) +{ + + if (SDMMC_DMALinkedList_UnlockNode(pNode) != SDMMC_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Enable Circular mode for DMA Linked List. + * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_EnableCircularMode(SD_DMALinkedListTypeDef *pLinkedList) +{ + + (void)SDMMC_DMALinkedList_EnableCircularMode(pLinkedList); + + return HAL_OK; + +} +/** + * @brief Disable Circular mode for DMA Linked List. + * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_DisableCircularMode(SD_DMALinkedListTypeDef *pLinkedList) +{ + + (void)SDMMC_DMALinkedList_DisableCircularMode(pLinkedList); + + return HAL_OK; + +} + + +/** + * @brief Reads block(s) from a specified address in a card. The received Data will be stored in linked list buffers. + * linked list should be prepared before call this function . + * @param hsd: SD handle + * @param pLinkedList: pointer to first linked list node + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Total number of blocks to read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SDMMC_DMALinkedListTypeDef *pLinkedList, + uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t DmaBase0_reg; + uint32_t DmaBase1_reg; + uint32_t add = BlockAdd; + + if (hsd->State == HAL_SD_STATE_READY) + { + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->Instance->IDMABASER = (uint32_t) pLinkedList->pHeadNode->IDMABASER; + hsd->Instance->IDMABSIZE = (uint32_t) pLinkedList->pHeadNode->IDMABSIZE; + + hsd->Instance->IDMABAR = (uint32_t) pLinkedList->pHeadNode; + hsd->Instance->IDMALAR = (uint32_t) SDMMC_IDMALAR_ABR | SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ULA | + sizeof(SDMMC_DMALinkNodeTypeDef) ; /* Initial configuration */ + + DmaBase0_reg = hsd->Instance->IDMABASER; + DmaBase1_reg = hsd->Instance->IDMABAR; + + if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U)) + { + hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0; + /* Clear old Flags*/ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_BUSY; + + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; + + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); + + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; + + /* Read Blocks in DMA mode */ + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); + if (errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } + + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | + SDMMC_IT_IDMABTC)); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + +} + +/** + * @brief Write block(s) to a specified address in a card. The transferred Data are stored linked list nodes buffers . + * linked list should be prepared before call this function . + * @param hsd: SD handle + * @param pLinkedList: pointer to first linked list node + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Total number of blocks to read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, SDMMC_DMALinkedListTypeDef *pLinkedList, + uint32_t BlockAdd, uint32_t NumberOfBlocks) + +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t DmaBase0_reg; + uint32_t DmaBase1_reg; + uint32_t add = BlockAdd; + + if (hsd->State == HAL_SD_STATE_READY) + { + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->Instance->IDMABASER = (uint32_t) pLinkedList->pHeadNode->IDMABASER; + hsd->Instance->IDMABSIZE = (uint32_t) pLinkedList->pHeadNode->IDMABSIZE; + + hsd->Instance->IDMABAR = (uint32_t) pLinkedList->pHeadNode; + hsd->Instance->IDMALAR = (uint32_t) SDMMC_IDMALAR_ABR | SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ULA | + sizeof(SDMMC_DMALinkNodeTypeDef) ; /* Initial configuration */ + + DmaBase0_reg = hsd->Instance->IDMABASER; + DmaBase1_reg = hsd->Instance->IDMABAR; + + if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U)) + { + hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0; + + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + hsd->State = HAL_SD_STATE_BUSY; + + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); + + hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; + + /* Write Blocks in DMA mode */ + hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); + if (errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } + + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | + SDMMC_IT_IDMABTC)); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SD_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sdram.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sdram.c new file mode 100644 index 00000000000..6617b9a0f93 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sdram.c @@ -0,0 +1,1429 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_sdram.c + * @author MCD Application Team + * @brief SDRAM HAL module driver. + * This file provides a generic firmware to drive SDRAM memories mounted + * as external device. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a generic layered driver which contains a set of APIs used to + control SDRAM memories. It uses the FMC layer functions to interface + with SDRAM devices. + The following sequence should be followed to configure the FMC to interface + with SDRAM memories: + + (#) Declare a SDRAM_HandleTypeDef handle structure, for example: + SDRAM_HandleTypeDef hsdram + + (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed + values of the structure member. + + (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined + base register instance for NOR or SDRAM device + + (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: + FMC_SDRAM_TimingTypeDef Timing; + and fill its fields with the allowed values of the structure member. + + (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function + performs the following sequence: + + (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() + (##) Control register configuration using the FMC SDRAM interface function + FMC_SDRAM_Init() + (##) Timing register configuration using the FMC SDRAM interface function + FMC_SDRAM_Timing_Init() + (##) Program the SDRAM external device by applying its initialization sequence + according to the device plugged in your hardware. This step is mandatory + for accessing the SDRAM device. + + (#) At this stage you can perform read/write accesses from/to the memory connected + to the SDRAM Bank. You can perform either polling or DMA transfer using the + following APIs: + (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access + (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer + + (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ + HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or + the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM + device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef + structure. + + (#) You can continuously monitor the SDRAM device HAL state by calling the function + HAL_SDRAM_GetState() + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_SDRAM_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) MspInitCallback : SDRAM MspInit. + (+) MspDeInitCallback : SDRAM MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. It allows to reset following callbacks: + (+) MspInitCallback : SDRAM MspInit. + (+) MspDeInitCallback : SDRAM MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET + all callbacks are reset to the corresponding legacy weak (overridden) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init + and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit + or HAL_SDRAM_Init function. + + When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (overridden) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + +/** @defgroup SDRAM SDRAM + * @brief SDRAM driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions + * @{ + */ +static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma); +static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma); +static void SDRAM_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions + * @{ + */ + +/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### SDRAM Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize + the SDRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Performs the SDRAM device initialization sequence. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param Timing Pointer to SDRAM control timing structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) +{ + /* Check the SDRAM handle parameter */ + if (hsdram == NULL) + { + return HAL_ERROR; + } + + if (hsdram->State == HAL_SDRAM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsdram->Lock = HAL_UNLOCKED; +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + if (hsdram->MspInitCallback == NULL) + { + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + } + hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; + hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + + /* Init the low level hardware */ + hsdram->MspInitCallback(hsdram); +#else + /* Initialize the low level hardware (MSP) */ + HAL_SDRAM_MspInit(hsdram); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ + } + + /* Initialize the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Initialize SDRAM control Interface */ + (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); + + /* Initialize SDRAM timing Interface */ + (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); + + /* Enable FMC Peripheral */ + __FMC_ENABLE(); + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Perform the SDRAM device initialization sequence. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) +{ +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + if (hsdram->MspDeInitCallback == NULL) + { + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + } + + /* DeInit the low level hardware */ + hsdram->MspDeInitCallback(hsdram); +#else + /* Initialize the low level hardware (MSP) */ + HAL_SDRAM_MspDeInit(hsdram); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ + + /* Configure the SDRAM registers with their reset values */ + (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); + + /* Reset the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief SDRAM MSP Init. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval None + */ +__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdram); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_MspInit could be implemented in the user file + */ +} + +/** + * @brief SDRAM MSP DeInit. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval None + */ +__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdram); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function handles SDRAM refresh error interrupt request. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) +{ + /* Check SDRAM interrupt Rising edge flag */ + if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) + { + /* SDRAM refresh error interrupt callback */ +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->RefreshErrorCallback(hsdram); +#else + HAL_SDRAM_RefreshErrorCallback(hsdram); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ + + /* Clear SDRAM refresh error interrupt pending bit */ + __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); + } +} + +/** + * @brief SDRAM Refresh error callback. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval None + */ +__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdram); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete error callback. + * @param hdma DMA handle + * @retval None + */ +__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions + * + @verbatim + ============================================================================== + ##### SDRAM Input and Output functions ##### + ============================================================================== + [..] + This section provides functions allowing to use and control the SDRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Reads 8-bit data buffer from the SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; + uint8_t *pdestbuff = pDstBuffer; + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Read data from source */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *(__IO uint8_t *)pSdramAddress; + pdestbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = state; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 8-bit data buffer to SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; + uint8_t *psrcbuff = pSrcBuffer; + + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *(__IO uint8_t *)pSdramAddress = *psrcbuff; + psrcbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads 16-bit data buffer from the SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *pSdramAddress = pAddress; + uint16_t *pdestbuff = pDstBuffer; + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Read data from memory */ + for (size = BufferSize; size >= 2U ; size -= 2U) + { + *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); + pdestbuff++; + *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U); + pdestbuff++; + pSdramAddress++; + } + + /* Read last 16-bits if size is not 32-bits multiple */ + if ((BufferSize % 2U) != 0U) + { + *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); + } + + /* Update the SDRAM controller state */ + hsdram->State = state; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 16-bit data buffer to SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *psdramaddress = pAddress; + uint16_t *psrcbuff = pSrcBuffer; + + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size >= 2U ; size -= 2U) + { + *psdramaddress = (uint32_t)(*psrcbuff); + psrcbuff++; + *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U); + psrcbuff++; + psdramaddress++; + } + + /* Write last 16-bits if size is not 32-bits multiple */ + if ((BufferSize % 2U) != 0U) + { + *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U); + } + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads 32-bit data buffer from the SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; + uint32_t *pdestbuff = pDstBuffer; + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Read data from source */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *(__IO uint32_t *)pSdramAddress; + pdestbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = state; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 32-bit data buffer to SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *pSdramAddress = pAddress; + uint32_t *psrcbuff = pSrcBuffer; + + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *pSdramAddress = *psrcbuff; + psrcbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads a Words data from the SDRAM memory using DMA transfer. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) +{ + HAL_StatusTypeDef status; + HAL_SDRAM_StateTypeDef state = hsdram->State; + uint32_t size; + uint32_t data_width; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + status = HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + if (state == HAL_SDRAM_STATE_READY) + { + hsdram->hdma->XferCpltCallback = SDRAM_DMACplt; + } + else + { + hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt; + } + hsdram->hdma->XferErrorCallback = SDRAM_DMAError; + + if ((hsdram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hsdram->hdma->LinkedListQueue != 0U) && (hsdram->hdma->LinkedListQueue->Head != 0U)) + { + /* Check destination data width and set the size to be transferred */ + data_width = hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; + + if (data_width == DMA_DEST_DATAWIDTH_WORD) + { + size = (BufferSize * 4U); + } + else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) + { + size = (BufferSize * 2U); + } + else + { + size = (BufferSize); + } + /* Set Source , destination , buffer size */ + /* Set DMA data size */ + hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size; + /* Set DMA source address */ + hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pAddress; + /* Set DMA destination address */ + hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pDstBuffer; + + /* Enable the DMA Stream */ + status = HAL_DMAEx_List_Start_IT(hsdram->hdma); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + status = HAL_ERROR; + } + } + else + { + /* Check destination data width and set the size to be transferred */ + data_width = hsdram->hdma->Init.DestDataWidth; + + if (data_width == DMA_DEST_DATAWIDTH_WORD) + { + size = (BufferSize * 4U); + } + else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) + { + size = (BufferSize * 2U); + } + else + { + size = (BufferSize); + } + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, size); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) +{ + HAL_StatusTypeDef status; + uint32_t size; + uint32_t data_width; + + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + status = HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + hsdram->hdma->XferCpltCallback = SDRAM_DMACplt; + hsdram->hdma->XferErrorCallback = SDRAM_DMAError; + + if ((hsdram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hsdram->hdma->LinkedListQueue != 0U) && (hsdram->hdma->LinkedListQueue->Head != 0U)) + { + /* Check destination data width and set the size to be transferred */ + data_width = hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; + + if (data_width == DMA_DEST_DATAWIDTH_WORD) + { + size = (BufferSize * 4U); + } + else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) + { + size = (BufferSize * 2U); + } + else + { + size = (BufferSize); + } + /* Set Source , destination , buffer size */ + /* Set DMA data size */ + hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size; + /* Set DMA source address */ + hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pSrcBuffer; + /* Set DMA destination address */ + hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pAddress; + + /* Enable the DMA Stream */ + status = HAL_DMAEx_List_Start_IT(hsdram->hdma); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + status = HAL_ERROR; + } + } + else + { + /* Check destination data width and set the size to be transferred */ + data_width = hsdram->hdma->Init.DestDataWidth; + + if (data_width == DMA_DEST_DATAWIDTH_WORD) + { + size = (BufferSize * 4U); + } + else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) + { + size = (BufferSize * 2U); + } + else + { + size = (BufferSize); + } + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, size); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + status = HAL_ERROR; + } + + return status; +} + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SDRAM Callback + * To be used to override the weak predefined callback + * @param hsdram : SDRAM handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID + * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID + * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SDRAM_StateTypeDef state; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + state = hsdram->State; + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = pCallback; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = pCallback; + break; + case HAL_SDRAM_REFRESH_ERR_CB_ID : + hsdram->RefreshErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsdram->State == HAL_SDRAM_STATE_RESET) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = pCallback; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User SDRAM Callback + * SDRAM Callback is redirected to the weak predefined callback + * @param hsdram : SDRAM handle + * @param CallbackId : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID + * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID + * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID + * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SDRAM_StateTypeDef state; + + state = hsdram->State; + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + break; + case HAL_SDRAM_REFRESH_ERR_CB_ID : + hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; + break; + case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : + hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + break; + case HAL_SDRAM_DMA_XFER_ERR_CB_ID : + hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsdram->State == HAL_SDRAM_STATE_RESET) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register a User SDRAM Callback for DMA transfers + * To be used to override the weak predefined callback + * @param hsdram : SDRAM handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_DmaCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SDRAM_StateTypeDef state; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsdram); + + state = hsdram->State; + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : + hsdram->DmaXferCpltCallback = pCallback; + break; + case HAL_SDRAM_DMA_XFER_ERR_CB_ID : + hsdram->DmaXferErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsdram); + return status; +} +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup SDRAM_Exported_Functions_Group3 Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### SDRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the SDRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically SDRAM write protection. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) +{ + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Enable write protection */ + (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disables dynamically SDRAM write protection. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) +{ + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Disable write protection */ + (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Sends Command to the SDRAM bank. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param Command SDRAM command structure + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, + uint32_t Timeout) +{ + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED)) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Send SDRAM command */ + (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); + + /* Update the SDRAM controller state state */ + if (Command->CommandMode == FMC_SDRAM_CMD_PALL) + { + hsdram->State = HAL_SDRAM_STATE_PRECHARGED; + } + else + { + hsdram->State = HAL_SDRAM_STATE_READY; + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Programs the SDRAM Memory Refresh rate. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param RefreshRate The SDRAM refresh rate value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) +{ + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Program the refresh rate */ + (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param AutoRefreshNumber The SDRAM auto Refresh number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) +{ + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Set the Auto-Refresh number */ + (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Returns the SDRAM memory current mode. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval The SDRAM memory mode. + */ +uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) +{ + /* Return the SDRAM memory current mode */ + return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); +} + +/** + * @} + */ + +/** @defgroup SDRAM_Exported_Functions_Group4 State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### SDRAM State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the SDRAM controller + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the SDRAM state. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL state + */ +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram) +{ + return hsdram->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions + * @{ + */ +/** + * @brief DMA SDRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma) +{ + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->DmaXferCpltCallback(hdma); +#else + HAL_SDRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma) +{ + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->DmaXferCpltCallback(hdma); +#else + HAL_SDRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SDRAM error callback. + * @param hdma : DMA handle + * @retval None + */ +static void SDRAM_DMAError(DMA_HandleTypeDef *hdma) +{ + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_ERROR; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->DmaXferErrorCallback(hdma); +#else + HAL_SDRAM_DMA_XferErrorCallback(hdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} + +/** + * @} + */ +/** + * @} + */ + +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_smartcard.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_smartcard.c new file mode 100644 index 00000000000..094a553a866 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_smartcard.c @@ -0,0 +1,3286 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_smartcard.c + * @author MCD Application Team + * @brief SMARTCARD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the SMARTCARD peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SMARTCARD HAL driver can be used as follows: + + (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard). + (#) Associate a USART to the SMARTCARD handle hsmartcard. + (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API: + (++) Enable the USARTx interface clock. + (++) USART pins configuration: + (+++) Enable the clock for the USART GPIOs. + (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). + (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT() + and HAL_SMARTCARD_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA() + and HAL_SMARTCARD_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly, + the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission + error enabling or disabling in the hsmartcard handle Init structure. + + (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...) + in the hsmartcard handle AdvancedInit structure. + + (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SMARTCARD_MspInit() API. + [..] + (@) The specific SMARTCARD interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process. + + [..] + [..] Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit() + (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT() + (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT() + (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback() + (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA() + (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA() + (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback() + (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback() + + *** SMARTCARD HAL driver macros list *** + ======================================== + [..] + Below the list of most used macros in SMARTCARD HAL driver. + + (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set + (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag + (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt + (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt + (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled + + [..] + (@) You can refer to the SMARTCARD HAL driver header file for more useful macros + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback. + Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : SMARTCARD MspInit. + (+) MspDeInitCallback : SMARTCARD MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : SMARTCARD MspInit. + (+) MspDeInitCallback : SMARTCARD MspDeInit. + + [..] + By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_SMARTCARD_Init() + and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit() + or HAL_SMARTCARD_Init() function. + + [..] + When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup SMARTCARD SMARTCARD + * @brief HAL SMARTCARD module driver + * @{ + */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants + * @{ + */ +#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ + +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE | USART_CR1_OVER8| \ + USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ + +#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ + USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ + +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \ + USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \ + USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ + +#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ + +#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SMARTCARD_Private_Functions + * @{ + */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard); +static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard); +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, + FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); +#if defined(HAL_DMA_MODULE_ENABLED) +static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions + * @{ + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx + associated to the SmartCard. + (+) These parameters can be configured: + (++) Baud Rate + (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity + (++) Receiver/transmitter modes + (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters) + (++) Prescaler value + (++) Guard bit time + (++) NACK enabling or disabling on transmission error + + (+) The following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) Time out enabling (and if activated, timeout value) + (++) Block length + (++) Auto-retry counter + [..] + The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures + (details for the procedures are available in reference manual). + +@endverbatim + + The USART frame format is given in the following table: + + Table 1. USART frame format. + +---------------------------------------------------------------+ + | M1M0 bits | PCE bit | USART frame | + |-----------------------|---------------------------------------| + | 01 | 1 | | SB | 8 bit data | PB | STB | | + +---------------------------------------------------------------+ + + + * @{ + */ + +/** + * @brief Initialize the SMARTCARD mode according to the specified + * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Check the SMARTCARD handle allocation */ + if (hsmartcard == NULL) + { + return HAL_ERROR; + } + + /* Check the USART associated to the SMARTCARD handle */ + assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); + + if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsmartcard->Lock = HAL_UNLOCKED; + +#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 + SMARTCARD_InitCallbacksToDefault(hsmartcard); + + if (hsmartcard->MspInitCallback == NULL) + { + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; + } + + /* Init the low level hardware */ + hsmartcard->MspInitCallback(hsmartcard); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_SMARTCARD_MspInit(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + } + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Disable the Peripheral to set smartcard mode */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* In SmartCard mode, the following bits must be kept cleared: + - LINEN in the USART_CR2 register, + - HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN)); + + /* set the USART in SMARTCARD mode */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN); + + /* Set the SMARTCARD Communication parameters */ + if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Set the SMARTCARD transmission completion indication */ + SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard); + + if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT) + { + SMARTCARD_AdvFeatureConfig(hsmartcard); + } + + /* Enable the Peripheral */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */ + return (SMARTCARD_CheckIdleState(hsmartcard)); +} + +/** + * @brief DeInitialize the SMARTCARD peripheral. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Check the SMARTCARD handle allocation */ + if (hsmartcard == NULL) + { + return HAL_ERROR; + } + + /* Check the USART/UART associated to the SMARTCARD handle */ + assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Disable the Peripheral */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + WRITE_REG(hsmartcard->Instance->CR1, 0x0U); + WRITE_REG(hsmartcard->Instance->CR2, 0x0U); + WRITE_REG(hsmartcard->Instance->CR3, 0x0U); + WRITE_REG(hsmartcard->Instance->RTOR, 0x0U); + WRITE_REG(hsmartcard->Instance->GTPR, 0x0U); + + /* DeInit the low level hardware */ +#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 + if (hsmartcard->MspDeInitCallback == NULL) + { + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; + } + /* DeInit the low level hardware */ + hsmartcard->MspDeInitCallback(hsmartcard); +#else + HAL_SMARTCARD_MspDeInit(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->gState = HAL_SMARTCARD_STATE_RESET; + hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Initialize the SMARTCARD MSP. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the SMARTCARD MSP. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SMARTCARD Callback + * To be used to override the weak predefined callback + * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID + * @param hsmartcard smartcard handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + switch (CallbackID) + { + + case HAL_SMARTCARD_TX_COMPLETE_CB_ID : + hsmartcard->TxCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_RX_COMPLETE_CB_ID : + hsmartcard->RxCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_ERROR_CB_ID : + hsmartcard->ErrorCallback = pCallback; + break; + + case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : + hsmartcard->AbortCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : + hsmartcard->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : + hsmartcard->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : + hsmartcard->RxFifoFullCallback = pCallback; + break; + + case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : + hsmartcard->TxFifoEmptyCallback = pCallback; + break; + + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = pCallback; + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = pCallback; + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an SMARTCARD callback + * SMARTCARD callback is redirected to the weak predefined callback + * @note The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID + * @param hsmartcard smartcard handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState) + { + switch (CallbackID) + { + case HAL_SMARTCARD_TX_COMPLETE_CB_ID : + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SMARTCARD_RX_COMPLETE_CB_ID : + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SMARTCARD_ERROR_CB_ID : + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback*/ + break; + + case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + break; + + case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; + + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState) + { + switch (CallbackID) + { + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions + * @brief SMARTCARD Transmit and Receive functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SMARTCARD data transfers. + + [..] + Smartcard is a single wire half duplex communication protocol. + The Smartcard interface is designed to support asynchronous protocol Smartcards as + defined in the ISO 7816-3 standard. The USART should be configured as: + (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register + (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. + + [..] + (#) There are two modes of transfer: + (##) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (##) Non-Blocking mode: The communication is performed using Interrupts + or DMA, the relevant API's return the HAL status. + The end of the data processing will be indicated through the + dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks + will be executed respectively at the end of the Transmit or Receive process + The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication + error is detected. + + (#) Blocking mode APIs are : + (##) HAL_SMARTCARD_Transmit() + (##) HAL_SMARTCARD_Receive() + + (#) Non Blocking mode APIs with Interrupt are : + (##) HAL_SMARTCARD_Transmit_IT() + (##) HAL_SMARTCARD_Receive_IT() + (##) HAL_SMARTCARD_IRQHandler() + + (#) Non Blocking mode functions with DMA are : + (##) HAL_SMARTCARD_Transmit_DMA() + (##) HAL_SMARTCARD_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (##) HAL_SMARTCARD_TxCpltCallback() + (##) HAL_SMARTCARD_RxCpltCallback() + (##) HAL_SMARTCARD_ErrorCallback() + + [..] + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (##) HAL_SMARTCARD_Abort() + (##) HAL_SMARTCARD_AbortTransmit() + (##) HAL_SMARTCARD_AbortReceive() + (##) HAL_SMARTCARD_Abort_IT() + (##) HAL_SMARTCARD_AbortTransmit_IT() + (##) HAL_SMARTCARD_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), + a set of Abort Complete Callbacks are provided: + (##) HAL_SMARTCARD_AbortCpltCallback() + (##) HAL_SMARTCARD_AbortTransmitCpltCallback() + (##) HAL_SMARTCARD_AbortReceiveCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, + Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. + If user wants to abort it, Abort services should be called by user. + (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt + mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + const uint8_t *ptmpdata = pData; + + /* Check that a Tx process is not already ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + if ((ptmpdata == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Disable the Peripheral first to update mode for TX master */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + /* Enable Tx */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); + + /* Enable the Peripheral */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* Perform a TX/RX FIFO Flush */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->TxXferSize = Size; + hsmartcard->TxXferCount = Size; + + while (hsmartcard->TxXferCount > 0U) + { + hsmartcard->TxXferCount--; + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU); + ptmpdata++; + } + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, + tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral first to update mode */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + /* In case of TX only mode, if NACK is enabled, receiver block has been enabled + for Transmit phase. Disable this receiver block. */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + } + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* At end of Tx process, restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + uint8_t *ptmpdata = pData; + + /* Check that a Rx process is not already ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + { + if ((ptmpdata == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + hsmartcard->RxXferSize = Size; + hsmartcard->RxXferCount = Size; + + /* Check the remain data to be received */ + while (hsmartcard->RxXferCount > 0U) + { + hsmartcard->RxXferCount--; + + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF); + ptmpdata++; + } + + /* At end of Rx process, restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_TDR register is empty, i.e one interrupt per data to transmit. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * TXFIFO threshold reached. In that case the interrupt rate depends on + * TXFIFO threshold configuration. + * @note This function sets the hsmartcard->TxIsr function pointer according to + * the FIFO mode (data transmission processing depends on FIFO mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; + + hsmartcard->pTxBuffPtr = pData; + hsmartcard->TxXferSize = Size; + hsmartcard->TxXferCount = Size; + hsmartcard->TxISR = NULL; + + /* Disable the Peripheral first to update mode for TX master */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + /* Enable Tx */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); + + /* Enable the Peripheral */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* Perform a TX/RX FIFO Flush */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + + /* Configure Tx interrupt processing */ + if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer */ + hsmartcard->TxISR = SMARTCARD_TxISR_FIFOEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Error Interrupt: (Frame error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Enable the TX FIFO threshold interrupt */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE); + } + else + { + /* Set the Tx ISR function pointer */ + hsmartcard->TxISR = SMARTCARD_TxISR; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Error Interrupt: (Frame error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_RDR register can be read, i.e one interrupt per data to receive. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * RXFIFO threshold reached. In that case the interrupt rate depends on + * RXFIFO threshold configuration. + * @note This function sets the hsmartcard->RxIsr function pointer according to + * the FIFO mode (data reception processing depends on FIFO mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; + + hsmartcard->pRxBuffPtr = pData; + hsmartcard->RxXferSize = Size; + hsmartcard->RxXferCount = Size; + + /* Configure Rx interrupt processing */ + if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer */ + hsmartcard->RxISR = SMARTCARD_RxISR_FIFOEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCART Parity Error interrupt and RX FIFO Threshold interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer */ + hsmartcard->RxISR = SMARTCARD_RxISR; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Send an amount of data in DMA mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Tx process is not already ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->pTxBuffPtr = pData; + hsmartcard->TxXferSize = Size; + hsmartcard->TxXferCount = Size; + + /* Disable the Peripheral first to update mode for TX master */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + /* Enable Tx */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); + + /* Enable the Peripheral */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* Perform a TX/RX FIFO Flush */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + + /* Set the SMARTCARD DMA transfer complete callback */ + hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; + + /* Set the SMARTCARD error callback */ + hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError; + + /* Set the DMA abort callback */ + hsmartcard->hdmatx->XferAbortCallback = NULL; + + /* Check linked list mode */ + if ((hsmartcard->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hsmartcard->hdmatx->LinkedListQueue != NULL) && (hsmartcard->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + hsmartcard->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size; + + /* Set DMA source address */ + hsmartcard->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)hsmartcard->pTxBuffPtr; + + /* Set DMA destination address */ + hsmartcard->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&hsmartcard->Instance->TDR; + + /* Enable the SMARTCARD transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(hsmartcard->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the SMARTCARD transmit DMA channel */ + status = HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, + (uint32_t)&hsmartcard->Instance->TDR, Size); + } + + if (status == HAL_OK) + { + /* Clear the TC flag in the ICR register */ + CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the UART Error Interrupt: (Frame error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the SMARTCARD associated USART CR3 register */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Restore hsmartcard->State to ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. + * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), + * the received data contain the parity bit (MSB position). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; + + hsmartcard->pRxBuffPtr = pData; + hsmartcard->RxXferSize = Size; + + /* Set the SMARTCARD DMA transfer complete callback */ + hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt; + + /* Set the SMARTCARD DMA error callback */ + hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError; + + /* Set the DMA abort callback */ + hsmartcard->hdmarx->XferAbortCallback = NULL; + + /* Check linked list mode */ + if ((hsmartcard->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hsmartcard->hdmarx->LinkedListQueue != NULL) && (hsmartcard->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + hsmartcard->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size; + + /* Set DMA source address */ + hsmartcard->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&hsmartcard->Instance->RDR; + + /* Set DMA destination address */ + hsmartcard->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)hsmartcard->pRxBuffPtr; + + /* Enable the SMARTCARD receive DMA channel */ + status = HAL_DMAEx_List_Start_IT(hsmartcard->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the DMA channel */ + status = HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, + (uint32_t)hsmartcard->pRxBuffPtr, Size); + } + + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Parity Error Interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the SMARTCARD associated USART CR3 register */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Restore hsmartcard->State to ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and + ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the SMARTCARD DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (hsmartcard->hdmatx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsmartcard->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (hsmartcard->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsmartcard->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx and Rx transfer counters */ + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Reset Handle ErrorCode to No Error */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE); + + /* Check if a receive process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the SMARTCARD DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (hsmartcard->hdmatx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsmartcard->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx transfer counter */ + hsmartcard->TxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); + + /* Restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (hsmartcard->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsmartcard->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Rx transfer counter */ + hsmartcard->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t abortcplt = 1U; + + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and + ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, + DMA Abort complete callbacks should be initialised before any call + to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (hsmartcard->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback; + } + else + { + hsmartcard->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (hsmartcard->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback; + } + else + { + hsmartcard->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the SMARTCARD DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (hsmartcard->hdmatx != NULL) + { + /* SMARTCARD Tx DMA Abort callback has already been initialised : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) + { + hsmartcard->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (hsmartcard->hdmarx != NULL) + { + /* SMARTCARD Rx DMA Abort callback has already been initialised : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) + { + hsmartcard->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; + + /* Clear ISR function pointers */ + hsmartcard->RxISR = NULL; + hsmartcard->TxISR = NULL; + + /* Reset errorCode */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hsmartcard->AbortCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort complete callback */ + HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE); + + /* Check if a receive process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the SMARTCARD DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (hsmartcard->hdmatx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) + { + /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */ + hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + hsmartcard->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + hsmartcard->TxISR = NULL; + + /* Restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hsmartcard->AbortTransmitCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Tx transfer counter */ + hsmartcard->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + hsmartcard->TxISR = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); + + /* Restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hsmartcard->AbortTransmitCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (hsmartcard->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) + { + /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */ + hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + hsmartcard->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hsmartcard->AbortReceiveCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Rx transfer counter */ + hsmartcard->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hsmartcard->AbortReceiveCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + + return HAL_OK; +} + +/** + * @brief Handle SMARTCARD interrupt requests. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR); + uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1); + uint32_t cr3its = READ_REG(hsmartcard->Instance->CR3); + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) + { + /* SMARTCARD in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (hsmartcard->RxISR != NULL) + { + hsmartcard->RxISR(hsmartcard); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))) + { + /* SMARTCARD parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF); + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE; + } + + /* SMARTCARD frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF); + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE; + } + + /* SMARTCARD noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF); + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE; + } + + /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U) + || ((cr3its & USART_CR3_EIE) != 0U))) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF); + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; + } + + /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF); + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO; + } + + /* Call SMARTCARD Error Call back function if need be --------------------------*/ + if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE) + { + /* SMARTCARD in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (hsmartcard->RxISR != NULL) + { + hsmartcard->RxISR(hsmartcard); + } + } + + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = hsmartcard->ErrorCode; + if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U)) + { + /* Blocking error : transfer is aborted + Set the SMARTCARD state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + SMARTCARD_EndRxTransfer(hsmartcard); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel */ + if (hsmartcard->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) + { + /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */ + hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx); + } + } + else + { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + /* other error type to be considered as blocking : + - Frame error in Transmission + */ + else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U)) + { + /* Blocking error : transfer is aborted + Set the SMARTCARD state ready to be able to start again the process, + Disable Tx Interrupts, and disable Tx DMA request, if ongoing */ + SMARTCARD_EndTxTransfer(hsmartcard); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the SMARTCARD DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + /* Abort the SMARTCARD DMA Tx channel */ + if (hsmartcard->hdmatx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) + { + /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */ + hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx); + } + } + else + { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/ + if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U)) + { + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + __HAL_UNLOCK(hsmartcard); +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ + HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information + to be available during HAL_SMARTCARD_RxCpltCallback() processing */ + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF); + return; + } + + /* SMARTCARD in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + if (hsmartcard->TxISR != NULL) + { + hsmartcard->TxISR(hsmartcard); + } + return; + } + + /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ + if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) + { + if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) + { + SMARTCARD_EndTransmit_IT(hsmartcard); + return; + } + } + + /* SMARTCARD TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + hsmartcard->TxFifoEmptyCallback(hsmartcard); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_SMARTCARDEx_TxFifoEmptyCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + return; + } + + /* SMARTCARD RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + hsmartcard->RxFifoFullCallback(hsmartcard); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_SMARTCARDEx_RxFifoFullCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD error callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD Abort Complete callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD Abort Complete callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD Abort Receive Complete callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief SMARTCARD State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of SmartCard + handle and also return Peripheral Errors occurred during communication process + (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state + of the SMARTCARD peripheral. + (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during + communication. + +@endverbatim + * @{ + */ + +/** + * @brief Return the SMARTCARD handle state. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval SMARTCARD handle state + */ +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Return SMARTCARD handle state */ + uint32_t temp1; + uint32_t temp2; + temp1 = (uint32_t)hsmartcard->gState; + temp2 = (uint32_t)hsmartcard->RxState; + + return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the SMARTCARD handle error code. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval SMARTCARD handle Error Code + */ +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard) +{ + return hsmartcard->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions + * @{ + */ + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/** + * @brief Initialize the callbacks to their default values. + * @param hsmartcard SMARTCARD handle. + * @retval none + */ +void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Init the SMARTCARD Callback settings */ + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak + RxFifoFullCallback */ + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak + TxFifoEmptyCallback */ + +} +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +/** + * @brief Configure the SMARTCARD associated USART peripheral. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t tmpreg; + SMARTCARD_ClockSourceTypeDef clocksource; + HAL_StatusTypeDef ret = HAL_OK; + static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); + assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate)); + assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength)); + assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits)); + assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity)); + assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode)); + assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity)); + assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase)); + assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit)); + assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling)); + assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable)); + assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable)); + assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount)); + assert_param(IS_SMARTCARD_CLOCKPRESCALER(hsmartcard->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity). + * Oversampling is forced to 16 (OVER8 = 0). + * Configure the Parity and Mode: + * set PS bit according to hsmartcard->Init.Parity value + * set TE and RE bits according to hsmartcard->Init.Mode value */ + tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) | + ((uint32_t)hsmartcard->Init.WordLength)); + MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = hsmartcard->Init.StopBits; + /* Synchronous mode is activated by default */ + tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; + tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; + tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - one-bit sampling method versus three samples' majority rule + * according to hsmartcard->Init.OneBitSampling + * - NACK transmission in case of parity error according + * to hsmartcard->Init.NACKEnable + * - autoretry counter according to hsmartcard->Init.AutoRetryCount */ + + tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable; + tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos); + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg); + + /*--------------------- SMARTCARD clock PRESC Configuration ----------------*/ + /* Configure + * - SMARTCARD Clock Prescaler: set PRESCALER according to hsmartcard->Init.ClockPrescaler value */ + MODIFY_REG(hsmartcard->Instance->PRESC, USART_PRESC_PRESCALER, hsmartcard->Init.ClockPrescaler); + + /*-------------------------- USART GTPR Configuration ----------------------*/ + tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos)); + MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg); + + /*-------------------------- USART RTOR Configuration ----------------------*/ + tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); + if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) + { + assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); + tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; + } + WRITE_REG(hsmartcard->Instance->RTOR, tmpreg); + + /*-------------------------- USART BRR Configuration -----------------------*/ + SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); + tmpreg = 0U; + switch (clocksource) + { + case SMARTCARD_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_PLL2Q: + pclk = HAL_RCC_GetPLL2QFreq(); + tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_PLL3Q: + pclk = HAL_RCC_GetPLL3QFreq(); + tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_HSI: + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + tmpreg = (uint32_t)((((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / + SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + } + else + { + tmpreg = (uint32_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + } + break; + case SMARTCARD_CLOCKSOURCE_CSI: + tmpreg = (uint32_t)(((CSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_LSE: + tmpreg = (uint32_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + break; + default: + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) + { + hsmartcard->Instance->BRR = (uint16_t)tmpreg; + } + else + { + ret = HAL_ERROR; + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + hsmartcard->NbTxDataToProcess = 1U; + hsmartcard->NbRxDataToProcess = 1U; + + /* Clear ISR function pointers */ + hsmartcard->RxISR = NULL; + hsmartcard->TxISR = NULL; + + return ret; +} + + +/** + * @brief Configure the SMARTCARD associated USART peripheral advanced features. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert)); + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert); + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap)); + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable)); + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable); + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError); + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst)); + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst); + } + +} + +/** + * @brief Check the SMARTCARD Idle State. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t tickstart; + + /* Initialize the SMARTCARD ErrorCode */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, + SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + /* Check if the Receiver is enabled */ + if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, + SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the SMARTCARD states */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Handle SMARTCARD Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param Flag Specifies the SMARTCARD flag to check. + * @param Status The actual Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout Timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, + FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + + +/** + * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* At end of Tx process, restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; +} + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; +} + + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA SMARTCARD transmit process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + hsmartcard->TxXferCount = 0U; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the SMARTCARD associated USART CR3 register */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); +} + +/** + * @brief DMA SMARTCARD receive process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + hsmartcard->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the SMARTCARD associated USART CR3 register */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ + HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} + +/** + * @brief DMA SMARTCARD communication error callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + + /* Stop SMARTCARD DMA Tx request if ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + { + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + hsmartcard->TxXferCount = 0U; + SMARTCARD_EndTxTransfer(hsmartcard); + } + } + + /* Stop SMARTCARD DMA Rx request if ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) + { + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + hsmartcard->RxXferCount = 0U; + SMARTCARD_EndRxTransfer(hsmartcard); + } + } + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA; +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} + +/** + * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + hsmartcard->RxXferCount = 0U; + hsmartcard->TxXferCount = 0U; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} + +/** + * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + + hsmartcard->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hsmartcard->hdmarx != NULL) + { + if (hsmartcard->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; + + /* Reset errorCode */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hsmartcard->AbortCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort complete callback */ + HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} + + +/** + * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + + hsmartcard->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hsmartcard->hdmatx != NULL) + { + if (hsmartcard->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; + + /* Reset errorCode */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hsmartcard->AbortCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort complete callback */ + HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} + + +/** + * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to + * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + + hsmartcard->TxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); + + /* Restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hsmartcard->AbortTransmitCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} + +/** + * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to + * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + + hsmartcard->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hsmartcard->AbortReceiveCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() + * and when the FIFO mode is disabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Check that a Tx process is ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + { + if (hsmartcard->TxXferCount == 0U) + { + /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); + } + else + { + hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU); + hsmartcard->pTxBuffPtr++; + hsmartcard->TxXferCount--; + } + } +} + +/** + * @brief Send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() + * and when the FIFO mode is enabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + { + for (nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (hsmartcard->TxXferCount == 0U) + { + /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); + } + else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU); + hsmartcard->pTxBuffPtr++; + hsmartcard->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); + + /* Check if a receive process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + + /* Disable the Peripheral first to update mode */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + /* In case of TX only mode, if NACK is enabled, receiver block has been enabled + for Transmit phase. Disable this receiver block. */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + } + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* Tx process is ended, restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Clear TxISR function pointer */ + hsmartcard->TxISR = NULL; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Tx complete callback */ + hsmartcard->TxCpltCallback(hsmartcard); +#else + /* Call legacy weak Tx complete callback */ + HAL_SMARTCARD_TxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} + +/** + * @brief Receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() + * and when the FIFO mode is disabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Check that a Rx process is ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) + { + *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + hsmartcard->pRxBuffPtr++; + + hsmartcard->RxXferCount--; + if (hsmartcard->RxXferCount == 0U) + { + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + + /* Disable the SMARTCARD Parity Error Interrupt */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ + HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief Receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() + * and when the FIFO mode is enabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint16_t nb_rx_data; + uint16_t rxdatacount; + + /* Check that a Rx process is ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) + { + for (nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + { + *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + hsmartcard->pRxBuffPtr++; + + hsmartcard->RxXferCount--; + if (hsmartcard->RxXferCount == 0U) + { + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + + /* Disable the SMARTCARD Parity Error Interrupt */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ + HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = hsmartcard->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < hsmartcard->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + hsmartcard->RxISR = SMARTCARD_RxISR; + + /* Enable the UART Data Register Not Empty interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_smartcard_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_smartcard_ex.c new file mode 100644 index 00000000000..26448e94c92 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_smartcard_ex.c @@ -0,0 +1,495 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_smartcard_ex.c + * @author MCD Application Team + * @brief SMARTCARD HAL module driver. + * This file provides extended firmware functions to manage the following + * functionalities of the SmartCard. + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================= + ##### SMARTCARD peripheral extended features ##### + ============================================================================= + [..] + The Extended SMARTCARD HAL driver can be used as follows: + + (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(), + then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut, + auto-retry counter,...) in the hsmartcard AdvancedInit structure. + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup SMARTCARDEx SMARTCARDEx + * @brief SMARTCARD Extended HAL module driver + * @{ + */ +#ifdef HAL_SMARTCARD_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup SMARTCARDEx_Private_Constants SMARTCARD Extended Private Constants + * @{ + */ +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 16U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 16U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions + * @{ + */ + +/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the SMARTCARD. + (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly + (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature + (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature + +@endverbatim + * @{ + */ + +/** @brief Update on the fly the SMARTCARD block length in RTOR register. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param BlockLength SMARTCARD block length (8-bit long at most) + * @retval None + */ +void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength) +{ + MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos)); +} + +/** @brief Update on the fly the receiver timeout value in RTOR register. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue) +{ + assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); + MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue); +} + +/** @brief Enable the SMARTCARD receiver timeout feature. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) +{ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** @brief Disable the SMARTCARD receiver timeout feature. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) +{ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions + * @brief SMARTCARD Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of FIFO mode related callback functions. + + (#) TX/RX Fifos Callbacks: + (++) HAL_SMARTCARDEx_RxFifoFullCallback() + (++) HAL_SMARTCARDEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +/** + * @brief SMARTCARD RX Fifo full callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD TX Fifo empty callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral FIFO Control functions + * @brief SMARTCARD control functions + * +@verbatim + =============================================================================== + ##### Peripheral FIFO Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SMARTCARD + FIFO feature. + (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold +@endverbatim + * @{ + */ + +/** + * @brief Enable the FIFO mode. + * @param hsmartcard SMARTCARD handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE; + + /* Restore SMARTCARD configuration */ + WRITE_REG(hsmartcard->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + SMARTCARDEx_SetNbDataToProcess(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param hsmartcard SMARTCARD handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Enable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE; + + /* Restore SMARTCARD configuration */ + WRITE_REG(hsmartcard->Instance->CR1, tmpcr1); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param hsmartcard SMARTCARD handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_8 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_4 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_2 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_3_4 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_7_8 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Update TX threshold configuration */ + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + SMARTCARDEx_SetNbDataToProcess(hsmartcard); + + /* Restore SMARTCARD configuration */ + MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param hsmartcard SMARTCARD handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_8 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_4 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_2 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_3_4 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_7_8 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Update RX threshold configuration */ + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + SMARTCARDEx_SetNbDataToProcess(hsmartcard); + + /* Restore SMARTCARD configuration */ + MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions + * @{ + */ + +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the USART configuration registers. + * @param hsmartcard SMARTCARD handle. + * @retval None + */ +static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE) + { + hsmartcard->NbTxDataToProcess = 1U; + hsmartcard->NbRxDataToProcess = 1U; + } + else + { + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \ + (uint16_t)denominator[tx_fifo_threshold]; + hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \ + (uint16_t)denominator[rx_fifo_threshold]; + } +} + +/** + * @} + */ + +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_smbus.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_smbus.c new file mode 100644 index 00000000000..38f5e4ba4df --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_smbus.c @@ -0,0 +1,2776 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_smbus.c + * @author MCD Application Team + * @brief SMBUS HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the System Management Bus (SMBus) peripheral, + * based on I2C principles of operation : + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SMBUS HAL driver can be used as follows: + + (#) Declare a SMBUS_HandleTypeDef handle structure, for example: + SMBUS_HandleTypeDef hsmbus; + + (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: + (##) Enable the SMBUSx interface clock + (##) SMBUS pins configuration + (+++) Enable the clock for the SMBUS GPIOs + (+++) Configure SMBUS pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SMBUSx interrupt priority + (+++) Enable the NVIC SMBUS IRQ Channel + + (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode, + Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, + Peripheral mode and Packet Error Check mode in the hsmbus Init structure. + + (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API: + (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SMBUS_MspInit(&hsmbus) API. + + (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() + + (#) For SMBUS IO operations, only one mode of operations is available within this driver + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Master_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback() + (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Master_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback() + (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT() + (++) The associated previous transfer callback is called at the end of abort process + (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit + (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive + (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode + using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT() + (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction + request by master/host (Write/Read). + (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback() + (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback() + (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Slave_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback() + (+) Enable/Disable the SMBUS alert mode using + HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT() + (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Alert Error Code using function HAL_SMBUS_GetError() + (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError() + (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Error Code using function HAL_SMBUS_GetError() + + *** SMBUS HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SMBUS HAL driver. + + (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral + (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral + (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not + (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag + (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt + (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function HAL_SMBUS_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback. + [..] + Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default + weak function. + HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback. + [..] + By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit() + or HAL_SMBUS_Init() function. + [..] + When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the SMBUS HAL driver header file for more useful macros + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup SMBUS SMBUS + * @brief SMBUS HAL module driver + * @{ + */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Define SMBUS Private Constants + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFUL) /*!< SMBUS TIMING clear register Mask */ +#define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_TC (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define MAX_NBYTE_SIZE 255U +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions + * @{ + */ +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout); + +/* Private functions for SMBUS transfer IRQ handler */ +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); + +/* Private function to flush TXDR register */ +static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus); + +/* Private function to handle start, restart or stop a transfer */ +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request); + +/* Private function to Convert Specific options */ +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions + * @{ + */ + +/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the SMBUSx peripheral: + + (+) User must Implement HAL_SMBUS_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, IT and NVIC ). + + (+) Call the function HAL_SMBUS_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Bus Timeout + (++) Analog Filer mode + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + (++) Packet Error Check mode + (++) Peripheral mode + + + (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration + of the selected SMBUSx peripheral. + + (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and + HAL_SMBUS_ConfigDigitalFilter(). + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the SMBUS according to the specified parameters + * in the SMBUS_InitTypeDef and initialize the associated handle. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the SMBUS handle allocation */ + if (hsmbus == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter)); + assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1)); + assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode)); + assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode)); + assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2)); + assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks)); + assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode)); + assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode)); + assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode)); + assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode)); + + if (hsmbus->State == HAL_SMBUS_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsmbus->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */ + + if (hsmbus->MspInitCallback == NULL) + { + hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hsmbus->MspInitCallback(hsmbus); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_SMBUS_MspInit(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/ + /* Configure SMBUSx: Frequency range */ + hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/ + /* Configure SMBUSx: Bus Timeout */ + hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN; + hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN; + hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout; + + /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/ + /* Configure SMBUSx: Own Address1 and ack own address1 mode */ + hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + if (hsmbus->Init.OwnAddress1 != 0UL) + { + if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) + { + hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1); + } + } + + /*---------------------------- SMBUSx CR2 Configuration ------------------------*/ + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */ + /* AUTOEND and NACK bit will be manage during Transfer process */ + hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ + /* Configure SMBUSx: Dual mode and Own Address2 */ + hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \ + (hsmbus->Init.OwnAddress2Masks << 8U)); + + /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ + /* Configure SMBUSx: Generalcall and NoStretch mode */ + hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \ + hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \ + hsmbus->Init.AnalogFilter); + + /* Enable Slave Byte Control only in case of Packet Error Check is enabled + and SMBUS Peripheral is set in Slave mode */ + if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \ + ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))) + { + hsmbus->Instance->CR1 |= I2C_CR1_SBC; + } + + /* Enable the selected SMBUS peripheral */ + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the SMBUS peripheral. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the SMBUS handle allocation */ + if (hsmbus == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the SMBUS Peripheral Clock */ + __HAL_SMBUS_DISABLE(hsmbus); + +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + if (hsmbus->MspDeInitCallback == NULL) + { + hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hsmbus->MspDeInitCallback(hsmbus); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_SMBUS_MspDeInit(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + hsmbus->PreviousState = HAL_SMBUS_STATE_RESET; + hsmbus->State = HAL_SMBUS_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} + +/** + * @brief Initialize the SMBUS MSP. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the SMBUS MSP. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Configure Analog noise filter. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref SMBUS_ANALOGFILTER_ENABLE + * @arg @ref SMBUS_ANALOGFILTER_DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Reset ANOFF bit */ + hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hsmbus->Instance->CR1 |= AnalogFilter; + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure Digital noise filter. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Get the old register value */ + tmpreg = hsmbus->Instance->CR1; + + /* Reset I2C DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos; + + /* Store the new register value */ + hsmbus->Instance->CR1 = tmpreg; + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SMBUS Callback + * To be used instead of the weak predefined callback + * @note The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in + * HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and + * HAL_SMBUS_MSPDEINIT_CB_ID. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID + * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID, + pSMBUS_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : + hsmbus->MasterTxCpltCallback = pCallback; + break; + + case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : + hsmbus->MasterRxCpltCallback = pCallback; + break; + + case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : + hsmbus->SlaveTxCpltCallback = pCallback; + break; + + case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : + hsmbus->SlaveRxCpltCallback = pCallback; + break; + + case HAL_SMBUS_LISTEN_COMPLETE_CB_ID : + hsmbus->ListenCpltCallback = pCallback; + break; + + case HAL_SMBUS_ERROR_CB_ID : + hsmbus->ErrorCallback = pCallback; + break; + + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = pCallback; + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SMBUS_STATE_RESET == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = pCallback; + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an SMBUS Callback + * SMBUS callback is redirected to the weak predefined callback + * @note The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in + * HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and + * HAL_SMBUS_MSPDEINIT_CB_ID + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID + * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : + hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : + hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : + hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : + hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_SMBUS_LISTEN_COMPLETE_CB_ID : + hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_SMBUS_ERROR_CB_ID : + hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SMBUS_STATE_RESET == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register the Slave Address Match SMBUS Callback + * To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, + pSMBUS_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + hsmbus->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Slave Address Match SMBUS Callback + * Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SMBUS data + transfers. + + (#) Blocking mode function to check if device is ready for usage is : + (++) HAL_SMBUS_IsDeviceReady() + + (#) There is only one mode of transfer: + (++) Non-Blocking mode : The communication is performed using Interrupts. + These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated SMBUS IRQ when using Interrupt mode. + + (#) Non-Blocking mode functions with Interrupt are : + (++) HAL_SMBUS_Master_Transmit_IT() + (++) HAL_SMBUS_Master_Receive_IT() + (++) HAL_SMBUS_Slave_Transmit_IT() + (++) HAL_SMBUS_Slave_Receive_IT() + (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT() + (++) HAL_SMBUS_DisableListen_IT() + (++) HAL_SMBUS_EnableAlert_IT() + (++) HAL_SMBUS_DisableAlert_IT() + + (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode: + (++) HAL_SMBUS_MasterTxCpltCallback() + (++) HAL_SMBUS_MasterRxCpltCallback() + (++) HAL_SMBUS_SlaveTxCpltCallback() + (++) HAL_SMBUS_SlaveRxCpltCallback() + (++) HAL_SMBUS_AddrCallback() + (++) HAL_SMBUS_ListenCpltCallback() + (++) HAL_SMBUS_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + /* In case of Quick command, remove autoend mode */ + /* Manage the stop generation by software */ + if (hsmbus->pBuffPtr == NULL) + { + hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; + } + + if (Size > MAX_NBYTE_SIZE) + { + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = Size; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) + { + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_START_WRITE); + } + else + { + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + + /* Store current volatile XferOptions, misra rule */ + tmp = hsmbus->XferOptions; + + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \ + (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + { + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); + } + /* Else transfer direction change, so generate Restart with new transfer direction */ + else + { + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Handle Transfer */ + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, + SMBUS_GENERATE_START_WRITE); + } + + /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) + { + if (hsmbus->XferSize > 0U) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else + { + return HAL_ERROR; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + /* In case of Quick command, remove autoend mode */ + /* Manage the stop generation by software */ + if (hsmbus->pBuffPtr == NULL) + { + hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; + } + + if (Size > MAX_NBYTE_SIZE) + { + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = Size; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) + { + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_START_READ); + } + else + { + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + + /* Store current volatile XferOptions, Misra rule */ + tmp = hsmbus->XferOptions; + + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \ + (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + { + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); + } + /* Else transfer direction change, so generate Restart with new transfer direction */ + else + { + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Handle Transfer */ + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, + SMBUS_GENERATE_START_READ); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master/host SMBUS process communication with Interrupt. + * @note This abort can be called only if state is ready + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) +{ + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + /* Keep the same state as previous */ + /* to perform as well the call of the corresponding end of transfer callback */ + if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; + } + else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); + } + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); + } + else + { + /* Nothing to do */ + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0UL)) + { + hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX); + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN); + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Set SBC bit to manage Acknowledge at each bit */ + hsmbus->Instance->CR1 |= I2C_CR1_SBC; + + /* Enable Address Acknowledge */ + hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + if (Size > MAX_NBYTE_SIZE) + { + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = Size; + } + + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) + { + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_NO_STARTSTOP); + } + else + { + /* Set NBYTE to transmit */ + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); + + /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the HOST */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0UL)) + { + hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX); + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN); + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Set SBC bit to manage Acknowledge at each bit */ + hsmbus->Instance->CR1 |= I2C_CR1_SBC; + + /* Enable Address Acknowledge */ + hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferSize = Size; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Set NBYTE to receive */ + /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */ + /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ + /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ + /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ + if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U)) + { + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); + } + else + { + SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); + } + + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the HOST */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus) +{ + hsmbus->State = HAL_SMBUS_STATE_LISTEN; + + /* Enable the Address Match interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR); + + return HAL_OK; +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) +{ + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) + { + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Disable the Address Match interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the SMBUS alert mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) +{ + /* Enable SMBus alert */ + hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN; + + /* Clear ALERT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); + + /* Enable Alert Interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT); + + return HAL_OK; +} +/** + * @brief Disable the SMBUS alert mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) +{ + /* Enable SMBus alert */ + hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN; + + /* Disable Alert Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT); + + return HAL_OK; +} + +/** + * @brief Check if target device is ready for communication. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t SMBUS_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + do + { + /* Generate Start */ + hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF); + tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + /* Device is ready */ + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Update SMBUS error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + return HAL_ERROR; + } + } + + tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF); + tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Device is ready */ + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + } + + /* Check if the maximum allowed number of trials has been reached */ + if (SMBUS_Trials == Trials) + { + /* Generate Stop */ + hsmbus->Instance->CR2 |= I2C_CR2_STOP; + + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + } + + /* Increment Trials */ + SMBUS_Trials++; + } while (SMBUS_Trials < Trials); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Update SMBUS error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief Handle SMBUS event interrupt request. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) +{ + /* Use a local variable to store the current ISR flags */ + /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ + uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR); + uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1); + + /* SMBUS in mode Transmitter ---------------------------------------------------*/ + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | + SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + { + /* Slave mode selected */ + if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + { + (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue); + } + /* Master mode selected */ + else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue); + } + else + { + /* Nothing to do */ + } + } + + /* SMBUS in mode Receiver ----------------------------------------------------*/ + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | + SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + { + /* Slave mode selected */ + if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) + { + (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue); + } + /* Master mode selected */ + else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue); + } + else + { + /* Nothing to do */ + } + } + + /* SMBUS in mode Listener Only --------------------------------------------------*/ + if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || + (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || + (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + { + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) + { + (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue); + } + } +} + +/** + * @brief Handle SMBUS error interrupt request. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) +{ + SMBUS_ITErrorHandler(hsmbus); +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param TransferDirection Master request Transfer Direction (Write/Read) + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief SMBUS error callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_ErrorCallback() could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the SMBUS handle state. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL state + */ +uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus) +{ + /* Return SMBUS handle state */ + return hsmbus->State; +} + +/** + * @brief Return the SMBUS error code. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval SMBUS Error Code + */ +uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus) +{ + return hsmbus->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions + * @brief Data transfers Private functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param StatusFlags Value of Interrupt Flags. + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) +{ + uint16_t DevAddress; + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Error callback to inform upper layer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ErrorCallback(hsmbus); +#else + HAL_SMBUS_ErrorCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET) + { + /* Check and treat errors if errors occurs during STOP process */ + SMBUS_ITErrorHandler(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + SMBUS_RESET_CR2(hsmbus); + + /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Re-enable the selected SMBUS peripheral */ + __HAL_SMBUS_ENABLE(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback(hsmbus); +#else + HAL_SMBUS_MasterTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + /* Store Last receive data if any */ + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + if ((hsmbus->XferSize > 0U)) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + SMBUS_RESET_CR2(hsmbus); + + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterRxCpltCallback(hsmbus); +#else + HAL_SMBUS_MasterRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + /* Increment Size counter */ + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET) + { + /* Write data to TXDR */ + hsmbus->Instance->TXDR = *hsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + /* Increment Size counter */ + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET) + { + if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U)) + { + DevAddress = (uint16_t)(hsmbus->Instance->CR2 & I2C_CR2_SADD); + + if (hsmbus->XferCount > MAX_NBYTE_SIZE) + { + SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, + (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), + SMBUS_NO_STARTSTOP); + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = hsmbus->XferCount; + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); + /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + } + else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U)) + { + /* Call TxCpltCallback() if no stop mode is set */ + if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback(hsmbus); +#else + HAL_SMBUS_MasterTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterRxCpltCallback(hsmbus); +#else + HAL_SMBUS_MasterRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + } + else + { + /* Nothing to do */ + } + } + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET) + { + if (hsmbus->XferCount == 0U) + { + /* Specific use case for Quick command */ + if (hsmbus->pBuffPtr == NULL) + { + /* Generate a Stop command */ + hsmbus->Instance->CR2 |= I2C_CR2_STOP; + } + /* Call TxCpltCallback() if no stop mode is set */ + else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + { + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */ + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback(hsmbus); +#else + HAL_SMBUS_MasterTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterRxCpltCallback(hsmbus); +#else + HAL_SMBUS_MasterRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else + { + /* Nothing to do */ + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param StatusFlags Value of Interrupt Flags. + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) +{ + uint8_t TransferDirection; + uint16_t SlaveAddrCode; + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET) + { + /* Check that SMBUS transfer finished */ + /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hsmbus->XferCount == 0U) + { + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + } + else + { + /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/ + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Set HAL State to "Idle" State, mean to LISTEN state */ + /* So reset Slave Busy state */ + hsmbus->PreviousState = hsmbus->State; + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX); + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); + + /* Disable RX/TX Interrupts, keep only ADDR Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Error callback to inform upper layer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ErrorCallback(hsmbus); +#else + HAL_SMBUS_ErrorCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + } + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET) + { + TransferDirection = (uint8_t)(SMBUS_GET_DIR(hsmbus)); + SlaveAddrCode = (uint16_t)(SMBUS_GET_ADDR_MATCH(hsmbus)); + + /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/ + /* Other ADDRInterrupt will be treat in next Listen usecase */ + __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call Slave Addr callback */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); +#else + HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || + (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)) + { + if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) + { + /* Read data from RXDR */ + *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + hsmbus->XferSize--; + hsmbus->XferCount--; + + if (hsmbus->XferCount == 1U) + { + /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */ + /* or only the last Byte of Transfer */ + /* So reset the RELOAD bit mode */ + hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; + SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + } + else if (hsmbus->XferCount == 0U) + { + /* Last Byte is received, disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */ + hsmbus->PreviousState = hsmbus->State; + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->SlaveRxCpltCallback(hsmbus); +#else + HAL_SMBUS_SlaveRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Set Reload for next Bytes */ + SMBUS_TransferConfig(hsmbus, 0, 1, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_NO_STARTSTOP); + + /* Ack last Byte Read */ + hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; + } + } + else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + { + if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U)) + { + if (hsmbus->XferCount > MAX_NBYTE_SIZE) + { + SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, + (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), + SMBUS_NO_STARTSTOP); + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = hsmbus->XferCount; + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); + /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + } + } + else + { + /* Nothing to do */ + } + } + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hsmbus->XferCount > 0U) + { + /* Write data to TXDR */ + hsmbus->Instance->TXDR = *hsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + hsmbus->XferCount--; + hsmbus->XferSize--; + } + + if (hsmbus->XferCount == 0U) + { + /* Last Byte is Transmitted */ + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->SlaveTxCpltCallback(hsmbus); +#else + HAL_SMBUS_SlaveTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } + + /* Check if STOPF is set */ + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET) + { + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) + { + /* Store Last receive data if any */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + if ((hsmbus->XferSize > 0U)) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + + /* Disable RX and TX Interrupts */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); + + /* Disable ADDR Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); + + /* Disable Address Acknowledge */ + hsmbus->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + SMBUS_RESET_CR2(hsmbus); + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Clear ADDR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); + + hsmbus->XferOptions = 0; + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ListenCpltCallback(hsmbus); +#else + HAL_SMBUS_ListenCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} +/** + * @brief Manage the enabling of Interrupts. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. + * @retval HAL status + */ +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) +{ + uint32_t tmpisr = 0UL; + + if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) + { + /* Enable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + { + /* Enable ADDR, STOP interrupt */ + tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI; + } + + if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + { + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI; + } + + if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + { + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI; + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of SMBUS interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr); +} +/** + * @brief Manage the disabling of Interrupts. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. + * @retval HAL status + */ +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) +{ + uint32_t tmpisr = 0UL; + uint32_t tmpstate = hsmbus->State; + + if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + { + /* Disable TC, STOP, NACK and TXI interrupt */ + tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; + + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL) + && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + { + /* Disable STOP and NACK interrupt */ + tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; + } + } + + if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + { + /* Disable TC, STOP, NACK and RXI interrupt */ + tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; + + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL) + && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + { + /* Disable STOP and NACK interrupt */ + tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; + } + } + + if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + { + /* Disable ADDR, STOP and NACK interrupt */ + tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; + + if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr); +} + +/** + * @brief SMBUS interrupts error handler. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) +{ + uint32_t itflags = READ_REG(hsmbus->Instance->ISR); + uint32_t itsources = READ_REG(hsmbus->Instance->CR1); + uint32_t tmpstate; + uint32_t tmperror; + + /* SMBUS Bus error interrupt occurred ------------------------------------*/ + if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); + } + + /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); + } + + /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ + if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); + } + + /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ + if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; + + /* Clear TIMEOUT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); + } + + /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ + if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; + + /* Clear ALERT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); + } + + /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ + if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; + + /* Clear PEC error flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); + } + + if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) + { + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + } + + /* Store current volatile hsmbus->ErrorCode, misra rule */ + tmperror = hsmbus->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF)) + { + /* Do not Reset the HAL state in case of ALERT error */ + if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) + { + /* Store current volatile hsmbus->State, misra rule */ + tmpstate = hsmbus->State; + + if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) + { + /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ + /* keep HAL_SMBUS_STATE_LISTEN if set */ + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_LISTEN; + } + } + + /* Call the Error callback to inform upper layer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ErrorCallback(hsmbus); +#else + HAL_SMBUS_ErrorCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Handle SMBUS Communication Timeout. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param Flag Specifies the SMBUS flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Update SMBUS error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +/** + * @brief SMBUS Tx data register flush process. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + { + hsmbus->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXE) == RESET) + { + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TXE); + } +} + +/** + * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hsmbus SMBUS handle. + * @param DevAddress specifies the slave address to be programmed. + * @param Size specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the SMBUS START condition generation. + * This parameter can be one or a combination of the following values: + * @arg @ref SMBUS_RELOAD_MODE Enable Reload mode. + * @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode. + * @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode. + * @param Request New state of the SMBUS START condition generation. + * This parameter can be one of the following values: + * @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request. + * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_TRANSFER_MODE(Mode)); + assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); + + /* update CR2 register */ + MODIFY_REG(hsmbus->Instance->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request)); +} + +/** + * @brief Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) +{ + /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to SMBUS_FIRST_FRAME */ + if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_FRAME; + } + /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */ + else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE; + } + /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */ + else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC; + } + /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */ + else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC; + } + else + { + /* Nothing to do */ + } +} +/** + * @} + */ + +#endif /* HAL_SMBUS_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_smbus_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_smbus_ex.c new file mode 100644 index 00000000000..a158cb3a166 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_smbus_ex.c @@ -0,0 +1,245 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_smbus_ex.c + * @author MCD Application Team + * @brief SMBUS Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of SMBUS Extended peripheral: + * + Extended features functions + * + WakeUp Mode Functions + * + FastModePlus Functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### SMBUS peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the SMBUS interface for STM32H7RSxx + devices contains the following additional features + + (+) Disable or enable wakeup from Stop mode(s) + + ##### How to use this driver ##### + ============================================================================== + (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions : + (++) HAL_SMBUSEx_EnableWakeUp() + (++) HAL_SMBUSEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_SMBUSEx_ConfigFastModePlus() + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup SMBUSEx SMBUSEx + * @brief SMBUS Extended HAL module driver + * @{ + */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Enable SMBUS wakeup from Stop mode(s). + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Enable wakeup from stop mode */ + hsmbus->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable SMBUS wakeup from Stop mode(s). + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Disable wakeup from stop mode */ + hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Configure SMBUS Fast Mode Plus. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @param FastModePlus New state of the Fast Mode Plus. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUSEx_ConfigFastModePlus(SMBUS_HandleTypeDef *hsmbus, uint32_t FastModePlus) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_FASTMODEPLUS(FastModePlus)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + if (FastModePlus == SMBUS_FASTMODEPLUS_ENABLE) + { + /* Set SMBUSx FMP bit */ + hsmbus->Instance->CR1 |= (I2C_CR1_FMP); + } + else + { + /* Reset SMBUSx FMP bit */ + hsmbus->Instance->CR1 &= ~(I2C_CR1_FMP); + } + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SMBUS_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_spdifrx.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_spdifrx.c new file mode 100644 index 00000000000..7d670b72454 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_spdifrx.c @@ -0,0 +1,1741 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_spdifrx.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the SPDIFRX audio interface: + * + Initialization and Configuration + * + Data transfers functions + * + DMA transfers management + * + Interrupts and flags management + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The SPDIFRX HAL driver can be used as follow: + + (#) Declare SPDIFRX_HandleTypeDef handle structure. + (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API: + (##) Enable the SPDIFRX interface clock. + (##) SPDIFRX pins configuration: + (+++) Enable the clock for the SPDIFRX GPIOs. + (+++) Configure these SPDIFRX pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveCtrlFlow_IT() and + HAL_SPDIFRX_ReceiveDataFlow_IT() API's). + (+++) Configure the SPDIFRX interrupt priority. + (+++) Enable the NVIC SPDIFRX IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and + HAL_SPDIFRX_ReceiveCtrlFlow_DMA() API's). + (+++) Declare a DMA handle structure for the reception of the Data Flow channel. + (+++) Declare a DMA handle structure for the reception of the Control Flow channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters. + (+++) Configure the DMA Channel. + (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the + DMA CtrlRx/DataRx channel. + + (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, + stereo mode and masking of user bits using HAL_SPDIFRX_Init() function. + + -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros + __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process. + -@- Make sure that ck_spdif clock is configured. + + (#) Three operation modes are available within this driver : + + *** Polling mode for reception operation (for debug purpose) *** + ================================================================ + [..] + (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow() + (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveCtrlFlow() + + *** Interrupt mode for reception operation *** + ========================================= + [..] + (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT() + (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveCtrlFlow_IT() + (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback + (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback + (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback + + *** DMA mode for reception operation *** + ======================================== + [..] + (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA() + (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveCtrlFlow_DMA() + (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback + (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback + (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback + (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop() + + *** SPDIFRX HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in SPDIFRX HAL driver. + (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDLE State) + (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State) + (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State) + (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts + (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts + (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not. + + [..] + (@) You can refer to the SPDIFRX HAL driver header file for more useful macros + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_SPDIFRX_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use HAL_SPDIFRX_RegisterCallback() function to register an interrupt callback. + + The HAL_SPDIFRX_RegisterCallback() function allows to register the following callbacks: + (+) RxHalfCpltCallback : SPDIFRX Data flow half completed callback. + (+) RxCpltCallback : SPDIFRX Data flow completed callback. + (+) CxHalfCpltCallback : SPDIFRX Control flow half completed callback. + (+) CxCpltCallback : SPDIFRX Control flow completed callback. + (+) ErrorCallback : SPDIFRX error callback. + (+) MspInitCallback : SPDIFRX MspInit. + (+) MspDeInitCallback : SPDIFRX MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use HAL_SPDIFRX_UnRegisterCallback() function to reset a callback to the default + weak function. + The HAL_SPDIFRX_UnRegisterCallback() function takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset the following callbacks: + (+) RxHalfCpltCallback : SPDIFRX Data flow half completed callback. + (+) RxCpltCallback : SPDIFRX Data flow completed callback. + (+) CxHalfCpltCallback : SPDIFRX Control flow half completed callback. + (+) CxCpltCallback : SPDIFRX Control flow completed callback. + (+) ErrorCallback : SPDIFRX error callback. + (+) MspInitCallback : SPDIFRX MspInit. + (+) MspDeInitCallback : SPDIFRX MspDeInit. + + By default, after the HAL_SPDIFRX_Init() and when the state is HAL_SPDIFRX_STATE_RESET + all callbacks are set to the corresponding weak functions : + HAL_SPDIFRX_RxHalfCpltCallback() , HAL_SPDIFRX_RxCpltCallback(), HAL_SPDIFRX_CxHalfCpltCallback(), + HAL_SPDIFRX_CxCpltCallback() and HAL_SPDIFRX_ErrorCallback() + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_SPDIFRX_Init()/ HAL_SPDIFRX_DeInit() only when + these callbacks pointers are NULL (not registered beforehand). + If not, MspInit or MspDeInit callbacks pointers are not null, the HAL_SPDIFRX_Init() / HAL_SPDIFRX_DeInit() + keep and use the user MspInit/MspDeInit functions (registered beforehand) + + Callbacks can be registered/unregistered in HAL_SPDIFRX_STATE_READY state only. + Exception done MspInit/MspDeInit callbacks that can be registered/unregistered + in HAL_SPDIFRX_STATE_READY or HAL_SPDIFRX_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SPDIFRX_RegisterCallback() before calling HAL_SPDIFRX_DeInit() + or HAL_SPDIFRX_Init() function. + + When The compilation define USE_HAL_SPDIFRX_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup SPDIFRX SPDIFRX + * @brief SPDIFRX HAL module driver + * @{ + */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED +#if defined (SPDIFRX) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup SPDIFRX_Private_Defines SPDIFRX Private Defines + * @{ + */ +#define SPDIFRX_TIMEOUT_VALUE 10U +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SPDIFRX_Private_Functions + * @{ + */ +static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma); +static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma); +static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma); +static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma); +static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif); +static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif); +static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, + FlagStatus Status, uint32_t Timeout, uint32_t tickstart); +/** + * @} + */ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions + * @{ + */ + +/** @defgroup SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SPDIFRX peripheral: + + (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with + the selected configuration: + (++) Input Selection (IN0, IN1,...) + (++) Maximum allowed re-tries during synchronization phase + (++) Wait for activity on SPDIF selected input + (++) Channel status selection (from channel A or B) + (++) Data format (LSB, MSB, ...) + (++) Stereo mode + (++) User bits masking (PT,C,U,V,...) + + (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration + of the selected SPDIFRXx peripheral. + @endverbatim + * @{ + */ + +/** + * @brief Initializes the SPDIFRX according to the specified parameters + * in the SPDIFRX_InitTypeDef and create the associated handle. + * @param hspdif SPDIFRX handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) +{ + uint32_t tmpreg; + + /* Check the SPDIFRX handle allocation */ + if (hspdif == NULL) + { + return HAL_ERROR; + } + + /* Check the SPDIFRX parameters */ + assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode)); + assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection)); + assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries)); + assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity)); + assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection)); + assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat)); + assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask)); + assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask)); + assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask)); + assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask)); + assert_param(IS_SYMBOL_CLOCK_GEN(hspdif->Init.SymbolClockGen)); + assert_param(IS_SYMBOL_CLOCK_GEN(hspdif->Init.BackupSymbolClockGen)); + +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) + if (hspdif->State == HAL_SPDIFRX_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspdif->Lock = HAL_UNLOCKED; + + hspdif->RxHalfCpltCallback = HAL_SPDIFRX_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hspdif->RxCpltCallback = HAL_SPDIFRX_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hspdif->CxHalfCpltCallback = HAL_SPDIFRX_CxHalfCpltCallback; /* Legacy weak CxHalfCpltCallback */ + hspdif->CxCpltCallback = HAL_SPDIFRX_CxCpltCallback; /* Legacy weak CxCpltCallback */ + hspdif->ErrorCallback = HAL_SPDIFRX_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hspdif->MspInitCallback == NULL) + { + hspdif->MspInitCallback = HAL_SPDIFRX_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hspdif->MspInitCallback(hspdif); + } +#else + if (hspdif->State == HAL_SPDIFRX_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspdif->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_SPDIFRX_MspInit(hspdif); + } +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ + + /* SPDIFRX peripheral state is BUSY */ + hspdif->State = HAL_SPDIFRX_STATE_BUSY; + + /* Disable SPDIFRX interface (IDLE State) */ + __HAL_SPDIFRX_IDLE(hspdif); + + /* Reset the old SPDIFRX CR configuration */ + tmpreg = hspdif->Instance->CR; + + tmpreg &= ~(SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK | + SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | + SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA | + SPDIFRX_CR_CKSEN | SPDIFRX_CR_CKSBKPEN | + SPDIFRX_CR_INSEL); + + /* Sets the new configuration of the SPDIFRX peripheral */ + tmpreg |= (hspdif->Init.StereoMode | + hspdif->Init.InputSelection | + hspdif->Init.Retries | + hspdif->Init.WaitForActivity | + hspdif->Init.ChannelSelection | + hspdif->Init.DataFormat | + hspdif->Init.PreambleTypeMask | + hspdif->Init.ChannelStatusMask | + hspdif->Init.ValidityBitMask | + hspdif->Init.ParityErrorMask + ); + + if (hspdif->Init.SymbolClockGen == ENABLE) + { + tmpreg |= SPDIFRX_CR_CKSEN; + } + + if (hspdif->Init.BackupSymbolClockGen == ENABLE) + { + tmpreg |= SPDIFRX_CR_CKSBKPEN; + } + + hspdif->Instance->CR = tmpreg; + + hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; + + /* SPDIFRX peripheral state is READY*/ + hspdif->State = HAL_SPDIFRX_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the SPDIFRX peripheral + * @param hspdif SPDIFRX handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) +{ + /* Check the SPDIFRX handle allocation */ + if (hspdif == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance)); + + hspdif->State = HAL_SPDIFRX_STATE_BUSY; + + /* Disable SPDIFRX interface (IDLE state) */ + __HAL_SPDIFRX_IDLE(hspdif); + +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) + if (hspdif->MspDeInitCallback == NULL) + { + hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hspdif->MspDeInitCallback(hspdif); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPDIFRX_MspDeInit(hspdif); +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ + + hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; + + /* SPDIFRX peripheral state is RESET*/ + hspdif->State = HAL_SPDIFRX_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspdif); + + return HAL_OK; +} + +/** + * @brief SPDIFRX MSP Init + * @param hspdif SPDIFRX handle + * @retval None + */ +__weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspdif); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPDIFRX_MspInit could be implemented in the user file + */ +} + +/** + * @brief SPDIFRX MSP DeInit + * @param hspdif SPDIFRX handle + * @retval None + */ +__weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspdif); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPDIFRX_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SPDIFRX Callback + * To be used instead of the weak predefined callback + * @param hspdif SPDIFRX handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SPDIFRX_RX_HALF_CB_ID SPDIFRX Data flow half completed callback ID + * @arg @ref HAL_SPDIFRX_RX_CPLT_CB_ID SPDIFRX Data flow completed callback ID + * @arg @ref HAL_SPDIFRX_CX_HALF_CB_ID SPDIFRX Control flow half completed callback ID + * @arg @ref HAL_SPDIFRX_CX_CPLT_CB_ID SPDIFRX Control flow completed callback ID + * @arg @ref HAL_SPDIFRX_ERROR_CB_ID SPDIFRX error callback ID + * @arg @ref HAL_SPDIFRX_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, + pSPDIFRX_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hspdif); + + if (HAL_SPDIFRX_STATE_READY == hspdif->State) + { + switch (CallbackID) + { + case HAL_SPDIFRX_RX_HALF_CB_ID : + hspdif->RxHalfCpltCallback = pCallback; + break; + + case HAL_SPDIFRX_RX_CPLT_CB_ID : + hspdif->RxCpltCallback = pCallback; + break; + + case HAL_SPDIFRX_CX_HALF_CB_ID : + hspdif->CxHalfCpltCallback = pCallback; + break; + + case HAL_SPDIFRX_CX_CPLT_CB_ID : + hspdif->CxCpltCallback = pCallback; + break; + + case HAL_SPDIFRX_ERROR_CB_ID : + hspdif->ErrorCallback = pCallback; + break; + + case HAL_SPDIFRX_MSPINIT_CB_ID : + hspdif->MspInitCallback = pCallback; + break; + + case HAL_SPDIFRX_MSPDEINIT_CB_ID : + hspdif->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPDIFRX_STATE_RESET == hspdif->State) + { + switch (CallbackID) + { + case HAL_SPDIFRX_MSPINIT_CB_ID : + hspdif->MspInitCallback = pCallback; + break; + + case HAL_SPDIFRX_MSPDEINIT_CB_ID : + hspdif->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspdif); + return status; +} + +/** + * @brief Unregister a SPDIFRX Callback + * SPDIFRX callback is redirected to the weak predefined callback + * @param hspdif SPDIFRX handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SPDIFRX_RX_HALF_CB_ID SPDIFRX Data flow half completed callback ID + * @arg @ref HAL_SPDIFRX_RX_CPLT_CB_ID SPDIFRX Data flow completed callback ID + * @arg @ref HAL_SPDIFRX_CX_HALF_CB_ID SPDIFRX Control flow half completed callback ID + * @arg @ref HAL_SPDIFRX_CX_CPLT_CB_ID SPDIFRX Control flow completed callback ID + * @arg @ref HAL_SPDIFRX_ERROR_CB_ID SPDIFRX error callback ID + * @arg @ref HAL_SPDIFRX_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, + HAL_SPDIFRX_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hspdif); + + if (HAL_SPDIFRX_STATE_READY == hspdif->State) + { + switch (CallbackID) + { + case HAL_SPDIFRX_RX_HALF_CB_ID : + hspdif->RxHalfCpltCallback = HAL_SPDIFRX_RxHalfCpltCallback; + break; + + case HAL_SPDIFRX_RX_CPLT_CB_ID : + hspdif->RxCpltCallback = HAL_SPDIFRX_RxCpltCallback; + break; + + case HAL_SPDIFRX_CX_HALF_CB_ID : + hspdif->CxHalfCpltCallback = HAL_SPDIFRX_CxHalfCpltCallback; + break; + + case HAL_SPDIFRX_CX_CPLT_CB_ID : + hspdif->CxCpltCallback = HAL_SPDIFRX_CxCpltCallback; + break; + + case HAL_SPDIFRX_ERROR_CB_ID : + hspdif->ErrorCallback = HAL_SPDIFRX_ErrorCallback; + break; + + default : + /* Update the error code */ + hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPDIFRX_STATE_RESET == hspdif->State) + { + switch (CallbackID) + { + case HAL_SPDIFRX_MSPINIT_CB_ID : + hspdif->MspInitCallback = HAL_SPDIFRX_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPDIFRX_MSPDEINIT_CB_ID : + hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit; /* Legacy weak MspInit */ + break; + + default : + /* Update the error code */ + hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspdif); + return status; +} + +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ + +/** + * @brief Set the SPDIFRX data format according to the specified parameters in the SPDIFRX_InitTypeDef. + * @param hspdif SPDIFRX handle + * @param sDataFormat SPDIFRX data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat) +{ + uint32_t tmpreg; + + /* Check the SPDIFRX handle allocation */ + if (hspdif == NULL) + { + return HAL_ERROR; + } + + /* Check the SPDIFRX parameters */ + assert_param(IS_STEREO_MODE(sDataFormat.StereoMode)); + assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat)); + assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask)); + assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask)); + assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask)); + assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask)); + + /* Reset the old SPDIFRX CR configuration */ + tmpreg = hspdif->Instance->CR; + + if (((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) && + (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) || + ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode))) + { + return HAL_ERROR; + } + + tmpreg &= ~(SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK | + SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK); + + /* Configure the new data format */ + tmpreg |= (sDataFormat.StereoMode | + sDataFormat.DataFormat | + sDataFormat.PreambleTypeMask | + sDataFormat.ChannelStatusMask | + sDataFormat.ValidityBitMask | + sDataFormat.ParityErrorMask); + + hspdif->Instance->CR = tmpreg; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim +=============================================================================== + ##### IO operation functions ##### +=============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SPDIFRX data + transfers. + + (#) There is two mode of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer start-up. + The end of the data processing will be indicated through the + dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_SPDIFRX_ReceiveDataFlow() + (++) HAL_SPDIFRX_ReceiveCtrlFlow() + (+@) Do not use blocking mode to receive both control and data flow at the same time. + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_SPDIFRX_ReceiveCtrlFlow_IT() + (++) HAL_SPDIFRX_ReceiveDataFlow_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_SPDIFRX_ReceiveCtrlFlow_DMA() + (++) HAL_SPDIFRX_ReceiveDataFlow_DMA() + + (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (++) HAL_SPDIFRX_RxCpltCallback() + (++) HAL_SPDIFRX_CxCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Receives an amount of data (Data Flow) in blocking mode. + * @param hspdif pointer to SPDIFRX_HandleTypeDef structure that contains + * the configuration information for SPDIFRX module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + uint16_t sizeCounter = Size; + uint32_t *pTmpBuf = pData; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hspdif->State == HAL_SPDIFRX_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hspdif); + + hspdif->State = HAL_SPDIFRX_STATE_BUSY; + + /* Start synchronisation */ + __HAL_SPDIFRX_SYNC(hspdif); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until SYNCD flag is set */ + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Start reception */ + __HAL_SPDIFRX_RCV(hspdif); + + /* Receive data flow */ + while (sizeCounter > 0U) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until RXNE flag is set */ + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*pTmpBuf) = hspdif->Instance->DR; + pTmpBuf++; + sizeCounter--; + } + + /* SPDIFRX ready */ + hspdif->State = HAL_SPDIFRX_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data (Control Flow) in blocking mode. + * @param hspdif pointer to a SPDIFRX_HandleTypeDef structure that contains + * the configuration information for SPDIFRX module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + uint16_t sizeCounter = Size; + uint32_t *pTmpBuf = pData; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hspdif->State == HAL_SPDIFRX_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hspdif); + + hspdif->State = HAL_SPDIFRX_STATE_BUSY; + + /* Start synchronization */ + __HAL_SPDIFRX_SYNC(hspdif); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until SYNCD flag is set */ + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Start reception */ + __HAL_SPDIFRX_RCV(hspdif); + + /* Receive control flow */ + while (sizeCounter > 0U) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until CSRNE flag is set */ + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*pTmpBuf) = hspdif->Instance->CSR; + pTmpBuf++; + sizeCounter--; + } + + /* SPDIFRX ready */ + hspdif->State = HAL_SPDIFRX_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data sample to be received . + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) +{ + uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); + + const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; + + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspdif); + + hspdif->pRxBuffPtr = pData; + hspdif->RxXferSize = Size; + hspdif->RxXferCount = Size; + + hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; + + /* Check if a receive process is ongoing or not */ + hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX; + + /* Enable the SPDIFRX PE Error Interrupt */ + __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE); + + /* Enable the SPDIFRX OVR Error Interrupt */ + __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE); + + /* Enable the SPDIFRX RXNE interrupt */ + __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE); + + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFRXEN) != SPDIFRX_STATE_RCV) + { + /* Start synchronization */ + __HAL_SPDIFRX_SYNC(hspdif); + + /* Wait until SYNCD flag is set */ + do + { + if (count == 0U) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt + process */ + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); + + hspdif->State = HAL_SPDIFRX_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_TIMEOUT; + } + count--; + } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET); + + /* Start reception */ + __HAL_SPDIFRX_RCV(hspdif); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data (Control Flow) with Interrupt + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data sample (Control Flow) to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) +{ + uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); + + const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; + + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspdif); + + hspdif->pCsBuffPtr = pData; + hspdif->CsXferSize = Size; + hspdif->CsXferCount = Size; + + hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; + + /* Check if a receive process is ongoing or not */ + hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX; + + /* Enable the SPDIFRX PE Error Interrupt */ + __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE); + + /* Enable the SPDIFRX OVR Error Interrupt */ + __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE); + + /* Enable the SPDIFRX CSRNE interrupt */ + __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE); + + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFRXEN) != SPDIFRX_STATE_RCV) + { + /* Start synchronization */ + __HAL_SPDIFRX_SYNC(hspdif); + + /* Wait until SYNCD flag is set */ + do + { + if (count == 0U) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt + process */ + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); + + hspdif->State = HAL_SPDIFRX_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_TIMEOUT; + } + count--; + } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET); + + /* Start reception */ + __HAL_SPDIFRX_RCV(hspdif); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data (Data Flow) mode with DMA + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data sample to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) +{ + uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); + + const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) + { + /* Process Locked */ + __HAL_LOCK(hspdif); + + hspdif->pRxBuffPtr = pData; + hspdif->RxXferSize = Size; + hspdif->RxXferCount = Size; + + hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; + hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX; + + /* Set the SPDIFRX Rx DMA Half transfer complete callback */ + hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt; + + /* Set the SPDIFRX Rx DMA transfer complete callback */ + hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt; + + /* Set the DMA error callback */ + hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError; + + /* Enable the DMA request */ + if ((hspdif->hdmaDrRx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hspdif->hdmaDrRx->LinkedListQueue != NULL) + { + hspdif->hdmaDrRx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t) Size * 4U; + hspdif->hdmaDrRx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t) &hspdif->Instance->DR; + hspdif->hdmaDrRx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t) hspdif->pRxBuffPtr; + + if (HAL_DMAEx_List_Start_IT(hspdif->hdmaDrRx) != HAL_OK) + { + /* Set SPDIFRX error */ + hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; + + /* Set SPDIFRX state */ + hspdif->State = HAL_SPDIFRX_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_ERROR; + } + } + else + { + /* Set SPDIFRX error */ + hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; + + /* Set SPDIFRX state */ + hspdif->State = HAL_SPDIFRX_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_ERROR; + } + } + else + { + if (HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, + (uint32_t) Size * 4U) != HAL_OK) + { + /* Set SPDIFRX error */ + hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; + + /* Set SPDIFRX state */ + hspdif->State = HAL_SPDIFRX_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_ERROR; + } + } + + /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/ + hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN; + + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFRXEN) != SPDIFRX_STATE_RCV) + { + /* Start synchronization */ + __HAL_SPDIFRX_SYNC(hspdif); + + /* Wait until SYNCD flag is set */ + do + { + if (count == 0U) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt + process */ + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); + + hspdif->State = HAL_SPDIFRX_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_TIMEOUT; + } + count--; + } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET); + + /* Start reception */ + __HAL_SPDIFRX_RCV(hspdif); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data (Control Flow) with DMA + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data (Control Flow) sample to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) +{ + uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); + + const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) + { + hspdif->pCsBuffPtr = pData; + hspdif->CsXferSize = Size; + hspdif->CsXferCount = Size; + + /* Process Locked */ + __HAL_LOCK(hspdif); + + hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; + hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX; + + /* Set the SPDIFRX Rx DMA Half transfer complete callback */ + hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt; + + /* Set the SPDIFRX Rx DMA transfer complete callback */ + hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt; + + /* Set the DMA error callback */ + hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError; + + /* Enable the DMA request */ + if ((hspdif->hdmaCsRx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hspdif->hdmaCsRx->LinkedListQueue != NULL) + { + hspdif->hdmaCsRx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t) Size * 4U; + hspdif->hdmaCsRx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t) &hspdif->Instance->CSR; + hspdif->hdmaCsRx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t) hspdif->pCsBuffPtr; + + if (HAL_DMAEx_List_Start_IT(hspdif->hdmaCsRx) != HAL_OK) + { + /* Set SPDIFRX error */ + hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; + + /* Set SPDIFRX state */ + hspdif->State = HAL_SPDIFRX_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_ERROR; + } + } + else + { + /* Set SPDIFRX error */ + hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; + + /* Set SPDIFRX state */ + hspdif->State = HAL_SPDIFRX_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_ERROR; + } + } + else + { + if (HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, + (uint32_t) Size * 4U) != HAL_OK) + { + /* Set SPDIFRX error */ + hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; + + /* Set SPDIFRX state */ + hspdif->State = HAL_SPDIFRX_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_ERROR; + } + } + + /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/ + hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN; + + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFRXEN) != SPDIFRX_STATE_RCV) + { + /* Start synchronization */ + __HAL_SPDIFRX_SYNC(hspdif); + + /* Wait until SYNCD flag is set */ + do + { + if (count == 0U) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt + process */ + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); + + hspdif->State = HAL_SPDIFRX_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_TIMEOUT; + } + count--; + } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET); + + /* Start reception */ + __HAL_SPDIFRX_RCV(hspdif); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief stop the audio stream receive from the Media. + * @param hspdif SPDIFRX handle + * @retval None + */ +HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif) +{ + /* Process Locked */ + __HAL_LOCK(hspdif); + + /* Disable the SPDIFRX DMA requests */ + hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN); + hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN); + + /* Disable the SPDIFRX DMA channel */ + if (hspdif->hdmaDrRx != NULL) + { + __HAL_DMA_DISABLE(hspdif->hdmaDrRx); + } + if (hspdif->hdmaCsRx != NULL) + { + __HAL_DMA_DISABLE(hspdif->hdmaCsRx); + } + + /* Disable SPDIFRX peripheral */ + __HAL_SPDIFRX_IDLE(hspdif); + + hspdif->State = HAL_SPDIFRX_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_OK; +} + +/** + * @brief This function handles SPDIFRX interrupt request. + * @param hspdif SPDIFRX handle + * @retval HAL status + */ +void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) +{ + uint32_t itFlag = hspdif->Instance->SR; + uint32_t itSource = hspdif->Instance->IMR; + + /* SPDIFRX in mode Data Flow Reception */ + if (((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource & SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE)) + { + __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE); + SPDIFRX_ReceiveDataFlow_IT(hspdif); + } + + /* SPDIFRX in mode Control Flow Reception */ + if (((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource & SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE)) + { + __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE); + SPDIFRX_ReceiveControlFlow_IT(hspdif); + } + + /* SPDIFRX Overrun error interrupt occurred */ + if (((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource & SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE)) + { + __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_OVRIE); + + /* Change the SPDIFRX error code */ + hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR; + + /* the transfer is not stopped */ + HAL_SPDIFRX_ErrorCallback(hspdif); + } + + /* SPDIFRX Parity error interrupt occurred */ + if (((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource & SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE)) + { + __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_PERRIE); + + /* Change the SPDIFRX error code */ + hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE; + + /* the transfer is not stopped */ + HAL_SPDIFRX_ErrorCallback(hspdif); + } +} + +/** + * @brief Rx Transfer (Data flow) half completed callbacks + * @param hspdif SPDIFRX handle + * @retval None + */ +__weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspdif); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer (Data flow) completed callbacks + * @param hspdif SPDIFRX handle + * @retval None + */ +__weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspdif); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx (Control flow) Transfer half completed callbacks + * @param hspdif SPDIFRX handle + * @retval None + */ +__weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspdif); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer (Control flow) completed callbacks + * @param hspdif SPDIFRX handle + * @retval None + */ +__weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspdif); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief SPDIFRX error callbacks + * @param hspdif SPDIFRX handle + * @retval None + */ +__weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspdif); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPDIFRX_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State functions + * +@verbatim +=============================================================================== +##### Peripheral State and Errors functions ##### +=============================================================================== +[..] +This subsection permit to get in run-time the status of the peripheral +and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the SPDIFRX state + * @param hspdif SPDIFRX handle + * @retval HAL state + */ +HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif) +{ + return hspdif->State; +} + +/** + * @brief Return the SPDIFRX error code + * @param hspdif SPDIFRX handle + * @retval SPDIFRX Error Code + */ +uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif) +{ + return hspdif->ErrorCode; +} + +/** + * @} + */ + +/** + * @brief DMA SPDIFRX receive process (Data flow) complete callback + * @param hdma DMA handle + * @retval None + */ +static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) +{ + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable Rx DMA Request */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN); + hspdif->RxXferCount = 0; + hspdif->State = HAL_SPDIFRX_STATE_READY; + } +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) + hspdif->RxCpltCallback(hspdif); +#else + HAL_SPDIFRX_RxCpltCallback(hspdif); +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPDIFRX receive process (Data flow) half complete callback + * @param hdma DMA handle + * @retval None + */ +static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) + hspdif->RxHalfCpltCallback(hspdif); +#else + HAL_SPDIFRX_RxHalfCpltCallback(hspdif); +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA SPDIFRX receive process (Control flow) complete callback + * @param hdma DMA handle + * @retval None + */ +static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) +{ + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable Cb DMA Request */ + hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN); + hspdif->CsXferCount = 0; + + hspdif->State = HAL_SPDIFRX_STATE_READY; +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) + hspdif->CxCpltCallback(hspdif); +#else + HAL_SPDIFRX_CxCpltCallback(hspdif); +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPDIFRX receive process (Control flow) half complete callback + * @param hdma DMA handle + * @retval None + */ +static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) +{ + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) + hspdif->CxHalfCpltCallback(hspdif); +#else + HAL_SPDIFRX_CxHalfCpltCallback(hspdif); +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPDIFRX communication error callback + * @param hdma DMA handle + * @retval None + */ +static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma) +{ + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable Rx and Cb DMA Request */ + hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN)); + hspdif->RxXferCount = 0; + + hspdif->State = HAL_SPDIFRX_STATE_READY; + + /* Set the error code and execute error callback*/ + hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA; + +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) + /* The transfer is not stopped */ + hspdif->ErrorCallback(hspdif); +#else + /* The transfer is not stopped */ + HAL_SPDIFRX_ErrorCallback(hspdif); +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ +} + +/** + * @brief Receive an amount of data (Data Flow) with Interrupt + * @param hspdif SPDIFRX handle + * @retval None + */ +static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) +{ + /* Receive data */ + (*hspdif->pRxBuffPtr) = hspdif->Instance->DR; + hspdif->pRxBuffPtr++; + hspdif->RxXferCount--; + + if (hspdif->RxXferCount == 0U) + { + /* Disable RXNE/PE and OVR interrupts */ + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE); + + hspdif->State = HAL_SPDIFRX_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) + hspdif->RxCpltCallback(hspdif); +#else + HAL_SPDIFRX_RxCpltCallback(hspdif); +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Receive an amount of data (Control Flow) with Interrupt + * @param hspdif SPDIFRX handle + * @retval None + */ +static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) +{ + /* Receive data */ + (*hspdif->pCsBuffPtr) = hspdif->Instance->CSR; + hspdif->pCsBuffPtr++; + hspdif->CsXferCount--; + + if (hspdif->CsXferCount == 0U) + { + /* Disable CSRNE interrupt */ + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); + + hspdif->State = HAL_SPDIFRX_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + +#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) + hspdif->CxCpltCallback(hspdif); +#else + HAL_SPDIFRX_CxCpltCallback(hspdif); +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ + } +} + +/** + * @brief This function handles SPDIFRX Communication Timeout. + * @param hspdif SPDIFRX handle + * @param Flag Flag checked + * @param Status Value of the flag expected + * @param Timeout Duration of the timeout + * @param tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, + FlagStatus Status, uint32_t Timeout, uint32_t tickstart) +{ + /* Wait until flag is set */ + while (__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt + process */ + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); + __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); + + hspdif->State = HAL_SPDIFRX_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspdif); + + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @} + */ + + +#endif /* SPDIFRX */ +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_spi.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_spi.c new file mode 100644 index 00000000000..5c5f00c3640 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_spi.c @@ -0,0 +1,3796 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_spi.c + * @author MCD Application Team + * @brief SPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process or DMA process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Stream/Channel + (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel + + (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SPI_MspInit() API. + [..] + Callback registration: + + (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1UL + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. + + Function HAL_SPI_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : SPI Tx Completed callback + (+) RxCpltCallback : SPI Rx Completed callback + (+) TxRxCpltCallback : SPI TxRx Completed callback + (+) TxHalfCpltCallback : SPI Tx Half Completed callback + (+) RxHalfCpltCallback : SPI Rx Half Completed callback + (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (+) ErrorCallback : SPI Error callback + (+) AbortCpltCallback : SPI Abort callback + (+) SuspendCallback : SPI Suspend callback + (+) MspInitCallback : SPI Msp Init callback + (+) MspDeInitCallback : SPI Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default + weak function. + HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : SPI Tx Completed callback + (+) RxCpltCallback : SPI Rx Completed callback + (+) TxRxCpltCallback : SPI TxRx Completed callback + (+) TxHalfCpltCallback : SPI Tx Half Completed callback + (+) RxHalfCpltCallback : SPI Rx Half Completed callback + (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (+) ErrorCallback : SPI Error callback + (+) AbortCpltCallback : SPI Abort callback + (+) SuspendCallback : SPI Suspend callback + (+) MspInitCallback : SPI Msp Init callback + (+) MspDeInitCallback : SPI Msp DeInit callback + + By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() + or HAL_SPI_Init() function. + + When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + SuspendCallback restriction: + SuspendCallback is called only when MasterReceiverAutoSusp is enabled and + EOT interrupt is activated. SuspendCallback is used in relation with functions + HAL_SPI_Transmit_IT, HAL_SPI_Receive_IT and HAL_SPI_TransmitReceive_IT. + + [..] + Circular mode restriction: + (+) The DMA circular mode cannot be used when the SPI is configured in these modes: + (++) Master 2Lines RxOnly + (++) Master 1Line Rx + (+) The CRC feature is not managed when the DMA circular mode is enabled + (+) The functions HAL_SPI_DMAPause()/ HAL_SPI_DMAResume() are not supported. Return always + HAL_ERROR with ErrorCode set to HAL_SPI_ERROR_NOT_SUPPORTED. + Those functions are maintained for backward compatibility reasons. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_DEFAULT_TIMEOUT 100UL +#define MAX_FIFO_LENGTH 16UL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, + FlagStatus FlagStatus, uint32_t Timeout, uint32_t Tickstart); +static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi); +static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi); +static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi); +static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi); +static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi); +static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi); +static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi); +static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi); + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + (++) CRC Length, used only with Data8 and Data16 + (++) FIFO reception threshold + (++) FIFO transmission threshold + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the SPI according to the specified parameters + * in the SPI_InitTypeDef and initialize the associated handle. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + uint32_t crc_length; + uint32_t packet_length; + + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_LIMITED_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); + } + else + { + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); + } + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + } +#if (USE_SPI_CRC != 0UL) + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_CRC_LENGTH(hspi->Init.CRCLength)); + } + else + { + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + } + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern)); + assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; +#endif /* USE_SPI_CRC */ + + assert_param(IS_SPI_RDY_MASTER_MANAGEMENT(hspi->Init.ReadyMasterManagement)); + assert_param(IS_SPI_RDY_POLARITY(hspi->Init.ReadyPolarity)); + assert_param(IS_SPI_MASTER_RX_AUTOSUSP(hspi->Init.MasterReceiverAutoSusp)); + + /* Verify that the SPI instance supports Data Size higher than 16bits */ + if ((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT)) + { + return HAL_ERROR; + } + + /* Verify that the SPI instance supports requested data packing */ + packet_length = SPI_GetPacketSize(hspi); + if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (packet_length > SPI_LOWEND_FIFO_SIZE)) || + ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (packet_length > SPI_HIGHEND_FIFO_SIZE))) + { + return HAL_ERROR; + } +#if (USE_SPI_CRC != 0UL) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Verify that the SPI instance supports CRC Length higher than 16bits */ + if ((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (hspi->Init.CRCLength > SPI_CRC_LENGTH_16BIT)) + { + return HAL_ERROR; + } + + /* Align the CRC Length on the data size */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + { + crc_length = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) << SPI_CFG1_CRCSIZE_Pos; + } + else + { + crc_length = hspi->Init.CRCLength; + } + + /* Verify that the CRC Length is higher than DataSize */ + if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos)) + { + return HAL_ERROR; + } + } + else + { + crc_length = hspi->Init.DataSize << SPI_CFG1_CRCSIZE_Pos; + } +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + /* Init the SPI Callback settings */ + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ + + if (hspi->MspInitCallback == NULL) + { + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + +#if (USE_SPI_CRC == 0) + /* Keep the default value of CRCSIZE in case of CRC is not used */ + crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE; +#endif /* USE_SPI_CRC */ + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, + Communication speed, First bit, CRC calculation state, CRC Length */ + + /* SPIx NSS Software Management Configuration */ + if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && \ + (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \ + ((hspi->Init.Mode == SPI_MODE_SLAVE) && \ + (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH)))) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI); + } + + /* SPIx Master Rx Auto Suspend Configuration */ + if (((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) && (hspi->Init.DataSize >= SPI_DATASIZE_8BIT)) + { + MODIFY_REG(hspi->Instance->CR1, SPI_CR1_MASRX, hspi->Init.MasterReceiverAutoSusp); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_MASRX); + } + + /* SPIx CFG1 Configuration */ + WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length | + hspi->Init.FifoThreshold | hspi->Init.DataSize)); + + /* SPIx CFG2 Configuration */ + WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | + hspi->Init.NSSPolarity | hspi->Init.NSS | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | + hspi->Init.FirstBit | hspi->Init.Mode | + hspi->Init.MasterInterDataIdleness | hspi->Init.Direction | + hspi->Init.MasterSSIdleness | hspi->Init.IOSwap | + hspi->Init.ReadyMasterManagement | hspi->Init.ReadyPolarity)); + +#if (USE_SPI_CRC != 0UL) + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Initialize TXCRC Pattern Initial Value */ + if (hspi->Init.TxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI); + } + + /* Initialize RXCRC Pattern Initial Value */ + if (hspi->Init.RxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI); + } + + /* Enable 33/17 bits CRC computation */ + if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) || + ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT))) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); + } + + /* Write CRC polynomial in SPI Register */ + WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); + } +#endif /* USE_SPI_CRC */ + + /* Insure that Underrun configuration is managed only by Salve */ + if (hspi->Init.Mode == SPI_MODE_SLAVE) + { +#if (USE_SPI_CRC != 0UL) + MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG); +#endif /* USE_SPI_CRC */ + } + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ + + /* Insure that AFCNTR is managed only by Master */ + if ((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) + { + /* Alternate function GPIOs control */ + MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState)); + } + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-Initialize the SPI peripheral. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check SPI Instance parameter */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + if (hspi->MspDeInitCallback == NULL) + { + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hspi->MspDeInitCallback(hspi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Initialize the SPI MSP. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspInit should be implemented in the user file + */ +} + +/** + * @brief De-Initialize the SPI MSP. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit should be implemented in the user file + */ +} + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +/** + * @brief Register a User SPI Callback + * To be used instead of the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Lock the process */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = pCallback; + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = pCallback; + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = pCallback; + break; + + case HAL_SPI_SUSPEND_CB_ID : + hspi->SuspendCallback = pCallback; + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} + +/** + * @brief Unregister an SPI Callback + * SPI callback is redirected to the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be unregistered + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Lock the process */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SPI_SUSPEND_CB_ID : + hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (##) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (##) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData : pointer to data buffer + * @param Size : amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); +#endif /* __GNUC__ */ + + uint32_t tickstart; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + __HAL_UNLOCK(hspi); + return errorcode; + } + + if ((pData == NULL) || (Size == 0UL)) + { + errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = (uint16_t) 0UL; + hspi->RxXferCount = (uint16_t) 0UL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + else + { + SPI_2LINES_TX(hspi); + } + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Transmit data in 32 Bit mode */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + /* Transmit data in 32 Bit mode */ + while (hspi->TxXferCount > 0UL) + { + /* Wait until TXP flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + return HAL_TIMEOUT; + } + } + } + } + /* Transmit data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0UL) + { + /* Wait until TXP flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) + { + if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount -= (uint16_t)2UL; + } + else + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + return HAL_TIMEOUT; + } + } + } + } + /* Transmit data in 8 Bit mode */ + else + { + while (hspi->TxXferCount > 0UL) + { + /* Wait until TXP flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) + { + if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount -= (uint16_t)4UL; + } + else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= (uint16_t)2UL; + } + else + { + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + return HAL_TIMEOUT; + } + } + } + } + + /* Wait for Tx (and CRC) data to be sent */ + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + hspi->State = HAL_SPI_STATE_READY; + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + return errorcode; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData : pointer to data buffer + * @param Size : amount of data to be received + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + HAL_StatusTypeDef errorcode = HAL_OK; +#if defined (__GNUC__) + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); +#endif /* __GNUC__ */ + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + __HAL_UNLOCK(hspi); + return errorcode; + } + + if ((pData == NULL) || (Size == 0UL)) + { + errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + hspi->RxISR = NULL; + hspi->TxISR = NULL; + + /* Configure communication direction: 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else + { + SPI_2LINES_RX(hspi); + } + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Receive data in 32 Bit mode */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + /* Transfer loop */ + while (hspi->RxXferCount > 0UL) + { + /* Check the RXWNE/EOT flag */ + if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + return HAL_TIMEOUT; + } + } + } + } + /* Receive data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Transfer loop */ + while (hspi->RxXferCount > 0UL) + { + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + return HAL_TIMEOUT; + } + } + } + } + /* Receive data in 8 Bit mode */ + else + { + /* Transfer loop */ + while (hspi->RxXferCount > 0UL) + { + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + return HAL_TIMEOUT; + } + } + } + } + +#if (USE_SPI_CRC != 0UL) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait for crc data to be received */ + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + } +#endif /* USE_SPI_CRC */ + + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + hspi->State = HAL_SPI_STATE_READY; + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + return errorcode; +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @param Size : amount of data to be sent and received + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef errorcode = HAL_OK; +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); +#endif /* __GNUC__ */ + + uint32_t tickstart; + uint16_t initial_TxXferCount; + uint16_t initial_RxXferCount; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + initial_TxXferCount = Size; + initial_RxXferCount = Size; + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + __HAL_UNLOCK(hspi); + return errorcode; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) + { + errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferCount = Size; + hspi->RxXferSize = Size; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferCount = Size; + hspi->TxXferSize = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + __HAL_SPI_ENABLE(hspi); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Transmit and Receive data in 32 Bit mode */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) + { + /* Check TXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL)) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount --; + initial_TxXferCount = hspi->TxXferCount; + } + + /* Check RXWNE/EOT flag */ + if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) && (initial_RxXferCount > 0UL)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount --; + initial_RxXferCount = hspi->RxXferCount; + } + + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + return HAL_TIMEOUT; + } + } + } + /* Transmit and Receive data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) + { + /* Check the TXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP) && (initial_TxXferCount > 0UL)) + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + initial_TxXferCount = hspi->TxXferCount; + } + + /* Check the RXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + return HAL_TIMEOUT; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) + { + /* Check the TXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL)) + { + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + initial_TxXferCount = hspi->TxXferCount; + } + + /* Check the RXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + return HAL_TIMEOUT; + } + } + } + + /* Wait for Tx/Rx (and CRC) data to be sent/received */ + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + hspi->State = HAL_SPI_STATE_READY; + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + return errorcode; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + + /* Lock the process */ + __HAL_LOCK(hspi); + + if ((pData == NULL) || (Size == 0UL)) + { + errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return errorcode; + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = (uint16_t) 0UL; + hspi->RxXferCount = (uint16_t) 0UL; + hspi->RxISR = NULL; + + /* Set the function for IT treatment */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + hspi->TxISR = SPI_TxISR_32BIT; + } + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + else + { + SPI_2LINES_TX(hspi); + } + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + /* Enable EOT, TXP, FRE, MODF and UDR interrupts */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + + /* Lock the process */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + __HAL_UNLOCK(hspi); + return errorcode; + } + + if ((pData == NULL) || (Size == 0UL)) + { + errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + hspi->TxISR = NULL; + + /* Set the function for IT treatment */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + hspi->RxISR = SPI_RxISR_32BIT; + } + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_RxISR_16BIT; + } + else + { + hspi->RxISR = SPI_RxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else + { + SPI_2LINES_RX(hspi); + } + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + /* Enable EOT, RXP, OVR, FRE and MODF interrupts */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @param Size : amount of data to be sent and received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + uint32_t tmp_TxXferCount; + +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); +#endif /* __GNUC__ */ + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Lock the process */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + __HAL_UNLOCK(hspi); + return errorcode; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) + { + errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + tmp_TxXferCount = hspi->TxXferCount; + + /* Set the function for IT treatment */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + hspi->TxISR = SPI_TxISR_32BIT; + hspi->RxISR = SPI_RxISR_32BIT; + } + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_RxISR_16BIT; + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->RxISR = SPI_RxISR_8BIT; + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + /* Fill in the TxFIFO */ + while ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (tmp_TxXferCount != 0UL)) + { + /* Transmit data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + /* Transmit data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + /* Transmit data in 8 Bit mode */ + else + { + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + } + + /* Enable EOT, DXP, UDR, OVR, FRE and MODF interrupts */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Start Master transfer */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + return errorcode; +} + + + + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + + /* Lock the process */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + __HAL_UNLOCK(hspi); + return errorcode; + } + + if ((pData == NULL) || (Size == 0UL)) + { + errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = NULL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + hspi->RxXferSize = (uint16_t)0UL; + hspi->RxXferCount = (uint16_t)0UL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + else + { + SPI_2LINES_TX(hspi); + } + + /* Packing mode management is enabled by the DMA settings */ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.SrcDataWidth != DMA_SRC_DATAWIDTH_WORD) && \ + (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE))) + { + /* Restriction the DMA data received is not allowed in this mode */ + errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Adjust XferCount according to DMA alignment / Data size */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL; + } + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + } + else + { + /* Adjustment done */ + } + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Clear TXDMAEN bit*/ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); + + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + hspi->TxXferCount = Size; + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + hspi->TxXferCount = Size * 2U; + } + else + { + hspi->TxXferCount = Size * 4U; + } + + /* Enable the Tx DMA Stream/Channel */ + if ((hspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hspi->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->TxXferCount; + + /* Set DMA source address */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hspi->pTxBuffPtr; + + /* Set DMA destination address */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR; + + errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmatx); + } + else + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + hspi->State = HAL_SPI_STATE_READY; + errorcode = HAL_ERROR; + return errorcode; + } + } + else + { + errorcode = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount); + } + + /* Check status */ + if (errorcode != HAL_OK) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + hspi->State = HAL_SPI_STATE_READY; + errorcode = HAL_ERROR; + return errorcode; + } + + /* Set the number of data at current transfer */ + if (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL); + } + else + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + } + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + + /* Lock the process */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + __HAL_UNLOCK(hspi); + return errorcode; + } + + if ((pData == NULL) || (Size == 0UL)) + { + errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + hspi->TxXferSize = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else + { + SPI_2LINES_RX(hspi); + } + + /* Packing mode management is enabled by the DMA settings */ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \ + (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) + { + /* Restriction the DMA data received is not allowed in this mode */ + errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Clear RXDMAEN bit */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); + + /* Adjust XferCount according to DMA alignment / Data size */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_HALFWORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL; + } + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + } + else + { + /* Adjustment done */ + } + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + hspi->RxXferCount = Size; + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + hspi->RxXferCount = Size * 2U; + } + else + { + hspi->RxXferCount = Size * 4U; + } + + /* Enable the Rx DMA Stream/Channel */ + if ((hspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hspi->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->RxXferCount; + + /* Set DMA source address */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->RXDR; + + /* Set DMA destination address */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr; + + errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmarx); + } + else + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + hspi->State = HAL_SPI_STATE_READY; + errorcode = HAL_ERROR; + return errorcode; + } + } + else + { + errorcode = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount); + } + + /* Check status */ + if (errorcode != HAL_OK) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + hspi->State = HAL_SPI_STATE_READY; + errorcode = HAL_ERROR; + return errorcode; + } + + /* Set the number of data at current transfer */ + if (hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL); + } + else + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + } + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @param Size : amount of data to be sent + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + HAL_StatusTypeDef errorcode; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Lock the process */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + __HAL_UNLOCK(hspi); + return errorcode; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) + { + errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + + /* Reset the Tx/Rx DMA bits */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Packing mode management is enabled by the DMA settings */ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \ + (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) + { + /* Restriction the DMA data received is not allowed in this mode */ + errorcode = HAL_ERROR; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Adjust XferCount according to DMA alignment / Data size */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL; + } + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_HALFWORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL; + } + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + } + else + { + /* Adjustment done */ + } + + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + hspi->RxXferCount = Size; + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + hspi->RxXferCount = Size * 2U; + } + else + { + hspi->RxXferCount = Size * 4U; + } + /* Enable the Rx DMA Stream/Channel */ + if ((hspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hspi->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->RxXferCount; + + /* Set DMA source address */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->RXDR; + + /* Set DMA destination address */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr; + + errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmarx); + } + else + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + hspi->State = HAL_SPI_STATE_READY; + errorcode = HAL_ERROR; + return errorcode; + } + } + else + { + errorcode = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount); + } + + /* Check status */ + if (errorcode != HAL_OK) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + hspi->State = HAL_SPI_STATE_READY; + errorcode = HAL_ERROR; + return errorcode; + } + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + hspi->hdmatx->XferHalfCpltCallback = NULL; + hspi->hdmatx->XferCpltCallback = NULL; + hspi->hdmatx->XferAbortCallback = NULL; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + hspi->TxXferCount = Size; + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + hspi->TxXferCount = Size * 2U; + } + else + { + hspi->TxXferCount = Size * 4U; + } + + /* Enable the Tx DMA Stream/Channel */ + if ((hspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hspi->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->TxXferCount; + + /* Set DMA source address */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hspi->pTxBuffPtr; + + /* Set DMA destination address */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR; + + errorcode = HAL_DMAEx_List_Start_IT(hspi->hdmatx); + } + else + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + hspi->State = HAL_SPI_STATE_READY; + errorcode = HAL_ERROR; + return errorcode; + } + } + else + { + errorcode = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount); + } + + /* Check status */ + if (errorcode != HAL_OK) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + hspi->State = HAL_SPI_STATE_READY; + errorcode = HAL_ERROR; + return errorcode; + } + + if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) && (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)) + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL); + } + else + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + } + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Abort ongoing transfer (blocking mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * @note This procedure performs following operations : + * + Disable SPI Interrupts (depending of transfer direction) + * + Disable the DMA transfer in the peripheral register (if enabled) + * + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * + Set handle State to READY. + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + + __IO uint32_t count; + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set hspi->state to aborting to avoid any interaction */ + hspi->State = HAL_SPI_STATE_ABORT; + + /* Initialized local variable */ + errorcode = HAL_OK; + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); + + /* If master communication on going, make sure current frame is done before closing the connection */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + + /* Request a Suspend transfer */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + + /* Clear SUSP flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) + { + if (hspi->hdmatx != NULL) + { + /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + } + } + + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + if (hspi->hdmarx != NULL) + { + /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + } + } + + /* Proceed with abort procedure */ + SPI_AbortTransfer(hspi); + + /* Check error during Abort procedure */ + if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT)) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + return errorcode; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * @note This procedure performs following operations : + * + Disable SPI Interrupts (depending of transfer direction) + * + Disable the DMA transfer in the peripheral register (if enabled) + * + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * + Set handle State to READY + * + At abort completion, call user abort complete callback. + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + __IO uint32_t count; + uint32_t dma_tx_abort_done = 1UL; + uint32_t dma_rx_abort_done = 1UL; + + /* Set hspi->state to aborting to avoid any interaction */ + hspi->State = HAL_SPI_STATE_ABORT; + + /* Initialized local variable */ + errorcode = HAL_OK; + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); + + /* If master communication on going, make sure current frame is done before closing the connection */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + + /* Request a Suspend transfer */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + + /* Clear SUSP flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); + } + + /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized + before any call to DMA Abort functions */ + + if (hspi->hdmatx != NULL) + { + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) + { + /* Set DMA Abort Complete callback if SPI DMA Tx request if enabled */ + hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; + + dma_tx_abort_done = 0UL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_NO_XFER) + { + dma_tx_abort_done = 1UL; + hspi->hdmatx->XferAbortCallback = NULL; + } + } + } + else + { + hspi->hdmatx->XferAbortCallback = NULL; + } + } + + if (hspi->hdmarx != NULL) + { + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */ + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + + dma_rx_abort_done = 0UL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_NO_XFER) + { + dma_rx_abort_done = 1UL; + hspi->hdmarx->XferAbortCallback = NULL; + } + } + } + else + { + hspi->hdmarx->XferAbortCallback = NULL; + } + } + + /* If no running DMA transfer, finish cleanup and call callbacks */ + if ((dma_tx_abort_done == 1UL) && (dma_rx_abort_done == 1UL)) + { + /* Proceed with abort procedure */ + SPI_AbortTransfer(hspi); + + /* Check error during Abort procedure */ + if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT)) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + return errorcode; +} + +/** + * @brief Pause the DMA Transfer. + * This API is not supported, it is maintained for backward compatibility. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL_ERROR + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Set error code to not supported */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED); + + return HAL_ERROR; +} + +/** + * @brief Resume the DMA Transfer. + * This API is not supported, it is maintained for backward compatibility. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL_ERROR + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Set error code to not supported */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED); + + return HAL_ERROR; +} + +/** + * @brief Stop the DMA Transfer. + * This API is not supported, it is maintained for backward compatibility. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL_ERROR + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + /* Set error code to not supported */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED); + + return HAL_ERROR; +} + +/** + * @brief Handle SPI interrupt request. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + uint32_t itsource = hspi->Instance->IER; + uint32_t itflag = hspi->Instance->SR; + uint32_t trigger = itsource & itflag; + uint32_t cfg1 = hspi->Instance->CFG1; + uint32_t handled = 0UL; + + HAL_SPI_StateTypeDef State = hspi->State; +#if defined (__GNUC__) + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); +#endif /* __GNUC__ */ + + /* SPI in SUSPEND mode ----------------------------------------------------*/ + if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT)) + { + /* Clear the Suspend flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + + /* Suspend on going, Call the Suspend callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->SuspendCallback(hspi); +#else + HAL_SPI_SuspendCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + + /* SPI in mode Transmitter and Receiver ------------------------------------*/ + if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \ + HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP)) + { + hspi->TxISR(hspi); + hspi->RxISR(hspi); + handled = 1UL; + } + + /* SPI in mode Receiver ----------------------------------------------------*/ + if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && \ + HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP)) + { + hspi->RxISR(hspi); + handled = 1UL; + } + + /* SPI in mode Transmitter -------------------------------------------------*/ + if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && \ + HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP)) + { + hspi->TxISR(hspi); + handled = 1UL; + } + + + if (handled != 0UL) + { + return; + } + + /* SPI End Of Transfer: DMA or IT based transfer */ + if (HAL_IS_BIT_SET(trigger, SPI_FLAG_EOT)) + { + /* Clear EOT/TXTF/SUSP flag */ + __HAL_SPI_CLEAR_EOTFLAG(hspi); + __HAL_SPI_CLEAR_TXTFFLAG(hspi); + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + + /* For the IT based receive extra polling maybe required for last packet */ + if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) + { + /* Pooling remaining data */ + while (hspi->RxXferCount != 0UL) + { + /* Receive data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + } + /* Receive data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + } + /* Receive data in 8 Bit mode */ + else + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + } + + hspi->RxXferCount--; + } + } + + /* Call SPI Standard close procedure */ + SPI_CloseTransfer(hspi); + + hspi->State = HAL_SPI_STATE_READY; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + /* Call appropriate user callback */ + if (State == HAL_SPI_STATE_BUSY_TX_RX) + { + hspi->TxRxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_RX) + { + hspi->RxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_TX) + { + hspi->TxCpltCallback(hspi); + } +#else + /* Call appropriate user callback */ + if (State == HAL_SPI_STATE_BUSY_TX_RX) + { + HAL_SPI_TxRxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_RX) + { + HAL_SPI_RxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_TX) + { + HAL_SPI_TxCpltCallback(hspi); + } +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + else + { + /* End of the appropriate call */ + } + + return; + } + + /* SPI in Error Treatment --------------------------------------------------*/ + if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != 0UL) + { + /* SPI Overrun error interrupt occurred ----------------------------------*/ + if ((trigger & SPI_FLAG_OVR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if ((trigger & SPI_FLAG_MODF) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + if ((trigger & SPI_FLAG_FRE) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + __HAL_SPI_CLEAR_FREFLAG(hspi); + } + + /* SPI Underrun error interrupt occurred ------------------------------------*/ + if ((trigger & SPI_FLAG_UDR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR); + __HAL_SPI_CLEAR_UDRFLAG(hspi); + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable all interrupts */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF | + SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR)); + + /* Disable the SPI DMA requests if enabled */ + if (HAL_IS_BIT_SET(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) + { + /* Disable the SPI DMA requests */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Abort the SPI DMA Rx channel */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + /* Abort the SPI DMA Tx channel */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + } + else + { + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Half Transfer callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief SPI error callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback should be implemented in the user file + */ + /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred + */ +} + +/** + * @brief SPI Abort Complete callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief SPI Suspend callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_SuspendCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI handle state. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) +{ + /* Return SPI handle state */ + return hspi->State; +} + +/** + * @brief Return the SPI error code. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI error code in bitmap format + */ +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) +{ + /* Return SPI ErrorCode */ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief DMA SPI transmit process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hspi->State != HAL_SPI_STATE_ABORT) + { + if (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Enable EOT interrupt */ + __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); + } + } +} + +/** + * @brief DMA SPI receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hspi->State != HAL_SPI_STATE_ABORT) + { + if (hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Enable EOT interrupt */ + __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); + } + } +} + +/** + * @brief DMA SPI transmit receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hspi->State != HAL_SPI_STATE_ABORT) + { + if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) && + (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Enable EOT interrupt */ + __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); + } + } +} + +/** + * @brief DMA SPI half transmit process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxHalfCpltCallback(hspi); +#else + HAL_SPI_TxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->RxHalfCpltCallback(hspi); +#else + HAL_SPI_RxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxRxHalfCpltCallback(hspi); +#else + HAL_SPI_TxRxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication error callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* if DMA error is FIFO error ignore it */ + if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_NONE) + { + /* Call SPI standard close procedure */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA SPI communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + hspi->RxXferCount = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hspi->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmarx != NULL) + { + if (hspi->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* Call the Abort procedure */ + SPI_AbortTransfer(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hspi->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmatx != NULL) + { + if (hspi->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* Call the Abort procedure */ + SPI_AbortTransfer(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief Manage the receive 8-bit in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8 Bit mode */ + *((uint8_t *)hspi->pRxBuffPtr) = (*(__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->RxXferCount == 0UL) + { + /* Disable RXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); + } +} + + +/** + * @brief Manage the 16-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ +#if defined (__GNUC__) + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); + + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = (*(__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->RxXferCount == 0UL) + { + /* Disable RXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); + } +} + + +/** + * @brief Manage the 32-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 32 Bit mode */ + *((uint32_t *)hspi->pRxBuffPtr) = (*(__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->RxXferCount == 0UL) + { + /* Disable RXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); + } +} + + +/** + * @brief Handle the data 8-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 8 Bit mode */ + *(__IO uint8_t *)&hspi->Instance->TXDR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->TxXferCount == 0UL) + { + /* Disable TXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); + } +} + +/** + * @brief Handle the data 16-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); + + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->TxXferCount == 0UL) + { + /* Disable TXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); + } +} + +/** + * @brief Handle the data 32-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 32 Bit mode */ + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->TxXferCount == 0UL) + { + /* Disable TXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); + } +} + +/** + * @brief Abort Transfer and clear flags. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi) +{ + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable ITs */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \ + SPI_IT_FRE | SPI_IT_MODF)); + + /* Clear the Status flags in the SR register */ + __HAL_SPI_CLEAR_EOTFLAG(hspi); + __HAL_SPI_CLEAR_TXTFFLAG(hspi); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_UDRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + +#if (USE_SPI_CRC != 0U) + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +#endif /* USE_SPI_CRC */ + + hspi->TxXferCount = (uint16_t)0UL; + hspi->RxXferCount = (uint16_t)0UL; +} + + +/** + * @brief Close Transfer and clear flags. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL_ERROR: if any error detected + * HAL_OK: if nothing detected + */ +static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi) +{ + uint32_t itflag = hspi->Instance->SR; + + __HAL_SPI_CLEAR_EOTFLAG(hspi); + __HAL_SPI_CLEAR_TXTFFLAG(hspi); + + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable ITs */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \ + SPI_IT_FRE | SPI_IT_MODF)); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Report UnderRun error for non RX Only communication */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + if ((itflag & SPI_FLAG_UDR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR); + __HAL_SPI_CLEAR_UDRFLAG(hspi); + } + } + + /* Report OverRun error for non TX Only communication */ + if (hspi->State != HAL_SPI_STATE_BUSY_TX) + { + if ((itflag & SPI_FLAG_OVR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + +#if (USE_SPI_CRC != 0UL) + /* Check if CRC error occurred */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + if ((itflag & SPI_FLAG_CRCERR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } +#endif /* USE_SPI_CRC */ + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if ((itflag & SPI_FLAG_MODF) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + if ((itflag & SPI_FLAG_FRE) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + __HAL_SPI_CLEAR_FREFLAG(hspi); + } + + hspi->TxXferCount = (uint16_t)0UL; + hspi->RxXferCount = (uint16_t)0UL; +} + +/** + * @brief Handle SPI Communication Timeout. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag: SPI flag to check + * @param Status: flag state to check + * @param Timeout: Timeout duration + * @param Tickstart: Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + /* Wait until flag is set */ + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if ((((HAL_GetTick() - Tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Compute configured packet size from fifo perspective. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval Packet size occupied in the fifo + */ +static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi) +{ + uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL; + uint32_t data_size = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) + 1UL; + + /* Convert data size to Byte */ + data_size = (data_size + 7UL) / 8UL; + + return data_size * fifo_threashold; +} + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_spi_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_spi_ex.c new file mode 100644 index 00000000000..8344ce57e00 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_spi_ex.c @@ -0,0 +1,228 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_spi_ex.c + * @author MCD Application Team + * @brief Extended SPI HAL module driver. + * This file provides firmware functions to manage the following + * SPI peripheral extended functionalities : + * + IO operation functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup SPIEx SPIEx + * @brief SPI Extended HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions + * @{ + */ + +/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of extended functions to manage the SPI + data transfers. + + (#) SPIEx function: + (++) HAL_SPIEx_FlushRxFifo() + (++) HAL_SPIEx_FlushRxFifo() + (++) HAL_SPIEx_EnableLockConfiguration() + (++) HAL_SPIEx_ConfigureUnderrun() + +@endverbatim + * @{ + */ + +/** + * @brief Flush the RX fifo. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi) +{ + uint8_t count = 0; + uint32_t itflag = hspi->Instance->SR; + __IO uint32_t tmpreg; + + while (((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_RX_FIFO_0PACKET) || ((itflag & SPI_FLAG_RXWNE) != 0UL)) + { + count += (uint8_t)4UL; + tmpreg = hspi->Instance->RXDR; + UNUSED(tmpreg); /* To avoid GCC warning */ + + if (IS_SPI_FULL_INSTANCE(hspi->Instance)) + { + if (count > SPI_HIGHEND_FIFO_SIZE) + { + return HAL_TIMEOUT; + } + } + else + { + if (count > SPI_LOWEND_FIFO_SIZE) + { + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + + +/** + * @brief Enable the Lock for the AF configuration of associated IOs + * and write protect the Content of Configuration register 2 + * when SPI is enabled + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Check if the SPI is disabled to edit IOLOCK bit */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK); + } + else + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Configure the UNDERRUN condition and behavior of slave transmitter. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param UnderrunDetection : Detection of underrun condition at slave transmitter + * This parameter is not supported in this SPI version. + * It is kept in order to not break the compatibility. + * @param UnderrunBehaviour : Behavior of slave transmitter at underrun condition + * This parameter can be a value of @ref SPI_Underrun_Behaviour. + * @retval None + */ +HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, + uint32_t UnderrunBehaviour) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(UnderrunDetection); + + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Check State and Insure that Underrun configuration is managed only by Salve */ + if ((hspi->State != HAL_SPI_STATE_READY) || (hspi->Init.Mode != SPI_MODE_SLAVE)) + { + errorcode = HAL_BUSY; + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Check the parameters */ + assert_param(IS_SPI_UNDERRUN_BEHAVIOUR(UnderrunBehaviour)); + + /* Check if the SPI is disabled to edit CFG1 register */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Configure Underrun fields */ + MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour); + } + else + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Configure Underrun fields */ + MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sram.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sram.c new file mode 100644 index 00000000000..6eada9574f1 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sram.c @@ -0,0 +1,1236 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_sram.c + * @author MCD Application Team + * @brief SRAM HAL module driver. + * This file provides a generic firmware to drive SRAM memories + * mounted as external device. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a generic layered driver which contains a set of APIs used to + control SRAM memories. It uses the FMC layer functions to interface + with SRAM devices. + The following sequence should be followed to configure the FMC to interface + with SRAM/PSRAM memories: + + (#) Declare a SRAM_HandleTypeDef handle structure, for example: + SRAM_HandleTypeDef hsram; and: + + (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed + values of the structure member. + + (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined + base register instance for NOR or SRAM device + + (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined + base register instance for NOR or SRAM extended mode + + (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended + mode timings; for example: + FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming; + and fill its fields with the allowed values of the structure member. + + (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function + performs the following sequence: + + (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit() + (##) Control register configuration using the FMC NORSRAM interface function + FMC_NORSRAM_Init() + (##) Timing register configuration using the FMC NORSRAM interface function + FMC_NORSRAM_Timing_Init() + (##) Extended mode Timing register configuration using the FMC NORSRAM interface function + FMC_NORSRAM_Extended_Timing_Init() + (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE() + + (#) At this stage you can perform read/write accesses from/to the memory connected + to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the + following APIs: + (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access + (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer + + (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/ + HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation + + (#) You can continuously monitor the SRAM device HAL state by calling the function + HAL_SRAM_GetState() + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_SRAM_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) MspInitCallback : SRAM MspInit. + (+) MspDeInitCallback : SRAM MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. It allows to reset following callbacks: + (+) MspInitCallback : SRAM MspInit. + (+) MspDeInitCallback : SRAM MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET + all callbacks are reset to the corresponding legacy weak (overridden) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (overridden) functions in the HAL_SRAM_Init + and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit + or HAL_SRAM_Init function. + + When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (overridden) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#ifdef HAL_SRAM_MODULE_ENABLED + +/** @defgroup SRAM SRAM + * @brief SRAM driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SRAM_Private_Functions SRAM Private Functions + * @{ + */ +static void SRAM_DMACplt(DMA_HandleTypeDef *hdma); +static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma); +static void SRAM_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SRAM_Exported_Functions SRAM Exported Functions + * @{ + */ + +/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * + @verbatim + ============================================================================== + ##### SRAM Initialization and de_initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to initialize/de-initialize + the SRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Performs the SRAM device initialization sequence + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param Timing Pointer to SRAM control timing structure + * @param ExtTiming Pointer to SRAM extended mode timing structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming) +{ + /* Check the SRAM handle parameter */ + if (hsram == NULL) + { + return HAL_ERROR; + } + + if (hsram->State == HAL_SRAM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsram->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + if (hsram->MspInitCallback == NULL) + { + hsram->MspInitCallback = HAL_SRAM_MspInit; + } + hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; + hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; + + /* Init the low level hardware */ + hsram->MspInitCallback(hsram); +#else + /* Initialize the low level hardware (MSP) */ + HAL_SRAM_MspInit(hsram); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ + } + + /* Initialize SRAM control Interface */ + (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); + + /* Initialize SRAM timing Interface */ + (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); + + /* Initialize SRAM extended mode timing Interface */ + (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, + hsram->Init.ExtendedMode); + + /* Enable the NORSRAM device */ + __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); + + /* Enable FMC Peripheral */ + __FMC_ENABLE(); + + /* Initialize the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Performs the SRAM device De-initialization sequence. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) +{ +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + if (hsram->MspDeInitCallback == NULL) + { + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + } + + /* DeInit the low level hardware */ + hsram->MspDeInitCallback(hsram); +#else + /* De-Initialize the low level hardware (MSP) */ + HAL_SRAM_MspDeInit(hsram); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ + + /* Configure the SRAM registers with their reset values */ + (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); + + /* Reset the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsram); + + return HAL_OK; +} + +/** + * @brief SRAM MSP Init. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsram); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_MspInit could be implemented in the user file + */ +} + +/** + * @brief SRAM MSP DeInit. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsram); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete callback. + * @param hdma pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete error callback. + * @param hdma pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions + * @brief Input Output and memory control functions + * + @verbatim + ============================================================================== + ##### SRAM Input and Output functions ##### + ============================================================================== + [..] + This section provides functions allowing to use and control the SRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Reads 8-bit buffer from SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint8_t *psramaddress = (uint8_t *)pAddress; + uint8_t *pdestbuff = pDstBuffer; + HAL_SRAM_StateTypeDef state = hsram->State; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Read data from memory */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *psramaddress; + pdestbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 8-bit buffer to SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint8_t *psramaddress = (uint8_t *)pAddress; + uint8_t *psrcbuff = pSrcBuffer; + + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *psramaddress = *psrcbuff; + psrcbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads 16-bit buffer from SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint16_t *pdestbuff = pDstBuffer; + uint8_t limit; + HAL_SRAM_StateTypeDef state = hsram->State; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Check if the size is a 32-bits multiple */ + limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); + + /* Read data from memory */ + for (size = BufferSize; size != limit; size -= 2U) + { + *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU); + pdestbuff++; + *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U); + pdestbuff++; + psramaddress++; + } + + /* Read last 16-bits if size is not 32-bits multiple */ + if (limit != 0U) + { + *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU); + } + + /* Update the SRAM controller state */ + hsram->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 16-bit buffer to SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint16_t *psrcbuff = pSrcBuffer; + uint8_t limit; + + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Check if the size is a 32-bits multiple */ + limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); + + /* Write data to memory */ + for (size = BufferSize; size != limit; size -= 2U) + { + *psramaddress = (uint32_t)(*psrcbuff); + psrcbuff++; + *psramaddress |= ((uint32_t)(*psrcbuff) << 16U); + psrcbuff++; + psramaddress++; + } + + /* Write last 16-bits if size is not 32-bits multiple */ + if (limit != 0U) + { + *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U); + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads 32-bit buffer from SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint32_t *pdestbuff = pDstBuffer; + HAL_SRAM_StateTypeDef state = hsram->State; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Read data from memory */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *psramaddress; + pdestbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 32-bit buffer to SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint32_t *psrcbuff = pSrcBuffer; + + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *psramaddress = *psrcbuff; + psrcbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads a Words data from the SRAM memory using DMA transfer. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) +{ + HAL_StatusTypeDef status; + HAL_SRAM_StateTypeDef state = hsram->State; + uint32_t size; + uint32_t data_width; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + if (state == HAL_SRAM_STATE_READY) + { + hsram->hdma->XferCpltCallback = SRAM_DMACplt; + } + else + { + hsram->hdma->XferCpltCallback = SRAM_DMACpltProt; + } + hsram->hdma->XferErrorCallback = SRAM_DMAError; + + if ((hsram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hsram->hdma->LinkedListQueue != 0U) && (hsram->hdma->LinkedListQueue->Head != 0U)) + { + /* Check destination data width and set the size to be transferred */ + data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; + + if (data_width == DMA_DEST_DATAWIDTH_WORD) + { + size = (BufferSize * 4U); + } + else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) + { + size = (BufferSize * 2U); + } + else + { + size = (BufferSize); + } + /* Set Source , destination , buffer size */ + /* Set DMA data size */ + hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size; + /* Set DMA source address */ + hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pAddress; + /* Set DMA destination address */ + hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pDstBuffer; + + /* Enable the DMA Stream */ + status = HAL_DMAEx_List_Start_IT(hsram->hdma); + } + else + { + /* Change SRAM state */ + hsram->State = HAL_SRAM_STATE_READY; + + __HAL_UNLOCK(hsram); + + status = HAL_ERROR; + } + } + else + { + /* Check destination data width and set the size to be transferred */ + data_width = hsram->hdma->Init.DestDataWidth; + + if (data_width == DMA_DEST_DATAWIDTH_WORD) + { + size = (BufferSize * 4U); + } + else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) + { + size = (BufferSize * 2U); + } + else + { + size = (BufferSize); + } + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, size); + } + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Writes a Words data buffer to SRAM memory using DMA transfer. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) +{ + HAL_StatusTypeDef status; + uint32_t size; + uint32_t data_width; + + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + hsram->hdma->XferCpltCallback = SRAM_DMACplt; + hsram->hdma->XferErrorCallback = SRAM_DMAError; + + if ((hsram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hsram->hdma->LinkedListQueue != 0U) && (hsram->hdma->LinkedListQueue->Head != 0U)) + { + /* Check destination data width and set the size to be transferred */ + data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; + + if (data_width == DMA_DEST_DATAWIDTH_WORD) + { + size = (BufferSize * 4U); + } + else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) + { + size = (BufferSize * 2U); + } + else + { + size = (BufferSize); + } + /* Set Source , destination , buffer size */ + /* Set DMA data size */ + hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size; + /* Set DMA source address */ + hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pSrcBuffer; + /* Set DMA destination address */ + hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pAddress; + /* Enable the DMA Stream */ + status = HAL_DMAEx_List_Start_IT(hsram->hdma); + } + else + { + /* Change SRAM state */ + hsram->State = HAL_SRAM_STATE_READY; + + __HAL_UNLOCK(hsram); + + status = HAL_ERROR; + } + } + else + { + /* Check destination data width and set the size to be transferred */ + data_width = hsram->hdma->Init.DestDataWidth; + + if (data_width == DMA_DEST_DATAWIDTH_WORD) + { + size = (BufferSize * 4U); + } + else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) + { + size = (BufferSize * 2U); + } + else + { + size = (BufferSize); + } + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, size); + } + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + status = HAL_ERROR; + } + + return status; +} + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SRAM Callback + * To be used to override the weak predefined callback + * @param hsram : SRAM handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID + * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SRAM_StateTypeDef state; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + state = hsram->State; + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = pCallback; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User SRAM Callback + * SRAM Callback is redirected to the weak predefined callback + * @param hsram : SRAM handle + * @param CallbackId : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID + * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID + * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SRAM_StateTypeDef state; + + state = hsram->State; + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (state == HAL_SRAM_STATE_RESET) + { + switch (CallbackId) + { + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register a User SRAM Callback for DMA transfers + * To be used to override the weak predefined callback + * @param hsram : SRAM handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_DmaCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SRAM_StateTypeDef state; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsram); + + state = hsram->State; + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = pCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsram); + return status; +} +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup SRAM_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### SRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the SRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically SRAM write operation. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) +{ + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_PROTECTED) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Enable write operation */ + (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disables dynamically SRAM write operation. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) +{ + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Disable write operation */ + (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_PROTECTED; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### SRAM State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the SRAM controller + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the SRAM controller state + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL state + */ +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) +{ + return hsram->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SRAM_Private_Functions SRAM Private Functions + * @{ + */ + +/** + * @brief DMA SRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) +{ + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + hsram->DmaXferCpltCallback(hdma); +#else + HAL_SRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) +{ + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_PROTECTED; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + hsram->DmaXferCpltCallback(hdma); +#else + HAL_SRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SRAM error callback. + * @param hdma : DMA handle + * @retval None + */ +static void SRAM_DMAError(DMA_HandleTypeDef *hdma) +{ + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_ERROR; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + hsram->DmaXferErrorCallback(hdma); +#else + HAL_SRAM_DMA_XferErrorCallback(hdma); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SRAM_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_tim.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_tim.c new file mode 100644 index 00000000000..78637cc3858 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_tim.c @@ -0,0 +1,8242 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare: + to use the Timer to generate an Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + (+) Break2Callback : TIM Break2 Callback. + (+) EncoderIndexCallback : TIM Encoder Index Callback. + (+) DirectionChangeCallback : TIM Direction Change Callback + (+) IndexErrorCallback : TIM Index Error Callback. + (+) TransitionErrorCallback : TIM Transition Error Callback + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + default: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + uint32_t itsource = htim->Instance->DIER; + uint32_t itflag = htim->Instance->SR; + + /* Capture compare 1 event */ + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) + { + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) + { + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) + { + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) + { + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) + { + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) + { + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ + ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) + { + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) + { + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) + { + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) + { + if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Encoder index event */ + if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX)) + { + if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->EncoderIndexCallback(htim); +#else + HAL_TIMEx_EncoderIndexCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Direction change event */ + if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR)) + { + if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->DirectionChangeCallback(htim); +#else + HAL_TIMEx_DirectionChangeCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Index error event */ + if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR)) + { + if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IndexErrorCallback(htim); +#else + HAL_TIMEx_IndexErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Transition error event */ + if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR)) + { + if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TransitionErrorCallback(htim); +#else + HAL_TIMEx_TransitionErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 5 in Output Compare */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 6 in Output Compare */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_4) + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + else + { + status = HAL_ERROR; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + HAL_StatusTypeDef status = HAL_OK; + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_DTR2 + * @arg TIM_DMABASE_ECR + * @arg TIM_DMABASE_TISEL + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t BlockDataLength = 0; + uint32_t data_width; + const DMA_HandleTypeDef *hdma = NULL; + + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + hdma = htim->hdma[TIM_DMA_ID_UPDATE]; + break; + } + case TIM_DMA_CC1: + { + hdma = htim->hdma[TIM_DMA_ID_CC1]; + break; + } + case TIM_DMA_CC2: + { + hdma = htim->hdma[TIM_DMA_ID_CC2]; + break; + } + case TIM_DMA_CC3: + { + hdma = htim->hdma[TIM_DMA_ID_CC3]; + break; + } + case TIM_DMA_CC4: + { + hdma = htim->hdma[TIM_DMA_ID_CC4]; + break; + } + case TIM_DMA_COM: + { + hdma = htim->hdma[TIM_DMA_ID_COMMUTATION]; + break; + } + case TIM_DMA_TRIGGER: + { + hdma = htim->hdma[TIM_DMA_ID_TRIGGER]; + break; + } + default: + status = HAL_ERROR; + break; + } + + if (hdma != NULL) + { + + if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U) + && (hdma->LinkedListQueue->Head != 0U)) + { + data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; + } + else + { + data_width = hdma->Init.SrcDataWidth; + } + + switch (data_width) + { + case DMA_SRC_DATAWIDTH_BYTE: + { + BlockDataLength = (BurstLength >> TIM_DCR_DBL_Pos) + 1UL; + break; + } + case DMA_SRC_DATAWIDTH_HALFWORD: + { + BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL; + break; + } + case DMA_SRC_DATAWIDTH_WORD: + { + BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL; + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + BlockDataLength); + } + } + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_DTR2 + * @arg TIM_DMABASE_ECR + * @arg TIM_DMABASE_TISEL + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpDBSS = 0; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = TIM_DCR_DBSS_0; + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = TIM_DCR_DBSS_1; + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = TIM_DCR_DBSS_2; + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_DTR2 + * @arg TIM_DMABASE_ECR + * @arg TIM_DMABASE_TISEL + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t BlockDataLength = 0; + uint32_t data_width; + const DMA_HandleTypeDef *hdma = NULL; + + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + hdma = htim->hdma[TIM_DMA_ID_UPDATE]; + break; + } + case TIM_DMA_CC1: + { + hdma = htim->hdma[TIM_DMA_ID_CC1]; + break; + } + case TIM_DMA_CC2: + { + hdma = htim->hdma[TIM_DMA_ID_CC2]; + break; + } + case TIM_DMA_CC3: + { + hdma = htim->hdma[TIM_DMA_ID_CC3]; + break; + } + case TIM_DMA_CC4: + { + hdma = htim->hdma[TIM_DMA_ID_CC4]; + break; + } + case TIM_DMA_COM: + { + hdma = htim->hdma[TIM_DMA_ID_COMMUTATION]; + break; + } + case TIM_DMA_TRIGGER: + { + hdma = htim->hdma[TIM_DMA_ID_TRIGGER]; + break; + } + default: + status = HAL_ERROR; + break; + } + + if (hdma != NULL) + { + + if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U) + && (hdma->LinkedListQueue->Head != 0U)) + { + data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; + } + else + { + data_width = hdma->Init.SrcDataWidth; + } + + switch (data_width) + + { + case DMA_SRC_DATAWIDTH_BYTE: + { + BlockDataLength = ((BurstLength) >> TIM_DCR_DBL_Pos) + 1UL; + break; + } + case DMA_SRC_DATAWIDTH_HALFWORD: + { + BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL; + break; + } + case DMA_SRC_DATAWIDTH_WORD: + { + BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL; + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + BlockDataLength); + } + } + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_DTR2 + * @arg TIM_DMABASE_ECR + * @arg TIM_DMABASE_TISEL + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpDBSS = 0; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = TIM_DCR_DBSS_0; + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = TIM_DCR_DBSS_1; + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = TIM_DCR_DBSS_2; + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant + * only for timer instances supporting break input(s). + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + case TIM_CHANNEL_5: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; + } + case TIM_CHANNEL_6: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; + } + default: + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + case TIM_CLOCKSOURCE_ITR4: + case TIM_CLOCKSOURCE_ITR5: + case TIM_CLOCKSOURCE_ITR6: + case TIM_CLOCKSOURCE_ITR7: + case TIM_CLOCKSOURCE_ITR8: + case TIM_CLOCKSOURCE_ITR9: + case TIM_CLOCKSOURCE_ITR10: + case TIM_CLOCKSOURCE_ITR11: + case TIM_CLOCKSOURCE_ITR13: + case TIM_CLOCKSOURCE_ITR14: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + status = HAL_ERROR; + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @brief Start the DMA data transfer. + * @param hdma DMA handle + * @param src : The source memory Buffer address. + * @param dst : The destination memory Buffer address. + * @param length : The size of a source block transfer in byte. + * @retval HAL status + */ +HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst, + uint32_t length) +{ + HAL_StatusTypeDef status ; + + /* Enable the DMA channel */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U)) + { + /* Enable the DMA channel */ + hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length; + hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = src; + hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = dst; + + status = HAL_DMAEx_List_Start_IT(hdma); + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hdma, src, dst, length); + } + + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + (+) TIM Index callback + (+) TIM Direction change callback + (+) TIM Index error callback + (+) TIM Transition error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID + * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID + * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID + * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = pCallback; + break; + + case HAL_TIM_ENCODER_INDEX_CB_ID : + htim->EncoderIndexCallback = pCallback; + break; + + case HAL_TIM_DIRECTION_CHANGE_CB_ID : + htim->DirectionChangeCallback = pCallback; + break; + + case HAL_TIM_INDEX_ERROR_CB_ID : + htim->IndexErrorCallback = pCallback; + break; + + case HAL_TIM_TRANSITION_ERROR_CB_ID : + htim->TransitionErrorCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID + * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID + * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID + * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + /* Legacy weak Break2 Callback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; + break; + + case HAL_TIM_ENCODER_INDEX_CB_ID : + /* Legacy weak Encoder Index Callback */ + htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; + break; + + case HAL_TIM_DIRECTION_CHANGE_CB_ID : + /* Legacy weak Direction Change Callback */ + htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; + break; + + case HAL_TIM_INDEX_ERROR_CB_ID : + /* Legacy weak Index Error Callback */ + htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; + break; + + case HAL_TIM_TRANSITION_ERROR_CB_ID : + /* Legacy weak Transition Error Callback */ + htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + + /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ + if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) + { + /* Clear the update flag */ + CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); + } +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC4NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 12U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC4NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + /* Reset the Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4N; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 5 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 6 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \ + (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET)) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + case TIM_TS_ITR4: + case TIM_TS_ITR5: + case TIM_TS_ITR6: + case TIM_TS_ITR7: + case TIM_TS_ITR8: + case TIM_TS_ITR9: + case TIM_TS_ITR10: + case TIM_TS_ITR11: + case TIM_TS_ITR13: + case TIM_TS_ITR14: + { + /* Check the parameter */ + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger)); + break; + } + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_CLOCKSOURCE_ITR3: Internal Trigger 3 + * @arg TIM_CLOCKSOURCE_ITR4: Internal Trigger 4 + * @arg TIM_CLOCKSOURCE_ITR5: Internal Trigger 5 + * @arg TIM_CLOCKSOURCE_ITR6: Internal Trigger 6 + * @arg TIM_CLOCKSOURCE_ITR7: Internal Trigger 7 + * @arg TIM_CLOCKSOURCE_ITR8: Internal Trigger 8 + * @arg TIM_CLOCKSOURCE_ITR9: Internal Trigger 9 + * @arg TIM_CLOCKSOURCE_ITR10: Internal Trigger 10 + * @arg TIM_CLOCKSOURCE_ITR11: Internal Trigger 11 + * @arg TIM_CLOCKSOURCE_ITR13: Internal Trigger 13 + * @arg TIM_CLOCKSOURCE_ITR14: Internal Trigger 14 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; + htim->Break2Callback = HAL_TIMEx_Break2Callback; + htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; + htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; + htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; + htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_tim_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_tim_ex.c new file mode 100644 index 00000000000..32076299005 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_tim_ex.c @@ -0,0 +1,3351 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + * + Timer remapping capabilities configuration + * + Timer encoder index configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + (#) In case of Pulse on compare, configure pulse length and delay + (#) Encoder index configuration + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + (#) In case of Pulse On Compare: + (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler + + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants + * @{ + */ +/* Timeout for break input rearm */ +#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */ +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel for Capture 1*/ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + case TIM_CHANNEL_4: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + (+) Select timer input source. + (+) Enable or disable channel grouping. + (+) Configure Pulse on compare. + (+) Configure Encoder index. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR4: Internal trigger 4 selected + * @arg TIM_TS_ITR5: Internal trigger 5 selected + * @arg TIM_TS_ITR6: Internal trigger 6 selected + * @arg TIM_TS_ITR7: Internal trigger 7 selected + * @arg TIM_TS_ITR8: Internal trigger 8 selected + * @arg TIM_TS_ITR9: Internal trigger 9 selected + * @arg TIM_TS_ITR10: Internal trigger 10 selected + * @arg TIM_TS_ITR11: Internal trigger 11 selected + * @arg TIM_TS_ITR13: Internal trigger 13 selected + * @arg TIM_TS_ITR14: Internal trigger 14 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger)); + + __HAL_LOCK(htim); + + if (CommutationSource == TIM_COMMUTATION_TRGI) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR4: Internal trigger 4 selected + * @arg TIM_TS_ITR5: Internal trigger 5 selected + * @arg TIM_TS_ITR6: Internal trigger 6 selected + * @arg TIM_TS_ITR7: Internal trigger 7 selected + * @arg TIM_TS_ITR8: Internal trigger 8 selected + * @arg TIM_TS_ITR9: Internal trigger 9 selected + * @arg TIM_TS_ITR10: Internal trigger 10 selected + * @arg TIM_TS_ITR11: Internal trigger 11 selected + * @arg TIM_TS_ITR13: Internal trigger 13 selected + * @arg TIM_TS_ITR14: Internal trigger 14 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger)); + + __HAL_LOCK(htim); + + if (CommutationSource == TIM_COMMUTATION_TRGI) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR4: Internal trigger 4 selected + * @arg TIM_TS_ITR5: Internal trigger 5 selected + * @arg TIM_TS_ITR6: Internal trigger 6 selected + * @arg TIM_TS_ITR7: Internal trigger 7 selected + * @arg TIM_TS_ITR8: Internal trigger 8 selected + * @arg TIM_TS_ITR9: Internal trigger 9 selected + * @arg TIM_TS_ITR10: Internal trigger 10 selected + * @arg TIM_TS_ITR11: Internal trigger 11 selected + * @arg TIM_TS_ITR13: Internal trigger 13 selected + * @arg TIM_TS_ITR14: Internal trigger 14 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger)); + + __HAL_LOCK(htim); + + if (CommutationSource == TIM_COMMUTATION_TRGI) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + } + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); + + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); + assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); + + /* Set the BREAK2 input related BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); + } + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the break input source. + * @param htim TIM handle. + * @param BreakInput Break input to configure + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @param sBreakInputConfig Break input source configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, + uint32_t BreakInput, + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmporx; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); + assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); + + /* Check input state */ + __HAL_LOCK(htim); + + switch (sBreakInputConfig->Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM_AF1_BKINE; + bkin_enable_bitpos = TIM_AF1_BKINE_Pos; + bkin_polarity_mask = TIM_AF1_BKINP; + bkin_polarity_bitpos = TIM_AF1_BKINP_Pos; + break; + } + + default: + { + bkin_enable_mask = 0U; + bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_bitpos = 0U; + break; + } + } + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_AF2 register value */ + tmporx = htim->Instance->AF2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + + /* Set TIMx_AF2 */ + htim->Instance->AF2 = tmporx; + break; + } + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * For TIM1, the parameter can take one of the following values: + * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO + * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3 + * @arg TIM_TIM1_ETR_ADC2_AWD1 TIM1 ETR is connected to ADC2 AWD1 + * @arg TIM_TIM1_ETR_ADC2_AWD2 TIM1 ETR is connected to ADC2 AWD2 + * @arg TIM_TIM1_ETR_ADC2_AWD3 TIM1 ETR is connected to ADC2 AWD3 + * + * For TIM2, the parameter can take one of the following values: + * @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO + * @arg TIM_TIM2_ETR_DCMIPP_HSYNC TIM2 ETR is connected to DCMIPP HSYNC pin + * @arg TIM_TIM2_ETR_LTDC_HSYNC TIM2 ETR is connected to LTDC HSYNC pin + * @arg TIM_TIM2_ETR_SAI1_FSA TIM2_ETR is connected to SAI1 FS_A + * @arg TIM_TIM2_ETR_SAI1_FSB TIM2_ETR is connected to SAI1 FS_B + * @arg TIM_TIM2_ETR_GFXTIM_TE TIM2_ETR is connected to GFXTIM TE + * @arg TIM_TIM2_ETR_DCMIPP_HSYNC TIM2 ETR is connected to DCMIPP HSYNC pin + * @arg TIM_TIM2_ETR_LTDC_HSYNC TIM2 ETR is connected to LTDC HSYNC pin + * @arg TIM_TIM3_ETR_TIM3_ETR TIM3_ETR is connected to TIM3 ETR + * @arg TIM_TIM3_ETR_TIM4_ETR TIM3_ETR is connected to TIM4 ETR + * @arg TIM_TIM3_ETR_TIM5_ETR TIM3_ETR is connected to TIM5 ETR + * @arg TIM_TIM2_ETR_ETH_PPS TIM2_ETR is connected to ETH PPS + * + * For TIM3, the parameter can take one of the following values: + * @arg TIM_TIM3_ETR_GPIO TIM3_ETR is not connected to I/O + * @arg TIM_TIM3_ETR_DCMIPP_HSYNC TIM3_ETR is connected to DCMIPP HSYNC + * @arg TIM_TIM3_ETR_LTDC_HSYNC TIM3_ETR is connected to LTDC HSYNC + * @arg TIM_TIM3_ETR_GFXTIM_TE TIM3_ETR is connected to GFXTIM TE + * @arg TIM_TIM3_ETR_DCMIPP_HSYNC TIM3_ETR is connected to DCMIPP VSYNC + * @arg TIM_TIM3_ETR_LTDC_VSYNC TIM3_ETR is connected to LTDC VSYNC + * @arg TIM_TIM3_ETR_TIM2_ETR TIM3_ETR is connected to TIM2 ETR + * @arg TIM_TIM3_ETR_TIM4_ETR TIM3_ETR is connected to TIM4 ETR + * @arg TIM_TIM3_ETR_TIM5_ETR TIM3_ETR is connected to TIM5 ETR + * @arg TIM_TIM3_ETR_ETH_PPS TIM3_ETR is connected to ETH PPS + * + * For TIM4, the parameter can take one of the following values: + * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO + * @arg TIM_TIM4_ETR_DCMIPP_HSYNC TIM4_ETR is connected to DCMIPP HSYNC + * @arg TIM_TIM4_ETR_LTDC_HSYNC TIM4_ETR is connected to LTDC HSYNC + * @arg TIM_TIM4_ETR_GFXTIM_TE TIM4_ETR is connected to GFXTIM TE + * @arg TIM_TIM4_ETR_DCMIPP_HSYNC TIM4_ETR is connected to DCMIPP VSYNC + * @arg TIM_TIM4_ETR_LTDC_VSYNC TIM4_ETR is connected to LTDC VSYNC + * @arg TIM_TIM4_ETR_TIM2_ETR TIM4_ETR is connected to TIM2 ETR + * @arg TIM_TIM4_ETR_TIM3_ETR TIM4_ETR is connected to TIM3 ETR + * @arg TIM_TIM4_ETR_TIM5_ETR TIM4_ETR is connected to TIM5 ETR + * @arg TIM_TIM4_ETR_ETH1_PPS TIM4_ETR is connected to ETH1 PPS + * + * For TIM5, the parameter can take one of the following values: + * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO + * @arg TIM_TIM5_ETR_SAI2_FSA TIM5_ETR is connected to SAI2 FS_A + * @arg TIM_TIM5_ETR_SAI2_FSB TIM5_ETR is connected to SAI2 FS_B + * @arg TIM_TIM5_ETR_DCMIPP_HSYNC TIM5_ETR is connected to DCMIPP HSYNC + * @arg TIM_TIM5_ETR_LTDC_HSYNC TIM5_ETR is connected to LTDC HSYNC + * @arg TIM_TIM5_ETR_GFXTIM_TE TIM5_ETR is connected to GFXTIM TE + * @arg TIM_TIM5_ETR_DCMIPP_HSYNC TIM5_ETR is connected to DCMIPP VSYNC + * @arg TIM_TIM5_ETR_LTDC_VSYNC TIM5_ETR is connected to LTDC VSYNC + * @arg TIM_TIM5_ETR_TIM2_ETR TIM5_ETR is connected to TIM2 ETR + * @arg TIM_TIM5_ETR_TIM3_ETR TIM5_ETR is connected to TIM3 ETR + * @arg TIM_TIM5_ETR_TIM3_ETR TIM5_ETR is connected to TIM4 ETR + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(htim->Instance, Remap)); + + __HAL_LOCK(htim); + + MODIFY_REG(htim->Instance->AF1, TIM_AF1_ETRSEL_Msk, Remap); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Select the timer input source + * @param htim TIM handle. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TI1 input channel + * @arg TIM_CHANNEL_2: TI2 input channel + * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows: + * For TIM2, the parameter is one of the following values: + * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO + * @arg TIM_TIM2_TI1_ETH_PPS: TIM2 TI1 is connected to ETH PPS + * + * For TIM3, the parameter is one of the following values: + * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO + * @arg TIM_TIM3_TI1_ETH_PPS: TIM3 TI1 is connected to ETH PPS + * + * For TIM9, the parameter is one of the following values: + * @arg TIM_TIM9_TI1_GPIO: TIM9 TI1 is connected to GPIO + * @arg TIM_TIM9_TI1_MCO1: TIM9 TI1 is connected to MCO1 + * @arg TIM_TIM9_TI1_MCO2: TIM9 TI1 is connected to MCO2 + * + * For TIM12, the parameter is one of the following values: + * @arg TIM_TIM12_TI1_GPIO: TIM12 TI1 is connected to GPIO + * @arg TIM_TIM12_TI1_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS + * @arg TIM_TIM12_TI1_HSI_1024: TIM12 TI1 is connected to HSI/1024 + * @arg TIM_TIM12_TI1_CSI_128: TIM12_TI1 is connected to CSI/128 + * @arg TIM_TIM12_TI1_MCO1: TIM12 TI1 is connected to MCO1 + * @arg TIM_TIM12_TI1_MCO2: TIM12 TI1 is connected to MCO2 + * + * For TIM15, the parameter is one of the following values: + * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO + * @arg TIM_TIM15_TI1_TIM2_CH1: TIM15 TI1 is connected to TIM2 CH1 + * @arg TIM_TIM15_TI1_TIM3_CH1: TIM15 TI1 is connected to TIM3 CH1 + * @arg TIM_TIM15_TI1_TIM4_CH1: TIM15 TI1 is connected to TIM4 CH1 + * @arg TIM_TIM15_TI1_MCO1: TIM15 TI1 is connected to MCO1 + * @arg TIM_TIM15_TI1_MCO2: TIM15 TI1 is connected to MCO2 + * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO + * @arg TIM_TIM15_TI2_TIM2_CH2: TIM15 TI2 is connected to TIM2 CH2 + * @arg TIM_TIM15_TI2_TIM3_CH2: TIM15 TI2 is connected to TIM3 CH2 + * @arg TIM_TIM15_TI2_TIM4_CH2: TIM15 TI2 is connected to TIM4 CH2 + * + * For TIM16, the parameter is one of the following values: + * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO + * @arg TIM_TIM16_TI1_RTC_WKUP: TIM16 TI1 is connected to RTC wakeup interrupt + * + * For TIM17, the parameter is one of the following values: + * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO + * @arg TIM_TIM17_TI1_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_TIM_TISEL_TIX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_TISEL(TISelection)); + + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection); + break; + case TIM_CHANNEL_2: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection); + break; + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Group channel 5 and channel 1, 2 or 3 + * @param htim TIM handle. + * @param Channels specifies the reference signal(s) the OC5REF is combined with. + * This parameter can be any combination of the following values: + * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC + * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF + * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF + * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) +{ + /* Check parameters */ + assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_GROUPCH5(Channels)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Clear GC5Cx bit fields */ + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); + + /* Set GC5Cx bit fields */ + htim->Instance->CCR5 |= Channels; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Disarm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to disarm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpbdtr; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM); + } + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM); + } + break; + } + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Arm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to arm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note Arming is possible at anytime, even if fault is present. + * @note Break input is automatically armed as soon as MOE bit is set. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) + { + /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) + { + /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Enable dithering + * @param htim TIM handle + * @note Main usage is PWM mode + * @note This function must be called when timer is stopped or disabled (CEN =0) + * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation: + * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers) + * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers + * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers + * - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers + * (corresponds to 4094 for the integer part and 15 for the dithered part). + * @note Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER() + * can be used to calculate period (ARR) and delay (CCRx) value. + * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. + * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. + * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD() + * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period . + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN); + return HAL_OK; +} + +/** + * @brief Disable dithering + * @param htim TIM handle + * @note This function must be called when timer is stopped or disabled (CEN =0) + * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation: + * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers) + * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers + * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers + * - ARR and CCRx values are limited to 0xFFEF in dithering mode + * (corresponds to 4094 for the integer part and 15 for the dithered part). + * @note Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. + * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD() + * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period . + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN); + return HAL_OK; +} + +/** + * @brief Initializes the pulse on compare pulse width and pulse prescaler + * @param htim TIM Output Compare handle + * @param PulseWidthPrescaler Pulse width prescaler + * This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7 + * @param PulseWidth Pulse width + * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, + uint32_t PulseWidthPrescaler, + uint32_t PulseWidth) +{ + uint32_t tmpecr; + + /* Check the parameters */ + assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth)); + assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx ECR register value */ + tmpecr = htim->Instance->ECR; + /* Reset the Pulse width prescaler and the Pulse width */ + tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW); + /* Set the Pulse width prescaler and Pulse width*/ + tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos; + tmpecr |= PulseWidth << TIM_ECR_PW_Pos; + /* Write to TIMx ECR */ + htim->Instance->ECR = tmpecr; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register) + * @param htim TIM handle + * @param Source Source of slave mode selection preload + * This parameter can be one of the following values: + * @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload + * @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source)); + + MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source); + return HAL_OK; +} + +/** + * @brief Enable preload of Slave Mode Selection bitfield (SMS in SMCR register) + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + + SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE); + return HAL_OK; +} + +/** + * @brief Disable preload of Slave Mode Selection bitfield (SMS in SMCR register) + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + + CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE); + return HAL_OK; +} + +/** + * @brief Enable deadtime preload + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + + SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); + return HAL_OK; +} + +/** + * @brief Disable deadtime preload + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + + CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); + return HAL_OK; +} + +/** + * @brief Configure deadtime + * @param htim TIM handle + * @param Deadtime Deadtime value + * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime) +{ + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DEADTIME(Deadtime)); + + MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime); + return HAL_OK; +} + +/** + * @brief Configure asymmetrical deadtime + * @param htim TIM handle + * @param FallingDeadtime Falling edge deadtime value + * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime) +{ + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DEADTIME(FallingDeadtime)); + + MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); + return HAL_OK; +} + +/** + * @brief Enable asymmetrical deadtime + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + + SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); + return HAL_OK; +} + +/** + * @brief Disable asymmetrical deadtime + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + + CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); + return HAL_OK; +} + +/** + * @brief Configures the encoder index. + * @note warning in case of encoder mode clock plus direction + * @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 + * Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN + * @param htim TIM handle. + * @param sEncoderIndexConfig Encoder index configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim, + TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity)); + assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler)); + assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter)); + assert_param(IS_TIM_ENCODERINDEX_BLANKING(sEncoderIndexConfig->Blanking)); + assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable)); + assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position)); + assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Configures the TIMx External Trigger (ETR) which is used as Index input */ + TIM_ETR_SetConfig(htim->Instance, + sEncoderIndexConfig->Prescaler, + sEncoderIndexConfig->Polarity, + sEncoderIndexConfig->Filter); + + /* Configures the encoder index */ + MODIFY_REG(htim->Instance->ECR, + TIM_ECR_IDIR_Msk | TIM_ECR_IBLK_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk, + (sEncoderIndexConfig->Direction | + (sEncoderIndexConfig->Blanking) | + ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | + sEncoderIndexConfig->Position | + TIM_ECR_IE)); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Enable encoder index + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + SET_BIT(htim->Instance->ECR, TIM_ECR_IE); + return HAL_OK; +} + +/** + * @brief Disable encoder index + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE); + return HAL_OK; +} + +/** + * @brief Enable encoder first index + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); + return HAL_OK; +} + +/** + * @brief Disable encoder first index + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Commutation callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Commutation half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +/** + * @brief Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} + +/** + * @brief Encoder index callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file + */ +} + +/** + * @brief Direction change callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file + */ +} + +/** + * @brief Index error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_IndexErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Transition error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_timebase_rtc_wakeup_template.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_timebase_rtc_wakeup_template.c new file mode 100644 index 00000000000..3c60f62cde1 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_timebase_rtc_wakeup_template.c @@ -0,0 +1,275 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_timebase_rtc_wakeup_template.c + * @author MCD Application Team + * @brief HAL time base based on the hardware RTC_WAKEUP Template. + * + * This file overrides the native HAL time base functions (defined as weak) + * to use the RTC WAKEUP for the time base generation: + * + Initializes the RTC peripheral and configures the wakeup timer to be + * incremented each 1ms + * + The wakeup feature is configured to assert an interrupt each 1ms + * + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback + * + HSE (default), LSE or LSI can be selected as RTC clock source + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This file must be copied to the application folder and modified as follows: + (#) Rename it to 'stm32h7rsxx_hal_timebase_rtc_wakeup.c' + (#) Add this file and the RTC HAL drivers to your project and uncomment + HAL_RTC_MODULE_ENABLED define in stm32h7rsxx_hal_conf.h + + [..] + (@) HAL RTC alarm and HAL RTC wakeup drivers can not be used with low power modes: + The wake up capability of the RTC may be intrusive in case of prior low power mode + configuration requiring different wake up sources. + Application/Example behavior is no more guaranteed + (@) The stm32h7rsxx_hal_timebase_tim use is recommended for the Applications/Examples + requiring low power modes + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup HAL_TimeBase_RTC_WakeUp_Template HAL TimeBase RTC WakeUp Template + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Uncomment the line below to select the appropriate RTC Clock source for your application: + + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision. + + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing + precision. + + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing + precision. + */ +#define RTC_CLOCK_SOURCE_HSE +/* #define RTC_CLOCK_SOURCE_LSE */ +/* #define RTC_CLOCK_SOURCE_LSI */ + +/* The time base should be 1ms + Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK + HSE as RTC clock + Time base = ((99 + 1) * (4 + 1)) / 500kHz + = 1ms + LSE as RTC clock + Time base = ((32 + 1) * (0 + 1)) / 32.768kHz + = ~1ms + LSI as RTC clock + Time base = ((31 + 1) * (0 + 1)) / 32kHz + = 1ms +*/ +#if defined (RTC_CLOCK_SOURCE_HSE) +#define RTC_ASYNCH_PREDIV 99U +#define RTC_SYNCH_PREDIV 4U +#elif defined (RTC_CLOCK_SOURCE_LSE) +#define RTC_ASYNCH_PREDIV 0U +#define RTC_SYNCH_PREDIV 32U +#elif defined (RTC_CLOCK_SOURCE_LSI) +#define RTC_ASYNCH_PREDIV 0U +#define RTC_SYNCH_PREDIV 31U +#else +#error Please select the RTC Clock source +#endif /* RTC_CLOCK_SOURCE_HSE */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static RTC_HandleTypeDef hRTC_Handle; + +/* Private function prototypes -----------------------------------------------*/ +void RTC_IRQHandler(void); +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1U) +void TimeBase_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the RTC wakeup timer as a time base source. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + HAL_StatusTypeDef Status; + + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Disable bkup domain protection */ + HAL_PWR_EnableBkUpAccess(); + + /* Force and Release the Backup domain reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + /* Enable RTC Clock */ + __HAL_RCC_RTC_ENABLE(); + __HAL_RCC_RTCAPB_CLK_ENABLE(); + +#if defined (RTC_CLOCK_SOURCE_LSE) + /* Configure LSE as RTC clock source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_NONE; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; +#elif defined (RTC_CLOCK_SOURCE_LSI) + /* Configure LSI as RTC clock source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_NONE; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; +#elif defined (RTC_CLOCK_SOURCE_HSE) + /* Configure HSE as RTC clock source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_NONE; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV48; +#else +#error Please select the RTC Clock source +#endif /* RTC_CLOCK_SOURCE_LSE */ + + Status = HAL_RCC_OscConfig(&RCC_OscInitStruct); + + if (Status == HAL_OK) + { + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + Status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + } + + if (Status == HAL_OK) + { + hRTC_Handle.Instance = RTC; + hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24; + hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV; + hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV; + hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE; + hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + hRTC_Handle.Init.BinMode = RTC_BINARY_NONE; + + Status = HAL_RTC_Init(&hRTC_Handle); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1U) + HAL_RTC_RegisterCallback(&hRTC_Handle, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID, TimeBase_RTCEx_WakeUpTimerEventCallback); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + if (Status == HAL_OK) + { + uint32_t WakeUpCounter = ((uint32_t)uwTickFreq / (uint32_t)HAL_TICK_FREQ_1KHZ) - 1U; + Status = HAL_RTCEx_SetWakeUpTimer_IT(&hRTC_Handle, WakeUpCounter, RTC_WAKEUPCLOCK_CK_SPRE_16BITS, 0); + } + + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /* Enable the RTC global Interrupt */ + HAL_NVIC_SetPriority(RTC_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + Status = HAL_ERROR; + } + + HAL_NVIC_EnableIRQ(RTC_IRQn); + + return Status; +} + +/** + * @brief Suspend Tick increment. + * @note Disable the tick increment by disabling RTC_WKUP interrupt. + * @retval None + */ +void HAL_SuspendTick(void) +{ + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); + /* Disable RTC WAKE UP TIMER Interrupt */ + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); +} + +/** + * @brief Resume Tick increment. + * @note Enable the tick increment by enabling RTC_WKUP interrupt. + * @retval None + */ +void HAL_ResumeTick(void) +{ + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); + /* Enable RTC WAKE UP TIMER interrupt */ + __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); +} + +/** + * @brief Wake Up Timer Event Callback in non blocking mode + * @note This function is called when RTC_WKUP interrupt took place, inside + * RTC_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param hrtc RTC handle + * @retval None + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1U) +void TimeBase_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +#else +void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS == 1U */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + HAL_IncTick(); +} + +/** + * @brief This function handles RTC WAKE UP TIMER interrupt request. + * @retval None + */ +void RTC_IRQHandler(void) +{ + HAL_RTCEx_WakeUpTimerIRQHandler(&hRTC_Handle); +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_timebase_tim_template.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_timebase_tim_template.c new file mode 100644 index 00000000000..08a8a6da82b --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_timebase_tim_template.c @@ -0,0 +1,221 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_timebase_tim_template.c + * @author MCD Application Team + * @brief Template for HAL time base based on the peripheral hardware TIM6. + * + * This file override the native HAL time base functions (defined as weak) + * the TIM time base: + * + Initializes the TIM6 peripheral to generate a Period elapsed Event each 1ms + * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This file must be copied to the application folder and modified as follows: + (#) Rename it to 'stm32h7rsxx_hal_timebase_tim.c' + (#) Add this file and the TIM HAL driver files to your project and make sure + HAL_TIM_MODULE_ENABLED is defined in stm32h7rsxx_hal_conf.h + + [..] + (@) The application needs to ensure that the time base is always set to 1 millisecond + to have correct HAL operation. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL_TimeBase + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define TIM_CNT_FREQ 500000U /* Timer counter frequency : 500 kHz */ +#define TIM_FREQ 1000U /* Timer frequency : 1 kHz => to have 1 ms interrupt */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static TIM_HandleTypeDef TimHandle; + +/* Private function prototypes -----------------------------------------------*/ +void TIM6_IRQHandler(void); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) +void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the TIM6 as a time base source. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + RCC_ClkInitTypeDef clkconfig; + uint32_t uwTimclock; + uint32_t uwAPB1Prescaler; + uint32_t uwPrescalerValue; + uint32_t pFLatency; + HAL_StatusTypeDef Status; + + /* Enable TIM6 clock */ + __HAL_RCC_TIM6_CLK_ENABLE(); + + /* Get clock configuration */ + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + + /* Get APB1 prescaler */ + uwAPB1Prescaler = clkconfig.APB1CLKDivider; + + /* Compute TIM6 clock */ + if (uwAPB1Prescaler == RCC_APB1_DIV1) + { + uwTimclock = HAL_RCC_GetPCLK1Freq(); + } + else if (uwAPB1Prescaler == RCC_APB1_DIV2) + { + uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); + } + else + { + if (__HAL_RCC_GET_TIMCLKPRESCALER() == RCC_TIMPRES_DISABLE) + { + uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); + } + else + { + uwTimclock = 4UL * HAL_RCC_GetPCLK1Freq(); + } + } + + /* Compute the prescaler value to have TIM6 counter clock equal to TIM_CNT_FREQ */ + uwPrescalerValue = (uint32_t)((uwTimclock / TIM_CNT_FREQ) - 1U); + + /* Initialize TIM6 */ + TimHandle.Instance = TIM6; + + /* Initialize TIMx peripheral as follow: + + Period = [uwTickFreq * (TIM_CNT_FREQ/TIM_FREQ) - 1]. to have a (uwTickFreq/TIM_FREQ) s time base. + + Prescaler = (uwTimclock/TIM_CNT_FREQ - 1) to have a TIM_CNT_FREQ counter clock. + + ClockDivision = 0 + + Counter direction = Up + */ + TimHandle.Init.Period = ((uint32_t)uwTickFreq * (TIM_CNT_FREQ / TIM_FREQ)) - 1U; + TimHandle.Init.Prescaler = uwPrescalerValue; + TimHandle.Init.ClockDivision = 0; + TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + Status = HAL_TIM_Base_Init(&TimHandle); + if (Status == HAL_OK) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) + HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Start the TIM time Base generation in interrupt mode */ + Status = HAL_TIM_Base_Start_IT(&TimHandle); + if (Status == HAL_OK) + { + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /* Configure the TIM6 global Interrupt priority */ + HAL_NVIC_SetPriority(TIM6_IRQn, TickPriority, 0); + + /* Enable the TIM6 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM6_IRQn); + + uwTickPrio = TickPriority; + } + else + { + Status = HAL_ERROR; + } + } + } + + /* Return function status */ + return Status; +} + +/** + * @brief Suspend Tick increment. + * @note Disable the tick increment by disabling TIM6 update interrupt. + * @retval None + */ +void HAL_SuspendTick(void) +{ + /* Disable TIM6 update interrupt */ + __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE); +} + +/** + * @brief Resume Tick increment. + * @note Enable the tick increment by enabling TIM6 update interrupt. + * @retval None + */ +void HAL_ResumeTick(void) +{ + /* Enable TIM6 update interrupt */ + __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE); +} + +/** + * @brief Period elapsed callback in non blocking mode + * @note This function is called when TIM6 interrupt took place, inside + * HAL_TIM6_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param htim TIM handle + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) +void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +#else +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + HAL_IncTick(); +} + +/** + * @brief This function handles TIM6 interrupt request. + * @retval None + */ +void TIM6_IRQHandler(void) +{ + HAL_TIM_IRQHandler(&TimHandle); +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_uart.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_uart.c new file mode 100644 index 00000000000..17202b3e627 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_uart.c @@ -0,0 +1,4867 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) UART interrupts handling: + -@@- The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) + are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() + inside the transmit and receive processes. + (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware + flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. + + (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) + in the huart handle AdvancedInit structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers + by calling the HAL_LIN_Init() API. + + (#) For the UART Multiprocessor mode, initialize the UART registers + by calling the HAL_MultiProcessor_Init() API. + + (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + [..] + (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), + also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + calling the customized HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). + + [..] + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ + USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \ + USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ + +#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ +#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ + +#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ +#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions + * @{ + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +#if defined(HAL_DMA_MODULE_ENABLED) +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup UART_Private_variables + * @{ + */ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +/** + * @} + */ + +/* Exported Constants --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API + follow respectively the UART asynchronous, UART Half duplex, UART LIN mode + and UART multiprocessor mode configuration procedures (details for the procedures + are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the UART mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* Check the parameters */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + } + else + { + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Initialize the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check UART instance */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + + /* LIN mode limited to 16-bit oversampling only */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + return HAL_ERROR; + } + /* LIN mode limited to 8-bit data length */ + if (huart->Init.WordLength != UART_WORDLENGTH_8B) + { + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In LIN mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod Specifies the UART wakeup method. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark + * @note If the user resorts to idle line detection wake up, the Address parameter + * is useless and ignored by the initialization function. + * @note If the user resorts to address mark wake up, the address length detection + * is configured by default to 4 bits only. For the UART to be able to + * manage 6-, 7- or 8-bit long addresses detection, the API + * HAL_MultiProcessorEx_AddressLength_Set() must be called after + * HAL_MultiProcessor_Init(). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the wake up method parameter */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In multiprocessor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + { + /* If address mark wake up method is chosen, set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); + } + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief DeInitialize the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Initialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used to override the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = pCallback; + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = pCallback; + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = pCallback; + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two mode of transfer: + (+) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (+) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (+) HAL_UART_Transmit() + (+) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (+) HAL_UART_Transmit_IT() + (+) HAL_UART_Receive_IT() + (+) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (+) HAL_UART_Transmit_DMA() + (+) HAL_UART_Receive_DMA() + (+) HAL_UART_DMAPause() + (+) HAL_UART_DMAResume() + (+) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (+) HAL_UART_TxHalfCpltCallback() + (+) HAL_UART_TxCpltCallback() + (+) HAL_UART_RxHalfCpltCallback() + (+) HAL_UART_RxCpltCallback() + (+) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (+) HAL_UART_Abort() + (+) HAL_UART_AbortTransmit() + (+) HAL_UART_AbortReceive() + (+) HAL_UART_Abort_IT() + (+) HAL_UART_AbortTransmit_IT() + (+) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (+) HAL_UART_AbortCpltCallback() + (+) HAL_UART_AbortTransmitCpltCallback() + (+) HAL_UART_AbortReceiveCpltCallback() + + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced + reception services: + (+) HAL_UARTEx_RxEventCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (const uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + huart->TxXferCount--; + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + huart->RxXferCount--; + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + huart->TxISR = NULL; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Configure Tx interrupt processing */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT_FIFOEN; + } + else + { + huart->TxISR = UART_TxISR_8BIT_FIFOEN; + } + + /* Enable the TX FIFO threshold interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + } + else + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT; + } + else + { + huart->TxISR = UART_TxISR_8BIT; + } + + /* Enable the Transmit Data Register Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + return (UART_Start_Receive_IT(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint16_t nbByte = Size; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + if (huart->hdmatx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((huart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((huart->hdmatx->LinkedListQueue != NULL) && (huart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)huart->pTxBuffPtr; + + /* Set DMA destination address */ + huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&huart->Instance->TDR; + + /* Enable the UART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(huart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the UART transmit DMA channel */ + status = HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, nbByte); + } + + if (status != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + return (UART_Start_Receive_DMA(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + /* Suspend the UART DMA Tx channel : use blocking DMA Suspend API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + huart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + /* Suspend the UART DMA Rx channel : use blocking DMA Suspend API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Set the UART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + huart->hdmarx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Resume the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(huart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Resume the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMAEx_Resume(huart->hdmarx) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t abortcplt = 1U; + + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + } + + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_ISR_IDLE) != 0U) + && ((cr1its & USART_ISR_IDLE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (huart->hdmarx->Mode != DMA_LINKEDLIST_CIRCULAR) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + } + else + { +#endif /* HAL_DMA_MODULE_ENABLED */ + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; +#if defined(HAL_DMA_MODULE_ENABLED) + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); + + /* UART Rx state is not reset as a reception process might be ongoing. + If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ + HAL_UARTEx_WakeupCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + if (huart->TxISR != NULL) + { + huart->TxISR(huart); + } + return; + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + UART_EndTransmit_IT(huart); + return; + } + + /* UART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + huart->TxFifoEmptyCallback(huart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_UARTEx_TxFifoEmptyCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + huart->RxFifoFullCallback(huart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_UARTEx_RxFifoFullCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode + (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode + (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode + (+) UART_SetConfig() API configures the UART peripheral + (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features + (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter + (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver + (+) HAL_LIN_SendBreak() API transmits the break characters +@endverbatim + * @{ + */ + +/** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); + } +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable UART in mute mode (does not mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable USART mute mode by setting the MME bit in the CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Enter UART mute mode (means UART actually enters mute mode). + * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. + * @param huart UART handle. + * @retval None + */ +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +} + +/** + * @brief Enable the UART transmitter and disable the UART receiver. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the UART receiver and disable the UART transmitter. + * @param huart UART handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + + +/** + * @brief Transmit break characters. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief UART Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the UART handle state. + (+) Return the UART handle error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the UART handle state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) +{ + uint32_t temp1; + uint32_t temp2; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART handle error code. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t lpuart_ker_ck_pres; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + if (UART_INSTANCE_LOWPOWER(huart)) + { + assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); + } + else + { + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + } + + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + + if (!(UART_INSTANCE_LOWPOWER(huart))) + { + tmpreg |= huart->Init.OneBitSampling; + } + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ + MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + + /* Check LPUART instance */ + if (UART_INSTANCE_LOWPOWER(huart)) + { + /* Retrieve frequency clock */ + switch (clocksource) + { + case UART_CLOCKSOURCE_PLL2Q: + pclk = HAL_RCC_GetPLL2QFreq(); + break; + case UART_CLOCKSOURCE_PLL3Q: + pclk = HAL_RCC_GetPLL3QFreq(); + break; + case UART_CLOCKSOURCE_PCLK4: + pclk = HAL_RCC_GetPCLK4Freq(); + break; + case UART_CLOCKSOURCE_HSI: + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); + } + else + { + pclk = (uint32_t) HSI_VALUE; + } + break; + case UART_CLOCKSOURCE_CSI: + pclk = (uint32_t) CSI_VALUE; + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + /* If proper clock source reported */ + if (pclk != 0U) + { + /* Compute clock after Prescaler */ + lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); + + /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ + if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || + (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) + { + ret = HAL_ERROR; + } + else + { + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if (pclk != 0) */ + } + /* Check UART Over Sampling to set Baud Rate Register */ + else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + break; + case UART_CLOCKSOURCE_PLL2Q: + pclk = HAL_RCC_GetPLL2QFreq(); + break; + case UART_CLOCKSOURCE_PLL3Q: + pclk = HAL_RCC_GetPLL3QFreq(); + break; + case UART_CLOCKSOURCE_HSI: + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); + } + else + { + pclk = (uint32_t) HSI_VALUE; + } + break; + case UART_CLOCKSOURCE_CSI: + pclk = (uint32_t) CSI_VALUE; + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + { + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + } + } + else + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + break; + case UART_CLOCKSOURCE_PLL2Q: + pclk = HAL_RCC_GetPLL2QFreq(); + break; + case UART_CLOCKSOURCE_PLL3Q: + pclk = HAL_RCC_GetPLL3QFreq(); + break; + case UART_CLOCKSOURCE_HSI: + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); + } + else + { + pclk = (uint32_t) HSI_VALUE; + } + break; + case UART_CLOCKSOURCE_CSI: + pclk = (uint32_t) CSI_VALUE; + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + if (pclk != 0U) + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = (uint16_t)usartdiv; + } + else + { + ret = HAL_ERROR; + } + } + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + huart->NbTxDataToProcess = 1; + huart->NbRxDataToProcess = 1; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + return ret; +} + +/** + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + } +} + +/** + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param huart UART handle. + * @param Flag Specifies the UART flag to check + * @param Status The actual Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + + return HAL_TIMEOUT; + } + + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Configure Rx interrupt processing */ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + } + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + return HAL_OK; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint16_t nbByte = Size; + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((huart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((huart->hdmarx->LinkedListQueue != NULL) && (huart->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&huart->Instance->RDR; + + /* Set DMA destination address */ + huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)huart->pRxBuffPtr; + + /* Enable the UART receive DMA channel */ + status = HAL_DMAEx_List_Start_IT(huart->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the UART receive DMA channel */ + status = HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, nbByte); + } + + if (status != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->RxState to ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + + /* Enable the UART Parity Error Interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, TXFT interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; +} + + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA UART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + huart->TxXferCount = 0U; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + huart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize / 2U); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + huart->TxXferCount = 0U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + huart->RxXferCount = 0U; + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->RxXferCount = 0U; + huart->TxXferCount = 0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->TxXferCount = 0U; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) +{ + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_8BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_16BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_uart_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_uart_ex.c new file mode 100644 index 00000000000..f67f58b9468 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_uart_ex.c @@ -0,0 +1,1044 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_uart_ex.c + * @author MCD Application Team + * @brief Extended UART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### UART peripheral extended features ##### + ============================================================================== + + (#) Declare a UART_HandleTypeDef handle structure. + + (#) For the UART RS485 Driver Enable mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When UART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup UARTEx UARTEx + * @brief UART Extended HAL module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UARTEX_Private_Constants UARTEx Private Constants + * @{ + */ +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 16U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 16U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UARTEx_Private_Functions UARTEx Private Functions + * @{ + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + * @{ + */ + +/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Extended Initialization and Configuration Functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration + procedures (details for the procedures are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param Polarity Select the driver enable polarity. + * This parameter can be one of the following values: + * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + * @param AssertionTime Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) +{ + uint32_t temp; + + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(Polarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions + * @brief Extended functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of Wakeup and FIFO mode related callback functions. + + (#) Wakeup from Stop mode Callback: + (+) HAL_UARTEx_WakeupCallback() + + (#) TX/RX Fifos Callbacks: + (+) HAL_UARTEx_RxFifoFullCallback() + (+) HAL_UARTEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +/** + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + +/** + * @brief UART RX Fifo full callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief UART TX Fifo empty callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. + (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode + trigger: address match, Start Bit detection or RXNE bit status. + (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode + (+) HAL_UARTEx_DisableStopMode() API disables the above functionality + (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (+) Detection of inactivity period (RX line has not been active for a given period). + (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + (++) RX inactivity detected by RTO, i.e. line has been in idle state + for a programmable time, after last received byte. + (+) Detection that a specific character has been received. + + (#) There are two mode of transfer: + (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (+) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (+) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (+) HAL_UARTEx_ReceiveToIdle_DMA() + +@endverbatim + * @{ + */ + +/** + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection; + * this API allows to enable longer addresses detection (6-, 7- or 8-bit + * long). + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + * @param huart UART handle. + * @param AddressLength This parameter can be one of the following values: + * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the address length parameter */ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Set Wakeup from Stop mode interrupt flag selection. + * @note It is the application responsibility to enable the interrupt used as + * usart_wkup interrupt source before entering low-power mode. + * @param huart UART handle. + * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUP_ON_ADDRESS + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* check the wake-up from stop mode UART instance */ + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the wake-up selection scheme */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + { + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + status = HAL_TIMEOUT; + } + else + { + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Enable UART Stop Mode. + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UESM bit */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UESM bit */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_ENABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Enable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_DISABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param huart UART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_TXFIFO_THRESHOLD_1_8 + * @arg @ref UART_TXFIFO_THRESHOLD_1_4 + * @arg @ref UART_TXFIFO_THRESHOLD_1_2 + * @arg @ref UART_TXFIFO_THRESHOLD_3_4 + * @arg @ref UART_TXFIFO_THRESHOLD_7_8 + * @arg @ref UART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update TX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param huart UART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_RXFIFO_THRESHOLD_1_8 + * @arg @ref UART_RXFIFO_THRESHOLD_1_4 + * @arg @ref UART_RXFIFO_THRESHOLD_1_2 + * @arg @ref UART_RXFIFO_THRESHOLD_3_4 + * @arg @ref UART_RXFIFO_THRESHOLD_7_8 + * @arg @ref UART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update RX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data + * is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received + * (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + (void)UART_Start_Receive_IT(huart, pData, Size); + + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value : + * In Interrupt Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one) + * In DMA Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one). + * In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return (huart->RxEventType); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UARTEx_Private_Functions + * @{ + */ + +/** + * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); +} + +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the UART configuration registers. + * @param huart UART handle. + * @retval None + */ +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (huart->FifoMode == UART_FIFOMODE_DISABLE) + { + huart->NbTxDataToProcess = 1U; + huart->NbRxDataToProcess = 1U; + } + else + { + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_usart.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_usart.c new file mode 100644 index 00000000000..c6dd4ef7e27 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_usart.c @@ -0,0 +1,3959 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_usart.c + * @author MCD Application Team + * @brief USART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter + * Peripheral (USART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The USART HAL driver can be used as follows: + + (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart). + (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) USART pins configuration: + (+++) Enable the clock for the USART GPIOs. + (+++) Configure these USART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(), + HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) USART interrupts handling: + -@@- The specific USART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process. + (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA() + HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode + (Receiver/Transmitter) in the husart handle Init structure. + + (#) Initialize the USART registers by calling the HAL_USART_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_USART_MspInit(&husart) API. + + [..] + (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's + HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and + HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_USART_RegisterCallback() to register a user callback. + Function HAL_USART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) TxRxCpltCallback : Tx Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : USART MspInit. + (+) MspDeInitCallback : USART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_USART_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) TxRxCpltCallback : Tx Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : USART MspInit. + (+) MspDeInitCallback : USART MspDeInit. + + [..] + By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_USART_Init() + and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit() + or HAL_USART_Init() function. + + [..] + When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup USART USART + * @brief HAL USART Synchronous module driver + * @{ + */ + +#ifdef HAL_USART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup USART_Private_Constants USART Private Constants + * @{ + */ +#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */ +#define USART_TEACK_REACK_TIMEOUT 1000U /*!< USART TX or RX enable acknowledge time-out value */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 | \ + USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by USART_SetConfig API */ + +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \ + USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \ + USART_CR2_DIS_NSS)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART or USART CR3 fields of parameters set by USART_SetConfig API */ + +#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */ +#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup USART_Private_Functions + * @{ + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +static void USART_EndTransfer(USART_HandleTypeDef *husart); +#if defined(HAL_DMA_MODULE_ENABLED) +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void USART_DMAError(DMA_HandleTypeDef *hdma); +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); +static void USART_TxISR_8BIT(USART_HandleTypeDef *husart); +static void USART_TxISR_16BIT(USART_HandleTypeDef *husart); +static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_EndTransmit_IT(USART_HandleTypeDef *husart); +static void USART_RxISR_8BIT(USART_HandleTypeDef *husart); +static void USART_RxISR_16BIT(USART_HandleTypeDef *husart); +static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USART + in asynchronous and in synchronous modes. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) USART polarity + (++) USART phase + (++) USART LastBit + (++) Receiver/transmitter modes + + [..] + The HAL_USART_Init() function follows the USART synchronous configuration + procedure (details for the procedure are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible USART formats are listed in the + following table. + + Table 1. USART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | USART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the USART mode according to the specified + * parameters in the USART_InitTypeDef and initialize the associated handle. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) +{ + /* Check the USART handle allocation */ + if (husart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_USART_INSTANCE(husart->Instance)); + + if (husart->State == HAL_USART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + husart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + USART_InitCallbacksToDefault(husart); + + if (husart->MspInitCallback == NULL) + { + husart->MspInitCallback = HAL_USART_MspInit; + } + + /* Init the low level hardware */ + husart->MspInitCallback(husart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_USART_MspInit(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + + husart->State = HAL_USART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_USART_DISABLE(husart); + + /* Set the Usart Communication parameters */ + if (USART_SetConfig(husart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register. + */ + husart->Instance->CR2 &= ~USART_CR2_LINEN; + husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + + /* Enable the Peripheral */ + __HAL_USART_ENABLE(husart); + + /* TEACK and/or REACK to check before moving husart->State to Ready */ + return (USART_CheckIdleState(husart)); +} + +/** + * @brief DeInitialize the USART peripheral. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) +{ + /* Check the USART handle allocation */ + if (husart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_USART_INSTANCE(husart->Instance)); + + husart->State = HAL_USART_STATE_BUSY; + + husart->Instance->CR1 = 0x0U; + husart->Instance->CR2 = 0x0U; + husart->Instance->CR3 = 0x0U; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + if (husart->MspDeInitCallback == NULL) + { + husart->MspDeInitCallback = HAL_USART_MspDeInit; + } + /* DeInit the low level hardware */ + husart->MspDeInitCallback(husart); +#else + /* DeInit the low level hardware */ + HAL_USART_MspDeInit(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Initialize the USART MSP. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the USART MSP. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User USART Callback + * To be used to override the weak predefined callback + * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID + * @param husart usart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status ++ */ +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (husart->State == HAL_USART_STATE_READY) + { + switch (CallbackID) + { + case HAL_USART_TX_HALFCOMPLETE_CB_ID : + husart->TxHalfCpltCallback = pCallback; + break; + + case HAL_USART_TX_COMPLETE_CB_ID : + husart->TxCpltCallback = pCallback; + break; + + case HAL_USART_RX_HALFCOMPLETE_CB_ID : + husart->RxHalfCpltCallback = pCallback; + break; + + case HAL_USART_RX_COMPLETE_CB_ID : + husart->RxCpltCallback = pCallback; + break; + + case HAL_USART_TX_RX_COMPLETE_CB_ID : + husart->TxRxCpltCallback = pCallback; + break; + + case HAL_USART_ERROR_CB_ID : + husart->ErrorCallback = pCallback; + break; + + case HAL_USART_ABORT_COMPLETE_CB_ID : + husart->AbortCpltCallback = pCallback; + break; + + case HAL_USART_RX_FIFO_FULL_CB_ID : + husart->RxFifoFullCallback = pCallback; + break; + + case HAL_USART_TX_FIFO_EMPTY_CB_ID : + husart->TxFifoEmptyCallback = pCallback; + break; + + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = pCallback; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (husart->State == HAL_USART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = pCallback; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an USART Callback + * USART callaback is redirected to the weak predefined callback + * @note The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID + * @param husart usart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_USART_STATE_READY == husart->State) + { + switch (CallbackID) + { + case HAL_USART_TX_HALFCOMPLETE_CB_ID : + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_USART_TX_COMPLETE_CB_ID : + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_USART_RX_HALFCOMPLETE_CB_ID : + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_USART_RX_COMPLETE_CB_ID : + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_USART_TX_RX_COMPLETE_CB_ID : + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_USART_ERROR_CB_ID : + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_USART_ABORT_COMPLETE_CB_ID : + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_USART_RX_FIFO_FULL_CB_ID : + husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_USART_TX_FIFO_EMPTY_CB_ID : + husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; + + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_USART_STATE_RESET == husart->State) + { + switch (CallbackID) + { + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = HAL_USART_MspInit; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = HAL_USART_MspDeInit; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group2 IO operation functions + * @brief USART Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART synchronous + data transfers. + + [..] The USART supports master mode only: it cannot receive or send data related to an input + clock (SCLK is always an output). + + [..] + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated USART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (++) HAL_USART_Transmit() in simplex mode + (++) HAL_USART_Receive() in full duplex receive only + (++) HAL_USART_TransmitReceive() in full duplex mode + + (#) Non-Blocking mode API's with Interrupt are : + (++) HAL_USART_Transmit_IT() in simplex mode + (++) HAL_USART_Receive_IT() in full duplex receive only + (++) HAL_USART_TransmitReceive_IT() in full duplex mode + (++) HAL_USART_IRQHandler() + + (#) No-Blocking mode API's with DMA are : + (++) HAL_USART_Transmit_DMA() in simplex mode + (++) HAL_USART_Receive_DMA() in full duplex receive only + (++) HAL_USART_TransmitReceive_DMA() in full duplex mode + (++) HAL_USART_DMAPause() + (++) HAL_USART_DMAResume() + (++) HAL_USART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (++) HAL_USART_TxCpltCallback() + (++) HAL_USART_RxCpltCallback() + (++) HAL_USART_TxHalfCpltCallback() + (++) HAL_USART_RxHalfCpltCallback() + (++) HAL_USART_ErrorCallback() + (++) HAL_USART_TxRxCpltCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_USART_Abort() + (++) HAL_USART_Abort_IT() + + (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided: + (++) HAL_USART_AbortCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify + error type, and HAL_USART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on USART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, + and HAL_USART_ErrorCallback() user callback is executed. + +@endverbatim + * @{ + */ + +/** + * @brief Simplex send an amount of data in blocking mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @param husart USART handle. + * @param pTxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout) +{ + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + ptxdata8bits = NULL; + ptxdata16bits = (const uint16_t *) pTxData; + } + else + { + ptxdata8bits = pTxData; + ptxdata16bits = NULL; + } + + /* Check the remaining data to be sent */ + while (husart->TxXferCount > 0U) + { + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (ptxdata8bits == NULL) + { + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU); + ptxdata16bits++; + } + else + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU); + ptxdata8bits++; + } + + husart->TxXferCount--; + } + + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear Transmission Complete Flag */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Clear overrun flag and discard the received data */ + __HAL_USART_CLEAR_OREFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + + /* At end of Tx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. + * @param husart USART handle. + * @param pRxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *prxdata8bits; + uint16_t *prxdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + husart->RxXferSize = Size; + husart->RxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + USART_MASK_COMPUTATION(husart); + uhMask = husart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + prxdata8bits = NULL; + prxdata16bits = (uint16_t *) pRxData; + } + else + { + prxdata8bits = pRxData; + prxdata16bits = NULL; + } + + /* as long as data have to be received */ + while (husart->RxXferCount > 0U) + { + if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) + { + /* Wait until TXE flag is set to send dummy byte in order to generate the + * clock for the slave to send data. + * Whatever the frame length (7, 8 or 9-bit long), the same dummy value + * can be written for all the cases. */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF); + } + + /* Wait for RXNE Flag */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (prxdata8bits == NULL) + { + *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); + prxdata16bits++; + } + else + { + *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + prxdata8bits++; + } + + husart->RxXferCount--; + + } + + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* At end of Rx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send and Receive an amount of data in blocking mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) +{ + uint8_t *prxdata8bits; + uint16_t *prxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; + uint16_t uhMask; + uint16_t rxdatacount; + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + husart->RxXferSize = Size; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + husart->RxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + USART_MASK_COMPUTATION(husart); + uhMask = husart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + prxdata8bits = NULL; + ptxdata8bits = NULL; + ptxdata16bits = (const uint16_t *) pTxData; + prxdata16bits = (uint16_t *) pRxData; + } + else + { + prxdata8bits = pRxData; + ptxdata8bits = pTxData; + ptxdata16bits = NULL; + prxdata16bits = NULL; + } + + if ((husart->TxXferCount == 0x01U) || (husart->SlaveMode == USART_SLAVEMODE_ENABLE)) + { + /* Wait until TXE flag is set to send data */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (ptxdata8bits == NULL) + { + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); + ptxdata16bits++; + } + else + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU)); + ptxdata8bits++; + } + + husart->TxXferCount--; + } + + /* Check the remain data to be sent */ + /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + rxdatacount = husart->RxXferCount; + while ((husart->TxXferCount > 0U) || (rxdatacount > 0U)) + { + if (husart->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (ptxdata8bits == NULL) + { + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); + ptxdata16bits++; + } + else + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU)); + ptxdata8bits++; + } + + husart->TxXferCount--; + } + + if (husart->RxXferCount > 0U) + { + /* Wait for RXNE Flag */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (prxdata8bits == NULL) + { + *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); + prxdata16bits++; + } + else + { + *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + prxdata8bits++; + } + + husart->RxXferCount--; + } + rxdatacount = husart->RxXferCount; + } + + /* At end of TxRx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @param husart USART handle. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) +{ + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + husart->TxISR = NULL; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + /* The USART Error Interrupts: (Frame error, noise error, overrun error) + are not managed by the USART Transmit Process to avoid the overrun interrupt + when the usart mode is configured for transmit and receive "USART_MODE_TX_RX" + to benefit for the frame error and noise interrupts the usart mode should be + configured only for transmit "USART_MODE_TX" */ + + /* Configure Tx interrupt processing */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT_FIFOEN; + } + else + { + husart->TxISR = USART_TxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the TX FIFO threshold interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT); + } + else + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT; + } + else + { + husart->TxISR = USART_TxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Transmit Data Register Empty Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. + * @param husart USART handle. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) +{ + uint16_t nb_dummy_data; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->RxXferCount = Size; + husart->RxISR = NULL; + + USART_MASK_COMPUTATION(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Configure Rx interrupt processing */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->RxISR = USART_RxISR_16BIT_FIFOEN; + } + else + { + husart->RxISR = USART_RxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->RxISR = USART_RxISR_16BIT; + } + else + { + husart->RxISR = USART_RxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error and Data Register not empty Interrupts */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + + if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) + { + /* Send dummy data in order to generate the clock for the Slave to send the next data. + When FIFO mode is disabled only one data must be transferred. + When FIFO mode is enabled data must be transmitted until the RX FIFO reaches its threshold. + */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0U ; nb_dummy_data--) + { + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + else + { + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->RxXferCount = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + USART_MASK_COMPUTATION(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX_RX; + + /* Configure TxRx interrupt processing */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT_FIFOEN; + husart->RxISR = USART_RxISR_16BIT_FIFOEN; + } + else + { + husart->TxISR = USART_TxISR_8BIT_FIFOEN; + husart->RxISR = USART_RxISR_8BIT_FIFOEN; + } + + /* Process Locked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the TX and RX FIFO Threshold interrupts */ + SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE)); + } + else + { + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT; + husart->RxISR = USART_RxISR_16BIT; + } + else + { + husart->TxISR = USART_TxISR_8BIT; + husart->RxISR = USART_RxISR_8BIT; + } + + /* Process Locked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + + /* Enable the USART Transmit Data Register Empty Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Send an amount of data in DMA mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @param husart USART handle. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + const uint32_t *tmp; + uint16_t nbByte = Size; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + if (husart->hdmatx != NULL) + { + /* Set the USART DMA transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + + /* Set the DMA error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + tmp = (const uint32_t *)&pTxData; + + /* Check linked list mode */ + if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp; + + /* Set DMA destination address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->TDR; + + /* Enable the USART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the USART transmit DMA channel */ + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); + } + } + + if (status == HAL_OK) + { + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the USART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. + * @param husart USART handle. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t *tmp = (uint32_t *)&pRxData; + uint16_t nbByte = Size; + + /* Check that a Rx process is not already ongoing */ + if (husart->State == HAL_USART_STATE_READY) + { + if ((pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->pTxBuffPtr = pRxData; + husart->TxXferSize = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + if (husart->hdmarx != NULL) + { + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; + + /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((husart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmarx->LinkedListQueue != NULL) && (husart->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->RDR; + + /* Set DMA destination address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = *(uint32_t *)tmp; + + /* Enable the USART receive DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the USART receive DMA channel */ + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, nbByte); + } + } + + if ((status == HAL_OK) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Enable the USART transmit DMA channel: the transmit channel is used in order + to generate in the non-blocking mode the clock to the slave device, + this mode isn't a simplex receive mode but a full-duplex receive mode */ + + /* Set the USART DMA Tx Complete and Error callback to Null */ + if (husart->hdmatx != NULL) + { + husart->hdmatx->XferErrorCallback = NULL; + husart->hdmatx->XferHalfCpltCallback = NULL; + husart->hdmatx->XferCpltCallback = NULL; + + /* Check linked list mode */ + if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(uint32_t *)tmp; + + /* Set DMA destination address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->TDR; + + /* Enable the USART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); + } + } + } + + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + if ((husart->hdmarx != NULL) && ((husart->hdmarx->Mode & DMA_LINKEDLIST) != DMA_LINKEDLIST)) + { + status = HAL_DMA_Abort(husart->hdmarx); + } + + /* No need to check on error code */ + UNUSED(status); + + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. + * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received/sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + HAL_StatusTypeDef status; + const uint32_t *tmp; + uint16_t nbByte = Size; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX_RX; + + if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL)) + { + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + + /* Set the USART DMA Tx transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + + /* Set the USART DMA Tx transfer error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; + + /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + tmp = (uint32_t *)&pRxData; + if ((husart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmarx->LinkedListQueue != NULL) && (husart->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->RDR; + + /* Set DMA destination address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp; + + /* Enable the USART receive DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the USART receive DMA channel */ + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, nbByte); + } + + /* Enable the USART transmit DMA channel */ + if (status == HAL_OK) + { + tmp = (const uint32_t *)&pTxData; + + /* Check linked list mode */ + if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp; + + /* Set DMA destination address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->TDR; + + /* Enable the USART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); + } + } + } + else + { + status = HAL_ERROR; + } + + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + if ((husart->hdmarx != NULL) && ((husart->hdmarx->Mode & DMA_LINKEDLIST) != DMA_LINKEDLIST)) + { + status = HAL_DMA_Abort(husart->hdmarx); + } + + /* No need to check on error code */ + UNUSED(status); + + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + + /* Process Locked */ + __HAL_LOCK(husart); + + if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) && + (state == HAL_USART_STATE_BUSY_TX)) + { + /* Suspend the USART DMA Tx channel : use blocking DMA Suspend API (no callback) */ + if (husart->hdmatx != NULL) + { + /* Set the USART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + husart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Set the USART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + husart->hdmarx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + + if (state == HAL_USART_STATE_BUSY_TX_RX) + { + /* Set the USART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + husart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + + /* Process Locked */ + __HAL_LOCK(husart); + + if (state == HAL_USART_STATE_BUSY_TX) + { + /* Resume the USART DMA Tx channel */ + if (husart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(husart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + /* Clear the Overrun flag before resuming the Rx transfer*/ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Resume the USART DMA Rx channel */ + if (husart->hdmarx != NULL) + { + if (HAL_DMAEx_Resume(husart->hdmarx) != HAL_OK) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_ERROR; + } + } + + if (state == HAL_USART_STATE_BUSY_TX_RX) + { + /* Resume the USART DMA Tx channel */ + if (husart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(husart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() / + HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + /* Disable the USART Tx/Rx DMA requests */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA tx channel */ + if (husart->hdmatx != NULL) + { + if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + /* Abort the USART DMA rx channel */ + if (husart->hdmarx != NULL) + { + if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + USART_EndTransfer(husart); + husart->State = HAL_USART_STATE_READY; + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param husart USART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable USART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) +{ + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the USART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the USART DMA Tx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (husart->hdmatx != NULL) + { + /* Set the USART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + husart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Abort the USART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (husart->hdmarx != NULL) + { + /* Set the USART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + husart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx and Rx transfer counters */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Reset Handle ErrorCode to No Error */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param husart USART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable USART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) +{ + uint32_t abortcplt = 1U; + + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (husart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if USART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback; + } + else + { + husart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (husart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if USART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback; + } + else + { + husart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Abort the USART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at USART level */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (husart->hdmatx != NULL) + { + /* USART Tx DMA Abort callback has already been initialised : + will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK) + { + husart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Abort the USART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (husart->hdmarx != NULL) + { + /* USART Rx DMA Abort callback has already been initialised : + will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + { + husart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle USART interrupt request. + * @param husart USART handle. + * @retval None + */ +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) +{ + uint32_t isrflags = READ_REG(husart->Instance->ISR); + uint32_t cr1its = READ_REG(husart->Instance->CR1); + uint32_t cr3its = READ_REG(husart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | + USART_ISR_UDR)); + if (errorflags == 0U) + { + /* USART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (husart->RxISR != NULL) + { + husart->RxISR(husart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))) + { + /* USART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); + + husart->ErrorCode |= HAL_USART_ERROR_PE; + } + + /* USART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); + + husart->ErrorCode |= HAL_USART_ERROR_FE; + } + + /* USART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); + + husart->ErrorCode |= HAL_USART_ERROR_NE; + } + + /* USART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); + + husart->ErrorCode |= HAL_USART_ERROR_ORE; + } + + /* USART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF); + + husart->ErrorCode |= HAL_USART_ERROR_RTO; + } + + /* USART SPI slave underrun error interrupt occurred -------------------------*/ + if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + /* Ignore SPI slave underrun errors when reception is going on */ + if (husart->State == HAL_USART_STATE_BUSY_RX) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + return; + } + else + { + __HAL_USART_CLEAR_UDRFLAG(husart); + husart->ErrorCode |= HAL_USART_ERROR_UDR; + } + } + + /* Call USART Error Call back function if need be --------------------------*/ + if (husart->ErrorCode != HAL_USART_ERROR_NONE) + { + /* USART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (husart->RxISR != NULL) + { + husart->RxISR(husart); + } + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE; + if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) || + (errorcode != 0U)) + { + /* Blocking error : transfer is aborted + Set the USART state ready to be able to start again the process, + Disable Interrupts, and disable DMA requests, if ongoing */ + USART_EndTransfer(husart); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the USART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); + + /* Abort the USART DMA Tx channel */ + if (husart->hdmatx != NULL) + { + /* Set the USART Tx DMA Abort callback to NULL : no callback + executed at end of DMA abort procedure */ + husart->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA TX */ + (void)HAL_DMA_Abort_IT(husart->hdmatx); + } + + /* Abort the USART DMA Rx channel */ + if (husart->hdmarx != NULL) + { + /* Set the USART Rx DMA Abort callback : + will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ + husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + { + /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */ + husart->hdmarx->XferAbortCallback(husart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Call user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + + /* USART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + if (husart->TxISR != NULL) + { + husart->TxISR(husart); + } + return; + } + + /* USART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + USART_EndTransmit_IT(husart); + return; + } + + /* USART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + husart->TxFifoEmptyCallback(husart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_USARTEx_TxFifoEmptyCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + return; + } + + /* USART RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + husart->RxFifoFullCallback(husart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_USARTEx_RxFifoFullCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_RxHalfCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Tx/Rx Transfers completed callback for the non-blocking process. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_TxRxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief USART error callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief USART Abort Complete callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief USART Peripheral State and Error functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the USART handle state + (+) Return the USART handle error code + +@endverbatim + * @{ + */ + + +/** + * @brief Return the USART handle state. + * @param husart pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART. + * @retval USART handle state + */ +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart) +{ + return husart->State; +} + +/** + * @brief Return the USART error code. + * @param husart pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART. + * @retval USART handle Error Code + */ +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart) +{ + return husart->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Functions USART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param husart USART handle. + * @retval none + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart) +{ + /* Init the USART Callback settings */ + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ +} +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion). + * @param husart USART handle. + * @retval None + */ +static void USART_EndTransfer(USART_HandleTypeDef *husart) +{ + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + + /* At end of process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA USART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + husart->TxXferCount = 0U; + + if (husart->State == HAL_USART_STATE_BUSY_TX) + { + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + } + /* DMA Circular mode */ + else + { + if (husart->State == HAL_USART_STATE_BUSY_TX) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Complete Callback */ + husart->TxCpltCallback(husart); +#else + /* Call legacy weak Tx Complete Callback */ + HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief DMA USART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Half Complete Callback */ + husart->TxHalfCpltCallback(husart); +#else + /* Call legacy weak Tx Half Complete Callback */ + HAL_USART_TxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode*/ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + husart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit + in USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + /* similarly, disable the DMA TX transfer that was started to provide the + clock to the slave device */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + if (husart->State == HAL_USART_STATE_BUSY_RX) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + husart->State = HAL_USART_STATE_READY; + } + /* DMA circular mode */ + else + { + if (husart->State == HAL_USART_STATE_BUSY_RX) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief DMA USART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Half Complete Callback */ + husart->RxHalfCpltCallback(husart); +#else + /* Call legacy weak Rx Half Complete Callback */ + HAL_USART_RxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAError(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; + USART_EndTransfer(husart); + + husart->ErrorCode |= HAL_USART_ERROR_DMA; + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + husart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (husart->hdmarx != NULL) + { + if (husart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +} + + +/** + * @brief DMA USART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + husart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (husart->hdmatx != NULL) + { + if (husart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Handle USART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param husart USART handle. + * @param Flag Specifies the USART flag to check. + * @param Status the actual Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Configure the USART peripheral. + * @param husart USART handle. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) +{ + uint32_t tmpreg; + USART_ClockSourceTypeDef clocksource; + HAL_StatusTypeDef ret = HAL_OK; + uint16_t brrtemp; + uint32_t usartdiv = 0x00000000; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); + assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); + assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); + assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); + assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength)); + assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); + assert_param(IS_USART_PARITY(husart->Init.Parity)); + assert_param(IS_USART_MODE(husart->Init.Mode)); + assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE and RE bits and configure + * the USART Word Length, Parity and Mode: + * set the M bits according to husart->Init.WordLength value + * set PCE and PS bits according to husart->Init.Parity value + * set TE and RE bits according to husart->Init.Mode value + * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ + tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; + MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*---------------------------- USART CR2 Configuration ---------------------*/ + /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: + * set CPOL bit according to husart->Init.CLKPolarity value + * set CPHA bit according to husart->Init.CLKPhase value + * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) + * set STOP[13:12] bits according to husart->Init.StopBits value */ + tmpreg = (uint32_t)(USART_CLOCK_ENABLE); + tmpreg |= (uint32_t)husart->Init.CLKLastBit; + tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); + tmpreg |= (uint32_t)husart->Init.StopBits; + MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg); + + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */ + MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ + USART_GETCLOCKSOURCE(husart, clocksource); + + switch (clocksource) + { + case USART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_PLL2Q: + pclk = HAL_RCC_GetPLL2QFreq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_PLL3Q: + pclk = HAL_RCC_GetPLL3QFreq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_HSI: + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + usartdiv = (uint32_t)(USART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), + husart->Init.BaudRate, husart->Init.ClockPrescaler)); + } + else + { + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + } + break; + case USART_CLOCKSOURCE_CSI: + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(CSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_LSE: + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + default: + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */ + if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + husart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + husart->NbTxDataToProcess = 1U; + husart->NbRxDataToProcess = 1U; + + /* Clear ISR function pointers */ + husart->RxISR = NULL; + husart->TxISR = NULL; + + return ret; +} + +/** + * @brief Check the USART Idle State. + * @param husart USART handle. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) +{ + uint32_t tickstart; + + /* Initialize the USART ErrorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + /* Check if the Receiver is enabled */ + if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the USART state*/ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + if (husart->TxXferCount == 0U) + { + /* Disable the USART Transmit data register empty interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + else + { + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF); + husart->pTxBuffPtr++; + husart->TxXferCount--; + } + } +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + const uint16_t *tmp; + + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + if (husart->TxXferCount == 0U) + { + /* Disable the USART Transmit data register empty interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + else + { + tmp = (const uint16_t *) husart->pTxBuffPtr; + husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); + husart->pTxBuffPtr += 2U; + husart->TxXferCount--; + } + } +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (husart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + + break; /* force exit loop */ + } + else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) + { + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF); + husart->pTxBuffPtr++; + husart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + const uint16_t *tmp; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (husart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + + break; /* force exit loop */ + } + else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) + { + tmp = (const uint16_t *) husart->pTxBuffPtr; + husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); + husart->pTxBuffPtr += 2U; + husart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Wraps up transmission in non-blocking mode. + * @param husart Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +static void USART_EndTransmit_IT(USART_HandleTypeDef *husart) +{ + /* Disable the USART Transmit Complete Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TC); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + /* Clear TxISR function pointer */ + husart->TxISR = NULL; + + if (husart->State == HAL_USART_STATE_BUSY_TX) + { + /* Clear overrun flag and discard the received data */ + __HAL_USART_CLEAR_OREFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Tx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Complete Callback */ + husart->TxCpltCallback(husart); +#else + /* Call legacy weak Tx Complete Callback */ + HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if (husart->RxXferCount == 0U) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t uhMask = husart->Mask; + uint32_t txftie; + + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + husart->pRxBuffPtr++; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } +} + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t *tmp; + uint16_t uhMask = husart->Mask; + uint32_t txftie; + + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + tmp = (uint16_t *) husart->pRxBuffPtr; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + husart->pRxBuffPtr += 2U; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } +} + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t rxdatacount; + uint16_t uhMask = husart->Mask; + uint16_t nb_rx_data; + uint32_t txftie; + + /* Check that a Rx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + { + if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) + { + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + husart->pRxBuffPtr++; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = husart->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess)) + { + /* Disable the USART RXFT interrupt*/ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + husart->RxISR = USART_RxISR_8BIT; + + /* Enable the USART Data Register Not Empty interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t rxdatacount; + uint16_t *tmp; + uint16_t uhMask = husart->Mask; + uint16_t nb_rx_data; + uint32_t txftie; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + { + if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) + { + tmp = (uint16_t *) husart->pRxBuffPtr; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + husart->pRxBuffPtr += 2U; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = husart->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess)) + { + /* Disable the USART RXFT interrupt*/ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + husart->RxISR = USART_RxISR_16BIT; + + /* Enable the USART Data Register Not Empty interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_USART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_usart_ex.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_usart_ex.c new file mode 100644 index 00000000000..f5ab759c791 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_usart_ex.c @@ -0,0 +1,541 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_usart_ex.c + * @author MCD Application Team + * @brief Extended USART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### USART peripheral extended features ##### + ============================================================================== + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When USART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + (#) Slave mode enabling/disabling and NSS pin configuration. + + -@- When USART operates in Slave mode, Slave mode must be enabled prior + starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup USARTEx USARTEx + * @brief USART Extended HAL module driver + * @{ + */ + +#ifdef HAL_USART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/** @defgroup USARTEx_Private_Constants USARTEx Private Constants + * @{ + */ +/* USART RX FIFO depth */ +#define RX_FIFO_DEPTH 16U + +/* USART TX FIFO depth */ +#define TX_FIFO_DEPTH 16U +/** + * @} + */ + +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup USARTEx_Private_Functions USARTEx Private Functions + * @{ + */ +static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USARTEx_Exported_Functions USARTEx Exported Functions + * @{ + */ + +/** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions + * @brief Extended USART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of FIFO mode related callback functions. + + (#) TX/RX Fifos Callbacks: + (+) HAL_USARTEx_RxFifoFullCallback() + (+) HAL_USARTEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +/** + * @brief USART RX Fifo full callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief USART TX Fifo empty callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode + (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode + (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS) + (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + + +@endverbatim + * @{ + */ + +/** + * @brief Enable the SPI slave mode. + * @note When the USART operates in SPI slave mode, it handles data flow using + * the serial interface clock derived from the external SCLK signal + * provided by the external master SPI device. + * @note In SPI slave mode, the USART must be enabled before starting the master + * communications (or between frames while the clock is stable). Otherwise, + * if the USART slave is enabled while the master is in the middle of a + * frame, it will become desynchronized with the master. + * @note The data register of the slave needs to be ready before the first edge + * of the communication clock or before the end of the ongoing communication, + * otherwise the SPI slave will transmit zeros. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* In SPI slave mode mode, the following bits must be kept cleared: + - LINEN and CLKEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Enable SPI slave mode */ + SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->SlaveMode = USART_SLAVEMODE_ENABLE; + + husart->State = HAL_USART_STATE_READY; + + /* Enable USART */ + __HAL_USART_ENABLE(husart); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Disable the SPI slave mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Disable SPI slave mode */ + CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->SlaveMode = USART_SLAVEMODE_DISABLE; + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Configure the Slave Select input pin (NSS). + * @note Software NSS management: SPI slave will always be selected and NSS + * input pin will be ignored. + * @note Hardware NSS management: the SPI slave selection depends on NSS + * input pin. The slave is selected when NSS is low and deselected when + * NSS is high. + * @param husart USART handle. + * @param NSSConfig NSS configuration. + * This parameter can be one of the following values: + * @arg @ref USART_NSS_HARD + * @arg @ref USART_NSS_SOFT + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + assert_param(IS_USART_NSS(NSSConfig)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Program DIS_NSS bit in the USART_CR2 register */ + MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Enable the FIFO mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + husart->FifoMode = USART_FIFOMODE_ENABLE; + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Enable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + husart->FifoMode = USART_FIFOMODE_DISABLE; + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param husart USART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref USART_TXFIFO_THRESHOLD_1_8 + * @arg @ref USART_TXFIFO_THRESHOLD_1_4 + * @arg @ref USART_TXFIFO_THRESHOLD_1_2 + * @arg @ref USART_TXFIFO_THRESHOLD_3_4 + * @arg @ref USART_TXFIFO_THRESHOLD_7_8 + * @arg @ref USART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Update TX threshold configuration */ + MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param husart USART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref USART_RXFIFO_THRESHOLD_1_8 + * @arg @ref USART_RXFIFO_THRESHOLD_1_4 + * @arg @ref USART_RXFIFO_THRESHOLD_1_2 + * @arg @ref USART_RXFIFO_THRESHOLD_3_4 + * @arg @ref USART_RXFIFO_THRESHOLD_7_8 + * @arg @ref USART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Update RX threshold configuration */ + MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup USARTEx_Private_Functions + * @{ + */ + +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the USART configuration registers. + * @param husart USART handle. + * @retval None + */ +static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (husart->FifoMode == USART_FIFOMODE_DISABLE) + { + husart->NbTxDataToProcess = 1U; + husart->NbRxDataToProcess = 1U; + } + else + { + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, + USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU); + tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, + USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU); + husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} +/** + * @} + */ + +#endif /* HAL_USART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_wwdg.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_wwdg.c new file mode 100644 index 00000000000..b7f4de68b3b --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_wwdg.c @@ -0,0 +1,420 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_wwdg.c + * @author MCD Application Team + * @brief WWDG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Window Watchdog (WWDG) peripheral: + * + Initialization and Configuration functions + * + IO operation functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### WWDG Specific features ##### + ============================================================================== + [..] + Once enabled the WWDG generates a system reset on expiry of a programmed + time period, unless the program refreshes the counter (T[6;0] downcounter) + before reaching 0x3F value (i.e. a reset is generated when the counter + value rolls down from 0x40 to 0x3F). + + (+) An MCU reset is also generated if the counter value is refreshed + before the counter has reached the refresh window value. This + implies that the counter must be refreshed in a limited window. + (+) Once enabled the WWDG cannot be disabled except by a system reset. + (+) If required by application, an Early Wakeup Interrupt can be triggered + in order to be warned before WWDG expiration. The Early Wakeup Interrupt + (EWI) can be used if specific safety operations or data logging must + be performed before the actual reset is generated. When the downcounter + reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt + line to be enabled in NVIC. Once enabled, EWI interrupt cannot be + disabled except by a system reset. + (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG + reset occurs. + (+) The WWDG counter input clock is derived from the APB clock divided + by a programmable prescaler. + (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler) + (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz) + where T[5;0] are the lowest 6 bits of Counter. + (+) WWDG Counter refresh is allowed between the following limits : + (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock + (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock + (+) Typical values: + (++) Counter min (T[5;0] = 0x00) at 30 MHz (PCLK1) with zero prescaler: + max timeout before reset: approximately 136.53us + (++) Counter max (T[5;0] = 0x3F) at 30 MHz (PCLK1) with prescaler + dividing by 128: + max timeout before reset: approximately 69.91ms + + ##### How to use this driver ##### + ============================================================================== + + *** Common driver usage *** + =========================== + + [..] + (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). + (+) Configure the WWDG prescaler, refresh window value, counter value and early + interrupt status using HAL_WWDG_Init() function. This will automatically + enable WWDG and start its downcounter. Time reference can be taken from + function exit. Care must be taken to provide a counter value + greater than 0x40 to prevent generation of immediate reset. + (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is + generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is + triggered by the interrupt service routine, flag will be automatically + cleared and HAL_WWDG_WakeupCallback user callback will be executed. User + can add his own code by customization of callback HAL_WWDG_WakeupCallback. + (+) Then the application program must refresh the WWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + HAL_WWDG_Refresh() function. This operation must occur only when + the counter is lower than the refresh window value already programmed. + + *** Callback registration *** + ============================= + + [..] + The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows + the user to configure dynamically the driver callbacks. Use Functions + HAL_WWDG_RegisterCallback() to register a user callback. + + (+) Function HAL_WWDG_RegisterCallback() allows to register following + callbacks: + (++) EwiCallback : callback for Early WakeUp Interrupt. + (++) MspInitCallback : WWDG MspInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to + the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback() + takes as parameters the HAL peripheral handle and the Callback ID. + This function allows to reset following callbacks: + (++) EwiCallback : callback for Early WakeUp Interrupt. + (++) MspInitCallback : WWDG MspInit. + + [..] + When calling HAL_WWDG_Init function, callbacks are reset to the + corresponding legacy weak (surcharged) functions: + HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have + not been registered before. + + [..] + When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + *** WWDG HAL driver macros list *** + =================================== + [..] + Below the list of available macros in WWDG HAL driver. + (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral + (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status + (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags + (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +#ifdef HAL_WWDG_MODULE_ENABLED +/** @defgroup WWDG WWDG + * @brief WWDG HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Functions WWDG Exported Functions + * @{ + */ + +/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions. + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and start the WWDG according to the specified parameters + in the WWDG_InitTypeDef of associated handle. + (+) Initialize the WWDG MSP. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the WWDG according to the specified. + * parameters in the WWDG_InitTypeDef of associated handle. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) +{ + /* Check the WWDG handle allocation */ + if (hwwdg == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); + assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler)); + assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); + assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); + assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode)); + +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) + /* Reset Callback pointers */ + if (hwwdg->EwiCallback == NULL) + { + hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback; + } + + if (hwwdg->MspInitCallback == NULL) + { + hwwdg->MspInitCallback = HAL_WWDG_MspInit; + } + + /* Init the low level hardware */ + hwwdg->MspInitCallback(hwwdg); +#else + /* Init the low level hardware */ + HAL_WWDG_MspInit(hwwdg); +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ + + /* Set WWDG Counter */ + WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); + + /* Set WWDG Prescaler and Window */ + WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window)); + + /* Return function status */ + return HAL_OK; +} + + +/** + * @brief Initialize the WWDG MSP. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @note When rewriting this function in user file, mechanism may be added + * to avoid multiple initialize when HAL_WWDG_Init function is called + * again to change parameters. + * @retval None + */ +__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hwwdg); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_WWDG_MspInit could be implemented in the user file + */ +} + + +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User WWDG Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hwwdg WWDG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID + * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, + pWWDG_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + status = HAL_ERROR; + } + else + { + switch (CallbackID) + { + case HAL_WWDG_EWI_CB_ID: + hwwdg->EwiCallback = pCallback; + break; + + case HAL_WWDG_MSPINIT_CB_ID: + hwwdg->MspInitCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + + return status; +} + + +/** + * @brief Unregister a WWDG Callback + * WWDG Callback is redirected to the weak (surcharged) predefined callback + * @param hwwdg WWDG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID + * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_WWDG_EWI_CB_ID: + hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback; + break; + + case HAL_WWDG_MSPINIT_CB_ID: + hwwdg->MspInitCallback = HAL_WWDG_MspInit; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Refresh the WWDG. + (+) Handle WWDG interrupt request and associated function callback. + +@endverbatim + * @{ + */ + +/** + * @brief Refresh the WWDG. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg) +{ + /* Write to WWDG CR the WWDG Counter value to refresh with */ + WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter)); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handle WWDG interrupt request. + * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations + * or data logging must be performed before the actual reset is generated. + * The EWI interrupt is enabled by calling HAL_WWDG_Init function with + * EWIMode set to WWDG_EWI_ENABLE. + * When the downcounter reaches the value 0x40, and EWI interrupt is + * generated and the corresponding Interrupt Service Routine (ISR) can + * be used to trigger specific actions (such as communications or data + * logging), before resetting the device. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval None + */ +void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) +{ + /* Check if Early Wakeup Interrupt is enable */ + if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET) + { + /* Check if WWDG Early Wakeup Interrupt occurred */ + if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) + { + /* Clear the WWDG Early Wakeup flag */ + __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF); + +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) + /* Early Wakeup registered callback */ + hwwdg->EwiCallback(hwwdg); +#else + /* Early Wakeup callback */ + HAL_WWDG_EarlyWakeupCallback(hwwdg); +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ + } + } +} + + +/** + * @brief WWDG Early Wakeup callback. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval None + */ +__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hwwdg); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_WWDG_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_xspi.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_xspi.c new file mode 100644 index 00000000000..3f05f73a718 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_xspi.c @@ -0,0 +1,3424 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_xspi.c + * @author MCD Application Team + * @brief XSPI HAL module driver. + This file provides firmware functions to manage the following + functionalities of the OctoSPI/HSPI interface (XSPI). + + Initialization and de-initialization functions + + Hyperbus configuration + + Indirect functional mode management + + Memory-mapped functional mode management + + Auto-polling functional mode management + + Interrupts and flags management + + DMA channel configuration for indirect functional mode + + Errors management and abort functionality + + IO manager configuration + + HIGH-SPEED INTERFACE configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + *** Initialization *** + ====================== + [..] + As prerequisite, fill in the HAL_XSPI_MspInit() : + (+) Enable OctoSPI/HSPI clocks interface with __HAL_RCC_XSPI_CLK_ENABLE(). + (+) Reset OctoSPI/HSPI Peripheral with __HAL_RCC_XSPI_FORCE_RESET() and __HAL_RCC_XSPI_RELEASE_RESET(). + (+) Enable the clocks for the OctoSPI/HSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). + (+) Configure these OctoSPI/HSPI pins in alternate mode using HAL_GPIO_Init(). + (+) If interrupt or DMA mode is used, enable and configure OctoSPI/HSPI global + interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (+) If DMA mode is used, enable the clocks for the OctoSPI/HSPI DMA channel + with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), + link it with OctoSPI/HSPI handle using __HAL_LINKDMA(), enable and configure + DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + [..] + Configure the fifo threshold, the memory mode, the memory type, the + device size, the CS high time, the free running clock, the clock mode, + the wrap size, the clock prescaler, the sample shifting, the hold delay + and the CS boundary using the HAL_XSPI_Init() function. + [..] + When using Hyperbus, configure the RW recovery time, the access time, + the write latency and the latency mode using the HAL_XSPI_HyperbusCfg() + function. + + *** Indirect functional mode *** + ================================ + [..] + In regular mode, configure the command sequence using the HAL_XSPI_Command() + or HAL_XSPI_Command_IT() functions : + (+) Instruction phase : the mode used and if present the size, the instruction + opcode and the DTR mode. + (+) Address phase : the mode used and if present the size, the address + value and the DTR mode. + (+) Alternate-bytes phase : the mode used and if present the size, the + alternate bytes values and the DTR mode. + (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). + (+) Data phase : the mode used and if present the number of bytes and the DTR mode. + (+) Data strobe (DQS) mode : the activation (or not) of this mode + (+) IO selection : to access external memory. + (+) Operation type : always common configuration. + [..] + In Hyperbus mode, configure the command sequence using the HAL_XSPI_HyperbusCmd() + function : + (+) Address space : indicate if the access will be done in register or memory + (+) Address size + (+) Number of data + (+) Data strobe (DQS) mode : the activation (or not) of this mode + [..] + If no data is required for the command (only for regular mode, not for + Hyperbus mode), it is sent directly to the memory : + (+) In polling mode, the output of the function is done when the transfer is complete. + (+) In interrupt mode, HAL_XSPI_CmdCpltCallback() will be called when the transfer is complete. + [..] + For the indirect write mode, use HAL_XSPI_Transmit(), HAL_XSPI_Transmit_DMA() or + HAL_XSPI_Transmit_IT() after the command configuration : + (+) In polling mode, the output of the function is done when the transfer is complete. + (+) In interrupt mode, HAL_XSPI_FifoThresholdCallback() will be called when the fifo threshold + is reached and HAL_XSPI_TxCpltCallback() will be called when the transfer is complete. + (+) In DMA mode, HAL_XSPI_TxHalfCpltCallback() will be called at the half transfer and + HAL_XSPI_TxCpltCallback() will be called when the transfer is complete. + [..] + For the indirect read mode, use HAL_XSPI_Receive(), HAL_XSPI_Receive_DMA() or + HAL_XSPI_Receive_IT() after the command configuration : + (+) In polling mode, the output of the function is done when the transfer is complete. + (+) In interrupt mode, HAL_XSPI_FifoThresholdCallback() will be called when the fifo threshold + is reached and HAL_XSPI_RxCpltCallback() will be called when the transfer is complete. + (+) In DMA mode, HAL_XSPI_RxHalfCpltCallback() will be called at the half transfer and + HAL_XSPI_RxCpltCallback() will be called when the transfer is complete. + + *** Auto-polling functional mode *** + ==================================== + [..] + Configure the command sequence by the same way than the indirect mode + [..] + Configure the auto-polling functional mode using the HAL_XSPI_AutoPolling() + or HAL_XSPI_AutoPolling_IT() functions : + (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND), + the polling interval and the automatic stop activation. + [..] + After the configuration : + (+) In polling mode, the output of the function is done when the status match is reached. The + automatic stop is activated to avoid an infinite loop. + (+) In interrupt mode, HAL_XSPI_StatusMatchCallback() will be called each time the status match is reached. + + *** Memory-mapped functional mode *** + ===================================== + [..] + Configure the command sequence by the same way than the indirect mode except + for the operation type in regular mode : + (+) Operation type equals to read configuration : the command configuration + applies to read access in memory-mapped mode + (+) Operation type equals to write configuration : the command configuration + applies to write access in memory-mapped mode + (+) Both read and write configuration should be performed before activating + memory-mapped mode + [..] + Configure the memory-mapped functional mode using the HAL_XSPI_MemoryMapped() + functions : + (+) The timeout activation and the timeout period. + [..] + After the configuration, the OctoSPI/HSPI will be used as soon as an access on the AHB is done on + the address range. HAL_XSPI_TimeOutCallback() will be called when the timeout expires. + + *** Errors management and abort functionality *** + ================================================= + [..] + HAL_XSPI_GetError() function gives the error raised during the last operation. + [..] + HAL_XSPI_Abort() and HAL_XSPI_AbortIT() functions aborts any on-going operation and + flushes the fifo : + (+) In polling mode, the output of the function is done when the transfer + complete bit is set and the busy bit cleared. + (+) In interrupt mode, HAL_XSPI_AbortCpltCallback() will be called when + the transfer complete bit is set. + + *** Control functions *** + ========================= + [..] + HAL_XSPI_GetState() function gives the current state of the HAL XSPI driver. + [..] + HAL_XSPI_SetTimeout() function configures the timeout value used in the driver. + [..] + HAL_XSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OctoSPI/HSPI Peripheral. + [..] + HAL_XSPI_SetMemoryType() function configures the type of the external memory. + [..] + HAL_XSPI_SetDeviceSize() function configures the size of the external memory. + [..] + HAL_XSPI_SetClockPrescaler() function configures the clock prescaler of the OctoSPI/HSPI Peripheral. + [..] + HAL_XSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + + *** IO manager configuration functions *** + ========================================== + [..] + HAL_XSPIM_Config() function configures the IO manager for the XSPI instance. + + *** High-speed interface and calibration functions *** + ========================================== + [..] + The purpose of High-speed interface is primary to shift data or data strobe by one quarter of octal + bus clock period, with a correct timing accuracy. DLL must be calibrated versus this clock period. + The calibration process is automatically enabled when one of the three conditions below is met: + (+) The XSPI exits Reset state. + (+) The Prescaler is set. + (+) The configuration of communication is set. + [..] + HAL_XSPI_GetDelayValue() function Get the delay values of the high-speed interface DLLs.. + [..] + HAL_XSPI_SetDelayValue() function Set the delay values of the high-speed interface DLLs.. + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_XSPI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use function HAL_XSPI_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : XSPI MspInit. + (+) MspDeInitCallback : XSPI MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_XSPI_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. It allows to reset following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : XSPI MspInit. + (+) MspDeInitCallback : XSPI MspDeInit. + [..] + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + [..] + By default, after the HAL_XSPI_Init() and if the state is HAL_XSPI_STATE_RESET + all callbacks are reset to the corresponding legacy weak (overridden) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (overridden) functions in the HAL_XSPI_Init() + and HAL_XSPI_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_XSPI_Init() and HAL_XSPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + [..] + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_XSPI_RegisterCallback() before calling HAL_XSPI_DeInit() + or HAL_XSPI_Init() function. + + [..] + When The compilation define USE_HAL_XSPI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (overridden) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +#if defined(XSPI) || defined(XSPI1) || defined(XSPI2) + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup XSPI XSPI + * @brief XSPI HAL module driver + * @{ + */ + +#ifdef HAL_XSPI_MODULE_ENABLED + +/** + @cond 0 + */ +/* Private typedef -----------------------------------------------------------*/ + +/* Private define ------------------------------------------------------------*/ +#define XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!< Indirect write mode */ +#define XSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)XSPI_CR_FMODE_0) /*!< Indirect read mode */ +#define XSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)XSPI_CR_FMODE_1) /*!< Automatic polling mode */ +#define XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)XSPI_CR_FMODE) /*!< Memory-mapped mode */ + +#define XSPI_CFG_STATE_MASK 0x00000004U +#define XSPI_BUSY_STATE_MASK 0x00000008U + +#define XSPI_NB_INSTANCE 2U +#define XSPI_IOM_NB_PORTS 2U +#define XSPI_IOM_PORT_MASK 0x1U + +/* Private macro -------------------------------------------------------------*/ +#define IS_XSPI_FUNCTIONAL_MODE(MODE) (((MODE) == XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \ + ((MODE) == XSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \ + ((MODE) == XSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \ + ((MODE) == XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)) + +/* Private variables ---------------------------------------------------------*/ + +/* Private function prototypes -----------------------------------------------*/ +static void XSPI_DMACplt(DMA_HandleTypeDef *hdma); +static void XSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma); +static void XSPI_DMAError(DMA_HandleTypeDef *hdma); +static void XSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, FlagStatus State, + uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd); +static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *const pCfg); +/** + @endcond + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup XSPI_Exported_Functions XSPI Exported Functions + * @{ + */ + +/** @defgroup XSPI_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Initialize the XSPI. + (+) De-initialize the XSPI. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the XSPI mode according to the specified parameters + * in the XSPI_InitTypeDef and initialize the associated handle. + * @param hxspi : XSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check the XSPI handle allocation */ + if (hxspi == NULL) + { + status = HAL_ERROR; + /* No error code can be set set as the handler is null */ + } + else + { + /* Check the parameters of the initialization structure */ + assert_param(IS_XSPI_MEMORY_MODE(hxspi->Init.MemoryMode)); + assert_param(IS_XSPI_MEMORY_TYPE(hxspi->Init.MemoryType)); + assert_param(IS_XSPI_MEMORY_SIZE(hxspi->Init.MemorySize)); + assert_param(IS_XSPI_CS_HIGH_TIME_CYCLE(hxspi->Init.ChipSelectHighTimeCycle)); + assert_param(IS_XSPI_FREE_RUN_CLK(hxspi->Init.FreeRunningClock)); + assert_param(IS_XSPI_CLOCK_MODE(hxspi->Init.ClockMode)); + assert_param(IS_XSPI_WRAP_SIZE(hxspi->Init.WrapSize)); + assert_param(IS_XSPI_CLK_PRESCALER(hxspi->Init.ClockPrescaler)); + assert_param(IS_XSPI_SAMPLE_SHIFTING(hxspi->Init.SampleShifting)); + assert_param(IS_XSPI_DHQC(hxspi->Init.DelayHoldQuarterCycle)); + assert_param(IS_XSPI_CS_BOUND(hxspi->Init.ChipSelectBoundary)); + assert_param(IS_XSPI_FIFO_THRESHOLD_BYTE(hxspi->Init.FifoThresholdByte)); + assert_param(IS_XSPI_MAXTRAN(hxspi->Init.MaxTran)); + assert_param(IS_XSPI_CSSEL(hxspi->Init.MemorySelect)); + /* Initialize error code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; + + /* Check if the state is the reset state */ + if (hxspi->State == HAL_XSPI_STATE_RESET) + { +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + /* Reset Callback pointers in HAL_XSPI_STATE_RESET only */ + hxspi->ErrorCallback = HAL_XSPI_ErrorCallback; + hxspi->AbortCpltCallback = HAL_XSPI_AbortCpltCallback; + hxspi->FifoThresholdCallback = HAL_XSPI_FifoThresholdCallback; + hxspi->CmdCpltCallback = HAL_XSPI_CmdCpltCallback; + hxspi->RxCpltCallback = HAL_XSPI_RxCpltCallback; + hxspi->TxCpltCallback = HAL_XSPI_TxCpltCallback; + hxspi->RxHalfCpltCallback = HAL_XSPI_RxHalfCpltCallback; + hxspi->TxHalfCpltCallback = HAL_XSPI_TxHalfCpltCallback; + hxspi->StatusMatchCallback = HAL_XSPI_StatusMatchCallback; + hxspi->TimeOutCallback = HAL_XSPI_TimeOutCallback; + + if (hxspi->MspInitCallback == NULL) + { + hxspi->MspInitCallback = HAL_XSPI_MspInit; + } + + /* Init the low level hardware */ + hxspi->MspInitCallback(hxspi); +#else + /* Initialization of the low level hardware */ + HAL_XSPI_MspInit(hxspi); +#endif /* defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + + /* Configure the default timeout for the XSPI memory access */ + (void)HAL_XSPI_SetTimeout(hxspi, HAL_XSPI_TIMEOUT_DEFAULT_VALUE); + + /* Configure memory type, device size, chip select high time, free running clock, clock mode */ + MODIFY_REG(hxspi->Instance->DCR1, + (XSPI_DCR1_MTYP | XSPI_DCR1_DEVSIZE | XSPI_DCR1_CSHT | XSPI_DCR1_FRCK | XSPI_DCR1_CKMODE), + (hxspi->Init.MemoryType | ((hxspi->Init.MemorySize) << XSPI_DCR1_DEVSIZE_Pos) | + ((hxspi->Init.ChipSelectHighTimeCycle - 1U) << XSPI_DCR1_CSHT_Pos) | hxspi->Init.ClockMode)); + + /* Configure wrap size */ + MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_WRAPSIZE, hxspi->Init.WrapSize); + + /* Configure chip select boundary */ + MODIFY_REG(hxspi->Instance->DCR3, XSPI_DCR3_CSBOUND, (hxspi->Init.ChipSelectBoundary << XSPI_DCR3_CSBOUND_Pos)); + + /* Configure maximum transfer */ + MODIFY_REG(hxspi->Instance->DCR3, XSPI_DCR3_MAXTRAN, \ + (hxspi->Init.MaxTran << XSPI_DCR3_MAXTRAN_Pos)); + + /* Configure refresh */ + hxspi->Instance->DCR4 = hxspi->Init.Refresh; + + /* Configure FIFO threshold */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FTHRES, ((hxspi->Init.FifoThresholdByte - 1U) << XSPI_CR_FTHRES_Pos)); + + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + /* Configure clock prescaler */ + MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER, + ((hxspi->Init.ClockPrescaler) << XSPI_DCR2_PRESCALER_Pos)); + + if (IS_XSPI_ALL_INSTANCE(hxspi->Instance)) + { + /* The configuration of clock prescaler trigger automatically a calibration process. + So it is necessary to wait the calibration is complete */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + if (status != HAL_OK) + { + return status; + } + } + /* Configure Dual Memory mode and CS Selection */ + MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_DMM | XSPI_CR_CSSEL), + (hxspi->Init.MemoryMode | hxspi->Init.MemorySelect)); + + /* Configure sample shifting and delay hold quarter cycle */ + MODIFY_REG(hxspi->Instance->TCR, (XSPI_TCR_SSHIFT | XSPI_TCR_DHQC), + (hxspi->Init.SampleShifting | hxspi->Init.DelayHoldQuarterCycle)); + + /* Enable XSPI */ + HAL_XSPI_ENABLE(hxspi); + + /* Enable free running clock if needed : must be done after XSPI enable */ + if (hxspi->Init.FreeRunningClock == HAL_XSPI_FREERUNCLK_ENABLE) + { + SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); + } + + /* Initialize the XSPI state */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + hxspi->State = HAL_XSPI_STATE_HYPERBUS_INIT; + } + else + { + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + } + return status; +} + +/** + * @brief Initialize the XSPI MSP. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_MspInit can be implemented in the user file + */ +} + +/** + * @brief De-Initialize the XSPI peripheral. + * @param hxspi : XSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the XSPI handle allocation */ + if (hxspi == NULL) + { + status = HAL_ERROR; + /* No error code can be set as the handler is null */ + } + else + { + /* Disable XSPI */ + HAL_XSPI_DISABLE(hxspi); + + /* Disable free running clock if needed : must be done after XSPI disable */ + CLEAR_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + if (hxspi->MspDeInitCallback == NULL) + { + hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; + } + + /* De-initialize the low level hardware */ + hxspi->MspDeInitCallback(hxspi); +#else + /* De-initialize the low-level hardware */ + HAL_XSPI_MspDeInit(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + + /* Reset the driver state */ + hxspi->State = HAL_XSPI_STATE_RESET; + } + + return status; +} + +/** + * @brief DeInitialize the XSPI MSP. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group2 Input and Output operation functions + * @brief XSPI Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Handle the interrupts. + (+) Handle the command sequence (regular and Hyperbus). + (+) Handle the Hyperbus configuration. + (+) Transmit data in blocking, interrupt or DMA mode. + (+) Receive data in blocking, interrupt or DMA mode. + (+) Manage the auto-polling functional mode. + (+) Manage the memory-mapped functional mode. + +@endverbatim + * @{ + */ + +/** + * @brief Handle XSPI interrupt request. + * @param hxspi : XSPI handle + * @retval None + */ +void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi) +{ + __IO uint32_t *data_reg = &hxspi->Instance->DR; + uint32_t flag = hxspi->Instance->SR; + uint32_t itsource = hxspi->Instance->CR; + uint32_t currentstate = hxspi->State; + + /* XSPI fifo threshold interrupt occurred -------------------------------*/ + if (((flag & HAL_XSPI_FLAG_FT) != 0U) && ((itsource & HAL_XSPI_IT_FT) != 0U)) + { + if (currentstate == HAL_XSPI_STATE_BUSY_TX) + { + /* Write a data in the fifo */ + *((__IO uint8_t *)data_reg) = *hxspi->pBuffPtr; + hxspi->pBuffPtr++; + hxspi->XferCount--; + } + else if (currentstate == HAL_XSPI_STATE_BUSY_RX) + { + /* Read a data from the fifo */ + *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); + hxspi->pBuffPtr++; + hxspi->XferCount--; + } + else + { + /* Nothing to do */ + } + + if (hxspi->XferCount == 0U) + { + /* All data have been received or transmitted for the transfer */ + /* Disable fifo threshold interrupt */ + HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_FT); + } + + /* Fifo threshold callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->FifoThresholdCallback(hxspi); +#else + HAL_XSPI_FifoThresholdCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + /* XSPI transfer complete interrupt occurred ----------------------------*/ + else if (((flag & HAL_XSPI_FLAG_TC) != 0U) && ((itsource & HAL_XSPI_IT_TC) != 0U)) + { + if (currentstate == HAL_XSPI_STATE_BUSY_RX) + { + if ((hxspi->XferCount > 0U) && ((flag & XSPI_SR_FLEVEL) != 0U)) + { + /* Read the last data received in the fifo */ + *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); + hxspi->pBuffPtr++; + hxspi->XferCount--; + } + else if (hxspi->XferCount == 0U) + { + /* Clear flag */ + hxspi->Instance->FCR = HAL_XSPI_FLAG_TC; + + /* Disable the interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); + + hxspi->State = HAL_XSPI_STATE_READY; + + /* RX complete callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->RxCpltCallback(hxspi); +#else + HAL_XSPI_RxCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else + { + /* Nothing to do */ + } + } + else + { + /* Clear flag */ + hxspi->Instance->FCR = HAL_XSPI_FLAG_TC; + + /* Disable the interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); + + hxspi->State = HAL_XSPI_STATE_READY; + + if (currentstate == HAL_XSPI_STATE_BUSY_TX) + { + /* TX complete callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->TxCpltCallback(hxspi); +#else + HAL_XSPI_TxCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else if (currentstate == HAL_XSPI_STATE_BUSY_CMD) + { + /* Command complete callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->CmdCpltCallback(hxspi); +#else + HAL_XSPI_CmdCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else if (currentstate == HAL_XSPI_STATE_ABORT) + { + if (hxspi->ErrorCode == HAL_XSPI_ERROR_NONE) + { + /* Abort called by the user */ + /* Abort complete callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->AbortCpltCallback(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else + { + /* Abort due to an error (eg : DMA error) */ + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + else + { + /* Nothing to do */ + } + } + } + /* XSPI status match interrupt occurred ---------------------------------*/ + else if (((flag & HAL_XSPI_FLAG_SM) != 0U) && ((itsource & HAL_XSPI_IT_SM) != 0U)) + { + /* Clear flag */ + hxspi->Instance->FCR = HAL_XSPI_FLAG_SM; + + /* Check if automatic poll mode stop is activated */ + if ((hxspi->Instance->CR & XSPI_CR_APMS) != 0U) + { + /* Disable the interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_SM | HAL_XSPI_IT_TE); + + hxspi->State = HAL_XSPI_STATE_READY; + } + + /* Status match callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->StatusMatchCallback(hxspi); +#else + HAL_XSPI_StatusMatchCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + /* XSPI transfer error interrupt occurred -------------------------------*/ + else if (((flag & HAL_XSPI_FLAG_TE) != 0U) && ((itsource & HAL_XSPI_IT_TE) != 0U)) + { + /* Clear flag */ + hxspi->Instance->FCR = HAL_XSPI_FLAG_TE; + + /* Disable all interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HAL_XSPI_IT_TE)); + + /* Set error code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_TRANSFER; + + /* Check if the DMA is enabled */ + if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) + { + /* Disable the DMA transfer on the XSPI side */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + + /* Disable the DMA transmit on the DMA side */ + hxspi->hdmatx->XferAbortCallback = XSPI_DMAAbortCplt; + if (HAL_DMA_Abort_IT(hxspi->hdmatx) != HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + + /* Disable the DMA receive on the DMA side */ + hxspi->hdmarx->XferAbortCallback = XSPI_DMAAbortCplt; + if (HAL_DMA_Abort_IT(hxspi->hdmarx) != HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + else + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + /* XSPI timeout interrupt occurred --------------------------------------*/ + else if (((flag & HAL_XSPI_FLAG_TO) != 0U) && ((itsource & HAL_XSPI_IT_TO) != 0U)) + { + /* Clear flag */ + hxspi->Instance->FCR = HAL_XSPI_FLAG_TO; + + /* Timeout callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->TimeOutCallback(hxspi); +#else + HAL_XSPI_TimeOutCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief Set the command configuration. + * @param hxspi : XSPI handle + * @param pCmd : structure that contains the command configuration information + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t state; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the command structure */ + assert_param(IS_XSPI_OPERATION_TYPE(pCmd->OperationType)); + if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) + { + assert_param(IS_XSPI_IO_SELECT(pCmd->IOSelect)); + } + + assert_param(IS_XSPI_INSTRUCTION_MODE(pCmd->InstructionMode)); + if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE) + { + assert_param(IS_XSPI_INSTRUCTION_WIDTH(pCmd->InstructionWidth)); + assert_param(IS_XSPI_INSTRUCTION_DTR_MODE(pCmd->InstructionDTRMode)); + } + + assert_param(IS_XSPI_ADDRESS_MODE(pCmd->AddressMode)); + if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) + { + assert_param(IS_XSPI_ADDRESS_WIDTH(pCmd->AddressWidth)); + assert_param(IS_XSPI_ADDRESS_DTR_MODE(pCmd->AddressDTRMode)); + } + + assert_param(IS_XSPI_ALT_BYTES_MODE(pCmd->AlternateBytesMode)); + if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE) + { + assert_param(IS_XSPI_ALT_BYTES_WIDTH(pCmd->AlternateBytesWidth)); + assert_param(IS_XSPI_ALT_BYTES_DTR_MODE(pCmd->AlternateBytesDTRMode)); + } + + assert_param(IS_XSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); + + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + assert_param(IS_XSPI_DATA_LENGTH(pCmd->DataLength)); + } + assert_param(IS_XSPI_DATA_DTR_MODE(pCmd->DataDTRMode)); + assert_param(IS_XSPI_DUMMY_CYCLES(pCmd->DummyCycles)); + } + + assert_param(IS_XSPI_DQS_MODE(pCmd->DQSMode)); + + /* Check the state of the driver */ + state = hxspi->State; + if (((state == HAL_XSPI_STATE_READY) && (hxspi->Init.MemoryType != HAL_XSPI_MEMTYPE_HYPERBUS)) || + ((state == HAL_XSPI_STATE_READ_CMD_CFG) && ((pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) || + (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG))) || + ((state == HAL_XSPI_STATE_WRITE_CMD_CFG) && + ((pCmd->OperationType == HAL_XSPI_OPTYPE_READ_CFG) || + (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG)))) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Initialize error code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; + + /* Configure the registers */ + status = XSPI_ConfigCmd(hxspi, pCmd); + + if (status == HAL_OK) + { + if (pCmd->DataMode == HAL_XSPI_DATA_NONE) + { + /* When there is no data phase, the transfer start as soon as the configuration is done + so wait until TC flag is set to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); + + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + } + else + { + /* Update the state */ + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + hxspi->State = HAL_XSPI_STATE_CMD_CFG; + } + else if (pCmd->OperationType == HAL_XSPI_OPTYPE_READ_CFG) + { + if (hxspi->State == HAL_XSPI_STATE_WRITE_CMD_CFG) + { + hxspi->State = HAL_XSPI_STATE_CMD_CFG; + } + else + { + hxspi->State = HAL_XSPI_STATE_READ_CMD_CFG; + } + } + else if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) + { + if (hxspi->State == HAL_XSPI_STATE_READ_CMD_CFG) + { + hxspi->State = HAL_XSPI_STATE_CMD_CFG; + } + else + { + hxspi->State = HAL_XSPI_STATE_WRITE_CMD_CFG; + } + } + else + { + /* Wrap configuration, no state change */ + } + } + } + } + else + { + status = HAL_BUSY; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Set the command configuration in interrupt mode. + * @param hxspi : XSPI handle + * @param pCmd : structure that contains the command configuration information + * @note This function is used only in Indirect Read or Write Modes + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the command structure */ + assert_param(IS_XSPI_OPERATION_TYPE(pCmd->OperationType)); + + if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) + { + assert_param(IS_XSPI_IO_SELECT(pCmd->IOSelect)); + } + + assert_param(IS_XSPI_INSTRUCTION_MODE(pCmd->InstructionMode)); + if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE) + { + assert_param(IS_XSPI_INSTRUCTION_WIDTH(pCmd->InstructionWidth)); + assert_param(IS_XSPI_INSTRUCTION_DTR_MODE(pCmd->InstructionDTRMode)); + } + + assert_param(IS_XSPI_ADDRESS_MODE(pCmd->AddressMode)); + if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) + { + assert_param(IS_XSPI_ADDRESS_WIDTH(pCmd->AddressWidth)); + assert_param(IS_XSPI_ADDRESS_DTR_MODE(pCmd->AddressDTRMode)); + } + + assert_param(IS_XSPI_ALT_BYTES_MODE(pCmd->AlternateBytesMode)); + if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE) + { + assert_param(IS_XSPI_ALT_BYTES_WIDTH(pCmd->AlternateBytesWidth)); + assert_param(IS_XSPI_ALT_BYTES_DTR_MODE(pCmd->AlternateBytesDTRMode)); + } + + assert_param(IS_XSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); + + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + assert_param(IS_XSPI_DATA_LENGTH(pCmd->DataLength)); + assert_param(IS_XSPI_DATA_DTR_MODE(pCmd->DataDTRMode)); + assert_param(IS_XSPI_DUMMY_CYCLES(pCmd->DummyCycles)); + } + + assert_param(IS_XSPI_DQS_MODE(pCmd->DQSMode)); + + /* Check the state of the driver */ + if ((hxspi->State == HAL_XSPI_STATE_READY) && (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) && + (pCmd->DataMode == HAL_XSPI_DATA_NONE) && (hxspi->Init.MemoryType != HAL_XSPI_MEMTYPE_HYPERBUS)) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + /* Initialize error code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); + + /* Configure the registers */ + status = XSPI_ConfigCmd(hxspi, pCmd); + + if (status == HAL_OK) + { + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_BUSY_CMD; + + /* Enable the transfer complete and transfer error interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_TE); + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Configure the Hyperbus parameters. + * @param hxspi : XSPI handle + * @param pCfg : Pointer to Structure containing the Hyperbus configuration + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pCfg, + uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t state; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the hyperbus configuration structure */ + assert_param(IS_XSPI_RW_RECOVERY_TIME_CYCLE(pCfg->RWRecoveryTimeCycle)); + assert_param(IS_XSPI_ACCESS_TIME_CYCLE(pCfg->AccessTimeCycle)); + assert_param(IS_XSPI_WRITE_ZERO_LATENCY(pCfg->WriteZeroLatency)); + assert_param(IS_XSPI_LATENCY_MODE(pCfg->LatencyMode)); + + /* Check the state of the driver */ + state = hxspi->State; + if ((state == HAL_XSPI_STATE_HYPERBUS_INIT) || (state == HAL_XSPI_STATE_READY)) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Configure Hyperbus configuration Latency register */ + WRITE_REG(hxspi->Instance->HLCR, ((pCfg->RWRecoveryTimeCycle << XSPI_HLCR_TRWR_Pos) | + (pCfg->AccessTimeCycle << XSPI_HLCR_TACC_Pos) | + pCfg->WriteZeroLatency | pCfg->LatencyMode)); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_READY; + } + else + { + status = HAL_BUSY; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Set the Hyperbus command configuration. + * @param hxspi : XSPI handle + * @param pCmd : Structure containing the Hyperbus command + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pCmd, + uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the hyperbus command structure */ + assert_param(IS_XSPI_ADDRESS_SPACE(pCmd->AddressSpace)); + assert_param(IS_XSPI_ADDRESS_WIDTH(pCmd->AddressWidth)); + assert_param(IS_XSPI_DATA_LENGTH(pCmd->DataLength)); + assert_param(IS_XSPI_DQS_MODE(pCmd->DQSMode)); + assert_param(IS_XSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); + + /* Check the state of the driver */ + if ((hxspi->State == HAL_XSPI_STATE_READY) && (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS)) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Re-initialize the value of the functional mode */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, 0U); + + /* Configure the address space in the DCR1 register */ + MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_MTYP_0, pCmd->AddressSpace); + + /* Configure the CCR and WCCR registers with the address size and the following configuration : + - DQS signal enabled (used as RWDS) + - DTR mode enabled on address and data */ + /* - address and data on 8 or 16 lines */ + WRITE_REG(hxspi->Instance->CCR, (pCmd->DQSMode | XSPI_CCR_DDTR | pCmd->DataMode | + pCmd->AddressWidth | XSPI_CCR_ADDTR | XSPI_CCR_ADMODE_2)); + WRITE_REG(hxspi->Instance->WCCR, (pCmd->DQSMode | XSPI_WCCR_DDTR | pCmd->DataMode | + pCmd->AddressWidth | XSPI_WCCR_ADDTR | XSPI_WCCR_ADMODE_2)); + + /* Configure the DLR register with the number of data */ + WRITE_REG(hxspi->Instance->DLR, (pCmd->DataLength - 1U)); + + /* Configure the AR register with the address value */ + WRITE_REG(hxspi->Instance->AR, pCmd->Address); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_CMD_CFG; + } + else + { + status = HAL_BUSY; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer + * @param Timeout : Timeout duration + * @note This function is used only in Indirect Write Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + __IO uint32_t *data_reg = &hxspi->Instance->DR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = (uint8_t *)pData; + + /* Configure CR register with functional mode as indirect write */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + do + { + /* Wait till fifo threshold flag is set to send data */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_FT, SET, tickstart, Timeout); + + if (status != HAL_OK) + { + break; + } + + *((__IO uint8_t *)data_reg) = *hxspi->pBuffPtr; + hxspi->pBuffPtr++; + hxspi->XferCount--; + } while (hxspi->XferCount > 0U); + + if (status == HAL_OK) + { + /* Wait till transfer complete flag is set to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear transfer complete flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer + * @param Timeout : Timeout duration + * @note This function is used only in Indirect Read Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + __IO uint32_t *data_reg = &hxspi->Instance->DR; + uint32_t addr_reg = hxspi->Instance->AR; + uint32_t ir_reg = hxspi->Instance->IR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect read */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hxspi->Instance->IR, ir_reg); + } + } + + do + { + /* Wait till fifo threshold or transfer complete flags are set to read received data */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, (HAL_XSPI_FLAG_FT | HAL_XSPI_FLAG_TC), SET, tickstart, Timeout); + + if (status != HAL_OK) + { + break; + } + + *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); + hxspi->pBuffPtr++; + hxspi->XferCount--; + } while (hxspi->XferCount > 0U); + + if (status == HAL_OK) + { + /* Wait till transfer complete flag is set to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear transfer complete flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Send an amount of data in non-blocking mode with interrupt. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer + * @note This function is used only in Indirect Write Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = (uint8_t *)pData; + + /* Configure CR register with functional mode as indirect write */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_BUSY_TX; + + /* Enable the transfer complete, fifo threshold and transfer error interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Receive an amount of data in non-blocking mode with interrupt. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer + * @note This function is used only in Indirect Read Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t addr_reg = hxspi->Instance->AR; + uint32_t ir_reg = hxspi->Instance->IR; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Configure counters and size */ + hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect read */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_BUSY_RX; + + /* Enable the transfer complete, fifo threshold and transfer error interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hxspi->Instance->IR, ir_reg); + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Send an amount of data in non-blocking mode with DMA. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer + * @note This function is used only in Indirect Write Mode + * @note If DMA peripheral access is configured as halfword, the number + * of data and the fifo threshold should be aligned on halfword + * @note If DMA peripheral access is configured as word, the number + * of data and the fifo threshold should be aligned on word + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t data_size = hxspi->Instance->DLR + 1U; + DMA_QListTypeDef *p_queue = {NULL}; + uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + p_queue = hxspi->hdmatx->LinkedListQueue; + if ((p_queue != NULL) && (p_queue->Head != NULL)) + { + data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; + } + else + { + /* Set Error Code function status */ + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + + /* Return function status */ + status = HAL_ERROR; + } + } + else + { + data_width = hxspi->hdmatx->Init.DestDataWidth; + } + /* Configure counters and size */ + if (data_width == DMA_DEST_DATAWIDTH_BYTE) + { + hxspi->XferCount = data_size; + } + else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) + { + if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U)) + { + /* The number of data or the fifo threshold is not aligned on halfword + => no transfer possible with DMA peripheral access configured as halfword */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hxspi->XferCount = data_size; + } + } + else if (data_width == DMA_DEST_DATAWIDTH_WORD) + { + if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U)) + { + /* The number of data or the fifo threshold is not aligned on word + => no transfer possible with DMA peripheral access configured as word */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hxspi->XferCount = data_size; + } + } + else + { + /* Nothing to do */ + } + + if (status == HAL_OK) + { + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = (uint8_t *)pData; + + /* Configure CR register with functional mode as indirect write */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_BUSY_TX; + + /* Set the DMA transfer complete callback */ + hxspi->hdmatx->XferCpltCallback = XSPI_DMACplt; + + /* Set the DMA Half transfer complete callback */ + hxspi->hdmatx->XferHalfCpltCallback = XSPI_DMAHalfCplt; + + /* Set the DMA error callback */ + hxspi->hdmatx->XferErrorCallback = XSPI_DMAError; + + /* Clear the DMA abort callback */ + hxspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the transmit DMA Channel */ + if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hxspi->hdmatx->LinkedListQueue != NULL) + { + /* Enable the DMA channel */ + MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ + (DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_INCREMENTED | DMA_DINC_FIXED)); + MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \ + DMA_CTR2_DREQ, DMA_MEMORY_TO_PERIPH); + /* Set DMA data size*/ + p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize; + /* Set DMA source address */ + p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + /* Set DMA destination address */ + p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR; + + status = HAL_DMAEx_List_Start_IT(hxspi->hdmatx); + } + else + { + /* Set Error Code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + + hxspi->State = HAL_XSPI_STATE_READY; + + /* Return function status */ + status = HAL_ERROR; + } + } + else + { + if ((hxspi->hdmatx->Init.Direction == DMA_MEMORY_TO_PERIPH) && + (hxspi->hdmatx->Init.SrcInc == DMA_SINC_INCREMENTED) && (hxspi->hdmatx->Init.DestInc == DMA_DINC_FIXED)) + { + status = HAL_DMA_Start_IT(hxspi->hdmatx, (uint32_t)pData, (uint32_t)&hxspi->Instance->DR, hxspi->XferSize); + } + else + { + /* no transmit possible with DMA peripheral, invalid configuration */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + } + if (status == HAL_OK) + { + /* Enable the transfer error interrupt */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE); + + /* Enable the DMA transfer by setting the DMAEN bit */ + SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hxspi : XSPI handle + * @param pData : pointer to data buffer. + * @note This function is used only in Indirect Read Mode + * @note If DMA peripheral access is configured as halfword, the number + * of data and the fifo threshold should be aligned on halfword + * @note If DMA peripheral access is configured as word, the number + * of data and the fifo threshold should be aligned on word + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t data_size = hxspi->Instance->DLR + 1U; + uint32_t addr_reg = hxspi->Instance->AR; + uint32_t ir_reg = hxspi->Instance->IR; + DMA_QListTypeDef *p_queue = {NULL}; + uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE; + + /* Check the data pointer allocation */ + if (pData == NULL) + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + else + { + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + p_queue = hxspi->hdmarx->LinkedListQueue; + if ((p_queue != NULL) && (p_queue->Head != NULL)) + { + data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; + } + else + { + /* Set Error Code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + + /* Return function status */ + status = HAL_ERROR; + } + } + else + { + data_width = hxspi->hdmarx->Init.DestDataWidth; + } + + /* Configure counters and size */ + if (data_width == DMA_DEST_DATAWIDTH_BYTE) + { + hxspi->XferCount = data_size; + } + else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) + { + if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U)) + { + /* The number of data or the fifo threshold is not aligned on halfword + => no transfer possible with DMA peripheral access configured as halfword */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hxspi->XferCount = data_size; + } + } + else if (data_width == DMA_DEST_DATAWIDTH_WORD) + { + if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U)) + { + /* The number of data or the fifo threshold is not aligned on word + => no transfer possible with DMA peripheral access configured as word */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + else + { + hxspi->XferCount = data_size; + } + } + else + { + /* Nothing to do */ + } + + if (status == HAL_OK) + { + hxspi->XferSize = hxspi->XferCount; + hxspi->pBuffPtr = pData; + + /* Configure CR register with functional mode as indirect read */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); + + /* Update the state */ + hxspi->State = HAL_XSPI_STATE_BUSY_RX; + + /* Set the DMA transfer complete callback */ + hxspi->hdmarx->XferCpltCallback = XSPI_DMACplt; + + /* Set the DMA Half transfer complete callback */ + hxspi->hdmarx->XferHalfCpltCallback = XSPI_DMAHalfCplt; + + /* Set the DMA error callback */ + hxspi->hdmarx->XferErrorCallback = XSPI_DMAError; + + /* Clear the DMA abort callback */ + hxspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the receive DMA Channel */ + if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hxspi->hdmarx->LinkedListQueue != NULL) + { + /* Enable the DMA channel */ + MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ + (DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_FIXED | DMA_DINC_INCREMENTED)); + MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \ + DMA_CTR2_DREQ, DMA_PERIPH_TO_MEMORY); + /* Set DMA data size */ + p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize; + /* Set DMA source address */ + p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR; + /* Set DMA destination address */ + p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + status = HAL_DMAEx_List_Start_IT(hxspi->hdmarx); + } + else + { + /* Set Error Code */ + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + + hxspi->State = HAL_XSPI_STATE_READY; + + /* Return function status */ + status = HAL_ERROR; + } + } + else + { + if ((hxspi->hdmarx->Init.Direction == DMA_PERIPH_TO_MEMORY) && (hxspi->hdmarx->Init.SrcInc == DMA_SINC_FIXED) + && (hxspi->hdmarx->Init.DestInc == DMA_DINC_INCREMENTED)) + { + status = HAL_DMA_Start_IT(hxspi->hdmarx, (uint32_t)&hxspi->Instance->DR, (uint32_t)pData, hxspi->XferSize); + } + else + { + /* no receive possible with DMA peripheral, invalid configuration */ + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + } + if (status == HAL_OK) + { + /* Enable the transfer error interrupt */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hxspi->Instance->IR, ir_reg); + } + } + + /* Enable the DMA transfer by setting the DMAEN bit */ + SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + + return status; +} + +/** + * @brief Configure the XSPI Automatic Polling Mode in blocking mode. + * @param hxspi : XSPI handle + * @param pCfg : Pointer to structure that contains the polling configuration information. + * @param Timeout : Timeout duration + * @note This function is used only in Automatic Polling Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg, + uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + uint32_t addr_reg = hxspi->Instance->AR; + uint32_t ir_reg = hxspi->Instance->IR; +#ifdef USE_FULL_ASSERT + uint32_t dlr_reg = hxspi->Instance->DLR; +#endif /* USE_FULL_ASSERT */ + + /* Check the parameters of the autopolling configuration structure */ + assert_param(IS_XSPI_MATCH_MODE(pCfg->MatchMode)); + assert_param(IS_XSPI_AUTOMATIC_STOP(pCfg->AutomaticStop)); + assert_param(IS_XSPI_INTERVAL(pCfg->IntervalTime)); + assert_param(IS_XSPI_STATUS_BYTES_SIZE(dlr_reg + 1U)); + + /* Check the state */ + if ((hxspi->State == HAL_XSPI_STATE_CMD_CFG) && (pCfg->AutomaticStop == HAL_XSPI_AUTOMATIC_STOP_ENABLE)) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Configure registers */ + WRITE_REG(hxspi->Instance->PSMAR, pCfg->MatchValue); + WRITE_REG(hxspi->Instance->PSMKR, pCfg->MatchMask); + WRITE_REG(hxspi->Instance->PIR, pCfg->IntervalTime); + MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE), + (pCfg->MatchMode | pCfg->AutomaticStop | XSPI_FUNCTIONAL_MODE_AUTO_POLLING)); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hxspi->Instance->IR, ir_reg); + } + } + + /* Wait till status match flag is set to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_SM, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear status match flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_SM); + + hxspi->State = HAL_XSPI_STATE_READY; + } + } + else + { + status = HAL_BUSY; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Configure the XSPI Automatic Polling Mode in non-blocking mode. + * @param hxspi : XSPI handle + * @param pCfg : Pointer to structure that contains the polling configuration information. + * @note This function is used only in Automatic Polling Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + uint32_t addr_reg = hxspi->Instance->AR; + uint32_t ir_reg = hxspi->Instance->IR; +#ifdef USE_FULL_ASSERT + uint32_t dlr_reg = hxspi->Instance->DLR; +#endif /* USE_FULL_ASSERT */ + + /* Check the parameters of the autopolling configuration structure */ + assert_param(IS_XSPI_MATCH_MODE(pCfg->MatchMode)); + assert_param(IS_XSPI_AUTOMATIC_STOP(pCfg->AutomaticStop)); + assert_param(IS_XSPI_INTERVAL(pCfg->IntervalTime)); + assert_param(IS_XSPI_STATUS_BYTES_SIZE(dlr_reg + 1U)); + + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + /* Configure registers */ + WRITE_REG(hxspi->Instance->PSMAR, pCfg->MatchValue); + WRITE_REG(hxspi->Instance->PSMKR, pCfg->MatchMask); + WRITE_REG(hxspi->Instance->PIR, pCfg->IntervalTime); + MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE), + (pCfg->MatchMode | pCfg->AutomaticStop | XSPI_FUNCTIONAL_MODE_AUTO_POLLING)); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_SM); + + hxspi->State = HAL_XSPI_STATE_BUSY_AUTO_POLLING; + + /* Enable the status match and transfer error interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_SM | HAL_XSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) + { + WRITE_REG(hxspi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hxspi->Instance->IR, ir_reg); + } + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Configure the Memory Mapped mode. + * @param hxspi : XSPI handle + * @param pCfg : Pointer to structure that contains the memory mapped configuration information. + * @note This function is used only in Memory mapped Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const pCfg) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters of the memory-mapped configuration structure */ + assert_param(IS_XSPI_TIMEOUT_ACTIVATION(pCfg->TimeOutActivation)); + + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) + { + /* Wait till busy flag is reset */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_BUSY_MEM_MAPPED; + + if (pCfg->TimeOutActivation == HAL_XSPI_TIMEOUT_COUNTER_ENABLE) + { + assert_param(IS_XSPI_TIMEOUT_PERIOD(pCfg->TimeoutPeriodClock)); + + /* Configure register */ + WRITE_REG(hxspi->Instance->LPTR, pCfg->TimeoutPeriodClock); + + /* Clear flags related to interrupt */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TO); + + /* Enable the timeout interrupt */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TO); + } + + /* Configure CR register with functional mode as memory-mapped */ + MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_TCEN | XSPI_CR_FMODE), + (pCfg->TimeOutActivation | XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)); + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Transfer Error callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Abort completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @brief FIFO Threshold callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_FIFOThresholdCallback could be implemented in the user file + */ +} + +/** + * @brief Command completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_CmdCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Transfer completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_XSPI_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Status Match callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_StatusMatchCallback could be implemented in the user file + */ +} + +/** + * @brief Timeout callback. + * @param hxspi : XSPI handle + * @retval None + */ +__weak void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hxspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_XSPI_TimeOutCallback could be implemented in the user file + */ +} + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User XSPI Callback + * To be used to override the weak predefined callback + * @param hxspi : XSPI handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_XSPI_ERROR_CB_ID XSPI Error Callback ID + * @arg @ref HAL_XSPI_ABORT_CB_ID XSPI Abort Callback ID + * @arg @ref HAL_XSPI_FIFO_THRESHOLD_CB_ID XSPI FIFO Threshold Callback ID + * @arg @ref HAL_XSPI_CMD_CPLT_CB_ID XSPI Command Complete Callback ID + * @arg @ref HAL_XSPI_RX_CPLT_CB_ID XSPI Rx Complete Callback ID + * @arg @ref HAL_XSPI_TX_CPLT_CB_ID XSPI Tx Complete Callback ID + * @arg @ref HAL_XSPI_RX_HALF_CPLT_CB_ID XSPI Rx Half Complete Callback ID + * @arg @ref HAL_XSPI_TX_HALF_CPLT_CB_ID XSPI Tx Half Complete Callback ID + * @arg @ref HAL_XSPI_STATUS_MATCH_CB_ID XSPI Status Match Callback ID + * @arg @ref HAL_XSPI_TIMEOUT_CB_ID XSPI Timeout Callback ID + * @arg @ref HAL_XSPI_MSP_INIT_CB_ID XSPI MspInit callback ID + * @arg @ref HAL_XSPI_MSP_DEINIT_CB_ID XSPI MspDeInit callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID, + pXSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hxspi->State == HAL_XSPI_STATE_READY) + { + switch (CallbackID) + { + case HAL_XSPI_ERROR_CB_ID : + hxspi->ErrorCallback = pCallback; + break; + case HAL_XSPI_ABORT_CB_ID : + hxspi->AbortCpltCallback = pCallback; + break; + case HAL_XSPI_FIFO_THRESHOLD_CB_ID : + hxspi->FifoThresholdCallback = pCallback; + break; + case HAL_XSPI_CMD_CPLT_CB_ID : + hxspi->CmdCpltCallback = pCallback; + break; + case HAL_XSPI_RX_CPLT_CB_ID : + hxspi->RxCpltCallback = pCallback; + break; + case HAL_XSPI_TX_CPLT_CB_ID : + hxspi->TxCpltCallback = pCallback; + break; + case HAL_XSPI_RX_HALF_CPLT_CB_ID : + hxspi->RxHalfCpltCallback = pCallback; + break; + case HAL_XSPI_TX_HALF_CPLT_CB_ID : + hxspi->TxHalfCpltCallback = pCallback; + break; + case HAL_XSPI_STATUS_MATCH_CB_ID : + hxspi->StatusMatchCallback = pCallback; + break; + case HAL_XSPI_TIMEOUT_CB_ID : + hxspi->TimeOutCallback = pCallback; + break; + case HAL_XSPI_MSP_INIT_CB_ID : + hxspi->MspInitCallback = pCallback; + break; + case HAL_XSPI_MSP_DEINIT_CB_ID : + hxspi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hxspi->State == HAL_XSPI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_XSPI_MSP_INIT_CB_ID : + hxspi->MspInitCallback = pCallback; + break; + case HAL_XSPI_MSP_DEINIT_CB_ID : + hxspi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User XSPI Callback + * XSPI Callback is redirected to the weak predefined callback + * @param hxspi : XSPI handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_XSPI_ERROR_CB_ID XSPI Error Callback ID + * @arg @ref HAL_XSPI_ABORT_CB_ID XSPI Abort Callback ID + * @arg @ref HAL_XSPI_FIFO_THRESHOLD_CB_ID XSPI FIFO Threshold Callback ID + * @arg @ref HAL_XSPI_CMD_CPLT_CB_ID XSPI Command Complete Callback ID + * @arg @ref HAL_XSPI_RX_CPLT_CB_ID XSPI Rx Complete Callback ID + * @arg @ref HAL_XSPI_TX_CPLT_CB_ID XSPI Tx Complete Callback ID + * @arg @ref HAL_XSPI_RX_HALF_CPLT_CB_ID XSPI Rx Half Complete Callback ID + * @arg @ref HAL_XSPI_TX_HALF_CPLT_CB_ID XSPI Tx Half Complete Callback ID + * @arg @ref HAL_XSPI_STATUS_MATCH_CB_ID XSPI Status Match Callback ID + * @arg @ref HAL_XSPI_TIMEOUT_CB_ID XSPI Timeout Callback ID + * @arg @ref HAL_XSPI_MSP_INIT_CB_ID XSPI MspInit callback ID + * @arg @ref HAL_XSPI_MSP_DEINIT_CB_ID XSPI MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hxspi->State == HAL_XSPI_STATE_READY) + { + switch (CallbackID) + { + case HAL_XSPI_ERROR_CB_ID : + hxspi->ErrorCallback = HAL_XSPI_ErrorCallback; + break; + case HAL_XSPI_ABORT_CB_ID : + hxspi->AbortCpltCallback = HAL_XSPI_AbortCpltCallback; + break; + case HAL_XSPI_FIFO_THRESHOLD_CB_ID : + hxspi->FifoThresholdCallback = HAL_XSPI_FifoThresholdCallback; + break; + case HAL_XSPI_CMD_CPLT_CB_ID : + hxspi->CmdCpltCallback = HAL_XSPI_CmdCpltCallback; + break; + case HAL_XSPI_RX_CPLT_CB_ID : + hxspi->RxCpltCallback = HAL_XSPI_RxCpltCallback; + break; + case HAL_XSPI_TX_CPLT_CB_ID : + hxspi->TxCpltCallback = HAL_XSPI_TxCpltCallback; + break; + case HAL_XSPI_RX_HALF_CPLT_CB_ID : + hxspi->RxHalfCpltCallback = HAL_XSPI_RxHalfCpltCallback; + break; + case HAL_XSPI_TX_HALF_CPLT_CB_ID : + hxspi->TxHalfCpltCallback = HAL_XSPI_TxHalfCpltCallback; + break; + case HAL_XSPI_STATUS_MATCH_CB_ID : + hxspi->StatusMatchCallback = HAL_XSPI_StatusMatchCallback; + break; + case HAL_XSPI_TIMEOUT_CB_ID : + hxspi->TimeOutCallback = HAL_XSPI_TimeOutCallback; + break; + case HAL_XSPI_MSP_INIT_CB_ID : + hxspi->MspInitCallback = HAL_XSPI_MspInit; + break; + case HAL_XSPI_MSP_DEINIT_CB_ID : + hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; + break; + default : + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hxspi->State == HAL_XSPI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_XSPI_MSP_INIT_CB_ID : + hxspi->MspInitCallback = HAL_XSPI_MspInit; + break; + case HAL_XSPI_MSP_DEINIT_CB_ID : + hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; + break; + default : + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group3 Peripheral Control and State functions + * @brief XSPI control and State functions + * +@verbatim + =============================================================================== + ##### Peripheral Control and State functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Check in run-time the state of the driver. + (+) Check the error code set during last operation. + (+) Abort any operation. + (+) Manage the Fifo threshold. + (+) Configure the timeout duration used in the driver. + +@endverbatim + * @{ + */ + +/** + * @brief Abort the current operation, return to the indirect mode. + * @param hxspi : XSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t state; + uint32_t tickstart = HAL_GetTick(); + + /* Check if the state is in one of the busy or configured states */ + state = hxspi->State; + if (((state & XSPI_BUSY_STATE_MASK) != 0U) || ((state & XSPI_CFG_STATE_MASK) != 0U)) + { + /* Check if the DMA is enabled */ + if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) + { + /* Disable the DMA transfer on the XSPI side */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + + /* Disable the DMA transmit on the DMA side */ + status = HAL_DMA_Abort(hxspi->hdmatx); + if (status != HAL_OK) + { + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + } + + /* Disable the DMA receive on the DMA side */ + status = HAL_DMA_Abort(hxspi->hdmarx); + if (status != HAL_OK) + { + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + } + } + + if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) + { + /* Perform an abort of the XSPI */ + SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); + + /* Wait until the transfer complete flag is set to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + /* Clear transfer complete flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + + /* Wait until the busy flag is reset to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout); + + if (status == HAL_OK) + { + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); + + hxspi->State = HAL_XSPI_STATE_READY; + } + } + } + else + { + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); + + hxspi->State = HAL_XSPI_STATE_READY; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** + * @brief Abort the current operation, return to the indirect mode. (non-blocking function) + * @param hxspi : XSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t state; + + /* Check if the state is in one of the busy or configured states */ + state = hxspi->State; + if (((state & XSPI_BUSY_STATE_MASK) != 0U) || ((state & XSPI_CFG_STATE_MASK) != 0U)) + { + /* Disable all interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HAL_XSPI_IT_TE)); + + hxspi->State = HAL_XSPI_STATE_ABORT; + + /* Check if the DMA is enabled */ + if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) + { + /* Disable the DMA transfer on the XSPI side */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + + /* Disable the DMA transmit on the DMA side */ + hxspi->hdmatx->XferAbortCallback = XSPI_DMAAbortCplt; + if (HAL_DMA_Abort_IT(hxspi->hdmatx) != HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Abort callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->AbortCpltCallback(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + + /* Disable the DMA receive on the DMA side */ + hxspi->hdmarx->XferAbortCallback = XSPI_DMAAbortCplt; + if (HAL_DMA_Abort_IT(hxspi->hdmarx) != HAL_OK) + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Abort callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->AbortCpltCallback(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + else + { + if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) + { + /* Clear transfer complete flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + + /* Enable the transfer complete interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); + + /* Perform an abort of the XSPI */ + SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); + + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); + } + else + { + /* Return to indirect mode */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); + + hxspi->State = HAL_XSPI_STATE_READY; + + /* Abort callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->AbortCpltCallback(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** @brief Set XSPI Fifo threshold. + * @param hxspi : XSPI handle. + * @param Threshold : Threshold of the Fifo. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_XSPI_FIFO_THRESHOLD_BYTE(Threshold)); + + /* Check the state */ + if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) + { + /* Synchronize initialization structure with the new fifo threshold value */ + hxspi->Init.FifoThresholdByte = Threshold; + + /* Configure new fifo threshold */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FTHRES, ((hxspi->Init.FifoThresholdByte - 1U) << XSPI_CR_FTHRES_Pos)); + + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** @brief Get XSPI Fifo threshold. + * @param hxspi : XSPI handle. + * @retval Fifo threshold + */ +uint32_t HAL_XSPI_GetFifoThreshold(const XSPI_HandleTypeDef *hxspi) +{ + return ((READ_BIT(hxspi->Instance->CR, XSPI_CR_FTHRES) >> XSPI_CR_FTHRES_Pos) + 1U); +} + +/** @brief Set XSPI Memory Type. + * @param hxspi : XSPI handle. + * @param Type : Memory Type. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_SetMemoryType(XSPI_HandleTypeDef *hxspi, uint32_t Type) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_XSPI_MEMORY_TYPE(Type)); + + /* Check the state */ + if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) + { + /* Synchronize initialization structure with the new memory type value */ + hxspi->Init.MemoryType = Type; + + /* Configure new memory type */ + MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_MTYP, hxspi->Init.MemoryType); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** @brief Set XSPI Device Size. + * @param hxspi : XSPI handle. + * @param Size : Device Size. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_SetDeviceSize(XSPI_HandleTypeDef *hxspi, uint32_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_XSPI_MEMORY_SIZE(Size)); + + /* Check the state */ + if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) + { + /* Synchronize initialization structure with the new device size value */ + hxspi->Init.MemorySize = Size; + + /* Configure new device size */ + MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_DEVSIZE, + (hxspi->Init.MemorySize << XSPI_DCR1_DEVSIZE_Pos)); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** @brief Set XSPI Clock prescaler. + * @param hxspi : XSPI handle. + * @param Prescaler : Clock prescaler. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_SetClockPrescaler(XSPI_HandleTypeDef *hxspi, uint32_t Prescaler) +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_XSPI_CLK_PRESCALER(Prescaler)); + + /* Check the state */ + if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) + { + /* Synchronize initialization structure with the new clock prescaler value */ + hxspi->Init.ClockPrescaler = Prescaler; + + /* Configure clock prescaler */ + MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER, + ((hxspi->Init.ClockPrescaler) << XSPI_DCR2_PRESCALER_Pos)); + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + + return status; +} + +/** @brief Set XSPI timeout. + * @param hxspi : XSPI handle. + * @param Timeout : Timeout for the memory access. + * @retval HAL state + */ +HAL_StatusTypeDef HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout) +{ + hxspi->Timeout = Timeout; + return HAL_OK; +} + +/** + * @brief Return the XSPI error code. + * @param hxspi : XSPI handle + * @retval XSPI Error Code + */ +uint32_t HAL_XSPI_GetError(const XSPI_HandleTypeDef *hxspi) +{ + return hxspi->ErrorCode; +} + +/** + * @brief Return the XSPI handle state. + * @param hxspi : XSPI handle + * @retval HAL state + */ +uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi) +{ + /* Return XSPI handle state */ + return hxspi->State; +} + +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group4 IO Manager configuration function + * @brief XSPI IO Manager configuration function + * +@verbatim + =============================================================================== + ##### IO Manager configuration function ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Configure the IO manager. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the XSPI IO manager. + * @param hxspi : XSPI handle + * @param pCfg : Pointer to Configuration of the IO Manager for the instance + * @param Timeout : Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint8_t index; + uint8_t xspi_enabled = 0U; + + XSPIM_CfgTypeDef IOM_cfg[XSPI_NB_INSTANCE] = {0}; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Timeout); + + /* Check the parameters of the XSPI IO Manager configuration structure */ + assert_param(IS_XSPIM_NCS_OVR(pCfg->nCSOverride)); + assert_param(IS_XSPIM_IO_PORT(pCfg->IOPort)); + assert_param(IS_XSPIM_REQ2ACKTIME(pCfg->Req2AckTime)); + + /**************** Get current configuration of the instances ****************/ + for (index = 0U; index < XSPI_NB_INSTANCE; index++) + { + XSPIM_GetConfig(index + 1U, &(IOM_cfg[index])); + } + + /********** Disable both XSPI to configure XSPI IO Manager **********/ + if ((XSPI1->CR & XSPI_CR_EN) != 0U) + { + CLEAR_BIT(XSPI1->CR, XSPI_CR_EN); + xspi_enabled |= 0x1U; + } + if ((XSPI2->CR & XSPI_CR_EN) != 0U) + { + CLEAR_BIT(XSPI2->CR, XSPI_CR_EN); + xspi_enabled |= 0x2U; + } + + /***************** Deactivation of previous configuration *****************/ + CLEAR_REG(XSPIM->CR); + + /******************** Activation of new configuration *********************/ + MODIFY_REG(XSPIM->CR, XSPIM_CR_REQ2ACK_TIME, ((pCfg->Req2AckTime - 1U) << XSPIM_CR_REQ2ACK_TIME_Pos)); + + if (hxspi->Instance == XSPI1) + { + IOM_cfg[0].IOPort = pCfg->IOPort ; + if (pCfg->nCSOverride != HAL_XSPI_CSSEL_OVR_DISABLED) + { + MODIFY_REG(XSPIM->CR, (XSPIM_CR_CSSEL_OVR_O1 | XSPIM_CR_CSSEL_OVR_EN), (pCfg->nCSOverride)); + } + else + { + /* Nothing to do */ + } + } + else if (hxspi->Instance == XSPI2) + { + IOM_cfg[1].IOPort = pCfg->IOPort ; + if (pCfg->nCSOverride != HAL_XSPI_CSSEL_OVR_DISABLED) + { + MODIFY_REG(XSPIM->CR, (XSPIM_CR_CSSEL_OVR_O2 | XSPIM_CR_CSSEL_OVR_EN), (pCfg->nCSOverride)); + } + else + { + /* Nothing to do */ + } + } + else + { + return HAL_ERROR; + } + + for (index = 0U; index < (XSPI_NB_INSTANCE - 1U); index++) + { + if ((IOM_cfg[index].IOPort == IOM_cfg[index + 1U].IOPort)) + { + /*Mux*/ + SET_BIT(XSPIM->CR, XSPIM_CR_MUXEN); + } + else + { + /* Nothing to do */ + } + if (IOM_cfg[0].IOPort == HAL_XSPIM_IOPORT_2) + { + /*Mode*/ + SET_BIT(XSPIM->CR, XSPIM_CR_MODE); + } + else + { + /* Nothing to do */ + } + } + + /******* Re-enable both XSPI after configure XSPI IO Manager ********/ + if ((xspi_enabled & 0x1U) != 0U) + { + SET_BIT(XSPI1->CR, XSPI_CR_EN); + } + if ((xspi_enabled & 0x2U) != 0U) + { + SET_BIT(XSPI2->CR, XSPI_CR_EN); + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup XSPI_Exported_Functions_Group6 High-speed interface and calibration functions + * @brief XSPI high-speed interface and calibration functions + * +@verbatim + =============================================================================== + ##### High-speed interface and calibration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Get the delay values of the high-speed interface DLLs. + (+) Set a delay value for the high-speed interface DLLs. + +@endverbatim + * @{ + */ + +/** + * @brief Get the delay values of the high-speed interface DLLs. + * @param hxspi : XSPI handle + * @param pCfg : Current delay values corresponding to the DelayValueType field. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t reg = 0; + + if (IS_XSPI_ALL_INSTANCE(hxspi->Instance)) + { + /* Check the parameter specified in the structure */ + assert_param(IS_XSPI_DELAY_TYPE(pCfg->DelayValueType)); + + switch (pCfg->DelayValueType) + { + case HAL_XSPI_CAL_FULL_CYCLE_DELAY: + reg = hxspi->Instance->CALFCR; + pCfg->MaxCalibration = (reg & XSPI_CALFCR_CALMAX); + break; + case HAL_XSPI_CAL_FEEDBACK_CLK_DELAY: + reg = hxspi->Instance->CALMR; + break; + case HAL_XSPI_CAL_DATA_OUTPUT_DELAY: + reg = hxspi->Instance->CALSOR; + break; + case HAL_XSPI_CAL_DQS_INPUT_DELAY: + reg = hxspi->Instance->CALSIR; + break; + default: + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + break; + } + + if (status == HAL_OK) + { + pCfg->FineCalibrationUnit = (reg & XSPI_CALFCR_FINE); + pCfg->CoarseCalibrationUnit = ((reg & XSPI_CALFCR_COARSE) >> XSPI_CALFCR_COARSE_Pos); + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + + return status; +} + +/** + * @brief Set a delay value for the high-speed interface DLLs. + * @param hxspi : XSPI handle + * @param pCfg : Configuration of delay value specified in DelayValueType field. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (IS_XSPI_ALL_INSTANCE(hxspi->Instance)) + { + /* Check the parameter specified in the structure */ + assert_param(IS_XSPI_DELAY_TYPE(pCfg->DelayValueType)); + assert_param(IS_XSPI_FINECAL_VALUE(pCfg->FineCalibrationUnit)); + assert_param(IS_XSPI_COARSECAL_VALUE(pCfg->CoarseCalibrationUnit)); + + /* Check if the state isn't in one of the busy states */ + if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) + { + switch (pCfg->DelayValueType) + { + case HAL_XSPI_CAL_FEEDBACK_CLK_DELAY: + MODIFY_REG(hxspi->Instance->CALMR, (XSPI_CALMR_COARSE | XSPI_CALMR_FINE), + (pCfg->FineCalibrationUnit | (pCfg->CoarseCalibrationUnit << XSPI_CALMR_COARSE_Pos))); + break; + case HAL_XSPI_CAL_DATA_OUTPUT_DELAY: + MODIFY_REG(hxspi->Instance->CALSOR, (XSPI_CALSOR_COARSE | XSPI_CALSOR_FINE), + (pCfg->FineCalibrationUnit | (pCfg->CoarseCalibrationUnit << XSPI_CALSOR_COARSE_Pos))); + break; + case HAL_XSPI_CAL_DQS_INPUT_DELAY: + MODIFY_REG(hxspi->Instance->CALSIR, (XSPI_CALSIR_COARSE | XSPI_CALSIR_FINE), + (pCfg->FineCalibrationUnit | (pCfg->CoarseCalibrationUnit << XSPI_CALSIR_COARSE_Pos))); + break; + default: + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + break; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; + } + } + else + { + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + + return status; +} + +/** + * @} + */ + +/** + @cond 0 + */ +/** + * @brief DMA XSPI process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void XSPI_DMACplt(DMA_HandleTypeDef *hdma) +{ + XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); + hxspi->XferCount = 0; + + /* Disable the DMA transfer on the XSPI side */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + + /* Enable the XSPI transfer complete Interrupt */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); +} + +/** + * @brief DMA XSPI process half complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void XSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma) +{ + XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); + hxspi->XferCount = (hxspi->XferCount >> 1); + + if (hxspi->State == HAL_XSPI_STATE_BUSY_RX) + { +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->RxHalfCpltCallback(hxspi); +#else + HAL_XSPI_RxHalfCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + else + { +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->TxHalfCpltCallback(hxspi); +#else + HAL_XSPI_TxHalfCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } +} + +/** + * @brief DMA XSPI communication error callback. + * @param hdma : DMA handle + * @retval None + */ +static void XSPI_DMAError(DMA_HandleTypeDef *hdma) +{ + XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); + hxspi->XferCount = 0; + hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; + + /* Disable the DMA transfer on the XSPI side */ + CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); + + /* Abort the XSPI */ + if (HAL_XSPI_Abort_IT(hxspi) != HAL_OK) + { + /* Disable the interrupts */ + HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); + + hxspi->State = HAL_XSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } +} + +/** + * @brief DMA XSPI abort complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void XSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) +{ + XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); + hxspi->XferCount = 0; + + /* Check the state */ + if (hxspi->State == HAL_XSPI_STATE_ABORT) + { + /* DMA abort called by XSPI abort */ + if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) + { + /* Clear transfer complete flag */ + HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); + + /* Enable the transfer complete interrupts */ + HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); + + /* Perform an abort of the XSPI */ + SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); + } + else + { + hxspi->State = HAL_XSPI_STATE_READY; + + /* Abort callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->AbortCpltCallback(hxspi); +#else + HAL_XSPI_AbortCpltCallback(hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } + } + else + { + /* DMA abort called due to a transfer error interrupt */ + hxspi->State = HAL_XSPI_STATE_READY; + + /* Error callback */ +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + hxspi->ErrorCallback(hxspi); +#else + HAL_XSPI_ErrorCallback(hxspi); +#endif /* defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + } +} + +/** + * @brief Wait for a flag state until timeout. + * @param hxspi : XSPI handle + * @param Flag : Flag checked + * @param State : Value of the flag expected + * @param Timeout : Duration of the timeout + * @param Tickstart : Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, + FlagStatus State, uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is in expected state */ + while ((HAL_XSPI_GET_FLAG(hxspi, Flag)) != State) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hxspi->State = HAL_XSPI_STATE_ERROR; + hxspi->ErrorCode |= HAL_XSPI_ERROR_TIMEOUT; + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Configure the registers for the regular command mode. + * @param hxspi : XSPI handle + * @param pCmd : structure that contains the command configuration information + * @retval HAL status + */ +static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *pCmd) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *ccr_reg; + __IO uint32_t *tcr_reg; + __IO uint32_t *ir_reg; + __IO uint32_t *abr_reg; + + /* Re-initialize the value of the functional mode */ + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, 0U); + + if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) + { + assert_param(IS_XSPI_IO_SELECT(pCmd->IOSelect)); + MODIFY_REG(hxspi->Instance->CR, XSPI_CR_MSEL, pCmd->IOSelect); + } + + if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) + { + ccr_reg = &(hxspi->Instance->WCCR); + tcr_reg = &(hxspi->Instance->WTCR); + ir_reg = &(hxspi->Instance->WIR); + abr_reg = &(hxspi->Instance->WABR); + } + else if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG) + { + ccr_reg = &(hxspi->Instance->WPCCR); + tcr_reg = &(hxspi->Instance->WPTCR); + ir_reg = &(hxspi->Instance->WPIR); + abr_reg = &(hxspi->Instance->WPABR); + } + else + { + ccr_reg = &(hxspi->Instance->CCR); + tcr_reg = &(hxspi->Instance->TCR); + ir_reg = &(hxspi->Instance->IR); + abr_reg = &(hxspi->Instance->ABR); + } + + /* Configure the CCR register with DQS and SIOO modes */ + *ccr_reg = pCmd->DQSMode; + + if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE) + { + /* Configure the ABR register with alternate bytes value */ + *abr_reg = pCmd->AlternateBytes; + + /* Configure the CCR register with alternate bytes communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_ABMODE | XSPI_CCR_ABDTR | XSPI_CCR_ABSIZE), + (pCmd->AlternateBytesMode | pCmd->AlternateBytesDTRMode | pCmd->AlternateBytesWidth)); + } + + /* Configure the TCR register with the number of dummy cycles */ + MODIFY_REG((*tcr_reg), XSPI_TCR_DCYC, pCmd->DummyCycles); + + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + /* Configure the DLR register with the number of data */ + hxspi->Instance->DLR = (pCmd->DataLength - 1U); + } + } + + if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE) + { + if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) + { + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + /* ---- Command with instruction, address and data ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE | + XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE | + XSPI_CCR_DMODE | XSPI_CCR_DDTR), + (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth | + pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth | + pCmd->DataMode | pCmd->DataDTRMode)); + } + else + { + /* ---- Command with instruction and address ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE | + XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE), + (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth | + pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth)); + + /* The DHQC bit is linked with DDTR bit which should be activated */ + if ((hxspi->Init.DelayHoldQuarterCycle == HAL_XSPI_DHQC_ENABLE) && + (pCmd->InstructionDTRMode == HAL_XSPI_INSTRUCTION_DTR_ENABLE)) + { + MODIFY_REG((*ccr_reg), XSPI_CCR_DDTR, HAL_XSPI_DATA_DTR_ENABLE); + } + } + /* Configure the IR register with the instruction value */ + *ir_reg = pCmd->Instruction; + + /* Configure the AR register with the address value */ + hxspi->Instance->AR = pCmd->Address; + } + else + { + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + /* ---- Command with instruction and data ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE | + XSPI_CCR_DMODE | XSPI_CCR_DDTR), + (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth | + pCmd->DataMode | pCmd->DataDTRMode)); + } + else + { + /* ---- Command with only instruction ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE), + (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth)); + + /* The DHQC bit is linked with DDTR bit which should be activated */ + if ((hxspi->Init.DelayHoldQuarterCycle == HAL_XSPI_DHQC_ENABLE) && + (pCmd->InstructionDTRMode == HAL_XSPI_INSTRUCTION_DTR_ENABLE)) + { + MODIFY_REG((*ccr_reg), XSPI_CCR_DDTR, HAL_XSPI_DATA_DTR_ENABLE); + } + } + + /* Configure the IR register with the instruction value */ + *ir_reg = pCmd->Instruction; + + } + } + else + { + if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) + { + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + /* ---- Command with address and data ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE | + XSPI_CCR_DMODE | XSPI_CCR_DDTR), + (pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth | + pCmd->DataMode | pCmd->DataDTRMode)); + } + else + { + /* ---- Command with only address ---- */ + + /* Configure the CCR register with all communication parameters */ + MODIFY_REG((*ccr_reg), (XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE), + (pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth)); + } + + /* Configure the AR register with the instruction value */ + hxspi->Instance->AR = pCmd->Address; + } + else + { + /* ---- Invalid command configuration (no instruction, no address) ---- */ + status = HAL_ERROR; + hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; + } + } + + return status; +} + +/** + * @brief Get the current IOM configuration for an XSPI instance. + * @param instance_nb : number of the instance + * @param pCfg : configuration of the IO Manager for the instance + * @retval HAL status + */ +static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *const pCfg) +{ + uint32_t mux; + uint32_t mode; + + if (instance_nb == 1U) + { + if ((XSPIM->CR & XSPIM_CR_MODE) == 0U) + { + pCfg->IOPort = HAL_XSPIM_IOPORT_1; + } + else + { + pCfg->IOPort = HAL_XSPIM_IOPORT_2; + } + + if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_EN) != XSPIM_CR_CSSEL_OVR_EN) + { + pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_DISABLED; + } + else if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_O1) == XSPIM_CR_CSSEL_OVR_O1) + { + pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS2; + } + else + { + pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1; + } + } + else + { + mux = (XSPIM->CR & XSPIM_CR_MUXEN); + mode = ((XSPIM->CR & XSPIM_CR_MODE) >> XSPIM_CR_MODE_Pos); + if (mux != mode) + { + pCfg->IOPort = HAL_XSPIM_IOPORT_1; + } + else + { + pCfg->IOPort = HAL_XSPIM_IOPORT_2; + } + if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_EN) != XSPIM_CR_CSSEL_OVR_EN) + { + pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_DISABLED; + } + else if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_O2) == XSPIM_CR_CSSEL_OVR_O2) + { + pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS2; + } + else + { + pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1; + } + } +} +/** + @endcond + */ + +/** + * @} + */ + +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* XSPI || XSPI1 || XSPI2 */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_adc.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_adc.c new file mode 100644 index 00000000000..ff334a8079a --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_adc.c @@ -0,0 +1,1067 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_adc.c + * @author MCD Application Team + * @brief ADC LL module driver + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_adc.h" +#include "stm32h7rsxx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (ADC1) || defined (ADC2) + +/** @addtogroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup ADC_LL_Private_Constants + * @{ + */ + +/* Definitions of ADC hardware constraints delays */ +/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ +/* not timeout values: */ +/* Timeout values for ADC operations are dependent to device clock */ +/* configuration (system clock versus ADC clock), */ +/* and therefore must be defined in user application. */ +/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ +/* values definition. */ +/* Note: ADC timeout values are defined here in CPU cycles to be independent */ +/* of device clock setting. */ +/* In user application, ADC timeout values should be defined with */ +/* temporal values, in function of device clock settings. */ +/* Highest ratio CPU clock frequency vs ADC clock frequency: */ +/* - ADC clock from synchronous clock with AHB prescaler 512, */ +/* ADC prescaler 4. */ +/* Ratio max = 512 *4 = 2048 */ +/* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */ +/* Highest CPU clock PLL (PLLR). */ +/* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */ +/* = 3968 */ +/* Unit: CPU cycles. */ +#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (3968UL) +#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) +#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup ADC_LL_Private_Macros + * @{ + */ + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* common to several ADC instances. */ +#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ + (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC instance. */ +#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ + (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ + ) + +#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ + (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ + || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ + ) + +#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ + (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ + || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC group regular */ +#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM12_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_CH1) \ + ) + +#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ + (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ + || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ + ) + +#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ + (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ + || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ + || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ + ) + +#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \ + (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ + || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ + ) + +#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ + (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ + ) + +#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ + (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC group injected */ +#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ + (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM12_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1) \ + ) + +#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ + (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ + || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ + || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ + ) + +#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ + (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ + || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ + ) + +#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ + (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ + || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ + || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ + || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ + ) + +#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ + (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ + || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ + ) + +#if defined(ADC_MULTIMODE_SUPPORT) +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* multimode. */ +#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ + (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ + ) + +#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ + (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \ + ) + +#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ + (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ + ) + +#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ + (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ + || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ + || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ + ) + +#endif /* ADC_MULTIMODE_SUPPORT */ +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize registers of all ADC instances belonging to + * the same ADC common instance to their default reset values. + * @note This function is performing a hard reset, using high level + * clock source RCC ADC reset. + * Caution: On this STM32 series, if several ADC instances are available + * on the selected device, RCC ADC reset will reset + * all ADC instances belonging to the common ADC instance. + * To de-initialize only 1 ADC instance, use + * function @ref LL_ADC_DeInit(). + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC common registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Check the parameters */ + assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); + + /* Prevent unused argument compilation warning */ + (void)(ADCxy_COMMON); + + /* Force reset of ADC clock (core clock) */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ADC12); + + /* Release reset of ADC clock (core clock) */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12); + + return SUCCESS; +} + +/** + * @brief Initialize some features of ADC common parameters + * (all ADC instances belonging to the same ADC common instance) + * and multimode (for devices with several ADC instances available). + * @note The setting of ADC common parameters is conditioned to + * ADC instances state: + * All ADC instances belonging to the same ADC common instance + * must be disabled. + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC common registers are initialized + * - ERROR: ADC common registers are not initialized + */ +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); + assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock)); + +#if defined(ADC_MULTIMODE_SUPPORT) + assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode)); + if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + { + assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(pADC_CommonInitStruct->MultiDMATransfer)); + assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(pADC_CommonInitStruct->MultiTwoSamplingDelay)); + } +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Note: Hardware constraint (refer to description of functions */ + /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ + /* On this STM32 series, setting of these features is conditioned to */ + /* ADC state: */ + /* All ADC instances of the ADC common group must be disabled. */ + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) + { + /* Configuration of ADC hierarchical scope: */ + /* - common to several ADC */ + /* (all ADC instances belonging to the same ADC common instance) */ + /* - Set ADC clock (conversion clock) */ + /* - multimode (if several ADC instances available on the */ + /* selected device) */ + /* - Set ADC multimode configuration */ + /* - Set ADC multimode DMA transfer */ + /* - Set ADC multimode: delay between 2 sampling phases */ +#if defined(ADC_MULTIMODE_SUPPORT) + if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + { + MODIFY_REG(ADCxy_COMMON->CCR, + ADC_CCR_CKMODE + | ADC_CCR_PRESC + | ADC_CCR_DUAL + | ADC_CCR_MDMA + | ADC_CCR_DELAY + , + pADC_CommonInitStruct->CommonClock + | pADC_CommonInitStruct->Multimode + | pADC_CommonInitStruct->MultiDMATransfer + | pADC_CommonInitStruct->MultiTwoSamplingDelay + ); + } + else + { + MODIFY_REG(ADCxy_COMMON->CCR, + ADC_CCR_CKMODE + | ADC_CCR_PRESC + | ADC_CCR_DUAL + | ADC_CCR_MDMA + | ADC_CCR_DELAY + , + pADC_CommonInitStruct->CommonClock + | LL_ADC_MULTI_INDEPENDENT + ); + } +#else + LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock); +#endif /* ADC_MULTIMODE_SUPPORT */ + } + else + { + /* Initialization error: One or several ADC instances belonging to */ + /* the same ADC common instance are not disabled. */ + status = ERROR; + } + + return status; +} + +/** + * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. + * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) +{ + /* Set pADC_CommonInitStruct fields to default values */ + /* Set fields of ADC common */ + /* (all ADC instances belonging to the same ADC common instance) */ + pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; + +#if defined(ADC_MULTIMODE_SUPPORT) + /* Set fields of ADC multimode */ + pADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; + pADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; + pADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE; +#endif /* ADC_MULTIMODE_SUPPORT */ +} + +/** + * @brief De-initialize registers of the selected ADC instance + * to their default reset values. + * @note To reset all ADC instances quickly (perform a hard reset), + * use function @ref LL_ADC_CommonDeInit(). + * @note If this functions returns error status, it means that ADC instance + * is in an unknown state. + * In this case, perform a hard reset using high level + * clock source RCC ADC reset. + * Caution: On this STM32 series, if several ADC instances are available + * on the selected device, RCC ADC reset will reset + * all ADC instances belonging to the common ADC instance. + * Refer to function @ref LL_ADC_CommonDeInit(). + * @param ADCx ADC instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are de-initialized + * - ERROR: ADC registers are not de-initialized + */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) +{ + ErrorStatus status = SUCCESS; + + __IO uint32_t timeout_cpu_cycles = 0UL; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + + /* Disable ADC instance if not already disabled. */ + if (LL_ADC_IsEnabled(ADCx) == 1UL) + { + /* Stop potential ADC conversion on going on ADC group regular. */ + if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) + { + if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL) + { + LL_ADC_REG_StopConversion(ADCx); + } + } + + /* Stop potential ADC conversion on going on ADC group injected. */ + if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) + { + if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL) + { + LL_ADC_INJ_StopConversion(ADCx); + } + } + + /* Wait for ADC conversions are effectively stopped */ + timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; + while ((LL_ADC_REG_IsStopConversionOngoing(ADCx) + | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL) + { + timeout_cpu_cycles--; + if (timeout_cpu_cycles == 0UL) + { + /* Time-out error */ + status = ERROR; + break; + } + } + + /* Flush group injected contexts queue (register JSQR): */ + /* Note: Bit JQM must be set to empty the contexts queue (otherwise */ + /* contexts queue is maintained with the last active context). */ + LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY); + + /* Disable the ADC instance */ + LL_ADC_Disable(ADCx); + + /* Wait for ADC instance is effectively disabled */ + timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; + while (LL_ADC_IsDisableOngoing(ADCx) == 1UL) + { + timeout_cpu_cycles--; + if (timeout_cpu_cycles == 0UL) + { + /* Time-out error */ + status = ERROR; + break; + } + } + } + + /* Check whether ADC state is compliant with expected state */ + if (READ_BIT(ADCx->CR, + (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART + | ADC_CR_ADDIS | ADC_CR_ADEN) + ) + == 0UL) + { + /* ========== Reset ADC registers ========== */ + /* Reset register IER */ + CLEAR_BIT(ADCx->IER, + (LL_ADC_IT_ADRDY + | LL_ADC_IT_EOC + | LL_ADC_IT_EOS + | LL_ADC_IT_OVR + | LL_ADC_IT_EOSMP + | LL_ADC_IT_JEOC + | LL_ADC_IT_JEOS + | LL_ADC_IT_JQOVF + | LL_ADC_IT_AWD1 + | LL_ADC_IT_AWD2 + | LL_ADC_IT_AWD3 + ) + ); + + /* Reset register ISR */ + SET_BIT(ADCx->ISR, + (LL_ADC_FLAG_ADRDY + | LL_ADC_FLAG_EOC + | LL_ADC_FLAG_EOS + | LL_ADC_FLAG_OVR + | LL_ADC_FLAG_EOSMP + | LL_ADC_FLAG_JEOC + | LL_ADC_FLAG_JEOS + | LL_ADC_FLAG_JQOVF + | LL_ADC_FLAG_AWD1 + | LL_ADC_FLAG_AWD2 + | LL_ADC_FLAG_AWD3 + ) + ); + + /* Reset register CR */ + /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */ + /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */ + /* access mode "read-set": no direct reset applicable. */ + /* - Reset Calibration mode to default setting (single ended). */ + /* - Disable ADC internal voltage regulator. */ + /* - Enable ADC deep power down. */ + /* Note: ADC internal voltage regulator disable and ADC deep power */ + /* down enable are conditioned to ADC state disabled: */ + /* already done above. */ + CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); + SET_BIT(ADCx->CR, ADC_CR_DEEPPWD); + + /* Reset register CFGR */ + MODIFY_REG(ADCx->CFGR, + (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN + | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM + | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN + | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD + | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN + | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN), + ADC_CFGR_JQDIS + ); + + /* Reset register CFGR2 */ + CLEAR_BIT(ADCx->CFGR2, + (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS + | ADC_CFGR2_SWTRIG | ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG + | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) + ); + + /* Reset register SMPR1 */ + CLEAR_BIT(ADCx->SMPR1, + (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 + | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 + | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1) + ); + + /* Reset register SMPR2 */ + CLEAR_BIT(ADCx->SMPR2, + (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 + | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 + | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10) + ); + + /* Reset register TR1 */ + MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT | ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1); + + /* Reset register TR2 */ + MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2); + + /* Reset register TR3 */ + MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3); + + /* Reset register SQR1 */ + CLEAR_BIT(ADCx->SQR1, + (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 + | ADC_SQR1_SQ1 | ADC_SQR1_L) + ); + + /* Reset register SQR2 */ + CLEAR_BIT(ADCx->SQR2, + (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 + | ADC_SQR2_SQ6 | ADC_SQR2_SQ5) + ); + + /* Reset register SQR3 */ + CLEAR_BIT(ADCx->SQR3, + (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 + | ADC_SQR3_SQ11 | ADC_SQR3_SQ10) + ); + + /* Reset register SQR4 */ + CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); + + /* Reset register JSQR */ + CLEAR_BIT(ADCx->JSQR, + (ADC_JSQR_JL + | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN + | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 + | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1) + ); + + /* Reset register DR */ + /* Note: bits in access mode read only, no direct reset applicable */ + + /* Reset register OFR1 */ + CLEAR_BIT(ADCx->OFR1, + ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN | ADC_OFR1_OFFSETPOS); + /* Reset register OFR2 */ + CLEAR_BIT(ADCx->OFR2, + ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN | ADC_OFR2_OFFSETPOS); + /* Reset register OFR3 */ + CLEAR_BIT(ADCx->OFR3, + ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS); + /* Reset register OFR4 */ + CLEAR_BIT(ADCx->OFR4, + ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS); + + /* Reset registers JDR1, JDR2, JDR3, JDR4 */ + /* Note: bits in access mode read only, no direct reset applicable */ + + /* Reset register AWD2CR */ + CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH); + + /* Reset register AWD3CR */ + CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH); + + /* Reset register DIFSEL */ + CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL); + + /* Reset register CALFACT */ + CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); + } + else + { + /* ADC instance is in an unknown state */ + /* Need to performing a hard reset of ADC instance, using high level */ + /* clock source RCC ADC reset. */ + /* Caution: On this STM32 series, if several ADC instances are available */ + /* on the selected device, RCC ADC reset will reset */ + /* all ADC instances belonging to the common ADC instance. */ + /* Caution: On this STM32 series, if several ADC instances are available */ + /* on the selected device, RCC ADC reset will reset */ + /* all ADC instances belonging to the common ADC instance. */ + status = ERROR; + } + + return status; +} + +/** + * @brief Initialize some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Affects both group regular and group injected (availability + * of ADC group injected depends on STM32 series). + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 series. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, some other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group regular or group injected sequencer: + * map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + + assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution)); + assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment)); + assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if (LL_ADC_IsEnabled(ADCx) == 0UL) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC instance */ + /* - Set ADC data resolution */ + /* - Set ADC conversion data alignment */ + /* - Set ADC low power mode */ + MODIFY_REG(ADCx->CFGR, + ADC_CFGR_RES + | ADC_CFGR_ALIGN + | ADC_CFGR_AUTDLY + , + pADC_InitStruct->Resolution + | pADC_InitStruct->DataAlignment + | pADC_InitStruct->LowPowerMode + ); + + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + + return status; +} + +/** + * @brief Set each @ref LL_ADC_InitTypeDef field to default value. + * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct) +{ + /* Set pADC_InitStruct fields to default values */ + /* Set fields of ADC instance */ + pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; + pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; + pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; + +} + +/** + * @brief Initialize some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 series. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group regular or group injected sequencer: + * map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource)); + assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength)); + if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + { + assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont)); + + /* ADC group regular continuous mode and discontinuous mode */ + /* can not be enabled simultenaeously */ + assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); + } + assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode)); + assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer)); + assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if (LL_ADC_IsEnabled(ADCx) == 0UL) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC group regular */ + /* - Set ADC group regular trigger source */ + /* - Set ADC group regular sequencer length */ + /* - Set ADC group regular sequencer discontinuous mode */ + /* - Set ADC group regular continuous mode */ + /* - Set ADC group regular conversion data transfer: no transfer or */ + /* transfer by DMA, and DMA requests mode */ + /* - Set ADC group regular overrun behavior */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ + /* setting of trigger source to SW start. */ + if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + { + MODIFY_REG(ADCx->CFGR, + ADC_CFGR_EXTSEL + | ADC_CFGR_EXTEN + | ADC_CFGR_DISCEN + | ADC_CFGR_DISCNUM + | ADC_CFGR_CONT + | ADC_CFGR_ADFCFG + | ADC_CFGR_DMAEN + | ADC_CFGR_DMACFG + | ADC_CFGR_OVRMOD + , + pADC_RegInitStruct->TriggerSource + | pADC_RegInitStruct->SequencerDiscont + | pADC_RegInitStruct->ContinuousMode + | pADC_RegInitStruct->DMATransfer + | pADC_RegInitStruct->Overrun + ); + } + else + { + MODIFY_REG(ADCx->CFGR, + ADC_CFGR_EXTSEL + | ADC_CFGR_EXTEN + | ADC_CFGR_DISCEN + | ADC_CFGR_DISCNUM + | ADC_CFGR_CONT + | ADC_CFGR_ADFCFG + | ADC_CFGR_DMAEN + | ADC_CFGR_DMACFG + | ADC_CFGR_OVRMOD + , + pADC_RegInitStruct->TriggerSource + | LL_ADC_REG_SEQ_DISCONT_DISABLE + | pADC_RegInitStruct->ContinuousMode + | pADC_RegInitStruct->DMATransfer + | pADC_RegInitStruct->Overrun + ); + } + + /* Set ADC group regular sequencer length and scan direction */ + LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength); + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. + * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) +{ + /* Set pADC_RegInitStruct fields to default values */ + /* Set fields of ADC group regular */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ + /* setting of trigger source to SW start. */ + pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; + pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; + pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; + pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; + pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; + pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; +} + +/** + * @brief Initialize some features of ADC group injected. + * @note These parameters have an impact on ADC scope: ADC group injected. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "INJ"). + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 series. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group injected sequencer: + * map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @note Caution if feature ADC group injected contexts queue is enabled + * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ): + * using successively several times this function will appear as + * having no effect. + * To set several features of ADC group injected, use + * function @ref LL_ADC_INJ_ConfigQueueContext(). + * @param ADCx ADC instance + * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(pADC_InjInitStruct->TriggerSource)); + assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_InjInitStruct->SequencerLength)); + if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) + { + assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(pADC_InjInitStruct->SequencerDiscont)); + } + assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_InjInitStruct->TrigAuto)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if (LL_ADC_IsEnabled(ADCx) == 0UL) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC group injected */ + /* - Set ADC group injected trigger source */ + /* - Set ADC group injected sequencer length */ + /* - Set ADC group injected sequencer discontinuous mode */ + /* - Set ADC group injected conversion trigger: independent or */ + /* from ADC group regular */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ + /* setting of trigger source to SW start. */ + if (pADC_InjInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + { + MODIFY_REG(ADCx->CFGR, + ADC_CFGR_JDISCEN + | ADC_CFGR_JAUTO + , + pADC_InjInitStruct->SequencerDiscont + | pADC_InjInitStruct->TrigAuto + ); + } + else + { + MODIFY_REG(ADCx->CFGR, + ADC_CFGR_JDISCEN + | ADC_CFGR_JAUTO + , + LL_ADC_REG_SEQ_DISCONT_DISABLE + | pADC_InjInitStruct->TrigAuto + ); + } + + MODIFY_REG(ADCx->JSQR, + ADC_JSQR_JEXTSEL + | ADC_JSQR_JEXTEN + | ADC_JSQR_JL + , + pADC_InjInitStruct->TriggerSource + | pADC_InjInitStruct->SequencerLength + ); + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. + * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct) +{ + /* Set pADC_InjInitStruct fields to default values */ + /* Set fields of ADC group injected */ + pADC_InjInitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; + pADC_InjInitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; + pADC_InjInitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; + pADC_InjInitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 || ADC2 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_cordic.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_cordic.c new file mode 100644 index 00000000000..f671f2fbbcc --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_cordic.c @@ -0,0 +1,102 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_cordic.c + * @author MCD Application Team + * @brief CORDIC LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_cordic.h" +#include "stm32h7rsxx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(CORDIC) + +/** @addtogroup CORDIC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORDIC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup CORDIC_LL_EF_Init + * @{ + */ + +/** + * @brief De-Initialize CORDIC peripheral registers to their default reset values. + * @param CORDICx CORDIC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: CORDIC registers are de-initialized + * - ERROR: CORDIC registers are not de-initialized + */ +ErrorStatus LL_CORDIC_DeInit(const CORDIC_TypeDef *CORDICx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_CORDIC_ALL_INSTANCE(CORDICx)); + + if (CORDICx == CORDIC) + { + /* Force CORDIC reset */ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_CORDIC); + + /* Release CORDIC reset */ + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_CORDIC); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CORDIC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_crc.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_crc.c new file mode 100644 index 00000000000..b11a4d38c45 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_crc.c @@ -0,0 +1,103 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_crc.c + * @author MCD Application Team + * @brief CRC LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_crc.h" +#include "stm32h7rsxx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (CRC) + +/** @addtogroup CRC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CRC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup CRC_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize CRC registers (Registers restored to their default values). + * @param CRCx CRC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: CRC registers are de-initialized + * - ERROR: CRC registers are not de-initialized + */ +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(CRCx)); + + if (CRCx == CRC) + { + /* Force CRC reset */ + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_CRC); + + /* Release CRC reset */ + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_CRC); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (CRC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_crs.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_crs.c new file mode 100644 index 00000000000..c6702f2489e --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_crs.c @@ -0,0 +1,81 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_crs.c + * @author MCD Application Team + * @brief CRS LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_crs.h" +#include "stm32h7rsxx_ll_bus.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(CRS) + +/** @defgroup CRS_LL CRS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CRS_LL_Exported_Functions + * @{ + */ + +/** @addtogroup CRS_LL_EF_Init + * @{ + */ + +/** + * @brief De-Initializes CRS peripheral registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: CRS registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_CRS_DeInit(void) +{ + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_CRS); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_CRS); + + return SUCCESS; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRS) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_dlyb.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_dlyb.c new file mode 100644 index 00000000000..9a2b969a149 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_dlyb.c @@ -0,0 +1,243 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_dlyb.c + * @author MCD Application Team + * @brief DelayBlock Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the DelayBlock peripheral: + * + input clock frequency + * + up to 12 oversampling phases + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### DelayBlock peripheral features ##### + ============================================================================== + [..] The DelayBlock is used to generate an Output clock which is de-phased from the Input + clock. The phase of the Output clock is programmed by FW. The Output clock is then used + to clock the receive data in i.e. a SDMMC, OSPI or QSPI interface. + The delay is Voltage and Temperature dependent, which may require FW to do re-tuning + and recenter the Output clock phase to the receive data. + + [..] The DelayBlock features include the following: + (+) Input clock frequency. + (+) Up to 12 oversampling phases. + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a considered as a driver of service for external devices drivers + that interfaces with the DELAY peripheral. + The LL_DLYB_SetDelay() function, configure the Delay value configured on SEL and UNIT. + The LL_DLYB_GetDelay() function, return the Delay value configured on SEL and UNIT. + The LL_DLYB_GetClockPeriod()function, get the clock period. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +/** @defgroup DLYB_LL DLYB + * @brief DLYB LL module driver. + * @{ + */ + +#if defined(HAL_SD_MODULE_ENABLED) +#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) + +/** + @cond 0 + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define DLYB_TIMEOUT 0xFFU +#define DLYB_LNG_10_0_MASK 0x07FF0000U +#define DLYB_LNG_11_10_MASK 0x0C000000U +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** + @endcond + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DLYB_LL_Exported_Functions + * @brief Configuration and control functions + * +@verbatim + =============================================================================== + ##### Control functions ##### + =============================================================================== + [..] This section provides functions allowing to + (+) Control the DLYB. +@endverbatim + * @{ + */ + +/** @addtogroup DLYB_Control_Functions DLYB Control functions + * @{ + */ + +/** + * @brief Set the Delay value configured on SEL and UNIT. + * @param DLYBx: Pointer to DLYB instance. + * @param pdlyb_cfg: Pointer to DLYB configuration structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: the Delay value is set. + * - ERROR: the Delay value is not set. + */ +void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg) +{ + /* Check the DelayBlock instance */ + assert_param(IS_DLYB_ALL_INSTANCE(DLYBx)); + + /* Enable the length sampling */ + SET_BIT(DLYBx->CR, DLYB_CR_SEN); + + /* Update the UNIT and SEL field */ + DLYBx->CFGR = (pdlyb_cfg->PhaseSel) | ((pdlyb_cfg->Units) << DLYB_CFGR_UNIT_Pos); + + /* Disable the length sampling */ + CLEAR_BIT(DLYBx->CR, DLYB_CR_SEN); +} + +/** + * @brief Get the Delay value configured on SEL and UNIT. + * @param DLYBx: Pointer to DLYB instance. + * @param pdlyb_cfg: Pointer to DLYB configuration structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: the Delay value is received. + * - ERROR: the Delay value is not received. + */ +void LL_DLYB_GetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg) +{ + /* Check the DelayBlock instance */ + assert_param(IS_DLYB_ALL_INSTANCE(DLYBx)); + + /* Fill the DelayBlock configuration structure with SEL and UNIT value */ + pdlyb_cfg->Units = ((DLYBx->CFGR & DLYB_CFGR_UNIT) >> DLYB_CFGR_UNIT_Pos); + pdlyb_cfg->PhaseSel = (DLYBx->CFGR & DLYB_CFGR_SEL); +} + +/** + * @brief Get the clock period. + * @param DLYBx: Pointer to DLYB instance. + * @param pdlyb_cfg: Pointer to DLYB configuration structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: there is a valid period detected and stored in pdlyb_cfg. + * - ERROR: there is no valid period detected. + */ +uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg) +{ + uint32_t i = 0U; + uint32_t nb ; + uint32_t lng ; + uint32_t tickstart; + + /* Check the DelayBlock instance */ + assert_param(IS_DLYB_ALL_INSTANCE(DLYBx)); + + /* Enable the length sampling */ + SET_BIT(DLYBx->CR, DLYB_CR_SEN); + + /* Delay line length detection */ + while (i < DLYB_MAX_UNIT) + { + /* Set the Delay of the UNIT(s)*/ + DLYBx->CFGR = DLYB_MAX_SELECT | (i << DLYB_CFGR_UNIT_Pos); + + /* Waiting for a LNG valid value */ + tickstart = HAL_GetTick(); + while ((DLYBx->CFGR & DLYB_CFGR_LNGF) == 0U) + { + if ((HAL_GetTick() - tickstart) >= DLYB_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if ((DLYBx->CFGR & DLYB_CFGR_LNGF) == 0U) + { + return (uint32_t) HAL_TIMEOUT; + } + } + } + + if ((DLYBx->CFGR & DLYB_LNG_10_0_MASK) != 0U) + { + if ((DLYBx->CFGR & (DLYB_CFGR_LNG_11 | DLYB_CFGR_LNG_10)) != DLYB_LNG_11_10_MASK) + { + /* Delay line length is configured to one input clock period*/ + break; + } + } + i++; + } + + if (DLYB_MAX_UNIT != i) + { + /* Determine how many unit delays (nb) span one input clock period */ + lng = (DLYBx->CFGR & DLYB_CFGR_LNG) >> 16U; + nb = 10U; + while ((nb > 0U) && ((lng >> nb) == 0U)) + { + nb--; + } + if (nb != 0U) + { + pdlyb_cfg->PhaseSel = nb ; + pdlyb_cfg->Units = i ; + + /* Disable the length sampling */ + DLYBx->CR = DLYB_CR_SEN; + + return (uint32_t)SUCCESS; + } + } + + /* Disable the length sampling */ + DLYBx->CR = DLYB_CR_SEN; + + return (uint32_t)ERROR; + +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 */ +#endif /* HAL_SD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_dma.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_dma.c new file mode 100644 index 00000000000..0981fba0a73 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_dma.c @@ -0,0 +1,1195 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_dma.c + * @author MCD Application Team + * @brief DMA LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### LL DMA driver acronyms ##### + ============================================================================== + [..] Acronyms table : + ========================================= + || Acronym || || + ========================================= + || SRC || Source || + || DEST || Destination || + || ADDR || Address || + || ADDRS || Addresses || + || INC || Increment / Incremented || + || DEC || Decrement / Decremented || + || BLK || Block || + || RPT || Repeat / Repeated || + || TRIG || Trigger || + ========================================= + @endverbatim + ****************************************************************************** + */ + +#if defined (USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_dma.h" +#include "stm32h7rsxx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if (defined (GPDMA1) || defined (HPDMA1)) + +/** @addtogroup DMA_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup DMA_LL_Private_Macros + * @{ + */ +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == HPDMA1) && \ + (((Channel) == LL_DMA_CHANNEL_0) || \ + ((Channel) == LL_DMA_CHANNEL_1) || \ + ((Channel) == LL_DMA_CHANNEL_2) || \ + ((Channel) == LL_DMA_CHANNEL_3) || \ + ((Channel) == LL_DMA_CHANNEL_4) || \ + ((Channel) == LL_DMA_CHANNEL_5) || \ + ((Channel) == LL_DMA_CHANNEL_6) || \ + ((Channel) == LL_DMA_CHANNEL_7) || \ + ((Channel) == LL_DMA_CHANNEL_8) || \ + ((Channel) == LL_DMA_CHANNEL_9) || \ + ((Channel) == LL_DMA_CHANNEL_10) || \ + ((Channel) == LL_DMA_CHANNEL_11) || \ + ((Channel) == LL_DMA_CHANNEL_12) || \ + ((Channel) == LL_DMA_CHANNEL_13) || \ + ((Channel) == LL_DMA_CHANNEL_14) || \ + ((Channel) == LL_DMA_CHANNEL_15) || \ + ((Channel) == LL_DMA_CHANNEL_ALL))) || \ + (((INSTANCE) == GPDMA1) && \ + (((Channel) == LL_DMA_CHANNEL_0) || \ + ((Channel) == LL_DMA_CHANNEL_1) || \ + ((Channel) == LL_DMA_CHANNEL_2) || \ + ((Channel) == LL_DMA_CHANNEL_3) || \ + ((Channel) == LL_DMA_CHANNEL_4) || \ + ((Channel) == LL_DMA_CHANNEL_5) || \ + ((Channel) == LL_DMA_CHANNEL_6) || \ + ((Channel) == LL_DMA_CHANNEL_7) || \ + ((Channel) == LL_DMA_CHANNEL_8) || \ + ((Channel) == LL_DMA_CHANNEL_9) || \ + ((Channel) == LL_DMA_CHANNEL_10) || \ + ((Channel) == LL_DMA_CHANNEL_11) || \ + ((Channel) == LL_DMA_CHANNEL_12) || \ + ((Channel) == LL_DMA_CHANNEL_13) || \ + ((Channel) == LL_DMA_CHANNEL_14) || \ + ((Channel) == LL_DMA_CHANNEL_15) || \ + ((Channel) == LL_DMA_CHANNEL_ALL)))) + +#define IS_LL_HPDMA_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == HPDMA1) && \ + (((Channel) == LL_DMA_CHANNEL_0) || \ + ((Channel) == LL_DMA_CHANNEL_1) || \ + ((Channel) == LL_DMA_CHANNEL_2) || \ + ((Channel) == LL_DMA_CHANNEL_3) || \ + ((Channel) == LL_DMA_CHANNEL_4) || \ + ((Channel) == LL_DMA_CHANNEL_5) || \ + ((Channel) == LL_DMA_CHANNEL_6) || \ + ((Channel) == LL_DMA_CHANNEL_7) || \ + ((Channel) == LL_DMA_CHANNEL_8) || \ + ((Channel) == LL_DMA_CHANNEL_9) || \ + ((Channel) == LL_DMA_CHANNEL_10) || \ + ((Channel) == LL_DMA_CHANNEL_11) || \ + ((Channel) == LL_DMA_CHANNEL_12) || \ + ((Channel) == LL_DMA_CHANNEL_13) || \ + ((Channel) == LL_DMA_CHANNEL_14) || \ + ((Channel) == LL_DMA_CHANNEL_15))) + +#define IS_LL_GPDMA_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \ + (((Channel) == LL_DMA_CHANNEL_0) || \ + ((Channel) == LL_DMA_CHANNEL_1) || \ + ((Channel) == LL_DMA_CHANNEL_2) || \ + ((Channel) == LL_DMA_CHANNEL_3) || \ + ((Channel) == LL_DMA_CHANNEL_4) || \ + ((Channel) == LL_DMA_CHANNEL_5) || \ + ((Channel) == LL_DMA_CHANNEL_6) || \ + ((Channel) == LL_DMA_CHANNEL_7) || \ + ((Channel) == LL_DMA_CHANNEL_8) || \ + ((Channel) == LL_DMA_CHANNEL_9) || \ + ((Channel) == LL_DMA_CHANNEL_10) || \ + ((Channel) == LL_DMA_CHANNEL_11) || \ + ((Channel) == LL_DMA_CHANNEL_12) || \ + ((Channel) == LL_DMA_CHANNEL_13) || \ + ((Channel) == LL_DMA_CHANNEL_14) || \ + ((Channel) == LL_DMA_CHANNEL_15))) + +#define IS_LL_DMA_2D_CHANNEL_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == HPDMA1) && \ + (((Channel) == LL_DMA_CHANNEL_12) || \ + ((Channel) == LL_DMA_CHANNEL_13) || \ + ((Channel) == LL_DMA_CHANNEL_14) || \ + ((Channel) == LL_DMA_CHANNEL_15))) || \ + (((INSTANCE) == GPDMA1) && \ + (((Channel) == LL_DMA_CHANNEL_12) || \ + ((Channel) == LL_DMA_CHANNEL_13) || \ + ((Channel) == LL_DMA_CHANNEL_14) || \ + ((Channel) == LL_DMA_CHANNEL_15)))) + +#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_NORMAL) || \ + ((__VALUE__) == LL_DMA_PFCTRL)) + +#define IS_LL_DMA_PFREQ_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == HPDMA1) && \ + (((Channel) == LL_DMA_CHANNEL_15))) || \ + (((INSTANCE) == GPDMA1) && \ + (((Channel) == LL_DMA_CHANNEL_0) || \ + ((Channel) == LL_DMA_CHANNEL_15)))) + +#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY) || \ + ((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)) + +#define IS_LL_DMA_DATA_ALIGNMENT(__VALUE__) (((__VALUE__) == LL_DMA_DATA_ALIGN_ZEROPADD) || \ + ((__VALUE__) == LL_DMA_DATA_ALIGN_SIGNEXTPADD) || \ + ((__VALUE__) == LL_DMA_DATA_PACK_UNPACK)) + +#define IS_LL_DMA_BURST_LENGTH(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= 64U)) + +#define IS_LL_DMA_SRC_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_SRC_DATAWIDTH_BYTE) || \ + ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_HALFWORD) || \ + ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_WORD) || \ + ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_DOUBLEWORD)) + +#define IS_LL_DMA_DEST_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_DEST_DATAWIDTH_BYTE) || \ + ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_HALFWORD) || \ + ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_WORD) || \ + ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_DOUBLEWORD)) + +#define IS_LL_DMA_SRC_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_FIXED) || \ + ((__VALUE__) == LL_DMA_SRC_INCREMENT)) + +#define IS_LL_DMA_DEST_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_FIXED) || \ + ((__VALUE__) == LL_DMA_DEST_INCREMENT)) + +#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_LOW_PRIORITY_LOW_WEIGHT) || \ + ((__VALUE__) == LL_DMA_LOW_PRIORITY_MID_WEIGHT) || \ + ((__VALUE__) == LL_DMA_LOW_PRIORITY_HIGH_WEIGHT) || \ + ((__VALUE__) == LL_DMA_HIGH_PRIORITY)) + +#define IS_LL_DMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0xFFFFU) + +#define IS_LL_DMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x0EFFU) + +#define IS_LL_DMA_TRIGGER_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TRIGM_BLK_TRANSFER) || \ + ((__VALUE__) == LL_DMA_TRIGM_RPT_BLK_TRANSFER) || \ + ((__VALUE__) == LL_DMA_TRIGM_LLI_LINK_TRANSFER) || \ + ((__VALUE__) == LL_DMA_TRIGM_SINGLBURST_TRANSFER )) + +#define IS_LL_DMA_TRIGGER_POLARITY(__VALUE__) (((__VALUE__) == LL_DMA_TRIG_POLARITY_MASKED) || \ + ((__VALUE__) == LL_DMA_TRIG_POLARITY_RISING) || \ + ((__VALUE__) == LL_DMA_TRIG_POLARITY_FALLING)) + +#define IS_LL_DMA_BLKHW_REQUEST(__VALUE__) (((__VALUE__) == LL_DMA_HWREQUEST_SINGLEBURST) || \ + ((__VALUE__) == LL_DMA_HWREQUEST_BLK)) + +#define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_TIM15_TRGO) + +#define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_I3C1_RS) + +#define IS_LL_DMA_TRANSFER_EVENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TCEM_BLK_TRANSFER) || \ + ((__VALUE__) == LL_DMA_TCEM_RPT_BLK_TRANSFER) || \ + ((__VALUE__) == LL_DMA_TCEM_EACH_LLITEM_TRANSFER) || \ + ((__VALUE__) == LL_DMA_TCEM_LAST_LLITEM_TRANSFER)) + +#define IS_LL_DMA_DEST_WORD_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_WORD_PRESERVE) || \ + ((__VALUE__) == LL_DMA_DEST_WORD_EXCHANGE)) + +#define IS_LL_DMA_DEST_HALFWORD_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_HALFWORD_PRESERVE) || \ + ((__VALUE__) == LL_DMA_DEST_HALFWORD_EXCHANGE)) + +#define IS_LL_DMA_DEST_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_BYTE_PRESERVE) || \ + ((__VALUE__) == LL_DMA_DEST_BYTE_EXCHANGE)) + +#define IS_LL_DMA_SRC_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_BYTE_PRESERVE) || \ + ((__VALUE__) == LL_DMA_SRC_BYTE_EXCHANGE)) + +#define IS_LL_DMA_LINK_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT0) || \ + ((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT1)) + +#define IS_LL_DMA_SRC_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT0) || \ + ((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT1)) + +#define IS_LL_DMA_DEST_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT0) || \ + ((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT1)) + +#define IS_LL_DMA_LINK_STEP_MODE(__VALUE__) (((__VALUE__) == LL_DMA_LSM_FULL_EXECUTION) || \ + ((__VALUE__) == LL_DMA_LSM_1LINK_EXECUTION)) + +#define IS_LL_DMA_BURST_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_SRC_ADDR_INCREMENT) || \ + ((__VALUE__) == LL_DMA_BURST_SRC_ADDR_DECREMENT)) + +#define IS_LL_DMA_BURST_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_DEST_ADDR_INCREMENT) || \ + ((__VALUE__) == LL_DMA_BURST_DEST_ADDR_DECREMENT)) + +#define IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU) + +#define IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_INCREMENT) || \ + ((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_DECREMENT)) + +#define IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_INCREMENT) || \ + ((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_DECREMENT)) + +#define IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0xFFFFU) + +#define IS_LL_DMA_LINK_BASEADDR(__VALUE__) (((__VALUE__) & 0xFFFFU) == 0U) + +#define IS_LL_DMA_LINK_ADDR_OFFSET(__VALUE__) (((__VALUE__) & 0x03U) == 0U) + +#define IS_LL_DMA_LINK_UPDATE_REGISTERS(__VALUE__) ((((__VALUE__) & 0x01FE0000U) == 0U) && ((__VALUE__) != 0U)) + +#define IS_LL_DMA_LINK_NODETYPE(__VALUE__) (((__VALUE__) == LL_DMA_HPDMA_2D_NODE) || \ + ((__VALUE__) == LL_DMA_HPDMA_LINEAR_NODE) || \ + ((__VALUE__) == LL_DMA_GPDMA_2D_NODE) || \ + ((__VALUE__) == LL_DMA_GPDMA_LINEAR_NODE)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DMA_LL_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the DMA registers to their default reset values. + * @note This API is used for all available DMA channels. + * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use + * helper macros : + * @arg @ref LL_DMA_GET_INSTANCE + * @arg @ref LL_DMA_GET_CHANNEL + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval An ErrorStatus enumeration value: + * - SUCCESS : DMA registers are de-initialized. + * - ERROR : DMA registers are not de-initialized. + */ +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) +{ + DMA_Channel_TypeDef *tmp; + ErrorStatus status = SUCCESS; + + /* Check the DMA Instance DMAx and Channel parameters */ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); + + if (Channel == LL_DMA_CHANNEL_ALL) + { + if (DMAx == GPDMA1) + { + /* Force reset of DMA clock */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA1); + + /* Release reset of DMA clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA1); + } + else + { + /* Force reset of DMA clock */ + LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_HPDMA1); + + /* Release reset of DMA clock */ + LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_HPDMA1); + } + } + else + { + /* Get the DMA Channel Instance */ + tmp = (DMA_Channel_TypeDef *)(LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Suspend DMA channel */ + LL_DMA_SuspendChannel(DMAx, Channel); + + /* Disable the selected Channel */ + LL_DMA_ResetChannel(DMAx, Channel); + + /* Reset DMAx_Channely control register */ + LL_DMA_WriteReg(tmp, CLBAR, 0U); + + /* Reset DMAx_Channely control register */ + LL_DMA_WriteReg(tmp, CCR, 0U); + + /* Reset DMAx_Channely Configuration register */ + LL_DMA_WriteReg(tmp, CTR1, 0U); + + /* Reset DMAx_Channely transfer register 2 */ + LL_DMA_WriteReg(tmp, CTR2, 0U); + + /* Reset DMAx_Channely block number of data register */ + LL_DMA_WriteReg(tmp, CBR1, 0U); + + /* Reset DMAx_Channely source address register */ + LL_DMA_WriteReg(tmp, CSAR, 0U); + + /* Reset DMAx_Channely destination address register */ + LL_DMA_WriteReg(tmp, CDAR, 0U); + + /* Check DMA channel */ + if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U) + { + /* Reset DMAx_Channely transfer register 3 */ + LL_DMA_WriteReg(tmp, CTR3, 0U); + + /* Reset DMAx_Channely Block register 2 */ + LL_DMA_WriteReg(tmp, CBR2, 0U); + } + + /* Reset DMAx_Channely Linked list address register */ + LL_DMA_WriteReg(tmp, CLLR, 0U); + + /* Reset DMAx_Channely pending flags */ + LL_DMA_WriteReg(tmp, CFCR, 0x00003F00U); + + /* Reset DMAx_Channely attribute */ + LL_DMA_DisableChannelPrivilege(DMAx, Channel); + + } + + return (uint32_t)status; +} + +/** + * @brief Initialize the DMA registers according to the specified parameters + * in DMA_InitStruct. + * @note This API is used for all available DMA channels. + * @note A software request transfer can be done once programming the direction + * field in memory to memory value. + * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use + * helper macros : + * @arg @ref LL_DMA_GET_INSTANCE + * @arg @ref LL_DMA_GET_CHANNEL + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS : DMA registers are initialized. + * - ERROR : Not applicable. + */ +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Check the DMA parameters from DMA_InitStruct */ + assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); + + /* Check direction */ + if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY) + { + assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitStruct->Request)); + } + + assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitStruct->DataAlignment)); + assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitStruct->SrcDataWidth)); + assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitStruct->DestDataWidth)); + assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitStruct->SrcIncMode)); + assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitStruct->DestIncMode)); + assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); + assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitStruct->BlkDataLength)); + assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitStruct->TriggerPolarity)); + assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitStruct->BlkHWRequest)); + assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitStruct->TransferEventMode)); + assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitStruct->LinkStepMode)); + assert_param(IS_LL_DMA_LINK_BASEADDR(DMA_InitStruct->LinkedListBaseAddr)); + assert_param(IS_LL_DMA_LINK_ADDR_OFFSET(DMA_InitStruct->LinkedListAddrOffset)); + assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); + if (DMA_InitStruct->Mode == LL_DMA_PFCTRL) + { + assert_param(IS_LL_DMA_PFREQ_INSTANCE(DMAx, Channel)); + } + + /* Check DMA instance */ + if ((IS_LL_HPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) || (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)) + { + assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->SrcBurstLength)); + assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->DestBurstLength)); + assert_param(IS_LL_DMA_DEST_WORD_EXCHANGE(DMA_InitStruct->DestWordExchange)); + assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitStruct->DestHWordExchange)); + assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitStruct->DestByteExchange)); + assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitStruct->SrcByteExchange)); + assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitStruct->LinkAllocatedPort)); + assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitStruct->SrcAllocatedPort)); + assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitStruct->DestAllocatedPort)); + } + + /* Check trigger polarity */ + if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED) + { + assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitStruct->TriggerMode)); + assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitStruct->TriggerSelection)); + } + + /* Check DMA channel */ + if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U) + { + assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitStruct->BlkRptCount)); + assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitStruct->SrcAddrUpdateMode)); + assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitStruct->DestAddrUpdateMode)); + assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->SrcAddrOffset)); + assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->DestAddrOffset)); + assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitStruct->BlkRptSrcAddrUpdateMode)); + assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitStruct->BlkRptDestAddrUpdateMode)); + assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptSrcAddrOffset)); + assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptDestAddrOffset)); + } + + /*-------------------------- DMAx CLBAR Configuration ------------------------ + * Configure the Transfer linked list address with parameter : + * - LinkedListBaseAdd: DMA_CLBAR_LBA[31:16] bits + */ + LL_DMA_SetLinkedListBaseAddr(DMAx, Channel, DMA_InitStruct->LinkedListBaseAddr); + + /*-------------------------- DMAx CCR Configuration -------------------------- + * Configure the control parameter : + * - LinkAllocatedPort: DMA_CCR_LAP bit + * - LinkStepMode: DMA_CCR_LSM bit + * - Priority: DMA_CCR_PRIO [23:22] bits + */ + LL_DMA_ConfigControl(DMAx, Channel, DMA_InitStruct->Priority | \ + DMA_InitStruct->LinkAllocatedPort | \ + DMA_InitStruct->LinkStepMode); + + /*-------------------------- DMAx CTR1 Configuration ------------------------- + * Configure the Data transfer parameter : + * - DestAllocatedPort: DMA_CTR1_DAP bit + * - DestWordExchange: DMA_CTR1_DWX bit + * - DestHWordExchange: DMA_CTR1_DHX bit + * - DestByteExchange: DMA_CTR1_DBX bit + * - DestIncMode: DMA_CTR1_DINC bit + * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits + * - SrcAllocatedPort: DMA_CTR1_SAP bit + * - SrcByteExchange: DMA_CTR1_SBX bit + * - DataAlignment: DMA_CTR1_PAM [12:11] bits + * - SrcIncMode: DMA_CTR1_SINC bit + * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits + * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits + * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits + */ + LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->DestAllocatedPort | \ + DMA_InitStruct->DestWordExchange | \ + DMA_InitStruct->DestHWordExchange | \ + DMA_InitStruct->DestByteExchange | \ + DMA_InitStruct->DestIncMode | \ + DMA_InitStruct->DestDataWidth | \ + DMA_InitStruct->SrcAllocatedPort | \ + DMA_InitStruct->SrcByteExchange | \ + DMA_InitStruct->DataAlignment | \ + DMA_InitStruct->SrcIncMode | \ + DMA_InitStruct->SrcDataWidth); + /* Check DMA instance */ + if ((IS_LL_HPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) || (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)) + { + LL_DMA_ConfigBurstLength(DMAx, Channel, DMA_InitStruct->SrcBurstLength, + DMA_InitStruct->DestBurstLength); + } + + /*-------------------------- DMAx CTR2 Configuration ------------------------- + * Configure the channel transfer parameter : + * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits + * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits + * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits + * - BlkHWRequest: DMA_CTR2_BREQ bit + * - Mode: DMA_CTR2_PFREQ bit + * - Direction: DMA_CTR2_DREQ bit + * - Direction: DMA_CTR2_SWREQ bit + * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits + * - Request: DMA_CTR2_REQSEL [6:0] bits + */ + LL_DMA_ConfigChannelTransfer(DMAx, Channel, DMA_InitStruct->TransferEventMode | \ + DMA_InitStruct->TriggerPolarity | \ + DMA_InitStruct->BlkHWRequest | \ + DMA_InitStruct->Mode | \ + DMA_InitStruct->Direction); + + /* Check direction */ + if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY) + { + LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->Request); + } + + /* Check trigger polarity */ + if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED) + { + LL_DMA_SetHWTrigger(DMAx, Channel, DMA_InitStruct->TriggerSelection); + LL_DMA_SetTriggerMode(DMAx, Channel, DMA_InitStruct->TriggerMode); + } + + /*-------------------------- DMAx CBR1 Configuration ------------------------- + * Configure the Transfer Block counters and update mode with parameter : + * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits + * - BlkRptCount: DMA_CBR1_BRC[26:16] bits + * BlkRptCount field is supported only by 2D addressing channels. + * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit + * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels. + * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit + * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels. + * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit + * SrcAddrUpdateMode field is supported only by 2D addressing channels. + * - DestAddrUpdateMode: DMA_CBR1_DDEC bit + * DestAddrUpdateMode field is supported only by 2D addressing channels. + */ + LL_DMA_SetBlkDataLength(DMAx, Channel, DMA_InitStruct->BlkDataLength); + + /* Check DMA channel */ + if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U) + { + LL_DMA_SetBlkRptCount(DMAx, Channel, DMA_InitStruct->BlkRptCount); + LL_DMA_ConfigBlkRptAddrUpdate(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrUpdateMode | \ + DMA_InitStruct->BlkRptDestAddrUpdateMode | \ + DMA_InitStruct->SrcAddrUpdateMode | \ + DMA_InitStruct->DestAddrUpdateMode); + } + + /*-------------------------- DMAx CSAR and CDAR Configuration ---------------- + * Configure the Transfer source address with parameter : + * - SrcAddress: DMA_CSAR_SA[31:0] bits + * - DestAddress: DMA_CDAR_DA[31:0] bits + */ + LL_DMA_ConfigAddresses(DMAx, Channel, DMA_InitStruct->SrcAddress, DMA_InitStruct->DestAddress); + + /* Check DMA channel */ + if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U) + { + /*------------------------ DMAx CTR3 Configuration ------------------------- + * Configure the Transfer Block counters and update mode with parameter : + * - SrcAddrOffset: DMA_CTR3_SAO[28:16] bits + * SrcAddrOffset field is supported only by 2D addressing channels. + * - DestAddrOffset: DMA_CTR3_DAO[12:0] bits + * DestAddrOffset field is supported only by 2D addressing channels. + */ + LL_DMA_ConfigAddrUpdateValue(DMAx, Channel, DMA_InitStruct->SrcAddrOffset, DMA_InitStruct->DestAddrOffset); + + /*------------------------ DMAx CBR2 Configuration ----------------------- + * Configure the Transfer Block counters and update mode with parameter : + * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits + * BlkRptSrcAddrOffset field is supported only by 2D addressing channels. + * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits + * BlkRptDestAddrOffset field is supported only by 2D addressing channels. + */ + LL_DMA_ConfigBlkRptAddrUpdateValue(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrOffset, + DMA_InitStruct->BlkRptDestAddrOffset); + } + + /*-------------------------- DMAx CLLR Configuration ------------------------- + * Configure the Transfer linked list address with parameter : + * - DestAddrOffset: DMA_CLLR_LA[15:2] bits + */ + LL_DMA_SetLinkedListAddrOffset(DMAx, Channel, DMA_InitStruct->LinkedListAddrOffset); + + return (uint32_t)SUCCESS; +} + +/** + * @brief Set each @ref LL_DMA_InitTypeDef field to default value. + * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval None. + */ +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Set DMA_InitStruct fields to default values */ + DMA_InitStruct->SrcAddress = 0x00000000U; + DMA_InitStruct->DestAddress = 0x00000000U; + DMA_InitStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + DMA_InitStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST; + DMA_InitStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD; + DMA_InitStruct->SrcBurstLength = 1U; + DMA_InitStruct->DestBurstLength = 1U; + DMA_InitStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE; + DMA_InitStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE; + DMA_InitStruct->SrcIncMode = LL_DMA_SRC_FIXED; + DMA_InitStruct->DestIncMode = LL_DMA_DEST_FIXED; + DMA_InitStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT; + DMA_InitStruct->BlkDataLength = 0x00000000U; + DMA_InitStruct->Mode = LL_DMA_NORMAL; + DMA_InitStruct->BlkRptCount = 0x00000000U; + DMA_InitStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER; + DMA_InitStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED; + DMA_InitStruct->TriggerSelection = 0x00000000U; + DMA_InitStruct->Request = 0x00000000U; + DMA_InitStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER; + DMA_InitStruct->DestWordExchange = LL_DMA_DEST_WORD_PRESERVE; + DMA_InitStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE; + DMA_InitStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE; + DMA_InitStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE; + DMA_InitStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0; + DMA_InitStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0; + DMA_InitStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0; + DMA_InitStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION; + DMA_InitStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT; + DMA_InitStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT; + DMA_InitStruct->SrcAddrOffset = 0x00000000U; + DMA_InitStruct->DestAddrOffset = 0x00000000U; + DMA_InitStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT; + DMA_InitStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT; + DMA_InitStruct->BlkRptSrcAddrOffset = 0x00000000U; + DMA_InitStruct->BlkRptDestAddrOffset = 0x00000000U; + DMA_InitStruct->LinkedListBaseAddr = 0x00000000U; + DMA_InitStruct->LinkedListAddrOffset = 0x00000000U; +} + +/** + * @brief Set each @ref LL_DMA_InitLinkedListTypeDef field to default value. + * @param DMA_InitLinkedListStruct Pointer to + * a @ref LL_DMA_InitLinkedListTypeDef structure. + * @retval None. + */ +void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct) +{ + /* Set LL_DMA_InitLinkedListTypeDef fields to default values */ + DMA_InitLinkedListStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT; + DMA_InitLinkedListStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION; + DMA_InitLinkedListStruct->TransferEventMode = LL_DMA_TCEM_LAST_LLITEM_TRANSFER; + DMA_InitLinkedListStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0; +} + +/** + * @brief De-initialize the DMA linked list. + * @note This API is used for all available DMA channels. + * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use + * helper macros : + * @arg @ref LL_DMA_GET_INSTANCE + * @arg @ref LL_DMA_GET_CHANNEL + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @retval An ErrorStatus enumeration value: + * - SUCCESS : DMA registers are de-initialized. + * - ERROR : DMA registers are not de-initialized. + */ +uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return LL_DMA_DeInit(DMAx, Channel); +} + +/** + * @brief Initialize the DMA linked list according to the specified parameters + * in LL_DMA_InitLinkedListTypeDef. + * @note This API is used for all available DMA channels. + * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use + * helper macros : + * @arg @ref LL_DMA_GET_INSTANCE + * @arg @ref LL_DMA_GET_CHANNEL + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 + * @arg @ref LL_DMA_CHANNEL_9 + * @arg @ref LL_DMA_CHANNEL_10 + * @arg @ref LL_DMA_CHANNEL_11 + * @arg @ref LL_DMA_CHANNEL_12 + * @arg @ref LL_DMA_CHANNEL_13 + * @arg @ref LL_DMA_CHANNEL_14 + * @arg @ref LL_DMA_CHANNEL_15 + * @param DMA_InitLinkedListStruct pointer to + * a @ref LL_DMA_InitLinkedListTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS : DMA registers are initialized. + * - ERROR : Not applicable. + */ +uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct) +{ + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Check the DMA parameters from DMA_InitLinkedListStruct */ + assert_param(IS_LL_DMA_PRIORITY(DMA_InitLinkedListStruct->Priority)); + assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitLinkedListStruct->LinkStepMode)); + assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitLinkedListStruct->TransferEventMode)); + /* Check DMA instance */ + if ((IS_LL_HPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) || (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)) + { + assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitLinkedListStruct->LinkAllocatedPort)); + } + + /*-------------------------- DMAx CCR Configuration -------------------------- + * Configure the control parameter : + * - LinkAllocatedPort: DMA_CCR_LAP bit + * LinkAllocatedPort field is supported only by GPDMA channels. + * - LinkStepMode: DMA_CCR_LSM bit + * - Priority: DMA_CCR_PRIO [23:22] bits + */ + LL_DMA_ConfigControl(DMAx, Channel, DMA_InitLinkedListStruct->Priority | \ + DMA_InitLinkedListStruct->LinkAllocatedPort | \ + DMA_InitLinkedListStruct->LinkStepMode); + + /*-------------------------- DMAx CTR2 Configuration ------------------------- + * Configure the channel transfer parameter : + * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits + */ + LL_DMA_SetTransferEventMode(DMAx, Channel, DMA_InitLinkedListStruct->TransferEventMode); + + return (uint32_t)SUCCESS; +} + +/** + * @brief Set each @ref LL_DMA_InitNodeTypeDef field to default value. + * @param DMA_InitNodeStruct Pointer to a @ref LL_DMA_InitNodeTypeDef + * structure. + * @retval None. + */ +void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct) +{ + /* Set DMA_InitNodeStruct fields to default values */ + DMA_InitNodeStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0; + DMA_InitNodeStruct->DestWordExchange = LL_DMA_DEST_WORD_PRESERVE; + DMA_InitNodeStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE; + DMA_InitNodeStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE; + DMA_InitNodeStruct->DestBurstLength = 1U; + DMA_InitNodeStruct->DestIncMode = LL_DMA_DEST_FIXED; + DMA_InitNodeStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE; + DMA_InitNodeStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0; + DMA_InitNodeStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE; + DMA_InitNodeStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD; + DMA_InitNodeStruct->SrcBurstLength = 1U; + DMA_InitNodeStruct->SrcIncMode = LL_DMA_SRC_FIXED; + DMA_InitNodeStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE; + DMA_InitNodeStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER; + DMA_InitNodeStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED; + DMA_InitNodeStruct->TriggerSelection = 0x00000000U; + DMA_InitNodeStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER; + DMA_InitNodeStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST; + DMA_InitNodeStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + DMA_InitNodeStruct->Request = 0x00000000U; + DMA_InitNodeStruct->Mode = LL_DMA_NORMAL; + DMA_InitNodeStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT; + DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT; + DMA_InitNodeStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT; + DMA_InitNodeStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT; + DMA_InitNodeStruct->BlkRptCount = 0x00000000U; + DMA_InitNodeStruct->BlkDataLength = 0x00000000U; + DMA_InitNodeStruct->SrcAddress = 0x00000000U; + DMA_InitNodeStruct->DestAddress = 0x00000000U; + DMA_InitNodeStruct->DestAddrOffset = 0x00000000U; + DMA_InitNodeStruct->SrcAddrOffset = 0x00000000U; + DMA_InitNodeStruct->BlkRptDestAddrOffset = 0x00000000U; + DMA_InitNodeStruct->BlkRptSrcAddrOffset = 0x00000000U; + DMA_InitNodeStruct->UpdateRegisters = (LL_DMA_UPDATE_CTR1 | LL_DMA_UPDATE_CTR2 | \ + LL_DMA_UPDATE_CBR1 | LL_DMA_UPDATE_CSAR | \ + LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CTR3 | \ + LL_DMA_UPDATE_CBR2 | LL_DMA_UPDATE_CLLR); + DMA_InitNodeStruct->NodeType = LL_DMA_GPDMA_LINEAR_NODE; +} + +/** + * @brief Initializes DMA linked list node according to the specified + * parameters in the DMA_InitNodeStruct. + * @param DMA_InitNodeStruct Pointer to a LL_DMA_InitNodeTypeDef structure + * that contains linked list node + * registers configurations. + * @param pNode Pointer to linked list node to fill according to + * LL_DMA_LinkNodeTypeDef parameters. + * @retval None + */ +uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode) +{ + uint32_t reg_counter = 0U; + + /* Check the DMA Node type */ + assert_param(IS_LL_DMA_LINK_NODETYPE(DMA_InitNodeStruct->NodeType)); + + /* Check the DMA parameters from DMA_InitNodeStruct */ + assert_param(IS_LL_DMA_DIRECTION(DMA_InitNodeStruct->Direction)); + + /* Check direction */ + if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY) + { + assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitNodeStruct->Request)); + } + + assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitNodeStruct->DataAlignment)); + assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitNodeStruct->SrcDataWidth)); + assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitNodeStruct->DestDataWidth)); + assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitNodeStruct->SrcIncMode)); + assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitNodeStruct->DestIncMode)); + assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitNodeStruct->BlkDataLength)); + assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitNodeStruct->TriggerPolarity)); + assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitNodeStruct->BlkHWRequest)); + assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitNodeStruct->TransferEventMode)); + assert_param(IS_LL_DMA_LINK_UPDATE_REGISTERS(DMA_InitNodeStruct->UpdateRegisters)); + assert_param(IS_LL_DMA_MODE(DMA_InitNodeStruct->Mode)); + + /* Check trigger polarity */ + if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED) + { + assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode)); + assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection)); + } + + /* Check node type */ + if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_LINEAR_NODE) || \ + (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_LINEAR_NODE)) + { + assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->SrcBurstLength)); + assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->DestBurstLength)); + assert_param(IS_LL_DMA_DEST_WORD_EXCHANGE(DMA_InitNodeStruct->DestWordExchange)); + assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitNodeStruct->DestHWordExchange)); + assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitNodeStruct->DestByteExchange)); + assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitNodeStruct->SrcByteExchange)); + assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitNodeStruct->SrcAllocatedPort)); + assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitNodeStruct->DestAllocatedPort)); + } + + /* Check DMA channel */ + if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || \ + (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)) + { + assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitNodeStruct->BlkRptCount)); + assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitNodeStruct->SrcAddrUpdateMode)); + assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitNodeStruct->DestAddrUpdateMode)); + assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->SrcAddrOffset)); + assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->DestAddrOffset)); + assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode)); + assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptDestAddrUpdateMode)); + assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptSrcAddrOffset)); + assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptDestAddrOffset)); + } + + /* Check if CTR1 register update is enabled */ + if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR1) == LL_DMA_UPDATE_CTR1) + { + /*-------------------------- DMAx CTR1 Configuration ----------------------- + * Configure the Data transfer parameter : + * - DestAllocatedPort: DMA_CTR1_DAP bit + * - DestWordExchange: DMA_CTR1_DWX bit + * - DestHWordExchange: DMA_CTR1_DHX bit + * - DestByteExchange: DMA_CTR1_DBX bit + * - DestIncMode: DMA_CTR1_DINC bit + * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits + * - SrcAllocatedPort: DMA_CTR1_SAP bit + * - SrcByteExchange: DMA_CTR1_SBX bit + * - DataAlignment: DMA_CTR1_PAM [12:11] bits + * - SrcIncMode: DMA_CTR1_SINC bit + * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits + * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits + * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits + */ + + pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->DestIncMode | \ + DMA_InitNodeStruct->DestDataWidth | \ + DMA_InitNodeStruct->DataAlignment | \ + DMA_InitNodeStruct->SrcIncMode | \ + DMA_InitNodeStruct->SrcDataWidth); + + /* Update CTR1 register fields */ + pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestAllocatedPort | \ + DMA_InitNodeStruct->DestWordExchange | \ + DMA_InitNodeStruct->DestHWordExchange | \ + DMA_InitNodeStruct->DestByteExchange | \ + ((DMA_InitNodeStruct->DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) | \ + DMA_InitNodeStruct->SrcAllocatedPort | \ + DMA_InitNodeStruct->SrcByteExchange | \ + ((DMA_InitNodeStruct->SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos)); + + /* Increment counter for the next register */ + reg_counter++; + } + + + /* Check if CTR2 register update is enabled */ + if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR2) == LL_DMA_UPDATE_CTR2) + { + /*-------------------------- DMAx CTR2 Configuration ----------------------- + * Configure the channel transfer parameter : + * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits + * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits + * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits + * - Mode: DMA_CTR2_PFREQ bit + * - BlkHWRequest: DMA_CTR2_BREQ bit + * - Direction: DMA_CTR2_DREQ bit + * - Direction: DMA_CTR2_SWREQ bit + * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits + * - Request: DMA_CTR2_REQSEL [6:0] bits + */ + pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->TransferEventMode | \ + DMA_InitNodeStruct->TriggerPolarity | \ + DMA_InitNodeStruct->BlkHWRequest | \ + DMA_InitNodeStruct->Mode | \ + DMA_InitNodeStruct->Direction); + + /* Check direction */ + if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY) + { + pNode->LinkRegisters[reg_counter] |= DMA_InitNodeStruct->Request & DMA_CTR2_REQSEL; + } + + /* Check trigger polarity */ + if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED) + { + pNode->LinkRegisters[reg_counter] |= (((DMA_InitNodeStruct->TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & \ + DMA_CTR2_TRIGSEL) | DMA_InitNodeStruct->TriggerMode); + } + + + /* Increment counter for the next register */ + reg_counter++; + } + + /* Check if CBR1 register update is enabled */ + if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR1) == LL_DMA_UPDATE_CBR1) + { + /*-------------------------- DMAx CBR1 Configuration ----------------------- + * Configure the Transfer Block counters and update mode with parameter : + * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits + * - BlkRptCount: DMA_CBR1_BRC[26:16] bits + * BlkRptCount field is supported only by 2D addressing channels. + * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit + * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels. + * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit + * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels. + * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit + * SrcAddrUpdateMode field is supported only by 2D addressing channels. + * - DestAddrUpdateMode: DMA_CBR1_DDEC bit + * DestAddrUpdateMode field is supported only by 2D addressing channels. + */ + pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->BlkDataLength; + + /* Update CBR1 register fields for 2D addressing channels */ + if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || \ + (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)) + { + pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->BlkRptDestAddrUpdateMode | \ + DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode | \ + DMA_InitNodeStruct->DestAddrUpdateMode | \ + DMA_InitNodeStruct->SrcAddrUpdateMode | \ + ((DMA_InitNodeStruct->BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC)); + } + + /* Increment counter for the next register */ + reg_counter++; + } + + /* Check if CSAR register update is enabled */ + if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CSAR) == LL_DMA_UPDATE_CSAR) + { + /*-------------------------- DMAx CSAR Configuration ----------------------- + * Configure the Transfer Block counters and update mode with parameter : + * - SrcAddress: DMA_CSAR_SA[31:0] bits + */ + pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->SrcAddress; + + /* Increment counter for the next register */ + reg_counter++; + } + + + /* Check if CDAR register update is enabled */ + if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CDAR) == LL_DMA_UPDATE_CDAR) + { + /*-------------------------- DMAx CDAR Configuration ----------------------- + * Configure the Transfer Block counters and update mode with parameter : + * - DestAddress: DMA_CDAR_DA[31:0] bits + */ + pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->DestAddress; + + /* Increment counter for the next register */ + reg_counter++; + } + + + /* Update CTR3 register fields for 2D addressing channels */ + if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)) + { + /* Check if CTR3 register update is enabled */ + if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR3) == LL_DMA_UPDATE_CTR3) + { + /*-------------------------- DMAx CTR3 Configuration --------------------- + * Configure the Block counters and update mode with parameter : + * - DestAddressOffset: DMA_CTR3_DAO[12:0] bits + * DestAddressOffset field is supported only by 2D addressing channels. + * - SrcAddressOffset: DMA_CTR3_SAO[12:0] bits + * SrcAddressOffset field is supported only by 2D addressing channels. + */ + pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->SrcAddrOffset | \ + ((DMA_InitNodeStruct->DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); + + /* Increment counter for the next register */ + reg_counter++; + } + } + + + /* Update CBR2 register fields for 2D addressing channels */ + if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)) + { + /* Check if CBR2 register update is enabled */ + if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR2) == LL_DMA_UPDATE_CBR2) + { + /*-------------------------- DMAx CBR2 Configuration --------------------- + * Configure the Block counters and update mode with parameter : + * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits + * BlkRptDestAddrOffset field is supported only by 2D addressing channels. + * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits + * BlkRptSrcAddrOffset field is supported only by 2D addressing channels. + */ + pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->BlkRptSrcAddrOffset | \ + ((DMA_InitNodeStruct->BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & \ + DMA_CBR2_BRDAO)); + + /* Increment counter for the next register */ + reg_counter++; + } + } + + /* Check if CLLR register update is enabled */ + if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CLLR) == LL_DMA_UPDATE_CLLR) + { + /*-------------------------- DMAx CLLR Configuration ----------------------- + * Configure the Transfer Block counters and update mode with parameter : + * - UpdateRegisters DMA_CLLR_UT1 bit + * - UpdateRegisters DMA_CLLR_UT2 bit + * - UpdateRegisters DMA_CLLR_UB1 bit + * - UpdateRegisters DMA_CLLR_USA bit + * - UpdateRegisters DMA_CLLR_UDA bit + * - UpdateRegisters DMA_CLLR_UT3 bit + * DMA_CLLR_UT3 bit is discarded for linear addressing channels. + * - UpdateRegisters DMA_CLLR_UB2 bit + * DMA_CLLR_UB2 bit is discarded for linear addressing channels. + * - UpdateRegisters DMA_CLLR_ULL bit + */ + pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CLLR_UT2 | \ + DMA_CLLR_UB1 | DMA_CLLR_USA | \ + DMA_CLLR_UDA | DMA_CLLR_ULL))); + + /* Update CLLR register fields for 2D addressing channels */ + if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || \ + (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)) + { + pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CLLR_UB2)); + } + } + + return (uint32_t)SUCCESS; +} + +/** + * @brief Connect Linked list Nodes. + * @param pPrevLinkNode Pointer to previous linked list node to be connected to new Linked list node. + * @param PrevNodeCLLRIdx Offset of Previous Node CLLR register. + * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET. + * @param pNewLinkNode Pointer to new Linked list. + * @param NewNodeCLLRIdx Offset of New Node CLLR register. + * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET. + * @retval None + */ +void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx, + LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx) +{ + pPrevLinkNode->LinkRegisters[PrevNodeCLLRIdx] = (((uint32_t)pNewLinkNode & DMA_CLLR_LA) | \ + (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \ + DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ + DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL))); +} + +/** + * @brief Disconnect the next linked list node. + * @param pLinkNode Pointer to linked list node to be disconnected from the next one. + * @param LinkNodeCLLRIdx Offset of Link Node CLLR register. + * @retval None. + */ +void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx) +{ + pLinkNode->LinkRegisters[LinkNodeCLLRIdx] = 0; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* GPDMA1 || HPDMA1 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_dma2d.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_dma2d.c new file mode 100644 index 00000000000..51f4fe0325e --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_dma2d.c @@ -0,0 +1,633 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_dma2d.c + * @author MCD Application Team + * @brief DMA2D LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_dma2d.h" +#include "stm32h7rsxx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (DMA2D) + +/** @addtogroup DMA2D_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup DMA2D_LL_Private_Constants DMA2D Private Constants + * @{ + */ +#define LL_DMA2D_COLOR 0xFFU /*!< Maximum output color setting */ +#define LL_DMA2D_NUMBEROFLINES DMA2D_NLR_NL /*!< Maximum number of lines */ +#define LL_DMA2D_NUMBEROFPIXELS (DMA2D_NLR_PL >> DMA2D_NLR_PL_Pos) /*!< Maximum number of pixels per lines */ +#define LL_DMA2D_OFFSET_MAX 0x3FFFU /*!< Maximum output line offset expressed in pixels */ +#define LL_DMA2D_CLUTSIZE_MAX 0xFFU /*!< Maximum CLUT size */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup DMA2D_LL_Private_Macros + * @{ + */ +#define IS_LL_DMA2D_MODE(MODE) (((MODE) == LL_DMA2D_MODE_M2M) || \ + ((MODE) == LL_DMA2D_MODE_M2M_PFC) || \ + ((MODE) == LL_DMA2D_MODE_M2M_BLEND) || \ + ((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG) || \ + ((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG) || \ + ((MODE) == LL_DMA2D_MODE_R2M)) + +#define IS_LL_DMA2D_OCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB8888) || \ + ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB888) || \ + ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB565) || \ + ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB1555) || \ + ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB4444)) + +#define IS_LL_DMA2D_GREEN(GREEN) ((GREEN) <= LL_DMA2D_COLOR) +#define IS_LL_DMA2D_RED(RED) ((RED) <= LL_DMA2D_COLOR) +#define IS_LL_DMA2D_BLUE(BLUE) ((BLUE) <= LL_DMA2D_COLOR) +#define IS_LL_DMA2D_ALPHA(ALPHA) ((ALPHA) <= LL_DMA2D_COLOR) + +#define IS_LL_DMA2D_OFFSET_MODE(MODE) (((MODE) == LL_DMA2D_LINE_OFFSET_PIXELS) || \ + ((MODE) == LL_DMA2D_LINE_OFFSET_BYTES)) + +#define IS_LL_DMA2D_OFFSET(OFFSET) ((OFFSET) <= LL_DMA2D_OFFSET_MAX) + +#define IS_LL_DMA2D_LINE(LINES) ((LINES) <= LL_DMA2D_NUMBEROFLINES) +#define IS_LL_DMA2D_PIXEL(PIXELS) ((PIXELS) <= LL_DMA2D_NUMBEROFPIXELS) + +#define IS_LL_DMA2D_SWAP_MODE(MODE) (((MODE) == LL_DMA2D_SWAP_MODE_REGULAR) || \ + ((MODE) == LL_DMA2D_SWAP_MODE_TWO_BY_TWO)) + +#define IS_LL_DMA2D_ALPHAINV(ALPHA) (((ALPHA) == LL_DMA2D_ALPHA_REGULAR) || \ + ((ALPHA) == LL_DMA2D_ALPHA_INVERTED)) + +#define IS_LL_DMA2D_RBSWAP(RBSWAP) (((RBSWAP) == LL_DMA2D_RB_MODE_REGULAR) || \ + ((RBSWAP) == LL_DMA2D_RB_MODE_SWAP)) + +#define IS_LL_DMA2D_LCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB8888) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB888) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB565) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB1555) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB4444) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L8) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL44) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL88) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L4) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A8) || \ + ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A4)) + +#define IS_LL_DMA2D_CLUTCMODE(CLUTCMODE) (((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_ARGB8888) || \ + ((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_RGB888)) + +#define IS_LL_DMA2D_CLUTSIZE(SIZE) ((SIZE) <= LL_DMA2D_CLUTSIZE_MAX) + +#define IS_LL_DMA2D_ALPHAMODE(MODE) (((MODE) == LL_DMA2D_ALPHA_MODE_NO_MODIF) || \ + ((MODE) == LL_DMA2D_ALPHA_MODE_REPLACE) || \ + ((MODE) == LL_DMA2D_ALPHA_MODE_COMBINE)) + +#define IS_LL_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == LL_DMA2D_CSS_444) || \ + ((CSS) == LL_DMA2D_CSS_422) || \ + ((CSS) == LL_DMA2D_CSS_420)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA2D_LL_Exported_Functions + * @{ + */ + +/** @addtogroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions + * @{ + */ + +/** + * @brief De-initialize DMA2D registers (registers restored to their default values). + * @param DMA2Dx DMA2D Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA2D registers are de-initialized + * - ERROR: DMA2D registers are not de-initialized + */ +ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); + + if (DMA2Dx == DMA2D) + { + /* Force reset of DMA2D clock */ + LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_DMA2D); + + /* Release reset of DMA2D clock */ + LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_DMA2D); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize DMA2D registers according to the specified parameters in DMA2D_InitStruct. + * @note DMA2D transfers must be disabled to set initialization bits in configuration registers, + * otherwise ERROR result is returned. + * @param DMA2Dx DMA2D Instance + * @param DMA2D_InitStruct pointer to a LL_DMA2D_InitTypeDef structure + * that contains the configuration information for the specified DMA2D peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content + * - ERROR: Issue occurred during DMA2D registers initialization + */ +ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct) +{ + ErrorStatus status = ERROR; + LL_DMA2D_ColorTypeDef dma2d_colorstruct; + uint32_t tmp; + uint32_t tmp1; + uint32_t tmp2; + uint32_t regMask; + uint32_t regValue; + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); + assert_param(IS_LL_DMA2D_MODE(DMA2D_InitStruct->Mode)); + assert_param(IS_LL_DMA2D_OCMODE(DMA2D_InitStruct->ColorMode)); + assert_param(IS_LL_DMA2D_LINE(DMA2D_InitStruct->NbrOfLines)); + assert_param(IS_LL_DMA2D_PIXEL(DMA2D_InitStruct->NbrOfPixelsPerLines)); + assert_param(IS_LL_DMA2D_GREEN(DMA2D_InitStruct->OutputGreen)); + assert_param(IS_LL_DMA2D_RED(DMA2D_InitStruct->OutputRed)); + assert_param(IS_LL_DMA2D_BLUE(DMA2D_InitStruct->OutputBlue)); + assert_param(IS_LL_DMA2D_ALPHA(DMA2D_InitStruct->OutputAlpha)); + assert_param(IS_LL_DMA2D_SWAP_MODE(DMA2D_InitStruct->OutputSwapMode)); + assert_param(IS_LL_DMA2D_OFFSET_MODE(DMA2D_InitStruct->LineOffsetMode)); + assert_param(IS_LL_DMA2D_OFFSET(DMA2D_InitStruct->LineOffset)); + assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_InitStruct->AlphaInversionMode)); + assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_InitStruct->RBSwapMode)); + + /* DMA2D transfers must be disabled to configure bits in initialization registers */ + tmp = LL_DMA2D_IsTransferOngoing(DMA2Dx); + tmp1 = LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2Dx); + tmp2 = LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2Dx); + if ((tmp == 0U) && (tmp1 == 0U) && (tmp2 == 0U)) + { + /* DMA2D CR register configuration -------------------------------------------*/ + MODIFY_REG(DMA2Dx->CR, (DMA2D_CR_MODE | DMA2D_CR_LOM), \ + (DMA2D_InitStruct->Mode | DMA2D_InitStruct->LineOffsetMode)); + + /* DMA2D OPFCCR register configuration ---------------------------------------*/ + regMask = DMA2D_OPFCCR_CM; + regValue = DMA2D_InitStruct->ColorMode; + + regMask |= DMA2D_OPFCCR_SB; + regValue |= DMA2D_InitStruct->OutputSwapMode; + + regMask |= (DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI); + regValue |= (DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode); + + + MODIFY_REG(DMA2Dx->OPFCCR, regMask, regValue); + + /* DMA2D OOR register configuration ------------------------------------------*/ + LL_DMA2D_SetLineOffset(DMA2Dx, DMA2D_InitStruct->LineOffset); + + /* DMA2D NLR register configuration ------------------------------------------*/ + LL_DMA2D_ConfigSize(DMA2Dx, DMA2D_InitStruct->NbrOfLines, DMA2D_InitStruct->NbrOfPixelsPerLines); + + /* DMA2D OMAR register configuration ------------------------------------------*/ + LL_DMA2D_SetOutputMemAddr(DMA2Dx, DMA2D_InitStruct->OutputMemoryAddress); + + /* DMA2D OCOLR register configuration ------------------------------------------*/ + dma2d_colorstruct.ColorMode = DMA2D_InitStruct->ColorMode; + dma2d_colorstruct.OutputBlue = DMA2D_InitStruct->OutputBlue; + dma2d_colorstruct.OutputGreen = DMA2D_InitStruct->OutputGreen; + dma2d_colorstruct.OutputRed = DMA2D_InitStruct->OutputRed; + dma2d_colorstruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha; + LL_DMA2D_ConfigOutputColor(DMA2Dx, &dma2d_colorstruct); + + status = SUCCESS; + } + /* If DMA2D transfers are not disabled, return ERROR */ + + return (status); +} + +/** + * @brief Set each @ref LL_DMA2D_InitTypeDef field to default value. + * @param DMA2D_InitStruct pointer to a @ref LL_DMA2D_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct) +{ + /* Set DMA2D_InitStruct fields to default values */ + DMA2D_InitStruct->Mode = LL_DMA2D_MODE_M2M; + DMA2D_InitStruct->ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB8888; + DMA2D_InitStruct->NbrOfLines = 0x0U; + DMA2D_InitStruct->NbrOfPixelsPerLines = 0x0U; + DMA2D_InitStruct->LineOffsetMode = LL_DMA2D_LINE_OFFSET_PIXELS; + DMA2D_InitStruct->LineOffset = 0x0U; + DMA2D_InitStruct->OutputBlue = 0x0U; + DMA2D_InitStruct->OutputGreen = 0x0U; + DMA2D_InitStruct->OutputRed = 0x0U; + DMA2D_InitStruct->OutputAlpha = 0x0U; + DMA2D_InitStruct->OutputMemoryAddress = 0x0U; + DMA2D_InitStruct->OutputSwapMode = LL_DMA2D_SWAP_MODE_REGULAR; + DMA2D_InitStruct->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR; + DMA2D_InitStruct->RBSwapMode = LL_DMA2D_RB_MODE_REGULAR; +} + +/** + * @brief Configure the foreground or background according to the specified parameters + * in the LL_DMA2D_LayerCfgTypeDef structure. + * @param DMA2Dx DMA2D Instance + * @param DMA2D_LayerCfg pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains + * the configuration information for the specified layer. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) + * @retval None + */ +void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LL_DMA2D_OFFSET(DMA2D_LayerCfg->LineOffset)); + assert_param(IS_LL_DMA2D_LCMODE(DMA2D_LayerCfg->ColorMode)); + assert_param(IS_LL_DMA2D_CLUTCMODE(DMA2D_LayerCfg->CLUTColorMode)); + assert_param(IS_LL_DMA2D_CLUTSIZE(DMA2D_LayerCfg->CLUTSize)); + assert_param(IS_LL_DMA2D_ALPHAMODE(DMA2D_LayerCfg->AlphaMode)); + assert_param(IS_LL_DMA2D_GREEN(DMA2D_LayerCfg->Green)); + assert_param(IS_LL_DMA2D_RED(DMA2D_LayerCfg->Red)); + assert_param(IS_LL_DMA2D_BLUE(DMA2D_LayerCfg->Blue)); + assert_param(IS_LL_DMA2D_ALPHA(DMA2D_LayerCfg->Alpha)); + assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_LayerCfg->AlphaInversionMode)); + assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_LayerCfg->RBSwapMode)); + assert_param(IS_LL_DMA2D_CHROMA_SUB_SAMPLING(DMA2D_LayerCfg->ChromaSubSampling)); + + + if (LayerIdx == 0U) + { + /* Configure the background memory address */ + LL_DMA2D_BGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress); + + /* Configure the background line offset */ + LL_DMA2D_BGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset); + + /* Configure the background Alpha value, Alpha mode, RB swap, Alpha inversion + CLUT size, CLUT Color mode and Color mode */ + MODIFY_REG(DMA2Dx->BGPFCCR, \ + (DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_RBS | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_AM | \ + DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM | DMA2D_BGPFCCR_CM), \ + ((DMA2D_LayerCfg->Alpha << DMA2D_BGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \ + DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->AlphaMode | \ + (DMA2D_LayerCfg->CLUTSize << DMA2D_BGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \ + DMA2D_LayerCfg->ColorMode)); + + /* Configure the background color */ + LL_DMA2D_BGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue); + + /* Configure the background CLUT memory address */ + LL_DMA2D_BGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress); + } + else + { + /* Configure the foreground memory address */ + LL_DMA2D_FGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress); + + /* Configure the foreground line offset */ + LL_DMA2D_FGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset); + + /* Configure the foreground Alpha value, Alpha mode, RB swap, Alpha inversion + CLUT size, CLUT Color mode and Color mode */ + MODIFY_REG(DMA2Dx->FGPFCCR, \ + (DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_RBS | DMA2D_FGPFCCR_AI | DMA2D_FGPFCCR_CSS | DMA2D_FGPFCCR_AM | \ + DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM | DMA2D_FGPFCCR_CM), \ + ((DMA2D_LayerCfg->Alpha << DMA2D_FGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \ + DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->ChromaSubSampling | \ + DMA2D_LayerCfg->AlphaMode | (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | \ + DMA2D_LayerCfg->CLUTColorMode | DMA2D_LayerCfg->ColorMode)); + + /* Configure the foreground color */ + LL_DMA2D_FGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue); + + /* Configure the foreground CLUT memory address */ + LL_DMA2D_FGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress); + } +} + +/** + * @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value. + * @param DMA2D_LayerCfg pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg) +{ + /* Set DMA2D_LayerCfg fields to default values */ + DMA2D_LayerCfg->MemoryAddress = 0x0U; + DMA2D_LayerCfg->ColorMode = LL_DMA2D_INPUT_MODE_ARGB8888; + DMA2D_LayerCfg->LineOffset = 0x0U; + DMA2D_LayerCfg->CLUTColorMode = LL_DMA2D_CLUT_COLOR_MODE_ARGB8888; + DMA2D_LayerCfg->CLUTSize = 0x0U; + DMA2D_LayerCfg->AlphaMode = LL_DMA2D_ALPHA_MODE_NO_MODIF; + DMA2D_LayerCfg->Alpha = 0x0U; + DMA2D_LayerCfg->Blue = 0x0U; + DMA2D_LayerCfg->Green = 0x0U; + DMA2D_LayerCfg->Red = 0x0U; + DMA2D_LayerCfg->CLUTMemoryAddress = 0x0U; + DMA2D_LayerCfg->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR; + DMA2D_LayerCfg->RBSwapMode = LL_DMA2D_RB_MODE_REGULAR; + DMA2D_LayerCfg->ChromaSubSampling = LL_DMA2D_CSS_444; +} + +/** + * @brief Initialize DMA2D output color register according to the specified parameters + * in DMA2D_ColorStruct. + * @param DMA2Dx DMA2D Instance + * @param DMA2D_ColorStruct pointer to a LL_DMA2D_ColorTypeDef structure that contains + * the color configuration information for the specified DMA2D peripheral. + * @retval None + */ +void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct) +{ + uint32_t outgreen; + uint32_t outred; + uint32_t outalpha; + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); + assert_param(IS_LL_DMA2D_OCMODE(DMA2D_ColorStruct->ColorMode)); + assert_param(IS_LL_DMA2D_GREEN(DMA2D_ColorStruct->OutputGreen)); + assert_param(IS_LL_DMA2D_RED(DMA2D_ColorStruct->OutputRed)); + assert_param(IS_LL_DMA2D_BLUE(DMA2D_ColorStruct->OutputBlue)); + assert_param(IS_LL_DMA2D_ALPHA(DMA2D_ColorStruct->OutputAlpha)); + + /* DMA2D OCOLR register configuration ------------------------------------------*/ + if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888) + { + outgreen = DMA2D_ColorStruct->OutputGreen << 8U; + outred = DMA2D_ColorStruct->OutputRed << 16U; + outalpha = DMA2D_ColorStruct->OutputAlpha << 24U; + } + else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) + { + outgreen = DMA2D_ColorStruct->OutputGreen << 8U; + outred = DMA2D_ColorStruct->OutputRed << 16U; + outalpha = 0x00000000U; + } + else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565) + { + outgreen = DMA2D_ColorStruct->OutputGreen << 5U; + outred = DMA2D_ColorStruct->OutputRed << 11U; + outalpha = 0x00000000U; + } + else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555) + { + outgreen = DMA2D_ColorStruct->OutputGreen << 5U; + outred = DMA2D_ColorStruct->OutputRed << 10U; + outalpha = DMA2D_ColorStruct->OutputAlpha << 15U; + } + else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */ + { + outgreen = DMA2D_ColorStruct->OutputGreen << 4U; + outred = DMA2D_ColorStruct->OutputRed << 8U; + outalpha = DMA2D_ColorStruct->OutputAlpha << 12U; + } + LL_DMA2D_SetOutputColor(DMA2Dx, (outgreen | outred | DMA2D_ColorStruct->OutputBlue | outalpha)); +} + +/** + * @brief Return DMA2D output Blue color. + * @param DMA2Dx DMA2D Instance. + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 + * @retval Output Blue color value between Min_Data=0 and Max_Data=0xFF + */ +uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + uint32_t color; + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); + assert_param(IS_LL_DMA2D_OCMODE(ColorMode)); + + /* DMA2D OCOLR register reading ------------------------------------------*/ + if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU)); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU)); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU)); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU)); + } + else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */ + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFU)); + } + + return color; +} + +/** + * @brief Return DMA2D output Green color. + * @param DMA2Dx DMA2D Instance. + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 + * @retval Output Green color value between Min_Data=0 and Max_Data=0xFF + */ +uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + uint32_t color; + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); + assert_param(IS_LL_DMA2D_OCMODE(ColorMode)); + + /* DMA2D OCOLR register reading ------------------------------------------*/ + if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7E0U) >> 5U); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x3E0U) >> 5U); + } + else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */ + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF0U) >> 4U); + } + + return color; +} + +/** + * @brief Return DMA2D output Red color. + * @param DMA2Dx DMA2D Instance. + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 + * @retval Output Red color value between Min_Data=0 and Max_Data=0xFF + */ +uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + uint32_t color; + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); + assert_param(IS_LL_DMA2D_OCMODE(ColorMode)); + + /* DMA2D OCOLR register reading ------------------------------------------*/ + if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF800U) >> 11U); + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7C00U) >> 10U); + } + else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */ + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF00U) >> 8U); + } + + return color; +} + +/** + * @brief Return DMA2D output Alpha color. + * @param DMA2Dx DMA2D Instance. + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 + * @retval Output Alpha color value between Min_Data=0 and Max_Data=0xFF + */ +uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + uint32_t color; + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); + assert_param(IS_LL_DMA2D_OCMODE(ColorMode)); + + /* DMA2D OCOLR register reading ------------------------------------------*/ + if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF000000U) >> 24U); + } + else if ((ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) || (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)) + { + color = 0x0U; + } + else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555) + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x8000U) >> 15U); + } + else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */ + { + color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF000U) >> 12U); + } + + return color; +} + +/** + * @brief Configure DMA2D transfer size. + * @param DMA2Dx DMA2D Instance + * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF + * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF + * @retval None + */ +void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines) +{ + MODIFY_REG(DMA2Dx->NLR, (DMA2D_NLR_PL | DMA2D_NLR_NL), \ + ((NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos) | NbrOfLines)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (DMA2D) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_exti.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_exti.c new file mode 100644 index 00000000000..4402324bcb0 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_exti.c @@ -0,0 +1,321 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_exti.c + * @author MCD Application Team + * @brief EXTI LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_exti.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Private_Macros + * @{ + */ + +#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) +#define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U) +#define IS_LL_EXTI_LINE_64_95(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_64_95) == 0x00000000U) + +#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ + || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ + || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) + + +#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the EXTI registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_EXTI_DeInit(void) +{ + /* Interrupt mask register set to default reset values */ + LL_EXTI_WriteReg(IMR1, 0xFFC00000U); + /* Event mask register set to default reset values */ + LL_EXTI_WriteReg(EMR1, 0x00000000U); + /* Rising Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(RTSR1, 0x00000000U); + /* Falling Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(FTSR1, 0x00000000U); + /* Pending register clear */ + LL_EXTI_WriteReg(PR1, 0x003FFFFFU); + + /* Interrupt mask register 2 set to default reset values */ + LL_EXTI_WriteReg(IMR2, 0xFFB5BFFBU); + /* Event mask register 2 set to default reset values */ + LL_EXTI_WriteReg(EMR2, 0x00000000U); + /* Rising Trigger selection register 2 set to default reset values */ + LL_EXTI_WriteReg(RTSR2, 0x00000000U); + /* Falling Trigger selection register 2 set to default reset values */ + LL_EXTI_WriteReg(FTSR2, 0x00000000U); + /* Pending register 2 clear */ + LL_EXTI_WriteReg(PR2, 0x004A4004U); + + /* Interrupt mask register 3 set to default reset values */ + LL_EXTI_WriteReg(IMR3, 0x00003FFFU); + /* Event mask register 3 set to default reset values */ + LL_EXTI_WriteReg(EMR3, 0x00000000U); + + return SUCCESS; +} + +/** + * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. + * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are initialized + * - ERROR: not applicable + */ +ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + ErrorStatus status = SUCCESS; + /* Check the parameters */ + assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); + assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63)); + assert_param(IS_LL_EXTI_LINE_64_95(EXTI_InitStruct->Line_64_95)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); + assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); + + /* ENABLE LineCommand */ + if (EXTI_InitStruct->LineCommand != DISABLE) + { + assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); + + /* Configure EXTI Lines in range from 0 to 31 */ + if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) + { + switch (EXTI_InitStruct->Mode) + { + case LL_EXTI_MODE_IT: + /* First Disable Event on provided Lines */ + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_EVENT: + /* First Disable IT on provided Lines */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Event on provided Lines */ + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_IT_EVENT: + /* Directly Enable IT & Event on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + switch (EXTI_InitStruct->Trigger) + { + case LL_EXTI_TRIGGER_RISING: + /* First Disable Falling Trigger on provided Lines */ + LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Rising Trigger on provided Lines */ + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_FALLING: + /* First Disable Rising Trigger on provided Lines */ + LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_RISING_FALLING: + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + } + } + /* Configure EXTI Lines in range from 32 to 63 */ + if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE) + { + switch (EXTI_InitStruct->Mode) + { + case LL_EXTI_MODE_IT: + /* First Disable Event on provided Lines */ + LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63); + break; + case LL_EXTI_MODE_EVENT: + /* First Disable IT on provided Lines */ + LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); + /* Then Enable Event on provided Lines */ + LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63); + break; + case LL_EXTI_MODE_IT_EVENT: + /* Directly Enable IT & Event on provided Lines */ + LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63); + LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63); + break; + default: + status = ERROR; + break; + } + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + switch (EXTI_InitStruct->Trigger) + { + case LL_EXTI_TRIGGER_RISING: + /* First Disable Falling Trigger on provided Lines */ + LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63); + break; + case LL_EXTI_TRIGGER_FALLING: + /* First Disable Rising Trigger on provided Lines */ + LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63); + /* Then Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63); + break; + case LL_EXTI_TRIGGER_RISING_FALLING: + LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63); + LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63); + break; + default: + status = ERROR; + break; + } + } + } + /* Configure EXTI Lines in range from 64 to 95 */ + if (EXTI_InitStruct->Line_64_95 != LL_EXTI_LINE_NONE) + { + switch (EXTI_InitStruct->Mode) + { + case LL_EXTI_MODE_IT: + /* First Disable Event on provided Lines */ + LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableIT_64_95(EXTI_InitStruct->Line_64_95); + break; + case LL_EXTI_MODE_EVENT: + /* First Disable IT on provided Lines */ + LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95); + /* Then Enable Event on provided Lines */ + LL_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95); + break; + case LL_EXTI_MODE_IT_EVENT: + /* Directly Enable IT & Event on provided Lines */ + LL_EXTI_EnableIT_64_95(EXTI_InitStruct->Line_64_95); + LL_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95); + break; + default: + status = ERROR; + break; + } + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + status = ERROR; + } + } + } + /* DISABLE LineCommand */ + else + { + /* De-configure EXTI Lines in range from 0 to 31 */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + /* De-configure EXTI Lines in range from 32 to 63 */ + LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); + LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); + /* De-configure EXTI Lines in range from 64 to 95 */ + LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95); + LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95); + } + return status; +} + +/** + * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. + * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval None + */ +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; + EXTI_InitStruct->Line_32_63 = LL_EXTI_LINE_NONE; + EXTI_InitStruct->Line_64_95 = LL_EXTI_LINE_NONE; + EXTI_InitStruct->LineCommand = DISABLE; + EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; + EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (EXTI) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_fmc.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_fmc.c new file mode 100644 index 00000000000..54dc70a9a9f --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_fmc.c @@ -0,0 +1,1107 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_fmc.c + * @author MCD Application Team + * @brief FMC Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Flexible Memory Controller (FMC) peripheral memories: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### FMC peripheral features ##### + ============================================================================== + [..] The Flexible memory controller (FMC) includes following memory controllers: + (+) The NOR/PSRAM memory controller + (+) The NAND memory controller + (+) The Synchronous DRAM (SDRAM) controller + + [..] The FMC functional block makes the interface with synchronous and asynchronous static + memories and SDRAM memories. Its main purposes are: + (+) to translate AHB transactions into the appropriate external device protocol + (+) to meet the access time requirements of the external memory devices + + [..] All external memories share the addresses, data and control signals with the controller. + Each external device is accessed by means of a unique Chip Select. The FMC performs + only one access at a time to an external device. + The main features of the FMC controller are the following: + (+) Interface with static-memory mapped devices including: + (++) Static random access memory (SRAM) + (++) Read-only memory (ROM) + (++) NOR Flash memory/OneNAND Flash memory + (++) PSRAM (4 memory banks) + (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of + data + (+) Interface with synchronous DRAM (SDRAM) memories + (+) Independent Chip Select control for each memory bank + (+) Independent configuration for each memory bank + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ +#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\ + || defined(HAL_SRAM_MODULE_ENABLED) + +/** @defgroup FMC_LL FMC Low Layer + * @brief FMC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants + * @{ + */ + +/* ----------------------- FMC registers bit mask --------------------------- */ + +/* --- BCR Register ---*/ +/* BCR register clear mask */ + +/* --- BTR Register ---*/ +/* BTR register clear mask */ +#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\ + FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\ + FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\ + FMC_BTRx_ACCMOD)) + +/* --- BWTR Register ---*/ +/* BWTR register clear mask */ +#if defined(FMC_BWTRx_BUSTURN) +#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ + FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ + FMC_BWTRx_ACCMOD)) +#else +#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ + FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD)) +#endif /* FMC_BWTRx_BUSTURN */ + +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \ + FMC_PCR_PWID | FMC_PCR_ECCEN | \ + FMC_PCR_TCLR | FMC_PCR_TAR | \ + FMC_PCR_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\ + FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\ + FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ)) + + +/* --- SDCR Register ---*/ +/* SDCR register clear mask */ +#define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCRx_NC | FMC_SDCRx_NR | \ + FMC_SDCRx_MWID | FMC_SDCRx_NB | \ + FMC_SDCRx_CAS | FMC_SDCRx_WP | \ + FMC_SDCRx_SDCLK | FMC_SDCRx_RBURST | \ + FMC_SDCRx_RPIPE)) + +/* --- SDTR Register ---*/ +/* SDTR register clear mask */ +#define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTRx_TMRD | FMC_SDTRx_TXSR | \ + FMC_SDTRx_TRAS | FMC_SDTRx_TRC | \ + FMC_SDTRx_TWR | FMC_SDTRx_TRP | \ + FMC_SDTRx_TRCD)) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions + * @{ + */ + + +/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions + * @brief NORSRAM Controller functions + * + @verbatim + ============================================================================== + ##### How to use NORSRAM device driver ##### + ============================================================================== + + [..] + This driver contains a set of APIs to interface with the FMC NORSRAM banks in order + to run the NORSRAM external devices. + + (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() + (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() + (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() + (+) FMC NORSRAM bank extended timing configuration using the function + FMC_NORSRAM_Extended_Timing_Init() + (+) FMC NORSRAM bank enable/disable write operation using the functions + FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() + +@endverbatim + * @{ + */ + +/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC NORSRAM interface + (+) De-initialize the FMC NORSRAM interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the FMC_NORSRAM device according to the specified + * control parameters in the FMC_NORSRAM_InitTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Init Pointer to NORSRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_InitTypeDef *Init) +{ + uint32_t flashaccess; + uint32_t btcr_reg; + uint32_t mask; + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); + assert_param(IS_FMC_MUX(Init->DataAddressMux)); + assert_param(IS_FMC_MEMORY(Init->MemoryType)); + assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); + assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); + assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); + assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); + assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); + assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); + assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); + assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); + assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); + assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); + assert_param(IS_FMC_PAGESIZE(Init->PageSize)); + + /* Disable NORSRAM Device */ + __FMC_NORSRAM_DISABLE(Device, Init->NSBank); + + /* Set NORSRAM device control parameters */ + if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) + { + flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE; + } + else + { + flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE; + } + + btcr_reg = (flashaccess | \ + Init->DataAddressMux | \ + Init->MemoryType | \ + Init->MemoryDataWidth | \ + Init->BurstAccessMode | \ + Init->WaitSignalPolarity | \ + Init->WaitSignalActive | \ + Init->WriteOperation | \ + Init->WaitSignal | \ + Init->ExtendedMode | \ + Init->AsynchronousWait | \ + Init->WriteBurst); + + btcr_reg |= Init->ContinuousClock; + btcr_reg |= Init->WriteFifo; + btcr_reg |= Init->PageSize; + + mask = (FMC_BCRx_MBKEN | + FMC_BCRx_MUXEN | + FMC_BCRx_MTYP | + FMC_BCRx_MWID | + FMC_BCRx_FACCEN | + FMC_BCRx_BURSTEN | + FMC_BCRx_WAITPOL | + FMC_BCRx_WAITCFG | + FMC_BCRx_WREN | + FMC_BCRx_WAITEN | + FMC_BCRx_EXTMOD | + FMC_BCRx_ASYNCWAIT | + FMC_BCRx_CBURSTRW); + + mask |= FMC_BCR1_CCLKEN; + mask |= FMC_BCR1_WFDIS; + mask |= FMC_BCRx_CPSIZE; + + MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); + + /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ + if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) + { + MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); + } + + if (Init->NSBank != FMC_NORSRAM_BANK1) + { + /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */ + SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); + } + + return HAL_OK; +} + +/** + * @brief DeInitialize the FMC_NORSRAM peripheral + * @param Device Pointer to NORSRAM device instance + * @param ExDevice Pointer to NORSRAM extended mode device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Disable the FMC_NORSRAM device */ + __FMC_NORSRAM_DISABLE(Device, Bank); + + /* De-initialize the FMC_NORSRAM device */ + /* FMC_NORSRAM_BANK1 */ + if (Bank == FMC_NORSRAM_BANK1) + { + Device->BTCR[Bank] = 0x000030DBU; + } + /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ + else + { + Device->BTCR[Bank] = 0x000030D2U; + } + + Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; + ExDevice->BWTR[Bank] = 0x0FFFFFFFU; + + return HAL_OK; +} + +/** + * @brief Initialize the FMC_NORSRAM Timing according to the specified + * parameters in the FMC_NORSRAM_TimingTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpr; + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); + assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Set FMC_NORSRAM device timing parameters */ + Device->BTCR[Bank + 1U] = + (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | + (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | + (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) | + (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) | + ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) | + ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) | + Timing->AccessMode; + + /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ + if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) + { + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); + tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); + MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); + } + + return HAL_OK; +} + +/** + * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified + * parameters in the FMC_NORSRAM_TimingTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number + * @param ExtendedMode FMC Extended Mode + * This parameter can be one of the following values: + * @arg FMC_EXTENDED_MODE_DISABLE + * @arg FMC_EXTENDED_MODE_ENABLE + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode) +{ + /* Check the parameters */ + assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE) + { + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); +#if defined(FMC_BWTRx_BUSTURN) + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); +#endif /* FMC_BWTRx_BUSTURN */ + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ +#if defined(FMC_BWTRx_BUSTURN) + MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | + Timing->AccessMode | + ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos))); +#else /* FMC_BWTRx_BUSTURN */ + MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | + Timing->AccessMode)); +#endif /* FMC_BWTRx_BUSTURN */ + } + else + { + Device->BWTR[Bank] = 0x0FFFFFFFU; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_NORSRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC NORSRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically FMC_NORSRAM write operation. + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Enable write operation */ + SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_NORSRAM write operation. + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Disable write operation */ + CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions + * @brief NAND Controller functions + * + @verbatim + ============================================================================== + ##### How to use NAND device driver ##### + ============================================================================== + [..] + This driver contains a set of APIs to interface with the FMC NAND banks in order + to run the NAND external devices. + + (+) FMC NAND bank reset using the function FMC_NAND_DeInit() + (+) FMC NAND bank control configuration using the function FMC_NAND_Init() + (+) FMC NAND bank common space timing configuration using the function + FMC_NAND_CommonSpace_Timing_Init() + (+) FMC NAND bank attribute space timing configuration using the function + FMC_NAND_AttributeSpace_Timing_Init() + (+) FMC NAND bank enable/disable ECC correction feature using the functions + FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() + (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() + +@endverbatim + * @{ + */ + +/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC NAND interface + (+) De-initialize the FMC NAND interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FMC_NAND device according to the specified + * control parameters in the FMC_NAND_HandleTypeDef + * @param Device Pointer to NAND device instance + * @param Init Pointer to NAND Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Init->NandBank)); + assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); + assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); + assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); + assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); + assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); + + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | + FMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) | + ((Init->TARSetupTime) << FMC_PCR_TAR_Pos))); + + return HAL_OK; +} + +/** + * @brief Initializes the FMC_NAND Common space Timing according to the specified + * parameters in the FMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* NAND bank 3 registers configuration */ + Device->PMEM =(Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | + ((Timing->HoldSetupTime )<< FMC_PMEM_MEMHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); + + return HAL_OK; +} + +/** + * @brief Initializes the FMC_NAND Attribute space Timing according to the specified + * parameters in the FMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* NAND bank 3 registers configuration */ + Device->PATT =(Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); + + return HAL_OK; +} + +/** + * @brief DeInitializes the FMC_NAND device + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Disable the NAND Bank */ + __FMC_NAND_DISABLE(Device, Bank); + + /* De-initialize the NAND Bank */ + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* Set the FMC_NAND_BANK3 registers to their reset values */ + WRITE_REG(Device->PCR, 0x00000018U); + WRITE_REG(Device->SR, 0x00000040U); + WRITE_REG(Device->PMEM, 0xFCFCFCFCU); + WRITE_REG(Device->PATT, 0xFCFCFCFCU); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_NAND Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC NAND interface. + +@endverbatim + * @{ + */ + + +/** + * @brief Enables dynamically FMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Enable ECC feature */ + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + SET_BIT(Device->PCR, FMC_PCR_ECCEN); + + return HAL_OK; +} + + +/** + * @brief Disables dynamically FMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Disable ECC feature */ + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * @param ECCval Pointer to ECC value + * @param Bank NAND bank number + * @param Timeout Timeout wait value + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until FIFO is empty */ + while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* Get the ECCR register value */ + *ECCval = (uint32_t)Device->ECCR; + + return HAL_OK; +} + +/** + * @} + */ + + + +/** @defgroup FMC_LL_SDRAM + * @brief SDRAM Controller functions + * + @verbatim + ============================================================================== + ##### How to use SDRAM device driver ##### + ============================================================================== + [..] + This driver contains a set of APIs to interface with the FMC SDRAM banks in order + to run the SDRAM external devices. + + (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() + (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init() + (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init() + (+) FMC SDRAM bank enable/disable write operation using the functions + FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() + (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() + +@endverbatim + * @{ + */ + +/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC SDRAM interface + (+) De-initialize the FMC SDRAM interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FMC_SDRAM device according to the specified + * control parameters in the FMC_SDRAM_InitTypeDef + * @param Device Pointer to SDRAM device instance + * @param Init Pointer to SDRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); + assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); + assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); + assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); + assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); + assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); + assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); + assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); + assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); + + /* Set SDRAM bank configuration parameters */ + if (Init->SDBank == FMC_SDRAM_BANK1) + { + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], + SDCR_CLEAR_MASK, + (Init->ColumnBitsNumber | + Init->RowBitsNumber | + Init->MemoryDataWidth | + Init->InternalBankNumber | + Init->CASLatency | + Init->WriteProtection | + Init->SDClockPeriod | + Init->ReadBurst | + Init->ReadPipeDelay)); + } + else /* FMC_Bank2_SDRAM */ + { + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], + FMC_SDCRx_SDCLK | + FMC_SDCRx_RBURST | + FMC_SDCRx_RPIPE, + (Init->SDClockPeriod | + Init->ReadBurst | + Init->ReadPipeDelay)); + + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], + SDCR_CLEAR_MASK, + (Init->ColumnBitsNumber | + Init->RowBitsNumber | + Init->MemoryDataWidth | + Init->InternalBankNumber | + Init->CASLatency | + Init->WriteProtection)); + } + + return HAL_OK; +} + + +/** + * @brief Initializes the FMC_SDRAM device timing according to the specified + * parameters in the FMC_SDRAM_TimingTypeDef + * @param Device Pointer to SDRAM device instance + * @param Timing Pointer to SDRAM Timing structure + * @param Bank SDRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); + assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); + assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); + assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); + assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); + assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); + assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Set SDRAM device timing parameters */ + if (Bank == FMC_SDRAM_BANK1) + { + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], + SDTR_CLEAR_MASK, + (((Timing->LoadToActiveDelay) - 1U) | + (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) | + (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) | + (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) | + (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) | + (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos) | + (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos))); + } + else /* FMC_Bank2_SDRAM */ + { + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], + FMC_SDTRx_TRC | + FMC_SDTRx_TRP, + (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) | + (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos)); + + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], + SDTR_CLEAR_MASK, + (((Timing->LoadToActiveDelay) - 1U) | + (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) | + (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) | + (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) | + (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos))); + } + + return HAL_OK; +} + +/** + * @brief DeInitializes the FMC_SDRAM peripheral + * @param Device Pointer to SDRAM device instance + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* De-initialize the SDRAM device */ + Device->SDCR[Bank] = 0x000002D0U; + Device->SDTR[Bank] = 0x0FFFFFFFU; + Device->SDCMR = 0x00000000U; + Device->SDRTR = 0x00000000U; + Device->SDSR = 0x00000000U; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2 + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_SDRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC SDRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically FMC_SDRAM write protection. + * @param Device Pointer to SDRAM device instance + * @param Bank SDRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Enable write protection */ + SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_SDRAM write protection. + * @param hsdram FMC_SDRAM handle + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Disable write protection */ + CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); + + return HAL_OK; +} + +/** + * @brief Send Command to the FMC SDRAM bank + * @param Device Pointer to SDRAM device instance + * @param Command Pointer to SDRAM command structure + * @param Timing Pointer to SDRAM Timing structure + * @param Timeout Timeout wait value + * @retval HAL state + */ +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); + assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); + assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); + + /* Set command register */ + MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD), + ((Command->CommandMode) | (Command->CommandTarget) | + (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) | + ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos))); + /* Prevent unused argument(s) compilation warning */ + UNUSED(Timeout); + return HAL_OK; +} + +/** + * @brief Program the SDRAM Memory Refresh rate. + * @param Device Pointer to SDRAM device instance + * @param RefreshRate The SDRAM refresh rate value. + * @retval HAL state + */ +HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); + + /* Set the refresh rate in command register */ + MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos)); + + return HAL_OK; +} + +/** + * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. + * @param Device Pointer to SDRAM device instance + * @param AutoRefreshNumber Specifies the auto Refresh number. + * @retval None + */ +HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, + uint32_t AutoRefreshNumber) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); + + /* Set the Auto-refresh number in command register */ + MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); + + return HAL_OK; +} + +/** + * @brief Returns the indicated FMC SDRAM bank mode status. + * @param Device Pointer to SDRAM device instance + * @param Bank Defines the FMC SDRAM bank. This parameter can be + * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. + * @retval The FMC SDRAM bank mode status, could be on of the following values: + * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or + * FMC_SDRAM_POWER_DOWN_MODE. + */ +uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Get the corresponding bank mode */ + if (Bank == FMC_SDRAM_BANK1) + { + tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); + } + else + { + tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U); + } + + /* Return the mode status */ + return tmpreg; +} + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_NOR_MODULE_ENABLED */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_gpio.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_gpio.c new file mode 100644 index 00000000000..c486233f65f --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_gpio.c @@ -0,0 +1,299 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_gpio.c + * @author MCD Application Team + * @brief GPIO LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_gpio.h" +#include "stm32h7rsxx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || \ + defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || \ + defined (GPIOM) || defined (GPION) || defined (GPIOO) || defined (GPIOP) + +/** @addtogroup GPIO_LL + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + * range of the shift operator in following API : + * LL_GPIO_Init + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Private_Macros + * @{ + */ +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) + +#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ + ((__VALUE__) == LL_GPIO_MODE_ANALOG)) + +#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ + ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) + +#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ + ((__VALUE__) == LL_GPIO_PULL_UP) ||\ + ((__VALUE__) == LL_GPIO_PULL_DOWN)) + +#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ + ((__VALUE__) == LL_GPIO_AF_1 ) ||\ + ((__VALUE__) == LL_GPIO_AF_2 ) ||\ + ((__VALUE__) == LL_GPIO_AF_3 ) ||\ + ((__VALUE__) == LL_GPIO_AF_4 ) ||\ + ((__VALUE__) == LL_GPIO_AF_5 ) ||\ + ((__VALUE__) == LL_GPIO_AF_6 ) ||\ + ((__VALUE__) == LL_GPIO_AF_7 ) ||\ + ((__VALUE__) == LL_GPIO_AF_8 ) ||\ + ((__VALUE__) == LL_GPIO_AF_9 ) ||\ + ((__VALUE__) == LL_GPIO_AF_10 ) ||\ + ((__VALUE__) == LL_GPIO_AF_11 ) ||\ + ((__VALUE__) == LL_GPIO_AF_12 ) ||\ + ((__VALUE__) == LL_GPIO_AF_13 ) ||\ + ((__VALUE__) == LL_GPIO_AF_14 ) ||\ + ((__VALUE__) == LL_GPIO_AF_15 )) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize GPIO registers (Registers restored to their default values). + * @param GPIOx GPIO Port + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: Wrong GPIO Port + */ +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Force and Release reset on clock of GPIOx Port */ + if (GPIOx == GPIOA) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOA); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOA); + } + else if (GPIOx == GPIOB) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOB); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOB); + } + else if (GPIOx == GPIOC) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOC); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOC); + } + else if (GPIOx == GPIOD) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOD); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOD); + } + else if (GPIOx == GPIOE) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOE); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOE); + } + else if (GPIOx == GPIOF) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOF); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOF); + } + else if (GPIOx == GPIOG) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOG); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOG); + } + else if (GPIOx == GPIOH) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOH); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOH); + } + else if (GPIOx == GPIOM) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOM); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOM); + } + else if (GPIOx == GPION) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPION); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPION); + } + else if (GPIOx == GPIOO) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOO); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOO); + } + else if (GPIOx == GPIOP) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOP); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOP); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. + * @param GPIOx GPIO Port + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * that contains the configuration information for the specified GPIO peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content + * - ERROR: Not applicable + */ +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, const LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t pinpos; + uint32_t currentpin; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); + assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); + + /* ------------------------- Configure the port pins ---------------- */ + /* Initialize pinpos on first pin set */ + pinpos = POSITION_VAL(GPIO_InitStruct->Pin); + + /* Configure the port pins */ + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u) + { + /* Get current io position */ + currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos); + + if (currentpin != 0x00u) + { + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) + { + /* Check Speed mode parameters */ + assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); + + /* Speed mode configuration */ + LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType); + } + + /* Pull-up Pull down resistor configuration*/ + LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); + + if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) + { + /* Check Alternate parameter */ + assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); + + /* Alternate function configuration */ + if (currentpin < LL_GPIO_PIN_8) + { + LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + else + { + LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + } + + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); + } + pinpos++; + } + + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; + GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct->Alternate = LL_GPIO_AF_0; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || */ +/* defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || */ +/* defined (GPIOM) || defined (GPION) || defined (GPIOO) || defined (GPIOP) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_i2c.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_i2c.c new file mode 100644 index 00000000000..7dcc7376e19 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_i2c.c @@ -0,0 +1,232 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_i2c.c + * @author MCD Application Team + * @brief I2C LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_i2c.h" +#include "stm32h7rsxx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) || defined (I2C3) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_LL_Private_Macros + * @{ + */ + +#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \ + ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \ + ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \ + ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP)) + +#define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \ + ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE)) + +#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU) + +#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU) + +#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \ + ((__VALUE__) == LL_I2C_NACK)) + +#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \ + ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_LL_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the I2C registers to their default reset values. + * @param I2Cx I2C Instance. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: I2C registers are de-initialized + * - ERROR: I2C registers are not de-initialized + */ +ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx) +{ + ErrorStatus status = SUCCESS; + + /* Check the I2C Instance I2Cx */ + assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); + + if (I2Cx == I2C1) + { + /* Force reset of I2C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1); + + /* Release reset of I2C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1); + } + else if (I2Cx == I2C2) + { + /* Force reset of I2C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2); + + /* Release reset of I2C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2); + + } + else if (I2Cx == I2C3) + { + /* Force reset of I2C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3); + + /* Release reset of I2C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3); + } + else + { + status = ERROR; + } + + return status; +} + +/** + * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct. + * @param I2Cx I2C Instance. + * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: I2C registers are initialized + * - ERROR: Not applicable + */ +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct) +{ + /* Check the I2C Instance I2Cx */ + assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); + + /* Check the I2C parameters from I2C_InitStruct */ + assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode)); + assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter)); + assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter)); + assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1)); + assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge)); + assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize)); + + /* Disable the selected I2Cx Peripheral */ + LL_I2C_Disable(I2Cx); + + /*---------------------------- I2Cx CR1 Configuration ------------------------ + * Configure the analog and digital noise filters with parameters : + * - AnalogFilter: I2C_CR1_ANFOFF bit + * - DigitalFilter: I2C_CR1_DNF[3:0] bits + */ + LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter); + + /*---------------------------- I2Cx TIMINGR Configuration -------------------- + * Configure the SDA setup, hold time and the SCL high, low period with parameter : + * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0], + * I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits + */ + LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing); + + /* Enable the selected I2Cx Peripheral */ + LL_I2C_Enable(I2Cx); + + /*---------------------------- I2Cx OAR1 Configuration ----------------------- + * Disable, Configure and Enable I2Cx device own address 1 with parameters : + * - OwnAddress1: I2C_OAR1_OA1[9:0] bits + * - OwnAddrSize: I2C_OAR1_OA1MODE bit + */ + LL_I2C_DisableOwnAddress1(I2Cx); + LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize); + + /* OwnAdress1 == 0 is reserved for General Call address */ + if (I2C_InitStruct->OwnAddress1 != 0U) + { + LL_I2C_EnableOwnAddress1(I2Cx); + } + + /*---------------------------- I2Cx MODE Configuration ----------------------- + * Configure I2Cx peripheral mode with parameter : + * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits + */ + LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode); + + /*---------------------------- I2Cx CR2 Configuration ------------------------ + * Configure the ACKnowledge or Non ACKnowledge condition + * after the address receive match code or next received byte with parameter : + * - TypeAcknowledge: I2C_CR2_NACK bit + */ + LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_I2C_InitTypeDef field to default value. + * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure. + * @retval None + */ +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct) +{ + /* Set I2C_InitStruct fields to default values */ + I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C; + I2C_InitStruct->Timing = 0U; + I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE; + I2C_InitStruct->DigitalFilter = 0U; + I2C_InitStruct->OwnAddress1 = 0U; + I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK; + I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 || I2C3 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_i3c.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_i3c.c new file mode 100644 index 00000000000..de45c2fac91 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_i3c.c @@ -0,0 +1,197 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_i3c.c + * @author MCD Application Team + * @brief I3C LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_i3c.h" +#include "stm32h7rsxx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (I3C1) + +/** @defgroup I3C_LL I3C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I3C_LL_Private_Macros + * @{ + */ +#define IS_LL_I3C_SDAHOLDTIME_VALUE(VALUE) (((VALUE) == LL_I3C_SDA_HOLD_TIME_0_5) || \ + ((VALUE) == LL_I3C_SDA_HOLD_TIME_1_5)) + +#define IS_LL_I3C_WAITTIME_VALUE(VALUE) (((VALUE) == LL_I3C_OWN_ACTIVITY_STATE_0) || \ + ((VALUE) == LL_I3C_OWN_ACTIVITY_STATE_1) || \ + ((VALUE) == LL_I3C_OWN_ACTIVITY_STATE_2) || \ + ((VALUE) == LL_I3C_OWN_ACTIVITY_STATE_3)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I3C_LL_Exported_Functions + * @{ + */ + +/** @addtogroup I3C_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the I3C registers to their default reset values. + * @param I3Cx I3C Instance. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: I3C registers are de-initialized + * - ERROR: I3C registers are not de-initialized + */ +ErrorStatus LL_I3C_DeInit(const I3C_TypeDef *I3Cx) +{ + ErrorStatus status = SUCCESS; + + /* Check the I3C Instance I3Cx */ + assert_param(IS_I3C_ALL_INSTANCE(I3Cx)); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(I3Cx); + + /* Force reset of I3C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I3C1); + + /* Release reset of I3C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I3C1); + + return status; +} + +/** + * @brief Initialize the I3C registers according to the specified parameters in I3C_InitStruct. + * @param I3Cx I3C Instance. + * @param I3C_InitStruct pointer to a @ref LL_I3C_InitTypeDef structure. + * @param Mode I3C peripheral mode. + * This parameter can be a value of @ref I3C_LL_EC_MODE. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: I3C registers are initialized + * - ERROR: Not applicable + */ +ErrorStatus LL_I3C_Init(I3C_TypeDef *I3Cx, LL_I3C_InitTypeDef *I3C_InitStruct, uint32_t Mode) +{ + uint32_t waveform_value; + uint32_t timing_value; + + /* Check the I3C Instance I3Cx */ + assert_param(IS_I3C_ALL_INSTANCE(I3Cx)); + + /* Disable the selected I3C peripheral */ + LL_I3C_Disable(I3Cx); + + /* Check on the I3C mode: initialization depends on the mode */ + if (Mode == LL_I3C_MODE_CONTROLLER) + { + /* Check the parameters */ + assert_param(IS_LL_I3C_SDAHOLDTIME_VALUE(I3C_InitStruct->CtrlBusCharacteristic.SDAHoldTime)); + assert_param(IS_LL_I3C_WAITTIME_VALUE(I3C_InitStruct->CtrlBusCharacteristic.WaitTime)); + + /* Set Controller mode */ + LL_I3C_SetMode(I3Cx, LL_I3C_MODE_CONTROLLER); + + /*------------------ SCL signal waveform configuration : I3C timing register 0 (I3C_TIMINGR0) ------------------- */ + /* Set the controller SCL waveform */ + waveform_value = + ((uint32_t)(I3C_InitStruct->CtrlBusCharacteristic.SCLPPLowDuration) | + ((uint32_t)I3C_InitStruct->CtrlBusCharacteristic.SCLI3CHighDuration << I3C_TIMINGR0_SCLH_I3C_Pos) | + ((uint32_t)I3C_InitStruct->CtrlBusCharacteristic.SCLODLowDuration << I3C_TIMINGR0_SCLL_OD_Pos) | + ((uint32_t)I3C_InitStruct->CtrlBusCharacteristic.SCLI2CHighDuration << I3C_TIMINGR0_SCLH_I2C_Pos)); + + LL_I3C_ConfigClockWaveForm(I3Cx, waveform_value); + + /*------------------- Timing configuration : I3C timing register 1 (I3C_TIMINGR1) ------------------------------- */ + /* Set SDA hold time, activity state, bus free duration and bus available duration */ + timing_value = ((uint32_t)(I3C_InitStruct->CtrlBusCharacteristic.SDAHoldTime) | + (uint32_t)(I3C_InitStruct->CtrlBusCharacteristic.WaitTime) | + ((uint32_t)I3C_InitStruct->CtrlBusCharacteristic.BusFreeDuration << I3C_TIMINGR1_FREE_Pos) | + (uint32_t)(I3C_InitStruct->CtrlBusCharacteristic.BusIdleDuration)); + + LL_I3C_SetCtrlBusCharacteristic(I3Cx, timing_value); + } + else + { + /* Set target mode */ + LL_I3C_SetMode(I3Cx, LL_I3C_MODE_TARGET); + + /*------------------- Timing configuration : I3C timing register 1 (I3C_TIMINGR1) ------------------------------- */ + /* Set the number of kernel clocks cycles for the bus available condition time */ + LL_I3C_SetTgtBusCharacteristic(I3Cx, I3C_InitStruct->TgtBusCharacteristic.BusAvailableDuration); + } + + /* Enable the selected I3C peripheral */ + LL_I3C_Enable(I3Cx); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_I3C_InitTypeDef field to default value. + * @param I3C_InitStruct Pointer to a @ref LL_I3C_InitTypeDef structure. + * @retval None + */ +void LL_I3C_StructInit(LL_I3C_InitTypeDef *I3C_InitStruct) +{ + /* Set I3C_InitStruct fields to default values */ + I3C_InitStruct->CtrlBusCharacteristic.SDAHoldTime = LL_I3C_SDA_HOLD_TIME_0_5; + I3C_InitStruct->CtrlBusCharacteristic.WaitTime = LL_I3C_OWN_ACTIVITY_STATE_0; + I3C_InitStruct->CtrlBusCharacteristic.SCLPPLowDuration = 0U; + I3C_InitStruct->CtrlBusCharacteristic.SCLI3CHighDuration = 0U; + I3C_InitStruct->CtrlBusCharacteristic.SCLODLowDuration = 0U; + I3C_InitStruct->CtrlBusCharacteristic.SCLI2CHighDuration = 0U; + I3C_InitStruct->CtrlBusCharacteristic.BusFreeDuration = 0U; + I3C_InitStruct->CtrlBusCharacteristic.BusIdleDuration = 0U; + I3C_InitStruct->TgtBusCharacteristic.BusAvailableDuration = 0U; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I3C1 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_lptim.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_lptim.c new file mode 100644 index 00000000000..b22135cad76 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_lptim.c @@ -0,0 +1,206 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_lptim.c + * @author MCD Application Team + * @brief LPTIM LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_lptim.h" +#include "stm32h7rsxx_ll_bus.h" +#include "stm32h7rsxx_ll_rcc.h" + + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5) + +/** @addtogroup LPTIM_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup LPTIM_LL_Private_Macros + * @{ + */ +#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ + || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) + +#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) + +#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ + || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) + +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LPTIM_LL_Exported_Functions + * @{ + */ + +/** @addtogroup LPTIM_LL_EF_Init + * @{ + */ + +/** + * @brief Set LPTIMx registers to their reset values. + * @param LPTIMx LP Timer instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPTIMx registers are de-initialized + * - ERROR: invalid LPTIMx instance + */ +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx) +{ + ErrorStatus result = SUCCESS; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(LPTIMx)); + + if (LPTIMx == LPTIM1) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1); + } + else if (LPTIMx == LPTIM2) + { + LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM2); + LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM2); + } + else if (LPTIMx == LPTIM3) + { + LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM3); + LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM3); + } + else if (LPTIMx == LPTIM4) + { + LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM4); + LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM4); + } + else if (LPTIMx == LPTIM5) + { + LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM5); + LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM5); + } + else + { + result = ERROR; + } + + return result; +} + +/** + * @brief Set each fields of the LPTIM_InitStruct structure to its default + * value. + * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure + * @retval None + */ +void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct) +{ + /* Set the default configuration */ + LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL; + LPTIM_InitStruct->Prescaler = LL_LPTIM_PRESCALER_DIV1; + LPTIM_InitStruct->Waveform = LL_LPTIM_OUTPUT_WAVEFORM_PWM; +} + +/** + * @brief Configure the LPTIMx peripheral according to the specified parameters. + * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled. + * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable(). + * @param LPTIMx LP Timer Instance + * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPTIMx instance has been initialized + * - ERROR: LPTIMx instance hasn't been initialized + */ +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct) +{ + ErrorStatus result = SUCCESS; + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(LPTIMx)); + assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); + assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); + assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); + + /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled + (ENABLE bit is reset to 0). + */ + if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL) + { + result = ERROR; + } + else + { + /* Set CKSEL bitfield according to ClockSource value */ + /* Set PRESC bitfield according to Prescaler value */ + /* Set WAVE bitfield according to Waveform value */ + MODIFY_REG(LPTIMx->CFGR, + (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE), + LPTIM_InitStruct->ClockSource | \ + LPTIM_InitStruct->Prescaler | \ + LPTIM_InitStruct->Waveform); + } + + return result; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_lpuart.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_lpuart.c new file mode 100644 index 00000000000..22faa2ca551 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_lpuart.c @@ -0,0 +1,285 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_lpuart.c + * @author MCD Application Team + * @brief LPUART LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_lpuart.h" +#include "stm32h7rsxx_ll_rcc.h" +#include "stm32h7rsxx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (LPUART1) + +/** @addtogroup LPUART_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup LPUART_LL_Private_Constants + * @{ + */ + +/* Definition of default baudrate value used for LPUART initialisation */ +#define LPUART_DEFAULT_BAUDRATE (9600U) + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup LPUART_LL_Private_Macros + * @{ + */ + +/* Check of parameters for configuration of LPUART registers */ + +#define IS_LL_LPUART_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256)) + +/* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register */ +/* value : */ +/* - fck must be in the range [3 x baudrate, 4096 x baudrate] */ +/* - LPUART_BRR register value should be >= 0x300 */ +/* - LPUART_BRR register value should be <= 0xFFFFF (20 bits) */ +/* Baudrate specified by the user should belong to [8, 41600000].*/ +#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 41600000U) && ((__BAUDRATE__) >= 8U)) + +/* __VALUE__ BRR content must be greater than or equal to 0x300. */ +#define IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U) + +/* __VALUE__ BRR content must be lower than or equal to 0xFFFFF. */ +#define IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU) + +#define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX)) + +#define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \ + || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \ + || ((__VALUE__) == LL_LPUART_PARITY_ODD)) + +#define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \ + || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B)) + +#define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \ + || ((__VALUE__) == LL_LPUART_STOPBITS_2)) + +#define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LPUART_LL_Exported_Functions + * @{ + */ + +/** @addtogroup LPUART_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize LPUART registers (Registers restored to their default values). + * @param LPUARTx LPUART Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPUART registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_LPUART_INSTANCE(LPUARTx)); + + if (LPUARTx == LPUART1) + { + /* Force reset of LPUART peripheral */ + LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPUART1); + + /* Release reset of LPUART peripheral */ + LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPUART1); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize LPUART registers according to the specified + * parameters in LPUART_InitStruct. + * @note As some bits in LPUART configuration registers can only be written when + * the LPUART is disabled (USART_CR1_UE bit =0), + * LPUART Peripheral should be in disabled state prior calling this function. + * Otherwise, ERROR result will be returned. + * @note Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0). + * @param LPUARTx LPUART Instance + * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure + * that contains the configuration information for the specified LPUART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content + * - ERROR: Problem occurred during LPUART Registers initialization + */ +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t periphclk; + + /* Check the parameters */ + assert_param(IS_LPUART_INSTANCE(LPUARTx)); + assert_param(IS_LL_LPUART_PRESCALER(LPUART_InitStruct->PrescalerValue)); + assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate)); + assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth)); + assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits)); + assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity)); + assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection)); + assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl)); + + /* LPUART needs to be in disabled state, in order to be able to configure some bits in + CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */ + if (LL_LPUART_IsEnabled(LPUARTx) == 0U) + { + /*---------------------------- LPUART CR1 Configuration ----------------------- + * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters: + * - DataWidth: USART_CR1_M bits according to LPUART_InitStruct->DataWidth value + * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value + * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value + */ + MODIFY_REG(LPUARTx->CR1, + (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE), + (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection)); + + /*---------------------------- LPUART CR2 Configuration ----------------------- + * Configure LPUARTx CR2 (Stop bits) with parameters: + * - Stop Bits: USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value. + */ + LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits); + + /*---------------------------- LPUART CR3 Configuration ----------------------- + * Configure LPUARTx CR3 (Hardware Flow Control) with parameters: + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according + * to LPUART_InitStruct->HardwareFlowControl value. + */ + LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl); + + /*---------------------------- LPUART BRR Configuration ----------------------- + * Retrieve Clock frequency used for LPUART Peripheral + */ + periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE); + + /* Configure the LPUART Baud Rate : + - prescaler value is required + - valid baud rate value (different from 0) is required + - Peripheral clock as returned by RCC service, should be valid (different from 0). + */ + if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) + && (LPUART_InitStruct->BaudRate != 0U)) + { + status = SUCCESS; + LL_LPUART_SetBaudRate(LPUARTx, + periphclk, + LPUART_InitStruct->PrescalerValue, + LPUART_InitStruct->BaudRate); + + /* Check BRR is greater than or equal to 0x300 */ + assert_param(IS_LL_LPUART_BRR_MIN(LPUARTx->BRR)); + + /* Check BRR is lower than or equal to 0xFFFFF */ + assert_param(IS_LL_LPUART_BRR_MAX(LPUARTx->BRR)); + } + + /*---------------------------- LPUART PRESC Configuration ----------------------- + * Configure LPUARTx PRESC (Prescaler) with parameters: + * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value. + */ + LL_LPUART_SetPrescaler(LPUARTx, LPUART_InitStruct->PrescalerValue); + } + + return (status); +} + +/** + * @brief Set each @ref LL_LPUART_InitTypeDef field to default value. + * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) +{ + /* Set LPUART_InitStruct fields to default values */ + LPUART_InitStruct->PrescalerValue = LL_LPUART_PRESCALER_DIV1; + LPUART_InitStruct->BaudRate = LPUART_DEFAULT_BAUDRATE; + LPUART_InitStruct->DataWidth = LL_LPUART_DATAWIDTH_8B; + LPUART_InitStruct->StopBits = LL_LPUART_STOPBITS_1; + LPUART_InitStruct->Parity = LL_LPUART_PARITY_NONE ; + LPUART_InitStruct->TransferDirection = LL_LPUART_DIRECTION_TX_RX; + LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPUART1 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_pka.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_pka.c new file mode 100644 index 00000000000..36e99c0a056 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_pka.c @@ -0,0 +1,163 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_pka.c + * @author MCD Application Team + * @brief PKA LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_pka.h" +#include "stm32h7rsxx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(PKA) + +/** @addtogroup PKA_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PKA_LL_Private_Macros PKA Private Constants + * @{ + */ +#define IS_LL_PKA_MODE(__VALUE__) (((__VALUE__)== LL_PKA_MODE_MODULAR_EXP) ||\ + ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_EXP_FAST) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_EXP_PROTECT) ||\ + ((__VALUE__) == LL_PKA_MODE_ECC_MUL) ||\ + ((__VALUE__) == LL_PKA_MODE_ECC_COMPLETE_ADD) ||\ + ((__VALUE__) == LL_PKA_MODE_ECDSA_SIGNATURE) ||\ + ((__VALUE__) == LL_PKA_MODE_ECDSA_VERIFICATION) ||\ + ((__VALUE__) == LL_PKA_MODE_POINT_CHECK) ||\ + ((__VALUE__) == LL_PKA_MODE_RSA_CRT_EXP) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_INV) ||\ + ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_ADD) ||\ + ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_SUB) ||\ + ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_MUL) ||\ + ((__VALUE__) == LL_PKA_MODE_COMPARISON) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_REDUC) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_ADD) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_SUB) ||\ + ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_MUL) ||\ + ((__VALUE__) == LL_PKA_MODE_DOUBLE_BASE_LADDER) ||\ + ((__VALUE__) == LL_PKA_MODE_ECC_PROJECTIVE_AFF)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PKA_LL_Exported_Functions + * @{ + */ + +/** @addtogroup PKA_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize PKA registers (Registers restored to their default values). + * @param PKAx PKA Instance. + * @retval ErrorStatus + * - SUCCESS: PKA registers are de-initialized + * - ERROR: PKA registers are not de-initialized + */ +ErrorStatus LL_PKA_DeInit(const PKA_TypeDef *PKAx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_PKA_ALL_INSTANCE(PKAx)); + + if (PKAx == PKA) + { + /* Force PKA reset */ + LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA); + + /* Release PKA reset */ + LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize PKA registers according to the specified parameters in PKA_InitStruct. + * @param PKAx PKA Instance. + * @param PKA_InitStruct pointer to a @ref LL_PKA_InitTypeDef structure + * that contains the configuration information for the specified PKA peripheral. + * @retval ErrorStatus + * - SUCCESS: PKA registers are initialized according to PKA_InitStruct content + * - ERROR: Not applicable + */ +ErrorStatus LL_PKA_Init(PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct) +{ + assert_param(IS_PKA_ALL_INSTANCE(PKAx)); + assert_param(IS_LL_PKA_MODE(PKA_InitStruct->Mode)); + + LL_PKA_Config(PKAx, PKA_InitStruct->Mode); + + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_PKA_InitTypeDef field to default value. + * @param PKA_InitStruct pointer to a @ref LL_PKA_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct) +{ + /* Reset PKA init structure parameters values */ + PKA_InitStruct->Mode = LL_PKA_MODE_MODULAR_EXP; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (PKA) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_pwr.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_pwr.c new file mode 100644 index 00000000000..39be2758f2e --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_pwr.c @@ -0,0 +1,83 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_pwr.c + * @author MCD Application Team + * @brief PWR LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#if defined (USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_pwr.h" + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_LL_Exported_Functions + * @{ + */ + +/** @addtogroup PWR_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the PWR registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PWR registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_PWR_DeInit(void) +{ + /* Clear PWR low power flags */ + LL_PWR_ClearFlag_STOP_SB(); + + /* Clear PWR wake up flags */ + LL_PWR_ClearFlag_WU(); + + return SUCCESS; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (PWR) */ +/** + * @} + */ + +#endif /* defined (USE_FULL_LL_DRIVER) */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_rcc.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_rcc.c new file mode 100644 index 00000000000..475fa1f4769 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_rcc.c @@ -0,0 +1,1972 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_rcc.c + * @author MCD Application Team + * @brief RCC LL module driver. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_rcc.h" +#include "stm32h7rsxx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_LL_DRIVER */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @addtogroup RCC_LL + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup RCC_LL_Exported_Variables + * @{ + */ +const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_LL_Private_Macros + * @{ + */ +#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_ADC_CLKSOURCE) + +#define IS_LL_RCC_ADF1_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADF1_CLKSOURCE)) + +#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) + +#define IS_LL_RCC_CLKP_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CLKP_CLKSOURCE)) + +#define IS_LL_RCC_ETH1PHY_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ETH1PHY_CLKSOURCE)) + +#define IS_LL_RCC_ETHREF_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ETHREF_CLKSOURCE)) + +#define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE)) + +#define IS_LL_RCC_FMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FMC_CLKSOURCE)) + +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C23_CLKSOURCE)) + +#define IS_LL_RCC_I3C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I3C1_CLKSOURCE) + +#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_LPTIM23_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_LPTIM45_CLKSOURCE)) + +#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) + +#define IS_LL_RCC_PSSI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_PSSI_CLKSOURCE) + +#define IS_LL_RCC_RTC_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_RTC_CLKSOURCE) + +#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE)) + +#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SDMMC_CLKSOURCE) + +#define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SPI23_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SPI45_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE)) + +#define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX_CLKSOURCE)) + +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART234578_CLKSOURCE)) + +#define IS_LL_RCC_XSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_XSPI1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_XSPI2_CLKSOURCE)) + +#define IS_LL_RCC_USBPHYC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USBPHYC_CLKSOURCE)) + +#define IS_LL_RCC_OTGFS_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OTGFS_CLKSOURCE)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_LL_Private_Functions RCC Private functions + * @{ + */ +static uint32_t RCC_GetSystemClockFreq(void); +static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_GetPCLK5ClockFreq(uint32_t HCLK_Frequency); + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_LL_EF_Init + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL1, PLL2 and PLL3 OFF + * - AHB, APB Bus pre-scaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @note In case the FMC or XSPI clock protection have been set, it must be disabled + * prior to calling this API. + * @warning FLASH latency must be adjusted according to the targeted system clock + * frequency and voltage scaling. + * @retval None + */ +void LL_RCC_DeInit(void) +{ + /* Increasing the CPU frequency */ + if (FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait for HSI READY bit */ + while (LL_RCC_HSI_IsReady() == 0U) + {} + + /* Reset CFGR register to select HSI as system clock */ + CLEAR_REG(RCC->CFGR); + + /* Reset CSION, CSIKERON, HSEON, HSEEXT, HSI48ON, HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEEXT | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_CSION | RCC_CR_CSIKERON | \ + RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); + + /* Wait for PLL1 READY bit to be reset */ + while (LL_RCC_PLL1_IsReady() != 0U) + {} + + /* Wait for PLL2 READY bit to be reset */ + while (LL_RCC_PLL2_IsReady() != 0U) + {} + + /* Wait for PLL3 READY bit to be reset */ + while (LL_RCC_PLL3_IsReady() != 0U) + {} + + /* Reset CDCFGR register */ + CLEAR_REG(RCC->CDCFGR); + + /* Reset BMCFGR register */ + CLEAR_REG(RCC->BMCFGR); + + /* Reset APBCFGR register */ + CLEAR_REG(RCC->APBCFGR); + + /* Reset PLLCKSELR register to default value */ + LL_RCC_WriteReg(PLLCKSELR, \ + (32U << RCC_PLLCKSELR_DIVM1_Pos) | (32U << RCC_PLLCKSELR_DIVM2_Pos) | (32U << RCC_PLLCKSELR_DIVM3_Pos)); + + /* Reset PLLCFGR register to default value */ + LL_RCC_WriteReg(PLLCFGR, 0U); + + /* Reset PLL1DIVR1/PLL1DIVR2 registers to default value */ + LL_RCC_WriteReg(PLL1DIVR1, 0x01010280U); + LL_RCC_WriteReg(PLL1DIVR2, 0x00000101U); + + /* Reset PLL1FRACR register */ + CLEAR_REG(RCC->PLL1FRACR); + + /* Reset PLL2DIVR1/PLL2DIVR2 registers to default value */ + LL_RCC_WriteReg(PLL2DIVR1, 0x01010280U); + LL_RCC_WriteReg(PLL2DIVR2, 0x00000101U); + + /* Reset PLL2FRACR register */ + CLEAR_REG(RCC->PLL2FRACR); + + /* Reset PLL2DIVR1/PLL2DIVR2 registers to default value */ + LL_RCC_WriteReg(PLL2DIVR1, 0x01010280U); + LL_RCC_WriteReg(PLL2DIVR2, 0x00000101U); + + /* Reset PLL3FRACR register */ + CLEAR_REG(RCC->PLL3FRACR); + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIER); + + /* Clear all interrupts */ + SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | \ + RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLL1RDYC | RCC_CICR_PLL2RDYC | \ + RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC); + + /* Clear reset source flags */ + SET_BIT(RCC->RSR, RCC_RSR_RMVF); + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } +} + +/** + * @} + */ + +/** @addtogroup RCC_LL_EF_Get_Freq + * @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks. + * and different peripheral clocks available on the device. + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in header file (default value + * 64 MHz) divider by HSIDIV, but the real value may vary depending on + * on the variations in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in header file (default value + * 24 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * @note (***) CSI_VALUE is a constant defined in header file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note The result of this function could be incorrect when using fractional + * value for HSE crystal. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * @{ + */ + +/** + * @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB4 and APB5 buses clocks. + * @note Each time SYSCLK, HCLK, PCLK1, PCLK2, PCLK4 and/or PCLK5 clock changes, this function + * must be called to update structure fields. Otherwise, any + * configuration based on this function will be incorrect. + * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies + * @retval None + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) +{ + /* Get SYSCLK frequency */ + RCC_Clocks->SYSCLK_Frequency = LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()); + + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); + + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); + + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); + + /* PCLK4 clock frequency */ + RCC_Clocks->PCLK4_Frequency = RCC_GetPCLK4ClockFreq(RCC_Clocks->HCLK_Frequency); + + /* PCLK5 clock frequency */ + RCC_Clocks->PCLK5_Frequency = RCC_GetPCLK5ClockFreq(RCC_Clocks->HCLK_Frequency); +} + +/** + * @brief Return PLL1 clocks frequencies + * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready + * @retval None + */ +void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks) +{ + uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO; + uint32_t pllsource; + uint32_t m; + uint32_t n; + uint32_t fracn = 0U; + + /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) + SYSCLK = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_HSI_IsDividerReady() != 0U) + { + pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + } + break; + + case LL_RCC_PLLSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + pllinputfreq = CSI_VALUE; + } + break; + + case LL_RCC_PLLSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + pllinputfreq = HSE_VALUE; + } + break; + + case LL_RCC_PLLSOURCE_NONE: + default: + /* PLL clock disabled */ + break; + } + + PLL_Clocks->PLL_P_Frequency = 0U; + PLL_Clocks->PLL_Q_Frequency = 0U; + PLL_Clocks->PLL_R_Frequency = 0U; + PLL_Clocks->PLL_S_Frequency = 0U; + PLL_Clocks->PLL_T_Frequency = 0U; + + m = LL_RCC_PLL1_GetM(); + n = LL_RCC_PLL1_GetN(); + if (LL_RCC_PLL1FRACN_IsEnabled() != 0U) + { + fracn = LL_RCC_PLL1_GetFRACN(); + } + + if (m != 0U) + { + if (LL_RCC_PLL1P_IsEnabled() != 0U) + { + PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetP()); + } + + if (LL_RCC_PLL1Q_IsEnabled() != 0U) + { + PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetQ()); + } + + if (LL_RCC_PLL1R_IsEnabled() != 0U) + { + PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetR()); + } + + if (LL_RCC_PLL1S_IsEnabled() != 0U) + { + PLL_Clocks->PLL_S_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetS()); + } + } +} + +/** + * @brief Return PLL2 clocks frequencies + * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready + * @retval None + */ +void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks) +{ + uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO; + uint32_t pllsource; + uint32_t m; + uint32_t n; + uint32_t fracn = 0U; + + /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) + SYSCLK = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_HSI_IsDividerReady() != 0U) + { + pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + } + break; + + case LL_RCC_PLLSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + pllinputfreq = CSI_VALUE; + } + break; + + case LL_RCC_PLLSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + pllinputfreq = HSE_VALUE; + } + break; + + case LL_RCC_PLLSOURCE_NONE: + default: + /* PLL clock disabled */ + break; + } + + PLL_Clocks->PLL_P_Frequency = 0U; + PLL_Clocks->PLL_Q_Frequency = 0U; + PLL_Clocks->PLL_R_Frequency = 0U; + PLL_Clocks->PLL_S_Frequency = 0U; + PLL_Clocks->PLL_T_Frequency = 0U; + + m = LL_RCC_PLL2_GetM(); + n = LL_RCC_PLL2_GetN(); + if (LL_RCC_PLL2FRACN_IsEnabled() != 0U) + { + fracn = LL_RCC_PLL2_GetFRACN(); + } + + if (m != 0U) + { + if (LL_RCC_PLL2P_IsEnabled() != 0U) + { + PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetP()); + } + + if (LL_RCC_PLL2Q_IsEnabled() != 0U) + { + PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetQ()); + } + + if (LL_RCC_PLL2R_IsEnabled() != 0U) + { + PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetR()); + } + + if (LL_RCC_PLL2S_IsEnabled() != 0U) + { + PLL_Clocks->PLL_S_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetS()); + } + + if (LL_RCC_PLL2T_IsEnabled() != 0U) + { + PLL_Clocks->PLL_T_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetT()); + } + } +} + +/** + * @brief Return PLL3 clocks frequencies + * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready + * @retval None + */ +void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks) +{ + uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO; + uint32_t pllsource; + uint32_t m; + uint32_t n; + uint32_t fracn = 0U; + + /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) + SYSCLK = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_HSI_IsDividerReady() != 0U) + { + pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + } + break; + + case LL_RCC_PLLSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + pllinputfreq = CSI_VALUE; + } + break; + + case LL_RCC_PLLSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + pllinputfreq = HSE_VALUE; + } + break; + + case LL_RCC_PLLSOURCE_NONE: + default: + /* PLL clock disabled */ + break; + } + + PLL_Clocks->PLL_P_Frequency = 0U; + PLL_Clocks->PLL_Q_Frequency = 0U; + PLL_Clocks->PLL_R_Frequency = 0U; + PLL_Clocks->PLL_S_Frequency = 0U; + PLL_Clocks->PLL_T_Frequency = 0U; + + m = LL_RCC_PLL3_GetM(); + n = LL_RCC_PLL3_GetN(); + if (LL_RCC_PLL3FRACN_IsEnabled() != 0U) + { + fracn = LL_RCC_PLL3_GetFRACN(); + } + + if ((m != 0U) && (pllinputfreq != 0U)) + { + if (LL_RCC_PLL3P_IsEnabled() != 0U) + { + PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetP()); + } + + if (LL_RCC_PLL3Q_IsEnabled() != 0U) + { + PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetQ()); + } + + if (LL_RCC_PLL3R_IsEnabled() != 0U) + { + PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetR()); + } + + if (LL_RCC_PLL3S_IsEnabled() != 0U) + { + PLL_Clocks->PLL_S_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetS()); + } + } +} + +/** + * @brief Configure Spread Spectrum used for PLL1 + * @note These bits must be written before enabling PLL1 + * @note MODPER x INCSTEP shall not exceed 2^15-1 + * @rmtoll PLL1SSCGR MODPER LL_RCC_PLL1_ConfigSpreadSpectrum\n + * PLL1SSCGR INCSTEP LL_RCC_PLL1_ConfigSpreadSpectrum\n + * PLL1SSCGR SPREADSEL LL_RCC_PLL1_ConfigSpreadSpectrum\n + * PLL1SSCGR TPDFNDIS LL_RCC_PLL1_ConfigSpreadSpectrum\n + * PLL1SSCGR RPDFNDIS LL_RCC_PLL1_ConfigSpreadSpectrum + * @param pConfig Pointer to LL_PLL_SpreadSpectrumTypeDef structure + * @retval None + */ +void LL_RCC_PLL1_ConfigSpreadSpectrum(const LL_PLL_SpreadSpectrumTypeDef *pConfig) +{ + MODIFY_REG(RCC->PLL1SSCGR, \ + (RCC_PLL1SSCGR_MODPER | RCC_PLL1SSCGR_INCSTEP | RCC_PLL1SSCGR_SPREADSEL | \ + RCC_PLL1SSCGR_TPDFNDIS | RCC_PLL1SSCGR_RPDFNDIS), \ + (pConfig->ModulationPeriod | ((uint32_t)pConfig->IncrementStep << RCC_PLL1SSCGR_INCSTEP_Pos) | \ + pConfig->SpreadMode | pConfig->DitheringTPDFN | pConfig->DitheringRPDFN)); +} + +/** + * @brief Configure Spread Spectrum used for PLL2 + * @note These bits must be written before enabling PLL2 + * @rmtoll PLL2SSCGR MODPER LL_RCC_PLL2_ConfigSpreadSpectrum\n + * PLL2SSCGR INCSTEP LL_RCC_PLL2_ConfigSpreadSpectrum\n + * PLL2SSCGR SPREADSEL LL_RCC_PLL2_ConfigSpreadSpectrum\n + * PLL2SSCGR TPDFNDIS LL_RCC_PLL2_ConfigSpreadSpectrum\n + * PLL2SSCGR RPDFNDIS LL_RCC_PLL2_ConfigSpreadSpectrum + * @param pConfig Pointer to LL_PLL_SpreadSpectrumTypeDef structure + * @retval None + */ +void LL_RCC_PLL2_ConfigSpreadSpectrum(const LL_PLL_SpreadSpectrumTypeDef *pConfig) +{ + MODIFY_REG(RCC->PLL2SSCGR, \ + (RCC_PLL2SSCGR_MODPER | RCC_PLL2SSCGR_INCSTEP | RCC_PLL2SSCGR_SPREADSEL | \ + RCC_PLL2SSCGR_TPDFNDIS | RCC_PLL2SSCGR_RPDFNDIS), \ + (pConfig->ModulationPeriod | ((uint32_t)pConfig->IncrementStep << RCC_PLL2SSCGR_INCSTEP_Pos) | \ + pConfig->SpreadMode | pConfig->DitheringTPDFN | pConfig->DitheringRPDFN)); +} + +/** + * @brief Configure Spread Spectrum used for PLL3 + * @note These bits must be written before enabling PLL3 + * @rmtoll PLL3SSCGR MODPER LL_RCC_PLL3_ConfigSpreadSpectrum\n + * PLL3SSCGR INCSTEP LL_RCC_PLL3_ConfigSpreadSpectrum\n + * PLL3SSCGR SPREADSEL LL_RCC_PLL3_ConfigSpreadSpectrum\n + * PLL3SSCGR TPDFNDIS LL_RCC_PLL3_ConfigSpreadSpectrum\n + * PLL3SSCGR RPDFNDIS LL_RCC_PLL3_ConfigSpreadSpectrum + * @param pConfig Pointer to LL_PLL_SpreadSpectrumTypeDef structure + * @retval None + */ +void LL_RCC_PLL3_ConfigSpreadSpectrum(const LL_PLL_SpreadSpectrumTypeDef *pConfig) +{ + MODIFY_REG(RCC->PLL3SSCGR, \ + (RCC_PLL3SSCGR_MODPER | RCC_PLL3SSCGR_INCSTEP | RCC_PLL3SSCGR_SPREADSEL | \ + RCC_PLL3SSCGR_TPDFNDIS | RCC_PLL3SSCGR_RPDFNDIS), \ + (pConfig->ModulationPeriod | ((uint32_t)pConfig->IncrementStep << RCC_PLL3SSCGR_INCSTEP_Pos) | \ + pConfig->SpreadMode | pConfig->DitheringTPDFN | pConfig->DitheringRPDFN)); +} + + +/** + * @brief Return USARTx clock frequency + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART234578_CLKSOURCE + * @retval USART clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) +{ + uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); + + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART1_CLKSOURCE_PCLK2: + usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_USART234578_CLKSOURCE_PCLK1: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_USART1_CLKSOURCE_PLL2Q: + case LL_RCC_USART234578_CLKSOURCE_PLL2Q: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + usart_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_USART1_CLKSOURCE_PLL3Q: + case LL_RCC_USART234578_CLKSOURCE_PLL3Q: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + usart_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_USART1_CLKSOURCE_HSI: + case LL_RCC_USART234578_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_HSI_IsDividerReady() != 0U) + { + usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + } + break; + + case LL_RCC_USART1_CLKSOURCE_CSI: + case LL_RCC_USART234578_CLKSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + usart_frequency = CSI_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_LSE: + case LL_RCC_USART234578_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + usart_frequency = LSE_VALUE; + } + break; + + default: + /* Kernel clock disabled */ + break; + } + + return usart_frequency; +} + +/** + * @brief Return UARTx clock frequency + * @param UARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART234578_CLKSOURCE + * @retval USART clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) +{ + uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_USART_CLKSOURCE(UARTxSource)); + + switch (LL_RCC_GetUSARTClockSource(UARTxSource)) + { + case LL_RCC_USART234578_CLKSOURCE_PCLK1: + uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_USART234578_CLKSOURCE_PLL2Q: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + uart_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_USART234578_CLKSOURCE_PLL3Q: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + uart_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_USART234578_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_HSI_IsDividerReady() != 0U) + { + uart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + } + break; + + case LL_RCC_USART234578_CLKSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + uart_frequency = CSI_VALUE; + } + break; + + case LL_RCC_USART234578_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + uart_frequency = LSE_VALUE; + } + break; + + default: + /* Kernel clock disabled */ + break; + } + + return uart_frequency; +} + +/** + * @brief Return LPUART clock frequency + * @param LPUARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval LPUART clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) +{ + uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource)); + + switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) + { + case LL_RCC_LPUART1_CLKSOURCE_PCLK4: + lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_LPUART1_CLKSOURCE_PLL2Q: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + lpuart_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_PLL3Q: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + lpuart_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_HSI_IsDividerReady() != 0U) + { + lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + lpuart_frequency = CSI_VALUE; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + lpuart_frequency = LSE_VALUE; + } + break; + + default: + /* Kernel clock disabled */ + break; + } + + return lpuart_frequency; +} + +/** + * @brief Return I2Cx clock frequency + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C23_CLKSOURCE + * @retval I2C clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) +{ + uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); + + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C1_CLKSOURCE_PCLK1: + case LL_RCC_I2C23_CLKSOURCE_PCLK1: + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_I2C1_CLKSOURCE_PLL3R: + case LL_RCC_I2C23_CLKSOURCE_PLL3R: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + i2c_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_I2C1_CLKSOURCE_HSI: + case LL_RCC_I2C23_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_HSI_IsDividerReady() != 0U) + { + i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + } + break; + + case LL_RCC_I2C1_CLKSOURCE_CSI: + case LL_RCC_I2C23_CLKSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + i2c_frequency = CSI_VALUE; + } + break; + + default: + /* Nothing to do */ + break; + } + + return i2c_frequency; +} + +/** + * @brief Return I3Cx clock frequency + * @param I3CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I3C1_CLKSOURCE + * @retval I3C clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource) +{ + uint32_t i3c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_I3C_CLKSOURCE(I3CxSource)); + + switch (LL_RCC_GetI3CClockSource(I3CxSource)) + { + case LL_RCC_I3C1_CLKSOURCE_PCLK1: + i3c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_I3C1_CLKSOURCE_PLL3R: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + i3c_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_I3C1_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_HSI_IsDividerReady() != 0U) + { + i3c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + } + break; + + case LL_RCC_I3C1_CLKSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + i3c_frequency = CSI_VALUE; + } + break; + + default: + /* Nothing to do */ + break; + } + + return i3c_frequency; +} + +/** + * @brief Return LPTIMx clock frequency + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM23_CLKSOURCE + * @arg @ref LL_RCC_LPTIM45_CLKSOURCE + * @retval LPTIM clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) +{ + uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource)); + + switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) + { + case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: + lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_LPTIM23_CLKSOURCE_PCLK4: + case LL_RCC_LPTIM45_CLKSOURCE_PCLK4: + lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_LPTIM1_CLKSOURCE_PLL2P: + case LL_RCC_LPTIM23_CLKSOURCE_PLL2P: + case LL_RCC_LPTIM45_CLKSOURCE_PLL2P: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + lptim_frequency = PLL_Clocks.PLL_P_Frequency; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_PLL3R: + case LL_RCC_LPTIM23_CLKSOURCE_PLL3R: + case LL_RCC_LPTIM45_CLKSOURCE_PLL3R: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + lptim_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_LSE: + case LL_RCC_LPTIM23_CLKSOURCE_LSE: + case LL_RCC_LPTIM45_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + lptim_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_LSI: + case LL_RCC_LPTIM23_CLKSOURCE_LSI: + case LL_RCC_LPTIM45_CLKSOURCE_LSI: + if (LL_RCC_LSI_IsReady() != 0U) + { + lptim_frequency = LSI_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_CLKP: + case LL_RCC_LPTIM23_CLKSOURCE_CLKP: + case LL_RCC_LPTIM45_CLKSOURCE_CLKP: + lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + default: + /* Kernel clock disabled */ + break; + } + + return lptim_frequency; +} + +/** + * @brief Return SAIx clock frequency + * @param SAIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @arg @ref LL_RCC_SAI2_CLKSOURCE + * @retval SAI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) +{ + uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource)); + + switch (LL_RCC_GetSAIClockSource(SAIxSource)) + { + case LL_RCC_SAI1_CLKSOURCE_PLL1Q: + case LL_RCC_SAI2_CLKSOURCE_PLL1Q: + if (LL_RCC_PLL1_IsReady() != 0U) + { + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + sai_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_SAI1_CLKSOURCE_PLL2P: + case LL_RCC_SAI2_CLKSOURCE_PLL2P: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + sai_frequency = PLL_Clocks.PLL_P_Frequency; + } + break; + + case LL_RCC_SAI1_CLKSOURCE_PLL3P: + case LL_RCC_SAI2_CLKSOURCE_PLL3P: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + sai_frequency = PLL_Clocks.PLL_P_Frequency; + } + break; + + case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN: + case LL_RCC_SAI2_CLKSOURCE_I2S_CKIN: + sai_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_SAI1_CLKSOURCE_CLKP: + case LL_RCC_SAI2_CLKSOURCE_CLKP: + sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + default: + /* Kernel clock disabled */ + break; + } + + return sai_frequency; +} + +/** + * @brief Return ADC clock frequency + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval ADC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) +{ + uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource)); + + switch (LL_RCC_GetADCClockSource(ADCxSource)) + { + case LL_RCC_ADC_CLKSOURCE_PLL2P: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + adc_frequency = PLL_Clocks.PLL_P_Frequency; + } + break; + + case LL_RCC_ADC_CLKSOURCE_PLL3R: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + adc_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_ADC_CLKSOURCE_CLKP: + adc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + default: + /* Kernel clock disabled */ + break; + } + + return adc_frequency; +} + +/** + * @brief Return SDMMC clock frequency + * @param SDMMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC_CLKSOURCE + * @retval SDMMC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) +{ + uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource)); + + switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource)) + { + case LL_RCC_SDMMC_CLKSOURCE_PLL2S: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + sdmmc_frequency = PLL_Clocks.PLL_S_Frequency; + } + break; + + case LL_RCC_SDMMC_CLKSOURCE_PLL2T: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + sdmmc_frequency = PLL_Clocks.PLL_T_Frequency; + } + break; + + default: + /* Nothing to do */ + break; + } + + return sdmmc_frequency; +} + +/** + * @brief Return CEC clock frequency + * @param CECxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval CEC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) +{ + uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); + + switch (LL_RCC_GetCECClockSource(CECxSource)) + { + case LL_RCC_CEC_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + cec_frequency = LSE_VALUE; + } + break; + + case LL_RCC_CEC_CLKSOURCE_LSI: + if (LL_RCC_LSI_IsReady() != 0U) + { + cec_frequency = LSI_VALUE; + } + break; + + case LL_RCC_CEC_CLKSOURCE_CSI_DIV_122: + if (LL_RCC_CSI_IsReady() != 0U) + { + cec_frequency = CSI_VALUE / 122U; + } + break; + + default: + /* Kernel clock disabled */ + break; + } + + return cec_frequency; +} + +/** + * @brief Return PSSI clock frequency + * @param PSSIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PSSI_CLKSOURCE + * @retval PSSI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetPSSIClockFreq(uint32_t PSSIxSource) +{ + uint32_t pssi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef pll_clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_PSSI_CLKSOURCE(PSSIxSource)); + + switch (LL_RCC_GetPSSIClockSource(PSSIxSource)) + { + case LL_RCC_PSSI_CLKSOURCE_PLL3R: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&pll_clocks); + pssi_frequency = pll_clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_PSSI_CLKSOURCE_CLKP: + pssi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + default: + /* Nothing to do */ + break; + } + + return pssi_frequency; +} + + +/** + * @brief Return USBPHYC clock frequency + * @param USBPHYCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USBPHYC_CLKSOURCE + * @retval USBPHYC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled + */ +uint32_t LL_RCC_GetUSBPHYCClockFreq(uint32_t USBPHYCxSource) +{ + uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_USBPHYC_CLKSOURCE(USBPHYCxSource)); + + switch (LL_RCC_GetUSBPHYCClockSource(USBPHYCxSource)) + { + case LL_RCC_USBPHYC_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + usb_frequency = HSE_VALUE; + } + break; + + case LL_RCC_USBPHYC_CLKSOURCE_HSE_DIV_2: + if (LL_RCC_HSE_IsReady() != 0U) + { + usb_frequency = (HSE_VALUE / 2U); + } + break; + + case LL_RCC_USBPHYC_CLKSOURCE_PLL3Q: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + usb_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_USBPHYC_CLKSOURCE_DISABLE: + default: + /* Nothing to do */ + break; + } + + return usb_frequency; +} + +/** + * @brief Return ADF clock frequency + * @param ADFxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADF1_CLKSOURCE + * @retval ADF clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetADFClockFreq(uint32_t ADFxSource) +{ + uint32_t adf_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_ADF1_CLKSOURCE(ADFxSource)); + + switch (LL_RCC_GetADFClockSource(ADFxSource)) + { + case LL_RCC_ADF1_CLKSOURCE_HCLK: + adf_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())); + break; + + case LL_RCC_ADF1_CLKSOURCE_PLL2P: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + adf_frequency = PLL_Clocks.PLL_P_Frequency; + } + break; + + case LL_RCC_ADF1_CLKSOURCE_PLL3P: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + adf_frequency = PLL_Clocks.PLL_P_Frequency; + } + break; + + case LL_RCC_ADF1_CLKSOURCE_I2S_CKIN: + adf_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_ADF1_CLKSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + adf_frequency = CSI_VALUE; + } + break; + + case LL_RCC_ADF1_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_HSI_IsDividerReady() != 0U) + { + adf_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + } + break; + + default: + /* Nothing to do */ + break; + } + + return adf_frequency; +} + +/** + * @brief Return SPDIFRX clock frequency + * @param SPDIFRXxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE + * @retval SPDIF clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource) +{ + uint32_t spdif_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource)); + + switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource)) + { + case LL_RCC_SPDIFRX_CLKSOURCE_PLL1Q: + if (LL_RCC_PLL1_IsReady() != 0U) + { + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + spdif_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_SPDIFRX_CLKSOURCE_PLL2R: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + spdif_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_SPDIFRX_CLKSOURCE_PLL3R: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + spdif_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_SPDIFRX_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_HSI_IsDividerReady() != 0U) + { + spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + } + break; + + default: + /* Nothing to do */ + break; + } + + return spdif_frequency; +} + +/** + * @brief Return SPIx clock frequency + * @param SPIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE + * @arg @ref LL_RCC_SPI23_CLKSOURCE + * @arg @ref LL_RCC_SPI45_CLKSOURCE + * @arg @ref LL_RCC_SPI6_CLKSOURCE + * @retval SPI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource) +{ + uint32_t spi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource)); + + switch (LL_RCC_GetSPIClockSource(SPIxSource)) + { + case LL_RCC_SPI1_CLKSOURCE_PLL1Q: + case LL_RCC_SPI23_CLKSOURCE_PLL1Q: + if (LL_RCC_PLL1_IsReady() != 0U) + { + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + spi_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_SPI1_CLKSOURCE_PLL2P: + case LL_RCC_SPI23_CLKSOURCE_PLL2P: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + spi_frequency = PLL_Clocks.PLL_P_Frequency; + } + break; + + case LL_RCC_SPI1_CLKSOURCE_PLL3P: + case LL_RCC_SPI23_CLKSOURCE_PLL3P: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + spi_frequency = PLL_Clocks.PLL_P_Frequency; + } + break; + + case LL_RCC_SPI1_CLKSOURCE_I2S_CKIN: + case LL_RCC_SPI23_CLKSOURCE_I2S_CKIN: + spi_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_SPI1_CLKSOURCE_CLKP: + case LL_RCC_SPI23_CLKSOURCE_CLKP: + spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_SPI45_CLKSOURCE_PCLK2: + spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_SPI6_CLKSOURCE_PCLK4: + spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_SPI45_CLKSOURCE_PLL2Q: + case LL_RCC_SPI6_CLKSOURCE_PLL2Q: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + spi_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_SPI45_CLKSOURCE_PLL3Q: + case LL_RCC_SPI6_CLKSOURCE_PLL3Q: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + spi_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_SPI45_CLKSOURCE_HSI: + case LL_RCC_SPI6_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_HSI_IsDividerReady() != 0U) + { + spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + } + break; + + case LL_RCC_SPI45_CLKSOURCE_CSI: + case LL_RCC_SPI6_CLKSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + spi_frequency = CSI_VALUE; + } + break; + + case LL_RCC_SPI45_CLKSOURCE_HSE: + case LL_RCC_SPI6_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + spi_frequency = HSE_VALUE; + } + break; + + default: + /* Kernel clock disabled */ + break; + } + + return spi_frequency; +} + +/** + * @brief Return ETH clock frequency + * @param ETHxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH1PHY_CLKSOURCE + * @retval ETH clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled + */ +uint32_t LL_RCC_GetETHPHYClockFreq(uint32_t ETHxSource) +{ + uint32_t eth_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_ETH1PHY_CLKSOURCE(ETHxSource)); + + switch (LL_RCC_GetETHPHYClockSource(ETHxSource)) + { + case LL_RCC_ETH1PHY_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + eth_frequency = HSE_VALUE; + } + break; + + case LL_RCC_ETH1PHY_CLKSOURCE_PLL3S: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + eth_frequency = PLL_Clocks.PLL_S_Frequency; + } + break; + + default: + /* Nothing to do */ + break; + } + + return eth_frequency; +} + + +/** + * @brief Return FDCAN clock frequency + * @param FDCANxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE + * @retval FDCAN clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource) +{ + uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource)); + + switch (LL_RCC_GetFDCANClockSource(FDCANxSource)) + { + case LL_RCC_FDCAN_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + fdcan_frequency = HSE_VALUE; + } + break; + + case LL_RCC_FDCAN_CLKSOURCE_PLL1Q: + if (LL_RCC_PLL1_IsReady() != 0U) + { + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + fdcan_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_FDCAN_CLKSOURCE_PLL2Q: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + fdcan_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + default: + /* Kernel clock disabled */ + break; + } + + return fdcan_frequency; +} + +/** + * @brief Return FMC clock frequency + * @param FMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE + * @retval FMC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource) +{ + uint32_t fmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + uint32_t clksource; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_FMC_CLKSOURCE(FMCxSource)); + + if (LL_RCC_GetFMCSwitchPosition() == LL_RCC_SWP_FMC_HCLK_DIV4) + { + clksource = LL_RCC_FMC_CLKSOURCE_HCLK_DIV4; + } + else + { + clksource = LL_RCC_GetFMCClockSource(FMCxSource); + } + + switch (clksource) + { + case LL_RCC_FMC_CLKSOURCE_HCLK: + fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())); + break; + + case LL_RCC_FMC_CLKSOURCE_PLL1Q: + if (LL_RCC_PLL1_IsReady() != 0U) + { + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + fmc_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_FMC_CLKSOURCE_PLL2R: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + fmc_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_FMC_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_HSI_IsDividerReady() != 0U) + { + fmc_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + } + break; + + case LL_RCC_FMC_CLKSOURCE_HCLK_DIV4: + fmc_frequency = (RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())) / 4U); + break; + + default: + /* Nothing to do */ + break; + } + + return fmc_frequency; +} + +/** + * @brief Return XSPI clock frequency + * @param XSPIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_XSPI1_CLKSOURCE + * @arg @ref LL_RCC_XSPI2_CLKSOURCE + * @retval XSPI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ + +uint32_t LL_RCC_GetXSPIClockFreq(uint32_t XSPIxSource) +{ + uint32_t xspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + uint32_t clksource; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_XSPI_CLKSOURCE(XSPIxSource)); + + clksource = LL_RCC_GetXSPIClockSource(XSPIxSource); + + /* Update clock source depending on the XSPI clock switch position */ + switch (XSPIxSource) + { + case LL_RCC_XSPI1_CLKSOURCE: + if (LL_RCC_GetXSPI1SwitchPosition() == LL_RCC_SWP_XSPI1_HCLK_DIV4) + { + clksource = LL_RCC_XSPI1_CLKSOURCE_HCLK_DIV4; + } + break; + case LL_RCC_XSPI2_CLKSOURCE: + if (LL_RCC_GetXSPI2SwitchPosition() == LL_RCC_SWP_XSPI2_HCLK_DIV4) + { + clksource = LL_RCC_XSPI2_CLKSOURCE_HCLK_DIV4; + } + break; + default: + /* Do nothing */ + break; + } + + switch (clksource) + { + case LL_RCC_XSPI1_CLKSOURCE_HCLK: + case LL_RCC_XSPI2_CLKSOURCE_HCLK: + xspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())); + break; + + case LL_RCC_XSPI1_CLKSOURCE_PLL2S: + case LL_RCC_XSPI2_CLKSOURCE_PLL2S: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + xspi_frequency = PLL_Clocks.PLL_S_Frequency; + } + break; + + case LL_RCC_XSPI1_CLKSOURCE_PLL2T: + case LL_RCC_XSPI2_CLKSOURCE_PLL2T: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + xspi_frequency = PLL_Clocks.PLL_T_Frequency; + } + break; + + case LL_RCC_XSPI1_CLKSOURCE_HCLK_DIV4: + case LL_RCC_XSPI2_CLKSOURCE_HCLK_DIV4: + xspi_frequency = (RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())) / 4U); + break; + + default: + /* Nothing to do */ + break; + } + + return xspi_frequency; +} + +/** + * @brief Return CLKP clock frequency + * @param CLKPxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE + * @retval CLKP clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource) +{ + uint32_t clkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_CLKP_CLKSOURCE(CLKPxSource)); + + switch (LL_RCC_GetCLKPClockSource(CLKPxSource)) + { + case LL_RCC_CLKP_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_HSI_IsDividerReady() != 0U) + { + clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + } + break; + + case LL_RCC_CLKP_CLKSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + clkp_frequency = CSI_VALUE; + } + break; + + case LL_RCC_CLKP_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + clkp_frequency = HSE_VALUE; + } + break; + + default: + /* CLKP clock disabled */ + break; + } + + return clkp_frequency; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_LL_Private_Functions + * @{ + */ + +/** + * @brief Return SYSTEM clock frequency + * @retval SYSTEM clock frequency (in Hz) + */ +static uint32_t RCC_GetSystemClockFreq(void) +{ + uint32_t frequency = 0U; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (LL_RCC_GetSysClkSource()) + { + /* No check on Ready: Won't be selected by hardware if not */ + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: + frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_CSI: + frequency = CSI_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: + frequency = HSE_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1: + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + frequency = PLL_Clocks.PLL_P_Frequency; + break; + + default: + /* Nothing to do */ + break; + } + + return frequency; +} + +/** + * @brief Return HCLK clock frequency + * @param SYSCLK_Frequency SYSCLK clock frequency + * @retval HCLK clock frequency (in Hz) + */ +static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +{ + /* HCLK clock frequency */ + return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); +} + +/** + * @brief Return PCLK1 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK1 clock frequency (in Hz) + */ +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK1 clock frequency */ + return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); +} + +/** + * @brief Return PCLK2 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK2 clock frequency (in Hz) + */ +static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK2 clock frequency */ + return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); +} + +/** + * @brief Return PCLK4 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK4 clock frequency (in Hz) + */ +static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK4 clock frequency */ + return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler()); +} + +/** + * @brief Return PCLK5 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK5 clock frequency (in Hz) + */ +static uint32_t RCC_GetPCLK5ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK5 clock frequency */ + return LL_RCC_CALC_PCLK5_FREQ(HCLK_Frequency, LL_RCC_GetAPB5Prescaler()); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_rng.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_rng.c new file mode 100644 index 00000000000..2e26527b2ab --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_rng.c @@ -0,0 +1,158 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_rng.c + * @author MCD Application Team + * @brief RNG LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_rng.h" +#include "stm32h7rsxx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (RNG) + +/** @addtogroup RNG_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RNG_LL_Private_Macros RNG Private Macros + * @{ + */ +#define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \ + ((__MODE__) == LL_RNG_CED_DISABLE)) + +#define IS_LL_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) ((__CLOCK_DIV__) <=0x0Fu) + + +#define IS_LL_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == LL_RNG_NIST_COMPLIANT) || \ + ((__NIST_COMPLIANCE__) == LL_RNG_NOTNIST_COMPLIANT)) + +#define IS_LL_RNG_CONFIG1 (__CONFIG1__) ((__CONFIG1__) <= 0x3FUL) + +#define IS_LL_RNG_CONFIG2 (__CONFIG2__) ((__CONFIG2__) <= 0x07UL) + +#define IS_LL_RNG_CONFIG3 (__CONFIG3__) ((__CONFIG3__) <= 0xFUL) +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RNG_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RNG_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize RNG registers (Registers restored to their default values). + * @param RNGx RNG Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RNG registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_RNG_ALL_INSTANCE(RNGx)); + if (RNGx == RNG) + { + /* Enable RNG reset state */ + LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG); + + /* Release RNG from reset state */ + LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG); + } + else + { + status = ERROR; + } + + return status; +} + +/** + * @brief Initialize RNG registers according to the specified parameters in RNG_InitStruct. + * @param RNGx RNG Instance + * @param RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure + * that contains the configuration information for the specified RNG peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content + * - ERROR: not applicable + */ +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_RNG_ALL_INSTANCE(RNGx)); + assert_param(IS_LL_RNG_CED(RNG_InitStruct->ClockErrorDetection)); + + /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, RNG_InitStruct->ClockErrorDetection | RNG_CR_CONDRST); + /* Writing bits CONDRST=0*/ + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); + + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_RNG_InitTypeDef field to default value. + * @param RNG_InitStruct pointer to a @ref LL_RNG_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct) +{ + /* Set RNG_InitStruct fields to default values */ + RNG_InitStruct->ClockErrorDetection = LL_RNG_CED_ENABLE; + +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RNG */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_rtc.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_rtc.c new file mode 100644 index 00000000000..73ab05af7d1 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_rtc.c @@ -0,0 +1,850 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_rtc.c + * @author MCD Application Team + * @brief RTC LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_rtc.h" +#include "stm32h7rsxx_ll_cortex.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @addtogroup RTC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RTC_LL_Private_Constants + * @{ + */ +/* Default values used for prescaler */ +#define RTC_ASYNCH_PRESC_DEFAULT ((uint32_t) 0x0000007FU) +#define RTC_SYNCH_PRESC_DEFAULT ((uint32_t) 0x000000FFU) + +/* Values used for timeout */ +#define RTC_INITMODE_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */ +#define RTC_SYNCHRO_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RTC_LL_Private_Macros + * @{ + */ + +#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \ + || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM)) + +#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU) + +#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU) + +#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \ + || ((__VALUE__) == LL_RTC_FORMAT_BCD)) + +#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \ + || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM)) + +#define IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U)) +#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U) +#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U) +#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U) + +#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY)) + +#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U)) + +#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U)) + +#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) + +#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL)) + +#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL)) + + +#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \ + ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY)) + +#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \ + ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY)) + + +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RTC_LL_EF_Init + * @{ + */ + +/** + * @brief De-Initializes the RTC registers to their default reset values. + * @note This function does not reset the RTC Clock source and RTC Backup Data + * registers. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are de-initialized + * - ERROR: RTC registers are not de-initialized + */ +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) +{ + ErrorStatus status = ERROR; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + WRITE_REG(RTCx->TR, 0U); + WRITE_REG(RTCx->DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + WRITE_REG(RTCx->CR, 0U); + WRITE_REG(RTCx->WUTR, RTC_WUTR_WUT); + WRITE_REG(RTCx->PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); + WRITE_REG(RTCx->ALRMAR, 0U); + WRITE_REG(RTCx->ALRMBR, 0U); + WRITE_REG(RTCx->SHIFTR, 0U); + WRITE_REG(RTCx->CALR, 0U); + WRITE_REG(RTCx->ALRMASSR, 0U); + WRITE_REG(RTCx->ALRMBSSR, 0U); + WRITE_REG(RTCx->PRIVCFGR, 0U); + + /* Clear some bits of RTC_ICSR and exit Initialization mode */ + CLEAR_BIT(RTCx->ICSR, RTC_ICSR_BCDU_Msk | RTC_ICSR_BIN_Msk | RTC_ICSR_INIT); + + /* Wait till the RTC RSF flag is set */ + status = LL_RTC_WaitForSynchro(RTCx); + } + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + /* DeInitialization of the TAMP registers */ + WRITE_REG(TAMP->CR1, 0U); + WRITE_REG(TAMP->CR2, 0U); + WRITE_REG(TAMP->CR3, 0U); + WRITE_REG(TAMP->CFGR, 0U); + WRITE_REG(TAMP->PRIVCFGR, 0U); + WRITE_REG(TAMP->FLTCR, 0U); + WRITE_REG(TAMP->ATCR1, 0x00070000U); + WRITE_REG(TAMP->ATCR2, 0U); + WRITE_REG(TAMP->IER, 0U); + WRITE_REG(TAMP->SCR, 0xFFFFFFFFU); + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTCx RTC Instance + * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat)); + assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler)); + assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Set Hour Format */ + LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat); + + /* Configure Synchronous and Asynchronous prescaler factor */ + LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler); + LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler); + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + status = SUCCESS; + } + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_InitTypeDef field to default value. + * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct) +{ + /* Set RTC_InitStruct fields to default values */ + RTC_InitStruct->HourFormat = LL_RTC_HOURFORMAT_24HOUR; + RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT; + RTC_InitStruct->SynchPrescaler = RTC_SYNCH_PRESC_DEFAULT; +} + +/** + * @brief Set the RTC current time. + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains + * the time configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours)); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat)); + } + else + { + RTC_TimeStruct->TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours)); + } + assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds)); + } + else + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat)); + } + else + { + RTC_TimeStruct->TimeFormat = 0U; + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); + } + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds))); + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Check the input parameters format */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours, + RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds); + } + else + { + LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours), + __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes), + __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds)); + } + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) + { + status = LL_RTC_WaitForSynchro(RTCx); + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec). + * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24; + RTC_TimeStruct->Hours = 0U; + RTC_TimeStruct->Minutes = 0U; + RTC_TimeStruct->Seconds = 0U; +} + +/** + * @brief Set the RTC current date. + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * the date configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Day register is configured + * - ERROR: RTC Day register is not configured + */ +ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + + if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U)) + { + RTC_DateStruct->Month = (uint8_t)((uint32_t) RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU; + } + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year)); + assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month)); + assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day)); + } + else + { + assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year))); + assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month))); + assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day))); + } + assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Check the input parameters format */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, + RTC_DateStruct->Year); + } + else + { + LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day), + __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), + __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year)); + } + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) + { + status = LL_RTC_WaitForSynchro(RTCx); + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00) + * @param RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY; + RTC_DateStruct->Day = 1U; + RTC_DateStruct->Month = LL_RTC_MONTH_JANUARY; + RTC_DateStruct->Year = 0U; +} + +/** + * @brief Set the RTC Alarm A. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use @ref LL_RTC_ALMA_Disable function). + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ALARMA registers are configured + * - ERROR: ALARMA registers are not configured + */ +ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask)); + assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); + } + assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + } + + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Select weekday selection */ + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + { + /* Set the date for ALARM */ + LL_RTC_ALMA_DisableWeekday(RTCx); + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + else + { + LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + /* Set the week day for ALARM */ + LL_RTC_ALMA_EnableWeekday(RTCx); + LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + + /* Configure the Alarm register */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours, + RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); + } + else + { + LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds)); + } + /* Set ALARM mask */ + LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask); + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return SUCCESS; +} + +/** + * @brief Set the RTC Alarm B. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (@ref LL_RTC_ALMB_Disable function). + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ALARMB registers are configured + * - ERROR: ALARMB registers are not configured + */ +ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask)); + assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); + } + assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + } + + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Select weekday selection */ + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + { + /* Set the date for ALARM */ + LL_RTC_ALMB_DisableWeekday(RTCx); + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + else + { + LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + /* Set the week day for ALARM */ + LL_RTC_ALMB_EnableWeekday(RTCx); + LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + + /* Configure the Alarm register */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours, + RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); + } + else + { + LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds)); + } + /* Set ALARM mask */ + LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask); + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / + * Day = 1st day of the month/Mask = all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM; + RTC_AlarmStruct->AlarmTime.Hours = 0U; + RTC_AlarmStruct->AlarmTime.Minutes = 0U; + RTC_AlarmStruct->AlarmTime.Seconds = 0U; + + /* Alarm Day Settings : Day = 1st day of the month */ + RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE; + RTC_AlarmStruct->AlarmDateWeekDay = 1U; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->AlarmMask = LL_RTC_ALMA_MASK_NONE; +} + +/** + * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / + * Day = 1st day of the month/Mask = all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM; + RTC_AlarmStruct->AlarmTime.Hours = 0U; + RTC_AlarmStruct->AlarmTime.Minutes = 0U; + RTC_AlarmStruct->AlarmTime.Seconds = 0U; + + /* Alarm Day Settings : Day = 1st day of the month */ + RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE; + RTC_AlarmStruct->AlarmDateWeekDay = 1U; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->AlarmMask = LL_RTC_ALMB_MASK_NONE; +} + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_INITMODE_TIMEOUT; + ErrorStatus status = SUCCESS; + uint32_t tmp; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Check if the Initialization mode is set */ + if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U) + { + /* Set the Initialization mode */ + LL_RTC_EnableInitMode(RTCx); + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + tmp = LL_RTC_IsActiveFlag_INIT(RTCx); + while ((timeout != 0U) && (tmp != 1U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout --; + } + tmp = LL_RTC_IsActiveFlag_INIT(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + } + return status; +} + +/** + * @brief Exit the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @note The RTC Initialization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC exited from in Init mode + * - ERROR: Not applicable + */ +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx) +{ + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Disable initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + return SUCCESS; +} + +/** + * @brief Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT; + uint32_t tmp; + ErrorStatus status = SUCCESS; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Clear RSF flag */ + LL_RTC_ClearFlag_RS(RTCx); + + /* Wait the registers to be synchronised */ + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + while ((timeout != 0U) && (tmp != 1U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout--; + } + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + } + + if (timeout == 0U) + { + status = ERROR; + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_sdmmc.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_sdmmc.c new file mode 100644 index 00000000000..28a3e1d5597 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_sdmmc.c @@ -0,0 +1,1907 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_sdmmc.c + * @author MCD Application Team + * @brief SDMMC Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the SDMMC peripheral: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### SDMMC peripheral features ##### + ============================================================================== + [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB + peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA + devices. + + [..] The SDMMC features include the following: + (+) Full compliance with MultiMediaCard System Specification Version 4.51. Card support + for three different databus modes: 1-bit (default), 4-bit and 8-bit. + (+) Full compatibility with previous versions of MultiMediaCards (backward compatibility). + (+) Full compliance with SD memory card specifications version 4.1. + (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and + UHS-II mode not supported). + (+) Full compliance with SDIO card specification version 4.0. Card support + for two different databus modes: 1-bit (default) and 4-bit. + (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and + UHS-II mode not supported). + (+) Data transfer up to 208 Mbyte/s for the 8 bit mode. (depending maximum allowed IO speed). + (+) Data and command output enable signals to control external bidirectional drivers + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a considered as a driver of service for external devices drivers + that interfaces with the SDMMC peripheral. + According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs + is used in the device's driver to perform SDMMC operations and functionalities. + + This driver is almost transparent for the final user, it is only used to implement other + functionalities of the external device. + + [..] + (+) The SDMMC clock is coming from output of PLL1_Q or PLL2_R. + Before start working with SDMMC peripheral make sure that the PLL is well configured. + The SDMMC peripheral uses two clock signals: + (++) PLL1_Q bus clock (default after reset) + (++) PLL2_R bus clock + + (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC + peripheral. + + (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx) + function and disable it using the function SDMMC_PowerState_OFF(SDMMCx). + + (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT) + and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode. + + (+) When using the DMA mode + (++) Configure the IDMA mode (Single buffer or double) + (++) Configure the buffer address + (++) Configure Data Path State Machine + + (+) To control the CPSM (Command Path State Machine) and send + commands to the card use the SDMMC_SendCommand(SDMMCx), + SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has + to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according + to the selected command to be sent. + The parameters that should be filled are: + (++) Command Argument + (++) Command Index + (++) Command Response type + (++) Command Wait + (++) CPSM Status (Enable or Disable). + + -@@- To check if the command is well received, read the SDMMC_CMDRESP + register using the SDMMC_GetCommandResponse(). + The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the + SDMMC_GetResponse() function. + + (+) To control the DPSM (Data Path State Machine) and send/receive + data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), + SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions. + + *** Read Operations *** + ======================= + [..] + (#) First, user has to fill the data structure (pointer to + SDMMC_DataInitTypeDef) according to the selected data type to be received. + The parameters that should be filled are: + (++) Data TimeOut + (++) Data Length + (++) Data Block size + (++) Data Transfer direction: should be from card (To SDMMC) + (++) Data Transfer mode + (++) DPSM Status (Enable or Disable) + + (#) Configure the SDMMC resources to receive the data from the card + according to selected transfer mode (Refer to Step 8, 9 and 10). + + (#) Send the selected Read command (refer to step 11). + + (#) Use the SDMMC flags/interrupts to check the transfer status. + + *** Write Operations *** + ======================== + [..] + (#) First, user has to fill the data structure (pointer to + SDMMC_DataInitTypeDef) according to the selected data type to be received. + The parameters that should be filled are: + (++) Data TimeOut + (++) Data Length + (++) Data Block size + (++) Data Transfer direction: should be to card (To CARD) + (++) Data Transfer mode + (++) DPSM Status (Enable or Disable) + + (#) Configure the SDMMC resources to send the data to the card according to + selected transfer mode. + + (#) Send the selected Write command. + + (#) Use the SDMMC flags/interrupts to check the transfer status. + + *** Command management operations *** + ===================================== + [..] + (#) The commands used for Read/Write/Erase operations are managed in + separate functions. + Each function allows to send the needed command with the related argument, + then check the response. + By the same approach, you could implement a command and check the response. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_HAL_Driver + * @{ + */ + +/** @defgroup SDMMC_LL SDMMC Low Layer + * @brief Low layer module for SD + * @{ + */ + +#if defined (SDMMC1) || defined (SDMMC2) +#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx); + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions + * @{ + */ + +/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization/de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SDMMC according to the specified + * parameters in the SDMMC_InitTypeDef and create the associated handle. + * @param SDMMCx: Pointer to SDMMC register base + * @param Init: SDMMC initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx)); + assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); + assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave)); + assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide)); + assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); + assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv)); + + /* Set SDMMC configuration parameters */ + tmpreg |= (Init.ClockEdge | \ + Init.ClockPowerSave | \ + Init.BusWide | \ + Init.HardwareFlowControl | \ + Init.ClockDiv + ); + + /* Write to SDMMC CLKCR */ + MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); + + return HAL_OK; +} + + +/** + * @} + */ + +/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### I/O operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SDMMC data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Read data (word) from Rx FIFO in blocking mode (polling) + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx) +{ + /* Read data from Rx FIFO */ + return (SDMMCx->FIFO); +} + +/** + * @brief Write data (word) to Tx FIFO in blocking mode (polling) + * @param SDMMCx: Pointer to SDMMC register base + * @param pWriteData: pointer to data to write + * @retval HAL status + */ +HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) +{ + /* Write data to FIFO */ + SDMMCx->FIFO = *pWriteData; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SDMMC data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Set SDMMC Power state to ON. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) +{ + /* Set power state to ON */ + SDMMCx->POWER |= SDMMC_POWER_PWRCTRL; + + return HAL_OK; +} + +/** + * @brief Set SDMMC Power state to Power-Cycle. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx) +{ + /* Set power state to Power Cycle*/ + SDMMCx->POWER |= SDMMC_POWER_PWRCTRL_1; + + return HAL_OK; +} + +/** + * @brief Set SDMMC Power state to OFF. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx) +{ + /* Set power state to OFF */ + SDMMCx->POWER &= ~(SDMMC_POWER_PWRCTRL); + + return HAL_OK; +} + +/** + * @brief Get SDMMC Power state. + * @param SDMMCx: Pointer to SDMMC register base + * @retval Power status of the controller. The returned value can be one of the + * following values: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx) +{ + return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL); +} + +/** + * @brief Configure the SDMMC command path according to the specified parameters in + * SDMMC_CmdInitTypeDef structure and send the command + * @param SDMMCx: Pointer to SDMMC register base + * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains + * the configuration information for the SDMMC command + * @retval HAL status + */ +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex)); + assert_param(IS_SDMMC_RESPONSE(Command->Response)); + assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt)); + assert_param(IS_SDMMC_CPSM(Command->CPSM)); + + /* Set the SDMMC Argument value */ + SDMMCx->ARG = Command->Argument; + + /* Set SDMMC command parameters */ + tmpreg |= (uint32_t)(Command->CmdIndex | \ + Command->Response | \ + Command->WaitForInterrupt | \ + Command->CPSM); + + /* Write to SDMMC CMD register */ + MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg); + + return HAL_OK; +} + +/** + * @brief Return the command index of last command for which response received + * @param SDMMCx: Pointer to SDMMC register base + * @retval Command index of the last command response received + */ +uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx) +{ + return (uint8_t)(SDMMCx->RESPCMD); +} + + +/** + * @brief Return the response received from the card for the last command + * @param SDMMCx: Pointer to SDMMC register base + * @param Response: Specifies the SDMMC response register. + * This parameter can be one of the following values: + * @arg SDMMC_RESP1: Response Register 1 + * @arg SDMMC_RESP2: Response Register 2 + * @arg SDMMC_RESP3: Response Register 3 + * @arg SDMMC_RESP4: Response Register 4 + * @retval The Corresponding response register value + */ +uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_SDMMC_RESP(Response)); + + /* Get the response */ + tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response; + + return (*(__IO uint32_t *) tmp); +} + +/** + * @brief Configure the SDMMC data path according to the specified + * parameters in the SDMMC_DataInitTypeDef. + * @param SDMMCx: Pointer to SDMMC register base + * @param Data : pointer to a SDMMC_DataInitTypeDef structure + * that contains the configuration information for the SDMMC data. + * @retval HAL status + */ +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength)); + assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize)); + assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir)); + assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode)); + assert_param(IS_SDMMC_DPSM(Data->DPSM)); + + /* Set the SDMMC Data TimeOut value */ + SDMMCx->DTIMER = Data->DataTimeOut; + + /* Set the SDMMC DataLength value */ + SDMMCx->DLEN = Data->DataLength; + + /* Set the SDMMC data configuration parameters */ + tmpreg |= (uint32_t)(Data->DataBlockSize | \ + Data->TransferDir | \ + Data->TransferMode | \ + Data->DPSM); + + /* Write to SDMMC DCTRL */ + MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); + + return HAL_OK; + +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @param SDMMCx: Pointer to SDMMC register base + * @retval Number of remaining data bytes to be transferred + */ +uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx) +{ + return (SDMMCx->DCOUNT); +} + +/** + * @brief Get the FIFO data + * @param SDMMCx: Pointer to SDMMC register base + * @retval Data received + */ +uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx) +{ + return (SDMMCx->FIFO); +} + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode. + * This parameter can be: + * @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK + * @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2 + * @retval None + */ +HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode)); + + /* Set SDMMC read wait mode */ + MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode); + + return HAL_OK; +} + +/** + * @} + */ + + +/** @defgroup HAL_SDMMC_LL_Group4 Command management functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Commands management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the needed commands. + +@endverbatim + * @{ + */ + +/** + * @brief Send the Data Block Length command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)BlockSize; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Data Block number command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)BlockCount; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCK_COUNT; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCK_COUNT, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Read Single Block command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Read Multi Block command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Write Single Block command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Write Multi Block command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Start Address Erase command for SD and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)StartAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the End Address Erase command for SD and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)EndAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Start Address Erase command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)StartAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the End Address Erase command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)EndAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Erase command and check the response + * @param SDMMCx Pointer to SDMMC register base + * @param EraseType Type of erase to be performed + * @retval HAL status + */ +uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = EraseType; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Stop Transfer command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD12 STOP_TRANSMISSION */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + + __SDMMC_CMDSTOP_ENABLE(SDMMCx); + __SDMMC_CMDTRANS_DISABLE(SDMMCx); + + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT); + + __SDMMC_CMDSTOP_DISABLE(SDMMCx); + + /* Ignore Address Out Of Range Error, Not relevant at end of memory */ + if (errorstate == SDMMC_ERROR_ADDR_OUT_OF_RANGE) + { + errorstate = SDMMC_ERROR_NONE; + } + + return errorstate; +} + +/** + * @brief Send the Select Deselect command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param addr: Address of the card to be selected + * @retval HAL status + */ +uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD7 SDMMC_SEL_DESEL_CARD */ + sdmmc_cmdinit.Argument = (uint32_t)Addr; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Go Idle State command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdError(SDMMCx); + + return errorstate; +} + +/** + * @brief Send the Operating Condition command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD8 to verify SD card interface operating condition */ + /* Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + /* CMD Response: R7 */ + sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp7(SDMMCx); + + return errorstate; +} + +/** + * @brief Send the Application command to verify that that the next command + * is an application specific com-mand rather than a standard command + * and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = (uint32_t)Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + /* If there is a HAL_ERROR, it is a MMC card, else + it is a SD card: SD card 2.0 (voltage range mismatch) + or SD card 1.x */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the command asking the accessed card to send its operating + * condition register (OCR) + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp3(SDMMCx); + + return errorstate; +} + +/** + * @brief Send the Bus Width command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param BusWidth: BusWidth + * @retval HAL status + */ +uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = (uint32_t)BusWidth; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Send SCR command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD51 SD_APP_SEND_SCR */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Send CID command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD2 ALL_SEND_CID */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp2(SDMMCx); + + return errorstate; +} + +/** + * @brief Send the Send CSD command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD9 SEND_CSD */ + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp2(SDMMCx); + + return errorstate; +} + +/** + * @brief Send the Send CSD command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param pRCA: Card RCA + * @retval HAL status + */ +uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD3 SD_CMD_SET_REL_ADDR */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA); + + return errorstate; +} + +/** + * @brief Send the Set Relative Address command to MMC card (not SD card). + * @param SDMMCx Pointer to SDMMC register base + * @param RCA Card RCA + * @retval HAL status + */ +uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD3 SD_CMD_SET_REL_ADDR */ + sdmmc_cmdinit.Argument = ((uint32_t)RCA << 16U); + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_REL_ADDR, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Sleep command to MMC card (not SD card). + * @param SDMMCx Pointer to SDMMC register base + * @param Argument Argument of the command (RCA and Sleep/Awake) + * @retval HAL status + */ +uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD5 SDMMC_CMD_MMC_SLEEP_AWAKE */ + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_MMC_SLEEP_AWAKE; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_MMC_SLEEP_AWAKE, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Status command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Status register command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Sends host capacity support information and activates the card's + * initialization process. Send SDMMC_CMD_SEND_OP_COND command + * @param SDMMCx: Pointer to SDMMC register base + * @parame Argument: Argument used for the command + * @retval HAL status + */ +uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp3(SDMMCx); + + return errorstate; +} + +/** + * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command + * @param SDMMCx: Pointer to SDMMC register base + * @parame Argument: Argument used for the command + * @retval HAL status + */ +uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */ + /* CMD Response: R1 */ + sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN*/ + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the command asking the accessed card to send its operating + * condition register (OCR) + * @param None + * @retval HAL status + */ +uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = 0x00000000; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_VOLTAGE_SWITCH; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_VOLTAGE_SWITCH, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Send EXT_CSD command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD9 SEND_CSD */ + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @} + */ + + +/** @defgroup HAL_SDMMC_LL_Group5 Responses management functions + * @brief Responses functions + * +@verbatim + =============================================================================== + ##### Responses management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the needed responses. + +@endverbatim + * @{ + */ +/** + * @brief Checks for error conditions for R1 response. + * @param hsd: SD handle + * @param SD_CMD: The sent command index + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout) +{ + uint32_t response_r1; + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The Timeout is expressed in ms */ + uint32_t count = Timeout * (SystemCoreClock / 8U / 1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT | + SDMMC_FLAG_BUSYD0END)) == 0U) || ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + + /* Check response received is of desired command */ + if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) + { + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* We have received response, retrieve it for analysis */ + response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); + + if ((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) + { + return SDMMC_ERROR_NONE; + } + else if ((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) + { + return SDMMC_ERROR_ADDR_OUT_OF_RANGE; + } + else if ((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) + { + return SDMMC_ERROR_ADDR_MISALIGNED; + } + else if ((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) + { + return SDMMC_ERROR_BLOCK_LEN_ERR; + } + else if ((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) + { + return SDMMC_ERROR_ERASE_SEQ_ERR; + } + else if ((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) + { + return SDMMC_ERROR_BAD_ERASE_PARAM; + } + else if ((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) + { + return SDMMC_ERROR_WRITE_PROT_VIOLATION; + } + else if ((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) + { + return SDMMC_ERROR_LOCK_UNLOCK_FAILED; + } + else if ((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) + { + return SDMMC_ERROR_COM_CRC_FAILED; + } + else if ((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) + { + return SDMMC_ERROR_ILLEGAL_CMD; + } + else if ((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) + { + return SDMMC_ERROR_CARD_ECC_FAILED; + } + else if ((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) + { + return SDMMC_ERROR_CC_ERR; + } + else if ((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) + { + return SDMMC_ERROR_STREAM_READ_UNDERRUN; + } + else if ((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) + { + return SDMMC_ERROR_STREAM_WRITE_OVERRUN; + } + else if ((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) + { + return SDMMC_ERROR_CID_CSD_OVERWRITE; + } + else if ((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) + { + return SDMMC_ERROR_WP_ERASE_SKIP; + } + else if ((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) + { + return SDMMC_ERROR_CARD_ECC_DISABLED; + } + else if ((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) + { + return SDMMC_ERROR_ERASE_RESET; + } + else if ((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) + { + return SDMMC_ERROR_AKE_SEQ_ERR; + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } +} + +/** + * @brief Checks for error conditions for R2 (CID or CSD) response. + * @param hsd: SD handle + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) +{ + uint32_t sta_reg; + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* No error flag set */ + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + } + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R3 (OCR) response. + * @param hsd: SD handle + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) +{ + uint32_t sta_reg; + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else + { + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + } + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R6 (RCA) response. + * @param hsd: SD handle + * @param SD_CMD: The sent command index + * @param pRCA: Pointer to the variable that will contain the SD card relative + * address RCA + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA) +{ + uint32_t response_r1; + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* Nothing to do */ + } + + /* Check response received is of desired command */ + if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) + { + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + + /* We have received response, retrieve it. */ + response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); + + if ((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | + SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) + { + *pRCA = (uint16_t)(response_r1 >> 16); + + return SDMMC_ERROR_NONE; + } + else if ((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) + { + return SDMMC_ERROR_ILLEGAL_CMD; + } + else if ((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) + { + return SDMMC_ERROR_COM_CRC_FAILED; + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } +} + +/** + * @brief Checks for error conditions for R7 response. + * @param hsd: SD handle + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) +{ + uint32_t sta_reg; + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + /* Card is not SD V2.0 compliant */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + /* Card is not SD V2.0 compliant */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* Nothing to do */ + } + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) + { + /* Card is SD V2.0 compliant */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND); + } + + return SDMMC_ERROR_NONE; + +} + +/** + * @} + */ + + +/** @defgroup HAL_SDMMC_LL_Group6 Linked List functions + * @brief Linked List management functions + * +@verbatim + =============================================================================== + ##### Linked List management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the needed functions. + +@endverbatim + * @{ + */ + +/** + * @brief Build new Linked List node. + * @param pNode: Pointer to new node to add. + * @param pNodeConf: Pointer to configuration parameters for new node to add. + * @retval Error status + */ +uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, SDMMC_DMALinkNodeConfTypeDef *pNodeConf) +{ + + if ((pNode == NULL) || (pNodeConf == NULL)) + { + return SDMMC_ERROR_INVALID_PARAMETER; + } + /* Configure the Link Node registers*/ + pNode->IDMABASER = pNodeConf->BufferAddress; + pNode->IDMABSIZE = pNodeConf->BufferSize; + pNode->IDMALAR = SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ABR; + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Insert new Linked List node. + * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes + * @param pPrevNode: Pointer to previous node . + * @param pNewNode: Pointer to new node to add. + * @retval Error status + */ +uint32_t SDMMC_DMALinkedList_InsertNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pPrevNode, + SDMMC_DMALinkNodeTypeDef *pNode) +{ + uint32_t link_list_offset; + uint32_t node_address = (uint32_t) pNode; + + /* First Node */ + if (pLinkedList->NodesCounter == 0U) + { + + pLinkedList->pHeadNode = pNode; + pLinkedList->pTailNode = pNode; + pLinkedList->NodesCounter = 1U; + + } + else if (pPrevNode == pLinkedList->pTailNode) + { + if (pNode <= pLinkedList->pHeadNode) + { + /* Node Address should greater than Head Node Address*/ + return SDMMC_ERROR_INVALID_PARAMETER; + } + + /*Last Node, no next node */ + MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_ULA, 0U); + + /*link Prev node with new one */ + MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_ULA, SDMMC_IDMALAR_ULA); + MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_IDMALA, (node_address - (uint32_t)pLinkedList->pHeadNode)); + + pLinkedList->NodesCounter ++; + pLinkedList->pTailNode = pNode; + + } + else + { + + if (pNode <= pLinkedList->pHeadNode) + { + /* Node Address should greater than Head Node Address*/ + return SDMMC_ERROR_INVALID_PARAMETER; + } + + /*link New node with Next one */ + link_list_offset = pNode->IDMALAR; + MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_IDMALA, link_list_offset); + + /*link Prev node with new one */ + MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_ULA, SDMMC_IDMALAR_ULA); + MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_IDMALA, (node_address - (uint32_t)pLinkedList->pHeadNode)); + + pLinkedList->NodesCounter ++; + + } + return SDMMC_ERROR_NONE; +} + +/** + * @brief Remove node from the Linked List. + * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes + * @param pNode: Pointer to new node to add. + * @retval Error status + */ +uint32_t SDMMC_DMALinkedList_RemoveNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pNode) +{ + uint32_t count = 0U; + uint32_t linked_list_offset; + SDMMC_DMALinkNodeTypeDef *prev_node = NULL; + SDMMC_DMALinkNodeTypeDef *curr_node ; + + /* First Node */ + if (pLinkedList->NodesCounter == 0U) + { + + return SDMMC_ERROR_INVALID_PARAMETER; + } + else + { + curr_node = pLinkedList->pHeadNode; + while ((curr_node != pNode) && (count <= pLinkedList->NodesCounter)) + { + prev_node = curr_node; + curr_node = (SDMMC_DMALinkNodeTypeDef *)((prev_node->IDMALAR & SDMMC_IDMALAR_IDMALA) + + (uint32_t)pLinkedList->pHeadNode); + count++; + } + + if ((count == 0U) || (count > pLinkedList->NodesCounter)) + { + /* Node not found in the linked list */ + return SDMMC_ERROR_INVALID_PARAMETER; + } + + pLinkedList->NodesCounter--; + + if (pLinkedList->NodesCounter == 0U) + { + pLinkedList->pHeadNode = 0U; + pLinkedList->pTailNode = 0U; + } + else + { + /*link prev node with next one */ + linked_list_offset = curr_node->IDMALAR; + MODIFY_REG(prev_node->IDMALAR, SDMMC_IDMALAR_IDMALA, linked_list_offset); + /* Configure the new Link Node registers*/ + pNode->IDMALAR |= linked_list_offset; + + pLinkedList->pTailNode = prev_node; + } + } + return SDMMC_ERROR_NONE; +} + +/** + * @brief Lock Linked List Node + * @param pNode: Pointer to node to lock. + * @retval Error status + + */ +uint32_t SDMMC_DMALinkedList_LockNode(SDMMC_DMALinkNodeTypeDef *pNode) +{ + + if (pNode == NULL) + { + return SDMMC_ERROR_INVALID_PARAMETER; + } + + MODIFY_REG(pNode->IDMALAR, SDMMC_IDMALAR_ABR, 0U); + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Unlock Linked List Node + * @param pNode: Pointer to node to unlock. + * @retval Error status + + */ +uint32_t SDMMC_DMALinkedList_UnlockNode(SDMMC_DMALinkNodeTypeDef *pNode) +{ + + if (pNode == NULL) + { + return SDMMC_ERROR_INVALID_PARAMETER; + } + + MODIFY_REG(pNode->IDMALAR, SDMMC_IDMALAR_ABR, SDMMC_IDMALAR_ABR); + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Enable Linked List circular mode + * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes + * @retval Error status + + */ +uint32_t SDMMC_DMALinkedList_EnableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList) +{ + + if (pLinkedList == NULL) + { + return SDMMC_ERROR_INVALID_PARAMETER; + } + + MODIFY_REG(pLinkedList->pTailNode->IDMALAR, SDMMC_IDMALAR_ULA | SDMMC_IDMALAR_IDMALA, SDMMC_IDMALAR_ULA); + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Disable DMA Linked List Circular mode + * @param pLinkedList: Pointer to the linkedlist that contains transfer nodes + * @retval Error status + */ +uint32_t SDMMC_DMALinkedList_DisableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList) +{ + + if (pLinkedList == NULL) + { + return SDMMC_ERROR_INVALID_PARAMETER; + } + + MODIFY_REG(pLinkedList->pTailNode->IDMALAR, SDMMC_IDMALAR_ULA, 0U); + + return SDMMC_ERROR_NONE; +} + +/** + * @} + */ + + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup SD_Private_Functions + * @{ + */ + +/** + * @brief Checks for error conditions for CMD0. + * @param hsd: SD handle + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) +{ + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + + } while (!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + + return SDMMC_ERROR_NONE; +} + +/** + * @} + */ + +#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_spi.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_spi.c new file mode 100644 index 00000000000..3878ae073c0 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_spi.c @@ -0,0 +1,751 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_spi.c + * @author MCD Application Team + * @brief SPI LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_spi.h" +#include "stm32h7rsxx_ll_bus.h" +#include "stm32h7rsxx_ll_rcc.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) + +/** @addtogroup SPI_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup SPI_LL_Private_Macros + * @{ + */ + +#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) || \ + ((__VALUE__) == LL_SPI_MODE_SLAVE)) + +#define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE)) + +#define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE)) + +#define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) || \ + ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN)) + +#define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) || \ + ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN)) + +#define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) || \ + ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) || \ + ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED)) + +#define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) || \ + ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) || \ + ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS)) + +#define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) || \ + ((__VALUE__) == LL_SPI_PROTOCOL_TI)) + +#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) || \ + ((__VALUE__) == LL_SPI_PHASE_2EDGE)) + +#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) || \ + ((__VALUE__) == LL_SPI_POLARITY_HIGH)) + +#define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_BYPASS) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) + +#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) || \ + ((__VALUE__) == LL_SPI_MSB_FIRST)) + +#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) || \ + ((__VALUE__) == LL_SPI_SIMPLEX_TX) || \ + ((__VALUE__) == LL_SPI_SIMPLEX_RX) || \ + ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) || \ + ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) + +#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT)) + +#define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_16DATA)) + +#define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) || \ + ((__VALUE__) == LL_SPI_CRC_5BIT) || \ + ((__VALUE__) == LL_SPI_CRC_6BIT) || \ + ((__VALUE__) == LL_SPI_CRC_7BIT) || \ + ((__VALUE__) == LL_SPI_CRC_8BIT) || \ + ((__VALUE__) == LL_SPI_CRC_9BIT) || \ + ((__VALUE__) == LL_SPI_CRC_10BIT) || \ + ((__VALUE__) == LL_SPI_CRC_11BIT) || \ + ((__VALUE__) == LL_SPI_CRC_12BIT) || \ + ((__VALUE__) == LL_SPI_CRC_13BIT) || \ + ((__VALUE__) == LL_SPI_CRC_14BIT) || \ + ((__VALUE__) == LL_SPI_CRC_15BIT) || \ + ((__VALUE__) == LL_SPI_CRC_16BIT) || \ + ((__VALUE__) == LL_SPI_CRC_17BIT) || \ + ((__VALUE__) == LL_SPI_CRC_18BIT) || \ + ((__VALUE__) == LL_SPI_CRC_19BIT) || \ + ((__VALUE__) == LL_SPI_CRC_20BIT) || \ + ((__VALUE__) == LL_SPI_CRC_21BIT) || \ + ((__VALUE__) == LL_SPI_CRC_22BIT) || \ + ((__VALUE__) == LL_SPI_CRC_23BIT) || \ + ((__VALUE__) == LL_SPI_CRC_24BIT) || \ + ((__VALUE__) == LL_SPI_CRC_25BIT) || \ + ((__VALUE__) == LL_SPI_CRC_26BIT) || \ + ((__VALUE__) == LL_SPI_CRC_27BIT) || \ + ((__VALUE__) == LL_SPI_CRC_28BIT) || \ + ((__VALUE__) == LL_SPI_CRC_29BIT) || \ + ((__VALUE__) == LL_SPI_CRC_30BIT) || \ + ((__VALUE__) == LL_SPI_CRC_31BIT) || \ + ((__VALUE__) == LL_SPI_CRC_32BIT)) + +#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) || \ + ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) || \ + ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) + +#define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) || \ + ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) || \ + ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) || \ + ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET)) + +#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) || \ + ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) + +#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the SPI registers to their default reset values. + * @param SPIx SPI Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are de-initialized + * - ERROR: SPI registers are not de-initialized + */ +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + +#if defined(SPI1) + if (SPIx == SPI1) + { + /* Force reset of SPI clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); + + /* Release reset of SPI clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); + + /* Update the return status */ + status = SUCCESS; + } +#endif /* SPI1 */ +#if defined(SPI2) + if (SPIx == SPI2) + { + /* Force reset of SPI clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); + + /* Release reset of SPI clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); + + /* Update the return status */ + status = SUCCESS; + } +#endif /* SPI2 */ +#if defined(SPI3) + if (SPIx == SPI3) + { + /* Force reset of SPI clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3); + + /* Release reset of SPI clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3); + + /* Update the return status */ + status = SUCCESS; + } +#endif /* SPI3 */ +#if defined(SPI4) + if (SPIx == SPI4) + { + /* Force reset of SPI clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4); + + /* Release reset of SPI clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4); + + /* Update the return status */ + status = SUCCESS; + } +#endif /* SPI4 */ +#if defined(SPI5) + if (SPIx == SPI5) + { + /* Force reset of SPI clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5); + + /* Release reset of SPI clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5); + + /* Update the return status */ + status = SUCCESS; + } +#endif /* SPI5 */ +#if defined(SPI6) + if (SPIx == SPI6) + { + /* Force reset of SPI clock */ + LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_SPI6); + + /* Release reset of SPI clock */ + LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_SPI6); + + /* Update the return status */ + status = SUCCESS; + } +#endif /* SPI6 */ + + return status; +} + +/** + * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. + * @note As some bits in SPI configuration registers can only be written when the SPI is disabled + * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. + * Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t tmp_nss; + uint32_t tmp_mode; + uint32_t tmp_nss_polarity; + + /* Check the SPI Instance SPIx*/ + assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + + /* Check the SPI parameters from SPI_InitStruct*/ + assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection)); + assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode)); + assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth)); + assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity)); + assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase)); + assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS)); + assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate)); + assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); + assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); + + /* Check the SPI instance is not enabled */ + if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL) + { + /*---------------------------- SPIx CFG1 Configuration ------------------------ + * Configure SPIx CFG1 with parameters: + * - Master Baud Rate : SPI_CFG1_MBR[2:0] bits & SPI_CFG1_BPASS bit + * - CRC Computation Enable : SPI_CFG1_CRCEN bit + * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits + */ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_BPASS | SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE, + SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth); + + tmp_nss = SPI_InitStruct->NSS; + tmp_mode = SPI_InitStruct->Mode; + tmp_nss_polarity = LL_SPI_GetNSSPolarity(SPIx); + + /* Checks to setup Internal SS signal level and avoid a MODF Error */ + if ((tmp_nss == LL_SPI_NSS_SOFT) && (((tmp_nss_polarity == LL_SPI_NSS_POLARITY_LOW) && \ + (tmp_mode == LL_SPI_MODE_MASTER)) || \ + ((tmp_nss_polarity == LL_SPI_NSS_POLARITY_HIGH) && \ + (tmp_mode == LL_SPI_MODE_SLAVE)))) + { + LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH); + } + + /*---------------------------- SPIx CFG2 Configuration ------------------------ + * Configure SPIx CFG2 with parameters: + * - NSS management : SPI_CFG2_SSM, SPI_CFG2_SSOE bits + * - ClockPolarity : SPI_CFG2_CPOL bit + * - ClockPhase : SPI_CFG2_CPHA bit + * - BitOrder : SPI_CFG2_LSBFRST bit + * - Master/Slave Mode : SPI_CFG2_MASTER bit + * - SPI Mode : SPI_CFG2_COMM[1:0] bits + */ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE | + SPI_CFG2_CPOL | SPI_CFG2_CPHA | + SPI_CFG2_LSBFRST | SPI_CFG2_MASTER | SPI_CFG2_COMM, + SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity | + SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder | + SPI_InitStruct->Mode | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM)); + + /*---------------------------- SPIx CR1 Configuration ------------------------ + * Configure SPIx CR1 with parameter: + * - Half Duplex Direction : SPI_CR1_HDDIR bit + */ + MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR); + + /*---------------------------- SPIx CRCPOLY Configuration ---------------------- + * Configure SPIx CRCPOLY with parameter: + * - CRCPoly : CRCPOLY[31:0] bits + */ + if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); + LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); + } + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); + + status = SUCCESS; + } + + return status; +} + +/** + * @brief Set each @ref LL_SPI_InitTypeDef field to default value. + * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) +{ + /* Set SPI_InitStruct fields to default values */ + SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX; + SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE; + SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT; + SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW; + SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE; + SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT; + SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; + SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST; + SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + SPI_InitStruct->CRCPoly = 7UL; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/** @addtogroup I2S_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2S_LL_Private_Constants I2S Private Constants + * @{ + */ +/* I2S registers Masks */ +#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ + SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_CKPOL | \ + SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_MCKOE | \ + SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Private_Macros I2S Private Macros + * @{ + */ + +#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) || \ + ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) || \ + ((__VALUE__) == LL_I2S_DATAFORMAT_24B) || \ + ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) || \ + ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) + +#define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__) (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH) || \ + ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH)) + +#define IS_LL_I2S_CKPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) || \ + ((__VALUE__) == LL_I2S_POLARITY_HIGH)) + +#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) || \ + ((__VALUE__) == LL_I2S_STANDARD_MSB) || \ + ((__VALUE__) == LL_I2S_STANDARD_LSB) || \ + ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) || \ + ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) + +#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) || \ + ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) || \ + ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX) || \ + ((__VALUE__) == LL_I2S_MODE_MASTER_TX) || \ + ((__VALUE__) == LL_I2S_MODE_MASTER_RX) || \ + ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX)) + +#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) || \ + ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) + +#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) && \ + ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) || \ + ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) + +#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) <= 0xFFUL) + +#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) || \ + ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) + +#define IS_LL_I2S_FIFO_TH (__VALUE__) (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA)) + +#define IS_LL_I2S_BIT_ORDER(__VALUE__) (((__VALUE__) == LL_I2S_LSB_FIRST) || \ + ((__VALUE__) == LL_I2S_MSB_FIRST)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2S_LL_Exported_Functions + * @{ + */ + +/** @addtogroup I2S_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the SPI/I2S registers to their default reset values. + * @param SPIx SPI Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are de-initialized + * - ERROR: SPI registers are not de-initialized + */ +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx) +{ + return LL_SPI_DeInit(SPIx); +} + +/** + * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. + * @note As some bits in I2S configuration registers can only be written when the SPI is disabled + * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. + * Otherwise, ERROR result will be returned. + * @note I2S (SPI) source clock must be ready before calling this function. Otherwise will results + * in wrong programming. + * @param SPIx SPI Instance + * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are Initialized + * - ERROR: SPI registers are not Initialized + */ +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) +{ + uint32_t i2sdiv = 0UL; + uint32_t i2sodd = 0UL; + uint32_t packetlength = 1UL; + uint32_t ispcm = 0UL; + uint32_t tmp; + uint32_t sourceclock; + + ErrorStatus status = ERROR; + + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); + assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); + assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); + assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); + assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); + assert_param(IS_LL_I2S_CKPOL(I2S_InitStruct->ClockPolarity)); + + /* Check that SPE bit is set to 0 in order to be sure that SPI/I2S block is disabled. + * In this case, it is useless to check if the I2SMOD bit is set to 0 because + * this bit I2SMOD only serves to select the desired mode. + */ + if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL) + { + /*---------------------------- SPIx I2SCFGR Configuration -------------------- + * Configure SPIx I2SCFGR with parameters: + * - Mode : SPI_I2SCFGR_I2SCFG[2:0] bits + * - Standard : SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits + * - DataFormat : SPI_I2SCFGR_CHLEN, SPI_I2SCFGR_DATFMT and SPI_I2SCFGR_DATLEN[1:0] bits + * - ClockPolarity : SPI_I2SCFGR_CKPOL bit + * - MCLKOutput : SPI_I2SPR_MCKOE bit + * - I2S mode : SPI_I2SCFGR_I2SMOD bit + */ + + /* Write to SPIx I2SCFGR */ + MODIFY_REG(SPIx->I2SCFGR, + I2S_I2SCFGR_CLEAR_MASK, + I2S_InitStruct->Mode | I2S_InitStruct->Standard | + I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | + I2S_InitStruct->MCLKOutput | SPI_I2SCFGR_I2SMOD); + + /*---------------------------- SPIx I2SCFGR Configuration ---------------------- + * Configure SPIx I2SCFGR with parameters: + * - AudioFreq : SPI_I2SCFGR_I2SDIV[7:0] and SPI_I2SCFGR_ODD bits + */ + + /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) + * else, default values are used: i2sodd = 0U, i2sdiv = 0U. + */ + if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) + { + /* Check the frame length (For the Prescaler computing) + * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). + */ + if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) + { + /* Packet length is 32 bits */ + packetlength = 2UL; + } + + /* Check if PCM standard is used */ + if ((I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_SHORT) || + (I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_LONG)) + { + ispcm = 1UL; + } + + /* Get the I2S (SPI) source clock value */ + if (SPIx == SPI1) + { + sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI1_CLKSOURCE); + } + else if ((SPIx == SPI2) || (SPIx == SPI3)) + { + sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI23_CLKSOURCE); + } + else /* SPI6 */ + { + sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI6_CLKSOURCE); + } + + /* Compute the Real divider depending on the MCLK output state with a fixed point */ + if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) + { + /* MCLK output is enabled */ + tmp = (((sourceclock / (256UL >> ispcm)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL; + } + else + { + /* MCLK output is disabled */ + tmp = (((sourceclock / ((32UL >> ispcm) * packetlength)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL; + } + + /* Remove the fixed point */ + tmp = tmp / 16UL; + + /* Check the parity of the divider */ + i2sodd = tmp & 0x1UL; + + /* Compute the i2sdiv prescaler */ + i2sdiv = tmp / 2UL; + } + + /* Test if the obtain values are forbidden or out of range */ + if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL)) + { + /* Set the default values */ + i2sdiv = 0UL; + i2sodd = 0UL; + } + + /* Write to SPIx I2SCFGR register the computed value */ + MODIFY_REG(SPIx->I2SCFGR, + SPI_I2SCFGR_ODD | SPI_I2SCFGR_I2SDIV, + (i2sodd << SPI_I2SCFGR_ODD_Pos) | (i2sdiv << SPI_I2SCFGR_I2SDIV_Pos)); + + status = SUCCESS; + } + + return status; +} + +/** + * @brief Set each @ref LL_I2S_InitTypeDef field to default value. + * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) +{ + /*--------------- Reset I2S init structure parameters values -----------------*/ + I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; + I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; + I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; + I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; + I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; + I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; +} + +/** + * @brief Set linear and parity prescaler. + * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n + * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). + * @param SPIx SPI Instance + * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF + * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) +{ + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); + assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); + + /* Write to SPIx I2SPR */ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos) | + (PrescalerParity << SPI_I2SCFGR_ODD_Pos)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_tim.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_tim.c new file mode 100644 index 00000000000..31cd5e4c4b0 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_tim.c @@ -0,0 +1,1388 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_tim.c + * @author MCD Application Team + * @brief TIM LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_tim.h" +#include "stm32h7rsxx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM9) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) + +/** @addtogroup TIM_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup TIM_LL_Private_Macros + * @{ + */ +#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) + +#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) + +#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ + || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \ + || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT)) + +#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ + || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) + +#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ + || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) + +#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ + || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) + +#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) + +#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) + +#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) + +#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) + +#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2)) + +#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + +#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) + +#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) + +#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) + +#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) + +#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) + +#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) + +#define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \ + || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL)) + +#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) + +#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) + +#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) + +#define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \ + || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL)) + +#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ + || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup TIM_LL_Private_Functions TIM Private Functions + * @{ + */ +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_LL_Exported_Functions + * @{ + */ + +/** @addtogroup TIM_LL_EF_Init + * @{ + */ + +/** + * @brief Set TIMx registers to their reset values. + * @param TIMx Timer instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: invalid TIMx instance + */ +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx) +{ + ErrorStatus result = SUCCESS; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(TIMx)); + + if (TIMx == TIM1) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); + } + else if (TIMx == TIM2) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); + } + else if (TIMx == TIM3) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); + } + else if (TIMx == TIM4) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); + } + else if (TIMx == TIM5) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); + } + else if (TIMx == TIM6) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); + } + else if (TIMx == TIM7) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); + } + else if (TIMx == TIM9) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9); + } + else if (TIMx == TIM12) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12); + } + else if (TIMx == TIM13) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13); + } + else if (TIMx == TIM14) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14); + } + else if (TIMx == TIM15) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15); + } + else if (TIMx == TIM16) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16); + } + else if (TIMx == TIM17) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17); + } + else + { + result = ERROR; + } + + return result; +} + +/** + * @brief Set the fields of the time base unit configuration data structure + * to their default values. + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) + * @retval None + */ +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) +{ + /* Set the default configuration */ + TIM_InitStruct->Prescaler = (uint16_t)0x0000; + TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct->Autoreload = 0xFFFFFFFFU; + TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + TIM_InitStruct->RepetitionCounter = 0x00000000U; +} + +/** + * @brief Configure the TIMx time base unit. + * @param TIMx Timer Instance + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure + * (TIMx time base unit configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); + assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); + + tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); + + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); + } + + /* Write to TIMx CR1 */ + LL_TIM_WriteReg(TIMx, CR1, tmpcr1); + + /* Set the Autoreload value */ + LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); + + /* Set the Prescaler value */ + LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); + } + + /* Generate an update event to reload the Prescaler + and the repetition counter value (if applicable) immediately */ + LL_TIM_GenerateEvent_UPDATE(TIMx); + + return SUCCESS; +} + +/** + * @brief Set the fields of the TIMx output channel configuration data + * structure to their default values. + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure + * (the output channel configuration data structure) + * @retval None + */ +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + /* Set the default configuration */ + TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; + TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct->CompareValue = 0x00000000U; + TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; + TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; +} + +/** + * @brief Configure the TIMx output channel. + * @param TIMx Timer Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration + * data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx output channel is initialized + * - ERROR: TIMx output channel is not initialized + */ +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + ErrorStatus result = ERROR; + + switch (Channel) + { + case LL_TIM_CHANNEL_CH1: + result = OC1Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH2: + result = OC2Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH3: + result = OC3Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH4: + result = OC4Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH5: + result = OC5Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH6: + result = OC6Config(TIMx, TIM_OC_InitStruct); + break; + default: + break; + } + + return result; +} + +/** + * @brief Set the fields of the TIMx input channel configuration data + * structure to their default values. + * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration + * data structure) + * @retval None + */ +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; + TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; + TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; +} + +/** + * @brief Configure the TIMx input channel. + * @param TIMx Timer Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data + * structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx output channel is initialized + * - ERROR: TIMx output channel is not initialized + */ +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) +{ + ErrorStatus result = ERROR; + + switch (Channel) + { + case LL_TIM_CHANNEL_CH1: + result = IC1Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH2: + result = IC2Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH3: + result = IC3Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH4: + result = IC4Config(TIMx, TIM_IC_InitStruct); + break; + default: + break; + } + + return result; +} + +/** + * @brief Fills each TIM_EncoderInitStruct field with its default value + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface + * configuration data structure) + * @retval None + */ +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +{ + /* Set the default configuration */ + TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; + TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; + TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; +} + +/** + * @brief Configure the encoder interface of the timer instance. + * @param TIMx Timer Instance + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface + * configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Configure TI1 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); + + /* Configure TI2 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); + + /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ + tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); + tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); + tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Set encoder mode */ + LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Set the fields of the TIMx Hall sensor interface configuration data + * structure to their default values. + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface + * configuration data structure) + * @retval None + */ +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +{ + /* Set the default configuration */ + TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + TIM_HallSensorInitStruct->CommutationDelay = 0U; +} + +/** + * @brief Configure the Hall sensor interface of the timer instance. + * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR + * to the TI1 input channel + * @note TIMx slave mode controller is configured in reset mode. + Selected internal trigger is TI1F_ED. + * @note Channel 1 is configured as input, IC1 is mapped on TRC. + * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed + * between 2 changes on the inputs. It gives information about motor speed. + * @note Channel 2 is configured in output PWM 2 mode. + * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. + * @note OC2REF is selected as trigger output on TRGO. + * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used + * when TIMx operates in Hall sensor interface mode. + * @param TIMx Timer Instance + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor + * interface configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +{ + uint32_t tmpcr2; + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); + assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx SMCR register value */ + tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); + + /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ + tmpcr2 |= TIM_CR2_TI1S; + + /* OC2REF signal is used as trigger output (TRGO) */ + tmpcr2 |= LL_TIM_TRGO_OC2REF; + + /* Configure the slave mode controller */ + tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); + tmpsmcr |= LL_TIM_TS_TI1F_ED; + tmpsmcr |= LL_TIM_SLAVEMODE_RESET; + + /* Configure input channel 1 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); + tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); + tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); + + /* Configure input channel 2 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); + tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); + + /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ + tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); + tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx SMCR */ + LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + /* Write to TIMx CCR2 */ + LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); + + return SUCCESS; +} + +/** + * @brief Set the fields of the Break and Dead Time configuration data structure + * to their default values. + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) + * @retval None + */ +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; + TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; + TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; + TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; + TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; + TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT; + TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; + TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; + TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; + TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT; + TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; +} + +/** + * @brief Configure the Break and Dead Time feature of the timer instance. + * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR + * and DTG[7:0] can be write-locked depending on the LOCK configuration, it + * can be necessary to configure all of them during the first write access to + * the TIMx_BDTR register. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @param TIMx Timer Instance + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Break and Dead Time is initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + uint32_t tmpbdtr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); + assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); + assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); + assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); + assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); + assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); + + if (IS_TIM_BKIN2_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State)); + assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); + assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); + assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode)); + + /* Set the BREAK2 input related BDTR bit-fields */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode); + } + + /* Set TIMx_BDTR */ + LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); + + return SUCCESS; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIM_LL_Private_Functions TIM Private Functions + * @brief Private functions + * @{ + */ +/** + * @brief Configure the TIMx output channel 1. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); + + /* Set the Output Compare Mode */ + MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 2. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 3. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + + /* Disable the Channel 3: Reset the CC3E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR2 */ + LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 4. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR2 */ + LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 5. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr3; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + + /* Disable the Channel 5: Reset the CC5E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CCMR3 register value */ + tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the Output Idle state */ + MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U); + + } + + /* Write to TIMx CCMR3 */ + LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 6. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr3; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + + /* Disable the Channel 5: Reset the CC6E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CCMR3 register value */ + tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the Output Idle state */ + MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U); + } + + /* Write to TIMx CCMR3 */ + LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 1. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR1, + (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); + + /* Select the Polarity and set the CC1E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC1P | TIM_CCER_CC1NP), + (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 2. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR1, + (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); + + /* Select the Polarity and set the CC2E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC2P | TIM_CCER_CC2NP), + ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 3. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR2, + (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); + + /* Select the Polarity and set the CC3E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC3P | TIM_CCER_CC3NP), + ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 4. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR2, + (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); + + /* Select the Polarity and set the CC4E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC4P | TIM_CCER_CC4NP), + ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); + + return SUCCESS; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM9 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_ucpd.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_ucpd.c new file mode 100644 index 00000000000..934b1f9a4d4 --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_ucpd.c @@ -0,0 +1,169 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_ucpd.c + * @author MCD Application Team + * @brief UCPD LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_ucpd.h" +#include "stm32h7rsxx_ll_bus.h" +#include "stm32h7rsxx_ll_rcc.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ +#if defined (UCPD1) +/** @addtogroup UCPD_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UCPD_LL_Private_Constants UCPD Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UCPD_LL_Private_Macros UCPD Private Macros + * @{ + */ + + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UCPD_LL_Exported_Functions + * @{ + */ + +/** @addtogroup UCPD_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the UCPD registers to their default reset values. + * @param UCPDx ucpd Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ucpd registers are de-initialized + * - ERROR: ucpd registers are not de-initialized + */ +ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_UCPD_ALL_INSTANCE(UCPDx)); + + LL_UCPD_Disable(UCPDx); + + if (UCPD1 == UCPDx) + { + /* Force reset of ucpd clock */ + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_UCPD1); + + /* Release reset of ucpd clock */ + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_UCPD1); + + /* Disable ucpd clock */ + LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_UCPD1); + + status = SUCCESS; + } + + return status; +} + +/** + * @brief Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct. + * @note As some bits in ucpd configuration registers can only be written when the ucpd is disabled + * (ucpd_CR1_SPE bit =0), UCPD peripheral should be in disabled state prior calling this function. + * Otherwise, ERROR result will be returned. + * @param UCPDx UCPD Instance + * @param UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure that contains + * the configuration information for the UCPD peripheral. + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct) +{ + /* Check the ucpd Instance UCPDx*/ + assert_param(IS_UCPD_ALL_INSTANCE(UCPDx)); + + if (UCPD1 == UCPDx) + { + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_UCPD1); + } + + + LL_UCPD_Disable(UCPDx); + + /*---------------------------- UCPDx CFG1 Configuration ------------------------*/ + MODIFY_REG(UCPDx->CFG1, + UCPD_CFG1_PSC_UCPDCLK | UCPD_CFG1_TRANSWIN | UCPD_CFG1_IFRGAP | UCPD_CFG1_HBITCLKDIV, + UCPD_InitStruct->psc_ucpdclk | (UCPD_InitStruct->transwin << UCPD_CFG1_TRANSWIN_Pos) | + (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_UCPD_InitTypeDef field to default value. + * @param UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct) +{ + /* Set UCPD_InitStruct fields to default values */ + UCPD_InitStruct->psc_ucpdclk = LL_UCPD_PSC_DIV2; + UCPD_InitStruct->transwin = 0x7; /* Divide by 8 */ + UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */ + UCPD_InitStruct->HbitClockDiv = 0x0D; /* Divide by 14 to produce HBITCLK */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (UCPD1) */ +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_usart.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_usart.c new file mode 100644 index 00000000000..cde51f5c7db --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_usart.c @@ -0,0 +1,451 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_usart.c + * @author MCD Application Team + * @brief USART LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_usart.h" +#include "stm32h7rsxx_ll_rcc.h" +#include "stm32h7rsxx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) \ + || defined(UART7) || defined(UART8) + +/** @addtogroup USART_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Constants + * @{ + */ + +/* Definition of default baudrate value used for USART initialisation */ +#define USART_DEFAULT_BAUDRATE (9600U) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Macros + * @{ + */ + +#define IS_LL_USART_PRESCALER(__VALUE__) (((__VALUE__) == LL_USART_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV256)) + +/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available + * divided by the smallest oversampling used on the USART (i.e. 8) */ +#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U) + +/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ +#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) + +#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ + || ((__VALUE__) == LL_USART_DIRECTION_RX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) + +#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ + || ((__VALUE__) == LL_USART_PARITY_EVEN) \ + || ((__VALUE__) == LL_USART_PARITY_ODD)) + +#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \ + || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) + +#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ + || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) + +#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ + || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) + +#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ + || ((__VALUE__) == LL_USART_PHASE_2EDGE)) + +#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ + || ((__VALUE__) == LL_USART_POLARITY_HIGH)) + +#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ + || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) + +#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_1) \ + || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_2)) + +#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USART_LL_Exported_Functions + * @{ + */ + +/** @addtogroup USART_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize USART registers (Registers restored to their default values). + * @param USARTx USART Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers are de-initialized + * - ERROR: USART registers are not de-initialized + */ +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + + if (USARTx == USART1) + { + /* Force reset of USART clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1); + + /* Release reset of USART clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1); + } + else if (USARTx == USART2) + { + /* Force reset of USART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2); + + /* Release reset of USART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); + } + else if (USARTx == USART3) + { + /* Force reset of USART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3); + + /* Release reset of USART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3); + } + else if (USARTx == UART4) + { + /* Force reset of UART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4); + + /* Release reset of UART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4); + } + else if (USARTx == UART5) + { + /* Force reset of UART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5); + + /* Release reset of UART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5); + } + else if (USARTx == UART7) + { + /* Force reset of UART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7); + + /* Release reset of UART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7); + } + else if (USARTx == UART8) + { + /* Force reset of UART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8); + + /* Release reset of UART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize USART registers according to the specified + * parameters in USART_InitStruct. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. + * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). + * @param USARTx USART Instance + * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure + * that contains the configuration information for the specified USART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers are initialized according to USART_InitStruct content + * - ERROR: Problem occurred during USART Registers initialization + */ +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue)); + assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate)); + assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth)); + assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits)); + assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity)); + assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection)); + assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl)); + assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling)); + + /* USART needs to be in disabled state, in order to be able to configure some bits in + CRx registers */ + if (LL_USART_IsEnabled(USARTx) == 0U) + { + /*---------------------------- USART CR1 Configuration --------------------- + * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters: + * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value + * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value + * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value + * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value. + */ + MODIFY_REG(USARTx->CR1, + (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + (USART_InitStruct->DataWidth | USART_InitStruct->Parity | + USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling)); + + /*---------------------------- USART CR2 Configuration --------------------- + * Configure USARTx CR2 (Stop bits) with parameters: + * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value. + * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit(). + */ + LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits); + + /*---------------------------- USART CR3 Configuration --------------------- + * Configure USARTx CR3 (Hardware Flow Control) with parameters: + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to + * USART_InitStruct->HardwareFlowControl value. + */ + LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); + + /*---------------------------- USART BRR Configuration --------------------- + * Retrieve Clock frequency used for USART Peripheral + */ + if (USARTx == USART1) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE); + } + else if (USARTx == USART2) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE); + } + else if (USARTx == USART3) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE); + } + else if (USARTx == UART4) + { + periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_USART234578_CLKSOURCE); + } + else if (USARTx == UART5) + { + periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_USART234578_CLKSOURCE); + } + else if (USARTx == UART7) + { + periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_USART234578_CLKSOURCE); + } + else if (USARTx == UART8) + { + periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_USART234578_CLKSOURCE); + } + else + { + /* Nothing to do, as error code is already assigned to ERROR value */ + } + + /* Configure the USART Baud Rate : + - prescaler value is required + - valid baud rate value (different from 0) is required + - Peripheral clock as returned by RCC service, should be valid (different from 0). + */ + if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) + && (USART_InitStruct->BaudRate != 0U)) + { + status = SUCCESS; + LL_USART_SetBaudRate(USARTx, + periphclk, + USART_InitStruct->PrescalerValue, + USART_InitStruct->OverSampling, + USART_InitStruct->BaudRate); + + /* Check BRR is greater than or equal to 16d */ + assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); + } + + /*---------------------------- USART PRESC Configuration ----------------------- + * Configure USARTx PRESC (Prescaler) with parameters: + * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value. + */ + LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue); + } + /* Endif (=> USART not in Disabled state => return ERROR) */ + + return (status); +} + +/** + * @brief Set each @ref LL_USART_InitTypeDef field to default value. + * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) +{ + /* Set USART_InitStruct fields to default values */ + USART_InitStruct->PrescalerValue = LL_USART_PRESCALER_DIV1; + USART_InitStruct->BaudRate = USART_DEFAULT_BAUDRATE; + USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; + USART_InitStruct->StopBits = LL_USART_STOPBITS_1; + USART_InitStruct->Parity = LL_USART_PARITY_NONE ; + USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX; + USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE; + USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16; +} + +/** + * @brief Initialize USART Clock related settings according to the + * specified parameters in the USART_ClockInitStruct. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. + * @param USARTx USART Instance + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure + * that contains the Clock configuration information for the specified USART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers related to Clock settings are initialized according + * to USART_ClockInitStruct content + * - ERROR: Problem occurred during USART Registers initialization + */ +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check USART Instance and Clock signal output parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput)); + + /* USART needs to be in disabled state, in order to be able to configure some bits in + CRx registers */ + if (LL_USART_IsEnabled(USARTx) == 0U) + { + /* Ensure USART instance is USART capable */ + assert_param(IS_USART_INSTANCE(USARTx)); + + /* Check clock related parameters */ + assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); + assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); + assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); + + /*---------------------------- USART CR2 Configuration ----------------------- + * Configure USARTx CR2 (Clock signal related bits) with parameters: + * - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value + * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value + * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value + * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. + */ + MODIFY_REG(USARTx->CR2, + USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, + USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity | + USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); + } + /* Else (USART not in Disabled state => return ERROR */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + /* Set LL_USART_ClockInitStruct fields with default values */ + USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; + USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || UART4 || UART5 || UART7 || UART8 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + + diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_usb.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_usb.c new file mode 100644 index 00000000000..9c7ad5e3b7b --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_usb.c @@ -0,0 +1,2316 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_usb.c + * @author MCD Application Team + * @brief USB Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Fill parameters of Init structure in USB_CfgTypeDef structure. + + (#) Call USB_CoreInit() API to initialize the USB Core peripheral. + + (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. + + @endverbatim + + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/** @addtogroup STM32H7RSxx_LL_USB_DRIVER + * @{ + */ + +#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ + +/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization/de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the USB Core + * @param USBx USB Instance + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret; +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) + { + /* Init The UTMI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS); + } + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + + if (cfg.dma_enable == 1U) + { + USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; + USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + } + } + else +#endif /* defined (USB_OTG_HS) */ + { + /* Select FS Embedded PHY */ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + + if (cfg.battery_charging_enable == 0U) + { + /* Activate the USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } + else + { + /* Deactivate the USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } + } + + return ret; +} + + +/** + * @brief Set the USB turnaround time + * @param USBx USB Instance + * @param hclk: AHB clock frequency + * @retval USB turnaround time In PHY Clocks number + */ +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, + uint32_t hclk, uint8_t speed) +{ + uint32_t UsbTrd; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + if (speed == USBD_FS_SPEED) + { + if ((hclk >= 14200000U) && (hclk < 15000000U)) + { + /* hclk Clock Range between 14.2-15 MHz */ + UsbTrd = 0xFU; + } + else if ((hclk >= 15000000U) && (hclk < 16000000U)) + { + /* hclk Clock Range between 15-16 MHz */ + UsbTrd = 0xEU; + } + else if ((hclk >= 16000000U) && (hclk < 17200000U)) + { + /* hclk Clock Range between 16-17.2 MHz */ + UsbTrd = 0xDU; + } + else if ((hclk >= 17200000U) && (hclk < 18500000U)) + { + /* hclk Clock Range between 17.2-18.5 MHz */ + UsbTrd = 0xCU; + } + else if ((hclk >= 18500000U) && (hclk < 20000000U)) + { + /* hclk Clock Range between 18.5-20 MHz */ + UsbTrd = 0xBU; + } + else if ((hclk >= 20000000U) && (hclk < 21800000U)) + { + /* hclk Clock Range between 20-21.8 MHz */ + UsbTrd = 0xAU; + } + else if ((hclk >= 21800000U) && (hclk < 24000000U)) + { + /* hclk Clock Range between 21.8-24 MHz */ + UsbTrd = 0x9U; + } + else if ((hclk >= 24000000U) && (hclk < 27700000U)) + { + /* hclk Clock Range between 24-27.7 MHz */ + UsbTrd = 0x8U; + } + else if ((hclk >= 27700000U) && (hclk < 32000000U)) + { + /* hclk Clock Range between 27.7-32 MHz */ + UsbTrd = 0x7U; + } + else /* if(hclk >= 32000000) */ + { + /* hclk Clock Range between 32-200 MHz */ + UsbTrd = 0x6U; + } + } + else if (speed == USBD_HS_SPEED) + { + UsbTrd = USBD_HS_TRDT_VALUE; + } + else + { + UsbTrd = USBD_DEFAULT_TRDT_VALUE; + } + + USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); + + return HAL_OK; +} + +/** + * @brief USB_EnableGlobalInt + * Enables the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_DisableGlobalInt + * Disable the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_SetCurrentMode Set functional mode + * @param USBx Selected device + * @param mode current core mode + * This parameter can be one of these values: + * @arg USB_DEVICE_MODE Peripheral mode + * @arg USB_HOST_MODE Host mode + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) +{ + uint32_t ms = 0U; + + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + + if (mode == USB_HOST_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + + do + { + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); + } + else if (mode == USB_DEVICE_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + + do + { + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); + } + else + { + return HAL_ERROR; + } + + if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief USB_DevInit Initializes the USB_OTG controller registers + * for device mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + for (i = 0U; i < 15U; i++) + { + USBx->DIEPTXF[i] = 0U; + } + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { + /* Disable USB PHY pulldown resistors */ + USBx->GCCFG &= ~USB_OTG_GCCFG_PULLDOWNEN; + } + + /* VBUS Sensing setup */ + if (cfg.vbus_sensing_enable == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + + /* Deactivate VBUS Sensing B */ + USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + /* B-peripheral session valid override enable */ + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { + USBx->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN; + USBx->GCCFG |= USB_OTG_GCCFG_VBVALOVAL; + } + else + { + USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + } + } + else + { + /* B-peripheral session valid override disable */ + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { + USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALEXTOEN; + USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALOVAL; + } + else + { + USBx->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOEN; + USBx->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL; + } + + /* Enable HW VBUS sensing */ + USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; + } + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { + if (cfg.speed == USBD_HS_SPEED) + { + /* Set Core speed to High speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); + } + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); + } + + /* Flush the FIFOs */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Clear all pending Device Interrupts */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + if (i == 0U) + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + } + else + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; + } + } + else + { + USBx_INEP(i)->DIEPCTL = 0U; + } + + USBx_INEP(i)->DIEPTSIZ = 0U; + USBx_INEP(i)->DIEPINT = 0xFB7FU; + } + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + if (i == 0U) + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + } + else + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; + } + } + else + { + USBx_OUTEP(i)->DOEPCTL = 0U; + } + + USBx_OUTEP(i)->DOEPTSIZ = 0U; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = 0xBFFFFFFFU; + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + /* Enable interrupts matching to the Device mode ONLY */ + USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | + USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; + + if (cfg.Sof_enable != 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; + } + + if (cfg.vbus_sensing_enable == 1U) + { + USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); + } + + return ret; +} + +/** + * @brief USB_FlushTxFifo Flush a Tx FIFO + * @param USBx Selected device + * @param num FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush TX Fifo */ + count = 0U; + USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo Flush Rx FIFO + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush RX Fifo */ + count = 0U; + USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register + * depending the PHY type and the enumeration speed of the device. + * @param USBx Selected device + * @param speed device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @retval Hal status + */ +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG |= speed; + return HAL_OK; +} + +/** + * @brief USB_GetDevSpeed Return the Dev Speed + * @param USBx Selected device + * @retval speed device speed + * This parameter can be one of these values: + * @arg USBD_HS_SPEED: High speed mode + * @arg USBD_FS_SPEED: Full speed mode + */ +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t speed; + uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; + + if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) + { + speed = USBD_HS_SPEED; + } + else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) + { + speed = USBD_FS_SPEED; + } + else + { + speed = 0xFU; + } + + return speed; +} + +/** + * @brief Activate and configure an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + } + else + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; + } + } + return HAL_OK; +} + +/** + * @brief Activate and configure a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DOEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + USB_OTG_DIEPCTL_MPSIZ | + USB_OTG_DIEPCTL_TXFNUM | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_EPTYP); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + USB_OTG_DOEPCTL_MPSIZ | + USB_OTG_DOEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_EPTYP); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + } + + return HAL_OK; +} + +/** + * @brief USB_EPStartXfer : setup and starts a transfer over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + uint16_t pktcnt; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + + if (epnum == 0U) + { + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & + (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); + } + } + + if (dma == 1U) + { + if ((uint32_t)ep->dma_addr != 0U) + { + USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + } + + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + } + else + { + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + if (ep->type != EP_TYPE_ISOC) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) + { + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + } + } + else + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + + (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); + } + } + } + else /* OUT endpoint */ + { + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (epnum == 0U) + { + if (ep->xfer_len > 0U) + { + ep->xfer_len = ep->maxpacket; + } + + /* Store transfer size, for EP0 this is equal to endpoint max packet size */ + ep->xfer_size = ep->maxpacket; + + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + if (ep->xfer_len == 0U) + { + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + ep->xfer_size = ep->maxpacket * pktcnt; + + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; + } + } + + if (dma == 1U) + { + if ((uint32_t)ep->xfer_buff != 0U) + { + USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); + } + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + } + else + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + } + } + /* EP enable */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + } + + return HAL_OK; +} + + +/** + * @brief USB_EPStoptXfer Stop transfer on an EP + * @param USBx usb device instance + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* EP enable, IN data in FIFO */ + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); + } + } + else /* OUT endpoint */ + { + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); + } + } + + return ret; +} + + +/** + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * with the EP/channel + * @param USBx Selected device + * @param src pointer to source buffer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to write + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t *pSrc = src; + uint32_t count32b; + uint32_t i; + + if (dma == 0U) + { + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) + { + USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); + pSrc++; + pSrc++; + pSrc++; + pSrc++; + } + } + + return HAL_OK; +} + +/** + * @brief USB_ReadPacket : read a packet from the RX FIFO + * @param USBx Selected device + * @param dest source pointer + * @param len Number of bytes to read + * @retval pointer to destination buffer + */ +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t *pDest = dest; + uint32_t pData; + uint32_t i; + uint32_t count32b = (uint32_t)len >> 2U; + uint16_t remaining_bytes = len % 4U; + + for (i = 0U; i < count32b; i++) + { + __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); + pDest++; + pDest++; + pDest++; + pDest++; + } + + /* When Number of data is not word aligned, read the remaining byte */ + if (remaining_bytes != 0U) + { + i = 0U; + __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); + + do + { + *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); + i++; + pDest++; + remaining_bytes--; + } while (remaining_bytes != 0U); + } + + return ((void *)pDest); +} + +/** + * @brief USB_EPSetStall : set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + } + + return HAL_OK; +} + +/** + * @brief USB_EPClearStall : Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + else + { + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + return HAL_OK; +} + +/** + * @brief USB_StopDevice : Stop the usb device mode + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) +{ + HAL_StatusTypeDef ret; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Clear Pending interrupt */ + for (i = 0U; i < 15U; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + /* Clear interrupt masks */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + /* Flush the FIFO */ + ret = USB_FlushRxFifo(USBx); + if (ret != HAL_OK) + { + return ret; + } + + ret = USB_FlushTxFifo(USBx, 0x10U); + if (ret != HAL_OK) + { + return ret; + } + + return ret; +} + +/** + * @brief USB_SetDevAddress : Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); + USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; + + return HAL_OK; +} + +/** + * @brief USB_DevConnect : Connect the USB device by enabling Rpu + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; + + return HAL_OK; +} + +/** + * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + + return HAL_OK; +} + +/** + * @brief USB_ReadInterrupts: return the global USB interrupt status + * @param USBx Selected device + * @retval USB Global Interrupt status + */ +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) +{ + uint32_t tmpreg; + + tmpreg = USBx->GINTSTS; + tmpreg &= USBx->GINTMSK; + + return tmpreg; +} + +/** + * @brief USB_ReadChInterrupts: return USB channel interrupt status + * @param USBx Selected device + * @param chnum Channel number + * @retval USB Channel Interrupt status + */ +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_HC(chnum)->HCINT; + tmpreg &= USBx_HC(chnum)->HCINTMSK; + + return tmpreg; +} + +/** + * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status + * @param USBx Selected device + * @retval USB Device OUT EP interrupt status + */ +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xffff0000U) >> 16); +} + +/** + * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status + * @param USBx Selected device + * @retval USB Device IN EP interrupt status + */ +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xFFFFU)); +} + +/** + * @brief Returns Device OUT EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device OUT EP Interrupt register + */ +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; + tmpreg &= USBx_DEVICE->DOEPMSK; + + return tmpreg; +} + +/** + * @brief Returns Device IN EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device IN EP Interrupt register + */ +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + uint32_t msk; + uint32_t emp; + + msk = USBx_DEVICE->DIEPMSK; + emp = USBx_DEVICE->DIEPEMPMSK; + msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; + tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + + return tmpreg; +} + +/** + * @brief USB_ClearInterrupts: clear a USB interrupt + * @param USBx Selected device + * @param interrupt flag + * @retval None + */ +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) +{ + USBx->GINTSTS &= interrupt; +} + +/** + * @brief Returns USB core mode + * @param USBx Selected device + * @retval return core mode : Host or Device + * This parameter can be one of these values: + * 0 : Host + * 1 : Device + */ +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) +{ + return ((USBx->GINTSTS) & 0x1U); +} + +/** + * @brief Activate EP0 for Setup transactions + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* Set the MPS of the IN EP0 to 64 bytes */ + USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; + + return HAL_OK; +} + +/** + * @brief Prepare the EP0 to start the first control setup + * @param USBx Selected device + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @param psetup pointer to setup packet + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + + if (gSNPSiD > USB_OTG_CORE_ID_300A) + { + if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + return HAL_OK; + } + } + + USBx_OUTEP(0U)->DOEPTSIZ = 0U; + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + + if (dma == 1U) + { + USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; + /* EP enable */ + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; + } + + return HAL_OK; +} + +/** + * @brief Reset the USB Core (needed after USB clock settings change) + * @param USBx Selected device + * @retval HAL status + */ +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Core Soft Reset */ + count = 0U; + USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + + return HAL_OK; +} + +/** + * @brief USB_HostInit : Initializes the USB OTG controller registers + * for Host mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { + /* Enable USB PHY pulldown resistors */ + USBx->GCCFG |= USB_OTG_GCCFG_PULLDOWNEN; + } + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { + /* Disable VBUS override */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBVALOVAL | USB_OTG_GCCFG_VBVALEXTOEN); + } + + /* Disable VBUS sensing */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + /* Disable Battery chargin detector */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); + } + else + { + /* Disable Battery chargin detector */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + } + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { + if (cfg.speed == USBH_FSLS_SPEED) + { + /* Force Device Enumeration to FS/LS mode only */ + USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + } + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + } + + /* Make sure the FIFOs are flushed. */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Clear all pending HC Interrupts */ + for (i = 0U; i < cfg.Host_channels; i++) + { + USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK; + USBx_HC(i)->HCINTMSK = 0U; + } + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x200U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); + USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); + } + else +#endif /* defined (USB_OTG_HS) */ + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x80U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); + USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); + } + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + /* Enable interrupts matching to the Host mode ONLY */ + USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ + USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + + return ret; +} + +/** + * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the + * HCFG register on the PHY type and set the right frame interval + * @param USBx Selected device + * @param freq clock frequency + * This parameter can be one of these values: + * HCFG_48_MHZ : Full Speed 48 MHz Clock + * HCFG_6_MHZ : Low Speed 6 MHz Clock + * @retval HAL status + */ +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); + USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; + + if (freq == HCFG_48_MHZ) + { + USBx_HOST->HFIR = HFIR_48_MHZ; + } + else if (freq == HCFG_6_MHZ) + { + USBx_HOST->HFIR = HFIR_6_MHZ; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief USB_OTG_ResetPort : Reset Host Port + * @param USBx Selected device + * @retval HAL status + * @note (1)The application must wait at least 10 ms + * before clearing the reset bit. + */ +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); + HAL_Delay(100U); /* See Note #1 */ + USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + HAL_Delay(10U); + + return HAL_OK; +} + +/** + * @brief USB_DriveVbus : activate or de-activate vbus + * @param state VBUS state + * This parameter can be one of these values: + * 0 : Deactivate VBUS + * 1 : Activate VBUS + * @retval HAL status + */ +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) + { + USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); + } + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) + { + USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); + } + return HAL_OK; +} + +/** + * @brief Return Host Core speed + * @param USBx Selected device + * @retval speed : Host speed + * This parameter can be one of these values: + * @arg HCD_SPEED_HIGH: High speed mode + * @arg HCD_SPEED_FULL: Full speed mode + * @arg HCD_SPEED_LOW: Low speed mode + */ +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); +} + +/** + * @brief Return Host Current Frame number + * @param USBx Selected device + * @retval current frame number + */ +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); +} + +/** + * @brief Initialize a host channel + * @param USBx Selected device + * @param ch_num Channel number + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @arg USB_OTG_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type + * This parameter can be one of these values: + * @arg EP_TYPE_CTRL: Control type + * @arg EP_TYPE_ISOC: Isochronous type + * @arg EP_TYPE_BULK: Bulk type + * @arg EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size + * This parameter can be a value from 0 to 32K + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t HCcharEpDir; + uint32_t HCcharLowSpeed; + uint32_t HostCoreSpeed; + + /* Clear old interrupt conditions for this host channel. */ + USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK; + + /* Enable channel interrupts required for this transfer. */ + switch (ep_type) + { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_NAKM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + else + { +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM; + } +#endif /* defined (USB_OTG_HS) */ + } + break; + + case EP_TYPE_INTR: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_NAKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + + break; + + case EP_TYPE_ISOC: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); + } + break; + + default: + ret = HAL_ERROR; + break; + } + + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + + /* Enable host channel Halt interrupt */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM; + + /* Enable the top level host channel interrupt. */ + USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + + /* Make sure host channel interrupts are enabled. */ + USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; + + /* Program the HCCHAR register */ + if ((epnum & 0x80U) == 0x80U) + { + HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + } + else + { + HCcharEpDir = 0U; + } + + HostCoreSpeed = USB_GetHostSpeed(USBx); + + /* LS device plugged to HUB */ + if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED)) + { + HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + } + else + { + HCcharLowSpeed = 0U; + } + + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | + USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed; + + if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) + { + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + } + + return ret; +} + +/** + * @brief Start a transfer over a host channel + * @param USBx Selected device + * @param hc pointer to host channel structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)hc->ch_num; + __IO uint32_t tmpreg; + uint8_t is_oddframe; + uint16_t len_words; + uint16_t num_packets; + uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT; + +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ + if (dma == 1U) + { + if (((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) && (hc->do_ssplit == 0U)) + { + + USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NAKM); + } + } + else + { + if ((hc->speed == USBH_HS_SPEED) && (hc->do_ping == 1U)) + { + (void)USB_DoPing(USBx, hc->ch_num); + return HAL_OK; + } + } + } +#endif /* defined (USB_OTG_HS) */ + + if (hc->do_ssplit == 1U) + { + /* Set number of packet to 1 for Split transaction */ + num_packets = 1U; + + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + if (hc->ep_type == EP_TYPE_ISOC) + { + if (hc->xfer_len > ISO_SPLT_MPS) + { + /* Isochrone Max Packet Size for Split mode */ + hc->XferSize = hc->max_packet; + hc->xfer_len = hc->XferSize; + + if ((hc->iso_splt_xactPos == HCSPLT_BEGIN) || (hc->iso_splt_xactPos == HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_MIDDLE; + } + else + { + hc->iso_splt_xactPos = HCSPLT_BEGIN; + } + } + else + { + hc->XferSize = hc->xfer_len; + + if ((hc->iso_splt_xactPos != HCSPLT_BEGIN) && (hc->iso_splt_xactPos != HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_FULL; + } + else + { + hc->iso_splt_xactPos = HCSPLT_END; + } + } + } + else + { + if ((dma == 1U) && (hc->xfer_len > hc->max_packet)) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + } + } + } + else + { + /* Compute the expected number of packets associated to the transfer */ + if (hc->xfer_len > 0U) + { + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + + if (num_packets > max_hc_pkt_count) + { + num_packets = max_hc_pkt_count; + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + } + else + { + num_packets = 1U; + } + + /* + * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of + * max_packet size. + */ + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + } + + /* Initialize the HCTSIZn register */ + USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); + + if (dma != 0U) + { + /* xfer_buff MUST be 32-bits aligned */ + USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff; + } + + is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + + if (hc->do_ssplit == 1U) + { + /* Set Hub start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) | + (uint32_t)hc->hub_port_nbr | USB_OTG_HCSPLT_SPLITEN; + + /* unmask ack & nyet for IN/OUT transactions */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NYET); + + if ((hc->do_csplit == 1U) && (hc->ep_is_in == 0U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; + } + + if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) && + (hc->do_csplit == 1U) && (hc->ep_is_in == 1U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + } + + /* Position management for iso out transaction on split mode */ + if ((hc->ep_type == EP_TYPE_ISOC) && (hc->ep_is_in == 0U)) + { + /* Set data payload position */ + switch (hc->iso_splt_xactPos) + { + case HCSPLT_BEGIN: + /* First data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_1; + break; + + case HCSPLT_MIDDLE: + /* Middle data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_Pos; + break; + + case HCSPLT_END: + /* End data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_0; + break; + + case HCSPLT_FULL: + /* Entire data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS; + break; + + default: + break; + } + } + } + else + { + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + } + + /* Set host channel enable */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + + /* make sure to set the correct ep direction */ + if (hc->ep_is_in != 0U) + { + tmpreg |= USB_OTG_HCCHAR_EPDIR; + } + else + { + tmpreg &= ~USB_OTG_HCCHAR_EPDIR; + } + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + + if (dma != 0U) /* dma mode */ + { + return HAL_OK; + } + + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U) && (hc->do_csplit == 0U)) + { + switch (hc->ep_type) + { + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + + /* check if there is enough space in FIFO space */ + if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) + { + /* need to process data in nptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; + } + break; + + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + /* check if there is enough space in FIFO space */ + if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + } + break; + + default: + break; + } + + /* Write packet into the Tx FIFO. */ + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); + } + + return HAL_OK; +} + +/** + * @brief Read all host channel interrupts status + * @param USBx Selected device + * @retval HAL state + */ +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return ((USBx_HOST->HAINT) & 0xFFFFU); +} + +/** + * @brief Halt a host channel + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t hcnum = (uint32_t)hc_num; + __IO uint32_t count = 0U; + uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; + uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; + uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31; + + /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels. + At the end of the next uframe/frame (in the worst case), the core generates a channel halted + and disables the channel automatically. */ + + if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) && + ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR))))) + { + return HAL_OK; + } + + /* Check for space in the request queue to issue the halt. */ + if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) + { + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + + return HAL_OK; +} + +/** + * @brief Initiate Do Ping protocol + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t chnum = (uint32_t)ch_num; + uint32_t num_packets = 1U; + uint32_t tmpreg; + + USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + USB_OTG_HCTSIZ_DOPING; + + /* Set host channel enable */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + + return HAL_OK; +} + +/** + * @brief Stop Host Core + * @param USBx Selected device + * @retval HAL state + */ +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t count = 0U; + uint32_t value; + uint32_t i; + + (void)USB_DisableGlobalInt(USBx); + + /* Flush USB FIFO */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Flush out any leftover queued requests. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value &= ~USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + } + + /* Halt all channels to put them into a known state. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value |= USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + + /* Clear any pending Host interrupts */ + USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK; + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; + + (void)USB_EnableGlobalInt(USBx); + + return ret; +} + +/** + * @brief USB_ActivateRemoteWakeup active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; + } + + return HAL_OK; +} + +/** + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_utils.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_utils.c new file mode 100644 index 00000000000..7439550de4d --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_ll_utils.c @@ -0,0 +1,866 @@ +/** + ****************************************************************************** + * @file stm32h7rsxx_ll_utils.c + * @author MCD Application Team + * @brief UTILS LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_ll_utils.h" +#include "stm32h7rsxx_ll_rcc.h" +#include "stm32h7rsxx_ll_pwr.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7RSxx_LL_Driver + * @{ + */ + +/** @addtogroup UTILS_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Constants + * @{ + */ +#define UTILS_MAX_FREQUENCY_SCALE0 467000000U /*!< Maximum frequency for system clock at power scale 0, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE1 365000000U /*!< Maximum frequency for system clock at power scale 1, in Hz */ + +/* Defines used for PLL range */ +#define UTILS_PLLVCO_INPUT_MIN1 1000000U /*!< Frequency min for the medium range PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MAX1 2000000U /*!< Frequency max for the medium range PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MIN2 2000000U /*!< Frequency min for the wide range PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MAX2 4000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MIN3 4000000U /*!< Frequency min for the wide range PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MAX3 8000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MIN4 8000000U /*!< Frequency min for the wide range PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MAX4 16000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */ + +#define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN 150000000U /*!< Frequency min for the medium range PLLVCO output, in Hz */ +#define UTILS_PLLVCO_WIDE_OUTPUT_MIN 400000000U /*!< Frequency min for the wide range PLLVCO output, in Hz */ +#define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX 420000000U /*!< Frequency max for the medium range PLLVCO output, in Hz */ +#define UTILS_PLLVCO_WIDE_OUTPUT_MAX 1600000000U /*!< Frequency max for the wide range PLLVCO output, in Hz */ + +/* Defines used for HSE range */ +#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ +#define UTILS_HSE_FREQUENCY_MAX 50000000U /*!< Frequency max for HSE frequency, in Hz */ + +/* Defines used for FLASH latency according to HCLK Frequency at */ +/* VOS0 (highest power/frequency) or VOS1 (lowest power/frequency) */ +#define UTILS_SCALE0_LATENCY0_FREQ 40000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 0 */ +#define UTILS_SCALE0_LATENCY1_FREQ 80000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 0 */ +#define UTILS_SCALE0_LATENCY2_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 0 */ +#define UTILS_SCALE0_LATENCY3_FREQ 160000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 0 */ +#define UTILS_SCALE0_LATENCY4_FREQ 200000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 0 */ +#define UTILS_SCALE0_LATENCY5_FREQ 234000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 0 */ + +#define UTILS_SCALE1_LATENCY0_FREQ 36000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */ +#define UTILS_SCALE1_LATENCY1_FREQ 72000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ +#define UTILS_SCALE1_LATENCY2_FREQ 108000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ +#define UTILS_SCALE1_LATENCY3_FREQ 144000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ +#define UTILS_SCALE1_LATENCY4_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ +#define UTILS_SCALE1_LATENCY5_FREQ 183000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Macros + * @{ + */ +#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) + +#define IS_LL_UTILS_AHB_DIV(__VALUE__) (((__VALUE__) == LL_RCC_AHB_DIV_1) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_2) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_4) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_8) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_16) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_64) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_128) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_256) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_512)) + +#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_16)) + +#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_16)) + +#define IS_LL_UTILS_APB4_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB4_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB4_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB4_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB4_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB4_DIV_16)) + +#define IS_LL_UTILS_APB5_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB5_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB5_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB5_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB5_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB5_DIV_16)) + +#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U)) + +#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 420U)) + +#define IS_LL_UTILS_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U)) + +#define IS_LL_UTILS_FRACN_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU) + +#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__, __RANGE__) \ + ((((__RANGE__) == LL_RCC_PLLINPUTRANGE_1_2) && \ + (UTILS_PLLVCO_INPUT_MIN1 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX1)) || \ + (((__RANGE__) == LL_RCC_PLLINPUTRANGE_2_4) && \ + (UTILS_PLLVCO_INPUT_MIN2 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX2)) || \ + (((__RANGE__) == LL_RCC_PLLINPUTRANGE_4_8) && \ + (UTILS_PLLVCO_INPUT_MIN3 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX3)) || \ + (((__RANGE__) == LL_RCC_PLLINPUTRANGE_8_16) && \ + (UTILS_PLLVCO_INPUT_MIN4 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX4))) + +#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__, __RANGE__) \ + ((((__RANGE__) == LL_RCC_PLLVCORANGE_MEDIUM) && \ + (UTILS_PLLVCO_MEDIUM_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_MEDIUM_OUTPUT_MAX)) || \ + (((__RANGE__) == LL_RCC_PLLVCORANGE_WIDE) && \ + (UTILS_PLLVCO_WIDE_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_WIDE_OUTPUT_MAX))) + +#define IS_LL_UTILS_CHECK_VCO_RANGES(__RANGEIN__, __RANGEOUT__) \ + ((((__RANGEIN__) == LL_RCC_PLLINPUTRANGE_1_2) && \ + ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_MEDIUM)) || \ + (((__RANGEIN__) != LL_RCC_PLLINPUTRANGE_1_2) && \ + ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_WIDE))) + +#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) \ + ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0) ? \ + ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE0) : ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1)) + +#define IS_LL_UTILS_HSE_BYPASS(__STATE__) \ + (((__STATE__) == LL_UTILS_HSEBYPASS_ON) || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) + +#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) \ + (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Functions UTILS Private functions + * @{ + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, + const LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +static ErrorStatus UTILS_IsPLLsNotBusy(void); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Exported_Functions + * @{ + */ + +/** @addtogroup UTILS_LL_EF_DELAY + * @{ + */ +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param CPU_Frequency Core frequency in Hz + * @note CPU_Frequency can be calculated thanks to RCC helper macro or function + * @ref LL_RCC_GetSystemClocksFreq + * @retval None + */ +void LL_Init1msTick(uint32_t CPU_Frequency) +{ + /* Use frequency provided in argument */ + LL_InitTick(CPU_Frequency, 1000U); +} + + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on SysTick counter flag + * @note When a RTOS is used, it is recommended to avoid using blocking delay + * and use rather osDelay service. + * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which + * will configure Systick to 1ms + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +void LL_mDelay(uint32_t Delay) +{ + uint32_t count = Delay; + __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + /* Add this code to indicate that local variable is not used */ + ((void)tmp); + + /* Add a period to ensure minimum wait */ + if (count < LL_MAX_DELAY) + { + count++; + } + + while (count != 0U) + { + if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + { + count--; + } + } +} + +/** + * @} + */ + +/** @addtogroup UTILS_EF_SYSTEM + * @brief System Configuration functions + * + @verbatim + =============================================================================== + ##### System Configuration functions ##### + =============================================================================== + [..] + System, AXI, AHB and APB buses clocks configuration + + (+) The maximum frequency of the SYSCLK is 464 MHz and HCLK is 232 MHz. + (+) The maximum frequency of the PCLK1, PCLK2, PCLK4 and PCLK5 is 116 MHz. + @endverbatim + @internal + Depending on the device voltage range, the maximum frequency should be + adapted accordingly: + (++) +---------------------------------------------------------------------------+ + (++) | Wait states | AXI interface clock frequency (MHz) vs Vcore range | + (++) | |-----------------------------------------------------| + (++) | (Latency) | voltage scale 1 | voltage scale 0 | + (++) | | 1.15V - 1.26V | 1.26V - 1.40V | + (++) |---------------------|--------------------------|--------------------------| + (++) | 0WS (1 CPU cycle) | 0 < HCLK <= 36 | 0 < HCLK <= 40 | + (++) |---------------------|--------------------------|--------------------------| + (++) | 1WS (2 CPU cycles) | 36 < HCLK <= 72 | 40 < HCLK <= 80 | + (++) |---------------------|--------------------------|--------------------------| + (++) | 2WS (3 CPU cycles) | 72 < HCLK <= 108 | 80 < HCLK <= 120 | + (++) |---------------------|--------------------------|--------------------------| + (++) | 3WS (4 CPU cycles) | 108 < HCLK <= 144 | 120 < HCLK <= 160 | + (++) |---------------------|--------------------------|--------------------------| + (++) | 4WS (5 CPU cycles) | 144 < HCLK <= 180 | 160 < HCLK <= 200 | + (++) |---------------------|--------------------------|--------------------------| + (++) | 5WS (6 CPU cycles) | 180 < HCLK <= 216 | 200 < HCLK <= 240 | + (++) |---------------------|--------------------------|--------------------------| + (++) | 6WS (7 CPU cycles) | 216 < HCLK <= 252 | | + (++) |---------------------|--------------------------|--------------------------| + + @endinternal + * @{ + */ + +/** + * @brief This function sets directly SystemCoreClock CMSIS variable. + * @note Variable can be calculated also through SystemCoreClockUpdate function. + * @param CPU_Frequency Core frequency in Hz + * @note CPU_Frequency can be calculated thanks to RCC helper macro or function + * @ref LL_RCC_GetSystemClocksFreq + * @retval None + */ +void LL_SetSystemCoreClock(uint32_t CPU_Frequency) +{ + /* SYSCLK clock frequency */ + SystemCoreClock = CPU_Frequency; +} + +/** + * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP) + * - PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLLVCO_input = HSI frequency / PLLM) + * - PLLN: ensure that the VCO output frequency is + * between 150 and 420 MHz (Medium) or + * between 400 to 1600 MHz (Wide) (PLLVCO_output = PLLVCO_input * PLLN) + * - PLLP: ensure that max frequency at 464 MHz is reached (PLLVCO_output / PLLP) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + * + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status; +#ifdef USE_FULL_ASSERT + uint32_t vcoinput_freq; + uint32_t vcooutput_freq; +#endif /* USE_FULL_ASSERT */ + uint32_t pllfreq; + uint32_t hsi_clk; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); + assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); + assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); + assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN)); + + hsi_clk = (HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos)); + + /* Check VCO Input frequency */ +#ifdef USE_FULL_ASSERT + vcoinput_freq = hsi_clk / UTILS_PLLInitStruct->PLLM; + assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input)); +#endif /* USE_FULL_ASSERT */ + + /* Check VCO Output frequency */ +#ifdef USE_FULL_ASSERT + vcooutput_freq = LL_RCC_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, + UTILS_PLLInitStruct->FRACN, 1UL); + assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output)); +#endif /* USE_FULL_ASSERT */ + + /* Check VCO Input ranges */ + assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output)); + + /* Check that no PLL is enabled and thus ready for configuration */ + if (UTILS_IsPLLsNotBusy() == SUCCESS) + { + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(hsi_clk, UTILS_PLLInitStruct); + + /* Enable HSI if not enabled */ + if (LL_RCC_HSI_IsReady() != 1U) + { + LL_RCC_HSI_Enable(); + while (LL_RCC_HSI_IsReady() != 1U) + { + /* Wait for HSI ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL1FRACN_Disable(); + LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSI); + LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input); + LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output); + LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM); + LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN); + LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP); + LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN); + LL_RCC_PLL1FRACN_Enable(); + LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @brief This function configures system clock at maximum frequency with CSI as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = (((CSI frequency / PLLM) * PLLN) / PLLP) + * - PLLM: ensure that the VCO input frequency ranges from 1 to 4 MHz (PLLVCO_input = CSI frequency / PLLM) + * - PLLN: ensure that the VCO output frequency is + * between 150 and 420 MHz (Medium) or + * between 400 to 1600 MHz (Wide) (PLLVCO_output = PLLVCO_input * PLLN) + * - PLLP: ensure that max frequency at 464 MHz is reached (PLLVCO_output / PLLP) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + * + */ +ErrorStatus LL_PLL_ConfigSystemClock_CSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status; +#ifdef USE_FULL_ASSERT + uint32_t vcoinput_freq; + uint32_t vcooutput_freq; +#endif /* USE_FULL_ASSERT */ + uint32_t pllfreq; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); + assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); + assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); + assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN)); + + /* Check VCO Input frequency */ +#ifdef USE_FULL_ASSERT + vcoinput_freq = CSI_VALUE / UTILS_PLLInitStruct->PLLM; + assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input)); +#endif /* USE_FULL_ASSERT */ + + /* Check VCO Output frequency */ +#ifdef USE_FULL_ASSERT + vcooutput_freq = LL_RCC_CalcPLLClockFreq(CSI_VALUE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, + UTILS_PLLInitStruct->FRACN, 1UL); + assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output)); +#endif /* USE_FULL_ASSERT */ + + /* Check VCO Input ranges */ + assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output)); + + /* Check that no PLL is enabled and thus ready for configuration */ + if (UTILS_IsPLLsNotBusy() == SUCCESS) + { + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(CSI_VALUE, UTILS_PLLInitStruct); + + /* Enable CSI if not enabled */ + if (LL_RCC_CSI_IsReady() != 1U) + { + LL_RCC_CSI_Enable(); + while (LL_RCC_CSI_IsReady() != 1U) + { + /* Wait for CSI ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL1FRACN_Disable(); + LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_CSI); + LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input); + LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output); + LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM); + LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN); + LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP); + LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN); + LL_RCC_PLL1FRACN_Enable(); + LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @brief This function configures system clock with HSE as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP) + * - PLLM: ensure that the VCO input frequency ranges from 1 to 4 MHz (PLLVCO_input = CSI frequency / PLLM) + * - PLLN: ensure that the VCO output frequency is + * between 150 and 420 MHz (Medium) or + * between 400 to 1600 MHz (Wide) (PLLVCO_output = PLLVCO_input * PLLN) + * - PLLP: ensure that max frequency at 464 MHz is reached (PLLVCO_output / PLLP) + * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 50000000 + * @param HSEBypass This parameter can be one of the following values: + * @arg @ref LL_UTILS_HSEBYPASS_ON + * @arg @ref LL_UTILS_HSEBYPASS_OFF + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + * + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status; +#ifdef USE_FULL_ASSERT + uint32_t vcoinput_freq; + uint32_t vcooutput_freq; +#endif /* USE_FULL_ASSERT */ + uint32_t pllfreq; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); + assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); + assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); + assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN)); + assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); + assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); + + /* Check VCO Input frequency */ +#ifdef USE_FULL_ASSERT + vcoinput_freq = HSEFrequency / UTILS_PLLInitStruct->PLLM; + assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input)); +#endif /* USE_FULL_ASSERT */ + + /* Check VCO output frequency */ +#ifdef USE_FULL_ASSERT + vcooutput_freq = LL_RCC_CalcPLLClockFreq(HSEFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, + UTILS_PLLInitStruct->FRACN, 1U); + assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output)); +#endif /* USE_FULL_ASSERT */ + + /* Check VCO Input/output ranges compatibility */ + assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output)); + + /* Check that no PLL is enabled and thus ready for configuration */ + if (UTILS_IsPLLsNotBusy() == SUCCESS) + { + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); + + /* Enable HSE if not enabled */ + if (LL_RCC_HSE_IsReady() != 1U) + { + /* Check if need to enable HSE bypass feature or not */ + if (HSEBypass == LL_UTILS_HSEBYPASS_ON) + { + LL_RCC_HSE_EnableBypass(); + } + else + { + LL_RCC_HSE_DisableBypass(); + } + + /* Enable HSE */ + LL_RCC_HSE_Enable(); + while (LL_RCC_HSE_IsReady() != 1U) + { + /* Wait for HSE ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL1FRACN_Disable(); + LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE); + LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input); + LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output); + LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM); + LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN); + LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP); + LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN); + LL_RCC_PLL1FRACN_Enable(); + LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN); + LL_RCC_PLL1FRACN_Enable(); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @} + */ + +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @param HCLK_Frequency HCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) +{ + ErrorStatus status = SUCCESS; + uint32_t timeout; + uint32_t getlatency; + uint32_t latency; + + /* Frequency cannot be equal to 0 */ + if (HCLK_Frequency == 0U) + { + status = ERROR; + } + else + { + if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0) /* Scale 0 */ + { + if ((HCLK_Frequency > UTILS_SCALE0_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY5_FREQ)) + { + latency = LL_FLASH_LATENCY_5; /* 5WS (6 CPU cycles) */ + } + else if ((HCLK_Frequency > UTILS_SCALE0_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY4_FREQ)) + { + latency = LL_FLASH_LATENCY_4; /* 4WS (5 CPU cycles) */ + } + else if ((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ)) + { + latency = LL_FLASH_LATENCY_3; /* 3WS (4 CPU cycles) */ + } + else if ((HCLK_Frequency > UTILS_SCALE0_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY2_FREQ)) + { + latency = LL_FLASH_LATENCY_2; /* 2WS (3 CPU cycles) */ + } + else if ((HCLK_Frequency > UTILS_SCALE0_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY1_FREQ)) + { + latency = LL_FLASH_LATENCY_1; /* 1WS (2 CPU cycles) */ + } + else + { + latency = LL_FLASH_LATENCY_0; /* 0WS (1 CPU cycles) */ + } + } + else /* Scale 1 */ + { + if ((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ)) + { + latency = LL_FLASH_LATENCY_5; /* 5WS (6 CPU cycles) */ + } + else if ((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ)) + { + latency = LL_FLASH_LATENCY_4; /* 4WS (5 CPU cycles) */ + } + else if ((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ)) + { + latency = LL_FLASH_LATENCY_3; /* 3WS (4 CPU cycles) */ + } + else if ((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ)) + { + latency = LL_FLASH_LATENCY_2; /* 2WS (3 CPU cycles) */ + } + else if ((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ)) + { + latency = LL_FLASH_LATENCY_1; /* 1WS (2 CPU cycles) */ + } + else + { + latency = LL_FLASH_LATENCY_0; /* 0WS (1 CPU cycles) */ + } + } + + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + timeout = 2; + do + { + /* Wait for Flash latency to be updated */ + getlatency = LL_FLASH_GetLatency(); + timeout--; + } while ((getlatency != latency) && (timeout > 0U)); + + if (getlatency != latency) + { + status = ERROR; + } + } + + return status; +} + + +/** + * @} + */ + +/** @addtogroup UTILS_LL_Private_Functions + * @{ + */ + + +/** + * @brief Function to Get PLL Output frequency + * @param PLL_InputFrequency PLL input frequency (in Hz) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @retval PLL output frequency (in Hz) + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, + const LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) +{ + uint32_t pllfreq; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); + assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); + assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); + assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN)); + + pllfreq = LL_RCC_CalcPLLClockFreq(PLL_InputFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, + UTILS_PLLInitStruct->FRACN, UTILS_PLLInitStruct->PLLP); + + return pllfreq; +} + +/** + * @brief Check that all PLLs are not busy therefore configuration can be done + * @retval An ErrorStatus enumeration value: + * - SUCCESS: All PLLs are ready so configuration can be done + * - ERROR: One PLL at least is busy + */ +static ErrorStatus UTILS_IsPLLsNotBusy(void) +{ + ErrorStatus status = SUCCESS; + + /* Check if one of the PLL1 is busy */ + if (LL_RCC_PLL1_IsReady() != 0U) + { + /* PLL1 configuration cannot be done */ + status = ERROR; + } + + /* Check if one of the PLL2 is busy */ + if (LL_RCC_PLL2_IsReady() != 0U) + { + /* PLL2 configuration cannot be done */ + status = ERROR; + } + + /* Check if one of the PLL3 is busy */ + if (LL_RCC_PLL3_IsReady() != 0U) + { + /* PLL3 configuration cannot be done */ + status = ERROR; + } + + return status; +} + +/** + * @brief Function to enable PLL and switch system clock to PLL + * @param SYSCLK_Frequency SYSCLK frequency + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: No problem to switch system to PLL + * - ERROR: Problem to switch system to PLL + */ +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t new_sysclk_frequency; + uint32_t new_hclk_frequency; + + assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider)); + assert_param(IS_LL_UTILS_AHB_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); + assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); + assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); + assert_param(IS_LL_UTILS_APB4_DIV(UTILS_ClkInitStruct->APB4CLKDivider)); + assert_param(IS_LL_UTILS_APB5_DIV(UTILS_ClkInitStruct->APB5CLKDivider)); + + /* Calculate the new HCLK frequency */ + new_sysclk_frequency = LL_RCC_CALC_SYSCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->SYSCLKDivider); + new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(new_sysclk_frequency, UTILS_ClkInitStruct->AHBCLKDivider); + + /* Increasing the number of wait states because of higher CPU frequency */ + if (SystemCoreClock < new_sysclk_frequency) + { + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(new_hclk_frequency); + } + + /* Update system clock configuration */ + if (status == SUCCESS) + { + /* Enable PLL */ + LL_RCC_PLL1_Enable(); + while (LL_RCC_PLL1_IsReady() != 1U) + { + /* Wait for PLL ready */ + } + + LL_RCC_PLL1P_Enable(); + + /* Set All APBxPrescaler to the Highest Divider */ + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16); + LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16); + LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16); + LL_RCC_SetAPB5Prescaler(LL_RCC_APB5_DIV_16); + + /* Set SYS prescaler*/ + LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider); + + /* Set AHB prescaler*/ + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + + /* Sysclk activation on the main PLL */ + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1); + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) + { + /* Wait for system clock switch to PLL */ + } + + /* Set APBn prescaler*/ + LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); + LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider); + LL_RCC_SetAPB5Prescaler(UTILS_ClkInitStruct->APB5CLKDivider); + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (SystemCoreClock > new_sysclk_frequency) + { + /* Set FLASH latency to lowest latency */ + status = LL_SetFlashLatency(new_hclk_frequency); + } + + /* Update SystemCoreClock variable */ + if (status == SUCCESS) + { + LL_SetSystemCoreClock(new_sysclk_frequency); + } + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_util_i3c.c b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_util_i3c.c new file mode 100644 index 00000000000..5b8bb8f6f2b --- /dev/null +++ b/bsp/stm32/libraries/STM32H7RSxx_HAL/STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_util_i3c.c @@ -0,0 +1,409 @@ +/** + ********************************************************************************************************************** + * @file stm32h7rsxx_util_i3c.c + * @author MCD Application Team + * @brief This utility help to calculate the different I3C Timing. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7rsxx_util_i3c.h" + +/** @addtogroup STM32H7RSxx_UTIL_Driver + * @{ + */ + +/** @addtogroup UTILITY_I3C + * @{ + */ + +/* Private typedef ---------------------------------------------------------------------------------------------------*/ +/* Private define ----------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_UTIL_Private_Define I3C Utility Private Define + * @{ + */ +#define SEC210PSEC (uint64_t)100000000000 /*!< 10ps, to take two decimal float of ns calculation */ +#define TI3CH_MIN 3200U /*!< Open drain & push pull SCL high min, 32ns */ +#define TI3CH_OD_MAX 4100U /*!< Open drain SCL high max, 41 ns */ +#define TI3CL_OD_MIN 20000U /*!< Open drain SCL low min, 200 ns */ +#define TFMPL_OD_MIN 50000U /*!< Fast Mode Plus Open drain SCL low min, 500 ns */ +#define TFML_OD_MIN 130000U /*!< Fast Mode Open drain SCL low min, 1300 ns */ +#define TFM_MIN 250000U /*!< Fast Mode, period min for ti3cclk, 2.5us */ +#define TSM_MIN 1000000U /*!< Standard Mode, period min for ti3cclk, 10us */ +#define TI3C_CAS_MIN 3840U /*!< Time SCL after START min, 38.4 ns */ +#define TCAPA 35000U /*!< Capacitor effect Value measure on Nucleo around 350ns */ +/** + * @} + */ + +/* Private macro -----------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_UTIL_Private_Macro I3C Utility Private Macro + * @{ + */ +#define DIV_ROUND_CLOSEST(x, d) (((x) + ((d) / 2U)) / (d)) +/** + * @} + */ + +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup I3C_UTIL_Exported_Functions I3C Utility Exported Functions + * @{ + */ + +/** @defgroup I3C_UTIL_EF_Computation Computation + * @{ + */ +/** + * @brief Calculate the I3C Controller timing according current I3C clock source and required I3C bus clock. + * @param pInputTiming : [IN] Pointer to an I3C_CtrlTimingTypeDef structure that contains + * the required parameter for I3C timing computation. + * @param pOutputConfig : [OUT] Pointer to an LL_I3C_CtrlBusConfTypeDef structure that contains + * the configuration information for the specified I3C. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Timing calculation successfully + * - ERROR: Parameters or timing calculation error + */ +ErrorStatus I3C_CtrlTimingComputation(const I3C_CtrlTimingTypeDef *pInputTiming, + LL_I3C_CtrlBusConfTypeDef *pOutputConfig) +{ + ErrorStatus status = SUCCESS; + + /* MIPI Standard constants */ + /* I3C: Open drain & push pull SCL high min, tDIG_H & tDIG_H_MIXED: 32 ns */ + uint32_t ti3ch_min = TI3CH_MIN; + + /* I3C: Open drain SCL high max, t_HIGH: 41 ns */ + uint32_t ti3ch_od_max = TI3CH_OD_MAX; + + /* I3C: Open drain SCL high max, tHIGH: 41 ns (Ti3ch_od_max= 410) + I3C (pure bus): Open drain SCL low min, tLOW_OD: 200 ns */ + uint32_t ti3cl_od_min = TI3CL_OD_MIN; + + /* I3C (mixed bus): Open drain SCL low min, + tLOW: 500 ns (FM+ I2C on the bus) + tLOW: 1300 ns (FM I2C on the bus) */ + uint32_t tfmpl_od_min = TFMPL_OD_MIN; + uint32_t tfml_od_min = TFML_OD_MIN; + + /* I2C: min ti3cclk + fSCL: 1 MHz (FM+) + fSCL: 100 kHz (SM) */ + uint32_t tfm_min = TFM_MIN; + uint32_t tsm_min = TSM_MIN; + + /* I3C: time SCL after START min, Tcas: 38,4 ns */ + uint32_t ti3c_cas_min = TI3C_CAS_MIN; + + /* Period Clock source */ + uint32_t ti3cclk = 0U; + + /* I3C: Push pull period */ + uint32_t ti3c_pp_min = 0U; + + /* I2C: Open drain period */ + uint32_t ti2c_od_min = 0U; + + /* Time for SDA rise to 70% VDD from GND, capacitor effect */ + /* Value measure on Nucleo around 350ns */ + uint32_t tcapa = TCAPA; + + /* Compute variable */ + uint32_t sclhi3c; + uint32_t scllpp; + uint32_t scllod; + uint32_t sclhi2c; + uint32_t oneus; + uint32_t free; + uint32_t sdahold; + + /* Verify Parameters */ + if (((pInputTiming->clockSrcFreq == 0U) || (pInputTiming->i3cPPFreq == 0U)) && + (pInputTiming->busType == I3C_PURE_I3C_BUS)) + { + status = ERROR; + } + + if (((pInputTiming->clockSrcFreq == 0U) || (pInputTiming->i3cPPFreq == 0U) || (pInputTiming->i2cODFreq == 0U)) && + (pInputTiming->busType == I3C_MIXED_BUS)) + { + status = ERROR; + } + + if (status == SUCCESS) + { + /* Period Clock source */ + ti3cclk = (uint32_t)((SEC210PSEC + ((uint64_t)pInputTiming->clockSrcFreq / (uint64_t)2)) / + (uint64_t)pInputTiming->clockSrcFreq); + + if ((pInputTiming->dutyCycle > 50U) || (ti3cclk == 0U)) + { + status = ERROR; + } + } + + if ((status == SUCCESS) && (ti3cclk != 0U)) + { + /* I3C: Push pull period */ + ti3c_pp_min = (uint32_t)((SEC210PSEC + ((uint64_t)pInputTiming->i3cPPFreq / (uint64_t)2)) / + (uint64_t)pInputTiming->i3cPPFreq); + + /* I2C: Open drain period */ + ti2c_od_min = (uint32_t)((SEC210PSEC + ((uint64_t)pInputTiming->i2cODFreq / (uint64_t)2)) / + (uint64_t)pInputTiming->i2cODFreq); + + if ((pInputTiming->busType != I3C_PURE_I3C_BUS) && (ti2c_od_min > tsm_min)) + { + status = ERROR; + } + } + + /* SCL Computation */ + if ((status == SUCCESS) && (ti3cclk != 0U)) + { + /* I3C SCL high level (push-pull & open drain) */ + if (pInputTiming->busType == I3C_PURE_I3C_BUS) + { + sclhi3c = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(ti3c_pp_min * pInputTiming->dutyCycle, ti3cclk), 100U) - 1U; + + /* Check if sclhi3c < ti3ch_min, in that case calculate sclhi3c based on ti3ch_min */ + if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min) + { + sclhi3c = DIV_ROUND_CLOSEST(ti3ch_min, ti3cclk) - 1U; + + /* Check if sclhi3c < ti3ch_min */ + if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min) + { + sclhi3c += 1U; + } + + scllpp = DIV_ROUND_CLOSEST(ti3c_pp_min, ti3cclk) - (sclhi3c + 1U) - 1U; + } + else + { + sclhi3c = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(ti3c_pp_min * pInputTiming->dutyCycle, ti3cclk), 100U) - 1U; + + /* Check if sclhi3c < ti3ch_min */ + if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min) + { + sclhi3c += 1U; + } + + scllpp = DIV_ROUND_CLOSEST((ti3c_pp_min - ((sclhi3c + 1U) * ti3cclk) + (ti3cclk / 2U)), ti3cclk) - 1U; + } + + } + else + { + /* Warning: (sclhi3c + 1) * ti3cclk > Ti3ch_od_max expected */ + sclhi3c = DIV_ROUND_CLOSEST(ti3ch_od_max, ti3cclk) - 1U; + + if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min) + { + sclhi3c += 1U; + } + else if (((sclhi3c + 1U) * ti3cclk) > ti3ch_od_max) + { + sclhi3c = (ti3ch_od_max / ti3cclk); + } + else + { + /* Do nothing, keep sclhi3c as previously calculated */ + } + + /* I3C SCL low level (push-pull) */ + /* tscllpp = (scllpp + 1) x ti3cclk */ + scllpp = DIV_ROUND_CLOSEST((ti3c_pp_min - ((sclhi3c + 1U) * ti3cclk)), ti3cclk) - 1U; + } + + /* Check if scllpp is superior at (ti3c_pp_min + 1/2 clock source cycle) */ + /* Goal is to choice the scllpp approach lowest, to have a value frequency highest approach as possible */ + uint32_t ideal_scllpp = (ti3c_pp_min - ((sclhi3c + 1U) * ti3cclk)); + if (((scllpp + 1U) * ti3cclk) >= (ideal_scllpp + (ti3cclk / 2U) + 1U)) + { + scllpp -= 1U; + } + + /* Check if scllpp + sclhi3c is inferior at (ti3c_pp_min + 1/2 clock source cycle) */ + /* Goal is to increase the scllpp, to have a value frequency not out of the clock request */ + if (((scllpp + sclhi3c + 1U + 1U) * ti3cclk) < (ideal_scllpp + (ti3cclk / 2U) + 1U)) + { + scllpp += 1U; + } + + /* I3C SCL low level (pure I3C bus) */ + if (pInputTiming->busType == I3C_PURE_I3C_BUS) + { + if (ti3c_pp_min < ti3cl_od_min) + { + scllod = DIV_ROUND_CLOSEST(ti3cl_od_min, ti3cclk) - 1U; + + if (((scllod + 1U) * ti3cclk) < ti3cl_od_min) + { + scllod += 1U; + } + } + else + { + scllod = scllpp; + } + + /* Verify that SCL Open drain Low duration is superior as SDA rise time 70% */ + if (((scllod + 1U) * ti3cclk) < tcapa) + { + scllod = DIV_ROUND_CLOSEST(tcapa, ti3cclk) + 1U; + } + + sclhi2c = 0U; /* I2C SCL not used in pure I3C bus */ + } + /* SCL low level on mixed bus (open-drain) */ + /* I2C SCL high level (mixed bus with I2C) */ + else + { + scllod = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(ti2c_od_min * (100U - pInputTiming->dutyCycle), + ti3cclk), 100U) - 1U; + + /* Mix Bus Fast Mode plus */ + if (ti2c_od_min < tfm_min) + { + if (((scllod + 1U) * ti3cclk) < tfmpl_od_min) + { + scllod = DIV_ROUND_CLOSEST(tfmpl_od_min, ti3cclk) - 1U; + } + } + /* Mix Bus Fast Mode */ + else + { + if (((scllod + 1U) * ti3cclk) < tfml_od_min) + { + scllod = DIV_ROUND_CLOSEST(tfml_od_min, ti3cclk) - 1U; + } + } + + sclhi2c = DIV_ROUND_CLOSEST((ti2c_od_min - ((scllod + 1U) * ti3cclk)), ti3cclk) - 1U; + } + + /* Clock After Start computation */ + + /* I3C pure bus: (Tcas + tcapa)/2 */ + if (pInputTiming->busType == I3C_PURE_I3C_BUS) + { + free = DIV_ROUND_CLOSEST((ti3c_cas_min + tcapa), (2U * ti3cclk)) + 1U; + } + /* I3C, I2C mixed: (scllod + tcapa)/2 */ + else + { + free = DIV_ROUND_CLOSEST((((scllod + 1U) * ti3cclk) + tcapa), (2U * ti3cclk)); + } + + /* One cycle hold time addition */ + /* By default 1/2 cycle: must be > 3 ns */ + if (ti3cclk > 600U) + { + sdahold = 0U; + } + else + { + sdahold = 1U; + } + + /* 1 microsecond reference */ + oneus = DIV_ROUND_CLOSEST(100000U, ti3cclk) - 2U; + + if ((scllpp > 0xFFU) || (sclhi3c > 0xFFU) || (scllod > 0xFFU) || (sclhi2c > 0xFFU) || + (free > 0xFFU) || (oneus > 0xFFU)) + { + /* Case of value is over 8bits, issue may be due to clocksource have a rate too high for bus clock request */ + /* Update the return status */ + status = ERROR; + } + else + { + /* SCL configuration */ + pOutputConfig->SCLPPLowDuration = (uint8_t)scllpp; + pOutputConfig->SCLI3CHighDuration = (uint8_t)sclhi3c; + pOutputConfig->SCLODLowDuration = (uint8_t)scllod; + pOutputConfig->SCLI2CHighDuration = (uint8_t)sclhi2c; + + /* Free, Idle and SDA hold time configuration */ + pOutputConfig->BusFreeDuration = (uint8_t)free; + pOutputConfig->BusIdleDuration = (uint8_t)oneus; + pOutputConfig->SDAHoldTime = (uint32_t)(sdahold << I3C_TIMINGR1_SDA_HD_Pos); + } + } + + return status; +} + +/** + * @brief Calculate the I3C Controller timing according current I3C clock source and required I3C bus clock. + * @param pInputTiming : [IN] Pointer to an I3C_TgtTimingTypeDef structure that contains + * the required parameter for I3C timing computation. + * @param pOutputConfig : [OUT] Pointer to an LL_I3C_TgtBusConfTypeDef structure that contains + * the configuration information for the specified I3C. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Timing calculation successfully + * - ERROR: Parameters or timing calculation error + */ +ErrorStatus I3C_TgtTimingComputation(const I3C_TgtTimingTypeDef *pInputTiming, + LL_I3C_TgtBusConfTypeDef *pOutputConfig) +{ + ErrorStatus status = SUCCESS; + uint32_t oneus; + uint32_t ti3cclk = 0U; + + /* Verify Parameters */ + if (pInputTiming->clockSrcFreq == 0U) + { + status = ERROR; + } + + if (status == SUCCESS) + { + /* Period Clock source */ + ti3cclk = (uint32_t)((SEC210PSEC + ((uint64_t)pInputTiming->clockSrcFreq / (uint64_t)2)) / + (uint64_t)pInputTiming->clockSrcFreq); + + /* Verify Parameters */ + if (ti3cclk == 0U) + { + status = ERROR; + } + } + + if ((status == SUCCESS) && (ti3cclk != 0U)) + { + /* 1 microsecond reference */ + oneus = DIV_ROUND_CLOSEST(100000U, ti3cclk) - 2U; + + /* Bus available time configuration */ + pOutputConfig->BusAvailableDuration = (uint8_t)oneus; + } + + return status; +} +/** + * @} + */ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/stm32f072-st-nucleo/applications/arduino_pinout/SConscript b/bsp/stm32/stm32f072-st-nucleo/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32f072-st-nucleo/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32f072-st-nucleo/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32f072-st-nucleo/project.ewp b/bsp/stm32/stm32f072-st-nucleo/project.ewp index 6c1a0abec0d..d7404e79784 100644 --- a/bsp/stm32/stm32f072-st-nucleo/project.ewp +++ b/bsp/stm32/stm32f072-st-nucleo/project.ewp @@ -2194,6 +2194,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f072-st-nucleo/project.uvproj b/bsp/stm32/stm32f072-st-nucleo/project.uvproj index c2921571ac4..41a7565ae83 100644 --- a/bsp/stm32/stm32f072-st-nucleo/project.uvproj +++ b/bsp/stm32/stm32f072-st-nucleo/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f072-st-nucleo/project.uvprojx b/bsp/stm32/stm32f072-st-nucleo/project.uvprojx index ae14208526b..af19330c34b 100644 --- a/bsp/stm32/stm32f072-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32f072-st-nucleo/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f091-st-nucleo/project.ewp b/bsp/stm32/stm32f091-st-nucleo/project.ewp index ab592a1c9f9..e9dafcbed21 100644 --- a/bsp/stm32/stm32f091-st-nucleo/project.ewp +++ b/bsp/stm32/stm32f091-st-nucleo/project.ewp @@ -2154,6 +2154,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f091-st-nucleo/project.uvprojx b/bsp/stm32/stm32f091-st-nucleo/project.uvprojx index bd406003b3f..33ea4c4d161 100644 --- a/bsp/stm32/stm32f091-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32f091-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-100ask-mini/.config b/bsp/stm32/stm32f103-100ask-mini/.config index a84aaa05492..a605c8ae5d0 100644 --- a/bsp/stm32/stm32f103-100ask-mini/.config +++ b/bsp/stm32/stm32f103-100ask-mini/.config @@ -77,7 +77,7 @@ CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_SCHED_THREAD_CTX is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x50100 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 diff --git a/bsp/stm32/stm32f103-100ask-mini/project.ewp b/bsp/stm32/stm32f103-100ask-mini/project.ewp index cebdbb38dbd..ee266687c94 100644 --- a/bsp/stm32/stm32f103-100ask-mini/project.ewp +++ b/bsp/stm32/stm32f103-100ask-mini/project.ewp @@ -225,7 +225,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT STM32F103xB __RTTHREAD__ USE_HAL_DRIVER @@ -1295,7 +1294,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT STM32F103xB __RTTHREAD__ USE_HAL_DRIVER @@ -2202,6 +2200,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f103-100ask-mini/project.uvprojx b/bsp/stm32/stm32f103-100ask-mini/project.uvprojx index c4b6e8a31d5..fd85054949a 100644 --- a/bsp/stm32/stm32f103-100ask-mini/project.uvprojx +++ b/bsp/stm32/stm32f103-100ask-mini/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-100ask-mini/rtconfig.h b/bsp/stm32/stm32f103-100ask-mini/rtconfig.h index d77c6e5ad29..747237711e0 100644 --- a/bsp/stm32/stm32f103-100ask-mini/rtconfig.h +++ b/bsp/stm32/stm32f103-100ask-mini/rtconfig.h @@ -48,7 +48,7 @@ #define RT_USING_DEVICE #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x50100 #define RT_BACKTRACE_LEVEL_MAX_NR 32 #define RT_USING_HW_ATOMIC diff --git a/bsp/stm32/stm32f103-100ask-pro/.config b/bsp/stm32/stm32f103-100ask-pro/.config index eee9305f87d..cfea4947c3c 100644 --- a/bsp/stm32/stm32f103-100ask-pro/.config +++ b/bsp/stm32/stm32f103-100ask-pro/.config @@ -77,7 +77,7 @@ CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_SCHED_THREAD_CTX is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x50100 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 diff --git a/bsp/stm32/stm32f103-100ask-pro/project.ewp b/bsp/stm32/stm32f103-100ask-pro/project.ewp index 333d09f3de2..d74c61d8c68 100644 --- a/bsp/stm32/stm32f103-100ask-pro/project.ewp +++ b/bsp/stm32/stm32f103-100ask-pro/project.ewp @@ -225,7 +225,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT STM32F103xE __RTTHREAD__ USE_HAL_DRIVER @@ -1295,7 +1294,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT STM32F103xE __RTTHREAD__ USE_HAL_DRIVER @@ -2202,6 +2200,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f103-100ask-pro/project.uvprojx b/bsp/stm32/stm32f103-100ask-pro/project.uvprojx index aab8dd625f8..08857955bdd 100644 --- a/bsp/stm32/stm32f103-100ask-pro/project.uvprojx +++ b/bsp/stm32/stm32f103-100ask-pro/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-100ask-pro/rtconfig.h b/bsp/stm32/stm32f103-100ask-pro/rtconfig.h index 0397869e081..0e170d1b614 100644 --- a/bsp/stm32/stm32f103-100ask-pro/rtconfig.h +++ b/bsp/stm32/stm32f103-100ask-pro/rtconfig.h @@ -48,7 +48,7 @@ #define RT_USING_DEVICE #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x50100 #define RT_BACKTRACE_LEVEL_MAX_NR 32 #define RT_USING_HW_ATOMIC diff --git a/bsp/stm32/stm32f103-atk-nano/project.ewp b/bsp/stm32/stm32f103-atk-nano/project.ewp index 72c737e9fed..dab57cdf581 100644 --- a/bsp/stm32/stm32f103-atk-nano/project.ewp +++ b/bsp/stm32/stm32f103-atk-nano/project.ewp @@ -2154,6 +2154,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f103-atk-nano/project.uvproj b/bsp/stm32/stm32f103-atk-nano/project.uvproj index 99d7fd552ae..8e3e2b55b85 100644 --- a/bsp/stm32/stm32f103-atk-nano/project.uvproj +++ b/bsp/stm32/stm32f103-atk-nano/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-atk-nano/project.uvprojx b/bsp/stm32/stm32f103-atk-nano/project.uvprojx index ba017211f28..a2ce75135ce 100644 --- a/bsp/stm32/stm32f103-atk-nano/project.uvprojx +++ b/bsp/stm32/stm32f103-atk-nano/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-atk-warshipv3/project.ewp b/bsp/stm32/stm32f103-atk-warshipv3/project.ewp index 6a8195d3313..ee0b81bfddc 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/project.ewp +++ b/bsp/stm32/stm32f103-atk-warshipv3/project.ewp @@ -2154,6 +2154,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f103-atk-warshipv3/project.uvproj b/bsp/stm32/stm32f103-atk-warshipv3/project.uvproj index 18e1785d990..66d4b907bab 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/project.uvproj +++ b/bsp/stm32/stm32f103-atk-warshipv3/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-atk-warshipv3/project.uvprojx b/bsp/stm32/stm32f103-atk-warshipv3/project.uvprojx index 715df3b44d8..7e32a0de20d 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/project.uvprojx +++ b/bsp/stm32/stm32f103-atk-warshipv3/project.uvprojx @@ -511,6 +511,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-blue-pill/applications/arduino_pinout/SConscript b/bsp/stm32/stm32f103-blue-pill/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32f103-blue-pill/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32f103-blue-pill/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32f103-blue-pill/project.ewp b/bsp/stm32/stm32f103-blue-pill/project.ewp index 4d0af016a4c..9746518aafb 100644 --- a/bsp/stm32/stm32f103-blue-pill/project.ewp +++ b/bsp/stm32/stm32f103-blue-pill/project.ewp @@ -2152,6 +2152,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f103-blue-pill/project.uvproj b/bsp/stm32/stm32f103-blue-pill/project.uvproj index 90236ebc1a8..e202663598c 100644 --- a/bsp/stm32/stm32f103-blue-pill/project.uvproj +++ b/bsp/stm32/stm32f103-blue-pill/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-blue-pill/project.uvprojx b/bsp/stm32/stm32f103-blue-pill/project.uvprojx index 29c95ca8291..7a5a491aacd 100644 --- a/bsp/stm32/stm32f103-blue-pill/project.uvprojx +++ b/bsp/stm32/stm32f103-blue-pill/project.uvprojx @@ -483,6 +483,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-dofly-M3S/project.ewp b/bsp/stm32/stm32f103-dofly-M3S/project.ewp index 0a5a416ec83..df393bd7e5e 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/project.ewp +++ b/bsp/stm32/stm32f103-dofly-M3S/project.ewp @@ -2157,6 +2157,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f103-dofly-M3S/project.uvproj b/bsp/stm32/stm32f103-dofly-M3S/project.uvproj index d9da22030f2..e1b03a9ac61 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/project.uvproj +++ b/bsp/stm32/stm32f103-dofly-M3S/project.uvproj @@ -530,6 +530,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-dofly-M3S/project.uvprojx b/bsp/stm32/stm32f103-dofly-M3S/project.uvprojx index f5a8051f81a..de27478bbb3 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/project.uvprojx +++ b/bsp/stm32/stm32f103-dofly-M3S/project.uvprojx @@ -380,16 +380,16 @@ Applications - nrf24l01_init.c + main.c 1 - applications\nrf24l01_init.c + applications\main.c - main.c + nrf24l01_init.c 1 - applications\main.c + applications\nrf24l01_init.c @@ -492,6 +492,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-dofly-lyc8/project.ewp b/bsp/stm32/stm32f103-dofly-lyc8/project.ewp index b7af62cb77d..7a80d8736ae 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/project.ewp +++ b/bsp/stm32/stm32f103-dofly-lyc8/project.ewp @@ -2178,6 +2178,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f103-dofly-lyc8/project.uvproj b/bsp/stm32/stm32f103-dofly-lyc8/project.uvproj index 5eafabade1b..efdd41fc7b7 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/project.uvproj +++ b/bsp/stm32/stm32f103-dofly-lyc8/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-dofly-lyc8/project.uvprojx b/bsp/stm32/stm32f103-dofly-lyc8/project.uvprojx index 3c5f3c1d9f7..e4b6f44c679 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/project.uvprojx +++ b/bsp/stm32/stm32f103-dofly-lyc8/project.uvprojx @@ -480,6 +480,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c index 6d472b14043..e3e04bf6192 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c @@ -11,7 +11,8 @@ #include #include "spi_flash.h" #include "spi_flash_sfud.h" -#include "drv_spi.h" +#include +#include #if defined(BSP_USING_SPI_FLASH) static int rt_hw_spi_flash_init(void) diff --git a/bsp/stm32/stm32f103-fire-arbitrary/project.ewp b/bsp/stm32/stm32f103-fire-arbitrary/project.ewp index 07843e62ed7..72e9f01b6f7 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/project.ewp +++ b/bsp/stm32/stm32f103-fire-arbitrary/project.ewp @@ -2154,6 +2154,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f103-fire-arbitrary/project.uvproj b/bsp/stm32/stm32f103-fire-arbitrary/project.uvproj index 8df4641e0a5..7e392d5cdee 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/project.uvproj +++ b/bsp/stm32/stm32f103-fire-arbitrary/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-fire-arbitrary/project.uvprojx b/bsp/stm32/stm32f103-fire-arbitrary/project.uvprojx index 70907397580..c168322d1ac 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/project.uvprojx +++ b/bsp/stm32/stm32f103-fire-arbitrary/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/project.ewp b/bsp/stm32/stm32f103-gizwits-gokitv21/project.ewp index fc302d02fa2..ea33c2481f8 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/project.ewp +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/project.ewp @@ -2194,6 +2194,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/project.uvproj b/bsp/stm32/stm32f103-gizwits-gokitv21/project.uvproj index 42b0ca52449..115a261f23c 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/project.uvproj +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/project.uvprojx b/bsp/stm32/stm32f103-gizwits-gokitv21/project.uvprojx index 69966af2957..6d10511fe90 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/project.uvprojx +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-hw100k-ibox/project.ewp b/bsp/stm32/stm32f103-hw100k-ibox/project.ewp index f82e9b1a637..7a16de3ef3a 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/project.ewp +++ b/bsp/stm32/stm32f103-hw100k-ibox/project.ewp @@ -2228,6 +2228,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f103-hw100k-ibox/project.uvproj b/bsp/stm32/stm32f103-hw100k-ibox/project.uvproj index 860721af958..b39cfe61a0f 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/project.uvproj +++ b/bsp/stm32/stm32f103-hw100k-ibox/project.uvproj @@ -522,6 +522,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-hw100k-ibox/project.uvprojx b/bsp/stm32/stm32f103-hw100k-ibox/project.uvprojx index 117eb4320b2..09ce794dfe6 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/project.uvprojx +++ b/bsp/stm32/stm32f103-hw100k-ibox/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-onenet-nbiot/project.ewp b/bsp/stm32/stm32f103-onenet-nbiot/project.ewp index 66bdd67fb25..46559658b54 100644 --- a/bsp/stm32/stm32f103-onenet-nbiot/project.ewp +++ b/bsp/stm32/stm32f103-onenet-nbiot/project.ewp @@ -2152,6 +2152,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f103-onenet-nbiot/project.uvproj b/bsp/stm32/stm32f103-onenet-nbiot/project.uvproj index 90cf0c51cb2..12481ef0fc3 100644 --- a/bsp/stm32/stm32f103-onenet-nbiot/project.uvproj +++ b/bsp/stm32/stm32f103-onenet-nbiot/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-onenet-nbiot/project.uvprojx b/bsp/stm32/stm32f103-onenet-nbiot/project.uvprojx index 0f8785717d4..6b481f8f1ad 100644 --- a/bsp/stm32/stm32f103-onenet-nbiot/project.uvprojx +++ b/bsp/stm32/stm32f103-onenet-nbiot/project.uvprojx @@ -511,6 +511,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-yf-ufun/project.ewp b/bsp/stm32/stm32f103-yf-ufun/project.ewp index df6624ff6a1..c5a2a6cbe61 100644 --- a/bsp/stm32/stm32f103-yf-ufun/project.ewp +++ b/bsp/stm32/stm32f103-yf-ufun/project.ewp @@ -2194,6 +2194,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f103-yf-ufun/project.uvproj b/bsp/stm32/stm32f103-yf-ufun/project.uvproj index 079dd7fe30e..6c36d13724e 100644 --- a/bsp/stm32/stm32f103-yf-ufun/project.uvproj +++ b/bsp/stm32/stm32f103-yf-ufun/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-yf-ufun/project.uvprojx b/bsp/stm32/stm32f103-yf-ufun/project.uvprojx index a950f19da3f..29fe87009c4 100644 --- a/bsp/stm32/stm32f103-yf-ufun/project.uvprojx +++ b/bsp/stm32/stm32f103-yf-ufun/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-ys-f1pro/project.ewp b/bsp/stm32/stm32f103-ys-f1pro/project.ewp index cdb0053fa11..24677ea62ec 100644 --- a/bsp/stm32/stm32f103-ys-f1pro/project.ewp +++ b/bsp/stm32/stm32f103-ys-f1pro/project.ewp @@ -2152,6 +2152,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f103-ys-f1pro/project.uvproj b/bsp/stm32/stm32f103-ys-f1pro/project.uvproj index d3d1cc113ec..beb90839ed6 100644 --- a/bsp/stm32/stm32f103-ys-f1pro/project.uvproj +++ b/bsp/stm32/stm32f103-ys-f1pro/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f103-ys-f1pro/project.uvprojx b/bsp/stm32/stm32f103-ys-f1pro/project.uvprojx index e469efdc74f..699009fa573 100644 --- a/bsp/stm32/stm32f103-ys-f1pro/project.uvprojx +++ b/bsp/stm32/stm32f103-ys-f1pro/project.uvprojx @@ -511,6 +511,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f107-uc-eval/project.ewp b/bsp/stm32/stm32f107-uc-eval/project.ewp index 743bcc7b6f8..b3411abb390 100644 --- a/bsp/stm32/stm32f107-uc-eval/project.ewp +++ b/bsp/stm32/stm32f107-uc-eval/project.ewp @@ -2152,6 +2152,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f107-uc-eval/project.uvproj b/bsp/stm32/stm32f107-uc-eval/project.uvproj index c273a01aada..297d7a16c41 100644 --- a/bsp/stm32/stm32f107-uc-eval/project.uvproj +++ b/bsp/stm32/stm32f107-uc-eval/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f107-uc-eval/project.uvprojx b/bsp/stm32/stm32f107-uc-eval/project.uvprojx index cac96635839..a65a78a1bae 100644 --- a/bsp/stm32/stm32f107-uc-eval/project.uvprojx +++ b/bsp/stm32/stm32f107-uc-eval/project.uvprojx @@ -483,6 +483,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f207-st-nucleo/project.ewp b/bsp/stm32/stm32f207-st-nucleo/project.ewp index 878e342fc8f..1f38af940f7 100644 --- a/bsp/stm32/stm32f207-st-nucleo/project.ewp +++ b/bsp/stm32/stm32f207-st-nucleo/project.ewp @@ -2226,6 +2226,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f207-st-nucleo/project.uvproj b/bsp/stm32/stm32f207-st-nucleo/project.uvproj index e0e10bf9bee..236b488b545 100644 --- a/bsp/stm32/stm32f207-st-nucleo/project.uvproj +++ b/bsp/stm32/stm32f207-st-nucleo/project.uvproj @@ -524,6 +524,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f207-st-nucleo/project.uvprojx b/bsp/stm32/stm32f207-st-nucleo/project.uvprojx index 3b6dba5778d..3c911069b65 100644 --- a/bsp/stm32/stm32f207-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32f207-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f302-st-nucleo/project.ewp b/bsp/stm32/stm32f302-st-nucleo/project.ewp index 982939e85c4..b4409a9eb63 100644 --- a/bsp/stm32/stm32f302-st-nucleo/project.ewp +++ b/bsp/stm32/stm32f302-st-nucleo/project.ewp @@ -2151,6 +2151,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f302-st-nucleo/project.uvprojx b/bsp/stm32/stm32f302-st-nucleo/project.uvprojx index ad2bcc32eb8..120c16f8886 100644 --- a/bsp/stm32/stm32f302-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32f302-st-nucleo/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f334-st-nucleo/project.ewp b/bsp/stm32/stm32f334-st-nucleo/project.ewp index 43aa088cab4..e19a71990f6 100644 --- a/bsp/stm32/stm32f334-st-nucleo/project.ewp +++ b/bsp/stm32/stm32f334-st-nucleo/project.ewp @@ -2151,6 +2151,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f334-st-nucleo/project.uvprojx b/bsp/stm32/stm32f334-st-nucleo/project.uvprojx index 286d410dae8..39698f0c47f 100644 --- a/bsp/stm32/stm32f334-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32f334-st-nucleo/project.uvprojx @@ -487,6 +487,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f401-st-nucleo/applications/arduino_pinout/SConscript b/bsp/stm32/stm32f401-st-nucleo/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32f401-st-nucleo/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32f401-st-nucleo/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32f401-st-nucleo/project.ewp b/bsp/stm32/stm32f401-st-nucleo/project.ewp index caed3f5361e..9bdd128b605 100644 --- a/bsp/stm32/stm32f401-st-nucleo/project.ewp +++ b/bsp/stm32/stm32f401-st-nucleo/project.ewp @@ -2160,6 +2160,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f401-st-nucleo/project.uvprojx b/bsp/stm32/stm32f401-st-nucleo/project.uvprojx index 29dd5029c19..e364dcdfaad 100644 --- a/bsp/stm32/stm32f401-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32f401-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f401-weact-blackpill/applications/arduino_pinout/SConscript b/bsp/stm32/stm32f401-weact-blackpill/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32f401-weact-blackpill/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32f401-weact-blackpill/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32f401-weact-blackpill/project.ewp b/bsp/stm32/stm32f401-weact-blackpill/project.ewp index 5396ea39f8e..dc7247be8ed 100644 --- a/bsp/stm32/stm32f401-weact-blackpill/project.ewp +++ b/bsp/stm32/stm32f401-weact-blackpill/project.ewp @@ -2151,6 +2151,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f401-weact-blackpill/project.uvproj b/bsp/stm32/stm32f401-weact-blackpill/project.uvproj index 4448a2dab73..a80ef68cab3 100644 --- a/bsp/stm32/stm32f401-weact-blackpill/project.uvproj +++ b/bsp/stm32/stm32f401-weact-blackpill/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f401-weact-blackpill/project.uvprojx b/bsp/stm32/stm32f401-weact-blackpill/project.uvprojx index fb5a808590e..fb886cdf01b 100644 --- a/bsp/stm32/stm32f401-weact-blackpill/project.uvprojx +++ b/bsp/stm32/stm32f401-weact-blackpill/project.uvprojx @@ -487,6 +487,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/project.ewp b/bsp/stm32/stm32f405-smdz-breadfruit/project.ewp index 696f133e1a6..4b485e74dfc 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/project.ewp +++ b/bsp/stm32/stm32f405-smdz-breadfruit/project.ewp @@ -2151,6 +2151,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/project.uvproj b/bsp/stm32/stm32f405-smdz-breadfruit/project.uvproj index 1ded2111f3b..9cd85bfd3e1 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/project.uvproj +++ b/bsp/stm32/stm32f405-smdz-breadfruit/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/project.uvprojx b/bsp/stm32/stm32f405-smdz-breadfruit/project.uvprojx index d1a1bcb537c..ffc686e57ca 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/project.uvprojx +++ b/bsp/stm32/stm32f405-smdz-breadfruit/project.uvprojx @@ -510,6 +510,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f405zg-mini-template/project.ewp b/bsp/stm32/stm32f405zg-mini-template/project.ewp index 4a37ddbe47e..d677a297b9a 100644 --- a/bsp/stm32/stm32f405zg-mini-template/project.ewp +++ b/bsp/stm32/stm32f405zg-mini-template/project.ewp @@ -2194,6 +2194,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f405zg-mini-template/project.uvprojx b/bsp/stm32/stm32f405zg-mini-template/project.uvprojx index c98cddd216e..e74b87833c0 100644 --- a/bsp/stm32/stm32f405zg-mini-template/project.uvprojx +++ b/bsp/stm32/stm32f405zg-mini-template/project.uvprojx @@ -487,6 +487,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f407-armfly-v5/project.ewp b/bsp/stm32/stm32f407-armfly-v5/project.ewp index bea1d875216..23d2418aebe 100644 --- a/bsp/stm32/stm32f407-armfly-v5/project.ewp +++ b/bsp/stm32/stm32f407-armfly-v5/project.ewp @@ -2153,6 +2153,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f407-armfly-v5/project.uvproj b/bsp/stm32/stm32f407-armfly-v5/project.uvproj index eddd28baa78..8eeac62815b 100644 --- a/bsp/stm32/stm32f407-armfly-v5/project.uvproj +++ b/bsp/stm32/stm32f407-armfly-v5/project.uvproj @@ -524,6 +524,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f407-armfly-v5/project.uvprojx b/bsp/stm32/stm32f407-armfly-v5/project.uvprojx index 7fc7ada788d..e22f3eb78bf 100644 --- a/bsp/stm32/stm32f407-armfly-v5/project.uvprojx +++ b/bsp/stm32/stm32f407-armfly-v5/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f407-atk-explorer/project.ewp b/bsp/stm32/stm32f407-atk-explorer/project.ewp index 6f8e6b78d28..9163b63cbfc 100644 --- a/bsp/stm32/stm32f407-atk-explorer/project.ewp +++ b/bsp/stm32/stm32f407-atk-explorer/project.ewp @@ -2162,6 +2162,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f407-atk-explorer/project.uvproj b/bsp/stm32/stm32f407-atk-explorer/project.uvproj index 319fbe33313..fb0bf8c41de 100644 --- a/bsp/stm32/stm32f407-atk-explorer/project.uvproj +++ b/bsp/stm32/stm32f407-atk-explorer/project.uvproj @@ -565,6 +565,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f407-atk-explorer/project.uvprojx b/bsp/stm32/stm32f407-atk-explorer/project.uvprojx index 8ca7f5935d5..2e3903e13b6 100644 --- a/bsp/stm32/stm32f407-atk-explorer/project.uvprojx +++ b/bsp/stm32/stm32f407-atk-explorer/project.uvprojx @@ -541,6 +541,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f407-lckfb-skystar/.ci/attachconfig/nano.attach b/bsp/stm32/stm32f407-lckfb-skystar/.ci/attachconfig/nano.attach new file mode 100644 index 00000000000..f1ad05b2391 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/.ci/attachconfig/nano.attach @@ -0,0 +1,2 @@ +# scons: --strict +CONFIG_RT_USING_NANO=y diff --git a/bsp/stm32/stm32f407-lckfb-skystar/.config b/bsp/stm32/stm32f407-lckfb-skystar/.config new file mode 100644 index 00000000000..24e63ca4d69 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/.config @@ -0,0 +1,1141 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# +CONFIG_SOC_STM32F407ZG=y +CONFIG_BOARD_STM32F407_SPARK=y + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50100 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# CONFIG_RT_USING_CACHE is not set +CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +# CONFIG_RT_DFS_ELM_USE_EXFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_ROMFS_USER_ROOT is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_GET_IRQ_PRIORITY is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32F4=y + +# +# Hardware Drivers Config +# + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_SPI_FLASH is not set +# CONFIG_BSP_USING_FS is not set +# CONFIG_BSP_USING_FAL is not set + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_UART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_SOFT_SPI is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_ONBOARD_PM is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_USBD is not set +# CONFIG_BSP_USING_PULSE_ENCODER is not set +# CONFIG_BSP_USING_EXT_FMC_IO is not set +# CONFIG_BSP_USING_FMC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_UDID is not set diff --git a/bsp/stm32/stm32f407-lckfb-skystar/.gitignore b/bsp/stm32/stm32f407-lckfb-skystar/.gitignore new file mode 100644 index 00000000000..7221bde019d --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/stm32/stm32f407-lckfb-skystar/Kconfig b/bsp/stm32/stm32f407-lckfb-skystar/Kconfig new file mode 100644 index 00000000000..60fa08a560f --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/Kconfig @@ -0,0 +1,35 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config SOC_STM32F407ZG + bool + select SOC_SERIES_STM32F4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config BOARD_STM32F407_SPARK + bool + default y + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" + +if !RT_USING_NANO +source "board/Kconfig" +endif diff --git a/bsp/stm32/stm32f407-lckfb-skystar/README.md b/bsp/stm32/stm32f407-lckfb-skystar/README.md new file mode 100644 index 00000000000..020d407d5e7 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/README.md @@ -0,0 +1,97 @@ +# STM32F407-lckfb-skystar立创天空星开发板BSP说明 + +## 简介 + +该开发板是由立创开发板精心打造的一款高性价比的开发工具，**软硬件全开源**。设计上充分考虑了与多种100脚封装的单片机的兼容性。这种设计使得它不仅适用于特定的芯片，还能够适配市场上多种不同厂家生产的100脚微控制器，极大地提高了适用范围和灵活性。该BSP适配立创梁山派·天空星开发板的主控芯片为STM32F407VET6。 + +为了最大限度的方便开发者和爱好者，该核心板通过排针将所有可用的IO（输入/输出）引脚都引出，这样大家就可以轻松地连接各种外部模块和设备，无需进行复杂的焊接工作。这一特点特别适合那些需要快速原型制作和迭代的场合，如学生电子竞赛、创客活动以及个人DIY项目。 + +此外，这款核心板的设计考虑到了大家在电子竞赛中对于稳定性和可靠性的需求，以及在小型项目开发中对低成本的追求。具体请看硬件设计手册。 + +![[(lckfb.com)](https://lckfb.com/project/detail/lckfb-lspi-skystar-stm32f407vet6-lite?param=baseInfo)](figures/board.png) + +## 资料罗列： + +* [硬件开源地址](https://oshwhub.com/li-chuang-kai-fa-ban/li-chuang-liang-shan-pai-tian-kong-xing-kai-fa-ban) +* [硬件文档](https://lceda001.feishu.cn/wiki/D4cqwUkiTi6723knO2cczSThnYb) +* [入门手册](https://lceda001.feishu.cn/wiki/Zawdwg0laig3Qnk2XuxcKrQRn2g) +* [模块移植手册](https://lceda001.feishu.cn/wiki/GySKwn3jMitXbAkhX0GcDjtBnQd) +* [购买地址](https://lckfb.com/project/detail/lckfb-lspi-skystar-stm32f407vet6-lite?param=baseInfo) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :----------- | :----------: | :------------------------------ | +| GPIO | 支持 | PA0, PA1... ---> PIN: 0, 1...81 | +| UART | 支持 | UART0 - UART6 | +| I2C | 支持 | I2C1 | +| SPI | 支持 | SPI0 -  SPI2 | +| ADC | 支持 | ADC0 - ADC2 | +| TF CARD | 支持 | SDIO | +| SPI FLASH | 支持 | SPI1 | +| **扩展模块** | **支持情况** | **备注** | +| 暂无 | 暂不支持 | 暂不支持 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + +### 快速上手 + +本 BSP 为开发者提供 MDK4、MDK5 工程，并且支持 GCC 开发环境，也可使用RT-Thread Studio开发。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，使用USB转TTL模块连接PA9(MCU TX)和PA10(MCU RX)，上电。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 CMSIS-DAP 仿真器下载程序，在通过 CMSIS-DAP 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，LED 闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Apr 13 2024 11:59:40 + 2006 - 2024 Copyright by RT-Thread team + +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口0的功能，如果需使用高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +## 注意事项 + +暂无 + +## 联系人信息 + +维护人: + +- [yuanzihao](https://github.com/zihao-yuan/), 邮箱：[y@yzh.email](mailto:y@yzh.email) \ No newline at end of file diff --git a/bsp/stm32/stm32f407-lckfb-skystar/SConscript b/bsp/stm32/stm32f407-lckfb-skystar/SConscript new file mode 100644 index 00000000000..20f7689c53c --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32f407-lckfb-skystar/SConstruct b/bsp/stm32/stm32f407-lckfb-skystar/SConstruct new file mode 100644 index 00000000000..b321fd9f022 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/SConstruct @@ -0,0 +1,59 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +stm32_library = 'STM32F4xx_HAL' +rtconfig.BSP_LIBRARY_TYPE = stm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'), variant_dir='build/libraries/'+stm32_library, duplicate=0)) +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'),variant_dir='build/libraries/'+'HAL_Drivers', duplicate=0)) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32f407-lckfb-skystar/applications/SConscript b/bsp/stm32/stm32f407-lckfb-skystar/applications/SConscript new file mode 100644 index 00000000000..03feb2016a7 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/applications/SConscript @@ -0,0 +1,18 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +if GetDepend(['PKG_USING_RTDUINO']) and not GetDepend(['RTDUINO_NO_SETUP_LOOP']): + src += ['arduino_main.cpp'] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_main.cpp b/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_main.cpp new file mode 100644 index 00000000000..1335fec08c1 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_main.cpp @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 Li ZhenHong first version + */ + +#include + +void setup(void) +{ + /* put your setup code here, to run once: */ + Serial.begin(); +} + +void loop(void) +{ + /* put your main code here, to run repeatedly: */ + Serial.println("Hello Arduino!"); + delay(800); +} diff --git a/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_pinout/README.md b/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_pinout/README.md new file mode 100644 index 00000000000..330a1089ffa --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_pinout/README.md @@ -0,0 +1,69 @@ +# stm32f407-rt-spark 开发板的Arduino生态兼容说明 + +## 1 RTduino - RT-Thread的Arduino生态兼容层 + +stm32f407-rt-spark 开发板已经完整适配了[RTduino软件包](https://github.com/RTduino/RTduino)，即RT-Thread的Arduino生态兼容层。用户可以按照Arduino的编程习惯来操作该BSP，并且可以使用大量Arduino社区丰富的库，是对RT-Thread生态的极大增强。更多信息，请参见[RTduino软件包说明文档](https://github.com/RTduino/RTduino)。 + +### 1.1 如何开启针对本BSP的Arduino生态兼容层 + +Env 工具下敲入 menuconfig 命令，或者 RT-Thread Studio IDE 下选择 RT-Thread Settings： + +```Kconfig +Hardware Drivers Config ---> + Onboard Peripheral Drivers ---> + [*] Compatible with Arduino Ecosystem (RTduino) +``` + +## 2 Arduino引脚排布 + +更多引脚布局相关信息参见 [pins_arduino.c](pins_arduino.c) 和 [pins_arduino.h](pins_arduino.h)。 + +![Rt-spark_Rtduino_Pin_Map.drawio](Rt-spark_Rtduino_Pin_Map.drawio.png) + +| Arduino引脚编号 | STM32引脚编号 | 5V容忍 | 备注 | +| ------------------- | --------- | ---- | ------------------------------------------------------------------------- | +| 0 (D0) | GET_PIN(A, 10) | 是 | Serial-RX,默认被RT-Thread的UART设备框架uart1接管 | +| 1 (D1) | GET_PIN(A, 9) | 是 | Serial-TX,默认被RT-Thread的UART设备框架uart1接管 | +| 2 (D2) | GET_PIN(A, 8) | 是 | | +| 3 (D3) | GET_PIN(B, 10) | 是 | PWM2-CH3,默认被RT-Thread的PWM设备框架pwm2接管 | +| 4 (D4) | GET_PIN(A, 1) | 是 | | +| 5 (D5) | GET_PIN(B, 14) | 是 | | +| 6 (D6) | GET_PIN(B, 11) | 是 | PWM2-CH4,默认被RT-Thread的PWM设备框架pwm2接管 | +| 7 (D7) | GET_PIN(B, 15) | 是 | | +| 8 (D8) | GET_PIN(F, 15) | 是 | | +| 9 (D9) | GET_PIN(E, 11) | 是 | PWM1-CH2,默认被RT-Thread的PWM设备框架pwm1接管 | +| 10 (D10) | GET_PIN(E, 13) | 是 | PWM1-CH3,默认被RT-Thread的PWM设备框架pwm1接管 | +| 11 (D11) | GET_PIN(D, 12) | 是 | PWM4-CH1,默认被RT-Thread的PWM设备框架pwm4接管 | +| 12 (D12) | GET_PIN(D, 10) | 是 | | +| 13 (D13) | GET_PIN(D, 8) | 是 | | +| 14 (D14) | GET_PIN(E, 14) | 是 | | +| 15 (D15) | GET_PIN(E, 12) | 是 | | +| 16 (D16) | GET_PIN(E, 15) | 是 | | +| 17 (D17) | GET_PIN(D, 9) | 是 | | +| 18 (D18) | GET_PIN(G, 2) | 是 | | +| 19 (D19) | GET_PIN(B, 2) | 是 | | +| 20 (D20) | GET_PIN(G, 0) | 是 | | +| 21 (D21) | GET_PIN(A, 0) | 是 | | +| 22 (D22) | GET_PIN(G, 5) | 是 | SSPI1-SCK,默认被RT-Thread的SPI设备框架sspi1接管| +| 23 (D23) | GET_PIN(G, 3) | 是 | SSPI1-MISO,默认被RT-Thread的SPI设备框架sspi1接管 | +| 24 (D24) | GET_PIN(G, 1) | 是 | SSPI1-MOSI,默认被RT-Thread的SPI设备框架sspi1接管 | +| 25 (D25) | GET_PIN(G, 7) | 是 | I2C1-SCL,默认被RT-Thread的I2C设备框架i2c1接管 | +| 26 (D26) | GET_PIN(D, 7) | 是 | I2C1-SDA,默认被RT-Thread的I2C设备框架i2c1接管 | +| 27 (D27) | GET_PIN(B, 6) | 是 | I2C2-SCL,默认被RT-Thread的I2C设备框架i2c2接管 | +| 28 (D28) | GET_PIN(B, 7) | 是 | I2C2-SDA,默认被RT-Thread的I2C设备框架i2c2接管 | +| 29 (D29) | GET_PIN(G, 6) | 是 | | +| 30 (D30) | GET_PIN(G, 4) | 是 | | +| 31 (D31) | GET_PIN(A, 2) | 是 | Serial2-TX,默认被RT-Thread的UART设备框架uart2接管 | +| 32 (D32) | GET_PIN(A, 3) | 是 | Serial2-RX,默认被RT-Thread的UART设备框架uart2接管 | +| 33 (D33) | GET_PIN(F, 12) | 是 | 板载用户R_LED | +| 34 (D34) | GET_PIN(F, 11) | 是 | 板载用户B_LED | +| 35 (D35) | GET_PIN(B, 0) | 是 | 板载蜂鸣器 | +| 36 (D36) | GET_PIN(C, 5) | 是 | 板载按键KEY_UP | +| 37 (D37) | GET_PIN(C, 1) | 是 | 板载按键KEY_DOWM | +| 38 (D38) | GET_PIN(C, 0) | 是 | 板载按键KEY_LEFT | +| 39 (D39) | GET_PIN(C, 4) | 是 | 板载按键KEY_RIGHT | +| 40 (A0) | GET_PIN(F, 6) | 是 | ADC3-CH4,默认被RT-Thread的ADC设备框架adc3接管 | +| 41 (A1) | GET_PIN(F, 7) | 是 | ADC3-CH5,默认被RT-Thread的ADC设备框架adc3接管 | +| 42 (A2) | GET_PIN(F, 4) | 是 | ADC3-CH14,默认被RT-Thread的ADC设备框架adc3接管 | +| 43 (A3) | GET_PIN(F, 5) | 是 | ADC3-CH15,默认被RT-Thread的ADC设备框架adc3接管 | +| 44 (DAC0) | GET_PIN(A, 4) | 否 | DAC1-CH1,默认被RT-Thread的DAC设备框架dac1接管 | diff --git a/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_pinout/Rt-spark_Rtduino_Pin_Map.drawio.png b/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_pinout/Rt-spark_Rtduino_Pin_Map.drawio.png new file mode 100644 index 00000000000..b84867a5366 Binary files /dev/null and b/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_pinout/Rt-spark_Rtduino_Pin_Map.drawio.png differ diff --git a/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_pinout/SConscript b/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_pinout/SConscript new file mode 100644 index 00000000000..25399290275 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_pinout/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +inc = [cwd] + +group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) + +Return('group') diff --git a/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_pinout/pins_arduino.c b/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_pinout/pins_arduino.c new file mode 100644 index 00000000000..88fed11beba --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_pinout/pins_arduino.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-10 Li ZhenHong first version + */ + +#include +#include "pins_arduino.h" +#include + +/* + * {Arduino Pin, RT-Thread Pin [, Device Name, Channel]} + * [] means optional + * Digital pins must NOT give the device name and channel. + * Analog pins MUST give the device name and channel(ADC, PWM or DAC). + * Arduino Pin must keep in sequence. + */ +const pin_map_t pin_map_table[]= +{ + {D0, GET_PIN(A, 10), "uart1"}, /* Serial-RX */ + {D1, GET_PIN(A, 9), "uart1"}, /* Serial-TX */ + {D2, GET_PIN(A, 8)}, + {D3, GET_PIN(B, 10), "pwm2", 3}, /* PWM */ + {D4, GET_PIN(A, 1)}, + {D5, GET_PIN(B, 14)}, + {D6, GET_PIN(B, 11), "pwm2", 4}, /* PWM */ + {D7, GET_PIN(B, 15)}, + {D8, GET_PIN(F, 15)}, + {D9, GET_PIN(E, 11), "pwm1", 2}, /* PWM */ + {D10, GET_PIN(E, 13), "pwm1", 3}, /* PWM */ + {D11, GET_PIN(D, 12), "pwm4", 1}, /* PWM */ + {D12, GET_PIN(D, 10)}, + {D13, GET_PIN(D, 8)}, + {D14, GET_PIN(E, 14)}, + {D15, GET_PIN(E, 12)}, + {D16, GET_PIN(E, 15)}, + {D17, GET_PIN(D, 9)}, + {D18, GET_PIN(G, 2)}, + {D19, GET_PIN(B, 2)}, + {D20, GET_PIN(G, 0)}, + {D21, GET_PIN(A, 0)}, + {D22, GET_PIN(G, 5), "sspi1"}, /* SOFT-SPI-SCK */ + {D23, GET_PIN(G, 3), "sspi1"}, /* SOFT-SPI-SCK */ + {D24, GET_PIN(G, 1), "sspi1"}, /* SOFT-SPI-SCK */ + {D25, GET_PIN(G, 7), "i2c4"}, /* I2C-SCL (Wire) */ + {D26, GET_PIN(D, 7), "i2c4"}, /* I2C-SDA (Wire) */ + {D27, GET_PIN(B, 6), "i2c5"}, /* I2C-SCL (Wire) */ + {D28, GET_PIN(B, 7), "i2c5"}, /* I2C-SDA (Wire) */ + {D29, GET_PIN(G, 6)}, /* SPI-SS */ + {D30, GET_PIN(G, 4)}, + {D31, GET_PIN(A, 2), "uart2"}, /* Serial2-TX */ + {D32, GET_PIN(A, 3), "uart2"}, /* Serial2-RX */ + {D33, GET_PIN(F, 12)}, /* On-Board R_LED */ + {D34, GET_PIN(F, 11)}, /* On-Board B_LED */ + {D35, GET_PIN(B, 0)}, /* On_Board Buzzer */ + {D36, GET_PIN(C, 5)}, /* On-Board KEY_UP */ + {D37, GET_PIN(C, 1)}, /* On-Board KEY_DOWM */ + {D38, GET_PIN(C, 0)}, /* On-Board KEY_LEFT */ + {D39, GET_PIN(C, 4)}, /* On-Board KEY_RIGHT */ + {A0, GET_PIN(F, 6), "adc3", 4}, /* ADC */ + {A1, GET_PIN(F, 7), "adc3", 5}, /* ADC */ + {A2, GET_PIN(F, 4), "adc3", 14}, /* ADC */ + {A3, GET_PIN(F, 5), "adc3", 15}, /* ADC */ + {DAC0, GET_PIN(A, 4), "dac1", 1}, /* DAC */ +}; diff --git a/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_pinout/pins_arduino.h b/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_pinout/pins_arduino.h new file mode 100644 index 00000000000..12b7d608853 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/applications/arduino_pinout/pins_arduino.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-07 Li ZhenHong first version + */ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +/* pins alias. Must keep in sequence */ +#define D0 (0) +#define D1 (1) +#define D2 (2) +#define D3 (3) +#define D4 (4) +#define D5 (5) +#define D6 (6) +#define D7 (7) +#define D8 (8) +#define D9 (9) +#define D10 (10) +#define D11 (11) +#define D12 (12) +#define D13 (13) +#define D14 (14) +#define D15 (15) +#define D16 (16) +#define D17 (17) +#define D18 (18) +#define D19 (19) +#define D20 (20) +#define D21 (21) +#define D22 (22) +#define D23 (23) +#define D24 (24) +#define D25 (25) +#define D26 (26) +#define D27 (27) +#define D28 (28) +#define D29 (29) +#define D30 (30) +#define D31 (31) +#define D32 (32) +#define D33 (33) +#define D34 (34) +#define D35 (35) +#define D36 (36) +#define D37 (37) +#define D38 (38) +#define D39 (39) +#define A0 (40) +#define A1 (41) +#define A2 (42) +#define A3 (43) +#define DAC0 (44) + +#define RTDUINO_PIN_MAX_LIMIT DAC0 /* pin number max limit check */ + +#define F_CPU 168000000L /* CPU:168MHz */ + +#define LED_BUILTIN D33 /* Default Built-in LED */ + +/* i2c4 : PD.7-SDA PG.7-SCL */ +#define RTDUINO_DEFAULT_IIC_BUS_NAME "i2c4" + +#define SS D32 /* Chip select pin of default spi */ +/* sspi1 : PG.5-SCK PG.3-MISO PG.1-MOSI */ +#define RTDUINO_DEFAULT_SPI_BUS_NAME "sspi1" + +/* Serial2(uart2) : PA.2-TX PA.3-RX */ +#define RTDUINO_SERIAL2_DEVICE_NAME "uart2" + +#endif /* Pins_Arduino_h */ diff --git a/bsp/stm32/stm32f407-lckfb-skystar/applications/main.c b/bsp/stm32/stm32f407-lckfb-skystar/applications/main.c new file mode 100644 index 00000000000..dd98dc75359 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/applications/main.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-07-06 Supperthomas first version + * 2023-12-03 Meco Man support nano version + * 2024-04-13 yuanzihao adaptation for SkyStar STM32F407 version + */ + +#include +#include +#include +#ifndef RT_USING_NANO +#include +#endif /* RT_USING_NANO */ + +#define GPIO_LED GET_PIN(B, 2) + +int main(void) +{ + rt_pin_mode(GPIO_LED, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(GPIO_LED, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(GPIO_LED, PIN_LOW); + rt_thread_mdelay(500); + } +} diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/.ignore_format.yml b/bsp/stm32/stm32f407-lckfb-skystar/board/.ignore_format.yml new file mode 100644 index 00000000000..0d7f3e360c6 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- CubeMX_Config diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/.mxproject new file mode 100644 index 00000000000..0573df56713 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/.mxproject @@ -0,0 +1,14 @@ +[PreviousLibFiles] +LibFiles=Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_sdmmc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_sd.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usart.h;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_sdmmc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_sd.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usart.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[PreviousUsedKeilFiles] +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;..\Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;..\\Src\system_stm32f4xx.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;..\Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;..\\Src\system_stm32f4xx.c;;; +HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; +CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +HeaderPath=..\Inc +HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; +SourcePath=..\Src +SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; + diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/CubeMX_Config.ioc new file mode 100644 index 00000000000..c26a2c3374f --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/CubeMX_Config.ioc @@ -0,0 +1,169 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.CPN=STM32F407VET6 +Mcu.Family=STM32F4 +Mcu.IP0=NVIC +Mcu.IP1=RCC +Mcu.IP2=SDIO +Mcu.IP3=SPI1 +Mcu.IP4=SYS +Mcu.IP5=USART1 +Mcu.IPNb=6 +Mcu.Name=STM32F407V(E-G)Tx +Mcu.Package=LQFP100 +Mcu.Pin0=PH0-OSC_IN +Mcu.Pin1=PH1-OSC_OUT +Mcu.Pin10=PA13 +Mcu.Pin11=PA14 +Mcu.Pin12=PC10 +Mcu.Pin13=PC11 +Mcu.Pin14=PC12 +Mcu.Pin15=PD2 +Mcu.Pin16=PD3 +Mcu.Pin17=PB3 +Mcu.Pin18=VP_SYS_VS_Systick +Mcu.Pin2=PA4 +Mcu.Pin3=PA5 +Mcu.Pin4=PA6 +Mcu.Pin5=PA7 +Mcu.Pin6=PC8 +Mcu.Pin7=PC9 +Mcu.Pin8=PA9 +Mcu.Pin9=PA10 +Mcu.PinsNb=19 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F407VETx +MxCube.Version=6.11.0 +MxDb.Version=DB.6.0.110 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA13.Mode=Trace_Asynchronous_SW +PA13.Signal=SYS_JTMS-SWDIO +PA14.Mode=Trace_Asynchronous_SW +PA14.Signal=SYS_JTCK-SWCLK +PA4.GPIOParameters=GPIO_Label +PA4.GPIO_Label=SPI_FLASH_CS +PA4.Locked=true +PA4.Signal=GPIO_Output +PA5.Mode=Full_Duplex_Master +PA5.Signal=SPI1_SCK +PA6.Mode=Full_Duplex_Master +PA6.Signal=SPI1_MISO +PA7.Mode=Full_Duplex_Master +PA7.Signal=SPI1_MOSI +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB3.Mode=Trace_Asynchronous_SW +PB3.Signal=SYS_JTDO-SWO +PC10.Mode=SD_4_bits_Wide_bus +PC10.Signal=SDIO_D2 +PC11.Mode=SD_4_bits_Wide_bus +PC11.Signal=SDIO_D3 +PC12.Mode=SD_4_bits_Wide_bus +PC12.Signal=SDIO_CK +PC8.Mode=SD_4_bits_Wide_bus +PC8.Signal=SDIO_D0 +PC9.Mode=SD_4_bits_Wide_bus +PC9.Signal=SDIO_D1 +PD2.Mode=SD_4_bits_Wide_bus +PD2.Signal=SDIO_CMD +PD3.GPIOParameters=GPIO_Label +PD3.GPIO_Label=SD_CARD_DET +PD3.Locked=true +PD3.Signal=GPIO_Input +PH0-OSC_IN.Mode=HSE-External-Oscillator +PH0-OSC_IN.Signal=RCC_OSC_IN +PH1-OSC_OUT.Mode=HSE-External-Oscillator +PH1-OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F407VETx +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.28.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=CubeMX_Config.ioc +ProjectManager.ProjectName=CubeMX_Config +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5 +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART1_UART_Init-USART1-false-HAL-true +RCC.48MHZClocksFreq_Value=48000000 +RCC.AHBFreq_Value=168000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=42000000 +RCC.APB1TimFreq_Value=84000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=84000000 +RCC.APB2TimFreq_Value=168000000 +RCC.CortexFreq_Value=168000000 +RCC.EthernetFreq_Value=168000000 +RCC.FCLKCortexFreq_Value=168000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=168000000 +RCC.HSE_VALUE=8000000 +RCC.HSI_VALUE=16000000 +RCC.I2SClocksFreq_Value=192000000 +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=168000000 +RCC.PLLCLKFreq_Value=168000000 +RCC.PLLM=8 +RCC.PLLN=168 +RCC.PLLQ=7 +RCC.PLLQCLKFreq_Value=48000000 +RCC.RTCFreq_Value=32000 +RCC.RTCHSEDivFreq_Value=4000000 +RCC.SYSCLKFreq_VALUE=168000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.VCOI2SOutputFreq_Value=384000000 +RCC.VCOInputFreq_Value=2000000 +RCC.VCOOutputFreq_Value=336000000 +RCC.VcooutputI2S=192000000 +SPI1.CalculateBaudRate=42.0 MBits/s +SPI1.Direction=SPI_DIRECTION_2LINES +SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI1.Mode=SPI_MODE_MASTER +SPI1.VirtualType=VM_MASTER +USART1.IPParameters=VirtualMode +USART1.VirtualMode=VM_ASYNC +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Inc/main.h new file mode 100644 index 00000000000..32d24c769ff --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Inc/main.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define SPI_FLASH_CS_Pin GPIO_PIN_4 +#define SPI_FLASH_CS_GPIO_Port GPIOA +#define SD_CARD_DET_Pin GPIO_PIN_3 +#define SD_CARD_DET_GPIO_Port GPIOD + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h new file mode 100644 index 00000000000..f2eb8c43721 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -0,0 +1,495 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f4xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_ETH_LEGACY_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED +/* #define HAL_MMC_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_FMPSMBUS_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External audio frequency in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ +#define USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U /* FMPSMBUS register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY 0x000000FFU +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY 0x00000FFFU + +#define PHY_READ_TO 0x0000FFFFU +#define PHY_WRITE_TO 0x0000FFFFU + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_eth_legacy.h" +#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_FMPSMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_fmpsmbus.h" +#endif /* HAL_FMPSMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Inc/stm32f4xx_it.h b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Inc/stm32f4xx_it.h new file mode 100644 index 00000000000..9716374d880 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Inc/stm32f4xx_it.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_IT_H +#define __STM32F4xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_IT_H */ diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Src/main.c new file mode 100644 index 00000000000..636bb0455f7 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Src/main.c @@ -0,0 +1,340 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +SD_HandleTypeDef hsd; + +SPI_HandleTypeDef hspi1; + +UART_HandleTypeDef huart1; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART1_UART_Init(void); +static void MX_SDIO_SD_Init(void); +static void MX_SPI1_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART1_UART_Init(); + MX_SDIO_SD_Init(); + MX_SPI1_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 168; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief SDIO Initialization Function + * @param None + * @retval None + */ +static void MX_SDIO_SD_Init(void) +{ + + /* USER CODE BEGIN SDIO_Init 0 */ + + /* USER CODE END SDIO_Init 0 */ + + /* USER CODE BEGIN SDIO_Init 1 */ + + /* USER CODE END SDIO_Init 1 */ + hsd.Instance = SDIO; + hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + hsd.Init.BusWide = SDIO_BUS_WIDE_4B; + hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + hsd.Init.ClockDiv = 0; + if (HAL_SD_Init(&hsd) != HAL_OK) + { + Error_Handler(); + } + if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SDIO_Init 2 */ + + /* USER CODE END SDIO_Init 2 */ + +} + +/** + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + + /* USER CODE BEGIN SPI1_Init 0 */ + + /* USER CODE END SPI1_Init 0 */ + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; +/* USER CODE BEGIN MX_GPIO_Init_1 */ +/* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(SPI_FLASH_CS_GPIO_Port, SPI_FLASH_CS_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin : SPI_FLASH_CS_Pin */ + GPIO_InitStruct.Pin = SPI_FLASH_CS_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(SPI_FLASH_CS_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : SD_CARD_DET_Pin */ + GPIO_InitStruct.Pin = SD_CARD_DET_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(SD_CARD_DET_GPIO_Port, &GPIO_InitStruct); + +/* USER CODE BEGIN MX_GPIO_Init_2 */ +/* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c new file mode 100644 index 00000000000..54b9ac66de4 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -0,0 +1,299 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief SD MSP Initialization +* This function configures the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspInit 0 */ + + /* USER CODE END SDIO_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDIO_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDIO; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN SDIO_MspInit 1 */ + + /* USER CODE END SDIO_MspInit 1 */ + } + +} + +/** +* @brief SD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) +{ + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspDeInit 0 */ + + /* USER CODE END SDIO_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDIO_CLK_DISABLE(); + + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* USER CODE BEGIN SDIO_MspDeInit 1 */ + + /* USER CODE END SDIO_MspDeInit 1 */ + } + +} + +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); + + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Src/stm32f4xx_it.c b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Src/stm32f4xx_it.c new file mode 100644 index 00000000000..ec270690356 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Src/stm32f4xx_it.c @@ -0,0 +1,203 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f4xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Src/system_stm32f4xx.c b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Src/system_stm32f4xx.c new file mode 100644 index 00000000000..3bd40f77881 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/CubeMX_Config/Src/system_stm32f4xx.c @@ -0,0 +1,747 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ + STM32F412Zx || STM32F412Vx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/Kconfig b/bsp/stm32/stm32f407-lckfb-skystar/board/Kconfig new file mode 100644 index 00000000000..12561c9c00a --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/Kconfig @@ -0,0 +1,422 @@ +menu "Hardware Drivers Config" + +menu "Onboard Peripheral Drivers" + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (GD25Q32 spi1)" + select BSP_USING_SPI + select BSP_USING_SPI1 + select RT_USING_SFUD + select RT_SFUD_USING_SFDP + default n + + menuconfig BSP_USING_FS + bool "Enable File System" + select RT_USING_DFS + select RT_USING_DFS_ROMFS + default n + + if BSP_USING_FS + config BSP_USING_SDCARD_FATFS + bool "Enable SDCARD (FATFS)" + select BSP_USING_SDIO + select RT_USING_DFS_ELMFAT + default n + if BSP_USING_SDCARD_FATFS + menuconfig BSP_USING_FS_AUTO_MOUNT + bool "Enable filesystem auto mount" + default y + endif + + config BSP_USING_FLASH_FATFS + bool "Enable FAL filesystem partition base on GD25Q32" + select BSP_USING_FAL + default n + if BSP_USING_FLASH_FATFS + menuconfig BSP_USING_FLASH_FS_AUTO_MOUNT + bool "Enable filesystem auto mount" + default y + endif + endif + + config BSP_USING_FAL + bool "Enable FAL (enable on-chip flash and spi1 flash)" + select BSP_USING_SPI_FLASH + select RT_USING_FAL + select FAL_DEBUG_CONFIG + select FAL_PART_HAS_TABLE_CFG + select FAL_USING_SFUD_PORT + select BSP_USING_ON_CHIP_FLASH + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART4 + bool "Enable UART4" + default n + + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART5 + bool "Enable UART5" + default n + + config BSP_UART5_RX_USING_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + + config BSP_UART5_TX_USING_DMA + bool "Enable UART5 TX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART6 + bool "Enable UART6" + default n + + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM11 + bool "Enable TIM11" + default n + + config BSP_USING_TIM13 + bool "Enable TIM13" + default n + + config BSP_USING_TIM14 + bool "Enable TIM14" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM1 + bool "Enable timer1 output PWM" + default n + if BSP_USING_PWM1 + config BSP_USING_PWM1_CH2 + bool "Enable PWM1 channel2" + default n + config BSP_USING_PWM1_CH3 + bool "Enable PWM1 channel3" + default n + endif + menuconfig BSP_USING_PWM2 + bool "Enable timer2 output PWM" + default n + if BSP_USING_PWM2 + config BSP_USING_PWM2_CH3 + bool "Enable PWM2 channel3" + default n + config BSP_USING_PWM2_CH4 + bool "Enable PWM2 channel4" + default n + endif + menuconfig BSP_USING_PWM3 + bool "Enable timer3 output PWM" + default n + if BSP_USING_PWM3 + config BSP_USING_PWM3_CH2 + bool "Enable PWM3 channel2" + default n + endif + if BSP_USING_PWM3 + config BSP_USING_PWM3_CH4 + bool "Enable PWM3 channel4" + default n + endif + menuconfig BSP_USING_PWM4 + bool "Enable timer4 output PWM" + default n + if BSP_USING_PWM4 + config BSP_USING_PWM4_CH1 + bool "Enable PWM4 channel1" + default n + endif + menuconfig BSP_USING_PWM14 + bool "Enable timer14 output PWM" + default n + if BSP_USING_PWM14 + config BSP_USING_PWM14_CH1 + bool "Enable PWM14 channel1" + default n + endif + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_SOFT_SPI + bool "Enable soft SPI BUS" + default n + select RT_USING_SPI + select RT_USING_SPI_BITOPS + select RT_USING_PIN + if BSP_USING_SOFT_SPI + menuconfig BSP_USING_SOFT_SPI1 + bool "Enable soft SPI1 BUS (software simulation)" + default n + if BSP_USING_SOFT_SPI1 + config BSP_S_SPI1_SCK_PIN + int "soft spi1 sck pin number(G,5)" + range 0 143 + default 101 + config BSP_S_SPI1_MISO_PIN + int "soft spi1 miso pin numbe(G,3)" + range 0 143 + default 99 + config BSP_S_SPI1_MOSI_PIN + int "soft spi1 mosi pin number(G,1)" + range 0 143 + default 97 + endif + + menuconfig BSP_USING_SOFT_SPI2 + bool "Enable soft SPI2 BUS (software simulation)" + default n + if BSP_USING_SOFT_SPI2 + config BSP_S_SPI2_SCK_PIN + int "soft spi2 sck pin number" + range 0 143 + default 19 + config BSP_S_SPI2_MISO_PIN + int "soft spi2 miso pin number" + range 0 143 + default 20 + config BSP_S_SPI2_MOSI_PIN + int "soft spi2 mosi pin number" + range 0 143 + default 21 + endif + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC3 + bool "Enable ADC3" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + if BSP_USING_I2C + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 0 143 + default 24 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 143 + default 25 + endif + endif + + config BSP_USING_ONBOARD_PM + bool "Enable Power Management" + select RT_USING_PM + select RT_USING_HOOK + default n + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + select RT_USING_DAC + if BSP_USING_DAC + config BSP_USING_DAC1 + bool "Enable DAC1" + default n + endif + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + config SDIO_MAX_FREQ + int "sdio max freq" + range 0 24000000 + depends on BSP_USING_SDIO + default 1000000 + + config BSP_USING_USBD + bool "Enable USB Device" + select RT_USING_USB_DEVICE + default n + + menuconfig BSP_USING_PULSE_ENCODER + bool "Enable Pulse Encoder" + default n + select RT_USING_PULSE_ENCODER + if BSP_USING_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER4 + bool "Enable Pulse Encoder4" + default n + + endif + + config BSP_USING_EXT_FMC_IO + bool + default n + + config BSP_USING_FMC + bool + default n + source "$BSP_DIR/../libraries/HAL_Drivers/drivers/Kconfig" + +endmenu + +endmenu diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/SConscript b/bsp/stm32/stm32f407-lckfb-skystar/board/SConscript new file mode 100644 index 00000000000..dcffdb097e5 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/SConscript @@ -0,0 +1,39 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +CubeMX_Config/Src/stm32f4xx_hal_msp.c +''') +path = [cwd] +path += [cwd + '/CubeMX_Config/Inc'] + + +startup_path_prefix = SDK_LIB + +if rtconfig.PLATFORM in ['gcc', 'llvm-arm']: + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s'] +elif rtconfig.PLATFORM in ['armcc', 'armclang']: + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f407xx.s'] +elif rtconfig.PLATFORM in ['iccarm']: + src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f407xx.s'] + +CPPDEFINES = ['STM32F407xx'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + + +# if os.path.isfile(os.path.join(cwd, "ports", 'SConscript')): +# group = group + SConscript(os.path.join("ports", 'SConscript')) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/board.c b/bsp/stm32/stm32f407-lckfb-skystar/board/board.c new file mode 100644 index 00000000000..d5679212881 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/board.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-07-06 Supperthomas first version + */ + +#include "board.h" +#include + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 168; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } +} diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/board.h b/bsp/stm32/stm32f407-lckfb-skystar/board/board.h new file mode 100644 index 00000000000..ebecce07793 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/board.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-07-06 Supperthomas first version + */ + + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define STM32_SRAM_SIZE (128) +#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) + +#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define STM32_FLASH_SIZE (512 * 1024) +#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +#if defined(__ARMCC_VERSION) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END STM32_SRAM_END + +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/linker_scripts/link.icf b/bsp/stm32/stm32f407-lckfb-skystar/board/linker_scripts/link.icf new file mode 100644 index 00000000000..c18f2cc1c54 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/linker_scripts/link.icf @@ -0,0 +1,30 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM1_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_RAM2_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM2_end__ = 0x1000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM1_region { readwrite, last block CSTACK }; diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/linker_scripts/link.lds b/bsp/stm32/stm32f407-lckfb-skystar/board/linker_scripts/link.lds new file mode 100644 index 00000000000..698e67037c1 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/linker_scripts/link.lds @@ -0,0 +1,177 @@ +/* + * linker script for STM32F4xx with GNU ld + * bernard.xiong 2009-10-14 + * flybreak 2018-11-19 Add support for RAM2 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */ + RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */ + RAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 64k /* 64K sram */ + MCUlcdgrambysram (rw) : ORIGIN = 0x68000000, LENGTH = 512k +} +ENTRY(Reset_Handler) +_system_stack_size = 0x400; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + KEEP(*(.eh_frame*)) + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM1 + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM1 + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM1 + __bss_end = .; + + .MCUlcdgrambysram (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + *(.MCUlcdgrambysram) + *(.MCUlcdgrambysram.*) + . = ALIGN(4); + __MCUlcdgrambysram_free__ = .; + } > MCUlcdgrambysram + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/linker_scripts/link.sct b/bsp/stm32/stm32f407-lckfb-skystar/board/linker_scripts/link.sct new file mode 100644 index 00000000000..5d1e3e6c008 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00080000 { ; load region size_region + ER_IROM1 0x08000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/ports/SConscript b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/SConscript new file mode 100644 index 00000000000..55027ef16be --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/SConscript @@ -0,0 +1,70 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = [] +path = [cwd] + +if GetDepend(['BSP_USING_ETH']): + src += Glob('phy_reset.c') + +if GetDepend(['BSP_USING_RS485']): + src += Glob('drv_rs485.c') + +if GetDepend(['BSP_USING_SOFT_SPI_FLASH']): + src += Glob('soft_spi_flash_init.c') + +if GetDepend(['BSP_USING_SPI_FLASH']): + src += Glob('spi_flash_init.c') + +if GetDepend(['BSP_USING_FS']): + src += Glob('drv_filesystem.c') + +if GetDepend(['BSP_USING_FAL']): + src += Glob('fal/fal_spi_flash_sfud_port.c') + path += [cwd + '/fal'] + +if GetDepend(['BSP_USING_SRAM']): + src += Glob('drv_sram.c') + +if GetDepend(['BSP_USING_ONBOARD_LCD']): + src += Glob('lcd/drv_lcd.c') + path += [cwd + '/lcd'] + +if GetDepend(['BSP_USING_ONBOARD_LED_MATRIX']): + src += Glob('led_matrix/drv_matrix_led.c') + path += [cwd + '/led_matrix'] + +if GetDepend(['BSP_USING_EASYFLASH']): + src += Glob('ef_fal_port.c') + +if GetDepend(['BSP_USING_ENC28j60']): + src += Glob('drv_enc28j60.c') + +if GetDepend(['BSP_USING_ONBOARD_PM']): + src += Glob('pm/drv_pm.c') + src += Glob('pm/drv_wakeup.c') + path += [cwd + '/pm'] + +if GetDepend(['BSP_USING_AUDIO']): + src += Glob('audio/drv_es8388.c') + src += Glob('audio/drv_sound.c') + path += [cwd + '/audio'] + +if GetDepend(['BSP_USING_AUDIO_RECORD']): + src += Glob('audio/drv_mic.c') + +CPPDEFINES = ['STM32F407xx'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/ports/drv_filesystem.c b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/drv_filesystem.c new file mode 100644 index 00000000000..8f3f532662c --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/drv_filesystem.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 balanceTWK add sdcard port file + * 2021-05-10 Meco Man fix a bug that cannot use fatfs in the main thread at starting up + * 2021-07-28 Meco Man implement romfs as the root filesystem + */ + +#include +#include +#include +#include + +#if DFS_FILESYSTEMS_MAX < 4 +#error "Please define DFS_FILESYSTEMS_MAX more than 4" +#endif +#if DFS_FILESYSTEM_TYPES_MAX < 4 +#error "Please define DFS_FILESYSTEM_TYPES_MAX more than 4" +#endif + +#define DBG_TAG "app.filesystem" +#define DBG_LVL DBG_INFO +#include + +#ifdef BSP_USING_FS_AUTO_MOUNT +#ifdef BSP_USING_SDCARD_FATFS +static int onboard_sdcard_mount(void) +{ + if (dfs_mount("sd0", "/sdcard", "elm", 0, 0) == RT_EOK) + { + LOG_I("SD card mount to '/sdcard'"); + } + else + { + LOG_E("SD card mount to '/sdcard' failed!"); + } + + return RT_EOK; +} +#endif /* BSP_USING_SDCARD_FATFS */ +#endif /* BSP_USING_FS_AUTO_MOUNT */ + +#ifdef BSP_USING_FLASH_FS_AUTO_MOUNT +#ifdef BSP_USING_FLASH_FATFS +#define FS_PARTITION_NAME "filesystem" + +static int onboard_fal_mount(void) +{ + /* 初始化 fal 功能 */ + extern int fal_init(void); + extern struct rt_device *fal_blk_device_create(const char *parition_name); + fal_init(); + /* 在 spi flash 中名为 "filesystem" 的分区上创建一个块设备 */ + struct rt_device *flash_dev = fal_blk_device_create(FS_PARTITION_NAME); + if (flash_dev == NULL) + { + LOG_E("Can't create a block device on '%s' partition.", FS_PARTITION_NAME); + } + else + { + LOG_D("Create a block device on the %s partition of flash successful.", FS_PARTITION_NAME); + } + + /* 挂载 spi flash 中名为 "filesystem" 的分区上的文件系统 */ + if (dfs_mount(flash_dev->parent.name, "/fal", "elm", 0, 0) == 0) + { + LOG_I("Filesystem initialized!"); + } + else + { + LOG_E("Failed to initialize filesystem!"); + LOG_D("You should create a filesystem on the block device first!"); + } + + return RT_EOK; +} +#endif /*BSP_USING_FLASH_FATFS*/ +#endif /*BSP_USING_FLASH_FS_AUTO_MOUNT*/ + + +const struct romfs_dirent _romfs_root[] = +{ +#ifdef BSP_USING_SDCARD_FATFS + {ROMFS_DIRENT_DIR, "sdcard", RT_NULL, 0}, +#endif + +#ifdef BSP_USING_FLASH_FATFS + {ROMFS_DIRENT_DIR, "fal", RT_NULL, 0}, +#endif +}; + +const struct romfs_dirent romfs_root = +{ + ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root) / sizeof(_romfs_root[0]) +}; + +static int filesystem_mount(void) +{ + +#ifdef BSP_USING_FS + if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) != 0) + { + LOG_E("rom mount to '/' failed!"); + } + + /* 确保块设备注册成功之后再挂载文件系统 */ + rt_thread_delay(500); +#endif +#ifdef BSP_USING_FS_AUTO_MOUNT + onboard_sdcard_mount(); +#endif /* BSP_USING_FS_AUTO_MOUNT */ + +#ifdef BSP_USING_FLASH_FS_AUTO_MOUNT + onboard_fal_mount(); +#endif + + return RT_EOK; +} +INIT_APP_EXPORT(filesystem_mount); diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/ports/ef_fal_port.c b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/ef_fal_port.c new file mode 100644 index 00000000000..17346524cc6 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/ef_fal_port.c @@ -0,0 +1,210 @@ +/* + * This file is part of the EasyFlash Library. + * + * Copyright (c) 2015, Armink, + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * 'Software'), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Function: Portable interface for FAL (Flash Abstraction Layer) partition. + * Created on: 2018-05-19 + */ + +#include +#include +#include +#include +#include +#include +#include + +/* EasyFlash partition name on FAL partition table */ +#define FAL_EF_PART_NAME "easyflash" + +/* default ENV set for user */ +static const ef_env default_env_set[] = { + {"iap_need_copy_app", "0"}, + {"iap_need_crc32_check", "0"}, + {"iap_copy_app_size", "0"}, + {"stop_in_bootloader", "0"}, +}; + +static char log_buf[RT_CONSOLEBUF_SIZE]; +static struct rt_semaphore env_cache_lock; +static const struct fal_partition *part = NULL; + +/** + * Flash port for hardware initialize. + * + * @param default_env default ENV set for user + * @param default_env_size default ENV size + * + * @return result + */ +EfErrCode ef_port_init(ef_env const **default_env, size_t *default_env_size) { + EfErrCode result = EF_NO_ERR; + + *default_env = default_env_set; + *default_env_size = sizeof(default_env_set) / sizeof(default_env_set[0]); + + rt_sem_init(&env_cache_lock, "env lock", 1, RT_IPC_FLAG_PRIO); + + part = fal_partition_find(FAL_EF_PART_NAME); + EF_ASSERT(part); + + return result; +} + +/** + * Read data from flash. + * @note This operation's units is word. + * + * @param addr flash address + * @param buf buffer to store read data + * @param size read bytes size + * + * @return result + */ +EfErrCode ef_port_read(uint32_t addr, uint32_t *buf, size_t size) { + EfErrCode result = EF_NO_ERR; + + fal_partition_read(part, addr, (uint8_t *)buf, size); + + return result; +} + +/** + * Erase data on flash. + * @note This operation is irreversible. + * @note This operation's units is different which on many chips. + * + * @param addr flash address + * @param size erase bytes size + * + * @return result + */ +EfErrCode ef_port_erase(uint32_t addr, size_t size) { + EfErrCode result = EF_NO_ERR; + + /* make sure the start address is a multiple of FLASH_ERASE_MIN_SIZE */ + EF_ASSERT(addr % EF_ERASE_MIN_SIZE == 0); + + if (fal_partition_erase(part, addr, size) < 0) + { + result = EF_ERASE_ERR; + } + + return result; +} +/** + * Write data to flash. + * @note This operation's units is word. + * @note This operation must after erase. @see flash_erase. + * + * @param addr flash address + * @param buf the write data buffer + * @param size write bytes size + * + * @return result + */ +EfErrCode ef_port_write(uint32_t addr, const uint32_t *buf, size_t size) { + EfErrCode result = EF_NO_ERR; + + if (fal_partition_write(part, addr, (uint8_t *)buf, size) < 0) + { + result = EF_WRITE_ERR; + } + + return result; +} + +/** + * lock the ENV ram cache + */ +void ef_port_env_lock(void) { + rt_sem_take(&env_cache_lock, RT_WAITING_FOREVER); +} + +/** + * unlock the ENV ram cache + */ +void ef_port_env_unlock(void) { + rt_sem_release(&env_cache_lock); +} + +/** + * This function is print flash debug info. + * + * @param file the file which has call this function + * @param line the line number which has call this function + * @param format output format + * @param ... args + * + */ +void ef_log_debug(const char *file, const long line, const char *format, ...) { + +#ifdef PRINT_DEBUG + + va_list args; + + /* args point to the first variable parameter */ + va_start(args, format); + ef_print("[Flash] (%s:%ld) ", file, line); + /* must use vprintf to print */ + rt_vsprintf(log_buf, format, args); + ef_print("%s", log_buf); + va_end(args); + +#endif + +} + +/** + * This function is print flash routine info. + * + * @param format output format + * @param ... args + */ +void ef_log_info(const char *format, ...) { + va_list args; + + /* args point to the first variable parameter */ + va_start(args, format); + ef_print("[Flash] "); + /* must use vprintf to print */ + rt_vsprintf(log_buf, format, args); + ef_print("%s", log_buf); + va_end(args); +} +/** + * This function is print flash non-package info. + * + * @param format output format + * @param ... args + */ +void ef_print(const char *format, ...) { + va_list args; + + /* args point to the first variable parameter */ + va_start(args, format); + /* must use vprintf to print */ + rt_vsprintf(log_buf, format, args); + rt_kprintf("%s", log_buf); + va_end(args); +} diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/ports/fal/fal_cfg.h b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/fal/fal_cfg.h new file mode 100644 index 00000000000..7e2d73980df --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/fal/fal_cfg.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-5 SummerGift first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#define FLASH_SIZE_GRANULARITY_16K (4 * 16 * 1024) +#define FLASH_SIZE_GRANULARITY_64K (8 * 64 * 1024) +#define FLASH_SIZE_GRANULARITY_128K (8 * 128 * 1024) +#define STM32_FLASH_START_ADRESS_16K STM32_FLASH_START_ADRESS +#define STM32_FLASH_START_ADRESS_64K STM32_FLASH_START_ADRESS +#define STM32_FLASH_START_ADRESS_128K STM32_FLASH_START_ADRESS + +extern const struct fal_flash_dev stm32_onchip_flash_16k; +extern const struct fal_flash_dev stm32_onchip_flash_64k; +extern const struct fal_flash_dev stm32_onchip_flash_128k; +extern struct fal_flash_dev gd25q32; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &stm32_onchip_flash_128k, \ + &gd25q32, \ +} + +/* ====================== Partition Configuration ========================== */ + +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WROD, "app", "onchip_flash_128k", 0, 384 * 1024, 0}, \ + {FAL_PART_MAGIC_WROD, "param", "onchip_flash_128k", 384 * 1024, 512 * 1024, 0}, \ + {FAL_PART_MAGIC_WROD, "easyflash", "GD25Q32", 0, 512 * 1024, 0}, \ + {FAL_PART_MAGIC_WROD, "download", "GD25Q32", 512 * 1024, 512 * 1024, 0}, \ + {FAL_PART_MAGIC_WROD, "filesystem", "GD25Q32", (512 + 512) * 1024, 3 * 1024 * 1024, 0}, \ +} +#endif /*FAL_PART_TABLE*/ + diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/ports/fal/fal_spi_flash_sfud_port.c b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/fal/fal_spi_flash_sfud_port.c new file mode 100644 index 00000000000..2c22f3fc0c7 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/fal/fal_spi_flash_sfud_port.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-07 Meco Man first version + */ + +#include +#include + +#ifdef RT_USING_SFUD +#include +#endif + +static int init(void); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); + +static sfud_flash_t sfud_dev = NULL; +struct fal_flash_dev gd25q32 = +{ + .name = "GD25Q32", + .addr = 0, + .len = 4 * 1024 * 1024, + .blk_size = 4096, + .ops = {init, read, write, erase}, + .write_gran = 1 +}; + +static int init(void) +{ + sfud_dev = rt_sfud_flash_find_by_dev_name("GD25Q32"); + if (RT_NULL == sfud_dev) + { + return -1; + } + + /* update the flash chip information */ + gd25q32.blk_size = sfud_dev->chip.erase_gran; + gd25q32.len = sfud_dev->chip.capacity; + + return 0; +} + +static int read(long offset, uint8_t *buf, size_t size) +{ + assert(sfud_dev); + assert(sfud_dev->init_ok); + sfud_read(sfud_dev, gd25q32.addr + offset, size, buf); + + return size; +} + +static int write(long offset, const uint8_t *buf, size_t size) +{ + assert(sfud_dev); + assert(sfud_dev->init_ok); + if (sfud_write(sfud_dev, gd25q32.addr + offset, size, buf) != SFUD_SUCCESS) + { + return -1; + } + + return size; +} + +static int erase(long offset, size_t size) +{ + assert(sfud_dev); + assert(sfud_dev->init_ok); + if (sfud_erase(sfud_dev, gd25q32.addr + offset, size) != SFUD_SUCCESS) + { + return -1; + } + + return size; +} diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/ports/phy_reset.c b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/phy_reset.c new file mode 100644 index 00000000000..ec5c61f1b00 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/phy_reset.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-23 flybreak first version + */ + +#include + +#define RESET_IO GET_PIN(D, 3) + +void phy_reset(void) +{ + rt_pin_write(RESET_IO, PIN_LOW); + rt_thread_mdelay(50); + rt_pin_write(RESET_IO, PIN_HIGH); +} + +int phy_init(void) +{ + rt_pin_mode(RESET_IO, PIN_MODE_OUTPUT); + rt_pin_write(RESET_IO, PIN_HIGH); + return RT_EOK; +} +INIT_BOARD_EXPORT(phy_init); diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/ports/pm/drv_pm.c b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/pm/drv_pm.c new file mode 100644 index 00000000000..d469ec592c0 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/pm/drv_pm.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-07-31 tanek first version + */ + +#include +#include +#include +#include +/** + * This function will put STM32F4xx into sleep mode. + * + * @param pm pointer to power manage structure + */ +static void sleep(struct rt_pm *pm, uint8_t mode) +{ + switch (mode) + { + case PM_SLEEP_MODE_NONE: + break; + + case PM_SLEEP_MODE_IDLE: + break; + + case PM_SLEEP_MODE_LIGHT: + HAL_SuspendTick(); /* 关闭系统时钟中断 */ + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); /* 进入 F407 sleep 模式，这个模式会停掉所有时钟，可被任意中断唤醒 */ + break; + + case PM_SLEEP_MODE_DEEP: + HAL_SuspendTick(); /* 关闭系统时钟中断 */ + HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); /* 进入 F407 stop 模式，这个模式会停掉所有时钟，可被任意中断唤醒 */ + break; + + case PM_SLEEP_MODE_STANDBY: + break; + + case PM_SLEEP_MODE_SHUTDOWN: + break; + + default: + RT_ASSERT(0); + break; + } +} + +/** + * This function will be Called in Wake up interrupt callback + * + * @param pm pointer to power manage structure + */ + +static struct rt_device *device = RT_NULL; +static struct rt_pm *pm = RT_NULL; + +void pm_wk_up() +{ + + switch (pm->sleep_mode) + { + case PM_SLEEP_MODE_NONE: + break; + + case PM_SLEEP_MODE_IDLE: + break; + + case PM_SLEEP_MODE_LIGHT: + HAL_ResumeTick(); /* 启动系统时钟中断 */ + break; + + case PM_SLEEP_MODE_DEEP: + SystemClock_Config(); /* 重新配置系统时钟 */ + HAL_ResumeTick(); /* 启动系统时钟中断 */ + break; + + case PM_SLEEP_MODE_STANDBY: + break; + + case PM_SLEEP_MODE_SHUTDOWN: + break; + + default: + RT_ASSERT(0); + break; + } + +} + +/** + * This function initialize the power manager + */ +static int drv_pm_hw_init(void) +{ + static const struct rt_pm_ops _ops = + { + sleep, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL + }; + + /* initialize system pm module */ + rt_system_pm_init(&_ops, 0, RT_NULL); + + /* get pm device */ + device = rt_device_find("pm"); + if(device == RT_NULL) + { + rt_kprintf("rt_pm find error"); + return 0; + } + pm = rt_container_of(device,struct rt_pm,parent); + return 1; +} +INIT_DEVICE_EXPORT(drv_pm_hw_init); diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/ports/pm/drv_wakeup.c b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/pm/drv_wakeup.c new file mode 100644 index 00000000000..2fea0afa114 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/pm/drv_wakeup.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-07 Tanek first implementation + */ + +#include +#include +#include +#include "board.h" +#include "drv_gpio.h" + +#define USER_WAKEUP_PIN GET_PIN(C, 5) +#define DRV_WKUP_PIN_IRQ_MODE PIN_IRQ_MODE_FALLING + +static void (*_wakeup_hook)(void); + +void bsp_register_wakeup(void (*hook)(void)) +{ + RT_ASSERT(hook != RT_NULL); + + _wakeup_hook = hook; +} + +static void _wakeup_callback(void *args) +{ + extern void pm_wk_up(); + pm_wk_up(); /* wakeup from deep sleep */ + if (_wakeup_hook) + _wakeup_hook(); +} + +static int rt_hw_wakeup_init(void) +{ + rt_pin_mode(USER_WAKEUP_PIN, PIN_MODE_INPUT_PULLUP); + rt_pin_attach_irq(USER_WAKEUP_PIN, DRV_WKUP_PIN_IRQ_MODE, _wakeup_callback, RT_NULL); + rt_pin_irq_enable(USER_WAKEUP_PIN, 1); + return 0; +} +INIT_BOARD_EXPORT(rt_hw_wakeup_init); diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/ports/pm/drv_wakeup.h b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/pm/drv_wakeup.h new file mode 100644 index 00000000000..abbeb7b58a1 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/pm/drv_wakeup.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-08-07 Tanek first implementation + */ + +#ifndef __DRV_WAKEUP_H__ +#define __DRV_WAKEUP_H__ + +extern void bsp_register_wakeup(void (*hook)(void)); + +#endif /* __DRV_WAKEUP_H__ */ + diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/ports/soft_spi_flash_init.c b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/soft_spi_flash_init.c new file mode 100644 index 00000000000..f1372de85ae --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/soft_spi_flash_init.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-6-14 solar first version + */ + +#include +#include "spi_flash.h" +#include "spi_flash_sfud.h" +#include +#include + +#ifdef BSP_USING_SOFT_SPI_FLASH + +static int rt_soft_spi_flash_init(void) +{ + __HAL_RCC_GPIOB_CLK_ENABLE(); + rt_hw_soft_spi_device_attach("sspi2", "sspi20", "PB.14"); + + if (RT_NULL == rt_sfud_flash_probe("W25Q128", "sspi20")) + { + return -RT_ERROR; + } + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_soft_spi_flash_init); +#endif /* BSP_USING_SOFT_SPI_FLASH */ diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/ports/spi_flash_init.c b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/spi_flash_init.c new file mode 100644 index 00000000000..16a5b78a844 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/ports/spi_flash_init.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-27 SummerGift add spi flash port file + */ + +#include +#include "spi_flash.h" +#include "spi_flash_sfud.h" +#include +#include + +#if defined(BSP_USING_SPI_FLASH) + +static int rt_hw_spi_flash_init(void) +{ + __HAL_RCC_GPIOB_CLK_ENABLE(); + rt_hw_spi_device_attach("spi1", "spi10", GET_PIN(A, 4)); + + if (RT_NULL == rt_sfud_flash_probe("GD25Q32", "spi10")) + { + return -RT_ERROR; + } + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init); +#endif + diff --git a/bsp/stm32/stm32f407-lckfb-skystar/figures/board.png b/bsp/stm32/stm32f407-lckfb-skystar/figures/board.png new file mode 100644 index 00000000000..0d356ad184d Binary files /dev/null and b/bsp/stm32/stm32f407-lckfb-skystar/figures/board.png differ diff --git a/bsp/stm32/stm32f407-lckfb-skystar/project.ewd b/bsp/stm32/stm32f407-lckfb-skystar/project.ewd new file mode 100644 index 00000000000..ea50b29bba0 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/project.ewd @@ -0,0 +1,2834 @@ + + + 3 + + rt-thread + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -O206 -S9 -C0 -P00000000 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32F407VETx$CMSIS\Flash\STM32F4xx_512.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F4xx_512 -FL080000 -FS08000000 -FP0($$Device:STM32F407VETx$CMSIS\Flash\STM32F4xx_512.FLM) + + + 0 + ST-LINKIII-KEIL_SWO + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F4xx_512 -FL080000 -FS08000000 -FP0($$Device:STM32F407VETx$CMSIS\Flash\STM32F4xx_512.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 5000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/stm32/stm32f407-lckfb-skystar/project.uvprojx b/bsp/stm32/stm32f407-lckfb-skystar/project.uvprojx new file mode 100644 index 00000000000..3594b46b0dc --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/project.uvprojx @@ -0,0 +1,1267 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F407VETx + STMicroelectronics + Keil.STM32F4xx_DFP.2.17.0 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_512 -FS08000000 -FL080000 -FP0($$Device:STM32F407VETx$CMSIS\Flash\STM32F4xx_512.FLM)) + 0 + $$Device:STM32F407VETx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VETx$CMSIS\SVD\STM32F407.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + RT_USING_LIBC, RT_USING_ARMLIBC, USE_HAL_DRIVER, STM32F407xx, __CLK_TCK=RT_TICK_PER_SECOND, __STDC_LIMIT_MACROS, __RTTHREAD__ + + ..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\HAL_Drivers\CMSIS\Include;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;board\CubeMX_Config\Inc;applications;..\..\..\components\libc\compilers\common\include;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\HAL_Drivers\drivers;..\..\..\components\dfs\dfs_v1\filesystems\elmfat;..\..\..\libcpu\arm\common;..\libraries\HAL_Drivers\drivers\config;..\..\..\components\finsh;..\..\..\components\libc\posix\io\epoll;..\..\..\components\dfs\dfs_v1\filesystems\devfs;..\libraries\HAL_Drivers;board;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\libc\posix\io\eventfd;board\ports;..\..\..\components\dfs\dfs_v1\filesystems\romfs;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;.;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\dfs\dfs_v1\include;..\..\..\components\libc\posix\ipc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + + + cunistd.c + 1 + ..\..\..\components\libc\compilers\common\cunistd.c + + + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + + + DeviceDrivers + + + device.c + 1 + ..\..\..\components\drivers\core\device.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + completion.c + 1 + ..\..\..\components\drivers\ipc\completion.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\ipc\dataqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + pipe.c + 1 + ..\..\..\components\drivers\ipc\pipe.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\ipc\ringblk_buf.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\ipc\ringbuffer.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + pin.c + 1 + ..\..\..\components\drivers\pin\pin.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + Drivers + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drivers\drv_usart.c + + + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + + + startup_stm32f407xx.s + 2 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f407xx.s + + + + + stm32f4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + + + + + board.c + 1 + board\board.c + + + + + Filesystem + + + devfs.c + 1 + ..\..\..\components\dfs\dfs_v1\filesystems\devfs\devfs.c + + + + + dfs_elm.c + 1 + ..\..\..\components\dfs\dfs_v1\filesystems\elmfat\dfs_elm.c + + + + + ff.c + 1 + ..\..\..\components\dfs\dfs_v1\filesystems\elmfat\ff.c + + + + + ffunicode.c + 1 + ..\..\..\components\dfs\dfs_v1\filesystems\elmfat\ffunicode.c + + + + + dfs_romfs.c + 1 + ..\..\..\components\dfs\dfs_v1\filesystems\romfs\dfs_romfs.c + + + + + dfs.c + 1 + ..\..\..\components\dfs\dfs_v1\src\dfs.c + + + + + dfs_file.c + 1 + ..\..\..\components\dfs\dfs_v1\src\dfs_file.c + + + + + dfs_fs.c + 1 + ..\..\..\components\dfs\dfs_v1\src\dfs_fs.c + + + + + dfs_posix.c + 1 + ..\..\..\components\dfs\dfs_v1\src\dfs_posix.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + msh_file.c + 1 + ..\..\..\components\finsh\msh_file.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_comm.c + 1 + ..\..\..\src\scheduler_comm.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_up.c + 1 + ..\..\..\src\scheduler_up.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + libcpu + + + atomic_arm.c + 1 + ..\..\..\libcpu\arm\common\atomic_arm.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + Libraries + + + stm32f4xx_hal_uart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + + + + stm32f4xx_hal_cryp_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c + + + + + stm32f4xx_hal_pwr_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + + + + + stm32f4xx_hal_rng.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + + + + + stm32f4xx_hal_dma.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + + + + + stm32f4xx_hal.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c + + + + + stm32f4xx_hal_rcc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + + + + stm32f4xx_hal_usart.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + + + + stm32f4xx_hal_cec.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c + + + + + stm32f4xx_hal_rcc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + + + + + stm32f4xx_hal_dma_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + + + + + stm32f4xx_hal_pwr.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + + + + + system_stm32f4xx.c + 1 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + + + + + stm32f4xx_hal_crc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + + + + + stm32f4xx_hal_cortex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + + + + + stm32f4xx_hal_cryp.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c + + + + + stm32f4xx_hal_gpio.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f407-lckfb-skystar/rtconfig.h b/bsp/stm32/stm32f407-lckfb-skystar/rtconfig.h new file mode 100644 index 00000000000..7e00d19b6d2 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/rtconfig.h @@ -0,0 +1,291 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +#define SOC_STM32F407ZG +#define BOARD_STM32F407_SPARK + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 + +/* kservice optimization */ + +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50100 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_ROMFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Memory protection */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* BL808 WiFi */ + + +/* CYW43439 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + + +/* Kendryte SDK */ + + +/* sensors drivers */ + + +/* touch drivers */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32F4 + +/* Hardware Drivers Config */ + +/* Onboard Peripheral Drivers */ + + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 + +#endif diff --git a/bsp/stm32/stm32f407-lckfb-skystar/rtconfig.py b/bsp/stm32/stm32f407-lckfb-skystar/rtconfig.py new file mode 100644 index 00000000000..8195d720df5 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/rtconfig.py @@ -0,0 +1,218 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' +elif CROSS_TOOL == 'llvm-arm': + PLATFORM = 'llvm-arm' + EXEC_PATH = r'D:\Progrem\LLVMEmbeddedToolchainForArm-17.0.1-Windows-x86_64\bin' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -Os' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' + POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' + CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' +elif PLATFORM == 'llvm-arm': + # toolchains + PREFIX = 'llvm-' + CC = 'clang' + AS = 'clang' + AR = PREFIX + 'ar' + CXX = 'clang++' + LINK = 'clang' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + DEVICE = ' --target=arm-none-eabihf -mfloat-abi=hard -march=armv7em -mfpu=fpv4-sp-d16' + DEVICE += ' -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -Wa,-mimplicit-it=thumb ' ## -x assembler-with-cpp + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-u,Reset_Handler -lcrt0 -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O3' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/stm32/stm32f407-lckfb-skystar/template.ewp b/bsp/stm32/stm32f407-lckfb-skystar/template.ewp new file mode 100644 index 00000000000..21c66ca0d01 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/template.ewp @@ -0,0 +1,2031 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/stm32/stm32f407-lckfb-skystar/template.eww b/bsp/stm32/stm32f407-lckfb-skystar/template.eww new file mode 100644 index 00000000000..bd036bb4c98 --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/stm32/stm32f407-lckfb-skystar/template.uvoptx b/bsp/stm32/stm32f407-lckfb-skystar/template.uvoptx new file mode 100644 index 00000000000..2749145cd9c --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/template.uvoptx @@ -0,0 +1,197 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -O206 -S9 -C0 -P00000000 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32F407VETx$CMSIS\Flash\STM32F4xx_512.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F4xx_512 -FL080000 -FS08000000 -FP0($$Device:STM32F407VETx$CMSIS\Flash\STM32F4xx_512.FLM) + + + 0 + ST-LINKIII-KEIL_SWO + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F4xx_512 -FL080000 -FS08000000 -FP0($$Device:STM32F407VETx$CMSIS\Flash\STM32F4xx_512.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 5000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/stm32/stm32f407-lckfb-skystar/template.uvprojx b/bsp/stm32/stm32f407-lckfb-skystar/template.uvprojx new file mode 100644 index 00000000000..2ba5f866a3b --- /dev/null +++ b/bsp/stm32/stm32f407-lckfb-skystar/template.uvprojx @@ -0,0 +1,397 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F407VETx + STMicroelectronics + Keil.STM32F4xx_DFP.2.17.0 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_512 -FS08000000 -FL080000 -FP0($$Device:STM32F407VETx$CMSIS\Flash\STM32F4xx_512.FLM)) + 0 + $$Device:STM32F407VETx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VETx$CMSIS\SVD\STM32F407.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f407-robomaster-c/applications/arduino_pinout/SConscript b/bsp/stm32/stm32f407-robomaster-c/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32f407-robomaster-c/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32f407-robomaster-c/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32f407-robomaster-c/project.ewp b/bsp/stm32/stm32f407-robomaster-c/project.ewp index 853d19cfa16..4047c9f8deb 100644 --- a/bsp/stm32/stm32f407-robomaster-c/project.ewp +++ b/bsp/stm32/stm32f407-robomaster-c/project.ewp @@ -2194,6 +2194,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f407-robomaster-c/project.uvproj b/bsp/stm32/stm32f407-robomaster-c/project.uvproj index 38b7ea86c42..12d89ce1885 100644 --- a/bsp/stm32/stm32f407-robomaster-c/project.uvproj +++ b/bsp/stm32/stm32f407-robomaster-c/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f407-robomaster-c/project.uvprojx b/bsp/stm32/stm32f407-robomaster-c/project.uvprojx index 200cd348077..4e4f48cf9ea 100644 --- a/bsp/stm32/stm32f407-robomaster-c/project.uvprojx +++ b/bsp/stm32/stm32f407-robomaster-c/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f407-rt-spark/.ci/attachconfig/online-packages/misc/misc.attach b/bsp/stm32/stm32f407-rt-spark/.ci/attachconfig/online-packages/misc/misc.attach new file mode 100644 index 00000000000..10ca7940047 --- /dev/null +++ b/bsp/stm32/stm32f407-rt-spark/.ci/attachconfig/online-packages/misc/misc.attach @@ -0,0 +1,4 @@ +# scons: --strict + +# MultiButton +CONFIG_PKG_USING_MULTIBUTTON=y diff --git a/bsp/stm32/stm32f407-rt-spark/.ci/attachconfig/online-packages/misc/vi.attach b/bsp/stm32/stm32f407-rt-spark/.ci/attachconfig/online-packages/misc/vi.attach new file mode 100644 index 00000000000..29acf55118f --- /dev/null +++ b/bsp/stm32/stm32f407-rt-spark/.ci/attachconfig/online-packages/misc/vi.attach @@ -0,0 +1,16 @@ +# scons: --strict +CONFIG_PKG_USING_VI=y +# CONFIG_VI_ENABLE_8BIT=y +CONFIG_VI_ENABLE_COLON=y +CONFIG_VI_ENABLE_COLON_EXPAND=y +CONFIG_VI_ENABLE_YANKMARK=y +CONFIG_VI_ENABLE_SEARCH=y +CONFIG_VI_ENABLE_DOT_CMD=y +CONFIG_VI_ENABLE_READONLY=y +CONFIG_VI_ENABLE_SETOPTS=y +CONFIG_VI_ENABLE_SET=y +CONFIG_VI_ENABLE_WIN_RESIZE=y +CONFIG_VI_ENABLE_VI_ASK_TERMINAL=y +CONFIG_VI_ENABLE_UNDO=y +CONFIG_VI_ENABLE_UNDO_QUEUE=y +CONFIG_VI_ENABLE_VERBOSE_STATUS=y diff --git a/bsp/stm32/stm32f407-rt-spark/.config b/bsp/stm32/stm32f407-rt-spark/.config index 0b4ff7b467f..679f170a5a3 100644 --- a/bsp/stm32/stm32f407-rt-spark/.config +++ b/bsp/stm32/stm32f407-rt-spark/.config @@ -1069,6 +1069,7 @@ CONFIG_SOC_SERIES_STM32F4=y # # Onboard Peripheral Drivers # +# CONFIG_BSP_USING_ARDUINO is not set CONFIG_BSP_USING_USB_TO_USART=y # CONFIG_BSP_USING_COM2 is not set # CONFIG_BSP_USING_COM3 is not set diff --git a/bsp/stm32/stm32f407-rt-spark/applications/SConscript b/bsp/stm32/stm32f407-rt-spark/applications/SConscript index 1eaad937dd6..03feb2016a7 100644 --- a/bsp/stm32/stm32f407-rt-spark/applications/SConscript +++ b/bsp/stm32/stm32f407-rt-spark/applications/SConscript @@ -2,8 +2,11 @@ from building import * import os cwd = GetCurrentDir() +src = Glob('*.c') CPPPATH = [cwd] -src = Glob('*.c') + +if GetDepend(['PKG_USING_RTDUINO']) and not GetDepend(['RTDUINO_NO_SETUP_LOOP']): + src += ['arduino_main.cpp'] group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/stm32/stm32f407-rt-spark/applications/arduino_main.cpp b/bsp/stm32/stm32f407-rt-spark/applications/arduino_main.cpp new file mode 100644 index 00000000000..1335fec08c1 --- /dev/null +++ b/bsp/stm32/stm32f407-rt-spark/applications/arduino_main.cpp @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-08 Li ZhenHong first version + */ + +#include + +void setup(void) +{ + /* put your setup code here, to run once: */ + Serial.begin(); +} + +void loop(void) +{ + /* put your main code here, to run repeatedly: */ + Serial.println("Hello Arduino!"); + delay(800); +} diff --git a/bsp/stm32/stm32f407-rt-spark/applications/arduino_pinout/README.md b/bsp/stm32/stm32f407-rt-spark/applications/arduino_pinout/README.md new file mode 100644 index 00000000000..330a1089ffa --- /dev/null +++ b/bsp/stm32/stm32f407-rt-spark/applications/arduino_pinout/README.md @@ -0,0 +1,69 @@ +# stm32f407-rt-spark 开发板的Arduino生态兼容说明 + +## 1 RTduino - RT-Thread的Arduino生态兼容层 + +stm32f407-rt-spark 开发板已经完整适配了[RTduino软件包](https://github.com/RTduino/RTduino)，即RT-Thread的Arduino生态兼容层。用户可以按照Arduino的编程习惯来操作该BSP，并且可以使用大量Arduino社区丰富的库，是对RT-Thread生态的极大增强。更多信息，请参见[RTduino软件包说明文档](https://github.com/RTduino/RTduino)。 + +### 1.1 如何开启针对本BSP的Arduino生态兼容层 + +Env 工具下敲入 menuconfig 命令，或者 RT-Thread Studio IDE 下选择 RT-Thread Settings： + +```Kconfig +Hardware Drivers Config ---> + Onboard Peripheral Drivers ---> + [*] Compatible with Arduino Ecosystem (RTduino) +``` + +## 2 Arduino引脚排布 + +更多引脚布局相关信息参见 [pins_arduino.c](pins_arduino.c) 和 [pins_arduino.h](pins_arduino.h)。 + +![Rt-spark_Rtduino_Pin_Map.drawio](Rt-spark_Rtduino_Pin_Map.drawio.png) + +| Arduino引脚编号 | STM32引脚编号 | 5V容忍 | 备注 | +| ------------------- | --------- | ---- | ------------------------------------------------------------------------- | +| 0 (D0) | GET_PIN(A, 10) | 是 | Serial-RX,默认被RT-Thread的UART设备框架uart1接管 | +| 1 (D1) | GET_PIN(A, 9) | 是 | Serial-TX,默认被RT-Thread的UART设备框架uart1接管 | +| 2 (D2) | GET_PIN(A, 8) | 是 | | +| 3 (D3) | GET_PIN(B, 10) | 是 | PWM2-CH3,默认被RT-Thread的PWM设备框架pwm2接管 | +| 4 (D4) | GET_PIN(A, 1) | 是 | | +| 5 (D5) | GET_PIN(B, 14) | 是 | | +| 6 (D6) | GET_PIN(B, 11) | 是 | PWM2-CH4,默认被RT-Thread的PWM设备框架pwm2接管 | +| 7 (D7) | GET_PIN(B, 15) | 是 | | +| 8 (D8) | GET_PIN(F, 15) | 是 | | +| 9 (D9) | GET_PIN(E, 11) | 是 | PWM1-CH2,默认被RT-Thread的PWM设备框架pwm1接管 | +| 10 (D10) | GET_PIN(E, 13) | 是 | PWM1-CH3,默认被RT-Thread的PWM设备框架pwm1接管 | +| 11 (D11) | GET_PIN(D, 12) | 是 | PWM4-CH1,默认被RT-Thread的PWM设备框架pwm4接管 | +| 12 (D12) | GET_PIN(D, 10) | 是 | | +| 13 (D13) | GET_PIN(D, 8) | 是 | | +| 14 (D14) | GET_PIN(E, 14) | 是 | | +| 15 (D15) | GET_PIN(E, 12) | 是 | | +| 16 (D16) | GET_PIN(E, 15) | 是 | | +| 17 (D17) | GET_PIN(D, 9) | 是 | | +| 18 (D18) | GET_PIN(G, 2) | 是 | | +| 19 (D19) | GET_PIN(B, 2) | 是 | | +| 20 (D20) | GET_PIN(G, 0) | 是 | | +| 21 (D21) | GET_PIN(A, 0) | 是 | | +| 22 (D22) | GET_PIN(G, 5) | 是 | SSPI1-SCK,默认被RT-Thread的SPI设备框架sspi1接管| +| 23 (D23) | GET_PIN(G, 3) | 是 | SSPI1-MISO,默认被RT-Thread的SPI设备框架sspi1接管 | +| 24 (D24) | GET_PIN(G, 1) | 是 | SSPI1-MOSI,默认被RT-Thread的SPI设备框架sspi1接管 | +| 25 (D25) | GET_PIN(G, 7) | 是 | I2C1-SCL,默认被RT-Thread的I2C设备框架i2c1接管 | +| 26 (D26) | GET_PIN(D, 7) | 是 | I2C1-SDA,默认被RT-Thread的I2C设备框架i2c1接管 | +| 27 (D27) | GET_PIN(B, 6) | 是 | I2C2-SCL,默认被RT-Thread的I2C设备框架i2c2接管 | +| 28 (D28) | GET_PIN(B, 7) | 是 | I2C2-SDA,默认被RT-Thread的I2C设备框架i2c2接管 | +| 29 (D29) | GET_PIN(G, 6) | 是 | | +| 30 (D30) | GET_PIN(G, 4) | 是 | | +| 31 (D31) | GET_PIN(A, 2) | 是 | Serial2-TX,默认被RT-Thread的UART设备框架uart2接管 | +| 32 (D32) | GET_PIN(A, 3) | 是 | Serial2-RX,默认被RT-Thread的UART设备框架uart2接管 | +| 33 (D33) | GET_PIN(F, 12) | 是 | 板载用户R_LED | +| 34 (D34) | GET_PIN(F, 11) | 是 | 板载用户B_LED | +| 35 (D35) | GET_PIN(B, 0) | 是 | 板载蜂鸣器 | +| 36 (D36) | GET_PIN(C, 5) | 是 | 板载按键KEY_UP | +| 37 (D37) | GET_PIN(C, 1) | 是 | 板载按键KEY_DOWM | +| 38 (D38) | GET_PIN(C, 0) | 是 | 板载按键KEY_LEFT | +| 39 (D39) | GET_PIN(C, 4) | 是 | 板载按键KEY_RIGHT | +| 40 (A0) | GET_PIN(F, 6) | 是 | ADC3-CH4,默认被RT-Thread的ADC设备框架adc3接管 | +| 41 (A1) | GET_PIN(F, 7) | 是 | ADC3-CH5,默认被RT-Thread的ADC设备框架adc3接管 | +| 42 (A2) | GET_PIN(F, 4) | 是 | ADC3-CH14,默认被RT-Thread的ADC设备框架adc3接管 | +| 43 (A3) | GET_PIN(F, 5) | 是 | ADC3-CH15,默认被RT-Thread的ADC设备框架adc3接管 | +| 44 (DAC0) | GET_PIN(A, 4) | 否 | DAC1-CH1,默认被RT-Thread的DAC设备框架dac1接管 | diff --git a/bsp/stm32/stm32f407-rt-spark/applications/arduino_pinout/Rt-spark_Rtduino_Pin_Map.drawio.png b/bsp/stm32/stm32f407-rt-spark/applications/arduino_pinout/Rt-spark_Rtduino_Pin_Map.drawio.png new file mode 100644 index 00000000000..b84867a5366 Binary files /dev/null and b/bsp/stm32/stm32f407-rt-spark/applications/arduino_pinout/Rt-spark_Rtduino_Pin_Map.drawio.png differ diff --git a/bsp/stm32/stm32f407-rt-spark/applications/arduino_pinout/SConscript b/bsp/stm32/stm32f407-rt-spark/applications/arduino_pinout/SConscript new file mode 100644 index 00000000000..da85e053c37 --- /dev/null +++ b/bsp/stm32/stm32f407-rt-spark/applications/arduino_pinout/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +inc = [cwd] + +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) + +Return('group') diff --git a/bsp/stm32/stm32f407-rt-spark/applications/arduino_pinout/pins_arduino.c b/bsp/stm32/stm32f407-rt-spark/applications/arduino_pinout/pins_arduino.c new file mode 100644 index 00000000000..88fed11beba --- /dev/null +++ b/bsp/stm32/stm32f407-rt-spark/applications/arduino_pinout/pins_arduino.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-10 Li ZhenHong first version + */ + +#include +#include "pins_arduino.h" +#include + +/* + * {Arduino Pin, RT-Thread Pin [, Device Name, Channel]} + * [] means optional + * Digital pins must NOT give the device name and channel. + * Analog pins MUST give the device name and channel(ADC, PWM or DAC). + * Arduino Pin must keep in sequence. + */ +const pin_map_t pin_map_table[]= +{ + {D0, GET_PIN(A, 10), "uart1"}, /* Serial-RX */ + {D1, GET_PIN(A, 9), "uart1"}, /* Serial-TX */ + {D2, GET_PIN(A, 8)}, + {D3, GET_PIN(B, 10), "pwm2", 3}, /* PWM */ + {D4, GET_PIN(A, 1)}, + {D5, GET_PIN(B, 14)}, + {D6, GET_PIN(B, 11), "pwm2", 4}, /* PWM */ + {D7, GET_PIN(B, 15)}, + {D8, GET_PIN(F, 15)}, + {D9, GET_PIN(E, 11), "pwm1", 2}, /* PWM */ + {D10, GET_PIN(E, 13), "pwm1", 3}, /* PWM */ + {D11, GET_PIN(D, 12), "pwm4", 1}, /* PWM */ + {D12, GET_PIN(D, 10)}, + {D13, GET_PIN(D, 8)}, + {D14, GET_PIN(E, 14)}, + {D15, GET_PIN(E, 12)}, + {D16, GET_PIN(E, 15)}, + {D17, GET_PIN(D, 9)}, + {D18, GET_PIN(G, 2)}, + {D19, GET_PIN(B, 2)}, + {D20, GET_PIN(G, 0)}, + {D21, GET_PIN(A, 0)}, + {D22, GET_PIN(G, 5), "sspi1"}, /* SOFT-SPI-SCK */ + {D23, GET_PIN(G, 3), "sspi1"}, /* SOFT-SPI-SCK */ + {D24, GET_PIN(G, 1), "sspi1"}, /* SOFT-SPI-SCK */ + {D25, GET_PIN(G, 7), "i2c4"}, /* I2C-SCL (Wire) */ + {D26, GET_PIN(D, 7), "i2c4"}, /* I2C-SDA (Wire) */ + {D27, GET_PIN(B, 6), "i2c5"}, /* I2C-SCL (Wire) */ + {D28, GET_PIN(B, 7), "i2c5"}, /* I2C-SDA (Wire) */ + {D29, GET_PIN(G, 6)}, /* SPI-SS */ + {D30, GET_PIN(G, 4)}, + {D31, GET_PIN(A, 2), "uart2"}, /* Serial2-TX */ + {D32, GET_PIN(A, 3), "uart2"}, /* Serial2-RX */ + {D33, GET_PIN(F, 12)}, /* On-Board R_LED */ + {D34, GET_PIN(F, 11)}, /* On-Board B_LED */ + {D35, GET_PIN(B, 0)}, /* On_Board Buzzer */ + {D36, GET_PIN(C, 5)}, /* On-Board KEY_UP */ + {D37, GET_PIN(C, 1)}, /* On-Board KEY_DOWM */ + {D38, GET_PIN(C, 0)}, /* On-Board KEY_LEFT */ + {D39, GET_PIN(C, 4)}, /* On-Board KEY_RIGHT */ + {A0, GET_PIN(F, 6), "adc3", 4}, /* ADC */ + {A1, GET_PIN(F, 7), "adc3", 5}, /* ADC */ + {A2, GET_PIN(F, 4), "adc3", 14}, /* ADC */ + {A3, GET_PIN(F, 5), "adc3", 15}, /* ADC */ + {DAC0, GET_PIN(A, 4), "dac1", 1}, /* DAC */ +}; diff --git a/bsp/stm32/stm32f407-rt-spark/applications/arduino_pinout/pins_arduino.h b/bsp/stm32/stm32f407-rt-spark/applications/arduino_pinout/pins_arduino.h new file mode 100644 index 00000000000..12b7d608853 --- /dev/null +++ b/bsp/stm32/stm32f407-rt-spark/applications/arduino_pinout/pins_arduino.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-07 Li ZhenHong first version + */ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +/* pins alias. Must keep in sequence */ +#define D0 (0) +#define D1 (1) +#define D2 (2) +#define D3 (3) +#define D4 (4) +#define D5 (5) +#define D6 (6) +#define D7 (7) +#define D8 (8) +#define D9 (9) +#define D10 (10) +#define D11 (11) +#define D12 (12) +#define D13 (13) +#define D14 (14) +#define D15 (15) +#define D16 (16) +#define D17 (17) +#define D18 (18) +#define D19 (19) +#define D20 (20) +#define D21 (21) +#define D22 (22) +#define D23 (23) +#define D24 (24) +#define D25 (25) +#define D26 (26) +#define D27 (27) +#define D28 (28) +#define D29 (29) +#define D30 (30) +#define D31 (31) +#define D32 (32) +#define D33 (33) +#define D34 (34) +#define D35 (35) +#define D36 (36) +#define D37 (37) +#define D38 (38) +#define D39 (39) +#define A0 (40) +#define A1 (41) +#define A2 (42) +#define A3 (43) +#define DAC0 (44) + +#define RTDUINO_PIN_MAX_LIMIT DAC0 /* pin number max limit check */ + +#define F_CPU 168000000L /* CPU:168MHz */ + +#define LED_BUILTIN D33 /* Default Built-in LED */ + +/* i2c4 : PD.7-SDA PG.7-SCL */ +#define RTDUINO_DEFAULT_IIC_BUS_NAME "i2c4" + +#define SS D32 /* Chip select pin of default spi */ +/* sspi1 : PG.5-SCK PG.3-MISO PG.1-MOSI */ +#define RTDUINO_DEFAULT_SPI_BUS_NAME "sspi1" + +/* Serial2(uart2) : PA.2-TX PA.3-RX */ +#define RTDUINO_SERIAL2_DEVICE_NAME "uart2" + +#endif /* Pins_Arduino_h */ diff --git a/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/.mxproject index 0971751d074..5e117bd4298 100644 --- a/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/.mxproject @@ -1,8 +1,8 @@ [PreviousLibFiles] -LibFiles=Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_adc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_adc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_adc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dac.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dac.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dac_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_fsmc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_sram.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_iwdg.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rtc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rtc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rtc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_sdmmc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_sd.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pcd.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pcd_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usb.h;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_adc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_adc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_adc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_adc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dac.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dac.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dac_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_fsmc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_sram.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_iwdg.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rtc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rtc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rtc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_sdmmc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_sd.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pcd.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pcd_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usb.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c; 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[PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;; +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_adc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c;..\Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;..\\Src\system_stm32f4xx.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_adc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c;..\Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;..\\Src\system_stm32f4xx.c;;; HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/CubeMX_Config.ioc index 71c65da7d5b..1e5006092da 100644 --- a/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/CubeMX_Config.ioc @@ -5,6 +5,11 @@ ADC1.NbrOfConversionFlag=1 ADC1.Rank-0\#ChannelRegularConversion=1 ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES ADC1.master=1 +ADC3.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_14 +ADC3.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag +ADC3.NbrOfConversionFlag=1 +ADC3.Rank-0\#ChannelRegularConversion=1 +ADC3.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES CAD.formats= CAD.pinconfig= CAD.provider= @@ -16,89 +21,94 @@ KeepUserPlacement=false Mcu.CPN=STM32F407ZGT6 Mcu.Family=STM32F4 Mcu.IP0=ADC1 -Mcu.IP1=DAC +Mcu.IP1=ADC3 Mcu.IP10=SYS -Mcu.IP11=TIM2 -Mcu.IP12=TIM3 -Mcu.IP13=TIM4 -Mcu.IP14=TIM11 -Mcu.IP15=TIM13 -Mcu.IP16=TIM14 -Mcu.IP17=USART1 -Mcu.IP18=USART3 -Mcu.IP19=USB_OTG_FS -Mcu.IP2=FSMC -Mcu.IP3=IWDG -Mcu.IP4=NVIC -Mcu.IP5=RCC -Mcu.IP6=RTC -Mcu.IP7=SDIO -Mcu.IP8=SPI1 +Mcu.IP11=TIM1 +Mcu.IP12=TIM2 +Mcu.IP13=TIM3 +Mcu.IP14=TIM4 +Mcu.IP15=TIM11 +Mcu.IP16=TIM13 +Mcu.IP17=TIM14 +Mcu.IP18=USART1 +Mcu.IP19=USART2 +Mcu.IP2=DAC +Mcu.IP20=USB_OTG_FS +Mcu.IP3=FSMC +Mcu.IP4=IWDG +Mcu.IP5=NVIC +Mcu.IP6=RCC +Mcu.IP7=RTC +Mcu.IP8=SDIO Mcu.IP9=SPI2 -Mcu.IPNb=20 +Mcu.IPNb=21 Mcu.Name=STM32F407Z(E-G)Tx Mcu.Package=LQFP144 Mcu.Pin0=PC14-OSC32_IN Mcu.Pin1=PC15-OSC32_OUT -Mcu.Pin10=PA5 -Mcu.Pin11=PB1 -Mcu.Pin12=PE7 -Mcu.Pin13=PE8 -Mcu.Pin14=PE9 -Mcu.Pin15=PE10 -Mcu.Pin16=PB10 -Mcu.Pin17=PB11 -Mcu.Pin18=PB13 -Mcu.Pin19=PD13 -Mcu.Pin2=PF9 -Mcu.Pin20=PD14 -Mcu.Pin21=PD15 -Mcu.Pin22=PC8 -Mcu.Pin23=PC9 -Mcu.Pin24=PA9 -Mcu.Pin25=PA10 -Mcu.Pin26=PA11 -Mcu.Pin27=PA12 -Mcu.Pin28=PA13 -Mcu.Pin29=PA14 -Mcu.Pin3=PH0-OSC_IN -Mcu.Pin30=PC10 -Mcu.Pin31=PC11 -Mcu.Pin32=PC12 -Mcu.Pin33=PD0 -Mcu.Pin34=PD1 -Mcu.Pin35=PD2 -Mcu.Pin36=PD4 -Mcu.Pin37=PD5 -Mcu.Pin38=PG10 -Mcu.Pin39=PG11 -Mcu.Pin4=PH1-OSC_OUT -Mcu.Pin40=PG13 -Mcu.Pin41=PG14 -Mcu.Pin42=PB3 -Mcu.Pin43=PB4 -Mcu.Pin44=PB5 -Mcu.Pin45=PB6 -Mcu.Pin46=PB7 -Mcu.Pin47=VP_IWDG_VS_IWDG -Mcu.Pin48=VP_RTC_VS_RTC_Activate -Mcu.Pin49=VP_SYS_VS_Systick -Mcu.Pin5=PC2 -Mcu.Pin50=VP_TIM2_VS_ClockSourceINT -Mcu.Pin51=VP_TIM3_VS_ClockSourceINT -Mcu.Pin52=VP_TIM11_VS_ClockSourceINT -Mcu.Pin53=VP_TIM13_VS_ClockSourceINT -Mcu.Pin54=VP_TIM14_VS_ClockSourceINT -Mcu.Pin6=PC3 -Mcu.Pin7=PA1 -Mcu.Pin8=PA3 -Mcu.Pin9=PA4 -Mcu.PinsNb=55 +Mcu.Pin10=PC3 +Mcu.Pin11=PA1 +Mcu.Pin12=PA2 +Mcu.Pin13=PA3 +Mcu.Pin14=PA4 +Mcu.Pin15=PA7 +Mcu.Pin16=PB1 +Mcu.Pin17=PE7 +Mcu.Pin18=PE8 +Mcu.Pin19=PE9 +Mcu.Pin2=PF4 +Mcu.Pin20=PE10 +Mcu.Pin21=PE11 +Mcu.Pin22=PE13 +Mcu.Pin23=PB10 +Mcu.Pin24=PB11 +Mcu.Pin25=PB13 +Mcu.Pin26=PD12 +Mcu.Pin27=PD13 +Mcu.Pin28=PD14 +Mcu.Pin29=PD15 +Mcu.Pin3=PF5 +Mcu.Pin30=PC8 +Mcu.Pin31=PC9 +Mcu.Pin32=PA9 +Mcu.Pin33=PA10 +Mcu.Pin34=PA11 +Mcu.Pin35=PA12 +Mcu.Pin36=PA13 +Mcu.Pin37=PA14 +Mcu.Pin38=PC10 +Mcu.Pin39=PC11 +Mcu.Pin4=PF6 +Mcu.Pin40=PC12 +Mcu.Pin41=PD0 +Mcu.Pin42=PD1 +Mcu.Pin43=PD2 +Mcu.Pin44=PD4 +Mcu.Pin45=PD5 +Mcu.Pin46=PG10 +Mcu.Pin47=PG11 +Mcu.Pin48=PG13 +Mcu.Pin49=PG14 +Mcu.Pin5=PF7 +Mcu.Pin50=VP_IWDG_VS_IWDG +Mcu.Pin51=VP_RTC_VS_RTC_Activate +Mcu.Pin52=VP_SYS_VS_Systick +Mcu.Pin53=VP_TIM1_VS_ClockSourceINT +Mcu.Pin54=VP_TIM2_VS_ClockSourceINT +Mcu.Pin55=VP_TIM3_VS_ClockSourceINT +Mcu.Pin56=VP_TIM11_VS_ClockSourceINT +Mcu.Pin57=VP_TIM13_VS_ClockSourceINT +Mcu.Pin58=VP_TIM14_VS_ClockSourceINT +Mcu.Pin6=PF9 +Mcu.Pin7=PH0-OSC_IN +Mcu.Pin8=PH1-OSC_OUT +Mcu.Pin9=PC2 +Mcu.PinsNb=59 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F407ZGTx -MxCube.Version=6.9.1 -MxDb.Version=DB.6.0.91 +MxCube.Version=6.11.0 +MxDb.Version=DB.6.0.110 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.ForceEnableDMAVector=true @@ -108,7 +118,6 @@ NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.SPI1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true @@ -126,38 +135,23 @@ PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK -PA3.Signal=S_TIM2_CH4 +PA2.Locked=true +PA2.Mode=Asynchronous +PA2.Signal=USART2_TX +PA3.Locked=true +PA3.Mode=Asynchronous +PA3.Signal=USART2_RX PA4.Signal=COMP_DAC1_group -PA5.Locked=true -PA5.Signal=COMP_DAC2_group +PA7.Signal=S_TIM3_CH2 PA9.GPIOParameters=GPIO_PuPd PA9.GPIO_PuPd=GPIO_PULLUP PA9.Mode=Asynchronous PA9.Signal=USART1_TX PB1.Signal=S_TIM3_CH4 -PB10.GPIOParameters=GPIO_PuPd -PB10.GPIO_PuPd=GPIO_PULLUP -PB10.Mode=Asynchronous -PB10.Signal=USART3_TX -PB11.GPIOParameters=GPIO_PuPd -PB11.GPIO_PuPd=GPIO_PULLUP -PB11.Mode=Asynchronous -PB11.Signal=USART3_RX +PB10.Signal=S_TIM2_CH3 +PB11.Signal=S_TIM2_CH4 PB13.Mode=Full_Duplex_Master PB13.Signal=SPI2_SCK -PB3.Locked=true -PB3.Mode=Full_Duplex_Master -PB3.Signal=SPI1_SCK -PB4.Locked=true -PB4.Mode=Full_Duplex_Master -PB4.Signal=SPI1_MISO -PB5.Locked=true -PB5.Mode=Full_Duplex_Master -PB5.Signal=SPI1_MOSI -PB6.Locked=true -PB6.Signal=S_TIM4_CH1 -PB7.Locked=true -PB7.Signal=S_TIM4_CH2 PC10.Mode=SD_4_bits_Wide_bus PC10.Signal=SDIO_D2 PC11.Mode=SD_4_bits_Wide_bus @@ -178,6 +172,7 @@ PC9.Mode=SD_4_bits_Wide_bus PC9.Signal=SDIO_D1 PD0.Signal=FSMC_D2_DA2 PD1.Signal=FSMC_D3_DA3 +PD12.Signal=S_TIM4_CH1 PD13.Signal=FSMC_A18 PD14.Signal=FSMC_D0_DA0 PD15.Signal=FSMC_D1_DA1 @@ -186,9 +181,24 @@ PD2.Signal=SDIO_CMD PD4.Signal=FSMC_NOE PD5.Signal=FSMC_NWE PE10.Signal=FSMC_D7_DA7 +PE11.Locked=true +PE11.Signal=S_TIM1_CH2 +PE13.Signal=S_TIM1_CH3 PE7.Signal=FSMC_D4_DA4 PE8.Signal=FSMC_D5_DA5 PE9.Signal=FSMC_D6_DA6 +PF4.Locked=true +PF4.Mode=IN14 +PF4.Signal=ADC3_IN14 +PF5.Locked=true +PF5.Mode=IN15 +PF5.Signal=ADC3_IN15 +PF6.Locked=true +PF6.Mode=IN4 +PF6.Signal=ADC3_IN4 +PF7.Locked=true +PF7.Mode=IN5 +PF7.Signal=ADC3_IN5 PF9.Signal=S_TIM14_CH1 PG10.Mode=NorPsramChipSelect3_1 PG10.Signal=FSMC_NE3 @@ -233,7 +243,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI1_Init-SPI1-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_USART3_UART_Init-USART3-false-HAL-true,7-MX_RTC_Init-RTC-false-HAL-true,8-MX_IWDG_Init-IWDG-false-HAL-true,9-MX_TIM14_Init-TIM14-false-HAL-true,10-MX_TIM13_Init-TIM13-false-HAL-true,11-MX_TIM11_Init-TIM11-false-HAL-true,12-MX_SDIO_SD_Init-SDIO-false-HAL-true,13-MX_TIM2_Init-TIM2-false-HAL-true,14-MX_SPI2_Init-SPI2-false-HAL-true,15-MX_TIM4_Init-TIM4-false-HAL-true,16-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,17-MX_FSMC_Init-FSMC-false-HAL-true,18-MX_DAC_Init-DAC-false-HAL-true,19-MX_TIM3_Init-TIM3-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI1_Init-SPI1-false-HAL-true,5-MX_RTC_Init-RTC-false-HAL-true,6-MX_IWDG_Init-IWDG-false-HAL-true,7-MX_TIM14_Init-TIM14-false-HAL-true,8-MX_TIM13_Init-TIM13-false-HAL-true,9-MX_TIM11_Init-TIM11-false-HAL-true,10-MX_SDIO_SD_Init-SDIO-false-HAL-true,11-MX_TIM2_Init-TIM2-false-HAL-true,12-MX_SPI2_Init-SPI2-false-HAL-true,13-MX_TIM4_Init-TIM4-false-HAL-true,14-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,15-MX_FSMC_Init-FSMC-false-HAL-true,16-MX_DAC_Init-DAC-false-HAL-true,17-MX_TIM3_Init-TIM3-false-HAL-true,18-MX_ADC1_Init-ADC1-false-HAL-true,19-MX_ADC3_Init-ADC3-false-HAL-true,20-MX_TIM1_Init-TIM1-false-HAL-true,21-MX_USART2_UART_Init-USART2-false-HAL-true RCC.48MHZClocksFreq_Value=48000000 RCC.AHBFreq_Value=168000000 RCC.APB1CLKDivider=RCC_HCLK_DIV4 @@ -272,8 +282,6 @@ SH.ADCx_IN1.0=ADC1_IN1,IN1 SH.ADCx_IN1.ConfNb=1 SH.COMP_DAC1_group.0=DAC_OUT1,DAC_OUT1 SH.COMP_DAC1_group.ConfNb=1 -SH.COMP_DAC2_group.0=DAC_OUT2,DAC_OUT2 -SH.COMP_DAC2_group.ConfNb=1 SH.FSMC_A18.0=FSMC_A18,A18_1 SH.FSMC_A18.ConfNb=1 SH.FSMC_D0_DA0.0=FSMC_D0,8b-d1 @@ -298,34 +306,42 @@ SH.FSMC_NWE.0=FSMC_NWE,Lcd1 SH.FSMC_NWE.ConfNb=1 SH.S_TIM14_CH1.0=TIM14_CH1,PWM Generation1 CH1 SH.S_TIM14_CH1.ConfNb=1 +SH.S_TIM1_CH2.0=TIM1_CH2,PWM Generation2 CH2 +SH.S_TIM1_CH2.ConfNb=1 +SH.S_TIM1_CH3.0=TIM1_CH3,PWM Generation3 CH3 +SH.S_TIM1_CH3.ConfNb=1 +SH.S_TIM2_CH3.0=TIM2_CH3,PWM Generation3 CH3 +SH.S_TIM2_CH3.ConfNb=1 SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4 SH.S_TIM2_CH4.ConfNb=1 +SH.S_TIM3_CH2.0=TIM3_CH2,PWM Generation2 CH2 +SH.S_TIM3_CH2.ConfNb=1 SH.S_TIM3_CH4.0=TIM3_CH4,PWM Generation4 CH4 SH.S_TIM3_CH4.ConfNb=1 -SH.S_TIM4_CH1.0=TIM4_CH1,Encoder_Interface +SH.S_TIM4_CH1.0=TIM4_CH1,PWM Generation1 CH1 SH.S_TIM4_CH1.ConfNb=1 -SH.S_TIM4_CH2.0=TIM4_CH2,Encoder_Interface -SH.S_TIM4_CH2.ConfNb=1 -SPI1.CalculateBaudRate=42.0 MBits/s -SPI1.Direction=SPI_DIRECTION_2LINES -SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate -SPI1.Mode=SPI_MODE_MASTER -SPI1.VirtualType=VM_MASTER SPI2.CalculateBaudRate=21.0 MBits/s SPI2.Direction=SPI_DIRECTION_2LINES SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate SPI2.Mode=SPI_MODE_MASTER SPI2.VirtualType=VM_MASTER +TIM1.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 +TIM1.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 +TIM1.IPParameters=Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3 TIM14.Channel=TIM_CHANNEL_1 TIM14.IPParameters=Channel +TIM2.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 -TIM2.IPParameters=Channel-PWM Generation4 CH4 +TIM2.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4 +TIM3.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 TIM3.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 -TIM3.IPParameters=Channel-PWM Generation4 CH4 +TIM3.IPParameters=Channel-PWM Generation4 CH4,Channel-PWM Generation2 CH2 +TIM4.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 +TIM4.IPParameters=Channel-PWM Generation1 CH1 USART1.IPParameters=VirtualMode USART1.VirtualMode=VM_ASYNC -USART3.IPParameters=VirtualMode -USART3.VirtualMode=VM_ASYNC +USART2.IPParameters=VirtualMode +USART2.VirtualMode=VM_ASYNC USB_OTG_FS.IPParameters=VirtualMode USB_OTG_FS.VirtualMode=Device_Only VP_IWDG_VS_IWDG.Mode=IWDG_Activate @@ -340,6 +356,8 @@ VP_TIM13_VS_ClockSourceINT.Mode=Enable_Timer VP_TIM13_VS_ClockSourceINT.Signal=TIM13_VS_ClockSourceINT VP_TIM14_VS_ClockSourceINT.Mode=Enable_Timer VP_TIM14_VS_ClockSourceINT.Signal=TIM14_VS_ClockSourceINT +VP_TIM1_VS_ClockSourceINT.Mode=Internal +VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT VP_TIM2_VS_ClockSourceINT.Mode=Internal VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT VP_TIM3_VS_ClockSourceINT.Mode=Internal diff --git a/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h index 9cfd3058cd7..48376792950 100644 --- a/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h +++ b/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -214,7 +214,7 @@ #define MAC_ADDR5 0U /* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE /* buffer size for receive */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ #define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ diff --git a/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Inc/stm32f4xx_it.h b/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Inc/stm32f4xx_it.h index 1e55ae743fa..21eff44484f 100644 --- a/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Inc/stm32f4xx_it.h +++ b/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Inc/stm32f4xx_it.h @@ -71,7 +71,6 @@ void SVC_Handler(void); void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); -void SPI1_IRQHandler(void); void USART1_IRQHandler(void); void OTG_FS_IRQHandler(void); /* USER CODE BEGIN EFP */ diff --git a/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Src/main.c deleted file mode 100644 index 57c88a932a1..00000000000 --- a/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Src/main.c +++ /dev/null @@ -1,981 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : main.c - * @brief : Main program body - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ -/* Includes ------------------------------------------------------------------*/ -#include "main.h" - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN PTD */ - -/* USER CODE END PTD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ - -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ -ADC_HandleTypeDef hadc1; - -DAC_HandleTypeDef hdac; - -IWDG_HandleTypeDef hiwdg; - -RTC_HandleTypeDef hrtc; - -SD_HandleTypeDef hsd; - -SPI_HandleTypeDef hspi1; -SPI_HandleTypeDef hspi2; - -TIM_HandleTypeDef htim2; -TIM_HandleTypeDef htim3; -TIM_HandleTypeDef htim4; -TIM_HandleTypeDef htim11; -TIM_HandleTypeDef htim13; -TIM_HandleTypeDef htim14; - -UART_HandleTypeDef huart1; -UART_HandleTypeDef huart3; - -PCD_HandleTypeDef hpcd_USB_OTG_FS; - -SRAM_HandleTypeDef hsram1; - -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -void SystemClock_Config(void); -static void MX_GPIO_Init(void); -static void MX_USART1_UART_Init(void); -static void MX_SPI1_Init(void); -static void MX_USART3_UART_Init(void); -static void MX_RTC_Init(void); -static void MX_IWDG_Init(void); -static void MX_TIM14_Init(void); -static void MX_TIM13_Init(void); -static void MX_TIM11_Init(void); -static void MX_SDIO_SD_Init(void); -static void MX_TIM2_Init(void); -static void MX_SPI2_Init(void); -static void MX_TIM4_Init(void); -static void MX_USB_OTG_FS_PCD_Init(void); -static void MX_FSMC_Init(void); -static void MX_DAC_Init(void); -static void MX_TIM3_Init(void); -static void MX_ADC1_Init(void); -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/** - * @brief The application entry point. - * @retval int - */ -int main(void) -{ - /* USER CODE BEGIN 1 */ - - /* USER CODE END 1 */ - - /* MCU Configuration--------------------------------------------------------*/ - - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - - /* USER CODE BEGIN Init */ - - /* USER CODE END Init */ - - /* Configure the system clock */ - SystemClock_Config(); - - /* USER CODE BEGIN SysInit */ - - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_USART1_UART_Init(); - MX_SPI1_Init(); - MX_USART3_UART_Init(); - MX_RTC_Init(); - MX_IWDG_Init(); - MX_TIM14_Init(); - MX_TIM13_Init(); - MX_TIM11_Init(); - MX_SDIO_SD_Init(); - MX_TIM2_Init(); - MX_SPI2_Init(); - MX_TIM4_Init(); - MX_USB_OTG_FS_PCD_Init(); - MX_FSMC_Init(); - MX_DAC_Init(); - MX_TIM3_Init(); - MX_ADC1_Init(); - /* USER CODE BEGIN 2 */ - - /* USER CODE END 2 */ - - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ - while (1) - { - /* USER CODE END WHILE */ - - /* USER CODE BEGIN 3 */ - } - /* USER CODE END 3 */ -} - -/** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - - /** Configure the main internal regulator output voltage - */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE - |RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 4; - RCC_OscInitStruct.PLL.PLLN = 168; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 7; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) - { - Error_Handler(); - } -} - -/** - * @brief ADC1 Initialization Function - * @param None - * @retval None - */ -static void MX_ADC1_Init(void) -{ - - /* USER CODE BEGIN ADC1_Init 0 */ - - /* USER CODE END ADC1_Init 0 */ - - ADC_ChannelConfTypeDef sConfig = {0}; - - /* USER CODE BEGIN ADC1_Init 1 */ - - /* USER CODE END ADC1_Init 1 */ - - /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) - */ - hadc1.Instance = ADC1; - hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; - hadc1.Init.Resolution = ADC_RESOLUTION_12B; - hadc1.Init.ScanConvMode = DISABLE; - hadc1.Init.ContinuousConvMode = DISABLE; - hadc1.Init.DiscontinuousConvMode = DISABLE; - hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; - hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - hadc1.Init.NbrOfConversion = 1; - hadc1.Init.DMAContinuousRequests = DISABLE; - hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; - if (HAL_ADC_Init(&hadc1) != HAL_OK) - { - Error_Handler(); - } - - /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. - */ - sConfig.Channel = ADC_CHANNEL_1; - sConfig.Rank = 1; - sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; - if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN ADC1_Init 2 */ - - /* USER CODE END ADC1_Init 2 */ - -} - -/** - * @brief DAC Initialization Function - * @param None - * @retval None - */ -static void MX_DAC_Init(void) -{ - - /* USER CODE BEGIN DAC_Init 0 */ - - /* USER CODE END DAC_Init 0 */ - - DAC_ChannelConfTypeDef sConfig = {0}; - - /* USER CODE BEGIN DAC_Init 1 */ - - /* USER CODE END DAC_Init 1 */ - - /** DAC Initialization - */ - hdac.Instance = DAC; - if (HAL_DAC_Init(&hdac) != HAL_OK) - { - Error_Handler(); - } - - /** DAC channel OUT1 config - */ - sConfig.DAC_Trigger = DAC_TRIGGER_NONE; - sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; - if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_1) != HAL_OK) - { - Error_Handler(); - } - - /** DAC channel OUT2 config - */ - if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_2) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN DAC_Init 2 */ - - /* USER CODE END DAC_Init 2 */ - -} - -/** - * @brief IWDG Initialization Function - * @param None - * @retval None - */ -static void MX_IWDG_Init(void) -{ - - /* USER CODE BEGIN IWDG_Init 0 */ - - /* USER CODE END IWDG_Init 0 */ - - /* USER CODE BEGIN IWDG_Init 1 */ - - /* USER CODE END IWDG_Init 1 */ - hiwdg.Instance = IWDG; - hiwdg.Init.Prescaler = IWDG_PRESCALER_4; - hiwdg.Init.Reload = 4095; - if (HAL_IWDG_Init(&hiwdg) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN IWDG_Init 2 */ - - /* USER CODE END IWDG_Init 2 */ - -} - -/** - * @brief RTC Initialization Function - * @param None - * @retval None - */ -static void MX_RTC_Init(void) -{ - - /* USER CODE BEGIN RTC_Init 0 */ - - /* USER CODE END RTC_Init 0 */ - - /* USER CODE BEGIN RTC_Init 1 */ - - /* USER CODE END RTC_Init 1 */ - - /** Initialize RTC Only - */ - hrtc.Instance = RTC; - hrtc.Init.HourFormat = RTC_HOURFORMAT_24; - hrtc.Init.AsynchPrediv = 127; - hrtc.Init.SynchPrediv = 255; - hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; - hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - if (HAL_RTC_Init(&hrtc) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN RTC_Init 2 */ - - /* USER CODE END RTC_Init 2 */ - -} - -/** - * @brief SDIO Initialization Function - * @param None - * @retval None - */ -static void MX_SDIO_SD_Init(void) -{ - - /* USER CODE BEGIN SDIO_Init 0 */ - - /* USER CODE END SDIO_Init 0 */ - - /* USER CODE BEGIN SDIO_Init 1 */ - - /* USER CODE END SDIO_Init 1 */ - hsd.Instance = SDIO; - hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; - hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; - hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; - hsd.Init.BusWide = SDIO_BUS_WIDE_4B; - hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; - hsd.Init.ClockDiv = 0; - if (HAL_SD_Init(&hsd) != HAL_OK) - { - Error_Handler(); - } - if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN SDIO_Init 2 */ - - /* USER CODE END SDIO_Init 2 */ - -} - -/** - * @brief SPI1 Initialization Function - * @param None - * @retval None - */ -static void MX_SPI1_Init(void) -{ - - /* USER CODE BEGIN SPI1_Init 0 */ - - /* USER CODE END SPI1_Init 0 */ - - /* USER CODE BEGIN SPI1_Init 1 */ - - /* USER CODE END SPI1_Init 1 */ - /* SPI1 parameter configuration*/ - hspi1.Instance = SPI1; - hspi1.Init.Mode = SPI_MODE_MASTER; - hspi1.Init.Direction = SPI_DIRECTION_2LINES; - hspi1.Init.DataSize = SPI_DATASIZE_8BIT; - hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; - hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; - hspi1.Init.NSS = SPI_NSS_SOFT; - hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; - hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; - hspi1.Init.TIMode = SPI_TIMODE_DISABLE; - hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; - hspi1.Init.CRCPolynomial = 10; - if (HAL_SPI_Init(&hspi1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN SPI1_Init 2 */ - - /* USER CODE END SPI1_Init 2 */ - -} - -/** - * @brief SPI2 Initialization Function - * @param None - * @retval None - */ -static void MX_SPI2_Init(void) -{ - - /* USER CODE BEGIN SPI2_Init 0 */ - - /* USER CODE END SPI2_Init 0 */ - - /* USER CODE BEGIN SPI2_Init 1 */ - - /* USER CODE END SPI2_Init 1 */ - /* SPI2 parameter configuration*/ - hspi2.Instance = SPI2; - hspi2.Init.Mode = SPI_MODE_MASTER; - hspi2.Init.Direction = SPI_DIRECTION_2LINES; - hspi2.Init.DataSize = SPI_DATASIZE_8BIT; - hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; - hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; - hspi2.Init.NSS = SPI_NSS_SOFT; - hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; - hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; - hspi2.Init.TIMode = SPI_TIMODE_DISABLE; - hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; - hspi2.Init.CRCPolynomial = 10; - if (HAL_SPI_Init(&hspi2) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN SPI2_Init 2 */ - - /* USER CODE END SPI2_Init 2 */ - -} - -/** - * @brief TIM2 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM2_Init(void) -{ - - /* USER CODE BEGIN TIM2_Init 0 */ - - /* USER CODE END TIM2_Init 0 */ - - TIM_ClockConfigTypeDef sClockSourceConfig = {0}; - TIM_MasterConfigTypeDef sMasterConfig = {0}; - TIM_OC_InitTypeDef sConfigOC = {0}; - - /* USER CODE BEGIN TIM2_Init 1 */ - - /* USER CODE END TIM2_Init 1 */ - htim2.Instance = TIM2; - htim2.Init.Prescaler = 0; - htim2.Init.CounterMode = TIM_COUNTERMODE_UP; - htim2.Init.Period = 4294967295; - htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim2) != HAL_OK) - { - Error_Handler(); - } - sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) - { - Error_Handler(); - } - if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) - { - Error_Handler(); - } - sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) - { - Error_Handler(); - } - sConfigOC.OCMode = TIM_OCMODE_PWM1; - sConfigOC.Pulse = 0; - sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; - sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; - if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN TIM2_Init 2 */ - - /* USER CODE END TIM2_Init 2 */ - HAL_TIM_MspPostInit(&htim2); - -} - -/** - * @brief TIM3 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM3_Init(void) -{ - - /* USER CODE BEGIN TIM3_Init 0 */ - - /* USER CODE END TIM3_Init 0 */ - - TIM_ClockConfigTypeDef sClockSourceConfig = {0}; - TIM_MasterConfigTypeDef sMasterConfig = {0}; - TIM_OC_InitTypeDef sConfigOC = {0}; - - /* USER CODE BEGIN TIM3_Init 1 */ - - /* USER CODE END TIM3_Init 1 */ - htim3.Instance = TIM3; - htim3.Init.Prescaler = 0; - htim3.Init.CounterMode = TIM_COUNTERMODE_UP; - htim3.Init.Period = 65535; - htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim3) != HAL_OK) - { - Error_Handler(); - } - sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) - { - Error_Handler(); - } - if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) - { - Error_Handler(); - } - sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) - { - Error_Handler(); - } - sConfigOC.OCMode = TIM_OCMODE_PWM1; - sConfigOC.Pulse = 0; - sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; - sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; - if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN TIM3_Init 2 */ - - /* USER CODE END TIM3_Init 2 */ - HAL_TIM_MspPostInit(&htim3); - -} - -/** - * @brief TIM4 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM4_Init(void) -{ - - /* USER CODE BEGIN TIM4_Init 0 */ - - /* USER CODE END TIM4_Init 0 */ - - TIM_Encoder_InitTypeDef sConfig = {0}; - TIM_MasterConfigTypeDef sMasterConfig = {0}; - - /* USER CODE BEGIN TIM4_Init 1 */ - - /* USER CODE END TIM4_Init 1 */ - htim4.Instance = TIM4; - htim4.Init.Prescaler = 0; - htim4.Init.CounterMode = TIM_COUNTERMODE_UP; - htim4.Init.Period = 65535; - htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - sConfig.EncoderMode = TIM_ENCODERMODE_TI1; - sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; - sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; - sConfig.IC1Prescaler = TIM_ICPSC_DIV1; - sConfig.IC1Filter = 0; - sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; - sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; - sConfig.IC2Prescaler = TIM_ICPSC_DIV1; - sConfig.IC2Filter = 0; - if (HAL_TIM_Encoder_Init(&htim4, &sConfig) != HAL_OK) - { - Error_Handler(); - } - sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN TIM4_Init 2 */ - - /* USER CODE END TIM4_Init 2 */ - -} - -/** - * @brief TIM11 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM11_Init(void) -{ - - /* USER CODE BEGIN TIM11_Init 0 */ - - /* USER CODE END TIM11_Init 0 */ - - /* USER CODE BEGIN TIM11_Init 1 */ - - /* USER CODE END TIM11_Init 1 */ - htim11.Instance = TIM11; - htim11.Init.Prescaler = 0; - htim11.Init.CounterMode = TIM_COUNTERMODE_UP; - htim11.Init.Period = 65535; - htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim11) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN TIM11_Init 2 */ - - /* USER CODE END TIM11_Init 2 */ - -} - -/** - * @brief TIM13 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM13_Init(void) -{ - - /* USER CODE BEGIN TIM13_Init 0 */ - - /* USER CODE END TIM13_Init 0 */ - - /* USER CODE BEGIN TIM13_Init 1 */ - - /* USER CODE END TIM13_Init 1 */ - htim13.Instance = TIM13; - htim13.Init.Prescaler = 0; - htim13.Init.CounterMode = TIM_COUNTERMODE_UP; - htim13.Init.Period = 65535; - htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim13.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim13) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN TIM13_Init 2 */ - - /* USER CODE END TIM13_Init 2 */ - -} - -/** - * @brief TIM14 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM14_Init(void) -{ - - /* USER CODE BEGIN TIM14_Init 0 */ - - /* USER CODE END TIM14_Init 0 */ - - TIM_OC_InitTypeDef sConfigOC = {0}; - - /* USER CODE BEGIN TIM14_Init 1 */ - - /* USER CODE END TIM14_Init 1 */ - htim14.Instance = TIM14; - htim14.Init.Prescaler = 0; - htim14.Init.CounterMode = TIM_COUNTERMODE_UP; - htim14.Init.Period = 65535; - htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim14) != HAL_OK) - { - Error_Handler(); - } - if (HAL_TIM_PWM_Init(&htim14) != HAL_OK) - { - Error_Handler(); - } - sConfigOC.OCMode = TIM_OCMODE_PWM1; - sConfigOC.Pulse = 0; - sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; - sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; - if (HAL_TIM_PWM_ConfigChannel(&htim14, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN TIM14_Init 2 */ - - /* USER CODE END TIM14_Init 2 */ - HAL_TIM_MspPostInit(&htim14); - -} - -/** - * @brief USART1 Initialization Function - * @param None - * @retval None - */ -static void MX_USART1_UART_Init(void) -{ - - /* USER CODE BEGIN USART1_Init 0 */ - - /* USER CODE END USART1_Init 0 */ - - /* USER CODE BEGIN USART1_Init 1 */ - - /* USER CODE END USART1_Init 1 */ - huart1.Instance = USART1; - huart1.Init.BaudRate = 115200; - huart1.Init.WordLength = UART_WORDLENGTH_8B; - huart1.Init.StopBits = UART_STOPBITS_1; - huart1.Init.Parity = UART_PARITY_NONE; - huart1.Init.Mode = UART_MODE_TX_RX; - huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart1.Init.OverSampling = UART_OVERSAMPLING_16; - if (HAL_UART_Init(&huart1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN USART1_Init 2 */ - - /* USER CODE END USART1_Init 2 */ - -} - -/** - * @brief USART3 Initialization Function - * @param None - * @retval None - */ -static void MX_USART3_UART_Init(void) -{ - - /* USER CODE BEGIN USART3_Init 0 */ - - /* USER CODE END USART3_Init 0 */ - - /* USER CODE BEGIN USART3_Init 1 */ - - /* USER CODE END USART3_Init 1 */ - huart3.Instance = USART3; - huart3.Init.BaudRate = 115200; - huart3.Init.WordLength = UART_WORDLENGTH_8B; - huart3.Init.StopBits = UART_STOPBITS_1; - huart3.Init.Parity = UART_PARITY_NONE; - huart3.Init.Mode = UART_MODE_TX_RX; - huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart3.Init.OverSampling = UART_OVERSAMPLING_16; - if (HAL_UART_Init(&huart3) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN USART3_Init 2 */ - - /* USER CODE END USART3_Init 2 */ - -} - -/** - * @brief USB_OTG_FS Initialization Function - * @param None - * @retval None - */ -static void MX_USB_OTG_FS_PCD_Init(void) -{ - - /* USER CODE BEGIN USB_OTG_FS_Init 0 */ - - /* USER CODE END USB_OTG_FS_Init 0 */ - - /* USER CODE BEGIN USB_OTG_FS_Init 1 */ - - /* USER CODE END USB_OTG_FS_Init 1 */ - hpcd_USB_OTG_FS.Instance = USB_OTG_FS; - hpcd_USB_OTG_FS.Init.dev_endpoints = 4; - hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; - hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; - hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; - hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; - hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; - hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; - hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; - hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; - if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN USB_OTG_FS_Init 2 */ - - /* USER CODE END USB_OTG_FS_Init 2 */ - -} - -/** - * @brief GPIO Initialization Function - * @param None - * @retval None - */ -static void MX_GPIO_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; -/* USER CODE BEGIN MX_GPIO_Init_1 */ -/* USER CODE END MX_GPIO_Init_1 */ - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOE_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - __HAL_RCC_GPIOG_CLK_ENABLE(); - - /*Configure GPIO pins : PG11 PG13 PG14 */ - GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_13|GPIO_PIN_14; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF11_ETH; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - -/* USER CODE BEGIN MX_GPIO_Init_2 */ -/* USER CODE END MX_GPIO_Init_2 */ -} - -/* FSMC initialization function */ -static void MX_FSMC_Init(void) -{ - - /* USER CODE BEGIN FSMC_Init 0 */ - - /* USER CODE END FSMC_Init 0 */ - - FSMC_NORSRAM_TimingTypeDef Timing = {0}; - - /* USER CODE BEGIN FSMC_Init 1 */ - - /* USER CODE END FSMC_Init 1 */ - - /** Perform the SRAM1 memory initialization sequence - */ - hsram1.Instance = FSMC_NORSRAM_DEVICE; - hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; - /* hsram1.Init */ - hsram1.Init.NSBank = FSMC_NORSRAM_BANK3; - hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; - hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; - hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_8; - hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; - hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; - hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; - hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; - hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; - hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; - hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE; - hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; - hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; - hsram1.Init.PageSize = FSMC_PAGE_SIZE_NONE; - /* Timing */ - Timing.AddressSetupTime = 15; - Timing.AddressHoldTime = 15; - Timing.DataSetupTime = 255; - Timing.BusTurnAroundDuration = 15; - Timing.CLKDivision = 16; - Timing.DataLatency = 17; - Timing.AccessMode = FSMC_ACCESS_MODE_A; - /* ExtTiming */ - - if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK) - { - Error_Handler( ); - } - - /* USER CODE BEGIN FSMC_Init 2 */ - - /* USER CODE END FSMC_Init 2 */ -} - -/* USER CODE BEGIN 4 */ - -/* USER CODE END 4 */ - -/** - * @brief This function is executed in case of error occurrence. - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - __disable_irq(); - while (1) - { - } - /* USER CODE END Error_Handler_Debug */ -} - -#ifdef USE_FULL_ASSERT -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t *file, uint32_t line) -{ - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ -} -#endif /* USE_FULL_ASSERT */ diff --git a/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index b9bf6b75b86..ca00ce6ef72 100644 --- a/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -41,7 +41,6 @@ /* Includes ------------------------------------------------------------------*/ #include "main.h" - /* USER CODE BEGIN Includes */ #include /* USER CODE END Includes */ @@ -81,11 +80,12 @@ /* USER CODE END 0 */ void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); - /** + /** * Initializes the Global MSP. */ void HAL_MspInit(void) { + /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ @@ -130,6 +130,30 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspInit 1 */ } + else if(hadc->Instance==ADC3) + { + /* USER CODE BEGIN ADC3_MspInit 0 */ + + /* USER CODE END ADC3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC3_CLK_ENABLE(); + + __HAL_RCC_GPIOF_CLK_ENABLE(); + /**ADC3 GPIO Configuration + PF4 ------> ADC3_IN14 + PF5 ------> ADC3_IN15 + PF6 ------> ADC3_IN4 + PF7 ------> ADC3_IN5 + */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC3_MspInit 1 */ + + /* USER CODE END ADC3_MspInit 1 */ + } } @@ -158,6 +182,26 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /* USER CODE END ADC1_MspDeInit 1 */ } + else if(hadc->Instance==ADC3) + { + /* USER CODE BEGIN ADC3_MspDeInit 0 */ + + /* USER CODE END ADC3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC3_CLK_DISABLE(); + + /**ADC3 GPIO Configuration + PF4 ------> ADC3_IN14 + PF5 ------> ADC3_IN15 + PF6 ------> ADC3_IN4 + PF7 ------> ADC3_IN5 + */ + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); + + /* USER CODE BEGIN ADC3_MspDeInit 1 */ + + /* USER CODE END ADC3_MspDeInit 1 */ + } } @@ -181,9 +225,8 @@ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) __HAL_RCC_GPIOA_CLK_ENABLE(); /**DAC GPIO Configuration PA4 ------> DAC_OUT1 - PA5 ------> DAC_OUT2 */ - GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Pin = GPIO_PIN_4; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); @@ -213,9 +256,8 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) /**DAC GPIO Configuration PA4 ------> DAC_OUT1 - PA5 ------> DAC_OUT2 */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4|GPIO_PIN_5); + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4); /* USER CODE BEGIN DAC_MspDeInit 1 */ @@ -373,35 +415,7 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(hspi->Instance==SPI1) - { - /* USER CODE BEGIN SPI1_MspInit 0 */ - - /* USER CODE END SPI1_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_SPI1_CLK_ENABLE(); - - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI1 GPIO Configuration - PB3 ------> SPI1_SCK - PB4 ------> SPI1_MISO - PB5 ------> SPI1_MOSI - */ - GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* SPI1 interrupt Init */ - HAL_NVIC_SetPriority(SPI1_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(SPI1_IRQn); - /* USER CODE BEGIN SPI1_MspInit 1 */ - - /* USER CODE END SPI1_MspInit 1 */ - } - else if(hspi->Instance==SPI2) + if(hspi->Instance==SPI2) { /* USER CODE BEGIN SPI2_MspInit 0 */ @@ -445,28 +459,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) */ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) { - if(hspi->Instance==SPI1) - { - /* USER CODE BEGIN SPI1_MspDeInit 0 */ - - /* USER CODE END SPI1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration - PB3 ------> SPI1_SCK - PB4 ------> SPI1_MISO - PB5 ------> SPI1_MOSI - */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5); - - /* SPI1 interrupt DeInit */ - HAL_NVIC_DisableIRQ(SPI1_IRQn); - /* USER CODE BEGIN SPI1_MspDeInit 1 */ - - /* USER CODE END SPI1_MspDeInit 1 */ - } - else if(hspi->Instance==SPI2) + if(hspi->Instance==SPI2) { /* USER CODE BEGIN SPI2_MspDeInit 0 */ @@ -498,7 +491,18 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { - if(htim_base->Instance==TIM2) + if(htim_base->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspInit 0 */ + + /* USER CODE END TIM1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM1_CLK_ENABLE(); + /* USER CODE BEGIN TIM1_MspInit 1 */ + + /* USER CODE END TIM1_MspInit 1 */ + } + else if(htim_base->Instance==TIM2) { /* USER CODE BEGIN TIM2_MspInit 0 */ @@ -557,34 +561,20 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) } /** -* @brief TIM_Encoder MSP Initialization +* @brief TIM_PWM MSP Initialization * This function configures the hardware resources used in this example -* @param htim_encoder: TIM_Encoder handle pointer +* @param htim_pwm: TIM_PWM handle pointer * @retval None */ -void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(htim_encoder->Instance==TIM4) + if(htim_pwm->Instance==TIM4) { /* USER CODE BEGIN TIM4_MspInit 0 */ /* USER CODE END TIM4_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM4_CLK_ENABLE(); - - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**TIM4 GPIO Configuration - PB6 ------> TIM4_CH1 - PB7 ------> TIM4_CH2 - */ - GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ @@ -595,21 +585,44 @@ void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(htim->Instance==TIM2) + if(htim->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspPostInit 0 */ + + /* USER CODE END TIM1_MspPostInit 0 */ + __HAL_RCC_GPIOE_CLK_ENABLE(); + /**TIM1 GPIO Configuration + PE11 ------> TIM1_CH2 + PE13 ------> TIM1_CH3 + */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM1_MspPostInit 1 */ + + /* USER CODE END TIM1_MspPostInit 1 */ + } + else if(htim->Instance==TIM2) { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ - __HAL_RCC_GPIOA_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); /**TIM2 GPIO Configuration - PA3 ------> TIM2_CH4 + PB10 ------> TIM2_CH3 + PB11 ------> TIM2_CH4 */ - GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /* USER CODE BEGIN TIM2_MspPostInit 1 */ @@ -621,10 +634,19 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE END TIM3_MspPostInit 0 */ + __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); /**TIM3 GPIO Configuration + PA7 ------> TIM3_CH2 PB1 ------> TIM3_CH4 */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + GPIO_InitStruct.Pin = GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; @@ -636,6 +658,27 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) /* USER CODE END TIM3_MspPostInit 1 */ } + else if(htim->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspPostInit 0 */ + + /* USER CODE END TIM4_MspPostInit 0 */ + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**TIM4 GPIO Configuration + PD12 ------> TIM4_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM4_MspPostInit 1 */ + + /* USER CODE END TIM4_MspPostInit 1 */ + } else if(htim->Instance==TIM14) { /* USER CODE BEGIN TIM14_MspPostInit 0 */ @@ -667,7 +710,18 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) */ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) { - if(htim_base->Instance==TIM2) + if(htim_base->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspDeInit 0 */ + + /* USER CODE END TIM1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM1_CLK_DISABLE(); + /* USER CODE BEGIN TIM1_MspDeInit 1 */ + + /* USER CODE END TIM1_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM2) { /* USER CODE BEGIN TIM2_MspDeInit 0 */ @@ -726,27 +780,20 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) } /** -* @brief TIM_Encoder MSP De-Initialization +* @brief TIM_PWM MSP De-Initialization * This function freeze the hardware resources used in this example -* @param htim_encoder: TIM_Encoder handle pointer +* @param htim_pwm: TIM_PWM handle pointer * @retval None */ -void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* htim_encoder) +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm) { - if(htim_encoder->Instance==TIM4) + if(htim_pwm->Instance==TIM4) { /* USER CODE BEGIN TIM4_MspDeInit 0 */ /* USER CODE END TIM4_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM4_CLK_DISABLE(); - - /**TIM4 GPIO Configuration - PB6 ------> TIM4_CH1 - PB7 ------> TIM4_CH2 - */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7); - /* USER CODE BEGIN TIM4_MspDeInit 1 */ /* USER CODE END TIM4_MspDeInit 1 */ @@ -790,29 +837,29 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 1 */ } - else if(huart->Instance==USART3) + else if(huart->Instance==USART2) { - /* USER CODE BEGIN USART3_MspInit 0 */ + /* USER CODE BEGIN USART2_MspInit 0 */ - /* USER CODE END USART3_MspInit 0 */ + /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ - __HAL_RCC_USART3_CLK_ENABLE(); + __HAL_RCC_USART2_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**USART3 GPIO Configuration - PB10 ------> USART3_TX - PB11 ------> USART3_RX + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX */ - GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF7_USART3; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - /* USER CODE BEGIN USART3_MspInit 1 */ + /* USER CODE BEGIN USART2_MspInit 1 */ - /* USER CODE END USART3_MspInit 1 */ + /* USER CODE END USART2_MspInit 1 */ } } @@ -845,23 +892,23 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 1 */ } - else if(huart->Instance==USART3) + else if(huart->Instance==USART2) { - /* USER CODE BEGIN USART3_MspDeInit 0 */ + /* USER CODE BEGIN USART2_MspDeInit 0 */ - /* USER CODE END USART3_MspDeInit 0 */ + /* USER CODE END USART2_MspDeInit 0 */ /* Peripheral clock disable */ - __HAL_RCC_USART3_CLK_DISABLE(); + __HAL_RCC_USART2_CLK_DISABLE(); - /**USART3 GPIO Configuration - PB10 ------> USART3_TX - PB11 ------> USART3_RX + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11); + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); - /* USER CODE BEGIN USART3_MspDeInit 1 */ + /* USER CODE BEGIN USART2_MspDeInit 1 */ - /* USER CODE END USART3_MspDeInit 1 */ + /* USER CODE END USART2_MspDeInit 1 */ } } diff --git a/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Src/stm32f4xx_it.c b/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Src/stm32f4xx_it.c index 83cc67f0c0e..51bf690c39c 100644 --- a/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Src/stm32f4xx_it.c +++ b/bsp/stm32/stm32f407-rt-spark/board/CubeMX_Config/Src/stm32f4xx_it.c @@ -71,7 +71,6 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ -extern SPI_HandleTypeDef hspi1; extern UART_HandleTypeDef huart1; extern PCD_HandleTypeDef hpcd_USB_OTG_FS; /* USER CODE BEGIN EV */ @@ -214,20 +213,6 @@ void SysTick_Handler(void) /* please refer to the startup file (startup_stm32f4xx.s). */ /******************************************************************************/ -/** - * @brief This function handles SPI1 global interrupt. - */ -void SPI1_IRQHandler(void) -{ - /* USER CODE BEGIN SPI1_IRQn 0 */ - - /* USER CODE END SPI1_IRQn 0 */ - HAL_SPI_IRQHandler(&hspi1); - /* USER CODE BEGIN SPI1_IRQn 1 */ - - /* USER CODE END SPI1_IRQn 1 */ -} - /** * @brief This function handles USART1 global interrupt. */ diff --git a/bsp/stm32/stm32f407-rt-spark/board/Kconfig b/bsp/stm32/stm32f407-rt-spark/board/Kconfig index b698018ea44..715194f2053 100644 --- a/bsp/stm32/stm32f407-rt-spark/board/Kconfig +++ b/bsp/stm32/stm32f407-rt-spark/board/Kconfig @@ -2,6 +2,36 @@ menu "Hardware Drivers Config" menu "Onboard Peripheral Drivers" + config BSP_USING_ARDUINO + bool "Compatible with Arduino Ecosystem (RTduino)" + select PKG_USING_RTDUINO + select BSP_USING_STLINK_TO_USART + select BSP_USING_UART1 + select BSP_USING_UART2 + select BSP_USING_GPIO + select BSP_USING_ADC + select BSP_USING_ADC3 + select BSP_USING_DAC + select BSP_USING_DAC1 + select BSP_USING_PWM + select BSP_USING_PWM1 + select BSP_USING_PWM1_CH2 + select BSP_USING_PWM1_CH3 + select BSP_USING_PWM2 + select BSP_USING_PWM2_CH3 + select BSP_USING_PWM2_CH4 + select BSP_USING_PWM4 + select BSP_USING_PWM4_CH1 + select BSP_USING_I2C + select BSP_USING_I2C4 + select BSP_USING_I2C5 + select BSP_USING_SOFT_SPI + select BSP_USING_SOFT_SPI1 + imply RTDUINO_USING_SERVO + imply RTDUINO_USING_WIRE + imply RTDUINO_USING_SPI + default n + config BSP_USING_USB_TO_USART bool "Enable USB TO USART (uart1)" select BSP_USING_UART @@ -30,7 +60,7 @@ menu "Onboard Peripheral Drivers" comment "set rts pin number " config BSP_RS485_RTS_PIN int "RS485 rts pin number" - range 1 176 + range 0 143 default 104 config RS485_UART_DEVICE_NAME @@ -363,10 +393,24 @@ menu "On-chip Peripheral Drivers" default n select RT_USING_PWM if BSP_USING_PWM + menuconfig BSP_USING_PWM1 + bool "Enable timer1 output PWM" + default n + if BSP_USING_PWM1 + config BSP_USING_PWM1_CH2 + bool "Enable PWM1 channel2" + default n + config BSP_USING_PWM1_CH3 + bool "Enable PWM1 channel3" + default n + endif menuconfig BSP_USING_PWM2 bool "Enable timer2 output PWM" default n if BSP_USING_PWM2 + config BSP_USING_PWM2_CH3 + bool "Enable PWM2 channel3" + default n config BSP_USING_PWM2_CH4 bool "Enable PWM2 channel4" default n @@ -384,6 +428,14 @@ menu "On-chip Peripheral Drivers" bool "Enable PWM3 channel4" default n endif + menuconfig BSP_USING_PWM4 + bool "Enable timer4 output PWM" + default n + if BSP_USING_PWM4 + config BSP_USING_PWM4_CH1 + bool "Enable PWM4 channel1" + default n + endif menuconfig BSP_USING_PWM14 bool "Enable timer14 output PWM" default n @@ -410,17 +462,17 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_SOFT_SPI1 config BSP_S_SPI1_SCK_PIN - int "soft spi1 sck pin number" - range 1 176 - default 16 + int "soft spi1 sck pin number(G,5)" + range 0 143 + default 101 config BSP_S_SPI1_MISO_PIN - int "soft spi1 miso pin number" - range 1 176 - default 18 + int "soft spi1 miso pin numbe(G,3)" + range 0 143 + default 99 config BSP_S_SPI1_MOSI_PIN - int "soft spi1 mosi pin number" - range 1 176 - default 91 + int "soft spi1 mosi pin number(G,1)" + range 0 143 + default 97 endif menuconfig BSP_USING_SOFT_SPI2 @@ -429,15 +481,15 @@ menu "On-chip Peripheral Drivers" if BSP_USING_SOFT_SPI2 config BSP_S_SPI2_SCK_PIN int "soft spi2 sck pin number" - range 1 176 + range 0 143 default 19 config BSP_S_SPI2_MISO_PIN int "soft spi2 miso pin number" - range 1 176 + range 0 143 default 20 config BSP_S_SPI2_MOSI_PIN int "soft spi2 mosi pin number" - range 1 176 + range 0 143 default 21 endif endif @@ -486,6 +538,9 @@ menu "On-chip Peripheral Drivers" config BSP_USING_ADC1 bool "Enable ADC1" default n + config BSP_USING_ADC3 + bool "Enable ADC3" + default n endif menuconfig BSP_USING_I2C @@ -542,6 +597,40 @@ menu "On-chip Peripheral Drivers" range 0 143 default 65 endif + + menuconfig BSP_USING_I2C4 + bool "Enable I2C4 BUS for RTduino(software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C4 + config BSP_I2C4_SCL_PIN + int "i2c4 scl pin number, PG7" + range 0 143 + default 103 + config BSP_I2C4_SDA_PIN + int "I2C4 sda pin number, PD7" + range 0 143 + default 55 + endif + + menuconfig BSP_USING_I2C5 + bool "Enable I2C5 BUS for RTduino(software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C5 + config BSP_I2C5_SCL_PIN + int "i2c5 scl pin number, PB6" + range 0 143 + default 22 + config BSP_I2C5_SDA_PIN + int "I2C5 sda pin number, PB7" + range 0 143 + default 23 + endif endif config BSP_USING_ONBOARD_PM diff --git a/bsp/stm32/stm32f407-rt-spark/board/ports/drv_filesystem.c b/bsp/stm32/stm32f407-rt-spark/board/ports/drv_filesystem.c index 8f3f532662c..1ed53bf820c 100644 --- a/bsp/stm32/stm32f407-rt-spark/board/ports/drv_filesystem.c +++ b/bsp/stm32/stm32f407-rt-spark/board/ports/drv_filesystem.c @@ -30,7 +30,7 @@ #ifdef BSP_USING_SDCARD_FATFS static int onboard_sdcard_mount(void) { - if (dfs_mount("sd0", "/sdcard", "elm", 0, 0) == RT_EOK) + if (dfs_mount("sd", "/sdcard", "elm", 0, 0) == RT_EOK) { LOG_I("SD card mount to '/sdcard'"); } diff --git a/bsp/stm32/stm32f407-rt-spark/project.ewp b/bsp/stm32/stm32f407-rt-spark/project.ewp index c71f4c30a6d..b959fddcd50 100644 --- a/bsp/stm32/stm32f407-rt-spark/project.ewp +++ b/bsp/stm32/stm32f407-rt-spark/project.ewp @@ -2164,6 +2164,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f407-rt-spark/project.uvprojx b/bsp/stm32/stm32f407-rt-spark/project.uvprojx index 6c344cc264d..047c22fd8e3 100644 --- a/bsp/stm32/stm32f407-rt-spark/project.uvprojx +++ b/bsp/stm32/stm32f407-rt-spark/project.uvprojx @@ -543,6 +543,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f407-st-discovery/project.ewp b/bsp/stm32/stm32f407-st-discovery/project.ewp index 59ccb229a7b..8fc8b08cceb 100644 --- a/bsp/stm32/stm32f407-st-discovery/project.ewp +++ b/bsp/stm32/stm32f407-st-discovery/project.ewp @@ -2151,6 +2151,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f407-st-discovery/project.uvproj b/bsp/stm32/stm32f407-st-discovery/project.uvproj index 36f4eadbdf8..0f6d77df06b 100644 --- a/bsp/stm32/stm32f407-st-discovery/project.uvproj +++ b/bsp/stm32/stm32f407-st-discovery/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f407-st-discovery/project.uvprojx b/bsp/stm32/stm32f407-st-discovery/project.uvprojx index 505567895bc..22284288415 100644 --- a/bsp/stm32/stm32f407-st-discovery/project.uvprojx +++ b/bsp/stm32/stm32f407-st-discovery/project.uvprojx @@ -482,6 +482,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f410-st-nucleo/applications/arduino_pinout/SConscript b/bsp/stm32/stm32f410-st-nucleo/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32f410-st-nucleo/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32f410-st-nucleo/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32f410-st-nucleo/project.ewp b/bsp/stm32/stm32f410-st-nucleo/project.ewp index b163cb0d60b..f85f357c042 100644 --- a/bsp/stm32/stm32f410-st-nucleo/project.ewp +++ b/bsp/stm32/stm32f410-st-nucleo/project.ewp @@ -2152,6 +2152,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f410-st-nucleo/project.uvprojx b/bsp/stm32/stm32f410-st-nucleo/project.uvprojx index ccdbc5ad6ac..39ba7d9e270 100644 --- a/bsp/stm32/stm32f410-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32f410-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f411-atk-nano/project.ewp b/bsp/stm32/stm32f411-atk-nano/project.ewp index 7e42a5081fa..0b271365da9 100644 --- a/bsp/stm32/stm32f411-atk-nano/project.ewp +++ b/bsp/stm32/stm32f411-atk-nano/project.ewp @@ -2166,6 +2166,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f411-atk-nano/project.uvprojx b/bsp/stm32/stm32f411-atk-nano/project.uvprojx index 3be78f65d8a..203ab728ae6 100644 --- a/bsp/stm32/stm32f411-atk-nano/project.uvprojx +++ b/bsp/stm32/stm32f411-atk-nano/project.uvprojx @@ -540,6 +540,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + --c99 + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f411-st-nucleo/applications/arduino_pinout/SConscript b/bsp/stm32/stm32f411-st-nucleo/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32f411-st-nucleo/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32f411-st-nucleo/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32f411-st-nucleo/project.ewp b/bsp/stm32/stm32f411-st-nucleo/project.ewp index 843c1f9f1e7..094bda20f2c 100644 --- a/bsp/stm32/stm32f411-st-nucleo/project.ewp +++ b/bsp/stm32/stm32f411-st-nucleo/project.ewp @@ -2152,6 +2152,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f411-st-nucleo/project.uvprojx b/bsp/stm32/stm32f411-st-nucleo/project.uvprojx index 6290f033bfa..943be58d4b2 100644 --- a/bsp/stm32/stm32f411-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32f411-st-nucleo/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f411-weact-blackpill/applications/arduino_pinout/SConscript b/bsp/stm32/stm32f411-weact-blackpill/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32f411-weact-blackpill/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32f411-weact-blackpill/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32f411-weact-blackpill/project.ewp b/bsp/stm32/stm32f411-weact-blackpill/project.ewp index a435ebf1fc0..8c353a560ef 100644 --- a/bsp/stm32/stm32f411-weact-blackpill/project.ewp +++ b/bsp/stm32/stm32f411-weact-blackpill/project.ewp @@ -2228,6 +2228,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f411-weact-blackpill/project.uvprojx b/bsp/stm32/stm32f411-weact-blackpill/project.uvprojx index c4384bb3139..c9e3daf1424 100644 --- a/bsp/stm32/stm32f411-weact-blackpill/project.uvprojx +++ b/bsp/stm32/stm32f411-weact-blackpill/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f412-st-nucleo/applications/arduino_pinout/SConscript b/bsp/stm32/stm32f412-st-nucleo/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32f412-st-nucleo/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32f412-st-nucleo/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32f412-st-nucleo/project.ewp b/bsp/stm32/stm32f412-st-nucleo/project.ewp index 120acea0f85..8db94208ea5 100644 --- a/bsp/stm32/stm32f412-st-nucleo/project.ewp +++ b/bsp/stm32/stm32f412-st-nucleo/project.ewp @@ -2194,6 +2194,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f412-st-nucleo/project.uvprojx b/bsp/stm32/stm32f412-st-nucleo/project.uvprojx index 4bd4170e127..8b03c1f38b6 100644 --- a/bsp/stm32/stm32f412-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32f412-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f413-st-nucleo/project.ewp b/bsp/stm32/stm32f413-st-nucleo/project.ewp index 87a04a1fa1c..42875e60dcc 100644 --- a/bsp/stm32/stm32f413-st-nucleo/project.ewp +++ b/bsp/stm32/stm32f413-st-nucleo/project.ewp @@ -2151,6 +2151,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f413-st-nucleo/project.uvproj b/bsp/stm32/stm32f413-st-nucleo/project.uvproj index d5f34f307c1..bd523dc02f5 100644 --- a/bsp/stm32/stm32f413-st-nucleo/project.uvproj +++ b/bsp/stm32/stm32f413-st-nucleo/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f413-st-nucleo/project.uvprojx b/bsp/stm32/stm32f413-st-nucleo/project.uvprojx index ceedbc217d8..4df4f0fd2dc 100644 --- a/bsp/stm32/stm32f413-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32f413-st-nucleo/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f427-robomaster-a/applications/arduino_pinout/SConscript b/bsp/stm32/stm32f427-robomaster-a/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32f427-robomaster-a/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32f427-robomaster-a/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32f427-robomaster-a/project.ewp b/bsp/stm32/stm32f427-robomaster-a/project.ewp index aedcdf2a673..ec1de8ee447 100644 --- a/bsp/stm32/stm32f427-robomaster-a/project.ewp +++ b/bsp/stm32/stm32f427-robomaster-a/project.ewp @@ -2153,6 +2153,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f427-robomaster-a/project.uvproj b/bsp/stm32/stm32f427-robomaster-a/project.uvproj index 5440683dcc4..57f1fcf1c76 100644 --- a/bsp/stm32/stm32f427-robomaster-a/project.uvproj +++ b/bsp/stm32/stm32f427-robomaster-a/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f427-robomaster-a/project.uvprojx b/bsp/stm32/stm32f427-robomaster-a/project.uvprojx index 9be0b4dfed1..1f1b466fd0c 100644 --- a/bsp/stm32/stm32f427-robomaster-a/project.uvprojx +++ b/bsp/stm32/stm32f427-robomaster-a/project.uvprojx @@ -482,6 +482,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f429-armfly-v6/project.ewp b/bsp/stm32/stm32f429-armfly-v6/project.ewp index 2854922d4a4..238341a6146 100644 --- a/bsp/stm32/stm32f429-armfly-v6/project.ewp +++ b/bsp/stm32/stm32f429-armfly-v6/project.ewp @@ -2153,6 +2153,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f429-armfly-v6/project.uvproj b/bsp/stm32/stm32f429-armfly-v6/project.uvproj index 0e8ec723b71..e4c99d7b680 100644 --- a/bsp/stm32/stm32f429-armfly-v6/project.uvproj +++ b/bsp/stm32/stm32f429-armfly-v6/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f429-armfly-v6/project.uvprojx b/bsp/stm32/stm32f429-armfly-v6/project.uvprojx index be26f1cbf52..df81f04197b 100644 --- a/bsp/stm32/stm32f429-armfly-v6/project.uvprojx +++ b/bsp/stm32/stm32f429-armfly-v6/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f429-atk-apollo/project.ewp b/bsp/stm32/stm32f429-atk-apollo/project.ewp index c26cf286269..ed52e3e4633 100644 --- a/bsp/stm32/stm32f429-atk-apollo/project.ewp +++ b/bsp/stm32/stm32f429-atk-apollo/project.ewp @@ -2154,6 +2154,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f429-atk-apollo/project.uvproj b/bsp/stm32/stm32f429-atk-apollo/project.uvproj index 91d4f920c41..11ce149cce3 100644 --- a/bsp/stm32/stm32f429-atk-apollo/project.uvproj +++ b/bsp/stm32/stm32f429-atk-apollo/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f429-atk-apollo/project.uvprojx b/bsp/stm32/stm32f429-atk-apollo/project.uvprojx index 509c487e29e..9ed213d45a6 100644 --- a/bsp/stm32/stm32f429-atk-apollo/project.uvprojx +++ b/bsp/stm32/stm32f429-atk-apollo/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f429-fire-challenger/project.ewp b/bsp/stm32/stm32f429-fire-challenger/project.ewp index c26cf286269..ed52e3e4633 100644 --- a/bsp/stm32/stm32f429-fire-challenger/project.ewp +++ b/bsp/stm32/stm32f429-fire-challenger/project.ewp @@ -2154,6 +2154,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f429-fire-challenger/project.uvproj b/bsp/stm32/stm32f429-fire-challenger/project.uvproj index 6ef3655d819..ed148f20f99 100644 --- a/bsp/stm32/stm32f429-fire-challenger/project.uvproj +++ b/bsp/stm32/stm32f429-fire-challenger/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f429-fire-challenger/project.uvprojx b/bsp/stm32/stm32f429-fire-challenger/project.uvprojx index 81e92b7166c..3bf2ebac2c3 100644 --- a/bsp/stm32/stm32f429-fire-challenger/project.uvprojx +++ b/bsp/stm32/stm32f429-fire-challenger/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f429-st-disco/project.ewp b/bsp/stm32/stm32f429-st-disco/project.ewp index d6bfc4722fd..247f8a6f3d7 100644 --- a/bsp/stm32/stm32f429-st-disco/project.ewp +++ b/bsp/stm32/stm32f429-st-disco/project.ewp @@ -220,7 +220,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT STM32F429xx __RTTHREAD__ USE_HAL_DRIVER @@ -1271,7 +1270,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT STM32F429xx __RTTHREAD__ USE_HAL_DRIVER @@ -2176,6 +2174,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f429-st-disco/project.uvproj b/bsp/stm32/stm32f429-st-disco/project.uvproj index 76deaba1059..cf3a1de131d 100644 --- a/bsp/stm32/stm32f429-st-disco/project.uvproj +++ b/bsp/stm32/stm32f429-st-disco/project.uvproj @@ -572,6 +572,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f429-st-disco/project.uvprojx b/bsp/stm32/stm32f429-st-disco/project.uvprojx index 0aea667b792..b9ede5f7e8c 100644 --- a/bsp/stm32/stm32f429-st-disco/project.uvprojx +++ b/bsp/stm32/stm32f429-st-disco/project.uvprojx @@ -549,6 +549,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f446-st-nucleo/project.ewp b/bsp/stm32/stm32f446-st-nucleo/project.ewp index c291fa75f15..e71103a08b8 100644 --- a/bsp/stm32/stm32f446-st-nucleo/project.ewp +++ b/bsp/stm32/stm32f446-st-nucleo/project.ewp @@ -2160,6 +2160,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f446-st-nucleo/project.uvprojx b/bsp/stm32/stm32f446-st-nucleo/project.uvprojx index bd6c16eb861..9bff2534233 100644 --- a/bsp/stm32/stm32f446-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32f446-st-nucleo/project.uvprojx @@ -511,6 +511,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f469-st-disco/applications/arduino_pinout/SConscript b/bsp/stm32/stm32f469-st-disco/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32f469-st-disco/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32f469-st-disco/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32f469-st-disco/project.ewp b/bsp/stm32/stm32f469-st-disco/project.ewp index b4e873875af..9627555ec59 100644 --- a/bsp/stm32/stm32f469-st-disco/project.ewp +++ b/bsp/stm32/stm32f469-st-disco/project.ewp @@ -2153,6 +2153,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f469-st-disco/project.uvproj b/bsp/stm32/stm32f469-st-disco/project.uvproj index 5cb98965eeb..bcd5b786c14 100644 --- a/bsp/stm32/stm32f469-st-disco/project.uvproj +++ b/bsp/stm32/stm32f469-st-disco/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f469-st-disco/project.uvprojx b/bsp/stm32/stm32f469-st-disco/project.uvprojx index 58ef0a4c82c..ec318bd36ea 100644 --- a/bsp/stm32/stm32f469-st-disco/project.uvprojx +++ b/bsp/stm32/stm32f469-st-disco/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f723-st-disco/project.ewp b/bsp/stm32/stm32f723-st-disco/project.ewp index 174f59043d9..2b18ebd9d34 100644 --- a/bsp/stm32/stm32f723-st-disco/project.ewp +++ b/bsp/stm32/stm32f723-st-disco/project.ewp @@ -2156,6 +2156,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f723-st-disco/project.uvprojx b/bsp/stm32/stm32f723-st-disco/project.uvprojx index 5298f594c07..89be6749a3f 100644 --- a/bsp/stm32/stm32f723-st-disco/project.uvprojx +++ b/bsp/stm32/stm32f723-st-disco/project.uvprojx @@ -505,6 +505,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f746-st-disco/project.ewp b/bsp/stm32/stm32f746-st-disco/project.ewp index 1b0a508120b..434f83e2caf 100644 --- a/bsp/stm32/stm32f746-st-disco/project.ewp +++ b/bsp/stm32/stm32f746-st-disco/project.ewp @@ -2156,6 +2156,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f746-st-disco/project.uvprojx b/bsp/stm32/stm32f746-st-disco/project.uvprojx index 40a682b162d..d6534ab24e0 100644 --- a/bsp/stm32/stm32f746-st-disco/project.uvprojx +++ b/bsp/stm32/stm32f746-st-disco/project.uvprojx @@ -504,6 +504,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f746-st-nucleo/project.ewp b/bsp/stm32/stm32f746-st-nucleo/project.ewp index 0233e8ab4ff..3590991a31b 100644 --- a/bsp/stm32/stm32f746-st-nucleo/project.ewp +++ b/bsp/stm32/stm32f746-st-nucleo/project.ewp @@ -2198,6 +2198,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f746-st-nucleo/project.uvprojx b/bsp/stm32/stm32f746-st-nucleo/project.uvprojx index 021521a5719..229365c6374 100644 --- a/bsp/stm32/stm32f746-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32f746-st-nucleo/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f767-atk-apollo/project.ewp b/bsp/stm32/stm32f767-atk-apollo/project.ewp index 677016b6f12..56a9a3522a5 100644 --- a/bsp/stm32/stm32f767-atk-apollo/project.ewp +++ b/bsp/stm32/stm32f767-atk-apollo/project.ewp @@ -2196,6 +2196,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f767-atk-apollo/project.uvprojx b/bsp/stm32/stm32f767-atk-apollo/project.uvprojx index 7741b66ceb9..3b7c9e1c25f 100644 --- a/bsp/stm32/stm32f767-atk-apollo/project.uvprojx +++ b/bsp/stm32/stm32f767-atk-apollo/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/project.ewp b/bsp/stm32/stm32f767-fire-challenger-v1/project.ewp index 607c14198fb..4d38c64e631 100644 --- a/bsp/stm32/stm32f767-fire-challenger-v1/project.ewp +++ b/bsp/stm32/stm32f767-fire-challenger-v1/project.ewp @@ -2155,6 +2155,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/project.uvprojx b/bsp/stm32/stm32f767-fire-challenger-v1/project.uvprojx index 5fd46f12fe1..4cd27a66e80 100644 --- a/bsp/stm32/stm32f767-fire-challenger-v1/project.uvprojx +++ b/bsp/stm32/stm32f767-fire-challenger-v1/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f767-st-nucleo/project.ewp b/bsp/stm32/stm32f767-st-nucleo/project.ewp index 483772c760e..9ceac2cdf0b 100644 --- a/bsp/stm32/stm32f767-st-nucleo/project.ewp +++ b/bsp/stm32/stm32f767-st-nucleo/project.ewp @@ -229,7 +229,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT STM32F767xx __RTTHREAD__ USE_HAL_DRIVER @@ -1299,7 +1298,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT STM32F767xx __RTTHREAD__ USE_HAL_DRIVER @@ -2202,6 +2200,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f767-st-nucleo/project.uvprojx b/bsp/stm32/stm32f767-st-nucleo/project.uvprojx index c0ff05c8bc6..d21e4530a04 100644 --- a/bsp/stm32/stm32f767-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32f767-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32f769-st-disco/project.ewp b/bsp/stm32/stm32f769-st-disco/project.ewp index 3182da248ab..f9b227b550b 100644 --- a/bsp/stm32/stm32f769-st-disco/project.ewp +++ b/bsp/stm32/stm32f769-st-disco/project.ewp @@ -2151,6 +2151,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32f769-st-disco/project.uvprojx b/bsp/stm32/stm32f769-st-disco/project.uvprojx index e7e50e8c626..2ff8c3e8938 100644 --- a/bsp/stm32/stm32f769-st-disco/project.uvprojx +++ b/bsp/stm32/stm32f769-st-disco/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32g070-st-nucleo/project.ewp b/bsp/stm32/stm32g070-st-nucleo/project.ewp index e0f16949235..916f65b545f 100644 --- a/bsp/stm32/stm32g070-st-nucleo/project.ewp +++ b/bsp/stm32/stm32g070-st-nucleo/project.ewp @@ -2196,6 +2196,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32g070-st-nucleo/project.uvprojx b/bsp/stm32/stm32g070-st-nucleo/project.uvprojx index dcc9b27b39b..dc5b593e512 100644 --- a/bsp/stm32/stm32g070-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32g070-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32g071-st-nucleo/project.ewp b/bsp/stm32/stm32g071-st-nucleo/project.ewp index 33c0470945f..30c8872a251 100644 --- a/bsp/stm32/stm32g071-st-nucleo/project.ewp +++ b/bsp/stm32/stm32g071-st-nucleo/project.ewp @@ -2194,6 +2194,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32g071-st-nucleo/project.uvprojx b/bsp/stm32/stm32g071-st-nucleo/project.uvprojx index 9bd93377163..1f1ffec88dd 100644 --- a/bsp/stm32/stm32g071-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32g071-st-nucleo/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32g431-st-nucleo/project.ewp b/bsp/stm32/stm32g431-st-nucleo/project.ewp index b8a864071ca..4550984724f 100644 --- a/bsp/stm32/stm32g431-st-nucleo/project.ewp +++ b/bsp/stm32/stm32g431-st-nucleo/project.ewp @@ -2160,6 +2160,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32g431-st-nucleo/project.uvprojx b/bsp/stm32/stm32g431-st-nucleo/project.uvprojx index c92cb8984ea..526b5fa575d 100644 --- a/bsp/stm32/stm32g431-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32g431-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32g474-st-nucleo/applications/arduino_pinout/SConscript b/bsp/stm32/stm32g474-st-nucleo/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32g474-st-nucleo/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32g474-st-nucleo/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32g474-st-nucleo/project.ewp b/bsp/stm32/stm32g474-st-nucleo/project.ewp index fb0ec6ef247..aadc6d98de8 100644 --- a/bsp/stm32/stm32g474-st-nucleo/project.ewp +++ b/bsp/stm32/stm32g474-st-nucleo/project.ewp @@ -2160,6 +2160,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32g474-st-nucleo/project.uvprojx b/bsp/stm32/stm32g474-st-nucleo/project.uvprojx index 3396f53ff84..21a06311c33 100644 --- a/bsp/stm32/stm32g474-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32g474-st-nucleo/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32g491-st-nucleo/project.ewp b/bsp/stm32/stm32g491-st-nucleo/project.ewp index 12d05f2d95b..a89dc283ec7 100644 --- a/bsp/stm32/stm32g491-st-nucleo/project.ewp +++ b/bsp/stm32/stm32g491-st-nucleo/project.ewp @@ -2208,6 +2208,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32g491-st-nucleo/project.uvprojx b/bsp/stm32/stm32g491-st-nucleo/project.uvprojx index 270e216cf60..1e5ed1f7b12 100644 --- a/bsp/stm32/stm32g491-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32g491-st-nucleo/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32h503-st-nucleo/applications/arduino_pinout/SConscript b/bsp/stm32/stm32h503-st-nucleo/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32h503-st-nucleo/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32h503-st-nucleo/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32h503-st-nucleo/project.ewp b/bsp/stm32/stm32h503-st-nucleo/project.ewp index c7e3992fa6f..195c6c5b527 100644 --- a/bsp/stm32/stm32h503-st-nucleo/project.ewp +++ b/bsp/stm32/stm32h503-st-nucleo/project.ewp @@ -2237,6 +2237,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32h503-st-nucleo/project.uvprojx b/bsp/stm32/stm32h503-st-nucleo/project.uvprojx index 2c69ef52b28..54cda1fb16d 100644 --- a/bsp/stm32/stm32h503-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32h503-st-nucleo/project.uvprojx @@ -543,6 +543,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32h563-st-nucleo/applications/arduino_pinout/SConscript b/bsp/stm32/stm32h563-st-nucleo/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32h563-st-nucleo/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32h563-st-nucleo/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32h563-st-nucleo/project.ewp b/bsp/stm32/stm32h563-st-nucleo/project.ewp index b713d48593b..bdabe27a5e2 100644 --- a/bsp/stm32/stm32h563-st-nucleo/project.ewp +++ b/bsp/stm32/stm32h563-st-nucleo/project.ewp @@ -2237,6 +2237,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32h563-st-nucleo/project.uvprojx b/bsp/stm32/stm32h563-st-nucleo/project.uvprojx index b97965af028..acd7cec91f4 100644 --- a/bsp/stm32/stm32h563-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32h563-st-nucleo/project.uvprojx @@ -543,6 +543,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32h743-armfly-v7/project.ewp b/bsp/stm32/stm32h743-armfly-v7/project.ewp index eece1737b81..1292983bb89 100644 --- a/bsp/stm32/stm32h743-armfly-v7/project.ewp +++ b/bsp/stm32/stm32h743-armfly-v7/project.ewp @@ -2178,6 +2178,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32h743-armfly-v7/project.uvprojx b/bsp/stm32/stm32h743-armfly-v7/project.uvprojx index a086ca697a7..7b2bf3cada4 100644 --- a/bsp/stm32/stm32h743-armfly-v7/project.uvprojx +++ b/bsp/stm32/stm32h743-armfly-v7/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32h743-atk-apollo/project.ewp b/bsp/stm32/stm32h743-atk-apollo/project.ewp index 2d02d4ce298..54c8d28d324 100644 --- a/bsp/stm32/stm32h743-atk-apollo/project.ewp +++ b/bsp/stm32/stm32h743-atk-apollo/project.ewp @@ -2226,6 +2226,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32h743-atk-apollo/project.uvprojx b/bsp/stm32/stm32h743-atk-apollo/project.uvprojx index 57ae7c669ff..7e2b4c012c0 100644 --- a/bsp/stm32/stm32h743-atk-apollo/project.uvprojx +++ b/bsp/stm32/stm32h743-atk-apollo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32h743-openmv-h7plus/project.ewp b/bsp/stm32/stm32h743-openmv-h7plus/project.ewp index 2f62b9c880b..9233397a393 100644 --- a/bsp/stm32/stm32h743-openmv-h7plus/project.ewp +++ b/bsp/stm32/stm32h743-openmv-h7plus/project.ewp @@ -220,7 +220,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT STM32H743xx __RTTHREAD__ USE_HAL_DRIVER @@ -1272,7 +1271,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT STM32H743xx __RTTHREAD__ USE_HAL_DRIVER @@ -2179,6 +2177,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c @@ -2534,10 +2535,10 @@ rt_usbd - $PROJ_DIR$\..\..\..\components\drivers\usb\usbdevice\core\usbdevice_core.c + $PROJ_DIR$\..\..\..\components\drivers\usb\usbdevice\class\cdc_vcom.c - $PROJ_DIR$\..\..\..\components\drivers\usb\usbdevice\class\cdc_vcom.c + $PROJ_DIR$\..\..\..\components\drivers\usb\usbdevice\core\usbdevice_core.c $PROJ_DIR$\..\..\..\components\drivers\usb\usbdevice\core\usbdevice.c diff --git a/bsp/stm32/stm32h743-openmv-h7plus/project.uvprojx b/bsp/stm32/stm32h743-openmv-h7plus/project.uvprojx index 7577c5e1446..8c01c5fe12d 100644 --- a/bsp/stm32/stm32h743-openmv-h7plus/project.uvprojx +++ b/bsp/stm32/stm32h743-openmv-h7plus/project.uvprojx @@ -562,6 +562,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + --c99 + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1799,23 +1818,23 @@ rt_usbd - cdc_vcom.c + usbdevice_core.c 1 - ..\..\..\components\drivers\usb\usbdevice\class\cdc_vcom.c + ..\..\..\components\drivers\usb\usbdevice\core\usbdevice_core.c - usbdevice_core.c + usbdevice.c 1 - ..\..\..\components\drivers\usb\usbdevice\core\usbdevice_core.c + ..\..\..\components\drivers\usb\usbdevice\core\usbdevice.c - usbdevice.c + cdc_vcom.c 1 - ..\..\..\components\drivers\usb\usbdevice\core\usbdevice.c + ..\..\..\components\drivers\usb\usbdevice\class\cdc_vcom.c diff --git a/bsp/stm32/stm32h743-st-nucleo/project.ewp b/bsp/stm32/stm32h743-st-nucleo/project.ewp index dfcc4a73fd0..a7fdbc20d09 100644 --- a/bsp/stm32/stm32h743-st-nucleo/project.ewp +++ b/bsp/stm32/stm32h743-st-nucleo/project.ewp @@ -2194,6 +2194,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32h743-st-nucleo/project.uvprojx b/bsp/stm32/stm32h743-st-nucleo/project.uvprojx index 093751ba7f5..c604da53114 100644 --- a/bsp/stm32/stm32h743-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32h743-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32h747-st-discovery/project.ewp b/bsp/stm32/stm32h747-st-discovery/project.ewp index 8c8998b6068..3f9368c21e4 100644 --- a/bsp/stm32/stm32h747-st-discovery/project.ewp +++ b/bsp/stm32/stm32h747-st-discovery/project.ewp @@ -2196,6 +2196,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32h747-st-discovery/project.uvprojx b/bsp/stm32/stm32h747-st-discovery/project.uvprojx index f63256a211c..95b1533fa4f 100644 --- a/bsp/stm32/stm32h747-st-discovery/project.uvprojx +++ b/bsp/stm32/stm32h747-st-discovery/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/project.ewp b/bsp/stm32/stm32h750-armfly-h7-tool/project.ewp index bf67bc0012b..09b9d7be460 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/project.ewp +++ b/bsp/stm32/stm32h750-armfly-h7-tool/project.ewp @@ -2205,6 +2205,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/project.uvprojx b/bsp/stm32/stm32h750-armfly-h7-tool/project.uvprojx index b33e70a1838..d5d0c386b18 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/project.uvprojx +++ b/bsp/stm32/stm32h750-armfly-h7-tool/project.uvprojx @@ -542,6 +542,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32h750-artpi/board/port/filesystem.c b/bsp/stm32/stm32h750-artpi/board/port/filesystem.c index a88c1b1b95d..d878f9bbcd9 100644 --- a/bsp/stm32/stm32h750-artpi/board/port/filesystem.c +++ b/bsp/stm32/stm32h750-artpi/board/port/filesystem.c @@ -32,7 +32,7 @@ #define DBG_LVL DBG_INFO #include - +#ifdef RT_USING_DFS_ROMFS #include "dfs_romfs.h" #ifdef RT_USING_DFS_ELMFAT @@ -54,7 +54,7 @@ const struct romfs_dirent romfs_root = { ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root) / sizeof(_romfs_root[0]) }; - +#endif #ifdef BSP_USING_SDCARD_FS @@ -65,19 +65,19 @@ static void _sdcard_mount(void) { rt_device_t device; - device = rt_device_find("sd0"); + device = rt_device_find("sd"); if (device == NULL) { mmcsd_wait_cd_changed(0); sdcard_change(); mmcsd_wait_cd_changed(RT_WAITING_FOREVER); - device = rt_device_find("sd0"); + device = rt_device_find("sd"); } if (device != RT_NULL) { - if (dfs_mount("sd0", "/sdcard", "elm", 0, 0) == RT_EOK) + if (dfs_mount("sd", "/sdcard", "elm", 0, 0) == RT_EOK) { LOG_I("sd card mount to '/sdcard'"); } diff --git a/bsp/stm32/stm32h750-artpi/project.ewp b/bsp/stm32/stm32h750-artpi/project.ewp index 6887826bf15..186181d17d4 100644 --- a/bsp/stm32/stm32h750-artpi/project.ewp +++ b/bsp/stm32/stm32h750-artpi/project.ewp @@ -2209,6 +2209,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32h750-artpi/project.uvprojx b/bsp/stm32/stm32h750-artpi/project.uvprojx index 23f01057278..89d3bbd59db 100644 --- a/bsp/stm32/stm32h750-artpi/project.uvprojx +++ b/bsp/stm32/stm32h750-artpi/project.uvprojx @@ -544,6 +544,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32h750-fk750m1-vbt6/project.ewp b/bsp/stm32/stm32h750-fk750m1-vbt6/project.ewp index d2144f14961..aa15c9c4697 100644 --- a/bsp/stm32/stm32h750-fk750m1-vbt6/project.ewp +++ b/bsp/stm32/stm32h750-fk750m1-vbt6/project.ewp @@ -229,7 +229,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT STM32H750xx __RTTHREAD__ USE_HAL_DRIVER @@ -1303,7 +1302,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT STM32H750xx __RTTHREAD__ USE_HAL_DRIVER @@ -2219,6 +2217,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32h750-fk750m1-vbt6/project.uvprojx b/bsp/stm32/stm32h750-fk750m1-vbt6/project.uvprojx index 4851c87dd4a..97d29d35bbe 100644 --- a/bsp/stm32/stm32h750-fk750m1-vbt6/project.uvprojx +++ b/bsp/stm32/stm32h750-fk750m1-vbt6/project.uvprojx @@ -542,6 +542,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + --c99 + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32h750-weact-ministm32h7xx/project.ewp b/bsp/stm32/stm32h750-weact-ministm32h7xx/project.ewp index 553b1a12059..abce888c20e 100644 --- a/bsp/stm32/stm32h750-weact-ministm32h7xx/project.ewp +++ b/bsp/stm32/stm32h750-weact-ministm32h7xx/project.ewp @@ -229,7 +229,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT STM32H750xx __RTTHREAD__ USE_HAL_DRIVER @@ -1305,7 +1304,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT STM32H750xx __RTTHREAD__ USE_HAL_DRIVER @@ -2214,6 +2212,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c @@ -2323,7 +2324,7 @@ $PROJ_DIR$\..\..\..\components\fal\src\fal_flash.c - $PROJ_DIR$\..\..\..\components\fal\src\fal_partition.c + $PROJ_DIR$\..\..\..\components\fal\src\fal.c $PROJ_DIR$\..\..\..\components\fal\samples\porting\fal_flash_sfud_port.c @@ -2332,7 +2333,7 @@ $PROJ_DIR$\..\..\..\components\fal\src\fal_rtt.c - $PROJ_DIR$\..\..\..\components\fal\src\fal.c + $PROJ_DIR$\..\..\..\components\fal\src\fal_partition.c diff --git a/bsp/stm32/stm32h750-weact-ministm32h7xx/project.uvprojx b/bsp/stm32/stm32h750-weact-ministm32h7xx/project.uvprojx index 18f50ead9ae..48f250f92e2 100644 --- a/bsp/stm32/stm32h750-weact-ministm32h7xx/project.uvprojx +++ b/bsp/stm32/stm32h750-weact-ministm32h7xx/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + --c99 + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -917,37 +936,37 @@ Fal - fal_rtt.c + fal.c 1 - ..\..\..\components\fal\src\fal_rtt.c + ..\..\..\components\fal\src\fal.c - fal_partition.c + fal_rtt.c 1 - ..\..\..\components\fal\src\fal_partition.c + ..\..\..\components\fal\src\fal_rtt.c - fal_flash_sfud_port.c + fal_flash.c 1 - ..\..\..\components\fal\samples\porting\fal_flash_sfud_port.c + ..\..\..\components\fal\src\fal_flash.c - fal.c + fal_partition.c 1 - ..\..\..\components\fal\src\fal.c + ..\..\..\components\fal\src\fal_partition.c - fal_flash.c + fal_flash_sfud_port.c 1 - ..\..\..\components\fal\src\fal_flash.c + ..\..\..\components\fal\samples\porting\fal_flash_sfud_port.c diff --git a/bsp/stm32/stm32h7s7-st-disco/.config b/bsp/stm32/stm32h7s7-st-disco/.config new file mode 100644 index 00000000000..049b1640b2d --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/.config @@ -0,0 +1,1100 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart4" +CONFIG_RT_VER_NUM=0x50100 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_HW_ATOMIC is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M7=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI_BITOPS is not set +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +CONFIG_RT_USING_TOUCH=y +# CONFIG_RT_TOUCH_PIN_IRQ is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_GET_IRQ_PRIORITY is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# +CONFIG_SOC_FAMILY_STM32=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32H7RS=y +CONFIG_SOC_SERIES_STM32H7RS=y + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_USB_TO_USART=y +# CONFIG_BSP_USING_FS is not set + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART3 is not set +CONFIG_BSP_USING_UART4=y +# CONFIG_BSP_UART4_RX_USING_DMA is not set +# CONFIG_BSP_UART4_TX_USING_DMA is not set +CONFIG_BSP_UART4_RX_BUFSIZE=256 +CONFIG_BSP_UART4_TX_BUFSIZE=0 +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_USBD is not set +# CONFIG_BSP_USING_USBH is not set +# CONFIG_BSP_USING_LTDC is not set +# CONFIG_BSP_USING_UDID is not set diff --git a/bsp/stm32/stm32h7s7-st-disco/.gitignore b/bsp/stm32/stm32h7s7-st-disco/.gitignore new file mode 100644 index 00000000000..7221bde019d --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/stm32/stm32h7s7-st-disco/EventRecorderStub.scvd b/bsp/stm32/stm32h7s7-st-disco/EventRecorderStub.scvd new file mode 100644 index 00000000000..2956b296838 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/bsp/stm32/stm32h7s7-st-disco/Kconfig b/bsp/stm32/stm32h7s7-st-disco/Kconfig new file mode 100644 index 00000000000..362bdfbed87 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/Kconfig @@ -0,0 +1,24 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" + +if !RT_USING_NANO +source "board/Kconfig" +endif diff --git a/bsp/stm32/stm32h7s7-st-disco/README.md b/bsp/stm32/stm32h7s7-st-disco/README.md new file mode 100644 index 00000000000..1e92fe65321 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/README.md @@ -0,0 +1,133 @@ +**中文** | [English](README_en.md) + +# STM32H750-artpi 开发板 BSP 说明 + +## 简介 + +本文档 为 STM32H7S78-DK 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +STM32H7S78-DK 是 ST 官方推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 600Mhz，该开发板具有丰富的板载资源，可以充分评估 STM32H7S7 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/board.jpg) + +该开发板常用 **板载资源** 如下： + +- MCU：STM32H7S7，主频 550MHz，64KB FLASH, 456KB RAM +- 常用接口：USB 转串口、USB OTG +- 调试接口，标准 ST-LINK V3 + +开发板更多详细信息请参考 [STM32H7S78-DK](https://www.st.com/en/evaluation-tools/stm32h7s78-dk.html)。 + + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------- | :----------: | :------- | +| LED | 支持 | 一个绿灯 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | | +| UART | 支持 | UART4 | +| SPI | 待支持 | SPI | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板的ST-Link端口到 PC，并确保板子上的供电跳线配置妥当。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST_LINK 仿真器下载程序，在通过 ST_LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，LED闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash +[I/board] System Clock information +[I/board] SYSCLK_Frequency = 550000000 +[I/board] HCLK_Frequency = 275000000 +[I/board] PCLK1_Frequency = 137500000 +[I/board] PCLK2_Frequency = 137500000 +[I/board] XSPI1_Frequency = 200000000 +[I/board] XSPI2_Frequency = 200000000 + + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Apr 10 2024 14:32:06 + 2006 - 2024 Copyright by RT-Thread team +msh > + +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口4 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +- 调试串口为串口4 映射说明 + + PD0 ------> USART4_RX + + PD1 ------> USART4_TX + +- Bootloader 损坏 或 缺失 + + 如遇到程序下载后，板子跑不起来的情况，请先检查bootloader是否未烧录过，或是因为擦除片内flash导致了丢失。若 bootloader 缺失，则需要重新烧写目录下 h7s7_disco_bootloader.bin 文件到芯片内部flash；在连接开发板至 PC 后，使用STM32CubeProgrammer工具（ST官方下载工具），将 h7s7_disco_bootloader.bin 导入到该工具的下载界面下，并执行下载 ，断开连接并手动复位MCU后，此时应该就可以执行片外跳转了。 + + 此 bin 文件由STM32H7RS SDK 内示例工程构建生成，如果外部的Flash型号有修改，则可以参考ST的该示例进行修改。 + + +## 联系人信息 + +RT-Thread [社区论坛](https://club.rt-thread.org/)。 + +- ART-Pi 官方交流 QQ 群(1016035998)。 + +## 贡献代码 + +此工程尚在初始阶段，BSP尚未完善，如果您对该项目感兴趣，并有一些好玩的项目愿意与大家分享，欢迎给我们贡献代码。 \ No newline at end of file diff --git a/bsp/stm32/stm32h7s7-st-disco/README_en.md b/bsp/stm32/stm32h7s7-st-disco/README_en.md new file mode 100644 index 00000000000..139b671fffc --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/README_en.md @@ -0,0 +1,123 @@ + +**English** | [中文](README.md) + +# STM32H750-artpi Development Board BSP Guide + +## Introduction + +Welcome to the realm of innovation with the STM32H7S78-DK development board. This document serves as your guide to unleash the full potential of the Board Support Package (BSP) tailored for this cutting-edge hardware. + +What's Inside? Let's embark on an exciting journey through this guide, which covers: + +- Introduction to the wealth of resources onboard. +- Quick Start for rapid deployment. +- Advanced Usage for harnessing the board's full capabilities. + +By reading the Quick Start section, developers can quickly get started with this BSP and run RT-Thread on the development board. In the Advanced Usage Guide section, more advanced features will be introduced to help developers utilize RT-Thread to drive more onboard resources. + +## Development Board Introduction + +Development Board Introduction The STM32H7S78-DK is a development board based on the ARM Cortex-M7 core, with a maximum main frequency of 600MHz. This development board has abundant onboard resources, allowing for a comprehensive evaluation of the performance of the STM32H7S7 chip. + +Take a look at the development board's sleek design: + +![board](figures/board.jpg) + +Explore its features: + +- MCU: STM32H7S7, running at 550MHz with 64KB FLASH and 456KB RAM. +- Interfaces: From USB to serial and USB OTG. +- Debugging: Seamlessly debug with the standard ST-LINK V3. + +## Peripheral Playground + +The current support status of peripherals in this BSP is as follows: + +| **Onboard peripherals** | Support | Remark | +| ----------------------- | ----------- | ------------ | +| LED | YES | One green LE | +| **On-chip peripherals** | **Support** | **Remark** | +| GPIO | YES | | +| UART | YES | UART4 | +| SPI | YES | SPI | + +## Instructions for Use + +Instructions for use are divided into the following two sections: + +**Quick Start** + +This section provides instructions for newcomers to RT-Thread, following simple steps to run the RT-Thread operating system on this development board and observe experimental results. + +**Advanced Usage** + +This section is for developers who need to use more development board resources on the RT-Thread operating system. By configuring the BSP using the ENV tool, more onboard resources can be enabled to implement more advanced features. + +### Quick Start + +This BSP provides an MDK5 project for developers and supports the GCC development environment. Below is an example using the MDK5 development environment to start the system. + +#### Hardware Connection + +Connect the ST-Link port of the development board to the PC using a data cable and ensure that the power supply jumpers on the board are properly configured. + +#### Compilation and Download + +Double-click the project.uvprojx file to open the MDK5 project, compile it, and download the program to the development board. + +> The project default configuration uses the ST-LINK emulator to download the program. After connecting the development board via ST-LINK, click the download button to download the program to the development board. + +#### Running Result + +After successful program download, the system will run automatically, and the LED will blink. + +Connect the corresponding serial port of the development board to the PC, open the terminal tool, and reset the device. You will see RT-Thread output information: + +``` +[I/board] System Clock information +[I/board] SYSCLK_Frequency = 550000000 +[I/board] HCLK_Frequency = 275000000 +[I/board] PCLK1_Frequency = 137500000 +[I/board] PCLK2_Frequency = 137500000 +[I/board] XSPI1_Frequency = 200000000 +[I/board] XSPI2_Frequency = 200000000 + + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Apr 10 2024 14:32:06 + 2006 - 2024 Copyright by RT-Thread team +msh > +``` + + + +### Advanced Usage + +By default, this BSP only enables the functions of GPIO and UART4. If more advanced features are required, ENV tools need to be used to configure BSP, as follows: + +1. Open the env tool under bsp. +2. Enter the `menuconfig` command to configure the project, save and exit after configuration. +3. Enter the `pkgs --update` command to update the software package. +4. Enter the `scons --target=mdk4/mdk5/iar` command to regenerate the project. + +## Pro Tips + +- Mapping of debug serial port to USART4: + + PD0 ------> USART4_RX + + PD1 ------> USART4_TX + +- Bootloader Damage or Loss + + In case the board does not boot after program download, please first check if the bootloader is not burned or is lost due to erasure of internal flash. If the bootloader is missing, it needs to be rewritten by downloading the h7s7_disco_bootloader.bin file under the directory to the chip's internal flash using the STM32CubeProgrammer tool (ST official download tool) after connecting the development board to the PC. Then disconnect and manually reset the MCU, and the external jump should be executed at this time. + + This bin file is generated from the STM32H7RS SDK internal example project. If the external Flash model is modified, you can refer to ST's example for modification. + +## Contact Info + +RT-Thread Club: https://club.rt-thread.io/ + +## Code Contribution + + This project is still in its initial stage, and the BSP is not yet perfect. If you are interested in this project and have some interesting projects to share with us, you are welcome to contribute code. \ No newline at end of file diff --git a/bsp/stm32/stm32h7s7-st-disco/SConscript b/bsp/stm32/stm32h7s7-st-disco/SConscript new file mode 100644 index 00000000000..c7ef7659ece --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32h7s7-st-disco/SConstruct b/bsp/stm32/stm32h7s7-st-disco/SConstruct new file mode 100644 index 00000000000..53e0186e1dd --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +stm32_library = 'STM32H7RSxx_HAL' +rtconfig.BSP_LIBRARY_TYPE = stm32_library + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'))) + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32h7s7-st-disco/applications/SConscript b/bsp/stm32/stm32h7s7-st-disco/applications/SConscript new file mode 100644 index 00000000000..034056eca76 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/applications/SConscript @@ -0,0 +1,16 @@ +import rtconfig +from building import * +import os + +cwd = GetCurrentDir() +path = [cwd] +src = Glob('*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = path) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/SConscript b/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/SConscript new file mode 100644 index 00000000000..79d9772177a --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/SConscript @@ -0,0 +1,16 @@ +from building import * +import os + +cwd = GetCurrentDir() +group = [] +src = Glob('*.c') +CPPPATH = [cwd] + +list = os.listdir(cwd) +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + group = group + SConscript(os.path.join(d, 'SConscript')) + +group = group + DefineGroup('LVGL-port', src, depend = ['BSP_USING_LVGL'], CPPPATH = CPPPATH) +Return('group') diff --git a/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_conf.h b/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_conf.h new file mode 100644 index 00000000000..cdbe8b6812c --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_conf.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-01-28 Rudy Lo The first version + */ + +#ifndef LV_CONF_H +#define LV_CONF_H + +#include + +#define LCD_W 480 +#define LCD_H 320 + +#define LV_COLOR_DEPTH 32 +#define LV_USE_PERF_MONITOR 1 +#define LV_HOR_RES_MAX LCD_W +#define LV_VER_RES_MAX LCD_H + +#ifdef PKG_USING_LV_MUSIC_DEMO +/* music player demo */ +#define LV_USE_DEMO_RTT_MUSIC 1 +#define LV_DEMO_RTT_MUSIC_AUTO_PLAY 1 +#define LV_FONT_MONTSERRAT_12 1 +#define LV_FONT_MONTSERRAT_16 1 +#define LV_COLOR_SCREEN_TRANSP 1 +#endif /* PKG_USING_LV_MUSIC_DEMO */ + +#endif diff --git a/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_demo.c b/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_demo.c new file mode 100644 index 00000000000..4facba04701 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_demo.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-01-28 Rudy Lo The first version + */ +#include +#include +#include +#define DBG_TAG "LVGL.demo" +#define DBG_LVL DBG_INFO +#include + +#ifndef LV_THREAD_STACK_SIZE +#define LV_THREAD_STACK_SIZE 4096 +#endif + +#ifndef LV_THREAD_PRIO +#define LV_THREAD_PRIO (RT_THREAD_PRIORITY_MAX * 2 / 3) +#endif + +static void lvgl_thread(void *parameter) +{ + extern void lv_demo_music(void); + lv_demo_music(); + + /* handle the tasks of LVGL */ + while(1) + { + lv_task_handler(); + rt_thread_mdelay(10); + } +} + +static int lvgl_demo_init(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("LVGL", lvgl_thread, RT_NULL, LV_THREAD_STACK_SIZE, LV_THREAD_PRIO, 0); + if(tid == RT_NULL) + { + LOG_E("Fail to create 'LVGL' thread"); + } + rt_thread_startup(tid); + + return 0; +} +INIT_APP_EXPORT(lvgl_demo_init); diff --git a/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_port_disp.c b/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_port_disp.c new file mode 100644 index 00000000000..689d934b4b6 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_port_disp.c @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-02-01 Rudy Lo The first version + */ + +#include +#include +#include "drv_spi_ili9488.h" + +#define MY_DISP_HOR_RES (LCD_W) +#define DISP_BUFFER_LINES (LCD_H / 5) + +/*A static or global variable to store the buffers*/ +static lv_disp_draw_buf_t disp_buf; + +/*Descriptor of a display driver*/ +static lv_disp_drv_t disp_drv; + +/*Static or global buffer(s). The second buffer is optional*/ +static lv_color_t buf_1[MY_DISP_HOR_RES * DISP_BUFFER_LINES]; +//static lv_color_t buf_2[MY_DISP_HOR_RES * DISP_BUFFER_LINES]; + +/*Flush the content of the internal buffer the specific area on the display + *You can use DMA or any hardware acceleration to do this operation in the background but + *'lv_disp_flush_ready()' has to be called when finished.*/ +static void disp_flush(lv_disp_drv_t * disp_drv, const lv_area_t * area, lv_color_t * color_p) +{ + /* color_p is a buffer pointer; the buffer is provided by LVGL */ + lcd_fill_array(area->x1, area->y1, area->x2, area->y2, color_p); + + /*IMPORTANT!!! + *Inform the graphics library that you are ready with the flushing*/ + lv_disp_flush_ready(disp_drv); +} + +void lv_port_disp_init(void) +{ + /*Initialize `disp_buf` with the buffer(s). With only one buffer use NULL instead buf_2 */ + lv_disp_draw_buf_init(&disp_buf, buf_1, RT_NULL, MY_DISP_HOR_RES * DISP_BUFFER_LINES); + + lv_disp_drv_init(&disp_drv); /*Basic initialization*/ + + /*Set the resolution of the display*/ + disp_drv.hor_res = LCD_W; + disp_drv.ver_res = LCD_H; + + /*Set a display buffer*/ + disp_drv.draw_buf = &disp_buf; + + /*Used to copy the buffer's content to the display*/ + disp_drv.flush_cb = disp_flush; + + /*Finally register the driver*/ + lv_disp_drv_register(&disp_drv); +} diff --git a/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_port_disp.h b/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_port_disp.h new file mode 100644 index 00000000000..5c93b6c9d49 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_port_disp.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-02-01 Rudy Lo The first version + */ + +#ifndef LV_PORT_DISP_H +#define LV_PORT_DISP_H + +#ifdef __cplusplus +extern "C" { +#endif + +void lv_port_disp_init(void); + +#ifdef __cplusplus +} /*extern "C"*/ +#endif + +#endif diff --git a/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_port_indev.c b/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_port_indev.c new file mode 100644 index 00000000000..26d0bc29881 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_port_indev.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-02-01 Rudy Lo The first version + */ + +#include +#include +#include +#include + +#include "ft6236.h" + +#define TOUCH_DEVICE_NAME "touch_ft" /* Touch device name */ +#define TOUCH_DEVICE_I2C_BUS "i2c2" /* SCL -> PH15(127), SDA -> PH13(125) */ +#define REST_PIN GET_PIN(A, 3) /* reset pin */ +#define USER_BUTTON_PIN GET_PIN(H, 4) /* Reserve for LV_INDEV_TYPE_BUTTON */ + +static rt_device_t ts; /* Touch device handle, Touchscreen */ +static struct rt_touch_data *read_data; + +static rt_int16_t last_x = 0; +static rt_int16_t last_y = 0; + +static bool touchpad_is_pressed(void) +{ + if (RT_EOK == rt_device_read(ts, 0, read_data, 1)) /* return RT_EOK is a bug (ft6236) */ + { + if (read_data->event == RT_TOUCH_EVENT_DOWN) { + /* swap x and y */ + rt_int16_t tmp_x = read_data->y_coordinate; + rt_int16_t tmp_y = read_data->x_coordinate; + + /* invert y */ + tmp_y = 320 - tmp_y; + + /* restore data */ + last_x = tmp_x; + last_y = tmp_y; + + rt_kprintf("touch: x = %d, y = %d\n", last_x, last_y); + return true; + } + } + + return false; +} + +static void touchpad_get_xy(rt_int16_t *x, rt_int16_t *y) +{ + *x = last_x; + *y = last_y; +} + +static void touchpad_read(lv_indev_drv_t *indev, lv_indev_data_t *data) +{ + /*`touchpad_is_pressed` and `touchpad_get_xy` needs to be implemented by you*/ + if(touchpad_is_pressed()) { + data->state = LV_INDEV_STATE_PRESSED; + touchpad_get_xy(&data->point.x, &data->point.y); + } else { + data->state = LV_INDEV_STATE_RELEASED; + } +} + +rt_err_t rt_hw_ft6236_register(void) +{ + struct rt_touch_config config; + config.dev_name = TOUCH_DEVICE_I2C_BUS; + rt_hw_ft6236_init(TOUCH_DEVICE_NAME, &config, REST_PIN); + + ts = rt_device_find(TOUCH_DEVICE_NAME); + if (!ts) { + return -RT_ERROR; + } + + read_data = (struct rt_touch_data *)rt_calloc(1, sizeof(struct rt_touch_data)); + if (!read_data) { + return -RT_ENOMEM; + } + + if (!rt_device_open(ts, RT_DEVICE_FLAG_RDONLY)) { + struct rt_touch_info info; + rt_device_control(ts, RT_TOUCH_CTRL_GET_INFO, &info); + rt_kprintf("type :%d\n", info.type); + rt_kprintf("vendor :%s\n", info.vendor); + rt_kprintf("point_num :%d\n", info.point_num); + rt_kprintf("range_x :%d\n", info.range_x); + rt_kprintf("range_y :%d\n", info.range_y); + return RT_EOK; + } else { + rt_kprintf("open touch device failed.\n"); + return -RT_ERROR; + } +} + +lv_indev_t * touch_indev; + +void lv_port_indev_init(void) +{ + static lv_indev_drv_t indev_drv; /* Descriptor of a input device driver */ + lv_indev_drv_init(&indev_drv); /* Basic initialization */ + indev_drv.type = LV_INDEV_TYPE_POINTER; /* Touch pad is a pointer-like device */ + indev_drv.read_cb = touchpad_read; /* Set your driver function */ + + /* Register the driver in LVGL and save the created input device object */ + touch_indev = lv_indev_drv_register(&indev_drv); + + /* Register touch device */ + rt_hw_ft6236_register(); +} diff --git a/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_port_indev.h b/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_port_indev.h new file mode 100644 index 00000000000..c546f232b90 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/applications/lvgl/lv_port_indev.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-02-01 Rudy Lo The first version + */ + +#ifndef LV_PORT_INDEV_H +#define LV_PORT_INDEV_H + +#ifdef __cplusplus +extern "C" { +#endif + +void lv_port_indev_init(void); + +#ifdef __cplusplus +} /*extern "C"*/ +#endif + +#endif diff --git a/bsp/stm32/stm32h7s7-st-disco/applications/main.c b/bsp/stm32/stm32h7s7-st-disco/applications/main.c new file mode 100644 index 00000000000..e4a76eb43d4 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/applications/main.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-03-17 supperthomas first version + */ + +#include +#include +#include + +/* defined the LED0 pin: PO1 */ +#define LED_PIN GET_PIN(O, 1) + +int main(void) +{ + rt_uint32_t count = 1; + + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + + while(count++) + { + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + } + return RT_EOK; +} + +#include "stm32h7rsxx.h" +static int vtor_config(void) +{ + /* Vector Table Relocation in Internal XSPI2_BASE */ + SCB->VTOR = XSPI2_BASE; + return 0; +} +INIT_BOARD_EXPORT(vtor_config); diff --git a/bsp/stm32/stm32h7s7-st-disco/board/.ignore_format.yml b/bsp/stm32/stm32h7s7-st-disco/board/.ignore_format.yml new file mode 100644 index 00000000000..0d7f3e360c6 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- CubeMX_Config diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/.mxproject new file mode 100644 index 00000000000..3a17e892d99 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/.mxproject @@ -0,0 +1,72 @@ +[Boot:PreviousLibFiles] +LibFiles=Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7s7xx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\system_stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[Boot:PreviousUsedKeilFiles] +SourceFiles=D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;;; +HeaderPath=D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32H7S7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[Appli:PreviousLibFiles] +LibFiles=Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_lpuart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_bus.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_crs.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_system.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_utils.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma2d.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_def.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_gpio.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cortex.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_exti.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim.c;Drivers\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_tim_ex.c;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_usart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_lpuart.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_uart_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_dma_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_rcc_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_bus.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_rcc.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_crs.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_system.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_utils.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_flash_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_gpio_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_gpio.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_dma2d.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_pwr_ex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_pwr.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_cortex.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_def.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_ll_exti.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim.h;Drivers\STM32H7RSxx_HAL_Driver\Inc\stm32h7rsxx_hal_tim_ex.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7s7xx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Include\system_stm32h7rsxx.h;Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Dr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+ +[Appli:PreviousUsedKeilFiles] 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+HeaderPath=D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\STM32H7RSxx_HAL_Driver\Inc;D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy;D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Include;..\Appli\Core\Inc; +CDefines=USE_HAL_DRIVER;STM32H7S7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[Eloader:PreviousLibFiles] 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+ +[Eloader:PreviousUsedKeilFiles] +SourceFiles=D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c;;; +HeaderPath=D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Include; +CDefines=USE_HAL_DRIVER;STM32H7S7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousLibFiles] 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+ +[PreviousUsedKeilFiles] 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+HeaderPath=D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\STM32H7RSxx_HAL_Driver\Inc;D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\STM32H7RSxx_HAL_Driver\Inc\Legacy;D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Device\ST\STM32H7RSxx\Include;D:\Packages\STM32Cube\Repository\STM32Cube_FW_H7RS_V1.0.0RC1\Drivers\CMSIS\Include;..\Appli\Core\Inc; +CDefines=USE_HAL_DRIVER;STM32H7S7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;STM32H7S7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;STM32H7S7xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[Boot:PreviousGenFiles] +SourceFiles=; + +[Appli:PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=3 +HeaderFiles#0=..\Appli\Core\Inc\stm32h7rsxx_it.h +HeaderFiles#1=..\Appli\Core\Inc\stm32h7rsxx_hal_conf.h +HeaderFiles#2=..\Appli\Core\Inc\main.h +HeaderFolderListSize=1 +HeaderPath#0=..\Appli\Core\Inc +HeaderFiles=; +SourceFileListSize=3 +SourceFiles#0=..\Appli\Core\Src\stm32h7rsxx_it.c +SourceFiles#1=..\Appli\Core\Src\stm32h7rsxx_hal_msp.c +SourceFiles#2=..\Appli\Core\Src\main.c +SourceFolderListSize=1 +SourcePath#0=..\Appli\Core\Src +SourceFiles=; + +[Eloader:PreviousGenFiles] +SourceFiles=; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=3 +HeaderFiles#0=..\Appli\Core\Inc\stm32h7rsxx_it.h +HeaderFiles#1=..\Appli\Core\Inc\stm32h7rsxx_hal_conf.h +HeaderFiles#2=..\Appli\Core\Inc\main.h +HeaderFolderListSize=1 +HeaderPath#0=..\Appli\Core\Inc +HeaderFiles=; +SourceFileListSize=3 +SourceFiles#0=..\Appli\Core\Src\stm32h7rsxx_it.c +SourceFiles#1=..\Appli\Core\Src\stm32h7rsxx_hal_msp.c +SourceFiles#2=..\Appli\Core\Src\main.c +SourceFolderListSize=1 +SourcePath#0=..\Appli\Core\Src +SourceFiles=; + diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Inc/main.h b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Inc/main.h new file mode 100644 index 00000000000..ec23c3a606f --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_hal_conf.h b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_hal_conf.h new file mode 100644 index 00000000000..3726989e151 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_hal_conf.h @@ -0,0 +1,501 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32h7rsxx_hal_conf.h. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_CONF_H +#define STM32H7RSxx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CORDIC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DCMIPP_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_DTS_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_FDCAN_MODULE_ENABLED */ +/* #define HAL_GFXMMU_MODULE_ENABLED */ +/* #define HAL_GFXTIM_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +/* #define HAL_GPU2D_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_I3C_MODULE_ENABLED */ +/* #define HAL_ICACHE_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_MCE_MODULE_ENABLED */ +/* #define HAL_MDF_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_PKA_MODULE_ENABLED */ +/* #define HAL_PSSI_MODULE_ENABLED */ +/* #define HAL_RAMECC_MODULE_ENABLED */ +/* #define HAL_RCC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_XSPI_MODULE_ENABLED */ +#define HAL_PWR_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 25000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up (in ms) */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low-power oscillator (CSI) default value. + * This value is the default CSI range value after Reset. + */ +#if !defined (CSI_VALUE) +#define CSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* CSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB OTG FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ + #if !defined (HSI48_VALUE) + #define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB OTG FS/RNG in Hz. + The real value my vary depending on manufacturing process variations. */ + #endif /* HSI48_VALUE */ + +/** +* @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz. + Value of the Internal Low Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature.*/ +#endif /* LSI_VALUE */ + +/** +* @brief External Low Speed oscillator (LSE) value. +*/ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up (in ms) */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for digital audio interfaces: SPI/I2S, SAI and ADF + * This value is used by the RCC HAL module to provide the digital audio interfaces + * frequency. This clock source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 48000UL /*!< Value of the external clock source in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL)/*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U + +/* ########################## Assert Selection ############################## */ +/** +* @brief Uncomment the line below to expanse the "assert_param" macro in the +* HAL drivers code +*/ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** +* @brief Set below the peripheral configuration to "1U" to add the support +* of HAL callback registration/unregistration feature for the HAL +* driver(s). This allows user application to provide specific callback +* functions thanks to HAL_PPP_RegisterCallback() rather than overwriting +* the default weak callback functions (see each stm32h7rsxx_hal_ppp.h file +* for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef +* for each PPP peripheral). +*/ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_MDF_REGISTER_CALLBACKS 0U +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U +#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 1U + +/* ################## CRYP peripheral configuration ########################## */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 0U + +/* ################## HASH peripheral configuration ########################## */ + +#define USE_HAL_HASH_SUSPEND_RESUME 0U + +/* ################## SDMMC peripheral configuration ######################### */ + +#define USE_SD_TRANSCEIVER 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32h7rsxx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32h7rsxx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32h7rsxx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32h7rsxx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32h7rsxx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32h7rsxx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED + #include "stm32h7rsxx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32h7rsxx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32h7rsxx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DCMIPP_MODULE_ENABLED + #include "stm32h7rsxx_hal_dcmipp.h" +#endif /* HAL_DCMIPP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32h7rsxx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED + #include "stm32h7rsxx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32h7rsxx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32h7rsxx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + #include "stm32h7rsxx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32h7rsxx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32h7rsxx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_GFXTIM_MODULE_ENABLED + #include "stm32h7rsxx_hal_gfxtim.h" +#endif /* HAL_GFXTIM_MODULE_ENABLED */ + +#ifdef HAL_GPU2D_MODULE_ENABLED + #include "stm32h7rsxx_hal_gpu2d.h" +#endif /* HAL_GPU2D_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32h7rsxx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32h7rsxx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32h7rsxx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32h7rsxx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_I3C_MODULE_ENABLED + #include "stm32h7rsxx_hal_i3c.h" +#endif /* HAL_I3C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED + #include "stm32h7rsxx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32h7rsxx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32h7rsxx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32h7rsxx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32h7rsxx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32h7rsxx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MCE_MODULE_ENABLED + #include "stm32h7rsxx_hal_mce.h" +#endif /* HAL_MCE_MODULE_ENABLED */ + +#ifdef HAL_MDF_MODULE_ENABLED + #include "stm32h7rsxx_hal_mdf.h" +#endif /* HAL_MDF_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32h7rsxx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32h7rsxx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32h7rsxx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32h7rsxx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED + #include "stm32h7rsxx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32h7rsxx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32h7rsxx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMECC_MODULE_ENABLED + #include "stm32h7rsxx_hal_ramecc.h" +#endif /* HAL_RAMECC_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32h7rsxx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32h7rsxx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32h7rsxx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32h7rsxx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32h7rsxx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32h7rsxx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32h7rsxx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32h7rsxx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32h7rsxx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32h7rsxx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32h7rsxx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32h7rsxx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32h7rsxx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32h7rsxx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED + #include "stm32h7rsxx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_CONF_H */ + diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_it.h b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_it.h new file mode 100644 index 00000000000..9020c13896c --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Inc/stm32h7rsxx_it.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7rsxx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7RSxx_IT_H +#define __STM32H7RSxx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7RSxx_IT_H */ diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Src/main.c b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Src/main.c new file mode 100644 index 00000000000..357c892a45d --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Src/main.c @@ -0,0 +1,165 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +UART_HandleTypeDef huart4; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +static void MX_GPIO_Init(void); +static void MX_UART4_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ + +/** + * @brief UART4 Initialization Function + * @param None + * @retval None + */ +static void MX_UART4_Init(void) +{ + + /* USER CODE BEGIN UART4_Init 0 */ + + /* USER CODE END UART4_Init 0 */ + + /* USER CODE BEGIN UART4_Init 1 */ + + /* USER CODE END UART4_Init 1 */ + huart4.Instance = UART4; + huart4.Init.BaudRate = 115200; + huart4.Init.WordLength = UART_WORDLENGTH_8B; + huart4.Init.StopBits = UART_STOPBITS_1; + huart4.Init.Parity = UART_PARITY_NONE; + huart4.Init.Mode = UART_MODE_TX_RX; + huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart4.Init.OverSampling = UART_OVERSAMPLING_16; + huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart4.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart4) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart4, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart4, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart4) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN UART4_Init 2 */ + + /* USER CODE END UART4_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ +/* USER CODE BEGIN MX_GPIO_Init_1 */ +/* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOD_CLK_ENABLE(); + +/* USER CODE BEGIN MX_GPIO_Init_2 */ +/* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_hal_msp.c b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_hal_msp.c new file mode 100644 index 00000000000..e8744c3c843 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_hal_msp.c @@ -0,0 +1,144 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==UART4) + { + /* USER CODE BEGIN UART4_MspInit 0 */ + + /* USER CODE END UART4_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_UART4_CLK_ENABLE(); + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**UART4 GPIO Configuration + PD1 ------> UART4_TX + PD0 ------> UART4_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF8_UART4; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN UART4_MspInit 1 */ + + /* USER CODE END UART4_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==UART4) + { + /* USER CODE BEGIN UART4_MspDeInit 0 */ + + /* USER CODE END UART4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_UART4_CLK_DISABLE(); + + /**UART4 GPIO Configuration + PD1 ------> UART4_TX + PD0 ------> UART4_RX + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_1|GPIO_PIN_0); + + /* USER CODE BEGIN UART4_MspDeInit 1 */ + + /* USER CODE END UART4_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_it.c b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_it.c new file mode 100644 index 00000000000..4c3a52adbc0 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Src/stm32h7rsxx_it.c @@ -0,0 +1,203 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7rsxx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32h7rsxx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32H7RSxx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32h7rsxx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Src/system_stm32h7rsxx.c b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Src/system_stm32h7rsxx.c new file mode 100644 index 00000000000..bd0ba8a5aaa --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Appli/Core/Src/system_stm32h7rsxx.c @@ -0,0 +1,304 @@ +/** + ****************************************************************************** + * @file system_stm32h7rsxx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h7rsxx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (sys_cpu_ck), it can + * be used by the user application to setup the + * SysTick timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (64 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32h7rsxx.s" file, to + * optionally configure the system clock before to branch to main program. + * + *============================================================================= + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32H7RSxx_System + * @{ + */ + +/** @addtogroup STM32H7RSxx_System_Private_Includes + * @{ + */ + +#include "stm32h7rsxx.h" +#include + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 24000000UL /*!< Value of the High-Speed External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 64000000UL /*!< Value of the High-Speed Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE 4000000UL /*!< Value of the Low-power Internal oscillator in Hz */ +#endif /* CSI_VALUE */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line or define USER_VECT_TAB_ADDRESS at compiler level if you need + to relocate the vector table anywhere in Flash or Sram, else the vector table is kept at + the automatic remap of the selected boot address */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line or define VECT_TAB_SRAM at compiler level if you need + to relocate your vector Table in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ + +#if defined(VECT_TAB_SRAM) +#if !defined(VECT_TAB_BASE_ADDRESS) +#define VECT_TAB_BASE_ADDRESS ITCM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#endif +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#endif +#else +#if !defined(VECT_TAB_BASE_ADDRESS) +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#endif +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#endif +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in two ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the first function listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = HSI_VALUE; + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @retval None + */ + +void SystemInit(void) +{ + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; +#endif + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to RCC registers values. + * The SystemCoreClock variable contains the core clock (sys_cpu_ck), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSI_VALUE(*) + * or CSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) CSI_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value + * 24 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t sysclk, hsivalue, pllsource, pllm, pllp, core_presc; + float_t pllfracn, pllvco; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x00: /* HSI used as system clock source (default after reset) */ + sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos)); + break; + + case 0x08: /* CSI used as system clock source */ + sysclk = CSI_VALUE; + break; + + case 0x10: /* HSE used as system clock source */ + sysclk = HSE_VALUE; + break; + + case 0x18: /* PLL1 used as system clock source */ + /* PLL1_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL1_VCO / PLL1R + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) ; + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) != 0U) + { + pllfracn = (float_t)(uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN)>> RCC_PLL1FRACR_FRACN_Pos)); + } + else + { + pllfracn = (float_t)0U; + } + + if (pllm != 0U) + { + switch (pllsource) + { + case 0x02: /* HSE used as PLL1 clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 ); + break; + + case 0x01: /* CSI used as PLL1 clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 ); + break; + + case 0x00: /* HSI used as PLL1 clock source */ + default: + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos)); + pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 ); + break; + } + pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U ) ; + sysclk = (uint32_t)(float_t)(pllvco/(float_t)pllp); + } + else + { + sysclk = 0U; + } + break; + + default: /* Unexpected, default to HSI used as system clock source (default after reset) */ + sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos)); + break; + } + + /* system clock frequency : CM7 CPU frequency */ + core_presc = (RCC->CDCFGR & RCC_CDCFGR_CPRE); + if (core_presc >= 8U) + { + SystemCoreClock = (sysclk >> (core_presc - RCC_CDCFGR_CPRE_3 + 1U)); + } + else + { + SystemCoreClock = sysclk; + } +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Inc/main.h b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Inc/main.h new file mode 100644 index 00000000000..ec23c3a606f --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Inc/stm32h7rsxx_hal_conf.h b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Inc/stm32h7rsxx_hal_conf.h new file mode 100644 index 00000000000..4d408a92e39 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Inc/stm32h7rsxx_hal_conf.h @@ -0,0 +1,501 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32h7rsxx_hal_conf.h. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_CONF_H +#define STM32H7RSxx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CORDIC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DCMIPP_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_DTS_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_FDCAN_MODULE_ENABLED */ +/* #define HAL_GFXMMU_MODULE_ENABLED */ +/* #define HAL_GFXTIM_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +/* #define HAL_GPU2D_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_I3C_MODULE_ENABLED */ +/* #define HAL_ICACHE_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_MCE_MODULE_ENABLED */ +/* #define HAL_MDF_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_PKA_MODULE_ENABLED */ +/* #define HAL_PSSI_MODULE_ENABLED */ +/* #define HAL_RAMECC_MODULE_ENABLED */ +/* #define HAL_RCC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_XSPI_MODULE_ENABLED */ +#define HAL_PWR_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 25000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up (in ms) */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low-power oscillator (CSI) default value. + * This value is the default CSI range value after Reset. + */ +#if !defined (CSI_VALUE) +#define CSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* CSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB OTG FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ + #if !defined (HSI48_VALUE) + #define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB OTG FS/RNG in Hz. + The real value my vary depending on manufacturing process variations. */ + #endif /* HSI48_VALUE */ + +/** +* @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz. + Value of the Internal Low Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature.*/ +#endif /* LSI_VALUE */ + +/** +* @brief External Low Speed oscillator (LSE) value. +*/ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up (in ms) */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for digital audio interfaces: SPI/I2S, SAI and ADF + * This value is used by the RCC HAL module to provide the digital audio interfaces + * frequency. This clock source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 48000UL /*!< Value of the external clock source in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL)/*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U + +/* ########################## Assert Selection ############################## */ +/** +* @brief Uncomment the line below to expanse the "assert_param" macro in the +* HAL drivers code +*/ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** +* @brief Set below the peripheral configuration to "1U" to add the support +* of HAL callback registration/unregistration feature for the HAL +* driver(s). This allows user application to provide specific callback +* functions thanks to HAL_PPP_RegisterCallback() rather than overwriting +* the default weak callback functions (see each stm32h7rsxx_hal_ppp.h file +* for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef +* for each PPP peripheral). +*/ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_MDF_REGISTER_CALLBACKS 0U +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U +#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 1U + +/* ################## CRYP peripheral configuration ########################## */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 0U + +/* ################## HASH peripheral configuration ########################## */ + +#define USE_HAL_HASH_SUSPEND_RESUME 0U + +/* ################## SDMMC peripheral configuration ######################### */ + +#define USE_SD_TRANSCEIVER 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32h7rsxx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32h7rsxx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32h7rsxx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32h7rsxx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32h7rsxx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32h7rsxx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED + #include "stm32h7rsxx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32h7rsxx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32h7rsxx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DCMIPP_MODULE_ENABLED + #include "stm32h7rsxx_hal_dcmipp.h" +#endif /* HAL_DCMIPP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32h7rsxx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED + #include "stm32h7rsxx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32h7rsxx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32h7rsxx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + #include "stm32h7rsxx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32h7rsxx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32h7rsxx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_GFXTIM_MODULE_ENABLED + #include "stm32h7rsxx_hal_gfxtim.h" +#endif /* HAL_GFXTIM_MODULE_ENABLED */ + +#ifdef HAL_GPU2D_MODULE_ENABLED + #include "stm32h7rsxx_hal_gpu2d.h" +#endif /* HAL_GPU2D_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32h7rsxx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32h7rsxx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32h7rsxx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32h7rsxx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_I3C_MODULE_ENABLED + #include "stm32h7rsxx_hal_i3c.h" +#endif /* HAL_I3C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED + #include "stm32h7rsxx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32h7rsxx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32h7rsxx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32h7rsxx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32h7rsxx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32h7rsxx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MCE_MODULE_ENABLED + #include "stm32h7rsxx_hal_mce.h" +#endif /* HAL_MCE_MODULE_ENABLED */ + +#ifdef HAL_MDF_MODULE_ENABLED + #include "stm32h7rsxx_hal_mdf.h" +#endif /* HAL_MDF_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32h7rsxx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32h7rsxx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32h7rsxx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32h7rsxx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED + #include "stm32h7rsxx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32h7rsxx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32h7rsxx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMECC_MODULE_ENABLED + #include "stm32h7rsxx_hal_ramecc.h" +#endif /* HAL_RAMECC_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32h7rsxx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32h7rsxx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32h7rsxx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32h7rsxx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32h7rsxx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32h7rsxx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32h7rsxx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32h7rsxx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32h7rsxx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32h7rsxx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32h7rsxx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32h7rsxx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32h7rsxx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32h7rsxx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED + #include "stm32h7rsxx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_CONF_H */ + diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Inc/stm32h7rsxx_it.h b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Inc/stm32h7rsxx_it.h new file mode 100644 index 00000000000..9020c13896c --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Inc/stm32h7rsxx_it.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7rsxx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7RSxx_IT_H +#define __STM32H7RSxx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7RSxx_IT_H */ diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Src/main.c b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Src/main.c new file mode 100644 index 00000000000..14f9b84f05f --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Src/main.c @@ -0,0 +1,229 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_FLASH_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL1.PLLM = 2; + RCC_OscInitStruct.PLL1.PLLN = 32; + RCC_OscInitStruct.PLL1.PLLP = 1; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLR = 2; + RCC_OscInitStruct.PLL1.PLLS = 2; + RCC_OscInitStruct.PLL1.PLLT = 2; + RCC_OscInitStruct.PLL1.PLLFractional = 0; + RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_PCLK4|RCC_CLOCKTYPE_PCLK5; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + RCC_ClkInitStruct.APB5CLKDivider = RCC_APB5_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief FLASH Initialization Function + * @param None + * @retval None + */ +static void MX_FLASH_Init(void) +{ + + /* USER CODE BEGIN FLASH_Init 0 */ + + /* USER CODE END FLASH_Init 0 */ + + FLASH_OBProgramInitTypeDef pOBInit = {0}; + + /* USER CODE BEGIN FLASH_Init 1 */ + + /* USER CODE END FLASH_Init 1 */ + if (HAL_FLASH_Unlock() != HAL_OK) + { + Error_Handler(); + } + if (HAL_FLASH_OB_Unlock() != HAL_OK) + { + Error_Handler(); + } + pOBInit.OptionType = OPTIONBYTE_USER; + pOBInit.USERType = OB_USER_SRAM_ECC; + pOBInit.USERConfig2 = OB_AXISRAM_ECC_DISABLE; + if (HAL_FLASHEx_OBProgram(&pOBInit) != HAL_OK) + { + Error_Handler(); + } + if (HAL_FLASH_OB_Lock() != HAL_OK) + { + Error_Handler(); + } + if (HAL_FLASH_Lock() != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN FLASH_Init 2 */ + + /* USER CODE END FLASH_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; +/* USER CODE BEGIN MX_GPIO_Init_1 */ +/* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pins : PD1 PD0 */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF8_UART4; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + +/* USER CODE BEGIN MX_GPIO_Init_2 */ +/* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Src/stm32h7rsxx_hal_msp.c b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Src/stm32h7rsxx_hal_msp.c new file mode 100644 index 00000000000..f236a66cbb6 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Src/stm32h7rsxx_hal_msp.c @@ -0,0 +1,87 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* Configure the system Power Supply */ + + if (HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY) != HAL_OK) + { + /* Initialization error */ + Error_Handler(); + } + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Src/stm32h7rsxx_it.c b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Src/stm32h7rsxx_it.c new file mode 100644 index 00000000000..b0b943f5ed4 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Src/stm32h7rsxx_it.c @@ -0,0 +1,203 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7rsxx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32h7rsxx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32H7RSxx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32h7rsxx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Src/system_stm32h7rsxx.c b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Src/system_stm32h7rsxx.c new file mode 100644 index 00000000000..33e4b7eeeff --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/Boot/Core/Src/system_stm32h7rsxx.c @@ -0,0 +1,304 @@ +/** + ****************************************************************************** + * @file system_stm32h7rsxx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h7rsxx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (sys_cpu_ck), it can + * be used by the user application to setup the + * SysTick timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (64 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32h7rsxx.s" file, to + * optionally configure the system clock before to branch to main program. + * + *============================================================================= + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32H7RSxx_System + * @{ + */ + +/** @addtogroup STM32H7RSxx_System_Private_Includes + * @{ + */ + +#include "stm32h7rsxx.h" +#include + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 25000000UL /*!< Value of the High-Speed External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 64000000UL /*!< Value of the High-Speed Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE 4000000UL /*!< Value of the Low-power Internal oscillator in Hz */ +#endif /* CSI_VALUE */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line or define USER_VECT_TAB_ADDRESS at compiler level if you need + to relocate the vector table anywhere in Flash or Sram, else the vector table is kept at + the automatic remap of the selected boot address */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line or define VECT_TAB_SRAM at compiler level if you need + to relocate your vector Table in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ + +#if defined(VECT_TAB_SRAM) +#if !defined(VECT_TAB_BASE_ADDRESS) +#define VECT_TAB_BASE_ADDRESS ITCM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#endif +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#endif +#else +#if !defined(VECT_TAB_BASE_ADDRESS) +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#endif +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#endif +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in two ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the first function listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = HSI_VALUE; + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @retval None + */ + +void SystemInit(void) +{ + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; +#endif + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to RCC registers values. + * The SystemCoreClock variable contains the core clock (sys_cpu_ck), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSI_VALUE(*) + * or CSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) CSI_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value + * 16 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t sysclk, hsivalue, pllsource, pllm, pllp, core_presc; + float_t pllfracn, pllvco; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x00: /* HSI used as system clock source (default after reset) */ + sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos)); + break; + + case 0x08: /* CSI used as system clock source */ + sysclk = CSI_VALUE; + break; + + case 0x10: /* HSE used as system clock source */ + sysclk = HSE_VALUE; + break; + + case 0x18: /* PLL1 used as system clock source */ + /* PLL1_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL1_VCO / PLL1R + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) ; + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) != 0U) + { + pllfracn = (float_t)(uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN)>> RCC_PLL1FRACR_FRACN_Pos)); + } + else + { + pllfracn = (float_t)0U; + } + + if (pllm != 0U) + { + switch (pllsource) + { + case 0x02: /* HSE used as PLL1 clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 ); + break; + + case 0x01: /* CSI used as PLL1 clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 ); + break; + + case 0x00: /* HSI used as PLL1 clock source */ + default: + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos)); + pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 ); + break; + } + pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U ) ; + sysclk = (uint32_t)(float_t)(pllvco/(float_t)pllp); + } + else + { + sysclk = 0U; + } + break; + + default: /* Unexpected, default to HSI used as system clock source (default after reset) */ + sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos)); + break; + } + + /* system clock frequency : CM7 CPU frequency */ + core_presc = (RCC->CDCFGR & RCC_CDCFGR_CPRE); + if (core_presc >= 8U) + { + SystemCoreClock = (sysclk >> (core_presc - RCC_CDCFGR_CPRE_3 + 1U)); + } + else + { + SystemCoreClock = sysclk; + } +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/CubeMX_Config.ioc new file mode 100644 index 00000000000..35e9a76ad31 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/CubeMX_Config.ioc @@ -0,0 +1,194 @@ +#MicroXplorer Configuration settings - do not modify +Appli.IPs=GPDMA1\:I,HPDMA1\:I,LINKEDLIST\:I,GPIO\:I,NVIC2\:I,UART4\:I +Boot.IPs=GPDMA1,HPDMA1,LINKEDLIST,RCC\:I,GPIO,NVIC1\:I,SYS\:I,CORTEX_M7\:I,FLASH\:I +CAD.formats= +CAD.pinconfig= +CAD.provider= +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.CPN=STM32H7S7L8H6H +Mcu.Context0=Boot +Mcu.Context1=Appli +Mcu.ContextNb=2 +Mcu.Family=STM32H7 +Mcu.IP0=CORTEX_M7 +Mcu.IP1=FLASH +Mcu.IP2=NVIC2 +Mcu.IP3=NVIC1 +Mcu.IP4=RCC +Mcu.IP5=SYS +Mcu.IP6=UART4 +Mcu.IPNb=7 +Mcu.Name=STM32H7S7L8HxH +Mcu.Package=TFBGA225 HEXA SMPS +Mcu.Pin0=PD1 +Mcu.Pin1=PD0 +Mcu.Pin2=PH0-OSC_IN(PH0) +Mcu.Pin3=PH1-OSC_OUT(PH1) +Mcu.Pin4=VP_FLASH_SIG_Activate_FlashIP +Mcu.Pin5=VP_SYS_VS_Systick +Mcu.PinsNb=6 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32H7S7L8HxH +MxCube.Version=6.99.23 +MxDb.Version=DB.6.0.100 +NVIC1.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.ForceEnableDMAVector=true +NVIC1.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC1.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC1.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC1.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.ForceEnableDMAVector=true +NVIC2.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC2.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC2.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC2.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PD0.GPIOParameters=PinAttribute +PD0.Locked=true +PD0.Mode=Asynchronous +PD0.PinAttribute=Appli +PD0.Signal=UART4_RX +PD1.GPIOParameters=PinAttribute +PD1.Locked=true +PD1.Mode=Asynchronous +PD1.PinAttribute=Appli +PD1.Signal=UART4_TX +PH0-OSC_IN(PH0).Mode=HSE-External-Oscillator +PH0-OSC_IN(PH0).Signal=RCC_OSC_IN +PH1-OSC_OUT(PH1).Mode=HSE-External-Oscillator +PH1-OSC_OUT(PH1).Signal=RCC_OSC_OUT +PinOutPanel.CurrentBGAView=Top +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage=..\\..\\..\\..\\..\\..\\..\\Packages\\STM32Cube\\Repository\\STM32Cube_FW_H7RS_V1.0.0RC1 +ProjectManager.DefaultFWLocation=false +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32H7S7L8HxH +ProjectManager.FirmwarePackage=STM32Cube FW_H7RS V0.3.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=App-0x200,EL-0x200,Boot-0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=2 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=true +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=CubeMX_Config.ioc +ProjectManager.ProjectName=CubeMX_Config +ProjectManager.ProjectStructure=Boot\:Boot Project\:false;App\:Appli Project\:true;EL\:Eloader Project\:false; +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=App-0x400,EL-0x400,Boot-0x400 +ProjectManager.TargetToolchain=MDK-ARM V5.37 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false-Boot,2-MX_FLASH_Init-FLASH-false-HAL-true-Boot,1-SystemClock_Config-RCC-false-HAL-false-Appli,2-MX_GPIO_Init-GPIO-false-HAL-true-Appli,3-MX_UART4_Init-UART4-false-HAL-true-Appli,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true-Boot,1-SystemClock_Config-RCC-false-HAL-false-Eloader +RCC.ADCFreq_Value=200000000 +RCC.ADFFreq_Value=280000000 +RCC.AHB1234Freq_Value=280000000 +RCC.AHB5ClockFreq_Value=280000000 +RCC.APB1Freq_Value=140000000 +RCC.APB2Freq_Value=140000000 +RCC.APB4Freq_Value=140000000 +RCC.APB5Freq_Value=140000000 +RCC.AXIClockFreq_Value=280000000 +RCC.BMPRE=RCC_HCLK_DIV2 +RCC.CECFreq_Value=32768 +RCC.CKPERFreq_Value=64000000 +RCC.CPREFreq_Value=560000000 +RCC.CortexFreq_Value=560000000 +RCC.CpuClockFreq_Value=560000000 +RCC.DIVM1=5 +RCC.DIVM2=8 +RCC.DIVN1=112 +RCC.DIVP1=1 +RCC.DIVP1Freq_Value=560000000 +RCC.DIVP2Freq_Value=200000000 +RCC.DIVP3Freq_Value=50000000 +RCC.DIVQ1Freq_Value=280000000 +RCC.DIVQ2Freq_Value=200000000 +RCC.DIVQ3Freq_Value=50000000 +RCC.DIVR1Freq_Value=280000000 +RCC.DIVR2Freq_Value=200000000 +RCC.DIVR3Freq_Value=50000000 +RCC.DIVS1Freq_Value=280000000 +RCC.DIVS2Freq_Value=200000000 +RCC.DIVS3Freq_Value=50000000 +RCC.DIVT1Freq_Value=280000000 +RCC.DIVT2Freq_Value=200000000 +RCC.DIVT3Freq_Value=50000000 +RCC.DTSFreq_Value=32768 +RCC.ETH1Freq_Value=25000000 +RCC.ETHPHYFreq_Value=25000000 +RCC.FDCANFreq_Value=25000000 +RCC.FMCFreq_Value=280000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=280000000 +RCC.HSE_VALUE=25000000 +RCC.I2C1Freq_Value=140000000 +RCC.I2C23Freq_Value=140000000 +RCC.IPParameters=ADCFreq_Value,ADFFreq_Value,AHB1234Freq_Value,AHB5ClockFreq_Value,APB1Freq_Value,APB2Freq_Value,APB4Freq_Value,APB5Freq_Value,AXIClockFreq_Value,BMPRE,CECFreq_Value,CKPERFreq_Value,CPREFreq_Value,CortexFreq_Value,CpuClockFreq_Value,DIVM1,DIVM2,DIVN1,DIVP1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,DIVS1Freq_Value,DIVS2Freq_Value,DIVS3Freq_Value,DIVT1Freq_Value,DIVT2Freq_Value,DIVT3Freq_Value,DTSFreq_Value,ETH1Freq_Value,ETHPHYFreq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,I2C1Freq_Value,I2C23Freq_Value,LPTIM1Freq_Value,LPTIM23Freq_Value,LPTIM45Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,OSPI1Freq_Value,OSPI2Freq_Value,PLLFRACN,PLLSource,PPRE1,PPRE2,PPRE4,PPRE5,PSSIFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI1Freq_Value,SPI23Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TPIUFreq_Value,Tim1OutputFreq_Value,Tim2OutputFreq_Value,UCPDFreq_Value,USART1Freq_Value,USART234578Freq_Value,USBOFSFreq_Value,USBPHYFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value +RCC.LPTIM1Freq_Value=140000000 +RCC.LPTIM23Freq_Value=140000000 +RCC.LPTIM45Freq_Value=140000000 +RCC.LPUART1Freq_Value=140000000 +RCC.LTDCFreq_Value=50000000 +RCC.MCO1PinFreq_Value=64000000 +RCC.MCO2PinFreq_Value=560000000 +RCC.OSPI1Freq_Value=280000000 +RCC.OSPI2Freq_Value=280000000 +RCC.PLLFRACN=0 +RCC.PLLSource=RCC_PLLSOURCE_HSE +RCC.PPRE1=RCC_APB1_DIV2 +RCC.PPRE2=RCC_APB2_DIV2 +RCC.PPRE4=RCC_APB4_DIV2 +RCC.PPRE5=RCC_APB5_DIV2 +RCC.PSSIFreq_Value=50000000 +RCC.RTCFreq_Value=32000 +RCC.SAI1Freq_Value=280000000 +RCC.SAI2Freq_Value=280000000 +RCC.SDMMCFreq_Value=200000000 +RCC.SPDIFRXFreq_Value=280000000 +RCC.SPI1Freq_Value=280000000 +RCC.SPI23Freq_Value=280000000 +RCC.SPI45Freq_Value=140000000 +RCC.SPI6Freq_Value=140000000 +RCC.SYSCLKFreq_VALUE=560000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.TPIUFreq_Value=186666666.66666666 +RCC.Tim1OutputFreq_Value=280000000 +RCC.Tim2OutputFreq_Value=280000000 +RCC.UCPDFreq_Value=16000000 +RCC.USART1Freq_Value=140000000 +RCC.USART234578Freq_Value=140000000 +RCC.USBOFSFreq_Value=48000000 +RCC.USBPHYFreq_Value=25000000 +RCC.VCO1OutputFreq_Value=560000000 +RCC.VCO2OutputFreq_Value=400000000 +RCC.VCO3OutputFreq_Value=100000000 +RCC.VCOInput1Freq_Value=5000000 +RCC.VCOInput2Freq_Value=3125000 +RCC.VCOInput3Freq_Value=781250 +VP_FLASH_SIG_Activate_FlashIP.Mode=Activate_FlashIP +VP_FLASH_SIG_Activate_FlashIP.Signal=FLASH_SIG_Activate_FlashIP +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom diff --git a/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/MDK-ARM/startup_stm32h7s7xx.s b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/MDK-ARM/startup_stm32h7s7xx.s new file mode 100644 index 00000000000..c47452b2e1a --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/CubeMX_Config/MDK-ARM/startup_stm32h7s7xx.s @@ -0,0 +1,633 @@ +;******************************************************************************* +;* File Name : startup_stm32h7s7xx.s +;* Author : MCD Application Team +;* Description : STM32H7S7xx Crypto devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;* Copyright (c) 2023 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + ; External Interrupts + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection + DCD 0 ; Reserved + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD IWDG_IRQHandler ; Internal Watchdog + DCD WWDG_IRQHandler ; Window Watchdog + DCD RCC_IRQHandler ; RCC global interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FLASH_IRQHandler ; FLASH interrupts + DCD RAMECC_IRQHandler ; RAMECC interrupts + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TAMP_IRQHandler ; Tamper and TimeStamp interrupts through EXTI Line detection + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD EXTI5_IRQHandler ; EXTI Line5 + DCD EXTI6_IRQHandler ; EXTI Line6 + DCD EXTI7_IRQHandler ; EXTI Line7 + DCD EXTI8_IRQHandler ; EXTI Line8 + DCD EXTI9_IRQHandler ; EXTI Line9 + DCD EXTI10_IRQHandler ; EXTI Line10 + DCD EXTI11_IRQHandler ; EXTI Line11 + DCD EXTI12_IRQHandler ; EXTI Line12 + DCD EXTI13_IRQHandler ; EXTI Line13 + DCD EXTI14_IRQHandler ; EXTI Line14 + DCD EXTI15_IRQHandler ; EXTI Line15 + DCD RTC_IRQHandler ; RTC wakeup and alarm interrupts through EXTI Line detection + DCD SAES_IRQHandler ; SAES + DCD CRYP_IRQHandler ; CRYP + DCD PKA_IRQHandler ; PKA + DCD HASH_IRQHandler ; HASH + DCD RNG_IRQHandler ; RNG + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 + DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 + DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 + DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 + DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 + DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 + DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 + DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD TIM5_IRQHandler ; TIM5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD TIM9_IRQHandler ; TIM9 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD SPI3_IRQHandler ; SPI3 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD HPDMA1_Channel0_IRQHandler ; HPDMA1 Channel 0 + DCD HPDMA1_Channel1_IRQHandler ; HPDMA1 Channel 1 + DCD HPDMA1_Channel2_IRQHandler ; HPDMA1 Channel 2 + DCD HPDMA1_Channel3_IRQHandler ; HPDMA1 Channel 3 + DCD HPDMA1_Channel4_IRQHandler ; HPDMA1 Channel 4 + DCD HPDMA1_Channel5_IRQHandler ; HPDMA1 Channel 5 + DCD HPDMA1_Channel6_IRQHandler ; HPDMA1 Channel 6 + DCD HPDMA1_Channel7_IRQHandler ; HPDMA1 Channel 7 + DCD SAI1_A_IRQHandler ; Serial Audio Interface 1 block A + DCD SAI1_B_IRQHandler ; Serial Audio Interface 1 block B + DCD SAI2_A_IRQHandler ; Serial Audio Interface 2 block A + DCD SAI2_B_IRQHandler ; Serial Audio Interface 2 block B + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD I3C1_EV_IRQHandler ; I3C1 Event + DCD I3C1_ER_IRQHandler ; I3C1 Error + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD ETH_IRQHandler ; Ethernet + DCD CORDIC_IRQHandler ; CORDIC + DCD GFXTIM_IRQHandler ; GFXTIM + DCD DCMIPP_IRQHandler ; DCMIPP + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD JPEG_IRQHandler ; JPEG + DCD GFXMMU_IRQHandler ; GFXMMU + DCD I3C1_WKUP_IRQHandler ; I3C1 wakeup + DCD MCE1_IRQHandler ; MCE1 + DCD MCE2_IRQHandler ; MCE2 + DCD MCE3_IRQHandler ; MCE3 + DCD XSPI1_IRQHandler ; XSPI1 + DCD XSPI2_IRQHandler ; XSPI2 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD LPTIM1_IRQHandler ; LP TIM1 + DCD LPTIM2_IRQHandler ; LP TIM2 + DCD LPTIM3_IRQHandler ; LP TIM3 + DCD LPTIM4_IRQHandler ; LP TIM4 + DCD LPTIM5_IRQHandler ; LP TIM5 + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD MDIOS_IRQHandler ; MDIOS + DCD ADF1_FLT0_IRQHandler ; ADF1 Filter 0 + DCD CRS_IRQHandler ; CRS + DCD UCPD1_IRQHandler ; UCPD1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD PSSI_IRQHandler ; PSSI + DCD LPUART1_IRQHandler ; LP UART1 + DCD WAKEUP_PIN_IRQHandler ; Wake-up pins interrupt + DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8 + DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9 + DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10 + DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11 + DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12 + DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13 + DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14 + DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15 + DCD HPDMA1_Channel8_IRQHandler ; HPDMA1 Channel 8 + DCD HPDMA1_Channel9_IRQHandler ; HPDMA1 Channel 9 + DCD HPDMA1_Channel10_IRQHandler ; HPDMA1 Channel 10 + DCD HPDMA1_Channel11_IRQHandler ; HPDMA1 Channel 11 + DCD HPDMA1_Channel12_IRQHandler ; HPDMA1 Channel 12 + DCD HPDMA1_Channel13_IRQHandler ; HPDMA1 Channel 13 + DCD HPDMA1_Channel14_IRQHandler ; HPDMA1 Channel 14 + DCD HPDMA1_Channel15_IRQHandler ; HPDMA1 Channel 15 + DCD GPU2D_IRQHandler ; GPU2D + DCD GPU2D_ER_IRQHandler ; GPU2D error + DCD ICACHE_IRQHandler ; ICACHE + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt 1 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt 1 + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT DTS_IRQHandler [WEAK] + EXPORT IWDG_IRQHandler [WEAK] + EXPORT WWDG_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RAMECC_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT TAMP_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI5_IRQHandler [WEAK] + EXPORT EXTI6_IRQHandler [WEAK] + EXPORT EXTI7_IRQHandler [WEAK] + EXPORT EXTI8_IRQHandler [WEAK] + EXPORT EXTI9_IRQHandler [WEAK] + EXPORT EXTI10_IRQHandler [WEAK] + EXPORT EXTI11_IRQHandler [WEAK] + EXPORT EXTI12_IRQHandler [WEAK] + EXPORT EXTI13_IRQHandler [WEAK] + EXPORT EXTI14_IRQHandler [WEAK] + EXPORT EXTI15_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT SAES_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT PKA_IRQHandler [WEAK] + EXPORT HASH_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT GPDMA1_Channel0_IRQHandler [WEAK] + EXPORT GPDMA1_Channel1_IRQHandler [WEAK] + EXPORT GPDMA1_Channel2_IRQHandler [WEAK] + EXPORT GPDMA1_Channel3_IRQHandler [WEAK] + EXPORT GPDMA1_Channel4_IRQHandler [WEAK] + EXPORT GPDMA1_Channel5_IRQHandler [WEAK] + EXPORT GPDMA1_Channel6_IRQHandler [WEAK] + EXPORT GPDMA1_Channel7_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT HPDMA1_Channel0_IRQHandler [WEAK] + EXPORT HPDMA1_Channel1_IRQHandler [WEAK] + EXPORT HPDMA1_Channel2_IRQHandler [WEAK] + EXPORT HPDMA1_Channel3_IRQHandler [WEAK] + EXPORT HPDMA1_Channel4_IRQHandler [WEAK] + EXPORT HPDMA1_Channel5_IRQHandler [WEAK] + EXPORT HPDMA1_Channel6_IRQHandler [WEAK] + EXPORT HPDMA1_Channel7_IRQHandler [WEAK] + EXPORT SAI1_A_IRQHandler [WEAK] + EXPORT SAI1_B_IRQHandler [WEAK] + EXPORT SAI2_A_IRQHandler [WEAK] + EXPORT SAI2_B_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT I3C1_EV_IRQHandler [WEAK] + EXPORT I3C1_ER_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT GFXTIM_IRQHandler [WEAK] + EXPORT DCMIPP_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT GFXMMU_IRQHandler [WEAK] + EXPORT I3C1_WKUP_IRQHandler [WEAK] + EXPORT MCE1_IRQHandler [WEAK] + EXPORT MCE2_IRQHandler [WEAK] + EXPORT MCE3_IRQHandler [WEAK] + EXPORT XSPI1_IRQHandler [WEAK] + EXPORT XSPI2_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT TIM12_IRQHandler [WEAK] + EXPORT TIM13_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT ADF1_FLT0_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT UCPD1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT PSSI_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + EXPORT GPDMA1_Channel8_IRQHandler [WEAK] + EXPORT GPDMA1_Channel9_IRQHandler [WEAK] + EXPORT GPDMA1_Channel10_IRQHandler [WEAK] + EXPORT GPDMA1_Channel11_IRQHandler [WEAK] + EXPORT GPDMA1_Channel12_IRQHandler [WEAK] + EXPORT GPDMA1_Channel13_IRQHandler [WEAK] + EXPORT GPDMA1_Channel14_IRQHandler [WEAK] + EXPORT GPDMA1_Channel15_IRQHandler [WEAK] + EXPORT HPDMA1_Channel8_IRQHandler [WEAK] + EXPORT HPDMA1_Channel9_IRQHandler [WEAK] + EXPORT HPDMA1_Channel10_IRQHandler [WEAK] + EXPORT HPDMA1_Channel11_IRQHandler [WEAK] + EXPORT HPDMA1_Channel12_IRQHandler [WEAK] + EXPORT HPDMA1_Channel13_IRQHandler [WEAK] + EXPORT HPDMA1_Channel14_IRQHandler [WEAK] + EXPORT HPDMA1_Channel15_IRQHandler [WEAK] + EXPORT GPU2D_IRQHandler [WEAK] + EXPORT GPU2D_ER_IRQHandler [WEAK] + EXPORT ICACHE_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + +PVD_PVM_IRQHandler +DTS_IRQHandler +IWDG_IRQHandler +WWDG_IRQHandler +RCC_IRQHandler +FLASH_IRQHandler +RAMECC_IRQHandler +FPU_IRQHandler +TAMP_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI5_IRQHandler +EXTI6_IRQHandler +EXTI7_IRQHandler +EXTI8_IRQHandler +EXTI9_IRQHandler +EXTI10_IRQHandler +EXTI11_IRQHandler +EXTI12_IRQHandler +EXTI13_IRQHandler +EXTI14_IRQHandler +EXTI15_IRQHandler +RTC_IRQHandler +SAES_IRQHandler +CRYP_IRQHandler +PKA_IRQHandler +HASH_IRQHandler +RNG_IRQHandler +ADC1_2_IRQHandler +GPDMA1_Channel0_IRQHandler +GPDMA1_Channel1_IRQHandler +GPDMA1_Channel2_IRQHandler +GPDMA1_Channel3_IRQHandler +GPDMA1_Channel4_IRQHandler +GPDMA1_Channel5_IRQHandler +GPDMA1_Channel6_IRQHandler +GPDMA1_Channel7_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +TIM5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +TIM9_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +HPDMA1_Channel0_IRQHandler +HPDMA1_Channel1_IRQHandler +HPDMA1_Channel2_IRQHandler +HPDMA1_Channel3_IRQHandler +HPDMA1_Channel4_IRQHandler +HPDMA1_Channel5_IRQHandler +HPDMA1_Channel6_IRQHandler +HPDMA1_Channel7_IRQHandler +SAI1_A_IRQHandler +SAI1_B_IRQHandler +SAI2_A_IRQHandler +SAI2_B_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +I3C1_EV_IRQHandler +I3C1_ER_IRQHandler +OTG_HS_IRQHandler +ETH_IRQHandler +CORDIC_IRQHandler +GFXTIM_IRQHandler +DCMIPP_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +JPEG_IRQHandler +GFXMMU_IRQHandler +I3C1_WKUP_IRQHandler +MCE1_IRQHandler +MCE2_IRQHandler +MCE3_IRQHandler +XSPI1_IRQHandler +XSPI2_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +SDMMC2_IRQHandler +OTG_FS_IRQHandler +TIM12_IRQHandler +TIM13_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +SPDIF_RX_IRQHandler +MDIOS_IRQHandler +ADF1_FLT0_IRQHandler +CRS_IRQHandler +UCPD1_IRQHandler +CEC_IRQHandler +PSSI_IRQHandler +LPUART1_IRQHandler +WAKEUP_PIN_IRQHandler +GPDMA1_Channel8_IRQHandler +GPDMA1_Channel9_IRQHandler +GPDMA1_Channel10_IRQHandler +GPDMA1_Channel11_IRQHandler +GPDMA1_Channel12_IRQHandler +GPDMA1_Channel13_IRQHandler +GPDMA1_Channel14_IRQHandler +GPDMA1_Channel15_IRQHandler +HPDMA1_Channel8_IRQHandler +HPDMA1_Channel9_IRQHandler +HPDMA1_Channel10_IRQHandler +HPDMA1_Channel11_IRQHandler +HPDMA1_Channel12_IRQHandler +HPDMA1_Channel13_IRQHandler +HPDMA1_Channel14_IRQHandler +HPDMA1_Channel15_IRQHandler +GPU2D_IRQHandler +GPU2D_ER_IRQHandler +ICACHE_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN2_IT1_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/bsp/stm32/stm32h7s7-st-disco/board/Kconfig b/bsp/stm32/stm32h7s7-st-disco/board/Kconfig new file mode 100644 index 00000000000..a5afaf45476 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/Kconfig @@ -0,0 +1,262 @@ +menu "Hardware Drivers Config" +config SOC_STM32H7RS + bool + select SOC_SERIES_STM32H7RS + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select RT_USING_CACHE + default y + +config SOC_SERIES_STM32H7RS + bool + select ARCH_ARM_CORTEX_M7 + select SOC_FAMILY_STM32 + default y + +menu "Onboard Peripheral Drivers" + + config BSP_USING_USB_TO_USART + bool "Enable Debuger USART (uart4)" + select BSP_USING_UART + select BSP_USING_UART4 + default n + + menuconfig BSP_USING_FS + bool "Enable filesystem" + select RT_USING_DFS + select RT_USING_DFS_ROMFS + default n + if BSP_USING_FS + config BSP_USING_SDCARD_FS + bool "Enable SDCARD filesystem" + select BSP_USING_SDIO_ARTPI + select BSP_USING_SDIO1 + select RT_USING_DFS_ELMFAT + default n + config BSP_USING_SPI_FLASH_FS + bool "Enable SPI FLASH filesystem" + select BSP_USING_SPI_FLASH + select RT_USING_MTD_NOR + select PKG_USING_LITTLEFS + default n + endif + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default n + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + select RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + select RT_SERIAL_USING_DMA + default n + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on BSP_USING_UART1 + default 256 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on BSP_USING_UART1 + default 0 + + endif + + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on BSP_USING_UART3 + default 256 + + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on BSP_USING_UART3 + default 0 + endif + + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + select RT_SERIAL_USING_DMA + default n + + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + select RT_SERIAL_USING_DMA + default n + + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on BSP_USING_UART4 + default 256 + + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on BSP_USING_UART4 + default 0 + endif + + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on BSP_USING_UART6 + default 256 + + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on BSP_USING_UART6 + default 0 + + endif + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1" + default n + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + config BSP_USING_SPI3 + bool "Enable SPI3" + default n + config BSP_USING_SPI4 + bool "Enable SPI4" + default n + config BSP_USING_SPI5 + bool "Enable SPI5" + default n + config BSP_USING_SPI6 + bool "Enable SPI6" + default n + endif + + config BSP_USING_ONCHIP_RTC + bool "Enable Onchip RTC" + select RT_USING_RTC + default n + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS (software simulation)" + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + default n + if BSP_USING_I2C + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + comment "Notice: PB6 --> 22; PB7 --> 23" + config BSP_I2C1_SCL_PIN + int "I2C1 scl pin number" + range 0 175 + default 22 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 175 + default 23 + endif + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS (software simulation)" + default n + if BSP_USING_I2C2 + comment "Notice: PH13 --> 125; PH15 --> 127" + config BSP_I2C2_SCL_PIN + int "i2c2 scl pin number" + range 1 176 + default 127 + config BSP_I2C2_SDA_PIN + int "I2C2 sda pin number" + range 0 175 + default 125 + endif + menuconfig BSP_USING_I2C3 + bool "Enable I2C3 BUS (software simulation)" + default n + if BSP_USING_I2C3 + comment "Notice: PH12 --> 124; PH11 --> 123" + config BSP_I2C3_SCL_PIN + int "i2c3 scl pin number" + range 0 175 + default 123 + config BSP_I2C3_SDA_PIN + int "I2C3 sda pin number" + range 0 175 + default 124 + endif + endif + + config BSP_USING_USBD + bool "Enable USB Device" + select RT_USING_USB_DEVICE + default n + + menuconfig BSP_USING_USBH + bool "Enable USB Host" + select RT_USING_USB_HOST + default n + if BSP_USING_USBH + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers" + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + + config BSP_USING_LTDC + bool + default n + source "$BSP_DIR/../libraries/HAL_Drivers/drivers/Kconfig" + +endmenu + +endmenu diff --git a/bsp/stm32/stm32h7s7-st-disco/board/SConscript b/bsp/stm32/stm32h7s7-st-disco/board/SConscript new file mode 100644 index 00000000000..fdfc9bbe500 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/SConscript @@ -0,0 +1,38 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +objs = [] +cwd = GetCurrentDir() +list = os.listdir(cwd) + +# add the general drivers. +src = Glob('board.c') + +# add cubemx drivers +src += Split(''' +CubeMX_Config/Appli/Core/Src/stm32h7rsxx_hal_msp.c +''') + +if GetDepend(['BSP_USING_FS']): + src += Glob('port/filesystem.c') + +path = [cwd] +path += [cwd + '/CubeMX_Config/Appli/Core/Inc'] +path += [cwd + '/port'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/gcc/startup_stm32h7s7xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/arm/startup_stm32h7s7xx.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/STM32H7RSxx_HAL/CMSIS/Device/ST/STM32H7RSxx/Source/Templates/iar/startup_stm32h7s7xx.s'] + +CPPDEFINES = ['STM32H7S7xx'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/stm32/stm32h7s7-st-disco/board/board.c b/bsp/stm32/stm32h7s7-st-disco/board/board.c new file mode 100644 index 00000000000..09f28c2d1e2 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/board.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-10 RealThread first version + */ + +#include "board.h" + +#define DBG_TAG "board" +#define DBG_LVL DBG_INFO +#include +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + //Notice: system main clock is set in user boot stage. + //you can modify it but be aware on XPI1 and XPI2 status. + return; +} + +int clock_information(void) +{ + LOG_I("System Clock information"); + LOG_I("SYSCLK_Frequency = %d", HAL_RCC_GetSysClockFreq()); + LOG_I("HCLK_Frequency = %d", HAL_RCC_GetHCLKFreq()); + LOG_I("PCLK1_Frequency = %d", HAL_RCC_GetPCLK1Freq()); + LOG_I("PCLK2_Frequency = %d", HAL_RCC_GetPCLK2Freq()); + LOG_I("XSPI1_Frequency = %d", HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_XSPI1)); + LOG_I("XSPI2_Frequency = %d", HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_XSPI2)); + return RT_EOK; +} +INIT_BOARD_EXPORT(clock_information); diff --git a/bsp/stm32/stm32h7s7-st-disco/board/board.h b/bsp/stm32/stm32h7s7-st-disco/board/board.h new file mode 100644 index 00000000000..5d1e9e90162 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/board.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-10 RealThread first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*-------------------------- CHIP CONFIG BEGIN --------------------------*/ + +#define CHIP_FAMILY_STM32 +#define CHIP_SERIES_STM32H7RS +#define CHIP_NAME_STM32H750XBHX + +/*-------------------------- CHIP CONFIG END --------------------------*/ + +/*-------------------------- ROM/RAM CONFIG BEGIN --------------------------*/ +/** + * @brief H7RS7 SRAM MEMORY Layout + * 0x24060000 - 0x23071FFF AXI SRAM shared with ECC + * 0x24040000 - 0x2305FFFF AXI SRAM shared with DTCM + * 0x24020000 - 0x2403FFFF AXI SRAM + * 0x24000000 - 0x2401FFFF AXI SRAM shared with ITCM + */ +#define ROM_START ((uint32_t)0x70000000) +#define ROM_SIZE (131072) +#define ROM_END ((uint32_t)(ROM_START + ROM_SIZE * 1024)) + +#define RAM_START (0x24000000) +#define RAM_SIZE (456) +#define RAM_END (RAM_START + RAM_SIZE * 1024) + +/*-------------------------- ROM/RAM CONFIG END --------------------------*/ + +/*-------------------------- CLOCK CONFIG BEGIN --------------------------*/ + +#define BSP_CLOCK_SOURCE ("HSE") +#define BSP_CLOCK_SOURCE_FREQ_MHZ ((int32_t)0) +#define BSP_CLOCK_SYSTEM_FREQ_MHZ ((int32_t)480) + +/*-------------------------- CLOCK CONFIG END --------------------------*/ + +/*-------------------------- UART CONFIG BEGIN --------------------------*/ + +/** After configuring corresponding UART or UART DMA, you can use it. + * + * STEP 1, define macro define related to the serial port opening based on the serial port number + * such as #define BSP_USING_UATR1 + * + * STEP 2, according to the corresponding pin of serial port, define the related serial port information macro + * such as #define BSP_UART1_TX_PIN "PA9" + * #define BSP_UART1_RX_PIN "PA10" + * + * STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings. + * RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode + * + * STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file + * such as #define BSP_UART1_RX_USING_DMA + * + */ + +#define STM32_FLASH_START_ADRESS ROM_START +#define STM32_FLASH_SIZE ROM_SIZE +#define STM32_FLASH_END_ADDRESS ROM_END + +#define STM32_SRAM1_SIZE RAM_SIZE +#define STM32_SRAM1_START RAM_START +#define STM32_SRAM1_END RAM_END + +#if defined(__ARMCC_VERSION) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END STM32_SRAM1_END + +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32/stm32h7s7-st-disco/board/linker_scripts/link.icf b/bsp/stm32/stm32h7s7-st-disco/board/linker_scripts/link.icf new file mode 100644 index 00000000000..8eb669c55ac --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00020000; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20020000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32h7s7-st-disco/board/linker_scripts/link.lds b/bsp/stm32/stm32h7s7-st-disco/board/linker_scripts/link.lds new file mode 100644 index 00000000000..9266a2dd95f --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/linker_scripts/link.lds @@ -0,0 +1,206 @@ +/* + * linker script for STM32H7S7L8HxH with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ +ROM (rx) : ORIGIN =0x70000000,LENGTH =8192k +RAM (rw) : ORIGIN =0x24000000,LENGTH =456k +RxDecripSection (rw) : ORIGIN =0x30040000,LENGTH =32k +TxDecripSection (rw) : ORIGIN =0x30040060,LENGTH =32k +RxArraySection (rw) : ORIGIN =0x30040200,LENGTH =32k +} +ENTRY(Reset_Handler) +_system_stack_size = 0x400; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for at server */ + . = ALIGN(4); + __rtatcmdtab_start = .; + KEEP(*(RtAtCmdTab)) + __rtatcmdtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + .RxDecripSection (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + *(.RxDecripSection) + *(.RxDecripSection.*) + . = ALIGN(4); + __RxDecripSection_free__ = .; + } > RxDecripSection + + .TxDecripSection (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + *(.TxDecripSection) + *(.TxDecripSection.*) + . = ALIGN(4); + __TxDecripSection_free__ = .; + } > TxDecripSection + + .RxArraySection (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + *(.RxArraySection) + *(.RxArraySection.*) + . = ALIGN(4); + __RxArraySection_free__ = .; + } > RxArraySection + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/stm32/stm32h7s7-st-disco/board/linker_scripts/link.sct b/bsp/stm32/stm32h7s7-st-disco/board/linker_scripts/link.sct new file mode 100644 index 00000000000..a1d713d0eb8 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/linker_scripts/link.sct @@ -0,0 +1,17 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x70000000 0x00800000 { ; load region size_region + ER_IROM1 0x70000000 0x00800000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x24000000 0x00072000 { ; AXI SRAM MAXIM 456K + .ANY (+RW +ZI) + } +} + + diff --git a/bsp/stm32/stm32h7s7-st-disco/board/port/fal_cfg.h b/bsp/stm32/stm32h7s7-st-disco/board/port/fal_cfg.h new file mode 100644 index 00000000000..ac5a076eff4 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/port/fal_cfg.h @@ -0,0 +1,54 @@ +/* + * File : fal_cfg.h + * This file is part of FAL (Flash Abstraction Layer) package + * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2018-05-17 armink the first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#define NOR_FLASH_DEV_NAME "norflash0" + +/* ===================== Flash device Configuration ========================= */ +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "wifi_image", NOR_FLASH_DEV_NAME, 0, 512*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "bt_image", NOR_FLASH_DEV_NAME, 512*1024, 512*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 1024*1024, 2*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 3*1024*1024, 1*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "filesystem", NOR_FLASH_DEV_NAME, 4*1024*1024, 12*1024*1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/stm32/stm32h7s7-st-disco/board/port/filesystem.c b/bsp/stm32/stm32h7s7-st-disco/board/port/filesystem.c new file mode 100644 index 00000000000..7e20e4f19bf --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/board/port/filesystem.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 balanceTWK add sdcard port file + * 2019-06-11 WillianChan Add SD card hot plug detection + */ + +#include + +#ifdef BSP_USING_FS +#if DFS_FILESYSTEMS_MAX < 4 + #error "Please define DFS_FILESYSTEMS_MAX more than 4" +#endif +#if DFS_FILESYSTEM_TYPES_MAX < 4 + #error "Please define DFS_FILESYSTEM_TYPES_MAX more than 4" +#endif + +#include + +#ifdef BSP_USING_SDCARD_FS + #include + #include "drv_sdio.h" +#endif +#ifdef BSP_USING_SPI_FLASH_FS + #include "fal.h" +#endif +#define DBG_TAG "app.filesystem" +#define DBG_LVL DBG_INFO +#include + + +#include "dfs_romfs.h" + +#ifdef RT_USING_DFS_ELMFAT +static const struct romfs_dirent _romfs_root[] = +{ + {ROMFS_DIRENT_DIR, "flash", RT_NULL, 0}, + {ROMFS_DIRENT_DIR, "sdcard", RT_NULL, 0}, + {ROMFS_DIRENT_DIR, "filesystem", RT_NULL, 0} +}; +#else +static const struct romfs_dirent _romfs_root[] = +{ + {ROMFS_DIRENT_DIR, "flash", RT_NULL, 0}, + {ROMFS_DIRENT_DIR, "sdcard", RT_NULL, 0} +}; +#endif + +const struct romfs_dirent romfs_root = +{ + ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root) / sizeof(_romfs_root[0]) +}; + + +#ifdef BSP_USING_SDCARD_FS + +/* SD Card hot plug detection pin */ +#define SD_CHECK_PIN GET_PIN(D, 5) + +static void _sdcard_mount(void) +{ + rt_device_t device; + + device = rt_device_find("sd"); + + if (device == NULL) + { + mmcsd_wait_cd_changed(0); + sdcard_change(); + mmcsd_wait_cd_changed(RT_WAITING_FOREVER); + device = rt_device_find("sd"); + } + + if (device != RT_NULL) + { + if (dfs_mount("sd", "/sdcard", "elm", 0, 0) == RT_EOK) + { + LOG_I("sd card mount to '/sdcard'"); + } + else + { + LOG_W("sd card mount to '/sdcard' failed!"); + } + } +} + +static void _sdcard_unmount(void) +{ + rt_thread_mdelay(200); + dfs_unmount("/sdcard"); + LOG_I("Unmount \"/sdcard\""); + + mmcsd_wait_cd_changed(0); + sdcard_change(); + mmcsd_wait_cd_changed(RT_WAITING_FOREVER); +} + +static void sd_mount(void *parameter) +{ + rt_uint8_t re_sd_check_pin = 1; + rt_thread_mdelay(200); + + if (rt_pin_read(SD_CHECK_PIN)) + { + _sdcard_mount(); + } + + while (1) + { + rt_thread_mdelay(200); + + if (!re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) != 0) + { + _sdcard_mount(); + } + + if (re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) == 0) + { + _sdcard_unmount(); + } + } +} + +#endif /* BSP_USING_SDCARD_FS */ + +int mount_init(void) +{ + #ifdef RT_USING_DFS_ROMFS + if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) != 0) + { + LOG_E("rom mount to '/' failed!"); + } + #endif + + #ifdef BSP_USING_SPI_FLASH_FS + struct rt_device *flash_dev = RT_NULL; + + #ifndef RT_USING_WIFI + fal_init(); + #endif + + flash_dev = fal_mtd_nor_device_create("filesystem"); + + #ifdef RT_USING_DFS_ELMFAT + flash_dev = fal_blk_device_create("filesystem"); + if (flash_dev) + { + //mount filesystem + if (dfs_mount(flash_dev->parent.name, "/filesystem", "elm", 0, 0) != 0) + { + LOG_W("mount to '/filesystem' failed! try to mkfs %s", flash_dev->parent.name); + dfs_mkfs("elm", flash_dev->parent.name); + if (dfs_mount(flash_dev->parent.name, "/filesystem", "elm", 0, 0) == 0) + { + LOG_I("mount to '/filesystem' success!"); + } + } + else + { + LOG_I("mount to '/filesystem' success!"); + } + } + else + { + LOG_E("Can't create block device filesystem or bt_image partition."); + } + #else + if (flash_dev) + { + //mount filesystem + if (dfs_mount(flash_dev->parent.name, "/flash", "lfs", 0, 0) != 0) + { + LOG_W("mount to '/flash' failed! try to mkfs %s", flash_dev->parent.name); + dfs_mkfs("lfs", flash_dev->parent.name); + + if (dfs_mount(flash_dev->parent.name, "/flash", "lfs", 0, 0) == 0) + { + LOG_I("mount to '/flash' success!"); + } + } + else + { + LOG_I("mount to '/flash' success!"); + } + } + else + { + LOG_E("Can't create block device filesystem or bt_image partition."); + } + #endif + + #endif + + #ifdef BSP_USING_SDCARD_FS + rt_thread_t tid; + + rt_pin_mode(SD_CHECK_PIN, PIN_MODE_INPUT_PULLUP); + + tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, + 2048, RT_THREAD_PRIORITY_MAX - 2, 20); + + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + } + + #endif + return RT_EOK; +} +INIT_APP_EXPORT(mount_init); + +#endif /* BSP_USING_FS */ diff --git a/bsp/stm32/stm32h7s7-st-disco/figures/board.jpg b/bsp/stm32/stm32h7s7-st-disco/figures/board.jpg new file mode 100644 index 00000000000..322a779c0ce Binary files /dev/null and b/bsp/stm32/stm32h7s7-st-disco/figures/board.jpg differ diff --git a/bsp/stm32/stm32h7s7-st-disco/h7s7_disco_bootloader.bin b/bsp/stm32/stm32h7s7-st-disco/h7s7_disco_bootloader.bin new file mode 100644 index 00000000000..75cc2204406 Binary files /dev/null and b/bsp/stm32/stm32h7s7-st-disco/h7s7_disco_bootloader.bin differ diff --git a/bsp/stm32/stm32h7s7-st-disco/project.uvoptx b/bsp/stm32/stm32h7s7-st-disco/project.uvoptx new file mode 100644 index 00000000000..6e3163725b0 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/project.uvoptx @@ -0,0 +1,177 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32H7Rx_64k -FL010000 -FS08000000 -FP0($$Device:STM32H7S7L8Hx$CMSIS\Flash\STM32H7Rx_64k.FLM) + + + 0 + ST-LINKIII-KEIL_SWO + -U003C00203431511737393330 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FCFFFC -FN2 -FF0STM32H7Rx_64k.FLM -FS08000000 -FL010000 -FP0($$Device:STM32H7S7L8Hx$CMSIS\Flash\STM32H7Rx_64k.FLM) -FF1MX66UW1G45G_STM32H7S78-DK.FLM -FS170000000 -FL18000000 -FP1($$Device:STM32H7S7L8Hx$CMSIS\Flash\MX66UW1G45G_STM32H7S78-DK.FLM) -WA0 -WE0 -WVCE4 -WS2710 -WM0 -WP2 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/bsp/stm32/stm32h7s7-st-disco/project.uvprojx b/bsp/stm32/stm32h7s7-st-disco/project.uvprojx new file mode 100644 index 00000000000..0a60e1051dd --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/project.uvprojx @@ -0,0 +1,1371 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + STM32H7S7L8Hx + STMicroelectronics + Keil.STM32H7Rx-7Sx_DFP.0.0.3 + https://www.keil.com/pack/ + IRAM(0x20000000,0x20000) IROM(0x08000000,0x010000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32H7Rx_64k -FS08000000 -FL010000 -FP0($$Device:STM32H7S7L8Hx$CMSIS\Flash\STM32H7Rx_64k.FLM)) + 0 + + + + + + + + + + + $$Device:STM32H7S7L8Hx$CMSIS\SVD\STM32H7RSxx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + 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+ + + irq.c + 1 + ..\..\..\src\irq.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_comm.c + 1 + ..\..\..\src\scheduler_comm.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_up.c + 1 + ..\..\..\src\scheduler_up.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + libcpu + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m7\context_rvds.S + + + + + cpu_cache.c + 1 + ..\..\..\libcpu\arm\cortex-m7\cpu_cache.c + + + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m7\cpuport.c + + + + + Libraries + + + stm32h7rsxx_hal_cryp.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cryp.c + + + + + stm32h7rsxx_hal_cortex.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cortex.c + + + + + stm32h7rsxx_hal_dma_ex.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma_ex.c + + + + + stm32h7rsxx_hal_gpio.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_gpio.c + + + + + stm32h7rsxx_hal_rng.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rng.c + + + + + stm32h7rsxx_hal_adc_ex.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_adc_ex.c + + + + + stm32h7rsxx_hal_rcc.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc.c + + + + + stm32h7rsxx_hal_pwr.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr.c + + + + + stm32h7rsxx_hal_usart.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_usart.c + + + + + stm32h7rsxx_hal_dma.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_dma.c + + + + + stm32h7rsxx_hal_pwr_ex.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_pwr_ex.c + + + + + stm32h7rsxx_hal.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal.c + + + + + stm32h7rsxx_hal_flash.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash.c + + + + + stm32h7rsxx_hal_cec.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cec.c + + + + + stm32h7rsxx_hal_sram.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_sram.c + + + + + stm32h7rsxx_hal_uart_ex.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart_ex.c + + + + + stm32h7rsxx_hal_flash_ex.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_flash_ex.c + + + + + stm32h7rsxx_hal_adc.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_adc.c + + + + + stm32h7rsxx_hal_xspi.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_xspi.c + + + + + stm32h7rsxx_hal_uart.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_uart.c + + + + + stm32h7rsxx_hal_crc.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_crc.c + + + + + stm32h7rsxx_hal_rcc_ex.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_rcc_ex.c + + + + + stm32h7rsxx_hal_crc_ex.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_crc_ex.c + + + + + system_stm32h7rsxx.c + 1 + ..\libraries\STM32H7RSxx_HAL\CMSIS\Device\ST\STM32H7RSxx\Source\Templates\system_stm32h7rsxx.c + + + + + stm32h7rsxx_hal_cryp_ex.c + 1 + ..\libraries\STM32H7RSxx_HAL\STM32H7RSxx_HAL_Driver\Src\stm32h7rsxx_hal_cryp_ex.c + + + + + + + + + + + + diff --git a/bsp/stm32/stm32h7s7-st-disco/rtconfig.h b/bsp/stm32/stm32h7s7-st-disco/rtconfig.h new file mode 100644 index 00000000000..ca15f6ac01c --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/rtconfig.h @@ -0,0 +1,272 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart4" +#define RT_VER_NUM 0x50100 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +#define RT_USING_CACHE +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M7 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_SPI +#define RT_USING_TOUCH +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Memory protection */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* BL808 WiFi */ + + +/* CYW43439 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + + +/* Kendryte SDK */ + + +/* sensors drivers */ + + +/* touch drivers */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +#define SOC_FAMILY_STM32 + +/* Hardware Drivers Config */ + +#define SOC_STM32H7RS +#define SOC_SERIES_STM32H7RS + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_USB_TO_USART + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART4 +#define BSP_UART4_RX_BUFSIZE 256 +#define BSP_UART4_TX_BUFSIZE 0 + +#endif diff --git a/bsp/stm32/stm32h7s7-st-disco/rtconfig.py b/bsp/stm32/stm32h7s7-st-disco/rtconfig.py new file mode 100644 index 00000000000..fa67b769411 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/rtconfig.py @@ -0,0 +1,185 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'/opt/gcc-arm-none-eabi/bin/' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=gnu99' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp.sp' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=gnu99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp.sp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-M7 ' + CFLAGS += ' -mcpu=cortex-M7 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=gnu99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M7' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv5_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M7' + AFLAGS += ' --fpu VFPv5_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/stm32/stm32h7s7-st-disco/template.uvoptx b/bsp/stm32/stm32h7s7-st-disco/template.uvoptx new file mode 100644 index 00000000000..6e3163725b0 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/template.uvoptx @@ -0,0 +1,177 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32H7Rx_64k -FL010000 -FS08000000 -FP0($$Device:STM32H7S7L8Hx$CMSIS\Flash\STM32H7Rx_64k.FLM) + + + 0 + ST-LINKIII-KEIL_SWO + -U003C00203431511737393330 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FCFFFC -FN2 -FF0STM32H7Rx_64k.FLM -FS08000000 -FL010000 -FP0($$Device:STM32H7S7L8Hx$CMSIS\Flash\STM32H7Rx_64k.FLM) -FF1MX66UW1G45G_STM32H7S78-DK.FLM -FS170000000 -FL18000000 -FP1($$Device:STM32H7S7L8Hx$CMSIS\Flash\MX66UW1G45G_STM32H7S78-DK.FLM) -WA0 -WE0 -WVCE4 -WS2710 -WM0 -WP2 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/bsp/stm32/stm32h7s7-st-disco/template.uvprojx b/bsp/stm32/stm32h7s7-st-disco/template.uvprojx new file mode 100644 index 00000000000..b02d2b53e74 --- /dev/null +++ b/bsp/stm32/stm32h7s7-st-disco/template.uvprojx @@ -0,0 +1,392 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + STM32H7S7L8Hx + STMicroelectronics + Keil.STM32H7Rx-7Sx_DFP.0.0.3 + https://www.keil.com/pack/ + IRAM(0x20000000,0x20000) IROM(0x08000000,0x010000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32H7Rx_64k -FS08000000 -FL010000 -FP0($$Device:STM32H7S7L8Hx$CMSIS\Flash\STM32H7Rx_64k.FLM)) + 0 + + + + + + + + + + + $$Device:STM32H7S7L8Hx$CMSIS\SVD\STM32H7RSxx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x10000 + + + 1 + 0x30000000 + 0x48000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 3 + 5 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32l010-st-nucleo/project.ewp b/bsp/stm32/stm32l010-st-nucleo/project.ewp index 52a4f69034d..2c7da730ee9 100644 --- a/bsp/stm32/stm32l010-st-nucleo/project.ewp +++ b/bsp/stm32/stm32l010-st-nucleo/project.ewp @@ -2226,6 +2226,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l010-st-nucleo/project.uvprojx b/bsp/stm32/stm32l010-st-nucleo/project.uvprojx index 07dcbcf39f0..bd710da0613 100644 --- a/bsp/stm32/stm32l010-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l010-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l053-st-nucleo/project.ewp b/bsp/stm32/stm32l053-st-nucleo/project.ewp index f1c60fa69df..cf5a09d9d0d 100644 --- a/bsp/stm32/stm32l053-st-nucleo/project.ewp +++ b/bsp/stm32/stm32l053-st-nucleo/project.ewp @@ -2226,6 +2226,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l053-st-nucleo/project.uvprojx b/bsp/stm32/stm32l053-st-nucleo/project.uvprojx index bcd3070934b..607334519b5 100644 --- a/bsp/stm32/stm32l053-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l053-st-nucleo/project.uvprojx @@ -482,6 +482,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l412-st-nucleo/project.ewp b/bsp/stm32/stm32l412-st-nucleo/project.ewp index 87aba903b68..5b1219896f4 100644 --- a/bsp/stm32/stm32l412-st-nucleo/project.ewp +++ b/bsp/stm32/stm32l412-st-nucleo/project.ewp @@ -2151,6 +2151,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l412-st-nucleo/project.uvprojx b/bsp/stm32/stm32l412-st-nucleo/project.uvprojx index 6fb24111449..bdc7bf36a8b 100644 --- a/bsp/stm32/stm32l412-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l412-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l431-BearPi/applications/arduino_pinout/SConscript b/bsp/stm32/stm32l431-BearPi/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32l431-BearPi/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32l431-BearPi/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32l431-BearPi/project.ewp b/bsp/stm32/stm32l431-BearPi/project.ewp index 7b4aeef0392..ce167478dac 100644 --- a/bsp/stm32/stm32l431-BearPi/project.ewp +++ b/bsp/stm32/stm32l431-BearPi/project.ewp @@ -2182,6 +2182,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l431-BearPi/project.uvprojx b/bsp/stm32/stm32l431-BearPi/project.uvprojx index 420825aafbc..8ca1e4f112e 100644 --- a/bsp/stm32/stm32l431-BearPi/project.uvprojx +++ b/bsp/stm32/stm32l431-BearPi/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l432-st-nucleo/project.ewp b/bsp/stm32/stm32l432-st-nucleo/project.ewp index 8c5ab9d4e4e..f532686262a 100644 --- a/bsp/stm32/stm32l432-st-nucleo/project.ewp +++ b/bsp/stm32/stm32l432-st-nucleo/project.ewp @@ -2151,6 +2151,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l432-st-nucleo/project.uvprojx b/bsp/stm32/stm32l432-st-nucleo/project.uvprojx index bd4604abd61..3d70a208d42 100644 --- a/bsp/stm32/stm32l432-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l432-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l433-ali-startkit/project.ewp b/bsp/stm32/stm32l433-ali-startkit/project.ewp index 51d577e5e09..ca8f4e7556f 100644 --- a/bsp/stm32/stm32l433-ali-startkit/project.ewp +++ b/bsp/stm32/stm32l433-ali-startkit/project.ewp @@ -2208,6 +2208,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l433-ali-startkit/project.uvprojx b/bsp/stm32/stm32l433-ali-startkit/project.uvprojx index cc417b23538..2c5f0977e19 100644 --- a/bsp/stm32/stm32l433-ali-startkit/project.uvprojx +++ b/bsp/stm32/stm32l433-ali-startkit/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l433-st-nucleo/project.ewp b/bsp/stm32/stm32l433-st-nucleo/project.ewp index 3f956bb75a7..9ac606ee087 100644 --- a/bsp/stm32/stm32l433-st-nucleo/project.ewp +++ b/bsp/stm32/stm32l433-st-nucleo/project.ewp @@ -2151,6 +2151,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l433-st-nucleo/project.uvprojx b/bsp/stm32/stm32l433-st-nucleo/project.uvprojx index 9458f7c616a..74d1e7be044 100644 --- a/bsp/stm32/stm32l433-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l433-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l452-st-nucleo/project.ewp b/bsp/stm32/stm32l452-st-nucleo/project.ewp index 2ead5fa660a..77067c39258 100644 --- a/bsp/stm32/stm32l452-st-nucleo/project.ewp +++ b/bsp/stm32/stm32l452-st-nucleo/project.ewp @@ -2196,6 +2196,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l452-st-nucleo/project.uvprojx b/bsp/stm32/stm32l452-st-nucleo/project.uvprojx index 0e486ce4705..509e0552429 100644 --- a/bsp/stm32/stm32l452-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l452-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l475-atk-pandora/applications/arduino_pinout/SConscript b/bsp/stm32/stm32l475-atk-pandora/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32l475-atk-pandora/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32l475-atk-pandora/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32l475-atk-pandora/project.ewp b/bsp/stm32/stm32l475-atk-pandora/project.ewp index 623d3825c94..cd980a35a33 100644 --- a/bsp/stm32/stm32l475-atk-pandora/project.ewp +++ b/bsp/stm32/stm32l475-atk-pandora/project.ewp @@ -2151,6 +2151,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l475-atk-pandora/project.uvprojx b/bsp/stm32/stm32l475-atk-pandora/project.uvprojx index 5bd2a1e4301..344775e20ef 100644 --- a/bsp/stm32/stm32l475-atk-pandora/project.uvprojx +++ b/bsp/stm32/stm32l475-atk-pandora/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l475-st-discovery/project.ewp b/bsp/stm32/stm32l475-st-discovery/project.ewp index 9a402aa0ba6..b9ee60e9474 100644 --- a/bsp/stm32/stm32l475-st-discovery/project.ewp +++ b/bsp/stm32/stm32l475-st-discovery/project.ewp @@ -2153,6 +2153,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l475-st-discovery/project.uvprojx b/bsp/stm32/stm32l475-st-discovery/project.uvprojx index 9479d1a6f2c..852677e4f1b 100644 --- a/bsp/stm32/stm32l475-st-discovery/project.uvprojx +++ b/bsp/stm32/stm32l475-st-discovery/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l476-st-nucleo/applications/arduino_pinout/SConscript b/bsp/stm32/stm32l476-st-nucleo/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32l476-st-nucleo/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32l476-st-nucleo/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32l476-st-nucleo/project.ewp b/bsp/stm32/stm32l476-st-nucleo/project.ewp index 4046bc9a84e..3f2d628b703 100644 --- a/bsp/stm32/stm32l476-st-nucleo/project.ewp +++ b/bsp/stm32/stm32l476-st-nucleo/project.ewp @@ -2153,6 +2153,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l476-st-nucleo/project.uvprojx b/bsp/stm32/stm32l476-st-nucleo/project.uvprojx index a09cea0d8a8..dbc186b58e6 100644 --- a/bsp/stm32/stm32l476-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l476-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l496-ali-developer/project.ewp b/bsp/stm32/stm32l496-ali-developer/project.ewp index 5bbb05711df..d504c08fe94 100644 --- a/bsp/stm32/stm32l496-ali-developer/project.ewp +++ b/bsp/stm32/stm32l496-ali-developer/project.ewp @@ -2153,6 +2153,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l496-ali-developer/project.uvprojx b/bsp/stm32/stm32l496-ali-developer/project.uvprojx index fcac8357cb2..e4c5c8df843 100644 --- a/bsp/stm32/stm32l496-ali-developer/project.uvprojx +++ b/bsp/stm32/stm32l496-ali-developer/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l496-st-discovery/project.ewp b/bsp/stm32/stm32l496-st-discovery/project.ewp index f291f6c5d1c..f37f6b7fa19 100644 --- a/bsp/stm32/stm32l496-st-discovery/project.ewp +++ b/bsp/stm32/stm32l496-st-discovery/project.ewp @@ -2151,6 +2151,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l496-st-discovery/project.uvprojx b/bsp/stm32/stm32l496-st-discovery/project.uvprojx index 615425e1a4b..9eef98d8725 100644 --- a/bsp/stm32/stm32l496-st-discovery/project.uvprojx +++ b/bsp/stm32/stm32l496-st-discovery/project.uvprojx @@ -487,6 +487,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l496-st-nucleo/project.ewp b/bsp/stm32/stm32l496-st-nucleo/project.ewp index 5bbb05711df..d504c08fe94 100644 --- a/bsp/stm32/stm32l496-st-nucleo/project.ewp +++ b/bsp/stm32/stm32l496-st-nucleo/project.ewp @@ -2153,6 +2153,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l496-st-nucleo/project.uvprojx b/bsp/stm32/stm32l496-st-nucleo/project.uvprojx index 0e23e95020d..6fea39d0261 100644 --- a/bsp/stm32/stm32l496-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l496-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l4r5-st-nucleo/project.ewp b/bsp/stm32/stm32l4r5-st-nucleo/project.ewp index 54e70c48850..8bf4cb2a4a0 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/project.ewp +++ b/bsp/stm32/stm32l4r5-st-nucleo/project.ewp @@ -2226,6 +2226,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l4r5-st-nucleo/project.uvprojx b/bsp/stm32/stm32l4r5-st-nucleo/project.uvprojx index f4b60f21032..6f7cc2fe087 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l4r5-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l4r9-st-eval/project.ewp b/bsp/stm32/stm32l4r9-st-eval/project.ewp index be1b40f1ded..c8acdb9e69f 100644 --- a/bsp/stm32/stm32l4r9-st-eval/project.ewp +++ b/bsp/stm32/stm32l4r9-st-eval/project.ewp @@ -2205,6 +2205,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l4r9-st-eval/project.uvprojx b/bsp/stm32/stm32l4r9-st-eval/project.uvprojx index 63c08ffa39e..6c7881087ff 100644 --- a/bsp/stm32/stm32l4r9-st-eval/project.uvprojx +++ b/bsp/stm32/stm32l4r9-st-eval/project.uvprojx @@ -542,6 +542,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l4r9-st-sensortile-box/project.ewp b/bsp/stm32/stm32l4r9-st-sensortile-box/project.ewp index 3c202b6226a..36dba92bcd9 100644 --- a/bsp/stm32/stm32l4r9-st-sensortile-box/project.ewp +++ b/bsp/stm32/stm32l4r9-st-sensortile-box/project.ewp @@ -2208,6 +2208,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l4r9-st-sensortile-box/project.uvprojx b/bsp/stm32/stm32l4r9-st-sensortile-box/project.uvprojx index 2e507184c6b..24f9d64a65d 100644 --- a/bsp/stm32/stm32l4r9-st-sensortile-box/project.uvprojx +++ b/bsp/stm32/stm32l4r9-st-sensortile-box/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32l552-st-nucleo/project.ewp b/bsp/stm32/stm32l552-st-nucleo/project.ewp index cd688ac70f8..3c4bfb5cef8 100644 --- a/bsp/stm32/stm32l552-st-nucleo/project.ewp +++ b/bsp/stm32/stm32l552-st-nucleo/project.ewp @@ -2226,6 +2226,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32l552-st-nucleo/project.uvprojx b/bsp/stm32/stm32l552-st-nucleo/project.uvprojx index 8667163f88b..cd5138709fe 100644 --- a/bsp/stm32/stm32l552-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l552-st-nucleo/project.uvprojx @@ -487,6 +487,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/drv_openamp.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/drv_openamp.c index 7d2b743e5ec..8895fb9e9a5 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/drv_openamp.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/drv_openamp.c @@ -27,7 +27,7 @@ static VIRT_UART_HandleTypeDef huart0; static rt_uint8_t rx_buffer[MAX_BUFFER_SIZE]; static rt_uint8_t tx_buffer[MAX_BUFFER_SIZE]; - + struct rthw_openamp { struct rt_device parent; @@ -36,41 +36,41 @@ struct rthw_openamp }; static struct rthw_openamp dev_openamp; -void IPCC_RX1_IRQHandler(void) +void IPCC_RX1_IRQHandler(void) { rt_interrupt_enter(); - + HAL_IPCC_RX_IRQHandler(&hipcc); - + rt_interrupt_leave(); } void IPCC_TX1_IRQHandler(void) { rt_interrupt_enter(); - + HAL_IPCC_TX_IRQHandler(&hipcc); - + rt_interrupt_leave(); } -void VIRT_UART0_RxCpltCallback(VIRT_UART_HandleTypeDef *huart) -{ +void VIRT_UART0_RxCpltCallback(VIRT_UART_HandleTypeDef *huart) +{ rt_uint16_t rx_size = 0, i = 0; rt_size_t count, size, offset; rt_uint8_t *buf = RT_NULL; - + struct rthw_openamp *device; device = (struct rthw_openamp *)rt_device_find("openamp"); RT_ASSERT(device != RT_NULL); - - buf = device->serial.rbuf; + + buf = device->serial.rbuf; count = device->serial.rbuf_count; size = device->serial.rbuf_size; offset = device->serial.rbuf_start + count; - + rt_sem_take(&device->sema, RT_WAITING_FOREVER); - + rx_size = (huart->RxXferSize < MAX_BUFFER_SIZE) ? huart->RxXferSize : MAX_BUFFER_SIZE - 1; if (count < size) @@ -79,7 +79,7 @@ void VIRT_UART0_RxCpltCallback(VIRT_UART_HandleTypeDef *huart) { offset -= size; } - + for (i = 0; i < rx_size; i++) { buf[offset++] = huart->pRxBuffPtr[i]; @@ -88,16 +88,16 @@ void VIRT_UART0_RxCpltCallback(VIRT_UART_HandleTypeDef *huart) } device->serial.rbuf_count = count; - + rt_sem_release(&device->sema); } - + static rt_err_t _init(struct rt_device *dev) { struct rthw_openamp *device; device = (struct rthw_openamp *)dev; RT_ASSERT(device != RT_NULL); - + device->serial.rbuf_start = 0; device->serial.rbuf_count = 0; device->serial.tbuf_start = 0; @@ -106,79 +106,79 @@ static rt_err_t _init(struct rt_device *dev) device->serial.tbuf_size = MAX_BUFFER_SIZE; device->serial.rbuf = rx_buffer; device->serial.tbuf = tx_buffer; - + if (rt_sem_init(&device->sema, "openamplock", 1, RT_IPC_FLAG_FIFO) != RT_EOK) { return -RT_ERROR; } - + return RT_EOK; } static rt_ssize_t _read(struct rt_device *dev, rt_off_t pos, void *buffer, rt_size_t size) { rt_size_t count, rbsize, offset; - rt_uint8_t *buf = RT_NULL; + rt_uint8_t *buf = RT_NULL; rt_uint8_t *pBuffer = RT_NULL; rt_uint16_t i = 0; - + struct rthw_openamp *device; device = (struct rthw_openamp *)dev; RT_ASSERT(device != RT_NULL); - + pBuffer = (unsigned char*)buffer; count = device->serial.rbuf_count; buf = device->serial.rbuf; - + if (count == 0) { return -RT_ERROR; } - + rt_sem_take(&device->sema, RT_WAITING_FOREVER); - + if (count >= size) { count = size; - } + } offset = device->serial.rbuf_start; rbsize = device->serial.rbuf_size; - + for (i = 0; i < count; i++) { *pBuffer++ = buf[offset++]; if (offset > rbsize) { - offset = 0; + offset = 0; } } device->serial.rbuf_start = offset; device->serial.rbuf_count -= count; - + rt_sem_release(&device->sema); - + return count; } - + static rt_ssize_t _write(struct rt_device *dev, rt_off_t pos, const void *buffer, rt_size_t size) { rt_err_t result = VIRT_UART_OK; - + struct rthw_openamp *device; device = (struct rthw_openamp *)dev; RT_ASSERT(device != RT_NULL); - + rt_sem_take(&device->sema, RT_WAITING_FOREVER); - result = VIRT_UART_Transmit(&huart0, (uint8_t *)buffer, size); + result = VIRT_UART_Transmit(&huart0, (uint8_t *)buffer, size); rt_sem_release(&device->sema); - + if (result != VIRT_UART_OK) { return -RT_ERROR; } - + return size; } @@ -206,7 +206,7 @@ static rt_err_t rt_hw_openamp_register(struct rthw_openamp *openamp, const char } static int openamp_init(void) -{ +{ extern int MX_OPENAMP_Init(int RPMsgRole, rpmsg_ns_bind_cb ns_bind_cb); /* IPCC init */ @@ -217,25 +217,25 @@ static int openamp_init(void) } /* openamp slave device */ MX_OPENAMP_Init(RPMSG_REMOTE, NULL); - - if (VIRT_UART_Init(&huart0) != VIRT_UART_OK) + + if (VIRT_UART_Init(&huart0) != VIRT_UART_OK) { return -RT_ERROR; } - if (VIRT_UART_RegisterCallback(&huart0, VIRT_UART_RXCPLT_CB_ID, VIRT_UART0_RxCpltCallback) != VIRT_UART_OK) + if (VIRT_UART_RegisterCallback(&huart0, VIRT_UART_RXCPLT_CB_ID, VIRT_UART0_RxCpltCallback) != VIRT_UART_OK) { return -RT_ERROR; } - - return RT_EOK; + + return RT_EOK; } int rt_hw_openamp_init(void) { openamp_init(); - + rt_hw_openamp_register(&dev_openamp, "openamp", 0, NULL); - + if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "openamp") == 0) { rt_console_set_device(RT_CONSOLE_DEVICE_NAME); @@ -245,27 +245,27 @@ int rt_hw_openamp_init(void) } INIT_PREV_EXPORT(rt_hw_openamp_init); -static void openamp_thread_entry(void *parameter) +static void openamp_thread_entry(void *parameter) { rt_size_t size = 0; struct rthw_openamp *device = RT_NULL; - + device = (struct rthw_openamp *)rt_device_find("openamp"); RT_ASSERT(device != RT_NULL); - - for (;;) + + for (;;) { OPENAMP_check_for_message(); size = device->serial.rbuf_count; if (size > 0) { - if (device->parent.rx_indicate != RT_NULL) + if (device->parent.rx_indicate != RT_NULL) { device->parent.rx_indicate(&device->parent, size); } } - + rt_thread_mdelay(1); } } @@ -273,22 +273,22 @@ static void openamp_thread_entry(void *parameter) static int creat_openamp_thread(void) { rt_thread_t tid = RT_NULL; - - tid = rt_thread_create("OpenAMP", - openamp_thread_entry, - RT_NULL, - OPENAMP_THREAD_STACK_SIZE, - OPENAMP_THREAD_PRIORITY, + + tid = rt_thread_create("OpenAMP", + openamp_thread_entry, + RT_NULL, + OPENAMP_THREAD_STACK_SIZE, + OPENAMP_THREAD_PRIORITY, OPENAMP_THREAD_TIMESLICE); - - if (tid == RT_NULL) + + if (tid == RT_NULL) { LOG_E("openamp thread create failed!"); return -RT_ERROR; - } - + } + rt_thread_startup(tid); - + return RT_EOK; } INIT_APP_EXPORT(creat_openamp_thread); @@ -298,7 +298,7 @@ INIT_APP_EXPORT(creat_openamp_thread); static int console(int argc, char **argv) { rt_err_t result = RT_EOK; - + if (argc > 1) { if (!strcmp(argv[1], "set")) diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/drv_openamp.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/drv_openamp.h index df1533b38b6..5f0cf49aee2 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/drv_openamp.h +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/drv_openamp.h @@ -18,22 +18,22 @@ extern "C" { struct rt_openamp { - rt_uint8_t *rbuf; - rt_uint8_t *tbuf; - volatile rt_uint16_t rbuf_size; + rt_uint8_t *rbuf; + rt_uint8_t *tbuf; + volatile rt_uint16_t rbuf_size; volatile rt_uint16_t tbuf_size; volatile rt_uint16_t rbuf_start; volatile rt_uint16_t rbuf_count; volatile rt_uint16_t tbuf_start; volatile rt_uint16_t tbuf_count; }; - + #define OPENAMP_THREAD_STACK_SIZE 512 #define OPENAMP_THREAD_PRIORITY 5 #define OPENAMP_THREAD_TIMESLICE 10 #define MAX_BUFFER_SIZE 256 - + #ifdef __cplusplus } #endif diff --git a/bsp/stm32/stm32mp157a-st-discovery/project.ewp b/bsp/stm32/stm32mp157a-st-discovery/project.ewp index e4e1aaad750..513f1af6962 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/project.ewp +++ b/bsp/stm32/stm32mp157a-st-discovery/project.ewp @@ -2242,6 +2242,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32mp157a-st-discovery/project.uvprojx b/bsp/stm32/stm32mp157a-st-discovery/project.uvprojx index 93763dc2185..d1e85b30e60 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/project.uvprojx +++ b/bsp/stm32/stm32mp157a-st-discovery/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32mp157a-st-ev1/project.ewp b/bsp/stm32/stm32mp157a-st-ev1/project.ewp index beda93f5a6f..04f3cb9cc36 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/project.ewp +++ b/bsp/stm32/stm32mp157a-st-ev1/project.ewp @@ -2240,6 +2240,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32mp157a-st-ev1/project.uvprojx b/bsp/stm32/stm32mp157a-st-ev1/project.uvprojx index 868fb89fb6b..e732a1f5bf4 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/project.uvprojx +++ b/bsp/stm32/stm32mp157a-st-ev1/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32u575-st-nucleo/applications/arduino_pinout/SConscript b/bsp/stm32/stm32u575-st-nucleo/applications/arduino_pinout/SConscript index 25399290275..da85e053c37 100644 --- a/bsp/stm32/stm32u575-st-nucleo/applications/arduino_pinout/SConscript +++ b/bsp/stm32/stm32u575-st-nucleo/applications/arduino_pinout/SConscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/stm32/stm32u575-st-nucleo/project.ewp b/bsp/stm32/stm32u575-st-nucleo/project.ewp index 75c0111b66c..6d5ac95d695 100644 --- a/bsp/stm32/stm32u575-st-nucleo/project.ewp +++ b/bsp/stm32/stm32u575-st-nucleo/project.ewp @@ -2239,6 +2239,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c @@ -2501,10 +2504,10 @@ $PROJ_DIR$\..\..\..\components\mprotect\examples\mprotect_example_exclusive_region.c - $PROJ_DIR$\..\..\..\components\mprotect\examples\mprotect_example_exception_hook.c + $PROJ_DIR$\..\..\..\components\mprotect\mprotect.c - $PROJ_DIR$\..\..\..\components\mprotect\mprotect.c + $PROJ_DIR$\..\..\..\components\mprotect\examples\mprotect_example_exception_hook.c diff --git a/bsp/stm32/stm32u575-st-nucleo/project.uvprojx b/bsp/stm32/stm32u575-st-nucleo/project.uvprojx index 3fc5b809d80..b97569563d5 100644 --- a/bsp/stm32/stm32u575-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32u575-st-nucleo/project.uvprojx @@ -543,6 +543,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1440,30 +1459,30 @@ mprotect - mprotect.c + mprotect_example_ro_data.c 1 - ..\..\..\components\mprotect\mprotect.c + ..\..\..\components\mprotect\examples\mprotect_example_ro_data.c - mprotect_example_exclusive_region.c + mprotect_example_exception_hook.c 1 - ..\..\..\components\mprotect\examples\mprotect_example_exclusive_region.c + ..\..\..\components\mprotect\examples\mprotect_example_exception_hook.c - mprotect_example_ro_data.c + mprotect_example_exclusive_region.c 1 - ..\..\..\components\mprotect\examples\mprotect_example_ro_data.c + ..\..\..\components\mprotect\examples\mprotect_example_exclusive_region.c - mprotect_example_exception_hook.c + mprotect.c 1 - ..\..\..\components\mprotect\examples\mprotect_example_exception_hook.c + ..\..\..\components\mprotect\mprotect.c diff --git a/bsp/stm32/stm32u585-iot02a/project.ewp b/bsp/stm32/stm32u585-iot02a/project.ewp index 1765dffcca7..729dedaaa49 100644 --- a/bsp/stm32/stm32u585-iot02a/project.ewp +++ b/bsp/stm32/stm32u585-iot02a/project.ewp @@ -2226,6 +2226,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32u585-iot02a/project.uvprojx b/bsp/stm32/stm32u585-iot02a/project.uvprojx index 94a9cd60b3e..23786974070 100644 --- a/bsp/stm32/stm32u585-iot02a/project.uvprojx +++ b/bsp/stm32/stm32u585-iot02a/project.uvprojx @@ -487,6 +487,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32wb55-st-nucleo/project.ewp b/bsp/stm32/stm32wb55-st-nucleo/project.ewp index a0993f4df98..151dd479179 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/project.ewp +++ b/bsp/stm32/stm32wb55-st-nucleo/project.ewp @@ -2153,6 +2153,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/stm32/stm32wb55-st-nucleo/project.uvprojx b/bsp/stm32/stm32wb55-st-nucleo/project.uvprojx index d7e5a904c49..a4acf5b6540 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32wb55-st-nucleo/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32wl55-st-nucleo/project.uvprojx b/bsp/stm32/stm32wl55-st-nucleo/project.uvprojx index d01bfa69d40..2ece37b5aee 100644 --- a/bsp/stm32/stm32wl55-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32wl55-st-nucleo/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32wle5-yizhilian-lm401/project.uvprojx b/bsp/stm32/stm32wle5-yizhilian-lm401/project.uvprojx index 51718f68c80..c3809d9ba06 100644 --- a/bsp/stm32/stm32wle5-yizhilian-lm401/project.uvprojx +++ b/bsp/stm32/stm32wle5-yizhilian-lm401/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/stm32/stm32wle5-yizhilian-lm402/project.uvprojx b/bsp/stm32/stm32wle5-yizhilian-lm402/project.uvprojx index 6d8a7ab6ec3..66f17843066 100644 --- a/bsp/stm32/stm32wle5-yizhilian-lm402/project.uvprojx +++ b/bsp/stm32/stm32wle5-yizhilian-lm402/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/synwit/libraries/SWM320_drivers/drv_gpio.c b/bsp/synwit/libraries/SWM320_drivers/drv_gpio.c index daffdffb9ec..01a5ee50880 100644 --- a/bsp/synwit/libraries/SWM320_drivers/drv_gpio.c +++ b/bsp/synwit/libraries/SWM320_drivers/drv_gpio.c @@ -325,16 +325,16 @@ static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t swm_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t swm_pin_read(rt_device_t dev, rt_base_t pin) { const struct swm_pin_device *gpio_obj; gpio_obj = _pin2struct(pin); if (gpio_obj == RT_NULL) { - return PIN_LOW; + return -RT_EINVAL; } - return (rt_int8_t)GPIO_GetBit(gpio_obj->gpio, gpio_obj->pin); + return (rt_ssize_t)GPIO_GetBit(gpio_obj->gpio, gpio_obj->pin); } static rt_err_t swm_pin_attach_irq(struct rt_device *device, @@ -496,14 +496,15 @@ static rt_base_t swm_pin_get(const char *name) } const static struct rt_pin_ops swm_pin_ops = - { - .pin_mode = swm_pin_mode, - .pin_write = swm_pin_write, - .pin_read = swm_pin_read, - .pin_attach_irq = swm_pin_attach_irq, - .pin_detach_irq = swm_pin_detach_irq, - .pin_irq_enable = swm_pin_irq_enable, - .pin_get = swm_pin_get}; +{ + .pin_mode = swm_pin_mode, + .pin_write = swm_pin_write, + .pin_read = swm_pin_read, + .pin_attach_irq = swm_pin_attach_irq, + .pin_detach_irq = swm_pin_detach_irq, + .pin_irq_enable = swm_pin_irq_enable, + .pin_get = swm_pin_get +}; static void swm_pin_isr(GPIO_TypeDef *GPIOx) { diff --git a/bsp/synwit/libraries/SWM341_drivers/drv_gpio.c b/bsp/synwit/libraries/SWM341_drivers/drv_gpio.c index 586530359b4..752f32cf850 100644 --- a/bsp/synwit/libraries/SWM341_drivers/drv_gpio.c +++ b/bsp/synwit/libraries/SWM341_drivers/drv_gpio.c @@ -347,16 +347,16 @@ static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t swm_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t swm_pin_read(rt_device_t dev, rt_base_t pin) { const struct swm_pin_device *gpio_obj; gpio_obj = _pin2struct(pin); if (gpio_obj == RT_NULL) { - return PIN_LOW; + return -RT_EINVAL; } - return (rt_int8_t)GPIO_GetBit(gpio_obj->gpio, gpio_obj->pin); + return (rt_ssize_t)GPIO_GetBit(gpio_obj->gpio, gpio_obj->pin); } static rt_err_t swm_pin_attach_irq(struct rt_device *device, @@ -521,14 +521,15 @@ static rt_base_t swm_pin_get(const char *name) } static const struct rt_pin_ops swm_pin_ops = - { - .pin_mode = swm_pin_mode, - .pin_write = swm_pin_write, - .pin_read = swm_pin_read, - .pin_attach_irq = swm_pin_attach_irq, - .pin_detach_irq = swm_pin_detach_irq, - .pin_irq_enable = swm_pin_irq_enable, - .pin_get = swm_pin_get}; +{ + .pin_mode = swm_pin_mode, + .pin_write = swm_pin_write, + .pin_read = swm_pin_read, + .pin_attach_irq = swm_pin_attach_irq, + .pin_detach_irq = swm_pin_detach_irq, + .pin_irq_enable = swm_pin_irq_enable, + .pin_get = swm_pin_get +}; static void swm_pin_isr(GPIO_TypeDef *GPIOx) { diff --git a/bsp/synwit/swm320-mini/project.ewp b/bsp/synwit/swm320-mini/project.ewp index 3f14f18aadf..1bcfa8fcccb 100644 --- a/bsp/synwit/swm320-mini/project.ewp +++ b/bsp/synwit/swm320-mini/project.ewp @@ -2147,6 +2147,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c @@ -2265,71 +2268,71 @@ Libraries - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_gpio.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_norflash.c $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_exti.c - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_timr.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_sdio.c - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_wdt.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_uart.c - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_adc.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_gpio.c - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_uart.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_spi.c - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_sdio.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_flash.c - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_spi.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_adc.c - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_sram.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_lcd.c $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_port.c - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_flash.c - - - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_crc.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_timr.c - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_lcd.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_wdt.c - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_i2c.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_can.c $PROJ_DIR$\..\libraries\SWM320_CSL\CMSIS\DeviceSupport\system_SWM320.c - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_norflash.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_dma.c $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_sdram.c - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_dma.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_pwm.c - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_can.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_crc.c - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_pwm.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_i2c.c - $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_rtc.c + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_sram.c $PROJ_DIR$\..\libraries\SWM320_CSL\CMSIS\DeviceSupport\startup\iar\startup_SWM320.s + + $PROJ_DIR$\..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_rtc.c + POSIX diff --git a/bsp/synwit/swm320-mini/project.uvprojx b/bsp/synwit/swm320-mini/project.uvprojx index 3ba4dd24ea7..dee8798c197 100644 --- a/bsp/synwit/swm320-mini/project.uvprojx +++ b/bsp/synwit/swm320-mini/project.uvprojx @@ -495,6 +495,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1026,37 +1045,37 @@ Libraries - SWM320_uart.c + SWM320_sdram.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_uart.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_sdram.c - SWM320_pwm.c + SWM320_uart.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_pwm.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_uart.c - SWM320_exti.c + SWM320_wdt.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_exti.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_wdt.c - SWM320_can.c + SWM320_lcd.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_can.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_lcd.c - SWM320_spi.c + SWM320_port.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_spi.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_port.c @@ -1068,114 +1087,114 @@ - SWM320_sram.c + SWM320_crc.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_sram.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_crc.c - SWM320_flash.c + SWM320_spi.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_flash.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_spi.c - SWM320_port.c + SWM320_sdio.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_port.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_sdio.c - SWM320_norflash.c + SWM320_pwm.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_norflash.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_pwm.c - SWM320_crc.c + SWM320_rtc.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_crc.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_rtc.c - startup_SWM320.s - 2 - ..\libraries\SWM320_CSL\CMSIS\DeviceSupport\startup\arm\startup_SWM320.s + SWM320_dma.c + 1 + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_dma.c - SWM320_adc.c + SWM320_i2c.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_adc.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_i2c.c - SWM320_dma.c - 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_dma.c + startup_SWM320.s + 2 + ..\libraries\SWM320_CSL\CMSIS\DeviceSupport\startup\arm\startup_SWM320.s - SWM320_gpio.c + SWM320_exti.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_gpio.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_exti.c - SWM320_wdt.c + SWM320_adc.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_wdt.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_adc.c - SWM320_rtc.c + SWM320_sram.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_rtc.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_sram.c - SWM320_sdio.c + SWM320_can.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_sdio.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_can.c - SWM320_lcd.c + SWM320_flash.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_lcd.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_flash.c - SWM320_i2c.c + SWM320_norflash.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_i2c.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_norflash.c - SWM320_sdram.c + SWM320_timr.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_sdram.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_timr.c - SWM320_timr.c + SWM320_gpio.c 1 - ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_timr.c + ..\libraries\SWM320_CSL\SWM320_StdPeriph_Driver\SWM320_gpio.c diff --git a/bsp/synwit/swm341-mini/project.ewp b/bsp/synwit/swm341-mini/project.ewp index 6b41dcf2575..51726bc3e0b 100644 --- a/bsp/synwit/swm341-mini/project.ewp +++ b/bsp/synwit/swm341-mini/project.ewp @@ -2147,6 +2147,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c @@ -2271,97 +2274,97 @@ Libraries - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_iofilt.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_jpeg.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_adc.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_qei.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_timr.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_flash.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_qei.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_uart.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_dma2d.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_cordic.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_div.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_lcd.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_jpeg.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_dac.c $PROJ_DIR$\..\libraries\SWM341_CSL\CMSIS\DeviceSupport\startup\iar\startup_SWM341.s - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_pwm.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sfc.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_lcd.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_i2c.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_rtc.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_exti.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_usbh.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_wdt.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_usbd.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_can.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_gpio.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sdio.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_port.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_rtc.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_spi.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_gpio.c - $PROJ_DIR$\..\libraries\SWM341_CSL\CMSIS\DeviceSupport\system_SWM341.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_dma2d.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_uart.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_div.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_wdt.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_spi.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_dma.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_port.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_crc.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_timr.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sdram.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_iofilt.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sfc.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_usbd.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_flash.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_dma.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_can.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sleep.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_dac.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sdram.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_exti.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_crc.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_i2c.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_pwm.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sdio.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_usbh.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sleep.c + $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_adc.c - $PROJ_DIR$\..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_cordic.c + $PROJ_DIR$\..\libraries\SWM341_CSL\CMSIS\DeviceSupport\system_SWM341.c diff --git a/bsp/synwit/swm341-mini/project.uvprojx b/bsp/synwit/swm341-mini/project.uvprojx index f4b347ef374..2d6f5f847ef 100644 --- a/bsp/synwit/swm341-mini/project.uvprojx +++ b/bsp/synwit/swm341-mini/project.uvprojx @@ -496,6 +496,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1041,177 +1060,177 @@ Libraries - SWM341_can.c + SWM341_dma2d.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_can.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_dma2d.c - SWM341_i2c.c + SWM341_port.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_i2c.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_port.c - SWM341_qei.c + SWM341_dac.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_qei.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_dac.c - SWM341_usbh.c + SWM341_jpeg.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_usbh.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_jpeg.c - SWM341_wdt.c + SWM341_flash.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_wdt.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_flash.c - SWM341_iofilt.c + SWM341_qei.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_iofilt.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_qei.c - SWM341_sdram.c + SWM341_sdio.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sdram.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sdio.c - SWM341_div.c + SWM341_uart.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_div.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_uart.c - SWM341_lcd.c + SWM341_sleep.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_lcd.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sleep.c - SWM341_rtc.c + SWM341_cordic.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_rtc.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_cordic.c - SWM341_port.c + SWM341_gpio.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_port.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_gpio.c - SWM341_flash.c + SWM341_rtc.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_flash.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_rtc.c - SWM341_sleep.c + SWM341_timr.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sleep.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_timr.c - SWM341_dac.c + SWM341_div.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_dac.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_div.c - SWM341_jpeg.c + SWM341_adc.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_jpeg.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_adc.c - system_SWM341.c + SWM341_iofilt.c 1 - ..\libraries\SWM341_CSL\CMSIS\DeviceSupport\system_SWM341.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_iofilt.c - SWM341_exti.c + SWM341_crc.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_exti.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_crc.c - SWM341_cordic.c + SWM341_sdram.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_cordic.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sdram.c - SWM341_usbd.c + system_SWM341.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_usbd.c + ..\libraries\SWM341_CSL\CMSIS\DeviceSupport\system_SWM341.c - SWM341_timr.c + SWM341_lcd.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_timr.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_lcd.c - SWM341_gpio.c + SWM341_usbd.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_gpio.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_usbd.c - SWM341_sdio.c + SWM341_pwm.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sdio.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_pwm.c - SWM341_dma.c + SWM341_usbh.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_dma.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_usbh.c - SWM341_dma2d.c + SWM341_dma.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_dma2d.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_dma.c - SWM341_uart.c + SWM341_can.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_uart.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_can.c @@ -1223,37 +1242,37 @@ - SWM341_sfc.c + SWM341_exti.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sfc.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_exti.c - SWM341_crc.c + SWM341_i2c.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_crc.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_i2c.c - SWM341_pwm.c - 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_pwm.c + startup_SWM341.s + 2 + ..\libraries\SWM341_CSL\CMSIS\DeviceSupport\startup\arm\startup_SWM341.s - SWM341_adc.c + SWM341_wdt.c 1 - ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_adc.c + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_wdt.c - startup_SWM341.s - 2 - ..\libraries\SWM341_CSL\CMSIS\DeviceSupport\startup\arm\startup_SWM341.s + SWM341_sfc.c + 1 + ..\libraries\SWM341_CSL\SWM341_StdPeriph_Driver\SWM341_sfc.c diff --git a/bsp/tae32f5300/drivers/drv_gpio.c b/bsp/tae32f5300/drivers/drv_gpio.c index 3b00d41b86b..e58a71ed252 100644 --- a/bsp/tae32f5300/drivers/drv_gpio.c +++ b/bsp/tae32f5300/drivers/drv_gpio.c @@ -123,16 +123,16 @@ void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin) +rt_ssize_t _pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value; + rt_ssize_t value; const struct pin_index *index; value = PIN_LOW; index = get_pin(pin); if (index == RT_NULL) { - return PIN_LOW; + return -RT_EINVAL; } if (LL_GPIO_ReadPin(index->gpio, index->pin) == GPIO_PIN_RESET) { diff --git a/bsp/tae32f5300/project.uvprojx b/bsp/tae32f5300/project.uvprojx index 9bc763026b2..ec623b47bac 100644 --- a/bsp/tae32f5300/project.uvprojx +++ b/bsp/tae32f5300/project.uvprojx @@ -556,6 +556,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/ti/c28x/libraries/HAL_Drivers/drv_gpio.c b/bsp/ti/c28x/libraries/HAL_Drivers/drv_gpio.c index f3fe1f71f35..598edff1ae0 100644 --- a/bsp/ti/c28x/libraries/HAL_Drivers/drv_gpio.c +++ b/bsp/ti/c28x/libraries/HAL_Drivers/drv_gpio.c @@ -76,10 +76,10 @@ static void c28x_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t c28x_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t c28x_pin_read(rt_device_t dev, rt_base_t pin) { volatile Uint32 *gpioDataReg; - rt_int8_t value = PIN_LOW; + rt_ssize_t value = PIN_LOW; if (PIN_PORT(pin) < PIN_c28x_PORT_MAX) { diff --git a/bsp/tkm32F499/drivers/drv_gpio.c b/bsp/tkm32F499/drivers/drv_gpio.c index fff9cc40df3..4736fbf508d 100644 --- a/bsp/tkm32F499/drivers/drv_gpio.c +++ b/bsp/tkm32F499/drivers/drv_gpio.c @@ -203,16 +203,16 @@ void tkm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -rt_int8_t tkm32_pin_read(rt_device_t dev, rt_base_t pin) +rt_ssize_t tkm32_pin_read(rt_device_t dev, rt_base_t pin) { - rt_int8_t value; + rt_ssize_t value; const struct pin_index *index; value = PIN_LOW; index = get_pin(pin); if (index == RT_NULL) { - return PIN_LOW; + return -RT_EINVAL; } if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) { diff --git a/bsp/tkm32F499/project.uvprojx b/bsp/tkm32F499/project.uvprojx index b9c0a07e047..06a30bae4db 100644 --- a/bsp/tkm32F499/project.uvprojx +++ b/bsp/tkm32F499/project.uvprojx @@ -486,6 +486,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1048,121 +1067,121 @@ TKM32_Lib - HAL_misc.c + HAL_gpio.c 1 - Libraries\Hal_lib\src\HAL_misc.c + Libraries\Hal_lib\src\HAL_gpio.c - HAL_dma_bak.c + HAL_wwdg.c 1 - Libraries\Hal_lib\src\HAL_dma_bak.c + Libraries\Hal_lib\src\HAL_wwdg.c - HAL_tim.c + HAL_i2c.c 1 - Libraries\Hal_lib\src\HAL_tim.c + Libraries\Hal_lib\src\HAL_i2c.c - HAL_pwr.c + HAL_spi.c 1 - Libraries\Hal_lib\src\HAL_pwr.c + Libraries\Hal_lib\src\HAL_spi.c - HAL_i2c.c + HAL_iwdg.c 1 - Libraries\Hal_lib\src\HAL_i2c.c + Libraries\Hal_lib\src\HAL_iwdg.c - startup_Tk499.s - 2 - Libraries\CMSIS_and_startup\startup_Tk499.s + HAL_tim.c + 1 + Libraries\Hal_lib\src\HAL_tim.c - HAL_spi.c - 1 - Libraries\Hal_lib\src\HAL_spi.c + startup_Tk499.s + 2 + Libraries\CMSIS_and_startup\startup_Tk499.s - HAL_exti.c + HAL_misc.c 1 - Libraries\Hal_lib\src\HAL_exti.c + Libraries\Hal_lib\src\HAL_misc.c - HAL_dma.c + HAL_rcc.c 1 - Libraries\Hal_lib\src\HAL_dma.c + Libraries\Hal_lib\src\HAL_rcc.c - HAL_syscfg.c + HAL_can.c 1 - Libraries\Hal_lib\src\HAL_syscfg.c + Libraries\Hal_lib\src\HAL_can.c - sys.c + HAL_dma_bak.c 1 - Libraries\CMSIS_and_startup\sys.c + Libraries\Hal_lib\src\HAL_dma_bak.c - HAL_uart.c + HAL_syscfg.c 1 - Libraries\Hal_lib\src\HAL_uart.c + Libraries\Hal_lib\src\HAL_syscfg.c - HAL_can.c + sys.c 1 - Libraries\Hal_lib\src\HAL_can.c + Libraries\CMSIS_and_startup\sys.c - HAL_wwdg.c + HAL_exti.c 1 - Libraries\Hal_lib\src\HAL_wwdg.c + Libraries\Hal_lib\src\HAL_exti.c - HAL_iwdg.c + HAL_uart.c 1 - Libraries\Hal_lib\src\HAL_iwdg.c + Libraries\Hal_lib\src\HAL_uart.c - HAL_gpio.c + HAL_dma.c 1 - Libraries\Hal_lib\src\HAL_gpio.c + Libraries\Hal_lib\src\HAL_dma.c - HAL_rcc.c + HAL_pwr.c 1 - Libraries\Hal_lib\src\HAL_rcc.c + Libraries\Hal_lib\src\HAL_pwr.c diff --git a/bsp/tm4c123bsp/.config b/bsp/tm4c123bsp/.config index 4b153416ee3..b257a4c07b3 100644 --- a/bsp/tm4c123bsp/.config +++ b/bsp/tm4c123bsp/.config @@ -1089,7 +1089,7 @@ CONFIG_BSP_USING_SPI0=y # CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_USING_SPI2 is not set # CONFIG_BSP_USING_SPI3 is not set -# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_TIM is not set CONFIG_BSP_USING_PWM=y # CONFIG_BSP_USING_PWM0 is not set diff --git a/bsp/tm4c123bsp/board/Kconfig b/bsp/tm4c123bsp/board/Kconfig index 9c93c1a0cc8..b7356b7fade 100644 --- a/bsp/tm4c123bsp/board/Kconfig +++ b/bsp/tm4c123bsp/board/Kconfig @@ -188,21 +188,75 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_I2C1 - bool "Enable I2C1 BUS (software simulation)" + menuconfig BSP_USING_I2C + bool "Enable I2C BUS" default n select RT_USING_I2C - select RT_USING_I2C_BITOPS - select RT_USING_PIN - if BSP_USING_I2C1 - config BSP_I2C1_SCL_PIN - int "i2c1 scl pin number" - range 0 175 - default 22 - config BSP_I2C1_SDA_PIN - int "I2C1 sda pin number" - range 0 175 - default 23 + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0 BUS" + default n + if BSP_USING_I2C0 + choice + prompt "I2C0 CLK frequency" + default BSP_I2C0_CLK_100 + + config BSP_I2C0_CLK_100 + bool "100kHz" + + config BSP_I2C0_CLK_400 + bool "400kHz" + endchoice + endif + + config BSP_USING_I2C1 + bool "Enable I2C1 BUS" + default n + if BSP_USING_I2C1 + choice + prompt "I2C1 CLK frequency" + default BSP_I2C1_CLK_100 + + config BSP_I2C1_CLK_100 + bool "100kHz" + + config BSP_I2C1_CLK_400 + bool "400kHz" + endchoice + endif + + config BSP_USING_I2C2 + bool "Enable I2C2 BUS" + default n + if BSP_USING_I2C2 + choice + prompt "I2C2 CLK frequency" + default BSP_I2C3_CLK_100 + + config BSP_I2C2_CLK_100 + bool "100kHz" + + config BSP_I2C2_CLK_400 + bool "400kHz" + endchoice + endif + + config BSP_USING_I2C3 + bool "Enable I2C3 BUS" + default n + if BSP_USING_I2C3 + choice + prompt "I2C3 CLK frequency" + default BSP_I2C4_CLK_100 + + config BSP_I2C3_CLK_100 + bool "100kHz" + + config BSP_I2C3_CLK_400 + bool "400kHz" + endchoice + endif + endif menuconfig BSP_USING_TIM diff --git a/bsp/tm4c123bsp/board/board.c b/bsp/tm4c123bsp/board/board.c index 4f75212b085..0748f2436bb 100644 --- a/bsp/tm4c123bsp/board/board.c +++ b/bsp/tm4c123bsp/board/board.c @@ -58,6 +58,9 @@ void rt_hw_board_init() #endif #ifdef RT_USING_PWM rt_hw_pwm_init(); +#endif +#ifdef RT_USING_I2C + rt_hw_i2c_init(); #endif /* Call components board initial (use INIT_BOARD_EXPORT()) */ #ifdef RT_USING_COMPONENTS_INIT diff --git a/bsp/tm4c123bsp/board/board.h b/bsp/tm4c123bsp/board/board.h index 0f8c5aff40b..990da9b42a2 100644 --- a/bsp/tm4c123bsp/board/board.h +++ b/bsp/tm4c123bsp/board/board.h @@ -47,6 +47,10 @@ #include "drv_spi.h" #endif /* RT_USING_SPI*/ +#ifdef RT_USING_I2C +#include "drv_i2c.h" +#endif /* RT_USING_I2C*/ + #endif /*__BOARD_H__*/ /************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/board/tm4c123_config.c b/bsp/tm4c123bsp/board/tm4c123_config.c index cc03988adf5..da8b1c1c437 100644 --- a/bsp/tm4c123bsp/board/tm4c123_config.c +++ b/bsp/tm4c123bsp/board/tm4c123_config.c @@ -6,12 +6,14 @@ * Change Logs: * Date Author Notes * 2020-06-27 AHTYDHD the first version + * 2024-04-11 Astrozen add i2c support */ #include #include #include #include "inc/hw_memmap.h" +#include "driverlib/rom.h" #include "driverlib/pin_map.h" #include "driverlib/sysctl.h" #include "driverlib/gpio.h" @@ -29,6 +31,9 @@ #ifdef RT_USING_SPI #include "driverlib/ssi.h" #endif /* RT_USING_SPI */ +#ifdef RT_USING_I2C +#include "driverlib/i2c.h" +#endif /* RT_USING_I2C */ #ifdef RT_USING_SERIAL @@ -85,4 +90,26 @@ void spi_hw_config(void) } #endif /* RT_USING_SPI */ +#ifdef RT_USING_I2C +void i2c_hw_config(void) +{ + /* I2C0 */ + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + + ROM_GPIOPinConfigure(GPIO_PB2_I2C0SCL); + ROM_GPIOPinConfigure(GPIO_PB3_I2C0SDA); + + ROM_GPIOPinTypeI2CSCL(GPIO_PORTB_BASE, GPIO_PIN_2); + ROM_GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_3); + + ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_I2C0); + ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_I2C0); + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C0); + while (!SysCtlPeripheralReady(SYSCTL_PERIPH_I2C0)); + + // timeout:5ms + ROM_I2CMasterTimeoutSet(I2C0_BASE, 0x7d); +} +#endif /* RT_USING_I2C */ + /************************** end of file ******************/ diff --git a/bsp/tm4c123bsp/board/tm4c123_config.h b/bsp/tm4c123bsp/board/tm4c123_config.h index 0153babcfa5..e62134c00e2 100644 --- a/bsp/tm4c123bsp/board/tm4c123_config.h +++ b/bsp/tm4c123bsp/board/tm4c123_config.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2020-06-27 AHTYDHD the first version + * 2024-04-11 Astrozen add i2c support */ #ifndef __TM4C123GH6PZ_CONFIG_H__ @@ -27,6 +28,9 @@ void pwm_hw_config(void); #ifdef RT_USING_SPI void spi_hw_config(void); #endif /* RT_USING_SPI */ +#ifdef RT_USING_I2C +void i2c_hw_config(void); +#endif /* RT_USING_I2C */ #ifdef __cplusplus } diff --git a/bsp/tm4c123bsp/libraries/Drivers/SConscript b/bsp/tm4c123bsp/libraries/Drivers/SConscript index d50fd5cadcb..94e0d77ba12 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/SConscript +++ b/bsp/tm4c123bsp/libraries/Drivers/SConscript @@ -26,9 +26,9 @@ if GetDepend(['RT_USING_SPI']): if GetDepend(['RT_USING_QSPI']): src += ['drv_qspi.c'] -if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): - if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'): - src += ['drv_soft_i2c.c'] +if GetDepend(['RT_USING_I2C']): + if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3'): + src += ['drv_i2c.c'] if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']): src += ['drv_eth.c'] diff --git a/bsp/tm4c123bsp/libraries/Drivers/config/i2c_config.h b/bsp/tm4c123bsp/libraries/Drivers/config/i2c_config.h new file mode 100644 index 00000000000..f89a3c3d8b6 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/config/i2c_config.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-01-20 wirano first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_I2C0_CLK_100) +#define I2C0_CLK 100000 +#elif defined(BSP_I2C0_CLK_400) +#define I2C0_CLK 400000 +#endif + +#if defined(BSP_I2C1_CLK_100) +#define I2C1_CLK 100000 +#elif defined(BSP_I2C1_CLK_400) +#define I2C1_CLK 400000 +#endif + +#if defined(BSP_I2C2_CLK_100) +#define I2C2_CLK 100000 +#elif defined(BSP_I2C2_CLK_400) +#define I2C2_CLK 400000 +#endif + +#if defined(BSP_I2C3_CLK_100) +#define I2C3_CLK 100000 +#elif defined(BSP_I2C3_CLK_400) +#define I2C3_CLK 400000 +#endif + +#ifdef BSP_USING_I2C0 +#ifndef I2C0_BUS_CONFIG +#define I2C0_BUS_CONFIG \ + { \ + .base = I2C0_BASE, \ + .bus_name = "i2c0", \ + .clk_freq = I2C0_CLK, \ + } +#endif /* I2C0_BUS_CONFIG */ +#endif /* BSP_USING_I2C0 */ + +#ifdef BSP_USING_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .base = I2C1_BASE, \ + .bus_name = "i2c1", \ + .clk_freq = I2C1_CLK, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_I2C1 */ + +#ifdef BSP_USING_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .base = I2C2_BASE, \ + .bus_name = "i2c2", \ + .clk_freq = I2C2_CLK, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_I2C2 */ + +#ifdef BSP_USING_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .base = I2C3_BASE, \ + .bus_name = "i2c3", \ + .clk_freq = I2C3_CLK, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_I2C3 */ + +#ifdef __cplusplus +} +#endif + +#endif //__I2C_CONFIG_H__ diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.c b/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.c index b55da5bd406..322d6df14de 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.c +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_gpio.c @@ -110,15 +110,15 @@ static void tm4c123_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t ui8Val) } } -static int tm4c123_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t tm4c123_pin_read(rt_device_t dev, rt_base_t pin) { const struct pin_index *index; - int value = 0; + rt_ssize_t value = 0; index = get_pin(pin); if (index == RT_NULL) { - return value; + return -RT_EINVAL; } value = GPIOPinRead(index ->gpioBaseAddress, index ->pin); diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_i2c.c b/bsp/tm4c123bsp/libraries/Drivers/drv_i2c.c new file mode 100644 index 00000000000..ec355963491 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_i2c.c @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-01-20 wirano first version + */ + + +#include +#include +#include + +#ifdef BSP_USING_I2C + +#if defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) + +#include "drv_i2c.h" +#include "inc/hw_memmap.h" +#include "i2c_config.h" + +enum { +#ifdef BSP_USING_I2C0 + I2C0_INDEX, +#endif +#ifdef BSP_USING_I2C1 + I2C1_INDEX, +#endif +#ifdef BSP_USING_I2C2 + I2C2_INDEX, +#endif +#ifdef BSP_USING_I2C3 + I2C3_INDEX, +#endif +}; + +static struct tm4c123_i2c tm4c123_i2cs[] = + { +#ifdef BSP_USING_I2C0 + I2C0_BUS_CONFIG, +#endif + +#ifdef BSP_USING_I2C1 + I2C1_BUS_CONFIG, +#endif + +#ifdef BSP_USING_I2C2 + I2C2_BUS_CONFIG, +#endif + +#ifdef BSP_USING_I2C3 + I2C3_BUS_CONFIG, +#endif + }; + + +static rt_ssize_t tm4c123_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num); + + +struct rt_i2c_bus_device_ops tm4c123_i2c_ops = + { + tm4c123_i2c_xfer, + RT_NULL, + RT_NULL + }; + + +static rt_ssize_t tm4c123_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) { + RT_ASSERT(bus != RT_NULL); + RT_ASSERT(msgs != RT_NULL); + + struct rt_i2c_msg *msg; + struct tm4c123_i2c *i2c_info = (struct tm4c123_i2c *) bus; + + rt_err_t ret = -RT_ERROR; + rt_uint32_t i; + + for (i = 0; i < num; i++) { + msg = &msgs[i]; + + if (msg->flags & RT_I2C_ADDR_10BIT) { + LOG_E("does not support 10bits address!\n"); + } + + if (msg->flags & RT_I2C_RD) { + rt_uint8_t *data = msg->buf; + + ROM_I2CMasterSlaveAddrSet(i2c_info->base, msg->addr, true); + + if (msg->flags & RT_I2C_NO_START) { + ROM_I2CMasterControl(i2c_info->base, I2C_MASTER_CMD_BURST_RECEIVE_CONT); + while (ROM_I2CMasterBusy(i2c_info->base)); + *data = ROM_I2CMasterDataGet(i2c_info->base); + } else { + ROM_I2CMasterControl(i2c_info->base, I2C_MASTER_CMD_BURST_RECEIVE_START); + while (ROM_I2CMasterBusy(i2c_info->base)); + *data = ROM_I2CMasterDataGet(i2c_info->base); + } + + if (msg->len > 1) { + data++; + + for (int j = 1; j < msg->len - 1; ++j) { + + ROM_I2CMasterControl(i2c_info->base, I2C_MASTER_CMD_BURST_RECEIVE_CONT); + while (ROM_I2CMasterBusy(i2c_info->base)); + *data = ROM_I2CMasterDataGet(i2c_info->base); + data++; + } + + if (msg->flags & RT_I2C_NO_STOP) { + ROM_I2CMasterControl(i2c_info->base, I2C_MASTER_CMD_BURST_RECEIVE_CONT); + while (ROM_I2CMasterBusy(i2c_info->base)); + *data = ROM_I2CMasterDataGet(i2c_info->base); + } else { + ROM_I2CMasterControl(i2c_info->base, I2C_MASTER_CMD_BURST_RECEIVE_FINISH); + while (ROM_I2CMasterBusy(i2c_info->base)); + *data = ROM_I2CMasterDataGet(i2c_info->base); + } + } + } else { + rt_uint8_t *data = msg->buf; + + ROM_I2CMasterSlaveAddrSet(i2c_info->base, msg->addr, false); + + // use single send when data len = 1 + if (msg->len == 1) { + if (msg->flags & RT_I2C_NO_START) { + ROM_I2CMasterDataPut(i2c_info->base, *data); + ROM_I2CMasterControl(i2c_info->base, I2C_MASTER_CMD_BURST_SEND_CONT); + } else if (msg->flags & RT_I2C_NO_STOP) { + ROM_I2CMasterDataPut(i2c_info->base, *data); + ROM_I2CMasterControl(i2c_info->base, I2C_MASTER_CMD_BURST_SEND_CONT); + } else { + ROM_I2CMasterControl(i2c_info->base, I2C_MASTER_CMD_SINGLE_SEND); + ROM_I2CMasterDataPut(i2c_info->base, *data); + } + while (ROM_I2CMasterBusy(i2c_info->base)); + // otherwise use burst send + } else { + if (msg->flags & RT_I2C_NO_START) { + ROM_I2CMasterDataPut(i2c_info->base, *data); + ROM_I2CMasterControl(i2c_info->base, I2C_MASTER_CMD_BURST_SEND_CONT); + while (ROM_I2CMasterBusy(i2c_info->base)); + } else { + ROM_I2CMasterDataPut(i2c_info->base, *data); + ROM_I2CMasterControl(i2c_info->base, I2C_MASTER_CMD_BURST_SEND_START); + while (ROM_I2CMasterBusy(i2c_info->base)); + } + + data++; + + for (int j = 1; j < msg->len - 1; ++j) { + ROM_I2CMasterDataPut(i2c_info->base, *data); + ROM_I2CMasterControl(i2c_info->base, I2C_MASTER_CMD_BURST_SEND_CONT); + while (ROM_I2CMasterBusy(i2c_info->base)); + data++; + } + + if (msg->flags & RT_I2C_NO_STOP) { + ROM_I2CMasterDataPut(i2c_info->base, *data); + ROM_I2CMasterControl(i2c_info->base, I2C_MASTER_CMD_BURST_SEND_CONT); + } else { + ROM_I2CMasterDataPut(i2c_info->base, *data); + ROM_I2CMasterControl(i2c_info->base, I2C_MASTER_CMD_BURST_SEND_FINISH); + } + while (ROM_I2CMasterBusy(i2c_info->base)); + } + + } + } + ret = i; + return ret; +} + +int rt_hw_i2c_init(void) { + rt_err_t ret = RT_EOK; + + i2c_hw_config(); + + for (uint32_t i = 0; i < sizeof(tm4c123_i2cs) / sizeof(tm4c123_i2cs[0]); i++) { + if (tm4c123_i2cs[i].clk_freq == 400000) { + ROM_I2CMasterInitExpClk(tm4c123_i2cs[i].base, ROM_SysCtlClockGet(), RT_TRUE); + } else { + ROM_I2CMasterInitExpClk(tm4c123_i2cs[i].base, ROM_SysCtlClockGet(), RT_FALSE); + } + ROM_I2CMasterEnable(tm4c123_i2cs[i].base); + + tm4c123_i2cs[i].bus.ops = &tm4c123_i2c_ops; + ret = rt_i2c_bus_device_register(&tm4c123_i2cs[i].bus, tm4c123_i2cs[i].bus_name); + if (ret != RT_EOK) { + LOG_E("rt i2c device %s register failed, status=%d\n", tm4c123_i2cs[i].bus_name, ret); + } + } + + return ret; +} + +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif /* BSP_USING_I2C1 || BSP_USING_I2C2 || BSP_USING_I2C3 || BSP_USING_I2C4 */ + +#endif /* BSP_USING_I2C */ + diff --git a/bsp/tm4c123bsp/libraries/Drivers/drv_i2c.h b/bsp/tm4c123bsp/libraries/Drivers/drv_i2c.h new file mode 100644 index 00000000000..3f1883e73c7 --- /dev/null +++ b/bsp/tm4c123bsp/libraries/Drivers/drv_i2c.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-01-20 wirano first version + */ + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + + +#include +#include +#include + + +struct tm4c123_i2c +{ + struct rt_i2c_bus_device bus; + uint32_t base; + char *bus_name; + uint32_t clk_freq; +}; + +int rt_hw_i2c_init(void); + +#endif /* __DRV_I2C_H__ */ + diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript b/bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript index bd6ba1b1cf9..6bd89e4889a 100644 --- a/bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript @@ -20,7 +20,8 @@ tm4c123_driverlib/src/gpio.c if GetDepend(['RT_USING_SERIAL']): src += ['tm4c123_driverlib/src/uart.c'] -#if GetDepend(['RT_USING_I2C']): +if GetDepend(['RT_USING_I2C']): + src += ['tm4c123_driverlib/src/i2c.c'] if GetDepend(['RT_USING_SPI']): diff --git a/bsp/tm4c123bsp/project.ewp b/bsp/tm4c123bsp/project.ewp index 1b52051815a..39c80c08fc5 100644 --- a/bsp/tm4c123bsp/project.ewp +++ b/bsp/tm4c123bsp/project.ewp @@ -2150,6 +2150,9 @@ $PROJ_DIR$\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/tm4c123bsp/project.uvproj b/bsp/tm4c123bsp/project.uvproj index 00974854cdb..16f55812aac 100644 --- a/bsp/tm4c123bsp/project.uvproj +++ b/bsp/tm4c123bsp/project.uvproj @@ -508,6 +508,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/tm4c123bsp/project.uvprojx b/bsp/tm4c123bsp/project.uvprojx index befb7e0bedc..4a60a97285e 100644 --- a/bsp/tm4c123bsp/project.uvprojx +++ b/bsp/tm4c123bsp/project.uvprojx @@ -519,6 +519,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/tm4c129x/project.ewp b/bsp/tm4c129x/project.ewp index 34d79dcb158..2948348de03 100644 --- a/bsp/tm4c129x/project.ewp +++ b/bsp/tm4c129x/project.ewp @@ -2007,6 +2007,9 @@ $PROJ_DIR$\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c @@ -2032,10 +2035,10 @@ Drivers - $PROJ_DIR$\drivers\drv_eth.c + $PROJ_DIR$\drivers\drv_uart.c - $PROJ_DIR$\drivers\drv_uart.c + $PROJ_DIR$\drivers\drv_eth.c @@ -2122,103 +2125,103 @@ Libraries - $PROJ_DIR$\libraries\driverlib\sysexc.c + $PROJ_DIR$\libraries\driverlib\eeprom.c - $PROJ_DIR$\libraries\driverlib\cpu.c + $PROJ_DIR$\libraries\driverlib\can.c - $PROJ_DIR$\libraries\driverlib\mpu.c + $PROJ_DIR$\libraries\driverlib\uart.c - $PROJ_DIR$\libraries\driverlib\emac.c + $PROJ_DIR$\libraries\driverlib\gpio.c - $PROJ_DIR$\libraries\driverlib\hibernate.c + $PROJ_DIR$\libraries\driverlib\des.c - $PROJ_DIR$\libraries\driverlib\tiva_timer.c + $PROJ_DIR$\libraries\driverlib\crc.c - $PROJ_DIR$\libraries\driverlib\can.c + $PROJ_DIR$\libraries\driverlib\flash.c - $PROJ_DIR$\libraries\driverlib\pwm.c + $PROJ_DIR$\libraries\driverlib\hibernate.c - $PROJ_DIR$\libraries\driverlib\usb.c + $PROJ_DIR$\libraries\driverlib\sysexc.c - $PROJ_DIR$\libraries\driverlib\sw_crc.c + $PROJ_DIR$\libraries\driverlib\emac.c - $PROJ_DIR$\libraries\driverlib\des.c + $PROJ_DIR$\libraries\driverlib\watchdog.c - $PROJ_DIR$\libraries\driverlib\shamd5.c + $PROJ_DIR$\libraries\driverlib\ssi.c - $PROJ_DIR$\libraries\driverlib\crc.c + $PROJ_DIR$\libraries\driverlib\epi.c - $PROJ_DIR$\libraries\driverlib\uart.c + $PROJ_DIR$\libraries\driverlib\usb.c - $PROJ_DIR$\libraries\driverlib\flash.c + $PROJ_DIR$\libraries\driverlib\systick.c - $PROJ_DIR$\libraries\driverlib\interrupt.c + $PROJ_DIR$\libraries\driverlib\lcd.c - $PROJ_DIR$\libraries\startup\startup_ewarm.c + $PROJ_DIR$\libraries\driverlib\aes.c - $PROJ_DIR$\libraries\driverlib\gpio.c + $PROJ_DIR$\libraries\driverlib\cpu.c - $PROJ_DIR$\libraries\driverlib\lcd.c + $PROJ_DIR$\libraries\driverlib\comp.c - $PROJ_DIR$\libraries\driverlib\eeprom.c + $PROJ_DIR$\libraries\driverlib\pwm.c - $PROJ_DIR$\libraries\driverlib\systick.c + $PROJ_DIR$\libraries\driverlib\adc.c - $PROJ_DIR$\libraries\driverlib\watchdog.c + $PROJ_DIR$\libraries\driverlib\shamd5.c - $PROJ_DIR$\libraries\driverlib\i2c.c + $PROJ_DIR$\libraries\driverlib\qei.c - $PROJ_DIR$\libraries\driverlib\epi.c + $PROJ_DIR$\libraries\startup\startup_ewarm.c - $PROJ_DIR$\libraries\driverlib\sysctl.c + $PROJ_DIR$\libraries\driverlib\i2c.c - $PROJ_DIR$\libraries\driverlib\fpu.c + $PROJ_DIR$\libraries\driverlib\udma.c - $PROJ_DIR$\libraries\driverlib\qei.c + $PROJ_DIR$\libraries\driverlib\onewire.c - $PROJ_DIR$\libraries\driverlib\aes.c + $PROJ_DIR$\libraries\driverlib\sw_crc.c - $PROJ_DIR$\libraries\driverlib\ssi.c + $PROJ_DIR$\libraries\driverlib\sysctl.c - $PROJ_DIR$\libraries\driverlib\adc.c + $PROJ_DIR$\libraries\driverlib\fpu.c - $PROJ_DIR$\libraries\driverlib\onewire.c + $PROJ_DIR$\libraries\driverlib\tiva_timer.c - $PROJ_DIR$\libraries\driverlib\comp.c + $PROJ_DIR$\libraries\driverlib\mpu.c - $PROJ_DIR$\libraries\driverlib\udma.c + $PROJ_DIR$\libraries\driverlib\interrupt.c diff --git a/bsp/tm4c129x/project.uvproj b/bsp/tm4c129x/project.uvproj index 69a9f8879e6..b345ebe1fef 100644 --- a/bsp/tm4c129x/project.uvproj +++ b/bsp/tm4c129x/project.uvproj @@ -407,16 +407,16 @@ Applications - board.c + application.c 1 - applications\board.c + applications\application.c - application.c + board.c 1 - applications\application.c + applications\board.c @@ -519,6 +519,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1043,37 +1062,37 @@ Libraries - hibernate.c + udma.c 1 - libraries\driverlib\hibernate.c + libraries\driverlib\udma.c - systick.c + aes.c 1 - libraries\driverlib\systick.c + libraries\driverlib\aes.c - tiva_timer.c + mpu.c 1 - libraries\driverlib\tiva_timer.c + libraries\driverlib\mpu.c - onewire.c + watchdog.c 1 - libraries\driverlib\onewire.c + libraries\driverlib\watchdog.c - fpu.c + epi.c 1 - libraries\driverlib\fpu.c + libraries\driverlib\epi.c @@ -1085,9 +1104,9 @@ - watchdog.c + sysexc.c 1 - libraries\driverlib\watchdog.c + libraries\driverlib\sysexc.c @@ -1099,177 +1118,177 @@ - pwm.c + sysctl.c 1 - libraries\driverlib\pwm.c + libraries\driverlib\sysctl.c - des.c + shamd5.c 1 - libraries\driverlib\des.c + libraries\driverlib\shamd5.c - sysctl.c + lcd.c 1 - libraries\driverlib\sysctl.c + libraries\driverlib\lcd.c - epi.c + crc.c 1 - libraries\driverlib\epi.c + libraries\driverlib\crc.c - uart.c + i2c.c 1 - libraries\driverlib\uart.c + libraries\driverlib\i2c.c - usb.c + tiva_timer.c 1 - libraries\driverlib\usb.c + libraries\driverlib\tiva_timer.c - can.c + pwm.c 1 - libraries\driverlib\can.c + libraries\driverlib\pwm.c - udma.c + flash.c 1 - libraries\driverlib\udma.c + libraries\driverlib\flash.c - emac.c + qei.c 1 - libraries\driverlib\emac.c + libraries\driverlib\qei.c - gpio.c + interrupt.c 1 - libraries\driverlib\gpio.c + libraries\driverlib\interrupt.c - interrupt.c + sw_crc.c 1 - libraries\driverlib\interrupt.c + libraries\driverlib\sw_crc.c - crc.c + ssi.c 1 - libraries\driverlib\crc.c + libraries\driverlib\ssi.c - lcd.c + fpu.c 1 - libraries\driverlib\lcd.c + libraries\driverlib\fpu.c - qei.c + gpio.c 1 - libraries\driverlib\qei.c + libraries\driverlib\gpio.c - cpu.c + uart.c 1 - libraries\driverlib\cpu.c + libraries\driverlib\uart.c - sysexc.c + hibernate.c 1 - libraries\driverlib\sysexc.c + libraries\driverlib\hibernate.c - sw_crc.c + comp.c 1 - libraries\driverlib\sw_crc.c + libraries\driverlib\comp.c - shamd5.c + onewire.c 1 - libraries\driverlib\shamd5.c + libraries\driverlib\onewire.c - adc.c + can.c 1 - libraries\driverlib\adc.c + libraries\driverlib\can.c - comp.c + usb.c 1 - libraries\driverlib\comp.c + libraries\driverlib\usb.c - flash.c + adc.c 1 - libraries\driverlib\flash.c + libraries\driverlib\adc.c - ssi.c + des.c 1 - libraries\driverlib\ssi.c + libraries\driverlib\des.c - aes.c + emac.c 1 - libraries\driverlib\aes.c + libraries\driverlib\emac.c - i2c.c + systick.c 1 - libraries\driverlib\i2c.c + libraries\driverlib\systick.c - mpu.c + cpu.c 1 - libraries\driverlib\mpu.c + libraries\driverlib\cpu.c diff --git a/bsp/w60x/.config b/bsp/w60x/.config index df3dbe3f024..b08a4e7b16e 100644 --- a/bsp/w60x/.config +++ b/bsp/w60x/.config @@ -222,6 +222,7 @@ CONFIG_RT_WLAN_SCAN_WAIT_MS=10000 CONFIG_RT_WLAN_CONNECT_WAIT_MS=10000 CONFIG_RT_WLAN_SCAN_SORT=y CONFIG_RT_WLAN_MSH_CMD_ENABLE=y +CONFIG_RT_WLAN_JOIN_SCAN_BY_MGNT=y CONFIG_RT_WLAN_AUTO_CONNECT_ENABLE=y CONFIG_AUTO_CONNECTION_PERIOD_MS=2000 CONFIG_RT_WLAN_CFG_ENABLE=y diff --git a/bsp/w60x/drivers/drv_pin.c b/bsp/w60x/drivers/drv_pin.c index 390127ba632..315647e77f0 100644 --- a/bsp/w60x/drivers/drv_pin.c +++ b/bsp/w60x/drivers/drv_pin.c @@ -58,7 +58,7 @@ static void wm_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t val return; } -static rt_int8_t wm_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t wm_pin_read(struct rt_device *device, rt_base_t pin) { rt_int16_t gpio_pin; gpio_pin = wm_get_pin(pin); diff --git a/bsp/w60x/project.ewp b/bsp/w60x/project.ewp index 2e516e6e8cc..def18b8757f 100644 --- a/bsp/w60x/project.ewp +++ b/bsp/w60x/project.ewp @@ -221,7 +221,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT __RTTHREAD__ WM_W600 __inline=inline @@ -1298,7 +1297,6 @@ RT_USING_LIBC _DLIB_ADD_EXTRA_SYMBOLS=0 _DLIB_FILE_DESCRIPTOR - _DLIB_THREAD_SUPPORT __RTTHREAD__ WM_W600 __inline=inline @@ -2246,6 +2244,9 @@ $PROJ_DIR$\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c diff --git a/bsp/w60x/project.uvprojx b/bsp/w60x/project.uvprojx index beae3fb2de0..30f2903494e 100644 --- a/bsp/w60x/project.uvprojx +++ b/bsp/w60x/project.uvprojx @@ -675,6 +675,25 @@ + + + condvar.c + 1 + ..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -2223,16 +2242,16 @@ Utilities - ulog.c + console_be.c 1 - ..\..\components\utilities\ulog\ulog.c + ..\..\components\utilities\ulog\backend\console_be.c - console_be.c + ulog.c 1 - ..\..\components\utilities\ulog\backend\console_be.c + ..\..\components\utilities\ulog\ulog.c diff --git a/bsp/w60x/rtconfig.h b/bsp/w60x/rtconfig.h index 329f57afb8d..23e3c1c0fdd 100644 --- a/bsp/w60x/rtconfig.h +++ b/bsp/w60x/rtconfig.h @@ -128,6 +128,7 @@ #define RT_WLAN_CONNECT_WAIT_MS 10000 #define RT_WLAN_SCAN_SORT #define RT_WLAN_MSH_CMD_ENABLE +#define RT_WLAN_JOIN_SCAN_BY_MGNT #define RT_WLAN_AUTO_CONNECT_ENABLE #define AUTO_CONNECTION_PERIOD_MS 2000 #define RT_WLAN_CFG_ENABLE diff --git a/bsp/wch/arm/Libraries/ch32_drivers/drv_gpio_ch32f10x.c b/bsp/wch/arm/Libraries/ch32_drivers/drv_gpio_ch32f10x.c index 576ae11333b..b8bba7f8a07 100644 --- a/bsp/wch/arm/Libraries/ch32_drivers/drv_gpio_ch32f10x.c +++ b/bsp/wch/arm/Libraries/ch32_drivers/drv_gpio_ch32f10x.c @@ -323,7 +323,7 @@ void ch32f1_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) GPIO_WriteBit(item->gpio, item->gpio_pin, (BitAction)value); } -rt_int8_t ch32f1_pin_read(rt_device_t dev, rt_base_t pin) +rt_ssize_t ch32f1_pin_read(rt_device_t dev, rt_base_t pin) { const struct pin_info *item; diff --git a/bsp/wch/arm/Libraries/ch32_drivers/drv_gpio_ch32f20x.c b/bsp/wch/arm/Libraries/ch32_drivers/drv_gpio_ch32f20x.c index 51d59c1e1b4..a733053a68a 100644 --- a/bsp/wch/arm/Libraries/ch32_drivers/drv_gpio_ch32f20x.c +++ b/bsp/wch/arm/Libraries/ch32_drivers/drv_gpio_ch32f20x.c @@ -354,7 +354,7 @@ void ch32f2_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) GPIO_WriteBit(item->gpio, item->gpio_pin, (BitAction)value); } -rt_int8_t ch32f2_pin_read(rt_device_t dev, rt_base_t pin) +rt_ssize_t ch32f2_pin_read(rt_device_t dev, rt_base_t pin) { const struct pin_info *item; diff --git a/bsp/wch/arm/ch32f103c8-core/project.uvprojx b/bsp/wch/arm/ch32f103c8-core/project.uvprojx index c3e16bab59b..7ed3754fab1 100644 --- a/bsp/wch/arm/ch32f103c8-core/project.uvprojx +++ b/bsp/wch/arm/ch32f103c8-core/project.uvprojx @@ -666,6 +666,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/wch/arm/ch32f203r-evt/project.uvprojx b/bsp/wch/arm/ch32f203r-evt/project.uvprojx index 952e50b89ce..6ba8cbd1e62 100644 --- a/bsp/wch/arm/ch32f203r-evt/project.uvprojx +++ b/bsp/wch/arm/ch32f203r-evt/project.uvprojx @@ -711,6 +711,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c diff --git a/bsp/wch/arm/ch579m/project.uvprojx b/bsp/wch/arm/ch579m/project.uvprojx index 7b3baa58b15..7d41648472e 100644 --- a/bsp/wch/arm/ch579m/project.uvprojx +++ b/bsp/wch/arm/ch579m/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -630,23 +649,23 @@ - drv_uart.c + drv_eth.c 1 - board\drv_uart.c + board\drv_eth.c - board.c + drv_uart.c 1 - board\board.c + board\drv_uart.c - drv_eth.c + board.c 1 - board\drv_eth.c + board\board.c @@ -985,58 +1004,51 @@ Libraries - CH57x_spi1.c - 1 - libraries\StdPeriphDriver\CH57x_spi1.c + startup_ARMCM0.s + 2 + libraries\Startup\startup_ARMCM0.s - CH57x_timer0.c + CH57x_spi0.c 1 - libraries\StdPeriphDriver\CH57x_timer0.c + libraries\StdPeriphDriver\CH57x_spi0.c - CH57x_uart2.c + CH57x_timer2.c 1 - libraries\StdPeriphDriver\CH57x_uart2.c - - - - - startup_ARMCM0.s - 2 - libraries\Startup\startup_ARMCM0.s + libraries\StdPeriphDriver\CH57x_timer2.c - CH57x_adc.c + CH57x_gpio.c 1 - libraries\StdPeriphDriver\CH57x_adc.c + libraries\StdPeriphDriver\CH57x_gpio.c - CH57x_uart3.c + CH57x_sys.c 1 - libraries\StdPeriphDriver\CH57x_uart3.c + libraries\StdPeriphDriver\CH57x_sys.c - CH57x_clk.c + CH57x_pwr.c 1 - libraries\StdPeriphDriver\CH57x_clk.c + libraries\StdPeriphDriver\CH57x_pwr.c - CH57x_timer1.c + CH57x_adc.c 1 - libraries\StdPeriphDriver\CH57x_timer1.c + libraries\StdPeriphDriver\CH57x_adc.c @@ -1048,16 +1060,16 @@ - CH57x_timer3.c + CH57x_timer0.c 1 - libraries\StdPeriphDriver\CH57x_timer3.c + libraries\StdPeriphDriver\CH57x_timer0.c - CH57x_gpio.c + CH57x_spi1.c 1 - libraries\StdPeriphDriver\CH57x_gpio.c + libraries\StdPeriphDriver\CH57x_spi1.c @@ -1069,58 +1081,65 @@ - CH57x_spi0.c + CH57x_int.c 1 - libraries\StdPeriphDriver\CH57x_spi0.c + libraries\StdPeriphDriver\CH57x_int.c - CH57x_timer2.c + CH57x_uart3.c 1 - libraries\StdPeriphDriver\CH57x_timer2.c + libraries\StdPeriphDriver\CH57x_uart3.c - CH57x_sys.c + CH57x_clk.c 1 - libraries\StdPeriphDriver\CH57x_sys.c + libraries\StdPeriphDriver\CH57x_clk.c - CH57x_lcd.c + CH57x_uart0.c 1 - libraries\StdPeriphDriver\CH57x_lcd.c + libraries\StdPeriphDriver\CH57x_uart0.c - CH57x_uart0.c + CH57x_uart2.c 1 - libraries\StdPeriphDriver\CH57x_uart0.c + libraries\StdPeriphDriver\CH57x_uart2.c - CH57x_int.c + CH57x_lcd.c 1 - libraries\StdPeriphDriver\CH57x_int.c + libraries\StdPeriphDriver\CH57x_lcd.c - CH57x_uart1.c + CH57x_timer1.c 1 - libraries\StdPeriphDriver\CH57x_uart1.c + libraries\StdPeriphDriver\CH57x_timer1.c - CH57x_pwr.c + CH57x_timer3.c 1 - libraries\StdPeriphDriver\CH57x_pwr.c + libraries\StdPeriphDriver\CH57x_timer3.c + + + + + CH57x_uart1.c + 1 + libraries\StdPeriphDriver\CH57x_uart1.c @@ -1449,16 +1468,16 @@ SAL - netdev_ipaddr.c + netdev.c 1 - ..\..\..\..\components\net\netdev\src\netdev_ipaddr.c + ..\..\..\..\components\net\netdev\src\netdev.c - netdev.c + netdev_ipaddr.c 1 - ..\..\..\..\components\net\netdev\src\netdev.c + ..\..\..\..\components\net\netdev\src\netdev_ipaddr.c diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript b/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript index b17b832dd0f..03d2b777325 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript @@ -18,6 +18,9 @@ if GetDepend('SOC_RISCV_FAMILY_CH32'): if GetDepend('BSP_USING_DAC'): src += ['drv_dac.c'] + if GetDepend('BSP_USING_I2C'): + src += ['drv_i2c.c'] + if GetDepend('BSP_USING_SOFT_I2C'): src += ['drv_soft_i2c.c'] diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c index a03d0f563dd..00a1ead30fe 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c @@ -143,11 +143,11 @@ static void ch32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t ch32_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t ch32_pin_read(rt_device_t dev, rt_base_t pin) { GPIO_TypeDef *gpio_port; rt_uint16_t gpio_pin; - rt_int8_t value = PIN_LOW; + rt_ssize_t value = PIN_LOW; if (PIN_PORT(pin) < PIN_STPORT_MAX) { @@ -155,6 +155,10 @@ static rt_int8_t ch32_pin_read(rt_device_t dev, rt_base_t pin) gpio_pin = PIN_STPIN(pin); value = GPIO_ReadInputDataBit(gpio_port, gpio_pin); } + else + { + return -RT_EINVAL; + } return value; } diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_i2c.c b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_i2c.c new file mode 100644 index 00000000000..7d6f58a92d8 --- /dev/null +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_i2c.c @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-4-1 IceBear003 the first version + */ + +#include "board.h" +#include "drv_i2c.h" + +#ifdef BSP_USING_HWI2C + +#define LOG_TAG "drv.hwi2c" +#include "drv_log.h" + +#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) +#error "Please define at least one BSP_USING_I2Cx" +/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +#define TIMEOUT 0xFF + +#ifdef BSP_USING_I2C1 +struct i2c_bus_device i2c_bus1; +#endif +#ifdef BSP_USING_I2C2 +struct i2c_bus_device i2c_bus2; +#endif + +static int i2c_read(I2C_TypeDef *i2c_periph, + rt_uint16_t addr, + rt_uint8_t flags, + rt_uint16_t len, + rt_uint8_t *buf) +{ + rt_uint16_t try = 0; + while (I2C_GetFlagStatus(i2c_periph, I2C_FLAG_BUSY)) + if (try++ >= TIMEOUT) return -1; + + I2C_GenerateSTART(i2c_periph, ENABLE); + + try = 0; + while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_MODE_SELECT)) //EVT5 + if (try++ >= TIMEOUT) return -1; + + if(flags & RT_I2C_ADDR_10BIT) //10-bit address mode + { + rt_uint8_t frame_head = 0xF0 + (addr >> 8) << 1; //11110XX0 + I2C_SendData(i2c_periph, frame_head); //FrameHead + + try = 0; + while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_MODE_ADDRESS10)) //EVT9 + if (try++ >= TIMEOUT) return -1; + + I2C_SendData(i2c_periph,0xff & addr); + + try = 0; + while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) //EVT6 + if (try++ >= TIMEOUT) return -1; + + I2C_GenerateSTART(i2c_periph, ENABLE); //Sr + + try = 0; + while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_MODE_SELECT)) //EVT5 + if (try++ >= TIMEOUT) return -1; + + I2C_SendData(i2c_periph,frame_head); //Resend FrameHead + } + else + { + I2C_Send7bitAddress(i2c_periph, addr << 1, I2C_Direction_Receiver); + } + + try = 0; + while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) //EVT6 + if (try++ >= TIMEOUT) return -1; + + while(len-- > 0) + { + + try = 0; + while (!I2C_GetFlagStatus(i2c_periph, I2C_FLAG_RXNE)) //Got ACK For the Last Byte + if (try++ >= TIMEOUT) return -1; + + *(buf++)=I2C_ReceiveData(i2c_periph); + } + + I2C_GenerateSTOP(i2c_periph, ENABLE); +} + +static int i2c_write(I2C_TypeDef *i2c_periph, + rt_uint16_t addr, + rt_uint8_t flags, + rt_uint8_t *buf, + rt_uint16_t len) +{ + rt_uint16_t try = 0; + while (I2C_GetFlagStatus(i2c_periph, I2C_FLAG_BUSY)) + if (try++ >= TIMEOUT) return -1; + + I2C_GenerateSTART(i2c_periph, ENABLE); + + try = 0; + while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_MODE_SELECT)) //EVT5 + if (try++ >= TIMEOUT) return -1; + + if(flags & RT_I2C_ADDR_10BIT) //10-bit address mode + { + I2C_SendData(i2c_periph,0xF0 + (addr >> 8) << 1); //FrameHead 11110XX0 + + try = 0; + while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_MODE_ADDRESS10)) //EVT9 + if (try++ >= TIMEOUT) return -1; + + I2C_SendData(i2c_periph,0xff & addr); + } + else //7-bit address mode + { + I2C_Send7bitAddress(i2c_periph, addr << 1, I2C_Direction_Transmitter); + } + + try = 0; + while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) //EVT6 + if (try++ >= TIMEOUT) return -1; + + //Missing Evt8_1 (No definition) + + while(len-- > 0) + { + try = 0; + while (!I2C_GetFlagStatus(i2c_periph, I2C_FLAG_TXE)) //Got ACK For the Last Byte + if (try++ >= TIMEOUT) return -1; + + I2C_SendData(i2c_periph,*(buf++)); + } + + try = 0; + while(!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_BYTE_TRANSMITTING)) //Last byte sent successfully + if (try++ >= TIMEOUT) return -1; + + I2C_GenerateSTOP(i2c_periph, ENABLE); +} + +rt_size_t i2c_master_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + struct rt_i2c_msg *msg; + struct i2c_bus_device *i2c_bus_dev; + rt_uint32_t index; + + i2c_bus_dev = (struct i2c_bus_device *)bus; + + for (index = 0; index < num; index++) + { + msg = &msgs[index]; + if (msg->flags & RT_I2C_RD) + { + i2c_read(i2c_bus_dev->periph, + msg->addr, + msg->flags, + msg->len, + msg->buf); + } + else + { + i2c_write(i2c_bus_dev->periph, + msg->addr, + msg->flags, + msg->buf, + msg->len); + } + } + + return index; +} + +static const struct rt_i2c_bus_device_ops ch32_i2c_ops = +{ + .master_xfer = i2c_master_xfer, + .slave_xfer = RT_NULL, //Not Used in i2c_core? + .i2c_bus_control = RT_NULL +}; + +int rt_hw_i2c_init(struct i2c_config *config = &{5000, I2C_DutyCycle_2, 0, I2C_Ack_Disable, I2C_AcknowledgedAddress_7bit}) +{ + int result = RT_EOK; + + GPIO_InitTypeDef GPIO_InitStructure = {0}; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; + + I2C_InitTypeDef I2C_InitTSturcture = {0}; + I2C_StructInit(&I2C_InitTSturcture); + I2C_InitTSturcture.I2C_ClockSpeed = config->clock_speed; + I2C_InitTSturcture.I2C_DutyCycle = config->duty_cycle; + I2C_InitTSturcture.I2C_OwnAddress1 = config->own_address; + I2C_InitTSturcture.I2C_Ack = config->enable_ack ? I2C_Ack_Enable : I2C_Ack_Disable; + I2C_InitTSturcture.I2C_AcknowledgedAddress = config->is_7_bit_address ? I2C_AcknowledgedAddress_7bit : I2C_AcknowledgedAddress_10bit; + + +#ifdef BSP_USING_I2C1 + + i2c_bus1.periph = I2C1; + + //Clock & IO Initialization + RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + GPIO_PinRemapConfig(GPIO_Remap_I2C1, ENABLE); + + //I2C Initialization Config + I2C_Init(I2C1, &I2C_InitTSturcture); + I2C_Cmd(I2C1, ENABLE); + + //Hook to RT-Thread + i2c_bus1.parent.ops = &ch32_i2c_ops; + result += rt_i2c_bus_device_register(&i2c_bus1.parent, "i2c1"); + +#endif + +#ifdef BSP_USING_I2C2 + + i2c_bus2.periph = I2C2; + + //Clock & IO Initialization + RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + //I2C Initialization Config + I2C_Init(I2C2, &I2C_InitTSturcture); + I2C_Cmd(I2C2, ENABLE); + + //Hook to RT-Thread + i2c_bus2.parent.ops = &ch32_i2c_ops; + result += rt_i2c_bus_device_register(&i2c_bus2.parent, "i2c2"); + +#endif + + return result; +} + +#endif //BSP_USING_HWI2C \ No newline at end of file diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_i2c.h b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_i2c.h new file mode 100644 index 00000000000..31c314c6009 --- /dev/null +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_i2c.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-4-1 IceBear003 the first version + */ + +#ifndef __DRV_I2C_H_ +#define __DRV_I2C_H_ + +#include +#include + +struct i2c_bus_device +{ + struct rt_i2c_bus_device parent; + I2C_TypeDef *periph; +}; + +struct i2c_config +{ + rt_uint32_t clock_speed; + uint16_t duty_cycle; + uint16_t own_address; + uint8_t enable_ack; + uint8_t is_7_bit_address; +}; + +struct i2c_config i2c_default_conf={5000, I2C_Mode_I2C, I2C_DutyCycle_2, 0, I2C_Ack_Disable, I2C_AcknowledgedAddress_7bit}; + +int rt_hw_i2c_init(struct i2c_config *config); + +#endif \ No newline at end of file diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_soft_spi.c b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_soft_spi.c index eb123a46863..4b1a6301f02 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_soft_spi.c +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_soft_spi.c @@ -26,6 +26,8 @@ static struct ch32_soft_spi_config soft_spi_config[] = #endif }; +static struct ch32_soft_spi spi_obj[sizeof(soft_spi_config) / sizeof(soft_spi_config[0])]; + /** * Attach the spi device to soft SPI bus, this function must be used after initialization. */ @@ -187,9 +189,20 @@ static void ch32_udelay(rt_uint32_t us) } } +static void ch32_pin_init(void) +{ + rt_size_t obj_num = sizeof(spi_obj) / sizeof(struct ch32_soft_spi); + + for(rt_size_t i; i < obj_num; i++) + { + ch32_spi_gpio_init(&spi_obj[i]); + } +} + static struct rt_spi_bit_ops ch32_soft_spi_ops = { .data = RT_NULL, + .pin_init = ch32_pin_init, .tog_sclk = ch32_tog_sclk, .set_sclk = ch32_set_sclk, .set_mosi = ch32_set_mosi, @@ -203,20 +216,17 @@ static struct rt_spi_bit_ops ch32_soft_spi_ops = .delay_us = 1, }; -static struct ch32_soft_spi spi_obj[sizeof(soft_spi_config) / sizeof(soft_spi_config[0])]; - /* Soft SPI initialization function */ int rt_soft_spi_init(void) { rt_size_t obj_num = sizeof(spi_obj) / sizeof(struct ch32_soft_spi); rt_err_t result; - for (int i = 0; i < obj_num; i++) + for (rt_size_t i = 0; i < obj_num; i++) { ch32_soft_spi_ops.data = (void *)&soft_spi_config[i]; spi_obj[i].spi.ops = &ch32_soft_spi_ops; spi_obj[i].cfg = (void *)&soft_spi_config[i]; - ch32_spi_gpio_init(&spi_obj[i]); result = rt_spi_bit_add_bus(&spi_obj[i].spi, soft_spi_config[i].bus_name, &ch32_soft_spi_ops); RT_ASSERT(result == RT_EOK); } diff --git a/bsp/wch/risc-v/Libraries/ch56x_drivers/ch56x_gpio.c b/bsp/wch/risc-v/Libraries/ch56x_drivers/ch56x_gpio.c index 8cc42421e01..72477c4a12a 100644 --- a/bsp/wch/risc-v/Libraries/ch56x_drivers/ch56x_gpio.c +++ b/bsp/wch/risc-v/Libraries/ch56x_drivers/ch56x_gpio.c @@ -149,7 +149,7 @@ static void gpio_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t v BITS_SET(px->OUT, bitpos); } -static rt_int8_t gpio_pin_read(struct rt_device *device, rt_base_t pin) +static rt_ssize_t gpio_pin_read(struct rt_device *device, rt_base_t pin) { volatile struct gpio_px_regs *px; diff --git a/bsp/wch/risc-v/ch32v208w-r0/applications/arduino_pinout/Sconscript b/bsp/wch/risc-v/ch32v208w-r0/applications/arduino_pinout/Sconscript index 25399290275..da85e053c37 100644 --- a/bsp/wch/risc-v/ch32v208w-r0/applications/arduino_pinout/Sconscript +++ b/bsp/wch/risc-v/ch32v208w-r0/applications/arduino_pinout/Sconscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/wch/risc-v/ch32v307v-r1/.config b/bsp/wch/risc-v/ch32v307v-r1/.config index 060fc9bc4c7..9f6858686a4 100644 --- a/bsp/wch/risc-v/ch32v307v-r1/.config +++ b/bsp/wch/risc-v/ch32v307v-r1/.config @@ -1077,6 +1077,7 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_UART8 is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_SOFT_I2C is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_SOFT_SPI is not set diff --git a/bsp/wch/risc-v/ch32v307v-r1/.cproject b/bsp/wch/risc-v/ch32v307v-r1/.cproject new file mode 100644 index 00000000000..6cb396cddec --- /dev/null +++ b/bsp/wch/risc-v/ch32v307v-r1/.cproject @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/wch/risc-v/ch32v307v-r1/.project b/bsp/wch/risc-v/ch32v307v-r1/.project new file mode 100644 index 00000000000..2fca752ff54 --- /dev/null +++ b/bsp/wch/risc-v/ch32v307v-r1/.project @@ -0,0 +1,28 @@ + + + project + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.rt-thread.studio.rttnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + diff --git a/bsp/wch/risc-v/ch32v307v-r1/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs b/bsp/wch/risc-v/ch32v307v-r1/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs new file mode 100644 index 00000000000..11a25ce798a --- /dev/null +++ b/bsp/wch/risc-v/ch32v307v-r1/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +toolchain.path.1287942917=${toolchain_install_path}\\WCH\\RISC-V-GCC-WCH\\8.2.0\\bin diff --git a/bsp/wch/risc-v/ch32v307v-r1/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs b/bsp/wch/risc-v/ch32v307v-r1/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs new file mode 100644 index 00000000000..d6dfeb70783 --- /dev/null +++ b/bsp/wch/risc-v/ch32v307v-r1/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +toolchain.path.512258282=${toolchain_install_path}/WCH/RISC-V-GCC-WCH/8.2.0/bin diff --git a/bsp/wch/risc-v/ch32v307v-r1/.settings/language.settings.xml b/bsp/wch/risc-v/ch32v307v-r1/.settings/language.settings.xml new file mode 100644 index 00000000000..79bf5a4bf07 --- /dev/null +++ b/bsp/wch/risc-v/ch32v307v-r1/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/bsp/wch/risc-v/ch32v307v-r1/.settings/local_temp_storage.prefs b/bsp/wch/risc-v/ch32v307v-r1/.settings/local_temp_storage.prefs new file mode 100644 index 00000000000..f126d697337 --- /dev/null +++ b/bsp/wch/risc-v/ch32v307v-r1/.settings/local_temp_storage.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +temp.toolchain.exec.path=D\:\\Apps\\RT-ThreadStudio\\repo\\Extract\\ToolChain_Support_Packages\\WCH\\RISC-V-GCC-WCH\\8.2.0/bin diff --git a/bsp/wch/risc-v/ch32v307v-r1/.settings/org.eclipse.core.runtime.prefs b/bsp/wch/risc-v/ch32v307v-r1/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 00000000000..9f1acfcfba2 --- /dev/null +++ b/bsp/wch/risc-v/ch32v307v-r1/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.asmSource/file-extensions=s +eclipse.preferences.version=1 \ No newline at end of file diff --git a/bsp/wch/risc-v/ch32v307v-r1/.settings/projcfg.ini b/bsp/wch/risc-v/ch32v307v-r1/.settings/projcfg.ini new file mode 100644 index 00000000000..a5fbfb2fbf5 --- /dev/null +++ b/bsp/wch/risc-v/ch32v307v-r1/.settings/projcfg.ini @@ -0,0 +1,19 @@ +#RT-Thread Studio Project Configuration +#Tue Mar 26 11:25:30 CST 2024 +cfg_version=v3.0 +board_name= +example_name= +hardware_adapter= +project_type=rt-thread +board_base_nano_proj=false +chip_name= +selected_rtt_version=latest +bsp_version= +os_branch=master +project_base_rtt_bsp=true +output_project_path=D\:\\Apps\\RT-ThreadStudio\\workspace +is_base_example_project=false +is_use_scons_build=true +project_name=project +os_version=latest +bsp_path= diff --git a/bsp/wch/risc-v/ch32v307v-r1/applications/arduino_pinout/Sconscript b/bsp/wch/risc-v/ch32v307v-r1/applications/arduino_pinout/Sconscript index 25399290275..da85e053c37 100644 --- a/bsp/wch/risc-v/ch32v307v-r1/applications/arduino_pinout/Sconscript +++ b/bsp/wch/risc-v/ch32v307v-r1/applications/arduino_pinout/Sconscript @@ -4,6 +4,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') inc = [cwd] -group = DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) +group = DefineGroup('RTduino-pinout', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc) Return('group') diff --git a/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig b/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig index 7a24302d4c7..19e9199239b 100644 --- a/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig +++ b/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig @@ -121,6 +121,21 @@ menu "On-chip Peripheral Drivers" default n endif + menuconfig BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + + if BSP_USING_I2C + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + + endif + menuconfig BSP_USING_SOFT_I2C bool "Enable I2C Bus" select RT_USING_I2C diff --git a/bsp/wch/risc-v/ch32v307v-r1/rtconfig_preinc.h b/bsp/wch/risc-v/ch32v307v-r1/rtconfig_preinc.h new file mode 100644 index 00000000000..41ac7cc49d7 --- /dev/null +++ b/bsp/wch/risc-v/ch32v307v-r1/rtconfig_preinc.h @@ -0,0 +1,10 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/xplorer4330/M0/project.uvproj b/bsp/xplorer4330/M0/project.uvproj index 5682c31fa7e..2a49eddcef0 100644 --- a/bsp/xplorer4330/M0/project.uvproj +++ b/bsp/xplorer4330/M0/project.uvproj @@ -390,16 +390,16 @@ Applications - startup.c + application.c 1 - ..\applications\startup.c + ..\applications\application.c - application.c + startup.c 1 - ..\applications\application.c + ..\applications\startup.c @@ -519,6 +519,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -657,16 +676,16 @@ Drivers - drv_uart.c + board.c 1 - ..\drivers\drv_uart.c + ..\drivers\board.c - board.c + drv_uart.c 1 - ..\drivers\board.c + ..\drivers\drv_uart.c diff --git a/bsp/xplorer4330/M4/project.uvproj b/bsp/xplorer4330/M4/project.uvproj index 01942cbe959..8b52625e372 100644 --- a/bsp/xplorer4330/M4/project.uvproj +++ b/bsp/xplorer4330/M4/project.uvproj @@ -390,16 +390,16 @@ Applications - startup.c + application.c 1 - ..\applications\startup.c + ..\applications\application.c - application.c + startup.c 1 - ..\applications\application.c + ..\applications\startup.c @@ -519,6 +519,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -676,16 +695,16 @@ Drivers - drv_led.c + drv_uart.c 1 - ..\drivers\drv_led.c + ..\drivers\drv_uart.c - drv_uart.c + drv_led.c 1 - ..\drivers\drv_uart.c + ..\drivers\drv_led.c diff --git a/bsp/yichip/yc3121-pos/drivers/drv_gpio.c b/bsp/yichip/yc3121-pos/drivers/drv_gpio.c index 5cd0345f162..cd9418d1f39 100644 --- a/bsp/yichip/yc3121-pos/drivers/drv_gpio.c +++ b/bsp/yichip/yc3121-pos/drivers/drv_gpio.c @@ -122,7 +122,7 @@ static void yc_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t yc_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t yc_pin_read(rt_device_t dev, rt_base_t pin) { return GPIO_IN(pin / 16) & (1 << (pin % 16)) ? 1 : 0; } diff --git a/bsp/yichip/yc3121-pos/project.ewp b/bsp/yichip/yc3121-pos/project.ewp index 1170a305ddf..efbc6f330e7 100644 --- a/bsp/yichip/yc3121-pos/project.ewp +++ b/bsp/yichip/yc3121-pos/project.ewp @@ -2140,6 +2140,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c @@ -2261,28 +2264,28 @@ Libraries - $PROJ_DIR$\Libraries\core\misc.c + $PROJ_DIR$\Libraries\sdk\yc_gpio.c - $PROJ_DIR$\Libraries\core\system.c + $PROJ_DIR$\Libraries\core\misc.c - $PROJ_DIR$\Libraries\startup\flash_start_iar.s + $PROJ_DIR$\Libraries\sdk\yc_dma.c - $PROJ_DIR$\Libraries\sdk\yc_systick.c + $PROJ_DIR$\Libraries\startup\flash_start_iar.s - $PROJ_DIR$\Libraries\sdk\yc_dma.c + $PROJ_DIR$\Libraries\core\system.c $PROJ_DIR$\Libraries\sdk\yc_uart.c - $PROJ_DIR$\Libraries\sdk\yc_gpio.c + $PROJ_DIR$\Libraries\sdk\yc_wdt.c - $PROJ_DIR$\Libraries\sdk\yc_wdt.c + $PROJ_DIR$\Libraries\sdk\yc_systick.c diff --git a/bsp/yichip/yc3121-pos/project.uvprojx b/bsp/yichip/yc3121-pos/project.uvprojx index 81bc3d0d26a..16b38e66da2 100644 --- a/bsp/yichip/yc3121-pos/project.uvprojx +++ b/bsp/yichip/yc3121-pos/project.uvprojx @@ -484,6 +484,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1032,13 +1051,6 @@ Libraries - - - yc_gpio.c - 1 - Libraries\sdk\yc_gpio.c - - startup.s @@ -1048,16 +1060,16 @@ - yc_wdt.c + yc_systick.c 1 - Libraries\sdk\yc_wdt.c + Libraries\sdk\yc_systick.c - flash_start.s - 2 - Libraries\startup\flash_start.s + yc_dma.c + 1 + Libraries\sdk\yc_dma.c @@ -1067,6 +1079,13 @@ Libraries\sdk\yc_uart.c + + + flash_start.s + 2 + Libraries\startup\flash_start.s + + system.c @@ -1076,16 +1095,16 @@ - yc_dma.c + yc_wdt.c 1 - Libraries\sdk\yc_dma.c + Libraries\sdk\yc_wdt.c - yc_systick.c + yc_gpio.c 1 - Libraries\sdk\yc_systick.c + Libraries\sdk\yc_gpio.c diff --git a/bsp/yichip/yc3122-pos/drivers/drv_gpio.c b/bsp/yichip/yc3122-pos/drivers/drv_gpio.c index 6fe1047a2e4..2c464a3d66f 100644 --- a/bsp/yichip/yc3122-pos/drivers/drv_gpio.c +++ b/bsp/yichip/yc3122-pos/drivers/drv_gpio.c @@ -122,7 +122,7 @@ static void yc_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) } } -static rt_int8_t yc_pin_read(rt_device_t dev, rt_base_t pin) +static rt_ssize_t yc_pin_read(rt_device_t dev, rt_base_t pin) { //return GPIO_IN(pin / 16) & (1 << (pin % 16)) ? 1 : 0; return GPIO_ReadInputDataBit((GPIO_TypeDef)(pin / 16), (GPIO_Pin_TypeDef)(1 << (pin % 16))); diff --git a/bsp/yichip/yc3122-pos/project.ewp b/bsp/yichip/yc3122-pos/project.ewp index 83986168727..a8e364ac585 100644 --- a/bsp/yichip/yc3122-pos/project.ewp +++ b/bsp/yichip/yc3122-pos/project.ewp @@ -2152,6 +2152,9 @@ $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c @@ -2291,25 +2294,25 @@ Libraries - $PROJ_DIR$\Libraries\CMSIS\Device\YICHIP\YC3122\Source\Templates\system_yc3122.c + $PROJ_DIR$\Libraries\core\system.c - $PROJ_DIR$\Libraries\sdk\yc_uart.c + $PROJ_DIR$\Libraries\sdk\yc_gpio.c - $PROJ_DIR$\Libraries\CMSIS\Device\YICHIP\YC3122\Source\Templates\iar\startup_yc3122.s + $PROJ_DIR$\Libraries\sdk\yc_exti.c - $PROJ_DIR$\Libraries\sdk\yc_gpio.c + $PROJ_DIR$\Libraries\sdk\yc_wdt.c - $PROJ_DIR$\Libraries\core\system.c + $PROJ_DIR$\Libraries\CMSIS\Device\YICHIP\YC3122\Source\Templates\system_yc3122.c - $PROJ_DIR$\Libraries\sdk\yc_wdt.c + $PROJ_DIR$\Libraries\CMSIS\Device\YICHIP\YC3122\Source\Templates\iar\startup_yc3122.s - $PROJ_DIR$\Libraries\sdk\yc_exti.c + $PROJ_DIR$\Libraries\sdk\yc_uart.c diff --git a/bsp/yichip/yc3122-pos/project.uvprojx b/bsp/yichip/yc3122-pos/project.uvprojx index 46a47fb2ea6..43a2f0e18ac 100644 --- a/bsp/yichip/yc3122-pos/project.uvprojx +++ b/bsp/yichip/yc3122-pos/project.uvprojx @@ -485,6 +485,25 @@ + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + --c99 + __RT_IPC_SOURCE__ + + + + + + + + dataqueue.c @@ -1154,6 +1173,13 @@ Libraries\core\system.c + + + system_yc3122.c + 1 + Libraries\CMSIS\Device\YICHIP\YC3122\Source\Templates\system_yc3122.c + + startup_yc3122.s @@ -1168,13 +1194,6 @@ Libraries\sdk\yc_gpio.c - - - yc_wdt.c - 1 - Libraries\sdk\yc_wdt.c - - sdk_yc_qspi.lib @@ -1191,16 +1210,16 @@ - system_yc3122.c + yc_uart.c 1 - Libraries\CMSIS\Device\YICHIP\YC3122\Source\Templates\system_yc3122.c + Libraries\sdk\yc_uart.c - yc_uart.c + yc_wdt.c 1 - Libraries\sdk\yc_uart.c + Libraries\sdk\yc_wdt.c diff --git a/bsp/zynqmp-a53-dfzu2eg/.config b/bsp/zynqmp-a53-dfzu2eg/.config new file mode 100644 index 00000000000..d0d05db28b5 --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/.config @@ -0,0 +1,1148 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=4 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=8192 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +CONFIG_RT_KPRINTF_USING_LONGLONG=y +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_DEBUGING_PAGE_LEAK is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_PAGE_MAX_ORDER=11 +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_MEMTRACE=y +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +CONFIG_RT_USING_DEVICE_OPS=y +CONFIG_RT_USING_INTERRUPT_INFO=y +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_SCHED_THREAD_CTX=y +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50100 +CONFIG_RT_USING_STDC_ATOMIC=y +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 + +# +# AArch64 Architecture Configuration +# +CONFIG_ARCH_TEXT_OFFSET=0x200000 +CONFIG_ARCH_RAM_OFFSET=0x0 +CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096 +CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_CPU_64BIT=y +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_HW_ATOMIC is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_MM_MMU=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_MMU=y +CONFIG_ARCH_ARMV8=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=10 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=256 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FD_MAX=32 +# CONFIG_RT_USING_DFS_V1 is not set +CONFIG_RT_USING_DFS_V2=y +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +# CONFIG_RT_DFS_ELM_USE_EXFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_ROMFS_USER_ROOT is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=256 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_NULL=y +CONFIG_RT_USING_ZERO=y +CONFIG_RT_USING_RANDOM=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +CONFIG_RT_USING_PM=y +CONFIG_PM_TICKLESS_THRESHOLD_TIME=2 +# CONFIG_PM_USING_CUSTOM_CONFIG is not set +# CONFIG_PM_ENABLE_DEBUG is not set +# CONFIG_PM_ENABLE_SUSPEND_SLEEP_MODE is not set +# CONFIG_PM_ENABLE_THRESHOLD_SLEEP_MODE is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +CONFIG_RT_USING_SOFT_RTC=y +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +CONFIG_RT_USING_DEV_BUS=y +# CONFIG_RT_USING_WIFI is not set +CONFIG_RT_USING_VIRTIO=y +CONFIG_RT_USING_VIRTIO10=y +CONFIG_RT_USING_VIRTIO_MMIO_ALIGN=y +CONFIG_RT_USING_VIRTIO_BLK=y +# CONFIG_RT_USING_VIRTIO_NET is not set +CONFIG_RT_USING_VIRTIO_CONSOLE=y +CONFIG_RT_USING_VIRTIO_CONSOLE_PORT_MAX_NR=4 +CONFIG_RT_USING_VIRTIO_GPU=y +CONFIG_RT_USING_VIRTIO_INPUT=y +CONFIG_RT_USING_PIN=y +CONFIG_RT_USING_KTIME=y +# CONFIG_RT_USING_HWTIMER is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +CONFIG_RT_USING_POSIX_FS=y +CONFIG_RT_USING_POSIX_DEVIO=y +CONFIG_RT_USING_POSIX_STDIO=y +CONFIG_RT_USING_POSIX_POLL=y +CONFIG_RT_USING_POSIX_SELECT=y +# CONFIG_RT_USING_POSIX_EVENTFD is not set +# CONFIG_RT_USING_POSIX_TIMERFD is not set +# CONFIG_RT_USING_POSIX_SOCKET is not set +CONFIG_RT_USING_POSIX_TERMIOS=y +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_POSIX_MMAN is not set +CONFIG_RT_USING_POSIX_DELAY=y +CONFIG_RT_USING_POSIX_CLOCK=y +CONFIG_RT_USING_POSIX_TIMER=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +CONFIG_RT_USING_POSIX_PIPE=y +CONFIG_RT_USING_POSIX_PIPE_SIZE=512 +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +CONFIG_RT_USING_RESOURCE_ID=y +CONFIG_RT_USING_ADT=y +CONFIG_RT_USING_ADT_AVL=y +CONFIG_RT_USING_ADT_BITMAP=y +CONFIG_RT_USING_ADT_HASHMAP=y +CONFIG_RT_USING_ADT_REF=y +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_NCNN is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# +CONFIG_SOC_ZYNQMP_AARCH64=y + +# +# Hardware Drivers Config +# +CONFIG_BSP_SUPPORT_FPU=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +CONFIG_BSP_USING_GIC=y +CONFIG_BSP_USING_GICV2=y +# CONFIG_BSP_USING_GICV3 is not set diff --git a/bsp/zynqmp-a53-dfzu2eg/Kconfig b/bsp/zynqmp-a53-dfzu2eg/Kconfig new file mode 100644 index 00000000000..5f97de80d3a --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/Kconfig @@ -0,0 +1,34 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_ZYNQMP_AARCH64 + bool + select ARCH_ARMV8 + select ARCH_CPU_64BIT + select ARCH_ARM_MMU + select RT_USING_CACHE + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select RT_USING_GIC + select BSP_USING_GIC + select ARCH_MM_MMU + default y + +source "$BSP_DIR/drivers/Kconfig" diff --git a/bsp/zynqmp-a53-dfzu2eg/README.md b/bsp/zynqmp-a53-dfzu2eg/README.md new file mode 100644 index 00000000000..6f69deb1c63 --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/README.md @@ -0,0 +1,157 @@ +# DFZU2EG MPSoC 板级支持包说明 + +## 1. 简介 + +正点原子 DFZU2EG MPSoC 开发板采用Xilinx的Zynq UltraScale+ MPSoC芯片作为主控芯片。它主要分为PS和PL两部分，在PS部分中主要由Arm Cortex A53（APU 共4个核）、Arm Cortex R5F（RPU 共两个核）以及Arm Mali 400 MP2（GPU）三种内核处理器构成，并且还包括DDR 控制单元、平台管理单元、高速外设控制器以及普通外设控制器等外设组成。 + +该板级支持包主要是针对APU做的一份移植，支持RT-Thread标准版和Smart版内核。 + +DFZU2EG MPSoC 开发板的详细资源信息可以查阅正点原子此开发板的相关手册，也可以参考下图： + +![2eg_mpsoc_board](figures/2eg_mpsoc_board.png) + +## 2. 编译说明 + +推荐使用ubuntu20的[env环境](https://github.com/RT-Thread/env)，当然也可以使用windows上的[env工具](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)进行编译。下面介绍**标准版**和**Smart版本**的编译流程。 + +### 2.1 RT-Thread编译 + +**1.menuconfig配置工程：** + +该BSP默认menuconfig支持的就是RT-Thread标准版，无需配置工程。 + +**2.配置工具链相关环境：** + +依次执行下面命令进行环境变量的相关配置： + +```shell +export RTT_CC=gcc +export RTT_EXEC_PATH="/opt/tools/gnu_gcc/arm-gnu-toolchain-13.2.Rel1-x86_64-aarch64-none-elf/bin" +export RTT_CC_PREFIX=aarch64-none-elf- +export PATH=$PATH:$RTT_EXEC_PATH +``` + +**3.编译：** + +```shell +scons -j12 +``` + +### 2.2 RT-Smart编译 + +**1.menuconfig配置工程：** + +```shell +RT-Thread Kernel ---> + [*] Enable RT-Thread Smart (microkernel on kernel/userland) +``` + +**2.配置工具链相关环境：** + +依次执行下面命令进行环境变量的相关配置： + +```shell +export RTT_CC=gcc +export RTT_EXEC_PATH="/opt/tools/gnu_gcc/aarch64-linux-musleabi_for_x86_64-pc-linux-gnu/bin" +export RTT_CC_PREFIX=aarch64-linux-musleabi- +export PATH=$PATH:$RTT_EXEC_PATH +``` + +**3.编译：** + +```shell +scons -j12 +``` + +如果编译正确无误，会产生 `rtthread.elf`, `rtthread.bin` 文件。 + +## 3. 环境搭建 + +### 3.1 准备好串口线 + +连线情况如下图所示： + +![2eg_mpsoc_uart](figures/2eg_mpsoc_uart.png) + +串口参数： 115200 8N1 ，硬件和软件流控为关。 + +### 3.2 RTT固件放在SD卡运行 + +暂时不支持，需要使用 u-boot 加载。 + +### 3.3 RTT程序用uboot加载 + +需要注意的以下问题： + +- 保证开发板和保存固件的PC机处于同一网段，互相可以ping通。 +- 保证PC机已经成功配置TFTP的相关服务。 + +可以使用开发板出厂自带的uboot(EMMC)来加载RTT程序，将网线连接到开发板的PS网口，然后在uboot控制台输入下列命令： + +```shell +setenv ipaddr 192.168.1.50 +setenv ethaddr b8:ae:1d:01:00:00 +setenv gatewayip 192.168.1.1 +setenv netmask 255.255.255.0 +setenv serverip 192.168.1.3 +tftpboot 0x00200000 rtthread.bin +go 0x00200000 +``` + +其中`192.168.1.3`为TFTP服务器的PC机的IP地址，大家可以根据自己的实际情况进行修改。 + +执行完上述命令后，uboot就可以自动从tftp服务器上获取固件，然后开始执行了。 + +完成后可以看到串口的输出信息： + +**标准版log信息：** + +```shell +heap: [0x00299540 - 0x04000000] + + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Apr 11 2024 11:43:19 + 2006 - 2024 Copyright by RT-Thread team +hello rt-thread +msh /> +``` + +**Smart版log信息：** + +```shell +heap: [0x002fd030 - 0x04000000] + + \ | / +- RT - Thread Smart Operating System + / | \ 5.1.0 build Apr 11 2024 11:47:02 + 2006 - 2024 Copyright by RT-Thread team +Press any key to stop init process startup ... 3 +Press any key to stop init process startup ... 2 +Press any key to stop init process startup ... 1 +Starting init ... +[E/lwp] lwp_startup: init program not found +Switching to legacy mode... +hello rt-thread +msh /> +``` + +## 4. 支持情况 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | UART0 | +| GPIO | 暂不支持 | - | +| SPI | 暂不支持 | - | +| SDIO | 暂不支持 | - | +| ETH | 暂不支持 | - | + +目前BSP仅保证成功运行，驱动后续会慢慢支持！ + +## 5. 注意事项 + +对于ZYNQ的开发，需要使用Vivado软件对开发板的硬件进行一些配置，来生产相应的fsbl.elf文件，比如串口引脚的初始化等等，所以如果大家需要修改串口的输出引脚信息，需要更新fsbl.elf，而这些知识是需要具备一定的ZYNQ开发基础的。 + +## 6. 联系人信息 + +维护人：[liYony](https://github.com/liYony) diff --git a/bsp/zynqmp-a53-dfzu2eg/SConscript b/bsp/zynqmp-a53-dfzu2eg/SConscript new file mode 100644 index 00000000000..c7ef7659ece --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/zynqmp-a53-dfzu2eg/SConstruct b/bsp/zynqmp-a53-dfzu2eg/SConstruct new file mode 100644 index 00000000000..3791a1bfac4 --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/SConstruct @@ -0,0 +1,44 @@ +import os +import sys +import rtconfig +import re + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.join(os.getcwd(), '..', '..') + + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT +TRACE_CONFIG = "" + +content = "" +with open("rtconfig.h") as f: + for line in f.readlines(): + if line.find("RT_BACKTRACE_FUNCTION_NAME") != -1: + for token in line.split(" "): + if re.match(r'RT_BACKTRACE_FUNCTION_NAME$', token, flags=0): + TRACE_CONFIG = " " + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS + TRACE_CONFIG, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS + TRACE_CONFIG, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS + TRACE_CONFIG, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] +env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group' + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/zynqmp-a53-dfzu2eg/applications/SConscript b/bsp/zynqmp-a53-dfzu2eg/applications/SConscript new file mode 100644 index 00000000000..c583d3016e0 --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/zynqmp-a53-dfzu2eg/applications/main.c b/bsp/zynqmp-a53-dfzu2eg/applications/main.c new file mode 100644 index 00000000000..4447a4f47de --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/applications/main.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/10/7 bernard the first version + */ + +#include + +int main(void) +{ + rt_kprintf("hello rt-thread\n"); + + return 0; +} diff --git a/bsp/zynqmp-a53-dfzu2eg/drivers/Kconfig b/bsp/zynqmp-a53-dfzu2eg/drivers/Kconfig new file mode 100644 index 00000000000..a1194aff55d --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/drivers/Kconfig @@ -0,0 +1,32 @@ +menu "Hardware Drivers Config" + config BSP_SUPPORT_FPU + bool "Using Float" + default y + + menuconfig BSP_USING_UART + bool "Using UART" + select RT_USING_SERIAL + default y + + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enabel UART 0" + default y + endif + + config BSP_USING_GIC + bool + default y + + choice + prompt "GIC Version" + default BSP_USING_GICV2 + + config BSP_USING_GICV2 + bool "GICv2" + + config BSP_USING_GICV3 + bool "GICv3" + endchoice + +endmenu diff --git a/bsp/zynqmp-a53-dfzu2eg/drivers/SConscript b/bsp/zynqmp-a53-dfzu2eg/drivers/SConscript new file mode 100644 index 00000000000..7f60b2bffae --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/drivers/SConscript @@ -0,0 +1,11 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd , cwd + '/zynqmp'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/zynqmp-a53-dfzu2eg/drivers/board.c b/bsp/zynqmp-a53-dfzu2eg/drivers/board.c new file mode 100644 index 00000000000..08a280d9412 --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/drivers/board.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-11 liYony the first version + */ + +#include +#include +#include +#include +#include +#include + +extern size_t MMUTable[]; + +#ifdef RT_USING_SMART +struct mem_desc platform_mem_desc[] = { + {KERNEL_VADDR_START, KERNEL_VADDR_START + 0x7FF00000 - 1, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM} +}; +#else +struct mem_desc platform_mem_desc[] = +{ + {0x00200000, 0x7FF00000 - 1, 0x00200000, NORMAL_MEM}, + {GIC400_DISTRIBUTOR_PPTR, GIC400_DISTRIBUTOR_PPTR + GIC400_SIZE - 1, GIC400_DISTRIBUTOR_PPTR, DEVICE_MEM}, + {GIC400_CONTROLLER_PPTR, GIC400_CONTROLLER_PPTR + GIC400_SIZE - 1, GIC400_CONTROLLER_PPTR, DEVICE_MEM}, +}; +#endif + +const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]); + +void idle_wfi(void) +{ + asm volatile("wfi"); +} + +void rt_hw_board_init(void) +{ +#ifdef RT_USING_SMART + rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET); +#else + rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xffffd0000000, 0x10000000, MMUTable, 0); +#endif + rt_region_t init_page_region; + init_page_region.start = PAGE_START; + init_page_region.end = PAGE_END; + rt_page_init(init_page_region); + + rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size); + +#ifdef RT_USING_HEAP + /* initialize system heap */ + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); + + /* initialize uart */ + rt_hw_uart_init(); + + /* initialize timer for os tick */ + rt_hw_gtimer_init(); + + rt_thread_idle_sethook(idle_wfi); +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + /* set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + rt_kprintf("heap: [0x%08x - 0x%08x]\n", HEAP_BEGIN, HEAP_END); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} diff --git a/bsp/zynqmp-a53-dfzu2eg/drivers/board.h b/bsp/zynqmp-a53-dfzu2eg/drivers/board.h new file mode 100644 index 00000000000..53f4a3a89de --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/drivers/board.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-11 liYony the first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +extern unsigned char __bss_end; + +#define HEAP_BEGIN ((void*)&__bss_end) + +#ifdef RT_USING_SMART +#define HEAP_END ((size_t)KERNEL_VADDR_START + 64 * 1024 * 1024) +#define PAGE_START HEAP_END +#define PAGE_END ((size_t)KERNEL_VADDR_START + 128 * 1024 * 1024) +#else +#define KERNEL_VADDR_START 0x0 + +#define HEAP_END (KERNEL_VADDR_START + 64 * 1024 * 1024) +#define PAGE_START HEAP_END +#define PAGE_END ((size_t)PAGE_START + 64 * 1024 * 1024) +#endif + +void rt_hw_board_init(void); + +int rt_hw_uart_init(void); + +#endif /* __BOARD_H__ */ diff --git a/bsp/zynqmp-a53-dfzu2eg/drivers/drv_uart.c b/bsp/zynqmp-a53-dfzu2eg/drivers/drv_uart.c new file mode 100644 index 00000000000..efaed8a1c2c --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/drivers/drv_uart.c @@ -0,0 +1,346 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-11 liYony the first version + */ + +#include +#include +#include +#include "board.h" +#include "zynqmp_uart.h" + +#define ZYNQMP_UART_DEVICE_DEFAULT(base, irq, clk) {{ \ + .ops = &_zynqmp_ops, \ + .config = RT_SERIAL_CONFIG_DEFAULT \ + }, \ + .hw_base = base, \ + .irqno = irq, \ + .in_clk = clk \ +} + +struct zynqmp_uart_device +{ + struct rt_serial_device device; + rt_ubase_t hw_base; + rt_uint32_t irqno; + rt_uint32_t in_clk; +}; + +static void _uart_set_fifo_threshold(rt_ubase_t base, rt_uint8_t trigger_level) +{ + rt_uint32_t reg_triger; + + /* Assert validates the input arguments */ + RT_ASSERT(base != RT_NULL); + RT_ASSERT(trigger_level <= (rt_uint8_t)XUARTPS_RXWM_MASK); + + reg_triger = ((rt_uint32_t)trigger_level) & (rt_uint32_t)XUARTPS_RXWM_MASK; + + /* + * Write the new value for the FIFO control register to it such that the + * threshold is changed + */ + writel(reg_triger, base + XUARTPS_RXWM_OFFSET); +} + +static void _uart_set_interrupt_mask(rt_ubase_t base, rt_uint32_t mask) +{ + rt_uint32_t temp_mask = mask; + + RT_ASSERT(base != RT_NULL); + + temp_mask &= (rt_uint32_t)XUARTPS_IXR_MASK; + + writel(temp_mask, base + XUARTPS_IER_OFFSET); + writel((~temp_mask), base + XUARTPS_IDR_OFFSET); +} + +static rt_err_t _uart_baudrate_init(rt_ubase_t base, struct serial_configure *cfg, rt_uint32_t in_clk) +{ + rt_uint32_t iter_baud_div; /* Iterator for available baud divisor values */ + rt_uint32_t brgr_value; /* Calculated value for baud rate generator */ + rt_uint32_t calc_baudrate; /* Calculated baud rate */ + rt_uint32_t baud_error; /* Diff between calculated and requested baud rate */ + rt_uint32_t best_brgr = 0U; /* Best value for baud rate generator */ + rt_uint8_t best_baud_div = 0U; /* Best value for baud divisor */ + rt_uint32_t best_error = 0xFFFFFFFFU; + rt_uint32_t percent_error; + rt_uint32_t mode_reg; + rt_uint32_t input_clk; + rt_uint32_t temp_reg; + + /* Asserts validate the input arguments */ + RT_ASSERT(base != RT_NULL); + RT_ASSERT(cfg->baud_rate <= (rt_uint32_t)XUARTPS_MAX_RATE); + RT_ASSERT(cfg->baud_rate >= (rt_uint32_t)XUARTPS_MIN_RATE); + + /* + * Make sure the baud rate is not impossilby large. + * Fastest possible baud rate is Input Clock / 2. + */ + if ((cfg->baud_rate * 2) > in_clk) + { + return -RT_EINVAL; + } + /* Check whether the input clock is divided by 8 */ + mode_reg = readl(base + XUARTPS_MR_OFFSET); + + input_clk = in_clk; + if (mode_reg & XUARTPS_MR_CLKSEL) + { + input_clk = in_clk / 8; + } + + /* + * Determine the Baud divider. It can be 4to 254. + * Loop through all possible combinations + */ + for (iter_baud_div = 4; iter_baud_div < 255; iter_baud_div++) + { + + /* Calculate the value for BRGR register */ + brgr_value = input_clk / (cfg->baud_rate * (iter_baud_div + 1)); + + /* Calculate the baud rate from the BRGR value */ + calc_baudrate = input_clk / (brgr_value * (iter_baud_div + 1)); + + /* Avoid unsigned integer underflow */ + if (cfg->baud_rate > calc_baudrate) + { + baud_error = cfg->baud_rate - calc_baudrate; + } + else + { + baud_error = calc_baudrate - cfg->baud_rate; + } + + /* Find the calculated baud rate closest to requested baud rate. */ + if (best_error > baud_error) + { + + best_brgr = brgr_value; + best_baud_div = iter_baud_div; + best_error = baud_error; + } + } + + /* Make sure the best error is not too large. */ + percent_error = (best_error * 100) / cfg->baud_rate; + if (XUARTPS_MAX_BAUD_ERROR_RATE < percent_error) + { + return -RT_EINVAL; + } + + /* Disable TX and RX to avoid glitches when setting the baud rate. */ + temp_reg = (((readl(base + XUARTPS_CR_OFFSET)) & ((rt_uint32_t)(~XUARTPS_CR_EN_DIS_MASK))) | + ((rt_uint32_t)XUARTPS_CR_RX_DIS | (rt_uint32_t)XUARTPS_CR_TX_DIS)); + writel(temp_reg, base + XUARTPS_CR_OFFSET); + + /* Set the baud rate divisor */ + writel(best_brgr, base + XUARTPS_BAUDGEN_OFFSET); + writel(best_baud_div, base + XUARTPS_BAUDDIV_OFFSET); + + /* RX and TX SW reset */ + writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST, base + XUARTPS_CR_OFFSET); + + /* Enable device */ + temp_reg = (((readl(base + XUARTPS_CR_OFFSET)) & ((rt_uint32_t)(~XUARTPS_CR_EN_DIS_MASK))) | + ((rt_uint32_t)XUARTPS_CR_RX_EN | (rt_uint32_t)XUARTPS_CR_TX_EN)); + writel(temp_reg, base + XUARTPS_CR_OFFSET); + + return RT_EOK; +} + +static rt_err_t zynqmp_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct zynqmp_uart_device *uart = (struct zynqmp_uart_device *)serial; + + RT_ASSERT(uart != RT_NULL); + + if (_uart_baudrate_init(uart->hw_base, cfg, uart->in_clk) != RT_EOK) + { + return -RT_ERROR; + } + + rt_uint32_t mode_reg = 0U; + + /* Set the parity mode */ + mode_reg = readl(uart->hw_base + XUARTPS_MR_OFFSET); + + /* Mask off what's already there */ + mode_reg &= (~((rt_uint32_t)XUARTPS_MR_CHARLEN_MASK | + (rt_uint32_t)XUARTPS_MR_STOPMODE_MASK | + (rt_uint32_t)XUARTPS_MR_PARITY_MASK)); + + switch (cfg->data_bits) + { + case DATA_BITS_6: + mode_reg |= (rt_uint32_t)XUARTPS_MR_CHARLEN_6_BIT; + break; + case DATA_BITS_7: + mode_reg |= (rt_uint32_t)XUARTPS_MR_CHARLEN_7_BIT; + break; + case DATA_BITS_8: + mode_reg |= (rt_uint32_t)XUARTPS_MR_CHARLEN_8_BIT; + break; + default: + mode_reg |= (rt_uint32_t)XUARTPS_MR_CHARLEN_8_BIT; + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + mode_reg |= (rt_uint32_t)XUARTPS_MR_STOPMODE_1_BIT; + break; + case STOP_BITS_2: + mode_reg |= (rt_uint32_t)XUARTPS_MR_STOPMODE_2_BIT; + break; + default: + mode_reg |= (rt_uint32_t)XUARTPS_MR_STOPMODE_1_BIT; + break; + } + + switch (cfg->parity) + { + case PARITY_NONE: + mode_reg |= (rt_uint32_t)XUARTPS_MR_PARITY_NONE; + break; + case PARITY_ODD: + mode_reg |= (rt_uint32_t)XUARTPS_MR_PARITY_ODD; + break; + case PARITY_EVEN: + mode_reg |= (rt_uint32_t)XUARTPS_MR_PARITY_EVEN; + break; + default: + mode_reg |= (rt_uint32_t)XUARTPS_MR_PARITY_NONE; + break; + } + + /* Write the mode register out */ + writel(mode_reg, uart->hw_base + XUARTPS_MR_OFFSET); + + /* Set the RX FIFO trigger at 8 data bytes. */ + writel(0x08U, uart->hw_base + XUARTPS_RXWM_OFFSET); + + /* Set the RX timeout to 1, which will be 4 character time */ + writel(0x01U, uart->hw_base + XUARTPS_RXTOUT_OFFSET); + + /* Disable all interrupts, polled mode is the default */ + writel(XUARTPS_IXR_MASK, uart->hw_base + XUARTPS_IDR_OFFSET); + + return RT_EOK; +} + +static rt_err_t zynqmp_uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct zynqmp_uart_device *uart = (struct zynqmp_uart_device *)serial; + + RT_ASSERT(uart != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* Disable the UART Interrupt */ + rt_hw_interrupt_mask(uart->irqno); + _uart_set_interrupt_mask(uart->hw_base, 0U); + break; + case RT_DEVICE_CTRL_SET_INT: + /* Enable the UART Interrupt */ + _uart_set_fifo_threshold(uart->hw_base, 1); + rt_hw_interrupt_umask(uart->irqno); + _uart_set_interrupt_mask(uart->hw_base, XUARTPS_IXR_RXOVR); + break; + } + + return RT_EOK; +} + +static int zynqmp_uart_putc(struct rt_serial_device *serial, char c) +{ + struct zynqmp_uart_device *uart = (struct zynqmp_uart_device *)serial; + + RT_ASSERT(uart != RT_NULL); + + /* Wait until there is space in TX FIFO */ + while ((readl(uart->hw_base + XUARTPS_SR_OFFSET) & + XUARTPS_SR_TXFULL) == XUARTPS_SR_TXFULL) + { + ; + } + + /* Write the byte into the TX FIFO */ + writel((rt_uint32_t)c, uart->hw_base + XUARTPS_FIFO_OFFSET); + + return 1; +} + +static int zynqmp_uart_getc(struct rt_serial_device *serial) +{ + struct zynqmp_uart_device *uart = (struct zynqmp_uart_device *)serial; + + RT_ASSERT(uart != RT_NULL); + + /* Wait until there is data */ + if ((readl(uart->hw_base + XUARTPS_SR_OFFSET) & + XUARTPS_SR_RXEMPTY) == XUARTPS_SR_RXEMPTY) + { + return -1; + } + + int ch = readl(uart->hw_base + XUARTPS_FIFO_OFFSET); + + return ch; +} + +static const struct rt_uart_ops _zynqmp_ops = +{ + zynqmp_uart_configure, + zynqmp_uart_control, + zynqmp_uart_putc, + zynqmp_uart_getc, +}; + +#ifdef BSP_USING_UART0 +static struct zynqmp_uart_device _uart0_device = + ZYNQMP_UART_DEVICE_DEFAULT(ZYNQMP_UART0_BASE, ZYNQMP_UART0_IRQNUM, ZYNQMP_UART0_CLK_FREQ_HZ); +#endif + +static void rt_hw_uart_isr(int irqno, void *param) +{ + struct zynqmp_uart_device *uart = (struct zynqmp_uart_device *)param; + + RT_ASSERT(uart != RT_NULL); + struct rt_serial_device *serial = &(uart->device); + rt_uint32_t isr_status; + + isr_status = readl(uart->hw_base + XUARTPS_IMR_OFFSET); + isr_status &= readl(uart->hw_base + XUARTPS_ISR_OFFSET); + if (isr_status & (rt_uint32_t)XUARTPS_IXR_RXOVR) + { + writel(XUARTPS_IXR_RXOVR, uart->hw_base + XUARTPS_ISR_OFFSET); + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } +} + +int rt_hw_uart_init(void) +{ + struct zynqmp_uart_device *uart = RT_NULL; + +#ifdef BSP_USING_UART0 + uart = &_uart0_device; + _uart0_device.hw_base = (rt_size_t)rt_ioremap((void*)_uart0_device.hw_base, ZYNQMP_UART0_SIZE); + /* register UART0 device */ + rt_hw_serial_register(&uart->device, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, uart, "uart0"); +#endif + + return 0; +} diff --git a/bsp/zynqmp-a53-dfzu2eg/drivers/drv_uart.h b/bsp/zynqmp-a53-dfzu2eg/drivers/drv_uart.h new file mode 100644 index 00000000000..20d2ca3c18a --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/drivers/drv_uart.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-11 liYony the first version + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +#include + +int rt_hw_uart_init(void); + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/zynqmp-a53-dfzu2eg/drivers/zynqmp.h b/bsp/zynqmp-a53-dfzu2eg/drivers/zynqmp.h new file mode 100644 index 00000000000..72da0549db9 --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/drivers/zynqmp.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-04-11 liYony the first version + */ + +#ifndef __ZYNQMP_H__ +#define __ZYNQMP_H__ + +#include +#include + +#ifdef RT_USING_SMART +#include +#endif + +#define __REG32(x) (*((volatile unsigned int *)(x))) +#define __REG16(x) (*((volatile unsigned short *)(x))) + +/* UART */ +#define ZYNQMP_UART0_BASE 0xFF000000 +#define ZYNQMP_UART0_SIZE 0x00010000 +#define ZYNQMP_UART0_IRQNUM (32 + 21) +#define ZYNQMP_UART0_CLK_FREQ_HZ (99999001) + +/* GIC */ +#define MAX_HANDLERS 195 +#define GIC_IRQ_START 0 +#define ARM_GIC_NR_IRQS 195 +#define ARM_GIC_MAX_NR 1 + +/* GICv2 */ +#define GIC400_DISTRIBUTOR_PPTR 0xF9010000U +#define GIC400_CONTROLLER_PPTR 0xF9020000U +#define GIC400_SIZE 0x00001000U + +/* the basic constants and interfaces needed by gic */ +rt_inline rt_ubase_t platform_get_gic_dist_base(void) +{ + return GIC400_DISTRIBUTOR_PPTR; +} + +rt_inline rt_ubase_t platform_get_gic_cpu_base(void) +{ + return GIC400_CONTROLLER_PPTR; +} + +#endif /* __ZYNQMP_H__ */ diff --git a/bsp/zynqmp-a53-dfzu2eg/drivers/zynqmp/zynqmp_reg.h b/bsp/zynqmp-a53-dfzu2eg/drivers/zynqmp/zynqmp_reg.h new file mode 100644 index 00000000000..b780da8b63d --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/drivers/zynqmp/zynqmp_reg.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __ZYNQMP_REG_H__ +#define __ZYNQMP_REG_H__ + +/* bit field helpers. */ +#define __M(n) (~(~0<<(n))) +#define __RBF(number, n) ((number)&__M(n)) +#define __BF(number, n, m) __RBF((number>>m), (n-m+1)) +#define REG_BF(number, n, m) (m + +/* The following constant defines the amount of error that is allowed for + * a specified baud rate. This error is the difference between the actual + * baud rate that will be generated using the specified clock and the + * desired baud rate. + */ +#define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */ + +/* + * The following constants indicate the max and min baud rates and these + * numbers are based only on the testing that has been done. The hardware + * is capable of other baud rates. + */ +#define XUARTPS_MAX_RATE 6240000U +#define XUARTPS_MIN_RATE 110U + +/** @name Register Map + * + * Register offsets for the UART. + * @{ + */ +#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */ +#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */ +#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */ +#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */ +#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */ +#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/ +#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */ +#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */ +#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */ +#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */ +#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */ +#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */ +#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */ +#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */ +#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */ +#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */ +#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */ +/* @} */ + +/** @name Control Register + * + * The Control register (CR) controls the major functions of the device. + * + * Control Register Bit Definition + */ +#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */ +#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */ +#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */ +#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */ +#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */ +#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */ +#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */ +#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */ +#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */ +#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */ +/* @}*/ + +/** @name Mode Register + * + * The mode register (MR) defines the mode of transfer as well as the data + * format. If this register is modified during transmission or reception, + * data validity cannot be guaranteed. + * + * Mode Register Bit Definition + * @{ + */ +#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */ +#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */ +#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */ +#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */ +#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */ +#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */ +#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */ +#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */ +#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */ +#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */ +#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */ +#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */ +#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */ +#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */ +#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */ +#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */ +#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */ +#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */ +#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */ +#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */ +#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */ +#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */ +#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */ +#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */ +#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */ +/* @} */ + +/** @name Interrupt Registers + * + * Interrupt control logic uses the interrupt enable register (IER) and the + * interrupt disable register (IDR) to set the value of the bits in the + * interrupt mask register (IMR). The IMR determines whether to pass an + * interrupt to the interrupt status register (ISR). + * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an + * interrupt. IMR and ISR are read only, and IER and IDR are write only. + * Reading either IER or IDR returns 0x00. + * + * All four registers have the same bit definitions. + * + * @{ + */ +#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */ +#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */ +#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */ +#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */ +#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */ +#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */ +#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */ +#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */ +#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */ +#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */ +#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */ +#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */ +#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */ +#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */ +#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */ +/* @} */ + +/** @name Baud Rate Generator Register + * + * The baud rate generator control register (BRGR) is a 16 bit register that + * controls the receiver bit sample clock and baud rate. + * Valid values are 1 - 65535. + * + * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit + * in the MR register. + * @{ + */ +#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */ +#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */ +#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */ + +/** @name Baud Divisor Rate register + * + * The baud rate divider register (BDIV) controls how much the bit sample + * rate is divided by. It sets the baud rate. + * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored. + * + * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by + * the MR_CCLK bit in the MR register. + * @{ + */ +#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */ +#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */ +/* @} */ + +/** @name Receiver Timeout Register + * + * Use the receiver timeout register (RTR) to detect an idle condition on + * the receiver data line. + * + * @{ + */ +#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */ +#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */ + +/** @name Receiver FIFO Trigger Level Register + * + * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at + * which the RX FIFO triggers an interrupt event. + * @{ + */ +#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */ +#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */ +#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */ +/* @} */ + +/** @name Transmit FIFO Trigger Level Register + * + * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at + * which the TX FIFO triggers an interrupt event. + * @{ + */ +#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */ +#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */ +/* @} */ + +/** @name Modem Control Register + * + * This register (MODEMCR) controls the interface with the modem or data set, + * or a peripheral device emulating a modem. + * + * @{ + */ +#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */ +#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */ +#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */ +/* @} */ + +/** @name Modem Status Register + * + * This register (MODEMSR) indicates the current state of the control lines + * from a modem, or another peripheral device, to the CPU. In addition, four + * bits of the modem status register provide change information. These bits + * are set to a logic 1 whenever a control input from the modem changes state. + * + * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem + * status interrupt is generated and this is reflected in the modem status + * register. + * + * @{ + */ +#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */ +#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */ +#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */ +#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */ +#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */ +#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */ +#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */ +#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */ +#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */ +/* @} */ + +/** @name Channel Status Register + * + * The channel status register (CSR) is provided to enable the control logic + * to monitor the status of bits in the channel interrupt status register, + * even if these are masked out by the interrupt mask register. + * + * @{ + */ +#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */ +#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */ +#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */ +#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */ +#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */ +#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */ +#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */ +#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */ +#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */ +#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */ +/* @} */ + +/** @name Flow Delay Register + * + * Operation of the flow delay register (FLOWDEL) is very similar to the + * receive FIFO trigger register. An internal trigger signal activates when the + * FIFO is filled to the level set by this register. This trigger will not + * cause an interrupt, although it can be read through the channel status + * register. In hardware flow control mode, RTS is deactivated when the trigger + * becomes active. RTS only resets when the FIFO level is four less than the + * level of the flow delay trigger and the flow delay trigger is not activated. + * A value less than 4 disables the flow delay. + * @{ + */ +#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */ +/* @} */ + +/** @name Receiver FIFO Byte Status Register + * + * The Receiver FIFO Status register is used to have a continuous + * monitoring of the raw unmasked byte status information. The register + * contains frame, parity and break status information for the top + * four bytes in the RX FIFO. + * + * Receiver FIFO Byte Status Register Bit Definition + * @{ + */ +#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */ +#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */ +#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */ +#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */ +#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */ +#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */ +#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */ +#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */ +#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */ +#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */ +#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */ +#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */ +#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */ +/* @} */ + +/* + * Defines for backwards compatibility, will be removed + * in the next version of the driver + */ +#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD +#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI +#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR +#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS + +#endif /* __ZYNQMP_UART_H__ */ diff --git a/bsp/zynqmp-a53-dfzu2eg/figures/2eg_mpsoc_board.png b/bsp/zynqmp-a53-dfzu2eg/figures/2eg_mpsoc_board.png new file mode 100644 index 00000000000..6cd636c7971 Binary files /dev/null and b/bsp/zynqmp-a53-dfzu2eg/figures/2eg_mpsoc_board.png differ diff --git a/bsp/zynqmp-a53-dfzu2eg/figures/2eg_mpsoc_uart.png b/bsp/zynqmp-a53-dfzu2eg/figures/2eg_mpsoc_uart.png new file mode 100644 index 00000000000..66e73007366 Binary files /dev/null and b/bsp/zynqmp-a53-dfzu2eg/figures/2eg_mpsoc_uart.png differ diff --git a/bsp/zynqmp-a53-dfzu2eg/rtconfig.h b/bsp/zynqmp-a53-dfzu2eg/rtconfig.h new file mode 100644 index 00000000000..a209b7de167 --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/rtconfig.h @@ -0,0 +1,342 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 16 +#define RT_CPUS_NR 4 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 8192 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 8192 + +/* kservice optimization */ + +#define RT_KSERVICE_USING_STDLIB +#define RT_KPRINTF_USING_LONGLONG +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_PAGE_MAX_ORDER 11 +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_MEMHEAP_AUTO_BINDING +#define RT_USING_MEMTRACE +#define RT_USING_HEAP +#define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS +#define RT_USING_INTERRUPT_INFO +#define RT_USING_SCHED_THREAD_CTX +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50100 +#define RT_USING_STDC_ATOMIC +#define RT_BACKTRACE_LEVEL_MAX_NR 32 + +/* AArch64 Architecture Configuration */ + +#define ARCH_TEXT_OFFSET 0x200000 +#define ARCH_RAM_OFFSET 0x0 +#define ARCH_SECONDARY_CPU_STACK_SIZE 4096 +#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS +#define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define RT_USING_CPU_FFS +#define ARCH_MM_MMU +#define ARCH_ARM +#define ARCH_ARM_MMU +#define ARCH_ARMV8 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 8192 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 10 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 256 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 32 +#define RT_USING_DFS_V2 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_ROMFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 256 +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_RANDOM +#define RT_USING_PM +#define PM_TICKLESS_THRESHOLD_TIME 2 +#define RT_USING_RTC +#define RT_USING_SOFT_RTC +#define RT_USING_DEV_BUS +#define RT_USING_VIRTIO +#define RT_USING_VIRTIO10 +#define RT_USING_VIRTIO_MMIO_ALIGN +#define RT_USING_VIRTIO_BLK +#define RT_USING_VIRTIO_CONSOLE +#define RT_USING_VIRTIO_CONSOLE_PORT_MAX_NR 4 +#define RT_USING_VIRTIO_GPU +#define RT_USING_VIRTIO_INPUT +#define RT_USING_PIN +#define RT_USING_KTIME + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + +#define RT_USING_POSIX_FS +#define RT_USING_POSIX_DEVIO +#define RT_USING_POSIX_STDIO +#define RT_USING_POSIX_POLL +#define RT_USING_POSIX_SELECT +#define RT_USING_POSIX_TERMIOS +#define RT_USING_POSIX_DELAY +#define RT_USING_POSIX_CLOCK +#define RT_USING_POSIX_TIMER + +/* Interprocess Communication (IPC) */ + +#define RT_USING_POSIX_PIPE +#define RT_USING_POSIX_PIPE_SIZE 512 + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Memory protection */ + + +/* Utilities */ + +#define RT_USING_RESOURCE_ID +#define RT_USING_ADT +#define RT_USING_ADT_AVL +#define RT_USING_ADT_BITMAP +#define RT_USING_ADT_HASHMAP +#define RT_USING_ADT_REF + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* BL808 WiFi */ + + +/* CYW43439 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + + +/* Kendryte SDK */ + + +/* sensors drivers */ + + +/* touch drivers */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +#define SOC_ZYNQMP_AARCH64 + +/* Hardware Drivers Config */ + +#define BSP_SUPPORT_FPU +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_USING_GIC +#define BSP_USING_GICV2 + +#endif diff --git a/bsp/zynqmp-a53-dfzu2eg/rtconfig.py b/bsp/zynqmp-a53-dfzu2eg/rtconfig.py new file mode 100644 index 00000000000..c363513a185 --- /dev/null +++ b/bsp/zynqmp-a53-dfzu2eg/rtconfig.py @@ -0,0 +1,47 @@ +import os + +# toolchains options +ARCH ='aarch64' +CPU ='cortex-a' +CROSS_TOOL = 'gcc' +PLATFORM = 'gcc' +EXEC_PATH = os.getenv('RTT_EXEC_PATH') or '/usr/bin' +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + CPP = PREFIX + 'cpp' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + CFPFLAGS = ' ' + AFPFLAGS = ' ' + DEVICE = ' -march=armv8-a -mtune=cortex-a53 -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing' + + CPPFLAGS= ' -E -P -x assembler-with-cpp' + CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall -fdiagnostics-color=always' + CFLAGS = DEVICE + CFPFLAGS + ' -Wall -Wno-cpp -std=gnu99 -fdiagnostics-color=always' + AFLAGS = ' -c' + AFPFLAGS + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + ' -lsupc++ -lgcc -static' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + CXXFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -Os' + CXXFLAGS += ' -Os' + CXXFLAGS += ' -Woverloaded-virtual -fno-exceptions -fno-rtti' + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.c b/bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.c index 81f1de959fd..3de829bef86 100644 --- a/bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.c +++ b/bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.c @@ -47,24 +47,26 @@ void xgpiops_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) XGpioPs_WritePin(&Gpio, pin, (value == PIN_HIGH)?1:0); } -rt_int8_t xgpiops_pin_read(rt_device_t dev, rt_base_t pin) +rt_ssize_t xgpiops_pin_read(rt_device_t dev, rt_base_t pin) { if (pin >= Gpio.MaxPinNum) - return 0; + { + return -RT_EINVAL; + } int DataRead = XGpioPs_ReadPin(&Gpio, pin); return DataRead?PIN_HIGH:PIN_LOW; } const static struct rt_pin_ops _xgpiops_pin_ops = - { - xgpiops_pin_mode, - xgpiops_pin_write, - xgpiops_pin_read, - RT_NULL, - RT_NULL, - RT_NULL, - RT_NULL, +{ + xgpiops_pin_mode, + xgpiops_pin_write, + xgpiops_pin_read, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, }; int rt_hw_pin_init(void) diff --git a/components/dfs/Kconfig b/components/dfs/Kconfig index 6af2555a143..2c822cf779e 100644 --- a/components/dfs/Kconfig +++ b/components/dfs/Kconfig @@ -45,6 +45,7 @@ endif config RT_USING_DFS_V2 bool "DFS v2.0" + select RT_USING_DEVICE_OPS endchoice if RT_USING_DFS_V1 @@ -170,6 +171,13 @@ endif depends on RT_USING_DFS_ROMFS default n +if RT_USING_SMART + config RT_USING_DFS_PTYFS + bool "Using Pseudo-Teletype Filesystem (UNIX98 PTY)" + depends on RT_USING_DFS_DEVFS + default y +endif + config RT_USING_DFS_CROMFS bool "Enable ReadOnly compressed file system on flash" default n diff --git a/components/dfs/dfs_v1/include/dfs_file.h b/components/dfs/dfs_v1/include/dfs_file.h index e125fb25acd..26c74c8f161 100644 --- a/components/dfs/dfs_v1/include/dfs_file.h +++ b/components/dfs/dfs_v1/include/dfs_file.h @@ -63,6 +63,7 @@ struct dfs_file struct dfs_vnode *vnode; /* file node struct */ void *data; /* Specific fd data */ }; +#define DFS_FILE_POS(dfs_file) ((dfs_file)->pos) #ifdef RT_USING_SMART struct dfs_mmap2_args diff --git a/components/dfs/dfs_v2/filesystems/devfs/devfs.c b/components/dfs/dfs_v2/filesystems/devfs/devfs.c index b2e75d06d80..7818ae19be9 100644 --- a/components/dfs/dfs_v2/filesystems/devfs/devfs.c +++ b/components/dfs/dfs_v2/filesystems/devfs/devfs.c @@ -13,6 +13,7 @@ #include #include +#include #include #include @@ -20,673 +21,501 @@ #include #include -#include "devfs.h" - -struct device_dirent -{ - struct rt_device **devices; - uint32_t device_count; -}; - -int dfs_devfs_open(struct dfs_file *file); -int dfs_devfs_close(struct dfs_file *file); -off_t generic_dfs_lseek(struct dfs_file *file, off_t offset, int whence); -ssize_t dfs_devfs_read(struct dfs_file *file, void *buf, size_t count, off_t *pos); -ssize_t dfs_devfs_write(struct dfs_file *file, const void *buf, size_t count, off_t *pos); -int dfs_devfs_ioctl(struct dfs_file *file, int cmd, void *args); -int dfs_devfs_getdents(struct dfs_file *file, struct dirent *dirp, uint32_t count); -static int dfs_devfs_poll(struct dfs_file *file, struct rt_pollreq *req); -int dfs_devfs_flush(struct dfs_file *file); -off_t dfs_devfs_lseek(struct dfs_file *file, off_t offset, int wherece); -int dfs_devfs_truncate(struct dfs_file *file, off_t offset); -int dfs_devfs_mmap(struct dfs_file *file, struct lwp_avl_struct *mmap); -int dfs_devfs_lock(struct dfs_file *file, struct file_lock *flock); -int dfs_devfs_flock(struct dfs_file *file, int operation, struct file_lock *flock); - -int dfs_devfs_mount(struct dfs_mnt *mnt, unsigned long rwflag, const void *data); -int dfs_devfs_umount(struct dfs_mnt *mnt); -int dfs_devfs_unlink(struct dfs_dentry *dentry); -int dfs_devfs_stat(struct dfs_dentry *dentry, struct stat *st); -int dfs_devfs_statfs(struct dfs_mnt *mnt, struct statfs *buf); -static struct dfs_vnode *dfs_devfs_lookup(struct dfs_dentry *dentry); -struct dfs_vnode *dfs_devfs_create_vnode(struct dfs_dentry *dentry, int type, mode_t mode); -static int dfs_devfs_free_vnode(struct dfs_vnode *vnode); - -static const struct dfs_file_ops _dev_fops = +static int dfs_devfs_open(struct dfs_file *file) { - .open = dfs_devfs_open, - .close = dfs_devfs_close, - .lseek = generic_dfs_lseek, - .read = dfs_devfs_read, - .write = dfs_devfs_write, - .ioctl = dfs_devfs_ioctl, - .getdents = dfs_devfs_getdents, - .poll = dfs_devfs_poll, - - .flush = dfs_devfs_flush, - .lseek = dfs_devfs_lseek, - .truncate = dfs_devfs_truncate, - .mmap = dfs_devfs_mmap, - .lock = dfs_devfs_lock, - .flock = dfs_devfs_flock, -}; - -static const struct dfs_filesystem_ops _devfs_ops = -{ - .name = "devfs", - - .default_fops = &_dev_fops, - .mount = dfs_devfs_mount, - .umount = dfs_devfs_umount, - .unlink = dfs_devfs_unlink, - .stat = dfs_devfs_stat, - .statfs = dfs_devfs_statfs, - .lookup = dfs_devfs_lookup, - .create_vnode = dfs_devfs_create_vnode, - .free_vnode = dfs_devfs_free_vnode, -}; - -static struct dfs_filesystem_type _devfs = -{ - .fs_ops = &_devfs_ops, -}; + int ret = RT_EOK; -static int _device_to_mode(struct rt_device *device) -{ - int mode = 0; + RT_ASSERT(file != RT_NULL); + RT_ASSERT(file->vnode->ref_count > 0); - switch (device->type) + if (file->vnode->ref_count > 1) { - case RT_Device_Class_Char: - mode = S_IFCHR | 0777; - break; - case RT_Device_Class_Block: - mode = S_IFBLK | 0777; - break; - case RT_Device_Class_Pipe: - mode = S_IFIFO | 0777; - break; - default: - mode = S_IFCHR | 0777; - break; + if (file->vnode->type == FT_DIRECTORY + && !(file->flags & O_DIRECTORY)) + { + return -ENOENT; + } + file->fpos = 0; } - return mode; -} - -static int _devfs_root_dirent_update(struct dfs_vnode *vnode) -{ - rt_err_t result = RT_EOK; - - if (vnode) + if (!S_ISDIR(file->vnode->mode)) { - // result = rt_mutex_take(&vnode->lock, RT_WAITING_FOREVER); - result = dfs_file_lock(); - if (result == RT_EOK) + rt_device_t device = RT_NULL; + struct dfs_dentry *de = file->dentry; + char *device_name = rt_malloc(DFS_PATH_MAX); + + if (!device_name) { - rt_uint32_t count = 0; - struct device_dirent *root_dirent = (struct device_dirent*) vnode->data; - if (root_dirent) rt_free(root_dirent); + return -ENOMEM; + } + + /* skip `/dev` */ + rt_snprintf(device_name, DFS_PATH_MAX, "%s%s", de->mnt->fullpath + sizeof("/dev") - 1, de->pathname); - count = rt_object_get_length(RT_Object_Class_Device); - root_dirent = (struct device_dirent *)rt_malloc(sizeof(struct device_dirent) + count * sizeof(rt_device_t)); - if (root_dirent != RT_NULL) + device = rt_device_find(device_name + 1); + if (device) + { + file->vnode->data = device; +#ifdef RT_USING_POSIX_DEVIO + if (device->fops && device->fops->open) { - root_dirent->device_count = count; - if (count != 0) + ret = device->fops->open(file); + if (ret == RT_EOK || ret == -RT_ENOSYS) { - root_dirent->devices = (rt_device_t *)(root_dirent + 1); - rt_object_get_pointers(RT_Object_Class_Device, (rt_object_t *)root_dirent->devices, count); + ret = RT_EOK; } - else + } + else if (device->ops && file->vnode->ref_count == 1) +#else + if (device->ops && file->vnode->ref_count == 1) +#endif /* RT_USING_POSIX_DEVIO */ + { + ret = rt_device_open(device, RT_DEVICE_OFLAG_RDWR); + if (ret == RT_EOK || ret == -RT_ENOSYS) { - root_dirent->devices = RT_NULL; + ret = RT_EOK; } } - - vnode->data = root_dirent; - result = count; - dfs_file_unlock(); } } - return result; + return ret; } -static struct dfs_vnode *dfs_devfs_lookup(struct dfs_dentry *dentry) +static int dfs_devfs_close(struct dfs_file *file) { - rt_device_t device = RT_NULL; - struct dfs_vnode *vnode = RT_NULL; - const char *pathname = dentry->pathname; + int ret = RT_EOK; + rt_device_t device; - DLOG(msg, "devfs", "vnode", DLOG_MSG, "dfs_vnode_create"); - vnode = dfs_vnode_create(); - if (vnode) + RT_ASSERT(file != RT_NULL); + RT_ASSERT(file->vnode->ref_count > 0); + + if (file->vnode && file->vnode->data) { - if (pathname[0] == '/' && pathname[1] == '\0') + /* get device handler */ + device = (rt_device_t)file->vnode->data; + +#ifdef RT_USING_POSIX_DEVIO + if (device->fops && device->fops->close) { - int count = _devfs_root_dirent_update(vnode); - - vnode->mode = S_IFDIR | 0644; - vnode->size = count; - vnode->nlink = 1; - vnode->fops = &_dev_fops; - vnode->mnt = dentry->mnt; - vnode->type = FT_DIRECTORY; + ret = device->fops->close(file); } - else + else if (file->vnode->ref_count == 1) +#else + if (device->ops && file->vnode->ref_count == 1) +#endif /* RT_USING_POSIX_DEVIO */ { - device = rt_device_find(&pathname[1]); - if (!device) - { - DLOG(msg, "devfs", "vnode", DLOG_MSG, "dfs_vnode_destroy(vnode), no-device"); - dfs_vnode_destroy(vnode); - vnode = RT_NULL; - } - else - { - vnode->mode = _device_to_mode(device); - vnode->size = device->ref_count; - vnode->nlink = 1; - vnode->fops = &_dev_fops; - vnode->data = device; - vnode->mnt = dentry->mnt; - vnode->type = FT_DEVICE; - } + /* close device handler */ + ret = rt_device_close(device); } } - return vnode; + return ret; } -struct dfs_vnode *dfs_devfs_create_vnode(struct dfs_dentry *dentry, int type, mode_t mode) +static ssize_t dfs_devfs_read(struct dfs_file *file, void *buf, size_t count, off_t *pos) { -#ifdef RT_USING_DEV_BUS - if (dentry && type == FT_DIRECTORY) - { - /* regester bus device */ - if (rt_device_bus_create(&dentry->pathname[1], 0)) - { - return dfs_devfs_lookup(dentry); - } - } -#endif + ssize_t ret = -RT_EIO; + rt_device_t device; - return RT_NULL; -} + RT_ASSERT(file != RT_NULL); -int dfs_devfs_free_vnode(struct dfs_vnode *vnode) -{ - if (S_ISDIR(vnode->mode)) + if (file->vnode && file->vnode->data) { - struct device_dirent *root_dirent; - - root_dirent = (struct device_dirent *)vnode->data; - RT_ASSERT(root_dirent != RT_NULL); + /* get device handler */ + device = (rt_device_t)file->vnode->data; - /* release dirent */ - DLOG(msg, "devfs", "devfs", DLOG_MSG, "free root_dirent"); - rt_free(root_dirent); - return RT_EOK; +#ifdef RT_USING_POSIX_DEVIO + if (device->fops && device->fops->read) + { + ret = device->fops->read(file, buf, count, pos); + } + else +#else + if (device->ops) +#endif /* RT_USING_POSIX_DEVIO */ + { + /* read device data */ + ret = rt_device_read(device, *pos, buf, count); + *pos += ret; + } } - /* which is a device */ - vnode->data = RT_NULL; - return 0; + return ret; } -int dfs_devfs_mount(struct dfs_mnt *mnt, unsigned long rwflag, const void *data) +static ssize_t dfs_devfs_write(struct dfs_file *file, const void *buf, size_t count, off_t *pos) { - RT_ASSERT(mnt != RT_NULL); + ssize_t ret = -RT_EIO; + rt_device_t device; - rt_atomic_add(&(mnt->ref_count), 1); - mnt->flags |= MNT_IS_LOCKED; + RT_ASSERT(file != RT_NULL); - return RT_EOK; -} + if(file->vnode->data) + { + /* get device handler */ + device = (rt_device_t)file->vnode->data; -int dfs_devfs_umount(struct dfs_mnt *mnt) -{ - return RT_EOK; -} + if ((file->dentry->pathname[0] == '/') && (file->dentry->pathname[1] == '\0')) + return -RT_ENOSYS; -int dfs_devfs_statfs(struct dfs_mnt *mnt, struct statfs *buf) -{ - if (mnt && buf) - { - buf->f_bsize = 512; - buf->f_blocks = 2048 * 64; // 64M - buf->f_bfree = buf->f_blocks; - buf->f_bavail = buf->f_bfree; +#ifdef RT_USING_POSIX_DEVIO + if (device->fops && device->fops->write) + { + ret = device->fops->write(file, buf, count, pos); + } + else +#else + if (device->ops) +#endif /* RT_USING_POSIX_DEVIO */ + { + /* read device data */ + ret = rt_device_write(device, *pos, buf, count); + *pos += ret; + } } - return RT_EOK; + return ret; } -int dfs_devfs_ioctl(struct dfs_file *file, int cmd, void *args) +static int dfs_devfs_ioctl(struct dfs_file *file, int cmd, void *args) { - rt_err_t result = RT_EOK; + int ret = RT_EOK; rt_device_t device; RT_ASSERT(file != RT_NULL); - /* get device handler */ - device = (rt_device_t)file->vnode->data; - RT_ASSERT(device != RT_NULL); + if (file->vnode && file->vnode->data) + { + /* get device handler */ + device = (rt_device_t)file->vnode->data; - if ((file->dentry->pathname[0] == '/') && (file->dentry->pathname[1] == '\0')) - return -RT_ENOSYS; + if ((file->dentry->pathname[0] == '/') && (file->dentry->pathname[1] == '\0')) + return -RT_ENOSYS; #ifdef RT_USING_POSIX_DEVIO - if (device->fops && device->fops->ioctl) - { - result = device->fops->ioctl(file, cmd, args); - } - else if (device->ops) -#else - if (device->ops) + if (device->fops && device->fops->ioctl) + { + ret = device->fops->ioctl(file, cmd, args); + } + else #endif /* RT_USING_POSIX_DEVIO */ - { - result = rt_device_control(device, cmd, args); + { + ret = rt_device_control(device, cmd, args); + } } - return result; + return ret; } -ssize_t dfs_devfs_read(struct dfs_file *file, void *buf, size_t count, off_t *pos) +static int dfs_devfs_getdents(struct dfs_file *file, struct dirent *dirp, uint32_t count) { - int result = -RT_EIO; - rt_device_t device; + int ret = -RT_ENOSYS; RT_ASSERT(file != RT_NULL); - /* get device handler */ - device = (rt_device_t)file->vnode->data; - RT_ASSERT(device != RT_NULL); - - if ((file->dentry->pathname[0] == '/') && (file->dentry->pathname[1] == '\0')) - return -RT_ENOSYS; - -#ifdef RT_USING_POSIX_DEVIO - if (device->fops && device->fops->read) - { - result = device->fops->read(file, buf, count, pos); - } - else if (device->ops) -#else - if (device->ops) -#endif /* RT_USING_POSIX_DEVIO */ - { - /* read device data */ - result = rt_device_read(device, *pos, buf, count); - *pos += result; - } - - return result; + return ret; } -ssize_t dfs_devfs_write(struct dfs_file *file, const void *buf, size_t count, off_t *pos) +static int dfs_devfs_poll(struct dfs_file *file, struct rt_pollreq *req) { - int result = -RT_EIO; + int mask = 0; rt_device_t device; RT_ASSERT(file != RT_NULL); - /* get device handler */ - device = (rt_device_t)file->vnode->data; - RT_ASSERT(device != RT_NULL); - - if ((file->dentry->pathname[0] == '/') && (file->dentry->pathname[1] == '\0')) - return -RT_ENOSYS; + if (file->vnode && file->vnode->data) + { + /* get device handler */ + device = (rt_device_t)file->vnode->data; #ifdef RT_USING_POSIX_DEVIO - if (device->fops && device->fops->write) - { - result = device->fops->write(file, buf, count, pos); - } - else if (device->ops) -#else - if (device->ops) + if (device->fops && device->fops->poll) + { + mask = device->fops->poll(file, req); + } #endif /* RT_USING_POSIX_DEVIO */ - { - /* read device data */ - result = rt_device_write(device, *pos, buf, count); - *pos += result; } - return result; + return mask; } -int dfs_devfs_close(struct dfs_file *file) +static int dfs_devfs_flush(struct dfs_file *file) { - rt_err_t result = RT_EOK; + int ret = RT_EOK; rt_device_t device; RT_ASSERT(file != RT_NULL); - if (!S_ISDIR(file->vnode->mode)) + if (file->vnode && file->vnode->data) { /* get device handler */ device = (rt_device_t)file->vnode->data; - RT_ASSERT(device != RT_NULL); #ifdef RT_USING_POSIX_DEVIO - if (device->fops && device->fops->close) + if (device->fops && device->fops->flush) { - result = device->fops->close(file); + ret = device->fops->flush(file); } - else if (device->ops) -#else - if (device->ops) #endif /* RT_USING_POSIX_DEVIO */ - { - /* close device handler */ - result = rt_device_close(device); - } } - return result; + return ret; } -int dfs_devfs_open(struct dfs_file *file) +static off_t dfs_devfs_lseek(struct dfs_file *file, off_t offset, int wherece) { - rt_err_t result = RT_EOK; + off_t ret = 0; + rt_device_t device; - /* open root directory */ - if ((file->dentry->pathname[0] == '/' && file->dentry->pathname[1] == '\0') || - (S_ISDIR(file->vnode->mode))) - { - /* re-open the root directory for re-scan devices */ - _devfs_root_dirent_update(file->vnode); - return RT_EOK; - } - else + RT_ASSERT(file != RT_NULL); + + if (file->vnode && file->vnode->data) { - rt_device_t device = RT_NULL; + /* get device handler */ + device = (rt_device_t)file->vnode->data; - device = (struct rt_device *)file->vnode->data; - if (device) - { #ifdef RT_USING_POSIX_DEVIO - if (device->fops && device->fops->open) - { - result = device->fops->open(file); - if (result == RT_EOK || result == -RT_ENOSYS) - { - file->fops = &_dev_fops; - return RT_EOK; - } - } - else if (device->ops) -#else - if (device->ops) -#endif /* RT_USING_POSIX_DEVIO */ - { - result = rt_device_open(device, RT_DEVICE_OFLAG_RDWR); - if (result == RT_EOK || result == -RT_ENOSYS) - { - file->fops = &_dev_fops; - return RT_EOK; - } - } + if (device->fops && device->fops->lseek) + { + ret = device->fops->lseek(file, offset, wherece); } +#endif /* RT_USING_POSIX_DEVIO */ } - /* open device failed. */ - return -EIO; + return ret; } -int dfs_devfs_unlink(struct dfs_dentry *dentry) +static int dfs_devfs_truncate(struct dfs_file *file, off_t offset) { -#ifdef RT_USING_DEV_BUS + int ret = RT_EOK; rt_device_t device; - device = rt_device_find(&dentry->pathname[1]); - if (device == RT_NULL) - { - return -1; - } - if (device->type != RT_Device_Class_Bus) - { - return -1; - } - rt_device_bus_destroy(device); -#endif - return RT_EOK; -} - -int dfs_devfs_stat(struct dfs_dentry *dentry, struct stat *st) -{ - int ret = RT_EOK; - const char *path = RT_NULL; - struct dfs_vnode *vnode = RT_NULL; + RT_ASSERT(file != RT_NULL); - if (dentry && dentry->vnode) + if (file->vnode && file->vnode->data) { - path = dentry->pathname; - vnode = dentry->vnode; + /* get device handler */ + device = (rt_device_t)file->vnode->data; - /* stat root directory */ - if ((path[0] == '/') && (path[1] == '\0')) +#ifdef RT_USING_POSIX_DEVIO + if (device->fops && device->fops->truncate) { - st->st_dev = 0; - st->st_gid = vnode->gid; - st->st_uid = vnode->uid; - st->st_ino = 0; - st->st_mode = vnode->mode; - st->st_nlink = vnode->nlink; - st->st_size = vnode->size; - st->st_mtim.tv_nsec = vnode->mtime.tv_nsec; - st->st_mtim.tv_sec = vnode->mtime.tv_sec; - st->st_ctim.tv_nsec = vnode->ctime.tv_nsec; - st->st_ctim.tv_sec = vnode->ctime.tv_sec; - st->st_atim.tv_nsec = vnode->atime.tv_nsec; - st->st_atim.tv_sec = vnode->atime.tv_sec; - } - else - { - rt_device_t device; - - device = rt_device_find(&path[1]); - if (device != RT_NULL) - { - st->st_dev = 0; - st->st_gid = vnode->gid; - st->st_uid = vnode->uid; - st->st_ino = 0; - st->st_mode = vnode->mode; - st->st_nlink = vnode->nlink; - st->st_size = vnode->size; - st->st_mtim.tv_nsec = vnode->mtime.tv_nsec; - st->st_mtim.tv_sec = vnode->mtime.tv_sec; - st->st_ctim.tv_nsec = vnode->ctime.tv_nsec; - st->st_ctim.tv_sec = vnode->ctime.tv_sec; - st->st_atim.tv_nsec = vnode->atime.tv_nsec; - st->st_atim.tv_sec = vnode->atime.tv_sec; - } - else - { - ret = -ENOENT; - } + ret = device->fops->truncate(file, offset); } +#endif /* RT_USING_POSIX_DEVIO */ } return ret; } -int dfs_devfs_getdents(struct dfs_file *file, struct dirent *dirp, uint32_t count) +static int dfs_devfs_mmap(struct dfs_file *file, struct lwp_avl_struct *mmap) { - rt_uint32_t index; - rt_object_t object; - struct dirent *d; - struct device_dirent *root_dirent; - - root_dirent = (struct device_dirent *)file->vnode->data; - RT_ASSERT(root_dirent != RT_NULL); + int ret = RT_EOK; + rt_device_t device; - /* make integer count */ - count = (count / sizeof(struct dirent)); - if (count == 0) - return -EINVAL; + RT_ASSERT(file != RT_NULL); - for (index = 0; index < count && index + file->fpos < root_dirent->device_count; index ++) + if (file->vnode && file->vnode->data) { - object = (rt_object_t)root_dirent->devices[file->fpos + index]; - - d = dirp + index; - d->d_type = DT_REG; - d->d_namlen = RT_NAME_MAX; - d->d_reclen = (rt_uint16_t)sizeof(struct dirent); - rt_strncpy(d->d_name, object->name, RT_NAME_MAX); - d->d_name[RT_NAME_MAX] = '\0'; - } + /* get device handler */ + device = (rt_device_t)file->vnode->data; - file->fpos += index; +#ifdef RT_USING_POSIX_DEVIO + if (device->fops && device->fops->mmap) + { + ret = device->fops->mmap(file, mmap); + } +#endif /* RT_USING_POSIX_DEVIO */ + } - return index * sizeof(struct dirent); + return ret; } -static int dfs_devfs_poll(struct dfs_file *file, struct rt_pollreq *req) +static int dfs_devfs_lock(struct dfs_file *file, struct file_lock *flock) { - int mask = 0; + int ret = RT_EOK; rt_device_t device; - /* get device handler */ - device = (rt_device_t)file->vnode->data; - RT_ASSERT(device != RT_NULL); + RT_ASSERT(file != RT_NULL); -#ifdef RT_USING_POSIX_DEVIO - if (device->fops && device->fops->poll) + if (file->vnode && file->vnode->data) { - mask = device->fops->poll(file, req); - } + /* get device handler */ + device = (rt_device_t)file->vnode->data; + +#ifdef RT_USING_POSIX_DEVIO + if (device->fops && device->fops->lock) + { + ret = device->fops->lock(file, flock); + } #endif /* RT_USING_POSIX_DEVIO */ + } - return mask; + return ret; } -int dfs_devfs_flush(struct dfs_file *file) +static int dfs_devfs_flock(struct dfs_file *file, int operation, struct file_lock *flock) { - int ret = 0; + int ret = RT_EOK; rt_device_t device; - /* get device handler */ - device = (rt_device_t)file->vnode->data; - RT_ASSERT(device != RT_NULL); + RT_ASSERT(file != RT_NULL); -#ifdef RT_USING_POSIX_DEVIO - if (device->fops && device->fops->flush) + if (file->vnode && file->vnode->data) { - ret = device->fops->flush(file); - } + /* get device handler */ + device = (rt_device_t)file->vnode->data; + +#ifdef RT_USING_POSIX_DEVIO + if (device->fops && device->fops->flock) + { + ret = device->fops->flock(file, operation, flock); + } #endif /* RT_USING_POSIX_DEVIO */ + } return ret; } -off_t dfs_devfs_lseek(struct dfs_file *file, off_t offset, int wherece) +static const struct dfs_file_ops _dev_fops = { - off_t ret = 0; - rt_device_t device; + .open = dfs_devfs_open, + .close = dfs_devfs_close, + .lseek = generic_dfs_lseek, + .read = dfs_devfs_read, + .write = dfs_devfs_write, + .ioctl = dfs_devfs_ioctl, + .getdents = dfs_devfs_getdents, + .poll = dfs_devfs_poll, + + .flush = dfs_devfs_flush, + .lseek = dfs_devfs_lseek, + .truncate = dfs_devfs_truncate, + .mmap = dfs_devfs_mmap, + .lock = dfs_devfs_lock, + .flock = dfs_devfs_flock, +}; - /* get device handler */ - device = (rt_device_t)file->vnode->data; - RT_ASSERT(device != RT_NULL); +const struct dfs_file_ops *dfs_devfs_fops(void) +{ + return &_dev_fops; +} -#ifdef RT_USING_POSIX_DEVIO - if (device->fops && device->fops->lseek) +mode_t dfs_devfs_device_to_mode(struct rt_device *device) +{ + mode_t mode = 0; + + switch (device->type) { - ret = device->fops->lseek(file, offset, wherece); + case RT_Device_Class_Char: + mode = S_IFCHR | 0777; + break; + case RT_Device_Class_Block: + mode = S_IFBLK | 0777; + break; + case RT_Device_Class_Pipe: + mode = S_IFIFO | 0777; + break; + default: + mode = S_IFCHR | 0777; + break; } -#endif /* RT_USING_POSIX_DEVIO */ - return ret; + return mode; } -int dfs_devfs_truncate(struct dfs_file *file, off_t offset) +static void dfs_devfs_mkdir(const char *fullpath, mode_t mode) { - int ret = 0; - rt_device_t device; - - /* get device handler */ - device = (rt_device_t)file->vnode->data; - RT_ASSERT(device != RT_NULL); + int len = rt_strlen(fullpath); + char *path = (char *)rt_malloc(len); -#ifdef RT_USING_POSIX_DEVIO - if (device->fops && device->fops->truncate) + if (path) { - ret = device->fops->truncate(file, offset); - } -#endif /* RT_USING_POSIX_DEVIO */ + int index = len - 1; - return ret; -} + rt_strcpy(path, fullpath); -int dfs_devfs_mmap(struct dfs_file *file, struct lwp_avl_struct *mmap) -{ - int ret = 0; - rt_device_t device; + if (path[index] == '/') + { + path[index] = '\0'; + index --; + } - /* get device handler */ - device = (rt_device_t)file->vnode->data; - RT_ASSERT(device != RT_NULL); + while (path[index] != '/' && index >= 0) + { + index --; + } -#ifdef RT_USING_POSIX_DEVIO - if (device->fops && device->fops->mmap) - { - ret = device->fops->mmap(file, mmap); - } -#endif /* RT_USING_POSIX_DEVIO */ + path[index] = '\0'; - return ret; -} + if (index > 0 && access(path, 0) != 0) + { + int i = 0; -int dfs_devfs_lock(struct dfs_file *file, struct file_lock *flock) -{ - int ret = 0; - rt_device_t device; + if (path[i] == '/') + { + i ++; + } + + while (index > i) + { + if (path[i] == '/') + { + path[i] = '\0'; + mkdir(path, mode); + path[i] = '/'; + } - /* get device handler */ - device = (rt_device_t)file->vnode->data; - RT_ASSERT(device != RT_NULL); + i ++; + } -#ifdef RT_USING_POSIX_DEVIO - if (device->fops && device->fops->lock) - { - ret = device->fops->lock(file, flock); + mkdir(path, mode); + } } -#endif /* RT_USING_POSIX_DEVIO */ - - return ret; } -int dfs_devfs_flock(struct dfs_file *file, int operation, struct file_lock *flock) +void dfs_devfs_device_add(rt_device_t device) { - int ret = 0; - rt_device_t device; - - /* get device handler */ - device = (rt_device_t)file->vnode->data; - RT_ASSERT(device != RT_NULL); + int fd; + char path[512]; -#ifdef RT_USING_POSIX_DEVIO - if (device->fops && device->fops->flock) + if (device) { - ret = device->fops->flock(file, operation, flock); - } -#endif /* RT_USING_POSIX_DEVIO */ + rt_snprintf(path, 512, "/dev/%s", device->parent.name); - return ret; + if (access(path, 0) != 0) + { + mode_t mode = dfs_devfs_device_to_mode(device); + + dfs_devfs_mkdir(path, mode); + + fd = open(path, O_RDWR | O_CREAT, mode); + if (fd >= 0) + { + close(fd); + } + } + } } -int dfs_devfs_init(void) +int dfs_devfs_update(void) { - /* register devfs file system */ - dfs_register(&_devfs); + int count = rt_object_get_length(RT_Object_Class_Device); + if (count > 0) + { + rt_device_t *devices = rt_malloc(count * sizeof(rt_device_t)); + if (devices) + { + rt_object_get_pointers(RT_Object_Class_Device, (rt_object_t *)devices, count); - dfs_mount(RT_NULL, "/dev", "devfs", 0, RT_NULL); + for (int index = 0; index < count; index ++) + { + dfs_devfs_device_add(devices[index]); + } + rt_free(devices); + } + } - return 0; + return count; } -INIT_COMPONENT_EXPORT(dfs_devfs_init); - diff --git a/components/dfs/dfs_v2/filesystems/devfs/devfs.h b/components/dfs/dfs_v2/filesystems/devfs/devfs.h index acaae11f2f5..e80b44ee091 100644 --- a/components/dfs/dfs_v2/filesystems/devfs/devfs.h +++ b/components/dfs/dfs_v2/filesystems/devfs/devfs.h @@ -10,6 +10,9 @@ #ifndef __DEVICE_FS_H__ #define __DEVICE_FS_H__ -int dfs_devfs_init(void); +const struct dfs_file_ops *dfs_devfs_fops(void); +mode_t dfs_devfs_device_to_mode(struct rt_device *device); +void dfs_devfs_device_add(rt_device_t device); +int dfs_devfs_update(void); #endif diff --git a/components/dfs/dfs_v2/filesystems/devfs/devtmpfs.c b/components/dfs/dfs_v2/filesystems/devfs/devtmpfs.c new file mode 100644 index 00000000000..3bea0c16dfa --- /dev/null +++ b/components/dfs/dfs_v2/filesystems/devfs/devtmpfs.c @@ -0,0 +1,678 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-24 flybreak the first version + * 2023-02-01 xqyjlj fix cannot open the same file repeatedly in 'w' mode + * 2023-09-20 zmq810150896 adds truncate functionality and standardized unlink adaptations + * 2023-12-02 Shell Support of dynamic device + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define TMPFS_MAGIC 0x0B0B0B0B +#define TMPFS_TYPE_FILE 0x00 +#define TMPFS_TYPE_DIR 0x01 +#define TMPFS_TYPE_DYN_DEV 0x02 /* dynamic device */ + +struct devtmpfs_sb; + +struct devtmpfs_file +{ + char name[DIRENT_NAME_MAX]; /* file name */ + + rt_uint32_t type; /* file type */ + rt_list_t subdirs; /* file subdir list */ + rt_list_t sibling; /* file sibling list */ + + struct devtmpfs_sb *sb; /* superblock ptr */ + + rt_uint32_t mode; + char *link; +}; + +struct devtmpfs_sb +{ + rt_uint32_t magic; /* TMPFS_MAGIC */ + struct devtmpfs_file root; /* root dir */ + rt_size_t df_size; /* df size */ + rt_list_t sibling; /* sb sibling list */ + struct rt_spinlock lock; /* tmpfs lock */ +}; + +static struct dfs_file_ops _default_fops = { 0 }; + +static int _path_separate(const char *path, char *parent_path, char *file_name) +{ + const char *path_p, *path_q; + + RT_ASSERT(path[0] == '/'); + + file_name[0] = '\0'; + path_p = path_q = &path[1]; +__next_dir: + while (*path_q != '/' && *path_q != '\0') + { + path_q++; + } + if (path_q != path_p) /*sub dir*/ + { + if (*path_q != '\0') + { + path_q++; + path_p = path_q; + goto __next_dir; + } + else /* Last level dir */ + { + rt_memcpy(parent_path, path, path_p - path - 1); + parent_path[path_p - path - 1] = '\0'; + rt_memcpy(file_name, path_p, path_q - path_p); + file_name[path_q - path_p] = '\0'; + } + } + if (parent_path[0] == 0) + { + parent_path[0] = '/'; + parent_path[1] = '\0'; + } + //LOG_D("parent_path: %s", parent_path); + //LOG_D("file_name: %s", file_name); + + return 0; +} + +static int _get_subdir(const char *path, char *name) +{ + const char *subpath = path; + while (*subpath == '/' && *subpath) + subpath ++; + while (*subpath != '/' && *subpath) + { + *name = *subpath; + name ++; + subpath ++; + } + return 0; +} + +#if 0 +static int _free_subdir(struct devtmpfs_file *dfile) +{ + struct devtmpfs_file *file; + rt_list_t *list, *temp_list; + struct devtmpfs_sb *superblock; + + RT_ASSERT(dfile->type == TMPFS_TYPE_DIR); + + rt_list_for_each_safe(list, temp_list, &dfile->subdirs) + { + file = rt_list_entry(list, struct devtmpfs_file, sibling); + if (file->type == TMPFS_TYPE_DIR) + { + _free_subdir(file); + } + + if (file->link) + { + rt_free(file->link); + } + + superblock = file->sb; + RT_ASSERT(superblock); + + rt_spin_lock(&superblock->lock); + rt_list_remove(&(file->sibling)); + rt_spin_unlock(&superblock->lock); + + rt_free(file); + } + return 0; +} +#endif + +static int devtmpfs_mount(struct dfs_mnt *mnt, unsigned long rwflag, const void *data) +{ + struct devtmpfs_sb *superblock; + + superblock = rt_calloc(1, sizeof(struct devtmpfs_sb)); + if (superblock) + { + superblock->df_size = sizeof(struct devtmpfs_sb); + superblock->magic = TMPFS_MAGIC; + rt_list_init(&superblock->sibling); + + superblock->root.name[0] = '/'; + superblock->root.sb = superblock; + superblock->root.type = TMPFS_TYPE_DIR; + superblock->root.mode = S_IFDIR | (S_IRUSR | S_IRGRP | S_IROTH) | (S_IXUSR | S_IXGRP | S_IXOTH); + rt_list_init(&superblock->root.sibling); + rt_list_init(&superblock->root.subdirs); + + rt_spin_lock_init(&superblock->lock); + + mnt->data = superblock; + } + else + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static int devtmpfs_unmount(struct dfs_mnt *mnt) +{ +#if 0 + struct devtmpfs_sb *superblock; + + /* FIXME: don't unmount on busy. */ + superblock = (struct devtmpfs_sb *)mnt->data; + RT_ASSERT(superblock != NULL); + + mnt->data = NULL; + _free_subdir(&(superblock->root)); + rt_free(superblock); +#endif + return -RT_ERROR; +} + +static struct devtmpfs_file *devtmpfs_file_lookup(struct devtmpfs_sb *superblock, const char *path) +{ + const char *subpath, *curpath, *filename = RT_NULL; + char subdir_name[DIRENT_NAME_MAX]; + struct devtmpfs_file *file, *curfile; + rt_list_t *list; + + subpath = path; + while (*subpath == '/' && *subpath) + subpath ++; + + if (! *subpath) /* is root directory */ + { + return &(superblock->root); + } + + curpath = subpath; + curfile = &superblock->root; + +find_subpath: + while (*subpath != '/' && *subpath) + subpath ++; + + if (! *subpath) /* is last directory */ + filename = curpath; + else + subpath ++; /* skip '/' */ + + memset(subdir_name, 0, DIRENT_NAME_MAX); + _get_subdir(curpath, subdir_name); + + rt_spin_lock(&superblock->lock); + + rt_list_for_each(list, &curfile->subdirs) + { + file = rt_list_entry(list, struct devtmpfs_file, sibling); + if (filename) /* find file */ + { + if (rt_strcmp(file->name, filename) == 0) + { + rt_spin_unlock(&superblock->lock); + return file; + } + } + else if (rt_strcmp(file->name, subdir_name) == 0) + { + curpath = subpath; + curfile = file; + rt_spin_unlock(&superblock->lock); + goto find_subpath; + } + } + rt_spin_unlock(&superblock->lock); + /* not found */ + return NULL; +} + +static int devtmpfs_statfs(struct dfs_mnt *mnt, struct statfs *buf) +{ + struct devtmpfs_sb *superblock; + + RT_ASSERT(mnt != NULL); + RT_ASSERT(buf != NULL); + + superblock = (struct devtmpfs_sb *)mnt->data; + RT_ASSERT(superblock != NULL); + + buf->f_bsize = 512; + buf->f_blocks = (superblock->df_size + 511) / 512; + buf->f_bfree = 1; + buf->f_bavail = buf->f_bfree; + + return RT_EOK; +} + +static int devtmpfs_stat(struct dfs_dentry *dentry, struct stat *st) +{ + struct dfs_vnode *vnode; + + if (dentry && dentry->vnode) + { + vnode = dentry->vnode; + + st->st_dev = (dev_t)(long)(dentry->mnt->dev_id); + st->st_ino = (ino_t)dfs_dentry_full_path_crc32(dentry); + + st->st_gid = vnode->gid; + st->st_uid = vnode->uid; + st->st_mode = vnode->mode; + st->st_nlink = vnode->nlink; + st->st_size = vnode->size; + st->st_mtim.tv_nsec = vnode->mtime.tv_nsec; + st->st_mtim.tv_sec = vnode->mtime.tv_sec; + st->st_ctim.tv_nsec = vnode->ctime.tv_nsec; + st->st_ctim.tv_sec = vnode->ctime.tv_sec; + st->st_atim.tv_nsec = vnode->atime.tv_nsec; + st->st_atim.tv_sec = vnode->atime.tv_sec; + } + + return RT_EOK; +} + +static int devtmpfs_getdents(struct dfs_file *file, struct dirent *dirp, uint32_t count) +{ + struct devtmpfs_file *d_file; + struct devtmpfs_sb *superblock; + + RT_ASSERT(file); + RT_ASSERT(file->dentry); + RT_ASSERT(file->dentry->mnt); + + superblock = (struct devtmpfs_sb *)file->dentry->mnt->data; + RT_ASSERT(superblock); + + d_file = devtmpfs_file_lookup(superblock, file->dentry->pathname); + if (d_file) + { + rt_size_t index, end; + struct dirent *d; + struct devtmpfs_file *n_file; + rt_list_t *list; + + /* make integer count */ + count = (count / sizeof(struct dirent)); + if (count == 0) + { + return -EINVAL; + } + + end = file->fpos + count; + index = 0; + count = 0; + + rt_list_for_each(list, &d_file->subdirs) + { + if (index >= (rt_size_t)file->fpos) + { + n_file = rt_list_entry(list, struct devtmpfs_file, sibling); + + d = dirp + count; + if (n_file->type == TMPFS_TYPE_FILE) + { + d->d_type = DT_REG; + } + if (n_file->type == TMPFS_TYPE_DIR) + { + d->d_type = DT_DIR; + } + + d->d_reclen = (rt_uint16_t)sizeof(struct dirent); + rt_strncpy(d->d_name, n_file->name, DIRENT_NAME_MAX); + d->d_namlen = rt_strlen(d->d_name); + + count += 1; + file->fpos += 1; + } + index += 1; + if (index >= end) + { + break; + } + } + } + + return count * sizeof(struct dirent); +} + +static int devtmpfs_symlink(struct dfs_dentry *parent_dentry, const char *target, const char *linkpath) +{ + int ret = RT_EOK; + struct devtmpfs_file *p_file, *l_file; + struct devtmpfs_sb *superblock; + + RT_ASSERT(parent_dentry); + RT_ASSERT(parent_dentry->mnt); + + superblock = (struct devtmpfs_sb *)parent_dentry->mnt->data; + RT_ASSERT(superblock); + + p_file = devtmpfs_file_lookup(superblock, parent_dentry->pathname); + if (p_file) + { + l_file = (struct devtmpfs_file *)rt_calloc(1, sizeof(struct devtmpfs_file)); + if (l_file) + { + superblock->df_size += sizeof(struct devtmpfs_file); + + strncpy(l_file->name, linkpath, DIRENT_NAME_MAX - 1); + + rt_list_init(&(l_file->subdirs)); + rt_list_init(&(l_file->sibling)); + l_file->sb = superblock; + l_file->type = TMPFS_TYPE_FILE; + l_file->mode = p_file->mode; + l_file->mode &= ~S_IFMT; + l_file->mode |= S_IFLNK; + l_file->link = rt_strdup(target); + + rt_spin_lock(&superblock->lock); + rt_list_insert_after(&(p_file->subdirs), &(l_file->sibling)); + rt_spin_unlock(&superblock->lock); + } + } + + return ret; +} + +static int devtmpfs_readlink(struct dfs_dentry *dentry, char *buf, int len) +{ + int ret = 0; + struct devtmpfs_file *d_file; + struct devtmpfs_sb *superblock; + + RT_ASSERT(dentry); + RT_ASSERT(dentry->mnt); + + superblock = (struct devtmpfs_sb *)dentry->mnt->data; + RT_ASSERT(superblock); + + d_file = devtmpfs_file_lookup(superblock, dentry->pathname); + if (d_file) + { + if (d_file->link) + { + if (d_file->type == TMPFS_TYPE_DYN_DEV) + { + rt_device_t device = (void *)d_file->link; + buf[0] = '\0'; + ret = device->readlink(device, buf, len); + if (ret == 0) + { + buf[len - 1] = '\0'; + ret = rt_strlen(buf); + } + else + { + ret = 0; + } + } + else + { + rt_strncpy(buf, (const char *)d_file->link, len); + buf[len - 1] = '\0'; + ret = rt_strlen(buf); + } + } + } + + return ret; +} + +static int devtmpfs_unlink(struct dfs_dentry *dentry) +{ + struct devtmpfs_file *d_file; + struct devtmpfs_sb *superblock; + + RT_ASSERT(dentry); + RT_ASSERT(dentry->mnt); + + superblock = (struct devtmpfs_sb *)dentry->mnt->data; + RT_ASSERT(superblock); + + d_file = devtmpfs_file_lookup(superblock, dentry->pathname); + if (d_file) + { + if (d_file->link && d_file->type != TMPFS_TYPE_DYN_DEV) + { + rt_free(d_file->link); + } + + rt_spin_lock(&superblock->lock); + rt_list_remove(&(d_file->sibling)); + rt_spin_unlock(&superblock->lock); + + rt_free(d_file); + } + + return RT_EOK; +} + +static int devtmpfs_setattr(struct dfs_dentry *dentry, struct dfs_attr *attr) +{ + struct devtmpfs_file *d_file; + struct devtmpfs_sb *superblock; + + RT_ASSERT(dentry); + RT_ASSERT(dentry->mnt); + + superblock = (struct devtmpfs_sb *)dentry->mnt->data; + RT_ASSERT(superblock); + + d_file = devtmpfs_file_lookup(superblock, dentry->pathname); + if (d_file) + { + d_file->mode &= ~0xFFF; + d_file->mode |= attr->st_mode & 0xFFF; + return RT_EOK; + } + + return -RT_ERROR; +} + +static struct dfs_vnode *devtmpfs_create_vnode(struct dfs_dentry *dentry, int type, mode_t mode) +{ + struct dfs_vnode *vnode = RT_NULL; + struct devtmpfs_sb *superblock; + struct devtmpfs_file *d_file, *p_file; + char parent_path[DFS_PATH_MAX], file_name[DIRENT_NAME_MAX]; + + if (dentry == NULL || dentry->mnt == NULL || dentry->mnt->data == NULL) + { + return NULL; + } + + superblock = (struct devtmpfs_sb *)dentry->mnt->data; + RT_ASSERT(superblock != NULL); + + vnode = dfs_vnode_create(); + if (vnode) + { + /* find parent file */ + _path_separate(dentry->pathname, parent_path, file_name); + if (file_name[0] == '\0') /* it's root dir */ + { + dfs_vnode_destroy(vnode); + return NULL; + } + + /* open parent directory */ + p_file = devtmpfs_file_lookup(superblock, parent_path); + if (p_file == NULL) + { + dfs_vnode_destroy(vnode); + return NULL; + } + + /* create a file entry */ + d_file = (struct devtmpfs_file *)rt_calloc(1, sizeof(struct devtmpfs_file)); + if (d_file == NULL) + { + dfs_vnode_destroy(vnode); + return NULL; + } + + superblock->df_size += sizeof(struct devtmpfs_file); + + strncpy(d_file->name, file_name, DIRENT_NAME_MAX); + + rt_list_init(&(d_file->subdirs)); + rt_list_init(&(d_file->sibling)); + d_file->sb = superblock; + + vnode->nlink = 1; + vnode->size = 0; + vnode->mode = mode; + vnode->mnt = dentry->mnt; + vnode->fops = &_default_fops; + + if (type == FT_DIRECTORY) + { + d_file->type = TMPFS_TYPE_DIR; + vnode->type = FT_DIRECTORY; + vnode->mode &= ~S_IFMT; + vnode->mode |= S_IFDIR; + } + else + { + d_file->type = TMPFS_TYPE_FILE; + vnode->type = FT_DEVICE; + } + + d_file->mode = vnode->mode; + + rt_spin_lock(&superblock->lock); + rt_list_insert_after(&(p_file->subdirs), &(d_file->sibling)); + rt_spin_unlock(&superblock->lock); + } + + return vnode; +} + +static struct dfs_vnode *devtmpfs_lookup(struct dfs_dentry *dentry) +{ + struct dfs_vnode *vnode = RT_NULL; + struct devtmpfs_sb *superblock; + struct devtmpfs_file *d_file; + + if (dentry == NULL || dentry->mnt == NULL || dentry->mnt->data == NULL) + { + return NULL; + } + + superblock = (struct devtmpfs_sb *)dentry->mnt->data; + + d_file = devtmpfs_file_lookup(superblock, dentry->pathname); + if (d_file) + { + vnode = dfs_vnode_create(); + if (vnode) + { + vnode->nlink = 1; + vnode->size = 0; + vnode->mnt = dentry->mnt; + vnode->fops = &_default_fops; + vnode->mode = d_file->mode; + + if (d_file->type == TMPFS_TYPE_DIR) + { + vnode->type = FT_DIRECTORY; + } + else if (d_file->link) + { + vnode->type = FT_SYMLINK; + } + else + { + vnode->type = FT_DEVICE; + } + } + } + else + { + rt_device_t device = RT_NULL; + + device = rt_device_find(&dentry->pathname[1]); + if (device) + { + vnode = devtmpfs_create_vnode(dentry, FT_REGULAR, dfs_devfs_device_to_mode(device)); + if (device->flag & RT_DEVICE_FLAG_DYNAMIC) + { + d_file = devtmpfs_file_lookup(superblock, dentry->pathname); + d_file->type = TMPFS_TYPE_DYN_DEV; + d_file->link = (char *)device; + } + } + } + + return vnode; +} + +static int devtmpfs_free_vnode(struct dfs_vnode *vnode) +{ + return RT_EOK; +} + +static const struct dfs_filesystem_ops _devtmpfs_ops = +{ + .name = "devtmpfs", + .flags = DFS_FS_FLAG_DEFAULT, + .default_fops = &_default_fops, + + .mount = devtmpfs_mount, + .umount = devtmpfs_unmount, + + .symlink = devtmpfs_symlink, + .readlink = devtmpfs_readlink, + + .unlink = devtmpfs_unlink, + .setattr = devtmpfs_setattr, + + .statfs = devtmpfs_statfs, + .stat = devtmpfs_stat, + + .lookup = devtmpfs_lookup, + .create_vnode = devtmpfs_create_vnode, + .free_vnode = devtmpfs_free_vnode +}; + +static struct dfs_filesystem_type _devtmpfs = +{ + .fs_ops = &_devtmpfs_ops, +}; + +int dfs_devtmpfs_init(void) +{ + _default_fops = *dfs_devfs_fops(); + _default_fops.getdents = devtmpfs_getdents; + + /* register file system */ + dfs_register(&_devtmpfs); + + dfs_mount(RT_NULL, "/dev", "devtmpfs", 0, RT_NULL); + dfs_devfs_update(); + + return 0; +} +INIT_COMPONENT_EXPORT(dfs_devtmpfs_init); diff --git a/components/dfs/dfs_v2/filesystems/mqueue/dfs_mqueue.c b/components/dfs/dfs_v2/filesystems/mqueue/dfs_mqueue.c index 70b34ef3cb2..4546455a31e 100644 --- a/components/dfs/dfs_v2/filesystems/mqueue/dfs_mqueue.c +++ b/components/dfs/dfs_v2/filesystems/mqueue/dfs_mqueue.c @@ -145,7 +145,7 @@ static struct dfs_vnode *dfs_mqueue_create_vnode(struct dfs_dentry *dentry, int } mq_file->msg_size = 8192; mq_file->max_msgs = 10; - strncpy(mq_file->name, dentry->pathname + 1, RT_NAME_MAX); + strncpy(mq_file->name, dentry->pathname + 1, RT_NAME_MAX - 1); dfs_mqueue_insert_after(&(mq_file->list)); } diff --git a/components/dfs/dfs_v2/filesystems/ptyfs/README.md b/components/dfs/dfs_v2/filesystems/ptyfs/README.md new file mode 100644 index 00000000000..1f805df80c9 --- /dev/null +++ b/components/dfs/dfs_v2/filesystems/ptyfs/README.md @@ -0,0 +1,5 @@ +# The Pseudo Terminal Filesystem + +The device register on ptyfs is also registered in device frameworks with `rt_device_register()`. + +It's possible to mount a new ptyfs instance on another path. Each instance is isolated to each other. And they don't share the id system. But generally speaking, you have to mount the ptyfs on `/dev` root, since all the file nodes in ptyfs are devices. diff --git a/components/dfs/dfs_v2/filesystems/ptyfs/SConscript b/components/dfs/dfs_v2/filesystems/ptyfs/SConscript new file mode 100644 index 00000000000..c0f8f395877 --- /dev/null +++ b/components/dfs/dfs_v2/filesystems/ptyfs/SConscript @@ -0,0 +1,11 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Filesystem', src, depend = ['RT_USING_DFS', 'RT_USING_DFS_PTYFS'], CPPPATH = CPPPATH) + +Return('group') diff --git a/components/dfs/dfs_v2/filesystems/ptyfs/ptyfs.c b/components/dfs/dfs_v2/filesystems/ptyfs/ptyfs.c new file mode 100644 index 00000000000..c6f4f3d52d2 --- /dev/null +++ b/components/dfs/dfs_v2/filesystems/ptyfs/ptyfs.c @@ -0,0 +1,658 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-12-02 Shell init ver. + */ +#define DBG_TAG "filesystem.ptyfs" +#define DBG_LVL DBG_INFO +#include + +#include "ptyfs.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifndef S_IRWXUGO +#define S_IRWXUGO (S_IRWXU | S_IRWXG | S_IRWXO) +#endif /* S_IRWXUGO */ +#ifndef S_IALLUGO +#define S_IALLUGO (S_ISUID | S_ISGID | S_ISVTX | S_IRWXUGO) +#endif /* S_IALLUGO */ +#ifndef S_IRUGO +#define S_IRUGO (S_IRUSR | S_IRGRP | S_IROTH) +#endif /* S_IRUGO */ +#ifndef S_IWUGO +#define S_IWUGO (S_IWUSR | S_IWGRP | S_IWOTH) +#endif /* S_IWUGO */ +#ifndef S_IXUGO +#define S_IXUGO (S_IXUSR | S_IXGRP | S_IXOTH) +#endif /* S_IXUGO */ + +#define PTYFS_MAGIC 0x9D94A07D +#define PTYFS_TYPE_DIR 0x00 +#define PTYFS_TYPE_FILE_PTMX 0x01 +#define PTYFS_TYPE_FILE_SLAVE 0x02 + +/* TODO: using Symbolic permission, but not ours */ +#define PTMX_DEFAULT_FILE_MODE (S_IFCHR | 0666) +#define PTS_DEFAULT_FILE_MODE (S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP) +#define ROOT_DEFUALT_FILE_MODE (S_IFDIR | S_IRUGO | S_IXUGO | S_IWUSR) + +struct ptyfs_sb; + +struct ptyfs_file +{ + char basename[DIRENT_NAME_MAX]; /* file name */ + rt_uint32_t mode; /* file modes allowed */ + rt_uint32_t type; /* file type */ + rt_list_t subdirs; /* file subdir list */ + rt_list_t ent_node; /* entry node in subdir list */ + struct ptyfs_sb *sb; /* superblock ptr */ + rt_device_t device; /* device binding on this file */ +}; + +struct ptyfs_sb +{ + struct rt_device ptmx_device; /* ptmx device */ + struct rt_mutex lock; /* tmpfs lock */ + struct ptyfs_file root_file; /* root dir */ + struct ptyfs_file ptmx_file; /* `/ptmx` file */ + struct rid_bitmap ptsno_pool; /* pts number pool */ + rt_uint32_t magic; /* PTYFS_MAGIC */ + rt_size_t df_size; /* df size */ + rt_list_t sibling; /* sb sibling list */ + struct dfs_mnt *mount; /* mount data */ + + /** + * Note: This upper limit is set to protect kernel memory from draining + * out by the application if it keeps allocating pty devices. + * + * Still, current implementation of bitmap can not efficiently use the + * memory + */ + rt_bitmap_t + ptsno_pool_bitset[LWP_PTY_MAX_PARIS_LIMIT / (sizeof(rt_bitmap_t) * 8)]; +}; + +static struct dfs_file_ops _default_fops; + +static int _split_out_subdir(const char *path, char *name) +{ + const char *subpath = path; + + while (*subpath == '/' && *subpath) + { + subpath++; + } + + while (*subpath != '/' && *subpath) + { + *name++ = *subpath++; + } + + *name = '\0'; + return 0; +} + +static rt_err_t ptyfile_init(struct ptyfs_file *file, struct ptyfs_sb *sb, + const char *name, rt_uint32_t type, + rt_uint32_t mode, rt_device_t device) +{ + if (name) + strncpy(file->basename, name, sizeof(file->basename)); + + file->type = type; + file->mode = mode; + rt_list_init(&file->subdirs); + rt_list_init(&file->ent_node); + file->sb = sb; + file->device = device; + + return 0; +} + +static rt_err_t ptyfile_add_to_root(struct ptyfs_sb *sb, + struct ptyfs_file *new_file) +{ + struct ptyfs_file *root_file = &sb->root_file; + + /* update super block */ + sb->df_size += sizeof(struct ptyfs_file); + + rt_mutex_take(&sb->lock, RT_WAITING_FOREVER); + rt_list_insert_after(&(root_file->subdirs), &(new_file->ent_node)); + rt_mutex_release(&sb->lock); + + return 0; +} + +static rt_err_t ptyfile_remove_from_root(struct ptyfs_sb *sb, + struct ptyfs_file *rm_file) +{ + /* update super block */ + sb->df_size -= sizeof(struct ptyfs_file); + + rt_mutex_take(&sb->lock, RT_WAITING_FOREVER); + rt_list_remove(&(rm_file->ent_node)); + rt_mutex_release(&sb->lock); + + return 0; +} + +static struct ptyfs_file *ptyfile_lookup(struct ptyfs_sb *superblock, + const char *path) +{ + const char *subpath_iter, *curpath_iter, *basename = RT_NULL; + char subdir_name[DIRENT_NAME_MAX]; + struct ptyfs_file *curfile, *found_file = RT_NULL; + rt_list_t *list; + int do_path_resolve = 1; + + subpath_iter = path; + + /* skip starting "/" */ + while (*subpath_iter == '/') subpath_iter++; + if (!*subpath_iter) + { + return &(superblock->root_file); + } + + curpath_iter = subpath_iter; + curfile = &superblock->root_file; + + /* resolve chain of files splited from path one by one */ + while (do_path_resolve) + { + do_path_resolve = 0; + + /* splitout sub-directory or basename */ + while (*subpath_iter != '/' && *subpath_iter) subpath_iter++; + if (!*subpath_iter) + { + basename = curpath_iter; + } + else + { + _split_out_subdir(curpath_iter, subdir_name); + + /* skip "/" for next search */ + subpath_iter++; + } + + rt_mutex_take(&superblock->lock, RT_WAITING_FOREVER); + rt_list_for_each(list, &curfile->subdirs) + { + struct ptyfs_file *file_iter; + file_iter = rt_list_entry(list, struct ptyfs_file, ent_node); + if (basename) + { + if (strcmp(file_iter->basename, basename) == 0) + { + found_file = file_iter; + break; + } + } + else if (strcmp(file_iter->basename, subdir_name) == 0) + { + curpath_iter = subpath_iter; + curfile = file_iter; + do_path_resolve = 1; + break; + } + } + rt_mutex_release(&superblock->lock); + } + + return found_file; +} + +const char *ptyfs_get_rootpath(rt_device_t ptmx) +{ + const char *rc; + struct ptyfs_sb *sb; + /* allocate id for it and register file */ + sb = rt_container_of(ptmx, struct ptyfs_sb, ptmx_device); + if (sb->magic != PTYFS_MAGIC) + { + rc = 0; + } + else + { + /* fullpath is always started with /dev/ */ + return sb->mount->fullpath + 5; + } + + return rc; +} + +ptsno_t ptyfs_register_pts(rt_device_t ptmx, rt_device_t pts) +{ + ptsno_t rc; + struct ptyfs_sb *sb; + struct ptyfs_file *pts_file; + struct rid_bitmap *ptsno_pool; + + /* allocate id for it and register file */ + sb = rt_container_of(ptmx, struct ptyfs_sb, ptmx_device); + if (sb->magic != PTYFS_MAGIC) + { + rc = -1; + } + else + { + ptsno_pool = &sb->ptsno_pool; + rc = rid_bitmap_get(ptsno_pool); + if (rc >= 0) + { + pts_file = rt_calloc(1, sizeof(struct ptyfs_file)); + if (pts_file) + { + snprintf(pts_file->basename, DIRENT_NAME_MAX, "%lu", rc); + ptyfile_init(pts_file, sb, 0, PTYFS_TYPE_FILE_SLAVE, + PTS_DEFAULT_FILE_MODE, pts); + ptyfile_add_to_root(sb, pts_file); + } + else + { + rid_bitmap_put(ptsno_pool, rc); + rc = -1; + } + } + /* else rc == -1 */ + } + + return rc; +} + +rt_err_t ptyfs_unregister_pts(rt_device_t ptmx, ptsno_t ptsno) +{ + ptsno_t rc; + struct ptyfs_sb *sb; + struct ptyfs_file *pts_file; + struct rid_bitmap *ptsno_pool; + char path_buf[DIRENT_NAME_MAX]; + + /* allocate id for it and register file */ + sb = rt_container_of(ptmx, struct ptyfs_sb, ptmx_device); + if (sb->magic != PTYFS_MAGIC || ptsno < 0) + { + rc = -EINVAL; + } + else + { + /* get path and findout device */ + snprintf(path_buf, sizeof(path_buf), "%lu", ptsno); + pts_file = ptyfile_lookup(sb, path_buf); + if (pts_file) + { + ptyfile_remove_from_root(sb, pts_file); + ptsno_pool = &sb->ptsno_pool; + rid_bitmap_put(ptsno_pool, ptsno); + rc = 0; + } + else + { + rc = -ENOENT; + } + } + + return rc; +} + +#define DEVFS_PREFIX "/dev/" +#define DEVFS_PREFIX_LEN (sizeof(DEVFS_PREFIX) - 1) + +/** + * Create an new instance of ptyfs, and mount on target point + * 2 basic files are created: root, ptmx. + * + * todo: support of mount options? + */ +static int ptyfs_ops_mount(struct dfs_mnt *mnt, unsigned long rwflag, + const void *data) +{ + struct ptyfs_sb *sb; + rt_device_t ptmx_device; + rt_err_t rc; + + if (strncmp(mnt->fullpath, DEVFS_PREFIX, DEVFS_PREFIX_LEN) != 0) + { + LOG_I("%s() Not mounted on `/dev/'", __func__); + return -EINVAL; + } + + sb = rt_calloc(1, sizeof(struct ptyfs_sb)); + if (sb) + { + rt_mutex_init(&sb->lock, "ptyfs", RT_IPC_FLAG_PRIO); + + /* setup the ptmx device */ + ptmx_device = &sb->ptmx_device; + rc = lwp_ptmx_init(ptmx_device, mnt->fullpath + DEVFS_PREFIX_LEN); + if (rc == RT_EOK) + { + /* setup 2 basic files */ + ptyfile_init(&sb->root_file, sb, "/", PTYFS_TYPE_DIR, + ROOT_DEFUALT_FILE_MODE, 0); + ptyfile_init(&sb->ptmx_file, sb, "ptmx", PTYFS_TYPE_FILE_PTMX, + PTMX_DEFAULT_FILE_MODE, ptmx_device); + ptyfile_add_to_root(sb, &sb->ptmx_file); + + /* setup rid */ + rid_bitmap_init(&sb->ptsno_pool, 0, LWP_PTY_MAX_PARIS_LIMIT, + sb->ptsno_pool_bitset, &sb->lock); + + /* setup properties and members */ + sb->magic = PTYFS_MAGIC; + + sb->df_size = sizeof(struct ptyfs_sb); + rt_list_init(&sb->sibling); + + /* binding superblocks and mount point */ + mnt->data = sb; + sb->mount = mnt; + rc = 0; + } + /* else just return rc */ + } + else + { + rc = -ENOMEM; + } + + return rc; +} + +static int ptyfs_ops_umount(struct dfs_mnt *mnt) +{ + /* Not supported yet */ + return -1; +} + +static int ptyfs_ops_setattr(struct dfs_dentry *dentry, struct dfs_attr *attr) +{ + struct ptyfs_file *pty_file; + struct ptyfs_sb *superblock; + + RT_ASSERT(dentry); + RT_ASSERT(dentry->mnt); + + superblock = (struct ptyfs_sb *)dentry->mnt->data; + RT_ASSERT(superblock); + + /* find the device related to current pts slave device */ + pty_file = ptyfile_lookup(superblock, dentry->pathname); + if (pty_file && pty_file->type == PTYFS_TYPE_FILE_SLAVE) + { + pty_file->mode &= ~0xFFF; + pty_file->mode |= attr->st_mode & 0xFFF; + return 0; + } + + return -1; +} + +#define OPTIMAL_BSIZE 1024 + +static int ptyfs_ops_statfs(struct dfs_mnt *mnt, struct statfs *buf) +{ + struct ptyfs_sb *superblock; + + RT_ASSERT(mnt != NULL); + RT_ASSERT(buf != NULL); + + superblock = (struct ptyfs_sb *)mnt->data; + RT_ASSERT(superblock != NULL); + + buf->f_bsize = OPTIMAL_BSIZE; + buf->f_blocks = (superblock->df_size + OPTIMAL_BSIZE - 1) / OPTIMAL_BSIZE; + buf->f_bfree = 1; + buf->f_bavail = buf->f_bfree; + + return RT_EOK; +} + +static int ptyfs_ops_stat(struct dfs_dentry *dentry, struct stat *st) +{ + struct dfs_vnode *vnode; + + if (dentry && dentry->vnode) + { + vnode = dentry->vnode; + + /* device id ? */ + st->st_dev = (dev_t)(long)(dentry->mnt->dev_id); + st->st_ino = (ino_t)dfs_dentry_full_path_crc32(dentry); + + st->st_gid = vnode->gid; + st->st_uid = vnode->uid; + st->st_mode = vnode->mode; + st->st_nlink = vnode->nlink; + st->st_size = vnode->size; + st->st_mtim.tv_nsec = vnode->mtime.tv_nsec; + st->st_mtim.tv_sec = vnode->mtime.tv_sec; + st->st_ctim.tv_nsec = vnode->ctime.tv_nsec; + st->st_ctim.tv_sec = vnode->ctime.tv_sec; + st->st_atim.tv_nsec = vnode->atime.tv_nsec; + st->st_atim.tv_sec = vnode->atime.tv_sec; + } + + return 0; +} + +static struct dfs_vnode *ptyfs_ops_lookup(struct dfs_dentry *dentry) +{ + struct dfs_vnode *vnode = RT_NULL; + struct ptyfs_sb *superblock; + struct ptyfs_file *pty_file; + + if (dentry == NULL || dentry->mnt == NULL || dentry->mnt->data == NULL) + { + return NULL; + } + + superblock = (struct ptyfs_sb *)dentry->mnt->data; + + pty_file = ptyfile_lookup(superblock, dentry->pathname); + if (pty_file) + { + vnode = dfs_vnode_create(); + if (vnode) + { + vnode->data = pty_file->device; + vnode->nlink = 1; + vnode->size = 0; + vnode->mnt = dentry->mnt; + /* if it's root directory */ + vnode->fops = &_default_fops; + vnode->mode = pty_file->mode; + vnode->type = pty_file->type == PTYFS_TYPE_DIR ? FT_DIRECTORY : FT_DEVICE; + } + } + + return vnode; +} + +static struct dfs_vnode *ptyfs_ops_create_vnode(struct dfs_dentry *dentry, + int type, mode_t mode) +{ + struct dfs_vnode *vnode = RT_NULL; + struct ptyfs_sb *sb; + struct ptyfs_file *pty_file; + char *vnode_path; + + if (dentry == NULL || dentry->mnt == NULL || dentry->mnt->data == NULL) + { + return NULL; + } + + sb = (struct ptyfs_sb *)dentry->mnt->data; + RT_ASSERT(sb != NULL); + + vnode = dfs_vnode_create(); + if (vnode) + { + vnode_path = dentry->pathname; + + /* Query if file existed. Filter out illegal open modes */ + pty_file = ptyfile_lookup(sb, vnode_path); + if (!pty_file || (~pty_file->mode & mode)) + { + dfs_vnode_destroy(vnode); + return NULL; + } + + vnode->data = pty_file->device; + vnode->nlink = 1; + vnode->size = 0; + vnode->mnt = dentry->mnt; + vnode->fops = pty_file->device ? pty_file->device->fops : RT_NULL; + vnode->mode &= pty_file->mode; + + if (type == FT_DIRECTORY) + { + vnode->mode |= S_IFDIR; + vnode->type = FT_DIRECTORY; + LOG_I("%s: S_IFDIR created", __func__); + } + else if (type == FT_REGULAR) + { + vnode->mode |= S_IFCHR; + vnode->type = FT_DEVICE; + LOG_I("%s: S_IFDIR created", __func__); + } + else + { + /* unsupported types */ + dfs_vnode_destroy(vnode); + return NULL; + } + } + + return vnode; +} + +static int ptyfs_ops_free_vnode(struct dfs_vnode *vnode) +{ + return RT_EOK; +} + +static int devpty_deffops_getdents(struct dfs_file *file, struct dirent *dirp, + uint32_t count) +{ + struct ptyfs_file *d_file; + struct ptyfs_sb *superblock; + + RT_ASSERT(file); + RT_ASSERT(file->dentry); + RT_ASSERT(file->dentry->mnt); + + superblock = (struct ptyfs_sb *)file->dentry->mnt->data; + RT_ASSERT(superblock); + + d_file = ptyfile_lookup(superblock, file->dentry->pathname); + if (d_file) + { + rt_size_t index, end; + struct dirent *d; + struct ptyfs_file *n_file; + rt_list_t *list; + + /* make integer count */ + count = (count / sizeof(struct dirent)); + if (count == 0) + { + return -EINVAL; + } + + end = file->fpos + count; + index = 0; + count = 0; + + rt_list_for_each(list, &d_file->subdirs) + { + if (index >= (rt_size_t)file->fpos) + { + n_file = rt_list_entry(list, struct ptyfs_file, ent_node); + + d = dirp + count; + if (n_file->type == PTYFS_TYPE_DIR) + { + d->d_type = DT_DIR; + } + else + { + /* ptmx(5,2) or slave(136,[0,1048575]) device, on Linux */ + d->d_type = DT_CHR; + } + + d->d_reclen = (rt_uint16_t)sizeof(struct dirent); + rt_strncpy(d->d_name, n_file->basename, DIRENT_NAME_MAX); + d->d_namlen = rt_strlen(d->d_name); + + count += 1; + file->fpos += 1; + } + index += 1; + if (index >= end) + { + break; + } + } + } + + return count * sizeof(struct dirent); +} + +static const struct dfs_filesystem_ops _ptyfs_ops = { + .name = "ptyfs", + .flags = DFS_FS_FLAG_DEFAULT, + .default_fops = &_default_fops, + + .mount = ptyfs_ops_mount, + .umount = ptyfs_ops_umount, + + /* don't allow to create symbolic link */ + .symlink = RT_NULL, + .readlink = RT_NULL, + .unlink = RT_NULL, + + .setattr = ptyfs_ops_setattr, + .statfs = ptyfs_ops_statfs, + .stat = ptyfs_ops_stat, + + .lookup = ptyfs_ops_lookup, + .create_vnode = ptyfs_ops_create_vnode, + .free_vnode = ptyfs_ops_free_vnode, +}; + +static struct dfs_filesystem_type _devptyfs = { + .fs_ops = &_ptyfs_ops, +}; + +static int _ptyfs_init(void) +{ + _default_fops = *dfs_devfs_fops(); + _default_fops.getdents = devpty_deffops_getdents; + + /* register file system */ + dfs_register(&_devptyfs); + + return 0; +} +INIT_COMPONENT_EXPORT(_ptyfs_init); diff --git a/components/dfs/dfs_v2/filesystems/ptyfs/ptyfs.h b/components/dfs/dfs_v2/filesystems/ptyfs/ptyfs.h new file mode 100644 index 00000000000..69b2fb66fd1 --- /dev/null +++ b/components/dfs/dfs_v2/filesystems/ptyfs/ptyfs.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-12-02 Shell init ver. + */ +#ifndef __FS_PTYFS_H__ +#define __FS_PTYFS_H__ +#include + +typedef rt_base_t ptsno_t; + +ptsno_t ptyfs_register_pts(rt_device_t ptmx, rt_device_t pts); + +rt_err_t ptyfs_unregister_pts(rt_device_t ptmx, ptsno_t ptsno); + +const char *ptyfs_get_rootpath(rt_device_t ptmx); + +#endif /* __FS_PTYFS_H__ */ diff --git a/components/dfs/dfs_v2/filesystems/romfs/romfs.c b/components/dfs/dfs_v2/filesystems/romfs/romfs.c index 91465116b37..45279bcb832 100644 --- a/components/dfs/dfs_v2/filesystems/romfs/romfs.c +++ b/components/dfs/dfs_v2/filesystems/romfs/romfs.c @@ -29,6 +29,9 @@ rt_weak const struct romfs_dirent _root_dirent[] = { {ROMFS_DIRENT_DIR, "dev", RT_NULL, 0}, {ROMFS_DIRENT_DIR, "mnt", RT_NULL, 0}, + {ROMFS_DIRENT_DIR, "proc", RT_NULL, 0}, + {ROMFS_DIRENT_DIR, "etc", RT_NULL, 0}, + {ROMFS_DIRENT_DIR, "bin", RT_NULL, 0}, {ROMFS_DIRENT_DIR, "dummy", (rt_uint8_t *)_dummy, sizeof(_dummy) / sizeof(_dummy[0])}, {ROMFS_DIRENT_FILE, "dummy.txt", _dummy_txt, sizeof(_dummy_txt)}, }; diff --git a/components/dfs/dfs_v2/filesystems/tmpfs/dfs_tmpfs.c b/components/dfs/dfs_v2/filesystems/tmpfs/dfs_tmpfs.c index f289fc44198..8644f51c267 100644 --- a/components/dfs/dfs_v2/filesystems/tmpfs/dfs_tmpfs.c +++ b/components/dfs/dfs_v2/filesystems/tmpfs/dfs_tmpfs.c @@ -202,6 +202,7 @@ int dfs_tmpfs_ioctl(struct dfs_file *file, int cmd, void *args) superblock = d_file->sb; RT_ASSERT(superblock != NULL); + RT_UNUSED(superblock); switch (cmd) { @@ -317,26 +318,21 @@ static ssize_t dfs_tmpfs_read(struct dfs_file *file, void *buf, size_t count, of return length; } -static ssize_t dfs_tmpfs_write(struct dfs_file *file, const void *buf, size_t count, off_t *pos) +static ssize_t _dfs_tmpfs_write(struct tmpfs_file *d_file, const void *buf, size_t count, off_t *pos) { - struct tmpfs_file *d_file; struct tmpfs_sb *superblock; - d_file = (struct tmpfs_file *)file->vnode->data; RT_ASSERT(d_file != NULL); superblock = d_file->sb; RT_ASSERT(superblock != NULL); - rt_mutex_take(&file->vnode->lock, RT_WAITING_FOREVER); - - if (count + *pos > file->vnode->size) + if (count + *pos > d_file->size) { rt_uint8_t *ptr; ptr = rt_realloc(d_file->data, *pos + count); if (ptr == NULL) { - rt_mutex_release(&file->vnode->lock); rt_set_errno(-ENOMEM); return 0; } @@ -347,7 +343,6 @@ static ssize_t dfs_tmpfs_write(struct dfs_file *file, const void *buf, size_t co /* update d_file and file size */ d_file->data = ptr; d_file->size = *pos + count; - file->vnode->size = d_file->size; LOG_D("tmpfile ptr:%x, size:%d", ptr, d_file->size); } @@ -356,6 +351,21 @@ static ssize_t dfs_tmpfs_write(struct dfs_file *file, const void *buf, size_t co /* update file current position */ *pos += count; + + return count; +} + +static ssize_t dfs_tmpfs_write(struct dfs_file *file, const void *buf, size_t count, off_t *pos) +{ + struct tmpfs_file *d_file; + + d_file = (struct tmpfs_file *)file->vnode->data; + RT_ASSERT(d_file != NULL); + + rt_mutex_take(&file->vnode->lock, RT_WAITING_FOREVER); + + count = _dfs_tmpfs_write(d_file, buf, count, pos); + rt_mutex_release(&file->vnode->lock); return count; @@ -504,6 +514,7 @@ static int dfs_tmpfs_getdents(struct dfs_file *file, superblock = d_file->sb; RT_ASSERT(superblock != RT_NULL); + RT_UNUSED(superblock); /* make integer count */ count = (count / sizeof(struct dirent)); @@ -797,6 +808,8 @@ static ssize_t dfs_tmp_page_read(struct dfs_file *file, struct dfs_page *page) ssize_t dfs_tmp_page_write(struct dfs_page *page) { + off_t pos; + size_t count = 0; struct tmpfs_file *d_file; if (page->aspace->vnode->type == FT_DIRECTORY) @@ -806,13 +819,16 @@ ssize_t dfs_tmp_page_write(struct dfs_page *page) d_file = (struct tmpfs_file *)(page->aspace->vnode->data); RT_ASSERT(d_file != RT_NULL); + rt_mutex_take(&page->aspace->vnode->lock, RT_WAITING_FOREVER); if (page->len > 0) - memcpy(d_file->data + page->fpos, page->page, page->len); - + { + pos = page->fpos; + count = _dfs_tmpfs_write(d_file, page->page, page->len, &pos); + } rt_mutex_release(&page->aspace->vnode->lock); - return F_OK; + return count; } #endif diff --git a/components/dfs/dfs_v2/include/dfs.h b/components/dfs/dfs_v2/include/dfs.h index 6815f5e0ab1..8b8c80188f8 100644 --- a/components/dfs/dfs_v2/include/dfs.h +++ b/components/dfs/dfs_v2/include/dfs.h @@ -25,6 +25,10 @@ #include #include +#ifndef ATTR_MODE_SET +#define ATTR_MODE_SET (1 << 6) +#endif + #ifndef ATTR_ATIME_SET #define ATTR_ATIME_SET (1 << 7) #endif @@ -33,6 +37,14 @@ #define ATTR_MTIME_SET (1 << 8) #endif +#ifndef ATTR_UID_SET +#define ATTR_UID_SET (1 << 9) +#endif + +#ifndef ATTR_GID_SET +#define ATTR_GID_SET (1 << 10) +#endif + #ifndef AT_SYMLINK_NOFOLLOW #define AT_SYMLINK_NOFOLLOW 0x100 #endif diff --git a/components/dfs/dfs_v2/include/dfs_file.h b/components/dfs/dfs_v2/include/dfs_file.h index 9a47198e4dd..48958028ab0 100644 --- a/components/dfs/dfs_v2/include/dfs_file.h +++ b/components/dfs/dfs_v2/include/dfs_file.h @@ -101,6 +101,7 @@ struct dfs_file void *data; }; +#define DFS_FILE_POS(dfs_file) ((dfs_file)->fpos) /* file is open for reading */ #define FMODE_READ 0x1 @@ -150,7 +151,9 @@ int dfs_file_close(struct dfs_file *file); off_t dfs_file_get_fpos(struct dfs_file *file); void dfs_file_set_fpos(struct dfs_file *file, off_t fpos); +ssize_t dfs_file_pread(struct dfs_file *file, void *buf, size_t len, off_t offset); ssize_t dfs_file_read(struct dfs_file *file, void *buf, size_t len); +ssize_t dfs_file_pwrite(struct dfs_file *file, const void *buf, size_t len, off_t offset); ssize_t dfs_file_write(struct dfs_file *file, const void *buf, size_t len); off_t generic_dfs_lseek(struct dfs_file *file, off_t offset, int whence); off_t dfs_file_lseek(struct dfs_file *file, off_t offset, int wherece); @@ -174,20 +177,25 @@ int dfs_file_isdir(const char *path); int dfs_file_access(const char *path, mode_t mode); int dfs_file_chdir(const char *path); char *dfs_file_getcwd(char *buf, size_t size); -char *dfs_nolink_path(struct dfs_mnt **mnt, char *fullpath, int mode); + #ifdef RT_USING_SMART int dfs_file_mmap2(struct dfs_file *file, struct dfs_mmap2_args *mmap2); int dfs_file_mmap(struct dfs_file *file, struct dfs_mmap2_args *mmap2); #endif -char *dfs_nolink_path(struct dfs_mnt **mnt, char *fullpath, int mode); - /* 0x5254 is just a magic number to make these relatively unique ("RT") */ #define RT_FIOFTRUNCATE 0x52540000U #define RT_FIOGETADDR 0x52540001U #define RT_FIOMMAP2 0x52540002U +/* dfs_file_realpath mode */ +#define DFS_REALPATH_EXCEPT_LAST 0 +#define DFS_REALPATH_EXCEPT_NONE 1 +#define DFS_REALPATH_ONLY_LAST 3 + +char *dfs_file_realpath(struct dfs_mnt **mnt, const char *fullpath, int mode); + #ifdef __cplusplus } #endif diff --git a/components/dfs/dfs_v2/include/dfs_fs.h b/components/dfs/dfs_v2/include/dfs_fs.h index 9dc99ee3672..d30967aac53 100644 --- a/components/dfs/dfs_v2/include/dfs_fs.h +++ b/components/dfs/dfs_v2/include/dfs_fs.h @@ -32,7 +32,9 @@ struct dfs_partition struct dfs_attr { unsigned int ia_valid; - mode_t st_mode; + uid_t st_uid; + gid_t st_gid; + mode_t st_mode; struct timespec ia_atime; struct timespec ia_mtime; }; diff --git a/components/dfs/dfs_v2/include/dfs_pcache.h b/components/dfs/dfs_v2/include/dfs_pcache.h index 356df6c4f96..01abfe31504 100644 --- a/components/dfs/dfs_v2/include/dfs_pcache.h +++ b/components/dfs/dfs_v2/include/dfs_pcache.h @@ -23,6 +23,8 @@ extern "C" { #endif +struct rt_varea; +struct rt_aspace; struct dfs_vnode; struct dfs_dentry; struct dfs_aspace; @@ -30,7 +32,8 @@ struct dfs_aspace; struct dfs_mmap { rt_list_t mmap_node; - struct rt_varea *varea; + struct rt_aspace *aspace; + void *vaddr; }; struct dfs_page diff --git a/components/dfs/dfs_v2/src/dfs.c b/components/dfs/dfs_v2/src/dfs.c index ad90822b93c..939e4dd66ef 100644 --- a/components/dfs/dfs_v2/src/dfs.c +++ b/components/dfs/dfs_v2/src/dfs.c @@ -557,6 +557,111 @@ int dfs_dup(int oldfd, int startfd) return newfd; } +/** + * @brief The fd in the current process dup to designate fd table. + * + * @param oldfd is the fd in current process. + * + * @param fdtab is the fd table to dup, if empty, use global (_fdtab). + * + * @return -1 on failed or the allocated file descriptor. + */ +int dfs_dup_to(int oldfd, struct dfs_fdtable *fdtab) +{ + int newfd = -1; + struct dfs_fdtable *fdt = NULL; + + if (dfs_file_lock() != RT_EOK) + { + return -RT_ENOSYS; + } + + if (fdtab == NULL) + { + fdtab = &_fdtab; + } + + /* check old fd */ + fdt = dfs_fdtable_get(); + if ((oldfd < 0) || (oldfd >= fdt->maxfd)) + { + goto exit; + } + if (!fdt->fds[oldfd]) + { + goto exit; + } + /* get a new fd*/ + newfd = _fdt_slot_alloc(fdtab, DFS_STDIO_OFFSET); + if (newfd >= 0) + { + fdtab->fds[newfd] = fdt->fds[oldfd]; + + /* inc ref_count */ + rt_atomic_add(&(fdtab->fds[newfd]->ref_count), 1); + } +exit: + dfs_file_unlock(); + + return newfd; +} + +/** + * @brief The fd in the designate fd table dup to current process. + * + * @param oldfd is the fd in the designate fd table. + * + * @param fdtab is the fd table for oldfd, if empty, use global (_fdtab). + * + * @return -1 on failed or the allocated file descriptor. + */ +int dfs_dup_from(int oldfd, struct dfs_fdtable *fdtab) +{ + int newfd = -1; + struct dfs_file *file; + + if (dfs_file_lock() != RT_EOK) + { + return -RT_ENOSYS; + } + + if (fdtab == NULL) + { + fdtab = &_fdtab; + } + + /* check old fd */ + if ((oldfd < 0) || (oldfd >= fdtab->maxfd)) + { + goto exit; + } + if (!fdtab->fds[oldfd]) + { + goto exit; + } + /* get a new fd*/ + newfd = fd_new(); + file = fd_get(newfd); + if (newfd >= 0 && file) + { + file->mode = fdtab->fds[oldfd]->mode; + file->flags = fdtab->fds[oldfd]->flags; + file->fops = fdtab->fds[oldfd]->fops; + file->dentry = dfs_dentry_ref(fdtab->fds[oldfd]->dentry); + file->vnode = fdtab->fds[oldfd]->vnode; + file->mmap_context = RT_NULL; + file->data = fdtab->fds[oldfd]->data; + } + + dfs_file_close(fdtab->fds[oldfd]); + +exit: + fdt_fd_release(fdtab, oldfd); + dfs_file_unlock(); + + return newfd; +} + #ifdef RT_USING_SMART sysret_t sys_dup(int oldfd) #else @@ -856,7 +961,11 @@ int dfs_fd_dump(int argc, char** argv) { int index; - dfs_file_lock(); + if (dfs_file_lock() != RT_EOK) + { + return -RT_ENOSYS; + } + for (index = 0; index < _fdtab.maxfd; index++) { struct dfs_file *file = _fdtab.fds[index]; diff --git a/components/dfs/dfs_v2/src/dfs_file.c b/components/dfs/dfs_v2/src/dfs_file.c index 5f55eaaba13..8a9cac7602e 100644 --- a/components/dfs/dfs_v2/src/dfs_file.c +++ b/components/dfs/dfs_v2/src/dfs_file.c @@ -29,22 +29,86 @@ #define MAX_RW_COUNT 0xfffc0000 -rt_inline int _find_path_node(const char *path) +rt_inline int _first_path_len(const char *path) { int i = 0; - while (path[i] != '\0') + if (path[i] == '/') { - if ('/' == path[i++]) + i++; + while (path[i] != '\0' && path[i] != '/') { - break; + i++; } } - /* return path-note length */ return i; } +static int _get_parent_path(const char *fullpath, char *path) +{ + int len = 0; + char *str = 0; + + str = strrchr(fullpath, '/'); + if (str) + { + len = str - fullpath; + if (len > 0) + { + rt_memcpy(path, fullpath, len); + path[len] = '\0'; + } + } + + return len; +} + +static int _try_readlink(const char *path, struct dfs_mnt *mnt, char *link) +{ + int ret = -1; + struct dfs_dentry *dentry = dfs_dentry_lookup(mnt, path, 0); + + if (dentry && dentry->vnode->type == FT_SYMLINK) + { + if (mnt->fs_ops->readlink) + { + if (dfs_is_mounted(mnt) == 0) + { + ret = mnt->fs_ops->readlink(dentry, link, DFS_PATH_MAX); + } + } + } + dfs_dentry_unref(dentry); + + return ret; +} + +static int _insert_link_path(const char *link_fn, int link_len, char *tmp_path, int *index) +{ + int ret = -1; + + if (link_fn[0] != '/') + { + if (link_len + 1 <= *index) + { + *index -= link_len; + rt_memcpy(tmp_path + *index, link_fn, link_len); + *index -= 1; + tmp_path[*index] = '/'; + ret = 0; + } + } + else if (link_len <= *index) + { + *index -= link_len; + rt_memcpy(tmp_path + *index, link_fn, link_len); + ret = 1; + } + + return ret; +} + /* * rw_verify_area doesn't like huge counts. We limit * them to something that fits in "int" so that others @@ -149,166 +213,97 @@ static void dfs_file_unref(struct dfs_file *file) } } -struct dfs_dentry* dfs_file_follow_link(struct dfs_dentry *dentry) -{ - int ret = 0; - struct dfs_dentry *tmp = dfs_dentry_ref(dentry); - - if (dentry && dentry->vnode && dentry->vnode->type == FT_SYMLINK) - { - char *buf = NULL; - - buf = (char *)rt_malloc(DFS_PATH_MAX); - if (buf) - { - do - { - if (dfs_is_mounted(tmp->mnt) == 0) - { - ret = tmp->mnt->fs_ops->readlink(tmp, buf, DFS_PATH_MAX); - } - - if (ret > 0) - { - struct dfs_mnt *mnt = NULL; - - if (buf[0] != '/') - { - char *dir = dfs_dentry_pathname(tmp); - - /* is the relative directory */ - if (dir) - { - char *fullpath = dfs_normalize_path(dir, buf); - if (fullpath) - { - strncpy(buf, fullpath, DFS_PATH_MAX); - - rt_free(fullpath); - } - rt_free(dir); - } - } - - mnt = dfs_mnt_lookup(buf); - if (mnt) - { - struct dfs_dentry *de = dfs_dentry_lookup(mnt, buf, 0); - - /* release the old dentry */ - dfs_dentry_unref(tmp); - tmp = de; - } - } - else - { - break; - } - } while (tmp && tmp->vnode->type == FT_SYMLINK); - } - - rt_free(buf); - } - - return tmp; -} - /* * this function is creat a nolink path. * * @param mnt * @param fullpath - * @param mode 0 middle path nolink; 1 all path nolink. + * @param mode * * @return new path. */ -char *dfs_nolink_path(struct dfs_mnt **mnt, char *fullpath, int mode) +char *dfs_file_realpath(struct dfs_mnt **mnt, const char *fullpath, int mode) { - int index = 0; - char *path = RT_NULL; - char *link_fn; - struct dfs_dentry *dentry = RT_NULL; - - path = (char *)rt_malloc((DFS_PATH_MAX * 2) + 2); // path + \0 + link_fn + \0 - if (!path) - { - return path; - } - link_fn = path + DFS_PATH_MAX + 1; + int path_len = 0, index = 0; + char *path = RT_NULL, *link_fn, *tmp_path; + struct dfs_mnt *tmp_mnt; if (*mnt && fullpath) { - int i = 0; - char *fp = fullpath; + int len, link_len; - while ((i = _find_path_node(fp)) > 0) + path = (char *)rt_malloc((DFS_PATH_MAX * 3) + 3); // path + \0 + link_fn + \0 + tmp_path + \0 + if (!path) { - if (i + index > DFS_PATH_MAX) + return RT_NULL; + } + + link_fn = path + DFS_PATH_MAX + 1; + tmp_path = link_fn + (DFS_PATH_MAX + 1); + + len = rt_strlen(fullpath); + if (len > DFS_PATH_MAX) + { + goto _ERR_RET; + } + + index = (DFS_PATH_MAX - len); + rt_strcpy(tmp_path + index, fullpath); + + if (mode == DFS_REALPATH_ONLY_LAST) + { + path_len = _get_parent_path(fullpath, path); + index += path_len; + } + + while ((len = _first_path_len(tmp_path + index)) > 0) + { + if (len + path_len > DFS_PATH_MAX) { goto _ERR_RET; } - rt_memcpy(path + index, fp, i); - path[index + i] = '\0'; + rt_memcpy(path + path_len, tmp_path + index, len); + path[path_len + len] = '\0'; + index += len; - /* the last should by mode process. */ - if ((fp[i] == '\0') && (!mode)) + tmp_mnt = dfs_mnt_lookup(path); + if (tmp_mnt == RT_NULL) { - break; + goto _ERR_RET; } - fp += i; + *mnt = tmp_mnt; - dentry = dfs_dentry_lookup(*mnt, path, 0); - if (dentry && dentry->vnode->type == FT_SYMLINK) + /* the last should by mode process. */ + if ((tmp_path[index] == '\0') && (mode == DFS_REALPATH_EXCEPT_LAST)) { - int ret = -1; + break; + } - if ((*mnt)->fs_ops->readlink) - { - if (dfs_is_mounted((*mnt)) == 0) - { - ret = (*mnt)->fs_ops->readlink(dentry, link_fn, DFS_PATH_MAX); - } - } + link_len = _try_readlink(path, *mnt, link_fn); + if (link_len > 0) + { + int ret = _insert_link_path(link_fn, link_len, tmp_path, &index); - if (ret > 0) + if (ret == 1) { - int len = rt_strlen(link_fn); - - if (link_fn[0] != '/') - { - path[index] = '/'; - } - else - { - index = 0; - } - - if (len + index + 1 >= DFS_PATH_MAX) - { - goto _ERR_RET; - } - - rt_memcpy(path + index, link_fn, len); - index += len; - path[index] = '\0'; - *mnt = dfs_mnt_lookup(path); + /* link_fn[0] == '/' */ + path_len = 0; } - else + else if (ret < 0) { goto _ERR_RET; } } else { - index += i; + path_len += len; } - dfs_dentry_unref(dentry); } - } - else - { + + return path; + _ERR_RET: rt_free(path); path = RT_NULL; @@ -349,7 +344,7 @@ int dfs_file_open(struct dfs_file *file, const char *path, int oflags, mode_t mo mnt = dfs_mnt_lookup(fullpath); if (mnt) { - char *tmp = dfs_nolink_path(&mnt, fullpath, 0); + char *tmp = dfs_file_realpath(&mnt, fullpath, DFS_REALPATH_EXCEPT_LAST); if (tmp) { rt_free(fullpath); @@ -370,9 +365,12 @@ int dfs_file_open(struct dfs_file *file, const char *path, int oflags, mode_t mo else { struct dfs_dentry *target_dentry = RT_NULL; - - /* follow symbol link */ - target_dentry = dfs_file_follow_link(dentry); + char *path = dfs_file_realpath(&mnt, fullpath, DFS_REALPATH_ONLY_LAST); + if (path) + { + target_dentry = dfs_dentry_lookup(mnt, path, oflags); + rt_free(path); + } dfs_dentry_unref(dentry); dentry = target_dentry; } @@ -507,7 +505,7 @@ int dfs_file_open(struct dfs_file *file, const char *path, int oflags, mode_t mo if (ret < 0) { - LOG_E("open %s failed in file system: %s", path, dentry->mnt->fs_ops->name); + LOG_I("open %s failed in file system: %s", path, dentry->mnt->fs_ops->name); DLOG(msg, mnt->fs_ops->name, "dfs_file", DLOG_MSG_RET, "open failed."); dfs_file_unref(file); } @@ -628,6 +626,54 @@ int dfs_file_close(struct dfs_file *file) return ret; } +ssize_t dfs_file_pread(struct dfs_file *file, void *buf, size_t len, off_t offset) +{ + ssize_t ret = -EBADF; + + if (file) + { + /* check whether read */ + if (!(dfs_fflags(file->flags) & DFS_F_FREAD)) + { + ret = -EPERM; + } + else if (!file->fops || !file->fops->read) + { + ret = -ENOSYS; + } + else if (file->vnode && file->vnode->type != FT_DIRECTORY) + { + off_t pos = offset; + + ret = rw_verify_area(file, &pos, len); + if (ret > 0) + { + len = ret; + + if (dfs_is_mounted(file->vnode->mnt) == 0) + { +#ifdef RT_USING_PAGECACHE + if (file->vnode->aspace && !(file->flags & O_DIRECT)) + { + ret = dfs_aspace_read(file, buf, len, &pos); + } + else +#endif + { + ret = file->fops->read(file, buf, len, &pos); + } + } + else + { + ret = -EINVAL; + } + } + } + } + + return ret; +} + ssize_t dfs_file_read(struct dfs_file *file, void *buf, size_t len) { ssize_t ret = -EBADF; @@ -679,9 +725,65 @@ ssize_t dfs_file_read(struct dfs_file *file, void *buf, size_t len) return ret; } +ssize_t dfs_file_pwrite(struct dfs_file *file, const void *buf, size_t len, off_t offset) +{ + ssize_t ret = -EBADF; + + if (file) + { + if (!(dfs_fflags(file->flags) & DFS_F_FWRITE)) + { + LOG_W("bad write flags."); + ret = -EBADF; + } + else if (!file->fops || !file->fops->write) + { + LOG_W("no fops write."); + ret = -ENOSYS; + } + else if (file->vnode && file->vnode->type != FT_DIRECTORY) + { + off_t pos = offset; + + ret = rw_verify_area(file, &pos, len); + if (ret > 0) + { + len = ret; + DLOG(msg, "dfs_file", file->dentry->mnt->fs_ops->name, DLOG_MSG, + "dfs_file_write(fd, buf, %d)", len); + + if (dfs_is_mounted(file->vnode->mnt) == 0) + { +#ifdef RT_USING_PAGECACHE + if (file->vnode->aspace && !(file->flags & O_DIRECT)) + { + ret = dfs_aspace_write(file, buf, len, &pos); + } + else +#endif + { + ret = file->fops->write(file, buf, len, &pos); + } + + if (file->flags & O_SYNC) + { + file->fops->flush(file); + } + } + else + { + ret = -EINVAL; + } + } + } + } + + return ret; +} + ssize_t dfs_file_write(struct dfs_file *file, const void *buf, size_t len) { - size_t ret = -EBADF; + ssize_t ret = -EBADF; if (file) { @@ -697,8 +799,17 @@ ssize_t dfs_file_write(struct dfs_file *file, const void *buf, size_t len) } else if (file->vnode && file->vnode->type != FT_DIRECTORY) { - /* fpos lock */ - off_t pos = dfs_file_get_fpos(file); + off_t pos; + + if (!(file->flags & O_APPEND)) + { + /* fpos lock */ + pos = dfs_file_get_fpos(file); + } + else + { + pos = file->vnode->size; + } ret = rw_verify_area(file, &pos, len); if (ret > 0) @@ -730,8 +841,11 @@ ssize_t dfs_file_write(struct dfs_file *file, const void *buf, size_t len) ret = -EINVAL; } } - /* fpos unlock */ - dfs_file_set_fpos(file, pos); + if (!(file->flags & O_APPEND)) + { + /* fpos unlock */ + dfs_file_set_fpos(file, pos); + } } } @@ -791,7 +905,7 @@ int dfs_file_stat(const char *path, struct stat *buf) mnt = dfs_mnt_lookup(fullpath); if (mnt) { - char *tmp = dfs_nolink_path(&mnt, fullpath, 1); + char *tmp = dfs_file_realpath(&mnt, fullpath, DFS_REALPATH_EXCEPT_NONE); if (tmp) { rt_free(fullpath); @@ -845,7 +959,7 @@ int dfs_file_lstat(const char *path, struct stat *buf) mnt = dfs_mnt_lookup(fullpath); if (mnt) { - char *tmp = dfs_nolink_path(&mnt, fullpath, 0); + char *tmp = dfs_file_realpath(&mnt, fullpath, DFS_REALPATH_EXCEPT_LAST); if (tmp) { rt_free(fullpath); @@ -924,7 +1038,7 @@ int dfs_file_setattr(const char *path, struct dfs_attr *attr) mnt = dfs_mnt_lookup(fullpath); if (mnt) { - char *tmp = dfs_nolink_path(&mnt, fullpath, 0); + char *tmp = dfs_file_realpath(&mnt, fullpath, DFS_REALPATH_EXCEPT_LAST); if (tmp) { rt_free(fullpath); @@ -1097,7 +1211,7 @@ int dfs_file_unlink(const char *path) mnt = dfs_mnt_lookup(fullpath); if (mnt) { - char *tmp = dfs_nolink_path(&mnt, fullpath, 0); + char *tmp = dfs_file_realpath(&mnt, fullpath, DFS_REALPATH_EXCEPT_LAST); if (tmp) { rt_free(fullpath); @@ -1199,7 +1313,7 @@ int dfs_file_link(const char *oldname, const char *newname) return -1; } - char *tmp = dfs_nolink_path(&mnt, old_fullpath, 0); + char *tmp = dfs_file_realpath(&mnt, old_fullpath, DFS_REALPATH_EXCEPT_LAST); if (tmp) { rt_free(old_fullpath); @@ -1210,7 +1324,7 @@ int dfs_file_link(const char *oldname, const char *newname) new_fullpath = dfs_normalize_path(NULL, newname); if (new_fullpath) { - char *tmp = dfs_nolink_path(&mnt, new_fullpath, 0); + char *tmp = dfs_file_realpath(&mnt, new_fullpath, DFS_REALPATH_EXCEPT_LAST); if (tmp) { rt_free(new_fullpath); @@ -1310,7 +1424,7 @@ int dfs_file_symlink(const char *target, const char *linkpath) mnt = dfs_mnt_lookup(parent); if (mnt) { - char *tmp = dfs_nolink_path(&mnt, parent, 0); + char *tmp = dfs_file_realpath(&mnt, parent, DFS_REALPATH_EXCEPT_LAST); if (tmp) { rt_free(parent); @@ -1318,7 +1432,7 @@ int dfs_file_symlink(const char *target, const char *linkpath) } DLOG(msg, "dfs_file", "dentry", DLOG_MSG, "dfs_dentry_lookup(mnt, %s)", fullpath); - dentry = dfs_dentry_lookup(mnt, parent, 0); + dentry = dfs_dentry_lookup(mnt, parent, DFS_REALPATH_EXCEPT_LAST); if (dentry) { if (dentry->mnt->fs_ops->symlink) @@ -1326,17 +1440,6 @@ int dfs_file_symlink(const char *target, const char *linkpath) char *path = dfs_normalize_path(parent, target); if (path) { - char *tmp = dfs_nolink_path(&mnt, path, 0); - if (tmp) - { - rt_free(path); - path = tmp; - } - else - { - tmp = path; - } - ret = rt_strncmp(parent, path, strlen(parent)); if (ret == 0) { @@ -1346,6 +1449,10 @@ int dfs_file_symlink(const char *target, const char *linkpath) tmp ++; } } + else + { + tmp = path; + } if (dfs_is_mounted(mnt) == 0) { @@ -1401,7 +1508,7 @@ int dfs_file_readlink(const char *path, char *buf, int bufsize) mnt = dfs_mnt_lookup(fullpath); if (mnt) { - char *tmp = dfs_nolink_path(&mnt, fullpath, 0); + char *tmp = dfs_file_realpath(&mnt, fullpath, DFS_REALPATH_EXCEPT_LAST); if (tmp) { rt_free(fullpath); @@ -1466,7 +1573,7 @@ int dfs_file_rename(const char *old_file, const char *new_file) return -1; } - char *tmp = dfs_nolink_path(&mnt, old_fullpath, 0); + char *tmp = dfs_file_realpath(&mnt, old_fullpath, DFS_REALPATH_EXCEPT_LAST); if (tmp) { rt_free(old_fullpath); @@ -1477,7 +1584,7 @@ int dfs_file_rename(const char *old_file, const char *new_file) new_fullpath = dfs_normalize_path(NULL, new_file); if (new_fullpath) { - char *tmp = dfs_nolink_path(&mnt, new_fullpath, 0); + char *tmp = dfs_file_realpath(&mnt, new_fullpath, DFS_REALPATH_EXCEPT_LAST); if (tmp) { rt_free(new_fullpath); @@ -1652,7 +1759,7 @@ int dfs_file_isdir(const char *path) mnt = dfs_mnt_lookup(fullpath); if (mnt) { - char *tmp = dfs_nolink_path(&mnt, fullpath, 1); + char *tmp = dfs_file_realpath(&mnt, fullpath, DFS_REALPATH_EXCEPT_NONE); if (tmp) { rt_free(fullpath); @@ -1853,7 +1960,7 @@ void ls(const char *pathname) mnt = dfs_mnt_lookup(fullpath); if (mnt) { - char *tmp = dfs_nolink_path(&mnt, fullpath, 0); + char *tmp = dfs_file_realpath(&mnt, fullpath, DFS_REALPATH_EXCEPT_LAST); if (tmp) { char *index; diff --git a/components/dfs/dfs_v2/src/dfs_pcache.c b/components/dfs/dfs_v2/src/dfs_pcache.c index 11f6172d08c..57f4510e93f 100644 --- a/components/dfs/dfs_v2/src/dfs_pcache.c +++ b/components/dfs/dfs_v2/src/dfs_pcache.c @@ -269,7 +269,6 @@ static void dfs_pcache_thread(void *parameter) { page->len = page->size; } - //rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, page->page, page->size); if (aspace->ops->write) { aspace->ops->write(page); @@ -676,9 +675,14 @@ static int dfs_page_unmap(struct dfs_page *page) if (map) { - void *vaddr = dfs_aspace_vaddr(map->varea, page->fpos); - //rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, vaddr, ARCH_PAGE_SIZE); - rt_varea_unmap_page(map->varea, vaddr); + rt_varea_t varea; + void *vaddr; + + varea = rt_aspace_query(map->aspace, map->vaddr); + RT_ASSERT(varea); + vaddr = dfs_aspace_vaddr(varea, page->fpos); + + rt_varea_unmap_page(varea, vaddr); rt_free(map); } @@ -741,7 +745,6 @@ static void dfs_page_release(struct dfs_page *page) { page->len = page->size; } - //rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, page->page, page->size); if (aspace->ops->write) { aspace->ops->write(page); @@ -995,7 +998,6 @@ static struct dfs_page *dfs_aspace_load_page(struct dfs_file *file, off_t pos) page->size = ARCH_PAGE_SIZE; page->fpos = pos / ARCH_PAGE_SIZE * ARCH_PAGE_SIZE; aspace->ops->read(file, page); - //rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, page->page, page->size); page->ref_count ++; dfs_page_insert(page); @@ -1105,7 +1107,6 @@ int dfs_aspace_read(struct dfs_file *file, void *buf, size_t count, off_t *pos) len = count > len ? len : count; if (len) { - //rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, page->page, page->size); rt_memcpy(ptr, page->page + *pos - page->fpos, len); ptr += len; *pos += len; @@ -1158,7 +1159,6 @@ int dfs_aspace_write(struct dfs_file *file, const void *buf, size_t count, off_t len = page->fpos + ARCH_PAGE_SIZE - *pos; len = count > len ? len : count; rt_memcpy(page->page + *pos - page->fpos, ptr, len); - //rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, page->page, page->size); ptr += len; *pos += len; count -= len; @@ -1225,7 +1225,7 @@ int dfs_aspace_flush(struct dfs_aspace *aspace) { page->len = page->size; } - //rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, page->page, page->size); + if (aspace->ops->write) { aspace->ops->write(page); @@ -1277,6 +1277,7 @@ void *dfs_aspace_mmap(struct dfs_file *file, struct rt_varea *varea, void *vaddr void *ret = RT_NULL; struct dfs_page *page; struct dfs_aspace *aspace = file->vnode->aspace; + rt_aspace_t target_aspace = varea->aspace; page = dfs_page_lookup(file, dfs_aspace_fpos(varea, vaddr)); if (page) @@ -1284,7 +1285,8 @@ void *dfs_aspace_mmap(struct dfs_file *file, struct rt_varea *varea, void *vaddr struct dfs_mmap *map = (struct dfs_mmap *)rt_calloc(1, sizeof(struct dfs_mmap)); if (map) { - void *pg_paddr = rt_kmem_v2p(page->page); + void *pg_vaddr = page->page; + void *pg_paddr = rt_kmem_v2p(pg_vaddr); int err = rt_varea_map_range(varea, vaddr, pg_paddr, page->size); if (err == RT_EOK) { @@ -1301,10 +1303,12 @@ void *dfs_aspace_mmap(struct dfs_file *file, struct rt_varea *varea, void *vaddr * fetching of the next instruction can see the coherent data with the data cache, * TLB, MMU, main memory, and all the other observers in the computer system. */ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, vaddr, ARCH_PAGE_SIZE); rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, vaddr, ARCH_PAGE_SIZE); - ret = page->page; - map->varea = varea; + ret = pg_vaddr; + map->aspace = target_aspace; + map->vaddr = vaddr; dfs_aspace_lock(aspace); rt_list_insert_after(&page->mmap_head, &map->mmap_node); dfs_page_release(page); @@ -1329,6 +1333,8 @@ int dfs_aspace_unmap(struct dfs_file *file, struct rt_varea *varea) { struct dfs_vnode *vnode = file->vnode; struct dfs_aspace *aspace = vnode->aspace; + void *unmap_start = varea->start; + void *unmap_end = (char *)unmap_start + varea->size; if (aspace) { @@ -1347,20 +1353,32 @@ int dfs_aspace_unmap(struct dfs_file *file, struct rt_varea *varea) { rt_list_t *node, *tmp; struct dfs_mmap *map; + rt_varea_t map_varea = RT_NULL; node = page->mmap_head.next; while (node != &page->mmap_head) { + rt_aspace_t map_aspace; map = rt_list_entry(node, struct dfs_mmap, mmap_node); tmp = node; node = node->next; - if (map && varea == map->varea) + if (map && varea->aspace == map->aspace + && map->vaddr >= unmap_start && map->vaddr < unmap_end) { - void *vaddr = dfs_aspace_vaddr(map->varea, page->fpos); + void *vaddr = map->vaddr; + map_aspace = map->aspace; + + if (!map_varea || map_varea->aspace != map_aspace || + vaddr < map_varea->start || + vaddr >= map_varea->start + map_varea->size) + { + /* lock the tree so we don't access uncompleted data */ + map_varea = rt_aspace_query(map_aspace, vaddr); + } - rt_varea_unmap_page(map->varea, vaddr); + rt_varea_unmap_page(map_varea, vaddr); if (varea->attr == MMU_MAP_U_RWCB && page->fpos < page->aspace->vnode->size) { @@ -1405,7 +1423,7 @@ int dfs_aspace_page_unmap(struct dfs_file *file, struct rt_varea *varea, void *v tmp = node; node = node->next; - if (map && varea == map->varea) + if (map && varea->aspace == map->aspace && vaddr == map->vaddr) { if (varea->attr == MMU_MAP_U_RWCB) { diff --git a/components/dfs/dfs_v2/src/dfs_posix.c b/components/dfs/dfs_v2/src/dfs_posix.c index 77ffe205165..ef6e8e78e51 100644 --- a/components/dfs/dfs_v2/src/dfs_posix.c +++ b/components/dfs/dfs_v2/src/dfs_posix.c @@ -1180,6 +1180,7 @@ int chdir(const char *path) /* this is a not exist directory */ dfs_unlock(); + rt_set_errno(-ENOTDIR); return -1; } @@ -1363,9 +1364,7 @@ ssize_t pread(int fd, void *buf, size_t len, off_t offset) /* fpos lock */ fpos = dfs_file_get_fpos(file); - dfs_file_lseek(file, offset, SEEK_SET); - result = dfs_file_read(file, buf, len); - dfs_file_lseek(file, fpos, SEEK_SET); + result = dfs_file_pread(file, buf, len, offset); /* fpos unlock */ dfs_file_set_fpos(file, fpos); if (result < 0) @@ -1411,9 +1410,7 @@ ssize_t pwrite(int fd, const void *buf, size_t len, off_t offset) } /* fpos lock */ fpos = dfs_file_get_fpos(file); - dfs_file_lseek(file, offset, SEEK_SET); - result = dfs_file_write(file, buf, len); - dfs_file_lseek(file, fpos, SEEK_SET); + result = dfs_file_pwrite(file, buf, len, offset); /* fpos unlock */ dfs_file_set_fpos(file, fpos); if (result < 0) diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index 486dae65257..5763ab80158 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -57,17 +57,6 @@ menuconfig RT_USING_SERIAL default 64 endif -config RT_USING_TTY - bool "Using TTY SYSTEM" - depends on RT_USING_SMART - default y - -if RT_USING_TTY - config RT_TTY_DEBUG - bool "Using TTY DEBUG" - default n -endif - config RT_USING_CAN bool "Using CAN device drivers" default n @@ -811,6 +800,10 @@ menuconfig RT_USING_WIFI bool "MSH command Enable" default y + config RT_WLAN_JOIN_SCAN_BY_MGNT + bool "Enable wlan join scan" + default y + config RT_WLAN_AUTO_CONNECT_ENABLE bool "Auto connect Enable" select RT_WLAN_CFG_ENABLE diff --git a/components/drivers/can/can.c b/components/drivers/can/can.c index a6c23d8f763..2ebab4afbc7 100644 --- a/components/drivers/can/can.c +++ b/components/drivers/can/can.c @@ -152,7 +152,7 @@ rt_inline int _can_int_tx(struct rt_can_device *can, const struct rt_can_msg *da rt_list_remove(&tx_tosnd->list); rt_hw_interrupt_enable(level); - no = ((rt_uint32_t)tx_tosnd - (rt_uint32_t)tx_fifo->buffer) / sizeof(struct rt_can_sndbxinx_list); + no = ((rt_ubase_t)tx_tosnd - (rt_ubase_t)tx_fifo->buffer) / sizeof(struct rt_can_sndbxinx_list); tx_tosnd->result = RT_CAN_SND_RESULT_WAIT; rt_completion_init(&tx_tosnd->completion); if (can->ops->sendmsg(can, data, no) != RT_EOK) @@ -407,20 +407,24 @@ static rt_err_t rt_can_close(struct rt_device *dev) { struct rt_can_rx_fifo *rx_fifo; + /* clear can rx interrupt */ + can->ops->control(can, RT_DEVICE_CTRL_CLR_INT, (void *)RT_DEVICE_FLAG_INT_RX); + rx_fifo = (struct rt_can_rx_fifo *)can->can_rx; RT_ASSERT(rx_fifo != RT_NULL); rt_free(rx_fifo); dev->open_flag &= ~RT_DEVICE_FLAG_INT_RX; can->can_rx = RT_NULL; - /* clear can rx interrupt */ - can->ops->control(can, RT_DEVICE_CTRL_CLR_INT, (void *)RT_DEVICE_FLAG_INT_RX); } if (dev->open_flag & RT_DEVICE_FLAG_INT_TX) { struct rt_can_tx_fifo *tx_fifo; + /* clear can tx interrupt */ + can->ops->control(can, RT_DEVICE_CTRL_CLR_INT, (void *)RT_DEVICE_FLAG_INT_TX); + tx_fifo = (struct rt_can_tx_fifo *)can->can_tx; RT_ASSERT(tx_fifo != RT_NULL); @@ -428,8 +432,6 @@ static rt_err_t rt_can_close(struct rt_device *dev) rt_free(tx_fifo); dev->open_flag &= ~RT_DEVICE_FLAG_INT_TX; can->can_tx = RT_NULL; - /* clear can tx interrupt */ - can->ops->control(can, RT_DEVICE_CTRL_CLR_INT, (void *)RT_DEVICE_FLAG_INT_TX); } can->ops->control(can, RT_DEVICE_CTRL_CLR_INT, (void *)RT_DEVICE_CAN_INT_ERR); @@ -515,7 +517,7 @@ static rt_err_t rt_can_control(struct rt_device *dev, case RT_CAN_CMD_SET_PRIV: /* configure device */ - if ((rt_uint32_t)args != can->config.privmode) + if ((rt_uint32_t)(rt_ubase_t)args != can->config.privmode) { int i; rt_base_t level; diff --git a/components/drivers/clk/clk.c b/components/drivers/clk/clk.c index 17cf878466c..053c67d0a61 100644 --- a/components/drivers/clk/clk.c +++ b/components/drivers/clk/clk.c @@ -1028,7 +1028,7 @@ rt_ssize_t rt_ofw_count_of_clk(struct rt_ofw_node *clk_ofw_np) if (prop) { - rt_uint32_t max_idx, idx; + rt_uint32_t max_idx = 0, idx; for (cell = rt_ofw_prop_next_u32(prop, RT_NULL, &idx); cell; diff --git a/components/drivers/core/device.c b/components/drivers/core/device.c index e59b7697338..c99cddf62ba 100644 --- a/components/drivers/core/device.c +++ b/components/drivers/core/device.c @@ -29,15 +29,19 @@ #include /* for wqueue_init */ #endif /* RT_USING_POSIX_DEVIO */ +#ifdef RT_USING_DFS_V2 +#include +#endif /* RT_USING_DFS_V2 */ + #ifdef RT_USING_DEVICE #ifdef RT_USING_DEVICE_OPS -#define device_init (dev->ops->init) -#define device_open (dev->ops->open) -#define device_close (dev->ops->close) -#define device_read (dev->ops->read) -#define device_write (dev->ops->write) -#define device_control (dev->ops->control) +#define device_init (dev->ops ? dev->ops->init : RT_NULL) +#define device_open (dev->ops ? dev->ops->open : RT_NULL) +#define device_close (dev->ops ? dev->ops->close : RT_NULL) +#define device_read (dev->ops ? dev->ops->read : RT_NULL) +#define device_write (dev->ops ? dev->ops->write : RT_NULL) +#define device_control (dev->ops ? dev->ops->control : RT_NULL) #else #define device_init (dev->init) #define device_open (dev->open) @@ -78,6 +82,10 @@ rt_err_t rt_device_register(rt_device_t dev, rt_wqueue_init(&(dev->wait_queue)); #endif /* RT_USING_POSIX_DEVIO */ +#ifdef RT_USING_DFS_V2 + dfs_devfs_device_add(dev); +#endif /* RT_USING_DFS_V2 */ + return RT_EOK; } RTM_EXPORT(rt_device_register); diff --git a/components/drivers/i2c/SConscript b/components/drivers/i2c/SConscript index aef9f5be9b8..3685e44e2da 100644 --- a/components/drivers/i2c/SConscript +++ b/components/drivers/i2c/SConscript @@ -11,6 +11,8 @@ if GetDepend('RT_USING_I2C_BITOPS'): src = src + ['i2c-bit-ops.c'] if GetDepend('RT_USING_SOFT_I2C'): src = src + ['soft_i2c.c'] +if GetDepend(['RT_USING_DM']): + src += ['i2c_bus.c', 'i2c_dm.c'] # The set of source files associated with this SConscript file. path = [cwd + '/../include'] diff --git a/components/drivers/i2c/i2c_bus.c b/components/drivers/i2c/i2c_bus.c new file mode 100644 index 00000000000..e9626cadd77 --- /dev/null +++ b/components/drivers/i2c/i2c_bus.c @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-12-06 GuEe-GUI first version + */ + +#include + +#define DBG_TAG "i2c.bus" +#define DBG_LVL DBG_INFO +#include + +static struct rt_bus i2c_bus; + +void i2c_bus_scan_clients(struct rt_i2c_bus_device *bus) +{ +#ifdef RT_USING_OFW + if (bus->parent.ofw_node) + { + struct rt_ofw_node *np = bus->parent.ofw_node, *child_np, *i2c_client_np; + + rt_ofw_foreach_available_child_node(np, child_np) + { + rt_uint32_t client_addr; + struct rt_i2c_client *client; + + if (rt_ofw_prop_read_bool(child_np, "compatible")) + { + i2c_client_np = child_np; + } + else + { + /* Maybe in i2c-mux */ + i2c_client_np = rt_ofw_get_next_child(child_np, RT_NULL); + + if (!rt_ofw_prop_read_bool(i2c_client_np, "compatible")) + { + continue; + } + } + + client = rt_calloc(1, sizeof(*client)); + + if (!client) + { + rt_ofw_node_put(i2c_client_np); + LOG_E("Not memory to create i2c client: %s", + rt_ofw_node_full_name(i2c_client_np)); + + return; + } + + rt_ofw_prop_read_u32(i2c_client_np, "reg", &client_addr); + + client->parent.ofw_node = i2c_client_np; + client->name = rt_ofw_node_name(i2c_client_np); + client->bus = bus; + client->client_addr = client_addr; + + rt_i2c_device_register(client); + + if (i2c_client_np != child_np) + { + rt_ofw_node_put(i2c_client_np); + } + } + } +#endif /* RT_USING_OFW */ +} + +rt_err_t rt_i2c_driver_register(struct rt_i2c_driver *driver) +{ + RT_ASSERT(driver != RT_NULL); + + driver->parent.bus = &i2c_bus; + + return rt_driver_register(&driver->parent); +} + +rt_err_t rt_i2c_device_register(struct rt_i2c_client *client) +{ + RT_ASSERT(client != RT_NULL); + + return rt_bus_add_device(&i2c_bus, &client->parent); +} + +static rt_bool_t i2c_match(rt_driver_t drv, rt_device_t dev) +{ + const struct rt_i2c_device_id *id; + struct rt_i2c_driver *driver = rt_container_of(drv, struct rt_i2c_driver, parent); + struct rt_i2c_client *client = rt_container_of(dev, struct rt_i2c_client, parent); + + if ((id = driver->ids)) + { + for (; id->name[0]; ++id) + { + if (!rt_strcmp(id->name, client->name)) + { + client->id = id; + client->ofw_id = RT_NULL; + + return RT_TRUE; + } + } + } + +#ifdef RT_USING_OFW + client->ofw_id = rt_ofw_node_match(client->parent.ofw_node, driver->ofw_ids); + + if (client->ofw_id) + { + client->id = RT_NULL; + + return RT_TRUE; + } +#endif + + return RT_FALSE; +} + +static rt_err_t i2c_probe(rt_device_t dev) +{ + rt_err_t err; + struct rt_i2c_driver *driver = rt_container_of(dev->drv, struct rt_i2c_driver, parent); + struct rt_i2c_client *client = rt_container_of(dev, struct rt_i2c_client, parent); + + if (!client->bus) + { + return -RT_EINVAL; + } + + err = driver->probe(client); + + return err; +} + +static rt_err_t i2c_remove(rt_device_t dev) +{ + struct rt_i2c_driver *driver = rt_container_of(dev->drv, struct rt_i2c_driver, parent); + struct rt_i2c_client *client = rt_container_of(dev, struct rt_i2c_client, parent); + + if (driver && driver->remove) + { + driver->remove(client); + } + + return RT_EOK; +} + +static rt_err_t i2c_shutdown(rt_device_t dev) +{ + struct rt_i2c_driver *driver = rt_container_of(dev->drv, struct rt_i2c_driver, parent); + struct rt_i2c_client *client = rt_container_of(dev, struct rt_i2c_client, parent); + + if (driver && driver->shutdown) + { + driver->shutdown(client); + } + + return RT_EOK; +} + +static struct rt_bus i2c_bus = +{ + .name = "i2c", + .match = i2c_match, + .probe = i2c_probe, + .remove = i2c_remove, + .shutdown = i2c_shutdown, +}; + +static int i2c_bus_init(void) +{ + rt_bus_register(&i2c_bus); + + return 0; +} +INIT_CORE_EXPORT(i2c_bus_init); diff --git a/components/drivers/i2c/i2c_core.c b/components/drivers/i2c/i2c_core.c index 127fdd25a42..2b8e58c90cd 100644 --- a/components/drivers/i2c/i2c_core.c +++ b/components/drivers/i2c/i2c_core.c @@ -32,6 +32,13 @@ rt_err_t rt_i2c_bus_device_register(struct rt_i2c_bus_device *bus, LOG_I("I2C bus [%s] registered", bus_name); +#ifdef RT_USING_DM + if (!res) + { + i2c_bus_scan_clients(bus); + } +#endif + return res; } diff --git a/components/drivers/i2c/i2c_dm.c b/components/drivers/i2c/i2c_dm.c new file mode 100644 index 00000000000..95b1fe63abb --- /dev/null +++ b/components/drivers/i2c/i2c_dm.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-12-06 GuEe-GUI first version + */ + +#include + +#define DBG_TAG "i2c.dm" +#define DBG_LVL DBG_INFO +#include + +#ifdef RT_USING_OFW +static void i2c_parse_timing(struct rt_ofw_node *dev_np, const char *propname, + rt_uint32_t *out_value, rt_uint32_t def_value, rt_bool_t use_defaults) +{ + if (rt_ofw_prop_read_u32(dev_np, propname, out_value) && use_defaults) + { + *out_value = def_value; + } +} + +rt_err_t i2c_timings_ofw_parse(struct rt_ofw_node *dev_np, struct i2c_timings *timings, + rt_bool_t use_defaults) +{ + rt_ubase_t def; + rt_bool_t udef = use_defaults; + struct i2c_timings *t = timings; + + i2c_parse_timing(dev_np, "clock-frequency", &t->bus_freq_hz, I2C_MAX_STANDARD_MODE_FREQ, udef); + + def = t->bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ ? 1000 : t->bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ ? 300 : 120; + i2c_parse_timing(dev_np, "i2c-scl-rising-time-ns", &t->scl_rise_ns, def, udef); + + def = t->bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ ? 300 : 120; + i2c_parse_timing(dev_np, "i2c-scl-falling-time-ns", &t->scl_fall_ns, def, udef); + + i2c_parse_timing(dev_np, "i2c-scl-internal-delay-ns", &t->scl_int_delay_ns, 0, udef); + i2c_parse_timing(dev_np, "i2c-sda-falling-time-ns", &t->sda_fall_ns, t->scl_fall_ns, udef); + i2c_parse_timing(dev_np, "i2c-sda-hold-time-ns", &t->sda_hold_ns, 0, udef); + i2c_parse_timing(dev_np, "i2c-digital-filter-width-ns", &t->digital_filter_width_ns, 0, udef); + i2c_parse_timing(dev_np, "i2c-analog-filter-cutoff-frequency", &t->analog_filter_cutoff_freq_hz, 0, udef); + + return RT_EOK; +} +#endif /* RT_USING_OFW */ diff --git a/components/drivers/include/drivers/i2c.h b/components/drivers/include/drivers/i2c.h index ed874252603..0473a1e8dd8 100644 --- a/components/drivers/include/drivers/i2c.h +++ b/components/drivers/include/drivers/i2c.h @@ -63,10 +63,42 @@ struct rt_i2c_bus_device struct rt_i2c_client { +#ifdef RT_USING_DM + struct rt_device parent; + + const char *name; + const struct rt_i2c_device_id *id; + const struct rt_ofw_node_id *ofw_id; +#endif struct rt_i2c_bus_device *bus; rt_uint16_t client_addr; }; +#ifdef RT_USING_DM +struct rt_i2c_device_id +{ + char name[20]; + void *data; +}; + +struct rt_i2c_driver +{ + struct rt_driver parent; + + const struct rt_i2c_device_id *ids; + const struct rt_ofw_node_id *ofw_ids; + + rt_err_t (*probe)(struct rt_i2c_client *client); + rt_err_t (*remove)(struct rt_i2c_client *client); + rt_err_t (*shutdown)(struct rt_i2c_client *client); +}; + +rt_err_t rt_i2c_driver_register(struct rt_i2c_driver *driver); +rt_err_t rt_i2c_device_register(struct rt_i2c_client *client); + +#define RT_I2C_DRIVER_EXPORT(driver) RT_DRIVER_EXPORT(driver, i2c, BUILIN) +#endif /* RT_USING_DM */ + rt_err_t rt_i2c_bus_device_register(struct rt_i2c_bus_device *bus, const char *bus_name); struct rt_i2c_bus_device *rt_i2c_bus_device_find(const char *bus_name); diff --git a/components/drivers/include/drivers/i2c_dm.h b/components/drivers/include/drivers/i2c_dm.h new file mode 100644 index 00000000000..4f5b251c609 --- /dev/null +++ b/components/drivers/include/drivers/i2c_dm.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-11-26 GuEe-GUI first version + */ + +#ifndef __I2C_DM_H__ +#define __I2C_DM_H__ + +#include +#include +#include + +/* I2C Frequency Modes */ +#define I2C_MAX_STANDARD_MODE_FREQ 100000 +#define I2C_MAX_FAST_MODE_FREQ 400000 +#define I2C_MAX_FAST_MODE_PLUS_FREQ 1000000 +#define I2C_MAX_TURBO_MODE_FREQ 1400000 +#define I2C_MAX_HIGH_SPEED_MODE_FREQ 3400000 +#define I2C_MAX_ULTRA_FAST_MODE_FREQ 5000000 + +struct i2c_timings +{ + rt_uint32_t bus_freq_hz; /* the bus frequency in Hz */ + rt_uint32_t scl_rise_ns; /* time SCL signal takes to rise in ns; t(r) in the I2C specification */ + rt_uint32_t scl_fall_ns; /* time SCL signal takes to fall in ns; t(f) in the I2C specification */ + rt_uint32_t scl_int_delay_ns; /* time IP core additionally needs to setup SCL in ns */ + rt_uint32_t sda_fall_ns; /* time SDA signal takes to fall in ns; t(f) in the I2C specification */ + rt_uint32_t sda_hold_ns; /* time IP core additionally needs to hold SDA in ns */ + rt_uint32_t digital_filter_width_ns; /* width in ns of spikes on i2c lines that the IP core digital filter can filter out */ + rt_uint32_t analog_filter_cutoff_freq_hz; /* threshold frequency for the low pass IP core analog filter */ +}; + +#ifdef RT_USING_OFW +rt_err_t i2c_timings_ofw_parse(struct rt_ofw_node *dev_np, struct i2c_timings *timings, + rt_bool_t use_defaults); +#else +rt_inline rt_err_t i2c_timings_ofw_parse(struct rt_ofw_node *dev_np, struct i2c_timings *timings, + rt_bool_t use_defaults) +{ + return RT_EOK; +} +#endif /* RT_USING_OFW */ + +void i2c_bus_scan_clients(struct rt_i2c_bus_device *bus); + +#endif /* __I2C_DM_H__ */ diff --git a/components/drivers/include/drivers/pic.h b/components/drivers/include/drivers/pic.h index 33c8c390bfe..8429007d16f 100755 --- a/components/drivers/include/drivers/pic.h +++ b/components/drivers/include/drivers/pic.h @@ -107,7 +107,7 @@ struct rt_pic_irq rt_uint32_t mode; rt_uint32_t priority; - RT_DECLARE_BITMAP(affinity, RT_CPUS_NR); + RT_BITMAP_DECLARE(affinity, RT_CPUS_NR); rt_list_t list; rt_list_t children_nodes; diff --git a/components/drivers/include/drivers/pin.h b/components/drivers/include/drivers/pin.h index 53e4465f8d5..22d4328e164 100644 --- a/components/drivers/include/drivers/pin.h +++ b/components/drivers/include/drivers/pin.h @@ -128,7 +128,7 @@ struct rt_pin_ops { void (*pin_mode)(struct rt_device *device, rt_base_t pin, rt_uint8_t mode); void (*pin_write)(struct rt_device *device, rt_base_t pin, rt_uint8_t value); - rt_int8_t (*pin_read)(struct rt_device *device, rt_base_t pin); + rt_ssize_t (*pin_read)(struct rt_device *device, rt_base_t pin); rt_err_t (*pin_attach_irq)(struct rt_device *device, rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args); rt_err_t (*pin_detach_irq)(struct rt_device *device, rt_base_t pin); @@ -145,8 +145,8 @@ struct rt_pin_ops int rt_device_pin_register(const char *name, const struct rt_pin_ops *ops, void *user_data); void rt_pin_mode(rt_base_t pin, rt_uint8_t mode); -void rt_pin_write(rt_base_t pin, rt_uint8_t value); -rt_int8_t rt_pin_read(rt_base_t pin); +void rt_pin_write(rt_base_t pin, rt_ssize_t value); +rt_ssize_t rt_pin_read(rt_base_t pin); rt_base_t rt_pin_get(const char *name); rt_err_t rt_pin_attach_irq(rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args); diff --git a/components/drivers/include/drivers/serial.h b/components/drivers/include/drivers/serial.h index 9435249cd84..9438ed43f95 100644 --- a/components/drivers/include/drivers/serial.h +++ b/components/drivers/include/drivers/serial.h @@ -26,10 +26,16 @@ #define BAUD_RATE_230400 230400 #define BAUD_RATE_460800 460800 #define BAUD_RATE_500000 500000 +#define BAUD_RATE_576000 576000 #define BAUD_RATE_921600 921600 +#define BAUD_RATE_1000000 1000000 +#define BAUD_RATE_1152000 1152000 +#define BAUD_RATE_1500000 1500000 #define BAUD_RATE_2000000 2000000 #define BAUD_RATE_2500000 2500000 #define BAUD_RATE_3000000 3000000 +#define BAUD_RATE_3500000 3500000 +#define BAUD_RATE_4000000 4000000 #define DATA_BITS_5 5 #define DATA_BITS_6 6 @@ -96,6 +102,14 @@ 0 \ } +/** + * @brief Sets a hook function when RX indicate is called + * + * @param thread is the target thread that initializing + */ +typedef void (*rt_hw_serial_rxind_hookproto_t)(rt_device_t dev, rt_size_t size); +RT_OBJECT_HOOKLIST_DECLARE(rt_hw_serial_rxind_hookproto_t, rt_hw_serial_rxind); + struct serial_configure { rt_uint32_t baud_rate; @@ -179,4 +193,6 @@ rt_err_t rt_hw_serial_register(struct rt_serial_device *serial, rt_uint32_t flag, void *data); +rt_err_t rt_hw_serial_register_tty(struct rt_serial_device *serial); + #endif diff --git a/components/drivers/serial/serial_dm.h b/components/drivers/include/drivers/serial_dm.h similarity index 100% rename from components/drivers/serial/serial_dm.h rename to components/drivers/include/drivers/serial_dm.h diff --git a/components/drivers/include/drivers/serial_v2.h b/components/drivers/include/drivers/serial_v2.h index 76c44333bdb..d0dcf378139 100644 --- a/components/drivers/include/drivers/serial_v2.h +++ b/components/drivers/include/drivers/serial_v2.h @@ -103,6 +103,14 @@ 0 \ } +/** + * @brief Sets a hook function when RX indicate is called + * + * @param thread is the target thread that initializing + */ +typedef void (*rt_hw_serial_rxind_hookproto_t)(rt_device_t dev, rt_size_t size); +RT_OBJECT_HOOKLIST_DECLARE(rt_hw_serial_rxind_hookproto_t, rt_hw_serial_rxind); + struct serial_configure { rt_uint32_t baud_rate; @@ -191,4 +199,5 @@ rt_err_t rt_hw_serial_register(struct rt_serial_device *serial, rt_uint32_t flag, void *data); +rt_err_t rt_hw_serial_register_tty(struct rt_serial_device *serial); #endif diff --git a/components/drivers/include/ipc/completion.h b/components/drivers/include/ipc/completion.h index efa2b7840d9..266ddd281ed 100644 --- a/components/drivers/include/ipc/completion.h +++ b/components/drivers/include/ipc/completion.h @@ -33,5 +33,6 @@ void rt_completion_init(struct rt_completion *completion); rt_err_t rt_completion_wait(struct rt_completion *completion, rt_int32_t timeout); void rt_completion_done(struct rt_completion *completion); +rt_err_t rt_completion_wakeup(struct rt_completion *completion); #endif diff --git a/components/drivers/include/ipc/condvar.h b/components/drivers/include/ipc/condvar.h new file mode 100644 index 00000000000..1211df420d1 --- /dev/null +++ b/components/drivers/include/ipc/condvar.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-20 Shell Add cond var API in kernel + */ + +#ifndef __LWP_TERMINAL_CONDVAR_H__ +#define __LWP_TERMINAL_CONDVAR_H__ + +#include + +typedef struct rt_condvar +{ +#ifdef USING_RT_OBJECT + struct rt_object parent; +#endif + rt_atomic_t waiters_cnt; + rt_atomic_t waiting_mtx; + struct rt_wqueue event; +} *rt_condvar_t; + +void rt_condvar_init(rt_condvar_t cv, char *name); +int rt_condvar_timedwait(rt_condvar_t cv, rt_mutex_t mtx, int suspend_flag, + rt_tick_t timeout); +int rt_condvar_signal(rt_condvar_t cv); +int rt_condvar_broadcast(rt_condvar_t cv); + +rt_inline void rt_condvar_detach(rt_condvar_t cv) +{ + RT_UNUSED(cv); + return ; +} + +#endif /* __LWP_TERMINAL_CONDVAR_H__ */ diff --git a/components/drivers/include/ipc/pipe.h b/components/drivers/include/ipc/pipe.h index 94ac10f635e..fdba84a57e0 100644 --- a/components/drivers/include/ipc/pipe.h +++ b/components/drivers/include/ipc/pipe.h @@ -12,6 +12,7 @@ #include #include +#include "condvar.h" /** * Pipe Device @@ -34,6 +35,7 @@ struct rt_pipe_device int writer; int reader; + struct rt_condvar waitfor_parter; struct rt_mutex lock; }; typedef struct rt_pipe_device rt_pipe_t; diff --git a/components/drivers/include/ipc/waitqueue.h b/components/drivers/include/ipc/waitqueue.h index 073300a72e9..dcc01ceff94 100644 --- a/components/drivers/include/ipc/waitqueue.h +++ b/components/drivers/include/ipc/waitqueue.h @@ -49,6 +49,7 @@ int rt_wqueue_wait(rt_wqueue_t *queue, int condition, int timeout); int rt_wqueue_wait_killable(rt_wqueue_t *queue, int condition, int timeout); int rt_wqueue_wait_interruptible(rt_wqueue_t *queue, int condition, int timeout); void rt_wqueue_wakeup(rt_wqueue_t *queue, void *key); +void rt_wqueue_wakeup_all(rt_wqueue_t *queue, void *key); #define DEFINE_WAIT_FUNC(name, function) \ struct rt_wqueue_node name = { \ diff --git a/components/drivers/include/rtdevice.h b/components/drivers/include/rtdevice.h index 5da3c955d66..afb5bb2533d 100644 --- a/components/drivers/include/rtdevice.h +++ b/components/drivers/include/rtdevice.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -26,6 +27,7 @@ #include "ipc/completion.h" #include "ipc/dataqueue.h" #include "ipc/workqueue.h" +#include "ipc/condvar.h" #include "ipc/waitqueue.h" #include "ipc/pipe.h" #include "ipc/poll.h" @@ -37,6 +39,23 @@ extern "C" { #define RT_DEVICE(device) ((rt_device_t)device) +#ifdef RT_USING_DM +#include "drivers/core/dm.h" +#include "drivers/platform.h" + +#ifdef RT_USING_OFW +#include "drivers/ofw.h" +#include "drivers/ofw_fdt.h" +#include "drivers/ofw_io.h" +#include "drivers/ofw_irq.h" +#include "drivers/ofw_raw.h" +#endif /* RT_USING_OFW */ + +#ifdef RT_USING_PIC +#include "drivers/pic.h" +#endif +#endif /* RT_USING_DM */ + #ifdef RT_USING_RTC #include "drivers/rtc.h" #ifdef RT_USING_ALARM @@ -79,6 +98,10 @@ extern "C" { #ifdef RT_USING_I2C_BITOPS #include "drivers/i2c-bit-ops.h" #endif /* RT_USING_I2C_BITOPS */ + +#ifdef RT_USING_DM +#include "drivers/i2c_dm.h" +#endif /* RT_USING_DM */ #endif /* RT_USING_I2C */ #ifdef RT_USING_PHY @@ -181,23 +204,6 @@ extern "C" { #include "drivers/clk.h" #endif /* RT_USING_CLK */ -#ifdef RT_USING_DM -#include "drivers/core/dm.h" -#include "drivers/platform.h" - -#ifdef RT_USING_OFW -#include "drivers/ofw.h" -#include "drivers/ofw_fdt.h" -#include "drivers/ofw_io.h" -#include "drivers/ofw_irq.h" -#include "drivers/ofw_raw.h" -#endif /* RT_USING_OFW */ - -#ifdef RT_USING_PIC -#include "drivers/pic.h" -#endif -#endif /* RT_USING_DM */ - #ifdef __cplusplus } #endif diff --git a/components/drivers/ipc/completion.c b/components/drivers/ipc/completion.c index d74fcdc8d1c..824f5381296 100644 --- a/components/drivers/ipc/completion.c +++ b/components/drivers/ipc/completion.c @@ -134,7 +134,7 @@ RTM_EXPORT(rt_completion_wait); * * @param completion is a pointer to a completion object. */ -void rt_completion_done(struct rt_completion *completion) +static int _completion_done(struct rt_completion *completion) { rt_base_t level; rt_err_t error; @@ -145,7 +145,7 @@ void rt_completion_done(struct rt_completion *completion) if (RT_COMPLETION_FLAG(completion) == RT_COMPLETED) { rt_spin_unlock_irqrestore(&_completion_lock, level); - return; + return -RT_EBUSY; } suspend_thread = RT_COMPLETION_THREAD(completion); @@ -160,10 +160,38 @@ void rt_completion_done(struct rt_completion *completion) LOG_D("%s: failed to resume thread", __func__); } } + else + { + /* no thread waiting */ + error = -RT_EEMPTY; + } completion->susp_thread_n_flag = RT_COMPLETION_NEW_STAT(RT_NULL, RT_COMPLETED); rt_spin_unlock_irqrestore(&_completion_lock, level); + + return error; +} + +/** + * @brief This function indicates a completion has done. + * + * @param completion is a pointer to a completion object. + */ +void rt_completion_done(struct rt_completion *completion) +{ + _completion_done(completion); } RTM_EXPORT(rt_completion_done); +/** + * @brief This function indicates a completion has done and wakeup the thread + * + * @param completion is a pointer to a completion object. + */ +rt_err_t rt_completion_wakeup(struct rt_completion *completion) +{ + return _completion_done(completion); +} +RTM_EXPORT(rt_completion_wakeup); + diff --git a/components/drivers/ipc/condvar.c b/components/drivers/ipc/condvar.c new file mode 100644 index 00000000000..1eb42dc9add --- /dev/null +++ b/components/drivers/ipc/condvar.c @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-20 Shell Support of condition variable + */ +#define DBG_TAG "ipc.condvar" +#define DBG_LVL DBG_INFO +#include + +#include +#include +#include + +static struct rt_spinlock _local_cv_queue_lock = RT_SPINLOCK_INIT; + +#define CV_ASSERT_LOCKED(cv) \ + RT_ASSERT(!(cv)->waiting_mtx || \ + rt_mutex_get_owner((rt_mutex_t)(cv)->waiting_mtx) == \ + rt_thread_self()) + +void rt_condvar_init(rt_condvar_t cv, char *name) +{ +#ifdef USING_RT_OBJECT + /* TODO: support rt object */ + rt_object_init(); +#endif + + rt_wqueue_init(&cv->event); + rt_atomic_store(&cv->waiters_cnt, 0); + rt_atomic_store(&cv->waiting_mtx, 0); +} + +static int _waitq_inqueue(rt_wqueue_t *queue, struct rt_wqueue_node *node, + rt_tick_t timeout, int suspend_flag) +{ + rt_thread_t tcb = node->polling_thread; + rt_timer_t timer = &(tcb->thread_timer); + rt_err_t ret; + + if (queue->flag != RT_WQ_FLAG_WAKEUP) + { + ret = rt_thread_suspend_with_flag(tcb, suspend_flag); + if (ret == RT_EOK) + { + rt_wqueue_add(queue, node); + if (timeout != RT_WAITING_FOREVER) + { + rt_timer_control(timer, RT_TIMER_CTRL_SET_TIME, &timeout); + + rt_timer_start(timer); + } + } + } + else + { + ret = RT_EOK; + } + + return ret; +} + +#define INIT_WAITQ_NODE(node) \ + { \ + .polling_thread = rt_thread_self(), .key = 0, \ + .wakeup = __wqueue_default_wake, .wqueue = &cv->event, \ + .list = RT_LIST_OBJECT_INIT(node.list) \ + } + +int rt_condvar_timedwait(rt_condvar_t cv, rt_mutex_t mtx, int suspend_flag, + rt_tick_t timeout) +{ + rt_err_t acq_mtx_succ, rc; + rt_atomic_t waiting_mtx; + struct rt_wqueue_node node = INIT_WAITQ_NODE(node); + + /* not allowed in IRQ & critical section */ + RT_DEBUG_SCHEDULER_AVAILABLE(1); + CV_ASSERT_LOCKED(cv); + + /** + * for the worst case, this is racy with the following works to reset field + * before mutex is taken. The spinlock then comes to rescue. + */ + rt_spin_lock(&_local_cv_queue_lock); + waiting_mtx = rt_atomic_load(&cv->waiting_mtx); + if (!waiting_mtx) + acq_mtx_succ = rt_atomic_compare_exchange_strong( + &cv->waiting_mtx, &waiting_mtx, (size_t)mtx); + else + acq_mtx_succ = 0; + + rt_spin_unlock(&_local_cv_queue_lock); + + if (acq_mtx_succ == 1 || waiting_mtx == (size_t)mtx) + { + rt_atomic_add(&cv->waiters_cnt, 1); + + rt_enter_critical(); + + if (suspend_flag == RT_INTERRUPTIBLE) + rc = _waitq_inqueue(&cv->event, &node, timeout, RT_INTERRUPTIBLE); + else /* UNINTERRUPTIBLE is forbidden, since it's not safe for user space */ + rc = _waitq_inqueue(&cv->event, &node, timeout, RT_KILLABLE); + + acq_mtx_succ = rt_mutex_release(mtx); + RT_ASSERT(acq_mtx_succ == 0); + rt_exit_critical(); + + if (rc == RT_EOK) + { + rt_schedule(); + + rc = rt_get_errno(); + rc = rc > 0 ? -rc : rc; + } + else + { + LOG_D("%s() failed to suspend", __func__); + } + + rt_wqueue_remove(&node); + + rt_spin_lock(&_local_cv_queue_lock); + if (rt_atomic_add(&cv->waiters_cnt, -1) == 1) + { + waiting_mtx = (size_t)mtx; + acq_mtx_succ = rt_atomic_compare_exchange_strong(&cv->waiting_mtx, + &waiting_mtx, 0); + RT_ASSERT(acq_mtx_succ == 1); + } + rt_spin_unlock(&_local_cv_queue_lock); + + acq_mtx_succ = rt_mutex_take(mtx, RT_WAITING_FOREVER); + RT_ASSERT(acq_mtx_succ == 0); + } + else + { + LOG_D("%s: conflict waiting mutex", __func__); + rc = -EBUSY; + } + + return rc; +} + +/** Keep in mind that we always operating when cv.waiting_mtx is taken */ + +int rt_condvar_signal(rt_condvar_t cv) +{ + CV_ASSERT_LOCKED(cv); + + /* to avoid spurious wakeups */ + if (rt_atomic_load(&cv->waiters_cnt) > 0) + rt_wqueue_wakeup(&cv->event, 0); + + cv->event.flag = 0; + return 0; +} + +int rt_condvar_broadcast(rt_condvar_t cv) +{ + CV_ASSERT_LOCKED(cv); + + /* to avoid spurious wakeups */ + if (rt_atomic_load(&cv->waiters_cnt) > 0) + rt_wqueue_wakeup_all(&cv->event, 0); + + cv->event.flag = 0; + return 0; +} diff --git a/components/drivers/ipc/pipe.c b/components/drivers/ipc/pipe.c index acd0c2def67..c39cd6bdc6a 100644 --- a/components/drivers/ipc/pipe.c +++ b/components/drivers/ipc/pipe.c @@ -9,11 +9,13 @@ * 2017-11-08 JasonJiaJie fix memory leak issue when close a pipe. * 2023-06-28 shell return POLLHUP when writer closed its channel on poll() * fix flag test on pipe_fops_open() + * 2023-12-02 shell Make read pipe operation interruptable. */ #include #include #include #include +#include #if defined(RT_USING_POSIX_DEVIO) && defined(RT_USING_POSIX_PIPE) #include @@ -69,12 +71,12 @@ static int pipe_fops_open(struct dfs_file *fd) if ((fd->flags & O_ACCMODE) == O_RDONLY) { - pipe->reader = 1; + pipe->reader += 1; } if ((fd->flags & O_ACCMODE) == O_WRONLY) { - pipe->writer = 1; + pipe->writer += 1; } if (fd->vnode->ref_count == 1) { @@ -86,6 +88,21 @@ static int pipe_fops_open(struct dfs_file *fd) } } + if ((fd->flags & O_ACCMODE) == O_RDONLY && !pipe->writer) + { + /* wait for partner */ + rc = rt_condvar_timedwait(&pipe->waitfor_parter, &pipe->lock, + RT_INTERRUPTIBLE, RT_WAITING_FOREVER); + if (rc != 0) + { + pipe->reader--; + } + } + else if ((fd->flags & O_ACCMODE) == O_WRONLY) + { + rt_condvar_broadcast(&pipe->waitfor_parter); + } + __exit: rt_mutex_release(&pipe->lock); @@ -117,12 +134,12 @@ static int pipe_fops_close(struct dfs_file *fd) if ((fd->flags & O_RDONLY) == O_RDONLY) { - pipe->reader = 0; + pipe->reader -= 1; } if ((fd->flags & O_WRONLY) == O_WRONLY) { - pipe->writer = 0; + pipe->writer -= 1; while (!rt_list_isempty(&pipe->reader_queue.waiting_list)) { rt_wqueue_wakeup(&pipe->reader_queue, (void*)POLLIN); @@ -234,7 +251,8 @@ static ssize_t pipe_fops_read(struct dfs_file *fd, void *buf, size_t count) rt_mutex_release(&pipe->lock); rt_wqueue_wakeup(&pipe->writer_queue, (void*)POLLOUT); - rt_wqueue_wait(&pipe->reader_queue, 0, -1); + if (rt_wqueue_wait_interruptible(&pipe->reader_queue, 0, -1) == -RT_EINTR) + return -EINTR; rt_mutex_take(&pipe->lock, RT_WAITING_FOREVER); } } @@ -309,7 +327,8 @@ static ssize_t pipe_fops_write(struct dfs_file *fd, const void *buf, size_t coun rt_mutex_release(&pipe->lock); rt_wqueue_wakeup(&pipe->reader_queue, (void*)POLLIN); /* pipe full, waiting on suspended write list */ - rt_wqueue_wait(&pipe->writer_queue, 0, -1); + if (rt_wqueue_wait_interruptible(&pipe->writer_queue, 0, -1) == -RT_EINTR) + return -EINTR; rt_mutex_take(&pipe->lock, -1); } rt_mutex_release(&pipe->lock); @@ -611,6 +630,8 @@ rt_pipe_t *rt_pipe_create(const char *name, int bufsz) rt_mutex_init(&pipe->lock, name, RT_IPC_FLAG_FIFO); rt_wqueue_init(&pipe->reader_queue); rt_wqueue_init(&pipe->writer_queue); + rt_condvar_init(&pipe->waitfor_parter, "piwfp"); + pipe->writer = 0; pipe->reader = 0; @@ -674,6 +695,7 @@ int rt_pipe_delete(const char *name) pipe = (rt_pipe_t *)device; + rt_condvar_detach(&pipe->waitfor_parter); rt_mutex_detach(&pipe->lock); #if defined(RT_USING_POSIX_DEVIO) && defined(RT_USING_POSIX_PIPE) resource_id_put(&id_mgr, pipe->pipeno); @@ -736,11 +758,6 @@ int pipe(int fildes[2]) pipe->is_named = RT_FALSE; /* unamed pipe */ pipe->pipeno = pipeno; rt_snprintf(dev_name, sizeof(dev_name), "/dev/%s", dname); - fildes[0] = open(dev_name, O_RDONLY, 0); - if (fildes[0] < 0) - { - return -1; - } fildes[1] = open(dev_name, O_WRONLY, 0); if (fildes[1] < 0) @@ -749,6 +766,12 @@ int pipe(int fildes[2]) return -1; } + fildes[0] = open(dev_name, O_RDONLY, 0); + if (fildes[0] < 0) + { + return -1; + } + return 0; } diff --git a/components/drivers/ipc/waitqueue.c b/components/drivers/ipc/waitqueue.c index 03901a9ba3f..75e14e58446 100644 --- a/components/drivers/ipc/waitqueue.c +++ b/components/drivers/ipc/waitqueue.c @@ -9,7 +9,11 @@ * to blocked thread. * 2022-01-24 THEWON let rt_wqueue_wait return thread->error when using signal * 2023-09-15 xqyjlj perf rt_hw_interrupt_disable/enable + * 2023-11-21 Shell Support wakeup_all */ +#define DBG_TAG "ipc.waitqueue" +#define DBG_LVL DBG_INFO +#include #include #include @@ -64,7 +68,8 @@ int __wqueue_default_wake(struct rt_wqueue_node *wait, void *key) } /** - * @brief This function will wake up a pending thread on the specified waiting queue that meets the conditions. + * @brief This function will wake up a pending thread on the specified + * waiting queue that meets the conditions. * * @param queue is a pointer to the wait queue. * @@ -94,17 +99,89 @@ void rt_wqueue_wakeup(rt_wqueue_t *queue, void *key) entry = rt_list_entry(node, struct rt_wqueue_node, list); if (entry->wakeup(entry, key) == 0) { - rt_thread_resume(entry->polling_thread); - need_schedule = 1; + /** + * even though another thread may interrupt the thread and + * wakeup it meanwhile, we can asuume that condition is ready + */ + entry->polling_thread->error = RT_EOK; + if (!rt_thread_resume(entry->polling_thread)) + { + need_schedule = 1; + + rt_list_remove(&(entry->list)); + + break; + } + } + } + } + rt_spin_unlock_irqrestore(&(queue->spinlock), level); + if (need_schedule) + rt_schedule(); + + return; +} + +/** + * @brief This function will wake up all pending thread on the specified + * waiting queue that meets the conditions. + * + * @param queue is a pointer to the wait queue. + * + * @param key is the wakeup conditions, but it is not effective now, because + * default wakeup function always return 0. + * If user wants to use it, user should define their own wakeup + * function. + */ +void rt_wqueue_wakeup_all(rt_wqueue_t *queue, void *key) +{ + rt_base_t level; + int need_schedule = 0; - rt_list_remove(&(entry->list)); - break; + rt_list_t *queue_list; + struct rt_list_node *node; + struct rt_wqueue_node *entry; + + queue_list = &(queue->waiting_list); + + level = rt_spin_lock_irqsave(&(queue->spinlock)); + /* set wakeup flag in the queue */ + queue->flag = RT_WQ_FLAG_WAKEUP; + + if (!(rt_list_isempty(queue_list))) + { + for (node = queue_list->next; node != queue_list; ) + { + entry = rt_list_entry(node, struct rt_wqueue_node, list); + if (entry->wakeup(entry, key) == 0) + { + /** + * even though another thread may interrupt the thread and + * wakeup it meanwhile, we can asuume that condition is ready + */ + entry->polling_thread->error = RT_EOK; + if (!rt_thread_resume(entry->polling_thread)) + { + need_schedule = 1; + } + else + { + /* wakeup happened too soon that waker hadn't slept */ + LOG_D("%s: Thread resume failed", __func__); + } + node = node->next; + } + else + { + node = node->next; } } } rt_spin_unlock_irqrestore(&(queue->spinlock), level); if (need_schedule) rt_schedule(); + + return; } /** @@ -184,7 +261,7 @@ static int _rt_wqueue_wait(rt_wqueue_t *queue, int condition, int msec, int susp rt_wqueue_remove(&__wait); - return tid->error; + return tid->error > 0 ? -tid->error : tid->error; } int rt_wqueue_wait(rt_wqueue_t *queue, int condition, int msec) diff --git a/components/drivers/ipc/workqueue.c b/components/drivers/ipc/workqueue.c index 984c36323f1..9a1301618dd 100644 --- a/components/drivers/ipc/workqueue.c +++ b/components/drivers/ipc/workqueue.c @@ -94,6 +94,7 @@ static rt_err_t _workqueue_submit_work(struct rt_workqueue *queue, struct rt_work *work, rt_tick_t ticks) { rt_base_t level; + rt_err_t err; level = rt_spin_lock_irqsave(&(queue->spinlock)); @@ -125,7 +126,6 @@ static rt_err_t _workqueue_submit_work(struct rt_workqueue *queue, /* Timer started */ if (work->flags & RT_WORK_STATE_SUBMITTING) { - rt_timer_stop(&work->timer); rt_timer_control(&work->timer, RT_TIMER_CTRL_SET_TIME, &ticks); } else @@ -137,9 +137,11 @@ static rt_err_t _workqueue_submit_work(struct rt_workqueue *queue, work->workqueue = queue; /* insert delay work list */ rt_list_insert_after(queue->delayed_list.prev, &(work->list)); + + err = rt_timer_start(&(work->timer)); rt_spin_unlock_irqrestore(&(queue->spinlock), level); - rt_timer_start(&(work->timer)); - return RT_EOK; + + return err; } rt_spin_unlock_irqrestore(&(queue->spinlock), level); return -RT_ERROR; @@ -156,7 +158,11 @@ static rt_err_t _workqueue_cancel_work(struct rt_workqueue *queue, struct rt_wor /* Timer started */ if (work->flags & RT_WORK_STATE_SUBMITTING) { - rt_timer_stop(&(work->timer)); + if ((err = rt_timer_stop(&(work->timer))) != RT_EOK) + { + rt_spin_unlock_irqrestore(&(queue->spinlock), level); + return err; + } rt_timer_detach(&(work->timer)); work->flags &= ~RT_WORK_STATE_SUBMITTING; } @@ -174,6 +180,8 @@ static void _delayed_work_timeout_handler(void *parameter) work = (struct rt_work *)parameter; queue = work->workqueue; + + RT_ASSERT(work->flags & RT_WORK_STATE_SUBMITTING); RT_ASSERT(queue != RT_NULL); level = rt_spin_lock_irqsave(&(queue->spinlock)); diff --git a/components/drivers/ktime/inc/ktime.h b/components/drivers/ktime/inc/ktime.h index 5fd5ffb763f..44e2578bcf8 100644 --- a/components/drivers/ktime/inc/ktime.h +++ b/components/drivers/ktime/inc/ktime.h @@ -136,6 +136,7 @@ rt_inline void rt_ktime_hrtimer_keep_errno(rt_ktime_hrtimer_t timer, rt_err_t er RT_ASSERT(timer != RT_NULL); timer->error = err; + rt_set_errno(-err); } /** diff --git a/components/drivers/misc/rt_drv_pwm.c b/components/drivers/misc/rt_drv_pwm.c index 4fcd528adcb..3f2086f3628 100644 --- a/components/drivers/misc/rt_drv_pwm.c +++ b/components/drivers/misc/rt_drv_pwm.c @@ -282,7 +282,8 @@ rt_err_t rt_pwm_set_phase(struct rt_device_pwm *device, int channel, rt_uint32_t return result; } -rt_err_t rt_pwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *cfg) + +static rt_err_t rt_pwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *cfg) { rt_err_t result = RT_EOK; @@ -313,7 +314,8 @@ enum pwm_list_parameters }; CMD_OPTIONS_STATEMENT(pwm_list) -int pwm_list(int argc, char **argv) + +static int pwm_list(int argc, char **argv) { rt_err_t result = -RT_ERROR; char *result_str; diff --git a/components/drivers/ofw/base.c b/components/drivers/ofw/base.c index 8b081bc9d4b..8d629a9f671 100644 --- a/components/drivers/ofw/base.c +++ b/components/drivers/ofw/base.c @@ -870,7 +870,7 @@ struct rt_ofw_node *rt_ofw_get_cpu_node(int cpu, int *thread, rt_bool_t (*match_ rt_ofw_foreach_cpu_node(cpu_np) { - rt_ssize_t prop_len; + rt_ssize_t prop_len = 0; rt_bool_t is_end = RT_FALSE; int tid, addr_cells = rt_ofw_io_addr_cells(cpu_np); const fdt32_t *cell = rt_ofw_prop_read_raw(cpu_np, propname, &prop_len); @@ -1109,17 +1109,20 @@ struct rt_ofw_node *rt_ofw_get_alias_node(const char *tag, int id) if (tag && id >= 0) { - rt_list_for_each_entry(info, &_aliases_nodes, list) + if (!rt_list_isempty(&_aliases_nodes)) { - if (rt_strncmp(info->tag, tag, info->tag_len)) + rt_list_for_each_entry(info, &_aliases_nodes, list) { - continue; - } + if (rt_strncmp(info->tag, tag, info->tag_len)) + { + continue; + } - if (info->id == id) - { - np = info->np; - break; + if (info->id == id) + { + np = info->np; + break; + } } } } @@ -1130,18 +1133,20 @@ struct rt_ofw_node *rt_ofw_get_alias_node(const char *tag, int id) int ofw_alias_node_id(struct rt_ofw_node *np) { int id; - struct alias_info *info; + struct alias_info *info = RT_NULL; if (np) { id = -1; - - rt_list_for_each_entry(info, &_aliases_nodes, list) + if (!rt_list_isempty(&_aliases_nodes)) { - if (info->np == np) + rt_list_for_each_entry(info, &_aliases_nodes, list) { - id = info->id; - break; + if (info->np == np) + { + id = info->id; + break; + } } } } @@ -1161,18 +1166,20 @@ int rt_ofw_get_alias_id(struct rt_ofw_node *np, const char *tag) if (np && tag) { id = -1; - - rt_list_for_each_entry(info, &_aliases_nodes, list) + if (!rt_list_isempty(&_aliases_nodes)) { - if (rt_strncmp(info->tag, tag, info->tag_len)) + rt_list_for_each_entry(info, &_aliases_nodes, list) { - continue; - } + if (rt_strncmp(info->tag, tag, info->tag_len)) + { + continue; + } - if (info->np == np) - { - id = info->id; - break; + if (info->np == np) + { + id = info->id; + break; + } } } } @@ -1192,17 +1199,19 @@ int rt_ofw_get_alias_last_id(const char *tag) if (tag) { id = -1; - - rt_list_for_each_entry(info, &_aliases_nodes, list) + if (!rt_list_isempty(&_aliases_nodes)) { - if (rt_strncmp(info->tag, tag, info->tag_len)) + rt_list_for_each_entry(info, &_aliases_nodes, list) { - continue; - } + if (rt_strncmp(info->tag, tag, info->tag_len)) + { + continue; + } - if (info->id > id) - { - id = info->id; + if (info->id > id) + { + id = info->id; + } } } } @@ -1465,7 +1474,7 @@ static const char *ofw_get_prop_fuzzy_name(const struct rt_ofw_node *np, const c char *sf, split_field[64]; rt_size_t len = 0, max_ak = 0; const char *str, *result = RT_NULL; - RT_DECLARE_BITMAP(ak, sizeof(split_field)); + RT_BITMAP_DECLARE(ak, sizeof(split_field)) = {0}; struct rt_ofw_prop *prop; /* diff --git a/components/drivers/ofw/irq.c b/components/drivers/ofw/irq.c index be843d6cb75..d5b2fb5a301 100755 --- a/components/drivers/ofw/irq.c +++ b/components/drivers/ofw/irq.c @@ -43,7 +43,7 @@ static rt_err_t ofw_parse_irq_map(struct rt_ofw_node *np, struct rt_ofw_cell_arg struct rt_ofw_node *ic_np = RT_NULL; const fdt32_t *addr, *map, *map_mask; int child_address_cells, child_interrupt_cells; - int parent_address_cells, parent_interrupt_cells; + int parent_address_cells = 0, parent_interrupt_cells = 0; int addr_cells, pin_cells, icaddr_cells, idx1, idx2, limit; /* @@ -624,7 +624,7 @@ int rt_ofw_get_irq(struct rt_ofw_node *np, int index) if ((rt_int64_t)cpuid >= 0) { - RT_DECLARE_BITMAP(affinity, RT_CPUS_NR) = { 0 }; + RT_BITMAP_DECLARE(affinity, RT_CPUS_NR) = { 0 }; rt_bitmap_set_bit(affinity, cpuid); diff --git a/components/drivers/ofw/ofw.c b/components/drivers/ofw/ofw.c index 23e03072e9f..1f30bd98f9d 100644 --- a/components/drivers/ofw/ofw.c +++ b/components/drivers/ofw/ofw.c @@ -12,7 +12,7 @@ #include #include #include -#include "../serial/serial_dm.h" +#include #define DBG_TAG "rtdm.ofw" #define DBG_LVL DBG_INFO diff --git a/components/drivers/pic/pic-gic-common.h b/components/drivers/pic/pic-gic-common.h index 0a2c7a006fa..2734d434a2f 100644 --- a/components/drivers/pic/pic-gic-common.h +++ b/components/drivers/pic/pic-gic-common.h @@ -12,10 +12,6 @@ #define __IRQ_GIC_COMMON_H__ #include - -#ifdef RT_PCI_MSI -#include -#endif #include #define GIC_SGI_NR 16 diff --git a/components/drivers/pic/pic_rthw.c b/components/drivers/pic/pic_rthw.c index b46c7bc26d4..e83f12a1fa9 100644 --- a/components/drivers/pic/pic_rthw.c +++ b/components/drivers/pic/pic_rthw.c @@ -66,7 +66,7 @@ void rt_hw_interrupt_uninstall(int vector, rt_isr_handler_t handler, void *param #if defined(RT_USING_SMP) || defined(RT_USING_AMP) void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) { - RT_DECLARE_BITMAP(cpu_masks, RT_CPUS_NR) = { cpu_mask }; + RT_BITMAP_DECLARE(cpu_masks, RT_CPUS_NR) = { cpu_mask }; rt_pic_irq_send_ipi(ipi_vector, cpu_masks); } diff --git a/components/drivers/pin/pin.c b/components/drivers/pin/pin.c index 504c243677f..303fb25b274 100644 --- a/components/drivers/pin/pin.c +++ b/components/drivers/pin/pin.c @@ -139,13 +139,13 @@ void rt_pin_mode(rt_base_t pin, rt_uint8_t mode) _hw_pin.ops->pin_mode(&_hw_pin.parent, pin, mode); } -void rt_pin_write(rt_base_t pin, rt_uint8_t value) +void rt_pin_write(rt_base_t pin, rt_ssize_t value) { RT_ASSERT(_hw_pin.ops != RT_NULL); _hw_pin.ops->pin_write(&_hw_pin.parent, pin, value); } -rt_int8_t rt_pin_read(rt_base_t pin) +rt_ssize_t rt_pin_read(rt_base_t pin) { RT_ASSERT(_hw_pin.ops != RT_NULL); return _hw_pin.ops->pin_read(&_hw_pin.parent, pin); diff --git a/components/drivers/pin/pin_ofw.c b/components/drivers/pin/pin_ofw.c index e4c18b17597..29d29d43682 100644 --- a/components/drivers/pin/pin_ofw.c +++ b/components/drivers/pin/pin_ofw.c @@ -20,14 +20,14 @@ static const char * const gpio_suffixes[] = rt_ssize_t rt_ofw_get_named_pin(struct rt_ofw_node *np, const char *propname, int index, rt_uint8_t *out_mode, rt_uint8_t *out_value) { - rt_ssize_t pin; + rt_ssize_t pin = -1; rt_uint8_t mode; rt_uint8_t value; rt_uint32_t flags; char gpios_name[64]; - struct rt_device_pin *pin_dev; - struct rt_ofw_node *pin_dev_np; - struct rt_ofw_cell_args pin_args; + struct rt_device_pin *pin_dev = 0; + struct rt_ofw_node *pin_dev_np = 0; + struct rt_ofw_cell_args pin_args = {0}; if (!np && index < 0) { diff --git a/components/drivers/serial/SConscript b/components/drivers/serial/SConscript index 2211134ef33..7ee41a43318 100644 --- a/components/drivers/serial/SConscript +++ b/components/drivers/serial/SConscript @@ -8,6 +8,9 @@ src = [] if not GetDepend(['RT_USING_SERIAL']): Return('group') +if GetDepend(['RT_USING_SMART']): + src += Glob('serial_tty.c') + if GetDepend(['RT_USING_SERIAL_V2']): src += ['serial_v2.c'] else: diff --git a/components/drivers/serial/serial.c b/components/drivers/serial/serial.c index 0382f3c8569..fef049ae036 100644 --- a/components/drivers/serial/serial.c +++ b/components/drivers/serial/serial.c @@ -57,10 +57,14 @@ #undef putc #endif +RT_OBJECT_HOOKLIST_DEFINE(rt_hw_serial_rxind); + static rt_err_t serial_fops_rx_ind(rt_device_t dev, rt_size_t size) { rt_wqueue_wakeup(&(dev->wait_queue), (void*)POLLIN); + RT_OBJECT_HOOKLIST_CALL(rt_hw_serial_rxind, (dev, size)); + return RT_EOK; } @@ -640,6 +644,11 @@ static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag) /* get open flags */ dev->open_flag = oflag & 0xff; +#ifdef RT_USING_PINCTRL + /* initialize iomux in DM */ + rt_pin_ctrl_confs_apply_by_name(dev, RT_NULL); +#endif + /* initialize the Rx/Tx structure according to open flag */ if (serial->serial_rx == RT_NULL) { @@ -909,7 +918,7 @@ static rt_ssize_t rt_serial_write(struct rt_device *dev, } } -#if defined(RT_USING_POSIX_TERMIOS) && !defined(RT_USING_TTY) +#if defined(RT_USING_POSIX_TERMIOS) struct speed_baudrate_item { speed_t speed; @@ -928,9 +937,16 @@ static const struct speed_baudrate_item _tbl[] = {B230400, BAUD_RATE_230400}, {B460800, BAUD_RATE_460800}, {B500000, BAUD_RATE_500000}, + {B576000, BAUD_RATE_576000}, {B921600, BAUD_RATE_921600}, + {B1000000, BAUD_RATE_1000000}, + {B1152000, BAUD_RATE_1152000}, + {B1500000, BAUD_RATE_1500000}, {B2000000, BAUD_RATE_2000000}, + {B2500000, BAUD_RATE_2500000}, {B3000000, BAUD_RATE_3000000}, + {B3500000, BAUD_RATE_3500000}, + {B4000000, BAUD_RATE_4000000}, }; static speed_t _get_speed(int baudrate) @@ -1002,6 +1018,30 @@ static void _tc_flush(struct rt_serial_device *serial, int queue) } } + +static inline int _termio_to_termios(const struct termio *termio, struct termios *termios) +{ + termios->c_iflag = termio->c_iflag; + termios->c_oflag = termio->c_oflag; + termios->c_cflag = termio->c_cflag; + termios->c_lflag = termio->c_lflag; + termios->c_line = termio->c_line; + rt_memcpy(termios->c_cc, termio->c_cc, NCC); + + return 0; +} + +static inline int _termios_to_termio(const struct termios *termios, struct termio *termio) +{ + termio->c_iflag = (unsigned short)termios->c_iflag; + termio->c_oflag = (unsigned short)termios->c_oflag; + termio->c_cflag = (unsigned short)termios->c_cflag; + termio->c_lflag = (unsigned short)termios->c_lflag; + termio->c_line = termios->c_line; + rt_memcpy(termio->c_cc, termios->c_cc, NCC); + + return 0; +} #endif /* RT_USING_POSIX_TERMIOS */ static rt_err_t rt_serial_control(struct rt_device *dev, @@ -1058,10 +1098,21 @@ static rt_err_t rt_serial_control(struct rt_device *dev, } break; #ifdef RT_USING_POSIX_STDIO -#if defined(RT_USING_POSIX_TERMIOS) && !defined(RT_USING_TTY) +#if defined(RT_USING_POSIX_TERMIOS) case TCGETA: + case TCGETS: { - struct termios *tio = (struct termios*)args; + struct termios *tio, tmp; + + if (cmd == TCGETS) + { + tio = (struct termios*)args; + } + else + { + tio = &tmp; + } + if (tio == RT_NULL) return -RT_EINVAL; tio->c_iflag = 0; @@ -1092,17 +1143,34 @@ static rt_err_t rt_serial_control(struct rt_device *dev, tio->c_cflag |= (PARODD | PARENB); cfsetospeed(tio, _get_speed(serial->config.baud_rate)); + + if (cmd == TCGETA) + { + _termios_to_termio(tio, args); + } } break; - case TCSETAW: case TCSETAF: case TCSETA: + case TCSETSW: + case TCSETSF: + case TCSETS: { int baudrate; struct serial_configure config; + struct termios *tio, tmp; + + if ((cmd >= TCSETA) && (cmd <= TCSETA + 2)) + { + _termio_to_termios(args, &tmp); + tio = &tmp; + } + else + { + tio = (struct termios*)args; + } - struct termios *tio = (struct termios*)args; if (tio == RT_NULL) return -RT_EINVAL; config = serial->config; @@ -1139,6 +1207,7 @@ static rt_err_t rt_serial_control(struct rt_device *dev, serial->ops->configure(serial, &config); } break; +#ifndef RT_USING_TTY case TCFLSH: { int queue = (int)(rt_ubase_t)args; @@ -1149,6 +1218,7 @@ static rt_err_t rt_serial_control(struct rt_device *dev, break; case TCXONC: break; +#endif /*RT_USING_TTY*/ #endif /*RT_USING_POSIX_TERMIOS*/ case TIOCSWINSZ: { @@ -1315,6 +1385,10 @@ rt_err_t rt_hw_serial_register(struct rt_serial_device *serial, device->fops = &_serial_fops; #endif +#if defined(RT_USING_SMART) + rt_hw_serial_register_tty(serial); +#endif + return ret; } @@ -1360,8 +1434,17 @@ void rt_hw_serial_isr(struct rt_serial_device *serial, int event) rt_spin_unlock_irqrestore(&(serial->spinlock), level); } - /* invoke callback */ - if (serial->parent.rx_indicate != RT_NULL) + /** + * Invoke callback. + * First try notify if any, and if notify is existed, rx_indicate() + * is not callback. This separate the priority and makes the reuse + * of same serial device reasonable for RT console. + */ + if (serial->rx_notify.notify) + { + serial->rx_notify.notify(serial->rx_notify.dev); + } + else if (serial->parent.rx_indicate != RT_NULL) { rt_size_t rx_length; @@ -1376,10 +1459,6 @@ void rt_hw_serial_isr(struct rt_serial_device *serial, int event) serial->parent.rx_indicate(&serial->parent, rx_length); } } - if (serial->rx_notify.notify) - { - serial->rx_notify.notify(serial->rx_notify.dev); - } break; } case RT_SERIAL_EVENT_TX_DONE: diff --git a/components/drivers/serial/serial_dm.c b/components/drivers/serial/serial_dm.c index f3847e17e87..c41a1fec165 100644 --- a/components/drivers/serial/serial_dm.c +++ b/components/drivers/serial/serial_dm.c @@ -9,7 +9,7 @@ */ #include -#include "serial_dm.h" +#include int serial_dev_set_name(struct rt_serial_device *sdev) { @@ -82,8 +82,9 @@ void *serial_base_from_args(char *str) return (void *)base; } -struct serial_configure serial_cfg_from_args(char *str) +struct serial_configure serial_cfg_from_args(char *_str) { + char *str = _str; struct serial_configure cfg = RT_SERIAL_CONFIG_DEFAULT; /* Format baudrate/parity/bits/flow (BBBBPNF), Default is 115200n8 */ diff --git a/components/drivers/serial/serial_tty.c b/components/drivers/serial/serial_tty.c new file mode 100644 index 00000000000..4bcc4b639ee --- /dev/null +++ b/components/drivers/serial/serial_tty.c @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-21 Shell init ver. + */ + +#define DBG_TAG "drivers.serial" +#define DBG_LVL DBG_INFO +#include + +#include +#include +#include +#include + +#define TTY_NAME_PREFIX "S" /* (S)erial */ +#define LWP_TTY_WORKQUEUE_PRIORITY 3 + +struct serial_tty_context +{ + struct rt_serial_device *parent; + struct rt_device_notify backup_notify; + struct rt_work work; +}; + +static struct rt_workqueue *_ttyworkq; /* system work queue */ + +#ifndef RT_USING_DM +static rt_atomic_t _device_id_counter = 0; + +static long get_dec_digits(rt_ubase_t val) +{ + long result = 1; + while (1) + { + if (val < 10) + return result; + if (val < 100) + return result + 1; + if (val < 1000) + return result + 2; + if (val < 10000) + return result + 3; + val /= 10000U; + result += 4; + } + return result; +} +#endif + +static char *alloc_device_name(struct rt_serial_device *serial) +{ + char *tty_dev_name; +#ifdef RT_USING_DM + char *serial_name = serial->parent.parent.name; + /* + * if RT_USING_DM is defined, the name of the serial device + * must be obtained using the serial_dev_set_name function, + * and it should begin with "uart". + */ + RT_ASSERT((strlen(serial_name) > strlen("uart")) && (strncmp(serial_name, "uart", 4) == 0)); + long digits_len = (sizeof(TTY_NAME_PREFIX) - 1) /* raw prefix */ + + strlen(serial_name + sizeof("uart") - 1) /* suffix of serial device name*/ + + 1; /* tailing \0 */ + + tty_dev_name = rt_malloc(digits_len); + if (tty_dev_name) + rt_sprintf(tty_dev_name, "%s%s", TTY_NAME_PREFIX, serial_name + sizeof("uart") - 1); +#else + RT_UNUSED(serial); + unsigned int devid = rt_atomic_add(&_device_id_counter, 1); + long digits_len = (sizeof(TTY_NAME_PREFIX) - 1) /* raw prefix */ + + get_dec_digits(devid) + 1; /* tailing \0 */ + + tty_dev_name = rt_malloc(digits_len); + if (tty_dev_name) + rt_sprintf(tty_dev_name, "%s%u", TTY_NAME_PREFIX, devid); +#endif + return tty_dev_name; +} + +#ifdef LWP_DEBUG_INIT +static volatile int _early_input = 0; + +static void _set_debug(rt_device_t dev, rt_size_t size); +RT_OBJECT_HOOKLIST_DEFINE_NODE(rt_hw_serial_rxind, _set_debug_node, _set_debug); + +static void _set_debug(rt_device_t dev, rt_size_t size) +{ + rt_list_remove(&_set_debug_node.list_node); + _early_input = 1; +} + +static void _setup_debug_rxind_hook(void) +{ + rt_hw_serial_rxind_sethook(&_set_debug_node); +} + +int lwp_startup_debug_request(void) +{ + return _early_input; +} + +#else /* !LWP_DEBUG_INIT */ + +static void _setup_debug_rxind_hook(void) +{ + return ; +} + +#endif /* LWP_DEBUG_INIT */ + +static void _tty_rx_notify(struct rt_device *device) +{ + lwp_tty_t tp; + struct serial_tty_context *softc; + + tp = rt_container_of(device, struct lwp_tty, parent); + RT_ASSERT(tp); + + softc = tty_softc(tp); + + if (_ttyworkq) + rt_workqueue_submit_work(_ttyworkq, &softc->work, 0); +} + +static void _tty_rx_worker(struct rt_work *work, void *data) +{ + char input; + rt_ssize_t readbytes; + lwp_tty_t tp = data; + struct serial_tty_context *softc; + struct rt_serial_device *serial; + + tty_lock(tp); + + while (1) + { + softc = tty_softc(tp); + serial = softc->parent; + readbytes = rt_device_read(&serial->parent, -1, &input, 1); + if (readbytes != 1) + { + break; + } + + ttydisc_rint(tp, input, 0); + } + + ttydisc_rint_done(tp); + tty_unlock(tp); +} + +rt_inline void _setup_serial(struct rt_serial_device *serial, lwp_tty_t tp, + struct serial_tty_context *softc) +{ + struct rt_device_notify notify; + + softc->backup_notify = serial->rx_notify; + notify.dev = &tp->parent; + notify.notify = _tty_rx_notify; + + rt_device_init(&serial->parent); + + rt_work_init(&softc->work, _tty_rx_worker, tp); + rt_device_control(&serial->parent, RT_DEVICE_CTRL_NOTIFY_SET, ¬ify); +} + +rt_inline void _restore_serial(struct rt_serial_device *serial, lwp_tty_t tp, + struct serial_tty_context *softc) +{ + rt_device_control(&serial->parent, RT_DEVICE_CTRL_NOTIFY_SET, &softc->backup_notify); +} + +static int _serial_isbusy(struct rt_serial_device *serial) +{ + rt_thread_t user_thread = rt_console_current_user(); + rt_thread_t self_thread = rt_thread_self(); + + return rt_console_get_device() == &serial->parent && + (user_thread != RT_NULL && user_thread != self_thread); +} + +static void serial_tty_outwakeup(struct lwp_tty *tp) +{ + char out_char; + int len; + struct serial_tty_context *context = tty_softc(tp); + struct rt_serial_device *device; + + if (!context || !context->parent) + { + LOG_E("%s: Data corruption", __func__); + return; + } + + device = context->parent; + + if (_serial_isbusy(device)) + { + return ; + } + + while ((len = ttydisc_getc(tp, &out_char, sizeof(out_char))) != 0) + { + device->ops->putc(device, out_char); + + /* discard remaining if emergency output is happened */ + if (_serial_isbusy(device)) + { + break; + } + } +} + +static int serial_tty_open(struct lwp_tty *tp) +{ + struct serial_tty_context *softc; + struct rt_serial_device *serial; + rt_err_t error; + int oflags; + + softc = tty_softc(tp); + serial = softc->parent; + + LOG_D("%s", __func__); + + rt_device_control(&serial->parent, RT_DEVICE_CTRL_CONSOLE_OFLAG, &oflags); + + error = rt_device_open(&serial->parent, oflags); + + if (!error) + { + /** + * to avoid driver accesssing null data, + * these are setup only after tty is registered + */ + _setup_serial(serial, tp, softc); + } + return error; +} + +static void serial_tty_close(struct lwp_tty *tp) +{ + struct serial_tty_context *softc; + struct rt_serial_device *serial; + softc = tty_softc(tp); + serial = softc->parent; + + LOG_D("%s", __func__); + + _restore_serial(serial, tp, softc); + rt_device_close(&serial->parent); +} + +static int serial_tty_ioctl(struct lwp_tty *tp, rt_ubase_t cmd, rt_caddr_t data, + struct rt_thread *td) +{ + int error; + switch (cmd) + { + case TCSETS: + case TCSETSW: + case TCSETSF: + RT_ASSERT(tp->t_devswsoftc); + struct serial_tty_context *softc = (struct serial_tty_context *)(tp->t_devswsoftc); + struct rt_serial_device *serial = softc->parent; + struct termios *termios = (struct termios *)data; + rt_device_control(&(serial->parent), cmd, termios); + error = -ENOIOCTL; + default: + /** + * Note: for the most case, we don't let serial layer handle ioctl, + * for that they can't act properly regarding to the process + * management system, since it is unawared of that. So a ENOSYS is + * returned and caused the TTY layer to handle ioctl itself. + */ + error = -ENOSYS; + break; + } + return error; +} + +static struct lwp_ttydevsw serial_ttydevsw = { + .tsw_open = serial_tty_open, + .tsw_close = serial_tty_close, + .tsw_ioctl = serial_tty_ioctl, + .tsw_outwakeup = serial_tty_outwakeup, +}; + +rt_err_t rt_hw_serial_register_tty(struct rt_serial_device *serial) +{ + rt_err_t rc; + lwp_tty_t tty; + char *dev_name; + struct serial_tty_context *softc; + + if (serial->rx_notify.dev) + { + return -RT_EBUSY; + } + + softc = rt_malloc(sizeof(struct serial_tty_context)); + if (softc) + { + dev_name = alloc_device_name(serial); + + if (dev_name) + { + softc->parent = serial; + tty = lwp_tty_create(&serial_ttydevsw, softc); + if (tty) + { + rc = lwp_tty_register(tty, dev_name); + + if (rc != RT_EOK) + { + rt_free(tty); + rt_free(softc); + } + } + else + { + rt_free(softc); + rc = -RT_ENOMEM; + } + + rt_free(dev_name); + } + else + { + rt_free(softc); + rc = -RT_ENOMEM; + } + } + else + { + rc = -RT_ENOMEM; + } + + return rc; +} + +rt_err_t rt_hw_serial_unregister_tty(struct rt_serial_device *serial) +{ + rt_device_t tty_dev; + lwp_tty_t tp; + struct serial_tty_context *softc; + + tty_dev = serial->rx_notify.dev; + tp = rt_container_of(tty_dev, struct lwp_tty, parent); + + /* restore serial setting */ + softc = tty_softc(tp); + serial->rx_notify = softc->backup_notify; + + tty_rel_gone(tp); + + /* device unregister? */ + rt_device_destroy(&tp->parent); + /* resource free? */ + lwp_tty_delete(tp); + + return RT_EOK; +} + +static int _tty_workqueue_init(void) +{ + if (_ttyworkq != RT_NULL) + return RT_EOK; + + _ttyworkq = rt_workqueue_create("ttyworkq", RT_SYSTEM_WORKQUEUE_STACKSIZE, + LWP_TTY_WORKQUEUE_PRIORITY); + RT_ASSERT(_ttyworkq != RT_NULL); + + _setup_debug_rxind_hook(); + + return RT_EOK; +} +INIT_PREV_EXPORT(_tty_workqueue_init); diff --git a/components/drivers/serial/serial_v2.c b/components/drivers/serial/serial_v2.c index ce657e55f66..d7576dbed87 100644 --- a/components/drivers/serial/serial_v2.c +++ b/components/drivers/serial/serial_v2.c @@ -35,10 +35,14 @@ #undef putc #endif +RT_OBJECT_HOOKLIST_DEFINE(rt_hw_serial_rxind); + static rt_err_t serial_fops_rx_ind(rt_device_t dev, rt_size_t size) { rt_wqueue_wakeup(&(dev->wait_queue), (void*)POLLIN); + RT_OBJECT_HOOKLIST_CALL(rt_hw_serial_rxind, (dev, size)); + return RT_EOK; } diff --git a/components/drivers/spi/spi-bit-ops.c b/components/drivers/spi/spi-bit-ops.c index d03e5007cfe..f551741873b 100644 --- a/components/drivers/spi/spi-bit-ops.c +++ b/components/drivers/spi/spi-bit-ops.c @@ -384,6 +384,11 @@ rt_err_t spi_bit_configure(struct rt_spi_device *device, struct rt_spi_configura RT_ASSERT(device != RT_NULL); RT_ASSERT(configuration != RT_NULL); + if(ops->pin_init != RT_NULL) + { + ops->pin_init(); + } + if (configuration->mode & RT_SPI_SLAVE) { return -RT_EIO; diff --git a/components/drivers/spi/spi-bit-ops.h b/components/drivers/spi/spi-bit-ops.h index b536b3d81e8..d1e83cdeddf 100644 --- a/components/drivers/spi/spi-bit-ops.h +++ b/components/drivers/spi/spi-bit-ops.h @@ -21,6 +21,7 @@ extern "C" { struct rt_spi_bit_ops { void *data; /* private data for lowlevel routines */ + void (*const pin_init)(void); void (*const tog_sclk)(void *data); void (*const set_sclk)(void *data, rt_int32_t state); void (*const set_mosi)(void *data, rt_int32_t state); diff --git a/components/drivers/tty/SConscript b/components/drivers/tty/SConscript deleted file mode 100644 index d972879b70e..00000000000 --- a/components/drivers/tty/SConscript +++ /dev/null @@ -1,10 +0,0 @@ -from building import * - -# The set of source files associated with this SConscript file. -src = Glob('*.c') -cwd = GetCurrentDir() -CPPPATH = [cwd + "/include"] - -group = DefineGroup('tty', src, depend = ['RT_USING_SMART', 'RT_USING_TTY'], CPPPATH = CPPPATH) - -Return('group') diff --git a/components/drivers/tty/console.c b/components/drivers/tty/console.c deleted file mode 100644 index a9c9b887311..00000000000 --- a/components/drivers/tty/console.c +++ /dev/null @@ -1,346 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021.12.07 linzhenxing first version - */ -#include -#include -#include -#include - -#define DBG_TAG "CONSOLE" -#ifdef RT_TTY_DEBUG -#define DBG_LVL DBG_LOG -#else -#define DBG_LVL DBG_INFO -#endif /* RT_TTY_DEBUG */ -#include - -#include -#include - -static struct tty_struct console_dev; -static struct rt_ringbuffer console_rx_ringbuffer; -static struct rt_wqueue console_rx_wqueue; -static rt_thread_t console_rx_thread; -static const size_t rb_bufsz = 0x1000; - -static void console_rx_work(void *parameter) -{ - int len; - char ch; - int lens; - static char buf[0x1000]; - - struct tty_struct *console; - console = &console_dev; - - while (1) - { - rt_wqueue_wait(&console_rx_wqueue, 0, RT_WAITING_FOREVER); - lens = 0; - - while (lens < sizeof(buf)) - { - len = rt_ringbuffer_get(&console_rx_ringbuffer, (void *)&ch, sizeof(ch)); - if (len == 0) - { - break; - } - lens += len; - buf[lens-1] = ch; - } - - if (lens && console->ldisc->ops->receive_buf) - { - console->ldisc->ops->receive_buf((struct tty_struct *)console, buf, lens); - } - } -} - -static int rx_thread_init(void) -{ - void *rb_buffer; - rt_thread_t thread; - - rb_buffer = rt_malloc(rb_bufsz); - rt_ringbuffer_init(&console_rx_ringbuffer, rb_buffer, rb_bufsz); - rt_wqueue_init(&console_rx_wqueue); - - thread = rt_thread_create("console_rx", console_rx_work, &console_dev, rb_bufsz, 10, 10); - if (thread != RT_NULL) - { - rt_thread_startup(thread); - console_rx_thread = thread; - } - - return 0; -} -INIT_COMPONENT_EXPORT(rx_thread_init); - -static void console_rx_notify(struct rt_device *dev) -{ - struct tty_struct *console = NULL; - int len = 0; - int lens = 0; - char ch = 0; - - console = (struct tty_struct *)dev; - RT_ASSERT(console != RT_NULL); - - while (1) - { - len = rt_device_read(console->io_dev, -1, &ch, 1); - if (len == 0) - { - break; - } - lens += len; - rt_ringbuffer_put(&console_rx_ringbuffer, (void *)&ch, sizeof(ch)); - if (lens > rb_bufsz) - { - break; - } - } - if (console_rx_thread) - rt_wqueue_wakeup(&console_rx_wqueue, 0); -} - -struct tty_struct *console_tty_get(void) -{ - return &console_dev; -} - -static void iodev_close(struct tty_struct *console) -{ - struct rt_device_notify rx_notify; - - rx_notify.notify = RT_NULL; - rx_notify.dev = RT_NULL; - - /* clear notify */ - rt_device_control(console->io_dev, RT_DEVICE_CTRL_NOTIFY_SET, &rx_notify); - rt_device_close(console->io_dev); -} - -static rt_err_t iodev_open(struct tty_struct *console) -{ - rt_err_t ret = RT_EOK; - struct rt_device_notify rx_notify; - rt_uint16_t oflags = 0; - - rt_device_control(console->io_dev, RT_DEVICE_CTRL_CONSOLE_OFLAG, &oflags); - - ret = rt_device_open(console->io_dev, oflags); - if (ret != RT_EOK) - { - return -RT_ERROR; - } - - rx_notify.notify = console_rx_notify; - rx_notify.dev = (struct rt_device *)console; - rt_device_control(console->io_dev, RT_DEVICE_CTRL_NOTIFY_SET, &rx_notify); - return RT_EOK; -} - -struct rt_device *console_get_iodev(void) -{ - return console_dev.io_dev; -} - -struct rt_device *console_set_iodev(struct rt_device *iodev) -{ - rt_base_t level = 0; - struct rt_device *io_before = RT_NULL; - struct tty_struct *console = RT_NULL; - - RT_ASSERT(iodev != RT_NULL); - - console = &console_dev; - - level = rt_spin_lock_irqsave(&console->spinlock); - - RT_ASSERT(console->init_flag >= TTY_INIT_FLAG_REGED); - - io_before = console->io_dev; - if (iodev == io_before) - { - goto exit; - } - - if (console->init_flag >= TTY_INIT_FLAG_INITED) - { - /* close old device */ - iodev_close(console); - } - - console->io_dev = iodev; - if (console->init_flag >= TTY_INIT_FLAG_INITED) - { - rt_err_t ret; - /* open new device */ - ret = iodev_open(console); - RT_ASSERT(ret == RT_EOK); - } - -exit: - rt_spin_unlock_irqrestore(&console->spinlock, level); - return io_before; -} - -/* RT-Thread Device Interface */ -/* - * This function initializes console device. - */ -static rt_err_t rt_console_init(struct rt_device *dev) -{ - rt_base_t level = 0; - rt_err_t result = RT_EOK; - struct tty_struct *console = RT_NULL; - - RT_ASSERT(dev != RT_NULL); - - console = (struct tty_struct *)dev; - - level = rt_spin_lock_irqsave(&console->spinlock); - - RT_ASSERT(console->init_flag == TTY_INIT_FLAG_REGED); - - result = iodev_open(console); - if (result != RT_EOK) - { - goto exit; - } - - console->init_flag = TTY_INIT_FLAG_INITED; -exit: - rt_spin_unlock_irqrestore(&console->spinlock, level); - return result; -} - -static rt_err_t rt_console_open(struct rt_device *dev, rt_uint16_t oflag) -{ - rt_err_t result = RT_EOK; - struct tty_struct *console = RT_NULL; - - RT_ASSERT(dev != RT_NULL); - console = (struct tty_struct *)dev; - RT_ASSERT(console != RT_NULL); - RT_ASSERT(console->init_flag == TTY_INIT_FLAG_INITED); - return result; -} - -static rt_err_t rt_console_close(struct rt_device *dev) -{ - rt_err_t result = RT_EOK; - struct tty_struct *console = RT_NULL; - - console = (struct tty_struct *)dev; - RT_ASSERT(console != RT_NULL); - RT_ASSERT(console->init_flag == TTY_INIT_FLAG_INITED); - return result; -} - -static rt_ssize_t rt_console_read(struct rt_device *dev, - rt_off_t pos, - void *buffer, - rt_size_t size) -{ - rt_size_t len = 0; - return len; -} - -static rt_ssize_t rt_console_write(struct rt_device *dev, - rt_off_t pos, - const void *buffer, - rt_size_t size) -{ - rt_size_t len = 0; - struct tty_struct *console = RT_NULL; - - console = (struct tty_struct *)dev; - RT_ASSERT(console != RT_NULL); - RT_ASSERT(console->init_flag == TTY_INIT_FLAG_INITED); - - len = rt_device_write((struct rt_device *)console->io_dev, -1, buffer, size); - - return len; -} - -static rt_err_t rt_console_control(rt_device_t dev, int cmd, void *args) -{ - rt_size_t len = 0; - struct tty_struct *console = RT_NULL; - - console = (struct tty_struct *)dev; - RT_ASSERT(console != RT_NULL); - RT_ASSERT(console->init_flag == TTY_INIT_FLAG_INITED); - - len = rt_device_control((struct rt_device *)console->io_dev, cmd, args); - - return len; -} - -#ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops console_ops = -{ - rt_console_init, - rt_console_open, - rt_console_close, - rt_console_read, - rt_console_write, - rt_console_control, -}; -#endif - -/* - * console register - */ -static struct dfs_file_ops con_fops; -rt_err_t console_register(const char *name, struct rt_device *iodev) -{ - rt_err_t ret = RT_EOK; - struct rt_device *device = RT_NULL; - struct tty_struct *console = &console_dev; - - RT_ASSERT(iodev != RT_NULL); - RT_ASSERT(console->init_flag == TTY_INIT_FLAG_NONE); - - tty_init(console, TTY_DRIVER_TYPE_CONSOLE, SERIAL_TYPE_NORMAL, iodev); - console_ldata_init(console); - - device = &(console->parent); - device->type = RT_Device_Class_Char; - -#ifdef RT_USING_DEVICE_OPS - device->ops = &console_ops; -#else - device->init = rt_console_init; - device->open = rt_console_open; - device->close = rt_console_close; - device->read = rt_console_read; - device->write = rt_console_write; - device->control = rt_console_control; -#endif - - /* register a character device */ - ret = rt_device_register(device, name, 0); - if (ret != RT_EOK) - { - LOG_E("console driver register fail\n"); - } - else - { -#ifdef RT_USING_POSIX_DEVIO - /* set fops */ - memcpy(&con_fops, tty_get_fops(), sizeof(struct dfs_file_ops)); - device->fops = &con_fops; -#endif - } - - return ret; -} diff --git a/components/drivers/tty/include/console.h b/components/drivers/tty/include/console.h deleted file mode 100644 index 653b31fadea..00000000000 --- a/components/drivers/tty/include/console.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021.12.07 linzhenxing first version - */ -#ifndef __CONSOLE_ -#define __CONSOLE_ -#include -#include "tty.h" - -struct tty_struct *console_tty_get(void); -struct rt_device *console_get_iodev(void); -struct rt_device *console_set_iodev(struct rt_device *iodev); -rt_err_t console_register(const char *name, struct rt_device *iodev); -#endif diff --git a/components/drivers/tty/include/tty.h b/components/drivers/tty/include/tty.h deleted file mode 100644 index 79e30b6f515..00000000000 --- a/components/drivers/tty/include/tty.h +++ /dev/null @@ -1,304 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021.12.07 linzhenxing first version - */ -#ifndef __TTY_H__ -#define __TTY_H__ -#include -#include -#include -#ifdef RT_USING_SMART -#include -#endif -#if defined(RT_USING_POSIX_TERMIOS) -#include -#include -#endif - -#ifndef ENOIOCTLCMD -#define ENOIOCTLCMD (515) /* No ioctl command */ -#endif - -#define current lwp_self() -#define __DISABLED_CHAR '\0' - -struct tty_node -{ - struct rt_lwp *lwp; - struct tty_node *next; -}; - -void tty_initstack(struct tty_node *node); -int tty_push(struct tty_node **head, struct rt_lwp *lwp); -struct rt_lwp *tty_pop(struct tty_node **head, struct rt_lwp *target_lwp); -/* - * When a break, frame error, or parity error happens, these codes are - * stuffed into the flags buffer. - */ -#define TTY_NORMAL 0 -#define TTY_BREAK 1 -#define TTY_FRAME 2 -#define TTY_PARITY 3 -#define TTY_OVERRUN 4 - -#define INTR_CHAR(tty) ((tty)->init_termios.c_cc[VINTR]) -#define QUIT_CHAR(tty) ((tty)->init_termios.c_cc[VQUIT]) -#define ERASE_CHAR(tty) ((tty)->init_termios.c_cc[VERASE]) -#define KILL_CHAR(tty) ((tty)->init_termios.c_cc[VKILL]) -#define EOF_CHAR(tty) ((tty)->init_termios.c_cc[VEOF]) -#define TIME_CHAR(tty) ((tty)->init_termios.c_cc[VTIME]) -#define MIN_CHAR(tty) ((tty)->init_termios.c_cc[VMIN]) -#define SWTC_CHAR(tty) ((tty)->init_termios.c_cc[VSWTC]) -#define START_CHAR(tty) ((tty)->init_termios.c_cc[VSTART]) -#define STOP_CHAR(tty) ((tty)->init_termios.c_cc[VSTOP]) -#define SUSP_CHAR(tty) ((tty)->init_termios.c_cc[VSUSP]) -#define EOL_CHAR(tty) ((tty)->init_termios.c_cc[VEOL]) -#define REPRINT_CHAR(tty) ((tty)->init_termios.c_cc[VREPRINT]) -#define DISCARD_CHAR(tty) ((tty)->init_termios.c_cc[VDISCARD]) -#define WERASE_CHAR(tty) ((tty)->init_termios.c_cc[VWERASE]) -#define LNEXT_CHAR(tty) ((tty)->init_termios.c_cc[VLNEXT]) -#define EOL2_CHAR(tty) ((tty)->init_termios.c_cc[VEOL2]) - -#define _I_FLAG(tty,f) ((tty)->init_termios.c_iflag & (f)) -#define _O_FLAG(tty,f) ((tty)->init_termios.c_oflag & (f)) -#define _C_FLAG(tty,f) ((tty)->init_termios.c_cflag & (f)) -#define _L_FLAG(tty,f) ((tty)->init_termios.c_lflag & (f)) - -#define I_IGNBRK(tty) _I_FLAG((tty),IGNBRK) -#define I_BRKINT(tty) _I_FLAG((tty),BRKINT) -#define I_IGNPAR(tty) _I_FLAG((tty),IGNPAR) -#define I_PARMRK(tty) _I_FLAG((tty),PARMRK) -#define I_INPCK(tty) _I_FLAG((tty),INPCK) -#define I_ISTRIP(tty) _I_FLAG((tty),ISTRIP) -#define I_INLCR(tty) _I_FLAG((tty),INLCR) -#define I_IGNCR(tty) _I_FLAG((tty),IGNCR) -#define I_ICRNL(tty) _I_FLAG((tty),ICRNL) -#define I_IUCLC(tty) _I_FLAG((tty),IUCLC) -#define I_IXON(tty) _I_FLAG((tty),IXON) -#define I_IXANY(tty) _I_FLAG((tty),IXANY) -#define I_IXOFF(tty) _I_FLAG((tty),IXOFF) -#define I_IMAXBEL(tty) _I_FLAG((tty),IMAXBEL) -#define I_IUTF8(tty) _I_FLAG((tty), IUTF8) - -#define O_OPOST(tty) _O_FLAG((tty),OPOST) -#define O_OLCUC(tty) _O_FLAG((tty),OLCUC) -#define O_ONLCR(tty) _O_FLAG((tty),ONLCR) -#define O_OCRNL(tty) _O_FLAG((tty),OCRNL) -#define O_ONOCR(tty) _O_FLAG((tty),ONOCR) -#define O_ONLRET(tty) _O_FLAG((tty),ONLRET) -#define O_OFILL(tty) _O_FLAG((tty),OFILL) -#define O_OFDEL(tty) _O_FLAG((tty),OFDEL) -#define O_NLDLY(tty) _O_FLAG((tty),NLDLY) -#define O_CRDLY(tty) _O_FLAG((tty),CRDLY) -#define O_TABDLY(tty) _O_FLAG((tty),TABDLY) -#define O_BSDLY(tty) _O_FLAG((tty),BSDLY) -#define O_VTDLY(tty) _O_FLAG((tty),VTDLY) -#define O_FFDLY(tty) _O_FLAG((tty),FFDLY) - -#define C_BAUD(tty) _C_FLAG((tty),CBAUD) -#define C_CSIZE(tty) _C_FLAG((tty),CSIZE) -#define C_CSTOPB(tty) _C_FLAG((tty),CSTOPB) -#define C_CREAD(tty) _C_FLAG((tty),CREAD) -#define C_PARENB(tty) _C_FLAG((tty),PARENB) -#define C_PARODD(tty) _C_FLAG((tty),PARODD) -#define C_HUPCL(tty) _C_FLAG((tty),HUPCL) -#define C_CLOCAL(tty) _C_FLAG((tty),CLOCAL) -#define C_CIBAUD(tty) _C_FLAG((tty),CIBAUD) -#define C_CRTSCTS(tty) _C_FLAG((tty),CRTSCTS) - -#define L_ISIG(tty) _L_FLAG((tty),ISIG) -#define L_ICANON(tty) _L_FLAG((tty),ICANON) -#define L_XCASE(tty) _L_FLAG((tty),XCASE) -#define L_ECHO(tty) _L_FLAG((tty),ECHO) -#define L_ECHOE(tty) _L_FLAG((tty),ECHOE) -#define L_ECHOK(tty) _L_FLAG((tty),ECHOK) -#define L_ECHONL(tty) _L_FLAG((tty),ECHONL) -#define L_NOFLSH(tty) _L_FLAG((tty),NOFLSH) -#define L_TOSTOP(tty) _L_FLAG((tty),TOSTOP) -#define L_ECHOCTL(tty) _L_FLAG((tty),ECHOCTL) -#define L_ECHOPRT(tty) _L_FLAG((tty),ECHOPRT) -#define L_ECHOKE(tty) _L_FLAG((tty),ECHOKE) -#define L_FLUSHO(tty) _L_FLAG((tty),FLUSHO) -#define L_PENDIN(tty) _L_FLAG((tty),PENDIN) -#define L_IEXTEN(tty) _L_FLAG((tty),IEXTEN) -#define L_EXTPROC(tty) _L_FLAG((tty), EXTPROC) - -/* - * Where all of the state associated with a tty is kept while the tty - * is open. Since the termios state should be kept even if the tty - * has been closed --- for things like the baud rate, etc --- it is - * not stored here, but rather a pointer to the real state is stored - * here. Possible the winsize structure should have the same - * treatment, but (1) the default 80x24 is usually right and (2) it's - * most often used by a windowing system, which will set the correct - * size each time the window is created or resized anyway. - * - TYT, 9/14/92 - */ -struct tty_struct -{ - struct rt_device parent; - int type; - int subtype; - int init_flag; - int index; //for pty - int pts_lock; //for pty - - struct tty_struct *other_struct; //for pty - - struct termios init_termios; - struct winsize winsize; - struct rt_mutex lock; - pid_t pgrp; - pid_t session; - struct rt_lwp *foreground; - struct tty_node *head; - - struct tty_ldisc *ldisc; - void *disc_data; - struct rt_device *io_dev; - - struct rt_wqueue wait_queue; - -#define RT_TTY_BUF 1024 - rt_list_t tty_drivers; - struct rt_spinlock spinlock; -}; - -enum -{ - TTY_INIT_FLAG_NONE = 0, - TTY_INIT_FLAG_ALLOCED, - TTY_INIT_FLAG_REGED, - TTY_INIT_FLAG_INITED, -}; - -#define TTY_DRIVER_TYPE_SYSTEM 0x0001 -#define TTY_DRIVER_TYPE_CONSOLE 0x0002 -#define TTY_DRIVER_TYPE_SERIAL 0x0003 -#define TTY_DRIVER_TYPE_PTY 0x0004 -#define TTY_DRIVER_TYPE_SCC 0x0005 /* scc driver */ -#define TTY_DRIVER_TYPE_SYSCONS 0x0006 - -/* tty magic number */ -#define TTY_MAGIC 0x5401 - -/* - * These bits are used in the flags field of the tty structure. - * - * So that interrupts won't be able to mess up the queues, - * copy_to_cooked must be atomic with respect to itself, as must - * tty->write. Thus, you must use the inline functions set_bit() and - * clear_bit() to make things atomic. - */ -#define TTY_THROTTLED 0 -#define TTY_IO_ERROR 1 -#define TTY_OTHER_CLOSED 2 -#define TTY_EXCLUSIVE 3 -#define TTY_DEBUG 4 -#define TTY_DO_WRITE_WAKEUP 5 -#define TTY_PUSH 6 -#define TTY_CLOSING 7 -#define TTY_DONT_FLIP 8 -#define TTY_HW_COOK_OUT 14 -#define TTY_HW_COOK_IN 15 -#define TTY_PTY_LOCK 16 -#define TTY_NO_WRITE_SPLIT 17 - -#define NR_LDISCS 30 - -/* line disciplines */ -#define N_TTY 0 -#define N_SLIP 1 -#define N_MOUSE 2 -#define N_PPP 3 -#define N_STRIP 4 -#define N_AX25 5 -#define N_X25 6 /* X.25 async */ -#define N_6PACK 7 -#define N_MASC 8 /* Reserved for Mobitex module */ -#define N_R3964 9 /* Reserved for Simatic R3964 module */ -#define N_PROFIBUS_FDL 10 /* Reserved for Profibus */ -#define N_IRDA 11 /* Linux IrDa - http://irda.sourceforge.net/ */ -#define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data */ - /* cards about SMS messages */ -#define N_HDLC 13 /* synchronous HDLC */ -#define N_SYNC_PPP 14 /* synchronous PPP */ -#define N_HCI 15 /* Bluetooth HCI UART */ -#define N_GIGASET_M101 16 /* Siemens Gigaset M101 serial DECT adapter */ -#define N_SLCAN 17 /* Serial / USB serial CAN Adaptors */ -#define N_PPS 18 /* Pulse per Second */ -#define N_V253 19 /* Codec control over voice modem */ -#define N_CAIF 20 /* CAIF protocol for talking to modems */ -#define N_GSM0710 21 /* GSM 0710 Mux */ -#define N_TI_WL 22 /* for TI's WL BT, FM, GPS combo chips */ -#define N_TRACESINK 23 /* Trace data routing for MIPI P1149.7 */ -#define N_TRACEROUTER 24 /* Trace data routing for MIPI P1149.7 */ -#define N_NCI 25 /* NFC NCI UART */ - -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 - -/* pty subtypes */ -#define PTY_TYPE_MASTER 0x0001 -#define PTY_TYPE_SLAVE 0x0002 - -/* serial subtype definitions */ -#define SERIAL_TYPE_NORMAL 1 - -#define max(a, b) ({\ - typeof(a) _a = a;\ - typeof(b) _b = b;\ - _a > _b ? _a : _b; }) - -#define min(a, b) ({\ - typeof(a) _a = a;\ - typeof(b) _b = b;\ - _a < _b ? _a : _b; }) - -void mutex_lock(rt_mutex_t mutex); -void mutex_unlock(rt_mutex_t mutex); -int __tty_check_change(struct tty_struct *tty, int sig); -int tty_check_change(struct tty_struct *tty); - -rt_inline struct rt_wqueue *wait_queue_get(struct rt_lwp *lwp, struct tty_struct *tty) -{ - if (lwp == RT_NULL) - { - return &tty->wait_queue; - } - return &lwp->wait_queue; -} - -rt_inline struct rt_wqueue *wait_queue_current_get(struct rt_lwp *lwp, struct tty_struct *tty) -{ - return wait_queue_get(lwp, tty); -} - -rt_inline void tty_wakeup_check(struct tty_struct *tty) -{ - struct rt_wqueue *wq = NULL; - - wq = wait_queue_current_get(tty->foreground, tty); - rt_wqueue_wakeup(wq, (void*)POLLIN); -} - -int tty_init(struct tty_struct *tty, int type, int subtype, struct rt_device *iodev); -const struct dfs_file_ops *tty_get_fops(void); - -int n_tty_ioctl_extend(struct tty_struct *tty, int cmd, void *arg); - -void console_ldata_init(struct tty_struct *tty); -int n_tty_receive_buf(struct tty_struct *tty, char *cp, int count); - -#endif /*__TTY_H__*/ diff --git a/components/drivers/tty/include/tty_ldisc.h b/components/drivers/tty/include/tty_ldisc.h deleted file mode 100644 index 9b95fd3591c..00000000000 --- a/components/drivers/tty/include/tty_ldisc.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021.12.07 linzhenxing first version - */ -#ifndef __TTY_LDISC_ -#define __TTY_LDISC_ -#include -#include -#include -#include -#if defined(RT_USING_POSIX_TERMIOS) -#include -#endif -struct tty_struct; - -struct tty_ldisc_ops -{ - char *name; - int num; - - int (*open) (struct dfs_file *fd); - int (*close) (struct tty_struct *tty); - int (*ioctl) (struct dfs_file *fd, int cmd, void *args); - int (*read) (struct dfs_file *fd, void *buf, size_t count); - int (*write) (struct dfs_file *fd, const void *buf, size_t count); - int (*flush) (struct dfs_file *fd); - int (*lseek) (struct dfs_file *fd, off_t offset); - int (*getdents) (struct dfs_file *fd, struct dirent *dirp, uint32_t count); - - int (*poll) (struct dfs_file *fd, struct rt_pollreq *req); - void (*set_termios) (struct tty_struct *tty, struct termios *old); - int (*receive_buf) (struct tty_struct *tty,char *cp, int count); - - int refcount; -}; - -struct tty_ldisc -{ - struct tty_ldisc_ops *ops; - struct tty_struct *tty; -}; - -#define TTY_LDISC_MAGIC 0x5403 - -int tty_register_ldisc(int disc, struct tty_ldisc_ops *new_ldisc); -void tty_ldisc_kill(struct tty_struct *tty); -void tty_ldisc_init(struct tty_struct *tty); -void tty_ldisc_release(struct tty_struct *tty); -void n_tty_init(void); - -#endif // __TTY_LDISC_ diff --git a/components/drivers/tty/n_tty.c b/components/drivers/tty/n_tty.c deleted file mode 100644 index bf1156ba381..00000000000 --- a/components/drivers/tty/n_tty.c +++ /dev/null @@ -1,2223 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021.12.07 linzhenxing first version - */ -#include -#include -#include -#include -#if defined(RT_USING_POSIX_TERMIOS) -#include -#endif -#include - -#define DBG_TAG "N_TTY" -#ifdef RT_TTY_DEBUG -#define DBG_LVL DBG_LOG -#else -#define DBG_LVL DBG_INFO -#endif /* RT_TTY_DEBUG */ -#include - -/* number of characters left in xmit buffer before select has we have room */ -#define WAKEUP_CHARS 256 - -/* - * This defines the low- and high-watermarks for throttling and - * unthrottling the TTY driver. These watermarks are used for - * controlling the space in the read buffer. - */ -#define TTY_THRESHOLD_THROTTLE 128 /* now based on remaining room */ -#define TTY_THRESHOLD_UNTHROTTLE 128 - -/* - * Special byte codes used in the echo buffer to represent operations - * or special handling of characters. Bytes in the echo buffer that - * are not part of such special blocks are treated as normal character - * codes. - */ -#define ECHO_OP_START 0xff -#define ECHO_OP_MOVE_BACK_COL 0x80 -#define ECHO_OP_SET_CANON_COL 0x81 -#define ECHO_OP_ERASE_TAB 0x82 - -#define ECHO_COMMIT_WATERMARK 256 -#define ECHO_BLOCK 256 -#define ECHO_DISCARD_WATERMARK RT_TTY_BUF - (ECHO_BLOCK + 32) - -static struct rt_spinlock _spinlock = RT_SPINLOCK_INIT; - -struct n_tty_data -{ - /* producer-published */ - size_t read_head; - size_t commit_head; - size_t canon_head; - size_t echo_head; - size_t echo_commit; - size_t echo_mark; - unsigned long char_map[256]; - - /* non-atomic */ - rt_bool_t no_room; - /* must hold exclusive termios_rwsem to reset these */ - unsigned char lnext:1, erasing:1, raw:1, real_raw:1, icanon:1; - unsigned char push:1; - - /* shared by producer and consumer */ - char read_buf[RT_TTY_BUF]; - unsigned long read_flags[RT_TTY_BUF]; - unsigned char echo_buf[RT_TTY_BUF]; - - /* consumer-published */ - size_t read_tail; - size_t line_start; - - /* protected by output lock */ - unsigned int column; - unsigned int canon_column; - size_t echo_tail; - - rt_mutex_t atomic_read_lock; - rt_mutex_t output_lock; -}; - -rt_inline int set_bit(int nr,int *addr) -{ - int mask, retval; - rt_base_t level; - - addr += nr >> 5; - mask = 1 << (nr & 0x1f); - level = rt_spin_lock_irqsave(&_spinlock); - retval = (mask & *addr) != 0; - *addr |= mask; - rt_spin_unlock_irqrestore(&_spinlock, level); - return retval; -} - -rt_inline int clear_bit(int nr, int *addr) -{ - int mask, retval; - rt_base_t level; - - addr += nr >> 5; - mask = 1 << (nr & 0x1f); - level = rt_spin_lock_irqsave(&_spinlock); - retval = (mask & *addr) != 0; - *addr &= ~mask; - rt_spin_unlock_irqrestore(&_spinlock, level); - return retval; -} - -rt_inline int test_bit(int nr, int *addr) -{ - int mask; - - addr += nr >> 5; - mask = 1 << (nr & 0x1f); - return ((mask & *addr) != 0); -} - -rt_inline int test_and_clear_bit(int nr, volatile void *addr) -{ - int mask, retval; - rt_base_t level; - volatile unsigned int *a = addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - level = rt_spin_lock_irqsave(&_spinlock); - retval = (mask & *a) != 0; - *a &= ~mask; - rt_spin_unlock_irqrestore(&_spinlock, level); - - return retval; -} - -#ifdef __GNUC__ -rt_inline unsigned long __ffs(unsigned long word) -{ - return __builtin_ffsl(word); -} -#else -rt_inline unsigned long __ffs(unsigned long word) -{ - int num = 0; - -#if BITS_PER_LONG == 64 - if ((word & 0xffffffff) == 0) - { - num += 32; - word >>= 32; - } -#endif - if ((word & 0xffff) == 0) - { - num += 16; - word >>= 16; - } - if ((word & 0xff) == 0) - { - num += 8; - word >>= 8; - } - if ((word & 0xf) == 0) - { - num += 4; - word >>= 4; - } - if ((word & 0x3) == 0) - { - num += 2; - word >>= 2; - } - if ((word & 0x1) == 0) - { - num += 1; - } - - return num; -} -#endif - -#define BITS_PER_LONG 32 -#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG) - -/* - * Find the next set bit in a memory region. - */ -rt_inline unsigned long find_next_bit(const unsigned long *addr, unsigned long size, - unsigned long offset) -{ - const unsigned long *p = addr + BITOP_WORD(offset); - unsigned long result = offset & ~(BITS_PER_LONG-1); - unsigned long tmp; - - if (offset >= size) - { - return size; - } - - size -= result; - offset %= BITS_PER_LONG; - if (offset) - { - tmp = *(p++); - tmp &= (~0UL << offset); - if (size < BITS_PER_LONG) - { - goto found_first; - } - - if (tmp) - { - goto found_middle; - } - - size -= BITS_PER_LONG; - result += BITS_PER_LONG; - } - - while (size & ~(BITS_PER_LONG-1)) - { - if ((tmp = *(p++))) - { - goto found_middle; - } - - result += BITS_PER_LONG; - size -= BITS_PER_LONG; - } - - if (!size) - { - return result; - } - - tmp = *p; - -found_first: - tmp &= (~0UL >> (BITS_PER_LONG - size)); - if (tmp == 0UL) /* Are any bits set? */ - { - return result + size; /* Nope. */ - } - -found_middle: - return result + __ffs(tmp); -} - -rt_inline void tty_sigaddset(lwp_sigset_t *set, int _sig) -{ - unsigned long sig = _sig - 1; - - if (_LWP_NSIG_WORDS == 1) - { - set->sig[0] |= 1UL << sig; - } - else - { - set->sig[sig / _LWP_NSIG_BPW] |= 1UL << (sig % _LWP_NSIG_BPW); - } -} - -rt_inline size_t read_cnt(struct n_tty_data *ldata) -{ - return ldata->read_head - ldata->read_tail; -} - -rt_inline char read_buf(struct n_tty_data *ldata, size_t i) -{ - return ldata->read_buf[i & (RT_TTY_BUF - 1)]; -} - -rt_inline char *read_buf_addr(struct n_tty_data *ldata, size_t i) -{ - return &ldata->read_buf[i & (RT_TTY_BUF - 1)]; -} - -rt_inline unsigned char echo_buf(struct n_tty_data *ldata, size_t i) -{ - return ldata->echo_buf[i & (RT_TTY_BUF - 1)]; -} - -rt_inline unsigned char *echo_buf_addr(struct n_tty_data *ldata, size_t i) -{ - return &ldata->echo_buf[i & (RT_TTY_BUF - 1)]; -} - -/** - * put_tty_queue - add character to tty - * @c: character - * @ldata: n_tty data - * - * Add a character to the tty read_buf queue. - * - * n_tty_receive_buf()/producer path: - * caller holds non-exclusive termios_rwsem - */ -rt_inline void put_tty_queue(unsigned char c, struct n_tty_data *ldata) -{ - *read_buf_addr(ldata, ldata->read_head) = c; - ldata->read_head++; -} - -/** - * reset_buffer_flags - reset buffer state - * @tty: terminal to reset - * - * Reset the read buffer counters and clear the flags. - * Called from n_tty_open() and n_tty_flush_buffer(). - * - * Locking: caller holds exclusive termios_rwsem - * (or locking is not required) - */ - -static void reset_buffer_flags(struct n_tty_data *ldata) -{ - ldata->read_head = ldata->canon_head = ldata->read_tail = 0; - ldata->echo_head = ldata->echo_tail = ldata->echo_commit = 0; - ldata->commit_head = 0; - ldata->echo_mark = 0; - ldata->line_start = 0; - - ldata->erasing = 0; - rt_memset(ldata->read_flags, 0, RT_TTY_BUF); - ldata->push = 0; -} - -/** - * add_echo_byte - add a byte to the echo buffer - * @c: unicode byte to echo - * @ldata: n_tty data - * - * Add a character or operation byte to the echo buffer. - */ - -rt_inline void add_echo_byte(unsigned char c, struct n_tty_data *ldata) -{ - *echo_buf_addr(ldata, ldata->echo_head++) = c; -} - -/** - * echo_move_back_col - add operation to move back a column - * @ldata: n_tty data - * - * Add an operation to the echo buffer to move back one column. - */ - -static void echo_move_back_col(struct n_tty_data *ldata) -{ - add_echo_byte(ECHO_OP_START, ldata); - add_echo_byte(ECHO_OP_MOVE_BACK_COL, ldata); -} - -/** - * echo_set_canon_col - add operation to set the canon column - * @ldata: n_tty data - * - * Add an operation to the echo buffer to set the canon column - * to the current column. - */ - -static void echo_set_canon_col(struct n_tty_data *ldata) -{ - add_echo_byte(ECHO_OP_START, ldata); - add_echo_byte(ECHO_OP_SET_CANON_COL, ldata); -} - -/** - * echo_erase_tab - add operation to erase a tab - * @num_chars: number of character columns already used - * @after_tab: true if num_chars starts after a previous tab - * @ldata: n_tty data - * - * Add an operation to the echo buffer to erase a tab. - * - * Called by the eraser function, which knows how many character - * columns have been used since either a previous tab or the start - * of input. This information will be used later, along with - * canon column (if applicable), to go back the correct number - * of columns. - */ - -static void echo_erase_tab(unsigned int num_chars, int after_tab, - struct n_tty_data *ldata) -{ - add_echo_byte(ECHO_OP_START, ldata); - add_echo_byte(ECHO_OP_ERASE_TAB, ldata); - - /* We only need to know this modulo 8 (tab spacing) */ - num_chars &= 7; - - /* Set the high bit as a flag if num_chars is after a previous tab */ - if (after_tab) - { - num_chars |= 0x80; - } - - add_echo_byte(num_chars, ldata); -} - -/** - * echo_char_raw - echo a character raw - * @c: unicode byte to echo - * @tty: terminal device - * - * Echo user input back onto the screen. This must be called only when - * L_ECHO(tty) is true. Called from the driver receive_buf path. - * - * This variant does not treat control characters specially. - */ - -static void echo_char_raw(unsigned char c, struct n_tty_data *ldata) -{ - if (c == ECHO_OP_START) - { - add_echo_byte(ECHO_OP_START, ldata); - add_echo_byte(ECHO_OP_START, ldata); - } - else - { - add_echo_byte(c, ldata); - } -} - -/** - * echo_char - echo a character - * @c: unicode byte to echo - * @tty: terminal device - * - * Echo user input back onto the screen. This must be called only when - * L_ECHO(tty) is true. Called from the driver receive_buf path. - * - * This variant tags control characters to be echoed as "^X" - * (where X is the letter representing the control char). - */ - -static void echo_char(unsigned char c, struct tty_struct *tty) -{ - struct n_tty_data *ldata = tty->disc_data; - - if (c == ECHO_OP_START) - { - add_echo_byte(ECHO_OP_START, ldata); - add_echo_byte(ECHO_OP_START, ldata); - } - else - { - if (L_ECHOCTL(tty) && iscntrl(c) && c != '\t') - { - add_echo_byte(ECHO_OP_START, ldata); - } - add_echo_byte(c, ldata); - } -} - -/** - * finish_erasing - complete erase - * @ldata: n_tty data - */ - -rt_inline void finish_erasing(struct n_tty_data *ldata) -{ - if (ldata->erasing) - { - echo_char_raw('/', ldata); - ldata->erasing = 0; - } -} - -/** - * is_utf8_continuation - utf8 multibyte check - * @c: byte to check - * - * Returns true if the utf8 character 'c' is a multibyte continuation - * character. We use this to correctly compute the on screen size - * of the character when printing - */ - -rt_inline int is_utf8_continuation(unsigned char c) -{ - return (c & 0xc0) == 0x80; -} - -/** - * is_continuation - multibyte check - * @c: byte to check - * - * Returns true if the utf8 character 'c' is a multibyte continuation - * character and the terminal is in unicode mode. - */ - -rt_inline int is_continuation(unsigned char c, struct tty_struct *tty) -{ - return I_IUTF8(tty) && is_utf8_continuation(c); -} - -/** - * eraser - handle erase function - * @c: character input - * @tty: terminal device - * - * Perform erase and necessary output when an erase character is - * present in the stream from the driver layer. Handles the complexities - * of UTF-8 multibyte symbols. - * - * n_tty_receive_buf()/producer path: - * caller holds non-exclusive termios_rwsem - */ - -static void eraser(unsigned char c, struct tty_struct *tty) -{ - struct n_tty_data *ldata = tty->disc_data; - enum { KERASE, WERASE, KILL } kill_type; - size_t head = 0; - size_t cnt = 0; - int seen_alnums = 0; - - if (ldata->read_head == ldata->canon_head) - { - /* process_output('\a', tty); */ /* what do you think? */ - return; - } - - if (c == ERASE_CHAR(tty)) - { - kill_type = KERASE; - } - else if (c == WERASE_CHAR(tty)) - { - kill_type = WERASE; - } - else - { - if (!L_ECHO(tty)) - { - ldata->read_head = ldata->canon_head; - return; - } - - if (!L_ECHOK(tty) || !L_ECHOKE(tty) || !L_ECHOE(tty)) - { - ldata->read_head = ldata->canon_head; - finish_erasing(ldata); - echo_char(KILL_CHAR(tty), tty); - /* Add a newline if ECHOK is on and ECHOKE is off. */ - if (L_ECHOK(tty)) - { - echo_char_raw('\n', ldata); - } - return; - } - kill_type = KILL; - } - - seen_alnums = 0; - while (ldata->read_head != ldata->canon_head) - { - head = ldata->read_head; - - /* erase a single possibly multibyte character */ - do - { - head--; - c = read_buf(ldata, head); - } while (is_continuation(c, tty) && head != ldata->canon_head); - - /* do not partially erase */ - if (is_continuation(c, tty)) - { - break; - } - - if (kill_type == WERASE) - { - /* Equivalent to BSD's ALTWERASE. */ - if (isalnum(c) || c == '_') - { - seen_alnums++; - } - else if (seen_alnums) - { - break; - } - } - cnt = ldata->read_head - head; - ldata->read_head = head; - if (L_ECHO(tty)) - { - if (L_ECHOPRT(tty)) - { - if (!ldata->erasing) - { - echo_char_raw('\\', ldata); - ldata->erasing = 1; - } - /* if cnt > 1, output a multi-byte character */ - echo_char(c, tty); - while (--cnt > 0) - { - head++; - echo_char_raw(read_buf(ldata, head), ldata); - echo_move_back_col(ldata); - } - } - else if (kill_type == KERASE && !L_ECHOE(tty)) - { - echo_char(ERASE_CHAR(tty), tty); - } - else if (c == '\t') - { - unsigned int num_chars = 0; - int after_tab = 0; - size_t tail = ldata->read_head; - - /* - * Count the columns used for characters - * since the start of input or after a - * previous tab. - * This info is used to go back the correct - * number of columns. - */ - while (tail != ldata->canon_head) - { - tail--; - c = read_buf(ldata, tail); - if (c == '\t') - { - after_tab = 1; - break; - } - else if (iscntrl(c)) - { - if (L_ECHOCTL(tty)) - { - num_chars += 2; - } - } - else if (!is_continuation(c, tty)) - { - num_chars++; - } - } - echo_erase_tab(num_chars, after_tab, ldata); - } - else - { - if (iscntrl(c) && L_ECHOCTL(tty)) - { - echo_char_raw('\b', ldata); - echo_char_raw(' ', ldata); - echo_char_raw('\b', ldata); - } - if (!iscntrl(c) || L_ECHOCTL(tty)) - { - echo_char_raw('\b', ldata); - echo_char_raw(' ', ldata); - echo_char_raw('\b', ldata); - } - } - } - if (kill_type == KERASE) - { - break; - } - } - if (ldata->read_head == ldata->canon_head && L_ECHO(tty)) - { - finish_erasing(ldata); - } -} - -/** - * isig - handle the ISIG optio - * @sig: signal - * @tty: terminal - * - * Called when a signal is being sent due to terminal input. - * Called from the driver receive_buf path so serialized. - * - * Performs input and output flush if !NOFLSH. In this context, the echo - * buffer is 'output'. The signal is processed first to alert any current - * readers or writers to discontinue and exit their i/o loops. - * - * Locking: ctrl_lock - */ - -static void __isig(int sig, struct tty_struct *tty) -{ - struct rt_lwp *lwp = tty->foreground; - struct tty_ldisc *ld = RT_NULL; - struct termios old_termios; - struct termios *new_termios = get_old_termios(); - - if (lwp) - { - if (sig == SIGTSTP) - { - struct rt_lwp *old_lwp; - - rt_memcpy(&old_termios, &(tty->init_termios), sizeof(struct termios)); - tty->init_termios = *new_termios; - ld = tty->ldisc; - if (ld != RT_NULL) - { - if (ld->ops->set_termios) - { - ld->ops->set_termios(tty, &old_termios); - } - } - lwp_signal_kill(lwp, SIGTTOU, SI_USER, 0); - old_lwp = tty_pop(&tty->head, RT_NULL); - tty->foreground = old_lwp; - } - else - { - lwp_signal_kill(lwp, sig, SI_USER, 0); - } - } -} - -static void isig(int sig, struct tty_struct *tty) -{ - struct n_tty_data *ldata = tty->disc_data; - - if (L_NOFLSH(tty)) - { - /* signal only */ - __isig(sig, tty); - - } - else - { /* signal and flush */ - __isig(sig, tty); - - /* clear echo buffer */ - ldata->echo_head = ldata->echo_tail = 0; - ldata->echo_mark = ldata->echo_commit = 0; - - /* clear input buffer */ - reset_buffer_flags(tty->disc_data); - } -} - -/** - * do_output_char - output one character - * @c: character (or partial unicode symbol) - * @tty: terminal device - * @space: space available in tty driver write buffer - * - * This is a helper function that handles one output character - * (including special characters like TAB, CR, LF, etc.), - * doing OPOST processing and putting the results in the - * tty driver's write buffer. - * - * Note that Linux currently ignores TABDLY, CRDLY, VTDLY, FFDLY - * and NLDLY. They simply aren't relevant in the world today. - * If you ever need them, add them here. - * - * Returns the number of bytes of buffer space used or -1 if - * no space left. - * - * Locking: should be called under the output_lock to protect - * the column state and space left in the buffer - */ - -static int do_output_char(unsigned char c, struct tty_struct *tty) -{ - struct n_tty_data *ldata = tty->disc_data; - int spaces = 0; - char *ch = RT_NULL; - - switch (c) - { - case '\n': - if (O_ONLRET(tty)) - { - ldata->column = 0; - } - - if (O_ONLCR(tty)) - { - ldata->canon_column = ldata->column = 0; - ch = "\r\n"; - rt_device_write((rt_device_t)tty, -1, ch, 2); - return 2; - } - ldata->canon_column = ldata->column; - break; - case '\r': - if (O_ONOCR(tty) && ldata->column == 0) - { - return 0; - } - - if (O_OCRNL(tty)) - { - c = '\n'; - if (O_ONLRET(tty)) - { - ldata->canon_column = ldata->column = 0; - } - break; - } - ldata->canon_column = ldata->column = 0; - break; - case '\t': - spaces = 8 - (ldata->column & 7); - if (O_TABDLY(tty) == XTABS) - { - ldata->column += spaces; - ch = " "; - rt_device_write((rt_device_t)tty, -1, &ch, spaces); - return spaces; - } - ldata->column += spaces; - break; - case '\b': - if (ldata->column > 0) - { - ldata->column--; - } - ch = "\b \b"; - rt_device_write((rt_device_t)tty, -1, ch, strlen(ch)); - return 1; - default: - if (!iscntrl(c)) - { - if (O_OLCUC(tty)) - { - c = toupper(c); - } - - if (!is_continuation(c, tty)) - { - ldata->column++; - } - } - break; - } - - rt_device_write((rt_device_t)tty, -1, &c, 1); - return 1; -} - -/** - * process_output - output post processor - * @c: character (or partial unicode symbol) - * @tty: terminal device - * - * Output one character with OPOST processing. - * Returns -1 when the output device is full and the character - * must be retried. - * - * Locking: output_lock to protect column state and space left - * (also, this is called from n_tty_write under the - * tty layer write lock) - */ - -static int process_output(unsigned char c, struct tty_struct *tty) -{ - int retval = 0; - - retval = do_output_char(c, tty); - if (retval < 0) - { - return -1; - } - else - { - return 0; - } -} - -/** - * process_output_block - block post processor - * @tty: terminal device - * @buf: character buffer - * @nr: number of bytes to output - * - * Output a block of characters with OPOST processing. - * Returns the number of characters output. - * - * This path is used to speed up block console writes, among other - * things when processing blocks of output data. It handles only - * the simple cases normally found and helps to generate blocks of - * symbols for the console driver and thus improve performance. - * - * Locking: output_lock to protect column state and space left - * (also, this is called from n_tty_write under the - * tty layer write lock) - */ - -static ssize_t process_output_block(struct tty_struct *tty, - const char *buf, unsigned int nr) -{ - struct n_tty_data *ldata = tty->disc_data; - int i = 0; - ssize_t size = 0; - const char *cp = RT_NULL; - - for (i = 0, cp = buf; i < nr; i++, cp++) - { - char c = *cp; - - switch (c) - { - case '\n': - if (O_ONLRET(tty)) - { - ldata->column = 0; - } - - if (O_ONLCR(tty)) - { - goto break_out; - } - ldata->canon_column = ldata->column; - break; - case '\r': - if (O_ONOCR(tty) && ldata->column == 0) - { - goto break_out; - } - - if (O_OCRNL(tty)) - { - goto break_out; - } - - ldata->canon_column = ldata->column = 0; - break; - case '\t': - goto break_out; - case '\b': - if (ldata->column > 0) - { - ldata->column--; - } - break; - default: - if (!iscntrl(c)) - { - if (O_OLCUC(tty)) - { - goto break_out; - } - - if (!is_continuation(c, tty)) - { - ldata->column++; - } - } - break; - } - } -break_out: - size = rt_device_write((rt_device_t)tty, -1, buf, i); - return size; -} - -static size_t __process_echoes(struct tty_struct *tty) -{ - struct n_tty_data *ldata = tty->disc_data; - size_t tail = 0; - unsigned char c = 0; - char ch = 0; - unsigned char num_chars = 0, num_bs = 0; - - tail = ldata->echo_tail; - while (ldata->echo_commit != tail) - { - c = echo_buf(ldata, tail); - if (c == ECHO_OP_START) - { - unsigned char op = 0; - - /* - * If the buffer byte is the start of a multi-byte - * operation, get the next byte, which is either the - * op code or a control character value. - */ - op = echo_buf(ldata, tail + 1); - - switch (op) - { - case ECHO_OP_ERASE_TAB: - num_chars = echo_buf(ldata, tail + 2); - - /* - * Determine how many columns to go back - * in order to erase the tab. - * This depends on the number of columns - * used by other characters within the tab - * area. If this (modulo 8) count is from - * the start of input rather than from a - * previous tab, we offset by canon column. - * Otherwise, tab spacing is normal. - */ - if (!(num_chars & 0x80)) - { - num_chars += ldata->canon_column; - } - num_bs = 8 - (num_chars & 7); - - while (num_bs--) - { - ch = '\b'; - rt_device_write((rt_device_t)tty, -1, &ch, 1); - if (ldata->column > 0) - { - ldata->column--; - } - } - tail += 3; - break; - - case ECHO_OP_SET_CANON_COL: - ldata->canon_column = ldata->column; - tail += 2; - break; - - case ECHO_OP_MOVE_BACK_COL: - if (ldata->column > 0) - { - ldata->column--; - } - tail += 2; - break; - - case ECHO_OP_START: - ch = ECHO_OP_START; - rt_device_write((rt_device_t)tty, -1, &ch, 1); - ldata->column++; - tail += 2; - break; - - default: - /* - * If the op is not a special byte code, - * it is a ctrl char tagged to be echoed - * as "^X" (where X is the letter - * representing the control char). - * Note that we must ensure there is - * enough space for the whole ctrl pair. - * - */ - ch = '^'; - rt_device_write((rt_device_t)tty, -1, &ch, 1); - ch = op ^ 0100; - rt_device_write((rt_device_t)tty, -1, &ch, 1); - ldata->column += 2; - tail += 2; - } - } - else - { - if (O_OPOST(tty)) - { - int retval = do_output_char(c, tty); - if (retval < 0) - { - break; - } - } - else - { - rt_device_write((rt_device_t)tty, -1, &c, 1); - } - tail += 1; - } - } - - /* If the echo buffer is nearly full (so that the possibility exists - * of echo overrun before the next commit), then discard enough - * data at the tail to prevent a subsequent overrun */ - while (ldata->echo_commit - tail >= ECHO_DISCARD_WATERMARK) - { - if (echo_buf(ldata, tail) == ECHO_OP_START) - { - if (echo_buf(ldata, tail + 1) == ECHO_OP_ERASE_TAB) - { - tail += 3; - } - else - { - tail += 2; - } - } - else - { - tail++; - } - } - - ldata->echo_tail = tail; - return 0; -} - -static void commit_echoes(struct tty_struct *tty) -{ - struct n_tty_data *ldata = tty->disc_data; - size_t nr = 0, old = 0; - size_t head = 0; - - head = ldata->echo_head; - ldata->echo_mark = head; - old = ldata->echo_commit - ldata->echo_tail; - - /* Process committed echoes if the accumulated # of bytes - * is over the threshold (and try again each time another - * block is accumulated) */ - nr = head - ldata->echo_tail; - if (nr < ECHO_COMMIT_WATERMARK || (nr % ECHO_BLOCK > old % ECHO_BLOCK)) - { - return; - } - - ldata->echo_commit = head; - __process_echoes(tty); -} - -static void process_echoes(struct tty_struct *tty) -{ - struct n_tty_data *ldata = tty->disc_data; - - if (ldata->echo_mark == ldata->echo_tail) - { - return; - } - - ldata->echo_commit = ldata->echo_mark; - __process_echoes(tty); -} - -/* NB: echo_mark and echo_head should be equivalent here */ -static void flush_echoes(struct tty_struct *tty) -{ - struct n_tty_data *ldata = tty->disc_data; - - if ((!L_ECHO(tty) && !L_ECHONL(tty)) || - ldata->echo_commit == ldata->echo_head) - { - return; - } - - ldata->echo_commit = ldata->echo_head; - __process_echoes(tty); -} -/** - * n_tty_set_termios - termios data changed - * @tty: terminal - * @old: previous data - * - * Called by the tty layer when the user changes termios flags so - * that the line discipline can plan ahead. This function cannot sleep - * and is protected from re-entry by the tty layer. The user is - * guaranteed that this function will not be re-entered or in progress - * when the ldisc is closed. - * - * Locking: Caller holds tty->termios_rwsem - */ - -static void n_tty_set_termios(struct tty_struct *tty, struct termios *old) -{ - struct n_tty_data *ldata = tty->disc_data; - - if (!old || (old->c_lflag ^ tty->init_termios.c_lflag) & (ICANON | EXTPROC)) - { - rt_memset(ldata->read_flags, 0, RT_TTY_BUF); - ldata->line_start = ldata->read_tail; - if (!L_ICANON(tty) || !read_cnt(ldata)) - { - ldata->canon_head = ldata->read_tail; - ldata->push = 0; - } - else - { - set_bit((ldata->read_head - 1) & (RT_TTY_BUF - 1),(int *)ldata->read_flags); - ldata->canon_head = ldata->read_head; - ldata->push = 1; - } - ldata->commit_head = ldata->read_head; - ldata->erasing = 0; - ldata->lnext = 0; - } - - ldata->icanon = (L_ICANON(tty) != 0); - - if (I_ISTRIP(tty) || I_IUCLC(tty) || I_IGNCR(tty) || - I_ICRNL(tty) || I_INLCR(tty) || L_ICANON(tty) || - I_IXON(tty) || L_ISIG(tty) || L_ECHO(tty) || - I_PARMRK(tty)) - { - rt_memset(ldata->char_map, 0, 256); - if (I_IGNCR(tty) || I_ICRNL(tty)) - { - set_bit('\r', (int *)ldata->char_map); - } - - if (I_INLCR(tty)) - { - set_bit('\n', (int *)ldata->char_map); - } - - if (L_ICANON(tty)) - { - set_bit(ERASE_CHAR(tty), (int *)ldata->char_map); - set_bit(KILL_CHAR(tty),(int *) ldata->char_map); - set_bit(EOF_CHAR(tty), (int *)ldata->char_map); - set_bit('\n',(int *) ldata->char_map); - set_bit(EOL_CHAR(tty),(int *) ldata->char_map); - if (L_IEXTEN(tty)) - { - set_bit(WERASE_CHAR(tty), (int *)ldata->char_map); - set_bit(LNEXT_CHAR(tty), (int *)ldata->char_map); - set_bit(EOL2_CHAR(tty), (int *)ldata->char_map); - if (L_ECHO(tty)) - { - set_bit(REPRINT_CHAR(tty), - (int *)ldata->char_map); - } - } - } - if (I_IXON(tty)) - { - set_bit(START_CHAR(tty), (int *)ldata->char_map); - set_bit(STOP_CHAR(tty), (int *)ldata->char_map); - } - if (L_ISIG(tty)) - { - set_bit(INTR_CHAR(tty), (int *)ldata->char_map); - set_bit(QUIT_CHAR(tty), (int *)ldata->char_map); - set_bit(SUSP_CHAR(tty), (int *)ldata->char_map); - } - clear_bit(__DISABLED_CHAR, (int *)ldata->char_map); - ldata->raw = 0; - ldata->real_raw = 0; - } - else - { - ldata->raw = 1; - if ((I_IGNBRK(tty) || (!I_BRKINT(tty) && !I_PARMRK(tty))) && - (I_IGNPAR(tty) || !I_INPCK(tty))/* && - (tty->driver->flags & TTY_DRIVER_REAL_RAW)*/) - { - ldata->real_raw = 1; - } - else - { - ldata->real_raw = 0; - } - } -} - -void console_ldata_init(struct tty_struct *tty) -{ - struct n_tty_data *ldata = RT_NULL; - - ldata = rt_malloc(sizeof(struct n_tty_data)); - if (ldata == RT_NULL) - { - LOG_E("console_ldata_init ldata malloc fail"); - return; - } - tty->disc_data = ldata; - reset_buffer_flags(ldata); - ldata->column = 0; - ldata->canon_column = 0; - ldata->no_room = 0; - ldata->lnext = 0; - n_tty_set_termios(tty, RT_NULL); - return; -} - -static int n_tty_open(struct dfs_file *fd) -{ - int ret = 0; - struct n_tty_data *ldata = RT_NULL; - struct tty_struct *tty = (struct tty_struct*)fd->vnode->data; - - ldata = rt_malloc(sizeof(struct n_tty_data)); - if (ldata == RT_NULL) - { - LOG_E("n_tty_open ldata malloc fail"); - return -1; - } - - ldata->atomic_read_lock = rt_mutex_create("atomic_read_lock",RT_IPC_FLAG_FIFO); - if(ldata->atomic_read_lock == RT_NULL) - { - LOG_E("n_tty_open atomic_read_lock create fail"); - return -1; - } - - ldata->output_lock = rt_mutex_create("output_lock",RT_IPC_FLAG_FIFO); - if(ldata->output_lock == RT_NULL) - { - LOG_E("n_tty_open output_lock create fail"); - return -1; - } - - tty->disc_data = ldata; - reset_buffer_flags(ldata); - ldata->column = 0; - ldata->canon_column = 0; - ldata->lnext = 0; - n_tty_set_termios(tty, RT_NULL); - return ret; -} - -rt_inline int input_available_p(struct tty_struct *tty, int poll) -{ - struct n_tty_data *ldata = tty->disc_data; - int amt = poll && !TIME_CHAR(tty) && MIN_CHAR(tty) ? MIN_CHAR(tty) : 1; - - if (ldata->icanon && !L_EXTPROC(tty)) - { - return ldata->canon_head != ldata->read_tail; - } - else - { - return ldata->commit_head - ldata->read_tail >= amt; - } -} - -/** - * copy_from_read_buf - copy read data directly - * @tty: terminal device - * @b: user data - * @nr: size of data - * - * Helper function to speed up n_tty_read. It is only called when - * ICANON is off; it copies characters straight from the tty queue to - * user space directly. It can be profitably called twice; once to - * drain the space from the tail pointer to the (physical) end of the - * buffer, and once to drain the space from the (physical) beginning of - * the buffer to head pointer. - * - * Called under the ldata->atomic_read_lock sem - * - * n_tty_read()/consumer path: - * caller holds non-exclusive termios_rwsem - * read_tail published - */ - -static int copy_from_read_buf(struct tty_struct *tty,char *b,size_t nr) -{ - struct n_tty_data *ldata = tty->disc_data; - size_t n = 0; - rt_bool_t is_eof = 0; - size_t head = ldata->commit_head; - size_t tail = ldata->read_tail & (RT_TTY_BUF - 1); - - n = min(head - ldata->read_tail, RT_TTY_BUF - tail); - n = min(nr, n); - if (n) - { - const char *from = read_buf_addr(ldata, tail); - memcpy(b, from, n); - is_eof = n == 1 && *from == EOF_CHAR(tty); - ldata->read_tail += n; - /* Turn single EOF into zero-length read */ - if (L_EXTPROC(tty) && ldata->icanon && is_eof && - (head == ldata->read_tail)) - { - n = 0; - } - - } - return n; -} - -/** - * canon_copy_from_read_buf - copy read data in canonical mode - * @tty: terminal device - * @b: user data - * @nr: size of data - * - * Helper function for n_tty_read. It is only called when ICANON is on; - * it copies one line of input up to and including the line-delimiting - * character into the user-space buffer. - * - * NB: When termios is changed from non-canonical to canonical mode and - * the read buffer contains data, n_tty_set_termios() simulates an EOF - * push (as if C-d were input) _without_ the DISABLED_CHAR in the buffer. - * This causes data already processed as input to be immediately available - * as input although a newline has not been received. - * - * Called under the atomic_read_lock mutex - * - * n_tty_read()/consumer path: - * caller holds non-exclusive termios_rwsem - * read_tail published - */ - -static int canon_copy_from_read_buf(struct tty_struct *tty, char *b, size_t nr) -{ - struct n_tty_data *ldata = tty->disc_data; - size_t n = 0, size = 0, more = 0, c = 0; - size_t eol = 0; - size_t tail = 0; - int found = 0; - - /* N.B. avoid overrun if nr == 0 */ - if (nr == 0) - { - return 0; - } - - n = min(nr + 1, ldata->canon_head - ldata->read_tail); - - tail = ldata->read_tail & (RT_TTY_BUF - 1); - size = min(tail + n, RT_TTY_BUF); - - eol = find_next_bit(ldata->read_flags, size, tail); - more = n - (size - tail); - if (eol == RT_TTY_BUF && more) - { - /* scan wrapped without finding set bit */ - eol = find_next_bit(ldata->read_flags, more, 0); - found = eol != more; - } - else - { - found = eol != size; - } - - n = eol - tail; - if (n > RT_TTY_BUF) - { - n += RT_TTY_BUF; - } - c = n + found; - - if (!found || read_buf(ldata, eol) != __DISABLED_CHAR) - { - c = min(nr, c); - n = c; - } - - size_t buf_size = RT_TTY_BUF - tail; - const void *from = read_buf_addr(ldata, tail); - size_t temp_n = n; - if (n > buf_size) - { - memcpy(b, from, buf_size); - b += buf_size; - temp_n -= buf_size; - from = ldata->read_buf; - } - memcpy(b, from, temp_n); - - if (found) - { - clear_bit(eol, (int *)ldata->read_flags); - } - ldata->read_tail = ldata->read_tail + c; - - if (found) - { - if (!ldata->push) - { - ldata->line_start = ldata->read_tail; - } - else - { - ldata->push = 0; - } - } - return n; -} - - -static int n_tty_close(struct tty_struct *tty) -{ - int ret = 0; - struct n_tty_data *ldata = RT_NULL; - struct tty_struct *o_tty = RT_NULL; - - RT_ASSERT(tty != RT_NULL); - if (tty->type == TTY_DRIVER_TYPE_PTY && tty->subtype == PTY_TYPE_MASTER) - { - o_tty = tty->other_struct; - } - else - { - o_tty = tty; - } - - ldata = o_tty->disc_data; - rt_free(ldata); - o_tty->disc_data = RT_NULL; - return ret; -} - -static int n_tty_ioctl(struct dfs_file *fd, int cmd, void *args) -{ - int ret = 0; - struct tty_struct *real_tty = RT_NULL; - struct tty_struct *tty = RT_NULL; - - tty = (struct tty_struct *)fd->vnode->data; - RT_ASSERT(tty != RT_NULL); - if (tty->type == TTY_DRIVER_TYPE_PTY && tty->subtype == PTY_TYPE_MASTER) - { - real_tty = tty->other_struct; - } - else - { - real_tty = tty; - } - - switch(cmd) - { - - default: - ret = n_tty_ioctl_extend(real_tty, cmd, args); - if (ret != -ENOIOCTLCMD) - { - return ret; - } - } - - ret = rt_device_control((rt_device_t)real_tty, cmd, args); - if (ret != -ENOIOCTLCMD) - { - return ret; - } - return ret; -} - -static void -n_tty_receive_signal_char(struct tty_struct *tty, int signal, unsigned char c) -{ - isig(signal, tty); - if (L_ECHO(tty)) - { - echo_char(c, tty); - commit_echoes(tty); - } - else - { - process_echoes(tty); - } - return; -} - -/** - * n_tty_receive_char - perform processing - * @tty: terminal device - * @c: character - * - * Process an individual character of input received from the driver. - * This is serialized with respect to itself by the rules for the - * driver above. - * - * n_tty_receive_buf()/producer path: - * caller holds non-exclusive termios_rwsem - * publishes canon_head if canonical mode is active - * - * Returns 1 if LNEXT was received, else returns 0 - */ - -static int n_tty_receive_char_special(struct tty_struct *tty, unsigned char c) -{ - struct n_tty_data *ldata = tty->disc_data; - - if (I_IXON(tty)) - { - if (c == START_CHAR(tty)) /*ctrl + p realize missing*/ - { - process_echoes(tty); - return 0; - } - if (c == STOP_CHAR(tty)) /*ctrl + s realize missing*/ - { - return 0; - } - } - - if (L_ISIG(tty)) - { - if (c == INTR_CHAR(tty)) /*ctrl + c realize missing*/ - { - n_tty_receive_signal_char(tty, SIGINT, c); - return 0; - } - else if (c == QUIT_CHAR(tty)) /*ctrl + d realize missing*/ - { - n_tty_receive_signal_char(tty, SIGQUIT, c); - return 0; - } - else if (c == SUSP_CHAR(tty)) /*ctrl + z realize missing*/ - { - n_tty_receive_signal_char(tty, SIGTSTP, c); - return 0; - } - } - - if (c == '\r') - { - if (I_IGNCR(tty)) - { - return 0; - } - - if (I_ICRNL(tty)) - { - c = '\n'; - } - } - else if (c == '\n' && I_INLCR(tty)) - { - c = '\r'; - } - - if (ldata->icanon) - { - if (c == ERASE_CHAR(tty) || c == KILL_CHAR(tty) || - (c == WERASE_CHAR(tty) && L_IEXTEN(tty))) - { - eraser(c, tty); - commit_echoes(tty); - return 0; - } - if (c == LNEXT_CHAR(tty) && L_IEXTEN(tty)) - { - ldata->lnext = 1; - if (L_ECHO(tty)) - { - finish_erasing(ldata); - if (L_ECHOCTL(tty)) - { - echo_char_raw('^', ldata); - echo_char_raw('\b', ldata); - commit_echoes(tty); - } - } - return 1; - } - if (c == REPRINT_CHAR(tty) && L_ECHO(tty) && L_IEXTEN(tty)) - { - size_t tail = ldata->canon_head; - - finish_erasing(ldata); - echo_char(c, tty); - echo_char_raw('\n', ldata); - while (tail != ldata->read_head) - { - echo_char(read_buf(ldata, tail), tty); - tail++; - } - commit_echoes(tty); - return 0; - } - if (c == '\n') - { - if (L_ECHO(tty) || L_ECHONL(tty)) - { - echo_char_raw('\n', ldata); - commit_echoes(tty); - } - goto handle_newline; - } - if (c == EOF_CHAR(tty)) - { - c = __DISABLED_CHAR; - goto handle_newline; - } - if ((c == EOL_CHAR(tty)) || - (c == EOL2_CHAR(tty) && L_IEXTEN(tty))) - { - /* - * XXX are EOL_CHAR and EOL2_CHAR echoed?!? - */ - if (L_ECHO(tty)) - { - /* Record the column of first canon char. */ - if (ldata->canon_head == ldata->read_head) - { - echo_set_canon_col(ldata); - } - - echo_char(c, tty); - commit_echoes(tty); - } - /* - * XXX does PARMRK doubling happen for - * EOL_CHAR and EOL2_CHAR? - */ - if (c == (unsigned char) '\377' && I_PARMRK(tty)) - { - put_tty_queue(c, ldata); - } - -handle_newline: - set_bit(ldata->read_head & (RT_TTY_BUF - 1), (int *)ldata->read_flags); - put_tty_queue(c, ldata); - ldata->canon_head = ldata->read_head; - tty_wakeup_check(tty); - return 0; - } - } - - if (L_ECHO(tty)) - { - finish_erasing(ldata); - if (c == '\n') - { - echo_char_raw('\n', ldata); - } - else - { - /* Record the column of first canon char. */ - if (ldata->canon_head == ldata->read_head) - { - echo_set_canon_col(ldata); - } - echo_char(c, tty); - } - commit_echoes(tty); - } - - /* PARMRK doubling check */ - if (c == (unsigned char) '\377' && I_PARMRK(tty)) - { - put_tty_queue(c, ldata); - } - - put_tty_queue(c, ldata); - return 0; -} - -rt_inline void n_tty_receive_char_inline(struct tty_struct *tty, unsigned char c) -{ - struct n_tty_data *ldata = tty->disc_data; - - if (L_ECHO(tty)) - { - finish_erasing(ldata); - /* Record the column of first canon char. */ - if (ldata->canon_head == ldata->read_head) - { - echo_set_canon_col(ldata); - } - - echo_char(c, tty); - commit_echoes(tty); - } - /* PARMRK doubling check */ - if (c == (unsigned char) '\377' && I_PARMRK(tty)) - { - put_tty_queue(c, ldata); - } - - put_tty_queue(c, ldata); -} - -static void n_tty_receive_char(struct tty_struct *tty, unsigned char c) -{ - n_tty_receive_char_inline(tty, c); -} - -static void n_tty_receive_char_lnext(struct tty_struct *tty, unsigned char c, char flag) -{ - struct n_tty_data *ldata = tty->disc_data; - - ldata->lnext = 0; - if (flag == TTY_NORMAL) - { - if (I_ISTRIP(tty)) - { - c &= 0x7f; - } - - if (I_IUCLC(tty) && L_IEXTEN(tty)) - { - c = tolower(c); - } - - n_tty_receive_char(tty, c); - } - else - { - //n_tty_receive_char_flagged(tty, c, flag); - } - -} - -static void n_tty_receive_buf_real_raw(struct tty_struct *tty, char *cp, int count) -{ - struct n_tty_data *ldata = tty->disc_data; - size_t n = 0, head = 0; - - head = ldata->read_head & (RT_TTY_BUF - 1); - n = min(count, RT_TTY_BUF - head); - rt_memcpy(read_buf_addr(ldata, head), cp, n); - ldata->read_head += n; - cp += n; - count -= n; - - head = ldata->read_head & (RT_TTY_BUF - 1); - n = min(count, RT_TTY_BUF - head); - rt_memcpy(read_buf_addr(ldata, head), cp, n); - ldata->read_head += n; -} - -static void n_tty_receive_buf_raw(struct tty_struct *tty, char *cp, int count) -{ - struct n_tty_data *ldata = tty->disc_data; - char flag = TTY_NORMAL; - - while (count--) - { - if (flag == TTY_NORMAL) - { - put_tty_queue(*cp++, ldata); - } - } -} - -static void n_tty_receive_buf_standard(struct tty_struct *tty, char *cp, int count) -{ - struct n_tty_data *ldata = tty->disc_data; - char flag = TTY_NORMAL; - - while (count--) - { - char c = *cp++; - - if (I_ISTRIP(tty)) - { - c &= 0x7f; - } - - if (I_IUCLC(tty) && L_IEXTEN(tty)) - { - c = tolower(c); - } - - if (L_EXTPROC(tty)) - { - put_tty_queue(c, ldata); - continue; - } - - if (!test_bit(c, (int *)ldata->char_map)) - { - n_tty_receive_char_inline(tty, c); - } - else if (n_tty_receive_char_special(tty, c) && count) - { - n_tty_receive_char_lnext(tty, *cp++, flag); - count--; - } - } -} - -rt_inline void n_tty_receive_char_fast(struct tty_struct *tty, unsigned char c) -{ - struct n_tty_data *ldata = tty->disc_data; - - if (L_ECHO(tty)) - { - finish_erasing(ldata); - /* Record the column of first canon char. */ - if (ldata->canon_head == ldata->read_head) - { - echo_set_canon_col(ldata); - } - - echo_char(c, tty); - commit_echoes(tty); - } - put_tty_queue(c, ldata); -} - -static void n_tty_receive_buf_fast(struct tty_struct *tty, char *cp, int count) -{ - struct n_tty_data *ldata = tty->disc_data; - char flag = TTY_NORMAL; - - while (count--) - { - unsigned char c = *cp++; - - if (!test_bit(c, (int *)ldata->char_map)) - { - n_tty_receive_char_fast(tty, c); - } - else if (n_tty_receive_char_special(tty, c) && count) - { - n_tty_receive_char_lnext(tty, *cp++, flag); - count--; - } - } -} - -static void __receive_buf(struct tty_struct *tty, char *cp, int count) -{ - struct n_tty_data *ldata = tty->disc_data; - rt_bool_t preops = I_ISTRIP(tty) || (I_IUCLC(tty) && L_IEXTEN(tty)); - - if (ldata->real_raw) - { - n_tty_receive_buf_real_raw(tty, cp, count); - } - - else if (ldata->raw || (L_EXTPROC(tty) && !preops)) - { - n_tty_receive_buf_raw(tty, cp, count); - } - else - { - if (!preops && !I_PARMRK(tty)) - { - n_tty_receive_buf_fast(tty, cp, count); - } - else - { - n_tty_receive_buf_standard(tty, cp, count); - } - flush_echoes(tty); - } - - if (ldata->icanon && !L_EXTPROC(tty)) - return; - - /* publish read_head to consumer */ - ldata->commit_head = ldata->read_head; - - if (read_cnt(ldata)) - { - tty_wakeup_check(tty); - } -} - -int n_tty_receive_buf(struct tty_struct *tty,char *cp, int count) -{ - int size = 0; - struct n_tty_data *ldata = tty->disc_data; - int room = 0, n = 0, rcvd = 0, overflow = 0; - - size = count; - while(1) - { - size_t tail = ldata->read_tail; - - room = RT_TTY_BUF - (ldata->read_head - tail); - - if (I_PARMRK(tty)) - { - room = (room +2)/3; - } - room--; - if (room <= 0) - { - overflow = ldata->icanon && ldata->canon_head == tail; - if (overflow && room < 0) - { - ldata->read_head--; - } - - room = overflow; - } - else - { - overflow = 0; - } - - n = min(size, room); - - if (!n) - { - break; - } - - if (!overflow) - { - __receive_buf(tty, cp, n); - } - - cp += n; - size -= n; - rcvd += n; - } - return count - size; -} - -/** - * job_control - check job control - * @tty: tty - * @file: file handle - * - * Perform job control management checks on this file/tty descriptor - * and if appropriate send any needed signals and return a negative - * error code if action should be taken. - * - * Locking: redirected write test is safe - * current->signal->tty check is safe - * ctrl_lock to safely reference tty->pgrp - */ - -static int job_control(struct tty_struct *tty) -{ - return __tty_check_change(tty, SIGTTIN); -} - -static struct rt_wqueue *_wait_queue_current_get(struct tty_struct *tty) -{ - struct rt_lwp *lwp; - - lwp = lwp_self(); - if (!lwp || !lwp->tty) - lwp = RT_NULL; - - return wait_queue_get(lwp, tty); -} - -static int n_tty_read(struct dfs_file *fd, void *buf, size_t count) -{ - rt_base_t level = 0; - char *b = (char *)buf; - struct tty_struct *tty = RT_NULL; - struct rt_wqueue *wq = RT_NULL; - int wait_ret = 0; - int retval = 0; - int c = 0; - - tty = (struct tty_struct *)fd->vnode->data; - RT_ASSERT(tty != RT_NULL); - c = job_control(tty); - if (c < 0) - { - return c; - } - - struct n_tty_data *ldata = tty->disc_data; - - wq = _wait_queue_current_get(tty); - - while(count) - { - if ((!input_available_p(tty, 0))) - { - if (fd->flags & O_NONBLOCK) - { - retval = -EAGAIN; - break; - } - - wait_ret = rt_wqueue_wait_interruptible(wq, 0, RT_WAITING_FOREVER); - - if (wait_ret != 0) - { - break; - } - } - - level = rt_spin_lock_irqsave(&tty->spinlock); - if (ldata->icanon && !L_EXTPROC(tty)) - { - retval = canon_copy_from_read_buf(tty, b, count); - } - else - { - retval = copy_from_read_buf(tty, b, count); - } - rt_spin_unlock_irqrestore(&tty->spinlock, level); - - if (retval >= 1) - { - break; - } - } - - return retval; -} - -static int n_tty_write(struct dfs_file *fd, const void *buf, size_t count) -{ - int retval = 0; - char *b = (char *)buf; - int c = 0; - struct tty_struct *tty = RT_NULL; - - tty = (struct tty_struct *)fd->vnode->data; - RT_ASSERT(tty != RT_NULL); - retval = tty_check_change(tty); - if (retval) - { - return retval; - } - - process_echoes(tty); - retval = count; - while(1) - { - if (O_OPOST(tty)) - { - while (count > 0) - { - ssize_t num = process_output_block(tty, b, count); - if (num < 0) - { - if (num == -EAGAIN) - { - break; - } - - retval = num; - goto break_out; - } - b += num; - count -= num; - if (count == 0) - { - break; - } - - c = *b; - if (process_output(c, tty) < 0) - { - break; - } - - b++; - count--; - } - retval -= count; - } - else - { - while (count > 0) - { - c = rt_device_write((rt_device_t)tty, -1, b, count); - if (c < 0) - { - retval = c; - goto break_out; - } - b += c; - count -= c; - } - retval -= count; - } - - if (!count) - { - break; - } - if (fd->flags & O_NONBLOCK) - { - break; - } - } -break_out: - return retval; -} - -static int n_tty_flush(struct dfs_file *fd) -{ - return 0; -} - -static int n_tty_lseek(struct dfs_file *fd, off_t offset) -{ - return 0; -} - -static int n_tty_getdents(struct dfs_file *fd, struct dirent *dirp, uint32_t count) -{ - return 0; -} - -static int n_tty_poll(struct dfs_file *fd, struct rt_pollreq *req) -{ - rt_base_t level = 0; - int mask = POLLOUT; - struct tty_struct *tty = RT_NULL; - struct rt_wqueue *wq = RT_NULL; - - tty = (struct tty_struct *)fd->vnode->data; - RT_ASSERT(tty != RT_NULL); - - RT_ASSERT(tty->init_flag == TTY_INIT_FLAG_INITED); - - wq = _wait_queue_current_get(tty); - rt_poll_add(wq, req); - - level = rt_spin_lock_irqsave(&tty->spinlock); - if (input_available_p(tty, 1)) - { - mask |= POLLIN; - } - rt_spin_unlock_irqrestore(&tty->spinlock, level); - - return mask; -} - -struct tty_ldisc_ops n_tty_ops = { - "n_tty", - 0, - n_tty_open, - n_tty_close, - n_tty_ioctl, - n_tty_read, - n_tty_write, - n_tty_flush, - n_tty_lseek, - n_tty_getdents, - n_tty_poll, - n_tty_set_termios, - n_tty_receive_buf, - 0, -}; diff --git a/components/drivers/tty/pty.c b/components/drivers/tty/pty.c deleted file mode 100644 index b6cbda55749..00000000000 --- a/components/drivers/tty/pty.c +++ /dev/null @@ -1,326 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021.12.07 linzhenxing first version - */ -#include -#include -#include - -#define DBG_TAG "PTY" -#ifdef RT_TTY_DEBUG -#define DBG_LVL DBG_LOG -#else -#define DBG_LVL DBG_INFO -#endif /* RT_TTY_DEBUG */ -#include - -#define PTY_PTS_SIZE 10 -static struct tty_struct ptm_dev; -static struct tty_struct pts_devs[PTY_PTS_SIZE]; -static int pts_index = 0; - -static int pts_register(struct tty_struct *ptmx, struct tty_struct *pts, int pts_index); - -/* check free pts device */ -static struct tty_struct *find_freepts(void) -{ - for(int i = 0; i < PTY_PTS_SIZE; i++) - { - if (pts_devs[i].init_flag == TTY_INIT_FLAG_NONE) - { - pts_devs[i].init_flag = TTY_INIT_FLAG_ALLOCED; - return &pts_devs[i]; - } - } - return RT_NULL; -} - -/* Set the lock flag on a pty */ -static int pty_set_lock(struct tty_struct *tty, int *arg) -{ - int val = *arg; - - if (val) - { - tty->pts_lock = val; - } - else - { - tty->pts_lock = val; - } - return 0; -} - -static int pty_get_lock(struct tty_struct *tty, int *arg) -{ - *arg = tty->pts_lock; - return 0; -} - -static int pty_get_index(struct tty_struct *tty, int *arg) -{ - *arg = tty->index; - return 0; -} -/* RT-Thread Device Interface */ -/* - * This function initializes console device. - */ -static rt_err_t pty_device_init(struct rt_device *dev) -{ - rt_err_t result = RT_EOK; - struct tty_struct *tty = RT_NULL; - - RT_ASSERT(dev != RT_NULL); - tty = (struct tty_struct *)dev; - - RT_ASSERT(tty->init_flag == TTY_INIT_FLAG_REGED); - tty->init_flag = TTY_INIT_FLAG_INITED; - - return result; -} - -static rt_err_t pty_device_open(struct rt_device *dev, rt_uint16_t oflag) -{ - rt_err_t result = RT_EOK; - return result; -} - -static rt_err_t pty_device_close(struct rt_device *dev) -{ - rt_err_t result = RT_EOK; - struct tty_struct *tty = (struct tty_struct*)dev; - //struct tty_struct *to = RT_NULL; - - if (tty->subtype == PTY_TYPE_MASTER) - { - // to = tty->other_struct; - // to->init_flag = TTY_INIT_FLAG_NONE; - // to->other_struct = RT_NULL; - // to->foreground = RT_NULL; - // to->index = -1; - // tty_ldisc_kill(to); - // tty->other_struct = RT_NULL; - } - else - { - // to = tty->other_struct; - // to->other_struct = RT_NULL; - // tty->init_flag = TTY_INIT_FLAG_NONE; - // tty->other_struct = RT_NULL; - // tty->foreground = RT_NULL; - // tty->index = -1; - // tty->other_struct = RT_NULL; - // tty_ldisc_kill(tty); - } - - return result; -} - -static rt_ssize_t pty_device_read(struct rt_device *dev, - rt_off_t pos, - void *buffer, - rt_size_t size) -{ - rt_size_t len = 0; - - return len; -} - -static rt_ssize_t pty_device_write(struct rt_device *dev, - rt_off_t pos, - const void *buffer, - rt_size_t size) -{ - rt_size_t len = 0; - rt_base_t level = 0; - struct tty_struct *tty = RT_NULL; - struct tty_struct *to = RT_NULL; - - tty = (struct tty_struct *)dev; - RT_ASSERT(tty != RT_NULL); - RT_ASSERT(tty->init_flag == TTY_INIT_FLAG_INITED); - to = tty->other_struct; - - level = rt_spin_lock_irqsave(&tty->spinlock); - if (to->ldisc->ops->receive_buf) - { - len = to->ldisc->ops->receive_buf(to, (char *)buffer, size); - } - rt_spin_unlock_irqrestore(&tty->spinlock, level); - - return len; -} - -static rt_err_t pty_device_control(rt_device_t dev, int cmd, void *args) -{ - struct tty_struct *tty = (struct tty_struct *)dev; - - switch (cmd) - { - case TIOCSPTLCK: /* Set PT Lock (disallow slave open) */ - return pty_set_lock(tty, (int *)args); - case TIOCGPTLCK: /* Get PT Lock status */ - return pty_get_lock(tty, (int *)args); - case TIOCGPTN: /* Get PT Number */ - return pty_get_index(tty, (int *)args); - } - - return -ENOIOCTLCMD; -} - -static int ptmx_open(struct dfs_file *fd) -{ - int ret = 0; - struct tty_struct *tty = RT_NULL; - struct tty_struct *pts = RT_NULL; - struct tty_ldisc *ld = RT_NULL; - - tty = (struct tty_struct *)fd->vnode->data; - RT_ASSERT(tty != RT_NULL); - - pts = find_freepts(); - if (pts == RT_NULL) - { - LOG_E("No free PTS device found.\n"); - return -1; - } - ret = pts_register(tty, pts, pts_index); - if (ret < 0) - { - LOG_E("pts register fail\n"); - rt_free(pts); - return -1; - } - pts_index++; - tty->other_struct = pts; - - ld = tty->ldisc; - if (ld->ops->open) - { - ret = ld->ops->open(fd); - } - - rt_device_t device = (rt_device_t)fd->vnode->data; - if(fd->vnode->ref_count == 1) - { - ret = rt_device_open(device, fd->flags); - } - - return ret; -} -#ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops pty_device_ops = -{ - pty_device_init, - pty_device_open, - pty_device_close, - pty_device_read, - pty_device_write, - pty_device_control, -}; -#endif /* RT_USING_DEVICE_OPS */ - -static struct dfs_file_ops pts_fops; -static struct dfs_file_ops ptmx_fops; -static int pts_register(struct tty_struct *ptmx, struct tty_struct *pts, int pts_index) -{ - char name[20]; - rt_err_t ret = RT_EOK; - struct rt_device *device = RT_NULL; - - RT_ASSERT(ptmx!=RT_NULL); - - if (pts->init_flag != TTY_INIT_FLAG_ALLOCED) - { - LOG_E("pts%d has been registered\n", pts_index); - ret = (-RT_EBUSY); - } - else - { - tty_init(pts, TTY_DRIVER_TYPE_PTY, PTY_TYPE_SLAVE, NULL); - pts->index = pts_index; - pts->pts_lock = 1; - pts->other_struct = ptmx; - - device = &pts->parent; - device->type = RT_Device_Class_Char; -#ifdef RT_USING_DEVICE_OPS - device->ops = &pty_device_ops; -#else - device->init = pty_device_init; - device->open = pty_device_open; - device->close = pty_device_close; - device->read = pty_device_read; - device->write = pty_device_write; - device->control = pty_device_control; -#endif /* RT_USING_DEVICE_OPS */ - - rt_snprintf(name, sizeof(name), "pts%d", pts_index); - ret = rt_device_register(device, name, RT_DEVICE_FLAG_RDWR); - if (ret != RT_EOK) - { - LOG_E("pts%d register failed\n", pts_index); - ret = -RT_EIO; - } - else - { -#ifdef RT_USING_POSIX_DEVIO - /* set fops */ - memcpy(&pts_fops, tty_get_fops(), sizeof(struct dfs_file_ops)); - device->fops = &pts_fops; -#endif - } - } - - return ret; -} - -static int ptmx_register(void) -{ - rt_err_t ret = RT_EOK; - struct rt_device *device = RT_NULL; - struct tty_struct *ptmx = &ptm_dev; - - RT_ASSERT(ptmx->init_flag == TTY_INIT_FLAG_NONE); - - tty_init(ptmx, TTY_DRIVER_TYPE_PTY, PTY_TYPE_MASTER, NULL); - - device = &(ptmx->parent); - device->type = RT_Device_Class_Char; - -#ifdef RT_USING_DEVICE_OPS - device->ops = &pty_device_ops; -#else - device->init = pty_device_init; - device->open = pty_device_open; - device->close = pty_device_close; - device->read = pty_device_read; - device->write = pty_device_write; - device->control = pty_device_control; -#endif /* RT_USING_DEVICE_OPS */ - - ret = rt_device_register(device, "ptmx", RT_DEVICE_FLAG_RDWR); - if (ret != RT_EOK) - { - LOG_E("ptmx register fail\n"); - ret = -RT_EIO; - } - else - { -#ifdef RT_USING_POSIX_DEVIO - /* set fops */ - memcpy(&ptmx_fops, tty_get_fops(), sizeof(struct dfs_file_ops)); - ptmx_fops.open = ptmx_open; - device->fops = &ptmx_fops; -#endif - } - - return ret; -} -INIT_DEVICE_EXPORT(ptmx_register); diff --git a/components/drivers/tty/tty.c b/components/drivers/tty/tty.c deleted file mode 100644 index 075b177d5c7..00000000000 --- a/components/drivers/tty/tty.c +++ /dev/null @@ -1,504 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-12-07 linzhenxing first version - * 2023-06-26 WangXiaoyao fix bug on foreground app switch - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(RT_USING_POSIX_DEVIO) -#include -#endif - -#define DBG_TAG "TTY" -#ifdef RT_TTY_DEBUG -#define DBG_LVL DBG_LOG -#else -#define DBG_LVL DBG_INFO -#endif /* RT_TTY_DEBUG */ -#include - -const struct termios tty_std_termios = { /* for the benefit of tty drivers */ - .c_iflag = IMAXBEL | IUCLC | INLCR | ICRNL | IGNPAR, - .c_oflag = OPOST, - .c_cflag = B38400 | CS8 | CREAD | HUPCL, - .c_lflag = ISIG | ECHOE | TOSTOP | NOFLSH, - RT_NULL,/* .c_line = N_TTY, */ - .c_cc = INIT_C_CC, - .__c_ispeed = 38400, - .__c_ospeed = 38400 -}; - -void tty_initstack(struct tty_node *node) -{ - node->lwp = RT_NULL; - node->next = RT_NULL; -} - -static struct tty_node tty_node_cache = { RT_NULL, RT_NULL }; - -static struct tty_node *_tty_node_alloc(void) -{ - struct tty_node *node = tty_node_cache.next; - - if (node == RT_NULL) - { - node = rt_calloc(1, sizeof(struct tty_node)); - } - else - { - tty_node_cache.next = node->next; - } - - return node; -} - -static void _tty_node_free(struct tty_node *node) -{ - node->next = tty_node_cache.next; - tty_node_cache.next = node; -} - -int tty_push(struct tty_node **head, struct rt_lwp *lwp) -{ - struct tty_node *node = _tty_node_alloc(); - - if (!node) - { - return -1; - } - - node->lwp = lwp; - node->next = *head; - *head = node; - - return 0; -} - -struct rt_lwp *tty_pop(struct tty_node **head, struct rt_lwp *target_lwp) -{ - struct tty_node *node; - struct rt_lwp *lwp = RT_NULL; - - if (!head || !*head) - { - return RT_NULL; - } - - node = *head; - - if (target_lwp != RT_NULL && node->lwp != target_lwp) - { - struct tty_node *prev = RT_NULL; - - while (node != RT_NULL && node->lwp != target_lwp) - { - prev = node; - node = node->next; - } - - if (node != RT_NULL) - { - /* prev is impossible equ RT_NULL */ - prev->next = node->next; - lwp = target_lwp; - _tty_node_free(node); - } - } - else - { - lwp = (*head)->lwp; - *head = (*head)->next; - node->lwp = RT_NULL; - _tty_node_free(node); - } - - return lwp; -} - -/** - * tty_check_change - check for POSIX terminal changes - * @tty: tty to check - * - * If we try to write to, or set the state of, a terminal and we're - * not in the foreground, send a SIGTTOU. If the signal is blocked or - * ignored, go ahead and perform the operation. (POSIX 7.2) - * - * Locking: ctrl_lock - */ - -int __tty_check_change(struct tty_struct *tty, int sig) -{ - pid_t pgrp = 0, tty_pgrp = 0; - int ret = 0; - struct rt_lwp *lwp; - - lwp = lwp_self(); - - if (lwp == RT_NULL) - { - return 0; - } - - if (lwp->tty != tty) - { - return 0; - } - - pgrp = lwp->__pgrp; - tty_pgrp = tty->pgrp; - - if (tty_pgrp && (pgrp != tty->pgrp)) - { - lwp_signal_kill(lwp, sig, SI_USER, 0); - } - - if (!tty_pgrp) - { - LOG_D("sig=%d, tty->pgrp == -1!\n", sig); - } - return ret; -} - -int tty_check_change(struct tty_struct *tty) -{ - return __tty_check_change(tty, SIGTTOU); -} - -static int tty_open(struct dfs_file *fd) -{ - int ret = 0; - int noctty = 0; - struct tty_struct *tty = RT_NULL; - struct tty_ldisc *ld = RT_NULL; - - tty = (struct tty_struct *)fd->vnode->data; - RT_ASSERT(tty != RT_NULL); - - ld = tty->ldisc; - if (ld->ops->open) - { - ret = ld->ops->open(fd); - } - noctty = (fd->flags & O_NOCTTY); - - rt_device_t device = (rt_device_t)fd->vnode->data; - if (fd->vnode->ref_count == 1) - { - ret = rt_device_open(device, fd->flags); - } - if (current == RT_NULL) //kernel mode not lwp - { - return ret; - } - - if (!noctty && - current->leader && - !current->tty && - tty->session == -1) - { - current->tty = tty; - current->tty_old_pgrp = 0; - tty->session = current->session; - tty->pgrp = current->__pgrp; - tty->foreground = current; - } - - return ret; -} - -static int tty_close(struct dfs_file *fd) -{ - int ret = 0; - struct tty_struct *tty = RT_NULL; - struct tty_ldisc *ld = RT_NULL; - tty = (struct tty_struct *)fd->vnode->data; - RT_ASSERT(tty != RT_NULL); - ld = tty->ldisc; - if (ld->ops->close) - { - //ld->ops->close(tty); - } - if (fd->vnode->ref_count == 1) - { - ret = rt_device_close((rt_device_t)tty); - } - return ret; -} - -static int tiocsctty(struct tty_struct *tty, int arg) -{ - if (current->leader && - (current->session == tty->session)) - { - return 0; - } - - /* - * The process must be a session leader and - * not have a controlling tty already. - */ - if (!current->leader || current->tty) - { - return -EPERM; - } - - if (tty->session > 0) - { - LOG_E("this tty have control process\n"); - - } - current->tty = tty; - current->tty_old_pgrp = 0; - tty->session = current->session; - tty->pgrp = current->__pgrp; - tty->foreground = current; - if (tty->type == TTY_DRIVER_TYPE_PTY) - { - tty->other_struct->foreground = current; - } - return 0; -} - -static int tiocswinsz(struct tty_struct *tty, struct winsize *p_winsize) -{ - rt_kprintf("\x1b[8;%d;%dt", p_winsize->ws_col, p_winsize->ws_row); - return 0; -} - -static int tiocgwinsz(struct tty_struct *tty, struct winsize *p_winsize) -{ - if(rt_thread_self() != rt_thread_find(FINSH_THREAD_NAME)) - { - /* only can be used in tshell thread; otherwise, return default size */ - p_winsize->ws_col = 80; - p_winsize->ws_row = 24; - } - else - { - #define _TIO_BUFLEN 20 - char _tio_buf[_TIO_BUFLEN]; - unsigned char cnt1, cnt2, cnt3, i; - char row_s[4], col_s[4]; - char *p; - - rt_memset(_tio_buf, 0, _TIO_BUFLEN); - - /* send the command to terminal for getting the window size of the terminal */ - rt_kprintf("\033[18t"); - - /* waiting for the response from the terminal */ - i = 0; - while(i < _TIO_BUFLEN) - { - _tio_buf[i] = finsh_getchar(); - if(_tio_buf[i] != 't') - { - i ++; - } - else - { - break; - } - } - if(i == _TIO_BUFLEN) - { - /* buffer overloaded, and return default size */ - p_winsize->ws_col = 80; - p_winsize->ws_row = 24; - return 0; - } - - /* interpreting data eg: "\033[8;1;15t" which means row is 1 and col is 15 (unit: size of ONE character) */ - rt_memset(row_s,0,4); - rt_memset(col_s,0,4); - cnt1 = 0; - while(cnt1 < _TIO_BUFLEN && _tio_buf[cnt1] != ';') - { - cnt1++; - } - cnt2 = ++cnt1; - while(cnt2 < _TIO_BUFLEN && _tio_buf[cnt2] != ';') - { - cnt2++; - } - p = row_s; - while(cnt1 < cnt2) - { - *p++ = _tio_buf[cnt1++]; - } - p = col_s; - cnt2++; - cnt3 = rt_strlen(_tio_buf) - 1; - while(cnt2 < cnt3) - { - *p++ = _tio_buf[cnt2++]; - } - - /* load the window size date */ - p_winsize->ws_col = atoi(col_s); - p_winsize->ws_row = atoi(row_s); - #undef _TIO_BUFLEN - } - - p_winsize->ws_xpixel = 0;/* unused */ - p_winsize->ws_ypixel = 0;/* unused */ - - return 0; -} - -static int tty_ioctl(struct dfs_file *fd, int cmd, void *args) -{ - int ret = 0; - void *p = (void *)args; - struct tty_struct *tty = RT_NULL; - struct tty_struct *real_tty = RT_NULL; - struct tty_ldisc *ld = RT_NULL; - - tty = (struct tty_struct *)fd->vnode->data; - RT_ASSERT(tty != RT_NULL); - - if (tty->type == TTY_DRIVER_TYPE_PTY && tty->subtype == PTY_TYPE_MASTER) - { - real_tty = tty->other_struct; - } - else - { - real_tty = tty; - } - - switch (cmd) - { - case TIOCSCTTY: - return tiocsctty(real_tty, 1); - case TIOCGWINSZ: - return tiocgwinsz(real_tty, p); - case TIOCSWINSZ: - return tiocswinsz(real_tty, p); - } - - ld = tty->ldisc; - if (ld->ops->ioctl) - { - ret = ld->ops->ioctl(fd, cmd, args); - } - return ret; -} - -#ifdef RT_USING_DFS_V2 -static ssize_t tty_read(struct dfs_file *fd, void *buf, size_t count, off_t *pos) -#else -static ssize_t tty_read(struct dfs_file *fd, void *buf, size_t count) -#endif -{ - int ret = 0; - struct tty_struct *tty = RT_NULL; - struct tty_ldisc *ld = RT_NULL; - - tty = (struct tty_struct *)fd->vnode->data; - RT_ASSERT(tty != RT_NULL); - - ld = tty->ldisc; - if (ld && ld->ops->read) - { - ret = ld->ops->read(fd, buf, count); - } - return ret; -} - -#ifdef RT_USING_DFS_V2 -static ssize_t tty_write(struct dfs_file *fd, const void *buf, size_t count, off_t *pos) -#else -static ssize_t tty_write(struct dfs_file *fd, const void *buf, size_t count ) -#endif -{ - int ret = 0; - struct tty_struct *tty = RT_NULL; - struct tty_ldisc *ld = RT_NULL; - - tty = (struct tty_struct *)fd->vnode->data; - RT_ASSERT(tty != RT_NULL); - - ld = tty->ldisc; - if (ld && ld->ops->write) - { - ret = ld->ops->write(fd, buf, count); - } - - return ret; -} - -static int tty_poll(struct dfs_file *fd, struct rt_pollreq *req) -{ - int ret = 0; - struct tty_struct *tty = RT_NULL; - struct tty_ldisc *ld = RT_NULL; - - tty = (struct tty_struct *)fd->vnode->data; - RT_ASSERT(tty != RT_NULL); - ld = tty->ldisc; - if (ld->ops->poll) - { - ret = ld->ops->poll(fd, req); - } - return ret; -} - -static const struct dfs_file_ops tty_fops = -{ - .open = tty_open, - .close = tty_close, - .ioctl = tty_ioctl, - .read = tty_read, - .write = tty_write, - .poll = tty_poll, -}; - -const struct dfs_file_ops *tty_get_fops(void) -{ - return &tty_fops; -} - -int tty_init(struct tty_struct *tty, int type, int subtype, struct rt_device *iodev) -{ - if (tty) - { - struct tty_node *node = NULL; - - node = rt_calloc(1, sizeof(struct tty_node)); - if (node) - { - tty->type = type; - tty->subtype = subtype; - tty->io_dev = iodev; - - tty->head = node; - tty_initstack(tty->head); - - tty->pgrp = -1; - tty->session = -1; - tty->foreground = RT_NULL; - - rt_mutex_init(&tty->lock, "ttyLock", RT_IPC_FLAG_PRIO); - rt_wqueue_init(&tty->wait_queue); - rt_spin_lock_init(&tty->spinlock); - - tty_ldisc_init(tty); - tty->init_termios = tty_std_termios; - tty->init_flag = TTY_INIT_FLAG_REGED; - } - } - - return 0; -} diff --git a/components/drivers/tty/tty_ioctl.c b/components/drivers/tty/tty_ioctl.c deleted file mode 100644 index 92206266c3c..00000000000 --- a/components/drivers/tty/tty_ioctl.c +++ /dev/null @@ -1,122 +0,0 @@ -#include -#include -#include -#if defined(RT_USING_POSIX_DEVIO) -#include -#endif - -#define DBG_TAG "TTY_IOCTL" -#ifdef RT_TTY_DEBUG -#define DBG_LVL DBG_LOG -#else -#define DBG_LVL DBG_INFO -#endif /* RT_TTY_DEBUG */ -#include - -/* - * Internal flag options for termios setting behavior - */ -#define TERMIOS_FLUSH 1 -#define TERMIOS_WAIT 2 -#define TERMIOS_TERMIO 4 -#define TERMIOS_OLD 8 - -/** - * set_termios - set termios values for a tty - * @tty: terminal device - * @arg: user data - * @opt: option information - * - * Helper function to prepare termios data and run necessary other - * functions before using tty_set_termios to do the actual changes. - * - * Locking: - * Called functions take ldisc and termios_rwsem locks - */ - -static int set_termios(struct tty_struct *tty, void *arg, int opt) -{ - struct termios old_termios; - struct tty_ldisc *ld = RT_NULL; - struct termios *new_termios = (struct termios *)arg; - rt_base_t level = 0; - int retval = tty_check_change(tty); - - if (retval) - { - return retval; - } - - memcpy(&old_termios, &(tty->init_termios), sizeof(struct termios)); - level = rt_spin_lock_irqsave(&tty->spinlock); - tty->init_termios = *new_termios; - rt_spin_unlock_irqrestore(&tty->spinlock, level); - ld = tty->ldisc; - if (ld != NULL) - { - if (ld->ops->set_termios) - { - ld->ops->set_termios(tty, &old_termios); - } - } - return 0; -} - -int n_tty_ioctl_extend(struct tty_struct *tty, int cmd, void *args) -{ - int ret = 0; - void *p = (void *)args; - struct tty_struct *real_tty = RT_NULL; - - if (tty->type == TTY_DRIVER_TYPE_PTY && tty->subtype == PTY_TYPE_MASTER) - { - real_tty = tty->other_struct; - } - else - { - real_tty = tty; - } - - switch(cmd) - { - case TCGETS: - case TCGETA: - { - struct termios *tio = (struct termios *)p; - if (tio == RT_NULL) - { - return -RT_EINVAL; - } - - memcpy(tio, &real_tty->init_termios, sizeof(real_tty->init_termios)); - return ret; - } - case TCSETSF: - { - return set_termios(real_tty, p, TERMIOS_FLUSH | TERMIOS_WAIT | TERMIOS_OLD); - } - case TCSETSW: - { - return set_termios(real_tty, p, TERMIOS_WAIT | TERMIOS_OLD); - } - case TCSETS: - { - return set_termios(real_tty, p, TERMIOS_OLD); - } - case TCSETAF: - { - return set_termios(real_tty, p, TERMIOS_FLUSH | TERMIOS_WAIT | TERMIOS_TERMIO); - } - case TCSETAW: - { - return set_termios(real_tty, p, TERMIOS_WAIT | TERMIOS_TERMIO); - } - case TCSETA: - { - return set_termios(real_tty, p, TERMIOS_TERMIO); - } - default: - break; - } - return -ENOIOCTLCMD; -} diff --git a/components/drivers/tty/tty_ldisc.c b/components/drivers/tty/tty_ldisc.c deleted file mode 100644 index f2aef64bcc8..00000000000 --- a/components/drivers/tty/tty_ldisc.c +++ /dev/null @@ -1,178 +0,0 @@ -#include -#include - -#define DBG_TAG "TTY_LDISC" -#ifdef RT_TTY_DEBUG -#define DBG_LVL DBG_LOG -#else -#define DBG_LVL DBG_INFO -#endif /* RT_TTY_DEBUG */ -#include - -extern struct tty_ldisc_ops n_tty_ops; -static struct tty_ldisc_ops *tty_ldiscs[NR_LDISCS] = { - &n_tty_ops, /* N_TTY = 0 */ -}; - -static struct rt_spinlock _spinlock = RT_SPINLOCK_INIT; - -static struct tty_ldisc_ops *get_ldops(int disc) -{ - struct tty_ldisc_ops *ldops = RT_NULL; - rt_base_t level = 0; - level = rt_spin_lock_irqsave(&_spinlock); - ldops = tty_ldiscs[disc]; - if (ldops) - { - ldops->refcount++; - } - rt_spin_unlock_irqrestore(&_spinlock, level); - return ldops; -} - -static void put_ldops(struct tty_ldisc_ops *ldops) -{ - rt_base_t level = 0; - - level = rt_spin_lock_irqsave(&_spinlock); - ldops->refcount--; - rt_spin_unlock_irqrestore(&_spinlock, level); -} - -static struct tty_ldisc *tty_ldisc_get(struct tty_struct *tty, int disc) -{ - struct tty_ldisc *ld = RT_NULL; - struct tty_ldisc_ops *ldops = RT_NULL; - - if (disc < N_TTY || disc >= NR_LDISCS) - { - return RT_NULL; - } - - ldops = get_ldops(disc); - if (ldops == RT_NULL) - { - LOG_E("tty ldisc get error\n"); - return RT_NULL; - } - - ld = rt_malloc(sizeof(struct tty_ldisc)); - if (ld == RT_NULL) - { - ldops->refcount--; - return RT_NULL; - } - - ld->ops = ldops; - ld->tty = tty; - - return ld; -} - -/** - * tty_ldisc_put - release the ldisc - * - * Complement of tty_ldisc_get(). - */ -static void tty_ldisc_put(struct tty_ldisc *ld) -{ - if (ld) - { - put_ldops(ld->ops); - rt_free(ld); - } -} - -/** - * tty_ldisc_close - close a line discipline - * @tty: tty we are opening the ldisc on - * @ld: discipline to close - * - * A helper close method. Also a convenient debugging and check - * point. - */ -static void tty_ldisc_close(struct tty_struct *tty, struct tty_ldisc *ld) -{ - if (ld && ld->ops->close) - { - ld->ops->close(tty); - } -} - -/** - * tty_ldisc_kill - teardown ldisc - * @tty: tty being released - * - * Perform final close of the ldisc and reset tty->ldisc - */ -void tty_ldisc_kill(struct tty_struct *tty) -{ - if (tty && tty->ldisc) - { - /* - * Now kill off the ldisc - */ - tty_ldisc_close(tty, tty->ldisc); - tty_ldisc_put(tty->ldisc); - /* Force an oops if we mess this up */ - tty->ldisc = NULL; - } -} - -int tty_register_ldisc(int disc, struct tty_ldisc_ops *new_ldisc) -{ - int ret = 0; - rt_base_t level = 0; - - if (disc < N_TTY || disc >= NR_LDISCS) - { - return -EINVAL; - } - - level = rt_spin_lock_irqsave(&_spinlock); - tty_ldiscs[disc] = new_ldisc; - new_ldisc->num = disc; - new_ldisc->refcount = 0; - rt_spin_unlock_irqrestore(&_spinlock, level); - - return ret; -} - -/** - * tty_ldisc_release - release line discipline - * @tty: tty being shut down (or one end of pty pair) - * - * Called during the final close of a tty or a pty pair in order to shut - * down the line discpline layer. On exit, each tty's ldisc is NULL. - */ - -void tty_ldisc_release(struct tty_struct *tty) -{ - struct tty_struct *o_tty = tty->other_struct; - - /* - * Shutdown this line discipline. As this is the final close, - * it does not race with the set_ldisc code path. - */ - tty_ldisc_kill(tty); - if (o_tty) - { - tty_ldisc_kill(o_tty); - } -} - -/** - * tty_ldisc_init - ldisc setup for new tty - * @tty: tty being allocated - * - * Set up the line discipline objects for a newly allocated tty. Note that - * the tty structure is not completely set up when this call is made. - */ - -void tty_ldisc_init(struct tty_struct *tty) -{ - if (tty) - { - tty->ldisc = tty_ldisc_get(tty, N_TTY); - } -} diff --git a/components/drivers/wlan/wlan_cmd.c b/components/drivers/wlan/wlan_cmd.c index fe5910b2425..b50261d42a6 100644 --- a/components/drivers/wlan/wlan_cmd.c +++ b/components/drivers/wlan/wlan_cmd.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-08-13 tyx the first version + * 2024-03-24 Evlers fixed a duplicate issue with the wifi scan command */ #include @@ -388,6 +389,7 @@ static void user_ap_info_callback(int event, struct rt_wlan_buff *buff, void *pa struct rt_wlan_info *info = RT_NULL; int index = 0; int ret = RT_EOK; + rt_uint32_t last_num = scan_result.num; RT_ASSERT(event == RT_WLAN_EVT_SCAN_REPORT); RT_ASSERT(buff != RT_NULL); @@ -404,8 +406,12 @@ static void user_ap_info_callback(int event, struct rt_wlan_buff *buff, void *pa scan_filter->ssid.len == info->ssid.len && rt_memcmp(&scan_filter->ssid.val[0], &info->ssid.val[0], scan_filter->ssid.len) == 0)) { - /*Print the info*/ - print_ap_info(info,index); + /*Check whether a new ap is added*/ + if (last_num < scan_result.num) + { + /*Print the info*/ + print_ap_info(info,index); + } index++; *((int *)(parameter)) = index; diff --git a/components/drivers/wlan/wlan_mgnt.c b/components/drivers/wlan/wlan_mgnt.c index 9fae21afff9..5eccdfd101c 100644 --- a/components/drivers/wlan/wlan_mgnt.c +++ b/components/drivers/wlan/wlan_mgnt.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-08-06 tyx the first version + * 2023-12-12 Evlers add the wlan join scan function */ #include @@ -858,7 +859,7 @@ static void rt_wlan_join_scan_callback(int event, struct rt_wlan_buff *buff, voi info->ssid.len == tgt_info->ssid.len) { /*Get the rssi the max ap*/ - if(info->rssi > tgt_info->rssi) + if((info->rssi > tgt_info->rssi) || (tgt_info->rssi == 0)) { tgt_info->security = info->security; tgt_info->band = info->band; diff --git a/components/fal/src/fal_rtt.c b/components/fal/src/fal_rtt.c index 89dcdf47228..f8d548d9a92 100644 --- a/components/fal/src/fal_rtt.c +++ b/components/fal/src/fal_rtt.c @@ -212,7 +212,7 @@ struct fal_mtd_nor_device const struct fal_partition *fal_part; }; -static rt_ssize_t mtd_nor_dev_read(struct rt_mtd_nor_device* device, rt_off_t offset, rt_uint8_t* data, rt_uint32_t length) +static rt_ssize_t mtd_nor_dev_read(struct rt_mtd_nor_device* device, rt_off_t offset, rt_uint8_t* data, rt_size_t length) { int ret = 0; struct fal_mtd_nor_device *part = (struct fal_mtd_nor_device*) device; @@ -233,7 +233,7 @@ static rt_ssize_t mtd_nor_dev_read(struct rt_mtd_nor_device* device, rt_off_t of return ret; } -static rt_ssize_t mtd_nor_dev_write(struct rt_mtd_nor_device* device, rt_off_t offset, const rt_uint8_t* data, rt_uint32_t length) +static rt_ssize_t mtd_nor_dev_write(struct rt_mtd_nor_device* device, rt_off_t offset, const rt_uint8_t* data, rt_size_t length) { int ret = 0; struct fal_mtd_nor_device *part; @@ -255,7 +255,7 @@ static rt_ssize_t mtd_nor_dev_write(struct rt_mtd_nor_device* device, rt_off_t o return ret; } -static rt_err_t mtd_nor_dev_erase(struct rt_mtd_nor_device* device, rt_off_t offset, rt_uint32_t length) +static rt_err_t mtd_nor_dev_erase(struct rt_mtd_nor_device* device, rt_off_t offset, rt_size_t length) { int ret = 0; struct fal_mtd_nor_device *part; @@ -265,7 +265,7 @@ static rt_err_t mtd_nor_dev_erase(struct rt_mtd_nor_device* device, rt_off_t off ret = fal_partition_erase(part->fal_part, offset, length); - if ((rt_uint32_t)ret != length || ret < 0) + if (ret != (int)length || ret < 0) { return -RT_ERROR; } @@ -277,10 +277,10 @@ static rt_err_t mtd_nor_dev_erase(struct rt_mtd_nor_device* device, rt_off_t off static const struct rt_mtd_nor_driver_ops _ops = { - RT_NULL, - mtd_nor_dev_read, - mtd_nor_dev_write, - mtd_nor_dev_erase, + RT_NULL, /* read_id */ + mtd_nor_dev_read, /* read */ + mtd_nor_dev_write, /* write*/ + mtd_nor_dev_erase, /* erase_block */ }; /** @@ -424,7 +424,7 @@ static int char_dev_fopen(struct dfs_file *fd) default: break; } - fd->pos = 0; + DFS_FILE_POS(fd) = 0; return RT_EOK; } @@ -436,15 +436,15 @@ static int char_dev_fread(struct dfs_file *fd, void *buf, size_t count) assert(part != RT_NULL); - if (fd->pos + count > part->fal_part->len) - count = part->fal_part->len - fd->pos; + if (DFS_FILE_POS(fd) + count > part->fal_part->len) + count = part->fal_part->len - DFS_FILE_POS(fd); - ret = fal_partition_read(part->fal_part, fd->pos, buf, count); + ret = fal_partition_read(part->fal_part, DFS_FILE_POS(fd), buf, count); if (ret != (int)(count)) return 0; - fd->pos += ret; + DFS_FILE_POS(fd) += ret; return ret; } @@ -456,15 +456,15 @@ static int char_dev_fwrite(struct dfs_file *fd, const void *buf, size_t count) assert(part != RT_NULL); - if (fd->pos + count > part->fal_part->len) - count = part->fal_part->len - fd->pos; + if (DFS_FILE_POS(fd) + count > part->fal_part->len) + count = part->fal_part->len - DFS_FILE_POS(fd); - ret = fal_partition_write(part->fal_part, fd->pos, buf, count); + ret = fal_partition_write(part->fal_part, DFS_FILE_POS(fd), buf, count); if (ret != (int) count) return 0; - fd->pos += ret; + DFS_FILE_POS(fd) += ret; return ret; } diff --git a/components/finsh/finsh.h b/components/finsh/finsh.h index f8e4ba5060f..9fe36fae5a2 100644 --- a/components/finsh/finsh.h +++ b/components/finsh/finsh.h @@ -35,6 +35,13 @@ typedef long (*syscall_func)(void); #define __TI_FINSH_EXPORT_FUNCTION(f) PRAGMA(DATA_SECTION(f,"FSymTab")) #endif /* __TI_COMPILER_VERSION__ */ +/** + * Macro to export a command along with its name, description, and options to the symbol table in MSVC. + * @param name The function name associated with the command. + * @param cmd The command name. + * @param desc The description of the command. + * @param opt The options associated with the command, used for option completion. + */ #ifdef _MSC_VER #define MSH_FUNCTION_EXPORT_CMD(name, cmd, desc, opt) \ const char __fsym_##cmd##_name[] = #cmd; \ @@ -80,9 +87,11 @@ typedef long (*syscall_func)(void); }; #endif /* _MSC_VER */ -#endif /* end of FINSH_USING_SYMTAB */ - +#endif /* FINSH_USING_SYMTAB */ +/** + * Macro definitions to simplify the declaration of exported functions or commands. + */ #define __MSH_GET_MACRO(_1, _2, _3, _FUN, ...) _FUN #define __MSH_GET_EXPORT_MACRO(_1, _2, _3, _4, _FUN, ...) _FUN @@ -143,9 +152,10 @@ typedef long (*syscall_func)(void); * @param alias is the alias of the command. * @param desc is the description of the command, which will show in help list. * @param opt This is an option, enter any content to enable option completion + * @note + * #define MSH_CMD_EXPORT_ALIAS(command, alias, desc) or + * #define MSH_CMD_EXPORT_ALIAS(command, alias, desc, opt) */ -/* #define MSH_CMD_EXPORT_ALIAS(command, alias, desc) or - #define MSH_CMD_EXPORT_ALIAS(command, alias, desc, opt) */ #define MSH_CMD_EXPORT_ALIAS(...) \ __MSH_GET_EXPORT_MACRO(__VA_ARGS__, _MSH_FUNCTION_EXPORT_CMD3_OPT, \ _MSH_FUNCTION_EXPORT_CMD3)(__VA_ARGS__) @@ -179,9 +189,31 @@ typedef struct msh_cmd_opt const char *des; } msh_cmd_opt_t; +/* Command options declaration and definition macros */ + +/** + * Declares a static array of command options for a specific command. + * @param command The command associated with these options. + */ #define CMD_OPTIONS_STATEMENT(command) static struct msh_cmd_opt command##_msh_options[]; + +/** + * Starts the definition of command options for a specific command. + * @param command The command these options are associated with. + */ #define CMD_OPTIONS_NODE_START(command) static struct msh_cmd_opt command##_msh_options[] = { + +/** + * Defines a single command option. + * @param _id Unique identifier for the option. + * @param _name The name of the option. + * @param _des Description of the option. + */ #define CMD_OPTIONS_NODE(_id, _name, _des) {.id = _id, .name = #_name, .des = #_des}, + +/** + * Marks the end of command options definition. + */ #define CMD_OPTIONS_NODE_END {0},}; void msh_opt_list_dump(void *options); @@ -208,9 +240,6 @@ extern struct finsh_syscall *_syscall_table_begin, *_syscall_table_end; #define FINSH_NEXT_SYSCALL(index) index++ #endif -/* find out system call, which should be implemented in user program */ -struct finsh_syscall *finsh_syscall_lookup(const char *name); - #if !defined(RT_USING_POSIX_STDIO) && defined(RT_USING_DEVICE) void finsh_set_device(const char *device_name); #endif diff --git a/components/finsh/msh_file.c b/components/finsh/msh_file.c index 105dad35706..07e22a82066 100644 --- a/components/finsh/msh_file.c +++ b/components/finsh/msh_file.c @@ -22,6 +22,10 @@ #include #endif +#ifdef RT_USING_SMART +#include "lwp.h" +#endif /* RT_USING_SMART */ + static int msh_readline(int fd, char *line_buf, int size) { char ch; @@ -159,7 +163,11 @@ static int cmd_ls(int argc, char **argv) if (argc == 1) { #ifdef DFS_USING_WORKDIR +#ifdef RT_USING_SMART + ls(lwp_getcwd()); +#else ls(working_directory); +#endif #else ls("/"); #endif diff --git a/components/finsh/shell.c b/components/finsh/shell.c index 0b17a75f00b..e698edd51f9 100644 --- a/components/finsh/shell.c +++ b/components/finsh/shell.c @@ -112,7 +112,11 @@ const char *finsh_get_prompt(void) getcwd(&finsh_prompt[rt_strlen(finsh_prompt)], RT_CONSOLEBUF_SIZE - rt_strlen(finsh_prompt)); #endif - strcat(finsh_prompt, ">"); + if (rt_strlen(finsh_prompt) + 2 < RT_CONSOLEBUF_SIZE) + { + finsh_prompt[rt_strlen(finsh_prompt)] = '>'; + finsh_prompt[rt_strlen(finsh_prompt) + 1] = '\0'; + } return finsh_prompt; } @@ -448,10 +452,28 @@ static void shell_push_history(struct finsh_shell *shell) } #endif +#ifdef RT_USING_HOOK +static void (*_finsh_thread_entry_hook)(void); + +/** + * @ingroup finsh + * + * @brief This function set a hook function at the entry of finsh thread + * + * @param hook the function point to be called + */ +void finsh_thread_entry_sethook(void (*hook)(void)) +{ + _finsh_thread_entry_hook = hook; +} +#endif /* RT_USING_HOOK */ + static void finsh_thread_entry(void *parameter) { int ch; + RT_OBJECT_HOOK_CALL(_finsh_thread_entry_hook, ()); + /* normal is echo mode */ #ifndef FINSH_ECHO_DISABLE_DEFAULT shell->echo_mode = 1; diff --git a/components/finsh/shell.h b/components/finsh/shell.h index a74f4dad057..db4a77d5566 100644 --- a/components/finsh/shell.h +++ b/components/finsh/shell.h @@ -102,4 +102,8 @@ void finsh_set_prompt_mode(rt_uint32_t prompt_mode); const char *finsh_get_password(void); #endif +#ifdef RT_USING_HOOK +void finsh_thread_entry_sethook(void (*hook)(void)); +#endif /* RT_USING_HOOK */ + #endif diff --git a/components/libc/compilers/common/ctime.c b/components/libc/compilers/common/ctime.c index 44822ec3799..c6602698ff1 100644 --- a/components/libc/compilers/common/ctime.c +++ b/components/libc/compilers/common/ctime.c @@ -25,6 +25,7 @@ * 2023-08-12 Meco Man re-implement RT-Thread lightweight timezone API * 2023-09-15 xqyjlj perf rt_hw_interrupt_disable/enable * 2023-10-23 Shell add lock for _g_timerid + * 2023-11-16 Shell Fixup of nanosleep if previous call was interrupted */ #include "sys/time.h" @@ -544,20 +545,24 @@ int nanosleep(const struct timespec *rqtp, struct timespec *rmtp) unsigned long ns = rqtp->tv_sec * NANOSECOND_PER_SECOND + rqtp->tv_nsec; rt_ktime_boottime_get_ns(&old_ts); rt_ktime_hrtimer_ndelay(ns); - if (rt_get_errno() == -RT_EINTR) + if (rt_get_errno() == RT_EINTR) { if (rmtp) { + rt_base_t rsec, rnsec; rt_ktime_boottime_get_ns(&new_ts); - rmtp->tv_sec = 0; - rmtp->tv_nsec = - (old_ts.tv_nsec + ns) - ((new_ts.tv_sec - old_ts.tv_sec) * NANOSECOND_PER_SECOND + new_ts.tv_nsec); - - if (rmtp->tv_nsec > NANOSECOND_PER_SECOND) + rsec = old_ts.tv_sec + rqtp->tv_sec - new_ts.tv_sec; + rnsec = old_ts.tv_nsec + rqtp->tv_nsec - new_ts.tv_nsec; + if (rnsec < 0) + { + rmtp->tv_sec = rsec - 1; + rmtp->tv_nsec = NANOSECOND_PER_SECOND + rnsec; + } + else { - rmtp->tv_nsec %= NANOSECOND_PER_SECOND; - rmtp->tv_sec += rmtp->tv_nsec / NANOSECOND_PER_SECOND; + rmtp->tv_sec = rsec; + rmtp->tv_nsec = rnsec; } } rt_set_errno(EINTR); @@ -874,7 +879,8 @@ static void rtthread_timer_wrapper(void *timerobj) } #ifdef RT_USING_SMART /* this field is named as tid in musl */ - int tid = *(int *)&timer->sigev_notify_function; + void *ptid = &timer->sigev_notify_function; + int tid = *(int *)ptid; struct lwp_timer_event_param *data = rt_container_of(timer->work, struct lwp_timer_event_param, work); data->signo = timer->sigev_signo; diff --git a/components/libc/compilers/common/include/dirent.h b/components/libc/compilers/common/include/dirent.h index f1a45d29864..51451e2d59b 100644 --- a/components/libc/compilers/common/include/dirent.h +++ b/components/libc/compilers/common/include/dirent.h @@ -32,9 +32,13 @@ extern "C" { #define DT_UNKNOWN 0x00 #define DT_FIFO 0x01 -#define DT_SYMLINK 0x03 +#define DT_CHR 0x02 #define DT_DIR 0x04 +#define DT_BLK 0x06 #define DT_REG 0x08 +#define DT_LNK 0x0a +#define DT_SOCK 0x0c +#define DT_SYMLINK DT_LNK #ifndef HAVE_DIR_STRUCTURE #define HAVE_DIR_STRUCTURE diff --git a/components/libc/compilers/common/include/sys/ioctl.h b/components/libc/compilers/common/include/sys/ioctl.h index ab0c0695508..908074863ac 100644 --- a/components/libc/compilers/common/include/sys/ioctl.h +++ b/components/libc/compilers/common/include/sys/ioctl.h @@ -15,6 +15,10 @@ extern "C" { #endif +#ifdef RT_USING_MUSLLIBC +#include_next +#else + struct winsize { unsigned short ws_row; @@ -23,9 +27,6 @@ struct winsize unsigned short ws_ypixel; }; -#ifdef RT_USING_MUSLLIBC -#include -#else /* * Direction bits, which any architecture can choose to override * before including this file. diff --git a/components/libc/compilers/common/include/sys/unistd.h b/components/libc/compilers/common/include/sys/unistd.h index b9c64f3bb61..824891d57e4 100644 --- a/components/libc/compilers/common/include/sys/unistd.h +++ b/components/libc/compilers/common/include/sys/unistd.h @@ -19,6 +19,8 @@ extern "C" { #endif +#define _POSIX_VDISABLE 0 + #define STDIN_FILENO 0 /* standard input file descriptor */ #define STDOUT_FILENO 1 /* standard output file descriptor */ #define STDERR_FILENO 2 /* standard error file descriptor */ diff --git a/components/libc/compilers/dlib/SConscript b/components/libc/compilers/dlib/SConscript index 98f664e8d95..51573b9e9a5 100644 --- a/components/libc/compilers/dlib/SConscript +++ b/components/libc/compilers/dlib/SConscript @@ -13,7 +13,8 @@ if rtconfig.PLATFORM in ['iccarm']: from iar import IARVersion CPPDEFINES = CPPDEFINES + ['_DLIB_FILE_DESCRIPTOR'] - if LooseVersion(IARVersion()) < LooseVersion("8.20.1"): + iar_version = LooseVersion(IARVersion()) + if iar_version != LooseVersion("0.0") and iar_version < LooseVersion("8.20.1"): CPPDEFINES = CPPDEFINES + ['_DLIB_THREAD_SUPPORT'] group = DefineGroup('Compiler', src, depend = [''], CPPDEFINES = CPPDEFINES) diff --git a/components/libc/compilers/musl/fcntl.h b/components/libc/compilers/musl/fcntl.h index 05d466f8486..9388f10de17 100644 --- a/components/libc/compilers/musl/fcntl.h +++ b/components/libc/compilers/musl/fcntl.h @@ -13,12 +13,37 @@ #include_next -#ifndef O_DIRECTORY -#define O_DIRECTORY 0x200000 -#endif +#define O_CREAT 0100 +#define O_EXCL 0200 +#define O_NOCTTY 0400 +#define O_TRUNC 01000 +#define O_APPEND 02000 +#define O_NONBLOCK 04000 +#define O_DSYNC 010000 +#define O_SYNC 04010000 +#define O_RSYNC 04010000 +#define O_DIRECTORY 040000 +#define O_NOFOLLOW 0100000 +#define O_CLOEXEC 02000000 + +#define O_ASYNC 020000 +#define O_DIRECT 0200000 +#define O_LARGEFILE 0400000 +#define O_NOATIME 01000000 +#define O_PATH 010000000 +#define O_TMPFILE 020040000 +#define O_NDELAY O_NONBLOCK #ifndef O_BINARY -#define O_BINARY 0x10000 +#define O_BINARY 00 #endif +#ifndef O_SEARCH +#define O_SEARCH O_PATH +#endif /* O_SEARCH */ + +#ifndef O_EXEC +#define O_EXEC O_PATH +#endif /* O_EXEC */ + #endif diff --git a/components/libc/cplusplus/cpp11/atomic_8.c b/components/libc/cplusplus/cpp11/atomic_8.c index bb8a2b637bf..65fe22abcf7 100644 --- a/components/libc/cplusplus/cpp11/atomic_8.c +++ b/components/libc/cplusplus/cpp11/atomic_8.c @@ -11,6 +11,7 @@ #include #include #include +#include /* * override gcc builtin atomic function for std::atomic, std::atomic @@ -69,6 +70,84 @@ bool __atomic_compare_exchange_8(volatile void *ptr, volatile void *expected, ui return exchanged; } +/** + * @param size is the length of the value to load. + * + * @param mem is the source memory to load the value from. + * + * @param _return is the pointer to the space where the loaded value will be stored. + */ +void __atomic_load(size_t size, void *mem, void *_return, int model) +{ + rt_base_t level; + level = rt_hw_interrupt_disable(); + rt_memcpy(_return, mem, size); + rt_hw_interrupt_enable(level); +} + +/** + * @param size is the length of the value to store. + * + * @param mem is the destination memory space to store the value. + * + * @param val is the pointer to the value to store. + */ +void __atomic_store(size_t size, void *mem, void *val, int model) +{ + rt_base_t level; + level = rt_hw_interrupt_disable(); + rt_memcpy(mem, val, size); + rt_hw_interrupt_enable(level); +} + +/** + * @param size is the length of value to exchange. + * + * @param mem is the destination space to exchange. + * + * @param val is the pointer of value to exchange. + * + * @param _return gives back the the value before exchanging. + */ +void __atomic_exchange(size_t size, void *mem, void *val, void *_return, int model) +{ + rt_base_t level; + level = rt_hw_interrupt_disable(); + rt_memcpy(_return, mem, size); + rt_memcpy(mem, val, size); + rt_hw_interrupt_enable(level); +} + +/** + * @param size is the length of value to operate. + * + * @param obj is the destination value space to operate. + * + * @param expected is the value to be compared with obj. + * + * @param desired is the value pointer to be written into obj, under the condition that *expected equals *obj. + * + * @return true if succeed in writing *desired into *obj; false if not. +*/ +bool __atomic_compare_exchange(size_t size, void *obj, void *expected, void *desired, int success, int failure) +{ + rt_base_t level; + volatile bool exchanged = false; + level = rt_hw_interrupt_disable(); + if (rt_memcmp(obj, expected, size) == 0) + { + rt_memcpy(obj, desired, size); + exchanged = true; + } + else + { + rt_memcpy(expected, obj, size); + exchanged = false; + } + rt_hw_interrupt_enable(level); + return exchanged; +} + #define __atomic_fetch_op_8(OPNAME, OP) \ uint64_t __atomic_fetch_##OPNAME##_8(volatile void *ptr, uint64_t val, int memorder) {\ volatile uint64_t* val_ptr = (volatile uint64_t*)ptr;\ diff --git a/components/libc/posix/Kconfig b/components/libc/posix/Kconfig index d8627c242a6..7d6539234f5 100644 --- a/components/libc/posix/Kconfig +++ b/components/libc/posix/Kconfig @@ -27,7 +27,7 @@ if RT_USING_POSIX_FS select RT_USING_POSIX_POLL default y if RT_USING_SMART default n - + config RT_USING_POSIX_EVENTFD bool "Enable I/O event eventfd " select RT_USING_POSIX_POLL diff --git a/components/libc/posix/delay/delay.c b/components/libc/posix/delay/delay.c index de8b9bbf76d..76b9e508342 100644 --- a/components/libc/posix/delay/delay.c +++ b/components/libc/posix/delay/delay.c @@ -12,36 +12,68 @@ #include #include +/** + * @brief Delays the execution of the current thread for the specified number of milliseconds. + * + * @param msecs The number of milliseconds to sleep. + */ void msleep(unsigned int msecs) { rt_thread_mdelay(msecs); } RTM_EXPORT(msleep); +/** + * @brief Delays the execution of the current thread for the specified number of seconds. + * + * @param seconds The number of seconds to sleep. + */ void ssleep(unsigned int seconds) { msleep(seconds * 1000); } RTM_EXPORT(ssleep); +/** + * @brief Delays the execution of the current thread for the specified number of milliseconds. + * + * @param msecs The number of milliseconds to delay. + */ void mdelay(unsigned long msecs) { rt_hw_us_delay(msecs * 1000); } RTM_EXPORT(mdelay); +/** + * @brief Delays the execution of the current thread for the specified number of microseconds. + * + * @param usecs The number of microseconds to delay. + */ void udelay(unsigned long usecs) { rt_hw_us_delay(usecs); } RTM_EXPORT(udelay); +/** + * @brief Delays the execution of the current thread for approximately one microsecond. + * + * @param nsecs This parameter is ignored. + */ void ndelay(unsigned long nsecs) { rt_hw_us_delay(1); } RTM_EXPORT(ndelay); +/** + * @brief Delays the execution of the current thread for the specified number of seconds. + * + * @param seconds The number of seconds to sleep. + * + * @return Returns 0 on success. + */ unsigned int sleep(unsigned int seconds) { if (rt_thread_self() != RT_NULL) @@ -61,6 +93,13 @@ unsigned int sleep(unsigned int seconds) } RTM_EXPORT(sleep); +/** + * @brief Delays the execution of the current thread for the specified number of microseconds. + * + * @param usec The number of microseconds to sleep. + * + * @return Returns 0 on success. + */ int usleep(useconds_t usec) { if (rt_thread_self() != RT_NULL) diff --git a/components/libc/posix/io/aio/aio.c b/components/libc/posix/io/aio/aio.c index 978522e4c2d..a6d8acab091 100644 --- a/components/libc/posix/io/aio/aio.c +++ b/components/libc/posix/io/aio/aio.c @@ -4,8 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2017/12/30 Bernard The first version. + * Date Author Notes + * 2017/12/30 Bernard The first version. + * 2024/03/26 TroyMitchelle Added some function comments + * 2024/03/27 TroyMitchelle Fix the issue of incorrect return of invalid parameters in aio_write */ #include @@ -63,7 +65,7 @@ int aio_cancel(int fd, struct aiocb *cb) * asynchronous I/O operation is the errno value that would be set by the corresponding * read(), write(), */ -int aio_error (const struct aiocb *cb) +int aio_error(const struct aiocb *cb) { if (cb) { @@ -134,6 +136,18 @@ static void aio_fync_work(struct rt_work* work, void* work_data) return ; } +/** + * @brief Initiates an asynchronous fsync operation. + * + * This function initiates an asynchronous fsync operation on the file associated + * with the specified aiocb structure. The operation is queued to the workqueue + * for execution. + * + * @param op The operation to be performed. This parameter is ignored. + * @param cb Pointer to the aiocb structure representing the asynchronous fsync operation. + * + * @return Returns 0 on success. + */ int aio_fsync(int op, struct aiocb *cb) { rt_base_t level; @@ -149,6 +163,16 @@ int aio_fsync(int op, struct aiocb *cb) return 0; } +/** + * @brief Worker function for asynchronous read operation. + * + * This function performs the actual reading of data from the file associated with + * the specified aiocb structure. It sets the result of the operation in the + * aio_result field of the aiocb structure. + * + * @param work Pointer to the work item. + * @param work_data Pointer to the aiocb structure representing the asynchronous read operation. + */ static void aio_read_work(struct rt_work* work, void* work_data) { int len; @@ -290,6 +314,16 @@ int aio_suspend(const struct aiocb *const list[], int nent, return -ENOSYS; } +/** + * @brief Worker function for asynchronous write operation. + * + * This function performs the actual writing of data to the file associated with + * the specified aiocb structure. It sets the result of the operation in the + * aio_result field of the aiocb structure. + * + * @param work Pointer to the work item. + * @param work_data Pointer to the aiocb structure representing the asynchronous write operation. + */ static void aio_write_work(struct rt_work* work, void* work_data) { rt_base_t level; @@ -368,7 +402,8 @@ int aio_write(struct aiocb *cb) /* check access mode */ oflags = fcntl(cb->aio_fildes, F_GETFL, 0); - if ((oflags & O_ACCMODE) != O_WRONLY || + /* If the flag is not in write only or read-write mode, it cannot be written then an invalid parameter is returned */ + if ((oflags & O_ACCMODE) != O_WRONLY && (oflags & O_ACCMODE) != O_RDWR) return -EINVAL; @@ -453,6 +488,14 @@ int lio_listio(int mode, struct aiocb * const list[], int nent, return -ENOSYS; } +/** + * @brief Initializes the asynchronous I/O system. + * + * This function initializes the asynchronous I/O system by creating a workqueue + * for asynchronous I/O operations. + * + * @return Returns 0 on success. + */ int aio_system_init(void) { aio_queue = rt_workqueue_create("aio", 2048, RT_THREAD_PRIORITY_MAX/2); diff --git a/components/libc/posix/io/aio/aio.h b/components/libc/posix/io/aio/aio.h index 35a5c194dbb..7e104850d74 100644 --- a/components/libc/posix/io/aio/aio.h +++ b/components/libc/posix/io/aio/aio.h @@ -4,8 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2017/12/30 Bernard The first version. + * Date Author Notes + * 2017/12/30 Bernard The first version. + * 2024/03/26 TroyMitchelle Align comments within the aiocb structure */ #ifndef __AIO_H__ @@ -17,14 +18,14 @@ struct aiocb { - int aio_fildes; /* File descriptor. */ - off_t aio_offset; /* File offset. */ - - volatile void *aio_buf; /* Location of buffer. */ - size_t aio_nbytes; /* Length of transfer. */ - int aio_reqprio; /* Request priority offset. */ - struct sigevent aio_sigevent; /* Signal number and value. */ - int aio_lio_opcode; /* Operation to be performed. */ + int aio_fildes; /* File descriptor. */ + off_t aio_offset; /* File offset. */ + + volatile void *aio_buf; /* Location of buffer. */ + size_t aio_nbytes; /* Length of transfer. */ + int aio_reqprio; /* Request priority offset. */ + struct sigevent aio_sigevent; /* Signal number and value. */ + int aio_lio_opcode; /* Operation to be performed. */ int aio_result; struct rt_work aio_work; diff --git a/components/libc/posix/io/epoll/epoll.c b/components/libc/posix/io/epoll/epoll.c index 6f579e5d7d6..7677b8deea5 100644 --- a/components/libc/posix/io/epoll/epoll.c +++ b/components/libc/posix/io/epoll/epoll.c @@ -4,8 +4,14 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2023-07-29 zmq810150896 first version + * Date Author Notes + * 2023-07-29 zmq810150896 first version + * 2024-03-26 TroyMitchelle Add comments for all functions, members within structure members and fix incorrect naming of triggered + * 2023-12-14 Shell When poll goes to sleep before the waitqueue has added a + * record and finished enumerating all the fd's, it may be + * incorrectly woken up. This is basically because the poll + * mechanism wakeup algorithm does not correctly distinguish + * the current wait state. */ #include @@ -26,32 +32,38 @@ struct rt_eventpoll; +enum rt_epoll_status { + RT_EPOLL_STAT_INIT, + RT_EPOLL_STAT_TRIG, + RT_EPOLL_STAT_WAITING, +}; + /* Monitor queue */ struct rt_fd_list { - rt_uint32_t revents; /* Monitored events */ - struct epoll_event epev; - rt_pollreq_t req; - struct rt_eventpoll *ep; - struct rt_wqueue_node wqn; - int exclusive;/* If triggered horizontally, a check is made to see if the data has been read, and if there is any data left to read, the readability event is returned in the next epoll_wait */ - rt_bool_t is_rdl_node; - int fd; - struct rt_fd_list *next; - rt_slist_t rdl_node; + rt_uint32_t revents; /**< Monitored events */ + struct epoll_event epev; /**< Epoll event structure */ + rt_pollreq_t req; /**< Poll request structure */ + struct rt_eventpoll *ep; /**< Pointer to the associated event poll */ + struct rt_wqueue_node wqn; /**< Wait queue node */ + int exclusive; /**< Indicates if the event is exclusive */ + rt_bool_t is_rdl_node; /**< Indicates if the node is in the ready list */ + int fd; /**< File descriptor */ + struct rt_fd_list *next; /**< Pointer to the next file descriptor list */ + rt_slist_t rdl_node; /**< Ready list node */ }; struct rt_eventpoll { - rt_uint32_t tirggered; /* the waited thread whether triggered */ - rt_wqueue_t epoll_read; - rt_thread_t polling_thread; - struct rt_mutex lock; - struct rt_fd_list *fdlist; /* Monitor list */ - int eventpoll_num; /* Number of ready lists */ - rt_pollreq_t req; - struct rt_spinlock spinlock; - rt_slist_t rdl_head; + rt_wqueue_t epoll_read; /**< Epoll read queue */ + rt_thread_t polling_thread; /**< Polling thread */ + struct rt_mutex lock; /**< Mutex lock */ + struct rt_fd_list *fdlist; /**< Monitor list */ + int eventpoll_num; /**< Number of ready lists */ + rt_pollreq_t req; /**< Poll request structure */ + struct rt_spinlock spinlock; /**< Spin lock */ + rt_slist_t rdl_head; /**< Ready list head */ + enum rt_epoll_status status; /* the waited thread whether triggered */ }; static int epoll_close(struct dfs_file *file); @@ -65,6 +77,15 @@ static const struct dfs_file_ops epoll_fops = .poll = epoll_poll, }; +/** + * @brief Closes the file descriptor list associated with epoll. + * + * This function closes the file descriptor list associated with epoll and frees the allocated memory. + * + * @param fdlist Pointer to the file descriptor list. + * + * @return Returns 0 on success. + */ static int epoll_close_fdlist(struct rt_fd_list *fdlist) { struct rt_fd_list *fre_node, *list; @@ -75,8 +96,7 @@ static int epoll_close_fdlist(struct rt_fd_list *fdlist) while (list->next != RT_NULL) { fre_node = list->next; - if (fre_node->wqn.wqueue) - rt_wqueue_remove(&fre_node->wqn); + rt_wqueue_remove(&fre_node->wqn); list->next = fre_node->next; rt_free(fre_node); @@ -88,6 +108,15 @@ static int epoll_close_fdlist(struct rt_fd_list *fdlist) return 0; } +/** + * @brief Closes the epoll file descriptor. + * + * This function closes the epoll file descriptor and cleans up associated resources. + * + * @param file Pointer to the file structure. + * + * @return Returns 0 on success. + */ static int epoll_close(struct dfs_file *file) { struct rt_eventpoll *ep; @@ -118,6 +147,16 @@ static int epoll_close(struct dfs_file *file) return 0; } +/** + * @brief Polls the epoll file descriptor for events. + * + * This function polls the epoll file descriptor for events and updates the poll request accordingly. + * + * @param file Pointer to the file structure. + * @param req Pointer to the poll request structure. + * + * @return Returns the events occurred on success. + */ static int epoll_poll(struct dfs_file *file, struct rt_pollreq *req) { struct rt_eventpoll *ep; @@ -144,18 +183,29 @@ static int epoll_poll(struct dfs_file *file, struct rt_pollreq *req) return events; } +/** + * @brief Callback function for the wait queue. + * + * This function is called when the file descriptor is ready for polling. + * + * @param wait Pointer to the wait queue node. + * @param key Key associated with the wait queue node. + * + * @return Returns 0 on success. + */ static int epoll_wqueue_callback(struct rt_wqueue_node *wait, void *key) { struct rt_fd_list *fdlist; struct rt_eventpoll *ep; rt_base_t level; + int is_waiting = 0; if (key && !((rt_ubase_t)key & wait->key)) return -1; fdlist = rt_container_of(wait, struct rt_fd_list, wqn); - ep = fdlist->ep; + if (ep) { level = rt_spin_lock_irqsave(&ep->spinlock); @@ -164,16 +214,30 @@ static int epoll_wqueue_callback(struct rt_wqueue_node *wait, void *key) rt_slist_append(&ep->rdl_head, &fdlist->rdl_node); fdlist->exclusive = 0; fdlist->is_rdl_node = RT_TRUE; - ep->tirggered = 1; - ep->eventpoll_num ++; + ep->eventpoll_num++; + is_waiting = (ep->status == RT_EPOLL_STAT_WAITING); + ep->status = RT_EPOLL_STAT_TRIG; rt_wqueue_wakeup(&ep->epoll_read, (void *)POLLIN); } rt_spin_unlock_irqrestore(&ep->spinlock, level); } - return __wqueue_default_wake(wait, key); + if (is_waiting) + { + return __wqueue_default_wake(wait, key); + } + + return -1; } +/** + * @brief Adds a callback function to the wait queue associated with epoll. + * + * This function adds a callback function to the wait queue associated with epoll. + * + * @param wq Pointer to the wait queue. + * @param req Pointer to the poll request structure. + */ static void epoll_wqueue_add_callback(rt_wqueue_t *wq, rt_pollreq_t *req) { struct rt_fd_list *fdlist; @@ -191,6 +255,14 @@ static void epoll_wqueue_add_callback(rt_wqueue_t *wq, rt_pollreq_t *req) rt_wqueue_add(wq, &fdlist->wqn); } +/** + * @brief Installs a file descriptor list into the epoll control structure. + * + * This function installs a file descriptor list into the epoll control structure. + * + * @param fdlist Pointer to the file descriptor list. + * @param ep Pointer to the epoll control structure. + */ static void epoll_ctl_install(struct rt_fd_list *fdlist, struct rt_eventpoll *ep) { rt_uint32_t mask = 0; @@ -209,7 +281,7 @@ static void epoll_ctl_install(struct rt_fd_list *fdlist, struct rt_eventpoll *ep rt_slist_append(&ep->rdl_head, &fdlist->rdl_node); fdlist->exclusive = 0; fdlist->is_rdl_node = RT_TRUE; - ep->tirggered = 1; + ep->status = RT_EPOLL_STAT_TRIG; ep->eventpoll_num ++; rt_spin_unlock_irqrestore(&ep->spinlock, level); rt_mutex_release(&ep->lock); @@ -217,9 +289,16 @@ static void epoll_ctl_install(struct rt_fd_list *fdlist, struct rt_eventpoll *ep } } +/** + * @brief Initializes the epoll control structure. + * + * This function initializes the epoll control structure. + * + * @param ep Pointer to the epoll control structure. + */ static void epoll_member_init(struct rt_eventpoll *ep) { - ep->tirggered = 0; + ep->status = RT_EPOLL_STAT_INIT; ep->eventpoll_num = 0; ep->polling_thread = rt_thread_self(); ep->fdlist = RT_NULL; @@ -230,6 +309,15 @@ static void epoll_member_init(struct rt_eventpoll *ep) rt_spin_lock_init(&ep->spinlock); } +/** + * @brief Initializes the epoll file descriptor. + * + * This function initializes the epoll file descriptor. + * + * @param fd File descriptor. + * + * @return Returns 0 on success. + */ static int epoll_epf_init(int fd) { struct dfs_file *df; @@ -286,6 +374,15 @@ static int epoll_epf_init(int fd) return ret; } +/** + * @brief Creates an epoll file descriptor. + * + * This function creates an epoll file descriptor. + * + * @param size Size of the epoll instance. + * + * @return Returns the file descriptor on success, or -1 on failure. + */ static int epoll_do_create(int size) { rt_err_t ret = -1; @@ -318,6 +415,17 @@ static int epoll_do_create(int size) return ret; } +/** + * @brief Adds a file descriptor to the epoll instance. + * + * This function adds a file descriptor to the epoll instance. + * + * @param df Pointer to the file structure. + * @param fd File descriptor to add. + * @param event Pointer to the epoll event structure. + * + * @return Returns 0 on success, or an error code on failure. + */ static int epoll_ctl_add(struct dfs_file *df, int fd, struct epoll_event *event) { struct rt_fd_list *fdlist; @@ -370,6 +478,16 @@ static int epoll_ctl_add(struct dfs_file *df, int fd, struct epoll_event *event) return ret; } +/** + * @brief Removes a file descriptor from the epoll instance. + * + * This function removes a file descriptor from the epoll instance. + * + * @param df Pointer to the file structure. + * @param fd File descriptor to remove. + * + * @return Returns 0 on success, or an error code on failure. + */ static int epoll_ctl_del(struct dfs_file *df, int fd) { struct rt_fd_list *fdlist, *fre_fd, *rdlist; @@ -423,6 +541,17 @@ static int epoll_ctl_del(struct dfs_file *df, int fd) return ret; } +/** + * @brief Modifies the events associated with a file descriptor in the epoll instance. + * + * This function modifies the events associated with a file descriptor in the epoll instance. + * + * @param df Pointer to the file structure. + * @param fd File descriptor to modify. + * @param event Pointer to the epoll event structure. + * + * @return Returns 0 on success, or an error code on failure. + */ static int epoll_ctl_mod(struct dfs_file *df, int fd, struct epoll_event *event) { struct rt_fd_list *fdlist; @@ -458,6 +587,19 @@ static int epoll_ctl_mod(struct dfs_file *df, int fd, struct epoll_event *event) return ret; } +/** + * @brief Controls an epoll instance. + * + * This function controls an epoll instance, performing operations such as adding, + * modifying, or removing file descriptors associated with the epoll instance. + * + * @param epfd File descriptor of the epoll instance. + * @param op Operation to perform (EPOLL_CTL_ADD, EPOLL_CTL_DEL, or EPOLL_CTL_MOD). + * @param fd File descriptor to add, modify, or remove. + * @param event Pointer to the epoll event structure. + * + * @return Returns 0 on success, or -1 on failure with errno set appropriately. + */ static int epoll_do_ctl(int epfd, int op, int fd, struct epoll_event *event) { struct dfs_file *epdf; @@ -483,7 +625,7 @@ static int epoll_do_ctl(int epfd, int op, int fd, struct epoll_event *event) rt_set_errno(EINVAL); return -1; } - event->events |= EPOLLERR | EPOLLHUP; + event->events |= EPOLLERR | EPOLLHUP; } if (!fd_get(fd)) @@ -528,6 +670,17 @@ static int epoll_do_ctl(int epfd, int op, int fd, struct epoll_event *event) return ret; } + +/** + * @brief Waits for events on an epoll instance with a specified timeout. + * + * This function waits for events on the specified epoll instance within the given timeout. + * + * @param ep Pointer to the epoll instance. + * @param msec Timeout in milliseconds. + * + * @return Returns 0 if no events occurred within the timeout, or 1 if events were triggered. + */ static int epoll_wait_timeout(struct rt_eventpoll *ep, int msec) { rt_int32_t timeout; @@ -541,7 +694,7 @@ static int epoll_wait_timeout(struct rt_eventpoll *ep, int msec) level = rt_spin_lock_irqsave(&ep->spinlock); - if (timeout != 0 && !ep->tirggered) + if (timeout != 0 && ep->status != RT_EPOLL_STAT_TRIG) { if (rt_thread_suspend_with_flag(thread, RT_KILLABLE) == RT_EOK) { @@ -553,20 +706,34 @@ static int epoll_wait_timeout(struct rt_eventpoll *ep, int msec) rt_timer_start(&(thread->thread_timer)); } + ep->status = RT_EPOLL_STAT_WAITING; + rt_spin_unlock_irqrestore(&ep->spinlock, level); rt_schedule(); level = rt_spin_lock_irqsave(&ep->spinlock); + if (ep->status == RT_EPOLL_STAT_WAITING) + ep->status = RT_EPOLL_STAT_INIT; } } - ret = !ep->tirggered; + ret = !(ep->status == RT_EPOLL_STAT_TRIG); rt_spin_unlock_irqrestore(&ep->spinlock, level); return ret; } +/** + * @brief Gets events associated with a file descriptor in the epoll instance. + * + * This function gets events associated with a file descriptor in the epoll instance. + * + * @param fl Pointer to the file descriptor list structure. + * @param req Pointer to the poll request structure. + * + * @return Returns the bitmask of events associated with the file descriptor. + */ static int epoll_get_event(struct rt_fd_list *fl, rt_pollreq_t *req) { struct dfs_file *df; @@ -594,6 +761,18 @@ static int epoll_get_event(struct rt_fd_list *fl, rt_pollreq_t *req) return mask; } +/** + * @brief Performs epoll operation to get triggered events. + * + * This function performs epoll operation to get triggered events. + * + * @param ep Pointer to the epoll instance. + * @param events Pointer to the array to store triggered events. + * @param maxevents Maximum number of events to store in the array. + * @param timeout Timeout value in milliseconds. + * + * @return Returns the number of triggered events. + */ static int epoll_do(struct rt_eventpoll *ep, struct epoll_event *events, int maxevents, int timeout) { struct rt_fd_list *rdlist; @@ -708,7 +887,7 @@ static int epoll_do(struct rt_eventpoll *ep, struct epoll_event *events, int max if (event_num || istimeout) { level = rt_spin_lock_irqsave(&ep->spinlock); - ep->tirggered = 0; + ep->status = RT_EPOLL_STAT_INIT; rt_spin_unlock_irqrestore(&ep->spinlock, level); if ((timeout >= 0) || (event_num > 0)) break; @@ -723,6 +902,19 @@ static int epoll_do(struct rt_eventpoll *ep, struct epoll_event *events, int max return event_num; } +/** + * @brief Waits for events on an epoll instance with specified parameters. + * + * This function waits for events on the specified epoll instance within the given timeout, optionally blocking signals based on the provided signal set. + * + * @param epfd File descriptor referring to the epoll instance. + * @param events Pointer to the array to store triggered events. + * @param maxevents Maximum number of events to store in the array. + * @param timeout Timeout value in milliseconds. + * @param ss Pointer to the signal set indicating signals to block during the wait operation. Pass NULL if no signals need to be blocked. + * + * @return Returns the number of triggered events on success, or -1 on failure. + */ static int epoll_do_wait(int epfd, struct epoll_event *events, int maxevents, int timeout, const sigset_t *ss) { struct rt_eventpoll *ep; @@ -736,7 +928,7 @@ static int epoll_do_wait(int epfd, struct epoll_event *events, int maxevents, in lwp_thread_signal_mask(rt_thread_self(), LWP_SIG_MASK_CMD_BLOCK, &new_sig, &old_sig); } - if ((maxevents > 0) && (epfd >=0)) + if ((maxevents > 0) && (epfd >= 0)) { df = fd_get(epfd); if (df && df->vnode) @@ -763,27 +955,87 @@ static int epoll_do_wait(int epfd, struct epoll_event *events, int maxevents, in return ret; } +/** + * @brief Creates an epoll instance. + * + * This function creates an epoll instance with the specified size. + * + * @param size Size of the epoll instance. + * + * @return Returns the file descriptor referring to the created epoll instance on success, or -1 on failure. + */ int epoll_create(int size) { return epoll_do_create(size); } +/** + * @brief Modifies an epoll instance. + * + * This function modifies the epoll instance referred to by 'epfd' according to the specified operation 'op', associated with the file descriptor 'fd', and the event structure 'event'. + * + * @param epfd File descriptor referring to the epoll instance. + * @param op Operation to perform (EPOLL_CTL_ADD, EPOLL_CTL_DEL, or EPOLL_CTL_MOD). + * @param fd File descriptor to associate with the epoll instance or remove from it. + * @param event Pointer to the event structure containing the events to modify. + * + * @return Returns 0 on success, or -1 on failure. + */ int epoll_ctl(int epfd, int op, int fd, struct epoll_event *event) { return epoll_do_ctl(epfd, op, fd, event); } +/** + * @brief Waits for events on an epoll instance. + * + * This function waits for events on the epoll instance referred to by 'epfd' within the given timeout. + * + * @param epfd File descriptor referring to the epoll instance. + * @param events Pointer to the array to store triggered events. + * @param maxevents Maximum number of events to store in the array. + * @param timeout Timeout value in milliseconds. + * + * @return Returns the number of triggered events on success, or -1 on failure. + */ int epoll_wait(int epfd, struct epoll_event *events, int maxevents, int timeout) { return epoll_do_wait(epfd, events, maxevents, timeout, RT_NULL); } +/** + * @brief Waits for events on an epoll instance, blocking signals. + * + * This function waits for events on the epoll instance referred to by 'epfd' within the given timeout, blocking signals based on the provided signal set 'ss'. + * + * @param epfd File descriptor referring to the epoll instance. + * @param events Pointer to the array to store triggered events. + * @param maxevents Maximum number of events to store in the array. + * @param timeout Timeout value in milliseconds. + * @param ss Pointer to the signal set indicating signals to block during the wait operation. + * + * @return Returns the number of triggered events on success, or -1 on failure. + */ int epoll_pwait(int epfd, struct epoll_event *events, int maxevents, int timeout, const sigset_t *ss) { return epoll_do_wait(epfd, events, maxevents, timeout, ss); } +/** + * @brief Waits for events on an epoll instance, blocking signals. + * + * This function waits for events on the epoll instance referred to by 'epfd' within the given timeout, blocking signals based on the provided signal set 'ss'. + * + * @param epfd File descriptor referring to the epoll instance. + * @param events Pointer to the array to store triggered events. + * @param maxevents Maximum number of events to store in the array. + * @param timeout Timeout value in milliseconds. + * @param ss Pointer to the signal set indicating signals to block during the wait operation. + * + * @return Returns the number of triggered events on success, or -1 on failure. + */ int epoll_pwait2(int epfd, struct epoll_event *events, int maxevents, int timeout, const sigset_t *ss) { return epoll_do_wait(epfd, events, maxevents, timeout, ss); } + diff --git a/components/libc/posix/io/eventfd/eventfd.c b/components/libc/posix/io/eventfd/eventfd.c index 81e3a830ae7..b42a9b01a0c 100644 --- a/components/libc/posix/io/eventfd/eventfd.c +++ b/components/libc/posix/io/eventfd/eventfd.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2023-07-20 zmq810150896 first version + * 2024-03-28 TroyMitchell Add comments for all functions */ #include @@ -58,6 +59,11 @@ static const struct dfs_file_ops eventfd_fops = .write = eventfd_write, }; +/** + * @brief Closes an event file descriptor. + * @param file Pointer to the file descriptor structure. + * @return 0 on success, otherwise an error code. + */ static int eventfd_close(struct dfs_file *file) { struct eventfd_ctx *ctx = file->vnode->data; @@ -71,6 +77,12 @@ static int eventfd_close(struct dfs_file *file) return 0; } +/** + * @brief Polls an event file descriptor for events. + * @param file Pointer to the file descriptor structure. + * @param req Pointer to the poll request structure. + * @return Events that occurred on the file descriptor. + */ static int eventfd_poll(struct dfs_file *file, struct rt_pollreq *req) { struct eventfd_ctx *ctx = (struct eventfd_ctx *)file->vnode->data; @@ -94,8 +106,23 @@ static int eventfd_poll(struct dfs_file *file, struct rt_pollreq *req) } #ifndef RT_USING_DFS_V2 +/** + * @brief Reads data from an event file descriptor. + * @param file Pointer to the file descriptor structure. + * @param buf Pointer to the buffer to read data into. + * @param count Maximum number of bytes to read. + * @return Number of bytes read on success, otherwise an error code. + */ static ssize_t eventfd_read(struct dfs_file *file, void *buf, size_t count) #else +/** + * @brief Reads data from an event file descriptor. + * @param file Pointer to the file descriptor structure. + * @param buf Pointer to the buffer to read data into. + * @param count Maximum number of bytes to read. + * @param pos Pointer to the file position (not used). + * @return Number of bytes read on success, otherwise an error code. + */ static ssize_t eventfd_read(struct dfs_file *file, void *buf, size_t count, off_t *pos) #endif { @@ -146,8 +173,23 @@ static ssize_t eventfd_read(struct dfs_file *file, void *buf, size_t count, off_ } #ifndef RT_USING_DFS_V2 +/** + * @brief Writes data to an event file descriptor. + * @param file Pointer to the file descriptor structure. + * @param buf Pointer to the buffer containing data to write. + * @param count Number of bytes to write. + * @return Number of bytes written on success, otherwise an error code. + */ static ssize_t eventfd_write(struct dfs_file *file, const void *buf, size_t count) #else +/** + * @brief Writes data to an event file descriptor. + * @param file Pointer to the file descriptor structure. + * @param buf Pointer to the buffer containing data to write. + * @param count Number of bytes to write. + * @param pos Pointer to the file position (not used). + * @return Number of bytes written on success, otherwise an error code. + */ static ssize_t eventfd_write(struct dfs_file *file, const void *buf, size_t count, off_t *pos) #endif { @@ -198,7 +240,13 @@ static ssize_t eventfd_write(struct dfs_file *file, const void *buf, size_t coun return ret; } - +/** + * @brief Creates an event file descriptor. + * @param df Pointer to the file descriptor structure. + * @param count Initial value of the event counter. + * @param flags Flags for the event file descriptor. + * @return 0 on success, otherwise an error code. + */ static int rt_eventfd_create(struct dfs_file *df, unsigned int count, int flags) { struct eventfd_ctx *ctx = RT_NULL; @@ -243,6 +291,12 @@ static int rt_eventfd_create(struct dfs_file *df, unsigned int count, int flags) return ret; } +/** + * @brief Internal function to create an event file descriptor. + * @param count Initial value of the event counter. + * @param flags Flags for the event file descriptor. + * @return File descriptor on success, otherwise an error code. + */ static int do_eventfd(unsigned int count, int flags) { struct dfs_file *file; @@ -279,6 +333,12 @@ static int do_eventfd(unsigned int count, int flags) return ret; } +/** + * @brief Creates an event file descriptor with the specified count and flags. + * @param count Initial value of the event counter. + * @param flags Flags for the event file descriptor. + * @return File descriptor on success, otherwise an error code. + */ int eventfd(unsigned int count, int flags) { return do_eventfd(count, flags); diff --git a/components/libc/posix/io/mman/mman.c b/components/libc/posix/io/mman/mman.c index 69a86d9bab2..68b906903c1 100644 --- a/components/libc/posix/io/mman/mman.c +++ b/components/libc/posix/io/mman/mman.c @@ -4,8 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2017/11/30 Bernard The first version. + * Date Author Notes + * 2017/11/30 Bernard The first version. + * 2024/03/29 TroyMitchelle Add all function comments */ #include @@ -20,6 +21,16 @@ #include "sys/mman.h" +/** + * @brief Maps a region of memory into the calling process's address space. + * @param addr Desired starting address of the mapping. + * @param length Length of the mapping. + * @param prot Protection of the mapped memory region. + * @param flags Type of the mapped memory region. + * @param fd File descriptor of the file to be mapped. + * @param offset Offset within the file to start the mapping. + * @return Upon success, returns a pointer to the mapped region; otherwise, MAP_FAILED is returned. + */ void *mmap(void *addr, size_t length, int prot, int flags, int fd, off_t offset) { @@ -59,6 +70,12 @@ void *mmap(void *addr, size_t length, int prot, int flags, return MAP_FAILED; } +/** + * @brief Unmaps a mapped region of memory. + * @param addr Starting address of the mapping to be unmapped. + * @param length Length of the mapping. + * @return Upon success, returns 0; otherwise, -1 is returned. + */ int munmap(void *addr, size_t length) { if (addr) diff --git a/components/libc/posix/io/mman/sys/mman.h b/components/libc/posix/io/mman/sys/mman.h index a730f33b6bd..0955975c650 100644 --- a/components/libc/posix/io/mman/sys/mman.h +++ b/components/libc/posix/io/mman/sys/mman.h @@ -4,8 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2017/11/30 Bernard The first version. + * Date Author Notes + * 2017/11/30 Bernard The first version. + * 2024/03/29 TroyMitchelle Add comments for all macros */ #ifndef __SYS_MMAN_H__ @@ -19,37 +20,42 @@ extern "C" { #define MAP_FAILED ((void *) -1) -#define MAP_SHARED 0x01 -#define MAP_PRIVATE 0x02 -#define MAP_TYPE 0x0f -#define MAP_FIXED 0x10 -#define MAP_ANON 0x20 -#define MAP_ANONYMOUS MAP_ANON -#define MAP_NORESERVE 0x4000 -#define MAP_GROWSDOWN 0x0100 -#define MAP_DENYWRITE 0x0800 -#define MAP_EXECUTABLE 0x1000 -#define MAP_LOCKED 0x2000 -#define MAP_POPULATE 0x8000 -#define MAP_NONBLOCK 0x10000 -#define MAP_STACK 0x20000 -#define MAP_HUGETLB 0x40000 -#define MAP_FILE 0 - -#define PROT_NONE 0 -#define PROT_READ 1 -#define PROT_WRITE 2 -#define PROT_EXEC 4 -#define PROT_GROWSDOWN 0x01000000 -#define PROT_GROWSUP 0x02000000 - -#define MS_ASYNC 1 -#define MS_INVALIDATE 2 -#define MS_SYNC 4 - -#define MCL_CURRENT 1 -#define MCL_FUTURE 2 -#define MCL_ONFAULT 4 +/* mmap flags */ +#define MAP_SHARED 0x01 /**< Share the mapping with other processes. */ +#define MAP_PRIVATE 0x02 /**< Create a private copy-on-write mapping. */ +#define MAP_TYPE 0x0f /**< Mask for type of mapping. */ +#define MAP_FIXED 0x10 /**< Interpret addr exactly. */ +#define MAP_ANON 0x20 /**< Anonymous mapping. */ +#define MAP_ANONYMOUS MAP_ANON /**< Synonym for MAP_ANON. */ +#define MAP_NORESERVE 0x4000 /**< Don't reserve swap space for this mapping. */ +#define MAP_GROWSDOWN 0x0100 /**< Stack-like segment. */ +#define MAP_DENYWRITE 0x0800 /**< ETXTBSY. */ +#define MAP_EXECUTABLE 0x1000 /**< Mark it as an executable. */ +#define MAP_LOCKED 0x2000 /**< Lock the mapping's pages. */ +#define MAP_POPULATE 0x8000 /**< Populate (prefault) pagetables. */ +#define MAP_NONBLOCK 0x10000 /**< Do not block on IO. */ +#define MAP_STACK 0x20000 /**< Allocation is a stack segment. */ +#define MAP_HUGETLB 0x40000 /**< Create a huge page mapping. */ +#define MAP_FILE 0 /**< Compatibility */ + +/* mmap protections */ +#define PROT_NONE 0 /**< No access. */ +#define PROT_READ 1 /**< Page can be read. */ +#define PROT_WRITE 2 /**< Page can be written. */ +#define PROT_EXEC 4 /**< Page can be executed. */ +#define PROT_GROWSDOWN 0x01000000/**< Extend change to start of growsdown vma (mprotect only). */ +#define PROT_GROWSUP 0x02000000/**< Extend change to start of growsup vma (mprotect only). */ + +/* msync flags */ +#define MS_ASYNC 1 /**< Perform asynchronous writes. */ +#define MS_INVALIDATE 2 /**< Invalidate mappings after writing. */ +#define MS_SYNC 4 /**< Perform synchronous writes. */ + +/* mlockall flags */ +#define MCL_CURRENT 1 /**< Lock all pages which are currently mapped into the address space of the process. */ +#define MCL_FUTURE 2 /**< Lock all pages which will become mapped into the address space of the process in the future. */ +#define MCL_ONFAULT 4 /**< Lock all pages which are currently mapped into the address space of the process on access. */ + void *mmap (void *start, size_t len, int prot, int flags, int fd, off_t off); int munmap (void *start, size_t len); diff --git a/components/libc/posix/io/poll/poll.c b/components/libc/posix/io/poll/poll.c index 105727e4b3d..7ab4a9bec13 100644 --- a/components/libc/posix/io/poll/poll.c +++ b/components/libc/posix/io/poll/poll.c @@ -4,9 +4,16 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2016-12-28 Bernard first version - * 2018-03-09 Bernard Add protection for pt->triggered. + * Date Author Notes + * 2016-12-28 Bernard first version + * 2018-03-09 Bernard Add protection for pt->triggered. + * 2023-12-04 Shell Fix return code and error verification + * 2023-12-14 Shell When poll goes to sleep before the waitqueue has added a + * record and finished enumerating all the fd's, it may be + * incorrectly woken up. This is basically because the poll + * mechanism wakeup algorithm does not correctly distinguish + * the current wait state. + * 2024-03-29 TroyMitchelle Add all function comments and comments to structure members */ #include @@ -15,38 +22,74 @@ #include #include "poll.h" -struct rt_poll_node; -struct rt_poll_table +enum rt_poll_status { - rt_pollreq_t req; - rt_uint32_t triggered; /* the waited thread whether triggered */ - rt_thread_t polling_thread; - struct rt_poll_node *nodes; + RT_POLL_STAT_INIT, /**< Poll operation initialization status. */ + RT_POLL_STAT_TRIG, /**< Poll operation triggered status. */ + RT_POLL_STAT_WAITING /**< Poll operation waiting status. */ }; -struct rt_poll_node + +struct rt_poll_table { - struct rt_wqueue_node wqn; - struct rt_poll_table *pt; - struct rt_poll_node *next; + rt_pollreq_t req; /**< Poll request. */ + enum rt_poll_status status; /**< Status of the poll operation. */ + rt_thread_t polling_thread; /**< Polling thread associated with the table. */ + struct rt_poll_node *nodes; /**< Linked list of poll nodes. */ +}; + + +struct rt_poll_node +{ + struct rt_wqueue_node wqn; /**< Wait queue node for the poll node. */ + struct rt_poll_table *pt; /**< Pointer to the parent poll table. */ + struct rt_poll_node *next; /**< Pointer to the next poll node. */ }; static RT_DEFINE_SPINLOCK(_spinlock); +/** + * @brief Wake-up function for the wait queue. + * + * This function is invoked when a node in the wait queue needs to be woken up. + * + * @param wait Pointer to the wait queue node. + * @param key Key associated with the wake-up operation. + * @return Upon successful wake-up, returns 0; otherwise, -1 is returned. + */ static int __wqueue_pollwake(struct rt_wqueue_node *wait, void *key) { + rt_ubase_t level; struct rt_poll_node *pn; + int is_waiting; if (key && !((rt_ubase_t)key & wait->key)) return -1; pn = rt_container_of(wait, struct rt_poll_node, wqn); - pn->pt->triggered = 1; - return __wqueue_default_wake(wait, key); + level = rt_spin_lock_irqsave(&_spinlock); + is_waiting = (pn->pt->status == RT_POLL_STAT_WAITING); + + pn->pt->status = RT_POLL_STAT_TRIG; + rt_spin_unlock_irqrestore(&_spinlock, level); + + if (is_waiting) + return __wqueue_default_wake(wait, key); + + return -1; } +/** + * @brief Adds a poll request to the wait queue. + * + * This function adds a poll request to the wait queue associated with the specified + * wait queue and poll request. + * + * @param wq Pointer to the wait queue. + * @param req Pointer to the poll request. + */ static void _poll_add(rt_wqueue_t *wq, rt_pollreq_t *req) { struct rt_poll_table *pt; @@ -68,14 +111,34 @@ static void _poll_add(rt_wqueue_t *wq, rt_pollreq_t *req) rt_wqueue_add(wq, &node->wqn); } +/** + * @brief Initializes a poll table. + * + * This function initializes a poll table with the provided poll request, status, + * and polling thread. + * + * @param pt Pointer to the poll table to be initialized. + */ static void poll_table_init(struct rt_poll_table *pt) { pt->req._proc = _poll_add; - pt->triggered = 0; + pt->status = RT_POLL_STAT_INIT; pt->nodes = RT_NULL; pt->polling_thread = rt_thread_self(); } +/** + * @brief Waits for events on the poll table with a specified timeout. + * + * This function waits for events on the poll table with the specified timeout + * in milliseconds. + * + * @param pt Pointer to the poll table. + * @param msec Timeout value in milliseconds. + * @return Upon successful completion, returns 0. If the timeout expires, -RT_ETIMEOUT + * is returned. If the operation is interrupted by a signal, -RT_EINTR is + * returned. + */ static int poll_wait_timeout(struct rt_poll_table *pt, int msec) { rt_int32_t timeout; @@ -89,7 +152,7 @@ static int poll_wait_timeout(struct rt_poll_table *pt, int msec) level = rt_spin_lock_irqsave(&_spinlock); - if (timeout != 0 && !pt->triggered) + if (timeout != 0 && pt->status != RT_POLL_STAT_TRIG) { if (rt_thread_suspend_with_flag(thread, RT_INTERRUPTIBLE) == RT_EOK) { @@ -99,22 +162,47 @@ static int poll_wait_timeout(struct rt_poll_table *pt, int msec) RT_TIMER_CTRL_SET_TIME, &timeout); rt_timer_start(&(thread->thread_timer)); + rt_set_errno(RT_ETIMEOUT); } - + else + { + rt_set_errno(0); + } + pt->status = RT_POLL_STAT_WAITING; rt_spin_unlock_irqrestore(&_spinlock, level); rt_schedule(); level = rt_spin_lock_irqsave(&_spinlock); + if (pt->status == RT_POLL_STAT_WAITING) + pt->status = RT_POLL_STAT_INIT; } } - ret = !pt->triggered; + ret = rt_get_errno(); + if (ret == RT_EINTR) + ret = -RT_EINTR; + else if (pt->status == RT_POLL_STAT_TRIG) + ret = RT_EOK; + else + ret = -RT_ETIMEOUT; + rt_spin_unlock_irqrestore(&_spinlock, level); return ret; } +/** + * @brief Performs poll operation for a single file descriptor. + * + * This function performs a poll operation for a single file descriptor and updates + * the revents field of the pollfd structure accordingly. + * + * @param pollfd Pointer to the pollfd structure. + * @param req Pointer to the poll request. + * @return Upon successful completion, returns the bitmask of events that occurred. + * If an error occurs, -1 is returned. + */ static int do_pollfd(struct pollfd *pollfd, rt_pollreq_t *req) { int mask = 0; @@ -152,6 +240,21 @@ static int do_pollfd(struct pollfd *pollfd, rt_pollreq_t *req) return mask; } +/** + * @brief Performs the poll operation on an array of file descriptors. + * + * This function performs the poll operation on an array of file descriptors and + * waits for events with the specified timeout. + * + * @param fds Pointer to the array of pollfd structures. + * @param nfds Number of file descriptors in the array. + * @param pt Pointer to the poll table. + * @param msec Timeout value in milliseconds. + * @return Upon successful completion, returns the number of file descriptors + * for which events were received. If the timeout expires, -RT_ETIMEOUT + * is returned. If the operation is interrupted by a signal, -RT_EINTR is + * returned. + */ static int poll_do(struct pollfd *fds, nfds_t nfds, struct rt_poll_table *pt, int msec) { int num; @@ -170,7 +273,7 @@ static int poll_do(struct pollfd *fds, nfds_t nfds, struct rt_poll_table *pt, in { pf = fds; num = 0; - pt->triggered = 0; + pt->status = RT_POLL_STAT_INIT; for (n = 0; n < nfds; n ++) { @@ -194,13 +297,26 @@ static int poll_do(struct pollfd *fds, nfds_t nfds, struct rt_poll_table *pt, in if (num || istimeout) break; - if (poll_wait_timeout(pt, msec)) + ret = poll_wait_timeout(pt, msec); + if (ret == -RT_EINTR) + return -EINTR; + else if (ret == -RT_ETIMEOUT) istimeout = 1; + else + istimeout = 0; } return num; } +/** + * @brief Tears down the poll table. + * + * This function tears down the poll table by removing all poll nodes associated + * with it. + * + * @param pt Pointer to the poll table. + */ static void poll_teardown(struct rt_poll_table *pt) { struct rt_poll_node *node, *next; @@ -215,6 +331,19 @@ static void poll_teardown(struct rt_poll_table *pt) } } +/** + * @brief Performs the poll operation on a set of file descriptors. + * + * This function performs the poll operation on a set of file descriptors and + * waits for events with the specified timeout. + * + * @param fds Pointer to the array of pollfd structures. + * @param nfds Number of file descriptors in the array. + * @param timeout Timeout value in milliseconds. + * @return Upon successful completion, returns the number of file descriptors + * for which events were received. If the timeout expires, 0 is returned. + * If an error occurs, -1 is returned. + */ int poll(struct pollfd *fds, nfds_t nfds, int timeout) { int num; diff --git a/components/libc/posix/io/poll/poll.h b/components/libc/posix/io/poll/poll.h index 7b710cd14e3..def526ff9d6 100644 --- a/components/libc/posix/io/poll/poll.h +++ b/components/libc/posix/io/poll/poll.h @@ -4,8 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2021-09-11 Meco Man First version + * Date Author Notes + * 2021-09-11 Meco Man First version + * 2024-03-29 TroyMitchelle Add all macro comments and comments to structure members */ #ifndef __POLL_H__ @@ -17,43 +18,43 @@ extern "C" { #ifdef RT_USING_MUSLLIBC #if !defined(POLLIN) && !defined(POLLOUT) -#define POLLIN 0x001 -#define POLLPRI 0x002 -#define POLLOUT 0x004 -#define POLLERR 0x008 -#define POLLHUP 0x010 -#define POLLNVAL 0x020 -#define POLLRDNORM 0x040 -#define POLLRDBAND 0x080 -#define POLLWRNORM 0x100 -#define POLLWRBAND 0x200 +#define POLLIN 0x001 /**< There is data to read. */ +#define POLLPRI 0x002 /**< There is urgent data to read. */ +#define POLLOUT 0x004 /**< Writing is now possible. */ +#define POLLERR 0x008 /**< Error condition. */ +#define POLLHUP 0x010 /**< Hang up. */ +#define POLLNVAL 0x020 /**< Invalid polling request. */ +#define POLLRDNORM 0x040 /**< Normal data may be read. */ +#define POLLRDBAND 0x080 /**< Priority data may be read. */ +#define POLLWRNORM 0x100 /**< Writing normal data is possible. */ +#define POLLWRBAND 0x200 /**< Writing priority data is possible. */ typedef unsigned int nfds_t; struct pollfd { - int fd; - short events; - short revents; + int fd; /**< File descriptor. */ + short events; /**< Requested events. */ + short revents; /**< Returned events. */ }; #endif #else #if !defined(POLLIN) && !defined(POLLOUT) -#define POLLIN 0x1 -#define POLLOUT 0x2 -#define POLLERR 0x4 -#define POLLNVAL 0x8 +#define POLLIN 0x1 /**< There is data to read. */ +#define POLLOUT 0x2 /**< Writing is now possible. */ +#define POLLERR 0x4 /**< Error condition. */ +#define POLLNVAL 0x8 /**< Invalid polling request. */ /* Below values are unimplemented */ -#define POLLRDNORM 0x10 -#define POLLRDBAND 0x20 -#define POLLPRI 0x40 -#define POLLWRNORM 0x80 -#define POLLWRBAND 0x100 -#define POLLHUP 0x200 +#define POLLRDNORM 0x10 /**< Normal data may be read. */ +#define POLLRDBAND 0x20 /**< Priority data may be read. */ +#define POLLPRI 0x40 /**< There is urgent data to read. */ +#define POLLWRNORM 0x80 /**< Writing normal data is possible. */ +#define POLLWRBAND 0x100 /**< Writing priority data is possible. */ +#define POLLHUP 0x200 /**< Hang up. */ typedef unsigned int nfds_t; struct pollfd { - int fd; - short events; - short revents; + int fd; /**< File descriptor. */ + short events; /**< Requested events. */ + short revents; /**< Returned events. */ }; #endif #endif /* !defined(POLLIN) && !defined(POLLOUT) */ diff --git a/components/libc/posix/io/poll/select.c b/components/libc/posix/io/poll/select.c index 864411f072a..a239a44a305 100644 --- a/components/libc/posix/io/poll/select.c +++ b/components/libc/posix/io/poll/select.c @@ -4,14 +4,21 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2016-12-28 Bernard first version + * Date Author Notes + * 2016-12-28 Bernard first version + * 2024-04-08 TroyMitchell Add all function comments */ #include #include #include +/** + * @brief Initialize the file descriptor set to have zero bits for all file descriptors. + * @param set Pointer to the file descriptor set to be initialized. + * @param nfds The maximum file descriptor in the set plus one. + * @note The actual size of the 'fd_set' is determined based on the parameter 'nfds'. + */ static void fdszero(fd_set *set, int nfds) { fd_mask *m; @@ -29,6 +36,15 @@ static void fdszero(fd_set *set, int nfds) } } +/** + * @brief Synchronous I/O multiplexing: multiplex input/output over a set of file descriptors. + * @param nfds The highest-numbered file descriptor in any of the three sets, plus 1. + * @param readfds A pointer to a set of file descriptors to be checked for read readiness. + * @param writefds A pointer to a set of file descriptors to be checked for write readiness. + * @param exceptfds A pointer to a set of file descriptors to be checked for exceptions. + * @param timeout The maximum time to wait for any of the specified file descriptors to become ready. + * @return Upon successful completion, the total number of file descriptors in all the sets that are ready for the requested operation is returned; otherwise, -1 is returned on error. + */ int select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, struct timeval *timeout) { int fd; diff --git a/components/libc/posix/io/signalfd/signalfd.c b/components/libc/posix/io/signalfd/signalfd.c index 735740fafc9..b4a08fa9467 100644 --- a/components/libc/posix/io/signalfd/signalfd.c +++ b/components/libc/posix/io/signalfd/signalfd.c @@ -4,8 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2023-08-29 zmq810150896 first version + * Date Author Notes + * 2023-08-29 zmq810150896 first version + * 2024-04-08 TroyMitchell Add all function comments */ #include @@ -50,6 +51,11 @@ static const struct dfs_file_ops signalfd_fops = .read = signalfd_read, }; +/** + * @brief Closes the file descriptor associated with a signalfd file. + * @param file Pointer to the file structure. + * @return Upon successful completion, returns 0; otherwise, returns an error code. + */ static int signalfd_close(struct dfs_file *file) { struct rt_signalfd_ctx *sfd; @@ -68,6 +74,12 @@ static int signalfd_close(struct dfs_file *file) return 0; } +/** + * @brief Adds a signalfd file descriptor to the poll queue and checks for pending events. + * @param file Pointer to the file structure. + * @param req Pointer to the poll request structure. + * @return The events that are ready on the file descriptor. + */ static int signalfd_poll(struct dfs_file *file, struct rt_pollreq *req) { struct rt_signalfd_ctx *sfd; @@ -92,8 +104,23 @@ static int signalfd_poll(struct dfs_file *file, struct rt_pollreq *req) } #ifndef RT_USING_DFS_V2 +/** + * @brief Reads signals from a signalfd file descriptor. + * @param file Pointer to the file structure. + * @param buf Pointer to the buffer to store the signals. + * @param count Maximum number of bytes to read. + * @return Upon successful completion, returns the number of bytes read; otherwise, returns an error code. + */ static ssize_t signalfd_read(struct dfs_file *file, void *buf, size_t count) #else +/** + * @brief Reads signals from a signalfd file descriptor with file offset. + * @param file Pointer to the file structure. + * @param buf Pointer to the buffer to store the signals. + * @param count Maximum number of bytes to read. + * @param pos Pointer to the file offset. + * @return Upon successful completion, returns the number of bytes read; otherwise, returns an negative error code. + */ static ssize_t signalfd_read(struct dfs_file *file, void *buf, size_t count, off_t *pos) #endif { @@ -158,6 +185,11 @@ static ssize_t signalfd_read(struct dfs_file *file, void *buf, size_t count, off return ret; } +/** + * @brief Callback function for signalfd file descriptor notifications. + * @param signalfd_queue Pointer to the signalfd queue. + * @param signum Signal number. + */ static void signalfd_callback(rt_wqueue_t *signalfd_queue, int signum) { struct rt_signalfd_ctx *sfd; @@ -180,6 +212,11 @@ static void signalfd_callback(rt_wqueue_t *signalfd_queue, int signum) } } +/** + * @brief Adds a signal file descriptor notification. + * @param sfd Pointer to the signalfd context. + * @return Upon successful completion, returns 0; otherwise, returns an error code. + */ static int signalfd_add_notify(struct rt_signalfd_ctx *sfd) { struct rt_lwp_notify *lwp_notify; @@ -236,6 +273,13 @@ static int signalfd_add_notify(struct rt_signalfd_ctx *sfd) return ret; } +/** + * @brief Creates a new signalfd file descriptor or modifies an existing one. + * @param fd File descriptor to modify (-1 to create a new one). + * @param mask Signal mask. + * @param flags File descriptor flags. + * @return Upon successful completion, returns the file descriptor number; otherwise, returns an error code. + */ static int signalfd_do(int fd, const sigset_t *mask, int flags) { struct dfs_file *df; @@ -328,6 +372,13 @@ static int signalfd_do(int fd, const sigset_t *mask, int flags) return ret; } +/** + * @brief Creates a new signalfd file descriptor or modifies an existing one. + * @param fd File descriptor to modify (-1 to create a new one). + * @param mask Signal mask. + * @param flags File descriptor flags. + * @return Upon successful completion, returns the file descriptor number; otherwise, returns an error code. + */ int signalfd(int fd, const sigset_t *mask, int flags) { return signalfd_do(fd, mask, flags); diff --git a/components/libc/posix/io/termios/termios.h b/components/libc/posix/io/termios/termios.h index 4a504daa7d7..884159ae2e2 100644 --- a/components/libc/posix/io/termios/termios.h +++ b/components/libc/posix/io/termios/termios.h @@ -36,6 +36,20 @@ struct termios { speed_t __c_ospeed; }; +#ifndef NCC +#define NCC 8 + +struct termio +{ + unsigned short c_iflag; /* input mode flags */ + unsigned short c_oflag; /* output mode flags */ + unsigned short c_cflag; /* control mode flags */ + unsigned short c_lflag; /* local mode flags */ + unsigned char c_line; /* line discipline */ + unsigned char c_cc[NCC]; /* control characters */ +}; +#endif + /* c_cc characters */ #define VINTR 0 #define VQUIT 1 diff --git a/components/libc/posix/pthreads/pthread_tls.c b/components/libc/posix/pthreads/pthread_tls.c index 041318666cb..2e709acb601 100644 --- a/components/libc/posix/pthreads/pthread_tls.c +++ b/components/libc/posix/pthreads/pthread_tls.c @@ -28,7 +28,7 @@ void *pthread_getspecific(pthread_key_t key) if (rt_thread_self() == NULL) return NULL; /* get pthread data from user data of thread */ - ptd = (_pthread_data_t *)rt_thread_self()->user_data; + ptd = (_pthread_data_t *)rt_thread_self()->pthread_data; RT_ASSERT(ptd != NULL); if (ptd->tls == NULL) @@ -48,7 +48,7 @@ int pthread_setspecific(pthread_key_t key, const void *value) if (rt_thread_self() == NULL) return EINVAL; /* get pthread data from user data of thread */ - ptd = (_pthread_data_t *)rt_thread_self()->user_data; + ptd = (_pthread_data_t *)rt_thread_self()->pthread_data; RT_ASSERT(ptd != NULL); /* check tls area */ diff --git a/components/libc/posix/signal/posix_signal.c b/components/libc/posix/signal/posix_signal.c index 00d925ea575..780d872faf4 100644 --- a/components/libc/posix/signal/posix_signal.c +++ b/components/libc/posix/signal/posix_signal.c @@ -229,6 +229,16 @@ int raise(int sig) } #include +/** + * @brief Sends a signal to the caller. + * + * This function sends the signal specified by @p sig to the caller. + * + * @param sig The signal to be sent. + * This should be one of the standard signal macros such as SIGUSR1, SIGUSR2, etc. + * + * @return Returns 0 on success. If an error occurs, -1 is returned and errno is set appropriately. + */ int sigqueue (pid_t pid, int signo, const union sigval value) { /* no support, signal queue */ diff --git a/components/libc/posix/signal/posix_signal.h b/components/libc/posix/signal/posix_signal.h index f04b54c5f80..deb0cc6dc51 100644 --- a/components/libc/posix/signal/posix_signal.h +++ b/components/libc/posix/signal/posix_signal.h @@ -18,40 +18,40 @@ extern "C" { #include enum rt_signal_value{ - SIG1 = SIGHUP, - SIG2 = SIGINT, - SIG3 = SIGQUIT, - SIG4 = SIGILL, - SIG5 = SIGTRAP, - SIG6 = SIGABRT, - SIG7 = SIGEMT, - SIG8 = SIGFPE, - SIG9 = SIGKILL, - SIG10 = SIGBUS, - SIG11 = SIGSEGV, - SIG12 = SIGSYS, - SIG13 = SIGPIPE, - SIG14 = SIGALRM, - SIG15 = SIGTERM, - SIG16 = SIGURG, - SIG17 = SIGSTOP, - SIG18 = SIGTSTP, - SIG19 = SIGCONT, - SIG20 = SIGCHLD, - SIG21 = SIGTTIN, - SIG22 = SIGTTOU, - SIG23 = SIGPOLL, - SIG24 = 24, // SIGXCPU, - SIG25 = 25, // SIGXFSZ, - SIG26 = 26, // SIGVTALRM, - SIG27 = 27, // SIGPROF, - SIG28 = SIGWINCH, - SIG29 = 29, // SIGLOST, - SIG30 = SIGUSR1, - SIG31 = SIGUSR2, - SIGRT_MIN = 27, // SIGRTMIN, - SIGRT_MAX = 31, // SIGRTMAX, - SIGMAX = NSIG, + SIG1 = SIGHUP, // Hangup detected on controlling terminal or death of controlling process + SIG2 = SIGINT, // Interrupt from keyboard + SIG3 = SIGQUIT, // Quit from keyboard + SIG4 = SIGILL, // Illegal instruction + SIG5 = SIGTRAP, // Trace trap + SIG6 = SIGABRT, // Abort signal from abort(3) + SIG7 = SIGEMT, // Emulator trap + SIG8 = SIGFPE, // Floating-point exception + SIG9 = SIGKILL, // Kill signal + SIG10 = SIGBUS, // Bus error + SIG11 = SIGSEGV, // Segmentation fault + SIG12 = SIGSYS, // Bad system call + SIG13 = SIGPIPE, // Broken pipe + SIG14 = SIGALRM, // Timer signal from alarm(2) + SIG15 = SIGTERM, // Termination signal + SIG16 = SIGURG, // Urgent condition on socket + SIG17 = SIGSTOP, // Stop executing (cannot be caught or ignored) + SIG18 = SIGTSTP, // Stop signal from keyboard to suspend execution + SIG19 = SIGCONT, // Continue if stopped + SIG20 = SIGCHLD, // Child status has changed + SIG21 = SIGTTIN, // Background read from control terminal attempted by background process + SIG22 = SIGTTOU, // Background write to control terminal attempted by background process + SIG23 = SIGPOLL, // Pollable event + SIG24 = 24, // SIGXCPU: CPU time limit exceeded + SIG25 = 25, // SIGXFSZ: File size limit exceeded + SIG26 = 26, // SIGVTALRM: Virtual timer expired + SIG27 = 27, // SIGPROF: Profiling timer expired + SIG28 = SIGWINCH,// Window size changed + SIG29 = 29, // SIGLOST + SIG30 = SIGUSR1, // User-defined signal 1 + SIG31 = SIGUSR2, // User-defined signal 2 + SIGRT_MIN = 27, // SIGRTMIN: Minimum real-time signal number + SIGRT_MAX = 31, // SIGRTMAX: Maximum real-time signal number + SIGMAX = NSIG // Number of signals (total) }; #ifdef __cplusplus diff --git a/components/lwp/Kconfig b/components/lwp/Kconfig index 719e8ffca42..16b23c4dd70 100644 --- a/components/lwp/Kconfig +++ b/components/lwp/Kconfig @@ -6,9 +6,16 @@ menuconfig RT_USING_LWP The lwP is a light weight process running in user mode. if RT_USING_LWP - config LWP_DEBUG + menuconfig LWP_DEBUG bool "Enable debugging features of LwP" + default y + + if LWP_DEBUG + config LWP_DEBUG_INIT + select RT_USING_HOOKLIST + bool "Enable debug mode of init process" default n + endif config RT_LWP_MAX_NR int "The max number of light-weight process" @@ -51,24 +58,6 @@ if RT_USING_LWP default y endif - config LWP_UNIX98_PTY - bool "The unix98 PTY support" - default n - - if LWP_UNIX98_PTY - config LWP_PTY_INPUT_BFSZ - int "The unix98 PTY input buffer size" - default 1024 - - config LWP_PTY_PTS_SIZE - int "The unix98 PTY device max num" - default 3 - - config LWP_PTY_USING_DEBUG - bool "The unix98 PTY debug output" - default n - endif - menuconfig RT_USING_LDSO bool "LDSO: dynamic load shared objects" depends on RT_USING_DFS_V2 @@ -85,5 +74,6 @@ if RT_USING_LWP default n endif +source "$RTT_DIR/components/lwp/terminal/Kconfig" endif diff --git a/components/lwp/SConscript b/components/lwp/SConscript index 3c43dcd86e7..5f4a618d480 100644 --- a/components/lwp/SConscript +++ b/components/lwp/SConscript @@ -22,11 +22,6 @@ if arch == 'risc-v': if cpu in rv64: cpu = 'rv64' -if GetDepend('LWP_UNIX98_PTY'): - # print("LWP_UNIX98_PTY") - src += Glob('unix98pty/*.c') - CPPPATH += ['unix98pty/'] - if platform in platform_file.keys(): # support platforms if arch in support_arch.keys() and cpu in support_arch[arch]: asm_path = 'arch/' + arch + '/' + cpu + '/*_' + platform_file[platform] @@ -40,6 +35,12 @@ if platform in platform_file.keys(): # support platforms CPPPATH = [cwd] CPPPATH += [cwd + '/arch/' + arch + '/' + cpu] +# Terminal I/O Subsystem +termios_path = ['./terminal/', './terminal/freebsd/'] +for item in termios_path: + src += Glob(item + '*.c') +CPPPATH += ['./terminal/'] + group = DefineGroup('lwP', src, depend = ['RT_USING_SMART'], CPPPATH = CPPPATH) Return('group') diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_arch.c b/components/lwp/arch/aarch64/cortex-a/lwp_arch.c index b9f9ec58dd1..3df6b2f4f7d 100644 --- a/components/lwp/arch/aarch64/cortex-a/lwp_arch.c +++ b/components/lwp/arch/aarch64/cortex-a/lwp_arch.c @@ -8,6 +8,7 @@ * 2021-05-18 Jesven first version * 2023-07-16 Shell Move part of the codes to C from asm in signal handling * 2023-10-16 Shell Support a new backtrace framework + * 2023-08-03 Shell Support of syscall restart (SA_RESTART) */ #include @@ -123,6 +124,7 @@ int arch_set_thread_context(void (*exit)(void), void *new_thread_stack, #define ALGIN_BYTES (16) +/* the layout is part of ABI, dont change it */ struct signal_ucontext { rt_int64_t sigreturn; @@ -130,11 +132,62 @@ struct signal_ucontext siginfo_t si; - rt_align(16) + rt_align(ALGIN_BYTES) struct rt_hw_exp_stack frame; }; -void *arch_signal_ucontext_restore(rt_base_t user_sp) +RT_STATIC_ASSERT(abi_offset_compatible, offsetof(struct signal_ucontext, si) == UCTX_ABI_OFFSET_TO_SI); + +void *arch_signal_ucontext_get_frame(struct signal_ucontext *uctx) +{ + return &uctx->frame; +} + +/* internal used only */ +void arch_syscall_prepare_signal(rt_base_t rc, struct rt_hw_exp_stack *exp_frame) +{ + long x0 = exp_frame->x0; + exp_frame->x0 = rc; + exp_frame->x7 = x0; + return ; +} + +void arch_syscall_restart(void *sp, void *ksp); + +void arch_syscall_set_errno(void *eframe, int expected, int code) +{ + struct rt_hw_exp_stack *exp_frame = eframe; + if (exp_frame->x0 == -expected) + exp_frame->x0 = -code; + return ; +} + +void arch_signal_check_erestart(void *eframe, void *ksp) +{ + struct rt_hw_exp_stack *exp_frame = eframe; + long rc = exp_frame->x0; + long sys_id = exp_frame->x8; + (void)sys_id; + + if (rc == -ERESTART) + { + LOG_D("%s(rc=%ld,sys_id=%ld,pid=%d)", __func__, rc, sys_id, lwp_self()->pid); + LOG_D("%s: restart rc = %ld", lwp_get_syscall_name(sys_id), rc); + exp_frame->x0 = exp_frame->x7; + arch_syscall_restart(eframe, ksp); + } + + return ; +} + +static void arch_signal_post_action(struct signal_ucontext *new_sp, rt_base_t kernel_sp) +{ + arch_signal_check_erestart(&new_sp->frame, (void *)kernel_sp); + + return ; +} + +void *arch_signal_ucontext_restore(rt_base_t user_sp, rt_base_t kernel_sp) { struct signal_ucontext *new_sp; new_sp = (void *)user_sp; @@ -142,6 +195,7 @@ void *arch_signal_ucontext_restore(rt_base_t user_sp) if (lwp_user_accessable(new_sp, sizeof(*new_sp))) { lwp_thread_signal_mask(rt_thread_self(), LWP_SIG_MASK_CMD_SET_MASK, &new_sp->save_sigmask, RT_NULL); + arch_signal_post_action(new_sp, kernel_sp); } else { @@ -157,7 +211,7 @@ void *arch_signal_ucontext_save(rt_base_t user_sp, siginfo_t *psiginfo, lwp_sigset_t *save_sig_mask) { struct signal_ucontext *new_sp; - new_sp = (void *)(user_sp - sizeof(struct signal_ucontext)); + new_sp = (void *)((user_sp - sizeof(struct signal_ucontext)) & ~0xf); if (lwp_user_accessable(new_sp, sizeof(*new_sp))) { diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_arch.h b/components/lwp/arch/aarch64/cortex-a/lwp_arch.h index c7d9c8d74ec..191f8e1bdc5 100644 --- a/components/lwp/arch/aarch64/cortex-a/lwp_arch.h +++ b/components/lwp/arch/aarch64/cortex-a/lwp_arch.h @@ -11,8 +11,7 @@ #ifndef LWP_ARCH_H__ #define LWP_ARCH_H__ -#include -#include +#include #ifdef ARCH_MM_MMU @@ -26,6 +25,13 @@ #define USER_VADDR_START 0x00200000UL #define USER_LOAD_VADDR USER_VADDR_START +#define UCTX_ABI_OFFSET_TO_SI 16 + +#ifndef __ASSEMBLY__ + +#include +#include + #ifdef __cplusplus extern "C" { #endif @@ -34,7 +40,7 @@ unsigned long rt_hw_ffz(unsigned long x); rt_inline void icache_invalid_all(void) { - asm volatile ("ic ialluis\n\tisb sy":::"memory"); + __asm__ volatile ("ic ialluis\n\tisb sy":::"memory"); } /** @@ -57,11 +63,14 @@ void *arch_signal_ucontext_save(rt_base_t user_sp, siginfo_t *psiginfo, * @param user_sp sp of user * @return void* */ -void *arch_signal_ucontext_restore(rt_base_t user_sp); +void *arch_signal_ucontext_restore(rt_base_t user_sp, rt_base_t kernel_sp); +void arch_syscall_restart(void *sp, void *ksp); + #ifdef __cplusplus } #endif +#endif /* __ASSEMBLY__ */ -#endif +#endif /* ARCH_MM_MMU */ #endif /*LWP_ARCH_H__*/ diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S b/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S index e33127b62bc..f5a93698d9a 100644 --- a/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S +++ b/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S @@ -7,6 +7,7 @@ * Date Author Notes * 2021-05-18 Jesven first version * 2023-07-16 Shell Move part of the codes to C from asm in signal handling + * 2023-08-03 Shell Support of syscall restart (SA_RESTART) */ #ifndef __ASSEMBLY__ @@ -17,6 +18,7 @@ #include "asm-generic.h" #include "asm-fpu.h" #include "armv8.h" +#include "lwp_arch.h" /********************* * SPSR BIT * @@ -155,6 +157,14 @@ START_POINT_END(SVC_Handler) .global arch_syscall_exit arch_syscall_exit: + + /** + * @brief back up former x0 which is required to restart syscall, then setup + * syscall return value in stack frame + */ + mov x1, sp + bl arch_syscall_prepare_signal + msr daifset, #3 ldp x2, x3, [sp], #0x10 /* SPSR and ELR. */ @@ -177,7 +187,10 @@ arch_syscall_exit: ldp x12, x13, [sp], #0x10 ldp x10, x11, [sp], #0x10 ldp x8, x9, [sp], #0x10 - add sp, sp, #0x40 + ldp x6, x7, [sp], #0x10 + ldp x4, x5, [sp], #0x10 + ldp x2, x3, [sp], #0x10 + ldp x0, x1, [sp], #0x10 RESTORE_FPU sp /* the sp is reset to the outer most level, irq and fiq are disabled */ @@ -383,10 +396,53 @@ lwp_check_debug_quit: ldp x29, x30, [sp], #0x10 ret +.global arch_syscall_restart +arch_syscall_restart: + msr daifset, 3 + + mov sp, x1 + /* drop exception frame in user stack */ + msr sp_el0, x0 + + /* restore previous exception frame */ + msr spsel, #0 + + ldp x2, x3, [sp], #0x10 + msr elr_el1, x2 + msr spsr_el1, x3 + + ldp x29, x30, [sp], #0x10 + + ldp x28, x29, [sp], #0x10 + msr fpcr, x28 + msr fpsr, x29 + + ldp x28, x29, [sp], #0x10 + ldp x26, x27, [sp], #0x10 + ldp x24, x25, [sp], #0x10 + ldp x22, x23, [sp], #0x10 + ldp x20, x21, [sp], #0x10 + ldp x18, x19, [sp], #0x10 + ldp x16, x17, [sp], #0x10 + ldp x14, x15, [sp], #0x10 + ldp x12, x13, [sp], #0x10 + ldp x10, x11, [sp], #0x10 + ldp x8, x9, [sp], #0x10 + ldp x6, x7, [sp], #0x10 + ldp x4, x5, [sp], #0x10 + ldp x2, x3, [sp], #0x10 + ldp x0, x1, [sp], #0x10 + RESTORE_FPU sp + + msr spsel, #1 + + b vector_exception + arch_signal_quit: /* drop current exception frame */ add sp, sp, #CONTEXT_SIZE + mov x1, sp mrs x0, sp_el0 bl arch_signal_ucontext_restore add x0, x0, #-CONTEXT_SIZE @@ -456,6 +512,11 @@ arch_thread_signal_enter: /* arch_signal_ucontext_save(user_sp, psiginfo, exp_frame, save_sig_mask); */ bl arch_signal_ucontext_save + mov x22, x0 + /* get and saved pointer to uframe */ + bl arch_signal_ucontext_get_frame + mov x2, x0 + mov x0, x22 dc cvau, x0 dsb sy @@ -483,12 +544,15 @@ arch_thread_signal_enter: /** set the return address to the sigreturn */ mov x30, x0 + cbnz x21, 1f + mov x21, x30 +1: /** set the entry address of signal handler */ msr elr_el1, x21 /* siginfo is above the return address */ - add x2, x30, 16 - add x1, x2, #CONTEXT_SIZE + add x1, x30, UCTX_ABI_OFFSET_TO_SI + /* uframe is saved in x2 */ mov x0, x19 /** diff --git a/components/lwp/arch/arm/cortex-a/lwp_arch.c b/components/lwp/arch/arm/cortex-a/lwp_arch.c index 0d8f9654294..0582ea70b7b 100644 --- a/components/lwp/arch/arm/cortex-a/lwp_arch.c +++ b/components/lwp/arch/arm/cortex-a/lwp_arch.c @@ -192,6 +192,12 @@ void *arch_signal_ucontext_save(rt_base_t lr, siginfo_t *psiginfo, return new_sp; } +void arch_syscall_set_errno(void *eframe, int expected, int code) +{ + /* NO support */ + return ; +} + #ifdef LWP_ENABLE_ASID #define MAX_ASID_BITS 8 #define MAX_ASID (1 << MAX_ASID_BITS) diff --git a/components/lwp/arch/arm/cortex-a/lwp_arch.h b/components/lwp/arch/arm/cortex-a/lwp_arch.h index 7262f446c84..6f5518e4c49 100644 --- a/components/lwp/arch/arm/cortex-a/lwp_arch.h +++ b/components/lwp/arch/arm/cortex-a/lwp_arch.h @@ -35,7 +35,7 @@ rt_inline unsigned long rt_hw_ffz(unsigned long x) rt_inline void icache_invalid_all(void) { - asm volatile ("mcr p15, 0, r0, c7, c5, 0\ndsb\nisb":::"memory");//iciallu + __asm__ volatile ("mcr p15, 0, r0, c7, c5, 0\ndsb\nisb":::"memory");//iciallu } unsigned int arch_get_asid(struct rt_lwp *lwp); diff --git a/components/lwp/arch/risc-v/rv64/lwp_arch.c b/components/lwp/arch/risc-v/rv64/lwp_arch.c index 4b3dfc2e194..62383f91fa9 100644 --- a/components/lwp/arch/risc-v/rv64/lwp_arch.c +++ b/components/lwp/arch/risc-v/rv64/lwp_arch.c @@ -242,6 +242,7 @@ int arch_set_thread_context(void (*exit)(void), void *new_thread_stack, * | | * +------------------------+ --> thread sp */ + return 0; } #define ALGIN_BYTES (16) @@ -317,6 +318,12 @@ void *arch_signal_ucontext_save(int signo, siginfo_t *psiginfo, return new_sp; } +void arch_syscall_set_errno(void *eframe, int expected, int code) +{ + /* NO support */ + return ; +} + /** * void lwp_exec_user(void *args, void *kernel_stack, void *user_entry) */ diff --git a/components/lwp/libc_musl.h b/components/lwp/libc_musl.h index 3129a0a6b70..fbc2ad5cb41 100644 --- a/components/lwp/libc_musl.h +++ b/components/lwp/libc_musl.h @@ -28,9 +28,9 @@ #define FUTEX_CLOCK_REALTIME 256 -#define FUTEX_WAITERS 0x80000000 -#define FUTEX_OWNER_DIED 0x40000000 -#define FUTEX_TID_MASK 0x3fffffff +#define FUTEX_WAITERS 0x80000000 +#define FUTEX_OWNER_DIED 0x40000000 +#define FUTEX_TID_MASK 0x3fffffff struct robust_list { diff --git a/components/lwp/lwp.c b/components/lwp/lwp.c index 7e85aaff9ea..87629cc890c 100644 --- a/components/lwp/lwp.c +++ b/components/lwp/lwp.c @@ -12,6 +12,8 @@ * 2023-02-20 wangxiaoyao inv icache before new app startup * 2023-02-20 wangxiaoyao fix bug on foreground app switch * 2023-10-16 Shell Support a new backtrace framework + * 2023-11-17 xqyjlj add process group and session support + * 2023-11-30 Shell add lwp_startup() */ #define DBG_TAG "lwp" @@ -39,7 +41,7 @@ #include "lwp_arch_comm.h" #include "lwp_signal.h" #include "lwp_dbg.h" -#include "console.h" +#include #ifdef ARCH_MM_MMU #include @@ -59,16 +61,31 @@ static const char elf_magic[] = {0x7f, 'E', 'L', 'F'}; #ifdef DFS_USING_WORKDIR extern char working_directory[]; #endif -static struct termios stdin_termios, old_stdin_termios; -int load_ldso(struct rt_lwp *lwp, char *exec_name, char *const argv[], char *const envp[]); - -struct termios *get_old_termios(void) +/** + * @brief The default console is only a backup device with lowest priority. + * It's always recommended to scratch the console from the boot arguments. + * And dont forget to register the device with a higher priority. + */ +static rt_err_t lwp_default_console_setup(void) { - return &old_stdin_termios; + rt_device_t bakdev = rt_device_find("ttyS0"); + rt_err_t rc; + + if (bakdev) + { + lwp_console_register_backend(bakdev, LWP_CONSOLE_LOWEST_PRIOR); + rc = RT_EOK; + } + else + { + rc = -RT_EINVAL; + } + + return rc; } -int lwp_component_init(void) +static int lwp_component_init(void) { int rc; if ((rc = lwp_tid_init()) != RT_EOK) @@ -83,10 +100,99 @@ int lwp_component_init(void) { LOG_E("%s: rt_channel_component_init failed", __func__); } + else if ((rc = lwp_futex_init()) != RT_EOK) + { + LOG_E("%s: lwp_futex_init() failed", __func__); + } + else if ((rc = lwp_default_console_setup()) != RT_EOK) + { + LOG_E("%s: lwp_default_console_setup() failed", __func__); + } return rc; } INIT_COMPONENT_EXPORT(lwp_component_init); +rt_weak int lwp_startup_debug_request(void) +{ + return 0; +} + +#define LATENCY_TIMES (3) +#define LATENCY_IN_MSEC (128) +#define LWP_CONSOLE_PATH "CONSOLE=/dev/console" +const char *init_search_path[] = { + "/sbin/init", + "/bin/init", +}; + +/** + * Startup process 0 and do the essential works + * This is the "Hello World" point of RT-Smart + */ +static int lwp_startup(void) +{ + int error; + + const char *init_path; + char *argv[] = {0, "&"}; + char *envp[] = {LWP_CONSOLE_PATH, 0}; + +#ifdef LWP_DEBUG_INIT + int command; + int countdown = LATENCY_TIMES; + while (countdown) + { + command = lwp_startup_debug_request(); + if (command) + { + return 0; + } + rt_kprintf("Press any key to stop init process startup ... %d\n", countdown); + countdown -= 1; + rt_thread_mdelay(LATENCY_IN_MSEC); + } + rt_kprintf("Starting init ...\n"); +#endif /* LWP_DEBUG_INIT */ + + for (size_t i = 0; i < sizeof(init_search_path)/sizeof(init_search_path[0]); i++) + { + struct stat s; + init_path = init_search_path[i]; + error = stat(init_path, &s); + if (error == 0) + { + argv[0] = (void *)init_path; + error = lwp_execve((void *)init_path, 0, sizeof(argv)/sizeof(argv[0]), argv, envp); + if (error < 0) + { + LOG_E("%s: failed to startup process 0 (init)\n" + "Switching to legacy mode...", __func__); + } + else if (error != 1) + { + LOG_E("%s: pid 1 is already allocated", __func__); + error = -EBUSY; + } + else + { + rt_lwp_t p = lwp_from_pid_locked(1); + p->sig_protected = 1; + + error = 0; + } + break; + } + } + + if (error) + { + LOG_D("%s: init program not found\n" + "Switching to legacy mode...", __func__); + } + return error; +} +INIT_APP_EXPORT(lwp_startup); + void lwp_setcwd(char *buf) { struct rt_lwp *lwp = RT_NULL; @@ -100,11 +206,11 @@ void lwp_setcwd(char *buf) lwp = (struct rt_lwp *)rt_thread_self()->lwp; if (lwp) { - rt_strncpy(lwp->working_directory, buf, DFS_PATH_MAX); + rt_strncpy(lwp->working_directory, buf, DFS_PATH_MAX - 1); } else { - rt_strncpy(working_directory, buf, DFS_PATH_MAX); + rt_strncpy(working_directory, buf, DFS_PATH_MAX - 1); } return ; @@ -114,8 +220,13 @@ char *lwp_getcwd(void) { char *dir_buf = RT_NULL; struct rt_lwp *lwp = RT_NULL; + rt_thread_t thread = rt_thread_self(); + + if (thread) + { + lwp = (struct rt_lwp *)thread->lwp; + } - lwp = (struct rt_lwp *)rt_thread_self()->lwp; if (lwp) { if(lwp->working_directory[0] != '/') @@ -1077,25 +1188,35 @@ void lwp_cleanup(struct rt_thread *tid) return; } -static void lwp_copy_stdio_fdt(struct rt_lwp *lwp) +static void lwp_execve_setup_stdio(struct rt_lwp *lwp) { - struct dfs_file *d; struct dfs_fdtable *lwp_fdt; + struct dfs_file *cons_file; + int cons_fd; lwp_fdt = &lwp->fdt; + + /* open console */ + cons_fd = open("/dev/console", O_RDWR); + if (cons_fd < 0) + { + LOG_E("%s: Cannot open console tty", __func__); + return ; + } + LOG_D("%s: open console as fd %d", __func__, cons_fd); + /* init 4 fds */ lwp_fdt->fds = rt_calloc(4, sizeof(void *)); if (lwp_fdt->fds) { + cons_file = fd_get(cons_fd); lwp_fdt->maxfd = 4; - d = fd_get(0); - fdt_fd_associate_file(lwp_fdt, 0, d); - d = fd_get(1); - fdt_fd_associate_file(lwp_fdt, 1, d); - d = fd_get(2); - fdt_fd_associate_file(lwp_fdt, 2, d); + fdt_fd_associate_file(lwp_fdt, 0, cons_file); + fdt_fd_associate_file(lwp_fdt, 1, cons_file); + fdt_fd_associate_file(lwp_fdt, 2, cons_file); } + close(cons_fd); return; } @@ -1197,11 +1318,8 @@ pid_t lwp_execve(char *filename, int debug, int argc, char **argv, char **envp) int result; struct rt_lwp *lwp; char *thread_name; - char *argv_last = argv[argc - 1]; - int bg = 0; struct process_aux *aux; int tid = 0; - int ret; if (filename == RT_NULL) { @@ -1213,7 +1331,7 @@ pid_t lwp_execve(char *filename, int debug, int argc, char **argv, char **envp) return -EACCES; } - lwp = lwp_create(LWP_CREATE_FLAG_ALLOC_PID); + lwp = lwp_create(LWP_CREATE_FLAG_ALLOC_PID | LWP_CREATE_FLAG_NOTRACE_EXEC); if (lwp == RT_NULL) { @@ -1236,12 +1354,6 @@ pid_t lwp_execve(char *filename, int debug, int argc, char **argv, char **envp) } #endif - if (argv_last[0] == '&' && argv_last[1] == '\0') - { - argc--; - bg = 1; - } - if ((aux = lwp_argscopy(lwp, argc, argv, envp)) == RT_NULL) { lwp_tid_put(tid); @@ -1263,7 +1375,7 @@ pid_t lwp_execve(char *filename, int debug, int argc, char **argv, char **envp) rt_thread_t thread = RT_NULL; rt_uint32_t priority = 25, tick = 200; - lwp_copy_stdio_fdt(lwp); + lwp_execve_setup_stdio(lwp); /* obtain the base name */ thread_name = strrchr(filename, '/'); @@ -1284,88 +1396,46 @@ pid_t lwp_execve(char *filename, int debug, int argc, char **argv, char **envp) if (thread != RT_NULL) { struct rt_lwp *self_lwp; + rt_session_t session; + rt_processgroup_t group; thread->tid = tid; lwp_tid_set_thread(tid, thread); LOG_D("lwp kernel => (0x%08x, 0x%08x)\n", (rt_size_t)thread->stack_addr, (rt_size_t)thread->stack_addr + thread->stack_size); self_lwp = lwp_self(); + + /* when create init, self_lwp == null */ + if (self_lwp == RT_NULL && lwp_to_pid(lwp) != 1) + { + self_lwp = lwp_from_pid_and_lock(1); + } + if (self_lwp) { - //lwp->tgroup_leader = &thread; //add thread group leader for lwp - lwp->__pgrp = tid; - lwp->session = self_lwp->session; /* lwp add to children link */ lwp_children_register(self_lwp, lwp); } - else - { - //lwp->tgroup_leader = &thread; //add thread group leader for lwp - lwp->__pgrp = tid; - } - if (!bg) + + session = RT_NULL; + group = RT_NULL; + + group = lwp_pgrp_create(lwp); + if (group) { - if (lwp->session == -1) + lwp_pgrp_insert(group, lwp); + if (self_lwp == RT_NULL) { - struct tty_struct *tty = RT_NULL; - struct rt_lwp *old_lwp; - tty = (struct tty_struct *)console_tty_get(); - old_lwp = tty->foreground; - if (old_lwp) - { - rt_mutex_take(&tty->lock, RT_WAITING_FOREVER); - ret = tty_push(&tty->head, old_lwp); - rt_mutex_release(&tty->lock); - - if (ret < 0) - { - lwp_tid_put(tid); - lwp_ref_dec(lwp); - LOG_E("malloc fail!\n"); - return -ENOMEM; - } - } - - lwp->tty = tty; - lwp->tty->pgrp = lwp->__pgrp; - lwp->tty->session = lwp->session; - lwp->tty->foreground = lwp; - tcgetattr(1, &stdin_termios); - old_stdin_termios = stdin_termios; - stdin_termios.c_lflag |= ICANON | ECHO | ECHOCTL; - tcsetattr(1, 0, &stdin_termios); + session = lwp_session_create(lwp); + lwp_session_insert(session, group); } else { - if (self_lwp != RT_NULL) - { - rt_mutex_take(&self_lwp->tty->lock, RT_WAITING_FOREVER); - ret = tty_push(&self_lwp->tty->head, self_lwp); - rt_mutex_release(&self_lwp->tty->lock); - if (ret < 0) - { - lwp_tid_put(tid); - lwp_ref_dec(lwp); - LOG_E("malloc fail!\n"); - return -ENOMEM; - } - - lwp->tty = self_lwp->tty; - lwp->tty->pgrp = lwp->__pgrp; - lwp->tty->session = lwp->session; - lwp->tty->foreground = lwp; - } - else - { - lwp->tty = RT_NULL; - } - + session = lwp_session_find(lwp_sid_get_byprocess(self_lwp)); + lwp_session_insert(session, group); } } - else - { - lwp->background = RT_TRUE; - } + thread->lwp = lwp; #ifndef ARCH_MM_MMU struct lwp_app_head *app_head = (struct lwp_app_head*)lwp->text_entry; @@ -1381,6 +1451,8 @@ pid_t lwp_execve(char *filename, int debug, int argc, char **argv, char **envp) #endif /* not defined ARCH_MM_MMU */ rt_list_insert_after(&lwp->t_grp, &thread->sibling); + lwp->did_exec = RT_TRUE; + if (debug && rt_dbg_ops) { lwp->debug = debug; @@ -1482,30 +1554,30 @@ rt_err_t lwp_backtrace_frame(rt_thread_t uthread, struct rt_hw_backtrace_frame * char **argv; rt_lwp_t lwp; - if (uthread->lwp) + if (uthread && uthread->lwp && rt_scheduler_is_available()) { lwp = uthread->lwp; argv = lwp_get_command_line_args(lwp); if (argv) { - LOG_RAW("please use: addr2line -e %s -a -f", argv[0]); + rt_kprintf("please use: addr2line -e %s -a -f", argv[0]); lwp_free_command_line_args(argv); } else { - LOG_RAW("please use: addr2line -e %s -a -f", lwp->cmd); + rt_kprintf("please use: addr2line -e %s -a -f", lwp->cmd); } while (nesting < RT_BACKTRACE_LEVEL_MAX_NR) { - LOG_RAW(" 0x%lx", frame->pc); + rt_kprintf(" 0x%lx", frame->pc); if (rt_hw_backtrace_frame_unwind(uthread, frame)) { break; } nesting++; } - LOG_RAW("\n"); + rt_kprintf("\n"); rc = RT_EOK; } return rc; diff --git a/components/lwp/lwp.h b/components/lwp/lwp.h index 1ac98493a15..c504ef60ad1 100644 --- a/components/lwp/lwp.h +++ b/components/lwp/lwp.h @@ -9,6 +9,9 @@ * 2019-10-12 Jesven Add MMU and userspace support * 2020-10-08 Bernard Architecture and code cleanup * 2021-08-26 linzhenxing add lwp_setcwd\lwp_getcwd + * 2023-11-17 xqyjlj add process group and session support + * 2023-12-02 Shell Add macro to create lwp status and + * fix dead lock problem on pgrp */ /* @@ -48,10 +51,6 @@ #include #endif /* RT_USING_MUSLLIBC */ -#ifdef RT_USING_TTY -struct tty_struct; -#endif /* RT_USING_TTY */ - #ifdef __cplusplus extern "C" { #endif @@ -76,12 +75,48 @@ struct rt_lwp_notify rt_slist_t list_node; }; +struct lwp_tty; + #ifdef RT_USING_MUSLLIBC -#define LWP_CREATE_STAT(exit_code) (((exit_code) & 0xff) << 8) +#define LWP_COREDUMP_FLAG 0x80 +#define LWP_CREATE_STAT_EXIT(exit_code) (((exit_code)&0xff) << 8) +#define LWP_CREATE_STAT_SIGNALED(signo, coredump) (((signo) & 0x7f) | (coredump ? LWP_COREDUMP_FLAG : 0)) +#define LWP_CREATE_STAT_STOPPED(signo) (LWP_CREATE_STAT_EXIT(signo) | 0x7f) +#define LWP_CREATE_STAT_CONTINUED (0xffff) #else #error "No compatible lwp set status provided for this libc" #endif +typedef struct rt_lwp *rt_lwp_t; +typedef struct rt_session *rt_session_t; +typedef struct rt_processgroup *rt_processgroup_t; + +struct rt_session { + struct rt_object object; + rt_lwp_t leader; + rt_list_t processgroup; + pid_t sid; + pid_t foreground_pgid; + struct rt_mutex mutex; + struct lwp_tty *ctty; +}; + +struct rt_processgroup { + struct rt_object object; + rt_lwp_t leader; + rt_list_t process; + rt_list_t pgrp_list_node; + pid_t pgid; + pid_t sid; + struct rt_session *session; + struct rt_mutex mutex; + + rt_atomic_t ref; + + /* flags on process group */ + unsigned int is_orphaned:1; +}; + struct rt_lwp { #ifdef ARCH_MM_MMU @@ -100,14 +135,21 @@ struct rt_lwp uint8_t lwp_type; uint8_t reserv[3]; - struct rt_lwp *parent; - struct rt_lwp *first_child; - struct rt_lwp *sibling; + /* flags */ + unsigned int terminated:1; + unsigned int background:1; + unsigned int term_ctrlterm:1; /* have control terminal? */ + unsigned int did_exec:1; /* Whether exec has been performed */ + unsigned int jobctl_stopped:1; /* job control: current proc is stopped */ + unsigned int wait_reap_stp:1; /* job control: has wait event for parent */ + unsigned int sig_protected:1; /* signal: protected proc cannot be killed or stopped */ + + struct rt_lwp *parent; /* parent process */ + struct rt_lwp *first_child; /* first child process */ + struct rt_lwp *sibling; /* sibling(child) process */ - rt_list_t wait_list; - rt_bool_t terminated; - rt_bool_t background; - int lwp_ret; + struct rt_wqueue waitpid_waiters; + lwp_status_t lwp_status; void *text_entry; uint32_t text_size; @@ -118,15 +160,16 @@ struct rt_lwp void *args; uint32_t args_length; pid_t pid; - pid_t __pgrp; /*Accessed via process_group()*/ - pid_t tty_old_pgrp; - pid_t session; - rt_list_t t_grp; - rt_list_t timer; /* POSIX timer object binding to a process */ + pid_t sid; /* session ID */ + pid_t pgid; /* process group ID */ + struct rt_processgroup *pgrp; + rt_list_t pgrp_node; /* process group node */ + rt_list_t t_grp; /* thread group */ + rt_list_t timer; /* POSIX timer object binding to a process */ - int leader; /* boolean value for session group_leader*/ struct dfs_fdtable fdt; char cmd[RT_NAME_MAX]; + char *exe_file; /* process file path */ /* POSIX signal */ struct lwp_signal signal; @@ -135,7 +178,7 @@ struct rt_lwp struct rt_mutex object_mutex; struct rt_user_context user_ctx; - struct rt_wqueue wait_queue; /*for console */ + struct rt_wqueue wait_queue; /* for console */ struct tty_struct *tty; /* NULL if no tty */ struct lwp_avl_struct *address_search_head; /* for addressed object fast search */ @@ -152,8 +195,9 @@ struct rt_lwp uint64_t generation; unsigned int asid; #endif + struct rusage rt_rusage; }; -typedef struct rt_lwp *rt_lwp_t; + struct rt_lwp *lwp_self(void); rt_err_t lwp_children_register(struct rt_lwp *parent, struct rt_lwp *child); @@ -182,7 +226,7 @@ void lwp_tid_put(int tid); * @return rt_thread_t */ rt_thread_t lwp_tid_get_thread_and_inc_ref(int tid); - +rt_thread_t lwp_tid_get_thread_raw(int tid); /** * @brief Decrease a reference count * @@ -216,6 +260,78 @@ rt_err_t lwp_futex_init(void); rt_err_t lwp_futex(struct rt_lwp *lwp, int *uaddr, int op, int val, const struct timespec *timeout, int *uaddr2, int val3); +/* processgroup api */ +rt_inline pid_t lwp_pgid_get_bypgrp(rt_processgroup_t group) +{ + return group ? group->pgid : 0; +} + +rt_inline pid_t lwp_pgid_get_byprocess(rt_lwp_t process) +{ + return process ? process->pgid : 0; +} +rt_processgroup_t lwp_pgrp_find(pid_t pgid); +void lwp_pgrp_dec_ref(rt_processgroup_t pgrp); +rt_processgroup_t lwp_pgrp_find_and_inc_ref(pid_t pgid); +rt_processgroup_t lwp_pgrp_create(rt_lwp_t leader); +int lwp_pgrp_delete(rt_processgroup_t group); + +/** + * Note: all the pgrp with process operation must be called in the context where + * process lock is taken. This is protect us from a possible dead lock condition + * + * The order is mandatory in the case: + * PGRP_LOCK(pgrp); + * LWP_LOCK(p); + * ... bussiness logic + * LWP_UNLOCK(p); + * PGRP_UNLOCK(pgrp); + */ +int lwp_pgrp_insert(rt_processgroup_t group, rt_lwp_t process); +int lwp_pgrp_remove(rt_processgroup_t group, rt_lwp_t process); +int lwp_pgrp_move(rt_processgroup_t group, rt_lwp_t process); + +int lwp_pgrp_update_children_info(rt_processgroup_t group, pid_t sid, pid_t pgid); + +/* session api */ +rt_inline pid_t lwp_sid_get_bysession(rt_session_t session) +{ + return session ? session->sid : 0; +} + +rt_inline pid_t lwp_sid_get_bypgrp(rt_processgroup_t group) +{ + return group ? group->sid : 0; +} + +rt_inline pid_t lwp_sid_get_byprocess(rt_lwp_t process) +{ + return process ? process->sid : 0; +} + +rt_session_t lwp_session_find(pid_t sid); +rt_session_t lwp_session_create(struct rt_lwp *leader); +int lwp_session_delete(rt_session_t session); + +/** + * Note: all the session operation must be called in the context where + * process lock is taken. This is protect us from a possible dead lock condition + * + * The order is mandatory in the case: + * PGRP_LOCK(pgrp); + * LWP_LOCK(p); + * ... bussiness logic + * LWP_UNLOCK(p); + * PGRP_UNLOCK(pgrp); + */ +int lwp_session_insert(rt_session_t session, rt_processgroup_t group); +int lwp_session_remove(rt_session_t session, rt_processgroup_t group); +int lwp_session_move(rt_session_t session, rt_processgroup_t group); +int lwp_session_update_children_info(rt_session_t session, pid_t sid); +int lwp_session_set_foreground(rt_session_t session, pid_t pgid); + +/* complete the job control related bussiness on process exit */ +void lwp_jobctrl_on_exit(struct rt_lwp *lwp); #ifdef __cplusplus } @@ -301,6 +417,7 @@ int dbg_step_type(void); void dbg_attach_req(void *pc); int dbg_check_suspend(void); void rt_hw_set_process_id(int pid); +void lwp_futex_exit_robust_list(rt_thread_t thread); /* backtrace service */ rt_err_t lwp_backtrace_frame(rt_thread_t uthread, struct rt_hw_backtrace_frame *frame); diff --git a/components/lwp/lwp_arch_comm.h b/components/lwp/lwp_arch_comm.h index 885cd63ca97..3eec4078623 100644 --- a/components/lwp/lwp_arch_comm.h +++ b/components/lwp/lwp_arch_comm.h @@ -61,6 +61,10 @@ rt_noreturn void arch_thread_signal_enter(int signo, siginfo_t *psiginfo, void *exp_frame, void *entry_uaddr, lwp_sigset_t *save_sig_mask); +void arch_signal_check_erestart(void *eframe, void *ksp); + +void arch_syscall_set_errno(void *eframe, int expected, int code); + int arch_backtrace_uthread(rt_thread_t thread); #endif /* __LWP_ARCH_COMM__ */ diff --git a/components/lwp/lwp_elf.c b/components/lwp/lwp_elf.c index 0610769b264..f654adc5b76 100644 --- a/components/lwp/lwp_elf.c +++ b/components/lwp/lwp_elf.c @@ -797,6 +797,7 @@ int lwp_load(const char *filename, struct rt_lwp *lwp, uint8_t *load_addr, size_ /* copy file name to process name */ rt_strncpy(lwp->cmd, filename, RT_NAME_MAX); + lwp->exe_file = dfs_normalize_path(NULL, filename); // malloc ret = elf_file_load(&load_info); if (ret != RT_EOK) diff --git a/components/lwp/lwp_futex.c b/components/lwp/lwp_futex.c index f32b4a18f40..a49a86680a0 100644 --- a/components/lwp/lwp_futex.c +++ b/components/lwp/lwp_futex.c @@ -475,6 +475,11 @@ static long _futex_wake(rt_futex_t futex, struct rt_lwp *lwp, int number, { number--; woken_cnt++; + is_empty = RT_FALSE; + } + else + { + is_empty = RT_TRUE; } _futex_unlock(lwp, op_flags); } @@ -512,23 +517,16 @@ static long _futex_requeue(rt_futex_t futex1, rt_futex_t futex2, */ while (nr_wake && !is_empty) { - rt_sched_lock_level_t slvl; - rt_sched_lock(&slvl); - is_empty = rt_list_isempty(&(futex1->waiting_thread)); - if (!is_empty) + if (rt_susp_list_dequeue(&futex1->waiting_thread, RT_EOK)) { - thread = RT_THREAD_LIST_NODE_ENTRY(futex1->waiting_thread.next); - /* remove from waiting list */ - rt_list_remove(&RT_THREAD_LIST_NODE(thread)); - - thread->error = RT_EOK; - /* resume the suspended thread */ - rt_thread_resume(thread); - nr_wake--; woken_cnt++; + is_empty = RT_FALSE; + } + else + { + is_empty = RT_TRUE; } - rt_sched_unlock(slvl); } rtn = woken_cnt; @@ -542,7 +540,10 @@ static long _futex_requeue(rt_futex_t futex1, rt_futex_t futex2, { rt_sched_lock_level_t slvl; rt_sched_lock(&slvl); + + /* moving from one susp list to another */ is_empty = rt_list_isempty(&(futex1->waiting_thread)); + if (!is_empty) { thread = RT_THREAD_LIST_NODE_ENTRY(futex1->waiting_thread.next); @@ -914,7 +915,7 @@ void lwp_futex_exit_robust_list(rt_thread_t thread) rc = _fetch_robust_entry(&next_entry, &entry->next, &next_pi); if (entry != pending) { - if (_handle_futex_death((void *)entry + futex_offset, thread, pi, + if (_handle_futex_death((int *)((size_t)entry + futex_offset), thread, pi, RT_FALSE)) return; } diff --git a/components/lwp/lwp_internal.c b/components/lwp/lwp_internal.c index bb316507908..1fc68f2e733 100644 --- a/components/lwp/lwp_internal.c +++ b/components/lwp/lwp_internal.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2023-07-25 Shell first version + * 2023-11-25 Shell Add pgrp, session lock API */ #define DBG_TAG "lwp.internal" @@ -15,7 +16,7 @@ #include #include "lwp_internal.h" -static rt_err_t _mutex_take_safe(rt_mutex_t mtx, rt_int32_t timeout, rt_bool_t interruptable) +static rt_err_t _mutex_take_safe(rt_mutex_t mtx, rt_int32_t timeout, int flags) { LWP_DEF_RETURN_CODE(rc); int retry; @@ -45,15 +46,15 @@ static rt_err_t _mutex_take_safe(rt_mutex_t mtx, rt_int32_t timeout, rt_bool_t i do { retry = 0; - if (interruptable) + if (flags & LWP_MTX_FLAGS_INTR) rc = rt_mutex_take_interruptible(mtx, effect_timeout); else - rc = rt_mutex_take(mtx, effect_timeout); + rc = rt_mutex_take_killable(mtx, effect_timeout); #ifdef LWP_DEBUG if (rc == RT_EOK) { - if (rt_mutex_get_hold(mtx) > 1) + if (!(flags & LWP_MTX_FALGS_NESTED) && rt_mutex_get_hold(mtx) > 1) { LOG_W("Already hold the lock"); rt_backtrace(); @@ -88,6 +89,7 @@ static rt_err_t _mutex_take_safe(rt_mutex_t mtx, rt_int32_t timeout, rt_bool_t i } else { + rc = -RT_ERROR; LOG_W("%s: mtx should not be NULL", __func__); RT_ASSERT(0); } @@ -95,10 +97,10 @@ static rt_err_t _mutex_take_safe(rt_mutex_t mtx, rt_int32_t timeout, rt_bool_t i LWP_RETURN(rc); } -rt_err_t lwp_mutex_take_safe(rt_mutex_t mtx, rt_int32_t timeout, rt_bool_t interruptable) +rt_err_t lwp_mutex_take_safe(rt_mutex_t mtx, rt_int32_t timeout, int flags) { LWP_DEF_RETURN_CODE(rc); - rc = _mutex_take_safe(mtx, timeout, interruptable); + rc = _mutex_take_safe(mtx, timeout, flags); LWP_RETURN(rc); } @@ -116,18 +118,17 @@ rt_err_t lwp_mutex_release_safe(rt_mutex_t mtx) LWP_RETURN(rc); } -rt_err_t lwp_critical_enter(struct rt_lwp *lwp) +rt_err_t lwp_critical_enter(struct rt_lwp *lwp, int flags) { rt_err_t rc; - rc = lwp_mutex_take_safe(&lwp->lwp_lock, RT_WAITING_FOREVER, 0); + do { + rc = lwp_mutex_take_safe(&lwp->lwp_lock, RT_WAITING_FOREVER, flags); + } while (rc != RT_EOK && !(flags & LWP_MTX_FLAGS_INTR) && rc == -RT_EINTR); /* if current process is force killed */ - if (rc != RT_EOK) + if (rc != RT_EOK && rc != -RT_EINTR) { - if (rc == -RT_EINTR && lwp_self() != RT_NULL) - sys_exit(EXIT_SUCCESS); - else - LOG_I("%s: unexpected return code = %ld", __func__, rc); + LOG_I("%s: unexpected return code = %ld", __func__, rc); } return rc; @@ -137,3 +138,45 @@ rt_err_t lwp_critical_exit(struct rt_lwp *lwp) { return lwp_mutex_release_safe(&lwp->lwp_lock); } + +rt_err_t lwp_pgrp_critical_enter(struct rt_processgroup *pgrp, int flags) +{ + rt_err_t rc; + do { + rc = lwp_mutex_take_safe(&pgrp->mutex, RT_WAITING_FOREVER, flags); + } while (rc != RT_EOK && !(flags & LWP_MTX_FLAGS_INTR) && rc == -RT_EINTR); + + /* if current process is force killed */ + if (rc != RT_EOK && rc != -RT_EINTR) + { + LOG_I("%s: unexpected return code = %ld", __func__, rc); + } + + return rc; +} + +rt_err_t lwp_pgrp_critical_exit(struct rt_processgroup *pgrp) +{ + return lwp_mutex_release_safe(&pgrp->mutex); +} + +rt_err_t lwp_sess_critical_enter(struct rt_session *sess, int flags) +{ + rt_err_t rc; + do { + rc = lwp_mutex_take_safe(&sess->mutex, RT_WAITING_FOREVER, flags); + } while (rc != RT_EOK && !(flags & LWP_MTX_FLAGS_INTR) && rc == -RT_EINTR); + + /* if current process is force killed */ + if (rc != RT_EOK && rc != -RT_EINTR) + { + LOG_I("%s: unexpected return code = %ld", __func__, rc); + } + + return rc; +} + +rt_err_t lwp_sess_critical_exit(struct rt_session *sess) +{ + return lwp_mutex_release_safe(&sess->mutex); +} diff --git a/components/lwp/lwp_internal.h b/components/lwp/lwp_internal.h index 1a605b007a1..c942be0136d 100644 --- a/components/lwp/lwp_internal.h +++ b/components/lwp/lwp_internal.h @@ -6,21 +6,32 @@ * Change Logs: * Date Author Notes * 2023-07-25 Shell first version + * 2023-11-25 Shell Add pgrp, session lock API */ #ifndef __LWP_INTERNAL_H__ #define __LWP_INTERNAL_H__ #include "lwp.h" +#include "lwp_arch.h" #include "lwp_user_mm.h" +#include "lwp_mm.h" #include #include "libc_musl.h" struct rt_lwp; -rt_err_t lwp_mutex_take_safe(rt_mutex_t mtx, rt_int32_t timeout, rt_bool_t interruptable); + +#define LWP_MTX_FLAGS_INTR 0x1 /* interruptible waiting */ +#define LWP_MTX_FALGS_NESTED 0x2 /* allow nested */ +rt_err_t lwp_mutex_take_safe(rt_mutex_t mtx, rt_int32_t timeout, int flags); rt_err_t lwp_mutex_release_safe(rt_mutex_t mtx); +rt_inline rt_bool_t lwp_in_user_space(const char *addr) +{ + return (addr >= (char *)USER_VADDR_START && addr < (char *)USER_VADDR_TOP); +} + #ifdef RT_USING_SMP #define LOCAL_IRQ_MASK() rt_hw_local_irq_disable() #define LOCAL_IRQ_UNMASK(level) rt_hw_local_irq_enable(level) @@ -30,16 +41,34 @@ rt_err_t lwp_mutex_release_safe(rt_mutex_t mtx); #endif #ifndef LWP_USING_CPUS_LOCK -rt_err_t lwp_critical_enter(struct rt_lwp *lwp); +rt_err_t lwp_sess_critical_enter(struct rt_session *sess, int flags); +rt_err_t lwp_sess_critical_exit(struct rt_session *sess); +rt_err_t lwp_pgrp_critical_enter(struct rt_processgroup *pgrp, int flags); +rt_err_t lwp_pgrp_critical_exit(struct rt_processgroup *pgrp); +rt_err_t lwp_critical_enter(struct rt_lwp *lwp, int flags); rt_err_t lwp_critical_exit(struct rt_lwp *lwp); -#define LWP_LOCK(lwp) \ - do { \ - RT_DEBUG_SCHEDULER_AVAILABLE(1); \ - if (lwp_critical_enter(lwp) != RT_EOK) \ - { \ - RT_ASSERT(0); \ - } \ +#define LWP_ASSERT_LOCKED(proc) RT_ASSERT(rt_mutex_get_owner(&(proc)->lwp_lock) == rt_thread_self()) +#define PGRP_ASSERT_LOCKED(pgrp) RT_ASSERT(rt_mutex_get_owner(&(pgrp)->mutex) == rt_thread_self()) + +#define LWP_LOCK(lwp) \ + do \ + { \ + RT_DEBUG_SCHEDULER_AVAILABLE(1); \ + if (lwp_critical_enter(lwp, 0) != RT_EOK) \ + { \ + RT_ASSERT(0); \ + } \ + } while (0) + +#define LWP_LOCK_NESTED(lwp) \ + do \ + { \ + RT_DEBUG_SCHEDULER_AVAILABLE(1); \ + if (lwp_critical_enter(lwp, LWP_MTX_FALGS_NESTED) != RT_EOK) \ + { \ + RT_ASSERT(0); \ + } \ } while (0) #define LWP_UNLOCK(lwp) \ @@ -50,10 +79,72 @@ rt_err_t lwp_critical_exit(struct rt_lwp *lwp); } \ } while (0) +#define PGRP_LOCK(pgrp) \ + do \ + { \ + RT_DEBUG_SCHEDULER_AVAILABLE(1); \ + if (lwp_pgrp_critical_enter(pgrp, 0) != RT_EOK) \ + { \ + RT_ASSERT(0); \ + } \ + } while (0) + +#define PGRP_LOCK_NESTED(pgrp) \ + do \ + { \ + RT_DEBUG_SCHEDULER_AVAILABLE(1); \ + if (lwp_pgrp_critical_enter(pgrp, LWP_MTX_FALGS_NESTED) != RT_EOK) \ + { \ + RT_ASSERT(0); \ + } \ + } while (0) + +#define PGRP_UNLOCK(pgrp) \ + do \ + { \ + if (lwp_pgrp_critical_exit(pgrp) != RT_EOK) \ + { \ + RT_ASSERT(0); \ + } \ + } while (0) + +#define SESS_LOCK(sess) \ + do \ + { \ + RT_DEBUG_SCHEDULER_AVAILABLE(1); \ + if (lwp_sess_critical_enter(sess, 0) != RT_EOK) \ + { \ + RT_ASSERT(0); \ + } \ + } while (0) + +#define SESS_LOCK_NESTED(sess) \ + do \ + { \ + RT_DEBUG_SCHEDULER_AVAILABLE(1); \ + if (lwp_sess_critical_enter(sess, LWP_MTX_FALGS_NESTED) != RT_EOK) \ + { \ + RT_ASSERT(0); \ + } \ + } while (0) + +#define SESS_UNLOCK(sess) \ + do \ + { \ + if (lwp_sess_critical_exit(sess) != RT_EOK) \ + { \ + RT_ASSERT(0); \ + } \ + } while (0) + #else #define LWP_LOCK(lwp) rt_base_t level = rt_hw_interrupt_disable() #define LWP_UNLOCK(lwp) rt_hw_interrupt_enable(level) +#define PGRP_LOCK(pgrp) rt_base_t level = rt_hw_interrupt_disable() +#define PGRP_UNLOCK(pgrp) rt_hw_interrupt_enable(level) +#define SESS_LOCK(sess) rt_base_t level = rt_hw_interrupt_disable() +#define SESS_UNLOCK(sess) rt_hw_interrupt_enable(level) #endif /* LWP_USING_CPUS_LOCK */ @@ -95,4 +186,6 @@ rt_err_t lwp_critical_exit(struct rt_lwp *lwp); #define LWP_RETURN(name) {RT_ASSERT(name != _LWP_UNINITIALIZED_RC);return name;} #endif /* LWP_DEBUG */ +int load_ldso(struct rt_lwp *lwp, char *exec_name, char *const argv[], char *const envp[]); + #endif /* __LWP_INTERNAL_H__ */ diff --git a/components/lwp/lwp_jobctrl.c b/components/lwp/lwp_jobctrl.c new file mode 100644 index 00000000000..5f4848f500f --- /dev/null +++ b/components/lwp/lwp_jobctrl.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-13 Shell init ver. + */ + +#define DBG_TAG "lwp.tty" +#define DBG_LVL DBG_INFO +#include + +#include +#include "lwp_internal.h" + +static void jobctrl_set_pgrp_orphaned(struct rt_processgroup *pgrp) +{ + rt_lwp_t proc, nx_proc; + PGRP_LOCK(pgrp); + + pgrp->is_orphaned = 1; + rt_list_for_each_entry(proc, &pgrp->process, pgrp_node) + { + LWP_LOCK(proc); + if (proc->jobctl_stopped) + { + LWP_UNLOCK(proc); + rt_list_for_each_entry_safe(proc, nx_proc, &pgrp->process, pgrp_node) + { + LWP_LOCK(proc); + lwp_signal_kill(proc, SIGHUP, SI_KERNEL, 0); + lwp_signal_kill(proc, SIGCONT, SI_KERNEL, 0); + LWP_UNLOCK(proc); + } + } + LWP_UNLOCK(proc); + } + + PGRP_UNLOCK(pgrp); +} + +void lwp_jobctrl_on_exit(struct rt_lwp *lwp) +{ + rt_processgroup_t pgrp; + rt_session_t session; + lwp_tty_t tp; + + pgrp = lwp->pgrp; + RT_ASSERT(pgrp); + session = pgrp->session; + RT_ASSERT(session); + + /** + * as a session leader, we have to mark tty as freed. So others can race to + * take it before we actually close and released that tty + */ + SESS_LOCK(session); + if (session->sid == lwp->pid) + { + tp = session->ctty; + session->leader = 0; + + /* signal to foreground group that modem is disconnected */ + if (tp) + { + tty_lock(tp); + if (tp->t_session == session) + lwp_tty_signal_pgrp(tp, SIGHUP); + tty_unlock(tp); + } + + /* revoke tty vnode ? */ + + rt_list_for_each_entry(pgrp, &session->processgroup, pgrp_list_node) + { + jobctrl_set_pgrp_orphaned(pgrp); + } + + } + SESS_UNLOCK(session); + + /* release tty */ + /* allow tty stolen? */ +} diff --git a/components/lwp/lwp_pgrp.c b/components/lwp/lwp_pgrp.c new file mode 100644 index 00000000000..700565b165b --- /dev/null +++ b/components/lwp/lwp_pgrp.c @@ -0,0 +1,542 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-17 xqyjlj the first version + * 2023-11-28 Shell Add reference management for pgrp; + * Using lwp lock API and fix the dead lock problem + */ + +#include "lwp.h" +#include "lwp_internal.h" +#include "lwp_syscall.h" + +#define DBG_TAG "lwp.pgrp" +#define DBG_LVL DBG_WARNING +#include + +void lwp_pgrp_dec_ref(rt_processgroup_t pgrp) +{ + if (rt_atomic_add(&pgrp->ref, -1) == 1) + { + rt_mutex_detach(&(pgrp->mutex)); + + /* clear self pgid */ + pgrp->pgid = 0; + rt_free(pgrp); + } +} + +rt_processgroup_t lwp_pgrp_find_and_inc_ref(pid_t pgid) +{ + rt_processgroup_t group; + + group = lwp_pgrp_find(pgid); + if (group) + { + rt_atomic_add(&(group->ref), 1); + } + + return group; +} + +rt_processgroup_t lwp_pgrp_find(pid_t pgid) +{ + rt_base_t level; + rt_processgroup_t group = RT_NULL; + rt_list_t *node = RT_NULL; + struct rt_object_information *information = RT_NULL; + + information = rt_object_get_information(RT_Object_Class_ProcessGroup); + + /* parameter check */ + if ((pgid < 0) || (information == RT_NULL)) + { + return RT_NULL; + } + + if (pgid == 0) + { + pgid = lwp_getpid(); + } + + /* enter critical */ + level = rt_spin_lock_irqsave(&(information->spinlock)); + + /* try to find process group */ + rt_list_for_each(node, &(information->object_list)) + { + group = (rt_processgroup_t)rt_list_entry(node, struct rt_object, list); + if (group->pgid == pgid) + { + rt_spin_unlock_irqrestore(&(information->spinlock), level); + + return group; + } + } + + rt_spin_unlock_irqrestore(&(information->spinlock), level); + + LOG_I("cannot find(pgid:%d)() by (pid:%d, pgid:%d)", pgid, lwp_getpid(), lwp_pgid_get_byprocess(lwp_self())); + + return RT_NULL; +} + +rt_processgroup_t lwp_pgrp_create(rt_lwp_t leader) +{ + rt_processgroup_t group = RT_NULL; + + /* parameter check */ + if (leader == RT_NULL) + { + return RT_NULL; + } + + group = rt_malloc(sizeof(struct rt_processgroup)); + if (group != RT_NULL) + { + rt_object_init(&(group->object), RT_Object_Class_ProcessGroup, "pgrp"); + rt_list_init(&(group->process)); + rt_list_init(&(group->pgrp_list_node)); + rt_mutex_init(&(group->mutex), "pgrp", RT_IPC_FLAG_PRIO); + group->leader = leader; + group->sid = 0; + group->session = RT_NULL; + group->is_orphaned = 0; + group->pgid = lwp_to_pid(leader); + rt_atomic_store(&group->ref, 1); + } + + LOG_I("create(ptr:%p, pgid:%d)() by pid:%d", group, group->pgid, lwp_getpid()); + + return group; +} + +#include + +int lwp_pgrp_delete(rt_processgroup_t group) +{ + int retry = 1; + rt_session_t session = RT_NULL; + int is_session_free = 0; + lwp_tty_t ctty; + + /* parameter check */ + if (group == RT_NULL) + { + return -EINVAL; + } + + LOG_I("delete(ptr:%p, pgid:%d)() by pid:%d", group, group->pgid, lwp_getpid()); + + while (retry) + { + retry = 0; + session = lwp_session_find(lwp_sid_get_bypgrp(group)); + if (session) + { + ctty = session->ctty; + if (ctty) + { + /** + * Note: it's safe to release pgrp even we do this multiple, + * the neccessary check is done before the tty actually detach + */ + tty_lock(ctty); + tty_rel_pgrp(ctty, group); // tty_unlock + } + + SESS_LOCK(session); + PGRP_LOCK_NESTED(group); + if (group->session == session && session->ctty == ctty) + { + rt_object_detach(&(group->object)); + is_session_free = lwp_session_remove(session, group); + } + else + { + retry = 1; + + } + + PGRP_UNLOCK(group); + if (is_session_free != 1) + SESS_UNLOCK(session); + } + else + { + rt_object_detach(&(group->object)); + } + } + + lwp_pgrp_dec_ref(group); + return 0; +} + +int lwp_pgrp_insert(rt_processgroup_t group, rt_lwp_t process) +{ + /* parameter check */ + if (group == RT_NULL || process == RT_NULL) + { + return -EINVAL; + } + + PGRP_LOCK_NESTED(group); + LWP_LOCK_NESTED(process); + RT_ASSERT(rt_mutex_get_hold(&process->lwp_lock) <= rt_mutex_get_hold(&group->mutex)); + + process->pgid = group->pgid; + process->pgrp = group; + process->sid = group->sid; + rt_list_insert_after(&(group->process), &(process->pgrp_node)); + + LWP_UNLOCK(process); + PGRP_UNLOCK(group); + + return 0; +} + +int lwp_pgrp_remove(rt_processgroup_t group, rt_lwp_t process) +{ + rt_bool_t is_empty = RT_FALSE; + + /* parameter check */ + if (group == RT_NULL || process == RT_NULL) + { + return -EINVAL; + } + + PGRP_LOCK_NESTED(group); + LWP_LOCK_NESTED(process); + RT_ASSERT(rt_mutex_get_hold(&process->lwp_lock) <= rt_mutex_get_hold(&group->mutex)); + + rt_list_remove(&(process->pgrp_node)); + /* clear children sid and pgid */ + process->pgrp = RT_NULL; + process->pgid = 0; + process->sid = 0; + + LWP_UNLOCK(process); + + is_empty = rt_list_isempty(&(group->process)); + + PGRP_UNLOCK(group); + + if (is_empty) + { + lwp_pgrp_delete(group); + return 1; + } + + return 0; +} + +int lwp_pgrp_move(rt_processgroup_t group, rt_lwp_t process) +{ + int retry = 1; + rt_processgroup_t old_group; + + /* parameter check */ + if (group == RT_NULL || process == RT_NULL) + { + return -EINVAL; + } + + if (lwp_pgid_get_bypgrp(group) == lwp_pgid_get_byprocess(process)) + { + return 0; + } + + PGRP_LOCK(group); + while (retry) + { + retry = 0; + old_group = lwp_pgrp_find_and_inc_ref(lwp_pgid_get_byprocess(process)); + + PGRP_LOCK(old_group); + LWP_LOCK(process); + + if (process->pgrp == old_group) + { + lwp_pgrp_remove(old_group, process); + lwp_pgrp_insert(group, process); + } + else + { + retry = 1; + } + PGRP_UNLOCK(old_group); + LWP_UNLOCK(process); + + lwp_pgrp_dec_ref(old_group); + } + PGRP_UNLOCK(group); + + return 0; +} + +int lwp_pgrp_update_children_info(rt_processgroup_t group, pid_t sid, pid_t pgid) +{ + rt_list_t *node = RT_NULL; + rt_lwp_t process = RT_NULL; + + if (group == RT_NULL) + { + return -EINVAL; + } + + PGRP_LOCK_NESTED(group); + + /* try to find process group */ + rt_list_for_each(node, &(group->process)) + { + process = (rt_lwp_t)rt_list_entry(node, struct rt_lwp, pgrp_node); + LWP_LOCK(process); + if (sid != -1) + { + process->sid = sid; + } + if (pgid != -1) + { + process->pgid = pgid; + process->pgrp = group; + } + LWP_UNLOCK(process); + } + + PGRP_UNLOCK(group); + return 0; +} + +/** + * setpgid() sets the PGID of the process specified by pid to pgid. + * If pid is zero, then the process ID of the calling process is used. + * If pgid is zero, then the PGID of the process specified by pid is made the same as its process ID. + * If setpgid() is used to move a process from one process group to another (as is done by some shells when + * creating pipelines), both process groups must be part of the same session (see setsid(2) and credentials(7)). + * In this case, the pgid specifies an existing process group to be joined and the session ID of that group must + * match the session ID of the joining process. + */ +sysret_t sys_setpgid(pid_t pid, pid_t pgid) +{ + rt_lwp_t process, self_process; + pid_t sid; + rt_processgroup_t group; + rt_session_t session; + sysret_t err = 0; + + if (pgid == 0) + { + pgid = pid; + } + if (pgid < 0) + { + return -EINVAL; + } + + self_process = lwp_self(); + + if (pid == 0) + { + pid = self_process->pid; + process = self_process; + } + else + { + lwp_pid_lock_take(); + process = lwp_from_pid_locked(pid); + lwp_pid_lock_release(); + + if (process == RT_NULL) + { + return -ESRCH; + } + } + + LWP_LOCK(process); + + if (process->parent == self_process) + { + /** + * change the process group ID of one of the children of the calling process and the child was in + * a different session + */ + if (lwp_sid_get_byprocess(process) != lwp_sid_get_byprocess(self_process)) + { + err = -EPERM; + LWP_UNLOCK(process); + goto exit; + } + /** + * An attempt was made to change the process group ID of one of the children of the calling process + * and the child had already performed an execve(2) + */ + if (process->did_exec) + { + err = -EACCES; + LWP_UNLOCK(process); + goto exit; + } + } + else + { + /** + * pid is not the calling process and not a child of the calling process. + */ + if (process != self_process) + { + err = -ESRCH; + LWP_UNLOCK(process); + goto exit; + } + } + + LWP_UNLOCK(process); + + sid = lwp_sid_get_byprocess(self_process); + if (pgid != pid) + { + group = lwp_pgrp_find(pgid); + if (group == RT_NULL) + { + group = lwp_pgrp_create(process); + } + else + { + /** + * An attempt was made to move a process into a process group in a different session + */ + if (sid != lwp_sid_get_bypgrp(group)) + { + err = -EPERM; + goto exit; + } + /** + * or to change the process group ID of a session leader + */ + if (sid == lwp_to_pid(process)) + { + err = -EPERM; + goto exit; + } + lwp_pgrp_move(group, process); + } + } + else + { + group = lwp_pgrp_find(pgid); + if (group == RT_NULL) + { + group = lwp_pgrp_create(process); + lwp_pgrp_move(group, process); + session = lwp_session_find(sid); + if (session == RT_NULL) + { + LOG_E("the session of sid: %d cannot be found", sid); + err = -EPERM; + goto exit; + } + else + { + lwp_session_insert(session, group); + } + } + else // this represents repeated calls + { + /** + * or to change the process group ID of a session leader + */ + if (lwp_sid_get_bypgrp(group) == lwp_pgid_get_bypgrp(group)) + { + err = -EPERM; + goto exit; + } + else + { + err = 0; + } + } + } + +exit: + return err; +} + +/** + * getpgid() returns the PGID of the process specified by pid. + * If pid is zero, the process ID of the calling process is used. (Retrieving the PGID of a process other + * than the caller is rarely necessary, and the POSIX.1 getpgrp() is preferred for that task.) + */ +sysret_t sys_getpgid(pid_t pid) +{ + rt_lwp_t process; + + lwp_pid_lock_take(); + process = lwp_from_pid_locked(pid); + lwp_pid_lock_release(); + + if (process == RT_NULL) + { + return -ESRCH; + } + + return lwp_pgid_get_byprocess(process); +} + +#ifdef RT_USING_FINSH + +#include "finsh.h" + +long list_processgroup(void) +{ + int count = 0, index; + rt_processgroup_t *groups; + rt_processgroup_t group; + rt_thread_t thread; + char name[RT_NAME_MAX]; + + rt_kprintf("PGID SID leader process\n"); + rt_kprintf("---- ---- ----------------\n"); + + count = rt_object_get_length(RT_Object_Class_ProcessGroup); + if (count > 0) + { + /* get pointers */ + groups = (rt_processgroup_t *)rt_calloc(count, sizeof(rt_processgroup_t)); + if (groups) + { + index = rt_object_get_pointers(RT_Object_Class_ProcessGroup, (rt_object_t *)groups, count); + if (index > 0) + { + for (index = 0; index < count; index++) + { + struct rt_processgroup pgrp; + group = groups[index]; + PGRP_LOCK(group); + rt_memcpy(&pgrp, group, sizeof(struct rt_processgroup)); + PGRP_UNLOCK(group); + + if (pgrp.leader) + { + thread = rt_list_entry(pgrp.leader->t_grp.prev, struct rt_thread, sibling); + rt_strncpy(name, thread->parent.name, RT_NAME_MAX); + } + else + { + rt_strncpy(name, "nil", RT_NAME_MAX); + } + + rt_kprintf("%4d %4d %-*.*s\n", pgrp.pgid, pgrp.sid, RT_NAME_MAX, RT_NAME_MAX, name); + } + } + rt_free(groups); + } + } + + return 0; +} +MSH_CMD_EXPORT(list_processgroup, list process group); +#endif diff --git a/components/lwp/lwp_pid.c b/components/lwp/lwp_pid.c index 7479df03572..5b9f1f4098d 100644 --- a/components/lwp/lwp_pid.c +++ b/components/lwp/lwp_pid.c @@ -14,32 +14,47 @@ * error * 2023-10-27 shell Format codes of sys_exit(). Fix the data racing where lock is missed * Add reference on pid/tid, so the resource is not freed while using. + * Add support for waitpid(options=WNOHANG) + * 2023-11-16 xqyjlj Fix the case where pid is 0 + * 2023-11-17 xqyjlj add process group and session support + * 2023-11-24 shell Support of waitpid(options=WNOTRACED|WCONTINUED); + * Reimplement the waitpid with a wait queue method, and fixup problem + * with waitpid(pid=-1)/waitpid(pid=-pgid)/waitpid(pid=0) that only one + * process can be traced while waiter suspend * 2024-01-25 shell porting to new sched API */ /* includes scheduler related API */ #define __RT_IPC_SOURCE__ -#include -#include +/* for waitpid, we are compatible to GNU extension */ +#define _GNU_SOURCE #define DBG_TAG "lwp.pid" #define DBG_LVL DBG_INFO #include +#include "lwp_internal.h" + +#include +#include #include #include #include /* rename() */ +#include #include #include /* statfs() */ - -#include "lwp_internal.h" -#include "tty.h" +#include #ifdef ARCH_MM_MMU #include "lwp_user_mm.h" #endif +#ifdef RT_USING_DFS_PROCFS +#include "proc.h" +#include "procfs.h" +#endif + #define PID_MAX 10000 #define PID_CT_ASSERT(name, x) \ @@ -147,8 +162,23 @@ static void lwp_pid_put_locked(pid_t pid) } } +#ifdef RT_USING_DFS_PROCFS + rt_inline void _free_proc_dentry(rt_lwp_t lwp) + { + char pid_str[64] = {0}; + + rt_snprintf(pid_str, 64, "%d", lwp->pid); + pid_str[63] = 0; + proc_remove_dentry(pid_str, 0); + } +#else + #define _free_proc_dentry(lwp) +#endif + void lwp_pid_put(struct rt_lwp *lwp) { + _free_proc_dentry(lwp); + lwp_pid_lock_take(); lwp_pid_put_locked(lwp->pid); lwp_pid_lock_release(); @@ -168,6 +198,13 @@ static void lwp_pid_set_lwp_locked(pid_t pid, struct rt_lwp *lwp) { p->data = lwp; lwp_ref_inc(lwp); + +#ifdef RT_USING_DFS_PROCFS + if (pid) + { + proc_pid(pid); + } +#endif } } @@ -352,19 +389,23 @@ rt_lwp_t lwp_create(rt_base_t flags) if (new_lwp) { /* minimal setup of lwp object */ - new_lwp->session = -1; new_lwp->ref = 1; #ifdef RT_USING_SMP new_lwp->bind_cpu = RT_CPUS_NR; #endif - rt_list_init(&new_lwp->wait_list); + new_lwp->exe_file = RT_NULL; rt_list_init(&new_lwp->t_grp); + rt_list_init(&new_lwp->pgrp_node); rt_list_init(&new_lwp->timer); lwp_user_object_lock_init(new_lwp); rt_wqueue_init(&new_lwp->wait_queue); + rt_wqueue_init(&new_lwp->waitpid_waiters); lwp_signal_init(&new_lwp->signal); rt_mutex_init(&new_lwp->lwp_lock, "lwp_lock", RT_IPC_FLAG_PRIO); + if (flags & LWP_CREATE_FLAG_NOTRACE_EXEC) + new_lwp->did_exec = RT_TRUE; + /* lwp with pid */ if (flags & LWP_CREATE_FLAG_ALLOC_PID) { @@ -375,7 +416,7 @@ rt_lwp_t lwp_create(rt_base_t flags) lwp_user_object_lock_destroy(new_lwp); rt_free(new_lwp); new_lwp = RT_NULL; - LOG_E("pid slot fulled!\n"); + LOG_E("%s: pid slot fulled", __func__); } else { @@ -384,6 +425,20 @@ rt_lwp_t lwp_create(rt_base_t flags) } lwp_pid_lock_release(); } + rt_memset(&new_lwp->rt_rusage,0, sizeof(new_lwp->rt_rusage)); + + if (flags & LWP_CREATE_FLAG_INIT_USPACE) + { + rt_err_t error = lwp_user_space_init(new_lwp, 0); + if (error) + { + lwp_pid_put(new_lwp); + lwp_user_object_lock_destroy(new_lwp); + rt_free(new_lwp); + new_lwp = RT_NULL; + LOG_E("%s: failed to initialize user space", __func__); + } + } } LOG_D("%s(pid=%d) => %p", __func__, new_lwp ? new_lwp->pid : -1, new_lwp); @@ -393,6 +448,8 @@ rt_lwp_t lwp_create(rt_base_t flags) /** when reference is 0, a lwp can be released */ void lwp_free(struct rt_lwp* lwp) { + rt_processgroup_t group = RT_NULL; + if (lwp == RT_NULL) { return; @@ -406,6 +463,10 @@ void lwp_free(struct rt_lwp* lwp) * all the reference is clear) */ LOG_D("lwp free: %p", lwp); + rt_free(lwp->exe_file); + group = lwp_pgrp_find(lwp_pgid_get_byprocess(lwp)); + if (group) + lwp_pgrp_remove(group, lwp); LWP_LOCK(lwp); @@ -472,6 +533,15 @@ void lwp_free(struct rt_lwp* lwp) rt_inline rt_noreturn void _thread_exit(rt_lwp_t lwp, rt_thread_t thread) { + LWP_LOCK(lwp); + lwp->rt_rusage.ru_stime.tv_sec += thread->system_time / RT_TICK_PER_SECOND; + lwp->rt_rusage.ru_stime.tv_usec += thread->system_time % RT_TICK_PER_SECOND * (1000000 / RT_TICK_PER_SECOND); + lwp->rt_rusage.ru_utime.tv_sec += thread->user_time / RT_TICK_PER_SECOND; + lwp->rt_rusage.ru_utime.tv_usec += thread->user_time % RT_TICK_PER_SECOND * (1000000 / RT_TICK_PER_SECOND); + rt_list_remove(&thread->sibling); + LWP_UNLOCK(lwp); + lwp_futex_exit_robust_list(thread); + /** * Note: the tid tree always hold a reference to thread, hence the tid must * be release before cleanup of thread @@ -479,10 +549,6 @@ void _thread_exit(rt_lwp_t lwp, rt_thread_t thread) lwp_tid_put(thread->tid); thread->tid = 0; - LWP_LOCK(lwp); - rt_list_remove(&thread->sibling); - LWP_UNLOCK(lwp); - rt_thread_delete(thread); rt_schedule(); while (1) ; @@ -497,11 +563,11 @@ rt_inline void _clear_child_tid(rt_thread_t thread) thread->clear_child_tid = RT_NULL; lwp_put_to_user(clear_child_tid, &t, sizeof t); - sys_futex(clear_child_tid, FUTEX_WAKE | FUTEX_PRIVATE, 1, RT_NULL, RT_NULL, 0); + sys_futex(clear_child_tid, FUTEX_WAKE, 1, RT_NULL, RT_NULL, 0); } } -void lwp_exit(rt_lwp_t lwp, rt_base_t status) +void lwp_exit(rt_lwp_t lwp, lwp_status_t status) { rt_thread_t thread; @@ -523,7 +589,7 @@ void lwp_exit(rt_lwp_t lwp, rt_base_t status) * Brief: only one thread should calls exit_group(), * but we can not ensured that during run-time */ - lwp->lwp_ret = LWP_CREATE_STAT(status); + lwp->lwp_status = status; LWP_UNLOCK(lwp); lwp_terminate(lwp); @@ -550,7 +616,7 @@ void lwp_exit(rt_lwp_t lwp, rt_base_t status) _thread_exit(lwp, thread); } -void lwp_thread_exit(rt_thread_t thread, rt_base_t status) +void lwp_thread_exit(rt_thread_t thread, int status) { rt_thread_t header_thr; struct rt_lwp *lwp; @@ -568,7 +634,11 @@ void lwp_thread_exit(rt_thread_t thread, rt_base_t status) header_thr = rt_list_entry(lwp->t_grp.prev, struct rt_thread, sibling); if (header_thr == thread && thread->sibling.prev == &lwp->t_grp) { - lwp->lwp_ret = LWP_CREATE_STAT(status); + /** + * if thread exit, treated as process exit normally. + * This is reasonable since trap event is exited through lwp_exit() + */ + lwp->lwp_status = LWP_CREATE_STAT_EXIT(status); LWP_UNLOCK(lwp); lwp_terminate(lwp); @@ -582,38 +652,6 @@ void lwp_thread_exit(rt_thread_t thread, rt_base_t status) _thread_exit(lwp, thread); } -static void _pop_tty(rt_lwp_t lwp) -{ - if (!lwp->background) - { - struct termios *old_stdin_termios = get_old_termios(); - struct rt_lwp *old_lwp = NULL; - - if (lwp->session == -1) - { - tcsetattr(1, 0, old_stdin_termios); - } - if (lwp->tty != RT_NULL) - { - rt_mutex_take(&lwp->tty->lock, RT_WAITING_FOREVER); - if (lwp->tty->foreground == lwp) - { - old_lwp = tty_pop(&lwp->tty->head, RT_NULL); - lwp->tty->foreground = old_lwp; - } - else - { - tty_pop(&lwp->tty->head, lwp); - } - rt_mutex_release(&lwp->tty->lock); - - LWP_LOCK(lwp); - lwp->tty = RT_NULL; - LWP_UNLOCK(lwp); - } - } -} - /** @note the reference is not for synchronization, but for the release of resource. the synchronization is done through lwp & pid lock */ int lwp_ref_inc(struct rt_lwp *lwp) { @@ -657,7 +695,7 @@ int lwp_ref_dec(struct rt_lwp *lwp) return ref; } -struct rt_lwp* lwp_from_pid_locked(pid_t pid) +struct rt_lwp* lwp_from_pid_raw_locked(pid_t pid) { struct lwp_avl_struct *p; struct rt_lwp *lwp = RT_NULL; @@ -671,6 +709,13 @@ struct rt_lwp* lwp_from_pid_locked(pid_t pid) return lwp; } +struct rt_lwp* lwp_from_pid_locked(pid_t pid) +{ + struct rt_lwp* lwp; + lwp = pid ? lwp_from_pid_raw_locked(pid) : lwp_self(); + return lwp; +} + pid_t lwp_to_pid(struct rt_lwp* lwp) { if (!lwp) @@ -733,162 +778,377 @@ pid_t lwp_name2pid(const char *name) int lwp_getpid(void) { - return ((struct rt_lwp *)rt_thread_self()->lwp)->pid; + rt_lwp_t lwp = lwp_self(); + return lwp ? lwp->pid : 1; + // return ((struct rt_lwp *)rt_thread_self()->lwp)->pid; } -/** - * @brief Wait for a child lwp to terminate. Do the essential recycling. Setup - * status code for user - */ -static sysret_t _lwp_wait_and_recycle(struct rt_lwp *child, rt_thread_t cur_thr, - struct rt_lwp *self_lwp, int *status, - int options) +rt_inline void _update_ru(struct rt_lwp *child, struct rt_lwp *self_lwp, struct rusage *uru) +{ + struct rusage rt_rusage; + if (uru != RT_NULL) + { + rt_rusage.ru_stime.tv_sec = child->rt_rusage.ru_stime.tv_sec; + rt_rusage.ru_stime.tv_usec = child->rt_rusage.ru_stime.tv_usec; + rt_rusage.ru_utime.tv_sec = child->rt_rusage.ru_utime.tv_sec; + rt_rusage.ru_utime.tv_usec = child->rt_rusage.ru_utime.tv_usec; + lwp_data_put(self_lwp, uru, &rt_rusage, sizeof(*uru)); + } +} + +/* do statistical summary and reap the child if neccessary */ +static rt_err_t _stats_and_reap_child(rt_lwp_t child, rt_thread_t cur_thr, + struct rt_lwp *self_lwp, int *ustatus, + int options, struct rusage *uru) { - sysret_t error; - int lwp_stat; - int terminated; + int lwp_stat = child->lwp_status; - if (!child) + /* report statistical data to process */ + _update_ru(child, self_lwp, uru); + + if (child->terminated && !(options & WNOWAIT)) + { + /** Reap the child process if it's exited */ + LOG_D("func %s: child detached", __func__); + lwp_pid_put(child); + lwp_children_unregister(self_lwp, child); + } + + if (ustatus) + lwp_data_put(self_lwp, ustatus, &lwp_stat, sizeof(*ustatus)); + + return RT_EOK; +} + +#define HAS_CHILD_BUT_NO_EVT (-1024) + +/* check if the process is already terminate */ +static sysret_t _query_event_from_lwp(rt_lwp_t child, rt_thread_t cur_thr, rt_lwp_t self_lwp, + int options, int *status) +{ + sysret_t rc; + + LWP_LOCK(child); + if (child->terminated) + { + rc = child->pid; + } + else if ((options & WSTOPPED) && child->jobctl_stopped && !child->wait_reap_stp) { - error = -RT_ERROR; + child->wait_reap_stp = 1; + rc = child->pid; } else + { + rc = HAS_CHILD_BUT_NO_EVT; + } + LWP_UNLOCK(child); + + LOG_D("%s(child_pid=%d ('%s'), stopped=%d) => %d", __func__, child->pid, child->cmd, child->jobctl_stopped, rc); + return rc; +} + +/* verify if the process is child, and reap it */ +static pid_t _verify_child_and_reap(rt_thread_t cur_thr, rt_lwp_t self_lwp, + pid_t wait_pid, int options, int *ustatus, + struct rusage *uru) +{ + sysret_t rc; + struct rt_lwp *child; + + /* check if pid is reference to a valid child */ + lwp_pid_lock_take(); + child = lwp_from_pid_locked(wait_pid); + if (!child) + rc = -EINVAL; + else if (child->parent != self_lwp) + rc = -ESRCH; + else + rc = wait_pid; + + lwp_pid_lock_release(); + + if (rc > 0) + { + rc = _query_event_from_lwp(child, cur_thr, self_lwp, options, ustatus); + if (rc > 0) + { + _stats_and_reap_child(child, cur_thr, self_lwp, ustatus, options, uru); + } + } + return rc; +} + +/* try to reap any child */ +static pid_t _reap_any_child_pid(rt_thread_t cur_thr, rt_lwp_t self_lwp, pid_t pair_pgid, + int options, int *ustatus, struct rusage *uru) +{ + sysret_t rc = -ECHILD; + struct rt_lwp *child; + + LWP_LOCK(self_lwp); + child = self_lwp->first_child; + + /* find a exited child if any */ + while (child) + { + if (pair_pgid && child->pgid != pair_pgid) + continue; + + rc = _query_event_from_lwp(child, cur_thr, self_lwp, options, ustatus); + if (rc > 0) + break; + + child = child->sibling; + } + LWP_UNLOCK(self_lwp); + + if (rc > 0) + { + _stats_and_reap_child(child, cur_thr, self_lwp, ustatus, options, uru); + } + return rc; +} + +rt_err_t lwp_waitpid_kick(rt_lwp_t parent, rt_lwp_t self_lwp) +{ + /* waker provide the message mainly through its lwp_status */ + rt_wqueue_wakeup(&parent->waitpid_waiters, self_lwp); + return RT_EOK; +} + +struct waitpid_handle { + struct rt_wqueue_node wq_node; + int options; + rt_lwp_t waker_lwp; +}; + +/* the IPC message is setup and notify the parent */ +static int _waitq_filter(struct rt_wqueue_node *wait_node, void *key) +{ + int can_accept_evt = 0; + rt_thread_t waiter = wait_node->polling_thread; + pid_t destiny = (pid_t)wait_node->key; + rt_lwp_t waker_lwp = key; + struct waitpid_handle *handle; + rt_ubase_t options; + + handle = rt_container_of(wait_node, struct waitpid_handle, wq_node); + + RT_ASSERT(waiter != RT_NULL); + options = handle->options; + + /* filter out if waker is not the one */ + if (destiny > 0) { /** - * Note: Critical Section - * - child lwp (RW. This will modify its parent if valid) + * in waitpid immediately return routine, we already do the check + * that pid is one of the child process of waiting thread */ - LWP_LOCK(child); - if (child->terminated) + can_accept_evt = waker_lwp->pid == destiny; + } + else if (destiny == -1) + { + can_accept_evt = waker_lwp->parent == waiter->lwp; + } + else + { + /* destiny == 0 || destiny == -pgid */ + pid_t waiter_pgid; + if (destiny == 0) { - error = child->pid; + waiter_pgid = lwp_pgid_get_byprocess(waiter->lwp); } - else if (rt_list_isempty(&child->wait_list)) + else { - /** - * Note: only one thread can wait on wait_list. - * dont reschedule before mutex unlock - */ - rt_enter_critical(); + waiter_pgid = -destiny; + } + can_accept_evt = waiter_pgid == lwp_pgid_get_byprocess(waker_lwp); + } - error = rt_thread_suspend_with_flag(cur_thr, RT_INTERRUPTIBLE); - if (error == 0) - { - rt_list_insert_before(&child->wait_list, &RT_THREAD_LIST_NODE(cur_thr)); - LWP_UNLOCK(child); + /* filter out if event is not desired */ + if (can_accept_evt) + { + if ((options & WEXITED) && waker_lwp->terminated) + can_accept_evt = 1; + else if ((options & WSTOPPED) && WIFSTOPPED(waker_lwp->lwp_status)) + can_accept_evt = 1; + else if ((options & WCONTINUED) && WIFCONTINUED(waker_lwp->lwp_status)) + can_accept_evt = 1; + else + can_accept_evt = 0; + } - rt_set_errno(RT_EINTR); - rt_exit_critical(); - rt_schedule(); + /* setup message for waiter if accepted */ + if (can_accept_evt) + handle->waker_lwp = waker_lwp; - /** - * Since parent is holding a reference to children this lock will - * not be freed before parent dereference to it. - */ - LWP_LOCK(child); + /* 0 if event is accepted, otherwise discard */ + return !can_accept_evt; +} - error = rt_get_errno(); - if (error == RT_EINTR) - { - error = -EINTR; - } - else if (error != RT_EOK) - { - LOG_W("%s: unexpected error code %ld", __func__, error); - } - else - { - error = child->pid; - } - } - else - rt_exit_critical(); - } - else - error = -RT_EINTR; +/* the waiter cleanup IPC message and wait for desired event here */ +static rt_err_t _wait_for_event(rt_thread_t cur_thr, rt_lwp_t self_lwp, + struct waitpid_handle *handle, pid_t destiny) +{ + rt_err_t ret; - lwp_stat = child->lwp_ret; - terminated = child->terminated; - LWP_UNLOCK(child); + /* current context checking */ + RT_DEBUG_SCHEDULER_AVAILABLE(RT_TRUE); - if (error > 0) - { - if (terminated) - { - LOG_D("func %s: child detached", __func__); - /** Reap the child process if it's exited */ - lwp_pid_put(child); - lwp_children_unregister(self_lwp, child); - } + handle->wq_node.polling_thread = cur_thr; + handle->wq_node.key = destiny; + handle->wq_node.wakeup = _waitq_filter; + handle->wq_node.wqueue = &self_lwp->waitpid_waiters; + rt_list_init(&handle->wq_node.list); - if (status) - lwp_data_put(self_lwp, status, &lwp_stat, sizeof(*status)); - } + cur_thr->error = RT_EOK; + + LOG_D("%s(self_lwp=%d) wait for event", __func__, self_lwp->pid); + + rt_enter_critical(); + ret = rt_thread_suspend_with_flag(cur_thr, RT_INTERRUPTIBLE); + if (ret == RT_EOK) + { + rt_wqueue_add(handle->wq_node.wqueue, &handle->wq_node); + rt_exit_critical(); + + rt_schedule(); + + ret = cur_thr->error; + + /** + * cur_thr error is a positive value, but some legacy implementation + * use a negative one. So we check to avoid errors + */ + ret = ret > 0 ? -ret : ret; + + /** + * we dont rely on this actually, but we cleanup it since wakeup API + * set this up durint operation, and this will cause some messy condition + */ + handle->wq_node.wqueue->flag = RT_WQ_FLAG_CLEAN; + rt_wqueue_remove(&handle->wq_node); + } + else + { + /* failed to suspend, return immediately with failure */ + rt_exit_critical(); } - return error; + return ret; } -pid_t waitpid(pid_t pid, int *status, int options) __attribute__((alias("lwp_waitpid"))); +/* wait for IPC event and do the cleanup if neccessary */ +static sysret_t _wait_and_reap(rt_thread_t cur_thr, rt_lwp_t self_lwp, const pid_t pid, + int options, int *ustatus, struct rusage *uru) +{ + sysret_t rc; + struct waitpid_handle handle; + rt_lwp_t waker; + + /* wait for SIGCHLD or other async events */ + handle.options = options; + handle.waker_lwp = 0; + rc = _wait_for_event(cur_thr, self_lwp, &handle, pid); + + waker = handle.waker_lwp; + if (waker != RT_NULL) + { + rc = waker->pid; + + /* check out if any process exited */ + LOG_D("%s: woken up by lwp=%d", __func__, waker->pid); + _stats_and_reap_child(waker, cur_thr, self_lwp, ustatus, options, uru); + } + /** + * else if (rc != RT_EOK) + * unable to do a suspend, or wakeup unexpectedly + * -> then returned a failure + */ + + return rc; +} -pid_t lwp_waitpid(const pid_t pid, int *status, int options) +pid_t lwp_waitpid(const pid_t pid, int *status, int options, struct rusage *ru) { pid_t rc = -1; - struct rt_thread *thread; - struct rt_lwp *child; + struct rt_thread *cur_thr; struct rt_lwp *self_lwp; - thread = rt_thread_self(); + cur_thr = rt_thread_self(); self_lwp = lwp_self(); - if (!self_lwp) + if (!cur_thr || !self_lwp) { - rc = -RT_EINVAL; + rc = -EINVAL; } else { + /* check if able to reap desired child immediately */ if (pid > 0) { - lwp_pid_lock_take(); - child = lwp_from_pid_locked(pid); - if (child->parent != self_lwp) - rc = -RT_ERROR; - else - rc = RT_EOK; - lwp_pid_lock_release(); - - if (rc == RT_EOK) - rc = _lwp_wait_and_recycle(child, thread, self_lwp, status, options); + /* if pid is child then try to reap it */ + rc = _verify_child_and_reap(cur_thr, self_lwp, pid, options, status, ru); } else if (pid == -1) { - LWP_LOCK(self_lwp); - child = self_lwp->first_child; - LWP_UNLOCK(self_lwp); - RT_ASSERT(!child || child->parent == self_lwp); - - rc = _lwp_wait_and_recycle(child, thread, self_lwp, status, options); + /* any terminated child */ + rc = _reap_any_child_pid(cur_thr, self_lwp, 0, options, status, ru); } else { - /* not supported yet */ - rc = -RT_EINVAL; + /** + * (pid < -1 || pid == 0) + * any terminated child with matched pgid + */ + + pid_t pair_pgid; + if (pid == 0) + { + pair_pgid = lwp_pgid_get_byprocess(self_lwp); + } + else + { + pair_pgid = -pid; + } + rc = _reap_any_child_pid(cur_thr, self_lwp, pair_pgid, options, status, ru); } - } - if (rc > 0) - { - LOG_D("%s: recycle child id %ld (status=0x%x)", __func__, (long)rc, status ? *status : 0); - } - else - { - RT_ASSERT(rc != 0); - LOG_D("%s: wait failed with code %ld", __func__, (long)rc); + if (rc == HAS_CHILD_BUT_NO_EVT) + { + if (!(options & WNOHANG)) + { + /* otherwise, arrange a suspend and wait for async event */ + options |= WEXITED; + rc = _wait_and_reap(cur_thr, self_lwp, pid, options, status, ru); + } + else + { + /** + * POSIX.1: If waitpid() was invoked with WNOHANG set in options, + * it has at least one child process specified by pid for which + * status is not available, and status is not available for any + * process specified by pid, 0 is returned + */ + rc = 0; + } + } + else + { + RT_ASSERT(rc != 0); + } } + LOG_D("waitpid() => %d, *status=0x%x", rc, status ? *status:0); return rc; } +pid_t waitpid(pid_t pid, int *status, int options) +{ + return lwp_waitpid(pid, status, options, RT_NULL); +} + #ifdef RT_USING_FINSH /* copy from components/finsh/cmd.c */ static void object_split(int len) @@ -910,7 +1170,7 @@ static void print_thread_info(struct rt_thread* thread, int maxlen) else rt_kprintf("%-*.*s N/A %3d ", maxlen, RT_NAME_MAX, thread->parent.name, RT_SCHED_PRIV(thread).current_priority); #else - rt_kprintf("%-*.*s %3d ", maxlen, RT_NAME_MAX, thread->parent.name, thread->current_priority); + rt_kprintf("%-*.*s %3d ", maxlen, RT_NAME_MAX, thread->parent.name, RT_SCHED_PRIV(thread).current_priority); #endif /*RT_USING_SMP*/ stat = (RT_SCHED_CTX(thread).stat & RT_THREAD_STAT_MASK); @@ -1044,7 +1304,7 @@ static void cmd_kill(int argc, char** argv) } } lwp_pid_lock_take(); - lwp_signal_kill(lwp_from_pid_locked(pid), sig, SI_USER, 0); + lwp_signal_kill(lwp_from_pid_raw_locked(pid), sig, SI_USER, 0); lwp_pid_lock_release(); } MSH_CMD_EXPORT_ALIAS(cmd_kill, kill, send a signal to a process); @@ -1061,7 +1321,7 @@ static void cmd_killall(int argc, char** argv) while((pid = lwp_name2pid(argv[1])) > 0) { lwp_pid_lock_take(); - lwp_signal_kill(lwp_from_pid_locked(pid), SIGKILL, SI_USER, 0); + lwp_signal_kill(lwp_from_pid_raw_locked(pid), SIGKILL, SI_USER, 0); lwp_pid_lock_release(); rt_thread_mdelay(100); } @@ -1073,15 +1333,15 @@ MSH_CMD_EXPORT_ALIAS(cmd_killall, killall, kill processes by name); int lwp_check_exit_request(void) { rt_thread_t thread = rt_thread_self(); - rt_base_t expected = LWP_EXIT_REQUEST_TRIGGERED; + rt_size_t expected = LWP_EXIT_REQUEST_TRIGGERED; if (!thread->lwp) { return 0; } - return rt_atomic_compare_exchange_strong(&thread->exit_request, &expected, - LWP_EXIT_REQUEST_IN_PROCESS); + return atomic_compare_exchange_strong(&thread->exit_request, &expected, + LWP_EXIT_REQUEST_IN_PROCESS); } static void _wait_sibling_exit(rt_lwp_t lwp, rt_thread_t curr_thread); @@ -1119,7 +1379,7 @@ static void _wait_sibling_exit(rt_lwp_t lwp, rt_thread_t curr_thread) rt_sched_lock_level_t slvl; rt_list_t *list; rt_thread_t thread; - rt_base_t expected = LWP_EXIT_REQUEST_NONE; + rt_size_t expected = LWP_EXIT_REQUEST_NONE; /* broadcast exit request for sibling threads */ LWP_LOCK(lwp); @@ -1127,8 +1387,8 @@ static void _wait_sibling_exit(rt_lwp_t lwp, rt_thread_t curr_thread) { thread = rt_list_entry(list, struct rt_thread, sibling); - rt_atomic_compare_exchange_strong(&thread->exit_request, &expected, - LWP_EXIT_REQUEST_TRIGGERED); + atomic_compare_exchange_strong(&thread->exit_request, &expected, + LWP_EXIT_REQUEST_TRIGGERED); rt_sched_lock(&slvl); /* dont release, otherwise thread may have been freed */ @@ -1213,8 +1473,43 @@ static void _wait_sibling_exit(rt_lwp_t lwp, rt_thread_t curr_thread) } } +static void _notify_parent(rt_lwp_t lwp) +{ + int si_code; + int signo_or_exitcode; + lwp_siginfo_ext_t ext; + lwp_status_t lwp_status = lwp->lwp_status; + rt_lwp_t parent = lwp->parent; + + if (WIFSIGNALED(lwp_status)) + { + si_code = (lwp_status & LWP_COREDUMP_FLAG) ? CLD_DUMPED : CLD_KILLED; + signo_or_exitcode = WTERMSIG(lwp_status); + } + else + { + si_code = CLD_EXITED; + signo_or_exitcode = WEXITSTATUS(lwp->lwp_status); + } + + lwp_waitpid_kick(parent, lwp); + + ext = rt_malloc(sizeof(struct lwp_siginfo)); + + if (ext) + { + rt_thread_t cur_thr = rt_thread_self(); + ext->sigchld.status = signo_or_exitcode; + ext->sigchld.stime = cur_thr->system_time; + ext->sigchld.utime = cur_thr->user_time; + } + lwp_signal_kill(parent, SIGCHLD, si_code, ext); +} + static void _resr_cleanup(struct rt_lwp *lwp) { + lwp_jobctrl_on_exit(lwp); + LWP_LOCK(lwp); lwp_signal_detach(&lwp->signal); @@ -1254,8 +1549,6 @@ static void _resr_cleanup(struct rt_lwp *lwp) } LWP_UNLOCK(lwp); - _pop_tty(lwp); - /** * @brief Wakeup parent if it's waiting for this lwp, otherwise a signal * will be sent to parent @@ -1264,29 +1557,26 @@ static void _resr_cleanup(struct rt_lwp *lwp) * - the parent lwp (RW.) */ LWP_LOCK(lwp); - if (lwp->parent) + if (lwp->parent && + !lwp_sigismember(&lwp->parent->signal.sig_action_nocldwait, SIGCHLD)) { - struct rt_thread *thread; - + /* if successfully race to setup lwp->terminated before parent detach */ LWP_UNLOCK(lwp); - if (!rt_list_isempty(&lwp->wait_list)) - { - thread = RT_THREAD_LIST_NODE_ENTRY(lwp->wait_list.next); - thread->error = RT_EOK; - thread->msg_ret = (void*)(rt_size_t)lwp->lwp_ret; - rt_thread_resume(thread); - } - else - { - /* children cannot detach itself and must wait for parent to take care of it */ - lwp_signal_kill(lwp->parent, SIGCHLD, CLD_EXITED, 0); - } + + /** + * Note: children cannot detach itself and must wait for parent to take + * care of it + */ + _notify_parent(lwp); } else { LWP_UNLOCK(lwp); - /* INFO: orphan hasn't parents to do the reap of pid */ + /** + * if process is orphan, it doesn't have parent to do the recycling. + * Otherwise, its parent had setup a flag to mask out recycling event + */ lwp_pid_put(lwp); } @@ -1315,10 +1605,8 @@ static int _lwp_setaffinity(pid_t pid, int cpu) int ret = -1; lwp_pid_lock_take(); - if(pid == 0) - lwp = lwp_self(); - else - lwp = lwp_from_pid_locked(pid); + lwp = lwp_from_pid_locked(pid); + if (lwp) { #ifdef RT_USING_SMP diff --git a/components/lwp/lwp_pid.h b/components/lwp/lwp_pid.h index c9e8b945b73..5e170f652da 100644 --- a/components/lwp/lwp_pid.h +++ b/components/lwp/lwp_pid.h @@ -11,14 +11,14 @@ #ifndef LWP_PID_H__ #define LWP_PID_H__ -#include "lwp.h" - #ifdef __cplusplus extern "C" { #endif -#define LWP_CREATE_FLAG_NONE 0x0000 -#define LWP_CREATE_FLAG_ALLOC_PID 0x0001 /* allocate pid on lwp object create */ +#define LWP_CREATE_FLAG_NONE 0x0000 +#define LWP_CREATE_FLAG_ALLOC_PID 0x0001 /* allocate pid on lwp object create */ +#define LWP_CREATE_FLAG_INIT_USPACE 0x0002 /* do user space initialization */ +#define LWP_CREATE_FLAG_NOTRACE_EXEC 0x0004 /* not trace if execve() after fork() */ struct rt_lwp; @@ -46,6 +46,7 @@ void lwp_free(struct rt_lwp* lwp); int lwp_ref_inc(struct rt_lwp *lwp); int lwp_ref_dec(struct rt_lwp *lwp); +struct rt_lwp* lwp_from_pid_raw_locked(pid_t pid); struct rt_lwp* lwp_from_pid_locked(pid_t pid); pid_t lwp_to_pid(struct rt_lwp* lwp); @@ -54,7 +55,29 @@ char* lwp_pid2name(int32_t pid); int lwp_getpid(void); -pid_t lwp_waitpid(const pid_t pid, int *status, int options); +struct rusage +{ + struct timeval ru_utime; + struct timeval ru_stime; + + long ru_maxrss; + long ru_ixrss; + long ru_idrss; + long ru_isrss; + long ru_minflt; + long ru_majflt; + long ru_nswap; + long ru_inblock; + long ru_oublock; + long ru_msgsnd; + long ru_msgrcv; + long ru_nsignals; + long ru_nvcsw; + long ru_nivcsw; + long reserved[16]; +}; +pid_t lwp_waitpid(const pid_t pid, int *status, int options, struct rusage *ru); +rt_err_t lwp_waitpid_kick(struct rt_lwp *parent, struct rt_lwp *self_lwp); pid_t waitpid(pid_t pid, int *status, int options); long list_process(void); @@ -85,8 +108,9 @@ rt_inline void lwp_from_pid_release_lock(struct rt_lwp *lwp) lwp_ref_dec(lwp); } -void lwp_thread_exit(rt_thread_t thread, rt_base_t status); -void lwp_exit(struct rt_lwp *lwp, rt_base_t status); +typedef rt_base_t lwp_status_t; +void lwp_thread_exit(rt_thread_t thread, int status); +void lwp_exit(struct rt_lwp *lwp, lwp_status_t status); #ifdef __cplusplus } diff --git a/components/lwp/lwp_pmutex.c b/components/lwp/lwp_pmutex.c deleted file mode 100644 index 08c8b3b0827..00000000000 --- a/components/lwp/lwp_pmutex.c +++ /dev/null @@ -1,459 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021/01/02 bernard the first version - * 2022/12/18 bernard fix the _m_lock to tid in user land. - */ - -#include "lwp_internal.h" -#include -#ifdef ARCH_MM_MMU -#include -#endif -#include -#include - -#define PMUTEX_NORMAL 0 /* Unable to recursion */ -#define PMUTEX_RECURSIVE 1 /* Can be recursion */ -#define PMUTEX_ERRORCHECK 2 /* This type of mutex provides error checking */ - -struct rt_pmutex -{ - union - { - rt_mutex_t kmutex; - rt_sem_t ksem; /* use sem to emulate the mutex without recursive */ - } lock; - - struct lwp_avl_struct node; - struct rt_object *custom_obj; - rt_uint8_t type; /* pmutex type */ -}; - -/* - * userspace mutex definitions in musl - */ -struct rt_umutex -{ - union - { - int __i[6]; - volatile int __vi[6]; - volatile void *volatile __p[6]; - } __u; -}; -#define _m_type __u.__i[0] -#define _m_lock __u.__vi[1] -#define _m_waiters __u.__vi[2] -#define _m_prev __u.__p[3] -#define _m_next __u.__p[4] -#define _m_count __u.__i[5] - -static struct rt_mutex _pmutex_lock; - -static int pmutex_system_init(void) -{ - rt_mutex_init(&_pmutex_lock, "pmtxLock", RT_IPC_FLAG_FIFO); - return 0; -} -INIT_PREV_EXPORT(pmutex_system_init); - -static rt_err_t pmutex_destory(void *data) -{ - rt_err_t ret = -1; - struct rt_pmutex *pmutex = (struct rt_pmutex *)data; - - if (pmutex) - { - lwp_mutex_take_safe(&_pmutex_lock, RT_WAITING_FOREVER, 0); - /* remove pmutex from pmutext avl */ - lwp_avl_remove(&pmutex->node, (struct lwp_avl_struct **)pmutex->node.data); - lwp_mutex_release_safe(&_pmutex_lock); - - if (pmutex->type == PMUTEX_NORMAL) - { - rt_sem_delete(pmutex->lock.ksem); - } - else - { - rt_mutex_delete(pmutex->lock.kmutex); - } - - /* release object */ - rt_free(pmutex); - ret = 0; - } - return ret; -} - -static struct rt_pmutex* pmutex_create(void *umutex, struct rt_lwp *lwp) -{ - struct rt_pmutex *pmutex = RT_NULL; - struct rt_object *obj = RT_NULL; - rt_ubase_t type; - - if (!lwp) - { - return RT_NULL; - } - - long *p = (long *)umutex; - /* umutex[0] bit[0-1] saved mutex type */ - type = *p & 3; - if (type != PMUTEX_NORMAL && type != PMUTEX_RECURSIVE && type != PMUTEX_ERRORCHECK) - { - return RT_NULL; - } - - pmutex = (struct rt_pmutex *)rt_malloc(sizeof(struct rt_pmutex)); - if (!pmutex) - { - return RT_NULL; - } - - if (type == PMUTEX_NORMAL) - { - pmutex->lock.ksem = rt_sem_create("pmutex", 1, RT_IPC_FLAG_PRIO); - if (!pmutex->lock.ksem) - { - rt_free(pmutex); - return RT_NULL; - } - } - else - { - pmutex->lock.kmutex = rt_mutex_create("pmutex", RT_IPC_FLAG_PRIO); - if (!pmutex->lock.kmutex) - { - rt_free(pmutex); - return RT_NULL; - } - } - - obj = rt_custom_object_create("pmutex", (void *)pmutex, pmutex_destory); - if (!obj) - { - if (pmutex->type == PMUTEX_NORMAL) - { - rt_sem_delete(pmutex->lock.ksem); - } - else - { - rt_mutex_delete(pmutex->lock.kmutex); - } - rt_free(pmutex); - return RT_NULL; - } - pmutex->node.avl_key = (avl_key_t)umutex; - pmutex->node.data = &lwp->address_search_head; - pmutex->custom_obj = obj; - pmutex->type = type; - - /* insert into pmutex head */ - lwp_avl_insert(&pmutex->node, &lwp->address_search_head); - return pmutex; -} - -static struct rt_pmutex* pmutex_get(void *umutex, struct rt_lwp *lwp) -{ - struct rt_pmutex *pmutex = RT_NULL; - struct lwp_avl_struct *node = RT_NULL; - - node = lwp_avl_find((avl_key_t)umutex, lwp->address_search_head); - if (!node) - { - return RT_NULL; - } - pmutex = rt_container_of(node, struct rt_pmutex, node); - return pmutex; -} - -static int _pthread_mutex_init(void *umutex) -{ - struct rt_lwp *lwp = RT_NULL; - struct rt_pmutex *pmutex = RT_NULL; - rt_err_t lock_ret = 0; - - /* umutex union is 6 x (void *) */ - if (!lwp_user_accessable(umutex, sizeof(void *) * 6)) - { - rt_set_errno(EINVAL); - return -EINVAL; - } - - lock_ret = rt_mutex_take_interruptible(&_pmutex_lock, RT_WAITING_FOREVER); - if (lock_ret != RT_EOK) - { - rt_set_errno(EAGAIN); - return -EAGAIN; - } - - lwp = lwp_self(); - pmutex = pmutex_get(umutex, lwp); - if (pmutex == RT_NULL) - { - /* create a pmutex according to this umutex */ - pmutex = pmutex_create(umutex, lwp); - if (pmutex == RT_NULL) - { - rt_mutex_release(&_pmutex_lock); - rt_set_errno(ENOMEM); - return -ENOMEM; - } - if (lwp_user_object_add(lwp, pmutex->custom_obj) != 0) - { - rt_custom_object_destroy(pmutex->custom_obj); - rt_set_errno(ENOMEM); - return -ENOMEM; - } - } - else - { - lwp_mutex_take_safe(&_pmutex_lock, RT_WAITING_FOREVER, 1); - if (pmutex->type == PMUTEX_NORMAL) - { - pmutex->lock.ksem->value = 1; - } - else - { - pmutex->lock.kmutex->owner = RT_NULL; - pmutex->lock.kmutex->priority = 0xFF; - pmutex->lock.kmutex->hold = 0; - pmutex->lock.kmutex->ceiling_priority = 0xFF; - } - lwp_mutex_release_safe(&_pmutex_lock); - } - - rt_mutex_release(&_pmutex_lock); - - return 0; -} - -static int _pthread_mutex_lock_timeout(void *umutex, struct timespec *timeout) -{ - struct rt_lwp *lwp = RT_NULL; - struct rt_pmutex *pmutex = RT_NULL; - struct rt_umutex *umutex_p = (struct rt_umutex*)umutex; - rt_err_t lock_ret = 0; - rt_int32_t time = RT_WAITING_FOREVER; - - if (!lwp_user_accessable((void *)umutex, sizeof(struct rt_umutex))) - { - rt_set_errno(EINVAL); - return -EINVAL; - } - - if (timeout) - { - if (!lwp_user_accessable((void *)timeout, sizeof(struct timespec))) - { - rt_set_errno(EINVAL); - return -EINVAL; - } - time = rt_timespec_to_tick(timeout); - } - - lock_ret = rt_mutex_take_interruptible(&_pmutex_lock, RT_WAITING_FOREVER); - if (lock_ret != RT_EOK) - { - rt_set_errno(EINTR); - return -EINTR; - } - - lwp = lwp_self(); - pmutex = pmutex_get(umutex, lwp); - if (pmutex == RT_NULL) - { - rt_mutex_release(&_pmutex_lock); - rt_set_errno(EINVAL); - return -ENOMEM; /* umutex not recored in kernel */ - } - - rt_mutex_release(&_pmutex_lock); - - switch (pmutex->type) - { - case PMUTEX_NORMAL: - lock_ret = rt_sem_take_interruptible(pmutex->lock.ksem, time); - break; - case PMUTEX_RECURSIVE: - lock_ret = rt_mutex_take_interruptible(pmutex->lock.kmutex, time); - if (lock_ret == RT_EOK) - { - umutex_p->_m_lock = rt_thread_self()->tid; - } - break; - case PMUTEX_ERRORCHECK: - lock_ret = lwp_mutex_take_safe(&_pmutex_lock, RT_WAITING_FOREVER, 1); - if (lock_ret != RT_EOK) - { - return -EINTR; - } - if (pmutex->lock.kmutex->owner == rt_thread_self()) - { - lwp_mutex_release_safe(&_pmutex_lock); - return -EDEADLK; - } - lwp_mutex_release_safe(&_pmutex_lock); - lock_ret = rt_mutex_take_interruptible(pmutex->lock.kmutex, time); - if (lock_ret == RT_EOK) - { - umutex_p->_m_lock = rt_thread_self()->tid; - } - break; - default: /* unknown type */ - return -EINVAL; - } - - if (lock_ret != RT_EOK) - { - if (lock_ret == -RT_ETIMEOUT) - { - if (time == 0) /* timeout is 0, means try lock failed */ - { - rt_set_errno(EBUSY); - return -EBUSY; - } - else - { - rt_set_errno(ETIMEDOUT); - return -ETIMEDOUT; - } - } - else if (lock_ret == -RT_EINTR) - { - rt_set_errno(EINTR); - return -EINTR; - } - else - { - rt_set_errno(EAGAIN); - return -EAGAIN; - } - } - return 0; -} - -static int _pthread_mutex_unlock(void *umutex) -{ - rt_err_t lock_ret = 0; - struct rt_lwp *lwp = RT_NULL; - struct rt_pmutex *pmutex = RT_NULL; - struct rt_umutex *umutex_p = (struct rt_umutex*)umutex; - - lock_ret = rt_mutex_take_interruptible(&_pmutex_lock, RT_WAITING_FOREVER); - if (lock_ret != RT_EOK) - { - rt_set_errno(EAGAIN); - return -EAGAIN; - } - - lwp = lwp_self(); - pmutex = pmutex_get(umutex, lwp); - if (pmutex == RT_NULL) - { - rt_mutex_release(&_pmutex_lock); - rt_set_errno(EPERM); - return -EPERM;//unlock static mutex of unlock state - } - - rt_mutex_release(&_pmutex_lock); - - switch (pmutex->type) - { - case PMUTEX_NORMAL: - if(pmutex->lock.ksem->value >=1) - { - rt_set_errno(EPERM); - return -EPERM;//unlock dynamic mutex of unlock state - } - else - { - lock_ret = rt_sem_release(pmutex->lock.ksem); - } - break; - case PMUTEX_RECURSIVE: - case PMUTEX_ERRORCHECK: - lock_ret = rt_mutex_release(pmutex->lock.kmutex); - if ((lock_ret == RT_EOK) && pmutex->lock.kmutex->owner == NULL) - { - umutex_p->_m_lock = 0; - } - break; - default: /* unknown type */ - return -EINVAL; - } - - if (lock_ret != RT_EOK) - { - rt_set_errno(EPERM); - return -EPERM; - } - return 0; -} - -static int _pthread_mutex_destroy(void *umutex) -{ - struct rt_lwp *lwp = RT_NULL; - struct rt_pmutex *pmutex = RT_NULL; - rt_err_t lock_ret = 0; - - lock_ret = rt_mutex_take_interruptible(&_pmutex_lock, RT_WAITING_FOREVER); - if (lock_ret != RT_EOK) - { - rt_set_errno(EAGAIN); - return -EAGAIN; - } - - lwp = lwp_self(); - pmutex = pmutex_get(umutex, lwp); - if (pmutex == RT_NULL) - { - rt_mutex_release(&_pmutex_lock); - rt_set_errno(EINVAL); - return -EINVAL; - } - - lwp_user_object_delete(lwp, pmutex->custom_obj); - rt_mutex_release(&_pmutex_lock); - - return 0; -} - -sysret_t sys_pmutex(void *umutex, int op, void *arg) -{ - int ret = -EINVAL; - - switch (op) - { - case PMUTEX_INIT: - ret = _pthread_mutex_init(umutex); - break; - case PMUTEX_LOCK: - ret = _pthread_mutex_lock_timeout(umutex, (struct timespec*)arg); - if (ret == -ENOMEM) - { - /* lock not init, try init it and lock again. */ - ret = _pthread_mutex_init(umutex); - if (ret == 0) - { - ret = _pthread_mutex_lock_timeout(umutex, (struct timespec*)arg); - } - } - break; - case PMUTEX_UNLOCK: - ret = _pthread_mutex_unlock(umutex); - break; - case PMUTEX_DESTROY: - ret = _pthread_mutex_destroy(umutex); - break; - default: - rt_set_errno(EINVAL); - break; - } - return ret; -} diff --git a/components/lwp/lwp_session.c b/components/lwp/lwp_session.c new file mode 100644 index 00000000000..6d51948267d --- /dev/null +++ b/components/lwp/lwp_session.c @@ -0,0 +1,432 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-17 xqyjlj the first version + * 2023-11-29 Shell Add direct reference of sess for group + */ + +#include "lwp.h" +#include "lwp_internal.h" +#include "lwp_syscall.h" +#include "terminal/terminal.h" + +#define DBG_TAG "lwp.session" +#define DBG_LVL DBG_WARNING +#include + +rt_session_t lwp_session_find(pid_t sid) +{ + rt_base_t level; + rt_session_t session = RT_NULL; + rt_list_t *node = RT_NULL; + struct rt_object_information *information = RT_NULL; + + information = rt_object_get_information(RT_Object_Class_Session); + + /* parameter check */ + if ((sid < 0) || (information == RT_NULL)) + { + return RT_NULL; + } + + if (sid == 0) + { + sid = lwp_getpid(); + } + + /* enter critical */ + level = rt_spin_lock_irqsave(&(information->spinlock)); + + /* try to find session */ + rt_list_for_each(node, &(information->object_list)) + { + session = (rt_session_t)rt_list_entry(node, struct rt_object, list); + if (session->sid == sid) + { + rt_spin_unlock_irqrestore(&(information->spinlock), level); + + return session; + } + } + + rt_spin_unlock_irqrestore(&(information->spinlock), level); + + return RT_NULL; +} + +rt_session_t lwp_session_create(rt_lwp_t leader) +{ + rt_session_t session = RT_NULL; + + /* parameter check */ + if (leader == RT_NULL) + { + return RT_NULL; + } + + session = rt_malloc(sizeof(struct rt_session)); + if (session != RT_NULL) + { + rt_object_init(&(session->object), RT_Object_Class_Session, "session"); + rt_list_init(&(session->processgroup)); + rt_mutex_init(&(session->mutex), "session", RT_IPC_FLAG_PRIO); + session->leader = leader; + session->sid = leader->pid; + lwp_pgrp_update_children_info(leader->pgrp, session->sid, leader->pgid); + session->foreground_pgid = session->sid; + session->ctty = RT_NULL; + } + return session; +} + +int lwp_session_delete(rt_session_t session) +{ + int retry = 1; + lwp_tty_t ctty; + + /* parameter check */ + if (session == RT_NULL) + { + return -EINVAL; + } + + /* clear children sid */ + lwp_session_update_children_info(session, 0); + + while (retry) + { + retry = 0; + ctty = session->ctty; + SESS_LOCK_NESTED(session); + + if (session->ctty == ctty) + { + if (ctty) + { + SESS_UNLOCK(session); + + /** + * Note: it's safe to release the session lock now. Even if someone + * race to acquire the tty, it's safe under protection of tty_lock() + * and the check inside + */ + tty_lock(ctty); + tty_rel_sess(ctty, session); + session->ctty = RT_NULL; + } + else + { + SESS_UNLOCK(session); + } + } + else + { + SESS_UNLOCK(session); + retry = 1; + } + } + + rt_object_detach(&(session->object)); + rt_mutex_detach(&(session->mutex)); + rt_free(session); + + return 0; +} + +int lwp_session_insert(rt_session_t session, rt_processgroup_t group) +{ + /* parameter check */ + if (session == RT_NULL || group == RT_NULL) + { + return -EINVAL; + } + + SESS_LOCK_NESTED(session); + PGRP_LOCK_NESTED(group); + + group->sid = session->sid; + group->session = session; + lwp_pgrp_update_children_info(group, session->sid, group->pgid); + rt_list_insert_after(&(session->processgroup), &(group->pgrp_list_node)); + + PGRP_UNLOCK(group); + SESS_UNLOCK(session); + + return 0; +} + +int lwp_session_remove(rt_session_t session, rt_processgroup_t group) +{ + rt_bool_t is_empty = RT_FALSE; + + /* parameter check */ + if (session == RT_NULL || group == RT_NULL) + { + return -EINVAL; + } + + SESS_LOCK_NESTED(session); + PGRP_LOCK_NESTED(group); + + rt_list_remove(&(group->pgrp_list_node)); + /* clear children sid */ + lwp_pgrp_update_children_info(group, 0, group->pgid); + group->sid = 0; + group->session = RT_NULL; + + PGRP_UNLOCK(group); + + is_empty = rt_list_isempty(&(session->processgroup)); + + SESS_UNLOCK(session); + + if (is_empty) + { + lwp_session_delete(session); + return 1; + } + + return 0; +} + +int lwp_session_move(rt_session_t session, rt_processgroup_t group) +{ + rt_session_t prev_session; + + /* parameter check */ + if (session == RT_NULL || group == RT_NULL) + { + return -EINVAL; + } + + if (lwp_sid_get_bysession(session) == lwp_sid_get_bypgrp(group)) + { + return 0; + } + + SESS_LOCK(session); + + prev_session = group->session; + if (prev_session) + { + SESS_LOCK(prev_session); + lwp_session_remove(prev_session, group); + SESS_UNLOCK(prev_session); + } + + lwp_session_insert(session, group); + + SESS_UNLOCK(session); + + return 0; +} + +int lwp_session_update_children_info(rt_session_t session, pid_t sid) +{ + rt_list_t *node = RT_NULL; + rt_processgroup_t group = RT_NULL; + + if (session == RT_NULL) + { + return -EINVAL; + } + + SESS_LOCK_NESTED(session); + + rt_list_for_each(node, &(session->processgroup)) + { + group = (rt_processgroup_t)rt_list_entry(node, struct rt_processgroup, pgrp_list_node); + PGRP_LOCK_NESTED(group); + if (sid != -1) + { + group->sid = sid; + group->session = session; + lwp_pgrp_update_children_info(group, sid, group->pgid); + } + PGRP_UNLOCK(group); + } + + SESS_UNLOCK(session); + return 0; +} + +int lwp_session_set_foreground(rt_session_t session, pid_t pgid) +{ + rt_processgroup_t group = RT_NULL; + rt_list_t *node = RT_NULL; + rt_bool_t is_contains = RT_FALSE; + + /* parameter check */ + if (session == RT_NULL || pgid <= 0) + { + return -EINVAL; + } + + SESS_LOCK(session); + + rt_list_for_each(node, &(session->processgroup)) + { + group = (rt_processgroup_t)rt_list_entry(node, struct rt_processgroup, pgrp_list_node); + PGRP_LOCK(group); + if (group->pgid == pgid) + { + is_contains = RT_TRUE; + } + PGRP_UNLOCK(group); + } + + if (is_contains) + { + session->foreground_pgid = pgid; + // TODO: maybe notify tty + } + + SESS_UNLOCK(session); + + return is_contains ? 0 : -EINVAL; +} + +/** + * setsid() creates a new session if the calling process is not a process group leader. + * The calling process is the leader of the new session (i.e., its session ID is made the same as its process ID). + * The calling process also becomes the process group leader of a new process group in the session + * (i.e., its process group ID is made the same as its process ID). + */ +sysret_t sys_setsid(void) +{ + rt_lwp_t process; + pid_t pid; + rt_processgroup_t group; + rt_session_t session; + sysret_t err = 0; + + process = lwp_self(); + pid = lwp_to_pid(process); + + /** + * if the calling process is already a process group leader. + */ + if (lwp_pgrp_find(pid)) + { + err = -EPERM; + goto exit; + } + + group = lwp_pgrp_create(process); + if (group) + { + lwp_pgrp_move(group, process); + session = lwp_session_create(process); + if (session) + { + lwp_session_move(session, group); + } + else + { + lwp_pgrp_delete(group); + } + err = lwp_sid_get_bysession(session); + } + else + { + err = -ENOMEM; + } + + +exit: + return err; +} + +/** + * getsid() returns the session ID of the process with process ID pid. + * If pid is 0, getsid() returns the session ID of the calling process. + */ +sysret_t sys_getsid(pid_t pid) +{ + rt_lwp_t process, self_process; + pid_t sid; + + lwp_pid_lock_take(); + process = lwp_from_pid_locked(pid); + lwp_pid_lock_release(); + + if (process == RT_NULL) + { + return -ESRCH; + } + + self_process = lwp_self(); + sid = lwp_sid_get_byprocess(process); + + if (sid != lwp_sid_get_byprocess(self_process)) + { + /** + * A process with process ID pid exists, but it is not in the same session as the calling process, + * and the implementation considers this an error. + * + * Note: Linux does not return EPERM. + */ + return -EPERM; + } + + return sid; +} + +#ifdef RT_USING_FINSH + +#include "finsh.h" + +long list_session(void) +{ + int count = 0, index; + rt_session_t *sessions; + rt_session_t session; + rt_thread_t thread; + char name[RT_NAME_MAX]; + + rt_kprintf("SID leader process\n"); + rt_kprintf("---- ----------------\n"); + + count = rt_object_get_length(RT_Object_Class_Session); + if (count > 0) + { + /* get pointers */ + sessions = (rt_session_t *)rt_calloc(count, sizeof(rt_session_t)); + if (sessions) + { + index = rt_object_get_pointers(RT_Object_Class_Session, (rt_object_t *)sessions, count); + if (index > 0) + { + for (index = 0; index < count; index++) + { + struct rt_session se; + session = sessions[index]; + SESS_LOCK(session); + rt_memcpy(&se, session, sizeof(struct rt_session)); + SESS_UNLOCK(session); + + if (se.leader && se.leader) + { + thread = rt_list_entry(se.leader->t_grp.prev, struct rt_thread, sibling); + rt_strncpy(name, thread->parent.name, RT_NAME_MAX); + } + else + { + rt_strncpy(name, "nil", RT_NAME_MAX); + } + + rt_kprintf("%4d %-*.*s\n", se.sid, RT_NAME_MAX, RT_NAME_MAX, name); + } + } + rt_free(sessions); + } + } + + return 0; +} +MSH_CMD_EXPORT(list_session, list session); +#endif diff --git a/components/lwp/lwp_setsid.c b/components/lwp/lwp_setsid.c deleted file mode 100644 index d72363bde56..00000000000 --- a/components/lwp/lwp_setsid.c +++ /dev/null @@ -1,27 +0,0 @@ -#include -#include - -#include "lwp.h" -//#include "lwp_tid.h" -#include "lwp_pid.h" - -int setsid(void) -{ - int err = -EPERM; - struct rt_thread *current_thread = rt_thread_self(); - struct rt_lwp *current_lwp = (struct rt_lwp *)rt_thread_self()->lwp; - - if (current_lwp->session == current_thread->tid) - { - return err; - } - - current_lwp->session = current_thread->tid; - current_lwp->__pgrp = current_thread->tid; - current_lwp->leader = 1; - current_lwp->tty = RT_NULL; - current_lwp->tty_old_pgrp = 0; - - err = current_lwp->session; - return err; -} diff --git a/components/lwp/lwp_signal.c b/components/lwp/lwp_signal.c index 9e947ce7deb..1f20ad50960 100644 --- a/components/lwp/lwp_signal.c +++ b/components/lwp/lwp_signal.c @@ -10,6 +10,9 @@ * 2023-07-04 Shell Support siginfo, sigqueue * remove lwp_signal_backup/restore() to reduce architecture codes * update the generation, pending and delivery routines + * 2023-11-22 Shell Support for job control signal. Fixup of signal catch while + * some of the signals is blocked, but no more further dequeue is applied. + * Add itimer support */ #define __RT_IPC_SOURCE__ #define DBG_TAG "lwp.signal" @@ -24,7 +27,7 @@ #include "sys/signal.h" #include "syscall_generic.h" -static lwp_siginfo_t siginfo_create(int signo, int code, int value) +static lwp_siginfo_t siginfo_create(rt_thread_t current, int signo, int code, lwp_siginfo_ext_t ext) { lwp_siginfo_t siginfo; struct rt_lwp *self_lwp; @@ -35,10 +38,10 @@ static lwp_siginfo_t siginfo_create(int signo, int code, int value) { siginfo->ksiginfo.signo = signo; siginfo->ksiginfo.code = code; - siginfo->ksiginfo.value = value; + siginfo->ext = ext; - self_lwp = lwp_self(); - self_thr = rt_thread_self(); + self_thr = current; + self_lwp = current->lwp; if (self_lwp) { siginfo->ksiginfo.from_pid = self_lwp->pid; @@ -56,6 +59,12 @@ static lwp_siginfo_t siginfo_create(int signo, int code, int value) rt_inline void siginfo_delete(lwp_siginfo_t siginfo) { + if (siginfo->ext) + { + rt_free(siginfo->ext); + siginfo->ext = RT_NULL; + } + rt_free(siginfo); } @@ -296,10 +305,30 @@ static lwp_siginfo_t sigqueue_dequeue(lwp_sigqueue_t sigqueue, int signo) return found; } +/** + * Discard all the signal matching `signo` in sigqueue + */ static void sigqueue_discard(lwp_sigqueue_t sigqueue, int signo) { lwp_siginfo_t queuing_si; - while (!sigqueue_isempty(sigqueue)) + while (sigqueue_ismember(sigqueue, signo)) + { + queuing_si = sigqueue_dequeue(sigqueue, signo); + siginfo_delete(queuing_si); + } +} + +/** + * Discard all the queuing signals in sigset + */ +static void sigqueue_discard_sigset(lwp_sigqueue_t sigqueue, lwp_sigset_t *sigset) +{ + lwp_siginfo_t queuing_si; + lwp_sigset_t mask; + int signo; + + _signotsets(&mask, sigset); + while ((signo = sigqueue_peek(sigqueue, &mask)) != 0) { queuing_si = sigqueue_dequeue(sigqueue, signo); siginfo_delete(queuing_si); @@ -312,11 +341,21 @@ RT_STATIC_ASSERT(lp_width_same, sizeof(void *) == sizeof(long)); /** translate lwp siginfo to user siginfo_t */ rt_inline void siginfo_k2u(lwp_siginfo_t ksigi, siginfo_t *usigi) { + int signo = ksigi->ksiginfo.signo; usigi->si_code = ksigi->ksiginfo.code; - usigi->si_signo = ksigi->ksiginfo.signo; - usigi->si_value.sival_ptr = (void *)ksigi->ksiginfo.value; + usigi->si_signo = signo; usigi->si_pid = ksigi->ksiginfo.from_pid; + if (ksigi->ext) + { + if (signo == SIGCHLD) + { + usigi->si_status = ksigi->ext->sigchld.status; + usigi->si_utime = ksigi->ext->sigchld.stime; + usigi->si_stime = ksigi->ext->sigchld.utime; + } + } + /* deprecated field */ usigi->si_errno = 0; } @@ -417,7 +456,10 @@ rt_err_t lwp_signal_init(struct lwp_signal *sig) memset(&sig->sig_action_onstack, 0, sizeof(sig->sig_action_onstack)); memset(&sig->sig_action_restart, 0, sizeof(sig->sig_action_restart)); memset(&sig->sig_action_siginfo, 0, sizeof(sig->sig_action_siginfo)); + memset(&sig->sig_action_nocldstop, 0, sizeof(sig->sig_action_nocldstop)); + memset(&sig->sig_action_nocldwait, 0, sizeof(sig->sig_action_nocldwait)); lwp_sigqueue_init(&sig->sig_queue); + return rc; } @@ -433,17 +475,19 @@ rt_err_t lwp_signal_detach(struct lwp_signal *signal) int lwp_thread_signal_suspend_check(rt_thread_t thread, int suspend_flag) { - struct rt_lwp *lwp = (struct rt_lwp*)thread->lwp; + struct rt_lwp *lwp = (struct rt_lwp *)thread->lwp; + lwp_sigset_t sigmask = thread->signal.sigset_mask; int ret = 0; + _sigaddset(&sigmask, SIGCONT); switch (suspend_flag) { case RT_INTERRUPTIBLE: - if (!sigqueue_isempty(_SIGQ(thread))) + if (sigqueue_peek(_SIGQ(thread), &sigmask)) { break; } - if (thread->lwp && !sigqueue_isempty(_SIGQ(lwp))) + if (thread->lwp && sigqueue_peek(_SIGQ(lwp), &sigmask)) { break; } @@ -470,84 +514,202 @@ int lwp_thread_signal_suspend_check(rt_thread_t thread, int suspend_flag) return ret; } -void lwp_thread_signal_catch(void *exp_frame) +rt_inline rt_bool_t _is_jobctl_signal(rt_lwp_t lwp, int signo) { - int signo = 0; - struct rt_thread *thread; - struct rt_lwp *lwp; - lwp_siginfo_t siginfo = 0; - lwp_sigqueue_t pending; - lwp_sigset_t *sig_mask; - lwp_sigset_t save_sig_mask; - lwp_sigset_t new_sig_mask; - lwp_sighandler_t handler = 0; - siginfo_t usiginfo; - siginfo_t *p_usi = RT_NULL; + lwp_sigset_t jobctl_sigset = lwp_sigset_init(LWP_SIG_JOBCTL_SET); - thread = rt_thread_self(); - lwp = (struct rt_lwp*)thread->lwp; + return lwp_sigismember(&jobctl_sigset, signo); +} - RT_ASSERT(!!lwp); - LWP_LOCK(lwp); +rt_inline rt_bool_t _is_stop_signal(rt_lwp_t lwp, int signo) +{ + lwp_sigset_t stop_sigset = lwp_sigset_init(LWP_SIG_STOP_SET); + + return lwp_sigismember(&stop_sigset, signo); +} + +rt_inline rt_bool_t _need_notify_status_changed(rt_lwp_t lwp, int signo) +{ + RT_ASSERT(lwp_sigismember(&lwp_sigset_init(LWP_SIG_JOBCTL_SET), signo)); + return !lwp_sigismember(&lwp->signal.sig_action_nocldstop, SIGCHLD); +} + +/** + * wakeup the waitpid_waiters if any, and try to generate SIGCHLD if they are + * not disable explicitly by user. + * + * TODO: This event is always per-process and doesn't make whole lot of + * sense for ptracers, who shouldn't consume the state via wait(2) either, + * but, for backward compatibility, notify the ptracer of the group leader + * too unless it's gonna be a duplicate. + */ +static void _notify_parent_and_leader(rt_lwp_t child_lwp, rt_thread_t child_thr, int trig_signo, rt_bool_t is_stop) +{ + int si_code; + lwp_siginfo_ext_t ext; + rt_lwp_t parent_lwp = child_lwp->parent; + + if (!parent_lwp) + return ; - /* check if signal exist */ - if (!sigqueue_isempty(_SIGQ(thread))) + /* prepare the event data for parent to query */ + if (is_stop) { - pending = _SIGQ(thread); - sig_mask = &thread->signal.sigset_mask; + si_code = CLD_STOPPED; + child_lwp->lwp_status = LWP_CREATE_STAT_STOPPED(trig_signo); } - else if (!sigqueue_isempty(_SIGQ(lwp))) + else { - pending = _SIGQ(lwp); - sig_mask = &thread->signal.sigset_mask; + si_code = CLD_CONTINUED; + child_lwp->lwp_status = LWP_CREATE_STAT_CONTINUED; } - else + + /* wakeup waiter on waitpid(2) */ + lwp_waitpid_kick(parent_lwp, child_lwp); + + if (_need_notify_status_changed(parent_lwp, trig_signo)) { - pending = RT_NULL; + ext = rt_malloc(sizeof(struct lwp_siginfo_ext)); + if (ext) + { + ext->sigchld.status = trig_signo; + + /* TODO: signal usage is not supported */ + ext->sigchld.stime = child_thr->system_time; + ext->sigchld.utime = child_thr->user_time; + } + + /* generate SIGCHLD for parent */ + lwp_signal_kill(parent_lwp, SIGCHLD, si_code, ext); } +} + +static int _do_signal_wakeup(rt_thread_t thread, int sig); +static rt_err_t _stop_thread_locked(rt_lwp_t self_lwp, rt_thread_t cur_thr, int signo, + lwp_siginfo_t si, lwp_sigqueue_t sq) +{ + rt_err_t error; + int jobctl_stopped = self_lwp->jobctl_stopped; + rt_thread_t iter; - if (pending) + /* race to setup jobctl stopped flags */ + if (!jobctl_stopped) { - /* peek the pending signal */ - signo = sigqueue_peek(pending, sig_mask); - if (signo) + self_lwp->jobctl_stopped = RT_TRUE; + self_lwp->wait_reap_stp = RT_FALSE; + rt_list_for_each_entry(iter, &self_lwp->t_grp, sibling) { - siginfo = sigqueue_dequeue(pending, signo); - RT_ASSERT(siginfo != RT_NULL); - handler = _get_sighandler_locked(lwp, signo); + if (iter != cur_thr) + _do_signal_wakeup(iter, signo); + } + } - /* IGN signal will never be queued */ - RT_ASSERT(handler != LWP_SIG_ACT_IGN); + /** + * raise the event again so siblings is able to catch it again. + * `si` will be discarded while SIGCONT is generatd + */ + sigqueue_enqueue(sq, si); - /* copy the blocked signal mask from the registered signal action */ - memcpy(&new_sig_mask, &lwp->signal.sig_action_mask[signo - 1], sizeof(new_sig_mask)); + /* release the lwp lock so we can happily suspend */ + LWP_UNLOCK(self_lwp); - if (!_sigismember(&lwp->signal.sig_action_nodefer, signo)) - _sigaddset(&new_sig_mask, signo); + rt_set_errno(RT_EOK); - _thread_signal_mask(thread, LWP_SIG_MASK_CMD_BLOCK, &new_sig_mask, &save_sig_mask); + /* After suspension, only the SIGKILL and SIGCONT will wake this thread up */ + error = rt_thread_suspend_with_flag(cur_thr, RT_KILLABLE); + if (error == RT_EOK) + { + rt_schedule(); + error = rt_get_errno(); + error = error > 0 ? -error : error; + } - /* siginfo is need for signal action */ - if (_sigismember(&lwp->signal.sig_action_siginfo, signo)) - { - siginfo_k2u(siginfo, &usiginfo); - p_usi = &usiginfo; - } - else - p_usi = RT_NULL; - } + if (!jobctl_stopped && + (sigqueue_ismember(_SIGQ(self_lwp), SIGCONT) || + sigqueue_ismember(_SIGQ(cur_thr), SIGCONT))) + { + /** + * if we are resumed by a SIGCONT and we are the winner of racing + * notify parent of the incoming event + */ + _notify_parent_and_leader(self_lwp, cur_thr, SIGCONT, RT_FALSE); } + + /* reacquire the lock since we release it before */ + LWP_LOCK(self_lwp); + + return error; +} + +static void _catch_signal_locked(rt_lwp_t lwp, rt_thread_t thread, int signo, + lwp_siginfo_t siginfo, lwp_sighandler_t handler, + void *exp_frame) +{ + lwp_sigset_t new_sig_mask; + lwp_sigset_t save_sig_mask; + siginfo_t usiginfo; + siginfo_t *p_usi; + + /* siginfo is need for signal action */ + if (_sigismember(&lwp->signal.sig_action_siginfo, signo)) + { + siginfo_k2u(siginfo, &usiginfo); + p_usi = &usiginfo; + } + else + { + p_usi = RT_NULL; + } + + /** + * lock is acquired by caller. Release it so that we can happily go to the + * signal handler in user space + */ LWP_UNLOCK(lwp); - if (pending && signo) + siginfo_delete(siginfo); + + /* signal default handler */ + if (handler == LWP_SIG_ACT_DFL) { - siginfo_delete(siginfo); + lwp_sigset_t ign_sigset; - /* signal default handler */ - if (handler == LWP_SIG_ACT_DFL) + ign_sigset = lwp_sigset_init(LWP_SIG_IGNORE_SET); + if (signo == SIGCONT) + { + arch_syscall_set_errno(exp_frame, EINTR, ERESTART); + arch_thread_signal_enter(signo, p_usi, exp_frame, 0, &thread->signal.sigset_mask); + } + else if (!lwp_sigismember(&ign_sigset, signo) && !lwp->sig_protected) { + /* for those defautl handler is to terminate process */ LOG_D("%s: default handler; and exit", __func__); - sys_exit_group(0); + + /* TODO: coredump if neccessary */ + lwp_exit(lwp, LWP_CREATE_STAT_SIGNALED(signo, 0)); + } + /** + * otherwise is to ignore the signal, + * -> then reacquire the lock and return + */ + } + else if (handler == LWP_SIG_ACT_IGN) + { + /* do nothing */ + } + else + { + /* copy the blocked signal mask from the registered signal action */ + memcpy(&new_sig_mask, &lwp->signal.sig_action_mask[signo - 1], sizeof(new_sig_mask)); + + if (!_sigismember(&lwp->signal.sig_action_nodefer, signo)) + _sigaddset(&new_sig_mask, signo); + + _thread_signal_mask(thread, LWP_SIG_MASK_CMD_BLOCK, &new_sig_mask, &save_sig_mask); + + if (_sigismember(&lwp->signal.sig_action_restart, signo)) + { + arch_syscall_set_errno(exp_frame, EINTR, ERESTART); } /** @@ -557,18 +719,92 @@ void lwp_thread_signal_catch(void *exp_frame) */ LOG_D("%s: enter signal handler(signo=%d) at %p", __func__, signo, handler); arch_thread_signal_enter(signo, p_usi, exp_frame, handler, &save_sig_mask); + /* the arch_thread_signal_enter() never return */ RT_ASSERT(0); } + + /* reacquire the lock because we release it before */ + LWP_LOCK(lwp); } + +void lwp_thread_signal_catch(void *exp_frame) +{ + struct rt_thread *thread; + struct rt_lwp *lwp; + lwp_sigqueue_t pending; + lwp_sigset_t *sig_mask; + int retry_signal_catch; + int signo; + + thread = rt_thread_self(); + lwp = (struct rt_lwp *)thread->lwp; + + RT_ASSERT(!!lwp); + LWP_LOCK(lwp); + + do { + /* if stopped process resume, we will retry to catch the signal */ + retry_signal_catch = 0; + signo = 0; + + /* try to peek a signal which is pending and not blocked by this thread */ + if (!sigqueue_isempty(_SIGQ(thread))) + { + pending = _SIGQ(thread); + sig_mask = &thread->signal.sigset_mask; + signo = sigqueue_peek(pending, sig_mask); + } + if (!signo && !sigqueue_isempty(_SIGQ(lwp))) + { + pending = _SIGQ(lwp); + sig_mask = &thread->signal.sigset_mask; + signo = sigqueue_peek(pending, sig_mask); + } + + if (signo) + { + lwp_siginfo_t siginfo; + lwp_sighandler_t handler; + + LOG_D("%s(signo=%d)", __func__, signo); + + siginfo = sigqueue_dequeue(pending, signo); + RT_ASSERT(siginfo != RT_NULL); + handler = _get_sighandler_locked(lwp, signo); + + if (_is_stop_signal(lwp, signo) && handler == LWP_SIG_ACT_DFL) + { + /* notify the status update for parent process */ + _notify_parent_and_leader(lwp, thread, signo, RT_TRUE); + + LOG_D("%s: pid=%d stopped", __func__, lwp->pid); + _stop_thread_locked(lwp, thread, signo, siginfo, pending); + LOG_D("%s: pid=%d continued", __func__, lwp->pid); + + /* wakeup and retry to catch signals send to us */ + retry_signal_catch = 1; + } + else + { + /* do a normal, non-jobctl signal handling */ + _catch_signal_locked(lwp, thread, signo, siginfo, handler, exp_frame); + } + } + } while (retry_signal_catch); + + LWP_UNLOCK(lwp); +} + static int _do_signal_wakeup(rt_thread_t thread, int sig) { int need_schedule; rt_sched_lock_level_t slvl; if (!_sigismember(&thread->signal.sigset_mask, sig)) { + int stat; rt_sched_lock(&slvl); - int stat = rt_sched_thread_get_stat(thread); + stat = rt_sched_thread_get_stat(thread); if ((stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK) { if ((stat & RT_SIGNAL_COMMON_WAKEUP_MASK) != RT_SIGNAL_COMMON_WAKEUP_MASK) @@ -599,6 +835,8 @@ static int _do_signal_wakeup(rt_thread_t thread, int sig) rt_sched_unlock(slvl); need_schedule = 0; } + + RT_SCHED_DEBUG_IS_UNLOCKED; } else need_schedule = 0; @@ -689,7 +927,63 @@ rt_inline rt_bool_t _sighandler_cannot_caught(struct rt_lwp *lwp, int signo) return signo == SIGKILL || signo == SIGSTOP; } -rt_err_t lwp_signal_kill(struct rt_lwp *lwp, long signo, long code, long value) +/* before signal is killed to target process/thread */ +static void _before_sending_jobctl_signal(int signo, rt_lwp_t target_lwp, lwp_siginfo_t si) +{ + rt_thread_t thr_iter; + rt_sched_lock_level_t slvl; + lwp_sigset_t jobctl_sigset = lwp_sigset_init(LWP_SIG_JOBCTL_SET); + + LWP_ASSERT_LOCKED(target_lwp); + + /** + * dequeue all the pending jobctl signals (including + * the one we are adding, since we don't want to pend it) + */ + sigqueue_discard_sigset(_SIGQ(target_lwp), &jobctl_sigset); + + if (signo == SIGCONT) + { + target_lwp->jobctl_stopped = RT_FALSE; + rt_list_for_each_entry(thr_iter, &target_lwp->t_grp, sibling) + { + rt_base_t stat; + sigqueue_discard_sigset(_SIGQ(thr_iter), &jobctl_sigset); + + /** + * Note: all stopped thread will be resumed + */ + rt_sched_lock(&slvl); + stat = rt_sched_thread_get_stat(thr_iter); + if ((stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK && + (stat & RT_SIGNAL_KILL_WAKEUP_MASK) == 0) + { + thr_iter->error = RT_EINTR; + + /** + * don't matter if we failed to resume the thread, since we + * only care about the event passing, but not ordering here + */ + rt_sched_unlock(slvl); + rt_thread_wakeup(thr_iter); + } + else + { + rt_sched_unlock(slvl); + } + + } + } + else + { + rt_list_for_each_entry(thr_iter, &target_lwp->t_grp, sibling) + { + sigqueue_discard_sigset(_SIGQ(thr_iter), &jobctl_sigset); + } + } +} + +rt_err_t lwp_signal_kill(struct rt_lwp *lwp, long signo, long code, lwp_siginfo_ext_t value) { rt_err_t ret = -1; @@ -700,10 +994,15 @@ rt_err_t lwp_signal_kill(struct rt_lwp *lwp, long signo, long code, long value) /** must be able to be suspended */ RT_DEBUG_SCHEDULER_AVAILABLE(RT_TRUE); - if (!lwp || signo <= 0 || signo > _LWP_NSIG) + if (!lwp || signo < 0 || signo > _LWP_NSIG) { ret = -RT_EINVAL; } + else if (signo == 0) + { + /* process exist and current process have privileges */ + ret = 0; + } else { LOG_D("%s(lwp=%p \"%s\",signo=%ld,code=%ld,value=%ld)", @@ -715,19 +1014,25 @@ rt_err_t lwp_signal_kill(struct rt_lwp *lwp, long signo, long code, long value) terminated = lwp->terminated; /* short-circuit code for inactive task, ignored signals */ - if (terminated || _sighandler_is_ignored(lwp, signo)) + if (terminated) { + /* no one rely on this, then free the resource */ + if (value) + rt_free(value); ret = 0; } else { - siginfo = siginfo_create(signo, code, value); + siginfo = siginfo_create(rt_thread_self(), signo, code, value); if (siginfo) { + if (_is_jobctl_signal(lwp, signo)) + _before_sending_jobctl_signal(signo, lwp, siginfo); + need_schedule = _siginfo_deliver_to_lwp(lwp, siginfo); - ret = 0; lwp_signal_notify(&lwp->signalfd_notify_head, siginfo); + ret = 0; } else { @@ -755,6 +1060,10 @@ static void _signal_action_flag_k2u(int signo, struct lwp_signal *signal, struct flags |= SA_RESTART; if (_sigismember(&signal->sig_action_siginfo, signo)) flags |= SA_SIGINFO; + if (_sigismember(&signal->sig_action_nocldstop, signo)) + flags |= SA_NOCLDSTOP; + if (_sigismember(&signal->sig_action_nocldwait, signo)) + flags |= SA_NOCLDWAIT; act->sa_flags = flags; } @@ -770,6 +1079,25 @@ static void _signal_action_flag_u2k(int signo, struct lwp_signal *signal, const _sigaddset(&signal->sig_action_restart, signo); if (flags & SA_SIGINFO) _sigaddset(&signal->sig_action_siginfo, signo); + if (signo == SIGCHLD) + { + /* These flags are meaningful only when establishing a handler for SIGCHLD */ + if (flags & SA_NOCLDSTOP) + _sigaddset(&signal->sig_action_nocldstop, signo); + if (flags & SA_NOCLDWAIT) + _sigaddset(&signal->sig_action_nocldwait, signo); + } + + #define _HANDLE_FLAGS (SA_RESTORER | SA_NODEFER | SA_ONSTACK | SA_RESTART | SA_SIGINFO | SA_NOCLDSTOP | SA_NOCLDWAIT) + if (flags & ~_HANDLE_FLAGS) + LOG_W("Unhandled flags: 0x%lx", flags & ~_HANDLE_FLAGS); +} + +rt_bool_t lwp_sigisign(struct rt_lwp *lwp, int _sig) +{ + unsigned long sig = _sig - 1; + + return lwp->signal.sig_action[sig] == LWP_SIG_ACT_IGN; } rt_err_t lwp_signal_action(struct rt_lwp *lwp, int signo, @@ -793,6 +1121,7 @@ rt_err_t lwp_signal_action(struct rt_lwp *lwp, int signo, oact->sa_restorer = RT_NULL; _signal_action_flag_k2u(signo, &lwp->signal, oact); } + if (act) { /** @@ -800,15 +1129,29 @@ rt_err_t lwp_signal_action(struct rt_lwp *lwp, int signo, * argument succeed, even in the case of signals that cannot be caught or ignored */ if (_sighandler_cannot_caught(lwp, signo)) - ret = -RT_EINVAL; + ret = -EINVAL; else { prev_handler = _get_sighandler_locked(lwp, signo); lwp->signal.sig_action_mask[signo - 1] = act->sa_mask; if (act->__sa_handler._sa_handler == SIG_IGN) - lwp->signal.sig_action[signo - 1] = LWP_SIG_ACT_IGN; + { + lwp_sigset_t no_ign_set = lwp_sigset_init(LWP_SIG_NO_IGN_SET); + if (!lwp_sigismember(&no_ign_set, signo)) + { + /* except those unignorable signals, discard them for proc */ + lwp->signal.sig_action[signo - 1] = LWP_SIG_ACT_IGN; + } + else + { + /* POSIX.1: SIG_IGN and SIG_DFL are equivalent for SIGCONT */ + lwp->signal.sig_action[signo - 1] = LWP_SIG_ACT_DFL; + } + } else + { lwp->signal.sig_action[signo - 1] = act->__sa_handler._sa_handler; + } _signal_action_flag_u2k(signo, &lwp->signal, act); @@ -837,12 +1180,12 @@ rt_err_t lwp_signal_action(struct rt_lwp *lwp, int signo, LWP_UNLOCK(lwp); } else - ret = -RT_EINVAL; + ret = -EINVAL; return ret; } -rt_err_t lwp_thread_signal_kill(rt_thread_t thread, long signo, long code, long value) +rt_err_t lwp_thread_signal_kill(rt_thread_t thread, long signo, long code, lwp_siginfo_ext_t value) { rt_err_t ret = -1; @@ -855,10 +1198,15 @@ rt_err_t lwp_thread_signal_kill(rt_thread_t thread, long signo, long code, long LOG_D("%s(signo=%d)", __func__, signo); - if (!thread || signo <= 0 || signo >= _LWP_NSIG) + if (!thread || signo < 0 || signo >= _LWP_NSIG) { ret = -RT_EINVAL; } + else if (signo == 0) + { + /* thread exist and current thread have privileges */ + ret = 0; + } else { lwp = thread->lwp; @@ -874,7 +1222,7 @@ rt_err_t lwp_thread_signal_kill(rt_thread_t thread, long signo, long code, long ret = 0; else { - siginfo = siginfo_create(signo, code, value); + siginfo = siginfo_create(rt_thread_self(), signo, code, value); if (siginfo) { @@ -919,7 +1267,7 @@ rt_err_t lwp_thread_signal_mask(rt_thread_t thread, lwp_sig_mask_cmd_t how, if (thread) { - lwp = (struct rt_lwp*)thread->lwp; + lwp = (struct rt_lwp *)thread->lwp; LWP_LOCK(lwp); if (!lwp) @@ -948,13 +1296,14 @@ static int _dequeue_signal(rt_thread_t thread, lwp_sigset_t *mask, siginfo_t *us lwp_sigset_t *pending; lwp_sigqueue_t sigqueue; + lwp = thread->lwp; + RT_ASSERT(lwp); + sigqueue = _SIGQ(thread); pending = &sigqueue->sigset_pending; signo = _next_signal(pending, mask); if (!signo) { - lwp = thread->lwp; - RT_ASSERT(lwp); sigqueue = _SIGQ(lwp); pending = &sigqueue->sigset_pending; signo = _next_signal(pending, mask); @@ -978,6 +1327,7 @@ rt_err_t lwp_thread_signal_timedwait(rt_thread_t thread, lwp_sigset_t *sigset, rt_err_t ret; lwp_sigset_t saved_sigset; lwp_sigset_t blocked_sigset; + lwp_sigset_t dontwait_sigset; int sig; struct rt_lwp *lwp = thread->lwp; @@ -990,10 +1340,10 @@ rt_err_t lwp_thread_signal_timedwait(rt_thread_t thread, lwp_sigset_t *sigset, /* Create a mask of signals user dont want or cannot catch */ _sigdelset(sigset, SIGKILL); _sigdelset(sigset, SIGSTOP); - _signotsets(sigset, sigset); + _signotsets(&dontwait_sigset, sigset); LWP_LOCK(lwp); - sig = _dequeue_signal(thread, sigset, usi); + sig = _dequeue_signal(thread, &dontwait_sigset, usi); LWP_UNLOCK(lwp); if (sig) return sig; @@ -1007,13 +1357,12 @@ rt_err_t lwp_thread_signal_timedwait(rt_thread_t thread, lwp_sigset_t *sigset, * Note: If the pending signal arrives before thread suspend, the suspend * operation will return a failure */ - _sigandsets(&blocked_sigset, &thread->signal.sigset_mask, sigset); + _sigandsets(&blocked_sigset, &thread->signal.sigset_mask, &dontwait_sigset); _thread_signal_mask(thread, LWP_SIG_MASK_CMD_SET_MASK, &blocked_sigset, &saved_sigset); if (timeout) { - rt_uint32_t time; - time = rt_timespec_to_tick(timeout); - + rt_tick_t time; + time = (timeout->tv_sec * RT_TICK_PER_SECOND) + ((timeout->tv_nsec * RT_TICK_PER_SECOND) / NANOSECOND_PER_SECOND); /** * Brief: POSIX * If the timespec structure pointed to by timeout is zero-valued and @@ -1023,11 +1372,13 @@ rt_err_t lwp_thread_signal_timedwait(rt_thread_t thread, lwp_sigset_t *sigset, if (time == 0) return -EAGAIN; + rt_enter_critical(); ret = rt_thread_suspend_with_flag(thread, RT_INTERRUPTIBLE); rt_timer_control(&(thread->thread_timer), RT_TIMER_CTRL_SET_TIME, &time); rt_timer_start(&(thread->thread_timer)); + rt_exit_critical(); } else @@ -1040,7 +1391,7 @@ rt_err_t lwp_thread_signal_timedwait(rt_thread_t thread, lwp_sigset_t *sigset, { rt_schedule(); /* If thread->error reliable? */ - if (thread->error == -RT_EINTR) + if (thread->error == RT_EINTR) ret = -EINTR; else ret = -EAGAIN; @@ -1049,7 +1400,7 @@ rt_err_t lwp_thread_signal_timedwait(rt_thread_t thread, lwp_sigset_t *sigset, _thread_signal_mask(thread, LWP_SIG_MASK_CMD_SET_MASK, &saved_sigset, RT_NULL); LWP_LOCK(lwp); - sig = _dequeue_signal(thread, sigset, usi); + sig = _dequeue_signal(thread, &dontwait_sigset, usi); LWP_UNLOCK(lwp); return sig ? sig : ret; @@ -1072,3 +1423,22 @@ void lwp_thread_signal_pending(rt_thread_t thread, lwp_sigset_t *pending) _sigandsets(pending, pending, &thread->signal.sigset_mask); } } + +rt_err_t lwp_pgrp_signal_kill(rt_processgroup_t pgrp, long signo, long code, + lwp_siginfo_ext_t value) +{ + struct rt_lwp *lwp; + rt_err_t rc = 0; + + PGRP_ASSERT_LOCKED(pgrp); + + if (pgrp) + { + rt_list_for_each_entry(lwp, &pgrp->process, pgrp_node) + { + lwp_signal_kill(lwp, signo, code, value); + } + } + + return rc; +} diff --git a/components/lwp/lwp_signal.h b/components/lwp/lwp_signal.h index 3b5fd91321d..f98b43dd3fd 100644 --- a/components/lwp/lwp_signal.h +++ b/components/lwp/lwp_signal.h @@ -7,6 +7,7 @@ * Date Author Notes * 2020-02-23 Jesven first version. * 2023-07-06 Shell update the generation, pending and delivery API + * 2023-11-22 Shell support for job control signal */ #ifndef __LWP_SIGNAL_H__ @@ -17,23 +18,33 @@ #include #include -struct timespec; -struct itimerspec; - #ifdef __cplusplus extern "C" { #endif #define _USIGNAL_SIGMASK(signo) (1u << ((signo)-1)) -#define LWP_SIG_IGNORE_SET (_USIGNAL_SIGMASK(SIGCHLD) | _USIGNAL_SIGMASK(SIGURG)) -#define LWP_SIG_ACT_DFL ((lwp_sighandler_t)0) -#define LWP_SIG_ACT_IGN ((lwp_sighandler_t)1) -#define LWP_SIG_USER_SA_FLAGS \ - (SA_NOCLDSTOP | SA_NOCLDWAIT | SA_SIGINFO | SA_ONSTACK | SA_RESTART | \ +#define LWP_SIG_NO_IGN_SET \ + (_USIGNAL_SIGMASK(SIGCONT) | _USIGNAL_SIGMASK(SIGSTOP) | \ + _USIGNAL_SIGMASK(SIGKILL)) +#define LWP_SIG_IGNORE_SET \ + (_USIGNAL_SIGMASK(SIGCHLD) | _USIGNAL_SIGMASK(SIGURG) | \ + _USIGNAL_SIGMASK(SIGWINCH) /* from 4.3 BSD, not POSIX.1 */) +#define LWP_SIG_JOBCTL_SET \ + (_USIGNAL_SIGMASK(SIGCONT) | _USIGNAL_SIGMASK(SIGSTOP) | \ + _USIGNAL_SIGMASK(SIGTSTP) | _USIGNAL_SIGMASK(SIGTTIN) | \ + _USIGNAL_SIGMASK(SIGTTOU)) +#define LWP_SIG_STOP_SET \ + (_USIGNAL_SIGMASK(SIGSTOP) | _USIGNAL_SIGMASK(SIGTSTP) | \ + _USIGNAL_SIGMASK(SIGTTIN) | _USIGNAL_SIGMASK(SIGTTOU)) +#define LWP_SIG_ACT_DFL ((lwp_sighandler_t)0) +#define LWP_SIG_ACT_IGN ((lwp_sighandler_t)1) +#define LWP_SIG_USER_SA_FLAGS \ + (SA_NOCLDSTOP | SA_NOCLDWAIT | SA_SIGINFO | SA_ONSTACK | SA_RESTART | \ SA_NODEFER | SA_RESETHAND | SA_EXPOSE_TAGBITS) #define LWP_SIG_INVALID_TIMER ((timer_t)-1) -typedef enum { +typedef enum +{ LWP_SIG_MASK_CMD_BLOCK, LWP_SIG_MASK_CMD_UNBLOCK, LWP_SIG_MASK_CMD_SET_MASK, @@ -43,7 +54,8 @@ typedef enum { /** * LwP implementation of POSIX signal */ -struct lwp_signal { +struct lwp_signal +{ timer_t real_timer; struct lwp_sigqueue sig_queue; rt_thread_t sig_dispatch_thr[_LWP_NSIG]; @@ -55,9 +67,12 @@ struct lwp_signal { lwp_sigset_t sig_action_onstack; lwp_sigset_t sig_action_restart; lwp_sigset_t sig_action_siginfo; + lwp_sigset_t sig_action_nocldstop; + lwp_sigset_t sig_action_nocldwait; }; struct rt_lwp; +struct rt_processgroup; #ifndef ARCH_MM_MMU void lwp_sighandler_set(int sig, lwp_sighandler_t func); @@ -93,12 +108,14 @@ rt_inline void lwp_thread_signal_detach(struct lwp_thread_signal *tsig) * @param signo the signal number * @param code as in siginfo * @param value as in siginfo - * @return rt_err_t RT_EINVAL if the parameter is invalid, RT_EOK as successful + * @return rt_err_t RT_EINVAL if the parameter is invalid, RT_EOK as + * successful * * @note the *signal_kill have the same definition of a successful return as * kill() in IEEE Std 1003.1-2017 */ -rt_err_t lwp_signal_kill(struct rt_lwp *lwp, long signo, long code, long value); +rt_err_t lwp_signal_kill(struct rt_lwp *lwp, long signo, long code, + lwp_siginfo_ext_t value); /** * @brief set or examine the signal action of signo @@ -119,9 +136,11 @@ rt_err_t lwp_signal_action(struct rt_lwp *lwp, int signo, * @param signo the signal number * @param code as in siginfo * @param value as in siginfo - * @return rt_err_t RT_EINVAL if the parameter is invalid, RT_EOK as successful + * @return rt_err_t RT_EINVAL if the parameter is invalid, RT_EOK as + * successful */ -rt_err_t lwp_thread_signal_kill(rt_thread_t thread, long signo, long code, long value); +rt_err_t lwp_thread_signal_kill(rt_thread_t thread, long signo, long code, + lwp_siginfo_ext_t value); /** * @brief set signal mask of target thread @@ -136,7 +155,8 @@ rt_err_t lwp_thread_signal_mask(rt_thread_t thread, lwp_sig_mask_cmd_t how, const lwp_sigset_t *sigset, lwp_sigset_t *oset); /** - * @brief Catch signal if exists and no return, otherwise return with no side effect + * @brief Catch signal if exists and no return, otherwise return with no + * side effect * * @param exp_frame the exception frame on kernel stack */ @@ -172,10 +192,43 @@ rt_err_t lwp_thread_signal_timedwait(rt_thread_t thread, lwp_sigset_t *sigset, */ void lwp_thread_signal_pending(rt_thread_t thread, lwp_sigset_t *sigset); +/** + * @brief send a signal to the process group + * + * @param pgrp target process group + * @param signo the signal number + * @param code as in siginfo + * @param value as in siginfo + * @return rt_err_t RT_EINVAL if the parameter is invalid, RT_EOK as + * successful + */ +rt_err_t lwp_pgrp_signal_kill(struct rt_processgroup *pgrp, long signo, + long code, lwp_siginfo_ext_t value); + +rt_inline int lwp_sigismember(lwp_sigset_t *set, int _sig) +{ + unsigned long sig = _sig - 1; + + if (_LWP_NSIG_WORDS == 1) + { + return 1 & (set->sig[0] >> sig); + } + else + { + return 1 & (set->sig[sig / _LWP_NSIG_BPW] >> (sig % _LWP_NSIG_BPW)); + } +} + +struct itimerspec; + +rt_bool_t lwp_sigisign(struct rt_lwp *lwp, int _sig); + rt_err_t lwp_signal_setitimer(struct rt_lwp *lwp, int which, const struct itimerspec *restrict new, struct itimerspec *restrict old); +rt_bool_t lwp_signal_restart_syscall(struct rt_lwp *lwp, int error_code); + #ifdef __cplusplus } #endif diff --git a/components/lwp/lwp_sys_socket.h b/components/lwp/lwp_sys_socket.h index 527d5ebbe81..28a0887203a 100644 --- a/components/lwp/lwp_sys_socket.h +++ b/components/lwp/lwp_sys_socket.h @@ -113,7 +113,7 @@ struct musl_ifreq { union { -#define IFNAMSIZ 16 +#define IFNAMSIZ 16 char ifrn_name[IFNAMSIZ]; } ifr_ifrn; union @@ -133,4 +133,23 @@ struct musl_ifreq } ifr_ifru; }; +struct musl_rtentry +{ + unsigned long int rt_pad1; + struct musl_sockaddr rt_dst; + struct musl_sockaddr rt_gateway; + struct musl_sockaddr rt_genmask; + unsigned short int rt_flags; + short int rt_pad2; + unsigned long int rt_pad3; + unsigned char rt_tos; + unsigned char rt_class; + short int rt_pad4[sizeof(long)/2-1]; + short int rt_metric; + char *rt_dev; + unsigned long int rt_mtu; + unsigned long int rt_window; + unsigned short int rt_irtt; +}; + #endif /* __LWP_SYS_SOCKET_H__ */ diff --git a/components/lwp/lwp_syscall.c b/components/lwp/lwp_syscall.c index 718636e102a..585101b71f6 100644 --- a/components/lwp/lwp_syscall.c +++ b/components/lwp/lwp_syscall.c @@ -13,6 +13,9 @@ * 2023-03-13 WangXiaoyao Format & fix syscall return value * 2023-07-06 Shell adapt the signal API, and clone, fork to new implementation of lwp signal * 2023-07-27 Shell Move tid_put() from lwp_free() to sys_exit() + * 2023-11-16 xqyjlj fix some syscalls (about sched_*, get/setpriority) + * 2023-11-17 xqyjlj add process group and session support + * 2023-11-30 Shell Fix sys_setitimer() and exit(status) */ #define __RT_IPC_SOURCE__ #define _GNU_SOURCE @@ -22,7 +25,6 @@ #include #include -#include #include #include @@ -57,6 +59,7 @@ #include #include /* statfs() */ #include +#include #ifdef RT_USING_MUSLLIBC #include #endif @@ -88,7 +91,6 @@ #define SYSCALL_USPACE(f) SYSCALL_SIGN(sys_notimpl) #endif /* defined(RT_USING_DFS) && defined(ARCH_MM_MMU) */ -#include #include "lwp_ipc_internal.h" #include @@ -329,10 +331,14 @@ static void _crt_thread_entry(void *parameter) sysret_t sys_exit_group(int value) { sysret_t rc = 0; + lwp_status_t lwp_status; struct rt_lwp *lwp = lwp_self(); if (lwp) - lwp_exit(lwp, value); + { + lwp_status = LWP_CREATE_STAT_EXIT(value); + lwp_exit(lwp, lwp_status); + } else { LOG_E("Can't find matching process of current thread"); @@ -350,7 +356,10 @@ sysret_t sys_exit(int status) tid = rt_thread_self(); if (tid && tid->lwp) + { lwp_thread_exit(tid, status); + } + else { LOG_E("Can't find matching process of current thread"); rc = -EINVAL; @@ -616,102 +625,9 @@ sysret_t sys_fstat(int file, struct stat *buf) #endif } -/* DFS and lwip definitions */ -#define IMPL_POLLIN (0x01) - -#define IMPL_POLLOUT (0x02) - -#define IMPL_POLLERR (0x04) -#define IMPL_POLLHUP (0x08) -#define IMPL_POLLNVAL (0x10) - -/* musl definitions */ -#define INTF_POLLIN 0x001 -#define INTF_POLLPRI 0x002 -#define INTF_POLLOUT 0x004 -#define INTF_POLLERR 0x008 -#define INTF_POLLHUP 0x010 -#define INTF_POLLNVAL 0x020 -#define INTF_POLLRDNORM 0x040 -#define INTF_POLLRDBAND 0x080 -#define INTF_POLLWRNORM 0x100 -#define INTF_POLLWRBAND 0x200 -#define INTF_POLLMSG 0x400 -#define INTF_POLLRDHUP 0x2000 - -#define INTF_POLLIN_MASK (INTF_POLLIN | INTF_POLLRDNORM | INTF_POLLRDBAND | INTF_POLLPRI) -#define INTF_POLLOUT_MASK (INTF_POLLOUT | INTF_POLLWRNORM | INTF_POLLWRBAND) - -static void musl2dfs_events(short *events) -{ - short origin_e = *events; - short result_e = 0; - - if (origin_e & INTF_POLLIN_MASK) - { - result_e |= IMPL_POLLIN; - } - - if (origin_e & INTF_POLLOUT_MASK) - { - result_e |= IMPL_POLLOUT; - } - - if (origin_e & INTF_POLLERR) - { - result_e |= IMPL_POLLERR; - } - - if (origin_e & INTF_POLLHUP) - { - result_e |= IMPL_POLLHUP; - } - - if (origin_e & INTF_POLLNVAL) - { - result_e |= IMPL_POLLNVAL; - } - - *events = result_e; -} - -static void dfs2musl_events(short *events) -{ - short origin_e = *events; - short result_e = 0; - - if (origin_e & IMPL_POLLIN) - { - result_e |= INTF_POLLIN_MASK; - } - - if (origin_e & IMPL_POLLOUT) - { - result_e |= INTF_POLLOUT_MASK; - } - - if (origin_e & IMPL_POLLERR) - { - result_e |= INTF_POLLERR; - } - - if (origin_e & IMPL_POLLHUP) - { - result_e |= INTF_POLLHUP; - } - - if (origin_e & IMPL_POLLNVAL) - { - result_e |= INTF_POLLNVAL; - } - - *events = result_e; -} - sysret_t sys_poll(struct pollfd *fds, nfds_t nfds, int timeout) { int ret = -1; - int i = 0; #ifdef ARCH_MM_MMU struct pollfd *kfds = RT_NULL; @@ -728,43 +644,20 @@ sysret_t sys_poll(struct pollfd *fds, nfds_t nfds, int timeout) lwp_get_from_user(kfds, fds, nfds * sizeof *kfds); - for (i = 0; i < nfds; i++) - { - musl2dfs_events(&kfds[i].events); - } ret = poll(kfds, nfds, timeout); if (ret > 0) { - for (i = 0; i < nfds; i++) - { - dfs2musl_events(&kfds->revents); - } lwp_put_to_user(fds, kfds, nfds * sizeof *kfds); } kmem_put(kfds); return ret; #else -#ifdef RT_USING_MUSLLIBC - for (i = 0; i < nfds; i++) - { - musl2dfs_events(&fds->events); - } -#endif /* RT_USING_MUSLLIBC */ if (!lwp_user_accessable((void *)fds, nfds * sizeof *fds)) { return -EFAULT; } ret = poll(fds, nfds, timeout); -#ifdef RT_USING_MUSLLIBC - if (ret > 0) - { - for (i = 0; i < nfds; i++) - { - dfs2musl_events(&fds->revents); - } - } -#endif /* RT_USING_MUSLLIBC */ return ret; #endif /* ARCH_MM_MMU */ } @@ -1014,9 +907,9 @@ sysret_t sys_exec(char *filename, int argc, char **argv, char **envp) sysret_t sys_kill(int pid, int signo) { - rt_err_t kret; + rt_err_t kret = 0; sysret_t sysret; - struct rt_lwp *lwp; + struct rt_lwp *lwp = RT_NULL; /* handling the semantics of sys_kill */ if (pid > 0) @@ -1027,31 +920,60 @@ sysret_t sys_kill(int pid, int signo) * - pid tree (READ. since the lwp is fetch from the pid tree, it must stay there) */ lwp_pid_lock_take(); - lwp = lwp_from_pid_locked(pid); + lwp = lwp_from_pid_raw_locked(pid); if (lwp) { lwp_ref_inc(lwp); lwp_pid_lock_release(); - - kret = lwp_signal_kill(lwp, signo, SI_USER, 0); - lwp_ref_dec(lwp); - kret = 0; } else { lwp_pid_lock_release(); kret = -RT_ENOENT; } + + if (lwp) + { + kret = lwp_signal_kill(lwp, signo, SI_USER, 0); + lwp_ref_dec(lwp); + } } - else if (pid == 0) + else if (pid < -1 || pid == 0) { - /** - * sig shall be sent to all processes (excluding an unspecified set - * of system processes) whose process group ID is equal to the process - * group ID of the sender, and for which the process has permission to - * send a signal. - */ - kret = -RT_ENOSYS; + pid_t pgid = 0; + rt_processgroup_t group; + + if (pid == 0) + { + /** + * sig shall be sent to all processes (excluding an unspecified set + * of system processes) whose process group ID is equal to the process + * group ID of the sender, and for which the process has permission to + * send a signal. + */ + pgid = lwp_pgid_get_byprocess(lwp_self()); + } + else + { + /** + * sig shall be sent to all processes (excluding an unspecified set + * of system processes) whose process group ID is equal to the absolute + * value of pid, and for which the process has permission to send a signal. + */ + pgid = -pid; + } + + group = lwp_pgrp_find(pgid); + if (group != RT_NULL) + { + PGRP_LOCK(group); + kret = lwp_pgrp_signal_kill(group, signo, SI_USER, 0); + PGRP_UNLOCK(group); + } + else + { + kret = -ECHILD; + } } else if (pid == -1) { @@ -1062,15 +984,6 @@ sysret_t sys_kill(int pid, int signo) */ kret = -RT_ENOSYS; } - else /* pid < -1 */ - { - /** - * sig shall be sent to all processes (excluding an unspecified set - * of system processes) whose process group ID is equal to the absolute - * value of pid, and for which the process has permission to send a signal. - */ - kret = -RT_ENOSYS; - } switch (kret) { @@ -1102,6 +1015,22 @@ sysret_t sys_getpid(void) return lwp_getpid(); } +sysret_t sys_getppid(void) +{ + rt_lwp_t process; + + process = lwp_self(); + if (process->parent == RT_NULL) + { + LOG_E("%s: process %d has no parent process", __func__, lwp_to_pid(process)); + return 0; + } + else + { + return lwp_to_pid(process->parent); + } +} + /* syscall: "getpriority" ret: "int" args: "int" "id_t" */ sysret_t sys_getpriority(int which, id_t who) { @@ -1112,10 +1041,7 @@ sysret_t sys_getpriority(int which, id_t who) struct rt_lwp *lwp = RT_NULL; lwp_pid_lock_take(); - if(who == 0) - lwp = lwp_self(); - else - lwp = lwp_from_pid_locked(who); + lwp = lwp_from_pid_locked(who); if (lwp) { @@ -1137,10 +1063,7 @@ sysret_t sys_setpriority(int which, id_t who, int prio) struct rt_lwp *lwp = RT_NULL; lwp_pid_lock_take(); - if(who == 0) - lwp = lwp_self(); - else - lwp = lwp_from_pid_locked(who); + lwp = lwp_from_pid_locked(who); if (lwp && prio >= 0 && prio < RT_THREAD_PRIORITY_MAX) { @@ -1317,7 +1240,7 @@ sysret_t sys_munmap(void *addr, size_t length) void *sys_mremap(void *old_address, size_t old_size, size_t new_size, int flags, void *new_address) { - return (void *)-1; + return lwp_mremap(lwp_self(), old_address, old_size, new_size, flags, new_address); } sysret_t sys_madvise(void *addr, size_t len, int behav) @@ -1475,6 +1398,34 @@ sysret_t sys_mb_recv(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout) return ret; } +rt_weak int syslog_ctrl(int type, char *buf, int len) +{ + return -EINVAL; +} + +sysret_t sys_syslog(int type, char *buf, int len) +{ + char *tmp; + int ret = -1; + + if (!lwp_user_accessable((void *)buf, len)) + { + return -EFAULT; + } + + tmp = (char *)rt_malloc(len); + if (!tmp) + { + return -ENOMEM; + } + + ret = syslog_ctrl(type, tmp, len); + lwp_put_to_user(buf, tmp, len); + rt_free(tmp); + + return ret; +} + rt_mq_t sys_mq_create(const char *name, rt_size_t msg_size, rt_size_t max_msgs, @@ -2012,13 +1963,21 @@ static void lwp_struct_copy(struct rt_lwp *dst, struct rt_lwp *src) dst->data_entry = src->data_entry; dst->data_size = src->data_size; dst->args = src->args; - dst->leader = 0; - dst->session = src->session; dst->background = src->background; - dst->tty_old_pgrp = 0; - dst->__pgrp = src->__pgrp; dst->tty = src->tty; + + /* terminal API */ + dst->term_ctrlterm = src->term_ctrlterm; + rt_memcpy(dst->cmd, src->cmd, RT_NAME_MAX); + if (src->exe_file) + { + if (dst->exe_file) + { + rt_free(dst->exe_file); + } + dst->exe_file = strndup(src->exe_file, DFS_PATH_MAX); + } rt_memcpy(&dst->signal.sig_action, &src->signal.sig_action, sizeof(dst->signal.sig_action)); rt_memcpy(&dst->signal.sig_action_mask, &src->signal.sig_action_mask, sizeof(dst->signal.sig_action_mask)); @@ -2026,6 +1985,8 @@ static void lwp_struct_copy(struct rt_lwp *dst, struct rt_lwp *src) rt_memcpy(&dst->signal.sig_action_onstack, &src->signal.sig_action_onstack, sizeof(dst->signal.sig_action_onstack)); rt_memcpy(&dst->signal.sig_action_restart, &dst->signal.sig_action_restart, sizeof(dst->signal.sig_action_restart)); rt_memcpy(&dst->signal.sig_action_siginfo, &dst->signal.sig_action_siginfo, sizeof(dst->signal.sig_action_siginfo)); + rt_memcpy(&dst->signal.sig_action_nocldstop, &dst->signal.sig_action_nocldstop, sizeof(dst->signal.sig_action_nocldstop)); + rt_memcpy(&dst->signal.sig_action_nocldwait, &dst->signal.sig_action_nocldwait, sizeof(dst->signal.sig_action_nocldwait)); rt_strcpy(dst->working_directory, src->working_directory); } @@ -2071,6 +2032,7 @@ sysret_t _sys_fork(void) rt_thread_t thread = RT_NULL; rt_thread_t self_thread = RT_NULL; void *user_stack = RT_NULL; + rt_processgroup_t group; /* new lwp */ lwp = lwp_create(LWP_CREATE_FLAG_ALLOC_PID); @@ -2145,6 +2107,17 @@ sysret_t _sys_fork(void) lwp_children_register(self_lwp, lwp); + /* set pgid and sid */ + group = lwp_pgrp_find(lwp_pgid_get_byprocess(self_lwp)); + if (group) + { + lwp_pgrp_insert(group, lwp); + } + else + { + LOG_W("the process group of pid: %d cannot be found", lwp_pgid_get_byprocess(self_lwp)); + } + /* copy kernel stack context from self thread */ lwp_memcpy(thread->stack_addr, self_thread->stack_addr, self_thread->stack_size); lwp_tid_set_thread(tid, thread); @@ -2157,28 +2130,6 @@ sysret_t _sys_fork(void) (void *)((char *)thread->stack_addr + thread->stack_size), user_stack, &thread->sp); - /* new thread never reach there */ - LWP_LOCK(lwp); - if (lwp->tty != RT_NULL) - { - int ret; - struct rt_lwp *old_lwp; - - old_lwp = lwp->tty->foreground; - rt_mutex_take(&lwp->tty->lock, RT_WAITING_FOREVER); - ret = tty_push(&lwp->tty->head, old_lwp); - rt_mutex_release(&lwp->tty->lock); - if (ret < 0) - { - LOG_E("malloc fail!\n"); - SET_ERRNO(ENOMEM); - goto fail; - } - - lwp->tty->foreground = lwp; - } - LWP_UNLOCK(lwp); - rt_thread_startup(thread); return lwp_to_pid(lwp); fail: @@ -2246,7 +2197,7 @@ static char *_insert_args(int new_argc, char *new_argv[], struct lwp_args_info * nsize = new_argc * sizeof(char *); for (i = 0; i < new_argc; i++) { - nsize += lwp_user_strlen(new_argv[i]) + 1; + nsize += lwp_strlen(lwp_self(), new_argv[i]) + 1; } if (nsize + args->size > ARCH_PAGE_SIZE) { @@ -2260,7 +2211,7 @@ static char *_insert_args(int new_argc, char *new_argv[], struct lwp_args_info * for (i = 0; i < new_argc; i++) { nargv[i] = p; - len = lwp_user_strlen(new_argv[i]) + 1; + len = lwp_strlen(lwp_self(), new_argv[i]) + 1; lwp_memcpy(p, new_argv[i], len); p += len; } @@ -2269,7 +2220,7 @@ static char *_insert_args(int new_argc, char *new_argv[], struct lwp_args_info * for (i = 0; i < args->argc; i++) { nargv[i] = p; - len = lwp_user_strlen(args->argv[i]) + 1; + len = lwp_strlen(lwp_self(), args->argv[i]) + 1; lwp_memcpy(p, args->argv[i], len); p += len; } @@ -2278,7 +2229,7 @@ static char *_insert_args(int new_argc, char *new_argv[], struct lwp_args_info * for (i = 0; i < args->envc; i++) { nenvp[i] = p; - len = lwp_user_strlen(args->envp[i]) + 1; + len = lwp_strlen(lwp_self(), args->envp[i]) + 1; lwp_memcpy(p, args->envp[i], len); p += len; } @@ -2427,7 +2378,7 @@ int load_ldso(struct rt_lwp *lwp, char *exec_name, char *const argv[], char *con { break; } - len = lwp_user_strlen_ext(lwp, (const char *)argv[argc]); + len = lwp_strlen(lwp, (const char *)argv[argc]); size += sizeof(char *) + len + 1; argc++; } @@ -2440,7 +2391,7 @@ int load_ldso(struct rt_lwp *lwp, char *exec_name, char *const argv[], char *con { break; } - len = lwp_user_strlen_ext(lwp, (const char *)envp[envc]); + len = lwp_strlen(lwp, (const char *)envp[envc]); size += sizeof(char *) + len + 1; envc++; } @@ -2461,7 +2412,7 @@ int load_ldso(struct rt_lwp *lwp, char *exec_name, char *const argv[], char *con for (i = 0; i < argc; i++) { kargv[i] = p; - len = lwp_user_strlen_ext(lwp, argv[i]) + 1; + len = lwp_strlen(lwp, argv[i]) + 1; lwp_memcpy(p, argv[i], len); p += len; } @@ -2473,7 +2424,7 @@ int load_ldso(struct rt_lwp *lwp, char *exec_name, char *const argv[], char *con for (i = 0; i < envc; i++) { kenvp[i] = p; - len = lwp_user_strlen_ext(lwp, envp[i]) + 1; + len = lwp_strlen(lwp, envp[i]) + 1; lwp_memcpy(p, envp[i], len); p += len; } @@ -2523,7 +2474,7 @@ int load_ldso(struct rt_lwp *lwp, char *exec_name, char *const argv[], char *con ret = lwp_load("/lib/ld.so", lwp, RT_NULL, 0, aux); - rt_strncpy(lwp->cmd, exec_name, RT_NAME_MAX); + rt_strncpy(lwp->cmd, exec_name, RT_NAME_MAX - 1); quit: if (page) { @@ -2749,8 +2700,10 @@ sysret_t sys_execve(const char *path, char *const argv[], char *const envp[]) */ RT_ASSERT(rt_list_entry(lwp->t_grp.prev, struct rt_thread, sibling) == thread); - strncpy(thread->parent.name, run_name + last_backslash, RT_NAME_MAX); + strncpy(thread->parent.name, run_name + last_backslash, RT_NAME_MAX - 1); strncpy(lwp->cmd, new_lwp->cmd, RT_NAME_MAX); + rt_free(lwp->exe_file); + lwp->exe_file = strndup(new_lwp->exe_file, DFS_PATH_MAX); rt_pages_free(page, 0); @@ -4412,7 +4365,7 @@ sysret_t sys_waitpid(int32_t pid, int *status, int options) } else { - ret = lwp_waitpid(pid, status, options); + ret = lwp_waitpid(pid, status, options, RT_NULL); } #else if (!lwp_user_accessable((void *)status, sizeof(int))) @@ -4715,7 +4668,7 @@ sysret_t sys_gethostbyname2_r(const char *name, int af, struct hostent *ret, rt_strncpy(ptr, k_name, buflen - (ptr - buf)); ret->h_name = ptr; - ptr += lwp_user_strlen(k_name); + ptr += strlen(k_name); ret->h_addr_list = (char**)ptr; ptr += cnt * sizeof(char *); @@ -4733,6 +4686,10 @@ sysret_t sys_gethostbyname2_r(const char *name, int af, struct hostent *ret, #endif ret_val = 0; } + else + { + SET_ERRNO(EINVAL); + } __exit: if (ret_val < 0) @@ -4794,6 +4751,7 @@ sysret_t sys_chdir(const char *path) #ifdef ARCH_MM_MMU int err = 0; int len = 0; + int errcode; char *kpath = RT_NULL; len = lwp_user_strlen(path); @@ -4815,16 +4773,46 @@ sysret_t sys_chdir(const char *path) } err = chdir(kpath); + errcode = err != 0 ? GET_ERRNO() : 0; kmem_put(kpath); - return (err < 0 ? GET_ERRNO() : err); + return errcode; #else int ret = chdir(path); return (ret < 0 ? GET_ERRNO() : ret); #endif } +sysret_t sys_fchdir(int fd) +{ + int errcode = -ENOSYS; +#ifdef ARCH_MM_MMU +#ifdef RT_USING_DFS_V2 + int err = -1; + struct dfs_file *d; + char *kpath; + + d = fd_get(fd); + if (!d || !d->vnode) + { + return -EBADF; + } + kpath = dfs_dentry_full_path(d->dentry); + if (!kpath) + { + return -EACCES; + } + + err = chdir(kpath); + errcode = err != 0 ? GET_ERRNO() : 0; + + kmem_put(kpath); +#endif +#endif + return errcode; +} + sysret_t sys_mkdir(const char *path, mode_t mode) { #ifdef ARCH_MM_MMU @@ -5055,6 +5043,11 @@ sysret_t sys_pipe(int fd[2]) return (ret < 0 ? GET_ERRNO() : ret); } +sysret_t sys_wait4(pid_t pid, int *status, int options, struct rusage *ru) +{ + return lwp_waitpid(pid, status, options, ru); +} + sysret_t sys_clock_settime(clockid_t clk, const struct timespec *ts) { int ret = 0; @@ -5271,7 +5264,7 @@ sysret_t sys_getrlimit(unsigned int resource, unsigned long rlim[2]) } lwp_put_to_user((void *)rlim, krlim, sizeof(unsigned long [2])); - kmem_put(krlim); + return (ret < 0 ? GET_ERRNO() : ret); } @@ -5280,13 +5273,6 @@ sysret_t sys_setrlimit(unsigned int resource, struct rlimit *rlim) return -ENOSYS; } -sysret_t sys_setsid(void) -{ - int ret = 0; - ret = setsid(); - return (ret < 0 ? GET_ERRNO() : ret); -} - sysret_t sys_getrandom(void *buf, size_t buflen, unsigned int flags) { int ret = -1; @@ -5353,12 +5339,16 @@ sysret_t sys_getrandom(void *buf, size_t buflen, unsigned int flags) return ret; } +/** + * readlink() places the contents of the symbolic link pathname in the buffer buf, which has size bufsiz. + * readlink() does not append a null byte to buf. + * It will (silently) truncate the contents(to a length of bufsiz characters), + * in case the buffer is too small to hold all of the contents. + */ ssize_t sys_readlink(char* path, char *buf, size_t bufsz) { size_t len, copy_len; int err, rtn; - int fd = -1; - struct dfs_file *d; char *copy_path; len = lwp_user_strlen(path); @@ -5381,91 +5371,27 @@ ssize_t sys_readlink(char* path, char *buf, size_t bufsz) copy_len = lwp_get_from_user(copy_path, path, len); copy_path[copy_len] = '\0'; - /* musl __procfdname */ - err = sscanf(copy_path, "/proc/self/fd/%d", &fd); - - if (err != 1) + char *link_fn = (char *)rt_malloc(DFS_PATH_MAX); + if (link_fn) { - rtn = 0; - if (access(copy_path, 0)) + err = dfs_file_readlink(copy_path, link_fn, DFS_PATH_MAX); + if (err > 0) { - rtn = -ENOENT; - LOG_E("readlink: path not is /proc/self/fd/* and path not exits, call by musl __procfdname()?"); + rtn = lwp_put_to_user(buf, link_fn, bufsz > err ? err : bufsz - 1); } else { -#ifdef RT_USING_DFS_V2 - char *link_fn = (char *)rt_malloc(DFS_PATH_MAX); - if (link_fn) - { - err = dfs_file_readlink(copy_path, link_fn, DFS_PATH_MAX); - if (err > 0) - { - rtn = lwp_put_to_user(buf, link_fn, bufsz > err ? err : bufsz - 1); - } - else - { - rtn = -EIO; - } - rt_free(link_fn); - } - else - { - rtn = -ENOMEM; - } -#else - rtn = lwp_put_to_user(buf, copy_path, copy_len); -#endif + rtn = -EIO; } - rt_free(copy_path); - return rtn; + rt_free(link_fn); } else { - rt_free(copy_path); - } - - d = fd_get(fd); - if (!d) - { - return -EBADF; - } - - if (!d->vnode) - { - return -EBADF; + rtn = -ENOMEM; } -#ifdef RT_USING_DFS_V2 - { - char *fullpath = dfs_dentry_full_path(d->dentry); - if (fullpath) - { - copy_len = strlen(fullpath); - if (copy_len > bufsz) - { - copy_len = bufsz; - } - - bufsz = lwp_put_to_user(buf, fullpath, copy_len); - rt_free(fullpath); - } - else - { - bufsz = 0; - } - } -#else - copy_len = strlen(d->vnode->fullpath); - if (copy_len > bufsz) - { - copy_len = bufsz; - } - - bufsz = lwp_put_to_user(buf, d->vnode->fullpath, copy_len); -#endif - - return bufsz; + rt_free(copy_path); + return rtn; } sysret_t sys_sched_setaffinity(pid_t pid, size_t size, void *set) @@ -5511,7 +5437,6 @@ sysret_t sys_sched_getaffinity(const pid_t pid, size_t size, void *set) LWP_DEF_RETURN_CODE(rc); void *mask; struct rt_lwp *lwp; - rt_bool_t need_release = RT_FALSE; if (size <= 0 || size > sizeof(cpu_set_t)) { @@ -5529,16 +5454,8 @@ sysret_t sys_sched_getaffinity(const pid_t pid, size_t size, void *set) CPU_ZERO_S(size, mask); - if (pid == 0) - { - lwp = lwp_self(); - } - else - { - need_release = RT_TRUE; - lwp_pid_lock_take(); - lwp = lwp_from_pid_locked(pid); - } + lwp_pid_lock_take(); + lwp = lwp_from_pid_locked(pid); if (!lwp) { @@ -5569,8 +5486,7 @@ sysret_t sys_sched_getaffinity(const pid_t pid, size_t size, void *set) rc = size; } - if (need_release) - lwp_pid_lock_release(); + lwp_pid_lock_release(); kmem_put(mask); @@ -5626,12 +5542,10 @@ sysret_t sys_sysinfo(void *info) #endif } -sysret_t sys_sched_setparam(pid_t pid, void *param) +sysret_t sys_sched_setparam(pid_t tid, void *param) { struct sched_param *sched_param = RT_NULL; - struct rt_lwp *lwp = NULL; - rt_thread_t main_thread; - rt_bool_t need_release = RT_FALSE; + rt_thread_t thread; int ret = -1; if (!lwp_user_accessable(param, sizeof(struct sched_param))) @@ -5651,26 +5565,15 @@ sysret_t sys_sched_setparam(pid_t pid, void *param) return -EINVAL; } - if (pid > 0) - { - need_release = RT_TRUE; - lwp_pid_lock_take(); - lwp = lwp_from_pid_locked(pid); - } - else if (pid == 0) - { - lwp = lwp_self(); - } + thread = lwp_tid_get_thread_and_inc_ref(tid); - if (lwp) + if (thread) { - main_thread = rt_list_entry(lwp->t_grp.prev, struct rt_thread, sibling); - if (need_release) - lwp_pid_lock_release(); - - ret = rt_thread_control(main_thread, RT_THREAD_CTRL_CHANGE_PRIORITY, (void *)&sched_param->sched_priority); + ret = rt_thread_control(thread, RT_THREAD_CTRL_CHANGE_PRIORITY, (void *)&sched_param->sched_priority); } + lwp_tid_dec_ref(thread); + kmem_put(sched_param); return ret; @@ -5767,37 +5670,24 @@ sysret_t sys_sched_setscheduler(int tid, int policy, void *param) return ret; } -sysret_t sys_sched_getscheduler(int tid, int *policy, void *param) +sysret_t sys_sched_getscheduler(int tid) { - struct sched_param *sched_param = RT_NULL; rt_thread_t thread = RT_NULL; + int rtn; - if (!lwp_user_accessable(param, sizeof(struct sched_param))) - { - return -EFAULT; - } + thread = lwp_tid_get_thread_and_inc_ref(tid); + lwp_tid_dec_ref(thread); - sched_param = kmem_get(sizeof(struct sched_param)); - if (sched_param == RT_NULL) + if (thread) { - return -ENOMEM; + rtn = SCHED_RR; } - - if (lwp_get_from_user(sched_param, param, sizeof(struct sched_param)) != sizeof(struct sched_param)) + else { - kmem_put(sched_param); - return -EINVAL; + rtn = -ESRCH; } - thread = lwp_tid_get_thread_and_inc_ref(tid); - sched_param->sched_priority = RT_SCHED_PRIV(thread).current_priority; - lwp_tid_dec_ref(thread); - - lwp_put_to_user((void *)param, sched_param, sizeof(struct sched_param)); - kmem_put(sched_param); - - *policy = 0; - return 0; + return rtn; } sysret_t sys_fsync(int fd) @@ -6409,24 +6299,31 @@ sysret_t sys_epoll_ctl(int fd, int op, int fd2, struct epoll_event *ev) int ret = 0; struct epoll_event *kev = RT_NULL; - if (!lwp_user_accessable((void *)ev, sizeof(struct epoll_event))) + if (ev) + { + if (!lwp_user_accessable((void *)ev, sizeof(struct epoll_event))) return -EFAULT; - kev = kmem_get(sizeof(struct epoll_event)); - if (kev == RT_NULL) - { - return -ENOMEM; - } + kev = kmem_get(sizeof(struct epoll_event)); + if (kev == RT_NULL) + { + return -ENOMEM; + } - if (lwp_get_from_user(kev, ev, sizeof(struct epoll_event)) != sizeof(struct epoll_event)) - { - kmem_put(kev); - return -EINVAL; - } + if (lwp_get_from_user(kev, ev, sizeof(struct epoll_event)) != sizeof(struct epoll_event)) + { + kmem_put(kev); + return -EINVAL; + } - ret = epoll_ctl(fd, op, fd2, kev); + ret = epoll_ctl(fd, op, fd2, kev); - kmem_put(kev); + kmem_put(kev); + } + else + { + ret = epoll_ctl(fd, op, fd2, RT_NULL); + } return (ret < 0 ? GET_ERRNO() : ret); } @@ -6537,45 +6434,93 @@ sysret_t sys_utimensat(int __fd, const char *__path, const struct timespec __tim #endif } -sysret_t sys_chmod(const char *fileName, mode_t mode) +sysret_t sys_chmod(const char *pathname, mode_t mode) { - char *copy_fileName; - size_t len_fileName, copy_len_fileName; -#ifdef RT_USING_DFS_V2 - struct dfs_attr attr; + char *copy_file; + size_t len_file, copy_len_file; + struct dfs_attr attr = {0}; + int ret = 0; + + len_file = lwp_user_strlen(pathname); + if (len_file <= 0) + { + return -EFAULT; + } + + copy_file = (char*)rt_malloc(len_file + 1); + if (!copy_file) + { + return -ENOMEM; + } + + copy_len_file = lwp_get_from_user(copy_file, (void *)pathname, len_file); + attr.st_mode = mode; -#endif + attr.ia_valid |= ATTR_MODE_SET; + + copy_file[copy_len_file] = '\0'; + ret = dfs_file_setattr(copy_file, &attr); + rt_free(copy_file); + + return (ret < 0 ? GET_ERRNO() : ret); +} + +sysret_t sys_chown(const char *pathname, uid_t owner, gid_t group) +{ + char *copy_file; + size_t len_file, copy_len_file; + struct dfs_attr attr = {0}; int ret = 0; - len_fileName = lwp_user_strlen(fileName); - if (len_fileName <= 0) + len_file = lwp_user_strlen(pathname); + if (len_file <= 0) { return -EFAULT; } - copy_fileName = (char*)rt_malloc(len_fileName + 1); - if (!copy_fileName) + copy_file = (char*)rt_malloc(len_file + 1); + if (!copy_file) { return -ENOMEM; } - copy_len_fileName = lwp_get_from_user(copy_fileName, (void *)fileName, len_fileName); - copy_fileName[copy_len_fileName] = '\0'; -#ifdef RT_USING_DFS_V2 - ret = dfs_file_setattr(copy_fileName, &attr); -#else - SET_ERRNO(EFAULT); -#endif - rt_free(copy_fileName); + copy_len_file = lwp_get_from_user(copy_file, (void *)pathname, len_file); + + if(owner >= 0) + { + attr.st_uid = owner; + attr.ia_valid |= ATTR_UID_SET; + } + + if(group >= 0) + { + attr.st_gid = group; + attr.ia_valid |= ATTR_GID_SET; + } + + copy_file[copy_len_file] = '\0'; + ret = dfs_file_setattr(copy_file, &attr); + rt_free(copy_file); return (ret < 0 ? GET_ERRNO() : ret); } -sysret_t sys_reboot(int magic) +#include +sysret_t sys_reboot(int magic, int magic2, int type) { - rt_hw_cpu_reset(); + sysret_t rc; + switch (type) + { + /* TODO add software poweroff protocols */ + case RB_AUTOBOOT: + case RB_POWER_OFF: + rt_hw_cpu_reset(); + break; + default: + rc = -ENOSYS; + } - return 0; + return rc; } ssize_t sys_pread64(int fd, void *buf, int size, size_t offset) @@ -6824,6 +6769,59 @@ sysret_t sys_setitimer(int which, const struct itimerspec *restrict new, struct return rc; } +sysret_t sys_set_robust_list(struct robust_list_head *head, size_t len) +{ + if (len != sizeof(*head)) + return -EINVAL; + + rt_thread_self()->robust_list = head; + return 0; +} + +sysret_t sys_get_robust_list(int tid, struct robust_list_head **head_ptr, size_t *len_ptr) +{ + rt_thread_t thread; + size_t len; + struct robust_list_head *head; + + if (!lwp_user_accessable((void *)head_ptr, sizeof(struct robust_list_head *))) + { + return -EFAULT; + } + if (!lwp_user_accessable((void *)len_ptr, sizeof(size_t))) + { + return -EFAULT; + } + + if (tid == 0) + { + thread = rt_thread_self(); + head = thread->robust_list; + } + else + { + thread = lwp_tid_get_thread_and_inc_ref(tid); + if (thread) + { + head = thread->robust_list; + lwp_tid_dec_ref(thread); + } + else + { + return -ESRCH; + } + } + + len = sizeof(*(head)); + + if (!lwp_put_to_user(len_ptr, &len, sizeof(size_t))) + return -EFAULT; + if (!lwp_put_to_user(head_ptr, &head, sizeof(struct robust_list_head *))) + return -EFAULT; + + return 0; +} + const static struct rt_syscall_def func_table[] = { SYSCALL_SIGN(sys_exit), /* 01 */ @@ -6994,22 +6992,22 @@ const static struct rt_syscall_def func_table[] = SYSCALL_SIGN(sys_clock_settime), SYSCALL_SIGN(sys_clock_gettime), SYSCALL_SIGN(sys_clock_getres), - SYSCALL_USPACE(SYSCALL_SIGN(sys_clone)), /* 130 */ + SYSCALL_USPACE(SYSCALL_SIGN(sys_clone)), /* 130 */ SYSCALL_USPACE(SYSCALL_SIGN(sys_futex)), - SYSCALL_USPACE(SYSCALL_SIGN(sys_pmutex)), + SYSCALL_SIGN(sys_notimpl), /* discarded: sys_pmutex */ SYSCALL_SIGN(sys_dup), SYSCALL_SIGN(sys_dup2), - SYSCALL_SIGN(sys_rename), /* 135 */ + SYSCALL_SIGN(sys_rename), /* 135 */ SYSCALL_USPACE(SYSCALL_SIGN(sys_fork)), SYSCALL_USPACE(SYSCALL_SIGN(sys_execve)), SYSCALL_USPACE(SYSCALL_SIGN(sys_vfork)), SYSCALL_SIGN(sys_gettid), - SYSCALL_SIGN(sys_prlimit64), /* 140 */ + SYSCALL_SIGN(sys_prlimit64), /* 140 */ SYSCALL_SIGN(sys_getrlimit), SYSCALL_SIGN(sys_setrlimit), SYSCALL_SIGN(sys_setsid), SYSCALL_SIGN(sys_getrandom), - SYSCALL_SIGN(sys_readlink), // SYSCALL_SIGN(sys_readlink) /* 145 */ + SYSCALL_SIGN(sys_readlink), /* 145 */ SYSCALL_USPACE(SYSCALL_SIGN(sys_mremap)), SYSCALL_USPACE(SYSCALL_SIGN(sys_madvise)), SYSCALL_SIGN(sys_sched_setparam), @@ -7044,7 +7042,7 @@ const static struct rt_syscall_def func_table[] = SYSCALL_SIGN(sys_umount2), SYSCALL_SIGN(sys_link), SYSCALL_SIGN(sys_symlink), - SYSCALL_SIGN(sys_sched_getaffinity), /* 180 */ + SYSCALL_SIGN(sys_sched_getaffinity), /* 180 */ SYSCALL_SIGN(sys_sysinfo), SYSCALL_SIGN(sys_chmod), SYSCALL_SIGN(sys_reboot), @@ -7069,12 +7067,21 @@ const static struct rt_syscall_def func_table[] = SYSCALL_SIGN(sys_setitimer), SYSCALL_SIGN(sys_utimensat), #ifdef RT_USING_POSIX_SOCKET - SYSCALL_SIGN(sys_notimpl), - SYSCALL_SIGN(sys_socketpair), /* 205 */ + SYSCALL_SIGN(sys_syslog), + SYSCALL_SIGN(sys_socketpair), /* 205 */ #else SYSCALL_SIGN(sys_notimpl), - SYSCALL_SIGN(sys_notimpl), + SYSCALL_SIGN(sys_notimpl), /* 205 */ #endif + SYSCALL_SIGN(sys_wait4), + SYSCALL_SIGN(sys_set_robust_list), + SYSCALL_SIGN(sys_get_robust_list), + SYSCALL_SIGN(sys_setpgid), + SYSCALL_SIGN(sys_getpgid), /* 210 */ + SYSCALL_SIGN(sys_getsid), + SYSCALL_SIGN(sys_getppid), + SYSCALL_SIGN(sys_fchdir), + SYSCALL_SIGN(sys_chown), }; const void *lwp_get_sys_api(rt_uint32_t number) diff --git a/components/lwp/lwp_syscall.h b/components/lwp/lwp_syscall.h index b7e7b09f553..1527a764f11 100644 --- a/components/lwp/lwp_syscall.h +++ b/components/lwp/lwp_syscall.h @@ -108,10 +108,15 @@ sysret_t sys_log(const char* log, int size); #ifdef ARCH_MM_MMU sysret_t sys_futex(int *uaddr, int op, int val, const struct timespec *timeout, int *uaddr2, int val3); -sysret_t sys_pmutex(void *umutex, int op, void *arg); sysret_t sys_cacheflush(void *addr, int len, int cache); #endif /* ARCH_MM_MMU */ +sysret_t sys_setsid(void); +sysret_t sys_getsid(pid_t pid); +sysret_t sys_setpgid(pid_t pid, pid_t pgid); +sysret_t sys_getpgid(pid_t pid); + + #ifdef __cplusplus } #endif diff --git a/components/lwp/lwp_tid.c b/components/lwp/lwp_tid.c index fdac54a36f6..3e330027de7 100644 --- a/components/lwp/lwp_tid.c +++ b/components/lwp/lwp_tid.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2021-01-15 shaojinchun first version + * 2023-11-16 xqyjlj Fix the case where tid is 0 */ #define DBG_TAG "lwp.tid" @@ -126,20 +127,28 @@ void lwp_tid_put(int tid) lwp_mutex_release_safe(&tid_lock); } -rt_thread_t lwp_tid_get_thread_and_inc_ref(int tid) +rt_thread_t lwp_tid_get_thread_raw(int tid) { struct lwp_avl_struct *p; rt_thread_t thread = RT_NULL; - lwp_mutex_take_safe(&tid_lock, RT_WAITING_FOREVER, 0); p = lwp_avl_find(tid, lwp_tid_root); if (p) { thread = (rt_thread_t)p->data; - if (thread != RT_NULL) - { - thread->tid_ref_count += 1; - } + } + return thread; +} + +rt_thread_t lwp_tid_get_thread_and_inc_ref(int tid) +{ + rt_thread_t thread = RT_NULL; + + lwp_mutex_take_safe(&tid_lock, RT_WAITING_FOREVER, 0); + thread = tid ? lwp_tid_get_thread_raw(tid) : rt_thread_self(); + if (thread != RT_NULL) + { + thread->tid_ref_count += 1; } lwp_mutex_release_safe(&tid_lock); return thread; diff --git a/components/lwp/lwp_user_mm.c b/components/lwp/lwp_user_mm.c index 3c23e59e05f..084b5bcf281 100644 --- a/components/lwp/lwp_user_mm.c +++ b/components/lwp/lwp_user_mm.c @@ -23,10 +23,7 @@ #ifdef ARCH_MM_MMU -#include -#include -#include -#include +#include "lwp_internal.h" #include #include @@ -161,10 +158,10 @@ void lwp_aspace_switch(struct rt_thread *thread) void lwp_unmap_user_space(struct rt_lwp *lwp) { - arch_user_space_free(lwp); + if (lwp->aspace) + arch_user_space_free(lwp); } - static void *_lwp_map_user(struct rt_lwp *lwp, void *map_va, size_t map_size, int text) { @@ -566,6 +563,14 @@ int lwp_munmap(struct rt_lwp *lwp, void *addr, size_t length) return lwp_errno_to_posix(ret); } +void *lwp_mremap(struct rt_lwp *lwp, void *old_address, size_t old_size, + size_t new_size, int flags, void *new_address) +{ + RT_ASSERT(lwp); + + return rt_aspace_mremap_range(lwp->aspace, old_address, old_size, new_size, flags, new_address); +} + size_t lwp_get_from_user(void *dst, void *src, size_t size) { struct rt_lwp *lwp = RT_NULL; @@ -621,11 +626,6 @@ size_t lwp_put_to_user(void *dst, void *src, size_t size) return lwp_data_put(lwp, dst, src, size); } -rt_inline rt_bool_t _in_user_space(const char *addr) -{ - return (addr >= (char *)USER_VADDR_START && addr < (char *)USER_VADDR_TOP); -} - rt_inline rt_bool_t _can_unaligned_access(const char *addr) { return rt_kmem_v2p((char *)addr) - PV_OFFSET == addr; @@ -636,9 +636,9 @@ void *lwp_memcpy(void * __restrict dst, const void * __restrict src, size_t size void *rc = dst; long len; - if (_in_user_space(dst)) + if (lwp_in_user_space(dst)) { - if (!_in_user_space(src)) + if (!lwp_in_user_space(src)) { len = lwp_put_to_user(dst, (void *)src, size); if (!len) @@ -654,7 +654,7 @@ void *lwp_memcpy(void * __restrict dst, const void * __restrict src, size_t size } else { - if (_in_user_space(src)) + if (lwp_in_user_space(src)) { len = lwp_get_from_user(dst, (void *)src, size); if (!len) @@ -979,6 +979,13 @@ size_t lwp_user_strlen(const char *s) return lwp_user_strlen_ext(lwp, s); } +size_t lwp_strlen(struct rt_lwp *lwp, const char *s) +{ + if (lwp_in_user_space(s)) + return lwp_user_strlen_ext(lwp, s); + else + return strlen(s); +} char** lwp_get_command_line_args(struct rt_lwp *lwp) { diff --git a/components/lwp/lwp_user_mm.h b/components/lwp/lwp_user_mm.h index cfc5b571528..232038c9148 100644 --- a/components/lwp/lwp_user_mm.h +++ b/components/lwp/lwp_user_mm.h @@ -56,6 +56,9 @@ void* lwp_mmap2(struct rt_lwp *lwp, void *addr, size_t length, int prot, int fla */ int lwp_munmap(struct rt_lwp *lwp, void *addr, size_t length); +void *lwp_mremap(struct rt_lwp *lwp, void *old_address, size_t old_size, + size_t new_size, int flags, void *new_address); + /** * @brief Test if address from user is accessible address by user * @@ -163,6 +166,7 @@ rt_base_t lwp_brk(void *addr); size_t lwp_user_strlen(const char *s); size_t lwp_user_strlen_ext(struct rt_lwp *lwp, const char *s); +size_t lwp_strlen(struct rt_lwp *lwp, const char *s); int lwp_fork_aspace(struct rt_lwp *dest_lwp, struct rt_lwp *src_lwp); diff --git a/components/lwp/terminal/Kconfig b/components/lwp/terminal/Kconfig new file mode 100644 index 00000000000..7fd77e75055 --- /dev/null +++ b/components/lwp/terminal/Kconfig @@ -0,0 +1,13 @@ +menuconfig LWP_USING_TERMINAL + bool "Terminal I/O Subsystem" + depends on RT_USING_SMART + default y + +if LWP_USING_TERMINAL + config LWP_PTY_MAX_PARIS_LIMIT + int "Max number of pty devices registered at the same time" + default 64 + help + This upper limit is set to protect kernel memory from draining + out by the application if it keeps allocating pty devices. +endif diff --git a/components/lwp/terminal/bsd_porting.h b/components/lwp/terminal/bsd_porting.h new file mode 100644 index 00000000000..fba8f47fb38 --- /dev/null +++ b/components/lwp/terminal/bsd_porting.h @@ -0,0 +1,741 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-13 Shell Add compatible layer for FreeBSD + */ + +#ifndef __LWP_TTY_BSD_PORTING_H__ +#define __LWP_TTY_BSD_PORTING_H__ + +#include +#include +#define _KERNEL + +#ifndef __unused +#define __unused __attribute__((__unused__)) +#endif + +/* functionability of bsd tty layer */ +#if 0 +#define USING_BSD_HOOK +#endif + +/* Only for devfs d_close() flags. */ +#define FLASTCLOSE O_DIRECTORY +#define FREVOKE 0x00200000 + +/* + * Output flags - software output processing + */ +#if !((OPOST | OLCUC | ONLCR) & 0x8) +#define ONOEOT 0x0008 /* discard EOT's (^D) on output) */ +#endif + +/* + * Kernel encoding of open mode; separate read and write bits that are + * independently testable: 1 greater than the above. + * + * XXX + * FREAD and FWRITE are excluded from the #ifdef _KERNEL so that TIOCFLUSH, + * which was documented to use FREAD/FWRITE, continues to work. + */ +#define FREAD 0x0001 +#define FWRITE 0x0002 + +/* + * Flags to memory allocation functions. + */ +#define M_NOWAIT 0x0001 /* do not block */ +#define M_WAITOK 0x0002 /* ok to block */ +#define M_NORECLAIM 0x0080 /* do not reclaim after failure */ +#define M_ZERO 0x0100 /* bzero the allocation */ +#define M_NOVM 0x0200 /* don't ask VM for pages */ +#define M_USE_RESERVE 0x0400 /* can alloc out of reserve memory */ +#define M_NODUMP 0x0800 /* don't dump pages in this allocation */ +#define M_FIRSTFIT 0x1000 /* only for vmem, fast fit */ +#define M_BESTFIT 0x2000 /* only for vmem, low fragmentation */ +#define M_EXEC 0x4000 /* allocate executable space */ +#define M_NEXTFIT 0x8000 /* only for vmem, follow cursor */ + +#define M_VERSION 2020110501 + +/* + * The INVARIANTS-enabled mtx_assert() functionality. + * + * The constants need to be defined for INVARIANT_SUPPORT infrastructure + * support as _mtx_assert() itself uses them and the latter implies that + * _mtx_assert() must build. + */ +#define MA_OWNED (1) +#define MA_NOTOWNED (2) +#define MA_RECURSED (4) +#define MA_NOTRECURSED (8) + +/* + * Indentification of modem control signals. These definitions match + * the TIOCMGET definitions in shifted a bit down, and + * that identity is enforced with CTASSERT at the bottom of kern/tty.c + * Both the modem bits and delta bits must fit in 16 bit. + */ +#define SER_DTR 0x0001 /* data terminal ready */ +#define SER_RTS 0x0002 /* request to send */ +#define SER_STX 0x0004 /* secondary transmit */ +#define SER_SRX 0x0008 /* secondary receive */ +#define SER_CTS 0x0010 /* clear to send */ +#define SER_DCD 0x0020 /* data carrier detect */ +#define SER_RI 0x0040 /* ring indicate */ +#define SER_DSR 0x0080 /* data set ready */ + +#define SER_MASK_STATE 0x00ff + +/* + * Flags for ioflag. (high 16 bits used to ask for read-ahead and + * help with write clustering) + * NB: IO_NDELAY and IO_DIRECT are linked to fcntl.h + */ +#if 0 +#define IO_UNIT 0x0001 /* do I/O as atomic unit */ +#define IO_APPEND 0x0002 /* append write to end */ +#endif /* not porting */ + +#define IO_NDELAY 0x0004 /* FNDELAY flag set in file table */ +#if 0 +#define IO_NODELOCKED 0x0008 /* underlying node already locked */ +#define IO_ASYNC 0x0010 /* bawrite rather then bdwrite */ +#define IO_VMIO 0x0020 /* data already in VMIO space */ +#define IO_INVAL 0x0040 /* invalidate after I/O */ +#define IO_SYNC 0x0080 /* do I/O synchronously */ +#define IO_DIRECT 0x0100 /* attempt to bypass buffer cache */ +#define IO_NOREUSE 0x0200 /* VMIO data won't be reused */ +#define IO_EXT 0x0400 /* operate on external attributes */ +#define IO_NORMAL 0x0800 /* operate on regular data */ +#define IO_NOMACCHECK 0x1000 /* MAC checks unnecessary */ +#define IO_BUFLOCKED 0x2000 /* ffs flag; indir buf is locked */ +#define IO_RANGELOCKED 0x4000 /* range locked */ +#define IO_DATASYNC 0x8000 /* do only data I/O synchronously */ + +#define IO_SEQMAX 0x7F /* seq heuristic max value */ +#define IO_SEQSHIFT 16 /* seq heuristic in upper 16 bits */ +#endif /* not porting */ + +/** Used to distinguish between normal, callout, lock and init devices. + * Note: this is not used in smart system. + */ +#define TTYUNIT_INIT 0x1 +#define TTYUNIT_LOCK 0x2 +#define TTYUNIT_CALLOUT 0x4 + +/* + * TTY privileges. + */ +#define PRIV_TTY_CONSOLE 250 /* Set console to tty. */ +#define PRIV_TTY_DRAINWAIT 251 /* Set tty drain wait time. */ +#define PRIV_TTY_DTRWAIT 252 /* Set DTR wait on tty. */ +#define PRIV_TTY_EXCLUSIVE 253 /* Override tty exclusive flag. */ +#define _PRIV_TTY_PRISON 254 /* Removed. */ +#define PRIV_TTY_STI 255 /* Simulate input on another tty. */ +#define PRIV_TTY_SETA 256 /* Set tty termios structure. */ + +#define MPASS(ex) RT_ASSERT(ex) + +#if !defined(MIN) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif + +#define curthread rt_thread_self() + +#ifdef USING_BSD_HOOK +#define ttyhook_hashook(tp, hook) \ + ((tp)->t_hook != NULL && (tp)->t_hook->th_##hook != NULL) +#else +#define ttyhook_hashook(tp, hook) (RT_FALSE) +#endif + +/* condvar API */ +#include + +#define cv_init(cvp, name) rt_condvar_init(cvp, name) +#define cv_destroy(cvp) rt_condvar_detach(cvp) +#define cv_wait(cvp, mp) \ + rt_condvar_timedwait(cvp, mp, RT_KILLABLE, RT_WAITING_FOREVER) +#define cv_wait_sig(cvp, mp) \ + rt_condvar_timedwait(cvp, mp, RT_INTERRUPTIBLE, RT_WAITING_FOREVER) +#define cv_signal(cvp) rt_condvar_signal(cvp) +#define cv_broadcast(cvp) rt_condvar_broadcast(cvp) +#define cv_timedwait(cvp, mp, t) rt_condvar_timedwait(cvp, mp, RT_KILLABLE, t) +#define cv_timedwait_sig(cvp, mp, t) \ + rt_condvar_timedwait(cvp, mp, RT_INTERRUPTIBLE, t) + +struct lwp_tty; +struct uio; + +/* TODO: just a place holder since devfs is not capable of doing this currently + */ +struct file +{ +}; + +typedef rt_base_t sbintime_t; +typedef rt_ubase_t vm_offset_t; +typedef rt_base_t vm_ooffset_t; +typedef rt_ubase_t vm_paddr_t; +typedef rt_ubase_t vm_pindex_t; +typedef rt_ubase_t vm_size_t; +typedef char *rt_caddr_t; + +/* + * The exact set of memory attributes is machine dependent. However, + * every machine is required to define VM_MEMATTR_DEFAULT and + * VM_MEMATTR_UNCACHEABLE. + */ +typedef char vm_memattr_t; /* memory attribute codes */ + +typedef int d_open_t(struct lwp_tty *tp, int oflags, int devtype, + struct rt_thread *td); +typedef int d_fdopen_t(struct lwp_tty *tp, int oflags, struct rt_thread *td, + struct file *fp); +typedef int d_close_t(struct lwp_tty *tp, int fflag, int devtype, + struct rt_thread *td); + +#ifdef USING_BSD_DEVICE_STRATEGY +typedef void d_strategy_t(struct bio *bp); +#endif + +typedef int d_ioctl_t(struct lwp_tty *tp, rt_ubase_t cmd, rt_caddr_t data, + int fflag, struct rt_thread *td); + +typedef int d_read_t(struct lwp_tty *tp, struct uio *uio, int ioflag); +typedef int d_write_t(struct lwp_tty *tp, struct uio *uio, int ioflag); +typedef int d_poll_t(struct lwp_tty *tp, rt_pollreq_t *req, + struct rt_thread *td); + +#ifdef USING_BSD_KNOTE +typedef int d_kqfilter_t(struct lwp_tty *tp, struct knote *kn); +#endif /* USING_BSD_KNOTE */ + +typedef int d_mmap_t(struct lwp_tty *tp, vm_ooffset_t offset, vm_paddr_t *paddr, + int nprot, vm_memattr_t *memattr); + +#ifdef USING_BSD_MMAP_SINGLE +typedef int d_mmap_single_t(struct cdev *cdev, vm_ooffset_t *offset, + vm_size_t size, struct vm_object **object, + int nprot); +#endif /* USING_BSD_MMAP_SINGLE */ + +typedef void d_purge_t(struct lwp_tty *tp); + +/* + * Character device switch table + */ +struct cdevsw +{ +#ifdef USING_BSD_RAW_CDEVSW + int d_version; + u_int d_flags; + const char *d_name; +#endif /* USING_BSD_RAW_CDEVSW */ + + d_open_t *d_open; + d_fdopen_t *d_fdopen; + d_close_t *d_close; + d_read_t *d_read; + d_write_t *d_write; + d_ioctl_t *d_ioctl; + d_poll_t *d_poll; + d_mmap_t *d_mmap; +#ifdef USING_BSD_DEVICE_STRATEGY + d_strategy_t *d_strategy; +#endif /* USING_BSD_DEVICE_STRATEGY */ + +#ifdef USING_BSD_RAW_CDEVSW + void *d_spare0; + d_kqfilter_t *d_kqfilter; + d_purge_t *d_purge; + d_mmap_single_t *d_mmap_single; + + int32_t d_spare1[3]; + void *d_spare2[3]; + + /* These fields should not be messed with by drivers */ + LIST_HEAD(, cdev) d_devs; + int d_spare3; + union + { + struct cdevsw *gianttrick; + SLIST_ENTRY(cdevsw) postfree_list; + } __d_giant; +#endif +}; + +struct iovec +{ + void *iov_base; /* Base address. */ + size_t iov_len; /* Length. */ +}; + +enum uio_rw +{ + UIO_READ, + UIO_WRITE +}; + +struct uio +{ + struct iovec *uio_iov; /* scatter/gather list */ + int uio_iovcnt; /* length of scatter/gather list */ + off_t uio_offset; /* offset in target object */ + ssize_t uio_resid; /* remaining bytes to process */ +#ifdef USING_BSD_UIO + enum uio_seg uio_segflg; /* address space */ +#endif + enum uio_rw uio_rw; /* operation */ +#ifdef USING_BSD_UIO + struct rt_thread *uio_td; /* owner */ + +#endif /* USING_BSD_UIO */ +}; + +#include +rt_inline int uiomove(void *operand, int n, struct uio *uio) +{ + switch (uio->uio_rw) + { + case UIO_READ: + memcpy(uio->uio_iov->iov_base, operand, n); + break; + case UIO_WRITE: + memcpy(operand, uio->uio_iov->iov_base, n); + break; + default: + return -1; + } + + uio->uio_iov->iov_base += n; + uio->uio_iov->iov_len--; + uio->uio_offset += n; + uio->uio_resid -= n; + return 0; +} + +/* privileges checking: 0 if okay */ +rt_inline int priv_check(struct rt_thread *td, int priv) +{ + return 0; +} + +/* Disable console redirection to a tty. */ +rt_inline int constty_clear(struct lwp_tty *tp) +{ + // rt_kprintf("\nTODO: %s unimplemented!\n", __func__); + return 0; +} + +rt_inline int constty_set(struct lwp_tty *tp) +{ + // rt_kprintf("\nTODO: %s unimplemented!\n", __func__); + return 0; +} + +/** + * UMA (Universal Memory Allocator) + */ +#define UMA_ALIGN_PTR (sizeof(void *) - 1) /* Alignment fit for ptr */ + +typedef int (*uma_ctor)(void *mem, int size, void *arg, int flags); +typedef void (*uma_dtor)(void *mem, int size, void *arg); +typedef int (*uma_init)(void *mem, int size, int flags); +typedef void (*uma_fini)(void *mem, int size); + +struct uma_zone +{ + char *name; + int align; + int size; +}; + +/* Opaque type used as a handle to the zone */ +typedef struct uma_zone *uma_zone_t; + +rt_inline uma_zone_t uma_zcreate(char *name, int size, uma_ctor ctor, + uma_dtor dtor, uma_init zinit, uma_fini zfini, + int align, uint16_t flags) +{ + uma_zone_t zone = rt_malloc(sizeof(struct uma_zone)); + if (zone) + { + RT_ASSERT(ctor == RT_NULL); + RT_ASSERT(dtor == RT_NULL); + RT_ASSERT(zinit == RT_NULL); + RT_ASSERT(zfini == RT_NULL); + + zone->size = size; + zone->name = name; + zone->align = align; + } + return zone; +} + +rt_inline void *uma_zalloc(uma_zone_t zone, int flags) +{ + void *buf = rt_malloc_align(zone->size, zone->align + 1); + if (buf) + rt_memset(buf, 0, sizeof(zone->size)); + return buf; +} + +rt_inline void uma_zfree(uma_zone_t zone, void *item) +{ + rt_free_align(item); +} + +/** + * bsd type of speed to linux type. + * Note: with switch blocks, compiler can generate the optimized version for us + */ +#include +rt_inline long bsd_speed_to_integer(speed_t speed) +{ + long speed_value; + switch (speed) + { + case B0: + speed_value = 0; + break; + case B50: + speed_value = 50; + break; + case B75: + speed_value = 75; + break; + case B110: + speed_value = 110; + break; + case B134: + speed_value = 134; + break; + case B150: + speed_value = 150; + break; + case B200: + speed_value = 200; + break; + case B300: + speed_value = 300; + break; + case B600: + speed_value = 600; + break; + case B1200: + speed_value = 1200; + break; + case B1800: + speed_value = 1800; + break; + case B2400: + speed_value = 2400; + break; + case B4800: + speed_value = 4800; + break; + case B9600: + speed_value = 9600; + break; + case B19200: + speed_value = 19200; + break; + case B38400: + speed_value = 38400; + break; + case B57600: + speed_value = 57600; + break; + case B115200: + speed_value = 115200; + break; + case B230400: + speed_value = 230400; + break; + case B460800: + speed_value = 460800; + break; + case B500000: + speed_value = 500000; + break; + case B576000: + speed_value = 576000; + break; + case B921600: + speed_value = 921600; + break; + case B1000000: + speed_value = 1000000; + break; + case B1152000: + speed_value = 1152000; + break; + case B1500000: + speed_value = 1500000; + break; + case B2000000: + speed_value = 2000000; + break; + case B2500000: + speed_value = 2500000; + break; + case B3000000: + speed_value = 3000000; + break; + case B3500000: + speed_value = 3500000; + break; + case B4000000: + speed_value = 4000000; + break; + default: + speed_value = -1; // invalid speed + break; + } + return speed_value; +} + +/* time.h */ + +/* Operations on timevals. */ + +#define timevalclear(tvp) ((tvp)->tv_sec = (tvp)->tv_usec = 0) +#define timevalisset(tvp) ((tvp)->tv_sec || (tvp)->tv_usec) +#define timevalcmp(tvp, uvp, cmp) \ + (((tvp)->tv_sec == (uvp)->tv_sec) ? ((tvp)->tv_usec cmp(uvp)->tv_usec) \ + : ((tvp)->tv_sec cmp(uvp)->tv_sec)) + +rt_inline void getmicrotime(struct timeval *now) +{ + gettimeofday(now, RT_NULL); +} + +rt_inline void timevalfix(struct timeval *tv) +{ + if (tv->tv_usec < 0) + { + tv->tv_sec--; + tv->tv_usec += 1000000; + } + if (tv->tv_usec >= 1000000) + { + tv->tv_sec++; + tv->tv_usec -= 1000000; + } +} + +rt_inline void timevaladd(struct timeval *op1, const struct timeval *op2) +{ + op1->tv_sec += op2->tv_sec; + op1->tv_usec += op2->tv_usec; + timevalfix(op1); +} + +rt_inline void timevalsub(struct timeval *op1, const struct timeval *op2) +{ + op1->tv_sec -= op2->tv_sec; + op1->tv_usec -= op2->tv_usec; + timevalfix(op1); +} + +rt_inline rt_tick_t tvtohz(struct timeval *tv) +{ + rt_tick_t rc; + rc = tv->tv_sec * RT_TICK_PER_SECOND; + rc += tv->tv_usec * RT_TICK_PER_SECOND / MICROSECOND_PER_SECOND; + return rc; +} + +/* ioctl */ +#define _BSD_TIOCTL(val) ((val) << 16) +enum bsd_ioctl_cmd +{ + BSD_TIOCDRAIN = 1, + BSD_TIOCFLUSH, + BSD_TIOCSTART, + BSD_TIOCSTOP, + BSD_TIOCSTAT, + BSD_TIOCGDRAINWAIT, + BSD_TIOCSDRAINWAIT, + BSD_TIOCSDTR, + BSD_TIOCCDTR, +}; + +#ifndef TIOCGETA /* get termios struct */ +#define TIOCGETA TCGETS +#endif +#ifndef TIOCSETA /* set termios struct */ +#define TIOCSETA TCSETS +#endif +#ifndef TIOCSETAW /* drain output, set */ +#define TIOCSETAW TCSETSW +#endif +#ifndef TIOCSETAF /* drn out, fls in, set */ +#define TIOCSETAF TCSETSF +#endif +#ifndef TIOCDRAIN /* wait till output drained */ +#define TIOCDRAIN _BSD_TIOCTL(BSD_TIOCDRAIN) +#endif +#ifndef TIOCFLUSH /* flush buffers */ +#define TIOCFLUSH _BSD_TIOCTL(BSD_TIOCFLUSH) +#endif +#ifndef TIOCSTART /* start output, like ^Q */ +#define TIOCSTART _BSD_TIOCTL(BSD_TIOCSTART) +#endif +#ifndef TIOCSTOP /* stop output, like ^S */ +#define TIOCSTOP _BSD_TIOCTL(BSD_TIOCSTOP) +#endif +#ifndef TIOCSTAT /* simulate ^T status message */ +#define TIOCSTAT _BSD_TIOCTL(BSD_TIOCSTAT) +#endif +#ifndef TIOCGDRAINWAIT /* get ttywait timeout */ +#define TIOCGDRAINWAIT _BSD_TIOCTL(BSD_TIOCGDRAINWAIT) +#endif +#ifndef TIOCSDRAINWAIT /* set ttywait timeout */ +#define TIOCSDRAINWAIT _BSD_TIOCTL(BSD_TIOCSDRAINWAIT) +#endif +#ifndef TIOCSDTR /* set data terminal ready */ +#define TIOCSDTR _BSD_TIOCTL(BSD_TIOCSDTR) +#endif +#ifndef TIOCCDTR /* clear data terminal ready */ +#define TIOCCDTR _BSD_TIOCTL(BSD_TIOCCDTR) +#endif + +#define ENOIOCTL ENOSYS +#define NO_PID -1 + +/* line discipline */ +#define TTYDISC 0 /* termios tty line discipline */ +#define SLIPDISC 4 /* serial IP discipline */ +#define PPPDISC 5 /* PPP discipline */ +#define NETGRAPHDISC 6 /* Netgraph tty node discipline */ +#define H4DISC 7 /* Netgraph Bluetooth H4 discipline */ + +/* + * Control flags - hardware control of terminal + */ +#if __BSD_VISIBLE +#define CIGNORE 0x00000001 /* ignore control flags */ +#define CCTS_OFLOW 0x00010000 /* CTS flow control of output */ +#define CRTSCTS (CCTS_OFLOW | CRTS_IFLOW) +#define CRTS_IFLOW 0x00020000 /* RTS flow control of input */ +#define CDTR_IFLOW 0x00040000 /* DTR flow control of input */ +#define CDSR_OFLOW 0x00080000 /* DSR flow control of output */ +#define CCAR_OFLOW 0x00100000 /* DCD flow control of output */ +#define CNO_RTSDTR 0x00200000 /* Do not assert RTS or DTR automatically */ +#else +#define CIGNORE 0 /* ignore control flags */ +#define CCTS_OFLOW 0 /* CTS flow control of output */ +#define CRTS_IFLOW 0 /* RTS flow control of input */ +#define CDTR_IFLOW 0 /* DTR flow control of input */ +#define CDSR_OFLOW 0 /* DSR flow control of output */ +#define CCAR_OFLOW 0 /* DCD flow control of output */ +#define CNO_RTSDTR 0 /* Do not assert RTS or DTR automatically */ +#endif + +#ifndef CRTSCTS +#define CRTSCTS (CCTS_OFLOW | CRTS_IFLOW) +#endif + +#ifndef howmany +#define howmany(x, y) (((x) + ((y)-1)) / (y)) +#endif + +struct ucred +{ +}; +#define NOCRED ((struct ucred *)0) /* no credential available */ +#define FSCRED ((struct ucred *)-1) /* filesystem credential */ + +/* convert from open() flags to/from fflags; convert O_RD/WR to FREAD/FWRITE */ +#include +#define FFLAGS(oflags) ((oflags)&O_EXEC ? (oflags) : (oflags) + 1) +#define OFLAGS(fflags) \ + (((fflags) & (O_EXEC | O_PATH)) != 0 ? (fflags) : (fflags)-1) + +typedef int fo_rdwr_t(struct lwp_tty *tp, struct uio *uio, + struct ucred *active_cred, int flags, + struct rt_thread *td); +typedef int fo_truncate_t(struct lwp_tty *tp, off_t length, + struct ucred *active_cred, struct rt_thread *td); +typedef int fo_ioctl_t(struct lwp_tty *tp, rt_ubase_t com, void *data, + struct ucred *active_cred, int fflags, struct rt_thread *td); +typedef int fo_poll_t(struct lwp_tty *tp, struct rt_pollreq *rq, struct ucred *active_cred, + struct rt_thread *td); +typedef int fo_stat_t(struct lwp_tty *tp, struct stat *sb, + struct ucred *active_cred); +typedef int fo_close_t(struct lwp_tty *tp, struct rt_thread *td); + +#ifdef USING_BSD_FO_EXT +typedef int fo_chmod_t(struct file *fp, mode_t mode, struct ucred *active_cred, + struct rt_thread *td); +typedef int fo_chown_t(struct file *fp, uid_t uid, gid_t gid, + struct ucred *active_cred, struct rt_thread *td); +typedef int fo_sendfile_t(struct file *fp, int sockfd, struct uio *hdr_uio, + struct uio *trl_uio, off_t offset, size_t nbytes, + off_t *sent, int flags, struct rt_thread *td); +typedef int fo_seek_t(struct file *fp, off_t offset, int whence, + struct rt_thread *td); + +typedef int fo_kqfilter_t(struct file *fp, struct knote *kn); +typedef int fo_fill_kinfo_t(struct file *fp, struct kinfo_file *kif, + struct filedesc *fdp); +typedef int fo_mmap_t(struct file *fp, vm_map_t map, vm_offset_t *addr, + vm_size_t size, vm_prot_t prot, vm_prot_t cap_maxprot, + int flags, vm_ooffset_t foff, struct rt_thread *td); +typedef int fo_aio_queue_t(struct file *fp, struct kaiocb *job); + +typedef int fo_add_seals_t(struct file *fp, int flags); +typedef int fo_get_seals_t(struct file *fp, int *flags); +typedef int fo_fallocate_t(struct file *fp, off_t offset, off_t len, + struct rt_thread *td); +typedef int fo_fspacectl_t(struct file *fp, int cmd, off_t *offset, + off_t *length, int flags, struct ucred *active_cred, + struct rt_thread *td); +typedef int fo_spare_t(struct file *fp); +#endif /* USING_BSD_FO_EXT */ + +typedef int fo_flags_t; + +struct bsd_fileops +{ + fo_rdwr_t *fo_read; + fo_rdwr_t *fo_write; + fo_truncate_t *fo_truncate; + fo_ioctl_t *fo_ioctl; + fo_poll_t *fo_poll; + fo_stat_t *fo_stat; + fo_close_t *fo_close; +#ifdef USING_BSD_FO_EXT + fo_chmod_t *fo_chmod; + fo_chown_t *fo_chown; + fo_sendfile_t *fo_sendfile; + fo_seek_t *fo_seek; + fo_kqfilter_t *fo_kqfilter; + fo_fill_kinfo_t *fo_fill_kinfo; + fo_mmap_t *fo_mmap; + fo_aio_queue_t *fo_aio_queue; + fo_add_seals_t *fo_add_seals; + fo_get_seals_t *fo_get_seals; + fo_fallocate_t *fo_fallocate; + fo_fspacectl_t *fo_fspacectl; + fo_spare_t *fo_spares[8]; /* Spare slots */ +#endif + fo_flags_t fo_flags; /* DFLAG_* below */ +}; + +#define DFLAG_PASSABLE 0x01 /* may be passed via unix sockets. */ +#define DFLAG_SEEKABLE 0x02 /* seekable / nonsequential */ + +#endif /* __LWP_TTY_BSD_PORTING_H__ */ diff --git a/components/lwp/terminal/bsd_ttydisc.h b/components/lwp/terminal/bsd_ttydisc.h new file mode 100644 index 00000000000..3d25f61e124 --- /dev/null +++ b/components/lwp/terminal/bsd_ttydisc.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-13 Shell init ver. + */ + +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2008 Ed Schouten + * All rights reserved. + * + * Portions of this software were developed under sponsorship from Snow + * B.V., the Netherlands. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _SYS_TTYDISC_H_ +#define _SYS_TTYDISC_H_ + +#ifndef __LWP_TERMINAL_H__ +#error "can only be included through " +#endif /* !__LWP_TERMINAL_H__ */ + +#include + +struct rt_wqueue; +struct rt_thread; +struct lwp_tty; +struct uio; + +/* Top half routines. */ +void ttydisc_open(struct lwp_tty *tp); +void ttydisc_close(struct lwp_tty *tp); +int ttydisc_read(struct lwp_tty *tp, struct uio *uio, int ioflag); +int ttydisc_write(struct lwp_tty *tp, struct uio *uio, int ioflag); +void ttydisc_optimize(struct lwp_tty *tp); + +/* Bottom half routines. */ +void ttydisc_modem(struct lwp_tty *tp, int open); +#define ttydisc_can_bypass(tp) ((tp)->t_flags & TF_BYPASS) +int ttydisc_rint(struct lwp_tty *tp, char c, int flags); +size_t ttydisc_rint_simple(struct lwp_tty *tp, const void *buf, size_t len); +size_t ttydisc_rint_bypass(struct lwp_tty *tp, const void *buf, size_t len); +void ttydisc_rint_done(struct lwp_tty *tp); +size_t ttydisc_rint_poll(struct lwp_tty *tp); +size_t ttydisc_getc(struct lwp_tty *tp, void *buf, size_t len); +int ttydisc_getc_uio(struct lwp_tty *tp, struct uio *uio); +size_t ttydisc_getc_poll(struct lwp_tty *tp); + +/* Error codes for ttydisc_rint(). */ +#define TRE_FRAMING 0x01 +#define TRE_PARITY 0x02 +#define TRE_OVERRUN 0x04 +#define TRE_BREAK 0x08 + +#endif /* !_SYS_TTYDISC_H_ */ diff --git a/components/lwp/terminal/bsd_ttyqueue.h b/components/lwp/terminal/bsd_ttyqueue.h new file mode 100644 index 00000000000..96b7ae3d8b6 --- /dev/null +++ b/components/lwp/terminal/bsd_ttyqueue.h @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-13 Shell init ver. + */ + +#include "bsd_porting.h" + +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2008 Ed Schouten + * All rights reserved. + * + * Portions of this software were developed under sponsorship from Snow + * B.V., the Netherlands. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _SYS_TTYQUEUE_H_ +#define _SYS_TTYQUEUE_H_ + +#ifndef __LWP_TERMINAL_H__ +#error "can only be included through " +#endif /* !__LWP_TERMINAL_H__ */ + +struct lwp_tty; +struct ttyinq_block; +struct ttyoutq_block; +struct uio; + +/* Data input queue. */ +struct ttyinq +{ + struct ttyinq_block *ti_firstblock; + struct ttyinq_block *ti_startblock; + struct ttyinq_block *ti_reprintblock; + struct ttyinq_block *ti_lastblock; + unsigned int ti_begin; + unsigned int ti_linestart; + unsigned int ti_reprint; + unsigned int ti_end; + unsigned int ti_nblocks; + unsigned int ti_quota; +}; +#define TTYINQ_DATASIZE 128 + +/* Data output queue. */ +struct ttyoutq +{ + struct ttyoutq_block *to_firstblock; + struct ttyoutq_block *to_lastblock; + unsigned int to_begin; + unsigned int to_end; + unsigned int to_nblocks; + unsigned int to_quota; +}; +#define TTYOUTQ_DATASIZE (256 - sizeof(struct ttyoutq_block *)) + +/* Input queue handling routines. */ +int ttyinq_setsize(struct ttyinq *ti, struct lwp_tty *tp, size_t len); +void ttyinq_free(struct ttyinq *ti); +int ttyinq_read_uio(struct ttyinq *ti, struct lwp_tty *tp, struct uio *uio, + size_t readlen, size_t flushlen); +size_t ttyinq_write(struct ttyinq *ti, const void *buf, size_t len, int quote); +int ttyinq_write_nofrag(struct ttyinq *ti, const void *buf, size_t len, + int quote); +void ttyinq_canonicalize(struct ttyinq *ti); +size_t ttyinq_findchar(struct ttyinq *ti, const char *breakc, size_t maxlen, + char *lastc); +void ttyinq_flush(struct ttyinq *ti); +int ttyinq_peekchar(struct ttyinq *ti, char *c, int *quote); +void ttyinq_unputchar(struct ttyinq *ti); +void ttyinq_reprintpos_set(struct ttyinq *ti); +void ttyinq_reprintpos_reset(struct ttyinq *ti); + +rt_inline size_t ttyinq_getsize(struct ttyinq *ti) +{ + return (ti->ti_nblocks * TTYINQ_DATASIZE); +} + +rt_inline size_t ttyinq_getallocatedsize(struct ttyinq *ti) +{ + return (ti->ti_quota * TTYINQ_DATASIZE); +} + +rt_inline size_t ttyinq_bytesleft(struct ttyinq *ti) +{ + size_t len; + + /* Make sure the usage never exceeds the length. */ + len = ti->ti_nblocks * TTYINQ_DATASIZE; + MPASS(len >= ti->ti_end); + + return (len - ti->ti_end); +} + +rt_inline size_t ttyinq_bytescanonicalized(struct ttyinq *ti) +{ + MPASS(ti->ti_begin <= ti->ti_linestart); + + return (ti->ti_linestart - ti->ti_begin); +} + +rt_inline size_t ttyinq_bytesline(struct ttyinq *ti) +{ + MPASS(ti->ti_linestart <= ti->ti_end); + + return (ti->ti_end - ti->ti_linestart); +} + +/* Input buffer iteration. */ +typedef void ttyinq_line_iterator_t(void *data, char c, int flags); +void ttyinq_line_iterate_from_linestart(struct ttyinq *ti, + ttyinq_line_iterator_t *iterator, + void *data); +void ttyinq_line_iterate_from_reprintpos(struct ttyinq *ti, + ttyinq_line_iterator_t *iterator, + void *data); + +/* Output queue handling routines. */ +void ttyoutq_flush(struct ttyoutq *to); +int ttyoutq_setsize(struct ttyoutq *to, struct lwp_tty *tp, size_t len); +void ttyoutq_free(struct ttyoutq *to); +size_t ttyoutq_read(struct ttyoutq *to, void *buf, size_t len); +int ttyoutq_read_uio(struct ttyoutq *to, struct lwp_tty *tp, struct uio *uio); +size_t ttyoutq_write(struct ttyoutq *to, const void *buf, size_t len); +int ttyoutq_write_nofrag(struct ttyoutq *to, const void *buf, size_t len); + +rt_inline size_t ttyoutq_getsize(struct ttyoutq *to) +{ + return (to->to_nblocks * TTYOUTQ_DATASIZE); +} + +rt_inline size_t ttyoutq_getallocatedsize(struct ttyoutq *to) +{ + return (to->to_quota * TTYOUTQ_DATASIZE); +} + +rt_inline size_t ttyoutq_bytesleft(struct ttyoutq *to) +{ + size_t len; + + /* Make sure the usage never exceeds the length. */ + len = to->to_nblocks * TTYOUTQ_DATASIZE; + MPASS(len >= to->to_end); + + return (len - to->to_end); +} + +rt_inline size_t ttyoutq_bytesused(struct ttyoutq *to) +{ + return (to->to_end - to->to_begin); +} + +#endif /* !_SYS_TTYQUEUE_H_ */ diff --git a/components/lwp/terminal/freebsd/tty.c b/components/lwp/terminal/freebsd/tty.c new file mode 100644 index 00000000000..cdd90062790 --- /dev/null +++ b/components/lwp/terminal/freebsd/tty.c @@ -0,0 +1,1447 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-13 Shell init ver. + */ +#include "../bsd_porting.h" +#include "../tty_config.h" +#include "../terminal.h" +#include "../tty_internal.h" + +#include +#include + +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2008 Ed Schouten + * All rights reserved. + * + * Portions of this software were developed under sponsorship from Snow + * B.V., the Netherlands. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +static void tty_rel_free(struct lwp_tty *tp); + +/* Character device of /dev/console. */ +static struct rt_device *dev_console; +#ifdef USING_BSD_CONSOLE_NAME +static const char *dev_console_filename; +#endif + +/* + * Flags that are supported and stored by this implementation. + */ +#ifndef ALTWERASE +#define ALTWERASE 0 +#endif +#ifndef NOKERNINFO +#define NOKERNINFO 0 +#endif +#define TTYSUP_IFLAG \ + (IGNBRK | BRKINT | IGNPAR | PARMRK | INPCK | ISTRIP | INLCR | IGNCR | \ + ICRNL | IXON | IXOFF | IXANY | IMAXBEL | IUTF8) +#define TTYSUP_OFLAG (OPOST | ONLCR | TAB3 | ONOEOT | OCRNL | ONOCR | ONLRET) +#define TTYSUP_LFLAG \ + (ECHOKE | ECHOE | ECHOK | ECHO | ECHONL | ECHOPRT | ECHOCTL | ISIG | \ + ICANON | ALTWERASE | IEXTEN | TOSTOP | FLUSHO | NOKERNINFO | NOFLSH) +#define TTYSUP_CFLAG \ + (CIGNORE | CSIZE | CSTOPB | CREAD | PARENB | PARODD | HUPCL | CLOCAL | \ + CCTS_OFLOW | CRTS_IFLOW | CDTR_IFLOW | CDSR_OFLOW | CCAR_OFLOW | \ + CNO_RTSDTR) + +/* + * Set TTY buffer sizes. + */ + +#define TTYBUF_MAX 65536 + +#ifdef PRINTF_BUFR_SIZE +#define TTY_PRBUF_SIZE PRINTF_BUFR_SIZE +#else +#define TTY_PRBUF_SIZE 256 +#endif + +/* Note: access to struct cdev:si_drv0. + Since pull-in, pull-out is not provided, this field + is constant value 0 in smart system */ +#define dev2unit(d) (0) +#define TTY_CALLOUT(tp, d) (dev2unit(d) & TTYUNIT_CALLOUT) + +/* + * Allocate buffer space if necessary, and set low watermarks, based on speed. + * Note that the ttyxxxq_setsize() functions may drop and then reacquire the tty + * lock during memory allocation. They will return ENXIO if the tty disappears + * while unlocked. + */ +static int tty_watermarks(struct lwp_tty *tp) +{ + size_t bs = 0; + int error; + + /* Provide an input buffer for 2 seconds of data. */ + if (tp->t_termios.c_cflag & CREAD) + bs = + MIN(bsd_speed_to_integer(tp->t_termios.__c_ispeed) / 5, TTYBUF_MAX); + error = ttyinq_setsize(&tp->t_inq, tp, bs); + if (error != 0) + return error; + + /* Set low watermark at 10% (when 90% is available). */ + tp->t_inlow = (ttyinq_getallocatedsize(&tp->t_inq) * 9) / 10; + + /* Provide an output buffer for 2 seconds of data. */ + bs = MIN(bsd_speed_to_integer(tp->t_termios.__c_ospeed) / 5, TTYBUF_MAX); + error = ttyoutq_setsize(&tp->t_outq, tp, bs); + if (error != 0) + return error; + + /* Set low watermark at 10% (when 90% is available). */ + tp->t_outlow = (ttyoutq_getallocatedsize(&tp->t_outq) * 9) / 10; + + return 0; +} + +/** + * Drain outq + */ +static int tty_drain(struct lwp_tty *tp, int leaving) +{ + rt_tick_t timeout_tick; + size_t bytes; + int error; + +#ifdef USING_BSD_HOOK + if (ttyhook_hashook(tp, getc_inject)) + /* buffer is inaccessible */ + return 0; +#endif /* USING_BSD_HOOK */ + + /* + * For close(), use the recent historic timeout of "1 second without + * making progress". For tcdrain(), use t_drainwait as the timeout, + * with zero meaning "no timeout" which gives POSIX behavior. + */ + if (leaving) + timeout_tick = rt_tick_get() + RT_TICK_PER_SECOND; + else if (tp->t_drainwait != 0) + timeout_tick = rt_tick_get() + RT_TICK_PER_SECOND * tp->t_drainwait; + else + timeout_tick = 0; + + /* + * Poll the output buffer and the hardware for completion, at 10 Hz. + * Polling is required for devices which are not able to signal an + * interrupt when the transmitter becomes idle (most USB serial devs). + * The unusual structure of this loop ensures we check for busy one more + * time after tty_timedwait() returns EWOULDBLOCK, so that success has + * higher priority than timeout if the IO completed in the last 100mS. + */ + error = 0; + bytes = ttyoutq_bytesused(&tp->t_outq); + for (;;) + { + if (ttyoutq_bytesused(&tp->t_outq) == 0 && !ttydevsw_busy(tp)) + return 0; + if (error != 0) + return error; + ttydevsw_outwakeup(tp); + error = tty_timedwait(tp, &tp->t_outwait, RT_TICK_PER_SECOND / 10); + if (error != 0 && error != EWOULDBLOCK) + return error; + else if (timeout_tick == 0 || rt_tick_get() < timeout_tick) + error = 0; + else if (leaving && ttyoutq_bytesused(&tp->t_outq) < bytes) + { + /* In close, making progress, grant an extra second. */ + error = 0; + timeout_tick += RT_TICK_PER_SECOND; + bytes = ttyoutq_bytesused(&tp->t_outq); + } + } +} + +/* + * Though ttydev_enter() and ttydev_leave() seem to be related, they + * don't have to be used together. ttydev_enter() is used by the cdev + * operations to prevent an actual operation from being processed when + * the TTY has been abandoned. ttydev_leave() is used by ttydev_open() + * and ttydev_close() to determine whether per-TTY data should be + * deallocated. + */ + +rt_inline int ttydev_enter(struct lwp_tty *tp) +{ + rt_err_t error = tty_lock(tp); + if (error) + RT_ASSERT(0); + + if (tty_gone(tp) || !tty_opened(tp)) + { + /* Device is already gone. */ + tty_unlock(tp); + return -ENXIO; + } + + return 0; +} + +static void ttydev_leave(struct lwp_tty *tp) +{ + tty_assert_locked(tp); + + if (tty_opened(tp) || tp->t_flags & TF_OPENCLOSE) + { + /* Device is still opened somewhere. */ + tty_unlock(tp); + return; + } + + tp->t_flags |= TF_OPENCLOSE; + + /* Remove console TTY. */ + constty_clear(tp); + + /* Drain any output. */ + if (!tty_gone(tp)) + tty_drain(tp, 1); + + ttydisc_close(tp); + + /* Free i/o queues now since they might be large. */ + ttyinq_free(&tp->t_inq); + tp->t_inlow = 0; + ttyoutq_free(&tp->t_outq); + tp->t_outlow = 0; + +#ifdef USING_BSD_KNOTE + knlist_clear(&tp->t_inpoll.si_note, 1); + knlist_clear(&tp->t_outpoll.si_note, 1); +#endif + + if (!tty_gone(tp)) + ttydevsw_close(tp); + + tp->t_flags &= ~TF_OPENCLOSE; + cv_broadcast(&tp->t_dcdwait); + tty_rel_free(tp); +} + +/* + * Operations that are exposed through the character device in /dev. + */ +static int ttydev_open(struct lwp_tty *tp, int oflags, int devtype, + struct rt_thread *td) +{ + rt_device_t dev = &tp->parent; + int error; + + error = 0; + tty_lock(tp); + if (tty_gone(tp)) + { + /* Device is already gone. */ + tty_unlock(tp); + return -ENXIO; + } + + /* + * Block when other processes are currently opening or closing + * the TTY. + */ + while (tp->t_flags & TF_OPENCLOSE) + { + error = tty_wait(tp, &tp->t_dcdwait); + if (error != 0) + { + tty_unlock(tp); + return error; + } + } + tp->t_flags |= TF_OPENCLOSE; + + /* + * Make sure the "tty" and "cua" device cannot be opened at the + * same time. The console is a "tty" device. + */ + if (TTY_CALLOUT(tp, dev)) + { + if (tp->t_flags & (TF_OPENED_CONS | TF_OPENED_IN)) + { + error = EBUSY; + goto done; + } + } + else + { + if (tp->t_flags & TF_OPENED_OUT) + { + error = EBUSY; + goto done; + } + } + + if (tp->t_flags & TF_EXCLUDE && priv_check(td, PRIV_TTY_EXCLUSIVE)) + { + error = EBUSY; + goto done; + } + + if (!tty_opened(tp)) + { + /* Set proper termios flags. */ + if (TTY_CALLOUT(tp, dev)) +#ifdef USING_BSD_INIT_LOCK_DEVICE + tp->t_termios = tp->t_termios_init_out; +#else + ; +#endif /* USING_BSD_INIT_LOCK_DEVICE */ + else + tp->t_termios = tp->t_termios_init_in; + + ttydevsw_param(tp, &tp->t_termios); + /* Prevent modem control on callout devices and /dev/console. */ + if (TTY_CALLOUT(tp, dev) || dev == dev_console) + tp->t_termios.c_cflag |= CLOCAL; + + if ((tp->t_termios.c_cflag & CNO_RTSDTR) == 0) + ttydevsw_modem(tp, SER_DTR | SER_RTS, 0); + + error = ttydevsw_open(tp); + if (error != 0) + goto done; + + ttydisc_open(tp); + error = tty_watermarks(tp); + if (error != 0) + goto done; + } + + /* Wait for Carrier Detect. */ + if ((oflags & O_NONBLOCK) == 0 && (tp->t_termios.c_cflag & CLOCAL) == 0) + { + while ((ttydevsw_modem(tp, 0, 0) & SER_DCD) == 0) + { + error = tty_wait(tp, &tp->t_dcdwait); + if (error != 0) + goto done; + } + } + + if (dev == dev_console) + tp->t_flags |= TF_OPENED_CONS; + else if (TTY_CALLOUT(tp, dev)) + tp->t_flags |= TF_OPENED_OUT; + else + tp->t_flags |= TF_OPENED_IN; + MPASS((tp->t_flags & (TF_OPENED_CONS | TF_OPENED_IN)) == 0 || + (tp->t_flags & TF_OPENED_OUT) == 0); + +done: + tp->t_flags &= ~TF_OPENCLOSE; + cv_broadcast(&tp->t_dcdwait); + ttydev_leave(tp); + + return error; +} + +static int ttydev_close(struct lwp_tty *tp, int fflag, int devtype __unused, + struct rt_thread *td __unused) +{ + rt_device_t dev = &tp->parent; + + tty_lock(tp); + + /* + * Don't actually close the device if it is being used as the + * console. + */ + MPASS((tp->t_flags & (TF_OPENED_CONS | TF_OPENED_IN)) == 0 || + (tp->t_flags & TF_OPENED_OUT) == 0); + if (dev == dev_console) + tp->t_flags &= ~TF_OPENED_CONS; + else + tp->t_flags &= ~(TF_OPENED_IN | TF_OPENED_OUT); + + if (tp->t_flags & TF_OPENED) + { + tty_unlock(tp); + return 0; + } + + /* If revoking, flush output now to avoid draining it later. */ + if (fflag & FREVOKE) + tty_flush(tp, FWRITE); + + tp->t_flags &= ~TF_EXCLUDE; + + /* Properly wake up threads that are stuck - revoke(). */ + tp->t_revokecnt++; + tty_wakeup(tp, FREAD | FWRITE); + cv_broadcast(&tp->t_bgwait); + cv_broadcast(&tp->t_dcdwait); + + ttydev_leave(tp); + + return 0; +} + +int tty_wait_background(struct lwp_tty *tp, struct rt_thread *td, int sig) +{ + struct rt_lwp *p; + struct rt_processgroup *pg; + int error; + + MPASS(sig == SIGTTIN || sig == SIGTTOU); + tty_assert_locked(tp); + + p = td->lwp; + for (;;) + { + pg = p->pgrp; + PGRP_LOCK(pg); + LWP_LOCK(p); + + /* + * pg may no longer be our process group. + * Re-check after locking. + */ + if (p->pgrp != pg) + { + LWP_UNLOCK(p); + PGRP_UNLOCK(pg); + continue; + } + + /* + * The process should only sleep, when: + * - This terminal is the controlling terminal + * - Its process group is not the foreground process + * group + * - The parent process isn't waiting for the child to + * exit + * - the signal to send to the process isn't masked + */ + if (!tty_is_ctty(tp, p) || pg == tp->t_pgrp) + { + /* Allow the action to happen. */ + LWP_UNLOCK(p); + PGRP_UNLOCK(pg); + return 0; + } + + /* Note: process itself don't have a sigmask in smart */ + if (lwp_sigisign(p, sig) || + lwp_sigismember(&td->signal.sigset_mask, sig)) + { + /* Only allow them in write()/ioctl(). */ + LWP_UNLOCK(p); + PGRP_UNLOCK(pg); + return (sig == SIGTTOU ? 0 : -EIO); + } + +#ifdef USING_VFORK_FLAG + if ((p->p_flag & P_PPWAIT) != 0 || pg->is_orphaned) +#else + if (pg->is_orphaned) +#endif + { + /* Don't allow the action to happen. */ + LWP_UNLOCK(p); + PGRP_UNLOCK(pg); + return -EIO; + } + LWP_UNLOCK(p); + + /* + * Send the signal and sleep until we're the new + * foreground process group. + */ + if (sig != 0) + { + lwp_pgrp_signal_kill(pg, sig, SI_KERNEL, 0); + } + + PGRP_UNLOCK(pg); + + error = tty_wait(tp, &tp->t_bgwait); + if (error) + return error; + } +} + +static int ttydev_read(struct lwp_tty *tp, struct uio *uio, int ioflag) +{ + int error; + + error = ttydev_enter(tp); + if (error) + goto done; + error = ttydisc_read(tp, uio, ioflag); + tty_unlock(tp); + + /* + * The read() call should not throw an error when the device is + * being destroyed. Silently convert it to an EOF. + */ +done: + if (error == -ENXIO) + error = 0; + return error; +} + +static int ttydev_write(struct lwp_tty *tp, struct uio *uio, int ioflag) +{ +#ifdef USING_BSD_DEFER_STOP + int defer; +#endif + int error; + + error = ttydev_enter(tp); + if (error) + return error; + + if (tp->t_termios.c_lflag & TOSTOP) + { + error = tty_wait_background(tp, curthread, SIGTTOU); + if (error) + goto done; + } + + if (ioflag & IO_NDELAY && tp->t_flags & TF_BUSY_OUT) + { + /* Allow non-blocking writes to bypass serialization. */ + error = ttydisc_write(tp, uio, ioflag); + } + else + { + /* Serialize write() calls. */ + while (tp->t_flags & TF_BUSY_OUT) + { + error = tty_wait(tp, &tp->t_outserwait); + if (error) + goto done; + } + + tp->t_flags |= TF_BUSY_OUT; +#ifdef USING_BSD_DEFER_STOP + defer = sigdeferstop(SIGDEFERSTOP_ERESTART); +#endif + error = ttydisc_write(tp, uio, ioflag); +#ifdef USING_BSD_DEFER_STOP + sigallowstop(defer); +#endif + tp->t_flags &= ~TF_BUSY_OUT; + cv_signal(&tp->t_outserwait); + } + +done: + tty_unlock(tp); + return error; +} + +static int ttydev_ioctl(struct lwp_tty *tp, rt_ubase_t cmd, rt_caddr_t data, int fflag, + struct rt_thread *td) +{ + int error; + + error = ttydev_enter(tp); + if (error) + return (error); + + switch (cmd) + { + case TIOCCBRK: + case TIOCCONS: + case TIOCDRAIN: + case TIOCEXCL: + case TIOCFLUSH: + case TIOCNXCL: + case TIOCSBRK: + case TIOCSCTTY: + case TIOCSETA: + case TIOCSETAF: + case TIOCSETAW: + case TIOCSPGRP: + case TIOCSTART: + case TIOCSTAT: + case TIOCSTI: + case TIOCSTOP: + case TIOCSWINSZ: +#if USING_BSD_TIOCSDRAINWAIT + case TIOCSDRAINWAIT: + case TIOCSETD: +#endif /* USING_BSD_TIOCSDRAINWAIT */ +#ifdef COMPAT_43TTY + case TIOCLBIC: + case TIOCLBIS: + case TIOCLSET: + case TIOCSETC: + case OTIOCSETD: + case TIOCSETN: + case TIOCSETP: + case TIOCSLTC: +#endif /* COMPAT_43TTY */ + /* + * If the ioctl() causes the TTY to be modified, let it + * wait in the background. + */ + error = tty_wait_background(tp, curthread, SIGTTOU); + if (error) + goto done; + } + +#ifdef USING_BSD_INIT_LOCK_DEVICE + if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) + { + struct termios *old = &tp->t_termios; + struct termios *new = (struct termios *)data; + struct termios *lock = TTY_CALLOUT(tp, dev) ? &tp->t_termios_lock_out + : &tp->t_termios_lock_in; + int cc; + + /* + * Lock state devices. Just overwrite the values of the + * commands that are currently in use. + */ + new->c_iflag = + (old->c_iflag & lock->c_iflag) | (new->c_iflag & ~lock->c_iflag); + new->c_oflag = + (old->c_oflag & lock->c_oflag) | (new->c_oflag & ~lock->c_oflag); + new->c_cflag = + (old->c_cflag & lock->c_cflag) | (new->c_cflag & ~lock->c_cflag); + new->c_lflag = + (old->c_lflag & lock->c_lflag) | (new->c_lflag & ~lock->c_lflag); + for (cc = 0; cc < NCCS; ++cc) + if (lock->c_cc[cc]) + new->c_cc[cc] = old->c_cc[cc]; + if (lock->__c_ispeed) + new->__c_ispeed = old->__c_ispeed; + if (lock->__c_ospeed) + new->__c_ospeed = old->__c_ospeed; + } +#endif /* USING_BSD_INIT_LOCK_DEVICE */ + + error = tty_ioctl(tp, cmd, data, fflag, td); +done: + tty_unlock(tp); + + return (error); +} + +static int ttydev_poll(struct lwp_tty *tp, rt_pollreq_t *req, struct rt_thread *td) +{ + int events = req->_key; + int error, revents = 0; + + error = ttydev_enter(tp); + if (error) + return ((events & (POLLIN | POLLRDNORM)) | POLLHUP); + + if (events & (POLLIN | POLLRDNORM)) + { + /* See if we can read something. */ + if (ttydisc_read_poll(tp) > 0) + revents |= events & (POLLIN | POLLRDNORM); + } + + if (tp->t_flags & TF_ZOMBIE) + { + /* Hangup flag on zombie state. */ + revents |= POLLHUP; + } + else if (events & (POLLOUT | POLLWRNORM)) + { + /* See if we can write something. */ + if (ttydisc_write_poll(tp) > 0) + revents |= events & (POLLOUT | POLLWRNORM); + } + + if (revents == 0) + { + if (events & (POLLIN | POLLRDNORM)) + rt_poll_add(&tp->t_inpoll, req); + if (events & (POLLOUT | POLLWRNORM)) + rt_poll_add(&tp->t_outpoll, req); + } + + tty_unlock(tp); + + return revents; +} + +static struct cdevsw ttydev_cdevsw = { + .d_open = ttydev_open, + .d_close = ttydev_close, + .d_read = ttydev_read, + .d_write = ttydev_write, + .d_ioctl = ttydev_ioctl, +#if 0 + .d_kqfilter = ttydev_kqfilter, +#endif + .d_poll = ttydev_poll, +#if 0 + .d_mmap = ttydev_mmap, +#endif + +#ifdef USING_BSD_RAW_CDEVSW + .d_version = D_VERSION.d_name = "ttydev", + .d_flags = D_TTY, +#endif /* USING_BSD_RAW_CDEVSW */ +}; + +extern struct cdevsw bsd_ttydev_methods __attribute__((alias("ttydev_cdevsw"))); + +/* + * Standard device routine implementations, mostly meant for + * pseudo-terminal device drivers. When a driver creates a new terminal + * device class, missing routines are patched. + */ +#define panic(msg) RT_ASSERT(0 && msg) + +static int ttydevsw_defopen(struct lwp_tty *tp __unused) +{ + return 0; +} + +static void ttydevsw_defclose(struct lwp_tty *tp __unused) +{ +} + +static void ttydevsw_defoutwakeup(struct lwp_tty *tp __unused) +{ + panic("Terminal device has output, while not implemented"); +} + +static void ttydevsw_definwakeup(struct lwp_tty *tp __unused) +{ +} + +static int ttydevsw_defioctl(struct lwp_tty *tp __unused, rt_ubase_t cmd __unused, + rt_caddr_t data __unused, + struct rt_thread *td __unused) +{ + return -ENOSYS; +} + +static int ttydevsw_defcioctl(struct lwp_tty *tp __unused, int unit __unused, + rt_ubase_t cmd __unused, rt_caddr_t data __unused, + struct rt_thread *td __unused) +{ + return -ENOSYS; +} + +static int ttydevsw_defparam(struct lwp_tty *tp __unused, struct termios *t) +{ + /* + * Allow the baud rate to be adjusted for pseudo-devices, but at + * least restrict it to 115200 to prevent excessive buffer + * usage. Also disallow 0, to prevent foot shooting. + */ + if (t->__c_ispeed < B50) + t->__c_ispeed = B50; + else if (t->__c_ispeed > B115200) + t->__c_ispeed = B115200; + if (t->__c_ospeed < B50) + t->__c_ospeed = B50; + else if (t->__c_ospeed > B115200) + t->__c_ospeed = B115200; + t->c_cflag |= CREAD; + + return 0; +} + +static int ttydevsw_defmodem(struct lwp_tty *tp __unused, int sigon __unused, + int sigoff __unused) +{ + /* Simulate a carrier to make the TTY layer happy. */ + return (SER_DCD); +} + +static int ttydevsw_defmmap(struct lwp_tty *tp __unused, + vm_ooffset_t offset __unused, + vm_paddr_t *paddr __unused, int nprot __unused, + vm_memattr_t *memattr __unused) +{ + return (-1); +} + +static void ttydevsw_defpktnotify(struct lwp_tty *tp __unused, + char event __unused) +{ +} + +static void ttydevsw_deffree(void *softc __unused) +{ + panic("Terminal device freed without a free-handler"); +} + +static rt_bool_t ttydevsw_defbusy(struct lwp_tty *tp __unused) +{ + return (RT_FALSE); +} + +void bsd_devsw_init(struct lwp_ttydevsw *tsw) +{ + /* Make sure the driver defines all routines. */ +#define PATCH_FUNC(x) \ + do \ + { \ + if (tsw->tsw_##x == NULL) \ + tsw->tsw_##x = ttydevsw_def##x; \ + } while (0) + + PATCH_FUNC(open); + PATCH_FUNC(close); + PATCH_FUNC(outwakeup); + PATCH_FUNC(inwakeup); + PATCH_FUNC(ioctl); + PATCH_FUNC(cioctl); + PATCH_FUNC(param); + PATCH_FUNC(modem); + PATCH_FUNC(mmap); + PATCH_FUNC(pktnotify); + PATCH_FUNC(free); + PATCH_FUNC(busy); +#undef PATCH_FUNC +} + +/* release tty, and free the cdev resource */ +static void tty_rel_free(struct lwp_tty *tp) +{ +#ifdef USING_BSD_CHAR_DEVICE + struct cdev *dev; +#endif + + tty_assert_locked(tp); + +#define TF_ACTIVITY (TF_GONE | TF_OPENED | TF_HOOK | TF_OPENCLOSE) + if (tp->t_sessioncnt != 0 || (tp->t_flags & TF_ACTIVITY) != TF_GONE) + { + /* TTY is still in use. */ + tty_unlock(tp); + return; + } + +#ifdef USING_BSD_AIO + /* Stop asynchronous I/O. */ + funsetown(&tp->t_sigio); +#endif /* USING_BSD_AIO */ + +#ifdef USING_BSD_CHAR_DEVICE + /* TTY can be deallocated. */ + dev = tp->t_dev; + tp->t_dev = NULL; +#endif /* USING_BSD_CHAR_DEVICE */ + + tty_unlock(tp); + +#ifdef USING_BSD_CHAR_DEVICE + if (dev != NULL) + { + sx_xlock(&tty_list_sx); + TAILQ_REMOVE(&tty_list, tp, t_list); + tty_list_count--; + sx_xunlock(&tty_list_sx); + destroy_dev_sched_cb(dev, tty_dealloc, tp); + } +#else + lwp_tty_delete(tp); +#endif +} + +void tty_rel_pgrp(struct lwp_tty *tp, struct rt_processgroup *pg) +{ + MPASS(tp->t_sessioncnt > 0); + tty_assert_locked(tp); + + if (tp->t_pgrp == pg) + tp->t_pgrp = NULL; + + tty_unlock(tp); +} + +void tty_rel_sess(struct lwp_tty *tp, struct rt_session *sess) +{ + MPASS(tp->t_sessioncnt > 0); + + /* Current session has left. */ + if (tp->t_session == sess) + { + tp->t_session = NULL; + MPASS(tp->t_pgrp == NULL); + } + tp->t_sessioncnt--; + tty_rel_free(tp); +} + +/* deallocate the tty */ +void tty_rel_gone(struct lwp_tty *tp) +{ + tty_assert_locked(tp); + MPASS(!tty_gone(tp)); + + /* Simulate carrier removal. */ + ttydisc_modem(tp, 0); + + /* Wake up all blocked threads. */ + tty_wakeup(tp, FREAD | FWRITE); + cv_broadcast(&tp->t_bgwait); + cv_broadcast(&tp->t_dcdwait); + + tp->t_flags |= TF_GONE; + tty_rel_free(tp); +} + +static int tty_drop_ctty(struct lwp_tty *tp, struct rt_lwp *p) +{ + struct rt_session *session; +#ifdef USING_BSD_VNODE + struct vnode *vp; +#endif + + /* + * This looks terrible, but it's generally safe as long as the tty + * hasn't gone away while we had the lock dropped. All of our sanity + * checking that this operation is OK happens after we've picked it back + * up, so other state changes are generally not fatal and the potential + * for this particular operation to happen out-of-order in a + * multithreaded scenario is likely a non-issue. + */ + tty_unlock(tp); + LWP_LOCK(p); + tty_lock(tp); + if (tty_gone(tp)) + { + LWP_UNLOCK(p); + return -ENODEV; + } + + /* + * If the session doesn't have a controlling TTY, or if we weren't + * invoked on the controlling TTY, we'll return ENOIOCTL as we've + * historically done. + */ + session = p->pgrp->session; + if (session->ctty == NULL || session->ctty != tp) + { + LWP_UNLOCK(p); + return -ENOTTY; + } + + if (!is_sess_leader(p)) + { + LWP_UNLOCK(p); + return -EPERM; + } + + SESS_LOCK(session); +#ifdef USING_BSD_VNODE + vp = session->s_ttyvp; +#endif + session->ctty = NULL; +#ifdef USING_BSD_VNODE + session->s_ttyvp = NULL; + session->s_ttydp = NULL; +#endif + SESS_UNLOCK(session); + + tp->t_sessioncnt--; + p->term_ctrlterm = RT_FALSE; + LWP_UNLOCK(p); + +#ifdef USING_BSD_VNODE + /* + * If we did have a vnode, release our reference. Ordinarily we manage + * these at the devfs layer, but we can't necessarily know that we were + * invoked on the vnode referenced in the session (i.e. the vnode we + * hold a reference to). We explicitly don't check VBAD/VIRF_DOOMED here + * to avoid a vnode leak -- in circumstances elsewhere where we'd hit a + * VIRF_DOOMED vnode, release has been deferred until the controlling TTY + * is either changed or released. + */ + if (vp != NULL) + devfs_ctty_unref(vp); +#endif + + return 0; +} + +void tty_wakeup(struct lwp_tty *tp, int flags) +{ +#ifdef USING_BSD_AIO + if (tp->t_flags & TF_ASYNC && tp->t_sigio != NULL) + pgsigio(&tp->t_sigio, SIGIO, (tp->t_session != NULL)); +#endif + + if (flags & FWRITE) + { + cv_broadcast(&tp->t_outwait); +#ifdef USING_BSD_POLL + selwakeup(&tp->t_outpoll); + KNOTE_LOCKED(&tp->t_outpoll.si_note, 0); +#else + rt_wqueue_wakeup_all(&tp->t_outpoll, (void *)POLLOUT); +#endif + } + if (flags & FREAD) + { + cv_broadcast(&tp->t_inwait); +#ifdef USING_BSD_POLL + selwakeup(&tp->t_inpoll); + KNOTE_LOCKED(&tp->t_inpoll.si_note, 0); +#else + rt_wqueue_wakeup_all(&tp->t_inpoll, (void *)POLLIN); +#endif + } +} + +int tty_wait(struct lwp_tty *tp, struct rt_condvar *cv) +{ + int error; + int revokecnt = tp->t_revokecnt; + + tty_lock_assert(tp, MA_OWNED | MA_NOTRECURSED); + MPASS(!tty_gone(tp)); + + error = cv_wait_sig(cv, tp->t_mtx); + + /* Bail out when the device slipped away. */ + if (tty_gone(tp)) + return -ENXIO; + + /* Restart the system call when we may have been revoked. */ + if (tp->t_revokecnt != revokecnt) + return -ERESTART; + + return error; +} + +int tty_timedwait(struct lwp_tty *tp, struct rt_condvar *cv, rt_tick_t timeout) +{ + int error; + int revokecnt = tp->t_revokecnt; + + tty_lock_assert(tp, MA_OWNED | MA_NOTRECURSED); + MPASS(!tty_gone(tp)); + + error = cv_timedwait_sig(cv, tp->t_mtx, timeout); + + /* Bail out when the device slipped away. */ + if (tty_gone(tp)) + return -ENXIO; + + /* Restart the system call when we may have been revoked. */ + if (tp->t_revokecnt != revokecnt) + return -ERESTART; + + return error; +} + +/* discard data in I/O buffers */ +void tty_flush(struct lwp_tty *tp, int flags) +{ + if (flags & FWRITE) + { + tp->t_flags &= ~TF_HIWAT_OUT; + ttyoutq_flush(&tp->t_outq); + tty_wakeup(tp, FWRITE); + if (!tty_gone(tp)) + { + ttydevsw_outwakeup(tp); + ttydevsw_pktnotify(tp, TIOCPKT_FLUSHWRITE); + } + } + if (flags & FREAD) + { + tty_hiwat_in_unblock(tp); + ttyinq_flush(&tp->t_inq); + tty_wakeup(tp, FREAD); + if (!tty_gone(tp)) + { + ttydevsw_inwakeup(tp); + ttydevsw_pktnotify(tp, TIOCPKT_FLUSHREAD); + } + } +} + +void tty_set_winsize(struct lwp_tty *tp, const struct winsize *wsz) +{ + if (memcmp(&tp->t_winsize, wsz, sizeof(*wsz)) == 0) + return; + tp->t_winsize = *wsz; + lwp_tty_signal_pgrp(tp, SIGWINCH); +} + +static int tty_generic_ioctl(struct lwp_tty *tp, rt_ubase_t cmd, void *data, + int fflag, struct rt_thread *td) +{ + int error; + + switch (cmd) + { + /* + * Modem commands. + * The SER_* and TIOCM_* flags are the same, but one bit + * shifted. I don't know why. + */ + case TIOCSDTR: + ttydevsw_modem(tp, SER_DTR, 0); + return 0; + case TIOCCDTR: + ttydevsw_modem(tp, 0, SER_DTR); + return 0; + case TIOCMSET: { + int bits = *(int *)data; + ttydevsw_modem(tp, (bits & (TIOCM_DTR | TIOCM_RTS)) >> 1, + ((~bits) & (TIOCM_DTR | TIOCM_RTS)) >> 1); + return 0; + } + case TIOCMBIS: { + int bits = *(int *)data; + ttydevsw_modem(tp, (bits & (TIOCM_DTR | TIOCM_RTS)) >> 1, 0); + return 0; + } + case TIOCMBIC: { + int bits = *(int *)data; + ttydevsw_modem(tp, 0, (bits & (TIOCM_DTR | TIOCM_RTS)) >> 1); + return 0; + } + case TIOCMGET: + *(int *)data = TIOCM_LE + (ttydevsw_modem(tp, 0, 0) << 1); + return 0; + + case FIOASYNC: + if (*(int *)data) + tp->t_flags |= TF_ASYNC; + else + tp->t_flags &= ~TF_ASYNC; + return 0; + case FIONBIO: + /* This device supports non-blocking operation. */ + return 0; + case FIONREAD: + *(int *)data = ttyinq_bytescanonicalized(&tp->t_inq); + return 0; + case FIONWRITE: + case TIOCOUTQ: + *(int *)data = ttyoutq_bytesused(&tp->t_outq); + return 0; +#if BSD_USING_FIO_OWNERSHIP + case FIOSETOWN: + if (tp->t_session != NULL && !tty_is_ctty(tp, td->lwp)) + /* Not allowed to set ownership. */ + return -ENOTTY; + + /* Temporarily unlock the TTY to set ownership. */ + tty_unlock(tp); + error = fsetown(*(int *)data, &tp->t_sigio); + tty_lock(tp); + return (error); + case FIOGETOWN: + if (tp->t_session != NULL && !tty_is_ctty(tp, td->lwp)) + /* Not allowed to set ownership. */ + return -ENOTTY; + + /* Get ownership. */ + *(int *)data = fgetown(&tp->t_sigio); + return 0; +#endif + case TIOCGETA: + /* Obtain terminal flags through tcgetattr(). */ + *(struct termios *)data = tp->t_termios; + return 0; + case TIOCSETA: + case TIOCSETAW: + case TIOCSETAF: { + struct termios *t = data; + + /* + * Who makes up these funny rules? According to POSIX, + * input baud rate is set equal to the output baud rate + * when zero. + */ + if (t->__c_ispeed == 0) + t->__c_ispeed = t->__c_ospeed; + + /* Discard any unsupported bits. */ + t->c_iflag &= TTYSUP_IFLAG; + t->c_oflag &= TTYSUP_OFLAG; + t->c_lflag &= TTYSUP_LFLAG; + t->c_cflag &= TTYSUP_CFLAG; + + /* Set terminal flags through tcsetattr(). */ + if (cmd == TIOCSETAW || cmd == TIOCSETAF) + { + error = tty_drain(tp, 0); + if (error) + return (error); + if (cmd == TIOCSETAF) + tty_flush(tp, FREAD); + } + + /* + * Only call param() when the flags really change. + */ + if ((t->c_cflag & CIGNORE) == 0 && + (tp->t_termios.c_cflag != t->c_cflag || + ((tp->t_termios.c_iflag ^ t->c_iflag) & + (IXON | IXOFF | IXANY)) || + tp->t_termios.__c_ispeed != t->__c_ispeed || + tp->t_termios.__c_ospeed != t->__c_ospeed)) + { + error = ttydevsw_param(tp, t); + if (error) + return (error); + + /* XXX: CLOCAL? */ + + tp->t_termios.c_cflag = t->c_cflag & ~CIGNORE; + tp->t_termios.__c_ispeed = t->__c_ispeed; + tp->t_termios.__c_ospeed = t->__c_ospeed; + + /* Baud rate has changed - update watermarks. */ + error = tty_watermarks(tp); + if (error) + return (error); + } + + /* Copy new non-device driver parameters. */ + tp->t_termios.c_iflag = t->c_iflag; + tp->t_termios.c_oflag = t->c_oflag; + tp->t_termios.c_lflag = t->c_lflag; + memcpy(&tp->t_termios.c_cc, t->c_cc, sizeof t->c_cc); + + ttydisc_optimize(tp); + + if ((t->c_lflag & ICANON) == 0) + { + /* + * When in non-canonical mode, wake up all + * readers. Canonicalize any partial input. VMIN + * and VTIME could also be adjusted. + */ + ttyinq_canonicalize(&tp->t_inq); + tty_wakeup(tp, FREAD); + } + + /** + * For packet mode: notify the PTY consumer that VSTOP + * and VSTART may have been changed. + * + * TODO: change the _CONTROL('S') to a CSTOP? + */ + if (tp->t_termios.c_iflag & IXON && + tp->t_termios.c_cc[VSTOP] == _CONTROL('S') && + tp->t_termios.c_cc[VSTART] == _CONTROL('Q')) + ttydevsw_pktnotify(tp, TIOCPKT_DOSTOP); + else + ttydevsw_pktnotify(tp, TIOCPKT_NOSTOP); + return 0; + } + case TIOCGETD: + /* For compatibility - we only support TTYDISC. */ + *(int *)data = TTYDISC; + return 0; + case TIOCGPGRP: + if (!tty_is_ctty(tp, td->lwp)) + return -ENOTTY; + + if (tp->t_pgrp != NULL) + *(int *)data = tp->t_pgrp->pgid; + else + *(int *)data = NO_PID; + return 0; + case TIOCGSID: + if (!tty_is_ctty(tp, td->lwp)) + return -ENOTTY; + + MPASS(tp->t_session); + *(int *)data = tp->t_session->sid; + return 0; + case TIOCNOTTY: + return tty_drop_ctty(tp, td->lwp); + case TIOCSCTTY: + return lwp_tty_set_ctrl_proc(tp, td); + case TIOCSPGRP: { + int pgid; + if (lwp_in_user_space((void *)data)) + { + if (lwp_get_from_user(&pgid, data, sizeof(int)) != sizeof(int)) + return -EFAULT; + } + else + { + pgid = *(int *)data; + } + return lwp_tty_assign_foreground(tp, td, pgid); + } + case TIOCFLUSH: { + int flags = *(int *)data; + + if (flags == 0) + flags = (FREAD | FWRITE); + else + flags &= (FREAD | FWRITE); + tty_flush(tp, flags); + return 0; + } + case TIOCDRAIN: + /* Drain TTY output. */ + return tty_drain(tp, 0); + case TIOCGDRAINWAIT: + *(int *)data = tp->t_drainwait; + return 0; + case TIOCSDRAINWAIT: + error = priv_check(td, PRIV_TTY_DRAINWAIT); + if (error == 0) + tp->t_drainwait = *(int *)data; + return (error); + case TIOCCONS: + /* Set terminal as console TTY. */ + if (*(int *)data) + { + error = priv_check(td, PRIV_TTY_CONSOLE); + if (error) + return (error); + error = constty_set(tp); + } + else + { + error = constty_clear(tp); + } + return (error); + case TIOCGWINSZ: + /* Obtain window size. */ + *(struct winsize *)data = tp->t_winsize; + return 0; + case TIOCSWINSZ: + /* Set window size. */ + tty_set_winsize(tp, data); + return 0; + case TIOCEXCL: + tp->t_flags |= TF_EXCLUDE; + return 0; + case TIOCNXCL: + tp->t_flags &= ~TF_EXCLUDE; + return 0; + case TIOCSTOP: + tp->t_flags |= TF_STOPPED; + ttydevsw_pktnotify(tp, TIOCPKT_STOP); + return 0; + case TIOCSTART: + tp->t_flags &= ~TF_STOPPED; + tp->t_termios.c_lflag &= ~FLUSHO; + ttydevsw_outwakeup(tp); + ttydevsw_pktnotify(tp, TIOCPKT_START); + return 0; + case TIOCSTAT: + tty_info(tp); + return 0; + case TIOCSTI: + if ((fflag & FREAD) == 0 && priv_check(td, PRIV_TTY_STI)) + return -EPERM; + if (!tty_is_ctty(tp, td->lwp) && priv_check(td, PRIV_TTY_STI)) + return -EACCES; + ttydisc_rint(tp, *(char *)data, 0); + ttydisc_rint_done(tp); + return 0; + } + +#ifdef COMPAT_43TTY + return tty_ioctl_compat(tp, cmd, data, fflag, td); +#else /* !COMPAT_43TTY */ + return -ENOIOCTL; +#endif /* COMPAT_43TTY */ +} + +int tty_ioctl(struct lwp_tty *tp, rt_ubase_t cmd, void *data, int fflag, + struct rt_thread *td) +{ + int error; + + tty_assert_locked(tp); + + if (tty_gone(tp)) + return -ENXIO; + + error = ttydevsw_ioctl(tp, cmd, data, td); + if (error == -ENOIOCTL) + error = tty_generic_ioctl(tp, cmd, data, fflag, td); + + return error; +} + +int tty_checkoutq(struct lwp_tty *tp) +{ + /* 256 bytes should be enough to print a log message. */ + return (ttyoutq_bytesleft(&tp->t_outq) >= 256); +} + +void tty_hiwat_in_block(struct lwp_tty *tp) +{ + if ((tp->t_flags & TF_HIWAT_IN) == 0 && tp->t_termios.c_iflag & IXOFF && + tp->t_termios.c_cc[VSTOP] != _POSIX_VDISABLE) + { + /* + * Input flow control. Only enter the high watermark when we + * can successfully store the VSTOP character. + */ + if (ttyoutq_write_nofrag(&tp->t_outq, &tp->t_termios.c_cc[VSTOP], 1) == + 0) + tp->t_flags |= TF_HIWAT_IN; + } + else + { + /* No input flow control. */ + tp->t_flags |= TF_HIWAT_IN; + } +} + +void tty_hiwat_in_unblock(struct lwp_tty *tp) +{ + if (tp->t_flags & TF_HIWAT_IN && tp->t_termios.c_iflag & IXOFF && + tp->t_termios.c_cc[VSTART] != _POSIX_VDISABLE) + { + /* + * Input flow control. Only leave the high watermark when we + * can successfully store the VSTART character. + */ + if (ttyoutq_write_nofrag(&tp->t_outq, &tp->t_termios.c_cc[VSTART], 1) == + 0) + tp->t_flags &= ~TF_HIWAT_IN; + } + else + { + /* No input flow control. */ + tp->t_flags &= ~TF_HIWAT_IN; + } + + if (!tty_gone(tp)) + ttydevsw_inwakeup(tp); +} diff --git a/components/lwp/terminal/freebsd/tty_compat.c b/components/lwp/terminal/freebsd/tty_compat.c new file mode 100644 index 00000000000..0f2c70a5c5f --- /dev/null +++ b/components/lwp/terminal/freebsd/tty_compat.c @@ -0,0 +1,711 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * (tty_compat.c) + * The compatible layer which interacts with process management core (lwp) + * + * Change Logs: + * Date Author Notes + * 2023-11-13 Shell init ver. + */ + +#define DBG_TAG "lwp.tty" +#define DBG_LVL DBG_INFO +#include + +#include "../tty_config.h" +#include "../tty_internal.h" +#include "../terminal.h" + +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 1994-1995 Søren Schmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* is the tty and session leader already binding ? */ +static rt_bool_t _is_already_binding(lwp_tty_t tp, rt_lwp_t p) +{ + rt_bool_t rc; + rt_processgroup_t pgrp = p->pgrp; + + /* lwp is already locked */ + RT_ASSERT(pgrp); + + /* Note: pgrp->session is constant after process group is created */ + if (tp->t_session && tp->t_session == pgrp->session) + { + rc = RT_TRUE; + } + else + { + rc = RT_FALSE; + } + return rc; +} + +static rt_bool_t _is_tty_or_sess_busy(lwp_tty_t tp, rt_lwp_t p) +{ + rt_bool_t rc; + rt_session_t sess = p->pgrp->session; + + SESS_LOCK(sess); + if (sess->ctty) + { + rc = RT_TRUE; + } + else if (tp->t_session) + { + /** + * TODO: allow TTY stolen if the sess leader is killed while resource + * had not been collected + */ + if (tp->t_session->leader == RT_NULL) + rc = RT_FALSE; + else + rc = RT_TRUE; + } + else + { + rc = RT_FALSE; + } + SESS_UNLOCK(sess); + return rc; +} + +int lwp_tty_bg_stop(struct lwp_tty *tp, struct rt_condvar *cv) +{ + int error; + int revokecnt = tp->t_revokecnt; + rt_lwp_t self_lwp; + rt_thread_t header_thr; + rt_thread_t cur_thr = rt_thread_self(); + int jobctl_stopped; + + self_lwp = cur_thr->lwp; + RT_ASSERT(self_lwp); + + jobctl_stopped = self_lwp->jobctl_stopped; + + tty_lock_assert(tp, MA_OWNED | MA_NOTRECURSED); + MPASS(!tty_gone(tp)); + + LWP_LOCK(self_lwp); + header_thr = rt_list_entry(self_lwp->t_grp.prev, struct rt_thread, sibling); + if (!jobctl_stopped && header_thr == cur_thr && + cur_thr->sibling.prev == &self_lwp->t_grp) + { + /* update lwp status */ + jobctl_stopped = self_lwp->jobctl_stopped = RT_TRUE; + } + LWP_UNLOCK(self_lwp); + + error = cv_wait(cv, tp->t_mtx); + + if (jobctl_stopped) + { + self_lwp->jobctl_stopped = RT_FALSE; + } + + /* Bail out when the device slipped away. */ + if (tty_gone(tp)) + return -ENXIO; + + /* Restart the system call when we may have been revoked. */ + if (tp->t_revokecnt != revokecnt) + return -ERESTART; + + return error; +} + +/* process management */ +int lwp_tty_set_ctrl_proc(lwp_tty_t tp, rt_thread_t td) +{ + int rc = -1; + struct rt_lwp *p = td->lwp; + + tty_unlock(tp); + LWP_LOCK(p); + tty_lock(tp); + + if (is_sess_leader(p)) + { + if (_is_already_binding(tp, p)) + { + rc = 0; + } + else if (_is_tty_or_sess_busy(tp, p)) + { + rc = -EPERM; + } + else + { + /** + * Binding controlling process + * note: p->pgrp is protected by lwp lock; + * pgrp->session is always constant. + */ + tp->t_session = p->pgrp->session; + tp->t_session->ctty = tp; + tp->t_sessioncnt++; + + /* Assign foreground process group */ + tp->t_pgrp = p->pgrp; + p->term_ctrlterm = RT_TRUE; + + LOG_D("%s(sid=%d)", __func__, tp->t_session->sid); + rc = 0; + } + } + else + { + rc = -EPERM; + } + + LWP_UNLOCK(p); + + return rc; +} + +int lwp_tty_assign_foreground(lwp_tty_t tp, rt_thread_t td, int pgid) +{ + struct rt_processgroup *pg; + rt_lwp_t cur_lwp = td->lwp; + + tty_unlock(tp); + pg = lwp_pgrp_find_and_inc_ref(pgid); + if (pg == NULL || cur_lwp == NULL) + { + tty_lock(tp); + return -EPERM; + } + else + { + PGRP_LOCK(pg); + + if (pg->sid != cur_lwp->sid) + { + PGRP_UNLOCK(pg); + lwp_pgrp_dec_ref(pg); + LOG_D("%s: NoPerm current process (pid=%d, pgid=%d, sid=%d), " + "tagget group (pgid=%d, sid=%d)", __func__, + cur_lwp->pid, cur_lwp->pgid, cur_lwp->sid, pgid, pg->sid); + tty_lock(tp); + return -EPERM; + } + } + tty_lock(tp); + + /** + * Determine if this TTY is the controlling TTY after + * relocking the TTY. + */ + if (!tty_is_ctty(tp, td->lwp)) + { + PGRP_UNLOCK(pg); + LOG_D("%s: NoCTTY current process (pid=%d, pgid=%d, sid=%d), " + "tagget group (pgid=%d, sid=%d)", __func__, + cur_lwp->pid, cur_lwp->pgid, cur_lwp->sid, pgid, pg->sid); + return -ENOTTY; + } + tp->t_pgrp = pg; + PGRP_UNLOCK(pg); + lwp_pgrp_dec_ref(pg); + + /* Wake up the background process groups. */ + cv_broadcast(&tp->t_bgwait); + + LOG_D("%s: Foreground group %p (pgid=%d)", __func__, tp->t_pgrp, + tp->t_pgrp ? tp->t_pgrp->pgid : -1); + + return 0; +} + +/** + * Signalling processes. + */ + +void lwp_tty_signal_sessleader(struct lwp_tty *tp, int sig) +{ + struct rt_lwp *p; + struct rt_session *s; + + tty_assert_locked(tp); + MPASS(sig >= 1 && sig < _LWP_NSIG); + + /* Make signals start output again. */ + tp->t_flags &= ~TF_STOPPED; + tp->t_termios.c_lflag &= ~FLUSHO; + + /** + * Load s.leader exactly once to avoid race where s.leader is + * set to NULL by a concurrent invocation of killjobc() by the + * session leader. Note that we are not holding t_session's + * lock for the read. + */ + if ((s = tp->t_session) != NULL && + (p = (void *)rt_atomic_load((rt_atomic_t *)&s->leader)) != NULL) + { + lwp_signal_kill(p, sig, SI_KERNEL, 0); + } +} + +void lwp_tty_signal_pgrp(struct lwp_tty *tp, int sig) +{ + tty_assert_locked(tp); + MPASS(sig >= 1 && sig < _LWP_NSIG); + + /* Make signals start output again. */ + tp->t_flags &= ~TF_STOPPED; + tp->t_termios.c_lflag &= ~FLUSHO; + +#ifdef USING_BSD_SIGINFO + if (sig == SIGINFO && !(tp->t_termios.c_lflag & NOKERNINFO)) + tty_info(tp); +#endif /* USING_BSD_SIGINFO */ + + if (tp->t_pgrp != NULL) + { + PGRP_LOCK(tp->t_pgrp); + lwp_pgrp_signal_kill(tp->t_pgrp, sig, SI_KERNEL, 0); + PGRP_UNLOCK(tp->t_pgrp); + } +} + +/* bsd_ttydev_methods.d_ioctl */ + +rt_inline size_t _copy_to_user(void *to, void *from, size_t n) +{ + return lwp_put_to_user(to, from, n) == n ? 0 : -EFAULT; +} + +rt_inline size_t _copy_from_user(void *to, void *from, size_t n) +{ + return lwp_get_from_user(to, from, n) == n ? 0 : -EFAULT; +} + +static void termios_to_termio(struct termios *tios, struct termio *tio) +{ + memset(tio, 0, sizeof(*tio)); + tio->c_iflag = tios->c_iflag; + tio->c_oflag = tios->c_oflag; + tio->c_cflag = tios->c_cflag; + tio->c_lflag = tios->c_lflag; + tio->c_line = tios->c_line; + memcpy(tio->c_cc, tios->c_cc, NCC); +} + +static void termio_to_termios(struct termio *tio, struct termios *tios) +{ + int i; + + tios->c_iflag = tio->c_iflag; + tios->c_oflag = tio->c_oflag; + tios->c_cflag = tio->c_cflag; + tios->c_lflag = tio->c_lflag; + for (i = NCC; i < NCCS; i++) + tios->c_cc[i] = _POSIX_VDISABLE; + memcpy(tios->c_cc, tio->c_cc, NCC); +} + +#define IOCTL(cmd, data, fflags, td) \ + bsd_ttydev_methods.d_ioctl(tp, cmd, data, fflags, td) + +int lwp_tty_ioctl_adapter(lwp_tty_t tp, int cmd, int oflags, void *args, rt_thread_t td) +{ + long fflags = FFLAGS(oflags); + struct termios tios; + struct termio tio; + int error; + + LOG_D("%s(cmd=0x%x, args=%p)", __func__, cmd, args); + switch (cmd & 0xffff) + { + case TCGETS: + error = IOCTL(TIOCGETA, (rt_caddr_t)&tios, fflags, td); + if (error) + break; + error = _copy_to_user(args, &tios, sizeof(tios)); + break; + + case TCSETS: + error = _copy_from_user(&tios, args, sizeof(tios)); + if (error) + break; + error = (IOCTL(TIOCSETA, (rt_caddr_t)&tios, fflags, td)); + break; + + case TCSETSW: + error = _copy_from_user(&tios, args, sizeof(tios)); + if (error) + break; + error = (IOCTL(TIOCSETAW, (rt_caddr_t)&tios, fflags, td)); + break; + + case TCSETSF: + error = _copy_from_user(&tios, args, sizeof(tios)); + if (error) + break; + error = (IOCTL(TIOCSETAF, (rt_caddr_t)&tios, fflags, td)); + break; + + case TCGETA: + error = IOCTL(TIOCGETA, (rt_caddr_t)&tios, fflags, td); + if (error) + break; + termios_to_termio(&tios, &tio); + error = _copy_to_user((void *)args, &tio, sizeof(tio)); + break; + + case TCSETA: + error = _copy_from_user(&tio, (void *)args, sizeof(tio)); + if (error) + break; + termio_to_termios(&tio, &tios); + error = (IOCTL(TIOCSETA, (rt_caddr_t)&tios, fflags, td)); + break; + + case TCSETAW: + error = _copy_from_user(&tio, (void *)args, sizeof(tio)); + if (error) + break; + termio_to_termios(&tio, &tios); + error = (IOCTL(TIOCSETAW, (rt_caddr_t)&tios, fflags, td)); + break; + + case TCSETAF: + error = _copy_from_user(&tio, (void *)args, sizeof(tio)); + if (error) + break; + termio_to_termios(&tio, &tios); + error = (IOCTL(TIOCSETAF, (rt_caddr_t)&tios, fflags, td)); + break; + + case TCSBRK: + if (args != 0) + { + /** + * Linux manual: SVr4, UnixWare, Solaris, and Linux treat + * tcsendbreak(fd,arg) with nonzero arg like tcdrain(fd). + */ + error = IOCTL(TIOCDRAIN, (rt_caddr_t)&tios, fflags, td); + } + else + { + /** + * Linux manual: If the terminal is using asynchronous serial + * data transmission, and arg is zero, then send a break (a + * stream of zero bits) for between 0.25 and 0.5 seconds. + */ + LOG_D("%s: ioctl TCSBRK arg 0 not implemented", __func__); + error = -ENOSYS; + } + break; + +#ifdef USING_BSD_IOCTL_EXT + /* Software flow control */ + case TCXONC: { + switch (args->arg) + { + case TCOOFF: + args->cmd = TIOCSTOP; + break; + case TCOON: + args->cmd = TIOCSTART; + break; + case TCIOFF: + case TCION: { + int c; + struct write_args wr; + error = IOCTL(TIOCGETA, (rt_caddr_t)&tios, fflags, + td); + if (error) + break; + fdrop(fp, td); + c = (args->arg == TCIOFF) ? VSTOP : VSTART; + c = tios.c_cc[c]; + if (c != _POSIX_VDISABLE) + { + wr.fd = args->fd; + wr.buf = &c; + wr.nbyte = sizeof(c); + return (sys_write(td, &wr)); + } + else + return 0; + } + default: + fdrop(fp, td); + return -EINVAL; + } + args->arg = 0; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; + } +#endif /* USING_BSD_IOCTL_EXT */ + case TCFLSH: { + int val; + error = 0; + switch ((rt_base_t)args) + { + case TCIFLUSH: + val = FREAD; + break; + case TCOFLUSH: + val = FWRITE; + break; + case TCIOFLUSH: + val = FREAD | FWRITE; + break; + default: + error = -EINVAL; + break; + } + if (!error) + error = (IOCTL(TIOCFLUSH, (rt_caddr_t)&val, fflags, td)); + break; + } + +#ifdef USING_BSD_IOCTL_EXT + case TIOCEXCL: + args->cmd = TIOCEXCL; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; + + case TIOCNXCL: + args->cmd = TIOCNXCL; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; +#endif /* USING_BSD_IOCTL_EXT */ + + /* Controlling terminal */ + case TIOCSCTTY: + case TIOCNOTTY: + + /* Process group and session ID */ + case TIOCGPGRP: + case TIOCSPGRP: + case TIOCGSID: + + /* TIOCOUTQ */ + /* TIOCSTI */ + case TIOCGWINSZ: + case TIOCSWINSZ: + error = IOCTL(cmd, (rt_caddr_t)args, fflags, td); + break; +#ifdef USING_BSD_IOCTL_EXT + case TIOCMGET: + args->cmd = TIOCMGET; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; + + case TIOCMBIS: + args->cmd = TIOCMBIS; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; + + case TIOCMBIC: + args->cmd = TIOCMBIC; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; + + case TIOCMSET: + args->cmd = TIOCMSET; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; + + /* TIOCGSOFTCAR */ + /* TIOCSSOFTCAR */ + + case FIONREAD: /* TIOCINQ */ + args->cmd = FIONREAD; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; + + /* TIOCLINUX */ + + case TIOCCONS: + args->cmd = TIOCCONS; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; + + case TIOCGSERIAL: { + struct linux_serial_struct lss; + + bzero(&lss, sizeof(lss)); + lss.type = PORT_16550A; + lss.flags = 0; + lss.close_delay = 0; + error = copyout(&lss, (void *)args->arg, sizeof(lss)); + break; + } + + case TIOCSSERIAL: { + struct linux_serial_struct lss; + error = copyin((void *)args->arg, &lss, sizeof(lss)); + if (error) + break; + /* XXX - It really helps to have an implementation that + * does nothing. NOT! + */ + error = 0; + break; + } + + case TIOCPKT: + args->cmd = TIOCPKT; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; + + case FIONBIO: + args->cmd = FIONBIO; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; + + case TIOCSETD: { + int line; + switch (args->arg) + { + case N_TTY: + line = TTYDISC; + break; + case N_SLIP: + line = SLIPDISC; + break; + case N_PPP: + line = PPPDISC; + break; + default: + fdrop(fp, td); + return -EINVAL; + } + error = (ioctl_emit(TIOCSETD, (rt_caddr_t)&line, fflags, td)); + break; + } + + case TIOCGETD: { + int linux_line; + int bsd_line = TTYDISC; + error = + ioctl_emit(TIOCGETD, (rt_caddr_t)&bsd_line, fflags, td); + if (error) + break; + switch (bsd_line) + { + case TTYDISC: + linux_line = N_TTY; + break; + case SLIPDISC: + linux_line = N_SLIP; + break; + case PPPDISC: + linux_line = N_PPP; + break; + default: + fdrop(fp, td); + return -EINVAL; + } + error = (copyout(&linux_line, (void *)args->arg, sizeof(int))); + break; + } + + /* TCSBRKP */ + /* TIOCTTYGSTRUCT */ + + case FIONCLEX: + args->cmd = FIONCLEX; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; + + case FIOCLEX: + args->cmd = FIOCLEX; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; + + case FIOASYNC: + args->cmd = FIOASYNC; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; + + /* TIOCSERCONFIG */ + /* TIOCSERGWILD */ + /* TIOCSERSWILD */ + /* TIOCGLCKTRMIOS */ + /* TIOCSLCKTRMIOS */ + + case TIOCSBRK: + args->cmd = TIOCSBRK; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; + + case TIOCCBRK: + args->cmd = TIOCCBRK; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; + case TIOCGPTN: { + int nb; + + error = ioctl_emit(TIOCGPTN, (rt_caddr_t)&nb, fflags, td); + if (!error) + error = copyout(&nb, (void *)args->arg, sizeof(int)); + break; + } + case TIOCGPTPEER: + linux_msg(td, "unsupported ioctl TIOCGPTPEER"); + error = -ENOIOCTL; + break; + case TIOCSPTLCK: + /* + * Our unlockpt() does nothing. Check that fd refers + * to a pseudo-terminal master device. + */ + args->cmd = TIOCPTMASTER; + error = (sys_ioctl(td, (struct ioctl_args *)args)); + break; +#endif /* USING_BSD_IOCTL_EXT */ + + /** + * those are for current implementation of devfs, and we dont want to + * log them + */ + case F_DUPFD: + case F_DUPFD_CLOEXEC: + case F_GETFD: + case F_SETFD: + case F_GETFL: + case F_SETFL: + /* fall back to fs */ + error = -ENOIOCTL; + break; + default: + LOG_I("%s: unhandle commands 0x%x", __func__, cmd); + error = -ENOSYS; + break; + } + + return (error); +} diff --git a/components/lwp/terminal/freebsd/tty_inq.c b/components/lwp/terminal/freebsd/tty_inq.c new file mode 100644 index 00000000000..1dc748d6c2f --- /dev/null +++ b/components/lwp/terminal/freebsd/tty_inq.c @@ -0,0 +1,507 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-13 Shell init ver. + */ + +#include "../bsd_porting.h" +#include "../terminal.h" + +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2008 Ed Schouten + * All rights reserved. + * + * Portions of this software were developed under sponsorship from Snow + * B.V., the Netherlands. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * TTY input queue buffering. + * + * Unlike the output queue, the input queue has more features that are + * needed to properly implement various features offered by the TTY + * interface: + * + * - Data can be removed from the tail of the queue, which is used to + * implement backspace. + * - Once in a while, input has to be `canonicalized'. When ICANON is + * turned on, this will be done after a CR has been inserted. + * Otherwise, it should be done after any character has been inserted. + * - The input queue can store one bit per byte, called the quoting bit. + * This bit is used by TTYDISC to make backspace work on quoted + * characters. + * + * In most cases, there is probably less input than output, so unlike + * the outq, we'll stick to 128 byte blocks here. + */ + +static int ttyinq_flush_secure = 1; + +#define TTYINQ_QUOTESIZE (TTYINQ_DATASIZE / BMSIZE) +#define BMSIZE 32 +#define GETBIT(tib, boff) \ + ((tib)->tib_quotes[(boff) / BMSIZE] & (1 << ((boff) % BMSIZE))) +#define SETBIT(tib, boff) \ + ((tib)->tib_quotes[(boff) / BMSIZE] |= (1 << ((boff) % BMSIZE))) +#define CLRBIT(tib, boff) \ + ((tib)->tib_quotes[(boff) / BMSIZE] &= ~(1 << ((boff) % BMSIZE))) + +struct ttyinq_block +{ + struct ttyinq_block *tib_prev; + struct ttyinq_block *tib_next; + uint32_t tib_quotes[TTYINQ_QUOTESIZE]; + char tib_data[TTYINQ_DATASIZE]; +}; + +static uma_zone_t ttyinq_zone; + +#define TTYINQ_INSERT_TAIL(ti, tib) \ + do \ + { \ + if (ti->ti_end == 0) \ + { \ + tib->tib_prev = NULL; \ + tib->tib_next = ti->ti_firstblock; \ + ti->ti_firstblock = tib; \ + } \ + else \ + { \ + tib->tib_prev = ti->ti_lastblock; \ + tib->tib_next = ti->ti_lastblock->tib_next; \ + ti->ti_lastblock->tib_next = tib; \ + } \ + if (tib->tib_next != NULL) \ + tib->tib_next->tib_prev = tib; \ + ti->ti_nblocks++; \ + } while (0) + +#define TTYINQ_REMOVE_HEAD(ti) \ + do \ + { \ + ti->ti_firstblock = ti->ti_firstblock->tib_next; \ + if (ti->ti_firstblock != NULL) \ + ti->ti_firstblock->tib_prev = NULL; \ + ti->ti_nblocks--; \ + } while (0) + +#define TTYINQ_RECYCLE(ti, tib) \ + do \ + { \ + if (ti->ti_quota <= ti->ti_nblocks) \ + uma_zfree(ttyinq_zone, tib); \ + else \ + TTYINQ_INSERT_TAIL(ti, tib); \ + } while (0) + +int ttyinq_setsize(struct ttyinq *ti, struct lwp_tty *tp, size_t size) +{ + struct ttyinq_block *tib; + + ti->ti_quota = howmany(size, TTYINQ_DATASIZE); + + while (ti->ti_quota > ti->ti_nblocks) + { + /* + * List is getting bigger. + * Add new blocks to the tail of the list. + * + * We must unlock the TTY temporarily, because we need + * to allocate memory. This won't be a problem, because + * in the worst case, another thread ends up here, which + * may cause us to allocate too many blocks, but this + * will be caught by the loop below. + */ + tty_unlock(tp); + tib = uma_zalloc(ttyinq_zone, M_WAITOK); + tty_lock(tp); + + if (tty_gone(tp)) + { + uma_zfree(ttyinq_zone, tib); + return -ENXIO; + } + + TTYINQ_INSERT_TAIL(ti, tib); + } + return 0; +} + +void ttyinq_free(struct ttyinq *ti) +{ + struct ttyinq_block *tib; + + ttyinq_flush(ti); + ti->ti_quota = 0; + + while ((tib = ti->ti_firstblock) != NULL) + { + TTYINQ_REMOVE_HEAD(ti); + uma_zfree(ttyinq_zone, tib); + } + + MPASS(ti->ti_nblocks == 0); +} + +int ttyinq_read_uio(struct ttyinq *ti, struct lwp_tty *tp, struct uio *uio, + size_t rlen, size_t flen) +{ + MPASS(rlen <= uio->uio_resid); + + while (rlen > 0) + { + int error; + struct ttyinq_block *tib; + size_t cbegin, cend, clen; + + /* See if there still is data. */ + if (ti->ti_begin == ti->ti_linestart) + return 0; + tib = ti->ti_firstblock; + if (tib == NULL) + return 0; + + /* + * The end address should be the lowest of these three: + * - The write pointer + * - The blocksize - we can't read beyond the block + * - The end address if we could perform the full read + */ + cbegin = ti->ti_begin; + cend = MIN(MIN(ti->ti_linestart, ti->ti_begin + rlen), TTYINQ_DATASIZE); + clen = cend - cbegin; + MPASS(clen >= flen); + rlen -= clen; + + /* + * We can prevent buffering in some cases: + * - We need to read the block until the end. + * - We don't need to read the block until the end, but + * there is no data beyond it, which allows us to move + * the write pointer to a new block. + */ + if (cend == TTYINQ_DATASIZE || cend == ti->ti_end) + { + /* + * Fast path: zero copy. Remove the first block, + * so we can unlock the TTY temporarily. + */ + TTYINQ_REMOVE_HEAD(ti); + ti->ti_begin = 0; + + /* + * Because we remove the first block, we must + * fix up the block offsets. + */ +#define CORRECT_BLOCK(t) \ + do \ + { \ + if (t <= TTYINQ_DATASIZE) \ + t = 0; \ + else \ + t -= TTYINQ_DATASIZE; \ + } while (0) + CORRECT_BLOCK(ti->ti_linestart); + CORRECT_BLOCK(ti->ti_reprint); + CORRECT_BLOCK(ti->ti_end); +#undef CORRECT_BLOCK + + /* + * Temporary unlock and copy the data to + * userspace. We may need to flush trailing + * bytes, like EOF characters. + */ + tty_unlock(tp); + error = uiomove(tib->tib_data + cbegin, clen - flen, uio); + tty_lock(tp); + + /* Block can now be readded to the list. */ + TTYINQ_RECYCLE(ti, tib); + } + else + { + char ob[TTYINQ_DATASIZE - 1]; + + /* + * Slow path: store data in a temporary buffer. + */ + memcpy(ob, tib->tib_data + cbegin, clen - flen); + ti->ti_begin += clen; + MPASS(ti->ti_begin < TTYINQ_DATASIZE); + + /* Temporary unlock and copy the data to userspace. */ + tty_unlock(tp); + error = uiomove(ob, clen - flen, uio); + tty_lock(tp); + } + + if (error != 0) + return error; + if (tty_gone(tp)) + return -ENXIO; + } + + return 0; +} + +rt_inline void ttyinq_set_quotes(struct ttyinq_block *tib, size_t offset, + size_t length, int value) +{ + if (value) + { + /* Set the bits. */ + for (; length > 0; length--, offset++) SETBIT(tib, offset); + } + else + { + /* Unset the bits. */ + for (; length > 0; length--, offset++) CLRBIT(tib, offset); + } +} + +size_t ttyinq_write(struct ttyinq *ti, const void *buf, size_t nbytes, + int quote) +{ + const char *cbuf = buf; + struct ttyinq_block *tib; + unsigned int boff; + size_t l; + + while (nbytes > 0) + { + boff = ti->ti_end % TTYINQ_DATASIZE; + + if (ti->ti_end == 0) + { + /* First time we're being used or drained. */ + MPASS(ti->ti_begin == 0); + tib = ti->ti_firstblock; + if (tib == NULL) + { + /* Queue has no blocks. */ + break; + } + ti->ti_lastblock = tib; + } + else if (boff == 0) + { + /* We reached the end of this block on last write. */ + tib = ti->ti_lastblock->tib_next; + if (tib == NULL) + { + /* We've reached the watermark. */ + break; + } + ti->ti_lastblock = tib; + } + else + { + tib = ti->ti_lastblock; + } + + /* Don't copy more than was requested. */ + l = MIN(nbytes, TTYINQ_DATASIZE - boff); + MPASS(l > 0); + memcpy(tib->tib_data + boff, cbuf, l); + + /* Set the quoting bits for the proper region. */ + ttyinq_set_quotes(tib, boff, l, quote); + + cbuf += l; + nbytes -= l; + ti->ti_end += l; + } + + return (cbuf - (const char *)buf); +} + +int ttyinq_write_nofrag(struct ttyinq *ti, const void *buf, size_t nbytes, + int quote) +{ + size_t ret __unused; + + if (ttyinq_bytesleft(ti) < nbytes) + return -1; + + /* We should always be able to write it back. */ + ret = ttyinq_write(ti, buf, nbytes, quote); + MPASS(ret == nbytes); + + return 0; +} + +void ttyinq_canonicalize(struct ttyinq *ti) +{ + ti->ti_linestart = ti->ti_reprint = ti->ti_end; + ti->ti_startblock = ti->ti_reprintblock = ti->ti_lastblock; +} + +size_t ttyinq_findchar(struct ttyinq *ti, const char *breakc, size_t maxlen, + char *lastc) +{ + struct ttyinq_block *tib = ti->ti_firstblock; + unsigned int boff = ti->ti_begin; + unsigned int bend = + MIN(MIN(TTYINQ_DATASIZE, ti->ti_linestart), ti->ti_begin + maxlen); + + MPASS(maxlen > 0); + + if (tib == NULL) + return 0; + + while (boff < bend) + { + if (strchr(breakc, tib->tib_data[boff]) && !GETBIT(tib, boff)) + { + *lastc = tib->tib_data[boff]; + return (boff - ti->ti_begin + 1); + } + boff++; + } + + /* Not found - just process the entire block. */ + return (bend - ti->ti_begin); +} + +void ttyinq_flush(struct ttyinq *ti) +{ + struct ttyinq_block *tib; + + ti->ti_begin = 0; + ti->ti_linestart = 0; + ti->ti_reprint = 0; + ti->ti_end = 0; + + /* Zero all data in the input queue to get rid of passwords. */ + if (ttyinq_flush_secure) + { + for (tib = ti->ti_firstblock; tib != NULL; tib = tib->tib_next) + memset(&tib->tib_data, 0, sizeof tib->tib_data); + } +} + +int ttyinq_peekchar(struct ttyinq *ti, char *c, int *quote) +{ + unsigned int boff; + struct ttyinq_block *tib = ti->ti_lastblock; + + if (ti->ti_linestart == ti->ti_end) + return -1; + + MPASS(ti->ti_end > 0); + boff = (ti->ti_end - 1) % TTYINQ_DATASIZE; + + *c = tib->tib_data[boff]; + *quote = GETBIT(tib, boff); + + return 0; +} + +void ttyinq_unputchar(struct ttyinq *ti) +{ + MPASS(ti->ti_linestart < ti->ti_end); + + if (--ti->ti_end % TTYINQ_DATASIZE == 0) + { + /* Roll back to the previous block. */ + ti->ti_lastblock = ti->ti_lastblock->tib_prev; + /* + * This can only fail if we are unputchar()'ing the + * first character in the queue. + */ + MPASS((ti->ti_lastblock == NULL) == (ti->ti_end == 0)); + } +} + +void ttyinq_reprintpos_set(struct ttyinq *ti) +{ + ti->ti_reprint = ti->ti_end; + ti->ti_reprintblock = ti->ti_lastblock; +} + +void ttyinq_reprintpos_reset(struct ttyinq *ti) +{ + ti->ti_reprint = ti->ti_linestart; + ti->ti_reprintblock = ti->ti_startblock; +} + +static void ttyinq_line_iterate(struct ttyinq *ti, + ttyinq_line_iterator_t *iterator, void *data, + unsigned int offset, struct ttyinq_block *tib) +{ + unsigned int boff; + + /* Use the proper block when we're at the queue head. */ + if (offset == 0) + tib = ti->ti_firstblock; + + /* Iterate all characters and call the iterator function. */ + for (; offset < ti->ti_end; offset++) + { + boff = offset % TTYINQ_DATASIZE; + MPASS(tib != NULL); + + /* Call back the iterator function. */ + iterator(data, tib->tib_data[boff], GETBIT(tib, boff)); + + /* Last byte iterated - go to the next block. */ + if (boff == TTYINQ_DATASIZE - 1) + tib = tib->tib_next; + } +} + +void ttyinq_line_iterate_from_linestart(struct ttyinq *ti, + ttyinq_line_iterator_t *iterator, + void *data) +{ + ttyinq_line_iterate(ti, iterator, data, ti->ti_linestart, + ti->ti_startblock); +} + +void ttyinq_line_iterate_from_reprintpos(struct ttyinq *ti, + ttyinq_line_iterator_t *iterator, + void *data) +{ + ttyinq_line_iterate(ti, iterator, data, ti->ti_reprint, + ti->ti_reprintblock); +} + +static int ttyinq_startup(void) +{ + ttyinq_zone = uma_zcreate("ttyinq", sizeof(struct ttyinq_block), NULL, NULL, + NULL, NULL, UMA_ALIGN_PTR, 0); + return 0; +} +INIT_PREV_EXPORT(ttyinq_startup); + +#if 0 + +SYSINIT(ttyinq, SI_SUB_DRIVERS, SI_ORDER_FIRST, ttyinq_startup, NULL); +#endif diff --git a/components/lwp/terminal/freebsd/tty_outq.c b/components/lwp/terminal/freebsd/tty_outq.c new file mode 100644 index 00000000000..214309813e0 --- /dev/null +++ b/components/lwp/terminal/freebsd/tty_outq.c @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-13 Shell init ver. + */ + +#include "../bsd_porting.h" +#include "../terminal.h" + +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2008 Ed Schouten + * All rights reserved. + * + * Portions of this software were developed under sponsorship from Snow + * B.V., the Netherlands. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * TTY output queue buffering. + * + * The previous design of the TTY layer offered the so-called clists. + * These clists were used for both the input queues and the output + * queue. We don't use certain features on the output side, like quoting + * bits for parity marking and such. This mechanism is similar to the + * old clists, but only contains the features we need to buffer the + * output. + */ + +struct ttyoutq_block +{ + struct ttyoutq_block *tob_next; + char tob_data[TTYOUTQ_DATASIZE]; +}; + +static uma_zone_t ttyoutq_zone; + +#define TTYOUTQ_INSERT_TAIL(to, tob) \ + do \ + { \ + if (to->to_end == 0) \ + { \ + tob->tob_next = to->to_firstblock; \ + to->to_firstblock = tob; \ + } \ + else \ + { \ + tob->tob_next = to->to_lastblock->tob_next; \ + to->to_lastblock->tob_next = tob; \ + } \ + to->to_nblocks++; \ + } while (0) + +#define TTYOUTQ_REMOVE_HEAD(to) \ + do \ + { \ + to->to_firstblock = to->to_firstblock->tob_next; \ + to->to_nblocks--; \ + } while (0) + +#define TTYOUTQ_RECYCLE(to, tob) \ + do \ + { \ + if (to->to_quota <= to->to_nblocks) \ + uma_zfree(ttyoutq_zone, tob); \ + else \ + TTYOUTQ_INSERT_TAIL(to, tob); \ + } while (0) + +void ttyoutq_flush(struct ttyoutq *to) +{ + to->to_begin = 0; + to->to_end = 0; +} + +int ttyoutq_setsize(struct ttyoutq *to, struct lwp_tty *tp, size_t size) +{ + struct ttyoutq_block *tob; + + to->to_quota = howmany(size, TTYOUTQ_DATASIZE); + + while (to->to_quota > to->to_nblocks) + { + /* + * List is getting bigger. + * Add new blocks to the tail of the list. + * + * We must unlock the TTY temporarily, because we need + * to allocate memory. This won't be a problem, because + * in the worst case, another thread ends up here, which + * may cause us to allocate too many blocks, but this + * will be caught by the loop below. + */ + tty_unlock(tp); + tob = uma_zalloc(ttyoutq_zone, M_WAITOK); + tty_lock(tp); + + if (tty_gone(tp)) + { + uma_zfree(ttyoutq_zone, tob); + return -ENXIO; + } + + TTYOUTQ_INSERT_TAIL(to, tob); + } + return 0; +} + +void ttyoutq_free(struct ttyoutq *to) +{ + struct ttyoutq_block *tob; + + ttyoutq_flush(to); + to->to_quota = 0; + + while ((tob = to->to_firstblock) != NULL) + { + TTYOUTQ_REMOVE_HEAD(to); + uma_zfree(ttyoutq_zone, tob); + } + + MPASS(to->to_nblocks == 0); +} + +size_t ttyoutq_read(struct ttyoutq *to, void *buf, size_t len) +{ + char *cbuf = buf; + + while (len > 0) + { + struct ttyoutq_block *tob; + size_t cbegin, cend, clen; + + /* See if there still is data. */ + if (to->to_begin == to->to_end) + break; + tob = to->to_firstblock; + if (tob == NULL) + break; + + /* + * The end address should be the lowest of these three: + * - The write pointer + * - The blocksize - we can't read beyond the block + * - The end address if we could perform the full read + */ + cbegin = to->to_begin; + cend = MIN(MIN(to->to_end, to->to_begin + len), TTYOUTQ_DATASIZE); + clen = cend - cbegin; + + /* Copy the data out of the buffers. */ + memcpy(cbuf, tob->tob_data + cbegin, clen); + cbuf += clen; + len -= clen; + + if (cend == to->to_end) + { + /* Read the complete queue. */ + to->to_begin = 0; + to->to_end = 0; + } + else if (cend == TTYOUTQ_DATASIZE) + { + /* Read the block until the end. */ + TTYOUTQ_REMOVE_HEAD(to); + to->to_begin = 0; + to->to_end -= TTYOUTQ_DATASIZE; + TTYOUTQ_RECYCLE(to, tob); + } + else + { + /* Read the block partially. */ + to->to_begin += clen; + } + } + + return cbuf - (char *)buf; +} + +/* + * An optimized version of ttyoutq_read() which can be used in pseudo + * TTY drivers to directly copy data from the outq to userspace, instead + * of buffering it. + * + * We can only copy data directly if we need to read the entire block + * back to the user, because we temporarily remove the block from the + * queue. Otherwise we need to copy it to a temporary buffer first, to + * make sure data remains in the correct order. + */ +int ttyoutq_read_uio(struct ttyoutq *to, struct lwp_tty *tp, struct uio *uio) +{ + while (uio->uio_resid > 0) + { + int error; + struct ttyoutq_block *tob; + size_t cbegin, cend, clen; + + /* See if there still is data. */ + if (to->to_begin == to->to_end) + return 0; + tob = to->to_firstblock; + if (tob == NULL) + return 0; + + /* + * The end address should be the lowest of these three: + * - The write pointer + * - The blocksize - we can't read beyond the block + * - The end address if we could perform the full read + */ + cbegin = to->to_begin; + cend = MIN(MIN(to->to_end, to->to_begin + uio->uio_resid), + TTYOUTQ_DATASIZE); + clen = cend - cbegin; + + /* + * We can prevent buffering in some cases: + * - We need to read the block until the end. + * - We don't need to read the block until the end, but + * there is no data beyond it, which allows us to move + * the write pointer to a new block. + */ + if (cend == TTYOUTQ_DATASIZE || cend == to->to_end) + { + /* + * Fast path: zero copy. Remove the first block, + * so we can unlock the TTY temporarily. + */ + TTYOUTQ_REMOVE_HEAD(to); + to->to_begin = 0; + if (to->to_end <= TTYOUTQ_DATASIZE) + to->to_end = 0; + else + to->to_end -= TTYOUTQ_DATASIZE; + + /* Temporary unlock and copy the data to userspace. */ + tty_unlock(tp); + error = uiomove(tob->tob_data + cbegin, clen, uio); + tty_lock(tp); + + /* Block can now be readded to the list. */ + TTYOUTQ_RECYCLE(to, tob); + } + else + { + char ob[TTYOUTQ_DATASIZE - 1]; + + /* + * Slow path: store data in a temporary buffer. + */ + memcpy(ob, tob->tob_data + cbegin, clen); + to->to_begin += clen; + MPASS(to->to_begin < TTYOUTQ_DATASIZE); + + /* Temporary unlock and copy the data to userspace. */ + tty_unlock(tp); + error = uiomove(ob, clen, uio); + tty_lock(tp); + } + + if (error != 0) + return error; + } + + return 0; +} + +size_t ttyoutq_write(struct ttyoutq *to, const void *buf, size_t nbytes) +{ + const char *cbuf = buf; + struct ttyoutq_block *tob; + unsigned int boff; + size_t l; + + while (nbytes > 0) + { + boff = to->to_end % TTYOUTQ_DATASIZE; + + if (to->to_end == 0) + { + /* First time we're being used or drained. */ + MPASS(to->to_begin == 0); + tob = to->to_firstblock; + if (tob == NULL) + { + /* Queue has no blocks. */ + break; + } + to->to_lastblock = tob; + } + else if (boff == 0) + { + /* We reached the end of this block on last write. */ + tob = to->to_lastblock->tob_next; + if (tob == NULL) + { + /* We've reached the watermark. */ + break; + } + to->to_lastblock = tob; + } + else + { + tob = to->to_lastblock; + } + + /* Don't copy more than was requested. */ + l = MIN(nbytes, TTYOUTQ_DATASIZE - boff); + MPASS(l > 0); + memcpy(tob->tob_data + boff, cbuf, l); + + cbuf += l; + nbytes -= l; + to->to_end += l; + } + + return (cbuf - (const char *)buf); +} + +int ttyoutq_write_nofrag(struct ttyoutq *to, const void *buf, size_t nbytes) +{ + size_t ret __unused; + + if (ttyoutq_bytesleft(to) < nbytes) + return -1; + + /* We should always be able to write it back. */ + ret = ttyoutq_write(to, buf, nbytes); + MPASS(ret == nbytes); + + return 0; +} + +static int ttyoutq_startup(void) +{ + ttyoutq_zone = uma_zcreate("ttyoutq", sizeof(struct ttyoutq_block), NULL, + NULL, NULL, NULL, UMA_ALIGN_PTR, 0); + return 0; +} +INIT_PREV_EXPORT(ttyoutq_startup); + +#if 0 +SYSINIT(ttyoutq, SI_SUB_DRIVERS, SI_ORDER_FIRST, ttyoutq_startup, NULL); +#endif diff --git a/components/lwp/terminal/freebsd/tty_pts.c b/components/lwp/terminal/freebsd/tty_pts.c new file mode 100644 index 00000000000..d25e668d861 --- /dev/null +++ b/components/lwp/terminal/freebsd/tty_pts.c @@ -0,0 +1,837 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-12-07 Shell init ver. + */ + +#include +#include +#include +#include +#include + +#include + +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2008 Ed Schouten + * All rights reserved. + * + * Portions of this software were developed under sponsorship from Snow + * B.V., the Netherlands. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#define PTS_EXTERNAL + +/* + * Per-PTS structure. + * + * List of locks + * (t) locked by tty_lock() + * (c) const until freeing + */ +struct pts_softc +{ + int pts_unit; /* (c) Device unit number. */ + unsigned int pts_flags; /* (t) Device flags. */ +#define PTS_PKT 0x1 /* Packet mode. */ +#define PTS_FINISHED 0x2 /* Return errors on read()/write(). */ +#define PTS_PTLOCKED 0x4 /* ioctl %TIOCSPTLCK/%TIOCGPTLCK */ + char pts_pkt; /* (t) Unread packet mode data. */ + + struct rt_condvar pts_inwait; /* (t) Blocking write() on master. */ + struct rt_wqueue pts_inpoll; /* (t) Select queue for write(). */ + struct rt_condvar pts_outwait; /* (t) Blocking read() on master. */ + struct rt_wqueue pts_outpoll; /* (t) Select queue for read(). */ + + struct ucred *pts_cred; /* (c) Resource limit. */ + rt_device_t pts_master; /** (c) Master device. + * (Note: in rtsmart kernel, we support + * multi-instance ptmx ) + */ +}; + +/** + * Controller-side file operations. + * (P)seudo-(T)erminal (M)ultiple(X)er + */ + +static int ptsdev_read(struct lwp_tty *tp, struct uio *uio, + struct ucred *active_cred, int oflags, + struct rt_thread *td) +{ + struct pts_softc *psc = tty_softc(tp); + int error = 0; + char pkt; + + if (uio->uio_resid == 0) + return (0); + + tty_lock(tp); + + for (;;) + { + /* + * Implement packet mode. When packet mode is turned on, + * the first byte contains a bitmask of events that + * occurred (start, stop, flush, window size, etc). + */ + if (psc->pts_flags & PTS_PKT && psc->pts_pkt) + { + pkt = psc->pts_pkt; + psc->pts_pkt = 0; + tty_unlock(tp); + + error = uiomove(&pkt, 1, uio); + return (error); + } + + /* + * Transmit regular data. + * + * XXX: We shouldn't use ttydisc_getc_poll()! Even + * though in this implementation, there is likely going + * to be data, we should just call ttydisc_getc_uio() + * and use its return value to sleep. + */ + if (ttydisc_getc_poll(tp)) + { + if (psc->pts_flags & PTS_PKT) + { + /* + * XXX: Small race. Fortunately PTY + * consumers aren't multithreaded. + */ + + tty_unlock(tp); + pkt = TIOCPKT_DATA; + error = uiomove(&pkt, 1, uio); + if (error) + return (error); + tty_lock(tp); + } + + error = ttydisc_getc_uio(tp, uio); + break; + } + + /* Maybe the device isn't used anyway. */ + if (psc->pts_flags & PTS_FINISHED) + break; + + /* Wait for more data. */ + if (oflags & O_NONBLOCK) + { + error = EWOULDBLOCK; + break; + } + error = cv_wait_sig(&psc->pts_outwait, tp->t_mtx); + if (error != 0) + break; + } + + tty_unlock(tp); + + return (error); +} + +static int ptsdev_write(struct lwp_tty *tp, struct uio *uio, + struct ucred *active_cred, int oflags, + struct rt_thread *td) +{ + struct pts_softc *psc = tty_softc(tp); + char ib[256], *ibstart; + size_t iblen, rintlen; + int error = 0; + + if (uio->uio_resid == 0) + return (0); + + for (;;) + { + ibstart = ib; + iblen = MIN(uio->uio_resid, sizeof ib); + error = uiomove(ib, iblen, uio); + + tty_lock(tp); + if (error != 0) + { + iblen = 0; + goto done; + } + + /* + * When possible, avoid the slow path. rint_bypass() + * copies all input to the input queue at once. + */ + MPASS(iblen > 0); + do + { + rintlen = ttydisc_rint_simple(tp, ibstart, iblen); + ibstart += rintlen; + iblen -= rintlen; + if (iblen == 0) + { + /* All data written. */ + break; + } + + /* Maybe the device isn't used anyway. */ + if (psc->pts_flags & PTS_FINISHED) + { + error = -EIO; + goto done; + } + + /* Wait for more data. */ + if (oflags & O_NONBLOCK) + { + error = -EWOULDBLOCK; + goto done; + } + + /* Wake up users on the slave side. */ + ttydisc_rint_done(tp); + error = cv_wait_sig(&psc->pts_inwait, tp->t_mtx); + if (error != 0) + goto done; + } while (iblen > 0); + + if (uio->uio_resid == 0) + break; + tty_unlock(tp); + } + +done: + ttydisc_rint_done(tp); + tty_unlock(tp); + + /* + * Don't account for the part of the buffer that we couldn't + * pass to the TTY. + */ + uio->uio_resid += iblen; + return (error); +} + +static int ptsdev_ioctl(struct lwp_tty *tp, rt_ubase_t cmd, void *data, + struct ucred *active_cred, int fflags, + struct rt_thread *td) +{ + struct pts_softc *psc = tty_softc(tp); + int error = 0, sig; + + switch (cmd) + { +#ifdef USING_BSD_IOCTL_EXT + case FIODTYPE: + *(int *)data = D_TTY; + return (0); +#endif + case FIONBIO: + /* This device supports non-blocking operation. */ + return (0); + case FIONREAD: + tty_lock(tp); + if (psc->pts_flags & PTS_FINISHED) + { + /* Force read() to be called. */ + *(int *)data = 1; + } + else + { + *(int *)data = ttydisc_getc_poll(tp); + } + tty_unlock(tp); + return (0); +#ifdef USING_BSD_IOCTL_EXT + case FIODGNAME: +#ifdef COMPAT_FREEBSD32 + case FIODGNAME_32: +#endif + { + struct fiodgname_arg *fgn; + const char *p; + int i; + + /* Reverse device name lookups, for ptsname() and ttyname(). */ + fgn = data; + p = tty_devname(tp); + i = strlen(p) + 1; + if (i > fgn->len) + return -EINVAL; + return (copyout(p, fiodgname_buf_get_ptr(fgn, cmd), i)); + } +#endif + /* + * We need to implement TIOCGPGRP and TIOCGSID here again. When + * called on the pseudo-terminal master, it should not check if + * the terminal is the foreground terminal of the calling + * process. + * + * TIOCGETA is also implemented here. Various Linux PTY routines + * often call isatty(), which is implemented by tcgetattr(). + */ + case TIOCGETA: + /* Obtain terminal flags through tcgetattr(). */ + tty_lock(tp); + *(struct termios *)data = tp->t_termios; + tty_unlock(tp); + return (0); + case TIOCSETAF: + case TIOCSETAW: + /* + * We must make sure we turn tcsetattr() calls of TCSAFLUSH and + * TCSADRAIN into something different. If an application would + * call TCSAFLUSH or TCSADRAIN on the master descriptor, it may + * deadlock waiting for all data to be read. + */ + cmd = TIOCSETA; + break; + case TIOCGPTN: + /* + * Get the device unit number. + */ + if (psc->pts_unit < 0) + return -ENOTTY; + *(unsigned int *)data = psc->pts_unit; + return (0); + case TIOCGPGRP: + /* Get the foreground process group ID. */ + tty_lock(tp); + if (tp->t_pgrp != NULL) + *(int *)data = tp->t_pgrp->pgid; + else + *(int *)data = NO_PID; + tty_unlock(tp); + return (0); + case TIOCGSID: + /* Get the session leader process ID. */ + tty_lock(tp); + if (tp->t_session == NULL) + error = -ENOTTY; + else + *(int *)data = tp->t_session->sid; + tty_unlock(tp); + return (error); +#ifdef USING_BSD_IOCTL_EXT + case TIOCPTMASTER: + /* Yes, we are a pseudo-terminal master. */ + return (0); +#endif /* USING_BSD_IOCTL_EXT */ + case TIOCSIG: + /* Signal the foreground process group. */ + sig = *(int *)data; + if (sig < 1 || sig >= _LWP_NSIG) + return -EINVAL; + + tty_lock(tp); + lwp_tty_signal_pgrp(tp, sig); + tty_unlock(tp); + return (0); + case TIOCPKT: + /* Enable/disable packet mode. */ + tty_lock(tp); + if (*(int *)data) + psc->pts_flags |= PTS_PKT; + else + psc->pts_flags &= ~PTS_PKT; + tty_unlock(tp); + return (0); + } + + /* Just redirect this ioctl to the slave device. */ + tty_lock(tp); + error = tty_ioctl(tp, cmd, data, fflags, td); + tty_unlock(tp); + if (error == -ENOIOCTL) + error = -ENOTTY; + + return error; +} + +static int ptsdev_poll(struct lwp_tty *tp, struct rt_pollreq *req, + struct ucred *active_cred, struct rt_thread *td) +{ + struct pts_softc *psc = tty_softc(tp); + int revents = 0; + int events = req->_key; + + tty_lock(tp); + + if (psc->pts_flags & PTS_FINISHED) + { + /* Slave device is not opened. */ + tty_unlock(tp); + return ((events & (POLLIN | POLLRDNORM)) | POLLHUP); + } + + if (events & (POLLIN | POLLRDNORM)) + { + /* See if we can getc something. */ + if (ttydisc_getc_poll(tp) || (psc->pts_flags & PTS_PKT && psc->pts_pkt)) + revents |= events & (POLLIN | POLLRDNORM); + } + if (events & (POLLOUT | POLLWRNORM)) + { + /* See if we can rint something. */ + if (ttydisc_rint_poll(tp)) + revents |= events & (POLLOUT | POLLWRNORM); + } + + /* + * No need to check for POLLHUP here. This device cannot be used + * as a callout device, which means we always have a carrier, + * because the master is. + */ + + if (revents == 0) + { + /* + * This code might look misleading, but the naming of + * poll events on this side is the opposite of the slave + * device. + */ + if (events & (POLLIN | POLLRDNORM)) + rt_poll_add(&psc->pts_outpoll, req); + if (events & (POLLOUT | POLLWRNORM)) + rt_poll_add(&psc->pts_inpoll, req); + } + + tty_unlock(tp); + + return (revents); +} + +#if USING_BSD_KQUEUE +/* + * kqueue support. + */ + +static void pts_kqops_read_detach(struct knote *kn) +{ + struct file *fp = kn->kn_fp; + struct lwp_tty *tp = fp->f_data; + struct pts_softc *psc = tty_softc(tp); + + knlist_remove(&psc->pts_outpoll.si_note, kn, 0); +} + +static int pts_kqops_read_event(struct knote *kn, long hint) +{ + struct file *fp = kn->kn_fp; + struct lwp_tty *tp = fp->f_data; + struct pts_softc *psc = tty_softc(tp); + + if (psc->pts_flags & PTS_FINISHED) + { + kn->kn_flags |= EV_EOF; + return (1); + } + else + { + kn->kn_data = ttydisc_getc_poll(tp); + return (kn->kn_data > 0); + } +} + +static void pts_kqops_write_detach(struct knote *kn) +{ + struct file *fp = kn->kn_fp; + struct lwp_tty *tp = fp->f_data; + struct pts_softc *psc = tty_softc(tp); + + knlist_remove(&psc->pts_inpoll.si_note, kn, 0); +} + +static int pts_kqops_write_event(struct knote *kn, long hint) +{ + struct file *fp = kn->kn_fp; + struct lwp_tty *tp = fp->f_data; + struct pts_softc *psc = tty_softc(tp); + + if (psc->pts_flags & PTS_FINISHED) + { + kn->kn_flags |= EV_EOF; + return (1); + } + else + { + kn->kn_data = ttydisc_rint_poll(tp); + return (kn->kn_data > 0); + } +} + +static struct filterops pts_kqops_read = { + .f_isfd = 1, + .f_detach = pts_kqops_read_detach, + .f_event = pts_kqops_read_event, +}; +static struct filterops pts_kqops_write = { + .f_isfd = 1, + .f_detach = pts_kqops_write_detach, + .f_event = pts_kqops_write_event, +}; + +static int ptsdev_kqfilter(struct file *fp, struct knote *kn) +{ + struct lwp_tty *tp = fp->f_data; + struct pts_softc *psc = tty_softc(tp); + int error = 0; + + tty_lock(tp); + + switch (kn->kn_filter) + { + case EVFILT_READ: + kn->kn_fop = &pts_kqops_read; + knlist_add(&psc->pts_outpoll.si_note, kn, 1); + break; + case EVFILT_WRITE: + kn->kn_fop = &pts_kqops_write; + knlist_add(&psc->pts_inpoll.si_note, kn, 1); + break; + default: + error = EINVAL; + break; + } + + tty_unlock(tp); + return (error); +} +#endif + +#if USING_BSD_STAT +static int ptsdev_stat(struct file *fp, struct stat *sb, + struct ucred *active_cred) +{ + struct lwp_tty *tp = fp->f_data; +#ifdef PTS_EXTERNAL + struct pts_softc *psc = tty_softc(tp); +#endif /* PTS_EXTERNAL */ + struct cdev *dev = tp->t_dev; + + /* + * According to POSIX, we must implement an fstat(). This also + * makes this implementation compatible with Linux binaries, + * because Linux calls fstat() on the pseudo-terminal master to + * obtain st_rdev. + * + * XXX: POSIX also mentions we must fill in st_dev, but how? + */ + + bzero(sb, sizeof *sb); +#ifdef PTS_EXTERNAL + if (psc->pts_cdev != NULL) + sb->st_ino = sb->st_rdev = dev2udev(psc->pts_cdev); + else +#endif /* PTS_EXTERNAL */ + sb->st_ino = sb->st_rdev = tty_udev(tp); + + sb->st_atim = dev->si_atime; + sb->st_ctim = dev->si_ctime; + sb->st_mtim = dev->si_mtime; + sb->st_uid = dev->si_uid; + sb->st_gid = dev->si_gid; + sb->st_mode = dev->si_mode | S_IFCHR; + + return (0); +} +#endif + +static int ptsdev_close(struct lwp_tty *tp, struct rt_thread *td) +{ + /* Deallocate TTY device. */ + tty_lock(tp); + tty_rel_gone(tp); + +#ifdef USING_BSD_VNODE + /* TODO: consider the vnode operation on DFS */ + + /* + * Open of /dev/ptmx or /dev/ptyXX changes the type of file + * from DTYPE_VNODE to DTYPE_PTS. vn_open() increases vnode + * use count, we need to decrement it, and possibly do other + * required cleanup. + */ + if (fp->f_vnode != NULL) + return (vnops.fo_close(fp, td)); +#endif /* USING_BSD_VNODE */ + + return 0; +} + +#ifdef USING_BSD_KINFO +static int ptsdev_fill_kinfo(struct file *fp, struct kinfo_file *kif, + struct filedesc *fdp) +{ + struct lwp_tty *tp; + + kif->kf_type = KF_TYPE_PTS; + tp = fp->f_data; + kif->kf_un.kf_pts.kf_pts_dev = tty_udev(tp); + kif->kf_un.kf_pts.kf_pts_dev_freebsd11 = + kif->kf_un.kf_pts.kf_pts_dev; /* truncate */ + strlcpy(kif->kf_path, tty_devname(tp), sizeof(kif->kf_path)); + return (0); +} +#endif + +struct bsd_fileops bsd_ptsdev_methods = { + .fo_read = ptsdev_read, + .fo_write = ptsdev_write, + // .fo_truncate = invfo_truncate, + .fo_ioctl = ptsdev_ioctl, + .fo_poll = ptsdev_poll, + // .fo_kqfilter = ptsdev_kqfilter, + // .fo_stat = ptsdev_stat, + .fo_close = ptsdev_close, + // .fo_chmod = invfo_chmod, + // .fo_chown = invfo_chown, + // .fo_sendfile = invfo_sendfile, + // .fo_fill_kinfo = ptsdev_fill_kinfo, + .fo_flags = DFLAG_PASSABLE, +}; + +/* + * Driver-side hooks. + */ + +static void ptsdrv_outwakeup(struct lwp_tty *tp) +{ + struct pts_softc *psc = tty_softc(tp); + + cv_broadcast(&psc->pts_outwait); + rt_wqueue_wakeup_all(&psc->pts_outpoll, (void *)POLLIN); +} + +static void ptsdrv_inwakeup(struct lwp_tty *tp) +{ + struct pts_softc *psc = tty_softc(tp); + + cv_broadcast(&psc->pts_inwait); + rt_wqueue_wakeup_all(&psc->pts_inpoll, (void *)POLLOUT); +} + +static int ptsdrv_open(struct lwp_tty *tp) +{ + struct pts_softc *psc = tty_softc(tp); + + /* for ioctl(TIOCSPTLCK) */ + if (psc->pts_flags & PTS_PTLOCKED) + return -EIO; + + psc->pts_flags &= ~PTS_FINISHED; + + return 0; +} + +static void ptsdrv_close(struct lwp_tty *tp) +{ + struct pts_softc *psc = tty_softc(tp); + + /* Wake up any blocked readers/writers. */ + psc->pts_flags |= PTS_FINISHED; + ptsdrv_outwakeup(tp); + ptsdrv_inwakeup(tp); +} + +static void ptsdrv_pktnotify(struct lwp_tty *tp, char event) +{ + struct pts_softc *psc = tty_softc(tp); + + /* + * Clear conflicting flags. + */ + + switch (event) + { + case TIOCPKT_STOP: + psc->pts_pkt &= ~TIOCPKT_START; + break; + case TIOCPKT_START: + psc->pts_pkt &= ~TIOCPKT_STOP; + break; + case TIOCPKT_NOSTOP: + psc->pts_pkt &= ~TIOCPKT_DOSTOP; + break; + case TIOCPKT_DOSTOP: + psc->pts_pkt &= ~TIOCPKT_NOSTOP; + break; + } + + psc->pts_pkt |= event; + + /** + * Note: on smart, we don't wakeup master until it's willing to accept + * packet event. Because on poll, we setup POLLIN for PTS_PKT only. So There + * is a chance when we wakeup ipc but we can't wakeup user again. Since + * current wakeup will remove the wakequeue node on the meanwhile + */ + if (psc->pts_flags & PTS_PKT) + ptsdrv_outwakeup(tp); +} + +static void ptsdrv_free(void *softc) +{ + struct pts_softc *psc = softc; + + /* Make device number available again. */ + if (psc->pts_unit >= 0) + ptyfs_unregister_pts(psc->pts_master, psc->pts_unit); + +#ifdef USING_BSD_UCRED + chgptscnt(psc->pts_cred->cr_ruidinfo, -1, 0); + racct_sub_cred(psc->pts_cred, RACCT_NPTS, 1); + crfree(psc->pts_cred); +#endif + + rt_wqueue_wakeup_all(&psc->pts_inpoll, (void *)POLLHUP); + rt_wqueue_wakeup_all(&psc->pts_outpoll, (void *)POLLHUP); + + rt_free(psc); +} + +static struct lwp_ttydevsw pts_class = { + .tsw_flags = TF_NOPREFIX, + .tsw_outwakeup = ptsdrv_outwakeup, + .tsw_inwakeup = ptsdrv_inwakeup, + .tsw_open = ptsdrv_open, + .tsw_close = ptsdrv_close, + .tsw_pktnotify = ptsdrv_pktnotify, + .tsw_free = ptsdrv_free, +}; + +int pts_alloc(int fflags, struct rt_thread *td, struct dfs_file *ptm_file) +{ + int unit; + struct lwp_tty *tp; + struct pts_softc *psc; + char name_buf[DIRENT_NAME_MAX]; + const char *rootpath; + rt_device_t ptmx_device = ptm_file->vnode->data; + +#ifdef USING_BSD_UCRED + struct rt_lwp *p = td->lwp; + int ok, error; + struct ucred *cred = td->td_ucred; +#endif + + /* Resource limiting. */ +#ifdef USING_BSD_UCRED + LWP_LOCK(p); + error = racct_add(p, RACCT_NPTS, 1); + if (error != 0) + { + LWP_UNLOCK(p); + return -EAGAIN; + } + ok = chgptscnt(cred->cr_ruidinfo, 1, lim_cur(td, RLIMIT_NPTS)); + if (!ok) + { + racct_sub(p, RACCT_NPTS, 1); + LWP_UNLOCK(p); + return -EAGAIN; + } + LWP_UNLOCK(p); +#endif + + /* Allocate TTY and softc. */ + psc = rt_calloc(1, sizeof(struct pts_softc)); + cv_init(&psc->pts_inwait, "ptsin"); + cv_init(&psc->pts_outwait, "ptsout"); + rt_wqueue_init(&psc->pts_inpoll); + rt_wqueue_init(&psc->pts_outpoll); + + psc->pts_master = ptmx_device; +#ifdef USING_BSD_UCRED + psc->pts_cred = crhold(cred); +#else + psc->pts_cred = 0; +#endif + + tp = lwp_tty_create(&pts_class, psc); + if (!tp) + { + rt_free(psc); + rt_condvar_detach(&psc->pts_inwait); + rt_condvar_detach(&psc->pts_outwait); + return -ENOMEM; + } + + /* Try to allocate a new pts uint*/ + unit = ptyfs_register_pts(ptmx_device, &tp->parent); + if (unit < 0) + { +#ifdef USING_BSD_UCRED + racct_sub(p, RACCT_NPTS, 1); + chgptscnt(cred->cr_ruidinfo, -1, 0); +#endif + lwp_tty_delete(tp); + return -EAGAIN; + } + psc->pts_unit = unit; + + /* Expose the slave device as well. */ +#ifdef USING_BSD_UCRED + tty_makedev(tp, td->td_ucred, "pts/%u", psc->pts_unit); +#else + rootpath = ptyfs_get_rootpath(ptmx_device); + RT_ASSERT(rootpath[strlen(rootpath) - 1] != '/'); + snprintf(name_buf, DIRENT_NAME_MAX, "%s/%d", rootpath, psc->pts_unit); + + /* setup the pts */ + lwp_tty_register(tp, name_buf); + + /* now this file operating on new pty */ + ptm_file->data = tp; +#endif + + return 0; +} + +void pts_set_lock(lwp_tty_t pts, rt_bool_t is_lock) +{ + struct pts_softc *psc = tty_softc(pts); + if (is_lock) + psc->pts_flags |= PTS_PTLOCKED; + else + psc->pts_flags &= ~PTS_PTLOCKED; +} + +rt_bool_t pts_is_locked(lwp_tty_t pts) +{ + struct pts_softc *psc = tty_softc(pts); + return !!(psc->pts_flags & PTS_PTLOCKED); +} + +int pts_get_pktmode(lwp_tty_t pts) +{ + struct pts_softc *psc = tty_softc(pts); + return !!(psc->pts_flags & PTS_PKT); +} diff --git a/components/lwp/terminal/freebsd/tty_ttydisc.c b/components/lwp/terminal/freebsd/tty_ttydisc.c new file mode 100644 index 00000000000..932ef2ec00d --- /dev/null +++ b/components/lwp/terminal/freebsd/tty_ttydisc.c @@ -0,0 +1,1479 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-13 Shell init ver. + */ +#include "../bsd_porting.h" +#include "../tty_config.h" +#include "../tty_internal.h" +#include "../terminal.h" + +#include + +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2008 Ed Schouten + * All rights reserved. + * + * Portions of this software were developed under sponsorship from Snow + * B.V., the Netherlands. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Standard TTYDISC `termios' line discipline. + */ + +/* Statistics. */ +static rt_atomic_t tty_nin = 0; +#ifdef USING_BSD_SYSCTL +SYSCTL_ULONG(_kern, OID_AUTO, tty_nin, CTLFLAG_RD, &tty_nin, 0, + "Total amount of bytes received"); +#endif + +static rt_atomic_t tty_nout = 0; +#ifdef USING_BSD_SYSCTL +SYSCTL_ULONG(_kern, OID_AUTO, tty_nout, CTLFLAG_RD, &tty_nout, 0, + "Total amount of bytes transmitted"); +#endif + +/* termios comparison macro's. */ +#define CMP_CC(v, c) \ + (tp->t_termios.c_cc[v] != _POSIX_VDISABLE && tp->t_termios.c_cc[v] == (c)) +#define CMP_FLAG(field, opt) (tp->t_termios.c_##field##flag & (opt)) + +/* Characters that cannot be modified through c_cc. */ +#define CTAB '\t' +#define CNL '\n' +#define CCR '\r' + +/* Character is a control character. */ +#define CTL_VALID(c) ((c) == 0x7f || (unsigned char)(c) < 0x20) +/* Control character should be processed on echo. */ +#define CTL_ECHO(c, q) \ + (!(q) && ((c) == CERASE2 || (c) == CTAB || (c) == CNL || (c) == CCR)) +/* Control character should be printed using ^X notation. */ +#define CTL_PRINT(c, q) \ + ((c) == 0x7f || \ + ((unsigned char)(c) < 0x20 && ((q) || ((c) != CTAB && (c) != CNL)))) +/* Character is whitespace. */ +#define CTL_WHITE(c) ((c) == ' ' || (c) == CTAB) +/* Character is alphanumeric. */ +#define CTL_ALNUM(c) \ + (((c) >= '0' && (c) <= '9') || ((c) >= 'a' && (c) <= 'z') || \ + ((c) >= 'A' && (c) <= 'Z')) +/* Character is UTF8-encoded. */ +#define CTL_UTF8(c) (!!((c)&0x80)) +/* Character is a UTF8 continuation byte. */ +#define CTL_UTF8_CONT(c) (((c)&0xc0) == 0x80) + +#define TTY_STACKBUF 256 +#define UTF8_STACKBUF 4 + +void ttydisc_open(struct lwp_tty *tp) +{ + ttydisc_optimize(tp); +} + +void ttydisc_close(struct lwp_tty *tp) +{ + /* Clean up our flags when leaving the discipline. */ + tp->t_flags &= ~(TF_STOPPED | TF_HIWAT | TF_ZOMBIE); + tp->t_termios.c_lflag &= ~FLUSHO; + + /* + * POSIX states that we must drain output and flush input on + * last close. Draining has already been done if possible. + */ + tty_flush(tp, FREAD | FWRITE); + +#ifdef USING_BSD_HOOK + if (ttyhook_hashook(tp, close)) + ttyhook_close(tp); +#endif +} + +static int ttydisc_read_canonical(struct lwp_tty *tp, struct uio *uio, + int ioflag) +{ + char breakc[4] = {CNL}; /* enough to hold \n, VEOF and VEOL. */ + int error; + size_t clen, flen = 0, n = 1; + unsigned char lastc = _POSIX_VDISABLE; + +#define BREAK_ADD(c) \ + do \ + { \ + if (tp->t_termios.c_cc[c] != _POSIX_VDISABLE) \ + breakc[n++] = tp->t_termios.c_cc[c]; \ + } while (0) + /* Determine which characters we should trigger on. */ + BREAK_ADD(VEOF); + BREAK_ADD(VEOL); +#undef BREAK_ADD + breakc[n] = '\0'; + + do + { + error = tty_wait_background(tp, curthread, SIGTTIN); + if (error) + return error; + + /* + * Quite a tricky case: unlike the old TTY + * implementation, this implementation copies data back + * to userspace in large chunks. Unfortunately, we can't + * calculate the line length on beforehand if it crosses + * ttyinq_block boundaries, because multiple reads could + * then make this code read beyond the newline. + * + * This is why we limit the read to: + * - The size the user has requested + * - The blocksize (done in tty_inq.c) + * - The amount of bytes until the newline + * + * This causes the line length to be recalculated after + * each block has been copied to userspace. This will + * cause the TTY layer to return data in chunks using + * the blocksize (except the first and last blocks). + */ + clen = + ttyinq_findchar(&tp->t_inq, breakc, uio->uio_resid, (char *)&lastc); + + /* No more data. */ + if (clen == 0) + { + if (tp->t_flags & TF_ZOMBIE) + return 0; + else if (ioflag & IO_NDELAY) + return -EWOULDBLOCK; + + error = tty_wait(tp, &tp->t_inwait); + if (error) + return error; + continue; + } + + /* Don't send the EOF char back to userspace. */ + if (CMP_CC(VEOF, lastc)) + flen = 1; + + MPASS(flen <= clen); + + /* Read and throw away the EOF character. */ + error = ttyinq_read_uio(&tp->t_inq, tp, uio, clen, flen); + if (error) + return error; + + /** Notes: proceed when read buf frees and not reaching breaks */ + } while (uio->uio_resid > 0 && lastc == _POSIX_VDISABLE); + + return 0; +} + +static int ttydisc_read_raw_no_timer(struct lwp_tty *tp, struct uio *uio, + int ioflag) +{ + size_t vmin = tp->t_termios.c_cc[VMIN]; + ssize_t oresid = uio->uio_resid; + int error; + + MPASS(tp->t_termios.c_cc[VTIME] == 0); + + /* + * This routine implements the easy cases of read()s while in + * non-canonical mode, namely case B and D, where we don't have + * any timers at all. + */ + + for (;;) + { + error = tty_wait_background(tp, curthread, SIGTTIN); + if (error) + return error; + + error = ttyinq_read_uio(&tp->t_inq, tp, uio, uio->uio_resid, 0); + if (error) + return error; + if (uio->uio_resid == 0 || (oresid - uio->uio_resid) >= vmin) + return 0; + + /* We have to wait for more. */ + if (tp->t_flags & TF_ZOMBIE) + return 0; + else if (ioflag & IO_NDELAY) + return -EWOULDBLOCK; + + error = tty_wait(tp, &tp->t_inwait); + if (error) + return error; + } +} + +static int ttydisc_read_raw_read_timer(struct lwp_tty *tp, struct uio *uio, + int ioflag, int oresid) +{ + size_t vmin = MAX(tp->t_termios.c_cc[VMIN], 1); + unsigned int vtime = tp->t_termios.c_cc[VTIME]; + struct timeval end, now, left; + int error, hz; + + MPASS(tp->t_termios.c_cc[VTIME] != 0); + + /* Determine when the read should be expired. */ + end.tv_sec = vtime / 10; + end.tv_usec = (vtime % 10) * 100000; + getmicrotime(&now); + timevaladd(&end, &now); + + for (;;) + { + error = tty_wait_background(tp, curthread, SIGTTIN); + if (error) + return error; + + error = ttyinq_read_uio(&tp->t_inq, tp, uio, uio->uio_resid, 0); + if (error) + return error; + if (uio->uio_resid == 0 || (oresid - uio->uio_resid) >= vmin) + return 0; + + /* Calculate how long we should wait. */ + getmicrotime(&now); + if (timevalcmp(&now, &end, >)) + return 0; + left = end; + timevalsub(&left, &now); + hz = tvtohz(&left); + + /* + * We have to wait for more. If the timer expires, we + * should return a 0-byte read. + */ + if (tp->t_flags & TF_ZOMBIE) + return 0; + else if (ioflag & IO_NDELAY) + return -EWOULDBLOCK; + + error = tty_timedwait(tp, &tp->t_inwait, hz); + if (error) + return (error == -EWOULDBLOCK ? 0 : error); + } + + return 0; +} + +static int ttydisc_read_raw_interbyte_timer(struct lwp_tty *tp, struct uio *uio, + int ioflag) +{ + size_t vmin = tp->t_termios.c_cc[VMIN]; + ssize_t oresid = uio->uio_resid; + int error; + + MPASS(tp->t_termios.c_cc[VMIN] != 0); + MPASS(tp->t_termios.c_cc[VTIME] != 0); + + /* + * When using the interbyte timer, the timer should be started + * after the first byte has been received. We just call into the + * generic read timer code after we've received the first byte. + */ + + for (;;) + { + error = tty_wait_background(tp, curthread, SIGTTIN); + if (error) + return error; + + error = ttyinq_read_uio(&tp->t_inq, tp, uio, uio->uio_resid, 0); + if (error) + return error; + if (uio->uio_resid == 0 || (oresid - uio->uio_resid) >= vmin) + return 0; + + /* + * Not enough data, but we did receive some, which means + * we'll now start using the interbyte timer. + */ + if (oresid != uio->uio_resid) + break; + + /* We have to wait for more. */ + if (tp->t_flags & TF_ZOMBIE) + return 0; + else if (ioflag & IO_NDELAY) + return -EWOULDBLOCK; + + error = tty_wait(tp, &tp->t_inwait); + if (error) + return error; + } + + return ttydisc_read_raw_read_timer(tp, uio, ioflag, oresid); +} + +int ttydisc_read(struct lwp_tty *tp, struct uio *uio, int ioflag) +{ + int error; + + tty_assert_locked(tp); + + if (uio->uio_resid == 0) + return 0; + + if (CMP_FLAG(l, ICANON)) + error = ttydisc_read_canonical(tp, uio, ioflag); + else if (tp->t_termios.c_cc[VTIME] == 0) + error = ttydisc_read_raw_no_timer(tp, uio, ioflag); + else if (tp->t_termios.c_cc[VMIN] == 0) + error = ttydisc_read_raw_read_timer(tp, uio, ioflag, uio->uio_resid); + else + error = ttydisc_read_raw_interbyte_timer(tp, uio, ioflag); + + if (ttyinq_bytesleft(&tp->t_inq) >= tp->t_inlow || + ttyinq_bytescanonicalized(&tp->t_inq) == 0) + { + /* Unset the input watermark when we've got enough space. */ + tty_hiwat_in_unblock(tp); + } + + return error; +} + +/* return the offset to special character from string start */ +rt_inline unsigned int ttydisc_findchar(const char *obstart, unsigned int oblen) +{ + const char *c = obstart; + + while (oblen--) + { + if (CTL_VALID(*c)) + break; + c++; + } + + return (c - obstart); +} + +static int ttydisc_write_oproc(struct lwp_tty *tp, char c) +{ + unsigned int scnt, error; + + MPASS(CMP_FLAG(o, OPOST)); + MPASS(CTL_VALID(c)); + +#define PRINT_NORMAL() ttyoutq_write_nofrag(&tp->t_outq, &c, 1) + switch (c) + { + case CEOF: + /* End-of-text dropping. */ + if (CMP_FLAG(o, ONOEOT)) + return 0; + return PRINT_NORMAL(); + + case CERASE2: + /* Handle backspace to fix tab expansion. */ + if (PRINT_NORMAL() != 0) + return (-1); + if (tp->t_column > 0) + tp->t_column--; + return 0; + + case CTAB: + /* Tab expansion. */ + scnt = 8 - (tp->t_column & 7); + if (CMP_FLAG(o, TAB3)) + { + error = ttyoutq_write_nofrag(&tp->t_outq, " ", scnt); + } + else + { + error = PRINT_NORMAL(); + } + if (error) + return (-1); + + tp->t_column += scnt; + MPASS((tp->t_column % 8) == 0); + return 0; + + case CNL: + /* Newline conversion. */ + if (CMP_FLAG(o, ONLCR)) + { + /* Convert \n to \r\n. */ + error = ttyoutq_write_nofrag(&tp->t_outq, "\r\n", 2); + } + else + { + error = PRINT_NORMAL(); + } + if (error) + return (-1); + + if (CMP_FLAG(o, ONLCR | ONLRET)) + { + tp->t_column = tp->t_writepos = 0; + ttyinq_reprintpos_set(&tp->t_inq); + } + return 0; + + case CCR: + /* Carriage return to newline conversion. */ + if (CMP_FLAG(o, OCRNL)) + c = CNL; + /* Omit carriage returns on column 0. */ + if (CMP_FLAG(o, ONOCR) && tp->t_column == 0) + return 0; + if (PRINT_NORMAL() != 0) + return (-1); + + tp->t_column = tp->t_writepos = 0; + ttyinq_reprintpos_set(&tp->t_inq); + return 0; + } + + /* + * Invisible control character. Print it, but don't + * increase the column count. + */ + return PRINT_NORMAL(); +#undef PRINT_NORMAL +} + +/* + * Just like the old TTY implementation, we need to copy data in chunks + * into a temporary buffer. One of the reasons why we need to do this, + * is because output processing (only TAB3 though) may allow the buffer + * to grow eight times. + */ +int ttydisc_write(struct lwp_tty *tp, struct uio *uio, int ioflag) +{ + char ob[TTY_STACKBUF]; + char *obstart; + int error = 0; + unsigned int oblen = 0; + + tty_assert_locked(tp); + + if (tp->t_flags & TF_ZOMBIE) + return -EIO; + + /* + * We don't need to check whether the process is the foreground + * process group or if we have a carrier. This is already done + * in ttydev_write(). + */ + + while (uio->uio_resid > 0) + { + unsigned int nlen; + + MPASS(oblen == 0); + + if (CMP_FLAG(l, FLUSHO)) + { + uio->uio_offset += uio->uio_resid; + uio->uio_resid = 0; + return 0; + } + + /* Step 1: read data. */ + obstart = ob; + nlen = MIN(uio->uio_resid, sizeof ob); + tty_unlock(tp); + error = uiomove(ob, nlen, uio); + tty_lock(tp); + if (error != 0) + break; + oblen = nlen; + + if (tty_gone(tp)) + { + error = -ENXIO; + break; + } + + MPASS(oblen > 0); + + /* Step 2: process data. */ + do + { + unsigned int plen, wlen; + + if (CMP_FLAG(l, FLUSHO)) + { + uio->uio_offset += uio->uio_resid; + uio->uio_resid = 0; + return 0; + } + + /* Search for special characters for post processing. */ + if (CMP_FLAG(o, OPOST)) + { + plen = ttydisc_findchar(obstart, oblen); + } + else + { + plen = oblen; + } + + if (plen == 0) + { + /* + * We're going to process a character + * that needs processing + */ + if (ttydisc_write_oproc(tp, *obstart) == 0) + { + obstart++; + oblen--; + + tp->t_writepos = tp->t_column; + ttyinq_reprintpos_set(&tp->t_inq); + continue; + } + } + else + { + /* We're going to write regular data. */ + wlen = ttyoutq_write(&tp->t_outq, obstart, plen); + obstart += wlen; + oblen -= wlen; + tp->t_column += wlen; + + tp->t_writepos = tp->t_column; + ttyinq_reprintpos_set(&tp->t_inq); + + if (wlen == plen) + continue; + } + + /* Watermark reached. Try to sleep. */ + tp->t_flags |= TF_HIWAT_OUT; + + if (ioflag & IO_NDELAY) + { + error = EWOULDBLOCK; + goto done; + } + + /* + * The driver may write back the data + * synchronously. Be sure to check the high + * water mark before going to sleep. + */ + ttydevsw_outwakeup(tp); + if ((tp->t_flags & TF_HIWAT_OUT) == 0) + continue; + + error = tty_wait(tp, &tp->t_outwait); + if (error) + goto done; + + if (tp->t_flags & TF_ZOMBIE) + { + error = EIO; + goto done; + } + } while (oblen > 0); + } + +done: + if (!tty_gone(tp)) + ttydevsw_outwakeup(tp); + + /* + * Add the amount of bytes that we didn't process back to the + * uio counters. We need to do this to make sure write() doesn't + * count the bytes we didn't store in the queue. + */ + uio->uio_resid += oblen; + return error; +} + +/* set optimize flags if possible */ +void ttydisc_optimize(struct lwp_tty *tp) +{ + tty_assert_locked(tp); + + if (ttyhook_hashook(tp, rint_bypass)) + { + tp->t_flags |= TF_BYPASS; + } + else if (ttyhook_hashook(tp, rint)) + { + tp->t_flags &= ~TF_BYPASS; + } + else if (!CMP_FLAG(i, ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON) && + (!CMP_FLAG(i, BRKINT) || CMP_FLAG(i, IGNBRK)) && + (!CMP_FLAG(i, PARMRK) || + CMP_FLAG(i, IGNPAR | IGNBRK) == (IGNPAR | IGNBRK)) && + !CMP_FLAG(l, ECHO | ICANON | IEXTEN | ISIG | PENDIN)) + { + tp->t_flags |= TF_BYPASS; + } + else + { + tp->t_flags &= ~TF_BYPASS; + } +} + +void ttydisc_modem(struct lwp_tty *tp, int open) +{ + tty_assert_locked(tp); + + if (open) + cv_broadcast(&tp->t_dcdwait); + + /* + * Ignore modem status lines when CLOCAL is turned on, but don't + * enter the zombie state when the TTY isn't opened, because + * that would cause the TTY to be in zombie state after being + * opened. + */ + if (!tty_opened(tp) || CMP_FLAG(c, CLOCAL)) + return; + + if (open == 0) + { + /* + * Lost carrier. + */ + tp->t_flags |= TF_ZOMBIE; + + lwp_tty_signal_sessleader(tp, SIGHUP); + tty_flush(tp, FREAD | FWRITE); + } + else + { + /* + * Carrier is back again. + */ + + /* XXX: what should we do here? */ + } +} + +static int ttydisc_echo_force(struct lwp_tty *tp, char c, int quote) +{ + if (CMP_FLAG(l, FLUSHO)) + return 0; + + if (CMP_FLAG(o, OPOST) && CTL_ECHO(c, quote)) + { + /* + * Only perform postprocessing when OPOST is turned on + * and the character is an unquoted BS/TB/NL/CR. + */ + return ttydisc_write_oproc(tp, c); + } + else if (CMP_FLAG(l, ECHOCTL) && CTL_PRINT(c, quote)) + { + /* + * Only use ^X notation when ECHOCTL is turned on and + * we've got an quoted control character. + * + * Print backspaces when echoing an end-of-file. + */ + char ob[4] = "^?\b\b"; + + /* Print ^X notation. */ + if (c != 0x7f) + ob[1] = c + 'A' - 1; + + if (!quote && CMP_CC(VEOF, c)) + { + return ttyoutq_write_nofrag(&tp->t_outq, ob, 4); + } + else + { + tp->t_column += 2; + return ttyoutq_write_nofrag(&tp->t_outq, ob, 2); + } + } + else + { + /* Can just be printed. */ + tp->t_column++; + return ttyoutq_write_nofrag(&tp->t_outq, &c, 1); + } +} + +static int ttydisc_echo(struct lwp_tty *tp, char c, int quote) +{ + /* + * Only echo characters when ECHO is turned on, or ECHONL when + * the character is an unquoted newline. + */ + if (!CMP_FLAG(l, ECHO) && (!CMP_FLAG(l, ECHONL) || c != CNL || quote)) + return 0; + + return ttydisc_echo_force(tp, c, quote); +} + +static void ttydisc_reprint_char(void *d, char c, int quote) +{ + struct lwp_tty *tp = d; + + ttydisc_echo(tp, c, quote); +} + +static void ttydisc_reprint(struct lwp_tty *tp) +{ + cc_t c; + + /* Print ^R\n, followed by the line. */ + c = tp->t_termios.c_cc[VREPRINT]; + if (c != _POSIX_VDISABLE) + ttydisc_echo(tp, c, 0); + ttydisc_echo(tp, CNL, 0); + ttyinq_reprintpos_reset(&tp->t_inq); + + ttyinq_line_iterate_from_linestart(&tp->t_inq, ttydisc_reprint_char, tp); +} + +struct ttydisc_recalc_length +{ + struct lwp_tty *tp; + unsigned int curlen; +}; + +static void ttydisc_recalc_charlength(void *d, char c, int quote) +{ + struct ttydisc_recalc_length *data = d; + struct lwp_tty *tp = data->tp; + + if (CTL_PRINT(c, quote)) + { + if (CMP_FLAG(l, ECHOCTL)) + data->curlen += 2; + } + else if (c == CTAB) + { + data->curlen += 8 - (data->curlen & 7); + } + else + { + data->curlen++; + } +} + +static unsigned int ttydisc_recalc_linelength(struct lwp_tty *tp) +{ + struct ttydisc_recalc_length data = {tp, tp->t_writepos}; + + ttyinq_line_iterate_from_reprintpos(&tp->t_inq, ttydisc_recalc_charlength, + &data); + return (data.curlen); +} + +static int ttydisc_rubchar(struct lwp_tty *tp) +{ + char c; + int quote; + unsigned int prevpos, tablen; + + if (ttyinq_peekchar(&tp->t_inq, &c, "e) != 0) + return (-1); + ttyinq_unputchar(&tp->t_inq); + + if (CMP_FLAG(l, ECHO)) + { + /* + * Remove the character from the screen. This is even + * safe for characters that span multiple characters + * (tabs, quoted, etc). + */ + if (tp->t_writepos >= tp->t_column) + { + /* Retype the sentence. */ + ttydisc_reprint(tp); + } + else if (CMP_FLAG(l, ECHOE)) + { + if (CTL_PRINT(c, quote)) + { + /* Remove ^X formatted chars. */ + if (CMP_FLAG(l, ECHOCTL)) + { + tp->t_column -= 2; + ttyoutq_write_nofrag(&tp->t_outq, "\b\b \b\b", 6); + } + } + else if (c == ' ') + { + /* Space character needs no rubbing. */ + tp->t_column -= 1; + ttyoutq_write_nofrag(&tp->t_outq, "\b", 1); + } + else if (c == CTAB) + { + /* + * Making backspace work with tabs is + * quite hard. Recalculate the length of + * this character and remove it. + * + * Because terminal settings could be + * changed while the line is being + * inserted, the calculations don't have + * to be correct. Make sure we keep the + * tab length within proper bounds. + */ + prevpos = ttydisc_recalc_linelength(tp); + if (prevpos >= tp->t_column) + tablen = 1; + else + tablen = tp->t_column - prevpos; + if (tablen > 8) + tablen = 8; + + tp->t_column = prevpos; + ttyoutq_write_nofrag(&tp->t_outq, "\b\b\b\b\b\b\b\b", tablen); + return 0; + } +#ifdef USING_BSD_UTF8 + else if ((tp->t_termios.c_iflag & IUTF8) != 0 && CTL_UTF8(c)) + { + uint8_t bytes[UTF8_STACKBUF] = {0}; + int curidx = UTF8_STACKBUF - 1, cwidth = 1, nb = 0; + teken_char_t codepoint; + + /* Save current byte. */ + bytes[curidx] = c; + curidx--; + nb++; + /* Loop back through inq until we hit the + * leading byte. */ + while (CTL_UTF8_CONT(c) && nb < UTF8_STACKBUF) + { + /* + * Check if we've reached the beginning + * of the line. + */ + if (ttyinq_peekchar(&tp->t_inq, &c, "e) != 0) + break; + ttyinq_unputchar(&tp->t_inq); + bytes[curidx] = c; + curidx--; + nb++; + } + /* + * Shift array so that the leading + * byte ends up at idx 0. + */ + if (nb < UTF8_STACKBUF) + memmove(&bytes[0], &bytes[curidx + 1], + nb * sizeof(uint8_t)); + /* Check for malformed UTF8 characters. */ + if (nb == UTF8_STACKBUF && CTL_UTF8_CONT(bytes[0])) + { + /* + * Place all bytes back into the inq and + * delete the last byte only. + */ + ttyinq_write(&tp->t_inq, bytes, UTF8_STACKBUF, 0); + ttyinq_unputchar(&tp->t_inq); + } + else + { + /* Find codepoint and width. */ + codepoint = teken_utf8_bytes_to_codepoint(bytes, nb); + if (codepoint == TEKEN_UTF8_INVALID_CODEPOINT || + (cwidth = teken_wcwidth(codepoint)) == -1) + { + /* + * Place all bytes back into the + * inq and fall back to + * default behaviour. + */ + cwidth = 1; + ttyinq_write(&tp->t_inq, bytes, nb, 0); + ttyinq_unputchar(&tp->t_inq); + } + } + tp->t_column -= cwidth; + /* + * Delete character by punching + * 'cwidth' spaces over it. + */ + if (cwidth == 1) + ttyoutq_write_nofrag(&tp->t_outq, "\b \b", 3); + else if (cwidth == 2) + ttyoutq_write_nofrag(&tp->t_outq, "\b\b \b\b", 6); + } +#endif + else + { + /* + * Remove a regular character by + * punching a space over it. + */ + tp->t_column -= 1; + ttyoutq_write_nofrag(&tp->t_outq, "\b \b", 3); + } + } + else + { + /* Don't print spaces. */ + ttydisc_echo(tp, tp->t_termios.c_cc[VERASE], 0); + } + } + + return 0; +} + +static void ttydisc_rubword(struct lwp_tty *tp) +{ + char c; + int quote; +#ifdef ALTWERASE + int alnum; +#endif + + /* Strip whitespace first. */ + for (;;) + { + if (ttyinq_peekchar(&tp->t_inq, &c, "e) != 0) + return; + if (!CTL_WHITE(c)) + break; + ttydisc_rubchar(tp); + } + + /* + * Record whether the last character from the previous iteration + * was alphanumeric or not. We need this to implement ALTWERASE. + */ +#ifdef ALTWERASE + alnum = CTL_ALNUM(c); +#endif + for (;;) + { + ttydisc_rubchar(tp); + + if (ttyinq_peekchar(&tp->t_inq, &c, "e) != 0) + return; + if (CTL_WHITE(c)) + return; +#ifdef ALTWERASE + if (CMP_FLAG(l, ALTWERASE) && CTL_ALNUM(c) != alnum) + return; +#endif + } +} + +int ttydisc_rint(struct lwp_tty *tp, char c, int flags) +{ + int signal, quote = 0; + char ob[3] = {0xff, 0x00}; + size_t ol; + + tty_assert_locked(tp); + + rt_atomic_add(&tty_nin, 1); + +#ifdef USING_BSD_HOOK + if (ttyhook_hashook(tp, rint)) + return ttyhook_rint(tp, c, flags); +#endif + + if (tp->t_flags & TF_BYPASS) + goto processed; + + if (flags) + { + if (flags & TRE_BREAK) + { + if (CMP_FLAG(i, IGNBRK)) + { + /* Ignore break characters. */ + return 0; + } + else if (CMP_FLAG(i, BRKINT)) + { + /* Generate SIGINT on break. */ + tty_flush(tp, FREAD | FWRITE); + lwp_tty_signal_pgrp(tp, SIGINT); + return 0; + } + else + { + /* Just print it. */ + goto parmrk; + } + } + else if (flags & TRE_FRAMING || + (flags & TRE_PARITY && CMP_FLAG(i, INPCK))) + { + if (CMP_FLAG(i, IGNPAR)) + { + /* Ignore bad characters. */ + return 0; + } + else + { + /* Just print it. */ + goto parmrk; + } + } + } + + /* Allow any character to perform a wakeup. */ + if (CMP_FLAG(i, IXANY)) + { + tp->t_flags &= ~TF_STOPPED; + tp->t_termios.c_lflag &= ~FLUSHO; /* FLUSHO: Output is being flushed */ + } + + /* Remove the top bit. */ + if (CMP_FLAG(i, ISTRIP)) + c &= ~0x80; + + /* Skip input processing when we want to print it literally. */ + if (tp->t_flags & TF_LITERAL) + { + tp->t_flags &= ~TF_LITERAL; + quote = 1; + goto processed; + } + + /* Special control characters that are implementation dependent. */ + if (CMP_FLAG(l, IEXTEN)) + { + /* Accept the next character as literal. */ + if (CMP_CC(VLNEXT, c)) + { + if (CMP_FLAG(l, ECHO)) + { + if (CMP_FLAG(l, ECHOE)) + ttyoutq_write_nofrag(&tp->t_outq, "^\b", 2); + else + ttydisc_echo(tp, c, 0); + } + tp->t_flags |= TF_LITERAL; + return 0; + } + /* Discard processing */ + if (CMP_CC(VDISCARD, c)) + { + if (CMP_FLAG(l, FLUSHO)) + { + tp->t_termios.c_lflag &= ~FLUSHO; + } + else + { + tty_flush(tp, FWRITE); + ttydisc_echo(tp, c, 0); + if (tp->t_inq.ti_end > 0) + ttydisc_reprint(tp); + tp->t_termios.c_lflag |= FLUSHO; + } + } + } + + /* + * Handle signal processing. + */ + if (CMP_FLAG(l, ISIG)) + { +#ifdef USING_BSD_SIGINFO + if (CMP_FLAG(l, ICANON | IEXTEN) == (ICANON | IEXTEN)) + { + if (CMP_CC(VSTATUS, c)) + { + tty_signal_pgrp(tp, SIGINFO); + return 0; + } + } +#endif /* USING_BSD_SIGINFO */ + + /* + * When compared to the old implementation, this + * implementation also flushes the output queue. POSIX + * is really brief about this, but does makes us assume + * we have to do so. + */ + signal = 0; + if (CMP_CC(VINTR, c)) + { + signal = SIGINT; + } + else if (CMP_CC(VQUIT, c)) + { + signal = SIGQUIT; + } + else if (CMP_CC(VSUSP, c)) + { + signal = SIGTSTP; + } + + if (signal != 0) + { + /* + * Echo the character before signalling the + * processes. + */ + if (!CMP_FLAG(l, NOFLSH)) + tty_flush(tp, FREAD | FWRITE); + ttydisc_echo(tp, c, 0); + lwp_tty_signal_pgrp(tp, signal); + return 0; + } + } + + /* + * Handle start/stop characters. + */ + if (CMP_FLAG(i, IXON)) + { + if (CMP_CC(VSTOP, c)) + { + /* Stop it if we aren't stopped yet. */ + if ((tp->t_flags & TF_STOPPED) == 0) + { + tp->t_flags |= TF_STOPPED; + return 0; + } + /* + * Fallthrough: + * When VSTART == VSTOP, we should make this key + * toggle it. + */ + if (!CMP_CC(VSTART, c)) + return 0; + } + if (CMP_CC(VSTART, c)) + { + tp->t_flags &= ~TF_STOPPED; + return 0; + } + } + + /* Conversion of CR and NL. */ + switch (c) + { + case CCR: + if (CMP_FLAG(i, IGNCR)) + return 0; + if (CMP_FLAG(i, ICRNL)) + c = CNL; + break; + case CNL: + if (CMP_FLAG(i, INLCR)) + c = CCR; + break; + } + + /* Canonical line editing. */ + if (CMP_FLAG(l, ICANON)) + { + if (CMP_CC(VERASE, c) +#ifdef VERASE2 + || CMP_CC(VERASE2, c) +#endif + ) + { + ttydisc_rubchar(tp); + return 0; + } + else if (CMP_CC(VKILL, c)) + { + while (ttydisc_rubchar(tp) == 0) + ; + return 0; + } + else if (CMP_FLAG(l, IEXTEN)) + { + if (CMP_CC(VWERASE, c)) + { + ttydisc_rubword(tp); + return 0; + } + else if (CMP_CC(VREPRINT, c)) + { + ttydisc_reprint(tp); + return 0; + } + } + } + +processed: + if (CMP_FLAG(i, PARMRK) && (unsigned char)c == 0xff) + { + /* Print 0xff 0xff. */ + ob[1] = 0xff; + ol = 2; + quote = 1; + } + else + { + ob[0] = c; + ol = 1; + } + + goto print; + +parmrk: + if (CMP_FLAG(i, PARMRK)) + { + /* Prepend 0xff 0x00 0x.. */ + ob[2] = c; + ol = 3; + quote = 1; + } + else + { + ob[0] = c; + ol = 1; + } + +print: + /* See if we can store this on the input queue. */ + if (ttyinq_write_nofrag(&tp->t_inq, ob, ol, quote) != 0) + { + if (CMP_FLAG(i, IMAXBEL)) + ttyoutq_write_nofrag(&tp->t_outq, "\a", 1); + + /* + * Prevent a deadlock here. It may be possible that a + * user has entered so much data, there is no data + * available to read(), but the buffers are full anyway. + * + * Only enter the high watermark if the device driver + * can actually transmit something. + */ + if (ttyinq_bytescanonicalized(&tp->t_inq) == 0) + return 0; + + tty_hiwat_in_block(tp); + return (-1); + } + + /* + * In raw mode, we canonicalize after receiving a single + * character. Otherwise, we canonicalize when we receive a + * newline, VEOL or VEOF, but only when it isn't quoted. + */ + if (!CMP_FLAG(l, ICANON) || + (!quote && (c == CNL || CMP_CC(VEOL, c) || CMP_CC(VEOF, c)))) + { + ttyinq_canonicalize(&tp->t_inq); + } + + ttydisc_echo(tp, c, quote); + + return 0; +} + +size_t ttydisc_rint_simple(struct lwp_tty *tp, const void *buf, size_t len) +{ + const char *cbuf; + + if (ttydisc_can_bypass(tp)) + return (ttydisc_rint_bypass(tp, buf, len)); + + for (cbuf = buf; len-- > 0; cbuf++) + { + if (ttydisc_rint(tp, *cbuf, 0) != 0) + break; + } + + return (cbuf - (const char *)buf); +} + +size_t ttydisc_rint_bypass(struct lwp_tty *tp, const void *buf, size_t len) +{ + size_t ret; + + tty_assert_locked(tp); + + MPASS(tp->t_flags & TF_BYPASS); + + rt_atomic_add(&tty_nin, len); + +#ifdef USING_BSD_HOOK + if (ttyhook_hashook(tp, rint_bypass)) + return ttyhook_rint_bypass(tp, buf, len); +#endif + + ret = ttyinq_write(&tp->t_inq, buf, len, 0); + ttyinq_canonicalize(&tp->t_inq); + if (ret < len) + tty_hiwat_in_block(tp); + + return (ret); +} + +void ttydisc_rint_done(struct lwp_tty *tp) +{ + tty_assert_locked(tp); + +#ifdef USING_BSD_HOOK + if (ttyhook_hashook(tp, rint_done)) + ttyhook_rint_done(tp); +#endif + + /* Wake up readers. */ + tty_wakeup(tp, FREAD); + /* Wake up driver for echo. */ + ttydevsw_outwakeup(tp); +} + +size_t ttydisc_rint_poll(struct lwp_tty *tp) +{ + size_t l; + + tty_assert_locked(tp); + +#ifdef USING_BSD_HOOK + if (ttyhook_hashook(tp, rint_poll)) + return ttyhook_rint_poll(tp); +#endif + + /* + * XXX: Still allow character input when there's no space in the + * buffers, but we haven't entered the high watermark. This is + * to allow backspace characters to be inserted when in + * canonical mode. + */ + l = ttyinq_bytesleft(&tp->t_inq); + if (l == 0 && (tp->t_flags & TF_HIWAT_IN) == 0) + return (1); + + return (l); +} + +static void ttydisc_wakeup_watermark(struct lwp_tty *tp) +{ + size_t c; + + c = ttyoutq_bytesleft(&tp->t_outq); + if (tp->t_flags & TF_HIWAT_OUT) + { + /* Only allow us to run when we're below the watermark. */ + if (c < tp->t_outlow) + return; + + /* Reset the watermark. */ + tp->t_flags &= ~TF_HIWAT_OUT; + } + else + { + /* Only run when we have data at all. */ + if (c == 0) + return; + } + tty_wakeup(tp, FWRITE); +} + +size_t ttydisc_getc(struct lwp_tty *tp, void *buf, size_t len) +{ + tty_assert_locked(tp); + + if (tp->t_flags & TF_STOPPED) + return 0; + +#ifdef USING_BSD_HOOK + if (ttyhook_hashook(tp, getc_inject)) + return ttyhook_getc_inject(tp, buf, len); +#endif + + len = ttyoutq_read(&tp->t_outq, buf, len); + +#ifdef USING_BSD_HOOK + if (ttyhook_hashook(tp, getc_capture)) + ttyhook_getc_capture(tp, buf, len); +#endif + + ttydisc_wakeup_watermark(tp); + rt_atomic_add(&tty_nout, len); + + return (len); +} + +int ttydisc_getc_uio(struct lwp_tty *tp, struct uio *uio) +{ + int error = 0; + ssize_t obytes = uio->uio_resid; + size_t len; + char buf[TTY_STACKBUF]; + + tty_assert_locked(tp); + + if (tp->t_flags & TF_STOPPED) + return 0; + + /* + * When a TTY hook is attached, we cannot perform unbuffered + * copying to userspace. Just call ttydisc_getc() and + * temporarily store data in a shadow buffer. + */ + if (ttyhook_hashook(tp, getc_capture) || ttyhook_hashook(tp, getc_inject)) + { + while (uio->uio_resid > 0) + { + /* Read to shadow buffer. */ + len = ttydisc_getc(tp, buf, MIN(uio->uio_resid, sizeof buf)); + if (len == 0) + break; + + /* Copy to userspace. */ + tty_unlock(tp); + error = uiomove(buf, len, uio); + tty_lock(tp); + + if (error != 0) + break; + } + } + else + { + error = ttyoutq_read_uio(&tp->t_outq, tp, uio); + + ttydisc_wakeup_watermark(tp); + rt_atomic_add(&tty_nout, obytes - uio->uio_resid); + } + + return error; +} + +size_t ttydisc_getc_poll(struct lwp_tty *tp) +{ + tty_assert_locked(tp); + + if (tp->t_flags & TF_STOPPED) + return 0; + +#if USING_BSD_HOOK + if (ttyhook_hashook(tp, getc_poll)) + return ttyhook_getc_poll(tp); +#endif + + return ttyoutq_bytesused(&tp->t_outq); +} diff --git a/components/lwp/terminal/terminal.h b/components/lwp/terminal/terminal.h new file mode 100644 index 00000000000..df0dc04128d --- /dev/null +++ b/components/lwp/terminal/terminal.h @@ -0,0 +1,415 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-13 Shell init ver. + */ + +#ifndef __LWP_TERMINAL_H__ +#define __LWP_TERMINAL_H__ + +#include "bsd_ttyqueue.h" +#include "bsd_ttydisc.h" + +#ifdef USING_BSD_HOOK +#include "bsd_ttyhook.h" +#endif + +#include +#include + +/* include kernel header for termios base definitions */ +#include +/* for _POSIX_VDISABLE */ +#include + +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2008 Ed Schouten + * All rights reserved. + * + * Portions of this software were developed under sponsorship from Snow + * B.V., the Netherlands. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +struct lwp_tty; + +/* + * Driver routines that are called from the line discipline to adjust + * hardware parameters and such. + */ +typedef int tsw_open_t(struct lwp_tty *tp); +typedef void tsw_close_t(struct lwp_tty *tp); +typedef void tsw_outwakeup_t(struct lwp_tty *tp); +typedef void tsw_inwakeup_t(struct lwp_tty *tp); +typedef int tsw_ioctl_t(struct lwp_tty *tp, rt_ubase_t cmd, rt_caddr_t data, + struct rt_thread *td); +typedef int tsw_cioctl_t(struct lwp_tty *tp, int unit, rt_ubase_t cmd, rt_caddr_t data, + struct rt_thread *td); +typedef int tsw_param_t(struct lwp_tty *tp, struct termios *t); +typedef int tsw_modem_t(struct lwp_tty *tp, int sigon, int sigoff); +typedef int tsw_mmap_t(struct lwp_tty *tp, vm_ooffset_t offset, + vm_paddr_t *paddr, int nprot, vm_memattr_t *memattr); + +typedef void tsw_pktnotify_t(struct lwp_tty *tp, char event); +typedef void tsw_free_t(void *softc); +typedef rt_bool_t tsw_busy_t(struct lwp_tty *tp); + +struct lwp_ttydevsw +{ + unsigned int tsw_flags; /* Default TTY flags. */ + + tsw_open_t *tsw_open; /* Device opening. */ + tsw_close_t *tsw_close; /* Device closure. */ + + tsw_outwakeup_t *tsw_outwakeup; /* Output available. */ + tsw_inwakeup_t *tsw_inwakeup; /* Input can be stored again. */ + + tsw_ioctl_t *tsw_ioctl; /* ioctl() hooks. */ + tsw_cioctl_t *tsw_cioctl; /* ioctl() on control devices. */ + tsw_param_t *tsw_param; /* TIOCSETA device parameter setting. */ + tsw_modem_t *tsw_modem; /* Modem sigon/sigoff. */ + + tsw_mmap_t *tsw_mmap; /* mmap() hooks. */ + tsw_pktnotify_t *tsw_pktnotify; /* TIOCPKT events. */ + + tsw_free_t *tsw_free; /* Destructor. */ + + tsw_busy_t *tsw_busy; /* Draining output. */ + + void *tsw_spare[3]; /* For future use. */ +}; +typedef struct lwp_ttydevsw *lwp_ttydevsw_t; + +struct lwp_tty +{ + struct rt_device parent; /* inherit from Class:RT_Device */ + struct rt_mutex *t_mtx; /* TTY lock. */ + struct rt_mutex t_mtxobj; /* Per-TTY lock (when not borrowing). */ + rt_list_t t_list; /* (l) TTY list entry. */ + int t_drainwait; /* (t) TIOCDRAIN timeout seconds. */ + unsigned int t_flags; /* (t) Terminal option flags. */ +/* Keep flags in sync with db_show_tty and pstat(8). */ +#define TF_NOPREFIX 0x00001 /* Don't prepend "tty" to device name. */ +#define TF_INITLOCK 0x00002 /* Create init/lock state devices. */ +#define TF_CALLOUT 0x00004 /* Create "cua" devices. */ +#define TF_OPENED_IN 0x00008 /* "tty" node is in use. */ +#define TF_OPENED_OUT 0x00010 /* "cua" node is in use. */ +#define TF_OPENED_CONS 0x00020 /* Device in use as console. */ +#define TF_OPENED (TF_OPENED_IN | TF_OPENED_OUT | TF_OPENED_CONS) +#define TF_GONE 0x00040 /* Device node is gone. */ +#define TF_OPENCLOSE 0x00080 /* Device is in open()/close(). */ +#define TF_ASYNC 0x00100 /* Asynchronous I/O enabled. */ +#define TF_LITERAL 0x00200 /* Accept the next character literally. */ +#define TF_HIWAT_IN 0x00400 /* We've reached the input watermark. */ +#define TF_HIWAT_OUT 0x00800 /* We've reached the output watermark. */ +#define TF_HIWAT (TF_HIWAT_IN | TF_HIWAT_OUT) +#define TF_STOPPED 0x01000 /* Output flow control - stopped. */ +#define TF_EXCLUDE 0x02000 /* Exclusive access. */ +#define TF_BYPASS 0x04000 /* Optimized input path. */ +#define TF_ZOMBIE 0x08000 /* Modem disconnect received. */ +#define TF_HOOK 0x10000 /* TTY has hook attached. */ +#define TF_BUSY_IN 0x20000 /* Process busy in read() -- not supported. */ +#define TF_BUSY_OUT 0x40000 /* Process busy in write(). */ +#define TF_BUSY (TF_BUSY_IN | TF_BUSY_OUT) + unsigned int t_revokecnt; /* (t) revoke() count. */ + + /* Buffering mechanisms. */ + struct ttyinq t_inq; /* (t) Input queue. */ + size_t t_inlow; /* (t) Input low watermark. */ + struct ttyoutq t_outq; /* (t) Output queue. */ + size_t t_outlow; /* (t) Output low watermark. */ + + /* Sleeping mechanisms. */ + struct rt_condvar t_inwait; /* (t) Input wait queue. */ + struct rt_condvar t_outwait; /* (t) Output wait queue. */ + struct rt_condvar t_outserwait; /* (t) Serial output wait queue. */ + struct rt_condvar t_bgwait; /* (t) Background wait queue. */ + struct rt_condvar t_dcdwait; /* (t) Carrier Detect wait queue. */ + + struct rt_wqueue t_inpoll; /* (t) Input poll queue. */ + struct rt_wqueue t_outpoll; /* (t) Output poll queue. */ + +#ifdef USING_BSD_AIO + struct sigio *t_sigio; /* (t) Asynchronous I/O. */ +#endif + + struct termios t_termios; /* (t) I/O processing flags. */ + struct winsize t_winsize; /* (t) Window size. */ + unsigned int t_column; /* (t) Current cursor position. */ + unsigned int t_writepos; /* (t) Where input was interrupted. */ + int t_compatflags; /* (t) COMPAT_43TTY flags. */ + + /* Init/lock-state devices. */ + struct termios t_termios_init_in; /* tty%s.init. */ + struct termios t_termios_lock_in; /* tty%s.lock. */ +#ifdef USING_BSD_INIT_LOCK_DEVICE + struct termios t_termios_init_out; /* cua%s.init. */ + struct termios t_termios_lock_out; /* cua%s.lock. */ + +#endif /* USING_BSD_INIT_LOCK_DEVICE */ + + struct lwp_ttydevsw *t_devsw; /* (c) Driver hooks. */ +#ifdef USING_BSD_HOOK + struct lwp_ttyhook *t_hook; /* (t) Capture/inject hook. */ +#endif + + /* Process signal delivery. */ + struct rt_processgroup *t_pgrp; /* (t) Foreground process group. */ + struct rt_session *t_session; /* (t) Associated session. */ + unsigned int t_sessioncnt; /* (t) Backpointing sessions. */ + + void *t_devswsoftc; /* (c) Soft config, for drivers. */ +#ifdef USING_BSD_HOOK + void *t_hooksoftc; /* (t) Soft config, for hooks. */ +#endif +#ifdef USING_BSD_CHAR_DEVICE + struct cdev *t_dev; /* (c) Primary character device. */ +#endif /* USING_BSD_CHAR_DEVICE */ +#ifdef USING_BSD_SIGINFO + size_t t_prbufsz; /* (t) SIGINFO buffer size. */ + char t_prbuf[]; /* (t) SIGINFO buffer. */ +#endif /* USING_BSD_SIGINFO */ +}; +typedef struct lwp_tty *lwp_tty_t; + +/* Allocation and deallocation. */ +void tty_rel_pgrp(struct lwp_tty *tp, struct rt_processgroup *pgrp); +void tty_rel_sess(struct lwp_tty *tp, struct rt_session *sess); +void tty_rel_gone(struct lwp_tty *tp); + +/* tty locking mechanism */ +#define tty_getlock(tp) ((tp)->t_mtx) +#define tty_lock(tp) rt_mutex_take(tty_getlock(tp), RT_WAITING_FOREVER); +#define tty_unlock(tp) rt_mutex_release(tty_getlock(tp)) +#define tty_lock_owned(tp) \ + (rt_mutex_get_owner(tty_getlock(tp)) == rt_thread_self()) +#define tty_lock_notrecused(tp) (rt_mutex_get_hold(tty_getlock(tp)) == 1) +#define tty_assert_locked(tp) RT_ASSERT(tty_lock_owned(tp)) +#define tty_lock_assert(tp, option) \ + (((option) == (MA_OWNED | MA_NOTRECURSED)) \ + ? (tty_lock_owned(tp) && tty_lock_notrecused(tp)) \ + : rt_assert_handler("Operation not allowed", __func__, __LINE__)) + +/* System messages. */ +int tty_checkoutq(struct lwp_tty *tp); +int tty_putchar(struct lwp_tty *tp, char c); +int tty_putstrn(struct lwp_tty *tp, const char *p, size_t n); + +int tty_ioctl(struct lwp_tty *tp, rt_ubase_t cmd, void *data, int fflag, + struct rt_thread *td); +int tty_ioctl_compat(struct lwp_tty *tp, rt_ubase_t cmd, rt_caddr_t data, int fflag, + struct rt_thread *td); +void tty_set_winsize(struct lwp_tty *tp, const struct winsize *wsz); +void tty_init_console(struct lwp_tty *tp, speed_t speed); +void tty_flush(struct lwp_tty *tp, int flags); +void tty_hiwat_in_block(struct lwp_tty *tp); +void tty_hiwat_in_unblock(struct lwp_tty *tp); +dev_t tty_udev(struct lwp_tty *tp); + +/* tesing on tty */ +#define tty_opened(tp) ((tp)->t_flags & TF_OPENED) +#define tty_gone(tp) ((tp)->t_flags & TF_GONE) +#define tty_softc(tp) ((tp)->t_devswsoftc) +#define tty_devname(tp) ((tp)->parent.parent.name) + +/** + * @brief TTY registeration on device subsystem + * + * @warning It's the duty of the caller to ensure that the name is not + * identical to any existed registered devices. + * + * @param terminal the target tty device + * @param name name of the device (must be exclusive) + * @return rt_err_t RT_EOK on success + */ +rt_err_t lwp_tty_register(lwp_tty_t terminal, const char *name); + +/** + * @brief TTY allocation and deallocation. TTY devices can be deallocated when + * the driver doesn't use it anymore, when the TTY isn't a session's + * controlling TTY and when the device node isn't opened through devfs. + * + * @param handle device handle of tty + * @param softc device configuration binding on tty + * @param prefix device name prefix + * @param cutom_mtx the lock provided to protect tty + * @return lwp_tty_t NULL on failure + */ +lwp_tty_t lwp_tty_create_ext(lwp_ttydevsw_t handle, void *softc, + rt_mutex_t custom_mtx); + +/** + * @brief Handful version of lwp_tty_create_ext + * + * @param softc device configuration binding on tty + * @param cutom_mtx the lock provided to protect tty + * @param prefix device name prefix + * @return lwp_tty_t NULL on failure + */ +lwp_tty_t lwp_tty_create(lwp_ttydevsw_t handle, void *softc); + +void lwp_tty_delete(lwp_tty_t tp); + +void lwp_tty_signal_sessleader(struct lwp_tty *tp, int sig); + +void lwp_tty_signal_pgrp(struct lwp_tty *tp, int sig); + +/** + * @brief Create a new pseudo-terminal multiplexer + * + * @param root_path path of root mount point of ptyfs + * @return rt_device_t new device object if succeed, otherwise NULL + */ +rt_err_t lwp_ptmx_init(rt_device_t ptmx_device, const char *root_path); + +#define LWP_CONSOLE_LOWEST_PRIOR 0 +#define LWP_CONSOLE_HIGHEST_PRIO INT_MAX +/** + * @brief Register an alternative backend tty device as console + */ +rt_err_t lwp_console_register_backend(struct rt_device *bakdev, int prio); + +rt_inline int ttydevsw_open(struct lwp_tty *tp) +{ + tty_assert_locked(tp); + MPASS(!tty_gone(tp)); + + return (tp->t_devsw->tsw_open(tp)); +} + +rt_inline void ttydevsw_close(struct lwp_tty *tp) +{ + tty_assert_locked(tp); + MPASS(!tty_gone(tp)); + + tp->t_devsw->tsw_close(tp); +} + +rt_inline void ttydevsw_outwakeup(struct lwp_tty *tp) +{ + tty_assert_locked(tp); + MPASS(!tty_gone(tp)); + + /* Prevent spurious wakeups. */ + if (ttydisc_getc_poll(tp) == 0) + return; + + tp->t_devsw->tsw_outwakeup(tp); +} + +rt_inline void ttydevsw_inwakeup(struct lwp_tty *tp) +{ + tty_assert_locked(tp); + MPASS(!tty_gone(tp)); + + /* Prevent spurious wakeups. */ + if (tp->t_flags & TF_HIWAT_IN) + return; + + tp->t_devsw->tsw_inwakeup(tp); +} + +rt_inline int ttydevsw_ioctl(struct lwp_tty *tp, rt_ubase_t cmd, rt_caddr_t data, + struct rt_thread *td) +{ + tty_assert_locked(tp); + MPASS(!tty_gone(tp)); + + return (tp->t_devsw->tsw_ioctl(tp, cmd, data, td)); +} + +rt_inline int ttydevsw_cioctl(struct lwp_tty *tp, int unit, rt_ubase_t cmd, + rt_caddr_t data, struct rt_thread *td) +{ + tty_assert_locked(tp); + MPASS(!tty_gone(tp)); + + return (tp->t_devsw->tsw_cioctl(tp, unit, cmd, data, td)); +} + +rt_inline int ttydevsw_param(struct lwp_tty *tp, struct termios *t) +{ + MPASS(!tty_gone(tp)); + + return (tp->t_devsw->tsw_param(tp, t)); +} + +rt_inline int ttydevsw_modem(struct lwp_tty *tp, int sigon, int sigoff) +{ + MPASS(!tty_gone(tp)); + + return (tp->t_devsw->tsw_modem(tp, sigon, sigoff)); +} + +rt_inline int ttydevsw_mmap(struct lwp_tty *tp, vm_ooffset_t offset, + vm_paddr_t *paddr, int nprot, vm_memattr_t *memattr) +{ + MPASS(!tty_gone(tp)); + + return (tp->t_devsw->tsw_mmap(tp, offset, paddr, nprot, memattr)); +} + +rt_inline void ttydevsw_pktnotify(struct lwp_tty *tp, char event) +{ + tty_assert_locked(tp); + MPASS(!tty_gone(tp)); + + tp->t_devsw->tsw_pktnotify(tp, event); +} + +rt_inline void ttydevsw_free(struct lwp_tty *tp) +{ + MPASS(tty_gone(tp)); + + tp->t_devsw->tsw_free(tty_softc(tp)); +} + +rt_inline rt_bool_t ttydevsw_busy(struct lwp_tty *tp) +{ + tty_assert_locked(tp); + MPASS(!tty_gone(tp)); + + return (tp->t_devsw->tsw_busy(tp)); +} + +rt_inline size_t ttydisc_read_poll(struct lwp_tty *tp) +{ + tty_assert_locked(tp); + + return ttyinq_bytescanonicalized(&tp->t_inq); +} + +rt_inline size_t ttydisc_write_poll(struct lwp_tty *tp) +{ + tty_assert_locked(tp); + + return ttyoutq_bytesleft(&tp->t_outq); +} + +#endif /* __LWP_TERMINAL_H__ */ diff --git a/components/lwp/terminal/tty_config.h b/components/lwp/terminal/tty_config.h new file mode 100644 index 00000000000..a1fe75dc7ab --- /dev/null +++ b/components/lwp/terminal/tty_config.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-13 Shell init ver. + */ + +#ifndef __TTY_CONFIG_H__ +#define __TTY_CONFIG_H__ + +/* default buffer size of tty siginfo */ +#define LWP_TTY_PRBUF_SIZE 256 + +/* + * System wide defaults for terminal state. + */ + +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1982, 1986, 1993 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)ttydefaults.h 8.4 (Berkeley) 1/21/94 + */ + +/* + * Defaults on "first" open. + */ +#define TTYDEF_IFLAG (BRKINT | ICRNL | IMAXBEL | IXON | IXANY | IUTF8) +#define TTYDEF_OFLAG (OPOST | ONLCR) +#define TTYDEF_LFLAG_NOECHO (ICANON | ISIG | IEXTEN) +#define TTYDEF_LFLAG_ECHO \ + (TTYDEF_LFLAG_NOECHO | ECHO | ECHOE | ECHOKE | ECHOCTL) +#define TTYDEF_LFLAG TTYDEF_LFLAG_ECHO +#define TTYDEF_CFLAG (CREAD | CS8 | HUPCL) +#define TTYDEF_SPEED (B9600) + +/* + * Control Character Defaults + */ +/* + * XXX: A lot of code uses lowercase characters, but control-character + * conversion is actually only valid when applied to uppercase + * characters. We just treat lowercase characters as if they were + * inserted as uppercase. + */ +#define _CONTROL(c) \ + ((c) >= 'a' && (c) <= 'z' ? ((c) - 'a' + 1) : (((c) - 'A' + 1) & 0x7f)) +#define CEOF _CONTROL('D') +#define CEOL 0xff /* XXX avoid _POSIX_VDISABLE */ +#define CERASE 0x7f +#define CERASE2 _CONTROL('H') +#define CINTR _CONTROL('C') +#define CSTATUS _CONTROL('T') +#define CKILL _CONTROL('U') +#define CMIN 1 +#define CQUIT _CONTROL('\\') +#define CSUSP _CONTROL('Z') +#define CTIME 0 +#define CDSUSP _CONTROL('Y') +#define CSTART _CONTROL('Q') +#define CSTOP _CONTROL('S') +#define CLNEXT _CONTROL('V') +#define CDISCARD _CONTROL('O') +#define CWERASE _CONTROL('W') +#define CREPRINT _CONTROL('R') +#define CEOT CEOF +/* compat */ +#define CBRK CEOL +#define CRPRNT CREPRINT +#define CFLUSH CDISCARD + +/* PROTECTED INCLUSION ENDS HERE */ +#endif /* !__TTY_CONFIG_H__ */ + +/* + * #define TTY_CONF_INCLUDE_CCHARS to include an array of default control + * characters. + */ +#ifdef TTY_CONF_INCLUDE_CCHARS +#include +#include +#include + +static const cc_t tty_ctrl_charset[NCCS] = { + [VINTR] = CINTR, + [VQUIT] = CQUIT, + [VERASE] = CERASE, + [VKILL] = CKILL, + [VEOF] = CEOF, + [VSTART] = CSTART, + [VSTOP] = CSTOP, + [VSUSP] = CSUSP, + [VREPRINT] = CREPRINT, + [VDISCARD] = CDISCARD, + [VWERASE] = CWERASE, + [VLNEXT] = CLNEXT, + [VMIN] = CMIN +#undef _CONTROL +}; + +#undef TTY_CONF_INCLUDE_CCHARS +#endif /* __TTY_CONFIG_H__ */ diff --git a/components/lwp/terminal/tty_cons.c b/components/lwp/terminal/tty_cons.c new file mode 100644 index 00000000000..42434f3568a --- /dev/null +++ b/components/lwp/terminal/tty_cons.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-12-11 Shell init ver. + */ + +#define DBG_TAG "lwp.tty" +#define DBG_LVL DBG_INFO +#include + +#include "tty_config.h" +#include "tty_internal.h" +#include "bsd_porting.h" +#include "terminal.h" + +#include + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops cons_rtdev_ops; +#endif + +struct backend_entry +{ + rt_list_t bakend_list_node; + int prio; + + rt_device_t bakdev; +}; + +static rt_list_t _bakend_list; + +static void _bent_enqueue(struct backend_entry *bent) +{ + struct backend_entry *idx; + rt_bool_t inserted = RT_FALSE; + rt_list_for_each_entry(idx, &_bakend_list, bakend_list_node) + { + if (idx->prio < bent->prio) + { + rt_list_insert_before(&idx->bakend_list_node, &bent->bakend_list_node); + inserted = RT_TRUE; + break; + } + } + + if (!inserted) + rt_list_insert_after(&_bakend_list, &bent->bakend_list_node); + return ; +} + +rt_err_t lwp_console_register_backend(struct rt_device *bakdev, int prio) +{ + rt_err_t ret = RT_EOK; + struct backend_entry *bent; + bent = rt_malloc(sizeof(struct backend_entry)); + if (bent) + { + rt_list_init(&bent->bakend_list_node); + bent->prio = prio; + bent->bakdev = bakdev; + + _bent_enqueue(bent); + } + else + { + ret = -RT_ENOMEM; + } + return ret; +} + +static struct rt_device _cons_rtdev; + +static int fops_open(struct dfs_file *file) +{ + return -EINVAL; +} + +static struct dfs_file_ops _cons_fops = { + .open = fops_open, +}; + +static rt_err_t _cons_readlink(struct rt_device *dev, char *buf, int len) +{ + int rc = -EIO; + struct backend_entry *bent; + if (!rt_list_isempty(&_bakend_list)) + { + bent = rt_list_first_entry(&_bakend_list, struct backend_entry, bakend_list_node); + if (bent) + { + RT_ASSERT(bent->bakdev); + strncpy(buf, bent->bakdev->parent.name, MIN(len, RT_NAME_MAX)); + LOG_D("%s: backend device %s", __func__, buf); + rc = 0; + } + } + + if (rc != 0) + { + LOG_W("%s: No backend device", __func__); + } + + return rc; +} + +static int _cons_init(void) +{ + rt_err_t rc; + + rt_list_init(&_bakend_list); + + /* setup system level device */ + _cons_rtdev.type = RT_Device_Class_Char; + _cons_rtdev.ops = &cons_rtdev_ops; + rc = rt_device_register(&_cons_rtdev, "console", RT_DEVICE_FLAG_DYNAMIC); + if (rc == RT_EOK) + { + _cons_rtdev.readlink = &_cons_readlink; + _cons_rtdev.fops = &_cons_fops; + } + + return rc; +} +INIT_DEVICE_EXPORT(_cons_init); diff --git a/components/lwp/terminal/tty_ctty.c b/components/lwp/terminal/tty_ctty.c new file mode 100644 index 00000000000..f0de0001f87 --- /dev/null +++ b/components/lwp/terminal/tty_ctty.c @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-30 Shell init ver. + */ +#define DBG_TAG "lwp.ctty" +#define DBG_LVL DBG_INFO +#include + +#define TTY_CONF_INCLUDE_CCHARS +#include "tty_config.h" +#include "tty_internal.h" +#include "terminal.h" + +static int fops_open(struct dfs_file *file) +{ + return -EINVAL; +} + +static rt_err_t ctty_readlink(struct rt_device *dev, char *buf, int len) +{ + int rc = -ENXIO; + lwp_tty_t tp; + rt_session_t sess; + rt_processgroup_t pgrp; + rt_lwp_t lwp; + + lwp = lwp_self(); + if (lwp) + { + pgrp = lwp->pgrp; + if (pgrp) + { + sess = pgrp->session; + if (sess) + { + tp = sess->ctty; + if (tp) + { + tty_lock(tp); + + if (lwp->pgrp == pgrp && pgrp->session == sess && sess->ctty == tp) + { + rt_strncpy(buf, tp->parent.parent.name, len); + rc = RT_EOK; + } + + tty_unlock(tp); + } + } + } + } + + return rc; +} + +static struct dfs_file_ops ctty_file_ops = { + .open = fops_open, +}; + +/* character device for tty */ +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops tty_dev_ops = { + /* IO directly through device is not allowed */ +}; +#else +#error Must enable RT_USING_DEVICE_OPS in Kconfig +#endif + +rt_inline void device_setup(rt_device_t ctty) +{ + ctty->type = RT_Device_Class_Char; +#ifdef RT_USING_DEVICE_OPS + ctty->ops = &tty_dev_ops; +#else +#error Must enable RT_USING_DEVICE_OPS in Kconfig +#endif +} + +/* register device to DFS */ +static int lwp_ctty_register(rt_device_t ctty) +{ + rt_err_t rc = -RT_ENOMEM; + const char *tty_name = "tty"; + + device_setup(ctty); + rc = rt_device_register(ctty, tty_name, RT_DEVICE_FLAG_DYNAMIC); + if (rc == RT_EOK) + { + ctty->readlink = &ctty_readlink; + ctty->fops = &ctty_file_ops; + } + return rc; +} + +static struct rt_device ctty; + +static int lwp_ctty_init(void) +{ + return lwp_ctty_register(&ctty); +} +INIT_DEVICE_EXPORT(lwp_ctty_init); diff --git a/components/lwp/terminal/tty_device.c b/components/lwp/terminal/tty_device.c new file mode 100644 index 00000000000..17364fabc10 --- /dev/null +++ b/components/lwp/terminal/tty_device.c @@ -0,0 +1,456 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-13 Shell init ver. + */ + +#define DBG_TAG "lwp.tty" +#define DBG_LVL DBG_INFO +#include + +#define TTY_CONF_INCLUDE_CCHARS +#include "tty_config.h" +#include "tty_internal.h" +#include "terminal.h" + +/* configure option: timeout of tty drain wait */ +static int tty_drainwait = 5 * 60; + +#define TTY_NAME_PREFIX "tty" +static char *alloc_device_name(const char *name) +{ + char *tty_dev_name; + long name_buf_len = (sizeof(TTY_NAME_PREFIX) - 1) /* raw prefix */ + + rt_strlen(name) /* custom name */ + + 1; /* tailing \0 */ + + tty_dev_name = rt_malloc(name_buf_len); + if (tty_dev_name) + sprintf(tty_dev_name, "%s%s", TTY_NAME_PREFIX, name); + return tty_dev_name; +} + +/* character device for tty */ +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops tty_dev_ops = { + /* IO directly through device is not allowed */ +}; +#else +#error Must enable RT_USING_DEVICE_OPS in Kconfig +#endif + +static int tty_fops_open(struct dfs_file *file) +{ + int rc; + lwp_tty_t tp; + rt_device_t device; + int devtype = 0; /* unused */ + + if (file->vnode && file->vnode->data) + { + if (file->vnode->ref_count != 1) + { + rc = 0; + } + else + { + device = (rt_device_t)file->vnode->data; + tp = rt_container_of(device, struct lwp_tty, parent); + rc = bsd_ttydev_methods.d_open(tp, file->flags, devtype, + rt_thread_self()); + } + } + else + { + rc = -EINVAL; + } + + return rc; +} + +static int tty_fops_close(struct dfs_file *file) +{ + int rc; + lwp_tty_t tp; + rt_device_t device; + int fflags = FFLAGS(file->flags); + int devtype = 0; /* unused */ + + if (file->vnode && file->vnode->data) + { + if (file->vnode->ref_count != 1) + { + rc = 0; + } + else + { + device = (rt_device_t)file->vnode->data; + tp = rt_container_of(device, struct lwp_tty, parent); + rc = bsd_ttydev_methods.d_close(tp, fflags, devtype, rt_thread_self()); + } + } + else + { + rc = -EINVAL; + } + + return rc; +} + +static int tty_fops_ioctl(struct dfs_file *file, int cmd, void *arg) +{ + int rc; + lwp_tty_t tp; + rt_device_t device; + + if (file->vnode && file->vnode->data) + { + device = (rt_device_t)file->vnode->data; + tp = rt_container_of(device, struct lwp_tty, parent); + rc = lwp_tty_ioctl_adapter(tp, cmd, file->flags, arg, rt_thread_self()); + } + else + { + rc = -EINVAL; + } + + return rc; +} + +static ssize_t tty_fops_read(struct dfs_file *file, void *buf, size_t count, + off_t *pos) +{ + ssize_t rc = 0; + int error; + struct uio uio; + struct iovec iov; + rt_device_t device; + struct lwp_tty *tp; + int ioflags; + int oflags = file->flags; + + if (file->vnode && file->vnode->data) + { + device = (rt_device_t)file->vnode->data; + tp = rt_container_of(device, struct lwp_tty, parent); + + /* setup ioflags */ + ioflags = 0; + if (oflags & O_NONBLOCK) + ioflags |= IO_NDELAY; + + /* setup uio parameters */ + iov.iov_base = (void *)buf; + iov.iov_len = count; + uio.uio_offset = file->fpos; + uio.uio_resid = count; + uio.uio_iov = &iov; + uio.uio_iovcnt = 1; + uio.uio_rw = UIO_READ; + + rc = count; + error = bsd_ttydev_methods.d_read(tp, &uio, ioflags); + rc -= uio.uio_resid; + if (error) + { + LOG_D("%s: failed to write %d bytes of data. error code %d", + __func__, uio.uio_resid, error); + rc = error; + } + + /* reset file context */ + file->fpos = uio.uio_offset; + } + + if (rc) + LOG_D("%s(len=%d, buf=%c \"%d\")", __func__, rc, *((char *)buf), + *((char *)buf)); + return rc; +} + +static ssize_t tty_fops_write(struct dfs_file *file, const void *buf, + size_t count, off_t *pos) +{ + ssize_t rc = 0; + int error; + struct uio uio; + struct iovec iov; + rt_device_t device; + struct lwp_tty *tp; + int ioflags; + int oflags = file->flags; + + if (file->vnode && file->vnode->data) + { + device = (rt_device_t)file->vnode->data; + tp = rt_container_of(device, struct lwp_tty, parent); + + /* setup ioflags */ + ioflags = 0; + if (oflags & O_NONBLOCK) + ioflags |= IO_NDELAY; + + /* setup uio parameters */ + iov.iov_base = (void *)buf; + iov.iov_len = count; + uio.uio_offset = file->fpos; + uio.uio_resid = count; + uio.uio_iov = &iov; + uio.uio_iovcnt = 1; + uio.uio_rw = UIO_WRITE; + + rc = count; + error = bsd_ttydev_methods.d_write(tp, &uio, ioflags); + if (error) + { + rc = error; + LOG_D("%s: failed to write %d bytes of data. error code %d", + __func__, uio.uio_resid, error); + } + else + { + rc -= uio.uio_resid; + } + + /* reset file context */ + file->fpos = uio.uio_offset; + } + return rc; +} + +static int tty_fops_flush(struct dfs_file *file) +{ + return -EINVAL; +} + +static off_t tty_fops_lseek(struct dfs_file *file, off_t offset, int wherece) +{ + return -EINVAL; +} + +static int tty_fops_truncate(struct dfs_file *file, off_t offset) +{ + /** + * regarding to POSIX.1, TRUNC is not supported for tty device. + * return 0 always to make filesystem happy + */ + return 0; +} + +static int tty_fops_poll(struct dfs_file *file, struct rt_pollreq *req) +{ + int rc; + rt_device_t device; + struct lwp_tty *tp; + + if (file->vnode && file->vnode->data) + { + device = (rt_device_t)file->vnode->data; + tp = rt_container_of(device, struct lwp_tty, parent); + + rc = bsd_ttydev_methods.d_poll(tp, req, rt_thread_self()); + } + else + { + rc = -1; + } + + return rc; +} + +static int tty_fops_mmap(struct dfs_file *file, struct lwp_avl_struct *mmap) +{ + return -EINVAL; +} + +static int tty_fops_lock(struct dfs_file *file, struct file_lock *flock) +{ + return -EINVAL; +} + +static int tty_fops_flock(struct dfs_file *file, int operation, struct file_lock *flock) +{ + return -EINVAL; +} + +static struct dfs_file_ops tty_file_ops = { + .open = tty_fops_open, + .close = tty_fops_close, + .ioctl = tty_fops_ioctl, + .read = tty_fops_read, + .write = tty_fops_write, + .flush = tty_fops_flush, + .lseek = tty_fops_lseek, + .truncate = tty_fops_truncate, + .poll = tty_fops_poll, + .mmap = tty_fops_mmap, + .lock = tty_fops_lock, + .flock = tty_fops_flock, +}; + +rt_inline void device_setup(lwp_tty_t terminal) +{ + terminal->parent.type = RT_Device_Class_Char; +#ifdef RT_USING_DEVICE_OPS + terminal->parent.ops = &tty_dev_ops; +#else +#error Must enable RT_USING_DEVICE_OPS in Kconfig +#endif +} + +/* register TTY device */ +rt_err_t lwp_tty_register(lwp_tty_t terminal, const char *name) +{ + rt_err_t rc = -RT_ENOMEM; + const char *tty_name; + char *alloc_name; + + if (terminal->t_devsw->tsw_flags & TF_NOPREFIX) + { + alloc_name = RT_NULL; + tty_name = name; + } + else + { + alloc_name = alloc_device_name(name); + tty_name = alloc_name; + } + + if (tty_name) + { + device_setup(terminal); + rc = rt_device_register(&terminal->parent, tty_name, 0); + if (rc == RT_EOK) + { + terminal->parent.fops = &tty_file_ops; + + LOG_D("%s() /dev/%s device registered", __func__, tty_name); + } + + rt_free(alloc_name); + } + return rc; +} + +static void tty_init_termios(lwp_tty_t tp) +{ + struct termios *t = &tp->t_termios_init_in; + + t->c_cflag = TTYDEF_CFLAG; + t->c_iflag = TTYDEF_IFLAG; + t->c_lflag = TTYDEF_LFLAG; + t->c_oflag = TTYDEF_OFLAG; + t->__c_ispeed = TTYDEF_SPEED; + t->__c_ospeed = TTYDEF_SPEED; + + memcpy(&t->c_cc, tty_ctrl_charset, + sizeof(tty_ctrl_charset) / sizeof(tty_ctrl_charset[0])); + +#ifdef USING_BSD_INIT_LOCK_DEVICE + tp->t_termios_init_out = *t; +#endif /* USING_BSD_INIT_LOCK_DEVICE */ +} + +lwp_tty_t lwp_tty_create_ext(lwp_ttydevsw_t handle, void *softc, + rt_mutex_t custom_mtx) +{ + lwp_tty_t tp; + + tp = rt_calloc(1, sizeof(struct lwp_tty) + #ifdef USING_BSD_SIGINFO + + LWP_TTY_PRBUF_SIZE + #endif + ); + + if (!tp) + return tp; + + bsd_devsw_init(handle); + +#ifdef USING_BSD_SIGINFO + tp->t_prbufsz = LWP_TTY_PRBUF_SIZE; +#endif + tp->t_devsw = handle; + tp->t_devswsoftc = softc; + tp->t_flags = handle->tsw_flags; + tp->t_drainwait = tty_drainwait; + + tty_init_termios(tp); + + cv_init(&tp->t_inwait, "ttyin"); + cv_init(&tp->t_outwait, "ttyout"); + cv_init(&tp->t_outserwait, "ttyosr"); + cv_init(&tp->t_bgwait, "ttybg"); + cv_init(&tp->t_dcdwait, "ttydcd"); + + rt_wqueue_init(&tp->t_inpoll); + rt_wqueue_init(&tp->t_outpoll); + + /* Allow drivers to use a custom mutex to lock the TTY. */ + if (custom_mtx != NULL) + { + tp->t_mtx = custom_mtx; + } + else + { + tp->t_mtx = &tp->t_mtxobj; + rt_mutex_init(&tp->t_mtxobj, "ttydev", RT_IPC_FLAG_PRIO); + } + +#ifdef USING_BSD_POLL + knlist_init_mtx(&tp->t_inpoll.si_note, tp->t_mtx); + knlist_init_mtx(&tp->t_outpoll.si_note, tp->t_mtx); +#endif + + return tp; +} + +lwp_tty_t lwp_tty_create(lwp_ttydevsw_t handle, void *softc) +{ + return lwp_tty_create_ext(handle, softc, NULL); +} + +void lwp_tty_delete(lwp_tty_t tp) +{ + /* + * ttyydev_leave() usually frees the i/o queues earlier, but it is + * not always called between queue allocation and here. The queues + * may be allocated by ioctls on a pty control device without the + * corresponding pty slave device ever being open, or after it is + * closed. + */ + ttyinq_free(&tp->t_inq); + ttyoutq_free(&tp->t_outq); + rt_wqueue_wakeup_all(&tp->t_inpoll, (void *)POLLHUP); + rt_wqueue_wakeup_all(&tp->t_outpoll, (void *)POLLHUP); + +#ifdef USING_BSD_POLL + knlist_destroy(&tp->t_inpoll.si_note); + knlist_destroy(&tp->t_outpoll.si_note); +#endif + + cv_destroy(&tp->t_inwait); + cv_destroy(&tp->t_outwait); + cv_destroy(&tp->t_bgwait); + cv_destroy(&tp->t_dcdwait); + cv_destroy(&tp->t_outserwait); + + if (tp->t_mtx == &tp->t_mtxobj) + rt_mutex_detach(&tp->t_mtxobj); + ttydevsw_free(tp); + rt_device_unregister(&tp->parent); + rt_free(tp); +} + +/* + * Report on state of foreground process group. + */ +void tty_info(struct lwp_tty *tp) +{ + /* TODO */ + return; +} diff --git a/components/lwp/terminal/tty_internal.h b/components/lwp/terminal/tty_internal.h new file mode 100644 index 00000000000..8bf336cb89a --- /dev/null +++ b/components/lwp/terminal/tty_internal.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-13 Shell init ver. + */ +#ifndef __LWP_TTY_INTERNAL_H__ +#define __LWP_TTY_INTERNAL_H__ + +#include "lwp.h" +#include "terminal.h" + +extern struct cdevsw bsd_ttydev_methods; + +extern struct bsd_fileops bsd_ptsdev_methods; + +/* bsd devsw porting */ +void bsd_devsw_init(struct lwp_ttydevsw *tsw); + +/** + * Do not assert RTS or DTR automatically. If CNO_RTSDTR is set then the RTS and + * DTR lines will not be asserted when the device is opened. As a result, this + * flag is only useful on initial-state devices. + * + * Note: this feature is not using on smart system, so this flag is always 0. + */ +#define CNO_RTSDTR 0 + +/* Waking up readers/writers. */ +int tty_wait(struct lwp_tty *tp, struct rt_condvar *cv); +int tty_wait_background(struct lwp_tty *tp, struct rt_thread *td, int sig); +int tty_timedwait(struct lwp_tty *tp, struct rt_condvar *cv, rt_tick_t timeout); +void tty_wakeup(struct lwp_tty *tp, int flags); + +void tty_info(struct lwp_tty *tp); + +void pts_set_lock(lwp_tty_t pts, rt_bool_t is_lock); +rt_bool_t pts_is_locked(lwp_tty_t pts); +int pts_get_pktmode(lwp_tty_t pts); +int pts_alloc(int fflags, struct rt_thread *td, struct dfs_file *ptm_file); + +int lwp_tty_ioctl_adapter(lwp_tty_t tp, int cmd, int oflags, void *args, rt_thread_t td); + +int lwp_tty_set_ctrl_proc(lwp_tty_t tp, rt_thread_t td); +int lwp_tty_assign_foreground(lwp_tty_t tp, rt_thread_t td, int pgid); +int lwp_tty_bg_stop(struct lwp_tty *tp, struct rt_condvar *cv); + +rt_inline rt_bool_t is_sess_leader(rt_lwp_t p) +{ + /** + * Note: a pgrp leader is never lose its group, so once it's + * true then it's always true + */ + return p->pid == p->sid; +} + +rt_inline int tty_is_ctty(struct lwp_tty *tp, struct rt_lwp *p) +{ + tty_assert_locked(tp); + + return p->pgrp->session == tp->t_session && p->term_ctrlterm; +} + +#endif /* __LWP_TTY_INTERNAL_H__ */ diff --git a/components/lwp/terminal/tty_ptmx.c b/components/lwp/terminal/tty_ptmx.c new file mode 100644 index 00000000000..8daebc099aa --- /dev/null +++ b/components/lwp/terminal/tty_ptmx.c @@ -0,0 +1,350 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-12-07 Shell init ver. + */ + +#define DBG_TAG "lwp.tty" +#define DBG_LVL DBG_INFO +#include + +#include "tty_config.h" +#include "tty_internal.h" +#include "bsd_porting.h" +#include "terminal.h" + +#include + +static struct dfs_file_ops ptm_fops; + +static int ptm_fops_open(struct dfs_file *file) +{ + int rc; + rt_uint32_t oflags = file->flags; + rt_thread_t cur_thr = rt_thread_self(); + + /* we don't check refcnt because each open will create a new device */ + if (file->vnode && file->vnode->data) + { + /** + * Filter out illegal flags + */ + if ((oflags & ~(O_RDWR | O_NOCTTY | O_CLOEXEC | O_LARGEFILE)) == 0) + { + rc = pts_alloc(FFLAGS(oflags & O_ACCMODE), cur_thr, file); + + /* detached operation from devfs */ + if (rc == 0) + file->vnode->fops = &ptm_fops; + } + else + { + rc = -EINVAL; + } + } + else + { + rc = -EINVAL; + } + + return rc; +} + +static int ptm_fops_close(struct dfs_file *file) +{ + int rc; + lwp_tty_t tp; + rt_device_t device; + + if (file->data) + { + if (file->vnode->ref_count != 1) + { + rc = 0; + } + else + { + device = (rt_device_t)file->data; + tp = rt_container_of(device, struct lwp_tty, parent); + rc = bsd_ptsdev_methods.fo_close(tp, rt_thread_self()); + } + } + else + { + rc = -EINVAL; + } + + return rc; +} + +static ssize_t ptm_fops_read(struct dfs_file *file, void *buf, size_t count, + off_t *pos) +{ + ssize_t rc = 0; + int error; + struct uio uio; + struct iovec iov; + rt_device_t device; + struct lwp_tty *tp; + int oflags = file->flags; + + if (file->data) + { + device = (rt_device_t)file->data; + tp = rt_container_of(device, struct lwp_tty, parent); + + /* setup uio parameters */ + iov.iov_base = (void *)buf; + iov.iov_len = count; + uio.uio_offset = file->fpos; + uio.uio_resid = count; + uio.uio_iov = &iov; + uio.uio_iovcnt = 1; + uio.uio_rw = UIO_READ; + + rc = count; + error = + bsd_ptsdev_methods.fo_read(tp, &uio, 0, oflags, rt_thread_self()); + rc -= uio.uio_resid; + if (error) + { + rc = error; + } + + /* reset file context */ + file->fpos = uio.uio_offset; + } + + return rc; +} + +static ssize_t ptm_fops_write(struct dfs_file *file, const void *buf, + size_t count, off_t *pos) +{ + ssize_t rc = 0; + int error; + struct uio uio; + struct iovec iov; + rt_device_t device; + struct lwp_tty *tp; + int oflags = file->flags; + + if (file->data) + { + device = (rt_device_t)file->data; + tp = rt_container_of(device, struct lwp_tty, parent); + + /* setup uio parameters */ + iov.iov_base = (void *)buf; + iov.iov_len = count; + uio.uio_offset = file->fpos; + uio.uio_resid = count; + uio.uio_iov = &iov; + uio.uio_iovcnt = 1; + uio.uio_rw = UIO_WRITE; + + rc = count; + error = + bsd_ptsdev_methods.fo_write(tp, &uio, 0, oflags, rt_thread_self()); + if (error) + { + rc = error; + } + else + { + rc -= uio.uio_resid; + } + + /* reset file context */ + file->fpos = uio.uio_offset; + } + return rc; +} + +static int ptm_fops_ioctl(struct dfs_file *file, int cmd, void *arg) +{ + int rc; + lwp_tty_t tp; + rt_device_t device; + rt_ubase_t cmd_normal = (unsigned int)cmd; + + if (file->data) + { + device = (rt_device_t)file->data; + tp = rt_container_of(device, struct lwp_tty, parent); + + switch (cmd_normal) + { + case TIOCSPTLCK: + { + int is_lock; + if (lwp_get_from_user(&is_lock, arg, sizeof(int)) != sizeof(int)) + return -EFAULT; + pts_set_lock(tp, is_lock); + rc = 0; + } + break; + case TIOCGPTLCK: + { + int is_lock = pts_is_locked(tp); + if (lwp_put_to_user(arg, &is_lock, sizeof(int)) != sizeof(int)) + return -EFAULT; + rc = 0; + } + break; + case TIOCGPKT: + { + int pktmode = pts_get_pktmode(tp); + if (lwp_put_to_user(arg, &pktmode, sizeof(int)) != sizeof(int)) + return -EFAULT; + rc = 0; + } + break; + default: + rc = bsd_ptsdev_methods.fo_ioctl( + tp, cmd_normal, arg, 0, FFLAGS(file->flags), rt_thread_self()); + break; + } + } + else + { + rc = -EINVAL; + } + + return rc; +} + +static int ptm_fops_flush(struct dfs_file *file) +{ + return -EINVAL; +} + +static off_t ptm_fops_lseek(struct dfs_file *file, off_t offset, int wherece) +{ + return -EINVAL; +} + +static int ptm_fops_truncate(struct dfs_file *file, off_t offset) +{ + return -EINVAL; +} + +static int ptm_fops_poll(struct dfs_file *file, struct rt_pollreq *req) +{ + int rc; + rt_device_t device; + struct lwp_tty *tp; + + if (file->data) + { + device = (rt_device_t)file->data; + tp = rt_container_of(device, struct lwp_tty, parent); + + rc = bsd_ptsdev_methods.fo_poll(tp, req, 0, rt_thread_self()); + } + else + { + rc = -1; + } + + return rc; +} + +static int ptm_fops_mmap(struct dfs_file *file, struct lwp_avl_struct *mmap) +{ + return -EINVAL; +} + +static int ptm_fops_lock(struct dfs_file *file, struct file_lock *flock) +{ + return -EINVAL; +} + +static int ptm_fops_flock(struct dfs_file *file, int operation, struct file_lock *flock) +{ + return -EINVAL; +} + +static struct dfs_file_ops ptm_fops = { + .open = ptm_fops_open, + .close = ptm_fops_close, + .ioctl = ptm_fops_ioctl, + .read = ptm_fops_read, + .write = ptm_fops_write, + .flush = ptm_fops_flush, + .lseek = ptm_fops_lseek, + .truncate = ptm_fops_truncate, + .poll = ptm_fops_poll, + .mmap = ptm_fops_mmap, + .lock = ptm_fops_lock, + .flock = ptm_fops_flock, +}; + +rt_err_t lwp_ptmx_init(rt_device_t ptmx_device, const char *root_path) +{ + char *device_name; + int root_len; + const char *dev_rel_path; + rt_err_t rc; + + root_len = strlen(root_path); + dev_rel_path = "/ptmx"; + device_name = rt_malloc(root_len + sizeof("/ptmx")); + + if (device_name) + { + /* Register device */ + sprintf(device_name, "%s%s", root_path, dev_rel_path); + rt_device_register(ptmx_device, device_name, 0); + + /* Setup fops */ + ptmx_device->fops = &ptm_fops; + + rt_free(device_name); + + rc = RT_EOK; + } + else + { + rc = -RT_ENOMEM; + } + + return rc; +} + +/* system level ptmx */ +static struct rt_device sysptmx; + +static struct dfs_file_ops sysptmx_file_ops; + +static rt_err_t sysptmx_readlink(struct rt_device *dev, char *buf, int len) +{ + int rc = 0; + + /* TODO: support multi-root ? */ + strncpy(buf, "pts/ptmx", len); + + return rc; +} + +static int _sys_ptmx_init(void) +{ + rt_err_t rc; + rt_device_t sysptmx_rtdev = &sysptmx; + + /* setup system level device */ + sysptmx_rtdev->type = RT_Device_Class_Char; + sysptmx_rtdev->ops = RT_NULL; + rc = rt_device_register(sysptmx_rtdev, "ptmx", RT_DEVICE_FLAG_DYNAMIC); + if (rc == RT_EOK) + { + sysptmx_rtdev->readlink = &sysptmx_readlink; + sysptmx_rtdev->fops = &sysptmx_file_ops; + } + return rc; +} +INIT_DEVICE_EXPORT(_sys_ptmx_init); diff --git a/components/mm/mm_page.c b/components/mm/mm_page.c index cc46ed46dae..ab3b8982247 100644 --- a/components/mm/mm_page.c +++ b/components/mm/mm_page.c @@ -109,7 +109,7 @@ static void _collect() rt_page_t page = _trace_head; if (!page) { - LOG_RAW("ok! ALLOC CNT %ld\n", _alloc_cnt); + rt_kprintf("ok! ALLOC CNT %ld\n", _alloc_cnt); } else { @@ -159,7 +159,7 @@ void _report(rt_page_t page, size_t size_bits, char *msg) { void *pg_va = rt_page_page2addr(page); LOG_W("%s: %p, allocator: %p, size bits: %lx", msg, pg_va, page->caller, page->trace_size); - LOG_RAW("backtrace\n"); + rt_kprintf("backtrace\n"); rt_backtrace(); } @@ -175,7 +175,7 @@ static void _trace_free(rt_page_t page, void *caller, size_t size_bits) } else if (page->trace_size != size_bits) { - LOG_RAW("free with size bits %lx\n", size_bits); + rt_kprintf("free with size bits %lx\n", size_bits); _report(page, size_bits, "incompatible size bits parameter"); return ; } @@ -622,27 +622,27 @@ void list_page(void) struct rt_page *lp = page_list_low[i]; struct rt_page *hp = page_list_high[i]; - LOG_RAW("level %d ", i); + rt_kprintf("level %d ", i); while (lp) { free += (1UL << i); - LOG_RAW("[0x%08p]", rt_page_page2addr(lp)); + rt_kprintf("[0x%08p]", rt_page_page2addr(lp)); lp = lp->next; } while (hp) { free += (1UL << i); - LOG_RAW("[0x%08p]", rt_page_page2addr(hp)); + rt_kprintf("[0x%08p]", rt_page_page2addr(hp)); hp = hp->next; } - LOG_RAW("\n"); + rt_kprintf("\n"); } rt_spin_unlock_irqrestore(&_spinlock, level); - LOG_RAW("-------------------------------\n"); - LOG_RAW("Page Summary:\n => free/installed: 0x%lx/0x%lx (%ld/%ld KB)\n", free, installed, PGNR2SIZE(free), PGNR2SIZE(installed)); - LOG_RAW("-------------------------------\n"); + rt_kprintf("-------------------------------\n"); + rt_kprintf("Page Summary:\n => free/installed: 0x%lx/0x%lx (%ld/%ld KB)\n", free, installed, PGNR2SIZE(free), PGNR2SIZE(installed)); + rt_kprintf("-------------------------------\n"); } MSH_CMD_EXPORT(list_page, show page info); diff --git a/components/net/sal/include/sal_msg.h b/components/net/sal/include/sal_msg.h index 2a2cff1d0b9..7d52b25b63a 100644 --- a/components/net/sal/include/sal_msg.h +++ b/components/net/sal/include/sal_msg.h @@ -58,6 +58,9 @@ struct unix_conn int type; int proto; +#ifdef SAL_USING_AF_UNIX + rt_atomic_t msg_count; +#endif rt_uint32_t send_timeout; rt_uint32_t recv_timeout; rt_wqueue_t wq_read_head; diff --git a/components/utilities/libadt/bitmap/bitmap.h b/components/utilities/libadt/bitmap/bitmap.h index 72fe54333ae..f1b689b72e1 100755 --- a/components/utilities/libadt/bitmap/bitmap.h +++ b/components/utilities/libadt/bitmap/bitmap.h @@ -18,7 +18,7 @@ typedef rt_ubase_t rt_bitmap_t; #define RT_BITMAP_BITS_MIN (sizeof(rt_bitmap_t) * 8) #define RT_BITMAP_LEN(bits) (((bits) + (RT_BITMAP_BITS_MIN) - 1) / (RT_BITMAP_BITS_MIN)) #define RT_BITMAP_BIT_LEN(nr) (nr * RT_BITMAP_BITS_MIN) -#define RT_DECLARE_BITMAP(name, bits) rt_bitmap_t name[RT_BITMAP_LEN(bits)] +#define RT_BITMAP_DECLARE(name, bits) rt_bitmap_t name[RT_BITMAP_LEN(bits)] rt_inline void rt_bitmap_set_bit(rt_bitmap_t *bitmap, rt_uint32_t bit) { diff --git a/components/utilities/resource/SConscript b/components/utilities/resource/SConscript index 6d572130a89..4410eaf9379 100644 --- a/components/utilities/resource/SConscript +++ b/components/utilities/resource/SConscript @@ -3,6 +3,10 @@ from building import * cwd = GetCurrentDir() src = Glob('*.c') CPPPATH = [cwd] + +if GetDepend('RT_USING_ADT_BITMAP') == False: + SrcRemove(src, ['rid_bitmap.c']) + group = DefineGroup('Utilities', src, depend = ['RT_USING_RESOURCE_ID'], CPPPATH = CPPPATH) Return('group') diff --git a/components/utilities/resource/rid_bitmap.c b/components/utilities/resource/rid_bitmap.c new file mode 100644 index 00000000000..ebadece2a44 --- /dev/null +++ b/components/utilities/resource/rid_bitmap.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-12-07 Shell First version + */ + +#include "rid_bitmap.h" +#include +#include + +void rid_bitmap_init(rid_bitmap_t mgr, int min_id, int total_id_count, + rt_bitmap_t *set, struct rt_mutex *id_lock) +{ + mgr->min_id = min_id; + mgr->total_id_count = total_id_count; + mgr->bitset = set; + mgr->id_lock = id_lock; + + return; +} + +long rid_bitmap_get(rid_bitmap_t mgr) +{ + long id; + long overflow; + if (mgr->id_lock) + { + rt_mutex_take(mgr->id_lock, RT_WAITING_FOREVER); + } + + overflow = mgr->total_id_count; + id = rt_bitmap_next_clear_bit(mgr->bitset, 0, overflow); + if (id == overflow) + { + id = -1; + } + else + { + rt_bitmap_set_bit(mgr->bitset, id); + id += mgr->min_id; + } + + if (mgr->id_lock) + { + rt_mutex_release(mgr->id_lock); + } + return id; +} + +long rid_bitmap_get_named(rid_bitmap_t mgr, long no) +{ + long id_relative; + long overflow; + long min; + + if (mgr->id_lock) + { + rt_mutex_take(mgr->id_lock, RT_WAITING_FOREVER); + } + + min = mgr->min_id; + id_relative = no - min; + overflow = mgr->total_id_count; + if (id_relative >= min && id_relative < overflow) + { + if (rt_bitmap_test_bit(mgr->bitset, id_relative)) + { + id_relative = -RT_EBUSY; + } + else + { + rt_bitmap_set_bit(mgr->bitset, id_relative); + id_relative += min; + } + } + else + { + id_relative = -1; + } + + if (mgr->id_lock) + { + rt_mutex_release(mgr->id_lock); + } + return id_relative; +} + +void rid_bitmap_put(rid_bitmap_t mgr, long no) +{ + long id_relative; + long overflow; + long min; + + if (mgr->id_lock) + { + rt_mutex_take(mgr->id_lock, RT_WAITING_FOREVER); + } + + min = mgr->min_id; + id_relative = no - min; + overflow = mgr->total_id_count; + if (id_relative >= min && id_relative < overflow && + rt_bitmap_test_bit(mgr->bitset, id_relative)) + { + rt_bitmap_clear_bit(mgr->bitset, id_relative); + } + + if (mgr->id_lock) + { + rt_mutex_release(mgr->id_lock); + } +} diff --git a/components/utilities/resource/rid_bitmap.h b/components/utilities/resource/rid_bitmap.h new file mode 100644 index 00000000000..d1e4e1ccc4f --- /dev/null +++ b/components/utilities/resource/rid_bitmap.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-12-07 Shell First version + */ + +#ifndef __RID_BITMAP_H__ +#define __RID_BITMAP_H__ + +#include +#include +#include + +#define RESOURCE_ID_INIT {0} + +typedef struct rid_bitmap +{ + struct rt_mutex *id_lock; + long min_id; + long total_id_count; + rt_bitmap_t *bitset; +} *rid_bitmap_t; + +void rid_bitmap_init(rid_bitmap_t mgr, int min_id, int total_id_count, + rt_bitmap_t *set, struct rt_mutex *id_lock); +long rid_bitmap_get(rid_bitmap_t mgr); +long rid_bitmap_get_named(rid_bitmap_t mgr, long no); +void rid_bitmap_put(rid_bitmap_t mgr, long no); + +#endif /* __RID_BITMAP_H__ */ diff --git a/components/utilities/ulog/ulog.c b/components/utilities/ulog/ulog.c index 4e091f9a2b5..cb0790b9de6 100644 --- a/components/utilities/ulog/ulog.c +++ b/components/utilities/ulog/ulog.c @@ -1272,7 +1272,7 @@ rt_err_t ulog_backend_register(ulog_backend_t backend, const char *name, rt_bool backend->support_color = support_color; backend->out_level = LOG_FILTER_LVL_ALL; - rt_strncpy(backend->name, name, RT_NAME_MAX); + rt_strncpy(backend->name, name, RT_NAME_MAX - 1); level = rt_spin_lock_irqsave(&_spinlock); rt_slist_append(&ulog.backend_list, &backend->list); diff --git a/components/utilities/ymodem/ry_sy.c b/components/utilities/ymodem/ry_sy.c index 557d4bcdabb..89664f1ad91 100644 --- a/components/utilities/ymodem/ry_sy.c +++ b/components/utilities/ymodem/ry_sy.c @@ -186,7 +186,10 @@ static enum rym_code _rym_send_end( rt_uint8_t *buf, rt_size_t len) { + struct custom_ctx *cctx = (struct custom_ctx *)ctx; rt_memset(buf, 0, len); + close(cctx->fd); + cctx->fd = -1; return RYM_CODE_SOH; } diff --git a/documentation/memory/figures/08smem_work4.png b/documentation/memory/figures/08smem_work4.png new file mode 100644 index 00000000000..92544169d03 Binary files /dev/null and b/documentation/memory/figures/08smem_work4.png differ diff --git a/documentation/memory/memory.md b/documentation/memory/memory.md index 892107fd751..2ac9fe30efb 100644 --- a/documentation/memory/memory.md +++ b/documentation/memory/memory.md @@ -43,7 +43,13 @@ Any or none of these memory heap management algorithms can be chosen when the sy ### Small Memory Management Algorithm -The small memory management algorithm is a simple memory allocation algorithm. Initially, it is a large piece of memory. When a memory block needs to be allocated, the matching memory block is segmented from the large memory block, and then this matching free memory block is returned to the heap management system. Each memory block contains data head for management use through which the used block and the free block are linked by a doubly linked list, as shown in the following figure: +The small memory management algorithm is a simple memory allocation algorithm. Initially, it is a large piece of memory. When a memory block needs to be allocated, the matching memory block is segmented from the large memory block, and then this matching free memory block is returned to the heap management system. Each memory block contains data head for management use through which the used block and the free block are linked by a doubly linked list. + + + +**Use this implementation before 4.1.0** + +As shown in the following figure: ![Small Memory Management Working Mechanism Diagram](figures/08smem_work.png) @@ -55,6 +61,22 @@ Each memory block (whether it is an allocated memory block or a free memory bloc The performance of memory management is mainly reflected in the allocation and release of memory. The small memory management algorithm can be embodied by the following examples. + + +**4.1.0 and later use this implementation** + +As shown in the following figure: + +![](figures/08smem_work4.png) + +**Heap Start**: The heap head address stores memory usage information, the heap head address pointer, the heap end address pointer, the minimum heap free address pointer, and the memory size. + +Each memory block (whether it is an allocated memory block or a free memory block) contains a data head, including: + +**pool_ptr**: Small memory object address. If the last bit of the memory block is 1, it is used. If the last bit of the memory block is 0, it is not used. When used, the structure members of the small memory algorithm can be quickly obtained by calc. + + + As shown in the following figure, the free list pointer lfree initially points to a 32-byte block of memory. When the user thread wants to allocate a 64-byte memory block, since the memory block pointed to by this lfree pointer is only 32 bytes and does not meet the requirements, the memory manager will continue to search for the next memory block. When the next memory block with 128 bytes is found, it meets the requirements of the allocation. Because this memory block is large, the allocator will split the memory block, and the remaining memory block (52 bytes) will remain in the lfree linked list, as shown in the following table which is after 64 bytes is allocated. ![Small Memory Management Algorithm Linked List Structure Diagram 1](figures/08smem_work2.png) diff --git a/examples/utest/testcases/kernel/mem_tc.c b/examples/utest/testcases/kernel/mem_tc.c index 028876dfa9f..aee9795117f 100644 --- a/examples/utest/testcases/kernel/mem_tc.c +++ b/examples/utest/testcases/kernel/mem_tc.c @@ -15,9 +15,6 @@ struct rt_small_mem_item { rt_ubase_t pool_ptr; /**< small memory object addr */ -#ifdef ARCH_CPU_64BIT - rt_uint32_t resv; -#endif /* ARCH_CPU_64BIT */ rt_size_t next; /**< next free item */ rt_size_t prev; /**< prev free item */ #ifdef RT_USING_MEMTRACE diff --git a/examples/utest/testcases/lwp/SConscript b/examples/utest/testcases/lwp/SConscript new file mode 100644 index 00000000000..68fe5bea41a --- /dev/null +++ b/examples/utest/testcases/lwp/SConscript @@ -0,0 +1,13 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = [] +CPPPATH = [cwd] + +if GetDepend(['UTEST_LWP_TC', 'RT_USING_SMART']): + src += ['condvar_timedwait_tc.c', 'condvar_broadcast_tc.c', 'condvar_signal_tc.c'] + +group = DefineGroup('utestcases', src, depend = ['RT_USING_UTESTCASES'], CPPPATH = CPPPATH) + +Return('group') diff --git a/examples/utest/testcases/lwp/condvar_broadcast_tc.c b/examples/utest/testcases/lwp/condvar_broadcast_tc.c new file mode 100644 index 00000000000..be35c606057 --- /dev/null +++ b/examples/utest/testcases/lwp/condvar_broadcast_tc.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-20 Shell add test suites + */ + +#include "common.h" +#include "rtconfig.h" +#include "utest_assert.h" + +#include +#include + +static struct rt_mutex _local_mtx; +static struct rt_condvar _local_cv; +#define THREAD_NUM 8 +#define STACK_SIZE (0x2000) + +static volatile int start_num; +static volatile int waken_num; + +static void thr_func(void *arg) +{ + int rc; + rt_mutex_t mutex = &_local_mtx; + rt_condvar_t cond = &_local_cv; + rt_mutex_take(mutex, RT_WAITING_FOREVER); + + start_num++; + rc = rt_condvar_timedwait(cond, mutex, RT_KILLABLE, RT_WAITING_FOREVER); + if (rc != 0) + { + LOG_E("cond_wait returned %d\n", rc); + uassert_false(1); + return; + } + + if (rt_mutex_get_owner(mutex) != rt_thread_self()) + { + LOG_E("Should not be able to lock the mutex again"); + uassert_false(1); + return; + } + else + { + uassert_true(1); + } + LOG_I("Thread was wakened and acquired the mutex again"); + waken_num++; + + if (rt_mutex_release(mutex) != 0) + { + LOG_E("Failed to release the mutex"); + uassert_false(1); + return; + } + else + { + uassert_true(1); + } + + return ; +} + +static void *stack_addr[THREAD_NUM]; + +static void condvar_broadcast_tc(void) +{ + rt_mutex_t mutex = &_local_mtx; + rt_condvar_t cond = &_local_cv; + struct rt_thread thread[THREAD_NUM]; + + for (size_t i = 0; i < THREAD_NUM; i++) + { + if (rt_thread_init(&thread[i], "utest", thr_func, RT_NULL, + stack_addr[i], STACK_SIZE, 25, 100) != 0) + { + LOG_E("Fail to create thread[%d]\n", i); + return; + } + rt_thread_startup(&thread[i]); + } + + while (start_num < THREAD_NUM) + rt_thread_mdelay(1); + + rt_mutex_take(mutex, RT_WAITING_FOREVER); + if (rt_condvar_broadcast(cond)) + { + uassert_false(1); + return ; + } + rt_mutex_release(mutex); + + rt_thread_mdelay(1); + + if (waken_num < THREAD_NUM) + { + LOG_E("[Main thread] Not all waiters were wakened\n"); + uassert_false(1); + return ; + } + else + { + utest_int_equal(waken_num, THREAD_NUM); + } + LOG_I("[Main thread] all waiters were wakened\n"); + + return; +} + +static rt_err_t utest_tc_init(void) +{ + start_num = 0; + waken_num = 0; + if (rt_mutex_init(&_local_mtx, "utest", RT_IPC_FLAG_PRIO) != 0) + { + perror("pthread_mutex_init() error"); + uassert_false(1); + return -1; + } + + rt_condvar_init(&_local_cv, NULL); + + for (size_t i = 0; i < THREAD_NUM; i++) + { + stack_addr[i] = + rt_pages_alloc_ext(rt_page_bits(STACK_SIZE), PAGE_ANY_AVAILABLE); + utest_int_not_equal(stack_addr[i], RT_NULL); + } + return RT_EOK; +} + +static rt_err_t utest_tc_cleanup(void) +{ + rt_mutex_detach(&_local_mtx); + rt_condvar_detach(&_local_cv); + + for (size_t i = 0; i < THREAD_NUM; i++) + { + rt_pages_free(stack_addr[i], rt_page_bits(STACK_SIZE)); + stack_addr[i] = 0; + } + return RT_EOK; +} + +static void testcase(void) +{ + UTEST_UNIT_RUN(condvar_broadcast_tc); +} +UTEST_TC_EXPORT(testcase, "testcases.ipc.condvar.broadcast", utest_tc_init, + utest_tc_cleanup, 10); diff --git a/examples/utest/testcases/lwp/condvar_signal_tc.c b/examples/utest/testcases/lwp/condvar_signal_tc.c new file mode 100644 index 00000000000..4bb65d423dc --- /dev/null +++ b/examples/utest/testcases/lwp/condvar_signal_tc.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-20 Shell add test suites + */ + +#include "common.h" +#include "utest_assert.h" + +#include +#include +#define STACK_SIZE (0x2000) + +static struct rt_mutex _local_mtx; +static struct rt_condvar _local_cv; + +static void waker_thr(void *param) +{ + int err; + rt_mutex_t mutex = &_local_mtx; + rt_condvar_t cond = &_local_cv; + rt_mutex_take(mutex, RT_WAITING_FOREVER); + err = rt_condvar_signal(cond); + + if (err != 0) + { + LOG_E("errno=%d, ret=%d\n", errno, err); + LOG_E("rt_condvar_signal() error"); + uassert_false(1); + } + else + { + uassert_false(0); + } + rt_mutex_release(mutex); + + return; +} + +static void condvar_signal_tc(void) +{ + rt_thread_t waker; + rt_mutex_t mutex = &_local_mtx; + rt_condvar_t cond = &_local_cv; + int err; + + waker = rt_thread_create("waker", waker_thr, 0, STACK_SIZE, 25, 50); + uassert_not_null(waker); + + if (rt_mutex_take(mutex, RT_WAITING_FOREVER) != 0) + { + LOG_E("pthread_mutex_lock() error"); + uassert_false(1); + return; + } + else + { + uassert_false(0); + } + + rt_thread_startup(waker); + + err = rt_condvar_timedwait(cond, mutex, RT_KILLABLE, 100); + if (err != 0) + { + if (err == -EINTR || err == -ETIMEDOUT) + { + puts("wait timed out"); + uassert_false(0); + } + else + { + LOG_E("errno=%d, ret=%d\n", errno, err); + LOG_E("pthread_cond_timedwait() error"); + uassert_false(1); + } + } + + err = rt_mutex_release(mutex); + if (err != 0) + { + LOG_E("errno=%d, ret=%d\n", errno, err); + LOG_E("rt_mutex_release() error"); + uassert_false(1); + } + else + { + uassert_false(0); + } + + return ; +} + +static rt_err_t utest_tc_init(void) +{ + if (rt_mutex_init(&_local_mtx, "utest", RT_IPC_FLAG_PRIO) != 0) + { + perror("pthread_mutex_init() error"); + uassert_false(1); + return -1; + } + + rt_condvar_init(&_local_cv, NULL); + return RT_EOK; +} + +static rt_err_t utest_tc_cleanup(void) +{ + rt_mutex_detach(&_local_mtx); + rt_condvar_detach(&_local_cv); + return RT_EOK; +} + +static void testcase(void) +{ + UTEST_UNIT_RUN(condvar_signal_tc); +} +UTEST_TC_EXPORT(testcase, "testcases.ipc.condvar.signal", utest_tc_init, utest_tc_cleanup, 10); diff --git a/examples/utest/testcases/lwp/condvar_timedwait_tc.c b/examples/utest/testcases/lwp/condvar_timedwait_tc.c new file mode 100644 index 00000000000..afd9418d56e --- /dev/null +++ b/examples/utest/testcases/lwp/condvar_timedwait_tc.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-11-20 Shell add test suites + */ + +#include "common.h" +#include "utest_assert.h" + +#include +#include + +static struct rt_mutex _local_mtx; +static struct rt_condvar _local_cv; + +static void condvar_timedwait_tc(void) +{ + rt_mutex_t mutex = &_local_mtx; + rt_condvar_t cond = &_local_cv; + int err; + + if (rt_mutex_take(mutex, RT_WAITING_FOREVER) != 0) + { + LOG_E("pthread_mutex_lock() error"); + uassert_false(1); + return; + } + + err = rt_condvar_timedwait(cond, mutex, RT_KILLABLE, 100); + if (err != 0) + { + if (err == -EINTR || err == -ETIMEDOUT) + { + puts("wait timed out"); + uassert_false(0); + } + else + { + LOG_E("errno=%d, ret=%d\n", errno, err); + LOG_E("pthread_cond_timedwait() error"); + uassert_false(1); + } + } + + return ; +} + +static rt_err_t utest_tc_init(void) +{ + if (rt_mutex_init(&_local_mtx, "utest", RT_IPC_FLAG_PRIO) != 0) + { + perror("pthread_mutex_init() error"); + uassert_false(1); + return -1; + } + + rt_condvar_init(&_local_cv, NULL); + return RT_EOK; +} + +static rt_err_t utest_tc_cleanup(void) +{ + rt_mutex_detach(&_local_mtx); + rt_condvar_detach(&_local_cv); + return RT_EOK; +} + +static void testcase(void) +{ + UTEST_UNIT_RUN(condvar_timedwait_tc); +} +UTEST_TC_EXPORT(testcase, "testcases.ipc.condvar.timedwait", utest_tc_init, utest_tc_cleanup, 10); diff --git a/include/rtdef.h b/include/rtdef.h index 47e02b3e9ea..e524800f439 100644 --- a/include/rtdef.h +++ b/include/rtdef.h @@ -53,6 +53,8 @@ * 2023-10-10 Chushicheng change version number to v5.1.0 * 2023-10-11 zmshahaha move specific devices related and driver to components/drivers * 2023-11-21 Meco Man add RT_USING_NANO macro + * 2023-11-17 xqyjlj add process group and session support + * 2023-12-01 Shell Support of dynamic device * 2023-12-18 xqyjlj add rt_always_inline * 2023-12-22 Shell Support hook list * 2024-01-18 Shell Seperate basical types to a rttypes.h @@ -181,7 +183,8 @@ typedef int (*init_fn_t)(void); /* init platform, user code... */ #define INIT_PLATFORM_EXPORT(fn) INIT_EXPORT(fn, "1.2") /* init sys-timer, clk, pinctrl... */ -#define INIT_SUBSYS_EXPORT(fn) INIT_EXPORT(fn, "1.3") +#define INIT_SUBSYS_EARLY_EXPORT(fn) INIT_EXPORT(fn, "1.3.0") +#define INIT_SUBSYS_EXPORT(fn) INIT_EXPORT(fn, "1.3.1") /* init early drivers */ #define INIT_DRIVER_EARLY_EXPORT(fn) INIT_EXPORT(fn, "1.4") @@ -384,8 +387,10 @@ enum rt_object_class_type RT_Object_Class_Module = 0x0b, /**< The object is a module. */ RT_Object_Class_Memory = 0x0c, /**< The object is a memory. */ RT_Object_Class_Channel = 0x0d, /**< The object is a channel */ - RT_Object_Class_Custom = 0x0e, /**< The object is a custom object */ - RT_Object_Class_Unknown = 0x0f, /**< The object is unknown. */ + RT_Object_Class_ProcessGroup = 0x0e, /**< The object is a process group */ + RT_Object_Class_Session = 0x0f, /**< The object is a session */ + RT_Object_Class_Custom = 0x10, /**< The object is a custom object */ + RT_Object_Class_Unknown = 0x11, /**< The object is unknown. */ RT_Object_Class_Static = 0x80 /**< The object is a static object. */ }; @@ -521,23 +526,23 @@ struct rt_object_information * do_other_things(); * } */ -#define _RT_OBJECT_HOOKLIST_CALL(nodetype, nested, list, lock, argv) \ - do \ - { \ - nodetype iter; \ - rt_ubase_t level = rt_spin_lock_irqsave(&lock); \ - nested += 1; \ - rt_spin_unlock_irqrestore(&lock, level); \ - if (!rt_list_isempty(&list)) \ - { \ - rt_list_for_each_entry(iter, &list, list_node) \ - { \ - iter->handler argv; \ - } \ - } \ - level = rt_spin_lock_irqsave(&lock); \ - nested -= 1; \ - rt_spin_unlock_irqrestore(&lock, level); \ +#define _RT_OBJECT_HOOKLIST_CALL(nodetype, nested, list, lock, argv) \ + do \ + { \ + nodetype iter, next; \ + rt_ubase_t level = rt_spin_lock_irqsave(&lock); \ + nested += 1; \ + rt_spin_unlock_irqrestore(&lock, level); \ + if (!rt_list_isempty(&list)) \ + { \ + rt_list_for_each_entry_safe(iter, next, &list, list_node) \ + { \ + iter->handler argv; \ + } \ + } \ + level = rt_spin_lock_irqsave(&lock); \ + nested -= 1; \ + rt_spin_unlock_irqrestore(&lock, level); \ } while (0) #define RT_OBJECT_HOOKLIST_CALL(name, argv) \ _RT_OBJECT_HOOKLIST_CALL(name##_hooklistnode_t, name##_nested, \ @@ -564,13 +569,14 @@ struct rt_object_information */ #define RT_TIMER_FLAG_DEACTIVATED 0x0 /**< timer is deactive */ #define RT_TIMER_FLAG_ACTIVATED 0x1 /**< timer is active */ +#define RT_TIMER_FLAG_PROCESSING 0x2 /**< timer's timeout fuction is processing */ #define RT_TIMER_FLAG_ONE_SHOT 0x0 /**< one shot timer */ -#define RT_TIMER_FLAG_PERIODIC 0x2 /**< periodic timer */ +#define RT_TIMER_FLAG_PERIODIC 0x4 /**< periodic timer */ #define RT_TIMER_FLAG_HARD_TIMER 0x0 /**< hard timer,the timer's callback function will be called in tick isr. */ -#define RT_TIMER_FLAG_SOFT_TIMER 0x4 /**< soft timer,the timer's callback function will be called in timer thread. */ +#define RT_TIMER_FLAG_SOFT_TIMER 0x8 /**< soft timer,the timer's callback function will be called in timer thread. */ #define RT_TIMER_FLAG_THREAD_TIMER \ - (0x8 | RT_TIMER_FLAG_HARD_TIMER) /**< thread timer that cooperates with scheduler directly */ + (0x10 | RT_TIMER_FLAG_HARD_TIMER) /**< thread timer that cooperates with scheduler directly */ #define RT_TIMER_CTRL_SET_TIME 0x0 /**< set timer control command */ #define RT_TIMER_CTRL_GET_TIME 0x1 /**< get timer control command */ @@ -794,17 +800,30 @@ struct lwp_sigaction { void (*sa_restorer)(void); }; +typedef struct lwp_siginfo_ext { + union { + /* for SIGCHLD */ + struct { + int status; + clock_t utime; + clock_t stime; + } sigchld; + }; +} *lwp_siginfo_ext_t; + typedef struct lwp_siginfo { rt_list_t node; struct { int signo; int code; - long value; int from_tid; pid_t from_pid; } ksiginfo; + + /* the signal specified extension field */ + struct lwp_siginfo_ext *ext; } *lwp_siginfo_t; typedef struct lwp_sigqueue { @@ -1238,6 +1257,7 @@ enum rt_device_class_type #define RT_DEVICE_FLAG_ACTIVATED 0x010 /**< device is activated */ #define RT_DEVICE_FLAG_SUSPENDED 0x020 /**< device is suspended */ #define RT_DEVICE_FLAG_STREAM 0x040 /**< stream mode */ +#define RT_DEVICE_FLAG_DYNAMIC 0x080 /**< device is determined when open() */ #define RT_DEVICE_FLAG_INT_RX 0x100 /**< INT mode on Rx */ #define RT_DEVICE_FLAG_DMA_RX 0x200 /**< DMA mode on Rx */ @@ -1352,6 +1372,9 @@ struct rt_device struct rt_wqueue wait_queue; #endif /* RT_USING_POSIX_DEVIO */ + rt_err_t (*readlink) + (rt_device_t dev, char *buf, int len); /**< for dynamic device */ + void *user_data; /**< device private data */ }; diff --git a/include/rthw.h b/include/rthw.h index 2d5bbd09e2c..1b4380c479c 100644 --- a/include/rthw.h +++ b/include/rthw.h @@ -132,6 +132,9 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name); +void rt_hw_interrupt_uninstall(int vector, + rt_isr_handler_t handler, + void *param); #ifdef RT_USING_SMP rt_base_t rt_hw_local_irq_disable(void); diff --git a/include/rtthread.h b/include/rtthread.h index 696f117de08..55f57a21188 100644 --- a/include/rtthread.h +++ b/include/rtthread.h @@ -828,20 +828,12 @@ do \ { \ if (need_check) \ { \ - rt_bool_t interrupt_disabled; \ - interrupt_disabled = rt_hw_interrupt_is_disabled(); \ if (rt_critical_level() != 0) \ { \ rt_kprintf("Function[%s]: scheduler is not available\n", \ __FUNCTION__); \ RT_ASSERT(0) \ } \ - if (interrupt_disabled == RT_TRUE) \ - { \ - rt_kprintf("Function[%s]: interrupt is disabled\n", \ - __FUNCTION__); \ - RT_ASSERT(0) \ - } \ RT_DEBUG_IN_THREAD_CONTEXT; \ } \ } \ diff --git a/include/rttypes.h b/include/rttypes.h index 9e21ba3170d..bce316e3978 100644 --- a/include/rttypes.h +++ b/include/rttypes.h @@ -79,15 +79,15 @@ typedef rt_ubase_t rt_dev_t; /**< Type for device */ typedef rt_base_t rt_off_t; /**< Type for offset */ #ifdef __cplusplus -typedef rt_base_t rt_atomic_t; +typedef rt_ubase_t rt_atomic_t; #else #if defined(RT_USING_HW_ATOMIC) -typedef rt_base_t rt_atomic_t; +typedef rt_ubase_t rt_atomic_t; #elif defined(RT_USING_STDC_ATOMIC) #include -typedef atomic_size_t rt_atomic_t; + typedef atomic_intptr_t rt_atomic_t; #else -typedef rt_base_t rt_atomic_t; +typedef rt_ubase_t rt_atomic_t; #endif /* RT_USING_STDC_ATOMIC */ #endif /* __cplusplus */ @@ -215,6 +215,9 @@ struct rt_spinlock struct rt_spinlock { +#ifdef RT_USING_DEBUG + rt_uint32_t critical_level; +#endif /* RT_USING_DEBUG */ rt_ubase_t lock; }; #define RT_SPINLOCK_INIT {0} diff --git a/libcpu/Kconfig b/libcpu/Kconfig index 5d36b7f51e3..200c2f62958 100644 --- a/libcpu/Kconfig +++ b/libcpu/Kconfig @@ -54,6 +54,10 @@ config ARCH_ARM_CORTEX_M bool select ARCH_ARM +config ARCH_ARM_CORTEX_R + bool + select ARCH_ARM + config ARCH_ARM_CORTEX_FPU bool @@ -109,6 +113,10 @@ config ARCH_ARM_CORTEX_R select ARCH_ARM select RT_USING_HW_ATOMIC +config ARCH_ARM_CORTEX_R52 + bool + select ARCH_ARM_CORTEX_R + config ARCH_ARM_MMU bool select RT_USING_CACHE diff --git a/libcpu/aarch64/common/SConscript b/libcpu/aarch64/common/SConscript index 7a36cad1adb..d66dfc6b0c2 100644 --- a/libcpu/aarch64/common/SConscript +++ b/libcpu/aarch64/common/SConscript @@ -12,8 +12,8 @@ if GetDepend('RT_USING_OFW') == False: SrcRemove(src, ['setup.c', 'cpu_psci.c', 'psci.c']) if GetDepend('RT_USING_PIC') == True: - SrcRemove(src, ['gicv3.c', 'gic.c', 'interrupt.c', 'gtimer.c']) - + SrcRemove(src, ['gicv3.c', 'gic.c', 'gtimer.c', 'interrupt.c']) + group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH) # build for sub-directory diff --git a/libcpu/aarch64/common/backtrace.c b/libcpu/aarch64/common/backtrace.c index 440d02d6fb9..0365ec71e47 100644 --- a/libcpu/aarch64/common/backtrace.c +++ b/libcpu/aarch64/common/backtrace.c @@ -85,7 +85,7 @@ rt_err_t rt_hw_backtrace_frame_unwind(rt_thread_t thread, struct rt_hw_backtrace if (fp && !((long)fp & 0x7)) { #ifdef RT_USING_SMART - if (thread && thread->lwp) + if (thread && thread->lwp && rt_scheduler_is_available()) { rt_lwp_t lwp = thread->lwp; void *this_lwp = lwp_self(); diff --git a/libcpu/aarch64/common/context_gcc.S b/libcpu/aarch64/common/context_gcc.S index bbd7e723710..c4254600291 100644 --- a/libcpu/aarch64/common/context_gcc.S +++ b/libcpu/aarch64/common/context_gcc.S @@ -19,6 +19,13 @@ #include "asm-fpu.h" #include "armv8.h" +#ifndef RT_USING_SMP +.section .data +rt_interrupt_from_thread: .zero 8 +rt_interrupt_to_thread: .zero 8 +rt_thread_switch_interrupt_flag: .zero 8 +#endif + .text .weak rt_hw_cpu_id_set .type rt_hw_cpu_id_set, @function @@ -314,6 +321,12 @@ rt_hw_interrupt_is_disabled: .globl rt_hw_interrupt_disable rt_hw_interrupt_disable: MRS X0, DAIF + AND X0, X0, #0xc0 + CMP X0, #0xc0 + /* branch if bits not both set(zero) */ + BNE 1f + RET +1: MSR DAIFSet, #3 DSB NSH ISB @@ -324,6 +337,12 @@ rt_hw_interrupt_disable: */ .globl rt_hw_interrupt_enable rt_hw_interrupt_enable: + AND X0, X0, #0xc0 + CMP X0, #0xc0 + /* branch if one of the bits not set(zero) */ + BNE 1f + RET +1: ISB DSB NSH AND X0, X0, #0xc0 @@ -439,7 +458,7 @@ rt_hw_context_switch_exit: MOV X0, SP RESTORE_CONTEXT -#else /* RT_USING_SMP */ +#else /* !RT_USING_SMP */ /* * void rt_hw_context_switch_to(rt_ubase_t to); diff --git a/libcpu/aarch64/common/gicv3.c b/libcpu/aarch64/common/gicv3.c index ba602b22581..6dbd572a224 100644 --- a/libcpu/aarch64/common/gicv3.c +++ b/libcpu/aarch64/common/gicv3.c @@ -41,125 +41,10 @@ extern rt_uint64_t rt_cpu_mpidr_early[]; #endif /* RT_USING_SMP */ -struct arm_gic -{ - rt_uint64_t offset; /* the first interrupt index in the vector table */ - rt_uint64_t redist_hw_base[ARM_GIC_CPU_NUM]; /* the pointer of the gic redistributor */ - rt_uint64_t dist_hw_base; /* the base address of the gic distributor */ - rt_uint64_t cpu_hw_base[ARM_GIC_CPU_NUM]; /* the base address of the gic cpu interface */ -}; - /* 'ARM_GIC_MAX_NR' is the number of cores */ static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; static unsigned int _gic_max_irq; -#define GET_GICV3_REG(reg, out) __asm__ volatile ("mrs %0, " reg:"=r"(out)::"memory"); -#define SET_GICV3_REG(reg, in) __asm__ volatile ("msr " reg ", %0"::"r"(in):"memory"); - -/* AArch64 System register interface to GICv3 */ -#define ICC_IAR0_EL1 "S3_0_C12_C8_0" -#define ICC_IAR1_EL1 "S3_0_C12_C12_0" -#define ICC_EOIR0_EL1 "S3_0_C12_C8_1" -#define ICC_EOIR1_EL1 "S3_0_C12_C12_1" -#define ICC_HPPIR0_EL1 "S3_0_C12_C8_2" -#define ICC_HPPIR1_EL1 "S3_0_C12_C12_2" -#define ICC_BPR0_EL1 "S3_0_C12_C8_3" -#define ICC_BPR1_EL1 "S3_0_C12_C12_3" -#define ICC_DIR_EL1 "S3_0_C12_C11_1" -#define ICC_PMR_EL1 "S3_0_C4_C6_0" -#define ICC_RPR_EL1 "S3_0_C12_C11_3" -#define ICC_CTLR_EL1 "S3_0_C12_C12_4" -#define ICC_CTLR_EL3 "S3_6_C12_C12_4" -#define ICC_SRE_EL1 "S3_0_C12_C12_5" -#define ICC_SRE_EL2 "S3_4_C12_C9_5" -#define ICC_SRE_EL3 "S3_6_C12_C12_5" -#define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6" -#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7" -#define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7" -#define ICC_SGI0R_EL1 "S3_0_C12_C11_7" -#define ICC_SGI1R_EL1 "S3_0_C12_C11_5" -#define ICC_ASGI1R_EL1 "S3_0_C12_C11_6" - -/* Macro to access the Distributor Control Register (GICD_CTLR) */ -#define GICD_CTLR_RWP (1U << 31) -#define GICD_CTLR_E1NWF (1U << 7) -#define GICD_CTLR_DS (1U << 6) -#define GICD_CTLR_ARE_NS (1U << 5) -#define GICD_CTLR_ARE_S (1U << 4) -#define GICD_CTLR_ENGRP1S (1U << 2) -#define GICD_CTLR_ENGRP1NS (1U << 1) -#define GICD_CTLR_ENGRP0 (1U << 0) - -/* Macro to access the Redistributor Control Register (GICR_CTLR) */ -#define GICR_CTLR_UWP (1U << 31) -#define GICR_CTLR_DPG1S (1U << 26) -#define GICR_CTLR_DPG1NS (1U << 25) -#define GICR_CTLR_DPG0 (1U << 24) -#define GICR_CTLR_RWP (1U << 3) -#define GICR_CTLR_IR (1U << 2) -#define GICR_CTLR_CES (1U << 1) -#define GICR_CTLR_EnableLPI (1U << 0) - -/* Macro to access the Generic Interrupt Controller Interface (GICC) */ -#define GIC_CPU_CTRL(hw_base) HWREG32((hw_base) + 0x00U) -#define GIC_CPU_PRIMASK(hw_base) HWREG32((hw_base) + 0x04U) -#define GIC_CPU_BINPOINT(hw_base) HWREG32((hw_base) + 0x08U) -#define GIC_CPU_INTACK(hw_base) HWREG32((hw_base) + 0x0cU) -#define GIC_CPU_EOI(hw_base) HWREG32((hw_base) + 0x10U) -#define GIC_CPU_RUNNINGPRI(hw_base) HWREG32((hw_base) + 0x14U) -#define GIC_CPU_HIGHPRI(hw_base) HWREG32((hw_base) + 0x18U) -#define GIC_CPU_IIDR(hw_base) HWREG32((hw_base) + 0xFCU) - -/* Macro to access the Generic Interrupt Controller Distributor (GICD) */ -#define GIC_DIST_CTRL(hw_base) HWREG32((hw_base) + 0x000U) -#define GIC_DIST_TYPE(hw_base) HWREG32((hw_base) + 0x004U) -#define GIC_DIST_IIDR(hw_base) HWREG32((hw_base) + 0x008U) -#define GIC_DIST_IGROUP(hw_base, n) HWREG32((hw_base) + 0x080U + ((n) / 32U) * 4U) -#define GIC_DIST_ENABLE_SET(hw_base, n) HWREG32((hw_base) + 0x100U + ((n) / 32U) * 4U) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) HWREG32((hw_base) + 0x180U + ((n) / 32U) * 4U) -#define GIC_DIST_PENDING_SET(hw_base, n) HWREG32((hw_base) + 0x200U + ((n) / 32U) * 4U) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) HWREG32((hw_base) + 0x280U + ((n) / 32U) * 4U) -#define GIC_DIST_ACTIVE_SET(hw_base, n) HWREG32((hw_base) + 0x300U + ((n) / 32U) * 4U) -#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) HWREG32((hw_base) + 0x380U + ((n) / 32U) * 4U) -#define GIC_DIST_PRI(hw_base, n) HWREG32((hw_base) + 0x400U + ((n) / 4U) * 4U) -#define GIC_DIST_TARGET(hw_base, n) HWREG32((hw_base) + 0x800U + ((n) / 4U) * 4U) -#define GIC_DIST_CONFIG(hw_base, n) HWREG32((hw_base) + 0xc00U + ((n) / 16U) * 4U) -#define GIC_DIST_SOFTINT(hw_base) HWREG32((hw_base) + 0xf00U) -#define GIC_DIST_CPENDSGI(hw_base, n) HWREG32((hw_base) + 0xf10U + ((n) / 4U) * 4U) -#define GIC_DIST_SPENDSGI(hw_base, n) HWREG32((hw_base) + 0xf20U + ((n) / 4U) * 4U) -#define GIC_DIST_ICPIDR2(hw_base) HWREG32((hw_base) + 0xfe8U) -#define GIC_DIST_IROUTER(hw_base, n) HWREG64((hw_base) + 0x6000U + (n) * 8U) - -/* SGI base address is at 64K offset from Redistributor base address */ -#define GIC_RSGI_OFFSET 0x10000 - -/* Macro to access the Generic Interrupt Controller Redistributor (GICR) */ -#define GIC_RDIST_CTRL(hw_base) HWREG32((hw_base) + 0x000U) -#define GIC_RDIST_IIDR(hw_base) HWREG32((hw_base) + 0x004U) -#define GIC_RDIST_TYPER(hw_base) HWREG64((hw_base) + 0x008U) -#define GIC_RDIST_TSTATUSR(hw_base) HWREG32((hw_base) + 0x010U) -#define GIC_RDIST_WAKER(hw_base) HWREG32((hw_base) + 0x014U) -#define GIC_RDIST_SETLPIR(hw_base) HWREG32((hw_base) + 0x040U) -#define GIC_RDIST_CLRLPIR(hw_base) HWREG32((hw_base) + 0x048U) -#define GIC_RDIST_PROPBASER(hw_base) HWREG32((hw_base) + 0x070U) -#define GIC_RDIST_PENDBASER(hw_base) HWREG32((hw_base) + 0x078U) -#define GIC_RDIST_INVLPIR(hw_base) HWREG32((hw_base) + 0x0A0U) -#define GIC_RDIST_INVALLR(hw_base) HWREG32((hw_base) + 0x0B0U) -#define GIC_RDIST_SYNCR(hw_base) HWREG32((hw_base) + 0x0C0U) - -#define GIC_RDISTSGI_IGROUPR0(hw_base, n) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n) * 4U) -#define GIC_RDISTSGI_ISENABLER0(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x100U) -#define GIC_RDISTSGI_ICENABLER0(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) -#define GIC_RDISTSGI_ISPENDR0(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x200U) -#define GIC_RDISTSGI_ICPENDR0(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x280U) -#define GIC_RDISTSGI_ISACTIVER0(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x300U) -#define GIC_RDISTSGI_ICACTIVER0(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x380U) -#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U) -#define GIC_RDISTSGI_ICFGR0(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U) -#define GIC_RDISTSGI_ICFGR1(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U) -#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n) * 4) -#define GIC_RDISTSGI_NSACR(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U) - int arm_gic_get_active_irq(rt_uint64_t index) { rt_base_t irq; @@ -939,6 +824,11 @@ static void arm_gic_bind_dump(void) #endif /* BSP_USING_GICV3 */ } +rt_uint64_t *arm_gic_get_gic_table_addr(void) +{ + return (rt_uint64_t *)&_gic_table[0]; +} + static void arm_gic_sgi_dump(rt_uint64_t index) { rt_int32_t cpu_id = rt_hw_cpu_id(); diff --git a/libcpu/aarch64/common/gicv3.h b/libcpu/aarch64/common/gicv3.h index ff821c42195..d449774c5fe 100644 --- a/libcpu/aarch64/common/gicv3.h +++ b/libcpu/aarch64/common/gicv3.h @@ -25,6 +25,120 @@ #define GICV3_ROUTED_TO_ALL 1UL #define GICV3_ROUTED_TO_SPEC 0UL +#define GET_GICV3_REG(reg, out) __asm__ volatile ("mrs %0, " reg:"=r"(out)::"memory"); +#define SET_GICV3_REG(reg, in) __asm__ volatile ("msr " reg ", %0"::"r"(in):"memory"); + +/* AArch64 System register interface to GICv3 */ +#define ICC_IAR0_EL1 "S3_0_C12_C8_0" +#define ICC_IAR1_EL1 "S3_0_C12_C12_0" +#define ICC_EOIR0_EL1 "S3_0_C12_C8_1" +#define ICC_EOIR1_EL1 "S3_0_C12_C12_1" +#define ICC_HPPIR0_EL1 "S3_0_C12_C8_2" +#define ICC_HPPIR1_EL1 "S3_0_C12_C12_2" +#define ICC_BPR0_EL1 "S3_0_C12_C8_3" +#define ICC_BPR1_EL1 "S3_0_C12_C12_3" +#define ICC_DIR_EL1 "S3_0_C12_C11_1" +#define ICC_PMR_EL1 "S3_0_C4_C6_0" +#define ICC_RPR_EL1 "S3_0_C12_C11_3" +#define ICC_CTLR_EL1 "S3_0_C12_C12_4" +#define ICC_CTLR_EL3 "S3_6_C12_C12_4" +#define ICC_SRE_EL1 "S3_0_C12_C12_5" +#define ICC_SRE_EL2 "S3_4_C12_C9_5" +#define ICC_SRE_EL3 "S3_6_C12_C12_5" +#define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6" +#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7" +#define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7" +#define ICC_SGI0R_EL1 "S3_0_C12_C11_7" +#define ICC_SGI1R_EL1 "S3_0_C12_C11_5" +#define ICC_ASGI1R_EL1 "S3_0_C12_C11_6" + +/* Macro to access the Distributor Control Register (GICD_CTLR) */ +#define GICD_CTLR_RWP (1U << 31) +#define GICD_CTLR_E1NWF (1U << 7) +#define GICD_CTLR_DS (1U << 6) +#define GICD_CTLR_ARE_NS (1U << 5) +#define GICD_CTLR_ARE_S (1U << 4) +#define GICD_CTLR_ENGRP1S (1U << 2) +#define GICD_CTLR_ENGRP1NS (1U << 1) +#define GICD_CTLR_ENGRP0 (1U << 0) + +/* Macro to access the Redistributor Control Register (GICR_CTLR) */ +#define GICR_CTLR_UWP (1U << 31) +#define GICR_CTLR_DPG1S (1U << 26) +#define GICR_CTLR_DPG1NS (1U << 25) +#define GICR_CTLR_DPG0 (1U << 24) +#define GICR_CTLR_RWP (1U << 3) +#define GICR_CTLR_IR (1U << 2) +#define GICR_CTLR_CES (1U << 1) +#define GICR_CTLR_EnableLPI (1U << 0) + +/* Macro to access the Generic Interrupt Controller Interface (GICC) */ +#define GIC_CPU_CTRL(hw_base) HWREG32((hw_base) + 0x00U) +#define GIC_CPU_PRIMASK(hw_base) HWREG32((hw_base) + 0x04U) +#define GIC_CPU_BINPOINT(hw_base) HWREG32((hw_base) + 0x08U) +#define GIC_CPU_INTACK(hw_base) HWREG32((hw_base) + 0x0cU) +#define GIC_CPU_EOI(hw_base) HWREG32((hw_base) + 0x10U) +#define GIC_CPU_RUNNINGPRI(hw_base) HWREG32((hw_base) + 0x14U) +#define GIC_CPU_HIGHPRI(hw_base) HWREG32((hw_base) + 0x18U) +#define GIC_CPU_IIDR(hw_base) HWREG32((hw_base) + 0xFCU) + +/* Macro to access the Generic Interrupt Controller Distributor (GICD) */ +#define GIC_DIST_CTRL(hw_base) HWREG32((hw_base) + 0x000U) +#define GIC_DIST_TYPE(hw_base) HWREG32((hw_base) + 0x004U) +#define GIC_DIST_IIDR(hw_base) HWREG32((hw_base) + 0x008U) +#define GIC_DIST_IGROUP(hw_base, n) HWREG32((hw_base) + 0x080U + ((n) / 32U) * 4U) +#define GIC_DIST_ENABLE_SET(hw_base, n) HWREG32((hw_base) + 0x100U + ((n) / 32U) * 4U) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) HWREG32((hw_base) + 0x180U + ((n) / 32U) * 4U) +#define GIC_DIST_PENDING_SET(hw_base, n) HWREG32((hw_base) + 0x200U + ((n) / 32U) * 4U) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) HWREG32((hw_base) + 0x280U + ((n) / 32U) * 4U) +#define GIC_DIST_ACTIVE_SET(hw_base, n) HWREG32((hw_base) + 0x300U + ((n) / 32U) * 4U) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) HWREG32((hw_base) + 0x380U + ((n) / 32U) * 4U) +#define GIC_DIST_PRI(hw_base, n) HWREG32((hw_base) + 0x400U + ((n) / 4U) * 4U) +#define GIC_DIST_TARGET(hw_base, n) HWREG32((hw_base) + 0x800U + ((n) / 4U) * 4U) +#define GIC_DIST_CONFIG(hw_base, n) HWREG32((hw_base) + 0xc00U + ((n) / 16U) * 4U) +#define GIC_DIST_SOFTINT(hw_base) HWREG32((hw_base) + 0xf00U) +#define GIC_DIST_CPENDSGI(hw_base, n) HWREG32((hw_base) + 0xf10U + ((n) / 4U) * 4U) +#define GIC_DIST_SPENDSGI(hw_base, n) HWREG32((hw_base) + 0xf20U + ((n) / 4U) * 4U) +#define GIC_DIST_ICPIDR2(hw_base) HWREG32((hw_base) + 0xfe8U) +#define GIC_DIST_IROUTER(hw_base, n) HWREG64((hw_base) + 0x6000U + (n) * 8U) + +/* SGI base address is at 64K offset from Redistributor base address */ +#define GIC_RSGI_OFFSET 0x10000 + +/* Macro to access the Generic Interrupt Controller Redistributor (GICR) */ +#define GIC_RDIST_CTRL(hw_base) HWREG32((hw_base) + 0x000U) +#define GIC_RDIST_IIDR(hw_base) HWREG32((hw_base) + 0x004U) +#define GIC_RDIST_TYPER(hw_base) HWREG64((hw_base) + 0x008U) +#define GIC_RDIST_TSTATUSR(hw_base) HWREG32((hw_base) + 0x010U) +#define GIC_RDIST_WAKER(hw_base) HWREG32((hw_base) + 0x014U) +#define GIC_RDIST_SETLPIR(hw_base) HWREG32((hw_base) + 0x040U) +#define GIC_RDIST_CLRLPIR(hw_base) HWREG32((hw_base) + 0x048U) +#define GIC_RDIST_PROPBASER(hw_base) HWREG32((hw_base) + 0x070U) +#define GIC_RDIST_PENDBASER(hw_base) HWREG32((hw_base) + 0x078U) +#define GIC_RDIST_INVLPIR(hw_base) HWREG32((hw_base) + 0x0A0U) +#define GIC_RDIST_INVALLR(hw_base) HWREG32((hw_base) + 0x0B0U) +#define GIC_RDIST_SYNCR(hw_base) HWREG32((hw_base) + 0x0C0U) + +#define GIC_RDISTSGI_IGROUPR0(hw_base, n) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n) * 4U) +#define GIC_RDISTSGI_ISENABLER0(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x100U) +#define GIC_RDISTSGI_ICENABLER0(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) +#define GIC_RDISTSGI_ISPENDR0(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x200U) +#define GIC_RDISTSGI_ICPENDR0(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x280U) +#define GIC_RDISTSGI_ISACTIVER0(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x300U) +#define GIC_RDISTSGI_ICACTIVER0(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x380U) +#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U) +#define GIC_RDISTSGI_ICFGR0(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U) +#define GIC_RDISTSGI_ICFGR1(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U) +#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n) * 4) +#define GIC_RDISTSGI_NSACR(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U) + +struct arm_gic +{ + rt_uint64_t offset; /* the first interrupt index in the vector table */ + rt_uint64_t redist_hw_base[ARM_GIC_CPU_NUM]; /* the pointer of the gic redistributor */ + rt_uint64_t dist_hw_base; /* the base address of the gic distributor */ + rt_uint64_t cpu_hw_base[ARM_GIC_CPU_NUM]; /* the base address of the gic cpu interface */ +}; int arm_gic_get_active_irq(rt_uint64_t index); void arm_gic_ack(rt_uint64_t index, int irq); @@ -74,6 +188,7 @@ int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start); int arm_gic_redist_init(rt_uint64_t index, rt_uint64_t redist_base); int arm_gic_cpu_init(rt_uint64_t index, rt_uint64_t cpu_base); +rt_uint64_t *arm_gic_get_gic_table_addr(void); void arm_gic_dump_type(rt_uint64_t index); void arm_gic_dump(rt_uint64_t index); diff --git a/libcpu/aarch64/common/interrupt.c b/libcpu/aarch64/common/interrupt.c index 570859aee68..08ab57b515d 100644 --- a/libcpu/aarch64/common/interrupt.c +++ b/libcpu/aarch64/common/interrupt.c @@ -16,17 +16,9 @@ #include "gicv3.h" #include "ioremap.h" - /* exception and interrupt handler table */ struct rt_irq_desc isr_table[MAX_HANDLERS]; -#ifndef RT_USING_SMP -/* Those variables will be accessed in ISR, so we need to share them. */ -rt_ubase_t rt_interrupt_from_thread = 0; -rt_ubase_t rt_interrupt_to_thread = 0; -rt_ubase_t rt_thread_switch_interrupt_flag = 0; -#endif - #ifndef RT_CPUS_NR #define RT_CPUS_NR 1 #endif @@ -86,9 +78,6 @@ void rt_hw_interrupt_init(void) /* init interrupt nest, and context in thread sp */ rt_atomic_store(&rt_interrupt_nest, 0); - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; #else rt_uint64_t gic_cpu_base; rt_uint64_t gic_dist_base; @@ -138,17 +127,17 @@ void rt_hw_interrupt_mask(int vector) #ifdef SOC_BCM283x if (vector < 32) { - IRQ_DISABLE1 = (1 << vector); + IRQ_DISABLE1 = (1UL << vector); } else if (vector < 64) { vector = vector % 32; - IRQ_DISABLE2 = (1 << vector); + IRQ_DISABLE2 = (1UL << vector); } else { vector = vector - 64; - IRQ_DISABLE_BASIC = (1 << vector); + IRQ_DISABLE_BASIC = (1UL << vector); } #else arm_gic_mask(0, vector); @@ -164,17 +153,17 @@ void rt_hw_interrupt_umask(int vector) #ifdef SOC_BCM283x if (vector < 32) { - IRQ_ENABLE1 = (1 << vector); + IRQ_ENABLE1 = (1UL << vector); } else if (vector < 64) { vector = vector % 32; - IRQ_ENABLE2 = (1 << vector); + IRQ_ENABLE2 = (1UL << vector); } else { vector = vector - 64; - IRQ_ENABLE_BASIC = (1 << vector); + IRQ_ENABLE_BASIC = (1UL << vector); } #else arm_gic_umask(0, vector); diff --git a/libcpu/aarch64/common/mmu.c b/libcpu/aarch64/common/mmu.c index d870a73b0f0..9583b9d2078 100644 --- a/libcpu/aarch64/common/mmu.c +++ b/libcpu/aarch64/common/mmu.c @@ -602,7 +602,7 @@ static int _map_single_page_2M(unsigned long *lv0_tbl, unsigned long va, return 0; } -void *rt_hw_mmu_tbl_get() +void *rt_hw_mmu_tbl_get(void) { uintptr_t tbl; __asm__ volatile("MRS %0, TTBR0_EL1" : "=r"(tbl)); @@ -625,7 +625,9 @@ void *rt_ioremap_early(void *paddr, size_t size) tbl = rt_hw_mmu_tbl_get(); } - count = (size + ARCH_SECTION_MASK) >> ARCH_SECTION_SHIFT; + /* get the total size required including overhead for alignment */ + count = (size + ((rt_ubase_t)paddr & ARCH_SECTION_MASK) + + ARCH_SECTION_MASK) >> ARCH_SECTION_SHIFT; base = (rt_ubase_t)paddr & (~ARCH_SECTION_MASK); while (count --> 0) @@ -688,6 +690,7 @@ static unsigned long *_query(rt_aspace_t aspace, void *vaddr, int *plvl_shf) if (!(cur_lv_tbl[off] & MMU_TYPE_USED)) { + *plvl_shf = level_shift; return (void *)0; } @@ -707,11 +710,11 @@ static unsigned long *_query(rt_aspace_t aspace, void *vaddr, int *plvl_shf) off &= MMU_LEVEL_MASK; page = cur_lv_tbl[off]; + *plvl_shf = level_shift; if (!(page & MMU_TYPE_USED)) { return (void *)0; } - *plvl_shf = level_shift; return &cur_lv_tbl[off]; } diff --git a/libcpu/aarch64/common/setup.c b/libcpu/aarch64/common/setup.c index a7bcd260709..5afcebfe8f3 100644 --- a/libcpu/aarch64/common/setup.c +++ b/libcpu/aarch64/common/setup.c @@ -253,6 +253,7 @@ void rt_hw_common_setup(void) break; } + mem_region++; } } diff --git a/libcpu/aarch64/common/stack.c b/libcpu/aarch64/common/stack.c index 18d6271a794..c554ab077d3 100644 --- a/libcpu/aarch64/common/stack.c +++ b/libcpu/aarch64/common/stack.c @@ -31,7 +31,8 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, { rt_ubase_t *stk; - stk = (rt_ubase_t *)stack_addr; + /* The AAPCS64 requires 128-bit (16 byte) stack alignment */ + stk = (rt_ubase_t*)RT_ALIGN_DOWN((rt_ubase_t)stack_addr, 16); for (int i = 0; i < 32; ++i) { diff --git a/libcpu/aarch64/cortex-a/entry_point.S b/libcpu/aarch64/cortex-a/entry_point.S index e8634612e23..b93978ea6e7 100644 --- a/libcpu/aarch64/cortex-a/entry_point.S +++ b/libcpu/aarch64/cortex-a/entry_point.S @@ -69,7 +69,8 @@ _head: .quad 0 /* Reserved */ .ascii "ARM\x64" /* Magic number */ .long 0 /* Reserved (used for PE COFF offset) */ -#endif +#endif /* RT_USING_OFW */ + /* Variable registers: x21~x28 */ dtb_paddr .req x21 boot_arg0 .req x22 @@ -109,6 +110,7 @@ _start: /* Now we are in the end of boot cpu process */ ldr x8, =rtthread_startup b init_mmu_early + /* never come back */ kernel_start: /* jump to the PE's system entry */ @@ -172,12 +174,15 @@ init_cpu_el: lsr x0, x0, #2 and x0, x0, #3 + /* running at EL3? */ cmp x0, #3 bne .init_cpu_hyp + /* should never be executed, just for completeness. (EL3) */ mov x1, #(1 << 0) /* EL0 and EL1 are in Non-Secure state */ orr x1, x1, #(1 << 4) /* RES1 */ orr x1, x1, #(1 << 5) /* RES1 */ + /* bic x1, x1, #(1 << 7) disable Secure Monitor Call */ orr x1, x1, #(1 << 10) /* The next lower level is AArch64 */ msr scr_el3, x1 @@ -193,7 +198,8 @@ init_cpu_el: eret .init_cpu_hyp: - cmp x0, #2 /* EL1 = 0100 */ + /* running at EL2? */ + cmp x0, #2 /* EL2 = 0b10 */ bne .init_cpu_sys /* Enable CNTP for EL1 */ @@ -220,7 +226,6 @@ init_cpu_el: .init_cpu_sys: mrs x0, sctlr_el1 - orr x0, x0, #(1 << 12) /* Enable Instruction */ bic x0, x0, #(3 << 3) /* Disable SP Alignment check */ bic x0, x0, #(1 << 1) /* Disable Alignment check */ msr sctlr_el1, x0 @@ -299,7 +304,9 @@ enable_mmu_early: ldr x30, =kernel_start /* Set LR to kernel_start function, it's virtual addresses */ + /* Enable page table translation */ mrs x1, sctlr_el1 + orr x1, x1, #(1 << 12) /* Stage 1 instruction access Cacheability control */ orr x1, x1, #(1 << 2) /* Cacheable Normal memory in stage1 */ orr x1, x1, #(1 << 0) /* MMU Enable */ msr sctlr_el1, x1 diff --git a/libcpu/arm/cortex-a/pmu.c b/libcpu/arm/cortex-a/pmu.c index 4b62849a1ac..68abed4e199 100644 --- a/libcpu/arm/cortex-a/pmu.c +++ b/libcpu/arm/cortex-a/pmu.c @@ -21,4 +21,5 @@ void rt_hw_pmu_dump_feature(void) LOG_D("ARM PMU Implementor: %c, ID code: %02x, %d counters\n", reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f); RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f)); + RT_UNUSED(reg); } diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index 3b126a37743..2f6add6058d 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -260,6 +260,7 @@ enable_mmu_page_table_early: mcr p15, 0, r0, c7, c5, 6 /* bpiall */ mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x7 /* clear bit1~3 */ orr r0, #((1 << 12) | (1 << 11)) /* instruction cache, branch prediction */ orr r0, #((1 << 2) | (1 << 0)) /* data cache, mmu enable */ mcr p15, 0, r0, c1, c0, 0 diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c index fe7acce2a1c..6ec4c826d5c 100644 --- a/libcpu/arm/cortex-m7/cpu_cache.c +++ b/libcpu/arm/cortex-m7/cpu_cache.c @@ -17,6 +17,8 @@ /* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ #define L1CACHE_LINESIZE_BYTE (32) +#ifdef RT_USING_CACHE + void rt_hw_cpu_icache_enable(void) { SCB_EnableICache(); @@ -89,3 +91,6 @@ void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) RT_ASSERT(0); } } + +#endif /* RT_USING_CACHE */ + diff --git a/libcpu/arm/cortex-r52/SConscript b/libcpu/arm/cortex-r52/SConscript new file mode 100644 index 00000000000..b259a94c946 --- /dev/null +++ b/libcpu/arm/cortex-r52/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM in ['armcc', 'armclang']: + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM in ['gcc']: + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM in ['iccarm']: + src += Glob('*_iar.S') + +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/cortex-r52/armv8.h b/libcpu/arm/cortex-r52/armv8.h new file mode 100644 index 00000000000..797223ed35e --- /dev/null +++ b/libcpu/arm/cortex-r52/armv8.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#ifndef __ARMV8_H__ +#define __ARMV8_H__ + +/* the exception stack without VFP registers */ +struct rt_hw_exp_stack +{ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; +}; + +struct rt_hw_stack +{ + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; +}; + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define MONITORMODE 0x16 +#define ABORTMODE 0x17 +#define HYPMODE 0x1b +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define T_Bit (1<<5) +#define F_Bit (1<<6) +#define I_Bit (1<<7) +#define A_Bit (1<<8) +#define E_Bit (1<<9) +#define J_Bit (1<<24) + +#define PABT_EXCEPTION 0x1 +#define DABT_EXCEPTION 0x2 +#define UND_EXCEPTION 0x3 +#define SWI_EXCEPTION 0x4 +#define RESV_EXCEPTION 0xF + +void rt_hw_show_register(struct rt_hw_exp_stack *regs); + +#endif diff --git a/libcpu/arm/cortex-r52/backtrace.c b/libcpu/arm/cortex-r52/backtrace.c new file mode 100644 index 00000000000..ca7ec26138f --- /dev/null +++ b/libcpu/arm/cortex-r52/backtrace.c @@ -0,0 +1,545 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-29 Jesven the first version + */ + +#ifndef __ICCARM__ +#ifndef __CHECKER__ +#if !defined (__ARM_EABI__) +#warning Your compiler does not have EABI support. +#warning ARM unwind is known to compile only with EABI compilers. +#warning Change compiler or disable ARM_UNWIND option. +#elif (__GNUC__ == 4 && __GNUC_MINOR__ <= 2) && !defined(__clang__) +#warning Your compiler is too buggy; it is known to not compile ARM unwind support. +#warning Change compiler or disable ARM_UNWIND option. +#endif +#endif /* __CHECKER__ */ + +#include +#include +#include + +#define DBG_TAG "BACKTRACE" +#define DBG_LVL DBG_INFO +#include + +#ifdef RT_USING_SMART +#include +#include +#include +#endif + +rt_inline void arm_get_current_stackframe(struct pt_regs *regs, struct stackframe *frame) +{ + frame->fp = frame_pointer(regs); + frame->sp = regs->ARM_sp; + frame->lr = regs->ARM_lr; + frame->pc = regs->ARM_pc; +} + +struct unwind_ctrl_block { + unsigned long vrs[16]; /* virtual register set */ + const unsigned long *insn; /* pointer to the current instructions word */ + unsigned long sp_high; /* highest value of sp allowed */ + /* + * 1 : check for stack overflow for each register pop. + * 0 : save overhead if there is plenty of stack remaining. + */ + int check_each_pop; + int entries; /* number of entries left to interpret */ + int byte; /* current byte number in the instructions word */ +}; + +enum regs +{ +#ifdef CONFIG_THUMB2_KERNEL + FP = 7, +#else + FP = 11, +#endif + SP = 13, + LR = 14, + PC = 15 +}; + +static int core_kernel_text(unsigned long addr) +{ + return 1; +} + +/* Convert a prel31 symbol to an absolute address */ +#define prel31_to_addr(ptr) \ + ({ \ + /* sign-extend to 32 bits */ \ + long offset = (((long)*(ptr)) << 1) >> 1; \ + (unsigned long)(ptr) + offset; \ + }) + +/* + * Binary search in the unwind index. The entries are + * guaranteed to be sorted in ascending order by the linker. + * + * start = first entry + * origin = first entry with positive offset (or stop if there is no such entry) + * stop - 1 = last entry + */ +static const struct unwind_idx *search_index(unsigned long addr, + const struct unwind_idx *start, + const struct unwind_idx *origin, + const struct unwind_idx *stop) +{ + unsigned long addr_prel31; + + LOG_D("%s(%08lx, %x, %x, %x)", + __func__, addr, start, origin, stop); + + /* + * only search in the section with the matching sign. This way the + * prel31 numbers can be compared as unsigned longs. + */ + if (addr < (unsigned long)start) + /* negative offsets: [start; origin) */ + stop = origin; + else + /* positive offsets: [origin; stop) */ + start = origin; + + /* prel31 for address relavive to start */ + addr_prel31 = (addr - (unsigned long)start) & 0x7fffffff; + + while (start < stop - 1) + { + const struct unwind_idx *mid = start + ((stop - start) >> 1); + + /* + * As addr_prel31 is relative to start an offset is needed to + * make it relative to mid. + */ + if (addr_prel31 - ((unsigned long)mid - (unsigned long)start) < + mid->addr_offset) + stop = mid; + else + { + /* keep addr_prel31 relative to start */ + addr_prel31 -= ((unsigned long)mid - + (unsigned long)start); + start = mid; + } + } + + if (start->addr_offset <= addr_prel31) + return start; + else + { + LOG_W("unwind: Unknown symbol address %08lx", addr); + return RT_NULL; + } +} + +static const struct unwind_idx *unwind_find_origin( + const struct unwind_idx *start, const struct unwind_idx *stop) +{ + LOG_D("%s(%x, %x)", __func__, start, stop); + while (start < stop) + { + const struct unwind_idx *mid = start + ((stop - start) >> 1); + + if (mid->addr_offset >= 0x40000000) + /* negative offset */ + start = mid + 1; + else + /* positive offset */ + stop = mid; + } + LOG_D("%s -> %x", __func__, stop); + return stop; +} + +static const struct unwind_idx *unwind_find_idx(unsigned long addr, const struct unwind_idx **origin_idx, const struct unwind_idx exidx_start[], const struct unwind_idx exidx_end[]) +{ + const struct unwind_idx *idx = RT_NULL; + + LOG_D("%s(%08lx)", __func__, addr); + + if (core_kernel_text(addr)) + { + if (!*origin_idx) + *origin_idx = + unwind_find_origin(exidx_start, + exidx_end); + + /* main unwind table */ + idx = search_index(addr, exidx_start, + *origin_idx, + exidx_end); + } + + LOG_D("%s: idx = %x", __func__, idx); + return idx; +} + +static unsigned long unwind_get_byte(struct unwind_ctrl_block *ctrl) +{ + unsigned long ret; + + if (ctrl->entries <= 0) + { + LOG_W("unwind: Corrupt unwind table"); + return 0; + } + + ret = (*ctrl->insn >> (ctrl->byte * 8)) & 0xff; + + if (ctrl->byte == 0) + { + ctrl->insn++; + ctrl->entries--; + ctrl->byte = 3; + } + else + ctrl->byte--; + + return ret; +} + +/* Before poping a register check whether it is feasible or not */ +static int unwind_pop_register(struct unwind_ctrl_block *ctrl, + unsigned long **vsp, unsigned int reg) +{ + if (ctrl->check_each_pop) + if (*vsp >= (unsigned long *)ctrl->sp_high) + return -URC_FAILURE; + + ctrl->vrs[reg] = *(*vsp)++; + return URC_OK; +} + +/* Helper functions to execute the instructions */ +static int unwind_exec_pop_subset_r4_to_r13(struct unwind_ctrl_block *ctrl, + unsigned long mask) +{ + unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; + int load_sp, reg = 4; + + load_sp = mask & (1 << (13 - 4)); + while (mask) + { + if (mask & 1) + if (unwind_pop_register(ctrl, &vsp, reg)) + return -URC_FAILURE; + mask >>= 1; + reg++; + } + if (!load_sp) + ctrl->vrs[SP] = (unsigned long)vsp; + + return URC_OK; +} + +static int unwind_exec_pop_r4_to_rN(struct unwind_ctrl_block *ctrl, + unsigned long insn) +{ + unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; + int reg; + + /* pop R4-R[4+bbb] */ + for (reg = 4; reg <= 4 + (insn & 7); reg++) + if (unwind_pop_register(ctrl, &vsp, reg)) + return -URC_FAILURE; + + if (insn & 0x8) + if (unwind_pop_register(ctrl, &vsp, 14)) + return -URC_FAILURE; + + ctrl->vrs[SP] = (unsigned long)vsp; + + return URC_OK; +} + +static int unwind_exec_pop_subset_r0_to_r3(struct unwind_ctrl_block *ctrl, + unsigned long mask) +{ + unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; + int reg = 0; + + /* pop R0-R3 according to mask */ + while (mask) + { + if (mask & 1) + if (unwind_pop_register(ctrl, &vsp, reg)) + return -URC_FAILURE; + mask >>= 1; + reg++; + } + ctrl->vrs[SP] = (unsigned long)vsp; + + return URC_OK; +} + +/* + * Execute the current unwind instruction. + */ +static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) +{ + unsigned long insn = unwind_get_byte(ctrl); + int ret = URC_OK; + + LOG_D("%s: insn = %08lx", __func__, insn); + + if ((insn & 0xc0) == 0x00) + ctrl->vrs[SP] += ((insn & 0x3f) << 2) + 4; + else if ((insn & 0xc0) == 0x40) + ctrl->vrs[SP] -= ((insn & 0x3f) << 2) + 4; + else if ((insn & 0xf0) == 0x80) + { + unsigned long mask; + + insn = (insn << 8) | unwind_get_byte(ctrl); + mask = insn & 0x0fff; + if (mask == 0) + { + LOG_W("unwind: 'Refuse to unwind' instruction %04lx", + insn); + return -URC_FAILURE; + } + + ret = unwind_exec_pop_subset_r4_to_r13(ctrl, mask); + if (ret) + goto error; + } + else if ((insn & 0xf0) == 0x90 && + (insn & 0x0d) != 0x0d) + ctrl->vrs[SP] = ctrl->vrs[insn & 0x0f]; + else if ((insn & 0xf0) == 0xa0) + { + ret = unwind_exec_pop_r4_to_rN(ctrl, insn); + if (ret) + goto error; + } + else if (insn == 0xb0) + { + if (ctrl->vrs[PC] == 0) + ctrl->vrs[PC] = ctrl->vrs[LR]; + /* no further processing */ + ctrl->entries = 0; + } + else if (insn == 0xb1) + { + unsigned long mask = unwind_get_byte(ctrl); + + if (mask == 0 || mask & 0xf0) + { + LOG_W("unwind: Spare encoding %04lx", + (insn << 8) | mask); + return -URC_FAILURE; + } + + ret = unwind_exec_pop_subset_r0_to_r3(ctrl, mask); + if (ret) + goto error; + } + else if (insn == 0xb2) + { + unsigned long uleb128 = unwind_get_byte(ctrl); + + ctrl->vrs[SP] += 0x204 + (uleb128 << 2); + } + else + { + LOG_W("unwind: Unhandled instruction %02lx", insn); + return -URC_FAILURE; + } + + LOG_D("%s: fp = %08lx sp = %08lx lr = %08lx pc = %08lx", __func__, + ctrl->vrs[FP], ctrl->vrs[SP], ctrl->vrs[LR], ctrl->vrs[PC]); + +error: + return ret; +} + +#ifdef RT_BACKTRACE_FUNCTION_NAME +static char *unwind_get_function_name(void *address) +{ + uint32_t flag_word = *(uint32_t *)((char*)address - 4); + + if ((flag_word & 0xff000000) == 0xff000000) + { + return (char *)((char*)address - 4 - (flag_word & 0x00ffffff)); + } + return RT_NULL; +} +#endif + +/* + * Unwind a single frame starting with *sp for the symbol at *pc. It + * updates the *pc and *sp with the new values. + */ +int unwind_frame(struct stackframe *frame, const struct unwind_idx **origin_idx, const struct unwind_idx exidx_start[], const struct unwind_idx exidx_end[]) +{ + unsigned long low; + const struct unwind_idx *idx; + struct unwind_ctrl_block ctrl; + struct rt_thread *rt_c_thread; + + /* store the highest address on the stack to avoid crossing it*/ + low = frame->sp; + rt_c_thread = rt_thread_self(); + ctrl.sp_high = (unsigned long)((char*)rt_c_thread->stack_addr + rt_c_thread->stack_size); + + LOG_D("%s(pc = %08lx lr = %08lx sp = %08lx)", __func__, + frame->pc, frame->lr, frame->sp); + + idx = unwind_find_idx(frame->pc, origin_idx, exidx_start, exidx_end); + if (!idx) + { + LOG_W("unwind: Index not found %08lx", frame->pc); + return -URC_FAILURE; + } + +#ifdef RT_BACKTRACE_FUNCTION_NAME + { + char *fun_name; + fun_name = unwind_get_function_name((void *)prel31_to_addr(&idx->addr_offset)); + if (fun_name) + { + rt_kprintf("0x%08x @ %s\n", frame->pc, fun_name); + } + } +#endif + + ctrl.vrs[FP] = frame->fp; + ctrl.vrs[SP] = frame->sp; + ctrl.vrs[LR] = frame->lr; + ctrl.vrs[PC] = 0; + + if (idx->insn == 1) + /* can't unwind */ + return -URC_FAILURE; + else if ((idx->insn & 0x80000000) == 0) + /* prel31 to the unwind table */ + ctrl.insn = (unsigned long *)prel31_to_addr(&idx->insn); + else if ((idx->insn & 0xff000000) == 0x80000000) + /* only personality routine 0 supported in the index */ + ctrl.insn = &idx->insn; + else + { + LOG_W("unwind: Unsupported personality routine %08lx in the index at %x", + idx->insn, idx); + return -URC_FAILURE; + } + + /* check the personality routine */ + if ((*ctrl.insn & 0xff000000) == 0x80000000) + { + ctrl.byte = 2; + ctrl.entries = 1; + } + else if ((*ctrl.insn & 0xff000000) == 0x81000000) + { + ctrl.byte = 1; + ctrl.entries = 1 + ((*ctrl.insn & 0x00ff0000) >> 16); + } + else + { + LOG_W("unwind: Unsupported personality routine %08lx at %x", + *ctrl.insn, ctrl.insn); + return -URC_FAILURE; + } + + ctrl.check_each_pop = 0; + + while (ctrl.entries > 0) + { + int urc; + if ((ctrl.sp_high - ctrl.vrs[SP]) < sizeof(ctrl.vrs)) + ctrl.check_each_pop = 1; + urc = unwind_exec_insn(&ctrl); + if (urc < 0) + return urc; + if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= ctrl.sp_high) + return -URC_FAILURE; + } + + if (ctrl.vrs[PC] == 0) + ctrl.vrs[PC] = ctrl.vrs[LR]; + + /* check for infinite loop */ + if (frame->pc == ctrl.vrs[PC]) + return -URC_FAILURE; + + frame->fp = ctrl.vrs[FP]; + frame->sp = ctrl.vrs[SP]; + frame->lr = ctrl.vrs[LR]; + frame->pc = ctrl.vrs[PC]; + + return URC_OK; +} + +void unwind_backtrace(struct pt_regs *regs, const struct unwind_idx exidx_start[], const struct unwind_idx exidx_end[]) +{ + struct stackframe frame; + const struct unwind_idx *origin_idx = RT_NULL; + + LOG_D("%s(regs = %x)", __func__, regs); + + arm_get_current_stackframe(regs, &frame); + +#ifndef RT_BACKTRACE_FUNCTION_NAME + rt_kprintf("please use: addr2line -e rtthread.elf -a -f %08x", frame.pc); +#endif + LOG_D("pc = %08x, sp = %08x", frame.pc, frame.sp); + + while (1) + { + int urc; + + urc = unwind_frame(&frame, &origin_idx, exidx_start, exidx_end); + if (urc < 0) + break; + //dump_backtrace_entry(where, frame.pc, frame.sp - 4); +#ifndef RT_BACKTRACE_FUNCTION_NAME + rt_kprintf(" %08x", frame.pc); +#endif + LOG_D("from: pc = %08x, frame = %08x", frame.pc, frame.sp - 4); + } + rt_kprintf("\n"); +} + +extern const struct unwind_idx __exidx_start[]; +extern const struct unwind_idx __exidx_end[]; + +void rt_unwind(struct rt_hw_exp_stack *regs, unsigned int pc_adj) +{ + struct pt_regs e_regs; + + e_regs.ARM_fp = regs->fp; + e_regs.ARM_sp = regs->sp; + e_regs.ARM_lr = regs->lr; + e_regs.ARM_pc = regs->pc - pc_adj; +#ifdef RT_USING_SMART + if (!lwp_user_accessable((void *)e_regs.ARM_pc, sizeof (void *))) + { + e_regs.ARM_pc = regs->lr - sizeof(void *); + } +#endif + rt_kprintf("backtrace:\n"); + unwind_backtrace(&e_regs, __exidx_start, __exidx_end); +} + +rt_err_t rt_backtrace(void) +{ + struct rt_hw_exp_stack regs; + + __asm volatile ("mov %0, fp":"=r"(regs.fp)); + __asm volatile ("mov %0, sp":"=r"(regs.sp)); + __asm volatile ("mov %0, lr":"=r"(regs.lr)); + __asm volatile ("mov %0, pc":"=r"(regs.pc)); + rt_unwind(®s, 8); + return RT_EOK; +} +#endif // (__ICCARM__) undefined diff --git a/libcpu/arm/cortex-r52/backtrace.h b/libcpu/arm/cortex-r52/backtrace.h new file mode 100644 index 00000000000..5e03c2afa77 --- /dev/null +++ b/libcpu/arm/cortex-r52/backtrace.h @@ -0,0 +1,83 @@ +#ifndef __BACKTRACE_H +#define __BACKTRACE_H + +#ifndef __ASSEMBLY__ +#include + +/* Unwind reason code according the the ARM EABI documents */ +enum unwind_reason_code +{ + URC_OK = 0, /* operation completed successfully */ + URC_CONTINUE_UNWIND = 8, + URC_FAILURE = 9 /* unspecified failure of some kind */ +}; + +struct unwind_idx +{ + unsigned long addr_offset; + unsigned long insn; +}; + +struct unwind_table +{ + const struct unwind_idx *start; + const struct unwind_idx *origin; + const struct unwind_idx *stop; + unsigned long begin_addr; + unsigned long end_addr; +}; + +struct stackframe +{ + /* + * FP member should hold R7 when CONFIG_THUMB2_KERNEL is enabled + * and R11 otherwise. + */ + unsigned long fp; + unsigned long sp; + unsigned long lr; + unsigned long pc; +}; + +struct pt_regs +{ + unsigned long uregs[18]; +}; + +#define ARM_cpsr uregs[16] +#define ARM_pc uregs[15] +#define ARM_lr uregs[14] +#define ARM_sp uregs[13] +#define ARM_ip uregs[12] +#define ARM_fp uregs[11] +#define ARM_r10 uregs[10] +#define ARM_r9 uregs[9] +#define ARM_r8 uregs[8] +#define ARM_r7 uregs[7] +#define ARM_r6 uregs[6] +#define ARM_r5 uregs[5] +#define ARM_r4 uregs[4] +#define ARM_r3 uregs[3] +#define ARM_r2 uregs[2] +#define ARM_r1 uregs[1] +#define ARM_r0 uregs[0] +#define ARM_ORIG_r0 uregs[17] + +#define instruction_pointer(regs) (regs)->ARM_pc + +#ifdef CONFIG_THUMB2_KERNEL +#define frame_pointer(regs) (regs)->ARM_r7 +#else +#define frame_pointer(regs) (regs)->ARM_fp +#endif + +int unwind_frame(struct stackframe *frame, const struct unwind_idx **origin_idx, const struct unwind_idx exidx_start[], const struct unwind_idx exidx_end[]); +void unwind_backtrace(struct pt_regs *regs, const struct unwind_idx exidx_start[], const struct unwind_idx exidx_end[]); + +void rt_unwind(struct rt_hw_exp_stack *regs, unsigned int pc_adj); +rt_err_t rt_backtrace(void); + +#endif /* !__ASSEMBLY__ */ + +#endif /* __BACKTRACE_H */ + diff --git a/libcpu/arm/cortex-r52/context_gcc.S b/libcpu/arm/cortex-r52/context_gcc.S new file mode 100644 index 00000000000..f02559ca45b --- /dev/null +++ b/libcpu/arm/cortex-r52/context_gcc.S @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-01 Wangyuqiang first version + */ + +/** + * @addtogroup cortex-r52 + */ +/*@{*/ + +//#include + + .text + .arm + .globl rt_thread_switch_interrupt_flag + .globl rt_interrupt_from_thread + .globl rt_interrupt_to_thread + .globl rt_interrupt_enter + .globl rt_interrupt_leave + .globl rt_hw_trap_irq + +/* + * rt_base_t rt_hw_interrupt_disable() + */ + .globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS r0, cpsr + CPSID IF + BX lr + +/* + * void rt_hw_interrupt_enable(rt_base_t level) + */ + .globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + MSR cpsr_c, r0 + BX lr + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) + * r0 --> from + * r1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + STMDB sp!, {lr} @ push pc (lr should be pushed in place of PC) + STMDB sp!, {r0-r12, lr} @ push lr & register file + + MRS r4, cpsr + TST lr, #0x01 + ORRNE r4, r4, #0x20 @ it's thumb code + + STMDB sp!, {r4} @ push cpsr + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + VMRS r4, fpexc + TST r4, #0x40000000 + BEQ __no_vfp_frame1 + VSTMDB sp!, {d0-d15} + VMRS r5, fpscr + @ TODO: add support for Common VFPv3. + @ Save registers like FPINST, FPINST2 + STMDB sp!, {r5} +__no_vfp_frame1: + STMDB sp!, {r4} +#endif + + STR sp, [r0] @ store sp in preempted tasks TCB + LDR sp, [r1] @ get new task stack pointer + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + LDMIA sp!, {r0} @ get fpexc + VMSR fpexc, r0 @ restore fpexc + TST r0, #0x40000000 + BEQ __no_vfp_frame2 + LDMIA sp!, {r1} @ get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame2: + #endif + + LDMIA sp!, {r4} @ pop new task cpsr to spsr + MSR spsr_cxsf, r4 + + LDMIA sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr + +/* + * void rt_hw_context_switch_to(rt_uint32 to) + * r0 --> to + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + LDR sp, [r0] @ get new task stack pointer + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + LDMIA sp!, {r0} @ get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_to + LDMIA sp!, {r1} @ get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_to: +#endif + + LDMIA sp!, {r4} @ pop new task cpsr to spsr + MSR spsr_cxsf, r4 + + LDMIA sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)@ + */ + + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 @ set rt_thread_switch_interrupt_flag to 1 + STR r3, [r2] + LDR r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread + + STR r0, [r2] +_reswitch: + LDR r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread + STR r1, [r2] + BX lr + + .globl IRQ_Handler +IRQ_Handler: + STMDB sp!, {r0-r12,lr} + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + VMRS r0, fpexc + TST r0, #0x40000000 + BEQ __no_vfp_frame_str_irq + VSTMDB sp!, {d0-d15} + VMRS r1, fpscr + @ TODO: add support for Common VFPv3. + @ Save registers like FPINST, FPINST2 + STMDB sp!, {r1} +__no_vfp_frame_str_irq: + STMDB sp!, {r0} +#endif + + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + @ if rt_thread_switch_interrupt_flag set, jump to + @ rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + LDMIA sp!, {r0} @ get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_ldr_irq + LDMIA sp!, {r1} @ get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_ldr_irq: +#endif + + LDMIA sp!, {r0-r12,lr} + SUBS pc, lr, #4 + +/* + * void rt_hw_context_switch_interrupt_do(rt_base_t flag) + */ + .globl rt_hw_context_switch_interrupt_do +rt_hw_context_switch_interrupt_do: + MOV r1, #0 @ clear flag + STR r1, [r0] + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + LDMIA sp!, {r0} @ get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_do1 + LDMIA sp!, {r1} @ get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_do1: +#endif + + LDMIA sp!, {r0-r12,lr} @ reload saved registers + STMDB sp, {r0-r3} @ save r0-r3. We will restore r0-r3 in the SVC + @ mode so there is no need to update SP. + SUB r1, sp, #16 @ save the right SP value in r1, so we could restore r0-r3. + SUB r2, lr, #4 @ save old task's pc to r2 + + MRS r3, spsr @ get cpsr of interrupt thread + + @ switch to SVC mode and no interrupt + CPSID IF, #0x13 + + STMDB sp!, {r2} @ push old task's pc + STMDB sp!, {r4-r12,lr} @ push old task's lr,r12-r4 + LDMIA r1!, {r4-r7} @ restore r0-r3 of the interrupted thread + STMDB sp!, {r4-r7} @ push old task's r3-r0. We don't need to push/pop them to + @ r0-r3 because we just want to transfer the data and don't + @ use them here. + STMDB sp!, {r3} @ push old task's cpsr + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + VMRS r0, fpexc + TST r0, #0x40000000 + BEQ __no_vfp_frame_do2 + VSTMDB sp!, {d0-d15} + VMRS r1, fpscr + @ TODO: add support for Common VFPv3. + @ Save registers like FPINST, FPINST2 + STMDB sp!, {r1} +__no_vfp_frame_do2: + STMDB sp!, {r0} +#endif + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] @ store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] @ get new task's stack pointer + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + LDMIA sp!, {r0} @ get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_do3 + LDMIA sp!, {r1} @ get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_do3: +#endif + + LDMIA sp!, {r4} @ pop new task's cpsr to spsr + MSR spsr_cxsf, r4 + + LDMIA sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr + diff --git a/libcpu/arm/cortex-r52/context_iar.S b/libcpu/arm/cortex-r52/context_iar.S new file mode 100644 index 00000000000..aca9f91a1b6 --- /dev/null +++ b/libcpu/arm/cortex-r52/context_iar.S @@ -0,0 +1,260 @@ +;/* +; * Copyright (c) 2006-2022, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-20 Bernard first version +; * 2011-07-22 Bernard added thumb mode porting +; * 2013-05-24 Grissiom port to CCS +; * 2013-05-26 Grissiom optimize for ARMv7 +; * 2013-10-20 Grissiom port to GCC +; * 2024-03-11 Wangyuqiang rzn2l adapt +; */ + + SECTION .text:CODE(2) + ARM + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_hw_trap_irq + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ + EXPORT rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS r0, CPSR + CPSID I + BX lr + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ + EXPORT rt_hw_interrupt_enable +rt_hw_interrupt_enable: + MSR CPSR_c, r0 + BX lr + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) +; * r0 --> from +; * r1 --> to +; */ + EXPORT rt_hw_context_switch +rt_hw_context_switch: + STMDB sp!, {lr} ; push pc (lr should be pushed in place of PC) + STMDB sp!, {r0-r12, lr} ; push lr & register file + + MRS r4, CPSR + TST lr, #0x01 + ;ORRNE r4, r4, #0x20 ; it's thumb code + CMP r4, #0 + BNE ne_label +ne_label: + ORR r4, r4, #0x20 + STMDB sp!, {r4} ; push cpsr + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + VMRS r4, fpexc + TST r4, #0x40000000 + BEQ __no_vfp_frame1 + VSTMDB sp!, {d0-d15} + VMRS r5, fpscr + ; TODO: add support for Common VFPv3. + ; Save registers like FPINST, FPINST2 + STMDB sp!, {r5} +__no_vfp_frame1: + STMDB sp!, {r4} +#endif + + STR sp, [r0] ; store sp in preempted tasks TCB + LDR sp, [r1] ; get new task stack pointer + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + LDMIA sp!, {r0} ;@ get fpexc + VMSR fpexc, r0 ;@ restore fpexc + TST r0, #0x40000000 + BEQ __no_vfp_frame2 + LDMIA sp!, {r1} ;@ get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame2: + #endif + + LDMIA sp!, {r4} ; pop new task cpsr to spsr + MSR spsr_cxsf, r4 + + LDMIA sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr + MOV lr, pc + STMIA sp!, {lr} + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to) +; * r0 --> to +; */ + EXPORT rt_hw_context_switch_to +rt_hw_context_switch_to: + LDR sp, [r0] ; get new task stack pointer + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + LDMIA sp!, {r0} @ get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_to + LDMIA sp!, {r1} @ get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_to: +#endif + + LDMIA sp!, {r4} ; pop new task cpsr to spsr + MSR spsr_cxsf, r4 + + LDMIA sp!, {r0-r12, lr, pc}^ + +;/* +; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)@ +; */ + + EXPORT rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1 + STR r3, [r2] + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + + STR r0, [r2] +_reswitch: + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + BX lr + + EXPORT IRQ_Handler +IRQ_Handler: + STMDB sp!, {r0-r12,lr} + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + VMRS r0, fpexc + TST r0, #0x40000000 + BEQ __no_vfp_frame_str_irq + VSTMDB sp!, {d0-d15} + VMRS r1, fpscr + ; TODO: add support for Common VFPv3. + ; Save registers like FPINST, FPINST2 + STMDB sp!, {r1} +__no_vfp_frame_str_irq: + STMDB sp!, {r0} +#endif + + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + LDMIA sp!, {r0} ; get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_ldr_irq + LDMIA sp!, {r1} ; get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_ldr_irq: +#endif + + LDMIA sp!, {r0-r12,lr} + SUBS pc, lr, #4 + +;/* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ + EXPORT rt_hw_context_switch_interrupt_do +rt_hw_context_switch_interrupt_do: + MOV r1, #0 ; clear flag + STR r1, [r0] + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + LDMIA sp!, {r0} ; get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_do1 + LDMIA sp!, {r1} ; get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_do1: +#endif + + LDMIA sp!, {r0-r12,lr} ; reload saved registers + STMDB sp, {r0-r3} ; save r0-r3. We will restore r0-r3 in the SVC + ; mode so there is no need to update SP. + SUB r1, sp, #16 ; save the right SP value in r1, so we could restore r0-r3. + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + CPSID IF, #0x13 + + STMDB sp!, {r2} ; push old task's pc + STMDB sp!, {r4-r12,lr} ; push old task's lr,r12-r4 + LDMIA r1!, {r4-r7} ; restore r0-r3 of the interrupted thread + STMDB sp!, {r4-r7} ; push old task's r3-r0. We don't need to push/pop them to + ; r0-r3 because we just want to transfer the data and don't + ; use them here. + STMDB sp!, {r3} ; push old task's cpsr + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + VMRS r0, fpexc + TST r0, #0x40000000 + BEQ __no_vfp_frame_do2 + VSTMDB sp!, {d0-d15} + VMRS r1, fpscr + ; TODO: add support for Common VFPv3. + ; Save registers like FPINST, FPINST2 + STMDB sp!, {r1} +__no_vfp_frame_do2: + STMDB sp!, {r0} +#endif + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + LDMIA sp!, {r0} ; get fpexc + VMSR fpexc, r0 + TST r0, #0x40000000 + BEQ __no_vfp_frame_do3 + LDMIA sp!, {r1} ; get fpscr + VMSR fpscr, r1 + VLDMIA sp!, {d0-d15} +__no_vfp_frame_do3: +#endif + + LDMIA sp!, {r4} ; pop new task's cpsr to spsr + MSR spsr_cxsf, r4 + + LDMIA sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr + MOV lr, pc + STMIA sp!, {r0-r12, lr} + STR pc, [sp] + + END diff --git a/libcpu/arm/cortex-r52/cp15.h b/libcpu/arm/cortex-r52/cp15.h new file mode 100644 index 00000000000..9bab60997ed --- /dev/null +++ b/libcpu/arm/cortex-r52/cp15.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2011-2024, Shanghai Real-Thread Electronic Technology Co.,Ltd + * + * Change Logs: + * Date Author Notes + * 2022-08-29 RT-Thread first version + */ + +#ifndef __CP15_H__ +#define __CP15_H__ + +#define __get_cp(cp, op1, Rt, CRn, CRm, op2) \ + __asm volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_cp(cp, op1, Rt, CRn, CRm, op2) \ + __asm volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_cp64(cp, op1, Rt, CRm) \ + __asm volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_cp64(cp, op1, Rt, CRm) \ + __asm volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#endif diff --git a/libcpu/arm/cortex-r52/cp15_gcc.S b/libcpu/arm/cortex-r52/cp15_gcc.S new file mode 100644 index 00000000000..1d5b84d5961 --- /dev/null +++ b/libcpu/arm/cortex-r52/cp15_gcc.S @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2011-2022, Shanghai Real-Thread Electronic Technology Co.,Ltd + * + * Change Logs: + * Date Author Notes + * 2022-08-29 RT-Thread first version + */ + + +.globl rt_cpu_get_smp_id +rt_cpu_get_smp_id: + mrc p15, #0, r0, c0, c0, #5 + bx lr + +.globl rt_cpu_vector_set_base +rt_cpu_vector_set_base: + /* clear SCTRL.V to customize the vector address */ + mrc p15, #0, r1, c1, c0, #0 + bic r1, #(1 << 13) + mcr p15, #0, r1, c1, c0, #0 + /* set up the vector address */ + mcr p15, #0, r0, c12, c0, #0 + dsb + bx lr + +.globl rt_hw_cpu_dcache_enable +rt_hw_cpu_dcache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00000004 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl rt_hw_cpu_icache_enable +rt_hw_cpu_icache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +_FLD_MAX_WAY: + .word 0x3ff +_FLD_MAX_IDX: + .word 0x7fff + +.globl rt_cpu_dcache_clean_flush +rt_cpu_dcache_clean_flush: +stmfd sp!, {r0-r12, lr} + bl v7_flush_dcache_all + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate + dsb + isb + ldmfd sp!, {r0-r12, lr} + mov pc, lr + +v7_flush_dcache_all: + dmb @ ensure ordering with previous memory accesses + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished @ if loc is 0, then no need to clean + mov r10, #0 @ start clean at cache level 0 +loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache level + mov r1, r0, lsr r2 @ extract cache type bits from clidr + and r1, r1, #7 @ mask of the bits for current cache only + cmp r1, #2 @ see what cache we have at this level + blt skip @ skip if no cache, or just i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + isb @ isb to sych the new cssr&csidr + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the way size + clz r5, r4 @ find bit position of way size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the index size +loop2: + mov r9, r4 @ create working copy of max way size +loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge loop3 + subs r7, r7, #1 @ decrement the index + bge loop2 +skip: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt loop1 +finished: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + dsb + isb + mov pc, lr +#if 0 + push {r4-r11} + dmb + mrc p15, #1, r0, c0, c0, #1 @ read clid register + ands r3, r0, #0x7000000 @ get level of coherency + mov r3, r3, lsr #23 + beq finished + mov r10, #0 +loop1: + add r2, r10, r10, lsr #1 + mov r1, r0, lsr r2 + and r1, r1, #7 + cmp r1, #2 + blt skip + mcr p15, #2, r10, c0, c0, #0 + isb + mrc p15, #1, r1, c0, c0, #0 + and r2, r1, #7 + add r2, r2, #4 + ldr r4, _FLD_MAX_WAY + ands r4, r4, r1, lsr #3 + clz r5, r4 + ldr r7, _FLD_MAX_IDX + ands r7, r7, r1, lsr #13 +loop2: + mov r9, r4 +loop3: + orr r11, r10, r9, lsl r5 + orr r11, r11, r7, lsl r2 + mcr p15, #0, r11, c7, c14, #2 + subs r9, r9, #1 + bge loop3 + subs r7, r7, #1 + bge loop2 +skip: + add r10, r10, #2 + cmp r3, r10 + bgt loop1 + +finished: + dsb + isb + pop {r4-r11} + bx lr +#endif +.globl rt_cpu_icache_flush +rt_cpu_icache_flush: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate + dsb + isb + bx lr + +.globl rt_hw_cpu_dcache_disable +rt_hw_cpu_dcache_disable: + push {r4-r11, lr} + bl rt_cpu_dcache_clean_flush + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x00000004 + mcr p15, #0, r0, c1, c0, #0 + pop {r4-r11, lr} + bx lr + +.globl rt_hw_cpu_icache_disable +rt_hw_cpu_icache_disable: + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr diff --git a/libcpu/arm/cortex-r52/cpuport.c b/libcpu/arm/cortex-r52/cpuport.c new file mode 100644 index 00000000000..16c3a5198a0 --- /dev/null +++ b/libcpu/arm/cortex-r52/cpuport.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2011-2024, Shanghai Real-Thread Electronic Technology Co.,Ltd + * + * Change Logs: + * Date Author Notes + * 2022-08-29 RT-Thread first version + */ + +#include +#include + +int rt_hw_cpu_id(void) +{ + int cpu_id; + __asm volatile ( + "mrc p15, 0, %0, c0, c0, 5" + :"=r"(cpu_id) + ); + cpu_id &= 0xf; + return cpu_id; +} + +/** + * @addtogroup ARM CPU + */ +/*@{*/ + +/** shutdown CPU */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +/*@}*/ diff --git a/libcpu/arm/cortex-r52/cpuport.h b/libcpu/arm/cortex-r52/cpuport.h new file mode 100644 index 00000000000..8b408e054cf --- /dev/null +++ b/libcpu/arm/cortex-r52/cpuport.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2011-2024, Shanghai Real-Thread Electronic Technology Co.,Ltd + * + * Change Logs: + * Date Author Notes + * 2022-08-29 RT-Thread first version + */ + + +#ifndef CPUPORT_H__ +#define CPUPORT_H__ + +/* the exception stack without VFP registers */ +struct rt_hw_exp_stack +{ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; +}; + +struct rt_hw_stack +{ + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; +}; + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define MONITORMODE 0x16 +#define ABORTMODE 0x17 +#define HYPMODE 0x1b +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define T_Bit (1<<5) +#define F_Bit (1<<6) +#define I_Bit (1<<7) +#define A_Bit (1<<8) +#define E_Bit (1<<9) +#define J_Bit (1<<24) + + +// rt_inline void rt_hw_isb(void) +// { +// __asm volatile ("isb":::"memory"); +// } + +// rt_inline void rt_hw_dmb(void) +// { +// __asm volatile ("dmb":::"memory"); +// } + +// rt_inline void rt_hw_dsb(void) +// { +// __asm volatile ("dsb":::"memory"); +// } + +#endif /*CPUPORT_H__*/ diff --git a/libcpu/arm/cortex-r52/gicv3.c b/libcpu/arm/cortex-r52/gicv3.c new file mode 100644 index 00000000000..e9d92ab86c9 --- /dev/null +++ b/libcpu/arm/cortex-r52/gicv3.c @@ -0,0 +1,682 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + * 2014-04-03 Grissiom many enhancements + * 2018-11-22 Jesven add rt_hw_ipi_send() + * add rt_hw_ipi_handler_install() + */ + +#include +#include + +#include "gicv3.h" +#include "cp15.h" + +#ifndef RT_CPUS_NR +#define RT_CPUS_NR 1 +#endif + +struct arm_gic_v3 +{ + rt_uint32_t offset; /* the first interrupt index in the vector table */ + rt_uint32_t redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */ + rt_uint32_t dist_hw_base; /* the base address of the gic distributor */ + rt_uint32_t cpu_hw_base[RT_CPUS_NR]; /* the base addrees of the gic cpu interface */ +}; + +/* 'ARM_GIC_MAX_NR' is the number of cores */ +static struct arm_gic_v3 _gic_table[ARM_GIC_MAX_NR]; +static unsigned int _gic_max_irq; + +/** + * @name: arm_gic_cpumask_to_affval + * @msg: + * @in param cpu_mask: + * @out param cluster_id: aff1 [0:7],aff2 [8:15],aff3 [16:23] + * @out param target_list: Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the + * PE within a cluster with an Affinity 0 value equal to the bit number. + * @return {rt_uint32_t} 0 is finish , 1 is data valid + */ +rt_weak rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list) +{ + return 0; +} + +rt_weak rt_uint64_t get_main_cpu_affval(void) +{ + return 0; +} + +int arm_gic_get_active_irq(rt_uint32_t index) +{ + int irq; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + __get_gicv3_reg(ICC_IAR1, irq); + + irq = (irq & 0x1FFFFFF) + _gic_table[index].offset; + return irq; +} + +void arm_gic_ack(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + RT_ASSERT(irq >= 0); + + __DSB(); + __set_gicv3_reg(ICC_EOIR1, irq); +} + +void arm_gic_mask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1U << (irq % 32U); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + if (irq < 32) + { + rt_int32_t cpu_id = rt_hw_cpu_id(); + RT_ASSERT((cpu_id) < RT_CPUS_NR); + GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; + } + else + { + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void arm_gic_umask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1U << (irq % 32U); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq > 0U); + + if (irq < 32) + { + rt_int32_t cpu_id = rt_hw_cpu_id(); + RT_ASSERT((cpu_id) < RT_CPUS_NR); + GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; + } + else + { + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq) +{ + rt_uint32_t pend; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq > 0U); + + if (irq >= 16) + { + pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + /* No CPU identification offered */ + if (pend != 0U) + { + pend = 1U; + } + else + { + pend = 0U; + } + } + + return (pend); +} + +void arm_gic_set_pending_irq(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq > 0U); + + if (irq >= 16) + { + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + /* Forward the interrupt to the CPU interface that requested it */ + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); + } +} + +void arm_gic_clear_pending_irq(rt_uint32_t index, int irq) +{ + rt_uint32_t mask; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq > 0U); + + if (irq >= 16U) + { + mask = 1U << (irq % 32U); + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } + else + { + mask = 1U << ((irq % 4U) * 8U); + GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config) +{ + rt_uint32_t icfgr; + rt_uint32_t shift; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq > 0U); + + icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); + shift = (irq % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= (config << shift); + + GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; +} + +rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq > 0U); + + return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); +} + +void arm_gic_clear_active(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1U << (irq % 32U); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq > 0U); + + GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +/* Set up the cpu mask for the specific interrupt */ +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) +{ + rt_uint32_t old_tgt; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq > 0U); + + old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); + + old_tgt &= ~(0x0FFUL << ((irq % 4U) * 8U)); + old_tgt |= cpumask << ((irq % 4U) * 8U); + + GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; +} + +rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq > 0U); + + return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; +} + +void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority) +{ + rt_uint32_t mask; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq > 0U); + + if (irq < 32U) + { + rt_int32_t cpu_id = rt_hw_cpu_id(); + RT_ASSERT((cpu_id) < RT_CPUS_NR); + + mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask; + } + else + { + mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq > 0U); + + if (irq < 32U) + { + rt_int32_t cpu_id = rt_hw_cpu_id(); + + RT_ASSERT((cpu_id) < RT_CPUS_NR); + return (GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + } + else + { + return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + } +} + +void arm_gic_set_system_register_enable_mask(rt_uint32_t index, rt_uint32_t value) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + value &= 0xFFUL; + /* set priority mask */ + __set_gicv3_reg(ICC_SRE, value); + __ISB(); +// __asm volatile ("isb 0xF":: +// :"memory"); +} + +rt_uint32_t arm_gic_get_system_register_enable_mask(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + rt_uint32_t value; + + __get_gicv3_reg(ICC_SRE, value); + return value; +} + +void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + priority &= 0xFFUL; + /* set priority mask */ + __set_gicv3_reg(ICC_PMR, priority); +} + +rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + rt_uint32_t priority; + + __get_gicv3_reg(ICC_PMR, priority); + return priority; +} + +void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point) +{ + index = index; + binary_point &= 0x7U; + + __set_gicv3_reg(ICC_BPR1, binary_point); +} + +rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index) +{ + rt_uint32_t binary_point; + + index = index; + __get_gicv3_reg(ICC_BPR1, binary_point); + return binary_point; +} + +rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq) +{ + rt_uint32_t pending; + rt_uint32_t active; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq > 0U); + + active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + + return ((active << 1U) | pending); +} + +rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index) +{ + rt_uint32_t irq; + RT_ASSERT(index < ARM_GIC_MAX_NR); + + index = index; + __get_gicv3_reg(ICC_HPPIR1, irq); + return irq; +} + +rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); +} + +void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group) +{ + rt_uint32_t igroupr; + rt_uint32_t shift; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + RT_ASSERT(group <= 1U); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq > 0U); + + igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); + shift = (irq % 32U); + igroupr &= (~(1U << shift)); + igroupr |= ((group & 0x1U) << shift); + + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; +} + +rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq > 0U); + + return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; +} + +static int arm_gicv3_wait_rwp(rt_uint32_t index, rt_uint32_t irq) +{ + rt_uint32_t rwp_bit; + rt_uint32_t base; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + if (irq < 32u) + { + rt_int32_t cpu_id = rt_hw_cpu_id(); + + RT_ASSERT((cpu_id) < RT_CPUS_NR); + base = _gic_table[index].redist_hw_base[cpu_id]; + rwp_bit = GICR_CTLR_RWP; + } + else + { + base = _gic_table[index].dist_hw_base; + rwp_bit = GICD_CTLR_RWP; + } + + while (__REG32(base) & rwp_bit) + { + ; + } + + return 0; +} + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) +{ + rt_uint64_t cpu0_affval; + unsigned int gic_type, i; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].dist_hw_base = dist_base; + _gic_table[index].offset = irq_start; + + /* Find out how many interrupts are supported. */ + gic_type = GIC_DIST_TYPE(dist_base); + _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (_gic_max_irq > 1020U) + _gic_max_irq = 1020U; + if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ + _gic_max_irq = ARM_GIC_NR_IRQS; + + GIC_DIST_CTRL(dist_base) = 0x0U; + /* Wait for register write pending */ + arm_gicv3_wait_rwp(0, 32); + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32U; i < _gic_max_irq; i += 16U) + GIC_DIST_CONFIG(dist_base, i) = 0x0U; + + arm_gicv3_wait_rwp(0, 32); + + cpu0_affval = get_main_cpu_affval(); + /* Set all global interrupts to this CPU only. */ + for (i = 32U; i < _gic_max_irq; i++) + { + GIC_DIST_IROUTER_LOW(dist_base, i) = cpu0_affval; + GIC_DIST_IROUTER_HIGH(dist_base, i) = cpu0_affval >> 32; + } + + arm_gicv3_wait_rwp(0, 32); + + /* Set priority on spi interrupts. */ + for (i = 32U; i < _gic_max_irq; i += 4U) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; + + arm_gicv3_wait_rwp(0, 32); + /* Disable all interrupts. */ + for (i = 0U; i < _gic_max_irq; i += 32U) + { + GIC_DIST_PENDING_CLEAR(dist_base, i) = 0xffffffffU; + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; + } + + arm_gicv3_wait_rwp(0, 32); + /* All interrupts defaults to IGROUP1(IRQ). */ + for (i = 0U; i < _gic_max_irq; i += 32U) + GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU; + + arm_gicv3_wait_rwp(0, 32); + + /* + The Distributor control register (GICD_CTLR) must be configured to enable the interrupt groups and to set the routing mode. + Enable Affinity routing (ARE bits) The ARE bits in GICD_CTLR control whether affinity routing is enabled. + If affinity routing is not enabled, GICv3 can be configured for legacy operation. + Whether affinity routing is enabled or not can be controlled separately for Secure and Non-secure state. + Enables GICD_CTLR contains separate enable bits for Group 0, Secure Group 1 and Non-secure Group 1: + GICD_CTLR.EnableGrp1S enables distribution of Secure Group 1 interrupts. + GICD_CTLR.EnableGrp1NS enables distribution of Non-secure Group 1 interrupts. + GICD_CTLR.EnableGrp0 enables distribution of Group 0 interrupts. + */ + GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS; + + return 0; +} + +int arm_gic_redist_address_set(rt_uint32_t index, rt_uint32_t redist_addr, rt_uint32_t cpu_id) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + RT_ASSERT((cpu_id) < RT_CPUS_NR); + _gic_table[index].redist_hw_base[cpu_id] = redist_addr; + + return 0; +} + +int arm_gic_cpu_interface_address_set(rt_uint32_t index, rt_uint32_t interface_addr, rt_uint32_t cpu_id) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + RT_ASSERT((cpu_id) < RT_CPUS_NR); + _gic_table[index].cpu_hw_base[cpu_id] = interface_addr; + + return 0; +} + +int arm_gic_redist_init(rt_uint32_t index) +{ + unsigned int i; + rt_uint32_t base; + rt_int32_t cpu_id = rt_hw_cpu_id(); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + RT_ASSERT((cpu_id) < RT_CPUS_NR); + + base = _gic_table[index].redist_hw_base[cpu_id]; + /* redistributor enable */ + // 将原来的值的第二位清零，其他位保持不变 + GIC_RDIST_WAKER(base) &= ~(1U << 1); + // 一直执行，直到GIC_RDIST_WAKER(base)的值的第2位（从0开始计数）为0 + while (GIC_RDIST_WAKER(base) & (1 << 2)) + { + ; + } + + /* Disable all sgi and ppi interrupt */ + GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF; + arm_gicv3_wait_rwp(0, 0); + + /* Clear all inetrrupt pending */ + GIC_RDISTSGI_ICPENDR0(base) = 0xFFFFFFFF; + + /* the corresponding interrupt is Group 1 or Non-secure Group 1. */ + GIC_RDISTSGI_IGROUPR0(base, 0) = 0xFFFFFFFF; + GIC_RDISTSGI_IGRPMODR0(base, 0) = 0xFFFFFFFF; + + /* Configure default priorities for SGI 0:15 and PPI 16:31. */ + for (i = 0; i < 32; i += 4) + { + GIC_RDISTSGI_IPRIORITYR(base, i) = 0xa0a0a0a0U; + } + + /* Trigger level for PPI interrupts*/ + GIC_RDISTSGI_ICFGR1(base) = 0x0U; // PPI is level-sensitive. + return 0; +} + +int arm_gic_cpu_init(rt_uint32_t index) +{ + rt_uint32_t value; + RT_ASSERT(index < ARM_GIC_MAX_NR); + + /* The Priority Mask sets the minimum priority an + * interrupt must have in order to be forwarded to the PE. + */ + value = arm_gic_get_system_register_enable_mask(index); + value |= (1U << 0); + + arm_gic_set_system_register_enable_mask(index, value); + __set_gicv3_reg(ICC_CTLR, 0); + + arm_gic_set_interface_prior_mask(index, 0xFFU); + + /* Enable group1 interrupt */ + value = 0x1U; + __set_gicv3_reg(ICC_IGRPEN1, value); + + /* The Binary Point register is used + * for priority grouping and preemption. + */ + arm_gic_set_binary_point(0, 0); + + /* ICC_BPR0_EL1 determines the preemption group for both + Group 0 and Group 1 interrupts. + */ + value = 0x1U; + __set_gicv3_reg(ICC_CTLR, value); + + return 0; +} + +#ifdef RT_USING_SMP +void arm_gic_secondary_cpu_init(void) +{ + arm_gic_redist_init(0); + + arm_gic_cpu_init(0); +} +#endif + +void arm_gic_dump_type(rt_uint32_t index) +{ + unsigned int gic_type; + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1U << 10U) ? "has" : "no", + gic_type); +} + +void arm_gic_dump(rt_uint32_t index) +{ + unsigned int i, k; + + k = arm_gic_get_high_pending_irq(0); + rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); + rt_kprintf("--- hw mask ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n--- hw pending ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n--- hw active ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n"); +} + +long gic_dump(void) +{ + arm_gic_dump_type(0); + arm_gic_dump(0); + + return 0; +} diff --git a/libcpu/arm/cortex-r52/gicv3.h b/libcpu/arm/cortex-r52/gicv3.h new file mode 100644 index 00000000000..e92c6cd9f7f --- /dev/null +++ b/libcpu/arm/cortex-r52/gicv3.h @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ + +#ifndef __GIC_V3_H__ +#define __GIC_V3_H__ + +#include +#include + +#define __get_gicv3_reg(CR, Rt) __asm volatile("MRC " CR \ + : "=r"(Rt) \ + : \ + : "memory") +#define __set_gicv3_reg(CR, Rt) __asm volatile("MCR " CR \ + : \ + : "r"(Rt) \ + : "memory") + + +/* AArch32 System register interface to GICv3 */ +#define ICC_IAR0 "p15, 0, %0, c12, c8, 0" +#define ICC_IAR1 "p15, 0, %0, c12, c12, 0" +#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1" +#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1" +#define ICC_HPPIR0 "p15, 0, %0, c12, c8, 2" +#define ICC_HPPIR1 "p15, 0, %0, c12, c12, 2" +#define ICC_BPR0 "p15, 0, %0, c12, c8, 3" +#define ICC_BPR1 "p15, 0, %0, c12, c12, 3" +#define ICC_DIR "p15, 0, %0, c12, c11, 1" +#define ICC_PMR "p15, 0, %0, c4, c6, 0" +#define ICC_RPR "p15, 0, %0, c12, c11, 3" +#define ICC_CTLR "p15, 0, %0, c12, c12, 4" +#define ICC_MCTLR "p15, 6, %0, c12, c12, 4" +#define ICC_SRE "p15, 0, %0, c12, c12, 5" +#define ICC_HSRE "p15, 4, %0, c12, c9, 5" +#define ICC_MSRE "p15, 6, %0, c12, c12, 5" +#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6" +#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7" +#define ICC_MGRPEN1 "p15, 6, %0, c12, c12, 7" + +#define __REG32(x) (*((volatile unsigned int*)((rt_uint32_t)x))) + +#define ROUTED_TO_ALL (1) +#define ROUTED_TO_SPEC (0) + +/** Macro to access the Distributor Control Register (GICD_CTLR) +*/ +#define GICD_CTLR_RWP ((unsigned int)1<<31) +#define GICD_CTLR_E1NWF (1<<7) +#define GICD_CTLR_DS (1<<6) // 当两种安全模式被同时支持时，可以通过GICD_CTLR.DS==1关闭其中一个，只支持non-secure模式 +#define GICD_CTLR_ARE_NS (1<<5) +#define GICD_CTLR_ARE_S (1<<4) +#define GICD_CTLR_ENGRP1S (1<<2) // secure group 1 +#define GICD_CTLR_ENGRP1NS (1<<1) // non-secure group 1 +#define GICD_CTLR_ENGRP0 (1<<0) // group 0 + +/** Macro to access the Redistributor Control Register (GICR_CTLR) +*/ +#define GICR_CTLR_UWP (1<<31) +#define GICR_CTLR_DPG1S (1<<26) +#define GICR_CTLR_DPG1NS (1<<25) +#define GICR_CTLR_DPG0 (1<<24) +#define GICR_CTLR_RWP (1<<3) +#define GICR_CTLR_IR (1<<2) +#define GICR_CTLR_CES (1<<1) +#define GICR_CTLR_EnableLPI (1<<0) + +/** Macro to access the Generic Interrupt Controller Interface (GICC) +*/ +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) +#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) + +/** Macro to access the Generic Interrupt Controller Distributor (GICD) +*/ +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) +#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) +#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U) +#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4) + +/* SGI base address is at 64K offset from Redistributor base address */ +#define GIC_RSGI_OFFSET 0x10000 + +/** Macro to access the Generic Interrupt Controller Redistributor (GICD) +*/ +#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U) +#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U) +#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U) +#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U) +#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U) +#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U) +#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U) +#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U) +#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U) +#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U) + +#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U) +#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U) +#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) +#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U) +#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U) +#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U) +#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U) +#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U) +#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U) +#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U) +#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4) +#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U) // 当执行一个非安全模式到安全模式的访问 + +#define GIC_RSGI_AFF1_OFFSET 16 +#define GIC_RSGI_AFF2_OFFSET 32 +#define GIC_RSGI_AFF3_OFFSET 48 + +rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list); +rt_uint64_t get_main_cpu_affval(void); +int arm_gic_get_active_irq(rt_uint32_t index); +void arm_gic_ack(rt_uint32_t index, int irq); + +void arm_gic_mask(rt_uint32_t index, int irq); +void arm_gic_umask(rt_uint32_t index, int irq); + +rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq); +void arm_gic_set_pending_irq(rt_uint32_t index, int irq); +void arm_gic_clear_pending_irq(rt_uint32_t index, int irq); + +void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config); +rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq); + +void arm_gic_clear_active(rt_uint32_t index, int irq); + +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); +rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq); + +void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority); +rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq); + +void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority); +rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index); + +void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point); +rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index); + +rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq); + +rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index); + +rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index); + +void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group); +rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq); + +int arm_gic_redist_address_set(rt_uint32_t index, rt_uint32_t redist_addr, rt_uint32_t cpu_id); +int arm_gic_cpu_interface_address_set(rt_uint32_t index, rt_uint32_t interface_addr, rt_uint32_t cpu_id); +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); +int arm_gic_cpu_init(rt_uint32_t index); +int arm_gic_redist_init(rt_uint32_t index); + +void arm_gic_dump_type(rt_uint32_t index); +void arm_gic_dump(rt_uint32_t index); + +void arm_gic_set_system_register_enable_mask(rt_uint32_t index, rt_uint32_t value); +rt_uint32_t arm_gic_get_system_register_enable_mask(rt_uint32_t index); +void arm_gic_secondary_cpu_init(void); + +void assemb_dsb_func(); +void assemb_isb_func(); + +#endif + diff --git a/libcpu/arm/cortex-r52/interrupt.c b/libcpu/arm/cortex-r52/interrupt.c new file mode 100644 index 00000000000..919a8bca512 --- /dev/null +++ b/libcpu/arm/cortex-r52/interrupt.c @@ -0,0 +1,282 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-06 Bernard first version + * 2018-11-22 Jesven add smp support + */ + +#include +#include +#include "interrupt.h" + +#include "gicv3.h" + +/* exception and interrupt handler table */ +struct rt_irq_desc isr_table[MAX_HANDLERS]; + +#ifndef RT_USING_SMP +/* Those varibles will be accessed in ISR, so we need to share them. */ +rt_uint32_t rt_interrupt_from_thread = 0; +rt_uint32_t rt_interrupt_to_thread = 0; +rt_uint32_t rt_thread_switch_interrupt_flag = 0; + +#ifdef RT_USING_HOOK +static void (*rt_interrupt_switch_hook)(void); + +void rt_interrupt_switch_sethook(void (*hook)(void)) +{ + rt_interrupt_switch_hook = hook; +} +#endif + +void rt_interrupt_hook(void) +{ + RT_OBJECT_HOOK_CALL(rt_interrupt_switch_hook, ()); +} +#endif + +const unsigned int VECTOR_BASE = 0x00; +extern void rt_cpu_vector_set_base(unsigned int addr); +extern int system_vectors; + +void rt_hw_vector_init(void) +{ + rt_cpu_vector_set_base((unsigned int)&system_vectors); +} + +/** + * This function will initialize hardware interrupt + * Called by the primary cpu(cpu0) + */ +void rt_hw_interrupt_init(void) +{ + rt_uint32_t gic_dist_base; + rt_uint32_t gic_irq_start; + + /* initialize vector table */ + /* rt_hw_vector_init(); */ + + /* initialize exceptions table */ + rt_memset(isr_table, 0x00, sizeof(isr_table)); + + /* initialize ARM GIC */ + gic_dist_base = platform_get_gic_dist_base(); + gic_irq_start = GIC_IRQ_START; + + arm_gic_dist_init(0, gic_dist_base, gic_irq_start); + + arm_gic_cpu_init(0); + arm_gic_redist_init(0); +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + arm_gic_mask(0, vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + arm_gic_umask(0, vector); +} + +/** + * This function returns the active interrupt number. + * @param none + */ +int rt_hw_interrupt_get_irq(void) +{ + return arm_gic_get_active_irq(0); +} + +/** + * This function acknowledges the interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_ack(int vector) +{ + arm_gic_ack(0, vector); +} + +/** + * This function set interrupt CPU targets. + * @param vector: the interrupt number + * cpu_mask: target cpus mask, one bit for one core + */ +void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask) +{ + arm_gic_set_cpu(0, vector, cpu_mask); +} + +/** + * This function get interrupt CPU targets. + * @param vector: the interrupt number + * @return target cpus mask, one bit for one core + */ +unsigned int rt_hw_interrupt_get_target_cpus(int vector) +{ + return arm_gic_get_target_cpu(0, vector); +} + +/** + * This function set interrupt triger mode. + * @param vector: the interrupt number + * mode: interrupt triger mode; 0: level triger, 1: edge triger + */ +void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode) +{ + arm_gic_set_configuration(0, vector, mode); +} + +/** + * This function get interrupt triger mode. + * @param vector: the interrupt number + * @return interrupt triger mode; 0: level triger, 1: edge triger + */ +unsigned int rt_hw_interrupt_get_triger_mode(int vector) +{ + return arm_gic_get_configuration(0, vector); +} + +/** + * This function set interrupt pending flag. + * @param vector: the interrupt number + */ +void rt_hw_interrupt_set_pending(int vector) +{ + arm_gic_set_pending_irq(0, vector); +} + +/** + * This function get interrupt pending flag. + * @param vector: the interrupt number + * @return interrupt pending flag, 0: not pending; 1: pending + */ +unsigned int rt_hw_interrupt_get_pending(int vector) +{ + return arm_gic_get_pending_irq(0, vector); +} + +/** + * This function clear interrupt pending flag. + * @param vector: the interrupt number + */ +void rt_hw_interrupt_clear_pending(int vector) +{ + arm_gic_clear_pending_irq(0, vector); +} + +/** + * This function set interrupt priority value. + * @param vector: the interrupt number + * priority: the priority of interrupt to set + */ +void rt_hw_interrupt_set_priority(int vector, unsigned int priority) +{ + arm_gic_set_priority(0, vector, priority); +} + +/** + * This function get interrupt priority. + * @param vector: the interrupt number + * @return interrupt priority value + */ +unsigned int rt_hw_interrupt_get_priority(int vector) +{ + return arm_gic_get_priority(0, vector); +} + +/** + * This function set priority masking threshold. + * @param priority: priority masking threshold + */ +void rt_hw_interrupt_set_priority_mask(unsigned int priority) +{ + arm_gic_set_interface_prior_mask(0, priority); +} + +/** + * This function get priority masking threshold. + * @param none + * @return priority masking threshold + */ +unsigned int rt_hw_interrupt_get_priority_mask(void) +{ + return arm_gic_get_interface_prior_mask(0); +} + +/** + * This function set priority grouping field split point. + * @param bits: priority grouping field split point + * @return 0: success; -1: failed + */ +int rt_hw_interrupt_set_prior_group_bits(unsigned int bits) +{ + int status; + + if (bits < 8) + { + arm_gic_set_binary_point(0, (7 - bits)); + status = 0; + } + else + { + status = -1; + } + + return (status); +} + +/** + * This function get priority grouping field split point. + * @param none + * @return priority grouping field split point + */ +unsigned int rt_hw_interrupt_get_prior_group_bits(void) +{ + unsigned int bp; + + bp = arm_gic_get_binary_point(0) & 0x07; + + return (7 - bp); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector < MAX_HANDLERS) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + } + + return old_handler; +} + diff --git a/libcpu/arm/cortex-r52/interrupt.h b/libcpu/arm/cortex-r52/interrupt.h new file mode 100644 index 00000000000..804943ea96f --- /dev/null +++ b/libcpu/arm/cortex-r52/interrupt.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-06 Bernard first version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +#define IRQ_MODE_TRIG_LEVEL (0x00) /* Trigger: level triggered interrupt */ +#define IRQ_MODE_TRIG_EDGE (0x01) /* Trigger: edge triggered interrupt */ + +void rt_hw_vector_init(void); + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); + +int rt_hw_interrupt_get_irq(void); +void rt_hw_interrupt_ack(int vector); + +void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask); +unsigned int rt_hw_interrupt_get_target_cpus(int vector); + +void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode); +unsigned int rt_hw_interrupt_get_triger_mode(int vector); + +void rt_hw_interrupt_set_pending(int vector); +unsigned int rt_hw_interrupt_get_pending(int vector); +void rt_hw_interrupt_clear_pending(int vector); + +void rt_hw_interrupt_set_priority(int vector, unsigned int priority); +unsigned int rt_hw_interrupt_get_priority(int vector); + +void rt_hw_interrupt_set_priority_mask(unsigned int priority); +unsigned int rt_hw_interrupt_get_priority_mask(void); + +int rt_hw_interrupt_set_prior_group_bits(unsigned int bits); +unsigned int rt_hw_interrupt_get_prior_group_bits(void); + +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +#endif + diff --git a/libcpu/arm/cortex-r52/stack.c b/libcpu/arm/cortex-r52/stack.c new file mode 100644 index 00000000000..540eb7146db --- /dev/null +++ b/libcpu/arm/cortex-r52/stack.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2011-2024, Shanghai Real-Thread Electronic Technology Co.,Ltd + * + * Change Logs: + * Date Author Notes + * 2022-08-29 RT-Thread first version + */ + +#include "armv8.h" +#include +//#include + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + + stack_addr += sizeof(rt_uint32_t); + stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); + stk = (rt_uint32_t *)stack_addr; + *(--stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0xdeadbeef; /* r12 */ + *(--stk) = 0xdeadbeef; /* r11 */ + *(--stk) = 0xdeadbeef; /* r10 */ + *(--stk) = 0xdeadbeef; /* r9 */ + *(--stk) = 0xdeadbeef; /* r8 */ + *(--stk) = 0xdeadbeef; /* r7 */ + *(--stk) = 0xdeadbeef; /* r6 */ + *(--stk) = 0xdeadbeef; /* r5 */ + *(--stk) = 0xdeadbeef; /* r4 */ + *(--stk) = 0xdeadbeef; /* r3 */ + *(--stk) = 0xdeadbeef; /* r2 */ + *(--stk) = 0xdeadbeef; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ + +#ifdef RT_USING_OSA + *(--stk) = 0; /* user lr */ + *(--stk) = 0; /* user sp*/ +#endif +#ifdef RT_USING_FPU + *(--stk) = 0; /* not use fpu*/ +#endif + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/libcpu/arm/cortex-r52/start_gcc.S b/libcpu/arm/cortex-r52/start_gcc.S new file mode 100644 index 00000000000..787d3e44fbb --- /dev/null +++ b/libcpu/arm/cortex-r52/start_gcc.S @@ -0,0 +1,504 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +@------------------------------------------------------------------------------- +@ sys_core.asm +@ +@ (c) Texas Instruments 2009-2013, All rights reserved. +@ + +//#include + +.equ Mode_USR, 0x10 +.equ Mode_FIQ, 0x11 +.equ Mode_IRQ, 0x12 +.equ Mode_SVC, 0x13 +.equ Mode_ABT, 0x17 +.equ Mode_UND, 0x1B +.equ Mode_SYS, 0x1F + +.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled +.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled + +.equ UND_Stack_Size, 0x00000000 +.equ SVC_Stack_Size, 0x00000000 +.equ ABT_Stack_Size, 0x00000000 +.equ FIQ_Stack_Size, 0x00001000 +.equ IRQ_Stack_Size, 0x00001000 + +.section .bss.noinit +/* stack */ +.globl stack_start +.globl stack_top + +.align 3 +stack_start: +.rept (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) +.byte 0 +.endr +stack_top: + +.section .text, "ax" + .text + .arm + + .globl _c_int00 + +.globl _reset +_reset: +@------------------------------------------------------------------------------- +@ Initialize CPU Registers +@ After reset, the CPU is in the Supervisor mode (M = 10011) + mov r0, #0x0000 + mov r1, #0x0000 + mov r2, #0x0000 + mov r3, #0x0000 + mov r4, #0x0000 + mov r5, #0x0000 + mov r6, #0x0000 + mov r7, #0x0000 + mov r8, #0x0000 + mov r9, #0x0000 + mov r10, #0x0000 + mov r11, #0x0000 + mov r12, #0x0000 + mov r13, #0x0000 + mrs r1, cpsr + msr spsr_cxsf, r1 + + cpsid if, #19 + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING) + @ Turn on FPV coprocessor + mrc p15, #0x00, r2, c1, c0, #0x02 + orr r2, r2, #0xF00000 + mcr p15, #0x00, r2, c1, c0, #0x02 + + fmrx r2, fpexc + orr r2, r2, #0x40000000 + fmxr fpexc, r2 +#endif + +@------------------------------------------------------------------------------- +@ Initialize Stack Pointers + ldr r0, =stack_top + + @ Set the startup stack for svc + mov sp, r0 + + @ Enter Undefined Instruction Mode and set its Stack Pointer + msr cpsr_c, #Mode_UND|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #UND_Stack_Size + + @ Enter Abort Mode and set its Stack Pointer + msr cpsr_c, #Mode_ABT|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #ABT_Stack_Size + + @ Enter FIQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #FIQ_Stack_Size + + @ Enter IRQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #IRQ_Stack_Size + + @ Switch back to SVC + msr cpsr_c, #Mode_SVC|I_Bit|F_Bit + + bl next1 +next1: + bl next2 +next2: + bl next3 +next3: + bl next4 +next4: + ldr lr, =_c_int00 + bx lr + +.globl data_init +data_init: + /* copy .data to SRAM */ + ldr r1, =_mdata /* .data start in image */ + ldr r2, =_data_end /* .data end in image */ + ldr r3, =_data_start /* sram data start */ +data_loop: + ldr r0, [r1, #0] + str r0, [r3] + + add r1, r1, #4 + add r3, r3, #4 + + cmp r3, r2 /* check if data to clear */ + blo data_loop /* loop until done */ + + /* clear .bss */ + mov r0,#0 /* get a zero */ + ldr r1,=__bss_start__ /* bss start */ + ldr r2,=__bss_end__ /* bss end */ + +bss_loop: + cmp r1,r2 /* check if data to clear */ + strlo r0,[r1],#4 /* clear 4 bytes */ + blo bss_loop /* loop until done */ + + /* call C++ constructors of global objects */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ + +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0], #4 + stmfd sp!, {r0-r3, ip, lr} + mov lr, pc + bx r2 + ldmfd sp!, {r0-r3, ip, lr} + b ctor_loop +ctor_end: + bx lr + +@------------------------------------------------------------------------------- +@ Enable RAM ECC Support + + .globl _coreEnableRamEcc_ +_coreEnableRamEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + orr r0, r0, #0x0C000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + +@------------------------------------------------------------------------------- +@ Disable RAM ECC Support + + .globl _coreDisableRamEcc_ +_coreDisableRamEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + bic r0, r0, #0x0C000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + + +@------------------------------------------------------------------------------- +@ Enable Flash ECC Support + + .globl _coreEnableFlashEcc_ +_coreEnableFlashEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + orr r0, r0, #0x02000000 + dmb + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + +@------------------------------------------------------------------------------- +@ Disable Flash ECC Support + + .globl _coreDisableFlashEcc_ +_coreDisableFlashEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + bic r0, r0, #0x02000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + + +@------------------------------------------------------------------------------- +@ Get data fault status register + + .globl _coreGetDataFault_ +_coreGetDataFault_: + + mrc p15, #0, r0, c5, c0, #0 + bx lr + + + +@------------------------------------------------------------------------------- +@ Clear data fault status register + + .globl _coreClearDataFault_ +_coreClearDataFault_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c5, c0, #0 + ldmfd sp!, {r0} + bx lr + + + +@------------------------------------------------------------------------------- +@ Get instruction fault status register + + .globl _coreGetInstructionFault_ +_coreGetInstructionFault_: + + mrc p15, #0, r0, c5, c0, #1 + bx lr + + + +@------------------------------------------------------------------------------- +@ Clear instruction fault status register + + .globl _coreClearInstructionFault_ +_coreClearInstructionFault_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c5, c0, #1 + ldmfd sp!, {r0} + bx lr + + + +@------------------------------------------------------------------------------- +@ Get data fault address register + + .globl _coreGetDataFaultAddress_ +_coreGetDataFaultAddress_: + + mrc p15, #0, r0, c6, c0, #0 + bx lr + + + +@------------------------------------------------------------------------------- +@ Clear data fault address register + + .globl _coreClearDataFaultAddress_ +_coreClearDataFaultAddress_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c6, c0, #0 + ldmfd sp!, {r0} + bx lr + + + +@------------------------------------------------------------------------------- +@ Get instruction fault address register + + .globl _coreGetInstructionFaultAddress_ +_coreGetInstructionFaultAddress_: + + mrc p15, #0, r0, c6, c0, #2 + bx lr + + + +@------------------------------------------------------------------------------- +@ Clear instruction fault address register + + .globl _coreClearInstructionFaultAddress_ +_coreClearInstructionFaultAddress_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c6, c0, #2 + ldmfd sp!, {r0} + bx lr + + + +@------------------------------------------------------------------------------- +@ Get auxiliary data fault status register + + .globl _coreGetAuxiliaryDataFault_ +_coreGetAuxiliaryDataFault_: + + mrc p15, #0, r0, c5, c1, #0 + bx lr + + + +@------------------------------------------------------------------------------- +@ Clear auxiliary data fault status register + + .globl _coreClearAuxiliaryDataFault_ +_coreClearAuxiliaryDataFault_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c5, c1, #0 + ldmfd sp!, {r0} + bx lr + + + +@------------------------------------------------------------------------------- +@ Get auxiliary instruction fault status register + + .globl _coreGetAuxiliaryInstructionFault_ +_coreGetAuxiliaryInstructionFault_: + + mrc p15, #0, r0, c5, c1, #1 + bx lr + + +@------------------------------------------------------------------------------- +@ Clear auxiliary instruction fault status register + + .globl _coreClearAuxiliaryInstructionFault_ +_coreClearAuxiliaryInstructionFault_: + + stmfd sp!, {r0} + mov r0, #0 + mrc p15, #0, r0, c5, c1, #1 + ldmfd sp!, {r0} + bx lr + + +@------------------------------------------------------------------------------- +@ Clear ESM CCM errorss + + .globl _esmCcmErrorsClear_ +_esmCcmErrorsClear_: + + stmfd sp!, {r0-r2} + ldr r0, ESMSR1_REG @ load the ESMSR1 status register address + ldr r2, ESMSR1_ERR_CLR + str r2, [r0] @ clear the ESMSR1 register + + ldr r0, ESMSR2_REG @ load the ESMSR2 status register address + ldr r2, ESMSR2_ERR_CLR + str r2, [r0] @ clear the ESMSR2 register + + ldr r0, ESMSSR2_REG @ load the ESMSSR2 status register address + ldr r2, ESMSSR2_ERR_CLR + str r2, [r0] @ clear the ESMSSR2 register + + ldr r0, ESMKEY_REG @ load the ESMKEY register address + mov r2, #0x5 @ load R2 with 0x5 + str r2, [r0] @ clear the ESMKEY register + + ldr r0, VIM_INTREQ @ load the INTREQ register address + ldr r2, VIM_INT_CLR + str r2, [r0] @ clear the INTREQ register + ldr r0, CCMR4_STAT_REG @ load the CCMR4 status register address + ldr r2, CCMR4_ERR_CLR + str r2, [r0] @ clear the CCMR4 status register + ldmfd sp!, {r0-r2} + bx lr + +ESMSR1_REG: .word 0xFFFFF518 +ESMSR2_REG: .word 0xFFFFF51C +ESMSR3_REG: .word 0xFFFFF520 +ESMKEY_REG: .word 0xFFFFF538 +ESMSSR2_REG: .word 0xFFFFF53C +CCMR4_STAT_REG: .word 0xFFFFF600 +ERR_CLR_WRD: .word 0xFFFFFFFF +CCMR4_ERR_CLR: .word 0x00010000 +ESMSR1_ERR_CLR: .word 0x80000000 +ESMSR2_ERR_CLR: .word 0x00000004 +ESMSSR2_ERR_CLR: .word 0x00000004 +VIM_INT_CLR: .word 0x00000001 +VIM_INTREQ: .word 0xFFFFFE20 + + +@------------------------------------------------------------------------------- +@ Work Around for Errata CORTEX-R4#57: +@ +@ Errata Description: +@ Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags +@ Workaround: +@ Disable out-of-order single-precision floating point +@ multiply-accumulate instruction completion + + .globl _errata_CORTEXR4_57_ +_errata_CORTEXR4_57_: + + push {r0} + mrc p15, #0, r0, c15, c0, #0 @ Read Secondary Auxiliary Control Register + orr r0, r0, #0x10000 @ Set BIT 16 (Set DOOFMACS) + mcr p15, #0, r0, c15, c0, #0 @ Write Secondary Auxiliary Control Register + pop {r0} + bx lr + +@------------------------------------------------------------------------------- +@ Work Around for Errata CORTEX-R4#66: +@ +@ Errata Description: +@ Register Corruption During A Load-Multiple Instruction At +@ an Exception Vector +@ Workaround: +@ Disable out-of-order completion for divide instructions in +@ Auxiliary Control register + + .globl _errata_CORTEXR4_66_ +_errata_CORTEXR4_66_: + + push {r0} + mrc p15, #0, r0, c1, c0, #1 @ Read Auxiliary Control register + orr r0, r0, #0x80 @ Set BIT 7 (Disable out-of-order completion + @ for divide instructions.) + mcr p15, #0, r0, c1, c0, #1 @ Write Auxiliary Control register + pop {r0} + bx lr + + .globl turnon_VFP +turnon_VFP: + @ Enable FPV + STMDB sp!, {r0} + fmrx r0, fpexc + orr r0, r0, #0x40000000 + fmxr fpexc, r0 + LDMIA sp!, {r0} + subs pc, lr, #4 + + .macro push_svc_reg + sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ + stmia sp, {r0 - r12} @/* Calling r0-r12 */ + mov r0, sp + mrs r6, spsr @/* Save CPSR */ + str lr, [r0, #15*4] @/* Push PC */ + str r6, [r0, #16*4] @/* Push CPSR */ + cps #Mode_SVC + str sp, [r0, #13*4] @/* Save calling SP */ + str lr, [r0, #14*4] @/* Save calling PC */ + .endm + + .globl vector_svc +vector_svc: + push_svc_reg + bl rt_hw_trap_svc + b . + + .globl vector_pabort +vector_pabort: + push_svc_reg + bl rt_hw_trap_pabt + b . + + .globl vector_dabort +vector_dabort: + push_svc_reg + bl rt_hw_trap_dabt + b . + + .globl vector_resv +vector_resv: + push_svc_reg + bl rt_hw_trap_resv + b . diff --git a/libcpu/arm/cortex-r52/start_iar.S b/libcpu/arm/cortex-r52/start_iar.S new file mode 100644 index 00000000000..9e110dd1525 --- /dev/null +++ b/libcpu/arm/cortex-r52/start_iar.S @@ -0,0 +1,334 @@ +;/* +; * Copyright (c) 2006-2022, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2024-03-11 Wangyuqiang first version +; */ +;@------------------------------------------------------------------------------- +;@ sys_core.asm +;@ +;@ (c) Texas Instruments 2009-2013, All rights reserved. +;@ + +; Constants +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 +F_Bit EQU 0x40 + +UND_Stack_Size EQU 0x00000000 +SVC_Stack_Size EQU 0x00000000 +ABT_Stack_Size EQU 0x00000000 +FIQ_Stack_Size EQU 0x00001000 +IRQ_Stack_Size EQU 0x00001000 + + IMPORT _c_int00 + IMPORT rt_hw_trap_svc + IMPORT rt_hw_trap_pabt + IMPORT rt_hw_trap_dabt + IMPORT rt_hw_trap_resv + IMPORT system_init + IMPORT __iar_program_start + +; Define sections + SECTION .text:CODE:REORDER:NOROOT(2) + + ; Define stack start and top + EXPORT stack_start + EXPORT stack_top + + ; Align stack start to a 4-byte boundary (32-bit word) + ALIGNRAM 5 +stack_start: + ; Reserve stack memory + REPT (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) + DCB 0 ; Define a byte of data and clear it to zero + ENDR + + ; Define stack top label +stack_top: + +; Define code section + SECTION .text:CODE:REORDER:NOROOT(2) + + ; Specify ARM mode + THUMB + +;@------------------------------------------------------------------------------- +;@ Enable RAM ECC Support + + EXPORT _coreEnableRamEcc_ +_coreEnableRamEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + orr r0, r0, #0x0C000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + +;@------------------------------------------------------------------------------- +;@ Disable RAM ECC Support + + EXPORT _coreDisableRamEcc_ +_coreDisableRamEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + bic r0, r0, #0x0C000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + +;@------------------------------------------------------------------------------- +;@ Enable Flash ECC Support + + EXPORT _coreEnableFlashEcc_ +_coreEnableFlashEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + orr r0, r0, #0x02000000 + dmb + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + +;@------------------------------------------------------------------------------- +;@ Disable Flash ECC Support + + EXPORT _coreDisableFlashEcc_ +_coreDisableFlashEcc_: + + stmfd sp!, {r0} + mrc p15, #0x00, r0, c1, c0, #0x01 + bic r0, r0, #0x02000000 + mcr p15, #0x00, r0, c1, c0, #0x01 + ldmfd sp!, {r0} + bx lr + +;@------------------------------------------------------------------------------- +;@ Get data fault status register + + EXPORT _coreGetDataFault_ +_coreGetDataFault_: + + mrc p15, #0, r0, c5, c0, #0 + bx lr + +;@------------------------------------------------------------------------------- +;@ Clear data fault status register + + EXPORT _coreClearDataFault_ +_coreClearDataFault_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c5, c0, #0 + ldmfd sp!, {r0} + bx lr + +;@------------------------------------------------------------------------------- +;@ Get instruction fault status register + + EXPORT _coreGetInstructionFault_ +_coreGetInstructionFault_: + + mrc p15, #0, r0, c5, c0, #1 + bx lr + +;@------------------------------------------------------------------------------- +;@ Clear instruction fault status register + + EXPORT _coreClearInstructionFault_ +_coreClearInstructionFault_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c5, c0, #1 + ldmfd sp!, {r0} + bx lr + +;@------------------------------------------------------------------------------- +;@ Get data fault address register + + EXPORT _coreGetDataFaultAddress_ +_coreGetDataFaultAddress_: + + mrc p15, #0, r0, c6, c0, #0 + bx lr + +;@------------------------------------------------------------------------------- +;@ Clear data fault address register + + EXPORT _coreClearDataFaultAddress_ +_coreClearDataFaultAddress_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c6, c0, #0 + ldmfd sp!, {r0} + bx lr + +;@------------------------------------------------------------------------------- +;@ Get instruction fault address register + + EXPORT _coreGetInstructionFaultAddress_ +_coreGetInstructionFaultAddress_: + + mrc p15, #0, r0, c6, c0, #2 + bx lr + +;@------------------------------------------------------------------------------- +;@ Clear instruction fault address register + + EXPORT _coreClearInstructionFaultAddress_ +_coreClearInstructionFaultAddress_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c6, c0, #2 + ldmfd sp!, {r0} + bx lr + +;@------------------------------------------------------------------------------- +;@ Get auxiliary data fault status register + + EXPORT _coreGetAuxiliaryDataFault_ +_coreGetAuxiliaryDataFault_: + + mrc p15, #0, r0, c5, c1, #0 + bx lr + + + +;@------------------------------------------------------------------------------- +;@ Clear auxiliary data fault status register + + EXPORT _coreClearAuxiliaryDataFault_ +_coreClearAuxiliaryDataFault_: + + stmfd sp!, {r0} + mov r0, #0 + mcr p15, #0, r0, c5, c1, #0 + ldmfd sp!, {r0} + bx lr + + + +;@------------------------------------------------------------------------------- +;@ Get auxiliary instruction fault status register + + EXPORT _coreGetAuxiliaryInstructionFault_ +_coreGetAuxiliaryInstructionFault_: + + mrc p15, #0, r0, c5, c1, #1 + bx lr + + +;@------------------------------------------------------------------------------- +;@ Clear auxiliary instruction fault status register + + EXPORT _coreClearAuxiliaryInstructionFault_ +_coreClearAuxiliaryInstructionFault_: + + stmfd sp!, {r0} + mov r0, #0 + mrc p15, #0, r0, c5, c1, #1 + ldmfd sp!, {r0} + bx lr + +;@------------------------------------------------------------------------------- +;@ Work Around for Errata CORTEX-R4#57: +;@ +;@ Errata Description: +;@ Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags +;@ Workaround: +;@ Disable out-of-order single-precision floating point +;@ multiply-accumulate instruction completion + + EXPORT _errata_CORTEXR4_57_ +_errata_CORTEXR4_57_: + + push {r0} + mrc p15, #0, r0, c15, c0, #0 ;@ Read Secondary Auxiliary Control Register + orr r0, r0, #0x10000 ;@ Set BIT 16 (Set DOOFMACS) + mcr p15, #0, r0, c15, c0, #0 ;@ Write Secondary Auxiliary Control Register + pop {r0} + bx lr + +;@------------------------------------------------------------------------------- +;@ Work Around for Errata CORTEX-R4#66: +;@ +;@ Errata Description: +;@ Register Corruption During A Load-Multiple Instruction At +;@ an Exception Vector +;@ Workaround: +;@ Disable out-of-order completion for divide instructions in +;@ Auxiliary Control register + + EXPORT _errata_CORTEXR4_66_ +_errata_CORTEXR4_66_: + + push {r0} + mrc p15, #0, r0, c1, c0, #1 ;@ Read Auxiliary Control register + orr r0, r0, #0x80 ;@ Set BIT 7 (Disable out-of-order completion + ;@ for divide instructions.) + mcr p15, #0, r0, c1, c0, #1 ;@ Write Auxiliary Control register + pop {r0} + bx lr + EXPORT turnon_VFP +turnon_VFP: + ;@ Enable FPV + stmdb sp!, {r0} + fmrx r0, fpexc + orr r0, r0, #0x40000000 + fmxr fpexc, r0 + ldmia sp!, {r0} + subs pc, lr, #4 + + macro push_svc_reg + sub sp, sp, #17 * 4 ;@/* Sizeof(struct rt_hw_exp_stack) */ + stmia sp, {r0 - r12} ;@/* Calling r0-r12 */ + mov r0, sp + mrs r6, spsr ;@/* Save CPSR */ + str lr, [r0, #15*4] ;@/* Push PC */ + str r6, [r0, #16*4] ;@/* Push CPSR */ + cps #Mode_SVC + str sp, [r0, #13*4] ;@/* Save calling SP */ + str lr, [r0, #14*4] ;@/* Save calling PC */ + endm + + EXPORT SVC_Handler +SVC_Handler: + push_svc_reg + bl rt_hw_trap_svc + b . + + EXPORT Prefetch_Handler +Prefetch_Handler: + push_svc_reg + bl rt_hw_trap_pabt + b . + + EXPORT Abort_Handler +Abort_Handler: + push_svc_reg + bl rt_hw_trap_dabt + b . + + EXPORT Reserved_Handler +Reserved_Handler: + push_svc_reg + bl rt_hw_trap_resv + b . + END diff --git a/libcpu/arm/cortex-r52/trap.c b/libcpu/arm/cortex-r52/trap.c new file mode 100644 index 00000000000..e5c217cb73e --- /dev/null +++ b/libcpu/arm/cortex-r52/trap.c @@ -0,0 +1,318 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ + +#include +#include +#include +#include +//#include + +#include "interrupt.h" + +#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) +extern long list_thread(void); +#endif + +/** + * The software interrupt instruction (SWI) is used for entering + * Supervisor mode, usually to request a particular supervisor + * function. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_svc(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("software interrupt\n"); + rt_hw_show_register(regs); +#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL; + +/** + * This function set the hook, which is invoked on fault exception handling. + * + * @param exception_handle the exception handling hook function. + */ +void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)) +{ + rt_exception_hook = exception_handle; +} + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void rt_hw_show_register(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + if (rt_exception_hook != RT_NULL) + { + rt_err_t result; + + result = rt_exception_hook(regs); + if (result == RT_EOK) return; + } +} + +void (*rt_trap_hook)(struct rt_hw_exp_stack *regs, const char *ex, unsigned int exception_type); + +/** + * This function will set a hook function to trap handler. + * + * @param hook the hook function + */ +void rt_hw_trap_set_hook(void (*hook)(struct rt_hw_exp_stack *regs, const char *ex, unsigned int exception_type)) +{ + rt_trap_hook = hook; +} + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) +{ +#ifdef RT_USING_FPU + { + uint32_t val; + uint32_t addr; + + if (regs->cpsr & (1 << 5)) + { + /* thumb mode */ + addr = regs->pc - 2; + } + else + { + addr = regs->pc - 4; + } + asm volatile ("vmrs %0, fpexc" : "=r"(val)::"memory"); + + if (!(val & 0x40000000)) + { + /* float ins */ + val = (1U << 30); + + asm volatile ("vmsr fpexc, %0"::"r"(val):"memory"); + regs->pc = addr; + return; + } + } +#endif + + if (rt_trap_hook == RT_NULL) + { + rt_kprintf("undefined instruction:\n"); + rt_hw_show_register(regs); +#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) + list_thread(); +#endif + rt_hw_cpu_shutdown(); + } + else + { + rt_trap_hook(regs, "undefined instruction", UND_EXCEPTION); + } +} + +/** + * The software interrupt instruction (SWI) is used for entering + * Supervisor mode, usually to request a particular supervisor + * function. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) +{ + if (rt_trap_hook == RT_NULL) + { + rt_kprintf("software interrupt:\n"); + rt_hw_show_register(regs); +#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) + list_thread(); +#endif + rt_hw_cpu_shutdown(); + } + else + { + rt_trap_hook(regs, "software instruction", SWI_EXCEPTION); + } +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during an instruction prefetch. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) +{ + if (rt_trap_hook == RT_NULL) + { + rt_kprintf("prefetch abort:\n"); + rt_hw_show_register(regs); +#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) + list_thread(); +#endif + rt_hw_cpu_shutdown(); + } + else + { + rt_trap_hook(regs, "prefetch abort", PABT_EXCEPTION); + } +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during a data access. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) +{ + if (rt_trap_hook == RT_NULL) + { + rt_kprintf("data abort:"); + rt_hw_show_register(regs); +#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) + list_thread(); +#endif + rt_hw_cpu_shutdown(); + } + else + { + rt_trap_hook(regs, "data abort", DABT_EXCEPTION); + } +} + +/** + * Normally, system will never reach here + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) +{ + if (rt_trap_hook == RT_NULL) + { + rt_kprintf("reserved trap:\n"); + rt_hw_show_register(regs); +#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS) + list_thread(); +#endif + rt_hw_cpu_shutdown(); + } + else + { + rt_trap_hook(regs, "reserved trap", RESV_EXCEPTION); + } +} + +void rt_hw_trap_irq(void) +{ + void *param; + int int_ack; + int ir; + volatile rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + int_ack = rt_hw_interrupt_get_irq(); + + ir = int_ack & GIC_ACK_INTID_MASK; + if (ir == 1023) + { + /* Spurious interrupt */ + return; + } + +#ifdef SOC_SERIES_R9A07G0 + extern fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES]; + + bsp_common_interrupt_handler((uint32_t)ir); + if (ir < MAX_HANDLERS) + { + /* get interrupt service routine */ + isr_table[ir].handler = (rt_isr_handler_t)g_vector_table[ir]; + isr_table[ir].param = RT_NULL; + } +#endif + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; + +#ifdef RT_USING_INTERRUPT_INFO + isr_table[ir].counter++; +#endif + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[ir].param; + /* turn to interrupt service routine */ + isr_func(ir, param); + } + + /* end of interrupt */ + rt_hw_interrupt_ack(int_ack); +} + +void rt_hw_trap_fiq(void) +{ + void *param; + int ir; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + ir = rt_hw_interrupt_get_irq(); + +#ifdef SOC_SERIES_R9A07G0 + extern fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES]; + + bsp_common_interrupt_handler((uint32_t)ir); + if (ir < MAX_HANDLERS) + { + /* get interrupt service routine */ + isr_table[ir].handler = (rt_isr_handler_t)g_vector_table[ir]; + isr_table[ir].param = RT_NULL; + } +#endif + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; + param = isr_table[ir].param; + + /* turn to interrupt service routine */ + isr_func(ir, param); + + /* end of interrupt */ + rt_hw_interrupt_ack(ir); +} + diff --git a/libcpu/arm/cortex-r52/vector_gcc.S b/libcpu/arm/cortex-r52/vector_gcc.S new file mode 100644 index 00000000000..a0421d535ea --- /dev/null +++ b/libcpu/arm/cortex-r52/vector_gcc.S @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +@------------------------------------------------------------------------------- +@ sys_intvecs.asm +@ +@ (c) Texas Instruments 2009-2013, All rights reserved. +@ + +.section .vectors, "ax" +.code 32 + +@------------------------------------------------------------------------------- +@ import reference for interrupt routines + + .globl Reset_Handler + .globl turnon_VFP + .globl SVC_Handler + .globl Prefetch_Handler + .globl Abort_Handler + .globl Reserved_Handler + .globl IRQ_Handler + .globl FIQ_Handler + + +.globl system_vectors +system_vectors: + b Reset_Handler + b turnon_VFP + b SVC_Handler + b Prefetch_Handler + b Abort_Handler + b Reserved_Handler + b IRQ_Handler + b FIQ_Handler diff --git a/libcpu/arm/cortex-r52/vector_iar.S b/libcpu/arm/cortex-r52/vector_iar.S new file mode 100644 index 00000000000..916e44d6a50 --- /dev/null +++ b/libcpu/arm/cortex-r52/vector_iar.S @@ -0,0 +1,44 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2024-03-11 Wangyuqiang first version +; */ +;@------------------------------------------------------------------------------- +;@ sys_intvecs.asm +;@ +;@ (c) Texas Instruments 2009-2013, All rights reserved. +;@ + + ;SECTION .vectors:"ax" + +;@------------------------------------------------------------------------------- +;@ import reference for interrupt routines + + IMPORT Reset_Handler + IMPORT Undefined_Handler + IMPORT SVC_Handler + IMPORT Prefetch_Handler + IMPORT Abort_Handler + IMPORT Reserved_Handler + IMPORT IRQ_Handler + IMPORT FIQ_Handler + +;/* +; * int system_vectors(void); +; */ + EXPORT system_vectors + SECTION .intvec:CODE:NOROOT(2) +system_vectors: + b Reset_Handler + b Undefined_Handler + b SVC_Handler + b Prefetch_Handler + b Abort_Handler + b Reserved_Handler + b IRQ_Handler + b FIQ_Handler + END diff --git a/libcpu/risc-v/virt64/backtrace.c b/libcpu/risc-v/virt64/backtrace.c index 47c8956936e..47eba3fb942 100644 --- a/libcpu/risc-v/virt64/backtrace.c +++ b/libcpu/risc-v/virt64/backtrace.c @@ -76,7 +76,7 @@ rt_err_t rt_hw_backtrace_frame_unwind(rt_thread_t thread, struct rt_hw_backtrace { void *lwp = thread->lwp; void *this_lwp = lwp_self(); - if (this_lwp == lwp && rt_hw_mmu_v2p(lwp, fp) != ARCH_MAP_FAILED) + if (this_lwp == lwp && rt_hw_mmu_v2p(((rt_lwp_t)lwp)->aspace, fp) != ARCH_MAP_FAILED) { rc = _bt_kaddr(fp, frame); } diff --git a/src/Kconfig b/src/Kconfig index 2b9fcdd789a..849ce5fa3b8 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -25,7 +25,6 @@ config RT_USING_SMART select RT_USING_DFS select RT_USING_POSIX_CLOCKTIME select RT_USING_DEVICE - select RT_USING_TTY select RT_USING_NULL select RT_USING_ZERO select RT_USING_RANDOM diff --git a/src/SConscript b/src/SConscript index f8dc5248ca3..9e84a4c91a2 100644 --- a/src/SConscript +++ b/src/SConscript @@ -30,6 +30,7 @@ else: SrcRemove(src, ['scheduler_up.c']) LOCAL_CFLAGS = '' +LINKFLAGS = '' if rtconfig.PLATFORM in ['gcc']: # only for GCC LOCAL_CFLAGS += ' -Wunused' # unused warning @@ -41,7 +42,11 @@ if rtconfig.PLATFORM in ['gcc']: # only for GCC if 'mips' not in rtconfig.PREFIX: # mips toolchain does not support LOCAL_CFLAGS += ' -Wimplicit-fallthrough' # implicit fallthrough warning LOCAL_CFLAGS += ' -Wduplicated-cond -Wduplicated-branches' # duplicated condition warning + if rtconfig.ARCH not in ['sim']: + LINKFLAGS += ' -Wl,--gc-sections,--print-memory-usage' # remove unused sections and print memory usage -group = DefineGroup('Kernel', src, depend=[''], CPPPATH=inc, CPPDEFINES=['__RTTHREAD__'], LOCAL_CFLAGS=LOCAL_CFLAGS, LOCAL_CPPDEFINES=['__RT_KERNEL_SOURCE__']) +group = DefineGroup('Kernel', src, depend=[''], CPPPATH=inc, + LINKFLAGS=LINKFLAGS, LOCAL_CFLAGS=LOCAL_CFLAGS, + CPPDEFINES=['__RTTHREAD__'], LOCAL_CPPDEFINES=['__RT_KERNEL_SOURCE__']) Return('group') diff --git a/src/ipc.c b/src/ipc.c index 33b9cfe4200..5ffcf017c2c 100644 --- a/src/ipc.c +++ b/src/ipc.c @@ -598,7 +598,7 @@ static rt_err_t _rt_sem_take(rt_sem_t sem, rt_int32_t timeout, int suspend_flag) thread = rt_thread_self(); /* reset thread error number */ - thread->error = -RT_EINTR; + thread->error = RT_EINTR; LOG_D("sem take: suspend thread - %s", thread->parent.name); diff --git a/src/kservice.c b/src/kservice.c index fc6dbab0b55..7c0cb0b58c1 100644 --- a/src/kservice.c +++ b/src/kservice.c @@ -47,7 +47,6 @@ #ifdef RT_USING_SMART #include #include -#include #endif /** @@ -283,27 +282,6 @@ RTM_EXPORT(rt_console_get_device); */ rt_device_t rt_console_set_device(const char *name) { -#ifdef RT_USING_SMART - rt_device_t new_iodev = RT_NULL, old_iodev = RT_NULL; - - /* find new console device */ - new_iodev = rt_device_find(name); - if (new_iodev != RT_NULL) - { - if (_console_device != RT_NULL) - { - old_iodev = console_set_iodev(new_iodev); - } - else - { - console_register("console", new_iodev); - _console_device = rt_device_find("console"); - rt_device_open(_console_device, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_STREAM); - } - } - - return old_iodev; -#else rt_device_t new_device, old_device; /* save old device */ @@ -329,7 +307,6 @@ rt_device_t rt_console_set_device(const char *name) } return old_device; -#endif } RTM_EXPORT(rt_console_set_device); #endif /* RT_USING_DEVICE */ diff --git a/src/mem.c b/src/mem.c index d0bfca9a9a9..644eeb268c3 100644 --- a/src/mem.c +++ b/src/mem.c @@ -59,9 +59,6 @@ struct rt_small_mem_item { rt_ubase_t pool_ptr; /**< small memory object addr */ -#ifdef ARCH_CPU_64BIT - rt_uint32_t resv; -#endif /* ARCH_CPU_64BIT */ rt_size_t next; /**< next free item */ rt_size_t prev; /**< prev free item */ #ifdef RT_USING_MEMTRACE @@ -85,18 +82,12 @@ struct rt_small_mem rt_size_t mem_size_aligned; /**< aligned memory size */ }; -#define HEAP_MAGIC 0x1ea0 - -#ifdef ARCH_CPU_64BIT -#define MIN_SIZE 24 -#else -#define MIN_SIZE 12 -#endif /* ARCH_CPU_64BIT */ +#define MIN_SIZE (sizeof(rt_ubase_t) + sizeof(rt_size_t) + sizeof(rt_size_t)) #define MEM_MASK ((~(rt_size_t)0) - 1) -#define MEM_USED() ((((rt_base_t)(small_mem)) & MEM_MASK) | 0x1) -#define MEM_FREED() ((((rt_base_t)(small_mem)) & MEM_MASK) | 0x0) +#define MEM_USED(_mem) ((((rt_base_t)(_mem)) & MEM_MASK) | 0x1) +#define MEM_FREED(_mem) ((((rt_base_t)(_mem)) & MEM_MASK) | 0x0) #define MEM_ISUSED(_mem) \ (((rt_base_t)(((struct rt_small_mem_item *)(_mem))->pool_ptr)) & (~MEM_MASK)) #define MEM_POOL(_mem) \ @@ -220,7 +211,7 @@ rt_smem_t rt_smem_init(const char *name, /* initialize the start of the heap */ mem = (struct rt_small_mem_item *)small_mem->heap_ptr; - mem->pool_ptr = MEM_FREED(); + mem->pool_ptr = MEM_FREED(small_mem); mem->next = small_mem->mem_size_aligned + SIZEOF_STRUCT_MEM; mem->prev = 0; #ifdef RT_USING_MEMTRACE @@ -229,7 +220,7 @@ rt_smem_t rt_smem_init(const char *name, /* initialize the end of the heap */ small_mem->heap_end = (struct rt_small_mem_item *)&small_mem->heap_ptr[mem->next]; - small_mem->heap_end->pool_ptr = MEM_USED(); + small_mem->heap_end->pool_ptr = MEM_USED(small_mem); small_mem->heap_end->next = small_mem->mem_size_aligned + SIZEOF_STRUCT_MEM; small_mem->heap_end->prev = small_mem->mem_size_aligned + SIZEOF_STRUCT_MEM; #ifdef RT_USING_MEMTRACE @@ -333,7 +324,7 @@ void *rt_smem_alloc(rt_smem_t m, rt_size_t size) /* create mem2 struct */ mem2 = (struct rt_small_mem_item *)&small_mem->heap_ptr[ptr2]; - mem2->pool_ptr = MEM_FREED(); + mem2->pool_ptr = MEM_FREED(small_mem); mem2->next = mem->next; mem2->prev = ptr; #ifdef RT_USING_MEMTRACE @@ -365,7 +356,7 @@ void *rt_smem_alloc(rt_smem_t m, rt_size_t size) small_mem->parent.max = small_mem->parent.used; } /* set small memory object */ - mem->pool_ptr = MEM_USED(); + mem->pool_ptr = MEM_USED(small_mem); #ifdef RT_USING_MEMTRACE if (rt_thread_self()) rt_smem_setname(mem, rt_thread_self()->parent.name); @@ -462,7 +453,7 @@ void *rt_smem_realloc(rt_smem_t m, void *rmem, rt_size_t newsize) ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize; mem2 = (struct rt_small_mem_item *)&small_mem->heap_ptr[ptr2]; - mem2->pool_ptr = MEM_FREED(); + mem2->pool_ptr = MEM_FREED(small_mem); mem2->next = mem->next; mem2->prev = ptr; #ifdef RT_USING_MEMTRACE @@ -530,7 +521,7 @@ void rt_smem_free(void *rmem) (rt_ubase_t)(mem->next - ((rt_uint8_t *)mem - small_mem->heap_ptr))); /* ... and is now unused. */ - mem->pool_ptr = MEM_FREED(); + mem->pool_ptr = MEM_FREED(small_mem); #ifdef RT_USING_MEMTRACE rt_smem_setname(mem, " "); #endif /* RT_USING_MEMTRACE */ diff --git a/src/object.c b/src/object.c index 66a7826681c..bdb69364ce3 100644 --- a/src/object.c +++ b/src/object.c @@ -15,6 +15,7 @@ * 2018-01-25 Bernard Fix the object find issue when enable MODULE. * 2022-01-07 Gabriel Moving __on_rt_xxxxx_hook to object.c * 2023-09-15 xqyjlj perf rt_hw_interrupt_disable/enable + * 2023-11-17 xqyjlj add process group and session support */ #include @@ -74,6 +75,8 @@ enum rt_object_info_type #endif #ifdef RT_USING_SMART RT_Object_Info_Channel, /**< The object is a IPC channel */ + RT_Object_Info_ProcessGroup, /**< The object is a process group */ + RT_Object_Info_Session, /**< The object is a session */ #endif #ifdef RT_USING_HEAP RT_Object_Info_Custom, /**< The object is a custom object */ @@ -133,6 +136,10 @@ static struct rt_object_information _object_container[RT_Object_Info_Unknown] = #ifdef RT_USING_SMART /* initialize object container - module */ {RT_Object_Class_Channel, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_Channel), sizeof(struct rt_channel), RT_SPINLOCK_INIT}, + {RT_Object_Class_ProcessGroup, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_ProcessGroup), sizeof(struct rt_processgroup), RT_SPINLOCK_INIT}, + {RT_Object_Class_Session, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_Session), sizeof(struct rt_session), RT_SPINLOCK_INIT}, +#endif +#ifdef RT_USING_HEAP {RT_Object_Class_Custom, _OBJ_CONTAINER_LIST_INIT(RT_Object_Info_Custom), sizeof(struct rt_custom_object), RT_SPINLOCK_INIT}, #endif }; @@ -469,7 +476,7 @@ rt_object_t rt_object_allocate(enum rt_object_class_type type, const char *name) object->flag = 0; #if RT_NAME_MAX > 0 - rt_strncpy(object->name, name, RT_NAME_MAX); /* copy name */ + rt_strncpy(object->name, name, RT_NAME_MAX - 1); /* copy name */ #else object->name = name; #endif /* RT_NAME_MAX > 0 */ diff --git a/src/scheduler_up.c b/src/scheduler_up.c index 44da38d8ffa..289a30a58f2 100644 --- a/src/scheduler_up.c +++ b/src/scheduler_up.c @@ -486,7 +486,7 @@ void rt_exit_critical_safe(rt_base_t critical_level) void rt_exit_critical_safe(rt_base_t critical_level) { - return rt_exit_critical(); + rt_exit_critical(); } #endif diff --git a/src/signal.c b/src/signal.c index 77379b1a31d..28d0fd1c9f1 100644 --- a/src/signal.c +++ b/src/signal.c @@ -19,7 +19,11 @@ #ifdef RT_USING_SIGNALS #ifndef RT_SIG_INFO_MAX -#define RT_SIG_INFO_MAX 32 + #ifdef ARCH_CPU_64BIT + #define RT_SIG_INFO_MAX 64 + #else + #define RT_SIG_INFO_MAX 32 + #endif /* ARCH_CPU_64BIT */ #endif /* RT_SIG_INFO_MAX */ #define DBG_TAG "SIGN" @@ -647,6 +651,7 @@ int rt_thread_kill(rt_thread_t tid, int sig) else { LOG_E("The allocation of signal info node failed."); + return -RT_EEMPTY; } /* deliver signal to this thread */ diff --git a/src/thread.c b/src/thread.c index d220d490e2e..1b489cf76f2 100644 --- a/src/thread.c +++ b/src/thread.c @@ -343,6 +343,7 @@ rt_err_t rt_thread_init(struct rt_thread *thread, /* parameter check */ RT_ASSERT(thread != RT_NULL); RT_ASSERT(stack_start != RT_NULL); + RT_ASSERT(tick != 0); /* initialize thread object */ rt_object_init((rt_object_t)thread, RT_Object_Class_Thread, name); @@ -512,6 +513,9 @@ rt_thread_t rt_thread_create(const char *name, rt_uint8_t priority, rt_uint32_t tick) { + /* parameter check */ + RT_ASSERT(tick != 0); + struct rt_thread *thread; void *stack_start; diff --git a/src/timer.c b/src/timer.c index 83850e5f47f..4d7b352d605 100644 --- a/src/timer.c +++ b/src/timer.c @@ -402,6 +402,11 @@ static rt_err_t _timer_start(rt_list_t *timer_list, rt_timer_t timer) unsigned int tst_nr; static unsigned int random_nr; + if (timer->parent.flag & RT_TIMER_FLAG_PROCESSING) + { + return -RT_ERROR; + } + /* remove timer from list */ _timer_remove(timer); /* change status of timer */ @@ -599,6 +604,11 @@ rt_err_t rt_timer_control(rt_timer_t timer, int cmd, void *arg) case RT_TIMER_CTRL_SET_TIME: RT_ASSERT((*(rt_tick_t *)arg) < RT_TICK_MAX / 2); + if (timer->parent.flag & RT_TIMER_FLAG_ACTIVATED) + { + _timer_remove(timer); + timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; + } timer->init_tick = *(rt_tick_t *)arg; break; @@ -702,6 +712,8 @@ void rt_timer_check(void) { t->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; } + + t->parent.flag |= RT_TIMER_FLAG_PROCESSING; /* add timer to temporary list */ rt_list_insert_after(&list, &(t->row[RT_TIMER_SKIP_LIST_LEVEL - 1])); rt_spin_unlock_irqrestore(&_htimer_lock, level); @@ -714,6 +726,9 @@ void rt_timer_check(void) RT_OBJECT_HOOK_CALL(rt_timer_exit_hook, (t)); LOG_D("current tick: %d", current_tick); level = rt_spin_lock_irqsave(&_htimer_lock); + + t->parent.flag &= ~RT_TIMER_FLAG_PROCESSING; + /* Check whether the timer object is detached or started again */ if (rt_list_isempty(&list)) { @@ -788,6 +803,8 @@ static void _soft_timer_check(void) { t->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; } + + t->parent.flag |= RT_TIMER_FLAG_PROCESSING; /* add timer to temporary list */ rt_list_insert_after(&list, &(t->row[RT_TIMER_SKIP_LIST_LEVEL - 1])); @@ -801,6 +818,8 @@ static void _soft_timer_check(void) level = rt_spin_lock_irqsave(&_stimer_lock); + t->parent.flag &= ~RT_TIMER_FLAG_PROCESSING; + /* Check whether the timer object is detached or started again */ if (rt_list_isempty(&list)) { diff --git a/tools/ci/cpp_check.py b/tools/ci/cpp_check.py index 018f86fda4b..e7b2847c4a5 100644 --- a/tools/ci/cpp_check.py +++ b/tools/ci/cpp_check.py @@ -23,7 +23,24 @@ def check(self): logging.info("Start to static code analysis.") check_result = True for file in file_list_filtered: - result = subprocess.run(['cppcheck', '-DRTM_EXPORT', '-DMSH_CMD_EXPORT(a,b)=', '--enable=warning', 'performance', 'portability', '--inline-suppr', '--error-exitcode=1', '--force', file], stdout = subprocess.PIPE, stderr = subprocess.PIPE) + result = subprocess.run( + [ + 'cppcheck', + '-DRT_ASSERT(x)=', + '-Drt_list_for_each_entry(a,b,c)=a=(void*)b;', + '-I include', + '-I thread/components/finsh', + # it's okay because CI will do the real compilation to check this + '--suppress=syntaxError', + '--enable=warning', + 'performance', + 'portability', + '--inline-suppr', + '--error-exitcode=1', + '--force', + file + ], + stdout = subprocess.PIPE, stderr = subprocess.PIPE) logging.info(result.stdout.decode()) logging.info(result.stderr.decode()) if result.stderr: diff --git a/tools/ci/file_check.py b/tools/ci/file_check.py index ea9052d2401..597c8c33b05 100644 --- a/tools/ci/file_check.py +++ b/tools/ci/file_check.py @@ -121,7 +121,7 @@ def __init__(self, file_list): self.file_list = file_list def __check_rt_errorcode(self, line): - pattern = re.compile(r'return\s+(RT_ERROR|RT_ETIMEOUT|RT_EFULL|RT_EEMPTY|RT_ENOMEM|RT_ENOSYS|RT_EBUSY|RT_EIO|RT_EINTR|RT_EINVAL|RT_ENOENT|RT_ENOSPC|RT_EPERM|RT_ETRAP|RT_EFAULT)') + pattern = re.compile(r'return\s+(RT_ERROR|RT_ETIMEOUT|RT_EFULL|RT_EEMPTY|RT_ENOMEM|RT_ENOSYS|RT_EBUSY|RT_EIO|RT_EINTR|RT_EINVAL|RT_ENOENT|RT_ENOSPC|RT_EPERM|RT_ETRAP|RT_EFAULT)') match = pattern.search(line) if match: return False @@ -163,14 +163,16 @@ def check(self): with open(file_path, 'rb') as f: file = f.read() # get file encoding - code = chardet.detect(file)['encoding'] + chardet_report = chardet.detect(file) + code = chardet_report['encoding'] + confidence = chardet_report['confidence'] except Exception as e: logging.error(e) else: continue - if code != 'utf-8' and code != 'ascii': - logging.error("[{0}]: encoding not utf-8, please format it.".format(file_path)) + if code != 'utf-8' and code != 'ascii' and confidence > 0.8: + logging.error("[{0}]: encoding {1} not utf-8, please format it.".format(file_path, code)) encoding_check_result = False else: logging.info('[{0}]: encoding check success.'.format(file_path))